From e10b058e5501646d7ca71e1bc88f998280a14d8b Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Tue, 26 Dec 2017 08:40:38 +0200 Subject: [PATCH 01/48] turn off debug messages by defualt --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index f7cbfa5..3cb0bed 100644 --- a/Makefile +++ b/Makefile @@ -67,7 +67,7 @@ CONFIG_WIFI_MONITOR = n CONFIG_MCC_MODE = n CONFIG_APPEND_VENDOR_IE_ENABLE = n ########################## Debug ########################### -CONFIG_RTW_DEBUG = y +CONFIG_RTW_DEBUG = n # default log level is _DRV_INFO_ = 4, # please refer to "How_to_set_driver_debug_log_level.doc" to set the available level. CONFIG_RTW_LOG_LEVEL = 4 From 493a10e30be6baf304d2a22f49acf8fed0329df5 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Tue, 26 Dec 2017 08:46:16 +0200 Subject: [PATCH 02/48] Fix compilation against kernel version 4.12 --- include/osdep_service_linux.h | 3 +++ os_dep/linux/ioctl_cfg80211.c | 36 +++++++++++++++++++++++++++++++++-- 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/include/osdep_service_linux.h b/include/osdep_service_linux.h index 1943a69..e3f7a6c 100644 --- a/include/osdep_service_linux.h +++ b/include/osdep_service_linux.h @@ -46,6 +46,9 @@ #endif #include #include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) + #include +#endif #include #include #include diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index c7f5199..2dd125e 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -23,6 +23,12 @@ #ifdef CONFIG_IOCTL_CFG80211 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) + #if !defined(WIPHY_FLAG_SUPPORTS_SCHED_SCAN) + #define WIPHY_FLAG_SUPPORTS_SCHED_SCAN BIT(12) + #endif +#endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) #define STATION_INFO_SIGNAL BIT(NL80211_STA_INFO_SIGNAL) #define STATION_INFO_TX_BITRATE BIT(NL80211_STA_INFO_TX_BITRATE) @@ -748,6 +754,17 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) { #endif RTW_INFO(FUNC_ADPT_FMT" call cfg80211_roamed\n", FUNC_ADPT_ARG(padapter)); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) + struct cfg80211_roam_info roam_info = { + .channel = notify_channel, + .bssid = cur_network->network.MacAddress, + .req_ie = pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2, + .req_ie_len = pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2, + .resp_ie = pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6, + .resp_ie_len = pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 + }; + cfg80211_roamed(padapter->pnetdev,&roam_info, GFP_ATOMIC); +#else cfg80211_roamed(padapter->pnetdev #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) , notify_channel @@ -758,6 +775,7 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) { , pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 , GFP_ATOMIC); +#endif } else { #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state); @@ -1721,7 +1739,11 @@ enum nl80211_iftype { #endif static int cfg80211_rtw_change_iface(struct wiphy *wiphy, struct net_device *ndev, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)) + enum nl80211_iftype type, +#else enum nl80211_iftype type, u32 *flags, +#endif struct vif_params *params) { enum nl80211_iftype old_type; NDIS_802_11_NETWORK_INFRASTRUCTURE networkType; @@ -3595,7 +3617,12 @@ static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct ne mon_ndev->type = ARPHRD_IEEE80211_RADIOTAP; strncpy(mon_ndev->name, name, IFNAMSIZ); mon_ndev->name[IFNAMSIZ - 1] = 0; - mon_ndev->destructor = rtw_ndev_destructor; +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(4,11,9)) + mon_ndev->needs_free_netdev = true; + mon_ndev->priv_destructor = rtw_ndev_destructor; +#else + mon_ndev->destructor = rtw_ndev_destructor; +#endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) mon_ndev->netdev_ops = &rtw_cfg80211_monitor_if_ops; @@ -3661,7 +3688,12 @@ cfg80211_rtw_add_virtual_intf( #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) unsigned char name_assign_type, #endif - enum nl80211_iftype type, u32 *flags, struct vif_params *params) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)) + enum nl80211_iftype type, struct vif_params *params) +#else + enum nl80211_iftype type, u32 *flags, struct vif_params *params) +#endif + { int ret = 0; struct net_device *ndev = NULL; _adapter *padapter = wiphy_to_adapter(wiphy); From ee02ca91bce7ff22989e2aa6366a956423f236a7 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Tue, 26 Dec 2017 08:50:36 +0200 Subject: [PATCH 03/48] fix unexported __vfs_read & vfs_read in kernel 4.14 --- core/efuse/rtw_efuse.c | 25 ++++++++++++++++++++----- core/rtw_wlan_util.c | 6 +++++- os_dep/osdep_service.c | 4 ++++ 3 files changed, 29 insertions(+), 6 deletions(-) diff --git a/core/efuse/rtw_efuse.c b/core/efuse/rtw_efuse.c index 4efa64d..579b805 100644 --- a/core/efuse/rtw_efuse.c +++ b/core/efuse/rtw_efuse.c @@ -2564,7 +2564,11 @@ u32 rtw_read_efuse_from_file(const char *path, u8 *buf) set_fs(KERNEL_DS); for (i = 0 ; i < HWSET_MAX_SIZE ; i++) { - vfs_read(fp, temp, 2, &pos); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + kernel_read(fp, temp, 2, &pos); + #else + vfs_read(fp, temp, 2, &pos); + #endif if (sscanf(temp, "%hhx", &buf[i]) != 1) { if (0) RTW_ERR("%s sscanf fail\n", __func__); @@ -2572,10 +2576,18 @@ u32 rtw_read_efuse_from_file(const char *path, u8 *buf) } if ((i % EFUSE_FILE_COLUMN_NUM) == (EFUSE_FILE_COLUMN_NUM - 1)) { /* Filter the lates space char. */ - vfs_read(fp, temp, 1, &pos); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + kernel_read(fp, temp, 1, &pos); + #else + vfs_read(fp, temp, 1, &pos); + #endif if (strchr(temp, ' ') == NULL) { pos--; - vfs_read(fp, temp, 2, &pos); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + kernel_read(fp, temp, 2, &pos); + #else + vfs_read(fp, temp, 2, &pos); + #endif } } else { pos += 1; /* Filter the space character */ @@ -2631,8 +2643,11 @@ u32 rtw_read_macaddr_from_file(const char *path, u8 *buf) fs = get_fs(); set_fs(KERNEL_DS); - - vfs_read(fp, source_addr, 18, &pos); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + kernel_read(fp, source_addr, 18, &pos); + #else + vfs_read(fp, source_addr, 18, &pos); + #endif source_addr[17] = ':'; head = end = source_addr; diff --git a/core/rtw_wlan_util.c b/core/rtw_wlan_util.c index a9b4a6f..71f55f4 100644 --- a/core/rtw_wlan_util.c +++ b/core/rtw_wlan_util.c @@ -4724,7 +4724,11 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid, source = rtw_zmalloc(2048); if (source != NULL) { - len = vfs_read(fp, source, len, &pos); + #if(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + len = kernel_read(fp, source, len, &pos); + #else + len = vfs_read(fp, source, len, &pos); + #endif rtw_parse_cipher_list(nlo_info, source); rtw_mfree(source, 2048); } diff --git a/os_dep/osdep_service.c b/os_dep/osdep_service.c index 6dd6341..9df4be6 100644 --- a/os_dep/osdep_service.c +++ b/os_dep/osdep_service.c @@ -1961,7 +1961,11 @@ static int readFile(struct file *fp, char *buf, int len) while (sum < len) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + rlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos); +#else rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos); +#endif #else rlen = fp->f_op->read(fp, buf + sum, len - sum, &fp->f_pos); #endif From b542c8075cb92576a8bc6a480ec88325af125a48 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Tue, 26 Dec 2017 09:04:05 +0200 Subject: [PATCH 04/48] revert debug change but chnage debug level to 0 --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 3cb0bed..8c12423 100644 --- a/Makefile +++ b/Makefile @@ -67,10 +67,10 @@ CONFIG_WIFI_MONITOR = n CONFIG_MCC_MODE = n CONFIG_APPEND_VENDOR_IE_ENABLE = n ########################## Debug ########################### -CONFIG_RTW_DEBUG = n +CONFIG_RTW_DEBUG = y # default log level is _DRV_INFO_ = 4, # please refer to "How_to_set_driver_debug_log_level.doc" to set the available level. -CONFIG_RTW_LOG_LEVEL = 4 +CONFIG_RTW_LOG_LEVEL = 0 ######################## Wake On Lan ########################## CONFIG_WOWLAN = n CONFIG_GPIO_WAKEUP = n From e4759ec1e28cb02628be5e95be59f60e361b6557 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Thu, 11 Jan 2018 13:53:48 +0200 Subject: [PATCH 05/48] update usb_intf.c --- os_dep/linux/usb_intf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/os_dep/linux/usb_intf.c b/os_dep/linux/usb_intf.c index 260d0f0..5f66e34 100644 --- a/os_dep/linux/usb_intf.c +++ b/os_dep/linux/usb_intf.c @@ -220,6 +220,7 @@ static struct usb_device_id rtw_usb_id_tbl[] = { #ifdef CONFIG_RTL8822B /*=== Realtek demoboard ===*/ + {USB_DEVICE(0x0BDA, 0xB812), .driver_info = RTL8822B}, {USB_DEVICE(0x0B05, 0x1812), .driver_info = RTL8812}, /* ASUS - Edimax */ {USB_DEVICE(0x7392, 0xB822), .driver_info = RTL8822B}, /* Edimax - EW-7822ULC */ {USB_DEVICE(0x0b05, 0x184c), .driver_info = RTL8822B}, /* ASUS USB AC53 */ From c878e75f0d05600cfad174fb88d017d7f4c7e828 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Thu, 8 Feb 2018 20:21:01 +0200 Subject: [PATCH 06/48] update to latest driver available from EDIMAX --- Makefile | 969 +- core/efuse/rtw_efuse.c | 1397 +- core/rtw_ap.c | 470 +- core/rtw_beamforming.c | 2326 +- core/rtw_br_ext.c | 10 +- core/rtw_bt_mp.c | 37 +- core/rtw_btcoex.c | 87 +- core/rtw_cmd.c | 1095 +- core/rtw_debug.c | 1630 +- core/rtw_eeprom.c | 56 +- core/rtw_ieee80211.c | 116 +- core/rtw_io.c | 47 +- core/rtw_ioctl_query.c | 21 +- core/rtw_ioctl_rtl.c | 27 +- core/rtw_ioctl_set.c | 220 +- core/rtw_iol.c | 9 +- core/rtw_mem.c | 39 +- core/rtw_mi.c | 431 +- core/rtw_mlme.c | 607 +- core/rtw_mlme_ext.c | 2680 +- core/rtw_mp.c | 760 +- core/rtw_mp_ioctl.c | 423 +- core/rtw_odm.c | 446 +- core/rtw_p2p.c | 463 +- core/rtw_pwrctrl.c | 381 +- core/rtw_recv.c | 424 +- core/rtw_rf.c | 1698 +- core/rtw_sdio.c | 69 +- core/rtw_security.c | 132 +- core/rtw_sreset.c | 13 +- core/rtw_sta_mgt.c | 336 +- core/rtw_tdls.c | 93 +- core/rtw_vht.c | 174 +- core/rtw_wapi.c | 21 +- core/rtw_wapi_sms4.c | 14 + core/rtw_wlan_util.c | 905 +- core/rtw_xmit.c | 753 +- hal/HalPwrSeqCmd.c | 25 +- hal/btc/halbtc8723d1ant.c | 4273 ++- hal/btc/halbtc8723d1ant.h | 139 +- hal/btc/halbtc8723d2ant.c | 4287 ++- hal/btc/halbtc8723d2ant.h | 134 +- hal/efuse/efuse_mask.h | 178 +- hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.c | 34 +- hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.h | 31 +- hal/efuse/rtl8822b/HalEfuseMask8822B_USB.c | 42 +- hal/efuse/rtl8822b/HalEfuseMask8822B_USB.h | 31 +- hal/hal_btcoex.c | 1058 +- hal/hal_com.c | 3734 ++- hal/hal_com_c2h.h | 80 +- hal/hal_com_phycfg.c | 6377 ++-- hal/hal_dm.c | 335 +- hal/hal_dm.h | 10 +- hal/hal_halmac.c | 1427 +- hal/hal_halmac.h | 67 +- hal/hal_hci/hal_usb.c | 75 +- hal/hal_intf.c | 815 +- hal/hal_mcc.c | 687 +- hal/hal_mp.c | 1482 +- hal/hal_phy.c | 15 +- hal/halmac/halmac_2_platform.h | 13 +- .../halmac_8822b/halmac_8822b_cfg.h | 122 +- .../halmac_8822b/halmac_8822b_pwr_seq.c | 292 +- .../halmac_8822b/halmac_8822b_pwr_seq.h | 244 +- .../halmac_8822b/halmac_api_8822b.c | 125 +- .../halmac_8822b/halmac_api_8822b.h | 20 + .../halmac_8822b/halmac_api_8822b_pcie.c | 261 +- .../halmac_8822b/halmac_api_8822b_pcie.h | 41 + .../halmac_8822b/halmac_api_8822b_sdio.c | 236 +- .../halmac_8822b/halmac_api_8822b_sdio.h | 28 + .../halmac_8822b/halmac_api_8822b_usb.c | 152 +- .../halmac_8822b/halmac_api_8822b_usb.h | 30 + .../halmac_8822b/halmac_func_8822b.c | 518 +- .../halmac_8822b/halmac_func_8822b.h | 15 + hal/halmac/halmac_88xx/halmac_88xx_cfg.h | 69 +- hal/halmac/halmac_88xx/halmac_api_88xx.c | 3907 ++- hal/halmac/halmac_88xx/halmac_api_88xx.h | 207 +- hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c | 138 +- hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h | 15 + hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c | 571 +- hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h | 49 + hal/halmac/halmac_88xx/halmac_api_88xx_usb.c | 187 +- hal/halmac/halmac_88xx/halmac_api_88xx_usb.h | 15 + hal/halmac/halmac_88xx/halmac_func_88xx.c | 2227 +- hal/halmac/halmac_88xx/halmac_func_88xx.h | 163 +- hal/halmac/halmac_api.c | 383 +- hal/halmac/halmac_api.h | 45 +- hal/halmac/halmac_bit2.h | 3885 ++- hal/halmac/halmac_bit_8821c.h | 2087 +- hal/halmac/halmac_bit_8822b.h | 1276 +- hal/halmac/halmac_fw_info.h | 19 +- hal/halmac/halmac_fw_offload_c2h_ap.h | 52 + hal/halmac/halmac_fw_offload_c2h_nic.h | 45 + hal/halmac/halmac_fw_offload_h2c_ap.h | 186 +- hal/halmac/halmac_fw_offload_h2c_nic.h | 121 + hal/halmac/halmac_h2c_extra_info_ap.h | 15 + hal/halmac/halmac_h2c_extra_info_nic.h | 15 + hal/halmac/halmac_hw_cfg.h | 162 +- hal/halmac/halmac_original_c2h_ap.h | 15 + hal/halmac/halmac_original_c2h_nic.h | 15 + hal/halmac/halmac_original_h2c_ap.h | 269 +- hal/halmac/halmac_original_h2c_nic.h | 183 +- hal/halmac/halmac_pcie_reg.h | 26 +- hal/halmac/halmac_pwr_seq_cmd.h | 21 +- hal/halmac/halmac_reg2.h | 723 +- hal/halmac/halmac_reg_8821c.h | 60 +- hal/halmac/halmac_reg_8822b.h | 30 + hal/halmac/halmac_rx_bd_ap.h | 15 + hal/halmac/halmac_rx_bd_chip.h | 15 + hal/halmac/halmac_rx_bd_nic.h | 15 + hal/halmac/halmac_rx_desc_ap.h | 39 + hal/halmac/halmac_rx_desc_chip.h | 22 + hal/halmac/halmac_rx_desc_nic.h | 39 + hal/halmac/halmac_sdio_reg.h | 49 +- hal/halmac/halmac_tx_bd_ap.h | 15 + hal/halmac/halmac_tx_bd_chip.h | 15 + hal/halmac/halmac_tx_bd_nic.h | 15 + hal/halmac/halmac_tx_desc_ap.h | 15 + hal/halmac/halmac_tx_desc_chip.h | 15 + hal/halmac/halmac_tx_desc_nic.h | 15 + hal/halmac/halmac_type.h | 651 +- hal/halmac/halmac_usb_reg.h | 15 + hal/led/hal_usb_led.c | 125 +- hal/phydm/halhwimg.h | 220 +- hal/phydm/mp_precomp.h | 12 +- hal/phydm/phydm.c | 5305 +-- hal/phydm/phydm.h | 2018 +- hal/phydm/phydm_acs.c | 1395 +- hal/phydm/phydm_acs.h | 122 +- hal/phydm/phydm_adaptivity.c | 1487 +- hal/phydm/phydm_adaptivity.h | 296 +- hal/phydm/phydm_adc_sampling.c | 977 +- hal/phydm/phydm_adc_sampling.h | 210 +- hal/phydm/phydm_antdect.c | 1500 +- hal/phydm/phydm_antdect.h | 100 +- hal/phydm/phydm_antdiv.c | 9251 +++--- hal/phydm/phydm_antdiv.h | 837 +- hal/phydm/phydm_beamforming.c | 2614 +- hal/phydm/phydm_beamforming.h | 616 +- hal/phydm/phydm_ccx.c | 640 +- hal/phydm/phydm_ccx.h | 149 +- hal/phydm/phydm_cfotracking.c | 536 +- hal/phydm/phydm_cfotracking.h | 82 +- hal/phydm/phydm_debug.c | 3487 +- hal/phydm/phydm_debug.h | 482 +- hal/phydm/phydm_dfs.c | 273 +- hal/phydm/phydm_dfs.h | 48 +- hal/phydm/phydm_dig.c | 3156 +- hal/phydm/phydm_dig.h | 492 +- hal/phydm/phydm_dynamicbbpowersaving.c | 159 +- hal/phydm/phydm_dynamicbbpowersaving.h | 57 +- hal/phydm/phydm_dynamictxpower.c | 666 +- hal/phydm/phydm_dynamictxpower.h | 141 +- hal/phydm/phydm_features.h | 176 +- hal/phydm/phydm_hwconfig.c | 5043 +-- hal/phydm/phydm_hwconfig.h | 813 +- hal/phydm/phydm_interface.c | 1705 +- hal/phydm/phydm_interface.h | 687 +- hal/phydm/phydm_noisemonitor.c | 426 +- hal/phydm/phydm_noisemonitor.h | 47 +- hal/phydm/phydm_pathdiv.c | 1142 +- hal/phydm/phydm_pathdiv.h | 526 +- hal/phydm/phydm_pre_define.h | 760 +- hal/phydm/phydm_precomp.h | 569 +- hal/phydm/phydm_rainfo.c | 4259 +-- hal/phydm/phydm_rainfo.h | 651 +- hal/phydm/phydm_reg.h | 225 +- hal/phydm/phydm_regdefine11ac.h | 46 +- hal/phydm/phydm_regdefine11n.h | 51 +- hal/phydm/phydm_types.h | 278 +- hal/phydm/rtl8822b/halhwimg8822b_bb.c | 6386 +++- hal/phydm/rtl8822b/halhwimg8822b_bb.h | 57 +- hal/phydm/rtl8822b/halhwimg8822b_fw.c | 26739 ++++++++-------- hal/phydm/rtl8822b/halhwimg8822b_fw.h | 79 +- hal/phydm/rtl8822b/halhwimg8822b_mac.c | 249 +- hal/phydm/rtl8822b/halhwimg8822b_mac.h | 41 +- hal/phydm/rtl8822b/halhwimg8822b_rf.c | 8944 +++++- hal/phydm/rtl8822b/halhwimg8822b_rf.h | 211 +- hal/phydm/rtl8822b/phydm_hal_api8822b.c | 2128 +- hal/phydm/rtl8822b/phydm_hal_api8822b.h | 168 +- hal/phydm/rtl8822b/phydm_regconfig8822b.c | 381 +- hal/phydm/rtl8822b/phydm_regconfig8822b.h | 127 +- hal/phydm/rtl8822b/phydm_rtl8822b.c | 399 +- hal/phydm/rtl8822b/phydm_rtl8822b.h | 13 +- hal/phydm/rtl8822b/version_rtl8822b.h | 4 +- hal/phydm/txbf/halcomtxbf.c | 672 +- hal/phydm/txbf/halcomtxbf.h | 236 +- hal/phydm/txbf/haltxbf8192e.c | 463 +- hal/phydm/txbf/haltxbf8192e.h | 86 +- hal/phydm/txbf/haltxbf8814a.c | 842 +- hal/phydm/txbf/haltxbf8814a.h | 129 +- hal/phydm/txbf/haltxbf8822b.c | 1203 +- hal/phydm/txbf/haltxbf8822b.h | 122 +- hal/phydm/txbf/haltxbfinterface.c | 1942 +- hal/phydm/txbf/haltxbfinterface.h | 281 +- hal/phydm/txbf/haltxbfjaguar.c | 595 +- hal/phydm/txbf/haltxbfjaguar.h | 113 +- hal/phydm/txbf/phydm_hal_txbf_api.c | 191 +- hal/phydm/txbf/phydm_hal_txbf_api.h | 86 +- hal/rtl8822b/rtl8822b.h | 54 +- hal/rtl8822b/rtl8822b_cmd.c | 379 +- hal/rtl8822b/rtl8822b_halinit.c | 127 +- hal/rtl8822b/rtl8822b_mac.c | 67 +- hal/rtl8822b/rtl8822b_ops.c | 1500 +- hal/rtl8822b/rtl8822b_phy.c | 2110 +- hal/rtl8822b/usb/rtl8822bu.h | 18 +- hal/rtl8822b/usb/rtl8822bu_halinit.c | 198 +- hal/rtl8822b/usb/rtl8822bu_halmac.c | 211 +- hal/rtl8822b/usb/rtl8822bu_io.c | 11 +- hal/rtl8822b/usb/rtl8822bu_led.c | 9 +- hal/rtl8822b/usb/rtl8822bu_ops.c | 114 +- hal/rtl8822b/usb/rtl8822bu_recv.c | 16 +- hal/rtl8822b/usb/rtl8822bu_xmit.c | 114 +- ifcfg-wlan0 | 6 +- include/Hal8188EPhyCfg.h | 23 +- include/Hal8188EPhyReg.h | 9 +- include/Hal8188EPwrSeq.h | 11 +- include/Hal8188FPhyCfg.h | 34 +- include/Hal8188FPhyReg.h | 9 +- include/Hal8188FPwrSeq.h | 14 + include/Hal8192EPhyCfg.h | 45 +- include/Hal8192EPhyReg.h | 14 + include/Hal8192EPwrSeq.h | 14 + include/Hal8703BPhyCfg.h | 31 +- include/Hal8703BPhyReg.h | 9 +- include/Hal8703BPwrSeq.h | 14 + include/Hal8723BPhyCfg.h | 32 +- include/Hal8723BPhyReg.h | 9 +- include/Hal8723BPwrSeq.h | 14 + include/Hal8723DPhyCfg.h | 31 +- include/Hal8723DPhyReg.h | 11 +- include/Hal8723DPwrSeq.h | 15 +- include/Hal8723PwrSeq.h | 14 + include/Hal8812PhyCfg.h | 37 +- include/Hal8812PhyReg.h | 9 +- include/Hal8812PwrSeq.h | 11 +- include/Hal8814PhyCfg.h | 42 +- include/Hal8814PhyReg.h | 9 +- include/Hal8814PwrSeq.h | 11 +- include/Hal8821APwrSeq.h | 14 + include/HalPwrSeqCmd.h | 9 +- include/HalVerDef.h | 41 +- include/autoconf.h | 293 +- include/basic_types.h | 33 +- include/byteorder/big_endian.h | 9 +- include/byteorder/generic.h | 9 +- include/byteorder/little_endian.h | 9 +- include/byteorder/swab.h | 9 +- include/byteorder/swabb.h | 9 +- include/circ_buf.h | 11 +- include/cmd_osdep.h | 9 +- include/custom_gpio.h | 14 + include/drv_conf.h | 221 +- include/drv_types.h | 398 +- include/drv_types_ce.h | 9 +- include/drv_types_gspi.h | 9 +- include/drv_types_linux.h | 9 +- include/drv_types_pci.h | 18 +- include/drv_types_sdio.h | 23 +- include/drv_types_xp.h | 9 +- include/ethernet.h | 9 +- include/gspi_hal.h | 9 +- include/gspi_ops.h | 11 +- include/gspi_ops_linux.h | 9 +- include/gspi_osintf.h | 9 +- include/h2clbk.h | 9 +- include/hal_btcoex.h | 20 +- include/hal_com.h | 174 +- include/hal_com_h2c.h | 318 +- include/hal_com_led.h | 9 +- include/hal_com_phycfg.h | 205 +- include/hal_com_reg.h | 1980 +- include/hal_data.h | 643 +- include/hal_gspi.h | 9 +- include/hal_ic_cfg.h | 119 +- include/hal_intf.h | 175 +- include/hal_pg.h | 52 +- include/hal_phy.h | 17 +- include/hal_phy_reg.h | 9 +- include/hal_sdio.h | 16 +- include/ieee80211.h | 215 +- include/ieee80211_ext.h | 39 +- include/if_ether.h | 9 +- include/ip.h | 9 +- include/linux/wireless.h | 9 +- include/mlme_osdep.h | 10 +- include/mp_custom_oid.h | 9 +- include/nic_spec.h | 9 +- include/osdep_intf.h | 72 +- include/osdep_service.h | 414 +- include/osdep_service_bsd.h | 1456 +- include/osdep_service_ce.h | 346 +- include/osdep_service_linux.h | 244 +- include/osdep_service_xp.h | 366 +- include/pci_hal.h | 9 +- include/pci_ops.h | 13 +- include/pci_osintf.h | 18 +- include/recv_osdep.h | 16 +- include/rtl8188e_cmd.h | 12 +- include/rtl8188e_dm.h | 9 +- include/rtl8188e_hal.h | 48 +- include/rtl8188e_led.h | 9 +- include/rtl8188e_recv.h | 9 +- include/rtl8188e_rf.h | 9 +- include/rtl8188e_spec.h | 30 +- include/rtl8188e_sreset.h | 9 +- include/rtl8188e_xmit.h | 9 +- include/rtl8188f_cmd.h | 24 +- include/rtl8188f_dm.h | 9 +- include/rtl8188f_hal.h | 98 +- include/rtl8188f_led.h | 25 +- include/rtl8188f_recv.h | 24 +- include/rtl8188f_rf.h | 9 +- include/rtl8188f_spec.h | 126 +- include/rtl8188f_sreset.h | 13 +- include/rtl8188f_xmit.h | 457 +- include/rtl8192e_cmd.h | 29 +- include/rtl8192e_dm.h | 9 +- include/rtl8192e_hal.h | 34 +- include/rtl8192e_led.h | 9 +- include/rtl8192e_recv.h | 9 +- include/rtl8192e_rf.h | 9 +- include/rtl8192e_spec.h | 114 +- include/rtl8192e_sreset.h | 9 +- include/rtl8192e_xmit.h | 9 +- include/rtl8703b_cmd.h | 12 +- include/rtl8703b_dm.h | 9 +- include/rtl8703b_hal.h | 67 +- include/rtl8703b_led.h | 9 +- include/rtl8703b_recv.h | 9 +- include/rtl8703b_rf.h | 9 +- include/rtl8703b_spec.h | 108 +- include/rtl8703b_sreset.h | 9 +- include/rtl8703b_xmit.h | 9 +- include/rtl8723b_cmd.h | 12 +- include/rtl8723b_dm.h | 9 +- include/rtl8723b_hal.h | 67 +- include/rtl8723b_led.h | 9 +- include/rtl8723b_recv.h | 9 +- include/rtl8723b_rf.h | 9 +- include/rtl8723b_spec.h | 108 +- include/rtl8723b_sreset.h | 9 +- include/rtl8723b_xmit.h | 9 +- include/rtl8723d_cmd.h | 12 +- include/rtl8723d_dm.h | 9 +- include/rtl8723d_hal.h | 73 +- include/rtl8723d_led.h | 9 +- include/rtl8723d_lps_poff.h | 9 +- include/rtl8723d_recv.h | 11 +- include/rtl8723d_rf.h | 9 +- include/rtl8723d_spec.h | 20 +- include/rtl8723d_sreset.h | 9 +- include/rtl8723d_xmit.h | 9 +- include/rtl8812a_cmd.h | 43 +- include/rtl8812a_dm.h | 9 +- include/rtl8812a_hal.h | 105 +- include/rtl8812a_led.h | 23 +- include/rtl8812a_recv.h | 25 +- include/rtl8812a_rf.h | 9 +- include/rtl8812a_spec.h | 500 +- include/rtl8812a_sreset.h | 13 +- include/rtl8812a_xmit.h | 54 +- include/rtl8814a_cmd.h | 56 +- include/rtl8814a_dm.h | 9 +- include/rtl8814a_hal.h | 37 +- include/rtl8814a_led.h | 9 +- include/rtl8814a_recv.h | 9 +- include/rtl8814a_rf.h | 9 +- include/rtl8814a_spec.h | 16 +- include/rtl8814a_sreset.h | 9 +- include/rtl8814a_xmit.h | 9 +- include/rtl8821a_spec.h | 20 +- include/rtl8821a_xmit.h | 65 +- include/rtl8821c_hal.h | 220 +- include/rtl8821cs_hal.h | 9 +- include/rtl8821cu_hal.h | 9 +- include/rtl8822b_hal.h | 33 +- include/rtl8822be_hal.h | 9 +- include/rtl8822bs_hal.h | 13 +- include/rtl8822bu_hal.h | 16 +- include/rtw_android.h | 17 +- include/rtw_ap.h | 106 +- include/rtw_beamforming.h | 300 +- include/rtw_br_ext.h | 27 +- include/rtw_bt_mp.h | 9 +- include/rtw_btcoex.h | 68 +- include/rtw_byteorder.h | 9 +- include/rtw_cmd.h | 158 +- include/rtw_debug.h | 345 +- include/rtw_eeprom.h | 23 +- include/rtw_efuse.h | 45 +- include/rtw_event.h | 9 +- include/rtw_ht.h | 9 +- include/rtw_io.h | 227 +- include/rtw_ioctl.h | 385 +- include/rtw_ioctl_query.h | 15 +- include/rtw_ioctl_rtl.h | 9 +- include/rtw_ioctl_set.h | 23 +- include/rtw_iol.h | 59 +- include/rtw_mcc.h | 33 +- include/rtw_mem.h | 9 +- include/rtw_mi.h | 134 +- include/rtw_mlme.h | 307 +- include/rtw_mlme_ext.h | 288 +- include/rtw_mp.h | 297 +- include/rtw_mp_ioctl.h | 19 +- include/rtw_mp_phy_regdef.h | 31 +- include/rtw_odm.h | 72 +- include/rtw_p2p.h | 91 +- include/rtw_pwrctrl.h | 153 +- include/rtw_qos.h | 9 +- include/rtw_recv.h | 92 +- include/rtw_rf.h | 138 +- include/rtw_sdio.h | 8 +- include/rtw_security.h | 83 +- include/rtw_sreset.h | 9 +- include/rtw_tdls.h | 36 +- include/rtw_version.h | 4 +- include/rtw_vht.h | 12 +- include/rtw_wapi.h | 14 + include/rtw_wifi_regd.h | 11 +- include/rtw_xmit.h | 150 +- include/sdio_hal.h | 23 +- include/sdio_ops.h | 149 +- include/sdio_ops_ce.h | 31 +- include/sdio_ops_linux.h | 62 +- include/sdio_ops_xp.h | 31 +- include/sdio_osintf.h | 15 +- include/sta_info.h | 119 +- include/usb_hal.h | 30 +- include/usb_ops.h | 81 +- include/usb_ops_linux.h | 33 +- include/usb_osintf.h | 9 +- include/usb_vendor_req.h | 19 +- include/wifi.h | 202 +- include/wlan_bssdef.h | 19 +- include/xmit_osdep.h | 45 +- os_dep/linux/custom_gpio_linux.c | 28 +- os_dep/linux/ioctl_cfg80211.c | 3044 +- os_dep/linux/ioctl_cfg80211.h | 198 +- os_dep/linux/ioctl_linux.c | 2449 +- os_dep/linux/ioctl_mp.c | 424 +- os_dep/linux/mlme_linux.c | 179 +- os_dep/linux/os_intfs.c | 1532 +- os_dep/linux/recv_linux.c | 122 +- os_dep/linux/rtw_android.c | 209 +- os_dep/linux/rtw_cfgvendor.c | 262 +- os_dep/linux/rtw_cfgvendor.h | 13 +- os_dep/linux/rtw_proc.c | 1964 +- os_dep/linux/rtw_proc.h | 48 +- os_dep/linux/usb_intf.c | 246 +- os_dep/linux/usb_ops_linux.c | 171 +- os_dep/linux/wifi_regd.c | 184 +- os_dep/linux/xmit_linux.c | 66 +- os_dep/osdep_service.c | 414 +- platform/custom_country_chplan.h | 12 +- platform/platform_ARM_SUN50IW1P1_sdio.c | 31 +- platform/platform_ARM_SUNnI_sdio.c | 45 +- platform/platform_ARM_SUNxI_sdio.c | 9 +- platform/platform_ARM_SUNxI_usb.c | 39 +- platform/platform_ARM_WMT_sdio.c | 9 +- platform/platform_RTK_DMP_usb.c | 9 +- platform/platform_arm_act_sdio.c | 13 +- platform/platform_ops.c | 9 +- platform/platform_ops.h | 9 +- platform/platform_sprd_sdio.c | 11 +- rtl8822b.mk | 78 +- 467 files changed, 122035 insertions(+), 83976 deletions(-) diff --git a/Makefile b/Makefile index 8c12423..2996eaf 100644 --- a/Makefile +++ b/Makefile @@ -7,16 +7,20 @@ EXTRA_CFLAGS += -O1 #EXTRA_CFLAGS += -pedantic #EXTRA_CFLAGS += -Wshadow -Wpointer-arith -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -PLATFORM = LINUX EXTRA_CFLAGS += -Wno-unused-variable EXTRA_CFLAGS += -Wno-unused-value EXTRA_CFLAGS += -Wno-unused-label EXTRA_CFLAGS += -Wno-unused-parameter EXTRA_CFLAGS += -Wno-unused-function EXTRA_CFLAGS += -Wno-unused +#EXTRA_CFLAGS += -Wno-uninitialized + +GCC_VER_49 := $(shell echo `$(CC) -dumpversion | cut -f1-2 -d.` \>= 4.9 | bc ) +ifeq ($(GCC_VER_49),1) +EXTRA_CFLAGS += -Wno-date-time # Fix compile error && warning on gcc 4.9 and later +endif EXTRA_CFLAGS += -I$(src)/include -EXTRA_CFLAGS += -I$(src)/hal/phydm EXTRA_LDFLAGS += --strip-debug @@ -35,7 +39,6 @@ CONFIG_RTL8188F = n CONFIG_RTL8822B = y CONFIG_RTL8723D = n CONFIG_RTL8821C = n - ######################### Interface ########################### CONFIG_USB_HCI = y CONFIG_PCI_HCI = n @@ -43,7 +46,7 @@ CONFIG_SDIO_HCI = n CONFIG_GSPI_HCI = n ########################## Features ########################### CONFIG_MP_INCLUDED = y -CONFIG_POWER_SAVING = n +CONFIG_POWER_SAVING = y CONFIG_USB_AUTOSUSPEND = n CONFIG_HW_PWRP_DETECTION = n CONFIG_WIFI_TEST = n @@ -54,8 +57,8 @@ CONFIG_EFUSE_CONFIG_FILE = y CONFIG_EXT_CLK = n CONFIG_TRAFFIC_PROTECT = y CONFIG_LOAD_PHY_PARA_FROM_FILE = y -CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY = n -CONFIG_CALIBRATE_TX_POWER_TO_MAX = n +CONFIG_TXPWR_BY_RATE_EN = y +CONFIG_TXPWR_LIMIT_EN = n CONFIG_RTW_ADAPTIVITY_EN = disable CONFIG_RTW_ADAPTIVITY_MODE = normal CONFIG_SIGNAL_SCALE_MAPPING = n @@ -66,11 +69,13 @@ CONFIG_TDLS = n CONFIG_WIFI_MONITOR = n CONFIG_MCC_MODE = n CONFIG_APPEND_VENDOR_IE_ENABLE = n +CONFIG_RTW_NAPI = y +CONFIG_RTW_GRO = y ########################## Debug ########################### -CONFIG_RTW_DEBUG = y +CONFIG_RTW_DEBUG = n # default log level is _DRV_INFO_ = 4, # please refer to "How_to_set_driver_debug_log_level.doc" to set the available level. -CONFIG_RTW_LOG_LEVEL = 0 +CONFIG_RTW_LOG_LEVEL = 4 ######################## Wake On Lan ########################## CONFIG_WOWLAN = n CONFIG_GPIO_WAKEUP = n @@ -85,7 +90,6 @@ CONFIG_RTW_SDIO_PM_KEEP_POWER = y ###################### MP HW TX MODE FOR VHT ####################### CONFIG_MP_VHT_HW_TX_MODE = n ###################### Platform Related ####################### -CONFIG_PLATFORM_ARM_RPI = n CONFIG_PLATFORM_I386_PC = y CONFIG_PLATFORM_ANDROID_X86 = n CONFIG_PLATFORM_ANDROID_INTEL_X86 = n @@ -131,9 +135,6 @@ CONFIG_PLATFORM_ARM_SUN50IW1P1 = n CONFIG_PLATFORM_ARM_RTD299X = n CONFIG_PLATFORM_ARM_SPREADTRUM_6820 = n CONFIG_PLATFORM_ARM_SPREADTRUM_8810 = n - -# Setting to n -CONFIG_PLATFORM_AML = y CONFIG_PLATFORM_ARM_WMT = n CONFIG_PLATFORM_TI_DM365 = n CONFIG_PLATFORM_MOZART = n @@ -141,20 +142,14 @@ CONFIG_PLATFORM_RTK119X = n CONFIG_PLATFORM_RTK129X = n CONFIG_PLATFORM_NOVATEK_NT72668 = n CONFIG_PLATFORM_HISILICON = n +CONFIG_PLATFORM_NV_TK1 = n +CONFIG_PLATFORM_RTL8197D = n ############################################################### CONFIG_DRVEXT_MODULE = n export TopDIR ?= $(shell pwd) -ifeq ($(CONFIG_PLATFORM_AML), y) -EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -fno-pic -EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DRTW_USE_CFG80211_STA_EVENT -EXTRA_CFLAGS += -DCONFIG_LPS_SLOW_TRANSITION -EXTRA_CFLAGS += -DCONFIG_RADIO_WORK -endif - ########### COMMON ################################# ifeq ($(CONFIG_GSPI_HCI), y) HCI_NAME = gspi @@ -207,60 +202,40 @@ _HAL_INTFS_FILES := hal/hal_intf.o \ hal/hal_com_phycfg.o \ hal/hal_phy.o \ hal/hal_dm.o \ + hal/hal_btcoex_wifionly.o \ hal/hal_btcoex.o \ hal/hal_mp.o \ hal/hal_mcc.o \ hal/hal_hci/hal_$(HCI_NAME).o \ hal/led/hal_$(HCI_NAME)_led.o - -_OUTSRC_FILES := hal/phydm/phydm_debug.o \ - hal/phydm/phydm_antdiv.o\ - hal/phydm/phydm_antdect.o\ - hal/phydm/phydm_interface.o\ - hal/phydm/phydm_hwconfig.o\ - hal/phydm/phydm.o\ - hal/phydm/halphyrf_ce.o\ - hal/phydm/phydm_edcaturbocheck.o\ - hal/phydm/phydm_dig.o\ - hal/phydm/phydm_pathdiv.o\ - hal/phydm/phydm_rainfo.o\ - hal/phydm/phydm_dynamicbbpowersaving.o\ - hal/phydm/phydm_powertracking_ce.o\ - hal/phydm/phydm_dynamictxpower.o\ - hal/phydm/phydm_adaptivity.o\ - hal/phydm/phydm_cfotracking.o\ - hal/phydm/phydm_noisemonitor.o\ - hal/phydm/phydm_acs.o\ - hal/phydm/phydm_beamforming.o\ - hal/phydm/phydm_dfs.o\ - hal/phydm/txbf/halcomtxbf.o\ - hal/phydm/txbf/haltxbfinterface.o\ - hal/phydm/phydm_kfree.o\ - hal/phydm/phydm_ccx.o - EXTRA_CFLAGS += -I$(src)/platform _PLATFORM_FILES := platform/platform_ops.o -ifeq ($(CONFIG_BT_COEXIST), y) EXTRA_CFLAGS += -I$(src)/hal/btc -_OUTSRC_FILES += hal/btc/HalBtc8192e1Ant.o \ - hal/btc/HalBtc8192e2Ant.o \ - hal/btc/HalBtc8723b1Ant.o \ - hal/btc/HalBtc8723b2Ant.o \ - hal/btc/HalBtc8812a1Ant.o \ - hal/btc/HalBtc8812a2Ant.o \ - hal/btc/HalBtc8821a1Ant.o \ - hal/btc/HalBtc8821a2Ant.o \ - hal/btc/HalBtc8821aCsr2Ant.o \ - hal/btc/HalBtc8703b1Ant.o \ +_BTC_FILES += hal/btc/halbtc8723bwifionly.o \ + hal/btc/halbtc8822bwifionly.o \ + hal/btc/halbtc8821cwifionly.o +ifeq ($(CONFIG_BT_COEXIST), y) +_BTC_FILES += hal/btc/halbtc8192e1ant.o \ + hal/btc/halbtc8192e2ant.o \ + hal/btc/halbtc8723b1ant.o \ + hal/btc/halbtc8723b2ant.o \ + hal/btc/halbtc8812a1ant.o \ + hal/btc/halbtc8812a2ant.o \ + hal/btc/halbtc8821a1ant.o \ + hal/btc/halbtc8821a2ant.o \ + hal/btc/halbtc8703b1ant.o \ hal/btc/halbtc8723d1ant.o \ hal/btc/halbtc8723d2ant.o \ - hal/btc/HalBtc8822b1Ant.o + hal/btc/halbtc8822b1ant.o \ + hal/btc/halbtc8822b2ant.o \ + hal/btc/halbtc8821c1ant.o \ + hal/btc/halbtc8821c2ant.o endif - +include $(TopDIR)/hal/phydm/phydm.mk ########### HAL_RTL8188E ################################# ifeq ($(CONFIG_RTL8188E), y) @@ -293,6 +268,8 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \ hal/$(RTL871X)/$(RTL871X)_dm.o \ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ hal/$(RTL871X)/$(RTL871X)_cmd.o \ + hal/$(RTL871X)/hal8188e_s_fw.o \ + hal/$(RTL871X)/hal8188e_t_fw.o \ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \ @@ -318,17 +295,6 @@ ifeq ($(CONFIG_SDIO_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_SDIO.o endif -#hal/OUTSRC/$(RTL871X)/Hal8188EFWImg_CE.o -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\ - hal/phydm/$(RTL871X)/halhwimg8188e_t_fw.o\ - hal/phydm/$(RTL871X)/halhwimg8188e_s_fw.o\ - hal/phydm/$(RTL871X)/halphyrf_8188e_ce.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\ - hal/phydm/$(RTL871X)/hal8188erateadaptive.o\ - hal/phydm/$(RTL871X)/phydm_rtl8188e.o - endif ########### HAL_RTL8192E ################################# @@ -358,6 +324,7 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \ hal/$(RTL871X)/$(RTL871X)_dm.o \ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ hal/$(RTL871X)/$(RTL871X)_cmd.o \ + hal/$(RTL871X)/hal8192e_fw.o \ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \ @@ -379,15 +346,9 @@ endif ifeq ($(CONFIG_PCI_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_PCIE.o endif - -#hal/OUTSRC/$(RTL871X)/HalHWImg8188E_FW.o -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\ - hal/phydm/$(RTL871X)/halhwimg8192e_fw.o\ - hal/phydm/$(RTL871X)/halphyrf_8192e_ce.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\ - hal/phydm/$(RTL871X)/phydm_rtl8192e.o +ifeq ($(CONFIG_SDIO_HCI), y) +_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_SDIO.o +endif endif @@ -448,18 +409,14 @@ endif ifeq ($(CONFIG_PCI_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_PCIE.o endif +ifeq ($(CONFIG_SDIO_HCI), y) +_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_SDIO.o +endif endif ifeq ($(CONFIG_RTL8812A), y) EXTRA_CFLAGS += -DCONFIG_RTL8812A -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_fw.o\ - hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\ - hal/phydm/$(RTL871X)/halphyrf_8812a_ce.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\ - hal/phydm/$(RTL871X)/phydm_rtl8812a.o\ - hal/phydm/txbf/haltxbfjaguar.o +_HAL_INTFS_FILES += hal/rtl8812a/hal8812a_fw.o endif ifeq ($(CONFIG_RTL8821A), y) @@ -484,93 +441,13 @@ endif endif EXTRA_CFLAGS += -DCONFIG_RTL8821A -_OUTSRC_FILES += hal/phydm/rtl8821a/halhwimg8821a_fw.o\ - hal/phydm/rtl8821a/halhwimg8821a_mac.o\ - hal/phydm/rtl8821a/halhwimg8821a_bb.o\ - hal/phydm/rtl8821a/halhwimg8821a_rf.o\ - hal/phydm/rtl8812a/halphyrf_8812a_ce.o\ - hal/phydm/rtl8821a/halphyrf_8821a_ce.o\ - hal/phydm/rtl8821a/phydm_regconfig8821a.o\ - hal/phydm/rtl8821a/phydm_rtl8821a.o\ - hal/phydm/rtl8821a/phydm_iqk_8821a_ce.o\ - hal/phydm/txbf/haltxbfjaguar.o - -endif - -endif - -RTL871X := rtl8822b -EXTRA_CFLAGS += -DCONFIG_RTL8822B -ifeq ($(CONFIG_USB_HCI), y) -MODULE_NAME = 8822bu -endif -ifeq ($(CONFIG_PCI_HCI), y) -MODULE_NAME = 8822be -endif -ifeq ($(CONFIG_SDIO_HCI), y) -MODULE_NAME = 8822bs +_HAL_INTFS_FILES += hal/rtl8812a/hal8821a_fw.o + endif -ifeq ($(CONFIG_MP_INCLUDED), y) -### 8822B Default Enable VHT MP HW TX MODE ### -#EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE -#CONFIG_MP_VHT_HW_TX_MODE = y endif -_HAL_HALMAC_FILES += hal/halmac/halmac_api.o - -_HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_api_88xx.o \ - hal/halmac/halmac_88xx/halmac_func_88xx.o \ - hal/halmac/halmac_88xx/halmac_api_88xx_usb.o \ - hal/halmac/halmac_88xx/halmac_api_88xx_sdio.o \ - hal/halmac/halmac_88xx/halmac_api_88xx_pcie.o - -_HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.o - -_HAL_INTFS_FILES += hal/hal_halmac.o - -_HAL_INTFS_FILES += hal/rtl8822b/rtl8822b_halinit.o \ - hal/rtl8822b/rtl8822b_mac.o \ - hal/rtl8822b/rtl8822b_cmd.o \ - hal/rtl8822b/rtl8822b_phy.o \ - hal/rtl8822b/rtl8822b_ops.o - -_HAL_INTFS_FILES += hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_halinit.o \ - hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_halmac.o \ - hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_io.o \ - hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \ - hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o \ - hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \ - hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_ops.o - -ifeq ($(CONFIG_USB_HCI), y) -_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8822B_USB.o -endif -ifeq ($(CONFIG_PCI_HCI), y) -_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8822B_PCIE.o -endif -ifeq ($(CONFIG_SDIO_HCI), y) -#_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8822B_SDIO.o -endif - -_OUTSRC_FILES += hal/phydm/rtl8822b/halhwimg8822b_bb.o \ - hal/phydm/rtl8822b/halhwimg8822b_fw.o \ - hal/phydm/rtl8822b/halhwimg8822b_mac.o \ - hal/phydm/rtl8822b/halhwimg8822b_rf.o \ - hal/phydm/rtl8822b/halphyrf_8822b.o \ - hal/phydm/rtl8822b/phydm_hal_api8822b.o \ - hal/phydm/rtl8822b/phydm_iqk_8822b.o \ - hal/phydm/rtl8822b/phydm_regconfig8822b.o \ - hal/phydm/rtl8822b/phydm_rtl8822b.o - -_HAL_INTFS_FILES += $(_HAL_HALMAC_FILES) - ########### HAL_RTL8723B ################################# ifeq ($(CONFIG_RTL8723B), y) @@ -597,7 +474,7 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \ hal/$(RTL871X)/$(RTL871X)_dm.o \ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ hal/$(RTL871X)/$(RTL871X)_cmd.o \ - + hal/$(RTL871X)/hal8723b_fw.o _HAL_INTFS_FILES += \ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \ @@ -617,23 +494,17 @@ endif ifeq ($(CONFIG_PCI_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_PCIE.o endif - -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\ - hal/phydm/$(RTL871X)/halhwimg8723b_fw.o\ - hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\ - hal/phydm/$(RTL871X)/halphyrf_8723b_ce.o\ - hal/phydm/$(RTL871X)/phydm_rtl8723b.o +ifeq ($(CONFIG_SDIO_HCI), y) +_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_SDIO.o +endif endif ########### HAL_RTL8814A ################################# ifeq ($(CONFIG_RTL8814A), y) ## ADD NEW VHT MP HW TX MODE ## -EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE -CONFIG_MP_VHT_HW_TX_MODE = y +#EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE +#CONFIG_MP_VHT_HW_TX_MODE = y ########################################## RTL871X = rtl8814a ifeq ($(CONFIG_USB_HCI), y) @@ -659,6 +530,7 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \ hal/$(RTL871X)/$(RTL871X)_dm.o \ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ hal/$(RTL871X)/$(RTL871X)_cmd.o \ + hal/$(RTL871X)/hal8814a_fw.o _HAL_INTFS_FILES += \ @@ -684,16 +556,6 @@ ifeq ($(CONFIG_PCI_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_PCIE.o endif -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\ - hal/phydm/$(RTL871X)/halhwimg8814a_fw.o\ - hal/phydm/$(RTL871X)/phydm_iqk_8814a.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\ - hal/phydm/$(RTL871X)/halphyrf_8814a_ce.o\ - hal/phydm/$(RTL871X)/phydm_rtl8814a.o\ - hal/phydm/txbf/haltxbf8814a.o - endif ########### HAL_RTL8723C ################################# @@ -725,7 +587,7 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \ hal/$(RTL871X)/$(RTL871X)_dm.o \ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ hal/$(RTL871X)/$(RTL871X)_cmd.o \ - + hal/$(RTL871X)/hal8703b_fw.o _HAL_INTFS_FILES += \ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \ @@ -746,12 +608,6 @@ ifeq ($(CONFIG_PCI_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_PCIE.o endif -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\ - hal/phydm/$(RTL871X)/halhwimg8703b_fw.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\ - hal/phydm/$(RTL871X)/halphyrf_8703b.o endif ########### HAL_RTL8723D ################################# @@ -783,6 +639,7 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \ hal/$(RTL871X)/$(RTL871X)_dm.o \ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ hal/$(RTL871X)/$(RTL871X)_cmd.o \ + hal/$(RTL871X)/hal8723d_fw.o \ hal/$(RTL871X)/$(RTL871X)_lps_poff.o @@ -805,13 +662,6 @@ ifeq ($(CONFIG_PCI_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_PCIE.o endif -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\ - hal/phydm/$(RTL871X)/halhwimg8723d_fw.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\ - hal/phydm/$(RTL871X)/phydm_rtl8723d.o\ - hal/phydm/$(RTL871X)/halphyrf_8723d.o endif ########### HAL_RTL8188F ################################# @@ -840,7 +690,7 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \ hal/$(RTL871X)/$(RTL871X)_dm.o \ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ hal/$(RTL871X)/$(RTL871X)_cmd.o \ - + hal/$(RTL871X)/hal8188f_fw.o _HAL_INTFS_FILES += \ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \ @@ -862,30 +712,16 @@ ifeq ($(CONFIG_SDIO_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_SDIO.o endif -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\ - hal/phydm/$(RTL871X)/halhwimg8188f_fw.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\ - hal/phydm/$(RTL871X)/halphyrf_8188f.o \ - hal/phydm/$(RTL871X)/phydm_rtl8188f.o - endif ########### HAL_RTL8822B ################################# -#ifeq ($(CONFIG_RTL8822B), y) -#include $(TopDIR)/rtl8822b.mk -#endif +ifeq ($(CONFIG_RTL8822B), y) +include $(TopDIR)/rtl8822b.mk +endif ########### HAL_RTL8821C ################################# ifeq ($(CONFIG_RTL8821C), y) include $(TopDIR)/rtl8821c.mk - -_OUTSRC_FILES += hal/phydm/rtl8821c/halhwimg8821c_testchip_bb.o \ - hal/phydm/rtl8821c/halhwimg8821c_testchip_mac.o \ - hal/phydm/rtl8821c/halhwimg8821c_testchip_rf.o \ - hal/phydm/rtl8821c/phydm_hal_api8821c.o \ - hal/phydm/rtl8821c/phydm_regconfig8821c.o endif ########### AUTO_CFG ################################# @@ -981,8 +817,25 @@ endif ifeq ($(CONFIG_LOAD_PHY_PARA_FROM_FILE), y) EXTRA_CFLAGS += -DCONFIG_LOAD_PHY_PARA_FROM_FILE -EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/etc/firmware/\" -#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"$(TopDIR)/\" +#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER +#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/lib/firmware/\" +EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"\" +endif + +ifeq ($(CONFIG_TXPWR_BY_RATE_EN), n) +EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=0 +else ifeq ($(CONFIG_TXPWR_BY_RATE_EN), y) +EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=1 +else ifeq ($(CONFIG_TXPWR_BY_RATE_EN), auto) +EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=2 +endif + +ifeq ($(CONFIG_TXPWR_LIMIT_EN), n) +EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=0 +else ifeq ($(CONFIG_TXPWR_LIMIT_EN), y) +EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=1 +else ifeq ($(CONFIG_TXPWR_LIMIT_EN), auto) +EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=2 endif ifeq ($(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY), y) @@ -1066,9 +919,6 @@ EXTRA_CFLAGS += -DCONFIG_BR_EXT EXTRA_CFLAGS += '-DCONFIG_BR_EXT_BRNAME="'$(BR_NAME)'"' endif -ifeq ($(CONFIG_ANTENNA_DIVERSITY), y) -EXTRA_CFLAGS += -DCONFIG_ANTENNA_DIVERSITY -endif ifeq ($(CONFIG_TDLS), y) EXTRA_CFLAGS += -DCONFIG_TDLS @@ -1082,6 +932,14 @@ ifeq ($(CONFIG_MCC_MODE), y) EXTRA_CFLAGS += -DCONFIG_MCC_MODE endif +ifeq ($(CONFIG_RTW_NAPI), y) +EXTRA_CFLAGS += -DCONFIG_RTW_NAPI +endif + +ifeq ($(CONFIG_RTW_GRO), y) +EXTRA_CFLAGS += -DCONFIG_RTW_GRO +endif + ifeq ($(CONFIG_MP_VHT_HW_TX_MODE), y) EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE ifeq ($(CONFIG_PLATFORM_I386_PC), y) @@ -1107,7 +965,6 @@ EXTRA_CFLAGS += -DDM_ODM_SUPPORT_TYPE=0x04 ifeq ($(CONFIG_PLATFORM_I386_PC), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT -EXTRA_CFLAGS += -DPLATFORM_LINUX SUBARCH := $(shell uname -m | sed -e s/i.86/i386/) ARCH ?= $(SUBARCH) CROSS_COMPILE ?= @@ -1117,13 +974,14 @@ MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/ INSTALL_PREFIX := endif -ifeq ($(CONFIG_PLATFORM_ARM_RPI), y) +ifeq ($(CONFIG_PLATFORM_NV_TK1), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1 EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT -EXTRA_CFLAGS += -DPLATFORM_LINUX +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE ARCH ?= arm CROSS_COMPILE ?= -KVER ?= $(shell uname -r) +KVER := $(shell uname -r) KSRC := /lib/modules/$(KVER)/build MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/ INSTALL_PREFIX := @@ -1142,6 +1000,53 @@ MODULE_NAME :=wlan endif +ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM705X), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +#EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC +# default setting for Android 4.1, 4.2, 4.3, 4.4 +EXTRA_CFLAGS += -DCONFIG_PLATFORM_ACTIONS_ATM705X +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT + +# Enable this for Android 5.0 +EXTRA_CFLAGS += -DCONFIG_RADIO_WORK + +ifeq ($(CONFIG_SDIO_HCI), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +_PLATFORM_FILES += platform/platform_arm_act_sdio.o +endif + +ARCH := arm +CROSS_COMPILE := /opt/arm-2011.09/bin/arm-none-linux-gnueabi- +KSRC := /home/android_sdk/Action-semi/705a_android_L/android/kernel +endif + +ifeq ($(CONFIG_PLATFORM_ARM_SUN50IW1P1), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN50IW1P1 +EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT +# default setting for Android 4.1, 4.2 +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE +EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS + +# Enable this for Android 5.0 +EXTRA_CFLAGS += -DCONFIG_RADIO_WORK + +ifeq ($(CONFIG_USB_HCI), y) +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX +_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o +endif +ifeq ($(CONFIG_SDIO_HCI), y) +_PLATFORM_FILES += platform/platform_ARM_SUN50IW1P1_sdio.o +endif + +ARCH := arm64 +# ===Cross compile setting for Android 5.1(64) SDK === +CROSS_COMPILE := /home/android_sdk/Allwinner/a64/android-51/lichee/out/sun50iw1p1/android/common/buildroot/external-toolchain/bin/aarch64-linux-gnu- +KSRC :=/home/android_sdk/Allwinner/a64/android-51/lichee/linux-3.10/ +endif ifeq ($(CONFIG_PLATFORM_TI_AM3517), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE @@ -1150,6 +1055,37 @@ KSRC := $(shell pwd)/../../../Android/kernel ARCH := arm endif +ifeq ($(CONFIG_PLATFORM_MSTAR_TITANIA12), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR -DCONFIG_PLATFORM_MSTAR_TITANIA12 +ARCH:=mips +CROSS_COMPILE:= /usr/src/Mstar_kernel/mips-4.3/bin/mips-linux-gnu- +KVER:= 2.6.28.9 +KSRC:= /usr/src/Mstar_kernel/2.6.28.9/ +endif + +ifeq ($(CONFIG_PLATFORM_MSTAR), y) +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR +EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR_HIGH +ifeq ($(CONFIG_USB_HCI), y) +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX -DCONFIG_FIX_NR_BULKIN_BUFFER +endif +ARCH:=arm +CROSS_COMPILE:= /usr/src/bin/arm-none-linux-gnueabi- +KVER:= 3.1.10 +KSRC:= /usr/src/Mstar_kernel/3.1.10/ +endif + +ifeq ($(CONFIG_PLATFORM_ANDROID_X86), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +SUBARCH := $(shell uname -m | sed -e s/i.86/i386/) +ARCH := $(SUBARCH) +CROSS_COMPILE := /media/DATA-2/android-x86/ics-x86_20120130/prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/bin/i686-unknown-linux-gnu- +KSRC := /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel +MODULE_NAME :=wlan +endif ifeq ($(CONFIG_PLATFORM_ANDROID_INTEL_X86), y) EXTRA_CFLAGS += -DCONFIG_PLATFORM_ANDROID_INTEL_X86 @@ -1163,10 +1099,469 @@ EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE endif endif +ifeq ($(CONFIG_PLATFORM_JB_X86), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +SUBARCH := $(shell uname -m | sed -e s/i.86/i386/) +ARCH := $(SUBARCH) +CROSS_COMPILE := /home/android_sdk/android-x86_JB/prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/bin/i686-linux-android- +KSRC := /home/android_sdk/android-x86_JB/out/target/product/x86/obj/kernel/ +MODULE_NAME :=wlan +endif + +ifeq ($(CONFIG_PLATFORM_ARM_PXA2XX), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +ARCH := arm +CROSS_COMPILE := arm-none-linux-gnueabi- +KVER := 2.6.34.1 +KSRC ?= /usr/src/linux-2.6.34.1 +endif + +ifeq ($(CONFIG_PLATFORM_ARM_S3C2K4), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +ARCH := arm +CROSS_COMPILE := arm-linux- +KVER := 2.6.24.7_$(ARCH) +KSRC := /usr/src/kernels/linux-$(KVER) +endif + +ifeq ($(CONFIG_PLATFORM_ARM_S3C6K4), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +ARCH := arm +CROSS_COMPILE := arm-none-linux-gnueabi- +KVER := 2.6.34.1 +KSRC ?= /usr/src/linux-2.6.34.1 +endif + +ifeq ($(CONFIG_PLATFORM_RTD2880B), y) +EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTD2880B +ARCH:= +CROSS_COMPILE:= +KVER:= +KSRC:= +endif + +ifeq ($(CONFIG_PLATFORM_MIPS_RMI), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +ARCH:=mips +CROSS_COMPILE:=mipsisa32r2-uclibc- +KVER:= +KSRC:= /root/work/kernel_realtek +endif + +ifeq ($(CONFIG_PLATFORM_MIPS_PLM), y) +EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN +ARCH:=mips +CROSS_COMPILE:=mipsisa32r2-uclibc- +KVER:= +KSRC:= /root/work/kernel_realtek +endif + +ifeq ($(CONFIG_PLATFORM_MSTAR389), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR389 +ARCH:=mips +CROSS_COMPILE:= mips-linux-gnu- +KVER:= 2.6.28.10 +KSRC:= /home/mstar/mstar_linux/2.6.28.9/ +endif + +ifeq ($(CONFIG_PLATFORM_MIPS_AR9132), y) +EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN +ARCH := mips +CROSS_COMPILE := mips-openwrt-linux- +KSRC := /home/alex/test_openwrt/tmp/linux-2.6.30.9 +endif + +ifeq ($(CONFIG_PLATFORM_DMP_PHILIPS), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM +ARCH := mips +#CROSS_COMPILE:=/usr/local/msdk-4.3.6-mips-EL-2.6.12.6-0.9.30.3/bin/mipsel-linux- +CROSS_COMPILE:=/usr/local/toolchain_mipsel/bin/mipsel-linux- +KSRC ?=/usr/local/Jupiter/linux-2.6.12 +endif + +ifeq ($(CONFIG_PLATFORM_RTK_DMP), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM -DCONFIG_WIRELESS_EXT +EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +ifeq ($(CONFIG_USB_HCI), y) +_PLATFORM_FILES += platform/platform_RTK_DMP_usb.o +endif +ARCH:=mips +CROSS_COMPILE:=mipsel-linux- +KVER:= +KSRC ?= /usr/src/DMP_Kernel/jupiter/linux-2.6.12 +endif + +ifeq ($(CONFIG_PLATFORM_MT53XX), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MT53XX +ARCH:= arm +CROSS_COMPILE:= arm11_mtk_le- +KVER:= 2.6.27 +KSRC?= /proj/mtk00802/BD_Compare/BDP/Dev/BDP_V301/BDP_Linux/linux-2.6.27 +endif + +ifeq ($(CONFIG_PLATFORM_ARM_MX51_241H), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_WISTRON_PLATFORM +ARCH := arm +CROSS_COMPILE := /opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi- +KVER := 2.6.31 +KSRC ?= /lib/modules/2.6.31-770-g0e46b52/source +endif + +ifeq ($(CONFIG_PLATFORM_FS_MX61), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +ARCH := arm +CROSS_COMPILE := /home/share/CusEnv/FreeScale/arm-eabi-4.4.3/bin/arm-eabi- +KSRC ?= /home/share/CusEnv/FreeScale/FS_kernel_env +endif + + + +ifeq ($(CONFIG_PLATFORM_ACTIONS_ATJ227X), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATJ227X +ARCH := mips +CROSS_COMPILE := /home/cnsd4/project/actions/tools-2.6.27/bin/mipsel-linux-gnu- +KVER := 2.6.27 +KSRC := /home/cnsd4/project/actions/linux-2.6.27.28 +endif + +ifeq ($(CONFIG_PLATFORM_TI_DM365), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_TI_DM365 +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX +EXTRA_CFLAGS += -DCONFIG_SINGLE_XMIT_BUF -DCONFIG_SINGLE_RECV_BUF +ARCH := arm +#CROSS_COMPILE := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/arm/v5t_le/bin/arm_v5t_le- +#KSRC := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365 +CROSS_COMPILE := /opt/montavista/pro5.0/devkit/arm/v5t_le/bin/arm-linux- +KSRC:= /home/vivotek/lsp/DM365/kernel_platform/kernel/linux-2.6.18 +KERNELOUTPUT := ${PRODUCTDIR}/tmp +KVER := 2.6.18 +endif + +ifeq ($(CONFIG_PLATFORM_MOZART), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MOZART +ARCH := arm +CROSS_COMPILE := /home/vivotek/lsp/mozart3v2/Mozart3e_Toolchain/build_arm_nofpu/usr/bin/arm-linux- +KVER := $(shell uname -r) +KSRC:= /opt/Vivotek/lsp/mozart3v2/kernel_platform/kernel/mozart_kernel-1.17 +KERNELOUTPUT := /home/pink/sample/ODM/IP8136W-VINT/tmp/kernel +endif + +ifeq ($(CONFIG_PLATFORM_TEGRA3_CARDHU), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +# default setting for Android 4.1, 4.2 +EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +ARCH := arm +CROSS_COMPILE := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- +KSRC := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/out/target/product/cardhu/obj/KERNEL +MODULE_NAME := wlan +endif + +ifeq ($(CONFIG_PLATFORM_TEGRA4_DALMORE), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +# default setting for Android 4.1, 4.2 +EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +ARCH := arm +CROSS_COMPILE := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi- +KSRC := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/out/target/product/dalmore/obj/KERNEL +MODULE_NAME := wlan +endif + +ifeq ($(CONFIG_PLATFORM_ARM_TCC8900), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +ARCH := arm +CROSS_COMPILE := /home/android_sdk/Telechips/SDK_2304_20110613/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- +KSRC := /home/android_sdk/Telechips/SDK_2304_20110613/kernel +MODULE_NAME := wlan +endif + +ifeq ($(CONFIG_PLATFORM_ARM_TCC8920), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +ARCH := arm +CROSS_COMPILE := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- +KSRC := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/kernel +MODULE_NAME := wlan +endif + +ifeq ($(CONFIG_PLATFORM_ARM_TCC8920_JB42), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +# default setting for Android 4.1, 4.2 +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +ARCH := arm +CROSS_COMPILE := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi- +KSRC := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/kernel +MODULE_NAME := wlan +endif + +ifeq ($(CONFIG_PLATFORM_ARM_RK2818), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS +ARCH := arm +CROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi- +KSRC := /usr/src/release_fae_version/kernel25_A7_281x +MODULE_NAME := wlan +endif + +ifeq ($(CONFIG_PLATFORM_ARM_RK3188), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS +# default setting for Android 4.1, 4.2, 4.3, 4.4 +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +# default setting for Power control +EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC +EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN +# default setting for Special function +ARCH := arm +CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3188/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi- +KSRC := /home/android_sdk/Rockchip/Rk3188/kernel +MODULE_NAME := wlan +endif + +ifeq ($(CONFIG_PLATFORM_ARM_RK3066), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_RK3066 +EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 +ifeq ($(CONFIG_SDIO_HCI), y) +EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN +endif +EXTRA_CFLAGS += -fno-pic +ARCH := arm +CROSS_COMPILE := /home/android_sdk/Rockchip/rk3066_20130607/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi- +#CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3066sdk/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi- +KSRC := /home/android_sdk/Rockchip/Rk3066sdk/kernel +MODULE_NAME :=wlan +endif + +ifeq ($(CONFIG_PLATFORM_ARM_URBETTER), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE +ARCH := arm +CROSS_COMPILE := /media/DATA-1/urbetter/arm-2009q3/bin/arm-none-linux-gnueabi- +KSRC := /media/DATA-1/urbetter/ics-urbetter/kernel +MODULE_NAME := wlan +endif + +ifeq ($(CONFIG_PLATFORM_ARM_TI_PANDA), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE +ARCH := arm +#CROSS_COMPILE := /media/DATA-1/aosp/ics-aosp_20111227/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- +#KSRC := /media/DATA-1/aosp/android-omap-panda-3.0_20120104 +CROSS_COMPILE := /media/DATA-1/android-4.0/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- +KSRC := /media/DATA-1/android-4.0/panda_kernel/omap +MODULE_NAME := wlan +endif + +ifeq ($(CONFIG_PLATFORM_MIPS_JZ4760), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_MINIMAL_MEMORY_USAGE +ARCH ?= mips +CROSS_COMPILE ?= /mnt/sdb5/Ingenic/Umido/mips-4.3/bin/mips-linux-gnu- +KSRC ?= /mnt/sdb5/Ingenic/Umido/kernel +endif + +ifeq ($(CONFIG_PLATFORM_SZEBOOK), y) +EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN +ARCH:=arm +CROSS_COMPILE:=/opt/crosstool2/bin/armeb-unknown-linux-gnueabi- +KVER:= 2.6.31.6 +KSRC:= ../code/linux-2.6.31.6-2020/ +endif + +#Add setting for MN10300 +ifeq ($(CONFIG_PLATFORM_MN10300), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MN10300 +ARCH := mn10300 +CROSS_COMPILE := mn10300-linux- +KVER := 2.6.32.2 +KSRC := /home/winuser/work/Plat_sLD2T_V3010/usr/src/linux-2.6.32.2 +INSTALL_PREFIX := +endif + + +ifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUNxI +# default setting for Android 4.1, 4.2 +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT + +EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +ifeq ($(CONFIG_USB_HCI), y) +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX +_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o +endif +ifeq ($(CONFIG_SDIO_HCI), y) +# default setting for A10-EVB mmc0 +#EXTRA_CFLAGS += -DCONFIG_WITS_EVB_V13 +_PLATFORM_FILES += platform/platform_ARM_SUNxI_sdio.o +endif + +ARCH := arm +#CROSS_COMPILE := arm-none-linux-gnueabi- +CROSS_COMPILE=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/buildroot/output/external-toolchain/bin/arm-none-linux-gnueabi- +KVER := 3.0.8 +#KSRC:= ../lichee/linux-3.0/ +KSRC=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/linux-3.0 +endif + +ifeq ($(CONFIG_PLATFORM_ARM_SUN6I), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN6I +EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT +# default setting for Android 4.1, 4.2, 4.3, 4.4 +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION + +EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +ifeq ($(CONFIG_USB_HCI), y) +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX +_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o +endif +ifeq ($(CONFIG_SDIO_HCI), y) +# default setting for A31-EVB mmc0 +EXTRA_CFLAGS += -DCONFIG_A31_EVB +_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o +endif + +ARCH := arm +#Android-JB42 +#CROSS_COMPILE := /home/android_sdk/Allwinner/a31/android-jb42/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi- +#KSRC :=/home/android_sdk/Allwinner/a31/android-jb42/lichee/linux-3.3 +#ifeq ($(CONFIG_USB_HCI), y) +#MODULE_NAME := 8188eu_sw +#endif +# ==== Cross compile setting for kitkat-a3x_v4.5 ===== +CROSS_COMPILE := /home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi- +KSRC :=/home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/linux-3.3 +endif + +ifeq ($(CONFIG_PLATFORM_ARM_SUN7I), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I +EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT +# default setting for Android 4.1, 4.2, 4.3, 4.4 +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION + +EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +ifeq ($(CONFIG_USB_HCI), y) +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX +_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o +endif +ifeq ($(CONFIG_SDIO_HCI), y) +_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o +endif + +ARCH := arm +# ===Cross compile setting for Android 4.2 SDK === +#CROSS_COMPILE := /home/android_sdk/Allwinner/a20_evb/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- +#KSRC := /home/android_sdk/Allwinner/a20_evb/lichee/linux-3.3 +# ==== Cross compile setting for Android 4.3 SDK ===== +#CROSS_COMPILE := /home/android_sdk/Allwinner/a20/android-jb43/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- +#KSRC := /home/android_sdk/Allwinner/a20/android-jb43/lichee/linux-3.4 +# ==== Cross compile setting for kitkat-a20_v4.4 ===== +CROSS_COMPILE := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- +KSRC := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/linux-3.4 +endif + +ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W3P1), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I +EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W3P1 +EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT +# default setting for Android 4.1, 4.2 +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT + +EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +ifeq ($(CONFIG_USB_HCI), y) +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX +_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o +endif +ifeq ($(CONFIG_SDIO_HCI), y) +_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o +endif + +ARCH := arm +# ===Cross compile setting for Android 4.2 SDK === +#CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-jb42/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- +#KSRC :=/home/android_sdk/Allwinner/a23/android-jb42/lichee/linux-3.4 +# ===Cross compile setting for Android 4.4 SDK === +CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-kk44/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- +KSRC :=/home/android_sdk/Allwinner/a23/android-kk44/lichee/linux-3.4 +endif + +ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W5P1), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I +EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W5P1 +EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT +# default setting for Android 4.1, 4.2 +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +# Enable this for Android 5.0 +EXTRA_CFLAGS += -DCONFIG_RADIO_WORK +EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +ifeq ($(CONFIG_USB_HCI), y) +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX +_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o +endif +ifeq ($(CONFIG_SDIO_HCI), y) +_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o +endif +ARCH := arm +# ===Cross compile setting for Android L SDK === +CROSS_COMPILE := /home/android_sdk/Allwinner/a33/android-L/lichee/out/sun8iw5p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- +KSRC :=/home/android_sdk/Allwinner/a33/android-L/lichee/linux-3.4 +endif +ifeq ($(CONFIG_PLATFORM_ACTIONS_ATV5201), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATV5201 +EXTRA_CFLAGS += -DCONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP +ARCH := mips +CROSS_COMPILE := mipsel-linux-gnu- +KVER := $(KERNEL_VER) +KSRC:= $(CFGDIR)/../../kernel/linux-$(KERNEL_VER) +endif + +ifeq ($(CONFIG_PLATFORM_ARM_RTD299X), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DUSB_XMITBUF_ALIGN_SZ=1024 -DUSB_PACKET_OFFSET_SZ=0 +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +ifeq ($(CONFIG_ANDROID), y) +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +# Enable this for Android 5.0 +EXTRA_CFLAGS += -DCONFIG_RADIO_WORK +endif +#ARCH, CROSS_COMPILE, KSRC,and MODDESTDIR are provided by external makefile +INSTALL_PREFIX := +endif + +ifeq ($(CONFIG_PLATFORM_HISILICON), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_HISILICON +ifeq ($(SUPPORT_CONCURRENT),y) +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +endif +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +ARCH := arm +ifeq ($(CROSS_COMPILE),) + CROSS_COMPILE = arm-hisiv200-linux- +endif +MODULE_NAME := rtl8192eu +ifeq ($(KSRC),) + KSRC := ../../../../../../kernel/linux-3.4.y +endif +endif # Platform setting ifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_6820), y) @@ -1201,16 +1596,30 @@ _PLATFORM_FILES += platform/platform_sprd_sdio.o endif endif -ifeq ($(CONFIG_PLATFORM_RTK129X), y) +ifeq ($(CONFIG_PLATFORM_ARM_WMT), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -EXTRA_CFLAGS += -DRTK_129X_PLATFORM +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +ifeq ($(CONFIG_SDIO_HCI), y) +_PLATFORM_FILES += platform/platform_ARM_WMT_sdio.o +endif +ARCH := arm +CROSS_COMPILE := /home/android_sdk/WonderMedia/wm8880-android4.4/toolchain/arm_201103_gcc4.5.2/mybin/arm_1103_le- +KSRC := /home/android_sdk/WonderMedia/wm8880-android4.4/kernel4.4/ +MODULE_NAME :=8189es_kk +endif + +ifeq ($(CONFIG_PLATFORM_RTK119X), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +#EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT # default setting for Android 4.1, 4.2 -#EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3 EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT -#EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION +#EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION -EXTRA_CFLAGS += -Wno-error=date-time #EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS ifeq ($(CONFIG_USB_HCI), y) @@ -1221,6 +1630,39 @@ ifeq ($(CONFIG_SDIO_HCI), y) _PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o endif +ARCH := arm + +# ==== Cross compile setting for Android 4.4 SDK ===== +#CROSS_COMPILE := arm-linux-gnueabihf- +KVER := 3.10.24 +#KSRC :=/home/android_sdk/Allwinner/a20/android-kitkat44/lichee/linux-3.4 +CROSS_COMPILE := /home/realtek/software_phoenix/phoenix/toolchain/usr/local/arm-2013.11/bin/arm-linux-gnueabihf- +KSRC := /home/realtek/software_phoenix/linux-kernel +MODULE_NAME := 8192eu + +endif + +ifeq ($(CONFIG_PLATFORM_RTK129X), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DRTK_129X_PLATFORM +EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT +# default setting for Android 4.1, 4.2 +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +#EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION +EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION +# Enable this for Android 5.0 +EXTRA_CFLAGS += -DCONFIG_RADIO_WORK +EXTRA_CFLAGS += -Wno-error=date-time +# default setting for Android 7.0 +ifeq ($(RTK_ANDROID_VERSION), nougat) +EXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1 +endif +#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS +ifeq ($(CONFIG_USB_HCI), y) +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX +endif + ARCH := arm64 # ==== Cross compile setting for Android 4.4 SDK ===== @@ -1231,6 +1673,45 @@ KSRC := $(LINUX_KERNEL_PATH) MODULE_NAME := 8822be endif +ifeq ($(CONFIG_PLATFORM_NOVATEK_NT72668), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_NOVATEK_NT72668 +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX +ARCH ?= arm +CROSS_COMPILE := arm-linux-gnueabihf- +KVER := 3.8.0 +KSRC := /Custom/Novatek/TCL/linux-3.8_header +#KSRC := $(KERNELDIR) +endif + +ifeq ($(CONFIG_PLATFORM_ARM_TCC8930_JB42), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +# default setting for Android 4.1, 4.2 +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +ARCH := arm +CROSS_COMPILE := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi- +KSRC := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/kernel +MODULE_NAME := wlan +endif + +ifeq ($(CONFIG_PLATFORM_RTL8197D), y) +EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTL8197D +export DIR_LINUX=$(shell pwd)/../SDK/rlxlinux-sdk321-v50/linux-2.6.30 +ARCH ?= rlx +CROSS_COMPILE:= $(DIR_LINUX)/../toolchain/rsdk-1.5.5-5281-EB-2.6.30-0.9.30.3-110714/bin/rsdk-linux- +KSRC := $(DIR_LINUX) +endif + +# ==== CENTOS ===== +CHECK_KVER := $(subst ., ,$(KVER)) +ifeq ($(findstring el7, $(CHECK_KVER)), el7) +EXTRA_CFLAGS += -DCONFIG_CENTOS_7 +endif +# ============== ifeq ($(CONFIG_MULTIDRV), y) @@ -1279,6 +1760,7 @@ rtk_core := core/rtw_cmd.o \ core/rtw_br_ext.o \ core/rtw_iol.o \ core/rtw_sreset.o \ + core/rtw_btcoex_wifionly.o \ core/rtw_btcoex.o \ core/rtw_beamforming.o \ core/rtw_odm.o \ @@ -1297,7 +1779,8 @@ $(MODULE_NAME)-$(CONFIG_WAPI_SUPPORT) += core/rtw_wapi.o \ $(MODULE_NAME)-y += $(_OS_INTFS_FILES) $(MODULE_NAME)-y += $(_HAL_INTFS_FILES) -$(MODULE_NAME)-y += $(_OUTSRC_FILES) +$(MODULE_NAME)-y += $(_PHYDM_FILES) +$(MODULE_NAME)-y += $(_BTC_FILES) $(MODULE_NAME)-y += $(_PLATFORM_FILES) $(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o @@ -1306,7 +1789,7 @@ ifeq ($(CONFIG_RTL8723B), y) $(MODULE_NAME)-$(CONFIG_MP_INCLUDED)+= core/rtw_bt_mp.o endif -obj-m := $(MODULE_NAME).o +obj-$(CONFIG_RTL8822BU) := $(MODULE_NAME).o else @@ -1315,7 +1798,7 @@ export CONFIG_RTL8822BU = m all: modules modules: - $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules + $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules strip: $(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded @@ -1336,10 +1819,8 @@ config_r: .PHONY: modules clean clean: - $(MAKE) -C $(KSRC) M=$(shell pwd) clean - cd hal/phydm/ ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko - cd hal/phydm/ ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko - cd hal/led ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko + #$(MAKE) -C $(KSRC) M=$(shell pwd) clean + cd hal ; rm -fr */*/*/*.mod.c */*/*/*.mod */*/*/*.o */*/*/.*.cmd */*/*/*.ko cd hal ; rm -fr */*/*.mod.c */*/*.mod */*/*.o */*/.*.cmd */*/*.ko cd hal ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko diff --git a/core/efuse/rtw_efuse.c b/core/efuse/rtw_efuse.c index 579b805..f3885e5 100644 --- a/core/efuse/rtw_efuse.c +++ b/core/efuse/rtw_efuse.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_EFUSE_C_ #include @@ -41,7 +36,7 @@ u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0}; u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0}; -u8 maskfileBuffer[32]; +u8 maskfileBuffer[64]; /*------------------------Define local variable------------------------------*/ BOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset) { @@ -113,10 +108,10 @@ BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset) return (IS_MASKED(8723D, _MUSB, Offset)) ? TRUE : FALSE; #endif - /*#if defined(CONFIG_RTL8821C) - if (IS_HARDWARE_TYPE_8821C(pAdapter)) - return (IS_MASKED(8821C,_MUSB,Offset)) ? TRUE : FALSE; - #endif*/ +#if defined(CONFIG_RTL8821C) + if (IS_HARDWARE_TYPE_8821CU(pAdapter)) + return (IS_MASKED(8821C, _MUSB, Offset)) ? TRUE : FALSE; +#endif #elif DEV_BUS_TYPE == RT_PCI_INTERFACE #if defined(CONFIG_RTL8188E) @@ -147,16 +142,40 @@ BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset) if (IS_HARDWARE_TYPE_8822B(pAdapter)) return (IS_MASKED(8822B, _MPCIE, Offset)) ? TRUE : FALSE; #endif +#if defined(CONFIG_RTL8821C) + if (IS_HARDWARE_TYPE_8821CE(pAdapter)) + return (IS_MASKED(8821C, _MPCIE, Offset)) ? TRUE : FALSE; +#endif #elif DEV_BUS_TYPE == RT_SDIO_INTERFACE #ifdef CONFIG_RTL8188E_SDIO if (IS_HARDWARE_TYPE_8188E(pAdapter)) return (IS_MASKED(8188E, _MSDIO, Offset)) ? TRUE : FALSE; #endif +#ifdef CONFIG_RTL8723B + if (IS_HARDWARE_TYPE_8723BS(pAdapter)) + return (IS_MASKED(8723B, _MSDIO, Offset)) ? TRUE : FALSE; +#endif #ifdef CONFIG_RTL8188F_SDIO if (IS_HARDWARE_TYPE_8188F(pAdapter)) return (IS_MASKED(8188F, _MSDIO, Offset)) ? TRUE : FALSE; #endif +#ifdef CONFIG_RTL8192E + if (IS_HARDWARE_TYPE_8192ES(pAdapter)) + return (IS_MASKED(8192E, _MSDIO, Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8821A) + if (IS_HARDWARE_TYPE_8821S(pAdapter)) + return (IS_MASKED(8821A, _MSDIO, Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8821C) + if (IS_HARDWARE_TYPE_8821CS(pAdapter)) + return (IS_MASKED(8821C, _MSDIO, Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8822B) + if (IS_HARDWARE_TYPE_8822B(pAdapter)) + return (IS_MASKED(8822B, _MSDIO, Offset)) ? TRUE : FALSE; +#endif #endif return FALSE; @@ -203,10 +222,12 @@ void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray) if (IS_HARDWARE_TYPE_8822B(pAdapter)) GET_MASK_ARRAY(8822B, _MUSB, pArray); #endif - /*#if defined(CONFIG_RTL8821C) - if (IS_HARDWARE_TYPE_8821C(pAdapter)) - GET_MASK_ARRAY(8821C,_MUSB,pArray); - #endif*/ +#if defined(CONFIG_RTL8821C) + if (IS_HARDWARE_TYPE_8821CU(pAdapter)) + GET_MASK_ARRAY(8821C, _MUSB, pArray); +#endif + + #elif DEV_BUS_TYPE == RT_PCI_INTERFACE #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(pAdapter)) @@ -236,15 +257,41 @@ void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray) if (IS_HARDWARE_TYPE_8822B(pAdapter)) GET_MASK_ARRAY(8822B, _MPCIE, pArray); #endif +#if defined(CONFIG_RTL8821C) + if (IS_HARDWARE_TYPE_8821CE(pAdapter)) + GET_MASK_ARRAY(8821C, _MPCIE, pArray); +#endif + + #elif DEV_BUS_TYPE == RT_SDIO_INTERFACE #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(pAdapter)) GET_MASK_ARRAY(8188E, _MSDIO, pArray); #endif +#if defined(CONFIG_RTL8723B) + if (IS_HARDWARE_TYPE_8723BS(pAdapter)) + GET_MASK_ARRAY(8723B, _MSDIO, pArray); +#endif #if defined(CONFIG_RTL8188F) if (IS_HARDWARE_TYPE_8188F(pAdapter)) GET_MASK_ARRAY(8188F, _MSDIO, pArray); #endif +#if defined(CONFIG_RTL8192E) + if (IS_HARDWARE_TYPE_8192ES(pAdapter)) + GET_MASK_ARRAY(8192E, _MSDIO, pArray); +#endif +#if defined(CONFIG_RTL8821A) + if (IS_HARDWARE_TYPE_8821S(pAdapter)) + GET_MASK_ARRAY(8821A, _MSDIO, pArray); +#endif +#if defined(CONFIG_RTL8821C) + if (IS_HARDWARE_TYPE_8821CS(pAdapter)) + GET_MASK_ARRAY(8821C , _MSDIO, pArray); +#endif +#if defined(CONFIG_RTL8822B) + if (IS_HARDWARE_TYPE_8822B(pAdapter)) + GET_MASK_ARRAY(8822B , _MSDIO, pArray); +#endif #endif /*#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE*/ } @@ -289,10 +336,12 @@ u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter) if (IS_HARDWARE_TYPE_8822B(pAdapter)) return GET_MASK_ARRAY_LEN(8822B, _MUSB); #endif - /*#if defined(CONFIG_RTL8821C) - if (IS_HARDWARE_TYPE_8821C(pAdapter)) - return GET_MASK_ARRAY_LEN(8821C,_MUSB); - #endif*/ +#if defined(CONFIG_RTL8821C) + if (IS_HARDWARE_TYPE_8821CU(pAdapter)) + return GET_MASK_ARRAY_LEN(8821C, _MUSB); +#endif + + #elif DEV_BUS_TYPE == RT_PCI_INTERFACE #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(pAdapter)) @@ -322,20 +371,350 @@ u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter) if (IS_HARDWARE_TYPE_8822B(pAdapter)) return GET_MASK_ARRAY_LEN(8822B, _MPCIE); #endif +#if defined(CONFIG_RTL8821C) + if (IS_HARDWARE_TYPE_8821CE(pAdapter)) + return GET_MASK_ARRAY_LEN(8821C, _MPCIE); +#endif + + #elif DEV_BUS_TYPE == RT_SDIO_INTERFACE #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(pAdapter)) return GET_MASK_ARRAY_LEN(8188E, _MSDIO); #endif +#if defined(CONFIG_RTL8723B) + if (IS_HARDWARE_TYPE_8723BS(pAdapter)) + return GET_MASK_ARRAY_LEN(8723B, _MSDIO); +#endif #if defined(CONFIG_RTL8188F) if (IS_HARDWARE_TYPE_8188F(pAdapter)) return GET_MASK_ARRAY_LEN(8188F, _MSDIO); #endif - +#if defined(CONFIG_RTL8192E) + if (IS_HARDWARE_TYPE_8192ES(pAdapter)) + return GET_MASK_ARRAY_LEN(8192E, _MSDIO); +#endif +#if defined(CONFIG_RTL8821A) + if (IS_HARDWARE_TYPE_8821S(pAdapter)) + return GET_MASK_ARRAY_LEN(8821A, _MSDIO); +#endif +#if defined(CONFIG_RTL8821C) + if (IS_HARDWARE_TYPE_8821CS(pAdapter)) + return GET_MASK_ARRAY_LEN(8821C, _MSDIO); +#endif +#if defined(CONFIG_RTL8822B) + if (IS_HARDWARE_TYPE_8822B(pAdapter)) + return GET_MASK_ARRAY_LEN(8822B, _MSDIO); +#endif #endif return 0; } +u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) +{ + u8 ret = _SUCCESS; + u16 mapLen = 0, i = 0; + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); + + ret = rtw_efuse_map_read(padapter, addr, cnts , data); + + if (padapter->registrypriv.boffefusemask == 0) { + + for (i = 0; i < cnts; i++) { + if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { + if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask.*/ + data[i] = 0xff; + } else { + /*RTW_INFO(" %s , data[%d] = %x\n", __func__, i, data[i]);*/ + if (efuse_IsMasked(padapter, addr + i)) { + data[i] = 0xff; + /*RTW_INFO(" %s ,mask data[%d] = %x\n", __func__, i, data[i]);*/ + } + } + } + + } + return ret; + +} + +/* *********************************************************** + * Efuse related code + * *********************************************************** */ +static u8 hal_EfuseSwitchToBank( + PADAPTER padapter, + u8 bank, + u8 bPseudoTest) +{ + u8 bRet = _FALSE; + u32 value32 = 0; +#ifdef HAL_EFUSE_MEMORY + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; +#endif + + + RTW_INFO("%s: Efuse switch bank to %d\n", __FUNCTION__, bank); + if (bPseudoTest) { +#ifdef HAL_EFUSE_MEMORY + pEfuseHal->fakeEfuseBank = bank; +#else + fakeEfuseBank = bank; +#endif + bRet = _TRUE; + } else { + value32 = rtw_read32(padapter, 0x34); + bRet = _TRUE; + switch (bank) { + case 0: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); + break; + case 1: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0); + break; + case 2: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1); + break; + case 3: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2); + break; + default: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); + bRet = _FALSE; + break; + } + rtw_write32(padapter, 0x34, value32); + } + + return bRet; +} + +void rtw_efuse_analyze(PADAPTER padapter, u8 Type, u8 Fake) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &(pHalData->EfuseHal); + u16 eFuse_Addr = 0; + u8 offset, wden; + u16 i, j; + u8 u1temp = 0; + u8 efuseHeader = 0, efuseExtHdr = 0, efuseData[EFUSE_MAX_WORD_UNIT*2] = {0}, dataCnt = 0; + u16 efuseHeader2Byte = 0; + u8 *eFuseWord = NULL;// [EFUSE_MAX_SECTION_NUM][EFUSE_MAX_WORD_UNIT]; + u8 offset_2_0 = 0; + u8 pgSectionCnt = 0; + u8 wd_cnt = 0; + u8 max_section = 64; + u16 mapLen = 0, maprawlen = 0; + boolean bExtHeader = _FALSE; + u8 efuseType = EFUSE_WIFI; + boolean bPseudoTest = _FALSE; + u8 bank = 0, startBank = 0, endBank = 1-1; + boolean bCheckNextBank = FALSE; + u8 protectBytesBank = 0; + u16 efuse_max = 0; + u8 ParseEfuseExtHdr, ParseEfuseHeader, ParseOffset, ParseWDEN, ParseOffset2_0; + + eFuseWord = rtw_zmalloc(EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2)); + + RTW_INFO("\n"); + if (Type == 0) { + if (Fake == 0) { + RTW_INFO("\n\tEFUSE_Analyze Wifi Content\n"); + efuseType = EFUSE_WIFI; + bPseudoTest = FALSE; + startBank = 0; + endBank = 0; + } else { + RTW_INFO("\n\tEFUSE_Analyze Wifi Pseudo Content\n"); + efuseType = EFUSE_WIFI; + bPseudoTest = TRUE; + startBank = 0; + endBank = 0; + } + } else { + if (Fake == 0) { + RTW_INFO("\n\tEFUSE_Analyze BT Content\n"); + efuseType = EFUSE_BT; + bPseudoTest = FALSE; + startBank = 1; + endBank = EFUSE_MAX_BANK - 1; + } else { + RTW_INFO("\n\tEFUSE_Analyze BT Pseudo Content\n"); + efuseType = EFUSE_BT; + bPseudoTest = TRUE; + startBank = 1; + endBank = EFUSE_MAX_BANK - 1; + if (IS_HARDWARE_TYPE_8821(padapter)) + endBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/ + } + } + + RTW_INFO("\n\r 1Byte header, [7:4]=offset, [3:0]=word enable\n"); + RTW_INFO("\n\r 2Byte header, header[7:5]=offset[2:0], header[4:0]=0x0F\n"); + RTW_INFO("\n\r 2Byte header, extHeader[7:4]=offset[6:3], extHeader[3:0]=word enable\n"); + + EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest); + EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAX_SECTION, (PVOID)&max_section, bPseudoTest); + EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_PROTECT_BYTES_BANK, (PVOID)&protectBytesBank, bPseudoTest); + EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, (PVOID)&efuse_max, bPseudoTest); + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&maprawlen, _FALSE); + + _rtw_memset(eFuseWord, 0xff, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2)); + _rtw_memset(pEfuseHal->fakeEfuseInitMap, 0xff, EFUSE_MAX_MAP_LEN); + + if (IS_HARDWARE_TYPE_8821(padapter)) + endBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/ + + for (bank = startBank; bank <= endBank; bank++) { + if (!hal_EfuseSwitchToBank(padapter, bank, bPseudoTest)) { + RTW_INFO("EFUSE_SwitchToBank() Fail!!\n"); + return; + } + + eFuse_Addr = bank * EFUSE_MAX_BANK_SIZE; + + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); + + if (efuseHeader == 0xFF && bank == startBank && Fake != TRUE) { + RTW_INFO("Non-PGed Efuse\n"); + return; + } + RTW_INFO("EFUSE_REAL_CONTENT_LEN = %d\n", maprawlen); + + while ((efuseHeader != 0xFF) && ((efuseType == EFUSE_WIFI && (eFuse_Addr < maprawlen)) || (efuseType == EFUSE_BT && (eFuse_Addr < (endBank + 1) * EFUSE_MAX_BANK_SIZE)))) { + + RTW_INFO("Analyzing: Offset: 0x%X\n", eFuse_Addr); + + /* Check PG header for section num.*/ + if (EXT_HEADER(efuseHeader)) { + bExtHeader = TRUE; + offset_2_0 = GET_HDR_OFFSET_2_0(efuseHeader); + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); + + if (efuseExtHdr != 0xff) { + if (ALL_WORDS_DISABLED(efuseExtHdr)) { + /* Read next pg header*/ + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); + continue; + } else { + offset = ((efuseExtHdr & 0xF0) >> 1) | offset_2_0; + wden = (efuseExtHdr & 0x0F); + efuseHeader2Byte = (efuseExtHdr<<8)|efuseHeader; + RTW_INFO("Find efuseHeader2Byte = 0x%04X, offset=%d, wden=0x%x\n", + efuseHeader2Byte, offset, wden); + } + } else { + RTW_INFO("Error, efuse[%d]=0xff, efuseExtHdr=0xff\n", eFuse_Addr-1); + break; + } + } else { + offset = ((efuseHeader >> 4) & 0x0f); + wden = (efuseHeader & 0x0f); + } + + _rtw_memset(efuseData, '\0', EFUSE_MAX_WORD_UNIT * 2); + dataCnt = 0; + + if (offset < max_section) { + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + /* Check word enable condition in the section */ + if (!(wden & (0x01<> 8; + ParseEfuseHeader = (efuseHeader2Byte & 0xff); + ParseOffset2_0 = GET_HDR_OFFSET_2_0(ParseEfuseHeader); + ParseOffset = ((ParseEfuseExtHdr & 0xF0) >> 1) | ParseOffset2_0; + ParseWDEN = (ParseEfuseExtHdr & 0x0F); + RTW_INFO("Header=0x%x, ExtHeader=0x%x, ", ParseEfuseHeader, ParseEfuseExtHdr); + } else { + ParseEfuseHeader = efuseHeader; + ParseOffset = ((ParseEfuseHeader >> 4) & 0x0f); + ParseWDEN = (ParseEfuseHeader & 0x0f); + RTW_INFO("Header=0x%x, ", ParseEfuseHeader); + } + RTW_INFO("offset=0x%x(%d), word enable=0x%x\n", ParseOffset, ParseOffset, ParseWDEN); + + wd_cnt = 0; + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + if (!(wden & (0x01 << i))) { + RTW_INFO("Map[ %02X ] = %02X %02X\n", ((offset * EFUSE_MAX_WORD_UNIT * 2) + (i * 2)), efuseData[wd_cnt * 2 + 0], efuseData[wd_cnt * 2 + 1]); + wd_cnt++; + } + } + + pgSectionCnt++; + bExtHeader = FALSE; + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); + if (efuseHeader == 0xFF) { + if ((eFuse_Addr + protectBytesBank) >= efuse_max) + bCheckNextBank = TRUE; + else + bCheckNextBank = FALSE; + } + } + if (!bCheckNextBank) { + RTW_INFO("Not need to check next bank, eFuse_Addr=%d, protectBytesBank=%d, efuse_max=%d\n", + eFuse_Addr, protectBytesBank, efuse_max); + break; + } + } + /* switch bank back to 0 for BT/wifi later use*/ + hal_EfuseSwitchToBank(padapter, 0, bPseudoTest); + + /* 3. Collect 16 sections and 4 word unit into Efuse map.*/ + for (i = 0; i < max_section; i++) { + for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) { + pEfuseHal->fakeEfuseInitMap[(i*8)+(j*2)] = (eFuseWord[(i*8)+(j*2)]); + pEfuseHal->fakeEfuseInitMap[(i*8)+((j*2)+1)] = (eFuseWord[(i*8)+((j*2)+1)]); + } + } + + RTW_INFO("\n\tEFUSE Analyze Map\n"); + i = 0; + j = 0; + + for (i = 0; i < mapLen; i++) { + if (i % 16 == 0) + RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i); + _RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s" + , pEfuseHal->fakeEfuseInitMap[i] + , ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? " " : " ") + ); + } + _RTW_PRINT_SEL(RTW_DBGDUMP, "\n"); + if (eFuseWord) + rtw_mfree((u8 *)eFuseWord, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2)); +} + #ifdef RTW_HALMAC #include "../../hal/hal_halmac.h" @@ -369,16 +748,45 @@ u16 efuse_GetMaxSize(PADAPTER adapter) return size; } -u8 efuse_bt_GetCurrentSize(PADAPTER adapter, u16 *size) +u16 efuse_GetavailableSize(PADAPTER adapter) { - *size = 0; + struct dvobj_priv *d; + u32 size = 0; + int err; - return _FAIL; + d = adapter_to_dvobj(adapter); + err = rtw_halmac_get_available_efuse_size(d, &size); + if (err) + return 0; + + return size; +} + + +u8 efuse_bt_GetCurrentSize(PADAPTER adapter, u16 *usesize) +{ + u8 *efuse_map; + + *usesize = 0; + efuse_map = rtw_malloc(EFUSE_BT_MAP_LEN); + if (efuse_map == NULL) { + RTW_DBG("%s: malloc FAIL\n", __FUNCTION__); + return _FAIL; + } + + /* for get bt phy efuse last use byte */ + hal_ReadEFuse_BT_logic_map(adapter, 0x00, EFUSE_BT_MAP_LEN, efuse_map); + *usesize = fakeBTEfuseUsedBytes; + + if (efuse_map) + rtw_mfree(efuse_map, EFUSE_BT_MAP_LEN); + + return _SUCCESS; } u16 efuse_bt_GetMaxSize(PADAPTER adapter) { - return 0; + return EFUSE_BT_REAL_CONTENT_LEN; } void EFUSE_GetEfuseDefinition(PADAPTER adapter, u8 efusetype, u8 type, void *out, BOOLEAN test) @@ -389,8 +797,8 @@ void EFUSE_GetEfuseDefinition(PADAPTER adapter, u8 efusetype, u8 type, void *out d = adapter_to_dvobj(adapter); - if (adapter->HalFunc.EFUSEGetEfuseDefinition) { - adapter->HalFunc.EFUSEGetEfuseDefinition(adapter, efusetype, type, out, test); + if (adapter->hal_func.EFUSEGetEfuseDefinition) { + adapter->hal_func.EFUSEGetEfuseDefinition(adapter, efusetype, type, out, test); return; } @@ -400,6 +808,21 @@ void EFUSE_GetEfuseDefinition(PADAPTER adapter, u8 efusetype, u8 type, void *out rtw_halmac_get_logical_efuse_size(d, &v32); *(u16 *)out = (u16)v32; return; + + case TYPE_EFUSE_REAL_CONTENT_LEN: + rtw_halmac_get_physical_efuse_size(d, &v32); + *(u16 *)out = (u16)v32; + return; + } + } else if (EFUSE_BT == efusetype) { + switch (type) { + case TYPE_EFUSE_MAP_LEN: + *(u16 *)out = EFUSE_BT_MAP_LEN; + return; + + case TYPE_EFUSE_REAL_CONTENT_LEN: + *(u16 *)out = EFUSE_BT_REAL_CONTENT_LEN; + return; } } } @@ -473,7 +896,7 @@ u8 rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data) d = adapter_to_dvobj(adapter); - size = EFUSE_BT_REAL_BANK_CONTENT_LEN; + size = EFUSE_BT_REAL_CONTENT_LEN; if ((addr + cnts) > size) return _FAIL; @@ -498,8 +921,9 @@ u8 rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data) } dump_buf(efuse + addr, cnts); - RTW_INFO("%s: rtw_halmac_read_bt_physical_efuse_map ok!\n", __FUNCTION__); _rtw_memcpy(data, efuse + addr, cnts); + + RTW_INFO("%s: rtw_halmac_read_bt_physical_efuse_map ok! data 0x%x\n", __FUNCTION__, *data); rtw_mfree(efuse, size); } } @@ -549,11 +973,6 @@ u8 rtw_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) return _SUCCESS; } -u8 rtw_efuse_mask_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) -{ - return rtw_efuse_map_read(adapter, addr, cnts, data); -} - u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) { struct dvobj_priv *d; @@ -587,7 +1006,11 @@ u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) RTW_INFO("Use mask Array Len: %d\n", mask_len); if (mask_len != 0) { - rtw_efuse_mask_array(adapter, mask_buf); + if (adapter->registrypriv.bFileMaskEfuse == _TRUE) + _rtw_memcpy(mask_buf, maskfileBuffer, mask_len); + else + rtw_efuse_mask_array(adapter, mask_buf); + err = rtw_halmac_write_logical_efuse_map(d, efuse, size, mask_buf, mask_len); } else err = rtw_halmac_write_logical_efuse_map(d, efuse, size, NULL, 0); @@ -654,7 +1077,7 @@ u8 rtw_BT_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) if (ret == _FAIL) goto exit; RTW_INFO("OFFSET\tVALUE(hex)\n"); - for (i = 0; i < 1024; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */ + for (i = 0; i < mapLen; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */ RTW_INFO("0x%03x\t", i); for (j = 0; j < 8; j++) RTW_INFO("%02X ", map[i + j]); @@ -679,13 +1102,13 @@ u8 rtw_BT_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) } if (word_en != 0xF) { + ret = EfusePgPacketWrite_BT(adapter, offset, word_en, newdata, _FALSE); RTW_INFO("offset=%x\n", offset); RTW_INFO("word_en=%x\n", word_en); RTW_INFO("%s: data=", __FUNCTION__); for (i = 0; i < PGPKT_DATA_SIZE; i++) RTW_INFO("0x%02X ", newdata[i]); RTW_INFO("\n"); - ret = EfusePgPacketWrite_BT(adapter, offset, word_en, newdata, _FALSE); if (ret == _FAIL) break; } @@ -725,17 +1148,17 @@ VOID hal_ReadEFuse_BT_logic_map( } efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN); - phyefuse = rtw_malloc(EFUSE_BT_REAL_BANK_CONTENT_LEN); - + phyefuse = rtw_malloc(EFUSE_BT_REAL_CONTENT_LEN); if (efuseTbl == NULL || phyefuse == NULL) { - RTW_INFO("%s: efuseTbl malloc fail!\n", __FUNCTION__); - return; + RTW_INFO("%s: efuseTbl or phyefuse malloc fail!\n", __FUNCTION__); + goto exit; } + /* 0xff will be efuse default value instead of 0x00. */ _rtw_memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN); - _rtw_memset(phyefuse, 0xFF, EFUSE_BT_REAL_BANK_CONTENT_LEN); + _rtw_memset(phyefuse, 0xFF, EFUSE_BT_REAL_CONTENT_LEN); - if(rtw_efuse_bt_access(padapter, _FALSE, 0, EFUSE_BT_REAL_BANK_CONTENT_LEN, phyefuse)) + if (rtw_efuse_bt_access(padapter, _FALSE, 0, EFUSE_BT_REAL_CONTENT_LEN, phyefuse)) dump_buf(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN); total = BANK_NUM; @@ -824,10 +1247,13 @@ VOID hal_ReadEFuse_BT_logic_map( efuse_usage = 100; fakeBTEfuseUsedBytes = used; + RTW_INFO("%s: BTEfuseUsed last Bytes = %#x\n", __FUNCTION__, fakeBTEfuseUsedBytes); exit: if (efuseTbl) rtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN); + if (phyefuse) + rtw_mfree(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN); } @@ -1085,36 +1511,198 @@ hal_EfusePgPacketWriteData( if (badworden != 0x0F) { RTW_INFO("%s: Fail!!\n", __FUNCTION__); return _FALSE; - } + } else + RTW_INFO("%s: OK!!\n", __FUNCTION__); - /* RTW_INFO("%s: ok\n", __FUNCTION__); */ return _TRUE; } -u8 EfusePgPacketWrite_BT( - PADAPTER pAdapter, - u8 offset, - u8 word_en, - u8 *pData, - u8 bPseudoTest) -{ - PGPKT_STRUCT targetPkt; - u16 startAddr = 0; - u8 efuseType = EFUSE_BT; - - hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); - if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) - return _FALSE; +#define EFUSE_CTRL 0x30 /* E-Fuse Control. */ - if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) - return _FALSE; +/* 11/16/2008 MH Read one byte from real Efuse. */ +u8 +efuse_OneByteRead( + IN PADAPTER pAdapter, + IN u16 addr, + IN u8 *data, + IN BOOLEAN bPseudoTest) +{ + u32 tmpidx = 0; + u8 bResult; + u8 readbyte; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) - return _FALSE; + if (IS_HARDWARE_TYPE_8723B(pAdapter) || + (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) || + (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id)) + ) { + /* <20130121, Kordan> For SMIC EFUSE specificatoin. */ + /* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */ + /* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */ + rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) & (~BIT11)); + } - return _TRUE; -} + /* -----------------e-fuse reg ctrl --------------------------------- */ + /* address */ + rtw_write8(pAdapter, EFUSE_CTRL + 1, (u8)(addr & 0xff)); + rtw_write8(pAdapter, EFUSE_CTRL + 2, ((u8)((addr >> 8) & 0x03)) | + (rtw_read8(pAdapter, EFUSE_CTRL + 2) & 0xFC)); + + /* rtw_write8(pAdapter, EFUSE_CTRL+3, 0x72); */ /* read cmd */ + /* Write bit 32 0 */ + readbyte = rtw_read8(pAdapter, EFUSE_CTRL + 3); + rtw_write8(pAdapter, EFUSE_CTRL + 3, (readbyte & 0x7f)); + + while (!(0x80 & rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 1000)) { + rtw_mdelay_os(1); + tmpidx++; + } + if (tmpidx < 100) { + *data = rtw_read8(pAdapter, EFUSE_CTRL); + bResult = _TRUE; + } else { + *data = 0xff; + bResult = _FALSE; + RTW_INFO("%s: [ERROR] addr=0x%x bResult=%d time out 1s !!!\n", __FUNCTION__, addr, bResult); + RTW_INFO("%s: [ERROR] EFUSE_CTRL =0x%08x !!!\n", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL)); + } + + return bResult; +} + + +static u16 +hal_EfuseGetCurrentSize_BT( + PADAPTER padapter, + u8 bPseudoTest) +{ +#ifdef HAL_EFUSE_MEMORY + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; +#endif + u16 btusedbytes; + u16 efuse_addr; + u8 bank, startBank; + u8 hoffset = 0, hworden = 0; + u8 efuse_data, word_cnts = 0; + u16 retU2 = 0; + u8 bContinual = _TRUE; + + + btusedbytes = fakeBTEfuseUsedBytes; + + efuse_addr = (u16)((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN)); + startBank = (u8)(1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN)); + + RTW_INFO("%s: start from bank=%d addr=0x%X\n", __FUNCTION__, startBank, efuse_addr); + retU2 = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK; + + for (bank = startBank; bank < 3; bank++) { + if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) { + RTW_ERR("%s: switch bank(%d) Fail!!\n", __FUNCTION__, bank); + /* bank = EFUSE_MAX_BANK; */ + break; + } + + /* only when bank is switched we have to reset the efuse_addr. */ + if (bank != startBank) + efuse_addr = 0; + + + while (AVAILABLE_EFUSE_ADDR(efuse_addr)) { + if (rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data) == _FALSE) { + RTW_ERR("%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __FUNCTION__, efuse_addr); + /* bank = EFUSE_MAX_BANK; */ + break; + } + RTW_INFO("%s: efuse_OneByteRead ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank); + + if (efuse_data == 0xFF) + break; + + if (EXT_HEADER(efuse_data)) { + hoffset = GET_HDR_OFFSET_2_0(efuse_data); + efuse_addr++; + rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data); + RTW_INFO("%s: efuse_OneByteRead EXT_HEADER ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank); + + if (ALL_WORDS_DISABLED(efuse_data)) { + efuse_addr++; + continue; + } + + /* hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */ + hoffset |= ((efuse_data & 0xF0) >> 1); + hworden = efuse_data & 0x0F; + } else { + hoffset = (efuse_data >> 4) & 0x0F; + hworden = efuse_data & 0x0F; + } + + RTW_INFO(FUNC_ADPT_FMT": Offset=%d Worden=%#X\n", + FUNC_ADPT_ARG(padapter), hoffset, hworden); + + word_cnts = Efuse_CalculateWordCnts(hworden); + /* read next header */ + efuse_addr += (word_cnts * 2) + 1; + } + /* Check if we need to check next bank efuse */ + if (efuse_addr < retU2) + break;/* don't need to check next bank. */ + } + retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr; + + fakeBTEfuseUsedBytes = retU2; + RTW_INFO("%s: CurrentSize=%d\n", __FUNCTION__, retU2); + return retU2; +} + + +static u8 +hal_BT_EfusePgCheckAvailableAddr( + PADAPTER pAdapter, + u8 bPseudoTest) +{ + u16 max_available = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK; + u16 current_size = 0; + + RTW_INFO("%s: max_available=%d\n", __FUNCTION__, max_available); + current_size = hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest); + if (current_size >= max_available) { + RTW_INFO("%s: Error!! current_size(%d)>max_available(%d)\n", __FUNCTION__, current_size, max_available); + return _FALSE; + } + return _TRUE; +} + +u8 EfusePgPacketWrite_BT( + PADAPTER pAdapter, + u8 offset, + u8 word_en, + u8 *pData, + u8 bPseudoTest) +{ + PGPKT_STRUCT targetPkt; + u16 startAddr = 0; + u8 efuseType = EFUSE_BT; + + if (!hal_BT_EfusePgCheckAvailableAddr(pAdapter, bPseudoTest)) + return _FALSE; + + hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); + + if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) + return _FALSE; + + if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) + return _FALSE; + + if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) + return _FALSE; + + return _TRUE; +} #else /* !RTW_HALMAC */ @@ -1123,6 +1711,48 @@ u8 EfusePgPacketWrite_BT( #define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ /* ------------------------------------------------------------------------------ */ +VOID efuse_PreUpdateAction( + PADAPTER pAdapter, + pu4Byte BackupRegs) +{ +#if defined(CONFIG_RTL8812A) + if (IS_HARDWARE_TYPE_8812AU(pAdapter)) { + /* <20131115, Kordan> Turn off Rx to prevent from being busy when writing the EFUSE. (Asked by Chunchu.)*/ + BackupRegs[0] = phy_query_mac_reg(pAdapter, REG_RCR, bMaskDWord); + BackupRegs[1] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord); + BackupRegs[2] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord); + BackupRegs[3] = phy_query_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord); + + PlatformEFIOWrite4Byte(pAdapter, REG_RCR, 0x1); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+1, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+2, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+3, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+4, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+5, 0); + + /* <20140410, Kordan> 0x11 = 0x4E, lower down LX_SPS0 voltage. (Asked by Chunchu)*/ + phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskByte1, 0x4E); + } +#endif +} + +VOID efuse_PostUpdateAction( + PADAPTER pAdapter, + pu4Byte BackupRegs) +{ +#if defined(CONFIG_RTL8812A) + if (IS_HARDWARE_TYPE_8812AU(pAdapter)) { + /* <20131115, Kordan> Turn on Rx and restore the registers. (Asked by Chunchu.)*/ + phy_set_mac_reg(pAdapter, REG_RCR, bMaskDWord, BackupRegs[0]); + phy_set_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord, BackupRegs[1]); + phy_set_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord, BackupRegs[2]); + phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord, BackupRegs[3]); + } +#endif +} + + BOOLEAN Efuse_Read1ByteFromFakeContent( IN PADAPTER pAdapter, @@ -1188,7 +1818,7 @@ Efuse_PowerSwitch( IN u8 bWrite, IN u8 PwrState) { - pAdapter->HalFunc.EfusePowerSwitch(pAdapter, bWrite, PwrState); + pAdapter->hal_func.EfusePowerSwitch(pAdapter, bWrite, PwrState); } VOID @@ -1197,8 +1827,8 @@ BTEfuse_PowerSwitch( IN u8 bWrite, IN u8 PwrState) { - if (pAdapter->HalFunc.BTEfusePowerSwitch) - pAdapter->HalFunc.BTEfusePowerSwitch(pAdapter, bWrite, PwrState); + if (pAdapter->hal_func.BTEfusePowerSwitch) + pAdapter->hal_func.BTEfusePowerSwitch(pAdapter, bWrite, PwrState); } /*----------------------------------------------------------------------------- @@ -1225,7 +1855,7 @@ Efuse_GetCurrentSize( { u16 ret = 0; - ret = pAdapter->HalFunc.EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest); + ret = pAdapter->hal_func.EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest); return ret; } @@ -1260,7 +1890,7 @@ ReadEFuseByte( if (IS_HARDWARE_TYPE_8723B(Adapter)) { /* <20130121, Kordan> For SMIC S55 EFUSE specificatoin. */ /* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */ - PHY_SetMacReg(Adapter, EFUSE_TEST, BIT11, 0); + phy_set_mac_reg(Adapter, EFUSE_TEST, BIT11, 0); } /* Write Address */ rtw_write8(Adapter, EFUSE_CTRL + 1, (_offset & 0xff)); @@ -1329,7 +1959,7 @@ efuse_ReadEFuse( IN BOOLEAN bPseudoTest ) { - Adapter->HalFunc.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest); + Adapter->hal_func.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest); } VOID @@ -1341,135 +1971,9 @@ EFUSE_GetEfuseDefinition( IN BOOLEAN bPseudoTest ) { - pAdapter->HalFunc.EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut, bPseudoTest); + pAdapter->hal_func.EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut, bPseudoTest); } -/*----------------------------------------------------------------------------- - * Function: EFUSE_Read1Byte - * - * Overview: Copy from WMAC fot EFUSE read 1 byte. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 09/23/2008 MHC Copy from WMAC. - * - *---------------------------------------------------------------------------*/ -u8 -EFUSE_Read1Byte( - IN PADAPTER Adapter, - IN u16 Address) -{ - u8 data; - u8 Bytetemp = {0x00}; - u8 temp = {0x00}; - u32 k = 0; - u16 contentLen = 0; - - EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI , TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&contentLen, _FALSE); - - if (Address < contentLen) { /* E-fuse 512Byte */ - /* Write E-fuse Register address bit0~7 */ - temp = Address & 0xFF; - rtw_write8(Adapter, EFUSE_CTRL + 1, temp); - Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 2); - /* Write E-fuse Register address bit8~9 */ - temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC); - rtw_write8(Adapter, EFUSE_CTRL + 2, temp); - - /* Write 0x30[31]=0 */ - Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3); - temp = Bytetemp & 0x7F; - rtw_write8(Adapter, EFUSE_CTRL + 3, temp); - - /* Wait Write-ready (0x30[31]=1) */ - Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3); - while (!(Bytetemp & 0x80)) { - Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3); - k++; - if (k == 1000) { - k = 0; - break; - } - } - data = rtw_read8(Adapter, EFUSE_CTRL); - return data; - } else - return 0xFF; - -} /* EFUSE_Read1Byte */ - -/*----------------------------------------------------------------------------- - * Function: EFUSE_Write1Byte - * - * Overview: Copy from WMAC fot EFUSE write 1 byte. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 09/23/2008 MHC Copy from WMAC. - * - *---------------------------------------------------------------------------*/ - -void -EFUSE_Write1Byte( - IN PADAPTER Adapter, - IN u16 Address, - IN u8 Value); -void -EFUSE_Write1Byte( - IN PADAPTER Adapter, - IN u16 Address, - IN u8 Value) -{ - u8 Bytetemp = {0x00}; - u8 temp = {0x00}; - u32 k = 0; - u16 contentLen = 0; - - /* RT_TRACE(COMP_EFUSE, DBG_LOUD, ("Addr=%x Data =%x\n", Address, Value)); */ - EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI , TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&contentLen, _FALSE); - - if (Address < contentLen) { /* E-fuse 512Byte */ - rtw_write8(Adapter, EFUSE_CTRL, Value); - - /* Write E-fuse Register address bit0~7 */ - temp = Address & 0xFF; - rtw_write8(Adapter, EFUSE_CTRL + 1, temp); - Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 2); - - /* Write E-fuse Register address bit8~9 */ - temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC); - rtw_write8(Adapter, EFUSE_CTRL + 2, temp); - - /* Write 0x30[31]=1 */ - Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3); - temp = Bytetemp | 0x80; - rtw_write8(Adapter, EFUSE_CTRL + 3, temp); - - /* Wait Write-ready (0x30[31]=0) */ - Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3); - while (Bytetemp & 0x80) { - Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3); - k++; - if (k == 100) { - k = 0; - break; - } - } - } -} /* EFUSE_Write1Byte */ - /* 11/16/2008 MH Read one byte from real Efuse. */ u8 @@ -1493,12 +1997,12 @@ efuse_OneByteRead( } if (IS_HARDWARE_TYPE_8723B(pAdapter) || - (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->VersionID))) || - (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->VersionID)) + (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) || + (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id)) ) { /* <20130121, Kordan> For SMIC EFUSE specificatoin. */ /* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */ - /* PHY_SetMacReg(pAdapter, 0x34, BIT11, 0); */ + /* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */ rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) & (~BIT11)); } @@ -1551,6 +2055,7 @@ efuse_OneByteWrite( return bResult; } + Efuse_PowerSwitch(pAdapter, _TRUE, _TRUE); /* -----------------e-fuse reg ctrl --------------------------------- */ /* address */ @@ -1563,17 +2068,19 @@ efuse_OneByteWrite( /* <20130227, Kordan> 8192E MP chip A-cut had better not set 0x34[11] until B-Cut. */ if (IS_HARDWARE_TYPE_8723B(pAdapter) || - (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->VersionID))) || - (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->VersionID)) + (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) || + (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id)) ) { /* <20130121, Kordan> For SMIC EFUSE specificatoin. */ /* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */ - /* PHY_SetMacReg(pAdapter, 0x34, BIT11, 1); */ + /* phy_set_mac_reg(pAdapter, 0x34, BIT11, 1); */ rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) | (BIT11)); rtw_write32(pAdapter, EFUSE_CTRL, 0x90600000 | ((addr << 8 | data))); } else rtw_write32(pAdapter, EFUSE_CTRL, efuseValue); + rtw_mdelay_os(1); + while ((0x80 & rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 100)) { rtw_mdelay_os(1); tmpidx++; @@ -1590,10 +2097,12 @@ efuse_OneByteWrite( /* disable Efuse program enable */ if (IS_HARDWARE_TYPE_8723B(pAdapter) || - (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->VersionID))) || - (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->VersionID)) + (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) || + (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id)) ) - PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT(11), 0); + phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT(11), 0); + + Efuse_PowerSwitch(pAdapter, _TRUE, _FALSE); return bResult; } @@ -1606,7 +2115,7 @@ Efuse_PgPacketRead(IN PADAPTER pAdapter, { int ret = 0; - ret = pAdapter->HalFunc.Efuse_PgPacketRead(pAdapter, offset, data, bPseudoTest); + ret = pAdapter->hal_func.Efuse_PgPacketRead(pAdapter, offset, data, bPseudoTest); return ret; } @@ -1620,7 +2129,7 @@ Efuse_PgPacketWrite(IN PADAPTER pAdapter, { int ret; - ret = pAdapter->HalFunc.Efuse_PgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest); + ret = pAdapter->hal_func.Efuse_PgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest); return ret; } @@ -1635,7 +2144,7 @@ Efuse_PgPacketWrite_BT(IN PADAPTER pAdapter, { int ret; - ret = pAdapter->HalFunc.Efuse_PgPacketWrite_BT(pAdapter, offset, word_en, data, bPseudoTest); + ret = pAdapter->hal_func.Efuse_PgPacketWrite_BT(pAdapter, offset, word_en, data, bPseudoTest); return ret; } @@ -1650,7 +2159,7 @@ Efuse_WordEnableDataWrite(IN PADAPTER pAdapter, { u8 ret = 0; - ret = pAdapter->HalFunc.Efuse_WordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest); + ret = pAdapter->hal_func.Efuse_WordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest); return ret; } @@ -1674,6 +2183,8 @@ u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 * u16 real_content_len = 0, max_available_size = 0; u8 res = _FAIL ; u8(*rw8)(PADAPTER, u16, u8 *); + u32 backupRegs[4] = {0}; + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&real_content_len, _FALSE); EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); @@ -1688,6 +2199,8 @@ u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 * } else rw8 = &efuse_read8; + efuse_PreUpdateAction(padapter, backupRegs); + Efuse_PowerSwitch(padapter, bWrite, _TRUE); /* e-fuse one byte read / write */ @@ -1704,6 +2217,8 @@ u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 * Efuse_PowerSwitch(padapter, bWrite, _FALSE); + efuse_PostUpdateAction(padapter, backupRegs); + return res; } /* ------------------------------------------------------------------------------ */ @@ -1792,12 +2307,16 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) u8 offset, word_en; u8 *map; u8 newdata[PGPKT_DATA_SIZE]; - s32 i, j, idx; + s32 i, j, idx, chk_total_byte; u8 ret = _SUCCESS; - u16 mapLen = 0; + u16 mapLen = 0, startAddr = 0, efuse_max_available_len = 0; + u32 backupRegs[4] = {0}; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, _FALSE); if ((addr + cnts) > mapLen) return _FAIL; @@ -1827,7 +2346,49 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) RTW_INFO("%s , data[%d] = %x, map[addr+i]= %x\n", __func__, i, data[i], map[addr + i]); } } - Efuse_PowerSwitch(padapter, _TRUE, _TRUE); + /*Efuse_PowerSwitch(padapter, _TRUE, _TRUE);*/ + + chk_total_byte = 0; + idx = 0; + offset = (addr >> 3); + + while (idx < cnts) { + word_en = 0xF; + j = (addr + idx) & 0x7; + for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) { + if (data[idx] != map[addr + idx]) + word_en &= ~BIT(i >> 1); + } + + if (word_en != 0xF) { + chk_total_byte += Efuse_CalculateWordCnts(word_en) * 2; + + if (offset >= EFUSE_MAX_SECTION_BASE) /* Over EFUSE_MAX_SECTION 16 for 2 ByteHeader */ + chk_total_byte += 2; + else + chk_total_byte += 1; + } + + offset++; + } + + RTW_INFO("Total PG bytes Count = %d\n", chk_total_byte); + rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr); + + if (startAddr == 0) { + startAddr = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE); + RTW_INFO("%s: Efuse_GetCurrentSize startAddr=%#X\n", __func__, startAddr); + } + RTW_DBG("%s: startAddr=%#X\n", __func__, startAddr); + + if ((startAddr + chk_total_byte) >= efuse_max_available_len) { + RTW_INFO("%s: startAddr(0x%X) + PG data len %d >= efuse_max_available_len(0x%X)\n", + __func__, startAddr, chk_total_byte, efuse_max_available_len); + ret = _FAIL; + goto exit; + } + + efuse_PreUpdateAction(padapter, backupRegs); idx = 0; offset = (addr >> 3); @@ -1841,7 +2402,7 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) newdata[i] = data[idx]; #ifdef CONFIG_RTL8723B if (addr + idx == 0x8) { - if (IS_C_CUT(pHalData->VersionID) || IS_B_CUT(pHalData->VersionID)) { + if (IS_C_CUT(pHalData->version_id) || IS_B_CUT(pHalData->version_id)) { if (pHalData->adjuseVoltageVal == 6) { newdata[i] = map[addr + idx]; RTW_INFO(" %s ,\n adjuseVoltageVal = %d ,newdata[%d] = %x\n", __func__, pHalData->adjuseVoltageVal, i, newdata[i]); @@ -1866,7 +2427,9 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) offset++; } - Efuse_PowerSwitch(padapter, _TRUE, _FALSE); + /*Efuse_PowerSwitch(padapter, _TRUE, _FALSE);*/ + + efuse_PostUpdateAction(padapter, backupRegs); exit: @@ -1875,34 +2438,6 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) return ret; } -u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) -{ - u8 ret = _SUCCESS; - u16 mapLen = 0, i = 0; - - EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); - - ret = rtw_efuse_map_read(padapter, addr, cnts , data); - - if (padapter->registrypriv.boffefusemask == 0) { - - for (i = 0; i < cnts; i++) { - if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { - if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask.*/ - data[i] = 0xff; - } else { - /*RTW_INFO(" %s , data[%d] = %x\n", __func__, i, data[i]);*/ - if (efuse_IsMasked(padapter, addr + i)) { - data[i] = 0xff; - /*RTW_INFO(" %s ,mask data[%d] = %x\n", __func__, i, data[i]);*/ - } - } - } - - } - return ret; - -} u8 rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) { @@ -2025,67 +2560,6 @@ Efuse_ReadAllMap( Efuse_PowerSwitch(pAdapter, _FALSE, _FALSE); } -/*----------------------------------------------------------------------------- - * Function: efuse_ShadowRead1Byte - * efuse_ShadowRead2Byte - * efuse_ShadowRead4Byte - * - * Overview: Read from efuse init map by one/two/four bytes !!!!! - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 11/12/2008 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -static VOID -efuse_ShadowRead1Byte( - IN PADAPTER pAdapter, - IN u16 Offset, - IN OUT u8 *Value) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - - *Value = pHalData->efuse_eeprom_data[Offset]; - -} /* EFUSE_ShadowRead1Byte */ - -/* ---------------Read Two Bytes */ -static VOID -efuse_ShadowRead2Byte( - IN PADAPTER pAdapter, - IN u16 Offset, - IN OUT u16 *Value) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - - *Value = pHalData->efuse_eeprom_data[Offset]; - *Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8; - -} /* EFUSE_ShadowRead2Byte */ - -/* ---------------Read Four Bytes */ -static VOID -efuse_ShadowRead4Byte( - IN PADAPTER pAdapter, - IN u16 Offset, - IN OUT u32 *Value) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - - *Value = pHalData->efuse_eeprom_data[Offset]; - *Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8; - *Value |= pHalData->efuse_eeprom_data[Offset + 2] << 16; - *Value |= pHalData->efuse_eeprom_data[Offset + 3] << 24; - -} /* efuse_ShadowRead4Byte */ - - /*----------------------------------------------------------------------------- * Function: efuse_ShadowWrite1Byte * efuse_ShadowWrite2Byte @@ -2156,38 +2630,6 @@ efuse_ShadowWrite4Byte( } /* efuse_ShadowWrite1Byte */ -/*----------------------------------------------------------------------------- - * Function: EFUSE_ShadowRead - * - * Overview: Read from efuse init map !!!!! - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 11/12/2008 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -void -EFUSE_ShadowRead( - IN PADAPTER pAdapter, - IN u8 Type, - IN u16 Offset, - IN OUT u32 *Value) -{ - if (Type == 1) - efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value); - else if (Type == 2) - efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value); - else if (Type == 4) - efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value); - -} /* EFUSE_ShadowRead */ - /*----------------------------------------------------------------------------- * Function: EFUSE_ShadowWrite * @@ -2259,6 +2701,87 @@ Efuse_InitSomeVar( _rtw_memset((PVOID)&fakeBTEfuseModifiedMap[0], 0xff, EFUSE_BT_MAX_MAP_LEN); } #endif /* !RTW_HALMAC */ +/*----------------------------------------------------------------------------- + * Function: efuse_ShadowRead1Byte + * efuse_ShadowRead2Byte + * efuse_ShadowRead4Byte + * + * Overview: Read from efuse init map by one/two/four bytes !!!!! + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +static VOID +efuse_ShadowRead1Byte( + IN PADAPTER pAdapter, + IN u16 Offset, + IN OUT u8 *Value) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + *Value = pHalData->efuse_eeprom_data[Offset]; + +} /* EFUSE_ShadowRead1Byte */ + +/* ---------------Read Two Bytes */ +static VOID +efuse_ShadowRead2Byte( + IN PADAPTER pAdapter, + IN u16 Offset, + IN OUT u16 *Value) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + *Value = pHalData->efuse_eeprom_data[Offset]; + *Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8; + +} /* EFUSE_ShadowRead2Byte */ + +/* ---------------Read Four Bytes */ +static VOID +efuse_ShadowRead4Byte( + IN PADAPTER pAdapter, + IN u16 Offset, + IN OUT u32 *Value) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + *Value = pHalData->efuse_eeprom_data[Offset]; + *Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8; + *Value |= pHalData->efuse_eeprom_data[Offset + 2] << 16; + *Value |= pHalData->efuse_eeprom_data[Offset + 3] << 24; + +} /* efuse_ShadowRead4Byte */ + +/*----------------------------------------------------------------------------- + * Function: EFUSE_ShadowRead + * + * Overview: Read from pHalData->efuse_eeprom_data + *---------------------------------------------------------------------------*/ +void +EFUSE_ShadowRead( + IN PADAPTER pAdapter, + IN u8 Type, + IN u16 Offset, + IN OUT u32 *Value) +{ + if (Type == 1) + efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value); + else if (Type == 2) + efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value); + else if (Type == 4) + efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value); + +} /* EFUSE_ShadowRead */ + /* 11/16/2008 MH Add description. Get current efuse area enabled word!!. */ u8 Efuse_CalculateWordCnts(IN u8 word_en) @@ -2482,7 +3005,7 @@ int retriveAdaptorInfoFile(char *path, u8 *efuse_data) u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len) { char *ptmpbuf = NULL, *ptr; - unsigned long val16; + u8 val8; u32 count, i, j; int err; u32 bufsize = 4096; @@ -2518,11 +3041,11 @@ u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len) ptr = &ptmpbuf[count-1]; } - err = kstrtoul(&ptmpbuf[i], 16, &val16); - if (err) { + err = sscanf(&ptmpbuf[i], "%hhx", &val8); + if (err != 1) { RTW_WARN("Something wrong to parse efuse file, string=%s\n", &ptmpbuf[i]); } else { - buf[j] = (u8)val16; + buf[j] = val8; RTW_DBG("i=%d, j=%d, 0x%02x\n", i, j, buf[j]); j++; } @@ -2536,141 +3059,143 @@ u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len) } #ifdef CONFIG_EFUSE_CONFIG_FILE -u32 rtw_read_efuse_from_file(const char *path, u8 *buf) +u32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size) { u32 i; + u8 c; u8 temp[3]; + u8 temp_i; + u8 end = _FALSE; u32 ret = _FAIL; - struct file *fp; - mm_segment_t fs; - loff_t pos = 0; - - fp = filp_open(path, O_RDONLY, 0); - if (fp == NULL || IS_ERR(fp)) { - if (fp != NULL) - RTW_PRINT("%s open %s fail, err:%ld\n" - , __func__, path, PTR_ERR(fp)); - else - RTW_PRINT("%s open %s fail, fp is NULL\n" - , __func__, path); + u8 *file_data = NULL; + u32 file_size, read_size, pos = 0; + u8 *map = NULL; + if (rtw_is_file_readable_with_size(path, &file_size) != _TRUE) { + RTW_PRINT("%s %s is not readable\n", __func__, path); goto exit; } - temp[2] = 0; /* add end of string '\0' */ + file_data = rtw_vmalloc(file_size); + if (!file_data) { + RTW_ERR("%s rtw_vmalloc(%d) fail\n", __func__, file_size); + goto exit; + } + + read_size = rtw_retrieve_from_file(path, file_data, file_size); + if (read_size == 0) { + RTW_ERR("%s read from %s fail\n", __func__, path); + goto exit; + } + + map = rtw_vmalloc(map_size); + if (!map) { + RTW_ERR("%s rtw_vmalloc(%d) fail\n", __func__, map_size); + goto exit; + } + _rtw_memset(map, 0xff, map_size); - fs = get_fs(); - set_fs(KERNEL_DS); + temp[2] = 0; /* end of string '\0' */ + + for (i = 0 ; i < map_size ; i++) { + temp_i = 0; + + while (1) { + if (pos >= read_size) { + end = _TRUE; + break; + } + c = file_data[pos++]; + + /* bypass spece or eol or null before first hex digit */ + if (temp_i == 0 && (is_eol(c) == _TRUE || is_space(c) == _TRUE || is_null(c) == _TRUE)) + continue; - for (i = 0 ; i < HWSET_MAX_SIZE ; i++) { - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) - kernel_read(fp, temp, 2, &pos); - #else - vfs_read(fp, temp, 2, &pos); - #endif - if (sscanf(temp, "%hhx", &buf[i]) != 1) { - if (0) - RTW_ERR("%s sscanf fail\n", __func__); - buf[i] = 0xFF; + if (IsHexDigit(c) == _FALSE) { + RTW_ERR("%s invalid 8-bit hex format for offset:0x%03x\n", __func__, i); + goto exit; + } + + temp[temp_i++] = c; + + if (temp_i == 2) { + /* parse value */ + if (sscanf(temp, "%hhx", &map[i]) != 1) { + RTW_ERR("%s sscanf fail for offset:0x%03x\n", __func__, i); + goto exit; + } + break; + } } - if ((i % EFUSE_FILE_COLUMN_NUM) == (EFUSE_FILE_COLUMN_NUM - 1)) { - /* Filter the lates space char. */ - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) - kernel_read(fp, temp, 1, &pos); - #else - vfs_read(fp, temp, 1, &pos); - #endif - if (strchr(temp, ' ') == NULL) { - pos--; - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) - kernel_read(fp, temp, 2, &pos); - #else - vfs_read(fp, temp, 2, &pos); - #endif + + if (end == _TRUE) { + if (temp_i != 0) { + RTW_ERR("%s incomplete 8-bit hex format for offset:0x%03x\n", __func__, i); + goto exit; } - } else { - pos += 1; /* Filter the space character */ + break; } } - set_fs(fs); - - RTW_PRINT("efuse file: %s\n", path); -#ifdef CONFIG_RTW_DEBUG - for (i = 0; i < HWSET_MAX_SIZE; i++) { - if (i % 16 == 0) - RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i); + RTW_PRINT("efuse file:%s, 0x%03x byte content read\n", path, i); - _RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s" - , buf[i] - , ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? " " : " ") - ); - } - _RTW_PRINT_SEL(RTW_DBGDUMP, "\n"); -#endif + _rtw_memcpy(buf, map, map_size); ret = _SUCCESS; exit: + if (file_data) + rtw_vmfree(file_data, file_size); + if (map) + rtw_vmfree(map, map_size); + return ret; } u32 rtw_read_macaddr_from_file(const char *path, u8 *buf) { - struct file *fp; - mm_segment_t fs; - loff_t pos = 0; - - u8 source_addr[18]; - u8 *head, *end; - int i; + u32 i; + u8 temp[3]; u32 ret = _FAIL; - _rtw_memset(source_addr, 0, 18); - - fp = filp_open(path, O_RDONLY, 0); - if (fp == NULL || IS_ERR(fp)) { - if (fp != NULL) - RTW_PRINT("%s open %s fail, err:%ld\n" - , __func__, path, PTR_ERR(fp)); - else - RTW_PRINT("%s open %s fail, fp is NULL\n" - , __func__, path); + u8 file_data[17]; + u32 read_size, pos = 0; + u8 addr[ETH_ALEN]; + if (rtw_is_file_readable(path) != _TRUE) { + RTW_PRINT("%s %s is not readable\n", __func__, path); goto exit; } - fs = get_fs(); - set_fs(KERNEL_DS); - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) - kernel_read(fp, source_addr, 18, &pos); - #else - vfs_read(fp, source_addr, 18, &pos); - #endif - source_addr[17] = ':'; + read_size = rtw_retrieve_from_file(path, file_data, 17); + if (read_size != 17) { + RTW_ERR("%s read from %s fail\n", __func__, path); + goto exit; + } - head = end = source_addr; - for (i = 0; i < ETH_ALEN; i++) { - while (end && (*end != ':')) - end++; + temp[2] = 0; /* end of string '\0' */ - if (end && (*end == ':')) - *end = '\0'; + for (i = 0 ; i < ETH_ALEN ; i++) { + if (IsHexDigit(file_data[i * 3]) == _FALSE || IsHexDigit(file_data[i * 3 + 1]) == _FALSE) { + RTW_ERR("%s invalid 8-bit hex format for address offset:%u\n", __func__, i); + goto exit; + } - if (sscanf(head, "%hhx", &buf[i]) != 1) { - if (0) - RTW_ERR("%s sscanf fail\n", __func__); - buf[i] = 0xFF; + if (i < ETH_ALEN - 1 && file_data[i * 3 + 2] != ':') { + RTW_ERR("%s invalid separator after address offset:%u\n", __func__, i); + goto exit; } - if (end) { - end++; - head = end; + temp[0] = file_data[i * 3]; + temp[1] = file_data[i * 3 + 1]; + if (sscanf(temp, "%hhx", &addr[i]) != 1) { + RTW_ERR("%s sscanf fail for address offset:0x%03x\n", __func__, i); + goto exit; } } - set_fs(fs); + _rtw_memcpy(buf, addr, ETH_ALEN); RTW_PRINT("wifi_mac file: %s\n", path); #ifdef CONFIG_RTW_DEBUG diff --git a/core/rtw_ap.c b/core/rtw_ap.c index d697688..99425b2 100644 --- a/core/rtw_ap.c +++ b/core/rtw_ap.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,16 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_AP_C_ #include - +#include #ifdef CONFIG_AP_MODE @@ -275,7 +270,7 @@ u8 chk_sta_is_alive(struct sta_info *psta) #ifdef DBG_EXPIRATION_CHK RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", expire_to:%u, %s%ssq_len:%u\n" , MAC_ARG(psta->hwaddr) - , psta->rssi_stat.UndecoratedSmoothedPWDB + , psta->rssi_stat.undecorated_smoothed_pwdb /* , STA_RX_PKTS_ARG(psta) */ , STA_RX_PKTS_DIFF_ARG(psta) , psta->expire_to @@ -540,9 +535,15 @@ void expire_timeout_chk(_adapter *padapter) #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK if (chk_alive_num) { - u8 backup_oper_channel = 0, switch_channel = _TRUE; + u8 backup_ch = 0, backup_bw = 0, backup_offset = 0; + u8 union_ch = 0, union_bw, union_offset; + u8 switch_channel = _TRUE; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) + || pmlmeext->cur_channel != union_ch) + goto bypass_active_keep_alive; + #ifdef CONFIG_MCC_MODE if (MCC_EN(padapter)) { /* driver doesn't switch channel under MCC */ @@ -551,11 +552,11 @@ void expire_timeout_chk(_adapter *padapter) } #endif /* switch to correct channel of current network before issue keep-alive frames */ - if (switch_channel) { - if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { - backup_oper_channel = rtw_get_oper_ch(padapter); - SelectChannel(padapter, pmlmeext->cur_channel); - } + if (switch_channel == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { + backup_ch = rtw_get_oper_ch(padapter); + backup_bw = rtw_get_oper_bw(padapter); + backup_offset = rtw_get_oper_choffset(padapter); + set_channel_bwmode(padapter, union_ch, union_offset, union_bw); } /* issue null data to check sta alive*/ @@ -601,21 +602,23 @@ void expire_timeout_chk(_adapter *padapter) } - if (switch_channel) { - if (backup_oper_channel > 0) /* back to the original operation channel */ - SelectChannel(padapter, backup_oper_channel); - } + /* back to the original operation channel */ + if (switch_channel && backup_ch > 0) + set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw); + +bypass_active_keep_alive: + ; } #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); } -void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level) +void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level, u8 is_update_bw) { int i; u8 rf_type; - unsigned char sta_band = 0, shortGIrate = _FALSE; + unsigned char sta_band = 0; u64 tx_ra_bitmap = 0; struct ht_priv *psta_ht = NULL; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -631,112 +634,9 @@ void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level) if (!(psta->state & _FW_LINKED)) return; -#if 0/* gtest */ - if (get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R) { - /* is this a 2r STA? */ - if ((pstat->tx_ra_bitmap & 0x0ff00000) != 0 && !(priv->pshare->has_2r_sta & BIT(pstat->aid))) { - priv->pshare->has_2r_sta |= BIT(pstat->aid); - if (rtw_read16(padapter, 0x102501f6) != 0xffff) { - rtw_write16(padapter, 0x102501f6, 0xffff); - reset_1r_sta_RA(priv, 0xffff); - Switch_1SS_Antenna(priv, 3); - } - } else { /* bg or 1R STA? */ - if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len && priv->pshare->has_2r_sta == 0) { - if (rtw_read16(padapter, 0x102501f6) != 0x7777) { - /* MCS7 SGI */ - rtw_write16(padapter, 0x102501f6, 0x7777); - reset_1r_sta_RA(priv, 0x7777); - Switch_1SS_Antenna(priv, 2); - } - } - } - - } - - if ((pstat->rssi_level < 1) || (pstat->rssi_level > 3)) { - if (pstat->rssi >= priv->pshare->rf_ft_var.raGoDownUpper) - pstat->rssi_level = 1; - else if ((pstat->rssi >= priv->pshare->rf_ft_var.raGoDown20MLower) || - ((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) && - (pstat->rssi >= priv->pshare->rf_ft_var.raGoDown40MLower) && - (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_)))) - pstat->rssi_level = 2; - else - pstat->rssi_level = 3; - } - - /* rate adaptive by rssi */ - if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len) { - if ((get_rf_mimo_mode(priv) == MIMO_1T2R) || (get_rf_mimo_mode(priv) == MIMO_1T1R)) { - switch (pstat->rssi_level) { - case 1: - pstat->tx_ra_bitmap &= 0x100f0000; - break; - case 2: - pstat->tx_ra_bitmap &= 0x100ff000; - break; - case 3: - if (priv->pshare->is_40m_bw) - pstat->tx_ra_bitmap &= 0x100ff005; - else - pstat->tx_ra_bitmap &= 0x100ff001; - - break; - } - } else { - switch (pstat->rssi_level) { - case 1: - pstat->tx_ra_bitmap &= 0x1f0f0000; - break; - case 2: - pstat->tx_ra_bitmap &= 0x1f0ff000; - break; - case 3: - if (priv->pshare->is_40m_bw) - pstat->tx_ra_bitmap &= 0x000ff005; - else - pstat->tx_ra_bitmap &= 0x000ff001; - - break; - } - - /* Don't need to mask high rates due to new rate adaptive parameters */ - /* if (pstat->is_broadcom_sta) */ /* use MCS12 as the highest rate vs. Broadcom sta */ - /* pstat->tx_ra_bitmap &= 0x81ffffff; */ - - /* NIC driver will report not supporting MCS15 and MCS14 in asoc req */ - /* if (pstat->is_rtl8190_sta && !pstat->is_2t_mimo_sta) */ - /* pstat->tx_ra_bitmap &= 0x83ffffff; */ /* if Realtek 1x2 sta, don't use MCS15 and MCS14 */ - } - } else if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) && isErpSta(pstat)) { - switch (pstat->rssi_level) { - case 1: - pstat->tx_ra_bitmap &= 0x00000f00; - break; - case 2: - pstat->tx_ra_bitmap &= 0x00000ff0; - break; - case 3: - pstat->tx_ra_bitmap &= 0x00000ff5; - break; - } - } else - pstat->tx_ra_bitmap &= 0x0000000d; - - /* disable tx short GI when station cannot rx MCS15(AP is 2T2R) */ - /* disable tx short GI when station cannot rx MCS7 (AP is 1T2R or 1T1R) */ - /* if there is only 1r STA and we are 2T2R, DO NOT mask SGI rate */ - if ((!(pstat->tx_ra_bitmap & 0x8000000) && (priv->pshare->has_2r_sta > 0) && (get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R)) || - (!(pstat->tx_ra_bitmap & 0x80000) && (get_rf_mimo_mode(padapter) != RTL8712_RF_2T2R))) - pstat->tx_ra_bitmap &= ~BIT(28); -#endif - rtw_hal_update_sta_rate_mask(padapter, psta); tx_ra_bitmap = psta->ra_mask; - shortGIrate = query_ra_short_GI(psta); - if (pcur_network->Configuration.DSConfig > 14) { if (tx_ra_bitmap & 0xffff000) @@ -766,17 +666,10 @@ void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level) psta->raid = rtw_hal_networktype_to_raid(padapter, psta); if (psta->aid < NUM_STA) { - u8 arg[4] = {0}; + RTW_INFO("%s=> mac_id:%d , raid:%d, tx_ra_bitmap:0x%016llx, networkType:0x%02x\n", + __FUNCTION__, psta->mac_id, psta->raid, tx_ra_bitmap, psta->wireless_mode); - arg[0] = psta->mac_id; - arg[1] = psta->raid; - arg[2] = shortGIrate; - arg[3] = psta->init_rate; - - RTW_INFO("%s=> mac_id:%d , raid:%d , shortGIrate=%d, tx_ra_bitmap:0x%016llx, networkType:0x%02x\n", - __FUNCTION__, psta->mac_id, psta->raid, shortGIrate, tx_ra_bitmap, psta->wireless_mode); - - rtw_hal_add_ra_tid(padapter, tx_ra_bitmap, arg, rssi_level); + rtw_update_ramask(padapter, psta, psta->mac_id, rssi_level, is_update_bw); } else RTW_INFO("station aid %d exceed the max number\n", psta->aid); @@ -787,7 +680,6 @@ void update_bmc_sta(_adapter *padapter) _irqL irqL; unsigned char network_type; int supportRateNum = 0; - u64 tx_ra_bitmap = 0; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; struct sta_info *psta = rtw_get_bcmc_stainfo(padapter); @@ -820,16 +712,15 @@ void update_bmc_sta(_adapter *padapter) psta->wireless_mode = network_type; rtw_hal_update_sta_rate_mask(padapter, psta); - tx_ra_bitmap = psta->ra_mask; psta->raid = rtw_hal_networktype_to_raid(padapter, psta); - rtw_sta_media_status_rpt(padapter, psta, 1); - _enter_critical_bh(&psta->lock, &irqL); psta->state = _FW_LINKED; _exit_critical_bh(&psta->lock, &irqL); + rtw_sta_media_status_rpt(padapter, psta, 1); + rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); } else RTW_INFO("add_RATid_bmc_sta error!\n"); @@ -1048,7 +939,7 @@ static void rtw_set_hw_wmm_param(_adapter *padapter) acm_mask = 0; - if (IsSupported5G(pmlmeext->cur_wireless_mode) || + if (is_supported_5g(pmlmeext->cur_wireless_mode) || (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) aSifsTime = 16; else @@ -1280,7 +1171,7 @@ static void rtw_ap_check_scan(_adapter *padapter) pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - if (rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 + if (rtw_chset_search_ch(adapter_to_chset(padapter), pnetwork->network.Configuration.DSConfig) >= 0 && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))) { delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned); @@ -1299,11 +1190,14 @@ static void rtw_ap_check_scan(_adapter *padapter) if (pbuf == NULL) { /* HT CAP INFO IE don't exist, it is b/g mode bss.*/ - if (pmlmepriv->olbc == _FALSE) - pmlmepriv->olbc = _TRUE; + if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc)) + ATOMIC_SET(&pmlmepriv->olbc, _TRUE); - if (pmlmepriv->olbc_ht == _FALSE) - pmlmepriv->olbc_ht = _TRUE; + if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht)) + ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE); + + if (padapter->registrypriv.wifi_spec) + RTW_INFO("%s: %s is a/b/g ap\n", __func__, pnetwork->network.Ssid.Ssid); } } } @@ -1375,6 +1269,9 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) req_bw = parm->req_bw; req_offset = parm->req_offset; goto chbw_decision; + } else { + /* inform this request comes from upper layer */ + req_ch = 0; } bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod; @@ -1456,6 +1353,21 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) #endif #ifdef CONFIG_MCC_MODE + if (MCC_EN(padapter)) { + /* + * due to check under rtw_ap_chbw_decision + * if under MCC mode, means req channel setting is the same as current channel setting + * if not under MCC mode, mean req channel setting is not the same as current channel setting + */ + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { + RTW_INFO(FUNC_ADPT_FMT": req channel setting is the same as current channel setting, go to update BCN\n" + , FUNC_ADPT_ARG(padapter)); + + goto update_beacon; + + } + } + /* issue null data to AP for all interface connecting to AP before switch channel setting for softap */ rtw_hal_mcc_issue_null_data(padapter, chbw_allow, 1); #endif /* CONFIG_MCC_MODE */ @@ -1481,13 +1393,13 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) dump_adapters_status(RTW_DBGDUMP , adapter_to_dvobj(padapter)); } +update_beacon: /* update beacon content only if bstart_bss is _TRUE */ if (_TRUE == pmlmeext->bstart_bss) { _irqL irqL; - if ((pmlmepriv->olbc == _TRUE) || (pmlmepriv->olbc_ht == _TRUE)) { - + if ((ATOMIC_READ(&pmlmepriv->olbc) == _TRUE) || (ATOMIC_READ(&pmlmepriv->olbc_ht) == _TRUE)) { /* AP is not starting a 40 MHz BSS in presence of an 802.11g BSS. */ pmlmepriv->ht_op_mode &= (~HT_INFO_OPERATION_MODE_OP_MODE_MASK); @@ -1515,9 +1427,7 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) rtw_scan_wait_completed(padapter); /* send beacon */ - if ((0 == rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY)) - && (0 == rtw_mi_check_fwstate(padapter, WIFI_OP_CH_SWITCHING)) - ) { + if (!rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY)) { /*update_beacon(padapter, _TIM_IE_, NULL, _TRUE);*/ @@ -1567,6 +1477,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) u8 vht_cap = _FALSE; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); u8 rf_num = 0; /* SSID */ @@ -1872,24 +1783,29 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) /* Update Supported MCS Set field */ { + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + u8 rx_nss = 0; int i; rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num); /* RX MCS Bitmask */ - switch (rf_type) { - case RF_1T1R: - case RF_1T2R: /* ? */ + switch (rx_nss) { + case 1: set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_1R); break; - case RF_2T2R: + case 2: set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_2R); break; - case RF_3T3R: + case 3: set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_3R); break; + case 4: + set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_4R); + break; default: - RTW_INFO("[warning] rf_type %d is not expected\n", rf_type); + RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", rf_type, hal_spec->rx_nss_num); } for (i = 0; i < 10; i++) *(HT_CAP_ELE_RX_MCS_MAP(pht_cap) + i) &= padapter->mlmeextpriv.default_supported_mcs_set[i]; @@ -1970,8 +1886,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) pmlmepriv->htpriv.ht_option = _TRUE; pmlmepriv->qospriv.qos_option = 1; - if (pregistrypriv->ampdu_enable == 1) - pmlmepriv->htpriv.ampdu_enable = _TRUE; + pmlmepriv->htpriv.ampdu_enable = pregistrypriv->ampdu_enable ? _TRUE : _FALSE; HT_caps_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_caps_ie); @@ -1994,7 +1909,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) && (pmlmepriv->htpriv.ht_option == _TRUE) && REGSTY_IS_11AC_ENABLE(pregistrypriv) && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent)) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) ) { if (vht_cap == _TRUE) pmlmepriv->vhtpriv.vht_option = _TRUE; @@ -2026,6 +1941,15 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) } #endif /* CONFIG_80211AC_VHT */ + if(pbss_network->Configuration.DSConfig <= 14 && padapter->registrypriv.wifi_spec == 1) { + uint len = 0; + + SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 1); + pmlmepriv->ext_capab_ie_len = 10; + rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len); + pbss_network->IELength += pmlmepriv->ext_capab_ie_len; + } + pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network); rtw_ies_get_chbw(pbss_network->IEs + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_ @@ -2596,7 +2520,7 @@ static void update_bcn_htinfo_ie(_adapter *padapter) __FUNCTION__, pmlmepriv->ht_op_mode); RTW_INFO("num_sta_40mhz_intolerant(%d), 20mhz_width_req(%d), intolerant_ch_rpt(%d), olbc(%d)\n", - pmlmepriv->num_sta_40mhz_intolerant, pmlmepriv->ht_20mhz_width_req, pmlmepriv->ht_intolerant_ch_reported, pmlmepriv->olbc); + pmlmepriv->num_sta_40mhz_intolerant, pmlmepriv->ht_20mhz_width_req, pmlmepriv->ht_intolerant_ch_reported, ATOMIC_READ(&pmlmepriv->olbc)); /*parsing HT_INFO_IE, currently only update ht_op_mode - pht_info->infos[1] & pht_info->infos[2] for wifi logo test*/ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); @@ -2608,7 +2532,7 @@ static void update_bcn_htinfo_ie(_adapter *padapter) /* for STA Channel Width/Secondary Channel Offset*/ if ((pmlmepriv->sw_to_20mhz == 0) && (pmlmeext->cur_channel <= 14)) { if ((pmlmepriv->num_sta_40mhz_intolerant > 0) || (pmlmepriv->ht_20mhz_width_req == _TRUE) - || (pmlmepriv->ht_intolerant_ch_reported == _TRUE) || (pmlmepriv->olbc == _TRUE)) { + || (pmlmepriv->ht_intolerant_ch_reported == _TRUE) || (ATOMIC_READ(&pmlmepriv->olbc) == _TRUE)) { SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info, 0); SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 0); @@ -2625,7 +2549,7 @@ static void update_bcn_htinfo_ie(_adapter *padapter) } else { if ((pmlmepriv->num_sta_40mhz_intolerant == 0) && (pmlmepriv->ht_20mhz_width_req == _FALSE) - && (pmlmepriv->ht_intolerant_ch_reported == _FALSE) && (pmlmepriv->olbc == _FALSE)) { + && (pmlmepriv->ht_intolerant_ch_reported == _FALSE) && (ATOMIC_READ(&pmlmepriv->olbc) == _FALSE)) { if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_40) { @@ -2732,6 +2656,9 @@ static void update_bcn_wps_ie(_adapter *padapter) if (sr) { set_fwstate(pmlmepriv, WIFI_UNDER_WPS); RTW_INFO("%s, set WIFI_UNDER_WPS\n", __func__); + } else { + clr_fwstate(pmlmepriv, WIFI_UNDER_WPS); + RTW_INFO("%s, clr WIFI_UNDER_WPS\n", __func__); } } #endif @@ -2867,7 +2794,7 @@ void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_l uint frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr); u8 category, action; - psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); if (psta == NULL) return; @@ -2960,7 +2887,7 @@ Set to 2 if only HT STAs are associated in BSS, Set to 3 (HT mixed mode) when one or more non-HT STAs are associated (currently non-GF HT station is considered as non-HT STA also) */ -static int rtw_ht_operation_update(_adapter *padapter) +int rtw_ht_operation_update(_adapter *padapter) { u16 cur_op_mode, new_op_mode; int op_mode_changes = 0; @@ -2990,12 +2917,12 @@ static int rtw_ht_operation_update(_adapter *padapter) } if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) && - (pmlmepriv->num_sta_no_ht || pmlmepriv->olbc_ht)) { + (pmlmepriv->num_sta_no_ht || ATOMIC_READ(&pmlmepriv->olbc_ht))) { pmlmepriv->ht_op_mode |= HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT; op_mode_changes++; } else if ((pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) && - (pmlmepriv->num_sta_no_ht == 0 && !pmlmepriv->olbc_ht)) { + (pmlmepriv->num_sta_no_ht == 0 && !ATOMIC_READ(&pmlmepriv->olbc_ht))) { pmlmepriv->ht_op_mode &= ~HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT; op_mode_changes++; @@ -3012,7 +2939,7 @@ static int rtw_ht_operation_update(_adapter *padapter) else if ((phtpriv_ap->ht_cap.cap_info & IEEE80211_HT_CAP_SUP_WIDTH) && pmlmepriv->num_sta_ht_20mhz) new_op_mode = OP_MODE_20MHZ_HT_STA_ASSOCED; - else if (pmlmepriv->olbc_ht) + else if (ATOMIC_READ(&pmlmepriv->olbc_ht)) new_op_mode = OP_MODE_MAY_BE_LEGACY_STAS; else new_op_mode = OP_MODE_PURE; @@ -3219,37 +3146,6 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_ht_20mhz); } - - if (ht_capab & RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT) { - - if (!psta->ht_40mhz_intolerant) { - psta->ht_40mhz_intolerant = 1; - pmlmepriv->num_sta_40mhz_intolerant++; - RTW_INFO("%s STA " MAC_FMT " - HT_CAP_40MHZ_INTOLERANT is set\n" , - __FUNCTION__, MAC_ARG(psta->hwaddr)); - beacon_updated = _TRUE; - } - - /* - if (pmlmepriv->ht_40mhz_intolerant == _FALSE) { - - pmlmepriv->ht_40mhz_intolerant = _TRUE; - - RTW_INFO("%s STA " MAC_FMT " - HT_CAP_40MHZ_INTOLERANT is set\n" , - __FUNCTION__, MAC_ARG(psta->hwaddr)); - - beacon_updated = _TRUE; - } - */ - - /*update ext_capab_ie_len & ext_capab_ie_data for beacon, probersp, assocrsp.*/ - if (pmlmepriv->ext_capab_ie_len == 0) - pmlmepriv->ext_capab_ie_len = 1; - SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 1); - - update_beacon(padapter, _EXT_CAP_IE_, NULL, _FALSE); - } - } else { if (!psta->no_ht_set) { psta->no_ht_set = 1; @@ -3333,20 +3229,7 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_ht_20mhz--; } - if (psta->ht_40mhz_intolerant) { - psta->ht_40mhz_intolerant = 0; - pmlmepriv->num_sta_40mhz_intolerant--; - - /*update ext_capab_ie_len & ext_capab_ie_data for beacon, probersp, assocrsp.*/ - if ((pmlmepriv->ext_capab_ie_len > 0) && (pmlmepriv->num_sta_40mhz_intolerant == 0)) { - SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 0); - update_beacon(padapter, _EXT_CAP_IE_, NULL, _FALSE); - } - beacon_updated = _TRUE; - - update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE); - } if (rtw_ht_operation_update(padapter) > 0) { update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); @@ -3564,19 +3447,14 @@ void sta_info_update(_adapter *padapter, struct sta_info *psta) psta->vhtpriv.vht_option = _FALSE; #endif - update_sta_info_apmode(padapter, psta); - - } /* called >= TSR LEVEL for USB or SDIO Interface*/ void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta) { - if (psta->state & _FW_LINKED) { - /* add ratid */ - add_RATid(padapter, psta, 0);/* DM_RATR_STA_INIT */ - } + if (psta->state & _FW_LINKED) + rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); /* DM_RATR_STA_INIT */ } /* restore hw setting from sw data structures */ void rtw_ap_restore_network(_adapter *padapter) @@ -3673,8 +3551,8 @@ void start_ap_mode(_adapter *padapter) pmlmepriv->num_sta_ht_20mhz = 0; pmlmepriv->num_sta_40mhz_intolerant = 0; - pmlmepriv->olbc = _FALSE; - pmlmepriv->olbc_ht = _FALSE; + ATOMIC_SET(&pmlmepriv->olbc, _FALSE); + ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE); #ifdef CONFIG_80211N_HT pmlmepriv->ht_20mhz_width_req = _FALSE; @@ -3800,17 +3678,17 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, /* update vht cap ie */ if (vht_cap_ie && vht_cap_ielen) { -#if UPDATE_VHT_CAP + #if UPDATE_VHT_CAP /* if ((bw == CHANNEL_WIDTH_160 || bw == CHANNEL_WIDTH_80_80) && pvhtpriv->sgi_160m) SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvht_cap_ie + 2, 1); else */ - SET_VHT_CAPABILITY_ELE_SHORT_GI160M(vht_cap_ie + 2, 0); + SET_VHT_CAPABILITY_ELE_SHORT_GI160M(vht_cap_ie + 2, 0); if (bw >= CHANNEL_WIDTH_80 && vhtpriv->sgi_80m) SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 1); else SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 0); -#endif + #endif } /* update vht op ie */ @@ -3841,7 +3719,7 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, /* update ht cap ie */ if (ht_cap_ie && ht_cap_ielen) { -#if UPDATE_HT_CAP + #if UPDATE_HT_CAP if (bw >= CHANNEL_WIDTH_40) SET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 1); else @@ -3856,7 +3734,7 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 1); else SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 0); -#endif + #endif } /* update ht op ie */ @@ -3915,27 +3793,49 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse bool changed = _FALSE; struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); WLAN_BSSID_EX *network = &(adapter->mlmepriv.cur_network.network); - u8 sta_num; - u8 ld_sta_num; - u8 lg_sta_num; - u8 ap_num; - u8 ld_ap_num; + struct mi_state mstate; bool set_u_ch = _FALSE, set_dec_ch = _FALSE; rtw_ies_get_chbw(network->IEs + sizeof(NDIS_802_11_FIXED_IEs) , network->IELength - sizeof(NDIS_802_11_FIXED_IEs) , &cur_ie_ch, &cur_ie_bw, &cur_ie_offset); +#ifdef CONFIG_MCC_MODE + if (MCC_EN(adapter)) { + if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) { + /* check channel settings are the same */ + if (cur_ie_ch == mlmeext->cur_channel + && cur_ie_bw == mlmeext->cur_bwmode + && cur_ie_offset == mlmeext->cur_ch_offset) { + + + RTW_INFO(FUNC_ADPT_FMT"req ch settings are the same as current ch setting, go to exit\n" + , FUNC_ADPT_ARG(adapter)); + + *chbw_allow = _FALSE; + goto exit; + } else { + RTW_INFO(FUNC_ADPT_FMT"request channel settings are not the same as current channel setting(%d,%d,%d,%d,%d,%d), restart MCC\n" + , FUNC_ADPT_ARG(adapter) + , cur_ie_ch, cur_ie_bw, cur_ie_bw + , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + + rtw_hal_set_mcc_setting_disconnect(adapter); + } + } + } +#endif /* CONFIG_MCC_MODE */ + /* use chbw of cur_ie updated with specifying req as temporary decision */ dec_ch = (req_ch <= 0) ? cur_ie_ch : req_ch; dec_bw = (req_bw < 0) ? cur_ie_bw : req_bw; dec_offset = (req_offset < 0) ? cur_ie_offset : req_offset; - rtw_mi_status_no_self(adapter, &sta_num, &ld_sta_num, &lg_sta_num, &ap_num, &ld_ap_num, NULL); + rtw_mi_status_no_self(adapter, &mstate); RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num%u, ap_num:%u\n" - , FUNC_ADPT_ARG(adapter), ld_sta_num, lg_sta_num, ap_num); + , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate), MSTATE_AP_NUM(&mstate)); - if (ld_sta_num || ap_num) { + if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_AP_NUM(&mstate)) { /* has linked STA or AP mode, follow */ rtw_warn_on(!rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset)); @@ -3967,7 +3867,7 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse , dec_ch, dec_bw, dec_offset); set_u_ch = _TRUE; - } else if (lg_sta_num) { + } else if (MSTATE_STA_LG_NUM(&mstate)) { /* has linking STA */ rtw_warn_on(!rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset)); @@ -4014,26 +3914,33 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse /* check temporary decision first */ rtw_adjust_chbw(adapter, dec_ch, &dec_bw, &dec_offset); if (!rtw_get_offset_by_chbw(dec_ch, dec_bw, &dec_offset)) { -#if defined(CONFIG_DFS_MASTER) if (req_ch == -1 || req_bw == -1) goto choose_chbw; -#endif RTW_WARN(FUNC_ADPT_FMT" req: %u,%u has no valid offset\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw); *chbw_allow = _FALSE; goto exit; } - if (!rtw_chset_is_chbw_valid(mlmeext->channel_set, dec_ch, dec_bw, dec_offset)) { -#if defined(CONFIG_DFS_MASTER) + if (!rtw_chset_is_chbw_valid(adapter_to_chset(adapter), dec_ch, dec_bw, dec_offset)) { if (req_ch == -1 || req_bw == -1) goto choose_chbw; -#endif RTW_WARN(FUNC_ADPT_FMT" req: %u,%u,%u doesn't fit in chplan\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw, dec_offset); *chbw_allow = _FALSE; goto exit; } - if (rtw_chset_is_ch_non_ocp(mlmeext->channel_set, dec_ch, dec_bw, dec_offset) == _FALSE) + if (rtw_odm_dfs_domain_unknown(adapter) && rtw_is_dfs_chbw(dec_ch, dec_bw, dec_offset)) { + if (req_ch >= 0) + RTW_WARN(FUNC_ADPT_FMT" DFS channel %u,%u,%u can't be used\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw, dec_offset); + if (req_ch > 0) { + /* specific channel and not from IE => don't change channel setting */ + *chbw_allow = _FALSE; + goto exit; + } + goto choose_chbw; + } + + if (rtw_chset_is_ch_non_ocp(adapter_to_chset(adapter), dec_ch, dec_bw, dec_offset) == _FALSE) goto update_bss_chbw; choose_chbw: @@ -4041,19 +3948,26 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse req_bw = cur_ie_bw; #if defined(CONFIG_DFS_MASTER) - /* choose 5G DFS channel for debug */ - if (adapter_to_rfctl(adapter)->dbg_dfs_master_choose_dfs_ch_first - && rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_2G | RTW_CHF_NON_DFS) == _TRUE) - RTW_INFO(FUNC_ADPT_FMT" choose 5G DFS channel for debug\n", FUNC_ADPT_ARG(adapter)); - else if (adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags - && rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags) == _TRUE) - RTW_INFO(FUNC_ADPT_FMT" choose with dfs_ch_sel_d_flags:0x%02x for debug\n", FUNC_ADPT_ARG(adapter), adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags); - else if (rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, 0) == _FALSE) { + if (!rtw_odm_dfs_domain_unknown(adapter)) { + /* choose 5G DFS channel for debug */ + if (adapter_to_rfctl(adapter)->dbg_dfs_master_choose_dfs_ch_first + && rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_2G | RTW_CHF_NON_DFS) == _TRUE) + RTW_INFO(FUNC_ADPT_FMT" choose 5G DFS channel for debug\n", FUNC_ADPT_ARG(adapter)); + else if (adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags + && rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags) == _TRUE) + RTW_INFO(FUNC_ADPT_FMT" choose with dfs_ch_sel_d_flags:0x%02x for debug\n", FUNC_ADPT_ARG(adapter), adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags); + else if (rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, 0) == _FALSE) { + RTW_WARN(FUNC_ADPT_FMT" no available channel\n", FUNC_ADPT_ARG(adapter)); + *chbw_allow = _FALSE; + goto exit; + } + } else +#endif /* defined(CONFIG_DFS_MASTER) */ + if (rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_DFS) == _FALSE) { RTW_WARN(FUNC_ADPT_FMT" no available channel\n", FUNC_ADPT_ARG(adapter)); *chbw_allow = _FALSE; goto exit; } -#endif /* defined(CONFIG_DFS_MASTER) */ update_bss_chbw: rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) @@ -4223,8 +4137,15 @@ void tx_beacon_handlder(struct dvobj_priv *pdvobj) #ifdef DBG_SWTIMER_BASED_TXBCN RTW_INFO("padapter=%p, PORT=%d\n", padapter, padapter->hw_port); #endif - /*update_beacon(padapter, _TIM_IE_, NULL, _FALSE);*/ - issue_beacon(padapter, 0); + /* bypass TX BCN queue if op ch is switching/waiting */ + if (!check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) + #ifdef CONFIG_DFS_MASTER + && !IS_CH_WAITING(adapter_to_rfctl(padapter)) + #endif + ) { + /*update_beacon(padapter, _TIM_IE_, NULL, _FALSE);*/ + issue_beacon(padapter, 0); + } } #if 0 @@ -4239,8 +4160,9 @@ void tx_beacon_handlder(struct dvobj_priv *pdvobj) } -void tx_beacon_timer_handlder(struct dvobj_priv *pdvobj) +void tx_beacon_timer_handlder(void *ctx) { + struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx; _adapter *padapter = pdvobj->padapters[0]; if (padapter) @@ -4248,4 +4170,50 @@ void tx_beacon_timer_handlder(struct dvobj_priv *pdvobj) } #endif +void rtw_ap_acdata_control(_adapter *padapter, u8 power_mode) +{ + _irqL irqL; + _list *phead, *plist; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 sta_alive_num = 0, i; + char sta_alive_list[NUM_STA]; + +#ifdef CONFIG_MCC_MODE + if (MCC_EN(padapter) && rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + /* driver doesn't access macid sleep reg under MCC */ + return; +#endif + + /*RTW_INFO(FUNC_ADPT_FMT " associated sta num:%d, make macid_%s!!\n", + FUNC_ADPT_ARG(padapter), pstapriv->asoc_list_cnt, power_mode ? "sleep" : "wakeup");*/ + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + int stainfo_offset; + + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + stainfo_offset = rtw_stainfo_offset(pstapriv, psta); + if (stainfo_offset_valid(stainfo_offset)) + sta_alive_list[sta_alive_num++] = stainfo_offset; + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + for (i = 0; i < sta_alive_num; i++) { + psta = rtw_get_stainfo_by_offset(pstapriv, sta_alive_list[i]); + + if (psta) { + if (power_mode) + rtw_hal_macid_sleep(padapter, psta->mac_id); + else + rtw_hal_macid_wakeup(padapter, psta->mac_id); + } + } +} #endif /* CONFIG_AP_MODE */ diff --git a/core/rtw_beamforming.c b/core/rtw_beamforming.c index 4a55842..6bd7a30 100644 --- a/core/rtw_beamforming.c +++ b/core/rtw_beamforming.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_BEAMFORMING_C_ #include @@ -24,110 +19,1132 @@ #ifdef CONFIG_BEAMFORMING -#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/ #ifdef RTW_BEAMFORMING_VERSION_2 + +struct ndpa_sta_info { + u16 aid:12; + u16 feedback_type:1; + u16 nc_index:3; +}; + +static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 *g_id, u16 *p_aid) +{ + struct mlme_priv *mlme; + u16 aid; + u8 *bssid; + u16 val16; + u8 i; + + + mlme = &adapter->mlmepriv; + + if (check_fwstate(mlme, WIFI_AP_STATE)) { + /* + * Sent by an AP and addressed to a STA associated with that AP + * or sent by a DLS or TDLS STA in a direct path to + * a DLS or TDLS peer STA + */ + + aid = sta->aid; + bssid = adapter_mac_addr(adapter); + RTW_INFO("%s: AID=0x%x BSSID=" MAC_FMT "\n", + __FUNCTION__, sta->aid, MAC_ARG(bssid)); + + /* AID[0:8] */ + aid &= 0x1FF; + /* BSSID[44:47] xor BSSID[40:43] */ + val16 = ((bssid[5] & 0xF0) >> 4) ^ (bssid[5] & 0xF); + /* (dec(AID[0:8]) + dec(BSSID)*2^5) mod 2^9 */ + *p_aid = (aid + (val16 << 5)) & 0x1FF; + *g_id = 63; + } else if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE) + || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + /* + * Otherwise, includes + * 1. Sent to an IBSS STA + * 2. Sent by an AP to a non associated STA + * 3. Sent to a STA for which it is not known + * which condition is applicable + */ + *p_aid = 0; + *g_id = 63; + } else { + /* Addressed to AP */ + bssid = sta->hwaddr; + RTW_INFO("%s: BSSID=" MAC_FMT "\n", __FUNCTION__, MAC_ARG(bssid)); + + /* BSSID[39:47] */ + *p_aid = (bssid[5] << 1) | (bssid[4] >> 7); + *g_id = 0; + } + + RTW_INFO("%s: GROUP_ID=0x%02x PARTIAL_AID=0x%04x\n", + __FUNCTION__, *g_id, *p_aid); +} + /* - * For phydm + * Parameters + * adapter struct _adapter* + * sta struct sta_info* + * sta_bf_cap beamforming capabe of sta + * sounding_dim Number of Sounding Dimensions + * comp_steering Compressed Steering Number of Beamformer Antennas Supported */ -BEAMFORMING_CAP beamforming_get_entry_beam_cap_by_mac_id(void *mlme, u8 mac_id) +static void _get_sta_beamform_cap(PADAPTER adapter, struct sta_info *sta, + u8 *sta_bf_cap, u8 *sounding_dim, u8 *comp_steering) { - PADAPTER adapter; - struct beamforming_info *pBeamInfo; + struct beamforming_info *info; + struct ht_priv *ht; +#ifdef CONFIG_80211AC_VHT + struct vht_priv *vht; +#endif /* CONFIG_80211AC_VHT */ + u16 bf_cap; + + + *sta_bf_cap = 0; + *sounding_dim = 0; + *comp_steering = 0; + + info = GET_BEAMFORM_INFO(adapter); + ht = &adapter->mlmepriv.htpriv; +#ifdef CONFIG_80211AC_VHT + vht = &adapter->mlmepriv.vhtpriv; +#endif /* CONFIG_80211AC_VHT */ + + if (is_supported_ht(sta->wireless_mode) == _TRUE) { + /* HT */ + bf_cap = ht->beamform_cap; + + if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) { + info->beamforming_cap |= BEAMFORMEE_CAP_HT_EXPLICIT; + *sta_bf_cap |= BEAMFORMER_CAP_HT_EXPLICIT; + *sounding_dim = (bf_cap & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6; + } + if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { + info->beamforming_cap |= BEAMFORMER_CAP_HT_EXPLICIT; + *sta_bf_cap |= BEAMFORMEE_CAP_HT_EXPLICIT; + *comp_steering = (bf_cap & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4; + } + } + +#ifdef CONFIG_80211AC_VHT + if (is_supported_vht(sta->wireless_mode) == _TRUE) { + /* VHT */ + bf_cap = vht->beamform_cap; + + /* We are SU Beamformee because the STA is SU Beamformer */ + if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) { + info->beamforming_cap |= BEAMFORMEE_CAP_VHT_SU; + *sta_bf_cap |= BEAMFORMER_CAP_VHT_SU; + + /* We are MU Beamformee because the STA is MU Beamformer */ + if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) { + info->beamforming_cap |= BEAMFORMEE_CAP_VHT_MU; + *sta_bf_cap |= BEAMFORMER_CAP_VHT_MU; + } + + *sounding_dim = (bf_cap & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; + } + /* We are SU Beamformer because the STA is SU Beamformee */ + if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { + info->beamforming_cap |= BEAMFORMER_CAP_VHT_SU; + *sta_bf_cap |= BEAMFORMEE_CAP_VHT_SU; + + /* We are MU Beamformer because the STA is MU Beamformee */ + if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { + info->beamforming_cap |= BEAMFORMER_CAP_VHT_MU; + *sta_bf_cap |= BEAMFORMEE_CAP_VHT_MU; + } + + *comp_steering = (bf_cap & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; + } + } +#endif /* CONFIG_80211AC_VHT */ +} + +static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, CHANNEL_WIDTH bw) +{ + /* General */ + struct xmit_priv *pxmitpriv; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + struct xmit_frame *pmgntframe; + /* Beamforming */ + struct beamforming_info *info; + struct beamformee_entry *bfee; + struct ndpa_sta_info sta_info; + u8 ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xE0, 0x4C}; + /* MISC */ + struct pkt_attrib *attrib; + struct rtw_ieee80211_hdr *pwlanhdr; + enum MGN_RATE txrate; + u8 *pframe; + u16 duration = 0; + u8 aSifsTime = 0; + + + RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra)); + + pxmitpriv = &adapter->xmitpriv; + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + bfee = rtw_bf_bfee_get_entry_by_addr(adapter, ra); + if (!bfee) { + RTW_ERR("%s: Cann't find beamformee entry!\n", __FUNCTION__); + return _FALSE; + } + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (!pmgntframe) { + RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__); + return _FALSE; + } + + txrate = beamforming_get_htndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer); + + /* update attribute */ + attrib = &pmgntframe->attrib; + update_mgntframe_attrib(adapter, attrib); + /*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */ + attrib->subtype = WIFI_ACTION_NOACK; + attrib->bwmode = bw; + /*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */ + attrib->order = 1; + attrib->rate = (u8)txrate; + attrib->bf_pkt_type = 0; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + /* Frame control */ + pwlanhdr->frame_ctl = 0; + set_frame_sub_type(pframe, attrib->subtype); + set_order_bit(pframe); + + /* Duration */ + if (pmlmeext->cur_wireless_mode == WIRELESS_11B) + aSifsTime = 10; + else + aSifsTime = 16; + duration = 2 * aSifsTime + 40; + if (bw == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + set_duration(pframe, duration); + + /* DA */ + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); + /* SA */ + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); + /* BSSID */ + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + + /* HT control field */ + SET_HT_CTRL_CSI_STEERING(pframe + 24, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1); + + /* + * Frame Body + * Category field: vender-specific value, 0x7F + * OUI: 0x00E04C + */ + _rtw_memcpy(pframe + 28, ActionHdr, 4); + + attrib->pktlen = 32; + attrib->last_txcmdsz = attrib->pktlen; + + dump_mgntframe(adapter, pmgntframe); + + return _TRUE; +} + +static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw) +{ + /* General */ + struct xmit_priv *pxmitpriv; + struct mlme_ext_priv *pmlmeext; + struct xmit_frame *pmgntframe; + /* Beamforming */ + struct beamforming_info *info; + struct beamformee_entry *bfee; + struct ndpa_sta_info sta_info; + /* MISC */ + struct pkt_attrib *attrib; + struct rtw_ieee80211_hdr *pwlanhdr; + u8 *pframe; + enum MGN_RATE txrate; + u16 duration = 0; + u8 sequence = 0, aSifsTime = 0; + + + RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra)); + + pxmitpriv = &adapter->xmitpriv; + pmlmeext = &adapter->mlmeextpriv; + info = GET_BEAMFORM_INFO(adapter); + bfee = rtw_bf_bfee_get_entry_by_addr(adapter, ra); + if (!bfee) { + RTW_ERR("%s: Cann't find beamformee entry!\n", __FUNCTION__); + return _FALSE; + } + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (!pmgntframe) { + RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__); + return _FALSE; + } + + txrate = beamforming_get_vht_ndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer); + + /* update attribute */ + attrib = &pmgntframe->attrib; + update_mgntframe_attrib(adapter, attrib); + /*pattrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */ + attrib->subtype = WIFI_NDPA; + attrib->bwmode = bw; + /*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */ + attrib->rate = (u8)txrate; + attrib->bf_pkt_type = 0; + + _rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET); + pframe = pmgntframe->buf_addr + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + /* Frame control */ + pwlanhdr->frame_ctl = 0; + set_frame_sub_type(pframe, attrib->subtype); + + /* Duration */ + if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) + aSifsTime = 16; + else + aSifsTime = 10; + duration = 2 * aSifsTime + 44; + if (bw == CHANNEL_WIDTH_80) + duration += 40; + else if (bw == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + set_duration(pframe, duration); + + /* RA */ + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); + + /* TA */ + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); + + /* Sounding Sequence, bit0~1 is reserved */ + sequence = info->sounding_sequence << 2; + if (info->sounding_sequence >= 0x3f) + info->sounding_sequence = 0; + else + info->sounding_sequence++; + _rtw_memcpy(pframe + 16, &sequence, 1); + + /* STA Info */ + /* + * "AID12" Equal to 0 if the STA is an AP, mesh STA or + * STA that is a member of an IBSS + */ + if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _FALSE) + aid = 0; + sta_info.aid = aid; + /* "Feedback Type" set to 0 for SU */ + sta_info.feedback_type = 0; + /* "Nc Index" reserved if the Feedback Type field indicates SU */ + sta_info.nc_index = 0; + _rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2); + + attrib->pktlen = 19; + attrib->last_txcmdsz = attrib->pktlen; + + dump_mgntframe(adapter, pmgntframe); + + return _TRUE; +} + +static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, CHANNEL_WIDTH bw) +{ + /* General */ + struct xmit_priv *pxmitpriv; + struct mlme_ext_priv *pmlmeext; + struct xmit_frame *pmgntframe; + /* Beamforming */ + struct beamforming_info *info; + struct sounding_info *sounding; + struct beamformee_entry *bfee; + struct ndpa_sta_info sta_info; + /* MISC */ + struct pkt_attrib *attrib; + struct rtw_ieee80211_hdr *pwlanhdr; + enum MGN_RATE txrate; + u8 *pframe; + u8 *ra = NULL; + u16 duration = 0; + u8 sequence = 0, aSifsTime = 0; + u8 i; + + + RTW_INFO("+%s\n", __FUNCTION__); + + pxmitpriv = &adapter->xmitpriv; + pmlmeext = &adapter->mlmeextpriv; + info = GET_BEAMFORM_INFO(adapter); + sounding = &info->sounding_info; + + txrate = MGN_VHT2SS_MCS0; + + /* + * Fill the first MU BFee entry (STA1) MAC addr to destination address then + * HW will change A1 to broadcast addr. + * 2015.05.28. Suggested by SD1 Chunchu. + */ + bfee = &info->bfee_entry[sounding->mu_sounding_list[0]]; + ra = bfee->mac_addr; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (!pmgntframe) { + RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__); + return _FALSE; + } + + /* update attribute */ + attrib = &pmgntframe->attrib; + update_mgntframe_attrib(adapter, attrib); + /*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */ + attrib->subtype = WIFI_NDPA; + attrib->bwmode = bw; + /*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */ + attrib->rate = (u8)txrate; + /* Set TxBFPktType of Tx desc to unicast type if there is only one MU STA for HW design */ + if (info->sounding_info.candidate_mu_bfee_cnt > 1) + attrib->bf_pkt_type = 1; + else + attrib->bf_pkt_type = 0; + + _rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET); + pframe = pmgntframe->buf_addr + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + /* Frame control */ + pwlanhdr->frame_ctl = 0; + set_frame_sub_type(pframe, attrib->subtype); + + /* Duration */ + if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) + aSifsTime = 16; + else + aSifsTime = 10; + duration = 2 * aSifsTime + 44; + if (bw == CHANNEL_WIDTH_80) + duration += 40; + else if (bw == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + set_duration(pframe, duration); + + /* RA */ + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); + + /* TA */ + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); + + /* Sounding Sequence, bit0~1 is reserved */ + sequence = info->sounding_sequence << 2; + if (info->sounding_sequence >= 0x3f) + info->sounding_sequence = 0; + else + info->sounding_sequence++; + _rtw_memcpy(pframe + 16, &sequence, 1); + + attrib->pktlen = 17; + + /* + * Construct STA info. for multiple STAs + * STA Info1, ..., STA Info n + */ + for (i = 0; i < sounding->candidate_mu_bfee_cnt; i++) { + bfee = &info->bfee_entry[sounding->mu_sounding_list[i]]; + sta_info.aid = bfee->aid; + sta_info.feedback_type = 1; /* 1'b1: MU */ + sta_info.nc_index = 0; + _rtw_memcpy(pframe + attrib->pktlen, (u8 *)&sta_info, 2); + attrib->pktlen += 2; + } + + attrib->last_txcmdsz = attrib->pktlen; + + dump_mgntframe(adapter, pmgntframe); + + return _TRUE; +} + +static u8 _send_bf_report_poll(PADAPTER adapter, u8 *ra, u8 bFinalPoll) +{ + /* General */ + struct xmit_priv *pxmitpriv; + struct xmit_frame *pmgntframe; + /* MISC */ + struct pkt_attrib *attrib; + struct rtw_ieee80211_hdr *pwlanhdr; + u8 *pframe; + + + RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra)); + + pxmitpriv = &adapter->xmitpriv; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (!pmgntframe) { + RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__); + return _FALSE; + } + + /* update attribute */ + attrib = &pmgntframe->attrib; + update_mgntframe_attrib(adapter, attrib); + /*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */ + attrib->subtype = WIFI_BF_REPORT_POLL; + attrib->bwmode = CHANNEL_WIDTH_20; + /*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */ + attrib->rate = MGN_6M; + if (bFinalPoll) + attrib->bf_pkt_type = 3; + else + attrib->bf_pkt_type = 2; + + _rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET); + pframe = pmgntframe->buf_addr + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + /* Frame control */ + pwlanhdr->frame_ctl = 0; + set_frame_sub_type(pframe, attrib->subtype); + + /* Duration */ + set_duration(pframe, 100); + + /* RA */ + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); + + /* TA */ + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); + + /* Feedback Segment Retransmission Bitmap */ + pframe[16] = 0xFF; + + attrib->pktlen = 17; + attrib->last_txcmdsz = attrib->pktlen; + + dump_mgntframe(adapter, pmgntframe); + + return _TRUE; +} + +static void _sounding_update_min_period(PADAPTER adapter, u16 period, u8 leave) +{ + struct beamforming_info *info; struct beamformee_entry *bfee; - BEAMFORMING_CAP cap = BEAMFORMING_CAP_NONE; u8 i = 0; + u16 min_val = 0xFFFF; - adapter = mlme_to_adapter((struct mlme_priv *)mlme); - pBeamInfo = GET_BEAMFORM_INFO(adapter); + info = GET_BEAMFORM_INFO(adapter); - for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) { - bfee = &pBeamInfo->bfee_entry[i]; - if ((bfee->used == _TRUE) - && (bfee->mac_id == mac_id)) { - cap = bfee->cap; + if (_TRUE == leave) { + /* + * When a BFee left, + * we need to find the latest min sounding period + * from the remaining BFees + */ + for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { + bfee = &info->bfee_entry[i]; + if ((bfee->used == _TRUE) + && (bfee->sound_period < min_val)) + min_val = bfee->sound_period; + } + + if (min_val == 0xFFFF) + info->sounding_info.min_sounding_period = 0; + else + info->sounding_info.min_sounding_period = min_val; + } else { + if ((info->sounding_info.min_sounding_period == 0) + || (period < info->sounding_info.min_sounding_period)) + info->sounding_info.min_sounding_period = period; + } +} + +static void _sounding_init(struct sounding_info *sounding) +{ + _rtw_memset(sounding->su_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_SU); + _rtw_memset(sounding->mu_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_MU); + sounding->state = SOUNDING_STATE_NONE; + sounding->su_bfee_curidx = 0xFF; + sounding->candidate_mu_bfee_cnt = 0; + sounding->min_sounding_period = 0; + sounding->sound_remain_cnt_per_period = 0; +} + +static void _sounding_reset_vars(PADAPTER adapter) +{ + struct beamforming_info *info; + struct sounding_info *sounding; + u8 idx; + + + info = GET_BEAMFORM_INFO(adapter); + sounding = &info->sounding_info; + + _rtw_memset(sounding->su_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_SU); + _rtw_memset(sounding->mu_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_MU); + sounding->su_bfee_curidx = 0xFF; + sounding->candidate_mu_bfee_cnt = 0; + + /* Clear bSound flag for the new period */ + for (idx = 0; idx < MAX_BEAMFORMEE_ENTRY_NUM; idx++) { + if ((info->bfee_entry[idx].used == _TRUE) + && (info->bfee_entry[idx].sounding == _TRUE)) { + info->bfee_entry[idx].sounding = _FALSE; + info->bfee_entry[idx].bCandidateSoundingPeer = _FALSE; + } + } +} + +/* + * Return + * 0 Prepare sounding list OK + * -1 Fail to prepare sounding list, because no beamformee need to souding + * -2 Fail to prepare sounding list, because beamformee state not ready + * + */ +static int _sounding_get_list(PADAPTER adapter) +{ + struct beamforming_info *info; + struct sounding_info *sounding; + struct beamformee_entry *bfee; + u8 i, mu_idx = 0, su_idx = 0, not_ready = 0; + int ret = 0; + + + info = GET_BEAMFORM_INFO(adapter); + sounding = &info->sounding_info; + + /* Add MU BFee list first because MU priority is higher than SU */ + for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { + bfee = &info->bfee_entry[i]; + if (bfee->used == _FALSE) + continue; + + if (bfee->state != BEAMFORM_ENTRY_HW_STATE_ADDED) { + RTW_ERR("%s: Invalid BFee idx(%d) Hw state=%d\n", __FUNCTION__, i, bfee->state); + not_ready++; + continue; + } + + /* + * Decrease BFee's SoundCnt per period + * If the remain count is 0, + * then it can be sounded at this time + */ + if (bfee->SoundCnt) { + bfee->SoundCnt--; + if (bfee->SoundCnt) + continue; + } + + /* + * + * If the STA supports MU BFee capability then we add it to MUSoundingList directly + * because we can only sound one STA by unicast NDPA with MU cap enabled to get correct channel info. + * Suggested by BB team Luke Lee. 2015.11.25. + */ + if (bfee->cap & BEAMFORMEE_CAP_VHT_MU) { + /* MU BFee */ + if (mu_idx >= MAX_NUM_BEAMFORMEE_MU) { + RTW_ERR("%s: Too much MU bfee entry(Limit:%d)\n", __FUNCTION__, MAX_NUM_BEAMFORMEE_MU); + continue; + } + + if (bfee->bApplySounding == _TRUE) { + bfee->bCandidateSoundingPeer = _TRUE; + bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, sounding->min_sounding_period); + sounding->mu_sounding_list[mu_idx] = i; + mu_idx++; + } + } else if (bfee->cap & (BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) { + /* SU BFee (HT/VHT) */ + if (su_idx >= MAX_NUM_BEAMFORMEE_SU) { + RTW_ERR("%s: Too much SU bfee entry(Limit:%d)\n", __FUNCTION__, MAX_NUM_BEAMFORMEE_SU); + continue; + } + + if (bfee->bDeleteSounding == _TRUE) { + sounding->su_sounding_list[su_idx] = i; + su_idx++; + } else if ((bfee->bApplySounding == _TRUE) + && (bfee->bSuspendSUCap == _FALSE)) { + bfee->bCandidateSoundingPeer = _TRUE; + bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, sounding->min_sounding_period); + sounding->su_sounding_list[su_idx] = i; + su_idx++; + } + } + } + + sounding->candidate_mu_bfee_cnt = mu_idx; + + if (su_idx + mu_idx == 0) { + ret = -1; + if (not_ready) + ret = -2; + } + + RTW_INFO("-%s: There are %d SU and %d MU BFees in this sounding period\n", __FUNCTION__, su_idx, mu_idx); + + return ret; +} + +static void _sounding_handler(PADAPTER adapter) +{ + struct beamforming_info *info; + struct sounding_info *sounding; + struct beamformee_entry *bfee; + u8 su_idx, i; + u32 timeout_period = 0; + u8 set_timer = _FALSE; + int ret = 0; + static u16 wait_cnt = 0; + + + info = GET_BEAMFORM_INFO(adapter); + sounding = &info->sounding_info; + + RTW_DBG("+%s: state=%d\n", __FUNCTION__, sounding->state); + if ((sounding->state != SOUNDING_STATE_INIT) + && (sounding->state != SOUNDING_STATE_SU_SOUNDDOWN) + && (sounding->state != SOUNDING_STATE_MU_SOUNDDOWN) + && (sounding->state != SOUNDING_STATE_SOUNDING_TIMEOUT)) { + RTW_WARN("%s: Invalid State(%d) and return!\n", __FUNCTION__, sounding->state); + return; + } + + if (sounding->state == SOUNDING_STATE_INIT) { + RTW_INFO("%s: Sounding start\n", __FUNCTION__); + + /* Init Var */ + _sounding_reset_vars(adapter); + + /* Get the sounding list of this sounding period */ + ret = _sounding_get_list(adapter); + if (ret == -1) { + wait_cnt = 0; + sounding->state = SOUNDING_STATE_NONE; + RTW_ERR("%s: No BFees found, set to SOUNDING_STATE_NONE\n", __FUNCTION__); + info->sounding_running--; + return; + } + if (ret == -2) { + RTW_WARN("%s: Temporarily cann't find BFee to sounding\n", __FUNCTION__); + if (wait_cnt < 5) { + wait_cnt++; + } else { + wait_cnt = 0; + sounding->state = SOUNDING_STATE_NONE; + RTW_ERR("%s: Wait changing state timeout!! Set to SOUNDING_STATE_NONE\n", __FUNCTION__); + } + info->sounding_running--; + return; + } + if (ret != 0) { + wait_cnt = 0; + RTW_ERR("%s: Unkown state(%d)!\n", __FUNCTION__, ret); + info->sounding_running--; + return; + + } + + wait_cnt = 0; + + if (check_fwstate(&adapter->mlmepriv, WIFI_SITE_MONITOR) == _TRUE) { + RTW_INFO("%s: Sounding abort! scanning APs...\n", __FUNCTION__); + info->sounding_running--; + return; + } + + rtw_ps_deny(adapter, PS_DENY_BEAMFORMING); + LeaveAllPowerSaveModeDirect(adapter); + } + + /* Get non-sound SU BFee index */ + for (i = 0; i < MAX_NUM_BEAMFORMEE_SU; i++) { + su_idx = sounding->su_sounding_list[i]; + if (su_idx >= MAX_BEAMFORMEE_ENTRY_NUM) + continue; + bfee = &info->bfee_entry[su_idx]; + if (_FALSE == bfee->sounding) break; + } + if (i < MAX_NUM_BEAMFORMEE_SU) { + sounding->su_bfee_curidx = su_idx; + /* Set to sounding start state */ + sounding->state = SOUNDING_STATE_SU_START; + RTW_DBG("%s: Set to SOUNDING_STATE_SU_START\n", __FUNCTION__); + + bfee->sounding = _TRUE; + /* Reset sounding timeout flag for the new sounding */ + bfee->bSoundingTimeout = _FALSE; + + if (_TRUE == bfee->bDeleteSounding) { + u8 res = _FALSE; + rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 0); + return; } + + /* Start SU sounding */ + if (bfee->cap & BEAMFORMEE_CAP_VHT_SU) + _send_vht_ndpa_packet(adapter, bfee->mac_addr, bfee->aid, bfee->sound_bw); + else if (bfee->cap & BEAMFORMEE_CAP_HT_EXPLICIT) + _send_ht_ndpa_packet(adapter, bfee->mac_addr, bfee->sound_bw); + + /* Set sounding timeout timer */ + _set_timer(&info->sounding_timeout_timer, SU_SOUNDING_TIMEOUT); + return; } - return cap; + if (sounding->candidate_mu_bfee_cnt > 0) { + /* + * If there is no SU BFee then find MU BFee and perform MU sounding + * + * Need to check the MU starting condition. 2015.12.15. + */ + sounding->state = SOUNDING_STATE_MU_START; + RTW_DBG("%s: Set to SOUNDING_STATE_MU_START\n", __FUNCTION__); + + /* Update MU BFee info */ + for (i = 0; i < sounding->candidate_mu_bfee_cnt; i++) { + bfee = &info->bfee_entry[sounding->mu_sounding_list[i]]; + bfee->sounding = _TRUE; + } + + /* Send MU NDPA */ + bfee = &info->bfee_entry[sounding->mu_sounding_list[0]]; + _send_vht_mu_ndpa_packet(adapter, bfee->sound_bw); + + /* Send BF report poll if more than 1 MU STA */ + for (i = 1; i < sounding->candidate_mu_bfee_cnt; i++) { + bfee = &info->bfee_entry[sounding->mu_sounding_list[i]]; + + if (i == (sounding->candidate_mu_bfee_cnt - 1))/* The last STA*/ + _send_bf_report_poll(adapter, bfee->mac_addr, _TRUE); + else + _send_bf_report_poll(adapter, bfee->mac_addr, _FALSE); + } + + sounding->candidate_mu_bfee_cnt = 0; + + /* Set sounding timeout timer */ + _set_timer(&info->sounding_timeout_timer, MU_SOUNDING_TIMEOUT); + return; + } + + info->sounding_running--; + sounding->state = SOUNDING_STATE_INIT; + RTW_INFO("%s: Sounding finished!\n", __FUNCTION__); + rtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING); +} + +static void _sounding_force_stop(PADAPTER adapter) +{ + struct beamforming_info *info; + struct sounding_info *sounding; + + info = GET_BEAMFORM_INFO(adapter); + sounding = &info->sounding_info; + + if ((sounding->state == SOUNDING_STATE_SU_START) + || (sounding->state == SOUNDING_STATE_MU_START)) { + u8 res = _FALSE; + _cancel_timer_ex(&info->sounding_timeout_timer); + rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 1); + return; + } + + info->sounding_running--; + sounding->state = SOUNDING_STATE_INIT; + RTW_INFO("%s: Sounding finished!\n", __FUNCTION__); + rtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING); +} + +static void _sounding_timer_handler(void *FunctionContext) +{ + PADAPTER adapter; + struct beamforming_info *info; + struct sounding_info *sounding; + static u8 delay = 0; + + + RTW_DBG("+%s\n", __FUNCTION__); + + adapter = (PADAPTER)FunctionContext; + info = GET_BEAMFORM_INFO(adapter); + sounding = &info->sounding_info; + + if (SOUNDING_STATE_NONE == sounding->state) { + RTW_INFO("%s: Stop!\n", __FUNCTION__); + if (info->sounding_running) + RTW_WARN("%s: souding_running=%d when thread stop!\n", + __FUNCTION__, info->sounding_running); + return; + } + + _set_timer(&info->sounding_timer, sounding->min_sounding_period); + + if (!info->sounding_running) { + if (SOUNDING_STATE_INIT != sounding->state) { + RTW_WARN("%s: state(%d) != SOUNDING_STATE_INIT!!\n", __FUNCTION__, sounding->state); + sounding->state = SOUNDING_STATE_INIT; + } + delay = 0; + info->sounding_running++; + rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1); + } else { + if (delay != 0xFF) + delay++; + RTW_WARN("%s: souding is still processing...(state:%d, running:%d, delay:%d)\n", + __FUNCTION__, sounding->state, info->sounding_running, delay); + if (delay > 3) { + RTW_WARN("%s: Stop sounding!!\n", __FUNCTION__); + _sounding_force_stop(adapter); + } + } } -struct beamformer_entry *beamforming_get_bfer_entry_by_addr(PADAPTER adapter, u8 *ra) +static void _sounding_timeout_timer_handler(void *FunctionContext) +{ + PADAPTER adapter; + struct beamforming_info *info; + struct sounding_info *sounding; + struct beamformee_entry *bfee; + + + RTW_WARN("+%s\n", __FUNCTION__); + + adapter = (PADAPTER)FunctionContext; + info = GET_BEAMFORM_INFO(adapter); + sounding = &info->sounding_info; + + if (SOUNDING_STATE_SU_START == sounding->state) { + sounding->state = SOUNDING_STATE_SOUNDING_TIMEOUT; + RTW_ERR("%s: Set to SU SOUNDING_STATE_SOUNDING_TIMEOUT\n", __FUNCTION__); + /* SU BFee */ + bfee = &info->bfee_entry[sounding->su_bfee_curidx]; + bfee->bSoundingTimeout = _TRUE; + RTW_WARN("%s: The BFee entry[%d] is Sounding Timeout!\n", __FUNCTION__, sounding->su_bfee_curidx); + } else if (SOUNDING_STATE_MU_START == sounding->state) { + sounding->state = SOUNDING_STATE_SOUNDING_TIMEOUT; + RTW_ERR("%s: Set to MU SOUNDING_STATE_SOUNDING_TIMEOUT\n", __FUNCTION__); + } else { + RTW_WARN("%s: unexpected sounding state:0x%02x\n", __FUNCTION__, sounding->state); + return; + } + + rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1); +} + +static struct beamformer_entry *_bfer_get_free_entry(PADAPTER adapter) { u8 i = 0; - struct beamforming_info *bf_info; - struct beamformer_entry *entry; + struct beamforming_info *info; + struct beamformer_entry *bfer; + + + info = GET_BEAMFORM_INFO(adapter); + + for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) { + bfer = &info->bfer_entry[i]; + if (bfer->used == _FALSE) + return bfer; + } + + return NULL; +} + +static struct beamformer_entry *_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra) +{ + u8 i = 0; + struct beamforming_info *info; + struct beamformer_entry *bfer; + + + info = GET_BEAMFORM_INFO(adapter); + + for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) { + bfer = &info->bfer_entry[i]; + if (bfer->used == _FALSE) + continue; + if (_rtw_memcmp(ra, bfer->mac_addr, ETH_ALEN) == _TRUE) + return bfer; + } + + return NULL; +} + +static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter, + struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering) +{ + struct mlme_priv *mlme; + struct beamforming_info *info; + struct beamformer_entry *bfer; + u8 *bssid; + u16 val16; + u8 i; + + + mlme = &adapter->mlmepriv; + info = GET_BEAMFORM_INFO(adapter); + + bfer = _bfer_get_entry_by_addr(adapter, sta->hwaddr); + if (!bfer) { + bfer = _bfer_get_free_entry(adapter); + if (!bfer) + return NULL; + } + + bfer->used = _TRUE; + _get_txvector_parameter(adapter, sta, &bfer->g_id, &bfer->p_aid); + _rtw_memcpy(bfer->mac_addr, sta->hwaddr, ETH_ALEN); + bfer->cap = bf_cap; + bfer->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT; + bfer->NumofSoundingDim = sounding_dim; + + if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_MU)) { + info->beamformer_mu_cnt += 1; + bfer->aid = sta->aid; + } else if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) { + info->beamformer_su_cnt += 1; + + /* Record HW idx info */ + for (i = 0; i < MAX_NUM_BEAMFORMER_SU; i++) { + if ((info->beamformer_su_reg_maping & BIT(i)) == 0) { + info->beamformer_su_reg_maping |= BIT(i); + bfer->su_reg_index = i; + break; + } + } + RTW_INFO("%s: Add BFer entry beamformer_su_reg_maping=%#x, su_reg_index=%d\n", + __FUNCTION__, info->beamformer_su_reg_maping, bfer->su_reg_index); + } + + return bfer; +} + +static void _bfer_remove_entry(PADAPTER adapter, struct beamformer_entry *entry) +{ + struct beamforming_info *info; + + + info = GET_BEAMFORM_INFO(adapter); + + entry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT; + + if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_MU)) { + info->beamformer_mu_cnt -= 1; + _rtw_memset(entry->gid_valid, 0, 8); + _rtw_memset(entry->user_position, 0, 16); + } else if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) { + info->beamformer_su_cnt -= 1; + } + + if (info->beamformer_mu_cnt == 0) + info->beamforming_cap &= ~BEAMFORMEE_CAP_VHT_MU; + if (info->beamformer_su_cnt == 0) + info->beamforming_cap &= ~(BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT); +} + +static u8 _bfer_set_entry_gid(PADAPTER adapter, u8 *addr, u8 *gid, u8 *position) +{ + struct beamformer_entry bfer; + memset(&bfer, 0, sizeof(bfer)); + memcpy(bfer.mac_addr, addr, 6); - bf_info = GET_BEAMFORM_INFO(adapter); + /* Parsing Membership Status Array */ + memcpy(bfer.gid_valid, gid, 8); - for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) { - entry = &bf_info->bfer_entry[i]; - if (entry->used == _FALSE) - continue; - if (_rtw_memcmp(ra, entry->mac_addr, ETH_ALEN) == _TRUE) { - return entry; - } - } + /* Parsing User Position Array */ + memcpy(bfer.user_position, position, 16); - return NULL; + /* Config HW GID table */ + rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_GID_TABLE, (u8 *) &bfer, + sizeof(bfer), 1); + + return _SUCCESS; } -struct beamformee_entry *beamforming_get_bfee_entry_by_addr(PADAPTER adapter, u8 *ra) +static struct beamformee_entry *_bfee_get_free_entry(PADAPTER adapter) { u8 i = 0; - struct beamforming_info *bf_info; - struct beamformee_entry *entry; + struct beamforming_info *info; + struct beamformee_entry *bfee; - bf_info = GET_BEAMFORM_INFO(adapter); + info = GET_BEAMFORM_INFO(adapter); for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { - entry = &bf_info->bfee_entry[i]; - if (entry->used == _FALSE) - continue; - if (_rtw_memcmp(ra, entry->mac_addr, ETH_ALEN) == _TRUE) - return entry; + bfee = &info->bfee_entry[i]; + if (bfee->used == _FALSE) + return bfee; } return NULL; } -static struct beamformer_entry *_get_bfer_free_entry(PADAPTER adapter) +static struct beamformee_entry *_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra) { u8 i = 0; - struct beamforming_info *bf_info; - struct beamformer_entry *entry; + struct beamforming_info *info; + struct beamformee_entry *bfee; - bf_info = GET_BEAMFORM_INFO(adapter); + info = GET_BEAMFORM_INFO(adapter); - for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) { - entry = &bf_info->bfer_entry[i]; - if (entry->used == _FALSE) - return entry; + for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { + bfee = &info->bfee_entry[i]; + if (bfee->used == _FALSE) + continue; + if (_rtw_memcmp(ra, bfee->mac_addr, ETH_ALEN) == _TRUE) + return bfee; } return NULL; } -static struct beamformee_entry *_get_bfee_free_entry(PADAPTER adapter) +static u8 _bfee_get_first_su_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore) { - u8 i = 0; - struct beamforming_info *bf_info; - struct beamformee_entry *entry; + struct beamforming_info *info; + struct beamformee_entry *bfee; + u8 i; - bf_info = GET_BEAMFORM_INFO(adapter); + info = GET_BEAMFORM_INFO(adapter); for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { - entry = &bf_info->bfee_entry[i]; - if (entry->used == _FALSE) - return entry; + bfee = &info->bfee_entry[i]; + if (ignore && (bfee == ignore)) + continue; + if (bfee->used == _FALSE) + continue; + if ((!TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU)) + && TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) + return i; } - return NULL; + return 0xFF; } /* @@ -135,354 +1152,208 @@ static struct beamformee_entry *_get_bfee_free_entry(PADAPTER adapter) * Get the first entry index of MU Beamformee. * * Return Value: - * Index of the first MU sta. + * Index of the first MU sta, or 0xFF for invalid index. * * 2015.05.25. Created by tynli. * */ -static u8 _get_first_mu_bfee_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore) +static u8 _bfee_get_first_mu_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore) { - struct beamforming_info *bf_info; - struct beamformee_entry *entry; - u8 idx = 0xFF; - u8 bFound = _FALSE; + struct beamforming_info *info; + struct beamformee_entry *bfee; + u8 i; - bf_info = GET_BEAMFORM_INFO(adapter); + info = GET_BEAMFORM_INFO(adapter); - for (idx = 0; idx < MAX_BEAMFORMEE_ENTRY_NUM; idx++) { - entry = &bf_info->bfee_entry[idx]; - if (ignore && (entry == ignore)) + for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { + bfee = &info->bfee_entry[i]; + if (ignore && (bfee == ignore)) continue; - if ((entry->used == _TRUE) && - TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_MU)) { - bFound = _TRUE; - break; - } + if (bfee->used == _FALSE) + continue; + if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU)) + return i; } - if (bFound == _FALSE) - idx = 0xFF; - - return idx; -} - -static void _update_min_sounding_period(PADAPTER adapter, u16 period, u8 leave) -{ - struct beamforming_info *bf_info; - struct beamformee_entry *entry; - u8 i = 0; - u16 min_val = 0xFFFF; - - - bf_info = GET_BEAMFORM_INFO(adapter); - - if (_TRUE == leave) { - /* - * When a BFee left, - * we need to find the latest min sounding period - * from the remaining BFees - */ - for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { - entry = &bf_info->bfee_entry[i]; - if ((entry->used == _TRUE) - && (entry->sound_period < min_val)) - min_val = entry->sound_period; - } - - if (min_val == 0xFFFF) - bf_info->sounding_info.min_sounding_period = 0; - else - bf_info->sounding_info.min_sounding_period = min_val; - } else { - if ((bf_info->sounding_info.min_sounding_period == 0) - || (period < bf_info->sounding_info.min_sounding_period)) - bf_info->sounding_info.min_sounding_period = period; - } + return 0xFF; } -static struct beamformer_entry *_add_bfer_entry(PADAPTER adapter, +static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter, struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering) { struct mlme_priv *mlme; - struct beamforming_info *bf_info; - struct beamformer_entry *entry; + struct beamforming_info *info; + struct beamformee_entry *bfee; u8 *bssid; u16 val16; u8 i; mlme = &adapter->mlmepriv; - bf_info = GET_BEAMFORM_INFO(adapter); + info = GET_BEAMFORM_INFO(adapter); - entry = beamforming_get_bfer_entry_by_addr(adapter, sta->hwaddr); - if (!entry) { - entry = _get_bfer_free_entry(adapter); - if (!entry) + bfee = _bfee_get_entry_by_addr(adapter, sta->hwaddr); + if (!bfee) { + bfee = _bfee_get_free_entry(adapter); + if (!bfee) return NULL; } - entry->used = _TRUE; - - if (check_fwstate(mlme, WIFI_AP_STATE)) { - bssid = adapter_mac_addr(adapter); - /* BSSID[44:47] xor BSSID[40:43] */ - val16 = ((bssid[5] & 0xF0) >> 4) ^ (bssid[5] & 0xF); - /* (dec(A) + dec(B)*32) mod 512 */ - entry->p_aid = (sta->aid + val16 * 32) & 0x1FF; - entry->g_id = 63; - } else if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE) - || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { - entry->p_aid = 0; - entry->g_id = 63; - } else { - bssid = sta->hwaddr; - /* BSSID[39:47] */ - entry->p_aid = (bssid[5] << 1) | (bssid[4] >> 7); - entry->g_id = 0; - } - RTW_INFO("%s: p_aid=0x%04x g_id=0x%04x aid=0x%x\n", - __FUNCTION__, entry->p_aid, entry->g_id, sta->aid); - - _rtw_memcpy(entry->mac_addr, sta->hwaddr, ETH_ALEN); - entry->cap = bf_cap; - entry->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT; - entry->NumofSoundingDim = sounding_dim; - - if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_MU)) { - bf_info->beamformer_mu_cnt += 1; - entry->aid = sta->aid; - } else if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) { - bf_info->beamformer_su_cnt += 1; + bfee->used = _TRUE; + bfee->aid = sta->aid; + bfee->mac_id = sta->mac_id; + bfee->sound_bw = sta->bw_mode; + + _get_txvector_parameter(adapter, sta, &bfee->g_id, &bfee->p_aid); + sta->txbf_gid = bfee->g_id; + sta->txbf_paid = bfee->p_aid; + + _rtw_memcpy(bfee->mac_addr, sta->hwaddr, ETH_ALEN); + bfee->txbf = _FALSE; + bfee->sounding = _FALSE; + bfee->sound_period = 40; + _sounding_update_min_period(adapter, bfee->sound_period, _FALSE); + bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, info->sounding_info.min_sounding_period); + bfee->cap = bf_cap; + bfee->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT; + + bfee->bCandidateSoundingPeer = _FALSE; + bfee->bSoundingTimeout = _FALSE; + bfee->bDeleteSounding = _FALSE; + bfee->bApplySounding = _TRUE; + + bfee->tx_timestamp = 0; + bfee->tx_bytes = 0; + + bfee->LogStatusFailCnt = 0; + bfee->NumofSoundingDim = sounding_dim; + bfee->comp_steering_num_of_bfer = comp_steering; + bfee->bSuspendSUCap = _FALSE; - /* Record HW idx info */ - for (i = 0; i < MAX_NUM_BEAMFORMER_SU; i++) { - if ((bf_info->beamformer_su_reg_maping & BIT(i)) == 0) { - bf_info->beamformer_su_reg_maping |= BIT(i); - entry->su_reg_index = i; - break; + if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_MU)) { + info->beamformee_mu_cnt += 1; + info->first_mu_bfee_index = _bfee_get_first_mu_entry_idx(adapter, NULL); + + if (_TRUE == info->bEnableSUTxBFWorkAround) { + /* When the first MU BFee added, discard SU BFee bfee's capability */ + if ((info->beamformee_mu_cnt == 1) && (info->beamformee_su_cnt > 0)) { + if (info->TargetSUBFee) { + info->TargetSUBFee->bSuspendSUCap = _TRUE; + info->TargetSUBFee->bDeleteSounding = _TRUE; + } else { + RTW_ERR("%s: UNEXPECTED!! info->TargetSUBFee is NULL!", __FUNCTION__); + } + info->TargetSUBFee = NULL; + _rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO)); + rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 0); } } - RTW_INFO("%s: Add BFer entry beamformer_su_reg_maping=%#X, su_reg_index=%d\n", - __FUNCTION__, bf_info->beamformer_su_reg_maping, entry->su_reg_index); - } - - return entry; -} - -static struct beamformee_entry *_add_bfee_entry(PADAPTER adapter, - struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering) -{ - struct mlme_priv *mlme; - struct beamforming_info *bf_info; - struct beamformee_entry *entry; - u8 *bssid; - u16 val16; - u8 i; - - - mlme = &adapter->mlmepriv; - bf_info = GET_BEAMFORM_INFO(adapter); - - entry = beamforming_get_bfee_entry_by_addr(adapter, sta->hwaddr); - if (!entry) { - entry = _get_bfee_free_entry(adapter); - if (!entry) - return NULL; - } - - entry->used = _TRUE; - entry->aid = sta->aid; - entry->mac_id = sta->mac_id; - entry->sound_bw = sta->bw_mode; - - if (check_fwstate(mlme, WIFI_AP_STATE)) { - bssid = adapter_mac_addr(adapter); - /* BSSID[44:47] xor BSSID[40:43] */ - val16 = ((bssid[5] & 0xF0) >> 4) ^ (bssid[5] & 0xF); - /* (dec(A) + dec(B)*32) mod 512 */ - entry->p_aid = (sta->aid + val16 * 32) & 0x1FF; - entry->g_id = 63; - } else if (check_fwstate(mlme, WIFI_ADHOC_STATE) || check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE)) { - entry->p_aid = 0; - entry->g_id = 63; - } else { - bssid = sta->hwaddr; - /* BSSID[39:47] */ - entry->p_aid = (bssid[5] << 1) | (bssid[4] >> 7); - entry->g_id = 0; - } - - _rtw_memcpy(entry->mac_addr, sta->hwaddr, ETH_ALEN); - entry->txbf = _FALSE; - entry->sounding = _FALSE; - entry->sound_period = 40; - entry->cap = bf_cap; - - _update_min_sounding_period(adapter, entry->sound_period, _FALSE); - entry->SoundCnt = GetInitSoundCnt(entry->sound_period, bf_info->sounding_info.min_sounding_period); - - entry->LogStatusFailCnt = 0; - - entry->NumofSoundingDim = sounding_dim; - entry->CompSteeringNumofBFer = comp_steering; - entry->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT; - - if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_MU)) { - bf_info->beamformee_mu_cnt += 1; - bf_info->first_mu_bfee_index = _get_first_mu_bfee_entry_idx(adapter, NULL); /* Record HW idx info */ for (i = 0; i < MAX_NUM_BEAMFORMEE_MU; i++) { - if ((bf_info->beamformee_mu_reg_maping & BIT(i)) == 0) { - bf_info->beamformee_mu_reg_maping |= BIT(i); - entry->mu_reg_index = i; + if ((info->beamformee_mu_reg_maping & BIT(i)) == 0) { + info->beamformee_mu_reg_maping |= BIT(i); + bfee->mu_reg_index = i; break; } } - RTW_INFO("%s: Add BFee entry beamformee_mu_reg_maping=%#X, mu_reg_index=%d\n", - __FUNCTION__, bf_info->beamformee_mu_reg_maping, entry->mu_reg_index); + RTW_INFO("%s: Add BFee entry beamformee_mu_reg_maping=%#x, mu_reg_index=%d\n", + __FUNCTION__, info->beamformee_mu_reg_maping, bfee->mu_reg_index); } else if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) { - bf_info->beamformee_su_cnt += 1; + info->beamformee_su_cnt += 1; + + if (_TRUE == info->bEnableSUTxBFWorkAround) { + /* Record the first SU BFee index. We only allow the first SU BFee to be sound */ + if ((info->beamformee_su_cnt == 1) && (info->beamformee_mu_cnt == 0)) { + info->TargetSUBFee = bfee; + _rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO)); + bfee->bSuspendSUCap = _FALSE; + } else { + bfee->bSuspendSUCap = _TRUE; + } + } /* Record HW idx info */ for (i = 0; i < MAX_NUM_BEAMFORMEE_SU; i++) { - if ((bf_info->beamformee_su_reg_maping & BIT(i)) == 0) { - bf_info->beamformee_su_reg_maping |= BIT(i); - entry->su_reg_index = i; + if ((info->beamformee_su_reg_maping & BIT(i)) == 0) { + info->beamformee_su_reg_maping |= BIT(i); + bfee->su_reg_index = i; break; } } - RTW_INFO("%s: Add BFee entry beamformee_su_reg_maping=%#X, su_reg_index=%d\n", - __FUNCTION__, bf_info->beamformee_su_reg_maping, entry->su_reg_index); - } - - return entry; -} - -static void _remove_bfer_entry(PADAPTER adapter, struct beamformer_entry *entry) -{ - struct beamforming_info *bf_info; - - - bf_info = GET_BEAMFORM_INFO(adapter); - - entry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT; - - if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_MU)) { - bf_info->beamformer_mu_cnt -= 1; - _rtw_memset(entry->gid_valid, 0, 8); - _rtw_memset(entry->user_position, 0, 16); - } else if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) { - bf_info->beamformer_su_cnt -= 1; + RTW_INFO("%s: Add BFee entry beamformee_su_reg_maping=%#x, su_reg_index=%d\n", + __FUNCTION__, info->beamformee_su_reg_maping, bfee->su_reg_index); } - if (bf_info->beamformer_mu_cnt == 0) - bf_info->beamforming_cap &= ~BEAMFORMEE_CAP_VHT_MU; - if (bf_info->beamformer_su_cnt == 0) - bf_info->beamforming_cap &= ~(BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT); + return bfee; } -static void _remove_bfee_entry(PADAPTER adapter, struct beamformee_entry *entry) +static void _bfee_remove_entry(PADAPTER adapter, struct beamformee_entry *entry) { - struct beamforming_info *bf_info; + struct beamforming_info *info; + u8 idx; - bf_info = GET_BEAMFORM_INFO(adapter); + info = GET_BEAMFORM_INFO(adapter); entry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT; if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_MU)) { - bf_info->beamformee_mu_cnt -= 1; - bf_info->first_mu_bfee_index = _get_first_mu_bfee_entry_idx(adapter, entry); + info->beamformee_mu_cnt -= 1; + info->first_mu_bfee_index = _bfee_get_first_mu_entry_idx(adapter, entry); + + if (_TRUE == info->bEnableSUTxBFWorkAround) { + if ((info->beamformee_mu_cnt == 0) && (info->beamformee_su_cnt > 0)) { + idx = _bfee_get_first_su_entry_idx(adapter, NULL); + info->TargetSUBFee = &info->bfee_entry[idx]; + _rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO)); + info->TargetSUBFee->bSuspendSUCap = _FALSE; + } + } } else if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) { - bf_info->beamformee_su_cnt -= 1; + info->beamformee_su_cnt -= 1; + + /* When the target SU BFee leaves, disable workaround */ + if ((_TRUE == info->bEnableSUTxBFWorkAround) + && (entry == info->TargetSUBFee)) { + entry->bSuspendSUCap = _TRUE; + info->TargetSUBFee = NULL; + _rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO)); + rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 0); + } } - if (bf_info->beamformee_mu_cnt == 0) - bf_info->beamforming_cap &= ~BEAMFORMER_CAP_VHT_MU; - if (bf_info->beamformee_su_cnt == 0) - bf_info->beamforming_cap &= ~(BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT); + if (info->beamformee_mu_cnt == 0) + info->beamforming_cap &= ~BEAMFORMER_CAP_VHT_MU; + if (info->beamformee_su_cnt == 0) + info->beamforming_cap &= ~(BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT); - _update_min_sounding_period(adapter, 0, _TRUE); + _sounding_update_min_period(adapter, 0, _TRUE); } -/* - * Parameters - * adapter struct _adapter* - * sta struct sta_info* - * sta_bf_cap beamforming capabe of sta - * sounding_dim Number of Sounding Dimensions - * comp_steering Compressed Steering Number of Beamformer Antennas Supported - */ -static void _get_sta_beamform_cap(PADAPTER adapter, struct sta_info *sta, - u8 *sta_bf_cap, u8 *sounding_dim, u8 *comp_steering) +static enum beamforming_cap _bfee_get_entry_cap_by_macid(PADAPTER adapter, u8 macid) { - struct ht_priv *ht; -#ifdef CONFIG_80211AC_VHT - struct vht_priv *vht; -#endif /* CONFIG_80211AC_VHT */ - u16 bf_cap; - - - *sta_bf_cap = 0; - *sounding_dim = 0; - *comp_steering = 0; + struct beamforming_info *info; + struct beamformee_entry *bfee; + u8 i; - ht = &adapter->mlmepriv.htpriv; -#ifdef CONFIG_80211AC_VHT - vht = &adapter->mlmepriv.vhtpriv; -#endif /* CONFIG_80211AC_VHT */ - if (IsSupportedHT(sta->wireless_mode) == _TRUE) { - /* HT */ - bf_cap = ht->beamform_cap; + info = GET_BEAMFORM_INFO(adapter); - if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) { - *sta_bf_cap |= BEAMFORMER_CAP_HT_EXPLICIT; - *sounding_dim = (bf_cap & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6; - } - if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { - *sta_bf_cap |= BEAMFORMEE_CAP_HT_EXPLICIT; - *comp_steering = (bf_cap & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4; - } + for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) { + bfee = &info->bfee_entry[i]; + if (bfee->used == _FALSE) + continue; + if (bfee->mac_id == macid) + return bfee->cap; } -#ifdef CONFIG_80211AC_VHT - if (IsSupportedVHT(sta->wireless_mode) == _TRUE) { - /* VHT */ - bf_cap = vht->beamform_cap; - - /* We are SU Beamformee because the STA is SU Beamformer */ - if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) { - *sta_bf_cap |= BEAMFORMER_CAP_VHT_SU; - - /* We are MU Beamformee because the STA is MU Beamformer */ - if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) - *sta_bf_cap |= BEAMFORMER_CAP_VHT_MU; - - *sounding_dim = (bf_cap & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; - } - /* We are SU Beamformer because the STA is SU Beamformee */ - if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { - *sta_bf_cap |= BEAMFORMEE_CAP_VHT_SU; - - /* We are MU Beamformer because the STA is MU Beamformee */ - if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) - *sta_bf_cap |= BEAMFORMEE_CAP_VHT_MU; - - *comp_steering = (bf_cap & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; - } - } -#endif /* CONFIG_80211AC_VHT */ + return BEAMFORMING_CAP_NONE; } -/* - * Return: - * _TRUE success - * _FALSE fail - */ -static u8 _init_entry(PADAPTER adapter, struct sta_info *sta) + +static void _beamforming_enter(PADAPTER adapter, void *p) { struct mlme_priv *mlme; struct ht_priv *htpriv; @@ -490,10 +1361,10 @@ static u8 _init_entry(PADAPTER adapter, struct sta_info *sta) struct vht_priv *vhtpriv; #endif struct mlme_ext_priv *mlme_ext; - struct sta_info *sta_real; + struct sta_info *sta, *sta_copy; + struct beamforming_info *info; struct beamformer_entry *bfer = NULL; struct beamformee_entry *bfee = NULL; - u8 *ra; u8 wireless_mode; u8 sta_bf_cap; u8 sounding_dim = 0; /* number of sounding dimensions */ @@ -506,14 +1377,27 @@ static u8 _init_entry(PADAPTER adapter, struct sta_info *sta) vhtpriv = &mlme->vhtpriv; #endif mlme_ext = &adapter->mlmeextpriv; - ra = sta->hwaddr; - wireless_mode = sta->wireless_mode; - sta_real = rtw_get_stainfo(&adapter->stapriv, ra); + info = GET_BEAMFORM_INFO(adapter); + + sta_copy = (struct sta_info *)p; + sta = rtw_get_stainfo(&adapter->stapriv, sta_copy->hwaddr); + if (!sta) { + RTW_ERR("%s: Cann't find STA info for " MAC_FMT "\n", + __FUNCTION__, MAC_ARG(sta_copy->hwaddr)); + return; + } + if (sta != sta_copy) { + RTW_WARN("%s: Origin sta(fake)=%p realsta=%p for " MAC_FMT "\n", + __FUNCTION__, sta_copy, sta, MAC_ARG(sta_copy->hwaddr)); + } /* The current setting does not support Beaforming */ - if ((IsSupportedHT(wireless_mode) == _FALSE) - && (IsSupportedVHT(wireless_mode) == _FALSE)) - return _FALSE; + wireless_mode = sta->wireless_mode; + if ((is_supported_ht(wireless_mode) == _FALSE) + && (is_supported_vht(wireless_mode) == _FALSE)) { + RTW_WARN("%s: Not support HT or VHT mode\n", __FUNCTION__); + return; + } if ((0 == htpriv->beamform_cap) #ifdef CONFIG_80211AC_VHT @@ -521,51 +1405,59 @@ static u8 _init_entry(PADAPTER adapter, struct sta_info *sta) #endif ) { RTW_INFO("The configuration disabled Beamforming! Skip...\n"); - return _FALSE; + return; } _get_sta_beamform_cap(adapter, sta, &sta_bf_cap, &sounding_dim, &comp_steering_num); RTW_INFO("STA Beamforming Capability=0x%02X\n", sta_bf_cap); - if (sta_bf_cap == BEAMFORMING_CAP_NONE) - return _FALSE; - + return; if ((sta_bf_cap & BEAMFORMEE_CAP_HT_EXPLICIT) || (sta_bf_cap & BEAMFORMEE_CAP_VHT_SU) || (sta_bf_cap & BEAMFORMEE_CAP_VHT_MU)) sta_bf_cap |= BEAMFORMEE_CAP; - else + if ((sta_bf_cap & BEAMFORMER_CAP_HT_EXPLICIT) + || (sta_bf_cap & BEAMFORMER_CAP_VHT_SU) + || (sta_bf_cap & BEAMFORMER_CAP_VHT_MU)) sta_bf_cap |= BEAMFORMER_CAP; if (sta_bf_cap & BEAMFORMER_CAP) { /* The other side is beamformer */ - bfer = _add_bfer_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num); - if (bfer == NULL) { + bfer = _bfer_add_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num); + if (!bfer) RTW_ERR("%s: Fail to allocate bfer entry!\n", __FUNCTION__); - return _FALSE; - } - - sta_real->txbf_paid = bfer->p_aid; - sta_real->txbf_gid = bfer->g_id; - } else { + } + if (sta_bf_cap & BEAMFORMEE_CAP) { /* The other side is beamformee */ - bfee = _add_bfee_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num); - if (bfee == NULL) { + bfee = _bfee_add_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num); + if (!bfee) RTW_ERR("%s: Fail to allocate bfee entry!\n", __FUNCTION__); - return _FALSE; - } + } + if (!bfer && !bfee) + return; + + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_ENTER, (u8*)sta); - sta_real->txbf_paid = bfee->p_aid; - sta_real->txbf_gid = bfee->g_id; + /* Perform sounding if there is BFee */ + if ((info->beamformee_su_cnt != 0) + || (info->beamformee_mu_cnt != 0)) { + if (SOUNDING_STATE_NONE == info->sounding_info.state) { + info->sounding_info.state = SOUNDING_STATE_INIT; + /* Start sounding after 2 sec */ + _set_timer(&info->sounding_timer, 2000); + } } +} - return _TRUE; +static void _beamforming_reset(PADAPTER adapter) +{ + RTW_ERR("%s: Not ready!!\n", __FUNCTION__); } -static void _deinit_entry(PADAPTER adapter, u8 *ra) +static void _beamforming_leave(PADAPTER adapter, u8 *ra) { - struct beamforming_info *bf_info; + struct beamforming_info *info; struct beamformer_entry *bfer = NULL; struct beamformee_entry *bfee = NULL; u8 bHwStateAddInit = _FALSE; @@ -573,9 +1465,9 @@ static void _deinit_entry(PADAPTER adapter, u8 *ra) RTW_INFO("+%s\n", __FUNCTION__); - bf_info = GET_BEAMFORM_INFO(adapter); - bfer = beamforming_get_bfer_entry_by_addr(adapter, ra); - bfee = beamforming_get_bfee_entry_by_addr(adapter, ra); + info = GET_BEAMFORM_INFO(adapter); + bfer = _bfer_get_entry_by_addr(adapter, ra); + bfee = _bfee_get_entry_by_addr(adapter, ra); if (!bfer && !bfee) { RTW_WARN("%s: " MAC_FMT " is neither beamforming ee or er!!\n", @@ -583,58 +1475,226 @@ static void _deinit_entry(PADAPTER adapter, u8 *ra) return; } - if (bfer && bfee) - RTW_ERR("%s: " MAC_FMT " is both beamforming ee & er!!\n", - __FUNCTION__, MAC_ARG(ra)); + if (bfer) + _bfer_remove_entry(adapter, bfer); + + if (bfee) + _bfee_remove_entry(adapter, bfee); + + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_LEAVE, ra); + + /* Stop sounding if there is no any BFee */ + if ((info->beamformee_su_cnt == 0) + && (info->beamformee_mu_cnt == 0)) { + _cancel_timer_ex(&info->sounding_timer); + _sounding_init(&info->sounding_info); + } + + RTW_INFO("-%s\n", __FUNCTION__); +} + +static void _beamforming_sounding_down(PADAPTER adapter, u8 status) +{ + struct beamforming_info *info; + struct sounding_info *sounding; + struct beamformee_entry *bfee; + + + info = GET_BEAMFORM_INFO(adapter); + sounding = &info->sounding_info; + + RTW_INFO("+%s: sounding=%d, status=0x%02x\n", __FUNCTION__, sounding->state, status); + + if (sounding->state == SOUNDING_STATE_MU_START) { + RTW_INFO("%s: MU sounding done\n", __FUNCTION__); + sounding->state = SOUNDING_STATE_MU_SOUNDDOWN; + RTW_INFO("%s: Set to SOUNDING_STATE_MU_SOUNDDOWN\n", __FUNCTION__); + info->SetHalSoundownOnDemandCnt++; + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status); + } else if (sounding->state == SOUNDING_STATE_SU_START) { + RTW_INFO("%s: SU entry[%d] sounding down\n", __FUNCTION__, sounding->su_bfee_curidx); + bfee = &info->bfee_entry[sounding->su_bfee_curidx]; + sounding->state = SOUNDING_STATE_SU_SOUNDDOWN; + RTW_INFO("%s: Set to SOUNDING_STATE_SU_SOUNDDOWN\n", __FUNCTION__); + + /* + * + * bfee->bSoundingTimeout this flag still cannot avoid + * old sound down event happens in the new sounding period. + * 2015.12.10 + */ + if (_TRUE == bfee->bSoundingTimeout) { + RTW_WARN("%s: The entry[%d] is bSoundingTimeout!\n", __FUNCTION__, sounding->su_bfee_curidx); + bfee->bSoundingTimeout = _FALSE; + return; + } + + if (_TRUE == status) { + /* success */ + bfee->LogStatusFailCnt = 0; + info->SetHalSoundownOnDemandCnt++; + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status); + } else if (_TRUE == bfee->bDeleteSounding) { + RTW_WARN("%s: Delete entry[%d] sounding info!\n", __FUNCTION__, sounding->su_bfee_curidx); + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status); + bfee->bDeleteSounding = _FALSE; + } else { + bfee->LogStatusFailCnt++; + RTW_WARN("%s: LogStatusFailCnt=%d\n", __FUNCTION__, bfee->LogStatusFailCnt); + if (bfee->LogStatusFailCnt > 30) { + RTW_ERR("%s: LogStatusFailCnt > 30, Stop SOUNDING!!\n", __FUNCTION__); + rtw_bf_cmd(adapter, BEAMFORMING_CTRL_LEAVE, bfee->mac_addr, ETH_ALEN, 1); + } + } + } else { + RTW_WARN("%s: unexpected sounding state:0x%02x\n", __FUNCTION__, sounding->state); + return; + } + + rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 0); +} + +static void _c2h_snd_txbf(PADAPTER adapter, u8 *buf, u8 buf_len) +{ + struct beamforming_info *info; + u8 res; + + info = GET_BEAMFORM_INFO(adapter); + + _cancel_timer_ex(&info->sounding_timeout_timer); + + res = C2H_SND_TXBF_GET_SND_RESULT(buf) ? _TRUE : _FALSE; + RTW_INFO("+%s: %s\n", __FUNCTION__, res==_TRUE?"Success":"Fail!"); + + rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 1); +} - if (bfer) - _remove_bfer_entry(adapter, bfer); +/* + * Description: + * This function is for phydm only + */ +enum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlme, u8 macid) +{ + PADAPTER adapter; + enum beamforming_cap cap = BEAMFORMING_CAP_NONE; - if (bfee) - _remove_bfee_entry(adapter, bfee); - rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_LEAVE, ra); + adapter = mlme_to_adapter((struct mlme_priv *)mlme); + cap = _bfee_get_entry_cap_by_macid(adapter, macid); - RTW_DBG("-%s\n", __FUNCTION__); + return cap; } -void _beamforming_reset(PADAPTER adapter) +struct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra) { - RTW_ERR("%s: Not ready!!\n", __FUNCTION__); + return _bfer_get_entry_by_addr(adapter, ra); } -void beamforming_enter(PADAPTER adapter, void *sta) +struct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra) { - u8 ret; - - ret = _init_entry(adapter, (struct sta_info *)sta); - if (ret == _FALSE) - return; - - rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_ENTER, sta); + return _bfee_get_entry_by_addr(adapter, ra); } -void beamforming_leave(PADAPTER adapter, u8 *ra) +void rtw_bf_get_ndpa_packet(PADAPTER adapter, union recv_frame *precv_frame) { - if (ra == NULL) - _beamforming_reset(adapter); - else - _deinit_entry(adapter, ra); + RTW_DBG("+%s\n", __FUNCTION__); } -void beamforming_sounding_fail(PADAPTER adapter) +u32 rtw_bf_get_report_packet(PADAPTER adapter, union recv_frame *precv_frame) { - RTW_ERR("+%s: not implemented yet!\n", __FUNCTION__); + u32 ret = _SUCCESS; + struct beamforming_info *info; + struct beamformee_entry *bfee = NULL; + u8 *pframe; + u32 frame_len; + u8 *ta; + u8 *frame_body; + u8 category, action; + u8 *pMIMOCtrlField, *pCSIMatrix; + u8 Nc = 0, Nr = 0, CH_W = 0, Ng = 0, CodeBook = 0; + u16 CSIMatrixLen = 0; + + + RTW_INFO("+%s\n", __FUNCTION__); + + info = GET_BEAMFORM_INFO(adapter); + pframe = precv_frame->u.hdr.rx_data; + frame_len = precv_frame->u.hdr.len; + + /* Memory comparison to see if CSI report is the same with previous one */ + ta = get_addr2_ptr(pframe); + bfee = _bfee_get_entry_by_addr(adapter, ta); + if (!bfee) + return _FAIL; + + frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + category = frame_body[0]; + action = frame_body[1]; + + if ((category == RTW_WLAN_CATEGORY_VHT) + && (action == RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING)) { + pMIMOCtrlField = pframe + 26; + Nc = (*pMIMOCtrlField) & 0x7; + Nr = ((*pMIMOCtrlField) & 0x38) >> 3; + CH_W = (((*pMIMOCtrlField) & 0xC0) >> 6); + Ng = (*(pMIMOCtrlField+1)) & 0x3; + CodeBook = ((*(pMIMOCtrlField+1)) & 0x4) >> 2; + /* + * 24+(1+1+3)+2 + * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2) + */ + pCSIMatrix = pMIMOCtrlField + 3 + Nc; + CSIMatrixLen = frame_len - 26 - 3 - Nc; + info->TargetCSIInfo.bVHT = _TRUE; + } else if ((category == RTW_WLAN_CATEGORY_HT) + && (action == RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING)) { + pMIMOCtrlField = pframe + 26; + Nc = (*pMIMOCtrlField) & 0x3; + Nr = ((*pMIMOCtrlField) & 0xC) >> 2; + CH_W = ((*pMIMOCtrlField) & 0x10) >> 4; + Ng = ((*pMIMOCtrlField) & 0x60) >> 5; + CodeBook = ((*(pMIMOCtrlField+1)) & 0x6) >> 1; + /* + * 24+(1+1+6)+2 + * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2) + */ + pCSIMatrix = pMIMOCtrlField + 6 + Nr; + CSIMatrixLen = frame_len - 26 - 6 - Nr; + info->TargetCSIInfo.bVHT = _FALSE; + } + + /* Update current CSI report info */ + if ((_TRUE == info->bEnableSUTxBFWorkAround) + && (info->TargetSUBFee == bfee)) { + if ((info->TargetCSIInfo.Nc != Nc) || (info->TargetCSIInfo.Nr != Nr) || + (info->TargetCSIInfo.ChnlWidth != CH_W) || (info->TargetCSIInfo.Ng != Ng) || + (info->TargetCSIInfo.CodeBook != CodeBook)) { + info->TargetCSIInfo.Nc = Nc; + info->TargetCSIInfo.Nr = Nr; + info->TargetCSIInfo.ChnlWidth = CH_W; + info->TargetCSIInfo.Ng = Ng; + info->TargetCSIInfo.CodeBook = CodeBook; + + rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 1); + } + } + + RTW_INFO("%s: pkt type=%d-%d, Nc=%d, Nr=%d, CH_W=%d, Ng=%d, CodeBook=%d\n", + __FUNCTION__, category, action, Nc, Nr, CH_W, Ng, CodeBook); + + return ret; } -u8 beamforming_send_vht_gid_mgnt_packet(PADAPTER adapter, struct beamformee_entry *entry) +u8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER adapter, u8 *ra, u8 *gid, u8 *position) { + /* General */ struct xmit_priv *xmitpriv; struct mlme_priv *mlmepriv; struct xmit_frame *pmgntframe; + /* MISC */ struct pkt_attrib *attrib; struct rtw_ieee80211_hdr *wlanhdr; - u8 *pframe; + u8 *pframe, *ptr; xmitpriv = &adapter->xmitpriv; @@ -657,19 +1717,23 @@ u8 beamforming_send_vht_gid_mgnt_packet(PADAPTER adapter, struct beamformee_entr wlanhdr = (struct rtw_ieee80211_hdr *)pframe; wlanhdr->frame_ctl = 0; - SetFrameSubType(pframe, attrib->subtype); - SetDuration(pframe, 0); + set_frame_sub_type(pframe, attrib->subtype); + set_duration(pframe, 0); SetFragNum(pframe, 0); SetSeqNum(pframe, 0); - _rtw_memcpy(wlanhdr->addr1, entry->mac_addr, ETH_ALEN); + _rtw_memcpy(wlanhdr->addr1, ra, ETH_ALEN); _rtw_memcpy(wlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); _rtw_memcpy(wlanhdr->addr3, get_bssid(mlmepriv), ETH_ALEN); pframe[24] = RTW_WLAN_CATEGORY_VHT; pframe[25] = RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT; - _rtw_memcpy(&pframe[26], entry->gid_valid, 8); - _rtw_memcpy(&pframe[34], entry->user_position, 16); + /* Set Membership Status Array */ + ptr = pframe + 26; + _rtw_memcpy(ptr, gid, 8); + /* Set User Position Array */ + ptr = pframe + 34; + _rtw_memcpy(ptr, position, 16); attrib->pktlen = 54; attrib->last_txcmdsz = attrib->pktlen; @@ -679,11 +1743,267 @@ u8 beamforming_send_vht_gid_mgnt_packet(PADAPTER adapter, struct beamformee_entr return _TRUE; } -void beamforming_watchdog(PADAPTER adapter) +/* + * Description: + * On VHT GID management frame by an MU beamformee. + */ +void rtw_bf_get_vht_gid_mgnt_packet(PADAPTER adapter, union recv_frame *precv_frame) +{ + u8 *pframe; + u8 *ta, *gid, *position; + + + RTW_DBG("+%s\n", __FUNCTION__); + + pframe = precv_frame->u.hdr.rx_data; + + /* Get address by Addr2 */ + ta = get_addr2_ptr(pframe); + /* Remove signaling TA */ + ta[0] &= 0xFE; + + /* Membership Status Array */ + gid = pframe + 26; + /* User Position Array */ + position= pframe + 34; + + _bfer_set_entry_gid(adapter, ta, gid, position); +} + +void rtw_bf_init(PADAPTER adapter) +{ + struct beamforming_info *info; + + + info = GET_BEAMFORM_INFO(adapter); + info->beamforming_cap = BEAMFORMING_CAP_NONE; + info->beamforming_state = BEAMFORMING_STATE_IDLE; +/* + info->bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM]; + info->bfer_entry[MAX_BEAMFORMER_ENTRY_NUM]; +*/ + info->sounding_sequence = 0; + info->beamformee_su_cnt = 0; + info->beamformer_su_cnt = 0; + info->beamformee_su_reg_maping = 0; + info->beamformer_su_reg_maping = 0; + info->beamformee_mu_cnt = 0; + info->beamformer_mu_cnt = 0; + info->beamformee_mu_reg_maping = 0; + info->first_mu_bfee_index = 0xFF; + info->mu_bfer_curidx = 0xFF; + info->cur_csi_rpt_rate = HALMAC_OFDM24; + + _sounding_init(&info->sounding_info); + rtw_init_timer(&info->sounding_timer, adapter, _sounding_timer_handler, adapter); + rtw_init_timer(&info->sounding_timeout_timer, adapter, _sounding_timeout_timer_handler, adapter); + + info->SetHalBFEnterOnDemandCnt = 0; + info->SetHalBFLeaveOnDemandCnt = 0; + info->SetHalSoundownOnDemandCnt = 0; + + info->bEnableSUTxBFWorkAround = _TRUE; + info->TargetSUBFee = NULL; + + info->sounding_running = 0; +} + +void rtw_bf_cmd_hdl(PADAPTER adapter, u8 type, u8 *pbuf) +{ + switch (type) { + case BEAMFORMING_CTRL_ENTER: + _beamforming_enter(adapter, pbuf); + break; + + case BEAMFORMING_CTRL_LEAVE: + if (pbuf == NULL) + _beamforming_reset(adapter); + else + _beamforming_leave(adapter, pbuf); + break; + + case BEAMFORMING_CTRL_START_PERIOD: + _sounding_handler(adapter); + break; + + case BEAMFORMING_CTRL_END_PERIOD: + _beamforming_sounding_down(adapter, *pbuf); + break; + + case BEAMFORMING_CTRL_SET_GID_TABLE: + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_SET_GID_TABLE, pbuf); + break; + + case BEAMFORMING_CTRL_SET_CSI_REPORT: + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_CSI_REPORT, pbuf); + break; + + default: + break; + } +} + +u8 rtw_bf_cmd(PADAPTER adapter, s32 type, u8 *pbuf, s32 size, u8 enqueue) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + u8 *wk_buf; + u8 res = _SUCCESS; + + + if (!enqueue) { + rtw_bf_cmd_hdl(adapter, type, pbuf); + goto exit; + } + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + if (pbuf != NULL) { + wk_buf = rtw_zmalloc(size); + if (wk_buf == NULL) { + rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + _rtw_memcpy(wk_buf, pbuf, size); + } else { + wk_buf = NULL; + size = 0; + } + + pdrvextra_cmd_parm->ec_id = BEAMFORMING_WK_CID; + pdrvextra_cmd_parm->type = type; + pdrvextra_cmd_parm->size = size; + pdrvextra_cmd_parm->pbuf = wk_buf; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + return res; +} + +void rtw_bf_update_attrib(PADAPTER adapter, struct pkt_attrib *attrib, struct sta_info *sta) +{ + if (sta) { + attrib->txbf_g_id = sta->txbf_gid; + attrib->txbf_p_aid = sta->txbf_paid; + } +} + +void rtw_bf_c2h_handler(PADAPTER adapter, u8 id, u8 *buf, u8 buf_len) +{ + switch (id) { + case CMD_ID_C2H_SND_TXBF: + _c2h_snd_txbf(adapter, buf, buf_len); + break; + } +} + +#define toMbps(bytes, secs) (rtw_division64(bytes >> 17, secs)) +void rtw_bf_update_traffic(PADAPTER adapter) { + struct beamforming_info *info; + struct sounding_info *sounding; + struct beamformee_entry *bfee; + struct sta_info *sta; + u8 bfee_cnt, sounding_idx, i; + u16 tp[MAX_BEAMFORMEE_ENTRY_NUM] = {0}; + u8 tx_rate[MAX_BEAMFORMEE_ENTRY_NUM] = {0}; + u64 tx_bytes, last_bytes; + u32 time, last_timestamp; + u8 set_timer = _FALSE; + + + info = GET_BEAMFORM_INFO(adapter); + sounding = &info->sounding_info; + + /* Check any bfee exist? */ + bfee_cnt = info->beamformee_su_cnt + info->beamformee_mu_cnt; + if (bfee_cnt == 0) + return; + + for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { + bfee = &info->bfee_entry[i]; + if (_FALSE == bfee->used) + continue; + + sta = rtw_get_stainfo(&adapter->stapriv, bfee->mac_addr); + if (!sta) { + RTW_ERR("%s: Cann't find sta_info for " MAC_FMT "!\n", __FUNCTION__, MAC_ARG(bfee->mac_addr)); + continue; + } + + last_timestamp = bfee->tx_timestamp; + last_bytes = bfee->tx_bytes; + bfee->tx_timestamp = rtw_get_current_time(); + bfee->tx_bytes = sta->sta_stats.tx_bytes; + if (last_timestamp) { + if (bfee->tx_bytes >= last_bytes) + tx_bytes = bfee->tx_bytes - last_bytes; + else + tx_bytes = bfee->tx_bytes + (~last_bytes); + time = rtw_get_time_interval_ms(last_timestamp, bfee->tx_timestamp); + time = (time > 1000) ? time/1000 : 1; + tp[i] = toMbps(tx_bytes, time); + tx_rate[i] = rtw_get_current_tx_rate(adapter, bfee->mac_id); + RTW_INFO("%s: BFee idx(%d), MadId(%d), TxTP=%lld bytes (%d Mbps), txrate=%d\n", + __FUNCTION__, i, bfee->mac_id, tx_bytes, tp[i], tx_rate[i]); + } + } + + sounding_idx = phydm_get_beamforming_sounding_info(GET_PDM_ODM(adapter), tp, MAX_BEAMFORMEE_ENTRY_NUM, tx_rate); + + for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { + bfee = &info->bfee_entry[i]; + if (_FALSE == bfee->used) { + if (sounding_idx & BIT(i)) + RTW_WARN("%s: bfee(%d) not in used but need sounding?!\n", __FUNCTION__, i); + continue; + } + + if (sounding_idx & BIT(i)) { + if (_FALSE == bfee->bApplySounding) { + bfee->bApplySounding = _TRUE; + bfee->SoundCnt = 0; + set_timer = _TRUE; + } + } else { + if (_TRUE == bfee->bApplySounding) { + bfee->bApplySounding = _FALSE; + bfee->bDeleteSounding = _TRUE; + bfee->SoundCnt = 0; + set_timer = _TRUE; + } + } + } + + if (_TRUE == set_timer) { + if (SOUNDING_STATE_NONE == info->sounding_info.state) { + info->sounding_info.state = SOUNDING_STATE_INIT; + _set_timer(&info->sounding_timer, 0); + } + } } + #else /* !RTW_BEAMFORMING_VERSION_2 */ +#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/ struct beamforming_entry *beamforming_get_entry_by_addr(struct mlme_priv *pmlmepriv, u8 *ra, u8 *idx) { u8 i = 0; @@ -796,7 +2116,7 @@ void beamforming_dym_ndpa_rate(PADAPTER adapter) u16 NDPARate = MGN_6M; PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); - if (pHalData->MinUndecoratedPWDBForDM > 30) /* link RSSI > 30% */ + if (pHalData->min_undecorated_pwdb_for_dm > 30) /* link RSSI > 30% */ NDPARate = MGN_24M; else NDPARate = MGN_6M; @@ -891,8 +2211,8 @@ BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 q fctrl = &pwlanhdr->frame_ctl; *(fctrl) = 0; - SetOrderBit(pframe); - SetFrameSubType(pframe, WIFI_ACTION_NOACK); + set_order_bit(pframe); + set_frame_sub_type(pframe, WIFI_ACTION_NOACK); _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN); @@ -910,7 +2230,7 @@ BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 q else duration += 180; - SetDuration(pframe, duration); + set_duration(pframe, duration); /*HT control field*/ SET_HT_CTRL_CSI_STEERING(pframe + 24, 3); @@ -967,8 +2287,8 @@ BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx fctrl = &pwlanhdr->frame_ctl; *(fctrl) = 0; - SetOrderBit(pframe); - SetFrameSubType(pframe, WIFI_ACTION_NOACK); + set_order_bit(pframe); + set_frame_sub_type(pframe, WIFI_ACTION_NOACK); _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN); @@ -986,7 +2306,7 @@ BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx else duration += 180; - SetDuration(pframe, duration); + set_duration(pframe, duration); /* HT control field */ SET_HT_CTRL_CSI_STEERING(pframe + 24, 3); @@ -1054,12 +2374,12 @@ BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDT fctrl = &pwlanhdr->frame_ctl; *(fctrl) = 0; - SetFrameSubType(pframe, WIFI_NDPA); + set_frame_sub_type(pframe, WIFI_NDPA); _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN); - if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode)) + if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) aSifsTime = 16; else aSifsTime = 10; @@ -1073,7 +2393,7 @@ BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDT else duration += 180; - SetDuration(pframe, duration); + set_duration(pframe, duration); sequence = pBeamInfo->sounding_sequence << 2; if (pBeamInfo->sounding_sequence >= 0x3f) @@ -1140,12 +2460,12 @@ BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH b fctrl = &pwlanhdr->frame_ctl; *(fctrl) = 0; - SetFrameSubType(pframe, WIFI_NDPA); + set_frame_sub_type(pframe, WIFI_NDPA); _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN); - if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode)) + if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) aSifsTime = 16; else aSifsTime = 10; @@ -1159,7 +2479,7 @@ BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH b else duration += 180; - SetDuration(pframe, duration); + set_duration(pframe, duration); sequence = pBeamInfo->sounding_sequence << 2; if (pBeamInfo->sounding_sequence >= 0x3f) @@ -1403,7 +2723,7 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8 *idx) wireless_mode = psta->wireless_mode; bw = psta->bw_mode; - if (IsSupportedHT(wireless_mode) || IsSupportedVHT(wireless_mode)) { + if (is_supported_ht(wireless_mode) || is_supported_vht(wireless_mode)) { /* 3 */ /* HT */ u8 cur_beamform; @@ -1417,7 +2737,7 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8 *idx) if (TEST_FLAG(cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) beamform_cap = (BEAMFORMING_CAP)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT); #ifdef CONFIG_80211AC_VHT - if (IsSupportedVHT(wireless_mode)) { + if (is_supported_vht(wireless_mode)) { /* 3 */ /* VHT */ cur_beamform = psta->vhtpriv.beamform_cap; @@ -1586,73 +2906,18 @@ void beamforming_watchdog(PADAPTER Adapter) beamforming_dym_period(Adapter); beamforming_dym_ndpa_rate(Adapter); } -#endif /* !RTW_BEAMFORMING_VERSION_2 */ #endif/* #if (BEAMFORMING_SUPPORT ==0) - for diver defined beamforming*/ -u32 beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_frame) +u32 rtw_beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_frame) { u32 ret = _SUCCESS; #if (BEAMFORMING_SUPPORT == 1) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); - ret = Beamforming_GetReportFrame(pDM_Odm, precv_frame); + ret = beamforming_get_report_frame(pDM_Odm, precv_frame); #else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/ -#ifdef RTW_BEAMFORMING_VERSION_2 - struct beamformee_entry *pBeamformEntry = NULL; - struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; - u8 *pframe = precv_frame->u.hdr.rx_data; - u32 frame_len = precv_frame->u.hdr.len; - u8 *ta; - u8 *frame_body; - u8 category, action; - u8 *pMIMOCtrlField, *pCSIMatrix; - u8 Nc = 0, Nr = 0, CH_W = 0; - u16 CSIMatrixLen = 0; - - - RTW_DBG("+%s\n", __FUNCTION__); - - /* Memory comparison to see if CSI report is the same with previous one */ - ta = GetAddr2Ptr(pframe); - pBeamformEntry = beamforming_get_bfee_entry_by_addr(Adapter, ta); - if (!pBeamformEntry) - return _FAIL; - - frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - category = frame_body[0]; - action = frame_body[1]; - - if ((category == RTW_WLAN_CATEGORY_VHT) - && (action == RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING)) { - pMIMOCtrlField = pframe + 26; - Nc = ((*pMIMOCtrlField) & 0x7) + 1; - Nr = (((*pMIMOCtrlField) & 0x38) >> 3) + 1; - CH_W = (((*pMIMOCtrlField) & 0xC0) >> 6); - /* - * 24+(1+1+3)+2 - * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2) - */ - pCSIMatrix = pMIMOCtrlField + 3 + Nc; - CSIMatrixLen = frame_len - 26 - 3 - Nc; - } else if ((category == RTW_WLAN_CATEGORY_HT) - && (action == RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING)) { - pMIMOCtrlField = pframe + 26; - Nc = ((*pMIMOCtrlField) & 0x3) + 1; - Nr = (((*pMIMOCtrlField) & 0xC) >> 2) + 1; - CH_W = ((*pMIMOCtrlField) & 0x10) >> 4; - /* - * 24+(1+1+6)+2 - * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2) - */ - pCSIMatrix = pMIMOCtrlField + 6 + Nr; - CSIMatrixLen = frame_len - 26 - 6 - Nr; - } - - RTW_INFO("%s: pkt type=%d-%d, Nc=%d, Nr=%d, CH_W=%d\n", - __FUNCTION__, category, action, Nc, Nr, CH_W); -#else /* !RTW_BEAMFORMING_VERSION_2 */ struct beamforming_entry *pBeamformEntry = NULL; struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); u8 *pframe = precv_frame->u.hdr.rx_data; @@ -1660,10 +2925,10 @@ u32 beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_fram u8 *ta; u8 idx, offset; - /*RTW_INFO("beamforming_get_report_frame\n");*/ + /*RTW_INFO("rtw_beamforming_get_report_frame\n");*/ /*Memory comparison to see if CSI report is the same with previous one*/ - ta = GetAddr2Ptr(pframe); + ta = get_addr2_ptr(pframe); pBeamformEntry = beamforming_get_entry_by_addr(pmlmepriv, ta, &idx); if (pBeamformEntry->beamforming_entry_cap & BEAMFORMER_CAP_VHT_SU) offset = 31; /*24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/ @@ -1687,37 +2952,33 @@ u32 beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_fram pBeamformEntry->bDefaultCSI = _TRUE; else pBeamformEntry->bDefaultCSI = _FALSE; -#endif /* !RTW_BEAMFORMING_VERSION_2 */ #endif return ret; } -void beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame) +void rtw_beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame) { #if (BEAMFORMING_SUPPORT == 1) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); - Beamforming_GetNDPAFrame(pDM_Odm, precv_frame); + beamforming_get_ndpa_frame(pDM_Odm, precv_frame); #else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/ -#ifdef RTW_BEAMFORMING_VERSION_2 - RTW_DBG("+%s\n", __FUNCTION__); -#else /* !RTW_BEAMFORMING_VERSION_2 */ u8 *ta; u8 idx, Sequence; u8 *pframe = precv_frame->u.hdr.rx_data; struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); struct beamforming_entry *pBeamformEntry = NULL; - /*RTW_INFO("beamforming_get_ndpa_frame\n");*/ + /*RTW_INFO("rtw_beamforming_get_ndpa_frame\n");*/ if (IS_HARDWARE_TYPE_8812(Adapter) == _FALSE) return; - else if (GetFrameSubType(pframe) != WIFI_NDPA) + else if (get_frame_sub_type(pframe) != WIFI_NDPA) return; - ta = GetAddr2Ptr(pframe); + ta = get_addr2_ptr(pframe); /*Remove signaling TA. */ ta[0] = ta[0] & 0xFE; @@ -1764,73 +3025,18 @@ void beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame /*Update LogSeq & PreLogSeq*/ pBeamformEntry->PreLogSeq = pBeamformEntry->LogSeq; pBeamformEntry->LogSeq = Sequence; -#endif /* !RTW_BEAMFORMING_VERSION_2 */ + #endif } -/* octets in data header, no WEP */ -#define sMacHdrLng 24 -/* VHT Group ID (GID) Management Frame */ -#define FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY (sMacHdrLng + 2) -#define FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY (sMacHdrLng + 10) -/* VHT GID Management Frame Info */ -#define GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(_pStart) LE_BITS_TO_1BYTE((_pStart), 0, 8) -#define GET_VHT_GID_MGNT_INFO_USER_POSITION(_pStart) LE_BITS_TO_1BYTE((_pStart), 0, 8) -/* - * Description: - * On VHT GID management frame by an MU beamformee. - * - * 2015.05.20. Created by tynli. - */ -u32 beamforming_get_vht_gid_mgnt_frame(PADAPTER adapter, union recv_frame *precv_frame) -{ -#ifdef RTW_BEAMFORMING_VERSION_2 - u8 *ta; - u8 idx; - u8 *pframe; - u8 *pBuffer = NULL; - struct beamformer_entry *bfer = NULL; - - - RTW_DBG("+%s\n", __FUNCTION__); - - pframe = precv_frame->u.hdr.rx_data; - /* Get BFer entry by Addr2 */ - ta = GetAddr2Ptr(pframe); - /* Remove signaling TA */ - ta[0] &= 0xFE; - - bfer = beamforming_get_bfer_entry_by_addr(adapter, ta); - if (!bfer) { - RTW_INFO("%s: Cannot find BFer entry!!\n", __FUNCTION__); - return _FAIL; - } - - /* Parsing Membership Status Array */ - pBuffer = pframe + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY; - for (idx = 0; idx < 8; idx++) - bfer->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(pBuffer+idx); - - /* Parsing User Position Array */ - pBuffer = pframe + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY; - for (idx = 0; idx < 16; idx++) - bfer->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(pBuffer+idx); - /* Config HW GID table */ - beamforming_wk_cmd(adapter, BEAMFORMING_CTRL_SET_GID_TABLE, (u8*)&bfer, sizeof(struct beamformer_entry *), 1); - return _SUCCESS; -#else /* !RTW_BEAMFORMING_VERSION_2 */ - return _FAIL; -#endif /* !RTW_BEAMFORMING_VERSION_2 */ -} void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - _func_enter_; + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); #if (BEAMFORMING_SUPPORT == 1) /*(BEAMFORMING_SUPPORT == 1)- for PHYDM beamfoming*/ switch (type) { @@ -1838,11 +3044,11 @@ void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf) struct sta_info *psta = (PVOID)pbuf; u16 staIdx = psta->mac_id; - Beamforming_Enter(pDM_Odm, staIdx); + beamforming_enter(pDM_Odm, staIdx); break; } case BEAMFORMING_CTRL_LEAVE: - Beamforming_Leave(pDM_Odm, pbuf); + beamforming_leave(pDM_Odm, pbuf); break; default: break; @@ -1866,15 +3072,10 @@ void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf) rtw_hal_set_hwreg(padapter, HW_VAR_SOUNDING_CLK, NULL); break; - case BEAMFORMING_CTRL_SET_GID_TABLE: - rtw_hal_set_hwreg(padapter, HW_VAR_SOUNDING_SET_GID_TABLE, *(void**)pbuf); - break; - default: break; } #endif - _func_exit_; } u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue) @@ -1882,9 +3083,14 @@ u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enque struct cmd_obj *ph2c; struct drvextra_cmd_parm *pdrvextra_cmd_parm; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u8 res = _SUCCESS; - _func_enter_; + /*20170214 ad_hoc mode and mp_mode not support BF*/ + if ((padapter->registrypriv.mp_mode == 1) + || (pmlmeinfo->state == WIFI_FW_ADHOC_STATE)) + return res; if (enqueue) { u8 *wk_buf; @@ -1930,7 +3136,6 @@ u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enque exit: - _func_exit_; return res; } @@ -1942,5 +3147,6 @@ void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, str pattrib->txbf_p_aid = psta->txbf_paid; } } +#endif /* !RTW_BEAMFORMING_VERSION_2 */ -#endif +#endif /* CONFIG_BEAMFORMING */ diff --git a/core/rtw_br_ext.c b/core/rtw_br_ext.c index 8fe3ee4..6509df3 100644 --- a/core/rtw_br_ext.c +++ b/core/rtw_br_ext.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,14 +11,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_BR_EXT_C_ -#include #ifdef __KERNEL__ #include diff --git a/core/rtw_bt_mp.c b/core/rtw_bt_mp.c index ee6f328..85516f9 100644 --- a/core/rtw_bt_mp.c +++ b/core/rtw_bt_mp.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include @@ -36,7 +31,7 @@ void MPh2c_timeout_handle(void *FunctionContext) RTW_INFO("[MPT], MPh2c_timeout_handle\n"); pAdapter = (PADAPTER)FunctionContext; - pMptCtx = &pAdapter->mppriv.MptCtx; + pMptCtx = &pAdapter->mppriv.mpt_ctx; pMptCtx->bMPh2c_timeout = _TRUE; @@ -48,7 +43,7 @@ void MPh2c_timeout_handle(void *FunctionContext) u32 WaitC2Hevent(PADAPTER pAdapter, u8 *C2H_event, u32 delay_time) { - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); pMptCtx->bMPh2c_timeout = _FALSE; if (pAdapter->registrypriv.mp_mode == 0) { @@ -107,7 +102,7 @@ mptbt_SendH2c( { /* KIRQL OldIrql = KeGetCurrentIrql(); */ BT_CTRL_STATUS h2cStatus = BT_STATUS_H2C_SUCCESS; - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); u1Byte i; RTW_INFO("[MPT], mptbt_SendH2c()=========>\n"); @@ -205,7 +200,7 @@ mptbt_BtFwOpCodeProcess( { u1Byte H2C_Parameter[6] = {0}; PBT_H2C pH2c = (PBT_H2C)&H2C_Parameter[0]; - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0]; u2Byte paraLen = 0, i; BT_CTRL_STATUS h2cStatus = BT_STATUS_H2C_SUCCESS, c2hStatus = BT_STATUS_C2H_SUCCESS; @@ -266,7 +261,7 @@ mptbt_BtReady( u1Byte retStatus = BT_STATUS_BT_OP_SUCCESS; u1Byte btOpcode; u1Byte btOpcodeVer = 0; - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0]; u1Byte i; u1Byte btFwVer = 0, bdAddr[6] = {0}; @@ -353,16 +348,16 @@ mptbt_BtReady( void mptbt_close_WiFiRF(PADAPTER Adapter) { - PHY_SetBBReg(Adapter, 0x824, 0xF, 0x0); - PHY_SetBBReg(Adapter, 0x824, 0x700000, 0x0); - PHY_SetRFReg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x0); + phy_set_bb_reg(Adapter, 0x824, 0xF, 0x0); + phy_set_bb_reg(Adapter, 0x824, 0x700000, 0x0); + phy_set_rf_reg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x0); } void mptbt_open_WiFiRF(PADAPTER Adapter) { - PHY_SetBBReg(Adapter, 0x824, 0x700000, 0x3); - PHY_SetBBReg(Adapter, 0x824, 0xF, 0x2); - PHY_SetRFReg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x3); + phy_set_bb_reg(Adapter, 0x824, 0x700000, 0x3); + phy_set_bb_reg(Adapter, 0x824, 0xF, 0x2); + phy_set_rf_reg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x3); } u4Byte mptbt_switch_RF(PADAPTER Adapter, u1Byte Enter) @@ -468,7 +463,7 @@ MPTBT_FwC2hBtMpCtrl( ) { u32 i; - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)tmpBuf; if (Adapter->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0) { @@ -537,7 +532,7 @@ mptbt_BtGetGeneral( IN PBT_RSP_CMD pBtRsp ) { - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0]; u1Byte h2cParaBuf[6] = {0}; u1Byte h2cParaLen = 0; @@ -1512,7 +1507,7 @@ mptbt_BtControlProcess( { u1Byte H2C_Parameter[6] = {0}; PBT_H2C pH2c = (PBT_H2C)&H2C_Parameter[0]; - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); PBT_REQ_CMD pBtReq = (PBT_REQ_CMD)pInBuf; PBT_RSP_CMD pBtRsp; u1Byte i; diff --git a/core/rtw_btcoex.c b/core/rtw_btcoex.c index 4046bd9..730447f 100644 --- a/core/rtw_btcoex.c +++ b/core/rtw_btcoex.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifdef CONFIG_BT_COEXIST #include @@ -34,6 +29,11 @@ void rtw_btcoex_PowerOnSetting(PADAPTER padapter) hal_btcoex_PowerOnSetting(padapter); } +void rtw_btcoex_PowerOffSetting(PADAPTER padapter) +{ + hal_btcoex_PowerOffSetting(padapter); +} + void rtw_btcoex_PreLoadFirmware(PADAPTER padapter) { hal_btcoex_PreLoadFirmware(padapter); @@ -78,12 +78,16 @@ void rtw_btcoex_ScanNotify(PADAPTER padapter, u8 type) if (_FALSE == pHalData->EEPROMBluetoothCoexist) return; -#ifdef CONFIG_CONCURRENT_MODE if (_FALSE == type) { + #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_buddy_check_fwstate(padapter, WIFI_SITE_MONITOR)) return; + #endif + + if (DEV_MGMT_TX_NUM(adapter_to_dvobj(padapter)) + || DEV_ROCH_NUM(adapter_to_dvobj(padapter))) + return; } -#endif #ifdef CONFIG_BT_COEXIST_SOCKET_TRX if (pBtMgnt->ExtConfig.bEnableWifiScanNotify) @@ -210,37 +214,25 @@ void rtw_btcoex_SuspendNotify(PADAPTER padapter, u8 state) void rtw_btcoex_HaltNotify(PADAPTER padapter) { PHAL_DATA_TYPE pHalData; + u8 do_halt = 1; pHalData = GET_HAL_DATA(padapter); if (_FALSE == pHalData->EEPROMBluetoothCoexist) - return; + do_halt = 0; if (_FALSE == padapter->bup) { RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n", FUNC_ADPT_ARG(padapter), padapter->bup); - - return; + do_halt = 0; } if (rtw_is_surprise_removed(padapter)) { RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s Skip!\n", FUNC_ADPT_ARG(padapter), rtw_is_surprise_removed(padapter) ? "True" : "False"); - - return; + do_halt = 0; } - hal_btcoex_HaltNotify(padapter); -} - -void rtw_btcoex_ScoreBoardStatusNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) -{ - PHAL_DATA_TYPE pHalData; - - pHalData = GET_HAL_DATA(padapter); - if (_FALSE == pHalData->EEPROMBluetoothCoexist) - return; - - hal_btcoex_ScoreBoardStatusNotify(padapter, length, tmpBuf); + hal_btcoex_HaltNotify(padapter, do_halt); } void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type) @@ -272,13 +264,6 @@ void rtw_btcoex_Handler(PADAPTER padapter) if (_FALSE == pHalData->EEPROMBluetoothCoexist) return; -#if defined(CONFIG_CONCURRENT_MODE) - if (padapter->adapter_type != PRIMARY_ADAPTER) - return; -#endif - - - hal_btcoex_Hanlder(padapter); } @@ -392,11 +377,23 @@ void rtw_btcoex_StackUpdateProfileInfo(void) hal_btcoex_StackUpdateProfileInfo(); } -void rtw_btcoex_BTOffOnNotify(PADAPTER padapter, u8 bBTON) +void rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON) { - hal_btcoex_BTOffOnNotify(padapter, bBTON); + hal_btcoex_pta_off_on_notify(padapter, bBTON); } +#ifdef CONFIG_RF4CE_COEXIST +void rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state) +{ + hal_btcoex_set_rf4ce_link_state(state); +} + +u8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter) +{ + return hal_btcoex_get_rf4ce_link_state(); +} +#endif + /* ================================================== * Below Functions are called by BT-Coex * ================================================== */ @@ -418,7 +415,7 @@ void rtw_btcoex_LPS_Enter(PADAPTER padapter) rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, lpsVal, "BTCOEX"); } -void rtw_btcoex_LPS_Leave(PADAPTER padapter) +u8 rtw_btcoex_LPS_Leave(PADAPTER padapter) { struct pwrctrl_priv *pwrpriv; @@ -430,6 +427,8 @@ void rtw_btcoex_LPS_Leave(PADAPTER padapter) LPS_RF_ON_check(padapter, 100); pwrpriv->bpower_saving = _FALSE; } + + return _TRUE; } u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data) @@ -474,7 +473,7 @@ u8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - return pHalData->RFEType; + return pHalData->rfe_type; } u8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter) @@ -1354,14 +1353,14 @@ void rtw_btcoex_recvmsgbysocket(void *data) /* attend ack */ pcoex_info->BT_attend = _TRUE; RTW_INFO("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); - rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend); + rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend); break; case RX_ATTEND_REQ: pcoex_info->BT_attend = _TRUE; RTW_INFO("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE); - rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend); + rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend); break; case RX_INVITE_REQ: @@ -1369,21 +1368,21 @@ void rtw_btcoex_recvmsgbysocket(void *data) pcoex_info->BT_attend = _TRUE; RTW_INFO("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE); - rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend); + rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend); break; case RX_INVITE_RSP: /*invite rsp*/ pcoex_info->BT_attend = _TRUE; RTW_INFO("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); - rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend); + rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend); break; case RX_LEAVE_ACK: /* mean BT know wifi will leave */ pcoex_info->BT_attend = _FALSE; RTW_INFO("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); - rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend); + rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend); break; case RX_BT_LEAVE: @@ -1391,7 +1390,7 @@ void rtw_btcoex_recvmsgbysocket(void *data) rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /* no ack */ pcoex_info->BT_attend = _FALSE; RTW_INFO("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); - rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend); + rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend); break; default: @@ -1560,7 +1559,7 @@ void rtw_btcoex_init_socket(_adapter *padapter) pbtcoexadapter = padapter; /* We expect BT is off if BT don't send ack to wifi */ RTW_INFO("We expect BT is off if BT send ack to wifi\n"); - rtw_btcoex_BTOffOnNotify(pbtcoexadapter, _FALSE); + rtw_btcoex_pta_off_on_notify(pbtcoexadapter, _FALSE); if (rtw_btcoex_create_kernel_socket(padapter) == _SUCCESS) pcoex_info->is_exist = _TRUE; else { diff --git a/core/rtw_cmd.c b/core/rtw_cmd.c index 5dd2286..1486afa 100644 --- a/core/rtw_cmd.c +++ b/core/rtw_cmd.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_CMD_C_ #include @@ -35,12 +30,10 @@ sint _rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) { sint res = _SUCCESS; - _func_enter_; _rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0); /* _rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0); */ - _rtw_init_sema(&(pcmdpriv->terminate_cmdthread_sema), 0); - + _rtw_init_sema(&(pcmdpriv->start_cmdthread_sema), 0); _rtw_init_queue(&(pcmdpriv->cmd_queue)); @@ -71,20 +64,72 @@ sint _rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) _rtw_mutex_init(&pcmdpriv->sctx_mutex); exit: - _func_exit_; return res; } #ifdef CONFIG_C2H_WK - static void c2h_wk_callback(_workitem *work); -#endif +static void c2h_wk_callback(_workitem *work) +{ + struct evt_priv *evtpriv = container_of(work, struct evt_priv, c2h_wk); + _adapter *adapter = container_of(evtpriv, _adapter, evtpriv); + u8 *c2h_evt; + c2h_id_filter direct_hdl_filter = rtw_hal_c2h_id_handle_directly; + u8 id, seq, plen; + u8 *payload; + + evtpriv->c2h_wk_alive = _TRUE; + + while (!rtw_cbuf_empty(evtpriv->c2h_queue)) { + c2h_evt = (u8 *)rtw_cbuf_pop(evtpriv->c2h_queue); + if (c2h_evt != NULL) { + /* This C2H event is read, clear it */ + c2h_evt_clear(adapter); + } else { + c2h_evt = (u8 *)rtw_malloc(C2H_REG_LEN); + if (c2h_evt == NULL) { + rtw_warn_on(1); + continue; + } + + /* This C2H event is not read, read & clear now */ + if (rtw_hal_c2h_evt_read(adapter, c2h_evt) != _SUCCESS) { + rtw_mfree(c2h_evt, C2H_REG_LEN); + continue; + } + } + + /* Special pointer to trigger c2h_evt_clear only */ + if ((void *)c2h_evt == (void *)evtpriv) + continue; + + if (!rtw_hal_c2h_valid(adapter, c2h_evt) + || rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload) != _SUCCESS + ) { + rtw_mfree(c2h_evt, C2H_REG_LEN); + continue; + } + + if (direct_hdl_filter(adapter, id, seq, plen, payload) == _TRUE) { + /* Handle directly */ + rtw_hal_c2h_handler(adapter, id, seq, plen, payload); + rtw_mfree(c2h_evt, C2H_REG_LEN); + } else { + /* Enqueue into cmd_thread for others */ + rtw_c2h_reg_wk_cmd(adapter, c2h_evt); + rtw_mfree(c2h_evt, C2H_REG_LEN); + } + } + + evtpriv->c2h_wk_alive = _FALSE; +} +#endif /* CONFIG_C2H_WK */ + sint _rtw_init_evt_priv(struct evt_priv *pevtpriv) { sint res = _SUCCESS; - _func_enter_; #ifdef CONFIG_H2CLBK _rtw_init_sema(&(pevtpriv->lbkevt_done), 0); @@ -100,7 +145,6 @@ sint _rtw_init_evt_priv(struct evt_priv *pevtpriv) #ifdef CONFIG_EVENT_THREAD_MODE _rtw_init_sema(&(pevtpriv->evt_notify), 0); - _rtw_init_sema(&(pevtpriv->terminate_evtthread_sema), 0); pevtpriv->evt_allocated_buf = rtw_zmalloc(MAX_EVTSZ + 4); if (pevtpriv->evt_allocated_buf == NULL) { @@ -143,21 +187,16 @@ sint _rtw_init_evt_priv(struct evt_priv *pevtpriv) pevtpriv->c2h_queue = rtw_cbuf_alloc(C2H_QUEUE_MAX_LEN + 1); #endif - _func_exit_; return res; } void _rtw_free_evt_priv(struct evt_priv *pevtpriv) { - _func_enter_; - RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("+_rtw_free_evt_priv\n")); #ifdef CONFIG_EVENT_THREAD_MODE _rtw_free_sema(&(pevtpriv->evt_notify)); - _rtw_free_sema(&(pevtpriv->terminate_evtthread_sema)); - if (pevtpriv->evt_allocated_buf) rtw_mfree(pevtpriv->evt_allocated_buf, MAX_EVTSZ + 4); @@ -171,28 +210,24 @@ void _rtw_free_evt_priv(struct evt_priv *pevtpriv) while (!rtw_cbuf_empty(pevtpriv->c2h_queue)) { void *c2h; c2h = rtw_cbuf_pop(pevtpriv->c2h_queue); - if (c2h != NULL - && c2h != (void *)pevtpriv) + if (c2h != NULL && c2h != (void *)pevtpriv) rtw_mfree(c2h, 16); } rtw_cbuf_free(pevtpriv->c2h_queue); #endif - RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("-_rtw_free_evt_priv\n")); - _func_exit_; } void _rtw_free_cmd_priv(struct cmd_priv *pcmdpriv) { - _func_enter_; if (pcmdpriv) { _rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock)); _rtw_free_sema(&(pcmdpriv->cmd_queue_sema)); /* _rtw_free_sema(&(pcmdpriv->cmd_done_sema)); */ - _rtw_free_sema(&(pcmdpriv->terminate_cmdthread_sema)); + _rtw_free_sema(&(pcmdpriv->start_cmdthread_sema)); if (pcmdpriv->cmd_allocated_buf) rtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ); @@ -202,7 +237,6 @@ void _rtw_free_cmd_priv(struct cmd_priv *pcmdpriv) _rtw_mutex_free(&pcmdpriv->sctx_mutex); } - _func_exit_; } /* @@ -215,14 +249,13 @@ ISR/Call-Back functions can't call this sub-function. */ #ifdef DBG_CMD_QUEUE - extern u8 dump_cmd_id; +extern u8 dump_cmd_id; #endif sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head) { _irqL irqL; - _func_enter_; if (obj == NULL) goto exit; @@ -276,7 +309,6 @@ sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head) exit: - _func_exit_; return _SUCCESS; } @@ -286,7 +318,6 @@ struct cmd_obj *_rtw_dequeue_cmd(_queue *queue) _irqL irqL; struct cmd_obj *obj; - _func_enter_; /* _enter_critical_bh(&(queue->lock), &irqL); */ _enter_critical(&queue->lock, &irqL); @@ -338,7 +369,6 @@ struct cmd_obj *_rtw_dequeue_cmd(_queue *queue) /* _exit_critical_bh(&(queue->lock), &irqL); */ _exit_critical(&queue->lock, &irqL); - _func_exit_; return obj; } @@ -346,35 +376,25 @@ struct cmd_obj *_rtw_dequeue_cmd(_queue *queue) u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) { u32 res; - _func_enter_; res = _rtw_init_cmd_priv(pcmdpriv); - _func_exit_; return res; } u32 rtw_init_evt_priv(struct evt_priv *pevtpriv) { int res; - _func_enter_; res = _rtw_init_evt_priv(pevtpriv); - _func_exit_; return res; } void rtw_free_evt_priv(struct evt_priv *pevtpriv) { - _func_enter_; - RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("rtw_free_evt_priv\n")); _rtw_free_evt_priv(pevtpriv); - _func_exit_; } void rtw_free_cmd_priv(struct cmd_priv *pcmdpriv) { - _func_enter_; - RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("rtw_free_cmd_priv\n")); _rtw_free_cmd_priv(pcmdpriv); - _func_exit_; } int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj); @@ -397,15 +417,6 @@ int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) } #endif -#ifndef CONFIG_C2H_PACKET_EN - /* C2H should be always allowed */ - if (cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) { - struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf; - if (pdrvextra_cmd_parm->ec_id == C2H_WK_CID) - bAllow = _TRUE; - } -#endif - if (cmd_obj->cmdcode == GEN_CMD_CODE(_SetChannelPlan)) bAllow = _TRUE; @@ -433,7 +444,6 @@ u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) int res = _FAIL; PADAPTER padapter = pcmdpriv->padapter; - _func_enter_; if (cmd_obj == NULL) goto exit; @@ -470,7 +480,6 @@ u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) exit: - _func_exit_; return res; } @@ -479,26 +488,21 @@ struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv) { struct cmd_obj *cmd_obj; - _func_enter_; cmd_obj = _rtw_dequeue_cmd(&pcmdpriv->cmd_queue); - _func_exit_; return cmd_obj; } void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv) { - _func_enter_; pcmdpriv->cmd_done_cnt++; /* _rtw_up_sema(&(pcmdpriv->cmd_done_sema)); */ - _func_exit_; } void rtw_free_cmd_obj(struct cmd_obj *pcmd) { struct drvextra_cmd_parm *extra_parm = NULL; - _func_enter_; if (pcmd->parmbuf != NULL) { /* free parmbuf in cmd_obj */ @@ -514,18 +518,15 @@ void rtw_free_cmd_obj(struct cmd_obj *pcmd) /* free cmd_obj */ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); - _func_exit_; } void rtw_stop_cmd_thread(_adapter *adapter) { - if (adapter->cmdThread && - ATOMIC_READ(&(adapter->cmdpriv.cmdthd_running)) == _TRUE && - adapter->cmdpriv.stop_req == 0) { - adapter->cmdpriv.stop_req = 1; + if (adapter->cmdThread) { _rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema); - _rtw_down_sema(&adapter->cmdpriv.terminate_cmdthread_sema); + rtw_thread_stop(adapter->cmdThread); + adapter->cmdThread = NULL; } } @@ -542,18 +543,14 @@ thread_return rtw_cmd_thread(thread_context context) struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); struct drvextra_cmd_parm *extra_parm = NULL; _irqL irqL; - _func_enter_; thread_enter("RTW_CMD_THREAD"); pcmdbuf = pcmdpriv->cmd_buf; prspbuf = pcmdpriv->rsp_buf; - - pcmdpriv->stop_req = 0; ATOMIC_SET(&(pcmdpriv->cmdthd_running), _TRUE); - _rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema); + _rtw_up_sema(&pcmdpriv->start_cmdthread_sema); - RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("start r871x rtw_cmd_thread !!!!\n")); while (1) { if (_rtw_down_sema(&pcmdpriv->cmd_queue_sema) == _FAIL) { @@ -562,16 +559,10 @@ thread_return rtw_cmd_thread(thread_context context) } if (RTW_CANNOT_RUN(padapter)) { - RTW_PRINT("%s: DriverStopped(%s) SurpriseRemoved(%s) break at line %d\n", - __func__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False" - , __LINE__); - break; - } - - if (pcmdpriv->stop_req) { - RTW_PRINT(FUNC_ADPT_FMT" stop_req:%u, break\n", FUNC_ADPT_ARG(padapter), pcmdpriv->stop_req); + RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n", + FUNC_ADPT_ARG(padapter), + rtw_is_drv_stopped(padapter) ? "True" : "False", + rtw_is_surprise_removed(padapter) ? "True" : "False"); break; } @@ -671,8 +662,7 @@ thread_return rtw_cmd_thread(thread_context context) _enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); if (pcmd->sctx) { if (0) - RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", - FUNC_ADPT_ARG(pcmd->padapter)); + RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter)); if (pcmd->res == H2C_SUCCESS) rtw_sctx_done(&pcmd->sctx); else @@ -691,14 +681,12 @@ thread_return rtw_cmd_thread(thread_context context) if (pcmd->cmdcode < (sizeof(rtw_cmd_callback) / sizeof(struct _cmd_callback))) { pcmd_callback = rtw_cmd_callback[pcmd->cmdcode].callback; if (pcmd_callback == NULL) { - RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("mlme_cmd_hdl(): pcmd_callback=0x%p, cmdcode=0x%x\n", pcmd_callback, pcmd->cmdcode)); rtw_free_cmd_obj(pcmd); } else { /* todo: !!! fill rsp_buf to pcmd->rsp if (pcmd->rsp!=NULL) */ pcmd_callback(pcmd->padapter, pcmd);/* need conider that free cmd_obj in rtw_cmd_callback */ } } else { - RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("%s: cmdcode=0x%x callback not defined!\n", __FUNCTION__, pcmd->cmdcode)); rtw_free_cmd_obj(pcmd); } @@ -730,15 +718,22 @@ thread_return rtw_cmd_thread(thread_context context) rtw_mfree(extra_parm->pbuf, extra_parm->size); } + _enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); + if (pcmd->sctx) { + if (0) + RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter)); + rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_DROP); + } + _exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); + rtw_free_cmd_obj(pcmd); } while (1); - _rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema); - - _func_exit_; + RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter)); - thread_exit(); + rtw_thread_wait_stop(); + return 0; } @@ -749,7 +744,6 @@ u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj) int res; _queue *queue = &pevtpriv->evt_queue; - _func_enter_; res = _SUCCESS; @@ -768,7 +762,6 @@ u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj) exit: - _func_exit_; return res; } @@ -778,7 +771,6 @@ struct evt_obj *rtw_dequeue_evt(_queue *queue) _irqL irqL; struct evt_obj *pevtobj; - _func_enter_; _enter_critical_bh(&queue->lock, &irqL); @@ -791,29 +783,24 @@ struct evt_obj *rtw_dequeue_evt(_queue *queue) _exit_critical_bh(&queue->lock, &irqL); - _func_exit_; return pevtobj; } void rtw_free_evt_obj(struct evt_obj *pevtobj) { - _func_enter_; if (pevtobj->parmbuf) rtw_mfree((unsigned char *)pevtobj->parmbuf, pevtobj->evtsz); rtw_mfree((unsigned char *)pevtobj, sizeof(struct evt_obj)); - _func_exit_; } void rtw_evt_notify_isr(struct evt_priv *pevtpriv) { - _func_enter_; pevtpriv->evt_done_cnt++; _rtw_up_sema(&(pevtpriv->evt_notify)); - _func_exit_; } #endif @@ -829,7 +816,6 @@ u8 rtw_setstandby_cmd(_adapter *padapter, uint action) u8 ret = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -852,7 +838,6 @@ u8 rtw_setstandby_cmd(_adapter *padapter, uint action) exit: - _func_exit_; return ret; } @@ -874,7 +859,6 @@ u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif /* CONFIG_P2P */ - _func_enter_; #ifdef CONFIG_LPS if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) @@ -898,7 +882,6 @@ u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, rtw_free_network_queue(padapter, _FALSE); - RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("%s: flush network queue\n", __FUNCTION__)); init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey)); @@ -943,20 +926,24 @@ u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, #ifdef CONFIG_SCAN_BACKOP if (rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) { - if (IsSupported5G(padapter->registrypriv.wireless_mode) + if (is_supported_5g(padapter->registrypriv.wireless_mode) && IsSupported24G(padapter->registrypriv.wireless_mode)) /* dual band */ mlme_set_scan_to_timer(pmlmepriv, CONC_SCANNING_TIMEOUT_DUAL_BAND); else /* single band */ mlme_set_scan_to_timer(pmlmepriv, CONC_SCANNING_TIMEOUT_SINGLE_BAND); } else #endif /* CONFIG_SCAN_BACKOP */ - mlme_set_scan_to_timer(pmlmepriv, SCANNING_TIMEOUT); +#ifdef CONFIG_CHNL_LOAD_MAGT + if (padapter->clm_flag == TRUE) + mlme_set_scan_to_timer(pmlmepriv, CLM_SCANNING_TIMEOUT); + else +#endif + mlme_set_scan_to_timer(pmlmepriv, SCANNING_TIMEOUT); rtw_led_control(padapter, LED_CTL_SITE_SURVEY); } else _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); - _func_exit_; return res; } @@ -968,7 +955,6 @@ u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset) struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -994,7 +980,6 @@ u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset) res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - _func_exit_; return res; } @@ -1006,7 +991,6 @@ u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset) struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -1028,7 +1012,6 @@ u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset) res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - _func_exit_; return res; } @@ -1050,7 +1033,6 @@ u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch) * struct registry_priv* pregistry_priv = &padapter->registrypriv; */ u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -1067,14 +1049,12 @@ u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch) init_h2fwcmd_w_parm_no_rsp(ph2c, psetphypara, _SetPhy_CMD_); - RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("CH=%d, modem=%d", ch, modem)); psetphypara->modem = modem; psetphypara->rfchannel = ch; res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - _func_exit_; return res; } @@ -1085,7 +1065,6 @@ u8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr) struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { res = _FAIL; @@ -1107,7 +1086,6 @@ u8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr) res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - _func_exit_; return res; } @@ -1123,7 +1101,6 @@ u8 rtw_setbbreg_cmd(_adapter *padapter, u8 offset, u8 val) struct writeBB_parm *pwritebbparm; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { res = _FAIL; @@ -1144,7 +1121,6 @@ u8 rtw_setbbreg_cmd(_adapter *padapter, u8 offset, u8 val) res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - _func_exit_; return res; } @@ -1155,7 +1131,6 @@ u8 rtw_getbbreg_cmd(_adapter *padapter, u8 offset, u8 *pval) struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { res = _FAIL; @@ -1179,7 +1154,6 @@ u8 rtw_getbbreg_cmd(_adapter *padapter, u8 offset, u8 *pval) res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - _func_exit_; return res; } @@ -1189,7 +1163,6 @@ u8 rtw_setrfreg_cmd(_adapter *padapter, u8 offset, u32 val) struct writeRF_parm *pwriterfparm; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { res = _FAIL; @@ -1210,7 +1183,6 @@ u8 rtw_setrfreg_cmd(_adapter *padapter, u8 offset, u32 val) res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - _func_exit_; return res; } @@ -1221,7 +1193,6 @@ u8 rtw_getrfreg_cmd(_adapter *padapter, u8 offset, u8 *pval) struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -1249,14 +1220,12 @@ u8 rtw_getrfreg_cmd(_adapter *padapter, u8 offset, u8 *pval) exit: - _func_exit_; return res; } void rtw_getbbrfreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) { - _func_enter_; /* rtw_free_cmd_obj(pcmd); */ rtw_mfree((unsigned char *) pcmd->parmbuf, pcmd->cmdsz); @@ -1266,12 +1235,10 @@ void rtw_getbbrfreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) if (padapter->registrypriv.mp_mode == 1) padapter->mppriv.workparam.bcompleted = _TRUE; #endif - _func_exit_; } void rtw_readtssi_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) { - _func_enter_; rtw_mfree((unsigned char *) pcmd->parmbuf, pcmd->cmdsz); rtw_mfree((unsigned char *) pcmd, sizeof(struct cmd_obj)); @@ -1281,7 +1248,6 @@ void rtw_readtssi_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) padapter->mppriv.workparam.bcompleted = _TRUE; #endif - _func_exit_; } static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc @@ -1295,7 +1261,7 @@ static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc u8 res = _SUCCESS; if (req_ch > 0 && req_bw >= 0 && req_offset >= 0) { - if (!rtw_chset_is_chbw_valid(adapter->mlmeextpriv.channel_set, req_ch, req_bw, req_offset)) { + if (!rtw_chset_is_chbw_valid(adapter_to_chset(adapter), req_ch, req_bw, req_offset)) { res = _FAIL; goto exit; } @@ -1357,25 +1323,25 @@ static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc inline u8 rtw_create_ibss_cmd(_adapter *adapter, int flags) { return rtw_createbss_cmd(adapter, flags - , 1 + , 1 , 0, -1, -1 /* for now, adhoc doesn't support ch,bw,offset request */ - ); + ); } inline u8 rtw_startbss_cmd(_adapter *adapter, int flags) { return rtw_createbss_cmd(adapter, flags - , 0 - , 0, -1, -1 /* excute entire AP setup cmd */ - ); + , 0 + , 0, -1, -1 /* excute entire AP setup cmd */ + ); } inline u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags, s16 req_ch, s8 req_bw, s8 req_offset) { return rtw_createbss_cmd(adapter, flags - , 0 - , req_ch, req_bw, req_offset - ); + , 0 + , req_ch, req_bw, req_offset + ); } u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) @@ -1398,21 +1364,18 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) NDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); u32 tmp_len; u8 *ptmp = NULL; - _func_enter_; +#ifdef CONFIG_RTW_80211R + struct _ft_priv *pftpriv = &pmlmepriv->ftpriv; +#endif rtw_led_control(padapter, LED_CTL_START_TO_LINK); - if (pmlmepriv->assoc_ssid.SsidLength == 0) - RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("+Join cmd: Any SSid\n")); - else - RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+Join cmd: SSid=[%s]\n", pmlmepriv->assoc_ssid.Ssid)); - pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmd == NULL) { res = _FAIL; - RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd: memory allocate for cmd_obj fail!!!\n")); goto exit; } #if 0 @@ -1461,7 +1424,6 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) res = _FAIL; - RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd :psecnetwork==NULL!!!\n")); goto exit; } @@ -1515,12 +1477,10 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) (padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_)) { rtw_ht_use_default_setting(padapter); - rtw_build_wmm_ie_ht(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength); - /* rtw_restructure_ht_ie */ rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[12], &psecnetwork->IEs[0], pnetwork->network.IELength - 12, &psecnetwork->IELength, - pnetwork->network.Configuration.DSConfig); + pnetwork->network.Configuration.DSConfig); } } @@ -1529,7 +1489,7 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) if (phtpriv->ht_option && REGSTY_IS_11AC_ENABLE(pregistrypriv) && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent)) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) ) { rtw_restructure_vht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, &psecnetwork->IELength); @@ -1540,6 +1500,34 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) #endif /* CONFIG_80211N_HT */ +#ifdef CONFIG_RTW_80211R + /*IEEE802.11-2012 Std. Table 8-101¡XAKM suite selectors*/ + if ((rtw_chk_ft_flags(padapter, RTW_FT_STA_SUPPORTED)) && + ((psecuritypriv->rsn_akm_suite_type == 3) || (psecuritypriv->rsn_akm_suite_type == 4)) + ) { + ptmp = rtw_get_ie(&pnetwork->network.IEs[12], _MDIE_, &tmp_len, pnetwork->network.IELength-12); + if (ptmp) { + _rtw_memcpy(&pftpriv->mdid, ptmp+2, 2); + pftpriv->ft_cap = *(ptmp+4); + + RTW_INFO("FT: Target AP "MAC_FMT" MDID=(0x%2x), capacity=(0x%2x)\n", MAC_ARG(pnetwork->network.MacAddress), pftpriv->mdid, pftpriv->ft_cap); + rtw_set_ft_flags(padapter, RTW_FT_SUPPORTED); + if ((rtw_chk_ft_flags(padapter, RTW_FT_STA_OVER_DS_SUPPORTED)) && (pftpriv->ft_roam_on_expired == _FALSE) && (pftpriv->ft_cap & 0x01)) + rtw_set_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED); + } else { + /*Don't use FT roaming if Target AP cannot support FT*/ + RTW_INFO("FT: Target AP "MAC_FMT" could not support FT\n", MAC_ARG(pnetwork->network.MacAddress)); + rtw_clr_ft_flags(padapter, RTW_FT_SUPPORTED|RTW_FT_OVER_DS_SUPPORTED); + rtw_reset_ft_status(padapter); + } + } else { + /*It could be a non-FT connection*/ + RTW_INFO("FT: non-FT rtw_joinbss_cmd\n"); + rtw_clr_ft_flags(padapter, RTW_FT_SUPPORTED|RTW_FT_OVER_DS_SUPPORTED); + rtw_reset_ft_status(padapter); + } +#endif + #if 0 psecuritypriv->supplicant_ie[0] = (u8)psecnetwork->IELength; @@ -1580,21 +1568,20 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) exit: - _func_exit_; return res; } -u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, bool enqueue) /* for sta_mode */ +u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags) /* for sta_mode */ { struct cmd_obj *cmdobj = NULL; struct disconnect_parm *param = NULL; struct cmd_priv *cmdpriv = &padapter->cmdpriv; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct submit_ctx sctx; u8 res = _SUCCESS; - _func_enter_; - RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_disassoc_cmd\n")); /* prepare cmd parameter */ param = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param)); @@ -1604,8 +1591,13 @@ u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, bool enqueue) /* } param->deauth_timeout_ms = deauth_timeout_ms; - if (enqueue) { - /* need enqueue, prepare cmd_obj and enqueue */ + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (disconnect_hdl(padapter, (u8 *)param) != H2C_SUCCESS) + res = _FAIL; + rtw_mfree((u8 *)param, sizeof(*param)); + + } else { cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); if (cmdobj == NULL) { res = _FAIL; @@ -1613,17 +1605,22 @@ u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, bool enqueue) /* goto exit; } init_h2fwcmd_w_parm_no_rsp(cmdobj, param, _DisConnect_CMD_); + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 2000); + } res = rtw_enqueue_cmd(cmdpriv, cmdobj); - } else { - /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ - if (H2C_SUCCESS != disconnect_hdl(padapter, (u8 *)param)) - res = _FAIL; - rtw_mfree((u8 *)param, sizeof(*param)); + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + } } exit: - _func_exit_; return res; } @@ -1636,7 +1633,6 @@ u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE net struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; psetop = (struct setopmode_parm *)rtw_zmalloc(sizeof(struct setopmode_parm)); if (psetop == NULL) { @@ -1661,7 +1657,6 @@ u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE net } exit: - _func_exit_; return res; } @@ -1677,7 +1672,6 @@ u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool struct security_priv *psecuritypriv = &padapter->securitypriv; u8 res = _SUCCESS; - _func_enter_; psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); if (psetstakey_para == NULL) { @@ -1732,7 +1726,6 @@ u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool } exit: - _func_exit_; return res; } @@ -1748,7 +1741,6 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue) s16 cam_id = 0; u8 res = _SUCCESS; - _func_enter_; if (!enqueue) { while ((cam_id = rtw_camid_search(padapter, sta->hwaddr, -1, -1)) >= 0) { @@ -1792,7 +1784,6 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue) exit: - _func_exit_; return res; } @@ -1803,7 +1794,6 @@ u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table) struct setratable_parm *psetrttblparm; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -1824,7 +1814,6 @@ u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table) res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - _func_exit_; return res; } @@ -1835,7 +1824,6 @@ u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval) struct getratable_parm *pgetrttblparm; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -1863,7 +1851,6 @@ u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval) res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - _func_exit_; return res; } @@ -1877,7 +1864,6 @@ u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr) u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -1909,7 +1895,6 @@ u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr) exit: - _func_exit_; return res; } @@ -1922,7 +1907,6 @@ u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr) u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -1949,7 +1933,6 @@ u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr) exit: - _func_exit_; return res; } @@ -1961,7 +1944,6 @@ u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u struct addBaRsp_parm *paddBaRsp_parm; u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -1989,7 +1971,6 @@ u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u exit: - _func_exit_; return res; } @@ -2001,7 +1982,6 @@ u8 rtw_reset_securitypriv_cmd(_adapter *padapter) struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -2029,7 +2009,6 @@ u8 rtw_reset_securitypriv_cmd(_adapter *padapter) exit: - _func_exit_; return res; @@ -2042,7 +2021,6 @@ u8 rtw_free_assoc_resources_cmd(_adapter *padapter) struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -2070,7 +2048,6 @@ u8 rtw_free_assoc_resources_cmd(_adapter *padapter) exit: - _func_exit_; return res; @@ -2083,7 +2060,6 @@ u8 rtw_dynamic_chk_wk_cmd(_adapter *padapter) struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; /* only primary padapter does this cmd */ @@ -2112,7 +2088,6 @@ u8 rtw_dynamic_chk_wk_cmd(_adapter *padapter) exit: - _func_exit_; return res; @@ -2126,7 +2101,6 @@ u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue) u8 res = _SUCCESS; - _func_enter_; RTW_INFO(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n", FUNC_NDEV_ARG(padapter->pnetdev), ch, bw, ch_offset); @@ -2168,7 +2142,6 @@ u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue) RTW_INFO(FUNC_NDEV_FMT" res:%u\n", FUNC_NDEV_ARG(padapter->pnetdev), res); - _func_exit_; return res; } @@ -2182,7 +2155,6 @@ u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct cou struct submit_ctx sctx; u8 res = _SUCCESS; - _func_enter_; /* check if allow software config */ if (swconfig && rtw_hal_is_disable_sw_channel_plan(adapter) == _TRUE) { @@ -2243,7 +2215,6 @@ u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct cou exit: - _func_exit_; return res; } @@ -2284,9 +2255,7 @@ u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed) u8 res = _SUCCESS; - _func_enter_; - RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_led_blink_cmd\n")); pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmdobj == NULL) { @@ -2308,7 +2277,6 @@ u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed) exit: - _func_exit_; return res; } @@ -2322,9 +2290,7 @@ u8 rtw_set_csa_cmd(_adapter *padapter, u8 new_ch_no) u8 res = _SUCCESS; - _func_enter_; - RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_csa_cmd\n")); pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmdobj == NULL) { @@ -2346,7 +2312,6 @@ u8 rtw_set_csa_cmd(_adapter *padapter, u8 new_ch_no) exit: - _func_exit_; return res; } @@ -2360,11 +2325,9 @@ u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option) u8 res = _SUCCESS; - _func_enter_; #ifdef CONFIG_TDLS - RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_tdls_cmd\n")); pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmdobj == NULL) { @@ -2392,7 +2355,6 @@ u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option) exit: - _func_exit_; return res; } @@ -2431,27 +2393,6 @@ u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter) return res; } -static void collect_traffic_statistics(_adapter *padapter) -{ - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - -#ifdef CONFIG_CONCURRENT_MODE - if (padapter->adapter_type != PRIMARY_ADAPTER) - return; -#endif - - rtw_mi_traffic_statistics(padapter); - - /* Calculate throughput in last interval */ - pdvobjpriv->traffic_stat.cur_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes - pdvobjpriv->traffic_stat.last_tx_bytes; - pdvobjpriv->traffic_stat.cur_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes - pdvobjpriv->traffic_stat.last_rx_bytes; - pdvobjpriv->traffic_stat.last_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes; - pdvobjpriv->traffic_stat.last_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes; - - pdvobjpriv->traffic_stat.cur_tx_tp = (u32)(pdvobjpriv->traffic_stat.cur_tx_bytes * 8 / 2 / 1024 / 1024); - pdvobjpriv->traffic_stat.cur_rx_tp = (u32)(pdvobjpriv->traffic_stat.cur_rx_bytes * 8 / 2 / 1024 / 1024); -} - /* from_timer == 1 means driver is in LPS */ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) { @@ -2483,7 +2424,6 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) } BusyThreshold = BusyThresholdHigh; - collect_traffic_statistics(padapter); /* */ /* Determine if our traffic is busy now */ @@ -2629,7 +2569,9 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) LPS_Leave(padapter, "TRAFFIC_BUSY"); else { #ifdef CONFIG_CONCURRENT_MODE + #ifndef CONFIG_FW_MULTI_PORT_SUPPORT if (padapter->hw_port == HW_PORT0) + #endif #endif rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_TRAFFIC_BUSY, 1); } @@ -2654,6 +2596,12 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) session_tracker_chk_cmd(padapter, NULL); +#ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 + rtw_bf_update_traffic(padapter); +#endif /* RTW_BEAMFORMING_VERSION_2 */ +#endif /* CONFIG_BEAMFORMING */ + pmlmepriv->LinkDetectInfo.NumRxOkInPeriod = 0; pmlmepriv->LinkDetectInfo.NumTxOkInPeriod = 0; pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod = 0; @@ -2668,64 +2616,113 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) } -void dynamic_chk_wk_hdl(_adapter *padapter) + +/* for 11n Logo 4.2.31/4.2.32 */ +static void dynamic_update_bcn_check(_adapter *padapter) { - struct mlme_priv *pmlmepriv; - pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; -#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK -#ifdef CONFIG_AP_MODE + if (!padapter->registrypriv.wifi_spec) + return; + + if (!MLME_IS_AP(padapter)) + return; + + if (pmlmeext->bstart_bss) { + /* In 10 * 2 = 20s, there are no legacy AP, update HT info */ + static u8 count = 1; + + if (count % 10 == 0) { + count = 1; + + if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc) + && _FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht)) { + + if (rtw_ht_operation_update(padapter) > 0) { + update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); + } + } + } + + /* In 2s, there are any legacy AP, update HT info, and then reset count */ + + if (_FALSE != ATOMIC_READ(&pmlmepriv->olbc) + && _FALSE != ATOMIC_READ(&pmlmepriv->olbc_ht)) { + + if (rtw_ht_operation_update(padapter) > 0) { + update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); + + } + ATOMIC_SET(&pmlmepriv->olbc, _FALSE); + ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE); + count = 0; + } + + count ++; + } +} +void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + #ifdef CONFIG_AP_MODE if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) expire_timeout_chk(padapter); -#endif -#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ + #endif + #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ + dynamic_update_bcn_check(padapter); -#ifdef DBG_CONFIG_ERROR_DETECT - rtw_hal_sreset_xmit_status_check(padapter); - rtw_hal_sreset_linked_status_check(padapter); -#endif + linked_status_chk(padapter, 0); + traffic_status_watchdog(padapter, 0); /* for debug purpose */ _linked_info_dump(padapter); + #ifdef CONFIG_BEAMFORMING + #ifndef RTW_BEAMFORMING_VERSION_2 + #if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/ + beamforming_watchdog(padapter); + #endif + #endif /* !RTW_BEAMFORMING_VERSION_2 */ + #endif + +} +void rtw_dynamic_chk_wk_hdl(_adapter *padapter) +{ + rtw_mi_dynamic_chk_wk_hdl(padapter); + +#ifdef DBG_CONFIG_ERROR_DETECT + rtw_hal_sreset_xmit_status_check(padapter); + rtw_hal_sreset_linked_status_check(padapter); +#endif /* if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)==_FALSE) */ { - linked_status_chk(padapter, 0); - traffic_status_watchdog(padapter, 0); #ifdef DBG_RX_COUNTER_DUMP rtw_dump_rx_counters(padapter); #endif dm_DynamicUsbTxAgg(padapter, 0); } - -#ifdef CONFIG_BEAMFORMING -#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/ - beamforming_watchdog(padapter); -#endif -#endif - rtw_hal_dm_watchdog(padapter); /* check_hw_pbc(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type); */ #ifdef CONFIG_BT_COEXIST - /* */ /* BT-Coexist */ - /* */ rtw_btcoex_Handler(padapter); #endif - #ifdef CONFIG_IPS_CHECK_IN_WD /* always call rtw_ps_processor() at last one. */ - if (is_primary_adapter(padapter)) - rtw_ps_processor(padapter); + rtw_ps_processor(padapter); #endif #ifdef CONFIG_MCC_MODE - if (is_primary_adapter(padapter)) - rtw_hal_mcc_sw_status_check(padapter); + rtw_hal_mcc_sw_status_check(padapter); #endif /* CONFIG_MCC_MODE */ } @@ -2739,7 +2736,6 @@ void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type) struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); u8 mstatus; - _func_enter_; if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) @@ -2809,7 +2805,6 @@ void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type) break; } - _func_exit_; } u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue) @@ -2820,7 +2815,6 @@ u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue) /* struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); */ u8 res = _SUCCESS; - _func_enter_; /* if(!pwrctrlpriv->bLeisurePs) */ /* return res; */ @@ -2852,7 +2846,6 @@ u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue) exit: - _func_exit_; return res; @@ -2994,7 +2987,6 @@ u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime) u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { res = _FAIL; @@ -3016,7 +3008,6 @@ u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime) res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - _func_exit_; return res; @@ -3040,7 +3031,6 @@ u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue) u8 res = _SUCCESS; int i; - _func_enter_; rtw_hal_get_def_var(padapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv)); if (_FALSE == bSupportAntDiv) return _FAIL; @@ -3075,7 +3065,6 @@ u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue) antenna_select_wk_hdl(padapter, antenna); exit: - _func_exit_; return res; @@ -3149,7 +3138,6 @@ u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType) struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) return res; @@ -3178,11 +3166,107 @@ u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType) exit: - _func_exit_; return res; } + +#ifdef CONFIG_IOCTL_CFG80211 +static u8 _p2p_roch_cmd(_adapter *adapter + , u64 cookie, struct wireless_dev *wdev + , struct ieee80211_channel *ch, enum nl80211_channel_type ch_type + , unsigned int duration + , u8 flags +) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + struct p2p_roch_parm *roch_parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct submit_ctx sctx; + u8 cancel = duration ? 0 : 1; + u8 res = _SUCCESS; + + roch_parm = (struct p2p_roch_parm *)rtw_zmalloc(sizeof(struct p2p_roch_parm)); + if (roch_parm == NULL) { + res = _FAIL; + goto exit; + } + + roch_parm->cookie = cookie; + roch_parm->wdev = wdev; + if (!cancel) { + _rtw_memcpy(&roch_parm->ch, ch, sizeof(struct ieee80211_channel)); + roch_parm->ch_type = ch_type; + roch_parm->duration = duration; + } + + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != p2p_protocol_wk_hdl(adapter, cancel ? P2P_CANCEL_RO_CH_WK : P2P_RO_CH_WK, (u8 *)roch_parm)) + res = _FAIL; + rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm)); + res = _FAIL; + goto exit; + } + + parm->ec_id = P2P_PROTO_WK_CID; + parm->type = cancel ? P2P_CANCEL_RO_CH_WK : P2P_RO_CH_WK; + parm->size = sizeof(*roch_parm); + parm->pbuf = (u8 *)roch_parm; + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm)); + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 10 * 1000); + } + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status != RTW_SCTX_DONE_SUCCESS) + res = _FAIL; + } + } + +exit: + return res; +} + +inline u8 p2p_roch_cmd(_adapter *adapter + , u64 cookie, struct wireless_dev *wdev + , struct ieee80211_channel *ch, enum nl80211_channel_type ch_type + , unsigned int duration + , u8 flags +) +{ + return _p2p_roch_cmd(adapter, cookie, wdev, ch, ch_type, duration, flags); +} + +inline u8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags) +{ + return _p2p_roch_cmd(adapter, cookie, wdev, NULL, 0, 0, flags); +} +#endif /* CONFIG_IOCTL_CFG80211 */ #endif /* CONFIG_P2P */ u8 rtw_ps_cmd(_adapter *padapter) @@ -3192,7 +3276,6 @@ u8 rtw_ps_cmd(_adapter *padapter) struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; #ifdef CONFIG_CONCURRENT_MODE if (padapter->adapter_type != PRIMARY_ADAPTER) @@ -3222,7 +3305,6 @@ u8 rtw_ps_cmd(_adapter *padapter) exit: - _func_exit_; return res; @@ -3312,8 +3394,8 @@ u8 rtw_dfs_master_hdl(_adapter *adapter) goto exit; if (rtw_get_on_cur_ch_time(adapter) == 0 - || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 300 - ) { + || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 300 + ) { /* offchannel , bypass radar detect */ goto cac_status_chk; } @@ -3324,12 +3406,12 @@ u8 rtw_dfs_master_hdl(_adapter *adapter) } if (!rfctl->dbg_dfs_master_fake_radar_detect_cnt - && rtw_odm_radar_detect(adapter) != _TRUE) + && rtw_odm_radar_detect(adapter) != _TRUE) goto cac_status_chk; if (rfctl->dbg_dfs_master_fake_radar_detect_cnt != 0) { RTW_INFO(FUNC_ADPT_FMT" fake radar detect, cnt:%d\n", FUNC_ADPT_ARG(adapter) - , rfctl->dbg_dfs_master_fake_radar_detect_cnt); + , rfctl->dbg_dfs_master_fake_radar_detect_cnt); rfctl->dbg_dfs_master_fake_radar_detect_cnt--; } @@ -3346,7 +3428,7 @@ u8 rtw_dfs_master_hdl(_adapter *adapter) if (!dvobj->padapters[i]) continue; if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE) - && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE)) + && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE)) break; } @@ -3354,7 +3436,7 @@ u8 rtw_dfs_master_hdl(_adapter *adapter) /* what? */ rtw_warn_on(1); } else { - rtw_chset_update_non_ocp(dvobj->padapters[i]->mlmeextpriv.channel_set + rtw_chset_update_non_ocp(rfctl->channel_set , rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset); rfctl->radar_detected = 1; @@ -3374,6 +3456,11 @@ u8 rtw_dfs_master_hdl(_adapter *adapter) rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause); rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED; + + if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) { + ResumeTxBeacon(adapter); + rtw_mi_tx_beacon_hdl(adapter); + } } set_timer: @@ -3417,9 +3504,9 @@ u8 rtw_dfs_master_cmd(_adapter *adapter, bool enqueue) return res; } -void rtw_dfs_master_timer_hdl(RTW_TIMER_HDL_ARGS) +void rtw_dfs_master_timer_hdl(void *ctx) { - _adapter *adapter = (_adapter *)FunctionContext; + _adapter *adapter = (_adapter *)ctx; rtw_dfs_master_cmd(adapter, _TRUE); } @@ -3443,6 +3530,9 @@ void rtw_dfs_master_enable(_adapter *adapter, u8 ch, u8 bw, u8 offset) rfctl->radar_detected = 0; + if (IS_CH_WAITING(rfctl)) + StopTxBeacon(adapter); + if (!rfctl->dfs_master_enabled) { RTW_INFO(FUNC_ADPT_FMT" set dfs_master_enabled\n", FUNC_ADPT_ARG(adapter)); rfctl->dfs_master_enabled = 1; @@ -3481,6 +3571,11 @@ void rtw_dfs_master_disable(_adapter *adapter, u8 ch, u8 bw, u8 offset, bool by_ rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED; _cancel_timer_ex(&adapter->mlmepriv.dfs_master_timer); + if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) { + ResumeTxBeacon(adapter); + rtw_mi_tx_beacon_hdl(adapter); + } + if (overlap_radar_detect_ch) { u8 pause = 0x00; @@ -3499,26 +3594,26 @@ void rtw_dfs_master_disable(_adapter *adapter, u8 ch, u8 bw, u8 offset, bool by_ void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action) { struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - u8 ld_sta_num, lg_sta_num, ap_num; + struct mi_state mstate; u8 u_ch, u_bw, u_offset; bool ld_sta_in_dfs = _FALSE; bool sync_ch = _FALSE; /* _FALSE: asign channel directly */ bool needed = _FALSE; - rtw_mi_status_no_self(adapter, NULL, &ld_sta_num, &lg_sta_num, &ap_num, NULL, NULL); + rtw_mi_status_no_self(adapter, &mstate); rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset); if (u_ch != 0) sync_ch = _TRUE; switch (self_action) { case MLME_STA_CONNECTING: - lg_sta_num++; + MSTATE_STA_LG_NUM(&mstate)++; break; case MLME_STA_CONNECTED: - ld_sta_num++; + MSTATE_STA_LD_NUM(&mstate)++; break; case MLME_AP_STARTED: - ap_num++; + MSTATE_AP_NUM(&mstate)++; break; case MLME_AP_STOPPED: case MLME_STA_DISCONNECTED: @@ -3534,39 +3629,40 @@ void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action) } rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset - , &u_ch, &u_bw, &u_offset); + , &u_ch, &u_bw, &u_offset); } else { u_ch = mlmeext->cur_channel; u_bw = mlmeext->cur_bwmode; u_offset = mlmeext->cur_ch_offset; } - if (ld_sta_num > 0) { + if (MSTATE_STA_LD_NUM(&mstate) > 0) { /* rely on AP on which STA mode connects */ - if (rtw_is_dfs_ch(u_ch, u_bw, u_offset)) + if (rtw_is_dfs_chbw(u_ch, u_bw, u_offset)) ld_sta_in_dfs = _TRUE; goto apply; } - if (lg_sta_num > 0) { + if (MSTATE_STA_LG_NUM(&mstate) > 0) { /* STA mode is linking */ goto apply; } - if (ap_num == 0) { + if (MSTATE_AP_NUM(&mstate) == 0) { /* No working AP mode */ goto apply; } - if (rtw_is_dfs_ch(u_ch, u_bw, u_offset)) + if (rtw_is_dfs_chbw(u_ch, u_bw, u_offset)) needed = _TRUE; apply: RTW_INFO(FUNC_ADPT_FMT" needed:%d, self_action:%u\n" - , FUNC_ADPT_ARG(adapter), needed, self_action); + , FUNC_ADPT_ARG(adapter), needed, self_action); RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, %u,%u,%u\n" - , FUNC_ADPT_ARG(adapter), ld_sta_num, lg_sta_num, ap_num, u_ch, u_bw, u_offset); + , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate), MSTATE_AP_NUM(&mstate) + , u_ch, u_bw, u_offset); if (needed == _TRUE) rtw_dfs_master_enable(adapter, u_ch, u_bw, u_offset); @@ -3774,60 +3870,261 @@ u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len) return res; } -/* #ifdef CONFIG_C2H_PACKET_EN */ -u8 rtw_c2h_packet_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length) +static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id) { - struct cmd_obj *ph2c; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 *extra_cmd_buf; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + int ret = H2C_SUCCESS; + uint status = _SUCCESS; + u8 rfreg0; + + if (mp_cmd_id == MP_START) { + if (padapter->registrypriv.mp_mode == 0) { + rtw_intf_stop(padapter); + rtw_hal_deinit(padapter); + padapter->registrypriv.mp_mode = 1; +#ifdef CONFIG_RF_POWER_TRIM + if (!IS_HARDWARE_TYPE_8814A(padapter) && !IS_HARDWARE_TYPE_8822B(padapter)) { + padapter->registrypriv.RegPwrTrimEnable = 1; + rtw_hal_read_chip_info(padapter); + } +#endif /*CONFIG_RF_POWER_TRIM*/ + rtw_reset_drv_sw(padapter); + status = rtw_hal_init(padapter); + if (status == _FAIL) { + ret = H2C_REJECTED; + goto exit; + } + rtw_intf_start(padapter); +#ifdef RTW_HALMAC /*for New IC*/ + MPT_InitializeAdapter(padapter, 1); +#endif /* CONFIG_MP_INCLUDED */ + } + + if (padapter->registrypriv.mp_mode == 0) { + ret = H2C_REJECTED; + goto exit; + } + + if (padapter->mppriv.mode == MP_OFF) { + if (mp_start_test(padapter) == _FAIL) { + ret = H2C_REJECTED; + goto exit; + } + padapter->mppriv.mode = MP_ON; + MPT_PwrCtlDM(padapter, 0); + } + padapter->mppriv.bmac_filter = _FALSE; +#ifdef CONFIG_RTL8723B +#ifdef CONFIG_USB_HCI + rtw_write32(padapter, 0x765, 0x0000); + rtw_write32(padapter, 0x948, 0x0280); +#else + rtw_write32(padapter, 0x765, 0x0000); + rtw_write32(padapter, 0x948, 0x0000); +#endif +#ifdef CONFIG_FOR_RTL8723BS_VQ0 + rtw_write32(padapter, 0x765, 0x0000); + rtw_write32(padapter, 0x948, 0x0280); +#endif + rtw_write8(padapter, 0x66, 0x27); /*Open BT uart Log*/ + rtw_write8(padapter, 0xc50, 0x20); /*for RX init Gain*/ +#endif +#ifdef CONFIG_RTL8188F + RTW_INFO("Set reg 0x88c, 0x58, 0x00\n"); + rfreg0 = phy_query_rf_reg(padapter, RF_PATH_A, 0x0, 0x1f); + phy_set_bb_reg(padapter, 0x88c, BIT21|BIT20, 0x3); + phy_set_rf_reg(padapter, RF_PATH_A, 0x58, BIT1, 0x1); + phy_set_rf_reg(padapter, RF_PATH_A, 0x0, 0xF001f, 0x2001f); + rtw_msleep_os(200); + phy_set_rf_reg(padapter, RF_PATH_A, 0x0, 0xF001f, 0x30000 | rfreg0); + phy_set_rf_reg(padapter, RF_PATH_A, 0x58, BIT1, 0x0); + phy_set_bb_reg(padapter, 0x88c, BIT21|BIT20, 0x0); + rtw_msleep_os(1000); +#endif + + odm_write_dig(&pHalData->odmpriv, 0x20); + + } else if (mp_cmd_id == MP_STOP) { + if (padapter->registrypriv.mp_mode == 1) { + MPT_DeInitAdapter(padapter); + rtw_intf_stop(padapter); + rtw_hal_deinit(padapter); + padapter->registrypriv.mp_mode = 0; + rtw_reset_drv_sw(padapter); + status = rtw_hal_init(padapter); + if (status == _FAIL) { + ret = H2C_REJECTED; + goto exit; + } + rtw_intf_start(padapter); + } + + if (padapter->mppriv.mode != MP_OFF) { + mp_stop_test(padapter); + padapter->mppriv.mode = MP_OFF; + } + + } else { + RTW_INFO(FUNC_ADPT_FMT"invalid id:%d\n", FUNC_ADPT_ARG(padapter), mp_cmd_id); + ret = H2C_PARAMETERS_ERROR; + rtw_warn_on(1); + } + +exit: + return ret; +} + +u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct submit_ctx sctx; u8 res = _SUCCESS; - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { res = _FAIL; goto exit; } - pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + parm->ec_id = MP_CMD_WK_CID; + parm->type = mp_cmd_id; + parm->size = 0; + parm->pbuf = NULL; + + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != rtw_mp_cmd_hdl(adapter, mp_cmd_id)) + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 10 * 1000); + } + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status != RTW_SCTX_DONE_SUCCESS) + res = _FAIL; + } + } + +exit: + return res; +} + +#ifdef CONFIG_RTW_CUSTOMER_STR +static s32 rtw_customer_str_cmd_hdl(_adapter *adapter, u8 write, const u8 *cstr) +{ + int ret = H2C_SUCCESS; + + if (write) + ret = rtw_hal_h2c_customer_str_write(adapter, cstr); + else + ret = rtw_hal_h2c_customer_str_req(adapter); + + return ret == _SUCCESS ? H2C_SUCCESS : H2C_REJECTED; +} + +static u8 rtw_customer_str_cmd(_adapter *adapter, u8 write, const u8 *cstr) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + u8 *str = NULL; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { res = _FAIL; goto exit; } - extra_cmd_buf = rtw_zmalloc(length); - if (extra_cmd_buf == NULL) { - rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); - rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); + if (write) { + str = rtw_zmalloc(RTW_CUSTOMER_STR_LEN); + if (str == NULL) { + rtw_mfree((u8 *)parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + } + + parm->ec_id = CUSTOMER_STR_WK_CID; + parm->type = write; + parm->size = write ? RTW_CUSTOMER_STR_LEN : 0; + parm->pbuf = write ? str : NULL; + + if (write) + _rtw_memcpy(str, cstr, RTW_CUSTOMER_STR_LEN); + + /* need enqueue, prepare cmd_obj and enqueue */ + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + if (write) + rtw_mfree(str, RTW_CUSTOMER_STR_LEN); goto exit; } - _rtw_memcpy(extra_cmd_buf, pbuf, length); - pdrvextra_cmd_parm->ec_id = C2H_WK_CID; - pdrvextra_cmd_parm->type = 0; - pdrvextra_cmd_parm->size = length; - pdrvextra_cmd_parm->pbuf = extra_cmd_buf; + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 2 * 1000); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status != RTW_SCTX_DONE_SUCCESS) + res = _FAIL; + } exit: return res; } -/* #else */ /* CONFIG_C2H_PACKET_EN */ -/* dont call R/W in this function, beucase SDIO interrupt have claim host - * or deadlock will happen and cause special-systemserver-died in android */ +inline u8 rtw_customer_str_req_cmd(_adapter *adapter) +{ + return rtw_customer_str_cmd(adapter, 0, NULL); +} + +inline u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr) +{ + return rtw_customer_str_cmd(adapter, 1, cstr); +} +#endif /* CONFIG_RTW_CUSTOMER_STR */ -u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *c2h_evt) +u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length, u8 type) { struct cmd_obj *ph2c; struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 res = _SUCCESS; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 *extra_cmd_buf; + u8 res = _SUCCESS; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -3842,20 +4139,41 @@ u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *c2h_evt) goto exit; } + extra_cmd_buf = rtw_zmalloc(length); + if (extra_cmd_buf == NULL) { + rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + _rtw_memcpy(extra_cmd_buf, pbuf, length); pdrvextra_cmd_parm->ec_id = C2H_WK_CID; - pdrvextra_cmd_parm->type = 0; - pdrvextra_cmd_parm->size = c2h_evt ? 16 : 0; - pdrvextra_cmd_parm->pbuf = c2h_evt; + pdrvextra_cmd_parm->type = type; + pdrvextra_cmd_parm->size = length; + pdrvextra_cmd_parm->pbuf = extra_cmd_buf; init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - return res; } -/* #endif */ /* CONFIG_C2H_PACKET_EN */ + +#ifdef CONFIG_FW_C2H_REG +inline u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt) +{ + return rtw_c2h_wk_cmd(adapter, c2h_evt, c2h_evt ? C2H_REG_LEN : 0, C2H_TYPE_REG); +} +#endif + +#ifdef CONFIG_FW_C2H_PKT +inline u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length) +{ + return rtw_c2h_wk_cmd(adapter, c2h_evt, length, C2H_TYPE_PKT); +} +#endif u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context) { @@ -3864,7 +4182,6 @@ u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context) struct RunInThread_param *parm; s32 res = _SUCCESS; - _func_enter_; pcmdpriv = &padapter->cmdpriv; @@ -3888,88 +4205,36 @@ u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context) res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - _func_exit_; return res; } +#ifdef CONFIG_FW_C2H_REG s32 c2h_evt_hdl(_adapter *adapter, u8 *c2h_evt, c2h_id_filter filter) { s32 ret = _FAIL; - u8 buf[16]; + u8 buf[C2H_REG_LEN] = {0}; + u8 id, seq, plen; + u8 *payload; if (!c2h_evt) { /* No c2h event in cmd_obj, read c2h event before handling*/ - if (rtw_hal_c2h_evt_read(adapter, buf) == _SUCCESS) { - c2h_evt = buf; - - if (filter && filter(c2h_evt) == _FALSE) - goto exit; - - ret = rtw_hal_c2h_handler(adapter, c2h_evt); - } - } else { - - if (filter && filter(c2h_evt) == _FALSE) + if (rtw_hal_c2h_evt_read(adapter, buf) != _SUCCESS) goto exit; - - ret = rtw_hal_c2h_handler(adapter, c2h_evt); + c2h_evt = buf; } -exit: - return ret; -} - -#ifdef CONFIG_C2H_WK -static void c2h_wk_callback(_workitem *work) -{ - struct evt_priv *evtpriv = container_of(work, struct evt_priv, c2h_wk); - _adapter *adapter = container_of(evtpriv, _adapter, evtpriv); - u8 *c2h_evt; - c2h_id_filter ccx_id_filter = rtw_hal_c2h_id_filter_ccx(adapter); - - evtpriv->c2h_wk_alive = _TRUE; - - while (!rtw_cbuf_empty(evtpriv->c2h_queue)) { - c2h_evt = (u8 *)rtw_cbuf_pop(evtpriv->c2h_queue); - if (c2h_evt != NULL) { - /* This C2H event is read, clear it */ - c2h_evt_clear(adapter); - } else { - c2h_evt = (u8 *)rtw_malloc(16); - if (c2h_evt == NULL) { - rtw_warn_on(1); - continue; - } - /* This C2H event is not read, read & clear now */ - if (rtw_hal_c2h_evt_read(adapter, c2h_evt) != _SUCCESS) { - rtw_mfree(c2h_evt, 16); - continue; - } - } + rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload); - /* Special pointer to trigger c2h_evt_clear only */ - if ((void *)c2h_evt == (void *)evtpriv) - continue; + if (filter && filter(adapter, id, seq, plen, payload) == _FALSE) + goto exit; - if (!rtw_hal_c2h_valid(adapter, c2h_evt)) { - rtw_mfree(c2h_evt, 16); - continue; - } + ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload); - if (ccx_id_filter(c2h_evt) == _TRUE) { - /* Handle CCX report here */ - rtw_hal_c2h_handler(adapter, c2h_evt); - rtw_mfree(c2h_evt, 16); - } else { - /* Enqueue into cmd_thread for others */ - rtw_c2h_wk_cmd(adapter, c2h_evt); - } - } - - evtpriv->c2h_wk_alive = _FALSE; +exit: + return ret; } -#endif +#endif /* CONFIG_FW_C2H_REG */ u8 session_tracker_cmd(_adapter *adapter, u8 cmd, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) { @@ -4073,8 +4338,8 @@ void session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta) pnext = get_next(pnext); if (st->status != ST_STATUS_ESTABLISH - && rtw_get_passing_time_ms(st->set_time) > ST_EXPIRE_MS - ) { + && rtw_get_passing_time_ms(st->set_time) > ST_EXPIRE_MS + ) { rtw_list_delete(&st->list); rtw_list_insert_tail(&st->list, &dlist); } @@ -4086,18 +4351,18 @@ void session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta) if (st->status != ST_STATUS_ESTABLISH) continue; -#ifdef CONFIG_WFD + #ifdef CONFIG_WFD if (0) RTW_INFO(FUNC_ADPT_FMT" local:%u, remote:%u, rtsp:%u, %u, %u\n", FUNC_ADPT_ARG(adapter) , ntohs(st->local_port), ntohs(st->remote_port), adapter->wfd_info.rtsp_ctrlport, adapter->wfd_info.tdls_rtsp_ctrlport - , adapter->wfd_info.peer_rtsp_ctrlport); + , adapter->wfd_info.peer_rtsp_ctrlport); if (ntohs(st->local_port) == adapter->wfd_info.rtsp_ctrlport) op_wfd_mode |= MIRACAST_SINK; if (ntohs(st->local_port) == adapter->wfd_info.tdls_rtsp_ctrlport) op_wfd_mode |= MIRACAST_SINK; if (ntohs(st->remote_port) == adapter->wfd_info.peer_rtsp_ctrlport) op_wfd_mode |= MIRACAST_SOURCE; -#endif + #endif } _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); @@ -4178,10 +4443,10 @@ void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm) if (DBG_SESSION_TRACKER) RTW_INFO(FUNC_ADPT_FMT" cmd:%u, sta:%p, local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT"\n" - , FUNC_ADPT_ARG(adapter), cmd, sta - , IP_ARG(&local_naddr), PORT_ARG(&local_port) - , IP_ARG(&remote_naddr), PORT_ARG(&remote_port) - ); + , FUNC_ADPT_ARG(adapter), cmd, sta + , IP_ARG(&local_naddr), PORT_ARG(&local_port) + , IP_ARG(&remote_naddr), PORT_ARG(&remote_port) + ); if (!(sta->state & _FW_LINKED)) goto exit; @@ -4196,9 +4461,9 @@ void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm) st = LIST_CONTAINOR(plist, struct session_tracker, list); if (st->local_naddr == local_naddr - && st->local_port == local_port - && st->remote_naddr == remote_naddr - && st->remote_port == remote_port) + && st->local_port == local_port + && st->remote_naddr == remote_naddr + && st->remote_port == remote_port) break; plist = get_next(plist); @@ -4251,6 +4516,7 @@ void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm) u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) { + int ret = H2C_SUCCESS; struct drvextra_cmd_parm *pdrvextra_cmd; if (!pbuf) @@ -4264,7 +4530,7 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) break; case DYNAMIC_CHK_WK_CID:/*only primary padapter go to this cmd, but execute dynamic_chk_wk_hdl() for two interfaces */ - rtw_mi_dynamic_chk_wk_hdl(padapter); + rtw_dynamic_chk_wk_hdl(padapter); break; case POWER_SAVING_CTRL_WK_CID: power_saving_wk_hdl(padapter); @@ -4301,7 +4567,7 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) * Commented by Albert 2011/07/01 * I used the type_size as the type command */ - p2p_protocol_wk_hdl(padapter, pdrvextra_cmd->type); + ret = p2p_protocol_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); break; #endif #ifdef CONFIG_AP_MODE @@ -4322,11 +4588,22 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) free_assoc_resources_hdl(padapter); break; case C2H_WK_CID: -#ifdef CONFIG_C2H_PACKET_EN - rtw_hal_set_hwreg_with_buf(padapter, HW_VAR_C2H_HANDLE, pdrvextra_cmd->pbuf, pdrvextra_cmd->size); -#else - c2h_evt_hdl(padapter, pdrvextra_cmd->pbuf, NULL); -#endif + switch (pdrvextra_cmd->type) { + #ifdef CONFIG_FW_C2H_REG + case C2H_TYPE_REG: + c2h_evt_hdl(padapter, pdrvextra_cmd->pbuf, NULL); + break; + #endif + #ifdef CONFIG_FW_C2H_PKT + case C2H_TYPE_PKT: + rtw_hal_c2h_pkt_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size); + break; + #endif + default: + RTW_ERR("unknown C2H type:%d\n", pdrvextra_cmd->type); + rtw_warn_on(1); + break; + } break; #ifdef CONFIG_BEAMFORMING case BEAMFORMING_WK_CID: @@ -4355,6 +4632,14 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) case TEST_H2C_CID: rtw_hal_fill_h2c_cmd(padapter, pdrvextra_cmd->pbuf[0], pdrvextra_cmd->size - 1, &pdrvextra_cmd->pbuf[1]); break; + case MP_CMD_WK_CID: + ret = rtw_mp_cmd_hdl(padapter, pdrvextra_cmd->type); + break; +#ifdef CONFIG_RTW_CUSTOMER_STR + case CUSTOMER_STR_WK_CID: + ret = rtw_customer_str_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); + break; +#endif default: break; } @@ -4362,14 +4647,13 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) if (pdrvextra_cmd->pbuf && pdrvextra_cmd->size > 0) rtw_mfree(pdrvextra_cmd->pbuf, pdrvextra_cmd->size); - return H2C_SUCCESS; + return ret; } void rtw_survey_cmd_callback(_adapter *padapter , struct cmd_obj *pcmd) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _func_enter_; if (pcmd->res == H2C_DROPPED) { /* TODO: cancel timer and do timeout handler directly... */ @@ -4377,28 +4661,22 @@ void rtw_survey_cmd_callback(_adapter *padapter , struct cmd_obj *pcmd) mlme_set_scan_to_timer(pmlmepriv, 1); } else if (pcmd->res != H2C_SUCCESS) { mlme_set_scan_to_timer(pmlmepriv, 1); - RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\n ********Error: MgntActrtw_set_802_11_bssid_LIST_SCAN Fail ************\n\n.")); } /* free cmd */ rtw_free_cmd_obj(pcmd); - _func_exit_; } void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) { _irqL irqL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _func_enter_; if (pcmd->res != H2C_SUCCESS) { _enter_critical_bh(&pmlmepriv->lock, &irqL); set_fwstate(pmlmepriv, _FW_LINKED); _exit_critical_bh(&pmlmepriv->lock, &irqL); - - RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\n ***Error: disconnect_cmd_callback Fail ***\n.")); - goto exit; } #ifdef CONFIG_BR_EXT @@ -4410,26 +4688,22 @@ void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) rtw_free_cmd_obj(pcmd); exit: - - _func_exit_; + return; } void rtw_getmacreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) { - _func_enter_; rtw_free_cmd_obj(pcmd); - _func_exit_; } void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _func_enter_; if (pcmd->res == H2C_DROPPED) { /* TODO: cancel timer and do timeout handler directly... */ @@ -4440,13 +4714,11 @@ void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) rtw_free_cmd_obj(pcmd); - _func_exit_; } void rtw_create_ibss_post_hdl(_adapter *padapter, int status) { _irqL irqL; - u8 timer_cancelled; struct sta_info *psta = NULL; struct wlan_network *pwlan = NULL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -4456,7 +4728,7 @@ void rtw_create_ibss_post_hdl(_adapter *padapter, int status) if (status != H2C_SUCCESS) _set_timer(&pmlmepriv->assoc_timer, 1); - _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled); + _cancel_timer_ex(&pmlmepriv->assoc_timer); _enter_critical_bh(&pmlmepriv->lock, &irqL); @@ -4468,7 +4740,6 @@ void rtw_create_ibss_post_hdl(_adapter *padapter, int status) if (pwlan == NULL) { pwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue); if (pwlan == NULL) { - RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("Error: can't get pwlan in rtw_joinbss_event_callback\n")); _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); goto createbss_cmd_fail; } @@ -4508,10 +4779,8 @@ void rtw_setstaKey_cmdrsp_callback(_adapter *padapter , struct cmd_obj *pcmd) struct set_stakey_rsp *psetstakey_rsp = (struct set_stakey_rsp *)(pcmd->rsp); struct sta_info *psta = rtw_get_stainfo(pstapriv, psetstakey_rsp->addr); - _func_enter_; if (psta == NULL) { - RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\nERROR: rtw_setstaKey_cmdrsp_callback => can't get sta_info \n\n")); goto exit; } @@ -4521,7 +4790,6 @@ void rtw_setstaKey_cmdrsp_callback(_adapter *padapter , struct cmd_obj *pcmd) rtw_free_cmd_obj(pcmd); - _func_exit_; } void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) @@ -4533,10 +4801,8 @@ void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) struct set_assocsta_rsp *passocsta_rsp = (struct set_assocsta_rsp *)(pcmd->rsp); struct sta_info *psta = rtw_get_stainfo(pstapriv, passocsta_parm->addr); - _func_enter_; if (psta == NULL) { - RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\nERROR: setassocsta_cmdrsp_callbac => can't get sta_info \n\n")); goto exit; } @@ -4553,13 +4819,11 @@ void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) exit: rtw_free_cmd_obj(pcmd); - _func_exit_; } void rtw_getrttbl_cmd_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); void rtw_getrttbl_cmd_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) { - _func_enter_; rtw_free_cmd_obj(pcmd); #ifdef CONFIG_MP_INCLUDED @@ -4567,6 +4831,5 @@ void rtw_getrttbl_cmd_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) padapter->mppriv.workparam.bcompleted = _TRUE; #endif - _func_exit_; } diff --git a/core/rtw_debug.c b/core/rtw_debug.c index 97f1c9b..986f8cc 100644 --- a/core/rtw_debug.c +++ b/core/rtw_debug.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_DEBUG_C_ #include @@ -47,14 +42,17 @@ const char *rtw_log_level_str[] = { void dump_drv_version(void *sel) { RTW_PRINT_SEL(sel, "%s %s\n", DRV_NAME, DRIVERVERSION); - //RTW_PRINT_SEL(sel, "build time: %s %s\n", __DATE__, __TIME__); +// RTW_PRINT_SEL(sel, "build time: %s %s\n", __DATE__, __TIME__); //EDX } void dump_drv_cfg(void *sel) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) char *kernel_version = utsname()->release; RTW_PRINT_SEL(sel, "\nKernel Version: %s\n", kernel_version); +#endif + RTW_PRINT_SEL(sel, "Driver Version: %s\n", DRIVERVERSION); RTW_PRINT_SEL(sel, "------------------------------------------------\n"); #ifdef CONFIG_IOCTL_CFG80211 @@ -62,6 +60,9 @@ void dump_drv_cfg(void *sel) #ifdef RTW_USE_CFG80211_STA_EVENT RTW_PRINT_SEL(sel, "RTW_USE_CFG80211_STA_EVENT\n"); #endif + #ifdef CONFIG_RADIO_WORK + RTW_PRINT_SEL(sel, "CONFIG_RADIO_WORK\n"); + #endif #else RTW_PRINT_SEL(sel, "WEXT\n"); #endif @@ -81,6 +82,11 @@ void dump_drv_cfg(void *sel) #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE RTW_PRINT_SEL(sel, "LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH=%s\n", REALTEK_CONFIG_PATH); + #if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER) + RTW_PRINT_SEL(sel, "LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER\n"); + #endif + +/* configurations about TX power */ #ifdef CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY RTW_PRINT_SEL(sel, "CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY\n"); #endif @@ -88,6 +94,11 @@ void dump_drv_cfg(void *sel) RTW_PRINT_SEL(sel, "CONFIG_CALIBRATE_TX_POWER_TO_MAX\n"); #endif #endif + RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT=0x%02x\n", RTW_DEF_MODULE_REGULATORY_CERT); + + RTW_PRINT_SEL(sel, "CONFIG_TXPWR_BY_RATE_EN=%d\n", CONFIG_TXPWR_BY_RATE_EN); + RTW_PRINT_SEL(sel, "CONFIG_TXPWR_LIMIT_EN=%d\n", CONFIG_TXPWR_LIMIT_EN); + #ifdef CONFIG_DISABLE_ODM RTW_PRINT_SEL(sel, "CONFIG_DISABLE_ODM\n"); @@ -114,6 +125,10 @@ void dump_drv_cfg(void *sel) RTW_PRINT_SEL(sel, "CONFIG_TDLS\n"); #endif +#ifdef CONFIG_RTW_80211R + RTW_PRINT_SEL(sel, "CONFIG_RTW_80211R\n"); +#endif + #ifdef CONFIG_USB_HCI #ifdef CONFIG_SUPPORT_USB_INT RTW_PRINT_SEL(sel, "CONFIG_SUPPORT_USB_INT\n"); @@ -214,7 +229,7 @@ void mac_reg_dump(void *sel, _adapter *adapter) for (i = 0x0; i < 0x800; i += 4) { if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%03x", i); + RTW_PRINT_SEL(sel, "0x%04x", i); _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); if ((j++) % 4 == 0) _RTW_PRINT_SEL(sel, "\n"); @@ -224,7 +239,7 @@ void mac_reg_dump(void *sel, _adapter *adapter) { for (i = 0x1000; i < 0x1650; i += 4) { if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%03x", i); + RTW_PRINT_SEL(sel, "0x%04x", i); _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); if ((j++) % 4 == 0) _RTW_PRINT_SEL(sel, "\n"); @@ -232,10 +247,11 @@ void mac_reg_dump(void *sel, _adapter *adapter) } #endif /* CONFIG_RTL8814A */ -#ifdef CONFIG_RTL8822B + +#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) for (i = 0x1000; i < 0x1800; i += 4) { if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%03x", i); + RTW_PRINT_SEL(sel, "0x%04x", i); _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); if ((j++) % 4 == 0) _RTW_PRINT_SEL(sel, "\n"); @@ -250,16 +266,16 @@ void bb_reg_dump(void *sel, _adapter *adapter) RTW_PRINT_SEL(sel, "======= BB REG =======\n"); for (i = 0x800; i < 0x1000; i += 4) { if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%03x", i); + RTW_PRINT_SEL(sel, "0x%04x", i); _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); if ((j++) % 4 == 0) _RTW_PRINT_SEL(sel, "\n"); } -#ifdef CONFIG_RTL8822B +#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) for (i = 0x1800; i < 0x2000; i += 4) { if (j % 4 == 1) - RTW_PRINT_SEL(sel, "0x%03x", i); + RTW_PRINT_SEL(sel, "0x%04x", i); _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); if ((j++) % 4 == 0) _RTW_PRINT_SEL(sel, "\n"); @@ -267,6 +283,26 @@ void bb_reg_dump(void *sel, _adapter *adapter) #endif /* CONFIG_RTL8822B */ } +void bb_reg_dump_ex(void *sel, _adapter *adapter) +{ + int i, j = 1; + + RTW_PRINT_SEL(sel, "======= BB REG =======\n"); + for (i = 0x800; i < 0x1000; i += 4) { + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); + _RTW_PRINT_SEL(sel, "\n"); + } + +#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) + for (i = 0x1800; i < 0x2000; i += 4) { + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); + _RTW_PRINT_SEL(sel, "\n"); + } +#endif /* CONFIG_RTL8822B */ +} + void rf_reg_dump(void *sel, _adapter *adapter) { int i, j = 1, path; @@ -295,48 +331,6 @@ void rf_reg_dump(void *sel, _adapter *adapter) } } -static u8 fwdl_test_chksum_fail = 0; -static u8 fwdl_test_wintint_rdy_fail = 0; - -bool rtw_fwdl_test_trigger_chksum_fail(void) -{ - if (fwdl_test_chksum_fail) { - RTW_PRINT("fwdl test case: trigger chksum_fail\n"); - fwdl_test_chksum_fail--; - return _TRUE; - } - return _FALSE; -} - -bool rtw_fwdl_test_trigger_wintint_rdy_fail(void) -{ - if (fwdl_test_wintint_rdy_fail) { - RTW_PRINT("fwdl test case: trigger wintint_rdy_fail\n"); - fwdl_test_wintint_rdy_fail--; - return _TRUE; - } - return _FALSE; -} - -static u32 g_wait_hiq_empty_ms = 0; - -u32 rtw_get_wait_hiq_empty_ms(void) -{ - return g_wait_hiq_empty_ms; -} - -static u8 del_rx_ampdu_test_no_tx_fail = 0; - -bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void) -{ - if (del_rx_ampdu_test_no_tx_fail) { - RTW_PRINT("del_rx_ampdu test case: trigger no_tx_fail\n"); - del_rx_ampdu_test_no_tx_fail--; - return _TRUE; - } - return _FALSE; -} - void rtw_sink_rtp_seq_dbg(_adapter *adapter, _pkt *pkt) { struct recv_priv *precvpriv = &(adapter->recvpriv); @@ -365,6 +359,45 @@ void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta) } } +void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj) +{ + _adapter *adapter = dvobj_get_primary_adapter(dvobj); + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + u8 bw; + + RTW_PRINT_SEL(sel, "%-6s", "bw"); + if (hal_chk_proto_cap(adapter, PROTO_CAP_11AC)) + _RTW_PRINT_SEL(sel, " %-11s", "vht"); + + _RTW_PRINT_SEL(sel, " %-11s %-4s %-3s\n", "ht", "ofdm", "cck"); + + for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) { + if (!hal_is_bw_support(adapter, bw)) + continue; + + RTW_PRINT_SEL(sel, "%6s", ch_width_str(bw)); + if (hal_chk_proto_cap(adapter, PROTO_CAP_11AC)) { + _RTW_PRINT_SEL(sel, " %03x %03x %03x" + , RATE_BMP_GET_VHT_3SS(rfctl->rate_bmp_vht_by_bw[bw]) + , RATE_BMP_GET_VHT_2SS(rfctl->rate_bmp_vht_by_bw[bw]) + , RATE_BMP_GET_VHT_1SS(rfctl->rate_bmp_vht_by_bw[bw]) + ); + } + + _RTW_PRINT_SEL(sel, " %02x %02x %02x %02x" + , bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_4SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0 + , bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_3SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0 + , bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_2SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0 + , bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_1SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0 + ); + + _RTW_PRINT_SEL(sel, " %03x %01x\n" + , bw <= CHANNEL_WIDTH_20 ? RATE_BMP_GET_OFDM(rfctl->rate_bmp_cck_ofdm) : 0 + , bw <= CHANNEL_WIDTH_20 ? RATE_BMP_GET_CCK(rfctl->rate_bmp_cck_ofdm) : 0 + ); + } +} + void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) { struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); @@ -374,118 +407,135 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) dump_mi_status(sel, dvobj); - RTW_PRINT_SEL(sel, "%-2s %-8s %-17s %-4s %-7s %s\n" - , "id", "ifname", "macaddr", "port", "ch", "status"); +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT + RTW_PRINT_SEL(sel, "default port id:%d\n\n", dvobj->default_port_id); +#endif /* CONFIG_FW_MULTI_PORT_SUPPORT */ - RTW_PRINT_SEL(sel, "------------------------------------------\n"); + RTW_PRINT_SEL(sel, "dev status:%s%s\n\n" + , dev_is_surprise_removed(dvobj) ? " SR" : "" + , dev_is_drv_stopped(dvobj) ? " DS" : "" + ); + +#ifdef CONFIG_P2P +#define P2P_INFO_TITLE_FMT " %-3s %-4s" +#define P2P_INFO_TITLE_ARG , "lch", "p2ps" +#ifdef CONFIG_IOCTL_CFG80211 +#define P2P_INFO_VALUE_FMT " %3u %c%3u" +#define P2P_INFO_VALUE_ARG , iface->wdinfo.listen_channel, iface->wdev_data.p2p_enabled ? 'e' : ' ', rtw_p2p_state(&iface->wdinfo) +#else +#define P2P_INFO_VALUE_FMT " %3u %4u" +#define P2P_INFO_VALUE_ARG , iface->wdinfo.listen_channel, rtw_p2p_state(&iface->wdinfo) +#endif +#define P2P_INFO_DASH "---------" +#else +#define P2P_INFO_TITLE_FMT "" +#define P2P_INFO_TITLE_ARG +#define P2P_INFO_VALUE_FMT "" +#define P2P_INFO_VALUE_ARG +#define P2P_INFO_DASH +#endif + + RTW_PRINT_SEL(sel, "%-2s %-15s %c %-3s %-3s %-3s %-17s %-4s %-7s" + P2P_INFO_TITLE_FMT + " %s\n" + , "id", "ifname", ' ', "bup", "nup", "ncd", "macaddr", "port", "ch" + P2P_INFO_TITLE_ARG + , "status"); + + RTW_PRINT_SEL(sel, "---------------------------------------------------------------" + P2P_INFO_DASH + "-------\n"); for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if (iface) { - RTW_PRINT_SEL(sel, "%2d %-8s "MAC_FMT" %4hhu %3u,%u,%u "MLME_STATE_FMT" %s%s\n" - , i, ADPT_ARG(iface) - , MAC_ARG(adapter_mac_addr(iface)) - , get_hw_port(iface) - , iface->mlmeextpriv.cur_channel - , iface->mlmeextpriv.cur_bwmode - , iface->mlmeextpriv.cur_ch_offset - , MLME_STATE_ARG(iface) - , rtw_is_surprise_removed(iface) ? " SR" : "" - , rtw_is_drv_stopped(iface) ? " DS" : "" - ); + RTW_PRINT_SEL(sel, "%2d %-15s %c %3u %3u %3u "MAC_FMT" %4hhu %3u,%u,%u" + P2P_INFO_VALUE_FMT + " "MLME_STATE_FMT"\n" + , i, iface->registered ? ADPT_ARG(iface) : NULL + , iface->registered ? 'R' : ' ' + , iface->bup + , iface->netif_up + , iface->net_closed + , MAC_ARG(adapter_mac_addr(iface)) + , get_hw_port(iface) + , iface->mlmeextpriv.cur_channel + , iface->mlmeextpriv.cur_bwmode + , iface->mlmeextpriv.cur_ch_offset + P2P_INFO_VALUE_ARG + , MLME_STATE_ARG(iface) + ); } } - RTW_PRINT_SEL(sel, "------------------------------------------\n"); + RTW_PRINT_SEL(sel, "---------------------------------------------------------------" + P2P_INFO_DASH + "-------\n"); - rtw_mi_get_ch_setting_union(dvobj->padapters[IFACE_ID0], &u_ch, &u_bw, &u_offset); - RTW_PRINT_SEL(sel, "%34s %3u,%u,%u\n" - , "union:" - , u_ch, u_bw, u_offset - ); + rtw_mi_get_ch_setting_union(dvobj_get_primary_adapter(dvobj), &u_ch, &u_bw, &u_offset); + RTW_PRINT_SEL(sel, "%55s %3u,%u,%u\n" + , "union:" + , u_ch, u_bw, u_offset + ); - RTW_PRINT_SEL(sel, "%34s %3u,%u,%u\n" - , "oper:" - , dvobj->oper_channel - , dvobj->oper_bwmode - , dvobj->oper_ch_offset - ); + RTW_PRINT_SEL(sel, "%55s %3u,%u,%u\n" + , "oper:" + , dvobj->oper_channel + , dvobj->oper_bwmode + , dvobj->oper_ch_offset + ); #ifdef CONFIG_DFS_MASTER if (rfctl->radar_detect_ch != 0) { - u32 non_ocp_ms; - u32 cac_ms; + RTW_PRINT_SEL(sel, "%55s %3u,%u,%u" + , "radar_detect:" + , rfctl->radar_detect_ch + , rfctl->radar_detect_bw + , rfctl->radar_detect_offset + ); + + if (rfctl->radar_detect_by_others) + _RTW_PRINT_SEL(sel, ", by AP of STA link"); + else { + u32 non_ocp_ms; + u32 cac_ms; + u8 dfs_domain = rtw_odm_get_dfs_domain(dvobj_get_primary_adapter(dvobj)); + + _RTW_PRINT_SEL(sel, ", domain:%u", dfs_domain); + + for (i = 0; i < dvobj->iface_nums; i++) { + if (!dvobj->padapters[i]) + continue; + if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE) + && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE)) + break; + } - for (i = 0; i < dvobj->iface_nums; i++) { - if (!dvobj->padapters[i]) - continue; - if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE) - && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE)) - break; - } + if (i >= dvobj->iface_nums) { + RTW_PRINT_SEL(sel, "DFS master enable without AP mode???"); + goto end_dfs_master; + } - if (i >= dvobj->iface_nums) { - RTW_PRINT_SEL(sel, "DFS master enable without AP mode???"); - goto end_dfs_master; + rtw_get_ch_waiting_ms(dvobj->padapters[i] + , rfctl->radar_detect_ch + , rfctl->radar_detect_bw + , rfctl->radar_detect_offset + , &non_ocp_ms + , &cac_ms + ); + + if (non_ocp_ms) + _RTW_PRINT_SEL(sel, ", non_ocp:%d", non_ocp_ms); + if (cac_ms) + _RTW_PRINT_SEL(sel, ", cac:%d", cac_ms); } - RTW_PRINT_SEL(sel, "%34s %3u,%u,%u" - , "radar_detect:" - , rfctl->radar_detect_ch - , rfctl->radar_detect_bw - , rfctl->radar_detect_offset - ); - - _RTW_PRINT_SEL(sel, ", domain:%u", rtw_odm_get_dfs_domain(dvobj->padapters[IFACE_ID0])); - - rtw_get_ch_waiting_ms(dvobj->padapters[i] - , rfctl->radar_detect_ch - , rfctl->radar_detect_bw - , rfctl->radar_detect_offset - , &non_ocp_ms - , &cac_ms - ); - - if (non_ocp_ms) - _RTW_PRINT_SEL(sel, ", non_ocp:%d", non_ocp_ms); - if (cac_ms) - _RTW_PRINT_SEL(sel, ", cac:%d", cac_ms); end_dfs_master: _RTW_PRINT_SEL(sel, "\n"); } #endif /* CONFIG_DFS_MASTER */ } -void dump_adapters_info(void *sel, struct dvobj_priv *dvobj) -{ - int i; - _adapter *iface; - u8 u_ch, u_bw, u_offset; - - RTW_PRINT_SEL(sel, "%-8s %-8s %-4s %-4s %-8s %-8s\n" - , "iface_id", "ifname", "port", "bup ", "netif_up", "net_closed"); - - RTW_PRINT_SEL(sel, "------------------------\n"); - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (iface) { - RTW_PRINT_SEL(sel, "%2d %-8s %u %s,%s,%s %s%s\n" - , iface->iface_id - , ADPT_ARG(iface) - , get_hw_port(iface) - , (iface->bup) ? " TRUE" : " FALSE" - , (iface->netif_up) ? " TRUE" : " FALSE" - , (iface->net_closed) ? " TRUE" : " FALSE" - , rtw_is_surprise_removed(iface) ? " SR" : "" - , rtw_is_drv_stopped(iface) ? " DS" : "" - ); - } - } - - RTW_PRINT_SEL(sel, "------------------------\n"); -} - #define SEC_CAM_ENT_ID_TITLE_FMT "%-2s" #define SEC_CAM_ENT_ID_TITLE_ARG "id" #define SEC_CAM_ENT_ID_VALUE_FMT "%2u" @@ -537,6 +587,21 @@ void dump_sec_cam(void *sel, _adapter *adapter) } } +void dump_sec_cam_cache(void *sel, _adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + int i; + + RTW_PRINT_SEL(sel, "SW sec cam cache:\n"); + dump_sec_cam_ent_title(sel, 1); + for (i = 0; i < cam_ctl->num; i++) { + if (dvobj->cam_cache[i].ctrl != 0) + dump_sec_cam_ent(sel, &dvobj->cam_cache[i], i); + } + +} + #ifdef CONFIG_PROC_DEBUG ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { @@ -650,6 +715,108 @@ ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t c } +int proc_get_rx_stat(struct seq_file *m, void *v) +{ + _irqL irqL; + _list *plist, *phead; + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_info *psta = NULL; + struct stainfo_stats *pstats = NULL; + struct sta_priv *pstapriv = &(adapter->stapriv); + u32 i, j; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + pstats = &psta->sta_stats; + + if (pstats == NULL) + continue; + if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(adapter), 6) != _TRUE)) { + RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + RTW_PRINT_SEL(m, "data_rx_cnt :\t%llu\n", pstats->rx_data_pkts - pstats->rx_data_last_pkts); + pstats->rx_data_last_pkts = pstats->rx_data_pkts; + RTW_PRINT_SEL(m, "duplicate_cnt :\t%u\n", pstats->duplicate_cnt); + pstats->duplicate_cnt = 0; + RTW_PRINT_SEL(m, "rx_per_rate_cnt :\n"); + + for (j = 0; j < 0x60; j++) { + RTW_PRINT_SEL(m, "%08u ", pstats->rxratecnt[j]); + pstats->rxratecnt[j] = 0; + if ((j%8) == 7) + RTW_PRINT_SEL(m, "\n"); + } + RTW_PRINT_SEL(m, "\n"); + } + } + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + return 0; +} + +int proc_get_tx_stat(struct seq_file *m, void *v) +{ + _irqL irqL; + _list *plist, *phead; + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_info *psta = NULL, *sta_rec[NUM_STA]; + struct stainfo_stats *pstats = NULL; + struct sta_priv *pstapriv = &(adapter->stapriv); + u32 i, macid_rec_idx = 0; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + struct submit_ctx gotc2h; + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (i = 0; i < NUM_STA; i++) { + sta_rec[i] = NULL; + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(adapter), 6) != _TRUE)) { + sta_rec[macid_rec_idx++] = psta; + } + } + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (i = 0; i < macid_rec_idx; i++) { + pstats = &(sta_rec[i]->sta_stats); + if (pstats == NULL) + continue; + pstapriv->c2h_sta = sta_rec[i]; + rtw_hal_reqtxrpt(adapter, sta_rec[i]->mac_id); + rtw_sctx_init(&gotc2h, 60); + pstapriv->gotc2h = &gotc2h; + if (rtw_sctx_wait(&gotc2h, __func__)) { + RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(sta_rec[i]->hwaddr)); + RTW_PRINT_SEL(m, "data_sent_cnt :\t%u\n", pstats->tx_ok_cnt + pstats->tx_fail_cnt); + RTW_PRINT_SEL(m, "success_cnt :\t%u\n", pstats->tx_ok_cnt); + RTW_PRINT_SEL(m, "failure_cnt :\t%u\n", pstats->tx_fail_cnt); + RTW_PRINT_SEL(m, "retry_cnt :\t%u\n\n", pstats->tx_retry_cnt); + } else { + RTW_PRINT_SEL(m, "Warming : Query timeout, operation abort!!\n"); + RTW_PRINT_SEL(m, "\n"); + pstapriv->c2h_sta = NULL; + break; + } + } + return 0; +} + int proc_get_fwstate(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -668,8 +835,8 @@ int proc_get_sec_info(struct seq_file *m, void *v) struct security_priv *sec = &padapter->securitypriv; RTW_PRINT_SEL(m, "auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", - sec->dot11AuthAlgrthm, sec->dot11PrivacyAlgrthm, - sec->ndisauthtype, sec->ndisencryptstatus); + sec->dot11AuthAlgrthm, sec->dot11PrivacyAlgrthm, + sec->ndisauthtype, sec->ndisencryptstatus); RTW_PRINT_SEL(m, "hw_decrypted=%d\n", sec->hw_decrypted); @@ -750,12 +917,13 @@ int proc_get_roam_param(struct seq_file *m, void *v) _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *mlme = &adapter->mlmepriv; - RTW_PRINT_SEL(m, "%12s %12s %11s\n", "rssi_diff_th", "scanr_exp_ms", "scan_int_ms"); - RTW_PRINT_SEL(m, "%-12u %-12u %-11u\n" - , mlme->roam_rssi_diff_th - , mlme->roam_scanr_exp_ms - , mlme->roam_scan_int_ms - ); + RTW_PRINT_SEL(m, "%12s %12s %11s %14s\n", "rssi_diff_th", "scanr_exp_ms", "scan_int_ms", "rssi_threshold"); + RTW_PRINT_SEL(m, "%-12u %-12u %-11u %-14u\n" + , mlme->roam_rssi_diff_th + , mlme->roam_scanr_exp_ms + , mlme->roam_scan_int_ms + , mlme->roam_rssi_threshold + ); return 0; } @@ -770,6 +938,7 @@ ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t u8 rssi_diff_th; u32 scanr_exp_ms; u32 scan_int_ms; + u8 rssi_threshold; if (count < 1) return -EFAULT; @@ -781,7 +950,7 @@ ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hhu %u %u", &rssi_diff_th, &scanr_exp_ms, &scan_int_ms); + int num = sscanf(tmp, "%hhu %u %u %hhu", &rssi_diff_th, &scanr_exp_ms, &scan_int_ms, &rssi_threshold); if (num >= 1) mlme->roam_rssi_diff_th = rssi_diff_th; @@ -789,6 +958,8 @@ ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t mlme->roam_scanr_exp_ms = scanr_exp_ms; if (num >= 3) mlme->roam_scan_int_ms = scan_int_ms; + if (num >= 4) + mlme->roam_rssi_threshold = rssi_threshold; } return count; @@ -824,6 +995,45 @@ ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, siz } #endif /* CONFIG_LAYER2_ROAMING */ +#ifdef CONFIG_RTW_80211R +ssize_t proc_set_ft_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + char tmp[32]; + u8 flags; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%hhx", &flags); + + if (num == 1) + adapter->mlmepriv.ftpriv.ft_flags = flags; + } + + return count; + +} + +int proc_get_ft_flags(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_PRINT_SEL(m, "0x%02x\n", adapter->mlmepriv.ftpriv.ft_flags); + + return 0; +} +#endif + int proc_get_qos_option(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -898,24 +1108,24 @@ int proc_get_scan_param(struct seq_file *m, void *v) #endif RTW_PRINT_SEL(m, - SCAN_PARAM_TITLE_FMT - SCAN_PARAM_TITLE_FMT_HT - SCAN_PARAM_TITLE_FMT_BACKOP - "\n" - SCAN_PARAM_TITLE_ARG - SCAN_PARAM_TITLE_ARG_HT - SCAN_PARAM_TITLE_ARG_BACKOP - ); + SCAN_PARAM_TITLE_FMT + SCAN_PARAM_TITLE_FMT_HT + SCAN_PARAM_TITLE_FMT_BACKOP + "\n" + SCAN_PARAM_TITLE_ARG + SCAN_PARAM_TITLE_ARG_HT + SCAN_PARAM_TITLE_ARG_BACKOP + ); RTW_PRINT_SEL(m, - SCAN_PARAM_VALUE_FMT - SCAN_PARAM_VALUE_FMT_HT - SCAN_PARAM_VALUE_FMT_BACKOP - "\n" - SCAN_PARAM_VALUE_ARG - SCAN_PARAM_VALUE_ARG_HT - SCAN_PARAM_VALUE_ARG_BACKOP - ); + SCAN_PARAM_VALUE_FMT + SCAN_PARAM_VALUE_FMT_HT + SCAN_PARAM_VALUE_FMT_BACKOP + "\n" + SCAN_PARAM_VALUE_ARG + SCAN_PARAM_VALUE_ARG_HT + SCAN_PARAM_VALUE_ARG_BACKOP + ); return 0; } @@ -962,13 +1172,13 @@ ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t if (buffer && !copy_from_user(tmp, buffer, count)) { int num = sscanf(tmp, - SCAN_PARAM_INPUT_FMT - SCAN_PARAM_INPUT_FMT_HT - SCAN_PARAM_INPUT_FMT_BACKOP - SCAN_PARAM_INPUT_ARG - SCAN_PARAM_INPUT_ARG_HT - SCAN_PARAM_INPUT_ARG_BACKOP - ); + SCAN_PARAM_INPUT_FMT + SCAN_PARAM_INPUT_FMT_HT + SCAN_PARAM_INPUT_FMT_BACKOP + SCAN_PARAM_INPUT_ARG + SCAN_PARAM_INPUT_ARG_HT + SCAN_PARAM_INPUT_ARG_BACKOP + ); if (num-- > 0) ss->scan_ch_ms = scan_ch_ms; @@ -1174,7 +1384,7 @@ ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_ return -EFAULT; #ifdef CONFIG_MP_INCLUDED - if (rtw_mi_mp_mode_check(padapter)) { + if (rtw_mp_mode_check(padapter)) { RTW_INFO("MP mode block Scan request\n"); goto exit; } @@ -1186,38 +1396,39 @@ ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_ rtw_ps_deny(padapter, PS_DENY_SCAN); if (_FAIL == rtw_pwr_wakeup(padapter)) - goto exit; + goto cancel_ps_deny; if (!rtw_is_adapter_up(padapter)) { RTW_INFO("scan abort!! adapter cannot use\n"); - goto exit; + goto cancel_ps_deny; } if (rtw_mi_busy_traffic_check(padapter, _FALSE)) { RTW_INFO("scan abort!! BusyTraffic == _TRUE\n"); - goto exit; + goto cancel_ps_deny; } if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { RTW_INFO("scan abort!! AP mode process WPS\n"); - goto exit; + goto cancel_ps_deny; } if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) { RTW_INFO("scan abort!! fwstate=0x%x\n", pmlmepriv->fw_state); - goto exit; + goto cancel_ps_deny; } #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_SURVEY | _FW_UNDER_LINKING | WIFI_UNDER_WPS)) { RTW_INFO("scan abort!! buddy_fwstate check failed\n"); - goto exit; + goto cancel_ps_deny; } #endif _status = rtw_set_802_11_bssid_list_scan(padapter, NULL, 0, NULL, 0); -exit: +cancel_ps_deny: rtw_ps_deny_cancel(padapter, PS_DENY_SCAN); +exit: return count; } @@ -1383,10 +1594,10 @@ int proc_get_rate_ctl(struct seq_file *m, void *v) sgi = adapter->fix_rate >> 7; data_fb = adapter->data_fb ? 1 : 0; RTW_PRINT_SEL(m, "FIXED %s%s%s\n" - , HDATA_RATE(data_rate) + , HDATA_RATE(data_rate) , data_rate > DESC_RATE54M ? (sgi ? " SGI" : " LGI") : "" - , data_fb ? " FB" : "" - ); + , data_fb ? " FB" : "" + ); RTW_PRINT_SEL(m, "0x%02x %u\n", adapter->fix_rate, adapter->data_fb); } else RTW_PRINT_SEL(m, "RA\n"); @@ -1414,35 +1625,36 @@ ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t c int num = sscanf(tmp, "%hhx %hhu", &fix_rate, &data_fb); - if (num >= 1) + if (num >= 1) { + u8 fix_rate_ori = adapter->fix_rate; + adapter->fix_rate = fix_rate; + if (adapter->fix_bw != 0xFF && fix_rate_ori != fix_rate) + rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter)); + } if (num >= 2) adapter->data_fb = data_fb ? 1 : 0; } return count; } -int proc_get_bw_ctl(struct seq_file *m, void *v) + +int proc_get_tx_power_offset(struct seq_file *m, void *v) { struct net_device *dev = m->private; + int i; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - u8 data_bw = 0; - - if (adapter->fix_bw != 0xff) { - data_bw = adapter->fix_bw; - RTW_PRINT_SEL(m, "FIXED %s\n", HDATA_BW(data_bw)); - } else - RTW_PRINT_SEL(m, "Auto\n"); + RTW_PRINT_SEL(m, "Tx power offset - %u\n", adapter->power_offset); return 0; } -ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; - u8 fix_bw; + u8 power_offset = 0; if (count < 1) return -EFAULT; @@ -1453,32 +1665,83 @@ ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t cou } if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hhu", &fix_bw); - if (num >= 1) - adapter->fix_bw = fix_bw; + int num = sscanf(tmp, "%hhu", &power_offset); + + if (num >= 1) { + if (power_offset > 5) + power_offset = 0; + + adapter->power_offset = power_offset; + } } return count; } -#ifdef DBG_RX_COUNTER_DUMP -int proc_get_rx_cnt_dump(struct seq_file *m, void *v) +int proc_get_bw_ctl(struct seq_file *m, void *v) { struct net_device *dev = m->private; - int i; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u8 data_bw = 0; - RTW_PRINT_SEL(m, "BIT0- Dump RX counters of DRV\n"); - RTW_PRINT_SEL(m, "BIT1- Dump RX counters of MAC\n"); - RTW_PRINT_SEL(m, "BIT2- Dump RX counters of PHY\n"); - RTW_PRINT_SEL(m, "BIT3- Dump TRX data frame of DRV\n"); - RTW_PRINT_SEL(m, "dump_rx_cnt_mode = 0x%02x\n", adapter->dump_rx_cnt_mode); + if (adapter->fix_bw != 0xff) { + data_bw = adapter->fix_bw; + RTW_PRINT_SEL(m, "FIXED %s\n", ch_width_str(data_bw)); + } else + RTW_PRINT_SEL(m, "Auto\n"); return 0; } -ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ + +ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 fix_bw; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%hhu", &fix_bw); + + if (num >= 1) { + u8 fix_bw_ori = adapter->fix_bw; + + adapter->fix_bw = fix_bw; + + if (adapter->fix_rate != 0xFF && fix_bw_ori != fix_bw) + rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter)); + } + } + + return count; +} + +#ifdef DBG_RX_COUNTER_DUMP +int proc_get_rx_cnt_dump(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + int i; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_PRINT_SEL(m, "BIT0- Dump RX counters of DRV\n"); + RTW_PRINT_SEL(m, "BIT1- Dump RX counters of MAC\n"); + RTW_PRINT_SEL(m, "BIT2- Dump RX counters of PHY\n"); + RTW_PRINT_SEL(m, "BIT3- Dump TRX data frame of DRV\n"); + RTW_PRINT_SEL(m, "dump_rx_cnt_mode = 0x%02x\n", adapter->dump_rx_cnt_mode); + + return 0; +} +ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; @@ -1504,6 +1767,30 @@ ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_ return count; } #endif + +static u8 fwdl_test_chksum_fail = 0; +static u8 fwdl_test_wintint_rdy_fail = 0; + +bool rtw_fwdl_test_trigger_chksum_fail(void) +{ + if (fwdl_test_chksum_fail) { + RTW_PRINT("fwdl test case: trigger chksum_fail\n"); + fwdl_test_chksum_fail--; + return _TRUE; + } + return _FALSE; +} + +bool rtw_fwdl_test_trigger_wintint_rdy_fail(void) +{ + if (fwdl_test_wintint_rdy_fail) { + RTW_PRINT("fwdl test case: trigger wintint_rdy_fail\n"); + fwdl_test_wintint_rdy_fail--; + return _TRUE; + } + return _FALSE; +} + ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; @@ -1525,6 +1812,18 @@ ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, si return count; } +static u8 del_rx_ampdu_test_no_tx_fail = 0; + +bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void) +{ + if (del_rx_ampdu_test_no_tx_fail) { + RTW_PRINT("del_rx_ampdu test case: trigger no_tx_fail\n"); + del_rx_ampdu_test_no_tx_fail--; + return _TRUE; + } + return _FALSE; +} + ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; @@ -1555,9 +1854,9 @@ int proc_get_dfs_master_test_case(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "%-24s %-19s\n", "radar_detect_trigger_non", "choose_dfs_ch_first"); RTW_PRINT_SEL(m, "%24hhu %19hhu\n" - , rfctl->dbg_dfs_master_radar_detect_trigger_non - , rfctl->dbg_dfs_master_choose_dfs_ch_first - ); + , rfctl->dbg_dfs_master_radar_detect_trigger_non + , rfctl->dbg_dfs_master_choose_dfs_ch_first + ); return 0; } @@ -1592,6 +1891,13 @@ ssize_t proc_set_dfs_master_test_case(struct file *file, const char __user *buff } #endif /* CONFIG_DFS_MASTER */ +static u32 g_wait_hiq_empty_ms = 0; + +u32 rtw_get_wait_hiq_empty_ms(void) +{ + return g_wait_hiq_empty_ms; +} + ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; @@ -1613,6 +1919,53 @@ ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, si return count; } +static u32 sta_linking_test_start_time = 0; +static u32 sta_linking_test_wait_ms = 0; +static u8 sta_linking_test_force_fail = 0; + +void rtw_sta_linking_test_set_start(void) +{ + sta_linking_test_start_time = rtw_get_current_time(); +} + +bool rtw_sta_linking_test_wait_done(void) +{ + return rtw_get_passing_time_ms(sta_linking_test_start_time) >= sta_linking_test_wait_ms; +} + +bool rtw_sta_linking_test_force_fail(void) +{ + return sta_linking_test_force_fail; +} + +ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + u32 wait_ms = 0; + u8 force_fail = 0; + int num = sscanf(tmp, "%u %hhu", &wait_ms, &force_fail); + + if (num >= 1) + sta_linking_test_wait_ms = wait_ms; + if (num >= 2) + sta_linking_test_force_fail = force_fail; + } + + return count; +} + int proc_get_suspend_resume_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -1921,8 +2274,11 @@ int proc_get_hw_status(struct seq_file *m, void *v) _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct dvobj_priv *dvobj = padapter->dvobj; struct debug_priv *pdbgpriv = &dvobj->drv_dbg; + struct registry_priv *regsty = dvobj_to_regsty(dvobj); - if (pdbgpriv->dbg_rx_fifo_last_overflow == 1 + if (regsty->check_hw_status == 0) + RTW_PRINT_SEL(m, "RX FIFO full count: not check in watch dog\n"); + else if (pdbgpriv->dbg_rx_fifo_last_overflow == 1 && pdbgpriv->dbg_rx_fifo_curr_overflow == 1 && pdbgpriv->dbg_rx_fifo_diff_overflow == 1 ) @@ -1934,6 +2290,37 @@ int proc_get_hw_status(struct seq_file *m, void *v) return 0; } + +ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = padapter->dvobj; + struct registry_priv *regsty = dvobj_to_regsty(dvobj); + char tmp[32]; + u32 enable; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &enable); + + if (regsty && enable <= 1) { + regsty->check_hw_status = enable; + RTW_INFO("check_hw_status=%d\n", regsty->check_hw_status); + } + } + + return count; +} + int proc_get_trx_info_debug(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -1963,6 +2350,25 @@ int proc_get_rx_signal(struct seq_file *m, void *v) /* RTW_PRINT_SEL(m, "rxpwdb:%d\n", padapter->recvpriv.rxpwdb); */ RTW_PRINT_SEL(m, "signal_strength:%u\n", padapter->recvpriv.signal_strength); RTW_PRINT_SEL(m, "signal_qual:%u\n", padapter->recvpriv.signal_qual); + if (padapter->registrypriv.mp_mode == 1) { + if (padapter->mppriv.antenna_rx == ANTENNA_A) + RTW_PRINT_SEL(m, "Antenna: A\n"); + else if (padapter->mppriv.antenna_rx == ANTENNA_B) + RTW_PRINT_SEL(m, "Antenna: B\n"); + else if (padapter->mppriv.antenna_rx == ANTENNA_C) + RTW_PRINT_SEL(m, "Antenna: C\n"); + else if (padapter->mppriv.antenna_rx == ANTENNA_D) + RTW_PRINT_SEL(m, "Antenna: D\n"); + else if (padapter->mppriv.antenna_rx == ANTENNA_AB) + RTW_PRINT_SEL(m, "Antenna: AB\n"); + else if (padapter->mppriv.antenna_rx == ANTENNA_BC) + RTW_PRINT_SEL(m, "Antenna: BC\n"); + else if (padapter->mppriv.antenna_rx == ANTENNA_CD) + RTW_PRINT_SEL(m, "Antenna: CD\n"); + else + RTW_PRINT_SEL(m, "Antenna: __\n"); + return 0; + } rtw_get_noise(padapter); RTW_PRINT_SEL(m, "noise:%d\n", padapter->recvpriv.noise); @@ -2075,6 +2481,8 @@ ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t co struct registry_priv *pregpriv = &padapter->registrypriv; char tmp[32]; u32 mode; + u8 bw_2g; + u8 bw_5g; if (count < 1) return -EFAULT; @@ -2086,12 +2494,14 @@ ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t co if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d ", &mode); + int num = sscanf(tmp, "%x ", &mode); + bw_5g = mode >> 4; + bw_2g = mode & 0x0f; - if (pregpriv && mode < 2) { + if (pregpriv && bw_2g <= 4 && bw_5g <= 4) { pregpriv->bw_mode = mode; - printk("bw_mode=%d\n", mode); + printk("bw_mode=0x%x\n", mode); } } @@ -2132,7 +2542,7 @@ ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size int num = sscanf(tmp, "%d ", &mode); - if (pregpriv && mode < 3) { + if (pregpriv && mode < 2) { pregpriv->ampdu_enable = mode; printk("ampdu_enable=%d\n", mode); } @@ -2172,6 +2582,20 @@ int proc_get_mac_rptbuf(struct seq_file *m, void *v) return 0; } +void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = adapter_to_regsty(adapter); + int i; + + RTW_PRINT_SEL(sel, "%-3s %-3s %-3s %-3s %-4s\n" + , "", "20M", "40M", "80M", "160M"); + for (i = 0; i < 4; i++) + RTW_PRINT_SEL(sel, "%dSS %3u %3u %3u %4u\n", i + 1 + , regsty->rx_ampdu_sz_limit_by_nss_bw[i][0] + , regsty->rx_ampdu_sz_limit_by_nss_bw[i][1] + , regsty->rx_ampdu_sz_limit_by_nss_bw[i][2] + , regsty->rx_ampdu_sz_limit_by_nss_bw[i][3]); +} int proc_get_rx_ampdu(struct seq_file *m, void *v) { @@ -2185,16 +2609,18 @@ int proc_get_rx_ampdu(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_accept, "(fixed)"); _RTW_PRINT_SEL(m, "size: "); - if (padapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) - RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_size(padapter), "(auto)"); - else + if (padapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) { + RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_size(padapter), "(auto) with conditional limit:"); + dump_regsty_rx_ampdu_size_limit(m, padapter); + } else RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_size, "(fixed)"); + RTW_PRINT_SEL(m, "\n"); RTW_PRINT_SEL(m, "%19s %17s\n", "fix_rx_ampdu_accept", "fix_rx_ampdu_size"); _RTW_PRINT_SEL(m, "%-19d %-17u\n" - , padapter->fix_rx_ampdu_accept - , padapter->fix_rx_ampdu_size); + , padapter->fix_rx_ampdu_accept + , padapter->fix_rx_ampdu_size); return 0; } @@ -2278,6 +2704,48 @@ ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer return count; } +int proc_get_tx_max_agg_num(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + + if (padapter) + RTW_PRINT_SEL(m, "tx max AMPDU num = 0x%02x\n", padapter->driver_tx_max_agg_num); + + return 0; +} + +ssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer + , size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 agg_num; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx ", &agg_num); + + if (padapter && (num == 1)) { + RTW_INFO("padapter->driver_tx_max_agg_num = 0x%02x\n", agg_num); + + padapter->driver_tx_max_agg_num = agg_num; + } + } + + return count; +} + int proc_get_rx_ampdu_density(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -2365,7 +2833,8 @@ ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, return count; } -#ifdef TX_AMSDU + +#ifdef CONFIG_TX_AMSDU int proc_get_tx_amsdu(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -2424,14 +2893,13 @@ ssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t c return count; } - int proc_get_tx_amsdu_rate(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); if (padapter) - RTW_PRINT_SEL(m, "tx ampdu rate = %d Mbps\n", padapter->tx_amsdu_rate); + RTW_PRINT_SEL(m, "tx amsdu rate = %d Mbps\n", padapter->tx_amsdu_rate); return 0; } @@ -2456,14 +2924,14 @@ ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, siz int num = sscanf(tmp, "%d ", &amsdu_rate); if (padapter && (num == 1)) { - RTW_INFO("padapter->tx_amsdu_rate = %d Mbps\n", amsdu_rate); + RTW_INFO("padapter->tx_amsdu_rate = %x\n", amsdu_rate); padapter->tx_amsdu_rate = amsdu_rate; } } return count; } -#endif +#endif /* CONFIG_TX_AMSDU */ #endif /* CONFIG_80211N_HT */ int proc_get_en_fwps(struct seq_file *m, void *v) @@ -2523,23 +2991,243 @@ int proc_get_two_path_rssi(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "%d %d\n", padapter->recvpriv.RxRssi[0], padapter->recvpriv.RxRssi[1]); - return 0; + return 0; +} +*/ +#ifdef CONFIG_80211N_HT +void rtw_dump_dft_phy_cap(void *sel, _adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + #ifdef CONFIG_80211AC_VHT + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + #endif + + #ifdef CONFIG_80211AC_VHT + RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) ? "V" : "X"); + #endif + RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Tx : %s\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) ? "V" : "X"); + + #ifdef CONFIG_80211AC_VHT + RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) ? "V" : "X"); + #endif + RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Tx : %s\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) ? "V" : "X"); + + #ifdef CONFIG_BEAMFORMING + #ifdef CONFIG_80211AC_VHT + RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) ? "V" : "X"); + #endif + RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfer : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfee : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) ? "V" : "X"); + #endif +} + +void rtw_get_dft_phy_cap(void *sel, _adapter *adapter) +{ + RTW_PRINT_SEL(sel, "\n ======== PHY CAP protocol ========\n"); + rtw_ht_use_default_setting(adapter); + #ifdef CONFIG_80211AC_VHT + rtw_vht_use_default_setting(adapter); + #endif + rtw_dump_dft_phy_cap(sel, adapter); +} + +void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter) +{ + struct registry_priv *pregistry_priv = &adapter->registrypriv; + + RTW_PRINT_SEL(sel, "\n ======== DRV's configuration ========\n"); + #if 0 + RTW_PRINT_SEL(sel, "[DRV CAP] TRx Capability : 0x%08x\n", phy_spec->trx_cap); + RTW_PRINT_SEL(sel, "[DRV CAP] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/ + RTW_PRINT_SEL(sel, "[DRV CAP] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/ + RTW_PRINT_SEL(sel, "[DRV CAP] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index [15:8]*/ + RTW_PRINT_SEL(sel, "[DRV CAP] Rx Path Num Index : %d\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index [7:0]*/ + #endif + + RTW_PRINT_SEL(sel, "[DRV CAP] STBC Capability : 0x%02x\n", pregistry_priv->stbc_cap); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT STBC Tx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT STBC Rx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT STBC Tx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT STBC Rx*/ + + RTW_PRINT_SEL(sel, "[DRV CAP] LDPC Capability : 0x%02x\n", pregistry_priv->ldpc_cap); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT LDPC Tx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT LDPC Rx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT LDPC Tx*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT LDPC Rx*/ + #ifdef CONFIG_BEAMFORMING + #if 0 + RTW_PRINT_SEL(sel, "[DRV CAP] TxBF parameter : 0x%08x\n", phy_spec->txbf_param); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/ + RTW_PRINT_SEL(sel, "[DRV CAP] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/ + RTW_PRINT_SEL(sel, "[DRV CAP] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/ + #endif + + /* + * BIT0: Enable VHT SU Beamformer + * BIT1: Enable VHT SU Beamformee + * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer + * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee + * BIT4: Enable HT Beamformer + * BIT5: Enable HT Beamformee + */ + RTW_PRINT_SEL(sel, "[DRV CAP] TxBF Capability : 0x%02x\n", pregistry_priv->beamform_cap); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT2)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT3)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT0)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT1)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT4)) ? "V" : "X"); + RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT5)) ? "V" : "X"); + + RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfer rf_num : %d\n", pregistry_priv->beamformer_rf_num); + RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfee rf_num : %d\n", pregistry_priv->beamformee_rf_num); + #endif +} + +int proc_get_stbc_cap(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + if (pregpriv) + RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->stbc_cap); + + return 0; +} + +ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u32 mode; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &mode); + + if (pregpriv) { + pregpriv->stbc_cap = mode; + RTW_INFO("stbc_cap = 0x%02x\n", mode); + } + } + + return count; +} +int proc_get_rx_stbc(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + if (pregpriv) + RTW_PRINT_SEL(m, "%d\n", pregpriv->rx_stbc); + + return 0; +} + +ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u32 mode; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &mode); + + if (pregpriv && (mode == 0 || mode == 1 || mode == 2 || mode == 3)) { + pregpriv->rx_stbc = mode; + printk("rx_stbc=%d\n", mode); + } + } + + return count; + +} +int proc_get_ldpc_cap(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + if (pregpriv) + RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->ldpc_cap); + + return 0; +} + +ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u32 mode; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &mode); + + if (pregpriv) { + pregpriv->ldpc_cap = mode; + RTW_INFO("ldpc_cap = 0x%02x\n", mode); + } + } + + return count; } -*/ -#ifdef CONFIG_80211N_HT -int proc_get_rx_stbc(struct seq_file *m, void *v) +#ifdef CONFIG_BEAMFORMING +int proc_get_txbf_cap(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct registry_priv *pregpriv = &padapter->registrypriv; if (pregpriv) - RTW_PRINT_SEL(m, "%d\n", pregpriv->rx_stbc); + RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->beamform_cap); return 0; } -ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -2559,15 +3247,15 @@ ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t co int num = sscanf(tmp, "%d ", &mode); - if (pregpriv && (mode == 0 || mode == 1 || mode == 2 || mode == 3)) { - pregpriv->rx_stbc = mode; - printk("rx_stbc=%d\n", mode); + if (pregpriv) { + pregpriv->beamform_cap = mode; + RTW_INFO("beamform_cap = 0x%02x\n", mode); } } return count; - } +#endif #endif /* CONFIG_80211N_HT */ /*int proc_get_rssi_disp(struct seq_file *m, void *v) @@ -2745,48 +3433,49 @@ int proc_get_best_channel(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0; - for (i = 0; pmlmeext->channel_set[i].ChannelNum != 0; i++) { - if (pmlmeext->channel_set[i].ChannelNum == 1) + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) { + if (rfctl->channel_set[i].ChannelNum == 1) index_24G = i; - if (pmlmeext->channel_set[i].ChannelNum == 36) + if (rfctl->channel_set[i].ChannelNum == 36) index_5G = i; } - for (i = 0; (i < MAX_CHANNEL_NUM) && (pmlmeext->channel_set[i].ChannelNum != 0) ; i++) { + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) { /* 2.4G */ - if (pmlmeext->channel_set[i].ChannelNum == 6) { - if (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_24G].rx_count) { + if (rfctl->channel_set[i].ChannelNum == 6) { + if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) { index_24G = i; - best_channel_24G = pmlmeext->channel_set[i].ChannelNum; + best_channel_24G = rfctl->channel_set[i].ChannelNum; } } /* 5G */ - if (pmlmeext->channel_set[i].ChannelNum >= 36 - && pmlmeext->channel_set[i].ChannelNum < 140) { + if (rfctl->channel_set[i].ChannelNum >= 36 + && rfctl->channel_set[i].ChannelNum < 140) { /* Find primary channel */ - if (((pmlmeext->channel_set[i].ChannelNum - 36) % 8 == 0) - && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count)) { + if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0) + && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) { index_5G = i; - best_channel_5G = pmlmeext->channel_set[i].ChannelNum; + best_channel_5G = rfctl->channel_set[i].ChannelNum; } } - if (pmlmeext->channel_set[i].ChannelNum >= 149 - && pmlmeext->channel_set[i].ChannelNum < 165) { + if (rfctl->channel_set[i].ChannelNum >= 149 + && rfctl->channel_set[i].ChannelNum < 165) { /* find primary channel */ - if (((pmlmeext->channel_set[i].ChannelNum - 149) % 8 == 0) - && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count)) { + if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0) + && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) { index_5G = i; - best_channel_5G = pmlmeext->channel_set[i].ChannelNum; + best_channel_5G = rfctl->channel_set[i].ChannelNum; } } #if 1 /* debug */ RTW_PRINT_SEL(m, "The rx cnt of channel %3d = %d\n", - pmlmeext->channel_set[i].ChannelNum, pmlmeext->channel_set[i].rx_count); + rfctl->channel_set[i].ChannelNum, rfctl->channel_set[i].rx_count); #endif } @@ -2800,6 +3489,7 @@ ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; char tmp[32]; @@ -2813,8 +3503,8 @@ ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size if (buffer && !copy_from_user(tmp, buffer, count)) { int i; - for (i = 0; pmlmeext->channel_set[i].ChannelNum != 0; i++) - pmlmeext->channel_set[i].rx_count = 0; + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) + rfctl->channel_set[i].rx_count = 0; RTW_INFO("set %s\n", "Clean Best Channel Count"); } @@ -2917,6 +3607,55 @@ int proc_get_btcoex_info(struct seq_file *m, void *v) return 0; } + +#ifdef CONFIG_RF4CE_COEXIST +int proc_get_rf4ce_state(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u8 state = 0, voice = 0; + + state = rtw_btcoex_GetRf4ceLinkState(adapter); + + RTW_PRINT_SEL(m, "RF4CE %s\n", state?"Connected":"Disconnect"); + + return 0; +} + +/* This interface is designed for user space application to inform RF4CE state + * Initial define for DHC 1295 E387 project + * + * echo state voice > rf4ce_state + * state + * 0: RF4CE disconnected + * 1: RF4CE connected + */ +ssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 state; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &state); + + if (num >= 1) + rtw_btcoex_SetRf4ceLinkState(adapter, state); + } + + return count; +} +#endif /* CONFIG_RF4CE_COEXIST */ #endif /* CONFIG_BT_COEXIST */ #if defined(DBG_CONFIG_ERROR_DETECT) @@ -2961,6 +3700,57 @@ ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t cou #ifdef CONFIG_PCI_HCI +int proc_get_pci_aspm(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); + u8 tmp8 = 0; + u16 tmp16 = 0; + u32 tmp32 = 0; + + + RTW_PRINT_SEL(m, "***** ASPM Capability *****\n"); + + pci_read_config_dword(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32); + + RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp32&BIT10) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp32&BIT11) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_l1off_capability(padapter); + RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", tmp8 ? "Enable" : "Disable"); + + RTW_PRINT_SEL(m, "***** ASPM CTRL Reg *****\n"); + + pci_read_config_word(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16); + + RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp16&BIT0) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp16&BIT1) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_l1off_nic_support(padapter); + RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", tmp8 ? "Enable" : "Disable"); + + RTW_PRINT_SEL(m, "***** ASPM Backdoor *****\n"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); + RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp8 & BIT4) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f); + RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp8&BIT7) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); + RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp8 & BIT3) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718); + RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", (tmp8 & BIT5) ? "Enable" : "Disable"); + + return 0; +} + int proc_get_rx_ring(struct seq_file *m, void *v) { _irqL irqL; @@ -3129,7 +3919,7 @@ ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer, return -EFAULT; } - if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_NUM) { + if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) { RTW_INFO("WARNING: priv-pattern is full(idx: %d)\n", pwrpriv->wowlan_pattern_idx); RTW_INFO("WARNING: please clean priv-pattern first\n"); @@ -3154,7 +3944,18 @@ ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer, return count; } -#endif + +int proc_get_wakeup_reason(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + u8 val = pwrpriv->wowlan_last_wake_reason; + + RTW_PRINT_SEL(m, "last wake reason: %#02x\n", val); + return 0; +} +#endif /*CONFIG_WOWLAN*/ #ifdef CONFIG_GPIO_WAKEUP int proc_get_wowlan_gpio_info(struct seq_file *m, void *v) @@ -3280,6 +4081,7 @@ int proc_get_ps_info(struct seq_file *m, void *v) struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); u8 ips_mode = pwrpriv->ips_mode; u8 lps_mode = pwrpriv->power_mgnt; + u8 lps_level = pwrpriv->lps_level; char *str = ""; RTW_PRINT_SEL(m, "======Power Saving Info:======\n"); @@ -3321,6 +4123,15 @@ int proc_get_ps_info(struct seq_file *m, void *v) RTW_PRINT_SEL(m, " DTIM: %d\n", pwrpriv->dtim); RTW_PRINT_SEL(m, " LPS enter count:%d, LPS leave count:%d\n", pwrpriv->lps_enter_cnts, pwrpriv->lps_leave_cnts); + + if (lps_level == LPS_LCLK) + str = "LPS_LCLK"; + else if (lps_level == LPS_PG) + str = "LPS_PG"; + else + str = "LPS_NORMAL"; + RTW_PRINT_SEL(m, " LPS level: %s\n", str); + RTW_PRINT_SEL(m, "=============================\n"); return 0; } @@ -3774,6 +4585,52 @@ ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t co return count; } +#ifdef DBG_XMIT_BLOCK +int proc_get_xmit_block(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + dump_xmit_block(m, padapter); + + return 0; +} + +ssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 xb_mode, xb_reason; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx %hhx", &xb_mode, &xb_reason); + + if (num != 2) { + RTW_INFO("invalid parameter!\n"); + return count; + } + + if (xb_mode == 0)/*set*/ + rtw_set_xmit_block(padapter, xb_reason); + else if (xb_mode == 1)/*clear*/ + rtw_clr_xmit_block(padapter, xb_reason); + else + RTW_INFO("invalid parameter!\n"); + } + + return count; +} +#endif #include int proc_get_efuse_map(struct seq_file *m, void *v) @@ -3793,24 +4650,49 @@ int proc_get_efuse_map(struct seq_file *m, void *v) ips_mode = pwrctrlpriv->ips_mode; rtw_pm_set_ips(padapter, IPS_NONE); - if (rtw_efuse_map_read(padapter, 0, mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL) + + if (pHalData->efuse_file_status == EFUSE_FILE_LOADED) { + RTW_PRINT_SEL(m, "File eFuse Map loaded! file path:%s\nDriver eFuse Map From File\n", EFUSE_MAP_PATH); + if (pHalData->bautoload_fail_flag) + RTW_PRINT_SEL(m, "File Autoload fail!!!\n"); + } else if (pHalData->efuse_file_status == EFUSE_FILE_FAILED) { + RTW_PRINT_SEL(m, "Open File eFuse Map Fail ! file path:%s\nDriver eFuse Map From Default\n", EFUSE_MAP_PATH); + if (pHalData->bautoload_fail_flag) + RTW_PRINT_SEL(m, "HW Autoload fail!!!\n"); + } else { + RTW_PRINT_SEL(m, "Driver eFuse Map From HW\n"); + if (pHalData->bautoload_fail_flag) + RTW_PRINT_SEL(m, "HW Autoload fail!!!\n"); + } + for (i = 0; i < mapLen; i += 16) { + RTW_PRINT_SEL(m, "0x%02x\t", i); + for (j = 0; j < 8; j++) + RTW_PRINT_SEL(m, "%02X ", pHalData->efuse_eeprom_data[i + j]); + RTW_PRINT_SEL(m, "\t"); + for (; j < 16; j++) + RTW_PRINT_SEL(m, "%02X ", pHalData->efuse_eeprom_data[i + j]); + RTW_PRINT_SEL(m, "\n"); + } + + if (rtw_efuse_map_read(padapter, 0, mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL) { RTW_PRINT_SEL(m, "WARN - Read Realmap Failed\n"); + return 0; + } RTW_PRINT_SEL(m, "\n"); + RTW_PRINT_SEL(m, "HW eFuse Map\n"); for (i = 0; i < mapLen; i += 16) { RTW_PRINT_SEL(m, "0x%02x\t", i); for (j = 0; j < 8; j++) RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]); - RTW_PRINT_SEL(m, "\t"); - for (; j < 16; j++) RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]); - RTW_PRINT_SEL(m, "\n"); - } + rtw_pm_set_ips(padapter, ips_mode); + return 0; } @@ -4101,60 +4983,96 @@ int proc_get_tx_auth(struct seq_file *m, void *v) } #endif /* CONFIG_IEEE80211W */ -#ifdef CONFIG_NAPI -int proc_get_napi(struct seq_file *m, void *v) +#ifdef CONFIG_MCC_MODE +int proc_get_mcc_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_adapters_status(m, adapter_to_dvobj(adapter)); + rtw_hal_dump_mcc_info(m, adapter_to_dvobj(adapter)); + return 0; +} + +int proc_get_mcc_policy_table(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *adapter = (_adapter *) rtw_netdev_priv(dev); - struct registry_priv *reg = &adapter->registrypriv; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - RTW_PRINT_SEL(m, "debug weight\n"); - RTW_PRINT_SEL(m, "------------\n"); - RTW_PRINT_SEL(m, "%05d %06d\n", reg->napi_debug, reg->napi_weight); + rtw_hal_dump_mcc_policy_table(m); return 0; } -ssize_t proc_set_napi(struct file *file, const char __user *buffer, - size_t count, loff_t *pos, void *data) +ssize_t proc_set_mcc_policy_table(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - _adapter *adapter = (_adapter *) rtw_netdev_priv(dev); - struct registry_priv *reg = &adapter->registrypriv; - char tmp[32]; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[255]; + s32 mcc_policy_table_idx; + u32 mcc_duration; + u32 mcc_tsf_sync_offset; + u32 mcc_start_time_offset; + u32 mcc_interval; + s32 mcc_guard_offset0; + s32 mcc_guard_offset1; - if (count < 1) + if (NULL == buffer) { + RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); + return -EFAULT; + } + + if (count < 1) { + RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); return -EFAULT; + } if (count > sizeof(tmp)) { + RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); rtw_warn_on(1); return -EFAULT; } if (buffer && !copy_from_user(tmp, buffer, count)) { - int num; - u32 debug; + #if 1 + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + _adapter *iface = NULL; + u8 i = 0; + int num = sscanf(tmp, "%d %u %u %u %u %d %d" + , &mcc_policy_table_idx, &mcc_duration, &mcc_tsf_sync_offset, &mcc_start_time_offset + , &mcc_interval, &mcc_guard_offset0, &mcc_guard_offset1); - num = sscanf(tmp, "%d ", &debug); - if (num >= 1) - reg->napi_debug = debug ? 1 : 0; + if (num < 7) { + RTW_INFO(FUNC_ADPT_FMT ": input parameters < 7\n", FUNC_ADPT_ARG(padapter)); + return -EINVAL; + } +#if 0 + RTW_INFO("mcc_policy_table_idx:%d\n", mcc_policy_table_idx); + RTW_INFO("mcc_duration:%d\n", mcc_duration); + RTW_INFO("mcc_tsf_sync_offset:%d\n", mcc_tsf_sync_offset); + RTW_INFO("mcc_start_time_offset:%d\n", mcc_start_time_offset); + RTW_INFO("mcc_interval:%d\n", mcc_interval); + RTW_INFO("mcc_guard_offset0:%d\n", mcc_guard_offset0); + RTW_INFO("mcc_guard_offset1:%d\n", mcc_guard_offset1); +#endif + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + iface->registrypriv.rtw_mcc_policy_table_idx = mcc_policy_table_idx; + iface->registrypriv.rtw_mcc_duration = mcc_duration; + iface->registrypriv.rtw_mcc_tsf_sync_offset = mcc_tsf_sync_offset; + iface->registrypriv.rtw_mcc_start_time_offset = mcc_start_time_offset; + iface->registrypriv.rtw_mcc_interval = mcc_interval; + iface->registrypriv.rtw_mcc_guard_offset0 = mcc_guard_offset0; + iface->registrypriv.rtw_mcc_guard_offset1 = mcc_guard_offset1; + } - /* we don't support run-time weight config */ + rtw_hal_mcc_update_switch_channel_policy_table(padapter); + #endif } return count; } -#endif /* CONFIG_NAPI */ - -#ifdef CONFIG_MCC_MODE -int proc_get_mcc_info(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - dump_adapters_status(m, adapter_to_dvobj(adapter)); - rtw_hal_dump_mcc_info(m, adapter_to_dvobj(adapter)); - return 0; -} ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { @@ -4500,4 +5418,118 @@ ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *bu } #endif /* CONFIG_MCC_MODE */ +int proc_get_ack_timeout(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 ack_timeout_val, ack_timeout_val_cck; + + ack_timeout_val = rtw_read8(padapter, REG_ACKTO); + +#ifdef CONFIG_RTL8821C + ack_timeout_val_cck = rtw_read8(padapter, REG_ACKTO_CCK_8821C); + RTW_PRINT_SEL(m, "Current CCK packet ACK Timeout = %d us (0x%x).\n", ack_timeout_val_cck, ack_timeout_val_cck); + RTW_PRINT_SEL(m, "Current non-CCK packet ACK Timeout = %d us (0x%x).\n", ack_timeout_val, ack_timeout_val); +#else + RTW_PRINT_SEL(m, "Current ACK Timeout = %d us (0x%x).\n", ack_timeout_val, ack_timeout_val); +#endif + + return 0; +} + +ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 ack_timeout_ms, ack_timeout_ms_cck; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%u %u", &ack_timeout_ms, &ack_timeout_ms_cck); + +#ifdef CONFIG_RTL8821C + if (num < 2) { + RTW_INFO(FUNC_ADPT_FMT ": input parameters < 2\n", FUNC_ADPT_ARG(padapter)); + return -EINVAL; + } +#else + if (num < 1) { + RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); + return -EINVAL; + } +#endif + /* This register sets the Ack time out value after Tx unicast packet. It is in units of us. */ + rtw_write8(padapter, REG_ACKTO, (u8)ack_timeout_ms); + +#ifdef CONFIG_RTL8821C + /* This register sets the Ack time out value after Tx unicast CCK packet. It is in units of us. */ + rtw_write8(padapter, REG_ACKTO_CCK_8821C, (u8)ack_timeout_ms_cck); + RTW_INFO("Set CCK packet ACK Timeout to %d us.\n", ack_timeout_ms_cck); + RTW_INFO("Set non-CCK packet ACK Timeout to %d us.\n", ack_timeout_ms); +#else + RTW_INFO("Set ACK Timeout to %d us.\n", ack_timeout_ms); +#endif + } + + return count; +} + +ssize_t proc_set_iqk_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + _adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter); + HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); + char tmp[32]; + u32 enable = 0; + + if (buffer == NULL) { + RTW_INFO("input buffer is NULL!\n"); + return -EFAULT; + } + + if (count < 1) { + RTW_INFO("input length is 0!\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + RTW_INFO("input length is too large\n"); + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%d", &enable); + + if (num < 1) { + RTW_INFO("input parameters < 1\n"); + return -EINVAL; + } + + if (hal->RegIQKFWOffload != enable) { + hal->RegIQKFWOffload = enable; + rtw_hal_update_iqk_fw_offload_cap(pri_adapter); + } + } + + return count; +} + +int proc_get_iqk_fw_offload(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); + + + RTW_PRINT_SEL(m, "IQK FW offload:%s\n", hal->RegIQKFWOffload?"enable":"disable"); + return 0; +} + #endif /* CONFIG_PROC_DEBUG */ diff --git a/core/rtw_eeprom.c b/core/rtw_eeprom.c index 78d5758..d48996e 100644 --- a/core/rtw_eeprom.c +++ b/core/rtw_eeprom.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_EEPROM_C_ #include @@ -25,31 +20,25 @@ void up_clk(_adapter *padapter, u16 *x) { - _func_enter_; *x = *x | _EESK; rtw_write8(padapter, EE_9346CR, (u8)*x); rtw_udelay_os(CLOCK_RATE); - _func_exit_; } void down_clk(_adapter *padapter, u16 *x) { - _func_enter_; *x = *x & ~_EESK; rtw_write8(padapter, EE_9346CR, (u8)*x); rtw_udelay_os(CLOCK_RATE); - _func_exit_; } void shift_out_bits(_adapter *padapter, u16 data, u16 count) { u16 x, mask; - _func_enter_; if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } mask = 0x01 << (count - 1); @@ -62,7 +51,6 @@ void shift_out_bits(_adapter *padapter, u16 data, u16 count) if (data & mask) x |= _EEDI; if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } rtw_write8(padapter, EE_9346CR, (u8)x); @@ -72,21 +60,18 @@ void shift_out_bits(_adapter *padapter, u16 data, u16 count) mask = mask >> 1; } while (mask); if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } x &= ~_EEDI; rtw_write8(padapter, EE_9346CR, (u8)x); out: - _func_exit_; + return; } u16 shift_in_bits(_adapter *padapter) { u16 x, d = 0, i; - _func_enter_; if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } x = rtw_read8(padapter, EE_9346CR); @@ -98,7 +83,6 @@ u16 shift_in_bits(_adapter *padapter) d = d << 1; up_clk(padapter, &x); if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } x = rtw_read8(padapter, EE_9346CR); @@ -110,7 +94,6 @@ u16 shift_in_bits(_adapter *padapter) down_clk(padapter, &x); } out: - _func_exit_; return d; } @@ -118,7 +101,6 @@ u16 shift_in_bits(_adapter *padapter) void standby(_adapter *padapter) { u8 x; - _func_enter_; x = rtw_read8(padapter, EE_9346CR); x &= ~(_EECS | _EESK); @@ -128,14 +110,12 @@ void standby(_adapter *padapter) x |= _EECS; rtw_write8(padapter, EE_9346CR, x); rtw_udelay_os(CLOCK_RATE); - _func_exit_; } u16 wait_eeprom_cmd_done(_adapter *padapter) { u8 x; u16 i, res = _FALSE; - _func_enter_; standby(padapter); for (i = 0; i < 200; i++) { x = rtw_read8(padapter, EE_9346CR); @@ -146,37 +126,31 @@ u16 wait_eeprom_cmd_done(_adapter *padapter) rtw_udelay_os(CLOCK_RATE); } exit: - _func_exit_; return res; } void eeprom_clean(_adapter *padapter) { u16 x; - _func_enter_; if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } x = rtw_read8(padapter, EE_9346CR); if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } x &= ~(_EECS | _EEDI); rtw_write8(padapter, EE_9346CR, (u8)x); if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } up_clk(padapter, &x); if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } down_clk(padapter, &x); out: - _func_exit_; + return; } void eeprom_write16(_adapter *padapter, u16 reg, u16 data) @@ -188,16 +162,13 @@ void eeprom_write16(_adapter *padapter, u16 reg, u16 data) tmp8_new = tmp8_ori & 0xf7; if (tmp8_ori != tmp8_new) { rtw_write8(padapter, 0x102502f1, tmp8_new); - RT_TRACE(_module_rtl871x_mp_ioctl_c_, _drv_err_, ("====write 0x102502f1=====\n")); } tmp8_clk_ori = rtw_read8(padapter, 0x10250003); tmp8_clk_new = tmp8_clk_ori | 0x20; if (tmp8_clk_new != tmp8_clk_ori) { - RT_TRACE(_module_rtl871x_mp_ioctl_c_, _drv_err_, ("====write 0x10250003=====\n")); rtw_write8(padapter, 0x10250003, tmp8_clk_new); } #endif - _func_enter_; x = rtw_read8(padapter, EE_9346CR); @@ -257,7 +228,6 @@ void eeprom_write16(_adapter *padapter, u16 reg, u16 data) rtw_write8(padapter, 0x102502f1, tmp8_ori); #endif - _func_exit_; return; } @@ -272,26 +242,21 @@ u16 eeprom_read16(_adapter *padapter, u16 reg) /* ReadEEprom */ tmp8_new = tmp8_ori & 0xf7; if (tmp8_ori != tmp8_new) { rtw_write8(padapter, 0x102502f1, tmp8_new); - RT_TRACE(_module_rtl871x_mp_ioctl_c_, _drv_err_, ("====write 0x102502f1=====\n")); } tmp8_clk_ori = rtw_read8(padapter, 0x10250003); tmp8_clk_new = tmp8_clk_ori | 0x20; if (tmp8_clk_new != tmp8_clk_ori) { - RT_TRACE(_module_rtl871x_mp_ioctl_c_, _drv_err_, ("====write 0x10250003=====\n")); rtw_write8(padapter, 0x10250003, tmp8_clk_new); } #endif - _func_enter_; if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } /* select EEPROM, reset bits, set _EECS */ x = rtw_read8(padapter, EE_9346CR); if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } @@ -316,7 +281,6 @@ u16 eeprom_read16(_adapter *padapter, u16 reg) /* ReadEEprom */ rtw_write8(padapter, 0x102502f1, tmp8_ori); #endif - _func_exit_; return data; @@ -331,16 +295,13 @@ void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz) u16 x, data16; u32 i; - _func_enter_; if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } /* select EEPROM, reset bits, set _EECS */ x = rtw_read8(padapter, EE_9346CR); if (rtw_is_surprise_removed(padapter)) { - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); goto out; } @@ -362,10 +323,7 @@ void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz) eeprom_clean(padapter); out: - _func_exit_; - - - + return; } @@ -374,7 +332,6 @@ u8 eeprom_read(_adapter *padapter, u32 addr_off, u8 sz, u8 *rbuf) { u8 quotient, remainder, addr_2align_odd; u16 reg, stmp , i = 0, idx = 0; - _func_enter_; reg = (u16)(addr_off >> 1); addr_2align_odd = (u8)(addr_off & 0x1); @@ -399,7 +356,6 @@ u8 eeprom_read(_adapter *padapter, u32 addr_off, u8 sz, u8 *rbuf) stmp = eeprom_read16(padapter, reg); rbuf[idx] = (u8)(stmp & 0xff); } - _func_exit_; return _TRUE; } @@ -408,8 +364,6 @@ u8 eeprom_read(_adapter *padapter, u32 addr_off, u8 sz, u8 *rbuf) VOID read_eeprom_content(_adapter *padapter) { - _func_enter_; - _func_exit_; } diff --git a/core/rtw_ieee80211.c b/core/rtw_ieee80211.c index eec9cab..2899985 100644 --- a/core/rtw_ieee80211.c +++ b/core/rtw_ieee80211.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _IEEE80211_C #ifdef CONFIG_PLATFORM_INTEL_BYT @@ -272,9 +267,7 @@ u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit) { sint tmp, i; u8 *p; - _func_enter_; if (limit < 1) { - _func_exit_; return NULL; } @@ -293,7 +286,6 @@ u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit) if (i >= limit) break; } - _func_exit_; return NULL; } @@ -390,7 +382,6 @@ int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 o void rtw_set_supported_rate(u8 *SupportedRates, uint mode) { - _func_enter_; _rtw_memset(SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX); @@ -416,13 +407,11 @@ void rtw_set_supported_rate(u8 *SupportedRates, uint mode) break; } - _func_exit_; } uint rtw_get_rateset_len(u8 *rateset) { uint i = 0; - _func_enter_; while (1) { if ((rateset[i]) == 0) break; @@ -432,7 +421,6 @@ uint rtw_get_rateset_len(u8 *rateset) i++; } - _func_exit_; return i; } @@ -443,7 +431,6 @@ int rtw_generate_ie(struct registry_priv *pregistrypriv) WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network; u8 *ie = pdev_network->IEs; - _func_enter_; /* timestamp will be inserted by hardware */ sz += 8; @@ -516,7 +503,6 @@ int rtw_generate_ie(struct registry_priv *pregistrypriv) /* pdev_network->IELength = sz; */ /* update IELength */ - _func_exit_; /* return _SUCCESS; */ @@ -648,7 +634,6 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwis left -= WPA_SELECTOR_LEN; } else if (left > 0) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s: ie length mismatch, %u too much", __FUNCTION__, left)); return _FAIL; } @@ -662,8 +647,6 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwis left -= 2; if (count == 0 || left < count * WPA_SELECTOR_LEN) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s: ie count botch (pairwise), " - "count %u left %u", __FUNCTION__, count, left)); return _FAIL; } @@ -675,7 +658,6 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwis } } else if (left == 1) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s: ie too short (for key mgmt)", __FUNCTION__)); return _FAIL; } @@ -683,7 +665,6 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwis if (left >= 6) { pos += 2; if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("%s : there has 802.1x auth\n", __FUNCTION__)); *is_8021x = 1; } } @@ -722,7 +703,6 @@ int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwi left -= RSN_SELECTOR_LEN; } else if (left > 0) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s: ie length mismatch, %u too much", __FUNCTION__, left)); return _FAIL; } @@ -734,8 +714,6 @@ int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwi left -= 2; if (count == 0 || left < count * RSN_SELECTOR_LEN) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s: ie count botch (pairwise), " - "count %u left %u", __FUNCTION__, count, left)); return _FAIL; } @@ -747,7 +725,6 @@ int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwi } } else if (left == 1) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s: ie too short (for key mgmt)", __FUNCTION__)); return _FAIL; } @@ -756,7 +733,6 @@ int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwi if (left >= 6) { pos += 2; if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("%s (): there has 802.1x auth\n", __FUNCTION__)); *is_8021x = 1; } } @@ -775,7 +751,6 @@ int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len) u8 wapi_oui1[4] = {0x0, 0x14, 0x72, 0x01}; u8 wapi_oui2[4] = {0x0, 0x14, 0x72, 0x02}; - _func_enter_; if (wapi_len) *wapi_len = 0; @@ -791,16 +766,9 @@ int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len) /* if(authmode==_WAPI_IE_) */ if (authmode == _WAPI_IE_ && (_rtw_memcmp(&in_ie[cnt + 6], wapi_oui1, 4) == _TRUE || _rtw_memcmp(&in_ie[cnt + 6], wapi_oui2, 4) == _TRUE)) { - if (wapi_ie) { + if (wapi_ie) _rtw_memcpy(wapi_ie, &in_ie[cnt], in_ie[cnt + 1] + 2); - for (i = 0; i < (in_ie[cnt + 1] + 2); i = i + 8) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\n %2x,%2x,%2x,%2x,%2x,%2x,%2x,%2x\n", - wapi_ie[i], wapi_ie[i + 1], wapi_ie[i + 2], wapi_ie[i + 3], wapi_ie[i + 4], - wapi_ie[i + 5], wapi_ie[i + 6], wapi_ie[i + 7])); - } - } - if (wapi_len) *wapi_len = in_ie[cnt + 1] + 2; @@ -813,7 +781,6 @@ int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len) if (wapi_len) len = *wapi_len; - _func_exit_; return len; @@ -826,7 +793,6 @@ int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01}; uint cnt; - _func_enter_; /* Search required WPA or WPA2 IE and copy to sec_ie[ ] */ @@ -838,34 +804,18 @@ int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, authmode = in_ie[cnt]; if ((authmode == _WPA_IE_ID_) && (_rtw_memcmp(&in_ie[cnt + 2], &wpa_oui[0], 4) == _TRUE)) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\n rtw_get_wpa_ie: sec_idx=%d in_ie[cnt+1]+2=%d\n", sec_idx, in_ie[cnt + 1] + 2)); - if (wpa_ie) { + if (wpa_ie) _rtw_memcpy(wpa_ie, &in_ie[cnt], in_ie[cnt + 1] + 2); - for (i = 0; i < (in_ie[cnt + 1] + 2); i = i + 8) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\n %2x,%2x,%2x,%2x,%2x,%2x,%2x,%2x\n", - wpa_ie[i], wpa_ie[i + 1], wpa_ie[i + 2], wpa_ie[i + 3], wpa_ie[i + 4], - wpa_ie[i + 5], wpa_ie[i + 6], wpa_ie[i + 7])); - } - } - *wpa_len = in_ie[cnt + 1] + 2; cnt += in_ie[cnt + 1] + 2; /* get next */ } else { if (authmode == _WPA2_IE_ID_) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\n get_rsn_ie: sec_idx=%d in_ie[cnt+1]+2=%d\n", sec_idx, in_ie[cnt + 1] + 2)); - if (rsn_ie) { + if (rsn_ie) _rtw_memcpy(rsn_ie, &in_ie[cnt], in_ie[cnt + 1] + 2); - for (i = 0; i < (in_ie[cnt + 1] + 2); i = i + 8) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\n %2x,%2x,%2x,%2x,%2x,%2x,%2x,%2x\n", - rsn_ie[i], rsn_ie[i + 1], rsn_ie[i + 2], rsn_ie[i + 3], rsn_ie[i + 4], - rsn_ie[i + 5], rsn_ie[i + 6], rsn_ie[i + 7])); - } - } - *rsn_len = in_ie[cnt + 1] + 2; cnt += in_ie[cnt + 1] + 2; /* get next */ } else { @@ -875,7 +825,6 @@ int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, } - _func_exit_; return *rsn_len + *wpa_len; @@ -1651,8 +1600,8 @@ void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset) void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset) { rtw_ies_get_chbw(bss->IEs + sizeof(NDIS_802_11_FIXED_IEs) - , bss->IELength - sizeof(NDIS_802_11_FIXED_IEs) - , ch, bw, offset); + , bss->IELength - sizeof(NDIS_802_11_FIXED_IEs) + , ch, bw, offset); if (*ch == 0) *ch = bss->Configuration.DSConfig; @@ -2542,14 +2491,11 @@ int rtw_get_cipher_info(struct wlan_network *pnetwork) pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12); if (pbuf && (wpa_ielen > 0)) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_cipher_info: wpa_ielen: %d", wpa_ielen)); if (_SUCCESS == rtw_parse_wpa_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x)) { pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher; pnetwork->BcnInfo.group_cipher = group_cipher; pnetwork->BcnInfo.is_8021x = is8021x; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("%s: pnetwork->pairwise_cipher: %d, is_8021x is %d", - __func__, pnetwork->BcnInfo.pairwise_cipher, pnetwork->BcnInfo.is_8021x)); ret = _SUCCESS; } } else { @@ -2557,15 +2503,10 @@ int rtw_get_cipher_info(struct wlan_network *pnetwork) pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12); if (pbuf && (wpa_ielen > 0)) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("get RSN IE\n")); if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x)) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("get RSN IE OK!!!\n")); pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher; pnetwork->BcnInfo.group_cipher = group_cipher; pnetwork->BcnInfo.is_8021x = is8021x; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("%s: pnetwork->pairwise_cipher: %d," - "pnetwork->group_cipher is %d, is_8021x is %d", __func__, pnetwork->BcnInfo.pairwise_cipher, - pnetwork->BcnInfo.group_cipher, pnetwork->BcnInfo.is_8021x)); ret = _SUCCESS; } } @@ -2593,10 +2534,6 @@ void rtw_get_bcn_info(struct wlan_network *pnetwork) } else pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_OPENSYS; rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, NULL, &rsn_len, NULL, &wpa_len); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_bcn_info: ssid=%s\n", pnetwork->network.Ssid.Ssid)); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_bcn_info: wpa_len=%d rsn_len=%d\n", wpa_len, rsn_len)); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_bcn_info: ssid=%s\n", pnetwork->network.Ssid.Ssid)); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_bcn_info: wpa_len=%d rsn_len=%d\n", wpa_len, rsn_len)); if (rsn_len > 0) pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WPA2; @@ -2606,10 +2543,6 @@ void rtw_get_bcn_info(struct wlan_network *pnetwork) if (bencrypt) pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WEP; } - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_bcn_info: pnetwork->encryp_protocol is %x\n", - pnetwork->BcnInfo.encryp_protocol)); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_bcn_info: pnetwork->encryp_protocol is %x\n", - pnetwork->BcnInfo.encryp_protocol)); rtw_get_cipher_info(pnetwork); /* get bwmode and ch_offset */ @@ -2647,13 +2580,43 @@ u8 rtw_ht_mcsset_to_nss(u8 *supp_mcs_set) return nss; } +u32 rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss) +{ + u8 i; + u32 bitmap = 0; + + for (i = 0; i < nss; i++) + bitmap |= mcs_set[i] << (i * 8); + + RTW_INFO("ht_mcs_set=%02x %02x %02x %02x, nss=%u, bitmap=%08x\n" + , mcs_set[0], mcs_set[1], mcs_set[2], mcs_set[3], nss, bitmap); + + return bitmap; +} + /* show MCS rate, unit: 100Kbps */ u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate) { u16 max_rate = 0; - /*MCS_rate[2] = 3T3R , MCS_rate[1] = 2T2R , MCS_rate[0] = 1T1R*/ - if (MCS_rate[2]) { + if (MCS_rate[3]) { + if (MCS_rate[3] & BIT(7)) + max_rate = (bw_40MHz) ? ((short_GI) ? 6000 : 5400) : ((short_GI) ? 2889 : 2600); + else if (MCS_rate[3] & BIT(6)) + max_rate = (bw_40MHz) ? ((short_GI) ? 5400 : 4860) : ((short_GI) ? 2600 : 2340); + else if (MCS_rate[3] & BIT(5)) + max_rate = (bw_40MHz) ? ((short_GI) ? 4800 : 4320) : ((short_GI) ? 2311 : 2080); + else if (MCS_rate[3] & BIT(4)) + max_rate = (bw_40MHz) ? ((short_GI) ? 3600 : 3240) : ((short_GI) ? 1733 : 1560); + else if (MCS_rate[3] & BIT(3)) + max_rate = (bw_40MHz) ? ((short_GI) ? 2400 : 2160) : ((short_GI) ? 1156 : 1040); + else if (MCS_rate[3] & BIT(2)) + max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780); + else if (MCS_rate[3] & BIT(1)) + max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520); + else if (MCS_rate[3] & BIT(0)) + max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260); + } else if (MCS_rate[2]) { if (MCS_rate[2] & BIT(7)) max_rate = (bw_40MHz) ? ((short_GI) ? 4500 : 4050) : ((short_GI) ? 2167 : 1950); else if (MCS_rate[2] & BIT(6)) @@ -2765,3 +2728,4 @@ const char *action_public_str(u8 action) action = (action >= ACT_PUBLIC_MAX) ? ACT_PUBLIC_MAX : action; return _action_public_str[action]; } + diff --git a/core/rtw_io.c b/core/rtw_io.c index 10f929d..cb8e6b8 100644 --- a/core/rtw_io.c +++ b/core/rtw_io.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* The purpose of rtw_io.c @@ -56,7 +51,7 @@ jackson@realtek.com.tw #error "Shall be Linux or Windows, but not both!\n" #endif -#ifdef CONFIG_SDIO_HCI +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PLATFORM_RTL8197D) #define rtw_le16_to_cpu(val) val #define rtw_le32_to_cpu(val) val #define rtw_cpu_to_le16(val) val @@ -76,11 +71,9 @@ u8 _rtw_read8(_adapter *adapter, u32 addr) struct io_priv *pio_priv = &adapter->iopriv; struct intf_hdl *pintfhdl = &(pio_priv->intf); u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr); - _func_enter_; _read8 = pintfhdl->io_ops._read8; r_val = _read8(pintfhdl, addr); - _func_exit_; return r_val; } @@ -91,11 +84,9 @@ u16 _rtw_read16(_adapter *adapter, u32 addr) struct io_priv *pio_priv = &adapter->iopriv; struct intf_hdl *pintfhdl = &(pio_priv->intf); u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr); - _func_enter_; _read16 = pintfhdl->io_ops._read16; r_val = _read16(pintfhdl, addr); - _func_exit_; return rtw_le16_to_cpu(r_val); } @@ -106,11 +97,9 @@ u32 _rtw_read32(_adapter *adapter, u32 addr) struct io_priv *pio_priv = &adapter->iopriv; struct intf_hdl *pintfhdl = &(pio_priv->intf); u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr); - _func_enter_; _read32 = pintfhdl->io_ops._read32; r_val = _read32(pintfhdl, addr); - _func_exit_; return rtw_le32_to_cpu(r_val); } @@ -122,11 +111,9 @@ int _rtw_write8(_adapter *adapter, u32 addr, u8 val) struct intf_hdl *pintfhdl = &(pio_priv->intf); int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); int ret; - _func_enter_; _write8 = pintfhdl->io_ops._write8; ret = _write8(pintfhdl, addr, val); - _func_exit_; return RTW_STATUS_CODE(ret); } @@ -137,12 +124,10 @@ int _rtw_write16(_adapter *adapter, u32 addr, u16 val) struct intf_hdl *pintfhdl = &(pio_priv->intf); int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); int ret; - _func_enter_; _write16 = pintfhdl->io_ops._write16; val = rtw_cpu_to_le16(val); ret = _write16(pintfhdl, addr, val); - _func_exit_; return RTW_STATUS_CODE(ret); } @@ -153,12 +138,10 @@ int _rtw_write32(_adapter *adapter, u32 addr, u32 val) struct intf_hdl *pintfhdl = &(pio_priv->intf); int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); int ret; - _func_enter_; _write32 = pintfhdl->io_ops._write32; val = rtw_cpu_to_le32(val); ret = _write32(pintfhdl, addr, val); - _func_exit_; return RTW_STATUS_CODE(ret); } @@ -170,11 +153,9 @@ int _rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *pdata) struct intf_hdl *pintfhdl = (struct intf_hdl *)(&(pio_priv->intf)); int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata); int ret; - _func_enter_; _writeN = pintfhdl->io_ops._writeN; ret = _writeN(pintfhdl, addr, length, pdata); - _func_exit_; return RTW_STATUS_CODE(ret); } @@ -187,7 +168,6 @@ u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr) struct intf_hdl *pintfhdl = &(pio_priv->intf); u8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr); - _func_enter_; _sd_f0_read8 = pintfhdl->io_ops._sd_f0_read8; if (_sd_f0_read8) @@ -195,7 +175,6 @@ u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr) else RTW_WARN(FUNC_ADPT_FMT" _sd_f0_read8 callback is NULL\n", FUNC_ADPT_ARG(adapter)); - _func_exit_; return r_val; } @@ -312,11 +291,9 @@ int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val) struct intf_hdl *pintfhdl = &(pio_priv->intf); int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val); int ret; - _func_enter_; _write8_async = pintfhdl->io_ops._write8_async; ret = _write8_async(pintfhdl, addr, val); - _func_exit_; return RTW_STATUS_CODE(ret); } @@ -327,11 +304,9 @@ int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val) struct intf_hdl *pintfhdl = &(pio_priv->intf); int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val); int ret; - _func_enter_; _write16_async = pintfhdl->io_ops._write16_async; val = rtw_cpu_to_le16(val); ret = _write16_async(pintfhdl, addr, val); - _func_exit_; return RTW_STATUS_CODE(ret); } @@ -342,11 +317,9 @@ int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val) struct intf_hdl *pintfhdl = &(pio_priv->intf); int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val); int ret; - _func_enter_; _write32_async = pintfhdl->io_ops._write32_async; val = rtw_cpu_to_le32(val); ret = _write32_async(pintfhdl, addr, val); - _func_exit_; return RTW_STATUS_CODE(ret); } @@ -358,12 +331,8 @@ void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) struct io_priv *pio_priv = &adapter->iopriv; struct intf_hdl *pintfhdl = &(pio_priv->intf); - _func_enter_; if (RTW_CANNOT_RUN(adapter)) { - RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%s) OR bSurpriseRemoved(%s)" - , rtw_is_drv_stopped(adapter) ? "True" : "False" - , rtw_is_surprise_removed(adapter) ? "True" : "False")); return; } @@ -371,7 +340,6 @@ void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) _read_mem(pintfhdl, addr, cnt, pmem); - _func_exit_; } @@ -382,13 +350,11 @@ void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) struct io_priv *pio_priv = &adapter->iopriv; struct intf_hdl *pintfhdl = &(pio_priv->intf); - _func_enter_; _write_mem = pintfhdl->io_ops._write_mem; _write_mem(pintfhdl, addr, cnt, pmem); - _func_exit_; } @@ -399,12 +365,8 @@ void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) struct io_priv *pio_priv = &adapter->iopriv; struct intf_hdl *pintfhdl = &(pio_priv->intf); - _func_enter_; if (RTW_CANNOT_RUN(adapter)) { - RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%s) OR bSurpriseRemoved(%s)" - , rtw_is_drv_stopped(adapter) ? "True" : "False" - , rtw_is_surprise_removed(adapter) ? "True" : "False")); return; } @@ -412,7 +374,6 @@ void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) _read_port(pintfhdl, addr, cnt, pmem); - _func_exit_; } @@ -438,13 +399,11 @@ u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) struct intf_hdl *pintfhdl = &(pio_priv->intf); u32 ret = _SUCCESS; - _func_enter_; _write_port = pintfhdl->io_ops._write_port; ret = _write_port(pintfhdl, addr, cnt, pmem); - _func_exit_; return ret; } diff --git a/core/rtw_ioctl_query.c b/core/rtw_ioctl_query.c index e9423ab..6f7613e 100644 --- a/core/rtw_ioctl_query.c +++ b/core/rtw_ioctl_query.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_IOCTL_QUERY_C_ #include @@ -68,7 +63,6 @@ query_802_11_capability( return _TRUE; } else { *pulOutLen = 0; - RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("_query_802_11_capability(): szAuthEnc size is too large.\n")); return _FALSE; } } @@ -106,13 +100,9 @@ u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIA else pDest[0] = 221; /* WPA(SSN) Information Element */ - RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("\n Adapter->ndisauthtype==Ndis802_11AuthModeWPA)?0xdd:0x30 [%d]", pDest[0])); supp_ie = &psecuritypriv->supplicant_ie[0]; - for (i = 0; i < supp_ie[0]; i++) - RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("IEs [%d] = 0x%x \n\n", i, supp_ie[i])); i = 13; /* 0~11 is fixed information element */ - RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("i= %d tgt_network->network.IELength=%d\n\n", i, (int)psecnetwork->IELength)); while ((i < supp_ie[0]) && (i < 256)) { if ((unsigned char)supp_ie[i] == pDest[0]) { _rtw_memcpy((u8 *)(pDest), @@ -125,7 +115,6 @@ u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIA i = i + supp_ie[i + 1] + 2; if (supp_ie[1 + i] == 0) i = i + 1; - RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("iteration i=%d IEs [%d] = 0x%x \n\n", i, i, supp_ie[i + 1])); } @@ -135,7 +124,6 @@ u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIA } - RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("\n psecnetwork != NULL,fwstate==_FW_UNDER_LINKING\n")); } @@ -159,8 +147,6 @@ u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIA pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength; auth_ie = &psecuritypriv->authenticator_ie[0]; - for (i = 0; i < auth_ie[0]; i++) - RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("IEs [%d] = 0x%x \n\n", i, auth_ie[i])); i = auth_ie[0] - 12; if (i > 0) { @@ -172,11 +158,8 @@ u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIA pAssocInfo->OffsetResponseIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength; - RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("\n tgt_network != NULL,fwstate==_FW_LINKED\n")); } } - RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("\n exit query_802_11_association_information\n")); - _func_exit_; return _TRUE; } diff --git a/core/rtw_ioctl_rtl.c b/core/rtw_ioctl_rtl.c index 0459138..5d9e76b 100644 --- a/core/rtw_ioctl_rtl.c +++ b/core/rtw_ioctl_rtl.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_IOCTL_RTL_C_ #include @@ -154,7 +149,6 @@ NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv *poid_par_priv) PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); _irqL oldirql; - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) { status = NDIS_STATUS_NOT_ACCEPTED; @@ -170,7 +164,6 @@ NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv *poid_par_priv) } else status = NDIS_STATUS_NOT_ACCEPTED; _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; #endif return status; } @@ -183,7 +176,6 @@ NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv *poid_par_priv) PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); _irqL oldirql; - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) { status = NDIS_STATUS_NOT_ACCEPTED; return status; @@ -200,7 +192,6 @@ NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv *poid_par_priv) } else status = NDIS_STATUS_NOT_ACCEPTED; _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; #endif return status; } @@ -436,13 +427,14 @@ NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv *poid_par_priv) { NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); if (poid_par_priv->type_of_oid != QUERY_OID) { status = NDIS_STATUS_NOT_ACCEPTED; return status; } *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - *(u16 *)poid_par_priv->information_buf = padapter->mlmepriv.ChannelPlan ; + *(u16 *)poid_par_priv->information_buf = rfctl->ChannelPlan; return status; } @@ -450,13 +442,14 @@ NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv *poid_par_priv) { NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); if (poid_par_priv->type_of_oid != SET_OID) { status = NDIS_STATUS_NOT_ACCEPTED; return status; } - padapter->mlmepriv.ChannelPlan = *(u16 *)poid_par_priv->information_buf ; + rfctl->ChannelPlan = *(u16 *)poid_par_priv->information_buf; return status; } @@ -585,7 +578,6 @@ NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv *poid_par_priv) ULONG channelnum; - _func_enter_; if (poid_par_priv->type_of_oid != QUERY_OID) { status = NDIS_STATUS_NOT_ACCEPTED; return status; @@ -602,7 +594,6 @@ NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv *poid_par_priv) *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - _func_exit_; @@ -765,7 +756,6 @@ NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); _irqL oldirql; - _func_enter_; /* DEBUG_ERR(("<**********************oid_rt_pro_rf_write_registry_hdl\n")); */ if (poid_par_priv->type_of_oid != SET_OID) { /* QUERY_OID */ status = NDIS_STATUS_NOT_ACCEPTED; @@ -788,7 +778,6 @@ NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv *poid_par_priv) } else status = NDIS_STATUS_INVALID_LENGTH; _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -800,7 +789,6 @@ NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv *poid_par_priv) #if 0 PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); _irqL oldirql; - _func_enter_; /* DEBUG_ERR(("<**********************oid_rt_pro_rf_read_registry_hdl\n")); */ if (poid_par_priv->type_of_oid != SET_OID) { /* QUERY_OID */ @@ -836,7 +824,6 @@ NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv *poid_par_priv) } else status = NDIS_STATUS_INVALID_LENGTH; _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; #endif return status; } @@ -885,7 +872,6 @@ NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv *poid_par_priv) #if 0 /* Rearrange the order to let the UI still shows connection when scan is in progress */ - RT_TRACE(COMP_OID_QUERY, DBG_LOUD, ("===> Query OID_RT_GET_CONNECT_STATE.\n")); if (pMgntInfo->mAssoc) ulInfo = 1; else if (pMgntInfo->mIbss) @@ -895,7 +881,6 @@ NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv *poid_par_priv) else ulInfo = 3; ulInfoLen = sizeof(ULONG); - RT_TRACE(COMP_OID_QUERY, DBG_LOUD, ("<=== Query OID_RT_GET_CONNECT_STATE: %d\n", ulInfo)); #endif return status; diff --git a/core/rtw_ioctl_set.c b/core/rtw_ioctl_set.c index 6761aa4..efd4fcf 100644 --- a/core/rtw_ioctl_set.c +++ b/core/rtw_ioctl_set.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_IOCTL_SET_C_ #include @@ -50,10 +45,8 @@ u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid) u8 i; u8 ret = _TRUE; - _func_enter_; if (ssid->SsidLength > 32) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid length >32\n")); ret = _FALSE; goto exit; } @@ -62,7 +55,6 @@ u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid) for (i = 0; i < ssid->SsidLength; i++) { /* wifi, printable ascii code must be supported */ if (!((ssid->Ssid[i] >= 0x20) && (ssid->Ssid[i] <= 0x7e))) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid has nonprintabl ascii\n")); ret = _FALSE; break; } @@ -71,7 +63,6 @@ u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid) exit: - _func_exit_; return ret; } @@ -86,13 +77,11 @@ u8 rtw_do_join(_adapter *padapter) _queue *queue = &(pmlmepriv->scanned_queue); u8 ret = _SUCCESS; - _func_enter_; _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); phead = get_list_head(queue); plist = get_next(phead); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("\n rtw_do_join: phead = %p; plist = %p \n\n\n", phead, plist)); pmlmepriv->cur_network.join_res = -2; @@ -112,12 +101,10 @@ u8 rtw_do_join(_adapter *padapter) if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE || rtw_to_roam(padapter) > 0 ) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_do_join(): site survey if scanned_queue is empty\n.")); /* submit site_survey_cmd */ ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); if (_SUCCESS != ret) { pmlmepriv->to_join = _FALSE; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("rtw_do_join(): site survey return error\n.")); } } else { pmlmepriv->to_join = _FALSE; @@ -152,14 +139,12 @@ u8 rtw_do_join(_adapter *padapter) rtw_generate_random_ibss(pibss); if (rtw_create_ibss_cmd(padapter, 0) != _SUCCESS) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("***Error=>do_goin: rtw_create_ibss_cmd status FAIL***\n")); ret = _FALSE; goto exit; } pmlmepriv->to_join = _FALSE; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("***Error=> rtw_select_and_join_from_scanned_queue FAIL under STA_Mode***\n ")); } else { /* can't associate ; reset under-linking */ @@ -170,7 +155,6 @@ u8 rtw_do_join(_adapter *padapter) if (_rtw_memcmp(pmlmepriv->cur_network.network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength)) { /* for funk to do roaming */ /* funk will reconnect, but funk will not sitesurvey before reconnect */ - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("for funk to do roaming")); if (pmlmepriv->sitesurveyctrl.traffic_busy == _FALSE) rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); } @@ -187,7 +171,6 @@ u8 rtw_do_join(_adapter *padapter) ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); if (_SUCCESS != ret) { pmlmepriv->to_join = _FALSE; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("do_join(): site survey return error\n.")); } } else { ret = _FAIL; @@ -201,7 +184,6 @@ u8 rtw_do_join(_adapter *padapter) exit: - _func_exit_; return ret; } @@ -210,15 +192,11 @@ u8 rtw_pnp_set_power_wakeup(_adapter *padapter) { u8 res = _SUCCESS; - _func_enter_; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("==>rtw_pnp_set_power_wakeup!!!\n")); res = rtw_setstandby_cmd(padapter, 0); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("<==rtw_pnp_set_power_wakeup!!!\n")); - _func_exit_; return res; } @@ -227,29 +205,20 @@ u8 rtw_pnp_set_power_sleep(_adapter *padapter) { u8 res = _SUCCESS; - _func_enter_; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("==>rtw_pnp_set_power_sleep!!!\n")); /* DbgPrint("+rtw_pnp_set_power_sleep\n"); */ res = rtw_setstandby_cmd(padapter, 1); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("<==rtw_pnp_set_power_sleep!!!\n")); - _func_exit_; return res; } u8 rtw_set_802_11_reload_defaults(_adapter *padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults) { - _func_enter_; - switch (reloadDefaults) { - case Ndis802_11ReloadWEPKeys: - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("SetInfo OID_802_11_RELOAD_DEFAULTS : Ndis802_11ReloadWEPKeys\n")); - break; - } + /* SecClearAllKeys(Adapter); */ /* 8711 CAM was not for En/Decrypt only */ @@ -258,7 +227,6 @@ u8 rtw_set_802_11_reload_defaults(_adapter *padapter, NDIS_802_11_RELOAD_DEFAULT /* TO DO... */ - _func_exit_; return _TRUE; } @@ -267,7 +235,6 @@ u8 set_802_11_test(_adapter *padapter, NDIS_802_11_TEST *test) { u8 ret = _TRUE; - _func_enter_; switch (test->Type) { case 1: @@ -285,7 +252,6 @@ u8 set_802_11_test(_adapter *padapter, NDIS_802_11_TEST *test) break; } - _func_exit_; return ret; } @@ -306,7 +272,6 @@ u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _func_enter_; RTW_PRINT("set bssid:%pM\n", bssid); @@ -326,17 +291,13 @@ u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid) goto release_mlme_lock; if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_bssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n")); if (_rtw_memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN) == _TRUE) { if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE) goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */ } else { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("Set BSSID not the same bssid\n")); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_bssid="MAC_FMT"\n", MAC_ARG(bssid))); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("cur_bssid="MAC_FMT"\n", MAC_ARG(pmlmepriv->cur_network.network.MacAddress))); - rtw_disassoc_cmd(padapter, 0, _TRUE); + rtw_disassoc_cmd(padapter, 0, 0); if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) rtw_indicate_disconnect(padapter, 0, _FALSE); @@ -369,10 +330,7 @@ u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid) _exit_critical_bh(&pmlmepriv->lock, &irqL); exit: - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, - ("rtw_set_802_11_bssid: status=%d\n", status)); - _func_exit_; return status; } @@ -386,14 +344,11 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_network *pnetwork = &pmlmepriv->cur_network; - _func_enter_; RTW_PRINT("set ssid [%s] fw_state=0x%08x\n", ssid->Ssid, get_fwstate(pmlmepriv)); if (!rtw_is_hw_init_completed(padapter)) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, - ("set_ssid: hw_init_completed==_FALSE=>exit!!!\n")); status = _FAIL; goto exit; } @@ -407,19 +362,14 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) goto release_mlme_lock; if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, - ("set_ssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n")); if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) && (_rtw_memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength) == _TRUE)) { if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, - ("Set SSID is the same ssid, fw_state=0x%08x\n", - get_fwstate(pmlmepriv))); if (rtw_is_same_ibss(padapter, pnetwork) == _FALSE) { /* if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again */ - rtw_disassoc_cmd(padapter, 0, _TRUE); + rtw_disassoc_cmd(padapter, 0, 0); if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) rtw_indicate_disconnect(padapter, 0, _FALSE); @@ -439,11 +389,8 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 1); #endif } else { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("Set SSID not the same ssid\n")); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_ssid=[%s] len=0x%x\n", ssid->Ssid, (unsigned int)ssid->SsidLength)); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("assoc_ssid=[%s] len=0x%x\n", pmlmepriv->assoc_ssid.Ssid, (unsigned int)pmlmepriv->assoc_ssid.SsidLength)); - rtw_disassoc_cmd(padapter, 0, _TRUE); + rtw_disassoc_cmd(padapter, 0, 0); if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) rtw_indicate_disconnect(padapter, 0, _FALSE); @@ -480,10 +427,7 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) _exit_critical_bh(&pmlmepriv->lock, &irqL); exit: - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, - ("-rtw_set_802_11_ssid: status=%d\n", status)); - _func_exit_; return status; @@ -498,7 +442,6 @@ u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid) bool ssid_valid = _TRUE; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _func_enter_; if (!ssid || rtw_validate_ssid(ssid) == _FALSE) ssid_valid = _FALSE; @@ -514,8 +457,6 @@ u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid) } if (!rtw_is_hw_init_completed(padapter)) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, - ("set_ssid: hw_init_completed==_FALSE=>exit!!!\n")); status = _FAIL; goto exit; } @@ -557,7 +498,6 @@ u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid) exit: - _func_exit_; return status; } @@ -569,21 +509,17 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_network *cur_network = &pmlmepriv->cur_network; NDIS_802_11_NETWORK_INFRASTRUCTURE *pold_state = &(cur_network->network.InfrastructureMode); + u8 ap2sta_mode = _FALSE; - _func_enter_; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_notice_, - ("+rtw_set_802_11_infrastructure_mode: old=%d new=%d fw_state=0x%08x\n", - *pold_state, networktype, get_fwstate(pmlmepriv))); if (*pold_state != networktype) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, (" change mode!")); /* RTW_INFO("change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); */ if (*pold_state == Ndis802_11APMode) { /* change to other mode from Ndis802_11APMode */ cur_network->join_res = -1; - + ap2sta_mode = _TRUE; #ifdef CONFIG_NATIVEAP_MLME stop_ap_mode(padapter); #endif @@ -592,7 +528,7 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, _enter_critical_bh(&pmlmepriv->lock, &irqL); if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || (*pold_state == Ndis802_11IBSS)) - rtw_disassoc_cmd(padapter, 0, _TRUE); + rtw_disassoc_cmd(padapter, 0, 0); if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) @@ -615,6 +551,9 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, case Ndis802_11Infrastructure: set_fwstate(pmlmepriv, WIFI_STATION_STATE); + + if (ap2sta_mode) + rtw_init_bcmc_stainfo(padapter); break; case Ndis802_11APMode: @@ -636,13 +575,10 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, /* SecClearAllKeys(adapter); */ - /* RT_TRACE(COMP_OID_SET, DBG_LOUD, ("set_infrastructure: fw_state:%x after changing mode\n", */ - /* get_fwstate(pmlmepriv) )); */ _exit_critical_bh(&pmlmepriv->lock, &irqL); } - _func_exit_; return _TRUE; } @@ -653,14 +589,12 @@ u8 rtw_set_802_11_disassociate(_adapter *padapter) _irqL irqL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _func_enter_; _enter_critical_bh(&pmlmepriv->lock, &irqL); if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("MgntActrtw_set_802_11_disassociate: rtw_indicate_disconnect\n")); - rtw_disassoc_cmd(padapter, 0, _TRUE); + rtw_disassoc_cmd(padapter, 0, 0); rtw_indicate_disconnect(padapter, 0, _FALSE); /* modify for CONFIG_IEEE80211W, none 11w can use it */ rtw_free_assoc_resources_cmd(padapter); @@ -670,7 +604,6 @@ u8 rtw_set_802_11_disassociate(_adapter *padapter) _exit_critical_bh(&pmlmepriv->lock, &irqL); - _func_exit_; return _TRUE; } @@ -696,9 +629,7 @@ u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, i struct mlme_priv *pmlmepriv = &padapter->mlmepriv; u8 res = _TRUE; - _func_enter_; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("+%s, fw_state=%x\n", __func__, get_fwstate(pmlmepriv))); if (padapter == NULL) { res = _FALSE; @@ -706,20 +637,15 @@ u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, i } if (!rtw_is_hw_init_completed(padapter)) { res = _FALSE; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n===%s:hw_init_completed==_FALSE===\n", __func__)); goto exit; } if ((check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) || (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)) { /* Scan or linking is in progress, do nothing. */ - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("%s fail since fw_state = %x\n", __func__, get_fwstate(pmlmepriv))); res = _TRUE; - if (check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING)) == _TRUE) - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n###_FW_UNDER_SURVEY | _FW_UNDER_LINKING\n\n")); - else - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n###pmlmepriv->sitesurveyctrl.traffic_busy == _TRUE\n\n")); + } else { if (rtw_is_scan_deny(padapter)) { RTW_INFO(FUNC_ADPT_FMT": scan deny\n", FUNC_ADPT_ARG(padapter)); @@ -735,7 +661,6 @@ u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, i } exit: - _func_exit_; return res; } @@ -746,13 +671,10 @@ u8 rtw_set_802_11_authentication_mode(_adapter *padapter, NDIS_802_11_AUTHENTICA int res; u8 ret; - _func_enter_; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_802_11_auth.mode(): mode=%x\n", authmode)); psecuritypriv->ndisauthtype = authmode; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_authentication_mode:psecuritypriv->ndisauthtype=%d", psecuritypriv->ndisauthtype)); if (psecuritypriv->ndisauthtype > 3) psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; @@ -769,7 +691,6 @@ u8 rtw_set_802_11_authentication_mode(_adapter *padapter, NDIS_802_11_AUTHENTICA else ret = _FALSE; - _func_exit_; return ret; } @@ -783,14 +704,12 @@ u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep) struct security_priv *psecuritypriv = &(padapter->securitypriv); u8 ret = _SUCCESS; - _func_enter_; bdefaultkey = (wep->KeyIndex & 0x40000000) > 0 ? _FALSE : _TRUE; /* for ??? */ btransmitkey = (wep->KeyIndex & 0x80000000) > 0 ? _TRUE : _FALSE; /* for ??? */ keyid = wep->KeyIndex & 0x3fffffff; if (keyid >= 4) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("MgntActrtw_set_802_11_add_wep:keyid>4=>fail\n")); ret = _FALSE; goto exit; } @@ -798,19 +717,15 @@ u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep) switch (wep->KeyLength) { case 5: psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("MgntActrtw_set_802_11_add_wep:wep->KeyLength=5\n")); break; case 13: psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("MgntActrtw_set_802_11_add_wep:wep->KeyLength=13\n")); break; default: psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("MgntActrtw_set_802_11_add_wep:wep->KeyLength!=5 or 13\n")); break; } - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_add_wep:befor memcpy, wep->KeyLength=0x%x wep->KeyIndex=0x%x keyid =%x\n", wep->KeyLength, wep->KeyIndex, keyid)); _rtw_memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]), &(wep->KeyMaterial), wep->KeyLength); @@ -818,12 +733,6 @@ u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep) psecuritypriv->dot11PrivacyKeyIndex = keyid; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_add_wep:security key material : %x %x %x %x %x %x %x %x %x %x %x %x %x\n", - psecuritypriv->dot11DefKey[keyid].skey[0], psecuritypriv->dot11DefKey[keyid].skey[1], psecuritypriv->dot11DefKey[keyid].skey[2], - psecuritypriv->dot11DefKey[keyid].skey[3], psecuritypriv->dot11DefKey[keyid].skey[4], psecuritypriv->dot11DefKey[keyid].skey[5], - psecuritypriv->dot11DefKey[keyid].skey[6], psecuritypriv->dot11DefKey[keyid].skey[7], psecuritypriv->dot11DefKey[keyid].skey[8], - psecuritypriv->dot11DefKey[keyid].skey[9], psecuritypriv->dot11DefKey[keyid].skey[10], psecuritypriv->dot11DefKey[keyid].skey[11], - psecuritypriv->dot11DefKey[keyid].skey[12])); res = rtw_set_key(padapter, psecuritypriv, keyid, 1, _TRUE); @@ -831,7 +740,6 @@ u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep) ret = _FALSE; exit: - _func_exit_; return ret; @@ -842,7 +750,6 @@ u8 rtw_set_802_11_remove_wep(_adapter *padapter, u32 keyindex) u8 ret = _SUCCESS; - _func_enter_; if (keyindex >= 0x80000000 || padapter == NULL) { @@ -870,7 +777,6 @@ u8 rtw_set_802_11_remove_wep(_adapter *padapter, u32 keyindex) exit: - _func_exit_; return ret; @@ -886,15 +792,11 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) u8 bgrouptkey = _FALSE;/* can be remove later */ u8 ret = _SUCCESS; - _func_enter_; if (((key->KeyIndex & 0x80000000) == 0) && ((key->KeyIndex & 0x40000000) > 0)) { /* It is invalid to clear bit 31 and set bit 30. If the miniport driver encounters this combination, */ /* it must fail the request and return NDIS_STATUS_INVALID_DATA. */ - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_add_key: ((key->KeyIndex & 0x80000000) == 0)[=%d] ", (int)(key->KeyIndex & 0x80000000) == 0)); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_add_key:((key->KeyIndex & 0x40000000) > 0)[=%d]" , (int)(key->KeyIndex & 0x40000000) > 0)); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_add_key: key->KeyIndex=%d\n" , (int)key->KeyIndex)); ret = _FAIL; goto exit; } @@ -902,31 +804,23 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) if (key->KeyIndex & 0x40000000) { /* Pairwise key */ - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY: +++++ Pairwise key +++++\n")); pbssid = get_bssid(&padapter->mlmepriv); stainfo = rtw_get_stainfo(&padapter->stapriv, pbssid); if ((stainfo != NULL) && (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY:( stainfo!=NULL)&&(Adapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X)\n")); encryptionalgo = stainfo->dot118021XPrivacy; } else { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY: stainfo==NULL)||(Adapter->securitypriv.dot11AuthAlgrthm!=dot11AuthAlgrthm_8021X)\n")); encryptionalgo = padapter->securitypriv.dot11PrivacyAlgrthm; } - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("rtw_set_802_11_add_key: (encryptionalgo ==%d)!\n", encryptionalgo)); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("rtw_set_802_11_add_key: (Adapter->securitypriv.dot11PrivacyAlgrthm ==%d)!\n", padapter->securitypriv.dot11PrivacyAlgrthm)); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("rtw_set_802_11_add_key: (Adapter->securitypriv.dot11AuthAlgrthm ==%d)!\n", padapter->securitypriv.dot11AuthAlgrthm)); - if ((stainfo != NULL)) - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("rtw_set_802_11_add_key: (stainfo->dot118021XPrivacy ==%d)!\n", stainfo->dot118021XPrivacy)); + if (key->KeyIndex & 0x000000FF) { /* The key index is specified in the lower 8 bits by values of zero to 255. */ /* The key index should be set to zero for a Pairwise key, and the driver should fail with */ /* NDIS_STATUS_INVALID_DATA if the lower 8 bits is not zero */ - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, (" key->KeyIndex & 0x000000FF.\n")); ret = _FAIL; goto exit; } @@ -934,7 +828,6 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) /* check BSSID */ if (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _TRUE) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("MacAddr_isBcst(key->BSSID)\n")); ret = _FALSE; goto exit; } @@ -942,7 +835,6 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) /* Check key length for TKIP. */ /* if(encryptionAlgorithm == RT_ENC_TKIP_ENCRYPTION && key->KeyLength != 32) */ if ((encryptionalgo == _TKIP_) && (key->KeyLength != 32)) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("TKIP KeyLength:0x%x != 32\n", key->KeyLength)); ret = _FAIL; goto exit; @@ -961,7 +853,6 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) /* Check key length for WEP. For NDTEST, 2005.01.27, by rcnjko. -> modify checking condition*/ if (((encryptionalgo == _WEP40_) && (key->KeyLength != 5)) || ((encryptionalgo == _WEP104_) && (key->KeyLength != 13))) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("WEP KeyLength:0x%x != 5 or 13\n", key->KeyLength)); ret = _FAIL; goto exit; } @@ -969,55 +860,35 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) bgroup = _FALSE; /* Check the pairwise key. Added by Annie, 2005-07-06. */ - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("------------------------------------------\n")); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("[Pairwise Key set]\n")); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("------------------------------------------\n")); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("key index: 0x%8x(0x%8x)\n", key->KeyIndex, (key->KeyIndex & 0x3))); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("key Length: %d\n", key->KeyLength)); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("------------------------------------------\n")); } else { /* Group key - KeyIndex(BIT30==0) */ - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY: +++++ Group key +++++\n")); /* when add wep key through add key and didn't assigned encryption type before */ if ((padapter->securitypriv.ndisauthtype <= 3) && (padapter->securitypriv.dot118021XGrpPrivacy == 0)) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("keylen=%d( Adapter->securitypriv.dot11PrivacyAlgrthm=%x )padapter->securitypriv.dot118021XGrpPrivacy(%x)\n", - key->KeyLength, padapter->securitypriv.dot11PrivacyAlgrthm, padapter->securitypriv.dot118021XGrpPrivacy)); switch (key->KeyLength) { case 5: padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n", - padapter->securitypriv.dot11PrivacyAlgrthm, key->KeyLength)); break; case 13: padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n", - padapter->securitypriv.dot11PrivacyAlgrthm, key->KeyLength)); break; default: padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n", - padapter->securitypriv.dot11PrivacyAlgrthm, key->KeyLength)); break; } encryptionalgo = padapter->securitypriv.dot11PrivacyAlgrthm; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, (" Adapter->securitypriv.dot11PrivacyAlgrthm=%x\n", padapter->securitypriv.dot11PrivacyAlgrthm)); } else { encryptionalgo = padapter->securitypriv.dot118021XGrpPrivacy; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, - ("( Adapter->securitypriv.dot11PrivacyAlgrthm=%x )encryptionalgo(%x)=padapter->securitypriv.dot118021XGrpPrivacy(%x)keylen=%d\n", - padapter->securitypriv.dot11PrivacyAlgrthm, encryptionalgo, padapter->securitypriv.dot118021XGrpPrivacy, key->KeyLength)); } if ((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE) == _TRUE) && (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _FALSE)) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, (" IBSS but BSSID is not Broadcast Address.\n")); ret = _FAIL; goto exit; } @@ -1025,7 +896,6 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) /* Check key length for TKIP */ if ((encryptionalgo == _TKIP_) && (key->KeyLength != 32)) { - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, (" TKIP GTK KeyLength:%u != 32\n", key->KeyLength)); ret = _FAIL; goto exit; @@ -1033,7 +903,6 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) /* Check key length for AES */ /* For NDTEST, we allow keylen=32 in this case. 2005.01.27, by rcnjko. */ - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("<=== SetInfo, OID_802_11_ADD_KEY: AES GTK KeyLength:%u != 16 or 32\n", key->KeyLength)); ret = _FAIL; goto exit; } @@ -1041,7 +910,6 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) /* Change the key length for EAPPkt9x.vxd. Added by Annie, 2005-11-03. */ if ((encryptionalgo == _AES_) && (key->KeyLength == 32)) { key->KeyLength = 16; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("AES key length changed: %u\n", key->KeyLength)); } if (key->KeyIndex & 0x8000000) /* error ??? 0x8000_0000 */ @@ -1052,12 +920,6 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) bgroup = _TRUE; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("------------------------------------------\n")); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("[Group Key set]\n")); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("------------------------------------------\n")) ; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("key index: 0x%8x(0x%8x)\n", key->KeyIndex, (key->KeyIndex & 0x3))); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("key Length: %d\n", key->KeyLength)) ; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("------------------------------------------\n")); } @@ -1068,14 +930,12 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) u32 len = FIELD_OFFSET(NDIS_802_11_KEY, KeyMaterial) + key->KeyLength; NDIS_802_11_WEP *wep = &padapter->securitypriv.ndiswep; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY: +++++ WEP key +++++\n")); wep->Length = len; keyindex = key->KeyIndex & 0x7fffffff; wep->KeyIndex = keyindex ; wep->KeyLength = key->KeyLength; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY:Before memcpy\n")); _rtw_memcpy(wep->KeyMaterial, key->KeyMaterial, key->KeyLength); _rtw_memcpy(&(padapter->securitypriv.dot11DefKey[keyindex].skey[0]), key->KeyMaterial, key->KeyLength); @@ -1091,7 +951,6 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) if (key->KeyIndex & 0x20000000) { /* SetRSC */ - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY: +++++ SetRSC+++++\n")); if (bgroup == _TRUE) { NDIS_802_11_KEY_RSC keysrc = key->KeyRSC & 0x00FFFFFFFFFFFFULL; _rtw_memcpy(&padapter->securitypriv.dot11Grprxpn, &keysrc, 8); @@ -1123,31 +982,11 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8); _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:rx mic :0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[0], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[1], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[2], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[3], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[4], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[5], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[6], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[7])); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:set Group mic key!!!!!!!!\n")); } else { _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8); _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:rx mic :0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[0], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[1], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[2], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[3], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[4], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[5], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[6], - padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[7])); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:set Group mic key!!!!!!!!\n")); } @@ -1160,7 +999,6 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) padapter->securitypriv.bcheck_grpkey = _FALSE; - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("reset group key")); res = rtw_set_key(padapter, &padapter->securitypriv, key->KeyIndex, 1, _TRUE); @@ -1183,10 +1021,6 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) if (encryptionalgo == _TKIP_) { padapter->securitypriv.busetkipkey = _FALSE; - /* _set_timer(&padapter->securitypriv.tkip_timer, 50); */ - - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n ==========_set_timer\n")); - /* if TKIP, save the Receive/Transmit MIC key in KeyMaterial[128-255] */ if ((key->KeyIndex & 0x10000000)) { _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 16, 8); @@ -1207,15 +1041,12 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) #if 0 if (bgrouptkey) { /* never go to here */ res = rtw_setstakey_cmd(padapter, stainfo, GROUP_KEY, _TRUE); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(group)\n")); } else { res = rtw_setstakey_cmd(padapter, stainfo, UNICAST_KEY, _TRUE); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(unicast)\n")); } #else res = rtw_setstakey_cmd(padapter, stainfo, UNICAST_KEY, _TRUE); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(unicast)\n")); #endif if (res == _FALSE) @@ -1227,7 +1058,6 @@ u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) exit: - _func_exit_; return ret; } @@ -1242,7 +1072,6 @@ u8 rtw_set_802_11_remove_key(_adapter *padapter, NDIS_802_11_REMOVE_KEY *key) u8 keyIndex = (u8)key->KeyIndex & 0x03; u8 ret = _SUCCESS; - _func_enter_; if ((key->KeyIndex & 0xbffffffc) > 0) { ret = _FAIL; @@ -1279,7 +1108,6 @@ u8 rtw_set_802_11_remove_key(_adapter *padapter, NDIS_802_11_REMOVE_KEY *key) exit: - _func_exit_; return _TRUE; @@ -1318,21 +1146,19 @@ u16 rtw_get_cur_max_rate(_adapter *adapter) if (psta == NULL) return 0; - short_GI = query_ra_short_GI(psta); + short_GI = query_ra_short_GI(psta, psta->bw_mode); #ifdef CONFIG_80211N_HT - if (IsSupportedHT(psta->wireless_mode)) { + if (is_supported_ht(psta->wireless_mode)) { rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); - - max_rate = rtw_mcs_rate( - rf_type, - ((psta->bw_mode == CHANNEL_WIDTH_40) ? 1 : 0), - short_GI, - psta->htpriv.ht_cap.supp_mcs_set - ); + max_rate = rtw_mcs_rate(rf_type + , (psta->bw_mode == CHANNEL_WIDTH_40) ? 1 : 0 + , short_GI + , psta->htpriv.ht_cap.supp_mcs_set + ); } #ifdef CONFIG_80211AC_VHT - else if (IsSupportedVHT(psta->wireless_mode)) + else if (is_supported_vht(psta->wireless_mode)) max_rate = ((rtw_vht_mcs_to_data_rate(psta->bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10; #endif /* CONFIG_80211AC_VHT */ else diff --git a/core/rtw_iol.c b/core/rtw_iol.c index 42d0b6b..aafac3f 100644 --- a/core/rtw_iol.c +++ b/core/rtw_iol.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include diff --git a/core/rtw_mem.c b/core/rtw_mem.c index d82fa7f..d9f5652 100644 --- a/core/rtw_mem.c +++ b/core/rtw_mem.c @@ -1,31 +1,49 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #include #include MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Realtek Wireless Lan Driver 802.11 AC"); -MODULE_AUTHOR("Brandon Bailey "); +MODULE_DESCRIPTION("Realtek Wireless Lan Driver"); +MODULE_AUTHOR("Realtek Semiconductor Corp."); MODULE_VERSION("DRIVERVERSION"); struct sk_buff_head rtk_skb_mem_q; struct u8 *rtk_buf_mem[NR_RECVBUFF]; -struct u8 *rtw_get_buf_premem(int index) { +struct u8 *rtw_get_buf_premem(int index) +{ printk("%s, rtk_buf_mem index : %d\n", __func__, index); return rtk_buf_mem[index]; } -u16 rtw_rtkm_get_buff_size(void) { +u16 rtw_rtkm_get_buff_size(void) +{ return MAX_RTKM_RECVBUF_SZ; } EXPORT_SYMBOL(rtw_rtkm_get_buff_size); -u8 rtw_rtkm_get_nr_recv_skb(void) { +u8 rtw_rtkm_get_nr_recv_skb(void) +{ return MAX_RTKM_NR_PREALLOC_RECV_SKB; } EXPORT_SYMBOL(rtw_rtkm_get_nr_recv_skb); -struct sk_buff *rtw_alloc_skb_premem(u16 in_size) { +struct sk_buff *rtw_alloc_skb_premem(u16 in_size) +{ struct sk_buff *skb = NULL; if (in_size > MAX_RTKM_RECVBUF_SZ) { @@ -42,7 +60,8 @@ struct sk_buff *rtw_alloc_skb_premem(u16 in_size) { } EXPORT_SYMBOL(rtw_alloc_skb_premem); -int rtw_free_skb_premem(struct sk_buff *pskb) { +int rtw_free_skb_premem(struct sk_buff *pskb) +{ if (!pskb) return -1; @@ -57,7 +76,8 @@ int rtw_free_skb_premem(struct sk_buff *pskb) { } EXPORT_SYMBOL(rtw_free_skb_premem); -static int __init rtw_mem_init(void) { +static int __init rtw_mem_init(void) +{ int i; SIZE_PTR tmpaddr = 0; SIZE_PTR alignment = 0; @@ -94,7 +114,8 @@ static int __init rtw_mem_init(void) { } -static void __exit rtw_mem_exit(void) { +static void __exit rtw_mem_exit(void) +{ if (skb_queue_len(&rtk_skb_mem_q)) printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q)); diff --git a/core/rtw_mi.c b/core/rtw_mi.c index 2532848..c4e1487 100644 --- a/core/rtw_mi.c +++ b/core/rtw_mi.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2015 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_MI_C_ #include @@ -110,33 +105,14 @@ inline int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw return _rtw_mi_get_ch_setting_union(adapter, ch, bw, offset, 0); } -void _rtw_mi_status(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num - , u8 *ap_num, u8 *ld_ap_num, u8 *uw_num, bool include_self) +/* For now, not return union_ch/bw/offset */ +void _rtw_mi_status(_adapter *adapter, struct mi_state *mstate, bool include_self) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); _adapter *iface; - struct mlme_ext_priv *mlmeext; - int i; - u8 sta_num_ret = 0; - u8 ld_sta_num_ret = 0; - u8 lg_sta_num_ret = 0; - u8 ap_num_ret = 0; - u8 ld_ap_num_ret = 0; - u8 uw_num_ret = 0; - - if (sta_num) - *sta_num = 0; - if (ld_sta_num) - *ld_sta_num = 0; - if (lg_sta_num) - *lg_sta_num = 0; - if (ap_num) - *ap_num = 0; - if (ld_ap_num) - *ld_ap_num = 0; - if (uw_num) - *uw_num = 0; + + _rtw_memset(mstate, 0, sizeof(struct mi_state)); for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -144,72 +120,75 @@ void _rtw_mi_status(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_n if (include_self == _FALSE && iface == adapter) continue; - /*mlmeext = &iface->mlmeextpriv; - - if (mlmeext_msr(mlmeext) == WIFI_FW_STATION_STATE) {*/ - if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE)) { - sta_num_ret++; + if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) { + MSTATE_STA_NUM(mstate)++; if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) - ld_sta_num_ret++; + MSTATE_STA_LD_NUM(mstate)++; + if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING) == _TRUE) - lg_sta_num_ret++; - } + MSTATE_STA_LG_NUM(mstate)++; - /*if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE*/ - if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) - && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE - ) { - ap_num_ret++; + } else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE + && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE + ) { + MSTATE_AP_NUM(mstate)++; if (iface->stapriv.asoc_sta_count > 2) - ld_ap_num_ret++; + MSTATE_AP_LD_NUM(mstate)++; + + } else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE + && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE + ) { + MSTATE_ADHOC_NUM(mstate)++; + if (iface->stapriv.asoc_sta_count > 2) + MSTATE_ADHOC_LD_NUM(mstate)++; } if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_WPS) == _TRUE) - uw_num_ret++; + MSTATE_WPS_NUM(mstate)++; - } +#ifdef CONFIG_IOCTL_CFG80211 + if (rtw_cfg80211_get_is_mgmt_tx(iface)) + MSTATE_MGMT_TX_NUM(mstate)++; + #ifdef CONFIG_P2P + if (rtw_cfg80211_get_is_roch(iface) == _TRUE) + MSTATE_ROCH_NUM(mstate)++; + #endif +#endif /* CONFIG_IOCTL_CFG80211 */ - if (sta_num) - *sta_num = sta_num_ret; - if (ld_sta_num) - *ld_sta_num = ld_sta_num_ret; - if (lg_sta_num) - *lg_sta_num = lg_sta_num_ret; - if (ap_num) - *ap_num = ap_num_ret; - if (ld_ap_num) - *ld_ap_num = ld_ap_num_ret; - if (uw_num) - *uw_num = uw_num_ret; + } } -inline void rtw_mi_status(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num - , u8 *ap_num, u8 *ld_ap_num, u8 *uw_num) +inline void rtw_mi_status(_adapter *adapter, struct mi_state *mstate) { - return _rtw_mi_status(adapter, sta_num, ld_sta_num, lg_sta_num, ap_num, ld_ap_num, uw_num, 1); + return _rtw_mi_status(adapter, mstate, 1); } -inline void rtw_mi_status_no_self(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num - , u8 *ap_num, u8 *ld_ap_num, u8 *uw_num) +inline void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate) { - return _rtw_mi_status(adapter, sta_num, ld_sta_num, lg_sta_num, ap_num, ld_ap_num, uw_num, 0); + return _rtw_mi_status(adapter, mstate, 0); } void dump_mi_status(void *sel, struct dvobj_priv *dvobj) { RTW_PRINT_SEL(sel, "== dvobj-iface_state ==\n"); - RTW_PRINT_SEL(sel, "sta_num:%d\n", dvobj->iface_state.sta_num); - RTW_PRINT_SEL(sel, "linking_sta_num:%d\n", dvobj->iface_state.lg_sta_num); - RTW_PRINT_SEL(sel, "linked_sta_num:%d\n", dvobj->iface_state.ld_sta_num); - RTW_PRINT_SEL(sel, "ap_num:%d\n", dvobj->iface_state.ap_num); - RTW_PRINT_SEL(sel, "linked_ap_num:%d\n", dvobj->iface_state.ld_ap_num); - RTW_PRINT_SEL(sel, "adhoc_num:%d\n", dvobj->iface_state.adhoc_num); - RTW_PRINT_SEL(sel, "linked_adhoc_num:%d\n", dvobj->iface_state.ld_adhoc_num); + RTW_PRINT_SEL(sel, "sta_num:%d\n", DEV_STA_NUM(dvobj)); + RTW_PRINT_SEL(sel, "linking_sta_num:%d\n", DEV_STA_LG_NUM(dvobj)); + RTW_PRINT_SEL(sel, "linked_sta_num:%d\n", DEV_STA_LD_NUM(dvobj)); + RTW_PRINT_SEL(sel, "ap_num:%d\n", DEV_AP_NUM(dvobj)); + RTW_PRINT_SEL(sel, "linked_ap_num:%d\n", DEV_AP_LD_NUM(dvobj)); + RTW_PRINT_SEL(sel, "adhoc_num:%d\n", DEV_ADHOC_NUM(dvobj)); + RTW_PRINT_SEL(sel, "linked_adhoc_num:%d\n", DEV_ADHOC_LD_NUM(dvobj)); #ifdef CONFIG_P2P RTW_PRINT_SEL(sel, "p2p_device_num:%d\n", rtw_mi_stay_in_p2p_mode(dvobj->padapters[IFACE_ID0])); #endif - RTW_PRINT_SEL(sel, "under_wps_num:%d\n", dvobj->iface_state.uwps_num); - RTW_PRINT_SEL(sel, "union_ch:%d\n", dvobj->iface_state.union_ch); - RTW_PRINT_SEL(sel, "union_bw:%d\n", dvobj->iface_state.union_bw); - RTW_PRINT_SEL(sel, "union_offset:%d\n", dvobj->iface_state.union_offset); +#if defined(CONFIG_IOCTL_CFG80211) + #if defined(CONFIG_P2P) + RTW_PRINT_SEL(sel, "roch_num:%d\n", DEV_ROCH_NUM(dvobj)); + #endif + RTW_PRINT_SEL(sel, "mgmt_tx_num:%d\n", DEV_MGMT_TX_NUM(dvobj)); +#endif + RTW_PRINT_SEL(sel, "under_wps_num:%d\n", DEV_WPS_NUM(dvobj)); + RTW_PRINT_SEL(sel, "union_ch:%d\n", DEV_U_CH(dvobj)); + RTW_PRINT_SEL(sel, "union_bw:%d\n", DEV_U_BW(dvobj)); + RTW_PRINT_SEL(sel, "union_offset:%d\n", DEV_U_OFFSET(dvobj)); RTW_PRINT_SEL(sel, "================\n\n"); } @@ -224,51 +203,22 @@ inline void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state) _adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv); struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct mi_state *iface_state = &dvobj->iface_state; + struct mi_state tmp_mstate; u8 i; u8 u_ch, u_offset, u_bw; _adapter *iface; - struct mlme_ext_priv *mlmeext; - if ((state == WIFI_MONITOR_STATE) || /* (state == WIFI_OP_CH_SWITCHING) || */ - (state == WIFI_ADHOC_MASTER_STATE) || (state == WIFI_ADHOC_STATE) || - (state == WIFI_SITE_MONITOR) || (state == 0xFFFFFFFF) || - (state == WIFI_UNDER_WPS) - ) + if (state == WIFI_MONITOR_STATE + || state == WIFI_SITE_MONITOR + || state == 0xFFFFFFFF + ) return; if (0) RTW_INFO("%s => will change or clean state to 0x%08x\n", __func__, state); - _rtw_memset(iface_state, 0, sizeof(struct mi_state)); - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - mlmeext = &iface->mlmeextpriv; - - if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) { - iface_state->sta_num++; - if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) - iface_state->ld_sta_num++; - - if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING) == _TRUE) - iface_state->lg_sta_num++; - } else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE - && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE - ) { - iface_state->ap_num++; - if (iface->stapriv.asoc_sta_count > 2) - iface_state->ld_ap_num++; - } else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE - && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE - ) { - iface_state->adhoc_num++; - if (iface->stapriv.asoc_sta_count > 2) - iface_state->ld_adhoc_num++; - } - - if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_WPS) == _TRUE) - iface_state->uwps_num++; - - } + rtw_mi_status(adapter, &tmp_mstate); + _rtw_memcpy(iface_state, &tmp_mstate, sizeof(struct mi_state)); if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) rtw_mi_update_union_chan_inf(adapter , u_ch, u_offset , u_bw); @@ -297,46 +247,46 @@ u8 rtw_mi_check_status(_adapter *adapter, u8 type) switch (type) { case MI_LINKED: - if (iface_state->ld_sta_num || iface_state->ap_num || iface_state->adhoc_num) /*check_fwstate(&iface->mlmepriv, _FW_LINKED)*/ + if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_NUM(iface_state) || MSTATE_ADHOC_NUM(iface_state)) /*check_fwstate(&iface->mlmepriv, _FW_LINKED)*/ ret = _TRUE; break; case MI_ASSOC: - if (iface_state->ld_sta_num || iface_state->ld_ap_num || iface_state->ld_adhoc_num) + if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_LD_NUM(iface_state) || MSTATE_ADHOC_LD_NUM(iface_state)) ret = _TRUE; break; case MI_UNDER_WPS: - if (iface_state->uwps_num) + if (MSTATE_WPS_NUM(iface_state)) ret = _TRUE; break; case MI_AP_MODE: - if (iface_state->ap_num) + if (MSTATE_AP_NUM(iface_state)) ret = _TRUE; break; case MI_AP_ASSOC: - if (iface_state->ld_ap_num) + if (MSTATE_AP_LD_NUM(iface_state)) ret = _TRUE; break; case MI_ADHOC: - if (iface_state->adhoc_num) + if (MSTATE_ADHOC_NUM(iface_state)) ret = _TRUE; break; case MI_ADHOC_ASSOC: - if (iface_state->ld_adhoc_num) + if (MSTATE_ADHOC_LD_NUM(iface_state)) ret = _TRUE; break; case MI_STA_NOLINK: /* this is misleading, but not used now */ - if (iface_state->sta_num && (!(iface_state->ld_sta_num || iface_state->lg_sta_num))) + if (MSTATE_STA_NUM(iface_state) && (!(MSTATE_STA_LD_NUM(iface_state) || MSTATE_STA_LG_NUM(iface_state)))) ret = _TRUE; break; case MI_STA_LINKED: - if (iface_state->ld_sta_num) + if (MSTATE_STA_LD_NUM(iface_state)) ret = _TRUE; break; case MI_STA_LINKING: - if (iface_state->lg_sta_num) + if (MSTATE_STA_LG_NUM(iface_state)) ret = _TRUE; break; @@ -346,170 +296,35 @@ u8 rtw_mi_check_status(_adapter *adapter, u8 type) return ret; } -#if 0 -inline void rtw_mi_update_fwstate(struct mlme_priv *pmlmepriv, sint state, u8 bset) -{ - _adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv); - - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct mi_state *iface_state = &dvobj->iface_state; - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - - if (!(state & (_FW_LINKED | _FW_UNDER_LINKING | WIFI_UNDER_WPS))) - return; - - if (mlmeext_msr(mlmeext) == WIFI_FW_STATION_STATE) { - /*ATOMIC_INC(&(iface_state->sta_num_ret));*/ - - if (state & _FW_LINKED) - (bset) ? ATOMIC_INC(&(iface_state->ld_sta_num_ret)) - : ATOMIC_DEC(&(iface_state->ld_sta_num_ret)); - - if (state & _FW_UNDER_LINKING) - (bset) ? ATOMIC_INC(&(iface_state->lg_sta_num_ret)) - : ATOMIC_DEC(&(iface_state->lg_sta_num_ret)); - } - - if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE - && check_fwstate(&adapter->mlmepriv, _FW_LINKED) == _TRUE - ) { - /*ATOMIC_INC(&(iface_state->ap_num_ret));*/ - if (adapter->stapriv.asoc_sta_count > 2) - ld_ap_num_ret++; - } - - if (state & WIFI_UNDER_WPS) - (bset) ? ATOMIC_INC(&(iface_state->uw_num_ret)) - : ATOMIC_DEC(&(iface_state->uw_num_ret)); - - _rtw_mi_status(adapter, &iface_state->sta_num, &iface_state->ld_sta_num, &iface_state->lg_sta_num - , &iface_state->ap_num, &iface_state->ld_ap_num, &iface_state->uwps_num, 1); -} -#endif - -#ifdef CONFIG_MP_INCLUDED -u8 rtw_mi_mp_mode_check(_adapter *padapter) +/* +* return value : 0 is failed or have not interface meet condition +* return value : !0 is success or interface numbers which meet condition +* return value of ops_func must be _TRUE or _FALSE +*/ +static u8 _rtw_mi_process(_adapter *padapter, bool exclude_self, + void *data, u8(*ops_func)(_adapter *padapter, void *data)) { -#ifdef CONFIG_CONCURRENT_MODE int i; + _adapter *iface; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - _adapter *iface = NULL; - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if ((iface) && (iface->registrypriv.mp_mode == 1)) { - RTW_INFO(ADPT_FMT "-MP mode enable\n", ADPT_ARG(iface)); - return _TRUE; - } - } -#else - if (padapter->registrypriv.mp_mode == 1) - return _TRUE; -#endif - return _FALSE; -} -#endif - -#ifdef CONFIG_CONCURRENT_MODE -u8 rtw_mi_buddy_under_survey(_adapter *padapter) -{ - int i; u8 ret = 0; - _adapter *iface = NULL; - _irqL irqL; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - -#ifdef CONFIG_IOCTL_CFG80211 - struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); -#endif - - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - - struct mlme_priv *buddy_mlmepriv; - struct rtw_wdev_priv *buddy_wdev_priv; for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if ((iface) && rtw_is_adapter_up(iface)) { - if (iface == padapter) + if ((exclude_self) && (iface == padapter)) continue; - buddy_mlmepriv = &iface->mlmepriv; - if (check_fwstate(buddy_mlmepriv, _FW_UNDER_SURVEY)) { - ret = UNDER_SURVEY_T1; - -#ifdef CONFIG_IOCTL_CFG80211 - buddy_wdev_priv = adapter_wdev_data(iface); - _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); - _enter_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL); - if (buddy_wdev_priv->scan_request) { - pmlmepriv->scanning_via_buddy_intf = _TRUE; - _enter_critical_bh(&pmlmepriv->lock, &irqL); - set_fwstate(pmlmepriv, _FW_UNDER_SURVEY); - _exit_critical_bh(&pmlmepriv->lock, &irqL); - ret = UNDER_SURVEY_T2; - } - _exit_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL); - _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); -#endif - - RTW_INFO(ADPT_FMT"_FW_UNDER_SURVEY\n", ADPT_ARG(iface)); - return ret; - } + if (ops_func) + if (_TRUE == ops_func(iface, data)) + ret++; } } return ret; } -void rtw_mi_buddy_indicate_scan_done(_adapter *padapter, bool bscan_aborted) -{ -#if defined(CONFIG_IOCTL_CFG80211) - int i; - u8 ret = 0; - _adapter *iface = NULL; - _irqL irqL; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct mlme_priv *mlmepriv; - struct rtw_wdev_priv *wdev_priv; - bool indicate_buddy_scan = _FALSE; - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if ((iface) && rtw_is_adapter_up(iface)) { - - if (iface == padapter) - continue; - - mlmepriv = &(iface->mlmepriv); - wdev_priv = adapter_wdev_data(iface); - - _enter_critical_bh(&wdev_priv->scan_req_lock, &irqL); - if (wdev_priv->scan_request && mlmepriv->scanning_via_buddy_intf == _TRUE) { - mlmepriv->scanning_via_buddy_intf = _FALSE; - clr_fwstate(mlmepriv, _FW_UNDER_SURVEY); - indicate_buddy_scan = _TRUE; - } - _exit_critical_bh(&wdev_priv->scan_req_lock, &irqL); - - if (indicate_buddy_scan == _TRUE) { - rtw_cfg80211_surveydone_event_callback(iface); - rtw_indicate_scan_done(iface, bscan_aborted); - } - - } - } -#endif - -} -#endif - -/* -* return value : 0 is failed or have not interface meet condition -* return value : !0 is success or interface numbers which meet condition -* return value of ops_func must be _TRUE or _FALSE -*/ -static u8 _rtw_mi_process(_adapter *padapter, bool exclude_self, +static u8 _rtw_mi_process_without_schk(_adapter *padapter, bool exclude_self, void *data, u8(*ops_func)(_adapter *padapter, void *data)) { int i; @@ -520,18 +335,18 @@ static u8 _rtw_mi_process(_adapter *padapter, bool exclude_self, for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; - if ((iface) && rtw_is_adapter_up(iface)) { - + if (iface) { if ((exclude_self) && (iface == padapter)) continue; if (ops_func) - if (_TRUE == ops_func(iface, data)) + if (ops_func(iface, data) == _TRUE) ret++; } } return ret; } + static u8 _rtw_mi_netif_stop_queue(_adapter *padapter, void *data) { bool carrier_off = *(bool *)data; @@ -663,11 +478,11 @@ static u8 _rtw_mi_reset_drv_sw(_adapter *adapter, void *data) } void rtw_mi_reset_drv_sw(_adapter *adapter) { - _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_reset_drv_sw); + _rtw_mi_process_without_schk(adapter, _FALSE, NULL, _rtw_mi_reset_drv_sw); } void rtw_mi_buddy_reset_drv_sw(_adapter *adapter) { - _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_reset_drv_sw); + _rtw_mi_process_without_schk(adapter, _TRUE, NULL, _rtw_mi_reset_drv_sw); } static u8 _rtw_mi_intf_start(_adapter *adapter, void *data) @@ -746,7 +561,7 @@ void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms) _rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_set_scan_deny); } -#endif +#endif /*CONFIG_SET_SCAN_DENY_TIMER*/ struct nulldata_param { unsigned char *da; @@ -987,20 +802,6 @@ static u8 _rtw_mi_traffic_statistics(_adapter *padapter , void *data) } u8 rtw_mi_traffic_statistics(_adapter *padapter) { - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - - /*_rtw_memset(&pdvobjpriv->traffic_stat, 0, sizeof(struct rtw_traffic_statistics));*/ - - /* Tx bytes reset*/ - pdvobjpriv->traffic_stat.tx_bytes = 0; - pdvobjpriv->traffic_stat.tx_pkts = 0; - pdvobjpriv->traffic_stat.tx_drop = 0; - - /* Rx bytes reset*/ - pdvobjpriv->traffic_stat.rx_bytes = 0; - pdvobjpriv->traffic_stat.rx_pkts = 0; - pdvobjpriv->traffic_stat.rx_drop = 0; - return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_traffic_statistics); } @@ -1085,7 +886,7 @@ void rtw_mi_buddy_adapter_reset(_adapter *padapter) static u8 _rtw_mi_dynamic_check_timer_handlder(_adapter *adapter, void *data) { - rtw_dynamic_check_timer_handlder(adapter); + rtw_iface_dynamic_check_timer_handlder(adapter); return _TRUE; } u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter) @@ -1113,7 +914,7 @@ u8 rtw_mi_buddy_dev_unload(_adapter *padapter) static u8 _rtw_mi_dynamic_chk_wk_hdl(_adapter *adapter, void *data) { - dynamic_chk_wk_hdl(adapter); + rtw_iface_dynamic_chk_wk_hdl(adapter); return _TRUE; } u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter) @@ -1415,17 +1216,18 @@ void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvf for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; - if ((iface) && rtw_is_adapter_up(iface)) { - if (iface == padapter) - continue; - pcloneframe = rtw_alloc_recvframe(pfree_recv_queue); - if (pcloneframe) { - ret = _rtw_mi_buddy_clone_bcmc_packet(iface, precvframe, pphy_status, pcloneframe); - if (_SUCCESS != ret) { - if (ret == -1) - rtw_free_recvframe(pcloneframe, pfree_recv_queue); - /*RTW_INFO(ADPT_FMT"-clone BC/MC frame failed\n", ADPT_ARG(iface));*/ - } + if (!iface || iface == padapter) + continue; + if (rtw_is_adapter_up(iface) == _FALSE || iface->registered == 0) + continue; + + pcloneframe = rtw_alloc_recvframe(pfree_recv_queue); + if (pcloneframe) { + ret = _rtw_mi_buddy_clone_bcmc_packet(iface, precvframe, pphy_status, pcloneframe); + if (_SUCCESS != ret) { + if (ret == -1) + rtw_free_recvframe(pcloneframe, pfree_recv_queue); + /*RTW_INFO(ADPT_FMT"-clone BC/MC frame failed\n", ADPT_ARG(iface));*/ } } } @@ -1478,3 +1280,28 @@ void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b) } #endif } + +#ifdef CONFIG_AP_MODE +static u8 _rtw_mi_ap_acdata_control(_adapter *padapter, void *data) +{ + u8 power_mode = *(u8 *)data; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + rtw_ap_acdata_control(padapter, power_mode); + return _TRUE; +} + +void rtw_mi_ap_acdata_control(_adapter *padapter, u8 power_mode) +{ + u8 in_data = power_mode; + + _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_ap_acdata_control); +} +void rtw_mi_buddy_ap_acdata_control(_adapter *padapter, u8 power_mode) +{ + u8 in_data = power_mode; + + _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_ap_acdata_control); +} +#endif /*CONFIG_AP_MODE*/ diff --git a/core/rtw_mlme.c b/core/rtw_mlme.c index 04e0d9a..74363ca 100644 --- a/core/rtw_mlme.c +++ b/core/rtw_mlme.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_MLME_C_ #include @@ -25,6 +20,27 @@ extern void indicate_wx_scan_complete_event(_adapter *padapter); extern u8 rtw_do_join(_adapter *padapter); +void rtw_init_mlme_timer(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + rtw_init_timer(&(pmlmepriv->assoc_timer), padapter, rtw_join_timeout_handler, padapter); + rtw_init_timer(&(pmlmepriv->scan_to_timer), padapter, rtw_scan_timeout_handler, padapter); + +#ifdef CONFIG_DFS_MASTER + rtw_init_timer(&(pmlmepriv->dfs_master_timer), padapter, rtw_dfs_master_timer_hdl, padapter); +#endif + +#ifdef CONFIG_SET_SCAN_DENY_TIMER + rtw_init_timer(&(pmlmepriv->set_scan_deny_timer), padapter, rtw_set_scan_deny_timer_hdl, padapter); +#endif + +#ifdef RTK_DMP_PLATFORM + _init_workitem(&(pmlmepriv->Linkup_workitem), Linkup_workitem_callback, padapter); + _init_workitem(&(pmlmepriv->Linkdown_workitem), Linkdown_workitem_callback, padapter); +#endif +} + sint _rtw_init_mlme_priv(_adapter *padapter) { sint i; @@ -33,7 +49,6 @@ sint _rtw_init_mlme_priv(_adapter *padapter) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; sint res = _SUCCESS; - _func_enter_; /* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */ /* _rtw_memset((u8 *)pmlmepriv, 0, sizeof(struct mlme_priv)); */ @@ -89,12 +104,14 @@ sint _rtw_init_mlme_priv(_adapter *padapter) rtw_clear_scan_deny(padapter); #ifdef CONFIG_ARP_KEEP_ALIVE pmlmepriv->bGetGateway = 0; + pmlmepriv->GetGatewayTryCnt = 0; #endif #ifdef CONFIG_LAYER2_ROAMING #define RTW_ROAM_SCAN_RESULT_EXP_MS (5*1000) #define RTW_ROAM_RSSI_DIFF_TH 10 #define RTW_ROAM_SCAN_INTERVAL_MS (10*1000) +#define RTW_ROAM_RSSI_THRESHOLD 70 pmlmepriv->roam_flags = 0 | RTW_ROAM_ON_EXPIRED @@ -109,13 +126,20 @@ sint _rtw_init_mlme_priv(_adapter *padapter) pmlmepriv->roam_scanr_exp_ms = RTW_ROAM_SCAN_RESULT_EXP_MS; pmlmepriv->roam_rssi_diff_th = RTW_ROAM_RSSI_DIFF_TH; pmlmepriv->roam_scan_int_ms = RTW_ROAM_SCAN_INTERVAL_MS; + pmlmepriv->roam_rssi_threshold = RTW_ROAM_RSSI_THRESHOLD; #endif /* CONFIG_LAYER2_ROAMING */ +#ifdef CONFIG_RTW_80211R + memset(&pmlmepriv->ftpriv, 0, sizeof(ft_priv)); + pmlmepriv->ftpriv.ft_flags = 0 + | RTW_FT_STA_SUPPORTED + | RTW_FT_STA_OVER_DS_SUPPORTED + ; +#endif rtw_init_mlme_timer(padapter); exit: - _func_exit_; return res; } @@ -164,6 +188,9 @@ void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv) rtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_resp_ie, &pmlmepriv->wfd_assoc_resp_ie_len); #endif +#ifdef CONFIG_RTW_80211R + rtw_free_mlme_ie_data(&pmlmepriv->auth_rsp, &pmlmepriv->auth_rsp_len); +#endif } #if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) @@ -265,7 +292,6 @@ int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_ void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv) { - _func_enter_; if (NULL == pmlmepriv) { rtw_warn_on(1); goto exit; @@ -279,14 +305,13 @@ void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv) rtw_vmfree(pmlmepriv->free_bss_buf, MAX_BSS_CNT * sizeof(struct wlan_network)); } exit: - _func_exit_; + return; } sint _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) { _irqL irqL; - _func_enter_; if (pnetwork == NULL) goto exit; @@ -299,7 +324,6 @@ sint _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) exit: - _func_exit_; return _SUCCESS; } @@ -311,7 +335,6 @@ struct wlan_network *_rtw_dequeue_network(_queue *queue) struct wlan_network *pnetwork; -_func_enter_; _enter_critical_bh(&queue->lock, &irqL); @@ -328,7 +351,6 @@ _func_enter_; _exit_critical_bh(&queue->lock, &irqL); -_func_exit_; return pnetwork; } @@ -341,7 +363,6 @@ struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue _queue *free_queue = &pmlmepriv->free_bss_pool; _list *plist = NULL; - _func_enter_; _enter_critical_bh(&free_queue->lock, &irqL); @@ -355,7 +376,6 @@ struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue rtw_list_delete(&pnetwork->list); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("_rtw_alloc_network: ptr=%p\n", plist)); pnetwork->network_type = 0; pnetwork->fixed = _FALSE; pnetwork->last_scanned = rtw_get_current_time(); @@ -367,7 +387,6 @@ struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue exit: _exit_critical_bh(&free_queue->lock, &irqL); - _func_exit_; return pnetwork; } @@ -379,7 +398,6 @@ void _rtw_free_network(struct mlme_priv *pmlmepriv , struct wlan_network *pnetwo _irqL irqL; _queue *free_queue = &(pmlmepriv->free_bss_pool); - _func_enter_; if (pnetwork == NULL) goto exit; @@ -411,9 +429,7 @@ void _rtw_free_network(struct mlme_priv *pmlmepriv , struct wlan_network *pnetwo _exit_critical_bh(&free_queue->lock, &irqL); exit: - - _func_exit_; - + return; } void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork) @@ -421,7 +437,6 @@ void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network * _queue *free_queue = &(pmlmepriv->free_bss_pool); - _func_enter_; if (pnetwork == NULL) goto exit; @@ -440,9 +455,7 @@ void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network * /* _exit_critical(&free_queue->lock, &irqL); */ exit: - - _func_exit_; - + return; } @@ -459,7 +472,6 @@ struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr) struct wlan_network *pnetwork = NULL; u8 zero_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; - _func_enter_; if (_rtw_memcmp(zero_addr, addr, ETH_ALEN)) { pnetwork = NULL; @@ -487,7 +499,6 @@ struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr) exit: - _func_exit_; return pnetwork; @@ -502,7 +513,6 @@ void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; _queue *scanned_queue = &pmlmepriv->scanned_queue; - _func_enter_; _enter_critical_bh(&scanned_queue->lock, &irqL); @@ -522,7 +532,6 @@ void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall) _exit_critical_bh(&scanned_queue->lock, &irqL); - _func_exit_; } @@ -533,18 +542,13 @@ sint rtw_if_up(_adapter *padapter) { sint res; - _func_enter_; if (RTW_CANNOT_RUN(padapter) || (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_if_up:bDriverStopped(%s) OR bSurpriseRemoved(%s)" - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False")); res = _FALSE; } else res = _TRUE; - _func_exit_; return res; } @@ -566,11 +570,9 @@ u8 *rtw_get_capability_from_ie(u8 *ie) u16 rtw_get_capability(WLAN_BSSID_EX *bss) { u16 val; - _func_enter_; _rtw_memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->IEs), 2); - _func_exit_; return le16_to_cpu(val); } @@ -588,27 +590,20 @@ u8 *rtw_get_beacon_interval_from_ie(u8 *ie) int rtw_init_mlme_priv(_adapter *padapter) /* (struct mlme_priv *pmlmepriv) */ { int res; - _func_enter_; res = _rtw_init_mlme_priv(padapter);/* (pmlmepriv); */ - _func_exit_; return res; } void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv) { - _func_enter_; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("rtw_free_mlme_priv\n")); _rtw_free_mlme_priv(pmlmepriv); - _func_exit_; } int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork); int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) { int res; - _func_enter_; res = _rtw_enqueue_network(queue, pnetwork); - _func_exit_; return res; } @@ -616,9 +611,7 @@ int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) static struct wlan_network *rtw_dequeue_network(_queue *queue) { struct wlan_network *pnetwork; -_func_enter_; pnetwork = _rtw_dequeue_network(queue); -_func_exit_; return pnetwork; } */ @@ -627,39 +620,29 @@ struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv); struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue *free_queue) */ { struct wlan_network *pnetwork; - _func_enter_; pnetwork = _rtw_alloc_network(pmlmepriv); - _func_exit_; return pnetwork; } void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall); void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall)/* (struct wlan_network *pnetwork, _queue *free_queue) */ { - _func_enter_; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("rtw_free_network==> ssid = %s \n\n" , pnetwork->network.Ssid.Ssid)); _rtw_free_network(pmlmepriv, pnetwork, is_freeall); - _func_exit_; } void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork); void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork) { - _func_enter_; - /* RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_network==> ssid = %s \n\n" , pnetwork->network.Ssid.Ssid)); */ _rtw_free_network_nolock(&(padapter->mlmepriv), pnetwork); #ifdef CONFIG_IOCTL_CFG80211 rtw_cfg80211_unlink_bss(padapter, pnetwork); #endif /* CONFIG_IOCTL_CFG80211 */ - _func_exit_; } void rtw_free_network_queue(_adapter *dev, u8 isfreeall) { - _func_enter_; _rtw_free_network_queue(dev, isfreeall); - _func_exit_; } /* @@ -694,8 +677,6 @@ int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork) inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b) { - /* RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("(%s,%d)(%s,%d)\n", */ - /* a->Ssid.Ssid,a->Ssid.SsidLength,b->Ssid.Ssid,b->Ssid.SsidLength)); */ return (a->Ssid.SsidLength == b->Ssid.SsidLength) && _rtw_memcmp(a->Ssid.Ssid, b->Ssid.Ssid, a->Ssid.SsidLength) == _TRUE; } @@ -704,7 +685,6 @@ int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature) { u16 s_cap, d_cap; - _func_enter_; if (rtw_bug_check(dst, src, &s_cap, &d_cap) == _FALSE) return _FALSE; @@ -716,7 +696,6 @@ int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature) s_cap = le16_to_cpu(s_cap); d_cap = le16_to_cpu(d_cap); - _func_exit_; #ifdef CONFIG_P2P if ((feature == 1) && /* 1: P2P supported */ @@ -782,7 +761,6 @@ struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue) struct wlan_network *pwlan = NULL; struct wlan_network *oldest = NULL; - _func_enter_; phead = get_list_head(scanned_queue); plist = get_next(phead); @@ -801,7 +779,6 @@ struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue) plist = get_next(plist); } - _func_exit_; return oldest; } @@ -821,7 +798,6 @@ void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, u8 sq_final; long rssi_final; - _func_enter_; #ifdef CONFIG_ANTENNA_DIVERSITY rtw_hal_antdiv_rssi_compared(padapter, dst, src); /* this will update src.Rssi, need consider again */ @@ -912,14 +888,12 @@ void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, #endif - _func_exit_; } static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) { struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - _func_enter_; rtw_bug_check(&(pmlmepriv->cur_network.network), &(pmlmepriv->cur_network.network), @@ -927,7 +901,6 @@ static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) &(pmlmepriv->cur_network.network)); if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork, 0))) { - /* RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"Same Network\n"); */ /* if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength) */ { @@ -937,7 +910,6 @@ static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) } } - _func_exit_; } @@ -964,12 +936,16 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) int target_find = 0; u8 feature = 0; - _func_enter_; _enter_critical_bh(&queue->lock, &irqL); phead = get_list_head(queue); plist = get_next(phead); +#if 0 + RTW_INFO("%s => ssid:%s , rssi:%ld , ss:%d\n", + __func__, target->Ssid.Ssid, target->Rssi, target->PhyInfo.SignalStrength); +#endif + #ifdef CONFIG_P2P if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) feature = 1; /* p2p enable */ @@ -999,10 +975,13 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) if (rtw_roam_flags(adapter)) { /* TODO: don't select netowrk in the same ess as oldest if it's new enough*/ } - +#ifdef CONFIG_RSSI_PRIORITY + if ((oldest == NULL) || (pnetwork->network.PhyInfo.SignalStrength < oldest->network.PhyInfo.SignalStrength)) + oldest = pnetwork; +#else if (oldest == NULL || time_after(oldest->last_scanned, pnetwork->last_scanned)) oldest = pnetwork; - +#endif plist = get_next(plist); } @@ -1017,9 +996,16 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) /* list_del_init(&oldest->list); */ pnetwork = oldest; if (pnetwork == NULL) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n\n\nsomething wrong here\n\n\n")); goto exit; } +#ifdef CONFIG_RSSI_PRIORITY + RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue (rssi:%ld , ss:%d)\n", + __func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Rssi, pnetwork->network.PhyInfo.SignalStrength); +#else + RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue\n", + __func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress)); +#endif + #ifdef CONFIG_ANTENNA_DIVERSITY rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL); #endif @@ -1042,7 +1028,6 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) pnetwork = rtw_alloc_network(pmlmepriv); /* will update scan_time */ if (pnetwork == NULL) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n\n\nsomething wrong here\n\n\n")); goto exit; } @@ -1089,7 +1074,6 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) exit: _exit_critical_bh(&queue->lock, &irqL); - _func_exit_; } void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork); @@ -1099,7 +1083,6 @@ void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) struct mlme_priv *pmlmepriv = &(((_adapter *)adapter)->mlmepriv); /* _queue *queue = &(pmlmepriv->scanned_queue); */ - _func_enter_; /* _enter_critical_bh(&queue->lock, &irqL); */ @@ -1117,7 +1100,6 @@ void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) /* _exit_critical_bh(&queue->lock, &irqL); */ - _func_exit_; } /* select the desired network based on the capability of the (i)bss. @@ -1183,9 +1165,6 @@ int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork) void rtw_atimdone_event_callback(_adapter *adapter , u8 *pbuf) { - _func_enter_; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("receive atimdone_evet\n")); - _func_exit_; return; } @@ -1197,11 +1176,9 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) WLAN_BSSID_EX *pnetwork; struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - _func_enter_; pnetwork = (WLAN_BSSID_EX *)pbuf; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_survey_event_callback, ssid=%s\n", pnetwork->Ssid.Ssid)); #ifdef CONFIG_RTL8712 /* endian_convert */ @@ -1224,7 +1201,6 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) len = get_WLAN_BSSID_EX_sz(pnetwork); if (len > (sizeof(WLAN_BSSID_EX))) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n ****rtw_survey_event_callback: return a wrong bss ***\n")); return; } @@ -1233,7 +1209,6 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) /* update IBSS_network 's timestamp */ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) { - /* RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"rtw_survey_event_callback : WIFI_ADHOC_MASTER_STATE \n\n"); */ if (_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN)) { struct wlan_network *ibss_wlan = NULL; _irqL irqL; @@ -1261,7 +1236,6 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) _exit_critical_bh(&pmlmepriv->lock, &irqL); - _func_exit_; return; } @@ -1269,14 +1243,15 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) { _irqL irqL; - u8 timer_cancelled; struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); +#ifdef CONFIG_RTW_80211R + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; +#endif #ifdef CONFIG_MLME_EXT mlmeext_surveydone_event_callback(adapter); #endif - _func_enter_; _enter_critical_bh(&pmlmepriv->lock, &irqL); if (pmlmepriv->wps_probe_req_ie) { @@ -1286,7 +1261,6 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) pmlmepriv->wps_probe_req_ie = NULL; } - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_surveydone_event_callback: fw_state:%x\n\n", get_fwstate(pmlmepriv))); if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _FALSE) { RTW_INFO(FUNC_ADPT_FMT" fw_state:0x%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); @@ -1296,7 +1270,7 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); _exit_critical_bh(&pmlmepriv->lock, &irqL); - _cancel_timer(&pmlmepriv->scan_to_timer, &timer_cancelled); + _cancel_timer_ex(&pmlmepriv->scan_to_timer); _enter_critical_bh(&pmlmepriv->lock, &irqL); @@ -1318,7 +1292,6 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) /* pmlmepriv->fw_state ^= _FW_UNDER_SURVEY; */ /* because don't set assoc_timer */ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("switching to adhoc master\n")); _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); @@ -1330,7 +1303,7 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS) - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("Error=>rtw_create_ibss_cmd status FAIL\n")); + RTW_ERR("rtw_create_ibss_cmd FAIL\n"); pmlmepriv->to_join = _FALSE; } @@ -1374,8 +1347,17 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED)) { if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) { +#ifdef CONFIG_RTW_80211R + if (rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED)) { + start_clnt_ft_action(adapter, (u8 *)pmlmepriv->roam_network->network.MacAddress); + } else { + /*wait a little time to retrieve packets buffered in the current ap while scan*/ + _set_timer(&pmlmeext->ft_roam_timer, 30); + } +#else receive_disconnect(adapter, pmlmepriv->cur_network.network.MacAddress , WLAN_REASON_ACTIVE_ROAM, _FALSE); +#endif } } } @@ -1410,11 +1392,11 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) #endif /* CONFIG_IOCTL_CFG80211 */ rtw_indicate_scan_done(adapter, _FALSE); -#ifdef CONFIG_CONCURRENT_MODE - rtw_mi_buddy_indicate_scan_done(adapter, _FALSE);/*scanning_via_buddy_intf*/ + +#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211) + rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _FALSE); #endif - _func_exit_; } void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf) @@ -1434,9 +1416,7 @@ static void free_scanqueue(struct mlme_priv *pmlmepriv) _queue *scan_queue = &pmlmepriv->scanned_queue; _list *plist, *phead, *ptemp; - _func_enter_; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+free_scanqueue\n")); _enter_critical_bh(&scan_queue->lock, &irqL0); _enter_critical_bh(&free_queue->lock, &irqL); @@ -1454,7 +1434,6 @@ static void free_scanqueue(struct mlme_priv *pmlmepriv) _exit_critical_bh(&free_queue->lock, &irqL); _exit_critical_bh(&scan_queue->lock, &irqL0); - _func_exit_; } void rtw_reset_rx_info(struct debug_priv *pdbgpriv) @@ -1483,9 +1462,7 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) #ifdef CONFIG_TDLS struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; #endif /* CONFIG_TDLS */ - _func_enter_; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+rtw_free_assoc_resources\n")); RTW_INFO("%s-"ADPT_FMT" tgt_network MacAddress=" MAC_FMT"ssid=%s\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid); @@ -1561,7 +1538,6 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) rtw_reset_rx_info(pdbgpriv); - _func_exit_; } @@ -1573,9 +1549,7 @@ void rtw_indicate_connect(_adapter *padapter) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - _func_enter_; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_indicate_connect\n")); pmlmepriv->to_join = _FALSE; @@ -1608,9 +1582,7 @@ void rtw_indicate_connect(_adapter *padapter) if (!check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE)) rtw_mi_set_scan_deny(padapter, 3000); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("-rtw_indicate_connect: fw_state=0x%08x\n", get_fwstate(pmlmepriv))); - _func_exit_; } @@ -1628,9 +1600,7 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate u8 *wps_ie = NULL; uint wpsie_len = 0; - _func_enter_; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_indicate_disconnect\n")); _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS); @@ -1692,7 +1662,6 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, cur_network->MacAddress, ETH_ALEN, 1); #endif /*CONFIG_BEAMFORMING*/ - _func_exit_; } inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted) @@ -1710,7 +1679,7 @@ inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted) pwrpriv = adapter_to_pwrctl(padapter); rtw_set_ips_deny(padapter, 0); #ifdef CONFIG_IPS_CHECK_IN_WD - _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 1); + _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 1); #else /* !CONFIG_IPS_CHECK_IN_WD */ _rtw_set_pwr_state_check_timer(pwrpriv, 1); #endif /* !CONFIG_IPS_CHECK_IN_WD */ @@ -1761,10 +1730,16 @@ static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms) void rtw_scan_wait_completed(_adapter *adapter) { - u32 scan_to = SCANNING_TIMEOUT; + u32 scan_to; +#ifdef CONFIG_CHNL_LOAD_MAGT + if (adapter->clm_flag == TRUE) + scan_to = CLM_SCANNING_TIMEOUT; + else +#endif + scan_to = SCANNING_TIMEOUT; #ifdef CONFIG_SCAN_BACKOP - if (IsSupported5G(adapter->registrypriv.wireless_mode) + if (is_supported_5g(adapter->registrypriv.wireless_mode) && IsSupported24G(adapter->registrypriv.wireless_mode)) /*dual band*/ scan_to = CONC_SCANNING_TIMEOUT_DUAL_BAND; else /*single band*/ @@ -1837,7 +1812,11 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); /* security related */ +#ifdef CONFIG_RTW_80211R + if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (psta->ft_pairwise_key_installed == _FALSE)) { +#else if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { +#endif padapter->securitypriv.binstallGrpkey = _FALSE; padapter->securitypriv.busetkipkey = _FALSE; padapter->securitypriv.bgrpkey_handshake = _FALSE; @@ -1916,8 +1895,6 @@ static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network * RTW_INFO("%s\n", __FUNCTION__); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\nfw_state:%x, BSSID:"MAC_FMT"\n" - , get_fwstate(pmlmepriv), MAC_ARG(pnetwork->network.MacAddress))); /* why not use ptarget_wlan?? */ @@ -1968,7 +1945,6 @@ static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network * default: /*pmlmepriv->fw_state = WIFI_NULL_STATE;*/ init_fwstate(pmlmepriv, WIFI_NULL_STATE); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("Invalid network_mode\n")); break; } @@ -1992,7 +1968,6 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) { _irqL irqL, irqL2; static u8 retry = 0; - u8 timer_cancelled; struct sta_info *ptarget_sta = NULL, *pcur_sta = NULL; struct sta_priv *pstapriv = &adapter->stapriv; struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); @@ -2001,7 +1976,6 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) struct wlan_network *pcur_wlan = NULL, *ptarget_wlan = NULL; unsigned int the_same_macaddr = _FALSE; - _func_enter_; #ifdef CONFIG_RTL8712 /* endian_convert */ @@ -2024,21 +1998,15 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) pnetwork->network.IELength = le32_to_cpu(pnetwork->network.IELength); #endif - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("joinbss event call back received with res=%d\n", pnetwork->join_res)); rtw_get_encrypt_decrypt_from_registrypriv(adapter); - if (pmlmepriv->assoc_ssid.SsidLength == 0) - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("@@@@@ joinbss event call back for Any SSid\n")); - else - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("@@@@@ rtw_joinbss_event_callback for SSid:%s\n", pmlmepriv->assoc_ssid.Ssid)); the_same_macaddr = _rtw_memcmp(pnetwork->network.MacAddress, cur_network->network.MacAddress, ETH_ALEN); pnetwork->network.Length = get_WLAN_BSSID_EX_sz(&pnetwork->network); if (pnetwork->network.Length > sizeof(WLAN_BSSID_EX)) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n\n ***joinbss_evt_callback return a wrong bss ***\n\n")); goto ignore_joinbss_callback; } @@ -2047,7 +2015,6 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\n rtw_joinbss_event_callback !! _enter_critical\n")); if (pnetwork->join_res > 0) { _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); @@ -2111,12 +2078,10 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) } /* s5. Cancle assoc_timer */ - _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled); + _cancel_timer_ex(&pmlmepriv->assoc_timer); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("Cancle assoc_timer\n")); } else { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("rtw_joinbss_event_callback err: fw_state:%x", get_fwstate(pmlmepriv))); _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); goto ignore_joinbss_callback; } @@ -2130,7 +2095,6 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) /* rtw_free_assoc_resources(adapter, 1); */ if ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _TRUE) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("fail! clear _FW_UNDER_LINKING ^^^fw_state=%x\n", get_fwstate(pmlmepriv))); _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); } @@ -2140,7 +2104,6 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) res = _FAIL; if (retry < 2) { res = rtw_select_and_join_from_scanned_queue(pmlmepriv); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("rtw_select_and_join_from_scanned_queue again! res:%d\n", res)); } if (res == _SUCCESS) { @@ -2151,7 +2114,6 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); rtw_indicate_connect(adapter); } else { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("Set Assoc_Timer = 1; can't find match ssid in scanned_q\n")); #endif _set_timer(&pmlmepriv->assoc_timer, 1); @@ -2166,20 +2128,17 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) ignore_joinbss_callback: _exit_critical_bh(&pmlmepriv->lock, &irqL); - _func_exit_; } void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf) { struct wlan_network *pnetwork = (struct wlan_network *)pbuf; - _func_enter_; mlmeext_joinbss_event_callback(adapter, pnetwork->join_res); rtw_mi_os_xmit_schedule(adapter); - _func_exit_; } void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected) @@ -2312,7 +2271,6 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) struct wlan_network *cur_network = &(pmlmepriv->cur_network); struct wlan_network *ptarget_wlan = NULL; - _func_enter_; #if CONFIG_RTW_MACADDR_ACL if (rtw_access_ctrl(adapter, pstassoc->macaddr) == _FALSE) @@ -2364,8 +2322,6 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) #endif/*CONFIG_BEAMFORMING*/ if (is_wep_enc(adapter->securitypriv.dot11PrivacyAlgrthm)) rtw_ap_wep_pk_setting(adapter, psta); - - rtw_mi_update_iface_status(pmlmepriv, WIFI_AP_STATE); } goto exit; } @@ -2417,9 +2373,7 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) #endif exit: - - _func_exit_; - + return; } #ifdef CONFIG_IEEE80211W @@ -2430,7 +2384,6 @@ void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf) struct stadel_event *pstadel = (struct stadel_event *)pbuf; struct sta_priv *pstapriv = &adapter->stapriv; - _func_enter_; psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr); @@ -2449,11 +2402,86 @@ void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf) } - _func_exit_; } #endif /* CONFIG_IEEE80211W */ +#ifdef CONFIG_RTW_80211R +void rtw_update_ft_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; + + psta = rtw_get_stainfo(pstapriv, pnetwork->MacAddress); + if (psta == NULL) + psta = rtw_alloc_stainfo(pstapriv, pnetwork->MacAddress); + + if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { + + padapter->securitypriv.binstallGrpkey = _FALSE; + padapter->securitypriv.busetkipkey = _FALSE; + padapter->securitypriv.bgrpkey_handshake = _FALSE; + + psta->ieee8021x_blocked = _TRUE; + psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; + psta->dot11txpn.val = psta->dot11txpn.val + 1; + + _rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype)); + _rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype)); + _rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype)); + _rtw_memset((u8 *)&psta->dot11txpn, 0, sizeof(union pn48)); +#ifdef CONFIG_IEEE80211W + _rtw_memset((u8 *)&psta->dot11wtxpn, 0, sizeof(union pn48)); +#endif + _rtw_memset((u8 *)&psta->dot11rxpn, 0, sizeof(union pn48)); + } + +} + +void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct stassoc_event *pstassoc = (struct stassoc_event *)pbuf; + ft_priv *pftpriv = &pmlmepriv->ftpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + struct cfg80211_ft_event_params ft_evt_parms; + _irqL irqL; + + _rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms)); + rtw_update_ft_stainfo(padapter, pnetwork); + ft_evt_parms.ies_len = pftpriv->ft_event.ies_len; + ft_evt_parms.ies = rtw_zmalloc(ft_evt_parms.ies_len); + if (ft_evt_parms.ies) + _rtw_memcpy((void *)ft_evt_parms.ies, pftpriv->ft_event.ies, ft_evt_parms.ies_len); + else + goto err_2; + + ft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN); + if (ft_evt_parms.target_ap) + _rtw_memcpy((void *)ft_evt_parms.target_ap, pstassoc->macaddr, ETH_ALEN); + else + goto err_1; + + ft_evt_parms.ric_ies = pftpriv->ft_event.ric_ies; + ft_evt_parms.ric_ies_len = pftpriv->ft_event.ric_ies_len; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + rtw_set_ft_status(padapter, RTW_FT_AUTHENTICATED_STA); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + rtw_cfg80211_ft_event(padapter, &ft_evt_parms); + RTW_INFO("%s: to "MAC_FMT"\n", __func__, MAC_ARG(ft_evt_parms.target_ap)); + + rtw_mfree((u8 *)pftpriv->ft_event.target_ap, ETH_ALEN); +err_1: + rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len); +err_2: + return; +} +#endif + void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id) { struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; @@ -2483,7 +2511,7 @@ void rtw_sta_mstatus_report(_adapter *adapter) struct wlan_network *tgt_network = &pmlmepriv->cur_network; struct sta_info *psta = NULL; - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); if (psta) rtw_sta_mstatus_disc_rpt(adapter, psta->mac_id); @@ -2509,7 +2537,6 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - _func_enter_; RTW_INFO("%s(mac_id=%d)=" MAC_FMT "\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr)); rtw_sta_mstatus_disc_rpt(adapter, pstadel->mac_id); @@ -2547,6 +2574,12 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) struct wlan_network *roam_target = NULL; #ifdef CONFIG_LAYER2_ROAMING +#ifdef CONFIG_RTW_80211R + if (reason == WLAN_REASON_EXPIRATION_CHK && rtw_chk_roam_flags(adapter, RTW_ROAM_ON_EXPIRED)) + pmlmepriv->ftpriv.ft_roam_on_expired = _TRUE; + else + pmlmepriv->ftpriv.ft_roam_on_expired = _FALSE; +#endif if (adapter->registrypriv.wifi_spec == 1) roam = _FALSE; else if (reason == WLAN_REASON_EXPIRATION_CHK && rtw_chk_roam_flags(adapter, RTW_ROAM_ON_EXPIRED)) @@ -2629,7 +2662,7 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) } if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS) - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("***Error=>stadel_event_callback: rtw_create_ibss_cmd status FAIL***\n")); + RTW_ERR("rtw_create_ibss_cmd FAIL\n"); } @@ -2637,7 +2670,6 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) _exit_critical_bh(&pmlmepriv->lock, &irqL2); - _func_exit_; } @@ -2648,36 +2680,31 @@ void rtw_cpwm_event_callback(PADAPTER padapter, u8 *pbuf) struct reportpwrstate_parm *preportpwrstate; #endif - _func_enter_; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_cpwm_event_callback !!!\n")); #ifdef CONFIG_LPS_LCLK preportpwrstate = (struct reportpwrstate_parm *)pbuf; preportpwrstate->state |= (u8)(adapter_to_pwrctl(padapter)->cpwm_tog + 0x80); cpwm_int_hdl(padapter, preportpwrstate); #endif - _func_exit_; } void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf) { - _func_enter_; WMMOnAssocRsp(padapter); - _func_exit_; } /* -* _rtw_join_timeout_handler - Timeout/faliure handler for CMD JoinBss -* @adapter: pointer to _adapter structure +* rtw_join_timeout_handler - Timeout/failure handler for CMD JoinBss */ -void _rtw_join_timeout_handler(_adapter *adapter) +void rtw_join_timeout_handler(void *ctx) { + _adapter *adapter = (_adapter *)ctx; _irqL irqL; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; @@ -2688,7 +2715,6 @@ void _rtw_join_timeout_handler(_adapter *adapter) } #endif - _func_enter_; RTW_INFO("%s, fw_state=%x\n", __FUNCTION__, get_fwstate(pmlmepriv)); @@ -2721,6 +2747,10 @@ void _rtw_join_timeout_handler(_adapter *adapter) } #endif /* CONFIG_INTEL_WIDI */ RTW_INFO("%s We've try roaming but fail\n", __FUNCTION__); +#ifdef CONFIG_RTW_80211R + rtw_clr_ft_flags(adapter, RTW_FT_SUPPORTED|RTW_FT_OVER_DS_SUPPORTED); + rtw_reset_ft_status(adapter); +#endif rtw_indicate_disconnect(adapter, 0, _FALSE); break; } @@ -2747,7 +2777,6 @@ void _rtw_join_timeout_handler(_adapter *adapter) #endif - _func_exit_; } @@ -2755,8 +2784,9 @@ void _rtw_join_timeout_handler(_adapter *adapter) * rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey * @adapter: pointer to _adapter structure */ -void rtw_scan_timeout_handler(_adapter *adapter) +void rtw_scan_timeout_handler(void *ctx) { + _adapter *adapter = (_adapter *)ctx; _irqL irqL; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; RTW_INFO(FUNC_ADPT_FMT" fw_state=%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); @@ -2772,8 +2802,9 @@ void rtw_scan_timeout_handler(_adapter *adapter) #endif /* CONFIG_IOCTL_CFG80211 */ rtw_indicate_scan_done(adapter, _TRUE); -#ifdef CONFIG_CONCURRENT_MODE - rtw_mi_buddy_indicate_scan_done(adapter, _TRUE);/*scanning_via_buddy_intf */ + +#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211) + rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _TRUE); #endif } @@ -2797,14 +2828,6 @@ void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason) interval_ms = rtw_min(interval_ms, 60 * 1000); *reason |= RTW_AUTO_SCAN_REASON_2040_BSS; } -#ifdef CONFIG_LAYER2_ROAMING - if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE) - && is_client_associated_to_ap(adapter) == _TRUE - ) { - interval_ms = rtw_min(interval_ms, mlme->roam_scan_int_ms); - *reason |= RTW_AUTO_SCAN_REASON_ROAM; - } -#endif exit: if (interval_ms == 0xffffffff) @@ -2843,8 +2866,15 @@ void rtw_drv_scan_by_self(_adapter *padapter, u8 reason) goto exit; if (rtw_mi_busy_traffic_check(padapter, _FALSE)) { - RTW_INFO(FUNC_ADPT_FMT" exit due to BusyTraffic\n", FUNC_ADPT_ARG(padapter)); - goto exit; +#ifdef CONFIG_LAYER2_ROAMING + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE) { + RTW_INFO("need to roam, don't care BusyTraffic\n"); + } else +#endif + { + RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } } if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { RTW_INFO(FUNC_ADPT_FMT" WIFI_AP_STATE && WIFI_UNDER_WPS\n", FUNC_ADPT_ARG(padapter)); @@ -2901,32 +2931,30 @@ static void rtw_auto_scan_handler(_adapter *padapter) exit: return; } +static u8 is_drv_in_lps(_adapter *adapter) +{ + u8 is_in_lps = _FALSE; -void rtw_dynamic_check_timer_handlder(_adapter *adapter) + #ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/ + if ((adapter_to_pwrctl(adapter)->bFwCurrentInPSMode == _TRUE) + #ifdef CONFIG_BT_COEXIST + && (rtw_btcoex_IsBtControlLps(adapter) == _FALSE) + #endif + ) + is_in_lps = _TRUE; + #endif /* CONFIG_LPS_LCLK_WD_TIMER*/ + return is_in_lps; +} +void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter) { #ifdef CONFIG_AP_MODE struct mlme_priv *pmlmepriv = &adapter->mlmepriv; #endif /* CONFIG_AP_MODE */ - struct registry_priv *pregistrypriv = &adapter->registrypriv; - - if (!adapter) - return; - - if (!rtw_is_hw_init_completed(adapter)) - return; - - if (RTW_CANNOT_RUN(adapter)) - return; if (adapter->net_closed == _TRUE) return; - -#ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/ - if ((adapter_to_pwrctl(adapter)->bFwCurrentInPSMode == _TRUE) -#ifdef CONFIG_BT_COEXIST - && (rtw_btcoex_IsBtControlLps(adapter) == _FALSE) -#endif - ) { + #ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/ + if (is_drv_in_lps(adapter)) { u8 bEnterPS; linked_status_chk(adapter, 1); @@ -2938,13 +2966,8 @@ void rtw_dynamic_check_timer_handlder(_adapter *adapter) } else { /* call rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1) in traffic_status_watchdog() */ } - - } else -#endif /* CONFIG_LPS_LCLK_WD_TIMER */ - { - if (is_primary_adapter(adapter)) - rtw_dynamic_chk_wk_cmd(adapter); } + #endif /* CONFIG_LPS_LCLK_WD_TIMER */ /* auto site survey */ rtw_auto_scan_handler(adapter); @@ -2967,14 +2990,13 @@ void rtw_dynamic_check_timer_handlder(_adapter *adapter) #else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ if (rcu_dereference(adapter->pnetdev->rx_handler_data) #endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ - && (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) { + && (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) { /* expire NAT2.5 entry */ void nat25_db_expire(_adapter *priv); nat25_db_expire(adapter); if (adapter->pppoe_connection_in_progress > 0) adapter->pppoe_connection_in_progress--; - /* due to rtw_dynamic_check_timer_handlder() is called every 2 seconds */ if (adapter->pppoe_connection_in_progress > 0) adapter->pppoe_connection_in_progress--; @@ -2988,6 +3010,79 @@ void rtw_dynamic_check_timer_handlder(_adapter *adapter) } +/*#define DBG_TRAFFIC_STATISTIC*/ +static void collect_traffic_statistics(_adapter *padapter) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + + /*_rtw_memset(&pdvobjpriv->traffic_stat, 0, sizeof(struct rtw_traffic_statistics));*/ + + /* Tx bytes reset*/ + pdvobjpriv->traffic_stat.tx_bytes = 0; + pdvobjpriv->traffic_stat.tx_pkts = 0; + pdvobjpriv->traffic_stat.tx_drop = 0; + + /* Rx bytes reset*/ + pdvobjpriv->traffic_stat.rx_bytes = 0; + pdvobjpriv->traffic_stat.rx_pkts = 0; + pdvobjpriv->traffic_stat.rx_drop = 0; + + rtw_mi_traffic_statistics(padapter); + + /* Calculate throughput in last interval */ + pdvobjpriv->traffic_stat.cur_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes - pdvobjpriv->traffic_stat.last_tx_bytes; + pdvobjpriv->traffic_stat.cur_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes - pdvobjpriv->traffic_stat.last_rx_bytes; + pdvobjpriv->traffic_stat.last_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes; + pdvobjpriv->traffic_stat.last_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes; + + pdvobjpriv->traffic_stat.cur_tx_tp = (u32)(pdvobjpriv->traffic_stat.cur_tx_bytes * 8 / 2 / 1024 / 1024); + pdvobjpriv->traffic_stat.cur_rx_tp = (u32)(pdvobjpriv->traffic_stat.cur_rx_bytes * 8 / 2 / 1024 / 1024); + + #ifdef DBG_TRAFFIC_STATISTIC + RTW_INFO("\n========================\n"); + RTW_INFO("cur_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_tx_bytes); + RTW_INFO("cur_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_rx_bytes); + + RTW_INFO("last_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_tx_bytes); + RTW_INFO("last_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_rx_bytes); + + RTW_INFO("cur_tx_tp:%d\n", pdvobjpriv->traffic_stat.cur_tx_tp); + RTW_INFO("cur_rx_tp:%d\n", pdvobjpriv->traffic_stat.cur_rx_tp); + #endif +} + +void rtw_dynamic_check_timer_handlder(void *ctx) +{ + struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx; + _adapter *adapter = dvobj_get_primary_adapter(pdvobj); + +#if (MP_DRIVER == 1) + if (adapter->registrypriv.mp_mode == 1 && adapter->mppriv.mp_dm == 0) { /* for MP ODM dynamic Tx power tracking */ + /* RTW_INFO("%s mp_dm =0 return\n", __func__); */ + goto exit; + } +#endif + + if (!adapter) + goto exit; + + if (!rtw_is_hw_init_completed(adapter)) + goto exit; + + if (RTW_CANNOT_RUN(adapter)) + goto exit; + + collect_traffic_statistics(adapter); + + rtw_mi_dynamic_check_timer_handlder(adapter); + + if (!is_drv_in_lps(adapter)) + rtw_dynamic_chk_wk_cmd(adapter); + +exit: + _set_timer(&pdvobj->dynamic_chk_timer, 2000); +} + #ifdef CONFIG_SET_SCAN_DENY_TIMER inline bool rtw_is_scan_deny(_adapter *adapter) @@ -3004,8 +3099,10 @@ inline void rtw_clear_scan_deny(_adapter *adapter) RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); } -void rtw_set_scan_deny_timer_hdl(_adapter *adapter) +void rtw_set_scan_deny_timer_hdl(void *ctx) { + _adapter *adapter = (_adapter *)ctx; + rtw_clear_scan_deny(adapter); } void rtw_set_scan_deny(_adapter *adapter, u32 ms) @@ -3029,6 +3126,12 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme { int updated = _FALSE; _adapter *adapter = container_of(mlme, _adapter, mlmepriv); +#ifdef CONFIG_RTW_80211R + ft_priv *pftpriv = &mlme->ftpriv; + u32 mdie_len = 0; + u8 *ptmp = NULL; +#endif + if (is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE) goto exit; @@ -3036,6 +3139,32 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme if (rtw_is_desired_network(adapter, competitor) == _FALSE) goto exit; +#ifdef CONFIG_LAYER2_ROAMING + if (mlme->need_to_roam == _FALSE) + goto exit; +#endif + +#ifdef CONFIG_RTW_80211R + if (rtw_chk_ft_flags(adapter, RTW_FT_SUPPORTED)) { + ptmp = rtw_get_ie(&competitor->network.IEs[12], _MDIE_, &mdie_len, competitor->network.IELength-12); + if (ptmp) { + if (!_rtw_memcmp(&pftpriv->mdid, ptmp+2, 2)) + goto exit; + + /*The candidate don't support over-the-DS*/ + if (rtw_chk_ft_flags(adapter, RTW_FT_STA_OVER_DS_SUPPORTED)) { + if ((rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && !(*(ptmp+4) & 0x01)) || + (!rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && (*(ptmp+4) & 0x01))) { + RTW_INFO("FT: ignore the candidate(" MAC_FMT ") for over-the-DS\n", MAC_ARG(competitor->network.MacAddress)); + rtw_clr_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED); + goto exit; + } + } + } else + goto exit; + } +#endif + RTW_INFO("roam candidate:%s %s("MAC_FMT", ch%3u) rssi:%d, age:%5d\n", (competitor == mlme->cur_network_scanned) ? "*" : " " , competitor->network.Ssid.Ssid, @@ -3084,7 +3213,6 @@ int rtw_select_roaming_candidate(struct mlme_priv *mlme) struct wlan_network *candidate = NULL; u8 bSupportAntDiv = _FALSE; - _func_enter_; if (mlme->cur_network_scanned == NULL) { rtw_warn_on(1); @@ -3101,7 +3229,6 @@ int rtw_select_roaming_candidate(struct mlme_priv *mlme) pnetwork = LIST_CONTAINOR(mlme->pscanned, struct wlan_network, list); if (pnetwork == NULL) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s return _FAIL:(pnetwork==NULL)\n", __FUNCTION__)); ret = _FAIL; goto exit; } @@ -3224,7 +3351,6 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv) struct wlan_network *candidate = NULL; u8 bSupportAntDiv = _FALSE; - _func_enter_; adapter = (_adapter *)pmlmepriv->nic_hdl; @@ -3245,7 +3371,6 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv) pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); if (pnetwork == NULL) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s return _FAIL:(pnetwork==NULL)\n", __FUNCTION__)); ret = _FAIL; goto exit; } @@ -3294,7 +3419,7 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv) } else #endif { - rtw_disassoc_cmd(adapter, 0, _TRUE); + rtw_disassoc_cmd(adapter, 0, 0); rtw_indicate_disconnect(adapter, 0, _FALSE); rtw_free_assoc_resources(adapter, 0); } @@ -3317,7 +3442,6 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv) exit: _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - _func_exit_; return ret; } @@ -3329,7 +3453,6 @@ sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv) struct cmd_priv *pcmdpriv = &(adapter->cmdpriv); sint res = _SUCCESS; - _func_enter_; pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmd == NULL) { @@ -3356,13 +3479,11 @@ sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv) _rtw_init_listhead(&pcmd->list); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("after enqueue set_auth_cmd, auth_mode=%x\n", psecuritypriv->dot11AuthAlgrthm)); res = rtw_enqueue_cmd(pcmdpriv, pcmd); exit: - _func_exit_; return res; @@ -3378,7 +3499,6 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); sint res = _SUCCESS; - _func_enter_; psetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm)); if (psetkeyparm == NULL) { @@ -3389,10 +3509,8 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { psetkeyparm->algorithm = (unsigned char)psecuritypriv->dot118021XGrpPrivacy; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n rtw_set_key: psetkeyparm->algorithm=(unsigned char)psecuritypriv->dot118021XGrpPrivacy=%d\n", psetkeyparm->algorithm)); } else { psetkeyparm->algorithm = (u8)psecuritypriv->dot11PrivacyAlgrthm; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n rtw_set_key: psetkeyparm->algorithm=(u8)psecuritypriv->dot11PrivacyAlgrthm=%d\n", psetkeyparm->algorithm)); } psetkeyparm->keyid = (u8)keyid;/* 0~3 */ @@ -3401,7 +3519,6 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke adapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid); RTW_INFO("==> rtw_set_key algorithm(%x),keyid(%x),key_mask(%x)\n", psetkeyparm->algorithm, psetkeyparm->keyid, adapter->securitypriv.key_mask); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n rtw_set_key: psetkeyparm->algorithm=%d psetkeyparm->keyid=(u8)keyid=%d\n", psetkeyparm->algorithm, keyid)); switch (psetkeyparm->algorithm) { @@ -3424,7 +3541,6 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke psetkeyparm->grpkey = 1; break; default: - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n rtw_set_key:psecuritypriv->dot11PrivacyAlgrthm = %x (must be 1 or 2 or 4 or 5)\n", psecuritypriv->dot11PrivacyAlgrthm)); res = _FAIL; rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm)); goto exit; @@ -3455,7 +3571,6 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke rtw_mfree((u8 *) psetkeyparm, sizeof(struct setkey_parm)); } exit: - _func_exit_; return res; } @@ -3623,11 +3738,7 @@ sint rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len) uint ndisauthmode = psecuritypriv->ndisauthtype; uint ndissecuritytype = psecuritypriv->ndisencryptstatus; - _func_enter_; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, - ("+rtw_restruct_sec_ie: ndisauthmode=%d ndissecuritytype=%d\n", - ndisauthmode, ndissecuritytype)); /* copy fixed ie only */ _rtw_memcpy(out_ie, in_ie, 12); @@ -3669,7 +3780,6 @@ sint rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len) ielength = rtw_append_pmkid(adapter, iEntry, out_ie, ielength); } - _func_exit_; return ielength; } @@ -3680,7 +3790,6 @@ void rtw_init_registrypriv_dev_network(_adapter *adapter) WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network; u8 *myhwaddr = adapter_mac_addr(adapter); - _func_enter_; _rtw_memcpy(pdev_network->MacAddress, myhwaddr, ETH_ALEN); @@ -3694,7 +3803,6 @@ void rtw_init_registrypriv_dev_network(_adapter *adapter) pdev_network->Configuration.FHConfig.DwellTime = 0; - _func_exit_; } @@ -3708,7 +3816,6 @@ void rtw_update_registrypriv_dev_network(_adapter *adapter) /* struct xmit_priv *pxmitpriv = &adapter->xmitpriv; */ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - _func_enter_; #if 0 pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense; @@ -3751,7 +3858,6 @@ void rtw_update_registrypriv_dev_network(_adapter *adapter) } pdev_network->Configuration.DSConfig = (pregistrypriv->channel); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("pregistrypriv->channel=%d, pdev_network->Configuration.DSConfig=0x%x\n", pregistrypriv->channel, pdev_network->Configuration.DSConfig)); if (cur_network->network.InfrastructureMode == Ndis802_11IBSS) { pdev_network->Configuration.ATIMWindow = (0); @@ -3777,16 +3883,13 @@ void rtw_update_registrypriv_dev_network(_adapter *adapter) /* notes: translate IELength & Length after assign the Length to cmdsz in createbss_cmd(); */ /* pdev_network->IELength = cpu_to_le32(sz); */ - _func_exit_; } void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter) { - _func_enter_; - _func_exit_; } @@ -3914,11 +4017,16 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui HT_CAP_AMPDU_DENSITY best_ampdu_density; unsigned char *p, *pframe; struct rtw_ieee80211_ht_cap ht_capie; - u8 cbw40_enable = 0, rf_type = 0, operation_bw = 0, rf_num = 0, rx_stbc_nss = 0; + u8 cbw40_enable = 0, rf_type = 0, operation_bw = 0, rf_num = 0, rx_stbc_nss = 0, rx_nss = 0; struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct ht_priv *phtpriv = &pmlmepriv->htpriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); +#ifdef CONFIG_80211AC_VHT + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; +#endif /* CONFIG_80211AC_VHT */ phtpriv->ht_option = _FALSE; @@ -4010,28 +4118,28 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui /* update default supported_mcs_set */ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num); - switch (rf_type) { - case RF_1T1R: + switch (rx_nss) { + case 1: set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_1R); break; - - case RF_2T2R: - case RF_1T2R: -#ifdef CONFIG_DISABLE_MCS13TO15 + case 2: + #ifdef CONFIG_DISABLE_MCS13TO15 if (((cbw40_enable == 1) && (operation_bw == CHANNEL_WIDTH_40)) && (pregistrypriv->wifi_spec != 1)) set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R_13TO15_OFF); else + #endif set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R); -#else /* CONFIG_DISABLE_MCS13TO15 */ - set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R); -#endif /* CONFIG_DISABLE_MCS13TO15 */ break; - case RF_3T3R: + case 3: set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_3R); break; + case 4: + set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_4R); + break; default: - RTW_INFO("[warning] rf_type %d is not expected\n", rf_type); + RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", rf_type, hal_spec->rx_nss_num); } { @@ -4099,7 +4207,14 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(&ht_capie, 1); /* Explicit Compressed Beamforming Feedback Capable */ SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(&ht_capie, 2); + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); +#ifdef CONFIG_80211AC_VHT + /* IOT action suggested by Yu Chen 2017/3/3 */ + if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) && + !GET_VHT_CAPABILITY_ELE_MU_BFER(&pvhtpriv->beamform_cap)) + rf_num = (rf_num >= 2 ? 2 : rf_num); +#endif SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, rf_num); } #endif/*CONFIG_BEAMFORMING*/ @@ -4156,10 +4271,7 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel) phtpriv->ampdu_enable = _TRUE; } else phtpriv->ampdu_enable = _TRUE; - } else if (pregistrypriv->ampdu_enable == 2) { - /* remove this part because testbed AP should disable RX AMPDU */ - /* phtpriv->ampdu_enable = _TRUE; */ - } + } /* check Max Rx A-MPDU Size */ @@ -4197,36 +4309,39 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel) if ((cbw40_enable) && (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) && (pmlmeinfo->HT_info.infos[0] & BIT(2))) { + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); int i; u8 rf_type = RF_1T1R; + u8 tx_nss = 0; rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); /* update the MCS set */ for (i = 0; i < 16; i++) pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i]; /* update the MCS rates */ - switch (rf_type) { - case RF_1T1R: - case RF_1T2R: + switch (tx_nss) { + case 1: set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R); break; - case RF_2T2R: -#ifdef CONFIG_DISABLE_MCS13TO15 + case 2: + #ifdef CONFIG_DISABLE_MCS13TO15 if (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1) set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF); else + #endif set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R); -#else /* CONFIG_DISABLE_MCS13TO15 */ - set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R); -#endif /* CONFIG_DISABLE_MCS13TO15 */ break; - case RF_3T3R: + case 3: set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R); break; + case 4: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R); + break; default: - RTW_INFO("[warning] rf_type %d is not expected\n", rf_type); + RTW_WARN("rf_type:%d or tx_nss_num:%u is not expected\n", rf_type, hal_spec->tx_nss_num); } /* switch to the 40M Hz mode accoring to the AP */ @@ -4474,6 +4589,10 @@ void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) continue; else { RTW_INFO("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__, __LINE__); +#ifdef CONFIG_RTW_80211R + rtw_clr_ft_flags(padapter, RTW_FT_SUPPORTED|RTW_FT_OVER_DS_SUPPORTED); + rtw_reset_ft_status(padapter); +#endif rtw_indicate_disconnect(padapter, 0, _FALSE); break; } diff --git a/core/rtw_mlme_ext.c b/core/rtw_mlme_ext.c index c256193..f7bc092 100644 --- a/core/rtw_mlme_ext.c +++ b/core/rtw_mlme_ext.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_MLME_EXT_C_ #include @@ -79,14 +74,16 @@ struct action_handler OnAction_tbl[] = { {RTW_WLAN_CATEGORY_BACK, "ACTION_BACK", &OnAction_back}, {RTW_WLAN_CATEGORY_PUBLIC, "ACTION_PUBLIC", on_action_public}, {RTW_WLAN_CATEGORY_RADIO_MEASUREMENT, "ACTION_RADIO_MEASUREMENT", &DoReserved}, - {RTW_WLAN_CATEGORY_FT, "ACTION_FT", &DoReserved}, + {RTW_WLAN_CATEGORY_FT, "ACTION_FT", &OnAction_ft}, {RTW_WLAN_CATEGORY_HT, "ACTION_HT", &OnAction_ht}, #ifdef CONFIG_IEEE80211W {RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &OnAction_sa_query}, #else {RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &DoReserved}, #endif /* CONFIG_IEEE80211W */ - /* add for CONFIG_IEEE80211W */ +#ifdef CONFIG_RTW_WNM + {RTW_WLAN_CATEGORY_WNM, "ACTION_WNM", &on_action_wnm}, +#endif {RTW_WLAN_CATEGORY_UNPROTECTED_WNM, "ACTION_UNPROTECTED_WNM", &DoReserved}, {RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &DoReserved}, {RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm}, @@ -143,166 +140,211 @@ static RT_CHANNEL_PLAN legacy_channel_plan[] = { }; #endif -static RT_CHANNEL_PLAN_2G RTW_ChannelPlan2G[] = { - /* 0, RTW_RD_2G_NULL */ {{}, 0}, - /* 1, RTW_RD_2G_WORLD */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, - /* 2, RTW_RD_2G_ETSI1 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, - /* 3, RTW_RD_2G_FCC1 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}, 11}, - /* 4, RTW_RD_2G_MKK1 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14}, - /* 5, RTW_RD_2G_ETSI2 */ {{10, 11, 12, 13}, 4}, - /* 6, RTW_RD_2G_GLOBAL */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14}, - /* 7, RTW_RD_2G_MKK2 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, - /* 8, RTW_RD_2G_FCC2 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, +static struct ch_list_t RTW_ChannelPlan2G[] = { + /* 0, RTW_RD_2G_NULL */ CH_LIST_ENT(0), + /* 1, RTW_RD_2G_WORLD */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 2, RTW_RD_2G_ETSI1 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 3, RTW_RD_2G_FCC1 */ CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11), + /* 4, RTW_RD_2G_MKK1 */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14), + /* 5, RTW_RD_2G_ETSI2 */ CH_LIST_ENT(4, 10, 11, 12, 13), + /* 6, RTW_RD_2G_GLOBAL */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14), + /* 7, RTW_RD_2G_MKK2 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 8, RTW_RD_2G_FCC2 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 9, RTW_RD_2G_IC1 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), }; -static RT_CHANNEL_PLAN_5G RTW_ChannelPlan5G[] = { - /* 0, RTW_RD_5G_NULL */ {{}, 0}, - /* 1, RTW_RD_5G_ETSI1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19}, - /* 2, RTW_RD_5G_ETSI2 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24}, - /* 3, RTW_RD_5G_ETSI3 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165}, 22}, - /* 4, RTW_RD_5G_FCC1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24}, - /* 5, RTW_RD_5G_FCC2 */ {{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9}, - /* 6, RTW_RD_5G_FCC3 */ {{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13}, - /* 7, RTW_RD_5G_FCC4 */ {{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161}, 12}, - /* 8, RTW_RD_5G_FCC5 */ {{149, 153, 157, 161, 165}, 5}, - /* 9, RTW_RD_5G_FCC6 */ {{36, 40, 44, 48, 52, 56, 60, 64}, 8}, - /* 10, RTW_RD_5G_FCC7 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 21}, - /* 11, RTW_RD_5G_KCC1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161}, 19}, - /* 12, RTW_RD_5G_MKK1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19}, - /* 13, RTW_RD_5G_MKK2 */ {{36, 40, 44, 48, 52, 56, 60, 64}, 8}, - /* 14, RTW_RD_5G_MKK3 */ {{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11}, - /* 15, RTW_RD_5G_NCC1 */ {{56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 16}, - /* 16, RTW_RD_5G_NCC2 */ {{56, 60, 64, 149, 153, 157, 161, 165}, 8}, - /* 17, RTW_RD_5G_NCC3 */ {{149, 153, 157, 161, 165}, 5}, - /* 18, RTW_RD_5G_ETSI4 */ {{36, 40, 44, 48}, 4}, - /* 19, RTW_RD_5G_ETSI5 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 21}, - /* 20, RTW_RD_5G_FCC8 */ {{149, 153, 157, 161}, 4}, - /* 21, RTW_RD_5G_ETSI6 */ {{36, 40, 44, 48, 52, 56, 60, 64}, 8}, - /* 22, RTW_RD_5G_ETSI7 */ {{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13}, - /* 23, RTW_RD_5G_ETSI8 */ {{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9}, - /* 24, RTW_RD_5G_ETSI9 */ {{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11}, - /* 25, RTW_RD_5G_ETSI10 */ {{149, 153, 157, 161, 165}, 5}, - /* 26, RTW_RD_5G_ETSI11 */ {{36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165}, 16}, - /* 27, RTW_RD_5G_NCC4 */ {{52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 17}, - /* 28, RTW_RD_5G_ETSI12 */ {{149, 153, 157, 161}, 4}, - /* 29, RTW_RD_5G_FCC9 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 21}, - /* 30, RTW_RD_5G_ETSI13 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140}, 16}, - /* 31, RTW_RD_5G_FCC10 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161}, 20}, - /* 32, RTW_RD_5G_MKK4 */ {{36, 40, 44, 48}, 4}, - /* 33, RTW_RD_5G_ETSI14 */ {{36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140}, 11}, +#ifdef CONFIG_IEEE80211_BAND_5GHZ +static struct ch_list_t RTW_ChannelPlan5G[] = { + /* 0, RTW_RD_5G_NULL */ CH_LIST_ENT(0), + /* 1, RTW_RD_5G_ETSI1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), + /* 2, RTW_RD_5G_ETSI2 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 3, RTW_RD_5G_ETSI3 */ CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165), + /* 4, RTW_RD_5G_FCC1 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 5, RTW_RD_5G_FCC2 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165), + /* 6, RTW_RD_5G_FCC3 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 7, RTW_RD_5G_FCC4 */ CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161), + /* 8, RTW_RD_5G_FCC5 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165), + /* 9, RTW_RD_5G_FCC6 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), + /* 10, RTW_RD_5G_FCC7 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 11, RTW_RD_5G_IC1 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 12, RTW_RD_5G_KCC1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161), + /* 13, RTW_RD_5G_MKK1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), + /* 14, RTW_RD_5G_MKK2 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), + /* 15, RTW_RD_5G_MKK3 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), + /* 16, RTW_RD_5G_NCC1 */ CH_LIST_ENT(16, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 17, RTW_RD_5G_NCC2 */ CH_LIST_ENT(8, 56, 60, 64, 149, 153, 157, 161, 165), + /* 18, RTW_RD_5G_NCC3 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165), + /* 19, RTW_RD_5G_ETSI4 */ CH_LIST_ENT(4, 36, 40, 44, 48), + /* 20, RTW_RD_5G_ETSI5 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 21, RTW_RD_5G_FCC8 */ CH_LIST_ENT(4, 149, 153, 157, 161), + /* 22, RTW_RD_5G_ETSI6 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), + /* 23, RTW_RD_5G_ETSI7 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 24, RTW_RD_5G_ETSI8 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165), + /* 25, RTW_RD_5G_ETSI9 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), + /* 26, RTW_RD_5G_ETSI10 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165), + /* 27, RTW_RD_5G_ETSI11 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165), + /* 28, RTW_RD_5G_NCC4 */ CH_LIST_ENT(17, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 29, RTW_RD_5G_ETSI12 */ CH_LIST_ENT(4, 149, 153, 157, 161), + /* 30, RTW_RD_5G_FCC9 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 31, RTW_RD_5G_ETSI13 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140), + /* 32, RTW_RD_5G_FCC10 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161), + /* 33, RTW_RD_5G_MKK4 */ CH_LIST_ENT(4, 36, 40, 44, 48), + /* 34, RTW_RD_5G_ETSI14 */ CH_LIST_ENT(11, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140), + /* 35, RTW_RD_5G_FCC11 */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165), + /* 36, RTW_RD_5G_ETSI15 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165), + /* 37, RTW_RD_5G_MKK5 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 38, RTW_RD_5G_ETSI16 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 39, RTW_RD_5G_ETSI17 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 40, RTW_RD_5G_FCC12*/ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 41, RTW_RD_5G_FCC13 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 42, RTW_RD_5G_FCC14 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 43, RTW_RD_5G_FCC15 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 44, RTW_RD_5G_FCC16 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 45, RTW_RD_5G_ETSI18 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165), + /* 46, RTW_RD_5G_ETSI19 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 47, RTW_RD_5G_FCC17 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140), + /* 48, RTW_RD_5G_ETSI20 */ CH_LIST_ENT(9, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 49, RTW_RD_5G_IC2 */ CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 144, 149, 153, 157, 161, 165), + /* 50, RTW_RD_5G_ETSI21 */ CH_LIST_ENT(13, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 51, RTW_RD_5G_FCC18 */ CH_LIST_ENT(8, 100, 104, 108, 112, 116, 132, 136, 140), + /* 52, RTW_RD_5G_WORLD */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165), /* === Below are driver defined for legacy channel plan compatible, NO static index assigned ==== */ - /* RTW_RD_5G_OLD_FCC1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20}, - /* RTW_RD_5G_OLD_NCC1 */ {{56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 15}, - /* RTW_RD_5G_OLD_KCC1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 20}, + /* RTW_RD_5G_OLD_FCC1 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165), + /* RTW_RD_5G_OLD_NCC1 */ CH_LIST_ENT(15, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165), + /* RTW_RD_5G_OLD_KCC1 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165), }; +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[] = { /* ===== 0x00 ~ 0x1F, legacy channel plan ===== */ - {RTW_RD_2G_FCC1, RTW_RD_5G_KCC1, TXPWR_LMT_FCC}, /* 0x00, RTW_CHPLAN_FCC */ - {RTW_RD_2G_FCC1, RTW_RD_5G_OLD_FCC1, TXPWR_LMT_FCC}, /* 0x01, RTW_CHPLAN_IC */ - {RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI}, /* 0x02, RTW_CHPLAN_ETSI */ - {RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI}, /* 0x03, RTW_CHPLAN_SPAIN */ - {RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI}, /* 0x04, RTW_CHPLAN_FRANCE */ - {RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK}, /* 0x05, RTW_CHPLAN_MKK */ - {RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK}, /* 0x06, RTW_CHPLAN_MKK1 */ - {RTW_RD_2G_ETSI1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI}, /* 0x07, RTW_CHPLAN_ISRAEL */ - {RTW_RD_2G_MKK1, RTW_RD_5G_FCC6, TXPWR_LMT_MKK}, /* 0x08, RTW_CHPLAN_TELEC */ - {RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */ - {RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */ - {RTW_RD_2G_FCC1, RTW_RD_5G_OLD_NCC1, TXPWR_LMT_FCC}, /* 0x0B, RTW_CHPLAN_TAIWAN */ - {RTW_RD_2G_ETSI1, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI}, /* 0x0C, RTW_CHPLAN_CHINA */ - {RTW_RD_2G_FCC1, RTW_RD_5G_FCC3, TXPWR_LMT_WW}, /* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ /* ETSI:Singapore, India. FCC:Mexico => WW */ - {RTW_RD_2G_FCC1, RTW_RD_5G_OLD_KCC1, TXPWR_LMT_ETSI}, /* 0x0E, RTW_CHPLAN_KOREA */ - {RTW_RD_2G_FCC1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI}, /* 0x0F, RTW_CHPLAN_TURKEY */ - {RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_MKK}, /* 0x10, RTW_CHPLAN_JAPAN */ - {RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC}, /* 0x11, RTW_CHPLAN_FCC_NO_DFS */ - {RTW_RD_2G_ETSI1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK}, /* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */ - {RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_WW}, /* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */ - {RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC}, /* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */ - {RTW_RD_2G_WORLD, RTW_RD_5G_FCC7, TXPWR_LMT_ETSI}, /* 0x15, RTW_CHPLAN_ETSI_NO_DFS */ - {RTW_RD_2G_WORLD, RTW_RD_5G_NCC1, TXPWR_LMT_ETSI}, /* 0x16, RTW_CHPLAN_KOREA_NO_DFS */ - {RTW_RD_2G_MKK1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK}, /* 0x17, RTW_CHPLAN_JAPAN_NO_DFS */ - {RTW_RD_2G_NULL, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI}, /* 0x18, RTW_CHPLAN_PAKISTAN_NO_DFS */ - {RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC}, /* 0x19, RTW_CHPLAN_TAIWAN2_NO_DFS */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1A, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1B, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1C, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1D, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1E, */ - {RTW_RD_2G_NULL, RTW_RD_5G_FCC1, TXPWR_LMT_WW}, /* 0x1F, RTW_CHPLAN_WORLD_WIDE_ONLY_5G */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_KCC1, TXPWR_LMT_FCC), /* 0x00, RTW_CHPLAN_FCC */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_FCC1, TXPWR_LMT_FCC), /* 0x01, RTW_CHPLAN_IC */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x02, RTW_CHPLAN_ETSI */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x03, RTW_CHPLAN_SPAIN */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x04, RTW_CHPLAN_FRANCE */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x05, RTW_CHPLAN_MKK */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x06, RTW_CHPLAN_MKK1 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI), /* 0x07, RTW_CHPLAN_ISRAEL */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_FCC6, TXPWR_LMT_MKK), /* 0x08, RTW_CHPLAN_TELEC */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_NCC1, TXPWR_LMT_FCC), /* 0x0B, RTW_CHPLAN_TAIWAN */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI), /* 0x0C, RTW_CHPLAN_CHINA */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC3, TXPWR_LMT_WW), /* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ /* ETSI:Singapore, India. FCC:Mexico => WW */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_KCC1, TXPWR_LMT_ETSI), /* 0x0E, RTW_CHPLAN_KOREA */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI), /* 0x0F, RTW_CHPLAN_TURKEY */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_MKK), /* 0x10, RTW_CHPLAN_JAPAN */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x11, RTW_CHPLAN_FCC_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK), /* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_WW), /* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC), /* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC7, TXPWR_LMT_ETSI), /* 0x15, RTW_CHPLAN_ETSI_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NCC1, TXPWR_LMT_ETSI), /* 0x16, RTW_CHPLAN_KOREA_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK), /* 0x17, RTW_CHPLAN_JAPAN_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI), /* 0x18, RTW_CHPLAN_PAKISTAN_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x19, RTW_CHPLAN_TAIWAN2_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1A, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1B, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_FCC1, TXPWR_LMT_WW), /* 0x1F, RTW_CHPLAN_WORLD_WIDE_ONLY_5G */ /* ===== 0x20 ~ 0x7F, new channel plan ===== */ - {RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x20, RTW_CHPLAN_WORLD_NULL */ - {RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI}, /* 0x21, RTW_CHPLAN_ETSI1_NULL */ - {RTW_RD_2G_FCC1, RTW_RD_5G_NULL, TXPWR_LMT_FCC}, /* 0x22, RTW_CHPLAN_FCC1_NULL */ - {RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK}, /* 0x23, RTW_CHPLAN_MKK1_NULL */ - {RTW_RD_2G_ETSI2, RTW_RD_5G_NULL, TXPWR_LMT_ETSI}, /* 0x24, RTW_CHPLAN_ETSI2_NULL */ - {RTW_RD_2G_FCC1, RTW_RD_5G_FCC1, TXPWR_LMT_FCC}, /* 0x25, RTW_CHPLAN_FCC1_FCC1 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI}, /* 0x26, RTW_CHPLAN_WORLD_ETSI1 */ - {RTW_RD_2G_MKK1, RTW_RD_5G_MKK1, TXPWR_LMT_MKK}, /* 0x27, RTW_CHPLAN_MKK1_MKK1 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_KCC1, TXPWR_LMT_ETSI}, /* 0x28, RTW_CHPLAN_WORLD_KCC1 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_FCC2, TXPWR_LMT_FCC}, /* 0x29, RTW_CHPLAN_WORLD_FCC2 */ - {RTW_RD_2G_FCC2, RTW_RD_5G_NULL, TXPWR_LMT_FCC}, /* 0x2A, RTW_CHPLAN_FCC2_NULL */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2B, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2C, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2D, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2E, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2F, */ - {RTW_RD_2G_WORLD, RTW_RD_5G_FCC3, TXPWR_LMT_FCC}, /* 0x30, RTW_CHPLAN_WORLD_FCC3 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_FCC4, TXPWR_LMT_FCC}, /* 0x31, RTW_CHPLAN_WORLD_FCC4 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_FCC5, TXPWR_LMT_FCC}, /* 0x32, RTW_CHPLAN_WORLD_FCC5 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_FCC6, TXPWR_LMT_FCC}, /* 0x33, RTW_CHPLAN_WORLD_FCC6 */ - {RTW_RD_2G_FCC1, RTW_RD_5G_FCC7, TXPWR_LMT_FCC}, /* 0x34, RTW_CHPLAN_FCC1_FCC7 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI2, TXPWR_LMT_ETSI}, /* 0x35, RTW_CHPLAN_WORLD_ETSI2 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI3, TXPWR_LMT_ETSI}, /* 0x36, RTW_CHPLAN_WORLD_ETSI3 */ - {RTW_RD_2G_MKK1, RTW_RD_5G_MKK2, TXPWR_LMT_MKK}, /* 0x37, RTW_CHPLAN_MKK1_MKK2 */ - {RTW_RD_2G_MKK1, RTW_RD_5G_MKK3, TXPWR_LMT_MKK}, /* 0x38, RTW_CHPLAN_MKK1_MKK3 */ - {RTW_RD_2G_FCC1, RTW_RD_5G_NCC1, TXPWR_LMT_FCC}, /* 0x39, RTW_CHPLAN_FCC1_NCC1 */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3A, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3B, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3C, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3D, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3E, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3F, */ - {RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC}, /* 0x40, RTW_CHPLAN_FCC1_NCC2 */ - {RTW_RD_2G_GLOBAL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x41, RTW_CHPLAN_GLOBAL_NULL */ - {RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI4, TXPWR_LMT_ETSI}, /* 0x42, RTW_CHPLAN_ETSI1_ETSI4 */ - {RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC}, /* 0x43, RTW_CHPLAN_FCC1_FCC2 */ - {RTW_RD_2G_FCC1, RTW_RD_5G_NCC3, TXPWR_LMT_FCC}, /* 0x44, RTW_CHPLAN_FCC1_NCC3 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI5, TXPWR_LMT_ETSI}, /* 0x45, RTW_CHPLAN_WORLD_ETSI5 */ - {RTW_RD_2G_FCC1, RTW_RD_5G_FCC8, TXPWR_LMT_FCC}, /* 0x46, RTW_CHPLAN_FCC1_FCC8 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI6, TXPWR_LMT_ETSI}, /* 0x47, RTW_CHPLAN_WORLD_ETSI6 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI7, TXPWR_LMT_ETSI}, /* 0x48, RTW_CHPLAN_WORLD_ETSI7 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI}, /* 0x49, RTW_CHPLAN_WORLD_ETSI8 */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4A, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4B, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4C, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4D, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4E, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4F, */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI9, TXPWR_LMT_ETSI}, /* 0x50, RTW_CHPLAN_WORLD_ETSI9 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI10, TXPWR_LMT_ETSI}, /* 0x51, RTW_CHPLAN_WORLD_ETSI10 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI11, TXPWR_LMT_ETSI}, /* 0x52, RTW_CHPLAN_WORLD_ETSI11 */ - {RTW_RD_2G_FCC1, RTW_RD_5G_NCC4, TXPWR_LMT_FCC}, /* 0x53, RTW_CHPLAN_FCC1_NCC4 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI12, TXPWR_LMT_ETSI}, /* 0x54, RTW_CHPLAN_WORLD_ETSI12 */ - {RTW_RD_2G_FCC1, RTW_RD_5G_FCC9, TXPWR_LMT_FCC}, /* 0x55, RTW_CHPLAN_FCC1_FCC9 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI13, TXPWR_LMT_ETSI}, /* 0x56, RTW_CHPLAN_WORLD_ETSI13 */ - {RTW_RD_2G_FCC1, RTW_RD_5G_FCC10, TXPWR_LMT_FCC}, /* 0x57, RTW_CHPLAN_FCC1_FCC10 */ - {RTW_RD_2G_MKK2, RTW_RD_5G_MKK4, TXPWR_LMT_MKK}, /* 0x58, RTW_CHPLAN_MKK2_MKK4 */ - {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI14, TXPWR_LMT_ETSI}, /* 0x59, RTW_CHPLAN_WORLD_ETSI14 */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5A, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5B, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5C, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5D, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5E, */ - {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5F, */ - {RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC}, /* 0x60, RTW_CHPLAN_FCC1_FCC5 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x20, RTW_CHPLAN_WORLD_NULL */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x21, RTW_CHPLAN_ETSI1_NULL */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NULL, TXPWR_LMT_FCC), /* 0x22, RTW_CHPLAN_FCC1_NULL */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x23, RTW_CHPLAN_MKK1_NULL */ + CHPLAN_ENT(RTW_RD_2G_ETSI2, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x24, RTW_CHPLAN_ETSI2_NULL */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC1, TXPWR_LMT_FCC), /* 0x25, RTW_CHPLAN_FCC1_FCC1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x26, RTW_CHPLAN_WORLD_ETSI1 */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK1, TXPWR_LMT_MKK), /* 0x27, RTW_CHPLAN_MKK1_MKK1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_KCC1, TXPWR_LMT_KCC), /* 0x28, RTW_CHPLAN_WORLD_KCC1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x29, RTW_CHPLAN_WORLD_FCC2 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_NULL, TXPWR_LMT_FCC), /* 0x2A, RTW_CHPLAN_FCC2_NULL */ + CHPLAN_ENT(RTW_RD_2G_IC1, RTW_RD_5G_IC2, TXPWR_LMT_IC), /* 0x2B, RTW_CHPLAN_IC1_IC2 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2F, */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC3, TXPWR_LMT_FCC), /* 0x30, RTW_CHPLAN_WORLD_FCC3 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC4, TXPWR_LMT_FCC), /* 0x31, RTW_CHPLAN_WORLD_FCC4 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x32, RTW_CHPLAN_WORLD_FCC5 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC6, TXPWR_LMT_FCC), /* 0x33, RTW_CHPLAN_WORLD_FCC6 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x34, RTW_CHPLAN_FCC1_FCC7 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI2, TXPWR_LMT_ETSI), /* 0x35, RTW_CHPLAN_WORLD_ETSI2 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI3, TXPWR_LMT_ETSI), /* 0x36, RTW_CHPLAN_WORLD_ETSI3 */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK2, TXPWR_LMT_MKK), /* 0x37, RTW_CHPLAN_MKK1_MKK2 */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK3, TXPWR_LMT_MKK), /* 0x38, RTW_CHPLAN_MKK1_MKK3 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC1, TXPWR_LMT_FCC), /* 0x39, RTW_CHPLAN_FCC1_NCC1 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3A, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3B, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3F, */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC), /* 0x40, RTW_CHPLAN_FCC1_NCC2 */ + CHPLAN_ENT(RTW_RD_2G_GLOBAL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x41, RTW_CHPLAN_GLOBAL_NULL */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI4, TXPWR_LMT_ETSI), /* 0x42, RTW_CHPLAN_ETSI1_ETSI4 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x43, RTW_CHPLAN_FCC1_FCC2 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC3, TXPWR_LMT_FCC), /* 0x44, RTW_CHPLAN_FCC1_NCC3 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI5, TXPWR_LMT_ETSI), /* 0x45, RTW_CHPLAN_WORLD_ETSI5 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC8, TXPWR_LMT_FCC), /* 0x46, RTW_CHPLAN_FCC1_FCC8 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI6, TXPWR_LMT_ETSI), /* 0x47, RTW_CHPLAN_WORLD_ETSI6 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI7, TXPWR_LMT_ETSI), /* 0x48, RTW_CHPLAN_WORLD_ETSI7 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI), /* 0x49, RTW_CHPLAN_WORLD_ETSI8 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4A, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4B, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4F, */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI9, TXPWR_LMT_ETSI), /* 0x50, RTW_CHPLAN_WORLD_ETSI9 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI10, TXPWR_LMT_ETSI), /* 0x51, RTW_CHPLAN_WORLD_ETSI10 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI11, TXPWR_LMT_ETSI), /* 0x52, RTW_CHPLAN_WORLD_ETSI11 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC4, TXPWR_LMT_FCC), /* 0x53, RTW_CHPLAN_FCC1_NCC4 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI12, TXPWR_LMT_ETSI), /* 0x54, RTW_CHPLAN_WORLD_ETSI12 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC9, TXPWR_LMT_FCC), /* 0x55, RTW_CHPLAN_FCC1_FCC9 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI13, TXPWR_LMT_ETSI), /* 0x56, RTW_CHPLAN_WORLD_ETSI13 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC10, TXPWR_LMT_FCC), /* 0x57, RTW_CHPLAN_FCC1_FCC10 */ + CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK4, TXPWR_LMT_MKK), /* 0x58, RTW_CHPLAN_MKK2_MKK4 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI14, TXPWR_LMT_ETSI), /* 0x59, RTW_CHPLAN_WORLD_ETSI14 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5A, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5B, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5F, */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x60, RTW_CHPLAN_FCC1_FCC5 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x61, RTW_CHPLAN_FCC2_FCC7 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC1, TXPWR_LMT_FCC), /* 0x62, RTW_CHPLAN_FCC2_FCC1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI15, TXPWR_LMT_ETSI), /* 0x63, RTW_CHPLAN_WORLD_ETSI15 */ + CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK5, TXPWR_LMT_MKK), /* 0x64, RTW_CHPLAN_MKK2_MKK5 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI16, TXPWR_LMT_ETSI), /* 0x65, RTW_CHPLAN_ETSI1_ETSI16 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC14, TXPWR_LMT_FCC), /* 0x66, RTW_CHPLAN_FCC1_FCC14 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x67, RTW_CHPLAN_FCC1_FCC12 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC14, TXPWR_LMT_FCC), /* 0x68, RTW_CHPLAN_FCC2_FCC14 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x69, RTW_CHPLAN_FCC2_FCC12 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI17, TXPWR_LMT_ETSI), /* 0x6A, RTW_CHPLAN_ETSI1_ETSI17 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC16, TXPWR_LMT_FCC), /* 0x6B, RTW_CHPLAN_WORLD_FCC16 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC13, TXPWR_LMT_FCC), /* 0x6C, RTW_CHPLAN_WORLD_FCC13 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC15, TXPWR_LMT_FCC), /* 0x6D, RTW_CHPLAN_FCC2_FCC15 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x6E, RTW_CHPLAN_WORLD_FCC12 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI), /* 0x6F, RTW_CHPLAN_NULL_ETSI8 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI18, TXPWR_LMT_ETSI), /* 0x70, RTW_CHPLAN_NULL_ETSI18 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI17, TXPWR_LMT_ETSI), /* 0x71, RTW_CHPLAN_NULL_ETSI17 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI19, TXPWR_LMT_ETSI), /* 0x72, RTW_CHPLAN_NULL_ETSI19 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x73, RTW_CHPLAN_WORLD_FCC7 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC17, TXPWR_LMT_FCC), /* 0x74, RTW_CHPLAN_FCC2_FCC17 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI20, TXPWR_LMT_ETSI), /* 0x75, RTW_CHPLAN_WORLD_ETSI20 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC11, TXPWR_LMT_FCC), /* 0x76, RTW_CHPLAN_FCC2_FCC11 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI21, TXPWR_LMT_ETSI), /* 0x77, RTW_CHPLAN_WORLD_ETSI21 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC18, TXPWR_LMT_FCC), /* 0x78, RTW_CHPLAN_FCC1_FCC18 */ }; -static RT_CHANNEL_PLAN_MAP RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE = { - RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_FCC /* 0x7F, Realtek Define */ -}; +static RT_CHANNEL_PLAN_MAP RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE = + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_FCC); /* 0x7F, Realtek Define */ bool rtw_chplan_is_empty(u8 id) { @@ -314,17 +356,351 @@ bool rtw_chplan_is_empty(u8 id) chplan_map = &RTW_ChannelPlanMap[id]; if (chplan_map->Index2G == RTW_RD_2G_NULL - && chplan_map->Index5G == RTW_RD_5G_NULL) + #ifdef CONFIG_IEEE80211_BAND_5GHZ + && chplan_map->Index5G == RTW_RD_5G_NULL + #endif + ) return _TRUE; return _FALSE; } +bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch) +{ + int i; + + for (i = 0; i < MAX_CHANNEL_NUM; i++) { + if (regsty->excl_chs[i] == 0) + break; + if (regsty->excl_chs[i] == ch) + return _TRUE; + } + return _FALSE; +} + +inline u8 rtw_rd_5g_band1_passive(u8 rtw_rd_5g) +{ + u8 passive = 0; + + switch (rtw_rd_5g) { + case RTW_RD_5G_FCC13: + case RTW_RD_5G_FCC16: + case RTW_RD_5G_ETSI18: + case RTW_RD_5G_ETSI19: + case RTW_RD_5G_WORLD: + passive = 1; + }; + + return passive; +} + +inline u8 rtw_rd_5g_band4_passive(u8 rtw_rd_5g) +{ + u8 passive = 0; + + switch (rtw_rd_5g) { + case RTW_RD_5G_MKK5: + case RTW_RD_5G_ETSI16: + case RTW_RD_5G_ETSI18: + case RTW_RD_5G_ETSI19: + case RTW_RD_5G_WORLD: + passive = 1; + }; + + return passive; +} + +static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set + , struct p2p_channels *channel_list) +{ + struct registry_priv *regsty = adapter_to_regsty(padapter); + + struct p2p_oper_class_map op_class[] = { + { IEEE80211G, 81, 1, 13, 1, BW20 }, + { IEEE80211G, 82, 14, 14, 1, BW20 }, +#if 0 /* Do not enable HT40 on 2 GHz */ + { IEEE80211G, 83, 1, 9, 1, BW40PLUS }, + { IEEE80211G, 84, 5, 13, 1, BW40MINUS }, +#endif + { IEEE80211A, 115, 36, 48, 4, BW20 }, + { IEEE80211A, 116, 36, 44, 8, BW40PLUS }, + { IEEE80211A, 117, 40, 48, 8, BW40MINUS }, + { IEEE80211A, 124, 149, 161, 4, BW20 }, + { IEEE80211A, 125, 149, 169, 4, BW20 }, + { IEEE80211A, 126, 149, 157, 8, BW40PLUS }, + { IEEE80211A, 127, 153, 161, 8, BW40MINUS }, + { -1, 0, 0, 0, 0, BW20 } + }; + + int cla, op; + + cla = 0; + + for (op = 0; op_class[op].op_class; op++) { + u8 ch; + struct p2p_oper_class_map *o = &op_class[op]; + struct p2p_reg_class *reg = NULL; + + for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) { + if (rtw_chset_search_ch(channel_set, ch) == -1) + continue; + + if ((padapter->registrypriv.ht_enable == 0) && (o->inc == 8)) + continue; + + if ((REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)) && + ((o->bw == BW40MINUS) || (o->bw == BW40PLUS))) + continue; + + if (reg == NULL) { + reg = &channel_list->reg_class[cla]; + cla++; + reg->reg_class = o->op_class; + reg->channels = 0; + } + reg->channel[reg->channels] = ch; + reg->channels++; + } + } + channel_list->reg_classes = cla; + +} + +static u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + struct registry_priv *regsty = adapter_to_regsty(padapter); + u8 index, chanset_size = 0; + u8 b5GBand = _FALSE, b2_4GBand = _FALSE; + u8 Index2G = 0, Index5G = 0; + int i; + + if (!rtw_is_channel_plan_valid(ChannelPlan)) { + RTW_ERR("ChannelPlan ID 0x%02X error !!!!!\n", ChannelPlan); + return chanset_size; + } + + _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); + + if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_2G)) + b2_4GBand = _TRUE; + + if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_5G)) + b5GBand = _TRUE; + + if (b2_4GBand == _FALSE && b5GBand == _FALSE) { + RTW_WARN("HW band_cap has no intersection with SW wireless_mode setting\n"); + return chanset_size; + } + + if (b2_4GBand) { + if (ChannelPlan == RTW_CHPLAN_REALTEK_DEFINE) + Index2G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index2G; + else + Index2G = RTW_ChannelPlanMap[ChannelPlan].Index2G; + + for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan2G[Index2G]); index++) { + if (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan2G[Index2G], index)) == _TRUE) + continue; + + if (chanset_size >= MAX_CHANNEL_NUM) { + RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM); + break; + } + + channel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan2G[Index2G], index); + + if (ChannelPlan == RTW_CHPLAN_GLOBAL_DOAMIN + || Index2G == RTW_RD_2G_GLOBAL + ) { + /* Channel 1~11 is active, and 12~14 is passive */ + if (channel_set[chanset_size].ChannelNum >= 1 && channel_set[chanset_size].ChannelNum <= 11) + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + else if ((channel_set[chanset_size].ChannelNum >= 12 && channel_set[chanset_size].ChannelNum <= 14)) + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + } else if (ChannelPlan == RTW_CHPLAN_WORLD_WIDE_13 + || ChannelPlan == RTW_CHPLAN_WORLD_WIDE_5G + || Index2G == RTW_RD_2G_WORLD + ) { + /* channel 12~13, passive scan */ + if (channel_set[chanset_size].ChannelNum <= 11) + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + else + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + } else + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + + chanset_size++; + } + } + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (b5GBand) { + if (ChannelPlan == RTW_CHPLAN_REALTEK_DEFINE) + Index5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index5G; + else + Index5G = RTW_ChannelPlanMap[ChannelPlan].Index5G; + + for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan5G[Index5G]); index++) { + if (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan5G[Index5G], index)) == _TRUE) + continue; + #ifndef CONFIG_DFS + if (rtw_is_dfs_ch(CH_LIST_CH(RTW_ChannelPlan5G[Index5G], index))) + continue; + #endif + + if (chanset_size >= MAX_CHANNEL_NUM) { + RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM); + break; + } + + channel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan5G[Index5G], index); + + if ((ChannelPlan == RTW_CHPLAN_WORLD_WIDE_5G) /* all channels passive */ + || (rtw_is_5g_band1(channel_set[chanset_size].ChannelNum) + && rtw_rd_5g_band1_passive(Index5G)) /* band1 passive */ + || (rtw_is_5g_band4(channel_set[chanset_size].ChannelNum) + && rtw_rd_5g_band4_passive(Index5G)) /* band4 passive */ + || (rtw_is_dfs_ch(channel_set[chanset_size].ChannelNum)) /* DFS channel(band2, 3) passive */ + ) + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + else + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + + chanset_size++; + } + } + + #ifdef CONFIG_DFS_MASTER + for (i = 0; i < chanset_size; i++) + channel_set[i].non_ocp_end_time = rtw_get_current_time(); + #endif +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ + + if (chanset_size) + RTW_INFO(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, ch num:%d\n" + , FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size); + else + RTW_WARN(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, final chset has no channel\n" + , FUNC_ADPT_ARG(padapter), ChannelPlan); + + return chanset_size; +} + +#ifdef CONFIG_TXPWR_LIMIT +void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl) +{ + u8 regd; + u8 regd_name; + struct regd_exc_ent *exc; + struct txpwr_lmt_ent *ent; + _irqL irqL; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + rfctl->regd_name = NULL; + + if (rfctl->txpwr_regd_num == 0) { + RTW_PRINT("there is no any txpwr_regd\n"); + goto release_lock; + } + + /* search from exception mapping */ + exc = _rtw_regd_exc_search(rfctl + , rfctl->country_ent ? rfctl->country_ent->alpha2 : NULL + , rfctl->ChannelPlan); + if (exc) { + u8 has_country = (exc->country[0] == '\0' && exc->country[1] == '\0') ? 0 : 1; + + if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_NONE)) == 0) + rfctl->regd_name = regd_str(TXPWR_LMT_NONE); + else if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_WW)) == 0) + rfctl->regd_name = regd_str(TXPWR_LMT_WW); + else { + ent = _rtw_txpwr_lmt_get_by_name(rfctl, exc->regd_name); + if (ent) + rfctl->regd_name = ent->regd_name; + } + + RTW_PRINT("exception mapping country:%c%c domain:0x%02x to%s regd_name:%s\n" + , has_country ? exc->country[0] : '0' + , has_country ? exc->country[1] : '0' + , exc->domain + , rfctl->regd_name ? "" : " unknown" + , exc->regd_name + ); + if (rfctl->regd_name) + goto release_lock; + } + + /* follow default channel plan mapping */ + if (rfctl->ChannelPlan == RTW_CHPLAN_REALTEK_DEFINE) + regd = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd; + else + regd = RTW_ChannelPlanMap[rfctl->ChannelPlan].regd; + + if (regd == TXPWR_LMT_NONE) + rfctl->regd_name = regd_str(TXPWR_LMT_NONE); + else if (regd == TXPWR_LMT_WW) + rfctl->regd_name = regd_str(TXPWR_LMT_WW); + else { + ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd)); + if (ent) + rfctl->regd_name = ent->regd_name; + } + + RTW_PRINT("default mapping domain:0x%02x to%s regd_name:%s\n" + , rfctl->ChannelPlan + , rfctl->regd_name ? "" : " unknown" + , regd_str(regd) + ); + if (rfctl->regd_name) + goto release_lock; + + switch (regd) { + /* + * To support older chips without IC and KCC regd: + * IC not found, use FCC instead + * KCC not found, use ETSI instead + */ + case TXPWR_LMT_IC: + case TXPWR_LMT_KCC: + if (regd == TXPWR_LMT_IC) + regd = TXPWR_LMT_FCC; + else if (regd == TXPWR_LMT_KCC) + regd = TXPWR_LMT_ETSI; + ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd)); + if (ent) + rfctl->regd_name = ent->regd_name; + RTW_PRINT("alternate regd_name:%s %s\n" + , regd_str(regd) + , rfctl->regd_name ? "is used" : "not found" + ); + if (rfctl->regd_name) + break; + default: + rfctl->regd_name = regd_str(TXPWR_LMT_WW); + RTW_PRINT("assign %s for default case\n", regd_str(TXPWR_LMT_WW)); + break; + }; + +release_lock: + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); +} +#endif /* CONFIG_TXPWR_LIMIT */ + void rtw_rfctl_init(_adapter *adapter) { struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - _rtw_memset(rfctl, 0, sizeof(*rfctl)); + rfctl->max_chan_nums = init_channel_set(adapter, rfctl->ChannelPlan, rfctl->channel_set); + init_channel_list(adapter, rfctl->channel_set, &rfctl->channel_list); + +#ifdef CONFIG_TXPWR_LIMIT + _rtw_mutex_init(&rfctl->txpwr_lmt_mutex); + _rtw_init_listhead(&rfctl->reg_exc_list); + _rtw_init_listhead(&rfctl->txpwr_lmt_list); +#endif #ifdef CONFIG_DFS_MASTER rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED; @@ -333,6 +709,21 @@ void rtw_rfctl_init(_adapter *adapter) #endif } +void rtw_rfctl_deinit(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + +#ifdef CONFIG_TXPWR_LIMIT + rtw_regd_exc_list_free(rfctl); + rtw_txpwr_lmt_list_free(rfctl); + _rtw_mutex_free(&rfctl->txpwr_lmt_mutex); +#endif + +#ifdef CONFIG_DFS_MASTER + /* TODO: dfs_master_timer */ +#endif +} + #ifdef CONFIG_DFS_MASTER /* * called in rtw_dfs_master_enable() @@ -412,8 +803,8 @@ bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 } if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch - , rfctl->radar_detect_bw, rfctl->radar_detect_offset - , &r_hi, &r_lo) == _FALSE) { + , rfctl->radar_detect_bw, rfctl->radar_detect_offset + , &r_hi, &r_lo) == _FALSE) { rtw_warn_on(1); goto exit; } @@ -428,9 +819,9 @@ bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl) { return _rtw_rfctl_overlap_radar_detect_ch(rfctl - , rfctl_to_dvobj(rfctl)->oper_channel - , rfctl_to_dvobj(rfctl)->oper_bwmode - , rfctl_to_dvobj(rfctl)->oper_ch_offset); + , rfctl_to_dvobj(rfctl)->oper_channel + , rfctl_to_dvobj(rfctl)->oper_bwmode + , rfctl_to_dvobj(rfctl)->oper_ch_offset); } bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl) @@ -447,7 +838,7 @@ bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) goto exit; - for (i = 0; ch_set[i].ChannelNum != 0; i++) { + for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) { if (!rtw_ch2freq(ch_set[i].ChannelNum)) { rtw_warn_on(1); continue; @@ -457,8 +848,8 @@ bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) continue; if (lo <= rtw_ch2freq(ch_set[i].ChannelNum) - && rtw_ch2freq(ch_set[i].ChannelNum) <= hi - ) { + && rtw_ch2freq(ch_set[i].ChannelNum) <= hi + ) { ret = _TRUE; break; } @@ -480,7 +871,7 @@ u32 rtw_chset_get_ch_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset current_time = rtw_get_current_time(); - for (i = 0; ch_set[i].ChannelNum != 0; i++) { + for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) { if (!rtw_ch2freq(ch_set[i].ChannelNum)) { rtw_warn_on(1); continue; @@ -490,8 +881,8 @@ u32 rtw_chset_get_ch_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset continue; if (lo <= rtw_ch2freq(ch_set[i].ChannelNum) - && rtw_ch2freq(ch_set[i].ChannelNum) <= hi - ) { + && rtw_ch2freq(ch_set[i].ChannelNum) <= hi + ) { if (rtw_systime_to_ms(ch_set[i].non_ocp_end_time - current_time) > ms) ms = rtw_systime_to_ms(ch_set[i].non_ocp_end_time - current_time); } @@ -517,15 +908,15 @@ static void _rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) goto exit; - for (i = 0; ch_set[i].ChannelNum != 0; i++) { + for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) { if (!rtw_ch2freq(ch_set[i].ChannelNum)) { rtw_warn_on(1); continue; } if (lo <= rtw_ch2freq(ch_set[i].ChannelNum) - && rtw_ch2freq(ch_set[i].ChannelNum) <= hi - ) { + && rtw_ch2freq(ch_set[i].ChannelNum) <= hi + ) { if (ms >= 0) ch_set[i].non_ocp_end_time = rtw_get_current_time() + rtw_ms_to_systime(ms); else @@ -555,8 +946,8 @@ u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non u32 cac_ms; u8 in_rd_range = 0; /* if in current radar detection range*/ - if (rtw_chset_is_ch_non_ocp(mlmeext->channel_set, ch, bw, offset)) - non_ocp_ms = rtw_chset_get_ch_non_ocp_ms(mlmeext->channel_set, ch, bw, offset); + if (rtw_chset_is_ch_non_ocp(rfctl->channel_set, ch, bw, offset)) + non_ocp_ms = rtw_chset_get_ch_non_ocp_ms(rfctl->channel_set, ch, bw, offset); else non_ocp_ms = 0; @@ -577,7 +968,7 @@ u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non in_rd_range = 1; } - if (!rtw_is_dfs_ch(ch, bw, offset)) + if (!rtw_is_dfs_chbw(ch, bw, offset)) cac_ms = 0; else if (in_rd_range && !non_ocp_ms) { if (IS_CH_WAITING(rfctl)) @@ -604,12 +995,12 @@ void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset) u32 cac_ms; rtw_get_ch_waiting_ms(adapter - , ch - , bw - , offset - , &non_ocp_ms - , &cac_ms - ); + , ch + , bw + , offset + , &non_ocp_ms + , &cac_ms + ); rfctl->cac_start_time = rtw_get_current_time() + rtw_ms_to_systime(non_ocp_ms); rfctl->cac_end_time = rfctl->cac_start_time + rtw_ms_to_systime(cac_ms); @@ -622,6 +1013,7 @@ void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset) if (rfctl->cac_end_time == RTW_CAC_STOPPED) rfctl->cac_end_time++; } +#endif /* CONFIG_DFS_MASTER */ /* choose channel with shortest waiting (non ocp + cac) time */ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset, u8 d_flags) @@ -630,7 +1022,6 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 #define DBG_CHOOSE_SHORTEST_WAITING_CH 0 #endif - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); struct registry_priv *regsty = adapter_to_regsty(adapter); u8 ch, bw, offset; @@ -648,12 +1039,12 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 if (!hal_is_bw_support(adapter, bw)) continue; - for (i = 0; i < mlmeext->max_chan_nums; i++) { - u32 non_ocp_ms; - u32 cac_ms; - u32 waiting_ms; + for (i = 0; i < rfctl->max_chan_nums; i++) { + u32 non_ocp_ms = 0; + u32 cac_ms = 0; + u32 waiting_ms = 0; - ch = mlmeext->channel_set[i].ChannelNum; + ch = rfctl->channel_set[i].ChannelNum; if ((d_flags & RTW_CHF_2G) && ch <= 14) continue; @@ -672,34 +1063,36 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 if (!rtw_get_offset_by_chbw(ch, bw, &offset)) continue; - if (!rtw_chset_is_chbw_valid(mlmeext->channel_set, ch, bw, offset)) + if (!rtw_chset_is_chbw_valid(rfctl->channel_set, ch, bw, offset)) continue; - if ((d_flags & RTW_CHF_NON_OCP) && rtw_chset_is_ch_non_ocp(mlmeext->channel_set, ch, bw, offset)) + if ((d_flags & RTW_CHF_NON_OCP) && rtw_chset_is_ch_non_ocp(rfctl->channel_set, ch, bw, offset)) continue; - if ((d_flags & RTW_CHF_DFS) && rtw_is_dfs_ch(ch, bw, offset)) + if ((d_flags & RTW_CHF_DFS) && rtw_is_dfs_chbw(ch, bw, offset)) continue; if ((d_flags & RTW_CHF_LONG_CAC) && rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(adapter))) continue; - if ((d_flags & RTW_CHF_NON_DFS) && !rtw_is_dfs_ch(ch, bw, offset)) + if ((d_flags & RTW_CHF_NON_DFS) && !rtw_is_dfs_chbw(ch, bw, offset)) continue; if ((d_flags & RTW_CHF_NON_LONG_CAC) && !rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(adapter))) continue; + #ifdef CONFIG_DFS_MASTER waiting_ms = rtw_get_ch_waiting_ms(adapter, ch, bw, offset, &non_ocp_ms, &cac_ms); + #endif if (DBG_CHOOSE_SHORTEST_WAITING_CH) RTW_INFO(FUNC_ADPT_FMT":%u,%u,%u %u(non_ocp:%u, cac:%u)\n" , FUNC_ADPT_ARG(adapter), ch, bw, offset, waiting_ms, non_ocp_ms, cac_ms); if (ch_c == 0 - || min_waiting_ms > waiting_ms - || (min_waiting_ms == waiting_ms && bw > bw_c) /* wider bw first */ - ) { + || min_waiting_ms > waiting_ms + || (min_waiting_ms == waiting_ms && bw > bw_c) /* wider bw first */ + ) { ch_c = ch; bw_c = bw; offset_c = offset; @@ -723,14 +1116,13 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 return _FALSE; } -#endif /* CONFIG_DFS_MASTER */ void dump_country_chplan(void *sel, const struct country_chplan *ent) { _RTW_PRINT_SEL(sel, "\"%c%c\", 0x%02X%s\n" - , ent->alpha2[0], ent->alpha2[1], ent->chplan - , COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : "" - ); + , ent->alpha2[0], ent->alpha2[1], ent->chplan + , COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : "" + ); } void dump_country_chplan_map(void *sel) @@ -776,25 +1168,27 @@ void dump_chplan_test(void *sel) /* check invalid channel */ for (i = 0; i < RTW_RD_2G_MAX; i++) { - for (j = 0; j < RTW_ChannelPlan2G[i].Len; j++) { - if (rtw_ch2freq(RTW_ChannelPlan2G[i].Channel[j]) == 0) - RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", RTW_ChannelPlan2G[i].Channel[j], i, j); + for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan2G[i]); j++) { + if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan2G[i], j)) == 0) + RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan2G[i], j), i, j); } } +#ifdef CONFIG_IEEE80211_BAND_5GHZ for (i = 0; i < RTW_RD_5G_MAX; i++) { - for (j = 0; j < RTW_ChannelPlan5G[i].Len; j++) { - if (rtw_ch2freq(RTW_ChannelPlan5G[i].Channel[j]) == 0) - RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", RTW_ChannelPlan5G[i].Channel[j], i, j); + for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan5G[i]); j++) { + if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan5G[i], j)) == 0) + RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan5G[i], j), i, j); } } +#endif } void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set) { u8 i; - for (i = 0; ch_set[i].ChannelNum != 0; i++) { + for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) { RTW_PRINT_SEL(sel, "ch:%3u, freq:%u, scan_type:%d" , ch_set[i].ChannelNum, rtw_ch2freq(ch_set[i].ChannelNum), ch_set[i].ScanType); @@ -803,7 +1197,7 @@ void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set) #endif #ifdef CONFIG_DFS_MASTER - if (rtw_is_dfs_ch(ch_set[i].ChannelNum, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE)) { + if (rtw_is_dfs_ch(ch_set[i].ChannelNum)) { if (CH_IS_NON_OCP(&ch_set[i])) _RTW_PRINT_SEL(sel, ", non_ocp:%d" , rtw_systime_to_ms(ch_set[i].non_ocp_end_time - rtw_get_current_time())); @@ -820,19 +1214,23 @@ void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set) void dump_cur_chset(void *sel, _adapter *adapter) { - struct mlme_priv *mlme = &adapter->mlmepriv; - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); struct registry_priv *regsty = adapter_to_regsty(adapter); HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); int i; - if (mlme->country_ent) - dump_country_chplan(sel, mlme->country_ent); + if (rfctl->country_ent) + dump_country_chplan(sel, rfctl->country_ent); else - RTW_PRINT_SEL(sel, "chplan:0x%02X\n", mlme->ChannelPlan); + RTW_PRINT_SEL(sel, "chplan:0x%02X\n", rfctl->ChannelPlan); - RTW_PRINT_SEL(sel, "2G_PLS:%u, 5G_PLS:%u\n" - , hal_data->Regulation2_4G, hal_data->Regulation5G); +#ifdef CONFIG_TXPWR_LIMIT + RTW_PRINT_SEL(sel, "PLS regd:%s\n", rfctl->regd_name); +#endif + +#ifdef CONFIG_DFS_MASTER + RTW_PRINT_SEL(sel, "dfs_domain:%u\n", rtw_odm_get_dfs_domain(adapter)); +#endif for (i = 0; i < MAX_CHANNEL_NUM; i++) if (regsty->excl_chs[i] != 0) @@ -848,7 +1246,7 @@ void dump_cur_chset(void *sel, _adapter *adapter) RTW_PRINT_SEL(sel, "\n"); } - dump_chset(sel, mlmeext->channel_set); + dump_chset(sel, rfctl->channel_set); } /* @@ -858,17 +1256,19 @@ void dump_cur_chset(void *sel, _adapter *adapter) * * return the index of channel_num in channel_set, -1 if not found */ -int rtw_ch_set_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch) +int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch) { int i; - for (i = 0; ch_set[i].ChannelNum != 0; i++) { + + if (ch == 0) + return -1; + + for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) { if (ch == ch_set[i].ChannelNum) - break; + return i; } - if (i >= ch_set[i].ChannelNum) - return -1; - return i; + return -1; } /* @@ -896,7 +1296,7 @@ u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) for (i = 0; i < op_ch_num; i++) { if (0) RTW_INFO("%u,%u,%u - cch:%u, bw:%u, op_ch:%u\n", ch, bw, offset, cch, bw, *(op_chs + i)); - if (rtw_ch_set_search_ch(ch_set, *(op_chs + i)) == -1) + if (rtw_chset_search_ch(ch_set, *(op_chs + i)) == -1) break; } @@ -917,9 +1317,9 @@ u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) bool rtw_mlme_band_check(_adapter *adapter, const u32 ch) { if (adapter->setband == WIFI_FREQUENCY_BAND_AUTO /* 2.4G and 5G */ - || (adapter->setband == WIFI_FREQUENCY_BAND_2GHZ && ch < 35) /* 2.4G only */ - || (adapter->setband == WIFI_FREQUENCY_BAND_5GHZ && ch > 35) /* 5G only */ - ) + || (adapter->setband == WIFI_FREQUENCY_BAND_2GHZ && ch < 35) /* 2.4G only */ + || (adapter->setband == WIFI_FREQUENCY_BAND_5GHZ && ch > 35) /* 5G only */ + ) return _TRUE; return _FALSE; } @@ -1055,201 +1455,16 @@ static void init_mlme_ext_priv_value(_adapter *padapter) pmlmeext->action_public_dialog_token = 0xff; } -static int has_channel(RT_CHANNEL_INFO *channel_set, - u8 chanset_size, - u8 chan) -{ - int i; - - for (i = 0; i < chanset_size; i++) { - if (channel_set[i].ChannelNum == chan) - return 1; - } - - return 0; -} - -static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set, - u8 chanset_size, - struct p2p_channels *channel_list) -{ - struct registry_priv *regsty = adapter_to_regsty(padapter); - - struct p2p_oper_class_map op_class[] = { - { IEEE80211G, 81, 1, 13, 1, BW20 }, - { IEEE80211G, 82, 14, 14, 1, BW20 }, -#if 0 /* Do not enable HT40 on 2 GHz */ - { IEEE80211G, 83, 1, 9, 1, BW40PLUS }, - { IEEE80211G, 84, 5, 13, 1, BW40MINUS }, -#endif - { IEEE80211A, 115, 36, 48, 4, BW20 }, - { IEEE80211A, 116, 36, 44, 8, BW40PLUS }, - { IEEE80211A, 117, 40, 48, 8, BW40MINUS }, - { IEEE80211A, 124, 149, 161, 4, BW20 }, - { IEEE80211A, 125, 149, 169, 4, BW20 }, - { IEEE80211A, 126, 149, 157, 8, BW40PLUS }, - { IEEE80211A, 127, 153, 161, 8, BW40MINUS }, - { -1, 0, 0, 0, 0, BW20 } - }; - - int cla, op; - - cla = 0; - - for (op = 0; op_class[op].op_class; op++) { - u8 ch; - struct p2p_oper_class_map *o = &op_class[op]; - struct p2p_reg_class *reg = NULL; - - for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) { - if (!has_channel(channel_set, chanset_size, ch)) - continue; - - if ((0 == padapter->registrypriv.ht_enable) && (8 == o->inc)) - continue; - - if ((REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)) && - ((BW40MINUS == o->bw) || (BW40PLUS == o->bw))) - continue; - - if (reg == NULL) { - reg = &channel_list->reg_class[cla]; - cla++; - reg->reg_class = o->op_class; - reg->channels = 0; - } - reg->channel[reg->channels] = ch; - reg->channels++; - } - } - channel_list->reg_classes = cla; - -} - -bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch) -{ - int i; - - for (i = 0; i < MAX_CHANNEL_NUM; i++) { - if (regsty->excl_chs[i] == 0) - break; - if (regsty->excl_chs[i] == ch) - return _TRUE; - } - return _FALSE; -} - -static u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set) +void init_mlme_ext_timer(_adapter *padapter) { - struct registry_priv *regsty = adapter_to_regsty(padapter); - u8 index, chanset_size = 0; - u8 b5GBand = _FALSE, b2_4GBand = _FALSE; - u8 Index2G = 0, Index5G = 0; - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); - int i; - - if (!rtw_is_channel_plan_valid(ChannelPlan)) { - RTW_ERR("ChannelPlan ID 0x%02X error !!!!!\n", ChannelPlan); - return chanset_size; - } - - _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); - - if (IsSupported24G(padapter->registrypriv.wireless_mode)) - b2_4GBand = _TRUE; - - if (IsSupported5G(padapter->registrypriv.wireless_mode)) - b5GBand = _TRUE; - - if (b2_4GBand) { - if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) - Index2G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index2G; - else - Index2G = RTW_ChannelPlanMap[ChannelPlan].Index2G; - - for (index = 0; index < RTW_ChannelPlan2G[Index2G].Len; index++) { - if (rtw_regsty_is_excl_chs(regsty, RTW_ChannelPlan2G[Index2G].Channel[index]) == _TRUE) - continue; - - channel_set[chanset_size].ChannelNum = RTW_ChannelPlan2G[Index2G].Channel[index]; - - if (RTW_CHPLAN_GLOBAL_DOAMIN == ChannelPlan - || RTW_CHPLAN_GLOBAL_NULL == ChannelPlan - ) { - /* Channel 1~11 is active, and 12~14 is passive */ - if (channel_set[chanset_size].ChannelNum >= 1 && channel_set[chanset_size].ChannelNum <= 11) - channel_set[chanset_size].ScanType = SCAN_ACTIVE; - else if ((channel_set[chanset_size].ChannelNum >= 12 && channel_set[chanset_size].ChannelNum <= 14)) - channel_set[chanset_size].ScanType = SCAN_PASSIVE; - } else if (RTW_CHPLAN_WORLD_WIDE_13 == ChannelPlan - || RTW_CHPLAN_WORLD_WIDE_5G == ChannelPlan - || RTW_RD_2G_WORLD == Index2G - ) { - /* channel 12~13, passive scan */ - if (channel_set[chanset_size].ChannelNum <= 11) - channel_set[chanset_size].ScanType = SCAN_ACTIVE; - else - channel_set[chanset_size].ScanType = SCAN_PASSIVE; - } else - channel_set[chanset_size].ScanType = SCAN_ACTIVE; - - chanset_size++; - } - } - - if (b5GBand) { - if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) - Index5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index5G; - else - Index5G = RTW_ChannelPlanMap[ChannelPlan].Index5G; - - for (index = 0; index < RTW_ChannelPlan5G[Index5G].Len; index++) { - if (rtw_regsty_is_excl_chs(regsty, RTW_ChannelPlan5G[Index5G].Channel[index]) == _TRUE) - continue; -#ifdef CONFIG_DFS - channel_set[chanset_size].ChannelNum = RTW_ChannelPlan5G[Index5G].Channel[index]; - if (channel_set[chanset_size].ChannelNum <= 48 - || channel_set[chanset_size].ChannelNum >= 149) { - if (RTW_CHPLAN_WORLD_WIDE_5G == ChannelPlan) /* passive scan for all 5G channels */ - channel_set[chanset_size].ScanType = SCAN_PASSIVE; - else - channel_set[chanset_size].ScanType = SCAN_ACTIVE; - } else - channel_set[chanset_size].ScanType = SCAN_PASSIVE; - chanset_size++; -#else /* CONFIG_DFS */ - if (RTW_ChannelPlan5G[Index5G].Channel[index] <= 48 - || RTW_ChannelPlan5G[Index5G].Channel[index] >= 149 - ) { - channel_set[chanset_size].ChannelNum = RTW_ChannelPlan5G[Index5G].Channel[index]; - if (RTW_CHPLAN_WORLD_WIDE_5G == ChannelPlan) /* passive scan for all 5G channels */ - channel_set[chanset_size].ScanType = SCAN_PASSIVE; - else - channel_set[chanset_size].ScanType = SCAN_ACTIVE; - RTW_INFO("%s(): channel_set[%d].ChannelNum = %d\n", __FUNCTION__, chanset_size, channel_set[chanset_size].ChannelNum); - chanset_size++; - } -#endif /* CONFIG_DFS */ - } - } - - if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) { - hal_data->Regulation2_4G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd; - hal_data->Regulation5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd; - } else { - hal_data->Regulation2_4G = RTW_ChannelPlanMap[ChannelPlan].regd; - hal_data->Regulation5G = RTW_ChannelPlanMap[ChannelPlan].regd; - } + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; -#ifdef CONFIG_DFS_MASTER - for (i = 0; i < chanset_size; i++) - channel_set[i].non_ocp_end_time = rtw_get_current_time(); + rtw_init_timer(&pmlmeext->survey_timer, padapter, survey_timer_hdl, padapter); + rtw_init_timer(&pmlmeext->link_timer, padapter, link_timer_hdl, padapter); +#ifdef CONFIG_RTW_80211R + rtw_init_timer(&pmlmeext->ft_link_timer, padapter, ft_link_timer_hdl, padapter); + rtw_init_timer(&pmlmeext->ft_roam_timer, padapter, ft_roam_timer_hdl, padapter); #endif - - RTW_INFO(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, ch num:%d\n" - , FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size); - - return chanset_size; } int init_mlme_ext_priv(_adapter *padapter) @@ -1276,8 +1491,6 @@ int init_mlme_ext_priv(_adapter *padapter) init_mlme_ap_info(padapter); #endif - pmlmeext->max_chan_nums = init_channel_set(padapter, pmlmepriv->ChannelPlan, pmlmeext->channel_set); - init_channel_list(padapter, pmlmeext->channel_set, pmlmeext->max_chan_nums, &pmlmeext->channel_list); pmlmeext->last_scan_time = 0; pmlmeext->mlmeext_init = _TRUE; @@ -1306,7 +1519,6 @@ void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext) if (rtw_is_drv_stopped(padapter)) { _cancel_timer_ex(&pmlmeext->survey_timer); _cancel_timer_ex(&pmlmeext->link_timer); - /* _cancel_timer_ex(&pmlmeext->ADDBA_timer); */ } } @@ -1352,20 +1564,17 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) #endif /* CONFIG_AP_MODE */ u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; u8 *pframe = precv_frame->u.hdr.rx_data; - struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, GetAddr2Ptr(pframe)); + struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(pframe)); struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, - ("+mgt_dispatcher: type(0x%x) subtype(0x%x)\n", - GetFrameType(pframe), GetFrameSubType(pframe))); #if 0 { u8 *pbuf; pbuf = GetAddr1Ptr(pframe); RTW_INFO("A1-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5)); - pbuf = GetAddr2Ptr(pframe); + pbuf = get_addr2_ptr(pframe); RTW_INFO("A2-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5)); pbuf = GetAddr3Ptr(pframe); RTW_INFO("A3-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5)); @@ -1373,7 +1582,6 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) #endif if (GetFrameType(pframe) != WIFI_MGT_TYPE) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("mgt_dispatcher: type(0x%x) error!\n", GetFrameType(pframe))); return; } @@ -1384,20 +1592,19 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) ptable = mlme_sta_tbl; - index = GetFrameSubType(pframe) >> 4; + index = get_frame_sub_type(pframe) >> 4; #ifdef CONFIG_TDLS if ((index << 4) == WIFI_ACTION) { /* category==public (4), action==TDLS_DISCOVERY_RESPONSE */ if (*(pframe + 24) == RTW_WLAN_CATEGORY_PUBLIC && *(pframe + 25) == TDLS_DISCOVERY_RESPONSE) { - RTW_INFO("[TDLS] Recv %s from "MAC_FMT"\n", rtw_tdls_action_txt(TDLS_DISCOVERY_RESPONSE), MAC_ARG(GetAddr2Ptr(pframe))); + RTW_INFO("[TDLS] Recv %s from "MAC_FMT"\n", rtw_tdls_action_txt(TDLS_DISCOVERY_RESPONSE), MAC_ARG(get_addr2_ptr(pframe))); On_TDLS_Dis_Rsp(padapter, precv_frame); } } #endif /* CONFIG_TDLS */ if (index >= (sizeof(mlme_sta_tbl) / sizeof(struct mlme_handler))) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("Currently we do not support reserved sub-fr-type=%d\n", index)); return; } ptable += index; @@ -1417,13 +1624,12 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) #else if (GetRetry(pframe)) { - /* RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("drop due to decache!\n")); */ /* return; */ } #endif #ifdef CONFIG_AP_MODE - switch (GetFrameSubType(pframe)) { + switch (get_frame_sub_type(pframe)) { case WIFI_AUTH: if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ptable->func = &OnAuth; @@ -1476,21 +1682,23 @@ u32 p2p_listen_state_process(_adapter *padapter, unsigned char *da) #ifdef CONFIG_IOCTL_CFG80211 if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) { - if (padapter->cfg80211_wdinfo.is_ro_ch == _FALSE - || rtw_get_oper_ch(padapter) != padapter->wdinfo.listen_channel - || adapter_wdev_data(padapter)->p2p_enabled == _FALSE - || padapter->mlmepriv.wps_probe_resp_ie == NULL - || padapter->mlmepriv.p2p_probe_resp_ie == NULL - ) { + if (rtw_cfg80211_get_is_roch(padapter) == _FALSE + || rtw_get_oper_ch(padapter) != padapter->wdinfo.listen_channel + || adapter_wdev_data(padapter)->p2p_enabled == _FALSE + || padapter->mlmepriv.wps_probe_resp_ie == NULL + || padapter->mlmepriv.p2p_probe_resp_ie == NULL + ) { #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p, ", - adapter_wdev_data(padapter)->p2p_enabled, - padapter->mlmepriv.wps_probe_resp_ie, - padapter->mlmepriv.p2p_probe_resp_ie); - RTW_INFO("is_ro_ch:%d, op_ch:%d, p2p_listen_channel:%d\n", - padapter->cfg80211_wdinfo.is_ro_ch, - rtw_get_oper_ch(padapter), - padapter->wdinfo.listen_channel); + RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p\n" + , ADPT_ARG(padapter) + , adapter_wdev_data(padapter)->p2p_enabled + , padapter->mlmepriv.wps_probe_resp_ie + , padapter->mlmepriv.p2p_probe_resp_ie); + RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: is_ro_ch:%d, op_ch:%d, p2p_listen_channel:%d\n" + , ADPT_ARG(padapter) + , rtw_cfg80211_get_is_roch(padapter) + , rtw_get_oper_ch(padapter) + , padapter->wdinfo.listen_channel); #endif response = _FALSE; } @@ -1546,8 +1754,8 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) if ((pwdinfo->driver_interface == DRIVER_CFG80211) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_PROBE_REQ) == _TRUE) - ) { - rtw_cfg80211_rx_probe_request(padapter, pframe, len); + ) { + rtw_cfg80211_rx_probe_request(padapter, precv_frame); return _SUCCESS; } #endif /* CONFIG_IOCTL_CFG80211 */ @@ -1784,7 +1992,7 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_P2P if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) { if (_TRUE == pwdinfo->tx_prov_disc_info.benable) { - if (_rtw_memcmp(pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr2Ptr(pframe), ETH_ALEN)) { + if (_rtw_memcmp(pwdinfo->tx_prov_disc_info.peerIFAddr, get_addr2_ptr(pframe), ETH_ALEN)) { if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) { pwdinfo->tx_prov_disc_info.benable = _FALSE; issue_p2p_provision_request(padapter, @@ -1804,7 +2012,7 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) { if (_TRUE == pwdinfo->nego_req_info.benable) { RTW_INFO("[%s] P2P State is GONEGO ING!\n", __FUNCTION__); - if (_rtw_memcmp(pwdinfo->nego_req_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN)) { + if (_rtw_memcmp(pwdinfo->nego_req_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN)) { pwdinfo->nego_req_info.benable = _FALSE; issue_p2p_GO_request(padapter, pwdinfo->nego_req_info.peerDevAddr); } @@ -1812,7 +2020,7 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) { if (_TRUE == pwdinfo->invitereq_info.benable) { RTW_INFO("[%s] P2P_STATE_TX_INVITE_REQ!\n", __FUNCTION__); - if (_rtw_memcmp(pwdinfo->invitereq_info.peer_macaddr, GetAddr2Ptr(pframe), ETH_ALEN)) { + if (_rtw_memcmp(pwdinfo->invitereq_info.peer_macaddr, get_addr2_ptr(pframe), ETH_ALEN)) { pwdinfo->invitereq_info.benable = _FALSE; issue_p2p_invitation_request(padapter, pwdinfo->invitereq_info.peer_macaddr); } @@ -1829,7 +2037,7 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) #if 0 /* move to validate_recv_mgnt_frame */ if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) { if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { - psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); if (psta != NULL) psta->sta_stats.rx_mgnt_pkts++; } @@ -1840,6 +2048,51 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) } +/* for 11n Logo 4.2.31/4.2.32 */ +static void rtw_check_legacy_ap(_adapter *padapter, u8 *pframe, u32 len) +{ + + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if (!padapter->registrypriv.wifi_spec) + return; + + if(!MLME_IS_AP(padapter)) + return; + + + if (pmlmeext->bstart_bss == _TRUE) { + int left; + u16 capability; + unsigned char *pos; + struct rtw_ieee802_11_elems elems; + struct HT_info_element *pht_info = NULL; + u16 cur_op_mode; + + /* checking IEs */ + left = len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_; + pos = pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_; + if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) { + RTW_INFO("%s: parse fail for "MAC_FMT"\n", __func__, MAC_ARG(GetAddr3Ptr(pframe))); + return; + } + + cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK; + + /* for legacy ap */ + if (elems.ht_capabilities == NULL && elems.ht_capabilities_len == 0) { + + if (0) + RTW_INFO("%s: "MAC_FMT" is legacy ap\n", __func__, MAC_ARG(GetAddr3Ptr(pframe))); + + ATOMIC_SET(&pmlmepriv->olbc, _TRUE); + ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE); + } + + } +} + unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) { struct sta_info *psta; @@ -1861,6 +2114,8 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) #endif #endif /* CONFIG_TDLS */ + if (validate_beacon_len(pframe, len) == _FALSE) + return _SUCCESS; #ifdef CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR p = rtw_get_ie(pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ielen, precv_frame->u.hdr.len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_); @@ -1878,8 +2133,18 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } + + rtw_check_legacy_ap(padapter, pframe, len); + if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) { - if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) { + if ((pmlmeinfo->state & WIFI_FW_AUTH_NULL) + && rtw_sta_linking_test_wait_done() + ) { + if (rtw_sta_linking_test_force_fail()) { + set_link_timer(pmlmeext, 1); + return _SUCCESS; + } + /* we should update current network before auth, or some IE is wrong */ pbss = (WLAN_BSSID_EX *)rtw_malloc(sizeof(WLAN_BSSID_EX)); if (pbss) { @@ -1919,7 +2184,8 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) _rtw_memset(pmlmeext->bcn_delay_ratio, 0, sizeof(pmlmeext->bcn_delay_ratio)); #ifdef CONFIG_P2P_PS - process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); + /* Comment by YiWei , in wifi p2p spec the "3.3 P2P Power Management" , "These mechanisms are available in a P2P Group in which only P2P Devices are associated." */ + /* process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); */ #endif /* CONFIG_P2P_PS */ #if defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE) @@ -1940,7 +2206,7 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) } if (((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) { - psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); if (psta != NULL) { #ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL /* Merge from 8712 FW code */ @@ -1967,6 +2233,8 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) update_beacon_info(padapter, pframe, len, psta); } + pmlmepriv->cur_network_scanned->network.Rssi = precv_frame->u.hdr.attrib.phy_info.RecvSignalPower; + adaptive_early_32k(pmlmeext, pframe, len); #ifdef CONFIG_TDLS @@ -2006,7 +2274,7 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) u8 rate_set[16]; u8 rate_num = 0; - psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); if (psta != NULL) { /* * update WMM, ERP in the beacon @@ -2024,7 +2292,7 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) goto _END_ONBEACON_; } - psta = rtw_alloc_stainfo(pstapriv, GetAddr2Ptr(pframe)); + psta = rtw_alloc_stainfo(pstapriv, get_addr2_ptr(pframe)); if (psta == NULL) { RTW_INFO(FUNC_ADPT_FMT" Exceed the upper limit of supported clients\n", FUNC_ADPT_ARG(padapter)); goto _END_ONBEACON_; @@ -2039,7 +2307,7 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) update_TSF(pmlmeext, pframe, len); /* report sta add event */ - report_add_sta_event(padapter, GetAddr2Ptr(pframe)); + report_add_sta_event(padapter, get_addr2_ptr(pframe)); } } } @@ -2082,7 +2350,7 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) RTW_INFO("+OnAuth\n"); - sa = GetAddr2Ptr(pframe); + sa = get_addr2_ptr(pframe); auth_mode = psecuritypriv->dot11AuthAlgrthm; @@ -2301,6 +2569,12 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) unsigned int go2asoc = 0; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); +#ifdef CONFIG_RTW_80211R + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + ft_priv *pftpriv = &pmlmepriv->ftpriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; +#endif u8 *pframe = precv_frame->u.hdr.rx_data; uint pkt_len = precv_frame->u.hdr.len; @@ -2351,7 +2625,7 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } else { - /* open system */ + /* open, or 802.11r FTAA system */ go2asoc = 1; } } else if (seq == 4) { @@ -2366,6 +2640,30 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) } if (go2asoc) { +#ifdef CONFIG_RTW_80211R + if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + u8 target_ap_addr[ETH_ALEN] = {0}; + + if ((rtw_chk_ft_status(padapter, RTW_FT_AUTHENTICATED_STA)) || + (rtw_chk_ft_status(padapter, RTW_FT_ASSOCIATING_STA)) || + (rtw_chk_ft_status(padapter, RTW_FT_ASSOCIATED_STA))) { + /*report_ft_reassoc_event already, and waiting for cfg80211_rtw_update_ft_ies*/ + return _SUCCESS; + } + + rtw_buf_update(&pmlmepriv->auth_rsp, &pmlmepriv->auth_rsp_len, pframe, pkt_len); + pftpriv->ft_event.ies = pmlmepriv->auth_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6; + pftpriv->ft_event.ies_len = pmlmepriv->auth_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6; + + /*Not support RIC*/ + pftpriv->ft_event.ric_ies = NULL; + pftpriv->ft_event.ric_ies_len = 0; + _rtw_memcpy(target_ap_addr, pmlmepriv->assoc_bssid, ETH_ALEN); + report_ft_reassoc_event(padapter, target_ap_addr); + return _SUCCESS; + } +#endif + RTW_PRINT("auth success, start assoc\n"); start_clnt_assoc(padapter); return _SUCCESS; @@ -2419,7 +2717,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) return _FAIL; - frame_type = GetFrameSubType(pframe); + frame_type = get_frame_sub_type(pframe); if (frame_type == WIFI_ASSOCREQ) { reassoc = 0; ie_offset = _ASOCREQ_IE_OFFSET_; @@ -2435,7 +2733,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) return _FAIL; } - pstat = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + pstat = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); if (pstat == (struct sta_info *)NULL) { status = _RSON_CLS2_; goto asoc_class2_error; @@ -2938,7 +3236,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) asoc_class2_error: #ifdef CONFIG_NATIVEAP_MLME - issue_deauth(padapter, (void *)GetAddr2Ptr(pframe), status); + issue_deauth(padapter, (void *)get_addr2_ptr(pframe), status); #endif return _FAIL; @@ -3125,9 +3423,9 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n" - , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe)); + , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe)); - psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); if (psta) { u8 updated = _FALSE; @@ -3166,10 +3464,10 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) } RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM, ignore=%d\n" - , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe), ignore_received_deauth); + , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe), ignore_received_deauth); if (0 == ignore_received_deauth) - receive_disconnect(padapter, GetAddr2Ptr(pframe), reason, _FALSE); + receive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE); } pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; return _SUCCESS; @@ -3215,9 +3513,9 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n" - , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe)); + , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe)); - psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); if (psta) { u8 updated = _FALSE; @@ -3238,9 +3536,9 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) #endif { RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n" - , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe)); + , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe)); - receive_disconnect(padapter, GetAddr2Ptr(pframe), reason, _FALSE); + receive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE); } pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; return _SUCCESS; @@ -3323,7 +3621,7 @@ unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame) RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev)); - psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); if (!psta) goto exit; @@ -3363,6 +3661,45 @@ unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } +#ifdef CONFIG_RTW_WNM +unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe) +{ + unsigned int ret = _FAIL; + struct sta_info *sta = NULL; + struct sta_priv *stapriv = &adapter->stapriv; + u8 *frame = rframe->u.hdr.rx_data; + uint frame_len = rframe->u.hdr.len; + u8 *frame_body = (u8 *)(frame + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 category; + u8 action; + int cnt = 0; + char msg[16]; + + sta = rtw_get_stainfo(stapriv, get_addr2_ptr(frame)); + if (!sta) + goto exit; + + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_WNM) + goto exit; + + action = frame_body[1]; + + switch (action) { + default: + #ifdef CONFIG_IOCTL_CFG80211 + cnt += sprintf((msg + cnt), "ACT_WNM %u", action); + rtw_cfg80211_rx_action(adapter, rframe, msg); + #endif + ret = _SUCCESS; + break; + } + +exit: + return ret; +} +#endif /* CONFIG_RTW_WNM */ + /** * rtw_rx_ampdu_size - Get the target RX AMPDU buffer size for the specific @adapter * @adapter: the adapter to get target RX AMPDU buffer size @@ -3374,11 +3711,6 @@ u8 rtw_rx_ampdu_size(_adapter *adapter) u8 size; HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor; - if (adapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID) { - size = adapter->fix_rx_ampdu_size; - goto exit; - } - #ifdef CONFIG_BT_COEXIST if (rtw_btcoex_IsBTCoexCtrlAMPDUSize(adapter) == _TRUE) { size = rtw_btcoex_GetAMPDUSize(adapter); @@ -3400,7 +3732,14 @@ u8 rtw_rx_ampdu_size(_adapter *adapter) max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)adapter->driver_rx_ampdu_factor; else rtw_hal_get_def_var(adapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); - + + /* In Maximum A-MPDU Length Exponent subfield of A-MPDU Parameters field of HT Capabilities element, + the unit of max_rx_ampdu_factor are octets. 8K, 16K, 32K, 64K is right. + But the buffer size subfield of Block Ack Parameter Set field in ADDBA action frame indicates + the number of buffers available for this particular TID. Each buffer is equal to max. size of + MSDU or AMSDU. + The size variable means how many MSDUs or AMSDUs, it's not Kbytes. + */ if (MAX_AMPDU_FACTOR_64K == max_rx_ampdu_factor) size = 64; else if (MAX_AMPDU_FACTOR_32K == max_rx_ampdu_factor) @@ -3569,6 +3908,35 @@ u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 ac return ret; } +u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta) +{ + u8 sz_limit = 0xFF; + +#ifdef CONFIG_80211N_HT + struct registry_priv *regsty = adapter_to_regsty(adapter); + struct mlme_priv *mlme = &adapter->mlmepriv; + struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info; + s8 nss = -1; + u8 bw = rtw_min(sta->bw_mode, adapter->mlmeextpriv.cur_bwmode); + + #ifdef CONFIG_80211AC_VHT + if (is_supported_vht(sta->wireless_mode)) { + nss = rtw_min(rtw_vht_mcsmap_to_nss(mlme->vhtpriv.vht_mcs_map) + , rtw_vht_mcsmap_to_nss(sta->vhtpriv.vht_mcs_map)); + } else + #endif + if (is_supported_ht(sta->wireless_mode)) { + nss = rtw_min(rtw_ht_mcsset_to_nss(mlmeinfo->HT_caps.u.HT_cap_element.MCS_rate) + , rtw_ht_mcsset_to_nss(sta->htpriv.ht_cap.supp_mcs_set)); + } + + if (nss >= 1) + sz_limit = regsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][bw]; +#endif /* CONFIG_80211N_HT */ + + return sz_limit; +} + /** * rx_ampdu_apply_sta - Apply RX AMPDU setting to the specific @sta * @adapter: the adapter to which @sta belongs @@ -3602,17 +3970,25 @@ u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 siz u16 rtw_rx_ampdu_apply(_adapter *adapter) { u16 adj_cnt = 0; - struct mlme_ext_priv *mlmeext; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; struct sta_info *sta; u8 accept = rtw_rx_ampdu_is_accept(adapter); - u8 size = rtw_rx_ampdu_size(adapter); + u8 size; - mlmeext = &adapter->mlmeextpriv; + if (adapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID) + size = adapter->fix_rx_ampdu_size; + else + size = rtw_rx_ampdu_size(adapter); if (mlmeext_msr(mlmeext) == WIFI_FW_STATION_STATE) { sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv)); - if (sta) - adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, size); + if (sta) { + u8 sta_size = size; + + if (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) + sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta)); + adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size); + } } else if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE) { _irqL irqL; @@ -3642,8 +4018,13 @@ u16 rtw_rx_ampdu_apply(_adapter *adapter) for (i = 0; i < peer_num; i++) { sta = rtw_get_stainfo_by_offset(pstapriv, peers[i]); - if (sta) - adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, size); + if (sta) { + u8 sta_size = size; + + if (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) + sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta)); + adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size); + } } } @@ -3681,7 +4062,7 @@ unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame) if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) return _SUCCESS; - addr = GetAddr2Ptr(pframe); + addr = get_addr2_ptr(pframe); psta = rtw_get_stainfo(pstapriv, addr); if (psta == NULL) @@ -3766,42 +4147,20 @@ unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame) } #ifdef CONFIG_P2P - -static int get_reg_classes_full_count(struct p2p_channels channel_list) +int get_reg_classes_full_count(struct p2p_channels *channel_list) { int cnt = 0; int i; - for (i = 0; i < channel_list.reg_classes; i++) - cnt += channel_list.reg_class[i].channels; + for (i = 0; i < channel_list->reg_classes; i++) + cnt += channel_list->reg_class[i].channels; return cnt; } -static void get_channel_cnt_24g_5gl_5gh(struct mlme_ext_priv *pmlmeext, u8 *p24g_cnt, u8 *p5gl_cnt, u8 *p5gh_cnt) -{ - int i = 0; - - *p24g_cnt = 0; - *p5gl_cnt = 0; - *p5gh_cnt = 0; - - for (i = 0; i < pmlmeext->max_chan_nums; i++) { - if (pmlmeext->channel_set[i].ChannelNum <= 14) - (*p24g_cnt)++; - else if ((pmlmeext->channel_set[i].ChannelNum > 14) && (pmlmeext->channel_set[i].ChannelNum <= 48)) { - /* Just include the channel 36, 40, 44, 48 channels for 5G low */ - (*p5gl_cnt)++; - } else if ((pmlmeext->channel_set[i].ChannelNum >= 149) && (pmlmeext->channel_set[i].ChannelNum <= 161)) { - /* Just include the channel 149, 153, 157, 161 channels for 5G high */ - (*p5gh_cnt)++; - } - } -} - void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) { - + struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; u8 action = P2P_PUB_ACTION_ACTION; u32 p2poui = cpu_to_be32(P2POUI); @@ -3848,7 +4207,7 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -4013,7 +4372,7 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) /* Intended P2P Interface Address */ /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_INTENTED_IF_ADDR; + p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR; /* Length: */ *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN); @@ -4033,8 +4392,8 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ /* + number of channels in all classes */ len_channellist_attr = 3 - + (1 + 1) * (u16)(pmlmeext->channel_list.reg_classes) - + get_reg_classes_full_count(pmlmeext->channel_list); + + (1 + 1) * (u16)(ch_list->reg_classes) + + get_reg_classes_full_count(ch_list); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) @@ -4079,36 +4438,22 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) /* Channel List */ p2pie[p2pielen++] = union_ch; - } else { - int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; - - /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; - - /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; - } - } -#else /* CONFIG_CONCURRENT_MODE */ + } else +#endif /* CONFIG_CONCURRENT_MODE */ { int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + for (j = 0; j < ch_list->reg_classes; j++) { /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + p2pie[p2pielen++] = ch_list->reg_class[j].channels; /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + for (i = 0; i < ch_list->reg_class[j].channels; i++) + p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; } } -#endif /* CONFIG_CONCURRENT_MODE */ /* Device Info */ /* Type: */ @@ -4213,7 +4558,7 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint len, u8 result) { - + struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; u8 action = P2P_PUB_ACTION_ACTION; u32 p2poui = cpu_to_be32(P2POUI); @@ -4263,7 +4608,7 @@ void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint l SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -4462,7 +4807,7 @@ void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint l /* Intended P2P Interface Address */ /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_INTENTED_IF_ADDR; + p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR; /* Length: */ *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN); @@ -4480,8 +4825,8 @@ void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint l /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ /* + number of channels in all classes */ len_channellist_attr = 3 - + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes - + get_reg_classes_full_count(pmlmeext->channel_list); + + (1 + 1) * (u16)ch_list->reg_classes + + get_reg_classes_full_count(ch_list); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) @@ -4526,37 +4871,22 @@ void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint l /*Channel List*/ p2pie[p2pielen++] = union_chan; - } else { - int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; - - /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; - - /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; - } - } -#else /* CONFIG_CONCURRENT_MODE */ + } else +#endif /* CONFIG_CONCURRENT_MODE */ { int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + for (j = 0; j < ch_list->reg_classes; j++) { /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + p2pie[p2pielen++] = ch_list->reg_class[j].channels; /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + for (i = 0; i < ch_list->reg_class[j].channels; i++) + p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; } } -#endif /* CONFIG_CONCURRENT_MODE */ - /* Device Info */ /* Type: */ @@ -4691,7 +5021,7 @@ void issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result) SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -4882,7 +5212,7 @@ void issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result) void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr) { - + struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; u8 action = P2P_PUB_ACTION_ACTION; u32 p2poui = cpu_to_be32(P2POUI); @@ -4929,7 +5259,7 @@ void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr) SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -5036,8 +5366,8 @@ void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr) /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ /* + number of channels in all classes */ len_channellist_attr = 3 - + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes - + get_reg_classes_full_count(pmlmeext->channel_list); + + (1 + 1) * (u16)ch_list->reg_classes + + get_reg_classes_full_count(ch_list); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) @@ -5079,36 +5409,22 @@ void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr) /* Channel List */ p2pie[p2pielen++] = union_ch; - } else { - int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; - - /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; - - /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; - } - } -#else /* CONFIG_CONCURRENT_MODE */ + } else +#endif /* CONFIG_CONCURRENT_MODE */ { int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + for (j = 0; j < ch_list->reg_classes; j++) { /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + p2pie[p2pielen++] = ch_list->reg_class[j].channels; /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + for (i = 0; i < ch_list->reg_class[j].channels; i++) + p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; } } -#endif /* CONFIG_CONCURRENT_MODE */ /* P2P Group ID */ @@ -5196,7 +5512,7 @@ void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr) void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 status_code) { - + struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; u8 action = P2P_PUB_ACTION_ACTION; u32 p2poui = cpu_to_be32(P2POUI); @@ -5242,7 +5558,7 @@ void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -5354,8 +5670,8 @@ void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ /* + number of channels in all classes */ len_channellist_attr = 3 - + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes - + get_reg_classes_full_count(pmlmeext->channel_list); + + (1 + 1) * (u16)ch_list->reg_classes + + get_reg_classes_full_count(ch_list); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) @@ -5397,36 +5713,22 @@ void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken /* Channel List */ p2pie[p2pielen++] = union_ch; - } else { - int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; - - /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; - - /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; - } - } -#else /* CONFIG_CONCURRENT_MODE */ + } else +#endif /* CONFIG_CONCURRENT_MODE */ { int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + for (j = 0; j < ch_list->reg_classes; j++) { /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + p2pie[p2pielen++] = ch_list->reg_class[j].channels; /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + for (i = 0; i < ch_list->reg_class[j].channels; i++) + p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; } } -#endif /* CONFIG_CONCURRENT_MODE */ } pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); @@ -5493,7 +5795,7 @@ void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -5612,6 +5914,12 @@ void issue_probersp_p2p(_adapter *padapter, unsigned char *da) pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); + if (IS_CCK_RATE(pattrib->rate)) { + /* force OFDM 6M rate */ + pattrib->rate = MGN_6M; + pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G); + } + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; @@ -5629,7 +5937,7 @@ void issue_probersp_p2p(_adapter *padapter, unsigned char *da) SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(fctrl, WIFI_PROBERSP); + set_frame_sub_type(fctrl, WIFI_PROBERSP); pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = pattrib->hdrlen; @@ -5932,6 +6240,11 @@ int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack) pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); + if (IS_CCK_RATE(pattrib->rate)) { + /* force OFDM 6M rate */ + pattrib->rate = MGN_6M; + pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G); + } _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); @@ -5961,7 +6274,7 @@ int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack) SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_PROBEREQ); + set_frame_sub_type(pframe, WIFI_PROBEREQ); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -6205,7 +6518,6 @@ int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack) pattrib->last_txcmdsz = pattrib->pktlen; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("issuing probe_req, tx_len=%d\n", pattrib->last_txcmdsz)); if (wait_ack) ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); @@ -6317,7 +6629,7 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame) _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey); #ifdef CONFIG_IOCTL_CFG80211 if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) - rtw_cfg80211_rx_p2p_action_public(padapter, pframe, len); + rtw_cfg80211_rx_p2p_action_public(padapter, precv_frame); else #endif /* CONFIG_IOCTL_CFG80211 */ { @@ -6356,10 +6668,10 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame) /* Commented by Kurt 20120113 */ /* Get peer_dev_addr here if peer doesn't issue prov_disc frame. */ if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.peerDevAddr, empty_addr, ETH_ALEN)) - _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN); + _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN); result = process_p2p_group_negotation_req(pwdinfo, frame_body, len); - issue_p2p_GO_response(padapter, GetAddr2Ptr(pframe), frame_body, len, result); + issue_p2p_GO_response(padapter, get_addr2_ptr(pframe), frame_body, len, result); #ifdef CONFIG_INTEL_WIDI if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) { padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION; @@ -6387,7 +6699,7 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame) _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); pwdinfo->nego_req_info.benable = _FALSE; result = process_p2p_group_negotation_resp(pwdinfo, frame_body, len); - issue_p2p_GO_confirm(pwdinfo->padapter, GetAddr2Ptr(pframe), result); + issue_p2p_GO_confirm(pwdinfo->padapter, get_addr2_ptr(pframe), result); if (P2P_STATUS_SUCCESS == result) { if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) { pwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch; @@ -6488,7 +6800,7 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame) u8 operatingch_info[5] = { 0x00 }; if (rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) { - if (rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, (u32)operatingch_info[4]) >= 0) { + if (rtw_chset_search_ch(adapter_to_chset(padapter), (u32)operatingch_info[4]) >= 0) { /* The operating channel is acceptable for this device. */ pwdinfo->rx_invitereq_info.operation_ch[0] = operatingch_info[4]; #ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH @@ -6565,7 +6877,7 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame) RTW_INFO("[%s] status_code = %d\n", __FUNCTION__, status_code); pwdinfo->inviteresp_info.token = frame_body[7]; - issue_p2p_invitation_response(padapter, GetAddr2Ptr(pframe), pwdinfo->inviteresp_info.token, status_code); + issue_p2p_invitation_response(padapter, get_addr2_ptr(pframe), pwdinfo->inviteresp_info.token, status_code); _set_timer(&pwdinfo->restore_p2p_state_timer, 3000); } #ifdef CONFIG_INTEL_WIDI @@ -6630,7 +6942,7 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame) case P2P_PROVISION_DISC_REQ: RTW_INFO("[%s] Got Provisioning Discovery Request Frame\n", __FUNCTION__); process_p2p_provdisc_req(pwdinfo, pframe, len); - _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN); + _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN); /* 20110902 Kurt */ /* Add the following statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */ @@ -6711,7 +7023,7 @@ unsigned int on_action_public_default(union recv_frame *precv_frame, u8 action) #ifdef CONFIG_IOCTL_CFG80211 cnt += sprintf((msg + cnt), "%s(token:%u)", action_public_str(action), token); - rtw_cfg80211_rx_action(adapter, pframe, frame_len, msg); + rtw_cfg80211_rx_action(adapter, precv_frame, msg); #endif ret = _SUCCESS; @@ -6759,6 +7071,91 @@ unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame) return ret; } +unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_RTW_80211R + u32 ret = _FAIL; + u32 frame_len = 0; + u8 action_code = 0; + u8 category = 0; + u8 *pframe = NULL; + u8 *pframe_body = NULL; + u8 sta_addr[ETH_ALEN] = {0}; + u8 *pie = NULL; + u32 ft_ie_len = 0; + u32 status_code = 0; + struct mlme_ext_priv *pmlmeext = NULL; + struct mlme_ext_info *pmlmeinfo = NULL; + struct mlme_priv *pmlmepriv = NULL; + struct wlan_network *proam_target = NULL; + ft_priv *pftpriv = NULL; + _irqL irqL; + + pmlmeext = &padapter->mlmeextpriv; + pmlmeinfo = &(pmlmeext->mlmext_info); + pmlmepriv = &padapter->mlmepriv; + pftpriv = &pmlmepriv->ftpriv; + pframe = precv_frame->u.hdr.rx_data; + frame_len = precv_frame->u.hdr.len; + pframe_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + category = pframe_body[0]; + + if (category != RTW_WLAN_CATEGORY_FT) + goto exit; + + action_code = pframe_body[1]; + switch (action_code) { + case RTW_WLAN_ACTION_FT_RESPONSE: + RTW_INFO("FT: %s RTW_WLAN_ACTION_FT_RESPONSE\n", __func__); + if (!_rtw_memcmp(adapter_mac_addr(padapter), &pframe_body[2], ETH_ALEN)) { + RTW_ERR("FT: Unmatched STA MAC Address "MAC_FMT"\n", MAC_ARG(&pframe_body[2])); + goto exit; + } + + status_code = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + 14)); + if (status_code != 0) { + RTW_ERR("FT: WLAN ACTION FT RESPONSE fail, status: %d\n", status_code); + goto exit; + } + + if (is_zero_mac_addr(&pframe_body[8]) || is_broadcast_mac_addr(&pframe_body[8])) { + RTW_ERR("FT: Invalid Target MAC Address "MAC_FMT"\n", MAC_ARG(padapter->mlmepriv.roam_tgt_addr)); + goto exit; + } + + pie = rtw_get_ie(pframe_body, _MDIE_, &ft_ie_len, frame_len); + if (pie) { + if (!_rtw_memcmp(&pftpriv->mdid, pie+2, 2)) { + RTW_ERR("FT: Invalid MDID\n"); + goto exit; + } + } + + rtw_set_ft_status(padapter, RTW_FT_REQUESTED_STA); + _cancel_timer_ex(&pmlmeext->ft_link_timer); + + /*Disconnect current AP*/ + receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress, WLAN_REASON_ACTIVE_ROAM, _FALSE); + + pftpriv->ft_action_len = frame_len; + _rtw_memcpy(pftpriv->ft_action, pframe, rtw_min(frame_len, RTW_MAX_FTIE_SZ)); + ret = _SUCCESS; + break; + case RTW_WLAN_ACTION_FT_REQUEST: + case RTW_WLAN_ACTION_FT_CONFIRM: + case RTW_WLAN_ACTION_FT_ACK: + default: + RTW_ERR("FT: Unsupported FT Action!\n"); + break; + } + +exit: + return ret; +#else + return _SUCCESS; +#endif +} + unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame) { u8 *pframe = precv_frame->u.hdr.rx_data; @@ -6780,14 +7177,14 @@ unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_80211N_HT #ifdef CONFIG_AP_MODE if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) - rtw_process_ht_action_smps(padapter, GetAddr2Ptr(pframe), frame_body[2]); + rtw_process_ht_action_smps(padapter, get_addr2_ptr(pframe), frame_body[2]); #endif /*CONFIG_AP_MODE*/ #endif /*CONFIG_80211N_HT*/ break; case RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING: #ifdef CONFIG_BEAMFORMING /*RTW_INFO("RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING\n");*/ - beamforming_get_report_frame(padapter, precv_frame); + rtw_beamforming_get_report_frame(padapter, precv_frame); #endif /*CONFIG_BEAMFORMING*/ break; default: @@ -6818,11 +7215,11 @@ unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame _rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16)); RTW_INFO("OnAction_sa_query request,action=%d, tid=%04x, pframe=%02x-%02x\n" , pframe[WLAN_HDR_A3_LEN + 1], tid, pframe[WLAN_HDR_A3_LEN + 2], pframe[WLAN_HDR_A3_LEN + 3]); - issue_action_SA_Query(padapter, GetAddr2Ptr(pframe), 1, tid, IEEE80211W_RIGHT_KEY); + issue_action_SA_Query(padapter, get_addr2_ptr(pframe), 1, tid, IEEE80211W_RIGHT_KEY); break; case 1: /* SA Query rsp */ - psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); if (psta != NULL) _cancel_timer_ex(&psta->dot11w_expire_timer); @@ -6873,7 +7270,7 @@ unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame) case RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING: #ifdef CONFIG_BEAMFORMING /*RTW_INFO("RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING\n");*/ - beamforming_get_report_frame(padapter, precv_frame); + rtw_beamforming_get_report_frame(padapter, precv_frame); #endif /*CONFIG_BEAMFORMING*/ break; case RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION: @@ -6885,7 +7282,9 @@ unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame) break; case RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT: #ifdef CONFIG_BEAMFORMING - beamforming_get_vht_gid_mgnt_frame(padapter, precv_frame); +#ifdef RTW_BEAMFORMING_VERSION_2 + rtw_beamforming_get_vht_gid_mgnt_frame(padapter, precv_frame); +#endif /* RTW_BEAMFORMING_VERSION_2 */ #endif /* CONFIG_BEAMFORMING */ break; default: @@ -6922,9 +7321,9 @@ unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_IOCTL_CFG80211 if (adapter_wdev_data(padapter)->p2p_enabled - && pwdinfo->driver_interface == DRIVER_CFG80211 - ) { - rtw_cfg80211_rx_action_p2p(padapter, pframe, len); + && pwdinfo->driver_interface == DRIVER_CFG80211 + ) { + rtw_cfg80211_rx_action_p2p(padapter, precv_frame); return _SUCCESS; } else #endif /* CONFIG_IOCTL_CFG80211 */ @@ -6990,7 +7389,7 @@ unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame) unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame) { - /* RTW_INFO("rcvd mgt frame(%x, %x)\n", (GetFrameSubType(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); */ + /* RTW_INFO("rcvd mgt frame(%x, %x)\n", (get_frame_sub_type(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); */ return _SUCCESS; } @@ -7127,8 +7526,6 @@ void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib) u8 wireless_mode; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct sta_info *psta = NULL; - struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *pbcmc_sta = NULL; /* _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); */ @@ -7154,7 +7551,7 @@ void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib) pattrib->pktlen = 0; - if (pmlmeext->tx_rate == IEEE80211_CCK_RATE_1MB) + if (IS_CCK_RATE(pmlmeext->tx_rate)) wireless_mode = WIRELESS_11B; else wireless_mode = WIRELESS_11G; @@ -7176,24 +7573,30 @@ void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib) pattrib->mbssid = 0; pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; - -#ifdef CONFIG_BEAMFORMING - psta = rtw_get_stainfo(pstapriv, pattrib->ra); - if (psta) - update_attrib_txbf_info(padapter, pattrib, psta); -#endif - } void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe) { u8 *pframe; struct pkt_attrib *pattrib = &pmgntframe->attrib; +#ifdef CONFIG_BEAMFORMING + struct sta_info *sta = NULL; +#endif /* CONFIG_BEAMFORMING */ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; _rtw_memcpy(pattrib->ra, GetAddr1Ptr(pframe), ETH_ALEN); - _rtw_memcpy(pattrib->ta, GetAddr2Ptr(pframe), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(pframe), ETH_ALEN); + +#ifdef CONFIG_BEAMFORMING + sta = pattrib->psta; + if (!sta) { + sta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + pattrib->psta = sta; + } + if (sta) + update_attrib_txbf_info(padapter, pattrib, sta); +#endif /* CONFIG_BEAMFORMING */ } void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe) @@ -7254,13 +7657,8 @@ s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *p pxmitpriv->seq_no = seq_no++; pmgntframe->ack_report = 1; rtw_sctx_init(&(pxmitpriv->ack_tx_ops), timeout_ms); - if (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS) { -#ifdef CONFIG_XMIT_ACK_POLLING - ret = rtw_ack_tx_polling(pxmitpriv, timeout_ms); -#else + if (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS) ret = rtw_sctx_wait(&(pxmitpriv->ack_tx_ops), __func__); -#endif - } pxmitpriv->ack_tx = _FALSE; _exit_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL); @@ -7398,7 +7796,7 @@ void issue_beacon(_adapter *padapter, int timeout_ms) SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); /* pmlmeext->mgnt_seq++; */ - SetFrameSubType(pframe, WIFI_BEACON); + set_frame_sub_type(pframe, WIFI_BEACON); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -7544,6 +7942,10 @@ void issue_beacon(_adapter *padapter, int timeout_ms) pframe += len; pattrib->pktlen += len; +#ifdef CONFIG_MCC_MODE + pframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen); +#endif /* CONFIG_MCC_MODE*/ + #ifdef CONFIG_WFD len = rtw_append_beacon_wfd_ie(padapter, pframe); pframe += len; @@ -7693,7 +8095,7 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(fctrl, WIFI_PROBERSP); + set_frame_sub_type(fctrl, WIFI_PROBERSP); pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = pattrib->hdrlen; @@ -7852,6 +8254,10 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe pframe += len; pattrib->pktlen += len; +#ifdef CONFIG_MCC_MODE + pframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen); +#endif /* CONFIG_MCC_MODE*/ + #ifdef CONFIG_WFD len = rtw_append_probe_resp_wfd_ie(padapter, pframe); pframe += len; @@ -7953,7 +8359,7 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_PROBEREQ); + set_frame_sub_type(pframe, WIFI_PROBEREQ); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -7989,7 +8395,6 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, pattrib->last_txcmdsz = pattrib->pktlen; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("issuing probe_req, tx_len=%d\n", pattrib->last_txcmdsz)); if (wait_ack) ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); @@ -8070,6 +8475,14 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); +#ifdef CONFIG_RTW_80211R + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + ft_priv *pftpriv = &pmlmepriv->ftpriv; + u8 is_ft_roaming = _FALSE; + u8 is_ft_roaming_with_rsn_ie = _TRUE; + u8 *pie = NULL; + u32 ft_ie_len = 0; +#endif if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) return; @@ -8092,7 +8505,7 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_AUTH); + set_frame_sub_type(pframe, WIFI_AUTH); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -8138,12 +8551,23 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); - /* setting auth algo number */ - val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ? 1 : 0; /* 0:OPEN System, 1:Shared key */ - if (val16) { +#ifdef CONFIG_RTW_80211R + /*For Fast BSS Transition */ + if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + is_ft_roaming = _TRUE; + val16 = 2; /* 2: 802.11R FTAA */ val16 = cpu_to_le16(val16); - use_shared_key = 1; + } else +#endif + { + /* setting auth algo number */ + val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ? 1 : 0; /* 0:OPEN System, 1:Shared key */ + if (val16) { + val16 = cpu_to_le16(val16); + use_shared_key = 1; + } } + /* RTW_INFO("%s auth_algo= %s auth_seq=%d\n",__FUNCTION__,(pmlmeinfo->auth_algo==0)?"OPEN":"SHARED",pmlmeinfo->auth_seq); */ /* setting IV for auth seq #3 */ @@ -8169,6 +8593,24 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status val16 = cpu_to_le16(val16); pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); +#ifdef CONFIG_RTW_80211R + if (is_ft_roaming == _TRUE) { + pie = rtw_get_ie(pftpriv->updated_ft_ies, EID_WPA2, &ft_ie_len, pftpriv->updated_ft_ies_len); + if (pie) + pframe = rtw_set_ie(pframe, EID_WPA2, ft_ie_len, pie+2, &(pattrib->pktlen)); + else + is_ft_roaming_with_rsn_ie = _FALSE; + + pie = rtw_get_ie(pftpriv->updated_ft_ies, _MDIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); + if (pie) + pframe = rtw_set_ie(pframe, _MDIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); + + pie = rtw_get_ie(pftpriv->updated_ft_ies, _FTIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); + if (pie && is_ft_roaming_with_rsn_ie) + pframe = rtw_set_ie(pframe, _FTIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); + } +#endif + /* then checking to see if sending challenging text... */ if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) { pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen)); @@ -8243,14 +8685,14 @@ void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *p *(fctrl) = 0; _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->hwaddr, ETH_ALEN); - _rtw_memcpy((void *)GetAddr2Ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; if ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP)) - SetFrameSubType(pwlanhdr, pkt_type); + set_frame_sub_type(pwlanhdr, pkt_type); else return; @@ -8417,7 +8859,7 @@ void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *p #endif } -void issue_assocreq(_adapter *padapter) +void _issue_assocreq(_adapter *padapter, u8 is_reassoc) { int ret = _FAIL; struct xmit_frame *pmgntframe; @@ -8446,12 +8888,18 @@ void issue_assocreq(_adapter *padapter) #endif /* CONFIG_P2P */ #ifdef CONFIG_DFS + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); u16 cap; /* Dot H */ u8 pow_cap_ele[2] = { 0x00 }; u8 sup_ch[30 * 2] = {0x00 }, sup_ch_idx = 0, idx_5g = 2; /* For supported channel */ #endif /* CONFIG_DFS */ +#ifdef CONFIG_RTW_80211R + u8 *pie = NULL; + u32 ft_ie_len = 0; + ft_priv *pftpriv = &pmlmepriv->ftpriv; +#endif if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; @@ -8478,7 +8926,10 @@ void issue_assocreq(_adapter *padapter) SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ASSOCREQ); + if (is_reassoc == _TRUE) + set_frame_sub_type(pframe, WIFI_REASSOCREQ); + else + set_frame_sub_type(pframe, WIFI_ASSOCREQ); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -8503,6 +8954,13 @@ void issue_assocreq(_adapter *padapter) pframe += 2; pattrib->pktlen += 2; + /*Construct Current AP Field for Reassoc-Req only*/ + if (is_reassoc == _TRUE) { + _rtw_memcpy(pframe, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + pframe += ETH_ALEN; + pattrib->pktlen += ETH_ALEN; + } + /* SSID */ pframe = rtw_set_ie(pframe, _SSID_IE_, pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen)); @@ -8514,16 +8972,17 @@ void issue_assocreq(_adapter *padapter) pframe = rtw_set_ie(pframe, EID_PowerCap, 2, pow_cap_ele, &(pattrib->pktlen)); /* supported channels */ - do { - if (pmlmeext->channel_set[sup_ch_idx].ChannelNum <= 14) { + while (sup_ch_idx < rfctl->max_chan_nums && rfctl->channel_set[sup_ch_idx].ChannelNum != 0) { + if (rfctl->channel_set[sup_ch_idx].ChannelNum <= 14) { + /* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */ sup_ch[0] = 1; /* First channel number */ - sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; /* Number of channel */ + sup_ch[1] = rfctl->channel_set[sup_ch_idx].ChannelNum; /* Number of channel */ } else { - sup_ch[idx_5g++] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; + sup_ch[idx_5g++] = rfctl->channel_set[sup_ch_idx].ChannelNum; sup_ch[idx_5g++] = 1; } sup_ch_idx++; - } while (pmlmeext->channel_set[sup_ch_idx].ChannelNum != 0); + } pframe = rtw_set_ie(pframe, EID_SupportedChannels, idx_5g, sup_ch, &(pattrib->pktlen)); } #endif /* CONFIG_DFS */ @@ -8632,7 +9091,14 @@ void issue_assocreq(_adapter *padapter) break; case EID_WPA2: - pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen)); +#ifdef CONFIG_RTW_80211R + if ((is_reassoc == _TRUE) && (rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + pie = rtw_get_ie(pftpriv->updated_ft_ies, EID_WPA2, &ft_ie_len, pftpriv->updated_ft_ies_len); + if (pie) + pframe = rtw_set_ie(pframe, EID_WPA2, ft_ie_len, pie+2, &(pattrib->pktlen)); + } else +#endif + pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen)); break; #ifdef CONFIG_80211N_HT case EID_HTCapability: @@ -8829,6 +9295,30 @@ void issue_assocreq(_adapter *padapter) #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_ASSOCREQ_VENDOR_IE_BIT); #endif +#ifdef CONFIG_RTW_80211R + if (rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + u8 mdieval[3] = {0}; + + _rtw_memcpy(mdieval, &(pftpriv->mdid), 2); + mdieval[2] = pftpriv->ft_cap; + pframe = rtw_set_ie(pframe, _MDIE_, 3, mdieval, &(pattrib->pktlen)); + } + + if (is_reassoc == _TRUE) { + if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + u8 is_ft_roaming_with_rsn_ie = _TRUE; + + pie = rtw_get_ie(pftpriv->updated_ft_ies, EID_WPA2, &ft_ie_len, pftpriv->updated_ft_ies_len); + if (!pie) + is_ft_roaming_with_rsn_ie = _FALSE; + + pie = rtw_get_ie(pftpriv->updated_ft_ies, _FTIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); + if (pie && is_ft_roaming_with_rsn_ie) + pframe = rtw_set_ie(pframe, _FTIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); + } + } +#endif + pattrib->last_txcmdsz = pattrib->pktlen; dump_mgntframe(padapter, pmgntframe); @@ -8843,6 +9333,16 @@ void issue_assocreq(_adapter *padapter) return; } +void issue_assocreq(_adapter *padapter) +{ + _issue_assocreq(padapter, _FALSE); +} + +void issue_reassocreq(_adapter *padapter) +{ + _issue_assocreq(padapter, _TRUE); +} + /* when wait_ack is ture, this function shoule be called at process context */ static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack) { @@ -8899,7 +9399,7 @@ static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int p SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_DATA_NULL); + set_frame_sub_type(pframe, WIFI_DATA_NULL); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -9093,7 +9593,7 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); + set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); @@ -9217,7 +9717,7 @@ static int _issue_deauth(_adapter *padapter, unsigned char *da, unsigned short r SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_DEAUTH); + set_frame_sub_type(pframe, WIFI_DEAUTH); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -9344,7 +9844,7 @@ void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_of SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -9419,7 +9919,7 @@ void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned ch SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -9520,7 +10020,7 @@ static int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned ch SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -9542,6 +10042,12 @@ static int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned ch BA_para_set = (0x1002 | ((tid & 0xf) << 2)); /* immediate ack & 64 buffer size */ #endif +#ifdef CONFIG_TX_AMSDU + if (padapter->tx_amsdu >= 1) /* TX AMSDU enabled */ + BA_para_set |= BIT(0); + else /* TX AMSDU disabled */ + BA_para_set &= ~BIT(0); +#endif BA_para_set = cpu_to_le16(BA_para_set); pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); @@ -9709,8 +10215,8 @@ inline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, } if (try_cnt && wait_ms) { - RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" tid=%u%s, %d/%d in %u ms\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), tid + RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status:=%u tid=%u size:%u%s, %d/%d in %u ms\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size , ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start)); } @@ -9851,7 +10357,7 @@ static void issue_action_BSSCoexistPacket(_adapter *padapter) SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -10001,7 +10507,7 @@ int _issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoP SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -10189,6 +10695,14 @@ unsigned int send_beacon(_adapter *padapter) #endif #ifdef CONFIG_PCI_HCI + /* bypass TX BCN queue because op ch is switching/waiting */ + if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) + #ifdef CONFIG_DFS_MASTER + || IS_CH_WAITING(adapter_to_rfctl(padapter)) + #endif + ) + return _SUCCESS; + /* RTW_INFO("%s\n", __FUNCTION__); */ rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); @@ -10210,6 +10724,14 @@ unsigned int send_beacon(_adapter *padapter) #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) u32 start = rtw_get_current_time(); + /* bypass TX BCN queue because op ch is switching/waiting */ + if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) + #ifdef CONFIG_DFS_MASTER + || IS_CH_WAITING(adapter_to_rfctl(padapter)) + #endif + ) + return _SUCCESS; + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); do { @@ -10235,8 +10757,8 @@ unsigned int send_beacon(_adapter *padapter) if (passing_time > 100 || issue > 3) RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); - /* else */ - /* RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); */ + else if (0) + RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); rtw_hal_fw_correct_bcn(padapter); @@ -10293,7 +10815,7 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI _rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX)); - subtype = GetFrameSubType(pframe); + subtype = get_frame_sub_type(pframe); if (subtype == WIFI_BEACON) { bssid->Reserved[0] = 1; @@ -10397,7 +10919,7 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI /* FIXME */ bssid->InfrastructureMode = Ndis802_11Infrastructure; - _rtw_memcpy(bssid->MacAddress, GetAddr2Ptr(pframe), ETH_ALEN); + _rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN); bssid->Privacy = 1; return _SUCCESS; } @@ -10434,7 +10956,7 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI if (val16 & BIT(0)) { bssid->InfrastructureMode = Ndis802_11Infrastructure; - _rtw_memcpy(bssid->MacAddress, GetAddr2Ptr(pframe), ETH_ALEN); + _rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN); } else { bssid->InfrastructureMode = Ndis802_11IBSS; _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); @@ -10515,7 +11037,6 @@ void start_create_ibss(_adapter *padapter) rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); /* switch channel */ - /* SelectChannel(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE); */ set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); doiqk = _FALSE; @@ -10529,7 +11050,6 @@ void start_create_ibss(_adapter *padapter) /* issue beacon */ if (send_beacon(padapter) == _FAIL) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("issuing beacon frame fail....\n")); report_join_res(padapter, -1); pmlmeinfo->state = WIFI_FW_NULL_STATE; @@ -10636,7 +11156,30 @@ void start_clnt_join(_adapter *padapter) _set_timer(&padapter->mlmepriv.assoc_timer, (REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO * REASSOC_LIMIT) + beacon_timeout); - pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; +#ifdef CONFIG_RTW_80211R + if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + if (rtw_chk_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED)) { + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + ft_priv *pftpriv = &pmlmepriv->ftpriv; + + pmlmeinfo->state = WIFI_FW_AUTH_SUCCESS | WIFI_FW_STATION_STATE; + pftpriv->ft_event.ies = pftpriv->ft_action + sizeof(struct rtw_ieee80211_hdr_3addr) + 16; + pftpriv->ft_event.ies_len = pftpriv->ft_action_len - sizeof(struct rtw_ieee80211_hdr_3addr); + + /*Not support RIC*/ + pftpriv->ft_event.ric_ies = NULL; + pftpriv->ft_event.ric_ies_len = 0; + report_ft_event(padapter); + } else { + pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; + start_clnt_auth(padapter); + } + } else +#endif + { + rtw_sta_linking_test_set_start(); + pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; + } } else if (caps & cap_IBSS) { /* adhoc client */ Set_MSR(padapter, WIFI_FW_ADHOC_STATE); @@ -10671,8 +11214,13 @@ void start_clnt_auth(_adapter *padapter) pmlmeinfo->link_count = 0; pmlmeext->retry = 0; - - RTW_PRINT("start auth\n"); +#ifdef CONFIG_RTW_80211R + if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + rtw_set_ft_status(padapter, RTW_FT_AUTHENTICATING_STA); + RTW_PRINT("start ft auth\n"); + } else +#endif + RTW_PRINT("start auth\n"); issue_auth(padapter, NULL, 0); set_link_timer(pmlmeext, REAUTH_TO); @@ -10690,7 +11238,12 @@ void start_clnt_assoc(_adapter *padapter) pmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE)); pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE); - issue_assocreq(padapter); +#ifdef CONFIG_RTW_80211R + if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) + issue_reassocreq(padapter); + else +#endif + issue_assocreq(padapter); set_link_timer(pmlmeext, REASSOC_TO); } @@ -10714,6 +11267,10 @@ unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsi pmlmeinfo->state = WIFI_FW_NULL_STATE; } else RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(padapter)); +#ifdef CONFIG_RTW_80211R + if ((rtw_to_roam(padapter) > 0) && !rtw_chk_ft_status(padapter, RTW_FT_REQUESTED_STA)) + rtw_reset_ft_status(padapter); +#endif } return _SUCCESS; @@ -10722,6 +11279,7 @@ unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsi #ifdef CONFIG_80211D static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct registry_priv *pregistrypriv; struct mlme_ext_priv *pmlmeext; RT_CHANNEL_INFO *chplan_new; @@ -10786,7 +11344,7 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) _RTW_INFO("}\n"); #endif - _rtw_memcpy(chplan_sta, pmlmeext->channel_set, sizeof(chplan_sta)); + _rtw_memcpy(chplan_sta, rfctl->channel_set, sizeof(chplan_sta)); #ifdef CONFIG_RTW_DEBUG i = 0; RTW_INFO("%s: STA channel plan {", __FUNCTION__); @@ -10797,8 +11355,8 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) _RTW_INFO("}\n"); #endif - _rtw_memset(pmlmeext->channel_set, 0, sizeof(pmlmeext->channel_set)); - chplan_new = pmlmeext->channel_set; + _rtw_memset(rfctl->channel_set, 0, sizeof(rfctl->channel_set)); + chplan_new = rfctl->channel_set; i = j = k = 0; if (pregistrypriv->wireless_mode & WIRELESS_11G) { @@ -10962,13 +11520,13 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) /* If channel is used by AP, set channel scan type to active */ channel = bssid->Configuration.DSConfig; - chplan_new = pmlmeext->channel_set; + chplan_new = rfctl->channel_set; i = 0; - while ((i < MAX_CHANNEL_NUM) && (chplan_new[i].ChannelNum != 0)) { + while (i < MAX_CHANNEL_NUM && chplan_new[i].ChannelNum != 0) { if (chplan_new[i].ChannelNum == channel) { if (chplan_new[i].ScanType == SCAN_PASSIVE) { /* 5G Bnad 2, 3 (DFS) doesn't change to active scan */ - if (channel >= 52 && channel <= 144) + if (rtw_is_dfs_ch(channel)) break; chplan_new[i].ScanType = SCAN_ACTIVE; @@ -10999,6 +11557,8 @@ void report_survey_event(_adapter *padapter, union recv_frame *precv_frame) struct cmd_priv *pcmdpriv; /* u8 *pframe = precv_frame->u.hdr.rx_data; */ /* uint len = precv_frame->u.hdr.len; */ + RT_CHANNEL_INFO *chset = adapter_to_chset(padapter); + int ch_set_idx = -1; if (!padapter) return; @@ -11044,6 +11604,15 @@ void report_survey_event(_adapter *padapter, union recv_frame *precv_frame) process_80211d(padapter, &psurvey_evt->bss); #endif +#ifdef CONFIG_DFS + ch_set_idx = rtw_chset_search_ch(chset, psurvey_evt->bss.Configuration.DSConfig); + if (ch_set_idx >= 0) { + if (psurvey_evt->bss.Ssid.SsidLength == 0 + || is_all_null(psurvey_evt->bss.Ssid.Ssid, psurvey_evt->bss.Ssid.SsidLength) == _TRUE) + chset[ch_set_idx].hidden_bss_cnt++; + } +#endif + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); pmlmeext->sitesurvey_res.bss_cnt++; @@ -11373,7 +11942,9 @@ bool rtw_port_switch_chk(_adapter *adapter) /* GC should use port0 for p2p ps */ if (((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) && (if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) +#ifdef CONFIG_P2P && !rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE) +#endif && !check_fwstate(&if_port1->mlmepriv, WIFI_UNDER_WPS) ) { RTW_INFO("%s "ADPT_FMT" is GC\n", __func__, ADPT_ARG(if_port1)); @@ -11585,6 +12156,7 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) } #ifdef CONFIG_ARP_KEEP_ALIVE pmlmepriv->bGetGateway = 1; + pmlmepriv->GetGatewayTryCnt = 0; #endif if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { @@ -11624,6 +12196,10 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) psta->wireless_mode = pmlmeext->cur_wireless_mode; +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT + rtw_hal_set_default_port_id_cmd(padapter, psta->mac_id); +#endif + /* set per sta rate after updating HT cap. */ set_sta_rate(padapter, psta); @@ -11653,7 +12229,9 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) } #ifdef CONFIG_LPS + #ifndef CONFIG_FW_MULTI_PORT_SUPPORT if (get_hw_port(padapter) == HW_PORT0) + #endif rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_CONNECT, 0); #endif @@ -11733,17 +12311,17 @@ void _linked_info_dump(_adapter *padapter) struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); HAL_DATA_TYPE *HalData = GET_HAL_DATA(padapter); - int UndecoratedSmoothedPWDB = 0; + int undecorated_smoothed_pwdb = 0; if (padapter->bLinkInfoDump) { RTW_INFO("\n============["ADPT_FMT"] linked status check ===================\n", ADPT_ARG(padapter)); if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { - rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB); + rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &undecorated_smoothed_pwdb); - RTW_INFO("AP[" MAC_FMT "] - UndecoratedSmoothedPWDB:%d\n", - MAC_ARG(padapter->mlmepriv.cur_network.network.MacAddress), UndecoratedSmoothedPWDB); + RTW_INFO("AP[" MAC_FMT "] - undecorated_smoothed_pwdb:%d\n", + MAC_ARG(padapter->mlmepriv.cur_network.network.MacAddress), undecorated_smoothed_pwdb); } else if ((pmlmeinfo->state & 0x03) == _HW_STATE_AP_) { _irqL irqL; _list *phead, *plist; @@ -11758,8 +12336,8 @@ void _linked_info_dump(_adapter *padapter) psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); plist = get_next(plist); - RTW_INFO("STA[" MAC_FMT "]:UndecoratedSmoothedPWDB:%d\n", - MAC_ARG(psta->hwaddr), psta->rssi_stat.UndecoratedSmoothedPWDB); + RTW_INFO("STA[" MAC_FMT "]:undecorated_smoothed_pwdb:%d\n", + MAC_ARG(psta->hwaddr), psta->rssi_stat.undecorated_smoothed_pwdb); } _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); @@ -11774,6 +12352,12 @@ void _linked_info_dump(_adapter *padapter) } +/******************************************************************** + +When station does not receive any packet in MAX_CONTINUAL_NORXPACKET_COUNT*2 seconds, +recipient station will teardown the block ack by issuing DELBA frame. + +*********************************************************************/ void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer) { int i = 0; @@ -11791,9 +12375,9 @@ void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer) */ if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) { for (i = 0; i < TID_NUM ; i++) { - if (sta_rx_data_qos_pkts(psta, i) == sta_last_rx_data_qos_pkts(psta, i)) { - if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) { - if (psta->recvreorder_ctrl[i].enable) { + if ((psta->recvreorder_ctrl[i].enable) && + (sta_rx_data_qos_pkts(psta, i) == sta_last_rx_data_qos_pkts(psta, i)) ) { + if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) { /* send a DELBA frame to the peer STA with the Reason Code field set to TIMEOUT */ if (!from_timer) ret = issue_del_ba_ex(padapter, psta->hwaddr, i, 39, 0, 3, 1); @@ -11803,8 +12387,7 @@ void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer) if (ret != _FAIL) psta->recvreorder_ctrl[i].ampdu_size = RX_AMPDU_SIZE_INVALID; rtw_reset_continual_no_rx_packet(psta, i); - } - } + } } else { /* The inactivity timer is reset when MPDUs to the TID is received. */ rtw_reset_continual_no_rx_packet(psta, i); @@ -11869,7 +12452,7 @@ u8 chk_adhoc_peer_is_alive(struct sta_info *psta) /*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/ ", expire_to:%u\n" , MAC_ARG(psta->hwaddr) - , psta->rssi_stat.UndecoratedSmoothedPWDB + , psta->rssi_stat.undecorated_smoothed_pwdb , STA_RX_PKTS_DIFF_ARG(psta) , psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts , psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts @@ -11997,10 +12580,15 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct sta_priv *pstapriv = &padapter->stapriv; -#ifdef CONFIG_ARP_KEEP_ALIVE +#if defined(CONFIG_ARP_KEEP_ALIVE) || defined(CONFIG_LAYER2_ROAMING) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; #endif +#ifdef CONFIG_LAYER2_ROAMING + struct recv_priv *precvpriv = &padapter->recvpriv; +#endif + if (padapter->registrypriv.mp_mode == _TRUE) + return; if (is_client_associated_to_ap(padapter)) { /* linked infrastructure client mode */ @@ -12009,6 +12597,17 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) int rx_chk_limit; int link_count_limit; +#ifdef CONFIG_LAYER2_ROAMING + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) { + RTW_INFO("signal_strength_data.avg_val = %d\n", precvpriv->signal_strength_data.avg_val); + if (precvpriv->signal_strength_data.avg_val < pmlmepriv->roam_rssi_threshold) { + pmlmepriv->need_to_roam = _TRUE; + rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM); + } else { + pmlmepriv->need_to_roam = _FALSE; + } + } +#endif #ifdef CONFIG_MCC_MODE /* * due to tx ps null date to ao, so ap doest not tx pkt to driver @@ -12027,8 +12626,9 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) rx_chk_limit = 8; #endif #ifdef CONFIG_ARP_KEEP_ALIVE - if (!from_timer && pmlmepriv->bGetGateway == 1) { - RTW_INFO("do rtw_gw_addr_query()"); + if (!from_timer && pmlmepriv->bGetGateway == 1 && pmlmepriv->GetGatewayTryCnt < 3) { + RTW_INFO("do rtw_gw_addr_query() : %d\n", pmlmepriv->GetGatewayTryCnt); + pmlmepriv->GetGatewayTryCnt++; if (rtw_gw_addr_query(padapter) == 0) pmlmepriv->bGetGateway = 0; else { @@ -12070,9 +12670,10 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) is_p2p_enable = !rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE); #endif +#ifdef CONFIG_ISSUE_DELBA_WHEN_NO_TRAFFIC /*issue delba when ap does not tx data packet that is Broadcom ap */ rtw_delba_check(padapter, psta, from_timer); - +#endif if (chk_ap_is_alive(padapter, psta) == _FALSE) rx_chk = _FAIL; @@ -12081,18 +12682,25 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) #if defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER) if (pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL) -#ifdef CONFIG_MCC_MODE - /* Driver don't know operation channel under MCC*/ - /* So driver don't do KEEP_ALIVE_CHECK */ - && (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) -#endif - ) { - u8 backup_oper_channel = 0; + #ifdef CONFIG_MCC_MODE + /* Driver don't know operation channel under MCC*/ + /* So driver don't do KEEP_ALIVE_CHECK */ + && (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) + #endif + ) { + u8 backup_ch = 0, backup_bw = 0, backup_offset = 0; + u8 union_ch = 0, union_bw, union_offset; + + if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) + || pmlmeext->cur_channel != union_ch) + goto bypass_active_keep_alive; /* switch to correct channel of current network before issue keep-alive frames */ if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { - backup_oper_channel = rtw_get_oper_ch(padapter); - SelectChannel(padapter, pmlmeext->cur_channel); + backup_ch = rtw_get_oper_ch(padapter); + backup_bw = rtw_get_oper_bw(padapter); + backup_offset = rtw_get_oper_choffset(padapter); + set_channel_bwmode(padapter, union_ch, union_offset, union_bw); } if (rx_chk != _SUCCESS) @@ -12106,9 +12714,11 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) } /* back to the original operation channel */ - if (backup_oper_channel > 0) - SelectChannel(padapter, backup_oper_channel); + if (backup_ch > 0) + set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw); +bypass_active_keep_alive: + ; } else #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ { @@ -12203,8 +12813,9 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) } -void survey_timer_hdl(_adapter *padapter) +void survey_timer_hdl(void *ctx) { + _adapter *padapter = (_adapter *)ctx; struct cmd_obj *cmd; struct sitesurvey_parm *psurveyPara; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; @@ -12235,15 +12846,23 @@ void survey_timer_hdl(_adapter *padapter) return; } -void link_timer_hdl(_adapter *padapter) +void link_timer_hdl(void *ctx) { + _adapter *padapter = (_adapter *)ctx; /* static unsigned int rx_pkt = 0; */ /* static u64 tx_cnt = 0; */ /* struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); */ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); /* struct sta_priv *pstapriv = &padapter->stapriv; */ +#ifdef CONFIG_RTW_80211R + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); +#endif + if (rtw_sta_linking_test_force_fail()) + RTW_INFO("rtw_sta_linking_test_force_fail\n"); if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) { RTW_INFO("link_timer_hdl:no beacon while connecting\n"); @@ -12273,20 +12892,38 @@ void link_timer_hdl(_adapter *padapter) /* re-assoc timer */ if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) { pmlmeinfo->state = WIFI_FW_NULL_STATE; +#ifdef CONFIG_RTW_80211R + if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); + if (psta) + rtw_free_stainfo(padapter, psta); + } +#endif report_join_res(padapter, -2); return; } - RTW_INFO("link_timer_hdl: assoc timeout and try again\n"); - issue_assocreq(padapter); +#ifdef CONFIG_RTW_80211R + if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + RTW_INFO("link_timer_hdl: reassoc timeout and try again\n"); + issue_reassocreq(padapter); + } else +#endif + { + RTW_INFO("link_timer_hdl: assoc timeout and try again\n"); + issue_assocreq(padapter); + } + set_link_timer(pmlmeext, REASSOC_TO); } return; } -void addba_timer_hdl(struct sta_info *psta) +void addba_timer_hdl(void *ctx) { + struct sta_info *psta = (struct sta_info *)ctx; + #ifdef CONFIG_80211N_HT struct ht_priv *phtpriv; @@ -12364,15 +13001,16 @@ void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short re void clnt_sa_query_timeout(_adapter *padapter) { - rtw_disassoc_cmd(padapter, 0, _TRUE); + rtw_disassoc_cmd(padapter, 0, 0); rtw_indicate_disconnect(padapter, 0, _FALSE); rtw_free_assoc_resources(padapter, 1); RTW_INFO("SA query timeout client disconnect\n"); } -void sa_query_timer_hdl(struct sta_info *psta) +void sa_query_timer_hdl(void *ctx) { + struct sta_info *psta = (struct sta_info *)ctx; _adapter *padapter = psta->padapter; _irqL irqL; struct sta_priv *pstapriv = &padapter->stapriv; @@ -12387,6 +13025,207 @@ void sa_query_timer_hdl(struct sta_info *psta) #endif /* CONFIG_IEEE80211W */ +#ifdef CONFIG_RTW_80211R +void start_clnt_ft_action(_adapter *padapter, u8 *pTargetAddr) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + rtw_set_ft_status(padapter, RTW_FT_REQUESTING_STA); + issue_action_ft_request(padapter, pTargetAddr); + _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO); +} + +void ft_link_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + ft_priv *pftpriv = &pmlmepriv->ftpriv; + + if (rtw_chk_ft_status(padapter, RTW_FT_REQUESTING_STA)) { + if (pftpriv->ft_req_retry_cnt < FT_ACTION_REQ_LIMIT) { + pftpriv->ft_req_retry_cnt++; + issue_action_ft_request(padapter, (u8 *)pmlmepriv->roam_network->network.MacAddress); + _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO); + } else { + pftpriv->ft_req_retry_cnt = 0; + + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) + rtw_set_ft_status(padapter, RTW_FT_ASSOCIATED_STA); + else + rtw_reset_ft_status(padapter); + } + } +} + +void ft_roam_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress + , WLAN_REASON_ACTIVE_ROAM, _FALSE); +} + +void issue_action_ft_request(_adapter *padapter, u8 *pTargetAddr) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct xmit_frame *pmgntframe = NULL; + struct rtw_ieee80211_hdr *pwlanhdr = NULL; + struct pkt_attrib *pattrib = NULL; + ft_priv *pftpriv = NULL; + u8 *pframe = NULL; + u8 category = RTW_WLAN_CATEGORY_FT; + u8 action = RTW_WLAN_ACTION_FT_REQUEST; + u8 is_ft_roaming_with_rsn_ie = _TRUE; + u8 *pie = NULL; + u16 *fctrl = NULL; + u32 ft_ie_len = 0; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + + _rtw_memcpy(pframe, adapter_mac_addr(padapter), ETH_ALEN); + pframe += ETH_ALEN; + pattrib->pktlen += ETH_ALEN; + + _rtw_memcpy(pframe, pTargetAddr, ETH_ALEN); + pframe += ETH_ALEN; + pattrib->pktlen += ETH_ALEN; + + pftpriv = &pmlmepriv->ftpriv; + pie = rtw_get_ie(pftpriv->updated_ft_ies, EID_WPA2, &ft_ie_len, pftpriv->updated_ft_ies_len); + if (pie) + pframe = rtw_set_ie(pframe, EID_WPA2, ft_ie_len, pie+2, &(pattrib->pktlen)); + else + is_ft_roaming_with_rsn_ie = _FALSE; + + pie = rtw_get_ie(pftpriv->updated_ft_ies, _MDIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); + if (pie) + pframe = rtw_set_ie(pframe, _MDIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); + + pie = rtw_get_ie(pftpriv->updated_ft_ies, _FTIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); + if (pie && is_ft_roaming_with_rsn_ie) + pframe = rtw_set_ie(pframe, _FTIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); + + pattrib->last_txcmdsz = pattrib->pktlen; + dump_mgntframe(padapter, pmgntframe); +} + +void report_ft_event(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + ft_priv *pftpriv = &pmlmepriv->ftpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + struct cfg80211_ft_event_params ft_evt_parms; + _irqL irqL; + + _rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms)); + rtw_update_ft_stainfo(padapter, pnetwork); + + if (!pnetwork) + goto err_2; + + ft_evt_parms.ies_len = pftpriv->ft_event.ies_len; + ft_evt_parms.ies = rtw_zmalloc(ft_evt_parms.ies_len); + if (ft_evt_parms.ies) + _rtw_memcpy((void *)ft_evt_parms.ies, pftpriv->ft_event.ies, ft_evt_parms.ies_len); + else + goto err_2; + + ft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN); + if (ft_evt_parms.target_ap) + _rtw_memcpy((void *)ft_evt_parms.target_ap, pnetwork->MacAddress, ETH_ALEN); + else + goto err_1; + + ft_evt_parms.ric_ies = pftpriv->ft_event.ric_ies; + ft_evt_parms.ric_ies_len = pftpriv->ft_event.ric_ies_len; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + rtw_set_ft_status(padapter, RTW_FT_AUTHENTICATED_STA); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + rtw_cfg80211_ft_event(padapter, &ft_evt_parms); + RTW_INFO("FT: report_ft_event\n"); + rtw_mfree((u8 *)pftpriv->ft_event.target_ap, ETH_ALEN); +err_1: + rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len); +err_2: + return; +} + +void report_ft_reassoc_event(_adapter *padapter, u8 *pMacAddr) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_obj *pcmd_obj = NULL; + struct stassoc_event *passoc_sta_evt = NULL; + struct C2HEvent_Header *pc2h_evt_hdr = NULL; + u8 *pevtcmd = NULL; + u32 cmdsz = 0; + + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) + return; + + cmdsz = (sizeof(struct stassoc_event) + sizeof(struct C2HEvent_Header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; + } + + _rtw_init_listhead(&pcmd_obj->list); + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct stassoc_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_FT_REASSOC); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + passoc_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct C2HEvent_Header)); + _rtw_memcpy((unsigned char *)(&(passoc_sta_evt->macaddr)), pMacAddr, ETH_ALEN); + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); +} +#endif + u8 NULL_hdl(_adapter *padapter, u8 *pbuf) { return H2C_SUCCESS; @@ -12511,6 +13350,10 @@ u8 setopmode_hdl(_adapter *padapter, u8 *pbuf) else type = _HW_STATE_NOLINK_; +#ifdef CONFIG_AP_PORT_SWAP + rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, (u8 *)(&type)); +#endif + rtw_hal_set_hwreg(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type)); #ifdef CONFIG_AUTO_AP_MODE @@ -12533,7 +13376,8 @@ u8 setopmode_hdl(_adapter *padapter, u8 *pbuf) } #ifdef CONFIG_BT_COEXIST - if (psetop->mode == Ndis802_11APMode) { + if (psetop->mode == Ndis802_11APMode || + psetop->mode == Ndis802_11Monitor) { /* Do this after port switch to */ /* prevent from downloading rsvd page to wrong port */ rtw_btcoex_MediaStatusNotify(padapter, 1); /* connect */ @@ -12576,14 +13420,6 @@ u8 createbss_hdl(_adapter *padapter, u8 *pbuf) pmlmeinfo->agg_enable_bitmap = 0; pmlmeinfo->candidate_tid_bitmap = 0; - /* config the initial gain under linking, need to write the BB registers */ - /* initialgain = 0x1E; */ - /*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/ - - /* disable dynamic functions, such as high power, DIG */ - rtw_phydm_ability_backup(padapter); - rtw_phydm_func_disable_all(padapter); - /* cancel link timer */ _cancel_timer_ex(&pmlmeext->link_timer); @@ -12825,6 +13661,8 @@ u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf) rtw_free_uc_swdec_pending_queue(padapter); + rtw_sta_mstatus_report(padapter); + return H2C_SUCCESS; } @@ -12898,6 +13736,11 @@ u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_nu #ifndef RTW_SCAN_SPARSE_CH_NUM_BG #define RTW_SCAN_SPARSE_CH_NUM_BG 4 #endif +#ifdef CONFIG_LAYER2_ROAMING +#ifndef RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE +#define RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE 1 +#endif +#endif #define SCAN_SPARSE_CH_NUM_INVALID 255 @@ -12946,6 +13789,13 @@ u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_nu max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_BG); #endif +#if defined(CONFIG_LAYER2_ROAMING) && defined(RTW_SCAN_SPARSE_ROAMING_ACTIVE) + if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) { + if (busy_traffic == _TRUE && adapter->mlmepriv.need_to_roam == _TRUE) + max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE); + } +#endif + if (max_allow_ch != SCAN_SPARSE_CH_NUM_INVALID) { int i; @@ -12983,7 +13833,7 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel int scan_ch_num = 0; int set_idx; u8 chan; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); /* clear first */ _rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel) * out_num); @@ -12995,11 +13845,13 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel if (0) RTW_INFO(FUNC_ADPT_FMT" "CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(&in[i])); - set_idx = rtw_ch_set_search_ch(pmlmeext->channel_set, in[i].hw_value); - if (in[i].hw_value && !(in[i].flags & RTW_IEEE80211_CHAN_DISABLED) - && set_idx >= 0 - && rtw_mlme_band_check(padapter, in[i].hw_value) == _TRUE - ) { + if (!in[i].hw_value || (in[i].flags & RTW_IEEE80211_CHAN_DISABLED)) + continue; + if (rtw_mlme_band_check(padapter, in[i].hw_value) == _FALSE) + continue; + + set_idx = rtw_chset_search_ch(rfctl->channel_set, in[i].hw_value); + if (set_idx >= 0) { if (j >= out_num) { RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n", FUNC_ADPT_ARG(padapter), out_num); @@ -13008,7 +13860,7 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel _rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel)); - if (pmlmeext->channel_set[set_idx].ScanType == SCAN_PASSIVE) + if (rfctl->channel_set[set_idx].ScanType == SCAN_PASSIVE) out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; j++; @@ -13019,8 +13871,8 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel /* if out is empty, use channel_set as default */ if (j == 0) { - for (i = 0; i < pmlmeext->max_chan_nums; i++) { - chan = pmlmeext->channel_set[i].ChannelNum; + for (i = 0; i < rfctl->max_chan_nums; i++) { + chan = rfctl->channel_set[i].ChannelNum; if (rtw_mlme_band_check(padapter, chan) == _TRUE) { if (rtw_mlme_ignore_chan(padapter, chan) == _TRUE) continue; @@ -13036,7 +13888,7 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel out[j].hw_value = chan; - if (pmlmeext->channel_set[i].ScanType == SCAN_PASSIVE) + if (rfctl->channel_set[i].ScanType == SCAN_PASSIVE) out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; j++; @@ -13053,10 +13905,16 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm) { struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res; + RT_CHANNEL_INFO *chset = adapter_to_chset(adapter); int i; ss->bss_cnt = 0; ss->channel_idx = 0; +#ifdef CONFIG_DFS + ss->dfs_ch_ssid_scan = 0; +#endif + ss->igi_scan = 0; + ss->igi_before_scan = 0; #ifdef CONFIG_SCAN_BACKOP ss->scan_cnt = 0; #endif @@ -13064,10 +13922,12 @@ static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm ss->is_sw_antdiv_bl_scan = 0; #endif + ss->ssid_num = 0; for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { if (parm->ssid[i].SsidLength) { _rtw_memcpy(ss->ssid[i].Ssid, parm->ssid[i].Ssid, IW_ESSID_MAX_SIZE); ss->ssid[i].SsidLength = parm->ssid[i].SsidLength; + ss->ssid_num++; } else ss->ssid[i].SsidLength = 0; } @@ -13077,6 +13937,11 @@ static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm , parm->ch, parm->ch_num ); +#ifdef CONFIG_DFS + for (i = 0; i < MAX_CHANNEL_NUM; i++) + chset[i].hidden_bss_cnt = 0; +#endif + ss->scan_mode = parm->scan_mode; } @@ -13088,7 +13953,8 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE * struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; struct ss_res *ss = &pmlmeext->sitesurvey_res; - + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + int ch_set_idx; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &padapter->wdinfo; #endif @@ -13108,12 +13974,10 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE * * Commented by Albert 2011/06/03 * The driver is in the find phase, it should go through the social channel. */ - int ch_set_idx; - scan_ch = pwdinfo->social_chan[ss->channel_idx]; - ch_set_idx = rtw_ch_set_search_ch(pmlmeext->channel_set, scan_ch); + ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scan_ch); if (ch_set_idx >= 0) - scan_type = pmlmeext->channel_set[ch_set_idx].ScanType; + scan_type = rfctl->channel_set[ch_set_idx].ScanType; else scan_type = SCAN_ACTIVE; } else @@ -13121,6 +13985,20 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE * { struct rtw_ieee80211_channel *ch; +#ifdef CONFIG_DFS + if (ss->channel_idx != 0 && ss->dfs_ch_ssid_scan == 0 + && pmlmeext->sitesurvey_res.ssid_num + && rtw_is_dfs_ch(ss->ch[ss->channel_idx - 1].hw_value) + ) { + ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, ss->ch[ss->channel_idx - 1].hw_value); + if (ch_set_idx != -1 && rfctl->channel_set[ch_set_idx].hidden_bss_cnt) { + ss->channel_idx--; + ss->dfs_ch_ssid_scan = 1; + } + } else + ss->dfs_ch_ssid_scan = 0; +#endif /* CONFIG_DFS */ + if (ss->channel_idx < ss->ch_num) { ch = &ss->ch[ss->channel_idx]; scan_ch = ch->hw_value; @@ -13132,22 +14010,17 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE * next_state = SCAN_PROCESS; #ifdef CONFIG_SCAN_BACKOP { - u8 sta_num; - u8 ld_sta_num; - u8 ap_num; - u8 ld_ap_num; + struct mi_state mstate; u8 backop_flags = 0; - rtw_mi_status(padapter, &sta_num, &ld_sta_num, NULL, &ap_num, &ld_ap_num, NULL); + rtw_mi_status(padapter, &mstate); - if ((ld_sta_num > 0 && mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) - || (sta_num > 0 && mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN_NL)) - ) + if ((MSTATE_STA_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) + || (MSTATE_STA_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN_NL))) backop_flags |= mlmeext_scan_backop_flags_sta(pmlmeext); - if ((ld_ap_num > 0 && mlmeext_chk_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN)) - || (ap_num > 0 && mlmeext_chk_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN_NL)) - ) + if ((MSTATE_AP_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN)) + || (MSTATE_AP_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN_NL))) backop_flags |= mlmeext_scan_backop_flags_ap(pmlmeext); if (backop_flags) { @@ -13220,6 +14093,8 @@ void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType) { struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct ss_res *ss = &pmlmeext->sitesurvey_res; + u8 ssid_scan = 0; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); @@ -13241,30 +14116,26 @@ void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType) } #endif +#ifdef CONFIG_DFS + if (ScanType == SCAN_PASSIVE && ss->dfs_ch_ssid_scan) + ssid_scan = 1; + else +#endif if (ScanType == SCAN_ACTIVE) { #ifdef CONFIG_P2P - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) || - rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) - ) { + #ifdef CONFIG_IOCTL_CFG80211 + if (rtw_cfg80211_is_p2p_scan(padapter)) + #else + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)) + #endif + { issue_probereq_p2p(padapter, NULL); issue_probereq_p2p(padapter, NULL); issue_probereq_p2p(padapter, NULL); } else #endif /* CONFIG_P2P */ { - int i; - - for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { - if (pmlmeext->sitesurvey_res.ssid[i].SsidLength) { - /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */ - if (padapter->registrypriv.wifi_spec) - issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); - else - issue_probereq_ex(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL, 0, 0, 0, 0); - issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); - } - } - if (pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE) { /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */ if (padapter->registrypriv.wifi_spec) @@ -13273,6 +14144,23 @@ void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType) issue_probereq_ex(padapter, NULL, NULL, 0, 0, 0, 0); issue_probereq(padapter, NULL, NULL); } + + ssid_scan = 1; + } + } + + if (ssid_scan) { + int i; + + for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { + if (pmlmeext->sitesurvey_res.ssid[i].SsidLength) { + /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */ + if (padapter->registrypriv.wifi_spec) + issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); + else + issue_probereq_ex(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL, 0, 0, 0, 0); + issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); + } } } } else { @@ -13357,6 +14245,10 @@ u8 sitesurvey_ps_annc(_adapter *padapter, bool ps) { u8 ps_anc = 0; + #ifdef CONFIG_AP_MODE + /*mac-id sleep or wake-up for AP mode*/ + rtw_mi_ap_acdata_control(padapter, ps); + #endif/*CONFIG_AP_MODE*/ if (rtw_mi_issue_nulldata(padapter, NULL, ps, 3, 500)) ps_anc = 1; return ps_anc; @@ -13399,30 +14291,56 @@ u8 sitesurvey_ps_annc(struct dvobj_priv *dvobj, bool ps) } #endif -void sitesurvey_set_igi(_adapter *adapter, bool enter) +void sitesurvey_set_igi(_adapter *adapter) { + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct ss_res *ss = &mlmeext->sitesurvey_res; u8 igi; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &adapter->wdinfo; #endif - if (enter) { -#ifdef CONFIG_P2P -#ifdef CONFIG_IOCTL_CFG80211 + switch (mlmeext_scan_state(mlmeext)) { + case SCAN_ENTER: + #ifdef CONFIG_P2P + #ifdef CONFIG_IOCTL_CFG80211 if (adapter_wdev_data(adapter)->p2p_enabled == _TRUE && pwdinfo->driver_interface == DRIVER_CFG80211) igi = 0x30; else -#endif /* CONFIG_IOCTL_CFG80211 */ - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) - igi = 0x28; - else -#endif /* CONFIG_P2P */ - igi = 0x1e; - } else { - igi = 0xff; /* restore RX GAIN */ - } + #endif /* CONFIG_IOCTL_CFG80211 */ + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + igi = 0x28; + else + #endif /* CONFIG_P2P */ + igi = 0x1e; - rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE); + /* record IGI status */ + ss->igi_scan = igi; + rtw_hal_get_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &ss->igi_before_scan, NULL); + + /* disable DIG and set IGI for scan */ + rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE); + break; + case SCAN_COMPLETE: + case SCAN_TO_P2P_LISTEN: + /* enable DIG and restore IGI */ + igi = 0xff; + rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE); + break; +#ifdef CONFIG_SCAN_BACKOP + case SCAN_BACKING_OP: + /* write IGI for op channel when DIG is not enabled */ + odm_write_dig(GET_ODM(adapter), ss->igi_before_scan); + break; + case SCAN_LEAVE_OP: + /* write IGI for scan when DIG is not enabled */ + odm_write_dig(GET_ODM(adapter), ss->igi_scan); + break; +#endif /* CONFIG_SCAN_BACKOP */ + default: + rtw_warn_on(1); + break; + } } void sitesurvey_set_msr(_adapter *adapter, bool enter) { @@ -13453,6 +14371,14 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct ss_res *ss = &pmlmeext->sitesurvey_res; +#ifdef CONFIG_CHNL_LOAD_MAGT + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct PHY_DM_STRUCT *p_dm_odm = &pHalData->odmpriv; + u16 *channel_clm = pHalData->clm_result; + int clm_ch_index; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); +#endif u8 val8; #ifdef CONFIG_P2P @@ -13497,8 +14423,7 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) /* apply rx ampdu setting */ if (ss->rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID - || ss->rx_ampdu_size != RX_AMPDU_SIZE_INVALID - ) + || ss->rx_ampdu_size != RX_AMPDU_SIZE_INVALID) rtw_rx_ampdu_apply(padapter); /* clear HW TX queue before scan */ @@ -13521,11 +14446,11 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) * HW register and DM setting for enter scan */ - /* config the initial gain under scanning */ - sitesurvey_set_igi(padapter, 1); - - /* disable dynamic functions, such as high power, DIG */ rtw_phydm_ability_backup(padapter); + + sitesurvey_set_igi(padapter); + + /* config dynamic functions for off channel */ rtw_phydm_func_for_offchannel(padapter); /* set MSR to no link state */ sitesurvey_set_msr(padapter, _TRUE); @@ -13541,6 +14466,9 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) RT_SCAN_TYPE scan_type; u8 next_state; u32 scan_ms; +#ifdef CONFIG_CHNL_LOAD_MAGT + bool ret; +#endif #ifdef CONFIG_AUTO_CHNL_SEL_NHM if ((ACS_ENABLE == GET_ACS_STATE(padapter)) && (0 != rtw_get_acs_channel(padapter))) { @@ -13551,6 +14479,35 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) #endif next_state = sitesurvey_pick_ch_behavior(padapter, &scan_ch, &scan_type); + +#ifdef CONFIG_CHNL_LOAD_MAGT + if (padapter->clm_flag == TRUE) { + + if ((next_state == SCAN_COMPLETE) || (ss->channel_idx != 0 && next_state == SCAN_PROCESS)) { + + ret = phydm_check_clm_ready(p_dm_odm); + /*RTW_INFO("DBG_CLM %s ; ss->ch = %u\n", __FUNCTION__,ss->ch[ss->channel_idx-1].hw_value);*/ + if (ret == true) { + ccx_info->echo_CLM_en = false; + phydm_get_clm_result(p_dm_odm); + clm_ch_index = rtw_chset_search_ch(rfctl->channel_set, ss->ch[ss->channel_idx-1].hw_value); + channel_clm[clm_ch_index] = 0; + channel_clm[clm_ch_index] = ccx_info->CLM_result; + RTW_INFO("DBG_CLM %s :clm_index = %d ; ch = %u;CLM_result = %d\n", __FUNCTION__, clm_ch_index, ss->ch[ss->channel_idx-1].hw_value, ccx_info->CLM_result); + } else + RTW_INFO("DBG_CLM %s : CLM is not ready\n", __FUNCTION__); +/* + RTW_INFO("DBG_CLM %s : ready = %d\n", __FUNCTION__, phydm_check_clm_ready(p_dm_odm)); + RTW_INFO("DBG_CLM %s : ODM_REG_CLM_11N reg 890= 0x%x\n", __FUNCTION__, rtw_read32(padapter, ODM_REG_CLM_11N)); + RTW_INFO("DBG_CLM %s : ODM_REG_CCX_PERIOD_11N reg 894= 0x%x\n", __FUNCTION__, rtw_read32(padapter, ODM_REG_CCX_PERIOD_11N)); + RTW_INFO("DBG_CLM %s : ODM_REG_CLM_READY_11N reg 8B4= 0x%x\n", __FUNCTION__, rtw_read32(padapter, ODM_REG_CLM_READY_11N)); + RTW_INFO("DBG_CLM %s : end_time =%d\n", __FUNCTION__, rtw_get_current_time()); + RTW_INFO("DBG_CLM %s : end_time =%d ms\n", __FUNCTION__, rtw_systime_to_ms(rtw_get_current_time())); +*/ + } + } +#endif + if (next_state != SCAN_PROCESS) { #ifdef CONFIG_AUTO_CHNL_SEL_NHM if (ACS_ENABLE == GET_ACS_STATE(padapter)) { @@ -13622,6 +14579,32 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) } #endif +#ifdef CONFIG_CHNL_LOAD_MAGT + + if (padapter->clm_flag == TRUE) { + + scan_ms = ss->scan_ch_ms; + /*beacause scan_ms 200ms ,clm only can test less than 195ms ,otherwise 0x8b4[16] will not be true;difference=5ms*/ + ccx_info->echo_CLM_en = TRUE; + + ccx_info->CLM_period = pHalData->clm_period; /*if CLM_period=0xC350; then 50000*4us=200ms*/ + phydm_clm_setting(p_dm_odm); + phydm_clm_trigger(p_dm_odm); +/* + RTW_INFO("DBG_CLM %s : scan_ms =%u clm_period = 0x%x\n",__FUNCTION__, scan_ms, ccx_info->CLM_period); + RTW_INFO("DBG_CLM %s : current_index = %d;cuurent_ch =%u\n",__FUNCTION__, ss->channel_idx,scan_ch); + RTW_INFO("DBG_CLM %s : start_time =%d\n",__FUNCTION__, rtw_get_current_time()); + RTW_INFO("DBG_CLM %s : start_time =%d ms\n",__FUNCTION__, rtw_systime_to_ms(rtw_get_current_time())); + RTW_INFO(FUNC_ADPT_FMT" %s ch=%u at %dms\n" + , FUNC_ADPT_ARG(padapter) + , mlmeext_scan_state_str(pmlmeext) + ,scan_ch + , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) + ); +*/ + } +#endif + set_survey_timer(pmlmeext, scan_ms); break; } @@ -13657,7 +14640,7 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) { - sitesurvey_set_igi(padapter, 0); + sitesurvey_set_igi(padapter); sitesurvey_ps_annc(padapter, 0); } @@ -13707,10 +14690,8 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) * HW register and DM setting for enter scan */ - if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) { - /* config the initial gain under scanning */ - sitesurvey_set_igi(padapter, 1); - } + if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) + sitesurvey_set_igi(padapter); sitesurvey_set_msr(padapter, _TRUE); @@ -13750,7 +14731,7 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) /* turn on phy-dynamic functions */ rtw_phydm_ability_restore(padapter); - sitesurvey_set_igi(padapter, 0); + sitesurvey_set_igi(padapter); mlmeext_set_scan_state(pmlmeext, SCAN_P2P_LISTEN); _set_timer(&pwdinfo->find_phase_timer, (u32)((u32)pwdinfo->listen_dwell * 100)); @@ -13790,7 +14771,7 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) /* turn on phy-dynamic functions */ rtw_phydm_ability_restore(padapter); - sitesurvey_set_igi(padapter, 0); + sitesurvey_set_igi(padapter); #ifdef CONFIG_MCC_MODE /* start MCC fail, then tx null data */ @@ -14066,7 +15047,6 @@ u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf) /* pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid); */ /* psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid); */ issue_addba_req(padapter, pparm->addr, (u8)pparm->tid); - /* _set_timer(&pmlmeext->ADDBA_timer, ADDBA_TO); */ _set_timer(&psta->addba_retry_timer, ADDBA_TO); } #ifdef CONFIG_TDLS @@ -14132,7 +15112,6 @@ u8 chk_bmc_sleepq_cmd(_adapter *padapter) struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); u8 res = _SUCCESS; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -14146,7 +15125,6 @@ u8 chk_bmc_sleepq_cmd(_adapter *padapter) exit: - _func_exit_; return res; } @@ -14161,7 +15139,6 @@ u8 set_tx_beacon_cmd(_adapter *padapter) u8 res = _SUCCESS; int len_diff = 0; - _func_enter_; ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (ph2c == NULL) { @@ -14192,7 +15169,6 @@ u8 set_tx_beacon_cmd(_adapter *padapter) exit: - _func_exit_; return res; } @@ -14218,7 +15194,6 @@ u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf) #ifdef CHECK_EVENT_SEQ /* checking event sequence... */ if (evt_seq != (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f)) { - RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("Evetn Seq Error! %d vs %d\n", (evt_seq & 0x7f), (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f))); pevt_priv->event_seq = (evt_seq + 1) & 0x7f; @@ -14228,7 +15203,6 @@ u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf) /* checking if event code is valid */ if (evt_code >= MAX_C2HEVT) { - RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\nEvent Code(%d) mismatch!\n", evt_code)); goto _abort_event_; } @@ -14236,8 +15210,6 @@ u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf) if ((wlanevents[evt_code].parmsize != 0) && (wlanevents[evt_code].parmsize != evt_sz)) { - RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\nEvent(%d) Parm Size mismatch (%d vs %d)!\n", - evt_code, wlanevents[evt_code].parmsize, evt_sz)); goto _abort_event_; } @@ -14440,8 +15412,8 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res) continue; if (check_fwstate(mlme, WIFI_AP_STATE) - && check_fwstate(mlme, WIFI_ASOC_STATE) - ) { + && check_fwstate(mlme, WIFI_ASOC_STATE) + ) { bool is_grouped = rtw_is_chbw_grouped(u_ch, u_bw, u_offset , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); @@ -14465,10 +15437,9 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res) rtw_start_bss_hdl_after_chbw_decided(iface); } + clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); update_beacon(iface, 0, NULL, _TRUE); } - - clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); } #ifdef CONFIG_DFS_MASTER @@ -14484,10 +15455,11 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res) continue; if (check_fwstate(mlme, WIFI_AP_STATE) - && check_fwstate(mlme, WIFI_ASOC_STATE)) + && check_fwstate(mlme, WIFI_ASOC_STATE) + ) { + clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); update_beacon(iface, 0, NULL, _TRUE); - - clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); + } } #ifdef CONFIG_DFS_MASTER rtw_dfs_master_status_apply(adapter, MLME_STA_DISCONNECTED); @@ -14538,20 +15510,16 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) _adapter *iface; struct mlme_priv *mlme; struct mlme_ext_priv *mlmeext; - u8 sta_num; - u8 ld_sta_num; - u8 lg_sta_num; - u8 ap_num; - u8 ld_ap_num; + struct mi_state mstate; int i; dvobj = adapter_to_dvobj(adapter); - rtw_mi_status_no_self(adapter, &sta_num, &ld_sta_num, &lg_sta_num, &ap_num, &ld_ap_num, NULL); + rtw_mi_status_no_self(adapter, &mstate); RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, ap_num:%u\n" - , FUNC_ADPT_ARG(adapter), ld_sta_num, ap_num); + , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_AP_NUM(&mstate)); - if (!ld_sta_num && !ap_num) { + if (!MSTATE_STA_LD_NUM(&mstate) && !MSTATE_AP_NUM(&mstate)) { /* consider linking STA? */ goto connect_allow_hdl; } @@ -14603,7 +15571,7 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) } #endif /* CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT */ - if ((ld_sta_num + ld_ap_num) >= 2) + if (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) >= 2) connect_allow = _FALSE; RTW_INFO(FUNC_ADPT_FMT" connect_allow:%d\n" @@ -14633,21 +15601,22 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) continue; if (check_fwstate(mlme, WIFI_AP_STATE) - && check_fwstate(mlme, WIFI_ASOC_STATE) - ) { -#ifdef CONFIG_SPCT_CH_SWITCH + && check_fwstate(mlme, WIFI_ASOC_STATE) + ) { + #ifdef CONFIG_SPCT_CH_SWITCH if (1) rtw_ap_inform_ch_switch(iface, pmlmeext->cur_channel , pmlmeext->cur_ch_offset); else -#endif + #endif rtw_sta_flush(iface, _FALSE); rtw_hal_set_hwreg(iface, HW_VAR_CHECK_TXBUF, 0); set_fwstate(mlme, WIFI_OP_CH_SWITCHING); + } else if (check_fwstate(mlme, WIFI_STATION_STATE) && check_fwstate(mlme, WIFI_ASOC_STATE) - ) { - rtw_disassoc_cmd(iface, 500, _FALSE); + ) { + rtw_disassoc_cmd(iface, 500, RTW_CMDF_DIRECTLY); rtw_indicate_disconnect(iface, 0, _FALSE); rtw_free_assoc_resources(iface, 1); } @@ -14696,7 +15665,7 @@ u8 set_ch_hdl(_adapter *padapter, u8 *pbuf) u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf) { struct SetChannelPlan_param *setChannelPlan_param; - struct mlme_priv *mlme = &padapter->mlmepriv; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; if (!pbuf) @@ -14707,11 +15676,14 @@ u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf) if (!rtw_is_channel_plan_valid(setChannelPlan_param->channel_plan)) return H2C_PARAMETERS_ERROR; - mlme->country_ent = setChannelPlan_param->country_ent; - mlme->ChannelPlan = setChannelPlan_param->channel_plan; + rfctl->country_ent = setChannelPlan_param->country_ent; + rfctl->ChannelPlan = setChannelPlan_param->channel_plan; - pmlmeext->max_chan_nums = init_channel_set(padapter, setChannelPlan_param->channel_plan, pmlmeext->channel_set); - init_channel_list(padapter, pmlmeext->channel_set, pmlmeext->max_chan_nums, &pmlmeext->channel_list); + rfctl->max_chan_nums = init_channel_set(padapter, rfctl->ChannelPlan, rfctl->channel_set); + init_channel_list(padapter, rfctl->channel_set, &rfctl->channel_list); +#ifdef CONFIG_TXPWR_LIMIT + rtw_txpwr_init_regd(rfctl); +#endif rtw_hal_set_odm_var(padapter, HAL_ODM_REGULATION, NULL, _TRUE); @@ -14756,17 +15728,17 @@ u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf) rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &sval8); RTW_INFO("DFS detected! Swiching channel to %d!\n", new_ch_no); - SelectChannel(padapter, new_ch_no); + set_channel_bwmode(padapter, new_ch_no, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &gval8); - rtw_disassoc_cmd(padapter, 0, _FALSE); + rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); rtw_indicate_disconnect(padapter, 0, _FALSE); rtw_free_assoc_resources(padapter, 1); rtw_free_network_queue(padapter, _TRUE); - if (((new_ch_no >= 52) && (new_ch_no <= 64)) || ((new_ch_no >= 100) && (new_ch_no <= 140))) - RTW_INFO("Switched to DFS band (ch %02x) again!!\n", new_ch_no); + if (rtw_is_dfs_ch(new_ch_no)) + RTW_INFO("Switched to DFS band (ch %u) again!!\n", new_ch_no); return H2C_SUCCESS; #else @@ -14876,7 +15848,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) ret = issue_tdls_ch_switch_rsp(padapter, &txmgmt, _TRUE); /* If we receive TDLS_CH_SW_REQ at off channel which it's target is AP's channel */ - /* then we just SelectChannel to AP's channel*/ + /* then we just switch to AP's channel*/ if (padapter->mlmeextpriv.cur_channel == pchsw_info->off_ch_num) { rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL); break; @@ -14923,10 +15895,8 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL); } } else { - u8 bcancelled; - if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) - _cancel_timer(&ptdls_sta->ch_sw_timer, &bcancelled); + _cancel_timer_ex(&ptdls_sta->ch_sw_timer); } diff --git a/core/rtw_mp.c b/core/rtw_mp.c index 98054d1..9a024bd 100644 --- a/core/rtw_mp.c +++ b/core/rtw_mp.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_MP_C_ #include #ifdef PLATFORM_FREEBSD @@ -151,6 +146,8 @@ static void _init_mp_priv_(struct mp_priv *pmp_priv) pmp_priv->bRTWSmbCfg = _FALSE; pmp_priv->bloopback = _FALSE; + pmp_priv->bloadefusemap = _FALSE; + pnetwork = &pmp_priv->mp_network.network; _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN); @@ -187,9 +184,6 @@ void mp_wi_callback( NdisGetCurrentSystemTime(&cur_time); /* driver version */ end_time = cur_time.QuadPart / 10; /* The return value is in microsecond */ - RT_TRACE(_module_mp_, _drv_info_, - ("WorkItemActType: %d, time spent: %I64d us\n", - pmp_wi_cntx->param.act_type, (end_time - start_time))); } NdisAcquireSpinLock(&(pmp_wi_cntx->mp_wi_lock)); @@ -354,7 +348,7 @@ s32 init_mp_priv(PADAPTER padapter) } pHalData->AntennaRxPath = pmppriv->antenna_rx; - pHalData->AntennaTxPath = pmppriv->antenna_tx; + pHalData->antenna_tx_path = pmppriv->antenna_tx; return _SUCCESS; } @@ -399,30 +393,30 @@ void mpt_InitHWConfig(PADAPTER Adapter) /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */ /* TODO: A better solution is configure it according EFUSE during the run-time. */ - PHY_SetMacReg(Adapter, 0x64, BIT20, 0x0); /* 0x66[4]=0 */ - PHY_SetMacReg(Adapter, 0x64, BIT24, 0x0); /* 0x66[8]=0 */ - PHY_SetMacReg(Adapter, 0x40, BIT4, 0x0); /* 0x40[4]=0 */ - PHY_SetMacReg(Adapter, 0x40, BIT3, 0x1); /* 0x40[3]=1 */ - PHY_SetMacReg(Adapter, 0x4C, BIT24, 0x1); /* 0x4C[24:23]=10 */ - PHY_SetMacReg(Adapter, 0x4C, BIT23, 0x0); /* 0x4C[24:23]=10 */ - PHY_SetBBReg(Adapter, 0x944, BIT1 | BIT0, 0x3); /* 0x944[1:0]=11 */ - PHY_SetBBReg(Adapter, 0x930, bMaskByte0, 0x77); /* 0x930[7:0]=77 */ - PHY_SetMacReg(Adapter, 0x38, BIT11, 0x1); /* 0x38[11]=1 */ + phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0); /* 0x66[4]=0 */ + phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0); /* 0x66[8]=0 */ + phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0); /* 0x40[4]=0 */ + phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1); /* 0x40[3]=1 */ + phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1); /* 0x4C[24:23]=10 */ + phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /* 0x4C[24:23]=10 */ + phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3); /* 0x944[1:0]=11 */ + phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77 */ + phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */ /* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */ - PHY_SetMacReg(Adapter, 0x778, 0x3, 0x3); /* Turn off hardware PTA control (Asked by Scott) */ - PHY_SetMacReg(Adapter, 0x64, bMaskDWord, 0x36000000); /* Fix BT S0/S1 */ - PHY_SetMacReg(Adapter, 0x948, bMaskDWord, 0x0); /* Fix BT can't Tx */ + phy_set_mac_reg(Adapter, 0x778, 0x3, 0x3); /* Turn off hardware PTA control (Asked by Scott) */ + phy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */ + phy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0); /* Fix BT can't Tx */ /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */ - PHY_SetBBReg(Adapter, 0xA00, BIT8, 0x0); /*0xA01[0] = 0*/ + phy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0); /*0xA01[0] = 0*/ } else if (IS_HARDWARE_TYPE_8821(Adapter)) { /* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock) <20131122, VincentL> Enable for all 8821A/8811AU (Asked by Alex)*/ - PHY_SetMacReg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[23:22]=01*/ - PHY_SetMacReg(Adapter, 0x4C, BIT22, 0x1); /*0x4C[23:22]=01*/ + phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[23:22]=01*/ + phy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1); /*0x4C[23:22]=01*/ } else if (IS_HARDWARE_TYPE_8188ES(Adapter)) - PHY_SetMacReg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/ + phy_set_mac_reg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/ #ifdef CONFIG_RTL8814A else if (IS_HARDWARE_TYPE_8814A(Adapter)) PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000); @@ -433,12 +427,12 @@ void mpt_InitHWConfig(PADAPTER Adapter) PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000); /* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */ - PHY_SetBBReg(Adapter, 0x70, bMaskByte3, 0x0e); - RTW_INFO(" 0x73 = 0x%x\n",PHY_QueryBBReg(Adapter, 0x70, bMaskByte3)); - PHY_SetBBReg(Adapter, 0x1704, bMaskDWord, 0x0000ff00); - RTW_INFO(" 0x1704 = 0x%x\n",PHY_QueryBBReg(Adapter, 0x1704, bMaskDWord)); - PHY_SetBBReg(Adapter, 0x1700, bMaskDWord, 0xc00f0038); - RTW_INFO(" 0x1700 = 0x%x\n",PHY_QueryBBReg(Adapter, 0x1700, bMaskDWord)); + phy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e); + RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(Adapter, 0x70, bMaskByte3)); + phy_set_bb_reg(Adapter, 0x1704, bMaskDWord, 0x0000ff00); + RTW_INFO(" 0x1704 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1704, bMaskDWord)); + phy_set_bb_reg(Adapter, 0x1700, bMaskDWord, 0xc00f0038); + RTW_INFO(" 0x1700 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1700, bMaskDWord)); } #endif /* CONFIG_RTL8822B */ #ifdef CONFIG_RTL8821C @@ -457,47 +451,47 @@ static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery) #ifdef CONFIG_RTL8723B pHalData = GET_HAL_DATA(padapter); b2ant = pHalData->EEPROMBluetoothAntNum == Ant_x2 ? _TRUE : _FALSE; - PHY_IQCalibrate_8723B(padapter, bReCovery, _FALSE, b2ant, pHalData->ant_path); + phy_iq_calibrate_8723b(padapter, bReCovery, _FALSE, b2ant, pHalData->ant_path); #endif } else if (IS_HARDWARE_TYPE_8188E(padapter)) { #ifdef CONFIG_RTL8188E - PHY_IQCalibrate_8188E(padapter, bReCovery); + phy_iq_calibrate_8188e(padapter, bReCovery); #endif } else if (IS_HARDWARE_TYPE_8814A(padapter)) { #ifdef CONFIG_RTL8814A - PHY_IQCalibrate_8814A(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); + phy_iq_calibrate_8814a(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); #endif } else if (IS_HARDWARE_TYPE_8812(padapter)) { #ifdef CONFIG_RTL8812A - PHY_IQCalibrate_8812A(padapter, bReCovery); + phy_iq_calibrate_8812a(padapter, bReCovery); #endif } else if (IS_HARDWARE_TYPE_8821(padapter)) { #ifdef CONFIG_RTL8821A - PHY_IQCalibrate_8821A(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); + phy_iq_calibrate_8821a(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); #endif } else if (IS_HARDWARE_TYPE_8192E(padapter)) { #ifdef CONFIG_RTL8192E - PHY_IQCalibrate_8192E(padapter, bReCovery); + phy_iq_calibrate_8192e(padapter, bReCovery); #endif } else if (IS_HARDWARE_TYPE_8703B(padapter)) { #ifdef CONFIG_RTL8703B - PHY_IQCalibrate_8703B(padapter, bReCovery); + phy_iq_calibrate_8703b(padapter, bReCovery); #endif } else if (IS_HARDWARE_TYPE_8188F(padapter)) { #ifdef CONFIG_RTL8188F - PHY_IQCalibrate_8188F(padapter, bReCovery, _FALSE); + phy_iq_calibrate_8188f(padapter, bReCovery, _FALSE); #endif } else if (IS_HARDWARE_TYPE_8822B(padapter)) { #ifdef CONFIG_RTL8822B - PHY_IQCalibrate_8822B(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); + phy_iq_calibrate_8822b(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); #endif } else if (IS_HARDWARE_TYPE_8723D(padapter)) { #ifdef CONFIG_RTL8723D - PHY_IQCalibrate_8723D(padapter, bReCovery); + phy_iq_calibrate_8723d(padapter, bReCovery); #endif } else if (IS_HARDWARE_TYPE_8821C(padapter)) { #ifdef CONFIG_RTL8821C - /*PHY_IQCalibrate_8821C(padapter, bReCovery);*/ + phy_iq_calibrate_8821c(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); #endif } @@ -507,93 +501,145 @@ static void PHY_LCCalibrate(PADAPTER padapter) { if (IS_HARDWARE_TYPE_8723B(padapter)) { #ifdef CONFIG_RTL8723B - PHY_LCCalibrate_8723B(&(GET_HAL_DATA(padapter)->odmpriv)); + phy_lc_calibrate_8723b(&(GET_HAL_DATA(padapter)->odmpriv)); #endif } else if (IS_HARDWARE_TYPE_8188E(padapter)) { #ifdef CONFIG_RTL8188E - PHY_LCCalibrate_8188E(&(GET_HAL_DATA(padapter)->odmpriv)); + phy_lc_calibrate_8188e(&(GET_HAL_DATA(padapter)->odmpriv)); #endif } else if (IS_HARDWARE_TYPE_8814A(padapter)) { #ifdef CONFIG_RTL8814A - PHY_LCCalibrate_8814A(&(GET_HAL_DATA(padapter)->odmpriv)); + phy_lc_calibrate_8814a(&(GET_HAL_DATA(padapter)->odmpriv)); #endif } else if (IS_HARDWARE_TYPE_8812(padapter)) { #ifdef CONFIG_RTL8812A - PHY_LCCalibrate_8812A(&(GET_HAL_DATA(padapter)->odmpriv)); + phy_lc_calibrate_8812a(&(GET_HAL_DATA(padapter)->odmpriv)); #endif } else if (IS_HARDWARE_TYPE_8821(padapter)) { #ifdef CONFIG_RTL8821A - PHY_LCCalibrate_8821A(&(GET_HAL_DATA(padapter)->odmpriv)); + phy_lc_calibrate_8821a(&(GET_HAL_DATA(padapter)->odmpriv)); #endif } else if (IS_HARDWARE_TYPE_8192E(padapter)) { #ifdef CONFIG_RTL8192E - PHY_LCCalibrate_8192E(&(GET_HAL_DATA(padapter)->odmpriv)); + phy_lc_calibrate_8192e(&(GET_HAL_DATA(padapter)->odmpriv)); #endif } else if (IS_HARDWARE_TYPE_8703B(padapter)) { #ifdef CONFIG_RTL8703B - PHY_LCCalibrate_8703B(&(GET_HAL_DATA(padapter)->odmpriv)); + phy_lc_calibrate_8703b(&(GET_HAL_DATA(padapter)->odmpriv)); #endif } else if (IS_HARDWARE_TYPE_8188F(padapter)) { #ifdef CONFIG_RTL8188F - PHY_LCCalibrate_8188F(&(GET_HAL_DATA(padapter)->odmpriv)); + phy_lc_calibrate_8188f(&(GET_HAL_DATA(padapter)->odmpriv)); #endif } else if (IS_HARDWARE_TYPE_8822B(padapter)) { #ifdef CONFIG_RTL8822B - PHY_LCCalibrate_8822B(&(GET_HAL_DATA(padapter)->odmpriv)); + phy_lc_calibrate_8822b(&(GET_HAL_DATA(padapter)->odmpriv)); #endif } else if (IS_HARDWARE_TYPE_8723D(padapter)) { #ifdef CONFIG_RTL8723D - PHY_LCCalibrate_8723D(&(GET_HAL_DATA(padapter)->odmpriv)); + phy_lc_calibrate_8723d(&(GET_HAL_DATA(padapter)->odmpriv)); #endif } else if (IS_HARDWARE_TYPE_8821C(padapter)) { #ifdef CONFIG_RTL8821C - /*PHY_IQCalibrate_8821C(&(GET_HAL_DATA(padapter)->odmpriv));*/ + /*phy_iq_calibrate_8821c(&(GET_HAL_DATA(padapter)->odmpriv));*/ #endif } } +static u8 PHY_QueryRFPathSwitch(PADAPTER padapter) +{ + u8 bmain = 0; +/* + if (IS_HARDWARE_TYPE_8723B(padapter)) { +#ifdef CONFIG_RTL8723B + bmain = PHY_QueryRFPathSwitch_8723B(padapter); +#endif + } else if (IS_HARDWARE_TYPE_8188E(padapter)) { +#ifdef CONFIG_RTL8188E + bmain = PHY_QueryRFPathSwitch_8188E(padapter); +#endif + } else if (IS_HARDWARE_TYPE_8814A(padapter)) { +#ifdef CONFIG_RTL8814A + bmain = PHY_QueryRFPathSwitch_8814A(padapter); +#endif + } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) { +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) + bmain = PHY_QueryRFPathSwitch_8812A(padapter); +#endif + } else if (IS_HARDWARE_TYPE_8192E(padapter)) { +#ifdef CONFIG_RTL8192E + bmain = PHY_QueryRFPathSwitch_8192E(padapter); +#endif + } else if (IS_HARDWARE_TYPE_8703B(padapter)) { +#ifdef CONFIG_RTL8703B + bmain = PHY_QueryRFPathSwitch_8703B(padapter); +#endif + } else if (IS_HARDWARE_TYPE_8188F(padapter)) { +#ifdef CONFIG_RTL8188F + bmain = PHY_QueryRFPathSwitch_8188F(padapter); +#endif + } else if (IS_HARDWARE_TYPE_8822B(padapter)) { +#ifdef CONFIG_RTL8822B + bmain = PHY_QueryRFPathSwitch_8822B(padapter); +#endif + } else if (IS_HARDWARE_TYPE_8723D(padapter)) { +#ifdef CONFIG_RTL8723D + bmain = PHY_QueryRFPathSwitch_8723D(padapter); +#endif + } else +*/ + + if (IS_HARDWARE_TYPE_8821C(padapter)) { +#ifdef CONFIG_RTL8821C + bmain = phy_query_rf_path_switch_8821c(padapter); +#endif + } + + return bmain; +} + static void PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) { if (IS_HARDWARE_TYPE_8723B(padapter)) { #ifdef CONFIG_RTL8723B - PHY_SetRFPathSwitch_8723B(padapter, bMain); + phy_set_rf_path_switch_8723b(padapter, bMain); #endif } else if (IS_HARDWARE_TYPE_8188E(padapter)) { #ifdef CONFIG_RTL8188E - PHY_SetRFPathSwitch_8188E(padapter, bMain); + phy_set_rf_path_switch_8188e(padapter, bMain); #endif } else if (IS_HARDWARE_TYPE_8814A(padapter)) { #ifdef CONFIG_RTL8814A - PHY_SetRFPathSwitch_8814A(padapter, bMain); + phy_set_rf_path_switch_8814a(padapter, bMain); #endif } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) { #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - PHY_SetRFPathSwitch_8812A(padapter, bMain); + phy_set_rf_path_switch_8812a(padapter, bMain); #endif } else if (IS_HARDWARE_TYPE_8192E(padapter)) { #ifdef CONFIG_RTL8192E - PHY_SetRFPathSwitch_8192E(padapter, bMain); + phy_set_rf_path_switch_8192e(padapter, bMain); #endif } else if (IS_HARDWARE_TYPE_8703B(padapter)) { #ifdef CONFIG_RTL8703B - PHY_SetRFPathSwitch_8703B(padapter, bMain); + phy_set_rf_path_switch_8703b(padapter, bMain); #endif } else if (IS_HARDWARE_TYPE_8188F(padapter)) { #ifdef CONFIG_RTL8188F - PHY_SetRFPathSwitch_8188F(padapter, bMain); + phy_set_rf_path_switch_8188f(padapter, bMain); #endif } else if (IS_HARDWARE_TYPE_8822B(padapter)) { #ifdef CONFIG_RTL8822B - PHY_SetRFPathSwitch_8822B(padapter, bMain); + phy_set_rf_path_switch_8822b(padapter, bMain); #endif } else if (IS_HARDWARE_TYPE_8723D(padapter)) { #ifdef CONFIG_RTL8723D - PHY_SetRFPathSwitch_8723D(padapter, bMain); + phy_set_rf_path_switch_8723d(padapter, bMain); #endif } else if (IS_HARDWARE_TYPE_8821C(padapter)) { #ifdef CONFIG_RTL8821C - /*PHY_SetRFPathSwitch_8821C(&(GET_HAL_DATA(padapter)->odmpriv));*/ + phy_set_rf_path_switch_8821c(padapter, bMain); #endif } } @@ -606,7 +652,7 @@ MPT_InitializeAdapter( { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); s32 rtStatus = _SUCCESS; - PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; + PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx; u32 ledsetting; struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; @@ -620,7 +666,7 @@ MPT_InitializeAdapter( pMptCtx->MptH2cRspEvent = _FALSE; pMptCtx->MptBtC2hEvent = _FALSE; _rtw_init_sema(&pMptCtx->MPh2c_Sema, 0); - _init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter->pnetdev, MPh2c_timeout_handle, pAdapter); + rtw_init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter, MPh2c_timeout_handle, pAdapter); #endif mpt_InitHWConfig(pAdapter); @@ -630,13 +676,13 @@ MPT_InitializeAdapter( if (IS_HARDWARE_TYPE_8723B(pAdapter)) { /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/ - PHY_SetBBReg(pAdapter, 0xA00, BIT8, 0x0); + phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0); PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/ /*<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten. */ if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)) - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); else - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); } /*set ant to wifi side in mp mode*/ rtw_write16(pAdapter, 0x870, 0x300); @@ -645,7 +691,7 @@ MPT_InitializeAdapter( pMptCtx->bMptWorkItemInProgress = _FALSE; pMptCtx->CurrMptAct = NULL; - pMptCtx->MptRfPath = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = ODM_RF_PATH_A; /* ------------------------------------------------------------------------- */ /* Don't accept any packets */ rtw_write32(pAdapter, REG_RCR, 0); @@ -659,25 +705,25 @@ MPT_InitializeAdapter( PHY_LCCalibrate(pAdapter); PHY_IQCalibrate(pAdapter, _FALSE); - /* dm_CheckTXPowerTracking(&pHalData->odmpriv); */ /* trigger thermal meter */ + /* dm_check_txpowertracking(&pHalData->odmpriv); */ /* trigger thermal meter */ PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */ - pMptCtx->backup0xc50 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0); - pMptCtx->backup0xc58 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0); - pMptCtx->backup0xc30 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0); - pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0); - pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0); + pMptCtx->backup0xc50 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0); + pMptCtx->backup0xc58 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0); + pMptCtx->backup0xc30 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0); + pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0); + pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0); #ifdef CONFIG_RTL8188E rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0); rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0); #endif #ifdef CONFIG_RTL8814A if (IS_HARDWARE_TYPE_8814A(pAdapter)) { - pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u1Byte)PHY_QueryBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0); - pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u1Byte)PHY_QueryBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0); - pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u1Byte)PHY_QueryBBReg(pAdapter, rC_IGI_Jaguar2, bMaskByte0); - pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u1Byte)PHY_QueryBBReg(pAdapter, rD_IGI_Jaguar2, bMaskByte0); + pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u1Byte)phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0); + pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u1Byte)phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0); + pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u1Byte)phy_query_bb_reg(pAdapter, rC_IGI_Jaguar2, bMaskByte0); + pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u1Byte)phy_query_bb_reg(pAdapter, rD_IGI_Jaguar2, bMaskByte0); } #endif return rtStatus; @@ -705,7 +751,7 @@ MPT_DeInitAdapter( IN PADAPTER pAdapter ) { - PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; + PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx; pMptCtx->bMptDrvUnload = _TRUE; #if defined(CONFIG_RTL8723B) @@ -713,7 +759,7 @@ MPT_DeInitAdapter( _cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer); #endif #if defined(CONFIG_RTL8723B) - PHY_SetBBReg(pAdapter, 0xA01, BIT0, 1); /* /suggestion by jerry for MP Rx. */ + phy_set_bb_reg(pAdapter, 0xA01, BIT0, 1); /* /suggestion by jerry for MP Rx. */ #endif #if 0 /* for Windows */ PlatformFreeWorkItem(&(pMptCtx->MptWorkItem)); @@ -728,15 +774,15 @@ MPT_DeInitAdapter( static u8 mpt_ProStartTest(PADAPTER padapter) { - PMPT_CONTEXT pMptCtx = &padapter->mppriv.MptCtx; + PMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx; pMptCtx->bMassProdTest = _TRUE; - pMptCtx->bStartContTx = _FALSE; + pMptCtx->is_start_cont_tx = _FALSE; pMptCtx->bCckContTx = _FALSE; pMptCtx->bOfdmContTx = _FALSE; pMptCtx->bSingleCarrier = _FALSE; - pMptCtx->bCarrierSuppression = _FALSE; - pMptCtx->bSingleTone = _FALSE; + pMptCtx->is_carrier_suppression = _FALSE; + pMptCtx->is_single_tone = _FALSE; pMptCtx->HWTxmode = PACKETS_TX; return _SUCCESS; @@ -757,63 +803,66 @@ void GetPowerTracking(PADAPTER padapter, u8 *enable) hal_mpt_GetPowerTracking(padapter, enable); } -static void disable_dm(PADAPTER padapter) +void rtw_mp_trigger_iqk(PADAPTER padapter) +{ + PHY_IQCalibrate(padapter, _FALSE); +} + +void rtw_mp_trigger_lck(PADAPTER padapter) +{ + PHY_LCCalibrate(padapter); +} + +static void init_mp_data(PADAPTER padapter) { u8 v8; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - /* 3 1. disable firmware dynamic mechanism */ - /* disable Power Training, Rate Adaptive */ + /*disable BCN*/ v8 = rtw_read8(padapter, REG_BCN_CTRL); v8 &= ~EN_BCN_FUNCTION; rtw_write8(padapter, REG_BCN_CTRL, v8); - /* 3 2. disable driver dynamic mechanism */ - rtw_phydm_func_disable_all(padapter); - - /* enable APK, LCK and IQK but disable power tracking */ - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE; - rtw_phydm_func_set(padapter, ODM_RF_CALIBRATION); - - /* #ifdef CONFIG_BT_COEXIST */ - /* rtw_btcoex_Switch(padapter, 0); */ /* remove for BT MP Down. */ - /* #endif */ + pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE; } - void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + u32 rf_ability; if (bstart == 1) { RTW_INFO("in MPT_PwrCtlDM start\n"); - rtw_phydm_func_set(padapter, ODM_RF_TX_PWR_TRACK | ODM_RF_CALIBRATION); - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; + rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) | HAL_RF_TX_PWR_TRACK; + halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability); + + pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE; padapter->mppriv.mp_dm = 1; } else { RTW_INFO("in MPT_PwrCtlDM stop\n"); - disable_dm(padapter); - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE; + rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) & ~HAL_RF_TX_PWR_TRACK; + halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability); + pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE; padapter->mppriv.mp_dm = 0; { - TXPWRTRACK_CFG c; + struct _TXPWRTRACK_CFG c; u1Byte chnl = 0 ; - _rtw_memset(&c, 0, sizeof(TXPWRTRACK_CFG)); - ConfigureTxpowerTrack(pDM_Odm, &c); - ODM_ClearTxPowerTrackingState(pDM_Odm); - if (*c.ODM_TxPwrTrackSetPwr) { - if (pDM_Odm->SupportICType == ODM_RTL8188F) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, chnl); - else if (pDM_Odm->SupportICType == ODM_RTL8723D) { - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl); + _rtw_memset(&c, 0, sizeof(struct _TXPWRTRACK_CFG)); + configure_txpower_track(pDM_Odm, &c); + odm_clear_txpowertracking_state(pDM_Odm); + if (*c.odm_tx_pwr_track_set_pwr) { + if (pDM_Odm->support_ic_type == ODM_RTL8188F) + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, chnl); + else if (pDM_Odm->support_ic_type == ODM_RTL8723D) { + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl); SetTxPower(padapter); } else { - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl); - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, ODM_RF_PATH_B, chnl); + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl); + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_B, chnl); } } } @@ -827,7 +876,7 @@ u32 mp_join(PADAPTER padapter, u8 mode) WLAN_BSSID_EX bssid; struct sta_info *psta; u32 length; - u8 val8; + u8 val8, join_type; _irqL irqL; s32 res = _SUCCESS; @@ -877,7 +926,7 @@ u32 mp_join(PADAPTER padapter, u8 mode) /* init mp_start_test status */ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { - rtw_disassoc_cmd(padapter, 500, _TRUE); + rtw_disassoc_cmd(padapter, 500, 0); rtw_indicate_disconnect(padapter, 0, _FALSE); rtw_free_assoc_resources(padapter, 1); } @@ -895,13 +944,15 @@ u32 mp_join(PADAPTER padapter, u8 mode) psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress); if (psta == NULL) { - RT_TRACE(_module_mp_, _drv_err_, ("mp_start_test: Can't alloc sta_info!\n")); /*pmlmepriv->fw_state = pmppriv->prev_fw_state;*/ init_fwstate(pmlmepriv, pmppriv->prev_fw_state); res = _FAIL; goto end_of_mp_start_test; } + if (mode == WIFI_FW_ADHOC_STATE) set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + else + set_fwstate(pmlmepriv, WIFI_STATION_STATE); /* 3 3. join psudo AdHoc */ tgt_network->join_res = 1; tgt_network->aid = psta->aid = 1; @@ -922,10 +973,16 @@ u32 mp_join(PADAPTER padapter, u8 mode) if (1) { /* (res == _SUCCESS) */ /* set MSR to WIFI_FW_ADHOC_STATE */ if (mode == WIFI_FW_ADHOC_STATE) { + /* set msr to WIFI_FW_ADHOC_STATE */ + pmlmeinfo->state = WIFI_FW_ADHOC_STATE; + Set_MSR(padapter, (pmlmeinfo->state & 0x3)); + + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); + join_type = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); - val8 = rtw_read8(padapter, MSR) & 0xFC; /* 0x0102 */ - val8 |= WIFI_FW_ADHOC_STATE; - rtw_write8(padapter, MSR, val8); /* Link in ad hoc network */ + report_join_res(padapter, 1); + pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; } else { Set_MSR(padapter, WIFI_FW_STATION_STATE); @@ -947,17 +1004,10 @@ s32 mp_start_test(PADAPTER padapter) padapter->registrypriv.mp_mode = 1; - /* 3 disable dynamic mechanism */ - disable_dm(padapter); + init_mp_data(padapter); #ifdef CONFIG_RTL8814A rtl8814_InitHalDm(padapter); #endif /* CONFIG_RTL8814A */ -#ifdef CONFIG_RTL8822B - rtl8822b_phy_init_haldm(padapter); -#endif /* CONFIG_RTL8822B */ -#ifdef CONFIG_RTL8821C - rtl8821c_phy_init_haldm(padapter); -#endif /* CONFIG_RTL8821C */ #ifdef CONFIG_RTL8812A rtl8812_InitHalDm(padapter); #endif /* CONFIG_RTL8812A */ @@ -973,13 +1023,16 @@ s32 mp_start_test(PADAPTER padapter) #ifdef CONFIG_RTL8188F rtl8188f_InitHalDm(padapter); #endif +#ifdef CONFIG_RTL8188E + rtl8188e_InitHalDm(padapter); +#endif #ifdef CONFIG_RTL8723D rtl8723d_InitHalDm(padapter); #endif /* CONFIG_RTL8723D */ /* 3 0. update mp_priv */ - if (padapter->registrypriv.rf_config == RF_MAX_TYPE) { + if (!RF_TYPE_VALID(padapter->registrypriv.rf_config)) { /* switch (phal->rf_type) { */ switch (GET_RF_TYPE(padapter)) { case RF_1T1R: @@ -1107,7 +1160,6 @@ static VOID mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Ch } } - /* RT_TRACE(COMP_CMD, DBG_LOUD, ("\n mpt_AdjustRFRegByRateByChan92CU():Chan:%d Rate=%d rfReg0x26:0x%08x\n",Channel, RateIdx,rfReg0x26)); */ for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26); } @@ -1141,11 +1193,6 @@ static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14); } -static void MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven) -{ - hal_mpt_CCKTxPowerAdjustbyIndex(pAdapter, beven); -} - /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ /* @@ -1206,6 +1253,10 @@ void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain) } +u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter) +{ + return PHY_QueryRFPathSwitch(pAdapter); +} s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther) { @@ -1245,18 +1296,6 @@ void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart); } -void SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart) -{ - PhySetTxPowerLevel(pAdapter); - hal_mpt_SetCCKContinuousTx(pAdapter, bStart); -} - -void SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart) -{ - PhySetTxPowerLevel(pAdapter); - hal_mpt_SetOFDMContinuousTx(pAdapter, bStart); -} /* mpt_StartOfdmContTx */ - void SetContinuousTx(PADAPTER pAdapter, u8 bStart) { PhySetTxPowerLevel(pAdapter); @@ -1268,25 +1307,9 @@ void PhySetTxPowerLevel(PADAPTER pAdapter) { struct mp_priv *pmp_priv = &pAdapter->mppriv; - if (pmp_priv->bSetTxPower == 0) { /* for NO manually set power index */ -#ifdef CONFIG_RTL8188E - PHY_SetTxPowerLevel8188E(pAdapter, pmp_priv->channel); -#endif -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - PHY_SetTxPowerLevel8812(pAdapter, pmp_priv->channel); -#endif -#if defined(CONFIG_RTL8192E) - PHY_SetTxPowerLevel8192E(pAdapter, pmp_priv->channel); -#endif -#if defined(CONFIG_RTL8723B) - PHY_SetTxPowerLevel8723B(pAdapter, pmp_priv->channel); -#endif -#if defined(CONFIG_RTL8188F) - PHY_SetTxPowerLevel8188F(pAdapter, pmp_priv->channel); -#endif - mpt_ProQueryCalTxPower(pAdapter, pmp_priv->antenna_tx); - } + if (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */ + rtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel); } /* ------------------------------------------------------------------------------ */ @@ -1375,7 +1398,8 @@ static thread_return mp_xmit_packet_thread(thread_context context) pmptx->pallocated_buf = NULL; pmptx->stop = 1; - thread_exit(); + thread_exit(NULL); + return 0; } void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc) @@ -1738,13 +1762,13 @@ static void Rtw_MPSetMacTxEDCA(PADAPTER padapter) rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */ /* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */ - PHY_SetMacReg(padapter, 0x458 , bMaskDWord , 0x0); - /* RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__,PHY_QueryBBReg(padapter, 0x460, bMaskDWord)); */ - PHY_SetMacReg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out vaule */ - /* PHY_SetMacReg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C); */ - /* PHY_SetMacReg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C); */ - /* PHY_SetMacReg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C); */ - RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, PHY_QueryBBReg(padapter, 0x460, bMaskDWord)); + phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0); + /*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/ + phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/ + /*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/ + /*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/ + /*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/ + RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord)); } @@ -1853,9 +1877,8 @@ void SetPacketTx(PADAPTER padapter) /* 3 4. make wlan header, make_wlanhdr() */ hdr = (struct rtw_ieee80211_hdr *)pkt_start; - SetFrameSubType(&hdr->frame_ctl, pattrib->subtype); - /* */ - SetFrDs(&hdr->frame_ctl); + set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype); + _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */ _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */ _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */ @@ -1898,8 +1921,10 @@ void SetPacketTx(PADAPTER padapter) /* 3 6. start thread */ #ifdef PLATFORM_LINUX pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD"); - if (IS_ERR(pmp_priv->tx.PktTxThread)) - RTW_INFO("Create PktTx Thread Fail !!!!!\n"); + if (IS_ERR(pmp_priv->tx.PktTxThread)) { + RTW_ERR("Create PktTx Thread Fail !!!!!\n"); + pmp_priv->tx.PktTxThread = NULL; + } #endif #ifdef PLATFORM_FREEBSD { @@ -1926,7 +1951,7 @@ void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB) if (bStartRx) { #ifdef CONFIG_RTL8723B - PHY_SetMacReg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc (in RX_WAIT_CCA state) */ + phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc (in RX_WAIT_CCA state) */ write_bbreg(pAdapter, 0xa01, BIT0, bDisable);/* improve Rx performance by jerry */ #endif pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL; @@ -1936,13 +1961,16 @@ void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB) if (pmppriv->bSetRxBssid == _TRUE) { RTW_INFO("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__, MAC_ARG(pmppriv->network_macaddr)); + pHalData->ReceiveConfig = 0; + pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF; + +#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) + write_bbreg(pAdapter, 0x550, BIT3, bEnable); +#endif + rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */ - /* Set_MSR(pAdapter, WIFI_FW_AP_STATE); */ - /* rtw_hal_set_hwreg(pAdapter, HW_VAR_BSSID, pmppriv->network_macaddr); */ - /* rtw_hal_set_hwreg(pAdapter, HW_VAR_SET_OPMODE, (u8 *)(&type)); */ } else { pHalData->ReceiveConfig |= RCR_ADF; - /* Accept all data frames */ rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF); } @@ -1951,10 +1979,11 @@ void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB) pHalData->ReceiveConfig |= RCR_AB; } else { #ifdef CONFIG_RTL8723B - PHY_SetMacReg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc (in RX_WAIT_CCA state) */ + phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc (in RX_WAIT_CCA state)*/ write_bbreg(pAdapter, 0xa01, BIT0, bEnable);/* improve Rx performance by jerry */ #endif pHalData->ReceiveConfig = 0; + rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */ } rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig); @@ -2057,13 +2086,11 @@ u32 mp_query_psd(PADAPTER pAdapter, u8 *data) #ifdef PLATFORM_LINUX if (!netif_running(pAdapter->pnetdev)) { - RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! interface not opened!\n")); return 0; } #endif if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { - RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! not in MP mode!\n")); return 0; } @@ -2138,7 +2165,6 @@ void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv) pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4); if (pxmitpriv->pallocated_xmit_extbuf == NULL) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("alloc xmit_extbuf fail!\n")); res = _FAIL; goto exit; } @@ -2182,284 +2208,8 @@ void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv) } #endif - -ULONG getPowerDiffByRate8188E( - IN PADAPTER pAdapter, - IN u1Byte CurrChannel, - IN ULONG RfPath -) -{ - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - ULONG PwrGroup = 0; - ULONG TxPower = 0, Limit = 0; - ULONG Pathmapping = (RfPath == ODM_RF_PATH_A ? 0 : 8); - - switch (pHalData->EEPROMRegulatory) { - case 0: /* driver-defined maximum power offset for longer communication range */ - /* refer to power by rate table */ - PwrGroup = 0; - Limit = 0xff; - break; - case 1: /* Power-limit table-defined maximum power offset range */ - /* choosed by min(power by rate, power limit). */ - { - if (pHalData->pwrGroupCnt == 1) - PwrGroup = 0; - if (pHalData->pwrGroupCnt >= 3) { - if (CurrChannel <= 3) - PwrGroup = 0; - else if (CurrChannel >= 4 && CurrChannel <= 9) - PwrGroup = 1; - else if (CurrChannel > 9) - PwrGroup = 2; - - if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_20) - PwrGroup++; - else - PwrGroup += 4; - } - Limit = 0xff; - } - break; - case 2: /* not support power offset by rate. */ - /* don't increase any power diff */ - PwrGroup = 0; - Limit = 0; - break; - default: - PwrGroup = 0; - Limit = 0xff; - break; - } - - - { - switch (pMptCtx->MptRateIndex) { - case MPT_RATE_1M: - case MPT_RATE_2M: - case MPT_RATE_55M: - case MPT_RATE_11M: - /* CCK rates, don't add any tx power index. */ - /* RT_DISP(FPHY, PHY_TXPWR,("CCK rates!\n")); */ - break; - case MPT_RATE_6M: /* 0xe00 [31:0] = 18M,12M,09M,06M */ - TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0 + Pathmapping]) & 0xff); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 6M, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower)); */ - break; - case MPT_RATE_9M: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0 + Pathmapping]) & 0xff00) >> 8); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 9M, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower)); */ - break; - case MPT_RATE_12M: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0 + Pathmapping]) & 0xff0000) >> 16); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 12M, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower)); */ - break; - case MPT_RATE_18M: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0 + Pathmapping]) & 0xff000000) >> 24); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 24M, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower)); */ - break; - case MPT_RATE_24M: /* 0xe04[31:0] = 54M,48M,36M,24M */ - TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1 + Pathmapping]) & 0xff); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 24M, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower)); */ - break; - case MPT_RATE_36M: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1 + Pathmapping]) & 0xff00) >> 8); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 36M, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower)); */ - break; - case MPT_RATE_48M: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1 + Pathmapping]) & 0xff0000) >> 16); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 48M, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower)); */ - break; - case MPT_RATE_54M: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1 + Pathmapping]) & 0xff000000) >> 24); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 54M, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower)); */ - break; - case MPT_RATE_MCS0: /* 0xe10[31:0]= MCS=03,02,01,00 */ - TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2 + Pathmapping]) & 0xff); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS0, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower)); */ - break; - case MPT_RATE_MCS1: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2 + Pathmapping]) & 0xff00) >> 8); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS1, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower)); */ - break; - case MPT_RATE_MCS2: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2 + Pathmapping]) & 0xff0000) >> 16); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS2, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower)); */ - break; - case MPT_RATE_MCS3: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2 + Pathmapping]) & 0xff000000) >> 24); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS3, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower)); */ - break; - case MPT_RATE_MCS4: /* 0xe14[31:0]= MCS=07,06,05,04 */ - TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3 + Pathmapping]) & 0xff); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS4, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower)); */ - break; - case MPT_RATE_MCS5: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3 + Pathmapping]) & 0xff00) >> 8); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS5, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower)); */ - break; - case MPT_RATE_MCS6: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3 + Pathmapping]) & 0xff0000) >> 16); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS6, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower)); */ - break; - case MPT_RATE_MCS7: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3 + Pathmapping]) & 0xff000000) >> 24); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS7, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower)); */ - break; - - case MPT_RATE_MCS8: /* 0xe18[31:0]= MCS=11,10,09,08 */ - TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4 + Pathmapping]) & 0xff); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS8, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower)); */ - break; - case MPT_RATE_MCS9: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4 + Pathmapping]) & 0xff00) >> 8); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS9, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower)); */ - break; - case MPT_RATE_MCS10: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4 + Pathmapping]) & 0xff0000) >> 16); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS10, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower)); */ - break; - case MPT_RATE_MCS11: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4 + Pathmapping]) & 0xff000000) >> 24); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS11, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower)); */ - break; - case MPT_RATE_MCS12: /* 0xe1c[31:0]= MCS=15,14,13,12 */ - TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5 + Pathmapping]) & 0xff); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS12, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower)); */ - break; - case MPT_RATE_MCS13: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5 + Pathmapping]) & 0xff00) >> 8); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS13, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower)); */ - break; - case MPT_RATE_MCS14: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5 + Pathmapping]) & 0xff0000) >> 16); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS14, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower)); */ - break; - case MPT_RATE_MCS15: - TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5 + Pathmapping]) & 0xff000000) >> 24); - /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS15, TxPower = %d\n", */ - /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower)); */ - break; - default: - break; - } - } - - if (TxPower > Limit) - TxPower = Limit; - - return TxPower; -} - - - -static ULONG -mpt_ProQueryCalTxPower_8188E( - IN PADAPTER pAdapter, - IN u1Byte RfPath -) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u1Byte TxCount = TX_1S, i = 0; /* default set to 1S */ - /* PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); */ - ULONG TxPower = 1, PwrGroup = 0, PowerDiffByRate = 0; - ULONG TxPowerCCK = 1, TxPowerOFDM = 1, TxPowerBW20 = 1, TxPowerBW40 = 1 ; - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - u1Byte CurrChannel = pHalData->CurrentChannel; - u1Byte index = (CurrChannel - 1); - u1Byte rf_path = (RfPath), rfPath; - u1Byte limit = 0, rate = 0; - - if (HAL_IsLegalChannel(pAdapter, CurrChannel) == FALSE) - CurrChannel = 1; - - if (pMptCtx->MptRateIndex <= MPT_RATE_11M) - TxPower = pHalData->Index24G_CCK_Base[rf_path][index]; - else if (pMptCtx->MptRateIndex >= MPT_RATE_6M && - pMptCtx->MptRateIndex <= MPT_RATE_54M) - TxPower = pHalData->Index24G_BW40_Base[rf_path][index]; - else if (pMptCtx->MptRateIndex >= MPT_RATE_MCS0 && - pMptCtx->MptRateIndex <= MPT_RATE_MCS7) - TxPower = pHalData->Index24G_BW40_Base[rf_path][index]; - - /* RT_DISP(FPHY, PHY_TXPWR, ("HT40 rate(%d) Tx power(RF-%c) = 0x%x\n", pMptCtx->MptRateIndex, ((rf_path==0)?'A':'B'), TxPower)); */ - - - if (pMptCtx->MptRateIndex >= MPT_RATE_6M && - pMptCtx->MptRateIndex <= MPT_RATE_54M) { - TxPower += pHalData->OFDM_24G_Diff[rf_path][TxCount]; - /* /RT_DISP(FPHY, PHY_TXPWR, ("+OFDM_PowerDiff(RF-%c) = 0x%x\n", ((rf_path==0)?'A':'B'), */ - /* pHalData->OFDM_24G_Diff[rf_path][TxCount])); */ - } - - if (pMptCtx->MptRateIndex >= MPT_RATE_MCS0) { - if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_20) { - TxPower += pHalData->BW20_24G_Diff[rf_path][TxCount]; - /* RT_DISP(FPHY, PHY_TXPWR, ("+HT20_PowerDiff(RF-%c) = 0x%x\n", ((rf_path==0)?'A':'B'), */ - /* pHalData->BW20_24G_Diff[rf_path][TxCount])); */ - } - } - - -#ifdef ENABLE_POWER_BY_RATE - PowerDiffByRate = getPowerDiffByRate8188E(pAdapter, CurrChannel, RfPath); -#else - PowerDiffByRate = 0; -#endif - - /* 2012/11/02 Awk: add power limit mechansim */ - if (pMptCtx->MptRateIndex <= MPT_RATE_11M) - rate = MGN_1M; - else if (pMptCtx->MptRateIndex >= MPT_RATE_6M && - pMptCtx->MptRateIndex <= MPT_RATE_54M) - rate = MGN_54M; - else if (pMptCtx->MptRateIndex >= MPT_RATE_MCS0 && - pMptCtx->MptRateIndex <= MPT_RATE_MCS7) - rate = MGN_MCS7; - - limit = (u8)PHY_GetTxPowerLimit(pAdapter, pMptCtx->RegTxPwrLimit, - pHalData->CurrentBandType, - pHalData->CurrentChannelBW, RfPath, - rate, CurrChannel); - - /* RT_DISP(FPHY, PHY_TXPWR, ("+PowerDiffByRate(RF-%c) = 0x%x\n", ((rf_path==0)?'A':'B'), */ - /* PowerDiffByRate)); */ - TxPower += PowerDiffByRate; - /* RT_DISP(FPHY, PHY_TXPWR, ("PowerDiffByRate limit value(RF-%c) = %d\n", ((rf_path==0)?'A':'B'), */ - /* limit)); */ - - TxPower += limit > (s8) PowerDiffByRate ? PowerDiffByRate : limit; - - return TxPower; -} - - u8 -MptToMgntRate( +mpt_to_mgnt_rate( IN ULONG MptRateIdx ) { @@ -2643,7 +2393,7 @@ MptToMgntRate( case MPT_RATE_LAST: /* fully automatiMGN_VHT2SS_MCS1; */ default: - RTW_INFO("<===MptToMgntRate(), Invalid Rate: %d!!\n", MptRateIdx); + RTW_INFO("<===mpt_to_mgnt_rate(), Invalid Rate: %d!!\n", MptRateIdx); return 0x0; } } @@ -2908,7 +2658,7 @@ u8 HwRateToMPTRate(u8 rate) break; default: - RTW_INFO("HwRateToMRate(): Non supported Rate [%x]!!!\n", rate); + RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate); break; } return ret_rate; @@ -2944,6 +2694,17 @@ u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr) return _FAIL; } +u8 rtw_mp_mode_check(PADAPTER pAdapter) +{ + PADAPTER primary_adapter = GET_PRIMARY_ADAPTER(pAdapter); + + if (primary_adapter->registrypriv.mp_mode == 1) + return _TRUE; + else + return _FALSE; +} + + ULONG mpt_ProQueryCalTxPower( PADAPTER pAdapter, u8 RfPath @@ -2951,59 +2712,18 @@ ULONG mpt_ProQueryCalTxPower( { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - - ULONG TxPower = 1, PwrGroup = 0, PowerDiffByRate = 0; - u1Byte limit = 0, rate = 0; - u8 mgn_rate = MptToMgntRate(pMptCtx->MptRateIndex); - -#if defined(CONFIG_RTL8188E) - if (IS_HARDWARE_TYPE_8188E(pAdapter)) - TxPower = PHY_GetTxPowerIndex_8188E(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); -#endif - -#if defined(CONFIG_RTL8723B) - if (IS_HARDWARE_TYPE_8723B(pAdapter)) - TxPower = PHY_GetTxPowerIndex_8723B(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); -#endif - -#if defined(CONFIG_RTL8192E) - if (IS_HARDWARE_TYPE_8192E(pAdapter)) - TxPower = PHY_GetTxPowerIndex_8192E(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); -#endif - -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) - TxPower = PHY_GetTxPowerIndex_8812A(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); -#endif - -#if defined(CONFIG_RTL8814A) - if (IS_HARDWARE_TYPE_8814A(pAdapter)) - TxPower = PHY_GetTxPowerIndex_8814A(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); -#endif - -#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) - if (IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) - TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); -#endif - -#if defined(CONFIG_RTL8703B) - if (IS_HARDWARE_TYPE_8703B(pAdapter)) - TxPower = PHY_GetTxPowerIndex_8703B(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); -#endif + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); -#if defined(CONFIG_RTL8188F) - if (IS_HARDWARE_TYPE_8188F(pAdapter)) - TxPower = PHY_GetTxPowerIndex_8188F(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); -#endif + ULONG TxPower = 1; + u1Byte rate = 0; + struct txpwr_idx_comp tic; + u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index); -#if defined(CONFIG_RTL8723D) - if (IS_HARDWARE_TYPE_8723D(pAdapter)) - TxPower = PHY_GetTxPowerIndex_8723D(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); -#endif + TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel, &tic); - RTW_INFO("txPower=%d ,CurrentChannelBW=%d ,CurrentChannel=%d ,rate =%d\n", - TxPower, pHalData->CurrentChannelBW, pHalData->CurrentChannel, mgn_rate); + RTW_INFO("bw=%d, ch=%d, rate=%d, txPower:%u = %u + (%d=%d:%d) + (%d) + (%d)\n", + pHalData->current_channel_bw, pHalData->current_channel, mgn_rate + , TxPower, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias); pAdapter->mppriv.txpoweridx = (u8)TxPower; pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)TxPower; diff --git a/core/rtw_mp_ioctl.c b/core/rtw_mp_ioctl.c index 0e7fee6..035d281 100644 --- a/core/rtw_mp_ioctl.c +++ b/core/rtw_mp_ioctl.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_MP_IOCTL_C_ #include @@ -29,7 +24,6 @@ NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; if (poid_par_priv->information_buf_len < sizeof(u8)) return NDIS_STATUS_INVALID_LENGTH; @@ -39,11 +33,9 @@ NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv *poid_par_priv) else if (poid_par_priv->type_of_oid == QUERY_OID) { *(u8 *)poid_par_priv->information_buf = Adapter->registrypriv.wireless_mode; *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_info_, ("-query Wireless Mode=%d\n", Adapter->registrypriv.wireless_mode)); } else status = NDIS_STATUS_NOT_ACCEPTED; - _func_exit_; return status; } @@ -59,9 +51,7 @@ NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_write_bb_reg_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -77,15 +67,11 @@ NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv *poid_par_priv) value = pbbreg->value; - RT_TRACE(_module_mp_, _drv_notice_, - ("oid_rt_pro_write_bb_reg_hdl: offset=0x%03X value=0x%08X\n", - offset, value)); _irqlevel_changed_(&oldirql, LOWER); write_bbreg(Adapter, offset, 0xFFFFFFFF, value); _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -101,9 +87,7 @@ NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_bb_reg_hdl\n")); if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -124,10 +108,6 @@ NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv *poid_par_priv) pbbreg->value = value; *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_notice_, - ("-oid_rt_pro_read_bb_reg_hdl: offset=0x%03X value:0x%08X\n", - offset, value)); - _func_exit_; return status; } @@ -144,9 +124,7 @@ NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_write_rf_reg_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -167,15 +145,11 @@ NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv *poid_par_priv) offset = (u8)pbbreg->offset; value = pbbreg->value; - RT_TRACE(_module_mp_, _drv_notice_, - ("oid_rt_pro_write_rf_reg_hdl: path=%d offset=0x%02X value=0x%05X\n", - path, offset, value)); _irqlevel_changed_(&oldirql, LOWER); write_rfreg(Adapter, path, offset, value); _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -192,9 +166,7 @@ NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv *poid_par_priv) PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); NDIS_STATUS status = NDIS_STATUS_SUCCESS; - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_rf_reg_hdl\n")); if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -220,11 +192,7 @@ NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv *poid_par_priv) *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_notice_, - ("-oid_rt_pro_read_rf_reg_hdl: path=%d offset=0x%02X value=0x%05X\n", - path, offset, value)); - _func_exit_; return status; } @@ -242,10 +210,7 @@ NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, - ("+oid_rt_pro_set_data_rate_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -254,8 +219,6 @@ NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv) return NDIS_STATUS_INVALID_LENGTH; ratevalue = *((u32 *)poid_par_priv->information_buf); /* 4 */ - RT_TRACE(_module_mp_, _drv_notice_, - ("oid_rt_pro_set_data_rate_hdl: data rate idx=%d\n", ratevalue)); if (ratevalue >= MPT_RATE_LAST) return NDIS_STATUS_INVALID_DATA; @@ -265,7 +228,6 @@ NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv) SetDataRate(Adapter); _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -279,9 +241,7 @@ NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_start_test_hdl\n")); if (Adapter->registrypriv.mp_mode == 0) return NDIS_STATUS_NOT_ACCEPTED; @@ -304,9 +264,7 @@ NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv *poid_par_priv) exit: _irqlevel_changed_(&oldirql, RAISE); - RT_TRACE(_module_mp_, _drv_notice_, ("-oid_rt_pro_start_test_hdl: mp_mode=%d\n", Adapter->mppriv.mode)); - _func_exit_; return status; } @@ -319,9 +277,7 @@ NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_STOP_TEST\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -330,9 +286,7 @@ NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv *poid_par_priv) mp_stop_test(Adapter); _irqlevel_changed_(&oldirql, RAISE); - RT_TRACE(_module_mp_, _drv_notice_, ("-Set OID_RT_PRO_STOP_TEST\n")); - _func_exit_; return status; } @@ -346,9 +300,7 @@ NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_channel_direct_call_hdl\n")); if (poid_par_priv->information_buf_len != sizeof(u32)) return NDIS_STATUS_INVALID_LENGTH; @@ -362,7 +314,6 @@ NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par return NDIS_STATUS_NOT_ACCEPTED; Channel = *((u32 *)poid_par_priv->information_buf); - RT_TRACE(_module_mp_, _drv_notice_, ("oid_rt_pro_set_channel_direct_call_hdl: Channel=%d\n", Channel)); if (Channel > 14) return NDIS_STATUS_NOT_ACCEPTED; Adapter->mppriv.channel = Channel; @@ -371,7 +322,6 @@ NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par SetChannel(Adapter); _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -386,10 +336,7 @@ NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_info_, - ("+oid_rt_set_bandwidth_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -409,11 +356,7 @@ NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv *poid_par_priv) SetBandwidth(padapter); _irqlevel_changed_(&oldirql, RAISE); - RT_TRACE(_module_mp_, _drv_notice_, - ("-oid_rt_set_bandwidth_hdl: bandwidth=%d channel_offset=%d\n", - bandwidth, channel_offset)); - _func_exit_; return status; } @@ -427,9 +370,7 @@ NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_antenna_bb_hdl\n")); if (poid_par_priv->information_buf_len != sizeof(u32)) return NDIS_STATUS_INVALID_LENGTH; @@ -439,9 +380,6 @@ NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv) Adapter->mppriv.antenna_tx = (u16)((antenna & 0xFFFF0000) >> 16); Adapter->mppriv.antenna_rx = (u16)(antenna & 0x0000FFFF); - RT_TRACE(_module_mp_, _drv_notice_, - ("oid_rt_pro_set_antenna_bb_hdl: tx_ant=0x%04x rx_ant=0x%04x\n", - Adapter->mppriv.antenna_tx, Adapter->mppriv.antenna_rx)); _irqlevel_changed_(&oldirql, LOWER); SetAntenna(Adapter); @@ -451,7 +389,6 @@ NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv) *(u32 *)poid_par_priv->information_buf = antenna; } - _func_exit_; return status; } @@ -465,9 +402,7 @@ NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv *poid_par_pr NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_set_tx_power_control_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -481,15 +416,11 @@ NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv *poid_par_pr Adapter->mppriv.txpoweridx = (u8)tx_pwr_idx; - RT_TRACE(_module_mp_, _drv_notice_, - ("oid_rt_pro_set_tx_power_control_hdl: idx=0x%2x\n", - Adapter->mppriv.txpoweridx)); _irqlevel_changed_(&oldirql, LOWER); SetTxPower(Adapter); _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -502,7 +433,6 @@ NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv *poid_par_pr NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; if (poid_par_priv->type_of_oid != QUERY_OID) { status = NDIS_STATUS_NOT_ACCEPTED; @@ -515,7 +445,6 @@ NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv *poid_par_pr } else status = NDIS_STATUS_INVALID_LENGTH; - _func_exit_; return status; } @@ -525,21 +454,17 @@ NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv *poid_pa NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; if (poid_par_priv->type_of_oid != QUERY_OID) { status = NDIS_STATUS_NOT_ACCEPTED; return status; } - RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_query_rx_packet_received_hdl.\n")); if (poid_par_priv->information_buf_len == sizeof(ULONG)) { *(ULONG *)poid_par_priv->information_buf = Adapter->mppriv.rx_pktcount; *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_alert_, ("recv_ok:%d\n", Adapter->mppriv.rx_pktcount)); } else status = NDIS_STATUS_INVALID_LENGTH; - _func_exit_; return status; } @@ -549,21 +474,17 @@ NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv *poid NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; if (poid_par_priv->type_of_oid != QUERY_OID) { status = NDIS_STATUS_NOT_ACCEPTED; return status; } - RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_query_rx_packet_crc32_error_hdl.\n")); if (poid_par_priv->information_buf_len == sizeof(ULONG)) { *(ULONG *)poid_par_priv->information_buf = Adapter->mppriv.rx_crcerrpktcount; *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_alert_, ("recv_err:%d\n", Adapter->mppriv.rx_crcerrpktcount)); } else status = NDIS_STATUS_INVALID_LENGTH; - _func_exit_; return status; } @@ -574,17 +495,14 @@ NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv *poid_par_pr NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) { status = NDIS_STATUS_NOT_ACCEPTED; return status; } - RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_reset_tx_packet_sent_hdl.\n")); Adapter->mppriv.tx_pktcount = 0; - _func_exit_; return status; } @@ -594,7 +512,6 @@ NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv *poid_pa NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) { status = NDIS_STATUS_NOT_ACCEPTED; @@ -607,7 +524,6 @@ NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv *poid_pa } else status = NDIS_STATUS_INVALID_LENGTH; - _func_exit_; return status; } @@ -620,7 +536,6 @@ NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv *poid_par_p NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) { status = NDIS_STATUS_NOT_ACCEPTED; @@ -631,7 +546,6 @@ NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv *poid_par_p ResetPhyRxPktCount(Adapter); _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -644,9 +558,7 @@ NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv *poid_par_ NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_get_phy_rx_packet_received_hdl\n")); if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -660,9 +572,7 @@ NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv *poid_par_ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_notice_, ("-oid_rt_get_phy_rx_packet_received_hdl: recv_ok=%d\n", *(ULONG *)poid_par_priv->information_buf)); - _func_exit_; return status; } @@ -675,9 +585,7 @@ NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_p NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_get_phy_rx_packet_crc32_error_hdl\n")); if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -692,9 +600,7 @@ NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_p *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_get_phy_rx_packet_crc32_error_hdl: recv_err=%d\n", *(ULONG *)poid_par_priv->information_buf)); - _func_exit_; return status; } @@ -708,9 +614,7 @@ NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_continuous_tx_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -732,7 +636,6 @@ NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv *poid_par_priv) } _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -746,9 +649,7 @@ NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv *poid_par_p NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_alert_, ("+oid_rt_pro_set_single_carrier_tx_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -770,7 +671,6 @@ NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv *poid_par_p } _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -784,9 +684,7 @@ NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv *poid_ NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_carrier_suppression_tx_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -808,7 +706,6 @@ NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv *poid_ } _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -822,9 +719,7 @@ NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv *poid_par_priv NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_alert_, ("+oid_rt_pro_set_single_tone_tx_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -835,7 +730,6 @@ NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv *poid_par_priv SetSingleToneTx(Adapter, (u8)bStartTest); _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -853,7 +747,6 @@ NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv) _irqL oldirql; #endif NDIS_STATUS status = NDIS_STATUS_SUCCESS; - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -862,7 +755,6 @@ NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv) rtw_hal_set_hwreg(Adapter, HW_VAR_TRIGGER_GPIO_0, 0); _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -880,7 +772,6 @@ NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv *poid_par_priv) PNDIS_802_11_SSID pssid; - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -901,7 +792,6 @@ NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv *poid_par_priv) *poid_par_priv->bytes_rw = sizeof(NDIS_802_11_SSID); - _func_exit_; return status; #else @@ -919,10 +809,7 @@ NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_info_, - ("+oid_rt_pro_read_register_hdl\n")); if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -948,15 +835,11 @@ NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv) RegRWStruct->value = rtw_read32(Adapter, offset); break; } - RT_TRACE(_module_mp_, _drv_notice_, - ("oid_rt_pro_read_register_hdl: offset:0x%04X value:0x%X\n", - offset, RegRWStruct->value)); _irqlevel_changed_(&oldirql, RAISE); *poid_par_priv->bytes_rw = width; - _func_exit_; return status; } @@ -971,10 +854,7 @@ NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_info_, - ("+oid_rt_pro_write_register_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1014,11 +894,7 @@ NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv) _irqlevel_changed_(&oldirql, RAISE); - RT_TRACE(_module_mp_, _drv_info_, - ("-oid_rt_pro_write_register_hdl: offset=0x%08X width=%d value=0x%X\n", - offset, width, value)); - _func_exit_; return status; } @@ -1033,9 +909,7 @@ NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv *poid_par_pri NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_burst_read_register_hdl\n")); if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1048,9 +922,7 @@ NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv *poid_par_pri *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_burst_read_register_hdl\n")); - _func_exit_; return status; #else @@ -1068,9 +940,7 @@ NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv *poid_par_pr NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_burst_write_register_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1081,9 +951,7 @@ NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv *poid_par_pr rtw_write_mem(padapter, pBstRwReg->offset, (u32)pBstRwReg->len, pBstRwReg->Data); _irqlevel_changed_(&oldirql, RAISE); - RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_burst_write_register_hdl\n")); - _func_exit_; return status; #else @@ -1104,20 +972,13 @@ NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv *poid_par_priv) TX_CMD_Desc *TxCmd_Info; - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; - RT_TRACE(_module_mp_, _drv_info_, ("+Set OID_RT_PRO_WRITE_TXCMD\n")); TxCmd_Info = (TX_CMD_Desc *)poid_par_priv->information_buf; - RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:Addr=%.8X\n", TxCmd_Info->offset)); - RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:1.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[0])); - RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:2.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[1])); - RT_TRACE(_module_mp_, _drv_info_, (("WRITE_TXCMD:3.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[2])); - RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:4.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[3])); _irqlevel_changed_(&oldirql, LOWER); @@ -1126,10 +987,7 @@ NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv *poid_par_priv) _irqlevel_changed_(&oldirql, RAISE); - RT_TRACE(_module_mp_, _drv_notice_, - ("-Set OID_RT_PRO_WRITE_TXCMD: status=0x%08X\n", status)); - _func_exit_; return status; #else @@ -1148,9 +1006,7 @@ NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_info_, ("+Query OID_RT_PRO_READ16_EEPROM\n")); if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1163,11 +1019,7 @@ NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv *poid_par_priv) *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_notice_, - ("-Query OID_RT_PRO_READ16_EEPROM: offset=0x%x value=0x%x\n", - pEEPROM->offset, pEEPROM->value)); - _func_exit_; return status; #else @@ -1186,9 +1038,7 @@ NDIS_STATUS oid_rt_pro_write16_eeprom_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_WRITE16_EEPROM\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1201,7 +1051,6 @@ NDIS_STATUS oid_rt_pro_write16_eeprom_hdl(struct oid_par_priv *poid_par_priv) *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - _func_exit_; return status; #else @@ -1218,7 +1067,6 @@ NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv *poid_par_priv) struct mp_wiparam *pwi_param; - _func_enter_; if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1233,10 +1081,8 @@ NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv *poid_par_priv) _rtw_memcpy(pwi_param, &Adapter->mppriv.workparam, sizeof(struct mp_wiparam)); Adapter->mppriv.act_in_progress = _FALSE; - /* RT_TRACE(_module_mp_, _drv_info_, ("rf:%x\n", pwiparam->IoValue)); */ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - _func_exit_; return status; #else @@ -1251,15 +1097,12 @@ NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro8711_pkt_loss_hdl\n")); if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; if (poid_par_priv->information_buf_len < sizeof(uint) * 2) { - RT_TRACE(_module_mp_, _drv_err_, ("-oid_rt_pro8711_pkt_loss_hdl: buf_len=%d\n", (int)poid_par_priv->information_buf_len)); return NDIS_STATUS_INVALID_LENGTH; } @@ -1269,7 +1112,6 @@ NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv *poid_par_priv) *((uint *)poid_par_priv->information_buf + 1) = Adapter->mppriv.rx_pktloss; *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - _func_exit_; return status; #else @@ -1293,9 +1135,7 @@ NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv *poid_par_priv) void (*_attrib_read)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); #endif - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+Query OID_RT_RD_ATTRIB_MEM\n")); if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1312,7 +1152,6 @@ NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv *poid_par_priv) _irqlevel_changed_(&oldirql, RAISE); #endif - _func_exit_; return status; #else @@ -1336,7 +1175,6 @@ NDIS_STATUS oid_rt_wr_attrib_mem_hdl(struct oid_par_priv *poid_par_priv) void (*_attrib_write)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); #endif - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1352,7 +1190,6 @@ NDIS_STATUS oid_rt_wr_attrib_mem_hdl(struct oid_par_priv *poid_par_priv) _irqlevel_changed_(&oldirql, RAISE); #endif - _func_exit_; return status; #else @@ -1370,9 +1207,7 @@ NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv *poid_par_priv) #endif NDIS_STATUS status = NDIS_STATUS_SUCCESS; - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+OID_RT_PRO_SET_RF_INTFS\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1384,7 +1219,6 @@ NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv *poid_par_priv) _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; #else @@ -1399,7 +1233,6 @@ NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; - _func_enter_; if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1407,7 +1240,6 @@ NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv *poid_par_priv) _rtw_memcpy(poid_par_priv->information_buf, (unsigned char *)&Adapter->mppriv.rxstat, sizeof(struct recv_stat)); *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - _func_exit_; return status; #else @@ -1424,38 +1256,26 @@ NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv *poid_par_priv) PCFG_DBG_MSG_STRUCT pdbg_msg; - _func_enter_; - /* RT_TRACE(0xffffffffff,_drv_alert_,("===> oid_rt_pro_cfg_debug_message_hdl.\n")); */ #if 0/*#ifdef CONFIG_DEBUG_RTL871X*/ pdbg_msg = (PCFG_DBG_MSG_STRUCT)(poid_par_priv->information_buf); if (poid_par_priv->type_of_oid == SET_OID) { - RT_TRACE(0xffffffffff, _drv_alert_, - ("===>Set level :0x%08x, H32:0x%08x L32:0x%08x\n", - pdbg_msg->DebugLevel, pdbg_msg->DebugComponent_H32, pdbg_msg->DebugComponent_L32)); GlobalDebugLevel = pdbg_msg->DebugLevel; GlobalDebugComponents = (pdbg_msg->DebugComponent_H32 << 32) | pdbg_msg->DebugComponent_L32; - RT_TRACE(0xffffffffff, _drv_alert_, - ("===> Set level :0x%08x, component:0x%016x\n", - GlobalDebugLevel, (u32)GlobalDebugComponents)); } else { pdbg_msg->DebugLevel = GlobalDebugLevel; pdbg_msg->DebugComponent_H32 = (u32)(GlobalDebugComponents >> 32); pdbg_msg->DebugComponent_L32 = (u32)GlobalDebugComponents; *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(0xffffffffff, _drv_alert_, - ("===>Query level:0x%08x H32:0x%08x L32:0x%08x\n", - (u32)pdbg_msg->DebugLevel, (u32)pdbg_msg->DebugComponent_H32, (u32)pdbg_msg->DebugComponent_L32)); } #endif - _func_exit_; return status; #else @@ -1472,9 +1292,7 @@ NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv *poid_par_priv) #endif NDIS_STATUS status = NDIS_STATUS_SUCCESS; - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+OID_RT_PRO_SET_DATA_RATE_EX\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1486,7 +1304,6 @@ NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv *poid_par_priv) _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -1500,9 +1317,7 @@ NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv *poid_par_priv) u8 thermal = 0; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_get_thermal_meter_hdl\n")); if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1517,7 +1332,6 @@ NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv *poid_par_priv) *(u32 *)poid_par_priv->information_buf = (u32)thermal; *poid_par_priv->bytes_rw = sizeof(u32); - _func_exit_; return status; } @@ -1532,9 +1346,7 @@ NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv *poid_par_priv) #endif NDIS_STATUS status = NDIS_STATUS_SUCCESS; - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_tssi_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1559,7 +1371,6 @@ NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv *poid_par_priv) _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; #else @@ -1576,7 +1387,6 @@ NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv *poid_par_priv PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; /* if (poid_par_priv->type_of_oid != SET_OID) * return NDIS_STATUS_NOT_ACCEPTED; */ @@ -1589,15 +1399,12 @@ NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv *poid_par_priv u8 enable; enable = *(u8 *)poid_par_priv->information_buf; - RT_TRACE(_module_mp_, _drv_notice_, - ("+oid_rt_pro_set_power_tracking_hdl: enable=%d\n", enable)); SetPowerTracking(Adapter, enable); } else GetPowerTracking(Adapter, (u8 *)poid_par_priv->information_buf); _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -1614,9 +1421,7 @@ NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - RT_TRACE(_module_mp_, _drv_info_, ("+OID_RT_PRO_SET_BASIC_RATE\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1628,7 +1433,6 @@ NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv) datarates[i] = mpdatarate[i]; else datarates[i] = 0xff; - RT_TRACE(_module_rtl871x_ioctl_c_, _drv_info_, ("basicrate_inx=%d\n", datarates[i])); } _irqlevel_changed_(&oldirql, LOWER); @@ -1638,10 +1442,7 @@ NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv) _irqlevel_changed_(&oldirql, RAISE); #endif - RT_TRACE(_module_mp_, _drv_notice_, - ("-OID_RT_PRO_SET_BASIC_RATE: status=0x%08X\n", status)); - _func_exit_; return status; #else @@ -1656,7 +1457,6 @@ NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; - _func_enter_; if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1668,11 +1468,7 @@ NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv *poid_par_priv) _rtw_memcpy(poid_par_priv->information_buf, &(adapter_to_pwrctl(Adapter)->pwr_mode), 8); *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_notice_, - ("-oid_rt_pro_qry_pwrstate_hdl: pwr_mode=%d smart_ps=%d\n", - adapter_to_pwrctl(Adapter)->pwr_mode, adapter_to_pwrctl(Adapter)->smart_ps)); - _func_exit_; return status; #else @@ -1689,9 +1485,7 @@ NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv *poid_par_priv) uint pwr_mode, smart_ps; - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_SET_PWRSTATE\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1707,7 +1501,6 @@ NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv *poid_par_priv) *poid_par_priv->bytes_rw = 8; - _func_exit_; return status; #else @@ -1728,7 +1521,6 @@ NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv *poid_par_priv struct setratable_parm *prate_table; u8 res; - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1746,7 +1538,6 @@ NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv *poid_par_priv if (res == _FAIL) status = NDIS_STATUS_FAILURE; - _func_exit_; return status; #else @@ -1761,7 +1552,6 @@ NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv *poid_par_priv NDIS_STATUS status = NDIS_STATUS_SUCCESS; - _func_enter_; if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -1791,7 +1581,6 @@ NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv *poid_par_priv DEBUG_INFO(("\n <=== Set OID_RT_PRO_H2C_GET_RATE_TABLE.\n")); #endif - _func_exit_; return status; #else @@ -1856,9 +1645,6 @@ NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv *poid_par_priv) break; } - RT_TRACE(_module_rtl871x_ioctl_c_, _drv_notice_, - ("-oid_rt_pro_encryption_ctrl_hdl: SET encry_mode=0x%x sw_encrypt=0x%x sw_decrypt=0x%x\n", - encry_mode, psecuritypriv->sw_encrypt, psecuritypriv->sw_decrypt)); } else { #if 0 if (Adapter->registrypriv.software_encrypt == _FALSE) { @@ -1888,9 +1674,6 @@ NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv *poid_par_priv) *(u8 *)poid_par_priv->information_buf = encry_mode; *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_notice_, - ("-oid_rt_pro_encryption_ctrl_hdl: QUERY encry_mode=0x%x\n", - encry_mode)); } return status; @@ -1922,8 +1705,6 @@ NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv *poid_par_priv) macaddr = (UCHAR *) poid_par_priv->information_buf ; - RT_TRACE(_module_rtl871x_ioctl_c_, _drv_notice_, - ("OID_RT_PRO_ADD_STA_INFO: addr="MAC_FMT"\n", MAC_ARG(macaddr))); _irqlevel_changed_(&oldirql, LOWER); @@ -1933,12 +1714,8 @@ NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv *poid_par_priv) psta = rtw_alloc_stainfo(&Adapter->stapriv, macaddr); if (psta == NULL) { - RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, ("Can't alloc sta_info when OID_RT_PRO_ADD_STA_INFO\n")); status = NDIS_STATUS_FAILURE; } - } else { /* (between drv has received this event before and fw have not yet to set key to CAM_ENTRY) */ - RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, - ("Error: OID_RT_PRO_ADD_STA_INFO: sta has been in sta_hash_queue\n")); } _irqlevel_changed_(&oldirql, RAISE); @@ -1971,8 +1748,6 @@ NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv *poid_par_priv) return NDIS_STATUS_INVALID_LENGTH; macaddr = (UCHAR *) poid_par_priv->information_buf ; - RT_TRACE(_module_rtl871x_ioctl_c_, _drv_notice_, - ("+OID_RT_PRO_ADD_STA_INFO: addr="MAC_FMT"\n", MAC_ARG(macaddr))); psta = rtw_get_stainfo(&Adapter->stapriv, macaddr); if (psta != NULL) { @@ -1995,9 +1770,7 @@ static u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var) if (offset == 1) { u16 tmp_blk_num; tmp_blk_num = rtw_read16(padapter, SDIO_RX0_RDYBLK_NUM); - RT_TRACE(_module_mp_, _drv_err_, ("Query Information, mp_query_drv_var SDIO_RX0_RDYBLK_NUM=0x%x dvobj.rxblknum=0x%x\n", tmp_blk_num, adapter_to_dvobj(padapter)->rxblknum)); if (adapter_to_dvobj(padapter)->rxblknum != tmp_blk_num) { - RT_TRACE(_module_mp_, _drv_err_, ("Query Information, mp_query_drv_var call recv rx\n")); /* sd_recv_rxfifo(padapter); */ } } @@ -2005,72 +1778,43 @@ static u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var) #if 0 if (offset <= 100) { /* For setting data rate and query data rate */ if (offset == 100) { /* For query data rate */ - RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d): query rate=0x%.2x\n", offset, padapter->registrypriv.tx_rate)); var = padapter->registrypriv.tx_rate; } else if (offset < 0x1d) { /* For setting data rate */ padapter->registrypriv.tx_rate = offset; var = padapter->registrypriv.tx_rate; padapter->registrypriv.use_rate = _TRUE; - RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d): set rate=0x%.2x\n", offset, padapter->registrypriv.tx_rate)); } else { /* not use the data rate */ padapter->registrypriv.use_rate = _FALSE; - RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d) out of rate range\n", offset)); } } else if (offset <= 110) { /* for setting debug level */ - RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d) for set debug level\n", offset)); if (offset == 110) { /* For query data rate */ - RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d): query dbg level=0x%.2x\n", offset, padapter->registrypriv.dbg_level)); padapter->registrypriv.dbg_level = GlobalDebugLevel; var = padapter->registrypriv.dbg_level; } else if (offset < 110 && offset > 100) { - RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d): set dbg level=0x%.2x\n", offset, offset - 100)); padapter->registrypriv.dbg_level = GlobalDebugLevel = offset - 100; var = padapter->registrypriv.dbg_level; - RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var(_drv_emerg_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel)); - RT_TRACE(_module_mp_, _drv_alert_, (" mp_query_drv_var(_drv_alert_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel)); - RT_TRACE(_module_mp_, _drv_crit_, (" mp_query_drv_var(_drv_crit_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel)); - RT_TRACE(_module_mp_, _drv_err_, (" mp_query_drv_var(_drv_err_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel)); - RT_TRACE(_module_mp_, _drv_warning_, (" mp_query_drv_var(_drv_warning_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel)); - RT_TRACE(_module_mp_, _drv_notice_, (" mp_query_drv_var(_drv_notice_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel)); - RT_TRACE(_module_mp_, _drv_info_, (" mp_query_drv_var(_drv_info_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel)); - RT_TRACE(_module_mp_, _drv_debug_, (" mp_query_drv_var(_drv_debug_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel)); } } else if (offset > 110 && offset < 116) { if (115 == offset) { - RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var(_drv_emerg_): offset(%d): query TRX access type: [tx_block_mode=%x,rx_block_mode=%x]\n", \ - offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj( - padapter)->rx_block_mode)); } else { switch (offset) { case 111: adapter_to_dvobj(padapter)->tx_block_mode = 1; adapter_to_dvobj(padapter)->rx_block_mode = 1; - RT_TRACE(_module_mp_, _drv_emerg_, \ - (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX block/RX block) [tx_block_mode=%x,rx_block_mode=%x]\n", \ - offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); break; case 112: adapter_to_dvobj(padapter)->tx_block_mode = 1; adapter_to_dvobj(padapter)->rx_block_mode = 0; - RT_TRACE(_module_mp_, _drv_emerg_, \ - (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX block/RX byte) [tx_block_mode=%x,rx_block_mode=%x]\n", \ - offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); break; case 113: adapter_to_dvobj(padapter)->tx_block_mode = 0; adapter_to_dvobj(padapter)->rx_block_mode = 1; - RT_TRACE(_module_mp_, _drv_emerg_, \ - (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX byte/RX block) [tx_block_mode=%x,rx_block_mode=%x]\n", \ - offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); break; case 114: adapter_to_dvobj(padapter)->tx_block_mode = 0; adapter_to_dvobj(padapter)->rx_block_mode = 0; - RT_TRACE(_module_mp_, _drv_emerg_, \ - (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX byte/RX byte) [tx_block_mode=%x,rx_block_mode=%x]\n", \ - offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); break; default: break; @@ -2086,31 +1830,15 @@ static u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var) chg_idx = offset - 0x80; tmp_dbg_comp = BIT(chg_idx); prnt_dbg_comp = padapter->registrypriv.dbg_component = GlobalDebugComponents; - RT_TRACE(_module_mp_, _drv_emerg_, - (" 1: mp_query_drv_var: offset(%d;0x%x):for dbg conpoment prnt_dbg_comp=0x%.16x GlobalDebugComponents=0x%.16x padapter->registrypriv.dbg_component=0x%.16x\n", offset, offset, - prnt_dbg_comp, GlobalDebugComponents, padapter->registrypriv.dbg_component)); if (offset == 127) { /* prnt_dbg_comp=padapter->registrypriv.dbg_component= GlobalDebugComponents; */ var = (u32)(padapter->registrypriv.dbg_component); - RT_TRACE(0xffffffff, _drv_emerg_, ("2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n", offset, offset, - padapter->registrypriv.dbg_component, prnt_dbg_comp)); prnt_dbg_comp = GlobalDebugComponents; - RT_TRACE(0xffffffff, _drv_emerg_, ("2-1: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n", offset, offset, - padapter->registrypriv.dbg_component, prnt_dbg_comp)); prnt_dbg_comp = GlobalDebugComponents = padapter->registrypriv.dbg_component; - RT_TRACE(0xffffffff, _drv_emerg_, ("2-2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n", offset, offset, - padapter->registrypriv.dbg_component, prnt_dbg_comp)); } else { - RT_TRACE(0xffffffff, _drv_emerg_, ("3: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) chg_idx=%d\n", offset, - offset, padapter->registrypriv.dbg_component, prnt_dbg_comp, chg_idx)); prnt_dbg_comp = GlobalDebugComponents; - RT_TRACE(0xffffffff, _drv_emerg_, ("3-1: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) chg_idx=%d\n", offset, - offset, padapter->registrypriv.dbg_component, prnt_dbg_comp, - chg_idx)); /* ("3-1: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment=0x%x chg_idx=%d or0x%x BIT(chg_idx[%d]=0x%x)\n",offset,offset,prnt_dbg_comp,chg_idx,chg_idx,(chg_idx),tmp_dbg_comp) */ prnt_dbg_comp = GlobalDebugComponents = padapter->registrypriv.dbg_component; - RT_TRACE(0xffffffff, _drv_emerg_, ("3-2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n", offset, offset, - padapter->registrypriv.dbg_component, prnt_dbg_comp)); if (GlobalDebugComponents & tmp_dbg_comp) { /* this bit is already set, now clear it */ @@ -2119,68 +1847,13 @@ static u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var) /* this bit is not set, now set it. */ GlobalDebugComponents = GlobalDebugComponents | tmp_dbg_comp; } - RT_TRACE(0xffffffff, _drv_emerg_, ("4: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment tmp_dbg_comp=0x%x GlobalDebugComponents=0x%x(l) 0x%x(h)", offset, offset, - tmp_dbg_comp, prnt_dbg_comp)); prnt_dbg_comp = GlobalDebugComponents; - RT_TRACE(0xffffffff, _drv_emerg_, ("4-1: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment tmp_dbg_comp=0x%x GlobalDebugComponents=0x%x(l) 0x%x(h)", offset, offset, - tmp_dbg_comp, prnt_dbg_comp)); - - RT_TRACE(_module_rtl871x_xmit_c_, _drv_emerg_, ("0: mp_query_drv_var(_module_rtl871x_xmit_c_:0): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - prnt_dbg_comp)); - RT_TRACE(_module_xmit_osdep_c_, _drv_emerg_, ("1: mp_query_drv_var(_module_xmit_osdep_c_:1): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_rtl871x_recv_c_, _drv_emerg_, ("2: mp_query_drv_var(_module_rtl871x_recv_c_:2): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_recv_osdep_c_, _drv_emerg_, ("3: mp_query_drv_var(_module_recv_osdep_c_:3): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_emerg_, ("4: mp_query_drv_var(_module_rtl871x_mlme_c_:4): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_mlme_osdep_c_, _drv_emerg_, (" 5:mp_query_drv_var(_module_mlme_osdep_c_:5): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_emerg_, ("6: mp_query_drv_var(_module_rtl871x_sta_mgt_c_:6): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, - offset, GlobalDebugComponents)); - RT_TRACE(_module_rtl871x_cmd_c_, _drv_emerg_, ("7: mp_query_drv_var(_module_rtl871x_cmd_c_:7): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_cmd_osdep_c_, _drv_emerg_, ("8: mp_query_drv_var(_module_cmd_osdep_c_:8): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_rtl871x_io_c_, _drv_emerg_, ("9: mp_query_drv_var(_module_rtl871x_io_c_:9): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_io_osdep_c_, _drv_emerg_, ("10: mp_query_drv_var(_module_io_osdep_c_:10): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_os_intfs_c_, _drv_emerg_, ("11: mp_query_drv_var(_module_os_intfs_c_:11): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_rtl871x_security_c_, _drv_emerg_, ("12: mp_query_drv_var(_module_rtl871x_security_c_:12): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, - offset, GlobalDebugComponents)); - RT_TRACE(_module_rtl871x_eeprom_c_, _drv_emerg_, ("13: mp_query_drv_var(_module_rtl871x_eeprom_c_:13): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, - offset, GlobalDebugComponents)); - RT_TRACE(_module_hal_init_c_, _drv_emerg_, ("14: mp_query_drv_var(_module_hal_init_c_:14): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_hci_hal_init_c_, _drv_emerg_, ("15: mp_query_drv_var(_module_hci_hal_init_c_:15): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_rtl871x_ioctl_c_, _drv_emerg_, ("16: mp_query_drv_var(_module_rtl871x_ioctl_c_:16): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, - offset, GlobalDebugComponents)); - RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_emerg_, ("17: mp_query_drv_var(_module_rtl871x_ioctl_set_c_:17): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", - offset, offset, GlobalDebugComponents)); - RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_emerg_, ("18: mp_query_drv_var(_module_rtl871x_ioctl_query_c_:18): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", - offset, offset, GlobalDebugComponents)); - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_emerg_, ("19: mp_query_drv_var(_module_rtl871x_pwrctrl_c_:19): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, - offset, GlobalDebugComponents)); - RT_TRACE(_module_hci_intfs_c_, _drv_emerg_, ("20: mp_query_drv_var(_module_hci_intfs_c_:20): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_hci_ops_c_, _drv_emerg_, ("21: mp_query_drv_var(_module_hci_ops_c_:21): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); - RT_TRACE(_module_osdep_service_c_, _drv_emerg_, ("22: mp_query_drv_var(_module_osdep_service_c_:22): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, - offset, GlobalDebugComponents)); - RT_TRACE(_module_mp_, _drv_emerg_, ("23: mp_query_drv_var(_module_mp_:23): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, GlobalDebugComponents)); - RT_TRACE(_module_hci_ops_os_c_, _drv_emerg_, ("24: mp_query_drv_var(_module_hci_ops_os_c_:24): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, - GlobalDebugComponents)); + var = (u32)(GlobalDebugComponents); /* GlobalDebugComponents=padapter->registrypriv.dbg_component; */ - RT_TRACE(0xffffffff, _drv_emerg_, (" ==mp_query_drv_var(_module_mp_): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, GlobalDebugComponents)); } - } else - RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d) >110\n", offset)); + } #endif #endif @@ -2208,7 +1881,6 @@ NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv *poid_par_priv) if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) return NDIS_STATUS_INVALID_LENGTH; - RT_TRACE(_module_mp_, _drv_notice_, ("+Query Information, OID_RT_PRO_QUERY_DR_VARIABLE\n")); pdrv_var = (struct _DR_VARIABLE_STRUCT_ *)poid_par_priv->information_buf; @@ -2218,9 +1890,6 @@ NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv *poid_par_priv) *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_notice_, - ("-oid_rt_pro_query_dr_variable_hdl: offset=0x%x valule=0x%x\n", - pdrv_var->offset, pdrv_var->variable)); return status; #else @@ -2235,7 +1904,6 @@ NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; - RT_TRACE(_module_mp_, _drv_err_, ("oid_rt_pro_rx_packet_type_hdl...................\n")); if (poid_par_priv->information_buf_len < sizeof(UCHAR)) { status = NDIS_STATUS_INVALID_LENGTH; @@ -2245,25 +1913,15 @@ NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv) if (poid_par_priv->type_of_oid == SET_OID) { Adapter->mppriv.rx_with_status = *(UCHAR *) poid_par_priv->information_buf; - RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d\n", \ - Adapter->mppriv.rx_with_status)); - RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, ("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x\n", - Adapter->eeprompriv.mac_addr[0], Adapter->eeprompriv.mac_addr[1], Adapter->eeprompriv.mac_addr[2], \ - Adapter->eeprompriv.mac_addr[3], Adapter->eeprompriv.mac_addr[4], Adapter->eeprompriv.mac_addr[5])); } else { *(UCHAR *) poid_par_priv->information_buf = Adapter->mppriv.rx_with_status; *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d\n", \ - Adapter->mppriv.rx_with_status)); /* *(u32 *)&Adapter->eeprompriv.mac_addr[0]=rtw_read32(Adapter, 0x10250050); */ /* *(u16 *)&Adapter->eeprompriv.mac_addr[4]=rtw_read16(Adapter, 0x10250054); */ - RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, ("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x\n", - Adapter->eeprompriv.mac_addr[0], Adapter->eeprompriv.mac_addr[1], Adapter->eeprompriv.mac_addr[2], \ - Adapter->eeprompriv.mac_addr[3], Adapter->eeprompriv.mac_addr[4], Adapter->eeprompriv.mac_addr[5])); } #endif @@ -2281,7 +1939,6 @@ NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -2294,26 +1951,20 @@ NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv) cnts = pefuse->cnts; data = pefuse->data; - RT_TRACE(_module_mp_, _drv_notice_, - ("+oid_rt_pro_read_efuse_hd: buf_len=%d addr=%d cnts=%d\n", - poid_par_priv->information_buf_len, addr, cnts)); EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); if ((addr + cnts) > max_available_size) { - RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_read_efuse_hdl: parameter error!\n")); return NDIS_STATUS_NOT_ACCEPTED; } _irqlevel_changed_(&oldirql, LOWER); if (rtw_efuse_access(Adapter, _FALSE, addr, cnts, data) == _FAIL) { - RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_read_efuse_hdl: rtw_efuse_access FAIL!\n")); status = NDIS_STATUS_FAILURE; } else *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -2330,7 +1981,6 @@ NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv) PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -2340,14 +1990,10 @@ NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv) cnts = pefuse->cnts; data = pefuse->data; - RT_TRACE(_module_mp_, _drv_notice_, - ("+oid_rt_pro_write_efuse_hdl: buf_len=%d addr=0x%04x cnts=%d\n", - poid_par_priv->information_buf_len, addr, cnts)); EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); if ((addr + cnts) > max_available_size) { - RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_write_efuse_hdl: parameter error")); return NDIS_STATUS_NOT_ACCEPTED; } @@ -2356,7 +2002,6 @@ NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv) status = NDIS_STATUS_FAILURE; _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; } @@ -2370,9 +2015,7 @@ NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; - /* RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_rw_efuse_pgpkt_hdl\n")); */ *poid_par_priv->bytes_rw = 0; @@ -2384,9 +2027,6 @@ NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv) _irqlevel_changed_(&oldirql, LOWER); if (poid_par_priv->type_of_oid == QUERY_OID) { - RT_TRACE(_module_mp_, _drv_notice_, - ("oid_rt_pro_rw_efuse_pgpkt_hdl: Read offset=0x%x\n", \ - ppgpkt->offset)); Efuse_PowerSwitch(Adapter, _FALSE, _TRUE); if (Efuse_PgPacketRead(Adapter, ppgpkt->offset, ppgpkt->data, _FALSE) == _TRUE) @@ -2395,9 +2035,6 @@ NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv) status = NDIS_STATUS_FAILURE; Efuse_PowerSwitch(Adapter, _FALSE, _FALSE); } else { - RT_TRACE(_module_mp_, _drv_notice_, - ("oid_rt_pro_rw_efuse_pgpkt_hdl: Write offset=0x%x word_en=0x%x\n", \ - ppgpkt->offset, ppgpkt->word_en)); Efuse_PowerSwitch(Adapter, _TRUE, _TRUE); if (Efuse_PgPacketWrite(Adapter, ppgpkt->offset, ppgpkt->word_en, ppgpkt->data, _FALSE) == _TRUE) @@ -2409,10 +2046,7 @@ NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv) _irqlevel_changed_(&oldirql, RAISE); - RT_TRACE(_module_mp_, _drv_info_, - ("-oid_rt_pro_rw_efuse_pgpkt_hdl: status=0x%08X\n", status)); - _func_exit_; return status; } @@ -2427,7 +2061,6 @@ NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -2444,7 +2077,6 @@ NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv } else status = NDIS_STATUS_FAILURE; - _func_exit_; return status; } @@ -2454,7 +2086,6 @@ NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); - _func_enter_; if (poid_par_priv->type_of_oid != QUERY_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -2465,11 +2096,7 @@ NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv *poid_par_priv) *(u32 *)poid_par_priv->information_buf = efuse_GetMaxSize(Adapter); *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - RT_TRACE(_module_mp_, _drv_info_, - ("-oid_rt_get_efuse_max_size_hdl: size=%d status=0x%08X\n", - *(int *)poid_par_priv->information_buf, status)); - _func_exit_; return status; } @@ -2478,18 +2105,14 @@ NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv) { NDIS_STATUS status; - _func_enter_; - RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_efuse_hdl\n")); if (poid_par_priv->type_of_oid == QUERY_OID) status = oid_rt_pro_read_efuse_hdl(poid_par_priv); else status = oid_rt_pro_write_efuse_hdl(poid_par_priv); - RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_efuse_hdl: status=0x%08X\n", status)); - _func_exit_; return status; } @@ -2504,9 +2127,7 @@ NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv) PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); u16 mapLen = 0; - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_efuse_map_hdl\n")); EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); @@ -2520,36 +2141,25 @@ NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv) _irqlevel_changed_(&oldirql, LOWER); if (poid_par_priv->type_of_oid == QUERY_OID) { - RT_TRACE(_module_mp_, _drv_info_, - ("oid_rt_pro_efuse_map_hdl: READ\n")); if (rtw_efuse_map_read(Adapter, 0, mapLen, data) == _SUCCESS) *poid_par_priv->bytes_rw = mapLen; else { - RT_TRACE(_module_mp_, _drv_err_, - ("oid_rt_pro_efuse_map_hdl: READ fail\n")); status = NDIS_STATUS_FAILURE; } } else { /* SET_OID */ - RT_TRACE(_module_mp_, _drv_info_, - ("oid_rt_pro_efuse_map_hdl: WRITE\n")); if (rtw_efuse_map_write(Adapter, 0, mapLen, data) == _SUCCESS) *poid_par_priv->bytes_rw = mapLen; else { - RT_TRACE(_module_mp_, _drv_err_, - ("oid_rt_pro_efuse_map_hdl: WRITE fail\n")); status = NDIS_STATUS_FAILURE; } } _irqlevel_changed_(&oldirql, RAISE); - RT_TRACE(_module_mp_, _drv_info_, - ("-oid_rt_pro_efuse_map_hdl: status=0x%08X\n", status)); - _func_exit_; return status; } @@ -2566,7 +2176,6 @@ NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv *poid_par_priv) u32 crystal_cap = 0; - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -2584,7 +2193,6 @@ NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv *poid_par_priv) SetCrystalCap(Adapter); _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; #endif return status; @@ -2600,9 +2208,7 @@ NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv) NDIS_STATUS status = NDIS_STATUS_SUCCESS; /* PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); */ - _func_enter_; - RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_set_rx_packet_type_hdl\n")); if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -2612,7 +2218,6 @@ NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv) rx_pkt_type = *((u8 *)poid_par_priv->information_buf); /* 4 */ - RT_TRACE(_module_mp_, _drv_info_, ("rx_pkt_type: %x\n", rx_pkt_type)); #if 0 _irqlevel_changed_(&oldirql, LOWER); #if 0 @@ -2668,7 +2273,6 @@ NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv) #endif _irqlevel_changed_(&oldirql, RAISE); #endif - _func_exit_; return status; } @@ -2685,7 +2289,6 @@ NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv *poid_par_priv) u32 txagc; - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -2694,14 +2297,11 @@ NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv *poid_par_priv) return NDIS_STATUS_INVALID_LENGTH; txagc = *(u32 *)poid_par_priv->information_buf; - RT_TRACE(_module_mp_, _drv_info_, - ("oid_rt_pro_set_tx_agc_offset_hdl: 0x%08x\n", txagc)); _irqlevel_changed_(&oldirql, LOWER); SetTxAGCOffset(Adapter, txagc); _irqlevel_changed_(&oldirql, RAISE); - _func_exit_; return status; #else @@ -2720,7 +2320,6 @@ NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv *poid_par_priv) struct mp_priv *pmppriv = &Adapter->mppriv; u32 type; - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) return NDIS_STATUS_NOT_ACCEPTED; @@ -2733,15 +2332,12 @@ NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv *poid_par_priv) if (_LOOPBOOK_MODE_ == type) { pmppriv->mode = type; set_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE); /* append txdesc */ - RT_TRACE(_module_mp_, _drv_info_, ("test mode change to loopback mode:0x%08x.\n", get_fwstate(pmlmepriv))); } else if (_2MAC_MODE_ == type) { pmppriv->mode = type; _clr_fwstate_(pmlmepriv, WIFI_MP_LPBK_STATE); - RT_TRACE(_module_mp_, _drv_info_, ("test mode change to 2mac mode:0x%08x.\n", get_fwstate(pmlmepriv))); } else status = NDIS_STATUS_NOT_ACCEPTED; - _func_exit_; return status; #else @@ -2756,7 +2352,6 @@ unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv) struct mp_priv *pmp_priv; struct pkt_attrib *pattrib; - RT_TRACE(_module_mp_, _drv_notice_, ("+%s\n", __func__)); pparm = (PMP_XMIT_PARM)poid_par_priv->information_buf; padapter = (PADAPTER)poid_par_priv->adapter_context; @@ -2839,7 +2434,7 @@ unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv) fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - SetFrameSubType(pframe, WIFI_DATA); + set_frame_sub_type(pframe, WIFI_DATA); _rtw_memcpy(pwlanhdr->addr1, pethhdr->h_dest, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, pethhdr->h_source, ETH_ALEN); @@ -2876,15 +2471,12 @@ NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv *poid_par_priv) #endif #endif - _func_enter_; if (poid_par_priv->type_of_oid != SET_OID) { status = NDIS_STATUS_NOT_ACCEPTED; return status; } - RT_TRACE(_module_mp_, _drv_info_, - ("\n ===> Setoid_rt_set_power_down_hdl.\n")); _irqlevel_changed_(&oldirql, LOWER); @@ -2900,7 +2492,6 @@ NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv *poid_par_priv) /* DEBUG_ERR(("\n <=== Query OID_RT_PRO_READ_REGISTER. */ /* Add:0x%08x Width:%d Value:0x%08x\n",RegRWStruct->offset,RegRWStruct->width,RegRWStruct->value)); */ - _func_exit_; return status; } @@ -2914,7 +2505,6 @@ NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv *poid_par_priv) /* _irqL oldirql; * #endif */ - _func_enter_; if (poid_par_priv->type_of_oid != QUERY_OID) { status = NDIS_STATUS_NOT_ACCEPTED; @@ -2925,15 +2515,12 @@ NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv *poid_par_priv) return status; } - RT_TRACE(_module_mp_, _drv_info_, - ("\n ===> oid_rt_get_power_mode_hdl.\n")); /* _irqlevel_changed_(&oldirql, LOWER); */ *(int *)poid_par_priv->information_buf = Adapter->registrypriv.low_power ? POWER_LOW : POWER_NORMAL; *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; /* _irqlevel_changed_(&oldirql, RAISE); */ - _func_exit_; return status; #else diff --git a/core/rtw_odm.c b/core/rtw_odm.c index 780cc39..7cb9d5f 100644 --- a/core/rtw_odm.c +++ b/core/rtw_odm.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,174 +11,58 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #include -const char *odm_comp_str[] = { - /* BIT0 */"ODM_COMP_DIG", - /* BIT1 */"ODM_COMP_RA_MASK", - /* BIT2 */"ODM_COMP_DYNAMIC_TXPWR", - /* BIT3 */"ODM_COMP_FA_CNT", - /* BIT4 */"ODM_COMP_RSSI_MONITOR", - /* BIT5 */"ODM_COMP_CCK_PD", - /* BIT6 */"ODM_COMP_ANT_DIV", - /* BIT7 */"ODM_COMP_PWR_SAVE", - /* BIT8 */"ODM_COMP_PWR_TRAIN", - /* BIT9 */"ODM_COMP_RATE_ADAPTIVE", - /* BIT10 */"ODM_COMP_PATH_DIV", - /* BIT11 */"ODM_COMP_PSD", - /* BIT12 */"ODM_COMP_DYNAMIC_PRICCA", - /* BIT13 */"ODM_COMP_RXHP", - /* BIT14 */"ODM_COMP_MP", - /* BIT15 */"ODM_COMP_CFO_TRACKING", - /* BIT16 */"ODM_COMP_ACS", - /* BIT17 */"PHYDM_COMP_ADAPTIVITY", - /* BIT18 */"PHYDM_COMP_RA_DBG", - /* BIT19 */"PHYDM_COMP_TXBF", - /* BIT20 */"ODM_COMP_EDCA_TURBO", - /* BIT21 */"ODM_COMP_EARLY_MODE", - /* BIT22 */"ODM_FW_DEBUG_TRACE", - /* BIT23 */NULL, - /* BIT24 */"ODM_COMP_TX_PWR_TRACK", - /* BIT25 */"ODM_COMP_RX_GAIN_TRACK", - /* BIT26 */"ODM_COMP_CALIBRATION", - /* BIT27 */NULL, - /* BIT28 */"ODM_PHY_CONFIG", - /* BIT29 */"BEAMFORMING_DEBUG", - /* BIT30 */"ODM_COMP_COMMON", - /* BIT31 */"ODM_COMP_INIT", - /* BIT32 */"ODM_COMP_NOISY_DETECT", - /* BIT33 */"ODM_COMP_DFS", -}; - -#define RTW_ODM_COMP_MAX 34 - -const char *odm_ability_str[] = { - /* BIT0 */"ODM_BB_DIG", - /* BIT1 */"ODM_BB_RA_MASK", - /* BIT2 */"ODM_BB_DYNAMIC_TXPWR", - /* BIT3 */"ODM_BB_FA_CNT", - /* BIT4 */"ODM_BB_RSSI_MONITOR", - /* BIT5 */"ODM_BB_CCK_PD", - /* BIT6 */"ODM_BB_ANT_DIV", - /* BIT7 */"ODM_BB_PWR_SAVE", - /* BIT8 */"ODM_BB_PWR_TRAIN", - /* BIT9 */"ODM_BB_RATE_ADAPTIVE", - /* BIT10 */"ODM_BB_PATH_DIV", - /* BIT11 */"ODM_BB_PSD", - /* BIT12 */"ODM_BB_RXHP", - /* BIT13 */"ODM_BB_ADAPTIVITY", - /* BIT14 */"ODM_BB_CFO_TRACKING", - /* BIT15 */"ODM_BB_NHM_CNT", - /* BIT16 */"ODM_BB_PRIMARY_CCA", - /* BIT17 */"ODM_BB_TXBF", - /* BIT18 */NULL, - /* BIT19 */NULL, - /* BIT20 */"ODM_MAC_EDCA_TURBO", - /* BIT21 */"ODM_MAC_EARLY_MODE", - /* BIT22 */NULL, - /* BIT23 */NULL, - /* BIT24 */"ODM_RF_TX_PWR_TRACK", - /* BIT25 */"ODM_RF_RX_GAIN_TRACK", - /* BIT26 */"ODM_RF_CALIBRATION", -}; - -#define RTW_ODM_ABILITY_MAX 27 - -const char *odm_dbg_level_str[] = { - NULL, - "ODM_DBG_OFF", - "ODM_DBG_SERIOUS", - "ODM_DBG_WARNING", - "ODM_DBG_LOUD", - "ODM_DBG_TRACE", -}; - -#define RTW_ODM_DBG_LEVEL_NUM 6 - -void rtw_odm_dbg_comp_msg(void *sel, _adapter *adapter) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - DM_ODM_T *odm = &pHalData->odmpriv; - int cnt = 0; - u64 dbg_comp = 0; - int i; - - rtw_hal_get_odm_var(adapter, HAL_ODM_DBG_FLAG, &dbg_comp, NULL); - - RTW_PRINT_SEL(sel, "odm.DebugComponents = 0x%016llx\n", dbg_comp); - for (i = 0; i < RTW_ODM_COMP_MAX; i++) { - if (odm_comp_str[i]) - RTW_PRINT_SEL(sel, "%cBIT%-2d %s\n", - (BIT0 & (dbg_comp >> i)) ? '+' : ' ', i, odm_comp_str[i]); - } -} - -inline void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps) -{ - rtw_hal_set_odm_var(adapter, HAL_ODM_DBG_FLAG, &comps, _FALSE); -} - -void rtw_odm_dbg_level_msg(void *sel, _adapter *adapter) +u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - DM_ODM_T *odm = &pHalData->odmpriv; - int cnt = 0; - u32 dbg_level = 0; - int i; - - rtw_hal_get_odm_var(adapter, HAL_ODM_DBG_LEVEL, &dbg_level, NULL); - RTW_PRINT_SEL(sel, "odm.DebugLevel = %u\n", dbg_level); - for (i = 0; i < RTW_ODM_DBG_LEVEL_NUM; i++) { - if (odm_dbg_level_str[i]) - RTW_PRINT_SEL(sel, "%u %s\n", i, odm_dbg_level_str[i]); - } -} - -inline void rtw_odm_dbg_level_set(_adapter *adapter, u32 level) -{ - rtw_hal_set_odm_var(adapter, HAL_ODM_DBG_LEVEL, &level, _FALSE); -} + struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv; + u32 result = 0; -void rtw_odm_ability_msg(void *sel, _adapter *adapter) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - DM_ODM_T *odm = &pHalData->odmpriv; - int cnt = 0; - u32 ability = 0; - int i; - - ability = rtw_phydm_ability_get(adapter); - RTW_PRINT_SEL(sel, "odm.SupportAbility = 0x%08x\n", ability); - for (i = 0; i < RTW_ODM_ABILITY_MAX; i++) { - if (odm_ability_str[i]) - RTW_PRINT_SEL(sel, "%cBIT%-2d %s\n", - (BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]); + switch (ops) { + case HAL_PHYDM_DIS_ALL_FUNC: + podmpriv->support_ability = DYNAMIC_FUNC_DISABLE; + halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, DYNAMIC_FUNC_DISABLE); + break; + case HAL_PHYDM_FUNC_SET: + podmpriv->support_ability |= ability; + break; + case HAL_PHYDM_FUNC_CLR: + podmpriv->support_ability &= ~(ability); + break; + case HAL_PHYDM_ABILITY_BK: + /* dm flag backup*/ + podmpriv->bk_support_ability = podmpriv->support_ability; + pHalData->bk_rf_ability = halrf_cmn_info_get(podmpriv, HALRF_CMNINFO_ABILITY); + break; + case HAL_PHYDM_ABILITY_RESTORE: + /* restore dm flag */ + podmpriv->support_ability = podmpriv->bk_support_ability; + halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, pHalData->bk_rf_ability); + break; + case HAL_PHYDM_ABILITY_SET: + podmpriv->support_ability = ability; + break; + case HAL_PHYDM_ABILITY_GET: + result = podmpriv->support_ability; + break; } -} - -inline void rtw_odm_ability_set(_adapter *adapter, u32 ability) -{ - rtw_phydm_ability_set(adapter, ability); + return result; } /* set ODM_CMNINFO_IC_TYPE based on chip_type */ void rtw_odm_init_ic_type(_adapter *adapter) { HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - DM_ODM_T *odm = &hal_data->odmpriv; + struct PHY_DM_STRUCT *odm = &hal_data->odmpriv; u4Byte ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter)); rtw_warn_on(!ic_type); - ODM_CmnInfoInit(odm, ODM_CMNINFO_IC_TYPE, ic_type); + odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type); } inline void rtw_odm_set_force_igi_lb(_adapter *adapter, u8 lb) @@ -208,7 +92,7 @@ void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter) struct registry_priv *regsty = &adapter->registrypriv; struct mlme_priv *mlme = &adapter->mlmepriv; HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - DM_ODM_T *odm = &hal_data->odmpriv; + struct PHY_DM_STRUCT *odm = &hal_data->odmpriv; RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_"); @@ -285,50 +169,50 @@ bool rtw_odm_adaptivity_needed(_adapter *adapter) void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - DM_ODM_T *odm = &pHalData->odmpriv; + struct PHY_DM_STRUCT *odm = &pHalData->odmpriv; rtw_odm_adaptivity_config_msg(sel, adapter); RTW_PRINT_SEL(sel, "%10s %16s %16s %22s %12s\n" - , "TH_L2H_ini", "TH_EDCCA_HL_diff", "TH_L2H_ini_mode2", "TH_EDCCA_HL_diff_mode2", "EDCCA_enable"); + , "th_l2h_ini", "th_edcca_hl_diff", "th_l2h_ini_mode2", "th_edcca_hl_diff_mode2", "edcca_enable"); RTW_PRINT_SEL(sel, "0x%-8x %-16d 0x%-14x %-22d %-12d\n" - , (u8)odm->TH_L2H_ini - , odm->TH_EDCCA_HL_diff - , (u8)odm->TH_L2H_ini_mode2 - , odm->TH_EDCCA_HL_diff_mode2 - , odm->EDCCA_enable - ); + , (u8)odm->th_l2h_ini + , odm->th_edcca_hl_diff + , (u8)odm->th_l2h_ini_mode2 + , odm->th_edcca_hl_diff_mode2 + , odm->edcca_enable + ); RTW_PRINT_SEL(sel, "%15s %9s\n", "AdapEnableState", "Adap_Flag"); RTW_PRINT_SEL(sel, "%-15x %-9x\n" - , odm->Adaptivity_enable - , odm->adaptivity_flag - ); + , odm->adaptivity_enable + , odm->adaptivity_flag + ); } -void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff, s8 TH_L2H_ini_mode2, s8 TH_EDCCA_HL_diff_mode2, u8 EDCCA_enable) +void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff, s8 th_l2h_ini_mode2, s8 th_edcca_hl_diff_mode2, u8 edcca_enable) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - DM_ODM_T *odm = &pHalData->odmpriv; + struct PHY_DM_STRUCT *odm = &pHalData->odmpriv; - odm->TH_L2H_ini = TH_L2H_ini; - odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff; - odm->TH_L2H_ini_mode2 = TH_L2H_ini_mode2; - odm->TH_EDCCA_HL_diff_mode2 = TH_EDCCA_HL_diff_mode2; - odm->EDCCA_enable = EDCCA_enable; + odm->th_l2h_ini = th_l2h_ini; + odm->th_edcca_hl_diff = th_edcca_hl_diff; + odm->th_l2h_ini_mode2 = th_l2h_ini_mode2; + odm->th_edcca_hl_diff_mode2 = th_edcca_hl_diff_mode2; + odm->edcca_enable = edcca_enable; } void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter) { HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - DM_ODM_T *odm = &(hal_data->odmpriv); + struct PHY_DM_STRUCT *odm = &(hal_data->odmpriv); - RTW_PRINT_SEL(sel, "RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n", - HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B); + RTW_PRINT_SEL(sel, "rx_rate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n", + HDATA_RATE(odm->rx_rate), odm->RSSI_A, odm->RSSI_B); } -void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type) +void rtw_odm_acquirespinlock(_adapter *adapter, enum rt_spinlock_type type) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); _irqL irqL; @@ -341,7 +225,7 @@ void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type) } } -void rtw_odm_releasespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type) +void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); _irqL irqL; @@ -354,15 +238,28 @@ void rtw_odm_releasespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type) } } -#ifdef CONFIG_DFS_MASTER inline u8 rtw_odm_get_dfs_domain(_adapter *adapter) { +#ifdef CONFIG_DFS_MASTER HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - PDM_ODM_T pDM_Odm = &(hal_data->odmpriv); + struct PHY_DM_STRUCT *pDM_Odm = &(hal_data->odmpriv); + + return pDM_Odm->dfs_region_domain; +#else + return PHYDM_DFS_DOMAIN_UNKNOWN; +#endif +} - return pDM_Odm->DFS_RegionDomain; +inline u8 rtw_odm_dfs_domain_unknown(_adapter *adapter) +{ +#ifdef CONFIG_DFS_MASTER + return rtw_odm_get_dfs_domain(adapter) == PHYDM_DFS_DOMAIN_UNKNOWN; +#else + return 1; +#endif } +#ifdef CONFIG_DFS_MASTER inline VOID rtw_odm_radar_detect_reset(_adapter *adapter) { phydm_radar_detect_reset(GET_ODM(adapter)); @@ -384,3 +281,196 @@ inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter) return phydm_radar_detect(GET_ODM(adapter)); } #endif /* CONFIG_DFS_MASTER */ + +void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys) +{ +#ifndef DBG_RX_PHYSTATUS_CHINFO +#define DBG_RX_PHYSTATUS_CHINFO 0 +#endif + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + _adapter *adapter = rframe->u.hdr.adapter; + struct PHY_DM_STRUCT *phydm = GET_ODM(adapter); + struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib; + u8 *wlanhdr = get_recvframe_data(rframe); + + if (phydm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) { + /* + * 8723D: + * type_0(CCK) + * l_rxsc + * is filled with primary channel SC, not real rxsc. + * 0:LSC, 1:USC + * type_1(OFDM) + * rf_mode + * RF bandwidth when RX + * l_rxsc(legacy), ht_rxsc + * see below RXSC N-series + * type_2(Not used) + */ + /* + * 8821C, 8822B: + * type_0(CCK) + * l_rxsc + * is filled with primary channel SC, not real rxsc. + * 0:LSC, 1:USC + * type_1(OFDM) + * rf_mode + * RF bandwidth when RX + * l_rxsc(legacy), ht_rxsc + * see below RXSC AC-series + * type_2(Not used) + */ + + if ((*phys & 0xf) == 0) { + struct _phy_status_rpt_jaguar2_type0 *phys_t0 = (struct _phy_status_rpt_jaguar2_type0 *)phys; + + if (DBG_RX_PHYSTATUS_CHINFO) { + RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n" + , *phys & 0xf + , MAC_ARG(get_ta(wlanhdr)) + , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC" + , HDATA_RATE(attrib->data_rate) + , phys_t0->band, phys_t0->channel, phys_t0->rxsc + ); + } + + } else if ((*phys & 0xf) == 1) { + struct _phy_status_rpt_jaguar2_type1 *phys_t1 = (struct _phy_status_rpt_jaguar2_type1 *)phys; + u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc; + u8 pkt_cch = 0; + u8 pkt_bw = CHANNEL_WIDTH_20; + + #if ODM_IC_11N_SERIES_SUPPORT + if (phydm->support_ic_type & ODM_IC_11N_SERIES) { + /* RXSC N-series */ + #define RXSC_DUP 0 + #define RXSC_LSC 1 + #define RXSC_USC 2 + #define RXSC_40M 3 + + static const s8 cch_offset_by_rxsc[4] = {0, -2, 2, 0}; + + if (phys_t1->rf_mode == 0) { + pkt_cch = phys_t1->channel; + pkt_bw = CHANNEL_WIDTH_20; + } else if (phys_t1->rf_mode == 1) { + if (rxsc == RXSC_LSC || rxsc == RXSC_USC) { + pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc]; + pkt_bw = CHANNEL_WIDTH_20; + } else if (rxsc == RXSC_40M) { + pkt_cch = phys_t1->channel; + pkt_bw = CHANNEL_WIDTH_40; + } + } else + rtw_warn_on(1); + + goto type1_end; + } + #endif /* ODM_IC_11N_SERIES_SUPPORT */ + + #if ODM_IC_11AC_SERIES_SUPPORT + if (phydm->support_ic_type & ODM_IC_11AC_SERIES) { + /* RXSC AC-series */ + #define RXSC_DUP 0 /* 0: RX from all SC of current rf_mode */ + + #define RXSC_LL20M_OF_160M 8 /* 1~8: RX from 20MHz SC */ + #define RXSC_L20M_OF_160M 6 + #define RXSC_L20M_OF_80M 4 + #define RXSC_L20M_OF_40M 2 + #define RXSC_U20M_OF_40M 1 + #define RXSC_U20M_OF_80M 3 + #define RXSC_U20M_OF_160M 5 + #define RXSC_UU20M_OF_160M 7 + + #define RXSC_L40M_OF_160M 12 /* 9~12: RX from 40MHz SC */ + #define RXSC_L40M_OF_80M 10 + #define RXSC_U40M_OF_80M 9 + #define RXSC_U40M_OF_160M 11 + + #define RXSC_L80M_OF_160M 14 /* 13~14: RX from 80MHz SC */ + #define RXSC_U80M_OF_160M 13 + + static const s8 cch_offset_by_rxsc[15] = {0, 2, -2, 6, -6, 10, -10, 14, -14, 4, -4, 12, -12, 8, -8}; + + if (phys_t1->rf_mode > 3) { + /* invalid rf_mode */ + rtw_warn_on(1); + goto type1_end; + } + + if (phys_t1->rf_mode == 0) { + /* RF 20MHz */ + pkt_cch = phys_t1->channel; + pkt_bw = CHANNEL_WIDTH_20; + goto type1_end; + } + + if (rxsc == 0) { + /* RF and RX with same BW */ + if (attrib->data_rate >= DESC_RATEMCS0) { + pkt_cch = phys_t1->channel; + pkt_bw = phys_t1->rf_mode; + } + goto type1_end; + } + + if ((phys_t1->rf_mode == 1 && rxsc >= 1 && rxsc <= 2) /* RF 40MHz, RX 20MHz */ + || (phys_t1->rf_mode == 2 && rxsc >= 1 && rxsc <= 4) /* RF 80MHz, RX 20MHz */ + || (phys_t1->rf_mode == 3 && rxsc >= 1 && rxsc <= 8) /* RF 160MHz, RX 20MHz */ + ) { + pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc]; + pkt_bw = CHANNEL_WIDTH_20; + } else if ((phys_t1->rf_mode == 2 && rxsc >= 9 && rxsc <= 10) /* RF 80MHz, RX 40MHz */ + || (phys_t1->rf_mode == 3 && rxsc >= 9 && rxsc <= 12) /* RF 160MHz, RX 40MHz */ + ) { + if (attrib->data_rate >= DESC_RATEMCS0) { + pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc]; + pkt_bw = CHANNEL_WIDTH_40; + } + } else if ((phys_t1->rf_mode == 3 && rxsc >= 13 && rxsc <= 14) /* RF 160MHz, RX 80MHz */ + ) { + if (attrib->data_rate >= DESC_RATEMCS0) { + pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc]; + pkt_bw = CHANNEL_WIDTH_80; + } + } else + rtw_warn_on(1); + + } + #endif /* ODM_IC_11AC_SERIES_SUPPORT */ + +type1_end: + if (DBG_RX_PHYSTATUS_CHINFO) { + RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, rf_mode:%u, l_rxsc:%u, ht_rxsc:%u) => %u,%u\n" + , *phys & 0xf + , MAC_ARG(get_ta(wlanhdr)) + , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC" + , HDATA_RATE(attrib->data_rate) + , phys_t1->band, phys_t1->channel, phys_t1->rf_mode, phys_t1->l_rxsc, phys_t1->ht_rxsc + , pkt_cch, pkt_bw + ); + } + + /* for now, only return cneter channel of 20MHz packet */ + if (pkt_cch && pkt_bw == CHANNEL_WIDTH_20) + attrib->ch = pkt_cch; + + } else { + struct _phy_status_rpt_jaguar2_type2 *phys_t2 = (struct _phy_status_rpt_jaguar2_type2 *)phys; + + if (DBG_RX_PHYSTATUS_CHINFO) { + RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n" + , *phys & 0xf + , MAC_ARG(get_ta(wlanhdr)) + , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC" + , HDATA_RATE(attrib->data_rate) + , phys_t2->band, phys_t2->channel, phys_t2->l_rxsc, phys_t2->ht_rxsc + ); + } + } + } +#endif /* (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) */ + +} + diff --git a/core/rtw_p2p.c b/core/rtw_p2p.c index 02f6a31..906a556 100644 --- a/core/rtw_p2p.c +++ b/core/rtw_p2p.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_P2P_C_ #include @@ -52,7 +47,7 @@ static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf) _adapter *padapter = pwdinfo->padapter; struct sta_priv *pstapriv = &padapter->stapriv; - RTW_INFO("%s\n", __FUNCTION__); + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); pdata_attr = rtw_zmalloc(MAX_P2P_IE_LEN); @@ -182,7 +177,7 @@ static void issue_group_disc_req(struct wifidirect_info *pwdinfo, u8 *da) SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -242,7 +237,7 @@ static void issue_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 s SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -320,7 +315,7 @@ static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8 *raddr, SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -424,7 +419,7 @@ static void issue_p2p_presence_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -2328,7 +2323,7 @@ u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint l if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) return P2P_STATUS_FAIL_REQUEST_UNABLE; - frame_type = GetFrameSubType(pframe); + frame_type = get_frame_sub_type(pframe); if (frame_type == WIFI_ASSOCREQ) ie_offset = _ASOCREQ_IE_OFFSET_; else /* WIFI_REASSOCREQ */ @@ -2491,7 +2486,7 @@ u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint le /* issue Device Discoverability Response */ - issue_p2p_devdisc_resp(pwdinfo, GetAddr2Ptr(pframe), status, dialogToken); + issue_p2p_devdisc_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken); return (status == P2P_STATUS_SUCCESS) ? _TRUE : _FALSE; @@ -2535,7 +2530,7 @@ u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint l break; } } - issue_p2p_provision_resp(pwdinfo, GetAddr2Ptr(pframe), frame_body, uconfig_method); + issue_p2p_provision_resp(pwdinfo, get_addr2_ptr(pframe), frame_body, uconfig_method); } } RTW_INFO("[%s] config method = %s\n", __FUNCTION__, pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req); @@ -2571,26 +2566,15 @@ u8 rtw_p2p_get_peer_ch_list(struct wifidirect_info *pwdinfo, u8 *ch_content, u8 return ch_no; } -u8 rtw_p2p_check_peer_oper_ch(struct mlme_ext_priv *pmlmeext, u8 ch) -{ - u8 i = 0; - - for (i = 0; i < pmlmeext->max_chan_nums; i++) { - if (pmlmeext->channel_set[i].ChannelNum == ch) - return _SUCCESS; - } - - return _FAIL; -} - -u8 rtw_p2p_ch_inclusion(struct mlme_ext_priv *pmlmeext, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned) +u8 rtw_p2p_ch_inclusion(_adapter *adapter, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); int i = 0, j = 0, temp = 0; u8 ch_no = 0; for (i = 0; i < peer_ch_num; i++) { - for (j = temp; j < pmlmeext->max_chan_nums; j++) { - if (*(peer_ch_list + i) == pmlmeext->channel_set[j].ChannelNum) { + for (j = temp; j < rfctl->max_chan_nums; j++) { + if (*(peer_ch_list + i) == rfctl->channel_set[j].ChannelNum) { ch_list_inclusioned[ch_no++] = *(peer_ch_list + i); temp = j; break; @@ -2708,14 +2692,14 @@ u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, RTW_INFO(FUNC_ADPT_FMT" listen channel :%u\n", FUNC_ADPT_ARG(padapter), pwdinfo->nego_req_info.peer_ch); attr_contentlen = 0; - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENTED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) { + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) { if (attr_contentlen != ETH_ALEN) _rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN); } if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt)) { peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, ch_content, ch_cnt, peer_ch_list); - ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned); + ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned); if (ch_num_inclusioned == 0) { RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__); @@ -2853,7 +2837,7 @@ u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe /* Try to get the peer's interface address */ attr_contentlen = 0; - if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENTED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) { + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) { if (attr_contentlen != ETH_ALEN) _rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN); } @@ -2910,7 +2894,7 @@ u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe RTW_INFO("[%s] channel list attribute found, len = %d\n", __FUNCTION__, pwdinfo->channel_list_attr_len); peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, pwdinfo->channel_list_attr, pwdinfo->channel_list_attr_len, peer_ch_list); - ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned); + ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned); if (ch_num_inclusioned == 0) { RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__); @@ -3004,9 +2988,8 @@ u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pfr result = attr_content; if (attr_content == P2P_STATUS_SUCCESS) { - u8 bcancelled = 0; - _cancel_timer(&pwdinfo->restore_p2p_state_timer, &bcancelled); + _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); /* Commented by Albert 20100911 */ /* Todo: Need to handle the case which both Intents are the same. */ @@ -3073,7 +3056,7 @@ u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint le /* todo: check NoA attribute */ - issue_p2p_presence_resp(pwdinfo, GetAddr2Ptr(pframe), status, dialogToken); + issue_p2p_presence_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken); return _TRUE; } @@ -3086,7 +3069,6 @@ void find_phase_handler(_adapter *padapter) _irqL irqL; u8 _status = 0; - _func_enter_; _rtw_memset((unsigned char *)&ssid, 0, sizeof(NDIS_802_11_SSID)); _rtw_memcpy(ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN); @@ -3099,7 +3081,6 @@ void find_phase_handler(_adapter *padapter) _exit_critical_bh(&pmlmepriv->lock, &irqL); - _func_exit_; } void p2p_concurrent_handler(_adapter *padapter); @@ -3109,7 +3090,6 @@ void restore_p2p_state_handler(_adapter *padapter) struct wifidirect_info *pwdinfo = &padapter->wdinfo; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _func_enter_; if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); @@ -3122,6 +3102,10 @@ void restore_p2p_state_handler(_adapter *padapter) if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP)) { set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + #ifdef CONFIG_AP_MODE + /*mac-id sleep or wake-up for AP mode*/ + rtw_mi_buddy_ap_acdata_control(padapter, 0); + #endif/*CONFIG_AP_MODE*/ rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); } } @@ -3138,42 +3122,36 @@ void restore_p2p_state_handler(_adapter *padapter) set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); #endif } - _func_exit_; } void pre_tx_invitereq_handler(_adapter *padapter) { struct wifidirect_info *pwdinfo = &padapter->wdinfo; u8 val8 = 1; - _func_enter_; set_channel_bwmode(padapter, pwdinfo->invitereq_info.peer_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); issue_probereq_p2p(padapter, NULL); _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); - _func_exit_; } void pre_tx_provdisc_handler(_adapter *padapter) { struct wifidirect_info *pwdinfo = &padapter->wdinfo; u8 val8 = 1; - _func_enter_; set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); issue_probereq_p2p(padapter, NULL); _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); - _func_exit_; } void pre_tx_negoreq_handler(_adapter *padapter) { struct wifidirect_info *pwdinfo = &padapter->wdinfo; u8 val8 = 1; - _func_enter_; set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); @@ -3182,7 +3160,6 @@ void pre_tx_negoreq_handler(_adapter *padapter) issue_probereq_p2p(padapter , pwdinfo->nego_req_info.peerDevAddr); _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); - _func_exit_; } #ifdef CONFIG_CONCURRENT_MODE @@ -3192,7 +3169,6 @@ void p2p_concurrent_handler(_adapter *padapter) struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u8 val8; - _func_enter_; if (rtw_mi_check_status(padapter, MI_LINKED)) { u8 union_ch = rtw_mi_get_union_chan(padapter); @@ -3204,7 +3180,10 @@ void p2p_concurrent_handler(_adapter *padapter) if (pwdinfo->driver_interface == DRIVER_CFG80211) { RTW_INFO("%s, switch ch back to union_ch=%d\n", __func__, union_ch); set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - + #ifdef CONFIG_AP_MODE + /*mac-id sleep or wake-up for AP mode*/ + rtw_mi_buddy_ap_acdata_control(padapter, 0); + #endif/*CONFIG_AP_MODE*/ rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); } else if (pwdinfo->driver_interface == DRIVER_WEXT) { @@ -3215,6 +3194,10 @@ void p2p_concurrent_handler(_adapter *padapter) RTW_INFO("[%s] P2P_STATE_IDLE, ext_listen_period = %d\n", __FUNCTION__, pwdinfo->ext_listen_period); if (union_ch != pwdinfo->listen_channel) { + #ifdef CONFIG_AP_MODE + /*mac-id sleep or wake-up for AP mode*/ + rtw_mi_buddy_ap_acdata_control(padapter, 1); + #endif/*CONFIG_AP_MODE*/ /* Will switch to listen channel so that need to send the NULL data with PW bit to AP. */ rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); @@ -3248,6 +3231,10 @@ void p2p_concurrent_handler(_adapter *padapter) rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); } rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE); + #ifdef CONFIG_AP_MODE + /*mac-id sleep or wake-up for AP mode*/ + rtw_mi_buddy_ap_acdata_control(padapter, 0); + #endif/*CONFIG_AP_MODE*/ rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); } @@ -3258,6 +3245,10 @@ void p2p_concurrent_handler(_adapter *padapter) val8 = 0; rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + #ifdef CONFIG_AP_MODE + /*mac-id sleep or wake-up for AP mode*/ + rtw_mi_buddy_ap_acdata_control(padapter, 0); + #endif/*CONFIG_AP_MODE*/ rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) { val8 = 1; @@ -3289,18 +3280,44 @@ void p2p_concurrent_handler(_adapter *padapter) RTW_INFO("%s, buddy not linked, go nego ok, not back to listen channel\n", __func__); } - _func_exit_; } #endif #ifdef CONFIG_IOCTL_CFG80211 -static void ro_ch_handler(_adapter *padapter) +static int ro_ch_handler(_adapter *adapter, u8 *buf) +{ + /* TODO: move remain on channel logical here */ + return H2C_SUCCESS; +} + +static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf) { + int ret = H2C_SUCCESS; + struct p2p_roch_parm *roch_parm = (struct p2p_roch_parm *)buf; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; + struct wireless_dev *wdev; struct wifidirect_info *pwdinfo = &padapter->wdinfo; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; u8 ch, bw, offset; - _func_enter_; + + _enter_critical_mutex(&pwdev_priv->roch_mutex, NULL); + + if (rtw_cfg80211_get_is_roch(padapter) != _TRUE) + goto exit; + + if (roch_parm->wdev && roch_parm->cookie) { + if (pcfg80211_wdinfo->ro_ch_wdev != roch_parm->wdev) { + RTW_WARN(FUNC_ADPT_FMT" ongoing wdev:%p, wdev:%p\n" + , FUNC_ADPT_ARG(padapter), pcfg80211_wdinfo->ro_ch_wdev, roch_parm->wdev); + rtw_warn_on(1); + } + + if (pcfg80211_wdinfo->remain_on_ch_cookie != roch_parm->cookie) { + RTW_WARN(FUNC_ADPT_FMT" ongoing cookie:0x%llx, cookie:0x%llx\n" + , FUNC_ADPT_ARG(padapter), pcfg80211_wdinfo->remain_on_ch_cookie, roch_parm->cookie); + rtw_warn_on(1); + } + } if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) { if (0) @@ -3323,39 +3340,49 @@ static void ro_ch_handler(_adapter *padapter) } set_channel_bwmode(padapter, ch, offset, bw); + if (rtw_mi_buddy_check_fwstate(padapter, _FW_LINKED)) { + #ifdef CONFIG_AP_MODE + /*mac-id sleep or wake-up for AP mode*/ + rtw_mi_buddy_ap_acdata_control(padapter, 0); + #endif/*CONFIG_AP_MODE*/ + rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); + } + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); #endif - pcfg80211_wdinfo->is_ro_ch = _FALSE; + wdev = pcfg80211_wdinfo->ro_ch_wdev; + + rtw_cfg80211_set_is_roch(padapter, _FALSE); + pcfg80211_wdinfo->ro_ch_wdev = NULL; pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); - RTW_INFO("cfg80211_remain_on_channel_expired cookie:0x%llx, ch=%d, bw=%d, offset=%d\n" - , pcfg80211_wdinfo->remain_on_ch_cookie - , rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter), rtw_get_oper_choffset(padapter)); + rtw_cfg80211_remain_on_channel_expired(wdev + , pcfg80211_wdinfo->remain_on_ch_cookie + , &pcfg80211_wdinfo->remain_on_ch_channel + , pcfg80211_wdinfo->remain_on_ch_type, GFP_KERNEL); + + RTW_INFO("cfg80211_remain_on_channel_expired cookie:0x%llx\n" + , pcfg80211_wdinfo->remain_on_ch_cookie); + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_ScanNotify(padapter, _FALSE); +#endif - rtw_cfg80211_remain_on_channel_expired(padapter, - pcfg80211_wdinfo->remain_on_ch_cookie, - &pcfg80211_wdinfo->remain_on_ch_channel, - pcfg80211_wdinfo->remain_on_ch_type, GFP_KERNEL); +exit: + _exit_critical_mutex(&pwdev_priv->roch_mutex, NULL); - _func_exit_; + return ret; } static void ro_ch_timer_process(void *FunctionContext) { _adapter *adapter = (_adapter *)FunctionContext; - struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); - /* printk("%s\n", __FUNCTION__); */ - -#ifdef CONFIG_CONCURRENT_MODE - ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); -#endif - - p2p_protocol_wk_cmd(adapter, P2P_RO_CH_WK); + p2p_cancel_roch_cmd(adapter, 0, NULL, 0); } static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch) @@ -3363,6 +3390,11 @@ static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 u8 *ies, *p2p_ie; u32 ies_len, p2p_ielen; +#ifdef CONFIG_MCC_MODE + if (MCC_EN(padapter)) + return; +#endif /* CONFIG_MCC_MODE */ + ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; @@ -3389,6 +3421,11 @@ static void rtw_change_p2pie_ch_list(_adapter *padapter, const u8 *frame_body, u u8 *ies, *p2p_ie; u32 ies_len, p2p_ielen; +#ifdef CONFIG_MCC_MODE + if (MCC_EN(padapter)) + return; +#endif /* CONFIG_MCC_MODE */ + ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; @@ -3515,6 +3552,11 @@ static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *fram u32 ies_len, p2p_ielen; u8 union_ch = rtw_mi_get_union_chan(padapter); +#ifdef CONFIG_MCC_MODE + if (MCC_EN(padapter)) + return; +#endif /* CONFIG_MCC_MODE */ + ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; @@ -3536,8 +3578,14 @@ static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *fram while (attr_contentlen > 0) { num_of_ch = *(pattr_temp + 1); - for (i = 0; i < num_of_ch; i++) - *(pattr_temp + 2 + i) = union_ch; /*forcing to the same channel*/ + for (i = 0; i < num_of_ch; i++) { + if (*(pattr_temp + 2 + i) && *(pattr_temp + 2 + i) != union_ch) { + #ifdef RTW_SINGLE_WIPHY + RTW_ERR("replace ch_list:%u with:%u\n", *(pattr_temp + 2 + i), union_ch); + #endif + *(pattr_temp + 2 + i) = union_ch; /*forcing to the same channel*/ + } + } pattr_temp += (2 + num_of_ch); attr_contentlen -= (2 + num_of_ch); @@ -3549,7 +3597,12 @@ static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *fram pattr = NULL; pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen); if (pattr != NULL) { - *(pattr + 4) = union_ch; /*forcing to the same channel */ + if (*(pattr + 4) && *(pattr + 4) != union_ch) { + #ifdef RTW_SINGLE_WIPHY + RTW_ERR("replace op_ch:%u with:%u\n", *(pattr + 4), union_ch); + #endif + *(pattr + 4) = union_ch; /*forcing to the same channel */ + } } /* Get the next P2P IE */ @@ -3792,6 +3845,8 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) int op_ch = -1; int listen_ch = -1; u8 intent = 0; + u8 *iaddr = NULL; + u8 *gbssid = NULL; frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr)); category = frame_body[0]; @@ -3799,20 +3854,21 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) if (category == RTW_WLAN_CATEGORY_PUBLIC) { action = frame_body[1]; if (action == ACT_PUBLIC_VENDOR - && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE - ) { + && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE + ) { OUI_Subtype = frame_body[6]; dialogToken = frame_body[7]; is_p2p_frame = OUI_Subtype; -#ifdef CONFIG_DEBUG_CFG80211 + + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("ACTION_CATEGORY_PUBLIC: ACT_PUBLIC_VENDOR, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", cpu_to_be32(*((u32 *)(frame_body + 2))), OUI_Subtype, dialogToken); -#endif + #endif p2p_ie = rtw_get_p2p_ie( - (u8 *)buf + sizeof(struct rtw_ieee80211_hdr_3addr) + _PUBLIC_ACTION_IE_OFFSET_, - len - sizeof(struct rtw_ieee80211_hdr_3addr) - _PUBLIC_ACTION_IE_OFFSET_, - NULL, &p2p_ielen); + (u8 *)buf + sizeof(struct rtw_ieee80211_hdr_3addr) + _PUBLIC_ACTION_IE_OFFSET_ + , len - sizeof(struct rtw_ieee80211_hdr_3addr) - _PUBLIC_ACTION_IE_OFFSET_ + , NULL, &p2p_ielen); switch (OUI_Subtype) { /* OUI Subtype */ u8 *cont; @@ -3821,17 +3877,17 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info; if (tx) { -#ifdef CONFIG_DRV_ISSUE_PROV_REQ /* IOT FOR S2 */ + #ifdef CONFIG_DRV_ISSUE_PROV_REQ /* IOT FOR S2 */ if (pwdev_priv->provdisc_req_issued == _FALSE) rtw_cfg80211_issue_p2p_provision_request(padapter, buf, len); -#endif /* CONFIG_DRV_ISSUE_PROV_REQ */ + #endif /* CONFIG_DRV_ISSUE_PROV_REQ */ /* pwdev_priv->provdisc_req_issued = _FALSE; */ -#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)); -#endif + #endif } cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len); @@ -3843,11 +3899,16 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len); if (cont) intent = *cont; + cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, NULL, &cont_len); + if (cont && cont_len == 6) + iaddr = cont; if (nego_info->token != dialogToken) rtw_wdev_nego_info_init(nego_info); - _rtw_memcpy(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN); + _rtw_memcpy(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN); + if (iaddr) + _rtw_memcpy(tx ? nego_info->iface_addr : nego_info->peer_iface_addr, iaddr, ETH_ALEN); nego_info->active = tx ? 1 : 0; nego_info->token = dialogToken; nego_info->req_op_ch = op_ch; @@ -3856,19 +3917,21 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) nego_info->state = 0; dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); - RTW_INFO("RTW_%s:P2P_GO_NEGO_REQ, dialogToken=%d, intent:%u%s, listen_ch:%d, op_ch:%d, ch_list:%s, full_ch_in_p2p_handshake:%d\n" , - (tx == _TRUE) ? "Tx" : "Rx" , dialogToken , (intent >> 1) , intent & 0x1 ? "+" : "-" , listen_ch , op_ch , ch_list_buf , - padapter->registrypriv.full_ch_in_p2p_handshake); + RTW_INFO("RTW_%s:P2P_GO_NEGO_REQ, dialogToken=%d, intent:%u%s, listen_ch:%d, op_ch:%d, ch_list:%s" + , (tx == _TRUE) ? "Tx" : "Rx" , dialogToken , (intent >> 1) , intent & 0x1 ? "+" : "-" , listen_ch , op_ch , ch_list_buf); + if (iaddr) + _RTW_INFO(", iaddr:"MAC_FMT, MAC_ARG(iaddr)); + _RTW_INFO("\n"); if (!tx) { -#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) if (rtw_mi_check_status(padapter, MI_LINKED) && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter)); rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0); } -#endif + #endif } break; @@ -3877,10 +3940,10 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info; if (tx) { -#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)); -#endif + #endif } cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len); @@ -3892,10 +3955,15 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len); if (cont) status = *cont; + cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, NULL, &cont_len); + if (cont && cont_len == 6) + iaddr = cont; if (nego_info->token == dialogToken && nego_info->state == 0 - && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE - ) { + && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE + ) { + if (iaddr) + _rtw_memcpy(tx ? nego_info->iface_addr : nego_info->peer_iface_addr, iaddr, ETH_ALEN); nego_info->status = (status == -1) ? 0xff : status; nego_info->rsp_op_ch = op_ch; nego_info->rsp_intent = intent; @@ -3905,19 +3973,22 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) } dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); - RTW_INFO("RTW_%s:P2P_GO_NEGO_RESP, dialogToken=%d, intent:%u%s, status:%d, op_ch:%d, ch_list:%s\n", - (tx == _TRUE) ? "Tx" : "Rx", dialogToken, (intent >> 1), intent & 0x1 ? "+" : "-", status, op_ch, ch_list_buf); + RTW_INFO("RTW_%s:P2P_GO_NEGO_RESP, dialogToken=%d, intent:%u%s, status:%d, op_ch:%d, ch_list:%s" + , (tx == _TRUE) ? "Tx" : "Rx", dialogToken, (intent >> 1), intent & 0x1 ? "+" : "-", status, op_ch, ch_list_buf); + if (iaddr) + _RTW_INFO(", iaddr:"MAC_FMT, MAC_ARG(iaddr)); + _RTW_INFO("\n"); if (!tx) { pwdev_priv->provdisc_req_issued = _FALSE; -#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) if (rtw_mi_check_status(padapter, MI_LINKED) && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter)); rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0); } -#endif + #endif } break; @@ -3927,10 +3998,10 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) bool is_go = _FALSE; if (tx) { -#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)); -#endif + #endif } cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len); @@ -3941,7 +4012,7 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) status = *cont; if (nego_info->token == dialogToken && nego_info->state == 1 - && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE + && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE ) { nego_info->status = (status == -1) ? 0xff : status; nego_info->conf_op_ch = (op_ch == -1) ? 0 : op_ch; @@ -3956,8 +4027,8 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) } dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); - RTW_INFO("RTW_%s:P2P_GO_NEGO_CONF, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n", - (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf); + RTW_INFO("RTW_%s:P2P_GO_NEGO_CONF, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n" + , (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf); if (!tx) { } @@ -3969,11 +4040,11 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) int flags = -1; if (tx) { -#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)); -#endif + #endif } cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INVITATION_FLAGS, NULL, &cont_len); @@ -3982,11 +4053,16 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len); if (cont) op_ch = *(cont + 4); + cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_BSSID, NULL, &cont_len); + if (cont && cont_len == 6) + gbssid = cont; if (invit_info->token != dialogToken) rtw_wdev_invit_info_init(invit_info); - _rtw_memcpy(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN); + _rtw_memcpy(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN); + if (gbssid) + _rtw_memcpy(invit_info->group_bssid, gbssid, ETH_ALEN); invit_info->active = tx ? 1 : 0; invit_info->token = dialogToken; invit_info->flags = (flags == -1) ? 0x0 : flags; @@ -3994,11 +4070,14 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) invit_info->state = 0; dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); - RTW_INFO("RTW_%s:P2P_INVIT_REQ, dialogToken=%d, flags:0x%02x, op_ch:%d, ch_list:%s\n", - (tx == _TRUE) ? "Tx" : "Rx", dialogToken, flags, op_ch, ch_list_buf); + RTW_INFO("RTW_%s:P2P_INVIT_REQ, dialogToken=%d, flags:0x%02x, op_ch:%d, ch_list:%s" + , (tx == _TRUE) ? "Tx" : "Rx", dialogToken, flags, op_ch, ch_list_buf); + if (gbssid) + _RTW_INFO(", gbssid:"MAC_FMT, MAC_ARG(gbssid)); + _RTW_INFO("\n"); if (!tx) { -#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { if (op_ch != -1 && rtw_chk_p2pie_op_ch_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) { RTW_INFO(FUNC_ADPT_FMT" op_ch:%u has no intersect with buddy\n", FUNC_ADPT_ARG(padapter), op_ch); @@ -4008,7 +4087,7 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0); } } -#endif + #endif } break; @@ -4017,28 +4096,31 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) struct rtw_wdev_invit_info *invit_info = &pwdev_priv->invit_info; if (tx) { -#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)); -#endif + #endif } cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len); if (cont) { -#ifdef CONFIG_P2P_INVITE_IOT + #ifdef CONFIG_P2P_INVITE_IOT if (tx && *cont == 7) { RTW_INFO("TX_P2P_INVITE_RESP, status is no common channel, change to unknown group\n"); *cont = 8; /* unknow group status */ } -#endif /* CONFIG_P2P_INVITE_IOT */ + #endif /* CONFIG_P2P_INVITE_IOT */ status = *cont; } cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len); if (cont) op_ch = *(cont + 4); + cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_BSSID, NULL, &cont_len); + if (cont && cont_len == 6) + gbssid = cont; if (invit_info->token == dialogToken && invit_info->state == 0 - && _rtw_memcmp(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE + && _rtw_memcmp(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE ) { invit_info->status = (status == -1) ? 0xff : status; invit_info->rsp_op_ch = op_ch; @@ -4047,8 +4129,11 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) } dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); - RTW_INFO("RTW_%s:P2P_INVIT_RESP, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n", - (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf); + RTW_INFO("RTW_%s:P2P_INVIT_RESP, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s" + , (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf); + if (gbssid) + _RTW_INFO(", gbssid:"MAC_FMT, MAC_ARG(gbssid)); + _RTW_INFO("\n"); if (!tx) { } @@ -4080,9 +4165,9 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, NULL, &contentlen)) { pwdev_priv->provdisc_req_issued = _FALSE;/* case: p2p_client join p2p GO */ } else { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("provdisc_req_issued is _TRUE\n"); -#endif /*CONFIG_DEBUG_CFG80211*/ + #endif /*CONFIG_DEBUG_CFG80211*/ pwdev_priv->provdisc_req_issued = _TRUE;/* case: p2p_devices connection before Nego req. */ } @@ -4104,10 +4189,10 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) OUI_Subtype = frame_body[5]; dialogToken = frame_body[6]; -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", cpu_to_be32(*((u32 *)(frame_body + 1))), OUI_Subtype, dialogToken); -#endif + #endif is_p2p_frame = OUI_Subtype; @@ -4141,26 +4226,25 @@ void rtw_init_cfg80211_wifidirect_info(_adapter *padapter) _rtw_memset(pcfg80211_wdinfo, 0x00, sizeof(struct cfg80211_wifidirect_info)); - _init_timer(&pcfg80211_wdinfo->remain_on_ch_timer, padapter->pnetdev, ro_ch_timer_process, padapter); + rtw_init_timer(&pcfg80211_wdinfo->remain_on_ch_timer, padapter, ro_ch_timer_process, padapter); } #endif /* CONFIG_IOCTL_CFG80211 */ -void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType) +s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf) { + int ret = H2C_SUCCESS; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - _func_enter_; - switch (intCmdType) { - case P2P_FIND_PHASE_WK: { + case P2P_FIND_PHASE_WK: find_phase_handler(padapter); break; - } - case P2P_RESTORE_STATE_WK: { + + case P2P_RESTORE_STATE_WK: restore_p2p_state_handler(padapter); break; - } - case P2P_PRE_TX_PROVDISC_PROCESS_WK: { + + case P2P_PRE_TX_PROVDISC_PROCESS_WK: #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED)) p2p_concurrent_handler(padapter); @@ -4170,8 +4254,8 @@ void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType) pre_tx_provdisc_handler(padapter); #endif break; - } - case P2P_PRE_TX_INVITEREQ_PROCESS_WK: { + + case P2P_PRE_TX_INVITEREQ_PROCESS_WK: #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED)) p2p_concurrent_handler(padapter); @@ -4181,8 +4265,8 @@ void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType) pre_tx_invitereq_handler(padapter); #endif break; - } - case P2P_PRE_TX_NEGOREQ_PROCESS_WK: { + + case P2P_PRE_TX_NEGOREQ_PROCESS_WK: #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED)) p2p_concurrent_handler(padapter); @@ -4192,25 +4276,28 @@ void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType) pre_tx_negoreq_handler(padapter); #endif break; - } -#ifdef CONFIG_P2P + #ifdef CONFIG_CONCURRENT_MODE - case P2P_AP_P2P_CH_SWITCH_PROCESS_WK: { + case P2P_AP_P2P_CH_SWITCH_PROCESS_WK: p2p_concurrent_handler(padapter); break; - } -#endif #endif + #ifdef CONFIG_IOCTL_CFG80211 - case P2P_RO_CH_WK: { - ro_ch_handler(padapter); + case P2P_RO_CH_WK: + ret = ro_ch_handler(padapter, buf); break; - } -#endif /* CONFIG_IOCTL_CFG80211 */ + case P2P_CANCEL_RO_CH_WK: + ret = cancel_ro_ch_handler(padapter, buf); + break; +#endif + default: + rtw_warn_on(1); + break; } - _func_exit_; + return ret; } int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength) @@ -4225,7 +4312,6 @@ int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength) struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - _func_enter_; if (IELength <= _BEACON_IE_OFFSET_) return ret; @@ -4246,7 +4332,6 @@ int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength) p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); } - _func_exit_; return ret; } @@ -4264,13 +4349,14 @@ void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength) u8 find_p2p = _FALSE, find_p2p_ps = _FALSE; u8 noa_offset, noa_num, noa_index; - _func_enter_; if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) return; #ifdef CONFIG_CONCURRENT_MODE +#ifndef CONFIG_FW_MULTI_PORT_SUPPORT if (padapter->hw_port != HW_PORT0) return; +#endif #endif if (IELength <= _BEACON_IE_OFFSET_) return; @@ -4341,15 +4427,14 @@ void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength) p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); } - _func_exit_; } void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - - _func_enter_; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u32 ps_deny = 0; /* Pre action for p2p state */ switch (p2p_ps_state) { @@ -4371,6 +4456,16 @@ void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) } break; case P2P_PS_ENABLE: + _enter_pwrlock(&adapter_to_pwrctl(padapter)->lock); + ps_deny = rtw_ps_deny_get(padapter); + _exit_pwrlock(&adapter_to_pwrctl(padapter)->lock); + + if ((ps_deny & (PS_DENY_SCAN | PS_DENY_JOIN)) + || rtw_mi_check_fwstate(padapter, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING))) { + pwdinfo->p2p_ps_mode = P2P_PS_NONE; + RTW_DBG(FUNC_ADPT_FMT" Block P2P PS under site survey or LINKING\n", FUNC_ADPT_ARG(padapter)); + return; + } if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) { #ifdef CONFIG_MCC_MODE if (MCC_EN(padapter)) { @@ -4405,7 +4500,6 @@ void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) break; } - _func_exit_; } u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue) @@ -4416,11 +4510,12 @@ u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue) struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - _func_enter_; if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) #ifdef CONFIG_CONCURRENT_MODE +#ifndef CONFIG_FW_MULTI_PORT_SUPPORT || (padapter->hw_port != HW_PORT0) +#endif #endif ) return res; @@ -4452,7 +4547,6 @@ u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue) exit: - _func_exit_; return res; @@ -4799,13 +4893,13 @@ void rtw_init_wifidirect_timers(_adapter *padapter) { struct wifidirect_info *pwdinfo = &padapter->wdinfo; - _init_timer(&pwdinfo->find_phase_timer, padapter->pnetdev, find_phase_timer_process, padapter); - _init_timer(&pwdinfo->restore_p2p_state_timer, padapter->pnetdev, restore_p2p_state_timer_process, padapter); - _init_timer(&pwdinfo->pre_tx_scan_timer, padapter->pnetdev, pre_tx_scan_timer_process, padapter); - _init_timer(&pwdinfo->reset_ch_sitesurvey, padapter->pnetdev, reset_ch_sitesurvey_timer_process, padapter); - _init_timer(&pwdinfo->reset_ch_sitesurvey2, padapter->pnetdev, reset_ch_sitesurvey_timer_process2, padapter); + rtw_init_timer(&pwdinfo->find_phase_timer, padapter, find_phase_timer_process, padapter); + rtw_init_timer(&pwdinfo->restore_p2p_state_timer, padapter, restore_p2p_state_timer_process, padapter); + rtw_init_timer(&pwdinfo->pre_tx_scan_timer, padapter, pre_tx_scan_timer_process, padapter); + rtw_init_timer(&pwdinfo->reset_ch_sitesurvey, padapter, reset_ch_sitesurvey_timer_process, padapter); + rtw_init_timer(&pwdinfo->reset_ch_sitesurvey2, padapter, reset_ch_sitesurvey_timer_process2, padapter); #ifdef CONFIG_CONCURRENT_MODE - _init_timer(&pwdinfo->ap_p2p_switch_timer, padapter->pnetdev, ap_p2p_switch_timer_process, padapter); + rtw_init_timer(&pwdinfo->ap_p2p_switch_timer, padapter, ap_p2p_switch_timer_process, padapter); #endif } @@ -4839,21 +4933,25 @@ void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role) pwdinfo->social_chan[2] = 11; pwdinfo->social_chan[3] = 0; /* channel 0 for scanning ending in site survey function. */ -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) - union_ch = rtw_mi_get_union_chan(padapter); - - if ((union_ch != 0) && - ((union_ch == 1) || (union_ch == 6) || (union_ch == 11)) - ) { - /* Use the AP's channel as the listen channel */ - /* This will avoid the channel switch between AP's channel and listen channel. */ - pwdinfo->listen_channel = union_ch; - } else -#endif /* CONFIG_CONCURRENT_MODE */ - { - /* Use the channel 11 as the listen channel */ - pwdinfo->listen_channel = 11; + if (role != P2P_ROLE_DISABLE + && pwdinfo->driver_interface != DRIVER_CFG80211 + ) { + #ifdef CONFIG_CONCURRENT_MODE + if (rtw_mi_check_status(padapter, MI_LINKED)) + union_ch = rtw_mi_get_union_chan(padapter); + + if (union_ch != 0 && + (union_ch == 1 || union_ch == 6 || union_ch == 11) + ) { + /* Use the AP's channel as the listen channel */ + /* This will avoid the channel switch between AP's channel and listen channel */ + pwdinfo->listen_channel = union_ch; + } else + #endif /* CONFIG_CONCURRENT_MODE */ + { + /* Use the channel 11 as the listen channel */ + pwdinfo->listen_channel = 11; + } } if (role == P2P_ROLE_DEVICE) { @@ -5125,7 +5223,7 @@ int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role) u8 channel, ch_offset; u16 bwmode; -#ifdef CONFIG_CONCURRENT_MODE +#if defined(CONFIG_CONCURRENT_MODE) && (!defined(RTW_P2P_GROUP_INTERFACE) || !RTW_P2P_GROUP_INTERFACE) /* Commented by Albert 2011/12/30 */ /* The driver just supports 1 P2P group operation. */ /* So, this function will do nothing if the buddy adapter had enabled the P2P function. */ @@ -5145,11 +5243,19 @@ int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role) /* Added by Albert 2011/03/22 */ /* In the P2P mode, the driver should not support the b mode. */ /* So, the Tx packet shouldn't use the CCK rate */ - update_tx_basic_rate(padapter, WIRELESS_11AGN); + #ifdef CONFIG_IOCTL_CFG80211 + if (rtw_cfg80211_iface_has_p2p_group_cap(padapter)) + #endif + update_tx_basic_rate(padapter, WIRELESS_11AGN); /* Enable P2P function */ init_wifidirect_info(padapter, role); + #ifdef CONFIG_IOCTL_CFG80211 + if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) + adapter_wdev_data(padapter)->p2p_enabled = _TRUE; + #endif + rtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _TRUE); #ifdef CONFIG_WFD if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) @@ -5162,11 +5268,12 @@ int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role) return ret; #endif /* CONFIG_INTEL_WIDI */ -#ifdef CONFIG_IOCTL_CFG80211 + #ifdef CONFIG_IOCTL_CFG80211 if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) adapter_wdev_data(padapter)->p2p_enabled = _FALSE; -#endif /* CONFIG_IOCTL_CFG80211 */ + #endif + pwdinfo->listen_channel = 0; /* Disable P2P function */ if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { diff --git a/core/rtw_pwrctrl.c b/core/rtw_pwrctrl.c index 2f3a8ad..eca0e4a 100644 --- a/core/rtw_pwrctrl.c +++ b/core/rtw_pwrctrl.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_PWRCTRL_C_ #include @@ -158,7 +153,7 @@ int ips_leave(_adapter *padapter) _exit_pwrlock(&pwrpriv->lock); if (_SUCCESS == ret) - ODM_DMReset(&GET_HAL_DATA(padapter)->odmpriv); + odm_dm_reset(&GET_HAL_DATA(padapter)->odmpriv); #ifdef CONFIG_BT_COEXIST if (_SUCCESS == ret) @@ -220,7 +215,7 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter) || check_fwstate(pmlmepriv, WIFI_AP_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) - || pcfg80211_wdinfo->is_ro_ch + || rtw_cfg80211_get_is_roch(iface) == _TRUE #elif defined(CONFIG_P2P) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) @@ -393,10 +388,9 @@ void rtw_ps_processor(_adapter *padapter) return; } -void pwr_state_check_handler(RTW_TIMER_HDL_ARGS); -void pwr_state_check_handler(RTW_TIMER_HDL_ARGS) +void pwr_state_check_handler(void *ctx) { - _adapter *padapter = (_adapter *)FunctionContext; + _adapter *padapter = (_adapter *)ctx; rtw_ps_cmd(padapter); } @@ -456,6 +450,61 @@ void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets) #endif /* CONFIG_CHECK_LEAVE_LPS */ } +#ifdef CONFIG_LPS_LCLK +u8 rtw_cpwm_polling(_adapter *adapter, u8 cpwm_orig) +{ + u8 result = _FAIL; + u8 cpwm_now; + u8 poll_cnt = 0; + u32 start_time; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + struct debug_priv *pdbgpriv = &(adapter_to_dvobj(adapter)->drv_dbg); + + /*RTW_INFO("%s.....\n", __func__);*/ + + start_time = rtw_get_current_time(); + + /* polling cpwm */ + do { + rtw_msleep_os(1); + poll_cnt++; + cpwm_now = 0; + rtw_hal_get_hwreg(adapter, HW_VAR_CPWM, &cpwm_now); + + if ((cpwm_orig ^ cpwm_now) & 0x80) { + pwrpriv->cpwm = PS_STATE_S4; + pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE; + #ifdef DBG_CHECK_FW_PS_STATE + RTW_INFO("%s: polling cpwm OK! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x , 0x100=0x%x\n" + , __func__, poll_cnt, cpwm_orig, cpwm_now, rtw_read8(adapter, REG_CR)); + if (rtw_fw_ps_state(adapter) == _FAIL) { + RTW_INFO("leave 32k but fw state in 32k\n"); + pdbgpriv->dbg_rpwm_toogle_cnt++; + } + #endif /* DBG_CHECK_FW_PS_STATE */ + result = _SUCCESS; + break; + } + + if (rtw_get_passing_time_ms(start_time) > LPS_RPWM_WAIT_MS) { + RTW_ERR("%s: polling cpwm timeout! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x\n" + , __func__, poll_cnt, cpwm_orig, cpwm_now); + #ifdef DBG_CHECK_FW_PS_STATE + if (rtw_fw_ps_state(adapter) == _FAIL) { + RTW_INFO("rpwm timeout and fw ps state in 32k\n"); + pdbgpriv->dbg_rpwm_timeout_fail_cnt++; + } + #endif /* DBG_CHECK_FW_PS_STATE */ + + #ifdef CONFIG_LPS_RPWM_TIMER + _set_timer(&pwrpriv->pwr_rpwm_timer, 1); + #endif /* CONFIG_LPS_RPWM_TIMER */ + break; + } + } while (1); + return result; +} +#endif /* * Description: * This function MUST be called under power lock protect @@ -469,12 +518,11 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv) { u8 rpwm; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); -#ifdef CONFIG_DETECT_CPWM_BY_POLLING +#ifdef CONFIG_LPS_LCLK u8 cpwm_orig; -#endif /* CONFIG_DETECT_CPWM_BY_POLLING */ +#endif struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - _func_enter_; pslv = PS_STATE(pslv); @@ -488,36 +536,23 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv) #ifdef CONFIG_LPS_LCLK || ((pwrpriv->rpwm >= PS_STATE_S2) && (pslv >= PS_STATE_S2)) #endif + || (pwrpriv->lps_level == LPS_NORMAL) ) { - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, - ("%s: Already set rpwm[0x%02X], new=0x%02X!\n", __FUNCTION__, pwrpriv->rpwm, pslv)); return; } } if (rtw_is_surprise_removed(padapter) || (!rtw_is_hw_init_completed(padapter))) { - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, - ("%s: SurpriseRemoved(%s) hw_init_completed(%s)\n" - , __func__ - , rtw_is_surprise_removed(padapter) ? "True" : "False" - , rtw_is_hw_init_completed(padapter) ? "True" : "False")); pwrpriv->cpwm = PS_STATE_S4; return; } - if (rtw_is_drv_stopped(padapter)) { - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, - ("%s: change power state(0x%02X) when DriverStopped\n", __FUNCTION__, pslv)); - - if (pslv < PS_STATE_S2) { - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, - ("%s: Reject to enter PS_STATE(0x%02X) lower than S2 when DriverStopped!!\n", __FUNCTION__, pslv)); + if (rtw_is_drv_stopped(padapter)) + if (pslv < PS_STATE_S2) return; - } - } rpwm = pslv | pwrpriv->tog; #ifdef CONFIG_LPS_LCLK @@ -525,12 +560,10 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv) if ((pwrpriv->cpwm < PS_STATE_S2) && (pslv >= PS_STATE_S2)) rpwm |= PS_ACK; #endif - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, - ("rtw_set_rpwm: rpwm=0x%02x cpwm=0x%02x\n", rpwm, pwrpriv->cpwm)); pwrpriv->rpwm = pslv; -#ifdef CONFIG_DETECT_CPWM_BY_POLLING +#ifdef CONFIG_LPS_LCLK cpwm_orig = 0; if (rpwm & PS_ACK) rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig); @@ -548,54 +581,21 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv) /* No LPS 32K, No Ack */ if (rpwm & PS_ACK) { #ifdef CONFIG_DETECT_CPWM_BY_POLLING - u32 start_time; - u8 cpwm_now; - u8 poll_cnt = 0; - - start_time = rtw_get_current_time(); - - /* polling cpwm */ - do { - rtw_msleep_os(1); - poll_cnt++; - cpwm_now = 0; - rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now); - if ((cpwm_orig ^ cpwm_now) & 0x80) { - pwrpriv->cpwm = PS_STATE_S4; - pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE; -#ifdef DBG_CHECK_FW_PS_STATE - RTW_INFO("%s: polling cpwm OK! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x , 0x100=0x%x\n" - , __FUNCTION__, poll_cnt, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR)); - if (rtw_fw_ps_state(padapter) == _FAIL) { - RTW_INFO("leave 32k but fw state in 32k\n"); - pdbgpriv->dbg_rpwm_toogle_cnt++; - } -#endif /* DBG_CHECK_FW_PS_STATE */ - break; - } - - if (rtw_get_passing_time_ms(start_time) > LPS_RPWM_WAIT_MS) { - RTW_INFO("%s: polling cpwm timeout! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x\n", __FUNCTION__, poll_cnt, cpwm_orig, cpwm_now); -#ifdef DBG_CHECK_FW_PS_STATE - if (rtw_fw_ps_state(padapter) == _FAIL) { - RTW_INFO("rpwm timeout and fw ps state in 32k\n"); - pdbgpriv->dbg_rpwm_timeout_fail_cnt++; - } -#endif /* DBG_CHECK_FW_PS_STATE */ -#ifdef CONFIG_LPS_RPWM_TIMER - _set_timer(&pwrpriv->pwr_rpwm_timer, 1); -#endif /* CONFIG_LPS_RPWM_TIMER */ - break; - } - } while (1); -#endif /* CONFIG_DETECT_CPWM_BY_POLLING */ + rtw_cpwm_polling(padapter, cpwm_orig); + #else + #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN) + if (pwrpriv->wowlan_mode == _TRUE || + pwrpriv->wowlan_ap_mode == _TRUE || + pwrpriv->wowlan_p2p_mode == _TRUE) + rtw_cpwm_polling(padapter, cpwm_orig); + #endif /*#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)*/ + #endif /*#ifdef CONFIG_DETECT_CPWM_BY_POLLING*/ } else #endif /* CONFIG_LPS_LCLK */ { pwrpriv->cpwm = pslv; } - _func_exit_; } u8 PS_RDY_CHECK(_adapter *padapter) @@ -634,7 +634,7 @@ u8 PS_RDY_CHECK(_adapter *padapter) || check_fwstate(pmlmepriv, WIFI_AP_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) - || pcfg80211_wdinfo->is_ro_ch + || rtw_cfg80211_get_is_roch(padapter) == _TRUE #endif || rtw_is_scan_deny(padapter) #ifdef CONFIG_TDLS @@ -789,15 +789,13 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode _list *plist, *phead; struct sta_info *ptdls_sta; #endif /* CONFIG_TDLS */ +#ifdef CONFIG_LPS_PG + u8 lps_pg_hdl_id = 0; +#endif - _func_enter_; - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, - ("%s: PowerMode=%d Smart_PS=%d\n", - __FUNCTION__, ps_mode, smart_ps)); if (ps_mode > PM_Card_Disable) { - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, ("ps_mode:%d error\n", ps_mode)); return; } @@ -812,6 +810,21 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode #endif /* !CONFIG_BT_COEXIST */ } +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT + if (PS_MODE_ACTIVE != ps_mode) { + rtw_set_ps_rsvd_page(padapter); + rtw_set_default_port_id(padapter); + } +#endif + +#ifdef CONFIG_LPS_PG + if ((PS_MODE_ACTIVE != ps_mode) && (pwrpriv->blpspg_info_up)) { + /*rtw_hal_set_lps_pg_info(padapter);*/ + lps_pg_hdl_id = LPS_PG_INFO_CFG; + rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id)); + } +#endif + #ifdef CONFIG_LPS_LCLK _enter_pwrlock(&pwrpriv->lock); #endif @@ -882,8 +895,22 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode rtw_usleep_os(100); } while (1); } +#endif +#ifdef CONFIG_LPS_PG + if (pwrpriv->lps_level == LPS_PG) { + lps_pg_hdl_id = LPS_PG_REDLEMEM; + rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id)); + } #endif rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); + +#ifdef CONFIG_LPS_PG + if (pwrpriv->lps_level == LPS_PG) { + lps_pg_hdl_id = LPS_PG_RESEND_H2C; + rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id)); + } +#endif + #ifdef CONFIG_LPS_POFF rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_SET_MODE, (u8 *)(&ps_mode)); @@ -976,7 +1003,6 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode _exit_pwrlock(&pwrpriv->lock); #endif - _func_exit_; } /* @@ -1028,9 +1054,10 @@ void LPS_Enter(PADAPTER padapter, const char *msg) int i; char buf[32] = {0}; - _func_enter_; /* RTW_INFO("+LeisurePSEnter\n"); */ + if (GET_HAL_DATA(padapter)->bFWReady == _FALSE) + return; #ifdef CONFIG_BT_COEXIST if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE) @@ -1045,9 +1072,11 @@ void LPS_Enter(PADAPTER padapter, const char *msg) if (n_assoc_iface != 1) return; +#ifndef CONFIG_FW_MULTI_PORT_SUPPORT /* Skip lps enter request for adapter not port0 */ if (get_hw_port(padapter) != HW_PORT0) return; +#endif for (i = 0; i < dvobj->iface_nums; i++) { if (PS_RDY_CHECK(dvobj->padapters[i]) == _FALSE) @@ -1062,11 +1091,6 @@ void LPS_Enter(PADAPTER padapter, const char *msg) if (pwrpriv->bLeisurePs) { /* Idle for a while if we connect to AP a while ago. */ -#ifdef CONFIG_LPS_PG - if (pwrpriv->LpsIdleCount == 2) - rtw_hal_set_lps_pg_info(padapter); -#endif - if (pwrpriv->LpsIdleCount >= 2) { /* 4 Sec */ if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) { sprintf(buf, "WIFI-%s", msg); @@ -1079,7 +1103,6 @@ void LPS_Enter(PADAPTER padapter, const char *msg) /* RTW_INFO("-LeisurePSEnter\n"); */ - _func_exit_; } /* @@ -1097,7 +1120,6 @@ void LPS_Leave(PADAPTER padapter, const char *msg) char buf[32] = {0}; struct debug_priv *pdbgpriv = &dvobj->drv_dbg; - _func_enter_; /* RTW_INFO("+LeisurePSLeave\n"); */ @@ -1125,7 +1147,20 @@ void LPS_Leave(PADAPTER padapter, const char *msg) #endif /* DBG_CHECK_FW_PS_STATE * RTW_INFO("-LeisurePSLeave\n"); */ - _func_exit_; +} + +void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en) +{ +#if defined(CONFIG_USB_HCI) && defined(CONFIG_LPS_LCLK) + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + + if (wow_en) { + pwrpriv->lps_level_bk = pwrpriv->lps_level; + pwrpriv->lps_level = LPS_LCLK; + } else + pwrpriv->lps_level = pwrpriv->lps_level_bk; +#endif } #endif @@ -1141,7 +1176,6 @@ void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) u32 start_time; #endif /* CONFIG_DETECT_CPWM_BY_POLLING */ - _func_enter_; RTW_INFO("%s.....\n", __FUNCTION__); @@ -1234,7 +1268,6 @@ void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) } } - _func_exit_; } /* @@ -1249,7 +1282,6 @@ void LeaveAllPowerSaveMode(IN PADAPTER Adapter) int n_assoc_iface = 0; int i; - _func_enter_; /* RTW_INFO("%s.....\n",__FUNCTION__); */ @@ -1276,7 +1308,13 @@ void LeaveAllPowerSaveMode(IN PADAPTER Adapter) #endif #ifdef CONFIG_P2P_PS - p2p_ps_wk_cmd(Adapter, P2P_PS_DISABLE, enqueue); + for (i = 0; i < dvobj->iface_nums; i++) { + _adapter *iface = dvobj->padapters[i]; + struct wifidirect_info *pwdinfo = &(iface->wdinfo); + + if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) + p2p_ps_wk_cmd(iface, P2P_PS_DISABLE, enqueue); + } #endif /* CONFIG_P2P_PS */ #ifdef CONFIG_LPS @@ -1308,7 +1346,6 @@ void LeaveAllPowerSaveMode(IN PADAPTER Adapter) } } - _func_exit_; } #ifdef CONFIG_LPS_LCLK @@ -1319,7 +1356,6 @@ void LPS_Leave_check( u32 start_time; u8 bReady; - _func_enter_; pwrpriv = adapter_to_pwrctl(padapter); @@ -1352,7 +1388,6 @@ void LPS_Leave_check( rtw_msleep_os(1); } - _func_exit_; } /* @@ -1368,14 +1403,15 @@ void cpwm_int_hdl( { struct pwrctrl_priv *pwrpriv; - _func_enter_; + if (!padapter) + goto exit; + + if (RTW_CANNOT_RUN(padapter)) + goto exit; pwrpriv = adapter_to_pwrctl(padapter); #if 0 if (pwrpriv->cpwm_tog == (preportpwrstate->state & PS_TOGGLE)) { - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, - ("cpwm_int_hdl: tog(old)=0x%02x cpwm(new)=0x%02x toggle bit didn't change!?\n", - pwrpriv->cpwm_tog, preportpwrstate->state)); goto exit; } #endif @@ -1404,17 +1440,14 @@ void cpwm_int_hdl( _exit_pwrlock(&pwrpriv->lock); exit: - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, - ("cpwm_int_hdl: cpwm=0x%02x\n", pwrpriv->cpwm)); - - _func_exit_; + return; } static void cpwm_event_callback(struct work_struct *work) { struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, cpwm_event); struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); - _adapter *adapter = dvobj->padapters[IFACE_ID0]; + _adapter *adapter = dvobj_get_primary_adapter(dvobj); struct reportpwrstate_parm report; /* RTW_INFO("%s\n",__FUNCTION__); */ @@ -1423,6 +1456,15 @@ static void cpwm_event_callback(struct work_struct *work) cpwm_int_hdl(adapter, &report); } +static void dma_event_callback(struct work_struct *work) +{ + struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, dma_event); + struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); + _adapter *adapter = dvobj_get_primary_adapter(dvobj); + + rtw_unregister_tx_alive(adapter); +} + #ifdef CONFIG_LPS_RPWM_TIMER static void rpwmtimeout_workitem_callback(struct work_struct *work) { @@ -1433,9 +1475,15 @@ static void rpwmtimeout_workitem_callback(struct work_struct *work) pwrpriv = container_of(work, struct pwrctrl_priv, rpwmtimeoutwi); dvobj = pwrctl_to_dvobj(pwrpriv); - padapter = dvobj->padapters[IFACE_ID0]; + padapter = dvobj_get_primary_adapter(dvobj); /* RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); */ + if (!padapter) + return; + + if (RTW_CANNOT_RUN(padapter)) + return; + _enter_pwrlock(&pwrpriv->lock); if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) { RTW_INFO("%s: rpwm=0x%02X cpwm=0x%02X CPWM done!\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); @@ -1482,6 +1530,12 @@ static void pwr_rpwm_timeout_handler(void *FunctionContext) padapter = (PADAPTER)FunctionContext; pwrpriv = adapter_to_pwrctl(padapter); + if (!padapter) + return; + + if (RTW_CANNOT_RUN(padapter)) + return; + RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) { @@ -1525,7 +1579,6 @@ s32 rtw_register_task_alive(PADAPTER padapter, u32 task) struct pwrctrl_priv *pwrctrl; u8 pslv; - _func_enter_; res = _SUCCESS; pwrctrl = adapter_to_pwrctl(padapter); @@ -1536,9 +1589,6 @@ s32 rtw_register_task_alive(PADAPTER padapter, u32 task) register_task_alive(pwrctrl, task); if (pwrctrl->bFwCurrentInPSMode == _TRUE) { - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, - ("%s: task=0x%x cpwm=0x%02x alives=0x%08x\n", - __FUNCTION__, task, pwrctrl->cpwm, pwrctrl->alives)); if (pwrctrl->cpwm < pslv) { if (pwrctrl->cpwm < PS_STATE_S2) @@ -1557,7 +1607,6 @@ s32 rtw_register_task_alive(PADAPTER padapter, u32 task) } #endif /* CONFIG_DETECT_CPWM_BY_POLLING */ - _func_exit_; return res; } @@ -1577,7 +1626,6 @@ void rtw_unregister_task_alive(PADAPTER padapter, u32 task) struct pwrctrl_priv *pwrctrl; u8 pslv; - _func_enter_; pwrctrl = adapter_to_pwrctl(padapter); pslv = PS_STATE_S0; @@ -1600,9 +1648,6 @@ void rtw_unregister_task_alive(PADAPTER padapter, u32 task) if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) && (pwrctrl->bFwCurrentInPSMode == _TRUE)) { - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, - ("%s: cpwm=0x%02x alives=0x%08x\n", - __FUNCTION__, pwrctrl->cpwm, pwrctrl->alives)); if (pwrctrl->cpwm > pslv) { if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0)) @@ -1612,7 +1657,6 @@ void rtw_unregister_task_alive(PADAPTER padapter, u32 task) _exit_pwrlock(&pwrctrl->lock); - _func_exit_; } /* @@ -1634,7 +1678,6 @@ s32 rtw_register_tx_alive(PADAPTER padapter) struct pwrctrl_priv *pwrctrl; u8 pslv; - _func_enter_; res = _SUCCESS; pwrctrl = adapter_to_pwrctl(padapter); @@ -1645,9 +1688,6 @@ s32 rtw_register_tx_alive(PADAPTER padapter) register_task_alive(pwrctrl, XMIT_ALIVE); if (pwrctrl->bFwCurrentInPSMode == _TRUE) { - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, - ("rtw_register_tx_alive: cpwm=0x%02x alives=0x%08x\n", - pwrctrl->cpwm, pwrctrl->alives)); if (pwrctrl->cpwm < pslv) { if (pwrctrl->cpwm < PS_STATE_S2) @@ -1666,7 +1706,6 @@ s32 rtw_register_tx_alive(PADAPTER padapter) } #endif /* CONFIG_DETECT_CPWM_BY_POLLING */ - _func_exit_; return res; } @@ -1690,7 +1729,6 @@ s32 rtw_register_cmd_alive(PADAPTER padapter) struct pwrctrl_priv *pwrctrl; u8 pslv; - _func_enter_; res = _SUCCESS; pwrctrl = adapter_to_pwrctl(padapter); @@ -1701,9 +1739,6 @@ s32 rtw_register_cmd_alive(PADAPTER padapter) register_task_alive(pwrctrl, CMD_ALIVE); if (pwrctrl->bFwCurrentInPSMode == _TRUE) { - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_info_, - ("rtw_register_cmd_alive: cpwm=0x%02x alives=0x%08x\n", - pwrctrl->cpwm, pwrctrl->alives)); if (pwrctrl->cpwm < pslv) { if (pwrctrl->cpwm < PS_STATE_S2) @@ -1722,7 +1757,6 @@ s32 rtw_register_cmd_alive(PADAPTER padapter) } #endif /* CONFIG_DETECT_CPWM_BY_POLLING */ - _func_exit_; return res; } @@ -1740,20 +1774,15 @@ s32 rtw_register_rx_alive(PADAPTER padapter) { struct pwrctrl_priv *pwrctrl; - _func_enter_; pwrctrl = adapter_to_pwrctl(padapter); _enter_pwrlock(&pwrctrl->lock); register_task_alive(pwrctrl, RECV_ALIVE); - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, - ("rtw_register_rx_alive: cpwm=0x%02x alives=0x%08x\n", - pwrctrl->cpwm, pwrctrl->alives)); _exit_pwrlock(&pwrctrl->lock); - _func_exit_; return _SUCCESS; } @@ -1771,20 +1800,15 @@ s32 rtw_register_evt_alive(PADAPTER padapter) { struct pwrctrl_priv *pwrctrl; - _func_enter_; pwrctrl = adapter_to_pwrctl(padapter); _enter_pwrlock(&pwrctrl->lock); register_task_alive(pwrctrl, EVT_ALIVE); - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, - ("rtw_register_evt_alive: cpwm=0x%02x alives=0x%08x\n", - pwrctrl->cpwm, pwrctrl->alives)); _exit_pwrlock(&pwrctrl->lock); - _func_exit_; return _SUCCESS; } @@ -1803,7 +1827,6 @@ void rtw_unregister_tx_alive(PADAPTER padapter) struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); u8 pslv, i; - _func_enter_; pwrctrl = adapter_to_pwrctl(padapter); pslv = PS_STATE_S0; @@ -1837,9 +1860,6 @@ void rtw_unregister_tx_alive(PADAPTER padapter) if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) && (pwrctrl->bFwCurrentInPSMode == _TRUE)) { - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, - ("%s: cpwm=0x%02x alives=0x%08x\n", - __FUNCTION__, pwrctrl->cpwm, pwrctrl->alives)); if (pwrctrl->cpwm > pslv) { if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0)) @@ -1849,7 +1869,6 @@ void rtw_unregister_tx_alive(PADAPTER padapter) _exit_pwrlock(&pwrctrl->lock); - _func_exit_; } /* @@ -1866,7 +1885,6 @@ void rtw_unregister_cmd_alive(PADAPTER padapter) struct pwrctrl_priv *pwrctrl; u8 pslv, i; - _func_enter_; pwrctrl = adapter_to_pwrctl(padapter); pslv = PS_STATE_S0; @@ -1901,9 +1919,6 @@ void rtw_unregister_cmd_alive(PADAPTER padapter) if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) && (pwrctrl->bFwCurrentInPSMode == _TRUE)) { - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_info_, - ("%s: cpwm=0x%02x alives=0x%08x\n", - __FUNCTION__, pwrctrl->cpwm, pwrctrl->alives)); if (pwrctrl->cpwm > pslv) { if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0)) @@ -1913,7 +1928,6 @@ void rtw_unregister_cmd_alive(PADAPTER padapter) _exit_pwrlock(&pwrctrl->lock); - _func_exit_; } /* @@ -1923,7 +1937,6 @@ void rtw_unregister_rx_alive(PADAPTER padapter) { struct pwrctrl_priv *pwrctrl; - _func_enter_; pwrctrl = adapter_to_pwrctl(padapter); @@ -1931,32 +1944,23 @@ void rtw_unregister_rx_alive(PADAPTER padapter) unregister_task_alive(pwrctrl, RECV_ALIVE); - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, - ("rtw_unregister_rx_alive: cpwm=0x%02x alives=0x%08x\n", - pwrctrl->cpwm, pwrctrl->alives)); _exit_pwrlock(&pwrctrl->lock); - _func_exit_; } void rtw_unregister_evt_alive(PADAPTER padapter) { struct pwrctrl_priv *pwrctrl; - _func_enter_; pwrctrl = adapter_to_pwrctl(padapter); unregister_task_alive(pwrctrl, EVT_ALIVE); - RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, - ("rtw_unregister_evt_alive: cpwm=0x%02x alives=0x%08x\n", - pwrctrl->cpwm, pwrctrl->alives)); _exit_pwrlock(&pwrctrl->lock); - _func_exit_; } #endif /* CONFIG_LPS_LCLK */ @@ -1967,7 +1971,7 @@ void rtw_unregister_evt_alive(PADAPTER padapter) void rtw_init_pwrctrl_priv(PADAPTER padapter) { struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - int i = 0; + u8 val8 = 0; #if defined(CONFIG_CONCURRENT_MODE) @@ -1975,7 +1979,6 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) return; #endif - _func_enter_; #ifdef PLATFORM_WINDOWS pwrctrlpriv->pnp_current_pwr_state = NdisDeviceStateD0; @@ -1992,6 +1995,7 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode; pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode; + pwrctrlpriv->lps_level = padapter->registrypriv.lps_level; pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL; pwrctrlpriv->pwr_state_check_cnts = 0; @@ -2006,6 +2010,11 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) #endif pwrctrlpriv->LpsIdleCount = 0; + +#ifdef CONFIG_LPS_PG + pwrctrlpriv->lpspg_rsvd_page_locate = 0; +#endif + /* pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt; */ /* PS_MODE_MIN; */ if (padapter->registrypriv.mp_mode == 1) pwrctrlpriv->power_mgnt = PS_MODE_ACTIVE ; @@ -2030,18 +2039,22 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) _init_workitem(&pwrctrlpriv->cpwm_event, cpwm_event_callback, NULL); + _init_workitem(&pwrctrlpriv->dma_event, dma_event_callback, NULL); + #ifdef CONFIG_LPS_RPWM_TIMER pwrctrlpriv->brpwmtimeout = _FALSE; _init_workitem(&pwrctrlpriv->rpwmtimeoutwi, rpwmtimeout_workitem_callback, NULL); - _init_timer(&pwrctrlpriv->pwr_rpwm_timer, padapter->pnetdev, pwr_rpwm_timeout_handler, padapter); + rtw_init_timer(&pwrctrlpriv->pwr_rpwm_timer, padapter, pwr_rpwm_timeout_handler, padapter); #endif /* CONFIG_LPS_RPWM_TIMER */ #endif /* CONFIG_LPS_LCLK */ - rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler); + rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler, padapter); pwrctrlpriv->wowlan_mode = _FALSE; pwrctrlpriv->wowlan_ap_mode = _FALSE; pwrctrlpriv->wowlan_p2p_mode = _FALSE; + pwrctrlpriv->wowlan_in_resume = _FALSE; + pwrctrlpriv->wowlan_last_wake_reason = 0; #ifdef CONFIG_RESUME_IN_WORKQUEUE _init_workitem(&pwrctrlpriv->resume_work, resume_workitem_callback, NULL); @@ -2064,30 +2077,23 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) #endif /* CONFIG_GPIO_WAKEUP */ #ifdef CONFIG_WOWLAN - pwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM; - - for (i = 0 ; i < MAX_WKFM_NUM; i++) { - _rtw_memset(pwrctrlpriv->patterns[i].content, '\0', - sizeof(pwrctrlpriv->patterns[i].content)); - _rtw_memset(pwrctrlpriv->patterns[i].mask, '\0', - sizeof(pwrctrlpriv->patterns[i].mask)); - pwrctrlpriv->patterns[i].len = 0; - } - + rtw_wow_pattern_sw_reset(padapter); #ifdef CONFIG_PNO_SUPPORT pwrctrlpriv->pno_inited = _FALSE; pwrctrlpriv->pnlo_info = NULL; pwrctrlpriv->pscan_info = NULL; pwrctrlpriv->pno_ssid_list = NULL; - pwrctrlpriv->pno_in_resume = _TRUE; #endif /* CONFIG_PNO_SUPPORT */ +#ifdef CONFIG_WOW_PATTERN_HW_CAM + _rtw_mutex_init(&pwrctrlpriv->wowlan_pattern_cam_mutex); +#endif + pwrctrlpriv->wowlan_aoac_rpt_loc = 0; #endif /* CONFIG_WOWLAN */ #ifdef CONFIG_LPS_POFF rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_INIT, 0); #endif - _func_exit_; } @@ -2101,7 +2107,6 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter) return; #endif - _func_enter_; /* _rtw_memset((unsigned char *)pwrctrlpriv, 0, sizeof(struct pwrctrl_priv)); */ @@ -2128,6 +2133,10 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter) if (pwrctrlpriv->pno_ssid_list != NULL) printk("****** pno_ssid_list memory leak********\n"); #endif +#ifdef CONFIG_WOW_PATTERN_HW_CAM + _rtw_mutex_free(&pwrctrlpriv->wowlan_pattern_cam_mutex); +#endif + #endif /* CONFIG_WOWLAN */ #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) @@ -2137,7 +2146,6 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter) _free_pwrlock(&pwrctrlpriv->lock); _free_pwrlock(&pwrctrlpriv->check_32k_lock); - _func_exit_; } #ifdef CONFIG_RESUME_IN_WORKQUEUE @@ -2147,7 +2155,7 @@ static void resume_workitem_callback(struct work_struct *work) { struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, resume_work); struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); - _adapter *adapter = dvobj->padapters[IFACE_ID0]; + _adapter *adapter = dvobj_get_primary_adapter(dvobj); RTW_INFO("%s\n", __FUNCTION__); @@ -2202,7 +2210,7 @@ static void rtw_late_resume(struct early_suspend *h) { struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); - _adapter *adapter = dvobj->padapters[IFACE_ID0]; + _adapter *adapter = dvobj_get_primary_adapter(dvobj); RTW_INFO("%s\n", __FUNCTION__); @@ -2255,7 +2263,7 @@ static void rtw_late_resume(android_early_suspend_t *h) { struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); - _adapter *adapter = dvobj->padapters[IFACE_ID0]; + _adapter *adapter = dvobj_get_primary_adapter(dvobj); RTW_INFO("%s\n", __FUNCTION__); if (pwrpriv->do_late_resume) { @@ -2473,6 +2481,19 @@ int rtw_pm_set_lps(_adapter *padapter, u8 mode) return ret; } +int rtw_pm_set_lps_level(_adapter *padapter, u8 level) +{ + int ret = 0; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if (level < LPS_LEVEL_MAX) + pwrctrlpriv->lps_level = level; + else + ret = -EINVAL; + + return ret; +} + int rtw_pm_set_ips(_adapter *padapter, u8 mode) { struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); diff --git a/core/rtw_recv.c b/core/rtw_recv.c index 2e46bfe..69c7a3c 100644 --- a/core/rtw_recv.c +++ b/core/rtw_recv.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_RECV_C_ #include @@ -30,7 +25,7 @@ #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS -void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS); +static void rtw_signal_stat_timer_hdl(void *ctx); enum { SIGNAL_STAT_CALC_PROFILE_0 = 0, @@ -53,7 +48,6 @@ void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv) { - _func_enter_; _rtw_memset((u8 *)psta_recvpriv, 0, sizeof(struct sta_recv_priv)); @@ -64,7 +58,6 @@ void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv) _rtw_init_queue(&psta_recvpriv->defrag_q); - _func_exit_; } @@ -75,13 +68,17 @@ sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter) union recv_frame *precvframe; sint res = _SUCCESS; - _func_enter_; /* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */ /* _rtw_memset((unsigned char *)precvpriv, 0, sizeof (struct recv_priv)); */ _rtw_spinlock_init(&precvpriv->lock); +#ifdef CONFIG_RECV_THREAD_MODE + _rtw_init_sema(&precvpriv->recv_sema, 0); + +#endif + _rtw_init_queue(&precvpriv->free_recv_queue); _rtw_init_queue(&precvpriv->recv_pending_queue); _rtw_init_queue(&precvpriv->uc_swdec_pending_queue); @@ -142,7 +139,7 @@ sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter) res = rtw_hal_init_recv_priv(padapter); #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - rtw_init_timer(&precvpriv->signal_stat_timer, padapter, RTW_TIMER_HDL_NAME(signal_stat)); + rtw_init_timer(&precvpriv->signal_stat_timer, padapter, rtw_signal_stat_timer_hdl, padapter); precvpriv->signal_stat_sampling_interval = 2000; /* ms */ /* precvpriv->signal_stat_converging_constant = 5000; */ /* ms */ @@ -152,7 +149,6 @@ sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter) exit: - _func_exit_; return res; @@ -164,7 +160,6 @@ void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv) _rtw_spinlock_free(&precvpriv->lock); #ifdef CONFIG_RECV_THREAD_MODE _rtw_free_sema(&precvpriv->recv_sema); - _rtw_free_sema(&precvpriv->terminate_recvthread_sema); #endif _rtw_spinlock_free(&precvpriv->free_recv_queue.lock); @@ -181,7 +176,6 @@ void _rtw_free_recv_priv(struct recv_priv *precvpriv) { _adapter *padapter = precvpriv->adapter; - _func_enter_; rtw_free_uc_swdec_pending_queue(padapter); @@ -194,7 +188,6 @@ void _rtw_free_recv_priv(struct recv_priv *precvpriv) rtw_hal_free_recv_priv(padapter); - _func_exit_; } @@ -218,7 +211,6 @@ union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue) _list *plist, *phead; _adapter *padapter; struct recv_priv *precvpriv; - _func_enter_; if (_rtw_queue_empty(pfree_recv_queue) == _TRUE) precvframe = NULL; @@ -238,7 +230,6 @@ union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue) } } - _func_exit_; return precvframe; @@ -272,7 +263,6 @@ int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue) _adapter *padapter = precvframe->u.hdr.adapter; struct recv_priv *precvpriv = &padapter->recvpriv; - _func_enter_; #ifdef CONFIG_CONCURRENT_MODE padapter = GET_PRIMARY_ADAPTER(padapter); @@ -300,7 +290,6 @@ int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue) _exit_critical_bh(&pfree_recv_queue->lock, &irqL); - _func_exit_; return _SUCCESS; @@ -315,7 +304,6 @@ sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) _adapter *padapter = precvframe->u.hdr.adapter; struct recv_priv *precvpriv = &padapter->recvpriv; - _func_enter_; /* _rtw_init_listhead(&(precvframe->u.hdr.list)); */ rtw_list_delete(&(precvframe->u.hdr.list)); @@ -328,7 +316,6 @@ sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) precvpriv->free_recvframe_cnt++; } - _func_exit_; return _SUCCESS; } @@ -370,7 +357,6 @@ void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue) union recv_frame *precvframe; _list *plist, *phead; - _func_enter_; _rtw_spinlock(&pframequeue->lock); phead = get_list_head(pframequeue); @@ -388,7 +374,6 @@ void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue) _rtw_spinunlock(&pframequeue->lock); - _func_exit_; } @@ -495,14 +480,10 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe) struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - _func_enter_; stainfo = rtw_get_stainfo(&adapter->stapriv , &prxattrib->ta[0]); if (prxattrib->encrypt == _TKIP_) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n recvframe_chkmic:prxattrib->encrypt ==_TKIP_\n")); - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n recvframe_chkmic:da=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", - prxattrib->ra[0], prxattrib->ra[1], prxattrib->ra[2], prxattrib->ra[3], prxattrib->ra[4], prxattrib->ra[5])); /* calculate mic code */ if (stainfo != NULL) { @@ -512,26 +493,22 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe) /* rxdata_key_idx =( ((iv[3])>>6)&0x3) ; */ mickey = &psecuritypriv->dot118021XGrprxmickey[prxattrib->key_index].skey[0]; - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n recvframe_chkmic: bcmc key\n")); /* RTW_INFO("\n recvframe_chkmic: bcmc key psecuritypriv->dot118021XGrpKeyid(%d),pmlmeinfo->key_index(%d) ,recv key_id(%d)\n", */ /* psecuritypriv->dot118021XGrpKeyid,pmlmeinfo->key_index,rxdata_key_idx); */ if (psecuritypriv->binstallGrpkey == _FALSE) { res = _FAIL; - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n")); RTW_INFO("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n"); goto exit; } } else { mickey = &stainfo->dot11tkiprxmickey.skey[0]; - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n recvframe_chkmic: unicast key\n")); } datalen = precvframe->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len - prxattrib->icv_len - 8; /* icv_len included the mic code */ pframe = precvframe->u.hdr.rx_data; payload = pframe + prxattrib->hdrlen + prxattrib->iv_len; - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n prxattrib->iv_len=%d prxattrib->icv_len=%d\n", prxattrib->iv_len, prxattrib->icv_len)); /* rtw_seccalctkipmic(&stainfo->dot11tkiprxmickey.skey[0],pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); */ /* care the length of the data */ @@ -543,7 +520,6 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe) for (i = 0; i < 8; i++) { if (miccode[i] != *(pframemic + i)) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("recvframe_chkmic:miccode[%d](%02x) != *(pframemic+%d)(%02x) ", i, miccode[i], i, *(pframemic + i))); bmic_err = _TRUE; } } @@ -551,28 +527,7 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe) if (bmic_err == _TRUE) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n *(pframemic-8)-*(pframemic-1)=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", - *(pframemic - 8), *(pframemic - 7), *(pframemic - 6), *(pframemic - 5), *(pframemic - 4), *(pframemic - 3), *(pframemic - 2), *(pframemic - 1))); - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n *(pframemic-16)-*(pframemic-9)=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", - *(pframemic - 16), *(pframemic - 15), *(pframemic - 14), *(pframemic - 13), *(pframemic - 12), *(pframemic - 11), *(pframemic - 10), *(pframemic - 9))); - - { - uint i; - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n ======demp packet (len=%d)======\n", precvframe->u.hdr.len)); - for (i = 0; i < precvframe->u.hdr.len; i = i + 8) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x", - *(precvframe->u.hdr.rx_data + i), *(precvframe->u.hdr.rx_data + i + 1), - *(precvframe->u.hdr.rx_data + i + 2), *(precvframe->u.hdr.rx_data + i + 3), - *(precvframe->u.hdr.rx_data + i + 4), *(precvframe->u.hdr.rx_data + i + 5), - *(precvframe->u.hdr.rx_data + i + 6), *(precvframe->u.hdr.rx_data + i + 7))); - } - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n ======demp packet end [len=%d]======\n", precvframe->u.hdr.len)); - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n hrdlen=%d,\n", prxattrib->hdrlen)); - } - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("ra=0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x psecuritypriv->binstallGrpkey=%d ", - prxattrib->ra[0], prxattrib->ra[1], prxattrib->ra[2], - prxattrib->ra[3], prxattrib->ra[4], prxattrib->ra[5], psecuritypriv->binstallGrpkey)); /* double check key_index for some timing issue , */ /* cannot compare with psecuritypriv->dot118021XGrpKeyid also cause timing issue */ @@ -581,10 +536,8 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe) if ((prxattrib->bdecrypted == _TRUE) && (brpt_micerror == _TRUE)) { rtw_handle_tkip_mic_err(adapter, stainfo, (u8)IS_MCAST(prxattrib->ra)); - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" mic error :prxattrib->bdecrypted=%d ", prxattrib->bdecrypted)); RTW_INFO(" mic error :prxattrib->bdecrypted=%d\n", prxattrib->bdecrypted); } else { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" mic error :prxattrib->bdecrypted=%d ", prxattrib->bdecrypted)); RTW_INFO(" mic error :prxattrib->bdecrypted=%d\n", prxattrib->bdecrypted); } @@ -594,12 +547,10 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe) /* mic checked ok */ if ((psecuritypriv->bcheck_grpkey == _FALSE) && (IS_MCAST(prxattrib->ra) == _TRUE)) { psecuritypriv->bcheck_grpkey = _TRUE; - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("psecuritypriv->bcheck_grpkey =_TRUE")); } } - } else - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("recvframe_chkmic: rtw_get_stainfo==NULL!!!\n")); + } recvframe_pull_tail(precvframe, 8); @@ -607,7 +558,6 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe) exit: - _func_exit_; return res; @@ -625,11 +575,9 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) union recv_frame *return_packet = precv_frame; u32 res = _SUCCESS; - _func_enter_; DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt); - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("prxstat->decrypted=%x prxattrib->encrypt = 0x%03x\n", prxattrib->bdecrypted, prxattrib->encrypt)); if (prxattrib->encrypt > 0) { u8 *iv = precv_frame->u.hdr.rx_data + prxattrib->hdrlen; @@ -704,7 +652,6 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) if ((prxstat->icv == 1) && (prxattrib->encrypt != _AES_)) { psecuritypriv->hw_decrypted = _FALSE; - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("psecuritypriv->hw_decrypted=_FALSE")); rtw_free_recvframe(precv_frame, &padapter->recvpriv.free_recv_queue); @@ -745,7 +692,6 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) prxattrib->bdecrypted = _TRUE; /* recvframe_chkmic(adapter, precv_frame); */ /* move to recvframme_defrag function */ - _func_exit_; return return_packet; @@ -765,7 +711,6 @@ union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame) u16 eapol_type = 0x888e;/* for Funia BD's WPA issue */ struct rx_pkt_attrib *pattrib; - _func_enter_; pstapriv = &adapter->stapriv; @@ -780,13 +725,11 @@ union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame) psta = rtw_get_stainfo(pstapriv, psta_addr); - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("########portctrl:adapter->securitypriv.dot11AuthAlgrthm=%d\n", adapter->securitypriv.dot11AuthAlgrthm)); if (auth_alg == dot11AuthAlgrthm_8021X) { if ((psta != NULL) && (psta->ieee8021x_blocked)) { /* blocked */ /* only accept EAPOL frame */ - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("########portctrl:psta->ieee8021x_blocked==1\n")); prtnframe = precv_frame; @@ -805,28 +748,19 @@ union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame) } else { /* allowed */ /* check decryption status, and decrypt the frame if needed */ - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("########portctrl:psta->ieee8021x_blocked==0\n")); - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("portctrl:precv_frame->hdr.attrib.privacy=%x\n", precv_frame->u.hdr.attrib.privacy)); - if (pattrib->bdecrypted == 0) - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("portctrl:prxstat->decrypted=%x\n", pattrib->bdecrypted)); prtnframe = precv_frame; /* check is the EAPOL frame or not (Rekey) */ /* if(ether_type == eapol_type){ */ - /* RT_TRACE(_module_rtl871x_recv_c_,_drv_notice_,("########portctrl:ether_type == 0x888e\n")); */ /* check Rekey */ /* prtnframe=precv_frame; */ /* } */ - /* else{ */ - /* RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:ether_type=0x%04x\n", ether_type)); */ - /* } */ } } else prtnframe = precv_frame; - _func_exit_; return prtnframe; @@ -840,17 +774,19 @@ sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcac u16 seq_ctrl = ((precv_frame->u.hdr.attrib.seq_num & 0xffff) << 4) | (precv_frame->u.hdr.attrib.frag_num & 0xf); - _func_enter_; if (tid > 15) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_decache, (tid>15)! seq_ctrl=0x%x, tid=0x%x\n", seq_ctrl, tid)); return _FAIL; } if (1) { /* if(bretry) */ if (seq_ctrl == prxcache->tid_rxseq[tid]) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_decache, seq_ctrl=0x%x, tid=0x%x, tid_rxseq=0x%x\n", seq_ctrl, tid, prxcache->tid_rxseq[tid])); + /* for non-AMPDU case */ + precv_frame->u.hdr.psta->sta_stats.duplicate_cnt++; + + if (precv_frame->u.hdr.psta->sta_stats.duplicate_cnt % 100 == 0) + RTW_INFO("%s: seq=%d\n", __func__, precv_frame->u.hdr.attrib.seq_num); return _FAIL; } @@ -858,7 +794,6 @@ sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcac prxcache->tid_rxseq[tid] = seq_ctrl; - _func_exit_; return _SUCCESS; @@ -1098,6 +1033,7 @@ void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_in pstats->rx_data_pkts++; pstats->rx_bytes += sz; + pstats->rxratecnt[pattrib->data_rate]++; /*record rx packets for every tid*/ pstats->rx_data_qos_pkts[pattrib->priority]++; @@ -1152,7 +1088,6 @@ sint sta2sta_data_frame( u8 *pframe_body = psnap_type + 2 + 1; #endif - _func_enter_; /* RTW_INFO("[%s] %d, seqnum:%d\n", __FUNCTION__, __LINE__, pattrib->seq_num); */ @@ -1161,7 +1096,6 @@ sint sta2sta_data_frame( /* filter packets that SA is myself or multicast or broadcast */ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" SA==myself\n")); ret = _FAIL; goto exit; } @@ -1223,7 +1157,7 @@ sint sta2sta_data_frame( process_pwrbit_data(adapter, precv_frame); /* if NULL-frame, check pwrbit */ - if ((GetFrameSubType(ptr) & WIFI_DATA_NULL) == WIFI_DATA_NULL) { + if ((get_frame_sub_type(ptr) & WIFI_DATA_NULL) == WIFI_DATA_NULL) { /* NULL-frame with pwrbit=1, buffer_STA should buffer frames for sleep_STA */ if (GetPwrMgt(ptr)) { /* it would be triggered when we are off channel and receiving NULL DATA */ @@ -1245,7 +1179,7 @@ sint sta2sta_data_frame( goto exit; } - if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) + if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) process_wmmps_data(adapter, precv_frame); ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE); @@ -1259,7 +1193,6 @@ sint sta2sta_data_frame( { /* For Station mode, sa and bssid should always be BSSID, and DA is my mac-address */ if (!_rtw_memcmp(pattrib->bssid, pattrib->src, ETH_ALEN)) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("bssid != TA under STATION_MODE; drop pkt\n")); ret = _FAIL; goto exit; } @@ -1286,7 +1219,7 @@ sint sta2sta_data_frame( } else if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) { _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN); _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); @@ -1308,7 +1241,6 @@ sint sta2sta_data_frame( #endif /* CONFIG_TDLS */ if (*psta == NULL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("can't get psta under sta2sta_data_frame ; drop pkt\n")); #ifdef CONFIG_MP_INCLUDED if (adapter->registrypriv.mp_mode == 1) { if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) @@ -1320,7 +1252,6 @@ sint sta2sta_data_frame( } exit: - _func_exit_; return ret; } @@ -1343,7 +1274,6 @@ sint ap2sta_data_frame( u8 *myhwaddr = adapter_mac_addr(adapter); sint bmcast = IS_MCAST(pattrib->dst); - _func_enter_; if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE @@ -1352,7 +1282,6 @@ sint ap2sta_data_frame( /* filter packets that SA is myself or multicast or broadcast */ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" SA==myself\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s SA="MAC_FMT", myhwaddr="MAC_FMT"\n", __FUNCTION__, MAC_ARG(pattrib->src), MAC_ARG(myhwaddr)); @@ -1363,8 +1292,6 @@ sint ap2sta_data_frame( /* da should be for me */ if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, - (" ap2sta_data_frame: compare DA fail; DA="MAC_FMT"\n", MAC_ARG(pattrib->dst))); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s DA="MAC_FMT"\n", __func__, MAC_ARG(pattrib->dst)); #endif @@ -1377,9 +1304,6 @@ sint ap2sta_data_frame( if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, - (" ap2sta_data_frame: compare BSSID fail ; BSSID="MAC_FMT"\n", MAC_ARG(pattrib->bssid))); - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("mybssid="MAC_FMT"\n", MAC_ARG(mybssid))); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s BSSID="MAC_FMT", mybssid="MAC_FMT"\n", __func__, MAC_ARG(pattrib->bssid), MAC_ARG(mybssid)); @@ -1400,7 +1324,6 @@ sint ap2sta_data_frame( *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get ap_info */ if (*psta == NULL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("ap2sta: can't get psta under STATION_MODE ; drop pkt\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s can't get psta under STATION_MODE ; drop pkt\n", __FUNCTION__); #endif @@ -1408,10 +1331,11 @@ sint ap2sta_data_frame( goto exit; } - if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) { + /*if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) { } + */ - if (GetFrameSubType(ptr) & BIT(6)) { + if (get_frame_sub_type(ptr) & BIT(6)) { /* No data, will not indicate to upper layer, temporily count it here */ count_rx_stats(adapter, precv_frame, *psta); ret = RTW_RX_HANDLED; @@ -1421,19 +1345,14 @@ sint ap2sta_data_frame( } else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN); _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); - /* */ - if (adapter->mppriv.bRTWSmbCfg == _FALSE) - _rtw_memcpy(pattrib->bssid, mybssid, ETH_ALEN); - *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */ if (*psta == NULL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("can't get psta under MP_MODE ; drop pkt\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__); #endif @@ -1474,7 +1393,6 @@ sint ap2sta_data_frame( exit: - _func_exit_; return ret; @@ -1496,7 +1414,6 @@ sint sta2ap_data_frame( unsigned char *mybssid = get_bssid(pmlmepriv); sint ret = _SUCCESS; - _func_enter_; if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { /* For AP mode, RA=BSSID, TX=STA(SRC_ADDR), A3=DST_ADDR */ @@ -1507,15 +1424,14 @@ sint sta2ap_data_frame( *psta = rtw_get_stainfo(pstapriv, pattrib->src); if (*psta == NULL) { -#ifdef CONFIG_DFS_MASTER + #ifdef CONFIG_DFS_MASTER struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); /* prevent RX tasklet blocks cmd_thread */ if (rfctl->radar_detected == 1) goto bypass_deauth7; -#endif + #endif - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("can't get psta under AP_MODE; drop pkt\n")); RTW_INFO("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src)); issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); @@ -1529,10 +1445,10 @@ sint sta2ap_data_frame( process_pwrbit_data(adapter, precv_frame); - if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) + if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) process_wmmps_data(adapter, precv_frame); - if (GetFrameSubType(ptr) & BIT(6)) { + if (get_frame_sub_type(ptr) & BIT(6)) { /* No data, will not indicate to upper layer, temporily count it here */ count_rx_stats(adapter, precv_frame, *psta); ret = RTW_RX_HANDLED; @@ -1542,17 +1458,14 @@ sint sta2ap_data_frame( (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { /* RTW_INFO("%s ,in WIFI_MP_STATE\n",__func__); */ _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN); _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); - /* */ - if (adapter->mppriv.bRTWSmbCfg == _FALSE) - _rtw_memcpy(pattrib->bssid, mybssid, ETH_ALEN); + *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */ if (*psta == NULL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("can't get psta under MP_MODE ; drop pkt\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__); #endif @@ -1574,7 +1487,6 @@ sint sta2ap_data_frame( exit: - _func_exit_; return ret; @@ -1598,7 +1510,7 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN)) return _FAIL; - psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); if (psta == NULL) return _FAIL; @@ -1606,7 +1518,7 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) psta->sta_stats.rx_ctrl_pkts++; /* only handle ps-poll */ - if (GetFrameSubType(pframe) == WIFI_PSPOLL) { + if (get_frame_sub_type(pframe) == WIFI_PSPOLL) { #ifdef CONFIG_AP_MODE u16 aid; u8 wmmps_ac = 0; @@ -1720,7 +1632,7 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) } } #endif /* CONFIG_AP_MODE */ - } else if (GetFrameSubType(pframe) == WIFI_NDPA) { + } else if (get_frame_sub_type(pframe) == WIFI_NDPA) { #ifdef CONFIG_BEAMFORMING beamforming_get_ndpa_frame(padapter, precv_frame); #endif/*CONFIG_BEAMFORMING*/ @@ -1736,7 +1648,6 @@ sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) { /* struct mlme_priv *pmlmepriv = &adapter->mlmepriv; */ - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("+validate_recv_mgnt_frame\n")); #if 0 if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { @@ -1751,20 +1662,19 @@ sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) precv_frame = recvframe_chk_defrag(padapter, precv_frame); if (precv_frame == NULL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("%s: fragment packet\n", __FUNCTION__)); return _SUCCESS; } { /* for rx pkt statistics */ - struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, GetAddr2Ptr(precv_frame->u.hdr.rx_data)); + struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(precv_frame->u.hdr.rx_data)); if (psta) { psta->sta_stats.rx_mgnt_pkts++; - if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_BEACON) + if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_BEACON) psta->sta_stats.rx_beacon_pkts++; - else if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ) + else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ) psta->sta_stats.rx_probereq_pkts++; - else if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) { + else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) { if (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE) psta->sta_stats.rx_probersp_pkts++; else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)) @@ -1810,8 +1720,7 @@ sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) case 3: _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" case 3\n")); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); break; default: @@ -1842,7 +1751,6 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) struct security_priv *psecuritypriv = &adapter->securitypriv; sint ret = _SUCCESS; - _func_enter_; bretry = GetRetry(ptr); pda = get_da(ptr); @@ -1883,9 +1791,8 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) case 3: _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); ret = _FAIL; - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" case 3\n")); break; default: @@ -1904,7 +1811,6 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) if (psta == NULL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" after to_fr_ds_chk; psta==NULL\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s psta == NULL\n", __func__); #endif @@ -1927,9 +1833,9 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) pattrib->hdrlen = pattrib->to_fr_ds == 3 ? 32 : 26; if (pattrib->priority != 0 && pattrib->priority != 3) - adapter->recvpriv.bIsAnyNonBEPkts = _TRUE; + adapter->recvpriv.is_any_non_be_pkts = _TRUE; else - adapter->recvpriv.bIsAnyNonBEPkts = _FALSE; + adapter->recvpriv.is_any_non_be_pkts = _FALSE; } else { pattrib->priority = 0; pattrib->hdrlen = pattrib->to_fr_ds == 3 ? 30 : 24; @@ -1943,7 +1849,6 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) /* decache, drop duplicate recv packets */ if (recv_decache(precv_frame, bretry, &psta->sta_recvpriv.rxcache) == _FAIL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("decache : drop pkt\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s recv_decache return _FAIL\n", __func__); #endif @@ -1953,8 +1858,6 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) if (pattrib->privacy) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("validate_recv_data_frame:pattrib->privacy=%x\n", pattrib->privacy)); - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n ^^^^^^^^^^^IS_MCAST(pattrib->ra(0x%02x))=%d^^^^^^^^^^^^^^^6\n", pattrib->ra[0], IS_MCAST(pattrib->ra))); #ifdef CONFIG_TDLS if ((psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta->dot118021XPrivacy == _AES_)) @@ -1963,7 +1866,6 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) #endif /* CONFIG_TDLS */ GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, IS_MCAST(pattrib->ra)); - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n pattrib->encrypt=%d\n", pattrib->encrypt)); SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); } else { @@ -1973,7 +1875,6 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) exit: - _func_exit_; return ret; } @@ -1990,7 +1891,7 @@ static sint validate_80211w_mgmt(_adapter *adapter, union recv_frame *precv_fram u8 subtype; type = GetFrameType(ptr); - subtype = GetFrameSubType(ptr); /* bit(7)~bit(2) */ + subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */ if (adapter->securitypriv.binstallBIPkey == _TRUE) { /* unicast management frame decrypt */ @@ -1998,7 +1899,7 @@ static sint validate_80211w_mgmt(_adapter *adapter, union recv_frame *precv_fram (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || subtype == WIFI_ACTION)) { u8 *ppp, *mgmt_DATA; u32 data_len = 0; - ppp = GetAddr2Ptr(ptr); + ppp = get_addr2_ptr(ptr); pattrib->bdecrypted = 0; pattrib->encrypt = _AES_; @@ -2006,7 +1907,7 @@ static sint validate_80211w_mgmt(_adapter *adapter, union recv_frame *precv_fram /* set iv and icv length */ SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); /* actual management data frame body */ data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; mgmt_DATA = rtw_zmalloc(data_len); @@ -2063,7 +1964,7 @@ static sint validate_80211w_mgmt(_adapter *adapter, union recv_frame *precv_fram } } /* 802.11w protect */ else { - psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(ptr)); + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(ptr)); if (subtype == WIFI_ACTION && psta && psta->bpairwise_key_installed == _TRUE) { /* according 802.11-2012 standard, these five types are not robust types */ @@ -2122,6 +2023,7 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) u8 *ptr = precv_frame->u.hdr.rx_data; u8 ver = (unsigned char)(*ptr) & 0x3 ; #ifdef CONFIG_FIND_BEST_CHANNEL + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; #endif @@ -2136,13 +2038,12 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) u8 external_len = 0; #endif - _func_enter_; #ifdef CONFIG_FIND_BEST_CHANNEL if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { - int ch_set_idx = rtw_ch_set_search_ch(pmlmeext->channel_set, rtw_get_oper_ch(adapter)); + int ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, rtw_get_oper_ch(adapter)); if (ch_set_idx >= 0) - pmlmeext->channel_set[ch_set_idx].rx_count++; + rfctl->channel_set[ch_set_idx].rx_count++; } #endif @@ -2167,14 +2068,13 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) /* add version chk */ if (ver != 0) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("validate_recv_data_frame fail! (ver!=0)\n")); retval = _FAIL; DBG_COUNTER(adapter->rx_logs.core_rx_pre_ver_err); goto exit; } type = GetFrameType(ptr); - subtype = GetFrameSubType(ptr); /* bit(7)~bit(2) */ + subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */ pattrib->to_fr_ds = get_tofr_ds(ptr); @@ -2216,7 +2116,6 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) retval = validate_recv_mgnt_frame(adapter, precv_frame); if (retval == _FAIL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("validate_recv_mgnt_frame fail\n")); DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err); } retval = _FAIL; /* only data frame return _SUCCESS */ @@ -2225,7 +2124,6 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl); retval = validate_recv_ctrl_frame(adapter, precv_frame); if (retval == _FAIL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("validate_recv_ctrl_frame fail\n")); DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl_err); } retval = _FAIL; /* only data frame return _SUCCESS */ @@ -2252,7 +2150,7 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) } } else { - if (rtw_wapi_drop_for_key_absent(adapter, GetAddr2Ptr(ptr))) { + if (rtw_wapi_drop_for_key_absent(adapter, get_addr2_ptr(ptr))) { retval = _FAIL; WAPI_TRACE(WAPI_RX, "drop for key absent for rx\n"); DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_wapi_key_err); @@ -2266,7 +2164,6 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) retval = validate_recv_data_frame(adapter, precv_frame); if (retval == _FAIL) { struct recv_priv *precvpriv = &adapter->recvpriv; - /* RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail\n")); */ precvpriv->rx_drop++; DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_err); } else if (retval == _SUCCESS) { @@ -2287,7 +2184,6 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) break; default: DBG_COUNTER(adapter->rx_logs.core_rx_pre_unknown); - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("validate_recv_data_frame fail! type=0x%x\n", type)); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME validate_recv_data_frame fail! type=0x%x\n", type); #endif @@ -2297,7 +2193,6 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) exit: - _func_exit_; return retval; } @@ -2322,7 +2217,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) u8 *ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */ struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; - _func_enter_; if (pattrib->encrypt) recvframe_pull_tail(precvframe, pattrib->icv_len); @@ -2346,7 +2240,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0); len = precvframe->u.hdr.len - rmv_len; - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n\n", pattrib->hdrlen, pattrib->iv_len)); _rtw_memcpy(ð_type, ptr + rmv_len, 2); eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */ @@ -2417,7 +2310,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) } exiting: - _func_exit_; return ret; } @@ -2440,7 +2332,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; struct _vlan *pvlan = NULL; - _func_enter_; psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len); psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE; @@ -2453,7 +2344,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) else if (_rtw_memcmp(psnap->oui, oui_8021h, WLAN_IEEE_OUI_LEN)) bsnaphdr = _TRUE; /* wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_TUNNEL; */ else { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("drop pkt due to invalid frame format!\n")); ret = _FAIL; goto exit; } @@ -2462,7 +2352,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) bsnaphdr = _FALSE; /* wlan_pkt_format = WLAN_PKT_FORMAT_OTHERS; */ rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0); - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n", pattrib->hdrlen, pattrib->iv_len)); if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) { ptr += rmv_len ; @@ -2497,10 +2386,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) /* piphdr->tos = tos; */ - /* if (piphdr->protocol == 0x06) */ - /* { */ - /* RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("@@@===recv tcp len:%d @@@===\n", precvframe->u.hdr.len)); */ - /* } */ } else if (eth_type == 0x8712) { /* append rx status for mp test packets */ /* ptr -= 16; */ /* _rtw_memcpy(ptr, get_rxmem(precvframe), 16); */ @@ -2537,7 +2422,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) exit: - _func_exit_; return ret; } @@ -2614,7 +2498,6 @@ union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q) union recv_frame *prframe, *pnextrframe; _queue *pfree_recv_queue; - _func_enter_; curfragnum = 0; pfree_recv_queue = &adapter->recvpriv.free_recv_queue; @@ -2688,9 +2571,7 @@ union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q) /* free the defrag_q queue and return the prframe */ rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("Performance defrag!!!!!\n")); - _func_exit_; return prframe; } @@ -2708,7 +2589,6 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec union recv_frame *prtnframe = NULL; _queue *pfree_recv_queue, *pdefrag_q; - _func_enter_; pstapriv = &padapter->stapriv; @@ -2756,7 +2636,6 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec rtw_list_insert_tail(&pfhdr->list, phead); /* _rtw_spinunlock(&pdefrag_q->lock); */ - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("Enqueuq: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum)); prtnframe = NULL; @@ -2764,7 +2643,6 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec /* can't find this ta's defrag_queue, so free this recv_frame */ rtw_free_recvframe(precv_frame, pfree_recv_queue); prtnframe = NULL; - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("Free because pdefrag_q ==NULL: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum)); } } @@ -2779,7 +2657,6 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec /* _rtw_spinunlock(&pdefrag_q->lock); */ /* call recvframe_defrag to defrag */ - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("defrag: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum)); precv_frame = recvframe_defrag(padapter, pdefrag_q); prtnframe = precv_frame; @@ -2787,7 +2664,6 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec /* can't find this ta's defrag_queue, so free this recv_frame */ rtw_free_recvframe(precv_frame, pfree_recv_queue); prtnframe = NULL; - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("Free because pdefrag_q ==NULL: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum)); } } @@ -2796,13 +2672,11 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec if ((prtnframe != NULL) && (prtnframe->u.hdr.attrib.privacy)) { /* after defrag we must check tkip mic code */ if (recvframe_chkmic(padapter, prtnframe) == _FAIL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("recvframe_chkmic(padapter, prtnframe)==_FAIL\n")); rtw_free_recvframe(prtnframe, pfree_recv_queue); prtnframe = NULL; } } - _func_exit_; return prtnframe; @@ -2911,7 +2785,6 @@ int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num) /* Drop out the packet which SeqNum is smaller than WinStart */ if (SN_LESS(seq_num, preorder_ctrl->indicate_seq)) { - /* RT_TRACE(COMP_RX_REORDER, DBG_LOUD, ("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, NewSeqNum)); */ /* DbgPrint("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ #ifdef DBG_RX_DROP_FRAME @@ -2936,7 +2809,6 @@ int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num) preorder_ctrl->indicate_seq, seq_num); #endif } else if (SN_LESS(wend, seq_num)) { - /* RT_TRACE(COMP_RX_REORDER, DBG_LOUD, ("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, NewSeqNum)); */ /* DbgPrint("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ /* boundary situation, when seq_num cross 0xFFF */ @@ -2982,7 +2854,6 @@ int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union rec plist = get_next(plist); else if (SN_EQUAL(pnextattrib->seq_num, pattrib->seq_num)) { /* Duplicate entry is found!! Do not insert current entry. */ - /* RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("InsertRxReorderList(): Duplicate packet is dropped!! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, SeqNum)); */ /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ @@ -3006,7 +2877,6 @@ int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union rec /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ - /* RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("InsertRxReorderList(): Pkt insert into buffer!! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, SeqNum)); */ return _TRUE; } @@ -3024,7 +2894,6 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced) { /* _irqL irql; */ - /* u8 bcancelled; */ _list *phead, *plist; union recv_frame *prframe; struct rx_pkt_attrib *pattrib; @@ -3080,9 +2949,6 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre pattrib = &prframe->u.hdr.attrib; if (!SN_LESS(preorder_ctrl->indicate_seq, pattrib->seq_num)) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, - ("recv_indicatepkts_in_order: indicate=%d seq=%d amsdu=%d\n", - preorder_ctrl->indicate_seq, pattrib->seq_num, pattrib->amsdu)); #if 0 /* This protect buffer from overflow. */ @@ -3110,8 +2976,8 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre /* Cancel previous pending timer. */ /* PlatformCancelTimer(Adapter, &pTS->RxPktPendingTimer); */ if (bforced != _TRUE) { - /* RTW_INFO("_cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled);\n"); */ - _cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled); + /* RTW_INFO("_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);\n"); */ + _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); } } #endif @@ -3190,7 +3056,6 @@ int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) /* s1. */ retval = wlanhdr_to_ethhdr(prframe); if (retval != _SUCCESS) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("wlanhdr_to_ethhdr: drop pkt\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__); #endif @@ -3201,7 +3066,6 @@ int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) /* || (pattrib->eth_type==0x0806) || (pattrib->ack_policy!=0)) */ if (pattrib->qos != 1) { if (!RTW_CANNOT_RUN(padapter)) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ recv_indicatepkt_reorder -recv_func recv_indicatepkt\n")); rtw_recv_indicatepkt(padapter, prframe); return _SUCCESS; @@ -3271,16 +3135,12 @@ int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); - RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, - ("recv_indicatepkt_reorder: indicate=%d seq=%d\n", - preorder_ctrl->indicate_seq, pattrib->seq_num)); /* s2. check if winstart_b(indicate_seq) needs to been updated */ if (!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) { pdbgpriv->dbg_rx_ampdu_drop_count++; /* pHTInfo->RxReorderDropCounter++; */ /* ReturnRFDList(Adapter, pRfd); */ - /* RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("RxReorderIndicatePacket() ==> Packet Drop!!\n")); */ /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ /* return _FAIL; */ @@ -3415,7 +3275,6 @@ int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe) { retval = wlanhdr_to_ethhdr(prframe); if (retval != _SUCCESS) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("wlanhdr_to_ethhdr: drop pkt\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__); #endif @@ -3424,14 +3283,9 @@ int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe) if (!RTW_CANNOT_RUN(padapter)) { /* indicate this recv_frame */ - RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ process_recv_indicatepkts- recv_func recv_indicatepkt\n")); rtw_recv_indicatepkt(padapter, prframe); } else { - RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ process_recv_indicatepkts- recv_func free_indicatepkt\n")); - RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)" - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False")); retval = _FAIL; return retval; } @@ -3450,6 +3304,7 @@ int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame) u8 type, subtype; struct mp_priv *pmppriv = &adapter->mppriv; struct mp_tx *pmptx; + unsigned char *sa , *da, *bs; pmptx = &pmppriv->tx; @@ -3457,7 +3312,7 @@ int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame) if (1) { u8 bDumpRxPkt; type = GetFrameType(ptr); - subtype = GetFrameSubType(ptr); /* bit(7)~bit(2) */ + subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */ rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt)); if (bDumpRxPkt == 1) { /* dump all rx packets */ @@ -3477,16 +3332,31 @@ int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame) ret = _FAIL; } } + if (pmppriv->bSetRxBssid == _TRUE) { + + sa = get_addr2_ptr(ptr); + da = GetAddr1Ptr(ptr); + bs = GetAddr3Ptr(ptr); + type = GetFrameType(ptr); + subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */ + + if (_rtw_memcmp(bs, adapter->mppriv.network_macaddr, ETH_ALEN) == _FALSE) + ret = _FAIL; + + RTW_DBG("############ type:0x%02x subtype:0x%02x #################\n", type, subtype); + RTW_DBG("A2 sa %02X:%02X:%02X:%02X:%02X:%02X \n", *(sa) , *(sa + 1), *(sa+ 2), *(sa + 3), *(sa + 4), *(sa + 5)); + RTW_DBG("A1 da %02X:%02X:%02X:%02X:%02X:%02X \n", *(da) , *(da + 1), *(da+ 2), *(da + 3), *(da + 4), *(da + 5)); + RTW_DBG("A3 bs %02X:%02X:%02X:%02X:%02X:%02X \n --------------------------\n", *(bs) , *(bs + 1), *(bs+ 2), *(bs + 3), *(bs + 4), *(bs + 5)); + } if (!adapter->mppriv.bmac_filter) return ret; - if (_rtw_memcmp(GetAddr2Ptr(ptr), adapter->mppriv.mac_filter, ETH_ALEN) == _FALSE) + if (_rtw_memcmp(get_addr2_ptr(ptr), adapter->mppriv.mac_filter, ETH_ALEN) == _FALSE) ret = _FAIL; return ret; } -#endif static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe) { @@ -3505,7 +3375,6 @@ static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe) u8 *ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */ struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; - _func_enter_; if (pattrib->encrypt) recvframe_pull_tail(precvframe, pattrib->icv_len); @@ -3529,7 +3398,6 @@ static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe) rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0); len = precvframe->u.hdr.len - rmv_len; - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n\n", pattrib->hdrlen, pattrib->iv_len)); _rtw_memcpy(ð_type, ptr + rmv_len, 2); eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */ @@ -3561,7 +3429,6 @@ static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe) } - _func_exit_; return ret; } @@ -3594,7 +3461,6 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) } if (pmppriv->rx_bindicatePkt == _FALSE) { - /* RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("MP - Not in loopback mode , drop pkt\n")); */ ret = _FAIL; rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ goto exit; @@ -3641,9 +3507,8 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) case 3: _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); ret = _FAIL; - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" case 3\n")); break; default: @@ -3654,7 +3519,6 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) ret = MPwlanhdr_to_ethhdr(rframe); if (ret != _SUCCESS) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("wlanhdr_to_ethhdr: drop pkt\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__); #endif @@ -3663,7 +3527,6 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) goto exit; } if (!RTW_CANNOT_RUN(padapter)) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: recv_func rtw_recv_indicatepkt\n")); /* indicate this recv_frame */ ret = rtw_recv_indicatepkt(padapter, rframe); if (ret != _SUCCESS) { @@ -3676,10 +3539,6 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) goto exit; } } else { - RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: rtw_free_recvframe\n")); - RT_TRACE(_module_rtl871x_recv_c_, _drv_debug_, ("recv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)" - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s ecv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)\n", __func__, rtw_is_drv_stopped(padapter) ? "True" : "False", @@ -3695,7 +3554,6 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) } - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("recv_func: validate_recv_frame fail! drop pkt\n")); rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ ret = _FAIL; @@ -3703,6 +3561,7 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) return ret; } +#endif static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, u8 *buf) { @@ -3737,6 +3596,11 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, /* (0 << IEEE80211_RADIOTAP_AMPDU_STATUS) | \ */ /* (0 << IEEE80211_RADIOTAP_VHT) | \ */ #endif + +#ifndef IEEE80211_RADIOTAP_RX_FLAGS +#define IEEE80211_RADIOTAP_RX_FLAGS 14 +#endif + #ifndef IEEE80211_RADIOTAP_MCS #define IEEE80211_RADIOTAP_MCS 19 #endif @@ -3837,13 +3701,13 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, tmp_16bit = 0; rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_CHANNEL); tmp_16bit = CHAN2FREQ(rtw_get_oper_ch(padapter)); - /*tmp_16bit = CHAN2FREQ(pHalData->CurrentChannel);*/ + /*tmp_16bit = CHAN2FREQ(pHalData->current_channel);*/ memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); rt_len += 2; /* channel flags */ tmp_16bit = 0; - if (pHalData->CurrentBandType == 0) + if (pHalData->current_band_type == 0) tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_2GHZ); else tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_5GHZ); @@ -4006,7 +3870,7 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, return ret; } - +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe) { int ret = _SUCCESS; @@ -4053,7 +3917,7 @@ int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe) exit: return ret; } - +#endif int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe) { int ret = _SUCCESS; @@ -4081,7 +3945,6 @@ int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe) /* check the frame crtl field and decache */ ret = validate_recv_frame(padapter, rframe); if (ret != _SUCCESS) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("recv_func: validate_recv_frame fail! drop pkt\n")); rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ goto exit; } @@ -4109,7 +3972,6 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) prframe = decryptor(padapter, prframe); if (prframe == NULL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("decryptor: drop pkt\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s decryptor: drop pkt\n", __FUNCTION__); #endif @@ -4157,7 +4019,6 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) prframe = recvframe_chk_defrag(padapter, prframe); if (prframe == NULL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("recvframe_chk_defrag: drop pkt\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s recvframe_chk_defrag: drop pkt\n", __FUNCTION__); #endif @@ -4167,7 +4028,6 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) prframe = portctrl(padapter, prframe); if (prframe == NULL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("portctrl: drop pkt\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s portctrl: drop pkt\n", __FUNCTION__); #endif @@ -4185,7 +4045,6 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) #ifdef CONFIG_80211N_HT ret = process_recv_indicatepkts(padapter, prframe); if (ret != _SUCCESS) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("recv_func: process_recv_indicatepkts fail!\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s process_recv_indicatepkts fail!\n", __FUNCTION__); #endif @@ -4197,7 +4056,6 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) if (!pattrib->amsdu) { ret = wlanhdr_to_ethhdr(prframe); if (ret != _SUCCESS) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("wlanhdr_to_ethhdr: drop pkt\n")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__); #endif @@ -4206,7 +4064,6 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) } if (!RTW_CANNOT_RUN(padapter)) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: recv_func rtw_recv_indicatepkt\n")); /* indicate this recv_frame */ ret = rtw_recv_indicatepkt(padapter, prframe); if (ret != _SUCCESS) { @@ -4216,10 +4073,6 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) goto _recv_data_drop; } } else { - RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: rtw_free_recvframe\n")); - RT_TRACE(_module_rtl871x_recv_c_, _drv_debug_, ("recv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)" - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False")); #ifdef DBG_RX_DROP_FRAME RTW_INFO("DBG_RX_DROP_FRAME %s recv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)\n", __func__ @@ -4268,7 +4121,9 @@ int recv_func(_adapter *padapter, union recv_frame *rframe) if (check_fwstate(mlmepriv, WIFI_MONITOR_STATE)) { /* monitor mode */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) recv_frame_monitor(padapter, rframe); +#endif ret = _SUCCESS; goto exit; } else @@ -4328,9 +4183,7 @@ s32 rtw_recv_entry(union recv_frame *precvframe) struct recv_priv *precvpriv; s32 ret = _SUCCESS; - _func_enter_; - /* RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("+rtw_recv_entry\n")); */ padapter = precvframe->u.hdr.adapter; @@ -4339,14 +4192,12 @@ s32 rtw_recv_entry(union recv_frame *precvframe) ret = recv_func(padapter, precvframe); if (ret == _FAIL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("rtw_recv_entry: recv_func return fail!!!\n")); goto _recv_entry_drop; } precvpriv->rx_pkts++; - _func_exit_; return ret; @@ -4357,17 +4208,15 @@ s32 rtw_recv_entry(union recv_frame *precvframe) padapter->mppriv.rx_pktloss = precvpriv->rx_drop; #endif - /* RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("_recv_entry_drop\n")); */ - _func_exit_; return ret; } #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS -void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS) +static void rtw_signal_stat_timer_hdl(void *ctx) { - _adapter *adapter = (_adapter *)FunctionContext; + _adapter *adapter = (_adapter *)ctx; struct recv_priv *recvpriv = &adapter->recvpriv; u32 tmp_s, tmp_q; @@ -4509,8 +4358,6 @@ static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe) padapter->recvpriv.rssi = (s8)translate_percentage_to_dbm(tmp_val); } - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val, - padapter->recvpriv.signal_strength_data.total_num)); #endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ } } @@ -4560,14 +4407,12 @@ static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe) if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX) padapter->recvpriv.signal_qual_data.index = 0; - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, pattrib->phy_info.SignalQuality)); /* <1> Showed on UI for user, in percentage. */ tmpVal = padapter->recvpriv.signal_qual_data.total_val / padapter->recvpriv.signal_qual_data.total_num; padapter->recvpriv.signal_qual = (u8)tmpVal; - } else - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" pattrib->signal_qual =%d\n", pattrib->phy_info.SignalQuality)); + } #endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ } @@ -4593,9 +4438,9 @@ void rx_query_phy_status( PADAPTER padapter = precvframe->u.hdr.adapter; struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - PODM_PHY_INFO_T pPHYInfo = (PODM_PHY_INFO_T)(&pattrib->phy_info); + struct _odm_phy_status_info_ *pPHYInfo = (struct _odm_phy_status_info_ *)(&pattrib->phy_info); u8 *wlanhdr; - ODM_PACKET_INFO_T pkt_info; + struct _odm_per_pkt_info_ pkt_info; u8 *sa; struct sta_priv *pstapriv; struct sta_info *psta = NULL; @@ -4603,28 +4448,28 @@ void rx_query_phy_status( struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; /* _irqL irqL; */ - pkt_info.bPacketMatchBSSID = _FALSE; - pkt_info.bPacketToSelf = _FALSE; - pkt_info.bPacketBeacon = _FALSE; + pkt_info.is_packet_match_bssid = _FALSE; + pkt_info.is_packet_to_self = _FALSE; + pkt_info.is_packet_beacon = _FALSE; wlanhdr = get_recvframe_data(precvframe); - pkt_info.bPacketMatchBSSID = (!IsFrameTypeCtrl(wlanhdr)) + pkt_info.is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr)) && (!pattrib->icv_err) && (!pattrib->crc_err) && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN); - pkt_info.bToSelf = (!pattrib->icv_err) && (!pattrib->crc_err) + pkt_info.is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err) && _rtw_memcmp(get_ra(wlanhdr), adapter_mac_addr(padapter), ETH_ALEN); - pkt_info.bPacketToSelf = pkt_info.bPacketMatchBSSID + pkt_info.is_packet_to_self = pkt_info.is_packet_match_bssid && _rtw_memcmp(get_ra(wlanhdr), adapter_mac_addr(padapter), ETH_ALEN); - pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID - && (GetFrameSubType(wlanhdr) == WIFI_BEACON); + pkt_info.is_packet_beacon = pkt_info.is_packet_match_bssid + && (get_frame_sub_type(wlanhdr) == WIFI_BEACON); sa = get_ta(wlanhdr); - pkt_info.StationID = 0xFF; + pkt_info.station_id = 0xFF; if (_rtw_memcmp(adapter_mac_addr(padapter), sa, ETH_ALEN) == _TRUE) { static u32 start_time = 0; @@ -4633,7 +4478,7 @@ void rx_query_phy_status( if (IsFrameTypeCtrl(wlanhdr)) { RTW_INFO("-->Control frame: Y\n"); RTW_INFO("-->pkt_len: %d\n", pattrib->pkt_len); - RTW_INFO("-->Sub Type = 0x%X\n", GetFrameSubType(wlanhdr)); + RTW_INFO("-->Sub Type = 0x%X\n", get_frame_sub_type(wlanhdr)); } /* Dump first 40 bytes of header */ @@ -4654,33 +4499,35 @@ void rx_query_phy_status( pstapriv = &padapter->stapriv; psta = rtw_get_stainfo(pstapriv, sa); if (psta) - pkt_info.StationID = psta->mac_id; + pkt_info.station_id = psta->mac_id; } - pkt_info.DataRate = pattrib->data_rate; + pkt_info.data_rate = pattrib->data_rate; /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ - ODM_PhyStatusQuery(&pHalData->odmpriv, pPHYInfo, pphy_status, &pkt_info); + odm_phy_status_query(&pHalData->odmpriv, pPHYInfo, pphy_status, &pkt_info); if (psta) psta->rssi = pattrib->phy_info.RecvSignalPower; /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ { precvframe->u.hdr.psta = NULL; - if (pkt_info.bPacketMatchBSSID - && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) + if ((pkt_info.is_packet_match_bssid + && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)) || (padapter->registrypriv.mp_mode == 1) ) { if (psta) { precvframe->u.hdr.psta = psta; rx_process_phy_info(padapter, precvframe); } - } else if (pkt_info.bPacketToSelf || pkt_info.bPacketBeacon) { + } else if (pkt_info.is_packet_to_self || pkt_info.is_packet_beacon) { if (psta) precvframe->u.hdr.psta = psta; rx_process_phy_info(padapter, precvframe); } } + + rtw_odm_parse_rx_phy_status_chinfo(precvframe, pphy_status); } /* * Increase and check if the continual_no_rx_packet of this @param pmlmepriv is larger than MAX_CONTINUAL_NORXPACKET_COUNT @@ -4717,6 +4564,11 @@ s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status) _adapter *iface = NULL; _adapter *primary_padapter = precvframe->u.hdr.adapter; +#ifdef CONFIG_MP_INCLUDED + if (rtw_mp_mode_check(primary_padapter)) + return ret; +#endif + pda = get_ra(pbuf); if (IS_MCAST(pda) == _FALSE) { /*unicast packets*/ @@ -4732,3 +4584,57 @@ s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status) return ret; } + +#ifdef CONFIG_RECV_THREAD_MODE +thread_return rtw_recv_thread(thread_context context) +{ + _adapter *adapter = (_adapter *)context; + struct recv_priv *recvpriv = &adapter->recvpriv; + s32 err = _SUCCESS; +#ifdef PLATFORM_LINUX + struct sched_param param = { .sched_priority = 1 }; + + sched_setscheduler(current, SCHED_FIFO, ¶m); +#endif /* PLATFORM_LINUX */ + thread_enter("RTW_RECV_THREAD"); + + RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter)); + + do { + err = _rtw_down_sema(&recvpriv->recv_sema); + if (_FAIL == err) { + RTW_ERR(FUNC_ADPT_FMT" down recv_sema fail!\n", FUNC_ADPT_ARG(adapter)); + goto exit; + } + + if (RTW_CANNOT_RUN(adapter)) { + RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n", + FUNC_ADPT_ARG(adapter), + rtw_is_drv_stopped(adapter) ? "True" : "False", + rtw_is_surprise_removed(adapter) ? "True" : "False"); + goto exit; + } + + err = rtw_hal_recv_hdl(adapter); + + if (err == RTW_RFRAME_UNAVAIL + || err == RTW_RFRAME_PKT_UNAVAIL + ) { + rtw_msleep_os(1); + _rtw_up_sema(&recvpriv->recv_sema); + } + + flush_signals_thread(); + + } while (err != _FAIL); + +exit: + + RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(adapter)); + + rtw_thread_wait_stop(); + + return 0; +} +#endif /* CONFIG_RECV_THREAD_MODE */ + diff --git a/core/rtw_rf.c b/core/rtw_rf.c index 667383a..60a714e 100644 --- a/core/rtw_rf.c +++ b/core/rtw_rf.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,24 +11,19 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_RF_C_ #include #include u8 center_ch_2g[CENTER_CH_2G_NUM] = { - /* G00 */1, 2, - /* G01 */3, 4, 5, - /* G02 */6, 7, 8, - /* G03 */9, 10, 11, - /* G04 */12, 13, - /* G05 */14 +/* G00 */1, 2, +/* G01 */3, 4, 5, +/* G02 */6, 7, 8, +/* G03 */9, 10, 11, +/* G04 */12, 13, +/* G05 */14 }; u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM] = { @@ -56,64 +51,81 @@ u8 op_chs_of_cch_2g_40m[CENTER_CH_2G_40M_NUM][2] = { }; u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM] = { - /* G00 */36, 38, 40, +/* G00 */36, 38, 40, 42, - /* G01 */44, 46, 48, +/* G01 */44, 46, 48, /* 50, */ - /* G02 */52, 54, 56, +/* G02 */52, 54, 56, 58, - /* G03 */60, 62, 64, - /* G04 */100, 102, 104, +/* G03 */60, 62, 64, +/* G04 */100, 102, 104, 106, - /* G05 */108, 110, 112, +/* G05 */108, 110, 112, /* 114, */ - /* G06 */116, 118, 120, +/* G06 */116, 118, 120, 122, - /* G07 */124, 126, 128, - /* G08 */132, 134, 136, +/* G07 */124, 126, 128, +/* G08 */132, 134, 136, 138, - /* G09 */140, 142, 144, - /* G10 */149, 151, 153, +/* G09 */140, 142, 144, +/* G10 */149, 151, 153, 155, - /* G11 */157, 159, 161, +/* G11 */157, 159, 161, /* 163, */ - /* G12 */165, 167, 169, +/* G12 */165, 167, 169, 171, - /* G13 */173, 175, 177 +/* G13 */173, 175, 177 }; u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM] = { - /* G00 */36, 40, - /* G01 */44, 48, - /* G02 */52, 56, - /* G03 */60, 64, - /* G04 */100, 104, - /* G05 */108, 112, - /* G06 */116, 120, - /* G07 */124, 128, - /* G08 */132, 136, - /* G09 */140, 144, - /* G10 */149, 153, - /* G11 */157, 161, - /* G12 */165, 169, - /* G13 */173, 177 +/* G00 */36, 40, +/* G01 */44, 48, +/* G02 */52, 56, +/* G03 */60, 64, +/* G04 */100, 104, +/* G05 */108, 112, +/* G06 */116, 120, +/* G07 */124, 128, +/* G08 */132, 136, +/* G09 */140, 144, +/* G10 */149, 153, +/* G11 */157, 161, +/* G12 */165, 169, +/* G13 */173, 177 }; u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM] = { - /* G00 */38, - /* G01 */46, - /* G02 */54, - /* G03 */62, - /* G04 */102, - /* G05 */110, - /* G06 */118, - /* G07 */126, - /* G08 */134, - /* G09 */142, - /* G10 */151, - /* G11 */159, - /* G12 */167, - /* G13 */175 +/* G00 */38, +/* G01 */46, +/* G02 */54, +/* G03 */62, +/* G04 */102, +/* G05 */110, +/* G06 */118, +/* G07 */126, +/* G08 */134, +/* G09 */142, +/* G10 */151, +/* G11 */159, +/* G12 */167, +/* G13 */175 +}; + +u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM] = { +/* G00 */36, 38, 40, +/* G01 */44, 46, 48, +/* G02 */52, 54, 56, +/* G03 */60, 62, 64, +/* G04 */100, 102, 104, +/* G05 */108, 110, 112, +/* G06 */116, 118, 120, +/* G07 */124, 126, 128, +/* G08 */132, 134, 136, +/* G09 */140, 142, 144, +/* G10 */149, 151, 153, +/* G11 */157, 159, 161, +/* G12 */165, 167, 169, +/* G13 */173, 175, 177 }; u8 op_chs_of_cch_5g_40m[CENTER_CH_5G_40M_NUM][2] = { @@ -134,13 +146,13 @@ u8 op_chs_of_cch_5g_40m[CENTER_CH_5G_40M_NUM][2] = { }; u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM] = { - /* G00 ~ G01*/42, - /* G02 ~ G03*/58, - /* G04 ~ G05*/106, - /* G06 ~ G07*/122, - /* G08 ~ G09*/138, - /* G10 ~ G11*/155, - /* G12 ~ G13*/171 +/* G00 ~ G01*/42, +/* G02 ~ G03*/58, +/* G04 ~ G05*/106, +/* G06 ~ G07*/122, +/* G08 ~ G09*/138, +/* G10 ~ G11*/155, +/* G12 ~ G13*/171 }; u8 op_chs_of_cch_5g_80m[CENTER_CH_5G_80M_NUM][4] = { @@ -154,9 +166,9 @@ u8 op_chs_of_cch_5g_80m[CENTER_CH_5G_80M_NUM][4] = { }; u8 center_ch_5g_160m[CENTER_CH_5G_160M_NUM] = { - /* G00 ~ G03*/50, - /* G04 ~ G07*/114, - /* G10 ~ G13*/163 +/* G00 ~ G03*/50, +/* G04 ~ G07*/114, +/* G10 ~ G13*/163 }; u8 op_chs_of_cch_5g_160m[CENTER_CH_5G_160M_NUM][8] = { @@ -182,6 +194,59 @@ struct center_chs_ent_t center_chs_5g_by_bw[] = { {CENTER_CH_5G_160M_NUM, center_ch_5g_160m}, }; +/* + * Get center channel of smaller bandwidth by @param cch, @param bw, @param offset + * @cch: the given center channel + * @bw: the given bandwidth + * @offset: the given primary SC offset of the given bandwidth + * + * return center channel of smaller bandiwdth if valid, or 0 + */ +u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset) +{ + int i; + u8 t_cch = 0; + + if (bw == CHANNEL_WIDTH_20) { + t_cch = cch; + goto exit; + } + + if (offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { + rtw_warn_on(1); + goto exit; + } + + /* 2.4G, 40MHz */ + if (cch >= 3 && cch <= 11 && bw == CHANNEL_WIDTH_40) { + t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; + goto exit; + } + + /* 5G, 160MHz */ + if (cch >= 50 && cch <= 163 && bw == CHANNEL_WIDTH_160) { + t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8; + goto exit; + + /* 5G, 80MHz */ + } else if (cch >= 42 && cch <= 171 && bw == CHANNEL_WIDTH_80) { + t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4; + goto exit; + + /* 5G, 40MHz */ + } else if (cch >= 38 && cch <= 175 && bw == CHANNEL_WIDTH_40) { + t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; + goto exit; + + } else { + rtw_warn_on(1); + goto exit; + } + +exit: + return t_cch; +} + struct op_chs_ent_t { u8 ch_num; u8 *chs; @@ -199,15 +264,36 @@ struct op_chs_ent_t op_chs_of_cch_5g_by_bw[] = { {8, (u8 *)op_chs_of_cch_5g_160m}, }; -inline u8 center_chs_5g_num(u8 bw) { - if (bw >= CHANNEL_WIDTH_160) +inline u8 center_chs_2g_num(u8 bw) +{ + if (bw > CHANNEL_WIDTH_40) + return 0; + + return center_chs_2g_by_bw[bw].ch_num; +} + +inline u8 center_chs_2g(u8 bw, u8 id) +{ + if (bw > CHANNEL_WIDTH_40) + return 0; + + if (id >= center_chs_2g_num(bw)) + return 0; + + return center_chs_2g_by_bw[bw].chs[id]; +} + +inline u8 center_chs_5g_num(u8 bw) +{ + if (bw > CHANNEL_WIDTH_80) return 0; return center_chs_5g_by_bw[bw].ch_num; } -inline u8 center_chs_5g(u8 bw, u8 id) { - if (bw >= CHANNEL_WIDTH_160) +inline u8 center_chs_5g(u8 bw, u8 id) +{ + if (bw > CHANNEL_WIDTH_80) return 0; if (id >= center_chs_5g_num(bw)) @@ -225,20 +311,21 @@ inline u8 center_chs_5g(u8 bw, u8 id) { * * return valid (1) or not (0) */ -u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num) { +u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num) +{ int i; struct center_chs_ent_t *c_chs_ent = NULL; struct op_chs_ent_t *op_chs_ent = NULL; u8 valid = 1; if (cch <= 14 - && bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_40 - ) { + && bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_40 + ) { c_chs_ent = ¢er_chs_2g_by_bw[bw]; op_chs_ent = &op_chs_of_cch_2g_by_bw[bw]; } else if (cch >= 36 && cch <= 177 - && bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_160 - ) { + && bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_160 + ) { c_chs_ent = ¢er_chs_5g_by_bw[bw]; op_chs_ent = &op_chs_of_cch_5g_by_bw[bw]; } else { @@ -262,7 +349,86 @@ u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num) { return valid; } -int rtw_ch2freq(int chan) { +u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group) +{ + BAND_TYPE band = BAND_MAX; + s8 gp = -1, cck_gp = -1; + + if (ch <= 14) { + band = BAND_ON_2_4G; + + if (1 <= ch && ch <= 2) + gp = 0; + else if (3 <= ch && ch <= 5) + gp = 1; + else if (6 <= ch && ch <= 8) + gp = 2; + else if (9 <= ch && ch <= 11) + gp = 3; + else if (12 <= ch && ch <= 14) + gp = 4; + else + band = BAND_MAX; + + if (ch == 14) + cck_gp = 5; + else + cck_gp = gp; + } else { + band = BAND_ON_5G; + + if (36 <= ch && ch <= 42) + gp = 0; + else if (44 <= ch && ch <= 48) + gp = 1; + else if (50 <= ch && ch <= 58) + gp = 2; + else if (60 <= ch && ch <= 64) + gp = 3; + else if (100 <= ch && ch <= 106) + gp = 4; + else if (108 <= ch && ch <= 114) + gp = 5; + else if (116 <= ch && ch <= 122) + gp = 6; + else if (124 <= ch && ch <= 130) + gp = 7; + else if (132 <= ch && ch <= 138) + gp = 8; + else if (140 <= ch && ch <= 144) + gp = 9; + else if (149 <= ch && ch <= 155) + gp = 10; + else if (157 <= ch && ch <= 161) + gp = 11; + else if (165 <= ch && ch <= 171) + gp = 12; + else if (173 <= ch && ch <= 177) + gp = 13; + else + band = BAND_MAX; + } + + if (band == BAND_MAX + || (band == BAND_ON_2_4G && cck_gp == -1) + || gp == -1 + ) { + RTW_WARN("%s invalid channel:%u", __func__, ch); + rtw_warn_on(1); + goto exit; + } + + if (group) + *group = gp; + if (cck_group && band == BAND_ON_2_4G) + *cck_group = cck_gp; + +exit: + return band; +} + +int rtw_ch2freq(int chan) +{ /* see 802.11 17.3.8.3.2 and Annex J * there are overlapping channel numbers in 5GHz and 2GHz bands */ @@ -282,7 +448,8 @@ int rtw_ch2freq(int chan) { return 0; /* not supported */ } -int rtw_freq2ch(int freq) { +int rtw_freq2ch(int freq) +{ /* see 802.11 17.3.8.3.2 and Annex J */ if (freq == 2484) return 14; @@ -298,7 +465,8 @@ int rtw_freq2ch(int freq) { return 0; } -bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo) { +bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo) +{ u8 c_ch; u32 freq; u32 hi_ret = 0, lo_ret = 0; @@ -373,6 +541,30 @@ const u8 _band_to_band_cap[] = { 0, }; +const u8 _rf_type_to_rf_tx_cnt[] = { + 1, + 2, + 2, + 1, + 2, + 2, + 3, + 3, + 4, +}; + +const u8 _rf_type_to_rf_rx_cnt[] = { + 2, + 4, + 2, + 1, + 2, + 3, + 3, + 4, + 4, +}; + #ifdef CONFIG_80211AC_VHT #define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) , .en_11ac = (_val) #else @@ -388,8 +580,8 @@ const u8 _band_to_band_cap[] = { /* has def_module_flags specified, used by common map and HAL dfference map */ #define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _en_11ac, _def_module_flags) \ {.alpha2 = (_alpha2), .chplan = (_chplan) \ - COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \ - COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_def_module_flags) \ + COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \ + COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_def_module_flags) \ } #ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP @@ -398,57 +590,93 @@ const u8 _band_to_band_cap[] = { #elif RTW_DEF_MODULE_REGULATORY_CERT -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2) -static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("CN", 0x51, 1, 0xFB), /* China */ - COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0xFB), /* Russia(fac/gost), Kaliningrad */ - COUNTRY_CHPLAN_ENT("UA", 0x26, 0, 0xFB), /* Ukraine */ +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2) /* 2013 certify */ +static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0x3FB), /* Canada */ + COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0x3F1), /* Chile */ + COUNTRY_CHPLAN_ENT("CN", 0x51, 1, 0x3FB), /* China */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x3F1), /* Mexico */ + COUNTRY_CHPLAN_ENT("MY", 0x47, 1, 0x3F1), /* Malaysia */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0x3FB), /* Ukraine */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ }; -static const u16 RTL8821AE_HMC_M2_country_chplan_map_sz = sizeof(RTL8821AE_HMC_M2_country_chplan_map) / sizeof(struct country_chplan); #endif -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU) -static const struct country_chplan RTL8821AU_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0xFB), /* Russia(fac/gost), Kaliningrad */ - COUNTRY_CHPLAN_ENT("UA", 0x26, 0, 0xFB), /* Ukraine */ +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU) /* 2014 certify */ +static const struct country_chplan RTL8821AU_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0x3FB), /* Canada */ + COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0x3FB), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0x3FB), /* Ukraine */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ }; -static const u16 RTL8821AU_country_chplan_map_sz = sizeof(RTL8821AU_country_chplan_map) / sizeof(struct country_chplan); #endif -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF) -static const struct country_chplan RTL8812AENF_NGFF_country_chplan_map[] = { +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF) /* 2014 certify */ +static const struct country_chplan RTL8812AENF_NGFF_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ }; -static const u16 RTL8812AENF_NGFF_country_chplan_map_sz = sizeof(RTL8812AENF_NGFF_country_chplan_map) / sizeof(struct country_chplan); #endif -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC) -static const struct country_chplan RTL8812AEBT_HMC_country_chplan_map[] = { +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC) /* 2013 certify */ +static const struct country_chplan RTL8812AEBT_HMC_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0x3FB), /* Canada */ + COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0x3FB), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0x3FB), /* Ukraine */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ }; -static const u16 RTL8812AEBT_HMC_country_chplan_map_sz = sizeof(RTL8812AEBT_HMC_country_chplan_map) / sizeof(struct country_chplan); #endif -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2) -static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_map[] = { +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2) /* 2012 certify */ +static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0x3FB), /* Canada */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x3F1), /* Mexico */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ }; -static const u16 RTL8188EE_HMC_M2_country_chplan_map_sz = sizeof(RTL8188EE_HMC_M2_country_chplan_map) / sizeof(struct country_chplan); #endif -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2) -static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_map[] = { +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2) /* 2013 certify */ +static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0x3FB), /* Canada */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x3F1), /* Mexico */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ }; -static const u16 RTL8723BE_HMC_M2_country_chplan_map_sz = sizeof(RTL8723BE_HMC_M2_country_chplan_map) / sizeof(struct country_chplan); #endif -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216) -static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_map[] = { +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216) /* 2014 certify */ +static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0x3FB), /* Canada */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x3F1), /* Mexico */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ }; -static const u16 RTL8723BS_NGFF1216_country_chplan_map_sz = sizeof(RTL8723BS_NGFF1216_country_chplan_map) / sizeof(struct country_chplan); #endif -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2) -static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_map[] = { +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2) /* 2013 certify */ +static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0x3FB), /* Canada */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x3F1), /* Mexico */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723DE_NGFF1630) /* 2016 certify */ +static const struct country_chplan RTL8723DE_NGFF1630_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CA", 0x2A, 1, 0x3FB), /* Canada */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x3F1), /* Mexico */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8822BE) /* 2016 certify */ +static const struct country_chplan RTL8822BE_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0x3F1), /* Chile */ }; -static const u16 RTL8192EEBT_HMC_M2_country_chplan_map_sz = sizeof(RTL8192EEBT_HMC_M2_country_chplan_map) / sizeof(struct country_chplan); #endif /** @@ -457,7 +685,8 @@ static const u16 RTL8192EEBT_HMC_M2_country_chplan_map_sz = sizeof(RTL8192EEBT_H * @return: * Return NULL for case referring to common map */ -static const struct country_chplan *rtw_def_module_get_chplan_from_country(const char *country_code) { +static const struct country_chplan *rtw_def_module_get_chplan_from_country(const char *country_code) +{ const struct country_chplan *ent = NULL; const struct country_chplan *hal_map = NULL; u16 hal_map_sz = 0; @@ -465,29 +694,35 @@ static const struct country_chplan *rtw_def_module_get_chplan_from_country(const /* TODO: runtime selection for multi driver */ #if (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AE_HMC_M2) - hal_map = RTL8821AE_HMC_M2_country_chplan_map; - hal_map_sz = RTL8821AE_HMC_M2_country_chplan_map_sz; + hal_map = RTL8821AE_HMC_M2_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8821AE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan); #elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AU) - hal_map = RTL8821AU_country_chplan_map; - hal_map_sz = RTL8821AU_country_chplan_map_sz; + hal_map = RTL8821AU_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8821AU_country_chplan_exc_map) / sizeof(struct country_chplan); #elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AENF_NGFF) - hal_map = RTL8812AENF_NGFF_country_chplan_map; - hal_map_sz = RTL8812AENF_NGFF_country_chplan_map_sz; + hal_map = RTL8812AENF_NGFF_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8812AENF_NGFF_country_chplan_exc_map) / sizeof(struct country_chplan); #elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AEBT_HMC) - hal_map = RTL8812AEBT_HMC_country_chplan_map; - hal_map_sz = RTL8812AEBT_HMC_country_chplan_map_sz; + hal_map = RTL8812AEBT_HMC_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8812AEBT_HMC_country_chplan_exc_map) / sizeof(struct country_chplan); #elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8188EE_HMC_M2) - hal_map = RTL8188EE_HMC_M2_country_chplan_map; - hal_map_sz = RTL8188EE_HMC_M2_country_chplan_map_sz; + hal_map = RTL8188EE_HMC_M2_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8188EE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan); #elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BE_HMC_M2) - hal_map = RTL8723BE_HMC_M2_country_chplan_map; - hal_map_sz = RTL8723BE_HMC_M2_country_chplan_map_sz; + hal_map = RTL8723BE_HMC_M2_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8723BE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan); #elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BS_NGFF1216) - hal_map = RTL8723BS_NGFF1216_country_chplan_map; - hal_map_sz = RTL8723BS_NGFF1216_country_chplan_map_sz; + hal_map = RTL8723BS_NGFF1216_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8723BS_NGFF1216_country_chplan_exc_map) / sizeof(struct country_chplan); #elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8192EEBT_HMC_M2) - hal_map = RTL8192EEBT_HMC_M2_country_chplan_map; - hal_map_sz = RTL8192EEBT_HMC_M2_country_chplan_map_sz; + hal_map = RTL8192EEBT_HMC_M2_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8192EEBT_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723DE_NGFF1630) + hal_map = RTL8723DE_NGFF1630_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8723DE_NGFF1630_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8822BE) + hal_map = RTL8822BE_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8822BE_country_chplan_exc_map) / sizeof(struct country_chplan); #endif if (hal_map == NULL || hal_map_sz == 0) @@ -506,238 +741,237 @@ static const struct country_chplan *rtw_def_module_get_chplan_from_country(const #endif /* CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP or RTW_DEF_MODULE_REGULATORY_CERT */ static const struct country_chplan country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AD", 0x26, 1, 0x00), /* Andorra */ - COUNTRY_CHPLAN_ENT("AE", 0x26, 1, 0xFB), /* United Arab Emirates */ - COUNTRY_CHPLAN_ENT("AF", 0x42, 1, 0x00), /* Afghanistan */ - COUNTRY_CHPLAN_ENT("AG", 0x30, 1, 0x00), /* Antigua & Barbuda */ - COUNTRY_CHPLAN_ENT("AI", 0x26, 1, 0x00), /* Anguilla(UK) */ - COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0xF1), /* Albania */ - COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0xB0), /* Armenia */ - COUNTRY_CHPLAN_ENT("AO", 0x26, 1, 0xE0), /* Angola */ - COUNTRY_CHPLAN_ENT("AQ", 0x26, 1, 0x00), /* Antarctica */ - COUNTRY_CHPLAN_ENT("AR", 0x57, 1, 0xF3), /* Argentina */ - COUNTRY_CHPLAN_ENT("AS", 0x34, 1, 0x00), /* American Samoa */ - COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0xFB), /* Austria */ - COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0xFB), /* Australia */ - COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0xB0), /* Aruba */ - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0xF1), /* Azerbaijan */ - COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0xF1), /* Bosnia & Herzegovina */ - COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0x50), /* Barbados */ - COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0xF1), /* Bangladesh */ - COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0xFB), /* Belgium */ - COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0xB0), /* Burkina Faso */ - COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0xF1), /* Bulgaria */ - COUNTRY_CHPLAN_ENT("BH", 0x47, 1, 0xF1), /* Bahrain */ - COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0xB0), /* Burundi */ - COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0xB0), /* Benin */ - COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0x10), /* Brunei */ - COUNTRY_CHPLAN_ENT("BO", 0x30, 1, 0xF1), /* Bolivia */ - COUNTRY_CHPLAN_ENT("BR", 0x34, 1, 0xF1), /* Brazil */ - COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0x20), /* Bahamas */ - COUNTRY_CHPLAN_ENT("BW", 0x26, 1, 0xF1), /* Botswana */ - COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0xF1), /* Belarus */ - COUNTRY_CHPLAN_ENT("BZ", 0x34, 1, 0x00), /* Belize */ - COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0xFB), /* Canada */ - COUNTRY_CHPLAN_ENT("CC", 0x26, 1, 0x00), /* Cocos (Keeling) Islands (Australia) */ - COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0xB0), /* Congo, Republic of the */ - COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0xB0), /* Central African Republic */ - COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0xB0), /* Congo, Democratic Republic of the. Zaire */ - COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0xFB), /* Switzerland */ - COUNTRY_CHPLAN_ENT("CI", 0x26, 1, 0xF1), /* Cote d'Ivoire */ - COUNTRY_CHPLAN_ENT("CK", 0x26, 1, 0x00), /* Cook Islands */ - COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0xF1), /* Chile */ - COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0xB0), /* Cameroon */ - COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0xFB), /* China */ - COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0xF1), /* Colombia */ - COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0xF1), /* Costa Rica */ - COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0xB0), /* Cape Verde */ - COUNTRY_CHPLAN_ENT("CX", 0x45, 1, 0x00), /* Christmas Island (Australia) */ - COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0xFB), /* Cyprus */ - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0xFB), /* Czech Republic */ - COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0xFB), /* Germany */ - COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0x80), /* Djibouti */ - COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0xFB), /* Denmark */ - COUNTRY_CHPLAN_ENT("DM", 0x34, 1, 0x00), /* Dominica */ - COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0xF1), /* Dominican Republic */ - COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0xF1), /* Algeria */ - COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0xF1), /* Ecuador */ - COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0xFB), /* Estonia */ - COUNTRY_CHPLAN_ENT("EG", 0x47, 0, 0xF1), /* Egypt */ - COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0x80), /* Western Sahara */ - COUNTRY_CHPLAN_ENT("ER", 0x26, 1, 0x00), /* Eritrea */ - COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0xFB), /* Spain, Canary Islands, Ceuta, Melilla */ - COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0xB0), /* Ethiopia */ - COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0xFB), /* Finland */ - COUNTRY_CHPLAN_ENT("FJ", 0x34, 1, 0x00), /* Fiji */ - COUNTRY_CHPLAN_ENT("FK", 0x26, 1, 0x00), /* Falkland Islands (Islas Malvinas) (UK) */ - COUNTRY_CHPLAN_ENT("FM", 0x34, 1, 0x00), /* Micronesia, Federated States of (USA) */ - COUNTRY_CHPLAN_ENT("FO", 0x26, 1, 0x00), /* Faroe Islands (Denmark) */ - COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0xFB), /* France */ - COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0xB0), /* Gabon */ - COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0xFB), /* Great Britain (United Kingdom; England) */ - COUNTRY_CHPLAN_ENT("GD", 0x34, 1, 0xB0), /* Grenada */ - COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0x00), /* Georgia */ - COUNTRY_CHPLAN_ENT("GF", 0x26, 1, 0x80), /* French Guiana */ - COUNTRY_CHPLAN_ENT("GG", 0x26, 1, 0x00), /* Guernsey (UK) */ - COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0xF1), /* Ghana */ - COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0x00), /* Gibraltar (UK) */ - COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0x00), /* Greenland (Denmark) */ - COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0xB0), /* Gambia */ - COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0x10), /* Guinea */ - COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0x00), /* Guadeloupe (France) */ - COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0xB0), /* Equatorial Guinea */ - COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0xFB), /* Greece */ - COUNTRY_CHPLAN_ENT("GS", 0x26, 1, 0x00), /* South Georgia and the Sandwich Islands (UK) */ - COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0xF1), /* Guatemala */ - COUNTRY_CHPLAN_ENT("GU", 0x34, 1, 0x00), /* Guam (USA) */ - COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0xB0), /* Guinea-Bissau */ - COUNTRY_CHPLAN_ENT("GY", 0x44, 1, 0x00), /* Guyana */ - COUNTRY_CHPLAN_ENT("HK", 0x26, 1, 0xFB), /* Hong Kong */ - COUNTRY_CHPLAN_ENT("HM", 0x45, 1, 0x00), /* Heard and McDonald Islands (Australia) */ - COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0xF1), /* Honduras */ - COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0xF9), /* Croatia */ - COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0x50), /* Haiti */ - COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0xFB), /* Hungary */ - COUNTRY_CHPLAN_ENT("ID", 0x54, 0, 0xF3), /* Indonesia */ - COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0xFB), /* Ireland */ - COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0xF1), /* Israel */ - COUNTRY_CHPLAN_ENT("IM", 0x26, 1, 0x00), /* Isle of Man (UK) */ - COUNTRY_CHPLAN_ENT("IN", 0x47, 1, 0xF1), /* India */ - COUNTRY_CHPLAN_ENT("IQ", 0x26, 1, 0x00), /* Iraq */ - COUNTRY_CHPLAN_ENT("IR", 0x26, 0, 0x00), /* Iran */ - COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0xFB), /* Iceland */ - COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0xFB), /* Italy */ - COUNTRY_CHPLAN_ENT("JE", 0x26, 1, 0x00), /* Jersey (UK) */ - COUNTRY_CHPLAN_ENT("JM", 0x51, 1, 0xF1), /* Jamaica */ - COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0xFB), /* Jordan */ - COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0xFF), /* Japan- Telec */ - COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0xF9), /* Kenya */ - COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0xF1), /* Kyrgyzstan */ - COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0xF1), /* Cambodia */ - COUNTRY_CHPLAN_ENT("KI", 0x26, 1, 0x00), /* Kiribati */ - COUNTRY_CHPLAN_ENT("KN", 0x34, 1, 0x00), /* Saint Kitts and Nevis */ - COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0xFB), /* South Korea */ - COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0xFB), /* Kuwait */ - COUNTRY_CHPLAN_ENT("KY", 0x34, 1, 0x00), /* Cayman Islands (UK) */ - COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0x00), /* Kazakhstan */ - COUNTRY_CHPLAN_ENT("LA", 0x26, 1, 0x00), /* Laos */ - COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0xF1), /* Lebanon */ - COUNTRY_CHPLAN_ENT("LC", 0x34, 1, 0x00), /* Saint Lucia */ - COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0xFB), /* Liechtenstein */ - COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0xF1), /* Sri Lanka */ - COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0xB0), /* Liberia */ - COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0xF1), /* Lesotho */ - COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0xFB), /* Lithuania */ - COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0xFB), /* Luxembourg */ - COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0xFB), /* Latvia */ - COUNTRY_CHPLAN_ENT("LY", 0x26, 1, 0x00), /* Libya */ - COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0xF1), /* Morocco */ - COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0xFB), /* Monaco */ - COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0xF1), /* Moldova */ - COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0xF1), /* Montenegro */ - COUNTRY_CHPLAN_ENT("MF", 0x34, 1, 0x00), /* Saint Martin */ - COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0x20), /* Madagascar */ - COUNTRY_CHPLAN_ENT("MH", 0x34, 1, 0x00), /* Marshall Islands (USA) */ - COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0xF1), /* Republic of Macedonia (FYROM) */ - COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0xB0), /* Mali */ - COUNTRY_CHPLAN_ENT("MM", 0x26, 1, 0x00), /* Burma (Myanmar) */ - COUNTRY_CHPLAN_ENT("MN", 0x26, 1, 0x00), /* Mongolia */ - COUNTRY_CHPLAN_ENT("MO", 0x26, 1, 0x00), /* Macau */ - COUNTRY_CHPLAN_ENT("MP", 0x34, 1, 0x00), /* Northern Mariana Islands (USA) */ - COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0x40), /* Martinique (France) */ - COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0xA0), /* Mauritania */ - COUNTRY_CHPLAN_ENT("MS", 0x26, 1, 0x00), /* Montserrat (UK) */ - COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0xFB), /* Malta */ - COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0xB0), /* Mauritius */ - COUNTRY_CHPLAN_ENT("MV", 0x26, 1, 0x00), /* Maldives */ - COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0xB0), /* Malawi */ - COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0xF1), /* Mexico */ - COUNTRY_CHPLAN_ENT("MY", 0x47, 1, 0xF1), /* Malaysia */ - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0xF1), /* Mozambique */ - COUNTRY_CHPLAN_ENT("NA", 0x26, 0, 0x00), /* Namibia */ - COUNTRY_CHPLAN_ENT("NC", 0x26, 1, 0x00), /* New Caledonia */ - COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0xB0), /* Niger */ - COUNTRY_CHPLAN_ENT("NF", 0x45, 1, 0x00), /* Norfolk Island (Australia) */ - COUNTRY_CHPLAN_ENT("NG", 0x50, 1, 0xF9), /* Nigeria */ - COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0xF1), /* Nicaragua */ - COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0xFB), /* Netherlands */ - COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0xFB), /* Norway */ - COUNTRY_CHPLAN_ENT("NP", 0x47, 1, 0xF0), /* Nepal */ - COUNTRY_CHPLAN_ENT("NR", 0x26, 1, 0x00), /* Nauru */ - COUNTRY_CHPLAN_ENT("NU", 0x45, 1, 0x00), /* Niue */ - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0xFB), /* New Zealand */ - COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0xF9), /* Oman */ - COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0xF1), /* Panama */ - COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0xF1), /* Peru */ - COUNTRY_CHPLAN_ENT("PF", 0x26, 1, 0x00), /* French Polynesia (France) */ - COUNTRY_CHPLAN_ENT("PG", 0x26, 1, 0xF1), /* Papua New Guinea */ - COUNTRY_CHPLAN_ENT("PH", 0x26, 1, 0xF1), /* Philippines */ - COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0xF1), /* Pakistan */ - COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0xFB), /* Poland */ - COUNTRY_CHPLAN_ENT("PM", 0x26, 1, 0x00), /* Saint Pierre and Miquelon (France) */ - COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0xF1), /* Puerto Rico */ - COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0xFB), /* Portugal */ - COUNTRY_CHPLAN_ENT("PW", 0x34, 1, 0x00), /* Palau */ - COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0xF1), /* Paraguay */ - COUNTRY_CHPLAN_ENT("QA", 0x51, 1, 0xF9), /* Qatar */ - COUNTRY_CHPLAN_ENT("RE", 0x26, 1, 0x00), /* Reunion (France) */ - COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0xF1), /* Romania */ - COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0xF1), /* Serbia, Kosovo */ - COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0xFB), /* Russia(fac/gost), Kaliningrad */ - COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0xB0), /* Rwanda */ - COUNTRY_CHPLAN_ENT("SA", 0x26, 1, 0xFB), /* Saudi Arabia */ - COUNTRY_CHPLAN_ENT("SB", 0x26, 1, 0x00), /* Solomon Islands */ - COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0x90), /* Seychelles */ - COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0xFB), /* Sweden */ - COUNTRY_CHPLAN_ENT("SG", 0x47, 1, 0xFB), /* Singapore */ - COUNTRY_CHPLAN_ENT("SH", 0x26, 1, 0x00), /* Saint Helena (UK) */ - COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0xFB), /* Slovenia */ - COUNTRY_CHPLAN_ENT("SJ", 0x26, 1, 0x00), /* Svalbard (Norway) */ - COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0xFB), /* Slovakia */ - COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0xB0), /* Sierra Leone */ - COUNTRY_CHPLAN_ENT("SM", 0x26, 1, 0x00), /* San Marino */ - COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0xF1), /* Senegal */ - COUNTRY_CHPLAN_ENT("SO", 0x26, 1, 0x00), /* Somalia */ - COUNTRY_CHPLAN_ENT("SR", 0x34, 1, 0x00), /* Suriname */ - COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0x80), /* Sao Tome and Principe */ - COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0xF1), /* El Salvador */ - COUNTRY_CHPLAN_ENT("SX", 0x34, 1, 0x00), /* Sint Marteen */ - COUNTRY_CHPLAN_ENT("SZ", 0x26, 1, 0x20), /* Swaziland */ - COUNTRY_CHPLAN_ENT("TC", 0x26, 1, 0x00), /* Turks and Caicos Islands (UK) */ - COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0xB0), /* Chad */ - COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0x80), /* French Southern and Antarctic Lands (FR Southern Territories) */ - COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0xB0), /* Togo */ - COUNTRY_CHPLAN_ENT("TH", 0x26, 1, 0xF1), /* Thailand */ - COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0x40), /* Tajikistan */ - COUNTRY_CHPLAN_ENT("TK", 0x45, 1, 0x00), /* Tokelau */ - COUNTRY_CHPLAN_ENT("TM", 0x26, 1, 0x00), /* Turkmenistan */ - COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0xF1), /* Tunisia */ - COUNTRY_CHPLAN_ENT("TO", 0x26, 1, 0x00), /* Tonga */ - COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0xF1), /* Turkey, Northern Cyprus */ - COUNTRY_CHPLAN_ENT("TT", 0x42, 1, 0xF1), /* Trinidad & Tobago */ - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0xFF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0xF0), /* Tanzania */ - COUNTRY_CHPLAN_ENT("UA", 0x26, 1, 0xFB), /* Ukraine */ - COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0xF1), /* Uganda */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0xFF), /* United States of America (USA) */ - COUNTRY_CHPLAN_ENT("UY", 0x34, 1, 0xF1), /* Uruguay */ - COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0xF0), /* Uzbekistan */ - COUNTRY_CHPLAN_ENT("VA", 0x26, 1, 0x00), /* Holy See (Vatican City) */ - COUNTRY_CHPLAN_ENT("VC", 0x34, 1, 0x10), /* Saint Vincent and the Grenadines */ - COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0xF1), /* Venezuela */ - COUNTRY_CHPLAN_ENT("VI", 0x34, 1, 0x00), /* United States Virgin Islands (USA) */ - COUNTRY_CHPLAN_ENT("VN", 0x26, 1, 0xF1), /* Vietnam */ - COUNTRY_CHPLAN_ENT("VU", 0x26, 1, 0x00), /* Vanuatu */ - COUNTRY_CHPLAN_ENT("WF", 0x26, 1, 0x00), /* Wallis and Futuna (France) */ - COUNTRY_CHPLAN_ENT("WS", 0x34, 1, 0x00), /* Samoa */ - COUNTRY_CHPLAN_ENT("YE", 0x26, 1, 0x40), /* Yemen */ - COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0x80), /* Mayotte (France) */ - COUNTRY_CHPLAN_ENT("ZA", 0x26, 1, 0xF1), /* South Africa */ - COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0xB0), /* Zambia */ - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0xF1), /* Zimbabwe */ -}; - -u16 const country_chplan_map_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan); + COUNTRY_CHPLAN_ENT("AD", 0x26, 1, 0x000), /* Andorra */ + COUNTRY_CHPLAN_ENT("AE", 0x26, 1, 0x3FB), /* United Arab Emirates */ + COUNTRY_CHPLAN_ENT("AF", 0x42, 1, 0x000), /* Afghanistan */ + COUNTRY_CHPLAN_ENT("AG", 0x26, 1, 0x000), /* Antigua & Barbuda */ + COUNTRY_CHPLAN_ENT("AI", 0x26, 1, 0x000), /* Anguilla(UK) */ + COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0x3F1), /* Albania */ + COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0x2B0), /* Armenia */ + COUNTRY_CHPLAN_ENT("AN", 0x26, 1, 0x3F1), /* Netherlands Antilles */ + COUNTRY_CHPLAN_ENT("AO", 0x47, 1, 0x2E0), /* Angola */ + COUNTRY_CHPLAN_ENT("AQ", 0x26, 1, 0x000), /* Antarctica */ + COUNTRY_CHPLAN_ENT("AR", 0x57, 1, 0x3F3), /* Argentina */ + COUNTRY_CHPLAN_ENT("AS", 0x34, 1, 0x000), /* American Samoa */ + COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0x3FB), /* Austria */ + COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0x3FB), /* Australia */ + COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0x0B0), /* Aruba */ + COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0x3F1), /* Azerbaijan */ + COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0x3F1), /* Bosnia & Herzegovina */ + COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0x250), /* Barbados */ + COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0x3F1), /* Bangladesh */ + COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0x3FB), /* Belgium */ + COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0x2B0), /* Burkina Faso */ + COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0x3F1), /* Bulgaria */ + COUNTRY_CHPLAN_ENT("BH", 0x47, 1, 0x3F1), /* Bahrain */ + COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0x2B0), /* Burundi */ + COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0x2B0), /* Benin */ + COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0x210), /* Brunei */ + COUNTRY_CHPLAN_ENT("BO", 0x73, 1, 0x3F1), /* Bolivia */ + COUNTRY_CHPLAN_ENT("BR", 0x34, 1, 0x3F1), /* Brazil */ + COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0x220), /* Bahamas */ + COUNTRY_CHPLAN_ENT("BW", 0x26, 1, 0x2F1), /* Botswana */ + COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0x3F1), /* Belarus */ + COUNTRY_CHPLAN_ENT("BZ", 0x34, 1, 0x000), /* Belize */ + COUNTRY_CHPLAN_ENT("CA", 0x2B, 1, 0x3FB), /* Canada */ + COUNTRY_CHPLAN_ENT("CC", 0x26, 1, 0x000), /* Cocos (Keeling) Islands (Australia) */ + COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0x2B0), /* Congo, Republic of the */ + COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0x2B0), /* Central African Republic */ + COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0x2B0), /* Congo, Democratic Republic of the. Zaire */ + COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0x3FB), /* Switzerland */ + COUNTRY_CHPLAN_ENT("CI", 0x26, 1, 0x3F1), /* Cote d'Ivoire */ + COUNTRY_CHPLAN_ENT("CK", 0x26, 1, 0x000), /* Cook Islands */ + COUNTRY_CHPLAN_ENT("CL", 0x73, 1, 0x3F1), /* Chile */ + COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0x2B0), /* Cameroon */ + COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0x3FB), /* China */ + COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0x3F1), /* Colombia */ + COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0x3F1), /* Costa Rica */ + COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0x2B0), /* Cape Verde */ + COUNTRY_CHPLAN_ENT("CX", 0x45, 1, 0x000), /* Christmas Island (Australia) */ + COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0x3FB), /* Cyprus */ + COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0x3FB), /* Czech Republic */ + COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0x3FB), /* Germany */ + COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0x280), /* Djibouti */ + COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0x3FB), /* Denmark */ + COUNTRY_CHPLAN_ENT("DM", 0x34, 1, 0x000), /* Dominica */ + COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0x3F1), /* Dominican Republic */ + COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0x3F1), /* Algeria */ + COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0x3F1), /* Ecuador */ + COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0x3FB), /* Estonia */ + COUNTRY_CHPLAN_ENT("EG", 0x47, 0, 0x3F1), /* Egypt */ + COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0x280), /* Western Sahara */ + COUNTRY_CHPLAN_ENT("ER", 0x26, 1, 0x000), /* Eritrea */ + COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0x3FB), /* Spain, Canary Islands, Ceuta, Melilla */ + COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0x0B0), /* Ethiopia */ + COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0x3FB), /* Finland */ + COUNTRY_CHPLAN_ENT("FJ", 0x34, 1, 0x200), /* Fiji */ + COUNTRY_CHPLAN_ENT("FK", 0x26, 1, 0x000), /* Falkland Islands (Islas Malvinas) (UK) */ + COUNTRY_CHPLAN_ENT("FM", 0x34, 1, 0x000), /* Micronesia, Federated States of (USA) */ + COUNTRY_CHPLAN_ENT("FO", 0x26, 1, 0x000), /* Faroe Islands (Denmark) */ + COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0x3FB), /* France */ + COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0x2B0), /* Gabon */ + COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0x3FB), /* Great Britain (United Kingdom; England) */ + COUNTRY_CHPLAN_ENT("GD", 0x34, 1, 0x0B0), /* Grenada */ + COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0x200), /* Georgia */ + COUNTRY_CHPLAN_ENT("GF", 0x26, 1, 0x080), /* French Guiana */ + COUNTRY_CHPLAN_ENT("GG", 0x26, 1, 0x000), /* Guernsey (UK) */ + COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0x3F1), /* Ghana */ + COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0x200), /* Gibraltar (UK) */ + COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0x200), /* Greenland (Denmark) */ + COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0x2B0), /* Gambia */ + COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0x210), /* Guinea */ + COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0x200), /* Guadeloupe (France) */ + COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0x2B0), /* Equatorial Guinea */ + COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0x3FB), /* Greece */ + COUNTRY_CHPLAN_ENT("GS", 0x26, 1, 0x000), /* South Georgia and the Sandwich Islands (UK) */ + COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0x3F1), /* Guatemala */ + COUNTRY_CHPLAN_ENT("GU", 0x34, 1, 0x200), /* Guam (USA) */ + COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0x2B0), /* Guinea-Bissau */ + COUNTRY_CHPLAN_ENT("GY", 0x44, 1, 0x000), /* Guyana */ + COUNTRY_CHPLAN_ENT("HK", 0x26, 1, 0x3FB), /* Hong Kong */ + COUNTRY_CHPLAN_ENT("HM", 0x45, 1, 0x000), /* Heard and McDonald Islands (Australia) */ + COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0x3F1), /* Honduras */ + COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0x3F9), /* Croatia */ + COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0x250), /* Haiti */ + COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0x3FB), /* Hungary */ + COUNTRY_CHPLAN_ENT("ID", 0x54, 0, 0x3F3), /* Indonesia */ + COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0x3FB), /* Ireland */ + COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0x3F1), /* Israel */ + COUNTRY_CHPLAN_ENT("IM", 0x26, 1, 0x000), /* Isle of Man (UK) */ + COUNTRY_CHPLAN_ENT("IN", 0x48, 1, 0x3F1), /* India */ + COUNTRY_CHPLAN_ENT("IQ", 0x26, 1, 0x000), /* Iraq */ + COUNTRY_CHPLAN_ENT("IR", 0x26, 0, 0x000), /* Iran */ + COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0x3FB), /* Iceland */ + COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0x3FB), /* Italy */ + COUNTRY_CHPLAN_ENT("JE", 0x26, 1, 0x000), /* Jersey (UK) */ + COUNTRY_CHPLAN_ENT("JM", 0x51, 1, 0x3F1), /* Jamaica */ + COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0x3FB), /* Jordan */ + COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0x3FF), /* Japan- Telec */ + COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0x3F9), /* Kenya */ + COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0x3F1), /* Kyrgyzstan */ + COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0x3F1), /* Cambodia */ + COUNTRY_CHPLAN_ENT("KI", 0x26, 1, 0x000), /* Kiribati */ + COUNTRY_CHPLAN_ENT("KN", 0x34, 1, 0x000), /* Saint Kitts and Nevis */ + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0x3FB), /* South Korea */ + COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0x3FB), /* Kuwait */ + COUNTRY_CHPLAN_ENT("KY", 0x34, 1, 0x000), /* Cayman Islands (UK) */ + COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0x300), /* Kazakhstan */ + COUNTRY_CHPLAN_ENT("LA", 0x26, 1, 0x000), /* Laos */ + COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0x3F1), /* Lebanon */ + COUNTRY_CHPLAN_ENT("LC", 0x34, 1, 0x000), /* Saint Lucia */ + COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0x3FB), /* Liechtenstein */ + COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0x3F1), /* Sri Lanka */ + COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0x2B0), /* Liberia */ + COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0x3F1), /* Lesotho */ + COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0x3FB), /* Lithuania */ + COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0x3FB), /* Luxembourg */ + COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0x3FB), /* Latvia */ + COUNTRY_CHPLAN_ENT("LY", 0x26, 1, 0x000), /* Libya */ + COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0x3F1), /* Morocco */ + COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0x3FB), /* Monaco */ + COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0x3F1), /* Moldova */ + COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0x3F1), /* Montenegro */ + COUNTRY_CHPLAN_ENT("MF", 0x34, 1, 0x000), /* Saint Martin */ + COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0x220), /* Madagascar */ + COUNTRY_CHPLAN_ENT("MH", 0x34, 1, 0x000), /* Marshall Islands (USA) */ + COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0x3F1), /* Republic of Macedonia (FYROM) */ + COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0x2B0), /* Mali */ + COUNTRY_CHPLAN_ENT("MM", 0x26, 1, 0x000), /* Burma (Myanmar) */ + COUNTRY_CHPLAN_ENT("MN", 0x26, 1, 0x000), /* Mongolia */ + COUNTRY_CHPLAN_ENT("MO", 0x26, 1, 0x200), /* Macau */ + COUNTRY_CHPLAN_ENT("MP", 0x34, 1, 0x000), /* Northern Mariana Islands (USA) */ + COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0x240), /* Martinique (France) */ + COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0x2A0), /* Mauritania */ + COUNTRY_CHPLAN_ENT("MS", 0x26, 1, 0x000), /* Montserrat (UK) */ + COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0x3FB), /* Malta */ + COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0x2B0), /* Mauritius */ + COUNTRY_CHPLAN_ENT("MV", 0x47, 1, 0x000), /* Maldives */ + COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0x2B0), /* Malawi */ + COUNTRY_CHPLAN_ENT("MX", 0x61, 1, 0x3F1), /* Mexico */ + COUNTRY_CHPLAN_ENT("MY", 0x63, 1, 0x3F1), /* Malaysia */ + COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0x3F1), /* Mozambique */ + COUNTRY_CHPLAN_ENT("NA", 0x26, 1, 0x300), /* Namibia */ + COUNTRY_CHPLAN_ENT("NC", 0x26, 1, 0x000), /* New Caledonia */ + COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0x2B0), /* Niger */ + COUNTRY_CHPLAN_ENT("NF", 0x45, 1, 0x000), /* Norfolk Island (Australia) */ + COUNTRY_CHPLAN_ENT("NG", 0x75, 1, 0x3F9), /* Nigeria */ + COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0x3F1), /* Nicaragua */ + COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0x3FB), /* Netherlands */ + COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0x3FB), /* Norway */ + COUNTRY_CHPLAN_ENT("NP", 0x47, 1, 0x2F0), /* Nepal */ + COUNTRY_CHPLAN_ENT("NR", 0x26, 1, 0x000), /* Nauru */ + COUNTRY_CHPLAN_ENT("NU", 0x45, 1, 0x000), /* Niue */ + COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0x3FB), /* New Zealand */ + COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0x3F9), /* Oman */ + COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0x3F1), /* Panama */ + COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0x3F1), /* Peru */ + COUNTRY_CHPLAN_ENT("PF", 0x26, 1, 0x000), /* French Polynesia (France) */ + COUNTRY_CHPLAN_ENT("PG", 0x26, 1, 0x3F1), /* Papua New Guinea */ + COUNTRY_CHPLAN_ENT("PH", 0x26, 1, 0x3F1), /* Philippines */ + COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0x3F1), /* Pakistan */ + COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0x3FB), /* Poland */ + COUNTRY_CHPLAN_ENT("PM", 0x26, 1, 0x000), /* Saint Pierre and Miquelon (France) */ + COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0x3F1), /* Puerto Rico */ + COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0x3FB), /* Portugal */ + COUNTRY_CHPLAN_ENT("PW", 0x34, 1, 0x000), /* Palau */ + COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0x3F1), /* Paraguay */ + COUNTRY_CHPLAN_ENT("QA", 0x51, 1, 0x3F9), /* Qatar */ + COUNTRY_CHPLAN_ENT("RE", 0x26, 1, 0x000), /* Reunion (France) */ + COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0x3F1), /* Romania */ + COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0x3F1), /* Serbia, Kosovo */ + COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0x3FB), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0x2B0), /* Rwanda */ + COUNTRY_CHPLAN_ENT("SA", 0x26, 1, 0x3FB), /* Saudi Arabia */ + COUNTRY_CHPLAN_ENT("SB", 0x26, 1, 0x000), /* Solomon Islands */ + COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0x290), /* Seychelles */ + COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0x3FB), /* Sweden */ + COUNTRY_CHPLAN_ENT("SG", 0x26, 1, 0x3FB), /* Singapore */ + COUNTRY_CHPLAN_ENT("SH", 0x26, 1, 0x000), /* Saint Helena (UK) */ + COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0x3FB), /* Slovenia */ + COUNTRY_CHPLAN_ENT("SJ", 0x26, 1, 0x000), /* Svalbard (Norway) */ + COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0x3FB), /* Slovakia */ + COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0x2B0), /* Sierra Leone */ + COUNTRY_CHPLAN_ENT("SM", 0x26, 1, 0x000), /* San Marino */ + COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0x3F1), /* Senegal */ + COUNTRY_CHPLAN_ENT("SO", 0x26, 1, 0x000), /* Somalia */ + COUNTRY_CHPLAN_ENT("SR", 0x74, 1, 0x000), /* Suriname */ + COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0x280), /* Sao Tome and Principe */ + COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0x3F1), /* El Salvador */ + COUNTRY_CHPLAN_ENT("SX", 0x34, 1, 0x000), /* Sint Marteen */ + COUNTRY_CHPLAN_ENT("SZ", 0x26, 1, 0x020), /* Swaziland */ + COUNTRY_CHPLAN_ENT("TC", 0x26, 1, 0x000), /* Turks and Caicos Islands (UK) */ + COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0x2B0), /* Chad */ + COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0x280), /* French Southern and Antarctic Lands (FR Southern Territories) */ + COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0x2B0), /* Togo */ + COUNTRY_CHPLAN_ENT("TH", 0x26, 1, 0x3F1), /* Thailand */ + COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0x240), /* Tajikistan */ + COUNTRY_CHPLAN_ENT("TK", 0x45, 1, 0x000), /* Tokelau */ + COUNTRY_CHPLAN_ENT("TM", 0x26, 1, 0x000), /* Turkmenistan */ + COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0x3F1), /* Tunisia */ + COUNTRY_CHPLAN_ENT("TO", 0x26, 1, 0x000), /* Tonga */ + COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0x3F1), /* Turkey, Northern Cyprus */ + COUNTRY_CHPLAN_ENT("TT", 0x42, 1, 0x3F1), /* Trinidad & Tobago */ + COUNTRY_CHPLAN_ENT("TW", 0x76, 1, 0x3FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0x2F0), /* Tanzania */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 1, 0x3FB), /* Ukraine */ + COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0x2F1), /* Uganda */ + COUNTRY_CHPLAN_ENT("US", 0x76, 1, 0x3FF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("UY", 0x30, 1, 0x3F1), /* Uruguay */ + COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0x2F0), /* Uzbekistan */ + COUNTRY_CHPLAN_ENT("VA", 0x26, 1, 0x000), /* Holy See (Vatican City) */ + COUNTRY_CHPLAN_ENT("VC", 0x34, 1, 0x010), /* Saint Vincent and the Grenadines */ + COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0x3F1), /* Venezuela */ + COUNTRY_CHPLAN_ENT("VI", 0x34, 1, 0x000), /* United States Virgin Islands (USA) */ + COUNTRY_CHPLAN_ENT("VN", 0x26, 1, 0x3F1), /* Vietnam */ + COUNTRY_CHPLAN_ENT("VU", 0x26, 1, 0x000), /* Vanuatu */ + COUNTRY_CHPLAN_ENT("WF", 0x26, 1, 0x000), /* Wallis and Futuna (France) */ + COUNTRY_CHPLAN_ENT("WS", 0x34, 1, 0x000), /* Samoa */ + COUNTRY_CHPLAN_ENT("YE", 0x26, 1, 0x040), /* Yemen */ + COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0x280), /* Mayotte (France) */ + COUNTRY_CHPLAN_ENT("ZA", 0x26, 1, 0x3F1), /* South Africa */ + COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0x2B0), /* Zambia */ + COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0x3F1), /* Zimbabwe */ +}; /* * rtw_get_chplan_from_country - @@ -745,7 +979,8 @@ u16 const country_chplan_map_sz = sizeof(country_chplan_map) / sizeof(struct cou * * Return pointer of struct country_chplan entry or NULL when unsupported country_code is given */ -const struct country_chplan *rtw_get_chplan_from_country(const char *country_code) { +const struct country_chplan *rtw_get_chplan_from_country(const char *country_code) +{ const struct country_chplan *ent = NULL; const struct country_chplan *map = NULL; u16 map_sz = 0; @@ -763,10 +998,10 @@ const struct country_chplan *rtw_get_chplan_from_country(const char *country_cod #ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP map = CUSTOMIZED_country_chplan_map; - map_sz = CUSTOMIZED_country_chplan_map_sz; + map_sz = sizeof(CUSTOMIZED_country_chplan_map) / sizeof(struct country_chplan); #else map = country_chplan_map; - map_sz = country_chplan_map_sz; + map_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan); #endif for (i = 0; i < map_sz; i++) { @@ -777,20 +1012,628 @@ const struct country_chplan *rtw_get_chplan_from_country(const char *country_cod } exit: -#if RTW_DEF_MODULE_REGULATORY_CERT + #if RTW_DEF_MODULE_REGULATORY_CERT if (ent && !(COUNTRY_CHPLAN_DEF_MODULE_FALGS(ent) & RTW_DEF_MODULE_REGULATORY_CERT)) ent = NULL; -#endif + #endif + + return ent; +} + +const char *const _regd_str[] = { + "NONE", + "FCC", + "MKK", + "ETSI", + "IC", + "KCC", + "WW", +}; + +#ifdef CONFIG_TXPWR_LIMIT +void _dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl) +{ + struct regd_exc_ent *ent; + _list *cur, *head; + + RTW_PRINT_SEL(sel, "regd_exc_num:%u\n", rfctl->regd_exc_num); + + if (!rfctl->regd_exc_num) + goto exit; + + RTW_PRINT_SEL(sel, "%-7s %-6s %-9s\n", "country", "domain", "regd_name"); + + head = &rfctl->reg_exc_list; + cur = get_next(head); + + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + u8 has_country; + + ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list); + cur = get_next(cur); + has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1; + + RTW_PRINT_SEL(sel, " %c%c 0x%02x %s\n" + , has_country ? ent->country[0] : '0' + , has_country ? ent->country[1] : '0' + , ent->domain + , ent->regd_name + ); + } + +exit: + return; +} + +inline void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl) +{ + _irqL irqL; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + _dump_regd_exc_list(sel, rfctl); + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); +} + +void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen) +{ + struct regd_exc_ent *ent; + _irqL irqL; + + if (!regd_name || !nlen) { + rtw_warn_on(1); + goto exit; + } + + ent = (struct regd_exc_ent *)rtw_zmalloc(sizeof(struct regd_exc_ent) + nlen + 1); + if (!ent) + goto exit; + + _rtw_init_listhead(&ent->list); + if (country) + _rtw_memcpy(ent->country, country, 2); + ent->domain = domain; + _rtw_memcpy(ent->regd_name, regd_name, nlen); + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + rtw_list_insert_tail(&ent->list, &rfctl->reg_exc_list); + rfctl->regd_exc_num++; + + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + +exit: + return; +} + +inline void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name) +{ + rtw_regd_exc_add_with_nlen(rfctl, country, domain, regd_name, strlen(regd_name)); +} + +struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain) +{ + struct regd_exc_ent *ent; + _list *cur, *head; + u8 match = 0; + + head = &rfctl->reg_exc_list; + cur = get_next(head); + + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + u8 has_country; + + ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list); + cur = get_next(cur); + has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1; + + /* entry has country condition to match */ + if (has_country) { + if (!country) + continue; + if (ent->country[0] != country[0] + || ent->country[1] != country[1]) + continue; + } + + /* entry has domain condition to match */ + if (ent->domain != 0xFF) { + if (domain == 0xFF) + continue; + if (ent->domain != domain) + continue; + } + + match = 1; + break; + } + +exit: + if (match) + return ent; + else + return NULL; +} + +inline struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain) +{ + struct regd_exc_ent *ent; + _irqL irqL; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + ent = _rtw_regd_exc_search(rfctl, country, domain); + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + return ent; +} + +void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl) +{ + struct regd_exc_ent *ent; + _irqL irqL; + _list *cur, *head; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + head = &rfctl->reg_exc_list; + cur = get_next(head); + + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list); + cur = get_next(cur); + rtw_list_delete(&ent->list); + rtw_mfree((u8 *)ent, sizeof(struct regd_exc_ent) + strlen(ent->regd_name) + 1); + } + rfctl->regd_exc_num = 0; + + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); +} + +void dump_txpwr_lmt(void *sel, _adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + _irqL irqL; + char fmt[16]; + s8 *lmt_idx = NULL; + int bw, band, ch_num, tlrs, ntx_idx, rs, i, path; + u8 ch, n, rfpath_num; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + _dump_regd_exc_list(sel, rfctl); + RTW_PRINT_SEL(sel, "\n"); + + if (!rfctl->txpwr_regd_num) + goto release_lock; + + lmt_idx = rtw_malloc(sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num); + if (!lmt_idx) { + RTW_ERR("%s alloc fail\n", __func__); + goto release_lock; + } + + RTW_PRINT_SEL(sel, "txpwr_lmt_2g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_2g_cck_ofdm_state); + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + RTW_PRINT_SEL(sel, "txpwr_lmt_5g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_5g_cck_ofdm_state); + RTW_PRINT_SEL(sel, "txpwr_lmt_5g_20_40_ref:0x%02x\n", rfctl->txpwr_lmt_5g_20_40_ref); + #endif + RTW_PRINT_SEL(sel, "\n"); + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; + + rfpath_num = (band == BAND_ON_2_4G ? hal_spec->rfpath_num_2g : hal_spec->rfpath_num_5g); + + for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) { + + if (bw >= CHANNEL_WIDTH_160) + break; + if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80) + break; + + if (band == BAND_ON_2_4G) + ch_num = CENTER_CH_2G_NUM; + else + ch_num = center_chs_5g_num(bw); + + if (ch_num == 0) { + rtw_warn_on(1); + break; + } + + for (tlrs = TXPWR_LMT_RS_CCK; tlrs < TXPWR_LMT_RS_NUM; tlrs++) { + + if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT) + continue; + if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK) + continue; + if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM)) + continue; + if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT) + continue; + if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + continue; + + for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { + struct txpwr_lmt_ent *ent; + _list *cur, *head; + + if (ntx_idx >= hal_spec->tx_nss_num) + continue; + + /* bypass CCK multi-TX is not defined */ + if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) { + if (band == BAND_ON_2_4G + && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx))) + continue; + } + + /* bypass OFDM multi-TX is not defined */ + if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) { + if (band == BAND_ON_2_4G + && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))) + continue; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (band == BAND_ON_5G + && !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))) + continue; + #endif + } + + /* bypass 5G 20M, 40M pure reference */ + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) { + if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) { + if (tlrs == TXPWR_LMT_RS_HT) + continue; + } else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) { + if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40) + continue; + } + } + #endif + + /* choose n-SS mapping rate section to get lmt diff value */ + if (tlrs == TXPWR_LMT_RS_CCK) + rs = CCK; + else if (tlrs == TXPWR_LMT_RS_OFDM) + rs = OFDM; + else if (tlrs == TXPWR_LMT_RS_HT) + rs = HT_1SS + ntx_idx; + else if (tlrs == TXPWR_LMT_RS_VHT) + rs = VHT_1SS + ntx_idx; + else { + RTW_ERR("%s invalid tlrs %u\n", __func__, tlrs); + continue; + } + + RTW_PRINT_SEL(sel, "[%s][%s][%s][%uT]\n" + , band_str(band) + , ch_width_str(bw) + , txpwr_lmt_rs_str(tlrs) + , ntx_idx + 1 + ); + + /* header for limit in db */ + RTW_PRINT_SEL(sel, "%3s ", "ch"); + + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + + sprintf(fmt, "%%%zus%%s ", strlen(ent->regd_name) < 4 ? 5 - strlen(ent->regd_name) : 1); + _RTW_PRINT_SEL(sel, fmt + , strcmp(ent->regd_name, rfctl->regd_name) == 0 ? "*" : "" + , ent->regd_name + ); + } + sprintf(fmt, "%%%zus%%s ", strlen(regd_str(TXPWR_LMT_WW)) < 4 ? 5 - strlen(regd_str(TXPWR_LMT_WW)) : 1); + _RTW_PRINT_SEL(sel, fmt + , strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? "*" : "" + , regd_str(TXPWR_LMT_WW) + ); + + /* header for limit offset */ + for (path = 0; path < RF_PATH_MAX; path++) { + if (path >= rfpath_num) + break; + _RTW_PRINT_SEL(sel, "|"); + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + _RTW_PRINT_SEL(sel, "%3c " + , strcmp(ent->regd_name, rfctl->regd_name) == 0 ? rf_path_char(path) : ' '); + } + _RTW_PRINT_SEL(sel, "%3c " + , strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? rf_path_char(path) : ' '); + } + _RTW_PRINT_SEL(sel, "\n"); + + for (n = 0; n < ch_num; n++) { + s8 lmt; + s8 lmt_offset; + u8 base; + + if (band == BAND_ON_2_4G) + ch = n + 1; + else + ch = center_chs_5g(bw, n); + + if (ch == 0) { + rtw_warn_on(1); + break; + } + + /* dump limit in db */ + RTW_PRINT_SEL(sel, "%3u ", ch); + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + lmt = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw, tlrs, ntx_idx, ch, 0); + if (lmt == MAX_POWER_INDEX) { + sprintf(fmt, "%%%zus ", strlen(ent->regd_name) >= 5 ? strlen(ent->regd_name) + 1 : 5); + _RTW_PRINT_SEL(sel, fmt, "NA"); + } else { + if (lmt % 2) { + sprintf(fmt, "%%%zud.5 ", strlen(ent->regd_name) >= 5 ? strlen(ent->regd_name) - 1 : 3); + _RTW_PRINT_SEL(sel, fmt, lmt / 2); + } else { + sprintf(fmt, "%%%zud ", strlen(ent->regd_name) >= 5 ? strlen(ent->regd_name) + 1 : 5); + _RTW_PRINT_SEL(sel, fmt, lmt / 2); + } + } + } + lmt = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw, tlrs, ntx_idx, ch, 0); + if (lmt == MAX_POWER_INDEX) { + sprintf(fmt, "%%%zus ", strlen(regd_str(TXPWR_LMT_WW)) >= 5 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 5); + _RTW_PRINT_SEL(sel, fmt, "NA"); + } else { + if (lmt % 2) { + sprintf(fmt, "%%%zud.5 ", strlen(regd_str(TXPWR_LMT_WW)) >= 5 ? strlen(regd_str(TXPWR_LMT_WW)) - 1 : 3); + _RTW_PRINT_SEL(sel, fmt, lmt / 2); + } else { + sprintf(fmt, "%%%zud ", strlen(regd_str(TXPWR_LMT_WW)) >= 5 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 5); + _RTW_PRINT_SEL(sel, fmt, lmt / 2); + } + } + + /* dump limit offset of each path */ + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (path >= rfpath_num) + break; + + base = PHY_GetTxPowerByRateBase(adapter, band, path, rs); + + _RTW_PRINT_SEL(sel, "|"); + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + i = 0; + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + lmt_offset = phy_get_txpwr_lmt(adapter, ent->regd_name, band, bw, path, rs, ntx_idx, ch, 0); + if (lmt_offset == MAX_POWER_INDEX) { + *(lmt_idx + i * RF_PATH_MAX + path) = MAX_POWER_INDEX; + _RTW_PRINT_SEL(sel, "%3s ", "NA"); + } else { + *(lmt_idx + i * RF_PATH_MAX + path) = lmt_offset + base; + _RTW_PRINT_SEL(sel, "%3d ", lmt_offset); + } + i++; + } + lmt_offset = phy_get_txpwr_lmt(adapter, regd_str(TXPWR_LMT_WW), band, bw, path, rs, ntx_idx, ch, 0); + if (lmt_offset == MAX_POWER_INDEX) + _RTW_PRINT_SEL(sel, "%3s ", "NA"); + else + _RTW_PRINT_SEL(sel, "%3d ", lmt_offset); + + } + + /* compare limit_idx of each path, print 'x' when mismatch */ + if (rfpath_num > 1) { + for (i = 0; i < rfctl->txpwr_regd_num; i++) { + for (path = 0; path < RF_PATH_MAX; path++) { + if (path >= rfpath_num) + break; + if (*(lmt_idx + i * RF_PATH_MAX + path) != *(lmt_idx + i * RF_PATH_MAX + ((path + 1) % rfpath_num))) + break; + } + if (path >= rfpath_num) + _RTW_PRINT_SEL(sel, " "); + else + _RTW_PRINT_SEL(sel, "x"); + } + } + _RTW_PRINT_SEL(sel, "\n"); + + } + RTW_PRINT_SEL(sel, "\n"); + } + } /* loop for rate sections */ + } /* loop for bandwidths */ + } /* loop for bands */ + + if (lmt_idx) + rtw_mfree(lmt_idx, sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num); + +release_lock: + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); +} + +/* search matcing first, if not found, alloc one */ +void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen + , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt) +{ + struct txpwr_lmt_ent *ent; + _irqL irqL; + _list *cur, *head; + s8 pre_lmt; + + if (!regd_name || !nlen) { + rtw_warn_on(1); + goto exit; + } + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + /* search for existed entry */ + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + + if (strlen(ent->regd_name) == nlen + && _rtw_memcmp(ent->regd_name, regd_name, nlen) == _TRUE) + goto chk_lmt_val; + } + + /* alloc new one */ + ent = (struct txpwr_lmt_ent *)rtw_zvmalloc(sizeof(struct txpwr_lmt_ent) + nlen + 1); + if (!ent) + goto release_lock; + + _rtw_init_listhead(&ent->list); + _rtw_memcpy(ent->regd_name, regd_name, nlen); + { + u8 j, k, l, m; + + for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j) + for (k = 0; k < TXPWR_LMT_RS_NUM_2G; ++k) + for (m = 0; m < CENTER_CH_2G_NUM; ++m) + for (l = 0; l < MAX_TX_COUNT; ++l) + ent->lmt_2g[j][k][m][l] = MAX_POWER_INDEX; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j) + for (k = 0; k < TXPWR_LMT_RS_NUM_5G; ++k) + for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m) + for (l = 0; l < MAX_TX_COUNT; ++l) + ent->lmt_5g[j][k][m][l] = MAX_POWER_INDEX; + #endif + } + + rtw_list_insert_tail(&ent->list, &rfctl->txpwr_lmt_list); + rfctl->txpwr_regd_num++; + +chk_lmt_val: + if (band == BAND_ON_2_4G) + pre_lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + else if (band == BAND_ON_5G) + pre_lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]; + #endif + else + goto release_lock; + + if (pre_lmt != MAX_POWER_INDEX) + RTW_PRINT("duplicate txpwr_lmt for [%s][%s][%s][%s][%uT][%d]\n" + , regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1 + , band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]); + + lmt = rtw_min(pre_lmt, lmt); + if (band == BAND_ON_2_4G) + ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] = lmt; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + else if (band == BAND_ON_5G) + ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] = lmt; + #endif + + if (0) + RTW_PRINT("%s, %4s, %6s, %7s, %uT, ch%3d = %d\n" + , regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1 + , band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx] + , lmt); + +release_lock: + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + +exit: + return; +} + +inline void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name + , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt) +{ + rtw_txpwr_lmt_add_with_nlen(rfctl, regd_name, strlen(regd_name) + , band, bw, tlrs, ntx_idx, ch_idx, lmt); +} + +struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name) +{ + struct txpwr_lmt_ent *ent; + _list *cur, *head; + u8 found = 0; + + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + + if (strcmp(ent->regd_name, regd_name) == 0) { + found = 1; + break; + } + } + + if (found) + return ent; + return NULL; +} + +inline struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name) +{ + struct txpwr_lmt_ent *ent; + _irqL irqL; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name); + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); return ent; } -int rtw_ch_to_bb_gain_sel(int ch) { +void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl) +{ + struct txpwr_lmt_ent *ent; + _irqL irqL; + _list *cur, *head; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + if (ent->regd_name == rfctl->regd_name) + rfctl->regd_name = regd_str(TXPWR_LMT_NONE); + rtw_list_delete(&ent->list); + rtw_vmfree((u8 *)ent, sizeof(struct txpwr_lmt_ent) + strlen(ent->regd_name) + 1); + } + rfctl->txpwr_regd_num = 0; + + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); +} +#endif /* CONFIG_TXPWR_LIMIT */ + +int rtw_ch_to_bb_gain_sel(int ch) +{ int sel = -1; if (ch >= 1 && ch <= 14) sel = BB_GAIN_2G; -#ifdef CONFIG_NL80211_BAND_5GHZ +#ifdef CONFIG_IEEE80211_BAND_5GHZ else if (ch >= 36 && ch < 48) sel = BB_GAIN_5GLB1; else if (ch >= 52 && ch <= 64) @@ -806,7 +1649,8 @@ int rtw_ch_to_bb_gain_sel(int ch) { return sel; } -s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch) { +s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch) +{ s8 kfree_offset = 0; #ifdef CONFIG_RF_POWER_TRIM @@ -821,49 +1665,71 @@ s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch) { if (kfree_data->flag & KFREE_FLAG_ON) { kfree_offset = kfree_data->bb_gain[bb_gain_sel][path]; - if (1) + if (IS_HARDWARE_TYPE_8723D(padapter)) + RTW_INFO("%s path:%s, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n" + , __func__, (path == 0)?"S1":"S0", + ch, bb_gain_sel, kfree_offset); + else RTW_INFO("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n" - , __func__, path, ch, bb_gain_sel, kfree_offset); + , __func__, path, ch, bb_gain_sel, kfree_offset); } exit: #endif /* CONFIG_RF_POWER_TRIM */ return kfree_offset; } -void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset) { +void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset) +{ u8 write_value; - - RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, path, 0x55, 0xffffffff)); + u8 target_path = 0; + u32 val32 = 0; + + if (IS_HARDWARE_TYPE_8723D(adapter)) { + target_path = RF_PATH_A; /*in 8723D case path means S0/S1*/ + if (path == PPG_8723D_S1) + RTW_INFO("kfree gain_offset 0x55:0x%x ", + rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff)); + else if (path == PPG_8723D_S0) + RTW_INFO("kfree gain_offset 0x65:0x%x ", + rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff)); + } else { + target_path = path; + RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff)); + } + switch (rtw_get_chip_type(adapter)) { #ifdef CONFIG_RTL8723D case RTL8723D: write_value = RF_TX_GAIN_OFFSET_8723D(offset); - rtw_hal_write_rfreg(adapter, path, 0x55, 0x0fc000, write_value); + if (path == PPG_8723D_S1) + rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value); + else if (path == PPG_8723D_S0) + rtw_hal_write_rfreg(adapter, target_path, 0x65, 0x0f8000, write_value); break; #endif /* CONFIG_RTL8723D */ #ifdef CONFIG_RTL8703B case RTL8703B: write_value = RF_TX_GAIN_OFFSET_8703B(offset); - rtw_hal_write_rfreg(adapter, path, 0x55, 0x0fc000, write_value); + rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value); break; #endif /* CONFIG_RTL8703B */ #ifdef CONFIG_RTL8188F case RTL8188F: write_value = RF_TX_GAIN_OFFSET_8188F(offset); - rtw_hal_write_rfreg(adapter, path, 0x55, 0x0fc000, write_value); + rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value); break; #endif /* CONFIG_RTL8188F */ #ifdef CONFIG_RTL8192E case RTL8192E: write_value = RF_TX_GAIN_OFFSET_8192E(offset); - rtw_hal_write_rfreg(adapter, path, 0x55, 0x0f8000, write_value); + rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value); break; #endif /* CONFIG_RTL8188F */ #ifdef CONFIG_RTL8821A case RTL8821: write_value = RF_TX_GAIN_OFFSET_8821A(offset); - rtw_hal_write_rfreg(adapter, path, 0x55, 0x0f8000, write_value); + rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value); break; #endif /* CONFIG_RTL8821A */ #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) @@ -878,42 +1744,98 @@ void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset) { rtw_warn_on(1); break; } - - RTW_INFO(" after :0x%x\n", rtw_hal_read_rfreg(adapter, path, 0x55, 0xffffffff)); + + if (IS_HARDWARE_TYPE_8723D(adapter)) { + if (path == PPG_8723D_S1) + val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff); + else if (path == PPG_8723D_S0) + val32 = rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff); + } else { + val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff); + } + RTW_INFO(" after :0x%x\n", val32); } -void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch) { +void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch) +{ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); s8 kfree_offset = 0; s8 tx_pwr_track_offset = 0; /* TODO: 8814A should consider tx pwr track when setting tx gain offset */ s8 total_offset; - int i; + int i, total = 0; - for (i = 0; i < hal_data->NumTotalRFPath; i++) { + if (IS_HARDWARE_TYPE_8723D(adapter)) + total = 2; /* S1 and S0 */ + else + total = hal_data->NumTotalRFPath; + + for (i = 0; i < total; i++) { kfree_offset = rtw_rf_get_kfree_tx_gain_offset(adapter, i, ch); total_offset = kfree_offset + tx_pwr_track_offset; rtw_rf_set_tx_gain_offset(adapter, i, total_offset); } } -bool rtw_is_dfs_range(u32 hi, u32 lo) { - return rtw_is_range_overlap(hi, lo, 5720 + 10, 5260 - 10) ? _TRUE : _FALSE; +inline u8 rtw_is_5g_band1(u8 ch) +{ + if (ch >= 36 && ch <= 48) + return 1; + return 0; +} + +inline u8 rtw_is_5g_band2(u8 ch) +{ + if (ch >= 52 && ch <= 64) + return 1; + return 0; +} + +inline u8 rtw_is_5g_band3(u8 ch) +{ + if (ch >= 100 && ch <= 144) + return 1; + return 0; } -bool rtw_is_dfs_ch(u8 ch, u8 bw, u8 offset) { +inline u8 rtw_is_5g_band4(u8 ch) +{ + if (ch >= 149 && ch <= 177) + return 1; + return 0; +} + +inline u8 rtw_is_dfs_range(u32 hi, u32 lo) +{ + return rtw_is_range_overlap(hi, lo, 5720 + 10, 5260 - 10); +} + +u8 rtw_is_dfs_ch(u8 ch) +{ u32 hi, lo; - if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) - return _FALSE; + if (!rtw_chbw_to_freq_range(ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, &hi, &lo)) + return 0; + + return rtw_is_dfs_range(hi, lo); +} + +u8 rtw_is_dfs_chbw(u8 ch, u8 bw, u8 offset) +{ + u32 hi, lo; + + if (!rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo)) + return 0; - return rtw_is_dfs_range(hi, lo) ? _TRUE : _FALSE; + return rtw_is_dfs_range(hi, lo); } -bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region) { +bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region) +{ return (dfs_region == PHYDM_DFS_DOMAIN_ETSI && rtw_is_range_overlap(hi, lo, 5660 + 10, 5600 - 10)) ? _TRUE : _FALSE; } -bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region) { +bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region) +{ u32 hi, lo; if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) diff --git a/core/rtw_sdio.c b/core/rtw_sdio.c index 63467bc..bf27f46 100644 --- a/core/rtw_sdio.c +++ b/core/rtw_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_SDIO_C_ #include /* struct dvobj_priv and etc. */ @@ -39,22 +35,61 @@ */ static u8 sdio_io(struct dvobj_priv *d, u32 addr, void *buf, size_t len, u8 write, u8 cmd52) { + u32 addr_drv; /* address with driver defined bit */ int err; + u8 retry = 0; + u8 stop_retry = _FALSE; /* flag for stopping retry or not */ - if (cmd52) - addr = RTW_SDIO_ADDR_CMD52_GEN(addr); - - if (write) - err = d->intf_ops->write(d, addr, buf, len, 0); - else - err = d->intf_ops->read(d, addr, buf, len, 0); - if (err) { - RTW_INFO("%s: [ERROR] %s FAIL! error(%d)\n", - __FUNCTION__, write ? "write" : "read", err); + if (rtw_is_surprise_removed(dvobj_get_primary_adapter(d))) { + RTW_ERR("%s: bSurpriseRemoved, skip %s 0x%05x, %zu bytes\n", + __FUNCTION__, write?"write":"read", addr, len); return _FAIL; } + addr_drv = addr; + if (cmd52) + addr_drv = RTW_SDIO_ADDR_CMD52_GEN(addr_drv); + + do { + if (write) + err = d->intf_ops->write(d, addr_drv, buf, len, 0); + else + err = d->intf_ops->read(d, addr_drv, buf, len, 0); + if (!err) { + if (retry) { + RTW_INFO("%s: Retry %s OK! addr=0x%05x %zu bytes, retry=%u,%u\n", + __FUNCTION__, write?"write":"read", + addr, len, retry, ATOMIC_READ(&d->continual_io_error)); + RTW_INFO_DUMP("Data: ", buf, len); + } + rtw_reset_continual_io_error(d); + break; + } + RTW_ERR("%s: %s FAIL! error(%d) addr=0x%05x %zu bytes, retry=%u,%u\n", + __FUNCTION__, write?"write":"read", err, addr, len, + retry, ATOMIC_READ(&d->continual_io_error)); + + retry++; + stop_retry = rtw_inc_and_chk_continual_io_error(d); + if ((err == -1) || (stop_retry == _TRUE) || (retry > SD_IO_TRY_CNT)) { + /* critical error, unrecoverable */ + RTW_ERR("%s: Fatal error! Set surprise remove flag ON! (retry=%u,%u)\n", + __FUNCTION__, retry, ATOMIC_READ(&d->continual_io_error)); + rtw_set_surprise_removed(dvobj_get_primary_adapter(d)); + return _FAIL; + } + + /* WLAN IOREG or SDIO Local */ + if ((addr & 0x10000) || !(addr & 0xE000)) { + RTW_WARN("%s: Retry %s addr=0x%05x %zu bytes, retry=%u,%u\n", + __FUNCTION__, write?"write":"read", addr, len, + retry, ATOMIC_READ(&d->continual_io_error)); + continue; + } + return _FAIL; + } while (1); + return _SUCCESS; } @@ -83,7 +118,6 @@ u8 rtw_sdio_f0_read(struct dvobj_priv *d, u32 addr, void *buf, size_t len) int err; u8 ret; - _func_enter_; ret = _SUCCESS; addr = RTW_SDIO_ADDR_F0_GEN(addr); @@ -94,7 +128,6 @@ u8 rtw_sdio_f0_read(struct dvobj_priv *d, u32 addr, void *buf, size_t len) ret = _FAIL; } - _func_exit_; return ret; } diff --git a/core/rtw_security.c b/core/rtw_security.c index 5a1d0cd..2206428 100644 --- a/core/rtw_security.c +++ b/core/rtw_security.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_SECURITY_C_ #include @@ -125,7 +120,6 @@ static void arcfour_init(struct arc4context *parc4ctx, u8 *key, u32 key_len) u32 stateindex; u8 *state; u32 counter; - _func_enter_; state = parc4ctx->state; parc4ctx->x = 0; parc4ctx->y = 0; @@ -142,7 +136,6 @@ static void arcfour_init(struct arc4context *parc4ctx, u8 *key, u32 key_len) if (++keyindex >= key_len) keyindex = 0; } - _func_exit_; } static u32 arcfour_byte(struct arc4context *parc4ctx) { @@ -150,7 +143,6 @@ static u32 arcfour_byte(struct arc4context *parc4ctx) u32 y; u32 sx, sy; u8 *state; - _func_enter_; state = parc4ctx->state; x = (parc4ctx->x + 1) & 0xff; sx = state[x]; @@ -160,7 +152,6 @@ static u32 arcfour_byte(struct arc4context *parc4ctx) parc4ctx->y = y; state[y] = (u8)sx; state[x] = (u8)sy; - _func_exit_; return state[(sx + sy) & 0xff]; } @@ -171,10 +162,8 @@ static void arcfour_encrypt(struct arc4context *parc4ctx, u32 len) { u32 i; - _func_enter_; for (i = 0; i < len; i++) dest[i] = src[i] ^ (unsigned char)arcfour_byte(parc4ctx); - _func_exit_; } static sint bcrc32initialized = 0; @@ -189,7 +178,6 @@ static u8 crc32_reverseBit(u8 data) static void crc32_init(void) { - _func_enter_; if (bcrc32initialized == 1) goto exit; else { @@ -214,14 +202,13 @@ static void crc32_init(void) bcrc32initialized = 1; } exit: - _func_exit_; + return; } static u32 getcrc32(u8 *buf, sint len) { u8 *p; u32 crc; - _func_enter_; if (bcrc32initialized == 0) crc32_init(); @@ -229,7 +216,6 @@ static u32 getcrc32(u8 *buf, sint len) for (p = buf; len > 0; ++p, --len) crc = crc32_table[(crc ^ *p) & 0xff] ^ (crc >> 8); - _func_exit_; return ~crc; /* transmit complement, per CRC-32 spec */ } @@ -254,7 +240,6 @@ void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe) struct security_priv *psecuritypriv = &padapter->securitypriv; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - _func_enter_; if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL) @@ -311,7 +296,6 @@ void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe) WEP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); } - _func_exit_; } @@ -327,7 +311,6 @@ void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe) struct rx_pkt_attrib *prxattrib = &(((union recv_frame *)precvframe)->u.hdr.attrib); struct security_priv *psecuritypriv = &padapter->securitypriv; - _func_enter_; pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data; @@ -351,16 +334,10 @@ void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe) /* calculate icv and compare the icv */ *((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4)); - if (crc[3] != payload[length - 1] || crc[2] != payload[length - 2] || crc[1] != payload[length - 3] || crc[0] != payload[length - 4]) { - RT_TRACE(_module_rtl871x_security_c_, _drv_err_, - ("rtw_wep_decrypt:icv error crc[3](%x)!=payload[length-1](%x) || crc[2](%x)!=payload[length-2](%x) || crc[1](%x)!=payload[length-3](%x) || crc[0](%x)!=payload[length-4](%x)\n", - crc[3], payload[length - 1], crc[2], payload[length - 2], crc[1], payload[length - 3], crc[0], payload[length - 4])); - } WEP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra); } - _func_exit_; return; @@ -373,10 +350,8 @@ static u32 secmicgetuint32(u8 *p) { s32 i; u32 res = 0; - _func_enter_; for (i = 0; i < 4; i++) res |= ((u32)(*p++)) << (8 * i); - _func_exit_; return res; } @@ -384,39 +359,32 @@ static void secmicputuint32(u8 *p, u32 val) /* Convert from Us4Byte32 to Byte[] in a portable way */ { long i; - _func_enter_; for (i = 0; i < 4; i++) { *p++ = (u8)(val & 0xff); val >>= 8; } - _func_exit_; } static void secmicclear(struct mic_data *pmicdata) { /* Reset the state to the empty message. */ - _func_enter_; pmicdata->L = pmicdata->K0; pmicdata->R = pmicdata->K1; pmicdata->nBytesInM = 0; pmicdata->M = 0; - _func_exit_; } void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key) { /* Set the key */ - _func_enter_; pmicdata->K0 = secmicgetuint32(key); pmicdata->K1 = secmicgetuint32(key + 4); /* and reset the message */ secmicclear(pmicdata); - _func_exit_; } void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b) { - _func_enter_; /* Append the byte to our word-sized buffer */ pmicdata->M |= ((unsigned long)b) << (8 * pmicdata->nBytesInM); pmicdata->nBytesInM++; @@ -435,23 +403,19 @@ void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b) pmicdata->M = 0; pmicdata->nBytesInM = 0; } - _func_exit_; } void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nbytes) { - _func_enter_; /* This is simple */ while (nbytes > 0) { rtw_secmicappendbyte(pmicdata, *src++); nbytes--; } - _func_exit_; } void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst) { - _func_enter_; /* Append the minimum padding */ rtw_secmicappendbyte(pmicdata, 0x5a); rtw_secmicappendbyte(pmicdata, 0); @@ -466,7 +430,6 @@ void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst) secmicputuint32(dst + 4, pmicdata->R); /* Reset to the empty message. */ secmicclear(pmicdata); - _func_exit_; } @@ -475,7 +438,6 @@ void rtw_seccalctkipmic(u8 *key, u8 *header, u8 *data, u32 data_len, u8 *mic_cod struct mic_data micdata; u8 priority[4] = {0x0, 0x0, 0x0, 0x0}; - _func_enter_; rtw_secmicsetkey(&micdata, key); priority[0] = pri; @@ -500,7 +462,6 @@ void rtw_seccalctkipmic(u8 *key, u8 *header, u8 *data, u32 data_len, u8 *mic_cod rtw_secmicappend(&micdata, data, data_len); rtw_secgetmic(&micdata, mic_code); - _func_exit_; } @@ -622,7 +583,6 @@ static const unsigned short Sbox1[2][256] = /* Sbox for hash (can be in ROM static void phase1(u16 *p1k, const u8 *tk, const u8 *ta, u32 iv32) { sint i; - _func_enter_; /* Initialize the 80 bits of P1K[] from IV32 and TA[0..5] */ p1k[0] = Lo16(iv32); p1k[1] = Hi16(iv32); @@ -641,7 +601,6 @@ static void phase1(u16 *p1k, const u8 *tk, const u8 *ta, u32 iv32) p1k[4] += _S_(p1k[3] ^ TK16((i & 1) + 0)); p1k[4] += (unsigned short)i; /* avoid "slide attacks" */ } - _func_exit_; } @@ -672,7 +631,6 @@ static void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16) { sint i; u16 PPK[6]; /* temporary key for mixing */ - _func_enter_; /* Note: all adds in the PPK[] equations below are mod 2**16 */ for (i = 0; i < 5; i++) PPK[i] = p1k[i]; /* first, copy P1K to PPK */ @@ -710,7 +668,6 @@ static void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16) rc4key[4 + 2 * i] = Lo8(PPK[i]); rc4key[5 + 2 * i] = Hi8(PPK[i]); } - _func_exit_; } @@ -735,7 +692,6 @@ u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe) struct security_priv *psecuritypriv = &padapter->securitypriv; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; u32 res = _SUCCESS; - _func_enter_; if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL) return _FAIL; @@ -775,7 +731,6 @@ u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe) return _FAIL; } */ - RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("rtw_tkip_encrypt: stainfo!=NULL!!!\n")); if (IS_MCAST(pattrib->ra)) prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; @@ -801,7 +756,6 @@ u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe) if ((curfragnum + 1) == pattrib->nr_frags) { /* 4 the last fragment */ length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; - RT_TRACE(_module_rtl871x_security_c_, _drv_info_, ("pattrib->iv_len =%x, pattrib->icv_len =%x\n", pattrib->iv_len, pattrib->icv_len)); *((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/ arcfour_init(&mycontext, rc4key, 16); @@ -825,14 +779,12 @@ u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe) } /* else{ - RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_encrypt: stainfo==NULL!!!\n")); RTW_INFO("%s, psta==NUL\n", __func__); res=_FAIL; } */ } - _func_exit_; return res; } @@ -859,7 +811,6 @@ u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe) /* struct recv_priv *precvpriv=&padapter->recvpriv; */ u32 res = _SUCCESS; - _func_enter_; pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data; @@ -934,20 +885,15 @@ u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe) *((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4)); if (crc[3] != payload[length - 1] || crc[2] != payload[length - 2] || crc[1] != payload[length - 3] || crc[0] != payload[length - 4]) { - RT_TRACE(_module_rtl871x_security_c_, _drv_err_, - ("rtw_wep_decrypt:icv error crc[3](%x)!=payload[length-1](%x) || crc[2](%x)!=payload[length-2](%x) || crc[1](%x)!=payload[length-3](%x) || crc[0](%x)!=payload[length-4](%x)\n", - crc[3], payload[length - 1], crc[2], payload[length - 2], crc[1], payload[length - 3], crc[0], payload[length - 4])); res = _FAIL; } TKIP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra); } else { - RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("rtw_tkip_decrypt: stainfo==NULL!!!\n")); res = _FAIL; } } - _func_exit_; exit: return res; @@ -1054,20 +1000,16 @@ static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext); static void xor_128(u8 *a, u8 *b, u8 *out) { sint i; - _func_enter_; for (i = 0; i < 16; i++) out[i] = a[i] ^ b[i]; - _func_exit_; } static void xor_32(u8 *a, u8 *b, u8 *out) { sint i; - _func_enter_; for (i = 0; i < 4; i++) out[i] = a[i] ^ b[i]; - _func_exit_; } @@ -1085,7 +1027,6 @@ static void next_key(u8 *key, sint round) 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x36, 0x36 }; - _func_enter_; sbox_key[0] = sbox(key[13]); sbox_key[1] = sbox(key[14]); sbox_key[2] = sbox(key[15]); @@ -1099,23 +1040,19 @@ static void next_key(u8 *key, sint round) xor_32(&key[4], &key[0], &key[4]); xor_32(&key[8], &key[4], &key[8]); xor_32(&key[12], &key[8], &key[12]); - _func_exit_; } static void byte_sub(u8 *in, u8 *out) { sint i; - _func_enter_; for (i = 0; i < 16; i++) out[i] = sbox(in[i]); - _func_exit_; } static void shift_row(u8 *in, u8 *out) { - _func_enter_; out[0] = in[0]; out[1] = in[5]; out[2] = in[10]; @@ -1132,7 +1069,6 @@ static void shift_row(u8 *in, u8 *out) out[13] = in[1]; out[14] = in[6]; out[15] = in[11]; - _func_exit_; } @@ -1147,7 +1083,6 @@ static void mix_column(u8 *in, u8 *out) u8 rotr[4]; u8 temp[4]; u8 tempb[4]; - _func_enter_; for (i = 0 ; i < 4; i++) { if ((in[i] & 0x80) == 0x80) add1b[i] = 0x1b; @@ -1191,7 +1126,6 @@ static void mix_column(u8 *in, u8 *out) xor_32(add1bf7, rotr, temp); xor_32(swap_halfs, rotl, tempb); xor_32(temp, tempb, out); - _func_exit_; } @@ -1202,7 +1136,6 @@ static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext) u8 intermediatea[16]; u8 intermediateb[16]; u8 round_key[16]; - _func_enter_; for (i = 0; i < 16; i++) round_key[i] = key[i]; @@ -1225,7 +1158,6 @@ static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext) next_key(round_key, round); } } - _func_exit_; } @@ -1246,7 +1178,6 @@ static void construct_mic_iv( ) { sint i; - _func_enter_; mic_iv[0] = 0x59; if (qc_exists && a4_exists) mic_iv[1] = mpdu[30] & 0x0f; /* QoS_TC */ @@ -1270,7 +1201,6 @@ static void construct_mic_iv( #endif mic_iv[14] = (unsigned char)(payload_length / 256); mic_iv[15] = (unsigned char)(payload_length % 256); - _func_exit_; } @@ -1287,7 +1217,6 @@ static void construct_mic_header1( uint frtype/* add for CONFIG_IEEE80211W, none 11w also can use */ ) { - _func_enter_; mic_header1[0] = (u8)((header_length - 2) / 256); mic_header1[1] = (u8)((header_length - 2) % 256); #ifdef CONFIG_IEEE80211W @@ -1311,7 +1240,6 @@ static void construct_mic_header1( mic_header1[13] = mpdu[13]; mic_header1[14] = mpdu[14]; mic_header1[15] = mpdu[15]; - _func_exit_; } @@ -1328,7 +1256,6 @@ static void construct_mic_header2( ) { sint i; - _func_enter_; for (i = 0; i < 16; i++) mic_header2[i] = 0x00; @@ -1363,7 +1290,6 @@ static void construct_mic_header2( mic_header2[15] = mpdu[31] & 0x00; } - _func_exit_; } @@ -1385,7 +1311,6 @@ static void construct_ctr_preload( ) { sint i = 0; - _func_enter_; for (i = 0; i < 16; i++) ctr_preload[i] = 0x00; i = 0; @@ -1411,7 +1336,6 @@ static void construct_ctr_preload( #endif ctr_preload[14] = (unsigned char)(c / 256); /* Ctr */ ctr_preload[15] = (unsigned char)(c % 256); - _func_exit_; } @@ -1422,10 +1346,8 @@ static void construct_ctr_preload( static void bitwise_xor(u8 *ina, u8 *inb, u8 *out) { sint i; - _func_enter_; for (i = 0; i < 16; i++) out[i] = ina[i] ^ inb[i]; - _func_exit_; } @@ -1449,9 +1371,8 @@ static sint aes_cipher(u8 *key, uint hdrlen, u8 mic[8]; /* uint offset = 0; */ uint frtype = GetFrameType(pframe); - uint frsubtype = GetFrameSubType(pframe); + uint frsubtype = get_frame_sub_type(pframe); - _func_enter_; frsubtype = frsubtype >> 4; @@ -1618,7 +1539,6 @@ static sint aes_cipher(u8 *key, uint hdrlen, bitwise_xor(aes_out, padded_buffer, chain_buffer); for (j = 0; j < 8; j++) pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<8;j++) message[payload_index++] = chain_buffer[j]; */ - _func_exit_; return _SUCCESS; } @@ -1646,7 +1566,6 @@ u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe) /* uint offset = 0; */ u32 res = _SUCCESS; - _func_enter_; if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL) return _FAIL; @@ -1686,7 +1605,6 @@ u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe) return _FAIL; } */ - RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("rtw_aes_encrypt: stainfo!=NULL!!!\n")); if (IS_MCAST(pattrib->ra)) prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; @@ -1729,7 +1647,6 @@ u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe) } /* else{ - RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo==NULL!!!\n")); RTW_INFO("%s, psta==NUL\n", __func__); res=_FAIL; } @@ -1738,7 +1655,6 @@ u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe) - _func_exit_; return res; } @@ -1764,8 +1680,7 @@ static sint aes_decipher(u8 *key, uint hdrlen, /* uint offset = 0; */ uint frtype = GetFrameType(pframe); - uint frsubtype = GetFrameSubType(pframe); - _func_enter_; + uint frsubtype = get_frame_sub_type(pframe); frsubtype = frsubtype >> 4; @@ -1997,14 +1912,11 @@ static sint aes_decipher(u8 *key, uint hdrlen, /* compare the mic */ for (i = 0; i < 8; i++) { if (pframe[hdrlen + 8 + plen - 8 + i] != message[hdrlen + 8 + plen - 8 + i]) { - RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("aes_decipher:mic check error mic[%d]: pframe(%x) != message(%x)\n", - i, pframe[hdrlen + 8 + plen - 8 + i], message[hdrlen + 8 + plen - 8 + i])); RTW_INFO("aes_decipher:mic check error mic[%d]: pframe(%x) != message(%x)\n", i, pframe[hdrlen + 8 + plen - 8 + i], message[hdrlen + 8 + plen - 8 + i]); res = _FAIL; } } - _func_exit_; return res; } @@ -2028,14 +1940,12 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe) struct security_priv *psecuritypriv = &padapter->securitypriv; /* struct recv_priv *precvpriv=&padapter->recvpriv; */ u32 res = _SUCCESS; - _func_enter_; pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data; /* 4 start to encrypt each fragment */ if ((prxattrib->encrypt == _AES_)) { stainfo = rtw_get_stainfo(&padapter->stapriv , &prxattrib->ta[0]); if (stainfo != NULL) { - RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("rtw_aes_decrypt: stainfo!=NULL!!!\n")); if (IS_MCAST(prxattrib->ra)) { static u32 start = 0; @@ -2078,7 +1988,7 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe) prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) { - RTW_INFO("not match packet_index=%d, install_index=%d\n" + RTW_DBG("not match packet_index=%d, install_index=%d\n" , prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid); res = _FAIL; goto exit; @@ -2114,12 +2024,10 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe) AES_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra); } else { - RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("rtw_aes_decrypt: stainfo==NULL!!!\n")); res = _FAIL; } } - _func_exit_; exit: return res; } @@ -2297,7 +2205,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in, unsigned long n; #define block_size 64 - if (md->curlen > sizeof(md->buf)) + if (md->curlen >= sizeof(md->buf)) return -1; while (inlen > 0) { @@ -3158,32 +3066,6 @@ int tdls_verify_mic(u8 *kck, u8 trans_seq, } #endif /* CONFIG_TDLS */ -void rtw_use_tkipkey_handler(RTW_TIMER_HDL_ARGS) -{ - _adapter *padapter = (_adapter *)FunctionContext; - - _func_enter_; - - RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("^^^rtw_use_tkipkey_handler ^^^\n")); - - /* - if (RTW_CANNOT_RUN(padapter)) { - RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler (padapter->bDriverStopped %s)(padapter->bSurpriseRemoved %s)^^^\n" - , rtw_is_drv_stopped(padapter)?"True":"False" - , rtw_is_surprise_removed(padapter)?"True":"False")); - - return; - } - */ - - padapter->securitypriv.busetkipkey = _TRUE; - - RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("^^^rtw_use_tkipkey_handler padapter->securitypriv.busetkipkey=%d^^^\n", padapter->securitypriv.busetkipkey)); - - _func_exit_; - -} - /* Restore HW wep key setting according to key_mask */ void rtw_sec_restore_wep_key(_adapter *adapter) { diff --git a/core/rtw_sreset.c b/core/rtw_sreset.c index 00f81d9..6baacb7 100644 --- a/core/rtw_sreset.c +++ b/core/rtw_sreset.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #include @@ -273,7 +268,7 @@ void sreset_stop_adapter(_adapter *padapter) if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) { rtw_set_to_roam(padapter, 0); - _rtw_join_timeout_handler(padapter); + rtw_join_timeout_handler(padapter); } } @@ -297,7 +292,7 @@ void sreset_start_adapter(_adapter *padapter) #endif if (is_primary_adapter(padapter)) - _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); + _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); rtw_netif_wake_queue(padapter->pnetdev); } diff --git a/core/rtw_sta_mgt.c b/core/rtw_sta_mgt.c index dd9978a..4bd110a 100644 --- a/core/rtw_sta_mgt.c +++ b/core/rtw_sta_mgt.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_STA_MGT_C_ #include @@ -166,7 +161,6 @@ void _rtw_init_stainfo(struct sta_info *psta); void _rtw_init_stainfo(struct sta_info *psta) { - _func_enter_; _rtw_memset((u8 *)psta, 0, sizeof(struct sta_info)); @@ -197,6 +191,9 @@ void _rtw_init_stainfo(struct sta_info *psta) psta->bpairwise_key_installed = _FALSE; +#ifdef CONFIG_RTW_80211R + psta->ft_pairwise_key_installed = _FALSE; +#endif #ifdef CONFIG_NATIVEAP_MLME psta->nonerp_set = 0; @@ -218,7 +215,6 @@ void _rtw_init_stainfo(struct sta_info *psta) rtw_st_ctl_init(&psta->st_ctl); - _func_exit_; } @@ -227,7 +223,6 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) struct sta_info *psta; s32 i; - _func_enter_; pstapriv->pallocated_stainfo_buf = rtw_zvmalloc(sizeof(struct sta_info) * NUM_STA + 4); @@ -293,7 +288,9 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) _rtw_init_queue(&(pstapriv->acl_list.acl_node_q)); #endif - _func_exit_; +#if CONFIG_RTW_PRE_LINK_STA + rtw_pre_link_sta_ctl_init(pstapriv); +#endif return _SUCCESS; @@ -320,7 +317,6 @@ inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv); void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv) { - _func_enter_; _rtw_spinlock_free(&psta_xmitpriv->lock); @@ -328,25 +324,21 @@ void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv) _rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock)); _rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock)); _rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock)); - _func_exit_; } static void _rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv) { - _func_enter_; _rtw_spinlock_free(&psta_recvpriv->lock); _rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock)); - _func_exit_; } void rtw_mfree_stainfo(struct sta_info *psta); void rtw_mfree_stainfo(struct sta_info *psta) { - _func_enter_; if (&psta->lock != NULL) _rtw_spinlock_free(&psta->lock); @@ -354,7 +346,6 @@ void rtw_mfree_stainfo(struct sta_info *psta) _rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv); _rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv); - _func_exit_; } @@ -366,7 +357,6 @@ void rtw_mfree_all_stainfo(struct sta_priv *pstapriv) _list *plist, *phead; struct sta_info *psta = NULL; - _func_enter_; _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); @@ -382,7 +372,6 @@ void rtw_mfree_all_stainfo(struct sta_priv *pstapriv) _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); - _func_exit_; } @@ -412,7 +401,6 @@ u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) struct recv_reorder_ctrl *preorder_ctrl; int index; - _func_enter_; if (pstapriv) { /* delete all reordering_ctrl_timer */ @@ -441,15 +429,26 @@ u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) _rtw_deinit_queue(&(pstapriv->acl_list.acl_node_q)); #endif +#if CONFIG_RTW_PRE_LINK_STA + rtw_pre_link_sta_ctl_deinit(pstapriv); +#endif + if (pstapriv->pallocated_stainfo_buf) rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info) * NUM_STA + 4); } - _func_exit_; return _SUCCESS; } +static void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl) +{ + _adapter *padapter = preorder_ctrl->padapter; + + rtw_init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter, rtw_reordering_ctrl_timeout_handler, preorder_ctrl); + +} + /* struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) */ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) { @@ -463,7 +462,6 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) int i = 0; u16 wRxSeqInitialValue = 0xffff; - _func_enter_; pfree_sta_queue = &pstapriv->free_sta_queue; @@ -490,10 +488,8 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) index = wifi_mac_hash(hwaddr); - RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_info_, ("rtw_alloc_stainfo: index = %x", index)); if (index >= NUM_STA) { - RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_err_, ("ERROR=> rtw_alloc_stainfo: index >= NUM_STA")); psta = NULL; goto exit; } @@ -515,12 +511,9 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) for (i = 0; i < 16; i++) _rtw_memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2); - RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_info_, ("alloc number_%d stainfo with hwaddr = %x %x %x %x %x %x\n", - pstapriv->asoc_sta_count , hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5])); - - init_addba_retry_timer(pstapriv->padapter, psta); + rtw_init_timer(&psta->addba_retry_timer, psta->padapter, addba_timer_hdl, psta); #ifdef CONFIG_IEEE80211W - init_dot11w_expire_timer(pstapriv->padapter, psta); + rtw_init_timer(&psta->dot11w_expire_timer, psta->padapter, sa_query_timer_hdl, psta); #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_TDLS rtw_init_tdls_timer(pstapriv->padapter, psta); @@ -551,8 +544,8 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) /* init for DM */ - psta->rssi_stat.UndecoratedSmoothedPWDB = (-1); - psta->rssi_stat.UndecoratedSmoothedCCK = (-1); + psta->rssi_stat.undecorated_smoothed_pwdb = (-1); + psta->rssi_stat.undecorated_smoothed_cck = (-1); #ifdef CONFIG_ATMEL_RC_PATCH psta->flag_atmel_rc = 0; #endif @@ -568,11 +561,11 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); - _func_exit_; - - return psta; + if (psta) + rtw_mi_update_iface_status(&(pstapriv->padapter->mlmepriv), 0); + return psta; } @@ -588,19 +581,24 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) struct sta_priv *pstapriv = &padapter->stapriv; struct hw_xmit *phwxmit; int pending_qcnt[4]; - - _func_enter_; + u8 is_pre_link_sta = _FALSE; if (psta == NULL) goto exit; - _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); - rtw_list_delete(&psta->hash_list); - RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_err_, ("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x\n", pstapriv->asoc_sta_count , psta->hwaddr[0], - psta->hwaddr[1], psta->hwaddr[2], psta->hwaddr[3], psta->hwaddr[4], psta->hwaddr[5])); - pstapriv->asoc_sta_count--; - _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + is_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->hwaddr); + if (is_pre_link_sta == _FALSE) { + _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + rtw_list_delete(&psta->hash_list); + pstapriv->asoc_sta_count--; + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + rtw_mi_update_iface_status(&(padapter->mlmepriv), 0); + } else { + _enter_critical_bh(&psta->lock, &irqL0); + psta->state = WIFI_FW_PRE_LINK; + _exit_critical_bh(&psta->lock, &irqL0); + } _enter_critical_bh(&psta->lock, &irqL0); psta->state &= ~_FW_LINKED; @@ -712,12 +710,13 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) } - if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->hwaddr))) + if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->hwaddr)) && is_pre_link_sta == _FALSE) rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE); /* release mac id for non-bc/mc station, */ - rtw_release_macid(pstapriv->padapter, psta); + if (is_pre_link_sta == _FALSE) + rtw_release_macid(pstapriv->padapter, psta); #ifdef CONFIG_AP_MODE @@ -770,20 +769,18 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) rtw_st_ctl_deinit(&psta->st_ctl); - _rtw_spinlock_free(&psta->lock); + if (is_pre_link_sta == _FALSE) { + _rtw_spinlock_free(&psta->lock); - /* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); */ - _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); - rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue)); - _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); - /* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); */ + /* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); */ + _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue)); + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + /* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); */ + } exit: - - _func_exit_; - return _SUCCESS; - } /* free all stainfo which in sta_hash[all] */ @@ -799,7 +796,6 @@ void rtw_free_all_stainfo(_adapter *padapter) char free_sta_list[NUM_STA]; int stainfo_offset; - _func_enter_; if (pstapriv->asoc_sta_count == 1) goto exit; @@ -816,8 +812,9 @@ void rtw_free_all_stainfo(_adapter *padapter) plist = get_next(plist); if (pbcmc_stainfo != psta) { - rtw_list_delete(&psta->hash_list); - /* rtw_free_stainfo(padapter , psta); */ + if (rtw_is_pre_link_sta(pstapriv, psta->hwaddr) == _FALSE) + rtw_list_delete(&psta->hash_list); + stainfo_offset = rtw_stainfo_offset(pstapriv, psta); if (stainfo_offset_valid(stainfo_offset)) free_sta_list[free_sta_num++] = stainfo_offset; @@ -835,9 +832,7 @@ void rtw_free_all_stainfo(_adapter *padapter) } exit: - - _func_exit_; - + return; } /* any station allocated can be searched by hash list */ @@ -856,7 +851,6 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - _func_enter_; if (hwaddr == NULL) return NULL; @@ -887,7 +881,6 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) } _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); - _func_exit_; return psta; } @@ -903,13 +896,11 @@ u32 rtw_init_bcmc_stainfo(_adapter *padapter) struct sta_priv *pstapriv = &padapter->stapriv; /* _queue *pstapending = &padapter->xmitpriv.bm_pending; */ - _func_enter_; psta = rtw_alloc_stainfo(pstapriv, bcast_addr); if (psta == NULL) { res = _FAIL; - RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_err_, ("rtw_alloc_stainfo fail")); goto exit; } #ifdef CONFIG_BEAMFORMING @@ -928,7 +919,6 @@ u32 rtw_init_bcmc_stainfo(_adapter *padapter) */ exit: - _func_exit_; return _SUCCESS; } @@ -939,14 +929,18 @@ struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter) struct sta_info *psta; struct sta_priv *pstapriv = &padapter->stapriv; u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - _func_enter_; psta = rtw_get_stainfo(pstapriv, bc_addr); - _func_exit_; return psta; } #if CONFIG_RTW_MACADDR_ACL +const char *const _acl_mode_str[] = { + "DISABLED", + "ACCEPT_UNLESS_LISTED", + "DENY_UNLESS_LISTED", +}; + u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr) { u8 res = _TRUE; @@ -983,4 +977,212 @@ u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr) return res; } + +void dump_macaddr_acl(void *sel, _adapter *adapter) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct wlan_acl_pool *acl = &stapriv->acl_list; + int i; + + RTW_PRINT_SEL(sel, "mode:%s(%d)\n", acl_mode_str(acl->mode), acl->mode); + RTW_PRINT_SEL(sel, "num:%d/%d\n", acl->num, NUM_ACL); + for (i = 0; i < NUM_ACL; i++) { + if (acl->aclnode[i].valid == _FALSE) + continue; + RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(acl->aclnode[i].addr)); + } +} #endif /* CONFIG_RTW_MACADDR_ACL */ + +bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr) +{ +#if CONFIG_RTW_PRE_LINK_STA + struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl; + struct sta_info *sta = NULL; + u8 exist = _FALSE; + int i; + _irqL irqL; + + _enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) { + if (pre_link_sta_ctl->node[i].valid == _TRUE + && _rtw_memcmp(pre_link_sta_ctl->node[i].addr, addr, ETH_ALEN) == _TRUE + ) { + exist = _TRUE; + break; + } + } + _exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + + return exist; +#else + return _FALSE; +#endif +} + +#if CONFIG_RTW_PRE_LINK_STA +struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr) +{ + struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl; + struct pre_link_sta_node_t *node = NULL; + struct sta_info *sta = NULL; + u8 exist = _FALSE; + int i; + _irqL irqL; + + if (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE) + goto exit; + + _enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) { + if (pre_link_sta_ctl->node[i].valid == _TRUE + && _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE + ) { + node = &pre_link_sta_ctl->node[i]; + exist = _TRUE; + break; + } + + if (node == NULL && pre_link_sta_ctl->node[i].valid == _FALSE) + node = &pre_link_sta_ctl->node[i]; + } + + if (exist == _FALSE && node) { + _rtw_memcpy(node->addr, hwaddr, ETH_ALEN); + node->valid = _TRUE; + pre_link_sta_ctl->num++; + } + _exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + + if (node == NULL) + goto exit; + + sta = rtw_get_stainfo(stapriv, hwaddr); + if (sta) + goto odm_hook; + + sta = rtw_alloc_stainfo(stapriv, hwaddr); + if (!sta) + goto exit; + + sta->state = WIFI_FW_PRE_LINK; + +odm_hook: + rtw_hal_set_odm_var(stapriv->padapter, HAL_ODM_STA_INFO, sta, _TRUE); + +exit: + return sta; +} + +void rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr) +{ + struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl; + struct pre_link_sta_node_t *node = NULL; + struct sta_info *sta = NULL; + u8 exist = _FALSE; + int i; + _irqL irqL; + + if (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE) + goto exit; + + _enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) { + if (pre_link_sta_ctl->node[i].valid == _TRUE + && _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE + ) { + node = &pre_link_sta_ctl->node[i]; + exist = _TRUE; + break; + } + } + + if (exist == _TRUE && node) { + node->valid = _FALSE; + pre_link_sta_ctl->num--; + } + _exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + + if (exist == _FALSE) + goto exit; + + sta = rtw_get_stainfo(stapriv, hwaddr); + if (!sta) + goto exit; + + if (sta->state == WIFI_FW_PRE_LINK) + rtw_free_stainfo(stapriv->padapter, sta); + +exit: + return; +} + +void rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv) +{ + struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl; + struct pre_link_sta_node_t *node = NULL; + struct sta_info *sta = NULL; + int i, j = 0; + _irqL irqL; + + u8 addrs[RTW_PRE_LINK_STA_NUM][ETH_ALEN]; + + _rtw_memset(addrs, 0, RTW_PRE_LINK_STA_NUM * ETH_ALEN); + + _enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) { + if (pre_link_sta_ctl->node[i].valid == _FALSE) + continue; + _rtw_memcpy(&(addrs[j][0]), pre_link_sta_ctl->node[i].addr, ETH_ALEN); + pre_link_sta_ctl->node[i].valid = _FALSE; + pre_link_sta_ctl->num--; + j++; + } + _exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL); + + for (i = 0; i < j; i++) { + sta = rtw_get_stainfo(stapriv, &(addrs[i][0])); + if (!sta) + continue; + + if (sta->state == WIFI_FW_PRE_LINK) + rtw_free_stainfo(stapriv->padapter, sta); + } +} + +void rtw_pre_link_sta_ctl_init(struct sta_priv *stapriv) +{ + struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl; + int i; + + _rtw_spinlock_init(&pre_link_sta_ctl->lock); + pre_link_sta_ctl->num = 0; + for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) + pre_link_sta_ctl->node[i].valid = _FALSE; +} + +void rtw_pre_link_sta_ctl_deinit(struct sta_priv *stapriv) +{ + struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl; + int i; + + rtw_pre_link_sta_ctl_reset(stapriv); + + _rtw_spinlock_free(&pre_link_sta_ctl->lock); +} + +void dump_pre_link_sta_ctl(void *sel, struct sta_priv *stapriv) +{ + struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl; + int i; + + RTW_PRINT_SEL(sel, "num:%d/%d\n", pre_link_sta_ctl->num, RTW_PRE_LINK_STA_NUM); + + for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) { + if (pre_link_sta_ctl->node[i].valid == _FALSE) + continue; + RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(pre_link_sta_ctl->node[i].addr)); + } +} +#endif /* CONFIG_RTW_PRE_LINK_STA */ + diff --git a/core/rtw_tdls.c b/core/rtw_tdls.c index 5b172b9..ecf1277 100644 --- a/core/rtw_tdls.c +++ b/core/rtw_tdls.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_TDLS_C_ #include @@ -198,7 +193,7 @@ int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsi SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); + set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); @@ -424,11 +419,12 @@ u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattr #ifdef CONFIG_80211AC_VHT void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; - u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, rf_type = RF_1T1R; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, rf_type = RF_1T1R, tx_nss = 0; u8 *pcap_mcs; - u8 vht_mcs[2]; _rtw_memset(&ptdls_sta->vhtpriv, 0, sizeof(struct vht_priv)); if (data && Length == 12) { @@ -450,7 +446,7 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 if (ptdls_sta->flags & WLAN_STA_VHT) { if (REGSTY_IS_11AC_ENABLE(&padapter->registrypriv) && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent))) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))) ptdls_sta->vhtpriv.vht_option = _TRUE; else ptdls_sta->vhtpriv.vht_option = _FALSE; @@ -492,18 +488,9 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 ptdls_sta->vhtpriv.ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(data); pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(data); - _rtw_memcpy(vht_mcs, pcap_mcs, 2); - rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); - if ((rf_type == RF_1T1R) || (rf_type == RF_1T2R)) - vht_mcs[0] |= 0xfc; - else if (rf_type == RF_2T2R) - vht_mcs[0] |= 0xf0; - else if (rf_type == RF_3T3R) - vht_mcs[0] |= 0xc0; - - _rtw_memcpy(ptdls_sta->vhtpriv.vht_mcs_map, vht_mcs, 2); - + tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + rtw_vht_nss_to_mcsmap(tx_nss, ptdls_sta->vhtpriv.vht_mcs_map, pcap_mcs); ptdls_sta->vhtpriv.vht_highest_rate = rtw_get_vht_highest_rate(ptdls_sta->vhtpriv.vht_mcs_map); } @@ -546,20 +533,22 @@ u8 *rtw_tdls_set_vht_op_mode_notify(_adapter *padapter, u8 *pframe, struct pkt_a #endif -u8 *rtw_tdls_set_sup_ch(struct mlme_ext_priv *pmlmeext, u8 *pframe, struct pkt_attrib *pattrib) +u8 *rtw_tdls_set_sup_ch(_adapter *adapter, u8 *pframe, struct pkt_attrib *pattrib) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); u8 sup_ch[30 * 2] = {0x00}, ch_set_idx = 0, sup_ch_idx = 2; - do { - if (pmlmeext->channel_set[ch_set_idx].ChannelNum <= 14) { + while (ch_set_idx < rfctl->max_chan_nums && rfctl->channel_set[ch_set_idx].ChannelNum != 0) { + if (rfctl->channel_set[ch_set_idx].ChannelNum <= 14) { + /* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */ sup_ch[0] = 1; /* First channel number */ - sup_ch[1] = pmlmeext->channel_set[ch_set_idx].ChannelNum; /* Number of channel */ + sup_ch[1] = rfctl->channel_set[ch_set_idx].ChannelNum; /* Number of channel */ } else { - sup_ch[sup_ch_idx++] = pmlmeext->channel_set[ch_set_idx].ChannelNum; + sup_ch[sup_ch_idx++] = rfctl->channel_set[ch_set_idx].ChannelNum; sup_ch[sup_ch_idx++] = 1; } ch_set_idx++; - } while (pmlmeext->channel_set[ch_set_idx].ChannelNum != 0 && ch_set_idx < MAX_CHANNEL_NUM); + } return rtw_set_ie(pframe, _SUPPORTED_CH_IE_, sup_ch_idx, sup_ch, &(pattrib->pktlen)); } @@ -832,9 +821,9 @@ s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_ty rtw_set_oper_bw(padapter, bwmode); center_ch = rtw_get_center_ch(channel, bwmode, channel_offset); - pHalData->CurrentChannel = center_ch; + pHalData->current_channel = center_ch; pHalData->CurrentCenterFrequencyIndex1 = center_ch; - pHalData->CurrentChannelBW = bwmode; + pHalData->current_channel_bw = bwmode; pHalData->nCur40MhzPrimeSC = channel_offset; if (bwmode == CHANNEL_WIDTH_80) { @@ -1338,7 +1327,7 @@ int issue_tdls_dis_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 priva SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -1560,7 +1549,7 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) struct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib); struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo); u8 empty_addr[ETH_ALEN] = { 0x00 }; - int UndecoratedSmoothedPWDB; + int undecorated_smoothed_pwdb; struct tdls_txmgmt txmgmt; int ret = _SUCCESS; @@ -1604,10 +1593,10 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) } } - rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB); + rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &undecorated_smoothed_pwdb); - if (pattrib->phy_info.RxPWDBAll + TDLS_SIGNAL_THRESH >= UndecoratedSmoothedPWDB) { - RTW_INFO("pattrib->RxPWDBAll=%d, pdmpriv->UndecoratedSmoothedPWDB=%d\n", pattrib->phy_info.RxPWDBAll, UndecoratedSmoothedPWDB); + if (pattrib->phy_info.RxPWDBAll + TDLS_SIGNAL_THRESH >= undecorated_smoothed_pwdb) { + RTW_INFO("pattrib->RxPWDBAll=%d, pdmpriv->undecorated_smoothed_pwdb=%d\n", pattrib->phy_info.RxPWDBAll, undecorated_smoothed_pwdb); _rtw_memcpy(txmgmt.peer, psa, ETH_ALEN); issue_tdls_setup_req(padapter, &txmgmt, _FALSE); } @@ -2642,6 +2631,7 @@ void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen) void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct pkt_attrib *pattrib = &pxmitframe->attrib; @@ -2668,7 +2658,7 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr pframe = rtw_tdls_set_capability(padapter, pframe, pattrib); pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib); - pframe = rtw_tdls_set_sup_ch(&(padapter->mlmeextpriv), pframe, pattrib); + pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib); pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib); if (pattrib->encrypt) @@ -2703,7 +2693,7 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14) && REGSTY_IS_11AC_ENABLE(pregistrypriv) && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!padapter->mlmepriv.country_ent || COUNTRY_CHPLAN_EN_11AC(padapter->mlmepriv.country_ent)) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) ) { pframe = rtw_tdls_set_aid(padapter, pframe, pattrib); pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib); @@ -2719,6 +2709,7 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct pkt_attrib *pattrib = &pxmitframe->attrib; @@ -2755,7 +2746,7 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); pframe = rtw_tdls_set_capability(padapter, pframe, pattrib); pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib); - pframe = rtw_tdls_set_sup_ch(&(padapter->mlmeextpriv), pframe, pattrib); + pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib); pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib); if (pattrib->encrypt) { @@ -2803,7 +2794,7 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14) && REGSTY_IS_11AC_ENABLE(pregistrypriv) && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!padapter->mlmepriv.country_ent || COUNTRY_CHPLAN_EN_11AC(padapter->mlmepriv.country_ent)) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) ) { pframe = rtw_tdls_set_aid(padapter, pframe, pattrib); pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib); @@ -2820,6 +2811,7 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -2880,7 +2872,7 @@ void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitfr && (ptdls_sta->vhtpriv.vht_option == _TRUE) && (pmlmeext->cur_channel > 14) && REGSTY_IS_11AC_ENABLE(pregistrypriv) && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!padapter->mlmepriv.country_ent || COUNTRY_CHPLAN_EN_11AC(padapter->mlmepriv.country_ent)) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) ) { pframe = rtw_tdls_set_vht_operation(padapter, pframe, pattrib, pmlmeext->cur_channel); pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode); @@ -2948,7 +2940,7 @@ void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfram pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib); - pframe = rtw_tdls_set_sup_ch(pmlmeext, pframe, pattrib); + pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib); if (privacy) pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, NULL); @@ -3246,15 +3238,15 @@ void _tdls_pti_timer_hdl(void *FunctionContext) void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta) { psta->padapter = padapter; - _init_timer(&psta->TPK_timer, padapter->pnetdev, _tdls_tpk_timer_hdl, psta); + rtw_init_timer(&psta->TPK_timer, padapter, _tdls_tpk_timer_hdl, psta); #ifdef CONFIG_TDLS_CH_SW - _init_timer(&psta->ch_sw_timer, padapter->pnetdev, _tdls_ch_switch_timer_hdl, psta); - _init_timer(&psta->delay_timer, padapter->pnetdev, _tdls_delay_timer_hdl, psta); - _init_timer(&psta->stay_on_base_chnl_timer, padapter->pnetdev, _tdls_stay_on_base_chnl_timer_hdl, psta); - _init_timer(&psta->ch_sw_monitor_timer, padapter->pnetdev, _tdls_ch_switch_monitor_timer_hdl, psta); + rtw_init_timer(&psta->ch_sw_timer, padapter, _tdls_ch_switch_timer_hdl, psta); + rtw_init_timer(&psta->delay_timer, padapter, _tdls_delay_timer_hdl, psta); + rtw_init_timer(&psta->stay_on_base_chnl_timer, padapter, _tdls_stay_on_base_chnl_timer_hdl, psta); + rtw_init_timer(&psta->ch_sw_monitor_timer, padapter, _tdls_ch_switch_monitor_timer_hdl, psta); #endif - _init_timer(&psta->handshake_timer, padapter->pnetdev, _tdls_handshake_timer_hdl, psta); - _init_timer(&psta->pti_timer, padapter->pnetdev, _tdls_pti_timer_hdl, psta); + rtw_init_timer(&psta->handshake_timer, padapter, _tdls_handshake_timer_hdl, psta); + rtw_init_timer(&psta->pti_timer, padapter, _tdls_pti_timer_hdl, psta); } void rtw_free_tdls_timer(struct sta_info *psta) @@ -3270,11 +3262,6 @@ void rtw_free_tdls_timer(struct sta_info *psta) _cancel_timer_ex(&psta->pti_timer); } -u8 update_sgi_tdls(_adapter *padapter, struct sta_info *psta) -{ - return query_ra_short_GI(psta); -} - u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta) { unsigned char sta_band = 0; diff --git a/core/rtw_vht.c b/core/rtw_vht.c index 496a300..bff68c1 100644 --- a/core/rtw_vht.c +++ b/core/rtw_vht.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,15 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_VHT_C #include +#include #ifdef CONFIG_80211AC_VHT /* 20/40/80, ShortGI, MCS Rate */ @@ -101,7 +97,7 @@ u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map) return nss; } -void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map) +void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map) { u8 i, j; u8 cur_rate, target_rate; @@ -143,6 +139,8 @@ void rtw_vht_use_default_setting(_adapter *padapter) u8 mu_bfer, mu_bfee; #endif /* CONFIG_BEAMFORMING */ u8 rf_type = 0; + u8 tx_nss, rx_nss; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); pvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE; @@ -224,67 +222,43 @@ void rtw_vht_use_default_setting(_adapter *padapter) pvhtpriv->ampdu_len = pregistrypriv->ampdu_factor; rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num); - if (rf_type == RF_3T3R) - pvhtpriv->vht_mcs_map[0] = 0xea; /* support 1SS MCS 0~9 2SS MCS 0~9 3SS MCS 0~9 */ - else if (rf_type == RF_2T2R) - pvhtpriv->vht_mcs_map[0] = 0xfa; /* support 1SS MCS 0~9 2SS MCS 0~9 */ - else - pvhtpriv->vht_mcs_map[0] = 0xfe; /* Only support 1SS MCS 0~9; */ - pvhtpriv->vht_mcs_map[1] = 0xff; - - if (pregistrypriv->vht_rate_sel == 1) { - pvhtpriv->vht_mcs_map[0] = 0xfc; /* support 1SS MCS 0~7 */ - } else if (pregistrypriv->vht_rate_sel == 2) { - pvhtpriv->vht_mcs_map[0] = 0xfd; /* Support 1SS MCS 0~8 */ - } else if (pregistrypriv->vht_rate_sel == 3) { - pvhtpriv->vht_mcs_map[0] = 0xfe; /* Support 1SS MCS 0~9 */ - } else if (pregistrypriv->vht_rate_sel == 4) { - pvhtpriv->vht_mcs_map[0] = 0xf0; /* support 1SS MCS 0~7 2SS MCS 0~7 */ - } else if (pregistrypriv->vht_rate_sel == 5) { - pvhtpriv->vht_mcs_map[0] = 0xf5; /* support 1SS MCS 0~8 2SS MCS 0~8 */ - } else if (pregistrypriv->vht_rate_sel == 6) { - pvhtpriv->vht_mcs_map[0] = 0xfa; /* support 1SS MCS 0~9 2SS MCS 0~9 */ - } else if (pregistrypriv->vht_rate_sel == 7) { - pvhtpriv->vht_mcs_map[0] = 0xf8; /* support 1SS MCS 0-7 2SS MCS 0~9 */ - } else if (pregistrypriv->vht_rate_sel == 8) { - pvhtpriv->vht_mcs_map[0] = 0xf9; /* support 1SS MCS 0-8 2SS MCS 0~9 */ - } else if (pregistrypriv->vht_rate_sel == 9) { - pvhtpriv->vht_mcs_map[0] = 0xf4; /* support 1SS MCS 0-7 2SS MCS 0~8 */ - } - + /* for now, vhtpriv.vht_mcs_map comes from RX NSS */ + rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pregistrypriv->vht_rx_mcs_map); pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map); } -u64 rtw_vht_rate_to_bitmap(u8 *pVHTRate) +u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss) { + u8 i, j, tmp; + u64 bitmap = 0; + u8 bits_nss = nss * 2; - u8 i, j , tmpRate; - u64 RateBitmap = 0; - u8 Bits_3ss = 6; - - for (i = j = 0; i < Bits_3ss; i += 2, j += 10) { + for (i = j = 0; i < bits_nss; i += 2, j += 10) { /* every two bits means single sptial stream */ - tmpRate = (pVHTRate[0] >> i) & 3; + tmp = (mcs_map[i / 8] >> i) & 3; - switch (tmpRate) { + switch (tmp) { case 2: - RateBitmap = RateBitmap | (0x03ff << j); + bitmap = bitmap | (0x03ff << j); break; case 1: - RateBitmap = RateBitmap | (0x01ff << j); + bitmap = bitmap | (0x01ff << j); break; - case 0: - RateBitmap = RateBitmap | (0x00ff << j); + bitmap = bitmap | (0x00ff << j); break; - default: break; } } - RTW_INFO("RateBitmap=%016llx , pVHTRate[0]=%02x, pVHTRate[1]=%02x\n", RateBitmap, pVHTRate[0], pVHTRate[1]); - return RateBitmap; + + RTW_INFO("vht_mcs_map=%02x %02x, nss=%u => bitmap=%016llx\n" + , mcs_map[0], mcs_map[1], nss, bitmap); + + return bitmap; } void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta) @@ -362,9 +336,7 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta) pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pvhtpriv_sta->vht_cap); _rtw_memcpy(pvhtpriv_sta->vht_mcs_map, pcap_mcs, 2); - pvhtpriv_sta->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv_sta->vht_mcs_map); - } void update_hw_vht_param(_adapter *padapter) @@ -383,14 +355,14 @@ void update_hw_vht_param(_adapter *padapter) void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) { + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, rf_type = RF_1T1R; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, rf_type = RF_1T1R, tx_nss = 0; u16 cur_beamform_cap = 0; u8 *pcap_mcs; - u8 vht_mcs[2]; if (pIE == NULL) return; @@ -489,18 +461,9 @@ void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data); pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data); - _rtw_memcpy(vht_mcs, pcap_mcs, 2); - rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); - if ((rf_type == RF_1T1R) || (rf_type == RF_1T2R)) - vht_mcs[0] |= 0xfc; - else if (rf_type == RF_2T2R) - vht_mcs[0] |= 0xf0; - else if (rf_type == RF_3T3R) - vht_mcs[0] |= 0xc0; - - _rtw_memcpy(pvhtpriv->vht_mcs_map, vht_mcs, 2); - + tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + rtw_vht_nss_to_mcsmap(tx_nss, pvhtpriv->vht_mcs_map, pcap_mcs); pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map); } @@ -526,7 +489,6 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta) u8 target_bw; u8 target_rxss, current_rxss; u8 update_ra = _FALSE; - u8 vht_mcs_map[2] = {}; if (pvhtpriv->vht_option == _FALSE) return; @@ -545,6 +507,8 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta) current_rxss = rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map); if (target_rxss != current_rxss) { + u8 vht_mcs_map[2] = {}; + update_ra = _TRUE; rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map); @@ -563,12 +527,10 @@ u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; /* struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; */ - u8 ChnlWidth, center_freq, bw_mode, rf_type = 0; + u8 ChnlWidth, center_freq, bw_mode; u32 len = 0; u8 operation[5]; - rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); - _rtw_memset(operation, 0, 5); bw_mode = REGSTY_BW_5G(pregistrypriv); /* TODO: control op bw with other info */ @@ -589,34 +551,7 @@ u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel) SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);/* Todo: need to set correct center channel */ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation, 0); - if (padapter->registrypriv.rf_config != RF_MAX_TYPE) - rf_type = padapter->registrypriv.rf_config; - - switch (rf_type) { - case RF_1T1R: - operation[3] = 0xfe; - operation[4] = 0xff; - break; - case RF_1T2R: - case RF_2T2R: - case RF_2T2R_GREEN: - operation[3] = 0xfa; - operation[4] = 0xff; - break; - case RF_2T3R: - case RF_2T4R: - case RF_3T3R: - case RF_3T4R: - operation[3] = 0xea; - operation[4] = 0xff; - break; - case RF_4T4R: - operation[3] = 0xaa; - operation[4] = 0xff; - break; - default: - RTW_INFO("%s, %d, unknown rf type\n", __func__, __LINE__); - } + _rtw_memcpy(operation + 3, pvhtpriv->vht_mcs_map, 2); rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len); @@ -629,18 +564,11 @@ u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; u32 len = 0; - u8 opmode = 0, rf_type = 0; + u8 opmode = 0; u8 chnl_width, rx_nss; chnl_width = bw; - - rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); - if (rf_type == RF_3T3R) - rx_nss = 3; - else if (rf_type == RF_2T2R) - rx_nss = 2; - else - rx_nss = 1; + rx_nss = rtw_vht_mcsmap_to_nss(pvhtpriv->vht_mcs_map); SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&opmode, chnl_width); SET_VHT_OPERATING_MODE_FIELD_RX_NSS(&opmode, (rx_nss - 1)); @@ -663,6 +591,8 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); pcap = pvhtpriv->vht_cap; _rtw_memset(pcap, 0, 32); @@ -695,46 +625,66 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0); /* B4 Rx LDPC */ - if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) + if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) { SET_VHT_CAPABILITY_ELE_RX_LDPC(pcap, 1); + RTW_INFO("[VHT] Declare supporting RX LDPC\n"); + } /* B5 ShortGI for 80MHz */ SET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m ? 1 : 0); /* We can receive Short GI of 80M */ + if (pvhtpriv->sgi_80m) + RTW_INFO("[VHT] Declare supporting SGI 80MHz\n"); /* B6 ShortGI for 160MHz */ /* SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0); */ /* B7 Tx STBC */ - if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) + if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) { SET_VHT_CAPABILITY_ELE_TX_STBC(pcap, 1); + RTW_INFO("[VHT] Declare supporting TX STBC\n"); + } /* B8 B9 B10 Rx STBC */ if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) { rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss)); SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss); + RTW_INFO("[VHT] Declare supporting RX STBC = %d\n", rx_stbc_nss); } /* B11 SU Beamformer Capable */ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1); + RTW_INFO("[VHT] Declare supporting SU Bfer\n"); /* B16 17 18 Number of Sounding Dimensions */ rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num); SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, rf_num); /* B19 MU Beamformer Capable */ - if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) + if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { SET_VHT_CAPABILITY_ELE_MU_BFER(pcap, 1); + RTW_INFO("[VHT] Declare supporting MU Bfer\n"); + } } /* B12 SU Beamformee Capable */ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) { SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1); - /* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */ + RTW_INFO("[VHT] Declare supporting SU Bfee\n"); + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); + + /* IOT action suggested by Yu Chen 2017/3/3 */ + if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) && + !GET_VHT_CAPABILITY_ELE_MU_BFER(&pvhtpriv->beamform_cap)) + rf_num = (rf_num >= 2 ? 2 : rf_num); + + /* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */ SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num); /* B20 SU Beamformee Capable */ - if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) + if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) { SET_VHT_CAPABILITY_ELE_MU_BFEE(pcap, 1); + RTW_INFO("[VHT] Declare supporting MU Bfee\n"); + } } /* B21 VHT TXOP PS */ diff --git a/core/rtw_wapi.c b/core/rtw_wapi.c index eb1605e..3143b62 100644 --- a/core/rtw_wapi.c +++ b/core/rtw_wapi.c @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifdef CONFIG_WAPI_SUPPORT #include @@ -161,14 +175,12 @@ WapiGetEntryForCamWrite(_adapter *padapter, u8 *pMacAddr, u8 KID, BOOLEAN IsMsk) /* if(RTIsListEmpty(&pWapiInfo->wapiCamIdleList)) { - RT_TRACE(COMP_SEC,DBG_LOUD,("No Entry for wapi!!!\n")); return 0; } pEntry = (PRT_WAPI_CAM_ENTRY)RTRemoveHeadList(&pWapiInfo->wapiCamIdleList); RTInsertTailList(&pWapiInfo->wapiCamUsedList, &pEntry->list); - RT_TRACE(COMP_SEC,DBG_LOUD,("<====WapiGetCamEntry(),Get Entry Idx:%d.but we just return 4 for test\n",pEntry->entry_idx)); return pEntry->entry_idx;*/ } @@ -200,7 +212,6 @@ u8 WapiGetEntryForCamClear(_adapter *padapter, u8 *pPeerMac, u8 keyid, u8 IsMsk) return 0xff; /* if(RTIsListEmpty(&pWapiInfo->wapiCamUsedList)) { - RT_TRACE(COMP_SEC,DBG_LOUD,("No Entry for wapi!!!\n")); return FALSE; } @@ -371,7 +382,7 @@ u8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data) return 0; } - pTaddr = GetAddr2Ptr(pkt_data); + pTaddr = get_addr2_ptr(pkt_data); if (list_empty(&pWapiInfo->wapiSTAUsedList)) bFind = false; else { @@ -426,7 +437,7 @@ void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame) else precv_hdr->UserPriority = 0; - pTA = GetAddr2Ptr(ptr); + pTA = get_addr2_ptr(ptr); _rtw_memcpy((u8 *)precv_hdr->WapiSrcAddr, pTA, 6); pRecvPN = ptr + precv_hdr->attrib.hdrlen + 2; _rtw_memcpy((u8 *)precv_hdr->WapiTempPN, pRecvPN, 16); diff --git a/core/rtw_wapi_sms4.c b/core/rtw_wapi_sms4.c index fc01212..4b7cf95 100644 --- a/core/rtw_wapi_sms4.c +++ b/core/rtw_wapi_sms4.c @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifdef CONFIG_WAPI_SUPPORT #include diff --git a/core/rtw_wlan_util.c b/core/rtw_wlan_util.c index 71f55f4..206bff6 100644 --- a/core/rtw_wlan_util.c +++ b/core/rtw_wlan_util.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,21 +11,19 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_WLAN_UTIL_C_ #include +#include #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) #include #define ETH_TYPE_OFFSET 12 #define PROTOCOL_OFFSET 23 #define IP_OFFSET 30 + #define IPv6_OFFSET 38 + #define IPv6_PROTOCOL_OFFSET 20 #endif unsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f}; @@ -103,80 +101,33 @@ int cckratesonly_included(unsigned char *rate, int ratelen) return _TRUE; } +#ifdef CONFIG_GET_RAID_BY_DRV s8 rtw_get_tx_nss(_adapter *adapter, struct sta_info *psta) { - u8 rf_type = RF_1T1R, custom_rf_type, vht_mcs[2]; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 rf_type = RF_1T1R, custom_rf_type; s8 nss = 1; - custom_rf_type = adapter->registrypriv.rf_config; - rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); - if (!psta) return nss; - /* rf_config is dependent on efuse or sw config */ - if (custom_rf_type != RF_MAX_TYPE) + custom_rf_type = adapter->registrypriv.rf_config; + rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + if (RF_TYPE_VALID(custom_rf_type)) rf_type = custom_rf_type; #ifdef CONFIG_80211AC_VHT if (psta->vhtpriv.vht_option) { - u8 vht_mcs[2]; - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv; - - _rtw_memcpy(vht_mcs, psta->vhtpriv.vht_mcs_map, 2); - /* doesn't support 5~8 SS so far */ - vht_mcs[1] = 0xff; - switch (rf_type) { - case RF_1T1R: - case RF_1T2R: - vht_mcs[0] |= 0xfc; - break; - case RF_2T2R: - case RF_2T4R: - case RF_2T2R_GREEN: - case RF_2T3R: - vht_mcs[0] |= 0xf0; - break; - case RF_3T3R: - case RF_3T4R: - vht_mcs[0] |= 0xc0; - break; - default: - RTW_INFO("%s,%d, unknown rf type\n", __func__, __LINE__); - break; - } - nss = rtw_vht_mcsmap_to_nss(vht_mcs); + nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map)); } else #endif /* CONFIG_80211AC_VHT */ - if (psta->htpriv.ht_option) { - u8 supp_mcs_set[4]; - - _rtw_memcpy(supp_mcs_set, psta->htpriv.ht_cap.supp_mcs_set, 4); - - switch (rf_type) { - case RF_1T1R: - case RF_1T2R: - supp_mcs_set[1] = supp_mcs_set[2] = supp_mcs_set[3] = 0; - break; - case RF_2T2R: - case RF_2T4R: - case RF_2T2R_GREEN: - case RF_2T3R: - supp_mcs_set[2] = supp_mcs_set[3] = 0; - break; - case RF_3T3R: - case RF_3T4R: - supp_mcs_set[3] = 0; - break; - default: - RTW_INFO("%s,%d, unknown rf type\n", __func__, __LINE__); - break; - } - nss = rtw_ht_mcsset_to_nss(supp_mcs_set); - } + if (psta->htpriv.ht_option) { + nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set)); + } - RTW_INFO("%s: %d SS, rf_type=%d\n", __func__, nss, rf_type); + RTW_INFO("%s: %d SS\n", __func__, nss); return nss; } @@ -312,7 +263,7 @@ u8 networktype_to_raid_ex(_adapter *adapter, struct sta_info *psta) return raid; } - +#endif u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen) { u8 network_type = 0; @@ -432,6 +383,9 @@ unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset) for (i = 0; i < NumRates; i++) { rate = pmlmeext->datarate[i]; + if (rtw_get_oper_ch(padapter) > 14 && rate < _6M_RATE_) /*5G no support CCK rate*/ + continue; + switch (rate) { case 0xff: return len; @@ -599,13 +553,19 @@ u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset) goto exit; } - /* TODO: 2.4G 40MHz offset choise */ - if (ch >= 1 && ch <= 4) offset = HAL_PRIME_CHNL_OFFSET_LOWER; - else if (ch >= 5 && ch <= 14) + else if (ch >= 5 && ch <= 9) { + if (*r_offset == HAL_PRIME_CHNL_OFFSET_LOWER || *r_offset == HAL_PRIME_CHNL_OFFSET_UPPER) + offset = *r_offset; /* both lower and upper is valid, obey input value */ + else + offset = HAL_PRIME_CHNL_OFFSET_UPPER; /* default use upper */ + } else if (ch >= 10 && ch <= 13) offset = HAL_PRIME_CHNL_OFFSET_UPPER; - else if (ch >= 36 && ch <= 177) { + else if (ch == 14) { + valid = 0; /* ch14 doesn't support 40MHz bandwidth */ + goto exit; + } else if (ch >= 36 && ch <= 177) { switch (ch) { case 36: case 44: @@ -746,110 +706,6 @@ inline u32 rtw_get_on_cur_ch_time(_adapter *adapter) return 0; } -void SelectChannel(_adapter *padapter, unsigned char channel) -{ - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - - _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); - -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - /* driver doesn't set channel reg under MCC */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { - RTW_INFO("Warning: Do not set channel reg MCC mode\n"); - rtw_warn_on(1); - } - } -#endif - -#ifdef CONFIG_DFS_MASTER - { - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl); - bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl, channel - , adapter_to_dvobj(padapter)->oper_bwmode, adapter_to_dvobj(padapter)->oper_ch_offset); - - if (new_overlap_radar_detect_ch) - rtw_odm_radar_detect_enable(padapter); - - if (new_overlap_radar_detect_ch && IS_CH_WAITING(rfctl)) { - u8 pause = 0xFF; - - rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause); - } -#endif /* CONFIG_DFS_MASTER */ - - /* saved channel info */ - rtw_set_oper_ch(padapter, channel); - - rtw_hal_set_chan(padapter, channel); - -#ifdef CONFIG_DFS_MASTER - if (ori_overlap_radar_detect_ch && !new_overlap_radar_detect_ch) { - u8 pause = 0x00; - - rtw_odm_radar_detect_disable(padapter); - rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause); - } - } -#endif /* CONFIG_DFS_MASTER */ - - _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); - -} - -void SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset) -{ - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - - _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setbw_mutex), NULL); - -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - /* driver doesn't set bw reg under MCC */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { - RTW_INFO("Warning: Do not set bw reg MCC mode\n"); - rtw_warn_on(1); - } - } -#endif - -#ifdef CONFIG_DFS_MASTER - { - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); - bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl); - bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl - , adapter_to_dvobj(padapter)->oper_channel, bwmode, channel_offset); - - if (new_overlap_radar_detect_ch) - rtw_odm_radar_detect_enable(padapter); - - if (new_overlap_radar_detect_ch && IS_CH_WAITING(rfctl)) { - u8 pause = 0xFF; - - rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause); - } -#endif /* CONFIG_DFS_MASTER */ - - /* saved bw info */ - rtw_set_oper_bw(padapter, bwmode); - rtw_set_oper_choffset(padapter, channel_offset); - - rtw_hal_set_bwmode(padapter, (CHANNEL_WIDTH)bwmode, channel_offset); - -#ifdef CONFIG_DFS_MASTER - if (ori_overlap_radar_detect_ch && !new_overlap_radar_detect_ch) { - u8 pause = 0x00; - - rtw_odm_radar_detect_disable(padapter); - rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause); - } - } -#endif /* CONFIG_DFS_MASTER */ - - _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setbw_mutex), NULL); -} - void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode) { u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; @@ -889,9 +745,6 @@ void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl); bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl, channel, bwmode, channel_offset); - if (new_overlap_radar_detect_ch) - rtw_odm_radar_detect_enable(padapter); - if (new_overlap_radar_detect_ch && IS_CH_WAITING(rfctl)) { u8 pause = 0xFF; @@ -925,7 +778,9 @@ void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char #endif #ifdef CONFIG_DFS_MASTER - if (ori_overlap_radar_detect_ch && !new_overlap_radar_detect_ch) { + if (new_overlap_radar_detect_ch) + rtw_odm_radar_detect_enable(padapter); + else if (ori_overlap_radar_detect_ch) { u8 pause = 0x00; rtw_odm_radar_detect_disable(padapter); @@ -1669,6 +1524,14 @@ void rtw_clean_dk_section(_adapter *adapter) } } } +void rtw_clean_hw_dk_cam(_adapter *adapter) +{ + int i; + + for (i = 0; i < 4; i++) + rtw_sec_clr_cam_ent(adapter, i); + /*_clear_cam_entry(adapter, i);*/ +} void flush_all_cam_entry(_adapter *padapter) { @@ -1810,7 +1673,7 @@ void WMMOnAssocRsp(_adapter *padapter) acm_mask = 0; - if (IsSupported5G(pmlmeext->cur_wireless_mode) || + if (is_supported_5g(pmlmeext->cur_wireless_mode) || (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) aSifsTime = 16; else @@ -1932,6 +1795,10 @@ void WMMOnAssocRsp(_adapter *padapter) pxmitpriv->wmm_para_seq[i] = inx[i]; RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]); } +#ifdef CONFIG_WMMPS + if (pmlmeinfo->WMM_param.QoS_info & BIT(7)) + rtw_hal_set_hwreg(padapter, HW_VAR_UAPSD_TID, NULL); +#endif } } @@ -2045,12 +1912,13 @@ void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) unsigned int i; u8 rf_type = RF_1T1R; u8 max_AMPDU_len, min_MPDU_spacing; - u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, tx_nss = 0; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct ht_priv *phtpriv = &pmlmepriv->htpriv; struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); if (pIE == NULL) return; @@ -2090,39 +1958,38 @@ void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info); pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps); - rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); - - /* update the MCS set */ for (i = 0; i < 16; i++) pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i]; - /* update the MCS rates */ - switch (rf_type) { - case RF_1T1R: - case RF_1T2R: + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + + switch (tx_nss) { + case 1: set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R); break; - case RF_2T2R: -#ifdef CONFIG_DISABLE_MCS13TO15 + case 2: + #ifdef CONFIG_DISABLE_MCS13TO15 if (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1) set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF); else + #endif set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R); -#else /* CONFIG_DISABLE_MCS13TO15 */ - set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R); -#endif /* CONFIG_DISABLE_MCS13TO15 */ break; - case RF_3T3R: + case 3: set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R); break; + case 4: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R); + break; default: - RTW_INFO("[warning] rf_type %d is not expected\n", rf_type); + RTW_WARN("rf_type:%d or tx_nss:%u is not expected\n", rf_type, hal_spec->tx_nss_num); } if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { /* Config STBC setting */ - if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_TX_STBC(pIE->data)) { + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) { SET_FLAG(cur_stbc_cap, STBC_HT_ENABLE_TX); RTW_INFO("Enable HT Tx STBC !\n"); } @@ -2164,6 +2031,22 @@ void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) phtpriv->stbc_cap = cur_stbc_cap; #ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 + /* Config beamforming setting */ + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + /* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6); + } + + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + /* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4); + } +#else /* !RTW_BEAMFORMING_VERSION_2 */ /* Config Tx beamforming setting */ if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) { @@ -2178,6 +2061,7 @@ void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) /* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4); } +#endif /* !RTW_BEAMFORMING_VERSION_2 */ phtpriv->beamform_cap = cur_beamform_cap; if (cur_beamform_cap) RTW_INFO("Client HT Beamforming Cap = 0x%02X\n", cur_beamform_cap); @@ -2261,8 +2145,6 @@ void HTOnAssocRsp(_adapter *padapter) pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; break; } - - /* SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset); */ } #endif @@ -2329,8 +2211,8 @@ void VCS_update(_adapter *padapter, struct sta_info *psta) case 2: /* auto */ default: if (((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1))) - /*||(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/ - ) { + /*||(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/ + ) { if (pregpriv->vcs_type == 1) { psta->rtsen = 1; psta->cts2self = 0; @@ -2373,6 +2255,49 @@ void update_ldpc_stbc_cap(struct sta_info *psta) #endif /* CONFIG_80211N_HT */ } +int check_ielen(u8 *start, uint len) +{ + int left = len; + u8 *pos = start; + int unknown = 0; + u8 id, elen; + + while (left >= 2) { + id = *pos++; + elen = *pos++; + left -= 2; + + if (elen > left) { + RTW_INFO("IEEE 802.11 element parse failed (id=%d elen=%d left=%lu)\n", + id, elen, (unsigned long) left); + return _FALSE; + } + if ((id == WLAN_EID_VENDOR_SPECIFIC) && (elen < 4)) + return _FALSE; + + left -= elen; + pos += elen; + } + if (left) + return _FALSE; + + return _TRUE; +} + +int validate_beacon_len(u8 *pframe, u32 len) +{ + u8 ie_offset = _BEACON_IE_OFFSET_ + sizeof(struct rtw_ieee80211_hdr_3addr); + + if (len < ie_offset) { + RTW_INFO("%s: incorrect beacon length(%d)\n", __func__, len); + return _FALSE; + } + + if (check_ielen(pframe + ie_offset, len - ie_offset) == _FALSE) + return _FALSE; + + return _TRUE; +} /* * rtw_get_bcn_keys: get beacon keys from recv frame @@ -2516,12 +2441,12 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr); if (len > MAX_IE_SZ) { - RTW_INFO("%s IE too long for survey event\n", __func__); + RTW_WARN("%s IE too long for survey event\n", __func__); return _FAIL; } if (_rtw_memcmp(cur_network->network.MacAddress, pbssid, 6) == _FALSE) { - RTW_INFO("Oops: rtw_check_network_encrypt linked but recv other bssid bcn\n" MAC_FMT MAC_FMT, + RTW_WARN("Oops: rtw_check_network_encrypt linked but recv other bssid bcn\n" MAC_FMT MAC_FMT, MAC_ARG(pbssid), MAC_ARG(cur_network->network.MacAddress)); return _TRUE; } @@ -2540,34 +2465,32 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) pmlmepriv->new_beacon_cnts = 0; else if ((pmlmepriv->new_beacon_cnts == 0) || _rtw_memcmp(&recv_beacon, &pmlmepriv->new_beacon_keys, sizeof(recv_beacon)) == _FALSE) { - RTW_ERR("%s: start new beacon (seq=%d)\n", __func__, GetSequence(pframe)); + RTW_DBG("%s: start new beacon (seq=%d)\n", __func__, GetSequence(pframe)); if (pmlmepriv->new_beacon_cnts == 0) { RTW_ERR("%s: cur beacon key\n", __func__); RTW_DBG_EXPR(rtw_dump_bcn_keys(&pmlmepriv->cur_beacon_keys)); } - RTW_ERR("%s: new beacon key\n", __func__); + RTW_DBG("%s: new beacon key\n", __func__); RTW_DBG_EXPR(rtw_dump_bcn_keys(&recv_beacon)); memcpy(&pmlmepriv->new_beacon_keys, &recv_beacon, sizeof(recv_beacon)); pmlmepriv->new_beacon_cnts = 1; } else { - RTW_ERR("%s: new beacon again (seq=%d)\n", __func__, GetSequence(pframe)); + RTW_DBG("%s: new beacon again (seq=%d)\n", __func__, GetSequence(pframe)); pmlmepriv->new_beacon_cnts++; } /* if counter >= max, it means beacon is changed really */ if (pmlmepriv->new_beacon_cnts >= new_bcn_max) { - RTW_ERR("%s: new beacon occur!!\n", __func__); - /* check bw mode change only? */ pmlmepriv->cur_beacon_keys.ht_cap_info = recv_beacon.ht_cap_info; pmlmepriv->cur_beacon_keys.ht_info_infos_0_sco = recv_beacon.ht_info_infos_0_sco; - if (_rtw_memcmp(&recv_beacon, &pmlmepriv->cur_beacon_keys, sizeof(recv_beacon)) == _FALSE) { /* beacon is changed, have to do disconnect/connect */ + RTW_WARN("%s: new beacon occur!!\n", __func__); return _FAIL; } @@ -2603,7 +2526,7 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) pmlmepriv->NumOfBcnInfoChkFail = 0; } - subtype = GetFrameSubType(pframe) >> 4; + subtype = get_frame_sub_type(pframe) >> 4; if (subtype == WIFI_BEACON) bssid->Reserved[0] = 1; @@ -2680,10 +2603,6 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) bssid->Ssid.Ssid[0] = '\0'; } - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("%s bssid.Ssid.Ssid:%s bssid.Ssid.SsidLength:%d " - "cur_network->network.Ssid.Ssid:%s len:%d\n", __func__, bssid->Ssid.Ssid, - bssid->Ssid.SsidLength, cur_network->network.Ssid.Ssid, - cur_network->network.Ssid.SsidLength)); if (_rtw_memcmp(bssid->Ssid.Ssid, cur_network->network.Ssid.Ssid, 32) == _FALSE || bssid->Ssid.SsidLength != cur_network->network.Ssid.SsidLength) { @@ -2701,9 +2620,6 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) else bssid->Privacy = 0; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, - ("%s(): cur_network->network.Privacy is %d, bssid.Privacy is %d\n", - __func__, cur_network->network.Privacy, bssid->Privacy)); if (cur_network->network.Privacy != bssid->Privacy) { RTW_INFO("%s(), privacy is not match\n", __func__); goto _mismatch; @@ -2728,25 +2644,15 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) if (encryp_protocol == ENCRYP_PROTOCOL_WPA || encryp_protocol == ENCRYP_PROTOCOL_WPA2) { pbuf = rtw_get_wpa_ie(&bssid->IEs[12], &wpa_ielen, bssid->IELength - 12); if (pbuf && (wpa_ielen > 0)) { - if (_SUCCESS == rtw_parse_wpa_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is_8021x)) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, - ("%s pnetwork->pairwise_cipher: %d, group_cipher is %d, is_8021x is %d\n", __func__, - pairwise_cipher, group_cipher, is_8021x)); - } + rtw_parse_wpa_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is_8021x); } else { pbuf = rtw_get_wpa2_ie(&bssid->IEs[12], &wpa_ielen, bssid->IELength - 12); if (pbuf && (wpa_ielen > 0)) { - if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is_8021x)) { - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, - ("%s pnetwork->pairwise_cipher: %d, pnetwork->group_cipher is %d, is_802x is %d\n", - __func__, pairwise_cipher, group_cipher, is_8021x)); - } + rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is_8021x); } } - RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, - ("%s cur_network->group_cipher is %d: %d\n", __func__, cur_network->BcnInfo.group_cipher, group_cipher)); if (pairwise_cipher != cur_network->BcnInfo.pairwise_cipher || group_cipher != cur_network->BcnInfo.group_cipher) { RTW_INFO("%s pairwise_cipher(%x:%x) or group_cipher(%x:%x) is not match\n", __func__, pairwise_cipher, cur_network->BcnInfo.pairwise_cipher, @@ -2809,7 +2715,7 @@ void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta break; - case _HT_EXTRA_INFO_IE_: /* HT info */ + case _HT_EXTRA_INFO_IE_: /* HT info */ /* HT_info_handler(padapter, pIE); */ bwmode_update_check(padapter, pIE); break; @@ -3062,15 +2968,6 @@ unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz) return mask; } -unsigned int update_MCS_rate(struct HT_caps_element *pHT_caps) -{ - unsigned int mask = 0; - - mask = ((pHT_caps->u.HT_cap_element.MCS_rate[0] << 12) | (pHT_caps->u.HT_cap_element.MCS_rate[1] << 20)); - - return mask; -} - int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode) { unsigned char bit_offset; @@ -3103,36 +3000,15 @@ unsigned char get_highest_rate_idx(u32 mask) return rate_idx; } -unsigned char get_highest_mcs_rate(struct HT_caps_element *pHT_caps); -unsigned char get_highest_mcs_rate(struct HT_caps_element *pHT_caps) -{ - int i, mcs_rate; - - mcs_rate = (pHT_caps->u.HT_cap_element.MCS_rate[0] | (pHT_caps->u.HT_cap_element.MCS_rate[1] << 8)); - - for (i = 15; i >= 0; i--) { - if (mcs_rate & (0x1 << i)) - break; - } - - return i; -} - void Update_RA_Entry(_adapter *padapter, struct sta_info *psta) { - rtw_hal_update_ra_mask(psta, psta->rssi_level); -} - -void enable_rate_adaptive(_adapter *padapter, struct sta_info *psta); -void enable_rate_adaptive(_adapter *padapter, struct sta_info *psta) -{ - Update_RA_Entry(padapter, psta); + rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); } void set_sta_rate(_adapter *padapter, struct sta_info *psta) { /* rate adaptive */ - enable_rate_adaptive(padapter, psta); + rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); } /* Update RRSR and Rate for USERATE */ @@ -3365,10 +3241,14 @@ void update_wireless_mode(_adapter *padapter) rtw_hal_set_hwreg(padapter, HW_VAR_WIRELESS_MODE, (u8 *)&(pmlmeext->cur_wireless_mode)); if ((pmlmeext->cur_wireless_mode & WIRELESS_11B) -#ifdef CONFIG_P2P - && rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) -#endif /* CONFIG_P2P */ - ) + #ifdef CONFIG_P2P + && (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) + #ifdef CONFIG_IOCTL_CFG80211 + || !rtw_cfg80211_iface_has_p2p_group_cap(padapter) + #endif + ) + #endif + ) update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB); else update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB); @@ -3471,7 +3351,12 @@ void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr) accept = rtw_rx_ampdu_is_accept(padapter); - size = rtw_rx_ampdu_size(padapter); + if (padapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID) + size = padapter->fix_rx_ampdu_size; + else { + size = rtw_rx_ampdu_size(padapter); + size = rtw_min(size, rx_ampdu_size_sta_limit(padapter, psta)); + } if (accept == _TRUE) rtw_addbarsp_cmd(padapter, addr, tid, 0, size, start_seq); @@ -3957,6 +3842,54 @@ inline void rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h RTW_INFO("macid:%u, h2c_msr:"H2C_MSR_FMT"\n", id, H2C_MSR_ARG(&macid_ctl->h2c_msr[id])); } +inline void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw) +{ + if (id >= macid_ctl->num) { + rtw_warn_on(1); + return; + } + + macid_ctl->bw[id] = bw; + if (0) + RTW_INFO("macid:%u, bw:%s\n", id, ch_width_str(macid_ctl->bw[id])); +} + +inline void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en) +{ + if (id >= macid_ctl->num) { + rtw_warn_on(1); + return; + } + + macid_ctl->vht_en[id] = en; + if (0) + RTW_INFO("macid:%u, vht_en:%u\n", id, macid_ctl->vht_en[id]); +} + +inline void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp) +{ + if (id >= macid_ctl->num) { + rtw_warn_on(1); + return; + } + + macid_ctl->rate_bmp0[id] = bmp; + if (0) + RTW_INFO("macid:%u, rate_bmp0:0x%08X\n", id, macid_ctl->rate_bmp0[id]); +} + +inline void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp) +{ + if (id >= macid_ctl->num) { + rtw_warn_on(1); + return; + } + + macid_ctl->rate_bmp1[id] = bmp; + if (0) + RTW_INFO("macid:%u, rate_bmp1:0x%08X\n", id, macid_ctl->rate_bmp1[id]); +} + inline void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl) { _rtw_spinlock_init(&macid_ctl->lock); @@ -3995,7 +3928,7 @@ unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame) _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); - SetFrameSubType(pframe, WIFI_BEACON); + set_frame_sub_type(pframe, WIFI_BEACON); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); len = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -4083,31 +4016,38 @@ _adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj) return port0_iface; } -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip) +_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj) { - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct in_device *my_ip_ptr = padapter->pnetdev->ip_ptr; - u8 ipaddress[4]; - - if ((pmlmeinfo->state & WIFI_FW_LINKING_STATE) || - pmlmeinfo->state & WIFI_FW_AP_STATE) { - if (my_ip_ptr != NULL) { - struct in_ifaddr *my_ifa_list = my_ip_ptr->ifa_list ; - if (my_ifa_list != NULL) { - ipaddress[0] = my_ifa_list->ifa_address & 0xFF; - ipaddress[1] = (my_ifa_list->ifa_address >> 8) & 0xFF; - ipaddress[2] = (my_ifa_list->ifa_address >> 16) & 0xFF; - ipaddress[3] = my_ifa_list->ifa_address >> 24; - RTW_INFO("%s: %d.%d.%d.%d ==========\n", __func__, - ipaddress[0], ipaddress[1], ipaddress[2], ipaddress[3]); - _rtw_memcpy(pcurrentip, ipaddress, 4); - } - } + _adapter *adapter = NULL; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (dvobj->padapters[i]->registered == 0) + break; } + + if (i < dvobj->iface_nums) + adapter = dvobj->padapters[i]; + + return adapter; } -#endif + +_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr) +{ + _adapter *adapter = NULL; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (_rtw_memcmp(dvobj->padapters[i]->mac_addr, addr, ETH_ALEN) == _TRUE) + break; + } + + if (i < dvobj->iface_nums) + adapter = dvobj->padapters[i]; + + return adapter; +} + #ifdef CONFIG_WOWLAN bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern, int *pattern_len, char *bit_mask) @@ -4185,21 +4125,38 @@ bool rtw_check_pattern_valid(u8 *input, u8 len) exit: return res; } +void rtw_wow_pattern_sw_reset(_adapter *adapter) +{ + int i; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter); + + pwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM; + + for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) { + _rtw_memset(pwrctrlpriv->patterns[i].content, '\0', sizeof(pwrctrlpriv->patterns[i].content)); + _rtw_memset(pwrctrlpriv->patterns[i].mask, '\0', sizeof(pwrctrlpriv->patterns[i].mask)); + pwrctrlpriv->patterns[i].len = 0; + } +} u8 rtw_set_default_pattern(_adapter *adapter) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); struct registry_priv *pregistrypriv = &adapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; u8 index = 0; - u8 currentip[4]; u8 multicast_addr[3] = {0x01, 0x00, 0x5e}; u8 multicast_ip[4] = {0xe0, 0x28, 0x28, 0x2a}; + u8 unicast_mask[5] = {0x3f, 0x70, 0x80, 0xc0, 0x03}; + u8 icmpv6_mask[7] = {0x00, 0x70, 0x10, 0x00, 0xc0, 0xc0, 0x3f}; u8 multicast_mask[5] = {0x07, 0x70, 0x80, 0xc0, 0x03}; + u8 ip_protocol[3] = {0x08, 0x00, 0x45}; - u8 icmp_protocol[1] = {0x01}; - u8 tcp_protocol[1] = {0x06}; - u8 udp_protocol[1] = {0x11}; + u8 ipv6_protocol[3] = {0x86, 0xdd, 0x60}; + + u8 *target = NULL; if (pregistrypriv->default_patterns_en == _FALSE) return 0; @@ -4212,253 +4169,107 @@ u8 rtw_set_default_pattern(_adapter *adapter) pwrpriv->patterns[index].len = 0; } - rtw_get_current_ip_address(adapter, currentip); - /*TCP/ICMP unicast*/ for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) { switch (index) { case 0: - _rtw_memcpy(pwrpriv->patterns[index].content, - adapter_mac_addr(adapter), + target = pwrpriv->patterns[index].content; + _rtw_memcpy(target, adapter_mac_addr(adapter), ETH_ALEN); - _rtw_memcpy(pwrpriv->patterns[index].content + ETH_TYPE_OFFSET, - &ip_protocol, sizeof(ip_protocol)); - _rtw_memcpy(pwrpriv->patterns[index].content + PROTOCOL_OFFSET, - &tcp_protocol, sizeof(tcp_protocol)); - _rtw_memcpy(pwrpriv->patterns[index].content + IP_OFFSET, - ¤tip, sizeof(currentip)); - _rtw_memcpy(pwrpriv->patterns[index].mask, - &unicast_mask, sizeof(unicast_mask)); - pwrpriv->patterns[index].len = IP_OFFSET + sizeof(currentip); - break; - case 1: - _rtw_memcpy(pwrpriv->patterns[index].content, - adapter_mac_addr(adapter), - ETH_ALEN); - _rtw_memcpy(pwrpriv->patterns[index].content + ETH_TYPE_OFFSET, - &ip_protocol, sizeof(ip_protocol)); - _rtw_memcpy(pwrpriv->patterns[index].content + PROTOCOL_OFFSET, - &icmp_protocol, sizeof(icmp_protocol)); - _rtw_memcpy(pwrpriv->patterns[index].content + IP_OFFSET, - ¤tip, sizeof(currentip)); - _rtw_memcpy(pwrpriv->patterns[index].mask, - &unicast_mask, sizeof(unicast_mask)); - pwrpriv->patterns[index].len = IP_OFFSET + sizeof(currentip); - break; - case 2: - _rtw_memcpy(pwrpriv->patterns[index].content, &multicast_addr, - sizeof(multicast_addr)); - _rtw_memcpy(pwrpriv->patterns[index].content + ETH_TYPE_OFFSET, - &ip_protocol, sizeof(ip_protocol)); - _rtw_memcpy(pwrpriv->patterns[index].content + PROTOCOL_OFFSET, - &udp_protocol, sizeof(udp_protocol)); - _rtw_memcpy(pwrpriv->patterns[index].content + IP_OFFSET, - &multicast_ip, sizeof(multicast_ip)); - _rtw_memcpy(pwrpriv->patterns[index].mask, - &multicast_mask, sizeof(multicast_mask)); - pwrpriv->patterns[index].len = - IP_OFFSET + sizeof(multicast_ip); - break; - } - } - - return index; -} - -bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx) -{ - u32 data_l = 0, data_h = 0, rx_dma_buff_sz = 0, page_sz = 0; - u16 offset, rx_buf_ptr = 0; - u16 cam_start_offset = 0; - u16 ctrl_l = 0, ctrl_h = 0; - u8 count = 0, tmp = 0; - int i = 0; - bool res = _TRUE; - - if (idx > MAX_WKFM_NUM) { - RTW_INFO("[Error]: %s, pattern index is out of range\n", - __func__); - return _FALSE; - } - - rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW, - (u8 *)&rx_dma_buff_sz); - if (rx_dma_buff_sz == 0) { - RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__); - return _FALSE; - } - - rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz); - - if (page_sz == 0) { - RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__); - return _FALSE; - } + target += ETH_TYPE_OFFSET; + _rtw_memcpy(target, &ip_protocol, + sizeof(ip_protocol)); - offset = (u16)PageNum(rx_dma_buff_sz, page_sz); - cam_start_offset = offset * page_sz; + /* TCP */ + target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET); + _rtw_memset(target, 0x06, 1); - ctrl_l = 0x0; - ctrl_h = 0x0; + target += (IP_OFFSET - PROTOCOL_OFFSET); - /* Enable RX packet buffer access */ - rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT); + _rtw_memcpy(target, pmlmeinfo->ip_addr, + RTW_IP_ADDR_LEN); - /* Read the WKFM CAM */ - for (i = 0; i < (WKFMCAM_ADDR_NUM / 2); i++) { - /* - * Set Rx packet buffer offset. - * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer. - * CAM start offset (unit: 1 byte) = Index*WKFMCAM_SIZE - * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8 - * * Index: The index of the wake up frame mask - * * WKFMCAM_SIZE: the total size of one WKFM CAM - * * per entry offset of a WKFM CAM: Addr i * 4 bytes - */ - rx_buf_ptr = - (cam_start_offset + idx * WKFMCAM_SIZE + i * 8) >> 3; - rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr); - - rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l); - data_l = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L); - data_h = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H); - - RTW_INFO("[%d]: %08x %08x\n", i, data_h, data_l); - - count = 0; - - do { - tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL); - rtw_udelay_os(2); - count++; - } while (!tmp && count < 100); + _rtw_memcpy(pwrpriv->patterns[index].mask, + &unicast_mask, sizeof(unicast_mask)); - if (count >= 100) { - RTW_INFO("%s count:%d\n", __func__, count); - res = _FALSE; - } - } + pwrpriv->patterns[index].len = + IP_OFFSET + RTW_IP_ADDR_LEN; + break; + case 1: + target = pwrpriv->patterns[index].content; + _rtw_memcpy(target, adapter_mac_addr(adapter), + ETH_ALEN); - /* Disable RX packet buffer access */ - rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, - DISABLE_TRXPKT_BUF_ACCESS); - return res; -} + target += ETH_TYPE_OFFSET; + _rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol)); -bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx, - struct rtl_wow_pattern *context) -{ - u32 data = 0, rx_dma_buff_sz = 0, page_sz = 0; - u16 offset, rx_buf_ptr = 0; - u16 cam_start_offset = 0; - u16 ctrl_l = 0, ctrl_h = 0; - u8 count = 0, tmp = 0; - int res = 0, i = 0; + /* ICMP */ + target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET); + _rtw_memset(target, 0x01, 1); - if (idx > MAX_WKFM_NUM) { - RTW_INFO("[Error]: %s, pattern index is out of range\n", - __func__); - return _FALSE; - } + target += (IP_OFFSET - PROTOCOL_OFFSET); + _rtw_memcpy(target, pmlmeinfo->ip_addr, + RTW_IP_ADDR_LEN); - rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW, - (u8 *)&rx_dma_buff_sz); + _rtw_memcpy(pwrpriv->patterns[index].mask, + &unicast_mask, sizeof(unicast_mask)); + pwrpriv->patterns[index].len = - if (rx_dma_buff_sz == 0) { - RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__); - return _FALSE; - } + IP_OFFSET + RTW_IP_ADDR_LEN; + break; + case 2: + if (pwrpriv->wowlan_ns_offload_en == _TRUE) { + target = pwrpriv->patterns[index].content; + target += ETH_TYPE_OFFSET; + + _rtw_memcpy(target, &ipv6_protocol, + sizeof(ipv6_protocol)); + + /* ICMPv6 */ + target += (IPv6_PROTOCOL_OFFSET - + ETH_TYPE_OFFSET); + _rtw_memset(target, 0x3a, 1); + + target += (IPv6_OFFSET - IPv6_PROTOCOL_OFFSET); + _rtw_memcpy(target, pmlmeinfo->ip6_addr, + RTW_IPv6_ADDR_LEN); + + _rtw_memcpy(pwrpriv->patterns[index].mask, + &icmpv6_mask, sizeof(icmpv6_mask)); + pwrpriv->patterns[index].len = + IPv6_OFFSET + RTW_IPv6_ADDR_LEN; + } + break; + case 3: + target = pwrpriv->patterns[index].content; + _rtw_memcpy(target, &multicast_addr, + sizeof(multicast_addr)); - rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz); + target += ETH_TYPE_OFFSET; + _rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol)); - if (page_sz == 0) { - RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__); - return _FALSE; - } + /* UDP */ + target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET); + _rtw_memset(target, 0x11, 1); - offset = (u16)PageNum(rx_dma_buff_sz, page_sz); + target += (IP_OFFSET - PROTOCOL_OFFSET); + _rtw_memcpy(target, &multicast_ip, + sizeof(multicast_ip)); - cam_start_offset = offset * page_sz; + _rtw_memcpy(pwrpriv->patterns[index].mask, + &multicast_mask, sizeof(multicast_mask)); - if (IS_HARDWARE_TYPE_8188E(adapter)) { - ctrl_l = 0x0001; - ctrl_h = 0x0001; - } else { - ctrl_l = 0x0f01; - ctrl_h = 0xf001; - } - - /* Enable RX packet buffer access */ - rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT); - - /* Write the WKFM CAM */ - for (i = 0; i < WKFMCAM_ADDR_NUM; i++) { - /* - * Set Rx packet buffer offset. - * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer. - * CAM start offset (unit: 1 byte) = Index*WKFMCAM_SIZE - * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8 - * * Index: The index of the wake up frame mask - * * WKFMCAM_SIZE: the total size of one WKFM CAM - * * per entry offset of a WKFM CAM: Addr i * 4 bytes - */ - rx_buf_ptr = - (cam_start_offset + idx * WKFMCAM_SIZE + i * 4) >> 3; - rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr); - - if (i == 0) { - if (context->type == PATTERN_VALID) - data = BIT(31); - else if (context->type == PATTERN_BROADCAST) - data = BIT(31) | BIT(26); - else if (context->type == PATTERN_MULTICAST) - data = BIT(31) | BIT(25); - else if (context->type == PATTERN_UNICAST) - data = BIT(31) | BIT(24); - - if (context->crc != 0) - data |= context->crc; - - rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data); - rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l); - } else if (i == 1) { - data = 0; - rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data); - rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h); - } else if (i == 2 || i == 4) { - data = context->mask[i - 2]; - rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data); - /* write to RX packet buffer*/ - rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l); - } else if (i == 3 || i == 5) { - data = context->mask[i - 2]; - rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data); - /* write to RX packet buffer*/ - rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h); + pwrpriv->patterns[index].len = + IP_OFFSET + sizeof(multicast_ip); + break; + default: + break; } - - count = 0; - do { - tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL); - rtw_udelay_os(2); - count++; - } while (tmp && count < 100); - - if (count >= 100) - res = _FALSE; - else - res = _TRUE; } - - /* Disable RX packet buffer access */ - rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, - DISABLE_TRXPKT_BUF_ACCESS); - - return res; + return index; } - void rtw_dump_priv_pattern(_adapter *adapter, u8 idx) { struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); @@ -4499,20 +4310,13 @@ void rtw_dump_priv_pattern(_adapter *adapter, u8 idx) RTW_INFO("%s: len: %d\n", __func__, pwrctl->patterns[idx].len); } -void rtw_clean_pattern(_adapter *adapter) +void rtw_wow_pattern_sw_dump(_adapter *adapter) { - struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); - struct rtl_wow_pattern zero_pattern; - int i = 0; - - _rtw_memset(&zero_pattern, 0, sizeof(struct rtl_wow_pattern)); - - zero_pattern.type = PATTERN_INVALID; - - for (i = 0; i < MAX_WKFM_NUM; i++) - rtw_write_to_frame_mask(adapter, i, &zero_pattern); + int i; - rtw_write8(adapter, REG_WKFMCAM_NUM, 0); + RTW_INFO("********[RTK priv-patterns]*********\n"); + for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) + rtw_dump_priv_pattern(adapter, i); } void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr) @@ -4529,9 +4333,10 @@ void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr) StaAddr[3], StaAddr[4], StaAddr[5]); if (psta) { - if (psecpriv->dot11PrivacyAlgrthm != _NO_PRIVACY_ && psta->dot11txpn.val > 0) - psta->dot11txpn.val--; - AES_IV(pcur_dot11txpn, psta->dot11txpn, 0); + if (psecpriv->dot11PrivacyAlgrthm == _AES_) + AES_IV(pcur_dot11txpn, psta->dot11txpn, 0); + else if (psecpriv->dot11PrivacyAlgrthm == _TKIP_) + TKIP_IV(pcur_dot11txpn, psta->dot11txpn, 0); RTW_INFO("%s(): CurrentIV: %02x %02x %02x %02x %02x %02x %02x %02x\n" , __func__, pcur_dot11txpn[0], pcur_dot11txpn[1], @@ -4539,28 +4344,6 @@ void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr) pcur_dot11txpn[5], pcur_dot11txpn[6], pcur_dot11txpn[7]); } } -void rtw_set_sec_pn(PADAPTER padapter) -{ - struct sta_info *psta; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct security_priv *psecpriv = &padapter->securitypriv; - - psta = rtw_get_stainfo(&padapter->stapriv, - get_my_bssid(&pmlmeinfo->network)); - - if (psta) { - if (pwrpriv->wowlan_fw_iv > psta->dot11txpn.val) { - if (psecpriv->dot11PrivacyAlgrthm != _NO_PRIVACY_) - psta->dot11txpn.val = pwrpriv->wowlan_fw_iv + 2; - } else { - RTW_INFO("%s(): FW IV is smaller than driver\n", __func__); - psta->dot11txpn.val += 2; - } - RTW_INFO("%s: dot11txpn: 0x%016llx\n", __func__ , psta->dot11txpn.val); - } -} #endif /* CONFIG_WOWLAN */ #ifdef CONFIG_PNO_SUPPORT @@ -4704,7 +4487,7 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid, } /* cipher array */ - fp = filp_open("/home/timlee/wpa_kk/wpa.conf", O_RDONLY, 0644); + fp = filp_open("/data/misc/wifi/wpa_supplicant.conf", O_RDONLY, 0644); if (IS_ERR(fp)) { RTW_INFO("Error, wpa_supplicant.conf doesn't exist.\n"); RTW_INFO("Error, cipher array using default value.\n"); @@ -4724,11 +4507,11 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid, source = rtw_zmalloc(2048); if (source != NULL) { - #if(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) - len = kernel_read(fp, source, len, &pos); - #else - len = vfs_read(fp, source, len, &pos); - #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + len = kernel_read(fp, source, len, &pos); + #else + len = vfs_read(fp, source, len, &pos); + #endif rtw_parse_cipher_list(nlo_info, source); rtw_mfree(source, 2048); } @@ -4778,7 +4561,7 @@ int rtw_dev_scan_info_set(_adapter *padapter, pno_ssid_t *ssid, scan_info->ssid_channel_info[i].timeout = 100; scan_info->ssid_channel_info[i].tx_power = - PHY_GetTxPowerIndex(padapter, 0, 0x02, bw_mode, i + 1); + phy_get_tx_power_index(padapter, 0, 0x02, bw_mode, i + 1); scan_info->ssid_channel_info[i].channel = i + 1; } @@ -4823,7 +4606,7 @@ int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num, goto failing; } - pwrctl->pno_in_resume = _FALSE; + pwrctl->wowlan_in_resume = _FALSE; pwrctl->pno_inited = _TRUE; /* NLO Info */ diff --git a/core/rtw_xmit.c b/core/rtw_xmit.c index cb91217..0112c37 100644 --- a/core/rtw_xmit.c +++ b/core/rtw_xmit.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,15 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_XMIT_C_ #include +#include #if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) #error "Shall be Linux or Windows, but not both!\n" @@ -31,18 +27,15 @@ static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 }; static void _init_txservq(struct tx_servq *ptxservq) { - _func_enter_; _rtw_init_listhead(&ptxservq->tx_pending); _rtw_init_queue(&ptxservq->sta_pending); ptxservq->qcnt = 0; - _func_exit_; } void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv) { - _func_enter_; _rtw_memset((unsigned char *)psta_xmitpriv, 0, sizeof(struct sta_xmit_priv)); @@ -58,10 +51,24 @@ void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv) _rtw_init_listhead(&psta_xmitpriv->legacy_dz); _rtw_init_listhead(&psta_xmitpriv->apsd); - _func_exit_; } +void rtw_init_xmit_block(_adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + _rtw_spinlock_init(&dvobj->xmit_block_lock); + dvobj->xmit_block = XMIT_BLOCK_NONE; + +} +void rtw_free_xmit_block(_adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + _rtw_spinlock_free(&dvobj->xmit_block_lock); +} + s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) { int i; @@ -69,7 +76,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) struct xmit_frame *pxframe; sint res = _SUCCESS; - _func_enter_; /* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */ /* _rtw_memset((unsigned char *)pxmitpriv, 0, sizeof(struct xmit_priv)); */ @@ -77,7 +83,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) _rtw_spinlock_init(&pxmitpriv->lock); _rtw_spinlock_init(&pxmitpriv->lock_sctx); _rtw_init_sema(&pxmitpriv->xmit_sema, 0); - _rtw_init_sema(&pxmitpriv->terminate_xmitthread_sema, 0); /* Please insert all the queue initializaiton using _rtw_init_queue below @@ -109,7 +114,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) if (pxmitpriv->pallocated_frame_buf == NULL) { pxmitpriv->pxmit_frame_buf = NULL; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("alloc xmit_frame fail!\n")); res = _FAIL; goto exit; } @@ -147,7 +151,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4); if (pxmitpriv->pallocated_xmitbuf == NULL) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("alloc xmit_buf fail!\n")); res = _FAIL; goto exit; } @@ -201,7 +204,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) if (pxmitpriv->xframe_ext_alloc_addr == NULL) { pxmitpriv->xframe_ext = NULL; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("alloc xframe_ext fail!\n")); res = _FAIL; goto exit; } @@ -233,7 +235,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4); if (pxmitpriv->pallocated_xmit_extbuf == NULL) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("alloc xmit_extbuf fail!\n")); res = _FAIL; goto exit; } @@ -322,17 +323,21 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) rtw_sctx_init(&pxmitpriv->ack_tx_ops, 0); #endif -#ifdef TX_AMSDU - _init_timer(&(pxmitpriv->amsdu_vo_timer), padapter->pnetdev, rtw_amsdu_vo_timeout_handler, padapter); +#ifdef CONFIG_TX_AMSDU + rtw_init_timer(&(pxmitpriv->amsdu_vo_timer), padapter, + rtw_amsdu_vo_timeout_handler, padapter); pxmitpriv->amsdu_vo_timeout = RTW_AMSDU_TIMER_UNSET; - _init_timer(&(pxmitpriv->amsdu_vi_timer), padapter->pnetdev, rtw_amsdu_vi_timeout_handler, padapter); + rtw_init_timer(&(pxmitpriv->amsdu_vi_timer), padapter, + rtw_amsdu_vi_timeout_handler, padapter); pxmitpriv->amsdu_vi_timeout = RTW_AMSDU_TIMER_UNSET; - _init_timer(&(pxmitpriv->amsdu_be_timer), padapter->pnetdev, rtw_amsdu_be_timeout_handler, padapter); + rtw_init_timer(&(pxmitpriv->amsdu_be_timer), padapter, + rtw_amsdu_be_timeout_handler, padapter); pxmitpriv->amsdu_be_timeout = RTW_AMSDU_TIMER_UNSET; - _init_timer(&(pxmitpriv->amsdu_bk_timer), padapter->pnetdev, rtw_amsdu_bk_timeout_handler, padapter); + rtw_init_timer(&(pxmitpriv->amsdu_bk_timer), padapter, + rtw_amsdu_bk_timeout_handler, padapter); pxmitpriv->amsdu_bk_timeout = RTW_AMSDU_TIMER_UNSET; pxmitpriv->amsdu_debug_set_timer = 0; @@ -340,11 +345,11 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxmitpriv->amsdu_debug_coalesce_one = 0; pxmitpriv->amsdu_debug_coalesce_two = 0; #endif - + rtw_init_xmit_block(padapter); rtw_hal_init_xmit_priv(padapter); + exit: - _func_exit_; return res; } @@ -354,7 +359,6 @@ void rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv) { _rtw_spinlock_free(&pxmitpriv->lock); _rtw_free_sema(&pxmitpriv->xmit_sema); - _rtw_free_sema(&pxmitpriv->terminate_xmitthread_sema); _rtw_spinlock_free(&pxmitpriv->be_pending.lock); _rtw_spinlock_free(&pxmitpriv->bk_pending.lock); @@ -378,7 +382,6 @@ void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv) struct xmit_frame *pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf; struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; - _func_enter_; rtw_hal_free_xmit_priv(padapter); @@ -441,14 +444,288 @@ void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv) #ifdef CONFIG_XMIT_ACK _rtw_mutex_free(&pxmitpriv->ack_tx_mutex); #endif - + rtw_free_xmit_block(padapter); out: + return; +} + +u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta) +{ + u8 bw; + + bw = sta->bw_mode; + if (MLME_STATE(adapter) & WIFI_ASOC_STATE) { + if (adapter->mlmeextpriv.cur_channel <= 14) + bw = rtw_min(bw, ADAPTER_TX_BW_2G(adapter)); + else + bw = rtw_min(bw, ADAPTER_TX_BW_5G(adapter)); + } + + return bw; +} + +void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + u8 fix_bw = 0xFF; + u16 bmp_cck_ofdm = 0; + u32 bmp_ht = 0; + u32 bmp_vht = 0; + int i; + + if (adapter->fix_rate != 0xFF && adapter->fix_bw != 0xFF) + fix_bw = adapter->fix_bw; + + /* TODO: adapter->fix_rate */ + + for (i = 0; i < macid_ctl->num; i++) { + if (!rtw_macid_is_used(macid_ctl, i)) + continue; + if (rtw_macid_get_if_g(macid_ctl, i) != adapter->iface_id) + continue; + + if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */ + bmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF; + + /* bypass mismatch bandwidth for HT, VHT */ + if ((fix_bw != 0xFF && fix_bw != bw) || (fix_bw == 0xFF && macid_ctl->bw[i] != bw)) + continue; + + if (macid_ctl->vht_en[i]) + bmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20); + else + bmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20); + } + + /* TODO: mlmeext->tx_rate*/ + +exit: + if (r_bmp_cck_ofdm) + *r_bmp_cck_ofdm = bmp_cck_ofdm; + if (r_bmp_ht) + *r_bmp_ht = bmp_ht; + if (r_bmp_vht) + *r_bmp_vht = bmp_vht; +} + +void rtw_get_shared_macid_tx_rate_bmp_by_bw(struct dvobj_priv *dvobj, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht) +{ + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u16 bmp_cck_ofdm = 0; + u32 bmp_ht = 0; + u32 bmp_vht = 0; + int i; + + for (i = 0; i < macid_ctl->num; i++) { + if (!rtw_macid_is_used(macid_ctl, i)) + continue; + if (rtw_macid_get_if_g(macid_ctl, i) != -1) + continue; + + if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */ + bmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF; + + /* bypass mismatch bandwidth for HT, VHT */ + if (macid_ctl->bw[i] != bw) + continue; + + if (macid_ctl->vht_en[i]) + bmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20); + else + bmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20); + } + + if (r_bmp_cck_ofdm) + *r_bmp_cck_ofdm = bmp_cck_ofdm; + if (r_bmp_ht) + *r_bmp_ht = bmp_ht; + if (r_bmp_vht) + *r_bmp_vht = bmp_vht; +} + +void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj) +{ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); + _adapter *adapter = dvobj_get_primary_adapter(dvobj); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 bw; + u16 bmp_cck_ofdm, tmp_cck_ofdm; + u32 bmp_ht, tmp_ht, ori_bmp_ht[2]; + u8 ori_highest_ht_rate_bw_bmp; + u32 bmp_vht, tmp_vht, ori_bmp_vht[4]; + u8 ori_highest_vht_rate_bw_bmp; + int i; + + /* backup the original ht & vht highest bw bmp */ + ori_highest_ht_rate_bw_bmp = rf_ctl->highest_ht_rate_bw_bmp; + ori_highest_vht_rate_bw_bmp = rf_ctl->highest_vht_rate_bw_bmp; + + for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) { + /* backup the original ht & vht bmp */ + if (bw <= CHANNEL_WIDTH_40) + ori_bmp_ht[bw] = rf_ctl->rate_bmp_ht_by_bw[bw]; + if (bw <= CHANNEL_WIDTH_160) + ori_bmp_vht[bw] = rf_ctl->rate_bmp_vht_by_bw[bw]; + + bmp_cck_ofdm = bmp_ht = bmp_vht = 0; + if (hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw)) { + for (i = 0; i < dvobj->iface_nums; i++) { + if (!dvobj->padapters[i]) + continue; + rtw_get_adapter_tx_rate_bmp_by_bw(dvobj->padapters[i], bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht); + bmp_cck_ofdm |= tmp_cck_ofdm; + bmp_ht |= tmp_ht; + bmp_vht |= tmp_vht; + } + rtw_get_shared_macid_tx_rate_bmp_by_bw(dvobj, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht); + bmp_cck_ofdm |= tmp_cck_ofdm; + bmp_ht |= tmp_ht; + bmp_vht |= tmp_vht; + } + if (bw == CHANNEL_WIDTH_20) + rf_ctl->rate_bmp_cck_ofdm = bmp_cck_ofdm; + if (bw <= CHANNEL_WIDTH_40) + rf_ctl->rate_bmp_ht_by_bw[bw] = bmp_ht; + if (bw <= CHANNEL_WIDTH_160) + rf_ctl->rate_bmp_vht_by_bw[bw] = bmp_vht; + } + +#ifndef DBG_HIGHEST_RATE_BMP_BW_CHANGE +#define DBG_HIGHEST_RATE_BMP_BW_CHANGE 0 +#endif + + { + u8 highest_rate_bw; + u8 highest_rate_bw_bmp; + u8 update_ht_rs = _FALSE; + u8 update_vht_rs = _FALSE; + + highest_rate_bw_bmp = BW_CAP_20M; + highest_rate_bw = CHANNEL_WIDTH_20; + for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_40; bw++) { + if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_ht_by_bw[bw]) { + highest_rate_bw_bmp = ch_width_to_bw_cap(bw); + highest_rate_bw = bw; + } else if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_ht_by_bw[bw]) + highest_rate_bw_bmp |= ch_width_to_bw_cap(bw); + } + rf_ctl->highest_ht_rate_bw_bmp = highest_rate_bw_bmp; + + if (ori_highest_ht_rate_bw_bmp != rf_ctl->highest_ht_rate_bw_bmp + || largest_bit(ori_bmp_ht[highest_rate_bw]) != largest_bit(rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw]) + ) { + if (DBG_HIGHEST_RATE_BMP_BW_CHANGE) { + RTW_INFO("highest_ht_rate_bw_bmp:0x%02x=>0x%02x\n", ori_highest_ht_rate_bw_bmp, rf_ctl->highest_ht_rate_bw_bmp); + RTW_INFO("rate_bmp_ht_by_bw[%u]:0x%08x=>0x%08x\n", highest_rate_bw, ori_bmp_ht[highest_rate_bw], rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw]); + } + update_ht_rs = _TRUE; + } - _func_exit_; + highest_rate_bw_bmp = BW_CAP_20M; + highest_rate_bw = CHANNEL_WIDTH_20; + for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) { + if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_vht_by_bw[bw]) { + highest_rate_bw_bmp = ch_width_to_bw_cap(bw); + highest_rate_bw = bw; + } else if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_vht_by_bw[bw]) + highest_rate_bw_bmp |= ch_width_to_bw_cap(bw); + } + rf_ctl->highest_vht_rate_bw_bmp = highest_rate_bw_bmp; + + if (ori_highest_vht_rate_bw_bmp != rf_ctl->highest_vht_rate_bw_bmp + || largest_bit(ori_bmp_vht[highest_rate_bw]) != largest_bit(rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw]) + ) { + if (DBG_HIGHEST_RATE_BMP_BW_CHANGE) { + RTW_INFO("highest_vht_rate_bw_bmp:0x%02x=>0x%02x\n", ori_highest_vht_rate_bw_bmp, rf_ctl->highest_vht_rate_bw_bmp); + RTW_INFO("rate_bmp_vht_by_bw[%u]:0x%08x=>0x%08x\n", highest_rate_bw, ori_bmp_vht[highest_rate_bw], rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw]); + } + update_vht_rs = _TRUE; + } + /* TODO: per rfpath and rate section handling? */ + if (update_ht_rs == _TRUE || update_vht_rs == _TRUE) + rtw_hal_set_tx_power_level(dvobj_get_primary_adapter(dvobj), hal_data->current_channel); + } +} + +inline u16 rtw_get_tx_rate_bmp_cck_ofdm(struct dvobj_priv *dvobj) +{ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); + + return rf_ctl->rate_bmp_cck_ofdm; +} + +inline u32 rtw_get_tx_rate_bmp_ht_by_bw(struct dvobj_priv *dvobj, u8 bw) +{ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); + + return rf_ctl->rate_bmp_ht_by_bw[bw]; +} + +inline u32 rtw_get_tx_rate_bmp_vht_by_bw(struct dvobj_priv *dvobj, u8 bw) +{ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); + + return rf_ctl->rate_bmp_vht_by_bw[bw]; +} + +u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw) +{ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); + u8 bw; + u8 bw_bmp = 0; + u32 rate_bmp; + + if (!IS_HT_RATE(rate)) { + rtw_warn_on(1); + goto exit; + } + + rate_bmp = 1 << (rate - MGN_MCS0); + + if (max_bw > CHANNEL_WIDTH_40) + max_bw = CHANNEL_WIDTH_40; + + for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) { + /* RA may use lower rate for retry */ + if (rf_ctl->rate_bmp_ht_by_bw[bw] >= rate_bmp) + bw_bmp |= ch_width_to_bw_cap(bw); + } + +exit: + return bw_bmp; } -u8 query_ra_short_GI(struct sta_info *psta) +u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw) +{ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); + u8 bw; + u8 bw_bmp = 0; + u32 rate_bmp; + + if (!IS_VHT_RATE(rate)) { + rtw_warn_on(1); + goto exit; + } + + rate_bmp = 1 << (rate - MGN_VHT1SS_MCS0); + + if (max_bw > CHANNEL_WIDTH_160) + max_bw = CHANNEL_WIDTH_160; + + for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) { + /* RA may use lower rate for retry */ + if (rf_ctl->rate_bmp_vht_by_bw[bw] >= rate_bmp) + bw_bmp |= ch_width_to_bw_cap(bw); + } + +exit: + return bw_bmp; +} + +u8 query_ra_short_GI(struct sta_info *psta, u8 bw) { u8 sgi = _FALSE, sgi_20m = _FALSE, sgi_40m = _FALSE, sgi_80m = _FALSE; @@ -456,14 +733,12 @@ u8 query_ra_short_GI(struct sta_info *psta) #ifdef CONFIG_80211AC_VHT if (psta->vhtpriv.vht_option) sgi_80m = psta->vhtpriv.sgi_80m; -#endif /* CONFIG_80211AC_VHT */ - { - sgi_20m = psta->htpriv.sgi_20m; - sgi_40m = psta->htpriv.sgi_40m; - } +#endif + sgi_20m = psta->htpriv.sgi_20m; + sgi_40m = psta->htpriv.sgi_40m; #endif - switch (psta->bw_mode) { + switch (bw) { case CHANNEL_WIDTH_80: sgi = sgi_80m; break; @@ -605,6 +880,7 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta) { struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; + u8 bw; pattrib->rtsen = psta->rtsen; pattrib->cts2self = psta->cts2self; @@ -619,12 +895,9 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri pattrib->raid = psta->raid; - if (mlmeext->cur_bwmode < psta->bw_mode) - pattrib->bwmode = mlmeext->cur_bwmode; - else - pattrib->bwmode = psta->bw_mode; - - pattrib->sgi = query_ra_short_GI(psta); + bw = rtw_get_tx_bw_mode(padapter, psta); + pattrib->bwmode = rtw_min(bw, mlmeext->cur_bwmode); + pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode); pattrib->ldpc = psta->ldpc; pattrib->stbc = psta->stbc; @@ -638,6 +911,17 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri pattrib->ampdu_spacing = padapter->driver_ampdu_spacing; else pattrib->ampdu_spacing = psta->htpriv.rx_ampdu_min_spacing; + + /* check if enable ampdu */ + if (pattrib->ht_en && psta->htpriv.ampdu_enable) { + if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) { + pattrib->ampdu_en = _TRUE; + if (psta->htpriv.tx_amsdu_enable == _TRUE) + pattrib->amsdu_ampdu_en = _TRUE; + else + pattrib->amsdu_ampdu_en = _FALSE; + } + } #endif /* CONFIG_80211N_HT */ /* if(pattrib->ht_en && psta->htpriv.ampdu_enable) */ /* { */ @@ -651,10 +935,10 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri pattrib->raid = psta->raid; #ifdef CONFIG_80211N_HT - pattrib->bwmode = psta->bw_mode; + pattrib->bwmode = rtw_get_tx_bw_mode(padapter, psta); pattrib->ht_en = psta->htpriv.ht_option; pattrib->ch_offset = psta->htpriv.ch_offset; - pattrib->sgi = query_ra_short_GI(psta); + pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode); #endif /* CONFIG_80211N_HT */ } #endif /* CONFIG_TDLS */ @@ -680,12 +964,10 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib pattrib->mac_id = psta->mac_id; if (psta->ieee8021x_blocked == _TRUE) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("\n psta->ieee8021x_blocked == _TRUE\n")); pattrib->encrypt = 0; if ((pattrib->ether_type != 0x888e) && (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("\npsta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%.4x) != 0x888e\n", pattrib->ether_type)); #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s psta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%04x) != 0x888e\n", __FUNCTION__, pattrib->ether_type); #endif @@ -788,19 +1070,12 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib if (pattrib->encrypt > 0) _rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16); - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, - ("update_attrib: encrypt=%d securitypriv.sw_encrypt=%d\n", - pattrib->encrypt, padapter->securitypriv.sw_encrypt)); if (pattrib->encrypt && ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) { pattrib->bswenc = _TRUE; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, - ("update_attrib: encrypt=%d securitypriv.hw_decrypted=%d bswenc=_TRUE\n", - pattrib->encrypt, padapter->securitypriv.sw_encrypt)); } else { pattrib->bswenc = _FALSE; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("update_attrib: bswenc=_FALSE\n")); } #if defined(CONFIG_CONCURRENT_MODE) @@ -990,7 +1265,6 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr struct xmit_priv *pxmitpriv = &padapter->xmitpriv; sint res = _SUCCESS; - _func_enter_; DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib); @@ -1030,7 +1304,6 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr psta = rtw_get_bcmc_stainfo(padapter); if (psta == NULL) { /* if we cannot get psta => drop the pkt */ DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta); - RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT "\n", MAC_ARG(pattrib->ra))); #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra)); #endif @@ -1041,7 +1314,6 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr psta = rtw_get_stainfo(pstapriv, pattrib->ra); if (psta == NULL) { /* if we cannot get psta => drop the pkt */ DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta); - RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT"\n", MAC_ARG(pattrib->ra))); #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra)); #endif @@ -1087,8 +1359,8 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr _rtw_pktfile_read(&pktfile, udp, 8); if ((GET_UDP_SRC(udp) == 68 && GET_UDP_DST(udp) == 67) - || (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68) - ) { + || (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68) + ) { /* 67 : UDP BOOTP server, 68 : UDP BOOTP client */ if (pattrib->pktlen > 282) { /* MINIMUM_DHCP_PACKET_SIZE */ pattrib->dhcp_pkt = 1; @@ -1100,7 +1372,7 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr } else if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */ && rtw_st_ctl_chk_reg_s_proto(&psta->st_ctl, 0x06) == _TRUE - ) { + ) { u8 tcp[20]; _rtw_pktfile_read(&pktfile, tcp, 20); @@ -1209,7 +1481,6 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr exit: - _func_exit_; return res; } @@ -1252,7 +1523,6 @@ static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe) } */ - _func_enter_; #ifdef CONFIG_USB_TX_AGGREGATION hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);; @@ -1316,11 +1586,8 @@ static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe) for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { payload = (u8 *)RND4((SIZE_PTR)(payload)); - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("===curfragnum=%d, pframe= 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x,!!!\n", - curfragnum, *payload, *(payload + 1), *(payload + 2), *(payload + 3), *(payload + 4), *(payload + 5), *(payload + 6), *(payload + 7))); payload = payload + pattrib->hdrlen + pattrib->iv_len; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("curfragnum=%d pattrib->hdrlen=%d pattrib->iv_len=%d", curfragnum, pattrib->hdrlen, pattrib->iv_len)); if ((curfragnum + 1) == pattrib->nr_frags) { length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0); rtw_secmicappend(&micdata, payload, length); @@ -1329,35 +1596,18 @@ static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe) length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0); rtw_secmicappend(&micdata, payload, length); payload = payload + length + pattrib->icv_len; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("curfragnum=%d length=%d pattrib->icv_len=%d", curfragnum, length, pattrib->icv_len)); } } rtw_secgetmic(&micdata, &(mic[0])); - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic: before add mic code!!!\n")); - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic: pattrib->last_txcmdsz=%d!!!\n", pattrib->last_txcmdsz)); - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic: mic[0]=0x%.2x ,mic[1]=0x%.2x ,mic[2]=0x%.2x ,mic[3]=0x%.2x \n\ - mic[4]=0x%.2x ,mic[5]=0x%.2x ,mic[6]=0x%.2x ,mic[7]=0x%.2x !!!!\n", - mic[0], mic[1], mic[2], mic[3], mic[4], mic[5], mic[6], mic[7])); /* add mic code and add the mic code length in last_txcmdsz */ _rtw_memcpy(payload, &(mic[0]), 8); pattrib->last_txcmdsz += 8; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("\n ========last pkt========\n")); payload = payload - pattrib->last_txcmdsz + 8; - for (curfragnum = 0; curfragnum < pattrib->last_txcmdsz; curfragnum = curfragnum + 8) - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, (" %.2x, %.2x, %.2x, %.2x, %.2x, %.2x, %.2x, %.2x ", - *(payload + curfragnum), *(payload + curfragnum + 1), *(payload + curfragnum + 2), *(payload + curfragnum + 3), - *(payload + curfragnum + 4), *(payload + curfragnum + 5), *(payload + curfragnum + 6), *(payload + curfragnum + 7))); } - /* - else{ - RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: rtw_get_stainfo==NULL!!!\n")); - } - */ } - _func_exit_; return _SUCCESS; } @@ -1370,7 +1620,6 @@ static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe struct pkt_attrib *pattrib = &pxmitframe->attrib; /* struct security_priv *psecuritypriv=&padapter->securitypriv; */ - _func_enter_; /* if((psecuritypriv->sw_encrypt)||(pattrib->bswenc)) */ if (pattrib->bswenc) { @@ -1379,7 +1628,6 @@ static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe ADPT_ARG(padapter), security_type_str(pattrib->encrypt)); #endif - RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("### xmitframe_swencrypt\n")); switch (pattrib->encrypt) { case _WEP40_: case _WEP104_: @@ -1399,10 +1647,8 @@ static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe break; } - } else - RT_TRACE(_module_rtl871x_xmit_c_, _drv_notice_, ("### xmitframe_hwencrypt\n")); + } - _func_exit_; return _SUCCESS; } @@ -1422,7 +1668,6 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) /* sint bmcst = IS_MCAST(pattrib->ra); */ - _func_enter_; /* psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); @@ -1447,7 +1692,7 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) _rtw_memset(hdr, 0, WLANHDR_OFFSET); - SetFrameSubType(fctrl, pattrib->subtype); + set_frame_sub_type(fctrl, pattrib->subtype); if (pattrib->subtype & WIFI_DATA_TYPE) { if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) { @@ -1492,7 +1737,6 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) if (pattrib->qos_en) qos_option = _TRUE; } else { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("fw_state:%x is not allowed to xmit frame\n", get_fwstate(pmlmepriv))); res = _FAIL; goto exit; } @@ -1547,12 +1791,13 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) SetSeqNum(hdr, pattrib->seqnum); #ifdef CONFIG_80211N_HT +#if 0 /* move into update_attrib_phy_info(). */ /* check if enable ampdu */ if (pattrib->ht_en && psta->htpriv.ampdu_enable) { if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) pattrib->ampdu_en = _TRUE; } - +#endif /* re-check if enable ampdu by BA_starting_seqctrl */ if (pattrib->ampdu_en == _TRUE) { u16 tx_seq; @@ -1584,7 +1829,6 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) exit: - _func_exit_; return res; } @@ -1720,11 +1964,10 @@ s32 rtw_make_tdls_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattr sint res = _SUCCESS; u16 *fctrl = &pwlanhdr->frame_ctl; - _func_enter_; _rtw_memset(hdr, 0, WLANHDR_OFFSET); - SetFrameSubType(fctrl, pattrib->subtype); + set_frame_sub_type(fctrl, pattrib->subtype); switch (ptxmgmt->action_code) { case TDLS_SETUP_REQUEST: @@ -1810,7 +2053,6 @@ s32 rtw_make_tdls_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattr exit: - _func_exit_; return res; } @@ -1829,7 +2071,6 @@ s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, st s32 bmcst = IS_MCAST(pattrib->ra); s32 res = _SUCCESS; - _func_enter_; if (pattrib->psta) psta = pattrib->psta; @@ -1918,7 +2159,6 @@ s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, st exit: - _func_exit_; return res; } @@ -1942,12 +2182,11 @@ u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib) return len; } -#ifdef TX_AMSDU - +#ifdef CONFIG_TX_AMSDU s32 check_amsdu(struct xmit_frame *pxmitframe) { struct pkt_attrib *pattrib; - int ret = _TRUE; + s32 ret = _TRUE; if (!pxmitframe) ret = _FALSE; @@ -1974,6 +2213,28 @@ s32 check_amsdu(struct xmit_frame *pxmitframe) return ret; } +s32 check_amsdu_tx_support(_adapter *padapter) +{ + struct dvobj_priv *pdvobjpriv; + int tx_amsdu; + int tx_amsdu_rate; + int current_tx_rate; + s32 ret = _FALSE; + + pdvobjpriv = adapter_to_dvobj(padapter); + tx_amsdu = padapter->tx_amsdu; + tx_amsdu_rate = padapter->tx_amsdu_rate; + current_tx_rate = pdvobjpriv->traffic_stat.cur_tx_tp; + + if (tx_amsdu == 1) + ret = _TRUE; + else if (tx_amsdu == 2 && (tx_amsdu_rate == 0 || current_tx_rate > tx_amsdu_rate)) + ret = _TRUE; + else + ret = _FALSE; + + return ret; +} s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue) { @@ -1997,9 +2258,6 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra u8 *pbuf_start; s32 res = _SUCCESS; - _func_enter_; - - if (pxmitframe->buf_addr == NULL) { RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__); return _FAIL; @@ -2142,12 +2400,10 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra pattrib->vcs_mode = NONE_VCS; exit: - - _func_exit_; - return res; } -#endif +#endif /* CONFIG_TX_AMSDU */ + /* This sub-routine will perform all the following: @@ -2183,7 +2439,6 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm s32 bmcst = IS_MCAST(pattrib->ra); s32 res = _SUCCESS; - _func_enter_; /* if (pattrib->psta) @@ -2229,7 +2484,6 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm mem_start = pbuf_start + hw_hdr_offset; if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n")); RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n"); res = _FAIL; goto exit; @@ -2289,9 +2543,6 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm #endif _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); - RT_TRACE(_module_rtl871x_xmit_c_, _drv_notice_, - ("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n", - padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3))); pframe += pattrib->iv_len; @@ -2332,8 +2583,7 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm ClearMFrag(mem_start); break; - } else - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("%s: There're still something in packet!\n", __FUNCTION__)); + } addr = (SIZE_PTR)(pframe); @@ -2343,7 +2593,6 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm } if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n")); RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"); res = _FAIL; goto exit; @@ -2358,7 +2607,6 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm exit: - _func_exit_; return res; } @@ -2391,10 +2639,9 @@ s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame mem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - _func_enter_; ori_len = BIP_AAD_SIZE + pattrib->pktlen; tmp_buf = BIP_AAD = rtw_zmalloc(ori_len); - subtype = GetFrameSubType(pframe); /* bit(7)~bit(2) */ + subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */ if (BIP_AAD == NULL) return _FAIL; @@ -2415,7 +2662,7 @@ s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame _rtw_memset(MME, 0, _MME_IE_LENGTH_); /* other types doesn't need the BIP */ - if (GetFrameSubType(pframe) != WIFI_DEAUTH && GetFrameSubType(pframe) != WIFI_DISASSOC) + if (get_frame_sub_type(pframe) != WIFI_DEAUTH && get_frame_sub_type(pframe) != WIFI_DISASSOC) goto xmitframe_coalesce_fail; MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); @@ -2591,13 +2838,11 @@ s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame xmitframe_coalesce_success: _exit_critical_bh(&padapter->security_key_mutex, &irqL); rtw_mfree(BIP_AAD, ori_len); - _func_exit_; return _SUCCESS; xmitframe_coalesce_fail: _exit_critical_bh(&padapter->security_key_mutex, &irqL); rtw_mfree(BIP_AAD, ori_len); - _func_exit_; return _FAIL; } @@ -2615,7 +2860,6 @@ s32 rtw_put_snap(u8 *data, u16 h_proto) struct ieee80211_snap_hdr *snap; u8 *oui; - _func_enter_; snap = (struct ieee80211_snap_hdr *)data; snap->dsap = 0xaa; @@ -2633,7 +2877,6 @@ s32 rtw_put_snap(u8 *data, u16 h_proto) *(u16 *)(data + SNAP_SIZE) = htons(h_proto); - _func_exit_; return SNAP_SIZE + sizeof(u16); } @@ -2647,7 +2890,6 @@ void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len) struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct registry_priv *pregistrypriv = &padapter->registrypriv; - _func_enter_; switch (pxmitpriv->vcs_setting) { case DISABLE_VCS: @@ -2677,7 +2919,6 @@ void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len) } - _func_exit_; } @@ -2727,7 +2968,6 @@ static struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv, { struct xmit_buf *pxmitbuf = NULL; - _func_enter_; pxmitbuf = &pxmitpriv->pcmd_xmitbuf[buf_type]; if (pxmitbuf != NULL) { @@ -2757,7 +2997,6 @@ static struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv, exit: - _func_exit_; return pxmitbuf; } @@ -2787,6 +3026,9 @@ struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, pcmdframe->buf_addr = pxmitbuf->pbuf; + /* initial memory to zero */ + _rtw_memset(pcmdframe->buf_addr, 0, MAX_CMDBUF_SZ); + pxmitbuf->priv_data = pcmdframe; return pcmdframe; @@ -2800,7 +3042,6 @@ struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv) _list *plist, *phead; _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; - _func_enter_; _enter_critical(&pfree_queue->lock, &irqL); @@ -2849,7 +3090,6 @@ struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv) _exit_critical(&pfree_queue->lock, &irqL); - _func_exit_; return pxmitbuf; } @@ -2859,7 +3099,6 @@ s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) _irqL irqL; _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; - _func_enter_; if (pxmitbuf == NULL) return _FAIL; @@ -2876,7 +3115,6 @@ s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) _exit_critical(&pfree_queue->lock, &irqL); - _func_exit_; return _SUCCESS; } @@ -2888,7 +3126,6 @@ struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv) _list *plist, *phead; _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; - _func_enter_; /* RTW_INFO("+rtw_alloc_xmitbuf\n"); */ @@ -2943,7 +3180,6 @@ struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv) _exit_critical(&pfree_xmitbuf_queue->lock, &irqL); - _func_exit_; return pxmitbuf; } @@ -2953,7 +3189,6 @@ s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) _irqL irqL; _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; - _func_enter_; /* RTW_INFO("+rtw_free_xmitbuf\n"); */ @@ -2983,7 +3218,6 @@ s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) _exit_critical(&pfree_xmitbuf_queue->lock, &irqL); } - _func_exit_; return _SUCCESS; } @@ -3049,12 +3283,10 @@ struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv)/* (_queue *p _list *plist, *phead; _queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue; - _func_enter_; _enter_critical_bh(&pfree_xmit_queue->lock, &irqL); if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe:%d\n", pxmitpriv->free_xmitframe_cnt)); pxframe = NULL; } else { phead = get_list_head(pfree_xmit_queue); @@ -3065,14 +3297,12 @@ struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv)/* (_queue *p rtw_list_delete(&(pxframe->list)); pxmitpriv->free_xmitframe_cnt--; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe():free_xmitframe_cnt=%d\n", pxmitpriv->free_xmitframe_cnt)); } _exit_critical_bh(&pfree_xmit_queue->lock, &irqL); rtw_init_xmitframe(pxframe); - _func_exit_; return pxframe; } @@ -3084,12 +3314,10 @@ struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv) _list *plist, *phead; _queue *queue = &pxmitpriv->free_xframe_ext_queue; - _func_enter_; _enter_critical_bh(&queue->lock, &irqL); if (_rtw_queue_empty(queue) == _TRUE) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe_ext:%d\n", pxmitpriv->free_xframe_ext_cnt)); pxframe = NULL; } else { phead = get_list_head(queue); @@ -3098,14 +3326,12 @@ struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv) rtw_list_delete(&(pxframe->list)); pxmitpriv->free_xframe_ext_cnt--; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe_ext():free_xmitframe_cnt=%d\n", pxmitpriv->free_xframe_ext_cnt)); } _exit_critical_bh(&queue->lock, &irqL); rtw_init_xmitframe(pxframe); - _func_exit_; return pxframe; } @@ -3146,10 +3372,8 @@ s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitfram _adapter *padapter = pxmitpriv->adapter; _pkt *pndis_pkt = NULL; - _func_enter_; if (pxmitframe == NULL) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("======rtw_free_xmitframe():pxmitframe==NULL!!!!!!!!!!\n")); goto exit; } @@ -3177,10 +3401,8 @@ s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitfram rtw_list_insert_tail(&pxmitframe->list, get_list_head(queue)); if (pxmitframe->ext_tag == 0) { pxmitpriv->free_xmitframe_cnt++; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_debug_, ("rtw_free_xmitframe():free_xmitframe_cnt=%d\n", pxmitpriv->free_xmitframe_cnt)); } else if (pxmitframe->ext_tag == 1) { pxmitpriv->free_xframe_ext_cnt++; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_debug_, ("rtw_free_xmitframe():free_xframe_ext_cnt=%d\n", pxmitpriv->free_xframe_ext_cnt)); } else { } @@ -3193,7 +3415,6 @@ s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitfram exit: - _func_exit_; return _SUCCESS; } @@ -3204,7 +3425,6 @@ void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue) _list *plist, *phead; struct xmit_frame *pxmitframe; - _func_enter_; _enter_critical_bh(&(pframequeue->lock), &irqL); @@ -3222,15 +3442,12 @@ void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue) } _exit_critical_bh(&(pframequeue->lock), &irqL); - _func_exit_; } s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) { DBG_COUNTER(padapter->tx_logs.core_tx_enqueue); if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, - ("rtw_xmitframe_enqueue: drop xmit pkt for classifier fail\n")); /* pxmitframe->pkt = NULL; */ return _FAIL; } @@ -3315,8 +3532,6 @@ struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame) /* int j, tmp, acirp_cnt[4]; */ #endif - _func_enter_; - inx[0] = 0; inx[1] = 1; inx[2] = 2; @@ -3356,8 +3571,6 @@ struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame) _exit_critical_bh(&pxmitpriv->lock, &irqL0); - _func_exit_; - return pxmitframe; } @@ -3377,7 +3590,6 @@ struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmi /* int j, tmp, acirp_cnt[4]; */ #endif - _func_enter_; inx[0] = 0; inx[1] = 1; @@ -3442,8 +3654,6 @@ struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmi _exit_critical_bh(&pxmitpriv->lock, &irqL0); - _func_exit_; - return pxmitframe; } @@ -3452,28 +3662,24 @@ struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, { struct tx_servq *ptxservq = NULL; - _func_enter_; switch (up) { case 1: case 2: ptxservq = &(psta->sta_xmitpriv.bk_q); *(ac) = 3; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : BK\n")); break; case 4: case 5: ptxservq = &(psta->sta_xmitpriv.vi_q); *(ac) = 1; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : VI\n")); break; case 6: case 7: ptxservq = &(psta->sta_xmitpriv.vo_q); *(ac) = 0; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : VO\n")); break; case 0: @@ -3481,12 +3687,10 @@ struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, default: ptxservq = &(psta->sta_xmitpriv.be_q); *(ac) = 2; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : BE\n")); break; } - _func_exit_; return ptxservq; } @@ -3497,7 +3701,6 @@ __inline static struct tx_servq *rtw_get_sta_pending struct tx_servq *ptxservq; struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; - _func_enter_; #ifdef CONFIG_RTL8711 @@ -3513,7 +3716,6 @@ __inline static struct tx_servq *rtw_get_sta_pending ptxservq = &(psta->sta_xmitpriv.bk_q); *ppstapending = &padapter->xmitpriv.bk_pending; (phwxmits + 3)->accnt++; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : BK\n")); break; case 4: @@ -3521,7 +3723,6 @@ __inline static struct tx_servq *rtw_get_sta_pending ptxservq = &(psta->sta_xmitpriv.vi_q); *ppstapending = &padapter->xmitpriv.vi_pending; (phwxmits + 1)->accnt++; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : VI\n")); break; case 6: @@ -3529,7 +3730,6 @@ __inline static struct tx_servq *rtw_get_sta_pending ptxservq = &(psta->sta_xmitpriv.vo_q); *ppstapending = &padapter->xmitpriv.vo_pending; (phwxmits + 0)->accnt++; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : VO\n")); break; case 0: @@ -3538,14 +3738,12 @@ __inline static struct tx_servq *rtw_get_sta_pending ptxservq = &(psta->sta_xmitpriv.be_q); *ppstapending = &padapter->xmitpriv.be_pending; (phwxmits + 2)->accnt++; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : BE\n")); break; } } - _func_exit_; return ptxservq; } @@ -3566,7 +3764,6 @@ s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe) struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; sint res = _SUCCESS; - _func_enter_; DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class); @@ -3590,7 +3787,6 @@ s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe) DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_nosta); res = _FAIL; RTW_INFO("rtw_xmit_classifier: psta == NULL\n"); - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmit_classifier: psta == NULL\n")); goto exit; } @@ -3619,7 +3815,6 @@ s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe) exit: - _func_exit_; return res; } @@ -3701,14 +3896,12 @@ void rtw_free_hwxmits(_adapter *padapter) void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry) { sint i; - _func_enter_; for (i = 0; i < entry; i++, phwxmit++) { /* _rtw_spinlock_init(&phwxmit->xmit_lock); */ /* _rtw_init_listhead(&phwxmit->pending); */ /* phwxmit->txcmdcnt = 0; */ phwxmit->accnt = 0; } - _func_exit_; } #ifdef CONFIG_BR_EXT @@ -3934,7 +4127,6 @@ static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib) u8 qsel; qsel = pattrib->priority; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("### do_queue_select priority=%d ,qsel = %d\n", pattrib->priority , qsel)); #ifdef CONFIG_CONCURRENT_MODE /* if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) @@ -3970,6 +4162,7 @@ static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib) * 0 success, hardware will handle this xmit frame(packet) * <0 fail */ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) { int ret = 0; @@ -4102,7 +4295,7 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) return 0; } - +#endif /* * The main transmit(tx) entry * @@ -4925,7 +5118,7 @@ struct xmit_buf *dequeue_pending_xmitbuf( return pxmitbuf; } -struct xmit_buf *dequeue_pending_xmitbuf_under_survey( +static struct xmit_buf *dequeue_pending_xmitbuf_under_survey( struct xmit_priv *pxmitpriv) { _irqL irql; @@ -4943,7 +5136,7 @@ struct xmit_buf *dequeue_pending_xmitbuf_under_survey( if (_rtw_queue_empty(pqueue) == _FALSE) { _list *plist, *phead; - u8 type; + u8 type = 0; phead = get_list_head(pqueue); plist = phead; @@ -4957,11 +5150,11 @@ struct xmit_buf *dequeue_pending_xmitbuf_under_survey( #ifdef CONFIG_USB_HCI pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; if (pxmitframe) - type = GetFrameSubType(pxmitbuf->pbuf + TXDESC_SIZE + pxmitframe->pkt_offset * PACKET_OFFSET_SZ); + type = get_frame_sub_type(pxmitbuf->pbuf + TXDESC_SIZE + pxmitframe->pkt_offset * PACKET_OFFSET_SZ); else RTW_INFO("%s, !!!ERROR!!! For USB, TODO ITEM\n", __FUNCTION__); #else - type = GetFrameSubType(pxmitbuf->pbuf + TXDESC_OFFSET); + type = get_frame_sub_type(pxmitbuf->pbuf + TXDESC_OFFSET); #endif if ((type == WIFI_PROBEREQ) || @@ -4979,6 +5172,63 @@ struct xmit_buf *dequeue_pending_xmitbuf_under_survey( return pxmitbuf; } +static struct xmit_buf *dequeue_pending_xmitbuf_ext( + struct xmit_priv *pxmitpriv) +{ + _irqL irql; + struct xmit_buf *pxmitbuf; + _queue *pqueue; + + pxmitbuf = NULL; + pqueue = &pxmitpriv->pending_xmitbuf_queue; + + _enter_critical_bh(&pqueue->lock, &irql); + + if (_rtw_queue_empty(pqueue) == _FALSE) { + _list *plist, *phead; + u8 type = 0; + + phead = get_list_head(pqueue); + plist = phead; + do { + plist = get_next(plist); + if (plist == phead) + break; + + pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); + + if (pxmitbuf->buf_tag == XMITBUF_MGNT) { + rtw_list_delete(&pxmitbuf->list); + break; + } + pxmitbuf = NULL; + } while (1); + } + + _exit_critical_bh(&pqueue->lock, &irql); + + return pxmitbuf; +} + +struct xmit_buf *select_and_dequeue_pending_xmitbuf(_adapter *padapter) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_buf *pxmitbuf = NULL; + + if (_TRUE == rtw_is_xmit_blocked(padapter)) + return pxmitbuf; + + if (rtw_xmit_ac_blocked(padapter) == _TRUE) + pxmitbuf = dequeue_pending_xmitbuf_under_survey(pxmitpriv); + else { + pxmitbuf = dequeue_pending_xmitbuf_ext(pxmitpriv); + if (pxmitbuf == NULL) + pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv); + } + + return pxmitbuf; +} + sint check_pending_xmitbuf( struct xmit_priv *pxmitpriv) { @@ -5014,12 +5264,74 @@ thread_return rtw_xmit_thread(thread_context context) flush_signals_thread(); } while (_SUCCESS == err); - _rtw_up_sema(&padapter->xmitpriv.terminate_xmitthread_sema); + RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter)); - thread_exit(); + rtw_thread_wait_stop(); + + return 0; } #endif +#ifdef DBG_XMIT_BLOCK +void dump_xmit_block(void *sel, _adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + RTW_PRINT_SEL(sel, "[XMIT-BLOCK] xmit_block :0x%02x\n", dvobj->xmit_block); + if (dvobj->xmit_block & XMIT_BLOCK_REDLMEM) + RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_REDLMEM"); + if (dvobj->xmit_block & XMIT_BLOCK_SUSPEND) + RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_SUSPEND"); + if (dvobj->xmit_block == XMIT_BLOCK_NONE) + RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_NONE"); +} +void dump_xmit_block_info(void *sel, const char *fun_name, _adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + RTW_INFO("\n"ADPT_FMT" call %s\n", ADPT_ARG(padapter), fun_name); + dump_xmit_block(sel, padapter); +} +#define DBG_XMIT_BLOCK_DUMP(adapter) dump_xmit_block_info(RTW_DBGDUMP, __func__, adapter) +#endif + +void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason) +{ + _irqL irqL; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + _enter_critical_bh(&dvobj->xmit_block_lock, &irqL); + dvobj->xmit_block |= reason; + _exit_critical_bh(&dvobj->xmit_block_lock, &irqL); + + #ifdef DBG_XMIT_BLOCK + DBG_XMIT_BLOCK_DUMP(padapter); + #endif +} + +void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason) +{ + _irqL irqL; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + _enter_critical_bh(&dvobj->xmit_block_lock, &irqL); + dvobj->xmit_block &= ~reason; + _exit_critical_bh(&dvobj->xmit_block_lock, &irqL); + + #ifdef DBG_XMIT_BLOCK + DBG_XMIT_BLOCK_DUMP(padapter); + #endif +} +bool rtw_is_xmit_blocked(_adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + #ifdef DBG_XMIT_BLOCK + DBG_XMIT_BLOCK_DUMP(padapter); + #endif + return ((dvobj->xmit_block) ? _TRUE : _FALSE); +} + bool rtw_xmit_ac_blocked(_adapter *adapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); @@ -5035,15 +5347,15 @@ bool rtw_xmit_ac_blocked(_adapter *adapter) /* check scan state */ if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE - && mlmeext_scan_state(mlmeext) != SCAN_BACK_OP - ) { + && mlmeext_scan_state(mlmeext) != SCAN_BACK_OP + ) { blocked = _TRUE; goto exit; } if (mlmeext_scan_state(mlmeext) == SCAN_BACK_OP - && !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME) - ) { + && !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME) + ) { blocked = _TRUE; goto exit; } @@ -5064,7 +5376,7 @@ bool rtw_xmit_ac_blocked(_adapter *adapter) return blocked; } -#ifdef TX_AMSDU +#ifdef CONFIG_TX_AMSDU void rtw_amsdu_vo_timeout_handler(void *FunctionContext) { _adapter *adapter = (_adapter *)FunctionContext; @@ -5073,6 +5385,7 @@ void rtw_amsdu_vo_timeout_handler(void *FunctionContext) tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet); } + void rtw_amsdu_vi_timeout_handler(void *FunctionContext) { _adapter *adapter = (_adapter *)FunctionContext; @@ -5081,6 +5394,7 @@ void rtw_amsdu_vi_timeout_handler(void *FunctionContext) tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet); } + void rtw_amsdu_be_timeout_handler(void *FunctionContext) { _adapter *adapter = (_adapter *)FunctionContext; @@ -5092,6 +5406,7 @@ void rtw_amsdu_be_timeout_handler(void *FunctionContext) tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet); } + void rtw_amsdu_bk_timeout_handler(void *FunctionContext) { _adapter *adapter = (_adapter *)FunctionContext; @@ -5129,6 +5444,7 @@ u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority) } return status; } + void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status) { struct xmit_priv *pxmitpriv = &padapter->xmitpriv; @@ -5154,6 +5470,7 @@ void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status) break; } } + void rtw_amsdu_set_timer(_adapter *padapter, u8 priority) { struct xmit_priv *pxmitpriv = &padapter->xmitpriv; @@ -5182,11 +5499,11 @@ void rtw_amsdu_set_timer(_adapter *padapter, u8 priority) } _set_timer(amsdu_timer, 1); } + void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority) { struct xmit_priv *pxmitpriv = &padapter->xmitpriv; _timer* amsdu_timer = NULL; - u8 cancel; switch(priority) { @@ -5208,9 +5525,9 @@ void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority) amsdu_timer = &pxmitpriv->amsdu_be_timer; break; } - _cancel_timer(amsdu_timer, &cancel); + _cancel_timer_ex(amsdu_timer); } -#endif +#endif /* CONFIG_TX_AMSDU */ void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms) { @@ -5278,63 +5595,8 @@ void rtw_sctx_done(struct submit_ctx **sctx) } #ifdef CONFIG_XMIT_ACK - -#ifdef CONFIG_XMIT_ACK_POLLING -s32 c2h_evt_hdl(_adapter *adapter, u8 *c2h_evt, c2h_id_filter filter); - -/** - * rtw_ack_tx_polling - - * @pxmitpriv: xmit_priv to address ack_tx_ops - * @timeout_ms: timeout msec - * - * Init ack_tx_ops and then do c2h_evt_hdl() and polling ack_tx_ops repeatedly - * till tx report or timeout - * Returns: _SUCCESS if TX report ok, _FAIL for others - */ -int rtw_ack_tx_polling(struct xmit_priv *pxmitpriv, u32 timeout_ms) -{ - int ret = _FAIL; - struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops; - _adapter *adapter = container_of(pxmitpriv, _adapter, xmitpriv); - - pack_tx_ops->submit_time = rtw_get_current_time(); - pack_tx_ops->timeout_ms = timeout_ms; - pack_tx_ops->status = RTW_SCTX_SUBMITTED; - - do { - c2h_evt_hdl(adapter, NULL, rtw_hal_c2h_id_filter_ccx(adapter)); - if (pack_tx_ops->status != RTW_SCTX_SUBMITTED) - break; - - if (rtw_is_drv_stopped(adapter)) { - pack_tx_ops->status = RTW_SCTX_DONE_DRV_STOP; - break; - } - if (rtw_is_surprise_removed(adapter)) { - pack_tx_ops->status = RTW_SCTX_DONE_DEV_REMOVE; - break; - } - - rtw_msleep_os(10); - } while (rtw_get_passing_time_ms(pack_tx_ops->submit_time) < timeout_ms); - - if (pack_tx_ops->status == RTW_SCTX_SUBMITTED) { - pack_tx_ops->status = RTW_SCTX_DONE_TIMEOUT; - RTW_INFO("%s timeout\n", __func__); - } - - if (pack_tx_ops->status == RTW_SCTX_DONE_SUCCESS) - ret = _SUCCESS; - - return ret; -} -#endif - int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms) { -#ifdef CONFIG_XMIT_ACK_POLLING - return rtw_ack_tx_polling(pxmitpriv, timeout_ms); -#else struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops; pack_tx_ops->submit_time = rtw_get_current_time(); @@ -5342,7 +5604,6 @@ int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms) pack_tx_ops->status = RTW_SCTX_SUBMITTED; return rtw_sctx_wait(pack_tx_ops, __func__); -#endif } void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status) diff --git a/hal/HalPwrSeqCmd.c b/hal/HalPwrSeqCmd.c index 411b3c6..6a2f9a6 100644 --- a/hal/HalPwrSeqCmd.c +++ b/hal/HalPwrSeqCmd.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /*++ Copyright (c) Realtek Semiconductor Corp. All rights reserved. @@ -63,16 +58,6 @@ u8 HalPwrSeqCmdParsing( do { PwrCfgCmd = PwrSeqCmd[AryIdx]; - RT_TRACE(_module_hal_init_c_ , _drv_info_, - ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n", - GET_PWR_CFG_OFFSET(PwrCfgCmd), - GET_PWR_CFG_CUT_MASK(PwrCfgCmd), - GET_PWR_CFG_FAB_MASK(PwrCfgCmd), - GET_PWR_CFG_INTF_MASK(PwrCfgCmd), - GET_PWR_CFG_BASE(PwrCfgCmd), - GET_PWR_CFG_CMD(PwrCfgCmd), - GET_PWR_CFG_MASK(PwrCfgCmd), - GET_PWR_CFG_VALUE(PwrCfgCmd))); /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */ if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) && @@ -80,11 +65,9 @@ u8 HalPwrSeqCmdParsing( (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) { switch (GET_PWR_CFG_CMD(PwrCfgCmd)) { case PWR_CMD_READ: - RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n")); break; case PWR_CMD_WRITE: - RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n")); offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); #ifdef CONFIG_SDIO_HCI @@ -120,7 +103,6 @@ u8 HalPwrSeqCmdParsing( break; case PWR_CMD_POLLING: - RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n")); bPollingBit = _FALSE; offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); @@ -151,7 +133,6 @@ u8 HalPwrSeqCmdParsing( break; case PWR_CMD_DELAY: - RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n")); if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US) rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)); else @@ -160,12 +141,10 @@ u8 HalPwrSeqCmdParsing( case PWR_CMD_END: /* When this command is parsed, end the process */ - RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n")); return _TRUE; break; default: - RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n")); break; } } diff --git a/hal/btc/halbtc8723d1ant.c b/hal/btc/halbtc8723d1ant.c index f877b20..5340c1b 100644 --- a/hal/btc/halbtc8723d1ant.c +++ b/hal/btc/halbtc8723d1ant.c @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ /* ************************************************************ * Description: * @@ -11,7 +25,7 @@ /* ************************************************************ * include files * ************************************************************ */ -#include "Mp_Precomp.h" +#include "mp_precomp.h" #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) @@ -33,9 +47,21 @@ const char *const glbt_info_src_8723d_1ant[] = { "BT Info[bt rsp]", "BT Info[bt auto report]", }; +/* ************************************************************ + * BtCoex Version Format: + * 1. date : glcoex_ver_date_XXXXX_1ant + * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant + * 3. BtCoexVersion : glcoex_ver_btdesired_XXXXX_1ant + * 4. others : glcoex_ver_XXXXXX_XXXXX_1ant + * + * Variable should be indicated IC and Antenna numbers !!! + * Please strictly follow this order and naming style !!! + * + * ************************************************************ */ +u32 glcoex_ver_date_8723d_1ant = 20161108; +u32 glcoex_ver_8723d_1ant = 0x10; +u32 glcoex_ver_btdesired_8723d_1ant = 0x10; -u32 glcoex_ver_date_8723d_1ant = 20160218; -u32 glcoex_ver_8723d_1ant = 0x05; /* ************************************************************ * local function proto type if needed @@ -324,8 +350,6 @@ void halbtc8723d1ant_query_bt_info(IN struct btc_coexist *btcoexist) { u8 h2c_parameter[1] = {0}; - coex_sta->c2h_bt_info_req_sent = true; - h2c_parameter[0] |= BIT(0); /* trigger */ btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); @@ -337,10 +361,11 @@ void halbtc8723d1ant_query_bt_info(IN struct btc_coexist *btcoexist) void halbtc8723d1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) { - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0, cnt_slave = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, + cnt_autoslot_hang = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ @@ -361,28 +386,48 @@ void halbtc8723d1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) coex_sta->low_priority_tx = reg_lp_tx; coex_sta->low_priority_rx = reg_lp_rx; + if (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + if (coex_sta->high_priority_rx >= 15) { + if (cnt_overhead < 3) + cnt_overhead++; + + if (cnt_overhead == 3) + coex_sta->is_hiPri_rx_overhead = true; + } else { + if (cnt_overhead > 0) + cnt_overhead--; + + if (cnt_overhead == 0) + coex_sta->is_hiPri_rx_overhead = false; + } + } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", - reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); + "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); BTC_TRACE(trace_buf); /* reset counter */ btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - if ((coex_sta->low_priority_tx > 1150) && - (!coex_sta->c2h_bt_inquiry_page)) + if ((coex_sta->low_priority_tx > 1150) && + (!coex_sta->c2h_bt_inquiry_page)) coex_sta->pop_event_cnt++; - if ((coex_sta->low_priority_rx >= 1150) && (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) - && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && (coex_sta->bt_link_exist)) { - if (cnt_slave >= 3) { + if ((coex_sta->low_priority_rx >= 1150) && + (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) + && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && + (coex_sta->bt_link_exist)) { + if (cnt_slave >= 2) { bt_link_info->slave_role = true; - cnt_slave = 3; + cnt_slave = 2; } else cnt_slave++; } else { - if (cnt_slave == 0) { + if (cnt_slave == 0) { bt_link_info->slave_role = false; cnt_slave = 0; } else @@ -390,186 +435,199 @@ void halbtc8723d1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) } - if ((coex_sta->high_priority_tx == 0) && (coex_sta->high_priority_rx == 0) && (coex_sta->low_priority_tx == 0) && - (coex_sta->low_priority_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8723d1ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; + if (coex_sta->is_tdma_btautoslot) { + if ((coex_sta->low_priority_tx >= 1300) && + (coex_sta->low_priority_rx <= 150)) { + if (cnt_autoslot_hang >= 2) { + coex_sta->is_tdma_btautoslot_hang = true; + cnt_autoslot_hang = 2; + } else + cnt_autoslot_hang++; + } else { + if (cnt_autoslot_hang == 0) { + coex_sta->is_tdma_btautoslot_hang = false; + cnt_autoslot_hang = 0; + } else + cnt_autoslot_hang--; } } -#if 0 - /* Add Hi-Pri Tx/Rx counter to avoid false detection */ - if (((coex_sta->hid_exist) || (coex_sta->sco_exist)) && - (coex_sta->high_priority_tx + coex_sta->high_priority_rx - >= 160) - && (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->bt_hi_pri_link_exist = true; - else - coex_sta->bt_hi_pri_link_exist = false; + if (!coex_sta->bt_disabled) { - if ((coex_sta->acl_busy) && - (coex_sta->num_of_profile == 0)) { - if (coex_sta->low_priority_tx + - coex_sta->low_priority_rx >= 160) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - coex_sta->wrong_profile_notification++; + if ((coex_sta->high_priority_tx == 0) && + (coex_sta->high_priority_rx == 0) && + (coex_sta->low_priority_tx == 0) && + (coex_sta->low_priority_rx == 0)) { + num_of_bt_counter_chk++; + if (num_of_bt_counter_chk >= 3) { + halbtc8723d1ant_query_bt_info(btcoexist); + num_of_bt_counter_chk = 0; + } } } -#endif } - - void halbtc8723d1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) { - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false; - static u8 cck_lock_counter = 0; - u32 total_cnt; +#if 1 + s32 wifi_rssi = 0; + boolean wifi_busy = false, wifi_under_b_mode = false, + wifi_scan = false; + boolean bt_idle = false, wl_idle = false; + static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, + wl_noisy_count1 = 3, wl_noisy_count2 = 0; + u32 total_cnt, reg_val1, reg_val2, cck_cnt; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_VHT); + + cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; + + if (cck_cnt > 250) { + if (wl_noisy_count2 < 3) + wl_noisy_count2++; + + if (wl_noisy_count2 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count1 = 0; + } + } else if (cck_cnt < 50) { + if (wl_noisy_count0 < 3) + wl_noisy_count0++; - if (coex_sta->under_ips) { - coex_sta->crc_ok_cck = 0; - coex_sta->crc_ok_11g = 0; - coex_sta->crc_ok_11n = 0; - coex_sta->crc_ok_11n_agg = 0; - - coex_sta->crc_err_cck = 0; - coex_sta->crc_err_11g = 0; - coex_sta->crc_err_11n = 0; - coex_sta->crc_err_11n_agg = 0; - } else { - coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf88); - coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf94); - coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf90); - coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfb8); - - coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf84); - coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf96); - coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf92); - coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfba); - } + if (wl_noisy_count0 == 3) { + wl_noisy_count1 = 0; + wl_noisy_count2 = 0; + } + } else { + if (wl_noisy_count1 < 3) + wl_noisy_count1++; + if (wl_noisy_count1 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count2 = 0; + } + } + + if (wl_noisy_count2 == 3) + coex_sta->wl_noisy_level = 2; + else if (wl_noisy_count1 == 3) + coex_sta->wl_noisy_level = 1; + else + coex_sta->wl_noisy_level = 0; + + if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { + total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht; + + if ((coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_SCO_BUSY)) { + if (coex_sta->crc_ok_cck > (total_cnt - + coex_sta->crc_ok_cck)) { + if (cck_lock_counter < 3) + cck_lock_counter++; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } - /* reset counter */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0); - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + - coex_sta->crc_ok_11n_agg; - - if ((coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == - BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == - BT_8723D_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; } else { if (cck_lock_counter > 0) cck_lock_counter--; } - } else { if (cck_lock_counter > 0) cck_lock_counter--; } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - if (cck_lock_counter >= 3) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } + if (!coex_sta->pre_ccklock) { - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = true; + if (cck_lock_counter >= 3) + coex_sta->cck_lock = true; + else + coex_sta->cck_lock = false; + } else { + if (cck_lock_counter == 0) + coex_sta->cck_lock = false; + else + coex_sta->cck_lock = true; + } - coex_sta->pre_ccklock = coex_sta->cck_lock; + if (coex_sta->cck_lock) + coex_sta->cck_ever_lock = true; + coex_sta->pre_ccklock = coex_sta->cck_lock; +#endif } -boolean halbtc8723d1ant_is_wifibt_status_changed(IN struct btc_coexist *btcoexist) +void halbtc8723d1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) { - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false, pre_bt_off = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + boolean bt_busy = false; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (coex_sta->bt_disabled != pre_bt_off) { - pre_bt_off = coex_sta->bt_disabled; + coex_sta->num_of_profile = 0; - if (coex_sta->bt_disabled) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); + /* set link exist status */ + if (!(coex_sta->bt_info & BT_INFO_8723D_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_FTP) { + coex_sta->pan_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->pan_exist = false; - BTC_TRACE(trace_buf); - return true; - } + if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_A2DP) { + coex_sta->a2dp_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->a2dp_exist = false; - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - } + if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_HID) { + coex_sta->hid_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->hid_exist = false; - return false; -} + if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) { + coex_sta->sco_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->sco_exist = false; -void halbtc8723d1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; + } btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); @@ -578,7 +636,6 @@ void halbtc8723d1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) bt_link_info->a2dp_exist = coex_sta->a2dp_exist; bt_link_info->pan_exist = coex_sta->pan_exist; bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->bt_hi_pri_link_exist = coex_sta->bt_hi_pri_link_exist; bt_link_info->acl_busy = coex_sta->acl_busy; /* work around for HS mode. */ @@ -622,8 +679,54 @@ void halbtc8723d1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) bt_link_info->hid_only = true; else bt_link_info->hid_only = false; + + if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_INQ_PAGE) { + coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_INQ_PAGE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); + } else if (!(coex_sta->bt_info & BT_INFO_8723D_1ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + } else if (coex_sta->bt_info == BT_INFO_8723D_1ANT_B_CONNECTION) { + /* connection exists but no busy */ + coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + } else if (((coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_BUSY)) && + (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_ACL_BUSY)) { + coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); + } else if ((coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + } else if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + } else { + coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + } + + BTC_TRACE(trace_buf); + + if ((BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + bt_busy = true; + else + bt_busy = false; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); } + void halbtc8723d1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, IN u8 type) { @@ -890,6 +993,7 @@ void halbtc8723d1ant_bt_auto_report(IN struct btc_coexist *btcoexist, void halbtc8723d1ant_set_fw_low_penalty_ra(IN struct btc_coexist *btcoexist, IN boolean low_penalty_ra) { +#if 1 u8 h2c_parameter[6] = {0}; h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ @@ -904,33 +1008,39 @@ void halbtc8723d1ant_set_fw_low_penalty_ra(IN struct btc_coexist } btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); +#endif } void halbtc8723d1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN boolean low_penalty_ra) { +#if 1 coex_dm->cur_low_penalty_ra = low_penalty_ra; if (!force_exec) { if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) return; } + halbtc8723d1ant_set_fw_low_penalty_ra(btcoexist, coex_dm->cur_low_penalty_ra); +#if 0 + if (low_penalty_ra) + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15); + else + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); +#endif coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} -void halbtc8723d1ant_sw_mechanism(IN struct btc_coexist *btcoexist, - IN boolean low_penalty_ra) -{ - halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); +#endif + } void halbtc8723d1ant_write_score_board( IN struct btc_coexist *btcoexist, IN u16 bitpos, - IN BOOLEAN state + IN boolean state ) { @@ -956,32 +1066,99 @@ void halbtc8723d1ant_read_score_board( 0xaa)) & 0x7fff; } -void halbtc8723d1ant_post_activestate_to_bt( +void halbtc8723d1ant_post_state_to_bt( IN struct btc_coexist *btcoexist, - IN boolean wifi_active + IN u16 type, + IN boolean state ) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8723d1ant_post_state_to_bt: type = %d, state =%d\n", + type, state); + BTC_TRACE(trace_buf); - if (wifi_active) - halbtc8723d1ant_write_score_board(btcoexist, (u16) BIT(0), TRUE); - else - halbtc8723d1ant_write_score_board(btcoexist, (u16) BIT(0), FALSE); - - /* The BT should set "No Shunt-down" mode if WL = Active for BT Synthesizer on/off interference WL Lo issue at 8703b b-cut. */ - + halbtc8723d1ant_write_score_board(btcoexist, (u16) type, state); } -void halbtc8723d1ant_post_onoffstate_to_bt( - IN struct btc_coexist *btcoexist, - IN boolean wifi_on -) +boolean halbtc8723d1ant_is_wifibt_status_changed(IN struct btc_coexist + *btcoexist) { + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false, pre_bt_off = false, pre_bt_slave = false; + static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - if (wifi_on) - halbtc8723d1ant_write_score_board(btcoexist, (u16) BIT(1), TRUE); - else - halbtc8723d1ant_write_score_board(btcoexist, (u16) BIT(1), FALSE); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (coex_sta->bt_disabled != pre_bt_off) { + pre_bt_off = coex_sta->bt_disabled; + + if (coex_sta->bt_disabled) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + return true; + } + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + + if (wifi_busy) + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_UNDERTEST, true); + else + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_UNDERTEST, false); + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { + pre_wl_noisy_level = coex_sta->wl_noisy_level; + return true; + } + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->hid_busy_num != pre_hid_busy_num) { + pre_hid_busy_num = coex_sta->hid_busy_num; + return true; + } + } + if (bt_link_info->slave_role != pre_bt_slave) { + pre_bt_slave = bt_link_info->slave_role; + return true; + } + + return false; } void halbtc8723d1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) @@ -1031,6 +1208,10 @@ void halbtc8723d1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) &bt_disabled); } + if (bt_disabled) + halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); + else + halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true); if (coex_sta->bt_disabled != bt_disabled) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -1043,10 +1224,12 @@ void halbtc8723d1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) } + + void halbtc8723d1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, boolean isenable) { - +#if BT_8723D_1ANT_COEX_DBG if (isenable) { btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); @@ -1079,7 +1262,7 @@ void halbtc8723d1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x1); } - +#endif } u32 halbtc8723d1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, @@ -1103,7 +1286,8 @@ u32 halbtc8723d1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, } -void halbtc8723d1ant_ltecoex_indirect_write_reg(IN struct btc_coexist *btcoexist, +void halbtc8723d1ant_ltecoex_indirect_write_reg(IN struct btc_coexist + *btcoexist, IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) { u32 val, i = 0, j = 0, bitpos = 0; @@ -1181,69 +1365,69 @@ void halbtc8723d1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, void halbtc8723d1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, IN u8 control_block, IN boolean sw_control, IN u8 state) { - u32 val = 0, bit_mask; + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; - state = state & 0x1; - val = (sw_control) ? ((state << 1) | 0x1) : 0; + val_orig = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); switch (control_block) { case BT_8723D_1ANT_GNT_BLOCK_RFC_BB: default: - bit_mask = 0xc000; - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[15:14] */ - bit_mask = 0x0c00; - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[11:10] */ + val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff); break; case BT_8723D_1ANT_GNT_BLOCK_RFC: - bit_mask = 0xc000; - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[15:14] */ + val = (val << 14) | (val_orig & 0xffff3fff); break; case BT_8723D_1ANT_GNT_BLOCK_BB: - bit_mask = 0x0c00; - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[11:10] */ + val = (val << 10) | (val_orig & 0xfffff3ff); break; - } + halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); } + void halbtc8723d1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, IN u8 control_block, IN boolean sw_control, IN u8 state) { - u32 val = 0, bit_mask; + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; - state = state & 0x1; - val = (sw_control) ? ((state << 1) | 0x1) : 0; + val_orig = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); switch (control_block) { case BT_8723D_1ANT_GNT_BLOCK_RFC_BB: default: - bit_mask = 0x3000; - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[13:12] */ - bit_mask = 0x0300; - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[9:8] */ + val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff); break; case BT_8723D_1ANT_GNT_BLOCK_RFC: - bit_mask = 0x3000; - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[13:12] */ + val = (val << 12) | (val_orig & 0xffffcfff); break; case BT_8723D_1ANT_GNT_BLOCK_BB: - bit_mask = 0x0300; - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[9:8] */ + val = (val << 8) | (val_orig & 0xfffffcff); break; - } + halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, + 0xffffffff, val); } + void halbtc8723d1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, IN u8 table_type, IN u16 table_content) { @@ -1290,25 +1474,60 @@ void halbtc8723d1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ - } -void halbtc8723d1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +void halbtc8723d1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 interval, + IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, + IN u8 val0x6c4_b3) { - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + static u8 pre_h2c_parameter[6] = {0}; + u8 cur_h2c_parameter[6] = {0}; + u8 i, match_cnt = 0; - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + cur_h2c_parameter[1] = interval; + cur_h2c_parameter[2] = val0x6c4_b0; + cur_h2c_parameter[3] = val0x6c4_b1; + cur_h2c_parameter[4] = val0x6c4_b2; + cur_h2c_parameter[5] = val0x6c4_b3; - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} + if (!force_exec) { + for (i = 1; i <= 5; i++) { + if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) + break; -void halbtc8723d1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ + match_cnt++; + } + + if (match_cnt == 5) + return; + } + + for (i = 1; i <= 5; i++) + pre_h2c_parameter[i] = cur_h2c_parameter[i]; + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); +} + + +void halbtc8723d1ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8723d1ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ coex_dm->cur_val0x6c0 = val0x6c0; coex_dm->cur_val0x6c4 = val0x6c4; coex_dm->cur_val0x6c8 = val0x6c8; @@ -1348,90 +1567,60 @@ void halbtc8723d1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, select_table = 0x3; } - switch (type) { - case 0: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, break_table, - select_table); - break; - case 1: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 2: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0xaa5a5a5a, 0xaa5a5a5a, break_table, - select_table); - break; - case 3: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0xaa555555, 0xaa5a5a5a, break_table, - select_table); - break; - case 4: - halbtc8723d1ant_coex_table(btcoexist, - force_exec, 0xaa555555, 0xaa5a5a5a, - break_table, select_table); - break; - case 5: - halbtc8723d1ant_coex_table(btcoexist, - force_exec, 0x5a5a5a5a, 0x5a5a5a5a, - break_table, select_table); - break; - case 6: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaaaaaa, break_table, - select_table); - break; - case 7: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, break_table, - select_table); - break; - case 8: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, break_table, - select_table); - break; - case 9: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, break_table, - select_table); - break; - case 10: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, break_table, - select_table); - break; - case 11: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, break_table, - select_table); - break; - case 12: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, break_table, - select_table); - break; - case 13: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0xaaaaaaaa, break_table, - select_table); - break; - case 14: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5ada5ada, break_table, - select_table); - break; - case 15: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0xaaaaaaaa, break_table, - select_table); - break; - default: - break; - } + switch (type) { + case 0: + halbtc8723d1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, break_table, + select_table); + break; + case 1: + halbtc8723d1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 2: + halbtc8723d1ant_coex_table(btcoexist, force_exec, + 0xaa5a5a5a, 0xaa5a5a5a, break_table, + select_table); + break; + case 3: + halbtc8723d1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 4: + halbtc8723d1ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 5: + halbtc8723d1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, break_table, + select_table); + break; + case 6: + halbtc8723d1ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 7: + halbtc8723d1ant_coex_table(btcoexist, force_exec, + 0xaaaaaaaa, 0xaaaaaaaa, break_table, + select_table); + break; + case 8: + halbtc8723d1ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xaaaaaaaa, break_table, + select_table); + break; + case 9: + halbtc8723d1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0xaaaa5aaa, break_table, + select_table); + break; + default: + break; + } } void halbtc8723d1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, @@ -1439,8 +1628,9 @@ void halbtc8723d1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, { u8 h2c_parameter[1] = {0}; - if (enable) + if (enable) { h2c_parameter[0] |= BIT(0); /* function enable */ + } btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); } @@ -1502,14 +1692,16 @@ void halbtc8723d1ant_ps_tdma_check_for_power_save_state( /* will leave LPS state, turn off psTdma first */ /*halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); } } else { /* NO PS state */ if (new_ps_state) { /* will enter LPS state, turn off psTdma first */ /*halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);*/ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); } else { /* keep state under NO PS state, do nothing. */ } @@ -1569,6 +1761,18 @@ void halbtc8723d1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, u8 h2c_parameter[5] = {0}; u8 real_byte1 = byte1, real_byte5 = byte5; boolean ap_enable = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if (byte5 & BIT(2)) + coex_sta->is_tdma_btautoslot = true; + else + coex_sta->is_tdma_btautoslot = false; + + /* release bt-auto slot for auto-slot hang is detected!! */ + if (coex_sta->is_tdma_btautoslot) + if ((coex_sta->is_tdma_btautoslot_hang) || + (bt_link_info->slave_role)) + byte5 = byte5 & 0xfb; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable); @@ -1576,7 +1780,7 @@ void halbtc8723d1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, if (ap_enable) { if (byte1 & BIT(4) && !(byte1 & BIT(5))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); + "[BTCoex], FW for AP mode\n"); BTC_TRACE(trace_buf); real_byte1 &= ~BIT(4); real_byte1 |= BIT(5); @@ -1584,7 +1788,8 @@ void halbtc8723d1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, real_byte5 |= BIT(5); real_byte5 &= ~BIT(6); - halbtc8723d1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + halbtc8723d1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); } } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { @@ -1593,7 +1798,8 @@ void halbtc8723d1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, btcoexist, BTC_PS_LPS_ON, 0x50, 0x4); } else { - halbtc8723d1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + halbtc8723d1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); } @@ -1620,20 +1826,20 @@ void halbtc8723d1ant_ps_tdma(IN struct btc_coexist *btcoexist, struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; struct btc_board_info *board_info = &btcoexist->board_info; boolean wifi_busy = false; - u8 rssi_adjust_val = 0; static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; static boolean pre_wifi_busy = false; #if BT_8723D_1ANT_ANTDET_ENABLE -#if BT_8723D_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE + if (board_info->btdm_ant_num_by_ant_det == 2) { +#if 0 if (turn_on) type = type + - 100; /* for WiFi RSSI low or BT RSSI low */ + 100; +#endif } -#endif #endif coex_dm->cur_ps_tdma_on = turn_on; @@ -1669,6 +1875,9 @@ void halbtc8723d1ant_ps_tdma(IN struct btc_coexist *btcoexist, "[BTCoex], ********** TDMA(on, %d) **********\n", coex_dm->cur_ps_tdma); BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** TDMA(off, %d) **********\n", @@ -1677,151 +1886,204 @@ void halbtc8723d1ant_ps_tdma(IN struct btc_coexist *btcoexist, } - if (turn_on) { - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - } - - if (turn_on) { switch (type) { default: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x11); + 0x61, 0x35, 0x03, 0x11, 0x11); break; - case 3: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x3a, 0x03, 0x10, 0x10); + 0x51, 0x3a, 0x03, 0x10, 0x50); break; case 4: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x21, 0x03, 0x10, 0x10); + 0x51, 0x21, 0x03, 0x10, 0x50); break; case 5: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x03, 0x11, 0x11); + 0x61, 0x15, 0x03, 0x11, 0x11); break; case 6: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x20, 0x03, 0x11, 0x11); + 0x61, 0x20, 0x03, 0x11, 0x11); break; case 7: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify); + 0x51, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); break; case 8: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify); + 0x51, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 9: + halbtc8723d1ant_set_fw_pstdma(btcoexist, + 0x55, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 10: + halbtc8723d1ant_set_fw_pstdma(btcoexist, + 0x61, 0x30, 0x03, 0x11, 0x10); + break; + case 11: + halbtc8723d1ant_set_fw_pstdma(btcoexist, + 0x65, 0x25, 0x03, 0x11, 0x11 | + psTdmaByte4Modify); + break; + case 12: + halbtc8723d1ant_set_fw_pstdma(btcoexist, + 0x55, 0x30, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); break; case 13: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x25, 0x03, 0x10, 0x10 | psTdmaByte4Modify); + 0x51, 0x25, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); break; case 14: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x15, 0x03, 0x10, 0x10 | psTdmaByte4Modify); + 0x51, 0x15, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); break; case 15: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x20, 0x03, 0x10, 0x10 | psTdmaByte4Modify); + 0x51, 0x20, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 16: + halbtc8723d1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x15 | + psTdmaByte4Modify); break; case 17: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x14 | psTdmaByte4Modify); + 0x61, 0x10, 0x03, 0x11, 0x14); + break; + case 18: + halbtc8723d1ant_set_fw_pstdma(btcoexist, + 0x51, 0x30, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); break; case 19: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x03, 0x11, 0x10); + 0x61, 0x15, 0x03, 0x11, 0x10); break; case 20: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); + 0x61, 0x30, 0x03, 0x11, 0x10); break; case 21: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); + 0x61, 0x30, 0x03, 0x11, 0x10); break; case 22: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x25, 0x03, 0x11, 0x10); + 0x61, 0x25, 0x03, 0x11, 0x10); + break; + case 23: + halbtc8723d1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x10); + break; + case 27: + halbtc8723d1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x15); break; case 32: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x11); + 0x61, 0x35, 0x03, 0x11, 0x11); break; case 33: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x10); + 0x61, 0x35, 0x03, 0x11, 0x10); + break; + case 57: + halbtc8723d1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 58: + halbtc8723d1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 67: + halbtc8723d1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x10 | + psTdmaByte4Modify); break; - /* 1-Ant to 2-Ant TDMA case */ case 103: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x3a, 0x03, 0x70, 0x10); + 0xd3, 0x3a, 0x03, 0x70, 0x10); break; case 104: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x21, 0x03, 0x70, 0x10); + 0xd3, 0x21, 0x03, 0x70, 0x10); break; case 105: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x15, 0x03, 0x71, 0x11); + 0xe3, 0x15, 0x03, 0x71, 0x11); break; case 106: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x20, 0x03, 0x71, 0x11); + 0xe3, 0x20, 0x03, 0x71, 0x11); break; case 107: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x10, 0x03, 0x70, 0x14 | psTdmaByte4Modify); + 0xd3, 0x10, 0x03, 0x70, 0x14 | + psTdmaByte4Modify); break; case 108: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x10, 0x03, 0x70, 0x14 | psTdmaByte4Modify); + 0xd3, 0x10, 0x03, 0x70, 0x14 | + psTdmaByte4Modify); break; case 113: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x25, 0x03, 0x70, 0x10 | psTdmaByte4Modify); + 0xd3, 0x25, 0x03, 0x70, 0x10 | + psTdmaByte4Modify); break; case 114: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x15, 0x03, 0x70, 0x10 | psTdmaByte4Modify); + 0xd3, 0x15, 0x03, 0x70, 0x10 | + psTdmaByte4Modify); break; case 115: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x20, 0x03, 0x70, 0x10 | psTdmaByte4Modify); + 0xd3, 0x20, 0x03, 0x70, 0x10 | + psTdmaByte4Modify); break; case 117: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x10, 0x03, 0x71, 0x14 | psTdmaByte4Modify); + 0xe3, 0x10, 0x03, 0x71, 0x14 | + psTdmaByte4Modify); break; case 119: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x15, 0x03, 0x71, 0x10); + 0xe3, 0x15, 0x03, 0x71, 0x10); break; case 120: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x30, 0x03, 0x71, 0x10); + 0xe3, 0x30, 0x03, 0x71, 0x10); break; case 121: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x30, 0x03, 0x71, 0x10); + 0xe3, 0x30, 0x03, 0x71, 0x10); break; case 122: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x25, 0x03, 0x71, 0x10); + 0xe3, 0x25, 0x03, 0x71, 0x10); break; case 132: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x35, 0x03, 0x71, 0x11); + 0xe3, 0x35, 0x03, 0x71, 0x11); break; case 133: halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x35, 0x03, 0x71, 0x10); + 0xe3, 0x35, 0x03, 0x71, 0x10); break; - } } else { @@ -1850,18 +2112,18 @@ void halbtc8723d1ant_ps_tdma(IN struct btc_coexist *btcoexist, void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg, - IN boolean wifi_off) + IN u8 ant_pos_type, IN boolean force_exec, + IN u8 phase) { struct btc_board_info *board_info = &btcoexist->board_info; u32 cnt_bt_cal_chk = 0; - boolean is_in_mp_mode = false; - u8 u8tmp = 0; + boolean is_in_mp_mode = false, is_hw_ant_div_on = false; + u8 u8tmp0 = 0, u8tmp1 = 0; u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - u16 u16tmp1 = 0; + u16 u16tmp0, u16tmp1 = 0; #if BT_8723D_1ANT_ANTDET_ENABLE -#if BT_8723D_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE + if (ant_pos_type == BTC_ANT_PATH_PTA) { if ((board_info->btdm_ant_det_finish) && (board_info->btdm_ant_num_by_ant_det == 2)) { @@ -1872,27 +2134,78 @@ void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist, ant_pos_type = BTC_ANT_PATH_BT; } } -#endif -#endif - coex_dm->cur_ant_pos_type = ant_pos_type; +#endif -#if 1 u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0x54); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + 0x38); + + /* To avoid indirect access fail */ + if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { + force_exec = true; + coex_sta->gnt_error_cnt++; + } +#if BT_8723D_1ANT_COEX_DBG + u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa); u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948); + u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x73); + u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before Set Ant Pat)\n", + u8tmp0, u16tmp1, u8tmp1); + BTC_TRACE(trace_buf); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Before Ant Setup) 0x948 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u16tmp1, u8tmp, u32tmp1, u32tmp2); + "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa = 0x%x(Before Set Ant Path)\n", + u32tmp1, u32tmp2, u16tmp0); BTC_TRACE(trace_buf); #endif - if (init_hwcfg) { + coex_dm->cur_ant_pos_type = ant_pos_type; + + if (!force_exec) { + if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Skip Antenna Path Setup because no change!!**********\n"); + BTC_TRACE(trace_buf); + return; + } + } + + coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; + + + switch (phase) { + case BT_8723D_1ANT_PHASE_COEX_POWERON: + /* Set Path control to WL */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, + 0x80, 0x0); + + /* set Path control owner to WL at initial step */ + halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8723D_1ANT_PCO_BTSIDE); + + /* set GNT_BT to SW high */ + halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8723D_1ANT_GNT_BLOCK_RFC_BB, + BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW low */ + halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8723D_1ANT_GNT_BLOCK_RFC_BB, + BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = false; + + break; + case BT_8723D_1ANT_PHASE_COEX_INIT: /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0); @@ -1906,18 +2219,20 @@ void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist, /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ while (cnt_bt_cal_chk <= 20) { - u8tmp = btcoexist->btc_read_1byte(btcoexist, - 0x49d); + u8tmp0 = btcoexist->btc_read_1byte(btcoexist, + 0x49d); cnt_bt_cal_chk++; - if (u8tmp & BIT(0)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + if (u8tmp0 & BIT(0)) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", cnt_bt_cal_chk); BTC_TRACE(trace_buf); delay_ms(50); } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL is NOT calibrating (wait cnt=%d)**********\n", cnt_bt_cal_chk); BTC_TRACE(trace_buf); break; @@ -1925,7 +2240,8 @@ void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist, } /* Set Path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, + 0x80, 0x1); /* set Path control owner to WL at initial step */ halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, @@ -1938,25 +2254,99 @@ void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist, BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); /* Set GNT_WL to SW low */ halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8723D_1ANT_GNT_BLOCK_RFC_BB, + BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = false; + break; + case BT_8723D_1ANT_PHASE_WLANONLY_INIT: + /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ + halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8723d1ant_ltecoex_set_coex_table(btcoexist, + BT_8723D_1ANT_CTT_WL_VS_LTE, 0xffff); + + /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8723d1ant_ltecoex_set_coex_table(btcoexist, + BT_8723D_1ANT_CTT_BT_VS_LTE, 0xffff); + + /* Set Path control to WL */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, + 0x80, 0x1); + + /* set Path control owner to WL at initial step */ + halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8723D_1ANT_PCO_WLSIDE); + + /* set GNT_BT to SW low */ + halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist, BT_8723D_1ANT_GNT_BLOCK_RFC_BB, BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, BT_8723D_1ANT_SIG_STA_SET_TO_LOW); + /* Set GNT_WL to SW high */ + halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8723D_1ANT_GNT_BLOCK_RFC_BB, + BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); - coex_sta->gnt_control_by_PTA = false; + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_WIFI; - } else if (wifi_off) { + coex_sta->run_time_state = false; + break; + case BT_8723D_1ANT_PHASE_WLAN_OFF: /* Disable LTE Coex Function in WiFi side */ halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0); /* Set Path control to BT */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, + 0x80, 0x0); /* set Path control owner to BT */ halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, BT_8723D_1ANT_PCO_BTSIDE); - coex_sta->gnt_control_by_PTA = false; - } else { + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = false; + break; + case BT_8723D_1ANT_PHASE_2G_RUNTIME: + + /* wait for WL/BT IQK finish, keep 0x38 = 0xff00 for WL IQK */ + while (cnt_bt_cal_chk <= 20) { + u8tmp0 = btcoexist->btc_read_1byte(btcoexist, + 0x1e6); + + u8tmp1 = btcoexist->btc_read_1byte(btcoexist, + 0x49d); + + cnt_bt_cal_chk++; + if ((u8tmp0 & BIT(0)) || (u8tmp1 & BIT(0))) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### WL or BT is IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + break; + } + } + + + /* Set Path control to WL */ + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1); */ halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, BT_8723D_1ANT_PCO_WLSIDE); @@ -1972,108 +2362,134 @@ void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist, BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA, BT_8723D_1ANT_SIG_STA_SET_BY_HW); - coex_sta->gnt_control_by_PTA = true; - } + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_PTA; - if (force_exec || - (coex_dm->cur_ant_pos_type != - coex_dm->pre_ant_pos_type)) { - /* internal switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - u16tmp1 = btcoexist->btc_read_2byte( - btcoexist, 0x948); - if ((u16tmp1 == 0x140) || - (u16tmp1 == 0x40)) - btcoexist->btc_write_2byte( - btcoexist, 0x948, - u16tmp1); - else - btcoexist->btc_write_2byte( - btcoexist, 0x948, 0x0); - } else { - u16tmp1 = btcoexist->btc_read_2byte( - btcoexist, 0x948); - if ((u16tmp1 == 0x140) || - (u16tmp1 == 0x40)) - btcoexist->btc_write_2byte( - btcoexist, 0x948, - u16tmp1); - else - btcoexist->btc_write_2byte( - btcoexist, 0x948, - 0x280); - } - break; - case BTC_ANT_PATH_BT: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - u16tmp1 = btcoexist->btc_read_2byte( - btcoexist, 0x948); - if ((u16tmp1 == 0x140) || - (u16tmp1 == 0x40)) - btcoexist->btc_write_2byte( - btcoexist, 0x948, - u16tmp1); - else - btcoexist->btc_write_2byte( - btcoexist, 0x948, - 0x280); - } else { - u16tmp1 = btcoexist->btc_read_2byte( - btcoexist, 0x948); - if ((u16tmp1 == 0x140) || - (u16tmp1 == 0x40)) - btcoexist->btc_write_2byte( - btcoexist, 0x948, - u16tmp1); - else - btcoexist->btc_write_2byte( - btcoexist, 0x948, 0x0); - } - break; - default: - case BTC_ANT_PATH_PTA: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_2byte( - btcoexist, 0x948, - 0x200); - else - btcoexist->btc_write_2byte( - btcoexist, 0x948, 0x80); - break; - } - } + coex_sta->run_time_state = true; + break; + case BT_8723D_1ANT_PHASE_BTMPMODE: + halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8723D_1ANT_PCO_WLSIDE); + /* Set Path control to WL */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, + 0x80, 0x1); -#if 1 + /* set GNT_BT to high */ + halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8723D_1ANT_GNT_BLOCK_RFC_BB, + BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to low */ + halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8723D_1ANT_GNT_BLOCK_RFC_BB, + BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_1ANT_SIG_STA_SET_TO_LOW); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = false; + break; + case BT_8723D_1ANT_PHASE_ANTENNA_DET: + halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8723D_1ANT_PCO_WLSIDE); + + /* Set Path control to WL */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, + 0x80, 0x1); + + /* set GNT_BT to high */ + halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8723D_1ANT_GNT_BLOCK_RFC_BB, + BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to high */ + halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8723D_1ANT_GNT_BLOCK_RFC_BB, + BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = false; + + break; + } + + + is_hw_ant_div_on = board_info->ant_div_cfg; + + if ((is_hw_ant_div_on) && (phase != BT_8723D_1ANT_PHASE_ANTENNA_DET)) + + if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) + /* 0x948 = 0x200, 0x0 while antenna diversity */ + btcoexist->btc_write_2byte(btcoexist, 0x948, 0x100); + else /* 0x948 = 0x80, 0x0 while antenna diversity */ + btcoexist->btc_write_2byte(btcoexist, 0x948, 0x40); + + else if ((is_hw_ant_div_on == false) && + (phase != BT_8723D_1ANT_PHASE_WLAN_OFF)) { /* internal switch setting */ + + switch (ant_pos_type) { + + case BTC_ANT_PATH_WIFI: + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + + btcoexist->btc_write_2byte( + btcoexist, 0x948, 0x0); + else + btcoexist->btc_write_2byte( + btcoexist, 0x948, 0x280); + + break; + case BTC_ANT_PATH_BT: + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + + btcoexist->btc_write_2byte( + btcoexist, 0x948, 0x280); + else + btcoexist->btc_write_2byte( + btcoexist, 0x948, 0x0); + + break; + default: + case BTC_ANT_PATH_PTA: + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + btcoexist->btc_write_2byte( + btcoexist, 0x948, + 0x200); + else + btcoexist->btc_write_2byte( + btcoexist, 0x948, 0x80); + break; + } + } + + +#if BT_8723D_1ANT_COEX_DBG u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa); u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x73); + u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); - if (init_hwcfg) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ant-Setup Init) 0x948 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u16tmp1, u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - } else if (wifi_off) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ant-Setup WiFi off) 0x948 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u16tmp1, u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ant-Setup Run time) 0x948 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u16tmp1, u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(After Set Ant Pat)\n", + u8tmp0, u16tmp1, u8tmp1); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa = 0x%x(After Set Ant Path)\n", + u32tmp1, u32tmp2, u16tmp0); + BTC_TRACE(trace_buf); #endif - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; } @@ -2091,9 +2507,6 @@ boolean halbtc8723d1ant_is_common_action(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); BTC_TRACE(trace_buf); - - /* halbtc8723d1ant_sw_mechanism(btcoexist, false); */ - common = true; } else if (wifi_connected && (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == @@ -2101,36 +2514,27 @@ boolean halbtc8723d1ant_is_common_action(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi connected + BT non connected-idle!!\n"); BTC_TRACE(trace_buf); - - /* halbtc8723d1ant_sw_mechanism(btcoexist, false); */ - common = true; } else if (!wifi_connected && - (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { + (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); BTC_TRACE(trace_buf); - - /* halbtc8723d1ant_sw_mechanism(btcoexist, false); */ - common = true; } else if (wifi_connected && - (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { + (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi connected + BT connected-idle!!\n"); BTC_TRACE(trace_buf); - - /* halbtc8723d1ant_sw_mechanism(btcoexist, false); */ - common = true; } else if (!wifi_connected && - (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) { + (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE != + coex_dm->bt_status)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); BTC_TRACE(trace_buf); - - /* halbtc8723d1ant_sw_mechanism(btcoexist, false); */ - common = true; } else { if (wifi_busy) { @@ -2152,615 +2556,441 @@ boolean halbtc8723d1ant_is_common_action(IN struct btc_coexist *btcoexist) /* ********************************************* * - * Software Coex Mechanism start + * Non-Software Coex Mechanism start * * ********************************************* */ - -/* SCO only or SCO+PAN(HS) */ - -/* -void halbtc8723d1ant_action_sco(IN struct btc_coexist* btcoexist) -{ - halbtc8723d1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8723d1ant_action_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8723d1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8723d1ant_action_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8723d1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8723d1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8723d1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8723d1ant_action_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8723d1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8723d1ant_action_pan_hs(IN struct btc_coexist* btcoexist) +void halbtc8723d1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) { - halbtc8723d1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8723d1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8723d1ant_sw_mechanism(btcoexist, false); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); } -void halbtc8723d1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist) +void halbtc8723d1ant_action_bt_hs(IN struct btc_coexist *btcoexist) { - halbtc8723d1ant_sw_mechanism(btcoexist, true); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); } - -void halbtc8723d1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist) +void halbtc8723d1ant_action_bt_relink(IN struct btc_coexist *btcoexist) { - halbtc8723d1ant_sw_mechanism(btcoexist, true); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + coex_sta->bt_relink_downcount = 2; } -void halbtc8723d1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist) +void halbtc8723d1ant_action_bt_idle(IN struct btc_coexist *btcoexist) { - halbtc8723d1ant_sw_mechanism(btcoexist, true); -} - -*/ + boolean wifi_busy = false; -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8723d1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) -{ - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); -void halbtc8723d1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, - false, false); - halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); -} + if (!wifi_busy) { + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + } else { + /* if wl busy */ + if (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); -void halbtc8723d1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); + } else { + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + } } -void halbtc8723d1ant_action_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); } void halbtc8723d1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, ap_enable = false, wifi_busy = false, - bt_busy = false; - boolean wifi_scan = false, wifi_link = false, wifi_roam = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, wifi_busy = false, bt_busy = false; + boolean wifi_scan = false, wifi_link = false, wifi_roam = false; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); - if ((wifi_link) || (wifi_roam) || (coex_sta->wifi_is_high_pri_task)) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); + if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) + || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { - } else if ((wifi_scan) && (coex_sta->bt_create_connection)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - } else if ((!wifi_connected) && (!wifi_scan)) { + if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17); + else + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); + } else if ((!wifi_connected) && (!wifi_scan)) { halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) { + } else if (bt_link_info->pan_exist) { halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (wifi_scan) { - - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if (bt_link_info->a2dp_exist) { - } else if (wifi_busy) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); } else { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 19); + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) + || (coex_sta->wifi_is_high_pri_task)) + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); + else + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); } } + void halbtc8723d1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) + *btcoexist) { struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false; + boolean wifi_connected = false, wifi_busy = false; + u32 wifi_bw = 1; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); - /* tdma and coex table */ - - if (bt_link_info->sco_exist) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else { /* HID */ - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } -} - -void halbtc8723d1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - if (bt_link_info->hid_only) { /* HID */ - halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist, - wifi_status); - coex_dm->auto_tdma_adjust = false; - return; - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); + + if (bt_link_info->sco_exist) { + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 5); halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; + NORMAL_EXEC, 5); + } else if (coex_sta->hid_busy_num >= 2) { + /*for 4/18 hid */ + /* if 11bg mode */ + if (wifi_bw == 0) { + + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 11); } else { - if (coex_sta->scan_ap_num >= - BT_8723D_1ANT_WIFI_NOISY_THRESH) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 17); - } else { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 7); - } + if (wifi_busy) { - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = true; + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 11); + } else { + + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 6); + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + + } } - } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255)) - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 15); - else - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - } else - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = false; - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8); - coex_dm->auto_tdma_adjust = false; - - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && - bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - if (BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 4); - else - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = false; } else { - /* BT no-profile busy (0x9) */ - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } -} - -void halbtc8723d1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - /* tdma and coex table */ - halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8723d1ant_action_wifi_not_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if (num_of_wifi_link >= 2) { - halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8723d1ant_action_bt_inquiry(btcoexist); - } else - halbtc8723d1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8723d1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723d1ant_action_hs(btcoexist); - return; - } - - /* tdma and coex table */ - if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 6); halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8723D_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + NORMAL_EXEC, 3); } } -void halbtc8723d1ant_action_wifi_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if (num_of_wifi_link >= 2) { - halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8723d1ant_action_bt_inquiry(btcoexist); - } else - halbtc8723d1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8723d1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723d1ant_action_hs(btcoexist); - return; - } - - - /* tdma and coex table */ - if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8723D_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8723d1ant_action_wifi_not_connected_asso_auth( - IN struct btc_coexist *btcoexist) +void halbtc8723d1ant_action_wifi_only(IN struct btc_coexist *btcoexist) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if (num_of_wifi_link >= 2) { - halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8723d1ant_action_bt_inquiry(btcoexist); - } else - halbtc8723d1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8723d1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723d1ant_action_hs(btcoexist); - return; - } - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2); - } + halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); + halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); } -void halbtc8723d1ant_action_wifi_connected_specific_packet( - IN struct btc_coexist *btcoexist) +void halbtc8723d1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) { struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - boolean wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if (num_of_wifi_link >= 2) { - halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8723d1ant_action_bt_inquiry(btcoexist); - } else - halbtc8723d1ant_action_wifi_multi_port(btcoexist); - return; - } + if (!bt_link_info->pan_exist) + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + else + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8723d1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723d1ant_action_hs(btcoexist); - return; - } +void halbtc8723d1ant_action_wifi_linkscan_process(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + if (bt_link_info->pan_exist) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - /* no specific packet process for both WiFi and BT very busy */ - if ((wifi_busy) && ((bt_link_info->pan_exist) || - (coex_sta->num_of_profile >= 2))) - return; + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); } else if (bt_link_info->a2dp_exist) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 27); + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); } else { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); + + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); } } -void halbtc8723d1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +void halbtc8723d1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist + *btcoexist) { - boolean wifi_busy = false; - boolean scan = false, link = false, roam = false; - boolean under_4way = false, ap_enable = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = false, wifi_turbo = false; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); + "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (under_4way) { - halbtc8723d1ant_action_wifi_connected_specific_packet(btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); - BTC_TRACE(trace_buf); - return; - } +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif + + if ((coex_sta->bt_relink_downcount != 0) + && (!bt_link_info->pan_exist) && (wifi_busy)) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - if (scan) - halbtc8723d1ant_action_wifi_connected_scan(btcoexist); - else - halbtc8723d1ant_action_wifi_connected_specific_packet( - btcoexist); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);*/ + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - /* tdma and coex table */ - if (!wifi_busy) { - if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8723d1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else if ((BT_8723D_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8723d1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); + } else if (bt_link_info->a2dp_only) { /* A2DP */ + if (!wifi_busy) { + /*halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32);*/ + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 27); halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - } - } else { - if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8723d1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8723D_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else if ((BT_8723D_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8723D_1ANT_WIFI_STATUS_CONNECTED_BUSY); + NORMAL_EXEC, 4); } else { - /* halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); */ + + if (coex_sta->wl_noisy_level == 2) + halbtc8723d1ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 17); + else + halbtc8723d1ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + + if (wifi_turbo) + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else if (((bt_link_info->a2dp_exist) && + (bt_link_info->pan_exist)) || + (bt_link_info->hid_exist && bt_link_info->a2dp_exist && + bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ + + if ((bt_link_info->hid_exist) && (coex_sta->hid_busy_num >= 2)) { + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + if (wifi_bw == 0) /* 11bg mode */ + halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + else + halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8723d1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - /* halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); */ + 12); + } else if (wifi_busy) { + if (((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) || + (!coex_sta->is_A2DP_3M)) + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 15); + else if (wifi_turbo) + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 18); + else + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 13); + } else + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 14); + + if (bt_link_info->hid_exist) + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + else if (wifi_turbo) + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { /* HID+A2DP */ + + if ((wifi_busy) && (coex_sta->hid_busy_num >= 2)) { /*for 4/18 hid */ + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + if (wifi_bw == 0) /* 11bg mode */ + halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + else + halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 9); + } else { + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 8); + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + } + + } else if ((bt_link_info->pan_only) + || (bt_link_info->hid_exist && bt_link_info->pan_exist)) { + /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ + + if ((bt_link_info->hid_exist) && (bt_link_info->pan_exist) && + (coex_sta->hid_busy_num >= 2)) { + + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + if (wifi_bw == 0) /* 11bg mode */ + halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + else + halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 12); + } else { + if (!wifi_busy) + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 4); + else + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 3); + + if (bt_link_info->hid_exist) + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + else if (wifi_turbo) + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else + halbtc8723d1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); } + } else { + /* BT no-profile busy (0x9) */ + halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); } } +void halbtc8723d1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +{ + /* tdma and coex table */ + halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + + +void halbtc8723d1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect()===>\n"); + BTC_TRACE(trace_buf); + + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); + + if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + + if (bt_link_info->hid_only) /* HID only */ + halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist); + else + halbtc8723d1ant_action_wifi_connected_bt_acl_busy(btcoexist); + + } else if ((BT_8723D_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist); + } else + halbtc8723d1ant_action_bt_idle(btcoexist); +} + + void halbtc8723d1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) { u8 algorithm = 0; @@ -2776,67 +3006,56 @@ void halbtc8723d1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = SCO.\n"); BTC_TRACE(trace_buf); - /* halbtc8723d1ant_action_sco(btcoexist); */ break; case BT_8723D_1ANT_COEX_ALGO_HID: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = HID.\n"); BTC_TRACE(trace_buf); - /* halbtc8723d1ant_action_hid(btcoexist); */ break; case BT_8723D_1ANT_COEX_ALGO_A2DP: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = A2DP.\n"); BTC_TRACE(trace_buf); - /* halbtc8723d1ant_action_a2dp(btcoexist); */ break; case BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); BTC_TRACE(trace_buf); - /* halbtc8723d1ant_action_a2dp_pan_hs(btcoexist); */ break; case BT_8723D_1ANT_COEX_ALGO_PANEDR: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = PAN(EDR).\n"); BTC_TRACE(trace_buf); - /* halbtc8723d1ant_action_pan_edr(btcoexist); */ break; case BT_8723D_1ANT_COEX_ALGO_PANHS: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = HS mode.\n"); BTC_TRACE(trace_buf); - /* halbtc8723d1ant_action_pan_hs(btcoexist); */ break; case BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = PAN+A2DP.\n"); BTC_TRACE(trace_buf); - /* halbtc8723d1ant_action_pan_edr_a2dp(btcoexist); */ break; case BT_8723D_1ANT_COEX_ALGO_PANEDR_HID: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); BTC_TRACE(trace_buf); - /* halbtc8723d1ant_action_pan_edr_hid(btcoexist); */ break; case BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); BTC_TRACE(trace_buf); - /* halbtc8723d1ant_action_hid_a2dp_pan_edr(btcoexist); */ break; case BT_8723D_1ANT_COEX_ALGO_HID_A2DP: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = HID+A2DP.\n"); BTC_TRACE(trace_buf); - /* halbtc8723d1ant_action_hid_a2dp(btcoexist); */ break; default: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = coexist All Off!!\n"); BTC_TRACE(trace_buf); - /* halbtc8723d1ant_coex_all_off(btcoexist); */ break; } coex_dm->pre_algorithm = coex_dm->cur_algorithm; @@ -2846,18 +3065,25 @@ void halbtc8723d1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) void halbtc8723d1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - boolean miracast_plus_bt = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, bt_hs_on = false; + boolean increase_scan_dev_num = false; + boolean bt_ctrl_agg_buf_size = false; + boolean miracast_plus_bt = false, wifi_under_5g = false; u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0, wifi_bw; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0, wifi_bw; u8 iot_peer = BTC_IOT_PEER_UNKNOWN; + boolean scan = false, link = false, roam = false, under_4way = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); + "[BTCoex], RunCoexistMechanism()===>\n"); BTC_TRACE(trace_buf); if (btcoexist->manual_control) { @@ -2876,163 +3102,198 @@ void halbtc8723d1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) if (coex_sta->under_ips) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (!coex_sta->run_time_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], return for run_time_state = false !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->freeze_coexrun_by_btinfo) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); BTC_TRACE(trace_buf); return; } if (coex_sta->bt_whck_test) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); + "[BTCoex], BT is under WHCK TEST!!!\n"); BTC_TRACE(trace_buf); - halbtc8723d1ant_action_bt_whck_test(btcoexist); + halbtc8723d1ant_action_bt_whql_test(btcoexist); return; } if (coex_sta->bt_disabled) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!!\n"); + "[BTCoex], BT is disabled !!!\n"); halbtc8723d1ant_action_wifi_only(btcoexist); return; } + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8723d1ant_action_bt_inquiry(btcoexist); + return; + } + + if (coex_sta->is_setupLink) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is re-link !!!\n"); + halbtc8723d1ant_action_bt_relink(btcoexist); + return; + } + if ((BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + (BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) increase_scan_dev_num = true; btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, &increase_scan_dev_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); + num_of_wifi_link, wifi_link_status); BTC_TRACE(trace_buf); - if (bt_link_info->bt_link_exist) { - halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, - 0, 1); + if (bt_link_info->bt_link_exist) miracast_plus_bt = true; - } else { - halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + else miracast_plus_bt = false; - } + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &miracast_plus_bt); + halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); + false, 0x5); - if (coex_sta->c2h_bt_inquiry_page) { + if (scan || link || roam || under_4way) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); BTC_TRACE(trace_buf); - halbtc8723d1ant_action_bt_inquiry(btcoexist); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); + BTC_TRACE(trace_buf); + + halbtc8723d1ant_action_wifi_linkscan_process(btcoexist); } else halbtc8723d1ant_action_wifi_multi_port(btcoexist); - return; } else { - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); + + miracast_plus_bt = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); } btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); - if (BTC_IOT_PEER_CISCO != iot_peer) { - if (bt_link_info->sco_exist) /* if (bt_link_info->bt_hi_pri_link_exist) */ + if (BTC_IOT_PEER_CISCO == iot_peer) { + + if (BTC_WIFI_BW_HT40 == wifi_bw) halbtc8723d1ant_limited_rx(btcoexist, - NORMAL_EXEC, true, false, 0x5); + NORMAL_EXEC, false, true, 0x10); else halbtc8723d1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, false, 0x5); - } else { - if (bt_link_info->sco_exist) - halbtc8723d1ant_limited_rx(btcoexist, - NORMAL_EXEC, true, false, 0x5); - else { - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8723d1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x10); - else - halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8); - } - } + } else + halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x5); + } - halbtc8723d1ant_sw_mechanism(btcoexist, true); - halbtc8723d1ant_run_sw_coexist_mechanism( + halbtc8723d1ant_run_sw_coexist_mechanism( btcoexist); /* just print debug message */ - } else { - halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x5); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - halbtc8723d1ant_sw_mechanism(btcoexist, false); - halbtc8723d1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is hs\n"); + BTC_TRACE(trace_buf); + halbtc8723d1ant_action_bt_hs(btcoexist); + return; } - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { + if ((BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) || + (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); + "############# [BTCoex], BT Is idle\n"); BTC_TRACE(trace_buf); - halbtc8723d1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723d1ant_action_hs(btcoexist); + halbtc8723d1ant_action_bt_idle(btcoexist); return; } - - if (!wifi_connected) { - boolean scan = false, link = false, roam = false; + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is non connected-idle !!!\n"); + "[BTCoex], wifi is under linkscan process!!\n"); BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + halbtc8723d1ant_action_wifi_linkscan_process(btcoexist); + } else if (wifi_connected) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under connected!!\n"); + BTC_TRACE(trace_buf); - if (scan || link || roam) { - if (scan) - halbtc8723d1ant_action_wifi_not_connected_scan( - btcoexist); - else - halbtc8723d1ant_action_wifi_not_connected_asso_auth( - btcoexist); - } else - halbtc8723d1ant_action_wifi_not_connected(btcoexist); - } else /* wifi LPS/Busy */ halbtc8723d1ant_action_wifi_connected(btcoexist); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under not-connected!!\n"); + BTC_TRACE(trace_buf); + + halbtc8723d1ant_action_wifi_not_connected(btcoexist); + } } + void halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist) { /* force to reset coex mechanism */ + halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); - /* sw all off */ - halbtc8723d1ant_sw_mechanism(btcoexist, false); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); coex_sta->pop_event_cnt = 0; + coex_sta->cnt_RemoteNameReq = 0; + coex_sta->cnt_ReInit = 0; + coex_sta->cnt_setupLink = 0; + coex_sta->cnt_IgnWlanAct = 0; + coex_sta->cnt_Page = 0; + coex_sta->cnt_RoleSwitch = 0; + + halbtc8723d1ant_query_bt_info(btcoexist); } void halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist, @@ -3040,21 +3301,50 @@ void halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist, { u32 u32tmp1 = 0, u32tmp2 = 0; u16 u16tmp1 = 0; + u8 u8tmp0 = 0, u8tmp1 = 0; struct btc_board_info *board_info = &btcoexist->board_info; + u8 i = 0; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 1Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + +#if BT_8723D_1ANT_COEX_DBG + u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, + 0x54); u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948); - u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x73); + u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Before Init HW config) 0x948= 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u16tmp1, u32tmp1, u32tmp2); + "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before init_hw_config)\n", + u8tmp0, u16tmp1, u8tmp1); BTC_TRACE(trace_buf); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); + "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x (Before init_hw_config)\n", + u32tmp1, u32tmp2); BTC_TRACE(trace_buf); +#endif + + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + coex_sta->isolation_btween_wb = BT_8723D_1ANT_DEFAULT_ISOLATION; + coex_sta->gnt_error_cnt = 0; + coex_sta->bt_relink_downcount = 0; + + for (i = 0; i <= 9; i++) + coex_sta->bt_afh_map[i] = 0; /* 0xf0[15:12] --> Chip Cut information */ coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, @@ -3076,45 +3366,54 @@ void halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist, /* Enable PTA (tx/rx signal form WiFi side) */ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); - halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, FALSE); + halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, true); +#if 0 /* check if WL firmware download ok */ if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) - halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, true); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ONOFF, true); +#endif + /* PTA parameter */ halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + psd_scan->ant_det_is_ant_det_available = true; + /* Antenna config */ if (wifi_only) { coex_sta->concurrent_rx_mode_on = false; halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, true, false); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, false, false); + FORCE_EXEC, + BT_8723D_1ANT_PHASE_WLANONLY_INIT); + + btcoexist->stop_coex_dm = true; } else { + /*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); + coex_sta->concurrent_rx_mode_on = true; btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); /* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */ btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, true, false); + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_COEX_INIT); - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Single Antenna, Antenna at Main Port: S1**********\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Single Antenna, Antenna at Aux Port: S0**********\n"); - BTC_TRACE(trace_buf); - } + btcoexist->stop_coex_dm = false; } - /* PTA parameter */ - halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - psd_scan->ant_det_is_ant_det_available = TRUE; + if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Single Antenna, Antenna at Main Port: S1**********\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Single Antenna, Antenna at Aux Port: S0**********\n"); + BTC_TRACE(trace_buf); + } } @@ -3173,7 +3472,31 @@ void halbtc8723d1ant_psd_show_antenna_detect_result(IN struct btc_coexist "\r\n============[Antenna Detection info] ============\n"); CL_PRINTF(cli_buf); - if (psd_scan->ant_det_result == 1) + if (psd_scan->ant_det_result == 12) { /* Get Ant Det from BT */ + + if (board_info->btdm_ant_num_by_ant_det == 1) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (%d~%d)", + "Ant Det Result", "1-Antenna", + BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT, + BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION); + else { + + if (psd_scan->ant_det_psd_scan_peak_val > + (BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION) + * 100) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (>%d)", + "Ant Det Result", "2-Antenna (Bad-Isolation)", + BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (%d~%d)", + "Ant Det Result", "2-Antenna (Good-Isolation)", + BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION, + BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); + } + } else if (psd_scan->ant_det_result == 1) CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)", "Ant Det Result", "2-Antenna (Bad-Isolation)", BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); @@ -3245,10 +3568,20 @@ void halbtc8723d1ant_psd_show_antenna_detect_result(IN struct btc_coexist case 11: CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(BT is Disabled)"); + case 12: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(BT is available, result from BT"); break; } CL_PRINTF(cli_buf); + if (psd_scan->ant_det_result == 12) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB", + "PSD Scan Peak Value", + psd_scan->ant_det_psd_scan_peak_val / 100); + CL_PRINTF(cli_buf); + return; + } CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Ant Detect Total Count", psd_scan->ant_det_try_count); @@ -3322,6 +3655,9 @@ void halbtc8723d1ant_psd_showdata(IN struct btc_coexist *btcoexist) u32 delta_freq_per_point; u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2; + if (psd_scan->ant_det_result == 12) + return; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n\n============[PSD info] (%d)============\n", psd_scan->psd_gen_count); @@ -3376,44 +3712,61 @@ void halbtc8723d1ant_psd_showdata(IN struct btc_coexist *btcoexist) while (1) { do { - freq = ((psd_scan->real_cent_freq - 20) * 1000000 + m * + freq = ((psd_scan->real_cent_freq - 20) * + 1000000 + m * delta_freq_per_point); freq1 = freq / 1000000; freq2 = freq / 1000 - freq1 * 1000; if (i == 1) { if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.000", freq1); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Freq%6d.000", + freq1); else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.0%2d", freq1, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Freq%6d.0%2d", + freq1, freq2); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.%3d", freq1, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Freq%6d.%3d", + freq1, freq2); } else if ((i % 8 == 0) || (m == psd_scan->psd_stop_point)) { if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, "%6d.000\n", freq1); else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.0%2d\n", freq1, freq2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.0%2d\n", freq1, + freq2); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.%3d\n", freq1, freq2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.%3d\n", freq1, + freq2); } else { if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, "%6d.000", freq1); else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.0%2d", freq1, freq2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.0%2d", freq1, + freq2); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.%3d", freq1, freq2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.%3d", freq1, + freq2); } i++; @@ -3424,35 +3777,48 @@ void halbtc8723d1ant_psd_showdata(IN struct btc_coexist *btcoexist) do { - psd_rep1 = psd_scan->psd_report_max_hold[n] / 100; - psd_rep2 = psd_scan->psd_report_max_hold[n] - psd_rep1 * + psd_rep1 = psd_scan->psd_report_max_hold[n] / + 100; + psd_rep2 = psd_scan->psd_report_max_hold[n] - + psd_rep1 * 100; if (j == 1) { if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Val %7d.0%d", psd_rep1, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Val %7d.0%d", + psd_rep1, psd_rep2); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Val %7d.%d", psd_rep1, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Val %7d.%d", + psd_rep1, psd_rep2); } else if ((j % 8 == 0) || (n == psd_scan->psd_stop_point)) { if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, "%7d.0%d\n", psd_rep1, psd_rep2); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.%d\n", psd_rep1, psd_rep2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%7d.%d\n", psd_rep1, + psd_rep2); } else { if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.0%d", psd_rep1, psd_rep2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%7d.0%d", psd_rep1, + psd_rep2); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.%d", psd_rep1, psd_rep2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%7d.%d", psd_rep1, + psd_rep2); } j++; @@ -3475,55 +3841,44 @@ void halbtc8723d1ant_psd_showdata(IN struct btc_coexist *btcoexist) } + +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif void halbtc8723d1ant_psd_maxholddata(IN struct btc_coexist *btcoexist, IN u32 gen_count) { - u32 i = 0, i_max = 0, val_max = 0; + u32 i = 0; + u32 loop_i_max = 0, loop_val_max = 0; if (gen_count == 1) { memcpy(psd_scan->psd_report_max_hold, psd_scan->psd_report, BT_8723D_1ANT_ANTDET_PSD_POINTS * sizeof(u32)); + } - for (i = psd_scan->psd_start_point; - i <= psd_scan->psd_stop_point; i++) { - - } - - psd_scan->psd_max_value_point = 0; - psd_scan->psd_max_value = 0; - - } else { - for (i = psd_scan->psd_start_point; - i <= psd_scan->psd_stop_point; i++) { - if (psd_scan->psd_report[i] > - psd_scan->psd_report_max_hold[i]) - psd_scan->psd_report_max_hold[i] = - psd_scan->psd_report[i]; - - /* search Max Value */ - if (i == psd_scan->psd_start_point) { - i_max = i; - val_max = psd_scan->psd_report_max_hold[i]; - } else { - if (psd_scan->psd_report_max_hold[i] > - val_max) { - i_max = i; - val_max = psd_scan->psd_report_max_hold[i]; - } - } + for (i = psd_scan->psd_start_point; + i <= psd_scan->psd_stop_point; i++) { + /* update max-hold value at each freq point */ + if (psd_scan->psd_report[i] > psd_scan->psd_report_max_hold[i]) + psd_scan->psd_report_max_hold[i] = + psd_scan->psd_report[i]; + /* search the max value in this seep */ + if (psd_scan->psd_report[i] > loop_val_max) { + loop_val_max = psd_scan->psd_report[i]; + loop_i_max = i; } - - psd_scan->psd_max_value_point = i_max; - psd_scan->psd_max_value = val_max; - } - + if (gen_count <= BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT) + psd_scan->psd_loop_max_value[gen_count - 1] = loop_val_max; } +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif u32 halbtc8723d1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) { /* reg 0x808[9:0]: FFT data x */ @@ -3531,6 +3886,7 @@ u32 halbtc8723d1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) /* reg 0x8b4[15:0]: FFT data y report */ u32 val = 0, psd_report = 0; + int k = 0; val = btcoexist->btc_read_4byte(btcoexist, 0x808); @@ -3542,6 +3898,10 @@ u32 halbtc8723d1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) val |= 0x00400000; btcoexist->btc_write_4byte(btcoexist, 0x808, val); + while (1) { + if (k++ > BT_8723D_1ANT_ANTDET_SWEEPPOINT_DELAY) + break; + } val = btcoexist->btc_read_4byte(btcoexist, 0x8b4); @@ -3550,7 +3910,9 @@ u32 halbtc8723d1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) return psd_report; } - +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist, IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points, IN u32 avgnum, IN u32 loopcnt) @@ -3563,8 +3925,9 @@ boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist, u8 flag = 0; u32 tmp = 0, u32tmp1 = 0; u32 wifi_original_channel = 1; + u32 psd_sum = 0, avg_cnt = 0; + u32 i_max = 0, val_max = 0, val_max2 = 0; - psd_scan->is_psd_running = true; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n"); BTC_TRACE(trace_buf); @@ -3726,10 +4089,6 @@ boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist, halbtc8723d1ant_psd_getdata( btcoexist, i); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Point=%d, psd_raw_data = 0x%08x\n", - i, psd_report); - BTC_TRACE(trace_buf); if (psd_report == 0) tmp = 0; else @@ -3741,17 +4100,96 @@ boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist, n = i - psd_scan->psd_start_base; psd_scan->psd_report[n] = tmp; - - halbtc8723d1ant_psd_maxholddata( - btcoexist, j); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "Point=%d, psd_dB_data = %d\n", + i, psd_scan->psd_report[n]); + BTC_TRACE(trace_buf); i++; } + halbtc8723d1ant_psd_maxholddata(btcoexist, j); + psd_scan->psd_gen_count = j; + + /*Accumulate Max PSD value in this loop if the value > threshold */ + if (psd_scan->psd_loop_max_value[j - 1] >= + 4000) { + psd_sum = psd_sum + + psd_scan->psd_loop_max_value[j - + 1]; + avg_cnt++; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "Loop=%d, Max_dB_data = %d\n", + j, psd_scan->psd_loop_max_value[j + - 1]); + BTC_TRACE(trace_buf); + + } + + if (loopcnt == BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT) { + + /* search the Max Value between each-freq-point-max-hold value of all sweep*/ + for (i = 1; + i <= BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT; + i++) { + + if (i == 1) { + i_max = i; + val_max = psd_scan->psd_loop_max_value[i + - 1]; + val_max2 = + psd_scan->psd_loop_max_value[i + - 1]; + } else if ( + psd_scan->psd_loop_max_value[i - + 1] > val_max) { + val_max2 = val_max; + i_max = i; + val_max = psd_scan->psd_loop_max_value[i + - 1]; + } else if ( + psd_scan->psd_loop_max_value[i - + 1] > val_max2) + val_max2 = + psd_scan->psd_loop_max_value[i + - 1]; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "i = %d, val_hold= %d, val_max = %d, val_max2 = %d\n", + i, psd_scan->psd_loop_max_value[i + - 1], + val_max, val_max2); + + BTC_TRACE(trace_buf); + } + + psd_scan->psd_max_value_point = i_max; + psd_scan->psd_max_value = val_max; + psd_scan->psd_max_value2 = val_max2; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "val_max = %d, val_max2 = %d\n", + psd_scan->psd_max_value, + psd_scan->psd_max_value2); + BTC_TRACE(trace_buf); } + if (avg_cnt != 0) { + psd_scan->psd_avg_value = (psd_sum / avg_cnt); + if ((psd_sum % avg_cnt) >= (avg_cnt / 2)) + psd_scan->psd_avg_value++; + } else + psd_scan->psd_avg_value = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "AvgLoop=%d, Avg_dB_data = %d\n", + avg_cnt, psd_scan->psd_avg_value); + BTC_TRACE(trace_buf); + flag = 100; break; case 99: /* error */ @@ -3797,10 +4235,6 @@ boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist, } while (!outloop); - - - psd_scan->is_psd_running = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n"); BTC_TRACE(trace_buf); @@ -3808,27 +4242,36 @@ boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist, } - -void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 bt_tx_time, IN u32 bt_le_channel) +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif +boolean halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist + *btcoexist) { u32 i = 0; - u32 wlpsd_cent_freq = 2484, wlpsd_span = 2, wlpsd_sweep_count = 50; + u32 wlpsd_cent_freq = 2484, wlpsd_span = 2; s32 wlpsd_offset = -4; + u32 bt_tx_time, bt_le_channel; u8 bt_le_ch[13] = {3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 33}; u8 h2c_parameter[3] = {0}, u8tmpa, u8tmpb; u8 state = 0; - boolean outloop = false, bt_resp = false; + boolean outloop = false, bt_resp = false, ant_det_finish = false; u32 freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point, - u32tmp, u32tmp0, u32tmp1, u32tmp2; + u32tmp, u32tmp0, u32tmp1, u32tmp2 ; struct btc_board_info *board_info = &btcoexist->board_info; - board_info->btdm_ant_det_finish = false; memset(psd_scan->ant_det_peak_val, 0, 16 * sizeof(u8)); memset(psd_scan->ant_det_peak_freq, 0, 16 * sizeof(u8)); + psd_scan->ant_det_bt_tx_time = + BT_8723D_1ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */ + psd_scan->ant_det_bt_le_channel = BT_8723D_1ANT_ANTDET_BTTXCHANNEL; + + bt_tx_time = psd_scan->ant_det_bt_tx_time; + bt_le_channel = psd_scan->ant_det_bt_le_channel; + if (board_info->tfbga_package) /* for TFBGA */ psd_scan->ant_det_thres_offset = 5; else @@ -3860,7 +4303,7 @@ void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, break; } } - +#if 0 wlpsd_sweep_count = bt_tx_time * 238 / 100; /* bt_tx_time/0.42 */ wlpsd_sweep_count = wlpsd_sweep_count / 5; @@ -3868,7 +4311,7 @@ void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, if (wlpsd_sweep_count % 5 != 0) wlpsd_sweep_count = (wlpsd_sweep_count / 5 + 1) * 5; - +#endif BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n", bt_tx_time, bt_le_channel); @@ -3878,7 +4321,7 @@ void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, wlpsd_cent_freq, wlpsd_offset, wlpsd_span, - wlpsd_sweep_count); + BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT); BTC_TRACE(trace_buf); state = 1; @@ -3904,37 +4347,17 @@ void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n"); BTC_TRACE(trace_buf); - - /* Set Antenna path, switch WiFi to un-certain antenna port */ - halbtc8723d1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, FORCE_EXEC, false, - false); } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n"); BTC_TRACE(trace_buf); - - /* Set Antenna path, switch WiFi to un-certain antenna port */ - halbtc8723d1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_WIFI, FORCE_EXEC, false, - false); } - - - + /* Set Antenna path, switch WiFi to un-certain antenna port */ /* Set Antenna Path, both GNT_WL/GNT_BT = 1, and control by SW */ - /* set GNT_BT to SW high */ - halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW high */ - halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); - + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_ANTENNA_DET); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n"); @@ -3954,13 +4377,16 @@ void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); + u32tmp = btcoexist->btc_read_2byte(btcoexist, 0x948); u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70); - u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg( + btcoexist, 0x38); + u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg( + btcoexist, 0x54); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (Before Ant Det) **********\n", - u32tmp0, u32tmp1, u32tmp2); + "[BTCoex], ********** 0x948 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (Before Ant Det)\n", + u32tmp, u32tmp0, u32tmp1, u32tmp2); BTC_TRACE(trace_buf); state = 2; @@ -3970,7 +4396,7 @@ void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, wlpsd_cent_freq, wlpsd_offset, wlpsd_span, BT_8723D_1ANT_ANTDET_PSD_POINTS, BT_8723D_1ANT_ANTDET_PSD_AVGNUM, 3)) { - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; board_info->btdm_ant_num_by_ant_det = 1; psd_scan->ant_det_result = 8; state = 99; @@ -3980,23 +4406,25 @@ void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, psd_scan->ant_det_pre_psdscan_peak_val = psd_scan->psd_max_value; - if (psd_scan->psd_max_value > + if (psd_scan->ant_det_pre_psdscan_peak_val > (BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND + psd_scan->ant_det_thres_offset) * 100) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n", - psd_scan->psd_max_value / 100, + psd_scan->ant_det_pre_psdscan_peak_val / + 100, BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND + psd_scan->ant_det_thres_offset); BTC_TRACE(trace_buf); - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; board_info->btdm_ant_num_by_ant_det = 1; psd_scan->ant_det_result = 5; state = 99; } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n", - psd_scan->psd_max_value / 100, + psd_scan->ant_det_pre_psdscan_peak_val / + 100, BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND + psd_scan->ant_det_thres_offset); BTC_TRACE(trace_buf); @@ -4009,21 +4437,36 @@ void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, btcoexist, (u8)(bt_tx_time & 0xff), (u8)(bt_le_channel & 0xff)); + /* Sync WL Rx PSD with BT Tx time because H2C->Mailbox delay */ + delay_ms(20); + if (!halbtc8723d1ant_psd_sweep_point(btcoexist, wlpsd_cent_freq, wlpsd_offset, wlpsd_span, BT_8723D_1ANT_ANTDET_PSD_POINTS, BT_8723D_1ANT_ANTDET_PSD_AVGNUM, - wlpsd_sweep_count)) { - board_info->btdm_ant_det_finish = false; + BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT)) { + ant_det_finish = false; board_info->btdm_ant_num_by_ant_det = 1; psd_scan->ant_det_result = 8; state = 99; break; } +#if 1 psd_scan->ant_det_psd_scan_peak_val = psd_scan->psd_max_value; +#endif +#if 0 + psd_scan->ant_det_psd_scan_peak_val = + ((psd_scan->psd_max_value - psd_scan->psd_avg_value) < + 800) ? + psd_scan->psd_max_value : (( + psd_scan->psd_max_value - + psd_scan->psd_max_value2 <= 300) ? + psd_scan->psd_avg_value : + psd_scan->psd_max_value2); +#endif psd_scan->ant_det_psd_scan_peak_freq = psd_scan->psd_max_value_point; state = 4; @@ -4037,8 +4480,9 @@ void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, psd_scan->psd_band_width / psd_scan->psd_point; - psd_rep1 = psd_scan->psd_max_value / 100; - psd_rep2 = psd_scan->psd_max_value - psd_rep1 * + psd_rep1 = psd_scan->ant_det_psd_scan_peak_val / 100; + psd_rep2 = psd_scan->ant_det_psd_scan_peak_val - + psd_rep1 * 100; freq = ((psd_scan->real_cent_freq - 20) * @@ -4089,41 +4533,50 @@ void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, psd_scan->ant_det_is_btreply_available = false; psd_scan->ant_det_result = 0; - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; board_info->btdm_ant_num_by_ant_det = 1; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n "); BTC_TRACE(trace_buf); - } else if (psd_scan->psd_max_value > + } else if (psd_scan->ant_det_psd_scan_peak_val > (BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION) * 100) { psd_scan->ant_det_result = 1; - board_info->btdm_ant_det_finish = true; + ant_det_finish = true; board_info->btdm_ant_num_by_ant_det = 2; + coex_sta->isolation_btween_wb = (u8)(85 - + psd_scan->ant_det_psd_scan_peak_val / + 100) & 0xff; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n"); BTC_TRACE(trace_buf); - } else if (psd_scan->psd_max_value > + } else if (psd_scan->ant_det_psd_scan_peak_val > (BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION + psd_scan->ant_det_thres_offset) * 100) { psd_scan->ant_det_result = 2; - board_info->btdm_ant_det_finish = true; + ant_det_finish = true; board_info->btdm_ant_num_by_ant_det = 2; + coex_sta->isolation_btween_wb = (u8)(85 - + psd_scan->ant_det_psd_scan_peak_val / + 100) & 0xff; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n"); BTC_TRACE(trace_buf); - } else if (psd_scan->psd_max_value > + } else if (psd_scan->ant_det_psd_scan_peak_val > (BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT) * 100) { psd_scan->ant_det_result = 3; - board_info->btdm_ant_det_finish = true; + ant_det_finish = true; board_info->btdm_ant_num_by_ant_det = 1; + coex_sta->isolation_btween_wb = (u8)(85 - + psd_scan->ant_det_psd_scan_peak_val / + 100) & 0xff; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n"); BTC_TRACE(trace_buf); } else { psd_scan->ant_det_result = 4; - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; board_info->btdm_ant_num_by_ant_det = 1; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n"); @@ -4148,24 +4601,19 @@ void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, h2c_parameter); /* Set Antenna Path, GNT_WL/GNT_BT control by PTA */ + /* Set Antenna path, switch WiFi to certain antenna port */ halbtc8723d1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, FORCE_EXEC, false, - false); + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!"); BTC_TRACE(trace_buf); - /* Resume Coex DM */ btcoexist->stop_coex_dm = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); - BTC_TRACE(trace_buf); - /* stimulate coex running */ - halbtc8723d1ant_run_coexist_mechanism( - btcoexist); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); + "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); BTC_TRACE(trace_buf); outloop = true; @@ -4174,78 +4622,55 @@ void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, } while (!outloop); - + return ant_det_finish; } -void halbtc8723d1ant_psd_antenna_detection_check(IN struct btc_coexist +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif +boolean halbtc8723d1ant_psd_antenna_detection_check(IN struct btc_coexist *btcoexist) { static u32 ant_det_count = 0, ant_det_fail_count = 0; struct btc_board_info *board_info = &btcoexist->board_info; - boolean scan, roam; + boolean scan, roam, ant_det_finish = false; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - /* psd_scan->ant_det_bt_tx_time = 20; */ - psd_scan->ant_det_bt_tx_time = - BT_8723D_1ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */ - psd_scan->ant_det_bt_le_channel = BT_8723D_1ANT_ANTDET_BTTXCHANNEL; - ant_det_count++; psd_scan->ant_det_try_count = ant_det_count; if (scan || roam) { - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; psd_scan->ant_det_result = 6; } else if (coex_sta->bt_disabled) { - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; psd_scan->ant_det_result = 11; } else if (coex_sta->num_of_profile >= 1) { - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; psd_scan->ant_det_result = 7; } else if ( !psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */ - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; psd_scan->ant_det_result = 9; } else if (coex_sta->c2h_bt_inquiry_page) { - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; psd_scan->ant_det_result = 10; } else { - btcoexist->stop_coex_dm = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_psd_antenna_detection(btcoexist, - psd_scan->ant_det_bt_tx_time, - psd_scan->ant_det_bt_le_channel); + ant_det_finish = halbtc8723d1ant_psd_antenna_detection( + btcoexist); delay_ms(psd_scan->ant_det_bt_tx_time); - - btcoexist->stop_coex_dm = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); - BTC_TRACE(trace_buf); - - /* stimulate coex running */ - /* - halbtc8723d1ant_run_coexist_mechanism( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); - BTC_TRACE(trace_buf); - */ } - if (!board_info->btdm_ant_det_finish) + /* board_info->ant_det_result = psd_scan->ant_det_result; */ + + if (!ant_det_finish) ant_det_fail_count++; psd_scan->ant_det_fail_count = ant_det_fail_count; @@ -4254,12 +4679,15 @@ void halbtc8723d1ant_psd_antenna_detection_check(IN struct btc_coexist "xxxxxxxxxxxxxxxx AntennaDetect(), result = %d, fail_count = %d, finish = %s\n", psd_scan->ant_det_result, psd_scan->ant_det_fail_count, - board_info->btdm_ant_det_finish == TRUE ? "Yes" : "No"); + ant_det_finish == true ? "Yes" : "No"); BTC_TRACE(trace_buf); + return ant_det_finish; + } + /* ************************************************************ * work around function start with wa_halbtc8723d1ant_ * ************************************************************ @@ -4284,59 +4712,43 @@ void ex_halbtc8723d1ant_power_on_setting(IN struct btc_coexist *btcoexist) BTC_TRACE(trace_buf); btcoexist->stop_coex_dm = true; - psd_scan->ant_det_is_ant_det_available = FALSE; - /* halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, TRUE); */ + psd_scan->ant_det_is_ant_det_available = false; /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */ u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - /* set Path control owner to WiFi */ - halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_1ANT_PCO_WLSIDE); - - /* set GNT_BT to high */ - halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to low */ - halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_LOW); - /* Local setting bit define */ /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ /* BIT1: "0" for internal switch; "1" for external switch */ /* BIT2: "0" for one antenna; "1" for two antenna */ /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - /* Set path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1); - /* Set Antenna Path to BT side */ /* Check efuse 0xc3[6] for Single Antenna Path */ if (board_info->single_ant_path == 0) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Single Antenna, Antenna at Main Port: S1**********\n"); - BTC_TRACE(trace_buf); - /* set to S1 */ board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - btcoexist->btc_write_2byte(btcoexist, 0x948, 0x280); u8tmp = 0; + value = 1; } else if (board_info->single_ant_path == 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Single Antenna, Antenna at Aux Port: S0**********\n"); - BTC_TRACE(trace_buf); - /* set to S0 */ board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0); u8tmp = 1; + value = 0; } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d **********\n", + board_info->single_ant_path , board_info->btdm_ant_pos); + BTC_TRACE(trace_buf); + + /* Set Antenna Path to BT side */ + halbtc8723d1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_COEX_POWERON); + /* Write Single Antenna Position to Registry to tell BT for 8723d. This line can be removed since BT EFuse also add "single antenna position" in EFuse for 8723d*/ btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, @@ -4351,7 +4763,7 @@ void ex_halbtc8723d1ant_power_on_setting(IN struct btc_coexist *btcoexist) btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, FALSE); + halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, true); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n", @@ -4360,7 +4772,8 @@ void ex_halbtc8723d1ant_power_on_setting(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0x948 (Power-On) = 0x%x / 0x%x**********\n", - btcoexist->btc_read_4byte(btcoexist, 0x70), btcoexist->btc_read_2byte(btcoexist, 0x948)); + btcoexist->btc_read_4byte(btcoexist, 0x70), + btcoexist->btc_read_2byte(btcoexist, 0x948)); BTC_TRACE(trace_buf); } @@ -4373,19 +4786,11 @@ void ex_halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist, IN boolean wifi_only) { halbtc8723d1ant_init_hw_config(btcoexist, true, wifi_only); - btcoexist->stop_coex_dm = false; - } void ex_halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - halbtc8723d1ant_init_coex_dm(btcoexist); - - /* halbtc8723d1ant_query_bt_info(btcoexist); */ } void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist) @@ -4394,12 +4799,14 @@ void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist) struct btc_stack_info *stack_info = &btcoexist->stack_info; struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u8 u8tmp[4], i, ps_tdma_case = 0; u16 u16tmp[4]; u32 u32tmp[4]; - u32 fa_of_dm, fa_cck; - u32 fw_ver = 0, bt_patch_ver = 0; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; static u8 pop_report_in_10s = 0; + u32 phyver = 0; + boolean lte_coex_on = false; CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); @@ -4432,33 +4839,63 @@ void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist) CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s (%d/%d/%d)", "Ant PG Num/ Mech(Ant_Det)/ Pos", - board_info->pg_ant_num, board_info->btdm_ant_num_by_ant_det, + board_info->pg_ant_num, + board_info->btdm_ant_num_by_ant_det, (board_info->btdm_ant_pos == 1 ? "S1" : "S0"), - psd_scan->ant_det_try_count, psd_scan->ant_det_fail_count, + psd_scan->ant_det_try_count, + psd_scan->ant_det_fail_count, psd_scan->ant_det_result); CL_PRINTF(cli_buf); if (board_info->btdm_ant_det_finish) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); + + if (psd_scan->ant_det_result != 12) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", + "Ant Det PSD Value", + psd_scan->ant_det_peak_val); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d", + "Ant Det PSD Value", + psd_scan->ant_det_psd_scan_peak_val + / 100); CL_PRINTF(cli_buf); } } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", - "BT stack/ hci ext ver", - ((stack_info->profile_notified) ? "Yes" : "No"), - stack_info->hci_version); - CL_PRINTF(cli_buf); + if (board_info->ant_det_result_five_complete) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d", + "AntDet(Registry) Num/PSD Value", + board_info->btdm_ant_num_by_ant_det, + (board_info->antdetval & 0x7f)); + CL_PRINTF(cli_buf); + } - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + + bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c", - "Version Coex/ Fw/ Patch/ Cut", - glcoex_ver_date_8723d_1ant, glcoex_ver_8723d_1ant, fw_ver, - bt_patch_ver, bt_patch_ver, coex_sta->cut_version + 65); + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8723d_1ant, glcoex_ver_8723d_1ant, + glcoex_ver_btdesired_8723d_1ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8723d_1ant ? + "Match" : "Mis-Match")))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", @@ -4466,12 +4903,6 @@ void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], coex_dm->wifi_chnl_info[2]); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", - "WifibHiPri/ Ccklock/ CckEverLock", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), - (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No")); - CL_PRINTF(cli_buf); /* wifi status */ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", @@ -4484,7 +4915,8 @@ void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist) CL_PRINTF(cli_buf); pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", "BT [status/ rssi/ retryCnt/ popCnt]", ((coex_sta->bt_disabled) ? ("disabled") : (( coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") @@ -4501,32 +4933,112 @@ void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist) pop_report_in_10s = 0; } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d / %d / %d / %d / %d", - "SCO/HID/PAN/A2DP/Hi-Pri", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist, - bt_link_info->bt_hi_pri_link_exist); + if (coex_sta->num_of_profile != 0) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s%s%s%s%s", + "Profiles", + ((bt_link_info->a2dp_exist) ? "A2DP," : ""), + ((bt_link_info->sco_exist) ? "SCO," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : + "HID(2/18),") : ""), + ((bt_link_info->pan_exist) ? "PAN," : ""), + ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = None", + "Profiles"); + CL_PRINTF(cli_buf); - if (stack_info->profile_notified) - btcoexist->btc_disp_dbg_msg(btcoexist, - BTC_DBG_DISP_BT_LINK_INFO); - else { - bt_info_ext = coex_sta->bt_info_ext; + if (bt_link_info->a2dp_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", + "A2DP Rate/Bitpool/Auto_Slot", + ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), + coex_sta->a2dp_bit_pool, + ((coex_sta->is_autoslot) ? "On" : "Off") + ); + CL_PRINTF(cli_buf); + } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s / %d", - "Role/A2DP Rate/Bitpool", - ((bt_link_info->slave_role) ? "Slave" : "Master"), - (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool); + if (bt_link_info->hid_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "HID PairNum/Forbid_Slot", + coex_sta->hid_pair_cnt, + coex_sta->forbidden_slot + ); CL_PRINTF(cli_buf); } + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x", + "Role/RoleSwCnt/IgnWlact/Feature", + ((bt_link_info->slave_role) ? "Slave" : "Master"), + coex_sta->cnt_RoleSwitch, + ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), + coex_sta->bt_coex_supported_feature); + CL_PRINTF(cli_buf); + + if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "BLEScan Type/TV/Init/Ble", + coex_sta->bt_ble_scan_type, + (coex_sta->bt_ble_scan_type & 0x1 ? + coex_sta->bt_ble_scan_para[0] : 0x0), + (coex_sta->bt_ble_scan_type & 0x2 ? + coex_sta->bt_ble_scan_para[1] : 0x0), + (coex_sta->bt_ble_scan_type & 0x4 ? + coex_sta->bt_ble_scan_para[2] : 0x0)); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "ReInit/ReLink/IgnWlact/Page/NameReq", + coex_sta->cnt_ReInit, + coex_sta->cnt_setupLink, + coex_sta->cnt_IgnWlanAct, + coex_sta->cnt_Page, + coex_sta->cnt_RemoteNameReq + ); + CL_PRINTF(cli_buf); + + halbtc8723d1ant_read_score_board(btcoexist, &u16tmp[0]); + + if ((coex_sta->bt_reg_vendor_ae == 0xffff) || + (coex_sta->bt_reg_vendor_ac == 0xffff)) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", + ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), + coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); + CL_PRINTF(cli_buf); + + if (coex_sta->num_of_profile > 0) { + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + "AFH MAP", + coex_sta->bt_afh_map[0], + coex_sta->bt_afh_map[1], + coex_sta->bt_afh_map[2], + coex_sta->bt_afh_map[3], + coex_sta->bt_afh_map[4], + coex_sta->bt_afh_map[5], + coex_sta->bt_afh_map[6], + coex_sta->bt_afh_map[7], + coex_sta->bt_afh_map[8], + coex_sta->bt_afh_map[9] + ); + CL_PRINTF(cli_buf); + } for (i = 0; i < BT_INFO_SRC_8723D_1ANT_MAX; i++) { if (coex_sta->bt_info_c2h_cnt[i]) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)", glbt_info_src_8723d_1ant[i], coex_sta->bt_info_c2h[i][0], coex_sta->bt_info_c2h[i][1], @@ -4546,186 +5058,219 @@ void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist) "============[mechanisms] (before Manual)============"); else CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); + "============[Mechanisms]============"); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "SM[LowPenaltyRA]", - coex_dm->cur_low_penalty_ra); - CL_PRINTF(cli_buf); - ps_tdma_case = coex_dm->cur_ps_tdma; CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", - "PS TDMA", + "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s)", + "TDMA", coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "On" : "Off"), - (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); - - CL_PRINTF(cli_buf); + (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off")); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "WL/BT Coex Table Type", - coex_sta->coex_table_type); CL_PRINTF(cli_buf); u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2]); + "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", + "Table/0x6c0/0x6c4/0x6c8", + coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); CL_PRINTF(cli_buf); u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x778/0x6cc/IgnWlanAct", - u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act); + "\r\n %-35s = 0x%x/ 0x%x", + "0x778/0x6cc", + u8tmp[0], u32tmp[0]); CL_PRINTF(cli_buf); - u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa0); - u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "LTE Coex Table W_L/B_L", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", + "AntDiv/ ForceLPS", + ((board_info->ant_div_cfg) ? "On" : "Off"), + ((coex_sta->force_lps_on) ? "On" : "Off")); CL_PRINTF(cli_buf); - u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa8); - u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0xac); - u32tmp[2] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb0); - u32tmp[3] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb4); + u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? true : false; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "LTE Break Table W_L/B_L/L_W/L_B", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, - u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); - CL_PRINTF(cli_buf); + if (lte_coex_on) { + + u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa0); + u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "LTE Coex Table W_L/B_L", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa8); + u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, + 0xac); + u32tmp[2] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, + 0xb0); + u32tmp[3] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, + 0xb4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "LTE Break Table W_L/B_L/L_W/L_B", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, + u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); + CL_PRINTF(cli_buf); + + } /* Hw setting */ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); CL_PRINTF(cli_buf); + /* + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); + u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", + "0x430/0x434/0x42a/0x456", + u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + */ + u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", + "LTE Coex/Path Owner", + ((lte_coex_on) ? "On" : "Off") , + ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); CL_PRINTF(cli_buf); + if (lte_coex_on) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %d/ %d", + "LTE 3Wire/OPMode/UART/UARTMode", + (int)((u32tmp[0] & BIT(6)) >> 6), + (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), + (int)((u32tmp[0] & BIT(3)) >> 3), + (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); + CL_PRINTF(cli_buf); - u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "LTE_Busy/UART_Busy", + (int)((u32tmp[1] & BIT(1)) >> 1), (int)(u32tmp[1] & BIT(0))); + CL_PRINTF(cli_buf); + } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s", - "LTE CoexOn/Path Ctrl Owner", - (int)((u32tmp[0] & BIT(7)) >> 7), ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", + ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), + ((u8tmp[0] & BIT(3)) ? "On" : "Off"), + coex_sta->gnt_error_cnt); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "LTE 3Wire/OPMode/UART/UARTMode", - (int)((u32tmp[0] & BIT(6)) >> 6), (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), - (int)((u32tmp[0] & BIT(3)) >> 3), - (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "GNT_WL/GNT_BT", + (int)((u32tmp[1] & BIT(2)) >> 2), + (int)((u32tmp[1] & BIT(3)) >> 3)); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s", - "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg", - (int)((u32tmp[0] & BIT(12)) >> 12), (int)((u32tmp[0] & BIT(14)) >> 14), - ((u8tmp[0] & BIT(3)) ? "On" : "Off")); + u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x948); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x948/0x67[7]", + u16tmp[0], (int)((u8tmp[0] & BIT(7)) >> 7)); CL_PRINTF(cli_buf); - u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x964); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x864); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xab7); + u8tmp[3] = btcoexist->btc_read_1byte(btcoexist, 0xa01); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "GNT_WL/GNT_BT/LTE_Busy/UART_Busy", - (int)((u32tmp[0] & BIT(2)) >> 2), (int)((u32tmp[0] & BIT(3)) >> 3), - (int)((u32tmp[0] & BIT(1)) >> 1), (int)(u32tmp[0] & BIT(0))); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "0x964[1]/0x864[0]/0xab7[5]/0xa01[7]", + (int)((u8tmp[0] & BIT(1)) >> 1), (int)((u8tmp[1] & BIT(0))), + (int)((u8tmp[2] & BIT(3)) >> 3), + (int)((u8tmp[3] & BIT(7)) >> 7)); CL_PRINTF(cli_buf); - - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x948); u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x45e); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x948/0x4c6[4]/0x40[5] (W/B PTA_En)", - u16tmp[0], (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5)); + "0x4c6[4]/0x40[5]/0x45e[3](TxRetry)", + (int)((u8tmp[0] & BIT(4)) >> 4), + (int)((u8tmp[1] & BIT(5)) >> 5), + (int)((u8tmp[2] & BIT(3)) >> 3)); CL_PRINTF(cli_buf); u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x67); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ %s", - "0x550/0x522/0x67[7]/4-RxAGC", - u32tmp[0], u8tmp[0], ((u8tmp[2] & 0x80) >> 7), (u8tmp[1] & 0x2) ? "On" : "Off"); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s", + "0x550/0x522/4-RxAGC", + u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off"); CL_PRINTF(cli_buf); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8); - u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c); - - fa_of_dm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000) - >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) + - ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] & 0xffff); - fa_cck = (u8tmp[0] << 8) + u8tmp[1]; - - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xc50); + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0xc50/OFDM-CCA/OFDM-FA/CCK-FA", - u32tmp[1] & 0xff, u32tmp[0] & 0xffff, fa_of_dm, fa_cck); + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); CL_PRINTF(cli_buf); - +#if 1 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-Agg", + "CRC_OK CCK/11g/11n/11n-agg", coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg); + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-Agg", + "CRC_Err CCK/11g/11n/11n-agg", coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg); + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); CL_PRINTF(cli_buf); +#endif - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "WlHiPri/ Locking/ Locked/ Noisy", + (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + (coex_sta->cck_lock ? "Yes" : "No"), + (coex_sta->cck_ever_lock ? "Yes" : "No"), + coex_sta->wl_noisy_level); CL_PRINTF(cli_buf); - halbtc8723d1ant_read_score_board(btcoexist, &u16tmp[0]); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx, + (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : "")); + CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x", - "ScoreBoard[14:0] (from BT)", u16tmp[0]); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : ( + coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); CL_PRINTF(cli_buf); btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); @@ -4744,20 +5289,34 @@ void ex_halbtc8723d1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) coex_sta->under_ips = true; /* Write WL "Active" in Score-board for LPS off */ - halbtc8723d1ant_post_activestate_to_bt(btcoexist, false); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE | + BT_8723D_1ANT_SCOREBOARD_ONOFF | + BT_8723D_1ANT_SCOREBOARD_SCAN | + BT_8723D_1ANT_SCOREBOARD_UNDERTEST, + false); halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); + + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_WLAN_OFF); + halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); } else if (BTC_IPS_LEAVE == type) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], IPS LEAVE notify\n"); BTC_TRACE(trace_buf); - halbtc8723d1ant_post_activestate_to_bt(btcoexist, true); +#if 0 + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE, true); + + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ONOFF, true); +#endif halbtc8723d1ant_init_hw_config(btcoexist, false, false); - halbtc8723d1ant_init_coex_dm(btcoexist); + halbtc8723d1ant_init_coex_dm(btcoexist);; coex_sta->under_ips = false; } @@ -4776,11 +5335,13 @@ void ex_halbtc8723d1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) if (coex_sta->force_lps_on == true) { /* LPS No-32K */ /* Write WL "Active" in Score-board for PS-TDMA */ - halbtc8723d1ant_post_activestate_to_bt(btcoexist, true); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE, true); } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ /* Write WL "Non-Active" in Score-board for Native-PS */ - halbtc8723d1ant_post_activestate_to_bt(btcoexist, false); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE, false); } } else if (BTC_LPS_DISABLE == type) { @@ -4790,7 +5351,8 @@ void ex_halbtc8723d1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) coex_sta->under_lps = false; /* Write WL "Active" in Score-board for LPS off */ - halbtc8723d1ant_post_activestate_to_bt(btcoexist, true); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE, true); } } @@ -4804,6 +5366,8 @@ void ex_halbtc8723d1ant_scan_notify(IN struct btc_coexist *btcoexist, btcoexist->stop_coex_dm) return; + coex_sta->freeze_coexrun_by_btinfo = false; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); @@ -4818,18 +5382,18 @@ void ex_halbtc8723d1ant_scan_notify(IN struct btc_coexist *btcoexist, "[BTCoex], SCAN START notify\n"); BTC_TRACE(trace_buf); - halbtc8723d1ant_post_activestate_to_bt(btcoexist, true); - halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE | + BT_8723D_1ANT_SCOREBOARD_SCAN | + BT_8723D_1ANT_SCOREBOARD_ONOFF, + true); /* Force antenna setup for no scan result issue */ - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); - if (!wifi_connected) /* non-connected scan */ - halbtc8723d1ant_action_wifi_not_connected_scan(btcoexist); - else /* wifi is connected */ - halbtc8723d1ant_action_wifi_connected_scan(btcoexist); + halbtc8723d1ant_run_coexist_mechanism(btcoexist); } else { @@ -4839,13 +5403,11 @@ void ex_halbtc8723d1ant_scan_notify(IN struct btc_coexist *btcoexist, &coex_sta->scan_ap_num); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", coex_sta->scan_ap_num); + "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", + coex_sta->scan_ap_num); BTC_TRACE(trace_buf); - if (!wifi_connected) - halbtc8723d1ant_action_wifi_not_connected(btcoexist); - else - halbtc8723d1ant_action_wifi_connected(btcoexist); + halbtc8723d1ant_run_coexist_mechanism(btcoexist); } BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -4870,13 +5432,16 @@ void ex_halbtc8723d1ant_connect_notify(IN struct btc_coexist *btcoexist, coex_sta->wifi_is_high_pri_task = true; - halbtc8723d1ant_post_activestate_to_bt(btcoexist, true); - halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE | + BT_8723D_1ANT_SCOREBOARD_SCAN | + BT_8723D_1ANT_SCOREBOARD_ONOFF, + true); /* Force antenna setup for no scan result issue */ - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], CONNECT START notify\n"); @@ -4884,19 +5449,21 @@ void ex_halbtc8723d1ant_connect_notify(IN struct btc_coexist *btcoexist, coex_dm->arp_cnt = 0; - halbtc8723d1ant_action_wifi_not_connected_asso_auth(btcoexist); + halbtc8723d1ant_run_coexist_mechanism(btcoexist); + + /* To keep TDMA case during connect process, + to avoid changed by Btinfo and runcoexmechanism */ + coex_sta->freeze_coexrun_by_btinfo = true; } else { coex_sta->wifi_is_high_pri_task = false; + coex_sta->freeze_coexrun_by_btinfo = false; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], CONNECT FINISH notify\n"); BTC_TRACE(trace_buf); - if (!wifi_connected) /* non-connected scan */ - halbtc8723d1ant_action_wifi_not_connected(btcoexist); - else - halbtc8723d1ant_action_wifi_connected(btcoexist); + halbtc8723d1ant_run_coexist_mechanism(btcoexist); } } @@ -4916,13 +5483,15 @@ void ex_halbtc8723d1ant_media_status_notify(IN struct btc_coexist *btcoexist, "[BTCoex], MEDIA connect notify\n"); BTC_TRACE(trace_buf); - halbtc8723d1ant_post_activestate_to_bt(btcoexist, true); - halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE | + BT_8723D_1ANT_SCOREBOARD_ONOFF, + true); /* Force antenna setup for no scan result issue */ - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &wifi_under_b_mode); @@ -4956,7 +5525,8 @@ void ex_halbtc8723d1ant_media_status_notify(IN struct btc_coexist *btcoexist, "[BTCoex], MEDIA disconnect notify\n"); BTC_TRACE(trace_buf); - halbtc8723d1ant_post_activestate_to_bt(btcoexist, false); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE, false); btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ @@ -4974,8 +5544,7 @@ void ex_halbtc8723d1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, boolean under_4way = false; if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) + btcoexist->stop_coex_dm) return; @@ -4994,32 +5563,43 @@ void ex_halbtc8723d1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, coex_dm->arp_cnt++; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify -cnt = %d\n", coex_dm->arp_cnt); + "[BTCoex], specific Packet ARP notify -cnt = %d\n", + coex_dm->arp_cnt); BTC_TRACE(trace_buf); } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", type); + "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", + type); BTC_TRACE(trace_buf); coex_sta->wifi_is_high_pri_task = true; coex_sta->specific_pkt_period_cnt = 2; } - if (coex_sta->wifi_is_high_pri_task) - halbtc8723d1ant_action_wifi_connected_specific_packet(btcoexist); + if (coex_sta->wifi_is_high_pri_task) { + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_SCAN, true); + halbtc8723d1ant_run_coexist_mechanism(btcoexist); + } } void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist, IN u8 *tmp_buf, IN u8 length) { - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean bt_busy = false; + u8 i, rsp_source = 0; + boolean wifi_connected = false; + boolean wifi_scan = false, wifi_link = false, wifi_roam = false, + wifi_busy = false; + static boolean is_scoreboard_scan = false; - coex_sta->c2h_bt_info_req_sent = false; + if (psd_scan->is_AntDet_running == true) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt_info_notify return for AntDet is running\n"); + BTC_TRACE(trace_buf); + return; + } rsp_source = tmp_buf[0] & 0xf; if (rsp_source >= BT_INFO_SRC_8723D_1ANT_MAX) @@ -5027,13 +5607,13 @@ void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist, coex_sta->bt_info_c2h_cnt[rsp_source]++; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, + "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, length); BTC_TRACE(trace_buf); + for (i = 0; i < length; i++) { coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; + if (i == length - 1) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", tmp_buf[i]); @@ -5045,187 +5625,175 @@ void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist, } } + coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; + coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; + coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; + if (BT_INFO_SRC_8723D_1ANT_WIFI_FW != rsp_source) { /* if 0xff, it means BT is under WHCK test */ - if (bt_info == 0xff) - coex_sta->bt_whck_test = true; - else - coex_sta->bt_whck_test = false; + coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true : + false); + + coex_sta->bt_create_connection = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true : + false); + + /* unit: %, value-100 to translate to unit: dBm */ + coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + + 10; + + coex_sta->c2h_bt_remote_name_req = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true : + false); + + coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & + 0x10) ? true : false); + + coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & + 0x9) ? true : false); + + coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? + true : false); + + coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & + BT_INFO_8723D_1ANT_B_INQ_PAGE) ? true : false); + + coex_sta->a2dp_bit_pool = ((( + coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? + coex_sta->bt_info_c2h[rsp_source][6] : 0); - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; + coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & + 0xf; + + coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; + + coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; + + coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; + + coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; if (coex_sta->bt_retry_cnt >= 1) coex_sta->pop_event_cnt++; - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_page = true; - else - coex_sta->c2h_bt_page = false; + if (coex_sta->c2h_bt_remote_name_req) + coex_sta->cnt_RemoteNameReq++; - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x80) - coex_sta->bt_create_connection = true; - else - coex_sta->bt_create_connection = false; + if (coex_sta->bt_info_ext & BIT(1)) + coex_sta->cnt_ReInit++; - /* unit: %, value-100 to translate to unit: dBm */ - coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; + if (coex_sta->bt_info_ext & BIT(2)) { + coex_sta->cnt_setupLink++; + coex_sta->is_setupLink = true; + } else + coex_sta->is_setupLink = false; - /* coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; */ + if (coex_sta->bt_info_ext & BIT(3)) + coex_sta->cnt_IgnWlanAct++; - if ((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) { - coex_sta->a2dp_bit_pool = - coex_sta->bt_info_c2h[rsp_source][6]; - } else - coex_sta->a2dp_bit_pool = 0; + if (coex_sta->bt_info_ext & BIT(6)) + coex_sta->cnt_RoleSwitch++; - if (coex_sta->bt_info_c2h[rsp_source][1] & 0x9) - coex_sta->acl_busy = true; - else - coex_sta->acl_busy = false; + if (coex_sta->bt_create_connection) { + coex_sta->cnt_Page++; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, + &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || + (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; + is_scoreboard_scan = true; + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_SCAN, true); + + } else + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_SCAN, false); + + } else { + if (is_scoreboard_scan) { + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_SCAN, false); + is_scoreboard_scan = false; + } + } /* Here we need to resend some wifi info to BT */ /* because bt is reset and loss of the info. */ - if ((!btcoexist->manual_control) && (!btcoexist->stop_coex_dm)) { + if ((!btcoexist->manual_control) && + (!btcoexist->stop_coex_dm)) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); - /* Re-Init */ - if (coex_sta->bt_info_ext & BIT(1)) { + /* Re-Init */ + if ((coex_sta->bt_info_ext & BIT(1))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); if (wifi_connected) - halbtc8723d1ant_update_wifi_channel_info(btcoexist, - BTC_MEDIA_CONNECT); + halbtc8723d1ant_update_wifi_channel_info( + btcoexist, BTC_MEDIA_CONNECT); else - halbtc8723d1ant_update_wifi_channel_info(btcoexist, - BTC_MEDIA_DISCONNECT); + halbtc8723d1ant_update_wifi_channel_info( + btcoexist, + BTC_MEDIA_DISCONNECT); } - /* If Ignore_WLanAct && not SetUp_Link */ - if ((coex_sta->bt_info_ext & BIT(3)) && (!(coex_sta->bt_info_ext & BIT(2)))) { + + /* If Ignore_WLanAct && not SetUp_Link or Role_Switch */ + if ((coex_sta->bt_info_ext & BIT(3)) && + (!(coex_sta->bt_info_ext & BIT(2))) && + (!(coex_sta->bt_info_ext & BIT(6)))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); BTC_TRACE(trace_buf); halbtc8723d1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, false); + } else { + if (coex_sta->bt_info_ext & BIT(2)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ignore Wlan active because Re-link!!\n"); + BTC_TRACE(trace_buf); + } else if (coex_sta->bt_info_ext & BIT(6)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ignore Wlan active because Role-Switch!!\n"); + BTC_TRACE(trace_buf); + } } } - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8723D_1ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - } - - coex_sta->num_of_profile = 0; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8723D_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - - coex_sta->bt_hi_pri_link_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8723D_1ANT_B_FTP) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8723D_1ANT_B_A2DP) { - coex_sta->a2dp_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8723D_1ANT_B_HID) { - coex_sta->hid_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) { - coex_sta->sco_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = false; - - } - - halbtc8723d1ant_update_bt_link_info(btcoexist); - - bt_info = bt_info & - 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ - - if (!(bt_info & BT_INFO_8723D_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8723D_1ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8723D_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8723D_1ANT_B_ACL_BUSY) { - if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) - coex_dm->auto_tdma_adjust = false; - coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), No run_coexist_mechanism return for Manual CTRL<===\n"); - BTC_TRACE(trace_buf); - return; } - if (btcoexist->stop_coex_dm) { + if ((coex_sta->bt_info_ext & BIT(5))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), No run_coexist_mechanism return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + BTC_TRACE(trace_buf); + coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist); + + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x4); } - /* don't run coex mechanism while receve BTInfo if GNT_WL/GNT_BT control by SW */ - if (!coex_sta->gnt_control_by_PTA) - return; + halbtc8723d1ant_update_bt_link_info(btcoexist); halbtc8723d1ant_run_coexist_mechanism(btcoexist); } + + void ex_halbtc8723d1ant_rf_status_notify(IN struct btc_coexist *btcoexist, IN u8 type) { @@ -5238,11 +5806,13 @@ void ex_halbtc8723d1ant_rf_status_notify(IN struct btc_coexist *btcoexist, "[BTCoex], RF is turned ON!!\n"); BTC_TRACE(trace_buf); - coex_sta->wl_rf_off_on_event = true; btcoexist->stop_coex_dm = false; - - halbtc8723d1ant_post_activestate_to_bt(btcoexist, TRUE); - halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, TRUE); +#if 0 + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE, true); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ONOFF, true); +#endif } else if (BTC_RF_OFF == type) { @@ -5250,15 +5820,20 @@ void ex_halbtc8723d1ant_rf_status_notify(IN struct btc_coexist *btcoexist, "[BTCoex], RF is turned OFF!!\n"); BTC_TRACE(trace_buf); - halbtc8723d1ant_post_activestate_to_bt(btcoexist, FALSE); - halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, FALSE); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE | + BT_8723D_1ANT_SCOREBOARD_ONOFF | + BT_8723D_1ANT_SCOREBOARD_SCAN | + BT_8723D_1ANT_SCOREBOARD_UNDERTEST, + false); halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); + + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_WLAN_OFF); btcoexist->stop_coex_dm = true; - coex_sta->wl_rf_off_on_event = false; } } @@ -5267,16 +5842,17 @@ void ex_halbtc8723d1ant_halt_notify(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); BTC_TRACE(trace_buf); - /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, FALSE); - - - halbtc8723d1ant_post_activestate_to_bt(btcoexist, FALSE); - halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, FALSE); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE | + BT_8723D_1ANT_SCOREBOARD_ONOFF | + BT_8723D_1ANT_SCOREBOARD_SCAN | + BT_8723D_1ANT_SCOREBOARD_UNDERTEST, + false); halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, - false, true); + + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8723D_1ANT_PHASE_WLAN_OFF); halbtc8723d1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); @@ -5291,20 +5867,30 @@ void ex_halbtc8723d1ant_pnp_notify(IN struct btc_coexist *btcoexist, BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); BTC_TRACE(trace_buf); - if (BTC_WIFI_PNP_SLEEP == pnp_state) { + if ((BTC_WIFI_PNP_SLEEP == pnp_state) || + (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify to SLEEP\n"); BTC_TRACE(trace_buf); - /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, FALSE); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE | + BT_8723D_1ANT_SCOREBOARD_ONOFF | + BT_8723D_1ANT_SCOREBOARD_SCAN | + BT_8723D_1ANT_SCOREBOARD_UNDERTEST, + false); - halbtc8723d1ant_post_activestate_to_bt(btcoexist, FALSE); - halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, FALSE); + if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); + } else { + + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_WLAN_OFF); + } btcoexist->stop_coex_dm = true; } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { @@ -5312,10 +5898,12 @@ void ex_halbtc8723d1ant_pnp_notify(IN struct btc_coexist *btcoexist, BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify to WAKE UP\n"); BTC_TRACE(trace_buf); - - halbtc8723d1ant_post_activestate_to_bt(btcoexist, TRUE); - halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, TRUE); - +#if 0 + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ACTIVE, true); + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_ONOFF, true); +#endif btcoexist->stop_coex_dm = false; } } @@ -5334,6 +5922,17 @@ void ex_halbtc8723d1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist) { + struct btc_board_info *board_info = &btcoexist->board_info; + boolean wifi_busy = false; + u4Byte value = 0; + u32 bt_patch_ver; + static u8 cnt = 0; + boolean bt_relink_finish = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ************* Periodical *************\n"); + BTC_TRACE(trace_buf); + #if (BT_AUTO_REPORT_ONLY_8723D_1ANT == 0) halbtc8723d1ant_query_bt_info(btcoexist); @@ -5344,33 +5943,158 @@ void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist) halbtc8723d1ant_monitor_bt_enable_disable(btcoexist); +#if 0 + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + /* halbtc8723d1ant_read_score_board(btcoexist, &bt_scoreboard_val); */ + + if (wifi_busy) { + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_UNDERTEST, true); + /* + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_WLBUSY, true); + + if (bt_scoreboard_val & BIT(6)) + halbtc8723d1ant_query_bt_info(btcoexist); */ + } else { + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_UNDERTEST, false); + /* + halbtc8723d1ant_post_state_to_bt(btcoexist, + BT_8723D_1ANT_SCOREBOARD_WLBUSY, + false); */ + } +#endif + + if (coex_sta->bt_relink_downcount != 0) { + coex_sta->bt_relink_downcount--; + + if (coex_sta->bt_relink_downcount == 0) + bt_relink_finish = true; + } + /* for 4-way, DHCP, EAPOL packet */ if (coex_sta->specific_pkt_period_cnt > 0) { coex_sta->specific_pkt_period_cnt--; - if ((coex_sta->specific_pkt_period_cnt == 0) && (coex_sta->wifi_is_high_pri_task)) + if ((coex_sta->specific_pkt_period_cnt == 0) && + (coex_sta->wifi_is_high_pri_task)) coex_sta->wifi_is_high_pri_task = false; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", (coex_sta->wifi_is_high_pri_task ? "Yes" : "No")); + "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", + (coex_sta->wifi_is_high_pri_task ? "Yes" : + "No")); BTC_TRACE(trace_buf); } + if (!coex_sta->bt_disabled) { + if (coex_sta->bt_coex_supported_feature == 0) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + if (coex_sta->bt_reg_vendor_ac == 0xffff) + coex_sta->bt_reg_vendor_ac = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xac) & 0xffff); + + if (coex_sta->bt_reg_vendor_ae == 0xffff) + coex_sta->bt_reg_vendor_ae = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xae) & 0xffff); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, + &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) { + cnt++; + + if (cnt >= 3) { + btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, + &coex_sta->bt_afh_map[0]); + cnt = 0; + } + } + +#if BT_8723D_1ANT_ANTDET_ENABLE + + if (board_info->btdm_ant_det_finish) { + if ((psd_scan->ant_det_result == 12) && + (psd_scan->ant_det_psd_scan_peak_val == 0) + && (!psd_scan->is_AntDet_running)) { + psd_scan->ant_det_psd_scan_peak_val = + btcoexist->btc_get_ant_det_val_from_bt( + btcoexist) * 100; + + board_info->antdetval = psd_scan->ant_det_psd_scan_peak_val/100; + value = board_info->antdetval; + +#ifdef PLATFORM_WINDOWS + { + PWCHAR registryName; + + registryName = L"antdetval"; + PlatformWriteCommonDwordRegistry(registryName, &value); + } +#endif + } + } + +#endif + } + if (halbtc8723d1ant_is_wifibt_status_changed(btcoexist)) halbtc8723d1ant_run_coexist_mechanism(btcoexist); } +void ex_halbtc8723d1ant_set_antenna_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (type == 2) { /* two antenna */ + board_info->ant_div_cfg = true; + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); + } else { /* one antenna */ + halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); + } +} + +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist, IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) { -#if BT_8723D_1ANT_ANTDET_ENABLE + static u32 ant_det_count = 0, ant_det_fail_count = 0; struct btc_board_info *board_info = &btcoexist->board_info; - /*boolean scan, roam;*/ + u16 u16tmp; + u8 AntDetval = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx Ext Call AntennaDetect()!!\n"); + BTC_TRACE(trace_buf); + +#if BT_8723D_1ANT_ANTDET_ENABLE BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx Call AntennaDetect()!!\n"); @@ -5395,31 +6119,118 @@ void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist, BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n"); BTC_TRACE(trace_buf); - halbtc8723d1ant_psd_antenna_detection_check(btcoexist); + + psd_scan->is_AntDet_running = true; + + halbtc8723d1ant_read_score_board(btcoexist, &u16tmp); + + if (u16tmp & BIT( + 2)) { /* Antenna detection is already done before last WL power on */ + board_info->btdm_ant_det_finish = true; + psd_scan->ant_det_try_count = 1; + psd_scan->ant_det_fail_count = 0; + board_info->btdm_ant_num_by_ant_det = (u16tmp & + BIT(3)) ? 1 : 2; + psd_scan->ant_det_result = 12; + + psd_scan->ant_det_psd_scan_peak_val = + btcoexist->btc_get_ant_det_val_from_bt( + btcoexist) * 100; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Result from BT (%d-Ant)\n", + board_info->btdm_ant_num_by_ant_det); + BTC_TRACE(trace_buf); + } else + board_info->btdm_ant_det_finish = + halbtc8723d1ant_psd_antenna_detection_check( + btcoexist); + + board_info->ant_det_result = psd_scan->ant_det_result; + btcoexist->bdontenterLPS = false; if (board_info->btdm_ant_det_finish) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n"); BTC_TRACE(trace_buf); -#if 1 - if (board_info->btdm_ant_num_by_ant_det == 2) - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, false, false); - else - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); -#endif + + if (board_info->btdm_ant_num_by_ant_det == 2) { + board_info->ant_div_cfg = true; + halbtc8723d1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_WIFI, FORCE_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); + } else + halbtc8723d1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8723D_1ANT_PHASE_2G_RUNTIME); + + /*for 8723d, btc_set_bt_trx_mask is just used to + notify BT stop le tx and Ant Det Result , not set BT RF TRx Mask */ + if (psd_scan->ant_det_result != 12) { + + AntDetval = (u8)( + psd_scan->ant_det_psd_scan_peak_val + / 100) & 0x7f; + + AntDetval = + (board_info->btdm_ant_num_by_ant_det + == 1) ? (AntDetval | 0x80) : + AntDetval; + board_info->antdetval = AntDetval; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxx AntennaDetect(), Ant Count = %d, PSD Val = %d\n", + ((AntDetval & + 0x80) ? 1 + : 2), AntDetval + & 0x7f); + BTC_TRACE(trace_buf); + + if (btcoexist->btc_set_bt_trx_mask( + btcoexist, AntDetval)) + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask ok!\n"); + else + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask fail!\n"); + + BTC_TRACE(trace_buf); + } else + board_info->antdetval = + psd_scan->ant_det_psd_scan_peak_val/100; + + board_info->btdm_ant_det_complete_fail = false; + } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n"); BTC_TRACE(trace_buf); + + board_info->btdm_ant_det_complete_fail = true; } + psd_scan->ant_det_inteval_count = 0; + psd_scan->is_AntDet_running = false; + /* stimulate coex running */ + halbtc8723d1ant_run_coexist_mechanism( + btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); + BTC_TRACE(trace_buf); + } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n", psd_scan->ant_det_inteval_count); BTC_TRACE(trace_buf); + + if (psd_scan->ant_det_inteval_count == 8) + btcoexist->bdontenterLPS = true; + else + btcoexist->bdontenterLPS = false; } } @@ -5439,7 +6250,6 @@ void ex_halbtc8723d1ant_display_ant_detection(IN struct btc_coexist *btcoexist) if (board_info->btdm_ant_det_finish) halbtc8723d1ant_psd_showdata(btcoexist); - return; } #endif @@ -5463,3 +6273,4 @@ void ex_halbtc8723d1ant_psd_scan(IN struct btc_coexist *btcoexist, #endif #endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ + diff --git a/hal/btc/halbtc8723d1ant.h b/hal/btc/halbtc8723d1ant.h index 2ccd575..a8fb447 100644 --- a/hal/btc/halbtc8723d1ant.h +++ b/hal/btc/halbtc8723d1ant.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) @@ -6,6 +20,7 @@ /* ******************************************* * The following is for 8723D 1ANT BT Co-exist definition * ******************************************* */ +#define BT_8723D_1ANT_COEX_DBG 0 #define BT_AUTO_REPORT_ONLY_8723D_1ANT 1 #define BT_INFO_8723D_1ANT_B_FTP BIT(7) @@ -23,6 +38,8 @@ #define BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT 2 #define BT_8723D_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ +#define BT_8723D_1ANT_DEFAULT_ISOLATION 15 /* unit: dB */ + /* for Antenna detection */ #define BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 @@ -30,11 +47,11 @@ #define BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 #define BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT 35 #define BT_8723D_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8723D_1ANT_ANTDET_SWEEPPOINT_DELAY 40000 -#define BT_8723D_1ANT_ANTDET_ENABLE 0 -#define BT_8723D_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0 +#define BT_8723D_1ANT_ANTDET_SWEEPPOINT_DELAY 60000 +#define BT_8723D_1ANT_ANTDET_ENABLE 1 #define BT_8723D_1ANT_ANTDET_BTTXTIME 100 #define BT_8723D_1ANT_ANTDET_BTTXCHANNEL 39 +#define BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT 50 #define BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 @@ -120,6 +137,26 @@ enum bt_8723d_1ant_coex_algo { BT_8723D_1ANT_COEX_ALGO_MAX = 0xb, }; +enum bt_8723d_1ant_phase { + BT_8723D_1ANT_PHASE_COEX_INIT = 0x0, + BT_8723D_1ANT_PHASE_WLANONLY_INIT = 0x1, + BT_8723D_1ANT_PHASE_WLAN_OFF = 0x2, + BT_8723D_1ANT_PHASE_2G_RUNTIME = 0x3, + BT_8723D_1ANT_PHASE_5G_RUNTIME = 0x4, + BT_8723D_1ANT_PHASE_BTMPMODE = 0x5, + BT_8723D_1ANT_PHASE_ANTENNA_DET = 0x6, + BT_8723D_1ANT_PHASE_COEX_POWERON = 0x7, + BT_8723D_1ANT_PHASE_MAX +}; + +enum bt_8723d_1ant_Scoreboard { + BT_8723D_1ANT_SCOREBOARD_ACTIVE = BIT(0), + BT_8723D_1ANT_SCOREBOARD_ONOFF = BIT(1), + BT_8723D_1ANT_SCOREBOARD_SCAN = BIT(2), + BT_8723D_1ANT_SCOREBOARD_UNDERTEST = BIT(3), + BT_8723D_1ANT_SCOREBOARD_WLBUSY = BIT(6) +}; + struct coex_dm_8723d_1ant { /* hw setting */ u8 pre_ant_pos_type; @@ -131,7 +168,6 @@ struct coex_dm_8723d_1ant { u8 cur_ps_tdma; u8 ps_tdma_para[5]; u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; boolean pre_ps_tdma_on; boolean cur_ps_tdma_on; boolean pre_bt_auto_report; @@ -179,66 +215,102 @@ struct coex_dm_8723d_1ant { }; struct coex_sta_8723d_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - boolean bt_hi_pri_link_exist; + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + boolean bt_hi_pri_link_exist; u8 num_of_profile; - boolean under_lps; - boolean under_ips; + boolean under_lps; + boolean under_ips; u32 specific_pkt_period_cnt; u32 high_priority_tx; u32 high_priority_rx; u32 low_priority_tx; u32 low_priority_rx; + boolean is_hiPri_rx_overhead; s8 bt_rssi; - boolean bt_tx_rx_mask; + boolean bt_tx_rx_mask; u8 pre_bt_rssi_state; u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; u8 bt_info_c2h[BT_INFO_SRC_8723D_1ANT_MAX][10]; u32 bt_info_c2h_cnt[BT_INFO_SRC_8723D_1ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; + boolean c2h_bt_page; /* Add for win8.1 page out issue */ + boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ u8 bt_retry_cnt; u8 bt_info_ext; + u8 bt_info_ext2; u32 pop_event_cnt; u8 scan_ap_num; u32 crc_ok_cck; u32 crc_ok_11g; u32 crc_ok_11n; - u32 crc_ok_11n_agg; + u32 crc_ok_11n_vht; u32 crc_err_cck; u32 crc_err_11g; u32 crc_err_11n; - u32 crc_err_11n_agg; + u32 crc_err_11n_vht; - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; + boolean cck_lock; + boolean pre_ccklock; + boolean cck_ever_lock; u8 coex_table_type; - boolean force_lps_on; - u32 wrong_profile_notification; + boolean force_lps_on; - boolean concurrent_rx_mode_on; + boolean concurrent_rx_mode_on; u16 score_board; + u8 isolation_btween_wb; /* 0~ 50 */ u8 a2dp_bit_pool; u8 cut_version; boolean acl_busy; - boolean wl_rf_off_on_event; boolean bt_create_connection; - boolean gnt_control_by_PTA; + + u32 bt_coex_supported_feature; + u32 bt_coex_supported_version; + + u8 bt_ble_scan_type; + u32 bt_ble_scan_para[3]; + + boolean run_time_state; + boolean freeze_coexrun_by_btinfo; + + boolean is_A2DP_3M; + boolean voice_over_HOGP; + u8 bt_info; + boolean is_autoslot; + u8 forbidden_slot; + u8 hid_busy_num; + u8 hid_pair_cnt; + + u32 cnt_RemoteNameReq; + u32 cnt_setupLink; + u32 cnt_ReInit; + u32 cnt_IgnWlanAct; + u32 cnt_Page; + u32 cnt_RoleSwitch; + + u16 bt_reg_vendor_ac; + u16 bt_reg_vendor_ae; + + boolean is_setupLink; + u8 wl_noisy_level; + u32 gnt_error_cnt; + + u8 bt_afh_map[10]; + u8 bt_relink_downcount; + boolean is_tdma_btautoslot; + boolean is_tdma_btautoslot_hang; }; #define BT_8723D_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ @@ -275,10 +347,13 @@ struct psdscan_sta_8723d_1ant { u32 psd_stop_point; u32 psd_max_value_point; u32 psd_max_value; + u32 psd_max_value2; + u32 psd_avg_value; /* filter loop_max_value that below BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/ + u32 psd_loop_max_value[BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT]; /*max value in each loop */ u32 psd_start_base; u32 psd_avg_num; /* 1/8/16/32 */ u32 psd_gen_count; - boolean is_psd_running; + boolean is_AntDet_running; boolean is_psd_show_max_only; }; @@ -311,6 +386,8 @@ void ex_halbtc8723d1ant_pnp_notify(IN struct btc_coexist *btcoexist, IN u8 pnp_state); void ex_halbtc8723d1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8723d1ant_set_antenna_notify(IN struct btc_coexist *btcoexist, + IN u8 type); void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist); void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist, IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); @@ -339,6 +416,7 @@ void ex_halbtc8723d1ant_display_ant_detection(IN struct btc_coexist *btcoexist); #define ex_halbtc8723d1ant_coex_dm_reset(btcoexist) #define ex_halbtc8723d1ant_periodical(btcoexist) #define ex_halbtc8723d1ant_display_coex_info(btcoexist) +#define ex_halbtc8723d1ant_set_antenna_notify(btcoexist, type) #define ex_halbtc8723d1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) #define ex_halbtc8723d1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) #define ex_halbtc8723d1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) @@ -346,3 +424,4 @@ void ex_halbtc8723d1ant_display_ant_detection(IN struct btc_coexist *btcoexist); #endif #endif + diff --git a/hal/btc/halbtc8723d2ant.c b/hal/btc/halbtc8723d2ant.c index a2801ae..318b8ec 100644 --- a/hal/btc/halbtc8723d2ant.c +++ b/hal/btc/halbtc8723d2ant.c @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ /* ************************************************************ * Description: * @@ -11,7 +25,7 @@ /* ************************************************************ * include files * ************************************************************ */ -#include "Mp_Precomp.h" +#include "mp_precomp.h" #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) @@ -32,9 +46,21 @@ const char *const glbt_info_src_8723d_2ant[] = { "BT Info[bt rsp]", "BT Info[bt auto report]", }; +/* ************************************************************ + * BtCoex Version Format: + * 1. date : glcoex_ver_date_XXXXX_1ant + * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant + * 3. BtCoexVersion : glcoex_ver_btdesired_XXXXX_1ant + * 4. others : glcoex_ver_XXXXXX_XXXXX_1ant + * + * Variable should be indicated IC and Antenna numbers !!! + * Please strictly follow this order and naming style !!! + * + * ************************************************************ */ +u32 glcoex_ver_date_8723d_2ant = 20161108; +u32 glcoex_ver_8723d_2ant = 0x10; +u32 glcoex_ver_btdesired_8723d_2ant = 0x10; -u32 glcoex_ver_date_8723d_2ant = 20160218; -u32 glcoex_ver_8723d_2ant = 0x05; /* ************************************************************ * local function proto type if needed @@ -167,8 +193,10 @@ void halbtc8723d2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist, s8 interference_wl_tx = 0, interference_bt_tx = 0; - interference_wl_tx = BT_8723D_2ANT_WIFI_MAX_TX_POWER - isolation_measuared; - interference_bt_tx = BT_8723D_2ANT_BT_MAX_TX_POWER - isolation_measuared; + interference_wl_tx = BT_8723D_2ANT_WIFI_MAX_TX_POWER - + isolation_measuared; + interference_bt_tx = BT_8723D_2ANT_BT_MAX_TX_POWER - + isolation_measuared; @@ -236,7 +264,6 @@ void halbtc8723d2ant_query_bt_info(IN struct btc_coexist *btcoexist) { u8 h2c_parameter[1] = {0}; - coex_sta->c2h_bt_info_req_sent = true; h2c_parameter[0] |= BIT(0); /* trigger */ @@ -247,7 +274,8 @@ void halbtc8723d2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) { u32 reg_hp_txrx, reg_lp_txrx, u32tmp; u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0, cnt_slave = 0; + static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, + cnt_autoslot_hang = 0; struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; @@ -267,6 +295,23 @@ void halbtc8723d2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) coex_sta->low_priority_tx = reg_lp_tx; coex_sta->low_priority_rx = reg_lp_rx; + if (BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + if (coex_sta->high_priority_rx >= 15) { + if (cnt_overhead < 3) + cnt_overhead++; + + if (cnt_overhead == 3) + coex_sta->is_hiPri_rx_overhead = true; + } else { + if (cnt_overhead > 0) + cnt_overhead--; + + if (cnt_overhead == 0) + coex_sta->is_hiPri_rx_overhead = false; + } + } /* reset counter */ btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); @@ -275,8 +320,10 @@ void halbtc8723d2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) (!coex_sta->c2h_bt_inquiry_page)) coex_sta->pop_event_cnt++; - if ((coex_sta->low_priority_rx >= 950) && (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) - && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && (coex_sta->bt_link_exist)) { + if ((coex_sta->low_priority_rx >= 950) && + (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) + && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && + (coex_sta->bt_link_exist)) { if (cnt_slave >= 2) { bt_link_info->slave_role = true; cnt_slave = 2; @@ -291,111 +338,197 @@ void halbtc8723d2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) } - if ((coex_sta->high_priority_tx == 0) && (coex_sta->high_priority_rx == 0) && (coex_sta->low_priority_tx == 0) && - (coex_sta->low_priority_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8723d2ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; + if (coex_sta->is_tdma_btautoslot) { + if ((coex_sta->low_priority_tx >= 1300) && + (coex_sta->low_priority_rx <= 150)) { + if (cnt_autoslot_hang >= 2) { + coex_sta->is_tdma_btautoslot_hang = true; + cnt_autoslot_hang = 2; + } else + cnt_autoslot_hang++; + } else { + if (cnt_autoslot_hang == 0) { + coex_sta->is_tdma_btautoslot_hang = false; + cnt_autoslot_hang = 0; + } else + cnt_autoslot_hang--; } } -} - -void halbtc8723d2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ + if (!coex_sta->bt_disabled) { - - if (coex_sta->under_ips) { - coex_sta->crc_ok_cck = 0; - coex_sta->crc_ok_11g = 0; - coex_sta->crc_ok_11n = 0; - coex_sta->crc_ok_11n_agg = 0; - - coex_sta->crc_err_cck = 0; - coex_sta->crc_err_11g = 0; - coex_sta->crc_err_11n = 0; - coex_sta->crc_err_11n_agg = 0; - } else { - coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf88); - coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf94); - coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf90); - coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfb8); - - coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf84); - coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf96); - coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf92); - coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfba); + if ((coex_sta->high_priority_tx == 0) && + (coex_sta->high_priority_rx == 0) && + (coex_sta->low_priority_tx == 0) && + (coex_sta->low_priority_rx == 0)) { + num_of_bt_counter_chk++; + if (num_of_bt_counter_chk >= 3) { + halbtc8723d2ant_query_bt_info(btcoexist); + num_of_bt_counter_chk = 0; + } + } } - /* reset counter */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0); } - -boolean halbtc8723d2ant_is_wifibt_status_changed(IN struct btc_coexist *btcoexist) +void halbtc8723d2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) { - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false, pre_bt_off = false; - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH; +#if 1 + s32 wifi_rssi = 0; + boolean wifi_busy = false, wifi_under_b_mode = false, + wifi_scan = false; + boolean bt_idle = false, wl_idle = false; + static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, + wl_noisy_count1 = 3, wl_noisy_count2 = 0; + u32 total_cnt, reg_val1, reg_val2, cck_cnt; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_VHT); + + cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; + + if (cck_cnt > 250) { + if (wl_noisy_count2 < 3) + wl_noisy_count2++; + + if (wl_noisy_count2 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count1 = 0; + } + } else if (cck_cnt < 50) { + if (wl_noisy_count0 < 3) + wl_noisy_count0++; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); + if (wl_noisy_count0 == 3) { + wl_noisy_count1 = 0; + wl_noisy_count2 = 0; + } + } else { + if (wl_noisy_count1 < 3) + wl_noisy_count1++; - if (coex_sta->bt_disabled != pre_bt_off) { - pre_bt_off = coex_sta->bt_disabled; + if (wl_noisy_count1 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count2 = 0; + } + } - if (coex_sta->bt_disabled) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); + if (wl_noisy_count2 == 3) + coex_sta->wl_noisy_level = 2; + else if (wl_noisy_count1 == 3) + coex_sta->wl_noisy_level = 1; else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - - BTC_TRACE(trace_buf); - return true; - } + coex_sta->wl_noisy_level = 0; + + if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { + total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht; + + if ((coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY) || + (coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_SCO_BUSY)) { + if (coex_sta->crc_ok_cck > (total_cnt - + coex_sta->crc_ok_cck)) { + if (cck_lock_counter < 3) + cck_lock_counter++; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; + + if (!coex_sta->pre_ccklock) { + + if (cck_lock_counter >= 3) + coex_sta->cck_lock = true; + else + coex_sta->cck_lock = false; + } else { + if (cck_lock_counter == 0) + coex_sta->cck_lock = false; + else + coex_sta->cck_lock = true; } - } + if (coex_sta->cck_lock) + coex_sta->cck_ever_lock = true; - return false; + coex_sta->pre_ccklock = coex_sta->cck_lock; + +#endif } void halbtc8723d2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) { struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; + boolean bt_hs_on = false; + boolean bt_busy = false; + + + coex_sta->num_of_profile = 0; + + /* set link exist status */ + if (!(coex_sta->bt_info & BT_INFO_8723D_2ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_FTP) { + coex_sta->pan_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->pan_exist = false; + + if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_A2DP) { + coex_sta->a2dp_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->a2dp_exist = false; + + if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_HID) { + coex_sta->hid_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->hid_exist = false; + + if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) { + coex_sta->sco_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->sco_exist = false; + + } btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); @@ -447,6 +580,51 @@ void halbtc8723d2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) bt_link_info->hid_only = true; else bt_link_info->hid_only = false; + + if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_INQ_PAGE) { + coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_INQ_PAGE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); + } else if (!(coex_sta->bt_info & BT_INFO_8723D_2ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + } else if (coex_sta->bt_info == BT_INFO_8723D_2ANT_B_CONNECTION) { + /* connection exists but no busy */ + coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + } else if (((coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_BUSY)) && + (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_ACL_BUSY)) { + coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); + } else if ((coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + } else if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + } else { + coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + } + + BTC_TRACE(trace_buf); + + if ((BT_8723D_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8723D_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + bt_busy = true; + else + bt_busy = false; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); } void halbtc8723d2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, @@ -537,6 +715,7 @@ void halbtc8723d2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, void halbtc8723d2ant_set_fw_low_penalty_ra(IN struct btc_coexist *btcoexist, IN boolean low_penalty_ra) { +#if 1 u8 h2c_parameter[6] = {0}; h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ @@ -551,21 +730,32 @@ void halbtc8723d2ant_set_fw_low_penalty_ra(IN struct btc_coexist } btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); +#endif } void halbtc8723d2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN boolean low_penalty_ra) { +#if 1 coex_dm->cur_low_penalty_ra = low_penalty_ra; if (!force_exec) { if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) return; } + halbtc8723d2ant_set_fw_low_penalty_ra(btcoexist, - coex_dm->cur_low_penalty_ra); + coex_dm->cur_low_penalty_ra); +#if 0 + if (low_penalty_ra) + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15); + else + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); +#endif coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; + +#endif } void halbtc8723d2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, @@ -596,26 +786,10 @@ void halbtc8723d2ant_bt_auto_report(IN struct btc_coexist *btcoexist, coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; } -void halbtc8723d2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, - IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, - IN boolean limited_dig, IN boolean bt_lna_constrain) -{ - - halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8723d2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, - IN boolean agc_table_shift, IN boolean adc_back_off, - IN boolean sw_dac_swing, IN u32 dac_swing_lvl) -{ - /* halbtc8723d2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */ - /* halbtc8723d2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */ -} - void halbtc8723d2ant_write_score_board( IN struct btc_coexist *btcoexist, IN u16 bitpos, - IN BOOLEAN state + IN boolean state ) { @@ -641,32 +815,102 @@ void halbtc8723d2ant_read_score_board( 0xaa)) & 0x7fff; } -void halbtc8723d2ant_post_activestate_to_bt( + +void halbtc8723d2ant_post_state_to_bt( IN struct btc_coexist *btcoexist, - IN boolean wifi_active + IN u16 type, + IN boolean state ) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8723d2ant_post_state_to_bt: type = %d, state =%d\n", + type, state); + BTC_TRACE(trace_buf); - if (wifi_active) - halbtc8723d2ant_write_score_board(btcoexist, (u16) BIT(0), TRUE); - else - halbtc8723d2ant_write_score_board(btcoexist, (u16) BIT(0), FALSE); - - /* The BT should set "No Shunt-down" mode if WL = Active for BT Synthesizer on/off interference WL Lo issue at 8703b b-cut. */ + halbtc8723d2ant_write_score_board(btcoexist, (u16) type, state); } -void halbtc8723d2ant_post_onoffstate_to_bt( - IN struct btc_coexist *btcoexist, - IN boolean wifi_on -) +boolean halbtc8723d2ant_is_wifibt_status_changed(IN struct btc_coexist + *btcoexist) { - if (wifi_on) - halbtc8723d2ant_write_score_board(btcoexist, (u16) BIT(1), TRUE); - else - halbtc8723d2ant_write_score_board(btcoexist, (u16) BIT(1), FALSE); + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false, pre_bt_off = false, pre_bt_slave = false; + static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (coex_sta->bt_disabled != pre_bt_off) { + pre_bt_off = coex_sta->bt_disabled; + + if (coex_sta->bt_disabled) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + return true; + } + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + + if (wifi_busy) + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_UNDERTEST, true); + else + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_UNDERTEST, false); + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { + pre_wl_noisy_level = coex_sta->wl_noisy_level; + return true; + } + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->hid_busy_num != pre_hid_busy_num) { + pre_hid_busy_num = coex_sta->hid_busy_num; + return true; + } + } + + if (bt_link_info->slave_role != pre_bt_slave) { + pre_bt_slave = bt_link_info->slave_role; + return true; + } + return false; } void halbtc8723d2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) @@ -716,6 +960,10 @@ void halbtc8723d2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) &bt_disabled); } + if (bt_disabled) + halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); + else + halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true); if (coex_sta->bt_disabled != bt_disabled) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -728,10 +976,12 @@ void halbtc8723d2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) } + + void halbtc8723d2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, boolean isenable) { - +#if BT_8723D_2ANT_COEX_DBG if (isenable) { btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); @@ -764,7 +1014,7 @@ void halbtc8723d2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x1); } - +#endif } u32 halbtc8723d2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, @@ -788,7 +1038,8 @@ u32 halbtc8723d2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, } -void halbtc8723d2ant_ltecoex_indirect_write_reg(IN struct btc_coexist *btcoexist, +void halbtc8723d2ant_ltecoex_indirect_write_reg(IN struct btc_coexist + *btcoexist, IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) { u32 val, i = 0, j = 0, bitpos = 0; @@ -866,67 +1117,66 @@ void halbtc8723d2ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, void halbtc8723d2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, IN u8 control_block, IN boolean sw_control, IN u8 state) { - u32 val = 0, bit_mask; + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; - state = state & 0x1; - val = (sw_control) ? ((state << 1) | 0x1) : 0; + val_orig = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); switch (control_block) { case BT_8723D_2ANT_GNT_BLOCK_RFC_BB: default: - bit_mask = 0xc000; - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[15:14] */ - bit_mask = 0x0c00; - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[11:10] */ + val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff); break; case BT_8723D_2ANT_GNT_BLOCK_RFC: - bit_mask = 0xc000; - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[15:14] */ + val = (val << 14) | (val_orig & 0xffff3fff); break; case BT_8723D_2ANT_GNT_BLOCK_BB: - bit_mask = 0x0c00; - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[11:10] */ + val = (val << 10) | (val_orig & 0xfffff3ff); break; - } + halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); } + void halbtc8723d2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, IN u8 control_block, IN boolean sw_control, IN u8 state) { - u32 val = 0, bit_mask; + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; - state = state & 0x1; - val = (sw_control) ? ((state << 1) | 0x1) : 0; + val_orig = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); switch (control_block) { case BT_8723D_2ANT_GNT_BLOCK_RFC_BB: default: - bit_mask = 0x3000; - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[13:12] */ - bit_mask = 0x0300; - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[9:8] */ + val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff); break; case BT_8723D_2ANT_GNT_BLOCK_RFC: - bit_mask = 0x3000; - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[13:12] */ + val = (val << 12) | (val_orig & 0xffffcfff); break; case BT_8723D_2ANT_GNT_BLOCK_BB: - bit_mask = 0x0300; - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[9:8] */ + val = (val << 8) | (val_orig & 0xfffffcff); break; - } + halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); } void halbtc8723d2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, @@ -978,6 +1228,40 @@ void halbtc8723d2ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, } +void halbtc8723d2ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 interval, + IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, + IN u8 val0x6c4_b3) +{ + static u8 pre_h2c_parameter[6] = {0}; + u8 cur_h2c_parameter[6] = {0}; + u8 i, match_cnt = 0; + + cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ + + cur_h2c_parameter[1] = interval; + cur_h2c_parameter[2] = val0x6c4_b0; + cur_h2c_parameter[3] = val0x6c4_b1; + cur_h2c_parameter[4] = val0x6c4_b2; + cur_h2c_parameter[5] = val0x6c4_b3; + + if (!force_exec) { + for (i = 1; i <= 5; i++) { + if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) + break; + + match_cnt++; + } + + if (match_cnt == 5) + return; + } + + for (i = 1; i <= 5; i++) + pre_h2c_parameter[i] = cur_h2c_parameter[i]; + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); +} void halbtc8723d2ant_set_coex_table(IN struct btc_coexist *btcoexist, IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) @@ -1033,46 +1317,50 @@ void halbtc8723d2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, select_table = 0x3; } - switch (type) { - case 0: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0xffffffff, 0xffffffff, break_table, select_table); - break; - case 1: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, break_table, select_table); - break; - case 2: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table); - break; - case 3: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0xdafadafa, 0xdafadafa, break_table, select_table); - break; - case 4: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0xddffddff, 0xffbbffbb, break_table, select_table); - break; - case 5: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5fff5fff, break_table, select_table); - break; - case 6: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0x55ff55ff, 0x5a5a5a5a, break_table, select_table); - break; - case 7: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0x5aff55ff, 0x5a7a5a7a, break_table, select_table); - break; - case 8: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaaaaaa, break_table, select_table); - break; - default: - break; - } + switch (type) { + case 0: + halbtc8723d2ant_coex_table(btcoexist, force_exec, + 0xffffffff, 0xffffffff, break_table, select_table); + break; + case 1: + halbtc8723d2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, select_table); + break; + case 2: + halbtc8723d2ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table); + break; + case 3: + halbtc8723d2ant_coex_table(btcoexist, force_exec, + 0xaa555555, 0xaa5a5a5a, break_table, select_table); + break; + case 4: + halbtc8723d2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, select_table); + break; + case 5: + halbtc8723d2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, break_table, select_table); + break; + case 6: + halbtc8723d2ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xfafafafa, break_table, select_table); + break; + case 7: + halbtc8723d2ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xaa5a5a5a, break_table, select_table); + break; + case 8: + halbtc8723d2ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xfafafafa, break_table, select_table); + break; + case 9: + halbtc8723d2ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0xaaaa5aaa, break_table, select_table); + break; + default: + break; + } } void halbtc8723d2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, @@ -1080,8 +1368,9 @@ void halbtc8723d2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, { u8 h2c_parameter[1] = {0}; - if (enable) + if (enable) { h2c_parameter[0] |= BIT(0); /* function enable */ + } btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); } @@ -1143,14 +1432,16 @@ void halbtc8723d2ant_ps_tdma_check_for_power_save_state( /* will leave LPS state, turn off psTdma first */ /*halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); } } else { /* NO PS state */ if (new_ps_state) { /* will enter LPS state, turn off psTdma first */ /*halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);*/ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); } else { /* keep state under NO PS state, do nothing. */ } @@ -1208,6 +1499,18 @@ void halbtc8723d2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, u8 h2c_parameter[5] = {0}; u8 real_byte1 = byte1, real_byte5 = byte5; boolean ap_enable = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if (byte5 & BIT(2)) + coex_sta->is_tdma_btautoslot = true; + else + coex_sta->is_tdma_btautoslot = false; + + /* release bt-auto slot for auto-slot hang is detected!! */ + if (coex_sta->is_tdma_btautoslot) + if ((coex_sta->is_tdma_btautoslot_hang) || + (bt_link_info->slave_role)) + byte5 = byte5 & 0xfb; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable); @@ -1215,7 +1518,7 @@ void halbtc8723d2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, if (ap_enable) { if (byte1 & BIT(4) && !(byte1 & BIT(5))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); + "[BTCoex], FW for AP mode\n"); BTC_TRACE(trace_buf); real_byte1 &= ~BIT(4); real_byte1 |= BIT(5); @@ -1223,7 +1526,8 @@ void halbtc8723d2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, real_byte5 |= BIT(5); real_byte5 &= ~BIT(6); - halbtc8723d2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + halbtc8723d2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); } } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { @@ -1232,7 +1536,8 @@ void halbtc8723d2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, btcoexist, BTC_PS_LPS_ON, 0x50, 0x4); } else { - halbtc8723d2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + halbtc8723d2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); } @@ -1281,109 +1586,179 @@ void halbtc8723d2ant_ps_tdma(IN struct btc_coexist *btcoexist, return; } - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s turn %s PS TDMA, type=%d\n", - (force_exec ? "force to" : ""), (turn_on ? "ON" : "OFF"), type); - BTC_TRACE(trace_buf); - - - if (turn_on) { + if (coex_dm->cur_ps_tdma_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(on, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, 0x1); /* enable TBTT nterrupt */ + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); } if (turn_on) { switch (type) { case 1: - default: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x03, 0xf1, - 0x14 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x91, + 0x54 | psTdmaByte4Modify); break; case 2: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x03, 0x71, - 0x11 | psTdmaByte4Modify); + default: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); break; case 3: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3a, 0x3, 0xf1, - 0x10 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x3a, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); break; case 4: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x21, 0x3, 0xf1, - 0x10 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x21, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); break; case 5: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x30, 0x3, 0xf1, - 0x10 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); break; case 6: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, - 0x10 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); break; case 7: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0xf1, - 0x10 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x20, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 8: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x15, 0x03, 0x11, + 0x11); + break; + case 10: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x30, 0x03, 0x11, + 0x10); break; case 11: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x30, 0x03, 0x71, - 0x10 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, + 0x10 | psTdmaByte4Modify); break; case 12: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x21, 0x03, 0x71, - 0x11 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, 0x11); break; case 13: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x03, 0x71, - 0x10 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x1c, 0x03, 0x11, + 0x10 | psTdmaByte4Modify); + break; + case 14: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x20, 0x03, 0x11, + 0x11); + break; + case 15: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x14); + break; + case 16: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x15); + break; + case 21: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x30, 0x03, 0x11, + 0x10); + break; + case 22: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, + 0x10); + break; + case 23: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x10); + break; + case 51: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x91, + 0x10 | psTdmaByte4Modify); break; case 101: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x10, 0x03, 0x70, - 0x14 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x03, 0x10, + 0x54 | psTdmaByte4Modify); break; case 102: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x03, 0x71, - 0x11 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); break; case 103: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x3a, 0x3, 0x70, - 0x10 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, + 0x3a, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); break; case 104: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x21, 0x3, 0x70, - 0x10 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, + 0x21, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); break; case 105: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x30, 0x3, 0x70, - 0x10 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, + 0x25, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); break; case 106: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1c, 0x3, 0x70, - 0x10 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); break; case 107: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x25, 0x3, 0x70, - 0x10 | psTdmaByte4Modify); + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, + 0x20, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 108: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 109: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x55, + 0x10, 0x03, 0x10, + 0x54 | psTdmaByte4Modify); + break; + case 110: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x55, + 0x30, 0x03, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 111: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x65, + 0x25, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); + break; + case 151: + halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x03, 0x10, + 0x50 | psTdmaByte4Modify); break; - - } } else { /* disable PS tdma */ @@ -1409,117 +1784,403 @@ void halbtc8723d2ant_ps_tdma(IN struct btc_coexist *btcoexist, } void halbtc8723d2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) + IN u8 ant_pos_type, IN boolean force_exec, + IN u8 phase) { struct btc_board_info *board_info = &btcoexist->board_info; u32 u32tmp = 0; - boolean pg_ext_switch = false; - u8 h2c_parameter[2] = {0}, u8tmp0 = 0; + boolean pg_ext_switch = false, is_hw_ant_div_on = false; + u8 h2c_parameter[2] = {0}; + u32 cnt_bt_cal_chk = 0; + u8 u8tmp0 = 0, u8tmp1 = 0; boolean is_in_mp_mode = false; u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0; - u16 u16tmp0 = 0; + u16 u16tmp0 = 0, u16tmp1 = 0; + + + u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + /* To avoid indirect access fail */ + if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { + force_exec = true; + coex_sta->gnt_error_cnt++; + } + + +#if BT_8723D_2ANT_COEX_DBG + u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa); + u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948); + u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x73); + u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before Set Ant Pat)\n", + u8tmp0, u16tmp1, u8tmp1); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa = 0x%x (Before Set Ant Path)\n", + u32tmp1, u32tmp2, u16tmp0); + BTC_TRACE(trace_buf); +#endif + + coex_dm->cur_ant_pos_type = ant_pos_type; + + if (!force_exec) { + if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Skip Antenna Path Setup because no change!!**********\n"); + BTC_TRACE(trace_buf); + return; + } + } + + coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; + + switch (phase) { + case BT_8723D_2ANT_PHASE_COEX_POWERON: + /* Set Path control to WL */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, + 0x80, 0x0); + + /* set Path control owner to WL at initial step */ + halbtc8723d2ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8723D_2ANT_PCO_BTSIDE); + + /* set GNT_BT to SW high */ + halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8723D_2ANT_GNT_BLOCK_RFC_BB, + BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW low */ + halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8723D_2ANT_GNT_BLOCK_RFC_BB, + BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_WIFI; - if (init_hwcfg) { + coex_sta->run_time_state = false; + break; + case BT_8723D_2ANT_PHASE_COEX_INIT: /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0); /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8723d2ant_ltecoex_set_coex_table(btcoexist, - BT_8723D_1ANT_CTT_WL_VS_LTE, 0xffff); + halbtc8723d2ant_ltecoex_set_coex_table( + btcoexist, + BT_8723D_2ANT_CTT_WL_VS_LTE, + 0xffff); /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8723d2ant_ltecoex_set_coex_table(btcoexist, - BT_8723D_1ANT_CTT_BT_VS_LTE, 0xffff); + halbtc8723d2ant_ltecoex_set_coex_table( + btcoexist, + BT_8723D_2ANT_CTT_BT_VS_LTE, + 0xffff); + + /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ + while (cnt_bt_cal_chk <= 20) { + u8tmp0 = btcoexist->btc_read_1byte( + btcoexist, + 0x49d); + cnt_bt_cal_chk++; + if (u8tmp0 & BIT(0)) { + BTC_SPRINTF( + trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", + cnt_bt_cal_chk); + BTC_TRACE( + trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF( + trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", + cnt_bt_cal_chk); + BTC_TRACE( + trace_buf); + break; + } + } + /* Set Path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0x67, 0x80, 0x1); /* set Path control owner to WL at initial step */ - halbtc8723d2ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_1ANT_PCO_WLSIDE); + halbtc8723d2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8723D_2ANT_PCO_WLSIDE); - /* set GNT_BT to high */ + /* set GNT_BT to SW high */ halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, BT_8723D_2ANT_GNT_BLOCK_RFC_BB, BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to high */ + /* Set GNT_WL to SW high */ halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, BT_8723D_2ANT_GNT_BLOCK_RFC_BB, BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); - /* Send antenna info (inverse, non-inverse, Int/Ext) to Firmware */ - if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { - /* tell firmware "no antenna inverse" */ - h2c_parameter[0] = 0; - } else { - /* tell firmware "antenna inverse" */ - h2c_parameter[0] = 1; + coex_sta->run_time_state = false; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; } - /* int switch type */ - h2c_parameter[1] = 0; - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, h2c_parameter); + break; + case BT_8723D_2ANT_PHASE_WLANONLY_INIT: + /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ + halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8723d2ant_ltecoex_set_coex_table( + btcoexist, + BT_8723D_2ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8723d2ant_ltecoex_set_coex_table( + btcoexist, + BT_8723D_2ANT_CTT_BT_VS_LTE, + 0xffff); + + /* Set Path control to WL */ + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0x67, 0x80, 0x1); + + /* set Path control owner to WL at initial step */ + halbtc8723d2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8723D_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Low */ + halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8723D_2ANT_GNT_BLOCK_RFC_BB, + BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_2ANT_SIG_STA_SET_TO_LOW); + /* Set GNT_WL to SW high */ + halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8723D_2ANT_GNT_BLOCK_RFC_BB, + BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = false; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } - coex_sta->gnt_control_by_PTA = false; - } else if (wifi_off) { + break; + case BT_8723D_2ANT_PHASE_WLAN_OFF: /* Disable LTE Coex Function in WiFi side */ halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0); /* Set Path control to BT */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0x67, 0x80, 0x0); - halbtc8723d2ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_1ANT_PCO_BTSIDE);/* set Path control owner to BT */ + /* set Path control owner to BT */ + halbtc8723d2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8723D_2ANT_PCO_BTSIDE); + + coex_sta->run_time_state = false; + break; + case BT_8723D_2ANT_PHASE_2G_RUNTIME: + + /* wait for WL/BT IQK finish, keep 0x38 = 0xff00 for WL IQK */ + while (cnt_bt_cal_chk <= 20) { + u8tmp0 = btcoexist->btc_read_1byte( + btcoexist, + 0x1e6); + + u8tmp1 = btcoexist->btc_read_1byte( + btcoexist, + 0x49d); + + cnt_bt_cal_chk++; + if ((u8tmp0 & BIT(0)) || + (u8tmp1 & BIT(0))) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### WL or BT is IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + break; + } + } + + /* Set Path control to WL */ + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);*/ + + /* set Path control owner to WL at runtime step */ + halbtc8723d2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8723D_2ANT_PCO_WLSIDE); - coex_sta->gnt_control_by_PTA = false; - } else { - /* set GNT_BT to PTA */ halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, BT_8723D_2ANT_GNT_BLOCK_RFC_BB, BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8723D_2ANT_SIG_STA_SET_BY_HW); + BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to PTA */ halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, BT_8723D_2ANT_GNT_BLOCK_RFC_BB, BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA, BT_8723D_2ANT_SIG_STA_SET_BY_HW); - coex_sta->gnt_control_by_PTA = true; - } + coex_sta->run_time_state = true; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } - switch (ant_pos_type) { - case BTC_ANT_WIFI_AT_MAIN: - u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0x948); - if ((u16tmp0 == 0x140) || (u16tmp0 == 0x40)) - btcoexist->btc_write_2byte(btcoexist, 0x948, u16tmp0); - else - btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0); break; - case BTC_ANT_WIFI_AT_AUX: - u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0x948); - if ((u16tmp0 == 0x140) || (u16tmp0 == 0x40)) - btcoexist->btc_write_2byte(btcoexist, 0x948, u16tmp0); - else - btcoexist->btc_write_2byte(btcoexist, 0x948, 0x280); + case BT_8723D_2ANT_PHASE_BTMPMODE: + /* Disable LTE Coex Function in WiFi side */ + halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0); + + /* Set Path control to WL */ + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0x67, 0x80, 0x1); + + /* set Path control owner to WL */ + halbtc8723d2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8723D_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Hi */ + halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8723D_2ANT_GNT_BLOCK_RFC_BB, + BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); + + /* Set GNT_WL to SW Lo */ + halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8723D_2ANT_GNT_BLOCK_RFC_BB, + BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_2ANT_SIG_STA_SET_TO_LOW); + + coex_sta->run_time_state = false; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + break; + case BT_8723D_2ANT_PHASE_ANTENNA_DET: + + /* Set Path control to WL */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, + 0x80, 0x1); + + /* set Path control owner to WL */ + halbtc8723d2ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8723D_2ANT_PCO_WLSIDE); + + /* Set Antenna Path, both GNT_WL/GNT_BT = 1, and control by SW */ + /* set GNT_BT to SW high */ + halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8723D_2ANT_GNT_BLOCK_RFC_BB, + BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); + + /* Set GNT_WL to SW high */ + halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8723D_2ANT_GNT_BLOCK_RFC_BB, + BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_WIFI_AT_AUX; + + coex_sta->run_time_state = false; + break; } + is_hw_ant_div_on = board_info->ant_div_cfg; - u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); - u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0x948); - u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70); + if ((is_hw_ant_div_on) && (phase != BT_8723D_2ANT_PHASE_ANTENNA_DET)) + btcoexist->btc_write_2byte(btcoexist, 0x948, 0x140); + else if ((is_hw_ant_div_on == false) && + (phase != BT_8723D_2ANT_PHASE_WLAN_OFF)) { + + switch (ant_pos_type) { + case BTC_ANT_WIFI_AT_MAIN: + + btcoexist->btc_write_2byte(btcoexist, + 0x948, 0x0); + break; + case BTC_ANT_WIFI_AT_AUX: + + btcoexist->btc_write_2byte(btcoexist, + 0x948, 0x280); + break; + } + } + + +#if BT_8723D_2ANT_COEX_DBG u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa); + u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948); + u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x73); + u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(After Set Ant Pat)\n", + u8tmp0, u16tmp1, u8tmp1); + BTC_TRACE(trace_buf); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (After Set Ant Path) **********\n", - u8tmp0, u16tmp0, u32tmp0, u32tmp1, u32tmp2); + "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa= 0x%x (After Set Ant Path)\n", + u32tmp1, u32tmp2, u16tmp0); BTC_TRACE(trace_buf); +#endif } @@ -1611,7 +2272,8 @@ u8 halbtc8723d2ant_action_algorithm(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], SCO + PAN(EDR)\n"); BTC_TRACE(trace_buf); - algorithm = BT_8723D_2ANT_COEX_ALGO_PANEDR; + algorithm = + BT_8723D_2ANT_COEX_ALGO_PANEDR; } } } else { @@ -1750,245 +2412,229 @@ void halbtc8723d2ant_action_coex_all_off(IN struct btc_coexist *btcoexist) halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - } -void halbtc8723d2ant_action_init_coex_dm(IN struct btc_coexist *btcoexist) +void halbtc8723d2ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) { - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* fw all off */ - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - /* sw all off */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - coex_sta->pop_event_cnt = 0; + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); } -void halbtc8723d2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +void halbtc8723d2ant_action_bt_hs(IN struct btc_coexist *btcoexist) { + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; - boolean wifi_connected = false; - boolean scan = false, link = false, roam = false; - boolean wifi_busy = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false, wifi_turbo = false; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif - if (link || roam || coex_sta->wifi_is_high_pri_task) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link/roam/hi-pri-task process + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); + wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres , 0); - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 8); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11); + wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2 , 0); - } else if (scan) { + bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres , 0); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi scan process + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); + bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2 , 0); - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 8); + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { - if (coex_sta->bt_create_connection) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 12); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11); + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); + halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; - } else if (wifi_connected) { + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 7); + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); + halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - if (wifi_busy) { + coex_dm->is_switch_to_1dot5_ant = false; - if ((bt_link_info->a2dp_exist) && (bt_link_info->acl_busy)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi no-link + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); + halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = true; halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); } - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - } -void halbtc8723d2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist) + +void halbtc8723d2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) { - u32 u32tmp, u32tmpb; - u8 u8tmpa; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + boolean wifi_connected = false; + boolean wifi_scan = false, wifi_link = false, wifi_roam = false; + boolean wifi_busy = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - if ((bt_link_info->a2dp_exist) && (bt_link_info->acl_busy)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); -} + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) + || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { -void halbtc8723d2ant_action_wifi_nonconnected(IN struct btc_coexist *btcoexist) -{ - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); - /* fw all off */ - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 8); - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 15); + else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 11); + } else if ((!wifi_connected) && (!wifi_scan)) { - /* sw all off */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi no-link + no-scan + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); -void halbtc8723d2ant_action_bt_idle(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else if (bt_link_info->pan_exist) { - boolean wifi_connected = false; - boolean scan = false, link = false, roam = false; - boolean wifi_busy = false; + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); + } else if (bt_link_info->a2dp_exist) { - bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); - bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + } else { + if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) + || (coex_sta->wifi_is_high_pri_task)) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); + else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + } - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18); + halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); +} - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link process + BT Idle!!\n"); - BTC_TRACE(trace_buf); +void halbtc8723d2ant_action_bt_relink(IN struct btc_coexist *btcoexist) +{ + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 7); + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18); + halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + coex_sta->bt_relink_downcount = 2; +} - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11); - } else if (wifi_connected) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT Idle!!\n"); - BTC_TRACE(trace_buf); +void halbtc8723d2ant_action_bt_idle(IN struct btc_coexist *btcoexist) +{ + boolean wifi_busy = false; - if (wifi_busy) { - if (!BTC_RSSI_HIGH(bt_rssi_state2)) - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 2); - else - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 0); - } else { - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 0); - } + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + if (!wifi_busy) { - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi no-link + BT Idle!!\n"); - BTC_TRACE(trace_buf); + halbtc8723d2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 0); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); + } else { /* if wl busy */ - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + if (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + halbtc8723d2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else { + + halbtc8723d2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 12); + } } halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - } + /* SCO only or SCO+PAN(HS) */ void halbtc8723d2ant_action_sco(IN struct btc_coexist *btcoexist) { static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; + u8 wifi_rssi_state, bt_rssi_state; static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false; + u32 wifi_bw = 1; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); @@ -2008,7 +2654,7 @@ void halbtc8723d2ant_action_sco(IN struct btc_coexist *btcoexist) if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { + BTC_RSSI_HIGH(bt_rssi_state)) { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); @@ -2025,18 +2671,11 @@ void halbtc8723d2ant_action_sco(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = false; - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 1); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8); } - - /* sw mechanism */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } @@ -2049,10 +2688,12 @@ void halbtc8723d2ant_action_hid(IN struct btc_coexist *btcoexist) static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; + boolean wifi_busy = false; + u32 wifi_bw = 1; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, &prewifi_rssi_state, 2, @@ -2070,7 +2711,7 @@ void halbtc8723d2ant_action_hid(IN struct btc_coexist *btcoexist) if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { + BTC_RSSI_HIGH(bt_rssi_state)) { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); @@ -2087,20 +2728,49 @@ void halbtc8723d2ant_action_hid(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = false; - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + /*for 4/18 hid */ + if (coex_sta->hid_busy_num >= 2) { + if (wifi_bw == 0) { /* if 11bg mode */ + + halbtc8723d2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 111); + } else { - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } + if (wifi_busy) { + halbtc8723d2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 111); + } else { + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 3); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); + } + } + } else { - /* sw mechanism */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 3); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); + } + } } + /* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist) { @@ -2111,10 +2781,21 @@ void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist) static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; + boolean wifi_busy = false, wifi_turbo = false; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, &prewifi_rssi_state, 2, @@ -2132,7 +2813,7 @@ void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist) if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { + BTC_RSSI_HIGH(bt_rssi_state)) { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); @@ -2145,7 +2826,7 @@ void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist) } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); coex_dm->is_switch_to_1dot5_ant = false; @@ -2153,11 +2834,11 @@ void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist) halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); if (wifi_busy) - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 1); else - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 16); } else { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); @@ -2165,23 +2846,40 @@ void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = true; - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + if ((coex_sta->bt_relink_downcount != 0) + && (wifi_busy)) { - if (wifi_busy) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 101); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 102); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); - } + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + + } else { + + if (wifi_turbo) + halbtc8723d2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + else + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 7); - /* sw mechanism */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); + if (wifi_busy) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 101); + else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 16); + /*halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 102);*/ + } + + } } + void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist) { static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; @@ -2191,10 +2889,21 @@ void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist) static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; + boolean wifi_busy = false, wifi_turbo = false; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, &prewifi_rssi_state, 2, @@ -2224,7 +2933,7 @@ void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist) #if 1 if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { + BTC_RSSI_HIGH(bt_rssi_state)) { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); @@ -2237,7 +2946,7 @@ void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist) } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); coex_dm->is_switch_to_1dot5_ant = false; @@ -2245,9 +2954,11 @@ void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist) halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); if (wifi_busy) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 3); else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 4); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 4); } else { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); @@ -2255,29 +2966,27 @@ void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = true; - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + if (wifi_turbo) + halbtc8723d2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + else + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 7); if (wifi_busy) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 103); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 103); else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 104); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 104); } #endif - - /* sw mechanism */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - -/* PAN(HS) only */ -void halbtc8723d2ant_action_pan_hs(IN struct btc_coexist *btcoexist) +void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) { static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; @@ -2286,9 +2995,11 @@ void halbtc8723d2ant_action_pan_hs(IN struct btc_coexist *btcoexist) static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; - + boolean wifi_busy = false; + u32 wifi_bw = 1; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, @@ -2305,8 +3016,9 @@ void halbtc8723d2ant_action_pan_hs(IN struct btc_coexist *btcoexist) bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2 , 0); + if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { + BTC_RSSI_HIGH(bt_rssi_state)) { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); @@ -2314,21 +3026,23 @@ void halbtc8723d2ant_action_pan_hs(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = false; halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); coex_dm->is_switch_to_1dot5_ant = false; - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + if (wifi_busy) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 1); + else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 16); } else { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); @@ -2336,21 +3050,51 @@ void halbtc8723d2ant_action_pan_hs(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = true; - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + if ((coex_sta->bt_relink_downcount != 0) + && (wifi_busy)) { - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + } else if (wifi_busy) { + if (coex_sta->hid_busy_num >= 2) { + halbtc8723d2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + if (wifi_bw == 0) /*11bg mode */ + halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + else + halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 109); + } else { + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 101); + } + } else { + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 1); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 16); + } + + } - /* sw mechanism */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); } -void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) +void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) { static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; @@ -2359,10 +3103,22 @@ void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; + boolean wifi_busy = false, wifi_turbo = false; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif + wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, &prewifi_rssi_state, 2, @@ -2380,7 +3136,7 @@ void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { + BTC_RSSI_HIGH(bt_rssi_state)) { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); @@ -2393,18 +3149,25 @@ void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); coex_dm->is_switch_to_1dot5_ant = false; halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - if (wifi_busy) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2); + if (wifi_busy) { + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 7); + else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 5); + } else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 6); } else { @@ -2413,26 +3176,33 @@ void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = true; - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - - if (wifi_busy) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 101); + if (wifi_turbo) + halbtc8723d2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 102); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 7); - } + if (wifi_busy) { + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 107); + else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 105); + } else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 106); - /* sw mechanism */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); + } } -void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) +/* PAN(EDR)+A2DP */ +void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) { static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; @@ -2441,10 +3211,22 @@ void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; + boolean wifi_busy = false, wifi_turbo = false; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif + wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, &prewifi_rssi_state, 2, @@ -2460,9 +3242,8 @@ void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2 , 0); - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { + BTC_RSSI_HIGH(bt_rssi_state)) { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); @@ -2470,12 +3251,11 @@ void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = false; halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); coex_dm->is_switch_to_1dot5_ant = false; @@ -2484,13 +3264,17 @@ void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) if (wifi_busy) { - if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 7); + if (((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) || + (!coex_sta->is_A2DP_3M)) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 7); else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 5); } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); - + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 6); } else { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); @@ -2498,32 +3282,35 @@ void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = true; - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + if (wifi_turbo) + halbtc8723d2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + else + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 7); if (wifi_busy) { - if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 107); + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 107); + else if (wifi_turbo) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 108); else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 105); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 105); } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 106); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 106); } - - /* sw mechanism */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - -/* PAN(EDR)+A2DP */ -void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) +void halbtc8723d2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) { static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; @@ -2531,9 +3318,12 @@ void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false; + u32 wifi_bw = 1; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); @@ -2551,8 +3341,9 @@ void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2 , 0); + if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { + BTC_RSSI_HIGH(bt_rssi_state)) { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); @@ -2560,26 +3351,23 @@ void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = false; halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); coex_dm->is_switch_to_1dot5_ant = false; halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 7); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); + if (wifi_busy) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 3); + else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 4); } else { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); @@ -2587,39 +3375,56 @@ void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = true; - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - - if (wifi_busy) { + if (coex_sta->hid_busy_num >= 2) { - if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 107); + halbtc8723d2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + if (wifi_bw == 0) /*11bg mode */ + halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 105); - } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 106); + halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 110); + } else { - } + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + if (wifi_busy) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 103); + else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 104); + } - /* sw mechanism */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); + } } -void halbtc8723d2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) + +/* HID+A2DP+PAN(EDR) */ +void halbtc8723d2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) { static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; + u8 wifi_rssi_state, bt_rssi_state; static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false; + u32 wifi_bw = 1; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); @@ -2639,7 +3444,7 @@ void halbtc8723d2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { + BTC_RSSI_HIGH(bt_rssi_state)) { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); @@ -2647,26 +3452,30 @@ void halbtc8723d2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = false; halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); coex_dm->is_switch_to_1dot5_ant = false; halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - if (wifi_busy) - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - else - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 4); - + if (wifi_busy) { + if (((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) || + (!coex_sta->is_A2DP_3M)) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 7); + else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 5); + } else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 6); } else { halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); @@ -2674,156 +3483,193 @@ void halbtc8723d2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) coex_dm->is_switch_to_1dot5_ant = true; - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - - if (wifi_busy) - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 103); - else + if (coex_sta->hid_busy_num >= 2) { + halbtc8723d2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + if (wifi_bw == 0) /*11bg mode */ + halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + else + halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 110); + } else { + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 104); + if (wifi_busy) { + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 107); + else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 105); + } else + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 106); + } } - - /* sw mechanism */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } -/* HID+A2DP+PAN(EDR) */ -void halbtc8723d2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); +void halbtc8723d2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); + halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + /* hw all off */ + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); +} - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); +void halbtc8723d2ant_action_wifi_linkscan_process(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - coex_dm->is_switch_to_1dot5_ant = false; + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18); + halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { + if (bt_link_info->pan_exist) { - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - coex_dm->is_switch_to_1dot5_ant = false; + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if (bt_link_info->a2dp_exist) { - if (wifi_busy) { + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); - if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 7); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); } else { - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; + halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 107); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 105); - } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 106); + halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); } - /* sw mechanism */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - - -void halbtc8723d2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) +void halbtc8723d2ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) { - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw mechanism all off */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + /* fw all off */ halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); -} -void halbtc8723d2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); +} - /* sw mechanism all off */ - halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); +void halbtc8723d2ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +{ + switch (coex_dm->cur_algorithm) { - /* hw all off */ - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + case BT_8723D_2ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_sco(btcoexist); + break; + case BT_8723D_2ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID.\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_hid(btcoexist); + break; + case BT_8723D_2ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_a2dp(btcoexist); + break; + case BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_a2dp_pan_hs(btcoexist); + break; + case BT_8723D_2ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_pan_edr(btcoexist); + break; + case BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_pan_edr_a2dp(btcoexist); + break; + case BT_8723D_2ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_pan_edr_hid(btcoexist); + break; + case BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_hid_a2dp_pan_edr( + btcoexist); + break; + case BT_8723D_2ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_hid_a2dp(btcoexist); + break; + case BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_bt_idle(btcoexist); + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_coex_all_off(btcoexist); + break; + } + + coex_dm->pre_algorithm = coex_dm->cur_algorithm; - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); } + void halbtc8723d2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) { - u8 algorithm = 0; - u32 num_of_wifi_link = 0; - u32 wifi_link_status = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean miracast_plus_bt = false; - boolean scan = false, link = false, roam = false, wifi_connected = false; - + u8 algorithm = 0; + u32 num_of_wifi_link = 0; + u32 wifi_link_status = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean miracast_plus_bt = false; + boolean scan = false, link = false, roam = false, + under_4way = false, + wifi_connected = false, wifi_under_5g = false, + bt_hs_on = false; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); + "[BTCoex], RunCoexistMechanism()===>\n"); BTC_TRACE(trace_buf); if (btcoexist->manual_control) { @@ -2842,22 +3688,36 @@ void halbtc8723d2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) if (coex_sta->under_ips) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (!coex_sta->run_time_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], return for run_time_state = false !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->freeze_coexrun_by_btinfo) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); BTC_TRACE(trace_buf); return; } if (coex_sta->bt_whck_test) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); + "[BTCoex], BT is under WHCK TEST!!!\n"); BTC_TRACE(trace_buf); - halbtc8723d2ant_action_bt_whck_test(btcoexist); + halbtc8723d2ant_action_bt_whql_test(btcoexist); return; } if (coex_sta->bt_disabled) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled!!!\n"); + "[BTCoex], BT is disabled!!!\n"); BTC_TRACE(trace_buf); halbtc8723d2ant_action_coex_all_off(btcoexist); return; @@ -2865,21 +3725,16 @@ void halbtc8723d2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) if (coex_sta->c2h_bt_inquiry_page) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); + "[BTCoex], BT is under inquiry/page scan !!\n"); BTC_TRACE(trace_buf); halbtc8723d2ant_action_bt_inquiry(btcoexist); return; } - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { + if (coex_sta->is_setupLink) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under Link Process !!\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_wifi_link_process(btcoexist); + "[BTCoex], BT is re-link !!!\n"); + halbtc8723d2ant_action_bt_relink(btcoexist); return; } @@ -2889,10 +3744,10 @@ void halbtc8723d2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) num_of_wifi_link = wifi_link_status >> 16; if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); + num_of_wifi_link, wifi_link_status); BTC_TRACE(trace_buf); if (bt_link_info->bt_link_exist) @@ -2902,7 +3757,20 @@ void halbtc8723d2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &miracast_plus_bt); - halbtc8723d2ant_action_wifi_multi_port(btcoexist); + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); + BTC_TRACE(trace_buf); + + halbtc8723d2ant_action_wifi_linkscan_process(btcoexist); + } else + halbtc8723d2ant_action_wifi_multi_port(btcoexist); return; } else { @@ -2911,144 +3779,131 @@ void halbtc8723d2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) &miracast_plus_bt); } + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is hs\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_bt_hs(btcoexist); + return; + } + + if ((BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) || + (BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, bt idle!!.\n"); + BTC_TRACE(trace_buf); + + halbtc8723d2ant_action_bt_idle(btcoexist); + return; + } algorithm = halbtc8723d2ant_action_algorithm(btcoexist); coex_dm->cur_algorithm = algorithm; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", - coex_dm->cur_algorithm); + coex_dm->cur_algorithm); BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); - if (!wifi_connected) { + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under Link Process !!\n"); + BTC_TRACE(trace_buf); + halbtc8723d2ant_action_wifi_linkscan_process(btcoexist); + } else if (wifi_connected) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, wifi non-connected!!.\n"); + "[BTCoex], Action 2-Ant, wifi connected!!.\n"); BTC_TRACE(trace_buf); - halbtc8723d2ant_action_wifi_nonconnected(btcoexist); + halbtc8723d2ant_action_wifi_connected(btcoexist); - } else if ((BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || (BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { + } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, bt idle!!.\n"); + "[BTCoex], Action 2-Ant, wifi not-connected!!.\n"); BTC_TRACE(trace_buf); + halbtc8723d2ant_action_wifi_not_connected(btcoexist); + } +} - halbtc8723d2ant_action_bt_idle(btcoexist); - } else { +void halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); - if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", - coex_dm->pre_algorithm, coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - } + halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); + halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - switch (coex_dm->cur_algorithm) { + /* sw all off */ + halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); - case BT_8723D_2ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_sco(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_hid(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_a2dp(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_pan_edr(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_pan_hs(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_pan_edr_hid(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_hid_a2dp(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_bt_idle(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_coex_all_off(btcoexist); - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } + coex_sta->pop_event_cnt = 0; + coex_sta->cnt_RemoteNameReq = 0; + coex_sta->cnt_ReInit = 0; + coex_sta->cnt_setupLink = 0; + coex_sta->cnt_IgnWlanAct = 0; + coex_sta->cnt_Page = 0; + + halbtc8723d2ant_query_bt_info(btcoexist); } + void halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist, IN boolean wifi_only) { - u8 u8tmp = 0; - u32 vendor; - u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0; + u8 u8tmp0 = 0, u8tmp1 = 0; + u32 vendor; + u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0; + u16 u16tmp1 = 0; + u8 i = 0; - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x67); - u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70); - u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 2Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + +#if BT_8723D_2ANT_COEX_DBG + u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, + 0x54); + u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948); + u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x73); + u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x67 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (Before Init HW config) **********\n", - u8tmp, u32tmp0, u32tmp1, u32tmp2); + "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before init_hw_config)\n", + u8tmp0, u16tmp1, u8tmp1); BTC_TRACE(trace_buf); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2Ant Init HW Config!!\n"); + "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x (Before init_hw_config)\n", + u32tmp1, u32tmp2); BTC_TRACE(trace_buf); +#endif + + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + coex_sta->gnt_error_cnt = 0; + coex_sta->bt_relink_downcount = 0; + + for (i = 0; i <= 9; i++) + coex_sta->bt_afh_map[i] = 0; #if 0 btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor); @@ -3065,7 +3920,8 @@ void halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist, /* default isolation = 15dB */ coex_sta->isolation_btween_wb = BT_8723D_2ANT_DEFAULT_ISOLATION; - halbtc8723d2ant_coex_switch_threshold(btcoexist, coex_sta->isolation_btween_wb); + halbtc8723d2ant_coex_switch_threshold(btcoexist, + coex_sta->isolation_btween_wb); btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, 0x1); /* enable TBTT nterrupt */ @@ -3083,53 +3939,57 @@ void halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist, /* Enable PTA (tx/rx signal form WiFi side) */ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); - halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, FALSE); + halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, true); + +#if 0 + /* check if WL firmware download ok */ + if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ONOFF, true); +#endif + + /* Enable counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, + 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ + + /* WLAN_Tx by GNT_WL 0x950[29] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0); + + halbtc8723d2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - /* check if WL firmware download ok */ - if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) - halbtc8723d2ant_post_onoffstate_to_bt(btcoexist, true); + halbtc8723d2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - /* Enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, - 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ + psd_scan->ant_det_is_ant_det_available = true; if (wifi_only) { coex_sta->concurrent_rx_mode_on = false; /* Path config */ - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true, - false); - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false, - false); + /* Set Antenna Path */ + halbtc8723d2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_WLANONLY_INIT); + + btcoexist->stop_coex_dm = true; } else { - /* coex_sta->concurrent_rx_mode_on = true; */ + /*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); + + coex_sta->concurrent_rx_mode_on = true; /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */ /* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */ btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0); /* Path config */ - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true, - false); - } - - /* WLAN_Tx by GNT_WL 0x950[29] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0); - - halbtc8723d2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x67); - u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70); - u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + halbtc8723d2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_COEX_INIT); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x67 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (After Init HW config) **********\n", - u8tmp, u32tmp0, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); + btcoexist->stop_coex_dm = false; + } - psd_scan->ant_det_is_ant_det_available = TRUE; } @@ -3188,7 +4048,33 @@ void halbtc8723d2ant_psd_show_antenna_detect_result(IN struct btc_coexist "\r\n============[Antenna Detection info] ============\n"); CL_PRINTF(cli_buf); - if (psd_scan->ant_det_result == 1) + if (psd_scan->ant_det_result == 12) { /* Get Ant Det from BT */ + + if (board_info->btdm_ant_num_by_ant_det == 1) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (%d~%d)", + "Ant Det Result", "1-Antenna", + BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT, + BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION); + else { + + if (psd_scan->ant_det_psd_scan_peak_val > + (BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION) + * 100) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (>%d)", + "Ant Det Result", "2-Antenna (Bad-Isolation)", + BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (%d~%d)", + "Ant Det Result", "2-Antenna (Good-Isolation)", + BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION + + psd_scan->ant_det_thres_offset, + BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); + } + + } else if (psd_scan->ant_det_result == 1) CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)", "Ant Det Result", "2-Antenna (Bad-Isolation)", BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); @@ -3260,10 +4146,20 @@ void halbtc8723d2ant_psd_show_antenna_detect_result(IN struct btc_coexist case 11: CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(BT is Disabled)"); + case 12: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(BT is available, result from BT"); break; } CL_PRINTF(cli_buf); + if (psd_scan->ant_det_result == 12) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB", + "PSD Scan Peak Value", + psd_scan->ant_det_psd_scan_peak_val / 100); + CL_PRINTF(cli_buf); + return; + } CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Ant Detect Total Count", psd_scan->ant_det_try_count); @@ -3335,6 +4231,9 @@ void halbtc8723d2ant_psd_showdata(IN struct btc_coexist *btcoexist) u32 delta_freq_per_point; u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2; + if (psd_scan->ant_det_result == 12) + return; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n\n============[PSD info] (%d)============\n", psd_scan->psd_gen_count); @@ -3389,44 +4288,61 @@ void halbtc8723d2ant_psd_showdata(IN struct btc_coexist *btcoexist) while (1) { do { - freq = ((psd_scan->real_cent_freq - 20) * 1000000 + m * + freq = ((psd_scan->real_cent_freq - 20) * + 1000000 + m * delta_freq_per_point); freq1 = freq / 1000000; freq2 = freq / 1000 - freq1 * 1000; if (i == 1) { if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.000", freq1); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Freq%6d.000", + freq1); else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.0%2d", freq1, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Freq%6d.0%2d", + freq1, freq2); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.%3d", freq1, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Freq%6d.%3d", + freq1, freq2); } else if ((i % 8 == 0) || (m == psd_scan->psd_stop_point)) { if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, "%6d.000\n", freq1); else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.0%2d\n", freq1, freq2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.0%2d\n", freq1, + freq2); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.%3d\n", freq1, freq2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.%3d\n", freq1, + freq2); } else { if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, "%6d.000", freq1); else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.0%2d", freq1, freq2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.0%2d", freq1, + freq2); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.%3d", freq1, freq2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.%3d", freq1, + freq2); } i++; @@ -3437,35 +4353,48 @@ void halbtc8723d2ant_psd_showdata(IN struct btc_coexist *btcoexist) do { - psd_rep1 = psd_scan->psd_report_max_hold[n] / 100; - psd_rep2 = psd_scan->psd_report_max_hold[n] - psd_rep1 * + psd_rep1 = psd_scan->psd_report_max_hold[n] / + 100; + psd_rep2 = psd_scan->psd_report_max_hold[n] - + psd_rep1 * 100; if (j == 1) { if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Val %7d.0%d", psd_rep1, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Val %7d.0%d", + psd_rep1, psd_rep2); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Val %7d.%d", psd_rep1, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Val %7d.%d", + psd_rep1, psd_rep2); } else if ((j % 8 == 0) || (n == psd_scan->psd_stop_point)) { if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, "%7d.0%d\n", psd_rep1, psd_rep2); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.%d\n", psd_rep1, psd_rep2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%7d.%d\n", psd_rep1, + psd_rep2); } else { if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.0%d", psd_rep1, psd_rep2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%7d.0%d", psd_rep1, + psd_rep2); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.%d", psd_rep1, psd_rep2); + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%7d.%d", psd_rep1, + psd_rep2); } j++; @@ -3488,49 +4417,45 @@ void halbtc8723d2ant_psd_showdata(IN struct btc_coexist *btcoexist) } +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif void halbtc8723d2ant_psd_maxholddata(IN struct btc_coexist *btcoexist, IN u32 gen_count) { - u32 i = 0, i_max = 0, val_max = 0; + u32 i = 0; + u32 loop_i_max = 0, loop_val_max = 0; if (gen_count == 1) { memcpy(psd_scan->psd_report_max_hold, psd_scan->psd_report, BT_8723D_2ANT_ANTDET_PSD_POINTS * sizeof(u32)); + } - psd_scan->psd_max_value_point = 0; - psd_scan->psd_max_value = 0; + for (i = psd_scan->psd_start_point; + i <= psd_scan->psd_stop_point; i++) { - } else { - for (i = psd_scan->psd_start_point; - i <= psd_scan->psd_stop_point; i++) { - if (psd_scan->psd_report[i] > - psd_scan->psd_report_max_hold[i]) - psd_scan->psd_report_max_hold[i] = - psd_scan->psd_report[i]; - - /* search Max Value */ - if (i == psd_scan->psd_start_point) { - i_max = i; - val_max = psd_scan->psd_report_max_hold[i]; - } else { - if (psd_scan->psd_report_max_hold[i] > - val_max) { - i_max = i; - val_max = psd_scan->psd_report_max_hold[i]; - } - } + /* update max-hold value at each freq point */ + if (psd_scan->psd_report[i] > psd_scan->psd_report_max_hold[i]) + psd_scan->psd_report_max_hold[i] = + psd_scan->psd_report[i]; + /* search the max value in this seep */ + if (psd_scan->psd_report[i] > loop_val_max) { + loop_val_max = psd_scan->psd_report[i]; + loop_i_max = i; } - - psd_scan->psd_max_value_point = i_max; - psd_scan->psd_max_value = val_max; - } + if (gen_count <= BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT) + psd_scan->psd_loop_max_value[gen_count - 1] = loop_val_max; } + +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif u32 halbtc8723d2ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) { /* reg 0x808[9:0]: FFT data x */ @@ -3562,7 +4487,9 @@ u32 halbtc8723d2ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) return psd_report; } - +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist, IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points, IN u32 avgnum, IN u32 loopcnt) @@ -3575,8 +4502,9 @@ boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist, u8 flag = 0; u32 tmp = 0, u32tmp1 = 0; u32 wifi_original_channel = 1; + u32 psd_sum = 0, avg_cnt = 0; + u32 i_max = 0, val_max = 0, val_max2 = 0; - psd_scan->is_psd_running = true; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n"); BTC_TRACE(trace_buf); @@ -3707,11 +4635,8 @@ boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist, break; case 3: psd_scan->psd_gen_count = 0; - for (j = 1; j <= loopcnt; j++) { - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0, 0xfffff, 0x320a0); */ - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); btcoexist->btc_get(btcoexist, @@ -3741,10 +4666,6 @@ boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist, halbtc8723d2ant_psd_getdata( btcoexist, i); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Point=%d, psd_raw_data = 0x%08x\n", - i, psd_report); - BTC_TRACE(trace_buf); if (psd_report == 0) tmp = 0; else @@ -3756,29 +4677,96 @@ boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist, n = i - psd_scan->psd_start_base; psd_scan->psd_report[n] = tmp; - - halbtc8723d2ant_psd_maxholddata( - btcoexist, j); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "Point=%d, psd_dB_data = %d\n", + i, psd_scan->psd_report[n]); + BTC_TRACE(trace_buf); i++; } - psd_scan->psd_gen_count = j; + halbtc8723d2ant_psd_maxholddata(btcoexist, j); + psd_scan->psd_gen_count = j; - /* - val = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - tmp = btcoexist->btc_read_4byte(btcoexist, 0x64); - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + /*Accumulate Max PSD value in this loop if the value > threshold */ + if (psd_scan->psd_loop_max_value[j - 1] >= + 4000) { + psd_sum = psd_sum + + psd_scan->psd_loop_max_value[j - + 1]; + avg_cnt++; + } BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "0x54 = 0x%08x, 0x67 = 0x%08x, 0x6c4 = 0x%08x\n", val, (tmp & 0xff000000) >> 24 ,u32tmp1); + "Loop=%d, Max_dB_data = %d\n", + j, psd_scan->psd_loop_max_value[j + - 1]); + BTC_TRACE(trace_buf); + + } + + if (loopcnt == BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT) { + + /* search the Max Value between each-freq-point-max-hold value of all sweep*/ + for (i = 1; + i <= BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT; + i++) { + + if (i == 1) { + i_max = i; + val_max = psd_scan->psd_loop_max_value[i + - 1]; + val_max2 = + psd_scan->psd_loop_max_value[i + - 1]; + } else if ( + psd_scan->psd_loop_max_value[i - + 1] > val_max) { + val_max2 = val_max; + i_max = i; + val_max = psd_scan->psd_loop_max_value[i + - 1]; + } else if ( + psd_scan->psd_loop_max_value[i - + 1] > val_max2) + val_max2 = + psd_scan->psd_loop_max_value[i + - 1]; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "i = %d, val_hold= %d, val_max = %d, val_max2 = %d\n", + i, psd_scan->psd_loop_max_value[i + - 1], + val_max, val_max2); + BTC_TRACE(trace_buf); - */ + } + + psd_scan->psd_max_value_point = i_max; + psd_scan->psd_max_value = val_max; + psd_scan->psd_max_value2 = val_max2; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "val_max = %d, val_max2 = %d\n", + psd_scan->psd_max_value, + psd_scan->psd_max_value2); + BTC_TRACE(trace_buf); } + if (avg_cnt != 0) { + psd_scan->psd_avg_value = (psd_sum / avg_cnt); + if ((psd_sum % avg_cnt) >= (avg_cnt / 2)) + psd_scan->psd_avg_value++; + } else + psd_scan->psd_avg_value = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "AvgLoop=%d, Avg_dB_data = %d\n", + avg_cnt, psd_scan->psd_avg_value); + BTC_TRACE(trace_buf); + flag = 100; break; case 99: /* error */ @@ -3824,10 +4812,6 @@ boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist, } while (!outloop); - - - psd_scan->is_psd_running = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n"); BTC_TRACE(trace_buf); @@ -3835,26 +4819,36 @@ boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist, } -void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 bt_tx_time, IN u32 bt_le_channel) +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif +boolean halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist + *btcoexist) { u32 i = 0; - u32 wlpsd_cent_freq = 2484, wlpsd_span = 2, wlpsd_sweep_count = 50; + u32 wlpsd_cent_freq = 2484, wlpsd_span = 2; s32 wlpsd_offset = -4; + u32 bt_tx_time, bt_le_channel; u8 bt_le_ch[13] = {3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 33}; u8 h2c_parameter[3] = {0}, u8tmpa, u8tmpb; u8 state = 0; - boolean outloop = false, bt_resp = false; + boolean outloop = false, bt_resp = false, ant_det_finish = false; u32 freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point, - u32tmp, u32tmp0, u32tmp1, u32tmp2; + u32tmp, u32tmp0, u32tmp1, u32tmp2 ; struct btc_board_info *board_info = &btcoexist->board_info; - board_info->btdm_ant_det_finish = false; memset(psd_scan->ant_det_peak_val, 0, 16 * sizeof(u8)); memset(psd_scan->ant_det_peak_freq, 0, 16 * sizeof(u8)); + psd_scan->ant_det_bt_tx_time = + BT_8723D_2ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */ + psd_scan->ant_det_bt_le_channel = BT_8723D_2ANT_ANTDET_BTTXCHANNEL; + + bt_tx_time = psd_scan->ant_det_bt_tx_time; + bt_le_channel = psd_scan->ant_det_bt_le_channel; + if (board_info->tfbga_package) /* for TFBGA */ psd_scan->ant_det_thres_offset = 5; else @@ -3886,7 +4880,7 @@ void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, break; } } - +#if 0 wlpsd_sweep_count = bt_tx_time * 238 / 100; /* bt_tx_time/0.42 */ wlpsd_sweep_count = wlpsd_sweep_count / 5; @@ -3894,7 +4888,7 @@ void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, if (wlpsd_sweep_count % 5 != 0) wlpsd_sweep_count = (wlpsd_sweep_count / 5 + 1) * 5; - +#endif BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n", bt_tx_time, bt_le_channel); @@ -3904,19 +4898,18 @@ void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, wlpsd_cent_freq, wlpsd_offset, wlpsd_span, - wlpsd_sweep_count); + BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT); BTC_TRACE(trace_buf); state = 1; break; case 1: /* stop coex DM & set antenna path */ /* Stop Coex DM */ - /* btcoexist->stop_coex_dm = true; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n"); - BTC_TRACE(trace_buf); */ + BTC_TRACE(trace_buf); /* Set TDMA off, */ halbtc8723d2ant_ps_tdma(btcoexist, FORCE_EXEC, @@ -3931,28 +4924,18 @@ void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n"); BTC_TRACE(trace_buf); - - - /* Set Antenna Path, both GNT_WL/GNT_BT = 1, and control by SW */ - /* Set Antenna path, switch WiFi to un-certain antenna port */ - - halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_WIFI_AT_AUX, true, - false); } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n"); BTC_TRACE(trace_buf); - - - /* Set Antenna Path, both GNT_WL/GNT_BT = 1, and control by SW */ - /* Set Antenna path, switch WiFi to un-certain antenna port */ - - halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_WIFI_AT_MAIN, true, - false); } + /* Set Antenna path, switch WiFi to un-certain antenna port */ + /* Set Antenna Path, both GNT_WL/GNT_BT = 1, and control by SW */ + halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_ANTENNA_DET); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n"); BTC_TRACE(trace_buf); @@ -3973,11 +4956,13 @@ void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, u32tmp = btcoexist->btc_read_2byte(btcoexist, 0x948); u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70); - u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg( + btcoexist, 0x38); + u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg( + btcoexist, 0x54); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x948 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (Before Ant Det) **********\n", + "[BTCoex], ********** 0x948 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (Before Ant Det)\n", u32tmp, u32tmp0, u32tmp1, u32tmp2); BTC_TRACE(trace_buf); @@ -3988,7 +4973,7 @@ void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, wlpsd_cent_freq, wlpsd_offset, wlpsd_span, BT_8723D_2ANT_ANTDET_PSD_POINTS, BT_8723D_2ANT_ANTDET_PSD_AVGNUM, 3)) { - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; board_info->btdm_ant_num_by_ant_det = 1; psd_scan->ant_det_result = 8; state = 99; @@ -3998,23 +4983,25 @@ void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, psd_scan->ant_det_pre_psdscan_peak_val = psd_scan->psd_max_value; - if (psd_scan->psd_max_value > + if (psd_scan->ant_det_pre_psdscan_peak_val > (BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND + psd_scan->ant_det_thres_offset) * 100) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n", - psd_scan->psd_max_value / 100, + psd_scan->ant_det_pre_psdscan_peak_val / + 100, BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND + psd_scan->ant_det_thres_offset); BTC_TRACE(trace_buf); - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; board_info->btdm_ant_num_by_ant_det = 1; psd_scan->ant_det_result = 5; state = 99; } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n", - psd_scan->psd_max_value / 100, + psd_scan->ant_det_pre_psdscan_peak_val / + 100, BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND + psd_scan->ant_det_thres_offset); BTC_TRACE(trace_buf); @@ -4026,21 +5013,36 @@ void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, btcoexist, (u8)(bt_tx_time & 0xff), (u8)(bt_le_channel & 0xff)); + /* Sync WL Rx PSD with BT Tx time because H2C->Mailbox delay */ + delay_ms(20); + if (!halbtc8723d2ant_psd_sweep_point(btcoexist, wlpsd_cent_freq, wlpsd_offset, wlpsd_span, BT_8723D_2ANT_ANTDET_PSD_POINTS, BT_8723D_2ANT_ANTDET_PSD_AVGNUM, - wlpsd_sweep_count)) { - board_info->btdm_ant_det_finish = false; + BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT)) { + ant_det_finish = false; board_info->btdm_ant_num_by_ant_det = 1; psd_scan->ant_det_result = 8; state = 99; break; } +#if 1 psd_scan->ant_det_psd_scan_peak_val = psd_scan->psd_max_value; +#endif +#if 0 + psd_scan->ant_det_psd_scan_peak_val = + ((psd_scan->psd_max_value - psd_scan->psd_avg_value) < + 800) ? + psd_scan->psd_max_value : (( + psd_scan->psd_max_value - + psd_scan->psd_max_value2 <= 300) ? + psd_scan->psd_avg_value : + psd_scan->psd_max_value2); +#endif psd_scan->ant_det_psd_scan_peak_freq = psd_scan->psd_max_value_point; state = 4; @@ -4054,8 +5056,9 @@ void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, psd_scan->psd_band_width / psd_scan->psd_point; - psd_rep1 = psd_scan->psd_max_value / 100; - psd_rep2 = psd_scan->psd_max_value - psd_rep1 * + psd_rep1 = psd_scan->ant_det_psd_scan_peak_val / 100; + psd_rep2 = psd_scan->ant_det_psd_scan_peak_val - + psd_rep1 * 100; freq = ((psd_scan->real_cent_freq - 20) * @@ -4106,44 +5109,50 @@ void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, psd_scan->ant_det_is_btreply_available = false; psd_scan->ant_det_result = 0; - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; board_info->btdm_ant_num_by_ant_det = 1; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n "); BTC_TRACE(trace_buf); - } else if (psd_scan->psd_max_value > + } else if (psd_scan->ant_det_psd_scan_peak_val > (BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION) * 100) { psd_scan->ant_det_result = 1; - board_info->btdm_ant_det_finish = true; + ant_det_finish = true; board_info->btdm_ant_num_by_ant_det = 2; - coex_sta->isolation_btween_wb = (u8)(85 - psd_scan->psd_max_value / 100) & 0xff; + coex_sta->isolation_btween_wb = (u8)(85 - + psd_scan->ant_det_psd_scan_peak_val / + 100) & 0xff; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n"); BTC_TRACE(trace_buf); - } else if (psd_scan->psd_max_value > + } else if (psd_scan->ant_det_psd_scan_peak_val > (BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION + psd_scan->ant_det_thres_offset) * 100) { psd_scan->ant_det_result = 2; - board_info->btdm_ant_det_finish = true; + ant_det_finish = true; board_info->btdm_ant_num_by_ant_det = 2; - coex_sta->isolation_btween_wb = (u8)(85 - psd_scan->psd_max_value / 100) & 0xff; + coex_sta->isolation_btween_wb = (u8)(85 - + psd_scan->ant_det_psd_scan_peak_val / + 100) & 0xff; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n"); BTC_TRACE(trace_buf); - } else if (psd_scan->psd_max_value > + } else if (psd_scan->ant_det_psd_scan_peak_val > (BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT) * 100) { psd_scan->ant_det_result = 3; - board_info->btdm_ant_det_finish = true; + ant_det_finish = true; board_info->btdm_ant_num_by_ant_det = 1; - coex_sta->isolation_btween_wb = (u8)(85 - psd_scan->psd_max_value / 100) & 0xff; + coex_sta->isolation_btween_wb = (u8)(85 - + psd_scan->ant_det_psd_scan_peak_val / + 100) & 0xff; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n"); BTC_TRACE(trace_buf); } else { psd_scan->ant_det_result = 4; - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; board_info->btdm_ant_num_by_ant_det = 1; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n"); @@ -4170,26 +5179,18 @@ void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, /* Set Antenna Path, GNT_WL/GNT_BT control by PTA */ /* Set Antenna path, switch WiFi to certain antenna port */ halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_WIFI_AT_MAIN, false, - false); + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8723D_2ANT_PHASE_2G_RUNTIME); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!"); BTC_TRACE(trace_buf); - /* Resume Coex DM */ - /* btcoexist->stop_coex_dm = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); - BTC_TRACE(trace_buf); */ - /* stimulate coex running */ - /* - halbtc8723d2ant_run_coexist_mechanism( - btcoexist); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); - BTC_TRACE(trace_buf); */ + "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); + BTC_TRACE(trace_buf); outloop = true; break; @@ -4197,78 +5198,54 @@ void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, } while (!outloop); - + return ant_det_finish; } -void halbtc8723d2ant_psd_antenna_detection_check(IN struct btc_coexist +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif +boolean halbtc8723d2ant_psd_antenna_detection_check(IN struct btc_coexist *btcoexist) { static u32 ant_det_count = 0, ant_det_fail_count = 0; struct btc_board_info *board_info = &btcoexist->board_info; - boolean scan, roam; + boolean scan, roam, ant_det_finish = false; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - /* psd_scan->ant_det_bt_tx_time = 20; */ - psd_scan->ant_det_bt_tx_time = - BT_8723D_2ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */ - psd_scan->ant_det_bt_le_channel = BT_8723D_2ANT_ANTDET_BTTXCHANNEL; - ant_det_count++; psd_scan->ant_det_try_count = ant_det_count; if (scan || roam) { - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; psd_scan->ant_det_result = 6; } else if (coex_sta->bt_disabled) { - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; psd_scan->ant_det_result = 11; } else if (coex_sta->num_of_profile >= 1) { - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; psd_scan->ant_det_result = 7; } else if ( !psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */ - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; psd_scan->ant_det_result = 9; } else if (coex_sta->c2h_bt_inquiry_page) { - board_info->btdm_ant_det_finish = false; + ant_det_finish = false; psd_scan->ant_det_result = 10; } else { - btcoexist->stop_coex_dm = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_psd_antenna_detection(btcoexist, - psd_scan->ant_det_bt_tx_time, - psd_scan->ant_det_bt_le_channel); + ant_det_finish = halbtc8723d2ant_psd_antenna_detection( + btcoexist); delay_ms(psd_scan->ant_det_bt_tx_time); - - btcoexist->stop_coex_dm = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); - BTC_TRACE(trace_buf); - - /* stimulate coex running */ - - halbtc8723d2ant_run_coexist_mechanism( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); - BTC_TRACE(trace_buf); } - if (!board_info->btdm_ant_det_finish) + if (!ant_det_finish) ant_det_fail_count++; psd_scan->ant_det_fail_count = ant_det_fail_count; @@ -4277,9 +5254,11 @@ void halbtc8723d2ant_psd_antenna_detection_check(IN struct btc_coexist "xxxxxxxxxxxxxxxx AntennaDetect(), result = %d, fail_count = %d, finish = %s\n", psd_scan->ant_det_result, psd_scan->ant_det_fail_count, - board_info->btdm_ant_det_finish == TRUE ? "Yes" : "No"); + ant_det_finish == true ? "Yes" : "No"); BTC_TRACE(trace_buf); + return ant_det_finish; + } @@ -4308,26 +5287,12 @@ void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist) btcoexist->stop_coex_dm = true; - psd_scan->ant_det_is_ant_det_available = FALSE; + psd_scan->ant_det_is_ant_det_available = false; /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */ u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - /* set Path control owner to WiFi */ - halbtc8723d2ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_2ANT_PCO_WLSIDE); - - /* set GNT_BT to high */ - halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to high */ - halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); /* Local setting bit define */ /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ @@ -4344,10 +5309,12 @@ void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist) /* set to S1 */ board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; u8tmp = 4; + value = 1; } else if (board_info->single_ant_path == 1) { /* set to S0 */ board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; u8tmp = 5; + value = 0; } BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -4355,6 +5322,12 @@ void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist) board_info->single_ant_path , board_info->btdm_ant_pos); BTC_TRACE(trace_buf); + /* Set Antenna Path to BT side */ + halbtc8723d2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_1ANT_PHASE_COEX_POWERON); + /* Write Single Antenna Position to Registry to tell BT for 872db. This line can be removed since BT EFuse also add "single antenna position" in EFuse for 8723d*/ btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, @@ -4369,7 +5342,7 @@ void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist) btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, FALSE); + halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, true); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n", @@ -4378,7 +5351,8 @@ void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0x948 (Power-On) = 0x%x / 0x%x**********\n", - btcoexist->btc_read_4byte(btcoexist, 0x70), btcoexist->btc_read_2byte(btcoexist, 0x948)); + btcoexist->btc_read_4byte(btcoexist, 0x70), + btcoexist->btc_read_2byte(btcoexist, 0x948)); BTC_TRACE(trace_buf); } @@ -4419,19 +5393,13 @@ void ex_halbtc8723d2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) void ex_halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist, IN boolean wifi_only) { - btcoexist->stop_coex_dm = false; halbtc8723d2ant_init_hw_config(btcoexist, wifi_only); } void ex_halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - halbtc8723d2ant_action_init_coex_dm(btcoexist); + halbtc8723d2ant_init_coex_dm(btcoexist); } void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist) @@ -4439,12 +5407,14 @@ void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist) struct btc_board_info *board_info = &btcoexist->board_info; struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u8 u8tmp[4], i, ps_tdma_case = 0; u32 u32tmp[4]; u16 u16tmp[4]; - u32 fa_of_dm, fa_cck; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck, bt_coex_ver = 0; u32 fw_ver = 0, bt_patch_ver = 0; static u8 pop_report_in_10s = 0; + u32 phyver = 0; + boolean lte_coex_on = false; CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); @@ -4469,28 +5439,64 @@ void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist) CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s (retry=%d/fail=%d/result=%d)", "Ant PG Num/ Mech(Ant_Det)/ Pos", - board_info->pg_ant_num, board_info->btdm_ant_num_by_ant_det, + board_info->pg_ant_num, + board_info->btdm_ant_num_by_ant_det, (board_info->btdm_ant_pos == 1 ? "S1" : "S0"), - psd_scan->ant_det_try_count, psd_scan->ant_det_fail_count, + psd_scan->ant_det_try_count, + psd_scan->ant_det_fail_count, psd_scan->ant_det_result); CL_PRINTF(cli_buf); if (board_info->btdm_ant_det_finish) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); + + if (psd_scan->ant_det_result != 12) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", + "Ant Det PSD Value", + psd_scan->ant_det_peak_val); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d", + "Ant Det PSD Value", + psd_scan->ant_det_psd_scan_peak_val + / 100); CL_PRINTF(cli_buf); } } + if (board_info->ant_det_result_five_complete) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d", + "AntDet(Registry) Num/PSD Value", + board_info->btdm_ant_num_by_ant_det, + (board_info->antdetval & 0x7f)); + CL_PRINTF(cli_buf); + } + - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + + bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8723d_2ant, glcoex_ver_8723d_2ant, + glcoex_ver_btdesired_8723d_2ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8723d_2ant ? + "Match" : "Mis-Match")))); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c", - "Version Coex/ Fw/ Patch/ Cut", - glcoex_ver_date_8723d_2ant, glcoex_ver_8723d_2ant, fw_ver, - bt_patch_ver, bt_patch_ver, coex_sta->cut_version + 65); + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", @@ -4517,7 +5523,8 @@ void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist) CL_PRINTF(cli_buf); pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", "BT [status/ rssi/ retryCnt/ popCnt]", ((coex_sta->bt_disabled) ? ("disabled") : (( coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") @@ -4535,26 +5542,113 @@ void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist) } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d / %d / %d / %d / %d / %d", - "SCO/HID/PAN/A2DP/NameReq/WHQL", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist, - coex_sta->c2h_bt_remote_name_req, - coex_sta->bt_whck_test); + if (coex_sta->num_of_profile != 0) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s%s%s%s%s", + "Profiles", + ((bt_link_info->a2dp_exist) ? "A2DP," : ""), + ((bt_link_info->sco_exist) ? "SCO," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : + "HID(2/18),") : ""), + ((bt_link_info->pan_exist) ? "PAN," : ""), + ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = None", + "Profiles"); + + CL_PRINTF(cli_buf); + + + if (bt_link_info->a2dp_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", + "A2DP Rate/Bitpool/Auto_Slot", + ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), + coex_sta->a2dp_bit_pool, + ((coex_sta->is_autoslot) ? "On" : "Off") + ); + CL_PRINTF(cli_buf); + } + + if (bt_link_info->hid_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "HID PairNum/Forbid_Slot", + coex_sta->hid_pair_cnt, + coex_sta->forbidden_slot + ); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ 0x%x/ 0x%x", + "Role/IgnWlanAct/Feature/BLEScan", + ((bt_link_info->slave_role) ? "Slave" : "Master"), + ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), + coex_sta->bt_coex_supported_feature, + coex_sta->bt_ble_scan_type); CL_PRINTF(cli_buf); - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s / %d", - "Role/A2DP Rate/Bitpool", - ((bt_link_info->slave_role) ? "Slave" : "Master"), - (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool); + if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%08x/ 0x%08x/ 0x%08x", + "BLEScan Intv-Win TV/Init/Ble", + (coex_sta->bt_ble_scan_type & 0x1 ? + coex_sta->bt_ble_scan_para[0] : 0x0), + (coex_sta->bt_ble_scan_type & 0x2 ? + coex_sta->bt_ble_scan_para[1] : 0x0), + (coex_sta->bt_ble_scan_type & 0x4 ? + coex_sta->bt_ble_scan_para[2] : 0x0)); + + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "ReInit/ReLink/IgnWlact/Page/NameReq", + coex_sta->cnt_ReInit, + coex_sta->cnt_setupLink, + coex_sta->cnt_IgnWlanAct, + coex_sta->cnt_Page, + coex_sta->cnt_RemoteNameReq + ); + CL_PRINTF(cli_buf); + + halbtc8723d2ant_read_score_board(btcoexist, &u16tmp[0]); + + if ((coex_sta->bt_reg_vendor_ae == 0xffff) || + (coex_sta->bt_reg_vendor_ac == 0xffff)) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", + ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), + coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); CL_PRINTF(cli_buf); + if (coex_sta->num_of_profile > 0) { + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + "AFH MAP", + coex_sta->bt_afh_map[0], + coex_sta->bt_afh_map[1], + coex_sta->bt_afh_map[2], + coex_sta->bt_afh_map[3], + coex_sta->bt_afh_map[4], + coex_sta->bt_afh_map[5], + coex_sta->bt_afh_map[6], + coex_sta->bt_afh_map[7], + coex_sta->bt_afh_map[8], + coex_sta->bt_afh_map[9] + ); + CL_PRINTF(cli_buf); + } + for (i = 0; i < BT_INFO_SRC_8723D_2ANT_MAX; i++) { if (coex_sta->bt_info_c2h_cnt[i]) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)", glbt_info_src_8723d_2ant[i], coex_sta->bt_info_c2h[i][0], coex_sta->bt_info_c2h[i][1], @@ -4574,191 +5668,226 @@ void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist) "============[mechanism] (before Manual)============"); else CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanism]============"); + "============[Mechanism]============"); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ 0x%x/ 0x%x ", - "LowP-RA/ DecWLPwr/ DecBTPwr", - (coex_dm->cur_low_penalty_ra ? "On" : "Off"), - coex_dm->cur_fw_dac_swing_lvl, - coex_dm->cur_bt_dec_pwr_lvl); - CL_PRINTF(cli_buf); ps_tdma_case = coex_dm->cur_ps_tdma; CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s, %s)", - "PS TDMA", + "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, %s)", + "TDMA", coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "On" : "Off"), + (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"), (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant")); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "WL/BT Coex Table Type", - coex_sta->coex_table_type); - CL_PRINTF(cli_buf); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2]); + "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", + "Table/0x6c0/0x6c4/0x6c8", + coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); CL_PRINTF(cli_buf); u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x778/0x6cc/IgnWlanAct", - u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act); + "\r\n %-35s = 0x%x/ 0x%x", + "0x778/0x6cc", + u8tmp[0], u32tmp[0]); CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", + "AntDiv/ ForceLPS", + ((board_info->ant_div_cfg) ? "On" : "Off"), + ((coex_sta->force_lps_on) ? "On" : "Off")); + CL_PRINTF(cli_buf); - u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0xa0); - u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0xa4); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "LTE Coex Table W_L/B_L", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + "WL_DACSwing/ BT_Dec_Pwr", coex_dm->cur_fw_dac_swing_lvl, + coex_dm->cur_bt_dec_pwr_lvl); CL_PRINTF(cli_buf); + u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? true : false; + + if (lte_coex_on) { - u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0xa8); - u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0xac); - u32tmp[2] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0xb0); - u32tmp[3] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0xb4); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "LTE Break Table W_L/B_L/L_W/L_B", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, - u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); - CL_PRINTF(cli_buf); + u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, + 0xa0); + u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, + 0xa4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "LTE Coex Table W_L/B_L", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, + 0xa8); + u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, + 0xac); + u32tmp[2] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, + 0xb0); + u32tmp[3] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, + 0xb4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "LTE Break Table W_L/B_L/L_W/L_B", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, + u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); + CL_PRINTF(cli_buf); + + } /* Hw setting */ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); CL_PRINTF(cli_buf); + /* + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); + u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", + "0x430/0x434/0x42a/0x456", + u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + */ + u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", + "LTE Coex/Path Owner", + ((lte_coex_on) ? "On" : "Off") , + ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); CL_PRINTF(cli_buf); + if (lte_coex_on) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %d/ %d", + "LTE 3Wire/OPMode/UART/UARTMode", + (int)((u32tmp[0] & BIT(6)) >> 6), + (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), + (int)((u32tmp[0] & BIT(3)) >> 3), + (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); + CL_PRINTF(cli_buf); - u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "LTE_Busy/UART_Busy", + (int)((u32tmp[1] & BIT(1)) >> 1), (int)(u32tmp[1] & BIT(0))); + CL_PRINTF(cli_buf); + } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s", - "LTE CoexOn/Path Ctrl Owner", - (int)((u32tmp[0] & BIT(7)) >> 7), ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); - CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", + ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), + ((u8tmp[0] & BIT(3)) ? "On" : "Off"), + coex_sta->gnt_error_cnt); + CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "LTE 3Wire/OPMode/UART/UARTMode", - (int)((u32tmp[0] & BIT(6)) >> 6), (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), - (int)((u32tmp[0] & BIT(3)) >> 3), - (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "GNT_WL/GNT_BT", + (int)((u32tmp[1] & BIT(2)) >> 2), + (int)((u32tmp[1] & BIT(3)) >> 3)); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s", - "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg", - (int)((u32tmp[0] & BIT(12)) >> 12), (int)((u32tmp[0] & BIT(14)) >> 14), - ((u8tmp[0] & BIT(3)) ? "On" : "Off")); + u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x948); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x948/0x67[7]", + u16tmp[0], (int)((u8tmp[0] & BIT(7)) >> 7)); CL_PRINTF(cli_buf); - u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x964); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x864); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xab7); + u8tmp[3] = btcoexist->btc_read_1byte(btcoexist, 0xa01); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "GNT_WL/GNT_BT/LTE_Busy/UART_Busy", - (int)((u32tmp[0] & BIT(2)) >> 2), (int)((u32tmp[0] & BIT(3)) >> 3), - (int)((u32tmp[0] & BIT(1)) >> 1), (int)(u32tmp[0] & BIT(0))); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "0x964[1]/0x864[0]/0xab7[5]/0xa01[7]", + (int)((u8tmp[0] & BIT(1)) >> 1), (int)((u8tmp[1] & BIT(0))), + (int)((u8tmp[2] & BIT(3)) >> 3), + (int)((u8tmp[3] & BIT(7)) >> 7)); CL_PRINTF(cli_buf); u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x45e); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x4c6[4]/0x40[5] (WL/BT PTA)", - (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5)); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x4c6[4]/0x40[5]/0x45e[3](TxRetry)", + (int)((u8tmp[0] & BIT(4)) >> 4), + (int)((u8tmp[1] & BIT(5)) >> 5), + (int)((u8tmp[2] & BIT(3)) >> 3)); CL_PRINTF(cli_buf); u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s", - "0x550(bcn ctrl)/0x522/4-RxAGC", - u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off"); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x948); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x948/ 0x67[7]/ 0xc50[7:0]", - u32tmp[0], - ((u8tmp[0] & 0x80) >> 7), u32tmp[1] & 0xff); + "0x550/0x522/4-RxAGC", + u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off"); CL_PRINTF(cli_buf); + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8); - u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c); - - fa_of_dm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000) - >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) + - ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] & 0xffff); - fa_cck = (u8tmp[0] << 8) + u8tmp[1]; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "OFDM-CCA/OFDM-FA/CCK-FA", - u32tmp[0] & 0xffff, fa_of_dm, fa_cck); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); CL_PRINTF(cli_buf); +#if 1 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-Agg", + "CRC_OK CCK/11g/11n/11n-agg", coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg); + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-Agg", + "CRC_Err CCK/11g/11n/11n-agg", coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg); + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); CL_PRINTF(cli_buf); +#endif - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "WlHiPri/ Locking/ Locked/ Noisy", + (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + (coex_sta->cck_lock ? "Yes" : "No"), + (coex_sta->cck_ever_lock ? "Yes" : "No"), + coex_sta->wl_noisy_level); CL_PRINTF(cli_buf); - halbtc8723d2ant_read_score_board(btcoexist, &u16tmp[0]); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx, + (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : "")); + CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x", - "ScoreBoard[14:0] (from BT)", u16tmp[0]); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : ( + coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); CL_PRINTF(cli_buf); btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); @@ -4776,16 +5905,34 @@ void ex_halbtc8723d2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) BTC_TRACE(trace_buf); coex_sta->under_ips = true; coex_sta->under_lps = false; - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false, - true); + + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE | + BT_8723D_2ANT_SCOREBOARD_ONOFF | + BT_8723D_2ANT_SCOREBOARD_SCAN | + BT_8723D_2ANT_SCOREBOARD_UNDERTEST, + false); + + halbtc8723d2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_WLAN_OFF); + halbtc8723d2ant_action_coex_all_off(btcoexist); } else if (BTC_IPS_LEAVE == type) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], IPS LEAVE notify\n"); BTC_TRACE(trace_buf); coex_sta->under_ips = false; +#if 0 + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE, true); + + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ONOFF, true); +#endif halbtc8723d2ant_init_hw_config(btcoexist, false); - halbtc8723d2ant_action_init_coex_dm(btcoexist); + halbtc8723d2ant_init_coex_dm(btcoexist); halbtc8723d2ant_query_bt_info(btcoexist); } } @@ -4801,11 +5948,27 @@ void ex_halbtc8723d2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) BTC_TRACE(trace_buf); coex_sta->under_lps = true; coex_sta->under_ips = false; + + if (coex_sta->force_lps_on == true) { /* LPS No-32K */ + /* Write WL "Active" in Score-board for PS-TDMA */ + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE, true); + + } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ + /* Write WL "Non-Active" in Score-board for Native-PS */ + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE, false); + } + + } else if (BTC_LPS_DISABLE == type) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], LPS DISABLE notify\n"); BTC_TRACE(trace_buf); coex_sta->under_lps = false; + + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE, true); } } @@ -4824,7 +5987,8 @@ void ex_halbtc8723d2ant_scan_notify(IN struct btc_coexist *btcoexist, btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); - halbtc8723d2ant_query_bt_info(btcoexist); /* this can't be removed for RF off_on event, or BT would dis-connect */ + /* this can't be removed for RF off_on event, or BT would dis-connect */ + halbtc8723d2ant_query_bt_info(btcoexist); if (BTC_SCAN_START == type) { @@ -4835,8 +5999,16 @@ void ex_halbtc8723d2ant_scan_notify(IN struct btc_coexist *btcoexist, "[BTCoex], SCAN START notify\n"); BTC_TRACE(trace_buf); - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false, - false); + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE | + BT_8723D_2ANT_SCOREBOARD_SCAN | + BT_8723D_2ANT_SCOREBOARD_ONOFF, + true); + + halbtc8723d2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_2G_RUNTIME); halbtc8723d2ant_run_coexist_mechanism(btcoexist); @@ -4848,9 +6020,13 @@ void ex_halbtc8723d2ant_scan_notify(IN struct btc_coexist *btcoexist, &coex_sta->scan_ap_num); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", coex_sta->scan_ap_num); + "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", + coex_sta->scan_ap_num); BTC_TRACE(trace_buf); + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_SCAN, false); + halbtc8723d2ant_run_coexist_mechanism(btcoexist); } @@ -4860,8 +6036,7 @@ void ex_halbtc8723d2ant_connect_notify(IN struct btc_coexist *btcoexist, IN u8 type) { if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) + btcoexist->stop_coex_dm) return; if (BTC_ASSOCIATE_START == type) { @@ -4872,16 +6047,28 @@ void ex_halbtc8723d2ant_connect_notify(IN struct btc_coexist *btcoexist, "[BTCoex], CONNECT START notify\n"); BTC_TRACE(trace_buf); - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false, - false); + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE | + BT_8723D_2ANT_SCOREBOARD_SCAN | + BT_8723D_2ANT_SCOREBOARD_ONOFF, + true); + + halbtc8723d2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_2G_RUNTIME); halbtc8723d2ant_run_coexist_mechanism(btcoexist); + /* To keep TDMA case during connect process, + to avoid changed by Btinfo and runcoexmechanism */ + coex_sta->freeze_coexrun_by_btinfo = true; coex_dm->arp_cnt = 0; } else if (BTC_ASSOCIATE_FINISH == type) { coex_sta->wifi_is_high_pri_task = false; + coex_sta->freeze_coexrun_by_btinfo = false; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], CONNECT FINISH notify\n"); @@ -4901,19 +6088,24 @@ void ex_halbtc8723d2ant_media_status_notify(IN struct btc_coexist *btcoexist, boolean wifi_under_b_mode = false; if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) + btcoexist->stop_coex_dm) return; if (BTC_MEDIA_CONNECT == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], MEDIA connect notify\n"); BTC_TRACE(trace_buf); - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false, - false); + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE | + BT_8723D_2ANT_SCOREBOARD_ONOFF, + true); - /* psd_scan->ant_det_is_ant_det_available = TRUE; */ + halbtc8723d2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_2G_RUNTIME); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &wifi_under_b_mode); @@ -4939,6 +6131,9 @@ void ex_halbtc8723d2ant_media_status_notify(IN struct btc_coexist *btcoexist, btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE, false); } @@ -4951,8 +6146,7 @@ void ex_halbtc8723d2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, boolean under_4way = false; if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) + btcoexist->stop_coex_dm) return; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, @@ -4971,36 +6165,44 @@ void ex_halbtc8723d2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, coex_dm->arp_cnt++; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify -cnt = %d\n", coex_dm->arp_cnt); + "[BTCoex], specific Packet ARP notify -cnt = %d\n", + coex_dm->arp_cnt); BTC_TRACE(trace_buf); } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", type); + "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", + type); BTC_TRACE(trace_buf); coex_sta->wifi_is_high_pri_task = true; coex_sta->specific_pkt_period_cnt = 2; } - if (coex_sta->wifi_is_high_pri_task) + if (coex_sta->wifi_is_high_pri_task) { + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE, true); halbtc8723d2ant_run_coexist_mechanism(btcoexist); + } } void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist, IN u8 *tmp_buf, IN u8 length) { - u8 bt_info = 0; u8 i, rsp_source = 0; - boolean bt_busy = false, limited_dig = false; - boolean wifi_connected = false; + boolean wifi_connected = false; + boolean wifi_scan = false, wifi_link = false, wifi_roam = false, + wifi_busy = false; + static boolean is_scoreboard_scan = false; - coex_sta->c2h_bt_info_req_sent = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + if (psd_scan->is_AntDet_running == true) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt_info_notify return for AntDet is running\n"); + BTC_TRACE(trace_buf); + return; + } rsp_source = tmp_buf[0] & 0xf; if (rsp_source >= BT_INFO_SRC_8723D_2ANT_MAX) @@ -5008,13 +6210,12 @@ void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist, coex_sta->bt_info_c2h_cnt[rsp_source]++; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, + "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, length); BTC_TRACE(trace_buf); + for (i = 0; i < length; i++) { coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; if (i == length - 1) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", @@ -5027,51 +6228,110 @@ void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist, } } + coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; + coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; + coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; + if (BT_INFO_SRC_8723D_2ANT_WIFI_FW != rsp_source) { /* if 0xff, it means BT is under WHCK test */ - if (bt_info == 0xff) - coex_sta->bt_whck_test = true; - else - coex_sta->bt_whck_test = false; + coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true : + false); + + coex_sta->bt_create_connection = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true : + false); + + /* unit: %, value-100 to translate to unit: dBm */ + coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + + 10; + + coex_sta->c2h_bt_remote_name_req = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true : + false); + + coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & + 0x10) ? true : false); - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; + coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & + 0x9) ? true : false); + + coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? + true : false); + + coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & + BT_INFO_8723D_2ANT_B_INQ_PAGE) ? true : false); + + coex_sta->a2dp_bit_pool = ((( + coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? + coex_sta->bt_info_c2h[rsp_source][6] : 0); + + coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & + 0xf; + + coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; + + coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; + + coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; + + coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; if (coex_sta->bt_retry_cnt >= 1) coex_sta->pop_event_cnt++; - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x80) - coex_sta->bt_create_connection = true; - else - coex_sta->bt_create_connection = false; - - /* unit: %, value-100 to translate to unit: dBm */ - coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; + if (coex_sta->c2h_bt_remote_name_req) + coex_sta->cnt_RemoteNameReq++; - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_remote_name_req = true; - else - coex_sta->c2h_bt_remote_name_req = false; + if (coex_sta->bt_info_ext & BIT(1)) + coex_sta->cnt_ReInit++; - if ((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) { - coex_sta->a2dp_bit_pool = - coex_sta->bt_info_c2h[rsp_source][6]; + if (coex_sta->bt_info_ext & BIT(2)) { + coex_sta->cnt_setupLink++; + coex_sta->is_setupLink = true; } else - coex_sta->a2dp_bit_pool = 0; + coex_sta->is_setupLink = false; - if (coex_sta->bt_info_c2h[rsp_source][1] & 0x9) - coex_sta->acl_busy = true; - else - coex_sta->acl_busy = false; + if (coex_sta->bt_info_ext & BIT(3)) + coex_sta->cnt_IgnWlanAct++; + + if (coex_sta->bt_create_connection) { + coex_sta->cnt_Page++; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, + &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || + (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; + is_scoreboard_scan = true; + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_SCAN, true); + + } else + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_SCAN, false); + + } else { + if (is_scoreboard_scan) { + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_SCAN, false); + is_scoreboard_scan = false; + } + } /* Here we need to resend some wifi info to BT */ /* because bt is reset and loss of the info. */ - if ((!btcoexist->manual_control) && (!btcoexist->stop_coex_dm)) { + if ((!btcoexist->manual_control) && + (!btcoexist->stop_coex_dm)) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); /* Re-Init */ if ((coex_sta->bt_info_ext & BIT(1))) { @@ -5079,132 +6339,55 @@ void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist, "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); BTC_TRACE(trace_buf); if (wifi_connected) - ex_halbtc8723d2ant_media_status_notify( + halbtc8723d2ant_update_wifi_channel_info( btcoexist, BTC_MEDIA_CONNECT); else - ex_halbtc8723d2ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); + halbtc8723d2ant_update_wifi_channel_info( + btcoexist, + BTC_MEDIA_DISCONNECT); } - /* If Ignore_WLanAct && not SetUp_Link */ - if ((coex_sta->bt_info_ext & BIT(3)) && (!(coex_sta->bt_info_ext & BIT(2)))) { + /* If Ignore_WLanAct && not SetUp_Link or Role_Switch */ + if ((coex_sta->bt_info_ext & BIT(3)) && + (!(coex_sta->bt_info_ext & BIT(2))) && + (!(coex_sta->bt_info_ext & BIT(6)))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); BTC_TRACE(trace_buf); halbtc8723d2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, false); + } else { + if (coex_sta->bt_info_ext & BIT(2)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ignore Wlan active because Re-link!!\n"); + BTC_TRACE(trace_buf); + } else if (coex_sta->bt_info_ext & BIT(6)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ignore Wlan active because Role-Switch!!\n"); + BTC_TRACE(trace_buf); + } } } - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8723D_2ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - } - - coex_sta->num_of_profile = 0; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8723D_2ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8723D_2ANT_B_FTP) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = false; - - if (bt_info & BT_INFO_8723D_2ANT_B_A2DP) { - coex_sta->a2dp_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = false; - - if (bt_info & BT_INFO_8723D_2ANT_B_HID) { - coex_sta->hid_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = false; - - if (bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) { - coex_sta->sco_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = false; - - } - - halbtc8723d2ant_update_bt_link_info(btcoexist); - - if (!(bt_info & BT_INFO_8723D_2ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8723D_2ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8723D_2ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8723D_2ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8723D_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8723D_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { - bt_busy = true; - limited_dig = true; - } else { - bt_busy = false; - limited_dig = false; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - coex_dm->limited_dig = limited_dig; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), No run_coexist_mechanism return for Manual CTRL<===\n"); - BTC_TRACE(trace_buf); - return; } - if (btcoexist->stop_coex_dm) { + if ((coex_sta->bt_info_ext & BIT(5))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), No run_coexist_mechanism return for Stop Coex DM <===\n"); + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); BTC_TRACE(trace_buf); - return; + coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist); + + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x4); } - /* don't run coex mechanism while receve BTInfo if GNT_WL/GNT_BT control by SW */ - if (!coex_sta->gnt_control_by_PTA) - return; + halbtc8723d2ant_update_bt_link_info(btcoexist); halbtc8723d2ant_run_coexist_mechanism(btcoexist); } @@ -5220,21 +6403,33 @@ void ex_halbtc8723d2ant_rf_status_notify(IN struct btc_coexist *btcoexist, "[BTCoex], RF is turned ON!!\n"); BTC_TRACE(trace_buf); - coex_sta->wl_rf_off_on_event = true; btcoexist->stop_coex_dm = false; - - halbtc8723d2ant_post_onoffstate_to_bt(btcoexist, TRUE); +#if 0 + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE, true); + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ONOFF, true); +#endif } else if (BTC_RF_OFF == type) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF is turned OFF!!\n"); BTC_TRACE(trace_buf); - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false, - true); + halbtc8723d2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_WLAN_OFF); + halbtc8723d2ant_action_coex_all_off(btcoexist); - halbtc8723d2ant_post_onoffstate_to_bt(btcoexist, FALSE); + + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE | + BT_8723D_2ANT_SCOREBOARD_ONOFF | + BT_8723D_2ANT_SCOREBOARD_SCAN | + BT_8723D_2ANT_SCOREBOARD_UNDERTEST, + false); + btcoexist->stop_coex_dm = true; - coex_sta->wl_rf_off_on_event = false; } } @@ -5244,14 +6439,19 @@ void ex_halbtc8723d2ant_halt_notify(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); BTC_TRACE(trace_buf); - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false, - true); + halbtc8723d2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_WLAN_OFF); ex_halbtc8723d2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, FALSE); - - halbtc8723d2ant_post_onoffstate_to_bt(btcoexist, FALSE); + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE | + BT_8723D_2ANT_SCOREBOARD_ONOFF | + BT_8723D_2ANT_SCOREBOARD_SCAN | + BT_8723D_2ANT_SCOREBOARD_UNDERTEST, + false); } void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist, @@ -5260,7 +6460,8 @@ void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist, BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); BTC_TRACE(trace_buf); - if (BTC_WIFI_PNP_SLEEP == pnp_state) { + if ((BTC_WIFI_PNP_SLEEP == pnp_state) || + (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify to SLEEP\n"); BTC_TRACE(trace_buf); @@ -5271,20 +6472,50 @@ void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist, coex_sta->under_ips = false; coex_sta->under_lps = false; - halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, FALSE); - halbtc8723d2ant_post_onoffstate_to_bt(btcoexist, FALSE); + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE | + BT_8723D_2ANT_SCOREBOARD_ONOFF | + BT_8723D_2ANT_SCOREBOARD_SCAN | + BT_8723D_2ANT_SCOREBOARD_UNDERTEST, + false); + + if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { + + halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_2G_RUNTIME); + } else { + + halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_WLAN_OFF); + } + + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify to WAKE UP\n"); BTC_TRACE(trace_buf); - - halbtc8723d2ant_post_onoffstate_to_bt(btcoexist, TRUE); +#if 0 + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ACTIVE, true); + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_ONOFF, true); +#endif } } void ex_halbtc8723d2ant_periodical(IN struct btc_coexist *btcoexist) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + struct btc_board_info *board_info = &btcoexist->board_info; + boolean wifi_busy = false; + u32 bt_patch_ver; + static u8 cnt = 0; + boolean bt_relink_finish = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ************* Periodical *************\n"); + BTC_TRACE(trace_buf); #if (BT_AUTO_REPORT_ONLY_8723D_2ANT == 0) halbtc8723d2ant_query_bt_info(btcoexist); @@ -5294,37 +6525,148 @@ void ex_halbtc8723d2ant_periodical(IN struct btc_coexist *btcoexist) halbtc8723d2ant_monitor_wifi_ctr(btcoexist); halbtc8723d2ant_monitor_bt_enable_disable(btcoexist); +#if 0 + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + /* halbtc8723d2ant_read_score_board(btcoexist, &bt_scoreboard_val); */ + + if (wifi_busy) { + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_UNDERTEST, true); + /* + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_WLBUSY, true); + + if (bt_scoreboard_val & BIT(6)) + halbtc8723d2ant_query_bt_info(btcoexist); */ + } else { + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_UNDERTEST, false); + /* + halbtc8723d2ant_post_state_to_bt(btcoexist, + BT_8723D_2ANT_SCOREBOARD_WLBUSY, + false); */ + } +#endif + + if (coex_sta->bt_relink_downcount != 0) { + coex_sta->bt_relink_downcount--; + + if (coex_sta->bt_relink_downcount == 0) + bt_relink_finish = true; + } + /* for 4-way, DHCP, EAPOL packet */ if (coex_sta->specific_pkt_period_cnt > 0) { coex_sta->specific_pkt_period_cnt--; - if ((coex_sta->specific_pkt_period_cnt == 0) && (coex_sta->wifi_is_high_pri_task)) + if ((coex_sta->specific_pkt_period_cnt == 0) && + (coex_sta->wifi_is_high_pri_task)) coex_sta->wifi_is_high_pri_task = false; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", (coex_sta->wifi_is_high_pri_task ? "Yes" : "No")); + "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", + (coex_sta->wifi_is_high_pri_task ? "Yes" : + "No")); BTC_TRACE(trace_buf); } + if (!coex_sta->bt_disabled) { + if (coex_sta->bt_coex_supported_feature == 0) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + if (coex_sta->bt_reg_vendor_ac == 0xffff) + coex_sta->bt_reg_vendor_ac = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xac) & 0xffff); + + if (coex_sta->bt_reg_vendor_ae == 0xffff) + coex_sta->bt_reg_vendor_ae = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xae) & 0xffff); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, + &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) { + cnt++; + + if (cnt >= 3) { + btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, + &coex_sta->bt_afh_map[0]); + cnt = 0; + } + } + +#if BT_8723D_2ANT_ANTDET_ENABLE + + if (board_info->btdm_ant_det_finish) { + if ((psd_scan->ant_det_result == 12) && + (psd_scan->ant_det_psd_scan_peak_val == 0) + && (!psd_scan->is_AntDet_running)) + psd_scan->ant_det_psd_scan_peak_val = + btcoexist->btc_get_ant_det_val_from_bt( + btcoexist) * 100; + } + +#endif + } + + if (halbtc8723d2ant_is_wifibt_status_changed(btcoexist)) halbtc8723d2ant_run_coexist_mechanism(btcoexist); } +void ex_halbtc8723d2ant_set_antenna_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (type == 2) { /* two antenna */ + board_info->ant_div_cfg = true; + + halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_2G_RUNTIME); + + } else { /* one antenna */ + + halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8723D_2ANT_PHASE_2G_RUNTIME); + } +} + +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist, IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) { + static u32 ant_det_count = 0, ant_det_fail_count = 0; + struct btc_board_info *board_info = &btcoexist->board_info; + u16 u16tmp; + u8 AntDetval = 0; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx Ext Call AntennaDetect()!!\n"); BTC_TRACE(trace_buf); #if BT_8723D_2ANT_ANTDET_ENABLE - static u32 ant_det_count = 0, ant_det_fail_count = 0; - struct btc_board_info *board_info = &btcoexist->board_info; - /*boolean scan, roam;*/ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx Call AntennaDetect()!!\n"); @@ -5349,36 +6691,103 @@ void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist, BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n"); BTC_TRACE(trace_buf); - halbtc8723d2ant_psd_antenna_detection_check(btcoexist); + + psd_scan->is_AntDet_running = true; + + halbtc8723d2ant_read_score_board(btcoexist, &u16tmp); + + if (u16tmp & BIT( + 2)) { /* Antenna detection is already done before last WL power on */ + board_info->btdm_ant_det_finish = true; + psd_scan->ant_det_try_count = 1; + psd_scan->ant_det_fail_count = 0; + board_info->btdm_ant_num_by_ant_det = (u16tmp & + BIT(3)) ? 1 : 2; + psd_scan->ant_det_result = 12; + + psd_scan->ant_det_psd_scan_peak_val = + btcoexist->btc_get_ant_det_val_from_bt( + btcoexist) * 100; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Result from BT (%d-Ant)\n", + board_info->btdm_ant_num_by_ant_det); + BTC_TRACE(trace_buf); + } else + board_info->btdm_ant_det_finish = + halbtc8723d2ant_psd_antenna_detection_check( + btcoexist); + + btcoexist->bdontenterLPS = false; if (board_info->btdm_ant_det_finish) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n"); BTC_TRACE(trace_buf); -#if 0 - board_info->btdm_ant_det_finish = false; -#endif + /*for 8723d, btc_set_bt_trx_mask is just used to + notify BT stop le tx and Ant Det Result , not set BT RF TRx Mask */ + if (psd_scan->ant_det_result != 12) { + + AntDetval = (u8)( + psd_scan->ant_det_psd_scan_peak_val + / 100) & 0x7f; + + AntDetval = + (board_info->btdm_ant_num_by_ant_det + == 1) ? (AntDetval | 0x80) : + AntDetval; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxx AntennaDetect(), Ant Count = %d, PSD Val = %d\n", + ((AntDetval & + 0x80) ? 1 + : 2), AntDetval + & 0x7f); + BTC_TRACE(trace_buf); + + if (btcoexist->btc_set_bt_trx_mask( + btcoexist, AntDetval)) + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask ok!\n"); + else + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask fail!\n"); + + BTC_TRACE(trace_buf); + } else + board_info->antdetval = + psd_scan->ant_det_psd_scan_peak_val/100; + + board_info->btdm_ant_det_complete_fail = false; -#if 0 - if (board_info->btdm_ant_num_by_ant_det == 2) - halbtc8723d2ant_mechanism_switch( - btcoexist, true); - else - halbtc8723d2ant_mechanism_switch( - btcoexist, false); -#endif } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n"); BTC_TRACE(trace_buf); } + psd_scan->ant_det_inteval_count = 0; + psd_scan->is_AntDet_running = false; + + /* stimulate coex running */ + halbtc8723d2ant_run_coexist_mechanism( + btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); + BTC_TRACE(trace_buf); } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n", psd_scan->ant_det_inteval_count); BTC_TRACE(trace_buf); + + if (psd_scan->ant_det_inteval_count == 8) + btcoexist->bdontenterLPS = true; + else + btcoexist->bdontenterLPS = false; } } @@ -5399,7 +6808,6 @@ void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist) if (board_info->btdm_ant_det_finish) halbtc8723d2ant_psd_showdata(btcoexist); - return; } #endif @@ -5409,3 +6817,4 @@ void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist) #endif #endif /* #if (RTL8723D_SUPPORT == 1) */ + diff --git a/hal/btc/halbtc8723d2ant.h b/hal/btc/halbtc8723d2ant.h index 15a56ce..ca064ec 100644 --- a/hal/btc/halbtc8723d2ant.h +++ b/hal/btc/halbtc8723d2ant.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) @@ -6,6 +20,7 @@ /* ******************************************* * The following is for 8723D 2Ant BT Co-exist definition * ******************************************* */ +#define BT_8723D_2ANT_COEX_DBG 0 #define BT_AUTO_REPORT_ONLY_8723D_2ANT 1 @@ -40,11 +55,12 @@ #define BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 52 #define BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT 40 #define BT_8723D_2ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8723D_2ANT_ANTDET_SWEEPPOINT_DELAY 40000 -#define BT_8723D_2ANT_ANTDET_ENABLE 0 -#define BT_8723D_2ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0 +#define BT_8723D_2ANT_ANTDET_SWEEPPOINT_DELAY 60000 +#define BT_8723D_2ANT_ANTDET_ENABLE 1 #define BT_8723D_2ANT_ANTDET_BTTXTIME 100 #define BT_8723D_2ANT_ANTDET_BTTXCHANNEL 39 +#define BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT 50 + #define BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 @@ -121,6 +137,28 @@ enum bt_8723d_2ant_coex_algo { BT_8723D_2ANT_COEX_ALGO_MAX }; +enum bt_8723d_2ant_phase { + BT_8723D_2ANT_PHASE_COEX_INIT = 0x0, + BT_8723D_2ANT_PHASE_WLANONLY_INIT = 0x1, + BT_8723D_2ANT_PHASE_WLAN_OFF = 0x2, + BT_8723D_2ANT_PHASE_2G_RUNTIME = 0x3, + BT_8723D_2ANT_PHASE_5G_RUNTIME = 0x4, + BT_8723D_2ANT_PHASE_BTMPMODE = 0x5, + BT_8723D_2ANT_PHASE_ANTENNA_DET = 0x6, + BT_8723D_2ANT_PHASE_COEX_POWERON = 0x7, + BT_8723D_2ANT_PHASE_MAX +}; + +enum bt_8723d_2ant_Scoreboard { + BT_8723D_2ANT_SCOREBOARD_ACTIVE = BIT(0), + BT_8723D_2ANT_SCOREBOARD_ONOFF = BIT(1), + BT_8723D_2ANT_SCOREBOARD_SCAN = BIT(2), + BT_8723D_2ANT_SCOREBOARD_UNDERTEST = BIT(3), + BT_8723D_2ANT_SCOREBOARD_WLBUSY = BIT(6) +}; + + + struct coex_dm_8723d_2ant { /* fw mechanism */ u8 pre_bt_dec_pwr_lvl; @@ -134,7 +172,6 @@ struct coex_dm_8723d_2ant { u8 ps_tdma_para[5]; u8 ps_tdma_du_adj_type; boolean reset_tdma_adjust; - boolean auto_tdma_adjust; boolean pre_ps_tdma_on; boolean cur_ps_tdma_on; boolean pre_bt_auto_report; @@ -181,56 +218,63 @@ struct coex_dm_8723d_2ant { boolean is_switch_to_1dot5_ant; u8 switch_thres_offset; u32 arp_cnt; + + u8 pre_ant_pos_type; + u8 cur_ant_pos_type; }; struct coex_sta_8723d_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + + boolean under_lps; + boolean under_ips; u32 high_priority_tx; u32 high_priority_rx; u32 low_priority_tx; u32 low_priority_rx; + boolean is_hiPri_rx_overhead; u8 bt_rssi; - boolean bt_tx_rx_mask; + boolean bt_tx_rx_mask; u8 pre_bt_rssi_state; u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; u8 bt_info_c2h[BT_INFO_SRC_8723D_2ANT_MAX][10]; u32 bt_info_c2h_cnt[BT_INFO_SRC_8723D_2ANT_MAX]; boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_remote_name_req; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; u8 bt_retry_cnt; u8 bt_info_ext; + u8 bt_info_ext2; u32 pop_event_cnt; u8 scan_ap_num; u32 crc_ok_cck; u32 crc_ok_11g; u32 crc_ok_11n; - u32 crc_ok_11n_agg; + u32 crc_ok_11n_vht; u32 crc_err_cck; u32 crc_err_11g; u32 crc_err_11n; - u32 crc_err_11n_agg; + u32 crc_err_11n_vht; + boolean cck_lock; + boolean pre_ccklock; + boolean cck_ever_lock; u8 coex_table_type; - boolean force_lps_on; + boolean force_lps_on; u8 dis_ver_info_cnt; u8 a2dp_bit_pool; u8 cut_version; - boolean concurrent_rx_mode_on; + boolean concurrent_rx_mode_on; u16 score_board; u8 isolation_btween_wb; /* 0~ 50 */ @@ -241,11 +285,44 @@ struct coex_sta_8723d_2ant { u8 num_of_profile; boolean acl_busy; - boolean wl_rf_off_on_event; boolean bt_create_connection; - boolean gnt_control_by_PTA; boolean wifi_is_high_pri_task; u32 specific_pkt_period_cnt; + u32 bt_coex_supported_feature; + u32 bt_coex_supported_version; + + u8 bt_ble_scan_type; + u32 bt_ble_scan_para[3]; + + boolean run_time_state; + boolean freeze_coexrun_by_btinfo; + + boolean is_A2DP_3M; + boolean voice_over_HOGP; + u8 bt_info; + boolean is_autoslot; + u8 forbidden_slot; + u8 hid_busy_num; + u8 hid_pair_cnt; + + u32 cnt_RemoteNameReq; + u32 cnt_setupLink; + u32 cnt_ReInit; + u32 cnt_IgnWlanAct; + u32 cnt_Page; + u32 cnt_RoleSwitch; + + u16 bt_reg_vendor_ac; + u16 bt_reg_vendor_ae; + + boolean is_setupLink; + boolean wl_noisy_level; + u32 gnt_error_cnt; + + u8 bt_afh_map[10]; + u8 bt_relink_downcount; + boolean is_tdma_btautoslot; + boolean is_tdma_btautoslot_hang; }; #define BT_8723D_2ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ @@ -282,10 +359,13 @@ struct psdscan_sta_8723d_2ant { u32 psd_stop_point; u32 psd_max_value_point; u32 psd_max_value; + u32 psd_max_value2; + u32 psd_avg_value; /* filter loop_max_value that below BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/ + u32 psd_loop_max_value[BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT]; /*max value in each loop */ u32 psd_start_base; u32 psd_avg_num; /* 1/8/16/32 */ u32 psd_gen_count; - boolean is_psd_running; + boolean is_AntDet_running; boolean is_psd_show_max_only; }; @@ -317,6 +397,8 @@ void ex_halbtc8723d2ant_rf_status_notify(IN struct btc_coexist *btcoexist, void ex_halbtc8723d2ant_halt_notify(IN struct btc_coexist *btcoexist); void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist, IN u8 pnp_state); +void ex_halbtc8723d2ant_set_antenna_notify(IN struct btc_coexist *btcoexist, + IN u8 type); void ex_halbtc8723d2ant_periodical(IN struct btc_coexist *btcoexist); void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist); void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist, @@ -341,8 +423,10 @@ void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist); #define ex_halbtc8723d2ant_pnp_notify(btcoexist, pnp_state) #define ex_halbtc8723d2ant_periodical(btcoexist) #define ex_halbtc8723d2ant_display_coex_info(btcoexist) +#define ex_halbtc8723d2ant_set_antenna_notify(btcoexist, type) #define ex_halbtc8723d2ant_display_ant_detection(btcoexist) -#define ex_halbtc8723d2ant_antenna_detection(btcoexist, centFreq, offset, span, seconds) +#define ex_halbtc8723d2ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) #endif #endif + diff --git a/hal/efuse/efuse_mask.h b/hal/efuse/efuse_mask.h index e1c38c1..8270569 100644 --- a/hal/efuse/efuse_mask.h +++ b/hal/efuse/efuse_mask.h @@ -1,98 +1,138 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #if DEV_BUS_TYPE == RT_USB_INTERFACE -#if defined(CONFIG_RTL8188E) - #include "rtl8188e/HalEfuseMask8188E_USB.h" -#endif + #if defined(CONFIG_RTL8188E) + #include "rtl8188e/HalEfuseMask8188E_USB.h" + #endif -#if defined(CONFIG_RTL8812A) - #include "rtl8812a/HalEfuseMask8812A_USB.h" -#endif + #if defined(CONFIG_RTL8812A) + #include "rtl8812a/HalEfuseMask8812A_USB.h" + #endif -#if defined(CONFIG_RTL8821A) - #include "rtl8812a/HalEfuseMask8821A_USB.h" -#endif + #if defined(CONFIG_RTL8821A) + #include "rtl8812a/HalEfuseMask8821A_USB.h" + #endif -#if defined(CONFIG_RTL8192E) - #include "rtl8192e/HalEfuseMask8192E_USB.h" -#endif + #if defined(CONFIG_RTL8192E) + #include "rtl8192e/HalEfuseMask8192E_USB.h" + #endif -#if defined(CONFIG_RTL8723B) - #include "rtl8723b/HalEfuseMask8723B_USB.h" -#endif + #if defined(CONFIG_RTL8723B) + #include "rtl8723b/HalEfuseMask8723B_USB.h" + #endif -#if defined(CONFIG_RTL8814A) - #include "rtl8814a/HalEfuseMask8814A_USB.h" -#endif + #if defined(CONFIG_RTL8814A) + #include "rtl8814a/HalEfuseMask8814A_USB.h" + #endif -#if defined(CONFIG_RTL8703B) - #include "rtl8703b/HalEfuseMask8703B_USB.h" -#endif + #if defined(CONFIG_RTL8703B) + #include "rtl8703b/HalEfuseMask8703B_USB.h" + #endif -#if defined(CONFIG_RTL8723D) - #include "rtl8723d/HalEfuseMask8723D_USB.h" -#endif + #if defined(CONFIG_RTL8723D) + #include "rtl8723d/HalEfuseMask8723D_USB.h" + #endif -#if defined(CONFIG_RTL8188F) - #include "rtl8188f/HalEfuseMask8188F_USB.h" -#endif + #if defined(CONFIG_RTL8188F) + #include "rtl8188f/HalEfuseMask8188F_USB.h" + #endif -#if defined(CONFIG_RTL8822B) - #include "rtl8822b/HalEfuseMask8822B_USB.h" -#endif + #if defined(CONFIG_RTL8822B) + #include "rtl8822b/HalEfuseMask8822B_USB.h" + #endif + + #if defined(CONFIG_RTL8821C) + #include "rtl8821c/HalEfuseMask8821C_USB.h" + #endif #elif DEV_BUS_TYPE == RT_PCI_INTERFACE -#if defined(CONFIG_RTL8188E) - #include "rtl8188e/HalEfuseMask8188E_PCIE.h" -#endif + #if defined(CONFIG_RTL8188E) + #include "rtl8188e/HalEfuseMask8188E_PCIE.h" + #endif -#if defined(CONFIG_RTL8812A) - #include "rtl8812a/HalEfuseMask8812A_PCIE.h" -#endif + #if defined(CONFIG_RTL8812A) + #include "rtl8812a/HalEfuseMask8812A_PCIE.h" + #endif -#if defined(CONFIG_RTL8821A) - #include "rtl8812a/HalEfuseMask8821A_PCIE.h" -#endif + #if defined(CONFIG_RTL8821A) + #include "rtl8812a/HalEfuseMask8821A_PCIE.h" + #endif -#if defined(CONFIG_RTL8192E) - #include "rtl8192e/HalEfuseMask8192E_PCIE.h" -#endif + #if defined(CONFIG_RTL8192E) + #include "rtl8192e/HalEfuseMask8192E_PCIE.h" + #endif -#if defined(CONFIG_RTL8723B) - #include "rtl8723b/HalEfuseMask8723B_PCIE.h" -#endif + #if defined(CONFIG_RTL8723B) + #include "rtl8723b/HalEfuseMask8723B_PCIE.h" + #endif -#if defined(CONFIG_RTL8814A) - #include "rtl8814a/HalEfuseMask8814A_PCIE.h" -#endif + #if defined(CONFIG_RTL8814A) + #include "rtl8814a/HalEfuseMask8814A_PCIE.h" + #endif -#if defined(CONFIG_RTL8703B) - #include "rtl8703b/HalEfuseMask8703B_PCIE.h" -#endif + #if defined(CONFIG_RTL8703B) + #include "rtl8703b/HalEfuseMask8703B_PCIE.h" + #endif -#if defined(CONFIG_RTL8822B) - #include "rtl8822b/HalEfuseMask8822B_PCIE.h" -#endif -#if defined(CONFIG_RTL8723D) - #include "rtl8723d/HalEfuseMask8723D_PCIE.h" -#endif + #if defined(CONFIG_RTL8822B) + #include "rtl8822b/HalEfuseMask8822B_PCIE.h" + #endif + #if defined(CONFIG_RTL8723D) + #include "rtl8723d/HalEfuseMask8723D_PCIE.h" + #endif + #if defined(CONFIG_RTL8821C) + #include "rtl8821c/HalEfuseMask8821C_PCIE.h" + #endif #elif DEV_BUS_TYPE == RT_SDIO_INTERFACE + #if defined(CONFIG_RTL8723B) + #include "rtl8723b/HalEfuseMask8723B_SDIO.h" + #endif -#if defined(CONFIG_RTL8188E) - #include "rtl8188e/HalEfuseMask8188E_SDIO.h" -#endif + #if defined(CONFIG_RTL8188E) + #include "rtl8188e/HalEfuseMask8188E_SDIO.h" + #endif -#if defined(CONFIG_RTL8703B) - #include "rtl8703b/HalEfuseMask8703B_SDIO.h" -#endif + #if defined(CONFIG_RTL8703B) + #include "rtl8703b/HalEfuseMask8703B_SDIO.h" + #endif -#if defined(CONFIG_RTL8188F) - #include "rtl8188f/HalEfuseMask8188F_SDIO.h" -#endif + #if defined(CONFIG_RTL8188F) + #include "rtl8188f/HalEfuseMask8188F_SDIO.h" + #endif -#if defined(CONFIG_RTL8723D) - #include "rtl8723d/HalEfuseMask8723D_SDIO.h" -#endif + #if defined(CONFIG_RTL8723D) + #include "rtl8723d/HalEfuseMask8723D_SDIO.h" + #endif + + #if defined(CONFIG_RTL8192E) + #include "rtl8192e/HalEfuseMask8192E_SDIO.h" + #endif + + #if defined(CONFIG_RTL8821A) + #include "rtl8812a/HalEfuseMask8821A_SDIO.h" + #endif + + #if defined(CONFIG_RTL8821C) + #include "rtl8821c/HalEfuseMask8821C_SDIO.h" + #endif + + #if defined(CONFIG_RTL8822B) + #include "rtl8822b/HalEfuseMask8822B_SDIO.h" + #endif #endif diff --git a/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.c b/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.c index 8e072a8..d8d61b9 100644 --- a/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.c +++ b/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.c @@ -1,22 +1,17 @@ /****************************************************************************** -* -* Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2015 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #include #include "HalEfuseMask8822B_PCIE.h" @@ -37,7 +32,7 @@ u1Byte Array_MP_8822B_MPCIE[] = { 0x00, 0x00, 0x00, - 0x0F, + 0x03, 0xF7, 0xFF, 0xFF, @@ -75,7 +70,6 @@ u1Byte Array_MP_8822B_MPCIE[] = { 0x00, 0x00, - }; u2Byte diff --git a/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.h b/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.h index e863d6a..af3faaa 100644 --- a/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.h +++ b/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.h @@ -1,22 +1,17 @@ /****************************************************************************** -* -* Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2015 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ /****************************************************************************** diff --git a/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.c b/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.c index 84dfde4..532d8b2 100644 --- a/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.c +++ b/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.c @@ -1,22 +1,17 @@ /****************************************************************************** -* -* Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2015 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #include #include "HalEfuseMask8822B_USB.h" @@ -37,15 +32,15 @@ u1Byte Array_MP_8822B_MUSB[] = { 0x00, 0x00, 0x00, - 0x0F, + 0x03, 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, - 0xF3, - 0x00, + 0xFF, + 0xFF, 0xF0, 0x00, 0x00, @@ -56,9 +51,7 @@ u1Byte Array_MP_8822B_MUSB[] = { 0x00, 0x00, 0x00, - 0x08, 0x00, - 0x80, 0x00, 0x00, 0x00, @@ -74,7 +67,8 @@ u1Byte Array_MP_8822B_MUSB[] = { 0x00, 0x00, 0x00, - + 0x00, + 0x00, }; u2Byte EFUSE_GetArrayLen_MP_8822B_MUSB(VOID) diff --git a/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.h b/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.h index b98ef77..ef368f2 100644 --- a/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.h +++ b/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.h @@ -1,22 +1,17 @@ /****************************************************************************** -* -* Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2015 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ diff --git a/hal/hal_btcoex.c b/hal/hal_btcoex.c index 4e213e7..05ab197 100644 --- a/hal/hal_btcoex.c +++ b/hal/hal_btcoex.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,19 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define __HAL_BTCOEX_C__ #ifdef CONFIG_BT_COEXIST #include #include -#include +#include "btc/mp_precomp.h" /* ************************************ * Global variables @@ -166,10 +161,22 @@ typedef enum _bt_c2h_status { /* C2H BT OP CODES */ typedef enum _bt_op_code { - BT_OP_GET_BT_VERSION = 0, - BT_OP_WRITE_REG_ADDR = 12, - BT_OP_WRITE_REG_VALUE, - BT_OP_READ_REG = 17 + BT_OP_GET_BT_VERSION = 0x00, + BT_OP_WRITE_REG_ADDR = 0x0c, + BT_OP_WRITE_REG_VALUE = 0x0d, + + BT_OP_READ_REG = 0x11, + + BT_LO_OP_GET_AFH_MAP_L = 0x1e, + BT_LO_OP_GET_AFH_MAP_M = 0x1f, + BT_LO_OP_GET_AFH_MAP_H = 0x20, + + BT_OP_GET_BT_COEX_SUPPORTED_FEATURE = 0x2a, + BT_OP_GET_BT_COEX_SUPPORTED_VERSION = 0x2b, + BT_OP_GET_BT_ANT_DET_VAL = 0x2c, + BT_OP_GET_BT_BLE_SCAN_PARA = 0x2d, + BT_OP_GET_BT_BLE_SCAN_TYPE = 0x2e, + BT_OP_MAX } BT_OP_CODE; #define BTC_MPOPER_TIMEOUT 50 /* unit: ms */ @@ -266,6 +273,22 @@ static u8 halbtcoutsrc_IsCsrBtCoex(PBTC_COEXIST pBtCoexist) return _FALSE; } +static void halbtcoutsrc_EnterPwrLock(PBTC_COEXIST pBtCoexist) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + + _enter_pwrlock(&pwrpriv->lock); +} + +static void halbtcoutsrc_ExitPwrLock(PBTC_COEXIST pBtCoexist) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + + _exit_pwrlock(&pwrpriv->lock); +} + static u8 halbtcoutsrc_IsHwMailboxExist(PBTC_COEXIST pBtCoexist) { if (pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC4 @@ -278,17 +301,17 @@ static u8 halbtcoutsrc_IsHwMailboxExist(PBTC_COEXIST pBtCoexist) return _TRUE; } -static void halbtcoutsrc_LeaveLps(PBTC_COEXIST pBtCoexist) +static u8 halbtcoutsrc_LeaveLps(PBTC_COEXIST pBtCoexist) { PADAPTER padapter; padapter = pBtCoexist->Adapter; - pBtCoexist->btInfo.bBtCtrlLps = _TRUE; - pBtCoexist->btInfo.bBtLpsOn = _FALSE; + pBtCoexist->bt_info.bt_ctrl_lps = _TRUE; + pBtCoexist->bt_info.bt_lps_on = _FALSE; - rtw_btcoex_LPS_Leave(padapter); + return rtw_btcoex_LPS_Leave(padapter); } void halbtcoutsrc_EnterLps(PBTC_COEXIST pBtCoexist) @@ -299,8 +322,8 @@ void halbtcoutsrc_EnterLps(PBTC_COEXIST pBtCoexist) padapter = pBtCoexist->Adapter; if (pBtCoexist->bdontenterLPS == _FALSE) { - pBtCoexist->btInfo.bBtCtrlLps = _TRUE; - pBtCoexist->btInfo.bBtLpsOn = _TRUE; + pBtCoexist->bt_info.bt_ctrl_lps = _TRUE; + pBtCoexist->bt_info.bt_lps_on = _TRUE; rtw_btcoex_LPS_Enter(padapter); } @@ -311,18 +334,17 @@ void halbtcoutsrc_NormalLps(PBTC_COEXIST pBtCoexist) PADAPTER padapter; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Normal LPS behavior!!!\n")); padapter = pBtCoexist->Adapter; - if (pBtCoexist->btInfo.bBtCtrlLps) { - pBtCoexist->btInfo.bBtLpsOn = _FALSE; + if (pBtCoexist->bt_info.bt_ctrl_lps) { + pBtCoexist->bt_info.bt_lps_on = _FALSE; rtw_btcoex_LPS_Leave(padapter); - pBtCoexist->btInfo.bBtCtrlLps = _FALSE; + pBtCoexist->bt_info.bt_ctrl_lps = _FALSE; /* recover the LPS state to the original */ #if 0 - padapter->HalFunc.UpdateLPSStatusHandler( + padapter->hal_func.UpdateLPSStatusHandler( padapter, pPSC->RegLeisurePsMode, pPSC->RegPowerSaveMode); @@ -330,6 +352,24 @@ void halbtcoutsrc_NormalLps(PBTC_COEXIST pBtCoexist) } } +void halbtcoutsrc_Pre_NormalLps(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + + padapter = pBtCoexist->Adapter; + + if (pBtCoexist->bt_info.bt_ctrl_lps) { + pBtCoexist->bt_info.bt_lps_on = _FALSE; + rtw_btcoex_LPS_Leave(padapter); + } +} + +void halbtcoutsrc_Post_NormalLps(PBTC_COEXIST pBtCoexist) +{ + if (pBtCoexist->bt_info.bt_ctrl_lps) + pBtCoexist->bt_info.bt_ctrl_lps = _FALSE; +} + /* * Constraint: * 1. this function will request pwrctrl->lock @@ -397,7 +437,7 @@ void halbtcoutsrc_NormalLowPower(PBTC_COEXIST pBtCoexist) void halbtcoutsrc_DisableLowPower(PBTC_COEXIST pBtCoexist, u8 bLowPwrDisable) { - pBtCoexist->btInfo.bBtDisableLowPwr = bLowPwrDisable; + pBtCoexist->bt_info.bt_disable_low_pwr = bLowPwrDisable; if (bLowPwrDisable) halbtcoutsrc_LeaveLowPower(pBtCoexist); /* leave 32k low power. */ else @@ -425,26 +465,26 @@ void halbtcoutsrc_AggregationCheck(PBTC_COEXIST pBtCoexist) else preTime = curTime; - if (pBtCoexist->btInfo.bRejectAggPkt) { + if (pBtCoexist->bt_info.reject_agg_pkt) { bNeedToAct = _TRUE; - pBtCoexist->btInfo.bPreRejectAggPkt = pBtCoexist->btInfo.bRejectAggPkt; + pBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt; } else { - if (pBtCoexist->btInfo.bPreRejectAggPkt) { + if (pBtCoexist->bt_info.pre_reject_agg_pkt) { bNeedToAct = _TRUE; - pBtCoexist->btInfo.bPreRejectAggPkt = pBtCoexist->btInfo.bRejectAggPkt; + pBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt; } - if (pBtCoexist->btInfo.bPreBtCtrlAggBufSize != - pBtCoexist->btInfo.bBtCtrlAggBufSize) { + if (pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size != + pBtCoexist->bt_info.bt_ctrl_agg_buf_size) { bNeedToAct = _TRUE; - pBtCoexist->btInfo.bPreBtCtrlAggBufSize = pBtCoexist->btInfo.bBtCtrlAggBufSize; + pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size = pBtCoexist->bt_info.bt_ctrl_agg_buf_size; } - if (pBtCoexist->btInfo.bBtCtrlAggBufSize) { - if (pBtCoexist->btInfo.preAggBufSize != - pBtCoexist->btInfo.aggBufSize) + if (pBtCoexist->bt_info.bt_ctrl_agg_buf_size) { + if (pBtCoexist->bt_info.pre_agg_buf_size != + pBtCoexist->bt_info.agg_buf_size) bNeedToAct = _TRUE; - pBtCoexist->btInfo.preAggBufSize = pBtCoexist->btInfo.aggBufSize; + pBtCoexist->bt_info.pre_agg_buf_size = pBtCoexist->bt_info.agg_buf_size; } } @@ -452,6 +492,26 @@ void halbtcoutsrc_AggregationCheck(PBTC_COEXIST pBtCoexist) rtw_btcoex_rx_ampdu_apply(padapter); } +u8 halbtcoutsrc_is_autoload_fail(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + PHAL_DATA_TYPE pHalData; + + padapter = pBtCoexist->Adapter; + pHalData = GET_HAL_DATA(padapter); + + return pHalData->bautoload_fail_flag; +} + +u8 halbtcoutsrc_is_fw_ready(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + + padapter = pBtCoexist->Adapter; + + return GET_HAL_DATA(padapter)->bFWReady; +} + u8 halbtcoutsrc_IsWifiBusy(PADAPTER padapter) { if (rtw_mi_check_status(padapter, MI_AP_MODE)) @@ -531,18 +591,6 @@ u32 halbtcoutsrc_GetWifiLinkStatus(PBTC_COEXIST pBtCoexist) return retVal; } -static u8 _is_btfwver_valid(PBTC_COEXIST pBtCoexist, u16 btfwver) -{ - if (!btfwver) - return _FALSE; - - if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) - if (btfwver == 0x8723) - return _FALSE; - - return _TRUE; -} - static void _btmpoper_timer_hdl(void *p) { if (GLBtcBtMpRptWait) { @@ -562,7 +610,6 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm u8 buf[H2C_BTMP_OPER_LEN] = {0}; u8 buflen; u8 seq; - u8 timer_cancelled; s32 ret; @@ -587,7 +634,7 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm padapter = pBtCoexist->Adapter; _set_timer(&GLBtcBtMpOperTimer, BTC_MPOPER_TIMEOUT); if (rtw_hal_fill_h2c_cmd(padapter, H2C_BT_MP_OPER, buflen, buf) == _FAIL) { - _cancel_timer(&GLBtcBtMpOperTimer, &timer_cancelled); + _cancel_timer_ex(&GLBtcBtMpOperTimer); ret = BT_STATUS_H2C_FAIL; goto exit; } @@ -596,17 +643,17 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm /* GLBtcBtMpRptWait should be 0 here*/ if (!GLBtcBtMpRptWiFiOK) { - RTW_INFO("%s: Didn't get H2C Rsp Event!\n", __FUNCTION__); + RTW_ERR("%s: Didn't get H2C Rsp Event!\n", __FUNCTION__); ret = BT_STATUS_H2C_TIMTOUT; goto exit; } if (!GLBtcBtMpRptBTOK) { - RTW_INFO("%s: Didn't get BT response!\n", __FUNCTION__); + RTW_DBG("%s: Didn't get BT response!\n", __FUNCTION__); ret = BT_STATUS_H2C_BT_NO_RSP; goto exit; } if (seq != GLBtcBtMpRptSeq) { - RTW_INFO("%s: Sequence number not match!(%d!=%d)!\n", + RTW_ERR("%s: Sequence number not match!(%d!=%d)!\n", __FUNCTION__, seq, GLBtcBtMpRptSeq); ret = BT_STATUS_C2H_REQNUM_MISMATCH; goto exit; @@ -616,23 +663,23 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm /* Examine the status reported from C2H */ case BT_STATUS_OK: ret = BT_STATUS_BT_OP_SUCCESS; - RTW_INFO("%s: C2H status = BT_STATUS_BT_OP_SUCCESS\n", __FUNCTION__); + RTW_DBG("%s: C2H status = BT_STATUS_BT_OP_SUCCESS\n", __FUNCTION__); break; case BT_STATUS_VERSION_MISMATCH: ret = BT_STATUS_OPCODE_L_VERSION_MISMATCH; - RTW_INFO("%s: C2H status = BT_STATUS_OPCODE_L_VERSION_MISMATCH\n", __FUNCTION__); + RTW_DBG("%s: C2H status = BT_STATUS_OPCODE_L_VERSION_MISMATCH\n", __FUNCTION__); break; case BT_STATUS_UNKNOWN_OPCODE: ret = BT_STATUS_UNKNOWN_OPCODE_L; - RTW_INFO("%s: C2H status = MP_BT_STATUS_UNKNOWN_OPCODE_L\n", __FUNCTION__); + RTW_DBG("%s: C2H status = MP_BT_STATUS_UNKNOWN_OPCODE_L\n", __FUNCTION__); break; case BT_STATUS_ERROR_PARAMETER: ret = BT_STATUS_PARAMETER_FORMAT_ERROR_L; - RTW_INFO("%s: C2H status = MP_BT_STATUS_PARAMETER_FORMAT_ERROR_L\n", __FUNCTION__); + RTW_DBG("%s: C2H status = MP_BT_STATUS_PARAMETER_FORMAT_ERROR_L\n", __FUNCTION__); break; default: ret = BT_STATUS_UNKNOWN_STATUS_L; - RTW_INFO("%s: C2H status = MP_BT_STATUS_UNKNOWN_STATUS_L\n", __FUNCTION__); + RTW_DBG("%s: C2H status = MP_BT_STATUS_UNKNOWN_STATUS_L\n", __FUNCTION__); break; } @@ -642,49 +689,109 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm u32 halbtcoutsrc_GetBtPatchVer(PBTC_COEXIST pBtCoexist) { - if (_is_btfwver_valid(pBtCoexist, pBtCoexist->btInfo.btRealFwVer) == _TRUE) - goto exit; + if (pBtCoexist->bt_info.get_bt_fw_ver_cnt <= 5) { + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + _irqL irqL; + u8 ret; - if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { - _irqL irqL; - u8 ret; - - - _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); - ret = _btmpoper_cmd(pBtCoexist, BT_OP_GET_BT_VERSION, 0, NULL, 0); - if (BT_STATUS_BT_OP_SUCCESS == ret) { - pBtCoexist->btInfo.btRealFwVer = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp); - pBtCoexist->btInfo.btFwVer = *(GLBtcBtMpRptRsp + 2); - } - pBtCoexist->btInfo.getBtFwVerCnt++; + ret = _btmpoper_cmd(pBtCoexist, BT_OP_GET_BT_VERSION, 0, NULL, 0); + if (BT_STATUS_BT_OP_SUCCESS == ret) { + pBtCoexist->bt_info.bt_real_fw_ver = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp); + pBtCoexist->bt_info.bt_fw_ver = *(GLBtcBtMpRptRsp + 2); + pBtCoexist->bt_info.get_bt_fw_ver_cnt++; + } - _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); - } else { + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + } else { #ifdef CONFIG_BT_COEXIST_SOCKET_TRX - u1Byte dataLen = 2; - u1Byte buf[4] = {0}; + u1Byte dataLen = 2; + u1Byte buf[4] = {0}; - buf[0] = 0x0; /* OP_Code */ - buf[1] = 0x0; /* OP_Code_Length */ - BT_SendEventExtBtCoexControl(pBtCoexist->Adapter, _FALSE, dataLen, &buf[0]); + buf[0] = 0x0; /* OP_Code */ + buf[1] = 0x0; /* OP_Code_Length */ + BT_SendEventExtBtCoexControl(pBtCoexist->Adapter, _FALSE, dataLen, &buf[0]); #endif /* !CONFIG_BT_COEXIST_SOCKET_TRX */ + } } exit: - return pBtCoexist->btInfo.btRealFwVer; + return pBtCoexist->bt_info.bt_real_fw_ver; } s32 halbtcoutsrc_GetWifiRssi(PADAPTER padapter) { PHAL_DATA_TYPE pHalData; - s32 UndecoratedSmoothedPWDB = 0; + s32 undecorated_smoothed_pwdb = 0; pHalData = GET_HAL_DATA(padapter); - UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; + undecorated_smoothed_pwdb = pHalData->entry_min_undecorated_smoothed_pwdb; - return UndecoratedSmoothedPWDB; + return undecorated_smoothed_pwdb; +} + +u32 halbtcoutsrc_GetBtCoexSupportedFeature(void *pBtcContext) +{ + PBTC_COEXIST pBtCoexist; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + u32 data = 0; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_GET_BT_COEX_SUPPORTED_FEATURE; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp); + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return data; +} + +u32 halbtcoutsrc_GetBtCoexSupportedVersion(void *pBtcContext) +{ + PBTC_COEXIST pBtCoexist; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + u32 data = 0xFFFF; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_GET_BT_COEX_SUPPORTED_VERSION; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp); + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return data; } static u8 halbtcoutsrc_GetWifiScanAPNum(PADAPTER padapter) @@ -747,6 +854,10 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) ret = _FALSE; break; + case BTC_GET_BL_WIFI_FW_READY: + *pu8 = halbtcoutsrc_is_fw_ready(pBtCoexist); + break; + case BTC_GET_BL_WIFI_CONNECTED: *pu8 = (rtw_mi_check_status(padapter, MI_LINKED)) ? _TRUE : _FALSE; break; @@ -778,7 +889,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) break; case BTC_GET_BL_WIFI_UNDER_5G: - *pu8 = (pHalData->CurrentBandType == 1) ? _TRUE : _FALSE; + *pu8 = (pHalData->current_band_type == 1) ? _TRUE : _FALSE; break; case BTC_GET_BL_WIFI_AP_MODE_ENABLE: @@ -811,6 +922,17 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) *pu8 = _FALSE; break; + case BTC_GET_BL_RF4CE_CONNECTED: +#ifdef CONFIG_RF4CE_COEXIST + if (hal_btcoex_get_rf4ce_link_state() == 0) + *pu8 = FALSE; + else + *pu8 = TRUE; +#else + *pu8 = FALSE; +#endif + break; + case BTC_GET_S4_WIFI_RSSI: *pS4Tmp = halbtcoutsrc_GetWifiRssi(padapter); break; @@ -824,7 +946,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) if (IsLegacyOnly(mlmeext->cur_wireless_mode)) *pU4Tmp = BTC_WIFI_BW_LEGACY; else { - switch (pHalData->CurrentChannelBW) { + switch (pHalData->current_channel_bw) { case CHANNEL_WIDTH_20: *pU4Tmp = BTC_WIFI_BW_HT20; break; @@ -838,7 +960,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) *pU4Tmp = BTC_WIFI_BW_HT160; break; default: - RTW_INFO("[BTCOEX] unkown bandwidth(%d)\n", pHalData->CurrentChannelBW); + RTW_INFO("[BTCOEX] unknown bandwidth(%d)\n", pHalData->current_channel_bw); *pU4Tmp = BTC_WIFI_BW_HT40; break; } @@ -855,11 +977,11 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) else *pU4Tmp = BTC_WIFI_TRAFFIC_RX; } - break; + break; case BTC_GET_U4_WIFI_FW_VER: - *pU4Tmp = pHalData->FirmwareVersion << 16; - *pU4Tmp |= pHalData->FirmwareSubVersion; + *pU4Tmp = pHalData->firmware_version << 16; + *pU4Tmp |= pHalData->firmware_sub_version; break; case BTC_GET_U4_WIFI_LINK_STATUS: @@ -874,16 +996,23 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) *pU4Tmp = BTC_VENDOR_OTHER; break; + case BTC_GET_U4_SUPPORTED_VERSION: + *pU4Tmp = halbtcoutsrc_GetBtCoexSupportedVersion(pBtCoexist); + break; + case BTC_GET_U4_SUPPORTED_FEATURE: + *pU4Tmp = halbtcoutsrc_GetBtCoexSupportedFeature(pBtCoexist); + break; + case BTC_GET_U4_WIFI_IQK_TOTAL: - *pU4Tmp = pHalData->odmpriv.nIQK_Cnt; + *pU4Tmp = pHalData->odmpriv.n_iqk_cnt; break; case BTC_GET_U4_WIFI_IQK_OK: - *pU4Tmp = pHalData->odmpriv.nIQK_OK_Cnt; + *pU4Tmp = pHalData->odmpriv.n_iqk_ok_cnt; break; case BTC_GET_U4_WIFI_IQK_FAIL: - *pU4Tmp = pHalData->odmpriv.nIQK_Fail_Cnt; + *pU4Tmp = pHalData->odmpriv.n_iqk_fail_cnt; break; case BTC_GET_U1_WIFI_DOT11_CHNL: @@ -891,7 +1020,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) break; case BTC_GET_U1_WIFI_CENTRAL_CHNL: - *pU1Tmp = pHalData->CurrentChannel; + *pU1Tmp = pHalData->current_channel; break; case BTC_GET_U1_WIFI_HS_CHNL: @@ -971,6 +1100,7 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) u8 *pU1Tmp; u32 *pU4Tmp; u8 ret; + u8 result = _TRUE; pBtCoexist = (PBTC_COEXIST)pBtcContext; @@ -987,48 +1117,52 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) switch (setType) { /* set some u8 type variables. */ case BTC_SET_BL_BT_DISABLE: - pBtCoexist->btInfo.bBtDisabled = *pu8; + pBtCoexist->bt_info.bt_disabled = *pu8; + break; + + case BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE: + pBtCoexist->bt_info.bt_enable_disable_change = *pu8; break; case BTC_SET_BL_BT_TRAFFIC_BUSY: - pBtCoexist->btInfo.bBtBusy = *pu8; + pBtCoexist->bt_info.bt_busy = *pu8; break; case BTC_SET_BL_BT_LIMITED_DIG: - pBtCoexist->btInfo.bLimitedDig = *pu8; + pBtCoexist->bt_info.limited_dig = *pu8; break; case BTC_SET_BL_FORCE_TO_ROAM: - pBtCoexist->btInfo.bForceToRoam = *pu8; + pBtCoexist->bt_info.force_to_roam = *pu8; break; case BTC_SET_BL_TO_REJ_AP_AGG_PKT: - pBtCoexist->btInfo.bRejectAggPkt = *pu8; + pBtCoexist->bt_info.reject_agg_pkt = *pu8; break; case BTC_SET_BL_BT_CTRL_AGG_SIZE: - pBtCoexist->btInfo.bBtCtrlAggBufSize = *pu8; + pBtCoexist->bt_info.bt_ctrl_agg_buf_size = *pu8; break; case BTC_SET_BL_INC_SCAN_DEV_NUM: - pBtCoexist->btInfo.bIncreaseScanDevNum = *pu8; + pBtCoexist->bt_info.increase_scan_dev_num = *pu8; break; case BTC_SET_BL_BT_TX_RX_MASK: - pBtCoexist->btInfo.bBtTxRxMask = *pu8; + pBtCoexist->bt_info.bt_tx_rx_mask = *pu8; break; case BTC_SET_BL_MIRACAST_PLUS_BT: - pBtCoexist->btInfo.bMiracastPlusBt = *pu8; + pBtCoexist->bt_info.miracast_plus_bt = *pu8; break; /* set some u8 type variables. */ case BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON: - pBtCoexist->btInfo.rssiAdjustForAgcTableOn = *pU1Tmp; + pBtCoexist->bt_info.rssi_adjust_for_agc_table_on = *pU1Tmp; break; case BTC_SET_U1_AGG_BUF_SIZE: - pBtCoexist->btInfo.aggBufSize = *pU1Tmp; + pBtCoexist->bt_info.agg_buf_size = *pU1Tmp; break; /* the following are some action which will be triggered */ @@ -1047,20 +1181,20 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) /* =======1Ant=========== */ /* set some u8 type variables. */ case BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE: - pBtCoexist->btInfo.rssiAdjustFor1AntCoexType = *pU1Tmp; + pBtCoexist->bt_info.rssi_adjust_for_1ant_coex_type = *pU1Tmp; break; case BTC_SET_U1_LPS_VAL: - pBtCoexist->btInfo.lpsVal = *pU1Tmp; + pBtCoexist->bt_info.lps_val = *pU1Tmp; break; case BTC_SET_U1_RPWM_VAL: - pBtCoexist->btInfo.rpwmVal = *pU1Tmp; + pBtCoexist->bt_info.rpwm_val = *pU1Tmp; break; /* the following are some action which will be triggered */ case BTC_SET_ACT_LEAVE_LPS: - halbtcoutsrc_LeaveLps(pBtCoexist); + result = halbtcoutsrc_LeaveLps(pBtCoexist); break; case BTC_SET_ACT_ENTER_LPS: @@ -1071,12 +1205,20 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) halbtcoutsrc_NormalLps(pBtCoexist); break; + case BTC_SET_ACT_PRE_NORMAL_LPS: + halbtcoutsrc_Pre_NormalLps(pBtCoexist); + break; + + case BTC_SET_ACT_POST_NORMAL_LPS: + halbtcoutsrc_Post_NormalLps(pBtCoexist); + break; + case BTC_SET_ACT_DISABLE_LOW_POWER: halbtcoutsrc_DisableLowPower(pBtCoexist, *pu8); break; case BTC_SET_ACT_UPDATE_RAMASK: - pBtCoexist->btInfo.raMask = *pU4Tmp; + pBtCoexist->bt_info.ra_mask = *pU4Tmp; if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) { struct sta_info *psta; @@ -1084,7 +1226,7 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) cur_network = &padapter->mlmeextpriv.mlmext_info.network; psta = rtw_get_stainfo(&padapter->stapriv, cur_network->MacAddress); - rtw_hal_update_ra_mask(psta, 0); + rtw_hal_update_ra_mask(psta, psta->rssi_level, _FALSE); } break; @@ -1153,7 +1295,7 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) break; } - return ret; + return result; } u8 halbtcoutsrc_UnderIps(PBTC_COEXIST pBtCoexist) @@ -1416,8 +1558,9 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist) pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_TOTAL, &iqk_cnt_total); pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_OK, &iqk_cnt_ok); pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_FAIL, &iqk_cnt_fail); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "IQK Total/ OK/ Fail", \ - iqk_cnt_total, iqk_cnt_ok, iqk_cnt_fail); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d %s %s", + "IQK All/ OK/ Fail/AutoLoad/FWDL", iqk_cnt_total, iqk_cnt_ok, iqk_cnt_fail, + ((halbtcoutsrc_is_autoload_fail(pBtCoexist) == _TRUE) ? "fail":"ok"), ((halbtcoutsrc_is_fw_ready(pBtCoexist) == _TRUE) ? "ok":"fail")); CL_PRINTF(cliBuf); if (wifiLinkStatus & WIFI_STA_CONNECTED) { @@ -1456,8 +1599,8 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist) pBtCoexist->pwrModeVal[0], pBtCoexist->pwrModeVal[1], pBtCoexist->pwrModeVal[2], pBtCoexist->pwrModeVal[3], pBtCoexist->pwrModeVal[4], pBtCoexist->pwrModeVal[5], - pBtCoexist->btInfo.lpsVal, - pBtCoexist->btInfo.rpwmVal); + pBtCoexist->bt_info.lps_val, + pBtCoexist->bt_info.rpwm_val); CL_PRINTF(cliBuf); } @@ -1605,7 +1748,7 @@ void halbtcoutsrc_SetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask, u32 Data pBtCoexist = (PBTC_COEXIST)pBtcContext; padapter = pBtCoexist->Adapter; - PHY_SetBBReg(padapter, RegAddr, BitMask, Data); + phy_set_bb_reg(padapter, RegAddr, BitMask, Data); } @@ -1618,7 +1761,7 @@ u32 halbtcoutsrc_GetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask) pBtCoexist = (PBTC_COEXIST)pBtcContext; padapter = pBtCoexist->Adapter; - return PHY_QueryBBReg(padapter, RegAddr, BitMask); + return phy_query_bb_reg(padapter, RegAddr, BitMask); } void halbtcoutsrc_SetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) @@ -1630,7 +1773,7 @@ void halbtcoutsrc_SetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMa pBtCoexist = (PBTC_COEXIST)pBtcContext; padapter = pBtCoexist->Adapter; - PHY_SetRFReg(padapter, eRFPath, RegAddr, BitMask, Data); + phy_set_rf_reg(padapter, eRFPath, RegAddr, BitMask, Data); } u32 halbtcoutsrc_GetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask) @@ -1642,7 +1785,7 @@ u32 halbtcoutsrc_GetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMas pBtCoexist = (PBTC_COEXIST)pBtcContext; padapter = pBtCoexist->Adapter; - return PHY_QueryRFReg(padapter, eRFPath, RegAddr, BitMask); + return phy_query_rf_reg(padapter, eRFPath, RegAddr, BitMask); } u16 halbtcoutsrc_SetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 Data) @@ -1700,7 +1843,39 @@ u8 halbtcoutsrc_SetBtAntDetection(void *pBtcContext, u8 txTime, u8 btChnl) #endif } -u16 halbtcoutsrc_GetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 *data) +BOOLEAN +halbtcoutsrc_SetBtTRXMASK( + IN PVOID pBtcContext, + IN u1Byte bt_trx_mask + ) +{ + /* Always return _FALSE since we don't implement this yet */ +#if 0 + struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext; + PADAPTER Adapter = pBtCoexist->Adapter; + BOOLEAN bStatus = FALSE; + u1Byte btCanTx = 0; + + if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter) || IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter) + || IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + + if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + bStatus = NDBG_SetBtTRXMASK(Adapter, 1, bt_trx_mask, &btCanTx); + else + bStatus = NDBG_SetBtTRXMASK(Adapter, 2, bt_trx_mask, &btCanTx); + } + + + if (bStatus) + return TRUE; + else + return FALSE; +#else + return _FALSE; +#endif +} + +u16 halbtcoutsrc_GetBtReg_with_status(void *pBtcContext, u8 RegType, u32 RegAddr, u32 *data) { PBTC_COEXIST pBtCoexist; u16 ret = BT_STATUS_BT_OP_SUCCESS; @@ -1733,6 +1908,13 @@ u16 halbtcoutsrc_GetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 *data) return ret; } +u32 halbtcoutsrc_GetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr) +{ + u32 regVal; + + return (BT_STATUS_BT_OP_SUCCESS == halbtcoutsrc_GetBtReg_with_status(pBtcContext, RegType, RegAddr, ®Val)) ? regVal : 0xffffffff; +} + void halbtcoutsrc_FillH2cCmd(void *pBtcContext, u8 elementId, u32 cmdLen, u8 *pCmdBuffer) { PBTC_COEXIST pBtCoexist; @@ -1772,15 +1954,10 @@ static COL_H2C_STATUS halbtcoutsrc_send_h2c(PADAPTER Adapter, PCOL_H2C pcol_h2c, if (TRUE) { #if 0 /*(USE_HAL_MAC_API == 1) */ if (RT_STATUS_SUCCESS == HAL_MAC_Send_BT_COEX(&GET_HAL_MAC_INFO(Adapter), (pu1Byte)(pcol_h2c), (u4Byte)h2c_cmd_len, 1)) { - RT_TRACE(COMP_COEX, DBG_LOUD, ("HAL_MAC_Send_BT_COEX successfully.\n")); - if (wait_for_completion_timeout(&gl_coex_offload.c2h_event[pcol_h2c->req_num], 20)) - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], received H2C rsp event!!\n")); - else { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], H2C timeout!!\n")); + if (!wait_for_completion_timeout(&gl_coex_offload.c2h_event[pcol_h2c->req_num], 20)) { h2c_status = COL_STATUS_H2C_TIMTOUT; } } else { - RT_TRACE(COMP_COEX, DBG_LOUD, ("HAL_MAC_Send_BT_COEX fail.\n")); h2c_status = COL_STATUS_H2C_HALMAC_FAIL; } #endif @@ -1796,11 +1973,8 @@ static COL_H2C_STATUS halbtcoutsrc_check_c2h_ack(PADAPTER Adapter, PCOL_SINGLE_H u8 req_num = p_h2c_cmd->req_num; PCOL_C2H_ACK p_c2h_ack = (PCOL_C2H_ACK)&gl_coex_offload.c2h_ack_buf[req_num]; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], c2h ack len=%d, coex return len=%d!!!\n", - gl_coex_offload.c2h_ack_len[req_num], p_c2h_ack->ret_len)); if ((COL_C2H_ACK_HDR_LEN + p_c2h_ack->ret_len) > gl_coex_offload.c2h_ack_len[req_num]) { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], coex data overflow!!!\n")); c2h_status = COL_STATUS_COEX_DATA_OVERFLOW; return c2h_status; } @@ -1810,18 +1984,13 @@ static COL_H2C_STATUS halbtcoutsrc_check_c2h_ack(PADAPTER Adapter, PCOL_SINGLE_H pH2cRecord->c2h_ack_len = gl_coex_offload.c2h_ack_len[req_num]; } - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], c2h ack: status=0x%x, opcode_ver=0x%x, req_num=%d, ret_len=%d\n", - p_c2h_ack->status, p_c2h_ack->opcode_ver, p_c2h_ack->req_num, p_c2h_ack->ret_len)); if (p_c2h_ack->req_num != p_h2c_cmd->req_num) { c2h_status = COL_STATUS_C2H_REQ_NUM_MISMATCH; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], Error!! C2H req_num Mismatch!!\n")); } else if (p_c2h_ack->opcode_ver != p_h2c_cmd->opcode_ver) { c2h_status = COL_STATUS_C2H_OPCODE_VER_MISMATCH; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], Error!! OPCode version mismatch!!\n")); } else { c2h_status = p_c2h_ack->status; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], status from fw = %d!!\n", c2h_status)); } return c2h_status; @@ -1846,8 +2015,6 @@ COL_H2C_STATUS halbtcoutsrc_CoexH2cProcess(void *pBtCoexist, _rtw_memmove(&pcol_h2c->buf[0], ph2c_par, h2c_par_len); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], H2C opcode/ opcode_ver/ req_num/ h2c_par_len=%d/ %d/ %d/ %d\n", - pcol_h2c->opcode, pcol_h2c->opcode_ver, pcol_h2c->req_num, h2c_par_len)); col_h2c_len = h2c_par_len + 2; /* 2=sizeof(OPCode, OPCode_version and Request number) */ BT_PrintData(Adapter, "[COL], H2C cmd: ", col_h2c_len, H2C_Parameter); @@ -1867,7 +2034,6 @@ COL_H2C_STATUS halbtcoutsrc_CoexH2cProcess(void *pBtCoexist, c2h_status = halbtcoutsrc_check_c2h_ack(Adapter, &gl_coex_offload.h2c_record[opcode]); ret_status = c2h_status; } else { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], H2C failed for opCode=%d\n", opcode)); /* check h2c status error, return error status code to upper layer. */ ret_status = h2c_status; } @@ -1877,29 +2043,143 @@ COL_H2C_STATUS halbtcoutsrc_CoexH2cProcess(void *pBtCoexist, return ret_status; } -u32 halbtcoutsrc_GetBtCoexSupportedFeature(void *pBtcContext) +u8 halbtcoutsrc_GetAntDetValFromBt(void *pBtcContext) { - struct btc_coexist *pBtCoexist=(struct btc_coexist *)pBtcContext; - PADAPTER Adapter=pBtCoexist->Adapter; - u4Byte coexSupportedFeature=0x0; + /* Always return 0 since we don't implement this yet */ +#if 0 + struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext; + PADAPTER Adapter = pBtCoexist->Adapter; + u1Byte AntDetVal = 0x0; u1Byte opcodeVer = 1; BOOLEAN status = false; + status = NDBG_GetAntDetValFromBt(Adapter, opcodeVer, &AntDetVal); + + RT_TRACE(COMP_DBG, DBG_LOUD, ("$$$ halbtcoutsrc_GetAntDetValFromBt(): status = %d, feature = %x\n", status, AntDetVal)); - return coexSupportedFeature; + return AntDetVal; +#else + return 0; +#endif } -u32 halbtcoutsrc_GetBtCoexSupportedVersion(void *pBtcContext) +u8 halbtcoutsrc_GetBleScanTypeFromBt(void *pBtcContext) +{ + PBTC_COEXIST pBtCoexist; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + u8 data = 0; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_GET_BT_BLE_SCAN_TYPE; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + data = *(u8 *)GLBtcBtMpRptRsp; + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return data; +} + +u32 halbtcoutsrc_GetBleScanParaFromBt(void *pBtcContext, u8 scanType) { - struct btc_coexist *pBtCoexist=(struct btc_coexist *)pBtcContext; - PADAPTER Adapter=pBtCoexist->Adapter; - u32 coexSupportedVersion=0x0; - u8 opcodeVer = 1; - u8 status = false; + PBTC_COEXIST pBtCoexist; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + u32 data = 0; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + - return coexSupportedVersion; -} + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_GET_BT_BLE_SCAN_PARA; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + data = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp); + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return data; +} + +u8 halbtcoutsrc_GetBtAFHMapFromBt(void *pBtcContext, u8 mapType, u8 *afhMap) +{ + struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext; + u8 buf[2] = {0}; + _irqL irqL; + u8 op_code; + u32 *AfhMapL = (u32 *)&(afhMap[0]); + u32 *AfhMapM = (u32 *)&(afhMap[4]); + u16 *AfhMapH = (u16 *)&(afhMap[8]); + u8 status; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _FALSE) + return _FALSE; + + buf[0] = 0; + buf[1] = mapType; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_LO_OP_GET_AFH_MAP_L; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + *AfhMapL = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp); + else { + ret = SET_BT_MP_OPER_RET(op_code, status); + goto exit; + } + + op_code = BT_LO_OP_GET_AFH_MAP_M; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + *AfhMapM = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp); + else { + ret = SET_BT_MP_OPER_RET(op_code, status); + goto exit; + } + + op_code = BT_LO_OP_GET_AFH_MAP_H; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + *AfhMapH = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp); + else { + ret = SET_BT_MP_OPER_RET(op_code, status); + goto exit; + } + +exit: + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + return (ret == BT_STATUS_BT_OP_SUCCESS) ? _TRUE : _FALSE; +} u32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext) { @@ -1934,6 +2214,31 @@ u32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext) return RELEASE_VERSION_8723D; #endif +#ifdef CONFIG_RTL8821C + return RELEASE_VERSION_8821C; +#endif +} + +void halbtcoutsrc_phydm_modify_RA_PCR_threshold(void *pBtcContext, u8 RA_offset_direction, u8 RA_threshold_offset) +{ + struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext; + +/* switch to #if 0 in case the phydm version does not provide the function */ +#if 1 + phydm_modify_RA_PCR_threshold(pBtCoexist->odm_priv, RA_offset_direction, RA_threshold_offset); +#endif +} + +u32 halbtcoutsrc_phydm_query_PHY_counter(void *pBtcContext, u8 info_type) +{ + struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext; + +/* switch to #if 0 in case the phydm version does not provide the function */ +#if 1 + return phydm_cmn_info_query((struct PHY_DM_STRUCT *)pBtCoexist->odm_priv, (enum phydm_info_query_e)info_type); +#else + return 0; +#endif } #if 0 @@ -1967,14 +2272,12 @@ static void BT_CoexOffloadC2hAckCheck(PADAPTER Adapter, u8 *tmpBuf, u8 length) gl_coex_offload.cnt_c2h_ack++; if (length < COL_C2H_ACK_HDR_LEN) { /* c2h ack length must >= 3 (status, opcode_ver, req_num and ret_len) */ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], invalid c2h ack length (%d)!!!\n", length)); gl_coex_offload.status[COL_STATUS_INVALID_C2H_LEN]++; } else { BT_PrintData(Adapter, "[COL], c2h ack:", length, tmpBuf); p_c2h_ack = (PCOL_C2H_ACK)tmpBuf; req_num = p_c2h_ack->req_num; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], req_num = %d!!!\n", req_num)); _rtw_memmove(&gl_coex_offload.c2h_ack_buf[req_num][0], tmpBuf, length); gl_coex_offload.c2h_ack_len[req_num] = length; @@ -1998,7 +2301,6 @@ static void BT_CoexOffloadC2hIndCheck(PADAPTER Adapter, u8 *tmpBuf, u8 length) gl_coex_offload.cnt_c2h_ind++; if (length < COL_C2H_IND_HDR_LEN) { /* c2h indication length must >= 3 (type, version and length) */ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], invalid c2h indication length (%d)!!!\n", length)); gl_coex_offload.c2h_ind_status[COL_STATUS_INVALID_C2H_LEN]++; } else { BT_PrintData(Adapter, "[COL], c2h indication:", length, tmpBuf); @@ -2007,8 +2309,6 @@ static void BT_CoexOffloadC2hIndCheck(PADAPTER Adapter, u8 *tmpBuf, u8 length) ind_type = p_c2h_ind->type; ind_version = p_c2h_ind->version; ind_length = p_c2h_ind->length; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], type/ version/ length = %d/ %d/ %d!!!\n", - ind_type, ind_version, ind_length)); _rtw_memmove(&gl_coex_offload.c2h_ind_buf[0], tmpBuf, length); gl_coex_offload.c2h_ind_len = length; @@ -2032,7 +2332,6 @@ void BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length) BT_PrintData(Adapter, "[COL], c2h packet:", Length - 2, Buffer + 2); c2hSubCmdId = (u1Byte)C2H_HDR_GET_C2H_SUB_CMD_ID(Buffer); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], c2hSubCmdId = 0x%x\n", c2hSubCmdId)); if (c2hSubCmdId == C2H_SUB_CMD_ID_H2C_ACK_HDR || c2hSubCmdId == C2H_SUB_CMD_ID_BT_COEX_INFO) { @@ -2040,10 +2339,8 @@ void BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length) /* coex c2h ack */ h2cCmdId = (u1Byte)H2C_ACK_HDR_GET_H2C_CMD_ID(Buffer); h2cSubCmdId = (u1Byte)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(Buffer); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], h2cCmdId/ h2cSubCmdId = 0x%x/ 0x%x\n", h2cCmdId, h2cSubCmdId)); if (h2cCmdId == 0xff && h2cSubCmdId == 0x60) { c2hAckLen = (u1Byte)C2H_HDR_GET_LEN(Buffer); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], c2hAckLen = 0x%x\n", c2hAckLen)); if (c2hAckLen >= 8) BT_CoexOffloadC2hAckCheck(Adapter, &Buffer[12], (u1Byte)(c2hAckLen - 8)); else @@ -2052,7 +2349,6 @@ void BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length) } else if (c2hSubCmdId == C2H_SUB_CMD_ID_BT_COEX_INFO) { /* coex c2h indication */ c2hIndLen = (u1Byte)C2H_HDR_GET_LEN(Buffer); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], c2hAckLen = 0x%x\n", c2hIndLen)); BT_CoexOffloadC2hIndCheck(Adapter, &Buffer[4], (u1Byte)c2hIndLen); } } @@ -2074,17 +2370,18 @@ u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter) else pBtCoexist->bBinded = _TRUE; - pBtCoexist->statistics.cntBind++; + pBtCoexist->statistics.cnt_bind++; pBtCoexist->Adapter = padapter; + pBtCoexist->odm_priv = (PVOID)&(pHalData->odmpriv); pBtCoexist->stack_info.profile_notified = _FALSE; - pBtCoexist->btInfo.bBtCtrlAggBufSize = _FALSE; - pBtCoexist->btInfo.aggBufSize = 5; + pBtCoexist->bt_info.bt_ctrl_agg_buf_size = _FALSE; + pBtCoexist->bt_info.agg_buf_size = 5; - pBtCoexist->btInfo.bIncreaseScanDevNum = _FALSE; - pBtCoexist->btInfo.bMiracastPlusBt = _FALSE; + pBtCoexist->bt_info.increase_scan_dev_num = _FALSE; + pBtCoexist->bt_info.miracast_plus_bt = _FALSE; antNum = rtw_btcoex_get_pg_ant_num((PADAPTER)padapter); EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_PG, antNum); @@ -2101,10 +2398,6 @@ u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter) pBtCoexist->board_info.btdm_ant_num_by_ant_det = 1; pBtCoexist->board_info.tfbga_package = rtw_btcoex_is_tfbga_package_type((PADAPTER)padapter); - if (pBtCoexist->board_info.tfbga_package) - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Package Type = TFBGA\n")); - else - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Package Type = Non-TFBGA\n")); pBtCoexist->board_info.rfe_type = rtw_btcoex_get_pg_rfe_type((PADAPTER)padapter); @@ -2158,15 +2451,20 @@ u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter) pBtCoexist->btc_get_bt_reg = halbtcoutsrc_GetBtReg; pBtCoexist->btc_set_bt_reg = halbtcoutsrc_SetBtReg; pBtCoexist->btc_set_bt_ant_detection = halbtcoutsrc_SetBtAntDetection; + pBtCoexist->btc_set_bt_trx_mask = halbtcoutsrc_SetBtTRXMASK; pBtCoexist->btc_coex_h2c_process = halbtcoutsrc_CoexH2cProcess; pBtCoexist->btc_get_bt_coex_supported_feature = halbtcoutsrc_GetBtCoexSupportedFeature; pBtCoexist->btc_get_bt_coex_supported_version= halbtcoutsrc_GetBtCoexSupportedVersion; + pBtCoexist->btc_get_ant_det_val_from_bt = halbtcoutsrc_GetAntDetValFromBt; + pBtCoexist->btc_get_ble_scan_type_from_bt = halbtcoutsrc_GetBleScanTypeFromBt; + pBtCoexist->btc_get_ble_scan_para_from_bt = halbtcoutsrc_GetBleScanParaFromBt; + pBtCoexist->btc_get_bt_afh_map_from_bt = halbtcoutsrc_GetBtAFHMapFromBt; pBtCoexist->btc_get_bt_phydm_version = halbtcoutsrc_GetPhydmVersion; + pBtCoexist->btc_phydm_modify_RA_PCR_threshold = halbtcoutsrc_phydm_modify_RA_PCR_threshold; + pBtCoexist->btc_phydm_query_PHY_counter = halbtcoutsrc_phydm_query_PHY_counter; pBtCoexist->cli_buf = &GLBtcDbgBuf[0]; - pBtCoexist->board_info.single_ant_path = 0; - GLBtcWiFiInScanState = _FALSE; GLBtcWiFiInIQKState = _FALSE; @@ -2180,7 +2478,7 @@ u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter) /* BT Control H2C/C2H*/ GLBtcBtMpOperSeq = 0; _rtw_mutex_init(&GLBtcBtMpOperLock); - _init_timer(&GLBtcBtMpOperTimer, ((PADAPTER)padapter)->pnetdev, _btmpoper_timer_hdl, pBtCoexist); + rtw_init_timer(&GLBtcBtMpOperTimer, padapter, _btmpoper_timer_hdl, pBtCoexist); _rtw_init_sema(&GLBtcBtMpRptSema, 0); GLBtcBtMpRptSeq = 0; GLBtcBtMpRptStatus = 0; @@ -2195,9 +2493,13 @@ u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter) void EXhalbtcoutsrc_PowerOnSetting(PBTC_COEXIST pBtCoexist) { + HAL_DATA_TYPE *pHalData = NULL; + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; + pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter); + /* Power on setting function is only added in 8723B currently */ if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) @@ -2213,9 +2515,18 @@ void EXhalbtcoutsrc_PowerOnSetting(PBTC_COEXIST pBtCoexist) ex_halbtc8723d1ant_power_on_setting(pBtCoexist); } - if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + if ((IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_power_on_setting(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_power_on_setting(pBtCoexist); + } + + if ((IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_power_on_setting(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_power_on_setting(pBtCoexist); } } @@ -2224,7 +2535,7 @@ void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist) if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntPreLoadFirmware++; + pBtCoexist->statistics.cnt_pre_load_firmware++; if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) @@ -2239,6 +2550,13 @@ void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist) else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_pre_load_firmware(pBtCoexist); } + + if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_pre_load_firmware(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_pre_load_firmware(pBtCoexist); + } } void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly) @@ -2246,12 +2564,15 @@ void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly) if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntInitHwConfig++; + pBtCoexist->statistics.cnt_init_hw_config++; if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_init_hw_config(pBtCoexist, bWifiOnly); - else if (pBtCoexist->board_info.btdm_ant_num == 2) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_init_hw_config(pBtCoexist, bWifiOnly); @@ -2281,6 +2602,21 @@ void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly) } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_init_hw_config(pBtCoexist, bWifiOnly); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_init_hw_config(pBtCoexist, bWifiOnly); + #ifdef CONFIG_FW_MULTI_PORT_SUPPORT + rtw_hal_set_default_port_id_cmd(pBtCoexist->Adapter, 0); + rtw_hal_set_wifi_port_id_cmd(pBtCoexist->Adapter); + #endif + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_init_hw_config(pBtCoexist, bWifiOnly); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_init_hw_config(pBtCoexist, bWifiOnly); + #ifdef CONFIG_FW_MULTI_PORT_SUPPORT + rtw_hal_set_default_port_id_cmd(pBtCoexist->Adapter, 0); + rtw_hal_set_wifi_port_id_cmd(pBtCoexist->Adapter); + #endif } } @@ -2289,12 +2625,15 @@ void EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist) if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntInitCoexDm++; + pBtCoexist->statistics.cnt_init_coex_dm++; if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_init_coex_dm(pBtCoexist); - else if (pBtCoexist->board_info.btdm_ant_num == 2) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_init_coex_dm(pBtCoexist); @@ -2324,6 +2663,13 @@ void EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist) } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_init_coex_dm(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_init_coex_dm(pBtCoexist); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_init_coex_dm(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_init_coex_dm(pBtCoexist); } pBtCoexist->initilized = _TRUE; @@ -2336,7 +2682,7 @@ void EXhalbtcoutsrc_ips_notify(PBTC_COEXIST pBtCoexist, u8 type) if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntIpsNotify++; + pBtCoexist->statistics.cnt_ips_notify++; if (pBtCoexist->manual_control) return; @@ -2352,9 +2698,12 @@ void EXhalbtcoutsrc_ips_notify(PBTC_COEXIST pBtCoexist, u8 type) * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_ips_notify(pBtCoexist, ipsType); - else if (pBtCoexist->board_info.btdm_ant_num == 2) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_ips_notify(pBtCoexist, ipsType); @@ -2384,6 +2733,13 @@ void EXhalbtcoutsrc_ips_notify(PBTC_COEXIST pBtCoexist, u8 type) } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_ips_notify(pBtCoexist, ipsType); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_ips_notify(pBtCoexist, ipsType); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_ips_notify(pBtCoexist, ipsType); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_ips_notify(pBtCoexist, ipsType); } /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ @@ -2397,7 +2753,7 @@ void EXhalbtcoutsrc_lps_notify(PBTC_COEXIST pBtCoexist, u8 type) if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntLpsNotify++; + pBtCoexist->statistics.cnt_lps_notify++; if (pBtCoexist->manual_control) return; @@ -2410,9 +2766,12 @@ void EXhalbtcoutsrc_lps_notify(PBTC_COEXIST pBtCoexist, u8 type) } if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_lps_notify(pBtCoexist, lpsType); - else if (pBtCoexist->board_info.btdm_ant_num == 2) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_lps_notify(pBtCoexist, lpsType); @@ -2442,6 +2801,13 @@ void EXhalbtcoutsrc_lps_notify(PBTC_COEXIST pBtCoexist, u8 type) } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_lps_notify(pBtCoexist, lpsType); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_lps_notify(pBtCoexist, lpsType); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_lps_notify(pBtCoexist, lpsType); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_lps_notify(pBtCoexist, lpsType); } } @@ -2451,7 +2817,7 @@ void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type) if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntScanNotify++; + pBtCoexist->statistics.cnt_scan_notify++; if (pBtCoexist->manual_control) return; @@ -2467,9 +2833,12 @@ void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type) * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_scan_notify(pBtCoexist, scanType); - else if (pBtCoexist->board_info.btdm_ant_num == 2) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_scan_notify(pBtCoexist, scanType); @@ -2499,18 +2868,55 @@ void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type) } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_scan_notify(pBtCoexist, scanType); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_scan_notify(pBtCoexist, scanType); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_scan_notify(pBtCoexist, scanType); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_scan_notify(pBtCoexist, scanType); } /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } +void EXhalbtcoutsrc_SetAntennaPathNotify(PBTC_COEXIST pBtCoexist, u8 type) +{ +#if 0 + u8 switchType; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + if (pBtCoexist->manual_control) + return; + + halbtcoutsrc_LeaveLowPower(pBtCoexist); + + switchType = type; + + if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8723b1ant_set_antenna_notify(pBtCoexist, type); + } + if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8723d1ant_set_antenna_notify(pBtCoexist, type); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8723d2ant_set_antenna_notify(pBtCoexist, type); + } + + halbtcoutsrc_NormalLowPower(pBtCoexist); +#endif +} + void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 action) { u8 assoType; if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntConnectNotify++; + pBtCoexist->statistics.cnt_connect_notify++; if (pBtCoexist->manual_control) return; @@ -2523,9 +2929,12 @@ void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 action) * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_connect_notify(pBtCoexist, assoType); - else if (pBtCoexist->board_info.btdm_ant_num == 2) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_connect_notify(pBtCoexist, assoType); @@ -2555,6 +2964,13 @@ void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 action) } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_connect_notify(pBtCoexist, assoType); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_connect_notify(pBtCoexist, assoType); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_connect_notify(pBtCoexist, assoType); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_connect_notify(pBtCoexist, assoType); } /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ @@ -2567,7 +2983,7 @@ void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntMediaStatusNotify++; + pBtCoexist->statistics.cnt_media_status_notify++; if (pBtCoexist->manual_control) return; @@ -2580,9 +2996,12 @@ void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_media_status_notify(pBtCoexist, mStatus); - else if (pBtCoexist->board_info.btdm_ant_num == 2) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_media_status_notify(pBtCoexist, mStatus); @@ -2612,6 +3031,13 @@ void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_media_status_notify(pBtCoexist, mStatus); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_media_status_notify(pBtCoexist, mStatus); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_media_status_notify(pBtCoexist, mStatus); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_media_status_notify(pBtCoexist, mStatus); } /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ @@ -2623,7 +3049,7 @@ void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType) if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntSpecificPacketNotify++; + pBtCoexist->statistics.cnt_specific_packet_notify++; if (pBtCoexist->manual_control) return; @@ -2642,9 +3068,12 @@ void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType) * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_specific_packet_notify(pBtCoexist, packetType); - else if (pBtCoexist->board_info.btdm_ant_num == 2) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_specific_packet_notify(pBtCoexist, packetType); @@ -2674,6 +3103,13 @@ void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType) } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_specific_packet_notify(pBtCoexist, packetType); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_specific_packet_notify(pBtCoexist, packetType); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_specific_packet_notify(pBtCoexist, packetType); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_specific_packet_notify(pBtCoexist, packetType); } /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ @@ -2684,15 +3120,18 @@ void EXhalbtcoutsrc_bt_info_notify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 lengt if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntBtInfoNotify++; + pBtCoexist->statistics.cnt_bt_info_notify++; /* All notify is called in cmd thread, don't need to leave low power again * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_bt_info_notify(pBtCoexist, tmpBuf, length); - else if (pBtCoexist->board_info.btdm_ant_num == 2) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_bt_info_notify(pBtCoexist, tmpBuf, length); @@ -2722,6 +3161,13 @@ void EXhalbtcoutsrc_bt_info_notify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 lengt } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_bt_info_notify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_bt_info_notify(pBtCoexist, tmpBuf, length); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_bt_info_notify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_bt_info_notify(pBtCoexist, tmpBuf, length); } /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ @@ -2735,7 +3181,7 @@ EXhalbtcoutsrc_RfStatusNotify( { if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntRfStatusNotify++; + pBtCoexist->statistics.cnt_rf_status_notify++; if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { @@ -2752,6 +3198,13 @@ EXhalbtcoutsrc_RfStatusNotify( } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_rf_status_notify(pBtCoexist, type); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_rf_status_notify(pBtCoexist, type); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_rf_status_notify(pBtCoexist, type); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_rf_status_notify(pBtCoexist, type); } } @@ -2787,9 +3240,12 @@ void EXhalbtcoutsrc_halt_notify(PBTC_COEXIST pBtCoexist) return; if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_halt_notify(pBtCoexist); - else if (pBtCoexist->board_info.btdm_ant_num == 2) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_halt_notify(pBtCoexist); @@ -2819,9 +3275,14 @@ void EXhalbtcoutsrc_halt_notify(PBTC_COEXIST pBtCoexist) } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_halt_notify(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_halt_notify(pBtCoexist); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_halt_notify(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_halt_notify(pBtCoexist); } - - pBtCoexist->bBinded = FALSE; } void EXhalbtcoutsrc_SwitchBtTRxMask(PBTC_COEXIST pBtCoexist) @@ -2859,9 +3320,12 @@ void EXhalbtcoutsrc_pnp_notify(PBTC_COEXIST pBtCoexist, u8 pnpState) else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_pnp_notify(pBtCoexist, pnpState); } else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_pnp_notify(pBtCoexist, pnpState); - else if (pBtCoexist->board_info.btdm_ant_num == 1) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_pnp_notify(pBtCoexist, pnpState); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_pnp_notify(pBtCoexist, pnpState); @@ -2874,27 +3338,21 @@ void EXhalbtcoutsrc_pnp_notify(PBTC_COEXIST pBtCoexist, u8 pnpState) } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_pnp_notify(pBtCoexist, pnpState); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_pnp_notify(pBtCoexist, pnpState); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_pnp_notify(pBtCoexist, pnpState); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_pnp_notify(pBtCoexist, pnpState); } } -void EXhalbtcoutsrc_ScoreBoardStatusNotify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 length) -{ -#if 0 - if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { - if (pBtCoexist->board_info.btdm_ant_num == 1) - ex_halbtc8703b1ant_ScoreBoardStatusNotify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { - if (pBtCoexist->board_info.btdm_ant_num == 1) - ;/*ex_halbtc8723d1ant_ScoreBoardStatusNotify(pBtCoexist, tmpBuf, length);*/ - } -#endif -} - void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist) { if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntCoexDmSwitch++; + pBtCoexist->statistics.cnt_coex_dm_switch++; halbtcoutsrc_LeaveLowPower(pBtCoexist); @@ -2925,16 +3383,19 @@ void EXhalbtcoutsrc_periodical(PBTC_COEXIST pBtCoexist) { if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntPeriodical++; + pBtCoexist->statistics.cnt_periodical++; /* Periodical should be called in cmd thread, */ /* don't need to leave low power again * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_periodical(pBtCoexist); - else if (pBtCoexist->board_info.btdm_ant_num == 2) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) { if (!halbtcoutsrc_UnderIps(pBtCoexist)) @@ -2966,6 +3427,13 @@ void EXhalbtcoutsrc_periodical(PBTC_COEXIST pBtCoexist) } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_periodical(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_periodical(pBtCoexist); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_periodical(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_periodical(pBtCoexist); } /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ @@ -2976,7 +3444,7 @@ void EXhalbtcoutsrc_dbg_control(PBTC_COEXIST pBtCoexist, u8 opCode, u8 opLen, u8 if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->statistics.cntDbgCtrl++; + pBtCoexist->statistics.cnt_dbg_ctrl++; /* This function doesn't be called yet, */ /* default no need to leave low power to avoid deadlock @@ -3102,8 +3570,8 @@ void EXhalbtcoutsrc_SetBtPatchVersion(u16 btHciVersion, u16 btPatchVersion) if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; - pBtCoexist->btInfo.btRealFwVer = btPatchVersion; - pBtCoexist->btInfo.btHciVer = btHciVersion; + pBtCoexist->bt_info.bt_real_fw_ver = btPatchVersion; + pBtCoexist->bt_info.bt_hci_ver = btHciVersion; } #if 0 @@ -3178,10 +3646,16 @@ void EXhalbtcoutsrc_DisplayBtCoexInfo(PBTC_COEXIST pBtCoexist) halbtcoutsrc_LeaveLowPower(pBtCoexist); + /* To prevent the racing with IPS enter */ + halbtcoutsrc_EnterPwrLock(pBtCoexist); + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#if 0 if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) ex_halbtc8821aCsr2ant_display_coex_info(pBtCoexist); - else if (pBtCoexist->board_info.btdm_ant_num == 2) + else +#endif + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_display_coex_info(pBtCoexist); @@ -3211,8 +3685,17 @@ void EXhalbtcoutsrc_DisplayBtCoexInfo(PBTC_COEXIST pBtCoexist) } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_display_coex_info(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_display_coex_info(pBtCoexist); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_display_coex_info(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_display_coex_info(pBtCoexist); } + halbtcoutsrc_ExitPwrLock(pBtCoexist); + halbtcoutsrc_NormalLowPower(pBtCoexist); } @@ -3226,19 +3709,22 @@ void EXhalbtcoutsrc_DisplayAntDetection(PBTC_COEXIST pBtCoexist) if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_display_ant_detection(pBtCoexist); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_display_ant_detection(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_display_ant_detection(pBtCoexist); } halbtcoutsrc_NormalLowPower(pBtCoexist); } -void EXhalbtcoutsrc_BTOffOnNotify(PBTC_COEXIST pBtCoexist, u8 bBTON) +void ex_halbtcoutsrc_pta_off_on_notify(PBTC_COEXIST pBtCoexist, u8 bBTON) { -#if 0 /* Jenyu Need commit to windows' SVN */ if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) - ex_halbtc8812a2ant_bt_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF); + ex_halbtc8812a2ant_pta_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF); } -#endif } void EXhalbtcoutsrc_set_rfe_type(u8 type) @@ -3246,6 +3732,18 @@ void EXhalbtcoutsrc_set_rfe_type(u8 type) GLBtCoexist.board_info.rfe_type= type; } +#ifdef CONFIG_RF4CE_COEXIST +void EXhalbtcoutsrc_set_rf4ce_link_state(u8 state) +{ + GLBtCoexist.rf4ce_info.link_state = state; +} + +u8 EXhalbtcoutsrc_get_rf4ce_link_state(void) +{ + return GLBtCoexist.rf4ce_info.link_state; +} +#endif + void EXhalbtcoutsrc_switchband_notify(struct btc_coexist *pBtCoexist, u8 type) { if(!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) @@ -3254,15 +3752,22 @@ void EXhalbtcoutsrc_switchband_notify(struct btc_coexist *pBtCoexist, u8 type) if(pBtCoexist->manual_control) return; - - halbtcoutsrc_LeaveLowPower(pBtCoexist); + /* Driver should guarantee that the HW status isn't in low power mode */ + /* halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if(IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if(pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_switchband_notify(pBtCoexist, type); + else if(pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8822b2ant_switchband_notify(pBtCoexist, type); + } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_switchband_notify(pBtCoexist, type); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_switchband_notify(pBtCoexist, type); } - halbtcoutsrc_NormalLowPower(pBtCoexist); + /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } static void halbt_init_hw_config92C(PADAPTER padapter) @@ -3348,7 +3853,7 @@ u8 hal_btcoex_IsBtDisabled(PADAPTER padapter) if (!hal_btcoex_IsBtExist(padapter)) return _TRUE; - if (GLBtCoexist.btInfo.bBtDisabled) + if (GLBtCoexist.bt_info.bt_disabled) return _TRUE; else return _FALSE; @@ -3392,6 +3897,14 @@ void hal_btcoex_PowerOnSetting(PADAPTER padapter) EXhalbtcoutsrc_PowerOnSetting(&GLBtCoexist); } +void hal_btcoex_PowerOffSetting(PADAPTER padapter) +{ + /* Clear the WiFi on/off bit in scoreboard reg. if necessary */ + if (IS_HARDWARE_TYPE_8703B(padapter) || IS_HARDWARE_TYPE_8723D(padapter) + || IS_HARDWARE_TYPE_8821C(padapter) || IS_HARDWARE_TYPE_8822B(padapter)) + rtw_write16(padapter, 0xaa, 0x8000); +} + void hal_btcoex_PreLoadFirmware(PADAPTER padapter) { EXhalbtcoutsrc_PreLoadFirmware(&GLBtCoexist); @@ -3478,7 +3991,7 @@ void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) } status = tmpBuf[1] & 0xF; - len = tmpBuf[1] >> 4; + len = length - 3; seq = tmpBuf[2] >> 4; GLBtcBtMpRptSeq = seq; @@ -3490,22 +4003,36 @@ void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state) { - if (state == 1) - state = BTC_WIFI_PNP_SLEEP; - else - state = BTC_WIFI_PNP_WAKE_UP; - - EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, state); + switch (state) { + case BTCOEX_SUSPEND_STATE_SUSPEND: + EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP); + break; + case BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT: + /* should switch to "#if 1" once all ICs' coex. revision are upgraded to support the KEEP_ANT case */ +#if 0 + EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT); +#else + EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP); + EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT); +#endif + break; + case BTCOEX_SUSPEND_STATE_RESUME: +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT + /* re-download FW after resume, inform WL FW port number */ + rtw_hal_set_wifi_port_id_cmd(GLBtCoexist.Adapter); +#endif + EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_WAKE_UP); + break; + } } -void hal_btcoex_HaltNotify(PADAPTER padapter) +void hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt) { - EXhalbtcoutsrc_halt_notify(&GLBtCoexist); -} + if (do_halt == 1) + EXhalbtcoutsrc_halt_notify(&GLBtCoexist); -void hal_btcoex_ScoreBoardStatusNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) -{ - EXhalbtcoutsrc_ScoreBoardStatusNotify(&GLBtCoexist, tmpBuf, length); + GLBtCoexist.bBinded = _FALSE; + GLBtCoexist.Adapter = NULL; } void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter) @@ -3515,22 +4042,29 @@ void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter) void hal_btcoex_Hanlder(PADAPTER padapter) { + u32 bt_patch_ver; + EXhalbtcoutsrc_periodical(&GLBtCoexist); + + if (GLBtCoexist.bt_info.bt_get_fw_ver == 0) { + GLBtCoexist.btc_get(&GLBtCoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + GLBtCoexist.bt_info.bt_get_fw_ver = bt_patch_ver; + } } s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter) { - return (s32)GLBtCoexist.btInfo.bRejectAggPkt; + return (s32)GLBtCoexist.bt_info.reject_agg_pkt; } s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter) { - return (s32)GLBtCoexist.btInfo.bBtCtrlAggBufSize; + return (s32)GLBtCoexist.bt_info.bt_ctrl_agg_buf_size; } u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter) { - return (u32)GLBtCoexist.btInfo.aggBufSize; + return (u32)GLBtCoexist.bt_info.agg_buf_size; } void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual) @@ -3557,10 +4091,10 @@ u8 hal_btcoex_IsBtControlLps(PADAPTER padapter) if (hal_btcoex_IsBtExist(padapter) == _FALSE) return _FALSE; - if (GLBtCoexist.btInfo.bBtDisabled) + if (GLBtCoexist.bt_info.bt_disabled) return _FALSE; - if (GLBtCoexist.btInfo.bBtCtrlLps) + if (GLBtCoexist.bt_info.bt_ctrl_lps) return _TRUE; return _FALSE; @@ -3574,10 +4108,10 @@ u8 hal_btcoex_IsLpsOn(PADAPTER padapter) if (hal_btcoex_IsBtExist(padapter) == _FALSE) return _FALSE; - if (GLBtCoexist.btInfo.bBtDisabled) + if (GLBtCoexist.bt_info.bt_disabled) return _FALSE; - if (GLBtCoexist.btInfo.bBtLpsOn) + if (GLBtCoexist.bt_info.bt_lps_on) return _TRUE; return _FALSE; @@ -3585,12 +4119,12 @@ u8 hal_btcoex_IsLpsOn(PADAPTER padapter) u8 hal_btcoex_RpwmVal(PADAPTER padapter) { - return GLBtCoexist.btInfo.rpwmVal; + return GLBtCoexist.bt_info.rpwm_val; } u8 hal_btcoex_LpsVal(PADAPTER padapter) { - return GLBtCoexist.btInfo.lpsVal; + return GLBtCoexist.bt_info.lps_val; } u32 hal_btcoex_GetRaMask(PADAPTER padapter) @@ -3598,7 +4132,7 @@ u32 hal_btcoex_GetRaMask(PADAPTER padapter) if (!hal_btcoex_IsBtExist(padapter)) return 0; - if (GLBtCoexist.btInfo.bBtDisabled) + if (GLBtCoexist.bt_info.bt_disabled) return 0; /* Modify by YiWei , suggest by Cosa and Jenyu @@ -3607,14 +4141,11 @@ u32 hal_btcoex_GetRaMask(PADAPTER padapter) /*if (GLBtCoexist.board_info.btdm_ant_num != 1) return 0;*/ - return GLBtCoexist.btInfo.raMask; + return GLBtCoexist.bt_info.ra_mask; } void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen) { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW write pwrModeCmd=0x%04x%08x\n", - pCmdBuf[0] << 8 | pCmdBuf[1], - pCmdBuf[2] << 24 | pCmdBuf[3] << 16 | pCmdBuf[4] << 8 | pCmdBuf[5])); _rtw_memcpy(GLBtCoexist.pwrModeVal, pCmdBuf, cmdLen); } @@ -3775,7 +4306,7 @@ u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER padapter) if (!hal_btcoex_IsBtExist(padapter)) return _FALSE; - if (GLBtCoexist.btInfo.bIncreaseScanDevNum) + if (GLBtCoexist.bt_info.increase_scan_dev_num) return _TRUE; return _FALSE; @@ -3804,9 +4335,9 @@ void hal_btcoex_StackUpdateProfileInfo(void) EXhalbtcoutsrc_StackUpdateProfileInfo(); } -void hal_btcoex_BTOffOnNotify(PADAPTER padapter, u8 bBTON) +void hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON) { - EXhalbtcoutsrc_BTOffOnNotify(&GLBtCoexist, bBTON); + ex_halbtcoutsrc_pta_off_on_notify(&GLBtCoexist, bBTON); } /* @@ -3956,9 +4487,7 @@ hal_btcoex_AntIsolationConfig_ParaFile( _rtw_memset(pHalData->para_file_buf , 0 , MAX_PARA_FILE_BUF_LEN); - - rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName); - + rtw_get_phy_file_path(Adapter, pFileName); if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); if (rlen > 0) @@ -3982,7 +4511,7 @@ u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data) halbtcoutsrc_LeaveLowPower(&GLBtCoexist); - ret = halbtcoutsrc_GetBtReg(&GLBtCoexist, type, addr, data); + ret = halbtcoutsrc_GetBtReg_with_status(&GLBtCoexist, type, addr, data); halbtcoutsrc_NormalLowPower(&GLBtCoexist); @@ -4006,6 +4535,19 @@ void hal_btcoex_set_rfe_type(u8 type) { EXhalbtcoutsrc_set_rfe_type(type); } + +#ifdef CONFIG_RF4CE_COEXIST +void hal_btcoex_set_rf4ce_link_state(u8 state) +{ + EXhalbtcoutsrc_set_rf4ce_link_state(state); +} + +u8 hal_btcoex_get_rf4ce_link_state(void) +{ + return EXhalbtcoutsrc_get_rf4ce_link_state(); +} +#endif /* CONFIG_RF4CE_COEXIST */ + void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type) { switch (band_type) { @@ -4013,7 +4555,7 @@ void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type) if (under_scan) EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G); else - EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G_NoForScan); + EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G_NOFORSCAN); break; case BAND_ON_5G: EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_5G); diff --git a/hal/hal_com.c b/hal/hal_com.c index 225804d..faf9617 100644 --- a/hal/hal_com.c +++ b/hal/hal_com.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_COM_C_ #include @@ -24,6 +19,24 @@ #include "hal_data.h" +#ifdef RTW_HALMAC +#include "../../hal/hal_halmac.h" +#endif + +void rtw_dump_fw_info(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = NULL; + + if (!adapter) + return; + + hal_data = GET_HAL_DATA(adapter); + if (hal_data->bFWReady) + RTW_PRINT_SEL(sel, "FW VER -%d.%d\n", hal_data->firmware_version, hal_data->firmware_sub_version); + else + RTW_PRINT_SEL(sel, "FW not ready\n"); +} + /* #define CONFIG_GTK_OL_DBG */ /*#define DBG_SEC_CAM_MOVE*/ @@ -174,19 +187,19 @@ void rtw_hal_config_rftype(PADAPTER padapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - if (IS_1T1R(pHalData->VersionID)) { + if (IS_1T1R(pHalData->version_id)) { pHalData->rf_type = RF_1T1R; pHalData->NumTotalRFPath = 1; - } else if (IS_2T2R(pHalData->VersionID)) { + } else if (IS_2T2R(pHalData->version_id)) { pHalData->rf_type = RF_2T2R; pHalData->NumTotalRFPath = 2; - } else if (IS_1T2R(pHalData->VersionID)) { + } else if (IS_1T2R(pHalData->version_id)) { pHalData->rf_type = RF_1T2R; pHalData->NumTotalRFPath = 2; - } else if (IS_3T3R(pHalData->VersionID)) { + } else if (IS_3T3R(pHalData->version_id)) { pHalData->rf_type = RF_3T3R; pHalData->NumTotalRFPath = 3; - } else if (IS_4T4R(pHalData->VersionID)) { + } else if (IS_4T4R(pHalData->version_id)) { pHalData->rf_type = RF_4T4R; pHalData->NumTotalRFPath = 4; } else { @@ -215,11 +228,8 @@ void rtw_hal_config_rftype(PADAPTER padapter) * def_chplan channel plan used when HW/SW both invalid * AutoLoadFail efuse autoload fail or not * - * Return: - * Final channel plan decision - * */ -u8 hal_com_config_channel_plan( +void hal_com_config_channel_plan( IN PADAPTER padapter, IN char *hw_alpha2, IN u8 hw_chplan, @@ -229,6 +239,7 @@ u8 hal_com_config_channel_plan( IN BOOLEAN AutoLoadFail ) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); PHAL_DATA_TYPE pHalData; u8 force_hw_chplan = _FALSE; int chplan = -1; @@ -302,10 +313,9 @@ u8 hal_com_config_channel_plan( } else RTW_PRINT("%s chplan:0x%02X\n", __func__, chplan); - padapter->mlmepriv.country_ent = country_ent; + rfctl->country_ent = country_ent; + rfctl->ChannelPlan = chplan; pHalData->bDisableSWChannelPlan = force_hw_chplan; - - return chplan; } BOOLEAN @@ -317,7 +327,7 @@ HAL_IsLegalChannel( BOOLEAN bLegalChannel = _TRUE; if (Channel > 14) { - if (IsSupported5G(Adapter->registrypriv.wireless_mode) == _FALSE) { + if (is_supported_5g(Adapter->registrypriv.wireless_mode) == _FALSE) { bLegalChannel = _FALSE; RTW_INFO("Channel > 14 but wireless_mode do not support 5G\n"); } @@ -600,7 +610,7 @@ u8 MRateToHwRate(u8 rate) return ret; } -u8 HwRateToMRate(u8 rate) +u8 hw_rate_to_m_rate(u8 rate) { u8 ret_rate = MGN_1M; @@ -860,7 +870,7 @@ u8 HwRateToMRate(u8 rate) break; default: - RTW_INFO("HwRateToMRate(): Non supported Rate [%x]!!!\n", rate); + RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate); break; } @@ -1100,6 +1110,12 @@ Hal_MappingOutPipe( } +void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid) +{ + if (padapter->hal_func.reqtxrpt) + padapter->hal_func.reqtxrpt(padapter, macid); +} + void rtw_hal_dump_macaddr(void *sel, _adapter *adapter) { int i; @@ -1149,32 +1165,31 @@ void rtw_init_hal_com_default_value(PADAPTER Adapter) struct registry_priv *regsty = adapter_to_regsty(Adapter); pHalData->AntDetection = 1; + pHalData->antenna_test = _FALSE; pHalData->u1ForcedIgiLb = regsty->force_igi_lb; -} + pHalData->RegIQKFWOffload = regsty->iqk_fw_offload; -/* -* C2H event format: -* Field TRIGGER CONTENT CMD_SEQ CMD_LEN CMD_ID -* BITS [127:120] [119:16] [15:8] [7:4] [3:0] -*/ +#ifdef CONFIG_CHNL_LOAD_MAGT + if (!pHalData->clm_period) + pHalData->clm_period = (SURVEY_TO - 5)*1000/4; /* CLM_period ; 4us per unit */ +#endif +} +#ifdef CONFIG_FW_C2H_REG void c2h_evt_clear(_adapter *adapter) { rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE); } -s32 c2h_evt_read(_adapter *adapter, u8 *buf) +s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf) { s32 ret = _FAIL; - struct c2h_evt_hdr *c2h_evt; int i; u8 trigger; if (buf == NULL) goto exit; -#if defined(CONFIG_RTL8188E) - trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR); if (trigger == C2H_EVT_HOST_CLOSE) { @@ -1183,27 +1198,23 @@ s32 c2h_evt_read(_adapter *adapter, u8 *buf) goto clear_evt; /* Not a valid value */ } - c2h_evt = (struct c2h_evt_hdr *)buf; - - _rtw_memset(c2h_evt, 0, 16); + _rtw_memset(buf, 0, C2H_REG_LEN); - *buf = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL); - *(buf + 1) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 1); - - RTW_DBG_DUMP("c2h_evt_read(): ", - &c2h_evt , sizeof(c2h_evt)); + /* Read ID, LEN, SEQ */ + SET_C2H_ID_88XX(buf, rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL)); + SET_C2H_SEQ_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX)); + SET_C2H_PLEN_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX)); if (0) { - RTW_INFO("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__ - , c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger); + RTW_INFO("%s id=0x%02x, seq=%u, plen=%u, trigger=0x%02x\n", __func__ + , C2H_ID_88XX(buf), C2H_SEQ_88XX(buf), C2H_PLEN_88XX(buf), trigger); } /* Read the content */ - for (i = 0; i < c2h_evt->plen; i++) - c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i); + for (i = 0; i < C2H_PLEN_88XX(buf); i++) + *(C2H_PAYLOAD_88XX(buf) + i) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i); - RTW_DBG_DUMP("c2h_evt_read(): Command Content:\n", - c2h_evt->payload, c2h_evt->plen); + RTW_DBG_DUMP("payload:\n", C2H_PAYLOAD_88XX(buf), C2H_PLEN_88XX(buf)); ret = _SUCCESS; @@ -1213,72 +1224,118 @@ s32 c2h_evt_read(_adapter *adapter, u8 *buf) * If this field isn't clear, the FW won't update the next command message. */ c2h_evt_clear(adapter); -#endif + exit: return ret; } +#endif /* CONFIG_FW_C2H_REG */ -/* -* C2H event format: -* Field TRIGGER CMD_LEN CONTENT CMD_SEQ CMD_ID -* BITS [127:120] [119:112] [111:16] [15:8] [7:0] -*/ -s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf) +#ifdef CONFIG_FW_C2H_PKT +#ifndef DBG_C2H_PKT_PRE_HDL +#define DBG_C2H_PKT_PRE_HDL 0 +#endif +#ifndef DBG_C2H_PKT_HDL +#define DBG_C2H_PKT_HDL 0 +#endif +void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len) { +#ifdef RTW_HALMAC + /* TODO: extract hal_mac IC's code here*/ +#else + u8 parse_fail = 0; + u8 hdl_here = 0; s32 ret = _FAIL; - struct c2h_evt_hdr_88xx *c2h_evt; - int i; - u8 trigger; + u8 id, seq, plen; + u8 *payload; - if (buf == NULL) + if (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) { + parse_fail = 1; goto exit; + } -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) \ - || defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8723B) \ - || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D) - - trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR); + hdl_here = rtw_hal_c2h_id_handle_directly(adapter, id, seq, plen, payload) == _TRUE ? 1 : 0; + if (hdl_here) + ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload); + else + ret = rtw_c2h_packet_wk_cmd(adapter, buf, len); - if (trigger == C2H_EVT_HOST_CLOSE) { - goto exit; /* Not ready */ - } else if (trigger != C2H_EVT_FW_CLOSE) { - goto clear_evt; /* Not a valid value */ +exit: + if (parse_fail) + RTW_ERR("%s parse fail, buf=%p, len=:%u\n", __func__, buf, len); + else if (ret != _SUCCESS || DBG_C2H_PKT_PRE_HDL > 0) { + RTW_PRINT("%s: id=0x%02x, seq=%u, plen=%u, %s %s\n", __func__, id, seq, plen + , hdl_here ? "handle" : "enqueue" + , ret == _SUCCESS ? "ok" : "fail" + ); + if (DBG_C2H_PKT_PRE_HDL >= 2) + RTW_PRINT_DUMP("dump: ", buf, len); } +#endif +} - c2h_evt = (struct c2h_evt_hdr_88xx *)buf; +void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len) +{ +#ifdef RTW_HALMAC + adapter->hal_func.hal_mac_c2h_handler(adapter, buf, len); +#else + u8 parse_fail = 0; + u8 bypass = 0; + s32 ret = _FAIL; + u8 id, seq, plen; + u8 *payload; - _rtw_memset(c2h_evt, 0, 16); + if (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) { + parse_fail = 1; + goto exit; + } - c2h_evt->id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL); - c2h_evt->seq = rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX); - c2h_evt->plen = rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX); +#ifdef CONFIG_WOWLAN + if (adapter_to_pwrctl(adapter)->wowlan_mode == _TRUE) { + bypass = 1; + ret = _SUCCESS; + goto exit; + } +#endif - RTW_DBG_DUMP("c2h_evt_read(): ", - &c2h_evt , sizeof(c2h_evt)); + ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload); - if (0) { - RTW_INFO("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__ - , c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger); +exit: + if (parse_fail) + RTW_ERR("%s parse fail, buf=%p, len=:%u\n", __func__, buf, len); + else if (ret != _SUCCESS || bypass || DBG_C2H_PKT_HDL > 0) { + RTW_PRINT("%s: id=0x%02x, seq=%u, plen=%u, %s %s\n", __func__, id, seq, plen + , !bypass ? "handle" : "bypass" + , ret == _SUCCESS ? "ok" : "fail" + ); + if (DBG_C2H_PKT_HDL >= 2) + RTW_PRINT_DUMP("dump: ", buf, len); } +#endif +} +#endif /* CONFIG_FW_C2H_PKT */ - /* Read the content */ - for (i = 0; i < c2h_evt->plen; i++) - c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i); +void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx; - RTW_DBG_DUMP("c2h_evt_read(): Command Content:\n", - c2h_evt->payload, c2h_evt->plen); + RTW_INFO("IQK offload finish in %dms\n", rtw_get_passing_time_ms(iqk_sctx->submit_time)); + if (0) + RTW_INFO_DUMP("C2H_IQK_FINISH: ", data, len); - ret = _SUCCESS; + rtw_sctx_done(&iqk_sctx); +} -clear_evt: - /* - * Clear event to notify FW we have read the command. - * If this field isn't clear, the FW won't update the next command message. - */ - c2h_evt_clear(adapter); -#endif -exit: - return ret; +int c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx; + + iqk_sctx->submit_time = rtw_get_current_time(); + iqk_sctx->timeout_ms = timeout_ms; + iqk_sctx->status = RTW_SCTX_SUBMITTED; + + return rtw_sctx_wait(iqk_sctx, __func__); } #define GET_C2H_MAC_HIDDEN_RPT_UUID_X(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 8) @@ -1286,7 +1343,8 @@ s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf) #define GET_C2H_MAC_HIDDEN_RPT_UUID_Z(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 5) #define GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(_data) LE_BITS_TO_2BYTE(((u8 *)(_data)) + 2, 5, 11) #define GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 4) -#define GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 4, 4) +#define GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 4, 3) +#define GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 7, 1) #define GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 4) #define GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 4, 4) #define GET_C2H_MAC_HIDDEN_RPT_BW(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 3) @@ -1295,9 +1353,10 @@ s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf) #define GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 6, 2) #ifndef DBG_C2H_MAC_HIDDEN_RPT_HANDLE - #define DBG_C2H_MAC_HIDDEN_RPT_HANDLE 0 +#define DBG_C2H_MAC_HIDDEN_RPT_HANDLE 0 #endif +#ifdef CONFIG_RTW_MAC_HIDDEN_RPT int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len) { HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); @@ -1312,6 +1371,7 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len) u8 hci_type; u8 package_type; + u8 tr_switch; u8 wl_func; u8 hw_stype; u8 bw; @@ -1334,6 +1394,8 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len) hci_type = GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(data); package_type = GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(data); + tr_switch = GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(data); + wl_func = GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(data); hw_stype = GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(data); @@ -1345,24 +1407,59 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len) if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) { for (i = 0; i < len; i++) - RTW_INFO("%s: 0x%02X\n", __func__, *(data + i)); + RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i)); - RTW_INFO("uuid x:0x%02x y:0x%02x z:0x%x crc:0x%x\n", uuid_x, uuid_y, uuid_z, uuid_crc); - RTW_INFO("hci_type:0x%x\n", hci_type); - RTW_INFO("package_type:0x%x\n", package_type); - RTW_INFO("wl_func:0x%x\n", wl_func); - RTW_INFO("hw_stype:0x%x\n", hw_stype); - RTW_INFO("bw:0x%x\n", bw); - RTW_INFO("ant_num:0x%x\n", ant_num); - RTW_INFO("protocol:0x%x\n", protocol); - RTW_INFO("nic:0x%x\n", nic); + RTW_PRINT("uuid x:0x%02x y:0x%02x z:0x%x crc:0x%x\n", uuid_x, uuid_y, uuid_z, uuid_crc); + RTW_PRINT("hci_type:0x%x\n", hci_type); + RTW_PRINT("package_type:0x%x\n", package_type); + RTW_PRINT("tr_switch:0x%x\n", tr_switch); + RTW_PRINT("wl_func:0x%x\n", wl_func); + RTW_PRINT("hw_stype:0x%x\n", hw_stype); + RTW_PRINT("bw:0x%x\n", bw); + RTW_PRINT("ant_num:0x%x\n", ant_num); + RTW_PRINT("protocol:0x%x\n", protocol); + RTW_PRINT("nic:0x%x\n", nic); } + /* + * NOTICE: + * for now, the following is common info/format + * if there is any hal difference need to export + * some IC dependent code will need to be implement + */ hal_data->PackageType = package_type; hal_spec->wl_func &= mac_hidden_wl_func_to_hal_wl_func(wl_func); hal_spec->bw_cap &= mac_hidden_max_bw_to_hal_bw_cap(bw); - hal_spec->nss_num = rtw_min(hal_spec->nss_num, ant_num); + hal_spec->tx_nss_num = rtw_min(hal_spec->tx_nss_num, ant_num); + hal_spec->rx_nss_num = rtw_min(hal_spec->rx_nss_num, ant_num); hal_spec->proto_cap &= mac_hidden_proto_to_hal_proto_cap(protocol); + hal_spec->hci_type = hci_type; + + /* TODO: tr_switch */ + + ret = _SUCCESS; + +exit: + return ret; +} + +int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + int ret = _FAIL; + + int i; + + if (len < MAC_HIDDEN_RPT_2_LEN) { + RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_2_LEN); + goto exit; + } + + if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) { + for (i = 0; i < len; i++) + RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i)); + } ret = _SUCCESS; @@ -1372,29 +1469,32 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len) int hal_read_mac_hidden_rpt(_adapter *adapter) { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); int ret = _FAIL; int ret_fwdl; - u8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN] = {0}; + u8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN] = {0}; u32 start = rtw_get_current_time(); u32 cnt = 0; u32 timeout_ms = 800; u32 min_cnt = 10; - u8 id = C2H_MAC_HIDDEN_RPT + 1; + u8 id = C2H_DEFEATURE_RSVD; int i; #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) u8 hci_type = rtw_get_intf_type(adapter); if ((hci_type == RTW_USB || hci_type == RTW_PCIE) - && !rtw_is_hw_init_completed(adapter)) + && !rtw_is_hw_init_completed(adapter)) rtw_hal_power_on(adapter); #endif - /* clear data ready */ - rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, id); + /* inform FW mac hidden rpt from reg is needed */ + rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DEFEATURE_RSVD); /* download FW */ + pHalData->not_xmitframe_fw_dl = 1; ret_fwdl = rtw_hal_fw_dl(adapter, _FALSE); + pHalData->not_xmitframe_fw_dl = 0; if (ret_fwdl != _SUCCESS) goto mac_hidden_rpt_hdl; @@ -1410,12 +1510,16 @@ int hal_read_mac_hidden_rpt(_adapter *adapter) if (id == C2H_MAC_HIDDEN_RPT) { /* read data */ - for (i = 0; i < MAC_HIDDEN_RPT_LEN; i++) + for (i = 0; i < MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN; i++) mac_hidden_rpt[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i); } + /* inform FW mac hidden rpt has read */ + rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DBG); + mac_hidden_rpt_hdl: c2h_mac_hidden_rpt_hdl(adapter, mac_hidden_rpt, MAC_HIDDEN_RPT_LEN); + c2h_mac_hidden_rpt_2_hdl(adapter, mac_hidden_rpt + MAC_HIDDEN_RPT_LEN, MAC_HIDDEN_RPT_2_LEN); if (ret_fwdl == _SUCCESS && id == C2H_MAC_HIDDEN_RPT) ret = _SUCCESS; @@ -1424,7 +1528,7 @@ int hal_read_mac_hidden_rpt(_adapter *adapter) #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) if ((hci_type == RTW_USB || hci_type == RTW_PCIE) - && !rtw_is_hw_init_completed(adapter)) + && !rtw_is_hw_init_completed(adapter)) rtw_hal_power_off(adapter); #endif @@ -1433,14 +1537,268 @@ int hal_read_mac_hidden_rpt(_adapter *adapter) return ret; } +#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */ + +int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + int ret = _FAIL; + + int i; + + if (len < DEFEATURE_DBG_LEN) { + RTW_WARN("%s len(%u) < %d\n", __func__, len, DEFEATURE_DBG_LEN); + goto exit; + } + + for (i = 0; i < len; i++) + RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i)); + + ret = _SUCCESS; + +exit: + return ret; +} + +#ifndef DBG_CUSTOMER_STR_RPT_HANDLE +#define DBG_CUSTOMER_STR_RPT_HANDLE 0 +#endif + +#ifdef CONFIG_RTW_CUSTOMER_STR +s32 rtw_hal_h2c_customer_str_req(_adapter *adapter) +{ + u8 h2c_data[H2C_CUSTOMER_STR_REQ_LEN] = {0}; + + SET_H2CCMD_CUSTOMER_STR_REQ_EN(h2c_data, 1); + return rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_REQ, H2C_CUSTOMER_STR_REQ_LEN, h2c_data); +} + +#define C2H_CUSTOMER_STR_RPT_BYTE0(_data) ((u8 *)(_data)) +#define C2H_CUSTOMER_STR_RPT_2_BYTE8(_data) ((u8 *)(_data)) + +int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + int ret = _FAIL; + int i; + + if (len < CUSTOMER_STR_RPT_LEN) { + RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_LEN); + goto exit; + } + + if (DBG_CUSTOMER_STR_RPT_HANDLE) + RTW_PRINT_DUMP("customer_str_rpt: ", data, CUSTOMER_STR_RPT_LEN); + + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + + if (dvobj->customer_str_sctx != NULL) { + if (dvobj->customer_str_sctx->status != RTW_SCTX_SUBMITTED) + RTW_WARN("%s invalid sctx.status:%d\n", __func__, dvobj->customer_str_sctx->status); + _rtw_memcpy(dvobj->customer_str, C2H_CUSTOMER_STR_RPT_BYTE0(data), CUSTOMER_STR_RPT_LEN); + dvobj->customer_str_sctx->status = RTX_SCTX_CSTR_WAIT_RPT2; + } else + RTW_WARN("%s sctx not set\n", __func__); + + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + + ret = _SUCCESS; + +exit: + return ret; +} + +int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + int ret = _FAIL; + int i; + + if (len < CUSTOMER_STR_RPT_2_LEN) { + RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_2_LEN); + goto exit; + } + + if (DBG_CUSTOMER_STR_RPT_HANDLE) + RTW_PRINT_DUMP("customer_str_rpt_2: ", data, CUSTOMER_STR_RPT_2_LEN); + + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + + if (dvobj->customer_str_sctx != NULL) { + if (dvobj->customer_str_sctx->status != RTX_SCTX_CSTR_WAIT_RPT2) + RTW_WARN("%s rpt not ready\n", __func__); + _rtw_memcpy(dvobj->customer_str + CUSTOMER_STR_RPT_LEN, C2H_CUSTOMER_STR_RPT_2_BYTE8(data), CUSTOMER_STR_RPT_2_LEN); + rtw_sctx_done(&dvobj->customer_str_sctx); + } else + RTW_WARN("%s sctx not set\n", __func__); + + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + + ret = _SUCCESS; + +exit: + return ret; +} + +/* read customer str */ +s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct submit_ctx sctx; + s32 ret = _SUCCESS; + + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + if (dvobj->customer_str_sctx != NULL) + ret = _FAIL; + else { + rtw_sctx_init(&sctx, 2 * 1000); + dvobj->customer_str_sctx = &sctx; + } + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + + if (ret == _FAIL) { + RTW_WARN("%s another handle ongoing\n", __func__); + goto exit; + } + + ret = rtw_customer_str_req_cmd(adapter); + if (ret != _SUCCESS) { + RTW_WARN("%s read cmd fail\n", __func__); + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + dvobj->customer_str_sctx = NULL; + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + goto exit; + } + + /* wait till rpt done or timeout */ + rtw_sctx_wait(&sctx, __func__); + + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + dvobj->customer_str_sctx = NULL; + if (sctx.status == RTW_SCTX_DONE_SUCCESS) + _rtw_memcpy(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN); + else + ret = _FAIL; + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + +exit: + return ret; +} + +s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs) +{ + u8 h2c_data_w1[H2C_CUSTOMER_STR_W1_LEN] = {0}; + u8 h2c_data_w2[H2C_CUSTOMER_STR_W2_LEN] = {0}; + u8 h2c_data_w3[H2C_CUSTOMER_STR_W3_LEN] = {0}; + s32 ret; + + SET_H2CCMD_CUSTOMER_STR_W1_EN(h2c_data_w1, 1); + _rtw_memcpy(H2CCMD_CUSTOMER_STR_W1_BYTE0(h2c_data_w1), cs, 6); + + SET_H2CCMD_CUSTOMER_STR_W2_EN(h2c_data_w2, 1); + _rtw_memcpy(H2CCMD_CUSTOMER_STR_W2_BYTE6(h2c_data_w2), cs + 6, 6); + + SET_H2CCMD_CUSTOMER_STR_W3_EN(h2c_data_w3, 1); + _rtw_memcpy(H2CCMD_CUSTOMER_STR_W3_BYTE12(h2c_data_w3), cs + 6 + 6, 4); + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W1, H2C_CUSTOMER_STR_W1_LEN, h2c_data_w1); + if (ret != _SUCCESS) { + RTW_WARN("%s w1 fail\n", __func__); + goto exit; + } + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W2, H2C_CUSTOMER_STR_W2_LEN, h2c_data_w2); + if (ret != _SUCCESS) { + RTW_WARN("%s w2 fail\n", __func__); + goto exit; + } + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W3, H2C_CUSTOMER_STR_W3_LEN, h2c_data_w3); + if (ret != _SUCCESS) { + RTW_WARN("%s w3 fail\n", __func__); + goto exit; + } + +exit: + return ret; +} + +/* write customer str and check if value reported is the same as requested */ +s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct submit_ctx sctx; + s32 ret = _SUCCESS; + + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + if (dvobj->customer_str_sctx != NULL) + ret = _FAIL; + else { + rtw_sctx_init(&sctx, 2 * 1000); + dvobj->customer_str_sctx = &sctx; + } + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + + if (ret == _FAIL) { + RTW_WARN("%s another handle ongoing\n", __func__); + goto exit; + } + + ret = rtw_customer_str_write_cmd(adapter, cs); + if (ret != _SUCCESS) { + RTW_WARN("%s write cmd fail\n", __func__); + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + dvobj->customer_str_sctx = NULL; + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + goto exit; + } + + ret = rtw_customer_str_req_cmd(adapter); + if (ret != _SUCCESS) { + RTW_WARN("%s read cmd fail\n", __func__); + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + dvobj->customer_str_sctx = NULL; + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + goto exit; + } + + /* wait till rpt done or timeout */ + rtw_sctx_wait(&sctx, __func__); + + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + dvobj->customer_str_sctx = NULL; + if (sctx.status == RTW_SCTX_DONE_SUCCESS) { + if (_rtw_memcmp(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN) != _TRUE) { + RTW_WARN("%s read back check fail\n", __func__); + RTW_INFO_DUMP("write req: ", cs, RTW_CUSTOMER_STR_LEN); + RTW_INFO_DUMP("read back: ", dvobj->customer_str, RTW_CUSTOMER_STR_LEN); + ret = _FAIL; + } + } else + ret = _FAIL; + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + +exit: + return ret; +} +#endif /* CONFIG_RTW_CUSTOMER_STR */ u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta) { +#ifdef CONFIG_GET_RAID_BY_DRV /*Just for 8188E now*/ if (IS_NEW_GENERATION_IC(adapter)) return networktype_to_raid_ex(adapter, psta); else return networktype_to_raid(adapter, psta); +#else + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + u8 bw; + bw = rtw_get_tx_bw_mode(adapter, psta); + + return phydm_rate_id_mapping(&pHalData->odmpriv, psta->wireless_mode, pHalData->rf_type, bw); +#endif } u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type) { @@ -1459,7 +1817,8 @@ u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type) void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta) { - u8 i, rf_type, limit; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + u8 i, rf_type, tx_nss; u64 tx_ra_bitmap; if (psta == NULL) @@ -1474,43 +1833,29 @@ void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta) } #ifdef CONFIG_80211N_HT + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); #ifdef CONFIG_80211AC_VHT - /* AC mode ra_bitmap */ - if (psta->vhtpriv.vht_option) - tx_ra_bitmap |= (rtw_vht_rate_to_bitmap(psta->vhtpriv.vht_mcs_map) << 12); - else + if (psta->vhtpriv.vht_option) { + /* AC mode ra_bitmap */ + tx_ra_bitmap |= (rtw_vht_mcs_map_to_bitmap(psta->vhtpriv.vht_mcs_map, tx_nss) << 12); + } else #endif /* CONFIG_80211AC_VHT */ - { + if (psta->htpriv.ht_option) { /* n mode ra_bitmap */ - if (psta->htpriv.ht_option) { - rf_type = RF_1T1R; - rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); - if (rf_type == RF_2T2R) - limit = 16; /* 2R */ - else if (rf_type == RF_3T3R) - limit = 24; /* 3R */ - else - limit = 8; /* 1R */ - - - /* Handling SMPS mode for AP MODE only*/ - if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { - /*0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/ - if (psta->htpriv.smps_cap == 0 || psta->htpriv.smps_cap == 1) { - /*operate with only one active receive chain // 11n-MCS rate <= MSC7*/ - limit = 8;/* 1R*/ - } - } - for (i = 0; i < limit; i++) { - if (psta->htpriv.ht_cap.supp_mcs_set[i / 8] & BIT(i % 8)) - tx_ra_bitmap |= BIT(i + 12); + /* Handling SMPS mode for AP MODE only*/ + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + /*0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/ + if (psta->htpriv.smps_cap == 0 || psta->htpriv.smps_cap == 1) { + /*operate with only one active receive chain // 11n-MCS rate <= MSC7*/ + tx_nss = rtw_min(tx_nss, 1); } } + + tx_ra_bitmap |= (rtw_ht_mcs_set_to_bitmap(psta->htpriv.ht_cap.supp_mcs_set, tx_nss) << 12); } #endif /* CONFIG_80211N_HT */ - RTW_INFO("supp_mcs_set = %02x, %02x, %02x, rf_type=%d, tx_ra_bitmap=%016llx\n" - , psta->htpriv.ht_cap.supp_mcs_set[0], psta->htpriv.ht_cap.supp_mcs_set[1], psta->htpriv.ht_cap.supp_mcs_set[2], rf_type, tx_ra_bitmap); psta->ra_mask = tx_ra_bitmap; psta->init_rate = get_highest_rate_idx(tx_ra_bitmap) & 0x3f; } @@ -1671,7 +2016,7 @@ void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) } #else - j = 5; + j = 7; #endif for (; j >= 0; j--) { @@ -1682,6 +2027,10 @@ void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) case 1: wdata = (mac[2] | (mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24)); break; + case 6: + case 7: + wdata = 0; + break; default: i = (j - 2) << 2; wdata = (key[i] | (key[i + 1] << 8) | (key[i + 2] << 16) | (key[i + 3] << 24)); @@ -1694,6 +2043,14 @@ void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) } } +void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id) +{ + u8 addr; + + addr = (id << 3); + rtw_sec_write_cam(adapter, addr, 0); +} + bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id) { bool res; @@ -2099,7 +2456,7 @@ void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr) u8 idx = 0; if ((check_fwstate(&adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) && - (adapter_to_dvobj(adapter)->iface_state.sta_num == 1)) { + (DEV_STA_NUM(adapter_to_dvobj(adapter)) == 1)) { for (idx = 0; idx < 6; idx++) rtw_write8(GET_PRIMARY_ADAPTER(adapter), (REG_MACID + idx), val[idx]); } else { @@ -2107,7 +2464,7 @@ void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr) u8 entry_id; if ((check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) && - (adapter_to_dvobj(adapter)->iface_state.ap_num == 1)) { + (DEV_AP_NUM(adapter_to_dvobj(adapter)) == 1)) { entry_id = 0; if (rtw_mbid_cam_assign(adapter, val, entry_id)) { RTW_INFO(FUNC_ADPT_FMT" Root AP assigned success\n", FUNC_ADPT_ARG(adapter)); @@ -2344,28 +2701,7 @@ void rtw_hal_set_msr(_adapter *adapter, u8 net_type) } } -void rtw_hal_port_reconfig(_adapter *adapter, u8 port) -{ -#ifdef CONFIG_CONCURRENT_MODE - u8 hal_port_num = 0; - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - - if (port > (hal_spec->port_num - 1)) { - RTW_INFO("[WARN] "ADPT_FMT"- hw_port : %d,will switch to invalid port-%d\n", - ADPT_ARG(adapter), adapter->hw_port, port); - rtw_warn_on(1); - } - - RTW_PRINT(ADPT_FMT"- hw_port : %d,will switch to port-%d\n", - ADPT_ARG(adapter), adapter->hw_port, port); - -#endif - -} - - -void hw_var_port_switch(_adapter *adapter) +void hw_var_port_switch(_adapter *adapter) { #ifdef CONFIG_CONCURRENT_MODE #ifdef CONFIG_RUNTIME_PORT_SWITCH @@ -2584,6 +2920,187 @@ const char *const _h2c_msr_role_str[] = { "INVALID", }; +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT +s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id) +{ + s32 ret = _SUCCESS; + u8 parm[H2C_DEFAULT_PORT_ID_LEN] = {0}; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + SET_H2CCMD_DFTPID_PORT_ID(parm, adapter->hw_port); + SET_H2CCMD_DFTPID_MAC_ID(parm, mac_id); + + RTW_DBG_DUMP("DFT port id parm:", parm, H2C_DEFAULT_PORT_ID_LEN); + RTW_INFO("%s port_id :%d, mad_id:%d\n", __func__, adapter->hw_port, mac_id); + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_DEFAULT_PORT_ID, H2C_DEFAULT_PORT_ID_LEN, parm); + dvobj->default_port_id = adapter->hw_port; + + return ret; +} +s32 rtw_set_default_port_id(_adapter *adapter) +{ + s32 ret = _SUCCESS; + struct sta_info *psta; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + if (adapter->hw_port == dvobj->default_port_id) + return ret; + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv)); + if (psta) + ret = rtw_hal_set_default_port_id_cmd(adapter, psta->mac_id); + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + + } else { + } + + return ret; +} +s32 rtw_set_ps_rsvd_page(_adapter *adapter) +{ + s32 ret = _SUCCESS; + u16 media_status_rpt = RT_MEDIA_CONNECT; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + if (adapter->hw_port == dvobj->default_port_id) + return ret; + + rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT, + (u8 *)&media_status_rpt); + + return ret; +} + +#endif + +#ifdef CONFIG_P2P_PS +#ifdef RTW_HALMAC +void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *psta; + HAL_P2P_PS_PARA p2p_ps_para; + int status = -1; + u8 i; + + _rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA)); + _rtw_memcpy((&p2p_ps_para), &hal->p2p_ps_offload, sizeof(hal->p2p_ps_offload)); + + (&p2p_ps_para)->p2p_port_id = adapter->hw_port; + (&p2p_ps_para)->p2p_group = 0; + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if (psta) { + (&p2p_ps_para)->p2p_macid = psta->mac_id; + } else { + if (p2p_ps_state != P2P_PS_DISABLE) { + RTW_ERR("%s , psta was NULL\n", __func__); + return; + } + } + + + switch (p2p_ps_state) { + case P2P_PS_DISABLE: + RTW_INFO("P2P_PS_DISABLE\n"); + _rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA)); + break; + + case P2P_PS_ENABLE: + RTW_INFO("P2P_PS_ENABLE\n"); + /* update CTWindow value. */ + if (pwdinfo->ctwindow > 0) { + (&p2p_ps_para)->ctwindow_en = 1; + (&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow; + /*RTW_INFO("%s , ctwindow_length = %d\n" , __func__ , (&p2p_ps_para)->ctwindow_length);*/ + } + + + if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) { + (&p2p_ps_para)->offload_en = 1; + if (pwdinfo->role == P2P_ROLE_GO) { + (&p2p_ps_para)->role = 1; + (&p2p_ps_para)->all_sta_sleep = 0; + } else + (&p2p_ps_para)->role = 0; + + (&p2p_ps_para)->discovery = 0; + } + /* hw only support 2 set of NoA */ + for (i = 0; i < pwdinfo->noa_num; i++) { + /* To control the register setting for which NOA */ + (&p2p_ps_para)->noa_sel = i; + (&p2p_ps_para)->noa_en = 1; + /* config P2P NoA Descriptor Register */ + /* config NOA duration */ + (&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[i]; + /* config NOA interval */ + (&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[i]; + /* config NOA start time */ + (&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[i]; + /* config NOA count */ + (&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[i]; + /*RTW_INFO("%s , noa_duration_para = %d , noa_interval_para = %d , noa_start_time_para = %d , noa_count_para = %d\n" , __func__ , + (&p2p_ps_para)->noa_duration_para , (&p2p_ps_para)->noa_interval_para , + (&p2p_ps_para)->noa_start_time_para , (&p2p_ps_para)->noa_count_para);*/ + status = rtw_halmac_p2pps(adapter_to_dvobj(adapter), (&p2p_ps_para)); + if (status == -1) + RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__); + } + + break; + + case P2P_PS_SCAN: + /*This feature FW not ready 20161116 YiWei*/ + return; + RTW_INFO("P2P_PS_SCAN\n"); + (&p2p_ps_para)->discovery = 1; + /* + (&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow; + (&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0]; + (&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0]; + (&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0]; + (&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0]; + */ + break; + + case P2P_PS_SCAN_DONE: + /*This feature FW not ready 20161116 YiWei*/ + return; + RTW_INFO("P2P_PS_SCAN_DONE\n"); + (&p2p_ps_para)->discovery = 0; + /* + pwdinfo->p2p_ps_state = P2P_PS_ENABLE; + (&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow; + (&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0]; + (&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0]; + (&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0]; + (&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0]; + */ + break; + + default: + break; + } + + if (p2p_ps_state != P2P_PS_ENABLE || (&p2p_ps_para)->noa_en == 0) { + status = rtw_halmac_p2pps(adapter_to_dvobj(adapter), (&p2p_ps_para)); + if (status == -1) + RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__); + } + _rtw_memcpy(&hal->p2p_ps_offload, (&p2p_ps_para), sizeof(hal->p2p_ps_offload)); + +} +#endif /* RTW_HALMAC */ +#endif /* CONFIG_P2P */ + /* * rtw_hal_set_FwMediaStatusRpt_cmd - * @@ -2610,30 +3127,15 @@ s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miraca SET_H2CCMD_MSRRPT_PARM_ROLE(parm, role); SET_H2CCMD_MSRRPT_PARM_MACID(parm, macid); SET_H2CCMD_MSRRPT_PARM_MACID_END(parm, macid_end); - - RTW_DBG_DUMP("MediaStatusRpt parm:", parm, H2C_MEDIA_STATUS_RPT_LEN); - -#ifdef CONFIG_DFS_MASTER - /* workaround for TXPAUSE cleared issue by FW's MediaStatusRpt handling */ - if (macid_ind == 0 && macid == 1) { - u8 parm0_bak = parm[0]; - - SET_H2CCMD_MSRRPT_PARM_MACID_IND(&parm0_bak, 0); - if (macid_ctl->h2c_msr[macid] == parm0_bak) { - ret = _SUCCESS; - goto post_action; - } - } +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT + SET_H2CCMD_MSRRPT_PARM_PORT_NUM(parm, adapter->hw_port); #endif + RTW_DBG_DUMP("MediaStatusRpt parm:", parm, H2C_MEDIA_STATUS_RPT_LEN); ret = rtw_hal_fill_h2c_cmd(adapter, H2C_MEDIA_STATUS_RPT, H2C_MEDIA_STATUS_RPT_LEN, parm); if (ret != _SUCCESS) goto exit; -#ifdef CONFIG_DFS_MASTER -post_action: -#endif - #if defined(CONFIG_RTL8188E) if (rtw_get_chip_type(adapter) == RTL8188E) { HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); @@ -2659,8 +3161,8 @@ s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miraca #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) /* TODO: this should move to IOT issue area */ if (rtw_get_chip_type(adapter) == RTL8812 - || rtw_get_chip_type(adapter) == RTL8821 - ) { + || rtw_get_chip_type(adapter) == RTL8821 + ) { if (MLME_IS_STA(adapter)) Hal_PatchwithJaguar_8812(adapter, opmode); } @@ -2670,8 +3172,17 @@ s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miraca if (macid_ind == 0) macid_end = macid; - for (i = macid; macid <= macid_end; macid++) + for (i = macid; macid <= macid_end; macid++) { rtw_macid_ctl_set_h2c_msr(macid_ctl, macid, parm[0]); + if (!opmode) { + rtw_macid_ctl_set_bw(macid_ctl, macid, CHANNEL_WIDTH_20); + rtw_macid_ctl_set_vht_en(macid_ctl, macid, 0); + rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, 0); + rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, 0); + } + } + if (!opmode) + rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter)); exit: return ret; @@ -2689,7 +3200,7 @@ inline s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode void rtw_hal_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) { - struct hal_ops *pHalFunc = &padapter->HalFunc; + struct hal_ops *pHalFunc = &padapter->hal_func; u8 u1H2CRsvdPageParm[H2C_RSVDPAGE_LOC_LEN] = {0}; u8 ret = 0; @@ -2714,12 +3225,17 @@ void rtw_hal_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) #ifdef CONFIG_GPIO_WAKEUP void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable) { + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + if (IS_8723D_SERIES(pHalData->version_id) || IS_8822B_SERIES(pHalData->version_id)) + rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable)); /* * Switch GPIO_13, GPIO_14 to wlan control, or pull GPIO_13,14 MUST fail. * It happended at 8723B/8192E/8821A. New IC will check multi function GPIO, * and implement HAL function. * TODO: GPIO_8 multi function? */ + if (index == 13 || index == 14) rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable)); } @@ -2780,37 +3296,52 @@ void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval) void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) { - struct hal_ops *pHalFunc = &padapter->HalFunc; + struct hal_ops *pHalFunc = &padapter->hal_func; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; u8 res = 0, count = 0, ret = 0; #ifdef CONFIG_WOWLAN u8 u1H2CAoacRsvdPageParm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0}; - RTW_INFO("AOACRsvdPageLoc: RWC=%d ArpRsp=%d NbrAdv=%d GtkRsp=%d GtkInfo=%d ProbeReq=%d NetworkList=%d\n", - rsvdpageloc->LocRemoteCtrlInfo, rsvdpageloc->LocArpRsp, - rsvdpageloc->LocNbrAdv, rsvdpageloc->LocGTKRsp, - rsvdpageloc->LocGTKInfo, rsvdpageloc->LocProbeReq, - rsvdpageloc->LocNetList); + RTW_INFO("%s: RWC: %d ArpRsp: %d NbrAdv: %d LocNDPInfo: %d\n", + __func__, rsvdpageloc->LocRemoteCtrlInfo, + rsvdpageloc->LocArpRsp, rsvdpageloc->LocNbrAdv, + rsvdpageloc->LocNDPInfo); + RTW_INFO("%s:GtkRsp: %d GtkInfo: %d ProbeReq: %d NetworkList: %d\n", + __func__, rsvdpageloc->LocGTKRsp, rsvdpageloc->LocGTKInfo, + rsvdpageloc->LocProbeReq, rsvdpageloc->LocNetList); if (check_fwstate(pmlmepriv, _FW_LINKED)) { SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocRemoteCtrlInfo); SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocArpRsp); - /* SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(u1H2CAoacRsvdPageParm, rsvdpageloc->LocNbrAdv); */ + SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(u1H2CAoacRsvdPageParm, + rsvdpageloc->LocNbrAdv); + SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(u1H2CAoacRsvdPageParm, + rsvdpageloc->LocNDPInfo); +#ifdef CONFIG_GTK_OL SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKRsp); SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKInfo); -#ifdef CONFIG_GTK_OL SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKEXTMEM); #endif /* CONFIG_GTK_OL */ ret = rtw_hal_fill_h2c_cmd(padapter, H2C_AOAC_RSVD_PAGE, H2C_AOAC_RSVDPAGE_LOC_LEN, u1H2CAoacRsvdPageParm); + + RTW_INFO("AOAC Report=%d\n", rsvdpageloc->LocAOACReport); + _rtw_memset(&u1H2CAoacRsvdPageParm, 0, sizeof(u1H2CAoacRsvdPageParm)); + SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(u1H2CAoacRsvdPageParm, + rsvdpageloc->LocAOACReport); + ret = rtw_hal_fill_h2c_cmd(padapter, + H2C_AOAC_RSVDPAGE3, + H2C_AOAC_RSVDPAGE_LOC_LEN, + u1H2CAoacRsvdPageParm); + pwrpriv->wowlan_aoac_rpt_loc = rsvdpageloc->LocAOACReport; } #ifdef CONFIG_PNO_SUPPORT else { - if (!pwrpriv->pno_in_resume) { + if (!pwrpriv->wowlan_in_resume) { RTW_INFO("NLO_INFO=%d\n", rsvdpageloc->LocPNOInfo); _rtw_memset(&u1H2CAoacRsvdPageParm, 0, sizeof(u1H2CAoacRsvdPageParm)); @@ -2826,6 +3357,125 @@ void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc #endif /* CONFIG_WOWLAN */ } +/*#define DBG_GET_RSVD_PAGE*/ +int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, + u32 page_num, u8 *buffer, u32 buffer_size) +{ + u32 addr = 0, size = 0, count = 0; + u32 page_size = 0, data_low = 0, data_high = 0; + u16 txbndy = 0, offset = 0; + u8 i = 0; + bool rst = _FALSE; + + rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); + + addr = page_offset * page_size; + size = page_num * page_size; + + if (buffer_size < size) { + RTW_ERR("%s buffer_size(%d) < get page total size(%d)\n", + __func__, buffer_size, size); + return rst; + } +#ifdef RTW_HALMAC + if (rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), 2, addr, size, buffer) < 0) + rst = _FALSE; + else + rst = _TRUE; +#else + txbndy = rtw_read8(adapter, REG_TDECTRL + 1); + + offset = (txbndy + page_offset) << 4; + count = (buffer_size / 8) + 1; + + rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x69); + + for (i = 0 ; i < count ; i++) { + rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, offset + i); + data_low = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L); + data_high = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H); + _rtw_memcpy(buffer + (i * 8), + &data_low, sizeof(data_low)); + _rtw_memcpy(buffer + ((i * 8) + 4), + &data_high, sizeof(data_high)); + } + rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x0); + rst = _TRUE; +#endif /*RTW_HALMAC*/ + +#ifdef DBG_GET_RSVD_PAGE + RTW_INFO("%s [page_offset:%d , page_num:%d][start_addr:0x%04x , size:%d]\n", + __func__, page_offset, page_num, addr, size); + RTW_INFO_DUMP("\n", buffer, size); + RTW_INFO(" ==================================================\n"); +#endif + return rst; +} + +void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num) +{ + u32 page_size = 0; + u8 *buffer = NULL; + u32 buf_size = 0; + + if (page_num == 0) + return; + + RTW_PRINT_SEL(sel, "======= RSVG PAGE DUMP =======\n"); + RTW_PRINT_SEL(sel, "page_offset:%d, page_num:%d\n", page_offset, page_num); + + rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); + if (page_size) { + buf_size = page_size * page_num; + buffer = rtw_zvmalloc(buf_size); + + if (buffer) { + rtw_hal_get_rsvd_page(adapter, page_offset, page_num, buffer, buf_size); + _RTW_DUMP_SEL(sel, buffer, buf_size); + rtw_vmfree(buffer, buf_size); + } else + RTW_PRINT_SEL(sel, "ERROR - rsvd_buf mem allocate failed\n"); + } else + RTW_PRINT_SEL(sel, "ERROR - Tx page size is zero ??\n"); + + RTW_PRINT_SEL(sel, "==========================\n"); +} + +#ifdef CONFIG_SUPPORT_FIFO_DUMP +void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size) +{ + u8 *buffer = NULL; + u8 buff_size = 0; + static const char * const fifo_sel_str[] = { + "TX", "RX", "RSVD_PAGE", "REPORT", "LLT", "RXBUF_FW" + }; + + if (fifo_sel > 5) { + RTW_ERR("fifo_sel:%d invalid\n", fifo_sel); + return; + } + + RTW_PRINT_SEL(sel, "========= FIFO DUMP =========\n"); + RTW_PRINT_SEL(sel, "%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[fifo_sel], fifo_addr, fifo_size); + + if (fifo_size) { + buff_size = RND4(fifo_size); + buffer = rtw_zvmalloc(buff_size); + if (buffer == NULL) + buff_size = 0; + } + + rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), fifo_sel, fifo_addr, buff_size, buffer); + + if (buffer) { + _RTW_DUMP_SEL(sel, buffer, fifo_size); + rtw_vmfree(buffer, buff_size); + } + + RTW_PRINT_SEL(sel, "==========================\n"); +} +#endif + #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) static void rtw_hal_force_enable_rxdma(_adapter *adapter) { @@ -2836,7 +3486,7 @@ static void rtw_hal_force_enable_rxdma(_adapter *adapter) rtw_write32(adapter, REG_RXPKT_NUM, (rtw_read32(adapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN))); } - +#if defined(CONFIG_RTL8188E) static void rtw_hal_disable_tx_report(_adapter *adapter) { rtw_write8(adapter, REG_TX_RPT_CTRL, @@ -2850,7 +3500,7 @@ static void rtw_hal_enable_tx_report(_adapter *adapter) ((rtw_read8(adapter, REG_TX_RPT_CTRL) | BIT(1))) | BIT(5)); RTW_INFO("enable TX_RPT:0x%02x\n", rtw_read8(adapter, REG_TX_RPT_CTRL)); } - +#endif static void rtw_hal_release_rx_dma(_adapter *adapter) { u32 val32 = 0; @@ -2865,9 +3515,9 @@ static void rtw_hal_release_rx_dma(_adapter *adapter) static u8 rtw_hal_pause_rx_dma(_adapter *adapter) { + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); u8 ret = 0; s8 trycnt = 100; - u16 len = 0; u32 tmp = 0; int res = 0; /* RX DMA stop */ @@ -2876,38 +3526,33 @@ static u8 rtw_hal_pause_rx_dma(_adapter *adapter) (rtw_read32(adapter, REG_RXPKT_NUM) | RW_RELEASE_EN)); do { if ((rtw_read32(adapter, REG_RXPKT_NUM) & RXDMA_IDLE)) { +#ifdef CONFIG_USB_HCI + /* stop interface before leave */ + if (_TRUE == hal->usb_intf_start) { + rtw_intf_stop(adapter); + RTW_ENABLE_FUNC(adapter, DF_RX_BIT); + RTW_ENABLE_FUNC(adapter, DF_TX_BIT); + } +#endif /* CONFIG_USB_HCI */ + RTW_PRINT("RX_DMA_IDLE is true\n"); ret = _SUCCESS; break; } #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) else { - /* If RX_DMA is not idle, receive one pkt from DMA */ - res = sdio_local_read(adapter, - SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp); - len = le16_to_cpu(tmp); - RTW_PRINT("RX len:%d\n", len); - - if (len > 0) - res = RecvOnePkt(adapter, len); - else - RTW_PRINT("read length fail %d\n", len); - + res = RecvOnePkt(adapter); RTW_PRINT("RecvOnePkt Result: %d\n", res); } #endif /* CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */ + #ifdef CONFIG_USB_HCI else { - rtw_intf_start(adapter); - - tmp = rtw_read32(adapter, REG_RXPKT_NUM) & RXDMA_IDLE; - if (tmp) { - rtw_intf_stop(adapter); - RTW_ENABLE_FUNC(adapter, DF_RX_BIT); - RTW_ENABLE_FUNC(adapter, DF_TX_BIT); - } + /* to avoid interface start repeatedly */ + if (_FALSE == hal->usb_intf_start) + rtw_intf_start(adapter); } -#endif +#endif /* CONFIG_USB_HCI */ } while (trycnt--); if (trycnt < 0) { @@ -2930,12 +3575,15 @@ static u8 rtw_hal_pause_rx_dma(_adapter *adapter) } #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +#ifndef RTW_HALMAC static u8 rtw_hal_enable_cpwm2(_adapter *adapter) { u8 ret = 0; int res = 0; u32 tmp = 0; - +#ifdef CONFIG_GPIO_WAKEUP + return _SUCCESS; +#else RTW_PRINT("%s\n", __func__); res = sdio_local_read(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp); @@ -2956,53 +3604,98 @@ static u8 rtw_hal_enable_cpwm2(_adapter *adapter) RTW_INFO("sdio_local_write fail\n"); ret = _FAIL; } - return ret; +#endif /* CONFIG_CPIO_WAKEUP */ } +#endif #endif /* CONFIG_SDIO_HCI, CONFIG_GSPI_HCI */ #endif /* CONFIG_WOWLAN || CONFIG_AP_WOWLAN */ #ifdef CONFIG_WOWLAN /* * rtw_hal_check_wow_ctrl - * chk_type: _TRUE means to check enable, if 0x690 & bit1, WOW enable successful - * _FALSE means to check disable, if 0x690 & bit1, WOW disable fail + * chk_type: _TRUE means to check enable, if 0x690 & bit1 (for 8051), WOW enable successful. + * If 0x1C7 == 0 (for 3081), WOW enable successful. + * _FALSE means to check disable, if 0x690 & bit1 (for 8051), WOW disable fail. + * If 0x120 & bit16 || 0x284 & bit18 (for 3081), WOW disable fail. */ static u8 rtw_hal_check_wow_ctrl(_adapter *adapter, u8 chk_type) { + u32 fe1_imr = 0xFF, rxpkt_num = 0xFF; u8 mstatus = 0; + u8 reason = 0xFF; u8 trycnt = 25; u8 res = _FALSE; - mstatus = rtw_read8(adapter, REG_WOW_CTRL); - RTW_INFO("%s mstatus:0x%02x\n", __func__, mstatus); + if (IS_HARDWARE_TYPE_JAGUAR2(adapter)) { + if (chk_type) { + reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON); + RTW_INFO("%s reason:0x%02x\n", __func__, reason); + + while (reason && trycnt > 1) { + reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON); + RTW_PRINT("Loop index: %d :0x%02x\n", + trycnt, reason); + trycnt--; + rtw_msleep_os(20); + } + if (!reason) + res = _TRUE; + else + res = _FALSE; + } else { + /* Wait FW to cleare 0x120 bit16, 0x284 bit18 to 0 */ + fe1_imr = rtw_read32(adapter, REG_FE1IMR); /* RxDone IMR for 3081 */ + rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM); /* Release RXDMA */ + RTW_PRINT("%s REG_FE1IMR (reg120): 0x%x, REG_RXPKT_NUM(reg284): 0x%x\n", __func__, fe1_imr, rxpkt_num); + + while (((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN)) && trycnt > 1) { + fe1_imr = rtw_read32(adapter, REG_FE1IMR); + rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM); + RTW_PRINT("Loop index: %d :0x%x, 0x%x\n", + trycnt, fe1_imr, rxpkt_num); + trycnt--; + rtw_msleep_os(20); + } - if (chk_type) { - while (!(mstatus & BIT1) && trycnt > 1) { - mstatus = rtw_read8(adapter, REG_WOW_CTRL); - RTW_PRINT("Loop index: %d :0x%02x\n", - trycnt, mstatus); - trycnt--; - rtw_msleep_os(20); + if ((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN)) + res = _FALSE; + else + res = _TRUE; } - if (mstatus & BIT1) - res = _TRUE; - else - res = _FALSE; } else { - while (mstatus & BIT1 && trycnt > 1) { - mstatus = rtw_read8(adapter, REG_WOW_CTRL); - RTW_PRINT("Loop index: %d :0x%02x\n", - trycnt, mstatus); - trycnt--; - rtw_msleep_os(20); - } + mstatus = rtw_read8(adapter, REG_WOW_CTRL); + RTW_INFO("%s mstatus:0x%02x\n", __func__, mstatus); - if (mstatus & BIT1) - res = _FALSE; - else - res = _TRUE; + + if (chk_type) { + while (!(mstatus & BIT1) && trycnt > 1) { + mstatus = rtw_read8(adapter, REG_WOW_CTRL); + RTW_PRINT("Loop index: %d :0x%02x\n", + trycnt, mstatus); + trycnt--; + rtw_msleep_os(20); + } + if (mstatus & BIT1) + res = _TRUE; + else + res = _FALSE; + } else { + while (mstatus & BIT1 && trycnt > 1) { + mstatus = rtw_read8(adapter, REG_WOW_CTRL); + RTW_PRINT("Loop index: %d :0x%02x\n", + trycnt, mstatus); + trycnt--; + rtw_msleep_os(20); + } + + if (mstatus & BIT1) + res = _FALSE; + else + res = _TRUE; + } } + RTW_PRINT("%s check_type: %d res: %d trycnt: %d\n", __func__, chk_type, res, (25 - trycnt)); return res; @@ -3015,7 +3708,7 @@ static u8 rtw_hal_check_pno_enabled(_adapter *adapter) u8 res = 0, count = 0; u8 ret = _FALSE; - if (ppwrpriv->wowlan_pno_enable && ppwrpriv->pno_in_resume == _FALSE) { + if (ppwrpriv->wowlan_pno_enable && ppwrpriv->wowlan_in_resume == _FALSE) { res = rtw_read8(adapter, REG_PNO_STATUS); while (!(res & BIT(7)) && count < 25) { RTW_INFO("[%d] cmd: 0x81 REG_PNO_STATUS: 0x%02x\n", @@ -3076,88 +3769,222 @@ static void rtw_hal_fw_sync_cam_id(_adapter *adapter) rtw_write8(adapter, REG_SECCFG, 0xcc); } + +static void rtw_dump_aoac_rpt(_adapter *adapter) +{ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; + + RTW_INFO_DUMP("[AOAC-RPT] IV -", paoac_rpt->iv, 8); + RTW_INFO_DUMP("[AOAC-RPT] Replay counter of EAPOL key - ", + paoac_rpt->replay_counter_eapol_key, 8); + RTW_INFO_DUMP("[AOAC-RPT] Group key - ", paoac_rpt->group_key, 32); + RTW_INFO("[AOAC-RPT] Key Index - %d\n", paoac_rpt->key_index); + RTW_INFO("[AOAC-RPT] Security Type - %d\n", paoac_rpt->security_type); +} + +static void rtw_hal_get_aoac_rpt(_adapter *adapter) +{ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; + u32 page_offset = 0, page_number = 0; + u32 page_size = 0, buf_size = 0; + u8 *buffer = NULL; + u8 i = 0, tmp = 0; + int ret = -1; + + /* read aoac report from rsvd page */ + page_offset = pwrctl->wowlan_aoac_rpt_loc; + page_number = 1; + + rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); + buf_size = page_size * page_number; + + buffer = rtw_zvmalloc(buf_size); + + if (NULL == buffer) { + RTW_ERR("%s buffer allocate failed size(%d)\n", + __func__, buf_size); + return; + } + + RTW_INFO("Get AOAC Report from rsvd page_offset:%d\n", page_offset); + + ret = rtw_hal_get_rsvd_page(adapter, page_offset, + page_number, buffer, buf_size); + + if (ret == _FALSE) { + RTW_ERR("%s get aoac report failed\n", __func__); + rtw_warn_on(1); + goto _exit; + } + + _rtw_memset(paoac_rpt, 0, sizeof(struct aoac_report)); + _rtw_memcpy(paoac_rpt, buffer, sizeof(struct aoac_report)); + + for (i = 0 ; i < 4 ; i++) { + tmp = paoac_rpt->replay_counter_eapol_key[i]; + paoac_rpt->replay_counter_eapol_key[i] = + paoac_rpt->replay_counter_eapol_key[7 - i]; + paoac_rpt->replay_counter_eapol_key[7 - i] = tmp; + } + + /* rtw_dump_aoac_rpt(adapter); */ + +_exit: + if (buffer) + rtw_vmfree(buffer, buf_size); +} + static void rtw_hal_update_gtk_offload_info(_adapter *adapter) { + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; struct security_priv *psecuritypriv = &adapter->securitypriv; struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; _irqL irqL; u8 get_key[16]; - u8 gtk_keyindex = 0; + u8 gtk_id = 0, offset = 0; + u64 replay_count = 0; if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) return; _rtw_memset(get_key, 0, sizeof(get_key)); + _rtw_memcpy(&replay_count, + paoac_rpt->replay_counter_eapol_key, 8); - if (psecuritypriv->binstallKCK_KEK == _TRUE) { + /*read gtk key index*/ + gtk_id = paoac_rpt->key_index; - /*read gtk key index*/ - gtk_keyindex = rtw_read8(adapter, 0x48c); - - if (gtk_keyindex > 4) { - RTW_INFO("%s [ERROR] gtk_keyindex:%d invalid\n", __func__, gtk_keyindex); - rtw_warn_on(1); - return; - } + if (gtk_id == 5 || gtk_id == 0) { + RTW_INFO("%s no rekey event happened.\n", __func__); + } else if (gtk_id > 0 && gtk_id < 4) { + RTW_INFO("%s update security key.\n", __func__); /*read key from sec-cam,for DK ,keyindex is equal to cam-id*/ - rtw_sec_read_cam_ent(adapter, gtk_keyindex, NULL, NULL, get_key); - - /*update key into related sw variable*/ - _enter_critical_bh(&cam_ctl->lock, &irqL); - if (_rtw_camid_is_gk(adapter, gtk_keyindex)) { - psecuritypriv->dot118021XGrpKeyid = gtk_keyindex; - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[gtk_keyindex].skey, get_key, 16); - _rtw_memcpy(&dvobj->cam_cache[gtk_keyindex].key, get_key, 16); + rtw_sec_read_cam_ent(adapter, gtk_id, + NULL, NULL, get_key); + rtw_clean_hw_dk_cam(adapter); + + if (_rtw_camid_is_gk(adapter, gtk_id)) { + _enter_critical_bh(&cam_ctl->lock, &irqL); + _rtw_memcpy(&dvobj->cam_cache[gtk_id].key, + get_key, 16); + _exit_critical_bh(&cam_ctl->lock, &irqL); + } else { + struct setkey_parm parm_gtk; + + parm_gtk.algorithm = paoac_rpt->security_type; + parm_gtk.keyid = gtk_id; + _rtw_memcpy(parm_gtk.key, get_key, 16); + setkey_hdl(adapter, (u8 *)&parm_gtk); } - _exit_critical_bh(&cam_ctl->lock, &irqL); - RTW_PRINT("GTK (%d) "KEY_FMT"\n", - gtk_keyindex, - KEY_ARG(psecuritypriv->dot118021XGrpKey[gtk_keyindex].skey)); + /*update key into related sw variable and sec-cam cache*/ + psecuritypriv->dot118021XGrpKeyid = gtk_id; + _rtw_memcpy(&psecuritypriv->dot118021XGrpKey[gtk_id], + get_key, 16); + /* update SW TKIP TX/RX MIC value */ + if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_) { + offset = RTW_KEK_LEN + RTW_TKIP_MIC_LEN; + _rtw_memcpy( + &psecuritypriv->dot118021XGrptxmickey[gtk_id], + &(paoac_rpt->group_key[offset]), + RTW_TKIP_MIC_LEN); + + offset = RTW_KEK_LEN; + _rtw_memcpy( + &psecuritypriv->dot118021XGrprxmickey[gtk_id], + &(paoac_rpt->group_key[offset]), + RTW_TKIP_MIC_LEN); + } - rtw_write8(adapter, REG_SECCFG, 0x0c); -#ifdef CONFIG_GTK_OL_DBG - /* if (gtk_keyindex != 5) */ - dump_sec_cam(RTW_DBGDUMP, adapter); -#endif + RTW_PRINT("GTK (%d) "KEY_FMT"\n", gtk_id, + KEY_ARG(psecuritypriv->dot118021XGrpKey[gtk_id].skey)); } + + rtw_clean_dk_section(adapter); + + rtw_write8(adapter, REG_SECCFG, 0x0c); + + #ifdef CONFIG_GTK_OL_DBG + /* if (gtk_keyindex != 5) */ + dump_sec_cam(RTW_DBGDUMP, adapter); + dump_sec_cam_cache(RTW_DBGDUMP, adapter); + #endif } -#endif static void rtw_hal_update_tx_iv(_adapter *adapter) { struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); - u64 iv_low = 0, iv_high = 0; - - /* 3.1 read fw iv */ - iv_low = rtw_read32(adapter, REG_TXPKTBUF_IV_LOW); - /* only low two bytes is PN, check AES_IV macro for detail */ - iv_low &= 0xffff; - iv_high = rtw_read32(adapter, REG_TXPKTBUF_IV_HIGH); - /* get the real packet number */ - pwrctl->wowlan_fw_iv = iv_high << 16 | iv_low; - RTW_PRINT("fw_iv: 0x%016llx\n", pwrctl->wowlan_fw_iv); + struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; + struct sta_info *psta; + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct security_priv *psecpriv = &adapter->securitypriv; + + u16 val16 = 0; + u32 val32 = 0; + u64 txiv = 0; + u8 *pval = NULL; + + psta = rtw_get_stainfo(&adapter->stapriv, + get_my_bssid(&pmlmeinfo->network)); + /* Update TX iv data. */ - rtw_set_sec_pn(adapter); + pval = (u8 *)&paoac_rpt->iv; + + if (psecpriv->dot11PrivacyAlgrthm == _TKIP_) { + val16 = ((u16)(paoac_rpt->iv[2]) << 0) + + ((u16)(paoac_rpt->iv[0]) << 8); + val32 = ((u32)(paoac_rpt->iv[4]) << 0) + + ((u32)(paoac_rpt->iv[5]) << 8) + + ((u32)(paoac_rpt->iv[6]) << 16) + + ((u32)(paoac_rpt->iv[7]) << 24); + } else if (psecpriv->dot11PrivacyAlgrthm == _AES_) { + val16 = ((u16)(paoac_rpt->iv[0]) << 0) + + ((u16)(paoac_rpt->iv[1]) << 8); + val32 = ((u32)(paoac_rpt->iv[4]) << 0) + + ((u32)(paoac_rpt->iv[5]) << 8) + + ((u32)(paoac_rpt->iv[6]) << 16) + + ((u32)(paoac_rpt->iv[7]) << 24); + } + + if (psta) { + txiv = val16 + ((u64)val32 << 16); + if (txiv != 0) + psta->dot11txpn.val = txiv; + } } +static void rtw_hal_update_sw_security_info(_adapter *adapter) +{ + rtw_hal_update_tx_iv(adapter); + rtw_hal_update_gtk_offload_info(adapter); +} +#endif /*CONFIG_GTK_OL*/ + static u8 rtw_hal_set_keep_alive_cmd(_adapter *adapter, u8 enable, u8 pkt_type) { - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; u8 u1H2CKeepAliveParm[H2C_KEEP_ALIVE_CTRL_LEN] = {0}; u8 adopt = 1, check_period = 5; u8 ret = _FAIL; - RTW_INFO("%s(): enable = %d\n", __func__, enable); SET_H2CCMD_KEEPALIVE_PARM_ENABLE(u1H2CKeepAliveParm, enable); SET_H2CCMD_KEEPALIVE_PARM_ADOPT(u1H2CKeepAliveParm, adopt); SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(u1H2CKeepAliveParm, pkt_type); SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(u1H2CKeepAliveParm, check_period); - - ret = rtw_hal_fill_h2c_cmd(adapter, +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT + SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(u1H2CKeepAliveParm, adapter->hw_port); + RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, adapter->hw_port); +#else + RTW_INFO("%s(): enable = %d\n", __func__, enable); +#endif + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_KEEP_ALIVE, H2C_KEEP_ALIVE_CTRL_LEN, u1H2CKeepAliveParm); @@ -3167,16 +3994,21 @@ static u8 rtw_hal_set_keep_alive_cmd(_adapter *adapter, u8 enable, u8 pkt_type) static u8 rtw_hal_set_disconnect_decision_cmd(_adapter *adapter, u8 enable) { - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; u8 u1H2CDisconDecisionParm[H2C_DISCON_DECISION_LEN] = {0}; u8 adopt = 1, check_period = 10, trypkt_num = 0; u8 ret = _FAIL; - RTW_INFO("%s(): enable = %d\n", __func__, enable); SET_H2CCMD_DISCONDECISION_PARM_ENABLE(u1H2CDisconDecisionParm, enable); SET_H2CCMD_DISCONDECISION_PARM_ADOPT(u1H2CDisconDecisionParm, adopt); SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(u1H2CDisconDecisionParm, check_period); SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(u1H2CDisconDecisionParm, trypkt_num); +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT + SET_H2CCMD_DISCONDECISION_PORT_NUM(u1H2CDisconDecisionParm, adapter->hw_port); + RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, adapter->hw_port); +#else + RTW_INFO("%s(): enable = %d\n", __func__, enable); +#endif ret = rtw_hal_fill_h2c_cmd(adapter, H2C_DISCON_DECISION, @@ -3189,7 +4021,7 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un { struct security_priv *psecpriv = &adapter->securitypriv; struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter); - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; u8 u1H2CWoWlanCtrlParm[H2C_WOWLAN_LEN] = {0}; u8 discont_wake = 1, gpionum = 0, gpio_dur = 0; @@ -3209,10 +4041,12 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un if (!ppwrpriv->wowlan_pno_enable) magic_pkt = enable; +#ifndef CONFIG_DEFAULT_PATTERNS_EN if (psecpriv->dot11PrivacyAlgrthm == _WEP40_ || psecpriv->dot11PrivacyAlgrthm == _WEP104_) hw_unicast = 1; else hw_unicast = 0; +#endif RTW_INFO("%s(): enable=%d change_unit=%d\n", __func__, enable, change_unit); @@ -3239,13 +4073,11 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un SET_H2CCMD_WOWLAN_GPIO_ACTIVE(u1H2CWoWlanCtrlParm, gpio_high_active); #ifdef CONFIG_GTK_OL - if (enable == _TRUE) { - /* GTK rekey only for AES, if GTK rekey is TKIP, then wake up*/ - if (psecpriv->dot118021XGrpPrivacy == _AES_) - SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 0); - else if (psecpriv->dot118021XGrpPrivacy == _TKIP_) - SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 1); - } + if (psecpriv->binstallKCK_KEK == _TRUE && + psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) + SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 0); + else + SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 1); #else SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, enable); #endif @@ -3268,7 +4100,7 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable) { - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; struct security_priv *psecuritypriv = &(adapter->securitypriv); struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter); struct registry_priv *pregistrypriv = &adapter->registrypriv; @@ -3284,16 +4116,22 @@ static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable) u1H2CRemoteWakeCtrlParm, 1); #ifdef CONFIG_GTK_OL if (psecuritypriv->binstallKCK_KEK == _TRUE && - psecuritypriv->dot11PrivacyAlgrthm == _AES_) { + psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) { SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN( u1H2CRemoteWakeCtrlParm, 1); } else { - RTW_INFO("no kck or security is not AES\n"); + RTW_INFO("no kck kek\n"); SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN( u1H2CRemoteWakeCtrlParm, 0); } #endif /* CONFIG_GTK_OL */ + if (ppwrpriv->wowlan_ns_offload_en == _TRUE) { + RTW_INFO("enable NS offload\n"); + SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN( + u1H2CRemoteWakeCtrlParm, enable); + } + if (pregistrypriv->default_patterns_en == _FALSE) { SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN( u1H2CRemoteWakeCtrlParm, enable); @@ -3307,7 +4145,8 @@ static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable) } if ((psecuritypriv->dot11PrivacyAlgrthm == _AES_) || - (psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_)) { + (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) || + (psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_)) { SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION( u1H2CRemoteWakeCtrlParm, 0); } else { @@ -3315,6 +4154,20 @@ static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable) u1H2CRemoteWakeCtrlParm, 1); } + if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_ && + psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) { + SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN( + u1H2CRemoteWakeCtrlParm, enable); + + if (IS_HARDWARE_TYPE_8188E(adapter) || + IS_HARDWARE_TYPE_8812(adapter)) { + SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN( + u1H2CRemoteWakeCtrlParm, 0); + SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION( + u1H2CRemoteWakeCtrlParm, 1); + } + } + SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP( u1H2CRemoteWakeCtrlParm, 1); } @@ -3347,7 +4200,7 @@ static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable) static u8 rtw_hal_set_global_info_cmd(_adapter *adapter, u8 group_alg, u8 pairwise_alg) { - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; u8 ret = _FAIL; u8 u1H2CAOACGlobalInfoParm[H2C_AOAC_GLOBAL_INFO_LEN] = {0}; @@ -3371,7 +4224,7 @@ static u8 rtw_hal_set_scan_offload_info_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc, u8 enable) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; u8 u1H2CScanOffloadInfoParm[H2C_SCAN_OFFLOAD_CTRL_LEN] = {0}; u8 res = 0, count = 0, ret = _FAIL; @@ -3409,7 +4262,6 @@ void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable) u8 ret = _SUCCESS; RTW_PRINT("+%s()+: enable=%d\n", __func__, enable); - _func_enter_; rtw_hal_set_wowlan_ctrl_cmd(padapter, enable, _FALSE); @@ -3446,7 +4298,6 @@ void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable) rtw_hal_set_remote_wake_ctrl_cmd(padapter, enable); } - _func_exit_; RTW_PRINT("-%s()-\n", __func__); } #endif /* CONFIG_WOWLAN */ @@ -3456,7 +4307,7 @@ static u8 rtw_hal_set_ap_wowlan_ctrl_cmd(_adapter *adapter, u8 enable) { struct security_priv *psecpriv = &adapter->securitypriv; struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter); - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; u8 u1H2CAPWoWlanCtrlParm[H2C_AP_WOW_GPIO_CTRL_LEN] = {0}; u8 gpionum = 0, gpio_dur = 0; @@ -3494,7 +4345,7 @@ static u8 rtw_hal_set_ap_wowlan_ctrl_cmd(_adapter *adapter, u8 enable) static u8 rtw_hal_set_ap_offload_ctrl_cmd(_adapter *adapter, u8 enable) { - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; u8 u1H2CAPOffloadCtrlParm[H2C_WOWLAN_LEN] = {0}; u8 ret = _FAIL; @@ -3512,7 +4363,7 @@ static u8 rtw_hal_set_ap_offload_ctrl_cmd(_adapter *adapter, u8 enable) static u8 rtw_hal_set_ap_ps_cmd(_adapter *adapter, u8 enable) { - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; u8 ap_ps_parm[H2C_AP_PS_LEN] = {0}; u8 ret = _FAIL; @@ -3538,7 +4389,7 @@ static u8 rtw_hal_set_ap_ps_cmd(_adapter *adapter, u8 enable) static void rtw_hal_set_ap_rsvdpage_loc_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) { - struct hal_ops *pHalFunc = &padapter->HalFunc; + struct hal_ops *pHalFunc = &padapter->hal_func; u8 rsvdparm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0}; u8 ret = _FAIL, header = 0; @@ -3591,8 +4442,9 @@ static void rtw_hal_ap_wow_enable(_adapter *padapter) struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); struct security_priv *psecuritypriv = &padapter->securitypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct hal_ops *pHalFunc = &padapter->HalFunc; + struct hal_ops *pHalFunc = &padapter->hal_func; struct sta_info *psta = NULL; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); #ifdef DBG_CHECK_FW_PS_STATE struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; @@ -3618,10 +4470,10 @@ static void rtw_hal_ap_wow_enable(_adapter *padapter) issue_beacon(padapter, 0); rtw_msleep_os(2); - + #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(padapter)) rtw_hal_disable_tx_report(padapter); - + #endif /* RX DMA stop */ res = rtw_hal_pause_rx_dma(padapter); if (res == _FAIL) @@ -3644,16 +4496,19 @@ static void rtw_hal_ap_wow_enable(_adapter *padapter) rtw_write8(padapter, REG_MCUTST_WOWLAN, 0); #ifdef CONFIG_USB_HCI rtw_mi_intf_stop(padapter); +#endif +#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) /* Invoid SE0 reset signal during suspending*/ rtw_write8(padapter, REG_RSV_CTRL, 0x20); - rtw_write8(padapter, REG_RSV_CTRL, 0x60); -#endif /*CONFIG_USB_HCI*/ + if (IS_8188F(pHalData->version_id) == FALSE) + rtw_write8(padapter, REG_RSV_CTRL, 0x60); +#endif } static void rtw_hal_ap_wow_disable(_adapter *padapter) { struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); - struct hal_ops *pHalFunc = &padapter->HalFunc; + struct hal_ops *pHalFunc = &padapter->hal_func; #ifdef DBG_CHECK_FW_PS_STATE struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; @@ -3678,8 +4533,10 @@ static void rtw_hal_ap_wow_disable(_adapter *padapter) } #endif /*DBG_CHECK_FW_PS_STATE*/ + #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(padapter)) rtw_hal_enable_tx_report(padapter); + #endif rtw_hal_force_enable_rxdma(padapter); @@ -3689,6 +4546,8 @@ static void rtw_hal_ap_wow_disable(_adapter *padapter) val8 = (pwrctl->is_high_active == 0) ? 1 : 0; RTW_PRINT("Set Wake GPIO to default(%d).\n", val8); rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8); + + rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _FALSE); #endif media_status_rpt = RT_MEDIA_CONNECT; @@ -3779,7 +4638,7 @@ static void rtw_hal_construct_P2PBeacon(_adapter *padapter, u8 *pframe, u32 *pLe SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); /* pmlmeext->mgnt_seq++; */ - SetFrameSubType(pframe, WIFI_BEACON); + set_frame_sub_type(pframe, WIFI_BEACON); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -3925,11 +4784,11 @@ static void rtw_hal_construct_P2PBeacon(_adapter *padapter, u8 *pframe, u32 *pLe pframe += len; pktlen += len; -#ifdef CONFIG_WFD + #ifdef CONFIG_WFD len = rtw_append_beacon_wfd_ie(padapter, pframe); pframe += len; pktlen += len; -#endif + #endif } #endif /* CONFIG_P2P */ @@ -4012,17 +4871,6 @@ static void rtw_hal_construct_P2PBeacon(_adapter *padapter, u8 *pframe, u32 *pLe #endif } -static int get_reg_classes_full_count(struct p2p_channels channel_list) -{ - int cnt = 0; - int i; - - for (i = 0; i < channel_list.reg_classes; i++) - cnt += channel_list.reg_class[i].channels; - - return cnt; -} - static void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength) { /* struct xmit_frame *pmgntframe; */ @@ -4069,7 +4917,7 @@ static void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *p _rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN); SetSeqNum(pwlanhdr, 0); - SetFrameSubType(fctrl, WIFI_PROBERSP); + set_frame_sub_type(fctrl, WIFI_PROBERSP); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); pframe += pktlen; @@ -4346,6 +5194,7 @@ static void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *p } static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pLength) { + struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; u8 action = P2P_PUB_ACTION_ACTION; u32 p2poui = cpu_to_be32(P2POUI); @@ -4391,7 +5240,7 @@ static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pL _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); SetSeqNum(pwlanhdr, 0); - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); pframe += pktlen; @@ -4572,7 +5421,7 @@ static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pL /* Intended P2P Interface Address */ /* Type: */ - p2pie[p2pielen++] = P2P_ATTR_INTENTED_IF_ADDR; + p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR; /* Length: */ *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN); @@ -4590,8 +5439,8 @@ static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pL /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ /* + number of channels in all classes */ len_channellist_attr = 3 - + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes - + get_reg_classes_full_count(pmlmeext->channel_list); + + (1 + 1) * (u16)ch_list->reg_classes + + get_reg_classes_full_count(ch_list); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_buddy_check_fwstate(padapter, _FW_LINKED)) @@ -4637,37 +5486,22 @@ static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pL /* Channel List */ p2pie[p2pielen++] = union_ch; - } else { - int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; - - /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; - - /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; - } - } -#else /* CONFIG_CONCURRENT_MODE */ + } else +#endif /* CONFIG_CONCURRENT_MODE */ { int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + for (j = 0; j < ch_list->reg_classes; j++) { /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + p2pie[p2pielen++] = ch_list->reg_class[j].channels; /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + for (i = 0; i < ch_list->reg_class[j].channels; i++) + p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; } } -#endif /* CONFIG_CONCURRENT_MODE */ - /* Device Info */ /* Type: */ @@ -4807,7 +5641,7 @@ static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 * _rtw_memset(pwlanhdr->addr3, 0, ETH_ALEN); SetSeqNum(pwlanhdr, 0); - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -4863,6 +5697,8 @@ static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 * /* due to defult value is FAIL INFO UNAVAILABLE, so the following IE is not needed */ #if 0 if (status_code == P2P_STATUS_SUCCESS) { + struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { /* The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */ /* In this case, the P2P Invitation response frame should carry the two more P2P attributes. */ @@ -4917,8 +5753,8 @@ static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 * /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ /* + number of channels in all classes */ len_channellist_attr = 3 - + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes - + get_reg_classes_full_count(pmlmeext->channel_list); + + (1 + 1) * (u16)ch_list->reg_classes + + get_reg_classes_full_count(ch_list); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED)) @@ -4964,36 +5800,22 @@ static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 * /* Channel List */ p2pie[p2pielen++] = union_ch; - } else { - int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; - - /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; - - /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; - } - } -#else /* CONFIG_CONCURRENT_MODE */ + } else +#endif /* CONFIG_CONCURRENT_MODE */ { int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + for (j = 0; j < ch_list->reg_classes; j++) { /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + p2pie[p2pielen++] = ch_list->reg_class[j].channels; /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + for (i = 0; i < ch_list->reg_class[j].channels; i++) + p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; } } -#endif /* CONFIG_CONCURRENT_MODE */ } #endif @@ -5062,7 +5884,7 @@ static void rtw_hal_construct_P2PProvisionDisRsp(_adapter *padapter, u8 *pframe, _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); SetSeqNum(pwlanhdr, 0); - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -5136,7 +5958,7 @@ static void rtw_hal_construct_P2PProvisionDisRsp(_adapter *padapter, u8 *pframe, u8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc) { u8 u1H2CP2PRsvdPageParm[H2C_P2PRSVDPAGE_LOC_LEN] = {0}; - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; u8 ret = _FAIL; RTW_INFO("P2PRsvdPageLoc: P2PBeacon=%d P2PProbeRsp=%d NegoRsp=%d InviteRsp=%d PDRsp=%d\n", @@ -5165,7 +5987,7 @@ u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter) u8 offload_cmd[H2C_P2P_OFFLOAD_LEN] = {0}; struct wifidirect_info *pwdinfo = &(adapter->wdinfo); struct P2P_WoWlan_Offload_t *p2p_wowlan_offload = (struct P2P_WoWlan_Offload_t *)offload_cmd; - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; u8 ret = _FAIL; _rtw_memset(p2p_wowlan_offload, 0 , sizeof(struct P2P_WoWlan_Offload_t)); @@ -5227,7 +6049,7 @@ static void rtw_hal_construct_beacon(_adapter *padapter, SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); /* pmlmeext->mgnt_seq++; */ - SetFrameSubType(pframe, WIFI_BEACON); + set_frame_sub_type(pframe, WIFI_BEACON); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -5317,10 +6139,10 @@ static void rtw_hal_construct_PSPoll(_adapter *padapter, fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; SetPwrMgt(fctrl); - SetFrameSubType(pframe, WIFI_PSPOLL); + set_frame_sub_type(pframe, WIFI_PSPOLL); /* AID. */ - SetDuration(pframe, (pmlmeinfo->aid | 0xc000)); + set_duration(pframe, (pmlmeinfo->aid | 0xc000)); /* BSSID. */ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); @@ -5385,7 +6207,7 @@ void rtw_hal_construct_NullFunctionData( if (bQoS == _TRUE) { struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; - SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); + set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe; SetPriority(&pwlanqoshdr->qc, AC); @@ -5393,7 +6215,7 @@ void rtw_hal_construct_NullFunctionData( pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); } else { - SetFrameSubType(pframe, WIFI_DATA_NULL); + set_frame_sub_type(pframe, WIFI_DATA_NULL); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); } @@ -5426,7 +6248,7 @@ void rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); SetSeqNum(pwlanhdr, 0); - SetFrameSubType(fctrl, WIFI_PROBERSP); + set_frame_sub_type(fctrl, WIFI_PROBERSP); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); pframe += pktlen; @@ -5442,6 +6264,52 @@ void rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, } #ifdef CONFIG_WOWLAN +static void rtw_hal_append_tkip_mic(PADAPTER padapter, + u8 *pframe, u32 offset) +{ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct rtw_ieee80211_hdr *pwlanhdr; + struct mic_data micdata; + struct sta_info *psta = NULL; + int res = 0; + + u8 *payload = (u8 *)(pframe + offset); + + u8 mic[8]; + u8 priority[4] = {0x0}; + u8 null_key[16] = {0x0}; + + RTW_INFO("%s(): Add MIC, offset: %d\n", __func__, offset); + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + psta = rtw_get_stainfo(&padapter->stapriv, + get_my_bssid(&(pmlmeinfo->network))); + if (psta != NULL) { + res = _rtw_memcmp(&psta->dot11tkiptxmickey.skey[0], + null_key, 16); + if (res == _TRUE) + RTW_INFO("%s(): STA dot11tkiptxmickey==0\n", __func__); + rtw_secmicsetkey(&micdata, &psta->dot11tkiptxmickey.skey[0]); + } + + rtw_secmicappend(&micdata, pwlanhdr->addr3, 6); /* DA */ + + rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); /* SA */ + + priority[0] = 0; + + rtw_secmicappend(&micdata, &priority[0], 4); + + rtw_secmicappend(&micdata, payload, 36); /* payload length = 8 + 28 */ + + rtw_secgetmic(&micdata, &(mic[0])); + + payload += 36; + + _rtw_memcpy(payload, &(mic[0]), 8); +} /* * Description: * Construct the ARP response packet to support ARP offload. @@ -5465,7 +6333,7 @@ static void rtw_hal_construct_ARPRsp( u8 *pARPRspPkt = pframe; /* for TKIP Cal MIC */ u8 *payload = pframe; - u8 EncryptionHeadOverhead = 0; + u8 EncryptionHeadOverhead = 0, arp_offset = 0; /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; @@ -5477,14 +6345,14 @@ static void rtw_hal_construct_ARPRsp( /* MAC Header. */ /* ------------------------------------------------------------------------- */ SetFrameType(fctrl, WIFI_DATA); - /* SetFrameSubType(fctrl, 0); */ + /* set_frame_sub_type(fctrl, 0); */ SetToDs(fctrl); _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); SetSeqNum(pwlanhdr, 0); - SetDuration(pwlanhdr, 0); + set_duration(pwlanhdr, 0); /* SET_80211_HDR_FRAME_CONTROL(pARPRspPkt, 0); */ /* SET_80211_HDR_TYPE_AND_SUBTYPE(pARPRspPkt, Type_Data); */ /* SET_80211_HDR_TO_DS(pARPRspPkt, 1); */ @@ -5529,7 +6397,8 @@ static void rtw_hal_construct_ARPRsp( /* ------------------------------------------------------------------------- */ /* Frame Body. */ /* ------------------------------------------------------------------------- */ - pARPRspPkt = (u8 *)(pframe + *pLength); + arp_offset = *pLength; + pARPRspPkt = (u8 *)(pframe + arp_offset); payload = pARPRspPkt; /* Get Payload pointer */ /* LLC header */ _rtw_memcpy(pARPRspPkt, ARPLLCHeader, 8); @@ -5564,45 +6433,191 @@ static void rtw_hal_construct_ARPRsp( *pLength += 28; if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) { - u8 mic[8]; - struct mic_data micdata; - struct sta_info *psta = NULL; - u8 priority[4] = {0x0, 0x0, 0x0, 0x0}; - u8 null_key[16] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + if (IS_HARDWARE_TYPE_8188E(padapter) || + IS_HARDWARE_TYPE_8812(padapter)) { + rtw_hal_append_tkip_mic(padapter, pframe, arp_offset); + } + *pLength += 8; + } +} - RTW_INFO("%s(): Add MIC\n", __FUNCTION__); +/* + * Description: Neighbor Discovery Offload. + */ +static void rtw_hal_construct_na_message(_adapter *padapter, + u8 *pframe, u32 *pLength) +{ + struct rtw_ieee80211_hdr *pwlanhdr = NULL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct security_priv *psecuritypriv = &padapter->securitypriv; - psta = rtw_get_stainfo(&padapter->stapriv, - get_my_bssid(&(pmlmeinfo->network))); - if (psta != NULL) { - if (_rtw_memcmp(&psta->dot11tkiptxmickey.skey[0], - null_key, 16) == _TRUE) { - RTW_INFO("%s(): STA dot11tkiptxmickey==0\n", - __func__); - } - /* start to calculate the mic code */ - rtw_secmicsetkey(&micdata, - &psta->dot11tkiptxmickey.skey[0]); - } + u32 pktlen = 0; + u16 *fctrl = NULL; + + u8 ns_hdr[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x86, 0xDD}; + u8 ipv6_info[4] = {0x60, 0x00, 0x00, 0x00}; + u8 ipv6_contx[4] = {0x00, 0x20, 0x3a, 0xff}; + u8 icmpv6_hdr[8] = {0x88, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00}; + u8 val8 = 0; + + u8 *p_na_msg = pframe; + /* for TKIP Cal MIC */ + u8 *payload = pframe; + u8 EncryptionHeadOverhead = 0, na_msg_offset = 0; + /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - rtw_secmicappend(&micdata, pwlanhdr->addr3, 6); /* DA */ + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; - rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); /* SA */ + /* ------------------------------------------------------------------------- */ + /* MAC Header. */ + /* ------------------------------------------------------------------------- */ + SetFrameType(fctrl, WIFI_DATA); + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, + get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, + adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, + get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - priority[0] = 0; + SetSeqNum(pwlanhdr, 0); + set_duration(pwlanhdr, 0); - rtw_secmicappend(&micdata, &priority[0], 4); +#ifdef CONFIG_WAPI_SUPPORT + *pLength = sMacHdrLng; +#else + *pLength = 24; +#endif + switch (psecuritypriv->dot11PrivacyAlgrthm) { + case _WEP40_: + case _WEP104_: + EncryptionHeadOverhead = 4; + break; + case _TKIP_: + EncryptionHeadOverhead = 8; + break; + case _AES_: + EncryptionHeadOverhead = 8; + break; +#ifdef CONFIG_WAPI_SUPPORT + case _SMS4_: + EncryptionHeadOverhead = 18; + break; +#endif + default: + EncryptionHeadOverhead = 0; + } - rtw_secmicappend(&micdata, payload, 36); /* payload length = 8 + 28 */ + if (EncryptionHeadOverhead > 0) { + _rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead); + *pLength += EncryptionHeadOverhead; + /* SET_80211_HDR_WEP(pARPRspPkt, 1); */ /* Suggested by CCW. */ + SetPrivacy(fctrl); + } - rtw_secgetmic(&micdata, &(mic[0])); + /* ------------------------------------------------------------------------- */ + /* Frame Body. */ + /* ------------------------------------------------------------------------- */ + na_msg_offset = *pLength; + p_na_msg = (u8 *)(pframe + na_msg_offset); + payload = p_na_msg; /* Get Payload pointer */ - pARPRspPkt += 28; - _rtw_memcpy(pARPRspPkt, &(mic[0]), 8); + /* LLC header */ + val8 = sizeof(ns_hdr); + _rtw_memcpy(p_na_msg, ns_hdr, val8); + *pLength += val8; + p_na_msg += val8; + + /* IPv6 Header */ + /* 1 . Information (4 bytes): 0x60 0x00 0x00 0x00 */ + val8 = sizeof(ipv6_info); + _rtw_memcpy(p_na_msg, ipv6_info, val8); + *pLength += val8; + p_na_msg += val8; + + /* 2 . playload : 0x00 0x20 , NextProt : 0x3a (ICMPv6) HopLim : 0xff */ + val8 = sizeof(ipv6_contx); + _rtw_memcpy(p_na_msg, ipv6_contx, val8); + *pLength += val8; + p_na_msg += val8; + + /* 3 . SA : 16 bytes , DA : 16 bytes ( Fw will filled ) */ + _rtw_memset(&(p_na_msg[*pLength]), 0, 32); + *pLength += 32; + p_na_msg += 32; + + /* ICMPv6 */ + /* 1. Type : 0x88 (NA) + * 2. Code : 0x00 + * 3. ChechSum : 0x00 0x00 (RSvd) + * 4. NAFlag: 0x60 0x00 0x00 0x00 ( Solicited , Override) + */ + val8 = sizeof(icmpv6_hdr); + _rtw_memcpy(p_na_msg, icmpv6_hdr, val8); + *pLength += val8; + p_na_msg += val8; + + /* TA: 16 bytes*/ + _rtw_memset(&(p_na_msg[*pLength]), 0, 16); + *pLength += 16; + p_na_msg += 16; + + /* ICMPv6 Target Link Layer Address */ + p_na_msg[0] = 0x02; /* type */ + p_na_msg[1] = 0x01; /* len 1 unit of 8 octes */ + *pLength += 2; + p_na_msg += 2; + + _rtw_memset(&(p_na_msg[*pLength]), 0, 6); + *pLength += 6; + p_na_msg += 6; + if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) { + if (IS_HARDWARE_TYPE_8188E(padapter) || + IS_HARDWARE_TYPE_8812(padapter)) { + rtw_hal_append_tkip_mic(padapter, pframe, + na_msg_offset); + } *pLength += 8; } } +/* + * Description: Neighbor Discovery Protocol Information. + */ +static void rtw_hal_construct_ndp_info(_adapter *padapter, + u8 *pframe, u32 *pLength) +{ + struct mlme_ext_priv *pmlmeext = NULL; + struct mlme_ext_info *pmlmeinfo = NULL; + struct rtw_ndp_info ndp_info; + u8 *pndp_info = pframe; + u8 len = sizeof(struct rtw_ndp_info); + + RTW_INFO("%s: len: %d\n", __func__, len); + + pmlmeext = &padapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + _rtw_memset(pframe, 0, len); + _rtw_memset(&ndp_info, 0, len); + + ndp_info.enable = 1; + ndp_info.check_remote_ip = 0; + ndp_info.num_of_target_ip = 1; + + _rtw_memcpy(&ndp_info.target_link_addr, adapter_mac_addr(padapter), + ETH_ALEN); + _rtw_memcpy(&ndp_info.target_ipv6_addr, pmlmeinfo->ip6_addr, + RTW_IPv6_ADDR_LEN); + + _rtw_memcpy(pndp_info, &ndp_info, len); +} #ifdef CONFIG_PNO_SUPPORT static void rtw_hal_construct_ProbeReq(_adapter *padapter, u8 *pframe, @@ -5632,7 +6647,7 @@ static void rtw_hal_construct_ProbeReq(_adapter *padapter, u8 *pframe, _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); SetSeqNum(pwlanhdr, 0); - SetFrameSubType(pframe, WIFI_PROBEREQ); + set_frame_sub_type(pframe, WIFI_PROBEREQ); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); pframe += pktlen; @@ -5811,7 +6826,7 @@ static void rtw_hal_construct_GTKRsp( /* MAC Header. */ /* ------------------------------------------------------------------------- */ SetFrameType(fctrl, WIFI_DATA); - /* SetFrameSubType(fctrl, 0); */ + /* set_frame_sub_type(fctrl, 0); */ SetToDs(fctrl); _rtw_memcpy(pwlanhdr->addr1, @@ -5824,7 +6839,7 @@ static void rtw_hal_construct_GTKRsp( get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); SetSeqNum(pwlanhdr, 0); - SetDuration(pwlanhdr, 0); + set_duration(pwlanhdr, 0); #ifdef CONFIG_WAPI_SUPPORT *pLength = sMacHdrLng; @@ -5873,6 +6888,11 @@ static void rtw_hal_construct_GTKRsp( /* GTK element */ pGTKRspPkt += 8; + /* GTK frame body after LLC, part 1 */ + /* TKIP key_length = 32, AES key_length = 16 */ + if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_) + GTKbody_a[8] = 0x20; + /* GTK frame body after LLC, part 1 */ _rtw_memcpy(pGTKRspPkt, GTKbody_a, 11); *pLength += 11; @@ -5882,6 +6902,8 @@ static void rtw_hal_construct_GTKRsp( *pLength += 88; pGTKRspPkt += 88; + if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_) + *pLength += 8; } #endif /* CONFIG_GTK_OL */ @@ -5894,15 +6916,15 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); struct mlme_ext_priv *pmlmeext; struct mlme_ext_info *pmlmeinfo; - u32 ARPLegnth = 0, GTKLegnth = 0, PNOLength = 0, ScanInfoLength = 0; - u32 SSIDLegnth = 0, ProbeReqLength = 0; + u32 ARPLength = 0, GTKLength = 0, PNOLength = 0, ScanInfoLength = 0; + u32 SSIDLegnth = 0, ProbeReqLength = 0, ns_len = 0; u8 CurtPktPageNum = 0; - u8 currentip[4]; u8 cur_dot11txpn[8]; #ifdef CONFIG_GTK_OL struct sta_priv *pstapriv = &adapter->stapriv; struct sta_info *psta; + struct security_priv *psecpriv = &adapter->securitypriv; u8 kek[RTW_KEK_LEN]; u8 kck[RTW_KCK_LEN]; #endif /* CONFIG_GTK_OL */ @@ -5916,25 +6938,52 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, if (pwrctl->wowlan_pno_enable == _FALSE) { /* ARP RSP * 1 page */ - rtw_get_current_ip_address(adapter, currentip); rsvd_page_loc->LocArpRsp = *page_num; RTW_INFO("LocArpRsp: %d\n", rsvd_page_loc->LocArpRsp); rtw_hal_construct_ARPRsp(adapter, &pframe[index], - &ARPLegnth, currentip); + &ARPLength, pmlmeinfo->ip_addr); rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc], - ARPLegnth, _FALSE, _FALSE, _TRUE); + ARPLength, _FALSE, _FALSE, _TRUE); - CurtPktPageNum = (u8)PageNum(tx_desc + ARPLegnth, page_size); + CurtPktPageNum = (u8)PageNum(tx_desc + ARPLength, page_size); *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + /* 2 NS offload and NDP Info*/ + if (pwrctl->wowlan_ns_offload_en == _TRUE) { + rsvd_page_loc->LocNbrAdv = *page_num; + RTW_INFO("LocNbrAdv: %d\n", rsvd_page_loc->LocNbrAdv); + rtw_hal_construct_na_message(adapter, + &pframe[index], &ns_len); + rtw_hal_fill_fake_txdesc(adapter, + &pframe[index - tx_desc], + ns_len, _FALSE, + _FALSE, _TRUE); + CurtPktPageNum = (u8)PageNum(tx_desc + ns_len, + page_size); + *page_num += CurtPktPageNum; + index += (CurtPktPageNum * page_size); + + rsvd_page_loc->LocNDPInfo = *page_num; + RTW_INFO("LocNDPInfo: %d\n", + rsvd_page_loc->LocNDPInfo); + + rtw_hal_construct_ndp_info(adapter, + &pframe[index - tx_desc], + &ns_len); + CurtPktPageNum = + (u8)PageNum(tx_desc + ns_len, page_size); + *page_num += CurtPktPageNum; + index += (CurtPktPageNum * page_size); + } + /* 3 SEC IV * 1 page */ rtw_get_sec_iv(adapter, cur_dot11txpn, get_my_bssid(&pmlmeinfo->network)); @@ -5969,27 +7018,19 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, rsvd_page_loc->LocGTKInfo = *page_num; RTW_INFO("LocGTKInfo: %d\n", rsvd_page_loc->LocGTKInfo); - if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8812(adapter)) { - struct security_priv *psecpriv = NULL; - - psecpriv = &adapter->securitypriv; - _rtw_memcpy(pframe + index - tx_desc, - &psecpriv->dot11PrivacyAlgrthm, 1); - _rtw_memcpy(pframe + index - tx_desc + 1, - &psecpriv->dot118021XGrpPrivacy, 1); - _rtw_memcpy(pframe + index - tx_desc + 2, - kck, RTW_KCK_LEN); - _rtw_memcpy(pframe + index - tx_desc + 2 + RTW_KCK_LEN, - kek, RTW_KEK_LEN); - CurtPktPageNum = (u8)PageNum(tx_desc + 2 + RTW_KCK_LEN + RTW_KEK_LEN, page_size); - } else { - _rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN); - _rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN, kek, RTW_KEK_LEN); - CurtPktPageNum = (u8)PageNum(tx_desc + RTW_KCK_LEN + RTW_KEK_LEN, page_size); - } - + _rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN); + _rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN, + kek, RTW_KEK_LEN); + GTKLength = tx_desc + RTW_KCK_LEN + RTW_KEK_LEN; + if (psta != NULL && + psecuritypriv->dot118021XGrpPrivacy == _TKIP_) { + _rtw_memcpy(pframe + index - tx_desc + 56, + &psta->dot11tkiptxmickey, RTW_TKIP_MIC_LEN); + GTKLength += RTW_TKIP_MIC_LEN; + } + CurtPktPageNum = (u8)PageNum(GTKLength, page_size); #if 0 { int i; @@ -6014,15 +7055,15 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, /* 3 GTK Response */ rsvd_page_loc->LocGTKRsp = *page_num; RTW_INFO("LocGTKRsp: %d\n", rsvd_page_loc->LocGTKRsp); - rtw_hal_construct_GTKRsp(adapter, &pframe[index], >KLegnth); + rtw_hal_construct_GTKRsp(adapter, &pframe[index], >KLength); rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc], - GTKLegnth, _FALSE, _FALSE, _TRUE); + GTKLength, _FALSE, _FALSE, _TRUE); #if 0 { int gj; printk("123GTK pkt=>\n"); - for (gj = 0; gj < GTKLegnth + tx_desc; gj++) { + for (gj = 0; gj < GTKLength + tx_desc; gj++) { printk(" %02x ", pframe[index - tx_desc + gj]); if ((gj + 1) % 16 == 0) printk("\n"); @@ -6032,10 +7073,10 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, RTW_INFO("%s(): HW_VAR_SET_TX_CMD: GTK RSP %p %d\n", __FUNCTION__, &pframe[index - tx_desc], - (tx_desc + GTKLegnth)); + (tx_desc + GTKLength)); #endif - CurtPktPageNum = (u8)PageNum(tx_desc + GTKLegnth, page_size); + CurtPktPageNum = (u8)PageNum(tx_desc + GTKLength, page_size); *page_num += CurtPktPageNum; @@ -6044,7 +7085,7 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, /* below page is empty for GTK extension memory */ /* 3(11) GTK EXT MEM */ rsvd_page_loc->LocGTKEXTMEM = *page_num; - + RTW_INFO("LocGTKEXTMEM: %d\n", rsvd_page_loc->LocGTKEXTMEM); CurtPktPageNum = 2; if (page_size >= 256) @@ -6053,11 +7094,18 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; /* extension memory for FW */ *total_pkt_len = index + (page_size * CurtPktPageNum); - #endif /* CONFIG_GTK_OL */ + + index += (CurtPktPageNum * page_size); + + /*Reserve 1 page for AOAC report*/ + rsvd_page_loc->LocAOACReport = *page_num; + RTW_INFO("LocAOACReport: %d\n", rsvd_page_loc->LocAOACReport); + *page_num += 1; + *total_pkt_len = index + (page_size * 1); } else { #ifdef CONFIG_PNO_SUPPORT - if (pwrctl->pno_in_resume == _FALSE && + if (pwrctl->wowlan_in_resume == _FALSE && pwrctl->pno_inited == _TRUE) { /* Broadcast Probe Request */ @@ -6130,7 +7178,6 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; *total_pkt_len = index + ScanInfoLength; index += (CurtPktPageNum * page_size); - } #endif /* CONFIG_PNO_SUPPORT */ } @@ -6179,80 +7226,49 @@ static void rtw_hal_reset_mac_rx(_adapter *adapter) RTW_INFO("0x%04x: %02x\n", REG_CR, rtw_read8(adapter, REG_CR)); } -static void rtw_hal_set_wow_rxff_boundary(_adapter *adapter, bool wow_mode) -{ - u8 val8 = 0; - u16 rxff_bndy = 0; - u32 rx_dma_buff_sz = 0; - - val8 = rtw_read8(adapter, REG_FIFOPAGE + 3); - if (val8 != 0) - RTW_INFO("%s:[%04x]some PKTs in TXPKTBUF\n", - __func__, (REG_FIFOPAGE + 3)); - - rtw_hal_reset_mac_rx(adapter); - - if (wow_mode) { - rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW, - (u8 *)&rx_dma_buff_sz); - rxff_bndy = rx_dma_buff_sz - 1; - - rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy); - RTW_INFO("%s: wow mode, 0x%04x: 0x%04x\n", __func__, - REG_TRXFF_BNDY + 2, - rtw_read16(adapter, (REG_TRXFF_BNDY + 2))); - } else { - rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ, - (u8 *)&rx_dma_buff_sz); - rxff_bndy = rx_dma_buff_sz - 1; - rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy); - RTW_INFO("%s: normal mode, 0x%04x: 0x%04x\n", __func__, - REG_TRXFF_BNDY + 2, - rtw_read16(adapter, (REG_TRXFF_BNDY + 2))); - } -} - -static int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern, - u8 len, u8 *mask, u8 idx) +static u8 rtw_hal_wow_pattern_generate(_adapter *adapter, u8 idx, struct rtl_wow_pattern *pwow_pattern) { struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); - struct mlme_ext_priv *pmlmeext = NULL; - struct mlme_ext_info *pmlmeinfo = NULL; - struct rtl_wow_pattern wow_pattern; + u8 *pattern; + u8 len = 0; + u8 *mask; + u8 mask_hw[MAX_WKFM_SIZE] = {0}; u8 content[MAX_WKFM_PATTERN_SIZE] = {0}; u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; u8 multicast_addr1[2] = {0x33, 0x33}; u8 multicast_addr2[3] = {0x01, 0x00, 0x5e}; - u8 res = _FALSE, index = 0, mask_len = 0; + u8 mask_len = 0; u8 mac_addr[ETH_ALEN] = {0}; u16 count = 0; int i, j; - if (pwrctl->wowlan_pattern_idx > MAX_WKFM_NUM) { + if (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) { RTW_INFO("%s pattern_idx is more than MAX_FMC_NUM: %d\n", - __func__, MAX_WKFM_NUM); - return _FALSE; + __func__, MAX_WKFM_CAM_NUM); + return _FAIL; } - pmlmeext = &adapter->mlmeextpriv; - pmlmeinfo = &pmlmeext->mlmext_info; + pattern = pwrctl->patterns[idx].content; + len = pwrctl->patterns[idx].len; + mask = pwrctl->patterns[idx].mask; + _rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN); - _rtw_memset(&wow_pattern, 0, sizeof(struct rtl_wow_pattern)); + _rtw_memset(pwow_pattern, 0, sizeof(struct rtl_wow_pattern)); mask_len = DIV_ROUND_UP(len, 8); /* 1. setup A1 table */ if (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0) - wow_pattern.type = PATTERN_BROADCAST; + pwow_pattern->type = PATTERN_BROADCAST; else if (memcmp(pattern, multicast_addr1, 2) == 0) - wow_pattern.type = PATTERN_MULTICAST; + pwow_pattern->type = PATTERN_MULTICAST; else if (memcmp(pattern, multicast_addr2, 3) == 0) - wow_pattern.type = PATTERN_MULTICAST; + pwow_pattern->type = PATTERN_MULTICAST; else if (memcmp(pattern, mac_addr, ETH_ALEN) == 0) - wow_pattern.type = PATTERN_UNICAST; + pwow_pattern->type = PATTERN_UNICAST; else - wow_pattern.type = PATTERN_INVALID; + pwow_pattern->type = PATTERN_INVALID; /* translate mask from os to mask for hw */ @@ -6287,10 +7303,10 @@ static int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern, mask_hw[0] &= 0xC0; for (i = 0; i < (MAX_WKFM_SIZE / 4); i++) { - wow_pattern.mask[i] = mask_hw[i * 4]; - wow_pattern.mask[i] |= (mask_hw[i * 4 + 1] << 8); - wow_pattern.mask[i] |= (mask_hw[i * 4 + 2] << 16); - wow_pattern.mask[i] |= (mask_hw[i * 4 + 3] << 24); + pwow_pattern->mask[i] = mask_hw[i * 4]; + pwow_pattern->mask[i] |= (mask_hw[i * 4 + 1] << 8); + pwow_pattern->mask[i] |= (mask_hw[i * 4 + 2] << 16); + pwow_pattern->mask[i] |= (mask_hw[i * 4 + 3] << 24); } /* To get the wake up pattern from the mask. @@ -6304,67 +7320,658 @@ static int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern, } } - wow_pattern.crc = rtw_calc_crc(content, count); + pwow_pattern->crc = rtw_calc_crc(content, count); + + if (pwow_pattern->crc != 0) { + if (pwow_pattern->type == PATTERN_INVALID) + pwow_pattern->type = PATTERN_VALID; + } + + return _SUCCESS; +} + +#ifndef CONFIG_WOW_PATTERN_HW_CAM +static void rtw_hal_set_wow_rxff_boundary(_adapter *adapter, bool wow_mode) +{ + u8 val8 = 0; + u16 rxff_bndy = 0; + u32 rx_dma_buff_sz = 0; + + val8 = rtw_read8(adapter, REG_FIFOPAGE + 3); + if (val8 != 0) + RTW_INFO("%s:[%04x]some PKTs in TXPKTBUF\n", + __func__, (REG_FIFOPAGE + 3)); + + rtw_hal_reset_mac_rx(adapter); + + if (wow_mode) { + rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW, + (u8 *)&rx_dma_buff_sz); + rxff_bndy = rx_dma_buff_sz - 1; + + rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy); + RTW_INFO("%s: wow mode, 0x%04x: 0x%04x\n", __func__, + REG_TRXFF_BNDY + 2, + rtw_read16(adapter, (REG_TRXFF_BNDY + 2))); + } else { + rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ, + (u8 *)&rx_dma_buff_sz); + rxff_bndy = rx_dma_buff_sz - 1; + rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy); + RTW_INFO("%s: normal mode, 0x%04x: 0x%04x\n", __func__, + REG_TRXFF_BNDY + 2, + rtw_read16(adapter, (REG_TRXFF_BNDY + 2))); + } +} + +bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx) +{ + u32 data_l = 0, data_h = 0, rx_dma_buff_sz = 0, page_sz = 0; + u16 offset, rx_buf_ptr = 0; + u16 cam_start_offset = 0; + u16 ctrl_l = 0, ctrl_h = 0; + u8 count = 0, tmp = 0; + int i = 0; + bool res = _TRUE; + + if (idx > MAX_WKFM_CAM_NUM) { + RTW_INFO("[Error]: %s, pattern index is out of range\n", + __func__); + return _FALSE; + } + + rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW, + (u8 *)&rx_dma_buff_sz); + + if (rx_dma_buff_sz == 0) { + RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__); + return _FALSE; + } + + rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz); + + if (page_sz == 0) { + RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__); + return _FALSE; + } + + offset = (u16)PageNum(rx_dma_buff_sz, page_sz); + cam_start_offset = offset * page_sz; + + ctrl_l = 0x0; + ctrl_h = 0x0; + + /* Enable RX packet buffer access */ + rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT); + + /* Read the WKFM CAM */ + for (i = 0; i < (WKFMCAM_ADDR_NUM / 2); i++) { + /* + * Set Rx packet buffer offset. + * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer. + * CAM start offset (unit: 1 byte) = Index*WKFMCAM_SIZE + * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8 + * * Index: The index of the wake up frame mask + * * WKFMCAM_SIZE: the total size of one WKFM CAM + * * per entry offset of a WKFM CAM: Addr i * 4 bytes + */ + rx_buf_ptr = + (cam_start_offset + idx * WKFMCAM_SIZE + i * 8) >> 3; + rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr); + + rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l); + data_l = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L); + data_h = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H); + + RTW_INFO("[%d]: %08x %08x\n", i, data_h, data_l); + + count = 0; + + do { + tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL); + rtw_udelay_os(2); + count++; + } while (!tmp && count < 100); + + if (count >= 100) { + RTW_INFO("%s count:%d\n", __func__, count); + res = _FALSE; + } + } + + /* Disable RX packet buffer access */ + rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, + DISABLE_TRXPKT_BUF_ACCESS); + return res; +} + +bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx, + struct rtl_wow_pattern *context) +{ + u32 data = 0, rx_dma_buff_sz = 0, page_sz = 0; + u16 offset, rx_buf_ptr = 0; + u16 cam_start_offset = 0; + u16 ctrl_l = 0, ctrl_h = 0; + u8 count = 0, tmp = 0; + int res = 0, i = 0; + + if (idx > MAX_WKFM_CAM_NUM) { + RTW_INFO("[Error]: %s, pattern index is out of range\n", + __func__); + return _FALSE; + } + + rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW, + (u8 *)&rx_dma_buff_sz); + + if (rx_dma_buff_sz == 0) { + RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__); + return _FALSE; + } + + rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz); + + if (page_sz == 0) { + RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__); + return _FALSE; + } + + offset = (u16)PageNum(rx_dma_buff_sz, page_sz); + + cam_start_offset = offset * page_sz; + + if (IS_HARDWARE_TYPE_8188E(adapter)) { + ctrl_l = 0x0001; + ctrl_h = 0x0001; + } else { + ctrl_l = 0x0f01; + ctrl_h = 0xf001; + } + + /* Enable RX packet buffer access */ + rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT); + + /* Write the WKFM CAM */ + for (i = 0; i < WKFMCAM_ADDR_NUM; i++) { + /* + * Set Rx packet buffer offset. + * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer. + * CAM start offset (unit: 1 byte) = Index*WKFMCAM_SIZE + * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8 + * * Index: The index of the wake up frame mask + * * WKFMCAM_SIZE: the total size of one WKFM CAM + * * per entry offset of a WKFM CAM: Addr i * 4 bytes + */ + rx_buf_ptr = + (cam_start_offset + idx * WKFMCAM_SIZE + i * 4) >> 3; + rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr); + + if (i == 0) { + if (context->type == PATTERN_VALID) + data = BIT(31); + else if (context->type == PATTERN_BROADCAST) + data = BIT(31) | BIT(26); + else if (context->type == PATTERN_MULTICAST) + data = BIT(31) | BIT(25); + else if (context->type == PATTERN_UNICAST) + data = BIT(31) | BIT(24); + + if (context->crc != 0) + data |= context->crc; + + rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data); + rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l); + } else if (i == 1) { + data = 0; + rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data); + rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h); + } else if (i == 2 || i == 4) { + data = context->mask[i - 2]; + rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data); + /* write to RX packet buffer*/ + rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l); + } else if (i == 3 || i == 5) { + data = context->mask[i - 2]; + rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data); + /* write to RX packet buffer*/ + rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h); + } + + count = 0; + do { + tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL); + rtw_udelay_os(2); + count++; + } while (tmp && count < 100); + + if (count >= 100) + res = _FALSE; + else + res = _TRUE; + } + + /* Disable RX packet buffer access */ + rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, + DISABLE_TRXPKT_BUF_ACCESS); + + return res; +} +void rtw_clean_pattern(_adapter *adapter) +{ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + struct rtl_wow_pattern zero_pattern; + int i = 0; + + _rtw_memset(&zero_pattern, 0, sizeof(struct rtl_wow_pattern)); + + zero_pattern.type = PATTERN_INVALID; + + for (i = 0; i < MAX_WKFM_CAM_NUM; i++) + rtw_write_to_frame_mask(adapter, i, &zero_pattern); + + rtw_write8(adapter, REG_WKFMCAM_NUM, 0); +} +static int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern, + u8 len, u8 *mask, u8 idx) +{ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + struct mlme_ext_priv *pmlmeext = NULL; + struct mlme_ext_info *pmlmeinfo = NULL; + struct rtl_wow_pattern wow_pattern; + u8 mask_hw[MAX_WKFM_SIZE] = {0}; + u8 content[MAX_WKFM_PATTERN_SIZE] = {0}; + u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 multicast_addr1[2] = {0x33, 0x33}; + u8 multicast_addr2[3] = {0x01, 0x00, 0x5e}; + u8 res = _FALSE, index = 0, mask_len = 0; + u8 mac_addr[ETH_ALEN] = {0}; + u16 count = 0; + int i, j; + + if (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) { + RTW_INFO("%s pattern_idx is more than MAX_FMC_NUM: %d\n", + __func__, MAX_WKFM_CAM_NUM); + return _FALSE; + } + + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + _rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN); + _rtw_memset(&wow_pattern, 0, sizeof(struct rtl_wow_pattern)); + + mask_len = DIV_ROUND_UP(len, 8); + + /* 1. setup A1 table */ + if (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0) + wow_pattern.type = PATTERN_BROADCAST; + else if (memcmp(pattern, multicast_addr1, 2) == 0) + wow_pattern.type = PATTERN_MULTICAST; + else if (memcmp(pattern, multicast_addr2, 3) == 0) + wow_pattern.type = PATTERN_MULTICAST; + else if (memcmp(pattern, mac_addr, ETH_ALEN) == 0) + wow_pattern.type = PATTERN_UNICAST; + else + wow_pattern.type = PATTERN_INVALID; + + /* translate mask from os to mask for hw */ + +/****************************************************************************** + * pattern from OS uses 'ethenet frame', like this: + + | 6 | 6 | 2 | 20 | Variable | 4 | + |--------+--------+------+-----------+------------+-----| + | 802.3 Mac Header | IP Header | TCP Packet | FCS | + | DA | SA | Type | + + * BUT, packet catched by our HW is in '802.11 frame', begin from LLC, + + | 24 or 30 | 6 | 2 | 20 | Variable | 4 | + |-------------------+--------+------+-----------+------------+-----| + | 802.11 MAC Header | LLC | IP Header | TCP Packet | FCS | + | Others | Tpye | + + * Therefore, we need translate mask_from_OS to mask_to_hw. + * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0, + * because new mask[0~5] means 'SA', but our HW packet begins from LLC, + * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match. + ******************************************************************************/ + /* Shift 6 bits */ + for (i = 0; i < mask_len - 1; i++) { + mask_hw[i] = mask[i] >> 6; + mask_hw[i] |= (mask[i + 1] & 0x3F) << 2; + } + + mask_hw[i] = (mask[i] >> 6) & 0x3F; + /* Set bit 0-5 to zero */ + mask_hw[0] &= 0xC0; + + for (i = 0; i < (MAX_WKFM_SIZE / 4); i++) { + wow_pattern.mask[i] = mask_hw[i * 4]; + wow_pattern.mask[i] |= (mask_hw[i * 4 + 1] << 8); + wow_pattern.mask[i] |= (mask_hw[i * 4 + 2] << 16); + wow_pattern.mask[i] |= (mask_hw[i * 4 + 3] << 24); + } + + /* To get the wake up pattern from the mask. + * We do not count first 12 bits which means + * DA[6] and SA[6] in the pattern to match HW design. */ + count = 0; + for (i = 12; i < len; i++) { + if ((mask[i / 8] >> (i % 8)) & 0x01) { + content[count] = pattern[i]; + count++; + } + } + + wow_pattern.crc = rtw_calc_crc(content, count); + + if (wow_pattern.crc != 0) { + if (wow_pattern.type == PATTERN_INVALID) + wow_pattern.type = PATTERN_VALID; + } + + index = idx; + + if (!pwrctl->bInSuspend) + index += 2; + + /* write pattern */ + res = rtw_write_to_frame_mask(adapter, index, &wow_pattern); + + if (res == _FALSE) + RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n", + __func__, idx); + + return res; +} +void rtw_fill_pattern(_adapter *adapter) +{ + int i = 0, total = 0, index; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + struct rtl_wow_pattern wow_pattern; + + total = pwrpriv->wowlan_pattern_idx; + + if (total > MAX_WKFM_CAM_NUM) + total = MAX_WKFM_CAM_NUM; + + for (i = 0 ; i < total ; i++) { + if (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) { + + index = i; + if (!pwrpriv->bInSuspend) + index += 2; + + if (rtw_write_to_frame_mask(adapter, index, &wow_pattern) == _FALSE) + RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n", __func__, i); + } + + } + rtw_write8(adapter, REG_WKFMCAM_NUM, total); + +} + +#else /*CONFIG_WOW_PATTERN_HW_CAM*/ + +#define WOW_CAM_ACCESS_TIMEOUT_MS 200 +#define WOW_VALID_BIT BIT31 +#define WOW_BC_BIT BIT26 +#define WOW_MC_BIT BIT25 +#define WOW_UC_BIT BIT24 + +static u32 _rtw_wow_pattern_read_cam(_adapter *adapter, u8 addr) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex; + + u32 rdata = 0; + u32 cnt = 0; + u32 start = 0; + u8 timeout = 0; + u8 rst = _FALSE; + + _enter_critical_mutex(mutex, NULL); + + rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_ADDR_V2(addr)); + + start = rtw_get_current_time(); + while (1) { + if (rtw_is_surprise_removed(adapter)) + break; + + cnt++; + if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) { + rst = _SUCCESS; + break; + } + if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) { + timeout = 1; + break; + } + } + + rdata = rtw_read32(adapter, REG_WKFMCAM_RWD); + + _exit_critical_mutex(mutex, NULL); + + /*RTW_INFO("%s ==> addr:0x%02x , rdata:0x%08x\n", __func__, addr, rdata);*/ + + if (timeout) + RTW_ERR(FUNC_ADPT_FMT" failed due to polling timeout\n", FUNC_ADPT_ARG(adapter)); + + return rdata; +} +void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct rtl_wow_pattern *context) +{ + int i; + u32 rdata; + + _rtw_memset(context, 0, sizeof(struct rtl_wow_pattern)); + + for (i = 4; i >= 0; i--) { + rdata = _rtw_wow_pattern_read_cam(adapter, (id << 3) | i); + + switch (i) { + case 4: + if (rdata & WOW_BC_BIT) + context->type = PATTERN_BROADCAST; + else if (rdata & WOW_MC_BIT) + context->type = PATTERN_MULTICAST; + else if (rdata & WOW_UC_BIT) + context->type = PATTERN_UNICAST; + else + context->type = PATTERN_INVALID; + + context->crc = rdata & 0xFFFF; + break; + default: + _rtw_memcpy(&context->mask[i], (u8 *)(&rdata), 4); + break; + } + } +} + +static void _rtw_wow_pattern_write_cam(_adapter *adapter, u8 addr, u32 wdata) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex; + u32 cnt = 0; + u32 start = 0, end = 0; + u8 timeout = 0; + + /*RTW_INFO("%s ==> addr:0x%02x , wdata:0x%08x\n", __func__, addr, wdata);*/ + _enter_critical_mutex(mutex, NULL); + + rtw_write32(adapter, REG_WKFMCAM_RWD, wdata); + rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_WE | BIT_WKFCAM_ADDR_V2(addr)); + + start = rtw_get_current_time(); + while (1) { + if (rtw_is_surprise_removed(adapter)) + break; + + cnt++; + if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) + break; + + if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) { + timeout = 1; + break; + } + } + end = rtw_get_current_time(); + + _exit_critical_mutex(mutex, NULL); + + if (timeout) { + RTW_ERR(FUNC_ADPT_FMT" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\n" + , FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end)); + } +} + +void rtw_wow_pattern_write_cam_ent(_adapter *adapter, u8 id, struct rtl_wow_pattern *context) +{ + int j; + u8 addr; + u32 wdata = 0; + + for (j = 4; j >= 0; j--) { + switch (j) { + case 4: + wdata = context->crc; + + if (PATTERN_BROADCAST == context->type) + wdata |= WOW_BC_BIT; + if (PATTERN_MULTICAST == context->type) + wdata |= WOW_MC_BIT; + if (PATTERN_UNICAST == context->type) + wdata |= WOW_UC_BIT; + if (PATTERN_INVALID != context->type) + wdata |= WOW_VALID_BIT; + break; + default: + wdata = context->mask[j]; + break; + } + + addr = (id << 3) + j; + + _rtw_wow_pattern_write_cam(adapter, addr, wdata); + } +} + +static u8 _rtw_wow_pattern_clean_cam(_adapter *adapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex; + u32 cnt = 0; + u32 start = 0; + u8 timeout = 0; + u8 rst = _FAIL; + + _enter_critical_mutex(mutex, NULL); + rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_CLR_V1); + + start = rtw_get_current_time(); + while (1) { + if (rtw_is_surprise_removed(adapter)) + break; + + cnt++; + if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) { + rst = _SUCCESS; + break; + } + if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) { + timeout = 1; + break; + } + } + _exit_critical_mutex(mutex, NULL); + + if (timeout) + RTW_ERR(FUNC_ADPT_FMT" falied ,polling timeout\n", FUNC_ADPT_ARG(adapter)); + + return rst; +} + +void rtw_clean_pattern(_adapter *adapter) +{ + if (_FAIL == _rtw_wow_pattern_clean_cam(adapter)) + RTW_ERR("rtw_clean_pattern failed\n"); +} + +void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx) +{ + int j; + + RTW_PRINT_SEL(sel, "=======WOW CAM-ID[%d]=======\n", idx); + RTW_PRINT_SEL(sel, "[WOW CAM] type:%d\n", pwow_pattern->type); + RTW_PRINT_SEL(sel, "[WOW CAM] crc:0x%04x\n", pwow_pattern->crc); + for (j = 0; j < 4; j++) + RTW_PRINT_SEL(sel, "[WOW CAM] Mask:0x%08x\n", pwow_pattern->mask[j]); +} + +void rtw_fill_pattern(_adapter *adapter) +{ + int i = 0, total = 0; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + struct rtl_wow_pattern wow_pattern; + + total = pwrpriv->wowlan_pattern_idx; + + if (total > MAX_WKFM_CAM_NUM) + total = MAX_WKFM_CAM_NUM; - if (wow_pattern.crc != 0) { - if (wow_pattern.type == PATTERN_INVALID) - wow_pattern.type = PATTERN_VALID; + for (i = 0 ; i < total ; i++) { + if (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) { + rtw_dump_wow_pattern(RTW_DBGDUMP, &wow_pattern, i); + rtw_wow_pattern_write_cam_ent(adapter, i, &wow_pattern); + } } +} - index = idx; +#endif +void rtw_wow_pattern_cam_dump(_adapter *adapter) +{ - if (!pwrctl->bInSuspend) - index += 2; +#ifndef CONFIG_WOW_PATTERN_HW_CAM + int i; - /* write pattern */ - res = rtw_write_to_frame_mask(adapter, index, &wow_pattern); + for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) { + RTW_INFO("=======[%d]=======\n", i); + rtw_read_from_frame_mask(adapter, i); + } +#else + struct rtl_wow_pattern context; + int i; - if (res == _FALSE) - RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n", - __func__, idx); + for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) { + rtw_wow_pattern_read_cam_ent(adapter, i, &context); + rtw_dump_wow_pattern(RTW_DBGDUMP, &context, i); + } - return res; +#endif } + static void rtw_hal_dl_pattern(_adapter *adapter, u8 mode) { - struct registry_priv *pregistrypriv = &adapter->registrypriv; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); - int i = 0, total = 0; - - total = pwrpriv->wowlan_pattern_idx; - - if (total > MAX_WKFM_NUM) - total = MAX_WKFM_NUM; - - rtw_clean_pattern(adapter); switch (mode) { case 0: - RTW_INFO("%s: total patterns: %d\n", __func__, total); + rtw_clean_pattern(adapter); + RTW_INFO("%s: total patterns: %d\n", __func__, pwrpriv->wowlan_pattern_idx); break; case 1: rtw_set_default_pattern(adapter); - for (i = 0 ; i < total ; i++) { - rtw_hal_set_pattern(adapter, - pwrpriv->patterns[i].content, - pwrpriv->patterns[i].len, - pwrpriv->patterns[i].mask, i); - } - rtw_write8(adapter, REG_WKFMCAM_NUM, total); - RTW_INFO("%s: pattern total: %d downloaded\n", - __func__, total); + rtw_fill_pattern(adapter); + RTW_INFO("%s: pattern total: %d downloaded\n", __func__, pwrpriv->wowlan_pattern_idx); break; case 2: - pwrpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM; - - for (i = DEFAULT_PATTERN_NUM ; i < MAX_WKFM_NUM ; i++) { - _rtw_memset(pwrpriv->patterns[i].content, '\0', - sizeof(pwrpriv->patterns[i].content)); - _rtw_memset(pwrpriv->patterns[i].mask, '\0', - sizeof(pwrpriv->patterns[i].mask)); - pwrpriv->patterns[i].len = 0; - } + rtw_clean_pattern(adapter); + rtw_wow_pattern_sw_reset(adapter); RTW_INFO("%s: clean patterns\n", __func__); break; default: @@ -6378,8 +7985,9 @@ static void rtw_hal_wow_enable(_adapter *adapter) struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); struct security_priv *psecuritypriv = &adapter->securitypriv; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; struct sta_info *psta = NULL; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); int res; u16 media_status_rpt; @@ -6387,35 +7995,45 @@ static void rtw_hal_wow_enable(_adapter *adapter) RTW_PRINT("%s, WOWLAN_ENABLE\n", __func__); rtw_hal_gate_bb(adapter, _TRUE); #ifdef CONFIG_GTK_OL - if (psecuritypriv->dot11PrivacyAlgrthm == _AES_) + if (psecuritypriv->binstallKCK_KEK == _TRUE) rtw_hal_fw_sync_cam_id(adapter); #endif if (IS_HARDWARE_TYPE_8723B(adapter)) rtw_hal_backup_rate(adapter); + rtw_hal_fw_dl(adapter, _TRUE); + media_status_rpt = RT_MEDIA_CONNECT; + rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT, + (u8 *)&media_status_rpt); + /* RX DMA stop */ + #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(adapter)) rtw_hal_disable_tx_report(adapter); + #endif res = rtw_hal_pause_rx_dma(adapter); if (res == _FAIL) RTW_PRINT("[WARNING] pause RX DMA fail\n"); + #ifndef CONFIG_WOW_PATTERN_HW_CAM /* Reconfig RX_FF Boundary */ rtw_hal_set_wow_rxff_boundary(adapter, _TRUE); + #endif /* redownload wow pattern */ rtw_hal_dl_pattern(adapter, 1); - rtw_hal_fw_dl(adapter, _TRUE); - media_status_rpt = RT_MEDIA_CONNECT; - rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT, - (u8 *)&media_status_rpt); - if (!pwrctl->wowlan_pno_enable) { psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv)); - if (psta != NULL) + + if (psta != NULL) { + #ifdef CONFIG_FW_MULTI_PORT_SUPPORT + rtw_hal_set_default_port_id_cmd(adapter, psta->mac_id); + #endif + rtw_sta_media_status_rpt(adapter, psta, 1); + } } #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) @@ -6443,25 +8061,80 @@ static void rtw_hal_wow_enable(_adapter *adapter) pwrctl->wowlan_wake_reason); #ifdef CONFIG_GTK_OL_DBG dump_sec_cam(RTW_DBGDUMP, adapter); + dump_sec_cam_cache(RTW_DBGDUMP, adapter); #endif #ifdef CONFIG_USB_HCI /* free adapter's resource */ rtw_mi_intf_stop(adapter); +#endif +#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) /* Invoid SE0 reset signal during suspending*/ rtw_write8(adapter, REG_RSV_CTRL, 0x20); - rtw_write8(adapter, REG_RSV_CTRL, 0x60); -#endif /*CONFIG_USB_HCI*/ + if (IS_8188F(pHalData->version_id) == FALSE) + rtw_write8(adapter, REG_RSV_CTRL, 0x60); +#endif rtw_hal_gate_bb(adapter, _FALSE); } +#define DBG_WAKEUP_REASON +#ifdef DBG_WAKEUP_REASON +void _dbg_wake_up_reason_string(_adapter *adapter, const char *srt_res) +{ + RTW_INFO(ADPT_FMT "- wake up reason - %s\n", ADPT_ARG(adapter), srt_res); +} +void _dbg_rtw_wake_up_reason(_adapter *adapter, u8 reason) +{ + if (RX_PAIRWISEKEY == reason) + _dbg_wake_up_reason_string(adapter, "Rx pairwise key"); + else if (RX_GTK == reason) + _dbg_wake_up_reason_string(adapter, "Rx GTK"); + else if (RX_FOURWAY_HANDSHAKE == reason) + _dbg_wake_up_reason_string(adapter, "Rx four way handshake"); + else if (RX_DISASSOC == reason) + _dbg_wake_up_reason_string(adapter, "Rx disassoc"); + else if (RX_DEAUTH == reason) + _dbg_wake_up_reason_string(adapter, "Rx deauth"); + else if (RX_ARP_REQUEST == reason) + _dbg_wake_up_reason_string(adapter, "Rx ARP request"); + else if (FW_DECISION_DISCONNECT == reason) + _dbg_wake_up_reason_string(adapter, "FW detect disconnect"); + else if (RX_MAGIC_PKT == reason) + _dbg_wake_up_reason_string(adapter, "Rx magic packet"); + else if (RX_UNICAST_PKT == reason) + _dbg_wake_up_reason_string(adapter, "Rx unicast packet"); + else if (RX_PATTERN_PKT == reason) + _dbg_wake_up_reason_string(adapter, "Rx pattern packet"); + else if (RTD3_SSID_MATCH == reason) + _dbg_wake_up_reason_string(adapter, "RTD3 SSID match"); + else if (RX_REALWOW_V2_WAKEUP_PKT == reason) + _dbg_wake_up_reason_string(adapter, "Rx real WOW V2 wakeup packet"); + else if (RX_REALWOW_V2_ACK_LOST == reason) + _dbg_wake_up_reason_string(adapter, "Rx real WOW V2 ack lost"); + else if (ENABLE_FAIL_DMA_IDLE == reason) + _dbg_wake_up_reason_string(adapter, "enable fail DMA idle"); + else if (ENABLE_FAIL_DMA_PAUSE == reason) + _dbg_wake_up_reason_string(adapter, "enable fail DMA pause"); + else if (AP_OFFLOAD_WAKEUP == reason) + _dbg_wake_up_reason_string(adapter, "AP offload wakeup"); + else if (CLK_32K_UNLOCK == reason) + _dbg_wake_up_reason_string(adapter, "clk 32k unlock"); + else if (RTIME_FAIL_DMA_IDLE == reason) + _dbg_wake_up_reason_string(adapter, "RTIME fail DMA idle"); + else if (CLK_32K_LOCK == reason) + _dbg_wake_up_reason_string(adapter, "clk 32k lock"); + else + _dbg_wake_up_reason_string(adapter, "unknown reasoen"); +} +#endif + static void rtw_hal_wow_disable(_adapter *adapter) { struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); struct security_priv *psecuritypriv = &adapter->securitypriv; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; struct sta_info *psta = NULL; int res; u16 media_status_rpt; @@ -6480,12 +8153,17 @@ static void rtw_hal_wow_disable(_adapter *adapter) if (0) { RTW_INFO("0x630:0x%02x\n", rtw_read8(adapter, 0x630)); RTW_INFO("0x631:0x%02x\n", rtw_read8(adapter, 0x631)); + RTW_INFO("0x634:0x%02x\n", rtw_read8(adapter, 0x634)); + RTW_INFO("0x1c7:0x%02x\n", rtw_read8(adapter, 0x1c7)); } pwrctl->wowlan_wake_reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON); RTW_PRINT("wakeup_reason: 0x%02x\n", pwrctl->wowlan_wake_reason); + #ifdef DBG_WAKEUP_REASON + _dbg_rtw_wake_up_reason(adapter, pwrctl->wowlan_wake_reason); + #endif rtw_hal_set_fw_wow_related_cmd(adapter, 0); @@ -6505,19 +8183,25 @@ static void rtw_hal_wow_disable(_adapter *adapter) /* clean HW pattern match */ rtw_hal_dl_pattern(adapter, 0); + #ifndef CONFIG_WOW_PATTERN_HW_CAM /* config RXFF boundary to original */ rtw_hal_set_wow_rxff_boundary(adapter, _FALSE); - + #endif rtw_hal_release_rx_dma(adapter); + #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(adapter)) rtw_hal_enable_tx_report(adapter); - - rtw_hal_update_tx_iv(adapter); + #endif #ifdef CONFIG_GTK_OL - if (psecuritypriv->dot11PrivacyAlgrthm == _AES_) - rtw_hal_update_gtk_offload_info(adapter); + if (((pwrctl->wowlan_wake_reason != RX_DISASSOC) || + (pwrctl->wowlan_wake_reason != RX_DEAUTH) || + (pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT)) && + psecuritypriv->binstallKCK_KEK == _TRUE) { + rtw_hal_get_aoac_rpt(adapter); + rtw_hal_update_sw_security_info(adapter); + } #endif /*CONFIG_GTK_OL*/ rtw_hal_fw_dl(adapter, _FALSE); @@ -6526,19 +8210,25 @@ static void rtw_hal_wow_disable(_adapter *adapter) val8 = (pwrctl->is_high_active == 0) ? 1 : 0; RTW_PRINT("Set Wake GPIO to default(%d).\n", val8); rtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, val8); + + rtw_hal_switch_gpio_wl_ctrl(adapter, WAKEUP_GPIO_IDX, _FALSE); #endif - if ((pwrctl->wowlan_wake_reason != FWDecisionDisconnect) && - (pwrctl->wowlan_wake_reason != Rx_Pairwisekey) && - (pwrctl->wowlan_wake_reason != Rx_DisAssoc) && - (pwrctl->wowlan_wake_reason != Rx_DeAuth)) { + if ((pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT) && + (pwrctl->wowlan_wake_reason != RX_PAIRWISEKEY) && + (pwrctl->wowlan_wake_reason != RX_DISASSOC) && + (pwrctl->wowlan_wake_reason != RX_DEAUTH)) { media_status_rpt = RT_MEDIA_CONNECT; rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)&media_status_rpt); - if (psta != NULL) + if (psta != NULL) { + #ifdef CONFIG_FW_MULTI_PORT_SUPPORT + rtw_hal_set_default_port_id_cmd(adapter, psta->mac_id); + #endif rtw_sta_media_status_rpt(adapter, psta, 1); + } } rtw_hal_gate_bb(adapter, _FALSE); } @@ -6641,33 +8331,20 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, } #endif /* CONFIG_P2P_WOWLAN */ -#ifdef CONFIG_LPS_PG - #define LPSPG_RSVD_PAGE_SET_MACID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 0, 8, _value)/*used macid*/ - #define LPSPG_RSVD_PAGE_SET_MBSSCAMID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 8, 8, _value)/*used BSSID CAM entry*/ - #define LPSPG_RSVD_PAGE_SET_PMC_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 16, 8, _value)/*Max used Pattern Match CAM entry*/ - #define LPSPG_RSVD_PAGE_SET_MU_RAID_GID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 24, 8, _value)/*Max MU rate table Group ID*/ - #define LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 0, 8, _value)/*used Security CAM entry number*/ - #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID1(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 0, 8, _value)/*used Security CAM entry -1*/ - #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID2(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 8, 8, _value)/*used Security CAM entry -2*/ - #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID3(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 16, 8, _value)/*used Security CAM entry -3*/ - #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID4(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 24, 8, _value)/*used Security CAM entry -4*/ - #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID5(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 0, 8, _value)/*used Security CAM entry -5*/ - #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID6(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 8, 8, _value)/*used Security CAM entry -6*/ - #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID7(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 16, 8, _value)/*used Security CAM entry -7*/ - #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID8(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 24, 8, _value)/*used Security CAM entry -8*/ -#endif #ifdef CONFIG_LPS_PG #include "hal_halmac.h" #define DBG_LPSPG_SEC_DUMP #define LPS_PG_INFO_RSVD_LEN 16 +#define LPS_PG_INFO_RSVD_PAGE_NUM 1 +#define DBG_LPSPG_INFO_DUMP static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter) { - u8 cur_pag_num = 0; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); struct sta_info *psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv)); struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + PHAL_DATA_TYPE phal_data = GET_HAL_DATA(adapter); u8 lps_pg_info[LPS_PG_INFO_RSVD_LEN] = {0}; #ifdef CONFIG_MBSSID_CAM u8 cam_id = INVALID_CAM_ID; @@ -6676,38 +8353,49 @@ static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter) u8 sec_cam_num = 0; if (!psta) { - RTW_INFO("%s [ERROR] sta is NULL\n", __func__); + RTW_ERR("%s [ERROR] sta is NULL\n", __func__); rtw_warn_on(1); return; } - LPSPG_RSVD_PAGE_SET_MACID(lps_pg_info, psta->mac_id); /*used macid*/ + /*Byte 0 - used macid*/ + LPSPG_RSVD_PAGE_SET_MACID(lps_pg_info, psta->mac_id); RTW_INFO("[LPSPG-INFO] mac_id:%d\n", psta->mac_id); #ifdef CONFIG_MBSSID_CAM + /*Byte 1 - used BSSID CAM entry*/ cam_id = rtw_mbid_cam_search_by_ifaceid(adapter, adapter->iface_id); if (cam_id != INVALID_CAM_ID) - LPSPG_RSVD_PAGE_SET_MBSSCAMID(lps_pg_info, cam_id); /*used BSSID CAM entry*/ + LPSPG_RSVD_PAGE_SET_MBSSCAMID(lps_pg_info, cam_id); RTW_INFO("[LPSPG-INFO] mbss_cam_id:%d\n", cam_id); #endif #ifdef CONFIG_WOWLAN /*&& pattern match cam used*/ + /*Btye 2 - Max used Pattern Match CAM entry*/ if (pwrpriv->wowlan_mode == _TRUE && check_fwstate(&adapter->mlmepriv, _FW_LINKED) == _TRUE) { - LPSPG_RSVD_PAGE_SET_PMC_NUM(lps_pg_info, pwrpriv->wowlan_pattern_idx); /*Max used Pattern Match CAM entry*/ - RTW_INFO("[LPSPG-INFO] Max Pattern Match CAM entry :%d\n", _value); + LPSPG_RSVD_PAGE_SET_PMC_NUM(lps_pg_info, pwrpriv->wowlan_pattern_idx); + RTW_INFO("[LPSPG-INFO] Max Pattern Match CAM entry :%d\n", pwrpriv->wowlan_pattern_idx); } #endif #ifdef CONFIG_BEAMFORMING /*&& MU BF*/ - LPSPG_RSVD_PAGE_SET_MU_RAID_GID(lps_pg_info, _value); /*Max MU rate table Group ID*/ + /*Btye 3 - Max MU rate table Group ID*/ + LPSPG_RSVD_PAGE_SET_MU_RAID_GID(lps_pg_info, _value); RTW_INFO("[LPSPG-INFO] Max MU rate table Group ID :%d\n", _value); #endif + /*Btye 8 ~15 - used Security CAM entry */ sec_cam_num = rtw_get_sec_camid(adapter, 8, psec_cam_id); + + /*Btye 4 - used Security CAM entry number*/ if (sec_cam_num < 8) - LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(lps_pg_info, sec_cam_num); /*used Security CAM entry number*/ + LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(lps_pg_info, sec_cam_num); RTW_INFO("[LPSPG-INFO] Security CAM entry number :%d\n", sec_cam_num); + /*Btye 5 - Txbuf used page number for fw offload*/ + LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(lps_pg_info, phal_data->drv_rsvd_page_number); + RTW_INFO("[LPSPG-INFO] DRV's rsvd page numbers :%d\n", phal_data->drv_rsvd_page_number); + #ifdef DBG_LPSPG_SEC_DUMP { int i; @@ -6730,9 +8418,13 @@ static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter) rtw_halmac_download_rsvd_page(dvobj, pwrpriv->lpspg_rsvd_page_locate, lps_pg_info, LPS_PG_INFO_RSVD_LEN); +#ifdef DBG_LPSPG_INFO_DUMP + RTW_INFO("Get LPS-PG INFO from rsvd page_offset:%d\n", pwrpriv->lpspg_rsvd_page_locate); + rtw_dump_rsvd_page(RTW_DBGDUMP, adapter, pwrpriv->lpspg_rsvd_page_locate, 1); +#endif } -#define DBG_LPSPG_INFO_DUMP + static u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); @@ -6749,7 +8441,7 @@ static u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter) SET_H2CCMD_LPSPG_MBID_CAM_EN(lpspg_info, 1); /*BSSIDCAM_En*/ #endif -#ifdef CONFIG_WOWLAN /*&& pattern match cam used*/ +#if defined(CONFIG_WOWLAN) && defined(CONFIG_WOW_PATTERN_HW_CAM) if (pwrpriv->wowlan_mode == _TRUE && check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { @@ -6787,11 +8479,60 @@ static u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter) u8 rtw_hal_set_lps_pg_info(_adapter *adapter) { u8 ret = _FAIL; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + + if (pwrpriv->lpspg_rsvd_page_locate == 0) { + RTW_ERR("%s [ERROR] lpspg_rsvd_page_locate = 0\n", __func__); + rtw_warn_on(1); + return ret; + } rtw_hal_set_lps_pg_info_rsvd_page(adapter); ret = rtw_hal_set_lps_pg_info_cmd(adapter); + if (_SUCCESS == ret) + pwrpriv->blpspg_info_up = _FALSE; + return ret; } + +void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id) +{ + switch (hdl_id) { + case LPS_PG_INFO_CFG: + rtw_hal_set_lps_pg_info(adapter); + break; + case LPS_PG_REDLEMEM: + { + /*set xmit_block*/ + rtw_set_xmit_block(adapter, XMIT_BLOCK_REDLMEM); + if (_FAIL == rtw_hal_fw_mem_dl(adapter, FW_EMEM)) + rtw_warn_on(1); + /*clearn xmit_block*/ + rtw_clr_xmit_block(adapter, XMIT_BLOCK_REDLMEM); + } + break; + + case LPS_PG_RESEND_H2C: + { + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + struct sta_info *sta; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + int i; + + for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { + sta = macid_ctl->sta[i]; + if (sta && !is_broadcast_mac_addr(sta->hwaddr)) + /*rtw_dm_ra_mask_hdl(adapter, sta);*/ + rtw_dm_ra_mask_wk_cmd(adapter, (u8 *)sta); + } + } + break; + + default: + break; + } +} + #endif /*CONFIG_LPS_PG*/ /* @@ -6810,6 +8551,7 @@ u8 rtw_hal_set_lps_pg_info(_adapter *adapter) * Page Size = 512: 8812a */ +/*#define DBG_DUMP_SET_RSVD_PAGE*/ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) { PHAL_DATA_TYPE pHalData; @@ -6820,7 +8562,7 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) struct mlme_ext_info *pmlmeinfo; struct pwrctrl_priv *pwrctl; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct hal_ops *pHalFunc = &adapter->HalFunc; + struct hal_ops *pHalFunc = &adapter->hal_func; u32 BeaconLength = 0, ProbeRspLength = 0, PSPollLength = 0; u32 NullDataLength = 0, QosNullLength = 0, BTQosNullLength = 0; u32 ProbeReqLength = 0, NullFunctionDataLength = 0; @@ -6881,7 +8623,7 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) ReservedPagePacket = pcmdframe->buf_addr; _rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC)); - /* beacon * 2 pages */ + /* beacon * 1 pages */ BufIndex = TxDescOffset; rtw_hal_construct_beacon(adapter, &ReservedPagePacket[BufIndex], &BeaconLength); @@ -6891,9 +8633,6 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) * packet, it will be filled in front of the packet in TXPKTBUF. */ CurtPktPageNum = (u8)PageNum((TxDescLen + BeaconLength), PageSize); - /* If we don't add 1 more page, ARP offload function will fail at 8723bs.*/ - if (CurtPktPageNum == 1) - CurtPktPageNum += 1; TotalPageNum += CurtPktPageNum; @@ -6933,24 +8672,29 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) BufIndex += (CurtPktPageNum * PageSize); #ifdef CONFIG_BT_COEXIST - /* BT Qos null data * 1 page */ - RsvdPageLoc.LocBTQosNull = TotalPageNum; - RTW_INFO("LocBTQosNull: %d\n", RsvdPageLoc.LocBTQosNull); - rtw_hal_construct_NullFunctionData( - adapter, - &ReservedPagePacket[BufIndex], - &BTQosNullLength, - get_my_bssid(&pmlmeinfo->network), - _TRUE, 0, 0, _FALSE); - rtw_hal_fill_fake_txdesc(adapter, - &ReservedPagePacket[BufIndex - TxDescLen], - BTQosNullLength, _FALSE, _TRUE, _FALSE); + if (pwrctl->wowlan_mode == _FALSE || + pwrctl->wowlan_in_resume == _TRUE) { + /* BT Qos null data * 1 page */ + RsvdPageLoc.LocBTQosNull = TotalPageNum; - CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength, PageSize); + RTW_INFO("LocBTQosNull: %d\n", RsvdPageLoc.LocBTQosNull); - TotalPageNum += CurtPktPageNum; + rtw_hal_construct_NullFunctionData(adapter, + &ReservedPagePacket[BufIndex], + &BTQosNullLength, + get_my_bssid(&pmlmeinfo->network), + _TRUE, 0, 0, _FALSE); - BufIndex += (CurtPktPageNum * PageSize); + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex - TxDescLen], + BTQosNullLength, _FALSE, _TRUE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength, + PageSize); + + TotalPageNum += CurtPktPageNum; + BufIndex += (CurtPktPageNum * PageSize); + } #endif /* CONFIG_BT_COEXIT */ #ifdef CONFIG_MCC_MODE @@ -6986,29 +8730,33 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) } #endif /* CONFIG_MCC_MODE */ - /* Qos null data * 1 page */ - RsvdPageLoc.LocQosNull = TotalPageNum; - RTW_INFO("LocQosNull: %d\n", RsvdPageLoc.LocQosNull); - rtw_hal_construct_NullFunctionData( - adapter, - &ReservedPagePacket[BufIndex], - &QosNullLength, - get_my_bssid(&pmlmeinfo->network), - _TRUE, 0, 0, _FALSE); - rtw_hal_fill_fake_txdesc(adapter, + if (pwrctl->wowlan_mode == _FALSE || + pwrctl->wowlan_in_resume == _TRUE) { + /* Qos null data * 1 page */ + RsvdPageLoc.LocQosNull = TotalPageNum; + RTW_INFO("LocQosNull: %d\n", RsvdPageLoc.LocQosNull); + rtw_hal_construct_NullFunctionData(adapter, + &ReservedPagePacket[BufIndex], + &QosNullLength, + get_my_bssid(&pmlmeinfo->network), + _TRUE, 0, 0, _FALSE); + rtw_hal_fill_fake_txdesc(adapter, &ReservedPagePacket[BufIndex - TxDescLen], QosNullLength, _FALSE, _FALSE, _FALSE); - CurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength, PageSize); + CurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength, + PageSize); - TotalPageNum += CurtPktPageNum; + TotalPageNum += CurtPktPageNum; - TotalPacketLen = BufIndex + QosNullLength; + BufIndex += (CurtPktPageNum * PageSize); + } - BufIndex += (CurtPktPageNum * PageSize); + TotalPacketLen = BufIndex + QosNullLength; #ifdef CONFIG_WOWLAN - if (pwrctl->wowlan_mode == _TRUE) { + if (pwrctl->wowlan_mode == _TRUE && + pwrctl->wowlan_in_resume == _FALSE) { rtw_hal_set_wow_fw_rsvd_page(adapter, ReservedPagePacket, BufIndex, TxDescLen, PageSize, &TotalPageNum, &TotalPacketLen, &RsvdPageLoc); @@ -7026,6 +8774,7 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) #ifdef CONFIG_LPS_PG /* must reserved last 1 x page for LPS PG Info*/ pwrctl->lpspg_rsvd_page_locate = TotalPageNum; + pwrctl->blpspg_info_up = _TRUE; #endif download_page: @@ -7033,8 +8782,19 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) RTW_INFO("%s PageNum(%d), pktlen(%d)\n", __func__, TotalPageNum, TotalPacketLen); +#ifdef CONFIG_LPS_PG + if ((TotalPacketLen + (LPS_PG_INFO_RSVD_PAGE_NUM * PageSize)) > MaxRsvdPageBufSize) { + pwrctl->lpspg_rsvd_page_locate = 0; + pwrctl->blpspg_info_up = _FALSE; + + RTW_ERR("%s rsvd page size is not enough!!TotalPacketLen+LPS_PG_INFO_LEN %d, MaxRsvdPageBufSize %d\n", + __func__, (TotalPacketLen + (LPS_PG_INFO_RSVD_PAGE_NUM * PageSize)), MaxRsvdPageBufSize); + rtw_warn_on(1); + } +#endif + if (TotalPacketLen > MaxRsvdPageBufSize) { - RTW_INFO("%s(ERROR): rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n", + RTW_ERR("%s(ERROR): rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n", __FUNCTION__, TotalPacketLen, MaxRsvdPageBufSize); rtw_warn_on(1); goto error; @@ -7054,11 +8814,18 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) RTW_INFO("%s: Set RSVD page location to Fw ,TotalPacketLen(%d), TotalPageNum(%d)\n", __func__, TotalPacketLen, TotalPageNum); - +#ifdef DBG_DUMP_SET_RSVD_PAGE + RTW_INFO(" ==================================================\n"); + RTW_INFO_DUMP("\n", ReservedPagePacket, TotalPacketLen); + RTW_INFO(" ==================================================\n"); +#endif if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { rtw_hal_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc); - if (pwrctl->wowlan_mode == _TRUE) +#ifdef CONFIG_WOWLAN + if (pwrctl->wowlan_mode == _TRUE && + pwrctl->wowlan_in_resume == _FALSE) rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc); +#endif /* CONFIG_WOWLAN */ #ifdef CONFIG_AP_WOWLAN if (pwrctl->wowlan_ap_mode == _TRUE) rtw_hal_set_ap_rsvdpage_loc_cmd(adapter, &RsvdPageLoc); @@ -7066,7 +8833,7 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) } else if (pwrctl->wowlan_pno_enable) { #ifdef CONFIG_PNO_SUPPORT rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc); - if (pwrctl->pno_in_resume) + if (pwrctl->wowlan_in_resume) rtw_hal_set_scan_offload_info_cmd(adapter, &RsvdPageLoc, 0); else @@ -7134,17 +8901,35 @@ s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset default: break; } - SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(ch_sw_h2c_buf, pHalData->RFEType); + SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(ch_sw_h2c_buf, pHalData->rfe_type); return rtw_hal_fill_h2c_cmd(padapter, H2C_CHNL_SWITCH_OPER_OFFLOAD, sizeof(ch_sw_h2c_buf), ch_sw_h2c_buf); } #endif #endif +#ifdef CONFIG_WMMPS +void rtw_hal_update_uapsd_tid(_adapter *adapter) +{ + rtw_write8(adapter, REG_WMMPS_UAPSD_TID, 0xFF); +} +#endif + +#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) +/* For multi-port support, driver needs to inform the port ID to FW for btc operations */ +s32 rtw_hal_set_wifi_port_id_cmd(_adapter *adapter) +{ + u8 port_id = 0; + u8 h2c_buf[H2C_BTC_WL_PORT_ID_LEN] = {0}; + + SET_H2CCMD_BTC_WL_PORT_ID(h2c_buf, adapter->hw_port); + return rtw_hal_fill_h2c_cmd(adapter, H2C_BTC_WL_PORT_ID, H2C_BTC_WL_PORT_ID_LEN, h2c_buf); +} +#endif + void SetHwReg(_adapter *adapter, u8 variable, u8 *val) { HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - _func_enter_; switch (variable) { case HW_VAR_MEDIA_STATUS: { @@ -7172,7 +8957,7 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) cmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | BIT_MBIDCAM_VALID | cam_val[1]; rtw_write32(adapter, REG_MBIDCAMCFG_2, cmd); } - break; + break; case HW_VAR_MBSSID_CAM_CLEAR: { u32 cmd; u8 entry_id = *(u8 *)val; @@ -7182,7 +8967,7 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) cmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | ((entry_id & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT); rtw_write32(adapter, REG_MBIDCAMCFG_2, cmd); } - break; + break; case HW_VAR_RCR_MBSSID_EN: if (*((u8 *)val)) rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR) | RCR_ENMBID); @@ -7201,7 +8986,7 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) case HW_VAR_INIT_RTS_RATE: { u16 brate_cfg = *((u16 *)val); u8 rate_index = 0; - HAL_VERSION *hal_ver = &hal_data->VersionID; + HAL_VERSION *hal_ver = &hal_data->version_id; if (IS_8188E(*hal_ver)) { @@ -7213,7 +8998,7 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) } else rtw_warn_on(1); } - break; + break; case HW_VAR_SEC_CFG: { u16 reg_scr_ori; u16 reg_scr; @@ -7230,7 +9015,7 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) if (reg_scr != reg_scr_ori) rtw_write16(adapter, REG_SECCFG, reg_scr); } - break; + break; case HW_VAR_SEC_DK_CFG: { struct security_priv *sec = &adapter->securitypriv; u8 reg_scr = rtw_read8(adapter, REG_SECCFG); @@ -7244,7 +9029,7 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) rtw_write8(adapter, REG_SECCFG, reg_scr); } - break; + break; case HW_VAR_ASIX_IOT: /* enable ASIX IOT function */ @@ -7290,13 +9075,28 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) break; } } - break; + break; #endif /*defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)*/ case HW_VAR_EN_HW_UPDATE_TSF: rtw_hal_set_hw_update_tsf(adapter); break; + case HW_VAR_APFM_ON_MAC: + hal_data->bMacPwrCtrlOn = *val; + RTW_INFO("%s: bMacPwrCtrlOn=%d\n", __func__, hal_data->bMacPwrCtrlOn); + break; +#ifdef CONFIG_WMMPS + case HW_VAR_UAPSD_TID: + rtw_hal_update_uapsd_tid(adapter); + break; +#endif +#ifdef CONFIG_LPS_PG + case HW_VAR_LPS_PG_HANDLE: + rtw_hal_lps_pg_handler(adapter, *val); + break; +#endif + default: if (0) RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n", @@ -7304,14 +9104,12 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) break; } - _func_exit_; } void GetHwReg(_adapter *adapter, u8 variable, u8 *val) { HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - _func_enter_; switch (variable) { case HW_VAR_BASIC_RATE: @@ -7331,7 +9129,9 @@ void GetHwReg(_adapter *adapter, u8 variable, u8 *val) *val = _TRUE; else *val = _FALSE; - + break; + case HW_VAR_APFM_ON_MAC: + *val = hal_data->bMacPwrCtrlOn; break; default: if (0) @@ -7340,7 +9140,6 @@ void GetHwReg(_adapter *adapter, u8 variable, u8 *val) break; } - _func_exit_; } u8 @@ -7435,7 +9234,7 @@ GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) pstapriv = &adapter->stapriv; psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress); if (psta) - *((int *)value) = psta->rssi_stat.UndecoratedSmoothedPWDB; + *((int *)value) = psta->rssi_stat.undecorated_smoothed_pwdb; } break; case HAL_DEF_DBG_DUMP_RXPKT: @@ -7486,32 +9285,34 @@ void SetHalODMVar( BOOLEAN bSet) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T podmpriv = &pHalData->odmpriv; + struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv; /* _irqL irqL; */ switch (eVariable) { case HAL_ODM_STA_INFO: { struct sta_info *psta = (struct sta_info *)pValue1; if (bSet) { RTW_INFO("### Set STA_(%d) info ###\n", psta->mac_id); - ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta); + odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta); } else { RTW_INFO("### Clean STA_(%d) info ###\n", psta->mac_id); /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ - ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL); + psta->rssi_level = 0; + odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL); /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ } } - break; + break; case HAL_ODM_P2P_STATE: - ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet); + odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet); break; case HAL_ODM_WIFI_DISPLAY_STATE: - ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet); + odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet); break; case HAL_ODM_REGULATION: - ODM_CmnInfoInit(podmpriv, ODM_CMNINFO_DOMAIN_CODE_2G, pHalData->Regulation2_4G); - ODM_CmnInfoInit(podmpriv, ODM_CMNINFO_DOMAIN_CODE_5G, pHalData->Regulation5G); + /* used to auto enable/disable adaptivity by SD7 */ + odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_2G, 0); + odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_5G, 0); break; #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) case HAL_ODM_NOISE_MONITOR: { @@ -7522,7 +9323,7 @@ void SetHalODMVar( pinfo->chan, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time); #endif - pHalData->noise[pinfo->chan] = ODM_InbandNoise_Monitor(podmpriv, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time); + pHalData->noise[pinfo->chan] = odm_inband_noise_monitor(podmpriv, pinfo->is_pause_dig, pinfo->igi_value, pinfo->max_time); RTW_INFO("chan_%d, noise = %d (dBm)\n", pinfo->chan, pHalData->noise[pinfo->chan]); #ifdef DBG_NOISE_MONITOR RTW_INFO("noise_a = %d, noise_b = %d noise_all:%d\n", @@ -7531,54 +9332,54 @@ void SetHalODMVar( podmpriv->noise_level.noise_all); #endif } - break; + break; #endif/*#ifdef CONFIG_BACKGROUND_NOISE_MONITOR*/ case HAL_ODM_INITIAL_GAIN: { u8 rx_gain = *((u8 *)(pValue1)); /*printk("rx_gain:%x\n",rx_gain);*/ if (rx_gain == 0xff) {/*restore rx gain*/ - /*ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue);*/ - odm_PauseDIG(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain); + /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/ + odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain); } else { - /*pDigTable->BackupIGValue = pDigTable->CurIGValue;*/ - /*ODM_Write_DIG(podmpriv,rx_gain);*/ - odm_PauseDIG(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain); + /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/ + /*odm_write_dig(podmpriv,rx_gain);*/ + odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain); } } break; case HAL_ODM_FA_CNT_DUMP: if (*((u8 *)pValue1)) - podmpriv->DebugComponents |= (ODM_COMP_DIG | ODM_COMP_FA_CNT); + podmpriv->debug_components |= (ODM_COMP_DIG | ODM_COMP_FA_CNT); else - podmpriv->DebugComponents &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT); + podmpriv->debug_components &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT); break; case HAL_ODM_DBG_FLAG: - ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_DBG_COMP, *((u8Byte *)pValue1)); + odm_cmn_info_update(podmpriv, ODM_CMNINFO_DBG_COMP, *((u8Byte *)pValue1)); break; case HAL_ODM_DBG_LEVEL: - ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_DBG_LEVEL, *((u4Byte *)pValue1)); + odm_cmn_info_update(podmpriv, ODM_CMNINFO_DBG_LEVEL, *((u4Byte *)pValue1)); break; case HAL_ODM_RX_INFO_DUMP: { - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(podmpriv , PHYDM_FALSEALMCNT); - pDIG_T pDM_DigTable = &podmpriv->DM_DigTable; + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(podmpriv , PHYDM_FALSEALMCNT); + struct _dynamic_initial_gain_threshold_ *pDM_DigTable = &podmpriv->dm_dig_table; void *sel; sel = pValue1; _RTW_PRINT_SEL(sel , "============ Rx Info dump ===================\n"); - _RTW_PRINT_SEL(sel , "bLinked = %d, RSSI_Min = %d(%%), CurrentIGI = 0x%x\n", podmpriv->bLinked, podmpriv->RSSI_Min, pDM_DigTable->CurIGValue); - _RTW_PRINT_SEL(sel , "Cnt_Cck_fail = %d, Cnt_Ofdm_fail = %d, Total False Alarm = %d\n", FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_all); + _RTW_PRINT_SEL(sel , "is_linked = %d, rssi_min = %d(%%), current_igi = 0x%x\n", podmpriv->is_linked, podmpriv->rssi_min, pDM_DigTable->cur_ig_value); + _RTW_PRINT_SEL(sel , "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n", false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all); - if (podmpriv->bLinked) { - _RTW_PRINT_SEL(sel , "RxRate = %s", HDATA_RATE(podmpriv->RxRate)); + if (podmpriv->is_linked) { + _RTW_PRINT_SEL(sel , "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate)); _RTW_PRINT_SEL(sel , " RSSI_A = %d(%%), RSSI_B = %d(%%)\n", podmpriv->RSSI_A, podmpriv->RSSI_B); #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA rtw_dump_raw_rssi_info(Adapter, sel); #endif } } - break; + break; case HAL_ODM_RX_Dframe_INFO: { void *sel; @@ -7589,14 +9390,12 @@ void SetHalODMVar( rtw_dump_rx_dframe_info(Adapter, sel); #endif } - break; + break; #ifdef CONFIG_AUTO_CHNL_SEL_NHM case HAL_ODM_AUTO_CHNL_SEL: { ACS_OP acs_op = *(ACS_OP *)pValue1; - rtw_phydm_func_set(Adapter, ODM_BB_NHM_CNT); - if (ACS_INIT == acs_op) { #ifdef DBG_AUTO_CHNL_SEL_NHM RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_INIT\n", ADPT_ARG(Adapter)); @@ -7607,7 +9406,7 @@ void SetHalODMVar( #ifdef DBG_AUTO_CHNL_SEL_NHM RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_RESET\n", ADPT_ARG(Adapter)); #endif - odm_AutoChannelSelectReset(podmpriv); + odm_auto_channel_select_reset(podmpriv); } else if (ACS_SELECT == acs_op) { /* Collect NHM measurement result after current channel */ @@ -7619,18 +9418,18 @@ void SetHalODMVar( RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: Unexpected OP\n", ADPT_ARG(Adapter)); } - break; + break; #endif #ifdef CONFIG_ANTENNA_DIVERSITY case HAL_ODM_ANTDIV_SELECT: { u8 antenna = (*(u8 *)pValue1); /*switch antenna*/ - ODM_UpdateRxIdleAnt(&pHalData->odmpriv, antenna); + odm_update_rx_idle_ant(&pHalData->odmpriv, antenna); /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/ } - break; + break; #endif default: @@ -7645,7 +9444,7 @@ void GetHalODMVar( PVOID pValue2) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T podmpriv = &pHalData->odmpriv; + struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv; switch (eVariable) { #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) @@ -7657,13 +9456,13 @@ void GetHalODMVar( chan, pHalData->noise[chan]); #endif } - break; + break; #endif/*#ifdef CONFIG_BACKGROUND_NOISE_MONITOR*/ case HAL_ODM_DBG_FLAG: - *((u8Byte *)pValue1) = podmpriv->DebugComponents; + *((u8Byte *)pValue1) = podmpriv->debug_components; break; case HAL_ODM_DBG_LEVEL: - *((u4Byte *)pValue1) = podmpriv->DebugLevel; + *((u4Byte *)pValue1) = podmpriv->debug_level; break; #ifdef CONFIG_AUTO_CHNL_SEL_NHM @@ -7673,65 +9472,29 @@ void GetHalODMVar( #endif /* Retrieve better channel from NHM mechanism */ if (IsSupported24G(Adapter->registrypriv.wireless_mode)) - *((u8 *)(pValue1)) = ODM_GetAutoChannelSelectResult(podmpriv, BAND_ON_2_4G); - if (IsSupported5G(Adapter->registrypriv.wireless_mode)) - *((u8 *)(pValue2)) = ODM_GetAutoChannelSelectResult(podmpriv, BAND_ON_5G); + *((u8 *)(pValue1)) = odm_get_auto_channel_select_result(podmpriv, BAND_ON_2_4G); + if (is_supported_5g(Adapter->registrypriv.wireless_mode)) + *((u8 *)(pValue2)) = odm_get_auto_channel_select_result(podmpriv, BAND_ON_5G); } - break; + break; #endif #ifdef CONFIG_ANTENNA_DIVERSITY case HAL_ODM_ANTDIV_SELECT: { - pFAT_T pDM_FatTable = &podmpriv->DM_FatTable; - *((u8 *)pValue1) = pDM_FatTable->RxIdleAnt; + struct _FAST_ANTENNA_TRAINNING_ *pDM_FatTable = &podmpriv->dm_fat_table; + *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant; } - break; + break; #endif case HAL_ODM_INITIAL_GAIN: { - pDIG_T pDM_DigTable = &podmpriv->DM_DigTable; - *((u8 *)pValue1) = pDM_DigTable->CurIGValue; - } - break; - default: - break; + struct _dynamic_initial_gain_threshold_ *pDM_DigTable = &podmpriv->dm_dig_table; + *((u8 *)pValue1) = pDM_DigTable->cur_ig_value; } -} - - -u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - PDM_ODM_T podmpriv = &pHalData->odmpriv; - u32 result = 0; - - switch (ops) { - case HAL_PHYDM_DIS_ALL_FUNC: - podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE; break; - case HAL_PHYDM_FUNC_SET: - podmpriv->SupportAbility |= ability; - break; - case HAL_PHYDM_FUNC_CLR: - podmpriv->SupportAbility &= ~(ability); - break; - case HAL_PHYDM_ABILITY_BK: - /* dm flag backup*/ - podmpriv->BK_SupportAbility = podmpriv->SupportAbility; - break; - case HAL_PHYDM_ABILITY_RESTORE: - /* restore dm flag */ - podmpriv->SupportAbility = podmpriv->BK_SupportAbility; - break; - case HAL_PHYDM_ABILITY_SET: - podmpriv->SupportAbility = ability; - break; - case HAL_PHYDM_ABILITY_GET: - result = podmpriv->SupportAbility; + default: break; } - return result; } - BOOLEAN eqNByte( u8 *str1, @@ -7925,8 +9688,13 @@ ParseQualifiedString( return _FALSE; i = (*Start); - while ((c = In[(*Start)++]) != RightQualifier) - ; /* find ']' */ + c = In[(*Start)++]; + while (c != RightQualifier && c != '\0') + c = In[(*Start)++]; + + if (c == '\0') + return _FALSE; + j = (*Start) - 2; strncpy((char *)Out, (const char *)(In + i), j - i + 1); @@ -7956,34 +9724,37 @@ void rtw_hal_check_rxfifo_full(_adapter *adapter) { struct dvobj_priv *psdpriv = adapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + struct registry_priv *regsty = &adapter->registrypriv; int save_cnt = _FALSE; - /* switch counter to RX fifo */ - if (IS_8188E(pHalData->VersionID) || - IS_8188F(pHalData->VersionID) || - IS_8812_SERIES(pHalData->VersionID) || - IS_8821_SERIES(pHalData->VersionID) || - IS_8723B_SERIES(pHalData->VersionID) || - IS_8192E(pHalData->VersionID) || - IS_8703B_SERIES(pHalData->VersionID) || - IS_8723D_SERIES(pHalData->VersionID)) { - rtw_write8(adapter, REG_RXERR_RPT + 3, rtw_read8(adapter, REG_RXERR_RPT + 3) | 0xa0); - save_cnt = _TRUE; - } else { - /* todo: other chips */ - } + if (regsty->check_hw_status == 1) { + /* switch counter to RX fifo */ + if (IS_8188E(pHalData->version_id) || + IS_8188F(pHalData->version_id) || + IS_8812_SERIES(pHalData->version_id) || + IS_8821_SERIES(pHalData->version_id) || + IS_8723B_SERIES(pHalData->version_id) || + IS_8192E(pHalData->version_id) || + IS_8703B_SERIES(pHalData->version_id) || + IS_8723D_SERIES(pHalData->version_id)) { + rtw_write8(adapter, REG_RXERR_RPT + 3, rtw_read8(adapter, REG_RXERR_RPT + 3) | 0xa0); + save_cnt = _TRUE; + } else { + /* todo: other chips */ + } - if (save_cnt) { - pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow; - pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT); - pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow; - } else { - /* special value to indicate no implementation */ - pdbgpriv->dbg_rx_fifo_last_overflow = 1; - pdbgpriv->dbg_rx_fifo_curr_overflow = 1; - pdbgpriv->dbg_rx_fifo_diff_overflow = 1; + if (save_cnt) { + pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow; + pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT); + pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow; + } else { + /* special value to indicate no implementation */ + pdbgpriv->dbg_rx_fifo_last_overflow = 1; + pdbgpriv->dbg_rx_fifo_curr_overflow = 1; + pdbgpriv->dbg_rx_fifo_diff_overflow = 1; + } } } @@ -8165,7 +9936,7 @@ void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; struct sta_info *psta = prframe->u.hdr.psta; - PODM_PHY_INFO_T pPhyInfo = (PODM_PHY_INFO_T)(&pattrib->phy_info); + struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)(&pattrib->phy_info); struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info; psample_pkt_rssi->data_rate = pattrib->data_rate; ptr = prframe->u.hdr.rx_data; @@ -8176,36 +9947,35 @@ void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe) if (precvpriv->store_law_data_flag) { isCCKrate = (pattrib->data_rate <= DESC_RATE11M) ? TRUE : FALSE; - psample_pkt_rssi->pwdball = pPhyInfo->RxPWDBAll; - psample_pkt_rssi->pwr_all = pPhyInfo->RecvSignalPower; + psample_pkt_rssi->pwdball = p_phy_info->rx_pwdb_all; + psample_pkt_rssi->pwr_all = p_phy_info->recv_signal_power; for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) { - psample_pkt_rssi->mimo_signal_strength[rf_path] = pPhyInfo->RxMIMOSignalStrength[rf_path]; - psample_pkt_rssi->mimo_signal_quality[rf_path] = pPhyInfo->RxMIMOSignalQuality[rf_path]; + psample_pkt_rssi->mimo_signal_strength[rf_path] = p_phy_info->rx_mimo_signal_strength[rf_path]; + psample_pkt_rssi->mimo_signal_quality[rf_path] = p_phy_info->rx_mimo_signal_quality[rf_path]; if (!isCCKrate) { - psample_pkt_rssi->ofdm_pwr[rf_path] = pPhyInfo->RxPwr[rf_path]; - psample_pkt_rssi->ofdm_snr[rf_path] = pPhyInfo->RxSNR[rf_path]; + psample_pkt_rssi->ofdm_pwr[rf_path] = p_phy_info->rx_pwr[rf_path]; + psample_pkt_rssi->ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path]; } } #ifdef DBG_RX_DFRAME_RAW_DATA - if (dframe_type == WIFI_DATA_TYPE || dframe_type == WIFI_QOS_DATA_TYPE) { + if ((dframe_type == WIFI_DATA_TYPE) || (dframe_type == WIFI_QOS_DATA_TYPE) || (padapter->registrypriv.mp_mode == 1)) { /*RTW_INFO("=>%s WIFI_DATA_TYPE or WIFI_QOS_DATA_TYPE\n", __FUNCTION__);*/ if (psta) { psta_dframe_info = &psta->sta_dframe_info; /*RTW_INFO("=>%s psta->hwaddr="MAC_FMT" !\n", __FUNCTION__, MAC_ARG(psta->hwaddr));*/ - if (_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN) != _TRUE) { - + if ((_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN) != _TRUE) || (padapter->registrypriv.mp_mode == 1)) { psta_dframe_info->sta_data_rate = pattrib->data_rate; psta_dframe_info->sta_sgi = pattrib->sgi; psta_dframe_info->sta_bw_mode = pattrib->bw; for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) { - psta_dframe_info->sta_mimo_signal_strength[rf_path] = (pPhyInfo->RxMIMOSignalStrength[rf_path]);/*Percentage to dbm*/ + psta_dframe_info->sta_mimo_signal_strength[rf_path] = (p_phy_info->rx_mimo_signal_strength[rf_path]);/*Percentage to dbm*/ if (!isCCKrate) { - psta_dframe_info->sta_ofdm_snr[rf_path] = pPhyInfo->RxSNR[rf_path]; - psta_dframe_info->sta_RxPwr[rf_path] = pPhyInfo->RxPwr[rf_path]; + psta_dframe_info->sta_ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path]; + psta_dframe_info->sta_RxPwr[rf_path] = p_phy_info->rx_pwr[rf_path]; } } } @@ -8418,23 +10188,27 @@ void rtw_dump_cur_efuse(PADAPTER padapter) EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapsize, _FALSE); if (mapsize <= 0 || mapsize > EEPROM_MAX_SIZE) { - RTW_INFO("wrong map size %d\n", mapsize); + RTW_ERR("wrong map size %d\n", mapsize); return; } if (hal_data->efuse_file_status == EFUSE_FILE_LOADED) - RTW_INFO("Use EFUSE FILE\n"); + RTW_INFO("EFUSE FILE\n"); else RTW_INFO("HW EFUSE\n"); #ifdef CONFIG_RTW_DEBUG -#ifdef PLATFORM_LINUX - RTW_INFO("eFuse Content:\n"); - print_hex_dump(KERN_DEBUG, "eFuse ", - DUMP_PREFIX_OFFSET, 16, 1, - hal_data->efuse_eeprom_data, mapsize, false); -#endif /* PLATFORM_LINUX */ -#endif /* CONFIG_RTW_DEBUG */ + for (i = 0; i < mapsize; i++) { + if (i % 16 == 0) + RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i); + + _RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s" + , hal_data->efuse_eeprom_data[i] + , ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? " " : " ") + ); + } + _RTW_PRINT_SEL(RTW_DBGDUMP, "\n"); +#endif } @@ -8452,12 +10226,13 @@ u32 Hal_readPGDataFromConfigFile(PADAPTER padapter) return _FALSE; } - ret = rtw_efuse_file_read(padapter, EFUSE_MAP_PATH, hal_data->efuse_eeprom_data, maplen); - if (ret == _FALSE) - ret = rtw_read_efuse_from_file(EFUSE_MAP_PATH, hal_data->efuse_eeprom_data); + ret = rtw_read_efuse_from_file(EFUSE_MAP_PATH, hal_data->efuse_eeprom_data, maplen); hal_data->efuse_file_status = ((ret == _FAIL) ? EFUSE_FILE_FAILED : EFUSE_FILE_LOADED); + if (hal_data->efuse_file_status == EFUSE_FILE_LOADED) + rtw_dump_cur_efuse(padapter); + return ret; } @@ -8467,8 +10242,8 @@ u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr) u32 ret = _FAIL; if (rtw_read_macaddr_from_file(WIFIMAC_PATH, mac_addr) == _SUCCESS - && rtw_check_invalid_mac_address(mac_addr, _TRUE) == _FALSE - ) { + && rtw_check_invalid_mac_address(mac_addr, _TRUE) == _FALSE + ) { hal_data->macaddr_file_status = MACADDR_FILE_LOADED; ret = _SUCCESS; } else @@ -8586,7 +10361,7 @@ void rtw_bb_rf_gain_offset(_adapter *padapter) res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff); RTW_INFO("Offset RF Gain. before reg 0x7f=0x%08x\n", res); - PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18 | BIT17 | BIT16 | BIT15, target); + phy_set_rf_reg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18 | BIT17 | BIT16 | BIT15, target); res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff); RTW_INFO("Offset RF Gain. After reg 0x7f=0x%08x\n", res); @@ -8756,10 +10531,18 @@ void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer) { struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct registry_priv *registry_par = &padapter->registrypriv; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); u8 cur_wireless_mode = WIRELESS_INVALID; #ifdef CONFIG_USB_RX_AGGREGATION + if (!registry_par->dynamic_agg_enable) + return; + +#ifdef RTW_HALMAC + if (IS_HARDWARE_TYPE_8822BU(padapter)) + rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, NULL); +#else /* !RTW_HALMAC */ if (IS_HARDWARE_TYPE_8821U(padapter)) { /* || IS_HARDWARE_TYPE_8192EU(padapter)) */ /* This AGG_PH_TH only for UsbRxAggMode == USB_RX_AGG_USB */ if ((pHalData->rxagg_mode == RX_AGG_USB) && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { @@ -8796,7 +10579,9 @@ void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer) rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode); #endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */ } -#endif +#endif /* RTW_HALMAC */ +#endif /* CONFIG_USB_RX_AGGREGATION */ + } /* bus-agg check for SoftAP mode */ @@ -9080,7 +10865,7 @@ void rtw_hal_ch_sw_iqk_info_backup(_adapter *padapter) u8 i; /* If it's an existed record, overwrite it */ - res = rtw_hal_ch_sw_iqk_info_search(padapter, pHalData->CurrentChannel, pHalData->CurrentChannelBW); + res = rtw_hal_ch_sw_iqk_info_search(padapter, pHalData->current_channel, pHalData->current_channel_bw); if ((res >= 0) && (res < MAX_IQK_INFO_BACKUP_CHNL_NUM)) { rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[res])); return; @@ -9118,42 +10903,42 @@ void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun return; } if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/ - - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x3); - mac_cck_ok = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0); - mac_ofdm_ok = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x6); - mac_ht_ok = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/ + + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x3); + mac_cck_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0); + mac_ofdm_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x6); + mac_ht_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ mac_vht_ok = 0; if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0); - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT26, 0x1); - mac_vht_ok = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/ - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/ - } - - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x4); - mac_cck_err = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1); - mac_ofdm_err = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x7); - mac_ht_err = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0); + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1); + mac_vht_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/ + } + + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x4); + mac_cck_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1); + mac_ofdm_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x7); + mac_ht_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ mac_vht_err = 0; if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1); - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT26, 0x1); - mac_vht_err = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/ - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1); + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1); + mac_vht_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/ } - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x5); - mac_cck_fa = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x2); - mac_ofdm_fa = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x9); - mac_ht_fa = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x5); + mac_cck_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x2); + mac_ofdm_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x9); + mac_ht_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ /* Mac_DropPacket */ rtw_write32(padapter, REG_RXERR_RPT, (rtw_read32(padapter, REG_RXERR_RPT) & 0x0FFFFFFF) | Mac_DropPacket); @@ -9173,11 +10958,11 @@ void rtw_reset_mac_rx_counters(_adapter *padapter) if (IS_HARDWARE_TYPE_8703B(padapter) || IS_HARDWARE_TYPE_8723D(padapter) || IS_HARDWARE_TYPE_8188F(padapter)) - PHY_SetMacReg(padapter, REG_RCR, BIT19, 0x1); + phy_set_mac_reg(padapter, REG_RCR, BIT19, 0x1); /* reset mac counter */ - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT27, 0x1); - PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT27, 0x0); + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x1); + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x0); } void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter) @@ -9188,28 +10973,28 @@ void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun return; } if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { - cckok = PHY_QueryBBReg(padapter, 0xF04, 0x3FFF); /* [13:0] */ - ofdmok = PHY_QueryBBReg(padapter, 0xF14, 0x3FFF); /* [13:0] */ - htok = PHY_QueryBBReg(padapter, 0xF10, 0x3FFF); /* [13:0] */ - vht_ok = PHY_QueryBBReg(padapter, 0xF0C, 0x3FFF); /* [13:0] */ - cckcrc = PHY_QueryBBReg(padapter, 0xF04, 0x3FFF0000); /* [29:16] */ - ofdmcrc = PHY_QueryBBReg(padapter, 0xF14, 0x3FFF0000); /* [29:16] */ - htcrc = PHY_QueryBBReg(padapter, 0xF10, 0x3FFF0000); /* [29:16] */ - vht_err = PHY_QueryBBReg(padapter, 0xF0C, 0x3FFF0000); /* [29:16] */ - CCK_FA = PHY_QueryBBReg(padapter, 0xA5C, bMaskLWord); - OFDM_FA = PHY_QueryBBReg(padapter, 0xF48, bMaskLWord); + cckok = phy_query_bb_reg(padapter, 0xF04, 0x3FFF); /* [13:0] */ + ofdmok = phy_query_bb_reg(padapter, 0xF14, 0x3FFF); /* [13:0] */ + htok = phy_query_bb_reg(padapter, 0xF10, 0x3FFF); /* [13:0] */ + vht_ok = phy_query_bb_reg(padapter, 0xF0C, 0x3FFF); /* [13:0] */ + cckcrc = phy_query_bb_reg(padapter, 0xF04, 0x3FFF0000); /* [29:16] */ + ofdmcrc = phy_query_bb_reg(padapter, 0xF14, 0x3FFF0000); /* [29:16] */ + htcrc = phy_query_bb_reg(padapter, 0xF10, 0x3FFF0000); /* [29:16] */ + vht_err = phy_query_bb_reg(padapter, 0xF0C, 0x3FFF0000); /* [29:16] */ + CCK_FA = phy_query_bb_reg(padapter, 0xA5C, bMaskLWord); + OFDM_FA = phy_query_bb_reg(padapter, 0xF48, bMaskLWord); } else { - cckok = PHY_QueryBBReg(padapter, 0xF88, bMaskDWord); - ofdmok = PHY_QueryBBReg(padapter, 0xF94, bMaskLWord); - htok = PHY_QueryBBReg(padapter, 0xF90, bMaskLWord); + cckok = phy_query_bb_reg(padapter, 0xF88, bMaskDWord); + ofdmok = phy_query_bb_reg(padapter, 0xF94, bMaskLWord); + htok = phy_query_bb_reg(padapter, 0xF90, bMaskLWord); vht_ok = 0; - cckcrc = PHY_QueryBBReg(padapter, 0xF84, bMaskDWord); - ofdmcrc = PHY_QueryBBReg(padapter, 0xF94, bMaskHWord); - htcrc = PHY_QueryBBReg(padapter, 0xF90, bMaskHWord); + cckcrc = phy_query_bb_reg(padapter, 0xF84, bMaskDWord); + ofdmcrc = phy_query_bb_reg(padapter, 0xF94, bMaskHWord); + htcrc = phy_query_bb_reg(padapter, 0xF90, bMaskHWord); vht_err = 0; - OFDM_FA = PHY_QueryBBReg(padapter, 0xCF0, bMaskLWord) + PHY_QueryBBReg(padapter, 0xCF2, bMaskLWord) + - PHY_QueryBBReg(padapter, 0xDA2, bMaskLWord) + PHY_QueryBBReg(padapter, 0xDA4, bMaskLWord) + - PHY_QueryBBReg(padapter, 0xDA6, bMaskLWord) + PHY_QueryBBReg(padapter, 0xDA8, bMaskLWord); + OFDM_FA = phy_query_bb_reg(padapter, 0xCF0, bMaskLWord) + phy_query_bb_reg(padapter, 0xCF2, bMaskLWord) + + phy_query_bb_reg(padapter, 0xDA2, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA4, bMaskLWord) + + phy_query_bb_reg(padapter, 0xDA6, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA8, bMaskLWord); CCK_FA = (rtw_read8(padapter, 0xA5B) << 8) | (rtw_read8(padapter, 0xA5C)); } @@ -9224,8 +11009,8 @@ void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun void rtw_reset_phy_trx_ok_counters(_adapter *padapter) { if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { - PHY_SetBBReg(padapter, 0xB58, BIT0, 0x1); - PHY_SetBBReg(padapter, 0xB58, BIT0, 0x0); + phy_set_bb_reg(padapter, 0xB58, BIT0, 0x1); + phy_set_bb_reg(padapter, 0xB58, BIT0, 0x0); } } void rtw_reset_phy_rx_counters(_adapter *padapter) @@ -9234,23 +11019,23 @@ void rtw_reset_phy_rx_counters(_adapter *padapter) if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { rtw_reset_phy_trx_ok_counters(padapter); - PHY_SetBBReg(padapter, 0x9A4, BIT17, 0x1);/* reset OFDA FA counter */ - PHY_SetBBReg(padapter, 0x9A4, BIT17, 0x0); + phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x1);/* reset OFDA FA counter */ + phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x0); - PHY_SetBBReg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */ - PHY_SetBBReg(padapter, 0xA2C, BIT15, 0x1); + phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */ + phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1); } else { - PHY_SetBBReg(padapter, 0xF14, BIT16, 0x1); + phy_set_bb_reg(padapter, 0xF14, BIT16, 0x1); rtw_msleep_os(10); - PHY_SetBBReg(padapter, 0xF14, BIT16, 0x0); + phy_set_bb_reg(padapter, 0xF14, BIT16, 0x0); - PHY_SetBBReg(padapter, 0xD00, BIT27, 0x1);/* reset OFDA FA counter */ - PHY_SetBBReg(padapter, 0xC0C, BIT31, 0x1);/* reset OFDA FA counter */ - PHY_SetBBReg(padapter, 0xD00, BIT27, 0x0); - PHY_SetBBReg(padapter, 0xC0C, BIT31, 0x0); + phy_set_bb_reg(padapter, 0xD00, BIT27, 0x1);/* reset OFDA FA counter */ + phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x1);/* reset OFDA FA counter */ + phy_set_bb_reg(padapter, 0xD00, BIT27, 0x0); + phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x0); - PHY_SetBBReg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */ - PHY_SetBBReg(padapter, 0xA2C, BIT15, 0x1); + phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */ + phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1); } } #ifdef DBG_RX_COUNTER_DUMP @@ -9340,7 +11125,7 @@ void rtw_get_noise(_adapter *padapter) LeaveAllPowerSaveModeDirect(padapter); rtw_hal_set_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &info, _FALSE); - /* ODM_InbandNoise_Monitor(podmpriv,_TRUE,0x20,100); */ + /* odm_inband_noise_monitor(podmpriv,_TRUE,0x20,100); */ rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &(info.chan), &(padapter->recvpriv.noise)); #ifdef DBG_NOISE_MONITOR @@ -9353,12 +11138,12 @@ void rtw_get_noise(_adapter *padapter) u8 rtw_get_current_tx_sgi(_adapter *padapter, u8 macid) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct _rate_adaptive_table_ *pRA_Table = &pDM_Odm->dm_ra_table; u8 curr_tx_sgi = 0; #if defined(CONFIG_RTL8188E) - curr_tx_sgi = ODM_RA_GetDecisionRate_8188E(pDM_Odm, macid); + curr_tx_sgi = odm_ra_get_decision_rate_8188e(pDM_Odm, macid); #else curr_tx_sgi = ((pRA_Table->link_tx_rate[macid]) & 0x80) >> 7; #endif @@ -9369,12 +11154,12 @@ u8 rtw_get_current_tx_sgi(_adapter *padapter, u8 macid) u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct _rate_adaptive_table_ *pRA_Table = &pDM_Odm->dm_ra_table; u8 rate_id = 0; #if (RATE_ADAPTIVE_SUPPORT == 1) - rate_id = ODM_RA_GetDecisionRate_8188E(pDM_Odm, macid); + rate_id = odm_ra_get_decision_rate_8188e(pDM_Odm, macid); #else rate_id = (pRA_Table->link_tx_rate[macid]) & 0x7f; #endif @@ -9383,58 +11168,6 @@ u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid) } -#ifdef CONFIG_FW_C2H_DEBUG - -/* C2H RX package original is 128. -if enable CONFIG_FW_C2H_DEBUG, it should increase to 256. - C2H FW debug message: - without aggregate: - {C2H_CmdID,Seq,SubID,Len,Content[0~n]} - Content[0~n]={'a','b','c',...,'z','\n'} - with aggregate: - {C2H_CmdID,Seq,SubID,Len,Content[0~n]} - Content[0~n]={'a','b','c',...,'z','\n',Extend C2H pkt 2...} - Extend C2H pkt 2={C2H CmdID,Seq,SubID,Len,Content = {'a','b','c',...,'z','\n'}} - Author: Isaac */ - -void Debug_FwC2H(PADAPTER padapter, u8 *pdata, u8 len) -{ - int i = 0; - int cnt = 0, total_length = 0; - u8 buf[128] = {0}; - u8 more_data = _FALSE; - u8 *nextdata = NULL; - u8 test = 0; - - u8 data_len; - u8 seq_no; - - nextdata = pdata; - do { - data_len = *(nextdata + 1); - seq_no = *(nextdata + 2); - - for (i = 0 ; i < data_len - 2 ; i++) { - cnt += sprintf((buf + cnt), "%c", nextdata[3 + i]); - - if (nextdata[3 + i] == 0x0a && nextdata[4 + i] == 0xff) - more_data = _TRUE; - else if (nextdata[3 + i] == 0x0a && nextdata[4 + i] != 0xff) - more_data = _FALSE; - } - - RTW_INFO("[RTKFW, SEQ=%d]: %s", seq_no, buf); - data_len += 3; - total_length += data_len; - - if (more_data == _TRUE) { - _rtw_memset(buf, '\0', 128); - cnt = 0; - nextdata = (pdata + total_length); - } - } while (more_data == _TRUE); -} -#endif /*CONFIG_FW_C2H_DEBUG*/ void update_IOT_info(_adapter *padapter) { struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; @@ -9449,14 +11182,10 @@ void update_IOT_info(_adapter *padapter) case HT_IOT_PEER_RALINK: pmlmeinfo->turboMode_cts2self = 0; pmlmeinfo->turboMode_rtsen = 1; - /* disable high power */ - rtw_phydm_func_clr(padapter, ODM_BB_DYNAMIC_TXPWR); break; case HT_IOT_PEER_REALTEK: /* rtw_write16(padapter, 0x4cc, 0xffff); */ /* rtw_write16(padapter, 0x546, 0x01c0); */ - /* disable high power */ - rtw_phydm_func_clr(padapter, ODM_BB_DYNAMIC_TXPWR); break; default: pmlmeinfo->turboMode_cts2self = 0; @@ -9500,13 +11229,13 @@ void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap) case RTL8188E: case RTL8188F: /* write 0x24[16:11] = 0x24[22:17] = CrystalCap */ - PHY_SetBBReg(adapter, REG_AFE_XTAL_CTRL, 0x007FF800, (crystal_cap | (crystal_cap << 6))); + phy_set_bb_reg(adapter, REG_AFE_XTAL_CTRL, 0x007FF800, (crystal_cap | (crystal_cap << 6))); break; #endif #if defined(CONFIG_RTL8812A) case RTL8812: /* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */ - PHY_SetBBReg(adapter, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6))); + phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6))); break; #endif #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \ @@ -9518,13 +11247,13 @@ void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap) case RTL8821: case RTL8192E: /* write 0x2C[23:18] = 0x2C[17:12] = CrystalCap */ - PHY_SetBBReg(adapter, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6))); + phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6))); break; #endif #if defined(CONFIG_RTL8814A) case RTL8814A: /* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap*/ - PHY_SetBBReg(adapter, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6))); + phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6))); break; #endif #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) @@ -9533,8 +11262,8 @@ void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap) case RTL8821C: /* write 0x28[6:1] = 0x24[30:25] = CrystalCap */ crystal_cap = crystal_cap & 0x3F; - PHY_SetBBReg(adapter, REG_AFE_XTAL_CTRL, 0x7E000000, crystal_cap); - PHY_SetBBReg(adapter, REG_AFE_PLL_CTRL, 0x7E, crystal_cap); + phy_set_bb_reg(adapter, REG_AFE_XTAL_CTRL, 0x7E000000, crystal_cap); + phy_set_bb_reg(adapter, REG_AFE_PLL_CTRL, 0x7E, crystal_cap); break; #endif default: @@ -9652,7 +11381,11 @@ void dump_hal_spec(void *sel, _adapter *adapter) RTW_PRINT_SEL(sel, "macid_num:%u\n", hal_spec->macid_num); RTW_PRINT_SEL(sel, "sec_cap:0x%02x\n", hal_spec->sec_cap); RTW_PRINT_SEL(sel, "sec_cam_ent_num:%u\n", hal_spec->sec_cam_ent_num); - RTW_PRINT_SEL(sel, "nss_num:%u\n", hal_spec->nss_num); + RTW_PRINT_SEL(sel, "rfpath_num_2g:%u\n", hal_spec->rfpath_num_2g); + RTW_PRINT_SEL(sel, "rfpath_num_5g:%u\n", hal_spec->rfpath_num_5g); + RTW_PRINT_SEL(sel, "max_tx_cnt:%u\n", hal_spec->max_tx_cnt); + RTW_PRINT_SEL(sel, "tx_nss_num:%u\n", hal_spec->tx_nss_num); + RTW_PRINT_SEL(sel, "rx_nss_num:%u\n", hal_spec->rx_nss_num); RTW_PRINT_SEL(sel, "band_cap:"); for (i = 0; i < BAND_CAP_BIT_NUM; i++) { @@ -9796,13 +11529,14 @@ void ResumeTxBeacon(_adapter *padapter) /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ /* which should be read from register to a global variable. */ - RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n")); + rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, + rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) | BIT(6)); - pHalData->RegFwHwTxQCtrl |= BIT(6); - rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl); - rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff); - pHalData->RegReg542 |= BIT(0); - rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542); + /*TBTT hold time :4ms 0x540[19:8]*/ + rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, + TBTT_PROBIHIT_HOLD_TIME & 0xFF); + rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, + (rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROBIHIT_HOLD_TIME >> 8)); } void StopTxBeacon(_adapter *padapter) @@ -9813,13 +11547,12 @@ void StopTxBeacon(_adapter *padapter) /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ /* which should be read from register to a global variable. */ - RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n")); + rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, + rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) & (~BIT6)); - pHalData->RegFwHwTxQCtrl &= ~BIT(6); - rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl); rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64); - pHalData->RegReg542 &= ~BIT(0); - rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542); + rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, + (rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0)); /*CheckFwRsvdPageContent(padapter);*/ /* 2010.06.23. Added by tynli. */ } @@ -9914,3 +11647,120 @@ void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_B } } #endif + +#ifdef CONFIG_PHY_CAPABILITY_QUERY +void rtw_dump_phy_cap_by_phydmapi(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + struct phy_spec_t *phy_spec = &pHalData->phy_spec; + + RTW_PRINT_SEL(sel, "[PHY SPEC] TRx Capability : 0x%08x\n", phy_spec->trx_cap); + RTW_PRINT_SEL(sel, "[PHY SPEC] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index [15:8]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] Rx Path Num Index : %d\n\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index [7:0]*/ + + RTW_PRINT_SEL(sel, "[PHY SPEC] STBC Capability : 0x%08x\n", phy_spec->stbc_cap); + RTW_PRINT_SEL(sel, "[PHY SPEC] VHT STBC Tx : %s\n", ((phy_spec->stbc_cap >> 24) & 0xFF) ? "Supported" : "N/A"); /*VHT STBC Tx [31:24]*/ + /*VHT STBC Rx [23:16] + 0 = not support + 1 = support for 1 spatial stream + 2 = support for 1 or 2 spatial streams + 3 = support for 1 or 2 or 3 spatial streams + 4 = support for 1 or 2 or 3 or 4 spatial streams*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] VHT STBC Rx :%d\n", ((phy_spec->stbc_cap >> 16) & 0xFF)); + RTW_PRINT_SEL(sel, "[PHY SPEC] HT STBC Tx : %s\n", ((phy_spec->stbc_cap >> 8) & 0xFF) ? "Supported" : "N/A"); /*HT STBC Tx [15:8]*/ + /*HT STBC Rx [7:0] + 0 = not support + 1 = support for 1 spatial stream + 2 = support for 1 or 2 spatial streams + 3 = support for 1 or 2 or 3 spatial streams*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] HT STBC Rx : %d\n\n", (phy_spec->stbc_cap & 0xFF)); + + RTW_PRINT_SEL(sel, "[PHY SPEC] LDPC Capability : 0x%08x\n", phy_spec->ldpc_cap); + RTW_PRINT_SEL(sel, "[PHY SPEC] VHT LDPC Tx : %s\n", ((phy_spec->ldpc_cap >> 24) & 0xFF) ? "Supported" : "N/A"); /*VHT LDPC Tx [31:24]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] VHT LDPC Rx : %s\n", ((phy_spec->ldpc_cap >> 16) & 0xFF) ? "Supported" : "N/A"); /*VHT LDPC Rx [23:16]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] HT LDPC Tx : %s\n", ((phy_spec->ldpc_cap >> 8) & 0xFF) ? "Supported" : "N/A"); /*HT LDPC Tx [15:8]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] HT LDPC Rx : %s\n\n", (phy_spec->ldpc_cap & 0xFF) ? "Supported" : "N/A"); /*HT LDPC Rx [7:0]*/ + #ifdef CONFIG_BEAMFORMING + RTW_PRINT_SEL(sel, "[PHY SPEC] TxBF Capability : 0x%08x\n", phy_spec->txbf_cap); + RTW_PRINT_SEL(sel, "[PHY SPEC] VHT MU Bfer : %s\n", ((phy_spec->txbf_cap >> 28) & 0xF) ? "Supported" : "N/A"); /*VHT MU Bfer [31:28]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] VHT MU Bfee : %s\n", ((phy_spec->txbf_cap >> 24) & 0xF) ? "Supported" : "N/A"); /*VHT MU Bfee [27:24]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] VHT SU Bfer : %s\n", ((phy_spec->txbf_cap >> 20) & 0xF) ? "Supported" : "N/A"); /*VHT SU Bfer [23:20]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] VHT SU Bfee : %s\n", ((phy_spec->txbf_cap >> 16) & 0xF) ? "Supported" : "N/A"); /*VHT SU Bfee [19:16]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] HT Bfer : %s\n", ((phy_spec->txbf_cap >> 4) & 0xF) ? "Supported" : "N/A"); /*HT Bfer [7:4]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] HT Bfee : %s\n\n", (phy_spec->txbf_cap & 0xF) ? "Supported" : "N/A"); /*HT Bfee [3:0]*/ + + RTW_PRINT_SEL(sel, "[PHY SPEC] TxBF parameter : 0x%08x\n", phy_spec->txbf_param); + RTW_PRINT_SEL(sel, "[PHY SPEC] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/ + RTW_PRINT_SEL(sel, "[PHY SPEC] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/ + #endif +} +#else +void rtw_dump_phy_cap_by_hal(void *sel, _adapter *adapter) +{ + u8 phy_cap = _FALSE; + + /* STBC */ + rtw_hal_get_def_var(adapter, HAL_DEF_TX_STBC, (u8 *)&phy_cap); + RTW_PRINT_SEL(sel, "[HAL] STBC Tx : %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A"); + + phy_cap = _FALSE; + rtw_hal_get_def_var(adapter, HAL_DEF_RX_STBC, (u8 *)&phy_cap); + RTW_PRINT_SEL(sel, "[HAL] STBC Rx : %s\n\n", (_TRUE == phy_cap) ? "Supported" : "N/A"); + + /* LDPC support */ + phy_cap = _FALSE; + rtw_hal_get_def_var(adapter, HAL_DEF_TX_LDPC, (u8 *)&phy_cap); + RTW_PRINT_SEL(sel, "[HAL] LDPC Tx : %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A"); + + phy_cap = _FALSE; + rtw_hal_get_def_var(adapter, HAL_DEF_RX_LDPC, (u8 *)&phy_cap); + RTW_PRINT_SEL(sel, "[HAL] LDPC Rx : %s\n\n", (_TRUE == phy_cap) ? "Supported" : "N/A"); + + #ifdef CONFIG_BEAMFORMING + phy_cap = _FALSE; + rtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&phy_cap); + RTW_PRINT_SEL(sel, "[HAL] Beamformer: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A"); + + phy_cap = _FALSE; + rtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&phy_cap); + RTW_PRINT_SEL(sel, "[HAL] Beamformee: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A"); + + phy_cap = _FALSE; + rtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMER, &phy_cap); + RTW_PRINT_SEL(sel, "[HAL] VHT MU Beamformer: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A"); + + phy_cap = _FALSE; + rtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMEE, &phy_cap); + RTW_PRINT_SEL(sel, "[HAL] VHT MU Beamformee: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A"); + #endif +} +#endif +void rtw_dump_phy_cap(void *sel, _adapter *adapter) +{ + RTW_PRINT_SEL(sel, "\n ======== PHY Capability ========\n"); +#ifdef CONFIG_PHY_CAPABILITY_QUERY + rtw_dump_phy_cap_by_phydmapi(sel, adapter); +#else + rtw_dump_phy_cap_by_hal(sel, adapter); +#endif +} + +void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter) +{ + PHAL_DATA_TYPE hal; + struct PHY_DM_STRUCT *p_dm_odm; + + hal = GET_HAL_DATA(adapter); + p_dm_odm = &hal->odmpriv; + + if (hal->RegIQKFWOffload) + rtw_sctx_init(&hal->iqk_sctx, 0); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_IQKFWOFFLOAD, hal->RegIQKFWOffload); + RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload?"enable":"disable"); +} + diff --git a/hal/hal_com_c2h.h b/hal/hal_com_c2h.h index 24599ec..d6cca9a 100644 --- a/hal/hal_com_c2h.h +++ b/hal/hal_com_c2h.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,35 +11,66 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __COMMON_C2H_H__ #define __COMMON_C2H_H__ +#define C2H_TYPE_REG 0 +#define C2H_TYPE_PKT 1 + +/* +* C2H event format: +* Fields TRIGGER PAYLOAD SEQ PLEN ID +* BITS [127:120] [119:16] [15:8] [7:4] [3:0] +*/ +#define C2H_ID(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 4) +#define C2H_PLEN(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)), 4, 4) +#define C2H_SEQ(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8) +#define C2H_PAYLOAD(_c2h) (((u8*)(_c2h)) + 2) + +#define SET_C2H_ID(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 4, _val) +#define SET_C2H_PLEN(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 4, 4, _val) +#define SET_C2H_SEQ(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1 , 0, 8, _val) + +/* +* C2H event format: +* Fields TRIGGER PLEN PAYLOAD SEQ ID +* BITS [127:120] [119:112] [111:16] [15:8] [7:0] +*/ +#define C2H_ID_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 8) +#define C2H_SEQ_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8) +#define C2H_PAYLOAD_88XX(_c2h) (((u8*)(_c2h)) + 2) +#define C2H_PLEN_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 14, 0, 8) +#define C2H_TRIGGER_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 15, 0, 8) + +#define SET_C2H_ID_88XX(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 8, _val) +#define SET_C2H_SEQ_88XX(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1, 0, 8, _val) +#define SET_C2H_PLEN_88XX(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 14, 0, 8, _val) + typedef enum _C2H_EVT { C2H_DBG = 0x00, C2H_LB = 0x01, C2H_TXBF = 0x02, C2H_CCX_TX_RPT = 0x03, + C2H_AP_REQ_TXRPT = 0x04, C2H_FW_SCAN_COMPLETE = 0x7, C2H_BT_INFO = 0x09, C2H_BT_MP_INFO = 0x0B, C2H_RA_RPT = 0x0C, + C2H_SPC_STAT = 0x0D, C2H_RA_PARA_RPT = 0x0E, C2H_FW_CHNL_SWITCH_COMPLETE = 0x10, C2H_IQK_FINISH = 0x11, C2H_MAILBOX_STATUS = 0x15, C2H_P2P_RPORT = 0x16, -#ifdef CONFIG_MCC_MODE C2H_MCC = 0x17, -#endif /* CONFIG_MCC_MODE */ C2H_MAC_HIDDEN_RPT = 0x19, + C2H_MAC_HIDDEN_RPT_2 = 0x1A, C2H_BCN_EARLY_RPT = 0x1E, - C2H_BT_SCOREBOARD_STATUS = 0x20, + C2H_DEFEATURE_DBG = 0x22, + C2H_CUSTOMER_STR_RPT = 0x24, + C2H_CUSTOMER_STR_RPT_2 = 0x25, + C2H_DEFEATURE_RSVD = 0xFD, C2H_EXTEND = 0xff, } C2H_EVT; @@ -47,8 +78,37 @@ typedef enum _EXTEND_C2H_EVT { EXTEND_C2H_DBG_PRINT = 0 } EXTEND_C2H_EVT; +#define C2H_REG_LEN 16 + +/* C2H_IQK_FINISH, 0x11 */ +#define IQK_OFFLOAD_LEN 1 +void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len); +int c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms); +#define rtl8812_iqk_wait c2h_iqk_offload_wait /* TODO: remove this after phydm call c2h_iqk_offload_wait instead */ + +#ifdef CONFIG_RTW_MAC_HIDDEN_RPT +/* C2H_MAC_HIDDEN_RPT, 0x19 */ #define MAC_HIDDEN_RPT_LEN 8 int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len); + +/* C2H_MAC_HIDDEN_RPT_2, 0x1A */ +#define MAC_HIDDEN_RPT_2_LEN 5 +int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len); int hal_read_mac_hidden_rpt(_adapter *adapter); +#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */ + +/* C2H_DEFEATURE_DBG, 0x22 */ +#define DEFEATURE_DBG_LEN 1 +int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len); + +#ifdef CONFIG_RTW_CUSTOMER_STR +/* C2H_CUSTOMER_STR_RPT, 0x24 */ +#define CUSTOMER_STR_RPT_LEN 8 +int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len); + +/* C2H_CUSTOMER_STR_RPT_2, 0x25 */ +#define CUSTOMER_STR_RPT_2_LEN 8 +int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len); +#endif /* CONFIG_RTW_CUSTOMER_STR */ #endif /* __COMMON_C2H_H__ */ diff --git a/hal/hal_com_phycfg.c b/hal/hal_com_phycfg.c index f912e39..3f3c491 100644 --- a/hal/hal_com_phycfg.c +++ b/hal/hal_com_phycfg.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,2417 +11,3140 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_COM_PHYCFG_C_ #include #include -/* -* rtw_regsty_get_target_tx_power - -* -* Return dBm or -1 for undefined -*/ -s8 rtw_regsty_get_target_tx_power( - IN PADAPTER Adapter, - IN u8 Band, - IN u8 RfPath, - IN RATE_SECTION RateSection -) { - struct registry_priv *regsty = adapter_to_regsty(Adapter); - s8 value = 0; +#define PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) (((_pg_v) & 0xf0) >> 4) +#define PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) ((_pg_v) & 0x0f) +#define PG_TXPWR_MSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_MSB_DIFF_S4BIT(_pg_v)) +#define PG_TXPWR_LSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_LSB_DIFF_S4BIT(_pg_v)) +#define IS_PG_TXPWR_BASE_INVALID(_base) ((_base) > 63) +#define IS_PG_TXPWR_DIFF_INVALID(_diff) ((_diff) > 7 || (_diff) < -8) +#define PG_TXPWR_INVALID_BASE 255 +#define PG_TXPWR_INVALID_DIFF 8 + +#if !IS_PG_TXPWR_BASE_INVALID(PG_TXPWR_INVALID_BASE) +#error "PG_TXPWR_BASE definition has problem" +#endif - if (RfPath > RF_PATH_D) { - RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath); - return -1; - } +#if !IS_PG_TXPWR_DIFF_INVALID(PG_TXPWR_INVALID_DIFF) +#error "PG_TXPWR_DIFF definition has problem" +#endif - if (Band != BAND_ON_2_4G -#ifdef CONFIG_NL80211_BAND_5GHZ - && Band != BAND_ON_5G +#define PG_TXPWR_SRC_PG_DATA 0 +#define PG_TXPWR_SRC_IC_DEF 1 +#define PG_TXPWR_SRC_DEF 2 +#define PG_TXPWR_SRC_NUM 3 + +const char *const _pg_txpwr_src_str[] = { + "PG_DATA", + "IC_DEF", + "DEF", + "UNKNOWN" +}; + +#define pg_txpwr_src_str(src) (((src) >= PG_TXPWR_SRC_NUM) ? _pg_txpwr_src_str[PG_TXPWR_SRC_NUM] : _pg_txpwr_src_str[(src)]) + +#ifndef DBG_PG_TXPWR_READ +#define DBG_PG_TXPWR_READ 0 #endif - ) { - RTW_PRINT("%s invalid Band:%d\n", __func__, Band); - return -1; + +#if DBG_PG_TXPWR_READ +static void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt) +{ + int path, group, tx_idx; + + RTW_PRINT_SEL(sel, "2.4G\n"); + RTW_PRINT_SEL(sel, "CCK-1T base:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) + _RTW_PRINT_SEL(sel, "G%02d ", group); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) + _RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexCCK_Base[path][group]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "CCK diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dT ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->CCK_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW40-1S base:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) + _RTW_PRINT_SEL(sel, "G%02d ", group); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) + _RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "OFDM diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dT ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW20 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dS ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW40 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dS ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); +} - if (RateSection >= RATE_SECTION_NUM -#ifdef CONFIG_NL80211_BAND_5GHZ - || (Band == BAND_ON_5G && RateSection == CCK) -#endif - ) { - RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d\n", __func__ - , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath); - return -1; +static void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt) +{ + int path, group, tx_idx; + + RTW_PRINT_SEL(sel, "5G\n"); + RTW_PRINT_SEL(sel, "BW40-1S base:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (group = 0; group < MAX_CHNL_GROUP_5G; group++) + _RTW_PRINT_SEL(sel, "G%02d ", group); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (group = 0; group < MAX_CHNL_GROUP_5G; group++) + _RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "OFDM diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dT ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW20 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dS ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW40 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dS ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW80 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dS ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW80_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW160 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dS ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW160_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); +} +#endif /* DBG_PG_TXPWR_READ */ + +const struct map_t pg_txpwr_def_info = + MAP_ENT(0xB8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 168, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, + 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, + 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, + 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, + 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, + 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, + 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, + 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, + 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE) + ); - if (Band == BAND_ON_2_4G) - value = regsty->target_tx_pwr_2g[RfPath][RateSection]; -#ifdef CONFIG_NL80211_BAND_5GHZ - else /* BAND_ON_5G */ - value = regsty->target_tx_pwr_5g[RfPath][RateSection - 1]; +#ifdef CONFIG_RTL8188E +static const struct map_t rtl8188e_pg_txpwr_def_info = + MAP_ENT(0xB8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 12, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24) + ); #endif - return value; -} +#ifdef CONFIG_RTL8188F +static const struct map_t rtl8188f_pg_txpwr_def_info = + MAP_ENT(0xB8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 12, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24) + ); +#endif -bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter) { - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - int path, tx_num, band, rs; - s8 target; +#ifdef CONFIG_RTL8723B +static const struct map_t rtl8723b_pg_txpwr_def_info = + MAP_ENT(0xB8, 2, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 12, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0) + , MAPSEG_ARRAY_ENT(0x3A, 12, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0) + ); +#endif - for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { - if (!hal_is_band_support(adapter, band)) - continue; +#ifdef CONFIG_RTL8703B +static const struct map_t rtl8703b_pg_txpwr_def_info = + MAP_ENT(0xB8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 12, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02) + ); +#endif - for (path = 0; path < RF_PATH_MAX; path++) { - if (path >= hal_data->NumTotalRFPath) - break; +#ifdef CONFIG_RTL8723D +static const struct map_t rtl8723d_pg_txpwr_def_info = + MAP_ENT(0xB8, 2, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 12, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02) + , MAPSEG_ARRAY_ENT(0x3A, 12, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x02) + ); +#endif - for (rs = 0; rs < RATE_SECTION_NUM; rs++) { - tx_num = rate_section_to_tx_num(rs); - if (tx_num >= hal_spec->nss_num) - continue; +#ifdef CONFIG_RTL8192E +static const struct map_t rtl8192e_pg_txpwr_def_info = + MAP_ENT(0xB8, 2, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 14, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE) + , MAPSEG_ARRAY_ENT(0x3A, 14, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE) + ); +#endif - if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) - continue; +#ifdef CONFIG_RTL8821A +static const struct map_t rtl8821a_pg_txpwr_def_info = + MAP_ENT(0xB8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 39, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, + 0x04, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00) + ); +#endif - if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) - continue; +#ifdef CONFIG_RTL8821C +static const struct map_t rtl8821c_pg_txpwr_def_info = + MAP_ENT(0xB8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 54, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, + 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEC, 0xFF, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02) + ); +#endif - target = rtw_regsty_get_target_tx_power(adapter, band, path, rs); - if (target == -1) - return _FALSE; - } - } - } +#ifdef CONFIG_RTL8812A +static const struct map_t rtl8812a_pg_txpwr_def_info = + MAP_ENT(0xB8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 82, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, + 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, + 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0x00, 0xEE, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, + 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, + 0x00, 0xEE) + ); +#endif - return _TRUE; -} +#ifdef CONFIG_RTL8822B +static const struct map_t rtl8822b_pg_txpwr_def_info = + MAP_ENT(0xB8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 82, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, + 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, + 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0xEC, 0xEC, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, + 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, + 0xEC, 0xEC) + ); +#endif -/* -* PHY_GetTxPowerByRateBase - -* -* Return 2 times of dBm -*/ -u8 -PHY_GetTxPowerByRateBase( - IN PADAPTER Adapter, - IN u8 Band, - IN u8 RfPath, - IN u8 TxNum, - IN RATE_SECTION RateSection -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 value = 0; +#ifdef CONFIG_RTL8814A +static const struct map_t rtl8814a_pg_txpwr_def_info = + MAP_ENT(0xB8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 168, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, + 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, + 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, + 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, + 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, + 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, + 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, + 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, + 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE) + ); +#endif - if (RfPath > RF_PATH_D) { - RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath); - return 0; - } +const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter) +{ + u8 interface_type = 0; + const struct map_t *map = NULL; - if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { - RTW_PRINT("%s invalid Band:%d\n", __func__, Band); - return 0; - } + interface_type = rtw_get_intf_type(adapter); - if (RateSection >= RATE_SECTION_NUM - || (Band == BAND_ON_5G && RateSection == CCK) - ) { - RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d, TxNum:%d\n", __func__ - , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath, TxNum); - return 0; + switch (rtw_get_chip_type(adapter)) { +#ifdef CONFIG_RTL8723B + case RTL8723B: + map = &rtl8723b_pg_txpwr_def_info; + break; +#endif +#ifdef CONFIG_RTL8703B + case RTL8703B: + map = &rtl8703b_pg_txpwr_def_info; + break; +#endif +#ifdef CONFIG_RTL8723D + case RTL8723D: + map = &rtl8723d_pg_txpwr_def_info; + break; +#endif +#ifdef CONFIG_RTL8188E + case RTL8188E: + map = &rtl8188e_pg_txpwr_def_info; + break; +#endif +#ifdef CONFIG_RTL8188F + case RTL8188F: + map = &rtl8188f_pg_txpwr_def_info; + break; +#endif +#ifdef CONFIG_RTL8812A + case RTL8812: + map = &rtl8812a_pg_txpwr_def_info; + break; +#endif +#ifdef CONFIG_RTL8821A + case RTL8821: + map = &rtl8821a_pg_txpwr_def_info; + break; +#endif +#ifdef CONFIG_RTL8192E + case RTL8192E: + map = &rtl8192e_pg_txpwr_def_info; + break; +#endif +#ifdef CONFIG_RTL8814A + case RTL8814A: + map = &rtl8814a_pg_txpwr_def_info; + break; +#endif +#ifdef CONFIG_RTL8822B + case RTL8822B: + map = &rtl8822b_pg_txpwr_def_info; + break; +#endif +#ifdef CONFIG_RTL8821C + case RTL8821C: + map = &rtl8821c_pg_txpwr_def_info; + break; +#endif } - if (Band == BAND_ON_2_4G) - value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][RateSection]; - else /* BAND_ON_5G */ - value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][RateSection - 1]; + if (map == NULL) { + RTW_ERR("%s: unknown chip_type:%u\n" + , __func__, rtw_get_chip_type(adapter)); + rtw_warn_on(1); + } - return value; + return map; } -VOID -phy_SetTxPowerByRateBase( - IN PADAPTER Adapter, - IN u8 Band, - IN u8 RfPath, - IN RATE_SECTION RateSection, - IN u8 TxNum, - IN u8 Value -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - if (RfPath > RF_PATH_D) { - RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath); - return; - } +static u8 hal_chk_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 path, group, tx_idx; - if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { - RTW_PRINT("%s invalid Band:%d\n", __func__, Band); - return; - } + if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G)) + return _SUCCESS; - if (RateSection >= RATE_SECTION_NUM - || (Band == BAND_ON_5G && RateSection == CCK) - ) { - RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d, TxNum:%d\n", __func__ - , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath, TxNum); - return; + for (path = 0; path < MAX_RF_PATH; path++) { + if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) + continue; + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { + if (IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexCCK_Base[path][group]) + || IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group])) + return _FAIL; + } + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) + continue; + if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])) + return _FAIL; + } } - if (Band == BAND_ON_2_4G) - pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][RateSection] = Value; - else /* BAND_ON_5G */ - pHalData->TxPwrByRateBase5G[RfPath][TxNum][RateSection - 1] = Value; + return _SUCCESS; } -/* -* phy_get_target_tx_power - -* -* Return 2 times of dBm -*/ -u8 phy_get_target_tx_power( - IN PADAPTER Adapter, - IN u8 Band, - IN u8 RfPath, - IN RATE_SECTION RateSection -) { - struct registry_priv *regsty = adapter_to_regsty(Adapter); - s16 target_power; +static u8 hal_chk_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info) +{ +#ifdef CONFIG_IEEE80211_BAND_5GHZ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 path, group, tx_idx; - if (phy_is_tx_power_by_rate_needed(Adapter) == _FALSE && regsty->target_tx_pwr_valid == _TRUE) - target_power = 2 * rtw_regsty_get_target_tx_power(Adapter, Band, RfPath, RateSection); - else - target_power = PHY_GetTxPowerByRateBase(Adapter, Band, RfPath, rate_section_to_tx_num(RateSection), RateSection); + if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G)) + return _SUCCESS; - return target_power; + for (path = 0; path < MAX_RF_PATH; path++) { + if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) + continue; + for (group = 0; group < MAX_CHNL_GROUP_5G; group++) + if (IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group])) + return _FAIL; + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) + continue; + if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx])) + return _FAIL; + } + } +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ + return _SUCCESS; } -#ifdef TX_POWER_BY_RATE_OLD -VOID -phy_StoreTxPowerByRateBaseOld( - IN PADAPTER pAdapter -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u16 rawValue = 0; - u8 base = 0; - u8 path = 0; - - rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][7] >> 8) & 0xFF; - base = (rawValue >> 4) * 10 + (rawValue & 0xF); - phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, CCK, RF_1TX, base); - - rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][1] >> 24) & 0xFF; - base = (rawValue >> 4) * 10 + (rawValue & 0xF); - phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, OFDM, RF_1TX, base); - - rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][3] >> 24) & 0xFF; - base = (rawValue >> 4) * 10 + (rawValue & 0xF); - phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, HT_MCS0_MCS7, RF_1TX, base); +static inline void hal_init_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 path, group, tx_idx; - rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][5] >> 24) & 0xFF; - base = (rawValue >> 4) * 10 + (rawValue & 0xF); - phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, HT_MCS8_MCS15, RF_2TX, base); + if (pwr_info == NULL) + return; - rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][7] & 0xFF); - base = (rawValue >> 4) * 10 + (rawValue & 0xF); - phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, CCK, RF_1TX, base); + _rtw_memset(pwr_info, 0, sizeof(TxPowerInfo24G)); - rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][9] >> 24) & 0xFF; - base = (rawValue >> 4) * 10 + (rawValue & 0xF); - phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, OFDM, RF_1TX, base); + /* init with invalid value */ + for (path = 0; path < MAX_RF_PATH; path++) { + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { + pwr_info->IndexCCK_Base[path][group] = PG_TXPWR_INVALID_BASE; + pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE; + } + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + pwr_info->CCK_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + } + } - rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][11] >> 24) & 0xFF; - base = (rawValue >> 4) * 10 + (rawValue & 0xF); - phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, HT_MCS0_MCS7, RF_1TX, base); + /* init for dummy base and diff */ + for (path = 0; path < MAX_RF_PATH; path++) { + if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) + break; + /* 2.4G BW40 base has 1 less group than CCK base*/ + pwr_info->IndexBW40_Base[path][MAX_CHNL_GROUP_24G - 1] = 0; - rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][13] >> 24) & 0xFF; - base = (rawValue >> 4) * 10 + (rawValue & 0xF); - phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, HT_MCS8_MCS15, RF_2TX, base); + /* dummy diff */ + pwr_info->CCK_Diff[path][0] = 0; /* 2.4G CCK-1TX */ + pwr_info->BW40_Diff[path][0] = 0; /* 2.4G BW40-1S */ + } } -#endif /* TX_POWER_BY_RATE_OLD */ -VOID -phy_StoreTxPowerByRateBase( - IN PADAPTER pAdapter -) { - struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter); +static inline void hal_init_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info) +{ +#ifdef CONFIG_IEEE80211_BAND_5GHZ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 path, group, tx_idx; - u8 rate_sec_base[RATE_SECTION_NUM] = { - MGN_11M, - MGN_54M, - MGN_MCS7, - MGN_MCS15, - MGN_MCS23, - MGN_MCS31, - MGN_VHT1SS_MCS7, - MGN_VHT2SS_MCS7, - MGN_VHT3SS_MCS7, - MGN_VHT4SS_MCS7, - }; + if (pwr_info == NULL) + return; - u8 band, path, rs, tx_num, base, index; + _rtw_memset(pwr_info, 0, sizeof(TxPowerInfo5G)); + + /* init with invalid value */ + for (path = 0; path < MAX_RF_PATH; path++) { + for (group = 0; group < MAX_CHNL_GROUP_5G; group++) + pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE; + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->BW80_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->BW160_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + } + } - for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + for (path = 0; path < MAX_RF_PATH; path++) { + if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) + break; + /* dummy diff */ + pwr_info->BW40_Diff[path][0] = 0; /* 5G BW40-1S */ + } +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ +} - for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { - /* TODO: 8814A's NumTotalRFPath differs at probe(3) and up(4), need fixed - if (path >= hal_data->NumTotalRFPath) - break; - */ +#if DBG_PG_TXPWR_READ +#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) 1 +#else +#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) (_txpwr_src > PG_TXPWR_SRC_PG_DATA) +#endif - for (rs = 0; rs < RATE_SECTION_NUM; rs++) { - tx_num = rate_section_to_tx_num(rs); - if (tx_num >= hal_spec->nss_num) - continue; +u16 hal_load_pg_txpwr_info_path_2g( + _adapter *adapter, + TxPowerInfo24G *pwr_info, + u32 path, + u8 txpwr_src, + const struct map_t *txpwr_map, + u16 pg_offset) +{ +#define PG_TXPWR_1PATH_BYTE_NUM_2G 18 - if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) - continue; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u16 offset = pg_offset; + u8 group, tx_idx; + u8 val; + u8 tmp_base; + s8 tmp_diff; + + if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G)) { + offset += PG_TXPWR_1PATH_BYTE_NUM_2G; + goto exit; + } - base = _PHY_GetTxPowerByRate(pAdapter, band, path, tx_num, rate_sec_base[rs]); - phy_SetTxPowerByRateBase(pAdapter, band, path, rs, tx_num, base); + if (DBG_PG_TXPWR_READ) + RTW_INFO("%s [%c] offset:0x%03x\n", __func__, rf_path_char(path), offset); + + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { + if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) { + tmp_base = map_read8(txpwr_map, offset); + if (!IS_PG_TXPWR_BASE_INVALID(tmp_base) + && IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexCCK_Base[path][group]) + ) { + pwr_info->IndexCCK_Base[path][group] = tmp_base; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G G%02d CCK-1T base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src)); } } + offset++; } -} - -#ifdef TX_POWER_BY_RATE_OLD -u8 -PHY_GetRateSectionIndexOfTxPowerByRate( - IN PADAPTER pAdapter, - IN u32 RegAddr, - IN u32 BitMask -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - u8 index = 0; - if (pDM_Odm->PhyRegPgVersion == 0) { - switch (RegAddr) { - case rTxAGC_A_Rate18_06: - index = 0; - break; - case rTxAGC_A_Rate54_24: - index = 1; - break; - case rTxAGC_A_CCK1_Mcs32: - index = 6; - break; - case rTxAGC_B_CCK11_A_CCK2_11: - if (BitMask == bMaskH3Bytes) - index = 7; - else if (BitMask == 0x000000ff) - index = 15; - break; + for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) { + if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) { + tmp_base = map_read8(txpwr_map, offset); + if (!IS_PG_TXPWR_BASE_INVALID(tmp_base) + && IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group]) + ) { + pwr_info->IndexBW40_Base[path][group] = tmp_base; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + } - case rTxAGC_A_Mcs03_Mcs00: - index = 2; - break; - case rTxAGC_A_Mcs07_Mcs04: - index = 3; - break; - case rTxAGC_A_Mcs11_Mcs08: - index = 4; - break; - case rTxAGC_A_Mcs15_Mcs12: - index = 5; - break; - case rTxAGC_B_Rate18_06: - index = 8; - break; - case rTxAGC_B_Rate54_24: - index = 9; - break; - case rTxAGC_B_CCK1_55_Mcs32: - index = 14; - break; - case rTxAGC_B_Mcs03_Mcs00: - index = 10; - break; - case rTxAGC_B_Mcs07_Mcs04: - index = 11; - break; - case rTxAGC_B_Mcs11_Mcs08: - index = 12; - break; - case rTxAGC_B_Mcs15_Mcs12: - index = 13; - break; - default: - RTW_INFO("Invalid RegAddr 0x3%x in PHY_GetRateSectionIndexOfTxPowerByRate()", RegAddr); - break; - }; + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (tx_idx == 0) { + if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx]) + ) { + pwr_info->BW20_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx]) + ) { + pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + } else { + if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]) + ) { + pwr_info->BW40_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + + } + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx]) + ) { + pwr_info->BW20_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + + if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx]) + ) { + pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx]) + ) { + pwr_info->CCK_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G CCK-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + } } - return index; + if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_2G) { + RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_2G); + rtw_warn_on(1); + } + +exit: + return offset; } -#endif /* TX_POWER_BY_RATE_OLD */ -VOID -PHY_GetRateValuesOfTxPowerByRate( - IN PADAPTER pAdapter, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Value, - OUT u8 *Rate, - OUT s8 *PwrByRateVal, - OUT u8 *RateNum -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - u8 index = 0, i = 0; +u16 hal_load_pg_txpwr_info_path_5g( + _adapter *adapter, + TxPowerInfo5G *pwr_info, + u32 path, + u8 txpwr_src, + const struct map_t *txpwr_map, + u16 pg_offset) +{ +#define PG_TXPWR_1PATH_BYTE_NUM_5G 24 - switch (RegAddr) { - case rTxAGC_A_Rate18_06: - case rTxAGC_B_Rate18_06: - Rate[0] = MGN_6M; - Rate[1] = MGN_9M; - Rate[2] = MGN_12M; - Rate[3] = MGN_18M; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u16 offset = pg_offset; + u8 group, tx_idx; + u8 val; + u8 tmp_base; + s8 tmp_diff; + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G)) +#endif + { + offset += PG_TXPWR_1PATH_BYTE_NUM_5G; + goto exit; + } + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (DBG_PG_TXPWR_READ) + RTW_INFO("%s[%c] eaddr:0x%03x\n", __func__, rf_path_char(path), offset); + + for (group = 0; group < MAX_CHNL_GROUP_5G; group++) { + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) { + tmp_base = map_read8(txpwr_map, offset); + if (!IS_PG_TXPWR_BASE_INVALID(tmp_base) + && IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group]) + ) { + pwr_info->IndexBW40_Base[path][group] = tmp_base; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src)); + } } - *RateNum = 4; - break; + offset++; + } - case rTxAGC_A_Rate54_24: - case rTxAGC_B_Rate54_24: - Rate[0] = MGN_24M; - Rate[1] = MGN_36M; - Rate[2] = MGN_48M; - Rate[3] = MGN_54M; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (tx_idx == 0) { + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx]) + ) { + pwr_info->BW20_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx]) + ) { + pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + } else { + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]) + ) { + pwr_info->BW40_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx]) + ) { + pwr_info->BW20_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; } - *RateNum = 4; - break; - - case rTxAGC_A_CCK1_Mcs32: - Rate[0] = MGN_1M; - PwrByRateVal[0] = (s8)((((Value >> (8 + 4)) & 0xF)) * 10 + - ((Value >> 8) & 0xF)); - *RateNum = 1; - break; - - case rTxAGC_B_CCK11_A_CCK2_11: - if (BitMask == 0xffffff00) { - Rate[0] = MGN_2M; - Rate[1] = MGN_5_5M; - Rate[2] = MGN_11M; - for (i = 1; i < 4; ++i) { - PwrByRateVal[i - 1] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); + } + + /* OFDM diff 2T ~ 3T */ + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, 1)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][1]) + ) { + pwr_info->OFDM_Diff[path][1] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 2, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + if (HAL_SPEC_CHK_TX_CNT(hal_spec, 2)) { + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][2]) + ) { + pwr_info->OFDM_Diff[path][2] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 3, tmp_diff, pg_txpwr_src_str(txpwr_src)); } - *RateNum = 3; - } else if (BitMask == 0x000000ff) { - Rate[0] = MGN_11M; - PwrByRateVal[0] = (s8)((((Value >> 4) & 0xF)) * 10 + - (Value & 0xF)); - *RateNum = 1; } - break; - - case rTxAGC_A_Mcs03_Mcs00: - case rTxAGC_B_Mcs03_Mcs00: - Rate[0] = MGN_MCS0; - Rate[1] = MGN_MCS1; - Rate[2] = MGN_MCS2; - Rate[3] = MGN_MCS3; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); + } + offset++; + + /* OFDM diff 4T */ + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, 3)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][3]) + ) { + pwr_info->OFDM_Diff[path][3] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 4, tmp_diff, pg_txpwr_src_str(txpwr_src)); } - *RateNum = 4; - break; - - case rTxAGC_A_Mcs07_Mcs04: - case rTxAGC_B_Mcs07_Mcs04: - Rate[0] = MGN_MCS4; - Rate[1] = MGN_MCS5; - Rate[2] = MGN_MCS6; - Rate[3] = MGN_MCS7; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); + } + offset++; + + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx]) + ) { + pwr_info->BW80_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G BW80-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx]) + ) { + pwr_info->BW160_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G BW160-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } } - *RateNum = 4; - break; + offset++; + } - case rTxAGC_A_Mcs11_Mcs08: - case rTxAGC_B_Mcs11_Mcs08: - Rate[0] = MGN_MCS8; - Rate[1] = MGN_MCS9; - Rate[2] = MGN_MCS10; - Rate[3] = MGN_MCS11; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 4; - break; + if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_5G) { + RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_5G); + rtw_warn_on(1); + } - case rTxAGC_A_Mcs15_Mcs12: - case rTxAGC_B_Mcs15_Mcs12: - Rate[0] = MGN_MCS12; - Rate[1] = MGN_MCS13; - Rate[2] = MGN_MCS14; - Rate[3] = MGN_MCS15; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 4; +#endif /* #ifdef CONFIG_IEEE80211_BAND_5GHZ */ - break; +exit: + return offset; +} - case rTxAGC_B_CCK1_55_Mcs32: - Rate[0] = MGN_1M; - Rate[1] = MGN_2M; - Rate[2] = MGN_5_5M; - for (i = 1; i < 4; ++i) { - PwrByRateVal[i - 1] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 3; +void hal_load_pg_txpwr_info( + _adapter *adapter, + TxPowerInfo24G *pwr_info_2g, + TxPowerInfo5G *pwr_info_5g, + u8 *pg_data, + BOOLEAN AutoLoadFail +) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 path; + u16 pg_offset; + u8 txpwr_src = PG_TXPWR_SRC_PG_DATA; + struct map_t pg_data_map = MAP_ENT(184, 1, 0xFF, MAPSEG_PTR_ENT(0x00, 184, pg_data)); + const struct map_t *txpwr_map = NULL; + + /* init with invalid value and some dummy base and diff */ + hal_init_pg_txpwr_info_2g(adapter, pwr_info_2g); + hal_init_pg_txpwr_info_5g(adapter, pwr_info_5g); + +select_src: + pg_offset = 0x10; + + switch (txpwr_src) { + case PG_TXPWR_SRC_PG_DATA: + txpwr_map = &pg_data_map; + break; + case PG_TXPWR_SRC_IC_DEF: + txpwr_map = hal_pg_txpwr_def_info(adapter); break; + case PG_TXPWR_SRC_DEF: + default: + txpwr_map = &pg_txpwr_def_info; + break; + }; - case 0xC20: - case 0xE20: - case 0x1820: - case 0x1a20: - Rate[0] = MGN_1M; - Rate[1] = MGN_2M; - Rate[2] = MGN_5_5M; - Rate[3] = MGN_11M; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); + if (txpwr_map == NULL) + goto end_parse; + + for (path = 0; path < MAX_RF_PATH ; path++) { + if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) + break; + pg_offset = hal_load_pg_txpwr_info_path_2g(adapter, pwr_info_2g, path, txpwr_src, txpwr_map, pg_offset); + pg_offset = hal_load_pg_txpwr_info_path_5g(adapter, pwr_info_5g, path, txpwr_src, txpwr_map, pg_offset); + } + + if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) == _SUCCESS + && hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) == _SUCCESS) + goto exit; + +end_parse: + txpwr_src++; + if (txpwr_src < PG_TXPWR_SRC_NUM) + goto select_src; + + if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) != _SUCCESS + || hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) != _SUCCESS) + rtw_warn_on(1); + +exit: + #if DBG_PG_TXPWR_READ + if (pwr_info_2g) + dump_pg_txpwr_info_2g(RTW_DBGDUMP, pwr_info_2g, 4, 4); + if (pwr_info_5g) + dump_pg_txpwr_info_5g(RTW_DBGDUMP, pwr_info_5g, 4, 4); + #endif + + return; +} + +void hal_load_txpwr_info( + _adapter *adapter, + TxPowerInfo24G *pwr_info_2g, + TxPowerInfo5G *pwr_info_5g, + u8 *pg_data +) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 max_tx_cnt = hal_spec->max_tx_cnt; + u8 rfpath, ch_idx, group, tx_idx; + + /* load from pg data (or default value) */ + hal_load_pg_txpwr_info(adapter, pwr_info_2g, pwr_info_5g, pg_data, _FALSE); + + /* transform to hal_data */ + for (rfpath = 0; rfpath < MAX_RF_PATH; rfpath++) { + + if (!pwr_info_2g || !HAL_SPEC_CHK_RF_PATH_2G(hal_spec, rfpath)) + goto bypass_2g; + + /* 2.4G base */ + for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) { + u8 cck_group; + + if (rtw_get_ch_group(ch_idx + 1, &group, &cck_group) != BAND_ON_2_4G) + continue; + + hal_data->Index24G_CCK_Base[rfpath][ch_idx] = pwr_info_2g->IndexCCK_Base[rfpath][cck_group]; + hal_data->Index24G_BW40_Base[rfpath][ch_idx] = pwr_info_2g->IndexBW40_Base[rfpath][group]; } - *RateNum = 4; - break; - case 0xC24: - case 0xE24: - case 0x1824: - case 0x1a24: - Rate[0] = MGN_6M; - Rate[1] = MGN_9M; - Rate[2] = MGN_12M; - Rate[3] = MGN_18M; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); + /* 2.4G diff */ + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (tx_idx >= max_tx_cnt) + break; + + hal_data->CCK_24G_Diff[rfpath][tx_idx] = pwr_info_2g->CCK_Diff[rfpath][tx_idx]; + hal_data->OFDM_24G_Diff[rfpath][tx_idx] = pwr_info_2g->OFDM_Diff[rfpath][tx_idx]; + hal_data->BW20_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW20_Diff[rfpath][tx_idx]; + hal_data->BW40_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW40_Diff[rfpath][tx_idx]; } - *RateNum = 4; - break; +bypass_2g: + ; - case 0xC28: - case 0xE28: - case 0x1828: - case 0x1a28: - Rate[0] = MGN_24M; - Rate[1] = MGN_36M; - Rate[2] = MGN_48M; - Rate[3] = MGN_54M; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (!pwr_info_5g || !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, rfpath)) + goto bypass_5g; + + /* 5G base */ + for (ch_idx = 0; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) { + if (rtw_get_ch_group(center_ch_5g_all[ch_idx], &group, NULL) != BAND_ON_5G) + continue; + hal_data->Index5G_BW40_Base[rfpath][ch_idx] = pwr_info_5g->IndexBW40_Base[rfpath][group]; } - *RateNum = 4; - break; - case 0xC2C: - case 0xE2C: - case 0x182C: - case 0x1a2C: - Rate[0] = MGN_MCS0; - Rate[1] = MGN_MCS1; - Rate[2] = MGN_MCS2; - Rate[3] = MGN_MCS3; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); + for (ch_idx = 0 ; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++) { + u8 upper, lower; + + if (rtw_get_ch_group(center_ch_5g_80m[ch_idx], &group, NULL) != BAND_ON_5G) + continue; + + upper = pwr_info_5g->IndexBW40_Base[rfpath][group]; + lower = pwr_info_5g->IndexBW40_Base[rfpath][group + 1]; + hal_data->Index5G_BW80_Base[rfpath][ch_idx] = (upper + lower) / 2; } - *RateNum = 4; - break; - case 0xC30: - case 0xE30: - case 0x1830: - case 0x1a30: - Rate[0] = MGN_MCS4; - Rate[1] = MGN_MCS5; - Rate[2] = MGN_MCS6; - Rate[3] = MGN_MCS7; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); + /* 5G diff */ + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (tx_idx >= max_tx_cnt) + break; + + hal_data->OFDM_5G_Diff[rfpath][tx_idx] = pwr_info_5g->OFDM_Diff[rfpath][tx_idx]; + hal_data->BW20_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW20_Diff[rfpath][tx_idx]; + hal_data->BW40_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW40_Diff[rfpath][tx_idx]; + hal_data->BW80_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW80_Diff[rfpath][tx_idx]; } - *RateNum = 4; - break; +bypass_5g: + ; +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ + } +} - case 0xC34: - case 0xE34: - case 0x1834: - case 0x1a34: - Rate[0] = MGN_MCS8; - Rate[1] = MGN_MCS9; - Rate[2] = MGN_MCS10; - Rate[3] = MGN_MCS11; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 4; - break; - - case 0xC38: - case 0xE38: - case 0x1838: - case 0x1a38: - Rate[0] = MGN_MCS12; - Rate[1] = MGN_MCS13; - Rate[2] = MGN_MCS14; - Rate[3] = MGN_MCS15; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 4; - break; - - case 0xC3C: - case 0xE3C: - case 0x183C: - case 0x1a3C: - Rate[0] = MGN_VHT1SS_MCS0; - Rate[1] = MGN_VHT1SS_MCS1; - Rate[2] = MGN_VHT1SS_MCS2; - Rate[3] = MGN_VHT1SS_MCS3; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 4; - break; - - case 0xC40: - case 0xE40: - case 0x1840: - case 0x1a40: - Rate[0] = MGN_VHT1SS_MCS4; - Rate[1] = MGN_VHT1SS_MCS5; - Rate[2] = MGN_VHT1SS_MCS6; - Rate[3] = MGN_VHT1SS_MCS7; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 4; - break; - - case 0xC44: - case 0xE44: - case 0x1844: - case 0x1a44: - Rate[0] = MGN_VHT1SS_MCS8; - Rate[1] = MGN_VHT1SS_MCS9; - Rate[2] = MGN_VHT2SS_MCS0; - Rate[3] = MGN_VHT2SS_MCS1; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 4; - break; - - case 0xC48: - case 0xE48: - case 0x1848: - case 0x1a48: - Rate[0] = MGN_VHT2SS_MCS2; - Rate[1] = MGN_VHT2SS_MCS3; - Rate[2] = MGN_VHT2SS_MCS4; - Rate[3] = MGN_VHT2SS_MCS5; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 4; - break; - - case 0xC4C: - case 0xE4C: - case 0x184C: - case 0x1a4C: - Rate[0] = MGN_VHT2SS_MCS6; - Rate[1] = MGN_VHT2SS_MCS7; - Rate[2] = MGN_VHT2SS_MCS8; - Rate[3] = MGN_VHT2SS_MCS9; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 4; - break; - - case 0xCD8: - case 0xED8: - case 0x18D8: - case 0x1aD8: - Rate[0] = MGN_MCS16; - Rate[1] = MGN_MCS17; - Rate[2] = MGN_MCS18; - Rate[3] = MGN_MCS19; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 4; - break; - - case 0xCDC: - case 0xEDC: - case 0x18DC: - case 0x1aDC: - Rate[0] = MGN_MCS20; - Rate[1] = MGN_MCS21; - Rate[2] = MGN_MCS22; - Rate[3] = MGN_MCS23; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 4; - break; - - case 0xCE0: - case 0xEE0: - case 0x18E0: - case 0x1aE0: - Rate[0] = MGN_VHT3SS_MCS0; - Rate[1] = MGN_VHT3SS_MCS1; - Rate[2] = MGN_VHT3SS_MCS2; - Rate[3] = MGN_VHT3SS_MCS3; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } - *RateNum = 4; - break; +void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + int path, ch_idx, tx_idx; + + RTW_PRINT_SEL(sel, "2.4G\n"); + RTW_PRINT_SEL(sel, "CCK-1T base:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) + _RTW_PRINT_SEL(sel, "%2d ", center_ch_2g[ch_idx]); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) + _RTW_PRINT_SEL(sel, "%2u ", hal_data->Index24G_CCK_Base[path][ch_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "CCK diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", hal_data->CCK_24G_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW40-1S base:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) + _RTW_PRINT_SEL(sel, "%2d ", center_ch_2g[ch_idx]); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) + _RTW_PRINT_SEL(sel, "%2u ", hal_data->Index24G_BW40_Base[path][ch_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "OFDM diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_24G_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW20 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_24G_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW40 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_24G_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); +} - case 0xCE4: - case 0xEE4: - case 0x18E4: - case 0x1aE4: - Rate[0] = MGN_VHT3SS_MCS4; - Rate[1] = MGN_VHT3SS_MCS5; - Rate[2] = MGN_VHT3SS_MCS6; - Rate[3] = MGN_VHT3SS_MCS7; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); +void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt) +{ +#ifdef CONFIG_IEEE80211_BAND_5GHZ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + int path, ch_idx, tx_idx; + u8 dump_section = 0; + u8 ch_idx_s = 0; + + RTW_PRINT_SEL(sel, "5G\n"); + RTW_PRINT_SEL(sel, "BW40-1S base:\n"); + do { + #define DUMP_5G_BW40_BASE_SECTION_NUM 3 + u8 end[DUMP_5G_BW40_BASE_SECTION_NUM] = {64, 144, 177}; + + RTW_PRINT_SEL(sel, "%4s ", ""); + for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) { + _RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_all[ch_idx]); + if (end[dump_section] == center_ch_5g_all[ch_idx]) + break; } - *RateNum = 4; - break; - - case 0xCE8: - case 0xEE8: - case 0x18E8: - case 0x1aE8: - Rate[0] = MGN_VHT3SS_MCS8; - Rate[1] = MGN_VHT3SS_MCS9; - for (i = 0; i < 2; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) { + _RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW40_Base[path][ch_idx]); + if (end[dump_section] == center_ch_5g_all[ch_idx]) + break; + } + _RTW_PRINT_SEL(sel, "\n"); } - *RateNum = 2; - break; + RTW_PRINT_SEL(sel, "\n"); - default: - RTW_PRINT("Invalid RegAddr 0x%x in %s()\n", RegAddr, __func__); - break; - }; + ch_idx_s = ch_idx + 1; + dump_section++; + if (dump_section >= DUMP_5G_BW40_BASE_SECTION_NUM) + break; + } while (1); + + RTW_PRINT_SEL(sel, "BW80-1S base:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++) + _RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_80m[ch_idx]); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++) + _RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW80_Base[path][ch_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "OFDM diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_5G_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW20 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_5G_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW40 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_5G_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW80 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW80_5G_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ } -void -PHY_StoreTxPowerByRateNew( - IN PADAPTER pAdapter, - IN u32 Band, - IN u32 RfPath, - IN u32 TxNum, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u8 i = 0, rates[4] = {0}, rateNum = 0; - s8 PwrByRateVal[4] = {0}; - - PHY_GetRateValuesOfTxPowerByRate(pAdapter, RegAddr, BitMask, Data, rates, PwrByRateVal, &rateNum); +/* +* rtw_regsty_get_target_tx_power - +* +* Return dBm or -1 for undefined +*/ +s8 rtw_regsty_get_target_tx_power( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN RATE_SECTION RateSection +) +{ + struct registry_priv *regsty = adapter_to_regsty(Adapter); + s8 value = 0; - if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { - RTW_PRINT("Invalid Band %d\n", Band); - return; + if (RfPath > RF_PATH_D) { + RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath); + return -1; } - if (RfPath > ODM_RF_PATH_D) { - RTW_PRINT("Invalid RfPath %d\n", RfPath); - return; + if (Band != BAND_ON_2_4G + #ifdef CONFIG_IEEE80211_BAND_5GHZ + && Band != BAND_ON_5G + #endif + ) { + RTW_PRINT("%s invalid Band:%d\n", __func__, Band); + return -1; } - if (TxNum > ODM_RF_PATH_D) { - RTW_PRINT("Invalid TxNum %d\n", TxNum); - return; + if (RateSection >= RATE_SECTION_NUM + #ifdef CONFIG_IEEE80211_BAND_5GHZ + || (Band == BAND_ON_5G && RateSection == CCK) + #endif + ) { + RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__ + , RateSection, Band, RfPath); + return -1; } - for (i = 0; i < rateNum; ++i) { - u8 rate_idx = PHY_GetRateIndexOfTxPowerByRate(rates[i]); + if (Band == BAND_ON_2_4G) + value = regsty->target_tx_pwr_2g[RfPath][RateSection]; +#ifdef CONFIG_IEEE80211_BAND_5GHZ + else /* BAND_ON_5G */ + value = regsty->target_tx_pwr_5g[RfPath][RateSection - 1]; +#endif - if (IS_1T_RATE(rates[i])) - pHalData->TxPwrByRateOffset[Band][RfPath][RF_1TX][rate_idx] = PwrByRateVal[i]; - else if (IS_2T_RATE(rates[i])) - pHalData->TxPwrByRateOffset[Band][RfPath][RF_2TX][rate_idx] = PwrByRateVal[i]; - else if (IS_3T_RATE(rates[i])) - pHalData->TxPwrByRateOffset[Band][RfPath][RF_3TX][rate_idx] = PwrByRateVal[i]; - else if (IS_4T_RATE(rates[i])) - pHalData->TxPwrByRateOffset[Band][RfPath][RF_4TX][rate_idx] = PwrByRateVal[i]; - else - rtw_warn_on(1); - } + return value; } -#ifdef TX_POWER_BY_RATE_OLD -void -PHY_StoreTxPowerByRateOld( - IN PADAPTER pAdapter, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u8 index = PHY_GetRateSectionIndexOfTxPowerByRate(pAdapter, RegAddr, BitMask); +bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + int path, tx_num, band, rs; + s8 target; - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][index] = Data; - /* RTW_INFO("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", pHalData->pwrGroupCnt, */ - /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]); */ -} -#endif /* TX_POWER_BY_RATE_OLD */ + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; -VOID -PHY_InitTxPowerByRate( - IN PADAPTER pAdapter -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u8 band = 0, rfPath = 0, TxNum = 0, rate = 0, i = 0, j = 0; + for (path = 0; path < RF_PATH_MAX; path++) { + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path)) + break; - if (IS_HARDWARE_TYPE_8188E(pAdapter)) { - for (i = 0; i < MAX_PG_GROUP; ++i) - for (j = 0; j < 16; ++j) - pHalData->MCSTxPowerLevelOriginalOffset[i][j] = 0; - } else { - for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) - for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath) - for (TxNum = 0; TxNum < TX_PWR_BY_RATE_NUM_RF; ++TxNum) - for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate) - pHalData->TxPwrByRateOffset[band][rfPath][TxNum][rate] = 0; - } -} + for (rs = 0; rs < RATE_SECTION_NUM; rs++) { + tx_num = rate_section_to_tx_num(rs); + if (tx_num >= hal_spec->tx_nss_num) + continue; -VOID -PHY_StoreTxPowerByRate( - IN PADAPTER pAdapter, - IN u32 Band, - IN u32 RfPath, - IN u32 TxNum, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) + continue; - if (pDM_Odm->PhyRegPgVersion > 0) - PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, TxNum, RegAddr, BitMask, Data); -#ifdef TX_POWER_BY_RATE_OLD - else if (pDM_Odm->PhyRegPgVersion == 0) { - PHY_StoreTxPowerByRateOld(pAdapter, RegAddr, BitMask, Data); + if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + continue; - if (RegAddr == rTxAGC_A_Mcs15_Mcs12 && pHalData->rf_type == RF_1T1R) - pHalData->pwrGroupCnt++; - else if (RegAddr == rTxAGC_B_Mcs15_Mcs12 && pHalData->rf_type != RF_1T1R) - pHalData->pwrGroupCnt++; + target = rtw_regsty_get_target_tx_power(adapter, band, path, rs); + if (target == -1) { + RTW_PRINT("%s return _FALSE for band:%d, path:%d, rs:%d, t:%d\n", __func__, band, path, rs, target); + return _FALSE; + } + } + } } -#endif - else - RTW_INFO("Invalid PHY_REG_PG.txt version %d\n", pDM_Odm->PhyRegPgVersion); + return _TRUE; } -#ifdef TX_POWER_BY_RATE_OLD -VOID -phy_ConvertTxPowerByRateByBase( - IN u32 *pData, - IN u8 Start, - IN u8 End, - IN u8 BaseValue -) { - s8 i = 0; - u8 TempValue = 0; - u32 TempData = 0; - - for (i = 3; i >= 0; --i) { - if (i >= Start && i <= End) { - /* Get the exact value */ - TempValue = (u8)(*pData >> (i * 8)) & 0xF; - TempValue += ((u8)((*pData >> (i * 8 + 4)) & 0xF)) * 10; - - /* Change the value to a relative value */ - TempValue = (TempValue > BaseValue) ? TempValue - BaseValue : BaseValue - TempValue; - } else - TempValue = (u8)(*pData >> (i * 8)) & 0xFF; +/* +* PHY_GetTxPowerByRateBase - +* +* Return 2 times of dBm +*/ +u8 +PHY_GetTxPowerByRateBase( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN RATE_SECTION RateSection +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 value = 0; - TempData <<= 8; - TempData |= TempValue; + if (RfPath > RF_PATH_D) { + RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath); + return 0; } - *pData = TempData; -} + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + RTW_PRINT("%s invalid Band:%d\n", __func__, Band); + return 0; + } + if (RateSection >= RATE_SECTION_NUM + || (Band == BAND_ON_5G && RateSection == CCK) + ) { + RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__ + , RateSection, Band, RfPath); + return 0; + } -VOID -PHY_ConvertTxPowerByRateInDbmToRelativeValuesOld( - IN PADAPTER pAdapter -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u8 base = 0; - - /* RTW_INFO("===>PHY_ConvertTxPowerByRateInDbmToRelativeValuesOld()\n" ); */ - - /* CCK */ - base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, CCK); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][6]), 1, 1, base); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][7]), 1, 3, base); - - /* OFDM */ - base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, OFDM); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][0]), 0, 3, base); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][1]), 0, 3, base); - - /* HT MCS0~7 */ - base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, HT_MCS0_MCS7); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][2]), 0, 3, base); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][3]), 0, 3, base); - - /* HT MCS8~15 */ - base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_2TX, HT_MCS8_MCS15); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][4]), 0, 3, base); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][5]), 0, 3, base); - - /* CCK */ - base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, RF_1TX, CCK); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][14]), 1, 3, base); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][15]), 0, 0, base); - - /* OFDM */ - base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, RF_1TX, OFDM); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][8]), 0, 3, base); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][9]), 0, 3, base); - - /* HT MCS0~7 */ - base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, RF_1TX, HT_MCS0_MCS7); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][10]), 0, 3, base); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][11]), 0, 3, base); - - /* HT MCS8~15 */ - base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, RF_2TX, HT_MCS8_MCS15); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][12]), 0, 3, base); - phy_ConvertTxPowerByRateByBase( - &(pHalData->MCSTxPowerLevelOriginalOffset[0][13]), 0, 3, base); - - /* RTW_INFO("<===PHY_ConvertTxPowerByRateInDbmToRelativeValuesOld()\n" ); */ + if (Band == BAND_ON_2_4G) + value = pHalData->TxPwrByRateBase2_4G[RfPath][RateSection]; + else /* BAND_ON_5G */ + value = pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1]; + + return value; } -#endif /* TX_POWER_BY_RATE_OLD */ VOID -phy_ConvertTxPowerByRateInDbmToRelativeValues( - IN PADAPTER pAdapter -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u8 base = 0, i = 0, value = 0, - band = 0, path = 0, txNum = 0, index = 0, - startIndex = 0, endIndex = 0; - u8 cckRates[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}, - ofdmRates[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}, - mcs0_7Rates[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}, - mcs8_15Rates[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}, - mcs16_23Rates[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}, - vht1ssRates[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4, - MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9 - }, - vht2ssRates[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, - MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9 - }, - vht3ssRates[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4, - MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9 - }; - - /* RTW_INFO("===>PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */ - - for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) { - for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) { - for (txNum = RF_1TX; txNum < RF_MAX_TX_NUM; ++txNum) { - /* CCK */ - base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_11M); - for (i = 0; i < sizeof(cckRates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, cckRates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, cckRates[i], value - base); - } - - /* OFDM */ - base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_54M); - for (i = 0; i < sizeof(ofdmRates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, ofdmRates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, ofdmRates[i], value - base); - } +phy_SetTxPowerByRateBase( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN RATE_SECTION RateSection, + IN u8 Value +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - /* HT MCS0~7 */ - base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_MCS7); - for (i = 0; i < sizeof(mcs0_7Rates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, mcs0_7Rates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, mcs0_7Rates[i], value - base); - } + if (RfPath > RF_PATH_D) { + RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath); + return; + } - /* HT MCS8~15 */ - base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_MCS15); - for (i = 0; i < sizeof(mcs8_15Rates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, mcs8_15Rates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, mcs8_15Rates[i], value - base); - } + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + RTW_PRINT("%s invalid Band:%d\n", __func__, Band); + return; + } - /* HT MCS16~23 */ - base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_MCS23); - for (i = 0; i < sizeof(mcs16_23Rates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, mcs16_23Rates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, mcs16_23Rates[i], value - base); - } + if (RateSection >= RATE_SECTION_NUM + || (Band == BAND_ON_5G && RateSection == CCK) + ) { + RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d\n", __func__ + , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath); + return; + } - /* VHT 1SS */ - base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_VHT1SS_MCS7); - for (i = 0; i < sizeof(vht1ssRates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, vht1ssRates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, vht1ssRates[i], value - base); - } + if (Band == BAND_ON_2_4G) + pHalData->TxPwrByRateBase2_4G[RfPath][RateSection] = Value; + else /* BAND_ON_5G */ + pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1] = Value; +} - /* VHT 2SS */ - base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_VHT2SS_MCS7); - for (i = 0; i < sizeof(vht2ssRates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, vht2ssRates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, vht2ssRates[i], value - base); - } +static inline BOOLEAN phy_is_txpwr_by_rate_undefined_of_band_path(_adapter *adapter, u8 band, u8 path) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 rate_idx = 0; - /* VHT 3SS */ - base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_VHT3SS_MCS7); - for (i = 0; i < sizeof(vht3ssRates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, vht3ssRates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, vht3ssRates[i], value - base); - } - } - } + for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) { + if (hal_data->TxPwrByRateOffset[band][path][rate_idx] != 0) + goto exit; } - /* RTW_INFO("<===PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */ +exit: + return rate_idx >= TX_PWR_BY_RATE_NUM_RATE ? _TRUE : _FALSE; } -/* - * This function must be called if the value in the PHY_REG_PG.txt(or header) - * is exact dBm values - */ -VOID -PHY_TxPowerByRateConfiguration( - IN PADAPTER pAdapter -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +static inline void phy_txpwr_by_rate_duplicate_band_path(_adapter *adapter, u8 band, u8 s_path, u8 t_path) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 rate_idx = 0; - phy_StoreTxPowerByRateBase(pAdapter); - phy_ConvertTxPowerByRateInDbmToRelativeValues(pAdapter); + for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) + hal_data->TxPwrByRateOffset[band][t_path][rate_idx] = hal_data->TxPwrByRateOffset[band][s_path][rate_idx]; } -VOID -PHY_SetTxPowerIndexByRateSection( - IN PADAPTER pAdapter, - IN u8 RFPath, - IN u8 Channel, - IN u8 RateSection -) { - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); +static void phy_txpwr_by_rate_chk_for_path_dup(_adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 band, path; + s8 src_path; - if (RateSection == CCK) { - u8 cckRates[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}; - if (pHalData->CurrentBandType == BAND_ON_2_4G) - PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, - cckRates, sizeof(cckRates) / sizeof(u8)); - - } else if (RateSection == OFDM) { - u8 ofdmRates[] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}; - PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, - ofdmRates, sizeof(ofdmRates) / sizeof(u8)); - - } else if (RateSection == HT_MCS0_MCS7) { - u8 htRates1T[] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}; - PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, - htRates1T, sizeof(htRates1T) / sizeof(u8)); - - } else if (RateSection == HT_MCS8_MCS15) { - u8 htRates2T[] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}; - PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, - htRates2T, sizeof(htRates2T) / sizeof(u8)); - - } else if (RateSection == HT_MCS16_MCS23) { - u1Byte htRates3T[] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}; - PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, - htRates3T, sizeof(htRates3T) / sizeof(u1Byte)); - - } else if (RateSection == HT_MCS24_MCS31) { - u1Byte htRates4T[] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31}; - PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, - htRates4T, sizeof(htRates4T) / sizeof(u1Byte)); - - } else if (RateSection == VHT_1SSMCS0_1SSMCS9) { - u8 vhtRates1T[] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4, - MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9 - }; - PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, - vhtRates1T, sizeof(vhtRates1T) / sizeof(u8)); - - } else if (RateSection == VHT_2SSMCS0_2SSMCS9) { - u8 vhtRates2T[] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, - MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9 - }; - - PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, - vhtRates2T, sizeof(vhtRates2T) / sizeof(u8)); - } else if (RateSection == VHT_3SSMCS0_3SSMCS9) { - u1Byte vhtRates3T[] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4, - MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9 - }; - - PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, - vhtRates3T, sizeof(vhtRates3T) / sizeof(u1Byte)); - } else if (RateSection == VHT_4SSMCS0_4SSMCS9) { - u1Byte vhtRates4T[] = {MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4, - MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9 - }; - - PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, - vhtRates4T, sizeof(vhtRates4T) / sizeof(u1Byte)); - } else - RTW_INFO("Invalid RateSection %d in %s", RateSection, __FUNCTION__); -} + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) + hal_data->txpwr_by_rate_undefined_band_path[band][path] = 0; -BOOLEAN -phy_GetChnlIndex( - IN u8 Channel, - OUT u8 *ChannelIdx -) { - u8 i = 0; - BOOLEAN bIn24G = _TRUE; + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; - if (Channel <= 14) { - bIn24G = _TRUE; - *ChannelIdx = Channel - 1; - } else { - bIn24G = _FALSE; + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path)) + continue; - for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) { - if (center_ch_5g_all[i] == Channel) { - *ChannelIdx = i; - return bIn24G; - } + if (phy_is_txpwr_by_rate_undefined_of_band_path(adapter, band, path)) + hal_data->txpwr_by_rate_undefined_band_path[band][path] = 1; } } - return bIn24G; -} - -u8 -PHY_GetTxPowerIndexBase( - IN PADAPTER pAdapter, - IN u8 RFPath, - IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, - IN u8 Channel, - OUT PBOOLEAN bIn24G -) { - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - u8 i = 0; /* default set to 1S */ - u8 txPower = 0; - u8 chnlIdx = (Channel - 1); - - if (HAL_IsLegalChannel(pAdapter, Channel) == _FALSE) { - chnlIdx = 0; - RTW_INFO("Illegal channel!!\n"); - } - - *bIn24G = phy_GetChnlIndex(Channel, &chnlIdx); - - /* RTW_INFO("[%s] Channel Index: %d\n", (*bIn24G?"2.4G":"5G"), chnlIdx); */ - - if (*bIn24G) { /* 3 ============================== 2.4 G ============================== */ - if (IS_CCK_RATE(Rate)) - txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx]; - else if (MGN_6M <= Rate) - txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx]; - else - RTW_INFO("PHY_GetTxPowerIndexBase: INVALID Rate.\n"); + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; - /* RTW_INFO("Base Tx power(RF-%c, Rate #%d, Channel Index %d) = 0x%X\n", */ - /* ((RFPath==0)?'A':'B'), Rate, chnlIdx, txPower); */ + src_path = -1; + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path)) + continue; - /* OFDM-1T */ - if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) { - txPower += pHalData->OFDM_24G_Diff[RFPath][TX_1S]; - /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (OFDM-1T) = (%d)\n", ((RFPath==0)?'A':'B'), pHalData->OFDM_24G_Diff[RFPath][TX_1S]); */ + /* find src */ + if (src_path == -1 && hal_data->txpwr_by_rate_undefined_band_path[band][path] == 0) + src_path = path; } - /* BW20-1S, BW20-2S */ - if (BandWidth == CHANNEL_WIDTH_20) { - if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_24G_Diff[RFPath][TX_1S]; - if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_24G_Diff[RFPath][TX_2S]; - if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_24G_Diff[RFPath][TX_3S]; - if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_24G_Diff[RFPath][TX_4S]; - /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (BW20-1S, BW20-2S, BW20-3S, BW20-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ - /* pHalData->BW20_24G_Diff[RFPath][TX_1S], pHalData->BW20_24G_Diff[RFPath][TX_2S], */ - /* pHalData->BW20_24G_Diff[RFPath][TX_3S], pHalData->BW20_24G_Diff[RFPath][TX_4S]); */ + if (src_path == -1) { + RTW_ERR("%s all power by rate undefined\n", __func__); + continue; } - /* BW40-1S, BW40-2S */ - else if (BandWidth == CHANNEL_WIDTH_40) { - if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S]; - if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S]; - if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S]; - if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S]; - /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (BW40-1S, BW40-2S, BW40-3S, BW40-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ - /* pHalData->BW40_24G_Diff[RFPath][TX_1S], pHalData->BW40_24G_Diff[RFPath][TX_2S], */ - /* pHalData->BW40_24G_Diff[RFPath][TX_3S], pHalData->BW40_24G_Diff[RFPath][TX_4S]); */ - } - /* Willis suggest adopt BW 40M power index while in BW 80 mode */ - else if (BandWidth == CHANNEL_WIDTH_80) { - if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S]; - if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S]; - if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S]; - if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S]; + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path)) + continue; - /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (BW40-1S, BW40-2S, BW40-3S, BW40-4T) = (%d, %d, %d, %d) P.S. Current is in BW 80MHz\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ - /* pHalData->BW40_24G_Diff[RFPath][TX_1S], pHalData->BW40_24G_Diff[RFPath][TX_2S], */ - /* pHalData->BW40_24G_Diff[RFPath][TX_3S], pHalData->BW40_24G_Diff[RFPath][TX_4S]); */ + /* duplicate src to undefined one */ + if (hal_data->txpwr_by_rate_undefined_band_path[band][path] == 1) { + RTW_INFO("%s duplicate %s [%c] to [%c]\n", __func__ + , band_str(band), rf_path_char(src_path), rf_path_char(path)); + phy_txpwr_by_rate_duplicate_band_path(adapter, band, src_path, path); + } } - } else { /* 3 ============================== 5 G ============================== */ - if (MGN_6M <= Rate) - txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx]; - else - RTW_INFO("===> mpt_ProQueryCalTxPower_Jaguar: INVALID Rate.\n"); + } +} - /* RTW_INFO("Base Tx power(RF-%c, Rate #%d, Channel Index %d) = 0x%X\n", */ - /* ((RFPath==0)?'A':'B'), Rate, chnlIdx, txPower); */ +VOID +phy_StoreTxPowerByRateBase( + IN PADAPTER pAdapter +) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter); + struct registry_priv *regsty = adapter_to_regsty(pAdapter); - /* OFDM-1T */ - if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) { - txPower += pHalData->OFDM_5G_Diff[RFPath][TX_1S]; - /* RTW_INFO("+PowerDiff 5G (RF-%c): (OFDM-1T) = (%d)\n", ((RFPath==0)?'A':'B'), pHalData->OFDM_5G_Diff[RFPath][TX_1S]); */ - } + u8 rate_sec_base[RATE_SECTION_NUM] = { + MGN_11M, + MGN_54M, + MGN_MCS7, + MGN_MCS15, + MGN_MCS23, + MGN_MCS31, + MGN_VHT1SS_MCS7, + MGN_VHT2SS_MCS7, + MGN_VHT3SS_MCS7, + MGN_VHT4SS_MCS7, + }; - /* BW20-1S, BW20-2S */ - if (BandWidth == CHANNEL_WIDTH_20) { - if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_5G_Diff[RFPath][TX_1S]; - if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_5G_Diff[RFPath][TX_2S]; - if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_5G_Diff[RFPath][TX_3S]; - if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_5G_Diff[RFPath][TX_4S]; + u8 band, path, rs, tx_num, base, index; - /* RTW_INFO("+PowerDiff 5G (RF-%c): (BW20-1S, BW20-2S, BW20-3S, BW20-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ - /* pHalData->BW20_5G_Diff[RFPath][TX_1S], pHalData->BW20_5G_Diff[RFPath][TX_2S], */ - /* pHalData->BW20_5G_Diff[RFPath][TX_3S], pHalData->BW20_5G_Diff[RFPath][TX_4S]); */ - } - /* BW40-1S, BW40-2S */ - else if (BandWidth == CHANNEL_WIDTH_40) { - if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_5G_Diff[RFPath][TX_1S]; - if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_5G_Diff[RFPath][TX_2S]; - if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_5G_Diff[RFPath][TX_3S]; - if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_5G_Diff[RFPath][TX_4S]; + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(pAdapter, band)) + continue; - /* RTW_INFO("+PowerDiff 5G(RF-%c): (BW40-1S, BW40-2S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ - /* pHalData->BW40_5G_Diff[RFPath][TX_1S], pHalData->BW40_5G_Diff[RFPath][TX_2S], */ - /* pHalData->BW40_5G_Diff[RFPath][TX_3S], pHalData->BW40_5G_Diff[RFPath][TX_4S]); */ - } - /* BW80-1S, BW80-2S */ - else if (BandWidth == CHANNEL_WIDTH_80) { - /* <20121220, Kordan> Get the index of array "Index5G_BW80_Base". */ - for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) - if (center_ch_5g_80m[i] == Channel) - chnlIdx = i; + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path)) + break; - txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx]; + for (rs = 0; rs < RATE_SECTION_NUM; rs++) { + tx_num = rate_section_to_tx_num(rs); + if (tx_num >= hal_spec->tx_nss_num) + continue; - if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += + pHalData->BW80_5G_Diff[RFPath][TX_1S]; - if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW80_5G_Diff[RFPath][TX_2S]; - if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW80_5G_Diff[RFPath][TX_3S]; - if ((MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW80_5G_Diff[RFPath][TX_4S]; + if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) + continue; - /* RTW_INFO("+PowerDiff 5G(RF-%c): (BW80-1S, BW80-2S, BW80-3S, BW80-4S) = (%d, %d, %d, %d)\n",((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ - /* pHalData->BW80_5G_Diff[RFPath][TX_1S], pHalData->BW80_5G_Diff[RFPath][TX_2S], */ - /* pHalData->BW80_5G_Diff[RFPath][TX_3S], pHalData->BW80_5G_Diff[RFPath][TX_4S]); */ + if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) + continue; + + if (regsty->target_tx_pwr_valid == _TRUE) + base = 2 * rtw_regsty_get_target_tx_power(pAdapter, band, path, rs); + else + base = _PHY_GetTxPowerByRate(pAdapter, band, path, rate_sec_base[rs]); + phy_SetTxPowerByRateBase(pAdapter, band, path, rs, base); + } } } - - return txPower; } -s8 -PHY_GetTxPowerTrackingOffset( - PADAPTER pAdapter, - u8 RFPath, - u8 Rate -) { - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - s8 offset = 0; - - if (pDM_Odm->RFCalibrateInfo.TxPowerTrackControl == _FALSE) - return offset; - - if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M)) { - offset = pDM_Odm->RFCalibrateInfo.Remnant_CCKSwingIdx; - /*RTW_INFO("+Remnant_CCKSwingIdx = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_CCKSwingIdx);*/ - } else { - offset = pDM_Odm->RFCalibrateInfo.Remnant_OFDMSwingIdx[RFPath]; - /*RTW_INFO("+Remanant_OFDMSwingIdx[RFPath %u][Rate 0x%x] = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]); */ - - } +VOID +PHY_GetRateValuesOfTxPowerByRate( + IN PADAPTER pAdapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Value, + OUT u8 *Rate, + OUT s8 *PwrByRateVal, + OUT u8 *RateNum +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + u8 index = 0, i = 0; - return offset; -} + switch (RegAddr) { + case rTxAGC_A_Rate18_06: + case rTxAGC_B_Rate18_06: + Rate[0] = MGN_6M; + Rate[1] = MGN_9M; + Rate[2] = MGN_12M; + Rate[3] = MGN_18M; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; -u8 -PHY_GetRateIndexOfTxPowerByRate( - IN u8 Rate -) { - u8 index = 0; - switch (Rate) { - case MGN_1M: - index = 0; + case rTxAGC_A_Rate54_24: + case rTxAGC_B_Rate54_24: + Rate[0] = MGN_24M; + Rate[1] = MGN_36M; + Rate[2] = MGN_48M; + Rate[3] = MGN_54M; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_2M: - index = 1; + + case rTxAGC_A_CCK1_Mcs32: + Rate[0] = MGN_1M; + PwrByRateVal[0] = (s8)((((Value >> (8 + 4)) & 0xF)) * 10 + + ((Value >> 8) & 0xF)); + *RateNum = 1; break; - case MGN_5_5M: - index = 2; - break; - case MGN_11M: - index = 3; - break; - case MGN_6M: - index = 4; - break; - case MGN_9M: - index = 5; - break; - case MGN_12M: - index = 6; - break; - case MGN_18M: - index = 7; - break; - case MGN_24M: - index = 8; - break; - case MGN_36M: - index = 9; - break; - case MGN_48M: - index = 10; - break; - case MGN_54M: - index = 11; - break; - case MGN_MCS0: - index = 12; - break; - case MGN_MCS1: - index = 13; - break; - case MGN_MCS2: - index = 14; - break; - case MGN_MCS3: - index = 15; - break; - case MGN_MCS4: - index = 16; - break; - case MGN_MCS5: - index = 17; - break; - case MGN_MCS6: - index = 18; - break; - case MGN_MCS7: - index = 19; - break; - case MGN_MCS8: - index = 20; - break; - case MGN_MCS9: - index = 21; - break; - case MGN_MCS10: - index = 22; - break; - case MGN_MCS11: - index = 23; - break; - case MGN_MCS12: - index = 24; - break; - case MGN_MCS13: - index = 25; - break; - case MGN_MCS14: - index = 26; - break; - case MGN_MCS15: - index = 27; - break; - case MGN_MCS16: - index = 28; - break; - case MGN_MCS17: - index = 29; - break; - case MGN_MCS18: - index = 30; - break; - case MGN_MCS19: - index = 31; - break; - case MGN_MCS20: - index = 32; - break; - case MGN_MCS21: - index = 33; - break; - case MGN_MCS22: - index = 34; - break; - case MGN_MCS23: - index = 35; - break; - case MGN_MCS24: - index = 36; - break; - case MGN_MCS25: - index = 37; - break; - case MGN_MCS26: - index = 38; - break; - case MGN_MCS27: - index = 39; - break; - case MGN_MCS28: - index = 40; - break; - case MGN_MCS29: - index = 41; - break; - case MGN_MCS30: - index = 42; - break; - case MGN_MCS31: - index = 43; - break; - case MGN_VHT1SS_MCS0: - index = 44; - break; - case MGN_VHT1SS_MCS1: - index = 45; - break; - case MGN_VHT1SS_MCS2: - index = 46; - break; - case MGN_VHT1SS_MCS3: - index = 47; - break; - case MGN_VHT1SS_MCS4: - index = 48; - break; - case MGN_VHT1SS_MCS5: - index = 49; - break; - case MGN_VHT1SS_MCS6: - index = 50; - break; - case MGN_VHT1SS_MCS7: - index = 51; - break; - case MGN_VHT1SS_MCS8: - index = 52; - break; - case MGN_VHT1SS_MCS9: - index = 53; - break; - case MGN_VHT2SS_MCS0: - index = 54; - break; - case MGN_VHT2SS_MCS1: - index = 55; - break; - case MGN_VHT2SS_MCS2: - index = 56; - break; - case MGN_VHT2SS_MCS3: - index = 57; - break; - case MGN_VHT2SS_MCS4: - index = 58; - break; - case MGN_VHT2SS_MCS5: - index = 59; - break; - case MGN_VHT2SS_MCS6: - index = 60; - break; - case MGN_VHT2SS_MCS7: - index = 61; + + case rTxAGC_B_CCK11_A_CCK2_11: + if (BitMask == 0xffffff00) { + Rate[0] = MGN_2M; + Rate[1] = MGN_5_5M; + Rate[2] = MGN_11M; + for (i = 1; i < 4; ++i) { + PwrByRateVal[i - 1] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 3; + } else if (BitMask == 0x000000ff) { + Rate[0] = MGN_11M; + PwrByRateVal[0] = (s8)((((Value >> 4) & 0xF)) * 10 + + (Value & 0xF)); + *RateNum = 1; + } break; - case MGN_VHT2SS_MCS8: - index = 62; + + case rTxAGC_A_Mcs03_Mcs00: + case rTxAGC_B_Mcs03_Mcs00: + Rate[0] = MGN_MCS0; + Rate[1] = MGN_MCS1; + Rate[2] = MGN_MCS2; + Rate[3] = MGN_MCS3; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT2SS_MCS9: - index = 63; + + case rTxAGC_A_Mcs07_Mcs04: + case rTxAGC_B_Mcs07_Mcs04: + Rate[0] = MGN_MCS4; + Rate[1] = MGN_MCS5; + Rate[2] = MGN_MCS6; + Rate[3] = MGN_MCS7; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT3SS_MCS0: - index = 64; + + case rTxAGC_A_Mcs11_Mcs08: + case rTxAGC_B_Mcs11_Mcs08: + Rate[0] = MGN_MCS8; + Rate[1] = MGN_MCS9; + Rate[2] = MGN_MCS10; + Rate[3] = MGN_MCS11; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT3SS_MCS1: - index = 65; + + case rTxAGC_A_Mcs15_Mcs12: + case rTxAGC_B_Mcs15_Mcs12: + Rate[0] = MGN_MCS12; + Rate[1] = MGN_MCS13; + Rate[2] = MGN_MCS14; + Rate[3] = MGN_MCS15; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; - case MGN_VHT3SS_MCS2: - index = 66; + + case rTxAGC_B_CCK1_55_Mcs32: + Rate[0] = MGN_1M; + Rate[1] = MGN_2M; + Rate[2] = MGN_5_5M; + for (i = 1; i < 4; ++i) { + PwrByRateVal[i - 1] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 3; break; - case MGN_VHT3SS_MCS3: - index = 67; + + case 0xC20: + case 0xE20: + case 0x1820: + case 0x1a20: + Rate[0] = MGN_1M; + Rate[1] = MGN_2M; + Rate[2] = MGN_5_5M; + Rate[3] = MGN_11M; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT3SS_MCS4: - index = 68; + + case 0xC24: + case 0xE24: + case 0x1824: + case 0x1a24: + Rate[0] = MGN_6M; + Rate[1] = MGN_9M; + Rate[2] = MGN_12M; + Rate[3] = MGN_18M; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT3SS_MCS5: - index = 69; + + case 0xC28: + case 0xE28: + case 0x1828: + case 0x1a28: + Rate[0] = MGN_24M; + Rate[1] = MGN_36M; + Rate[2] = MGN_48M; + Rate[3] = MGN_54M; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT3SS_MCS6: - index = 70; + + case 0xC2C: + case 0xE2C: + case 0x182C: + case 0x1a2C: + Rate[0] = MGN_MCS0; + Rate[1] = MGN_MCS1; + Rate[2] = MGN_MCS2; + Rate[3] = MGN_MCS3; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT3SS_MCS7: - index = 71; + + case 0xC30: + case 0xE30: + case 0x1830: + case 0x1a30: + Rate[0] = MGN_MCS4; + Rate[1] = MGN_MCS5; + Rate[2] = MGN_MCS6; + Rate[3] = MGN_MCS7; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT3SS_MCS8: - index = 72; + + case 0xC34: + case 0xE34: + case 0x1834: + case 0x1a34: + Rate[0] = MGN_MCS8; + Rate[1] = MGN_MCS9; + Rate[2] = MGN_MCS10; + Rate[3] = MGN_MCS11; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT3SS_MCS9: - index = 73; + + case 0xC38: + case 0xE38: + case 0x1838: + case 0x1a38: + Rate[0] = MGN_MCS12; + Rate[1] = MGN_MCS13; + Rate[2] = MGN_MCS14; + Rate[3] = MGN_MCS15; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT4SS_MCS0: - index = 74; + + case 0xC3C: + case 0xE3C: + case 0x183C: + case 0x1a3C: + Rate[0] = MGN_VHT1SS_MCS0; + Rate[1] = MGN_VHT1SS_MCS1; + Rate[2] = MGN_VHT1SS_MCS2; + Rate[3] = MGN_VHT1SS_MCS3; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT4SS_MCS1: - index = 75; + + case 0xC40: + case 0xE40: + case 0x1840: + case 0x1a40: + Rate[0] = MGN_VHT1SS_MCS4; + Rate[1] = MGN_VHT1SS_MCS5; + Rate[2] = MGN_VHT1SS_MCS6; + Rate[3] = MGN_VHT1SS_MCS7; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT4SS_MCS2: - index = 76; + + case 0xC44: + case 0xE44: + case 0x1844: + case 0x1a44: + Rate[0] = MGN_VHT1SS_MCS8; + Rate[1] = MGN_VHT1SS_MCS9; + Rate[2] = MGN_VHT2SS_MCS0; + Rate[3] = MGN_VHT2SS_MCS1; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT4SS_MCS3: - index = 77; + + case 0xC48: + case 0xE48: + case 0x1848: + case 0x1a48: + Rate[0] = MGN_VHT2SS_MCS2; + Rate[1] = MGN_VHT2SS_MCS3; + Rate[2] = MGN_VHT2SS_MCS4; + Rate[3] = MGN_VHT2SS_MCS5; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT4SS_MCS4: - index = 78; + + case 0xC4C: + case 0xE4C: + case 0x184C: + case 0x1a4C: + Rate[0] = MGN_VHT2SS_MCS6; + Rate[1] = MGN_VHT2SS_MCS7; + Rate[2] = MGN_VHT2SS_MCS8; + Rate[3] = MGN_VHT2SS_MCS9; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT4SS_MCS5: - index = 79; + + case 0xCD8: + case 0xED8: + case 0x18D8: + case 0x1aD8: + Rate[0] = MGN_MCS16; + Rate[1] = MGN_MCS17; + Rate[2] = MGN_MCS18; + Rate[3] = MGN_MCS19; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT4SS_MCS6: - index = 80; + + case 0xCDC: + case 0xEDC: + case 0x18DC: + case 0x1aDC: + Rate[0] = MGN_MCS20; + Rate[1] = MGN_MCS21; + Rate[2] = MGN_MCS22; + Rate[3] = MGN_MCS23; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT4SS_MCS7: - index = 81; + + case 0xCE0: + case 0xEE0: + case 0x18E0: + case 0x1aE0: + Rate[0] = MGN_VHT3SS_MCS0; + Rate[1] = MGN_VHT3SS_MCS1; + Rate[2] = MGN_VHT3SS_MCS2; + Rate[3] = MGN_VHT3SS_MCS3; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT4SS_MCS8: - index = 82; + + case 0xCE4: + case 0xEE4: + case 0x18E4: + case 0x1aE4: + Rate[0] = MGN_VHT3SS_MCS4; + Rate[1] = MGN_VHT3SS_MCS5; + Rate[2] = MGN_VHT3SS_MCS6; + Rate[3] = MGN_VHT3SS_MCS7; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; break; - case MGN_VHT4SS_MCS9: - index = 83; + + case 0xCE8: + case 0xEE8: + case 0x18E8: + case 0x1aE8: + Rate[0] = MGN_VHT3SS_MCS8; + Rate[1] = MGN_VHT3SS_MCS9; + for (i = 0; i < 2; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 2; break; + default: - RTW_INFO("Invalid rate 0x%x in %s\n", Rate, __FUNCTION__); + RTW_PRINT("Invalid RegAddr 0x%x in %s()\n", RegAddr, __func__); break; }; - - return index; } -s8 -_PHY_GetTxPowerByRate( - IN PADAPTER pAdapter, - IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, - IN u8 Rate -) { +void +PHY_StoreTxPowerByRateNew( + IN PADAPTER pAdapter, + IN u32 Band, + IN u32 RfPath, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data +) +{ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - s8 value = 0; - u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate); + u8 i = 0, rates[4] = {0}, rateNum = 0; + s8 PwrByRateVal[4] = {0}; + + PHY_GetRateValuesOfTxPowerByRate(pAdapter, RegAddr, BitMask, Data, rates, PwrByRateVal, &rateNum); if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { - RTW_INFO("Invalid band %d in %s\n", Band, __func__); - goto exit; - } - if (RFPath > ODM_RF_PATH_D) { - RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __func__); - goto exit; - } - if (TxNum >= RF_MAX_TX_NUM) { - RTW_INFO("Invalid TxNum %d in %s\n", TxNum, __func__); - goto exit; - } - if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) { - RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __func__); - goto exit; + RTW_PRINT("Invalid Band %d\n", Band); + return; } - value = pHalData->TxPwrByRateOffset[Band][RFPath][TxNum][rateIndex]; - -exit: - return value; -} - + if (RfPath > ODM_RF_PATH_D) { + RTW_PRINT("Invalid RfPath %d\n", RfPath); + return; + } -s8 -PHY_GetTxPowerByRate( - IN PADAPTER pAdapter, - IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, - IN u8 Rate -) { - if (!phy_is_tx_power_by_rate_needed(pAdapter)) - return 0; + for (i = 0; i < rateNum; ++i) { + u8 rate_idx = PHY_GetRateIndexOfTxPowerByRate(rates[i]); - return _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, TxNum, Rate); + pHalData->TxPwrByRateOffset[Band][RfPath][rate_idx] = PwrByRateVal[i]; + } } -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI -s8 -PHY_GetTxPowerByRateOriginal( - IN PADAPTER pAdapter, - IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, - IN u8 Rate -) { +VOID +PHY_InitTxPowerByRate( + IN PADAPTER pAdapter +) +{ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - s8 value = 0, limit = 0; - u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate); - - if ((pAdapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory == 2) || - pAdapter->registrypriv.RegEnableTxPowerByRate == 0) - return 0; - - if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { - DBG_871X("Invalid band %d in %s\n", Band, __func__); - return value; - } - if (RFPath > ODM_RF_PATH_D) { - DBG_871X("Invalid RfPath %d in %s\n", RFPath, __func__); - return value; - } - if (TxNum >= RF_MAX_TX_NUM) { - DBG_871X("Invalid TxNum %d in %s\n", TxNum, __func__); - return value; - } - if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) { - DBG_871X("Invalid RateIndex %d in %s\n", rateIndex, __func__); - return value; - } - - value = pHalData->TxPwrByRate[Band][RFPath][TxNum][rateIndex]; + u8 band = 0, rfPath = 0, rate = 0, i = 0, j = 0; - return value; + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) + for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath) + for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate) + pHalData->TxPwrByRateOffset[band][rfPath][rate] = 0; } -#endif - - VOID -PHY_SetTxPowerByRate( - IN PADAPTER pAdapter, - IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, - IN u8 Rate, - IN s8 Value -) { +phy_store_tx_power_by_rate( + IN PADAPTER pAdapter, + IN u32 Band, + IN u32 RfPath, + IN u32 TxNum, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data +) +{ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { - RTW_INFO("Invalid band %d in %s\n", Band, __FUNCTION__); - return; - } - if (RFPath > ODM_RF_PATH_D) { - RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __FUNCTION__); - return; - } - if (TxNum >= RF_MAX_TX_NUM) { - RTW_INFO("Invalid TxNum %d in %s\n", TxNum, __FUNCTION__); - return; - } - if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) { - RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __FUNCTION__); - return; - } + if (pDM_Odm->phy_reg_pg_version > 0) + PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, RegAddr, BitMask, Data); + else + RTW_INFO("Invalid PHY_REG_PG.txt version %d\n", pDM_Odm->phy_reg_pg_version); - pHalData->TxPwrByRateOffset[Band][RFPath][TxNum][rateIndex] = Value; } VOID -PHY_SetTxPowerLevelByPath( - IN PADAPTER Adapter, - IN u8 channel, - IN u8 path -) { - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - BOOLEAN bIsIn24G = (pHalData->CurrentBandType == BAND_ON_2_4G); - - /* if ( pMgntInfo->RegNByteAccess == 0 ) */ - { - if (bIsIn24G) - PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, CCK); - - PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, OFDM); - PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS0_MCS7); - - if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter)) - PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9); - - if (pHalData->NumTotalRFPath >= 2) { - PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS8_MCS15); +phy_ConvertTxPowerByRateInDbmToRelativeValues( + IN PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u8 base = 0, i = 0, value = 0, + band = 0, path = 0, index = 0, + startIndex = 0, endIndex = 0; + u8 cckRates[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}, + ofdmRates[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}, + mcs0_7Rates[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}, + mcs8_15Rates[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}, + mcs16_23Rates[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}, + vht1ssRates[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4, + MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9}, + vht2ssRates[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, + MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9}, + vht3ssRates[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4, + MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9}; - if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter)) - PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9); + /* RTW_INFO("===>PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */ - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS16_MCS23); - PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9); + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) { + for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) { + /* CCK */ + if (band == BAND_ON_2_4G) { + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, CCK); + for (i = 0; i < sizeof(cckRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, cckRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, cckRates[i], value - base); + } } - } - } -} -VOID -PHY_SetTxPowerIndexByRateArray( - IN PADAPTER pAdapter, - IN u8 RFPath, - IN CHANNEL_WIDTH BandWidth, - IN u8 Channel, - IN u8 *Rates, - IN u8 RateArraySize -) { - u32 powerIndex = 0; - int i = 0; + /* OFDM */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, OFDM); + for (i = 0; i < sizeof(ofdmRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, ofdmRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, ofdmRates[i], value - base); + } - for (i = 0; i < RateArraySize; ++i) { - powerIndex = PHY_GetTxPowerIndex(pAdapter, RFPath, Rates[i], BandWidth, Channel); - PHY_SetTxPowerIndex(pAdapter, powerIndex, RFPath, Rates[i]); - } -} + /* HT MCS0~7 */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_1SS); + for (i = 0; i < sizeof(mcs0_7Rates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i], value - base); + } -s8 -phy_GetWorldWideLimit( - s8 *LimitTable -) { - s8 min = LimitTable[0]; - u8 i = 0; + /* HT MCS8~15 */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_2SS); + for (i = 0; i < sizeof(mcs8_15Rates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i], value - base); + } - for (i = 0; i < MAX_REGULATION_NUM; ++i) { - if (LimitTable[i] < min) - min = LimitTable[i]; - } + /* HT MCS16~23 */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_3SS); + for (i = 0; i < sizeof(mcs16_23Rates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i], value - base); + } - return min; -} + /* VHT 1SS */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_1SS); + for (i = 0; i < sizeof(vht1ssRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, vht1ssRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, vht1ssRates[i], value - base); + } -s8 -phy_GetChannelIndexOfTxPowerLimit( - IN u8 Band, - IN u8 Channel -) { - s8 channelIndex = -1; - u8 i = 0; + /* VHT 2SS */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_2SS); + for (i = 0; i < sizeof(vht2ssRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, vht2ssRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, vht2ssRates[i], value - base); + } - if (Band == BAND_ON_2_4G) - channelIndex = Channel - 1; - else if (Band == BAND_ON_5G) { - for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) { - if (center_ch_5g_all[i] == Channel) - channelIndex = i; + /* VHT 3SS */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_3SS); + for (i = 0; i < sizeof(vht3ssRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, vht3ssRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, vht3ssRates[i], value - base); + } } - } else - RTW_PRINT("Invalid Band %d in %s\n", Band, __func__); - - if (channelIndex == -1) - RTW_PRINT("Invalid Channel %d of Band %d in %s\n", Channel, Band, __func__); - - return channelIndex; -} - -s8 -PHY_GetTxPowerLimit( - IN PADAPTER Adapter, - IN u32 RegPwrTblSel, - IN BAND_TYPE Band, - IN CHANNEL_WIDTH Bandwidth, - IN u8 RfPath, - IN u8 DataRate, - IN u8 Channel -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - s16 band = -1, regulation = -1, bandwidth = -1, - rateSection = -1, channel = -1; - s8 powerLimit = MAX_POWER_INDEX; - - if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory != 1) || - Adapter->registrypriv.RegEnableTxPowerLimit == 0) - return MAX_POWER_INDEX; - - switch (RegPwrTblSel) { - case 1: - regulation = TXPWR_LMT_ETSI; - break; - case 2: - regulation = TXPWR_LMT_MKK; - break; - case 3: - regulation = TXPWR_LMT_FCC; - break; - case 4: - regulation = TXPWR_LMT_WW; - break; - default: - regulation = (Band == BAND_ON_2_4G) ? pHalData->Regulation2_4G : pHalData->Regulation5G; - break; } - /* RTW_INFO("pMgntInfo->RegPwrTblSel %d, final regulation %d\n", Adapter->registrypriv.RegPwrTblSel, regulation ); */ - - - if (Band == BAND_ON_2_4G) - band = 0; - else if (Band == BAND_ON_5G) - band = 1; - - if (Bandwidth == CHANNEL_WIDTH_20) - bandwidth = 0; - else if (Bandwidth == CHANNEL_WIDTH_40) - bandwidth = 1; - else if (Bandwidth == CHANNEL_WIDTH_80) - bandwidth = 2; - else if (Bandwidth == CHANNEL_WIDTH_160) - bandwidth = 3; - - switch (DataRate) { - case MGN_1M: - case MGN_2M: - case MGN_5_5M: - case MGN_11M: - rateSection = 0; - break; - - case MGN_6M: - case MGN_9M: - case MGN_12M: - case MGN_18M: - case MGN_24M: - case MGN_36M: - case MGN_48M: - case MGN_54M: - rateSection = 1; - break; - - case MGN_MCS0: - case MGN_MCS1: - case MGN_MCS2: - case MGN_MCS3: - case MGN_MCS4: - case MGN_MCS5: - case MGN_MCS6: - case MGN_MCS7: - rateSection = 2; - break; - - case MGN_MCS8: - case MGN_MCS9: - case MGN_MCS10: - case MGN_MCS11: - case MGN_MCS12: - case MGN_MCS13: - case MGN_MCS14: - case MGN_MCS15: - rateSection = 3; - break; - - case MGN_MCS16: - case MGN_MCS17: - case MGN_MCS18: - case MGN_MCS19: - case MGN_MCS20: - case MGN_MCS21: - case MGN_MCS22: - case MGN_MCS23: - rateSection = 4; - break; - - case MGN_MCS24: - case MGN_MCS25: - case MGN_MCS26: - case MGN_MCS27: - case MGN_MCS28: - case MGN_MCS29: - case MGN_MCS30: - case MGN_MCS31: - rateSection = 5; - break; - - case MGN_VHT1SS_MCS0: - case MGN_VHT1SS_MCS1: - case MGN_VHT1SS_MCS2: - case MGN_VHT1SS_MCS3: - case MGN_VHT1SS_MCS4: - case MGN_VHT1SS_MCS5: - case MGN_VHT1SS_MCS6: - case MGN_VHT1SS_MCS7: - case MGN_VHT1SS_MCS8: - case MGN_VHT1SS_MCS9: - rateSection = 6; - break; - - case MGN_VHT2SS_MCS0: - case MGN_VHT2SS_MCS1: - case MGN_VHT2SS_MCS2: - case MGN_VHT2SS_MCS3: - case MGN_VHT2SS_MCS4: - case MGN_VHT2SS_MCS5: - case MGN_VHT2SS_MCS6: - case MGN_VHT2SS_MCS7: - case MGN_VHT2SS_MCS8: - case MGN_VHT2SS_MCS9: - rateSection = 7; - break; + /* RTW_INFO("<===PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */ +} - case MGN_VHT3SS_MCS0: - case MGN_VHT3SS_MCS1: - case MGN_VHT3SS_MCS2: - case MGN_VHT3SS_MCS3: - case MGN_VHT3SS_MCS4: - case MGN_VHT3SS_MCS5: - case MGN_VHT3SS_MCS6: - case MGN_VHT3SS_MCS7: - case MGN_VHT3SS_MCS8: - case MGN_VHT3SS_MCS9: - rateSection = 8; - break; +/* + * This function must be called if the value in the PHY_REG_PG.txt(or header) + * is exact dBm values + */ +VOID +PHY_TxPowerByRateConfiguration( + IN PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - case MGN_VHT4SS_MCS0: - case MGN_VHT4SS_MCS1: - case MGN_VHT4SS_MCS2: - case MGN_VHT4SS_MCS3: - case MGN_VHT4SS_MCS4: - case MGN_VHT4SS_MCS5: - case MGN_VHT4SS_MCS6: - case MGN_VHT4SS_MCS7: - case MGN_VHT4SS_MCS8: - case MGN_VHT4SS_MCS9: - rateSection = 9; - break; + phy_txpwr_by_rate_chk_for_path_dup(pAdapter); + phy_StoreTxPowerByRateBase(pAdapter); + phy_ConvertTxPowerByRateInDbmToRelativeValues(pAdapter); +} - default: - RTW_INFO("Wrong rate 0x%x\n", DataRate); - break; +VOID +phy_set_tx_power_index_by_rate_section( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Channel, + IN u8 RateSection +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + if (RateSection >= RATE_SECTION_NUM) { + RTW_INFO("Invalid RateSection %d in %s", RateSection, __func__); + rtw_warn_on(1); + goto exit; } - if (Band == BAND_ON_5G && rateSection == 0) - RTW_INFO("Wrong rate 0x%x: No CCK in 5G Band\n", DataRate); + if (RateSection == CCK && pHalData->current_band_type != BAND_ON_2_4G) + goto exit; - /* workaround for wrong index combination to obtain tx power limit, */ - /* OFDM only exists in BW 20M */ - if (rateSection == 1) - bandwidth = 0; + PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->current_channel_bw, Channel, + rates_by_sections[RateSection].rates, rates_by_sections[RateSection].rate_num); - /* workaround for wrong index combination to obtain tx power limit, */ - /* CCK table will only be given in BW 20M */ - if (rateSection == 0) - bandwidth = 0; +exit: + return; +} - /* workaround for wrong indxe combination to obtain tx power limit, */ - /* HT on 80M will reference to HT on 40M */ - if ((rateSection == 2 || rateSection == 3) && Band == BAND_ON_5G && bandwidth == 2) - bandwidth = 1; +BOOLEAN +phy_GetChnlIndex( + IN u8 Channel, + OUT u8 *ChannelIdx +) +{ + u8 i = 0; + BOOLEAN bIn24G = _TRUE; - if (Band == BAND_ON_2_4G) - channel = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, Channel); - else if (Band == BAND_ON_5G) - channel = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, Channel); - else if (Band == BAND_ON_BOTH) { - /* BAND_ON_BOTH don't care temporarily */ + if (Channel <= 14) { + bIn24G = _TRUE; + *ChannelIdx = Channel - 1; + } else { + bIn24G = _FALSE; + + for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) { + if (center_ch_5g_all[i] == Channel) { + *ChannelIdx = i; + return bIn24G; + } + } } - if (band == -1 || regulation == -1 || bandwidth == -1 || - rateSection == -1 || channel == -1) { - /* RTW_INFO("Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnlGroup %d]\n", */ - /* band, regulation, bandwidth, RfPath, rateSection, channelGroup ); */ + return bIn24G; +} + +u8 +PHY_GetTxPowerIndexBase( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + u8 ntx_idx, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel, + OUT PBOOLEAN bIn24G +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + u8 i = 0; /* default set to 1S */ + u8 txPower = 0; + u8 chnlIdx = (Channel - 1); - return MAX_POWER_INDEX; + if (HAL_IsLegalChannel(pAdapter, Channel) == _FALSE) { + chnlIdx = 0; + RTW_INFO("Illegal channel!!\n"); } - if (Band == BAND_ON_2_4G) { - s8 limits[10] = {0}; - u8 i = 0; - if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) - bandwidth = MAX_2_4G_BANDWIDTH_NUM - 1; - for (i = 0; i < MAX_REGULATION_NUM; ++i) - limits[i] = pHalData->TxPwrLimit_2_4G[i][bandwidth][rateSection][channel][RfPath]; - - powerLimit = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) : - pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channel][RfPath]; - - } else if (Band == BAND_ON_5G) { - s8 limits[10] = {0}; - u8 i = 0; - for (i = 0; i < MAX_REGULATION_NUM; ++i) - limits[i] = pHalData->TxPwrLimit_5G[i][bandwidth][rateSection][channel][RfPath]; - - powerLimit = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) : - pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channel][RfPath]; - } else - RTW_INFO("No power limit table of the specified band\n"); - - /* combine 5G VHT & HT rate */ - /* 5G 20M and 40M HT and VHT can cross reference */ - /* - if ( Band == BAND_ON_5G && powerLimit == MAX_POWER_INDEX ) { - if ( bandwidth == 0 || bandwidth == 1 ) { - RT_TRACE( COMP_INIT, DBG_LOUD, ( "No power limit table of the specified band %d, bandwidth %d, ratesection %d, rf path %d\n", - band, bandwidth, rateSection, RfPath ) ); - if ( rateSection == 2 ) - powerLimit = pHalData->TxPwrLimit_5G[regulation] - [bandwidth][4][channelGroup][RfPath]; - else if ( rateSection == 4 ) - powerLimit = pHalData->TxPwrLimit_5G[regulation] - [bandwidth][2][channelGroup][RfPath]; - else if ( rateSection == 3 ) - powerLimit = pHalData->TxPwrLimit_5G[regulation] - [bandwidth][5][channelGroup][RfPath]; - else if ( rateSection == 5 ) - powerLimit = pHalData->TxPwrLimit_5G[regulation] - [bandwidth][3][channelGroup][RfPath]; + *bIn24G = phy_GetChnlIndex(Channel, &chnlIdx); + + if (0) + RTW_INFO("[%s] Channel Index: %d\n", (*bIn24G ? "2.4G" : "5G"), chnlIdx); + + if (*bIn24G) { + if (IS_CCK_RATE(Rate)) { + /* CCK-nTX */ + txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx]; + txPower += pHalData->CCK_24G_Diff[RFPath][RF_1TX]; + if (ntx_idx >= RF_2TX) + txPower += pHalData->CCK_24G_Diff[RFPath][RF_2TX]; + if (ntx_idx >= RF_3TX) + txPower += pHalData->CCK_24G_Diff[RFPath][RF_3TX]; + if (ntx_idx >= RF_4TX) + txPower += pHalData->CCK_24G_Diff[RFPath][RF_4TX]; + goto exit; + } + + txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx]; + + /* OFDM-nTX */ + if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) { + txPower += pHalData->OFDM_24G_Diff[RFPath][RF_1TX]; + if (ntx_idx >= RF_2TX) + txPower += pHalData->OFDM_24G_Diff[RFPath][RF_2TX]; + if (ntx_idx >= RF_3TX) + txPower += pHalData->OFDM_24G_Diff[RFPath][RF_3TX]; + if (ntx_idx >= RF_4TX) + txPower += pHalData->OFDM_24G_Diff[RFPath][RF_4TX]; + goto exit; + } + + /* BW20-nS */ + if (BandWidth == CHANNEL_WIDTH_20) { + if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_24G_Diff[RFPath][RF_1TX]; + if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_24G_Diff[RFPath][RF_2TX]; + if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_24G_Diff[RFPath][RF_3TX]; + if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_24G_Diff[RFPath][RF_4TX]; + goto exit; + } + + /* BW40-nS */ + if (BandWidth == CHANNEL_WIDTH_40) { + if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX]; + if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX]; + if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX]; + if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX]; + goto exit; + } + + /* Willis suggest adopt BW 40M power index while in BW 80 mode */ + if (BandWidth == CHANNEL_WIDTH_80) { + if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX]; + if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX]; + if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX]; + if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX]; + goto exit; } } - */ - /* RTW_INFO("TxPwrLmt[Regulation %d][Band %d][BW %d][RFPath %d][Rate 0x%x][Chnl %d] = %d\n", */ - /* regulation, pHalData->CurrentBandType, Bandwidth, RfPath, DataRate, Channel, powerLimit); */ - return powerLimit; -} +#ifdef CONFIG_IEEE80211_BAND_5GHZ + else { + if (Rate >= MGN_6M) + txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx]; + else { + RTW_INFO("===>PHY_GetTxPowerIndexBase: INVALID Rate(0x%02x).\n", Rate); + goto exit; + } -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI -s8 -PHY_GetTxPowerLimitOriginal( - IN PADAPTER Adapter, - IN u32 RegPwrTblSel, - IN BAND_TYPE Band, - IN CHANNEL_WIDTH Bandwidth, - IN u8 RfPath, - IN u8 DataRate, - IN u8 Channel -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - s16 band = -1, regulation = -1, bandwidth = -1, - rateSection = -1, channel = -1; - s8 powerLimit = MAX_POWER_INDEX; + /* OFDM-nTX */ + if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) { + txPower += pHalData->OFDM_5G_Diff[RFPath][RF_1TX]; + if (ntx_idx >= RF_2TX) + txPower += pHalData->OFDM_5G_Diff[RFPath][RF_2TX]; + if (ntx_idx >= RF_3TX) + txPower += pHalData->OFDM_5G_Diff[RFPath][RF_3TX]; + if (ntx_idx >= RF_4TX) + txPower += pHalData->OFDM_5G_Diff[RFPath][RF_4TX]; + goto exit; + } - if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory != 1) || - Adapter->registrypriv.RegEnableTxPowerLimit == 0) - return MAX_POWER_INDEX; + /* BW20-nS */ + if (BandWidth == CHANNEL_WIDTH_20) { + if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_5G_Diff[RFPath][RF_1TX]; + if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_5G_Diff[RFPath][RF_2TX]; + if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_5G_Diff[RFPath][RF_3TX]; + if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_5G_Diff[RFPath][RF_4TX]; + goto exit; + } - switch (Adapter->registrypriv.RegPwrTblSel) { - case 1: - regulation = TXPWR_LMT_ETSI; - break; + /* BW40-nS */ + if (BandWidth == CHANNEL_WIDTH_40) { + if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_5G_Diff[RFPath][RF_1TX]; + if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_5G_Diff[RFPath][RF_2TX]; + if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_5G_Diff[RFPath][RF_3TX]; + if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_5G_Diff[RFPath][RF_4TX]; + goto exit; + } - case 2: - regulation = TXPWR_LMT_MKK; - break; + /* BW80-nS */ + if (BandWidth == CHANNEL_WIDTH_80) { + /* get 80MHz cch index */ + for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) { + if (center_ch_5g_80m[i] == Channel) { + chnlIdx = i; + break; + } + } + if (i >= CENTER_CH_5G_80M_NUM) { + rtw_warn_on(1); + txPower = 0; + goto exit; + } - case 3: - regulation = TXPWR_LMT_FCC; - break; + txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx]; - case 4: - regulation = TXPWR_LMT_WW; - break; + if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += + pHalData->BW80_5G_Diff[RFPath][RF_1TX]; + if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW80_5G_Diff[RFPath][RF_2TX]; + if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW80_5G_Diff[RFPath][RF_3TX]; + if ((MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW80_5G_Diff[RFPath][RF_4TX]; + goto exit; + } - default: - regulation = (Band == BAND_ON_2_4G) ? pHalData->Regulation2_4G - : pHalData->Regulation5G; - break; + /* TODO: BW160-nS */ + rtw_warn_on(1); } +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ + +exit: + return txPower; +} + +s8 +PHY_GetTxPowerTrackingOffset( + PADAPTER pAdapter, + u8 RFPath, + u8 Rate +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + s8 offset = 0; + + if (pDM_Odm->rf_calibrate_info.txpowertrack_control == _FALSE) + return offset; + + if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M)) { + offset = pDM_Odm->rf_calibrate_info.remnant_cck_swing_idx; + /*RTW_INFO("+Remnant_CCKSwingIdx = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_CCKSwingIdx);*/ + } else { + offset = pDM_Odm->rf_calibrate_info.remnant_ofdm_swing_idx[RFPath]; + /*RTW_INFO("+Remanant_OFDMSwingIdx[RFPath %u][Rate 0x%x] = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]); */ - /*DBG_871X("pMgntInfo->RegPwrTblSel %d, final regulation %d\n", Adapter->registrypriv.RegPwrTblSel, regulation );*/ + } + return offset; +} - if (Band == BAND_ON_2_4G) - band = 0; - else if (Band == BAND_ON_5G) - band = 1; - - if (Bandwidth == CHANNEL_WIDTH_20) - bandwidth = 0; - else if (Bandwidth == CHANNEL_WIDTH_40) - bandwidth = 1; - else if (Bandwidth == CHANNEL_WIDTH_80) - bandwidth = 2; - else if (Bandwidth == CHANNEL_WIDTH_160) - bandwidth = 3; - - switch (DataRate) { +/*The same as MRateToHwRate in hal_com.c*/ +u8 +PHY_GetRateIndexOfTxPowerByRate( + IN u8 Rate +) +{ + u8 index = 0; + switch (Rate) { case MGN_1M: + index = 0; + break; case MGN_2M: + index = 1; + break; case MGN_5_5M: + index = 2; + break; case MGN_11M: - rateSection = 0; + index = 3; break; - case MGN_6M: + index = 4; + break; case MGN_9M: + index = 5; + break; case MGN_12M: + index = 6; + break; case MGN_18M: + index = 7; + break; case MGN_24M: + index = 8; + break; case MGN_36M: + index = 9; + break; case MGN_48M: + index = 10; + break; case MGN_54M: - rateSection = 1; + index = 11; break; - case MGN_MCS0: + index = 12; + break; case MGN_MCS1: + index = 13; + break; case MGN_MCS2: + index = 14; + break; case MGN_MCS3: + index = 15; + break; case MGN_MCS4: + index = 16; + break; case MGN_MCS5: + index = 17; + break; case MGN_MCS6: + index = 18; + break; case MGN_MCS7: - rateSection = 2; + index = 19; break; - case MGN_MCS8: + index = 20; + break; case MGN_MCS9: + index = 21; + break; case MGN_MCS10: + index = 22; + break; case MGN_MCS11: + index = 23; + break; case MGN_MCS12: + index = 24; + break; case MGN_MCS13: + index = 25; + break; case MGN_MCS14: + index = 26; + break; case MGN_MCS15: - rateSection = 3; + index = 27; break; - case MGN_MCS16: + index = 28; + break; case MGN_MCS17: + index = 29; + break; case MGN_MCS18: + index = 30; + break; case MGN_MCS19: + index = 31; + break; case MGN_MCS20: + index = 32; + break; case MGN_MCS21: + index = 33; + break; case MGN_MCS22: + index = 34; + break; case MGN_MCS23: - rateSection = 4; + index = 35; break; - case MGN_MCS24: + index = 36; + break; case MGN_MCS25: + index = 37; + break; case MGN_MCS26: + index = 38; + break; case MGN_MCS27: + index = 39; + break; case MGN_MCS28: + index = 40; + break; case MGN_MCS29: + index = 41; + break; case MGN_MCS30: + index = 42; + break; case MGN_MCS31: - rateSection = 5; + index = 43; break; - case MGN_VHT1SS_MCS0: + index = 44; + break; case MGN_VHT1SS_MCS1: + index = 45; + break; case MGN_VHT1SS_MCS2: + index = 46; + break; case MGN_VHT1SS_MCS3: + index = 47; + break; case MGN_VHT1SS_MCS4: + index = 48; + break; case MGN_VHT1SS_MCS5: + index = 49; + break; case MGN_VHT1SS_MCS6: + index = 50; + break; case MGN_VHT1SS_MCS7: + index = 51; + break; case MGN_VHT1SS_MCS8: + index = 52; + break; case MGN_VHT1SS_MCS9: - rateSection = 6; + index = 53; break; - case MGN_VHT2SS_MCS0: + index = 54; + break; case MGN_VHT2SS_MCS1: + index = 55; + break; case MGN_VHT2SS_MCS2: + index = 56; + break; case MGN_VHT2SS_MCS3: + index = 57; + break; case MGN_VHT2SS_MCS4: + index = 58; + break; case MGN_VHT2SS_MCS5: + index = 59; + break; case MGN_VHT2SS_MCS6: + index = 60; + break; case MGN_VHT2SS_MCS7: + index = 61; + break; case MGN_VHT2SS_MCS8: + index = 62; + break; case MGN_VHT2SS_MCS9: - rateSection = 7; + index = 63; break; - case MGN_VHT3SS_MCS0: + index = 64; + break; case MGN_VHT3SS_MCS1: + index = 65; + break; case MGN_VHT3SS_MCS2: + index = 66; + break; case MGN_VHT3SS_MCS3: + index = 67; + break; case MGN_VHT3SS_MCS4: + index = 68; + break; case MGN_VHT3SS_MCS5: + index = 69; + break; case MGN_VHT3SS_MCS6: + index = 70; + break; case MGN_VHT3SS_MCS7: + index = 71; + break; case MGN_VHT3SS_MCS8: + index = 72; + break; case MGN_VHT3SS_MCS9: - rateSection = 8; + index = 73; break; - case MGN_VHT4SS_MCS0: + index = 74; + break; case MGN_VHT4SS_MCS1: + index = 75; + break; case MGN_VHT4SS_MCS2: + index = 76; + break; case MGN_VHT4SS_MCS3: + index = 77; + break; case MGN_VHT4SS_MCS4: + index = 78; + break; case MGN_VHT4SS_MCS5: + index = 79; + break; case MGN_VHT4SS_MCS6: + index = 80; + break; case MGN_VHT4SS_MCS7: + index = 81; + break; case MGN_VHT4SS_MCS8: + index = 82; + break; case MGN_VHT4SS_MCS9: - rateSection = 9; + index = 83; break; - default: - DBG_871X("Wrong rate 0x%x\n", DataRate); + RTW_INFO("Invalid rate 0x%x in %s\n", Rate, __FUNCTION__); break; + }; + + return index; +} + +s8 +_PHY_GetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 Rate +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + s8 value = 0; + u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate); + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + RTW_INFO("Invalid band %d in %s\n", Band, __func__); + goto exit; + } + if (RFPath > ODM_RF_PATH_D) { + RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __func__); + goto exit; + } + if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) { + RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __func__); + goto exit; + } + + value = pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex]; + +exit: + return value; +} + + +s8 +PHY_GetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 Rate +) +{ + if (!phy_is_tx_power_by_rate_needed(pAdapter)) + return 0; + + return _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, Rate); +} + +VOID +PHY_SetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 Rate, + IN s8 Value +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate); + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + RTW_INFO("Invalid band %d in %s\n", Band, __FUNCTION__); + return; + } + if (RFPath > ODM_RF_PATH_D) { + RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __FUNCTION__); + return; + } + if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) { + RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __FUNCTION__); + return; + } + + pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex] = Value; +} + +VOID +phy_set_tx_power_level_by_path( + IN PADAPTER Adapter, + IN u8 channel, + IN u8 path +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + BOOLEAN bIsIn24G = (pHalData->current_band_type == BAND_ON_2_4G); + + /* if ( pMgntInfo->RegNByteAccess == 0 ) */ + { + if (bIsIn24G) + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, CCK); + + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, OFDM); + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS0_MCS7); + + if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter)) + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9); + + if (pHalData->NumTotalRFPath >= 2) { + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS8_MCS15); + + if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter)) + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9); + + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS16_MCS23); + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9); + } + } } +} + +#ifndef DBG_TX_POWER_IDX +#define DBG_TX_POWER_IDX 0 +#endif + +VOID +PHY_SetTxPowerIndexByRateArray( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel, + IN u8 *Rates, + IN u8 RateArraySize +) +{ + u32 powerIndex = 0; + int i = 0; - if (Band == BAND_ON_5G && rateSection == 0) - DBG_871X("Wrong rate 0x%x: No CCK in 5G Band\n", DataRate); + for (i = 0; i < RateArraySize; ++i) { +#if DBG_TX_POWER_IDX + struct txpwr_idx_comp tic; - /*workaround for wrong index combination to obtain tx power limit,*/ - /*OFDM only exists in BW 20M*/ - if (rateSection == 1) - bandwidth = 0; + powerIndex = rtw_hal_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel, &tic); + RTW_INFO("TXPWR: [%c][%s]ch:%u, %s %uT, pwr_idx:%u = %u + (%d=%d:%d) + (%d) + (%d)\n" + , rf_path_char(RFPath), ch_width_str(BandWidth), Channel, MGN_RATE_STR(Rates[i]), tic.ntx_idx + 1 + , powerIndex, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias); +#else + powerIndex = phy_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel); +#endif + PHY_SetTxPowerIndex(pAdapter, powerIndex, RFPath, Rates[i]); + } +} - /*workaround for wrong index combination to obtain tx power limit,*/ - /*CCK table will only be given in BW 20M*/ - if (rateSection == 0) - bandwidth = 0; +#ifdef CONFIG_TXPWR_LIMIT +const char *const _txpwr_lmt_rs_str[] = { + "CCK", + "OFDM", + "HT", + "VHT", + "UNKNOWN", +}; - /*workaround for wrong indxe combination to obtain tx power limit,*/ - /*HT on 80M will reference to HT on 40M*/ - if ((rateSection == 2 || rateSection == 3) && Band == BAND_ON_5G && bandwidth == 2) - bandwidth = 1; +static s8 +phy_GetChannelIndexOfTxPowerLimit( + IN u8 Band, + IN u8 Channel +) +{ + s8 channelIndex = -1; + u8 i = 0; if (Band == BAND_ON_2_4G) - channel = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, Channel); - else if (Band == BAND_ON_5G) - channel = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, Channel); - else if (Band == BAND_ON_BOTH) - /*BAND_ON_BOTH don't care temporarily*/ - - if (band == -1 || regulation == -1 || bandwidth == -1 || - rateSection == -1 || channel == -1) { - /*DBG_871X("Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnlGroup %d]\n",*/ - /* band, regulation, bandwidth, RfPath, rateSection, channelGroup );*/ - - return MAX_POWER_INDEX; + channelIndex = Channel - 1; + else if (Band == BAND_ON_5G) { + for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) { + if (center_ch_5g_all[i] == Channel) + channelIndex = i; } + } else + RTW_PRINT("Invalid Band %d in %s\n", Band, __func__); + + if (channelIndex == -1) + RTW_PRINT("Invalid Channel %d of Band %d in %s\n", Channel, Band, __func__); + + return channelIndex; +} + +/* return txpwr limit absolute value */ +s8 phy_get_txpwr_lmt_abs( + IN PADAPTER Adapter, + IN const char *regd_name, + IN BAND_TYPE Band, + IN CHANNEL_WIDTH bw, + u8 tlrs, + u8 ntx_idx, + u8 cch, + u8 lock +) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(Adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(Adapter); + struct txpwr_lmt_ent *ent = NULL; + _irqL irqL; + _list *cur, *head; + s8 ch_idx; + u8 is_ww_regd = 0; + s8 lmt = MAX_POWER_INDEX; + + if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory != 1) || + Adapter->registrypriv.RegEnableTxPowerLimit == 0) + goto exit; + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + RTW_ERR("%s invalid band:%u\n", __func__, Band); + rtw_warn_on(1); + goto exit; + } + + if (Band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK) { + RTW_ERR("5G has no CCK\n"); + goto exit; + } + + if (lock) + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + if (!regd_name) /* no regd_name specified, use currnet */ + regd_name = rfctl->regd_name; + + if (rfctl->txpwr_regd_num == 0 + || strcmp(regd_name, regd_str(TXPWR_LMT_NONE)) == 0) + goto release_lock; + + if (strcmp(regd_name, regd_str(TXPWR_LMT_WW)) == 0) + is_ww_regd = 1; + + if (!is_ww_regd) { + ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name); + if (!ent) + goto release_lock; + } + + ch_idx = phy_GetChannelIndexOfTxPowerLimit(Band, cch); + if (ch_idx == -1) + goto release_lock; if (Band == BAND_ON_2_4G) { - s8 limits[10] = {0}; - u8 i = 0; + if (is_ww_regd) { + lmt = MAX_POWER_INDEX; + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + lmt = rtw_min(lmt, ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]); + } + } else + lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]; + } + #ifdef CONFIG_IEEE80211_BAND_5GHZ + else if (Band == BAND_ON_5G) { + if (is_ww_regd) { + lmt = MAX_POWER_INDEX; + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + lmt = rtw_min(lmt, ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]); + } + } else + lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]; + } + #endif + +release_lock: + if (lock) + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + +exit: + return lmt; +} - if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) - bandwidth = MAX_2_4G_BANDWIDTH_NUM - 1; +/* return txpwr limit diff value */ +inline s8 phy_get_txpwr_lmt(_adapter *adapter + , const char *regd_name + , BAND_TYPE band, CHANNEL_WIDTH bw + , u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock +) +{ + u8 tlrs; + s8 lmt = MAX_POWER_INDEX; + + if (IS_CCK_RATE_SECTION(rs)) + tlrs = TXPWR_LMT_RS_CCK; + else if (IS_OFDM_RATE_SECTION(rs)) + tlrs = TXPWR_LMT_RS_OFDM; + else if (IS_HT_RATE_SECTION(rs)) + tlrs = TXPWR_LMT_RS_HT; + else if (IS_VHT_RATE_SECTION(rs)) + tlrs = TXPWR_LMT_RS_VHT; + else { + RTW_ERR("%s invalid rs %u\n", __func__, rs); + rtw_warn_on(1); + goto exit; + } + + lmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock); + + if (lmt != MAX_POWER_INDEX) { + /* return diff value */ + lmt = lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs); + } + +exit: + return lmt; +} + +/* +* May search for secondary channels for min limit +* return txpwr limit diff value +*/ +s8 +PHY_GetTxPowerLimit(_adapter *adapter + , const char *regd_name + , BAND_TYPE band, CHANNEL_WIDTH bw + , u8 rfpath, u8 rate, u8 ntx_idx, u8 cch) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + BOOLEAN no_sc = _FALSE; + s8 tlrs = -1, rs = -1; + s8 lmt = MAX_POWER_INDEX; + u8 tmp_cch = 0; + u8 tmp_bw; + u8 bw_bmp = 0; + s8 min_lmt = MAX_POWER_INDEX; + u8 final_bw = bw, final_cch = cch; + _irqL irqL; + + /* MP mode channel don't use secondary channel */ + if (rtw_mp_mode_check(adapter) == _TRUE) + no_sc = _TRUE; + + if (IS_CCK_RATE(rate)) { + tlrs = TXPWR_LMT_RS_CCK; + rs = CCK; + } else if (IS_OFDM_RATE(rate)) { + tlrs = TXPWR_LMT_RS_OFDM; + rs = OFDM; + } else if (IS_HT_RATE(rate)) { + tlrs = TXPWR_LMT_RS_HT; + rs = HT_1SS + (IS_HT1SS_RATE(rate) ? 0 : IS_HT2SS_RATE(rate) ? 1 : IS_HT3SS_RATE(rate) ? 2 : IS_HT4SS_RATE(rate) ? 3 : 0); + } else if (IS_VHT_RATE(rate)) { + tlrs = TXPWR_LMT_RS_VHT; + rs = VHT_1SS + (IS_VHT1SS_RATE(rate) ? 0 : IS_VHT2SS_RATE(rate) ? 1 : IS_VHT3SS_RATE(rate) ? 2 : IS_VHT4SS_RATE(rate) ? 3 : 0); + } else { + RTW_ERR("%s invalid rate 0x%x\n", __func__, rate); + rtw_warn_on(1); + goto exit; + } + + if (no_sc == _TRUE) { + /* use the input center channel and bandwidth directly */ + tmp_cch = cch; + bw_bmp = ch_width_to_bw_cap(bw); + } else { + /* + * find the possible tx bandwidth bmp for this rate, and then will get center channel for each bandwidth + * if no possible tx bandwidth bmp, select valid bandwidth up to current RF bandwidth into bmp + */ + if (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM) + bw_bmp = BW_CAP_20M; /* CCK, OFDM only BW 20M */ + else if (tlrs == TXPWR_LMT_RS_HT) { + bw_bmp = rtw_get_tx_bw_bmp_of_ht_rate(dvobj, rate, bw); + if (bw_bmp == 0) + bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_40 ? CHANNEL_WIDTH_40 : bw); + } else if (tlrs == TXPWR_LMT_RS_VHT) { + bw_bmp = rtw_get_tx_bw_bmp_of_vht_rate(dvobj, rate, bw); + if (bw_bmp == 0) + bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_160 ? CHANNEL_WIDTH_160 : bw); + } else + rtw_warn_on(1); + } + + if (bw_bmp == 0) + goto exit; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + /* loop for each possible tx bandwidth to find minimum limit */ + for (tmp_bw = CHANNEL_WIDTH_20; tmp_bw <= bw; tmp_bw++) { + if (!(ch_width_to_bw_cap(tmp_bw) & bw_bmp)) + continue; + + if (no_sc == _FALSE) { + if (tmp_bw == CHANNEL_WIDTH_20) + tmp_cch = hal_data->cch_20; + else if (tmp_bw == CHANNEL_WIDTH_40) + tmp_cch = hal_data->cch_40; + else if (tmp_bw == CHANNEL_WIDTH_80) + tmp_cch = hal_data->cch_80; + else { + tmp_cch = 0; + rtw_warn_on(1); + } + } + + lmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, tmp_bw, tlrs, ntx_idx, tmp_cch, 0); + + if (min_lmt >= lmt) { + min_lmt = lmt; + final_cch = tmp_cch; + final_bw = tmp_bw; + } + + } + + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + if (min_lmt != MAX_POWER_INDEX) { + /* return diff value */ + min_lmt = min_lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs); + } + +exit: + + if (0) { + if (final_bw != bw && (IS_HT_RATE(rate) || IS_VHT_RATE(rate))) + RTW_INFO("%s min_lmt: %s ch%u -> %s ch%u\n" + , MGN_RATE_STR(rate) + , ch_width_str(bw), cch + , ch_width_str(final_bw), final_cch); + } + + return min_lmt; +} - for (i = 0; i < MAX_REGULATION_NUM; ++i) - limits[i] = pHalData->TxPwrLimit_2_4G_Original[i][bandwidth][rateSection][channel][RfPath]; +static void phy_txpwr_lmt_cck_ofdm_mt_chk(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct txpwr_lmt_ent *ent; + _list *cur, *head; + u8 channel, tlrs, ntx_idx; - powerLimit = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) : - pHalData->TxPwrLimit_2_4G_Original[regulation][bandwidth][rateSection][channel][RfPath]; + rfctl->txpwr_lmt_2g_cck_ofdm_state = 0; +#ifdef CONFIG_IEEE80211_BAND_5GHZ + rfctl->txpwr_lmt_5g_cck_ofdm_state = 0; +#endif + + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + + /* check 2G CCK, OFDM state*/ + for (tlrs = TXPWR_LMT_RS_CCK; tlrs <= TXPWR_LMT_RS_OFDM; tlrs++) { + for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { + for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) { + if (ent->lmt_2g[CHANNEL_WIDTH_20][tlrs][channel][ntx_idx] != MAX_POWER_INDEX) { + if (tlrs == TXPWR_LMT_RS_CCK) + rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_CCK_1T << ntx_idx; + else + rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx; + break; + } + } + } + } - } else if (Band == BAND_ON_5G) { - s8 limits[10] = {0}; - u8 i = 0; + /* if 2G OFDM multi-TX is not defined, reference HT20 */ + for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) { + for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { + if (rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)) + continue; + ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM][channel][ntx_idx] = + ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT][channel][ntx_idx]; + } + } - for (i = 0; i < MAX_REGULATION_NUM; ++i) - limits[i] = pHalData->TxPwrLimit_5G_Original[i][bandwidth][rateSection][channel][RfPath]; +#ifdef CONFIG_IEEE80211_BAND_5GHZ + /* check 5G OFDM state*/ + for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { + for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) { + if (ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] != MAX_POWER_INDEX) { + rfctl->txpwr_lmt_5g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx; + break; + } + } + } - powerLimit = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) : - pHalData->TxPwrLimit_5G_Original[regulation][bandwidth][rateSection][channel][RfPath]; - } else - DBG_871X("No power limit table of the specified band\n"); - - /*combine 5G VHT & HT rate*/ - /*5G 20M and 40M HT and VHT can cross reference*/ - /* - if (Band == BAND_ON_5G && powerLimit == MAX_POWER_INDEX) { - if (bandwidth == 0 || bandwidth == 1) { - RT_TRACE(COMP_INIT, DBG_LOUD, ( "No power limit table of the specified band %d, bandwidth %d, ratesection %d, rf path %d\n", - band, bandwidth, rateSection, RfPath)); - if (rateSection == 2) - powerLimit = pHalData->TxPwrLimit_5G_Original[regulation] - [bandwidth][4][channelGroup][RfPath]; - else if (rateSection == 4) - powerLimit = pHalData->TxPwrLimit_5G_Original[regulation] - [bandwidth][2][channelGroup][RfPath]; - else if (rateSection == 3) - powerLimit = pHalData->TxPwrLimit_5G_Original[regulation] - [bandwidth][5][channelGroup][RfPath]; - else if (rateSection == 5) - powerLimit = pHalData->TxPwrLimit_5G_Original[regulation] - [bandwidth][3][channelGroup][RfPath]; + for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) { + for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { + if (rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)) + continue; + /* if 5G OFDM multi-TX is not defined, reference HT20 */ + ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] = + ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT - 1][channel][ntx_idx]; + } } +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ } - */ - /*DBG_871X("TxPwrLmt[Regulation %d][Band %d][BW %d][RFPath %d][Rate 0x%x][Chnl %d] = %d\n",*/ - /* regulation, pHalData->CurrentBandType, Bandwidth, RfPath, DataRate, Channel, powerLimit);*/ - return powerLimit; } -#endif - -VOID -phy_CrossReferenceHTAndVHTTxPowerLimit( - IN PADAPTER pAdapter -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u8 regulation, bw, channel, rs, ref_rs; +#ifdef CONFIG_IEEE80211_BAND_5GHZ +static void phy_txpwr_lmt_cross_ref_ht_vht(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct txpwr_lmt_ent *ent; + _list *cur, *head; + u8 bw, channel, tlrs, ref_tlrs, ntx_idx; int ht_ref_vht_5g_20_40 = 0; int vht_ref_ht_5g_20_40 = 0; int ht_has_ref_5g_20_40 = 0; int vht_has_ref_5g_20_40 = 0; - pHalData->tx_pwr_lmt_5g_20_40_ref = 0; + rfctl->txpwr_lmt_5g_20_40_ref = 0; + + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); - for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) { - for (rs = 0; rs < MAX_RATE_SECTION_NUM; ++rs) { + for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; ++tlrs) { /* 5G 20M 40M VHT and HT can cross reference */ if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) { - if (rs == HT_1SS) - ref_rs = VHT_1SS; - else if (rs == HT_2SS) - ref_rs = VHT_2SS; - else if (rs == HT_3SS) - ref_rs = VHT_3SS; - else if (rs == HT_4SS) - ref_rs = VHT_4SS; - else if (rs == VHT_1SS) - ref_rs = HT_1SS; - else if (rs == VHT_2SS) - ref_rs = HT_2SS; - else if (rs == VHT_3SS) - ref_rs = HT_3SS; - else if (rs == VHT_4SS) - ref_rs = HT_4SS; + if (tlrs == TXPWR_LMT_RS_HT) + ref_tlrs = TXPWR_LMT_RS_VHT; + else if (tlrs == TXPWR_LMT_RS_VHT) + ref_tlrs = TXPWR_LMT_RS_HT; else continue; - if (pHalData->TxPwrLimit_5G[regulation][bw][ref_rs][channel][RF_PATH_A] == MAX_POWER_INDEX) - continue; + for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { - if (IS_HT_RATE_SECTION(rs)) - ht_has_ref_5g_20_40++; - else if (IS_VHT_RATE_SECTION(rs)) - vht_has_ref_5g_20_40++; - else - continue; + if (ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx] == MAX_POWER_INDEX) + continue; - if (pHalData->TxPwrLimit_5G[regulation][bw][rs][channel][RF_PATH_A] != MAX_POWER_INDEX) - continue; + if (tlrs == TXPWR_LMT_RS_HT) + ht_has_ref_5g_20_40++; + else if (tlrs == TXPWR_LMT_RS_VHT) + vht_has_ref_5g_20_40++; + else + continue; + + if (ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] != MAX_POWER_INDEX) + continue; - if (IS_HT_RATE_SECTION(rs) && IS_VHT_RATE_SECTION(ref_rs)) - ht_ref_vht_5g_20_40++; - else if (IS_VHT_RATE_SECTION(rs) && IS_HT_RATE_SECTION(ref_rs)) - vht_ref_ht_5g_20_40++; + if (tlrs == TXPWR_LMT_RS_HT && ref_tlrs == TXPWR_LMT_RS_VHT) + ht_ref_vht_5g_20_40++; + else if (tlrs == TXPWR_LMT_RS_VHT && ref_tlrs == TXPWR_LMT_RS_HT) + vht_ref_ht_5g_20_40++; - if (0) - RTW_INFO("reg:%u, bw:%u, ch:%u, %s ref %s\n" - , regulation, bw, channel - , rate_section_str(rs), rate_section_str(ref_rs)); + if (0) + RTW_INFO("reg:%s, bw:%u, ch:%u, %s-%uT ref %s-%uT\n" + , ent->regd_name, bw, channel + , txpwr_lmt_rs_str(tlrs), ntx_idx + 1 + , txpwr_lmt_rs_str(ref_tlrs), ntx_idx + 1); - pHalData->TxPwrLimit_5G[regulation][bw][rs][channel][RF_PATH_A] = - pHalData->TxPwrLimit_5G[regulation][bw][ref_rs][channel][RF_PATH_A]; + ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] = + ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx]; + } } } @@ -2436,170 +3159,274 @@ phy_CrossReferenceHTAndVHTTxPowerLimit( /* 5G 20M&40M HT all come from VHT*/ if (ht_ref_vht_5g_20_40 && ht_has_ref_5g_20_40 == ht_ref_vht_5g_20_40) - pHalData->tx_pwr_lmt_5g_20_40_ref |= TX_PWR_LMT_REF_HT_FROM_VHT; + rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_HT_FROM_VHT; /* 5G 20M&40M VHT all come from HT*/ if (vht_ref_ht_5g_20_40 && vht_has_ref_5g_20_40 == vht_ref_ht_5g_20_40) - pHalData->tx_pwr_lmt_5g_20_40_ref |= TX_PWR_LMT_REF_VHT_FROM_HT; + rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_VHT_FROM_HT; } +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ -VOID -PHY_ConvertTxPowerLimitToPowerIndex( - IN PADAPTER Adapter -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 base; - u8 regulation, bw, channel, rateSection; - s8 tempValue = 0, tempPwrLmt = 0; - u8 rfPath = 0; +#ifndef DBG_TXPWR_LMT_BAND_CHK +#define DBG_TXPWR_LMT_BAND_CHK 0 +#endif - if (pHalData->odmpriv.PhyRegPgValueType != PHY_REG_PG_EXACT_VALUE) { - rtw_warn_on(1); - return; - } +#if DBG_TXPWR_LMT_BAND_CHK +/* check if larger bandwidth limit is less than smaller bandwidth for HT & VHT rate */ +void phy_txpwr_limit_bandwidth_chk(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 band, bw, path, tlrs, ntx_idx, cch, offset, scch; + u8 ch_num, n, i; + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; + + for (bw = CHANNEL_WIDTH_40; bw <= CHANNEL_WIDTH_80; bw++) { + if (bw >= CHANNEL_WIDTH_160) + continue; + if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80) + continue; - phy_CrossReferenceHTAndVHTTxPowerLimit(Adapter); + if (band == BAND_ON_2_4G) + ch_num = center_chs_2g_num(bw); + else + ch_num = center_chs_5g_num(bw); - for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { + if (ch_num == 0) { + rtw_warn_on(1); + break; + } - for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) { + for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; tlrs++) { - for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) { + if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT) + continue; + if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK) + continue; + if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM)) + continue; + if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT) + continue; + if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + continue; - for (rateSection = CCK; rateSection <= HT_4SS; ++rateSection) { - tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][RF_PATH_A]; + for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { + struct txpwr_lmt_ent *ent; + _list *cur, *head; - if (tempPwrLmt != MAX_POWER_INDEX) { + if (ntx_idx >= hal_spec->tx_nss_num) + continue; - for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH; ++rfPath) { - base = phy_get_target_tx_power(Adapter, BAND_ON_2_4G, rfPath, rateSection); - tempValue = tempPwrLmt - base; - pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue; - } + /* bypass CCK multi-TX is not defined */ + if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) { + if (band == BAND_ON_2_4G + && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx))) + continue; } - } - } - } - } - if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) { + /* bypass OFDM multi-TX is not defined */ + if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) { + if (band == BAND_ON_2_4G + && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))) + continue; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (band == BAND_ON_5G + && !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))) + continue; + #endif + } - for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { + /* bypass 5G 20M, 40M pure reference */ + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) { + if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) { + if (tlrs == TXPWR_LMT_RS_HT) + continue; + } else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) { + if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40) + continue; + } + } + #endif - for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { + for (n = 0; n < ch_num; n++) { + u8 cch_by_bw[3]; + u8 offset_by_bw; /* bitmap, 0 for lower, 1 for upper */ + u8 bw_pos; + s8 lmt[3]; - for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) { + if (band == BAND_ON_2_4G) + cch = center_chs_2g(bw, n); + else + cch = center_chs_5g(bw, n); - for (rateSection = OFDM; rateSection <= VHT_4SS; ++rateSection) { - tempPwrLmt = pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][RF_PATH_A]; + if (cch == 0) { + rtw_warn_on(1); + break; + } - if (tempPwrLmt != MAX_POWER_INDEX) { + _rtw_memset(cch_by_bw, 0, 3); + cch_by_bw[bw] = cch; + offset_by_bw = 0x01; + + do { + for (bw_pos = bw; bw_pos >= CHANNEL_WIDTH_40; bw_pos--) + cch_by_bw[bw_pos - 1] = rtw_get_scch_by_cch_offset(cch_by_bw[bw_pos], bw_pos, offset_by_bw & BIT(bw_pos) ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER); + + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + + for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) + lmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0); + + for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--) + if (lmt[bw_pos] > lmt[bw_pos - 1]) + break; + if (bw_pos == CHANNEL_WIDTH_20) + continue; + + RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:" + , band_str(band) + , ch_width_str(bw) + , txpwr_lmt_rs_str(tlrs) + , ntx_idx + 1 + , ent->regd_name + ); + for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) + _RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]); + _RTW_PRINT_SEL(RTW_DBGDUMP, "limit:"); + for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) { + if (lmt[bw_pos] == MAX_POWER_INDEX) + _RTW_PRINT_SEL(RTW_DBGDUMP, "N/A "); + else + _RTW_PRINT_SEL(RTW_DBGDUMP, "%2u%s ", lmt[bw_pos] / 2, lmt[bw_pos] % 2 ? ".5" : ""); + } + _RTW_PRINT_SEL(RTW_DBGDUMP, "\n"); + } + for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) + lmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0); - for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH; ++rfPath) { - base = phy_get_target_tx_power(Adapter, BAND_ON_5G, rfPath, rateSection); - tempValue = tempPwrLmt - base; - pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][rfPath] = tempValue; + for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--) + if (lmt[bw_pos] > lmt[bw_pos - 1]) + break; + if (bw_pos != CHANNEL_WIDTH_20) { + RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:" + , band_str(band) + , ch_width_str(bw) + , txpwr_lmt_rs_str(tlrs) + , ntx_idx + 1 + , regd_str(TXPWR_LMT_WW) + ); + for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) + _RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]); + _RTW_PRINT_SEL(RTW_DBGDUMP, "limit:"); + for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) { + if (lmt[bw_pos] == MAX_POWER_INDEX) + _RTW_PRINT_SEL(RTW_DBGDUMP, "N/A "); + else + _RTW_PRINT_SEL(RTW_DBGDUMP, "%2u%s ", lmt[bw_pos] / 2, lmt[bw_pos] % 2 ? ".5" : ""); + } + _RTW_PRINT_SEL(RTW_DBGDUMP, "\n"); } - } - } - } - } - } - } + + offset_by_bw += 2; + if (offset_by_bw & BIT(bw + 1)) + break; + } while (1); /* loop for all ch combinations */ + } /* loop for center channels */ + } /* loop fo each ntx_idx */ + } /* loop for tlrs */ + } /* loop for bandwidth */ + } /* loop for band */ } +#endif /* DBG_TXPWR_LMT_BAND_CHK */ -/* -* PHY_InitTxPowerLimit - Set all hal_data.TxPwrLimit_2_4G, TxPwrLimit_5G array to MAX_POWER_INDEX -*/ -VOID -PHY_InitTxPowerLimit( - IN PADAPTER Adapter -) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 i, j, k, l, m; - - for (i = 0; i < MAX_REGULATION_NUM; ++i) - for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j) - for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) - for (m = 0; m < CENTER_CH_2G_NUM; ++m) - for (l = 0; l < MAX_RF_PATH; ++l) - pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX; - - for (i = 0; i < MAX_REGULATION_NUM; ++i) - for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j) - for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) - for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m) - for (l = 0; l < MAX_RF_PATH; ++l) - pHalData->TxPwrLimit_5G[i][j][k][m][l] = MAX_POWER_INDEX; +static void phy_txpwr_lmt_post_hdl(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + _irqL irqL; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + phy_txpwr_lmt_cross_ref_ht_vht(adapter); +#endif + phy_txpwr_lmt_cck_ofdm_mt_chk(adapter); + +#if DBG_TXPWR_LMT_BAND_CHK + phy_txpwr_limit_bandwidth_chk(adapter); +#endif + + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); } +#endif /* CONFIG_TXPWR_LIMIT */ /* -* PHY_SetTxPowerLimit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm +* phy_set_tx_power_limit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm */ VOID -PHY_SetTxPowerLimit( - IN PDM_ODM_T pDM_Odm, - IN u8 *Regulation, - IN u8 *Band, - IN u8 *Bandwidth, - IN u8 *RateSection, - IN u8 *RfPath, - IN u8 *Channel, - IN u8 *PowerLimit -) { - PADAPTER Adapter = pDM_Odm->Adapter; +phy_set_tx_power_limit( + IN struct PHY_DM_STRUCT *pDM_Odm, + IN u8 *Regulation, + IN u8 *Band, + IN u8 *Bandwidth, + IN u8 *RateSection, + IN u8 *ntx, + IN u8 *Channel, + IN u8 *PowerLimit +) +{ +#ifdef CONFIG_TXPWR_LIMIT + PADAPTER Adapter = pDM_Odm->adapter; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 regulation = 0, bandwidth = 0, rateSection = 0, channel; + u8 band = 0, bandwidth = 0, tlrs = 0, channel; + u8 ntx_idx; s8 powerLimit = 0, prevPowerLimit, channelIndex; if (0) - RTW_INFO("Index of power limit table [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s][val %s]\n" - , Band, Regulation, Bandwidth, RateSection, RfPath, Channel, PowerLimit); + RTW_INFO("Index of power limit table [regulation %s][band %s][bw %s][rate section %s][ntx %s][chnl %s][val %s]\n" + , Regulation, Band, Bandwidth, RateSection, ntx, Channel, PowerLimit); if (GetU1ByteIntegerFromStringInDecimal((s8 *)Channel, &channel) == _FALSE - || GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit) == _FALSE - ) { + || GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit) == _FALSE + ) { RTW_PRINT("Illegal index of power limit table [ch %s][val %s]\n", Channel, PowerLimit); return; } powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit; - if (eqNByte(Regulation, (u8 *)("FCC"), 3)) - regulation = TXPWR_LMT_FCC; - else if (eqNByte(Regulation, (u8 *)("MKK"), 3)) - regulation = TXPWR_LMT_MKK; - else if (eqNByte(Regulation, (u8 *)("ETSI"), 4)) - regulation = TXPWR_LMT_ETSI; - else if (eqNByte(Regulation, (u8 *)("WW13"), 4)) - regulation = TXPWR_LMT_WW; + if (eqNByte(RateSection, (u8 *)("CCK"), 3)) + tlrs = TXPWR_LMT_RS_CCK; + else if (eqNByte(RateSection, (u8 *)("OFDM"), 4)) + tlrs = TXPWR_LMT_RS_OFDM; + else if (eqNByte(RateSection, (u8 *)("HT"), 2)) + tlrs = TXPWR_LMT_RS_HT; + else if (eqNByte(RateSection, (u8 *)("VHT"), 3)) + tlrs = TXPWR_LMT_RS_VHT; else { - RTW_PRINT("unknown regulation:%s", Regulation); + RTW_PRINT("Wrong rate section:%s\n", RateSection); return; } - if (eqNByte(RateSection, (u8 *)("CCK"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2)) - rateSection = CCK; - else if (eqNByte(RateSection, (u8 *)("OFDM"), 4) && eqNByte(RfPath, (u8 *)("1T"), 2)) - rateSection = OFDM; - else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("1T"), 2)) - rateSection = HT_1SS; - else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("2T"), 2)) - rateSection = HT_2SS; - else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("3T"), 2)) - rateSection = HT_3SS; - else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("4T"), 2)) - rateSection = HT_4SS; - else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2)) - rateSection = VHT_1SS; - else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("2T"), 2)) - rateSection = VHT_2SS; - else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("3T"), 2)) - rateSection = VHT_3SS; - else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("4T"), 2)) - rateSection = VHT_4SS; + if (eqNByte(ntx, (u8 *)("1T"), 2)) + ntx_idx = RF_1TX; + else if (eqNByte(ntx, (u8 *)("2T"), 2)) + ntx_idx = RF_2TX; + else if (eqNByte(ntx, (u8 *)("3T"), 2)) + ntx_idx = RF_3TX; + else if (eqNByte(ntx, (u8 *)("4T"), 2)) + ntx_idx = RF_4TX; else { - RTW_PRINT("Wrong rate section: (%s,%s)\n", RateSection, RfPath); + RTW_PRINT("Wrong tx num:%s\n", ntx); return; } @@ -2609,12 +3436,15 @@ PHY_SetTxPowerLimit( bandwidth = CHANNEL_WIDTH_40; else if (eqNByte(Bandwidth, (u8 *)("80M"), 3)) bandwidth = CHANNEL_WIDTH_80; + else if (eqNByte(Bandwidth, (u8 *)("160M"), 4)) + bandwidth = CHANNEL_WIDTH_160; else { RTW_PRINT("unknown bandwidth: %s\n", Bandwidth); return; } if (eqNByte(Band, (u8 *)("2.4G"), 4)) { + band = BAND_ON_2_4G; channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel); if (channelIndex == -1) { @@ -2627,20 +3457,11 @@ PHY_SetTxPowerLimit( return; } - prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]; - - if (prevPowerLimit != MAX_POWER_INDEX) - RTW_PRINT("duplicate tx power limit combination [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s]\n" - , Band, Regulation, Bandwidth, RateSection, RfPath, Channel); - - if (powerLimit < prevPowerLimit) - pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit; - - if (0) - RTW_INFO("2.4G Band value : [regulation %d][bw %d][rate_section %d][chnl %d][val %d]\n" - , regulation, bandwidth, rateSection, channelIndex, pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A]); - } else if (eqNByte(Band, (u8 *)("5G"), 2)) { - + rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit); + } +#ifdef CONFIG_IEEE80211_BAND_5GHZ + else if (eqNByte(Band, (u8 *)("5G"), 2)) { + band = BAND_ON_5G; channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel); if (channelIndex == -1) { @@ -2648,81 +3469,36 @@ PHY_SetTxPowerLimit( return; } - prevPowerLimit = pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]; - - if (prevPowerLimit != MAX_POWER_INDEX) - RTW_PRINT("duplicate tx power limit combination [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s]\n" - , Band, Regulation, Bandwidth, RateSection, RfPath, Channel); - - if (powerLimit < prevPowerLimit) - pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit; - - if (0) - RTW_INFO("5G Band value : [regulation %d][bw %d][rate_section %d][chnl %d][val %d]\n" - , regulation, bandwidth, rateSection, channel, pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]); - } else { - RTW_PRINT("Cannot recognize the band info in %s\n", Band); + rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit); + } +#endif + else { + RTW_PRINT("unknown/unsupported band:%s\n", Band); return; } +#endif } u8 -PHY_GetTxPowerIndex( - IN PADAPTER pAdapter, - IN u8 RFPath, - IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, - IN u8 Channel -) { - u8 txPower = 0x3E; - - if (IS_HARDWARE_TYPE_8814A(pAdapter)) { -#if (RTL8814A_SUPPORT == 1) - txPower = PHY_GetTxPowerIndex_8814A(pAdapter, RFPath, Rate, BandWidth, Channel); -#endif - } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) { -#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) - txPower = PHY_GetTxPowerIndex_8812A(pAdapter, RFPath, Rate, BandWidth, Channel); -#endif - } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { -#if (RTL8723B_SUPPORT == 1) - txPower = PHY_GetTxPowerIndex_8723B(pAdapter, RFPath, Rate, BandWidth, Channel); -#endif - } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { -#if (RTL8703B_SUPPORT == 1) - txPower = PHY_GetTxPowerIndex_8703B(pAdapter, RFPath, Rate, BandWidth, Channel); -#endif - } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) { -#if (RTL8723D_SUPPORT == 1) - txPower = PHY_GetTxPowerIndex_8723D(pAdapter, RFPath, Rate, BandWidth, Channel); -#endif - } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { -#if (RTL8192E_SUPPORT == 1) - txPower = PHY_GetTxPowerIndex_8192E(pAdapter, RFPath, Rate, BandWidth, Channel); -#endif - } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) { -#if (RTL8188E_SUPPORT == 1) - txPower = PHY_GetTxPowerIndex_8188E(pAdapter, RFPath, Rate, BandWidth, Channel); -#endif - } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { -#if (RTL8188F_SUPPORT == 1) - txPower = PHY_GetTxPowerIndex_8188F(pAdapter, RFPath, Rate, BandWidth, Channel); -#endif - } else if (IS_HARDWARE_TYPE_8822B(pAdapter)) - txPower = rtw_hal_get_tx_power_index(pAdapter, RFPath, Rate, BandWidth, Channel); - else if (IS_HARDWARE_TYPE_8821C(pAdapter)) - txPower = rtw_hal_get_tx_power_index(pAdapter, RFPath, Rate, BandWidth, Channel); - - return txPower; +phy_get_tx_power_index( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel +) +{ + return rtw_hal_get_tx_power_index(pAdapter, RFPath, Rate, BandWidth, Channel, NULL); } VOID PHY_SetTxPowerIndex( - IN PADAPTER pAdapter, - IN u32 PowerIndex, - IN u8 RFPath, - IN u8 Rate -) { + IN PADAPTER pAdapter, + IN u32 PowerIndex, + IN u8 RFPath, + IN u8 Rate +) +{ if (IS_HARDWARE_TYPE_8814A(pAdapter)) { #if (RTL8814A_SUPPORT == 1) PHY_SetTxPowerIndex_8814A(pAdapter, PowerIndex, RFPath, Rate); @@ -2761,41 +3537,99 @@ PHY_SetTxPowerIndex( rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate); } -bool phy_is_tx_power_limit_needed(_adapter *adapter) { +void dump_tx_power_idx_title(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 bw = hal_data->current_channel_bw; + + RTW_PRINT_SEL(sel, "%s", ch_width_str(bw)); + if (bw >= CHANNEL_WIDTH_80) + _RTW_PRINT_SEL(sel, ", cch80:%u", hal_data->cch_80); + if (bw >= CHANNEL_WIDTH_40) + _RTW_PRINT_SEL(sel, ", cch40:%u", hal_data->cch_40); + _RTW_PRINT_SEL(sel, ", cch20:%u\n", hal_data->cch_20); + + RTW_PRINT_SEL(sel, "%-4s %-9s %2s %-3s %-4s %-3s %-4s %-4s %-3s %-5s\n" + , "path", "rate", "", "pwr", "base", "", "(byr", "lmt)", "tpt", "ebias"); +} + +void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 power_idx; + struct txpwr_idx_comp tic; + u8 tx_num, i; + u8 band = hal_data->current_band_type; + u8 cch = hal_data->current_channel; + u8 bw = hal_data->current_channel_bw; + + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, rfpath)) + return; + + if (rs >= RATE_SECTION_NUM) + return; + + tx_num = rate_section_to_tx_num(rs); + if (tx_num >= hal_spec->tx_nss_num || tx_num >= hal_spec->max_tx_cnt) + return; + + if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) + return; + + if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + return; + + for (i = 0; i < rates_by_sections[rs].rate_num; i++) { + power_idx = rtw_hal_get_tx_power_index(adapter, rfpath, rates_by_sections[rs].rates[i], bw, cch, &tic); + + RTW_PRINT_SEL(sel, "%4c %9s %uT %3u %4u %3d (%3d %3d) %3d %5d\n" + , rf_path_char(rfpath), MGN_RATE_STR(rates_by_sections[rs].rates[i]), tic.ntx_idx + 1 + , power_idx, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias); + } +} + +void dump_tx_power_idx(void *sel, _adapter *adapter) +{ + u8 rfpath, rs; + + dump_tx_power_idx_title(sel, adapter); + for (rfpath = RF_PATH_A; rfpath < RF_PATH_MAX; rfpath++) + for (rs = CCK; rs < RATE_SECTION_NUM; rs++) + dump_tx_power_idx_by_path_rs(sel, adapter, rfpath, rs); +} + +bool phy_is_tx_power_limit_needed(_adapter *adapter) +{ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); +#ifdef CONFIG_TXPWR_LIMIT if (regsty->RegEnableTxPowerLimit == 1 - || (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1)) + || (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1)) return _TRUE; +#endif + return _FALSE; } -bool phy_is_tx_power_by_rate_needed(_adapter *adapter) { +bool phy_is_tx_power_by_rate_needed(_adapter *adapter) +{ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); if (regsty->RegEnableTxPowerByRate == 1 - || (regsty->RegEnableTxPowerByRate == 2 && hal_data->EEPROMRegulatory != 2)) + || (regsty->RegEnableTxPowerByRate == 2 && hal_data->EEPROMRegulatory != 2)) return _TRUE; return _FALSE; } -int phy_load_tx_power_by_rate(_adapter *adapter, const char *hal_file_name, u8 force) { +int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file) +{ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); int ret = _FAIL; - if (!force - && !rtw_is_phy_file_readable(hal_file_name) - && hal_data->txpwr_by_rate_loaded == 1 - && hal_data->txpwr_by_rate_from_file == 0 - ) { - /* No file and already load default(compile-time) table */ - ret = _SUCCESS; - goto exit; - } - hal_data->txpwr_by_rate_loaded = 0; PHY_InitTxPowerByRate(adapter); @@ -2803,292 +3637,144 @@ int phy_load_tx_power_by_rate(_adapter *adapter, const char *hal_file_name, u8 f hal_data->txpwr_limit_loaded = 0; #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE - if (rtw_is_phy_file_readable(hal_file_name) - && phy_ConfigBBWithPgParaFile(adapter, hal_file_name) == _SUCCESS - ) { + if (chk_file + && phy_ConfigBBWithPgParaFile(adapter, PHY_FILE_PHY_REG_PG) == _SUCCESS + ) { hal_data->txpwr_by_rate_from_file = 1; goto post_hdl; } #endif #ifdef CONFIG_EMBEDDED_FWIMG - if (HAL_STATUS_SUCCESS == ODM_ConfigBBWithHeaderFile(&hal_data->odmpriv, CONFIG_BB_PHY_REG_PG)) { + if (HAL_STATUS_SUCCESS == odm_config_bb_with_header_file(&hal_data->odmpriv, CONFIG_BB_PHY_REG_PG)) { RTW_INFO("default power by rate loaded\n"); hal_data->txpwr_by_rate_from_file = 0; goto post_hdl; } #endif - RTW_ERR("%s():Read Tx power by rate fail\n", __func__); - goto exit; - -post_hdl: - if (hal_data->odmpriv.PhyRegPgValueType != PHY_REG_PG_EXACT_VALUE) { - rtw_warn_on(1); - goto exit; - } - - PHY_TxPowerByRateConfiguration(adapter); - hal_data->txpwr_by_rate_loaded = 1; - - ret = _SUCCESS; - -exit: - return ret; -} - -int phy_load_tx_power_limit(_adapter *adapter, const char *hal_file_name, u8 force) { - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); - int ret = _FAIL; - - if (!force - && !rtw_is_phy_file_readable(hal_file_name) - && hal_data->txpwr_by_rate_loaded == 1 - && hal_data->txpwr_by_rate_from_file == 0 - ) { - /* No file and already load default(compile-time) table */ - ret = _SUCCESS; - goto exit; - } - - hal_data->txpwr_limit_loaded = 0; - PHY_InitTxPowerLimit(adapter); - - if (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) { - RTW_ERR("%s():Read Tx power limit before target tx power is specify\n", __func__); - goto exit; - } - -#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE - if (rtw_is_phy_file_readable(hal_file_name) - && PHY_ConfigRFWithPowerLimitTableParaFile(adapter, hal_file_name) == _SUCCESS - ) { - hal_data->txpwr_limit_from_file = 1; - goto post_hdl; - } -#endif - -#ifdef CONFIG_EMBEDDED_FWIMG - if (HAL_STATUS_SUCCESS == ODM_ConfigRFWithHeaderFile(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, (ODM_RF_RADIO_PATH_E)0)) { - RTW_INFO("default power limit loaded\n"); - hal_data->txpwr_limit_from_file = 0; - goto post_hdl; - } -#endif - - RTW_ERR("%s():Read Tx power limit fail\n", __func__); - goto exit; - -post_hdl: - PHY_ConvertTxPowerLimitToPowerIndex(adapter); - hal_data->txpwr_limit_loaded = 1; - ret = _SUCCESS; - -exit: - return ret; -} - -const char *hal_phy_reg_pg_str(_adapter *adapter) { - u8 interface_type = 0; - const char *str = NULL; - - interface_type = rtw_get_intf_type(adapter); - - switch (rtw_get_chip_type(adapter)) { -#ifdef CONFIG_RTL8723B - case RTL8723B: - str = RTL8723B_PHY_REG_PG; - break; -#endif -#ifdef CONFIG_RTL8703B - case RTL8703B: - str = RTL8703B_PHY_REG_PG; - break; -#endif -#ifdef CONFIG_RTL8723D - case RTL8723D: - str = RTL8723D_PHY_REG_PG; - break; -#endif -#ifdef CONFIG_RTL8188E - case RTL8188E: - str = RTL8188E_PHY_REG_PG; - break; -#endif -#ifdef CONFIG_RTL8188F - case RTL8188F: - str = RTL8188F_PHY_REG_PG; - break; -#endif -#ifdef CONFIG_RTL8812A - case RTL8812: - str = RTL8812_PHY_REG_PG; - break; -#endif -#ifdef CONFIG_RTL8821A - case RTL8821: - str = RTL8821_PHY_REG_PG; - break; -#endif -#ifdef CONFIG_RTL8192E - case RTL8192E: - str = RTL8192E_PHY_REG_PG; - break; -#endif -#ifdef CONFIG_RTL8814A - case RTL8814A: - str = RTL8814A_PHY_REG_PG; - break; -#endif -#ifdef CONFIG_RTL8822B - case RTL8822B: - str = RTL8822B_PHY_REG_PG; - break; -#endif -#ifdef CONFIG_RTL8821C - case RTL8821C: - str = RTL8821C_PHY_REG_PG; - break; -#endif - } + RTW_ERR("%s():Read Tx power by rate fail\n", __func__); + goto exit; - if (str == NULL) { - RTW_ERR("%s: unknown chip_type:%u\n" - , __func__, rtw_get_chip_type(adapter)); +post_hdl: + if (hal_data->odmpriv.phy_reg_pg_value_type != PHY_REG_PG_EXACT_VALUE) { + rtw_warn_on(1); + goto exit; } - return str; + PHY_TxPowerByRateConfiguration(adapter); + hal_data->txpwr_by_rate_loaded = 1; + + ret = _SUCCESS; + +exit: + return ret; } -const char *hal_txpwr_lmt_str(_adapter *adapter) { - u8 interface_type = 0; - const char *str = NULL; +#ifdef CONFIG_TXPWR_LIMIT +int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + int ret = _FAIL; - interface_type = rtw_get_intf_type(adapter); + hal_data->txpwr_limit_loaded = 0; + rtw_regd_exc_list_free(rfctl); + rtw_txpwr_lmt_list_free(rfctl); - switch (rtw_get_chip_type(adapter)) { -#ifdef CONFIG_RTL8723B - case RTL8723B: - str = RTL8723B_TXPWR_LMT; - break; -#endif -#ifdef CONFIG_RTL8703B - case RTL8703B: - str = RTL8703B_TXPWR_LMT; - break; -#endif -#ifdef CONFIG_RTL8723D - case RTL8723D: - str = RTL8723D_TXPWR_LMT; - break; -#endif -#ifdef CONFIG_RTL8188E - case RTL8188E: - str = RTL8188E_TXPWR_LMT; - break; -#endif -#ifdef CONFIG_RTL8188F - case RTL8188F: - str = RTL8188F_TXPWR_LMT; - break; -#endif -#ifdef CONFIG_RTL8812A - case RTL8812: - str = RTL8812_TXPWR_LMT; - break; -#endif -#ifdef CONFIG_RTL8821A - case RTL8821: - str = RTL8821_TXPWR_LMT; - break; -#endif -#ifdef CONFIG_RTL8192E - case RTL8192E: - str = RTL8192E_TXPWR_LMT; - break; -#endif -#ifdef CONFIG_RTL8814A - case RTL8814A: - str = RTL8814A_TXPWR_LMT; - break; -#endif -#ifdef CONFIG_RTL8822B - case RTL8822B: - str = RTL8822B_TXPWR_LMT; - break; -#endif -#ifdef CONFIG_RTL8821C - case RTL8821C: - str = RTL8821C_TXPWR_LMT; - break; -#endif + if (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) { + RTW_ERR("%s():Read Tx power limit before target tx power is specify\n", __func__); + goto exit; } - if (str == NULL) { - RTW_ERR("%s: unknown chip_type:%u\n" - , __func__, rtw_get_chip_type(adapter)); +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + if (chk_file + && PHY_ConfigRFWithPowerLimitTableParaFile(adapter, PHY_FILE_TXPWR_LMT) == _SUCCESS + ) { + hal_data->txpwr_limit_from_file = 1; + goto post_hdl; + } +#endif + +#ifdef CONFIG_EMBEDDED_FWIMG + if (HAL_STATUS_SUCCESS == odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, (enum odm_rf_radio_path_e)0)) { + RTW_INFO("default power limit loaded\n"); + hal_data->txpwr_limit_from_file = 0; + goto post_hdl; } +#endif + + RTW_ERR("%s():Read Tx power limit fail\n", __func__); + goto exit; + +post_hdl: + phy_txpwr_lmt_post_hdl(adapter); + rtw_txpwr_init_regd(rfctl); + hal_data->txpwr_limit_loaded = 1; + ret = _SUCCESS; - return str; +exit: + return ret; } +#endif /* CONFIG_TXPWR_LIMIT */ -void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file, u8 force) { +void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file) +{ struct registry_priv *regsty = adapter_to_regsty(adapter); - const char *str = NULL; /* check registy target tx power */ regsty->target_tx_pwr_valid = rtw_regsty_chk_target_tx_power_valid(adapter); /* power by rate and limit */ if (phy_is_tx_power_by_rate_needed(adapter) - || (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE) - ) { - str = chk_file ? hal_phy_reg_pg_str(adapter) : NULL; - phy_load_tx_power_by_rate(adapter, str, force); - } + || (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE) + ) + phy_load_tx_power_by_rate(adapter, chk_file); - if (phy_is_tx_power_limit_needed(adapter)) { - str = chk_file ? hal_txpwr_lmt_str(adapter) : NULL; - phy_load_tx_power_limit(adapter, str, force); - } +#ifdef CONFIG_TXPWR_LIMIT + if (phy_is_tx_power_limit_needed(adapter)) + phy_load_tx_power_limit(adapter, chk_file); +#endif } -inline void phy_reload_tx_power_ext_info(_adapter *adapter) { - phy_load_tx_power_ext_info(adapter, 1, 1); +inline void phy_reload_tx_power_ext_info(_adapter *adapter) +{ + phy_load_tx_power_ext_info(adapter, 1); } -inline void phy_reload_default_tx_power_ext_info(_adapter *adapter) { - phy_load_tx_power_ext_info(adapter, 0, 1); +inline void phy_reload_default_tx_power_ext_info(_adapter *adapter) +{ + phy_load_tx_power_ext_info(adapter, 0); } -void dump_tx_power_ext_info(void *sel, _adapter *adapter) { +void dump_tx_power_ext_info(void *sel, _adapter *adapter) +{ struct registry_priv *regsty = adapter_to_regsty(adapter); HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - if (phy_is_tx_power_by_rate_needed(adapter) - || (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE)) - RTW_PRINT_SEL(sel, "target_tx_power: from powr by rate\n"); - else if (regsty->target_tx_pwr_valid == _TRUE) + if (regsty->target_tx_pwr_valid == _TRUE) RTW_PRINT_SEL(sel, "target_tx_power: from registry\n"); + else if (phy_is_tx_power_by_rate_needed(adapter)) + RTW_PRINT_SEL(sel, "target_tx_power: from power by rate\n"); else RTW_PRINT_SEL(sel, "target_tx_power: unavailable\n"); - RTW_PRINT_SEL(sel, "tx_power_by_rate: %s, %s, %s\n" - , phy_is_tx_power_by_rate_needed(adapter) ? "enabled" : "disabled" - , hal_data->txpwr_by_rate_loaded ? "loaded" : "unloaded" - , hal_data->txpwr_by_rate_from_file ? "file" : "default" - ); + , phy_is_tx_power_by_rate_needed(adapter) ? "enabled" : "disabled" + , hal_data->txpwr_by_rate_loaded ? "loaded" : "unloaded" + , hal_data->txpwr_by_rate_from_file ? "file" : "default" + ); RTW_PRINT_SEL(sel, "tx_power_limit: %s, %s, %s\n" - , phy_is_tx_power_limit_needed(adapter) ? "enabled" : "disabled" - , hal_data->txpwr_limit_loaded ? "loaded" : "unloaded" - , hal_data->txpwr_limit_from_file ? "file" : "default" - ); + , phy_is_tx_power_limit_needed(adapter) ? "enabled" : "disabled" + , hal_data->txpwr_limit_loaded ? "loaded" : "unloaded" + , hal_data->txpwr_limit_from_file ? "file" : "default" + ); } -void dump_target_tx_power(void *sel, _adapter *adapter) { +void dump_target_tx_power(void *sel, _adapter *adapter) +{ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); struct registry_priv *regsty = adapter_to_regsty(adapter); @@ -3100,14 +3786,15 @@ void dump_target_tx_power(void *sel, _adapter *adapter) { continue; for (path = 0; path < RF_PATH_MAX; path++) { - if (path >= hal_data->NumTotalRFPath) + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path)) break; - RTW_PRINT_SEL(sel, "[%s][%c]\n", band_str(band), rf_path_char(path)); + RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path) + , (regsty->target_tx_pwr_valid == _FALSE && hal_data->txpwr_by_rate_undefined_band_path[band][path]) ? "(dup)" : ""); for (rs = 0; rs < RATE_SECTION_NUM; rs++) { tx_num = rate_section_to_tx_num(rs); - if (tx_num >= hal_spec->nss_num) + if (tx_num >= hal_spec->tx_nss_num) continue; if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) @@ -3116,7 +3803,7 @@ void dump_target_tx_power(void *sel, _adapter *adapter) { if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) continue; - target = phy_get_target_tx_power(adapter, band, path, rs); + target = PHY_GetTxPowerByRateBase(adapter, band, path, rs); if (target % 2) _RTW_PRINT_SEL(sel, "%7s: %2d.5\n", rate_section_str(rs), target / 2); @@ -3130,7 +3817,8 @@ void dump_target_tx_power(void *sel, _adapter *adapter) { return; } -void dump_tx_power_by_rate(void *sel, _adapter *adapter) { +void dump_tx_power_by_rate(void *sel, _adapter *adapter) +{ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); int path, tx_num, band, n, rs; @@ -3142,14 +3830,15 @@ void dump_tx_power_by_rate(void *sel, _adapter *adapter) { continue; for (path = 0; path < RF_PATH_MAX; path++) { - if (path >= hal_data->NumTotalRFPath) + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path)) break; - RTW_PRINT_SEL(sel, "[%s][%c]\n", band_str(band), rf_path_char(path)); + RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path) + , hal_data->txpwr_by_rate_undefined_band_path[band][path] ? "(dup)" : ""); for (rs = 0; rs < RATE_SECTION_NUM; rs++) { tx_num = rate_section_to_tx_num(rs); - if (tx_num >= hal_spec->nss_num) + if (tx_num >= hal_spec->tx_nss_num) continue; if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) @@ -3163,13 +3852,13 @@ void dump_tx_power_by_rate(void *sel, _adapter *adapter) { else max_rate_num = 8; rate_num = rate_section_rate_num(rs); - base = PHY_GetTxPowerByRateBase(adapter, band, path, tx_num, rs); + base = PHY_GetTxPowerByRateBase(adapter, band, path, rs); RTW_PRINT_SEL(sel, "%7s: ", rate_section_str(rs)); /* dump power by rate in db */ for (n = rate_num - 1; n >= 0; n--) { - by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, tx_num, rates_by_sections[rs].rates[n]); + by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]); if ((base + by_rate_offset) % 2) _RTW_PRINT_SEL(sel, "%2d.5 ", (base + by_rate_offset) / 2); @@ -3183,7 +3872,7 @@ void dump_tx_power_by_rate(void *sel, _adapter *adapter) { /* dump power by rate in offset */ for (n = rate_num - 1; n >= 0; n--) { - by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, tx_num, rates_by_sections[rs].rates[n]); + by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]); _RTW_PRINT_SEL(sel, "%3d ", by_rate_offset); } RTW_PRINT_SEL(sel, "\n"); @@ -3193,184 +3882,24 @@ void dump_tx_power_by_rate(void *sel, _adapter *adapter) { } } -void dump_tx_power_limit(void *sel, _adapter *adapter) { +/* + * phy file path is stored in global char array rtw_phy_para_file_path + * need to care about racing + */ +int rtw_get_phy_file_path(_adapter *adapter, const char *file_name) +{ +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); - - int bw, band, ch_num, rs, i, path; - u8 ch, n, rd; - - if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) - RTW_PRINT_SEL(sel, "tx_pwr_lmt_5g_20_40_ref:0x%02x\n", hal_data->tx_pwr_lmt_5g_20_40_ref); - - for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { - if (!hal_is_band_support(adapter, band)) - continue; - - rd = (band == BAND_ON_2_4G ? hal_data->Regulation2_4G : hal_data->Regulation5G); - - for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) { - - if (bw >= CHANNEL_WIDTH_160) - break; - if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80) - break; - - if (band == BAND_ON_2_4G) - ch_num = CENTER_CH_2G_NUM; - else - ch_num = center_chs_5g_num(bw); - - if (ch_num == 0) { - rtw_warn_on(1); - break; - } - - for (rs = 0; rs < RATE_SECTION_NUM; rs++) { - if (band == BAND_ON_2_4G && IS_VHT_RATE_SECTION(rs)) - continue; - if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) - continue; - if (bw > CHANNEL_WIDTH_20 && (IS_CCK_RATE_SECTION(rs) || IS_OFDM_RATE_SECTION(rs))) - continue; - if (bw > CHANNEL_WIDTH_40 && IS_HT_RATE_SECTION(rs)) - continue; + int len = 0; - if (rate_section_to_tx_num(rs) >= hal_spec->nss_num) - continue; - - if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) - continue; - - /* by pass 5G 20M, 40M pure reference */ - if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) { - if (hal_data->tx_pwr_lmt_5g_20_40_ref == TX_PWR_LMT_REF_HT_FROM_VHT) { - if (IS_HT_RATE_SECTION(rs)) - continue; - } else if (hal_data->tx_pwr_lmt_5g_20_40_ref == TX_PWR_LMT_REF_VHT_FROM_HT) { - if (IS_VHT_RATE_SECTION(rs) && bw <= CHANNEL_WIDTH_40) - continue; - } - } - - RTW_PRINT_SEL(sel, "[%s][%s][%s]\n" - , band_str(band) - , ch_width_str(bw) - , rate_section_str(rs) - ); - - /* header for limit in db */ - RTW_PRINT_SEL(sel, "%3s %5s %5s %5s %5s " - , "ch" - , (rd == TXPWR_LMT_FCC ? "*FCC" : "FCC") - , (rd == TXPWR_LMT_ETSI ? "*ETSI" : "ETSI") - , (rd == TXPWR_LMT_MKK ? "*MKK" : "MKK") - , (rd == TXPWR_LMT_WW ? "*WW" : "WW") - ); - - /* header for limit offset */ - for (path = 0; path < RF_PATH_MAX; path++) { - if (path >= hal_data->NumTotalRFPath) - break; - _RTW_PRINT_SEL(sel, "|%3c %3c %3c %3c " - , (rd == TXPWR_LMT_FCC ? rf_path_char(path) : ' ') - , (rd == TXPWR_LMT_ETSI ? rf_path_char(path) : ' ') - , (rd == TXPWR_LMT_MKK ? rf_path_char(path) : ' ') - , (rd == TXPWR_LMT_WW ? rf_path_char(path) : ' ') - ); - } - _RTW_PRINT_SEL(sel, "\n"); - - for (n = 0; n < ch_num; n++) { - s8 limit_idx[RF_PATH_MAX][MAX_REGULATION_NUM]; - s8 limit_offset[MAX_REGULATION_NUM]; - u8 base; - - if (band == BAND_ON_2_4G) - ch = n + 1; - else - ch = center_chs_5g(bw, n); - - if (ch == 0) { - rtw_warn_on(1); - break; - } - - /* dump limit in db (calculate from path A) */ - limit_offset[0] = PHY_GetTxPowerLimit(adapter, 3, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* FCC */ - limit_offset[1] = PHY_GetTxPowerLimit(adapter, 1, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* ETSI */ - limit_offset[2] = PHY_GetTxPowerLimit(adapter, 2, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* MKK */ - limit_offset[3] = PHY_GetTxPowerLimit(adapter, 4, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* WW */ - - base = phy_get_target_tx_power(adapter, band, RF_PATH_A, rs); - - RTW_PRINT_SEL(sel, "%3u ", ch); - for (i = 0; i < MAX_REGULATION_NUM; i++) { - if (limit_offset[i] == MAX_POWER_INDEX) { - limit_idx[0][i] = MAX_POWER_INDEX; - _RTW_PRINT_SEL(sel, "%5s ", "NA"); - } else { - limit_idx[0][i] = limit_offset[i] + base; - if ((limit_offset[i] + base) % 2) - _RTW_PRINT_SEL(sel, "%3d.5 ", (limit_offset[i] + base) / 2); - else - _RTW_PRINT_SEL(sel, "%5d ", (limit_offset[i] + base) / 2); - } - } - - /* dump limit offset of each path */ - for (path = 0; path < RF_PATH_MAX; path++) { - if (path >= hal_data->NumTotalRFPath) - break; - limit_offset[0] = PHY_GetTxPowerLimit(adapter, 3, band, bw, path, rates_by_sections[rs].rates[0], ch); /* FCC */ - limit_offset[1] = PHY_GetTxPowerLimit(adapter, 1, band, bw, path, rates_by_sections[rs].rates[0], ch); /* ETSI */ - limit_offset[2] = PHY_GetTxPowerLimit(adapter, 2, band, bw, path, rates_by_sections[rs].rates[0], ch); /* MKK */ - limit_offset[3] = PHY_GetTxPowerLimit(adapter, 4, band, bw, path, rates_by_sections[rs].rates[0], ch); /* WW */ - - base = phy_get_target_tx_power(adapter, band, path, rs); - - _RTW_PRINT_SEL(sel, "|"); - for (i = 0; i < MAX_REGULATION_NUM; i++) { - if (limit_offset[i] == MAX_POWER_INDEX) { - limit_idx[path][i] = MAX_POWER_INDEX; - _RTW_PRINT_SEL(sel, "%3s ", "NA"); - } else { - limit_idx[path][i] = limit_offset[i] + base; - _RTW_PRINT_SEL(sel, "%3d ", limit_offset[i]); - } - } - } - - /* compare limit_idx of each path, print 'x' when mismatch */ - if (hal_data->NumTotalRFPath > 1) { - for (i = 0; i < MAX_REGULATION_NUM; i++) { - for (path = 0; path < RF_PATH_MAX; path++) { - if (path >= hal_data->NumTotalRFPath) - break; - if (limit_idx[path][i] != limit_idx[(path + 1) % hal_data->NumTotalRFPath][i]) - break; - } - if (path >= hal_data->NumTotalRFPath) - _RTW_PRINT_SEL(sel, " "); - else - _RTW_PRINT_SEL(sel, "x"); - } - } - _RTW_PRINT_SEL(sel, "\n"); - - } - RTW_PRINT_SEL(sel, "\n"); - } - } - } -} + if (file_name) { + len += snprintf(rtw_phy_para_file_path, PATH_LENGTH_MAX, "%s", rtw_phy_file_path); + #if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER) + len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s/", hal_spec->ic_name); + #endif + len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s", file_name); -int rtw_is_phy_file_readable(const char *hal_file_name) { -#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE - if (hal_file_name) { - rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, hal_file_name); - return rtw_is_file_readable(rtw_phy_para_file_path); + return _TRUE; } #endif return _FALSE; @@ -3379,9 +3908,10 @@ int rtw_is_phy_file_readable(const char *hal_file_name) { #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE int phy_ConfigMACWithParaFile( - IN PADAPTER Adapter, - IN char *pFileName -) { + IN PADAPTER Adapter, + IN char *pFileName +) +{ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); int rlen = 0, rtStatus = _FAIL; char *szLine, *ptmp; @@ -3393,8 +3923,7 @@ phy_ConfigMACWithParaFile( _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); if ((pHalData->mac_reg_len == 0) && (pHalData->mac_reg == NULL)) { - rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName); - + rtw_get_phy_file_path(Adapter, pFileName); if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); if (rlen > 0) { @@ -3441,10 +3970,11 @@ phy_ConfigMACWithParaFile( int phy_ConfigBBWithParaFile( - IN PADAPTER Adapter, - IN char *pFileName, - IN u32 ConfigType -) { + IN PADAPTER Adapter, + IN char *pFileName, + IN u32 ConfigType +) +{ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); int rlen = 0, rtStatus = _FAIL; char *szLine, *ptmp; @@ -3472,8 +4002,7 @@ phy_ConfigBBWithParaFile( _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) { - rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName); - + rtw_get_phy_file_path(Adapter, pFileName); if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); if (rlen > 0) { @@ -3533,10 +4062,10 @@ phy_ConfigBBWithParaFile( szLine += u4bMove; if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) { /* RTW_INFO("[BB-ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */ - PHY_SetBBReg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue); + phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue); if (u4bRegOffset == 0xa24) - pHalData->odmpriv.RFCalibrateInfo.RegA24 = u4bRegValue; + pHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue; /* Add 1us delay between BB/RF register setting. */ rtw_udelay_os(1); @@ -3552,9 +4081,10 @@ phy_ConfigBBWithParaFile( VOID phy_DecryptBBPgParaFile( - PADAPTER Adapter, - char *buffer -) { + PADAPTER Adapter, + char *buffer +) +{ u32 i = 0, j = 0; u8 map[95] = {0}; u8 currentChar; @@ -3589,9 +4119,10 @@ phy_DecryptBBPgParaFile( int phy_ParseBBPgParaFile( - PADAPTER Adapter, - char *buffer -) { + PADAPTER Adapter, + char *buffer +) +{ int rtStatus = _SUCCESS; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); char *szLine, *ptmp; @@ -3616,10 +4147,10 @@ phy_ParseBBPgParaFile( if (firstLine) { if (eqNByte(szLine, (u8 *)("#[v1]"), 5)) { - pHalData->odmpriv.PhyRegPgVersion = szLine[3] - '0'; + pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0'; /* RTW_INFO("This is a new format PHY_REG_PG.txt\n"); */ } else if (eqNByte(szLine, (u8 *)("#[v0]"), 5)) { - pHalData->odmpriv.PhyRegPgVersion = szLine[3] - '0'; + pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0'; /* RTW_INFO("This is a old format PHY_REG_PG.txt ok\n"); */ } else { RTW_INFO("The format in PHY_REG_PG are invalid %s\n", szLine); @@ -3627,12 +4158,12 @@ phy_ParseBBPgParaFile( } if (eqNByte(szLine + 5, (u8 *)("[Exact]#"), 8)) { - pHalData->odmpriv.PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; /* RTW_INFO("The values in PHY_REG_PG are exact values ok\n"); */ firstLine = _FALSE; continue; } else if (eqNByte(szLine + 5, (pu1Byte)("[Relative]#"), 11)) { - pHalData->odmpriv.PhyRegPgValueType = PHY_REG_PG_RELATIVE_VALUE; + pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_RELATIVE_VALUE; /* RTW_INFO("The values in PHY_REG_PG are relative values ok\n"); */ firstLine = _FALSE; continue; @@ -3642,7 +4173,7 @@ phy_ParseBBPgParaFile( } } - if (pHalData->odmpriv.PhyRegPgVersion == 0) { + if (pHalData->odmpriv.phy_reg_pg_version == 0) { /* Get 1st hex value as register offset. */ if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) { szLine += u4bMove; @@ -3657,14 +4188,14 @@ phy_ParseBBPgParaFile( else return _FAIL; - if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_RELATIVE_VALUE) { + if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_RELATIVE_VALUE) { /* Get 3rd hex value as register value. */ if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) { - PHY_StoreTxPowerByRate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, u4bRegValue); + phy_store_tx_power_by_rate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, u4bRegValue); /* RTW_INFO("[ADDR] %03X=%08X Mask=%08x\n", u4bRegOffset, u4bRegValue, u4bRegMask); */ } else return _FAIL; - } else if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) { + } else if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) { u32 combineValue = 0; u8 integer = 0, fraction = 0; @@ -3714,12 +4245,12 @@ phy_ParseBBPgParaFile( combineValue <<= 8; combineValue |= (((integer / 10) << 4) + (integer % 10)); /* RTW_INFO(" %d", integer ); */ - PHY_StoreTxPowerByRate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, combineValue); + phy_store_tx_power_by_rate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, combineValue); /* RTW_INFO("[ADDR] 0x%3x = 0x%4x\n", u4bRegOffset, combineValue ); */ } } - } else if (pHalData->odmpriv.PhyRegPgVersion > 0) { + } else if (pHalData->odmpriv.phy_reg_pg_version > 0) { u32 index = 0, cnt = 0; if (eqNByte(szLine, "0xffff", 6)) @@ -3773,14 +4304,14 @@ phy_ParseBBPgParaFile( else return _FAIL; - if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_RELATIVE_VALUE) { + if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_RELATIVE_VALUE) { /* Get 3rd hex value as register value. */ if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) { - PHY_StoreTxPowerByRate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, u4bRegValue); + phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, u4bRegValue); /* RTW_INFO("[ADDR] %03X (tx_num %d) =%08X Mask=%08x\n", u4bRegOffset, tx_num, u4bRegValue, u4bRegMask); */ } else return _FAIL; - } else if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) { + } else if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) { u32 combineValue = 0; u8 integer = 0, fraction = 0; @@ -3830,7 +4361,7 @@ phy_ParseBBPgParaFile( combineValue <<= 8; combineValue |= (((integer / 10) << 4) + (integer % 10)); /* RTW_INFO(" %d", integer ); */ - PHY_StoreTxPowerByRate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue); + phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue); /* RTW_INFO("[ADDR] 0x%3x (tx_num %d) = 0x%4x\n", u4bRegOffset, tx_num, combineValue ); */ } @@ -3845,8 +4376,9 @@ phy_ParseBBPgParaFile( int phy_ConfigBBWithPgParaFile( - IN PADAPTER Adapter, - IN const char *pFileName) { + IN PADAPTER Adapter, + IN const char *pFileName) +{ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); int rlen = 0, rtStatus = _FAIL; @@ -3856,8 +4388,7 @@ phy_ConfigBBWithPgParaFile( _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); if (pHalData->bb_phy_reg_pg == NULL) { - rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName); - + rtw_get_phy_file_path(Adapter, pFileName); if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); if (rlen > 0) { @@ -3891,9 +4422,10 @@ phy_ConfigBBWithPgParaFile( int phy_ConfigBBWithMpParaFile( - IN PADAPTER Adapter, - IN char *pFileName -) { + IN PADAPTER Adapter, + IN char *pFileName +) +{ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); int rlen = 0, rtStatus = _FAIL; char *szLine, *ptmp; @@ -3905,8 +4437,7 @@ phy_ConfigBBWithMpParaFile( _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); if ((pHalData->bb_phy_reg_mp_len == 0) && (pHalData->bb_phy_reg_mp == NULL)) { - rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName); - + rtw_get_phy_file_path(Adapter, pFileName); if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); if (rlen > 0) { @@ -3959,7 +4490,7 @@ phy_ConfigBBWithMpParaFile( szLine += u4bMove; if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) { /* RTW_INFO("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */ - PHY_SetBBReg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue); + phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue); /* Add 1us delay between BB/RF register setting. */ rtw_udelay_os(1); @@ -3977,10 +4508,11 @@ phy_ConfigBBWithMpParaFile( int PHY_ConfigRFWithParaFile( - IN PADAPTER Adapter, - IN char *pFileName, - IN u8 eRFPath -) { + IN PADAPTER Adapter, + IN char *pFileName, + IN u8 eRFPath +) +{ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); int rlen = 0, rtStatus = _FAIL; char *szLine, *ptmp; @@ -4009,8 +4541,7 @@ PHY_ConfigRFWithParaFile( _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) { - rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName); - + rtw_get_phy_file_path(Adapter, pFileName); if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); if (rlen > 0) { @@ -4075,7 +4606,7 @@ PHY_ConfigRFWithParaFile( /* Get 2nd hex value as register value. */ szLine += u4bMove; if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) { - PHY_SetRFReg(Adapter, eRFPath, u4bRegOffset, bRFRegOffsetMask, u4bRegValue); + phy_set_rf_reg(Adapter, eRFPath, u4bRegOffset, bRFRegOffsetMask, u4bRegValue); /* Temp add, for frequency lock, if no delay, that may cause */ /* frequency shift, ex: 2412MHz => 2417MHz */ @@ -4098,14 +4629,15 @@ PHY_ConfigRFWithParaFile( VOID initDeltaSwingIndexTables( - PADAPTER Adapter, - char *Band, - char *Path, - char *Sign, - char *Channel, - char *Rate, - char *Data -) { + PADAPTER Adapter, + char *Band, + char *Path, + char *Sign, + char *Channel, + char *Rate, + char *Data +) +{ #define STR_EQUAL_5G(_band, _path, _sign, _rate, _chnl) \ ((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\ (strcmp(Rate, _rate) == 0) && (strcmp(Channel, _chnl) == 0)\ @@ -4123,8 +4655,8 @@ initDeltaSwingIndexTables( } } while (0)\ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); u32 j = 0; char *token; char delim[] = ","; @@ -4134,65 +4666,66 @@ initDeltaSwingIndexTables( /* Band, Path, Sign, Channel, Rate, Data); */ if (STR_EQUAL_2G("2G", "A", "+", "CCK")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p, j); else if (STR_EQUAL_2G("2G", "A", "-", "CCK")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n, j); else if (STR_EQUAL_2G("2G", "B", "+", "CCK")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p, j); else if (STR_EQUAL_2G("2G", "B", "-", "CCK")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n, j); else if (STR_EQUAL_2G("2G", "A", "+", "ALL")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_p, j); else if (STR_EQUAL_2G("2G", "A", "-", "ALL")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_n, j); else if (STR_EQUAL_2G("2G", "B", "+", "ALL")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_p, j); else if (STR_EQUAL_2G("2G", "B", "-", "ALL")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_n, j); else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "0")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[0], j); else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "0")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[0], j); else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "0")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[0], j); else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "0")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[0], j); else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "1")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[1], j); else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "1")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[1], j); else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "1")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[1], j); else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "1")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[1], j); else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "2")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[2], j); else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "2")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[2], j); else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "2")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[2], j); else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "2")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[2], j); else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "3")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[3], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[3], j); else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "3")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[3], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[3], j); else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "3")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[3], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[3], j); else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "3")) - STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[3], j); + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[3], j); else RTW_INFO("===>initDeltaSwingIndexTables(): The input is invalid!!\n"); } int PHY_ConfigRFWithTxPwrTrackParaFile( - IN PADAPTER Adapter, - IN char *pFileName -) { + IN PADAPTER Adapter, + IN char *pFileName +) +{ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); int rlen = 0, rtStatus = _FAIL; char *szLine, *ptmp; u32 i = 0, j = 0; @@ -4204,8 +4737,7 @@ PHY_ConfigRFWithTxPwrTrackParaFile( _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); if ((pHalData->rf_tx_pwr_track_len == 0) && (pHalData->rf_tx_pwr_track == NULL)) { - rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName); - + rtw_get_phy_file_path(Adapter, pFileName); if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); if (rlen > 0) { @@ -4263,42 +4795,164 @@ PHY_ConfigRFWithTxPwrTrackParaFile( RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); #if 0 for (i = 0; i < DELTA_SWINGIDX_SIZE; ++i) { - RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P[i]); - RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N[i]); - RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P[i]); - RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N[i]); - RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P[i]); - RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N[i]); - RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P[i]); - RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N[i]); + RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_p[i]); + RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_n[i]); + RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_p[i]); + RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_n[i]); + RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[i]); + RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[i]); + RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[i]); + RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[i]); for (j = 0; j < 3; ++j) { - RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[%d][%d] = %d\n", j, i, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[j][i]); - RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[%d][%d] = %d\n", j, i, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[j][i]); - RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[%d][%d] = %d\n", j, i, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[j][i]); - RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[%d][%d] = %d\n", j, i, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[j][i]); + RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_p[j][i]); + RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_n[j][i]); + RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_p[j][i]); + RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_n[j][i]); } } #endif return rtStatus; } -int +#ifdef CONFIG_TXPWR_LIMIT + +#ifndef DBG_TXPWR_LMT_FILE_PARSE +#define DBG_TXPWR_LMT_FILE_PARSE 0 +#endif + +#define PARSE_RET_NO_HDL 0 +#define PARSE_RET_SUCCESS 1 +#define PARSE_RET_FAIL 2 + +/* +* @@Ver=2.0 +* or +* @@DomainCode=0x28, Regulation=C6 +* or +* @@CountryCode=GB, Regulation=C7 +*/ +static u8 parse_reg_exc_config(_adapter *adapter, char *szLine) +{ +#define VER_PREFIX "Ver=" +#define DOMAIN_PREFIX "DomainCode=0x" +#define COUNTRY_PREFIX "CountryCode=" +#define REG_PREFIX "Regulation=" + + const u8 ver_prefix_len = strlen(VER_PREFIX); + const u8 domain_prefix_len = strlen(DOMAIN_PREFIX); + const u8 country_prefix_len = strlen(COUNTRY_PREFIX); + const u8 reg_prefix_len = strlen(REG_PREFIX); + u32 i, i_val_s, i_val_e; + u32 j; + u8 domain = 0xFF; + char *country = NULL; + u8 parse_reg = 0; + + if (szLine[0] != '@' || szLine[1] != '@') + return PARSE_RET_NO_HDL; + + i = 2; + if (strncmp(szLine + i, VER_PREFIX, ver_prefix_len) == 0) + ; /* nothing to do */ + else if (strncmp(szLine + i, DOMAIN_PREFIX, domain_prefix_len) == 0) { + /* get string after domain prefix to ',' */ + i += domain_prefix_len; + i_val_s = i; + while (szLine[i] != ',') { + if (szLine[i] == '\0') + return PARSE_RET_FAIL; + i++; + } + i_val_e = i; + + /* check if all hex */ + for (j = i_val_s; j < i_val_e; j++) + if (IsHexDigit(szLine[j]) == _FALSE) + return PARSE_RET_FAIL; + + /* get value from hex string */ + if (sscanf(szLine + i_val_s, "%hhx", &domain) != 1) + return PARSE_RET_FAIL; + + parse_reg = 1; + } else if (strncmp(szLine + i, COUNTRY_PREFIX, country_prefix_len) == 0) { + /* get string after country prefix to ',' */ + i += country_prefix_len; + i_val_s = i; + while (szLine[i] != ',') { + if (szLine[i] == '\0') + return PARSE_RET_FAIL; + i++; + } + i_val_e = i; + + if (i_val_e - i_val_s != 2) + return PARSE_RET_FAIL; + + /* check if all alpha */ + for (j = i_val_s; j < i_val_e; j++) + if (is_alpha(szLine[j]) == _FALSE) + return PARSE_RET_FAIL; + + country = szLine + i_val_s; + + parse_reg = 1; + + } else + return PARSE_RET_FAIL; + + if (parse_reg) { + /* move to 'R' */ + while (szLine[i] != 'R') { + if (szLine[i] == '\0') + return PARSE_RET_FAIL; + i++; + } + + /* check if matching regulation prefix */ + if (strncmp(szLine + i, REG_PREFIX, reg_prefix_len) != 0) + return PARSE_RET_FAIL; + + /* get string after regulation prefix ending with space */ + i += reg_prefix_len; + i_val_s = i; + while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0') + i++; + + if (i == i_val_s) + return PARSE_RET_FAIL; + + rtw_regd_exc_add_with_nlen(adapter_to_rfctl(adapter), country, domain, szLine + i_val_s, i - i_val_s); + } + + return PARSE_RET_SUCCESS; +} + +static int phy_ParsePowerLimitTableFile( - PADAPTER Adapter, - char *buffer -) { + PADAPTER Adapter, + char *buffer +) +{ +#define LD_STAGE_EXC_MAPPING 0 +#define LD_STAGE_TAB_DEFINE 1 +#define LD_STAGE_TAB_START 2 +#define LD_STAGE_COLUMN_DEFINE 3 +#define LD_STAGE_CH_ROW 4 + + int rtStatus = _FAIL; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + u8 loadingStage = LD_STAGE_EXC_MAPPING; u32 i = 0, forCnt = 0; - u8 loadingStage = 0, limitValue = 0, fraction = 0; + u8 limitValue = 0, fraction = 0; char *szLine, *ptmp; - int rtStatus = _SUCCESS; - char band[10], bandwidth[10], rateSection[10], - regulation[TXPWR_LMT_MAX_REGULATION_NUM][10], rfPath[10], colNumBuf[10]; + char band[10], bandwidth[10], rateSection[10], ntx[10], colNumBuf[10]; + char **regulation = NULL; u8 colNum = 0; - RTW_INFO("===>phy_ParsePowerLimitTableFile()\n"); + RTW_INFO("%s enter\n", __func__); if (Adapter->registrypriv.RegDecryptCustomFile == 1) phy_DecryptBBPgParaFile(Adapter, buffer); @@ -4307,20 +4961,25 @@ phy_ParsePowerLimitTableFile( for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) { if (isAllSpaceOrTab(szLine, sizeof(*szLine))) continue; - - /* skip comment */ if (IsCommentString(szLine)) continue; - if (loadingStage == 0) { - for (forCnt = 0; forCnt < TXPWR_LMT_MAX_REGULATION_NUM; ++forCnt) - _rtw_memset((PVOID) regulation[forCnt], 0, 10); - _rtw_memset((PVOID) band, 0, 10); - _rtw_memset((PVOID) bandwidth, 0, 10); - _rtw_memset((PVOID) rateSection, 0, 10); - _rtw_memset((PVOID) rfPath, 0, 10); - _rtw_memset((PVOID) colNumBuf, 0, 10); + if (loadingStage == LD_STAGE_EXC_MAPPING) { + if (szLine[0] == '#' || szLine[1] == '#') { + loadingStage = LD_STAGE_TAB_DEFINE; + if (DBG_TXPWR_LMT_FILE_PARSE) + dump_regd_exc_list(RTW_DBGDUMP, adapter_to_rfctl(Adapter)); + } else { + if (parse_reg_exc_config(Adapter, szLine) == PARSE_RET_FAIL) { + RTW_ERR("Fail to parse regulation exception ruls!\n"); + goto exit; + } + continue; + } + } + if (loadingStage == LD_STAGE_TAB_DEFINE) { + /* read "## 2.4G, 20M, 1T, CCK" */ if (szLine[0] != '#' || szLine[1] != '#') continue; @@ -4332,25 +4991,30 @@ phy_ParsePowerLimitTableFile( szLine[--i] = ' '; /* return the space in front of the regulation info */ /* Parse the label of the table */ + _rtw_memset((PVOID) band, 0, 10); + _rtw_memset((PVOID) bandwidth, 0, 10); + _rtw_memset((PVOID) ntx, 0, 10); + _rtw_memset((PVOID) rateSection, 0, 10); if (!ParseQualifiedString(szLine, &i, band, ' ', ',')) { - RTW_INFO("Fail to parse band!\n"); - return _FAIL; + RTW_ERR("Fail to parse band!\n"); + goto exit; } if (!ParseQualifiedString(szLine, &i, bandwidth, ' ', ',')) { - RTW_INFO("Fail to parse bandwidth!\n"); - return _FAIL; + RTW_ERR("Fail to parse bandwidth!\n"); + goto exit; } - if (!ParseQualifiedString(szLine, &i, rfPath, ' ', ',')) { - RTW_INFO("Fail to parse rf path!\n"); - return _FAIL; + if (!ParseQualifiedString(szLine, &i, ntx, ' ', ',')) { + RTW_ERR("Fail to parse ntx!\n"); + goto exit; } if (!ParseQualifiedString(szLine, &i, rateSection, ' ', ',')) { - RTW_INFO("Fail to parse rate!\n"); - return _FAIL; + RTW_ERR("Fail to parse rate!\n"); + goto exit; } - loadingStage = 1; - } else if (loadingStage == 1) { + loadingStage = LD_STAGE_TAB_START; + } else if (loadingStage == LD_STAGE_TAB_START) { + /* read "## START" */ if (szLine[0] != '#' || szLine[1] != '#') continue; @@ -4360,12 +5024,13 @@ phy_ParsePowerLimitTableFile( ++i; if (!eqNByte((u8 *)(szLine + i), (u8 *)("START"), 5)) { - RTW_INFO("Lost \"## START\" label\n"); - return _FAIL; + RTW_ERR("Missing \"## START\" label\n"); + goto exit; } - loadingStage = 2; - } else if (loadingStage == 2) { + loadingStage = LD_STAGE_COLUMN_DEFINE; + } else if (loadingStage == LD_STAGE_COLUMN_DEFINE) { + /* read "## #5# FCC ETSI MKK IC KCC" */ if (szLine[0] != '#' || szLine[1] != '#') continue; @@ -4374,39 +5039,59 @@ phy_ParsePowerLimitTableFile( while (szLine[i] == ' ' || szLine[i] == '\t') ++i; + _rtw_memset((PVOID) colNumBuf, 0, 10); if (!ParseQualifiedString(szLine, &i, colNumBuf, '#', '#')) { - RTW_INFO("Fail to parse column number!\n"); - return _FAIL; + RTW_ERR("Fail to parse column number!\n"); + goto exit; + } + if (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum)) { + RTW_ERR("Column number \"%s\" is not unsigned decimal\n", colNumBuf); + goto exit; + } + if (colNum == 0) { + RTW_ERR("Column number is 0\n"); + goto exit; } - if (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum)) - return _FAIL; + if (DBG_TXPWR_LMT_FILE_PARSE) + RTW_PRINT("[%s][%s][%s][%s] column num:%d\n", band, bandwidth, rateSection, ntx, colNum); - if (colNum > TXPWR_LMT_MAX_REGULATION_NUM) { - RTW_INFO("unvalid col number %d (greater than max %d)\n", - colNum, TXPWR_LMT_MAX_REGULATION_NUM); - return _FAIL; + regulation = (char **)rtw_zmalloc(sizeof(char *) * colNum); + if (!regulation) { + RTW_ERR("Regulation alloc fail\n"); + goto exit; } for (forCnt = 0; forCnt < colNum; ++forCnt) { - u8 regulation_name_cnt = 0; + u32 i_ns; /* skip the space */ while (szLine[i] == ' ' || szLine[i] == '\t') - ++i; + i++; + i_ns = i; while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0') - regulation[forCnt][regulation_name_cnt++] = szLine[i++]; - /* RTW_INFO("regulation %s!\n", regulation[forCnt]); */ + i++; - if (regulation_name_cnt == 0) { - RTW_INFO("unvalid number of regulation!\n"); - return _FAIL; + regulation[forCnt] = (char *)rtw_malloc(i - i_ns + 1); + if (!regulation[forCnt]) { + RTW_ERR("Regulation alloc fail\n"); + goto exit; } + + _rtw_memcpy(regulation[forCnt], szLine + i_ns, i - i_ns); + regulation[forCnt][i - i_ns] = '\0'; + } + + if (DBG_TXPWR_LMT_FILE_PARSE) { + RTW_PRINT("column name:"); + for (forCnt = 0; forCnt < colNum; ++forCnt) + _RTW_PRINT(" %s", regulation[forCnt]); + _RTW_PRINT("\n"); } - loadingStage = 3; - } else if (loadingStage == 3) { + loadingStage = LD_STAGE_CH_ROW; + } else if (loadingStage == LD_STAGE_CH_ROW) { char channel[10] = {0}, powerLimit[10] = {0}; u8 cnt = 0; @@ -4417,18 +5102,29 @@ phy_ParsePowerLimitTableFile( ++i; if (eqNByte((u8 *)(szLine + i), (u8 *)("END"), 3)) { - loadingStage = 0; + loadingStage = LD_STAGE_TAB_DEFINE; + if (regulation) { + for (forCnt = 0; forCnt < colNum; ++forCnt) { + if (regulation[forCnt]) { + rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1); + regulation[forCnt] = NULL; + } + } + rtw_mfree((u8 *)regulation, sizeof(char *) * colNum); + regulation = NULL; + } + colNum = 0; continue; } else { - RTW_INFO("Wrong format\n"); - RTW_INFO("<===== phy_ParsePowerLimitTableFile()\n"); - return _FAIL; + RTW_ERR("Missing \"## END\" label\n"); + goto exit; } } if ((szLine[0] != 'c' && szLine[0] != 'C') || - (szLine[1] != 'h' && szLine[1] != 'H')) { - RTW_INFO("Meet wrong channel => power limt pair '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]); + (szLine[1] != 'h' && szLine[1] != 'H') + ) { + RTW_WARN("Wrong channel prefix: '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]); continue; } i = 2;/* move to the location behind 'h' */ @@ -4457,8 +5153,8 @@ phy_ParsePowerLimitTableFile( fraction = szLine[i + 1]; i += 2; } else { - RTW_INFO("Wrong fraction in TXPWR_LMT.txt\n"); - return _FAIL; + RTW_ERR("Wrong fraction '%c'(%d)\n", szLine[i + 1], szLine[i + 1]); + goto exit; } break; @@ -4474,8 +5170,10 @@ phy_ParsePowerLimitTableFile( powerLimit[1] = '3'; i += 2; } else { - if (!GetU1ByteIntegerFromStringInDecimal(powerLimit, &limitValue)) - return _FAIL; + if (!GetU1ByteIntegerFromStringInDecimal(powerLimit, &limitValue)) { + RTW_ERR("Limit \"%s\" is not unsigned decimal\n", powerLimit); + goto exit; + } limitValue *= 2; cnt = 0; @@ -4511,26 +5209,37 @@ phy_ParsePowerLimitTableFile( /* RTW_INFO("ch%s => %s\n", channel, powerLimit); */ /* store the power limit value */ - PHY_SetTxPowerLimit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band, - (u8 *)bandwidth, (u8 *)rateSection, (u8 *)rfPath, (u8 *)channel, (u8 *)powerLimit); + phy_set_tx_power_limit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band, + (u8 *)bandwidth, (u8 *)rateSection, (u8 *)ntx, (u8 *)channel, (u8 *)powerLimit); } - } else { - RTW_INFO("Abnormal loading stage in phy_ParsePowerLimitTableFile()!\n"); - rtStatus = _FAIL; - break; } } - RTW_INFO("<===phy_ParsePowerLimitTableFile()\n"); + rtStatus = _SUCCESS; + +exit: + if (regulation) { + for (forCnt = 0; forCnt < colNum; ++forCnt) { + if (regulation[forCnt]) { + rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1); + regulation[forCnt] = NULL; + } + } + rtw_mfree((u8 *)regulation, sizeof(char *) * colNum); + regulation = NULL; + } + + RTW_INFO("%s return %d\n", __func__, rtStatus); return rtStatus; } int PHY_ConfigRFWithPowerLimitTableParaFile( - IN PADAPTER Adapter, - IN const char *pFileName -) { + IN PADAPTER Adapter, + IN const char *pFileName +) +{ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); int rlen = 0, rtStatus = _FAIL; @@ -4540,8 +5249,7 @@ PHY_ConfigRFWithPowerLimitTableParaFile( _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); if (pHalData->rf_tx_pwr_lmt == NULL) { - rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName); - + rtw_get_phy_file_path(Adapter, pFileName); if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); if (rlen > 0) { @@ -4570,8 +5278,10 @@ PHY_ConfigRFWithPowerLimitTableParaFile( return rtStatus; } +#endif /* CONFIG_TXPWR_LIMIT */ -void phy_free_filebuf_mask(_adapter *padapter, u8 mask) { +void phy_free_filebuf_mask(_adapter *padapter, u8 mask) +{ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); if (pHalData->mac_reg && (mask & LOAD_MAC_PARA_FILE)) { @@ -4616,7 +5326,8 @@ void phy_free_filebuf_mask(_adapter *padapter, u8 mask) { } } -inline void phy_free_filebuf(_adapter *padapter) { +inline void phy_free_filebuf(_adapter *padapter) +{ phy_free_filebuf_mask(padapter, 0xFF); } diff --git a/hal/hal_dm.c b/hal/hal_dm.c index 851d529..021231b 100644 --- a/hal/hal_dm.c +++ b/hal/hal_dm.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2014 Realtek Corporation. All rights reserved. + * Copyright(c) 2014 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,20 +11,15 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #include /* A mapping from HalData to ODM. */ -ODM_BOARD_TYPE_E boardType(u8 InterfaceSel) +enum odm_board_type_e boardType(u8 InterfaceSel) { - ODM_BOARD_TYPE_E board = ODM_BOARD_DEFAULT; + enum odm_board_type_e board = ODM_BOARD_DEFAULT; #ifdef CONFIG_PCI_HCI INTERFACE_SELECT_PCIE pcie = (INTERFACE_SELECT_PCIE)InterfaceSel; @@ -74,7 +69,7 @@ void Init_ODM_ComInfo(_adapter *adapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); @@ -82,44 +77,44 @@ void Init_ODM_ComInfo(_adapter *adapter) _rtw_memset(pDM_Odm, 0, sizeof(*pDM_Odm)); - pDM_Odm->Adapter = adapter; + pDM_Odm->adapter = adapter; - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PLATFORM, ODM_CE); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PLATFORM, ODM_CE); rtw_odm_init_ic_type(adapter); if (rtw_get_intf_type(adapter) == RTW_GSPI) - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO); else - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter)); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter)); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->VersionID)); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id)); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec); if (pHalData->rf_type == RF_1T1R) - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T1R); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T1R); else if (pHalData->rf_type == RF_1T2R) - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T2R); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T2R); else if (pHalData->rf_type == RF_2T2R) - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R); else if (pHalData->rf_type == RF_2T2R_GREEN) - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R_GREEN); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R_GREEN); else if (pHalData->rf_type == RF_2T3R) - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T3R); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T3R); else if (pHalData->rf_type == RF_2T4R) - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T4R); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T4R); else if (pHalData->rf_type == RF_3T3R) - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T3R); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T3R); else if (pHalData->rf_type == RF_3T4R) - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T4R); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T4R); else if (pHalData->rf_type == RF_4T4R) - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_4T4R); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_4T4R); else - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_XTXR); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_XTXR); { @@ -128,84 +123,274 @@ void Init_ODM_ComInfo(_adapter *adapter) if (pHalData->ExternalLNA_2G != 0) { odm_board_type |= ODM_BOARD_EXT_LNA; - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1); } - if (pHalData->ExternalLNA_5G != 0) { + if (pHalData->external_lna_5g != 0) { odm_board_type |= ODM_BOARD_EXT_LNA_5G; - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1); } if (pHalData->ExternalPA_2G != 0) { odm_board_type |= ODM_BOARD_EXT_PA; - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, 1); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1); } - if (pHalData->ExternalPA_5G != 0) { + if (pHalData->external_pa_5g != 0) { odm_board_type |= ODM_BOARD_EXT_PA_5G; - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1); } if (pHalData->EEPROMBluetoothCoexist) odm_board_type |= ODM_BOARD_BT; - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type); /* 1 ============== End of BoardType ============== */ } - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_DOMAIN_CODE_2G, pHalData->Regulation2_4G); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_DOMAIN_CODE_5G, pHalData->Regulation5G); + rtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE); #ifdef CONFIG_DFS_MASTER - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter->registrypriv.dfs_region_domain); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->dfs_master_enabled)); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter->registrypriv.dfs_region_domain); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->dfs_master_enabled)); #endif - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->RFEType); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0); /*Add by YuChen for kfree init*/ - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable); - /*Add by YuChen for adaptivity init*/ - phydm_adaptivityInfoInit(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE); - phydm_adaptivityInfoInit(pDM_Odm, PHYDM_ADAPINFO_DCBACKOFF, adapter->registrypriv.adaptivity_dc_backoff); - phydm_adaptivityInfoInit(pDM_Odm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, (adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE); - phydm_adaptivityInfoInit(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini); - phydm_adaptivityInfoInit(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff); + /*Antenna diversity relative parameters*/ + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg)); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch); + /* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */ + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8); + + /*Add by YuChen for adaptivity init*/ + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode)); + phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE); + phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DCBACKOFF, adapter->registrypriv.adaptivity_dc_backoff); + phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, (adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE); + phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini); + phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff); + + if (rtw_odm_adaptivity_needed(adapter) == _TRUE) + rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter); + +#ifdef CONFIG_IQK_PA_OFF + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1); +#endif + /* odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKFWOFFLOAD, pHalData->RegIQKFWOffload); */ + rtw_hal_update_iqk_fw_offload_cap(adapter); /* Pointer reference */ - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes)); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes)); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_WM_MODE, &(pmlmeext->cur_wireless_mode)); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->CurrentBandType)); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate)); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb)); - - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC)); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm)); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->CurrentChannelBW)); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->CurrentChannel)); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed)); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb)); - - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SCAN, &(pmlmepriv->bScanInProcess)); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_WM_MODE, &(pmlmeext->cur_wireless_mode)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb)); + + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb)); + + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pmlmepriv->bScanInProcess)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving)); /*Add by Yuchen for phydm beamforming*/ - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp)); - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test)); #ifdef CONFIG_USB_HCI - ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed)); #endif for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) - ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS, i, NULL); + odm_cmn_info_ptr_array_hook(pDM_Odm, ODM_CMNINFO_STA_STATUS, i, NULL); + + phydm_init_debug_setting(pDM_Odm); /* TODO */ - /* ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */ - /* ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */ + /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */ + /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */ +} + + +static u32 edca_setting_UL[HT_IOT_PEER_MAX] = +/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/ +/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */ +{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322}; + +static u32 edca_setting_DL[HT_IOT_PEER_MAX] = +/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/ +/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/ +{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b}; + +static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] = +/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/ +/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */ +{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b}; + +void rtw_hal_turbo_edca(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct recv_priv *precvpriv = &(adapter->recvpriv); + struct registry_priv *pregpriv = &adapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /* Parameter suggested by Scott */ +#if 0 + u32 EDCA_BE_UL = edca_setting_UL[p_mgnt_info->iot_peer]; + u32 EDCA_BE_DL = edca_setting_DL[p_mgnt_info->iot_peer]; +#endif + u32 EDCA_BE_UL = 0x5ea42b; + u32 EDCA_BE_DL = 0x00a42b; + u8 ic_type = rtw_get_chip_type(adapter); + + u8 iot_peer = 0; + u8 wireless_mode = 0xFF; /* invalid value */ + u8 traffic_index; + u32 edca_param; + u64 cur_tx_bytes = 0; + u64 cur_rx_bytes = 0; + u8 bbtchange = _TRUE; + u8 is_bias_on_rx = _FALSE; + u8 is_linked = _FALSE; + u8 interface_type; + + if (hal_data->dis_turboedca) + return; + + if (rtw_mi_check_status(adapter, MI_ASSOC)) + is_linked = _TRUE; + + if (is_linked != _TRUE) { + precvpriv->is_any_non_be_pkts = _FALSE; + return; + } + + if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */ + precvpriv->is_any_non_be_pkts = _FALSE; + return; + } + + interface_type = rtw_get_intf_type(adapter); + wireless_mode = pmlmeext->cur_wireless_mode; + + iot_peer = pmlmeinfo->assoc_AP_vendor; + + if (iot_peer >= HT_IOT_PEER_MAX) { + precvpriv->is_any_non_be_pkts = _FALSE; + return; + } + + if (ic_type == RTL8188E) { + if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS)) + is_bias_on_rx = _TRUE; + } + + /* Check if the status needs to be changed. */ + if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) { + cur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes; + cur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes; + + /* traffic, TX or RX */ + if (is_bias_on_rx) { + if (cur_tx_bytes > (cur_rx_bytes << 2)) { + /* Uplink TP is present. */ + traffic_index = UP_LINK; + } else { + /* Balance TP is present. */ + traffic_index = DOWN_LINK; + } + } else { + if (cur_rx_bytes > (cur_tx_bytes << 2)) { + /* Downlink TP is present. */ + traffic_index = DOWN_LINK; + } else { + /* Balance TP is present. */ + traffic_index = UP_LINK; + } + } +#if 0 + if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index) + || (!p_dm_odm->dm_edca_table.is_current_turbo_edca)) +#endif + { + if (interface_type == RTW_PCIE) { + EDCA_BE_UL = 0x6ea42b; + EDCA_BE_DL = 0x6ea42b; + } + + /* 92D txop can't be set to 0x3e for cisco1250 */ + if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) { + EDCA_BE_DL = edca_setting_DL[iot_peer]; + EDCA_BE_UL = edca_setting_UL[iot_peer]; + } + /* merge from 92s_92c_merge temp*/ + else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B))) + EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer]; + else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A))) + EDCA_BE_DL = 0xa630; + else if (iot_peer == HT_IOT_PEER_MARVELL) { + EDCA_BE_DL = edca_setting_DL[iot_peer]; + EDCA_BE_UL = edca_setting_UL[iot_peer]; + } else if (iot_peer == HT_IOT_PEER_ATHEROS) { + /* Set DL EDCA for Atheros peer to 0x3ea42b.*/ + /* Suggested by SD3 Wilson for ASUS TP issue.*/ + EDCA_BE_DL = edca_setting_DL[iot_peer]; + } + + if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E)) { /* add 8812AU/8812AE */ + EDCA_BE_UL = 0x5ea42b; + EDCA_BE_DL = 0x5ea42b; + + RTW_DBG("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\n", EDCA_BE_UL, EDCA_BE_DL); + } + + if (interface_type == RTW_PCIE && + (ic_type == RTL8822B)) { + EDCA_BE_DL = 0xa630; + } + + if (traffic_index == DOWN_LINK) + edca_param = EDCA_BE_DL; + else + edca_param = EDCA_BE_UL; + + rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param)); + + RTW_DBG("Turbo EDCA =0x%x\n", edca_param); + + hal_data->prv_traffic_idx = traffic_index; + } + + hal_data->is_turbo_edca = _TRUE; + } else { + /* */ + /* Turn Off EDCA turbo here. */ + /* Restore original EDCA according to the declaration of AP. */ + /* */ + if (hal_data->is_turbo_edca) { + edca_param = hal_data->ac_param_be; + rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param)); + hal_data->is_turbo_edca = _FALSE; + } + } + } + + diff --git a/hal/hal_dm.h b/hal/hal_dm.h index 1232708..a25d3a7 100644 --- a/hal/hal_dm.h +++ b/hal/hal_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,15 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_DM_H__ #define __HAL_DM_H__ void Init_ODM_ComInfo(_adapter *adapter); +void rtw_hal_turbo_edca(_adapter *adapter); #endif /* __HAL_DM_H__ */ diff --git a/hal/hal_halmac.c b/hal/hal_halmac.c index fb49134..a5d2df4 100644 --- a/hal/hal_halmac.c +++ b/hal/hal_halmac.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_HALMAC_C_ #include /* PADAPTER, struct dvobj_priv, SDIO_ERR_VAL8 and etc. */ @@ -26,6 +21,7 @@ #define DEFAULT_INDICATOR_TIMELMT 1000 /* ms */ #define FIRMWARE_MAX_SIZE HALMAC_FW_SIZE_MAX_88XX +#define MSG_PREFIX "[HALMAC]" /* * Driver API for HALMAC operations @@ -33,6 +29,32 @@ #ifdef CONFIG_SDIO_HCI #include + +static u8 _halmac_mac_reg_page0_chk(const char *func, struct dvobj_priv *dvobj, u32 offset) +{ +#if defined(CONFIG_IO_CHECK_IN_ANA_LOW_CLK) && defined(CONFIG_LPS_LCLK) + struct pwrctrl_priv *pwrpriv = &dvobj->pwrctl_priv; + u32 mac_reg_offset = 0; + + if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) + return _TRUE; + + if (pwrpriv->rpwm >= PS_STATE_S2) + return _TRUE; + + if (offset & (WLAN_IOREG_DEVICE_ID << 13)) { /*WLAN_IOREG_OFFSET*/ + mac_reg_offset = offset & HALMAC_WLAN_MAC_REG_MSK; + if (mac_reg_offset < 0x100) { + RTW_ERR(FUNC_ADPT_FMT "access MAC REG -0x%04x in PS-mode:0x%02x\n", + FUNC_ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mac_reg_offset, pwrpriv->pwr_mode); + rtw_warn_on(1); + return _FALSE; + } + } +#endif + return _TRUE; +} + static u8 _halmac_sdio_cmd52_read(void *p, u32 offset) { struct dvobj_priv *d; @@ -41,9 +63,10 @@ static u8 _halmac_sdio_cmd52_read(void *p, u32 offset) d = (struct dvobj_priv *)p; + _halmac_mac_reg_page0_chk(__func__, d, offset); ret = rtw_sdio_read_cmd52(d, offset, &val, 1); if (_FAIL == ret) { - RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__); + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); return SDIO_ERR_VAL8; } @@ -57,9 +80,10 @@ static void _halmac_sdio_cmd52_write(void *p, u32 offset, u8 val) d = (struct dvobj_priv *)p; + _halmac_mac_reg_page0_chk(__func__, d, offset); ret = rtw_sdio_write_cmd52(d, offset, &val, 1); if (_FAIL == ret) - RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__); + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); } static u8 _halmac_sdio_reg_read_8(void *p, u32 offset) @@ -67,18 +91,19 @@ static u8 _halmac_sdio_reg_read_8(void *p, u32 offset) struct dvobj_priv *d; u8 *pbuf; u8 val; - int err; + u8 ret; d = (struct dvobj_priv *)p; val = SDIO_ERR_VAL8; + _halmac_mac_reg_page0_chk(__func__, d, offset); pbuf = rtw_zmalloc(1); if (!pbuf) return val; - err = d->intf_ops->read(d, offset, pbuf, 1, 0); - if (err) { - RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__); + ret = rtw_sdio_read_cmd53(d, offset, pbuf, 1); + if (ret == _FAIL) { + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); goto exit; } @@ -95,18 +120,19 @@ static u16 _halmac_sdio_reg_read_16(void *p, u32 offset) struct dvobj_priv *d; u8 *pbuf; u16 val; - int err; + u8 ret; d = (struct dvobj_priv *)p; val = SDIO_ERR_VAL16; + _halmac_mac_reg_page0_chk(__func__, d, offset); pbuf = rtw_zmalloc(2); if (!pbuf) return val; - err = d->intf_ops->read(d, offset, pbuf, 2, 0); - if (err) { - RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__); + ret = rtw_sdio_read_cmd53(d, offset, pbuf, 2); + if (ret == _FAIL) { + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); goto exit; } @@ -123,18 +149,19 @@ static u32 _halmac_sdio_reg_read_32(void *p, u32 offset) struct dvobj_priv *d; u8 *pbuf; u32 val; - int err; + u8 ret; d = (struct dvobj_priv *)p; val = SDIO_ERR_VAL32; + _halmac_mac_reg_page0_chk(__func__, d, offset); pbuf = rtw_zmalloc(4); if (!pbuf) return val; - err = d->intf_ops->read(d, offset, pbuf, 4, 0); - if (err) { - RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__); + ret = rtw_sdio_read_cmd53(d, offset, pbuf, 4); + if (ret == _FAIL) { + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); goto exit; } @@ -146,22 +173,55 @@ static u32 _halmac_sdio_reg_read_32(void *p, u32 offset) return val; } +static u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data) +{ + struct dvobj_priv *d = (struct dvobj_priv *)p; + PSDIO_DATA psdio = &d->intf_data; + u8 *pbuf; + u8 ret; + u8 rst = _FALSE; + u32 sdio_read_size; + + + sdio_read_size = RND4(size); + if (sdio_read_size > psdio->block_transfer_len) + sdio_read_size = _RND(sdio_read_size, psdio->block_transfer_len); + + pbuf = rtw_zmalloc(sdio_read_size); + if ((!pbuf) || (!data)) + return rst; + + ret = rtw_sdio_read_cmd53(d, offset, pbuf, sdio_read_size); + if (ret == _FAIL) { + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); + goto exit; + } + + _rtw_memcpy(data, pbuf, size); + rst = _TRUE; +exit: + rtw_mfree(pbuf, sdio_read_size); + + return rst; +} + static void _halmac_sdio_reg_write_8(void *p, u32 offset, u8 val) { struct dvobj_priv *d; u8 *pbuf; - int err; + u8 ret; d = (struct dvobj_priv *)p; + _halmac_mac_reg_page0_chk(__func__, d, offset); pbuf = rtw_zmalloc(1); if (!pbuf) return; _rtw_memcpy(pbuf, &val, 1); - err = d->intf_ops->write(d, offset, pbuf, 1, 0); - if (err) - RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__); + ret = rtw_sdio_write_cmd53(d, offset, pbuf, 1); + if (ret == _FAIL) + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); rtw_mfree(pbuf, 1); } @@ -170,19 +230,20 @@ static void _halmac_sdio_reg_write_16(void *p, u32 offset, u16 val) { struct dvobj_priv *d; u8 *pbuf; - int err; + u8 ret; d = (struct dvobj_priv *)p; + _halmac_mac_reg_page0_chk(__func__, d, offset); val = cpu_to_le16(val); pbuf = rtw_zmalloc(2); if (!pbuf) return; _rtw_memcpy(pbuf, &val, 2); - err = d->intf_ops->write(d, offset, pbuf, 2, 0); - if (err) - RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__); + ret = rtw_sdio_write_cmd53(d, offset, pbuf, 2); + if (ret == _FAIL) + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); rtw_mfree(pbuf, 2); } @@ -191,19 +252,20 @@ static void _halmac_sdio_reg_write_32(void *p, u32 offset, u32 val) { struct dvobj_priv *d; u8 *pbuf; - int err; + u8 ret; d = (struct dvobj_priv *)p; + _halmac_mac_reg_page0_chk(__func__, d, offset); val = cpu_to_le32(val); pbuf = rtw_zmalloc(4); if (!pbuf) return; _rtw_memcpy(pbuf, &val, 4); - err = d->intf_ops->write(d, offset, pbuf, 4, 0); - if (err) - RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__); + ret = rtw_sdio_write_cmd53(d, offset, pbuf, 4); + if (ret == _FAIL) + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); rtw_mfree(pbuf, 4); } @@ -217,7 +279,7 @@ static u8 _halmac_reg_read_8(void *p, u32 offset) d = (struct dvobj_priv *)p; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); return rtw_read8(adapter, offset); } @@ -229,7 +291,7 @@ static u16 _halmac_reg_read_16(void *p, u32 offset) d = (struct dvobj_priv *)p; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); return rtw_read16(adapter, offset); } @@ -241,7 +303,7 @@ static u32 _halmac_reg_read_32(void *p, u32 offset) d = (struct dvobj_priv *)p; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); return rtw_read32(adapter, offset); } @@ -254,11 +316,11 @@ static void _halmac_reg_write_8(void *p, u32 offset, u8 val) d = (struct dvobj_priv *)p; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); err = rtw_write8(adapter, offset, val); if (err == _FAIL) - RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__); + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); } static void _halmac_reg_write_16(void *p, u32 offset, u16 val) @@ -269,11 +331,11 @@ static void _halmac_reg_write_16(void *p, u32 offset, u16 val) d = (struct dvobj_priv *)p; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); err = rtw_write16(adapter, offset, val); if (err == _FAIL) - RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__); + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); } static void _halmac_reg_write_32(void *p, u32 offset, u32 val) @@ -284,11 +346,11 @@ static void _halmac_reg_write_32(void *p, u32 offset, u32 val) d = (struct dvobj_priv *)p; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); err = rtw_write32(adapter, offset, val); if (err == _FAIL) - RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__); + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); } #endif /* !CONFIG_SDIO_HCI */ @@ -352,41 +414,47 @@ static u8 _halmac_mutex_unlock(void *p, HALMAC_MUTEX *pMutex) static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...) { #define MSG_LEN 100 -#define MSG_PREFIX "[HALMAC]" va_list args; u8 str[MSG_LEN] = {0}; - u32 type; - u8 level; + int err; + u8 ret = _TRUE; str[0] = '\n'; - type = 0xFFFFFFFF; - if (rtw_drv_log_level <= _DRV_ERR_) - level = HALMAC_DBG_ERR; - else if (rtw_drv_log_level <= _DRV_INFO_) - level = HALMAC_DBG_WARN; - else - level = HALMAC_DBG_TRACE; - - if (!(type & BIT(msg_type))) - return _TRUE; - if (level < msg_level) - return _TRUE; - va_start(args, fmt); - vsnprintf(str, MSG_LEN, fmt, args); + err = vsnprintf(str, MSG_LEN, fmt, args); va_end(args); - if (msg_level <= HALMAC_DBG_ERR) + /* An output error is encountered */ + if (err < 0) + return _FALSE; + /* Output may be truncated due to size limit */ + if ((err == (MSG_LEN - 1)) && (str[MSG_LEN - 2] != '\n')) + ret = _FALSE; + + if (msg_level == HALMAC_DBG_ALWAYS) + RTW_PRINT(MSG_PREFIX "%s", str); + else if (msg_level <= HALMAC_DBG_ERR) RTW_ERR(MSG_PREFIX "%s", str); else if (msg_level <= HALMAC_DBG_WARN) RTW_WARN(MSG_PREFIX "%s", str); else RTW_DBG(MSG_PREFIX "%s", str); + return ret; +} + +static u8 _halmac_buff_print(void *p, u32 msg_type, u8 msg_level, s8 *buf, u32 size) +{ + if (msg_level <= HALMAC_DBG_WARN) + RTW_INFO_DUMP(MSG_PREFIX, buf, size); + else + RTW_DBG_DUMP(MSG_PREFIX, buf, size); + return _TRUE; } + const char *const RTW_HALMAC_FEATURE_NAME[] = { "HALMAC_FEATURE_CFG_PARA", "HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE", @@ -409,17 +477,15 @@ static inline u8 is_valid_id_status(HALMAC_FEATURE_ID id, HALMAC_CMD_PROCESS_STA break; case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE: RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); - if (HALMAC_CMD_PROCESS_DONE != status) { - RTW_INFO("%s: id(%d) unspecified status(%d)!\n", + if (HALMAC_CMD_PROCESS_DONE != status) + RTW_INFO("%s: id(%d) unspecified status(%d)!\n", __FUNCTION__, id, status); - } break; case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE: RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); - if (HALMAC_CMD_PROCESS_DONE != status) { - RTW_INFO("%s: id(%d) unspecified status(%d)!\n", + if (HALMAC_CMD_PROCESS_DONE != status) + RTW_INFO("%s: id(%d) unspecified status(%d)!\n", __FUNCTION__, id, status); - } break; case HALMAC_FEATURE_UPDATE_PACKET: RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); @@ -446,7 +512,7 @@ static inline u8 is_valid_id_status(HALMAC_FEATURE_ID id, HALMAC_CMD_PROCESS_STA RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); break; default: - RTW_INFO("%s: unknown feature id(%d)\n", __FUNCTION__, id); + RTW_ERR("%s: unknown feature id(%d)\n", __FUNCTION__, id); return _FALSE; } @@ -463,7 +529,7 @@ static int init_halmac_event_with_waittime(struct dvobj_priv *d, HALMAC_FEATURE_ if (!sctx) return -1; } else { - RTW_INFO("%s: id(%d) sctx is not NULL!!\n", __FUNCTION__, id); + RTW_WARN("%s: id(%d) sctx is not NULL!!\n", __FUNCTION__, id); sctx = d->hmpriv.indicator[id].sctx; d->hmpriv.indicator[id].sctx = NULL; } @@ -499,6 +565,8 @@ static void free_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) static int wait_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) { + PHALMAC_ADAPTER mac; + PHALMAC_API api; struct submit_ctx *sctx; int ret; @@ -512,6 +580,13 @@ static int wait_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) if (_SUCCESS == ret) return 0; + /* timeout! We have to reset halmac state */ + RTW_ERR("%s: Wait id(%d, %s) TIMEOUT! Reset HALMAC state!\n", + __FUNCTION__, id, RTW_HALMAC_FEATURE_NAME[id]); + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + api->halmac_reset_feature(mac, id); + return -1; } @@ -531,10 +606,11 @@ static u8 _halmac_event_indication(void *p, HALMAC_FEATURE_ID feature_id, HALMAC d = (struct dvobj_priv *)p; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); hal = GET_HAL_DATA(adapter); tbl = d->hmpriv.indicator; + /* Filter(Skip) middle status indication */ ret = is_valid_id_status(feature_id, process_status); if (_FALSE == ret) goto exit; @@ -543,23 +619,24 @@ static u8 _halmac_event_indication(void *p, HALMAC_FEATURE_ID feature_id, HALMAC indicator->status = process_status; indicator->ret_size = size; if (!indicator->sctx) { - RTW_INFO("%s: No feature id(%d) waiting!!\n", __FUNCTION__, feature_id); + RTW_WARN("%s: No feature id(%d, %s) waiting!!\n", __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]); goto exit; } sctx = indicator->sctx; if (HALMAC_CMD_PROCESS_ERROR == process_status) { - RTW_INFO("%s: Something wrong id(%d)!!\n", __FUNCTION__, feature_id); + RTW_ERR("%s: Something wrong id(%d, %s)!!\n", __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]); rtw_sctx_done_err(&sctx, RTW_SCTX_DONE_UNKNOWN); goto exit; } if (size > indicator->buf_size) { - RTW_INFO("%s: id(%d) buffer is not enough(%d<%d), data will be truncated!\n", - __FUNCTION__, feature_id, indicator->buf_size, size); + RTW_WARN("%s: id(%d, %s) buffer is not enough(%d<%d), data will be truncated!\n", + __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id], indicator->buf_size, size); cpsz = indicator->buf_size; - } else + } else { cpsz = size; + } if (cpsz && indicator->buffer) _rtw_memcpy(indicator->buffer, buf, cpsz); @@ -576,10 +653,12 @@ HALMAC_PLATFORM_API rtw_halmac_platform_api = { .SDIO_CMD53_READ_8 = _halmac_sdio_reg_read_8, .SDIO_CMD53_READ_16 = _halmac_sdio_reg_read_16, .SDIO_CMD53_READ_32 = _halmac_sdio_reg_read_32, + .SDIO_CMD53_READ_N = _halmac_sdio_reg_read_n, .SDIO_CMD52_WRITE = _halmac_sdio_cmd52_write, .SDIO_CMD53_WRITE_8 = _halmac_sdio_reg_write_8, .SDIO_CMD53_WRITE_16 = _halmac_sdio_reg_write_16, .SDIO_CMD53_WRITE_32 = _halmac_sdio_reg_write_32, + #endif /* CONFIG_SDIO_HCI */ #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCIE_HCI) .REG_READ_8 = _halmac_reg_read_8, @@ -612,6 +691,7 @@ HALMAC_PLATFORM_API rtw_halmac_platform_api = { .MUTEX_UNLOCK = _halmac_mutex_unlock, .MSG_PRINT = _halmac_msg_print, + .BUFF_PRINT = _halmac_buff_print, .EVENT_INDICATION = _halmac_event_indication, }; @@ -654,6 +734,66 @@ u32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr) return api->halmac_reg_read_32(mac, addr); } +void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem) +{ +#if defined(CONFIG_SDIO_HCI) + PHALMAC_ADAPTER mac; + PHALMAC_API api; + + if (pmem == NULL) { + RTW_ERR("pmem is NULL\n"); + return; + } + /* WARNING: pintf_dev should not be null! */ + mac = dvobj_to_halmac(pintfhdl->pintf_dev); + api = HALMAC_GET_API(mac); + + api->halmac_reg_sdio_cmd53_read_n(mac, addr, cnt, pmem); +#endif +} + +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + + /* WARNING: pintf_dev should not be null! */ + mac = dvobj_to_halmac(pintfhdl->pintf_dev); + api = HALMAC_GET_API(mac); + + /*return api->halmac_reg_read_indirect_8(mac, addr);*/ + return api->halmac_reg_read_8(mac, addr); +} + +u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + u16 val16 = 0; + + /* WARNING: pintf_dev should not be null! */ + mac = dvobj_to_halmac(pintfhdl->pintf_dev); + api = HALMAC_GET_API(mac); + + /*return api->halmac_reg_read_indirect_16(mac, addr);*/ + return api->halmac_reg_read_16(mac, addr); +} + +u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + + + /* WARNING: pintf_dev should not be null! */ + mac = dvobj_to_halmac(pintfhdl->pintf_dev); + api = HALMAC_GET_API(mac); + + return api->halmac_reg_read_indirect_32(mac, addr); +} +#endif + int rtw_halmac_write8(struct intf_hdl *pintfhdl, u32 addr, u8 value) { PHALMAC_ADAPTER mac; @@ -717,9 +857,8 @@ static int init_priv(struct halmacpriv *priv) u32 count, size; - size = sizeof(*priv); - _rtw_memset(priv, 0, size); - + if (priv->indicator) + RTW_WARN("%s: HALMAC private data is not CLEAR!\n", __FUNCTION__); count = HALMAC_FEATURE_ALL + 1; size = sizeof(*indicator) * count; indicator = (struct halmac_indicator *)rtw_zmalloc(size); @@ -750,7 +889,7 @@ static void deinit_priv(struct halmacpriv *priv) if (!indicator[i].sctx) continue; - RTW_INFO("%s: %s id(%d) sctx still exist!!\n", + RTW_WARN("%s: %s id(%d) sctx still exist!!\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[i], i); sctx = indicator[i].sctx; indicator[i].sctx = NULL; @@ -763,6 +902,35 @@ static void deinit_priv(struct halmacpriv *priv) } } +#ifdef CONFIG_SDIO_HCI +static enum _HALMAC_SDIO_SPEC_VER _sdio_ver_drv2halmac(struct dvobj_priv *d) +{ + bool v3; + enum _HALMAC_SDIO_SPEC_VER ver; + + + v3 = rtw_is_sdio30(dvobj_get_primary_adapter(d)); + if (v3) + ver = HALMAC_SDIO_SPEC_VER_3_00; + else + ver = HALMAC_SDIO_SPEC_VER_2_00; + + return ver; +} +#endif /* CONFIG_SDIO_HCI */ + +void rtw_dump_halmac_info(void *sel) +{ + HALMAC_RET_STATUS status; + HALMAC_VER halmac_version; + + status = halmac_get_version(&halmac_version); + if (status != HALMAC_RET_SUCCESS) + return; + + RTW_PRINT_SEL(sel, "HALMAC VER -%x.%x.%x\n", halmac_version.major_ver, halmac_version.prototype_ver, halmac_version.minor_ver); +} + int rtw_halmac_init_adapter(struct dvobj_priv *d, PHALMAC_PLATFORM_API pf_api) { PHALMAC_ADAPTER halmac; @@ -770,6 +938,9 @@ int rtw_halmac_init_adapter(struct dvobj_priv *d, PHALMAC_PLATFORM_API pf_api) HALMAC_INTERFACE intf; HALMAC_RET_STATUS status; int err = 0; +#ifdef CONFIG_SDIO_HCI + HALMAC_SDIO_HW_INFO info; +#endif /* CONFIG_SDIO_HCI */ halmac = dvobj_to_halmac(d); @@ -794,13 +965,40 @@ int rtw_halmac_init_adapter(struct dvobj_priv *d, PHALMAC_PLATFORM_API pf_api) #endif status = halmac_init_adapter(d, pf_api, intf, &halmac, &api); if (HALMAC_RET_SUCCESS != status) { - RTW_INFO("%s: halmac_init_adapter fail!(status=%d)\n", __FUNCTION__, status); + RTW_ERR("%s: halmac_init_adapter fail!(status=%d)\n", __FUNCTION__, status); err = -1; goto out; } dvobj_set_halmac(d, halmac); + status = api->halmac_interface_integration_tuning(halmac); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: halmac_interface_integration_tuning fail!(status=%d)\n", __FUNCTION__, status); + err = -1; + goto out; + } + + status = api->halmac_phy_cfg(halmac, HALMAC_INTF_PHY_PLATFORM_ALL); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: halmac_phy_cfg fail!(status=%d)\n", __FUNCTION__, status); + err = -1; + goto out; + } + +#ifdef CONFIG_SDIO_HCI + info.spec_ver = _sdio_ver_drv2halmac(d); + /* clock unit is MHz */ + info.clock_speed = RTW_DIV_ROUND_UP(rtw_sdio_get_clock(d), 1000000); + RTW_DBG("%s: SDIO clock=%uMHz ver=%u\n", __FUNCTION__, info.clock_speed, info.spec_ver+2); + status = api->halmac_sdio_hw_info(halmac, &info); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: halmac_sdio_hw_info fail!(status=%d)\n", __FUNCTION__, status); + err = -1; + goto out; + } +#endif /* CONFIG_SDIO_HCI */ + out: if (err) rtw_halmac_deinit_adapter(d); @@ -834,6 +1032,17 @@ int rtw_halmac_deinit_adapter(struct dvobj_priv *d) return err; } +/* + * Description: + * Power on device hardware. + * [Notice!] If device's power state is on before, + * it would be power off first and turn on power again. + * + * Return: + * 0 power on success + * -1 power on fail + * -2 power state unchange + */ int rtw_halmac_poweron(struct dvobj_priv *d) { PHALMAC_ADAPTER halmac; @@ -852,9 +1061,28 @@ int rtw_halmac_poweron(struct dvobj_priv *d) if (status != HALMAC_RET_SUCCESS) goto out; - status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON); +#ifdef CONFIG_SDIO_HCI + status = api->halmac_sdio_cmd53_4byte(halmac, HALMAC_SDIO_CMD53_4BYTE_MODE_RW); if (status != HALMAC_RET_SUCCESS) goto out; +#endif /* CONFIG_SDIO_HCI */ + + status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON); + if (HALMAC_RET_PWR_UNCHANGE == status) { + /* + * Work around for warm reboot but device not power off, + * but it would also fall into this case when auto power on is enabled. + */ + api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF); + status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON); + RTW_WARN("%s: Power state abnormal, try to recover...%s\n", + __FUNCTION__, (HALMAC_RET_SUCCESS == status)?"OK":"FAIL!"); + } + if (HALMAC_RET_SUCCESS != status) { + if (HALMAC_RET_PWR_UNCHANGE == status) + err = -2; + goto out; + } status = api->halmac_init_system_cfg(halmac); if (status != HALMAC_RET_SUCCESS) @@ -865,6 +1093,14 @@ int rtw_halmac_poweron(struct dvobj_priv *d) return err; } +/* + * Description: + * Power off device hardware. + * + * Return: + * 0 Power off success + * -1 Power off fail + */ int rtw_halmac_poweroff(struct dvobj_priv *d) { PHALMAC_ADAPTER halmac; @@ -880,7 +1116,8 @@ int rtw_halmac_poweroff(struct dvobj_priv *d) api = HALMAC_GET_API(halmac); status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF); - if (status != HALMAC_RET_SUCCESS) + if ((HALMAC_RET_SUCCESS != status) + && (HALMAC_RET_PWR_UNCHANGE != status)) goto out; err = 0; @@ -912,55 +1149,72 @@ int rtw_halmac_config_rx_info(struct dvobj_priv *d, HALMAC_DRV_INFO info) return err; } -static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d) +#ifdef CONFIG_SUPPORT_TRX_SHARED +static inline HALMAC_RX_FIFO_EXPANDING_MODE _trx_share_mode_drv2halmac(u8 trx_share_mode) { - PADAPTER p; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_WLAN_ADDR hwa; - HALMAC_RET_STATUS status; - u8 wifi_test = 0; - u8 nettype; - int err; + if (0 == trx_share_mode) + return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE; + else if (1 == trx_share_mode) + return HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK; + else if (2 == trx_share_mode) + return HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK; + else if (3 == trx_share_mode) + return HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK; + else + return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE; +} +static HALMAC_RX_FIFO_EXPANDING_MODE _rtw_get_trx_share_mode(_adapter *adapter) +{ + struct registry_priv *registry_par = &adapter->registrypriv; + return _trx_share_mode_drv2halmac(registry_par->trx_share_mode); +} +void dump_trx_share_mode(void *sel, _adapter *adapter) +{ + struct registry_priv *registry_par = &adapter->registrypriv; + u8 mode = _trx_share_mode_drv2halmac(registry_par->trx_share_mode); - p = d->padapters[IFACE_ID0]; - halmac = dvobj_to_halmac(d); - api = HALMAC_GET_API(halmac); - if (p->registrypriv.wifi_spec) - wifi_test = 1; + if (HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK == mode) + RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_1"); + else if (HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK == mode) + RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_2"); + else if (HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK == mode) + RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_3"); + else + RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "DISABLE"); +} +#endif -#ifdef CONFIG_USB_HCI - status = api->halmac_set_bulkout_num(halmac, d->RtNumOutPipes); - if (status != HALMAC_RET_SUCCESS) - goto out; -#endif /* CONFIG_USB_HCI */ +static u8 _get_drv_rsvd_page(HALMAC_DRV_RSVD_PG_NUM rsvd_page_number) +{ + if (HALMAC_RSVD_PG_NUM16 == rsvd_page_number) + return 16; + else if (HALMAC_RSVD_PG_NUM24 == rsvd_page_number) + return 24; + else if (HALMAC_RSVD_PG_NUM32 == rsvd_page_number) + return 32; - if (wifi_test) - status = api->halmac_init_mac_cfg(halmac, HALMAC_TRX_MODE_WMM); - else - status = api->halmac_init_mac_cfg(halmac, HALMAC_TRX_MODE_NORMAL); - if (status != HALMAC_RET_SUCCESS) - goto out; + RTW_ERR("%s unknown HALMAC_RSVD_PG type :%d\n", __func__, rsvd_page_number); + rtw_warn_on(1); + return 0; +} - err = rtw_halmac_rx_agg_switch(d, _TRUE); - if (err) - goto out; +static HALMAC_TRX_MODE _choose_trx_mode(struct dvobj_priv *d) +{ + PADAPTER p; - nettype = dvobj_to_regsty(d)->wireless_mode; - if (IsSupportedVHT(nettype) == _TRUE) - status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_AC); - else if (IsSupportedHT(nettype) == _TRUE) - status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_N); - else if (IsSupportedTxOFDM(nettype) == _TRUE) - status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_G); - else - status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_B); - if (status != HALMAC_RET_SUCCESS) - goto out; -out: - return status; + p = dvobj_get_primary_adapter(d); + + if (p->registrypriv.wifi_spec) + return HALMAC_TRX_MODE_WMM; + +#ifdef CONFIG_SUPPORT_TRX_SHARED + if (_rtw_get_trx_share_mode(p)) + return HALMAC_TRX_MODE_TRXSHARE; +#endif + + return HALMAC_TRX_MODE_NORMAL; } static inline HALMAC_RF_TYPE _rf_type_drv2halmac(RT_RF_TYPE_DEF_E rf_drv) @@ -1015,7 +1269,7 @@ static int _send_general_info(struct dvobj_priv *d) u8 val8; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); hal = GET_HAL_DATA(adapter); halmac = dvobj_to_halmac(d); if (!halmac) @@ -1023,7 +1277,7 @@ static int _send_general_info(struct dvobj_priv *d) api = HALMAC_GET_API(halmac); _rtw_memset(&info, 0, sizeof(info)); - info.rfe_type = (u8)hal->RFEType; + info.rfe_type = (u8)hal->rfe_type; rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &val8); info.rf_type = _rf_type_drv2halmac(val8); @@ -1043,28 +1297,181 @@ static int _send_general_info(struct dvobj_priv *d) } /* - * Notices: - * Make sure - * 1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE) - * 2. HAL_DATA_TYPE.rfe_type - * already ready for use before calling this function. + * Description: + * Downlaod Firmware Flow + * + * Parameters: + * d pointer of struct dvobj_priv + * fw firmware array + * fwsize firmware size + * re_dl re-download firmware or not + * 0: run in init hal flow, not re-download + * 1: it is a stand alone operation, not in init hal flow + * + * Return: + * 0 Success + * others Fail */ -static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize) +static int download_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize, u8 re_dl) { - PADAPTER adapter; - PHALMAC_ADAPTER halmac; + PHALMAC_ADAPTER mac; PHALMAC_API api; HALMAC_RET_STATUS status; - u32 ok = _TRUE; - u8 fw_ok = _FALSE; - int err, err_ret = -1; + int err = 0; + PHAL_DATA_TYPE hal; + HALMAC_FW_VERSION fw_vesion; - adapter = d->padapters[IFACE_ID0]; - halmac = dvobj_to_halmac(d); - if (!halmac) - goto out; - api = HALMAC_GET_API(halmac); + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + hal = GET_HAL_DATA(dvobj_get_primary_adapter(d)); + + if ((!fw) || (!fwsize)) + return -1; + + /* 1. Driver Stop Tx */ + /* ToDo */ + + /* 2. Driver Check Tx FIFO is empty */ + /* ToDo */ + + /* 3. Config MAX download size */ +#ifdef CONFIG_USB_HCI + /* for USB do not exceed MAX_CMDBUF_SZ */ + api->halmac_cfg_max_dl_size(mac, 0x1000); +#elif defined CONFIG_PCIE_HCI + /* required a even length from u32 */ + api->halmac_cfg_max_dl_size(mac, (MAX_CMDBUF_SZ - TXDESC_OFFSET) & 0xFFFFFFFE); +#endif + + /* 4. Download Firmware */ + status = api->halmac_download_firmware(mac, fw, fwsize); + if (HALMAC_RET_SUCCESS != status) + return -1; + + /* 5. Driver resume TX if needed */ + /* ToDo */ + + if (re_dl) { + HALMAC_TRX_MODE mode; + + /* 6. Init TRX Configuration */ + mode = _choose_trx_mode(d); + status = api->halmac_init_trx_cfg(mac, mode); + if (HALMAC_RET_SUCCESS != status) + return -1; + + /* 7. Config RX Aggregation */ + err = rtw_halmac_rx_agg_switch(d, _TRUE); + if (err) + return -1; + + /* 8. Send General Info */ + err = _send_general_info(d); + if (err) + return -1; + } + + /* 9. Reset driver variables if needed */ + hal->LastHMEBoxNum = 0; + + /* 10. Get FW version */ + status = api->halmac_get_fw_version(mac, &fw_vesion); + if (status == HALMAC_RET_SUCCESS) { + hal->firmware_version = fw_vesion.version; + hal->firmware_sub_version = fw_vesion.sub_version; + hal->firmware_size = fwsize; + } + + return err; +} + +static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d) +{ + PADAPTER p; + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + HALMAC_WLAN_ADDR hwa; + HALMAC_TRX_MODE trx_mode; + HALMAC_RET_STATUS status; + u8 nettype; + int err; + PHAL_DATA_TYPE hal; + HALMAC_DRV_RSVD_PG_NUM rsvd_page_number = HALMAC_RSVD_PG_NUM16;/*HALMAC_RSVD_PG_NUM24/HALMAC_RSVD_PG_NUM32*/ + + p = dvobj_get_primary_adapter(d); + hal = GET_HAL_DATA(p); + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + +#ifdef CONFIG_SUPPORT_TRX_SHARED + status = api->halmac_cfg_rx_fifo_expanding_mode(halmac, _rtw_get_trx_share_mode(p)); + if (status != HALMAC_RET_SUCCESS) + goto out; +#endif + +#ifdef CONFIG_PNO_SUPPORT + rsvd_page_number = HALMAC_RSVD_PG_NUM32; +#endif + status = api->halmac_cfg_drv_rsvd_pg_num(halmac, rsvd_page_number); + if (status != HALMAC_RET_SUCCESS) + goto out; + hal->drv_rsvd_page_number = _get_drv_rsvd_page(rsvd_page_number); + +#ifdef CONFIG_USB_HCI + status = api->halmac_set_bulkout_num(halmac, d->RtNumOutPipes); + if (status != HALMAC_RET_SUCCESS) + goto out; +#endif /* CONFIG_USB_HCI */ + + trx_mode = _choose_trx_mode(d); + status = api->halmac_init_mac_cfg(halmac, trx_mode); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = rtw_halmac_rx_agg_switch(d, _TRUE); + if (err) + goto out; + + nettype = dvobj_to_regsty(d)->wireless_mode; + if (is_supported_vht(nettype) == _TRUE) + status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_AC); + else if (is_supported_ht(nettype) == _TRUE) + status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_N); + else if (IsSupportedTxOFDM(nettype) == _TRUE) + status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_G); + else + status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_B); + if (status != HALMAC_RET_SUCCESS) + goto out; + +out: + return status; +} + +/* + * Notices: + * Make sure + * 1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE) + * 2. HAL_DATA_TYPE.rfe_type + * already ready for use before calling this function. + */ +static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize) +{ + PADAPTER adapter; + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + u32 ok = _TRUE; + u8 fw_ok = _FALSE; + int err, err_ret = -1; + + + adapter = dvobj_get_primary_adapter(d); + halmac = dvobj_to_halmac(d); + if (!halmac) + goto out; + api = HALMAC_GET_API(halmac); /* StatePowerOff */ @@ -1074,15 +1481,14 @@ static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize) /* halmac_mac_power_switch(on) */ /* halmac_Init_system_cfg */ ok = rtw_hal_power_on(adapter); - if (_FALSE == ok) + if (_FAIL == ok) goto out; /* StatePowerOn */ /* DownloadFW */ - d->hmpriv.send_general_info = 0; if (fw && fwsize) { - err = rtw_halmac_dlfw(d, fw, fwsize); + err = download_fw(d, fw, fwsize, 0); if (err) goto out; fw_ok = _TRUE; @@ -1095,12 +1501,10 @@ static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize) /* halmac_send_general_info */ if (_TRUE == fw_ok) { - d->hmpriv.send_general_info = 0; err = _send_general_info(d); if (err) goto out; - } else - d->hmpriv.send_general_info = 1; + } /* Init Phy parameter-MAC */ ok = rtw_hal_init_mac_register(adapter); @@ -1194,7 +1598,7 @@ int rtw_halmac_deinit_hal(struct dvobj_priv *d) int err = -1; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); halmac = dvobj_to_halmac(d); if (!halmac) goto out; @@ -1235,19 +1639,44 @@ int rtw_halmac_self_verify(struct dvobj_priv *d) return err; } -int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize) +u8 rtw_halmac_txfifo_is_empty(struct dvobj_priv *d) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + u8 rst = _TRUE; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + if (HALMAC_RET_TXFIFO_NO_EMPTY == api->halmac_txfifo_is_empty(mac, 10)) + rst = _FALSE; + + return rst; +} + +static HALMAC_DLFW_MEM _get_halmac_fw_mem(enum fw_mem mem) +{ + if (FW_EMEM == mem) + return HALMAC_DLFW_MEM_EMEM; + else if (FW_IMEM == mem) + return HALMAC_DLFW_MEM_UNDEFINE; + else if (FW_DMEM == mem) + return HALMAC_DLFW_MEM_UNDEFINE; + else + return HALMAC_DLFW_MEM_UNDEFINE; +} + +#define DBG_DL_FW_MEM +int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem) { PHALMAC_ADAPTER mac; PHALMAC_API api; HALMAC_RET_STATUS status; int err = 0; - PHAL_DATA_TYPE hal; - HALMAC_FW_VERSION fw_vesion; - + u8 chk_cnt = 0; + bool txfifo_empty = _FALSE; mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - hal = GET_HAL_DATA(d->padapters[IFACE_ID0]); if ((!fw) || (!fwsize)) return -1; @@ -1256,42 +1685,115 @@ int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize) /* ToDo */ /* 2. Driver Check Tx FIFO is empty */ + do { + txfifo_empty = rtw_halmac_txfifo_is_empty(d); + chk_cnt++; + #ifdef DBG_DL_FW_MEM + RTW_INFO("polling txfifo empty chk_cnt:%d\n", chk_cnt); + #endif + rtw_msleep_os(2); + } while ((!txfifo_empty) && (chk_cnt < 100)); + + if (_FALSE == txfifo_empty) { + #ifdef DBG_DL_FW_MEM + { + PADAPTER adapter = dvobj_get_primary_adapter(d); + + RTW_ERR("%s => polling txfifo empty failed\n", __func__); + RTW_ERR("REG_210:0x%08x\n", rtw_read32(adapter, 0x210)); + RTW_ERR("REG_230:0x%08x\n", rtw_read32(adapter, 0x230)); + RTW_ERR("REG_234:0x%08x\n", rtw_read32(adapter, 0x234)); + RTW_ERR("REG_238:0x%08x\n", rtw_read32(adapter, 0x238)); + RTW_ERR("REG_23C:0x%08x\n", rtw_read32(adapter, 0x23C)); + RTW_ERR("REG_240:0x%08x\n", rtw_read32(adapter, 0x240)); + } + #endif + return -1; + } + + /* 3. Download Firmware MEM */ + status = api->halmac_free_download_firmware(mac, _get_halmac_fw_mem(mem), fw, fwsize); + if (HALMAC_RET_SUCCESS != status) { + #ifdef DBG_DL_FW_MEM + RTW_ERR("%s => halmac_free_download_firmware failed\n", __func__); + #endif + return -1; + } + /* 4. Driver resume TX if needed */ /* ToDo */ - /* 3. Config MAX download size */ -#ifdef CONFIG_USB_HCI - /* for USB do not exceed MAX_CMDBUF_SZ */ - api->halmac_cfg_max_dl_size(mac, 0x1000); -#elif defined CONFIG_PCIE_HCI - /* required a even length from u32 */ - api->halmac_cfg_max_dl_size(mac, (MAX_CMDBUF_SZ - TXDESC_OFFSET) & 0xFFFFFFFE); -#endif + return err; +} - /* 4. Download Firmware */ - status = api->halmac_download_firmware(mac, fw, fwsize); - if (HALMAC_RET_SUCCESS != status) +int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem) +{ + u8 *fw = NULL; + u32 fwmaxsize, size = 0; + int err = 0; + + fwmaxsize = FIRMWARE_MAX_SIZE; + fw = rtw_zmalloc(fwmaxsize); + if (!fw) return -1; - if (d->hmpriv.send_general_info) { - d->hmpriv.send_general_info = 0; - err = _send_general_info(d); - } + size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize); + if (size) + err = rtw_halmac_dlfw_mem(d, fw, size, mem); + else + err = -1; - /* 5. Driver resume TX if needed */ - /* ToDo */ + rtw_mfree(fw, fwmaxsize); + fw = NULL; - /* 6. Reset driver variables if needed */ - hal->LastHMEBoxNum = 0; + return err; +} +/* + * Return: + * 0 Success + * -22 Invalid arguemnt + */ +int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize) +{ + PADAPTER adapter; + HALMAC_RET_STATUS status; + u32 ok = _TRUE; + int err, err_ret = -1; - /* 7. Get FW version */ - status = api->halmac_get_fw_version(mac, &fw_vesion); - if (status == HALMAC_RET_SUCCESS) { - hal->FirmwareVersion = fw_vesion.version; - hal->FirmwareSubVersion = fw_vesion.sub_version; + + if (!fw || !fwsize) + return -22; + + adapter = dvobj_get_primary_adapter(d); + + /* re-download firmware */ + if (rtw_is_hw_init_completed(adapter)) + return download_fw(d, fw, fwsize, 1); + + /* Download firmware before hal init */ + /* Power on, download firmware and init mac */ + ok = rtw_hal_power_on(adapter); + if (_FAIL == ok) + goto out; + + err = download_fw(d, fw, fwsize, 0); + if (err) { + err_ret = err; + goto out; } - return err; + status = init_mac_flow(d); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = _send_general_info(d); + if (err) + goto out; + + err_ret = 0; + +out: + return err_ret; } int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath) @@ -1337,7 +1839,7 @@ int rtw_halmac_phy_power_switch(struct dvobj_priv *d, u8 enable) HALMAC_RET_STATUS status; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); halmac = dvobj_to_halmac(d); if (!halmac) return -1; @@ -1356,8 +1858,6 @@ static u8 _is_fw_read_cmd_down(PADAPTER adapter, u8 msgbox_num) int retry_cnts = 100; u8 valid; - /* RTW_INFO("_is_fw_read_cmd_down, reg_1cc(%x), msg_box(%d)...\n", rtw_read8(adapter, REG_HMETFR), msgbox_num); */ - do { valid = rtw_read8(adapter, REG_HMETFR) & BIT(msgbox_num); if (0 == valid) @@ -1366,52 +1866,64 @@ static u8 _is_fw_read_cmd_down(PADAPTER adapter, u8 msgbox_num) rtw_msleep_os(1); } while ((!read_down) && (retry_cnts--)); + if (_FALSE == read_down) + RTW_WARN("%s, reg_1cc(%x), msg_box(%d)...\n", __func__, rtw_read8(adapter, REG_HMETFR), msgbox_num); + return read_down; } +/** + * rtw_halmac_send_h2c() - Send H2C to firmware + * @d: struct dvobj_priv* + * @h2c: H2C data buffer, suppose to be 8 bytes + * + * Send H2C to firmware by message box register(0x1D0~0x1D3 & 0x1F0~0x1F3). + * + * Return: 0 if process OK, otherwise fail to send this H2C. + */ int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c) { - PADAPTER adapter = d->padapters[IFACE_ID0]; + PADAPTER adapter = dvobj_get_primary_adapter(d); PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); u8 h2c_box_num = 0; u32 msgbox_addr = 0; u32 msgbox_ex_addr = 0; u32 h2c_cmd = 0; u32 h2c_cmd_ex = 0; - s32 ret = _FAIL; + int err = -1; - if (adapter->bFWReady == _FALSE) { - RTW_INFO("%s: return H2C cmd because fw is not ready\n", __FUNCTION__); - return ret; + if (hal->bFWReady == _FALSE) { + RTW_WARN("%s: return H2C cmd because fw is not ready\n", __FUNCTION__); + return err; } if (!h2c) { - RTW_INFO("%s: pbuf is NULL\n", __FUNCTION__); - return ret; + RTW_WARN("%s: pbuf is NULL\n", __FUNCTION__); + return err; } if (rtw_is_surprise_removed(adapter)) { - RTW_INFO("%s: surprise removed\n", __FUNCTION__); - return ret; + RTW_WARN("%s: surprise removed\n", __FUNCTION__); + return err; } _enter_critical_mutex(&d->h2c_fwcmd_mutex, NULL); - /* pay attention to if race condition happened in H2C cmd setting */ + /* pay attention to if race condition happened in H2C cmd setting */ h2c_box_num = hal->LastHMEBoxNum; if (!_is_fw_read_cmd_down(adapter, h2c_box_num)) { - RTW_INFO(" fw read cmd failed...\n"); + RTW_WARN(" fw read cmd failed...\n"); goto exit; } - /* Write Ext command(byte 4 -7) */ + /* Write Ext command (byte 4~7) */ msgbox_ex_addr = REG_HMEBOX_E0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE); _rtw_memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, EX_MESSAGE_BOX_SIZE); h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex); rtw_write32(adapter, msgbox_ex_addr, h2c_cmd_ex); - /* Write command (byte 0 -3 ) */ + /* Write command (byte 0~3) */ msgbox_addr = REG_HMEBOX0 + (h2c_box_num * MESSAGE_BOX_SIZE); _rtw_memcpy((u8 *)(&h2c_cmd), h2c, 4); h2c_cmd = le32_to_cpu(h2c_cmd); @@ -1419,13 +1931,31 @@ int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c) /* update last msg box number */ hal->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS; - ret = _SUCCESS; + err = 0; +#ifdef DBG_H2C_CONTENT + RTW_INFO_DUMP("[H2C] - ", h2c, RTW_HALMAC_H2C_MAX_SIZE); +#endif exit: _exit_critical_mutex(&d->h2c_fwcmd_mutex, NULL); - return ret; + return err; } +/** + * rtw_halmac_c2h_handle() - Handle C2H for HALMAC + * @d: struct dvobj_priv* + * @c2h: Full C2H packet, including RX description and payload + * @size: Size(byte) of c2h + * + * Send C2H packet to HALMAC to process C2H packets, and the expected C2H ID is + * 0xFF. This function won't have any I/O, so caller doesn't have to call it in + * I/O safe place(ex. command thread). + * + * Please sure doesn't call this function in the same thread as someone is + * waiting HALMAC C2H ack, otherwise there is a deadlock happen. + * + * Return: 0 if process OK, otherwise no action for this C2H. + */ int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size) { PHALMAC_ADAPTER mac; @@ -1443,6 +1973,25 @@ int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size) return 0; } +int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + u32 val; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_get_efuse_available_size(mac, &val); + if (HALMAC_RET_SUCCESS != status) + return -1; + + *size = val; + return 0; +} + int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size) { PHALMAC_ADAPTER mac; @@ -1479,7 +2028,7 @@ int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) if (ret) return -1; - status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_AUTO); + status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_DRV); if (HALMAC_RET_SUCCESS != status) { free_halmac_event(d, id); return -1; @@ -1499,19 +2048,40 @@ int rtw_halmac_read_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 HALMAC_RET_STATUS status; u8 v; u32 i; + u8 *efuse = NULL; + u32 size = 0; + int err = 0; mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - for (i = 0; i < cnt; i++) { - status = api->halmac_read_efuse(mac, offset + i, &v); - if (HALMAC_RET_SUCCESS != status) + if (api->halmac_read_efuse) { + for (i = 0; i < cnt; i++) { + status = api->halmac_read_efuse(mac, offset + i, &v); + if (HALMAC_RET_SUCCESS != status) + return -1; + data[i] = v; + } + } else { + err = rtw_halmac_get_physical_efuse_size(d, &size); + if (err) return -1; - data[i] = v; + + efuse = rtw_zmalloc(size); + if (!efuse) + return -1; + + err = rtw_halmac_read_physical_efuse_map(d, efuse, size); + if (err) + err = -1; + else + _rtw_memcpy(data, efuse + offset, cnt); + + rtw_mfree(efuse, size); } - return 0; + return err; } int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) @@ -1525,6 +2095,9 @@ int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); + if (api->halmac_write_efuse == NULL) + return -1; + for (i = 0; i < cnt; i++) { status = api->halmac_write_efuse(mac, offset + i, data[i]); if (HALMAC_RET_SUCCESS != status) @@ -1570,7 +2143,7 @@ int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) if (ret) return -1; - status = api->halmac_dump_logical_efuse_map(mac, HALMAC_EFUSE_R_AUTO); + status = api->halmac_dump_logical_efuse_map(mac, HALMAC_EFUSE_R_DRV); if (HALMAC_RET_SUCCESS != status) { free_halmac_event(d, id); return -1; @@ -1684,7 +2257,7 @@ int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 siz api = HALMAC_GET_API(mac); status = api->halmac_dump_efuse_map_bt(mac, bank, size, map); - if (HALMAC_RET_SUCCESS != status) { + if (HALMAC_RET_SUCCESS != status) { printk("%s: halmac_dump_efuse_map_bt fail!\n", __FUNCTION__); return -1; } @@ -1790,6 +2363,56 @@ int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 return 0; } +/** + * rtw_halmac_set_edca() - config edca parameter + * @d: struct dvobj_priv* + * @queue: XMIT_[VO/VI/BE/BK]_QUEUE + * @aifs: Arbitration inter-frame space(AIFS) + * @cw: Contention window(CW) + * @txop: MAX Transmit Opportunity(TXOP) + * + * Return: 0 if process OK, otherwise -1. + */ +int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_ACQ_ID ac; + HALMAC_EDCA_PARA edca; + HALMAC_RET_STATUS status; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + switch (queue) { + case XMIT_VO_QUEUE: + ac = HALMAC_ACQ_ID_VO; + break; + case XMIT_VI_QUEUE: + ac = HALMAC_ACQ_ID_VI; + break; + case XMIT_BE_QUEUE: + ac = HALMAC_ACQ_ID_BE; + break; + case XMIT_BK_QUEUE: + ac = HALMAC_ACQ_ID_BK; + break; + default: + return -1; + } + + edca.aifs = aifs; + edca.cw = cw; + edca.txop_limit = txop; + + status = api->halmac_cfg_edca_para(mac, ac, &edca); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + int rtw_halmac_get_hw_value(struct dvobj_priv *d, HALMAC_HW_ID hw_id, VOID *pvalue) { PHALMAC_ADAPTER mac; @@ -1807,35 +2430,83 @@ int rtw_halmac_get_hw_value(struct dvobj_priv *d, HALMAC_HW_ID hw_id, VOID *pval return 0; } -int rtw_halmac_dump_fifo(struct dvobj_priv *d, HAL_FIFO_SEL halmac_fifo_sel) +static enum _HAL_FIFO_SEL _fifo_sel_drv2halmac(u8 fifo_sel) +{ + switch (fifo_sel) { + case 0: + return HAL_FIFO_SEL_TX; + case 1: + return HAL_FIFO_SEL_RX; + case 2: + return HAL_FIFO_SEL_RSVD_PAGE; + case 3: + return HAL_FIFO_SEL_REPORT; + case 4: + return HAL_FIFO_SEL_LLT; + case 5: + return HAL_FIFO_SEL_RXBUF_FW; + } + + return HAL_FIFO_SEL_RSVD_PAGE; +} + +/*#define CONFIG_HALMAC_FIFO_DUMP*/ +int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer) { PHALMAC_ADAPTER mac; PHALMAC_API api; HALMAC_RET_STATUS status; u8 *pfifo_map = NULL; u32 fifo_size = 0; - s8 ret = 0; + s8 ret = 0;/* 0:success, -1:error */ + u8 mem_created = _FALSE; + + HAL_FIFO_SEL halmac_fifo_sel; mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - fifo_size = api->halmac_get_fifo_size(mac, halmac_fifo_sel); - if (fifo_size) - pfifo_map = rtw_vmalloc(fifo_size); - if (pfifo_map == NULL) + if ((size != 0) && (buffer == NULL)) return -1; - status = api->halmac_dump_fifo(mac, halmac_fifo_sel, pfifo_map, fifo_size); + halmac_fifo_sel = _fifo_sel_drv2halmac(fifo_sel); + + if ((size) && (buffer)) { + pfifo_map = buffer; + fifo_size = size; + } else { + fifo_size = api->halmac_get_fifo_size(mac, halmac_fifo_sel); + + if (fifo_size) + pfifo_map = rtw_zvmalloc(fifo_size); + if (pfifo_map == NULL) + return -1; + mem_created = _TRUE; + } + + status = api->halmac_dump_fifo(mac, halmac_fifo_sel, addr, fifo_size, pfifo_map); if (HALMAC_RET_SUCCESS != status) { ret = -1; goto _exit; } +#ifdef CONFIG_HALMAC_FIFO_DUMP + { + static const char * const fifo_sel_str[] = { + "TX", "RX", "RSVD_PAGE", "REPORT", "LLT", "RXBUF_FW" + }; + + RTW_INFO("%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[halmac_fifo_sel], addr, fifo_size); + RTW_INFO_DUMP("\n", pfifo_map, fifo_size); + RTW_INFO(" ==================================================\n"); + } +#endif /* CONFIG_HALMAC_FIFO_DUMP */ + _exit: - if (pfifo_map) + if ((mem_created == _TRUE) && pfifo_map) rtw_vmfree(pfifo_map, fifo_size); - return ret; + return ret; } int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable) @@ -1849,7 +2520,7 @@ int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable) int err = -1; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); hal = GET_HAL_DATA(adapter); halmac = dvobj_to_halmac(d); api = HALMAC_GET_API(halmac); @@ -1897,25 +2568,6 @@ int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable) return err; } -int rtw_halmac_get_wow_reason(struct dvobj_priv *d, u8 *reason) -{ - PADAPTER adapter; - u8 val8; - int err = -1; - - - adapter = d->padapters[IFACE_ID0]; - - val8 = rtw_read8(adapter, 0x1C7); - if (val8 == 0xEA) - goto out; - - *reason = val8; - err = 0; -out: - return err; -} - /* * Description: * Get RX driver info size. RX driver info is a small memory space between @@ -1943,17 +2595,18 @@ int rtw_halmac_get_wow_reason(struct dvobj_priv *d, u8 *reason) int rtw_halmac_get_drv_info_sz(struct dvobj_priv *d, u8 *sz) { HALMAC_RET_STATUS status; - u8 dw = 6; /* max number */ + PHALMAC_ADAPTER halmac = dvobj_to_halmac(d); + PHALMAC_API api = HALMAC_GET_API(halmac); + u8 dw = 0; -#if 0 /* TODO wait for halmac ready */ - status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_, &dw); + status = api->halmac_get_hw_value(halmac, HALMAC_HW_DRV_INFO_SIZE, &dw); if (status != HALMAC_RET_SUCCESS) return -1; -#endif *sz = dw * 8; return 0; } + int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg) { HALMAC_RET_STATUS status; @@ -1967,13 +2620,118 @@ int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg) return 0; } -int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u16 page_idx, u8 *pbuf, u8 length) +int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size) +{ + enum _HALMAC_RET_STATUS status; + struct _HALMAC_ADAPTER *halmac; + struct _HALMAC_API *api; + u8 val; + + + if (!size) + return -1; + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_OQT_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + return 0; +} + +int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num) +{ + enum _HALMAC_RET_STATUS status; + struct _HALMAC_ADAPTER *halmac; + struct _HALMAC_API *api; + u8 val; + + + if (!num) + return -1; + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_QUEUE_NUM, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *num = val; + return 0; +} + +int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size) { HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj); PHALMAC_API api = HALMAC_GET_API(halmac); - /*status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, drv_pg);*/ + status = api->halmac_dl_drv_rsvd_page(halmac, pg_offset, pbuf, size); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +/* + * Description + * Fill following spec info from HALMAC API: + * sec_cam_ent_num + * + * Return + * 0 Success + * others Fail + */ +int rtw_halmac_fill_hal_spec(struct dvobj_priv *dvobj, struct hal_spec_t *spec) +{ + HALMAC_RET_STATUS status; + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + u8 cam = 0; /* Security Cam Entry Number */ + + + halmac = dvobj_to_halmac(dvobj); + api = HALMAC_GET_API(halmac); + + /* Prepare data from HALMAC */ + status = api->halmac_get_hw_value(halmac, HALMAC_HW_CAM_ENTRY_NUM, &cam); + if (status != HALMAC_RET_SUCCESS) + return -1; + + /* Fill data to hal_spec_t */ + spec->sec_cam_ent_num = cam; + + return 0; +} + +int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para) +{ + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj); + PHALMAC_API api = HALMAC_GET_API(halmac); + HALMAC_P2PPS halmac_p2p_ps; + + (&halmac_p2p_ps)->offload_en = pp2p_ps_para->offload_en; + (&halmac_p2p_ps)->role = pp2p_ps_para->role; + (&halmac_p2p_ps)->ctwindow_en = pp2p_ps_para->ctwindow_en; + (&halmac_p2p_ps)->noa_en = pp2p_ps_para->noa_en; + (&halmac_p2p_ps)->noa_sel = pp2p_ps_para->noa_sel; + (&halmac_p2p_ps)->all_sta_sleep = pp2p_ps_para->all_sta_sleep; + (&halmac_p2p_ps)->discovery = pp2p_ps_para->discovery; + (&halmac_p2p_ps)->p2p_port_id = _hw_port_drv2halmac(pp2p_ps_para->p2p_port_id); + (&halmac_p2p_ps)->p2p_group = pp2p_ps_para->p2p_group; + (&halmac_p2p_ps)->p2p_macid = pp2p_ps_para->p2p_macid; + (&halmac_p2p_ps)->ctwindow_length = pp2p_ps_para->ctwindow_length; + (&halmac_p2p_ps)->noa_duration_para = pp2p_ps_para->noa_duration_para; + (&halmac_p2p_ps)->noa_interval_para = pp2p_ps_para->noa_interval_para; + (&halmac_p2p_ps)->noa_start_time_para = pp2p_ps_para->noa_start_time_para; + (&halmac_p2p_ps)->noa_count_para = pp2p_ps_para->noa_count_para; + + status = api->halmac_p2pps(halmac, (&halmac_p2p_ps)); if (status != HALMAC_RET_SUCCESS) return -1; @@ -1981,6 +2739,61 @@ int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u16 page_idx, u8 *pb } +/** + * rtw_halmac_iqk() - Run IQ Calibration + * @d: struct dvobj_priv* + * @clear: IQK parameters + * @segment: IQK parameters + * + * Process IQ Calibration(IQK). + * + * Rteurn: 0 for OK, otherwise fail. + */ +int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + HALMAC_FEATURE_ID id; + HALMAC_IQK_PARA para; + int ret; + u8 retry = 3; + u8 delay = 1; /* ms */ + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + id = HALMAC_FEATURE_IQK; + + ret = init_halmac_event(d, id, NULL, 0); + if (ret) + return -1; + + para.clear = clear; + para.segment_iqk = segment; + + do { + status = api->halmac_start_iqk(mac, ¶); + if (status != HALMAC_RET_BUSY_STATE) + break; + RTW_WARN("%s: Fail to start IQK, status is BUSY! retry=%d\n", __FUNCTION__, retry); + if (!retry) + break; + retry--; + rtw_msleep_os(delay); + } while (1); + if (status != HALMAC_RET_SUCCESS) { + free_halmac_event(d, id); + return -1; + } + + ret = wait_halmac_event(d, id); + if (ret) + return -1; + + return 0; +} + #ifdef CONFIG_SDIO_HCI /* @@ -2007,7 +2820,7 @@ int rtw_halmac_query_tx_page_num(struct dvobj_priv *d) u8 i; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); hmpriv = &d->hmpriv; halmac = dvobj_to_halmac(d); api = HALMAC_GET_API(halmac); @@ -2194,7 +3007,7 @@ u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode) PADAPTER adapter; HALMAC_USB_MODE halmac_usb_mode; - adapter = d->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(d); mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); halmac_usb_mode = _usb_mode_drv2halmac(usb_mode); @@ -2206,3 +3019,137 @@ u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode) return _SUCCESS; } #endif /* CONFIG_USB_HCI */ + +#ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 +int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para, + u16 my_aid, HALMAC_CSI_SEG_LEN sel, u8 *addr) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + HALMAC_MU_BFER_INIT_PARA param; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + memset(¶m, 0, sizeof(param)); + param.paid = paid; + param.csi_para = csi_para; + param.my_aid = my_aid; + param.csi_length_sel = sel; + memcpy(param.bfer_address.Address, addr, 6); + + status = api->halmac_mu_bfer_entry_init(mac, ¶m); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_mu_bfer_entry_del(mac); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + + +int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, + HALMAC_SND_ROLE role, HALMAC_DATA_RATE rate) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_cfg_sounding(mac, role, rate); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, + HALMAC_SND_ROLE role) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_del_sounding(mac, role); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, + u8 rssi, u8 current_rate, u8 fixrate_en, + u8 *new_rate) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_cfg_csi_rate(mac, + rssi, current_rate, fixrate_en, new_rate); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, HALMAC_SND_ROLE role, + u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en, + u32 *given_gid_tab, u32 *given_user_pos) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + HALMAC_CFG_MUMIMO_PARA param; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + memset(¶m, 0, sizeof(param)); + + param.role = role; + param.grouping_bitmap = grouping_bitmap; + param.mu_tx_en = mu_tx_en; + + if (sounding_sts) + memcpy(param.sounding_sts, sounding_sts, 6); + + if (given_gid_tab) + memcpy(param.given_gid_tab, given_gid_tab, 8); + + if (given_user_pos) + memcpy(param.given_user_pos, given_user_pos, 16); + + status = api->halmac_cfg_mumimo(mac, ¶m); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +#endif /* RTW_BEAMFORMING_VERSION_2 */ +#endif /* CONFIG_BEAMFORMING */ diff --git a/hal/hal_halmac.h b/hal/hal_halmac.h index c59df43..5b006f7 100644 --- a/hal/hal_halmac.h +++ b/hal/hal_halmac.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,16 +11,12 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _HAL_HALMAC_H_ #define _HAL_HALMAC_H_ #include /* adapter_to_dvobj(), struct intf_hdl and etc. */ +#include /* struct hal_spec_t */ #include "halmac/halmac_api.h" /* PHALMAC_ADAPTER and etc. */ /* HALMAC Definition for Driver */ @@ -47,10 +43,18 @@ extern HALMAC_PLATFORM_API rtw_halmac_platform_api; u8 rtw_halmac_read8(struct intf_hdl *, u32 addr); u16 rtw_halmac_read16(struct intf_hdl *, u32 addr); u32 rtw_halmac_read32(struct intf_hdl *, u32 addr); +void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr); +u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr); +u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr); +#endif int rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value); int rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value); int rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value); +void rtw_dump_halmac_info(void *sel); + int rtw_halmac_init_adapter(struct dvobj_priv *, PHALMAC_PLATFORM_API); int rtw_halmac_deinit_adapter(struct dvobj_priv *); int rtw_halmac_poweron(struct dvobj_priv *); @@ -62,9 +66,12 @@ int rtw_halmac_deinit_hal(struct dvobj_priv *); int rtw_halmac_self_verify(struct dvobj_priv *); int rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize); int rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath); +int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem); +int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem); int rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable); int rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c); int rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size); +int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size); int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size); int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); @@ -81,17 +88,25 @@ int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size int rtw_halmac_config_rx_info(struct dvobj_priv *, HALMAC_DRV_INFO); int rtw_halmac_set_mac_address(struct dvobj_priv *, enum _hw_port, u8 *addr); -int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); +int rtw_halmac_set_bssid(struct dvobj_priv *, enum _hw_port hwport, u8 *addr); int rtw_halmac_set_bandwidth(struct dvobj_priv *, u8 channel, u8 pri_ch_idx, u8 bw); -int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable); -int rtw_halmac_get_hw_value(struct dvobj_priv *d, HALMAC_HW_ID hw_id, VOID *pvalue); +int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop); +int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer); +int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable); +int rtw_halmac_get_hw_value(struct dvobj_priv *, HALMAC_HW_ID hw_id, VOID *pvalue); int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason); -int rtw_halmac_get_drv_info_sz(struct dvobj_priv *d, u8 *sz); - +int rtw_halmac_get_drv_info_sz(struct dvobj_priv *, u8 *sz); int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg); -int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u16 page_idx, u8 *pbuf, u8 length); +int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size); +int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num); + +/* Specific function APIs*/ +int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size); +int rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *); +int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para); +int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment); #ifdef CONFIG_SDIO_HCI int rtw_halmac_query_tx_page_num(struct dvobj_priv *); @@ -106,4 +121,30 @@ u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *, u8 *buf, u32 size); u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode); #endif /* CONFIG_USB_HCI */ +#ifdef CONFIG_SUPPORT_TRX_SHARED +void dump_trx_share_mode(void *sel, _adapter *adapter); +#endif + +#ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 +int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para, + u16 my_aid, HALMAC_CSI_SEG_LEN sel, u8 *addr); +int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d); + +int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, HALMAC_SND_ROLE role, + HALMAC_DATA_RATE rate); +int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, HALMAC_SND_ROLE role); + +int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate, + u8 fixrate_en, u8 *new_rate); + +int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, HALMAC_SND_ROLE role, + u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en, + u32 *given_gid_tab, u32 *given_user_pos); +#define rtw_halmac_bf_cfg_mu_bfee(d, gid_tab, user_pos) \ + rtw_halmac_bf_cfg_mu_mimo(d, HAL_BFEE, NULL, 0, 0, gid_tab, user_pos) + +#endif /* RTW_BEAMFORMING_VERSION_2 */ +#endif /* CONFIG_BEAMFORMING */ + #endif /* _HAL_HALMAC_H_ */ diff --git a/hal/hal_hci/hal_usb.c b/hal/hal_hci/hal_usb.c index 060fe9c..50b3d57 100644 --- a/hal/hal_hci/hal_usb.c +++ b/hal/hal_hci/hal_usb.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,32 +11,18 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_USB_C_ #include #include -#ifdef CONFIG_RTL8821C - #include /* MAX_RECVBUF_SZ */ -#endif /* CONFIG_RTL8821C */ - int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz) { struct recv_priv *precvpriv = &padapter->recvpriv; int i, res = _SUCCESS; struct recv_buf *precvbuf; -#ifdef CONFIG_RECV_THREAD_MODE - _rtw_init_sema(&precvpriv->recv_sema, 0);/* will be removed */ - _rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);/* will be removed */ -#endif /* CONFIG_RECV_THREAD_MODE */ - #ifdef PLATFORM_LINUX tasklet_init(&precvpriv->recv_tasklet, (void(*)(unsigned long))usb_recv_tasklet, @@ -79,7 +65,6 @@ int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz) precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF * sizeof(struct recv_buf) + 4); if (precvpriv->pallocated_recv_buf == NULL) { res = _FAIL; - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("alloc recv_buf fail!\n")); goto exit; } @@ -236,6 +221,42 @@ void usb_free_recv_priv(_adapter *padapter, u16 ini_in_buf_sz) #endif /* PLATFORM_FREEBSD */ } +#ifdef CONFIG_FW_C2H_REG +void usb_c2h_hisr_hdl(_adapter *adapter, u8 *buf) +{ + u8 *c2h_evt = buf; + u8 id, seq, plen; + u8 *payload; + + if (rtw_hal_c2h_reg_hdr_parse(adapter, buf, &id, &seq, &plen, &payload) != _SUCCESS) + return; + + if (0) + RTW_PRINT("%s C2H == %d\n", __func__, id); + + if (rtw_hal_c2h_id_handle_directly(adapter, id, seq, plen, payload)) { + /* Handle directly */ + rtw_hal_c2h_handler(adapter, id, seq, plen, payload); + + /* Replace with special pointer to trigger c2h_evt_clear only */ + if (rtw_cbuf_push(adapter->evtpriv.c2h_queue, (void*)&adapter->evtpriv) != _SUCCESS) + RTW_ERR("%s rtw_cbuf_push fail\n", __func__); + } else { + c2h_evt = rtw_malloc(C2H_REG_LEN); + if (c2h_evt != NULL) { + _rtw_memcpy(c2h_evt, buf, C2H_REG_LEN); + if (rtw_cbuf_push(adapter->evtpriv.c2h_queue, (void*)c2h_evt) != _SUCCESS) + RTW_ERR("%s rtw_cbuf_push fail\n", __func__); + } else { + /* Error handling for malloc fail */ + if (rtw_cbuf_push(adapter->evtpriv.c2h_queue, (void*)NULL) != _SUCCESS) + RTW_ERR("%s rtw_cbuf_push fail\n", __func__); + } + } + _set_workitem(&adapter->evtpriv.c2h_wk); +} +#endif + #ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ int usb_write_async(struct usb_device *udev, u32 addr, void *pdata, u16 len) { @@ -263,10 +284,8 @@ int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val) struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; struct usb_device *udev = pdvobjpriv->pusbdev; - _func_enter_; data = val; ret = usb_write_async(udev, addr, &data, 1); - _func_exit_; return ret; } @@ -278,10 +297,8 @@ int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val) struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; struct usb_device *udev = pdvobjpriv->pusbdev; - _func_enter_; data = val; ret = usb_write_async(udev, addr, &data, 2); - _func_exit_; return ret; } @@ -293,10 +310,8 @@ int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; struct usb_device *udev = pdvobjpriv->pusbdev; - _func_enter_; data = val; ret = usb_write_async(udev, addr, &data, 4); - _func_exit_; return ret; } @@ -311,7 +326,6 @@ u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr) u16 len; u8 data = 0; - _func_enter_; request = 0x05; requesttype = 0x01;/* read_in */ @@ -322,7 +336,6 @@ u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr) usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype); - _func_exit_; return data; } @@ -336,7 +349,6 @@ u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr) u16 len; u16 data = 0; - _func_enter_; request = 0x05; requesttype = 0x01;/* read_in */ @@ -347,7 +359,6 @@ u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr) usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype); - _func_exit_; return data; @@ -362,7 +373,6 @@ u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr) u16 len; u32 data = 0; - _func_enter_; request = 0x05; requesttype = 0x01;/* read_in */ @@ -373,7 +383,6 @@ u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr) usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype); - _func_exit_; return data; } @@ -388,7 +397,6 @@ int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val) u8 data; int ret; - _func_enter_; request = 0x05; requesttype = 0x00;/* write_out */ @@ -401,7 +409,6 @@ int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val) ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype); - _func_exit_; return ret; } @@ -416,7 +423,6 @@ int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val) u16 data; int ret; - _func_enter_; request = 0x05; requesttype = 0x00;/* write_out */ @@ -429,7 +435,6 @@ int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val) ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype); - _func_exit_; return ret; @@ -445,7 +450,6 @@ int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) u32 data; int ret; - _func_enter_; request = 0x05; requesttype = 0x00;/* write_out */ @@ -457,7 +461,6 @@ int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype); - _func_exit_; return ret; @@ -473,7 +476,6 @@ int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata) u8 buf[VENDOR_CMD_MAX_DATA_LEN] = {0}; int ret; - _func_enter_; request = 0x05; requesttype = 0x00;/* write_out */ @@ -485,7 +487,6 @@ int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata) ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, buf, len, requesttype); - _func_exit_; return ret; } diff --git a/hal/hal_intf.c b/hal/hal_intf.c index 99e2221..3956950 100644 --- a/hal/hal_intf.c +++ b/hal/hal_intf.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_INTF_C_ @@ -41,11 +36,20 @@ const u32 _chip_type_to_odm_ic_type[] = { void rtw_hal_chip_configure(_adapter *padapter) { - padapter->HalFunc.intf_chip_configure(padapter); + padapter->hal_func.intf_chip_configure(padapter); } -void rtw_hal_read_chip_info(_adapter *padapter) +/* + * Description: + * Read chip internal ROM data + * + * Return: + * _SUCCESS success + * _FAIL fail + */ +u8 rtw_hal_read_chip_info(_adapter *padapter) { + u8 rtn = _SUCCESS; u8 hci_type = rtw_get_intf_type(padapter); u32 start = rtw_get_current_time(); @@ -54,25 +58,27 @@ void rtw_hal_read_chip_info(_adapter *padapter) && !rtw_is_hw_init_completed(padapter)) rtw_hal_power_on(padapter); - padapter->HalFunc.read_adapter_info(padapter); + rtn = padapter->hal_func.read_adapter_info(padapter); if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI) && !rtw_is_hw_init_completed(padapter)) rtw_hal_power_off(padapter); RTW_INFO("%s in %d ms\n", __func__, rtw_get_passing_time_ms(start)); + + return rtn; } void rtw_hal_read_chip_version(_adapter *padapter) { - padapter->HalFunc.read_chip_version(padapter); + padapter->hal_func.read_chip_version(padapter); rtw_odm_init_ic_type(padapter); } void rtw_hal_def_value_init(_adapter *padapter) { if (is_primary_adapter(padapter)) { - padapter->HalFunc.init_default_value(padapter); + padapter->hal_func.init_default_value(padapter); rtw_init_hal_com_default_value(padapter); @@ -126,11 +132,11 @@ void rtw_hal_dm_init(_adapter *padapter) if (is_primary_adapter(padapter)) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - padapter->HalFunc.dm_init(padapter); + padapter->hal_func.dm_init(padapter); _rtw_spinlock_init(&pHalData->IQKSpinLock); - phy_load_tx_power_ext_info(padapter, 1, 1); + phy_load_tx_power_ext_info(padapter, 1); } } void rtw_hal_dm_deinit(_adapter *padapter) @@ -138,26 +144,35 @@ void rtw_hal_dm_deinit(_adapter *padapter) if (is_primary_adapter(padapter)) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - padapter->HalFunc.dm_deinit(padapter); + padapter->hal_func.dm_deinit(padapter); _rtw_spinlock_free(&pHalData->IQKSpinLock); } } void rtw_hal_sw_led_init(_adapter *padapter) { - if (padapter->HalFunc.InitSwLeds) - padapter->HalFunc.InitSwLeds(padapter); + if (padapter->hal_func.InitSwLeds) + padapter->hal_func.InitSwLeds(padapter); } void rtw_hal_sw_led_deinit(_adapter *padapter) { - if (padapter->HalFunc.DeInitSwLeds) - padapter->HalFunc.DeInitSwLeds(padapter); + if (padapter->hal_func.DeInitSwLeds) + padapter->hal_func.DeInitSwLeds(padapter); } u32 rtw_hal_power_on(_adapter *padapter) { - return padapter->HalFunc.hal_power_on(padapter); + u32 ret = 0; + + ret = padapter->hal_func.hal_power_on(padapter); + +#ifdef CONFIG_BT_COEXIST + if (ret == _SUCCESS) + rtw_btcoex_PowerOnSetting(padapter); +#endif + + return ret; } void rtw_hal_power_off(_adapter *padapter) { @@ -165,7 +180,11 @@ void rtw_hal_power_off(_adapter *padapter) _rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT); - padapter->HalFunc.hal_power_off(padapter); +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_PowerOffSetting(padapter); +#endif + + padapter->hal_func.hal_power_off(padapter); } @@ -196,7 +215,7 @@ uint rtw_hal_init(_adapter *padapter) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); int i; - status = padapter->HalFunc.hal_init(padapter); + status = padapter->hal_func.hal_init(padapter); if (status == _SUCCESS) { pHalData->hw_init_completed = _TRUE; @@ -220,10 +239,9 @@ uint rtw_hal_init(_adapter *padapter) } else { pHalData->hw_init_completed = _FALSE; - RTW_INFO("rtw_hal_init: hal__init fail\n"); + RTW_INFO("rtw_hal_init: hal_init fail\n"); } - RT_TRACE(_module_hal_init_c_, _drv_err_, ("-rtl871x_hal_init:status=0x%x\n", status)); return status; @@ -235,9 +253,8 @@ uint rtw_hal_deinit(_adapter *padapter) struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); int i; - _func_enter_; - status = padapter->HalFunc.hal_deinit(padapter); + status = padapter->hal_func.hal_deinit(padapter); if (status == _SUCCESS) { rtw_led_control(padapter, LED_CTL_POWER_OFF); @@ -245,52 +262,43 @@ uint rtw_hal_deinit(_adapter *padapter) } else RTW_INFO("\n rtw_hal_deinit: hal_init fail\n"); - _func_exit_; return status; } void rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val) { - padapter->HalFunc.SetHwRegHandler(padapter, variable, val); + padapter->hal_func.set_hw_reg_handler(padapter, variable, val); } void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val) { - padapter->HalFunc.GetHwRegHandler(padapter, variable, val); + padapter->hal_func.GetHwRegHandler(padapter, variable, val); } -#ifdef CONFIG_C2H_PACKET_EN -void rtw_hal_set_hwreg_with_buf(_adapter *padapter, u8 variable, u8 *pbuf, int len) -{ - if (padapter->HalFunc.SetHwRegHandlerWithBuf) - padapter->HalFunc.SetHwRegHandlerWithBuf(padapter, variable, pbuf, len); -} -#endif - u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue) { - return padapter->HalFunc.SetHalDefVarHandler(padapter, eVariable, pValue); + return padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue); } u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue) { - return padapter->HalFunc.GetHalDefVarHandler(padapter, eVariable, pValue); + return padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue); } void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet) { - padapter->HalFunc.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet); + padapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet); } void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2) { - padapter->HalFunc.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2); + padapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2); } /* FOR SDIO & PCIE */ void rtw_hal_enable_interrupt(_adapter *padapter) { #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) - padapter->HalFunc.enable_interrupt(padapter); + padapter->hal_func.enable_interrupt(padapter); #endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */ } @@ -298,7 +306,7 @@ void rtw_hal_enable_interrupt(_adapter *padapter) void rtw_hal_disable_interrupt(_adapter *padapter) { #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) - padapter->HalFunc.disable_interrupt(padapter); + padapter->hal_func.disable_interrupt(padapter); #endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */ } @@ -306,24 +314,37 @@ void rtw_hal_disable_interrupt(_adapter *padapter) u8 rtw_hal_check_ips_status(_adapter *padapter) { u8 val = _FALSE; - if (padapter->HalFunc.check_ips_status) - val = padapter->HalFunc.check_ips_status(padapter); + if (padapter->hal_func.check_ips_status) + val = padapter->hal_func.check_ips_status(padapter); else - RTW_INFO("%s: HalFunc.check_ips_status is NULL!\n", __FUNCTION__); + RTW_INFO("%s: hal_func.check_ips_status is NULL!\n", __FUNCTION__); return val; } s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan) { - return padapter->HalFunc.fw_dl(padapter, wowlan); + return padapter->hal_func.fw_dl(padapter, wowlan); +} + +#ifdef RTW_HALMAC +s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem) +{ + u32 dlfw_start_time = rtw_get_current_time(); + s32 rst = _FALSE; + + rst = padapter->hal_func.fw_mem_dl(padapter, mem); + RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(dlfw_start_time)); + + return rst; } +#endif #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) void rtw_hal_clear_interrupt(_adapter *padapter) { #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - padapter->HalFunc.clear_interrupt(padapter); + padapter->hal_func.clear_interrupt(padapter); #endif } #endif @@ -332,14 +353,14 @@ void rtw_hal_clear_interrupt(_adapter *padapter) u32 rtw_hal_inirp_init(_adapter *padapter) { if (is_primary_adapter(padapter)) - return padapter->HalFunc.inirp_init(padapter); + return padapter->hal_func.inirp_init(padapter); return _SUCCESS; } u32 rtw_hal_inirp_deinit(_adapter *padapter) { if (is_primary_adapter(padapter)) - return padapter->HalFunc.inirp_deinit(padapter); + return padapter->hal_func.inirp_deinit(padapter); return _SUCCESS; } @@ -348,26 +369,78 @@ u32 rtw_hal_inirp_deinit(_adapter *padapter) #if defined(CONFIG_PCI_HCI) void rtw_hal_irp_reset(_adapter *padapter) { - padapter->HalFunc.irp_reset(GET_PRIMARY_ADAPTER(padapter)); + padapter->hal_func.irp_reset(GET_PRIMARY_ADAPTER(padapter)); +} + +void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data) +{ + u16 cmd[2]; + + cmd[0] = addr; + cmd[1] = data; + + padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_DBI, (u8 *) cmd); +} + +u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr) +{ + padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_DBI, (u8 *)(&addr)); + + return (u8)addr; +} + +void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data) +{ + u16 cmd[2]; + + cmd[0] = (u16)addr; + cmd[1] = data; + + padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_MDIO, (u8 *) cmd); +} + +u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr) +{ + padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_MDIO, &addr); + + return (u8)addr; +} + +u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter) +{ + u8 l1off; + + padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_NIC_SUPPORT, &l1off); + return l1off; +} + +u8 rtw_hal_pci_l1off_capability(_adapter *padapter) +{ + u8 l1off; + + padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_CAPABILITY, &l1off); + return l1off; } + + #endif /* #if defined(CONFIG_PCI_HCI) */ /* for USB Auto-suspend */ u8 rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val) { - if (padapter->HalFunc.interface_ps_func) - return padapter->HalFunc.interface_ps_func(padapter, efunc_id, val); + if (padapter->hal_func.interface_ps_func) + return padapter->hal_func.interface_ps_func(padapter, efunc_id, val); return _FAIL; } s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) { - return padapter->HalFunc.hal_xmitframe_enqueue(padapter, pxmitframe); + return padapter->hal_func.hal_xmitframe_enqueue(padapter, pxmitframe); } s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe) { - return padapter->HalFunc.hal_xmit(padapter, pxmitframe); + return padapter->hal_func.hal_xmit(padapter, pxmitframe); } /* @@ -383,7 +456,7 @@ s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe) update_mgntframe_attrib_addr(padapter, pmgntframe); pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - subtype = GetFrameSubType(pframe); /* bit(7)~bit(2) */ + subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */ /* pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; */ /* _rtw_memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN); */ @@ -409,29 +482,102 @@ s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe) } #endif /* CONFIG_IEEE80211W */ no_mgmt_coalesce: - ret = padapter->HalFunc.mgnt_xmit(padapter, pmgntframe); + ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe); return ret; } s32 rtw_hal_init_xmit_priv(_adapter *padapter) { - return padapter->HalFunc.init_xmit_priv(padapter); + return padapter->hal_func.init_xmit_priv(padapter); } void rtw_hal_free_xmit_priv(_adapter *padapter) { - padapter->HalFunc.free_xmit_priv(padapter); + padapter->hal_func.free_xmit_priv(padapter); } s32 rtw_hal_init_recv_priv(_adapter *padapter) { - return padapter->HalFunc.init_recv_priv(padapter); + return padapter->hal_func.init_recv_priv(padapter); } void rtw_hal_free_recv_priv(_adapter *padapter) { - padapter->HalFunc.free_recv_priv(padapter); + padapter->hal_func.free_recv_priv(padapter); +} + +void rtw_update_ramask(_adapter *padapter, struct sta_info *psta, u32 mac_id, u8 rssi_level, u8 is_update_bw) +{ + struct macid_cfg h2c_macid_cfg; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + u8 disable_cck_rate = FALSE, MimoPs_enable = FALSE; + u32 ratr_bitmap_msb = 0, ratr_bitmap_lsb = 0; + u64 mask = 0, rate_bitmap = 0; + u8 bw, short_gi; + + if (psta == NULL) { + RTW_ERR(FUNC_ADPT_FMT" macid:%u, sta is NULL\n", FUNC_ADPT_ARG(padapter), mac_id); + rtw_warn_on(1); + return; + } + _rtw_memset(&h2c_macid_cfg, 0, sizeof(struct macid_cfg)); + + bw = rtw_get_tx_bw_mode(padapter, psta); + short_gi = query_ra_short_GI(psta, bw); + + ratr_bitmap_msb = (u32)(psta->ra_mask >> 32); + ratr_bitmap_lsb = (u32)(psta->ra_mask); + + phydm_update_hal_ra_mask(&hal_data->odmpriv, psta->wireless_mode, hal_data->rf_type, bw, MimoPs_enable, disable_cck_rate, &ratr_bitmap_msb, &ratr_bitmap_lsb, rssi_level); + mask = (((u64)ratr_bitmap_msb) << 32) | ((u64)ratr_bitmap_lsb); + + +#ifdef CONFIG_BT_COEXIST + if (hal_data->EEPROMBluetoothCoexist == 1) { + rate_bitmap = rtw_btcoex_GetRaMask(padapter); + mask &= ~rate_bitmap; + } +#endif /* CONFIG_BT_COEXIST */ + +#ifdef CONFIG_CMCC_TEST +#ifdef CONFIG_BT_COEXIST + if (pmlmeext->cur_wireless_mode & WIRELESS_11G) { + if (mac_id == 0) { + RTW_INFO("CMCC_BT update raid entry, mask=0x%x\n", mask); + /*mask &=0xffffffc0; //disable CCK & <12M OFDM rate for 11G mode for CMCC */ + mask &= 0xffffff00; /*disable CCK & <24M OFDM rate for 11G mode for CMCC */ + RTW_INFO("CMCC_BT update raid entry, mask=0x%x\n", mask); + } + } +#endif +#endif + + /*set correct initial date rate for each mac_id */ + hal_data->INIDATA_RATE[mac_id] = psta->init_rate; + + + RTW_INFO("%s => mac_id:%d, networkType:0x%02x, mask:0x%016llx\n\t ==> rssi_level:%d, rate_bitmap:0x%016llx, shortGIrate=%d\n\t ==> bw:%d, ignore_bw:0x%d\n", + __func__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap, short_gi, bw, (!is_update_bw)); + + rtw_macid_ctl_set_bw(macid_ctl, mac_id, bw); + rtw_macid_ctl_set_vht_en(macid_ctl, mac_id, is_supported_vht(psta->wireless_mode)); + rtw_macid_ctl_set_rate_bmp0(macid_ctl, mac_id, mask); + rtw_macid_ctl_set_rate_bmp1(macid_ctl, mac_id, mask >> 32); + rtw_update_tx_rate_bmp(adapter_to_dvobj(padapter)); + + h2c_macid_cfg.mac_id = mac_id; + h2c_macid_cfg.rate_id = psta->raid; + h2c_macid_cfg.bandwidth = bw; + h2c_macid_cfg.ignore_bw = (!is_update_bw); + h2c_macid_cfg.short_gi = short_gi; + h2c_macid_cfg.ra_mask = mask; + + padapter->hal_func.update_ra_mask_handler(padapter, psta, &h2c_macid_cfg); } -void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level) +void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level, u8 is_update_bw) { _adapter *padapter; struct mlme_priv *pmlmepriv; @@ -444,14 +590,11 @@ void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level) pmlmepriv = &(padapter->mlmepriv); if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) - add_RATid(padapter, psta, rssi_level); - else - padapter->HalFunc.UpdateRAMaskHandler(padapter, psta->mac_id, rssi_level); -} - -void rtw_hal_add_ra_tid(_adapter *padapter, u64 bitmap, u8 *arg, u8 rssi_level) -{ - padapter->HalFunc.Add_RateATid(padapter, bitmap, arg, rssi_level); + add_RATid(padapter, psta, rssi_level, is_update_bw); + else { + psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + rtw_update_ramask(padapter, psta, psta->mac_id, rssi_level, is_update_bw); + } } /* Start specifical interface thread */ @@ -459,7 +602,7 @@ void rtw_hal_start_thread(_adapter *padapter) { #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) #ifndef CONFIG_SDIO_TX_TASKLET - padapter->HalFunc.run_thread(padapter); + padapter->hal_func.run_thread(padapter); #endif #endif } @@ -469,7 +612,7 @@ void rtw_hal_stop_thread(_adapter *padapter) #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) #ifndef CONFIG_SDIO_TX_TASKLET - padapter->HalFunc.cancel_thread(padapter); + padapter->hal_func.cancel_thread(padapter); #endif #endif @@ -478,22 +621,22 @@ void rtw_hal_stop_thread(_adapter *padapter) u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask) { u32 data = 0; - if (padapter->HalFunc.read_bbreg) - data = padapter->HalFunc.read_bbreg(padapter, RegAddr, BitMask); + if (padapter->hal_func.read_bbreg) + data = padapter->hal_func.read_bbreg(padapter, RegAddr, BitMask); return data; } void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data) { - if (padapter->HalFunc.write_bbreg) - padapter->HalFunc.write_bbreg(padapter, RegAddr, BitMask, Data); + if (padapter->hal_func.write_bbreg) + padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data); } u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask) { u32 data = 0; - if (padapter->HalFunc.read_rfreg) { - data = padapter->HalFunc.read_rfreg(padapter, eRFPath, RegAddr, BitMask); + if (padapter->hal_func.read_rfreg) { + data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask); if (match_rf_read_sniff_ranges(eRFPath, RegAddr, BitMask)) { RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n" @@ -506,14 +649,14 @@ u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) { - if (padapter->HalFunc.write_rfreg) { + if (padapter->hal_func.write_rfreg) { if (match_rf_write_sniff_ranges(eRFPath, RegAddr, BitMask)) { RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n" , eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data); } - padapter->HalFunc.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data); + padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data); #ifdef CONFIG_PCI_HCI if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/ @@ -526,79 +669,77 @@ void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMa s32 rtw_hal_interrupt_handler(_adapter *padapter) { s32 ret = _FAIL; - ret = padapter->HalFunc.interrupt_handler(padapter); + ret = padapter->hal_func.interrupt_handler(padapter); return ret; } #endif #if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT) void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf) { - padapter->HalFunc.interrupt_handler(padapter, pkt_len, pbuf); + padapter->hal_func.interrupt_handler(padapter, pkt_len, pbuf); } #endif -void rtw_hal_set_bwmode(_adapter *padapter, CHANNEL_WIDTH Bandwidth, u8 Offset) +void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress == _TRUE) + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0; + u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0; + u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0; + u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0; + + odm_acquire_spin_lock(pDM_Odm, RT_IQK_SPINLOCK); + if (pDM_Odm->rf_calibrate_info.is_iqk_in_progress == _TRUE) RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__); - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - padapter->HalFunc.set_bwmode_handler(padapter, Bandwidth, Offset); + odm_release_spin_lock(pDM_Odm, RT_IQK_SPINLOCK); -} - -void rtw_hal_set_chan(_adapter *padapter, u8 channel) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + /* MP mode channel don't use secondary channel */ + if (rtw_mp_mode_check(padapter) == _FALSE) { + #if 0 + if (cch_160 != 0) + cch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80); + #endif + if (cch_80 != 0) + cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, Offset80); + if (cch_40 != 0) + cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, Offset40); + } - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress == _TRUE) - RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__); - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - padapter->HalFunc.set_channel_handler(padapter, channel); -} + pHalData->cch_80 = cch_80; + pHalData->cch_40 = cch_40; + pHalData->cch_20 = cch_20; -void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + if (0) + RTW_INFO("%s cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u)\n", __func__ + , channel, ch_width_str(Bandwidth), Offset40, Offset80 + , pHalData->cch_80, pHalData->cch_40, pHalData->cch_20); - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - if (pDM_Odm->RFCalibrateInfo.bIQKInProgress == _TRUE) - RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__); - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - padapter->HalFunc.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80); + padapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80); } void rtw_hal_set_tx_power_level(_adapter *padapter, u8 channel) { - if (padapter->HalFunc.set_tx_power_level_handler) - padapter->HalFunc.set_tx_power_level_handler(padapter, channel); + if (padapter->hal_func.set_tx_power_level_handler) + padapter->hal_func.set_tx_power_level_handler(padapter, channel); } void rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel) { - if (padapter->HalFunc.get_tx_power_level_handler) - padapter->HalFunc.get_tx_power_level_handler(padapter, powerlevel); + if (padapter->hal_func.get_tx_power_level_handler) + padapter->hal_func.get_tx_power_level_handler(padapter, powerlevel); } void rtw_hal_dm_watchdog(_adapter *padapter) { - if (!is_primary_adapter(padapter)) - return; - #ifdef CONFIG_MCC_MODE if (MCC_EN(padapter)) { if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) return; } #endif /* CONFIG_MCC_MODE */ - - padapter->HalFunc.hal_dm_watchdog(padapter); + rtw_hal_turbo_edca(padapter); + padapter->hal_func.hal_dm_watchdog(padapter); } @@ -606,26 +747,28 @@ void rtw_hal_dm_watchdog(_adapter *padapter) void rtw_hal_dm_watchdog_in_lps(_adapter *padapter) { #if defined(CONFIG_CONCURRENT_MODE) +#ifndef CONFIG_FW_MULTI_PORT_SUPPORT if (padapter->hw_port != HW_PORT0) return; +#endif #endif if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE) { - padapter->HalFunc.hal_dm_watchdog_in_lps(padapter);/* this fuction caller is in interrupt context */ + padapter->hal_func.hal_dm_watchdog_in_lps(padapter);/* this function caller is in interrupt context */ } } #endif void rtw_hal_bcn_related_reg_setting(_adapter *padapter) { - padapter->HalFunc.SetBeaconRelatedRegistersHandler(padapter); + padapter->hal_func.SetBeaconRelatedRegistersHandler(padapter); } #ifdef CONFIG_HOSTAPD_MLME s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt) { - if (padapter->HalFunc.hostap_mgnt_xmit_entry) - return padapter->HalFunc.hostap_mgnt_xmit_entry(padapter, pkt); + if (padapter->hal_func.hostap_mgnt_xmit_entry) + return padapter->hal_func.hostap_mgnt_xmit_entry(padapter, pkt); return _FAIL; } #endif /* CONFIG_HOSTAPD_MLME */ @@ -633,49 +776,44 @@ s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt) #ifdef DBG_CONFIG_ERROR_DETECT void rtw_hal_sreset_init(_adapter *padapter) { - padapter->HalFunc.sreset_init_value(padapter); + padapter->hal_func.sreset_init_value(padapter); } void rtw_hal_sreset_reset(_adapter *padapter) { padapter = GET_PRIMARY_ADAPTER(padapter); - padapter->HalFunc.silentreset(padapter); + padapter->hal_func.silentreset(padapter); } void rtw_hal_sreset_reset_value(_adapter *padapter) { - padapter->HalFunc.sreset_reset_value(padapter); + padapter->hal_func.sreset_reset_value(padapter); } void rtw_hal_sreset_xmit_status_check(_adapter *padapter) { - if (!is_primary_adapter(padapter)) - return; - - padapter->HalFunc.sreset_xmit_status_check(padapter); + padapter->hal_func.sreset_xmit_status_check(padapter); } void rtw_hal_sreset_linked_status_check(_adapter *padapter) { - if (!is_primary_adapter(padapter)) - return; - padapter->HalFunc.sreset_linked_status_check(padapter); + padapter->hal_func.sreset_linked_status_check(padapter); } u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter) { - return padapter->HalFunc.sreset_get_wifi_status(padapter); + return padapter->hal_func.sreset_get_wifi_status(padapter); } bool rtw_hal_sreset_inprogress(_adapter *padapter) { padapter = GET_PRIMARY_ADAPTER(padapter); - return padapter->HalFunc.sreset_inprogress(padapter); + return padapter->hal_func.sreset_inprogress(padapter); } #endif /* DBG_CONFIG_ERROR_DETECT */ #ifdef CONFIG_IOL -int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt) +int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_waiting_ms, u32 bndy_cnt) { - if (adapter->HalFunc.IOL_exec_cmds_sync) - return adapter->HalFunc.IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms, bndy_cnt); + if (adapter->hal_func.IOL_exec_cmds_sync) + return adapter->hal_func.IOL_exec_cmds_sync(adapter, xmit_frame, max_waiting_ms, bndy_cnt); return _FAIL; } #endif @@ -683,60 +821,204 @@ int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wat #ifdef CONFIG_XMIT_THREAD_MODE s32 rtw_hal_xmit_thread_handler(_adapter *padapter) { - return padapter->HalFunc.xmit_thread_handler(padapter); + return padapter->hal_func.xmit_thread_handler(padapter); +} +#endif + +#ifdef CONFIG_RECV_THREAD_MODE +s32 rtw_hal_recv_hdl(_adapter *adapter) +{ + return adapter->hal_func.recv_hdl(adapter); } #endif void rtw_hal_notch_filter(_adapter *adapter, bool enable) { - if (adapter->HalFunc.hal_notch_filter) - adapter->HalFunc.hal_notch_filter(adapter, enable); + if (adapter->hal_func.hal_notch_filter) + adapter->hal_func.hal_notch_filter(adapter, enable); } -bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf) +#ifdef CONFIG_FW_C2H_REG +inline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf) { HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter); - HAL_VERSION *hal_ver = &HalData->VersionID; + HAL_VERSION *hal_ver = &HalData->version_id; bool ret = _FAIL; - if (IS_8188E(*hal_ver)) - ret = c2h_evt_valid((struct c2h_evt_hdr *)buf); - else if (IS_8192E(*hal_ver) || IS_8812_SERIES(*hal_ver) || IS_8821_SERIES(*hal_ver) || IS_8723B_SERIES(*hal_ver)) - ret = c2h_evt_valid((struct c2h_evt_hdr_88xx *)buf); - else - rtw_warn_on(1); + ret = C2H_ID_88XX(buf) || C2H_PLEN_88XX(buf); return ret; } -s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf) +inline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf) { HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter); - HAL_VERSION *hal_ver = &HalData->VersionID; + HAL_VERSION *hal_ver = &HalData->version_id; s32 ret = _FAIL; - if (IS_8188E(*hal_ver)) - ret = c2h_evt_read(adapter, buf); - else if (IS_8192E(*hal_ver) || IS_8812_SERIES(*hal_ver) || IS_8821_SERIES(*hal_ver) || IS_8723B_SERIES(*hal_ver)) - ret = c2h_evt_read_88xx(adapter, buf); - else - rtw_warn_on(1); + ret = c2h_evt_read_88xx(adapter, buf); + + return ret; +} + +bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload) +{ + HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter); + HAL_VERSION *hal_ver = &HalData->version_id; + bool ret = _FAIL; + + *id = C2H_ID_88XX(buf); + *seq = C2H_SEQ_88XX(buf); + *plen = C2H_PLEN_88XX(buf); + *payload = C2H_PAYLOAD_88XX(buf); + ret = _SUCCESS; + + return ret; +} +#endif /* CONFIG_FW_C2H_REG */ + +#ifdef CONFIG_FW_C2H_PKT +bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload) +{ + HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter); + HAL_VERSION *hal_ver = &HalData->version_id; + bool ret = _FAIL; + + if (!buf || len > 256 || len < 3) + goto exit; + + *id = C2H_ID_88XX(buf); + *seq = C2H_SEQ_88XX(buf); + *plen = len - 2; + *payload = C2H_PAYLOAD_88XX(buf); + ret = _SUCCESS; + +exit: + return ret; +} +#endif /* CONFIG_FW_C2H_PKT */ + +#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B) +#include /* for MPTBT_FwC2hBtMpCtrl */ +#endif +s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *odm = &hal_data->odmpriv; + u8 sub_id = 0; + s32 ret = _SUCCESS; + + switch (id) { + case C2H_FW_SCAN_COMPLETE: + RTW_INFO("[C2H], FW Scan Complete\n"); + break; + +#ifdef CONFIG_BT_COEXIST + case C2H_BT_INFO: + rtw_btcoex_BtInfoNotify(adapter, plen, payload); + break; + case C2H_BT_MP_INFO: + #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B) + MPTBT_FwC2hBtMpCtrl(adapter, payload, plen); + #endif + rtw_btcoex_BtMpRptNotify(adapter, plen, payload); + break; + case C2H_MAILBOX_STATUS: + RTW_INFO_DUMP("C2H_MAILBOX_STATUS: ", payload, plen); + break; +#endif /* CONFIG_BT_COEXIST */ + + case C2H_IQK_FINISH: + c2h_iqk_offload(adapter, payload, plen); + break; + +#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) + case C2H_FW_CHNL_SWITCH_COMPLETE: + rtw_tdls_chsw_oper_done(adapter); + break; + case C2H_BCN_EARLY_RPT: + rtw_tdls_ch_sw_back_to_base_chnl(adapter); + break; +#endif + +#ifdef CONFIG_MCC_MODE + case C2H_MCC: + rtw_hal_mcc_c2h_handler(adapter, plen, payload); + break; +#endif + +#ifdef CONFIG_RTW_MAC_HIDDEN_RPT + case C2H_MAC_HIDDEN_RPT: + c2h_mac_hidden_rpt_hdl(adapter, payload, plen); + break; + case C2H_MAC_HIDDEN_RPT_2: + c2h_mac_hidden_rpt_2_hdl(adapter, payload, plen); + break; +#endif + + case C2H_DEFEATURE_DBG: + c2h_defeature_dbg_hdl(adapter, payload, plen); + break; + +#ifdef CONFIG_RTW_CUSTOMER_STR + case C2H_CUSTOMER_STR_RPT: + c2h_customer_str_rpt_hdl(adapter, payload, plen); + break; + case C2H_CUSTOMER_STR_RPT_2: + c2h_customer_str_rpt_2_hdl(adapter, payload, plen); + break; +#endif + + case C2H_EXTEND: + sub_id = payload[0]; + /* no handle, goto default */ + + default: + if (phydm_c2H_content_parsing(odm, id, plen, payload) != TRUE) + ret = _FAIL; + break; + } + +exit: + if (ret != _SUCCESS) { + if (id == C2H_EXTEND) + RTW_WARN("%s: unknown C2H(0x%02x, 0x%02x)\n", __func__, id, sub_id); + else + RTW_WARN("%s: unknown C2H(0x%02x)\n", __func__, id); + } return ret; } -s32 rtw_hal_c2h_handler(_adapter *adapter, u8 *c2h_evt) +#ifndef RTW_HALMAC +s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) { s32 ret = _FAIL; - if (adapter->HalFunc.c2h_handler) - ret = adapter->HalFunc.c2h_handler(adapter, c2h_evt); + + ret = adapter->hal_func.c2h_handler(adapter, id, seq, plen, payload); + if (ret != _SUCCESS) + ret = c2h_handler(adapter, id, seq, plen, payload); + return ret; } -c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter) +s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) { - return adapter->HalFunc.c2h_id_filter_ccx; + switch (id) { + case C2H_CCX_TX_RPT: + case C2H_BT_MP_INFO: + case C2H_FW_CHNL_SWITCH_COMPLETE: + case C2H_IQK_FINISH: + case C2H_MCC: + case C2H_BCN_EARLY_RPT: + case C2H_AP_REQ_TXRPT: + case C2H_SPC_STAT: + return _TRUE; + default: + return _FALSE; + } } +#endif /* !RTW_HALMAC */ s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter) { @@ -791,8 +1073,8 @@ s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBu { _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter); - if (pri_adapter->bFWReady == _TRUE) - return padapter->HalFunc.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer); + if (GET_HAL_DATA(pri_adapter)->bFWReady == _TRUE) + return padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer); else if (padapter->registrypriv.mp_mode == 0) RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n" , FUNC_ADPT_ARG(padapter), ElementID); @@ -802,52 +1084,52 @@ s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBu void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame) { - padapter->HalFunc.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame); + padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame); } u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan) { - return adapter->HalFunc.hal_get_tx_buff_rsvd_page_num(adapter, wowlan); + return adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan); } #ifdef CONFIG_GPIO_API void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag) { - if (padapter->HalFunc.update_hisr_hsisr_ind) - padapter->HalFunc.update_hisr_hsisr_ind(padapter, flag); + if (padapter->hal_func.update_hisr_hsisr_ind) + padapter->hal_func.update_hisr_hsisr_ind(padapter, flag); } int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num) { int ret = _SUCCESS; - if (padapter->HalFunc.hal_gpio_func_check) - ret = padapter->HalFunc.hal_gpio_func_check(padapter, gpio_num); + if (padapter->hal_func.hal_gpio_func_check) + ret = padapter->hal_func.hal_gpio_func_check(padapter, gpio_num); return ret; } void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num) { - if (padapter->HalFunc.hal_gpio_multi_func_reset) - padapter->HalFunc.hal_gpio_multi_func_reset(padapter, gpio_num); + if (padapter->hal_func.hal_gpio_multi_func_reset) + padapter->hal_func.hal_gpio_multi_func_reset(padapter, gpio_num); } #endif void rtw_hal_fw_correct_bcn(_adapter *padapter) { - if (padapter->HalFunc.fw_correct_bcn) - padapter->HalFunc.fw_correct_bcn(padapter); + if (padapter->hal_func.fw_correct_bcn) + padapter->hal_func.fw_correct_bcn(padapter); } void rtw_hal_set_tx_power_index(PADAPTER padapter, u32 powerindex, u8 rfpath, u8 rate) { - return padapter->HalFunc.set_tx_power_index_handler(padapter, powerindex, rfpath, rate); + return padapter->hal_func.set_tx_power_index_handler(padapter, powerindex, rfpath, rate); } -u8 rtw_hal_get_tx_power_index(PADAPTER padapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel) +u8 rtw_hal_get_tx_power_index(PADAPTER padapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic) { - return padapter->HalFunc.get_tx_power_index_handler(padapter, rfpath, rate, bandwidth, channel); + return padapter->hal_func.get_tx_power_index_handler(padapter, rfpath, rate, bandwidth, channel, tic); } #ifdef RTW_HALMAC @@ -861,7 +1143,7 @@ u8 rtw_hal_get_tx_power_index(PADAPTER padapter, u8 rfpath, u8 rate, u8 bandwidt */ u8 rtw_hal_init_mac_register(PADAPTER adapter) { - return adapter->HalFunc.init_mac_register(adapter); + return adapter->hal_func.init_mac_register(adapter); } /* @@ -874,87 +1156,87 @@ u8 rtw_hal_init_mac_register(PADAPTER adapter) */ u8 rtw_hal_init_phy(PADAPTER adapter) { - return adapter->HalFunc.init_phy(adapter); + return adapter->hal_func.init_phy(adapter); } #endif /* RTW_HALMAC */ #define rtw_hal_error_msg(ops_fun) \ - RTW_PRINT("### %s - Error : Please hook HalFunc.%s ###\n", __FUNCTION__, ops_fun) + RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun) u8 rtw_hal_ops_check(_adapter *padapter) { u8 ret = _SUCCESS; #if 1 /*** initialize section ***/ - if (NULL == padapter->HalFunc.read_chip_version) { + if (NULL == padapter->hal_func.read_chip_version) { rtw_hal_error_msg("read_chip_version"); ret = _FAIL; } - if (NULL == padapter->HalFunc.init_default_value) { + if (NULL == padapter->hal_func.init_default_value) { rtw_hal_error_msg("init_default_value"); ret = _FAIL; } - if (NULL == padapter->HalFunc.intf_chip_configure) { + if (NULL == padapter->hal_func.intf_chip_configure) { rtw_hal_error_msg("intf_chip_configure"); ret = _FAIL; } - if (NULL == padapter->HalFunc.read_adapter_info) { + if (NULL == padapter->hal_func.read_adapter_info) { rtw_hal_error_msg("read_adapter_info"); ret = _FAIL; } - if (NULL == padapter->HalFunc.hal_power_on) { + if (NULL == padapter->hal_func.hal_power_on) { rtw_hal_error_msg("hal_power_on"); ret = _FAIL; } - if (NULL == padapter->HalFunc.hal_power_off) { + if (NULL == padapter->hal_func.hal_power_off) { rtw_hal_error_msg("hal_power_off"); ret = _FAIL; } - if (NULL == padapter->HalFunc.hal_init) { + if (NULL == padapter->hal_func.hal_init) { rtw_hal_error_msg("hal_init"); ret = _FAIL; } - if (NULL == padapter->HalFunc.hal_deinit) { + if (NULL == padapter->hal_func.hal_deinit) { rtw_hal_error_msg("hal_deinit"); ret = _FAIL; } /*** xmit section ***/ - if (NULL == padapter->HalFunc.init_xmit_priv) { + if (NULL == padapter->hal_func.init_xmit_priv) { rtw_hal_error_msg("init_xmit_priv"); ret = _FAIL; } - if (NULL == padapter->HalFunc.free_xmit_priv) { + if (NULL == padapter->hal_func.free_xmit_priv) { rtw_hal_error_msg("free_xmit_priv"); ret = _FAIL; } - if (NULL == padapter->HalFunc.hal_xmit) { + if (NULL == padapter->hal_func.hal_xmit) { rtw_hal_error_msg("hal_xmit"); ret = _FAIL; } - if (NULL == padapter->HalFunc.mgnt_xmit) { + if (NULL == padapter->hal_func.mgnt_xmit) { rtw_hal_error_msg("mgnt_xmit"); ret = _FAIL; } #ifdef CONFIG_XMIT_THREAD_MODE - if (NULL == padapter->HalFunc.xmit_thread_handler) { + if (NULL == padapter->hal_func.xmit_thread_handler) { rtw_hal_error_msg("xmit_thread_handler"); ret = _FAIL; } #endif - if (NULL == padapter->HalFunc.hal_xmitframe_enqueue) { + if (NULL == padapter->hal_func.hal_xmitframe_enqueue) { rtw_hal_error_msg("hal_xmitframe_enqueue"); ret = _FAIL; } #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) #ifndef CONFIG_SDIO_TX_TASKLET - if (NULL == padapter->HalFunc.run_thread) { + if (NULL == padapter->hal_func.run_thread) { rtw_hal_error_msg("run_thread"); ret = _FAIL; } - if (NULL == padapter->HalFunc.cancel_thread) { + if (NULL == padapter->hal_func.cancel_thread) { rtw_hal_error_msg("cancel_thread"); ret = _FAIL; } @@ -962,20 +1244,26 @@ u8 rtw_hal_ops_check(_adapter *padapter) #endif /*** recv section ***/ - if (NULL == padapter->HalFunc.init_recv_priv) { + if (NULL == padapter->hal_func.init_recv_priv) { rtw_hal_error_msg("init_recv_priv"); ret = _FAIL; } - if (NULL == padapter->HalFunc.free_recv_priv) { + if (NULL == padapter->hal_func.free_recv_priv) { rtw_hal_error_msg("free_recv_priv"); ret = _FAIL; } +#ifdef CONFIG_RECV_THREAD_MODE + if (NULL == padapter->hal_func.recv_hdl) { + rtw_hal_error_msg("recv_hdl"); + ret = _FAIL; + } +#endif #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) - if (NULL == padapter->HalFunc.inirp_init) { + if (NULL == padapter->hal_func.inirp_init) { rtw_hal_error_msg("inirp_init"); ret = _FAIL; } - if (NULL == padapter->HalFunc.inirp_deinit) { + if (NULL == padapter->hal_func.inirp_deinit) { rtw_hal_error_msg("inirp_deinit"); ret = _FAIL; } @@ -984,24 +1272,24 @@ u8 rtw_hal_ops_check(_adapter *padapter) /*** interrupt hdl section ***/ #if defined(CONFIG_PCI_HCI) - if (NULL == padapter->HalFunc.irp_reset) { + if (NULL == padapter->hal_func.irp_reset) { rtw_hal_error_msg("irp_reset"); ret = _FAIL; } #endif/*#if defined(CONFIG_PCI_HCI)*/ #if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)) - if (NULL == padapter->HalFunc.interrupt_handler) { + if (NULL == padapter->hal_func.interrupt_handler) { rtw_hal_error_msg("interrupt_handler"); ret = _FAIL; } #endif /*#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))*/ #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) - if (NULL == padapter->HalFunc.enable_interrupt) { + if (NULL == padapter->hal_func.enable_interrupt) { rtw_hal_error_msg("enable_interrupt"); ret = _FAIL; } - if (NULL == padapter->HalFunc.disable_interrupt) { + if (NULL == padapter->hal_func.disable_interrupt) { rtw_hal_error_msg("disable_interrupt"); ret = _FAIL; } @@ -1009,184 +1297,175 @@ u8 rtw_hal_ops_check(_adapter *padapter) /*** DM section ***/ - if (NULL == padapter->HalFunc.dm_init) { + if (NULL == padapter->hal_func.dm_init) { rtw_hal_error_msg("dm_init"); ret = _FAIL; } - if (NULL == padapter->HalFunc.dm_deinit) { + if (NULL == padapter->hal_func.dm_deinit) { rtw_hal_error_msg("dm_deinit"); ret = _FAIL; } - if (NULL == padapter->HalFunc.hal_dm_watchdog) { + if (NULL == padapter->hal_func.hal_dm_watchdog) { rtw_hal_error_msg("hal_dm_watchdog"); ret = _FAIL; } #ifdef CONFIG_LPS_LCLK_WD_TIMER - if (NULL == padapter->HalFunc.hal_dm_watchdog_in_lps) { + if (NULL == padapter->hal_func.hal_dm_watchdog_in_lps) { rtw_hal_error_msg("hal_dm_watchdog_in_lps"); ret = _FAIL; } #endif /*** xxx section ***/ - if (NULL == padapter->HalFunc.set_bwmode_handler) { - rtw_hal_error_msg("set_bwmode_handler"); - ret = _FAIL; - } - - if (NULL == padapter->HalFunc.set_channel_handler) { - rtw_hal_error_msg("set_channel_handler"); - ret = _FAIL; - } - - if (NULL == padapter->HalFunc.set_chnl_bw_handler) { + if (NULL == padapter->hal_func.set_chnl_bw_handler) { rtw_hal_error_msg("set_chnl_bw_handler"); ret = _FAIL; } - if (NULL == padapter->HalFunc.SetHwRegHandler) { - rtw_hal_error_msg("SetHwRegHandler"); + if (NULL == padapter->hal_func.set_hw_reg_handler) { + rtw_hal_error_msg("set_hw_reg_handler"); ret = _FAIL; } - if (NULL == padapter->HalFunc.GetHwRegHandler) { + if (NULL == padapter->hal_func.GetHwRegHandler) { rtw_hal_error_msg("GetHwRegHandler"); ret = _FAIL; } - if (NULL == padapter->HalFunc.GetHalDefVarHandler) { - rtw_hal_error_msg("GetHalDefVarHandler"); + if (NULL == padapter->hal_func.get_hal_def_var_handler) { + rtw_hal_error_msg("get_hal_def_var_handler"); ret = _FAIL; } - if (NULL == padapter->HalFunc.SetHalDefVarHandler) { + if (NULL == padapter->hal_func.SetHalDefVarHandler) { rtw_hal_error_msg("SetHalDefVarHandler"); ret = _FAIL; } - if (NULL == padapter->HalFunc.GetHalODMVarHandler) { + if (NULL == padapter->hal_func.GetHalODMVarHandler) { rtw_hal_error_msg("GetHalODMVarHandler"); ret = _FAIL; } - if (NULL == padapter->HalFunc.SetHalODMVarHandler) { + if (NULL == padapter->hal_func.SetHalODMVarHandler) { rtw_hal_error_msg("SetHalODMVarHandler"); ret = _FAIL; } - if (NULL == padapter->HalFunc.UpdateRAMaskHandler) { - rtw_hal_error_msg("UpdateRAMaskHandler"); + if (NULL == padapter->hal_func.update_ra_mask_handler) { + rtw_hal_error_msg("update_ra_mask_handler"); ret = _FAIL; } - if (NULL == padapter->HalFunc.SetBeaconRelatedRegistersHandler) { + if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) { rtw_hal_error_msg("SetBeaconRelatedRegistersHandler"); ret = _FAIL; } - if (NULL == padapter->HalFunc.Add_RateATid) { - rtw_hal_error_msg("Add_RateATid"); + if (NULL == padapter->hal_func.fill_h2c_cmd) { + rtw_hal_error_msg("fill_h2c_cmd"); ret = _FAIL; } - if (NULL == padapter->HalFunc.fill_h2c_cmd) { - rtw_hal_error_msg("fill_h2c_cmd"); +#ifdef RTW_HALMAC + if (NULL == padapter->hal_func.hal_mac_c2h_handler) { + rtw_hal_error_msg("hal_mac_c2h_handler"); + ret = _FAIL; + } +#elif !defined(CONFIG_RTL8188E) + if (NULL == padapter->hal_func.c2h_handler) { + rtw_hal_error_msg("c2h_handler"); ret = _FAIL; } +#endif + #if defined(CONFIG_LPS) || defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - if (NULL == padapter->HalFunc.fill_fake_txdesc) { + if (NULL == padapter->hal_func.fill_fake_txdesc) { rtw_hal_error_msg("fill_fake_txdesc"); ret = _FAIL; } #endif - if (NULL == padapter->HalFunc.hal_get_tx_buff_rsvd_page_num) { + if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) { rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num"); ret = _FAIL; } #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - if (NULL == padapter->HalFunc.clear_interrupt) { + if (NULL == padapter->hal_func.clear_interrupt) { rtw_hal_error_msg("clear_interrupt"); ret = _FAIL; } #endif #endif /* CONFIG_WOWLAN */ - if (NULL == padapter->HalFunc.fw_dl) { + if (NULL == padapter->hal_func.fw_dl) { rtw_hal_error_msg("fw_dl"); ret = _FAIL; } +#if defined(RTW_HALMAC) && defined(CONFIG_LPS_PG) + if (NULL == padapter->hal_func.fw_mem_dl) { + rtw_hal_error_msg("fw_mem_dl"); + ret = _FAIL; + } +#endif + if ((IS_HARDWARE_TYPE_8814A(padapter) || IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8822BS(padapter)) - && NULL == padapter->HalFunc.fw_correct_bcn) { + && NULL == padapter->hal_func.fw_correct_bcn) { rtw_hal_error_msg("fw_correct_bcn"); ret = _FAIL; } if (IS_HARDWARE_TYPE_8822B(padapter) || IS_HARDWARE_TYPE_8821C(padapter)) { - if (!padapter->HalFunc.set_tx_power_index_handler) { + if (!padapter->hal_func.set_tx_power_index_handler) { rtw_hal_error_msg("set_tx_power_index_handler"); ret = _FAIL; } - if (!padapter->HalFunc.get_tx_power_index_handler) { - rtw_hal_error_msg("get_tx_power_index_handler"); - ret = _FAIL; - } + } + + if (!padapter->hal_func.get_tx_power_index_handler) { + rtw_hal_error_msg("get_tx_power_index_handler"); + ret = _FAIL; } /*** SReset section ***/ #ifdef DBG_CONFIG_ERROR_DETECT - if (NULL == padapter->HalFunc.sreset_init_value) { + if (NULL == padapter->hal_func.sreset_init_value) { rtw_hal_error_msg("sreset_init_value"); ret = _FAIL; } - if (NULL == padapter->HalFunc.sreset_reset_value) { + if (NULL == padapter->hal_func.sreset_reset_value) { rtw_hal_error_msg("sreset_reset_value"); ret = _FAIL; } - if (NULL == padapter->HalFunc.silentreset) { + if (NULL == padapter->hal_func.silentreset) { rtw_hal_error_msg("silentreset"); ret = _FAIL; } - if (NULL == padapter->HalFunc.sreset_xmit_status_check) { + if (NULL == padapter->hal_func.sreset_xmit_status_check) { rtw_hal_error_msg("sreset_xmit_status_check"); ret = _FAIL; } - if (NULL == padapter->HalFunc.sreset_linked_status_check) { + if (NULL == padapter->hal_func.sreset_linked_status_check) { rtw_hal_error_msg("sreset_linked_status_check"); ret = _FAIL; } - if (NULL == padapter->HalFunc.sreset_get_wifi_status) { + if (NULL == padapter->hal_func.sreset_get_wifi_status) { rtw_hal_error_msg("sreset_get_wifi_status"); ret = _FAIL; } - if (NULL == padapter->HalFunc.sreset_inprogress) { + if (NULL == padapter->hal_func.sreset_inprogress) { rtw_hal_error_msg("sreset_inprogress"); ret = _FAIL; } #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */ #ifdef RTW_HALMAC - if (NULL == padapter->HalFunc.init_mac_register) { + if (NULL == padapter->hal_func.init_mac_register) { rtw_hal_error_msg("init_mac_register"); ret = _FAIL; } - if (NULL == padapter->HalFunc.init_phy) { + if (NULL == padapter->hal_func.init_phy) { rtw_hal_error_msg("init_phy"); ret = _FAIL; } #endif /* RTW_HALMAC */ - -#ifdef CONFIG_NAPI - if (NULL == padapter->HalFunc.napi_irq_disable) { - rtw_hal_error_msg("napi_irq_disable"); - ret = _FAIL; - } - if (NULL == padapter->HalFunc.napi_irq_enable) { - rtw_hal_error_msg("napi_irq_enable"); - ret = _FAIL; - } - if (NULL == padapter->HalFunc.napi_poll) { - rtw_hal_error_msg("napi_poll"); - ret = _FAIL; - } -#endif #endif return ret; } diff --git a/hal/hal_mcc.c b/hal/hal_mcc.c index eb65f59..606d02a 100644 --- a/hal/hal_mcc.c +++ b/hal/hal_mcc.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - ******************************************************************************/ + *****************************************************************************/ #ifdef CONFIG_MCC_MODE #define _HAL_MCC_C_ @@ -24,14 +20,201 @@ #include /* HAL_DATA */ #include /* power control */ -/* backup IQK value */ -void rtw_hal_mcc_backup_IQK_val(PADAPTER padapter) +#define MCC_DURATION_IDX 0 +#define MCC_TSF_SYNC_OFFSET_IDX 1 +#define MCC_START_TIME_OFFSET_IDX 2 +#define MCC_INTERVAL_IDX 3 +#define MCC_GUARD_OFFSET0_IDX 4 +#define MCC_GUARD_OFFSET1_IDX 5 +#define TU 1024 /* 1 TU equals 1024 microseconds */ +/* port 1 druration, TSF sync offset, start time offset, interval (unit:TU (1024 microseconds))*/ +u8 mcc_switch_channel_policy_table[][6]={ + {35, 50, 30, 100, 0, 0}, + {19, 50, 40, 100, 2, 2}, + {25, 50, 30, 100, 5, 5}, +}; + +const int mcc_max_policy_num = sizeof(mcc_switch_channel_policy_table) /sizeof(u8) /6; + +static void dump_iqk_val_table(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct hal_iqk_reg_backup *iqk_reg_backup = pHalData->iqk_reg_backup; + u8 total_rf_path = pHalData->NumTotalRFPath; + u8 rf_path_idx = 0; + u8 backup_chan_idx = 0; + u8 backup_reg_idx = 0; + + RTW_INFO("=============dump IQK backup table================\n"); + for (backup_chan_idx = 0; backup_chan_idx < MAX_IQK_INFO_BACKUP_CHNL_NUM; backup_chan_idx++) { + for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx++) { + for(backup_reg_idx = 0; backup_reg_idx < MAX_IQK_INFO_BACKUP_REG_NUM; backup_reg_idx++) { + RTW_INFO("ch:%d. bw:%d. rf path:%d. reg[%d] = 0x%02x \n" + , iqk_reg_backup[backup_chan_idx].central_chnl + , iqk_reg_backup[backup_chan_idx].bw_mode + , rf_path_idx + , backup_reg_idx + , iqk_reg_backup[backup_chan_idx].reg_backup[rf_path_idx][backup_reg_idx] + ); + } + } + } + RTW_INFO("=============================================\n"); +} + +static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_len) +{ + struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + u8 p2p_noa_attr_ie[MAX_P2P_IE_LEN] = {0x00}; + u32 p2p_noa_attr_len = 0; + u8 noa_desc_num = 1; + u8 opp_ps = 0; /* Disable OppPS */ + u8 noa_count = 255; + u32 noa_duration = 0x20; + u32 noa_interval = 0x64; + u8 noa_index = 0; + u8 mcc_policy_idx = 0; + + mcc_policy_idx = pmccobjpriv->policy_index; + noa_duration = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX]; + noa_interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX]; + + /* P2P OUI(4 bytes) */ + _rtw_memcpy(p2p_noa_attr_ie, P2P_OUI, 4); + p2p_noa_attr_len = p2p_noa_attr_len + 4; + + /* attrute ID(1 byte) */ + p2p_noa_attr_ie[p2p_noa_attr_len] = P2P_ATTR_NOA; + p2p_noa_attr_len = p2p_noa_attr_len + 1; + + /* attrute length(2 bytes) length = noa_desc_num*13 + 2 */ + RTW_PUT_LE16(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_desc_num*13 + 2)); + p2p_noa_attr_len = p2p_noa_attr_len + 2; + + /* Index (1 byte) */ + p2p_noa_attr_ie[p2p_noa_attr_len] = noa_index; + p2p_noa_attr_len = p2p_noa_attr_len + 1; + + /* CTWindow and OppPS Parameters (1 byte) */ + p2p_noa_attr_ie[p2p_noa_attr_len] = opp_ps; + p2p_noa_attr_len = p2p_noa_attr_len+ 1; + + /* NoA Count (1 byte) */ + p2p_noa_attr_ie[p2p_noa_attr_len] = noa_count; + p2p_noa_attr_len = p2p_noa_attr_len + 1; + + /* NoA Duration (4 bytes) unit: microseconds */ + RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_duration * TU)); + p2p_noa_attr_len = p2p_noa_attr_len + 4; + + /* NoA Interval (4 bytes) unit: microseconds */ + RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_interval * TU)); + p2p_noa_attr_len = p2p_noa_attr_len + 4; + + /* NoA Start Time (4 bytes) unit: microseconds */ + RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, pmccadapriv->noa_start_time); + if (0) + RTW_INFO("indxe:%d, start_time=0x%02x:0x%02x:0x%02x:0x%02x\n" + , noa_index + , p2p_noa_attr_ie[p2p_noa_attr_len] + , p2p_noa_attr_ie[p2p_noa_attr_len + 1] + , p2p_noa_attr_ie[p2p_noa_attr_len + 2] + , p2p_noa_attr_ie[p2p_noa_attr_len + 3]); + + p2p_noa_attr_len = p2p_noa_attr_len + 4; + rtw_set_ie(ie, _VENDOR_SPECIFIC_IE_, p2p_noa_attr_len, (u8 *)p2p_noa_attr_ie, ie_len); +} + + +/** + * rtw_hal_mcc_update_go_p2p_ie - update go p2p ie(add NoA attribute) + * @padapter: the adapter to be update go p2p ie + */ +static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter) +{ + struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + u8 *pos = NULL; + + + /* no noa attribute, build it */ + if (pmccadapriv->p2p_go_noa_ie_len == 0) + rtw_hal_mcc_build_p2p_noa_attr(padapter, pmccadapriv->p2p_go_noa_ie, &pmccadapriv->p2p_go_noa_ie_len); + else { + /* has noa attribut, modify it */ + /* update index */ + pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 15; + /* 0~255 */ + (*pos) = ((*pos) + 1) % 256; + if (1) + RTW_INFO("indxe:%d\n", (*pos)); + + /* update start time */ + pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 4; + RTW_PUT_LE32(pos, pmccadapriv->noa_start_time); + if (0) + RTW_INFO("start_time=0x%02x:0x%02x:0x%02x:0x%02x\n" + , ((u8*)(pos))[0] + , ((u8*)(pos))[1] + , ((u8*)(pos))[2] + , ((u8*)(pos))[3]); + + } + + if (0) { + u8 i = 0; + RTW_INFO("p2p_go_noa_ie_len:%d\n", pmccadapriv->p2p_go_noa_ie_len); + + for (i = 0;i < pmccadapriv->p2p_go_noa_ie_len; i++) { + if ((i+1)%8 != 0) + printk("0x%02x ", pmccadapriv->p2p_go_noa_ie[i]); + else + printk("0x%02x\n", pmccadapriv->p2p_go_noa_ie[i]); + } + printk("\n"); + } + update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE); +} + +/** + * rtw_hal_mcc_remove_go_p2p_ie - remove go p2p ie(add NoA attribute) + * @padapter: the adapter to be update go p2p ie + */ +static void rtw_hal_mcc_remove_go_p2p_ie(PADAPTER padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + + /* chech has noa ie or not */ + if (pmccadapriv->p2p_go_noa_ie_len == 0) + return; + + pmccadapriv->p2p_go_noa_ie_len = 0; + update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE); +} + +/* restore IQK value for all interface */ +void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter) { u8 take_care_iqk = _FALSE; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + _adapter *iface = NULL; + u8 i = 0; rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk); - if (take_care_iqk == _TRUE && MCC_EN(padapter)) - rtw_hal_ch_sw_iqk_info_restore(padapter, CH_SW_USE_CASE_MCC); + if (take_care_iqk == _TRUE && MCC_EN(padapter)) { + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface == NULL) + continue; + + rtw_hal_ch_sw_iqk_info_restore(iface, CH_SW_USE_CASE_MCC); + } + } + + if (0) + dump_iqk_val_table(padapter); } u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status) @@ -58,6 +241,73 @@ void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status) pmccobjpriv->mcc_status &= (~mcc_status); } +void rtw_hal_mcc_update_switch_channel_policy_table(PADAPTER padapter) +{ + struct registry_priv *registry_par = &padapter->registrypriv; + u8 idx = 0; + + if (registry_par->rtw_mcc_policy_table_idx < 0) + return; + + if (registry_par->rtw_mcc_policy_table_idx >= mcc_max_policy_num) { + RTW_INFO("[MCC] mcc_policy_table_idx error, do not update policy table\n"); + return; + } + + idx = registry_par->rtw_mcc_policy_table_idx; + + if (registry_par->rtw_mcc_duration > 0) + mcc_switch_channel_policy_table[idx][MCC_DURATION_IDX] = registry_par->rtw_mcc_duration; + + if (registry_par->rtw_mcc_tsf_sync_offset > 0) + mcc_switch_channel_policy_table[idx][MCC_TSF_SYNC_OFFSET_IDX] = registry_par->rtw_mcc_tsf_sync_offset; + + if (registry_par->rtw_mcc_start_time_offset > 0) + mcc_switch_channel_policy_table[idx][MCC_START_TIME_OFFSET_IDX] = registry_par->rtw_mcc_start_time_offset; + + if (registry_par->rtw_mcc_interval > 0) + mcc_switch_channel_policy_table[idx][MCC_INTERVAL_IDX] = registry_par->rtw_mcc_interval; + + if (registry_par->rtw_mcc_guard_offset0 >= 0) + mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET0_IDX] = registry_par->rtw_mcc_guard_offset0; + + if (registry_par->rtw_mcc_guard_offset1 >= 0) + mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET1_IDX] = registry_par->rtw_mcc_guard_offset1; + +} + +static void rtw_hal_config_mcc_switch_channel_setting(PADAPTER padapter) +{ + struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + struct registry_priv *registry_par = &padapter->registrypriv; + u8 interval = pmlmepriv->cur_network.network.Configuration.BeaconPeriod; + u8 i = 0; + s8 mcc_policy_idx = 0; + + rtw_hal_mcc_update_switch_channel_policy_table(padapter); + mcc_policy_idx = registry_par->rtw_mcc_policy_table_idx; + + if (mcc_policy_idx < 0 || mcc_policy_idx >= mcc_max_policy_num) { + pmccobjpriv->policy_index = 0; + RTW_INFO("[MCC] can't find table(%d,%d,%d), use default policy(%d)\n" + , pmccobjpriv->duration, interval, mcc_policy_idx, pmccobjpriv->policy_index); + } else + pmccobjpriv->policy_index = mcc_policy_idx; + + RTW_INFO("[MCC] policy(%d): %d,%d,%d,%d,%d,%d\n" + , pmccobjpriv->policy_index + , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX] + , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_TSF_SYNC_OFFSET_IDX] + , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_START_TIME_OFFSET_IDX] + , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX] + , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX] + , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]); + +} + static void rtw_hal_config_mcc_role_setting(PADAPTER padapter) { struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); @@ -69,13 +319,22 @@ static void rtw_hal_config_mcc_role_setting(PADAPTER padapter) struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta = NULL; struct registry_priv *preg = &padapter->registrypriv; + u8 policy_index = 0; + u8 mcc_duration = 0; + u8 mcc_interval = 0; + + policy_index = pmccobjpriv->policy_index; + mcc_duration = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX] + - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX] + - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]; + mcc_interval = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX]; /* GO/AP is 1nd order GC/STA is 2nd order */ switch (pmccadapriv->role) { case MCC_ROLE_STA: case MCC_ROLE_GC: pmccadapriv->order = 1; - pmccadapriv->mcc_duration = pmccobjpriv->duration; + pmccadapriv->mcc_duration = mcc_duration; switch (pmlmeext->cur_bwmode) { case CHANNEL_WIDTH_20: @@ -116,7 +375,9 @@ static void rtw_hal_config_mcc_role_setting(PADAPTER padapter) case MCC_ROLE_AP: case MCC_ROLE_GO: pmccadapriv->order = 0; - pmccadapriv->mcc_duration = 100 - pmccobjpriv->duration; /* 100 means beacon interval */ + /* total druation value equals interval */ + pmccadapriv->mcc_duration = mcc_interval - mcc_duration; + pmccadapriv->p2p_go_noa_ie_len = 0; /* not NoA attribute at init time */ switch (pmlmeext->cur_bwmode) { case CHANNEL_WIDTH_20: @@ -158,23 +419,21 @@ static void rtw_hal_config_mcc_role_setting(PADAPTER padapter) pmccobjpriv->iface[pmccadapriv->order] = padapter; RTW_INFO(FUNC_ADPT_FMT": order:%d, role:%d, mcc duration:%d, target tx bytes:%d, mgmt queue macid:%d, bitmap:0x%02x\n" , FUNC_ADPT_ARG(padapter), pmccadapriv->order, pmccadapriv->role, pmccadapriv->mcc_duration - , pmccadapriv->mcc_target_tx_bytes_to_port, pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap); + , pmccadapriv->mcc_target_tx_bytes_to_port, pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap); } static void rtw_hal_clear_mcc_macid(PADAPTER padapter) { + u16 media_status_rpt; struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; switch (pmccadapriv->role) { case MCC_ROLE_STA: case MCC_ROLE_GC: - /* release mgmt queue macid */ - rtw_hal_set_FwMediaStatusRpt_single_cmd(padapter - , 0, 0, 0, H2C_MSR_ROLE_AP, pmccadapriv->mgmt_queue_macid); break; case MCC_ROLE_AP: case MCC_ROLE_GO: - /* nothing to do */ + /* nothing to do */ break; default: RTW_INFO("Unknown role\n"); @@ -235,7 +494,7 @@ static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength) u8 broadcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; /* frame type, length = 1*/ - SetFrameSubType(pframe, WIFI_RTS); + set_frame_sub_type(pframe, WIFI_RTS); /* frame control flag, length = 1 */ *(pframe + 1) = 0; @@ -247,13 +506,13 @@ static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength) /* frame recvaddr, length = 6 */ _rtw_memcpy((pframe + 4), broadcast_addr, ETH_ALEN); _rtw_memcpy((pframe + 4 + ETH_ALEN), adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy((pframe + 4 + ETH_ALEN * 2), adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy((pframe + 4 + ETH_ALEN*2), adapter_mac_addr(padapter), ETH_ALEN); *pLength = 22; } u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, - u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len, - RSVDPAGE_LOC *rsvd_page_loc) + u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len, + RSVDPAGE_LOC *rsvd_page_loc) { u32 len = 0; _adapter *iface = NULL; @@ -291,8 +550,8 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, _rtw_memcpy(bssid, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); rtw_hal_construct_NullFunctionData(iface , &pframe[*index], &len, bssid, _FALSE, 0, 0, _FALSE); - rtw_hal_fill_fake_txdesc(iface, &pframe[*index - tx_desc], - len, _FALSE, _FALSE, _FALSE); + rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc], + len, _FALSE, _FALSE, _FALSE); CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size); *page_num += CurtPktPageNum; @@ -306,8 +565,8 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, len = 0; rtw_hal_construct_CTS(iface, &pframe[*index], &len); - rtw_hal_fill_fake_txdesc(iface, &pframe[*index - tx_desc], - len, _FALSE, _FALSE, _FALSE); + rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc], + len, _FALSE, _FALSE, _FALSE); CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size); *page_num += CurtPktPageNum; @@ -315,7 +574,7 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, *total_pkt_len = *index + len; break; case MCC_ROLE_GO: - /* To DO */ + /* To DO */ break; } } @@ -346,7 +605,7 @@ static void rtw_hal_set_fw_mcc_rsvd_page(PADAPTER padapter) iface = pmccobjpriv->iface[i]; pmccadapriv = &iface->mcc_adapterpriv; if (pmccadapriv->role == MCC_ROLE_AP - || pmccadapriv->role == MCC_ROLE_GO) + || pmccadapriv->role == MCC_ROLE_GO) tx_beacon_hdl(iface, NULL); } } @@ -367,7 +626,7 @@ static void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter) order = iface->mcc_adapterpriv.order; if (order >= H2C_MCC_LOCATION_LEN) { RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n" - , FUNC_ADPT_ARG(padapter), order); + , FUNC_ADPT_ARG(padapter), order); continue; } @@ -390,11 +649,16 @@ static void rtw_hal_set_mcc_noa_cmd(PADAPTER padapter) { struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); u8 cmd[H2C_MCC_NOA_PARAM_LEN] = {0}; + u8 policy_idx = pmccobjpriv->policy_index; u8 noa_fw_eable = 1; - u8 noa_tsf_sync_offset = 50; - u8 noa_start_time = 30; - u8 noa_interval = pmlmepriv->cur_network.network.Configuration.BeaconPeriod; + u8 noa_tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX]; + u8 noa_start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX]; + u8 noa_interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX]; + u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX]; + u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX]; u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME; u8 i = 0; @@ -403,7 +667,7 @@ static void rtw_hal_set_mcc_noa_cmd(PADAPTER padapter) /* TSF Sync offset */ SET_H2CCMD_MCC_NOA_TSF_SYNC_OFFSET(cmd, noa_tsf_sync_offset); /* NoA start time offset */ - SET_H2CCMD_MCC_NOA_START_TIME(cmd, noa_start_time); + SET_H2CCMD_MCC_NOA_START_TIME(cmd, (noa_start_time_offset + guard_offset0)); /* NoA interval */ SET_H2CCMD_MCC_NOA_INTERVAL(cmd, noa_interval); /* Early time to inform driver by C2H before switch channel */ @@ -424,71 +688,79 @@ static void rtw_hal_set_mcc_noa_cmd(PADAPTER padapter) static void rtw_hal_set_mcc_IQK_offload_cmd(PADAPTER padapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); struct mcc_adapter_priv *pmccadapriv = NULL; _adapter *iface = NULL; u8 cmd[H2C_MCC_IQK_PARAM_LEN] = {0}, bready = 0, i = 0, order = 0; u16 TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0; + u8 total_rf_path = GET_HAL_DATA(padapter)->NumTotalRFPath; + u8 rf_path_idx = 0, last_order = MAX_MCC_NUM - 1, last_rf_path_index = total_rf_path - 1; + /* by order, last order & last_rf_path_index must set ready bit = 1 */ for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; + iface = pmccobjpriv->iface[i]; if (iface == NULL) continue; pmccadapriv = &iface->mcc_adapterpriv; order = pmccadapriv->order; - /* TO DO for multi-antenna(FW not support) */ - TX_X = pmccadapriv->mcc_iqk_arr[0].TX_X & 0x7ff;/* [10:0] */ - TX_Y = pmccadapriv->mcc_iqk_arr[0].TX_Y & 0x7ff;/* [10:0] */ - RX_X = pmccadapriv->mcc_iqk_arr[0].RX_X & 0x3ff;/* [9:0] */ - RX_Y = pmccadapriv->mcc_iqk_arr[0].RX_Y & 0x3ff;/* [9:0] */ - _rtw_memset(cmd, 0, H2C_MCC_IQK_PARAM_LEN); - - /* ready or not */ - if (order == 1) - bready = 1; - else - bready = 0; - - SET_H2CCMD_MCC_IQK_READY(cmd, bready); - SET_H2CCMD_MCC_IQK_ORDER(cmd, order); - - /* fill RX_X[7:0] to (cmd+1)[7:0] bitlen=8 */ - SET_H2CCMD_MCC_IQK_RX_L(cmd, (u8)(RX_X & 0xff)); - /* fill RX_X[9:8] to (cmd+2)[1:0] bitlen=2 */ - SET_H2CCMD_MCC_IQK_RX_M1(cmd, (u8)((RX_X >> 8) & 0x03)); - /* fill RX_Y[5:0] to (cmd+2)[7:2] bitlen=6 */ - SET_H2CCMD_MCC_IQK_RX_M2(cmd, (u8)(RX_Y & 0x3f)); - /* fill RX_Y[9:6] to (cmd+3)[3:0] bitlen=4 */ - SET_H2CCMD_MCC_IQK_RX_H(cmd, (u8)((RX_Y >> 6) & 0x0f)); - - - /* fill TX_X[7:0] to (cmd+4)[7:0] bitlen=8 */ - SET_H2CCMD_MCC_IQK_TX_L(cmd, (u8)(TX_X & 0xff)); - /* fill TX_X[10:8] to (cmd+5)[2:0] bitlen=3 */ - SET_H2CCMD_MCC_IQK_TX_M1(cmd, (u8)((TX_X >> 8) & 0x07)); - /* fill TX_Y[4:0] to (cmd+5)[7:3] bitlen=5 */ - SET_H2CCMD_MCC_IQK_TX_M2(cmd, (u8)(TX_Y & 0x1f)); - /* fill TX_Y[10:5] to (cmd+6)[5:0] bitlen=6 */ - SET_H2CCMD_MCC_IQK_TX_H(cmd, (u8)((TX_Y >> 5) & 0x3f)); + + for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx ++) { + + _rtw_memset(cmd, 0, H2C_MCC_IQK_PARAM_LEN); + TX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_X & 0x7ff;/* [10:0] */ + TX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_Y & 0x7ff;/* [10:0] */ + RX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_X & 0x3ff;/* [9:0] */ + RX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_Y & 0x3ff;/* [9:0] */ + + /* ready or not */ + if (order == last_order && rf_path_idx == last_rf_path_index) + bready = 1; + else + bready = 0; + + SET_H2CCMD_MCC_IQK_READY(cmd, bready); + SET_H2CCMD_MCC_IQK_ORDER(cmd, order); + SET_H2CCMD_MCC_IQK_PATH(cmd, rf_path_idx); + + /* fill RX_X[7:0] to (cmd+1)[7:0] bitlen=8 */ + SET_H2CCMD_MCC_IQK_RX_L(cmd, (u8)(RX_X & 0xff)); + /* fill RX_X[9:8] to (cmd+2)[1:0] bitlen=2 */ + SET_H2CCMD_MCC_IQK_RX_M1(cmd, (u8)((RX_X >> 8) & 0x03)); + /* fill RX_Y[5:0] to (cmd+2)[7:2] bitlen=6 */ + SET_H2CCMD_MCC_IQK_RX_M2(cmd, (u8)(RX_Y & 0x3f)); + /* fill RX_Y[9:6] to (cmd+3)[3:0] bitlen=4 */ + SET_H2CCMD_MCC_IQK_RX_H(cmd, (u8)((RX_Y >> 6) & 0x0f)); + + + /* fill TX_X[7:0] to (cmd+4)[7:0] bitlen=8 */ + SET_H2CCMD_MCC_IQK_TX_L(cmd, (u8)(TX_X & 0xff)); + /* fill TX_X[10:8] to (cmd+5)[2:0] bitlen=3 */ + SET_H2CCMD_MCC_IQK_TX_M1(cmd, (u8)((TX_X >> 8) & 0x07)); + /* fill TX_Y[4:0] to (cmd+5)[7:3] bitlen=5 */ + SET_H2CCMD_MCC_IQK_TX_M2(cmd, (u8)(TX_Y & 0x1f)); + /* fill TX_Y[10:5] to (cmd+6)[5:0] bitlen=6 */ + SET_H2CCMD_MCC_IQK_TX_H(cmd, (u8)((TX_Y >> 5) & 0x3f)); #ifdef CONFIG_MCC_MODE_DEBUG - RTW_INFO("=========================\n"); - RTW_INFO(FUNC_ADPT_FMT" IQK:\n", FUNC_ADPT_ARG(iface)); - RTW_INFO("TX_X: 0x%02x\n", TX_X); - RTW_INFO("TX_Y: 0x%02x\n", TX_Y); - RTW_INFO("RX_X: 0x%02x\n", RX_X); - RTW_INFO("RX_Y: 0x%02x\n", RX_Y); - RTW_INFO("cmd[0]:0x%02x\n", cmd[0]); - RTW_INFO("cmd[1]:0x%02x\n", cmd[1]); - RTW_INFO("cmd[2]:0x%02x\n", cmd[2]); - RTW_INFO("cmd[3]:0x%02x\n", cmd[3]); - RTW_INFO("cmd[4]:0x%02x\n", cmd[4]); - RTW_INFO("cmd[5]:0x%02x\n", cmd[5]); - RTW_INFO("cmd[6]:0x%02x\n", cmd[6]); - RTW_INFO("=========================\n"); + RTW_INFO("=========================\n"); + RTW_INFO(FUNC_ADPT_FMT" IQK:\n", FUNC_ADPT_ARG(iface)); + RTW_INFO("TX_X: 0x%02x\n", TX_X); + RTW_INFO("TX_Y: 0x%02x\n", TX_Y); + RTW_INFO("RX_X: 0x%02x\n", RX_X); + RTW_INFO("RX_Y: 0x%02x\n", RX_Y); + RTW_INFO("cmd[0]:0x%02x\n", cmd[0]); + RTW_INFO("cmd[1]:0x%02x\n", cmd[1]); + RTW_INFO("cmd[2]:0x%02x\n", cmd[2]); + RTW_INFO("cmd[3]:0x%02x\n", cmd[3]); + RTW_INFO("cmd[4]:0x%02x\n", cmd[4]); + RTW_INFO("cmd[5]:0x%02x\n", cmd[5]); + RTW_INFO("cmd[6]:0x%02x\n", cmd[6]); + RTW_INFO("=========================\n"); #endif /* CONFIG_MCC_MODE_DEBUG */ - rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_IQK_PARAM, H2C_MCC_IQK_PARAM_LEN, cmd); + rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_IQK_PARAM, H2C_MCC_IQK_PARAM_LEN, cmd); + } } } @@ -510,9 +782,9 @@ static void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter) order = pmccadapriv->order; bitmap = pmccadapriv->mcc_macid_bitmap; - if (order >= (H2C_MCC_MACID_BITMAP_LEN / 2)) { + if (order >= (H2C_MCC_MACID_BITMAP_LEN/2)) { RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n" - , FUNC_ADPT_ARG(padapter), order); + , FUNC_ADPT_ARG(padapter), order); continue; } SET_H2CCMD_MCC_MACID_BITMAP_L((cmd + order * 2), (u8)(bitmap & 0xff)); @@ -530,9 +802,9 @@ static void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter) rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_MACID_BITMAP, H2C_MCC_MACID_BITMAP_LEN, cmd); } -static void rtw_hal_set_mcc_parameter_cmd(PADAPTER padapter, u8 stop) +static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop) { - u8 cmd[H2C_MCC_INFO_LEN] = {0}, i = 0; + u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0; u8 order = 0, totalnum = 0, chidx = 0, bw = 0, bw40sc = 0, bw80sc = 0; u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0, chscan = 0; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); @@ -585,7 +857,7 @@ static void rtw_hal_set_mcc_parameter_cmd(PADAPTER padapter, u8 stop) incurch = _FALSE; if (IS_HARDWARE_TYPE_8812(padapter)) - rfetype = pHalData->RFEType; /* RFETYPE (only for 8812)*/ + rfetype = pHalData->rfe_type; /* RFETYPE (only for 8812)*/ else rfetype = 0; @@ -604,19 +876,19 @@ static void rtw_hal_set_mcc_parameter_cmd(PADAPTER padapter, u8 stop) c2hrpt = MCC_C2H_REPORT_ALL_STATUS; chscan = MCC_CHIDX; - SET_H2CCMD_MCC_INFO_ORDER(cmd, order); - SET_H2CCMD_MCC_INFO_TOTALNUM(cmd, totalnum); - SET_H2CCMD_MCC_INFO_CHIDX(cmd, chidx); - SET_H2CCMD_MCC_INFO_BW(cmd, bw); - SET_H2CCMD_MCC_INFO_BW40SC(cmd, bw40sc); - SET_H2CCMD_MCC_INFO_BW80SC(cmd, bw80sc); - SET_H2CCMD_MCC_INFO_DURATION(cmd, duration); - SET_H2CCMD_MCC_INFO_ROLE(cmd, role); - SET_H2CCMD_MCC_INFO_INCURCH(cmd, incurch); - SET_H2CCMD_MCC_INFO_RFETYPE(cmd, rfetype); - SET_H2CCMD_MCC_INFO_DISTXNULL(cmd, distxnull); - SET_H2CCMD_MCC_INFO_C2HRPT(cmd, c2hrpt); - SET_H2CCMD_MCC_INFO_CHSCAN(cmd, chscan); + SET_H2CCMD_MCC_CTRL_ORDER(cmd, order); + SET_H2CCMD_MCC_CTRL_TOTALNUM(cmd, totalnum); + SET_H2CCMD_MCC_CTRL_CHIDX(cmd, chidx); + SET_H2CCMD_MCC_CTRL_BW(cmd, bw); + SET_H2CCMD_MCC_CTRL_BW40SC(cmd, bw40sc); + SET_H2CCMD_MCC_CTRL_BW80SC(cmd, bw80sc); + SET_H2CCMD_MCC_CTRL_DURATION(cmd, duration); + SET_H2CCMD_MCC_CTRL_ROLE(cmd, role); + SET_H2CCMD_MCC_CTRL_INCURCH(cmd, incurch); + SET_H2CCMD_MCC_CTRL_RFETYPE(cmd, rfetype); + SET_H2CCMD_MCC_CTRL_DISTXNULL(cmd, distxnull); + SET_H2CCMD_MCC_CTRL_C2HRPT(cmd, c2hrpt); + SET_H2CCMD_MCC_CTRL_CHSCAN(cmd, chscan); #ifdef CONFIG_MCC_MODE_DEBUG RTW_INFO("=========================\n"); @@ -631,7 +903,7 @@ static void rtw_hal_set_mcc_parameter_cmd(PADAPTER padapter, u8 stop) RTW_INFO("=========================\n"); #endif /* CONFIG_MCC_MODE_DEBUG */ - rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_INFO, H2C_MCC_INFO_LEN, cmd); + rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL, H2C_MCC_CTRL_LEN, cmd); } } @@ -653,6 +925,9 @@ static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status) goto exit; } + /* configure mcc switch channel setting */ + rtw_hal_config_mcc_switch_channel_setting(padapter); + if (rtw_hal_decide_mcc_role(padapter) == _FAIL) { ret = _FAIL; goto exit; @@ -677,8 +952,8 @@ static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status) /* set mac id to fw */ rtw_hal_set_mcc_macid_cmd(padapter); - /* set mcc parameter */ - rtw_hal_set_mcc_parameter_cmd(padapter, _FALSE); + /* set mcc parameter */ + rtw_hal_set_mcc_ctrl_cmd(padapter, _FALSE); exit: return ret; @@ -703,7 +978,7 @@ static void rtw_hal_set_mcc_stop_setting(PADAPTER padapter, u8 status) continue; /* use other interface to set cmd */ if (iface != padapter) { - rtw_hal_set_mcc_parameter_cmd(iface, _TRUE); + rtw_hal_set_mcc_ctrl_cmd(iface, _TRUE); break; } } @@ -747,6 +1022,9 @@ static void rtw_hal_mcc_stop_posthdl(PADAPTER padapter) iface->mcc_adapterpriv.mcc_tx_bytes_from_kernel = 0; iface->mcc_adapterpriv.mcc_last_tx_bytes_from_kernel = 0; iface->mcc_adapterpriv.mcc_tx_bytes_to_port = 0; + + if (iface->mcc_adapterpriv.role == MCC_ROLE_GO) + rtw_hal_mcc_remove_go_p2p_ie(iface); } } @@ -785,8 +1063,6 @@ static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status) pmccobjpriv->mcc_c2h_status = MCC_RPT_MAX; if (stop == _FALSE) { - pmccobjpriv->duration = MCC_DURATION; - /* handle mcc start */ if (rtw_hal_set_mcc_start_setting(padapter, status) == _FAIL) goto exit; @@ -854,7 +1130,7 @@ static void rtw_hal_mcc_check_case_not_limit_traffic(PADAPTER cur_iface, PADAPTE static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter) { struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); + struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv); struct mcc_adapter_priv *cur_mccadapriv = NULL, *next_mccadapriv = NULL; _adapter *iface = NULL, *cur_iface = NULL, *next_iface = NULL; struct registry_priv *preg = &padapter->registrypriv; @@ -937,6 +1213,48 @@ static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter) } } +static void rtw_hal_mcc_update_noa_start_time_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv); + struct mcc_adapter_priv *pmccadapriv = NULL; + PADAPTER iface = NULL; + u8 i = 0; + u8 policy_idx = pmccobjpriv->policy_index; + u8 noa_tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX]; + u8 noa_start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX]; + + for (i = 0; i < pdvobjpriv->iface_nums; i++) { + iface = pdvobjpriv->padapters[i]; + if (iface == NULL) + continue; + + pmccadapriv = &iface->mcc_adapterpriv; + /* GO & channel match */ + if (pmccadapriv->role == MCC_ROLE_GO) { + /* convert GO TBTT from FW to noa_start_time(TU convert to mircosecond) */ + pmccadapriv->noa_start_time = RTW_GET_LE32(tmpBuf + 2) + noa_start_time_offset * TU; + + if (0) { + RTW_INFO("TBTT:0x%02x\n", RTW_GET_LE32(tmpBuf + 2)); + RTW_INFO("noa_tsf_sync_offset:%d, noa_start_time_offset:%d\n", noa_tsf_sync_offset, noa_start_time_offset); + RTW_INFO(FUNC_ADPT_FMT"buf=0x%02x:0x%02x:0x%02x:0x%02x, noa_start_time=0x%02x\n" + , FUNC_ADPT_ARG(iface) + , tmpBuf[2] + , tmpBuf[3] + , tmpBuf[4] + , tmpBuf[5] + ,pmccadapriv->noa_start_time); + } + + rtw_hal_mcc_update_go_p2p_ie(iface); + + break; + } + } + +} + /** * rtw_hal_mcc_c2h_handler - mcc c2h handler */ @@ -988,6 +1306,9 @@ void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf) pdvobjpriv->oper_channel = tmpBuf[1]; rtw_hal_mcc_sw_ch_fw_notify_hdl(padapter); break; + case MCC_RPT_UPDATE_NOA_START_TIME: + rtw_hal_mcc_update_noa_start_time_hdl(padapter, buflen, tmpBuf); + break; default: /* RTW_INFO("[MCC] Other MCC status(%d)\n", pmccobjpriv->mcc_c2h_status); */ break; @@ -1007,7 +1328,7 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter) u8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL; _irqL irqL; - /* #define MCC_RESTART 1 */ +/* #define MCC_RESTART 1 */ if (!MCC_EN(padapter)) return; @@ -1049,10 +1370,10 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter) if (check_ret != _SUCCESS) { RTW_INFO("============ MCC swich channel check fail (%d)=============\n", diff_cnt); /* restart MCC */ -#ifdef MCC_RESTART - rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_DISCONNECT); - rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT); -#endif /* MCC_RESTART */ + #ifdef MCC_RESTART + rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_DISCONNECT); + rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT); + #endif /* MCC_RESTART */ } } else { _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL); @@ -1090,7 +1411,7 @@ u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset) for (i = 0; i < dvobj->iface_nums; i++) { if (!dvobj->padapters[i]) - continue; + continue; pmlmeext = &dvobj->padapters[i]->mlmeextpriv; pmccadapriv = &dvobj->padapters[i]->mcc_adapterpriv; @@ -1160,11 +1481,11 @@ inline void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len) if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) pmccadapriv->mcc_tx_bytes_to_port += len; - if (0) - RTW_INFO("%s(order:%d): mcc tx bytes to port:%d, mcc target tx bytes to port:%d\n" - , __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_to_port - , pmccadapriv->mcc_target_tx_bytes_to_port); - } + if (0) + RTW_INFO("%s(order:%d): mcc tx bytes to port:%d, mcc target tx bytes to port:%d\n" + , __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_to_port + , pmccadapriv->mcc_target_tx_bytes_to_port); + } } /** @@ -1232,7 +1553,7 @@ u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter) _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) - ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_SCAN_DONE); + ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_SCAN_DONE); _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); } @@ -1253,14 +1574,14 @@ u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_allow) if (MCC_EN(padapter)) { /* channel bw offset can not be allowed, start MCC */ if (chbw_allow == _FALSE) { - struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); + struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); - rtw_hal_mcc_backup_IQK_val(padapter); - _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); - ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT); - _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); + rtw_hal_mcc_restore_iqk_val(padapter); + _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); + ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT); + _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); + } } - } return ret; } @@ -1296,11 +1617,11 @@ u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter) u8 ret = _FAIL; if (MCC_EN(padapter)) { - u8 sta_num = 0, ld_sta_num = 0, lg_sta_num = 0, ap_num = 0, ld_ap_num = 0; + struct mi_state mstate; - rtw_mi_status_no_self(padapter, &sta_num, &ld_sta_num, &lg_sta_num, &ap_num, &ld_ap_num, NULL); + rtw_mi_status_no_self(padapter, &mstate); - if (ld_sta_num || lg_sta_num || ap_num) { + if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_STA_LG_NUM(&mstate) || MSTATE_AP_NUM(&mstate)) { bool chbw_allow = _TRUE; u8 u_ch, u_offset, u_bw; struct mlme_ext_priv *cur_mlmeext = &padapter->mlmeextpriv; @@ -1310,22 +1631,23 @@ u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter) dump_adapters_status(RTW_DBGDUMP , dvobj); rtw_warn_on(1); } + RTW_INFO(FUNC_ADPT_FMT" union no self: %u,%u,%u\n" , FUNC_ADPT_ARG(padapter), u_ch, u_bw, u_offset); /* chbw_allow? */ chbw_allow = rtw_is_chbw_grouped(cur_mlmeext->cur_channel , cur_mlmeext->cur_bwmode, cur_mlmeext->cur_ch_offset - , u_ch, u_bw, u_offset); + , u_ch, u_bw, u_offset); RTW_INFO(FUNC_ADPT_FMT" chbw_allow:%d\n" - , FUNC_ADPT_ARG(padapter), chbw_allow); + , FUNC_ADPT_ARG(padapter), chbw_allow); /* if chbw_allow = false, start MCC setting */ if (chbw_allow == _FALSE) { struct mcc_obj_priv *pmccobjpriv = &dvobj->mcc_objpriv; - rtw_hal_mcc_backup_IQK_val(padapter); + rtw_hal_mcc_restore_iqk_val(padapter); _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT); _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); @@ -1348,7 +1670,7 @@ u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw { u8 ret = _FAIL; - /* if chbw_allow = false under en_mcc = TRUE, we do not change channel related setting */ + /* if chbw_allow = false under en_mcc = TRUE, we do not change channel related setting */ if (MCC_EN(padapter)) { /* restore union channel related setting to current channel related setting */ if (chbw_allow == _FALSE) { @@ -1360,7 +1682,7 @@ u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw RTW_INFO(FUNC_ADPT_FMT" en_mcc:%d(%d,%d,%d,)\n" , FUNC_ADPT_ARG(padapter), padapter->registrypriv.en_mcc - , *ch, *bw, *offset); + , *ch, *bw, *offset); ret = _SUCCESS; } } @@ -1368,6 +1690,23 @@ u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw return ret; } +static void rtw_hal_mcc_dump_noa_content(void *sel, PADAPTER padapter) +{ + struct mcc_adapter_priv *pmccadapriv = NULL; + u8 *pos = NULL; + pmccadapriv = &padapter->mcc_adapterpriv; + /* last position for NoA attribute */ + pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len; + + + RTW_PRINT_SEL(sel, "\nStart to dump NoA Content\n"); + RTW_PRINT_SEL(sel, "NoA Counts:%d\n", *(pos - 13)); + RTW_PRINT_SEL(sel, "NoA Duration(TU):%d\n", (RTW_GET_LE32(pos - 12))/TU); + RTW_PRINT_SEL(sel, "NoA Interval(TU):%d\n", (RTW_GET_LE32(pos - 8))/TU); + RTW_PRINT_SEL(sel, "NoA Start time(microseconds):0x%02x\n", RTW_GET_LE32(pos - 4)); + RTW_PRINT_SEL(sel, "End to dump NoA Content\n"); +} + void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj) { struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); @@ -1405,10 +1744,14 @@ void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj) RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M ):%d Mbps\n", regpriv->rtw_mcc_sta_bw40_target_tx_tp); RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_sta_bw80_target_tx_tp); RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", regpriv->rtw_mcc_single_tx_cri); + if (MLME_IS_GO(iface)) + rtw_hal_mcc_dump_noa_content(sel, iface); RTW_PRINT_SEL(sel, "**********************************************\n"); } } RTW_PRINT_SEL(sel, "------------------------------------------\n"); + RTW_PRINT_SEL(sel, "policy index:%d\n", pmccobjpriv->policy_index); + RTW_PRINT_SEL(sel, "------------------------------------------\n"); RTW_PRINT_SEL(sel, "define data:\n"); RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", MCC_AP_BW20_TARGET_TX_TP); RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", MCC_AP_BW40_TARGET_TX_TP); @@ -1446,9 +1789,9 @@ inline u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg) iface = dvobj->padapters[i]; mlmeext = &iface->mlmeextpriv; if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE) { -#ifdef DBG_EXPIRATION_CHK - RTW_INFO(FUNC_ADPT_FMT" don't enter %s under scan for MCC mode\n", FUNC_ADPT_ARG(padapter), msg); -#endif + #ifdef DBG_EXPIRATION_CHK + RTW_INFO(FUNC_ADPT_FMT" don't enter %s under scan for MCC mode\n", FUNC_ADPT_ARG(padapter), msg); + #endif ret = _FALSE; goto exit; } @@ -1467,24 +1810,64 @@ void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode) u32 start = rtw_get_current_time(); u8 i = 0; - if (MCC_EN(padapter)) { - if (chbw_allow == _FALSE) { - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - /* issue null data to inform ap station will leave */ - if (is_client_associated_to_ap(iface)) { - struct mlme_ext_priv *mlmeext = &iface->mlmeextpriv; - u8 ch = mlmeext->cur_channel; - u8 bw = mlmeext->cur_bwmode; - u8 offset = mlmeext->cur_ch_offset; - - set_channel_bwmode(iface, ch, bw, offset); - issue_nulldata(iface, NULL, ps_mode, 3, 50); - } - } - RTW_INFO("%s(%d ms)\n", __func__, rtw_get_passing_time_ms(start)); + if (!MCC_EN(padapter)) + return; + + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + return; + + if (chbw_allow == _TRUE) + return; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + /* issue null data to inform ap station will leave */ + if (is_client_associated_to_ap(iface)) { + struct mlme_ext_priv *mlmeext = &iface->mlmeextpriv; + u8 ch = mlmeext->cur_channel; + u8 bw = mlmeext->cur_bwmode; + u8 offset = mlmeext->cur_ch_offset; + + set_channel_bwmode(iface, ch, bw, offset); + issue_nulldata(iface, NULL, ps_mode, 3, 50); } } + RTW_INFO("%s(%d ms)\n", __func__, rtw_get_passing_time_ms(start)); +} + +u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len) +{ + struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + + if (!MCC_EN(padapter)) + return pframe; + + if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + return pframe; + + if (pmccadapriv->p2p_go_noa_ie_len == 0) + return pframe; + + _rtw_memcpy(pframe, pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len); + *len = *len + pmccadapriv->p2p_go_noa_ie_len; + + return pframe + pmccadapriv->p2p_go_noa_ie_len; +} + +void rtw_hal_dump_mcc_policy_table(void *sel) +{ + u8 idx = 0; + RTW_PRINT_SEL(sel, "duration\t,tsf sync offset\t,start time offset\t,interval\t,guard offset0\t,guard offset1\n"); + + for (idx = 0; idx < mcc_max_policy_num; idx ++) { + RTW_PRINT_SEL(sel, "%d\t\t,%d\t\t\t,%d\t\t\t,%d\t\t,%d\t\t,%d\n" + , mcc_switch_channel_policy_table[idx][MCC_DURATION_IDX] + , mcc_switch_channel_policy_table[idx][MCC_TSF_SYNC_OFFSET_IDX] + , mcc_switch_channel_policy_table[idx][MCC_START_TIME_OFFSET_IDX] + , mcc_switch_channel_policy_table[idx][MCC_INTERVAL_IDX] + , mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET0_IDX] + , mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET1_IDX]); + } } #endif /* CONFIG_MCC_MODE */ diff --git a/hal/hal_mp.c b/hal/hal_mp.c index 16fdd7f..1cc498a 100644 --- a/hal/hal_mp.c +++ b/hal/hal_mp.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_MP_C_ #include @@ -75,57 +70,55 @@ u8 MgntQuery_NssTxRate(u16 Rate) void hal_mpt_SwitchRfSetting(PADAPTER pAdapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); u8 ChannelToSw = pMptCtx->MptChannelToSw; - ULONG ulRateIdx = pMptCtx->MptRateIndex; + ULONG ulRateIdx = pMptCtx->mpt_rate_index; ULONG ulbandwidth = pMptCtx->MptBandWidth; /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/ if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) && (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) { - pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0); - pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0); + pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0); + pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0); if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) { - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); } else { - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD); } } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/ if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) { - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ } else { - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ } } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) { - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B); } } s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); if (!netif_running(padapter->pnetdev)) { - RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n")); return _FAIL; } if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { - RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n")); return _FAIL; } if (enable) - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; + pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE; else - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE; + pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE; return _SUCCESS; } @@ -133,10 +126,10 @@ s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable) void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); - *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl; + *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control; } @@ -146,20 +139,16 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12; u8 i; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - u1Byte u1Channel = pHalData->CurrentChannel; - ULONG ulRateIdx = pMptCtx->MptRateIndex; + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); + u1Byte u1Channel = pHalData->current_channel; + ULONG ulRateIdx = pMptCtx->mpt_rate_index; u1Byte DataRate = 0xFF; - /* Suggested by BB David. 2015.04.27*/ - if(IS_HARDWARE_TYPE_8188F(Adapter)) - return; - /* Do not modify CCK TX filter parameters for 8822B*/ if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter)) return; - DataRate = MptToMgntRate(ulRateIdx); + DataRate = mpt_to_mgnt_rate(ulRateIdx); if (u1Channel == 14 && IS_CCK_RATE(DataRate)) pHalData->bCCKinCH14 = TRUE; @@ -169,33 +158,89 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) if (IS_HARDWARE_TYPE_8703B(Adapter)) { if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) { /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */ - PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0); - PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskLWord, 0); + phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0); + phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0); - RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B CCK in Channel %u\n", u1Channel)); } else { /* Normal setting for 8703B, just recover to the default setting. */ /* This hardcore values reference from the parameter which BB team gave. */ for (i = 0 ; i < 2 ; ++i) - PHY_SetBBReg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value); + phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value); - RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B in Channel %u restore to default setting\n", u1Channel)); } } else if (IS_HARDWARE_TYPE_8723D(Adapter)) { /* 2.4G CCK TX DFIR */ /* 2016.01.20 Suggest from RS BB mingzhi*/ if ((u1Channel == 14)) { - PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C); - PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000); - PHY_SetBBReg(Adapter, 0xAAC, bMaskDWord, 0x00003667); + phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C); + phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000); + phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667); } else { for (i = 0 ; i < 3 ; ++i) { - PHY_SetBBReg(Adapter, + phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value); } } + } else if (IS_HARDWARE_TYPE_8188F(Adapter)) { + /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/ + CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord); + CCKSwingIndex = 20; /* default index */ + + if (!pHalData->bCCKinCH14) { + /* Readback the current bb cck swing value and compare with the table to */ + /* get the current swing index */ + for (i = 0; i < CCK_TABLE_SIZE_88F; i++) { + if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) && + (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) { + CCKSwingIndex = i; + break; + } + } + write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]); + write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]); + write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]); + write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]); + write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]); + write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]); + write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]); + write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]); + write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]); + write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]); + write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]); + write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]); + write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]); + write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]); + write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]); + write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]); + RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex); + } else { + for (i = 0; i < CCK_TABLE_SIZE_88F; i++) { + if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) && + (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) { + CCKSwingIndex = i; + break; + } + } + write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]); + write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]); + write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]); + write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]); + write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]); + write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]); + write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]); + write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]); + write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]); + write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]); + write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]); + write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]); + write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]); + write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]); + write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]); + write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]); + RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex); + } } else { /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/ @@ -205,57 +250,53 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) /* Readback the current bb cck swing value and compare with the table to */ /* get the current swing index */ for (i = 0; i < CCK_TABLE_SIZE; i++) { - if (((CurrCCKSwingVal & 0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) && - (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) { + if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) && + (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) { CCKSwingIndex = i; - RT_TRACE(_module_mp_, DBG_LOUD, ("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n", - (rCCK0_TxFilter1 + 2), CurrCCKSwingVal, CCKSwingIndex)); break; } } /*Write 0xa22 0xa23*/ - TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] + - (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1] << 8); + TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] + + (cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8); /*Write 0xa24 ~ 0xa27*/ TempVal2 = 0; - TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] + - (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3] << 8) + - (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4] << 16) + - (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5] << 24); + TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] + + (cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) + + (cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) + + (cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24); /*Write 0xa28 0xa29*/ TempVal3 = 0; - TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] + - (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7] << 8); + TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] + + (cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8); } else { for (i = 0; i < CCK_TABLE_SIZE; i++) { - if (((CurrCCKSwingVal & 0xff) == (u32)CCKSwingTable_Ch14[i][0]) && - (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)CCKSwingTable_Ch14[i][1])) { + if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) && + (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) { CCKSwingIndex = i; - RT_TRACE(_module_mp_, DBG_LOUD, ("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n", - (rCCK0_TxFilter1 + 2), CurrCCKSwingVal, CCKSwingIndex)); break; } } /*Write 0xa22 0xa23*/ - TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] + - (CCKSwingTable_Ch14[CCKSwingIndex][1] << 8); + TempVal = cck_swing_table_ch14[CCKSwingIndex][0] + + (cck_swing_table_ch14[CCKSwingIndex][1] << 8); /*Write 0xa24 ~ 0xa27*/ TempVal2 = 0; - TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] + - (CCKSwingTable_Ch14[CCKSwingIndex][3] << 8) + - (CCKSwingTable_Ch14[CCKSwingIndex][4] << 16) + - (CCKSwingTable_Ch14[CCKSwingIndex][5] << 24); + TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] + + (cck_swing_table_ch14[CCKSwingIndex][3] << 8) + + (cck_swing_table_ch14[CCKSwingIndex][4] << 16) + + (cck_swing_table_ch14[CCKSwingIndex][5] << 24); /*Write 0xa28 0xa29*/ TempVal3 = 0; - TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] + - (CCKSwingTable_Ch14[CCKSwingIndex][7] << 8); + TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] + + (cck_swing_table_ch14[CCKSwingIndex][7] << 8); } write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal); @@ -269,15 +310,13 @@ void hal_mpt_SetChannel(PADAPTER pAdapter) { u8 eRFPath; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); struct mp_priv *pmp = &pAdapter->mppriv; u8 channel = pmp->channel; u8 bandwidth = pmp->bandwidth; hal_mpt_SwitchRfSetting(pAdapter); - SelectChannel(pAdapter, channel); - pHalData->bSwChnl = _TRUE; pHalData->bSetChnlBW = _TRUE; rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); @@ -298,7 +337,6 @@ void hal_mpt_SetBandwidth(PADAPTER pAdapter) u8 channel = pmp->channel; u8 bandwidth = pmp->bandwidth; - SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset); pHalData->bSwChnl = _TRUE; pHalData->bSetChnlBW = _TRUE; rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); @@ -308,7 +346,6 @@ void hal_mpt_SetBandwidth(PADAPTER pAdapter) void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower) { - RT_TRACE(_module_mp_, DBG_LOUD, ("===>mpt_SetTxPower_Old(): Case = %d\n", Rate)); switch (Rate) { case MPT_CCK: { u4Byte TxAGC = 0, pwr = 0; @@ -317,14 +354,14 @@ void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower) pwr = pTxPower[ODM_RF_PATH_A]; if (pwr < 0x3f) { TxAGC = (pwr << 16) | (pwr << 8) | (pwr); - PHY_SetBBReg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]); - PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]); + phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); } pwr = pTxPower[ODM_RF_PATH_B]; if (pwr < 0x3f) { TxAGC = (pwr << 16) | (pwr << 8) | (pwr); - PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]); - PHY_SetBBReg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]); + phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC); } } break; @@ -337,24 +374,24 @@ void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower) if (pwr < 0x3f) { TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC); - PHY_SetBBReg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); } TxAGC = 0; pwr = pTxPower[1]; if (pwr < 0x3f) { TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC); - PHY_SetBBReg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); - PHY_SetBBReg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); - PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); - PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); - PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); - PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); } } break; @@ -463,8 +500,8 @@ mpt_SetTxPower( void hal_mpt_SetTxPower(PADAPTER pAdapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; if (pHalData->rf_chip < RF_TYPE_MAX) { if (IS_HARDWARE_TYPE_8188E(pAdapter) || @@ -472,11 +509,10 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter) IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) { - u8 path = (pHalData->AntennaTxPath == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B); + u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B); RTW_INFO("===> MPT_ProSetTxPower: Old\n"); - RT_TRACE(_module_mp_, DBG_LOUD, ("===> MPT_ProSetTxPower[Old]:\n")); mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel); mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel); @@ -491,16 +527,16 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter) } else RTW_INFO("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip); - ODM_ClearTxPowerTrackingState(pDM_Odm); + odm_clear_txpowertracking_state(pDM_Odm); } void hal_mpt_SetDataRate(PADAPTER pAdapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); u32 DataRate; - DataRate = MptToMgntRate(pMptCtx->MptRateIndex); + DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index); hal_mpt_SwitchRfSetting(pAdapter); @@ -508,24 +544,24 @@ void hal_mpt_SetDataRate(PADAPTER pAdapter) #ifdef CONFIG_RTL8723B if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) { if (IS_CCK_RATE(DataRate)) { - if (pMptCtx->MptRfPath == ODM_RF_PATH_A) - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6); + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6); else - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6); } else { - if (pMptCtx->MptRfPath == ODM_RF_PATH_A) - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE); + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE); else - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE); } } if ((IS_HARDWARE_TYPE_8723BS(pAdapter) && ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) { - if (pMptCtx->MptRfPath == ODM_RF_PATH_A) - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE); + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE); else - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE); } #endif } @@ -554,9 +590,9 @@ VOID mpt_ToggleIG_8814A(PADAPTER pAdapter) break; } - IGvalue = PHY_QueryBBReg(pAdapter, IGReg, bMaskByte0); - PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue + 2); - PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue); + IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0); + phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2); + phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue); } } @@ -564,15 +600,15 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; + PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx; R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */ R_ANTENNA_SELECT_CCK *p_cck_txrx; - u8 ForcedDataRate = MptToMgntRate(pMptCtx->MptRateIndex); + u8 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index); u8 HtStbcCap = pAdapter->registrypriv.stbc_cap; /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/ /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/ - u32 ulAntennaTx = pHalData->AntennaTxPath; + u32 ulAntennaTx = pHalData->antenna_tx_path; u32 ulAntennaRx = pHalData->AntennaRxPath; u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate); @@ -581,21 +617,21 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) switch (ulAntennaTx) { case ANTENNA_BC: - pMptCtx->MptRfPath = ODM_RF_PATH_BC; + pMptCtx->mpt_rf_path = ODM_RF_PATH_BC; /*pHalData->ValidTxPath = 0x06; linux no use */ - PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x106); /*/ 0x940[15:4]=12'b0000_0100_0011*/ + phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x106); /*/ 0x940[15:4]=12'b0000_0100_0011*/ break; case ANTENNA_CD: - pMptCtx->MptRfPath = ODM_RF_PATH_CD; + pMptCtx->mpt_rf_path = ODM_RF_PATH_CD; /*pHalData->ValidTxPath = 0x0C;*/ - PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x40c); /*/ 0x940[15:4]=12'b0000_0100_0011*/ + phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x40c); /*/ 0x940[15:4]=12'b0000_0100_0011*/ break; case ANTENNA_AB: default: - pMptCtx->MptRfPath = ODM_RF_PATH_AB; + pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; /*pHalData->ValidTxPath = 0x03;*/ - PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x043); /*/ 0x940[15:4]=12'b0000_0100_0011*/ + phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x043); /*/ 0x940[15:4]=12'b0000_0100_0011*/ break; } @@ -604,16 +640,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) switch (ulAntennaTx) { case ANTENNA_BCD: - pMptCtx->MptRfPath = ODM_RF_PATH_BCD; + pMptCtx->mpt_rf_path = ODM_RF_PATH_BCD; /*pHalData->ValidTxPath = 0x0e;*/ - PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/ + phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/ break; case ANTENNA_ABC: default: - pMptCtx->MptRfPath = ODM_RF_PATH_ABC; + pMptCtx->mpt_rf_path = ODM_RF_PATH_ABC; /*pHalData->ValidTxPath = 0x0d;*/ - PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/ + phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/ break; } @@ -621,51 +657,51 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) RTW_INFO("===> SetAntenna 1T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); switch (ulAntennaTx) { case ANTENNA_BCD: - pMptCtx->MptRfPath = ODM_RF_PATH_BCD; + pMptCtx->mpt_rf_path = ODM_RF_PATH_BCD; /*pHalData->ValidTxPath = 0x0e;*/ - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7); - PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe); - PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe); + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7); + phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe); + phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe); break; case ANTENNA_BC: - pMptCtx->MptRfPath = ODM_RF_PATH_BC; + pMptCtx->mpt_rf_path = ODM_RF_PATH_BC; /*pHalData->ValidTxPath = 0x06;*/ - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6); - PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6); - PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6); + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6); + phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6); + phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6); break; case ANTENNA_B: - pMptCtx->MptRfPath = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = ODM_RF_PATH_B; /*pHalData->ValidTxPath = 0x02;*/ - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/ - PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/ - PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/ + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/ + phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/ + phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/ break; case ANTENNA_C: - pMptCtx->MptRfPath = ODM_RF_PATH_C; + pMptCtx->mpt_rf_path = ODM_RF_PATH_C; /*pHalData->ValidTxPath = 0x04;*/ - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/ - PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/ - PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/ + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/ + phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/ + phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/ break; case ANTENNA_D: - pMptCtx->MptRfPath = ODM_RF_PATH_D; + pMptCtx->mpt_rf_path = ODM_RF_PATH_D; /*pHalData->ValidTxPath = 0x08;*/ - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/ - PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/ - PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/ + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/ + phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/ + phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/ break; case ANTENNA_A: default: - pMptCtx->MptRfPath = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = ODM_RF_PATH_A; /*pHalData->ValidTxPath = 0x01;*/ - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/ - PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/ - PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/ + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/ + phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/ + phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/ break; } } @@ -673,133 +709,131 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) switch (ulAntennaRx) { case ANTENNA_A: /*pHalData->ValidRxPath = 0x01;*/ - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); - PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11); - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); + phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11); + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ /*/ CCA related PD_delay_th*/ - PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); + phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); break; case ANTENNA_B: /*pHalData->ValidRxPath = 0x02;*/ - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); - PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22); - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); + phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22); + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ /*/ CCA related PD_delay_th*/ - PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); + phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); break; case ANTENNA_C: /*pHalData->ValidRxPath = 0x04;*/ - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); - PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44); - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); + phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44); + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ /*/ CCA related PD_delay_th*/ - PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); + phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); break; case ANTENNA_D: /*pHalData->ValidRxPath = 0x08;*/ - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); - PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88); - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); + phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88); + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ /*/ CCA related PD_delay_th*/ - PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); + phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); break; case ANTENNA_BC: /*pHalData->ValidRxPath = 0x06;*/ - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); - PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66); - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); + phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66); + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ /*/ CCA related PD_delay_th*/ - PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); + phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); break; case ANTENNA_CD: /*pHalData->ValidRxPath = 0x0C;*/ - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); - PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc); - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); + phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc); + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ /*/ CCA related PD_delay_th*/ - PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); + phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); break; case ANTENNA_BCD: /*pHalData->ValidRxPath = 0x0e;*/ - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); - PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee); - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/ + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); + phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee); + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/ /*/ CCA related PD_delay_th*/ - PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3); - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8); + phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8); break; case ANTENNA_ABCD: /*pHalData->ValidRxPath = 0x0f;*/ - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); - PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff); - PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); + phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff); + phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ /*/ CCA related PD_delay_th*/ - PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3); - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8); + phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8); break; default: - RT_TRACE(_module_mp_, _drv_warning_, ("Unknown Rx antenna.\n")); break; } PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx); mpt_ToggleIG_8814A(pAdapter); - RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n")); } #endif /* CONFIG_RTL8814A */ #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) @@ -810,23 +844,23 @@ mpt_SetSingleTone_8814A( IN BOOLEAN bEnPMacTx) { - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_A; static u4Byte regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0; if (bSingleTone) { - regIG0 = PHY_QueryBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/ - regIG1 = PHY_QueryBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/ - regIG2 = PHY_QueryBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/ - regIG3 = PHY_QueryBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/ + regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/ + regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/ + regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/ + regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/ - switch (pMptCtx->MptRfPath) { + switch (pMptCtx->mpt_rf_path) { case ODM_RF_PATH_A: case ODM_RF_PATH_B: case ODM_RF_PATH_C: case ODM_RF_PATH_D: - StartPath = pMptCtx->MptRfPath; - EndPath = pMptCtx->MptRfPath; + StartPath = pMptCtx->mpt_rf_path; + EndPath = pMptCtx->mpt_rf_path; break; case ODM_RF_PATH_AB: EndPath = ODM_RF_PATH_B; @@ -848,31 +882,31 @@ mpt_SetSingleTone_8814A( } if (bEnPMacTx == FALSE) { - hal_mpt_SetOFDMContinuousTx(pAdapter, _TRUE); + hal_mpt_SetContinuousTx(pAdapter, _TRUE); issue_nulldata(pAdapter, NULL, 1, 3, 500); } - PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/ for (StartPath; StartPath <= EndPath; StartPath++) { - PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ - PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ + phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ + phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ - PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/ + phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ } - PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/ - PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/ - PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/ - PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/ + phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/ + phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/ + phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/ + phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/ } else { - switch (pMptCtx->MptRfPath) { + switch (pMptCtx->mpt_rf_path) { case ODM_RF_PATH_A: case ODM_RF_PATH_B: case ODM_RF_PATH_C: case ODM_RF_PATH_D: - StartPath = pMptCtx->MptRfPath; - EndPath = pMptCtx->MptRfPath; + StartPath = pMptCtx->mpt_rf_path; + EndPath = pMptCtx->mpt_rf_path; break; case ODM_RF_PATH_AB: EndPath = ODM_RF_PATH_B; @@ -893,17 +927,17 @@ mpt_SetSingleTone_8814A( break; } for (StartPath; StartPath <= EndPath; StartPath++) - PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x0); /* RF LO disabled */ + phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */ - PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/ if (bEnPMacTx == FALSE) - hal_mpt_SetOFDMContinuousTx(pAdapter, _FALSE); + hal_mpt_SetContinuousTx(pAdapter, _FALSE); - PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/ - PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/ - PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/ - PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/ + phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/ + phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/ + phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/ + phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/ } } @@ -913,37 +947,37 @@ mpt_SetSingleTone_8814A( void mpt_SetRFPath_8812A(PADAPTER pAdapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; + PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx; struct mp_priv *pmp = &pAdapter->mppriv; u8 channel = pmp->channel; u8 bandwidth = pmp->bandwidth; u8 eLNA_2g = pHalData->ExternalLNA_2G; u32 ulAntennaTx, ulAntennaRx; - ulAntennaTx = pHalData->AntennaTxPath; + ulAntennaTx = pHalData->antenna_tx_path; ulAntennaRx = pHalData->AntennaRxPath; switch (ulAntennaTx) { case ANTENNA_A: - pMptCtx->MptRfPath = ODM_RF_PATH_A; - PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111); - if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) - PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0); + pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111); + if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) + phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0); break; case ANTENNA_B: - pMptCtx->MptRfPath = ODM_RF_PATH_B; - PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222); - if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) - PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1); + pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222); + if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) + phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1); break; case ANTENNA_AB: - pMptCtx->MptRfPath = ODM_RF_PATH_AB; - PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333); - if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) - PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0); + pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; + phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333); + if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) + phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0); break; default: - pMptCtx->MptRfPath = ODM_RF_PATH_AB; + pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; RTW_INFO("Unknown Tx antenna.\n"); break; } @@ -951,15 +985,15 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) switch (ulAntennaRx) { u32 reg0xC50 = 0; case ANTENNA_A: - PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3); + phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3); /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/ - reg0xC50 = PHY_QueryBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0); - PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2); - PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50); + reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0); + phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2); + phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50); /* set PWED_TH for BB Yn user guide R29 */ if (IS_HARDWARE_TYPE_8812(pAdapter)) { @@ -967,25 +1001,25 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) if (bandwidth == CHANNEL_WIDTH_20 && eLNA_2g == 0) { /* 0x830[3:1]=3'b010 */ - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02); } else /* 0x830[3:1]=3'b100 */ - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04); } else /* 0x830[3:1]=3'b100 for 5G */ - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04); } break; case ANTENNA_B: - PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */ - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3); + phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */ + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3); /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/ - reg0xC50 = PHY_QueryBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0); - PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2); - PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50); + reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0); + phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2); + phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50); /* set PWED_TH for BB Yn user guide R29 */ if (IS_HARDWARE_TYPE_8812(pAdapter)) { @@ -993,27 +1027,26 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) if (bandwidth == CHANNEL_WIDTH_20 && eLNA_2g == 0) { /* 0x830[3:1]=3'b010 */ - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02); } else /* 0x830[3:1]=3'b100 */ - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04); } else /* 0x830[3:1]=3'b100 for 5G */ - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04); } break; case ANTENNA_AB: - PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/ - PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); + phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/ + phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); /* set PWED_TH for BB Yn user guide R29 */ - PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04); + phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04); break; default: RTW_INFO("Unknown Rx antenna.\n"); break; } - RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n")); } #endif @@ -1022,11 +1055,11 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); u32 ulAntennaTx, ulAntennaRx; - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); - ulAntennaTx = pHalData->AntennaTxPath; + ulAntennaTx = pHalData->antenna_tx_path; ulAntennaRx = pHalData->AntennaRxPath; if (pHalData->rf_chip >= RF_TYPE_MAX) { @@ -1037,31 +1070,31 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter) switch (pAdapter->mppriv.antenna_tx) { u8 p = 0, i = 0; case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/ - pMptCtx->MptRfPath = ODM_RF_PATH_A; - PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0); - PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/ + pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0); + phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/ /*/<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/ if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)) - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); else - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); for (i = 0; i < 3; ++i) { - u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0]; - u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][1]; + u4Byte offset = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_A][i][0]; + u4Byte data = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_A][i][1]; if (offset != 0) { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data); } } for (i = 0; i < 2; ++i) { - u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0]; - u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][1]; + u4Byte offset = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_A][i][0]; + u4Byte data = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_A][i][1]; if (offset != 0) { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); } } @@ -1071,41 +1104,39 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter) u4Byte offset; u4Byte data; - pMptCtx->MptRfPath = ODM_RF_PATH_B; - PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5); - PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/ + pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5); + phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/ /* <20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/ if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)) - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); else - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); for (i = 0; i < 3; ++i) { /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/ - offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0]; - data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][1]; - if (pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + offset = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_A][i][0]; + data = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_B][i][1]; + if (pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_B][i][0] != 0) { + phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); } } /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/ for (i = 0; i < 2; ++i) { - offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0]; - data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][1]; - if (pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + offset = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_A][i][0]; + data = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_B][i][1]; + if (pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_B][i][0] != 0) { + phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); } } } break; default: - pMptCtx->MptRfPath = RF_PATH_AB; - RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n")); + pMptCtx->mpt_rf_path = RF_PATH_AB; break; } - RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n")); } #endif @@ -1114,11 +1145,11 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); u4Byte ulAntennaTx, ulAntennaRx; - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); - ulAntennaTx = pHalData->AntennaTxPath; + ulAntennaTx = pHalData->antenna_tx_path; ulAntennaRx = pHalData->AntennaRxPath; if (pHalData->rf_chip >= RF_TYPE_MAX) { @@ -1130,63 +1161,61 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter) u1Byte p = 0, i = 0; case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */ - pMptCtx->MptRfPath = ODM_RF_PATH_A; - PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0); - PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/ + pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0); + phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/ for (i = 0; i < 3; ++i) { - u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0]; - u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1]; + u4Byte offset = pRFCalibrateInfo->tx_iqc_8703b[i][0]; + u4Byte data = pRFCalibrateInfo->tx_iqc_8703b[i][1]; if (offset != 0) { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data); } } for (i = 0; i < 2; ++i) { - u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0]; - u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1]; + u4Byte offset = pRFCalibrateInfo->rx_iqc_8703b[i][0]; + u4Byte data = pRFCalibrateInfo->rx_iqc_8703b[i][1]; if (offset != 0) { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); } } } break; case ANTENNA_B: { /* Actually path S0 (BT)*/ - pMptCtx->MptRfPath = ODM_RF_PATH_B; - PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5); - PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */ + pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5); + phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */ for (i = 0; i < 3; ++i) { - u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0]; - u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1]; + u4Byte offset = pRFCalibrateInfo->tx_iqc_8703b[i][0]; + u4Byte data = pRFCalibrateInfo->tx_iqc_8703b[i][1]; - if (pRFCalibrateInfo->TxIQC_8703B[i][0] != 0) { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) { + phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); } } for (i = 0; i < 2; ++i) { - u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0]; - u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1]; + u4Byte offset = pRFCalibrateInfo->rx_iqc_8703b[i][0]; + u4Byte data = pRFCalibrateInfo->rx_iqc_8703b[i][1]; - if (pRFCalibrateInfo->RxIQC_8703B[i][0] != 0) { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) { + phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); } } } break; default: - pMptCtx->MptRfPath = RF_PATH_AB; - RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n")); + pMptCtx->mpt_rf_path = RF_PATH_AB; break; } - RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n")); } #endif @@ -1196,11 +1225,11 @@ void mpt_SetRFPath_8723D(PADAPTER pAdapter) HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); u1Byte p = 0, i = 0; u4Byte ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0; - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); - ulAntennaTx = pHalData->AntennaTxPath; + ulAntennaTx = pHalData->antenna_tx_path; ulAntennaRx = pHalData->AntennaRxPath; if (pHalData->rf_chip >= RF_TYPE_MAX) { @@ -1211,101 +1240,28 @@ void mpt_SetRFPath_8723D(PADAPTER pAdapter) switch (pAdapter->mppriv.antenna_tx) { /* Actually path S1 (Wi-Fi) */ case ANTENNA_A: { - pMptCtx->MptRfPath = ODM_RF_PATH_A; - PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, - BIT9 | BIT8 | BIT7, 0x0); - /* AGC Table Sel */ - PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); - - /*<20130522, Kordan> 0x51 and 0x71 should be set immediately - after path switched, or they might be overwritten.*/ - if ((pHalData->PackageType == PACKAGE_TFBGA79) || - (pHalData->PackageType == PACKAGE_TFBGA90)) - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, - 0x51, bRFRegOffsetMask, 0x6B10E); - else - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, - 0x51, bRFRegOffsetMask, 0x6B04E); - - - for (i = 0; i < 3; ++i) { - offset = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_A][i][0]; - data = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_A][i][1]; - if (offset != 0) { - PHY_SetBBReg(pAdapter, offset, - bMaskDWord, data); - RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data); - } - - } - for (i = 0; i < 2; ++i) { - offset = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_A][i][0]; - data = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_A][i][1]; - if (offset != 0) { - PHY_SetBBReg(pAdapter, offset, - bMaskDWord, data); - RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); - } - } + pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0); } break; /* Actually path S0 (BT) */ case ANTENNA_B: { - pMptCtx->MptRfPath = ODM_RF_PATH_B; - PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5); - /* AGC Table Sel */ - PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); - /* <20130522, Kordan> 0x51 and 0x71 should be set immediately - after path switched, or they might be overwritten.*/ - if ((pHalData->PackageType == PACKAGE_TFBGA79) || - (pHalData->PackageType == PACKAGE_TFBGA90)) - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, - bRFRegOffsetMask, 0x6B10E); - else - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, - bRFRegOffsetMask, 0x6B04E); - - - for (i = 0; i < 3; ++i) { - /* <20130603, Kordan> Because BB suppors only 1T1R, - we restore IQC to S1 instead of S0.*/ - offset = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_A][i][0]; - data = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_B][i][1]; - val32 = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_B][i][0]; - if (val32 != 0) { - PHY_SetBBReg(pAdapter, offset, - bMaskDWord, data); - RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); - } - } - for (i = 0; i < 2; ++i) { - /* <20130603, Kordan> Because BB suppors only 1T1R, we restore - * IQC to S1 instead of S0.*/ - offset = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_A][i][0]; - data = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_B][i][1]; - val32 = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_B][i][0]; - if (val32 != 0) { - PHY_SetBBReg(pAdapter, offset, - bMaskDWord, data); - RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); - } - } + pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA); } break; default: - pMptCtx->MptRfPath = RF_PATH_AB; - RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n")); + pMptCtx->mpt_rf_path = RF_PATH_AB; break; } - RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n")); } #endif VOID mpt_SetRFPath_819X(PADAPTER pAdapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); u4Byte ulAntennaTx, ulAntennaRx; R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */ R_ANTENNA_SELECT_CCK *p_cck_txrx; @@ -1313,7 +1269,7 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter) u1Byte chgTx = 0, chgRx = 0; u4Byte r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0; - ulAntennaTx = pHalData->AntennaTxPath; + ulAntennaTx = pHalData->antenna_tx_path; ulAntennaRx = pHalData->AntennaRxPath; p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val; @@ -1335,21 +1291,21 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter) /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/ /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/ { - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); - PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1); r_ofdm_tx_en_val = 0x3; /*/ Power save*/ /*/cosa r_ant_select_ofdm_val = 0x11111111;*/ /*/ We need to close RFB by SW control*/ if (pHalData->rf_type == RF_2T2R) { - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1); - PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0); } } - pMptCtx->MptRfPath = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = ODM_RF_PATH_A; break; case ANTENNA_B: p_ofdm_tx->r_tx_antenna = 0x2; @@ -1362,21 +1318,21 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter) /*/ From SD3 Willis suggestion !!! Set RF A as standby*/ /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/ { - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); - PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/ /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/ if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) { - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1); - PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); - /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/ - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); + /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/ + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); } } - pMptCtx->MptRfPath = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = ODM_RF_PATH_B; break; case ANTENNA_AB:/*/ For 8192S*/ p_ofdm_tx->r_tx_antenna = 0x3; @@ -1389,21 +1345,21 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter) /*/ From SD3Willis suggestion !!! Set RF B as standby*/ /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/ { - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); - PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); /* Disable Power save*/ /*cosa r_ant_select_ofdm_val = 0x3321333;*/ /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/ if (pHalData->rf_type == RF_2T2R) { - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); - /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/ - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); + /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/ + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); } } - pMptCtx->MptRfPath = ODM_RF_PATH_AB; + pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; break; default: break; @@ -1443,15 +1399,15 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter) case RF_8256: case RF_6052: /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/ - PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/ - PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/ - PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/ - PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/ + phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/ + phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/ + phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/ + phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/ if (IS_HARDWARE_TYPE_8192E(pAdapter)) { - PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/ - PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/ + phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/ + phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/ } - PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/ + phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/ break; default: @@ -1525,13 +1481,11 @@ s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther) HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); if (!netif_running(pAdapter->pnetdev)) { - RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n")); return _FAIL; } if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { - RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n")); return _FAIL; } @@ -1542,7 +1496,7 @@ s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther) else if (target_ther > 0x1d) target_ther = 0x1d; - pHalData->EEPROMThermalMeter = target_ther; + pHalData->eeprom_thermal_meter = target_ther; return _SUCCESS; } @@ -1550,7 +1504,7 @@ s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther) void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter) { - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03); } @@ -1558,11 +1512,25 @@ void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter) u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter) { + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(pAdapter); + struct PHY_DM_STRUCT *p_dm_odm = &hal_data->odmpriv; u32 ThermalValue = 0; + s32 thermal_value_temp = 0; + s8 thermal_offset = 0; - ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/ - return (u8)ThermalValue; + ThermalValue = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/ + thermal_offset = phydm_get_thermal_offset(p_dm_odm); + + thermal_value_temp = ThermalValue + thermal_offset; + + if (thermal_value_temp > 63) + ThermalValue = 63; + else if (thermal_value_temp < 0) + ThermalValue = 0; + else + ThermalValue = thermal_value_temp; + return (u8)ThermalValue; } @@ -1586,28 +1554,27 @@ void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - pAdapter->mppriv.MptCtx.bSingleCarrier = bStart; + pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart; if (bStart) {/*/ Start Single Carrier.*/ - RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n")); /*/ Start Single Carrier.*/ /*/ 1. if OFDM block on?*/ - if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) - PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/ + if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/ /*/ 2. set CCK test mode off, set to CCK normal mode*/ - PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0); + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0); /*/ 3. turn on scramble setting*/ - PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1); + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1); /*/ 4. Turn On Continue Tx and turn off the other test modes.*/ #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) - PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier); + phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier); else #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */ - PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier); + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier); } else { /*/ Stop Single Carrier.*/ @@ -1615,15 +1582,15 @@ void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) /*/ Turn off all test modes.*/ #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) - PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); + phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); else #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */ - PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); rtw_msleep_os(10); /*/BB Reset*/ - PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); - PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); } } @@ -1631,8 +1598,8 @@ void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - u4Byte ulAntennaTx = pHalData->AntennaTxPath; + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + u4Byte ulAntennaTx = pHalData->antenna_tx_path; static u4Byte regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0; u8 rfPath; @@ -1652,92 +1619,93 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) break; } - pAdapter->mppriv.MptCtx.bSingleTone = bStart; + pAdapter->mppriv.mpt_ctx.is_single_tone = bStart; if (bStart) { /*/ Start Single Tone.*/ /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/ if (IS_HARDWARE_TYPE_8188E(pAdapter)) { - regRF = PHY_QueryRFReg(pAdapter, rfPath, LNA_Low_Gain_3, bRFRegOffsetMask); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/ - PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0); - PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0); + regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0); + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0); } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/ /*/Set MAC REG 88C: Prevent SingleTone Fail*/ - PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0xF); - PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO disabled*/ - PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF); + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { - if (pMptCtx->MptRfPath == ODM_RF_PATH_A) { - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/ + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/ } else { /*/ S0/S1 both use PATH A to configure*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/ } } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { - if (pMptCtx->MptRfPath == ODM_RF_PATH_A) { - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */ + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */ } } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { /*Set BB REG 88C: Prevent SingleTone Fail*/ - PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF); - PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); - PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); + phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF); + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) { - if (pMptCtx->MptRfPath == ODM_RF_PATH_A) { - PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x1); + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x1); } else {/* S0/S1 both use PATH A to configure */ - PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x1); + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x1); } } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) { -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) u1Byte p = ODM_RF_PATH_A; - regRF = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask); - regBB0 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord); - regBB1 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord); - regBB2 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord); - regBB3 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord); + regRF = phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask); + regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord); + regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord); + regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord); + regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord); - PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/ + phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/ - if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) { + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_AB) { for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) { - PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ - PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ - PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/ + phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ + phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ + phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ } } else { - PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ - PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ - PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ } - PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ - PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ - if (pHalData->ExternalPA_5G) { - PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/ - PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/ + if (pHalData->external_pa_5g) { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/ } else if (pHalData->ExternalPA_2G) { - PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/ - PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/ + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/ } #endif } -#ifdef CONFIG_RTL8814A - else if (IS_HARDWARE_TYPE_8814A(pAdapter)) - mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE); +#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821C) + else if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) + mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE); #endif + else /*/ Turn On SingleTone and turn off the other test modes.*/ - PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone); + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone); write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); @@ -1745,71 +1713,71 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) } else {/*/ Stop Single Ton e.*/ if (IS_HARDWARE_TYPE_8188E(pAdapter)) { - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, regRF); - PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1); - PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF); + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1); + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1); } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { - PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/ - PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0);/*/ RF LO disabled */ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */ /*/ RESTORE MAC REG 88C: Enable RF Functions*/ - PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0x0); + phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0); } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { - if (pMptCtx->MptRfPath == ODM_RF_PATH_A) { - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/ + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/ } else { /*/ S0/S1 both use PATH A to configure*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/ } } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { - if (pMptCtx->MptRfPath == ODM_RF_PATH_A) { - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */ - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */ + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */ } } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { - PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3); /*Tx mode*/ - PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0); /*RF LO disabled*/ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/ /*Set BB REG 88C: Prevent SingleTone Fail*/ - PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc); + phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc); } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) { - if (pMptCtx->MptRfPath == ODM_RF_PATH_A) { - PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x0); + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x0); } else { /* S0/S1 both use PATH A to configure */ - PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1); - PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x0); + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x0); } } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) { -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) u1Byte p = ODM_RF_PATH_A; - PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/ + phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/ - if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) { + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_AB) { for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) { - PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF); - PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/ + phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF); + phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/ } } else { - PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF); - PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/ + phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF); + phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/ } - PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0); - PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1); - PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2); - PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3); + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0); + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1); + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2); + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3); #endif } #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) - else if (IS_HARDWARE_TYPE_8814A(pAdapter)) + else if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE); else/*/ Turn off all test modes.*/ - PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); + phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); #endif write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); @@ -1821,11 +1789,10 @@ void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) { u8 Rate; - pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart; + pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart; Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx); if (bStart) {/* Start Carrier Suppression.*/ - RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n")); if (Rate <= MPT_RATE_11M) { /*/ 1. if CCK block on?*/ if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn)) @@ -1833,9 +1800,9 @@ void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) /*/Turn Off All Test Mode*/ if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/) - PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/ + phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/ else - PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/ @@ -1849,7 +1816,6 @@ void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); } else {/* Stop Carrier Suppression.*/ - RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n")); if (Rate <= MPT_RATE_11M) { write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/ @@ -1866,148 +1832,16 @@ void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n"); } -void hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart) -{ - u32 cckrate; - - if (bStart) { - RT_TRACE(_module_mp_, _drv_alert_, - ("SetCCKContinuousTx: test start\n")); - - /*/ 1. if CCK block on?*/ - if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn)) - write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/ - - /*/Turn Off All Test Mode*/ - if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) - PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /*rSingleTone_ContTx_Jaguar*/ - else - PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); - - /*/Set CCK Tx Test Rate*/ - - cckrate = pAdapter->mppriv.rateidx; - - write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate); - write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/ - write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/ - - if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) { - PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 11 force cck rxiq = 0*/ - PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /*/ 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/ - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1); - PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1); - } - - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); - - } else { - RT_TRACE(_module_mp_, _drv_info_, - ("SetCCKContinuousTx: test stop\n")); - - write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*/normal mode*/ - write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/ - - if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /* && !IS_HARDWARE_TYPE_8822B(pAdapter) */) { - PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/* rCCK0_RxHP 0xa15[1:0] = 2b00*/ - PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /*/ 0xc08[16] = 0*/ - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0); - PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0); - } - - /*/BB Reset*/ - write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); - write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); - - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); - } - - pAdapter->mppriv.MptCtx.bCckContTx = bStart; - pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE; -} - -void hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - if (bStart) { - RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));/*/ 1. if OFDM block on?*/ - if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) - PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*/set OFDM block on*/ - - /*/ 2. set CCK test mode off, set to CCK normal mode*/ - PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0); - - /*/ 3. turn on scramble setting*/ - PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1); - - if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&& !IS_HARDWARE_TYPE_8822B(pAdapter)*/) { - PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 2b'11*/ - PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/ - } - - /*/ 4. Turn On Continue Tx and turn off the other test modes.*/ - if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/) - PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx); /*rSingleTone_ContTx_Jaguar*/ - else - PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx); - - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); - - } else { - RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test stop\n")); - if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/) - PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); - else - PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); - /*/Delay 10 ms*/ - rtw_msleep_os(10); - - if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&&! IS_HARDWARE_TYPE_8822B(pAdapter)*/) { - PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/*/ 0xa15[1:0] = 0*/ - PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);/*/ 0xc08[16] = 0*/ - } - - /*/BB Reset*/ - PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); - PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); - - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); - } - - pAdapter->mppriv.MptCtx.bCckContTx = _FALSE; - pAdapter->mppriv.MptCtx.bOfdmContTx = bStart; -} - -void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart) -{ - u8 Rate; - - RT_TRACE(_module_mp_, _drv_info_, - ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx)); - Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx); - pAdapter->mppriv.MptCtx.bStartContTx = bStart; - - if (Rate <= MPT_RATE_11M) - hal_mpt_SetCCKContinuousTx(pAdapter, bStart); - else if (Rate >= MPT_RATE_6M) - hal_mpt_SetOFDMContinuousTx(pAdapter, bStart); -} - u32 hal_mpt_query_phytxok(PADAPTER pAdapter) { - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo; u16 count = 0; if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) - count = PHY_QueryBBReg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/ + count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/ else - count = PHY_QueryBBReg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/ + count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/ if (count > 50000) { rtw_reset_phy_trx_ok_counters(pAdapter); @@ -2019,36 +1853,35 @@ u32 hal_mpt_query_phytxok(PADAPTER pAdapter) } -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) -/* for HW TX mode */ static VOID mpt_StopCckContTx( PADAPTER pAdapter ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); u1Byte u1bReg; pMptCtx->bCckContTx = FALSE; pMptCtx->bOfdmContTx = FALSE; - PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/ - PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/ + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/ + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/ - if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) { - PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/ - PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/ + if (!IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) { + phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/ + phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/ - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0); - PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0); + phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0); } /*BB Reset*/ - PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); - PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); - PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); } /* mpt_StopCckContTx */ @@ -2058,7 +1891,7 @@ static VOID mpt_StopOfdmContTx( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); u1Byte u1bReg; u4Byte data; @@ -2066,23 +1899,23 @@ static VOID mpt_StopOfdmContTx( pMptCtx->bOfdmContTx = FALSE; if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) - PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); + phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); else - PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); rtw_mdelay_os(10); if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) { - PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/ - PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/ + phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/ + phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/ } /*BB Reset*/ - PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); - PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); - PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); } /* mpt_StopOfdmContTx */ @@ -2091,35 +1924,36 @@ static VOID mpt_StartCckContTx( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); u4Byte cckrate; /* 1. if CCK block on */ - if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn)) - PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/ + if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/ /*Turn Off All Test Mode*/ if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) - PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); + phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); else - PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); cckrate = pAdapter->mppriv.rateidx; - PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, cckrate); + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate); - PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/ - PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/ + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/ + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/ if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) { - PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/ - PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/ - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1); - PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1); + phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/ + phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/ + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1); + phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1); } - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); - PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); pMptCtx->bCckContTx = TRUE; pMptCtx->bOfdmContTx = FALSE; @@ -2132,52 +1966,54 @@ static VOID mpt_StartOfdmContTx( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); /* 1. if OFDM block on?*/ - if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) - PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/ + if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/ /* 2. set CCK test mode off, set to CCK normal mode*/ - PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0); + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0); /* 3. turn on scramble setting*/ - PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1); + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1); if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) { - PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/ - PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/ + phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/ + phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/ } /* 4. Turn On Continue Tx and turn off the other test modes.*/ if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) - PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx); + phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx); else - PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx); + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx); - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); - PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); pMptCtx->bCckContTx = FALSE; pMptCtx->bOfdmContTx = TRUE; } /* mpt_StartOfdmContTx */ +#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) +/* for HW TX mode */ void mpt_ProSetPMacTx(PADAPTER Adapter) { - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo; u32 u4bTmp; - DbgPrint("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound); - DbgPrint("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount, + dbg_print("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound); + dbg_print("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount, PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern); #if 0 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3); PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6); PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6); PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4); - DbgPrint("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC); + dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC); PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4); PRINT_DATA("Src Address", Adapter->mac_addr, 6); @@ -2186,17 +2022,17 @@ void mpt_ProSetPMacTx(PADAPTER Adapter) if (PMacTxInfo.bEnPMacTx == FALSE) { if (PMacTxInfo.Mode == CONTINUOUS_TX) { - PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/ + phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/ if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) mpt_StopCckContTx(Adapter); else mpt_StopOfdmContTx(Adapter); } else if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) { - u4bTmp = PHY_QueryBBReg(Adapter, 0xf50, bMaskLWord); - PHY_SetBBReg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50); - PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/ + u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord); + phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50); + phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/ } else - PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/ + phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/ if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) { /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/ @@ -2234,22 +2070,22 @@ void mpt_ProSetPMacTx(PADAPTER Adapter) if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) { /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/ u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16); - PHY_SetBBReg(Adapter, 0xb1c, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp); /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/ u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16); - PHY_SetBBReg(Adapter, 0xb40, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp); u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8); - PHY_SetBBReg(Adapter, 0xb44, bMaskLWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp); if (PMacTxInfo.bSPreamble) - PHY_SetBBReg(Adapter, 0xb0c, BIT27, 0); + phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0); else - PHY_SetBBReg(Adapter, 0xb0c, BIT27, 1); + phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1); } else { - PHY_SetBBReg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount); + phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount); u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24); - PHY_SetBBReg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/ + phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/ if (PMacTxInfo.PacketPattern == 0x12) u4bTmp = 0x3000000; @@ -2259,103 +2095,127 @@ void mpt_ProSetPMacTx(PADAPTER Adapter) if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) { u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16); - PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp); u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16); - PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp); + phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp); } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) { u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16); - PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp); u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16); - PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp); + phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp); _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4); - PHY_SetBBReg(Adapter, 0xb14, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp); } if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) { u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod; /* for TX interval */ - PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp); _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4); - PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp); /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/ /*& Duration & Frame control*/ - PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, 0x00000040); + phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040); /* Address1 [0:3]*/ u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24); - PHY_SetBBReg(Adapter, 0xb2C, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp); /* Address3 [3:0]*/ - PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp); /* Address2[0:1] & Address1 [5:4]*/ u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24); - PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp); /* Address2 [5:2]*/ u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24); - PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp); /* Sequence Control & Address3 [5:4]*/ /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/ - /*PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/ + /*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/ } else { - PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/ + phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/ /* & Duration & Frame control */ - PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, 0x00000040); + phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040); /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/ /* Address1 [0:3]*/ u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24); - PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp); /* Address3 [3:0]*/ - PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp); /* Address2[0:1] & Address1 [5:4]*/ u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24); - PHY_SetBBReg(Adapter, 0xb2c, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp); /* Address2 [5:2] */ u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24); - PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp); /* Sequence Control & Address3 [5:4]*/ u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8); - PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp); + phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp); } - PHY_SetBBReg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX); + phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX); /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/ u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8); - PHY_SetBBReg(Adapter, 0xb4c, 0x1ff, u4bTmp); + phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp); if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) { u4Byte offset = 0xb44; if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE)) - PHY_SetBBReg(Adapter, offset, 0xc0000000, 0); + phy_set_bb_reg(Adapter, offset, 0xc0000000, 0); else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) - PHY_SetBBReg(Adapter, offset, 0xc0000000, 1); + phy_set_bb_reg(Adapter, offset, 0xc0000000, 1); else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) - PHY_SetBBReg(Adapter, offset, 0xc0000000, 2); + phy_set_bb_reg(Adapter, offset, 0xc0000000, 2); } - PHY_SetBBReg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/ - /* PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */ + phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/ + /* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */ if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) { - PHY_SetBBReg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/ - PHY_SetBBReg(Adapter, 0xA84, BIT31, 0); + phy_set_bb_reg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/ + phy_set_bb_reg(Adapter, 0xA84, BIT31, 0); } else - PHY_SetBBReg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */ + phy_set_bb_reg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */ if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE); } + #endif +void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart) +{ + u8 Rate; + + RT_TRACE(_module_mp_, _drv_info_, + ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx)); + Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx); + pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart; + + if (Rate <= MPT_RATE_11M) { + if (bStart) + mpt_StartCckContTx(pAdapter); + else + mpt_StopCckContTx(pAdapter); + + } else if (Rate >= MPT_RATE_6M) { + if (bStart) + mpt_StartOfdmContTx(pAdapter); + else + mpt_StopOfdmContTx(pAdapter); + } +} + #endif /* CONFIG_MP_INCLUDE*/ diff --git a/hal/hal_phy.c b/hal/hal_phy.c index 9d809ed..88c1b1c 100644 --- a/hal/hal_phy.c +++ b/hal/hal_phy.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_PHY_C_ #include @@ -120,9 +115,6 @@ PHY_RFShadowCompare( if (RF_Shadow[eRFPath][Offset].Value != reg) { /* Locate error position. */ RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE; - /* RT_TRACE(COMP_INIT, DBG_LOUD, */ - /* ("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n", */ - /* eRFPath, Offset, reg)); */ } return RF_Shadow[eRFPath][Offset].ErrorOrNot ; } @@ -142,9 +134,6 @@ PHY_RFShadowRecorver( if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE) { rtw_hal_write_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask, RF_Shadow[eRFPath][Offset].Value); - /* RT_TRACE(COMP_INIT, DBG_LOUD, */ - /* ("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx", */ - /* eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value)); */ } } diff --git a/hal/halmac/halmac_2_platform.h b/hal/halmac/halmac_2_platform.h index 2541867..c6352de 100644 --- a/hal/halmac/halmac_2_platform.h +++ b/hal/halmac/halmac_2_platform.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * ******************************************************************************/ + #ifndef _HALMAC_2_PLATFORM_H_ #define _HALMAC_2_PLATFORM_H_ @@ -70,8 +66,9 @@ typedef s32 *ps32; /*[Driver] config if enable the dbg msg or notl*/ #define HALMAC_DBG_MSG_ENABLE 1 -/*[Driver] define the Platform SDIO Bus CLK */ -#define PLATFORM_SD_CLK 50000000 /*50MHz*/ +/*[Driver] define the Rx FIFO expanding mode packet size unit for 8821C and 8822B */ +/*Should be 8 Byte alignment*/ +#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 48 /*Bytes*/ /*[Driver] provide the type mutex*/ /* Mutex type */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h index 36537ed..e2a9c96 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_8822B_CFG_H_ #define _HALMAC_8822B_CFG_H_ @@ -18,15 +33,29 @@ #endif #define HALMAC_TX_FIFO_SIZE_8822B 262144 /* 256k */ -#define HALMAC_TX_FIFO_SIZE_LA_8822B 131072 /* 128k */ -#define HALMAC_RX_FIFO_SIZE_8822B 24320 /* 24k */ +#define HALMAC_TX_FIFO_SIZE_LA_8822B (HALMAC_TX_FIFO_SIZE_8822B >> 1) /* 128k */ +#define HALMAC_RX_FIFO_SIZE_8822B 24576 /* 24k */ #define HALMAC_TX_PAGE_SIZE_8822B 128 /* PageSize 128Byte */ +#define HALMAC_TX_ALIGN_SIZE_8822B 8 #define HALMAC_TX_PAGE_SIZE_2_POWER_8822B 7 /* 128 = 2^7 */ #define HALMAC_SECURITY_CAM_ENTRY_NUM_8822B 64 /* CAM Entry Size */ #define HALMAC_TX_AGG_ALIGNMENT_SIZE_8822B 8 #define HALMAC_TX_DESC_SIZE_8822B 48 #define HALMAC_RX_DESC_SIZE_8822B 24 -#define HALMAC_WOWLAN_PATTERN_SIZE_8822B 256 +#define HALMAC_C2H_PKT_BUF_8822B 256 +#define HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B 80 /*8*10 Bytes*/ +#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B 80 /* should be 8 Byte alignment*/ + +#define HALMAC_RX_FIFO_EXPANDING_UNIT_8822B (HALMAC_RX_DESC_SIZE_8822B + HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE) /* should be 8 Byte alignment*/ +#define HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8822B (HALMAC_RX_DESC_SIZE_8822B + HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B) /* should be 8 Byte alignment*/ + +#define HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B 196608 /* 192k */ +#define HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B ((((HALMAC_RX_FIFO_EXPANDING_UNIT_8822B << 8) - 1) >> 10) << 10) /* < 46k*/ +#define HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_MAX_8822B ((((HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8822B << 8) - 1) >> 10) << 10) /* 45k < 64K*/ +#define HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_2_BLOCK_8822B 131072 /* 128k */ +#define HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_2_BLOCK_8822B 155648 /* 152k */ +#define HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_3_BLOCK_8822B 65536 /* 64k */ +#define HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_3_BLOCK_8822B 221184 /* 216k */ /* * TXFIFO LAYOUT @@ -53,68 +82,6 @@ #define HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B 0 /*0*/ #define HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B 4 /*512*/ -/* -* Normal mode -*/ -#define HALMAC_NORMAL_HPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_NORMAL_NPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_NORMAL_LPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_NORMAL_EXPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_NORMAL_GAP_PGNUM_8822B 1 /*128*/ - -/* -* Loopback mode -*/ -#define HALMAC_LB_HPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_LB_NPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_LB_LPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_LB_EXPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_LB_GAP_PGNUM_8822B 640 /*81920*/ - -/* -* Normal mode - 2Bulkout -*/ -#define HALMAC_NORMAL_2BULKOUT_HPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_NORMAL_2BULKOUT_NPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_NORMAL_2BULKOUT_LPQ_PGNUM_8822B 0 /*0*/ -#define HALMAC_NORMAL_2BULKOUT_EXPQ_PGNUM_8822B 0 /*0*/ -#define HALMAC_NORMAL_2BULKOUT_GAP_PGNUM_8822B 1 /*128*/ - -/* -* Loopback mode - 2Bulkout -*/ -#define HALMAC_LB_2BULKOUT_HPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_LB_2BULKOUT_NPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_LB_2BULKOUT_LPQ_PGNUM_8822B 0 /*0*/ -#define HALMAC_LB_2BULKOUT_EXPQ_PGNUM_8822B 0 /*0*/ -#define HALMAC_LB_2BULKOUT_GAP_PGNUM_8822B 1024 /*131072*/ - -/* -* Normal mode - 3BULKOUT -*/ -#define HALMAC_NORMAL_3BULKOUT_HPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_NORMAL_3BULKOUT_NPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_NORMAL_3BULKOUT_LPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_NORMAL_3BULKOUT_EXPQ_PGNUM_8822B 0 /*0*/ -#define HALMAC_NORMAL_3BULKOUT_GAP_PGNUM_8822B 1 /*128*/ - -/* -* Loopback mode - 3BULKOUT -*/ -#define HALMAC_LB_3BULKOUT_HPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_LB_3BULKOUT_NPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_LB_3BULKOUT_LPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_LB_3BULKOUT_EXPQ_PGNUM_8822B 0 /*0*/ -#define HALMAC_LB_3BULKOUT_GAP_PGNUM_8822B 1024 /*131072*/ - -/* -* WMM mode -*/ -#define HALMAC_WMM_HPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_WMM_NPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_WMM_LPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_WMM_EXPQ_PGNUM_8822B 64 /*8192*/ -#define HALMAC_WMM_GAP_PGNUM_8822B 1 /*128*/ #define HALMAC_EFUSE_SIZE_8822B 1024 /* 0x400 */ #define HALMAC_BT_EFUSE_SIZE_8822B 128 /* 0x80 */ @@ -125,14 +92,23 @@ #define HALMAC_BLK_DESC_NUM_8822B 0x3 /* Only for USB */ -typedef enum _HALMAC_NORMAL_RXAGG_TH_TO_8822B { - HALMAC_NORMAL_RXAGG_THRESHOLD_8822B = 0xFF, - HALMAC_NORMAL_RXAGG_TIMEOUT_8822B = 0x01, -} HALMAC_NORMAL_RXAGG_TH_TO_8822B; +/* AMPDU max time (unit : 32us) */ +#define HALMAC_AMPDU_MAX_TIME_8822B 0x70 + +/* Protect mode control */ +#define HALMAC_PROT_RTS_LEN_TH_8822B 0xFF +#define HALMAC_PROT_RTS_TX_TIME_TH_8822B 0x08 +#define HALMAC_PROT_MAX_AGG_PKT_LIMIT_8822B 0x20 +#define HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8822B 0x20 + +/* Fast EDCA setting */ +#define HALMAC_FAST_EDCA_VO_TH_8822B 0x06 +#define HALMAC_FAST_EDCA_VI_TH_8822B 0x06 +#define HALMAC_FAST_EDCA_BE_TH_8822B 0x06 +#define HALMAC_FAST_EDCA_BK_TH_8822B 0x06 -typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO_8822B { - HALMAC_LOOPBACK_RXAGG_THRESHOLD_8822B = 0xFF, - HALMAC_LOOPBACK_RXAGG_TIMEOUT_8822B = 0x01, -} HALMAC_LOOPBACK_RXAGG_TH_TO_8822B; +/* BAR setting */ +#define HALMAC_BAR_RETRY_LIMIT_8822B 0x01 +#define HALMAC_RA_TRY_RATE_AGG_LIMIT_8822B 0x08 #endif diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c index c26c88d..79e2a5a 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c @@ -1,76 +1,264 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "../halmac_88xx_cfg.h" #include "halmac_8822b_cfg.h" -/* - * drivers should parse below arrays and do the corresponding actions - */ -/* 3 Power on Array */ -HALMAC_WLAN_PWR_CFG halmac_8822b_power_on_flow[] = { - HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT - HALMAC_RTL8822B_TRANS_END +HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0012, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*SWR OCP = SWR OCP = 010 1382.40*/ + {0x0012, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*SWR OCP = 010 1382.40 */ + {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ + {0x0001, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWRSEQ_DELAY_MS}, /*Delay 1ms*/ + {0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ + {0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* Disable USB suspend */ + {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, /* wait till 0x04[17] = 1 power ready*/ + {0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /* Enable USB suspend */ + {0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*0xFF1A = 0 to release resume signals*/ + {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* release WLON reset 0x04[16]=1*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0}, /* disable HWPDN 0x04[15]=0*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, /* disable WL suspend*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* polling until return 0*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(0), 0}, + {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, /*Enable XTAL_CLK*/ + {0x10A8, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0},/*NFC pad enabled*/ + {0x10A9, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xef},/*NFC pad enabled*/ + {0x10AA, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x0c},/*NFC pad enabled*/ + {0x0068, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO pad power down disabled*/ + {0x0029, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xF9}, /*PLL seting*/ + {0x0024, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /*CH13»P5G³¡¤ÀCH TX EVMªº§ïµ½*/ + {0x0074, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*PCIE WAKE# enabled*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, }; -/* 3 Radio off GPIO Array */ -HALMAC_WLAN_PWR_CFG halmac_8822b_radio_off_flow[] = { - HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU - HALMAC_RTL8822B_TRANS_END +HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0003, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /*0x02[10] = 0 Disable MCU Core*/ + {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0}, /*LPS option 0x93[3]=0 , SWR PFM*/ + {0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ + {0x00EF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*0xEF[7:0] = 0 turn off RF*/ + {0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x30}, /*0xFF1A = 0x30 to block resume signals*/ + {0x0049, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*Enable rising edge triggering interrupt*/ + {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* release WLON reset 0x04[16]=1*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /* Whole BB is reset */ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ + {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0}, /* XTAL_CLK gated*/ + {0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, }; -/* 3 Card Disable Array */ -HALMAC_WLAN_PWR_CFG halmac_8822b_card_disable_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8822B_TRANS_END_STEPS] = { - HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU - HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS - HALMAC_RTL8822B_TRANS_END +HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/ + {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, }; -/* 3 Card Enable Array */ -HALMAC_WLAN_PWR_CFG halmac_8822b_card_enable_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8822B_TRANS_END_STEPS] = { - HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU - HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT - HALMAC_RTL8822B_TRANS_END +HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, }; -/* 3 Suspend Array */ -HALMAC_WLAN_PWR_CFG halmac_8822b_suspend_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8822B_TRANS_END_STEPS] = { - HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU - HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS - HALMAC_RTL8822B_TRANS_END +HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*suspend enable and power down enable*/ + {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ + {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0}, /*0x67[5]=0 , BIT_PAPE_WLBT_SEL*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/ + {0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ + {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /* 0: BT PAPE control ; 1: WL BB LNAON control*/ + {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /* 0: BT GPIO[11:10] control ; 1: WL BB LNAON control*/ + {0x004F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* 0: BT Control*/ + {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /* turn off BT_3DD_SYNC_B and BT_GPIO[18] */ + {0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6) }, /* GPIO[6] : Output mode*/ + {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0 }, /* turn off BT_GPIO[16] */ + {0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /* GPIO[7] : Output mode*/ + {0x0062, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* GPIO[12] : Output mode */ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ + {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*0x90[1]=0 , disable 32k clock*/ + {0x0044, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*0x90[1]=0 , disable 32k clock by indirect access*/ + {0x0040, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x90}, /*0x90[1]=0 , disable 32k clock by indirect access*/ + {0x0041, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x00}, /*0x90[1]=0 , disable 32k clock by indirect access*/ + {0x0042, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x04}, /*0x90[1]=0 , disable 32k clock by indirect access*/ + {0x0081, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0}, /*0x80[15]clean fw init ready bit*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, }; -/* 3 Resume Array */ -HALMAC_WLAN_PWR_CFG halmac_8822b_resume_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8822B_TRANS_END_STEPS] = { - HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU - HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT - HALMAC_RTL8822B_TRANS_END +HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/ + {0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, /*clear suspend enable and power down enable*/ + {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, }; +HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_CARDEMU_TO_PDN[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ + {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /* 0x04[16] = 0*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /* 0x04[15] = 1*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; +HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_PDN_TO_CARDEMU[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0}, + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_ACT_TO_LPS[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/ + {0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, /*Register write data of 32K calibration*/ + {0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/ + {0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/ + {0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable 32K CLK*/ + {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x42}, /* LPS Option MAC OFF enable*/ + {0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /* LPS Option Enable memory to deep sleep mode*/ + {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, /* enable reg use 32K CLK*/ + {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*PCIe DMA stop*/ + {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*Tx Pause*/ + {0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*Whole BB is reset*/ + {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F}, /*Reset MAC TRX*/ + {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*check if removed later*/ + {0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/ + {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /* switch TSF clock to 32K*/ + {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)}, /*Polling 0x109[7]=0 TSF in 40M*/ + {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable WL_LPS_EN*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/ + {0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, /*Register write data of 32K calibration*/ + {0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/ + {0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/ + {0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable 32K CLK*/ + {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x40}, /* LPS Option MAC OFF enable*/ + {0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /* LPS Option Enable memory to deep sleep mode*/ + {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, /* enable reg use 32K CLK*/ + {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*PCIe DMA stop*/ + {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*Tx Pause*/ + {0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*Whole BB is reset*/ + {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F}, /*Reset MAC TRX*/ + {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*check if removed later*/ + {0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/ + {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /* switch TSF clock to 32K*/ + {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)}, /*Polling 0x109[7]=1 TSF in 32K*/ + {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable WL_LPS_EN*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_LPS_TO_ACT[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*SDIO RPWM*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/ + {0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), 0}, /*SDIO RPWM*/ + {0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ + {0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/ + {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0}, /* switch TSF to 40M*/ + {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/ + {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, + {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*nable WMAC TRX*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, /*nable BB macro*/ + {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x03}, /*clear RPWM INT*/ + {0x0124, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/ + {0x0125, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/ + {0x0126, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/ + {0x0127, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/ + {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /* disable reg use 32K CLK*/ + {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /*disable 32k calibration and thermal meter*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +/* Card Enable Array */ +PHALMAC_WLAN_PWR_CFG halmac_8822b_card_enable_flow[] = { + HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU, + HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT, + NULL +}; + +/* Card Disable Array */ +PHALMAC_WLAN_PWR_CFG halmac_8822b_card_disable_flow[] = { + HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU, + HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS, + NULL +}; + +/* Suspend Array */ +PHALMAC_WLAN_PWR_CFG halmac_8822b_suspend_flow[] = { + HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU, + HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS, + NULL +}; + +/* Resume Array */ +PHALMAC_WLAN_PWR_CFG halmac_8822b_resume_flow[] = { + HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU, + HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT, + NULL +}; -/* 3HWPDN Array */ -HALMAC_WLAN_PWR_CFG halmac_8822b_hwpdn_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8822B_TRANS_END_STEPS] = { - /* TRANS_ACT_TO_CARDEMU */ - /* TRANS_CARDEMU_TO_PDN */ - /* HW behavior */ - HALMAC_RTL8822B_TRANS_END +/* HWPDN Array - HW behavior */ +PHALMAC_WLAN_PWR_CFG halmac_8822b_hwpdn_flow[] = { + NULL }; -/* 3 Enter LPS */ -HALMAC_WLAN_PWR_CFG halmac_8822b_enter_lps_flow[HALMAC_8822B_TRANS_ACT_TO_LPS_STEPS + HALMAC_8822B_TRANS_END_STEPS] = { - /* FW behavior */ - HALMAC_RTL8822B_TRANS_ACT_TO_LPS - HALMAC_RTL8822B_TRANS_END +/* Enter LPS - FW behavior */ +PHALMAC_WLAN_PWR_CFG halmac_8822b_enter_lps_flow[] = { + HALMAC_RTL8822B_TRANS_ACT_TO_LPS, + NULL }; -/* 3 Enter Deep LPS */ -HALMAC_WLAN_PWR_CFG halmac_8822b_enter_deep_lps_flow[HALMAC_8822B_TRANS_ACT_TO_DEEP_LPS_STEPS + HALMAC_8822B_TRANS_END_STEPS] = { - /* FW behavior */ - HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS - HALMAC_RTL8822B_TRANS_END +/* Enter Deep LPS - FW behavior */ +PHALMAC_WLAN_PWR_CFG halmac_8822b_enter_deep_lps_flow[] = { + HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS, + NULL }; -/* 3 Leave LPS */ -HALMAC_WLAN_PWR_CFG halmac_8822b_leave_lps_flow[HALMAC_8822B_TRANS_LPS_TO_ACT_STEPS + HALMAC_8822B_TRANS_END_STEPS] = { - /* FW behavior */ - HALMAC_RTL8822B_TRANS_LPS_TO_ACT - HALMAC_RTL8822B_TRANS_END +/* Leave LPS -FW behavior */ +PHALMAC_WLAN_PWR_CFG halmac_8822b_leave_lps_flow[] = { + HALMAC_RTL8822B_TRANS_LPS_TO_ACT, + NULL }; diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h index 5f97169..0b8e246 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h @@ -1,227 +1,31 @@ -#ifndef HALMAC_POWER_SEQUENCE_8822B -#define HALMAC_POWER_SEQUENCE_8822B - -#include "../../halmac_pwr_seq_cmd.h" - -/* - * Check document WM-20151103-v02-JackieLau-RTL8822B_Power_Architecture.vsd - * There are 6 HW Power States: - * 0: POFF--Power Off - * 1: PDN--Power Down - * 2: CARDEMU--Card Emulation - * 3: ACT--Active Mode - * 4: LPS--Low Power State - * 5: SUS--Suspend +/****************************************************************************** * - * The transition from different states are defined below - * TRANS_CARDEMU_TO_ACT - * TRANS_ACT_TO_CARDEMU - * TRANS_CARDEMU_TO_SUS - * TRANS_SUS_TO_CARDEMU - * TRANS_CARDEMU_TO_PDN - * TRANS_ACT_TO_LPS - * TRANS_LPS_TO_ACT + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. * - * TRANS_END - */ - -#define HALMAC_8822B_TRANS_CARDEMU_TO_ACT_STEPS 25 -#define HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define HALMAC_8822B_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define HALMAC_8822B_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define HALMAC_8822B_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define HALMAC_8822B_TRANS_ACT_TO_LPS_STEPS 25 -#define HALMAC_8822B_TRANS_ACT_TO_DEEP_LPS_STEPS 25 -#define HALMAC_8822B_TRANS_LPS_TO_ACT_STEPS 20 -#define HALMAC_8822B_TRANS_END_STEPS 1 - - -#define HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ - { 0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ - { 0x0001, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWRSEQ_DELAY_MS }, /*Delay 1ms*/ \ - { 0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0 }, /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \ - { 0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* Disable USB suspend */ \ - { 0x0004, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /* enabled usb resume */ \ - { 0x0004, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0 }, /* disable usb resume */ \ - { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /* wait till 0x04[17] = 1 power ready*/ \ - { 0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* Enable USB suspend */ \ - { 0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0xFF1A = 0 to release resume signals*/ \ - { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* release WLON reset 0x04[16]=1*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /* disable HWPDN 0x04[15]=0*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0 }, /* disable WL suspend*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* polling until return 0*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(0), 0 }, /**/ \ - { 0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /*Enable XTAL_CLK*/ \ - { 0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*0x67[5]=1 , BIT_PAPE_WLBT_SEL*/ \ - -#define HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0x1F[7:0] = 0 turn off RF*/ \ - { 0x00EF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0xEF[7:0] = 0 turn off RF*/ \ - { 0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x30 }, /*0xFF1A = 0x30 to block resume signals*/ \ - { 0x0049, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Enable rising edge triggering interrupt*/ \ - { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* release WLON reset 0x04[16]=1*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /* Whole BB is reset */ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - { 0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0 }, /* XTAL_CLK gated*/ \ - { 0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ - -#define HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3)) }, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4) }, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*Set SDIO suspend local register*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait power state to suspend*/ - -#define HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0 }, /*clear suspend enable and power down enable*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*Set SDIO suspend local register*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /*wait power state to suspend*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0 }, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07=0x20 , SOP option to disable BG/MB*/ \ - { 0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /*0x67[5]=0 , BIT_PAPE_WLBT_SEL*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*0x04[10] = 1, enable SW LPS*/ \ - { 0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*Set SDIO suspend local register*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait power state to suspend*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*0x90[1]=0 , disable 32k clock*/ \ - { 0x0044, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ \ - { 0x0040, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x90 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ \ - { 0x0041, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x00 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ \ - { 0x0042, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x04 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ - -#define HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0 }, /*clear suspend enable and power down enable*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*Set SDIO suspend local register*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /*wait power state to suspend*/ \ - { 0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0 }, /*0x04[12:11] = 2b'01enable WL suspend*/ \ - { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*PCIe DMA start*/ - - -#define HALMAC_RTL8822B_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ - { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* 0x04[16] = 0*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /* 0x04[15] = 1*/ - -#define HALMAC_RTL8822B_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 },/* 0x04[15] = 0*/ - -#define HALMAC_RTL8822B_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*Enable 32k calibration and thermal meter*/ \ - { 0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /*Register write data of 32K calibration*/ \ - { 0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*Enable 32k calibration reg write*/ \ - { 0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1) }, /*set RPWM IMR*/ \ - { 0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable 32K CLK*/ \ - { 0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x42 }, /* LPS Option MAC OFF enable*/ \ - { 0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /* LPS Option Enable memory to deep sleep mode*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /* enable reg use 32K CLK*/ \ - { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*PCIe DMA stop*/ \ - { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*Tx Pause*/ \ - { 0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*CCK and OFDM are disabled,and clock are gated*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US }, /*Delay 1us*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Whole BB is reset*/ \ - { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F }, /*Reset MAC TRX*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*check if removed later*/ \ - { 0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*Respond TxOK to scheduler*/ \ - { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* switch TSF clock to 32K*/ \ - { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7) }, /*Polling 0x109[7]=0 TSF in 40M*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable WL_LPS_EN*/ - -#define HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*Enable 32k calibration and thermal meter*/ \ - { 0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /*Register write data of 32K calibration*/ \ - { 0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*Enable 32k calibration reg write*/ \ - { 0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1) }, /*set RPWM IMR*/ \ - { 0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable 32K CLK*/ \ - { 0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x40 }, /* LPS Option MAC OFF enable*/ \ - { 0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /* LPS Option Enable memory to deep sleep mode*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /* enable reg use 32K CLK*/ \ - { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*PCIe DMA stop*/ \ - { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*Tx Pause*/ \ - { 0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*CCK and OFDM are disabled,and clock are gated*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US }, /*Delay 1us*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Whole BB is reset*/ \ - { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F }, /*Reset MAC TRX*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*check if removed later*/ \ - { 0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*Respond TxOK to scheduler*/ \ - { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* switch TSF clock to 32K*/ \ - { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7) }, /*Polling 0x109[7]=1 TSF in 32K*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable WL_LPS_EN*/ - -#define HALMAC_RTL8822B_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*SDIO RPWM*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS }, /*Delay*/ \ - { 0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /*SDIO RPWM*/ \ - { 0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84 }, /*USB RPWM*/ \ - { 0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84 }, /*PCIe RPWM*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS }, /*Delay*/ \ - { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /*. 0x08[4] = 0 switch TSF to 40M*/ \ - { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), 0 }, /*Polling 0x109[7]=0 TSF in 40M*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /*. 0x101[1] = 1*/ \ - { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0) }, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \ - { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*. 0x522 = 0*/ \ - { 0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x03 }, /*clear RPWM INT*/ \ - { 0x0124, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \ - { 0x0125, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \ - { 0x0126, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \ - { 0x0127, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /* disable reg use 32K CLK*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0 }, /*disable 32k calibration and thermal meter*/ + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ -#define HALMAC_RTL8822B_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0 }, /* */ +#ifndef HALMAC_POWER_SEQUENCE_8822B +#define HALMAC_POWER_SEQUENCE_8822B +#include "../../halmac_pwr_seq_cmd.h" -extern HALMAC_WLAN_PWR_CFG halmac_8822b_power_on_flow[HALMAC_8822B_TRANS_CARDEMU_TO_ACT_STEPS + HALMAC_8822B_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8822b_radio_off_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8822b_card_disable_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8822B_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8822b_card_enable_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8822B_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8822b_suspend_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8822B_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8822b_resume_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8822B_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8822b_hwpdn_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8822B_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8822b_enter_lps_flow[HALMAC_8822B_TRANS_ACT_TO_LPS_STEPS + HALMAC_8822B_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8822b_enter_deep_lps_flow[HALMAC_8822B_TRANS_ACT_TO_DEEP_LPS_STEPS + HALMAC_8822B_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8822b_leave_lps_flow[HALMAC_8822B_TRANS_LPS_TO_ACT_STEPS + HALMAC_8822B_TRANS_END_STEPS]; +#define HALMAC_8822B_PWR_SEQ_VER "V21" +extern PHALMAC_WLAN_PWR_CFG halmac_8822b_card_disable_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8822b_card_enable_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8822b_suspend_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8822b_resume_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8822b_hwpdn_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8822b_enter_lps_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8822b_enter_deep_lps_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8822b_leave_lps_flow[]; #endif diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.c index 440eec1..7dcca57 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.c +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.c @@ -1,7 +1,22 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "halmac_8822b_cfg.h" #include "halmac_func_8822b.h" #include "../halmac_func_88xx.h" - +#include "halmac_gpio_8822b.h" /** * halmac_mount_api_8822b() - attach functions to function pointer @@ -28,35 +43,51 @@ halmac_mount_api_8822b( pHalmac_adapter->hw_config_info.rxdesc_size = HALMAC_RX_DESC_SIZE_8822B; pHalmac_adapter->hw_config_info.tx_fifo_size = HALMAC_TX_FIFO_SIZE_8822B; pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_8822B; + pHalmac_adapter->hw_config_info.page_size = HALMAC_TX_PAGE_SIZE_8822B; + pHalmac_adapter->hw_config_info.tx_align_size = HALMAC_TX_ALIGN_SIZE_8822B; + pHalmac_adapter->hw_config_info.page_size_2_power = HALMAC_TX_PAGE_SIZE_2_POWER_8822B; pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = HALMAC_RSVD_DRV_PGNUM_8822B; #if HALMAC_8822B_SUPPORT pHalmac_api->halmac_init_trx_cfg = halmac_init_trx_cfg_8822b; + pHalmac_api->halmac_init_protocol_cfg = halmac_init_protocol_cfg_8822b; pHalmac_api->halmac_init_h2c = halmac_init_h2c_8822b; + pHalmac_api->halmac_pinmux_get_func = halmac_pinmux_get_func_8822b; + pHalmac_api->halmac_pinmux_set_func = halmac_pinmux_set_func_8822b; + pHalmac_api->halmac_pinmux_free_func = halmac_pinmux_free_func_8822b; - if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { - pHalmac_api->halmac_tx_allowed_sdio = halmac_tx_allowed_sdio_8822b; + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { + pHalmac_api->halmac_tx_allowed_sdio = halmac_tx_allowed_sdio_88xx; pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_sdio_not_support_88xx; pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8822b_sdio; - } else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) { + pHalmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_sdio; + pHalmac_api->halmac_interface_integration_tuning = halmac_interface_integration_tuning_8822b_sdio; + } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) { pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8822b_usb; pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_usb_not_support_88xx; - } else if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) { + pHalmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_usb; + pHalmac_api->halmac_interface_integration_tuning = halmac_interface_integration_tuning_8822b_usb; + } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) { pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8822b_pcie; pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_pcie_not_support_88xx; + pHalmac_api->halmac_pcie_switch = halmac_pcie_switch_8822b; + pHalmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_pcie; + pHalmac_api->halmac_interface_integration_tuning = halmac_interface_integration_tuning_8822b_pcie; + } else { + pHalmac_api->halmac_pcie_switch = halmac_pcie_switch_8822b_nc; } #endif return HALMAC_RET_SUCCESS; } - /** * halmac_init_trx_cfg_8822b() - config trx dma register - * @pHalmac_adapter - * @halmac_trx_mode + * @pHalmac_adapter : the adapter of halmac + * @halmac_trx_mode : trx mode selection * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_init_trx_cfg_8822b( @@ -65,29 +96,26 @@ halmac_init_trx_cfg_8822b( ) { u8 value8; - u16 value16; u32 value32; VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_TRX_CFG); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; pHalmac_adapter->trx_mode = halmac_trx_mode; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg ==========>halmac_trx_mode = %d\n", halmac_trx_mode); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_trx_cfg ==========>halmac_trx_mode = %d\n", halmac_trx_mode); status = halmac_txdma_queue_mapping_8822b(pHalmac_adapter, halmac_trx_mode); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_txdma_queue_mapping fail!\n"); return status; } @@ -97,22 +125,16 @@ halmac_init_trx_cfg_8822b( value8 = HALMAC_CR_TRX_ENABLE_8822B; HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31)); - value16 = BIT_MAC_SEC_EN | BIT_32K_CAL_TMR_EN; - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_CR, (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_CR) | value16)); status = halmac_priority_queue_config_8822b(pHalmac_adapter, halmac_trx_mode); + if (pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode != HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_DRVINFO_SZ, HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B >> 3); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_txdma_queue_mapping fail!\n"); return status; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Init Network type\n"); - - value8 = (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 2) & ~BIT_MASK_NETYPE0); - value8 = (u8)(value8 | HALMAC_NETWORK_NO_LINK); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 2, value8); - /* Config H2C packet buffer */ value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_HEAD); value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B); @@ -146,16 +168,63 @@ halmac_init_trx_cfg_8822b( return HALMAC_RET_GET_H2C_SPACE_ERR; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_trx_cfg <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_init_protocol_cfg_8822b() - config protocol register + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_init_protocol_cfg_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u32 value32; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_init_protocol_cfg_8822b ==========>\n"); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AMPDU_MAX_TIME_V1, HALMAC_AMPDU_MAX_TIME_8822B); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); + + value32 = HALMAC_PROT_RTS_LEN_TH_8822B | (HALMAC_PROT_RTS_TX_TIME_TH_8822B << 8) | + (HALMAC_PROT_MAX_AGG_PKT_LIMIT_8822B << 16) | (HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8822B << 24); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PROT_MODE_CTRL, value32); + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BAR_MODE_CTRL + 2, HALMAC_BAR_RETRY_LIMIT_8822B | HALMAC_RA_TRY_RATE_AGG_LIMIT_8822B << 8); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_VOVI_SETTING, HALMAC_FAST_EDCA_VO_TH_8822B); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_VOVI_SETTING + 2, HALMAC_FAST_EDCA_VI_TH_8822B); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_BEBK_SETTING, HALMAC_FAST_EDCA_BE_TH_8822B); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_BEBK_SETTING + 2, HALMAC_FAST_EDCA_BK_TH_8822B); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_init_protocol_cfg_8822b <==========\n"); return HALMAC_RET_SUCCESS; } /** * halmac_init_h2c_8822b() - config h2c packet buffer - * @pHalmac_adapter + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_init_h2c_8822b( @@ -167,10 +236,10 @@ halmac_init_h2c_8822b( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.h index f5a5194..846a0d3 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.h +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_API_8822B_H_ #define _HALMAC_API_8822B_H_ @@ -15,6 +30,11 @@ halmac_init_trx_cfg_8822b( IN HALMAC_TRX_MODE halmac_trx_mode ); +HALMAC_RET_STATUS +halmac_init_protocol_cfg_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter +); + HALMAC_RET_STATUS halmac_init_h2c_8822b( IN PHALMAC_ADAPTER pHalmac_adapter diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c index 5b09c10..471d452 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c @@ -1,13 +1,29 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "../halmac_88xx_cfg.h" +#include "../halmac_api_88xx_pcie.h" #include "halmac_8822b_cfg.h" - /** - * halmac_mac_power_switch_8822b_pcie() - change mac power - * @pHalmac_adapter - * @halmac_power + * halmac_mac_power_switch_8822b_pcie() - switch mac power + * @pHalmac_adapter : the adapter of halmac + * @halmac_power : power state * Author : KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_mac_power_switch_8822b_pcie( @@ -16,53 +32,234 @@ halmac_mac_power_switch_8822b_pcie( ) { u8 interface_mask; + u8 value8; VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MAC_POWER_SWITCH); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_mac_power_switch_88xx_pcie halmac_power = %x ==========>\n", halmac_power); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_mac_power_switch_88xx_pcie halmac_power = %x ==========>\n", halmac_power); interface_mask = HALMAC_PWR_INTF_PCI_MSK; - if (0xEA == HALMAC_REG_READ_8(pHalmac_adapter, REG_CR)) + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR); + if (value8 == 0xEA) pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; + else + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; /* Check if power switch is needed */ - if (halmac_power == pHalmac_adapter->halmac_state.mac_power) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "halmac_mac_power_switch power state unchange!\n"); + if (halmac_power == HALMAC_MAC_POWER_ON && pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "[WARN]halmac_mac_power_switch power state unchange!\n"); + return HALMAC_RET_PWR_UNCHANGE; + } + + if (halmac_power == HALMAC_MAC_POWER_OFF) { + if (halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, + interface_mask, halmac_8822b_card_disable_flow) != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Handle power off cmd error\n"); + return HALMAC_RET_POWER_OFF_FAIL; + } + + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; + pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE; + pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter); } else { - if (HALMAC_MAC_POWER_OFF == halmac_power) { - if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_TESTCHIP_MSK, HALMAC_PWR_FAB_TSMC_MSK, - interface_mask, halmac_8822b_card_disable_flow)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power off cmd error\n"); - return HALMAC_RET_POWER_OFF_FAIL; - } - - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE; - pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; - } else { - if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_TESTCHIP_MSK, HALMAC_PWR_FAB_TSMC_MSK, - interface_mask, halmac_8822b_card_enable_flow)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power on cmd error\n"); - return HALMAC_RET_POWER_ON_FAIL; - } - - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT; + if (halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, + interface_mask, halmac_8822b_card_enable_flow) != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Handle power on cmd error\n"); + return HALMAC_RET_POWER_ON_FAIL; } + + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; + pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_mac_power_switch_88xx_pcie <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_mac_power_switch_88xx_pcie <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pcie_switch_8822b() - pcie gen1/gen2 switch + * @pHalmac_adapter : the adapter of halmac + * @pcie_cfg : gen1/gen2 selection + * Author : KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_pcie_switch_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PCIE_CFG pcie_cfg +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + u8 current_link_speed = 0; + u32 count = 0; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_pcie_switch_8822b ==========>\n"); + + /** + * Link Control 2 Register[3:0] Target Link Speed + * Defined encodings are: + * 0001b Target Link 2.5 GT/s + * 0010b Target Link 5.0 GT/s + * 0100b Target Link 8.0 GT/s + */ + + if (pcie_cfg == HALMAC_PCIE_GEN1) { + /* cfg 0xA0[3:0]=4'b0001 */ + halmac_dbi_write8_88xx(pHalmac_adapter, LINK_CTRL2_REG_OFFSET, (halmac_dbi_read8_88xx(pHalmac_adapter, LINK_CTRL2_REG_OFFSET) & 0xF0) | BIT(0)); + + /* cfg 0x80C[17]=1 //PCIe DesignWave */ + halmac_dbi_write32_88xx(pHalmac_adapter, GEN2_CTRL_OFFSET, halmac_dbi_read32_88xx(pHalmac_adapter, GEN2_CTRL_OFFSET) | BIT(17)); + + /* check link speed if GEN1 */ + /* cfg 0x82[3:0]=4'b0001 */ + current_link_speed = halmac_dbi_read8_88xx(pHalmac_adapter, LINK_STATUS_REG_OFFSET) & 0x0F; + count = 2000; + + while ((current_link_speed != HALMAC_PCIE_GEN1_SPEED_88XX) && (count != 0)) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); + current_link_speed = halmac_dbi_read8_88xx(pHalmac_adapter, LINK_STATUS_REG_OFFSET) & 0x0F; + count--; + } + + if (current_link_speed != HALMAC_PCIE_GEN1_SPEED_88XX) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Speed change to GEN1 fail !\n"); + return HALMAC_RET_FAIL; + } + + } else if (pcie_cfg == HALMAC_PCIE_GEN2) { + /* cfg 0xA0[3:0]=4'b0010 */ + halmac_dbi_write8_88xx(pHalmac_adapter, LINK_CTRL2_REG_OFFSET, (halmac_dbi_read8_88xx(pHalmac_adapter, LINK_CTRL2_REG_OFFSET) & 0xF0) | BIT(1)); + + /* cfg 0x80C[17]=1 //PCIe DesignWave */ + halmac_dbi_write32_88xx(pHalmac_adapter, GEN2_CTRL_OFFSET, halmac_dbi_read32_88xx(pHalmac_adapter, GEN2_CTRL_OFFSET) | BIT(17)); + + /* check link speed if GEN2 */ + /* cfg 0x82[3:0]=4'b0010 */ + current_link_speed = halmac_dbi_read8_88xx(pHalmac_adapter, LINK_STATUS_REG_OFFSET) & 0x0F; + count = 2000; + + while ((current_link_speed != HALMAC_PCIE_GEN2_SPEED_88XX) && (count != 0)) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); + current_link_speed = halmac_dbi_read8_88xx(pHalmac_adapter, LINK_STATUS_REG_OFFSET) & 0x0F; + count--; + } + + if (current_link_speed != HALMAC_PCIE_GEN2_SPEED_88XX) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Speed change to GEN1 fail !\n"); + return HALMAC_RET_FAIL; + } + + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Error Speed !\n"); + return HALMAC_RET_FAIL; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_pcie_switch_8822b <==========\n"); + + return HALMAC_RET_SUCCESS; +} +HALMAC_RET_STATUS +halmac_pcie_switch_8822b_nc( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PCIE_CFG pcie_cfg +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_pcie_switch_8822b_nc ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_pcie_switch_8822b_nc <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_phy_cfg_8822b_pcie() - phy config + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_phy_cfg_8822b_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_INTF_PHY_PLATFORM platform +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + PHALMAC_API pHalmac_api; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_phy_cfg ==========>\n"); + + status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8822B_PCIE_PHY_GEN1, platform, HAL_INTF_PHY_PCIE_GEN1); + + if (status != HALMAC_RET_SUCCESS) + return status; + + status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8822B_PCIE_PHY_GEN2, platform, HAL_INTF_PHY_PCIE_GEN2); + + if (status != HALMAC_RET_SUCCESS) + return status; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_phy_cfg <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_interface_integration_tuning_8822b_pcie() - pcie interface fine tuning + * @pHalmac_adapter : the adapter of halmac + * Author : Rick Liu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_interface_integration_tuning_8822b_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ return HALMAC_RET_SUCCESS; } diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h index 9c3763f..2371c19 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h @@ -1,13 +1,54 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_API_8822B_PCIE_H_ #define _HALMAC_API_8822B_PCIE_H_ #include "../../halmac_2_platform.h" #include "../../halmac_type.h" +extern HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_PCIE_PHY_GEN1[]; +extern HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_PCIE_PHY_GEN2[]; + HALMAC_RET_STATUS halmac_mac_power_switch_8822b_pcie( IN PHALMAC_ADAPTER pHalmac_adapter, IN HALMAC_MAC_POWER halmac_power ); +HALMAC_RET_STATUS +halmac_pcie_switch_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PCIE_CFG pcie_cfg +); + +HALMAC_RET_STATUS +halmac_pcie_switch_8822b_nc( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PCIE_CFG pcie_cfg +); + +HALMAC_RET_STATUS +halmac_phy_cfg_8822b_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_INTF_PHY_PLATFORM platform +); + +HALMAC_RET_STATUS +halmac_interface_integration_tuning_8822b_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter +); + #endif/* _HALMAC_API_8822B_PCIE_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c index 63fe7c1..50d1407 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c @@ -1,11 +1,27 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "halmac_8822b_cfg.h" /** - * halmac_mac_power_switch_8822b_sdio() - change mac power - * @pHalmac_adapter - * @halmac_power + * halmac_mac_power_switch_8822b_sdio() - switch mac power + * @pHalmac_adapter : the adapter of halmac + * @halmac_power : power state * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_mac_power_switch_8822b_sdio( @@ -14,199 +30,127 @@ halmac_mac_power_switch_8822b_sdio( ) { u8 interface_mask; + u8 value8; u8 rpwm; + u32 imr_backup; VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MAC_POWER_SWITCH); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_mac_power_switch_88xx_sdio halmac_power = %x ==========>\n", halmac_power); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_mac_power_switch_88xx_sdio==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_power = %x ==========>\n", halmac_power); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]8822B pwr seq ver = %s\n", HALMAC_8822B_PWR_SEQ_VER); interface_mask = HALMAC_PWR_INTF_SDIO_MSK; pHalmac_adapter->rpwm_record = HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HRPWM1); /* Check FW still exist or not */ - if (0xC078 == HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL)) { + if (HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) == 0xC078) { /* Leave 32K */ rpwm = (u8)((pHalmac_adapter->rpwm_record ^ BIT(7)) & 0x80); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HRPWM1, rpwm); } - if (0xEA == HALMAC_REG_READ_8(pHalmac_adapter, REG_CR)) + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR); + if (value8 == 0xEA) pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; + else + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; /*Check if power switch is needed*/ - if (halmac_power == pHalmac_adapter->halmac_state.mac_power) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "halmac_mac_power_switch power state unchange!\n"); + if (halmac_power == HALMAC_MAC_POWER_ON && pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "[WARN]halmac_mac_power_switch power state unchange!\n"); + return HALMAC_RET_PWR_UNCHANGE; + } + + imr_backup = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_HIMR); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_HIMR, 0); + + if (halmac_power == HALMAC_MAC_POWER_OFF) { + if (halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, + interface_mask, halmac_8822b_card_disable_flow) != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Handle power off cmd error\n"); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_HIMR, imr_backup); + return HALMAC_RET_POWER_OFF_FAIL; + } + + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; + pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE; + pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter); } else { - if (HALMAC_MAC_POWER_OFF == halmac_power) { - if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_TESTCHIP_MSK, HALMAC_PWR_FAB_TSMC_MSK, - interface_mask, halmac_8822b_card_disable_flow)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power off cmd error\n"); - return HALMAC_RET_POWER_OFF_FAIL; - } - - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE; - pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; - } else { - if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_TESTCHIP_MSK, HALMAC_PWR_FAB_TSMC_MSK, - interface_mask, halmac_8822b_card_enable_flow)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power on cmd error\n"); - return HALMAC_RET_POWER_ON_FAIL; - } - - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT; + if (halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, + interface_mask, halmac_8822b_card_enable_flow) != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Handle power on cmd error\n"); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_HIMR, imr_backup); + return HALMAC_RET_POWER_ON_FAIL; } + + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; + pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_mac_power_switch_88xx_sdio <==========\n"); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_HIMR, imr_backup); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_mac_power_switch_88xx_sdio <==========\n"); return HALMAC_RET_SUCCESS; } /** - * halmac_tx_allowed_sdio_8822b() - check sdio tx reserved page - * @pHalmac_adapter - * @pHalmac_buf - * @halmac_size - * Author : Ivan Lin + * halmac_phy_cfg_8822b_sdio() - phy config + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS -halmac_tx_allowed_sdio_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHalmac_buf, - IN u32 halmac_size +halmac_phy_cfg_8822b_sdio( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_INTF_PHY_PLATFORM platform ) { - u8 *pCurr_packet; - u16 *pCurr_free_space; - u32 i, counter; - u32 tx_agg_num, packet_size; - u32 tx_required_page_num, total_required_page_num = 0; VOID *pDriver_adapter = NULL; - HALMAC_DMA_MAPPING dma_mapping; + PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_TX_ALLOWED_SDIO); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_tx_allowed_sdio_8822b ==========>\n"); - - tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(pHalmac_buf); - pCurr_packet = pHalmac_buf; - - tx_agg_num = (tx_agg_num == 0) ? 1 : tx_agg_num; - - switch ((HALMAC_QUEUE_SELECT)GET_TX_DESC_QSEL(pCurr_packet)) { - case HALMAC_QUEUE_SELECT_VO: - case HALMAC_QUEUE_SELECT_VO_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]; - break; - case HALMAC_QUEUE_SELECT_VI: - case HALMAC_QUEUE_SELECT_VI_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]; - break; - case HALMAC_QUEUE_SELECT_BE: - case HALMAC_QUEUE_SELECT_BE_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]; - break; - case HALMAC_QUEUE_SELECT_BK: - case HALMAC_QUEUE_SELECT_BK_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]; - break; - case HALMAC_QUEUE_SELECT_MGNT: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]; - break; - case HALMAC_QUEUE_SELECT_HIGH: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]; - break; - case HALMAC_QUEUE_SELECT_BCN: - case HALMAC_QUEUE_SELECT_CMD: - return HALMAC_RET_SUCCESS; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Qsel is out of range\n"); - return HALMAC_RET_QSEL_INCORRECT; - } - - switch (dma_mapping) { - case HALMAC_DMA_MAPPING_HIGH: - pCurr_free_space = &(pHalmac_adapter->sdio_free_space.high_queue_number); - break; - case HALMAC_DMA_MAPPING_NORMAL: - pCurr_free_space = &(pHalmac_adapter->sdio_free_space.normal_queue_number); - break; - case HALMAC_DMA_MAPPING_LOW: - pCurr_free_space = &(pHalmac_adapter->sdio_free_space.low_queue_number); - break; - case HALMAC_DMA_MAPPING_EXTRA: - pCurr_free_space = &(pHalmac_adapter->sdio_free_space.extra_queue_number); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "DmaMapping is out of range\n"); - return HALMAC_RET_DMA_MAP_INCORRECT; - } - - for (i = 0; i < tx_agg_num; i++) { - packet_size = GET_TX_DESC_TXPKTSIZE(pCurr_packet) + GET_TX_DESC_OFFSET(pCurr_packet); - tx_required_page_num = (packet_size >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B) + ((packet_size & (HALMAC_TX_PAGE_SIZE_8822B - 1)) ? 1 : 0); - total_required_page_num += tx_required_page_num; - - packet_size = HALMAC_ALIGN(packet_size, 8); - - pCurr_packet += packet_size; - } - - counter = 10; - while (1) { - if ((u32)(*pCurr_free_space + pHalmac_adapter->sdio_free_space.public_queue_number) >= total_required_page_num) { - if (*pCurr_free_space >= total_required_page_num) { - *pCurr_free_space -= (u16)total_required_page_num; - } else { - pHalmac_adapter->sdio_free_space.public_queue_number -= (u16)(total_required_page_num - *pCurr_free_space); - *pCurr_free_space = 0; - } - break; - } else { - halmac_update_sdio_free_page_88xx(pHalmac_adapter); - } - - counter--; - if (0 == counter) - return HALMAC_RET_FREE_SPACE_NOT_ENOUGH; - } - - counter = 10; - while (pHalmac_adapter->sdio_free_space.ac_oqt_number < tx_agg_num) { - halmac_update_oqt_free_space_88xx(pHalmac_adapter); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg ==========>\n"); - counter--; - if (0 == counter) - return HALMAC_RET_FREE_SPACE_NOT_ENOUGH; - } - pHalmac_adapter->sdio_free_space.ac_oqt_number -= (u8)tx_agg_num; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "sdio no phy\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_tx_allowed_sdio_8822b <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg <==========\n"); return HALMAC_RET_SUCCESS; } - +/** + * halmac_interface_integration_tuning_8822b_sdio() - sdio interface fine tuning + * @pHalmac_adapter : the adapter of halmac + * Author : Ivan + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_interface_integration_tuning_8822b_sdio( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + return HALMAC_RET_SUCCESS; +} \ No newline at end of file diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h index 5d61a8b..36b70ac 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_API_8822B_SDIO_H_ #define _HALMAC_API_8822B_SDIO_H_ @@ -10,11 +25,24 @@ halmac_mac_power_switch_8822b_sdio( IN HALMAC_MAC_POWER halmac_power ); +#if 0 HALMAC_RET_STATUS halmac_tx_allowed_sdio_8822b( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pHalmac_buf, IN u32 halmac_size ); +#endif + +HALMAC_RET_STATUS +halmac_phy_cfg_8822b_sdio( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_INTF_PHY_PLATFORM platform +); + +HALMAC_RET_STATUS +halmac_interface_integration_tuning_8822b_sdio( + IN PHALMAC_ADAPTER pHalmac_adapter +); #endif/* _HALMAC_API_8822B_SDIO_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c index 95f26c4..f7956f4 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c @@ -1,12 +1,28 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "../halmac_88xx_cfg.h" #include "halmac_8822b_cfg.h" /** - * halmac_mac_power_switch_8822b_usb() - change mac power - * @pHalmac_adapter - * @halmac_power + * halmac_mac_power_switch_8822b_usb() - switch mac power + * @pHalmac_adapter : the adapter of halmac + * @halmac_power : power state * Author : KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_mac_power_switch_8822b_usb( @@ -15,54 +31,132 @@ halmac_mac_power_switch_8822b_usb( ) { u8 interface_mask; + u8 value8; + u8 rpwm; VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MAC_POWER_SWITCH); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_mac_power_switch_88xx_usb halmac_power = %x ==========>\n", halmac_power); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_mac_power_switch_88xx_usb halmac_power = %x ==========>\n", halmac_power); interface_mask = HALMAC_PWR_INTF_USB_MSK; - if (0xEA == HALMAC_REG_READ_8(pHalmac_adapter, REG_CR)) + pHalmac_adapter->rpwm_record = HALMAC_REG_READ_8(pHalmac_adapter, 0xFE58); + + /* Check FW still exist or not */ + if (HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) == 0xC078) { + /* Leave 32K */ + rpwm = (u8)((pHalmac_adapter->rpwm_record ^ BIT(7)) & 0x80); + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xFE58, rpwm); + } + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR); + if (value8 == 0xEA) { pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; + } else { + if (BIT(0) == (HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_STATUS1 + 1) & BIT(0))) + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; + else + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; + } /*Check if power switch is needed*/ - if (halmac_power == pHalmac_adapter->halmac_state.mac_power) { + if (halmac_power == HALMAC_MAC_POWER_ON && pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "halmac_mac_power_switch power state unchange!\n"); - } else { - if (HALMAC_MAC_POWER_OFF == halmac_power) { - if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_TESTCHIP_MSK, HALMAC_PWR_FAB_TSMC_MSK, - interface_mask, halmac_8822b_card_disable_flow)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power off cmd error\n"); - return HALMAC_RET_POWER_OFF_FAIL; - } + return HALMAC_RET_PWR_UNCHANGE; + } - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE; - pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; - } else { - if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_TESTCHIP_MSK, HALMAC_PWR_FAB_TSMC_MSK, - interface_mask, halmac_8822b_card_enable_flow)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power on cmd error\n"); - return HALMAC_RET_POWER_ON_FAIL; - } + if (halmac_power == HALMAC_MAC_POWER_OFF) { + if (halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, + interface_mask, halmac_8822b_card_disable_flow) != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power off cmd error\n"); + return HALMAC_RET_POWER_OFF_FAIL; + } - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT; + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; + pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE; + pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter); + } else { + if (halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, + interface_mask, halmac_8822b_card_enable_flow) != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power on cmd error\n"); + return HALMAC_RET_POWER_ON_FAIL; } + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_STATUS1 + 1, HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_STATUS1 + 1) & ~(BIT(0))); + + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; + pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_mac_power_switch_88xx_usb <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_mac_power_switch_88xx_usb <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_phy_cfg_8822b_usb() - phy config + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_phy_cfg_8822b_usb( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_INTF_PHY_PLATFORM platform +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + PHALMAC_API pHalmac_api; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg ==========>\n"); + + status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8822B_USB2_PHY, platform, HAL_INTF_PHY_USB2); + if (status != HALMAC_RET_SUCCESS) + return status; + + status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8822B_USB3_PHY, platform, HAL_INTF_PHY_USB3); + + if (status != HALMAC_RET_SUCCESS) + return status; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_interface_integration_tuning_8822b_usb() - usb interface fine tuning + * @pHalmac_adapter : the adapter of halmac + * Author : Ivan + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_interface_integration_tuning_8822b_usb( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ return HALMAC_RET_SUCCESS; } diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h index 7105d8d..fdae4e2 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h @@ -1,6 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_API_8822B_USB_H_ #define _HALMAC_API_8822B_USB_H_ +extern HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_USB2_PHY[]; +extern HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_USB3_PHY[]; + #include "../../halmac_2_platform.h" #include "../../halmac_type.h" @@ -9,4 +27,16 @@ halmac_mac_power_switch_8822b_usb( IN PHALMAC_ADAPTER pHalmac_adapter, IN HALMAC_MAC_POWER halmac_power ); + +HALMAC_RET_STATUS +halmac_phy_cfg_8822b_usb( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_INTF_PHY_PLATFORM platform +); + +HALMAC_RET_STATUS +halmac_interface_integration_tuning_8822b_usb( + IN PHALMAC_ADAPTER pHalmac_adapter +); + #endif/* _HALMAC_API_8822B_USB_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.c index e2e27a1..8b80fc3 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.c +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.c @@ -1,4 +1,154 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "halmac_8822b_cfg.h" +#if HALMAC_PLATFORM_WINDOWS +/*SDIO RQPN Mapping for Windows, extra queue is not implemented in Driver code*/ +HALMAC_RQPN HALMAC_RQPN_SDIO_8822B[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, +}; +#else +/*SDIO RQPN Mapping*/ +HALMAC_RQPN HALMAC_RQPN_SDIO_8822B[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, +}; +#endif + +/*PCIE RQPN Mapping*/ +HALMAC_RQPN HALMAC_RQPN_PCIE_8822B[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, +}; + +/*USB 2 Bulkout RQPN Mapping*/ +HALMAC_RQPN HALMAC_RQPN_2BULKOUT_8822B[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, +}; + +/*USB 3 Bulkout RQPN Mapping*/ +HALMAC_RQPN HALMAC_RQPN_3BULKOUT_8822B[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, +}; + +/*USB 4 Bulkout RQPN Mapping*/ +HALMAC_RQPN HALMAC_RQPN_4BULKOUT_8822B[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, +}; + +#if HALMAC_PLATFORM_WINDOWS +/*SDIO Page Number*/ +HALMAC_PG_NUM HALMAC_PG_NUM_SDIO_8822B[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 0, 1}, + {HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 640}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 640}, +}; +#else +/*SDIO Page Number*/ +HALMAC_PG_NUM HALMAC_PG_NUM_SDIO_8822B[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 32, 1}, + {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640}, +}; +#endif + +/*PCIE Page Number*/ +HALMAC_PG_NUM HALMAC_PG_NUM_PCIE_8822B[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640}, +}; + +/*USB 2 Bulkout Page Number*/ +HALMAC_PG_NUM HALMAC_PG_NUM_2BULKOUT_8822B[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 64, 64, 0, 0, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 0, 0, 1}, + {HALMAC_TRX_MODE_WMM, 64, 64, 0, 0, 1}, + {HALMAC_TRX_MODE_P2P, 64, 64, 0, 0, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1024}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1024}, +}; + +/*USB 3 Bulkout Page Number*/ +HALMAC_PG_NUM HALMAC_PG_NUM_3BULKOUT_8822B[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1024}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1024}, +}; + +/*USB 4 Bulkout Page Number*/ +HALMAC_PG_NUM HALMAC_PG_NUM_4BULKOUT_8822B[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640}, +}; HALMAC_RET_STATUS halmac_txdma_queue_mapping_8822b( @@ -8,143 +158,36 @@ halmac_txdma_queue_mapping_8822b( { u16 value16; VOID *pDriver_adapter = NULL; + PHALMAC_RQPN pCurr_rqpn_Sel = NULL; + HALMAC_RET_STATUS status; PHALMAC_API pHalmac_api; pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - /* Default mapping (PCIE + SDIO + USB 4 bulkout) */ - switch (halmac_trx_mode) { - case HALMAC_TRX_MODE_NORMAL: - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_LOW; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_EXTRA; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - break; - case HALMAC_TRX_MODE_TRXSHARE: - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - break; - case HALMAC_TRX_MODE_WMM: - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_LOW; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_EXTRA; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - break; - case HALMAC_TRX_MODE_P2P: - case HALMAC_TRX_MODE_LOOPBACK: - case HALMAC_TRX_MODE_DELAY_LOOPBACK: - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_LOW; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_EXTRA; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg_8822b 0 switch case not support\n"); - return HALMAC_RET_TRX_MODE_NOT_SUPPORT; - } - - /* Extra mapping */ - if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) { + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { + pCurr_rqpn_Sel = HALMAC_RQPN_SDIO_8822B; + } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) { + pCurr_rqpn_Sel = HALMAC_RQPN_PCIE_8822B; + } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) { if (pHalmac_adapter->halmac_bulkout_num == 2) { - /* In USB 2 bulkout, only High and Normal queue can be used */ - switch (halmac_trx_mode) { - case HALMAC_TRX_MODE_NORMAL: - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - - break; - case HALMAC_TRX_MODE_TRXSHARE: - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - break; - case HALMAC_TRX_MODE_WMM: - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - break; - case HALMAC_TRX_MODE_P2P: - case HALMAC_TRX_MODE_LOOPBACK: - case HALMAC_TRX_MODE_DELAY_LOOPBACK: - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg_8822b 1 switch case not support\n"); - return HALMAC_RET_TRX_MODE_NOT_SUPPORT; - } + pCurr_rqpn_Sel = HALMAC_RQPN_2BULKOUT_8822B; } else if (pHalmac_adapter->halmac_bulkout_num == 3) { - /* in USB 3 bulkout, only High, Normal, Low queue can be used */ - switch (halmac_trx_mode) { - case HALMAC_TRX_MODE_NORMAL: - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_LOW; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - - break; - case HALMAC_TRX_MODE_TRXSHARE: - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - break; - case HALMAC_TRX_MODE_WMM: - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_EXTRA; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - break; - case HALMAC_TRX_MODE_P2P: - case HALMAC_TRX_MODE_LOOPBACK: - case HALMAC_TRX_MODE_DELAY_LOOPBACK: - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_NORMAL; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg_8822b 2 switch case not support\n"); - return HALMAC_RET_TRX_MODE_NOT_SUPPORT; - } + pCurr_rqpn_Sel = HALMAC_RQPN_3BULKOUT_8822B; + } else if (pHalmac_adapter->halmac_bulkout_num == 4) { + pCurr_rqpn_Sel = HALMAC_RQPN_4BULKOUT_8822B; + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]interface not support\n"); + return HALMAC_RET_NOT_SUPPORT; } + } else { + return HALMAC_RET_NOT_SUPPORT; } + status = halmac_rqpn_parser_88xx(pHalmac_adapter, halmac_trx_mode, pCurr_rqpn_Sel); + if (status != HALMAC_RET_SUCCESS) + return status; + value16 = 0; value16 |= BIT_TXDMA_HIQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]); value16 |= BIT_TXDMA_MGQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]); @@ -165,22 +208,32 @@ halmac_priority_queue_config_8822b( { u8 transfer_mode = 0; u8 value8; - u16 HPQ_num = 0, LPQ_Nnum = 0, NPQ_num = 0, GAPQ_num = 0; - u16 EXPQ_num = 0, PUBQ_num = 0; - u16 tx_page_boundary = 0, rx_f_ifo_boundary = 0; - u16 h2c_extra_info_boundary = 0, fw_txbuff_boundary = 0; u32 counter; + HALMAC_RET_STATUS status; + PHALMAC_PG_NUM pCurr_pg_num = NULL; VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - if (HALMAC_LA_MODE_DISABLE == pHalmac_adapter->txff_allocation.la_mode) - pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_8822B >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B; - else + if (pHalmac_adapter->txff_allocation.la_mode == HALMAC_LA_MODE_DISABLE) { + if (pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode == HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) { + pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_8822B >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B; + } else if (pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode == HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK) { + pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B; + pHalmac_adapter->hw_config_info.tx_fifo_size = HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B; + if (HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B <= HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_MAX_8822B) + pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B; + else + pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_MAX_8822B; + } else { + pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_8822B >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]rx_fifo_expanding_mode = %d not support\n", pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode); + } + } else { pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_LA_8822B >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B; - + } pHalmac_adapter->txff_allocation.rsvd_pg_num = (pHalmac_adapter->txff_allocation.rsvd_drv_pg_num + HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B + HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B + @@ -197,173 +250,58 @@ halmac_priority_queue_config_8822b( pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy - HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B; pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_drv_pg_num; - /* Default setting (PCIE + SDIO + USB 4 bulkout) */ - switch (halmac_trx_mode) { - case HALMAC_TRX_MODE_NORMAL: - HPQ_num = HALMAC_NORMAL_HPQ_PGNUM_8822B; - LPQ_Nnum = HALMAC_NORMAL_LPQ_PGNUM_8822B; - NPQ_num = HALMAC_NORMAL_NPQ_PGNUM_8822B; - EXPQ_num = HALMAC_NORMAL_EXPQ_PGNUM_8822B; - GAPQ_num = HALMAC_NORMAL_GAP_PGNUM_8822B; - PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num; - rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - HALMAC_WOWLAN_PATTERN_SIZE_8822B - 1; - transfer_mode = HALMAC_TRNSFER_NORMAL; - break; - case HALMAC_TRX_MODE_TRXSHARE: - break; - case HALMAC_TRX_MODE_WMM: - HPQ_num = HALMAC_WMM_HPQ_PGNUM_8822B; - LPQ_Nnum = HALMAC_WMM_LPQ_PGNUM_8822B; - NPQ_num = HALMAC_WMM_NPQ_PGNUM_8822B; - EXPQ_num = HALMAC_WMM_EXPQ_PGNUM_8822B; - GAPQ_num = HALMAC_WMM_GAP_PGNUM_8822B; - PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num; - rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - HALMAC_WOWLAN_PATTERN_SIZE_8822B - 1; - transfer_mode = HALMAC_TRNSFER_NORMAL; - break; - case HALMAC_TRX_MODE_P2P: - case HALMAC_TRX_MODE_LOOPBACK: - case HALMAC_TRX_MODE_DELAY_LOOPBACK: - HPQ_num = HALMAC_LB_HPQ_PGNUM_8822B; - LPQ_Nnum = HALMAC_LB_LPQ_PGNUM_8822B; - NPQ_num = HALMAC_LB_NPQ_PGNUM_8822B; - EXPQ_num = HALMAC_LB_EXPQ_PGNUM_8822B; - GAPQ_num = HALMAC_LB_GAP_PGNUM_8822B; - PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num; - rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - 1; - transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT; - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_WMAC_LBK_BUF_HD_V1, (u16)pHalmac_adapter->txff_allocation.rsvd_pg_bndy); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg_8822b 3 switch case not support\n"); - return HALMAC_RET_TRX_MODE_NOT_SUPPORT; - } - - /* Extra setting */ - if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) { + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { + pCurr_pg_num = HALMAC_PG_NUM_SDIO_8822B; + } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) { + pCurr_pg_num = HALMAC_PG_NUM_PCIE_8822B; + } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) { if (pHalmac_adapter->halmac_bulkout_num == 2) { - /* In USB 2 bulkout, only High and Normal queue can be used */ - switch (halmac_trx_mode) { - case HALMAC_TRX_MODE_NORMAL: - HPQ_num = HALMAC_NORMAL_2BULKOUT_HPQ_PGNUM_8822B; - LPQ_Nnum = HALMAC_NORMAL_2BULKOUT_LPQ_PGNUM_8822B; - NPQ_num = HALMAC_NORMAL_2BULKOUT_NPQ_PGNUM_8822B; - EXPQ_num = HALMAC_NORMAL_2BULKOUT_EXPQ_PGNUM_8822B; - GAPQ_num = HALMAC_NORMAL_2BULKOUT_GAP_PGNUM_8822B; - PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num; - rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - HALMAC_WOWLAN_PATTERN_SIZE_8822B - 1; - transfer_mode = HALMAC_TRNSFER_NORMAL; - break; - case HALMAC_TRX_MODE_TRXSHARE: - break; - case HALMAC_TRX_MODE_WMM: - HPQ_num = HALMAC_WMM_HPQ_PGNUM_8822B; - LPQ_Nnum = HALMAC_WMM_LPQ_PGNUM_8822B; - NPQ_num = HALMAC_WMM_NPQ_PGNUM_8822B; - EXPQ_num = HALMAC_WMM_EXPQ_PGNUM_8822B; - GAPQ_num = HALMAC_WMM_GAP_PGNUM_8822B; - PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num; - rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - HALMAC_WOWLAN_PATTERN_SIZE_8822B - 1; - transfer_mode = HALMAC_TRNSFER_NORMAL; - break; - case HALMAC_TRX_MODE_P2P: - case HALMAC_TRX_MODE_LOOPBACK: - case HALMAC_TRX_MODE_DELAY_LOOPBACK: - HPQ_num = HALMAC_LB_2BULKOUT_HPQ_PGNUM_8822B; - LPQ_Nnum = HALMAC_LB_2BULKOUT_LPQ_PGNUM_8822B; - NPQ_num = HALMAC_LB_2BULKOUT_NPQ_PGNUM_8822B; - EXPQ_num = HALMAC_LB_2BULKOUT_EXPQ_PGNUM_8822B; - GAPQ_num = HALMAC_LB_2BULKOUT_GAP_PGNUM_8822B; - PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num; - rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - 1; - transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT; - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_WMAC_LBK_BUF_HD_V1, (u16)pHalmac_adapter->txff_allocation.rsvd_pg_bndy); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg_8822b 4 switch case not support\n"); - return HALMAC_RET_TRX_MODE_NOT_SUPPORT; - } + pCurr_pg_num = HALMAC_PG_NUM_2BULKOUT_8822B; } else if (pHalmac_adapter->halmac_bulkout_num == 3) { - /* in USB 3 bulkout, only High, Normal, Low queue can be used */ - switch (halmac_trx_mode) { - case HALMAC_TRX_MODE_NORMAL: - HPQ_num = HALMAC_NORMAL_3BULKOUT_HPQ_PGNUM_8822B; - LPQ_Nnum = HALMAC_NORMAL_3BULKOUT_LPQ_PGNUM_8822B; - NPQ_num = HALMAC_NORMAL_3BULKOUT_NPQ_PGNUM_8822B; - EXPQ_num = HALMAC_NORMAL_3BULKOUT_EXPQ_PGNUM_8822B; - GAPQ_num = HALMAC_NORMAL_3BULKOUT_GAP_PGNUM_8822B; - PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num; - rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - HALMAC_WOWLAN_PATTERN_SIZE_8822B - 1; - transfer_mode = HALMAC_TRNSFER_NORMAL; - break; - case HALMAC_TRX_MODE_TRXSHARE: - break; - case HALMAC_TRX_MODE_WMM: - HPQ_num = HALMAC_WMM_HPQ_PGNUM_8822B; - LPQ_Nnum = HALMAC_WMM_LPQ_PGNUM_8822B; - NPQ_num = HALMAC_WMM_NPQ_PGNUM_8822B; - EXPQ_num = HALMAC_WMM_EXPQ_PGNUM_8822B; - GAPQ_num = HALMAC_WMM_GAP_PGNUM_8822B; - PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num; - rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - HALMAC_WOWLAN_PATTERN_SIZE_8822B - 1; - transfer_mode = HALMAC_TRNSFER_NORMAL; - break; - case HALMAC_TRX_MODE_P2P: - case HALMAC_TRX_MODE_LOOPBACK: - case HALMAC_TRX_MODE_DELAY_LOOPBACK: - HPQ_num = HALMAC_LB_3BULKOUT_HPQ_PGNUM_8822B; - LPQ_Nnum = HALMAC_LB_3BULKOUT_LPQ_PGNUM_8822B; - NPQ_num = HALMAC_LB_3BULKOUT_NPQ_PGNUM_8822B; - EXPQ_num = HALMAC_LB_3BULKOUT_EXPQ_PGNUM_8822B; - GAPQ_num = HALMAC_LB_3BULKOUT_GAP_PGNUM_8822B; - PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num; - rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - 1; - transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT; - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_WMAC_LBK_BUF_HD_V1, (u16)pHalmac_adapter->txff_allocation.rsvd_pg_bndy); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg_8822b 5 switch case not support\n"); - return HALMAC_RET_TRX_MODE_NOT_SUPPORT; - } + pCurr_pg_num = HALMAC_PG_NUM_3BULKOUT_8822B; + } else if (pHalmac_adapter->halmac_bulkout_num == 4) { + pCurr_pg_num = HALMAC_PG_NUM_4BULKOUT_8822B; + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]interface not support\n"); + return HALMAC_RET_NOT_SUPPORT; } + } else { + return HALMAC_RET_NOT_SUPPORT; } + status = halmac_pg_num_parser_88xx(pHalmac_adapter, halmac_trx_mode, pCurr_pg_num); + if (status != HALMAC_RET_SUCCESS) + return status; - if (pHalmac_adapter->txff_allocation.ac_q_pg_num < HPQ_num + LPQ_Nnum + NPQ_num + EXPQ_num + GAPQ_num) - return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL; - - pHalmac_adapter->txff_allocation.high_queue_pg_num = HPQ_num; - pHalmac_adapter->txff_allocation.low_queue_pg_num = LPQ_Nnum; - pHalmac_adapter->txff_allocation.normal_queue_pg_num = NPQ_num; - pHalmac_adapter->txff_allocation.extra_queue_pg_num = EXPQ_num; - pHalmac_adapter->txff_allocation.pub_queue_pg_num = PUBQ_num; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Set FIFO page\n"); - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, HPQ_num); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_2, LPQ_Nnum); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_3, NPQ_num); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_4, EXPQ_num); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_5, PUBQ_num); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, pHalmac_adapter->txff_allocation.high_queue_pg_num); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_2, pHalmac_adapter->txff_allocation.low_queue_pg_num); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_3, pHalmac_adapter->txff_allocation.normal_queue_pg_num); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_4, pHalmac_adapter->txff_allocation.extra_queue_pg_num); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_5, pHalmac_adapter->txff_allocation.pub_queue_pg_num); - pHalmac_adapter->sdio_free_space.high_queue_number = HPQ_num; - pHalmac_adapter->sdio_free_space.normal_queue_number = NPQ_num; - pHalmac_adapter->sdio_free_space.low_queue_number = LPQ_Nnum; - pHalmac_adapter->sdio_free_space.public_queue_number = PUBQ_num; - pHalmac_adapter->sdio_free_space.extra_queue_number = EXPQ_num; + pHalmac_adapter->sdio_free_space.high_queue_number = pHalmac_adapter->txff_allocation.high_queue_pg_num; + pHalmac_adapter->sdio_free_space.normal_queue_number = pHalmac_adapter->txff_allocation.normal_queue_pg_num; + pHalmac_adapter->sdio_free_space.low_queue_number = pHalmac_adapter->txff_allocation.low_queue_pg_num; + pHalmac_adapter->sdio_free_space.public_queue_number = pHalmac_adapter->txff_allocation.pub_queue_pg_num; + pHalmac_adapter->sdio_free_space.extra_queue_number = pHalmac_adapter->txff_allocation.extra_queue_pg_num; HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31)); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BCNQ_BDNY_V1, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCNQ_PGBNDY_V1)); + + /*20170223 Soar*/ + /*SDIO sometimes use two CMD52 to do HALMAC_REG_WRITE_16 and may cause a mismatch between HW status and Reg value.*/ + /*A patch is to write it again*/ + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BCNQ_BDNY_V1, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCNQ_PGBNDY_V1)); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BCNQ1_BDNY_V1, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCNQ_PGBNDY_V1)); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RXFF_BNDY, rx_f_ifo_boundary); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Init LLT table\n"); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RXFF_BNDY, pHalmac_adapter->hw_config_info.rx_fifo_size - HALMAC_C2H_PKT_BUF_8822B - 1); - if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) { + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) { value8 = (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) & ~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM)); value8 = (u8)(value8 | (HALMAC_BLK_DESC_NUM_8822B << BIT_SHIFT_BLK_DESC_NUM)); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1, value8); @@ -380,8 +318,14 @@ halmac_priority_queue_config_8822b( return HALMAC_RET_INIT_LLT_FAIL; } - if (HALMAC_TRX_MODE_DELAY_LOOPBACK == halmac_trx_mode) + if (halmac_trx_mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) { transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY; + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_WMAC_LBK_BUF_HD_V1, (u16)pHalmac_adapter->txff_allocation.rsvd_pg_bndy); + } else if (halmac_trx_mode == HALMAC_TRX_MODE_LOOPBACK) { + transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT; + } else { + transfer_mode = HALMAC_TRNSFER_NORMAL; + } HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 3, (u8)transfer_mode); diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.h index 68654d9..be7906e 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.h +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_FUNC_8822B_H_ #define _HALMAC_FUNC_8822B_H_ diff --git a/hal/halmac/halmac_88xx/halmac_88xx_cfg.h b/hal/halmac/halmac_88xx/halmac_88xx_cfg.h index fc53ff1..b40ff3a 100644 --- a/hal/halmac/halmac_88xx/halmac_88xx_cfg.h +++ b/hal/halmac/halmac_88xx/halmac_88xx_cfg.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_88XX_CFG_H_ #define _HALMAC_88XX_CFG_H_ @@ -20,21 +35,23 @@ #include "halmisc_api_88xx_sdio.h" #endif -#define HALMAC_SVN_VER_88XX "11974M" - -/* major version, ver_1 for async_api */ -#define HALMAC_MAJOR_VER_88XX 0x0001 -/* For halmac_api num change or prototype change, increment prototype version */ -#define HALMAC_PROTOTYPE_VER_88XX 0x0002 -/* else increment minor version */ -#define HALMAC_MINOR_VER_88XX 0x0000 - +#define HALMAC_SVN_VER_88XX "13359M" +#define HALMAC_MAJOR_VER_88XX 0x0001 /* major version, ver_1 for async_api */ +#define HALMAC_PROTOTYPE_VER_88XX 0x0003 /* For halmac_api num change or prototype change, increment prototype version */ +#define HALMAC_MINOR_VER_88XX 0x0009 /* else increment minor version */ +#define HALMAC_PATCH_VER_88XX 0x0000 /* patch version */ #define HALMAC_C2H_DATA_OFFSET_88XX 10 #define HALMAC_RX_AGG_ALIGNMENT_SIZE_88XX 8 #define HALMAC_TX_AGG_ALIGNMENT_SIZE_88XX 8 #define HALMAC_TX_AGG_BUFF_SIZE_88XX 32768 +#define HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX 80 /*8*10 Bytes*/ +#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_88XX 80 /* should be 8 Byte alignment*/ + +#define HALMAC_TX_PAGE_SIZE_88XX 128 /* PageSize 128Byte */ +#define HALMAC_TX_PAGE_SIZE_2_POWER_88XX 7 /* 128 = 2^7 */ +#define HALMAC_RX_BUF_FW_88XX 12288 /* 12K */ #define HALMAC_EXTRA_INFO_BUFF_SIZE_88XX 4096 /*4K*/ #define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX 16384 /*16K*/ @@ -54,11 +71,17 @@ #define HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX 0x7C00 #define DLFW_RESTORE_REG_NUM_88XX 9 +#define ID_INFORM_DLEMEM_RDY 0x80 /* FW header information */ -#define HALMAC_FWHDR_OFFSET_VERSION_88XX 4 -#define HALMAC_FWHDR_OFFSET_SUBVERSION_88XX 6 -#define HALMAC_FWHDR_OFFSET_SUBINDEX_88XX 7 +#define HALMAC_FWHDR_OFFSET_VERSION_88XX 4 +#define HALMAC_FWHDR_OFFSET_SUBVERSION_88XX 6 +#define HALMAC_FWHDR_OFFSET_SUBINDEX_88XX 7 +#define HALMAC_FWHDR_OFFSET_MONTH_88XX 16 +#define HALMAC_FWHDR_OFFSET_DATE_88XX 17 +#define HALMAC_FWHDR_OFFSET_HOUR_88XX 18 +#define HALMAC_FWHDR_OFFSET_MIN_88XX 19 +#define HALMAC_FWHDR_OFFSET_YEAR_88XX 20 #define HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX 24 #define HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX 28 #define HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX 32 @@ -74,7 +97,8 @@ #define HALMAC_OCPBASE_IMEM_88XX 0x00000000 /* define the SDIO Bus CLK threshold, for avoiding CMD53 fails that result from SDIO CLK sync to ana_clk fail */ -#define HALMAC_SD_CLK_THRESHOLD_88XX 150000000 /* 150MHz */ +#define HALMAC_SDIO_CLK_THRESHOLD_88XX 150 /* 150MHz */ +#define HALMAC_SDIO_CLOCK_SPEED_MAX_88XX 208 /* 208MHz */ /* MAC clock */ #define HALMAC_MAC_CLOCK_88XX 80 /* 80M */ @@ -83,7 +107,7 @@ #define HALMAC_H2C_CMD_SIZE_88XX 32 #define HALMAC_H2C_CMD_HDR_SIZE_88XX 8 -#define HALMAC_RESERVED_EFUSE_SIZE_88XX 0x30 +#define HALMAC_PROTECTED_EFUSE_SIZE_88XX 0x60 /* Function enable */ #define HALMAC_FUNCTION_ENABLE_88XX 0xDC @@ -145,4 +169,21 @@ /* Security config */ #define HALMAC_SECURITY_CONFIG_88XX 0x01CC +/* CCK rate ACK timeout */ +#define HALMAC_ACK_TO_CCK_88XX 0x40 + +/* RX pkt max size */ +#define HALMAC_RXPKT_MAX_SIZE 12288 /* 12K */ +#define HALMAC_RXPKT_MAX_SIZE_BASE512 (HALMAC_RXPKT_MAX_SIZE >> 9) + +/* OQT entry */ +#define HALMAC_OQT_ENTRY_AC_88XX 32 +#define HALMAC_OQT_ENTRY_NOAC_88XX 32 + +/* MACID number */ +#define HALMAC_MACID_MAX_88XX 127 + +#define HALMAC_PCIE_GEN1_SPEED_88XX 0x01 +#define HALMAC_PCIE_GEN2_SPEED_88XX 0x02 + #endif diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx.c b/hal/halmac/halmac_88xx/halmac_api_88xx.c index 75b1fc8..c4360b9 100644 --- a/hal/halmac/halmac_88xx/halmac_api_88xx.c +++ b/hal/halmac/halmac_88xx/halmac_api_88xx.c @@ -1,4 +1,20 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "halmac_88xx_cfg.h" +#include "halmac_gpio_88xx.h" /** * halmac_init_adapter_para_88xx() - int halmac adapter @@ -14,9 +30,7 @@ halmac_init_adapter_para_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ) { - pHalmac_adapter->api_record.array_wptr = 0; pHalmac_adapter->pHalAdapter_backup = pHalmac_adapter; - pHalmac_adapter->h2c_packet_seq = 0; pHalmac_adapter->pHalEfuse_map = (u8 *)NULL; pHalmac_adapter->hal_efuse_map_valid = _FALSE; pHalmac_adapter->efuse_end = 0; @@ -29,31 +43,9 @@ halmac_init_adapter_para_88xx( pHalmac_adapter->pHal_bss_addr[1].Address_L_H.Address_Low = 0; pHalmac_adapter->pHal_bss_addr[1].Address_L_H.Address_High = 0; - pHalmac_adapter->low_clk = _FALSE; - pHalmac_adapter->h2c_buf_free_space = 0; pHalmac_adapter->max_download_size = HALMAC_FW_MAX_DL_SIZE_88XX; - /* Init LPS Option */ - pHalmac_adapter->fwlps_option.mode = 0x01; /*0:Active 1:LPS 2:WMMPS*/ - pHalmac_adapter->fwlps_option.awake_interval = 1; - pHalmac_adapter->fwlps_option.enter_32K = 1; - pHalmac_adapter->fwlps_option.clk_request = 0; - pHalmac_adapter->fwlps_option.rlbm = 0; - pHalmac_adapter->fwlps_option.smart_ps = 0; - pHalmac_adapter->fwlps_option.awake_interval = 1; - pHalmac_adapter->fwlps_option.all_queue_uapsd = 0; - pHalmac_adapter->fwlps_option.pwr_state = 0; - pHalmac_adapter->fwlps_option.low_pwr_rx_beacon = 0; - pHalmac_adapter->fwlps_option.ant_auto_switch = 0; - pHalmac_adapter->fwlps_option.ps_allow_bt_high_Priority = 0; - pHalmac_adapter->fwlps_option.protect_bcn = 0; - pHalmac_adapter->fwlps_option.silence_period = 0; - pHalmac_adapter->fwlps_option.fast_bt_connect = 0; - pHalmac_adapter->fwlps_option.two_antenna_en = 0; - pHalmac_adapter->fwlps_option.adopt_user_Setting = 1; - pHalmac_adapter->fwlps_option.drv_bcn_early_shift = 0; - pHalmac_adapter->config_para_info.pCfg_para_buf = NULL; pHalmac_adapter->config_para_info.pPara_buf_w = NULL; pHalmac_adapter->config_para_info.para_num = 0; @@ -72,12 +64,74 @@ halmac_init_adapter_para_88xx( pHalmac_adapter->ch_sw_info.total_size = 0; pHalmac_adapter->ch_sw_info.ch_num = 0; - pHalmac_adapter->gen_info_valid = _FALSE; + pHalmac_adapter->drv_info_size = 0; - PLATFORM_RTL_MEMSET(pHalmac_adapter->pDriver_adapter, pHalmac_adapter->api_record.api_array, HALMAC_API_STUFF, sizeof(pHalmac_adapter->api_record.api_array)); + pHalmac_adapter->txff_allocation.tx_fifo_pg_num = 0; + pHalmac_adapter->txff_allocation.ac_q_pg_num = 0; + pHalmac_adapter->txff_allocation.rsvd_pg_bndy = 0; + pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy = 0; + pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy = 0; + pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy = 0; + pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy = 0; + pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy = 0; + pHalmac_adapter->txff_allocation.pub_queue_pg_num = 0; + pHalmac_adapter->txff_allocation.high_queue_pg_num = 0; + pHalmac_adapter->txff_allocation.low_queue_pg_num = 0; + pHalmac_adapter->txff_allocation.normal_queue_pg_num = 0; + pHalmac_adapter->txff_allocation.extra_queue_pg_num = 0; + pHalmac_adapter->txff_allocation.la_mode = HALMAC_LA_MODE_DISABLE; + pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode = HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE; + + pHalmac_adapter->hw_config_info.ac_oqt_size = HALMAC_OQT_ENTRY_AC_88XX; + pHalmac_adapter->hw_config_info.non_ac_oqt_size = HALMAC_OQT_ENTRY_NOAC_88XX; + pHalmac_adapter->hw_config_info.ac_queue_num = 8; + + pHalmac_adapter->sdio_cmd53_4byte = HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE; + pHalmac_adapter->sdio_hw_info.io_hi_speed_flag = 0; + pHalmac_adapter->sdio_hw_info.spec_ver = HALMAC_SDIO_SPEC_VER_2_00; + pHalmac_adapter->sdio_hw_info.clock_speed = 50; + + pHalmac_adapter->pinmux_info.wl_led = 0; + pHalmac_adapter->pinmux_info.sdio_int = 0; + pHalmac_adapter->pinmux_info.sw_io_0 = 0; + pHalmac_adapter->pinmux_info.sw_io_1 = 0; + pHalmac_adapter->pinmux_info.sw_io_2 = 0; + pHalmac_adapter->pinmux_info.sw_io_3 = 0; + pHalmac_adapter->pinmux_info.sw_io_4 = 0; + pHalmac_adapter->pinmux_info.sw_io_5 = 0; + pHalmac_adapter->pinmux_info.sw_io_6 = 0; + pHalmac_adapter->pinmux_info.sw_io_7 = 0; + pHalmac_adapter->pinmux_info.sw_io_8 = 0; + pHalmac_adapter->pinmux_info.sw_io_9 = 0; + pHalmac_adapter->pinmux_info.sw_io_10 = 0; + pHalmac_adapter->pinmux_info.sw_io_11 = 0; + pHalmac_adapter->pinmux_info.sw_io_12 = 0; + pHalmac_adapter->pinmux_info.sw_io_13 = 0; + pHalmac_adapter->pinmux_info.sw_io_14 = 0; + pHalmac_adapter->pinmux_info.sw_io_15 = 0; + + halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter); halmac_init_state_machine_88xx(pHalmac_adapter); +} +/** + * halmac_init_adapter_dynamic_para_88xx() - int halmac adapter + * @pHalmac_adapter + * + * SD1 internal use + * + * Author : KaiYuan Chang/Ivan Lin + * Return : VOID + */ +VOID +halmac_init_adapter_dynamic_para_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + pHalmac_adapter->h2c_packet_seq = 0; + pHalmac_adapter->h2c_buf_free_space = 0; + pHalmac_adapter->gen_info_valid = _FALSE; } /** @@ -94,40 +148,16 @@ halmac_init_state_machine_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ) { - PHALMAC_STATE pState = &(pHalmac_adapter->halmac_state); + PHALMAC_STATE pState = &pHalmac_adapter->halmac_state; - pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE; - pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->efuse_state_set.seq_num = pHalmac_adapter->h2c_packet_seq; - - pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE; - pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->cfg_para_state_set.seq_num = pHalmac_adapter->h2c_packet_seq; - - pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE; - pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->scan_state_set.seq_num = pHalmac_adapter->h2c_packet_seq; - - pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->update_packet_set.seq_num = pHalmac_adapter->h2c_packet_seq; - - pState->iqk_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->iqk_set.seq_num = pHalmac_adapter->h2c_packet_seq; - - pState->power_tracking_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->power_tracking_set.seq_num = pHalmac_adapter->h2c_packet_seq; - - pState->psd_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->psd_set.seq_num = pHalmac_adapter->h2c_packet_seq; - pState->psd_set.data_size = 0; - pState->psd_set.segment_size = 0; - pState->psd_set.pData = NULL; + halmac_init_offload_feature_state_machine_88xx(pHalmac_adapter); pState->api_state = HALMAC_API_STATE_INIT; pState->dlfw_state = HALMAC_DLFW_NONE; pState->mac_power = HALMAC_MAC_POWER_OFF; pState->ps_state = HALMAC_PS_STATE_UNDEFINE; + pState->gpio_cfg_state = HALMAC_GPIO_CFG_STATE_IDLE; } /** @@ -146,29 +176,27 @@ halmac_mount_api_88xx( { VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; PHALMAC_API pHalmac_api = (PHALMAC_API)NULL; - u8 chip_id, chip_version; - u32 polling_count; pHalmac_adapter->pHalmac_api = (PHALMAC_API)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(HALMAC_API)); - if (NULL == pHalmac_adapter->pHalmac_api) + if (pHalmac_adapter->pHalmac_api == NULL) return HALMAC_RET_MALLOC_FAIL; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, HALMAC_SVN_VER_88XX"\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_MAJOR_VER_88XX = %x\n", HALMAC_MAJOR_VER_88XX); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_PROTOTYPE_88XX = %x\n", HALMAC_PROTOTYPE_VER_88XX); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_MINOR_VER_88XX = %x\n", HALMAC_MINOR_VER_88XX); - + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, HALMAC_SVN_VER_88XX"\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MAJOR_VER_88XX = %x\n", HALMAC_MAJOR_VER_88XX); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PROTOTYPE_88XX = %x\n", HALMAC_PROTOTYPE_VER_88XX); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MINOR_VER_88XX = %x\n", HALMAC_MINOR_VER_88XX); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PATCH_VER_88XX = %x\n", HALMAC_PATCH_VER_88XX); /* Mount function pointer */ pHalmac_api->halmac_download_firmware = halmac_download_firmware_88xx; + pHalmac_api->halmac_free_download_firmware = halmac_free_download_firmware_88xx; pHalmac_api->halmac_get_fw_version = halmac_get_fw_version_88xx; pHalmac_api->halmac_cfg_mac_addr = halmac_cfg_mac_addr_88xx; pHalmac_api->halmac_cfg_bssid = halmac_cfg_bssid_88xx; pHalmac_api->halmac_cfg_multicast_addr = halmac_cfg_multicast_addr_88xx; pHalmac_api->halmac_pre_init_system_cfg = halmac_pre_init_system_cfg_88xx; pHalmac_api->halmac_init_system_cfg = halmac_init_system_cfg_88xx; - pHalmac_api->halmac_init_protocol_cfg = halmac_init_protocol_cfg_88xx; pHalmac_api->halmac_init_edca_cfg = halmac_init_edca_cfg_88xx; pHalmac_api->halmac_cfg_operation_mode = halmac_cfg_operation_mode_88xx; pHalmac_api->halmac_cfg_ch_bw = halmac_cfg_ch_bw_88xx; @@ -184,24 +212,19 @@ halmac_mount_api_88xx( pHalmac_api->halmac_dump_efuse_map = halmac_dump_efuse_map_88xx; pHalmac_api->halmac_dump_efuse_map_bt = halmac_dump_efuse_map_bt_88xx; pHalmac_api->halmac_write_efuse_bt = halmac_write_efuse_bt_88xx; + pHalmac_api->halmac_read_efuse_bt = halmac_read_efuse_bt_88xx; + pHalmac_api->halmac_cfg_efuse_auto_check = halmac_cfg_efuse_auto_check_88xx; pHalmac_api->halmac_dump_logical_efuse_map = halmac_dump_logical_efuse_map_88xx; - /* pHalmac_api->halmac_write_efuse = halmac_write_efuse_88xx; */ pHalmac_api->halmac_pg_efuse_by_map = halmac_pg_efuse_by_map_88xx; pHalmac_api->halmac_get_efuse_size = halmac_get_efuse_size_88xx; + pHalmac_api->halmac_get_efuse_available_size = halmac_get_efuse_available_size_88xx; pHalmac_api->halmac_get_c2h_info = halmac_get_c2h_info_88xx; - /* pHalmac_api->halmac_read_efuse = halmac_read_efuse_88xx; */ pHalmac_api->halmac_get_logical_efuse_size = halmac_get_logical_efuse_size_88xx; pHalmac_api->halmac_write_logical_efuse = halmac_write_logical_efuse_88xx; pHalmac_api->halmac_read_logical_efuse = halmac_read_logical_efuse_88xx; - pHalmac_api->halmac_cfg_fwlps_option = halmac_cfg_fwlps_option_88xx; - pHalmac_api->halmac_cfg_fwips_option = halmac_cfg_fwips_option_88xx; - pHalmac_api->halmac_enter_wowlan = halmac_enter_wowlan_88xx; - pHalmac_api->halmac_leave_wowlan = halmac_leave_wowlan_88xx; - pHalmac_api->halmac_enter_ps = halmac_enter_ps_88xx; - pHalmac_api->halmac_leave_ps = halmac_leave_ps_88xx; pHalmac_api->halmac_h2c_lb = halmac_h2c_lb_88xx; pHalmac_api->halmac_debug = halmac_debug_88xx; pHalmac_api->halmac_cfg_parameter = halmac_cfg_parameter_88xx; @@ -228,6 +251,7 @@ halmac_mount_api_88xx( pHalmac_api->halmac_add_ch_info = halmac_add_ch_info_88xx; pHalmac_api->halmac_add_extra_ch_info = halmac_add_extra_ch_info_88xx; pHalmac_api->halmac_ctrl_ch_switch = halmac_ctrl_ch_switch_88xx; + pHalmac_api->halmac_p2pps = halmac_p2pps_88xx; pHalmac_api->halmac_clear_ch_info = halmac_clear_ch_info_88xx; pHalmac_api->halmac_send_general_info = halmac_send_general_info_88xx; @@ -235,6 +259,13 @@ halmac_mount_api_88xx( pHalmac_api->halmac_ctrl_pwr_tracking = halmac_ctrl_pwr_tracking_88xx; pHalmac_api->halmac_psd = halmac_psd_88xx; pHalmac_api->halmac_cfg_la_mode = halmac_cfg_la_mode_88xx; + pHalmac_api->halmac_cfg_rx_fifo_expanding_mode = halmac_cfg_rx_fifo_expanding_mode_88xx; + + pHalmac_api->halmac_config_security = halmac_config_security_88xx; + pHalmac_api->halmac_get_used_cam_entry_num = halmac_get_used_cam_entry_num_88xx; + pHalmac_api->halmac_read_cam_entry = halmac_read_cam_entry_88xx; + pHalmac_api->halmac_write_cam = halmac_write_cam_88xx; + pHalmac_api->halmac_clear_cam_entry = halmac_clear_cam_entry_88xx; pHalmac_api->halmac_get_hw_value = halmac_get_hw_value_88xx; pHalmac_api->halmac_set_hw_value = halmac_set_hw_value_88xx; @@ -252,8 +283,25 @@ halmac_mount_api_88xx( pHalmac_api->halmac_get_fifo_size = halmac_get_fifo_size_88xx; pHalmac_api->halmac_chk_txdesc = halmac_chk_txdesc_88xx; + pHalmac_api->halmac_dl_drv_rsvd_page = halmac_dl_drv_rsvd_page_88xx; + pHalmac_api->halmac_cfg_csi_rate = halmac_cfg_csi_rate_88xx; - if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { + pHalmac_api->halmac_sdio_cmd53_4byte = halmac_sdio_cmd53_4byte_88xx; + pHalmac_api->halmac_sdio_hw_info = halmac_sdio_hw_info_88xx; + pHalmac_api->halmac_txfifo_is_empty = halmac_txfifo_is_empty_88xx; + pHalmac_api->halmac_download_flash = halmac_download_flash_88xx; + pHalmac_api->halmac_read_flash = halmac_read_flash_88xx; + pHalmac_api->halmac_erase_flash = halmac_erase_flash_88xx; + pHalmac_api->halmac_check_flash = halmac_check_flash_88xx; + pHalmac_api->halmac_cfg_edca_para = halmac_cfg_edca_para_88xx; + pHalmac_api->halmac_pinmux_wl_led_mode = halmac_pinmux_wl_led_mode_88xx; + pHalmac_api->halmac_pinmux_wl_led_sw_ctrl = halmac_pinmux_wl_led_sw_ctrl_88xx; + pHalmac_api->halmac_pinmux_sdio_int_polarity = halmac_pinmux_sdio_int_polarity_88xx; + pHalmac_api->halmac_pinmux_gpio_mode = halmac_pinmux_gpio_mode_88xx; + pHalmac_api->halmac_pinmux_gpio_output = halmac_pinmux_gpio_output_88xx; + pHalmac_api->halmac_pinmux_pin_status = halmac_pinmux_pin_status_88xx; + + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_sdio; pHalmac_api->halmac_init_interface_cfg = halmac_init_sdio_cfg_88xx; pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_sdio_cfg_88xx; @@ -263,7 +311,9 @@ halmac_mount_api_88xx( pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_sdio_88xx; pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_sdio_88xx; pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_sdio_88xx; - } else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) { + pHalmac_api->halmac_reg_read_indirect_32 = halmac_reg_read_indirect_32_sdio_88xx; + pHalmac_api->halmac_reg_sdio_cmd53_read_n = halmac_reg_read_nbyte_sdio_88xx; + } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) { pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_usb; pHalmac_api->halmac_init_interface_cfg = halmac_init_usb_cfg_88xx; pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_usb_cfg_88xx; @@ -273,7 +323,7 @@ halmac_mount_api_88xx( pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_usb_88xx; pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_usb_88xx; pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_usb_88xx; - } else if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) { + } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) { pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_pcie; pHalmac_api->halmac_init_interface_cfg = halmac_init_pcie_cfg_88xx; pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_pcie_cfg_88xx; @@ -293,62 +343,22 @@ halmac_mount_api_88xx( pHalmac_api->halmac_timer_2s = halmac_timer_2s_88xx; pHalmac_api->halmac_fill_txdesc_checksum = halmac_fill_txdesc_check_sum_88xx; - /* Get Chip_id and Chip_version */ - chip_id = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2); - if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { - if (chip_id == 0xEA) { - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL) & ~(BIT(0))); - - polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT; - while (!(HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL) & 0x02)) { - polling_count--; - if (polling_count == 0) - return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL; - } - } - chip_id = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2); - } - chip_version = (u8)HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG1 + 1) >> 4; - - pHalmac_adapter->chip_version = (HALMAC_CHIP_VER)chip_version; - if (HALMAC_CHIP_ID_HW_DEF_8822B == chip_id) { + if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8822B) { #if HALMAC_8822B_SUPPORT /*mount 8822b function and data*/ halmac_mount_api_8822b(pHalmac_adapter); #endif - } else if (HALMAC_CHIP_ID_HW_DEF_8821C == chip_id) { + } else if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) { #if HALMAC_8821C_SUPPORT /*mount 8822b function and data*/ halmac_mount_api_8821c(pHalmac_adapter); -#endif - } else if (HALMAC_CHIP_ID_HW_DEF_8197F == chip_id) { -#if HALMAC_8197F_SUPPORT - /*mount 8822b function and data*/ - halmac_mount_api_8197f(pHalmac_adapter); #endif } else { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Chip ID undefine!!\n"); return HALMAC_RET_CHIP_NOT_SUPPORT; } - - pHalmac_adapter->txff_allocation.tx_fifo_pg_num = 0; - pHalmac_adapter->txff_allocation.ac_q_pg_num = 0; - pHalmac_adapter->txff_allocation.rsvd_pg_bndy = 0; - pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy = 0; - pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy = 0; - pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy = 0; - pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy = 0; - pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy = 0; - pHalmac_adapter->txff_allocation.pub_queue_pg_num = 0; - pHalmac_adapter->txff_allocation.high_queue_pg_num = 0; - pHalmac_adapter->txff_allocation.low_queue_pg_num = 0; - pHalmac_adapter->txff_allocation.normal_queue_pg_num = 0; - pHalmac_adapter->txff_allocation.extra_queue_pg_num = 0; - - pHalmac_adapter->txff_allocation.la_mode = HALMAC_LA_MODE_DISABLE; - #if HALMAC_PLATFORM_TESTPROGRAM pHalmac_api->halmac_write_efuse = halmac_write_efuse_88xx; pHalmac_api->halmac_read_efuse = halmac_read_efuse_88xx; @@ -383,52 +393,54 @@ halmac_mount_api_88xx( pHalmac_api->halmac_get_management_txdesc = halmac_get_management_txdesc_88xx; pHalmac_api->halmac_send_control = halmac_send_control_88xx; pHalmac_api->halmac_send_hiqueue = halmac_send_hiqueue_88xx; - pHalmac_api->halmac_media_status_rpt = halmac_media_status_rpt_88xx; pHalmac_api->halmac_timer_10ms = halmac_timer_10ms_88xx; pHalmac_api->halmac_download_firmware_fpag = halmac_download_firmware_fpga_88xx; pHalmac_api->halmac_download_rom_fpga = halmac_download_rom_fpga_88xx; - pHalmac_api->halmac_download_flash = halmac_download_flash_88xx; - pHalmac_api->halmac_erase_flash = halmac_erase_flash_88xx; - pHalmac_api->halmac_check_flash = halmac_check_flash_88xx; pHalmac_api->halmac_send_nlo = halmac_send_nlo_88xx; - pHalmac_api->halmac_config_security = halmac_config_security_88xx; - pHalmac_api->halmac_read_cam = halmac_read_cam_88xx; - pHalmac_api->halmac_write_cam = halmac_write_cam_88xx; pHalmac_api->halmac_dump_cam_table = halmac_dump_cam_table_88xx; pHalmac_api->halmac_load_cam_table = halmac_load_cam_table_88xx; pHalmac_api->halmac_get_chip_type = halmac_get_chip_type_88xx; pHalmac_api->halmac_get_rx_agg_num = halmac_get_rx_agg_num_88xx; + pHalmac_api->halmac_check_rx_scsi_resp = halmac_check_rx_scsi_resp_88xx_usb; + pHalmac_api->halmac_get_hcpwm = halmac_get_hcpwm_88xx; + pHalmac_api->halmac_get_hcpwm2 = halmac_get_hcpwm2_88xx; + pHalmac_api->halmac_set_hrpwm = halmac_set_hrpwm_88xx; + pHalmac_api->halmac_set_hrpwm2 = halmac_set_hrpwm2_88xx; + pHalmac_api->halmac_coex_cfg = halmac_coex_cfg_88xx; +#if HALMAC_8822B_SUPPORT if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8822B) pHalmac_api->halmac_run_pwrseq = halmac_run_pwrseq_8822b; - else if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) +#endif +#if HALMAC_8821C_SUPPORT + if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) pHalmac_api->halmac_run_pwrseq = halmac_run_pwrseq_8821c; - - if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { - pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_sdio_tp_88xx; - pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_sdio_tp_88xx; - pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_sdio_tp_88xx; - pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_sdio_tp_88xx; - pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_sdio_tp_88xx; - pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_sdio_tp_88xx; +#endif + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { + pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_sdio_88xx; + pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_sdio_88xx; + pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_sdio_88xx; + pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_sdio_88xx; + pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_sdio_88xx; + pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_sdio_88xx; } #endif return HALMAC_RET_SUCCESS; } - /** * halmac_download_firmware_88xx() - download Firmware - * @pHalmac_adapter - * @pHamacl_fw : FW bin file - * @halmac_fw_size + * @pHalmac_adapter : the adapter of halmac + * @pHamacl_fw : firmware bin + * @halmac_fw_size : firmware size * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_download_firmware_88xx( @@ -441,37 +453,33 @@ halmac_download_firmware_88xx( u8 *pFile_ptr; u16 value16; u32 restore_index = 0; - u32 halmac_h2c_ver = 0, fw_h2c_ver = 0; + u16 halmac_h2c_ver = 0, fw_h2c_ver = 0; u32 iram_pkt_size, dmem_pkt_size, eram_pkt_size = 0; VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; HALMAC_RESTORE_INFO restore_info[DLFW_RESTORE_REG_NUM_88XX]; - HALMAC_RET_STATUS status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DOWNLOAD_FIRMWARE); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx start!!\n"); if (halmac_fw_size > HALMAC_FW_SIZE_MAX_88XX || halmac_fw_size < HALMAC_FWHDR_SIZE_88XX) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "FW size error!\n"); return HALMAC_RET_FW_SIZE_ERR; } - fw_h2c_ver = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX)); + fw_h2c_ver = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX))); halmac_h2c_ver = H2C_FORMAT_VERSION; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac h2c/c2h format = %x, fw h2c/c2h format = %x!!\n", halmac_h2c_ver, fw_h2c_ver); if (fw_h2c_ver != halmac_h2c_ver) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "H2C/C2H version mismatch between HALMAC and FW, Offload Feature May fail!\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "[WARN]H2C/C2H version between HALMAC and FW is compatible!!\n"); pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; @@ -479,6 +487,9 @@ halmac_download_firmware_88xx( value8 = (u8)(value8 & ~(BIT(2))); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, value8); /* Disable CPU reset */ + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RSV_CTRL + 1); + value8 = (u8)(value8 & ~(BIT(0))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RSV_CTRL + 1, value8); restore_info[restore_index].length = 1; restore_info[restore_index].mac_register = REG_TXDMA_PQ_MAP + 1; @@ -513,14 +524,10 @@ halmac_download_firmware_88xx( HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, 0x200); HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, restore_info[restore_index - 1].value); - if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_TX_CTRL, 0x00000000); - } - pHalmac_adapter->fw_version.version = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_VERSION_88XX))); - pHalmac_adapter->fw_version.sub_version = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_SUBVERSION_88XX); - pHalmac_adapter->fw_version.sub_index = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_SUBINDEX_88XX); + halmac_update_fw_info_88xx(pHalmac_adapter, pHamacl_fw, halmac_fw_size); dmem_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX)); iram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX)); @@ -533,7 +540,7 @@ halmac_download_firmware_88xx( dmem_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; iram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; - if (0 != eram_pkt_size) + if (eram_pkt_size != 0) eram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; if (halmac_fw_size != (HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size + eram_pkt_size)) { @@ -582,50 +589,33 @@ halmac_download_firmware_88xx( value8 |= BIT(0); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2, value8); - /* Download to DMEM */ pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX; - /* if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, HALMAC_OCPBASE_DMEM_88XX, dmem_pkt_size)) */ - if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, - (*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX))) & ~(BIT(31)), dmem_pkt_size)) + if (halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, + rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX))) & ~(BIT(31)), dmem_pkt_size) != HALMAC_RET_SUCCESS) goto DLFW_END; - /* Download to IMEM */ pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size; - /* if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, HALMAC_OCPBASE_IMEM_88XX, iram_pkt_size)) */ - if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, - (*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX))) & ~(BIT(31)), iram_pkt_size)) + if (halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, + rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX))) & ~(BIT(31)), iram_pkt_size) != HALMAC_RET_SUCCESS) goto DLFW_END; - /* Download to EMEM */ - if (0 != eram_pkt_size) { + if (eram_pkt_size != 0) { pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size; - if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, - (*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX))) & ~(BIT(31)), eram_pkt_size)) + if (halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, + rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX))) & ~(BIT(31)), eram_pkt_size) != HALMAC_RET_SUCCESS) goto DLFW_END; } + halmac_init_offload_feature_state_machine_88xx(pHalmac_adapter); DLFW_END: halmac_restore_mac_register_88xx(pHalmac_adapter, restore_info, DLFW_RESTORE_REG_NUM_88XX); - if (HALMAC_RET_SUCCESS != halmac_dlfw_end_flow_88xx(pHalmac_adapter)) + if (halmac_dlfw_end_flow_88xx(pHalmac_adapter) != HALMAC_RET_SUCCESS) goto DLFW_FAIL; pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_DONE; - - if (_TRUE == pHalmac_adapter->gen_info_valid) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Auto send halmac_send_general_info after redownload fw\n"); - status = halmac_send_general_info_88xx(pHalmac_adapter, &(pHalmac_adapter->general_info)); - - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_send_general_info error = %x\n", status); - return status; - } - if (HALMAC_DLFW_DONE == pHalmac_adapter->halmac_state.dlfw_state) - pHalmac_adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT; - } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx <==========\n"); return HALMAC_RET_SUCCESS; @@ -639,11 +629,100 @@ halmac_download_firmware_88xx( } /** - * halmac_get_fw_version_88xx() - get FW version + * halmac_free_download_firmware_88xx() - download specific memory firmware * @pHalmac_adapter - * @pFw_version + * @dlfw_mem : memory selection + * @pHamacl_fw : firmware bin + * @halmac_fw_size : firmware size + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + */ +HALMAC_RET_STATUS +halmac_free_download_firmware_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DLFW_MEM dlfw_mem, + IN u8 *pHamacl_fw, + IN u32 halmac_fw_size +) +{ + u8 tx_pause_backup; + u8 *pFile_ptr; + u16 bcn_head_backup; + u32 iram_pkt_size, dmem_pkt_size, eram_pkt_size = 0; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_DLFW_FAIL; + PHALMAC_API pHalmac_api; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_free_download_firmware_88xx ==========>\n"); + + if (halmac_fw_size > HALMAC_FW_SIZE_MAX_88XX || halmac_fw_size < HALMAC_FWHDR_SIZE_88XX) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]FW size error!\n"); + return HALMAC_RET_FW_SIZE_ERR; + } + + dmem_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX)); + iram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX)); + if (0 != ((*(pHamacl_fw + HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX)) & BIT(4))) + eram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX)); + + dmem_pkt_size = rtk_le32_to_cpu(dmem_pkt_size); + iram_pkt_size = rtk_le32_to_cpu(iram_pkt_size); + eram_pkt_size = rtk_le32_to_cpu(eram_pkt_size); + + dmem_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; + iram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; + if (eram_pkt_size != 0) + eram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; + + if (halmac_fw_size != (HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size + eram_pkt_size)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]FW size mismatch the real fw size!\n"); + return HALMAC_RET_DLFW_FAIL; + } + + tx_pause_backup = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPAUSE); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXPAUSE, tx_pause_backup | BIT(7)); + + bcn_head_backup = HALMAC_REG_READ_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2) | BIT(15); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0x8000); + + if (eram_pkt_size != 0) { + pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size; + status = halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, + rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX))) & ~(BIT(31)), eram_pkt_size); + if (status != HALMAC_RET_SUCCESS) + goto DL_FREE_FW_END; + } + + status = halmac_free_dl_fw_end_flow_88xx(pHalmac_adapter); + +DL_FREE_FW_END: + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXPAUSE, tx_pause_backup); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, bcn_head_backup); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_free_download_firmware_88xx <==========\n"); + + return status; +} + +/** + * halmac_get_fw_version_88xx() - get FW version + * @pHalmac_adapter : the adapter of halmac + * @pFw_version : fw version info * Author : Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_get_fw_version_88xx( @@ -651,27 +730,38 @@ halmac_get_fw_version_88xx( OUT PHALMAC_FW_VERSION pFw_version ) { - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + PHALMAC_FW_VERSION pFw_info = &pHalmac_adapter->fw_version; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (0 == pHalmac_adapter->halmac_state.dlfw_state) { - return HALMAC_RET_DLFW_FAIL; - } else { - pFw_version->version = pHalmac_adapter->fw_version.version; - pFw_version->sub_version = pHalmac_adapter->fw_version.sub_version; - pFw_version->sub_index = pHalmac_adapter->fw_version.sub_index; - } + if (pFw_version == NULL) + return HALMAC_RET_NULL_POINTER; + + if (pHalmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) + return HALMAC_RET_NO_DLFW; + + pFw_version->version = pFw_info->version; + pFw_version->sub_version = pFw_info->sub_version; + pFw_version->sub_index = pFw_info->sub_index; + pFw_version->h2c_version = pFw_info->h2c_version; + pFw_version->build_time.month = pFw_info->build_time.month; + pFw_version->build_time.date = pFw_info->build_time.date; + pFw_version->build_time.hour = pFw_info->build_time.hour; + pFw_version->build_time.min = pFw_info->build_time.min; + pFw_version->build_time.year = pFw_info->build_time.year; return HALMAC_RET_SUCCESS; } /** - * halmac_cfg_mac_addr_88xx() - config Mac Address - * @pHalmac_adapter - * @halmac_port : 0 : port0 1 : port1 + * halmac_cfg_mac_addr_88xx() - config mac address + * @pHalmac_adapter : the adapter of halmac + * @halmac_port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 * @pHal_address : mac address * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_mac_addr_88xx( @@ -685,21 +775,19 @@ halmac_cfg_mac_addr_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MAC_ADDR); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_mac_addr_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_mac_addr_88xx ==========>\n"); - if (halmac_port > 2) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "port index > 2\n"); + if (halmac_port >= HALMAC_PORTIDMAX) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]port index > 5\n"); return HALMAC_RET_PORT_NOT_SUPPORT; } @@ -712,26 +800,49 @@ halmac_cfg_mac_addr_88xx( pHalmac_adapter->pHal_mac_addr[halmac_port].Address_L_H.Address_Low = mac_address_L; pHalmac_adapter->pHal_mac_addr[halmac_port].Address_L_H.Address_High = mac_address_H; - if (0 == halmac_port) { + switch (halmac_port) { + case HALMAC_PORTID0: HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID, mac_address_L); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID + 4, mac_address_H); - } else { + break; + + case HALMAC_PORTID1: HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID1, mac_address_L); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID1 + 4, mac_address_H); + break; + + case HALMAC_PORTID2: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID2, mac_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID2 + 4, mac_address_H); + break; + + case HALMAC_PORTID3: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID3, mac_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID3 + 4, mac_address_H); + break; + + case HALMAC_PORTID4: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID4, mac_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID4 + 4, mac_address_H); + break; + + default: + break; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_mac_addr_88xx <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_mac_addr_88xx <==========\n"); return HALMAC_RET_SUCCESS; } /** * halmac_cfg_bssid_88xx() - config BSSID - * @pHalmac_adapter - * @halmac_port : 0 : port0 1 : port1 - * @pHal_address : mac address + * @pHalmac_adapter : the adapter of halmac + * @halmac_port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @pHal_address : bssid * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_bssid_88xx( @@ -745,21 +856,19 @@ halmac_cfg_bssid_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_BSSID); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_bssid_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_bssid_88xx ==========>\n"); - if (halmac_port > 2) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "port index > 2\n"); + if (halmac_port >= HALMAC_PORTIDMAX) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]port index > 5\n"); return HALMAC_RET_PORT_NOT_SUPPORT; } @@ -772,25 +881,48 @@ halmac_cfg_bssid_88xx( pHalmac_adapter->pHal_bss_addr[halmac_port].Address_L_H.Address_Low = bssid_address_L; pHalmac_adapter->pHal_bss_addr[halmac_port].Address_L_H.Address_High = bssid_address_H; - if (0 == halmac_port) { + switch (halmac_port) { + case HALMAC_PORTID0: HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID, bssid_address_L); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID + 4, bssid_address_H); - } else { + break; + + case HALMAC_PORTID1: HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID1, bssid_address_L); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID1 + 4, bssid_address_H); + break; + + case HALMAC_PORTID2: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID2, bssid_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID2 + 4, bssid_address_H); + break; + + case HALMAC_PORTID3: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID3, bssid_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID3 + 4, bssid_address_H); + break; + + case HALMAC_PORTID4: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID4, bssid_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID4 + 4, bssid_address_H); + break; + + default: + break; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_bssid_88xx <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_bssid_88xx <==========\n"); return HALMAC_RET_SUCCESS; } /** * halmac_cfg_multicast_addr_88xx() - config multicast address - * @pHalmac_adapter - * @pHal_address : mac address + * @pHalmac_adapter : the adapter of halmac + * @pHal_address : multicast address * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_multicast_addr_88xx( @@ -803,14 +935,12 @@ halmac_cfg_multicast_addr_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MULTICAST_ADDR); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -831,34 +961,51 @@ halmac_cfg_multicast_addr_88xx( } /** - * halmac_pre_init_system_cfg_88xx() - config system register before power on - * @pHalmac_adapter + * halmac_pre_init_system_cfg_88xx() - pre-init system config + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_pre_init_system_cfg_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ) { - u32 value32; + u32 value32, counter; VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; u8 enable_bb; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PRE_INIT_SYSTEM_CFG); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pre_init_system_cfg ==========>\n"); + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL) & ~(BIT(0))); + counter = 10000; + while (!(HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL) & 0x02)) { + counter--; + if (counter == 0) + return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL; + } + + if (pHalmac_adapter->sdio_hw_info.spec_ver == HALMAC_SDIO_SPEC_VER_3_00) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_HCI_OPT_CTRL + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_HCI_OPT_CTRL + 2) | BIT(2)); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_HCI_OPT_CTRL + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_HCI_OPT_CTRL + 2) & ~(BIT(2))); + } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) { + if (HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2 + 3) == 0x20) /* usb3.0 */ + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xFE5B, HALMAC_REG_READ_8(pHalmac_adapter, 0xFE5B) | BIT(4)); + } + /* Config PIN Mux */ value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL1); value32 = value32 & (~(BIT(28) | BIT(29))); @@ -884,10 +1031,11 @@ halmac_pre_init_system_cfg_88xx( } /** - * halmac_init_system_cfg_88xx() - config system register after power on - * @pHalmac_adapter + * halmac_init_system_cfg_88xx() - init system config + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_init_system_cfg_88xx( @@ -896,16 +1044,15 @@ halmac_init_system_cfg_88xx( { VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; + u32 temp = 0; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_SYSTEM_CFG); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -915,7 +1062,12 @@ halmac_init_system_cfg_88xx( HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SYS_SDIO_CTRL, (u32)(HALMAC_REG_READ_32(pHalmac_adapter, REG_SYS_SDIO_CTRL) | BIT_LTE_MUX_CTRL_PATH)); HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CPU_DMEM_CON, (u32)(HALMAC_REG_READ_32(pHalmac_adapter, REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST)); - /* pHalmac_api->halmac_init_h2c(pHalmac_adapter); */ + /*disable boot-from-flash for driver's DL FW*/ + temp = HALMAC_REG_READ_32(pHalmac_adapter, REG_MCUFW_CTRL); + if (temp & BIT_BOOT_FSPI_EN) { + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MCUFW_CTRL, temp & (~BIT_BOOT_FSPI_EN)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_GPIO_MUXCFG, HALMAC_REG_READ_32(pHalmac_adapter, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN)); + } PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_system_cfg <==========\n"); @@ -923,76 +1075,27 @@ halmac_init_system_cfg_88xx( } /** - * halmac_init_protocol_cfg_88xx() - config protocol related register - * @pHalmac_adapter - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ -HALMAC_RET_STATUS -halmac_init_protocol_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u16 value16; - u32 value32; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; - - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) - return HALMAC_RET_API_INVALID; - - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_PROTOCOL_CFG); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_protocol_cfg_88xx ==========>\n"); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BASIC_CFEND_RATE, HALMAC_BASIC_CFEND_RATE_88XX); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_STBC_CFEND_RATE, HALMAC_STBC_CFEND_RATE_88XX); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_RRSR); - value32 = (value32 & ~BIT_MASK_RRSC_BITMAP) | HALMAC_RESPONSE_RATE_88XX; - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RRSR, value32); - - value16 = HALMAC_SIFS_CCK_PTCL_88XX | (HALMAC_SIFS_OFDM_PTCL_88XX << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_SPEC_SIFS, value16); - - value16 = BIT_LRL(HALMAC_LONG_RETRY_LIMIT_88XX) | BIT_SRL(HALMAC_SHORT_RETRY_LIMIT_88XX); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RETRY_LIMIT, value16); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_protocol_cfg_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_init_edca_cfg_88xx() - config EDCA register - * @pHalmac_adapter + * halmac_init_edca_cfg_88xx() - init EDCA config + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_init_edca_cfg_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ) { - u8 value8; u32 value32; VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_EDCA_CFG); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -1014,16 +1117,8 @@ halmac_init_edca_cfg_88xx( HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RD_NAV_NXT, HALMAC_RDG_NAV_88XX | (HALMAC_TXOP_NAV_88XX << 16)); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXTSF_OFFSET_CCK, HALMAC_CCK_RX_TSF_88XX | (HALMAC_OFDM_RX_TSF_88XX) << 8); - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RD_CTRL + 1); - value8 |= (BIT_VOQ_RD_INIT_EN | BIT_VIQ_RD_INIT_EN | BIT_BEQ_RD_INIT_EN); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RD_CTRL + 1, value8); - - /* Set beacon cotrol - enable TSF and other related functions */ + /* Set beacon cotnrol - enable TSF and other related functions */ HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL) | BIT_EN_BCN_FUNCTION)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL_CLINT0, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL_CLINT0) | BIT_CLI0_EN_BCN_FUNCTION)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL_CLINT1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL_CLINT1) | BIT_CLI1_EN_BCN_FUNCTION)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL_CLINT2, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL_CLINT2) | BIT_CLI2_EN_BCN_FUNCTION)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL_CLINT3, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL_CLINT3) | BIT_CLI3_EN_BCN_FUNCTION)); /* Set send beacon related registers */ HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TBTT_PROHIBIT, HALMAC_TBTT_PROHIBIT_88XX | (HALMAC_TBTT_HOLD_TIME_88XX << BIT_SHIFT_TBTT_HOLD_TIME_AP)); @@ -1036,10 +1131,11 @@ halmac_init_edca_cfg_88xx( } /** - * halmac_init_wmac_cfg_88xx() - config WMAC register - * @pHalmac_adapter + * halmac_init_wmac_cfg_88xx() - init wmac config + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_init_wmac_cfg_88xx( @@ -1049,14 +1145,12 @@ halmac_init_wmac_cfg_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_WMAC_CFG); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -1067,15 +1161,19 @@ halmac_init_wmac_cfg_88xx( HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RCR, HALMAC_RCR_CONFIG_88XX); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_SECCFG, HALMAC_SECURITY_CONFIG_88XX); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_PKT_LIMIT, HALMAC_RXPKT_MAX_SIZE_BASE512); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_TCR + 1) | 0x30)); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 2, 0x30); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 1, 0x00); +#if HALMAC_8821C_SUPPORT + if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_ACKTO_CCK, HALMAC_ACK_TO_CCK_88XX); +#endif + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 8, 0x30810041); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4, 0x50802080); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1, 0xC00F0038); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4, 0x50802098); PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_wmac_cfg_88xx <==========\n"); @@ -1084,10 +1182,11 @@ halmac_init_wmac_cfg_88xx( /** * halmac_init_mac_cfg_88xx() - config page1~page7 register - * @pHalmac_adapter - * @mode : normal, trxshare, wmm, p2p, loopback + * @pHalmac_adapter : the adapter of halmac + * @mode : trx mode * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_init_mac_cfg_88xx( @@ -1099,39 +1198,37 @@ halmac_init_mac_cfg_88xx( PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_MAC_CFG); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_mac_cfg_88xx ==========>mode = %d\n", mode); status = pHalmac_api->halmac_init_trx_cfg(pHalmac_adapter, mode); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg errorr = %x\n", status); return status; } #if 1 - status = halmac_init_protocol_cfg_88xx(pHalmac_adapter); - if (HALMAC_RET_SUCCESS != status) { + status = pHalmac_api->halmac_init_protocol_cfg(pHalmac_adapter); + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_protocol_cfg_88xx error = %x\n", status); return status; } status = halmac_init_edca_cfg_88xx(pHalmac_adapter); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_edca_cfg_88xx error = %x\n", status); return status; } status = halmac_init_wmac_cfg_88xx(pHalmac_adapter); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_wmac_cfg_88xx error = %x\n", status); return status; } @@ -1143,10 +1240,11 @@ halmac_init_mac_cfg_88xx( /** * halmac_cfg_operation_mode_88xx() - config operation mode - * @pHalmac_adapter - * @wireless_mode : b/g/n/ac + * @pHalmac_adapter : the adapter of halmac + * @wireless_mode : 802.11 standard(b/g/n/ac¡K) * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_operation_mode_88xx( @@ -1155,34 +1253,32 @@ halmac_cfg_operation_mode_88xx( ) { VOID *pDriver_adapter = NULL; - HALMAC_WIRELESS_MODE wireless_mode_local = HALMAC_WIRELESS_MODE_UNDEFINE; - - wireless_mode_local = wireless_mode; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_OPERATION_MODE); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_operation_mode_88xx ==========>wireless_mode = %d\n", wireless_mode); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_operation_mode_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]wireless_mode = %d\n", wireless_mode); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_operation_mode_88xx <==========\n"); return HALMAC_RET_SUCCESS; } /** - * halmac_cfg_bw_88xx() - config channel & bandwidth - * @pHalmac_adapter + * halmac_cfg_ch_bw_88xx() - config channel & bandwidth + * @pHalmac_adapter : the adapter of halmac * @channel : WLAN channel, support 2.4G & 5G - * @pri_ch_idx : idx1, idx2, idx3, idx4 - * @bw : 20, 40, 80, 160, 5 ,10 + * @pri_ch_idx : primary channel index, idx1, idx2, idx3, idx4 + * @bw : band width, 20, 40, 80, 160, 5 ,10 * Author : KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_ch_bw_88xx( @@ -1193,20 +1289,17 @@ halmac_cfg_ch_bw_88xx( ) { VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CH_BW); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_bw_88xx ==========>ch = %d, idx=%d, bw=%d\n", channel, pri_ch_idx, bw); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_ch_bw_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]ch = %d, idx=%d, bw=%d\n", channel, pri_ch_idx, bw); halmac_cfg_pri_ch_idx_88xx(pHalmac_adapter, pri_ch_idx); @@ -1219,16 +1312,6 @@ halmac_cfg_ch_bw_88xx( return HALMAC_RET_SUCCESS; } - -/** - * halmac_cfg_bw_88xx() - config channel & bandwidth - * @pHalmac_adapter - * @channel : WLAN channel, support 2.4G & 5G - * @pri_ch_idx : idx1, idx2, idx3, idx4 - * @bw : 20, 40, 80, 160, 5 ,10 - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - */ HALMAC_RET_STATUS halmac_cfg_ch_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -1239,18 +1322,17 @@ halmac_cfg_ch_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CH_BW); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_88xx ==========>ch = %d\n", channel); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_ch_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]ch = %d\n", channel); value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CCK_CHECK); value8 = value8 & (~(BIT(7))); @@ -1265,15 +1347,6 @@ halmac_cfg_ch_88xx( return HALMAC_RET_SUCCESS; } -/** - * halmac_cfg_bw_88xx() - config channel & bandwidth - * @pHalmac_adapter - * @channel : WLAN channel, support 2.4G & 5G - * @pri_ch_idx : idx1, idx2, idx3, idx4 - * @bw : 20, 40, 80, 160, 5 ,10 - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - */ HALMAC_RET_STATUS halmac_cfg_pri_ch_idx_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -1284,21 +1357,20 @@ halmac_cfg_pri_ch_idx_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CH_BW); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_pri_ch_idx_88xx ==========> idx=%d\n", pri_ch_idx); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_pri_ch_idx_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]idx=%d\n", pri_ch_idx); txsc_20 = pri_ch_idx; - if ((HALMAC_CH_IDX_1 == txsc_20) || (HALMAC_CH_IDX_3 == txsc_20)) + if ((txsc_20 == HALMAC_CH_IDX_1) || (txsc_20 == HALMAC_CH_IDX_3)) txsc_40 = 9; else txsc_40 = 10; @@ -1308,15 +1380,15 @@ halmac_cfg_pri_ch_idx_88xx( PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_pri_ch_idx_88xx <==========\n"); return HALMAC_RET_SUCCESS; - } /** * halmac_cfg_bw_88xx() - config bandwidth - * @pHalmac_adapter - * @bw : 20, 40, 80, 160, 5 ,10 + * @pHalmac_adapter : the adapter of halmac + * @bw : band width, 20, 40, 80, 160, 5 ,10 * Author : KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_bw_88xx( @@ -1328,18 +1400,17 @@ halmac_cfg_bw_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_BW); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_bw_88xx ==========>bw=%d\n", bw); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_bw_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]bw=%d\n", bw); /* RF Mode */ value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WMAC_TRXPTCL_CTL); @@ -1355,7 +1426,6 @@ halmac_cfg_bw_88xx( case HALMAC_BW_20: case HALMAC_BW_10: case HALMAC_BW_5: - value32 = value32; break; default: PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_bw_88xx switch case not support\n"); @@ -1376,46 +1446,13 @@ halmac_cfg_bw_88xx( return HALMAC_RET_SUCCESS; } -/** - * halmac_clear_security_cam_88xx() - clear security CAM - * @pHalmac_adapter - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - */ -HALMAC_RET_STATUS -halmac_clear_security_cam_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; - - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_clear_security_cam_88xx ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_clear_security_cam_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - /** * halmac_dump_efuse_map_88xx() - dump "physical" efuse map - * @pHalmac_adapter - * @cfg : dump with auto/driver/FW + * @pHalmac_adapter : the adapter of halmac + * @cfg : dump efuse method * Author : Ivan Lin/KaiYuan Chang - * - * halmac_dump_efuse_map_88xx is async architecture, user can - * refer to DumpEfuseMap page of FlowChart.vsd. - * dump_efuse_map page of Halmac_flow_control.vsd is halmac api control - * flow, only for SD1 internal use. - * * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_dump_efuse_map_88xx( @@ -1425,47 +1462,48 @@ halmac_dump_efuse_map_88xx( { VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_EFUSE_MAP); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_88xx ==========>cfg=%d\n", cfg); - if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(dump efuse)...\n"); return HALMAC_RET_BUSY_STATE; } - if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); return HALMAC_RET_ERROR_STATE; } + if (pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_WARN, "[WARN]Dump efuse in suspend mode\n"); + *pProcess_status = HALMAC_CMD_PROCESS_IDLE; pHalmac_adapter->event_trigger.physical_efuse_map = 1; status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); return status; } status = halmac_dump_efuse_88xx(pHalmac_adapter, cfg); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_efuse error = %x\n", status); return status; } - if (_TRUE == pHalmac_adapter->hal_efuse_map_valid) { + if (pHalmac_adapter->hal_efuse_map_valid == _TRUE) { *pProcess_status = HALMAC_CMD_PROCESS_DONE; PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, *pProcess_status, @@ -1473,7 +1511,7 @@ halmac_dump_efuse_map_88xx( pHalmac_adapter->event_trigger.physical_efuse_map = 0; } - if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_88xx <==========\n"); @@ -1483,16 +1521,13 @@ halmac_dump_efuse_map_88xx( /** * halmac_dump_efuse_map_bt_88xx() - dump "BT physical" efuse map - * @pHalmac_adapter - * @cfg : dump with auto/driver/FW + * @pHalmac_adapter : the adapter of halmac + * @halmac_efuse_bank : bt efuse bank + * @bt_efuse_map_size : bt efuse map size. get from halmac_get_efuse_size API + * @pBT_efuse_map : bt efuse map * Author : Soar / Ivan Lin - * - * halmac_dump_efuse_map_bt_88xx is async architecture, user can - * refer to DumpEfuseMap page of FlowChart.vsd. - * dump_efuse_map_bt page of Halmac_flow_control.vsd is halmac api control - * flow, only for SD1 internal use. - * * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_dump_efuse_map_bt_88xx( @@ -1504,16 +1539,14 @@ halmac_dump_efuse_map_bt_88xx( { VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_EFUSE_MAP_BT); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_bt_88xx ==========>\n"); @@ -1526,30 +1559,30 @@ halmac_dump_efuse_map_bt_88xx( return HALMAC_RET_EFUSE_BANK_INCORRECT; } - if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(dump efuse)...\n"); return HALMAC_RET_BUSY_STATE; } - if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); return HALMAC_RET_ERROR_STATE; } status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, halmac_efuse_bank); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); return status; } status = halmac_read_hw_efuse_88xx(pHalmac_adapter, 0, bt_efuse_map_size, pBT_efuse_map); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_hw_efuse_88xx error = %x\n", status); return status; } - if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_bt_88xx <==========\n"); @@ -1557,47 +1590,15 @@ halmac_dump_efuse_map_bt_88xx( return HALMAC_RET_SUCCESS; } -/** - * halmac_read_efuse_88xx() - read "physical" efuse offset - * @pHalmac_adapter - * @halmac_offset - * @pValue - * Author : Ivan Lin/KaiYuan Chang - * Return : HALMAC_RET_STATUS - */ -/* - * HALMAC_RET_STATUS - * halmac_read_efuse_88xx( - * IN PHALMAC_ADAPTER pHalmac_adapter, - * IN u32 halmac_offset, - * OUT u8 *pValue - *) - */ - -/** - * halmac_write_efuse_88xx() - write "physical" efuse offset - * @pHalmac_adapter - * @halmac_offset - * @halmac_value - * Author : Ivan Lin/KaiYuan Chang - * Return : HALMAC_RET_STATUS - */ -/* - * HALMAC_RET_STATUS - * halmac_write_efuse_88xx( - * IN PHALMAC_ADAPTER pHalmac_adapter, - * IN u32 halmac_offset, - * IN u8 halmac_value - *) - */ - /** * halmac_write_efuse_bt_88xx() - write "BT physical" efuse offset - * @pHalmac_adapter - * @halmac_offset - * @halmac_value + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : offset + * @halmac_value : Write value + * @pBT_efuse_map : bt efuse map * Author : Soar * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_write_efuse_bt_88xx( @@ -1610,28 +1611,25 @@ halmac_write_efuse_bt_88xx( VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); - - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_WRITE_EFUSE_BT); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_efuse_bt_88xx ==========>\n"); PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "offset : %X value : %X Bank : %X\n", halmac_offset, halmac_value, halmac_efuse_bank); - if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); return HALMAC_RET_BUSY_STATE; } - if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); return HALMAC_RET_ERROR_STATE; } @@ -1647,18 +1645,18 @@ halmac_write_efuse_bt_88xx( } status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, halmac_efuse_bank); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); return status; } status = halmac_func_write_efuse_88xx(pHalmac_adapter, halmac_offset, halmac_value); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_write_efuse error = %x\n", status); return status; } - if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_efuse_bt_88xx <==========\n"); @@ -1666,12 +1664,158 @@ halmac_write_efuse_bt_88xx( return HALMAC_RET_SUCCESS; } +/** + * halmac_read_efuse_bt_88xx() - read "BT physical" efuse offset + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : offset + * @pValue : 1 byte efuse value + * @HALMAC_EFUSE_BANK : efuse bank + * Author : Soar + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_read_efuse_bt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + OUT u8 *pValue, + IN HALMAC_EFUSE_BANK halmac_efuse_bank +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_efuse_bt_88xx ==========>\n"); + + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (halmac_offset >= pHalmac_adapter->hw_config_info.efuse_size) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if ((halmac_efuse_bank > HALMAC_EFUSE_BANK_MAX) || (halmac_efuse_bank == HALMAC_EFUSE_BANK_WIFI)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Undefined BT bank\n"); + return HALMAC_RET_EFUSE_BANK_INCORRECT; + } + + status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, halmac_efuse_bank); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); + return status; + } + + status = halmac_func_read_efuse_88xx(pHalmac_adapter, halmac_offset, 1, pValue); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_read_efuse error = %x\n", status); + return status; + } + + if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_efuse_bt_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_efuse_auto_check_88xx() - check efuse after writing it + * @pHalmac_adapter : the adapter of halmac + * @enable : 1, enable efuse auto check. others, disable + * Author : Soar + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_efuse_auto_check_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 enable +) +{ + VOID *pDriver_adapter = NULL; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_efuse_auto_check_88xx ==========> function enable = %d\n", enable); + + pHalmac_adapter->efuse_auto_check_en = enable; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_efuse_auto_check_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_get_efuse_available_size_88xx() - get efuse available size + * @pHalmac_adapter : the adapter of halmac + * @halmac_size : physical efuse available size + * Author : Soar + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_get_efuse_available_size_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u32 *halmac_size +) +{ + HALMAC_RET_STATUS status; + VOID *pDriver_adapter = NULL; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_available_size_88xx ==========>\n"); + + status = halmac_dump_logical_efuse_map_88xx(pHalmac_adapter, HALMAC_EFUSE_R_DRV); + + if (status != HALMAC_RET_SUCCESS) + return status; + + *halmac_size = pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - pHalmac_adapter->efuse_end; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_available_size_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + /** * halmac_get_efuse_size_88xx() - get "physical" efuse size - * @pHalmac_adapter - * @halmac_size : Output physical efuse size + * @pHalmac_adapter : the adapter of halmac + * @halmac_size : physical efuse size * Author : Ivan Lin/KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_get_efuse_size_88xx( @@ -1681,14 +1825,12 @@ halmac_get_efuse_size_88xx( { VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_EFUSE_SIZE); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_size_88xx ==========>\n"); @@ -1702,10 +1844,11 @@ halmac_get_efuse_size_88xx( /** * halmac_get_logical_efuse_size_88xx() - get "logical" efuse size - * @pHalmac_adapter - * @halmac_size : Output logical efuse size + * @pHalmac_adapter : the adapter of halmac + * @halmac_size : logical efuse size * Author : Ivan Lin/KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_get_logical_efuse_size_88xx( @@ -1715,14 +1858,12 @@ halmac_get_logical_efuse_size_88xx( { VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_LOGICAL_EFUSE_SIZE); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_logical_efuse_size_88xx ==========>\n"); @@ -1736,16 +1877,11 @@ halmac_get_logical_efuse_size_88xx( /** * halmac_dump_logical_efuse_map_88xx() - dump "logical" efuse map - * @pHalmac_adapter - * @cfg : dump with auto/driver/FW + * @pHalmac_adapter : the adapter of halmac + * @cfg : dump efuse method * Author : Soar - * - * halmac_dump_logical_efuse_map_88xx is async architecture, user can - * refer to DumpEEPROMMap page of FlowChart.vsd. - * dump_efuse_map page of Halmac_flow_control.vsd is halmac api control - * flow, only for SD1 internal use. - * * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_dump_logical_efuse_map_88xx( @@ -1757,58 +1893,61 @@ halmac_dump_logical_efuse_map_88xx( u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_LOGICAL_EFUSE_MAP); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_logical_efuse_map_88xx ==========>cfg = %d\n", cfg); - if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); return HALMAC_RET_BUSY_STATE; } - if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); return HALMAC_RET_ERROR_STATE; } + if (pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_WARN, "[WARN]Dump logical efuse in suspend mode\n"); + *pProcess_status = HALMAC_CMD_PROCESS_IDLE; pHalmac_adapter->event_trigger.logical_efuse_map = 1; status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); return status; } status = halmac_dump_efuse_88xx(pHalmac_adapter, cfg); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_eeprom_parser_88xx error = %x\n", status); return status; } - if (_TRUE == pHalmac_adapter->hal_efuse_map_valid) { + if (pHalmac_adapter->hal_efuse_map_valid == _TRUE) { *pProcess_status = HALMAC_CMD_PROCESS_DONE; pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); - if (NULL == pEeprom_map) { + if (pEeprom_map == NULL) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n"); return HALMAC_RET_MALLOC_FAIL; } PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); - if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map)) + if (halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map) != HALMAC_RET_SUCCESS) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); return HALMAC_RET_EEPROM_PARSING_FAIL; + } PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, *pProcess_status, pEeprom_map, eeprom_size); pHalmac_adapter->event_trigger.logical_efuse_map = 0; @@ -1816,7 +1955,7 @@ halmac_dump_logical_efuse_map_88xx( PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); } - if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_logical_efuse_map_88xx <==========\n"); @@ -1825,12 +1964,13 @@ halmac_dump_logical_efuse_map_88xx( } /** - * halmac_read_logical_efuse_88xx() - read "logical" efuse offset - * @pHalmac_adapter - * @halmac_offset - * @pValue + * halmac_read_logical_efuse_88xx() - read logical efuse map 1 byte + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : offset + * @pValue : 1 byte efuse value * Author : Soar * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_read_logical_efuse_88xx( @@ -1844,16 +1984,14 @@ halmac_read_logical_efuse_88xx( VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_READ_LOGICAL_EFUSE); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_logical_efuse_88xx ==========>\n"); @@ -1863,38 +2001,41 @@ halmac_read_logical_efuse_88xx( return HALMAC_RET_EFUSE_SIZE_INCORRECT; } - if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); return HALMAC_RET_BUSY_STATE; } - if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); return HALMAC_RET_ERROR_STATE; } + status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); + return status; + } + pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); - if (NULL == pEeprom_map) { + if (pEeprom_map == NULL) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n"); return HALMAC_RET_MALLOC_FAIL; } PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); - status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); - return status; - } - status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_logical_efuse_map error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); return status; } *pValue = *(pEeprom_map + halmac_offset); - if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); return HALMAC_RET_ERROR_STATE; + } PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_logical_efuse_88xx <==========\n"); @@ -1905,11 +2046,12 @@ halmac_read_logical_efuse_88xx( /** * halmac_write_logical_efuse_88xx() - write "logical" efuse offset - * @pHalmac_adapter - * @halmac_offset - * @halmac_value + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : offset + * @halmac_value : value * Author : Soar * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_write_logical_efuse_88xx( @@ -1922,16 +2064,14 @@ halmac_write_logical_efuse_88xx( PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_WRITE_LOGICAL_EFUSE); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -1942,29 +2082,29 @@ halmac_write_logical_efuse_88xx( return HALMAC_RET_EFUSE_SIZE_INCORRECT; } - if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); return HALMAC_RET_BUSY_STATE; } - if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); return HALMAC_RET_ERROR_STATE; } status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); return status; } status = halmac_func_write_logical_efuse_88xx(pHalmac_adapter, halmac_offset, halmac_value); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_write_logical_efuse error = %x\n", status); return status; } - if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_logical_efuse_88xx <==========\n"); @@ -1973,12 +2113,13 @@ halmac_write_logical_efuse_88xx( } /** - * halmac_pg_efuse_by_map_88xx() - pg efuse by map - * @pHalmac_adapter - * @pPg_efuse_info : map, map size, mask, mask size - * @cfg : dump with auto/driver/FW + * halmac_pg_efuse_by_map_88xx() - pg logical efuse by map + * @pHalmac_adapter : the adapter of halmac + * @pPg_efuse_info : efuse map information + * @cfg : dump efuse method * Author : Soar * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_pg_efuse_by_map_88xx( @@ -1990,16 +2131,14 @@ halmac_pg_efuse_by_map_88xx( VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PG_EFUSE_BY_MAP); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_pg_efuse_by_map_88xx ==========>\n"); @@ -2019,40 +2158,40 @@ halmac_pg_efuse_by_map_88xx( return HALMAC_RET_EFUSE_SIZE_INCORRECT; } - if (NULL == pPg_efuse_info->pEfuse_map) { + if (pPg_efuse_info->pEfuse_map == NULL) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map is NULL\n"); return HALMAC_RET_NULL_POINTER; } - if (NULL == pPg_efuse_info->pEfuse_mask) { + if (pPg_efuse_info->pEfuse_mask == NULL) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_mask is NULL\n"); return HALMAC_RET_NULL_POINTER; } - if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); return HALMAC_RET_BUSY_STATE; } - if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); return HALMAC_RET_ERROR_STATE; } status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); return status; } status = halmac_func_pg_efuse_by_map_88xx(pHalmac_adapter, pPg_efuse_info, cfg); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_pg_efuse_by_map error = %x\n", status); return status; } - if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_pg_efuse_by_map_88xx <==========\n"); @@ -2062,15 +2201,16 @@ halmac_pg_efuse_by_map_88xx( /** * halmac_get_c2h_info_88xx() - process halmac C2H packet - * @pHalmac_adapter - * @halmac_buf - * @halmac_size + * @pHalmac_adapter : the adapter of halmac + * @halmac_buf : RX Packet pointer + * @halmac_size : RX Packet size * Author : KaiYuan Chang/Ivan Lin * * Used to process c2h packet info from RX path. After receiving the packet, * user need to call this api and pass the packet pointer. * * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_get_c2h_info_88xx( @@ -2083,25 +2223,23 @@ halmac_get_c2h_info_88xx( HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_C2H_INFO); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_c2h_info_88xx ==========>\n"); */ /* Check if it is C2H packet */ - if (_TRUE == GET_RX_DESC_C2H(halmac_buf)) { + if (GET_RX_DESC_C2H(halmac_buf) == _TRUE) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H packet, start parsing!\n"); status = halmac_parse_c2h_packet_88xx(pHalmac_adapter, halmac_buf, halmac_size); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_parse_c2h_packet_88xx error = %x\n", status); return status; } @@ -2113,376 +2251,64 @@ halmac_get_c2h_info_88xx( } /** - * halmac_cfg_fwlps_option_88xx() -config FW LPS option - * @pHalmac_adapter - * @pLps_option : refer to HALMAC_FWLPS_OPTION structure - * Author : KaiYuan Chang/Ivan Lin - * - * Used to config FW LPS option. If user has called this function, - * halmac uses this setting to run FW LPS. If user never called this function, - * halmac uses default setting to run FW LPS - * - * Return : HALMAC_RET_STATUS - */ -HALMAC_RET_STATUS -halmac_cfg_fwlps_option_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_FWLPS_OPTION pLps_option -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_FWLPS_OPTION pHal_fwlps_option; - - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; - - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) - return HALMAC_RET_API_INVALID; - - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_FWLPS_OPTION); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHal_fwlps_option = &(pHalmac_adapter->fwlps_option); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwlps_option_88xx ==========>\n"); - - pHal_fwlps_option->mode = pLps_option->mode; - pHal_fwlps_option->clk_request = pLps_option->clk_request; - pHal_fwlps_option->rlbm = pLps_option->rlbm; - pHal_fwlps_option->smart_ps = pLps_option->smart_ps; - pHal_fwlps_option->awake_interval = pLps_option->awake_interval; - pHal_fwlps_option->all_queue_uapsd = pLps_option->all_queue_uapsd; - pHal_fwlps_option->pwr_state = pLps_option->pwr_state; - pHal_fwlps_option->low_pwr_rx_beacon = pLps_option->low_pwr_rx_beacon; - pHal_fwlps_option->ant_auto_switch = pLps_option->ant_auto_switch; - pHal_fwlps_option->ps_allow_bt_high_Priority = pLps_option->ps_allow_bt_high_Priority; - pHal_fwlps_option->protect_bcn = pLps_option->protect_bcn; - pHal_fwlps_option->silence_period = pLps_option->silence_period; - pHal_fwlps_option->fast_bt_connect = pLps_option->fast_bt_connect; - pHal_fwlps_option->two_antenna_en = pLps_option->two_antenna_en; - pHal_fwlps_option->adopt_user_Setting = pLps_option->adopt_user_Setting; - pHal_fwlps_option->drv_bcn_early_shift = pLps_option->drv_bcn_early_shift; - pHal_fwlps_option->enter_32K = pLps_option->enter_32K; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwlps_option_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_fwips_option_88xx() -config FW IPS option - * @pHalmac_adapter - * @pIps_option : refer to HALMAC_FWIPS_OPTION structure + * (debug API)halmac_h2c_lb_88xx() - send h2c loopback packet + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang/Ivan Lin - * - * Used to config FW IPS option. If user has called this function, - * halmac uses this setting to run FW IPS. If user never called this function, - * halmac uses default setting to run FW IPS - * * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS -halmac_cfg_fwips_option_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_FWIPS_OPTION pIps_option +halmac_h2c_lb_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter ) { VOID *pDriver_adapter = NULL; - PHALMAC_FWIPS_OPTION pIps_option_local; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_FWIPS_OPTION); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwips_option_88xx ==========>\n"); - - pIps_option_local = pIps_option; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_h2c_lb_88xx ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwips_option_88xx <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_h2c_lb_88xx <==========\n"); return HALMAC_RET_SUCCESS; } /** - * halmac_enter_wowlan_88xx() - enter wowlan - * @pHalmac_adapter - * @pWowlan_option + * halmac_debug_88xx() - dump information for debugging + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS -halmac_enter_wowlan_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_WOWLAN_OPTION pWowlan_option +halmac_debug_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter ) { + u8 temp8 = 0; + u32 i = 0, temp32 = 0; VOID *pDriver_adapter = NULL; - PHALMAC_WOWLAN_OPTION pWowlan_option_local; + PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ENTER_WOWLAN); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_wowlan_88xx ==========>\n"); - - pWowlan_option_local = pWowlan_option; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug_88xx ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_wowlan_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_leave_wowlan_88xx() - leave wowlan - * @pHalmac_adapter - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ -HALMAC_RET_STATUS -halmac_leave_wowlan_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; - - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) - return HALMAC_RET_API_INVALID; - - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_LEAVE_WOWLAN); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_wowlan_88xx ==========>\n"); - - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_wowlan_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_enter_ps_88xx() - enter power saving state - * @pHalmac_adapter - * @ps_state - * - * If user has called halmac_cfg_fwlps_option or - * halmac_cfg_fwips_option, halmac uses the specified setting. - * Otherwise, halmac uses default setting. - * - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ -HALMAC_RET_STATUS -halmac_enter_ps_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_PS_STATE ps_state -) -{ - u8 rpwm; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; - - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) - return HALMAC_RET_API_INVALID; - - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) - return HALMAC_RET_NO_DLFW; - - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ENTER_PS); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_ps_88xx ==========>\n"); - - if (ps_state == pHalmac_adapter->halmac_state.ps_state) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "power state is already in PS State!!\n"); - return HALMAC_RET_SUCCESS; - } - - if (HALMAC_PS_STATE_LPS == ps_state) { - status = halmac_send_h2c_set_pwr_mode_88xx(pHalmac_adapter, &(pHalmac_adapter->fwlps_option)); - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_send_h2c_set_pwr_mode_88xx error = %x!!\n", status); - return status; - } - } else if (HALMAC_PS_STATE_IPS == ps_state) { - } - - pHalmac_adapter->halmac_state.ps_state = ps_state; - - /* Enter 32K */ - if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { - if (_TRUE == pHalmac_adapter->fwlps_option.enter_32K) { - rpwm = (u8)(((pHalmac_adapter->rpwm_record ^ (BIT(7))) | (BIT(0))) & 0x81); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HRPWM1, rpwm); - pHalmac_adapter->low_clk = _TRUE; - } - } else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) { - if (_TRUE == pHalmac_adapter->fwlps_option.enter_32K) { - rpwm = (u8)(((pHalmac_adapter->rpwm_record ^ (BIT(7))) | (BIT(0))) & 0x81); - HALMAC_REG_WRITE_8(pHalmac_adapter, 0xFE58, rpwm); - pHalmac_adapter->low_clk = _TRUE; - } - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_ps_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_leave_ps_88xx() - leave power saving state - * @pHalmac_adapter - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ -HALMAC_RET_STATUS -halmac_leave_ps_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u8 rpwm, cpwm; - u32 counter; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_FWLPS_OPTION fw_lps_option; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; - - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) - return HALMAC_RET_API_INVALID; - - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) - return HALMAC_RET_NO_DLFW; - - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_LEAVE_PS); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_ps_88xx ==========>\n"); - - if (HALMAC_PS_STATE_ACT == pHalmac_adapter->halmac_state.ps_state) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "power state is already in active!!\n"); - return HALMAC_RET_SUCCESS; - } - - if (_TRUE == pHalmac_adapter->low_clk) { - cpwm = HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HRPWM1); - rpwm = (u8)(((pHalmac_adapter->rpwm_record ^ (BIT(7))) | (BIT(6))) & 0xC0); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HRPWM1, rpwm); - - cpwm = (u8)((cpwm ^ BIT(7)) & BIT(7)); - counter = 100; - while (cpwm != (HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HRPWM1) & BIT(7))) { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); - counter--; - if (0 == counter) - return HALMAC_RET_CHANGE_PS_FAIL; - } - pHalmac_adapter->low_clk = _FALSE; - } - - PLATFORM_RTL_MEMCPY(pDriver_adapter, &fw_lps_option, &(pHalmac_adapter->fwlps_option), sizeof(HALMAC_FWLPS_OPTION)); - fw_lps_option.mode = 0; - - status = halmac_send_h2c_set_pwr_mode_88xx(pHalmac_adapter, &(fw_lps_option)); - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_send_h2c_set_pwr_mode_88xx error!!=%x\n", status); - return status; - } - - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_ps_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_h2c_lb_88xx() - send h2c loopback packet - * @pHalmac_adapter - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ -HALMAC_RET_STATUS -halmac_h2c_lb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; - - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) - return HALMAC_RET_API_INVALID; - - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_H2C_LB); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_h2c_lb_88xx ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_h2c_lb_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_debug_88xx() - read some registers for debug - * @pHalmac_adapter - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ -HALMAC_RET_STATUS -halmac_debug_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u8 temp8 = 0; - u32 i = 0, temp32 = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; - - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) - return HALMAC_RET_API_INVALID; - - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEBUG); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug_88xx ==========>\n"); - - if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { - /* Dump CCCR, it needs new platform api */ + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { + /* Dump CCCR, it needs new platform api */ /*Dump SDIO Local Register, use CMD52*/ for (i = 0x10250000; i < 0x102500ff; i++) { @@ -2539,10 +2365,10 @@ halmac_debug_88xx( } /** - * halmac_cfg_parameter_88xx() - config register with register array - * @pHalmac_adapter + * halmac_cfg_parameter_88xx() - config parameter by FW + * @pHalmac_adapter : the adapter of halmac * @para_info : cmd id, content - * @full_fifo + * @full_fifo : parameter information * * If msk_en = _TRUE, the format of array is {reg_info, mask, value}. * If msk_en =_FAUSE, the format of array is {reg_info, value} @@ -2562,6 +2388,7 @@ halmac_debug_88xx( * * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_parameter_88xx( @@ -2572,35 +2399,36 @@ halmac_cfg_parameter_88xx( { VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.cfg_para_state_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.cfg_para_state_set.process_status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_NO_DLFW; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_PARAMETER); + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; pDriver_adapter = pHalmac_adapter->pDriver_adapter; /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_parameter_88xx ==========>\n"); */ - if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state) { + if (pHalmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_cfg_parameter_88xx Fail due to DLFW NONE!!\n"); return HALMAC_RET_DLFW_FAIL; } - if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(cfg para)...\n"); return HALMAC_RET_BUSY_STATE; } - if ((HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE != halmac_query_cfg_para_curr_state_88xx(pHalmac_adapter)) && - (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING != halmac_query_cfg_para_curr_state_88xx(pHalmac_adapter))) { + if ((halmac_query_cfg_para_curr_state_88xx(pHalmac_adapter) != HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) && + (halmac_query_cfg_para_curr_state_88xx(pHalmac_adapter) != HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING)) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(cfg para)...\n"); return HALMAC_RET_BUSY_STATE; } @@ -2609,7 +2437,7 @@ halmac_cfg_parameter_88xx( ret_status = halmac_send_h2c_phy_parameter_88xx(pHalmac_adapter, para_info, full_fifo); - if (HALMAC_RET_SUCCESS != ret_status) { + if (ret_status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_phy_parameter_88xx Fail!! = %x\n", ret_status); return ret_status; } @@ -2620,17 +2448,17 @@ halmac_cfg_parameter_88xx( } /** - * halmac_update_packet_88xx() - send some specified packet to FW - * @pHalmac_adapter - * @pkt_id : probe request, sync beacon, discovery beacon - * @pkt - * @pkt_size + * halmac_update_packet_88xx() - send specific packet to FW + * @pHalmac_adapter : the adapter of halmac + * @pkt_id : packet id, to know the purpose of this packet + * @pkt : packet + * @pkt_size : packet size * - * Send new specified packet to FW. - * Note : TX_DESC is not included in the @pkt + * Note : TX_DESC is not included in the pkt * * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_update_packet_88xx( @@ -2641,27 +2469,26 @@ halmac_update_packet_88xx( ) { VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.update_packet_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.update_packet_set.process_status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_NO_DLFW; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_UPDATE_PACKET); + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_packet_88xx ==========>\n"); - if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(update_packet)...\n"); return HALMAC_RET_BUSY_STATE; } @@ -2670,7 +2497,7 @@ halmac_update_packet_88xx( status = halmac_send_h2c_update_packet_88xx(pHalmac_adapter, pkt_id, pkt, pkt_size); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_packet_88xx packet = %x, fail = %x!!\n", pkt_id, status); return status; } @@ -2680,13 +2507,6 @@ halmac_update_packet_88xx( return HALMAC_RET_SUCCESS; } -/** - * halmac_bcn_ie_filter_88xx() - filter beacon & probe response - * @pHalmac_adapter - * @pBcn_ie_info - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ HALMAC_RET_STATUS halmac_bcn_ie_filter_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -2696,16 +2516,17 @@ halmac_bcn_ie_filter_88xx( VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_NO_DLFW; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_BCN_IE_FILTER); + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -2713,7 +2534,7 @@ halmac_bcn_ie_filter_88xx( status = halmac_send_h2c_update_bcn_parse_info_88xx(pHalmac_adapter, pBcn_ie_info); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_bcn_parse_info_88xx fail = %x\n", status); return status; } @@ -2723,14 +2544,6 @@ halmac_bcn_ie_filter_88xx( return HALMAC_RET_SUCCESS; } -/** - * halmac_update_datapack_88xx() - - * @pHalmac_adapter - * @halmac_data_type - * @para_info - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ HALMAC_RET_STATUS halmac_update_datapack_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -2739,42 +2552,28 @@ halmac_update_datapack_88xx( ) { VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_NO_DLFW; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_UPDATE_DATAPACK); + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_datapack_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_update_datapack_88xx ==========>\n"); pDriver_adapter = pHalmac_adapter->pDriver_adapter; - /* ret_status = halmac_send_h2c_update_datapack_88xx(pHalmac_adapter, halmac_data_type, para_info); */ - - if (HALMAC_RET_SUCCESS != ret_status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_datapack_88xx Fail, datatype = %x, status = %x\n", halmac_data_type, ret_status); - return ret_status; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_datapack_88xx <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_update_datapack_88xx <==========\n"); return HALMAC_RET_SUCCESS; } -/** - * halmac_run_datapack_88xx() - - * @pHalmac_adapter - * @halmac_data_type - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ HALMAC_RET_STATUS halmac_run_datapack_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -2784,16 +2583,17 @@ halmac_run_datapack_88xx( VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_NO_DLFW; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_RUN_DATAPACK); + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -2801,7 +2601,7 @@ halmac_run_datapack_88xx( ret_status = halmac_send_h2c_run_datapack_88xx(pHalmac_adapter, halmac_data_type); - if (HALMAC_RET_SUCCESS != ret_status) { + if (ret_status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_run_datapack_88xx Fail, datatype = %x, status = %x!!\n", halmac_data_type, ret_status); return ret_status; } @@ -2813,10 +2613,11 @@ halmac_run_datapack_88xx( /** * halmac_cfg_drv_info_88xx() - config driver info - * @pHalmac_adapter - * @halmac_drv_info : none, phy status, phy sniffer, phy plcp + * @pHalmac_adapter : the adapter of halmac + * @halmac_drv_info : driver information selection * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_drv_info_88xx( @@ -2833,20 +2634,17 @@ halmac_cfg_drv_info_88xx( PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_DRV_INFO); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_info_88xx ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_info = %d\n", halmac_drv_info); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_drv_info_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_drv_info = %d\n", halmac_drv_info); switch (halmac_drv_info) { case HALMAC_DRV_INFO_NONE: @@ -2879,19 +2677,24 @@ halmac_cfg_drv_info_88xx( return status; } + if (pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode != HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) + drv_info_size = HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX >> 3; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_DRVINFO_SZ, drv_info_size); + pHalmac_adapter->drv_info_size = drv_info_size; + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_RCR); value32 = (value32 & (~BIT_APP_PHYSTS)); - if (1 == phy_status_en) + if (phy_status_en == 1) value32 = value32 | BIT_APP_PHYSTS; HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RCR, value32); value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4); value32 = (value32 & (~(BIT(8) | BIT(9)))); - if (1 == sniffer_en) + if (sniffer_en == 1) value32 = value32 | BIT(9); - if (1 == plcp_hdr_en) + if (plcp_hdr_en == 1) value32 = value32 | BIT(8); HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4, value32); @@ -2900,15 +2703,6 @@ halmac_cfg_drv_info_88xx( return HALMAC_RET_SUCCESS; } -/** - * halmac_send_bt_coex_88xx() - - * @pHalmac_adapter - * @pBt_buf - * @bt_size - * @ack - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ HALMAC_RET_STATUS halmac_send_bt_coex_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -2918,28 +2712,24 @@ halmac_send_bt_coex_88xx( ) { VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_NO_DLFW; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SEND_BT_COEX); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_88xx ==========>\n"); ret_status = halmac_send_bt_coex_cmd_88xx(pHalmac_adapter, pBt_buf, bt_size, ack); - if (HALMAC_RET_SUCCESS != ret_status) { + if (ret_status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_bt_coex_cmd_88xx Fail = %x!!\n", ret_status); return ret_status; } @@ -2950,10 +2740,11 @@ halmac_send_bt_coex_88xx( } /** - * halmac_verify_platform_api_88xx() - verify platform api - * @pHalmac_adapter + * (debug API)halmac_verify_platform_api_88xx() - verify platform api + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_verify_platform_api_88xx( @@ -2963,27 +2754,25 @@ halmac_verify_platform_api_88xx( VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_VERIFY_PLATFORM_API); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_verify_platform_api_88xx ==========>\n"); ret_status = halmac_verify_io_88xx(pHalmac_adapter); - if (HALMAC_RET_SUCCESS != ret_status) + if (ret_status != HALMAC_RET_SUCCESS) return ret_status; - if (HALMAC_LA_MODE_FULL != pHalmac_adapter->txff_allocation.la_mode) + if (pHalmac_adapter->txff_allocation.la_mode != HALMAC_LA_MODE_FULL) ret_status = halmac_verify_send_rsvd_page_88xx(pHalmac_adapter); - if (HALMAC_RET_SUCCESS != ret_status) + if (ret_status != HALMAC_RET_SUCCESS) return ret_status; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_verify_platform_api_88xx <==========\n"); @@ -2991,15 +2780,6 @@ halmac_verify_platform_api_88xx( return ret_status; } -/** - * halmac_send_original_h2c_88xx() - send original format h2c packet - * @pHalmac_adapter - * @original_h2c - * @seq - * @ack - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ HALMAC_RET_STATUS halmac_send_original_h2c_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -3009,28 +2789,24 @@ halmac_send_original_h2c_88xx( ) { VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_NO_DLFW; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SEND_ORIGINAL_H2C); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c_88xx ==========>\n"); status = halmac_func_send_original_h2c_88xx(pHalmac_adapter, original_h2c, seq, ack); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_original_h2c FAIL = %x!!\n", status); return status; } @@ -3040,12 +2816,6 @@ halmac_send_original_h2c_88xx( return HALMAC_RET_SUCCESS; } -/** - * halmac_timer_2s_88xx() - periodic operation - * @pHalmac_adapter - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ HALMAC_RET_STATUS halmac_timer_2s_88xx( IN PHALMAC_ADAPTER pHalmac_adapter @@ -3053,10 +2823,10 @@ halmac_timer_2s_88xx( { VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -3071,13 +2841,11 @@ halmac_timer_2s_88xx( /** * halmac_fill_txdesc_check_sum_88xx() - fill in tx desc check sum - * @pHalmac_adapter - * @pCur_desc - * - * User input tx descriptor, halmac output tx descriptor check sum - * + * @pHalmac_adapter : the adapter of halmac + * @pCur_desc : tx desc packet * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_fill_txdesc_check_sum_88xx( @@ -3089,21 +2857,16 @@ halmac_fill_txdesc_check_sum_88xx( u16 *pData = (u16 *)NULL; u32 i; VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_FILL_TXDESC_CHECKSUM); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (NULL == pCur_desc) { + if (pCur_desc == NULL) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_fill_txdesc_check_sum_88xx NULL PTR"); return HALMAC_RET_NULL_POINTER; } @@ -3116,6 +2879,10 @@ halmac_fill_txdesc_check_sum_88xx( for (i = 0; i < 8; i++) chk_result ^= (*(pData + 2 * i) ^ *(pData + (2 * i + 1))); + /* *(pData + 2 * i) & *(pData + (2 * i + 1) have endain issue*/ + /* Process eniadn issue after checksum calculation */ + chk_result = rtk_le16_to_cpu(chk_result); + SET_TX_DESC_TXDESC_CHECKSUM(pCur_desc, chk_result); return HALMAC_RET_SUCCESS; @@ -3123,63 +2890,64 @@ halmac_fill_txdesc_check_sum_88xx( /** * halmac_dump_fifo_88xx() - dump fifo data - * @pHalmac_adapter - * @halmac_fifo_sel : tx, rx, rsvd page, report buff, llt - * @pFifo_map - * @halmac_fifo_dump_size + * @pHalmac_adapter : the adapter of halmac + * @halmac_fifo_sel : FIFO selection + * @halmac_start_addr : start address of selected FIFO + * @halmac_fifo_dump_size : dump size of selected FIFO + * @pFifo_map : FIFO data * * Note : before dump fifo, user need to call halmac_get_fifo_size to * get fifo size. Then input this size to halmac_dump_fifo. * * Author : Ivan Lin/KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_dump_fifo_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN HAL_FIFO_SEL halmac_fifo_sel, - OUT u8 *pFifo_map, - IN u32 halmac_fifo_dump_size + IN u32 halmac_start_addr, + IN u32 halmac_fifo_dump_size, + OUT u8 *pFifo_map ) { VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_FIFO); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_fifo_88xx ==========>\n"); - if (HAL_FIFO_SEL_TX == halmac_fifo_sel && halmac_fifo_dump_size > pHalmac_adapter->hw_config_info.tx_fifo_size) { + if (halmac_fifo_sel == HAL_FIFO_SEL_TX && (halmac_start_addr + halmac_fifo_dump_size) > pHalmac_adapter->hw_config_info.tx_fifo_size) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TX fifo dump size is too large\n"); return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; } - if (HAL_FIFO_SEL_RX == halmac_fifo_sel && halmac_fifo_dump_size > pHalmac_adapter->hw_config_info.rx_fifo_size) { + if (halmac_fifo_sel == HAL_FIFO_SEL_RX && (halmac_start_addr + halmac_fifo_dump_size) > pHalmac_adapter->hw_config_info.rx_fifo_size) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "RX fifo dump size is too large\n"); return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; } - if (0 != (halmac_fifo_dump_size & (4 - 1))) { + if ((halmac_fifo_dump_size & (4 - 1)) != 0) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_fifo_dump_size shall 4byte align\n"); return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; } - if (NULL == pFifo_map) { + if (pFifo_map == NULL) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "pFifo_map address is NULL\n"); return HALMAC_RET_NULL_POINTER; } - status = halmac_buffer_read_88xx(pHalmac_adapter, 0x00, halmac_fifo_dump_size, halmac_fifo_sel, pFifo_map); + status = halmac_buffer_read_88xx(pHalmac_adapter, halmac_start_addr, halmac_fifo_dump_size, halmac_fifo_sel, pFifo_map); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buffer_read_88xx error = %x\n", status); return status; } @@ -3191,10 +2959,11 @@ halmac_dump_fifo_88xx( /** * halmac_get_fifo_size_88xx() - get fifo size - * @pHalmac_adapter - * @halmac_fifo_sel : tx, rx, rsvd page, report buff, llt + * @pHalmac_adapter : the adapter of halmac + * @halmac_fifo_sel : FIFO selection * Author : Ivan Lin/KaiYuan Chang - * Return : fifo size + * Return : u32 + * More details of status code can be found in prototype document */ u32 halmac_get_fifo_size_88xx( @@ -3204,33 +2973,38 @@ halmac_get_fifo_size_88xx( { u32 fifo_size = 0; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_FIFO_SIZE); - - if (HAL_FIFO_SEL_TX == halmac_fifo_sel) + if (halmac_fifo_sel == HAL_FIFO_SEL_TX) fifo_size = pHalmac_adapter->hw_config_info.tx_fifo_size; - else if (HAL_FIFO_SEL_RX == halmac_fifo_sel) + else if (halmac_fifo_sel == HAL_FIFO_SEL_RX) fifo_size = pHalmac_adapter->hw_config_info.rx_fifo_size; - else if (HAL_FIFO_SEL_RSVD_PAGE == halmac_fifo_sel) - fifo_size = ((pHalmac_adapter->hw_config_info.tx_fifo_size >> 7) - pHalmac_adapter->txff_allocation.rsvd_pg_bndy) << 7; - else if (HAL_FIFO_SEL_REPORT == halmac_fifo_sel) + else if (halmac_fifo_sel == HAL_FIFO_SEL_RSVD_PAGE) + fifo_size = ((pHalmac_adapter->hw_config_info.tx_fifo_size >> HALMAC_TX_PAGE_SIZE_2_POWER_88XX) + - pHalmac_adapter->txff_allocation.rsvd_pg_bndy) << HALMAC_TX_PAGE_SIZE_2_POWER_88XX; + else if (halmac_fifo_sel == HAL_FIFO_SEL_REPORT) fifo_size = 65536; - else if (HAL_FIFO_SEL_LLT == halmac_fifo_sel) + else if (halmac_fifo_sel == HAL_FIFO_SEL_LLT) fifo_size = 65536; + else if (halmac_fifo_sel == HAL_FIFO_SEL_RXBUF_FW) + fifo_size = HALMAC_RX_BUF_FW_88XX; return fifo_size; } /** * halmac_cfg_txbf_88xx() - enable/disable specific user's txbf - * @pHalmac_adapter + * @pHalmac_adapter : the adapter of halmac + * @userid : su bfee userid = 0 or 1 to apply TXBF + * @bw : the sounding bandwidth + * @txbf_en : 0: disable TXBF, 1: enable TXBF * Author : chunchu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_txbf_88xx( @@ -3244,14 +3018,12 @@ halmac_cfg_txbf_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TXBF); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -3290,10 +3062,12 @@ halmac_cfg_txbf_88xx( } /** - * halmac_cfg_mumimo_88xx() - - * @pHalmac_adapter + * halmac_cfg_mumimo_88xx() -config mumimo + * @pHalmac_adapter : the adapter of halmac + * @pCfgmu : parameters to configure MU PPDU Tx/Rx * Author : chunchu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_mumimo_88xx( @@ -3308,33 +3082,31 @@ halmac_cfg_mumimo_88xx( u32 gid_valid[6] = {0}; u8 temp14C0 = 0; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MUMIMO); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; if (pCfgmu->role == HAL_BFEE) { /*config MU BFEE*/ temp14C0 = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~BIT_MASK_R_MU_TABLE_VALID; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, (temp14C0|BIT(0)|BIT(1)) & ~(BIT(7))); /*enable MU table 0 and 1, disable MU TX*/ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, (temp14C0 | BIT(0) | BIT(1)) & ~(BIT(7))); /*enable MU table 0 and 1, disable MU TX*/ /*config GID valid table and user position table*/ - mu_tab_sel = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL+1) & ~(BIT(0)|BIT(1)|BIT(2)); + mu_tab_sel = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL + 1) & ~(BIT(0) | BIT(1) | BIT(2)); for (i = 0; i < 2; i++) { - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL+1, mu_tab_sel | i); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL + 1, mu_tab_sel | i); HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, pCfgmu->given_gid_tab[i]); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO, pCfgmu->given_user_pos[i*2]); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO+4, pCfgmu->given_user_pos[i*2+1]); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO, pCfgmu->given_user_pos[i * 2]); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO + 4, pCfgmu->given_user_pos[i * 2 + 1]); } } else { /*config MU BFER*/ - if (_FALSE == pCfgmu->mu_tx_en) { + if (pCfgmu->mu_tx_en == _FALSE) { HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(7))); PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_mumimo_88xx disable mu tx <==========\n"); return HALMAC_RET_SUCCESS; @@ -3385,28 +3157,31 @@ halmac_cfg_mumimo_88xx( } /*set MU STA GID valid TABLE*/ - mu_tab_sel = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL+1) & ~(BIT(0)|BIT(1)|BIT(2)); + mu_tab_sel = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL + 1) & ~(BIT(0) | BIT(1) | BIT(2)); for (idx = 0; idx < 6; idx++) { - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL+1, idx | mu_tab_sel); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL + 1, idx | mu_tab_sel); HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, gid_valid[idx]); } /*To validate the sounding successful MU STA and enable MU TX*/ for (i = 0; i < 6; i++) { - if (_TRUE == pCfgmu->sounding_sts[i]) + if (pCfgmu->sounding_sts[i] == _TRUE) mu_tab_valid |= BIT(i); } - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, mu_tab_valid | BIT(7)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, mu_tab_valid | BIT(7)); } PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_mumimo_88xx <==========\n"); return HALMAC_RET_SUCCESS; } /** - * halmac_cfg_sounding_88xx() - set general sounding control registers - * @pHalmac_adapter + * halmac_cfg_sounding_88xx() - configure general sounding + * @pHalmac_adapter : the adapter of halmac + * @role : driver's role, BFer or BFee + * @datarate : set ndpa tx rate if driver is BFer, or set csi response rate if driver is BFee * Author : chunchu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_sounding_88xx( @@ -3418,14 +3193,12 @@ halmac_cfg_sounding_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_SOUNDING); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -3435,17 +3208,19 @@ halmac_cfg_sounding_88xx( | BIT_USE_NDPA_PARAMETER | BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_NDPA_RATE, datarate); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_NDPA_OPT_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_NDPA_OPT_CTRL) & (~(BIT(0) | BIT(1)))); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 1, 0x2); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 1, 0x2 | BIT(7)); /*service file length 2 bytes; fix non-STA1 csi start offset */ HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 2, 0x2); break; case HAL_BFEE: HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL, 0xDB); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 3, 0x50); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BBPSF_CTRL + 3, datarate); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 3, 0x24); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BBPSF_CTRL + 3, HALMAC_OFDM54 | BIT(6)); //use ndpa rx rate to decide csi rate HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, HALMAC_REG_READ_16(pHalmac_adapter, REG_RRSR) | BIT(datarate)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXFLTMAP1, HALMAC_REG_READ_8(pHalmac_adapter, REG_RXFLTMAP1) & (~(BIT(4)))); /*RXFF do not accept BF Rpt Poll, avoid CSI crc error*/ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXFLTMAP4, HALMAC_REG_READ_8(pHalmac_adapter, REG_RXFLTMAP4) & (~(BIT(4)))); /*FWFF do not accept BF Rpt Poll, avoid CSI crc error*/ break; default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_sounding_88xx invalid role \n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_sounding_88xx invalid role\n"); return HALMAC_RET_INVALID_SOUNDING_SETTING; } @@ -3455,10 +3230,12 @@ halmac_cfg_sounding_88xx( } /** - * halmac_del_sounding_88xx() - reset general sounding control registers - * @pHalmac_adapter + * halmac_del_sounding_88xx() - reset general sounding + * @pHalmac_adapter : the adapter of halmac + * @role : driver's role, BFer or BFee * Author : chunchu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_del_sounding_88xx( @@ -3469,14 +3246,12 @@ halmac_del_sounding_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEL_SOUNDING); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -3488,7 +3263,7 @@ halmac_del_sounding_88xx( HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL, 0); break; default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_del_sounding_88xx invalid role \n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_del_sounding_88xx invalid role\n"); return HALMAC_RET_INVALID_SOUNDING_SETTING; } @@ -3499,9 +3274,12 @@ halmac_del_sounding_88xx( /** * halmac_su_bfee_entry_init_88xx() - config SU beamformee's registers - * @pHalmac_adapter + * @pHalmac_adapter : the adapter of halmac + * @userid : SU bfee userid = 0 or 1 to be added + * @paid : partial AID of this bfee * Author : chunchu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_su_bfee_entry_init_88xx( @@ -3514,14 +3292,12 @@ halmac_su_bfee_entry_init_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFEE_ENTRY_INIT); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -3529,16 +3305,15 @@ halmac_su_bfee_entry_init_88xx( case 0: temp42C = HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, temp42C | paid); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 3, 0x60); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL, paid | BIT(9)); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL, paid); break; case 1: temp42C = HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, temp42C | paid); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 2, paid | BIT(9) | 0xe000); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 2, paid | BIT(9)); break; default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfee_entry_init_88xx invalid userid %d \n", userid); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfee_entry_init_88xx invalid userid %d\n", userid); return HALMAC_RET_INVALID_SOUNDING_SETTING; } @@ -3549,9 +3324,11 @@ halmac_su_bfee_entry_init_88xx( /** * halmac_su_bfee_entry_init_88xx() - config SU beamformer's registers - * @pHalmac_adapter + * @pHalmac_adapter : the adapter of halmac + * @pSu_bfer_init : parameters to configure SU BFER entry * Author : chunchu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_su_bfer_entry_init_88xx( @@ -3564,22 +3341,20 @@ halmac_su_bfer_entry_init_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFER_ENTRY_INIT); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; /* mac_address_L = bfer_address.Address_L_H.Address_Low; */ /* mac_address_H = bfer_address.Address_L_H.Address_High; */ - mac_address_L = rtk_le32_to_cpu(pSu_bfer_init->pbfer_address->Address_L_H.Address_Low); - mac_address_H = rtk_le16_to_cpu(pSu_bfer_init->pbfer_address->Address_L_H.Address_High); + mac_address_L = rtk_le32_to_cpu(pSu_bfer_init->bfer_address.Address_L_H.Address_Low); + mac_address_H = rtk_le16_to_cpu(pSu_bfer_init->bfer_address.Address_L_H.Address_High); switch (pSu_bfer_init->userid) { case 0: @@ -3606,9 +3381,11 @@ halmac_su_bfer_entry_init_88xx( /** * halmac_mu_bfee_entry_init_88xx() - config MU beamformee's registers - * @pHalmac_adapter + * @pHalmac_adapter : the adapter of halmac + * @pMu_bfee_init : parameters to configure MU BFEE entry * Author : chunchu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_mu_bfee_entry_init_88xx( @@ -3620,25 +3397,23 @@ halmac_mu_bfee_entry_init_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFEE_ENTRY_INIT); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; temp168X |= pMu_bfee_init->paid | BIT(9); HALMAC_REG_WRITE_16(pHalmac_adapter, (0x1680 + pMu_bfee_init->userid * 2), temp168X); - temp14C0 = HALMAC_REG_READ_16(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(8)|BIT(9)|BIT(10)); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MU_TX_CTL, temp14C0|((pMu_bfee_init->userid-2)<<8)); + temp14C0 = HALMAC_REG_READ_16(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(8) | BIT(9) | BIT(10)); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MU_TX_CTL, temp14C0 | ((pMu_bfee_init->userid - 2) << 8)); HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, 0); HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO, pMu_bfee_init->user_position_l); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO+4, pMu_bfee_init->user_position_h); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO + 4, pMu_bfee_init->user_position_h); PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfee_entry_init_88xx <==========\n"); @@ -3646,10 +3421,12 @@ halmac_mu_bfee_entry_init_88xx( } /** - * halmac_mu_bfer_entry_init_88xx() - config SU beamformer's registers - * @pHalmac_adapter + * halmac_mu_bfer_entry_init_88xx() - config MU beamformer's registers + * @pHalmac_adapter : the adapter of halmac + * @pMu_bfer_init : parameters to configure MU BFER entry * Author : chunchu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_mu_bfer_entry_init_88xx( @@ -3663,22 +3440,20 @@ halmac_mu_bfer_entry_init_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFER_ENTRY_INIT); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; /* mac_address_L = pHalmac_adapter->snd_info.bfer_address.Address_L_H.Address_Low; */ /* mac_address_H = pHalmac_adapter->snd_info.bfer_address.Address_L_H.Address_High; */ - mac_address_L = rtk_le32_to_cpu(pMu_bfer_init->pbfer_address->Address_L_H.Address_Low); - mac_address_H = rtk_le16_to_cpu(pMu_bfer_init->pbfer_address->Address_L_H.Address_High); + mac_address_L = rtk_le32_to_cpu(pMu_bfer_init->bfer_address.Address_L_H.Address_Low); + mac_address_H = rtk_le16_to_cpu(pMu_bfer_init->bfer_address.Address_L_H.Address_High); HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, mac_address_L); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, mac_address_H); @@ -3696,9 +3471,11 @@ halmac_mu_bfer_entry_init_88xx( /** * halmac_su_bfee_entry_del_88xx() - reset SU beamformee's registers - * @pHalmac_adapter + * @pHalmac_adapter : the adapter of halmac + * @userid : the SU BFee userid to be deleted * Author : chunchu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_su_bfee_entry_del_88xx( @@ -3709,25 +3486,23 @@ halmac_su_bfee_entry_del_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFEE_ENTRY_DEL); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; switch (userid) { case 0: - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & \ + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M)); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL, 0); break; case 1: - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & \ + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M)); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 2, 0); break; @@ -3743,9 +3518,11 @@ halmac_su_bfee_entry_del_88xx( /** * halmac_su_bfee_entry_del_88xx() - reset SU beamformer's registers - * @pHalmac_adapter + * @pHalmac_adapter : the adapter of halmac + * @userid : the SU BFer userid to be deleted * Author : chunchu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_su_bfer_entry_del_88xx( @@ -3756,14 +3533,12 @@ halmac_su_bfer_entry_del_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFER_ENTRY_DEL); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -3788,9 +3563,11 @@ halmac_su_bfer_entry_del_88xx( /** * halmac_mu_bfee_entry_del_88xx() - reset MU beamformee's registers - * @pHalmac_adapter + * @pHalmac_adapter : the adapter of halmac + * @userid : the MU STA userid to be deleted * Author : chunchu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_mu_bfee_entry_del_88xx( @@ -3801,19 +3578,17 @@ halmac_mu_bfee_entry_del_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFEE_ENTRY_DEL); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680 + userid * 2, 0); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(userid-2))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(userid - 2))); PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfee_entry_del_88xx <==========\n"); @@ -3822,9 +3597,10 @@ halmac_mu_bfee_entry_del_88xx( /** * halmac_mu_bfer_entry_del_88xx() -reset MU beamformer's registers - * @pHalmac_adapter + * @pHalmac_adapter : the adapter of halmac * Author : chunchu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_mu_bfer_entry_del_88xx( @@ -3834,14 +3610,12 @@ halmac_mu_bfer_entry_del_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFER_ENTRY_DEL); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -3856,11 +3630,12 @@ halmac_mu_bfer_entry_del_88xx( } /** - * halmac_add_ch_info_88xx() -used to construct channel info - * @pHalmac_adapter - * @pCh_info + * halmac_add_ch_info_88xx() -add channel information + * @pHalmac_adapter : the adapter of halmac + * @pCh_info : channel information * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_add_ch_info_88xx( @@ -3872,32 +3647,32 @@ halmac_add_ch_info_88xx( PHALMAC_CS_INFO pCh_sw_info; HALMAC_SCAN_CMD_CONSTRUCT_STATE state_scan; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ADD_CH_INFO); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pCh_sw_info = &(pHalmac_adapter->ch_sw_info); + pCh_sw_info = &pHalmac_adapter->ch_sw_info; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_ch_info_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_add_ch_info_88xx ==========>\n"); - if (HALMAC_GEN_INFO_SENT != pHalmac_adapter->halmac_state.dlfw_state) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_ch_info_88xx: gen_info is not send to FW!!!!\n"); + if (pHalmac_adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_add_ch_info_88xx: gen_info is not send to FW!!!!\n"); return HALMAC_RET_GEN_INFO_NOT_SENT; } state_scan = halmac_query_scan_curr_state_88xx(pHalmac_adapter); - if ((HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED != state_scan) && (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != state_scan)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Scan machine fail(add ch info)...\n"); + if ((state_scan != HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) && (state_scan != HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "[WARN]Scan machine fail(add ch info)...\n"); return HALMAC_RET_ERROR_STATE; } - if (NULL == pCh_sw_info->ch_info_buf) { + if (pCh_sw_info->ch_info_buf == NULL) { pCh_sw_info->ch_info_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, HALMAC_EXTRA_INFO_BUFF_SIZE_88XX); + if (pCh_sw_info->ch_info_buf == NULL) + return HALMAC_RET_NULL_POINTER; pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf; pCh_sw_info->buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX; pCh_sw_info->avai_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX; @@ -3906,17 +3681,17 @@ halmac_add_ch_info_88xx( pCh_sw_info->ch_num = 0; } - if (1 == pCh_sw_info->extra_info_en) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_ch_info_88xx: construct sequence wrong!!\n"); + if (pCh_sw_info->extra_info_en == 1) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_add_ch_info_88xx: construct sequence wrong!!\n"); return HALMAC_RET_CH_SW_SEQ_WRONG; } - if (4 > pCh_sw_info->avai_buf_size) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_ch_info_88xx: no availabe buffer!!\n"); + if (pCh_sw_info->avai_buf_size < 4) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_add_ch_info_88xx: no available buffer!!\n"); return HALMAC_RET_CH_SW_NO_BUF; } - if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING)) + if (halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; CHANNEL_INFO_SET_CHANNEL(pCh_sw_info->ch_info_buf_w, pCh_info->channel); @@ -3932,17 +3707,18 @@ halmac_add_ch_info_88xx( pCh_sw_info->extra_info_en = pCh_info->extra_info; pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf_w + 4; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_ch_info_88xx <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_add_ch_info_88xx <==========\n"); return HALMAC_RET_SUCCESS; } /** - * halmac_add_extra_ch_info_88xx() -used to construct extra channel info - * @pHalmac_adapter - * @pCh_extra_info + * halmac_add_extra_ch_info_88xx() -add extra channel information + * @pHalmac_adapter : the adapter of halmac + * @pCh_extra_info : extra channel information * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_add_extra_ch_info_88xx( @@ -3953,40 +3729,38 @@ halmac_add_extra_ch_info_88xx( VOID *pDriver_adapter = NULL; PHALMAC_CS_INFO pCh_sw_info; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ADD_EXTRA_CH_INFO); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pCh_sw_info = &(pHalmac_adapter->ch_sw_info); + pCh_sw_info = &pHalmac_adapter->ch_sw_info; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_extra_ch_info_88xx ==========>\n"); - if (NULL == pCh_sw_info->ch_info_buf) { + if (pCh_sw_info->ch_info_buf == NULL) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: NULL==pCh_sw_info->ch_info_buf!!\n"); return HALMAC_RET_CH_SW_SEQ_WRONG; } - if (0 == pCh_sw_info->extra_info_en) { + if (pCh_sw_info->extra_info_en == 0) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: construct sequence wrong!!\n"); return HALMAC_RET_CH_SW_SEQ_WRONG; } if (pCh_sw_info->avai_buf_size < (u32)(pCh_extra_info->extra_info_size + 2)) {/* 2:ch_extra_info_id, ch_extra_info, ch_extra_info_size are totally 2Byte */ - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: no availabe buffer!!\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: no available buffer!!\n"); return HALMAC_RET_CH_SW_NO_BUF; } - if (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != halmac_query_scan_curr_state_88xx(pHalmac_adapter)) { + if (halmac_query_scan_curr_state_88xx(pHalmac_adapter) != HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Scan machine fail(add extra ch info)...\n"); return HALMAC_RET_ERROR_STATE; } - if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING)) + if (halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_action_id); @@ -4005,11 +3779,12 @@ halmac_add_extra_ch_info_88xx( } /** - * halmac_ctrl_ch_switch_88xx() -used to send channel switch cmd - * @pHalmac_adapter - * @pCs_option + * halmac_ctrl_ch_switch_88xx() -send channel switch cmd + * @pHalmac_adapter : the adapter of halmac + * @pCs_option : channel switch config * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_ctrl_ch_switch_88xx( @@ -4021,40 +3796,41 @@ halmac_ctrl_ch_switch_88xx( PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; HALMAC_SCAN_CMD_CONSTRUCT_STATE state_scan; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.scan_state_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.scan_state_set.process_status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_NO_DLFW; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CTRL_CH_SWITCH); + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx pCs_option->switch_en = %d==========>\n", pCs_option->switch_en); - if (_FALSE == pCs_option->switch_en) + if (pCs_option->switch_en == _FALSE) *pProcess_status = HALMAC_CMD_PROCESS_IDLE; - if ((HALMAC_CMD_PROCESS_SENDING == *pProcess_status) || (HALMAC_CMD_PROCESS_RCVD == *pProcess_status)) { + if ((*pProcess_status == HALMAC_CMD_PROCESS_SENDING) || (*pProcess_status == HALMAC_CMD_PROCESS_RCVD)) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(ctrl ch switch)...\n"); return HALMAC_RET_BUSY_STATE; } state_scan = halmac_query_scan_curr_state_88xx(pHalmac_adapter); - if (_TRUE == pCs_option->switch_en) { - if (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != state_scan) { + if (pCs_option->switch_en == _TRUE) { + if (state_scan != HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx(on) invalid in state %x\n", state_scan); return HALMAC_RET_ERROR_STATE; } } else { - if (HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED != state_scan) { + if (state_scan != HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx(off) invalid in state %x\n", state_scan); return HALMAC_RET_ERROR_STATE; } @@ -4062,7 +3838,7 @@ halmac_ctrl_ch_switch_88xx( status = halmac_func_ctrl_ch_switch_88xx(pHalmac_adapter, pCs_option); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_ctrl_ch_switch FAIL = %x!!\n", status); return status; } @@ -4073,10 +3849,11 @@ halmac_ctrl_ch_switch_88xx( } /** - * halmac_clear_ch_info_88xx() -used to clear channel info - * @pHalmac_adapter + * halmac_clear_ch_info_88xx() -clear channel information + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_clear_ch_info_88xx( @@ -4084,27 +3861,23 @@ halmac_clear_ch_info_88xx( ) { VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CLEAR_CH_INFO); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_clear_ch_info_88xx ==========>\n"); - if (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == halmac_query_scan_curr_state_88xx(pHalmac_adapter)) { + if (halmac_query_scan_curr_state_88xx(pHalmac_adapter) == HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Scan machine fail(clear ch info)...\n"); return HALMAC_RET_ERROR_STATE; } - if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED)) + if (halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.buf_size); @@ -4121,12 +3894,95 @@ halmac_clear_ch_info_88xx( return HALMAC_RET_SUCCESS; } +HALMAC_RET_STATUS +halmac_p2pps_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_P2PPS pP2PPS +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (pHalmac_adapter->fw_version.h2c_version < 6) + return HALMAC_RET_FW_NO_SUPPORT; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + status = halmac_func_p2pps_88xx(pHalmac_adapter, pP2PPS); + + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_p2pps FAIL = %x!!\n", status); + return status; + } + + return HALMAC_RET_SUCCESS; +} + +static HALMAC_RET_STATUS +halmac_func_p2pps_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_P2PPS pP2PPS +) +{ + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u16 h2c_seq_mum = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_p2pps !!\n"); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + P2PPS_SET_OFFLOAD_EN(pH2c_buff, pP2PPS->offload_en); + P2PPS_SET_ROLE(pH2c_buff, pP2PPS->role); + P2PPS_SET_CTWINDOW_EN(pH2c_buff, pP2PPS->ctwindow_en); + P2PPS_SET_NOA_EN(pH2c_buff, pP2PPS->noa_en); + P2PPS_SET_NOA_SEL(pH2c_buff, pP2PPS->noa_sel); + P2PPS_SET_ALLSTASLEEP(pH2c_buff, pP2PPS->all_sta_sleep); + P2PPS_SET_DISCOVERY(pH2c_buff, pP2PPS->discovery); + P2PPS_SET_P2P_PORT_ID(pH2c_buff, pP2PPS->p2p_port_id); + P2PPS_SET_P2P_GROUP(pH2c_buff, pP2PPS->p2p_group); + P2PPS_SET_P2P_MACID(pH2c_buff, pP2PPS->p2p_macid); + + P2PPS_SET_CTWINDOW_LENGTH(pH2c_buff, pP2PPS->ctwindow_length); + + P2PPS_SET_NOA_DURATION_PARA(pH2c_buff, pP2PPS->noa_duration_para); + P2PPS_SET_NOA_INTERVAL_PARA(pH2c_buff, pP2PPS->noa_interval_para); + P2PPS_SET_NOA_START_TIME_PARA(pH2c_buff, pP2PPS->noa_start_time_para); + P2PPS_SET_NOA_COUNT_PARA(pH2c_buff, pP2PPS->noa_count_para); + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_P2PPS; + h2c_header_info.content_size = 24; + h2c_header_info.ack = _FALSE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _FALSE); + + if (status != HALMAC_RET_SUCCESS) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_send_h2c_p2pps_88xx Fail = %x!!\n", status); + + return status; +} + /** - * halmac_send_general_info_88xx() -send general info - * @pHalmac_adapter - * @pGeneral_info + * halmac_send_general_info_88xx() -send general information to FW + * @pHalmac_adapter : the adapter of halmac + * @pGeneral_info : general information * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_send_general_info_88xx( @@ -4137,38 +3993,39 @@ halmac_send_general_info_88xx( VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_NO_DLFW; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SEND_GENERAL_INFO); + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info_88xx ==========>\n"); - if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state) { + if (pHalmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_general_info_88xx Fail due to DLFW NONE!!\n"); return HALMAC_RET_DLFW_FAIL; } status = halmac_func_send_general_info_88xx(pHalmac_adapter, pGeneral_info); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_send_general_info error = %x\n", status); return status; } - if (HALMAC_DLFW_DONE == pHalmac_adapter->halmac_state.dlfw_state) + if (pHalmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_DONE) pHalmac_adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT; pHalmac_adapter->gen_info_valid = _TRUE; - PLATFORM_RTL_MEMCPY(pDriver_adapter, &(pHalmac_adapter->general_info), pGeneral_info, sizeof(HALMAC_GENERAL_INFO)); + PLATFORM_RTL_MEMCPY(pDriver_adapter, &pHalmac_adapter->general_info, pGeneral_info, sizeof(HALMAC_GENERAL_INFO)); PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info_88xx <==========\n"); @@ -4176,16 +4033,17 @@ halmac_send_general_info_88xx( } /** - * halmac_start_iqk_88xx() -start iqk - * @pHalmac_adapter - * @clear + * halmac_start_iqk_88xx() -trigger FW IQK + * @pHalmac_adapter : the adapter of halmac + * @pIqk_para : IQK parameter * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_start_iqk_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 clear + IN PHALMAC_IQK_PARA pIqk_para ) { u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; @@ -4193,31 +4051,30 @@ halmac_start_iqk_88xx( VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.iqk_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.iqk_set.process_status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_NO_DLFW; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_START_IQK); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx ==========>\n"); - if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(iqk)...\n"); return HALMAC_RET_BUSY_STATE; } *pProcess_status = HALMAC_CMD_PROCESS_SENDING; - IQK_SET_CLEAR(pH2c_buff, clear); + IQK_SET_CLEAR(pH2c_buff, pIqk_para->clear); + IQK_SET_SEGMENT_IQK(pH2c_buff, pIqk_para->segment_iqk); h2c_header_info.sub_cmd_id = SUB_CMD_ID_IQK; h2c_header_info.content_size = 1; @@ -4228,8 +4085,9 @@ halmac_start_iqk_88xx( status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); + halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_IQK); return status; } @@ -4239,11 +4097,12 @@ halmac_start_iqk_88xx( } /** - * halmac_ctrl_pwr_tracking_88xx() -control power tracking - * @pHalmac_adapter - * @pPwr_tracking_opt + * halmac_ctrl_pwr_tracking_88xx() -trigger FW power tracking + * @pHalmac_adapter : the adapter of halmac + * @pPwr_tracking_opt : power tracking option * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_ctrl_pwr_tracking_88xx( @@ -4256,24 +4115,22 @@ halmac_ctrl_pwr_tracking_88xx( VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.power_tracking_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.power_tracking_set.process_status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_NO_DLFW; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CTRL_PWR_TRACKING); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx ==========>\n"); - if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(pwr tracking)...\n"); return HALMAC_RET_BUSY_STATE; } @@ -4308,8 +4165,9 @@ halmac_ctrl_pwr_tracking_88xx( status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); + halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_POWER_TRACKING); return status; } @@ -4319,21 +4177,22 @@ halmac_ctrl_pwr_tracking_88xx( } /** - * halmac_query_status_88xx() -query async feature status - * @pHalmac_adapter - * @feature_id - * @pProcess_status - * @data - * @size + * halmac_query_status_88xx() -query the offload feature status + * @pHalmac_adapter : the adapter of halmac + * @feature_id : feature_id + * @pProcess_status : feature_status + * @data : data buffer + * @size : data size * * Note : - * If user wants to know the data size, use can allocate random + * If user wants to know the data size, use can allocate zero * size buffer first. If this size less than the data size, halmac * will return HALMAC_RET_BUFFER_TOO_SMALL. User need to * re-allocate data buffer with correct data size. * * Author : Ivan Lin/KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_query_status_88xx( @@ -4347,19 +4206,17 @@ halmac_query_status_88xx( VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_QUERY_STATE); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_query_status_88xx ==========>\n"); */ - if (NULL == pProcess_status) { + if (pProcess_status == NULL) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "null pointer!!\n"); return HALMAC_RET_NULL_POINTER; } @@ -4400,11 +4257,12 @@ halmac_query_status_88xx( } /** - * halmac_reset_feature_88xx() -reset async feature status - * @pHalmac_adapter - * @feature_id + * halmac_reset_feature_88xx() -reset async api cmd status + * @pHalmac_adapter : the adapter of halmac + * @feature_id : feature_id * Author : Ivan Lin/KaiYuan Chang - * Return : HALMAC_RET_STATUS + * Return : HALMAC_RET_STATUS. + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_reset_feature_88xx( @@ -4413,19 +4271,17 @@ halmac_reset_feature_88xx( ) { VOID *pDriver_adapter = NULL; - PHALMAC_STATE pState = &(pHalmac_adapter->halmac_state); + PHALMAC_STATE pState = &pHalmac_adapter->halmac_state; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_RESET_FEATURE); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_reset_feature_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_reset_feature_88xx ==========>\n"); switch (feature_id) { case HALMAC_FEATURE_CFG_PARA: @@ -4444,6 +4300,15 @@ halmac_reset_feature_88xx( case HALMAC_FEATURE_UPDATE_PACKET: pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE; break; + case HALMAC_FEATURE_IQK: + pState->iqk_set.process_status = HALMAC_CMD_PROCESS_IDLE; + break; + case HALMAC_FEATURE_POWER_TRACKING: + pState->power_tracking_set.process_status = HALMAC_CMD_PROCESS_IDLE; + break; + case HALMAC_FEATURE_PSD: + pState->psd_set.process_status = HALMAC_CMD_PROCESS_IDLE; + break; case HALMAC_FEATURE_ALL: pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE; @@ -4452,23 +4317,27 @@ halmac_reset_feature_88xx( pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE; pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->iqk_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->power_tracking_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->psd_set.process_status = HALMAC_CMD_PROCESS_IDLE; break; default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_reset_feature_88xx invalid feature id %d \n", feature_id); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "[ERR]halmac_reset_feature_88xx invalid feature id %d\n", feature_id); return HALMAC_RET_INVALID_FEATURE_ID; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_reset_feature_88xx <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_reset_feature_88xx <==========\n"); return HALMAC_RET_SUCCESS; } /** * halmac_check_fw_status_88xx() -check fw status - * @pHalmac_adapter - * @fw_status + * @pHalmac_adapter : the adapter of halmac + * @fw_status : fw status * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_check_fw_status_88xx( @@ -4478,25 +4347,21 @@ halmac_check_fw_status_88xx( { u32 value32 = 0, value32_backup = 0, i = 0; VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CHECK_FW_STATUS); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_check_fw_status_88xx ==========>\n"); value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG6); - if (0 != value32) { + if (value32 != 0) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_check_fw_status REG_FW_DBG6 !=0\n"); *fw_status = _FALSE; return status; @@ -4506,14 +4371,13 @@ halmac_check_fw_status_88xx( for (i = 0; i <= 10; i++) { value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG7); - if (value32_backup != value32) { + if (value32_backup != value32) break; - } else { - if (10 == i) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_check_fw_status Polling FW PC fail\n"); - *fw_status = _FALSE; - return status; - } + + if (i == 10) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_check_fw_status Polling FW PC fail\n"); + *fw_status = _FALSE; + return status; } } @@ -4522,14 +4386,6 @@ halmac_check_fw_status_88xx( return status; } -/** - * halmac_dump_fw_dmem_88xx() -dump dmem - * @pHalmac_adapter - * @dmem - * @size - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ HALMAC_RET_STATUS halmac_dump_fw_dmem_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -4540,39 +4396,37 @@ halmac_dump_fw_dmem_88xx( VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_FW_DMEM); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_dump_fw_dmem_88xx ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_dump_fw_dmem_88xx <==========\n"); return status; } /** - * halmac_cfg_max_dl_size_88xx() - config max download size - * @pHalmac_adapter - * @halmac_offset - * Author : Ivan Lin/KaiYuan Chang + * halmac_cfg_max_dl_size_88xx() - config max download FW size + * @pHalmac_adapter : the adapter of halmac + * @size : max download fw size * * Halmac uses this setting to set max packet size for * download FW. * If user has not called this API, halmac use default * setting for download FW - * Note1 : size need power of 2 + * Note1 : size need multiple of 2 * Note2 : max size is 31K * + * Author : Ivan Lin/KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_max_dl_size_88xx( @@ -4582,14 +4436,12 @@ halmac_cfg_max_dl_size_88xx( { VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MAX_DL_SIZE); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "halmac_cfg_max_dl_size_88xx ==========>\n"); @@ -4607,19 +4459,19 @@ halmac_cfg_max_dl_size_88xx( pHalmac_adapter->max_download_size = size; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "Cfg max size is : %X\n", size); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "halmac_cfg_max_dl_size_88xx <==========\n"); return HALMAC_RET_SUCCESS; } /** - * halmac_psd_88xx() - trigger fw offload psd - * @pHalmac_adapter - * @start_psd - * @end_psd + * halmac_psd_88xx() - trigger fw psd + * @pHalmac_adapter : the adapter of halmac + * @start_psd : start PSD + * @end_psd : end PSD * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_psd_88xx( @@ -4633,29 +4485,27 @@ halmac_psd_88xx( VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.psd_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.psd_set.process_status; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_NO_DLFW; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PSD); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_psd_88xx ==========>\n"); - if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(psd)...\n"); return HALMAC_RET_BUSY_STATE; } - if (NULL != pHalmac_adapter->halmac_state.psd_set.pData) { + if (pHalmac_adapter->halmac_state.psd_set.pData != NULL) { PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->halmac_state.psd_set.pData, pHalmac_adapter->halmac_state.psd_set.data_size); pHalmac_adapter->halmac_state.psd_set.pData = (u8 *)NULL; } @@ -4675,8 +4525,9 @@ halmac_psd_88xx( status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); + halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_PSD); return status; } @@ -4687,10 +4538,14 @@ halmac_psd_88xx( /** * halmac_cfg_la_mode_88xx() - config la mode - * @pHalmac_adapter - * @la_mode + * @pHalmac_adapter : the adapter of halmac + * @la_mode : + * disable : no TXFF space reserved for LA debug + * partial : partial TXFF space is reserved for LA debug + * full : all TXFF space is reserved for LA debug * Author : KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_la_mode_88xx( @@ -4700,14 +4555,12 @@ halmac_cfg_la_mode_88xx( { VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_LA_MODE); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_la_mode_88xx ==========>la_mode = %d\n", la_mode); @@ -4719,323 +4572,542 @@ halmac_cfg_la_mode_88xx( return HALMAC_RET_SUCCESS; } - /** - * halmac_get_hw_value_88xx() - - * @pHalmac_adapter - * @hw_id - * @pvalue - * Author : KaiYuan Chang + * halmac_cfg_rx_fifo_expanding_mode_88xx() - rx fifo expanding + * @pHalmac_adapter : the adapter of halmac + * @la_mode : + * disable : normal mode + * 1 block : Rx FIFO + 1 FIFO block; Tx fifo - 1 FIFO block + * 2 block : Rx FIFO + 2 FIFO block; Tx fifo - 2 FIFO block + * 3 block : Rx FIFO + 3 FIFO block; Tx fifo - 3 FIFO block + * Author : Soar * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS -halmac_get_hw_value_88xx( +halmac_cfg_rx_fifo_expanding_mode_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_HW_ID hw_id, - OUT VOID *pvalue + IN HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode ) { VOID *pDriver_adapter = NULL; - PHALMAC_RQPN_MAP pRQPN_Map; - u32 *pEfuse_size, *pTxff_size; - u16 *pDrv_pg_bndy; - u16 hcpwm2 = 0; - u8 hcpwm = 0; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_HW_VALUE); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_hw_value_88xx ==========>\n"); - - if (NULL == pvalue) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_get_hw_value_88xx (NULL ==pvalue)==========>\n"); - return HALMAC_RET_NULL_POINTER; - } - switch (hw_id) { - case HALMAC_HW_RQPN_MAPPING: - pRQPN_Map = (PHALMAC_RQPN_MAP)pvalue; - pRQPN_Map->dma_map_vo = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]; - pRQPN_Map->dma_map_vi = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]; - pRQPN_Map->dma_map_be = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]; - pRQPN_Map->dma_map_bk = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]; - pRQPN_Map->dma_map_mg = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]; - pRQPN_Map->dma_map_hi = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]; - break; - case HALMAC_HW_EFUSE_SIZE: - pEfuse_size = (pu32)pvalue; - halmac_get_efuse_size_88xx(pHalmac_adapter, pEfuse_size); - break; - case HALMAC_HW_EEPROM_SIZE: - pEfuse_size = (pu32)pvalue; - *pEfuse_size = pHalmac_adapter->hw_config_info.eeprom_size; - halmac_get_logical_efuse_size_88xx(pHalmac_adapter, pEfuse_size); - break; - case HALMAC_HW_BT_BANK_EFUSE_SIZE: - *(u32 *)pvalue = pHalmac_adapter->hw_config_info.bt_efuse_size; - break; - case HALMAC_HW_BT_BANK1_EFUSE_SIZE: - case HALMAC_HW_BT_BANK2_EFUSE_SIZE: - *(u32 *)pvalue = 0; - break; - case HALMAC_HW_TXFIFO_SIZE: - pTxff_size = (pu32)pvalue; - *pTxff_size = pHalmac_adapter->hw_config_info.tx_fifo_size; - break; - case HALMAC_HW_RSVD_PG_BNDY: - pDrv_pg_bndy = (pu16)pvalue; - *pDrv_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy; - break; - case HALMAC_HW_CAM_ENTRY_NUM: - *(u8 *)pvalue = pHalmac_adapter->hw_config_info.cam_entry_num; - break; - case HALMAC_HW_HCPWM: - halmac_get_hcpwm_88xx(pHalmac_adapter, &hcpwm); - *(u8 *)pvalue = hcpwm; - break; - case HALMAC_HW_HCPWM2: - halmac_get_hcpwm2_88xx(pHalmac_adapter, &hcpwm2); - *(u16 *)pvalue = hcpwm2; - break; - case HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE: - status = halmac_dump_logical_efuse_map_88xx(pHalmac_adapter, HALMAC_EFUSE_R_DRV); - if (HALMAC_RET_SUCCESS != status) - return status; - pEfuse_size = (pu32)pvalue; - *pEfuse_size = pHalmac_adapter->hw_config_info.efuse_size - HALMAC_RESERVED_EFUSE_SIZE_88XX - pHalmac_adapter->efuse_end; - break; - - case HALMAC_HW_TXFF_ALLOCATION: - PLATFORM_RTL_MEMCPY(pDriver_adapter, pvalue, &(pHalmac_adapter->txff_allocation), sizeof(HALMAC_TXFF_ALLOCATION)); - break; - default: - break; - } - + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_rx_fifo_expanding_mode_88xx ==========>rx_fifo_expanding_mode = %d\n", rx_fifo_expanding_mode); + pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode = rx_fifo_expanding_mode; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_hw_value_88xx <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_rx_fifo_expanding_mode_88xx <==========\n"); return HALMAC_RET_SUCCESS; } - -/** - * halmac_set_hw_value_88xx() - - * @pHalmac_adapter - * @hw_id - * @pvalue - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - */ HALMAC_RET_STATUS -halmac_set_hw_value_88xx( +halmac_config_security_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_HW_ID hw_id, - IN void *pvalue + IN PHALMAC_SECURITY_SETTING pSec_setting ) { - VOID *pDriver_adapter = NULL; - u16 hrpwm2 = 0; - u8 hrpwm = 0, value8 = 0; - HALMAC_USB_MODE usb_mode = HALMAC_USB_MODE_U2, current_usb_mode = HALMAC_USB_MODE_U2; - u8 hw_seq_en = 0; - u32 value32 = 0; - u32 usb_temp = 0; - HALMAC_BW bw; - u8 channel, enable_bb; - HALMAC_PRI_CH_IDX pri_ch_idx; PHALMAC_API pHalmac_api; + VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_HW_VALUE); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + pDriver_adapter = pHalmac_adapter->pDriver_adapter; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_hw_value_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_config_security_88xx ==========>\n"); - if (NULL == pvalue) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_set_hw_value_88xx (NULL ==pvalue)==========>\n"); - return HALMAC_RET_NULL_POINTER; + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_CR, (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_CR) | BIT_MAC_SEC_EN)); + + if (pSec_setting->tx_encryption == 1) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) | BIT(2)); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) & ~(BIT(2))); + + if (pSec_setting->rx_decryption == 1) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) | BIT(3)); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) & ~(BIT(3))); + + if (pSec_setting->bip_enable == 1) { + if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8822B) + return HALMAC_RET_BIP_NO_SUPPORT; +#if HALMAC_8821C_SUPPORT + if (pSec_setting->tx_encryption == 1) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) | (BIT(3) | BIT(5))); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) & ~(BIT(3) | BIT(5))); + + if (pSec_setting->rx_decryption == 1) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) | (BIT(4) | BIT(6))); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) & ~(BIT(4) | BIT(6))); +#endif } - switch (hw_id) { - case HALMAC_HW_ID_UNDEFINE: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_config_security_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +u8 +halmac_get_used_cam_entry_num_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HAL_SECURITY_TYPE sec_type +) +{ + u8 entry_num; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_get_used_cam_entry_num_88xx ==========>\n"); + + switch (sec_type) { + case HAL_SECURITY_TYPE_WEP40: + case HAL_SECURITY_TYPE_WEP104: + case HAL_SECURITY_TYPE_TKIP: + case HAL_SECURITY_TYPE_AES128: + case HAL_SECURITY_TYPE_GCMP128: + case HAL_SECURITY_TYPE_GCMSMS4: + case HAL_SECURITY_TYPE_BIP: + entry_num = 1; break; - case HALMAC_HW_HRPWM: - hrpwm = *(u8 *)pvalue; - halmac_set_hrpwm_88xx(pHalmac_adapter, hrpwm); + case HAL_SECURITY_TYPE_WAPI: + case HAL_SECURITY_TYPE_AES256: + case HAL_SECURITY_TYPE_GCMP256: + entry_num = 2; break; - case HALMAC_HW_HRPWM2: - hrpwm2 = *(u16 *)pvalue; - halmac_set_hrpwm2_88xx(pHalmac_adapter, hrpwm2); + default: + entry_num = 0; break; - case HALMAC_HW_USB_MODE: - /* Get driver config USB mode*/ - usb_mode = *(HALMAC_USB_MODE *)pvalue; - - /* Get current USB mode*/ - current_usb_mode = (HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2 + 3) == 0x20) ? HALMAC_USB_MODE_U3 : HALMAC_USB_MODE_U2; + } - /*check if HW supports usb2_usb3 swtich*/ - usb_temp = HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL2); - if (_FALSE == (BIT_GET_USB23_SW_MODE_V1(usb_temp) | (usb_temp & BIT_USB3_USB2_TRANSITION))) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "HALMAC_HW_USB_MODE usb mode HW unsupport\n"); - return HALMAC_RET_USB2_3_SWITCH_UNSUPPORT; - } + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_get_used_cam_entry_num_88xx <==========\n"); - if (usb_mode == current_usb_mode) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "HALMAC_HW_USB_MODE usb mode unchange\n"); - return HALMAC_RET_USB_MODE_UNCHANGE; - } + return entry_num; +} - usb_temp &= ~(BIT_USB23_SW_MODE_V1(0x3)); /* clear 0xC6[3:2] */ +HALMAC_RET_STATUS +halmac_write_cam_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 entry_index, + IN PHALMAC_CAM_ENTRY_INFO pCam_entry_info +) +{ + u32 i; + u32 command = 0x80010000; + PHALMAC_API pHalmac_api; + VOID *pDriver_adapter = NULL; + PHALMAC_CAM_ENTRY_FORMAT pCam_entry_format = NULL; - if (HALMAC_USB_MODE_U2 == usb_mode) { - /* usb3 to usb2 */ - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U2) | BIT_RSM_EN_V1); /* set usb mode and enable timer */ - } else { - /* usb2 to usb3 */ - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U3) | BIT_RSM_EN_V1); /* set usb mode and enable timer */ - } + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PAD_CTRL2 + 1, 4); /* set counter down timer 4x64 ms */ - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_16(pHalmac_adapter, REG_SYS_PW_CTRL) | BIT_APFM_OFFMAC); /* auto MAC off */ - PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL2) | BIT_NO_PDN_CHIPOFF_V1); /* chip off */ - break; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_write_cam_88xx ==========>\n"); - case HALMAC_HW_SEQ_EN: + if (entry_index >= pHalmac_adapter->hw_config_info.cam_entry_num) + return HALMAC_RET_ENTRY_INDEX_ERROR; - hw_seq_en = *(u8 *)pvalue; + if (pCam_entry_info->key_id > 3) + return HALMAC_RET_FAIL; - break; - case HALMAC_HW_BANDWIDTH: + pCam_entry_format = (PHALMAC_CAM_ENTRY_FORMAT)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(*pCam_entry_format)); + if (pCam_entry_format == NULL) + return HALMAC_RET_NULL_POINTER; + PLATFORM_RTL_MEMSET(pDriver_adapter, pCam_entry_format, 0x00, sizeof(*pCam_entry_format)); - bw = *(HALMAC_BW *)pvalue; - halmac_cfg_bw_88xx(pHalmac_adapter, bw); + pCam_entry_format->key_id = pCam_entry_info->key_id; + pCam_entry_format->valid = pCam_entry_info->valid; + PLATFORM_RTL_MEMCPY(pDriver_adapter, pCam_entry_format->mac_address, pCam_entry_info->mac_address, 6); + PLATFORM_RTL_MEMCPY(pDriver_adapter, pCam_entry_format->key, pCam_entry_info->key, 16); + switch (pCam_entry_info->security_type) { + case HAL_SECURITY_TYPE_NONE: + pCam_entry_format->type = 0; break; - case HALMAC_HW_CHANNEL: + case HAL_SECURITY_TYPE_WEP40: + pCam_entry_format->type = 1; + break; + case HAL_SECURITY_TYPE_WEP104: + pCam_entry_format->type = 5; + break; + case HAL_SECURITY_TYPE_TKIP: + pCam_entry_format->type = 2; + break; + case HAL_SECURITY_TYPE_AES128: + pCam_entry_format->type = 4; + break; + case HAL_SECURITY_TYPE_WAPI: + pCam_entry_format->type = 6; + break; + case HAL_SECURITY_TYPE_AES256: + pCam_entry_format->type = 4; + pCam_entry_format->ext_sectype = 1; + break; + case HAL_SECURITY_TYPE_GCMP128: + pCam_entry_format->type = 7; + break; + case HAL_SECURITY_TYPE_GCMP256: + case HAL_SECURITY_TYPE_GCMSMS4: + pCam_entry_format->type = 7; + pCam_entry_format->ext_sectype = 1; + break; + case HAL_SECURITY_TYPE_BIP: + pCam_entry_format->type = (pCam_entry_info->unicast == 1) ? 4 : 0; + pCam_entry_format->mgnt = 1; + pCam_entry_format->grp = (pCam_entry_info->unicast == 1) ? 0 : 1; + break; + default: + PLATFORM_RTL_FREE(pDriver_adapter, pCam_entry_format, sizeof(*pCam_entry_format)); + return HALMAC_RET_FAIL; + } - channel = *(u8 *)pvalue; - halmac_cfg_ch_88xx(pHalmac_adapter, channel); - break; - case HALMAC_HW_PRI_CHANNEL_IDX: + for (i = 0; i < 8; i++) { + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMWRITE, *((u32 *)pCam_entry_format + i)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | ((entry_index << 3) + i)); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]1 - CAM entry format : %X\n", *((u32 *)pCam_entry_format + i)); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]1 - REG_CAMCMD : %X\n", command | ((entry_index << 3) + i)); + } - pri_ch_idx = *(HALMAC_PRI_CH_IDX *)pvalue; - halmac_cfg_pri_ch_idx_88xx(pHalmac_adapter, pri_ch_idx); + if (HAL_SECURITY_TYPE_WAPI == pCam_entry_info->security_type || HAL_SECURITY_TYPE_AES256 == pCam_entry_info->security_type || + HAL_SECURITY_TYPE_GCMP256 == pCam_entry_info->security_type || HAL_SECURITY_TYPE_GCMSMS4 == pCam_entry_info->security_type) { + pCam_entry_format->mic = 1; + PLATFORM_RTL_MEMCPY(pDriver_adapter, pCam_entry_format->key, pCam_entry_info->key_ext, 16); - break; - case HALMAC_HW_EN_BB_RF: + for (i = 0; i < 8; i++) { + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMWRITE, *((u32 *)pCam_entry_format + i)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | (((entry_index + 1) << 3) + i)); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]2 - CAM entry format : %X\n", *((u32 *)pCam_entry_format + i)); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]2 - REG_CAMCMD : %X\n", command | (((entry_index + 1) << 3) + i)); + } + } - enable_bb = *(u8 *)pvalue; + PLATFORM_RTL_FREE(pDriver_adapter, pCam_entry_format, sizeof(*pCam_entry_format)); - if (_TRUE == enable_bb) { - /* enable bb, rf */ - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN); - value8 = value8 | BIT(0) | BIT(1); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN, value8); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_write_cam_88xx <==========\n"); - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RF_CTRL); - value8 = value8 | BIT(0) | BIT(1) | BIT(2); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RF_CTRL, value8); + return HALMAC_RET_SUCCESS; +} - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WLRF1); - value32 = value32 | BIT(24) | BIT(25) | BIT(26); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WLRF1, value32); - } else { - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN); - value8 = value8 & (~(BIT(0) | BIT(1))); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN, value8); +HALMAC_RET_STATUS +halmac_read_cam_entry_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 entry_index, + OUT PHALMAC_CAM_ENTRY_FORMAT pContent +) +{ + u32 i; + u32 command = 0x80000000; + PHALMAC_API pHalmac_api; + VOID *pDriver_adapter = NULL; - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RF_CTRL); - value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2))); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RF_CTRL, value8); + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WLRF1); - value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26))); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WLRF1, value32); - } + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_read_cam_entry_88xx ==========>\n"); - break; + if (entry_index >= pHalmac_adapter->hw_config_info.cam_entry_num) + return HALMAC_RET_ENTRY_INDEX_ERROR; - default: - break; + for (i = 0; i < 8; i++) { + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | ((entry_index << 3) + i)); + *((u32 *)pContent + i) = HALMAC_REG_READ_32(pHalmac_adapter, REG_CAMREAD); } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_hw_value_88xx <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_read_cam_entry_88xx <==========\n"); return HALMAC_RET_SUCCESS; } - -/** - * halmac_cfg_drv_rsvd_pg_num_88xx() - - * @pHalmac_adapter - * @pg_num - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - */ HALMAC_RET_STATUS -halmac_cfg_drv_rsvd_pg_num_88xx( +halmac_clear_cam_entry_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DRV_RSVD_PG_NUM pg_num + IN u32 entry_index ) { + u32 i; + u32 command = 0x80010000; VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + PHALMAC_CAM_ENTRY_FORMAT pCam_entry_format; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_DRV_RSVD_PG_NUM); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_rsvd_pg_num_88xx ==========>pg_num = %d\n", pg_num); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_clear_security_cam_88xx ==========>\n"); - switch (pg_num) { - case HALMAC_RSVD_PG_NUM16: - pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 16; - break; - case HALMAC_RSVD_PG_NUM24: - pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 24; - break; - case HALMAC_RSVD_PG_NUM32: - pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 32; - break; - } + if (entry_index >= pHalmac_adapter->hw_config_info.cam_entry_num) + return HALMAC_RET_ENTRY_INDEX_ERROR; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_rsvd_pg_num_88xx <==========\n"); + pCam_entry_format = (PHALMAC_CAM_ENTRY_FORMAT)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(*pCam_entry_format)); + if (pCam_entry_format == NULL) + return HALMAC_RET_NULL_POINTER; + PLATFORM_RTL_MEMSET(pDriver_adapter, pCam_entry_format, 0x00, sizeof(*pCam_entry_format)); + + for (i = 0; i < 8; i++) { + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMWRITE, *((u32 *)pCam_entry_format + i)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | ((entry_index << 3) + i)); + } + + PLATFORM_RTL_FREE(pDriver_adapter, pCam_entry_format, sizeof(*pCam_entry_format)); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_clear_security_cam_88xx <==========\n"); return HALMAC_RET_SUCCESS; } +/** + * halmac_get_hw_value_88xx() -get hw config value + * @pHalmac_adapter : the adapter of halmac + * @hw_id : hw id for driver to query + * @pvalue : hw value, reference table to get data type + * Author : KaiYuan Chang / Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_get_hw_value_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_HW_ID hw_id, + OUT VOID *pvalue +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_hw_value_88xx ==========>\n"); + + if (pvalue == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_get_hw_value_88xx (NULL ==pvalue)==========>\n"); + return HALMAC_RET_NULL_POINTER; + } + + switch (hw_id) { + case HALMAC_HW_RQPN_MAPPING: + ((PHALMAC_RQPN_MAP)pvalue)->dma_map_vo = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]; + ((PHALMAC_RQPN_MAP)pvalue)->dma_map_vi = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]; + ((PHALMAC_RQPN_MAP)pvalue)->dma_map_be = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]; + ((PHALMAC_RQPN_MAP)pvalue)->dma_map_bk = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]; + ((PHALMAC_RQPN_MAP)pvalue)->dma_map_mg = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]; + ((PHALMAC_RQPN_MAP)pvalue)->dma_map_hi = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]; + break; + case HALMAC_HW_EFUSE_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.efuse_size; + break; + case HALMAC_HW_EEPROM_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.eeprom_size; + break; + case HALMAC_HW_BT_BANK_EFUSE_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.bt_efuse_size; + break; + case HALMAC_HW_BT_BANK1_EFUSE_SIZE: + case HALMAC_HW_BT_BANK2_EFUSE_SIZE: + *(u32 *)pvalue = 0; + break; + case HALMAC_HW_TXFIFO_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.tx_fifo_size; + break; + case HALMAC_HW_RSVD_PG_BNDY: + *(u16 *)pvalue = pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy; + break; + case HALMAC_HW_CAM_ENTRY_NUM: + *(u8 *)pvalue = pHalmac_adapter->hw_config_info.cam_entry_num; + break; + case HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE: /*Remove later*/ + status = halmac_dump_logical_efuse_map_88xx(pHalmac_adapter, HALMAC_EFUSE_R_DRV); + if (status != HALMAC_RET_SUCCESS) + return status; + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - pHalmac_adapter->efuse_end; + break; + case HALMAC_HW_IC_VERSION: + *(u8 *)pvalue = pHalmac_adapter->chip_version; + break; + case HALMAC_HW_PAGE_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.page_size; + break; + case HALMAC_HW_TX_AGG_ALIGN_SIZE: + *(u16 *)pvalue = pHalmac_adapter->hw_config_info.tx_align_size; + break; + case HALMAC_HW_RX_AGG_ALIGN_SIZE: + *(u8 *)pvalue = 8; + break; + case HALMAC_HW_DRV_INFO_SIZE: + *(u8 *)pvalue = pHalmac_adapter->drv_info_size; + break; + case HALMAC_HW_TXFF_ALLOCATION: + PLATFORM_RTL_MEMCPY(pDriver_adapter, pvalue, &pHalmac_adapter->txff_allocation, sizeof(HALMAC_TXFF_ALLOCATION)); + break; + case HALMAC_HW_TX_DESC_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.txdesc_size; + break; + case HALMAC_HW_RX_DESC_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.rxdesc_size; + break; + case HALMAC_HW_AC_OQT_SIZE: + *(u8 *)pvalue = pHalmac_adapter->hw_config_info.ac_oqt_size; + break; + case HALMAC_HW_NON_AC_OQT_SIZE: + *(u8 *)pvalue = pHalmac_adapter->hw_config_info.non_ac_oqt_size; + break; + case HALMAC_HW_AC_QUEUE_NUM: + *(u8 *)pvalue = pHalmac_adapter->hw_config_info.ac_queue_num; + break; + default: + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_hw_value_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} /** - * halmac_get_chip_version_88xx() - - * @pHalmac_adapter - * @version + * halmac_set_hw_value_88xx() -set hw config value + * @pHalmac_adapter : the adapter of halmac + * @hw_id : hw id for driver to config + * @pvalue : hw value, reference table to get data type + * Author : KaiYuan Chang / Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_set_hw_value_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_HW_ID hw_id, + IN VOID *pvalue +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_hw_value_88xx ==========>\n"); + + if (pvalue == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_set_hw_value_88xx (NULL == pvalue)==========>\n"); + return HALMAC_RET_NULL_POINTER; + } + + switch (hw_id) { + case HALMAC_HW_USB_MODE: + status = halmac_set_usb_mode_88xx(pHalmac_adapter, *(HALMAC_USB_MODE *)pvalue); + if (status != HALMAC_RET_SUCCESS) + return status; + break; + case HALMAC_HW_SEQ_EN: + /*if (_TRUE == hw_seq_en) { + } else { + }*/ + break; + case HALMAC_HW_BANDWIDTH: + halmac_cfg_bw_88xx(pHalmac_adapter, *(HALMAC_BW *)pvalue); + break; + case HALMAC_HW_CHANNEL: + halmac_cfg_ch_88xx(pHalmac_adapter, *(u8 *)pvalue); + break; + case HALMAC_HW_PRI_CHANNEL_IDX: + halmac_cfg_pri_ch_idx_88xx(pHalmac_adapter, *(HALMAC_PRI_CH_IDX *)pvalue); + break; + case HALMAC_HW_EN_BB_RF: + halmac_enable_bb_rf_88xx(pHalmac_adapter, *(u8 *)pvalue); + break; + case HALMAC_HW_SDIO_TX_PAGE_THRESHOLD: + halmac_config_sdio_tx_page_threshold_88xx(pHalmac_adapter, (PHALMAC_TX_PAGE_THRESHOLD_INFO)pvalue); + break; + case HALMAC_HW_AMPDU_CONFIG: + halmac_config_ampdu_88xx(pHalmac_adapter, (PHALMAC_AMPDU_CONFIG)pvalue); + break; + case HALMAC_HW_RX_SHIFT: + halmac_rx_shift_88xx(pHalmac_adapter, *(u8 *)pvalue); + break; + default: + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_hw_value_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_drv_rsvd_pg_num_88xx() -config reserved page number for driver + * @pHalmac_adapter : the adapter of halmac + * @pg_num : page number * Author : KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ +HALMAC_RET_STATUS +halmac_cfg_drv_rsvd_pg_num_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DRV_RSVD_PG_NUM pg_num +) +{ + VOID *pDriver_adapter = NULL; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_drv_rsvd_pg_num_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]pg_num = %d\n", pg_num); + + switch (pg_num) { + case HALMAC_RSVD_PG_NUM16: + pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 16; + break; + case HALMAC_RSVD_PG_NUM24: + pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 24; + break; + case HALMAC_RSVD_PG_NUM32: + pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 32; + break; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_rsvd_pg_num_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + HALMAC_RET_STATUS halmac_get_chip_version_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -5045,14 +5117,12 @@ halmac_get_chip_version_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SWITCH_EFUSE_BANK); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -5066,12 +5136,13 @@ halmac_get_chip_version_88xx( } /** - * halmac_chk_txdesc_88xx() - - * @pHalmac_adapter - * @halmac_buf - * @halmac_size + * halmac_chk_txdesc_88xx() -check if the tx packet format is incorrect + * @pHalmac_adapter : the adapter of halmac + * @halmac_buf : tx Packet buffer, tx desc is included + * @halmac_size : tx packet size * Author : KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_chk_txdesc_88xx( @@ -5080,28 +5151,652 @@ halmac_chk_txdesc_88xx( IN u32 halmac_size ) { - VOID *pDriver_adapter = NULL; + u32 mac_clk = 0; PHALMAC_API pHalmac_api; + VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_chk_txdesc_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_chk_txdesc_88xx ==========>\n"); - if (_TRUE == GET_TX_DESC_BMC(pHalmac_buf)) - if (_TRUE == GET_TX_DESC_AGG_EN(pHalmac_buf)) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TxDesc: Agg should not be set when BMC\n"); + if (GET_TX_DESC_BMC(pHalmac_buf) == _TRUE) + if (GET_TX_DESC_AGG_EN(pHalmac_buf) == _TRUE) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]TxDesc: Agg should not be set when BMC\n"); if (halmac_size < (GET_TX_DESC_TXPKTSIZE(pHalmac_buf) + GET_TX_DESC_OFFSET(pHalmac_buf))) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TxDesc: PktSize too small\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]TxDesc: PktSize too small\n"); + + if (GET_TX_DESC_AMSDU_PAD_EN(pHalmac_buf) != 0) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]TxDesc: Do not set AMSDU_PAD_EN\n"); + + switch (BIT_GET_MAC_CLK_SEL(HALMAC_REG_READ_32(pHalmac_adapter, REG_AFE_CTRL1))) { + case 0x0: + mac_clk = 80; + break; + case 0x1: + mac_clk = 40; + break; + case 0x2: + mac_clk = 20; + break; + case 0x3: + mac_clk = 10; + break; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ALWAYS, "MAC clock : 0x%XM\n", mac_clk); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ALWAYS, "TX mac agg enable : 0x%X\n", GET_TX_DESC_AGG_EN(pHalmac_buf)); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ALWAYS, "TX mac agg num : 0x%X\n", GET_TX_DESC_MAX_AGG_NUM(pHalmac_buf)); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_chk_txdesc_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_dl_drv_rsvd_page_88xx() - download packet to rsvd page + * @pHalmac_adapter : the adapter of halmac + * @pg_offset : page offset of driver's rsvd page + * @halmac_buf : data to be downloaded, tx_desc is not included + * @halmac_size : data size to be downloaded + * Author : KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_dl_drv_rsvd_page_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 pg_offset, + IN u8 *pHalmac_buf, + IN u32 halmac_size +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS ret_status; + u16 drv_pg_bndy = 0; + u32 dl_pg_num = 0; + + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dl_drv_rsvd_page_88xx ==========>\n"); + + /*check boundary and size valid*/ + dl_pg_num = halmac_size / pHalmac_adapter->hw_config_info.page_size + ((halmac_size & (pHalmac_adapter->hw_config_info.page_size - 1)) ? 1 : 0); + if (pg_offset + dl_pg_num > pHalmac_adapter->txff_allocation.rsvd_drv_pg_num) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERROR] driver download offset or size error ==========>\n"); + return HALMAC_RET_DRV_DL_ERR; + } + + /*update to target download boundary*/ + drv_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy + pg_offset; + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(drv_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + + ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pHalmac_buf, halmac_size); + + /*restore to original bundary*/ + if (ret_status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", ret_status); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + return ret_status; + } + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dl_drv_rsvd_page_88xx < ==========\n"); + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_csi_rate_88xx() - config CSI frame Tx rate + * @pHalmac_adapter : the adapter of halmac + * @rssi : rssi in decimal value + * @current_rate : current CSI frame rate + * @fixrate_en : enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate + * @new_rate : API returns the final CSI frame rate + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_csi_rate_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 rssi, + IN u8 current_rate, + IN u8 fixrate_en, + OUT u8 *new_rate +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + u32 temp_csi_setting; + u16 current_rrsr; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_csi_rate_88xx ==========>\n"); + +#if HALMAC_8821C_SUPPORT + if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) { + if (fixrate_en) { + temp_csi_setting = HALMAC_REG_READ_32(pHalmac_adapter, REG_BBPSF_CTRL) & ~(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BBPSF_CTRL, temp_csi_setting | BIT_CSI_FORCE_RATE_EN | BIT_CSI_RSC(1) | BIT_WMAC_CSI_RATE(HALMAC_VHT_NSS1_MCS3)); + *new_rate = HALMAC_VHT_NSS1_MCS3; + return HALMAC_RET_SUCCESS; + } + } + temp_csi_setting = HALMAC_REG_READ_32(pHalmac_adapter, REG_BBPSF_CTRL) & ~(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE) & ~BIT_CSI_FORCE_RATE_EN; +#else + temp_csi_setting = HALMAC_REG_READ_32(pHalmac_adapter, REG_BBPSF_CTRL) & ~(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE); +#endif + + current_rrsr = HALMAC_REG_READ_16(pHalmac_adapter, REG_RRSR); + + if (rssi >= 40) { + if (current_rate != HALMAC_OFDM54) { + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, current_rrsr | BIT(HALMAC_OFDM54)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BBPSF_CTRL, temp_csi_setting | BIT_WMAC_CSI_RATE(HALMAC_OFDM54)); + } + *new_rate = HALMAC_OFDM54; + return HALMAC_RET_SUCCESS; + } + + if (current_rate != HALMAC_OFDM24) { + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, current_rrsr & ~(BIT(HALMAC_OFDM54))); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BBPSF_CTRL, temp_csi_setting | BIT_WMAC_CSI_RATE(HALMAC_OFDM24)); + } + *new_rate = HALMAC_OFDM24; + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_txfifo_is_empty_88xx() -check if txfifo is empty + * @pHalmac_adapter : the adapter of halmac + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_txfifo_is_empty_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 chk_num +) +{ + u32 counter; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_txfifo_is_empty_88xx ==========>\n"); + + counter = (chk_num <= 10) ? 10 : chk_num; + do { + if (HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPKT_EMPTY) != 0xFF) + return HALMAC_RET_TXFIFO_NO_EMPTY; + + if ((HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPKT_EMPTY + 1) & 0x07) != 0x07) + return HALMAC_RET_TXFIFO_NO_EMPTY; + counter--; + + } while (counter != 0); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_txfifo_is_empty_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_download_flash_88xx() -download firmware to flash + * @pHalmac_adapter : the adapter of halmac + * @pHalmac_fw : pointer to fw + * @halmac_fw_size : fw size + * @rom_address : flash start address where fw should be download + * Author : Pablo Chiu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_download_flash_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHalmac_fw, + IN u32 halmac_fw_size, + IN u32 rom_address +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS status; + HALMAC_H2C_HEADER_INFO h2c_header_info; + u8 value8; + u8 restore[3]; + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0}; + u16 h2c_seq_mum = 0; + u32 send_pkt_size, mem_offset; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_flash_88xx ==========>\n"); + + pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + + value8 = HALMAC_DMA_MAPPING_HIGH << 6; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP + 1, value8); + + /* DLFW only use HIQ, map HIQ to hi priority */ + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; + value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31)); + + /* Config hi priority queue and public priority queue page number (only for DLFW) */ + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, 0x200); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31)); + + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { + HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_TX_CTRL, 0x00000000); + } + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 1); + restore[0] = value8; + value8 = (u8)(value8 | BIT(0)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, value8); + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL); + restore[1] = value8; + value8 = (u8)((value8 & (~(BIT(3)))) | BIT(4)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, value8); + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2); + restore[2] = value8; + value8 = (u8)(value8 & ~(BIT(6))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8); + + /* Set beacon header to 0 */ + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0x8000); + + /* Download FW to Flash flow */ + mem_offset = 0; + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + + while (halmac_fw_size != 0) { + if (halmac_fw_size >= (HALMAC_EXTRA_INFO_BUFF_SIZE_88XX - 48)) + send_pkt_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX - 48; + else + send_pkt_size = halmac_fw_size; + + status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pHalmac_fw + mem_offset, send_pkt_size); + + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", status); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + goto DLFW_FAIL; + } else { + /* Construct H2C Content */ + DOWNLOAD_FLASH_SET_SPI_CMD(pH2c_buff, 0x02); + DOWNLOAD_FLASH_SET_LOCATION(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy); + DOWNLOAD_FLASH_SET_SIZE(pH2c_buff, send_pkt_size); + DOWNLOAD_FLASH_SET_START_ADDR(pH2c_buff, rom_address); + + /* Fill in H2C Header */ + h2c_header_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH; + h2c_header_info.content_size = 20; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + + /* Send H2C Cmd Packet */ + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n"); + goto DLFW_FAIL; + } + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I); + value8 |= BIT(0); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUTST_I, value8); + } + + rom_address += send_pkt_size; + mem_offset += send_pkt_size; + halmac_fw_size -= send_pkt_size; + + while (((HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I)) & BIT(0)) != 0) + PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000); + + if (((HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I)) & BIT(0)) != 0) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "download flash fail!!\n"); + goto DLFW_FAIL; + } + } + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, restore[2]); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, restore[1]); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, restore[0]); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_flash_88xx <==========\n"); + return HALMAC_RET_SUCCESS; + +DLFW_FAIL: + + return HALMAC_RET_DLFW_FAIL; +} + +/** + * halmac_read_flash_88xx() -read data from flash + * @pHalmac_adapter : the adapter of halmac + * @addr : flash start address where fw should be read + * Author : Pablo Chiu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_read_flash_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + u32 addr +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS status; + HALMAC_H2C_HEADER_INFO h2c_header_info; + u8 value8; + u8 restore[3]; + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0}; + u16 h2c_seq_mum = 0; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_flash_88xx ==========>\n"); + + pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + + value8 = HALMAC_DMA_MAPPING_HIGH << 6; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP + 1, value8); + + /* DLFW only use HIQ, map HIQ to hi priority */ + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; + value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31)); + + /* Config hi priority queue and public priority queue page number (only for DLFW) */ + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, 0x200); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31)); + + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { + HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_TX_CTRL, 0x00000000); + } + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 1); + restore[0] = value8; + value8 = (u8)(value8 | BIT(0)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, value8); + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL); + restore[1] = value8; + value8 = (u8)((value8 & (~(BIT(3)))) | BIT(4)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, value8); + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2); + restore[2] = value8; + value8 = (u8)(value8 & ~(BIT(6))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8); + + /* Set beacon header to 0 */ + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0x8000); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I); + value8 |= BIT(0); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUTST_I, value8); + + /* Construct H2C Content */ + DOWNLOAD_FLASH_SET_SPI_CMD(pH2c_buff, 0x03); + DOWNLOAD_FLASH_SET_LOCATION(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy); + DOWNLOAD_FLASH_SET_SIZE(pH2c_buff, 4096); + DOWNLOAD_FLASH_SET_START_ADDR(pH2c_buff, addr); + + /* Fill in H2C Header */ + h2c_header_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH; + h2c_header_info.content_size = 16; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + + /* Send H2C Cmd Packet */ + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n"); + goto DLFW_FAIL; + } + + while (((HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I)) & BIT(0)) != 0) + PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000); + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, restore[2]); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, restore[1]); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, restore[0]); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_flash_88xx <==========\n"); + return HALMAC_RET_SUCCESS; + +DLFW_FAIL: + + return HALMAC_RET_FAIL; +} + +/** + * halmac_erase_flash_88xx() -erase flash data + * @pHalmac_adapter : the adapter of halmac + * @erase_cmd : erase command + * @addr : flash start address where fw should be erased + * Author : Pablo Chiu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_erase_flash_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + u8 erase_cmd, + u32 addr +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status; + HALMAC_H2C_HEADER_INFO h2c_header_info; + PHALMAC_API pHalmac_api; + u8 value8; + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0}; + u16 h2c_seq_mum = 0; + u32 timeout; + + /* Construct H2C Content */ + DOWNLOAD_FLASH_SET_SPI_CMD(pH2c_buff, erase_cmd); + DOWNLOAD_FLASH_SET_LOCATION(pH2c_buff, 0); + DOWNLOAD_FLASH_SET_START_ADDR(pH2c_buff, addr); + DOWNLOAD_FLASH_SET_SIZE(pH2c_buff, 0); + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I); + value8 |= BIT(0); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUTST_I, value8); + + /* Fill in H2C Header */ + h2c_header_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH; + h2c_header_info.content_size = 16; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + + /* Send H2C Cmd Packet */ + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + + if (status != HALMAC_RET_SUCCESS) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n"); + + timeout = 5000; + while ((((HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I)) & BIT(0)) != 0) && (timeout != 0)) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000); + timeout--; + } + + if (timeout == 0) + return HALMAC_RET_FAIL; + else + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_check_flash_88xx() -check flash data + * @pHalmac_adapter : the adapter of halmac + * @pHalmac_fw : pointer to fw + * @halmac_fw_size : fw size + * @addr : flash start address where fw should be checked + * Author : Pablo Chiu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_check_flash_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHalmac_fw, + IN u32 halmac_fw_size, + IN u32 addr +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + u8 value8; + u16 value16, residue; + u32 send_pkt_size, start_page, counter; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + while (halmac_fw_size != 0) { + start_page = ((pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy << 7) >> 12) + 0x780; + residue = (pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy << 7) & (4096 - 1); + + if (halmac_fw_size >= HALMAC_EXTRA_INFO_BUFF_SIZE_88XX) + send_pkt_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX; + else + send_pkt_size = halmac_fw_size; + + halmac_read_flash_88xx(pHalmac_adapter, addr); + + value16 = HALMAC_REG_READ_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL); + counter = 0; + while (counter < send_pkt_size) { + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL, (u16)(start_page | (value16 & 0xF000))); + for (value16 = 0x8000 + residue; value16 <= 0x8FFF; value16++) { + value8 = HALMAC_REG_READ_8(pHalmac_adapter, value16); + + if (*pHalmac_fw != value8) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "check flash fail!!\n"); + goto DLFW_FAIL; + } + pHalmac_fw++; + + counter++; + if (counter == send_pkt_size) + break; + } + residue = 0; + start_page++; + } + addr += send_pkt_size; + halmac_fw_size -= send_pkt_size; + } + + return HALMAC_RET_SUCCESS; + +DLFW_FAIL: + + return HALMAC_RET_FAIL; +} + + +/** + * halmac_cfg_edca_para_88xx() - config edca parameter + * @pHalmac_adapter : the adapter of halmac + * @acq_id : VO/VI/BE/BK + * @pEdca_para : aifs, cw, txop limit + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_edca_para_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_ACQ_ID acq_id, + IN PHALMAC_EDCA_PARA pEdca_para +) +{ + u32 offset, value32; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_edca_88xx ==========>\n"); + + switch (acq_id) { + case HALMAC_ACQ_ID_VO: + offset = REG_EDCA_VO_PARAM; + break; + case HALMAC_ACQ_ID_VI: + offset = REG_EDCA_VI_PARAM; + break; + case HALMAC_ACQ_ID_BE: + offset = REG_EDCA_BE_PARAM; + break; + case HALMAC_ACQ_ID_BK: + offset = REG_EDCA_BK_PARAM; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + value32 = (pEdca_para->aifs & 0xFF) | ((pEdca_para->cw & 0xFF) << 8) | ((pEdca_para->txop_limit & 0x7FF) << 16); + + HALMAC_REG_WRITE_32(pHalmac_adapter, offset, value32); - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "halmac_chk_txdesc_88xx <==========\n"); */ + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_edca_88xx <==========\n"); return HALMAC_RET_SUCCESS; } diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx.h b/hal/halmac/halmac_88xx/halmac_api_88xx.h index 252941a..74a747f 100644 --- a/hal/halmac/halmac_88xx/halmac_api_88xx.h +++ b/hal/halmac/halmac_88xx/halmac_api_88xx.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_API_88XX_H_ #define _HALMAC_API_88XX_H_ @@ -14,6 +29,11 @@ halmac_init_adapter_para_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ); +VOID +halmac_init_adapter_dynamic_para_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + HALMAC_RET_STATUS halmac_mount_api_88xx( IN PHALMAC_ADAPTER pHalmac_adapter @@ -26,6 +46,14 @@ halmac_download_firmware_88xx( IN u32 halmac_fw_size ); +HALMAC_RET_STATUS +halmac_free_download_firmware_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DLFW_MEM dlfw_mem, + IN u8 *pHamacl_fw, + IN u32 halmac_fw_size +); + HALMAC_RET_STATUS halmac_get_fw_version_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -68,11 +96,6 @@ halmac_cfg_rx_aggregation_88xx( IN HALMAC_RXAGG_CFG halmac_rxagg_cfg ); -HALMAC_RET_STATUS -halmac_init_protocol_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - HALMAC_RET_STATUS halmac_init_edca_cfg_88xx( IN PHALMAC_ADAPTER pHalmac_adapter @@ -121,11 +144,6 @@ halmac_init_mac_cfg_88xx( IN HALMAC_TRX_MODE mode ); -HALMAC_RET_STATUS -halmac_clear_security_cam_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - HALMAC_RET_STATUS halmac_dump_efuse_map_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -148,6 +166,20 @@ halmac_write_efuse_bt_88xx( IN HALMAC_EFUSE_BANK halmac_efuse_bank ); +HALMAC_RET_STATUS +halmac_read_efuse_bt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + OUT u8 *pValue, + IN HALMAC_EFUSE_BANK halmac_efuse_bank +); + +HALMAC_RET_STATUS +halmac_cfg_efuse_auto_check_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 enable +); + HALMAC_RET_STATUS halmac_pg_efuse_by_map_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -161,6 +193,12 @@ halmac_get_efuse_size_88xx( OUT u32 *halmac_size ); +HALMAC_RET_STATUS +halmac_get_efuse_available_size_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u32 *halmac_size +); + HALMAC_RET_STATUS halmac_get_c2h_info_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -194,40 +232,6 @@ halmac_read_logical_efuse_88xx( OUT u8 *pValue ); -HALMAC_RET_STATUS -halmac_cfg_fwlps_option_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_FWLPS_OPTION pLps_option -); - -HALMAC_RET_STATUS -halmac_cfg_fwips_option_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_FWIPS_OPTION pIps_option -); - -HALMAC_RET_STATUS -halmac_enter_wowlan_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_WOWLAN_OPTION pWowlan_option -); - -HALMAC_RET_STATUS -halmac_leave_wowlan_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_enter_ps_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_PS_STATE ps_state -); - -HALMAC_RET_STATUS -halmac_leave_ps_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - HALMAC_RET_STATUS halmac_h2c_lb_88xx( IN PHALMAC_ADAPTER pHalmac_adapter @@ -314,8 +318,9 @@ HALMAC_RET_STATUS halmac_dump_fifo_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN HAL_FIFO_SEL halmac_fifo_sel, - OUT u8 *pFifo_map, - IN u32 halmac_fifo_dump_size + IN u32 halmac_start_addr, + IN u32 halmac_fifo_dump_size, + OUT u8 *pFifo_map ); u32 @@ -417,6 +422,18 @@ halmac_ctrl_ch_switch_88xx( IN PHALMAC_CH_SWITCH_OPTION pCs_option ); +HALMAC_RET_STATUS +halmac_p2pps_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_P2PPS pP2PPS +); + +static HALMAC_RET_STATUS +halmac_func_p2pps_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_P2PPS pP2PPS +); + HALMAC_RET_STATUS halmac_clear_ch_info_88xx( IN PHALMAC_ADAPTER pHalmac_adapter @@ -431,7 +448,7 @@ halmac_send_general_info_88xx( HALMAC_RET_STATUS halmac_start_iqk_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 clear + IN PHALMAC_IQK_PARA pIqk_para ); HALMAC_RET_STATUS @@ -488,6 +505,44 @@ halmac_cfg_la_mode_88xx( IN HALMAC_LA_MODE la_mode ); +HALMAC_RET_STATUS +halmac_cfg_rx_fifo_expanding_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode +); + +HALMAC_RET_STATUS +halmac_config_security_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_SECURITY_SETTING pSec_setting +); + +u8 +halmac_get_used_cam_entry_num_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HAL_SECURITY_TYPE sec_type +); + +HALMAC_RET_STATUS +halmac_write_cam_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 entry_index, + IN PHALMAC_CAM_ENTRY_INFO pCam_entry_info +); + +HALMAC_RET_STATUS +halmac_read_cam_entry_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 entry_index, + OUT PHALMAC_CAM_ENTRY_FORMAT pContent +); + +HALMAC_RET_STATUS +halmac_clear_cam_entry_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 entry_index +); + HALMAC_RET_STATUS halmac_get_hw_value_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -521,5 +576,63 @@ halmac_chk_txdesc_88xx( IN u32 halmac_size ); +HALMAC_RET_STATUS +halmac_dl_drv_rsvd_page_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 pg_offset, + IN u8 *pHalmac_buf, + IN u32 halmac_size +); + +HALMAC_RET_STATUS +halmac_cfg_csi_rate_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 rssi, + IN u8 current_rate, + IN u8 fixrate_en, + OUT u8 *new_rate +); + +HALMAC_RET_STATUS +halmac_txfifo_is_empty_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 chk_num +); + +HALMAC_RET_STATUS +halmac_download_flash_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHalmac_fw, + IN u32 halmac_fw_size, + IN u32 rom_address +); + +HALMAC_RET_STATUS +halmac_read_flash_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + u32 addr +); + +HALMAC_RET_STATUS +halmac_erase_flash_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + u8 erase_cmd, + u32 addr +); + +HALMAC_RET_STATUS +halmac_check_flash_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHalmac_fw, + IN u32 halmac_fw_size, + IN u32 addr +); + +HALMAC_RET_STATUS +halmac_cfg_edca_para_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_ACQ_ID acq_id, + IN PHALMAC_EDCA_PARA pEdca_para +); #endif/* _HALMAC_API_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c b/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c index 76e5cd3..c08801b 100644 --- a/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c +++ b/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c @@ -1,10 +1,26 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "halmac_88xx_cfg.h" /** - * halmac_init_pcie_cfg_88xx() - init PCIE related register - * @pHalmac_adapter + * halmac_init_pcie_cfg_88xx() - init PCIe + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_init_pcie_cfg_88xx( @@ -13,14 +29,12 @@ halmac_init_pcie_cfg_88xx( { VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_PCIE_CFG); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_pcie_cfg_88xx ==========>\n"); @@ -31,10 +45,11 @@ halmac_init_pcie_cfg_88xx( } /** - * halmac_deinit_pcie_cfg_88xx() - deinit PCIE related register - * @pHalmac_adapter + * halmac_deinit_pcie_cfg_88xx() - deinit PCIE + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_deinit_pcie_cfg_88xx( @@ -43,14 +58,12 @@ halmac_deinit_pcie_cfg_88xx( { VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEINIT_PCIE_CFG); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_pcie_cfg_88xx ==========>\n"); @@ -62,10 +75,11 @@ halmac_deinit_pcie_cfg_88xx( /** * halmac_cfg_rx_aggregation_88xx_pcie() - config rx aggregation - * @pHalmac_adapter + * @pHalmac_adapter : the adapter of halmac * @halmac_rx_agg_mode * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_rx_aggregation_88xx_pcie( @@ -75,14 +89,12 @@ halmac_cfg_rx_aggregation_88xx_pcie( { VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_RX_AGGREGATION); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_pcie ==========>\n"); @@ -94,10 +106,11 @@ halmac_cfg_rx_aggregation_88xx_pcie( /** * halmac_reg_read_8_pcie_88xx() - read 1byte register - * @pHalmac_adapter - * @halmac_offset + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ u8 halmac_reg_read_8_pcie_88xx( @@ -108,10 +121,10 @@ halmac_reg_read_8_pcie_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -122,11 +135,12 @@ halmac_reg_read_8_pcie_88xx( /** * halmac_reg_write_8_pcie_88xx() - write 1byte register - * @pHalmac_adapter - * @halmac_offset - * @halmac_data + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_data : register value * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_reg_write_8_pcie_88xx( @@ -138,10 +152,10 @@ halmac_reg_write_8_pcie_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -154,10 +168,11 @@ halmac_reg_write_8_pcie_88xx( /** * halmac_reg_read_16_pcie_88xx() - read 2byte register - * @pHalmac_adapter - * @halmac_offset + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ u16 halmac_reg_read_16_pcie_88xx( @@ -168,10 +183,10 @@ halmac_reg_read_16_pcie_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -182,11 +197,12 @@ halmac_reg_read_16_pcie_88xx( /** * halmac_reg_write_16_pcie_88xx() - write 2byte register - * @pHalmac_adapter - * @halmac_offset - * @halmac_data + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_data : register value * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_reg_write_16_pcie_88xx( @@ -198,10 +214,10 @@ halmac_reg_write_16_pcie_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -214,10 +230,11 @@ halmac_reg_write_16_pcie_88xx( /** * halmac_reg_read_32_pcie_88xx() - read 4byte register - * @pHalmac_adapter - * @halmac_offset + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ u32 halmac_reg_read_32_pcie_88xx( @@ -228,10 +245,10 @@ halmac_reg_read_32_pcie_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -242,11 +259,12 @@ halmac_reg_read_32_pcie_88xx( /** * halmac_reg_write_32_pcie_88xx() - write 4byte register - * @pHalmac_adapter - * @halmac_offset - * @halmac_data + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_data : register value * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_reg_write_32_pcie_88xx( @@ -258,10 +276,10 @@ halmac_reg_write_32_pcie_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -273,12 +291,13 @@ halmac_reg_write_32_pcie_88xx( } /** - * halmac_cfg_tx_agg_align_pcie_not_support_88xx() - - * @pHalmac_adapter - * @enable - * @align_size + * halmac_cfg_tx_agg_align_pcie_88xx() -config sdio bus tx agg alignment + * @pHalmac_adapter : the adapter of halmac + * @enable : function enable(1)/disable(0) + * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11) * Author : Soar Tu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_tx_agg_align_pcie_not_support_88xx( @@ -287,26 +306,5 @@ halmac_cfg_tx_agg_align_pcie_not_support_88xx( IN u16 align_size ) { - PHALMAC_API pHalmac_api; - VOID *pDriver_adapter = NULL; - - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; - - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) - return HALMAC_RET_API_INVALID; - - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_pcie_not_support_88xx ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_pcie_not_support_88xx not support\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_pcie_not_support_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; + return HALMAC_RET_NOT_SUPPORT; } - diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h b/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h index 434d9bd..0e471b1 100644 --- a/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h +++ b/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_API_88XX_PCIE_H_ #define _HALMAC_API_88XX_PCIE_H_ diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c b/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c index b5c9a8b..3d4e6c1 100644 --- a/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c +++ b/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c @@ -1,45 +1,68 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "halmac_88xx_cfg.h" /** - * halmac_init_sdio_cfg_88xx() - init SDIO related register - * @pHalmac_adapter + * halmac_init_sdio_cfg_88xx() - init SDIO + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_init_sdio_cfg_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ) { + u32 value32; VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_SDIO_CFG); + if (pHalmac_adapter->halmac_interface != HALMAC_INTERFACE_SDIO) + return HALMAC_RET_WRONG_INTF; pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_sdio_cfg_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_init_sdio_cfg_88xx ==========>\n"); HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_TX_CTRL, 0x00000000); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_sdio_cfg_88xx <==========\n"); + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_TX_CTRL); + value32 &= 0x0000FFFF; + value32 &= ~(BIT_CMD_ERR_STOP_INT_EN | BIT_EN_MASK_TIMER | BIT_EN_RXDMA_MASK_INT); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_TX_CTRL, value32); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_init_sdio_cfg_88xx <==========\n"); return HALMAC_RET_SUCCESS; } /** - * halmac_deinit_sdio_cfg_88xx() - deinit SDIO related register - * @pHalmac_adapter + * halmac_deinit_sdio_cfg_88xx() - deinit SDIO + * @pHalmac_adapter : the adapter of halmac * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_deinit_sdio_cfg_88xx( @@ -48,14 +71,12 @@ halmac_deinit_sdio_cfg_88xx( { VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEINIT_SDIO_CFG); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_sdio_cfg_88xx ==========>\n"); @@ -67,10 +88,11 @@ halmac_deinit_sdio_cfg_88xx( /** * halmac_cfg_rx_aggregation_88xx_sdio() - config rx aggregation - * @pHalmac_adapter + * @pHalmac_adapter : the adapter of halmac * @halmac_rx_agg_mode * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_rx_aggregation_88xx_sdio( @@ -78,25 +100,22 @@ halmac_cfg_rx_aggregation_88xx_sdio( IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg ) { - u8 value8, dma_usb_agg = 0; + u8 value8; u8 size = 0, timeout = 0, agg_enable = 0; VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_RX_AGGREGATION); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_sdio ==========>\n"); - dma_usb_agg = HALMAC_REG_READ_8(pHalmac_adapter, REG_RXDMA_AGG_PG_TH + 3); agg_enable = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP); switch (phalmac_rxagg_cfg->mode) { @@ -104,13 +123,8 @@ halmac_cfg_rx_aggregation_88xx_sdio( agg_enable &= ~(BIT_RXDMA_AGG_EN); break; case HALMAC_RX_AGG_MODE_DMA: - agg_enable |= BIT_RXDMA_AGG_EN; - dma_usb_agg |= BIT(7); - break; - case HALMAC_RX_AGG_MODE_USB: agg_enable |= BIT_RXDMA_AGG_EN; - dma_usb_agg &= ~(BIT(7)); break; default: PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_rx_aggregation_88xx_usb switch case not support\n"); @@ -118,7 +132,7 @@ halmac_cfg_rx_aggregation_88xx_sdio( break; } - if (_FALSE == phalmac_rxagg_cfg->threshold.drv_define) { + if (phalmac_rxagg_cfg->threshold.drv_define == _FALSE) { size = 0xFF; timeout = 0x01; } else { @@ -126,10 +140,8 @@ halmac_cfg_rx_aggregation_88xx_sdio( timeout = phalmac_rxagg_cfg->threshold.timeout; } - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP, agg_enable); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXDMA_AGG_PG_TH + 3, dma_usb_agg); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXDMA_AGG_PG_TH, (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO))); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXDMA_AGG_PG_TH, (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1))); value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RXDMA_MODE); if (0 != (agg_enable & BIT_RXDMA_AGG_EN)) @@ -144,10 +156,11 @@ halmac_cfg_rx_aggregation_88xx_sdio( /** * halmac_reg_read_8_sdio_88xx() - read 1byte register - * @pHalmac_adapter - * @halmac_offset + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ u8 halmac_reg_read_8_sdio_88xx( @@ -160,10 +173,10 @@ halmac_reg_read_8_sdio_88xx( PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -174,7 +187,7 @@ halmac_reg_read_8_sdio_88xx( status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_8_sdio_88xx error = %x\n", status); return status; } @@ -186,11 +199,12 @@ halmac_reg_read_8_sdio_88xx( /** * halmac_reg_write_8_sdio_88xx() - write 1byte register - * @pHalmac_adapter - * @halmac_offset - * @halmac_data + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_data : register value * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_reg_write_8_sdio_88xx( @@ -203,10 +217,10 @@ halmac_reg_write_8_sdio_88xx( PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -217,7 +231,7 @@ halmac_reg_write_8_sdio_88xx( status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_8_sdio_88xx error = %x\n", status); return status; } @@ -229,10 +243,11 @@ halmac_reg_write_8_sdio_88xx( /** * halmac_reg_read_16_sdio_88xx() - read 2byte register - * @pHalmac_adapter - * @halmac_offset + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ u16 halmac_reg_read_16_sdio_88xx( @@ -241,42 +256,48 @@ halmac_reg_read_16_sdio_88xx( ) { VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + u32 halmac_offset_old = 0; union { u16 word; u8 byte[2]; } value16 = { 0x0000 }; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + halmac_offset_old = halmac_offset; if (0 == (halmac_offset & 0xFFFF0000)) halmac_offset |= WLAN_IOREG_OFFSET; status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_16_sdio_88xx error = %x\n", status); return status; } - if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) { + if ((pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) || ((halmac_offset & (2 - 1)) != 0) || + (pHalmac_adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW) || (pHalmac_adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_R)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]use cmd52, offset = %x\n", halmac_offset); value16.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset); value16.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1); value16.word = rtk_le16_to_cpu(value16.word); } else { - if ((PLATFORM_SD_CLK > HALMAC_SD_CLK_THRESHOLD_88XX) && ((halmac_offset & 0xffffef00) == 0x00000000)) { - value16.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset); - value16.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1); - value16.word = rtk_le16_to_cpu(value16.word); + if (pHalmac_adapter->sdio_hw_info.io_hi_speed_flag != 0) { + if ((halmac_offset_old & 0xffffef00) == 0x00000000) { + value16.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset); + value16.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1); + value16.word = rtk_le16_to_cpu(value16.word); + } else { + value16.word = PLATFORM_SDIO_CMD53_READ_16(pDriver_adapter, halmac_offset); + } } else { value16.word = PLATFORM_SDIO_CMD53_READ_16(pDriver_adapter, halmac_offset); } @@ -287,11 +308,12 @@ halmac_reg_read_16_sdio_88xx( /** * halmac_reg_write_16_sdio_88xx() - write 2byte register - * @pHalmac_adapter - * @halmac_offset - * @halmac_data + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_data : register value * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_reg_write_16_sdio_88xx( @@ -301,29 +323,29 @@ halmac_reg_write_16_sdio_88xx( ) { VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; if (0 == (halmac_offset & 0xFFFF0000)) halmac_offset |= WLAN_IOREG_OFFSET; status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_16_sdio_88xx error = %x\n", status); return status; } - if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) { + if ((pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) || ((halmac_offset & (2 - 1)) != 0) || + (pHalmac_adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW) || (pHalmac_adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_W)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]use cmd52, offset = %x\n", halmac_offset); PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, (u8)(halmac_data & 0xFF)); PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 1, (u8)((halmac_data & 0xFF00) >> 8)); } else { @@ -335,10 +357,11 @@ halmac_reg_write_16_sdio_88xx( /** * halmac_reg_read_32_sdio_88xx() - read 4byte register - * @pHalmac_adapter - * @halmac_offset + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ u32 halmac_reg_read_32_sdio_88xx( @@ -346,51 +369,51 @@ halmac_reg_read_32_sdio_88xx( IN u32 halmac_offset ) { - u8 rtemp = 0xFF; - u32 counter = 1000; VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + u32 halmac_offset_old = 0; union { u32 dword; u8 byte[4]; } value32 = { 0x00000000 }; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + halmac_offset_old = halmac_offset; if (0 == (halmac_offset & 0xFFFF0000)) halmac_offset |= WLAN_IOREG_OFFSET; status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_32_sdio_88xx error = %x\n", status); return status; } - if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) { + if (pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF || (halmac_offset & (4 - 1)) != 0) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_WARN, "[WARN]use cmd52, offset = %x\n", halmac_offset); value32.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset); value32.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1); value32.byte[2] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 2); value32.byte[3] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 3); value32.dword = rtk_le32_to_cpu(value32.dword); } else { - if ((PLATFORM_SD_CLK > HALMAC_SD_CLK_THRESHOLD_88XX) && ((halmac_offset & 0xffffef00) == 0x00000000)) { - PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, REG_SDIO_INDIRECT_REG_CFG, halmac_offset | BIT(19) | BIT(17)); - - do { - rtemp = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, REG_SDIO_INDIRECT_REG_CFG + 2); - counter--; - } while (((rtemp & BIT(4)) != 0) && (counter > 0)); - - value32.dword = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, REG_SDIO_INDIRECT_REG_DATA); + if (pHalmac_adapter->sdio_hw_info.io_hi_speed_flag != 0) { + if ((halmac_offset_old & 0xffffef00) == 0x00000000) { + value32.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset); + value32.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1); + value32.byte[2] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 2); + value32.byte[3] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 3); + value32.dword = rtk_le32_to_cpu(value32.dword); + } else { + value32.dword = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset); + } } else { value32.dword = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset); } @@ -401,11 +424,12 @@ halmac_reg_read_32_sdio_88xx( /** * halmac_reg_write_32_sdio_88xx() - write 4byte register - * @pHalmac_adapter - * @halmac_offset - * @halmac_data + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_data : register value * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_reg_write_32_sdio_88xx( @@ -415,29 +439,27 @@ halmac_reg_write_32_sdio_88xx( ) { VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - if (0 == (halmac_offset & 0xFFFF0000)) + if ((halmac_offset & 0xFFFF0000) == 0) halmac_offset |= WLAN_IOREG_OFFSET; status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_32_sdio_88xx error = %x\n", status); return status; } - if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) { + if (pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF || (halmac_offset & (4 - 1)) != 0) { PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, (u8)(halmac_data & 0xFF)); PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 1, (u8)((halmac_data & 0xFF00) >> 8)); PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 2, (u8)((halmac_data & 0xFF0000) >> 16)); @@ -450,13 +472,64 @@ halmac_reg_write_32_sdio_88xx( } /** - * halmac_get_sdio_tx_addr_88xx() - get CMD53 addr for the TX packet - * @pHalmac_adapter - * @halmac_buf - * @halmac_size - * @pcmd53_addr + * halmac_reg_read_nbyte_sdio_88xx() - read n byte register + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_size : register value size + * @halmac_data : register value + * Author : Soar + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +u8 +halmac_reg_read_nbyte_sdio_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + IN u32 halmac_size, + OUT u8 *halmac_data +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + if (0 == (halmac_offset & 0xFFFF0000)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_offset error = 0x%x\n", halmac_offset); + return HALMAC_RET_FAIL; + } + + status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_nbyte_sdio_88xx error = %x\n", status); + return status; + } + + if (pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_state error = 0x%x\n", pHalmac_adapter->halmac_state.mac_power); + return HALMAC_RET_FAIL; + } + + PLATFORM_SDIO_CMD53_READ_N(pDriver_adapter, halmac_offset, halmac_size, halmac_data); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_get_sdio_tx_addr_sdio_88xx() - get CMD53 addr for the TX packet + * @pHalmac_adapter : the adapter of halmac + * @halmac_buf : tx packet, include txdesc + * @halmac_size : tx packet size + * @pcmd53_addr : cmd53 addr value * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_get_sdio_tx_addr_88xx( @@ -472,25 +545,23 @@ halmac_get_sdio_tx_addr_88xx( HALMAC_QUEUE_SELECT queue_sel; HALMAC_DMA_MAPPING dma_mapping; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_SDIO_TX_ADDR); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_sdio_tx_addr_88xx ==========>\n"); - if (NULL == halmac_buf) { + if (halmac_buf == NULL) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buf is NULL!!\n"); return HALMAC_RET_DATA_BUF_NULL; } - if (0 == halmac_size) { + if (halmac_size == 0) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_size is 0!!\n"); return HALMAC_RET_DATA_SIZE_INCORRECT; } @@ -555,12 +626,13 @@ halmac_get_sdio_tx_addr_88xx( } /** - * halmac_cfg_tx_agg_align_sdio_88xx() - - * @pHalmac_adapter - * @enable - * @align_size + * halmac_cfg_tx_agg_align_sdio_88xx() -config sdio bus tx agg alignment + * @pHalmac_adapter : the adapter of halmac + * @enable : function enable(1)/disable(0) + * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11) * Author : Soar Tu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_tx_agg_align_sdio_88xx( @@ -573,14 +645,12 @@ halmac_cfg_tx_agg_align_sdio_88xx( VOID *pDriver_adapter = NULL; u8 i, align_size_ok = 0; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -603,6 +673,9 @@ halmac_cfg_tx_agg_align_sdio_88xx( return HALMAC_RET_FAIL; } + /*Keep sdio tx agg alignment size for driver query*/ + pHalmac_adapter->hw_config_info.tx_align_size = align_size; + if (enable) HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RQPN_CTRL_2, 0x8000 | align_size); else @@ -613,14 +686,6 @@ halmac_cfg_tx_agg_align_sdio_88xx( return HALMAC_RET_SUCCESS; } -/** - * halmac_cfg_tx_agg_align_sdio_not_support_88xx() - - * @pHalmac_adapter - * @enable - * @align_size - * Author : Soar Tu - * Return : HALMAC_RET_STATUS - */ HALMAC_RET_STATUS halmac_cfg_tx_agg_align_sdio_not_support_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -631,14 +696,12 @@ halmac_cfg_tx_agg_align_sdio_not_support_88xx( PHALMAC_API pHalmac_api; VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -651,3 +714,267 @@ halmac_cfg_tx_agg_align_sdio_not_support_88xx( return HALMAC_RET_SUCCESS; } +/** + * halmac_tx_allowed_sdio_88xx() - check tx status + * @pHalmac_adapter : the adapter of halmac + * @pHalmac_buf : tx packet, include txdesc + * @halmac_size : tx packet size, include txdesc + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_tx_allowed_sdio_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHalmac_buf, + IN u32 halmac_size +) +{ + u8 *pCurr_packet; + u16 *pCurr_free_space; + u32 i, counter; + u32 tx_agg_num, packet_size = 0; + u32 tx_required_page_num, total_required_page_num = 0; + u8 macid_group[HALMAC_MACID_MAX_88XX + 1] = {0}, qsel; + u8 macid, macid_counter = 0; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + VOID *pDriver_adapter = NULL; + HALMAC_DMA_MAPPING dma_mapping; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_tx_allowed_sdio_88xx ==========>\n"); + + tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(pHalmac_buf); + pCurr_packet = pHalmac_buf; + + tx_agg_num = (tx_agg_num == 0) ? 1 : tx_agg_num; + + qsel = (u8)GET_TX_DESC_QSEL(pCurr_packet); + switch ((HALMAC_QUEUE_SELECT)qsel) { + case HALMAC_QUEUE_SELECT_VO: + case HALMAC_QUEUE_SELECT_VO_V2: + dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]; + break; + case HALMAC_QUEUE_SELECT_VI: + case HALMAC_QUEUE_SELECT_VI_V2: + dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]; + break; + case HALMAC_QUEUE_SELECT_BE: + case HALMAC_QUEUE_SELECT_BE_V2: + dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]; + break; + case HALMAC_QUEUE_SELECT_BK: + case HALMAC_QUEUE_SELECT_BK_V2: + dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]; + break; + case HALMAC_QUEUE_SELECT_MGNT: + dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]; + break; + case HALMAC_QUEUE_SELECT_HIGH: + dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]; + break; + case HALMAC_QUEUE_SELECT_BCN: + case HALMAC_QUEUE_SELECT_CMD: + return HALMAC_RET_SUCCESS; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "Qsel is out of range\n"); + return HALMAC_RET_QSEL_INCORRECT; + } + + switch (dma_mapping) { + case HALMAC_DMA_MAPPING_HIGH: + pCurr_free_space = &pHalmac_adapter->sdio_free_space.high_queue_number; + break; + case HALMAC_DMA_MAPPING_NORMAL: + pCurr_free_space = &pHalmac_adapter->sdio_free_space.normal_queue_number; + break; + case HALMAC_DMA_MAPPING_LOW: + pCurr_free_space = &pHalmac_adapter->sdio_free_space.low_queue_number; + break; + case HALMAC_DMA_MAPPING_EXTRA: + pCurr_free_space = &pHalmac_adapter->sdio_free_space.extra_queue_number; + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "DmaMapping is out of range\n"); + return HALMAC_RET_DMA_MAP_INCORRECT; + } + + for (i = 0; i < tx_agg_num; i++) { + /*MACID parser*/ + macid = (u8)GET_TX_DESC_MACID(pCurr_packet); + if (macid_group[macid] == 0) { + macid_group[macid] = 1; + macid_counter++; + } + /*QSEL parser*/ + if (qsel != GET_TX_DESC_QSEL(pCurr_packet)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "Multi-Qsel in a bus agg is not allowed, qsel = %d, %d\n", qsel, GET_TX_DESC_QSEL(pCurr_packet)); + return HALMAC_RET_QSEL_INCORRECT; + } + /*Page number parser*/ + packet_size = GET_TX_DESC_TXPKTSIZE(pCurr_packet) + GET_TX_DESC_OFFSET(pCurr_packet) + (GET_TX_DESC_PKT_OFFSET(pCurr_packet) << 3); + tx_required_page_num = (packet_size >> pHalmac_adapter->hw_config_info.page_size_2_power) + ((packet_size & (pHalmac_adapter->hw_config_info.page_size - 1)) ? 1 : 0); + total_required_page_num += tx_required_page_num; + + packet_size = HALMAC_ALIGN(packet_size, 8); + + pCurr_packet += packet_size; + } + + counter = 10; + do { + if ((u32)(*pCurr_free_space + pHalmac_adapter->sdio_free_space.public_queue_number) > total_required_page_num) { + status = halmac_check_oqt_88xx(pHalmac_adapter, tx_agg_num, pHalmac_buf, macid_counter); + + if (status != HALMAC_RET_SUCCESS) + return status; + + if (*pCurr_free_space >= total_required_page_num) { + *pCurr_free_space -= (u16)total_required_page_num; + } else { + pHalmac_adapter->sdio_free_space.public_queue_number -= (u16)(total_required_page_num - *pCurr_free_space); + *pCurr_free_space = 0; + } + + break; + } + + halmac_update_sdio_free_page_88xx(pHalmac_adapter); + + counter--; + if (counter == 0) + return HALMAC_RET_FREE_SPACE_NOT_ENOUGH; + } while (1); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_tx_allowed_sdio_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_reg_read_indirect_32_sdio_88xx() - read MAC reg by SDIO reg + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * Author : Soar + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +u32 +halmac_reg_read_indirect_32_sdio_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset +) +{ + u8 rtemp; + u32 counter = 1000; + VOID *pDriver_adapter = NULL; + + union { + u32 dword; + u8 byte[4]; + } value32 = { 0x00000000 }; + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | (REG_SDIO_INDIRECT_REG_CFG & HALMAC_SDIO_LOCAL_MSK), halmac_offset | BIT(19) | BIT(17)); + + do { + rtemp = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | ((REG_SDIO_INDIRECT_REG_CFG + 2) & HALMAC_SDIO_LOCAL_MSK)); + counter--; + } while (((rtemp & BIT(4)) != 0) && (counter > 0)); + + value32.dword = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | (REG_SDIO_INDIRECT_REG_DATA & HALMAC_SDIO_LOCAL_MSK)); + + return value32.dword; +} + + +/** + * halmac_sdio_cmd53_4byte_88xx() - cmd53 only for 4byte len register IO + * @pHalmac_adapter : the adapter of halmac + * @enable : 1->CMD53 only use in 4byte reg, 0 : No limitation + * Author : Ivan Lin/KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_sdio_cmd53_4byte_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_SDIO_CMD53_4BYTE_MODE cmd53_4byte_mode +) +{ + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + if (pHalmac_adapter->halmac_interface != HALMAC_INTERFACE_SDIO) + return HALMAC_RET_WRONG_INTF; + + pHalmac_adapter->sdio_cmd53_4byte = cmd53_4byte_mode; + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_sdio_hw_info_88xx() - info sdio hw info + * @pHalmac_adapter : the adapter of halmac + * @HALMAC_SDIO_CMD53_4BYTE_MODE : + * clock_speed : sdio bus clock. Unit -> MHz + * spec_ver : sdio spec version + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_sdio_hw_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_SDIO_HW_INFO pSdio_hw_info +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_sdio_hw_info_88xx ==========>\n"); + + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ADAPTER_INVALID; + + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_API_INVALID; + + if (pHalmac_adapter->halmac_interface != HALMAC_INTERFACE_SDIO) + return HALMAC_RET_WRONG_INTF; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]SDIO hw clock : %d, spec : %d\n", pSdio_hw_info->clock_speed, pSdio_hw_info->spec_ver); + + if (pSdio_hw_info->clock_speed > HALMAC_SDIO_CLOCK_SPEED_MAX_88XX) + return HALMAC_RET_SDIO_CLOCK_ERR; + + if (pSdio_hw_info->clock_speed > HALMAC_SDIO_CLK_THRESHOLD_88XX) + pHalmac_adapter->sdio_hw_info.io_hi_speed_flag = 1; + + pHalmac_adapter->sdio_hw_info.clock_speed = pSdio_hw_info->clock_speed; + pHalmac_adapter->sdio_hw_info.spec_ver = pSdio_hw_info->spec_ver; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_sdio_hw_info_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h b/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h index dbb4a0e..06885a8 100644 --- a/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h +++ b/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_API_88XX_SDIO_H_ #define _HALMAC_API_88XX_SDIO_H_ @@ -81,4 +96,38 @@ halmac_cfg_tx_agg_align_sdio_not_support_88xx( IN u16 align_size ); +HALMAC_RET_STATUS +halmac_tx_allowed_sdio_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHalmac_buf, + IN u32 halmac_size +); + +u32 +halmac_reg_read_indirect_32_sdio_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset +); + + +HALMAC_RET_STATUS +halmac_sdio_cmd53_4byte_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_SDIO_CMD53_4BYTE_MODE cmd53_4byte_mode +); + +u8 +halmac_reg_read_nbyte_sdio_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + IN u32 halmac_size, + OUT u8 *halmac_data +); + +HALMAC_RET_STATUS +halmac_sdio_hw_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_SDIO_HW_INFO pSdio_hw_info +); + #endif/* _HALMAC_API_88XX_SDIO_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c b/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c index f4a8919..5b70718 100644 --- a/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c +++ b/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c @@ -1,10 +1,26 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "halmac_88xx_cfg.h" /** - * halmac_init_usb_cfg_88xx() - init USB related register - * @pHalmac_adapter - * Author : KaiYuan Chang + * halmac_init_usb_cfg_88xx() - init USB + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_init_usb_cfg_88xx( @@ -14,26 +30,24 @@ halmac_init_usb_cfg_88xx( VOID *pDriver_adapter = NULL; u8 value8 = 0; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_USB_CFG); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_usb_cfg_88xx ==========>\n"); - value8 |= (BIT_DMA_MODE | (0x3 << BIT_SHIFT_BURST_CNT)); /* burst number = 4 */ + value8 |= (BIT_DMA_MODE | (0x3 << BIT_SHIFT_BURST_CNT)); /* burst number = 4 */ - if (PLATFORM_REG_READ_8(pDriver_adapter, REG_SYS_CFG2 + 3) == 0x20) { /* usb3.0 */ + if (PLATFORM_REG_READ_8(pDriver_adapter, REG_SYS_CFG2 + 3) == 0x20) { /* usb3.0 */ value8 |= (HALMAC_USB_BURST_SIZE_3_0 << BIT_SHIFT_BURST_SIZE); } else { - if ((PLATFORM_REG_READ_8(pDriver_adapter, REG_USB_USBSTAT) & 0x3) == 0x1) /* usb2.0 */ + if ((PLATFORM_REG_READ_8(pDriver_adapter, REG_USB_USBSTAT) & 0x3) == 0x1) /* usb2.0 */ value8 |= HALMAC_USB_BURST_SIZE_2_0_HSPEED << BIT_SHIFT_BURST_SIZE; - else /* usb1.1 */ + else /* usb1.1 */ value8 |= HALMAC_USB_BURST_SIZE_2_0_FSPEED << BIT_SHIFT_BURST_SIZE; } @@ -46,10 +60,11 @@ halmac_init_usb_cfg_88xx( } /** - * halmac_deinit_usb_cfg_88xx() - init USB related register - * @pHalmac_adapter - * Author : KaiYuan Chang + * halmac_deinit_usb_cfg_88xx() - deinit USB + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_deinit_usb_cfg_88xx( @@ -58,14 +73,12 @@ halmac_deinit_usb_cfg_88xx( { VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEINIT_USB_CFG); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_usb_cfg_88xx ==========>\n"); @@ -76,11 +89,12 @@ halmac_deinit_usb_cfg_88xx( } /** - * halmac_cfg_rx_aggregation_88xx_usb() - config rx aggregation - * @pHalmac_adapter + * halmac_cfg_rx_aggregation_88xx_usb() - config rx aggregation + * @pHalmac_adapter : the adapter of halmac * @halmac_rx_agg_mode - * Author : KaiYuan Chang + * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_rx_aggregation_88xx_usb( @@ -93,14 +107,12 @@ halmac_cfg_rx_aggregation_88xx_usb( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_RX_AGGREGATION); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -128,7 +140,7 @@ halmac_cfg_rx_aggregation_88xx_usb( break; } - if (_FALSE == phalmac_rxagg_cfg->threshold.drv_define) { + if (phalmac_rxagg_cfg->threshold.drv_define == _FALSE) { if (PLATFORM_REG_READ_8(pDriver_adapter, REG_SYS_CFG2 + 3) == 0x20) { /* usb3.0 */ size = 0x5; @@ -145,7 +157,7 @@ halmac_cfg_rx_aggregation_88xx_usb( HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP, agg_enable); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXDMA_AGG_PG_TH + 3, dma_usb_agg); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXDMA_AGG_PG_TH, (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO))); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXDMA_AGG_PG_TH, (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1))); PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_usb <==========\n"); @@ -154,10 +166,11 @@ halmac_cfg_rx_aggregation_88xx_usb( /** * halmac_reg_read_8_usb_88xx() - read 1byte register - * @pHalmac_adapter - * @halmac_offset - * Author : KaiYuan Chang + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ u8 halmac_reg_read_8_usb_88xx( @@ -169,10 +182,10 @@ halmac_reg_read_8_usb_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -189,11 +202,12 @@ halmac_reg_read_8_usb_88xx( /** * halmac_reg_write_8_usb_88xx() - write 1byte register - * @pHalmac_adapter - * @halmac_offset - * @halmac_data - * Author : KaiYuan Chang + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_data : register value + * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_reg_write_8_usb_88xx( @@ -205,10 +219,10 @@ halmac_reg_write_8_usb_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -226,10 +240,11 @@ halmac_reg_write_8_usb_88xx( /** * halmac_reg_read_16_usb_88xx() - read 2byte register - * @pHalmac_adapter - * @halmac_offset - * Author : KaiYuan Chang + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ u16 halmac_reg_read_16_usb_88xx( @@ -245,10 +260,10 @@ halmac_reg_read_16_usb_88xx( u8 byte[2]; } value16 = { 0x0000 }; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -265,11 +280,12 @@ halmac_reg_read_16_usb_88xx( /** * halmac_reg_write_16_usb_88xx() - write 2byte register - * @pHalmac_adapter - * @halmac_offset - * @halmac_data - * Author : KaiYuan Chang + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_data : register value + * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_reg_write_16_usb_88xx( @@ -281,10 +297,10 @@ halmac_reg_write_16_usb_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -301,10 +317,11 @@ halmac_reg_write_16_usb_88xx( /** * halmac_reg_read_32_usb_88xx() - read 4byte register - * @pHalmac_adapter - * @halmac_offset - * Author : KaiYuan Chang + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ u32 halmac_reg_read_32_usb_88xx( @@ -320,10 +337,10 @@ halmac_reg_read_32_usb_88xx( u8 byte[4]; } value32 = { 0x00000000 }; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -340,11 +357,12 @@ halmac_reg_read_32_usb_88xx( /** * halmac_reg_write_32_usb_88xx() - write 4byte register - * @pHalmac_adapter - * @halmac_offset - * @halmac_data - * Author : KaiYuan Chang + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_data : register value + * Author : KaiYuan Chang/Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_reg_write_32_usb_88xx( @@ -356,10 +374,10 @@ halmac_reg_write_32_usb_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; @@ -375,11 +393,12 @@ halmac_reg_write_32_usb_88xx( } /** - * halmac_set_bulkout_num_88xx() - set bulk out endpoint number - * @pHalmac_adapter - * @bulkout_num + * halmac_set_bulkout_num_usb_88xx() - inform bulk-out num + * @pHalmac_adapter : the adapter of halmac + * @bulkout_num : usb bulk-out number * Author : KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_set_bulkout_num_88xx( @@ -390,14 +409,12 @@ halmac_set_bulkout_num_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SET_BULKOUT_NUM); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; @@ -412,13 +429,14 @@ halmac_set_bulkout_num_88xx( } /** - * halmac_get_usb_bulkout_id_88xx() - get bulk out id for the TX packet - * @pHalmac_adapter - * @halmac_buf - * @halmac_size - * @bulkout_id + * halmac_get_usb_bulkout_id_usb_88xx() - get bulk out id for the TX packet + * @pHalmac_adapter : the adapter of halmac + * @halmac_buf : tx packet, include txdesc + * @halmac_size : tx packet size + * @bulkout_id : usb bulk-out id * Author : KaiYuan Chang * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_get_usb_bulkout_id_88xx( @@ -433,25 +451,23 @@ halmac_get_usb_bulkout_id_88xx( HALMAC_QUEUE_SELECT queue_sel; HALMAC_DMA_MAPPING dma_mapping; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_USB_BULKOUT_ID); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_usb_bulkout_id_88xx ==========>\n"); - if (NULL == halmac_buf) { + if (halmac_buf == NULL) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buf is NULL!!\n"); return HALMAC_RET_DATA_BUF_NULL; } - if (0 == halmac_size) { + if (halmac_size == 0) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_size is 0!!\n"); return HALMAC_RET_DATA_SIZE_INCORRECT; } @@ -512,12 +528,13 @@ halmac_get_usb_bulkout_id_88xx( } /** - * halmac_cfg_tx_agg_align_usb_not_support_88xx() - - * @pHalmac_adapter - * @enable - * @align_size + * halmac_cfg_tx_agg_align_usb_88xx() -config sdio bus tx agg alignment + * @pHalmac_adapter : the adapter of halmac + * @enable : function enable(1)/disable(0) + * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11) * Author : Soar Tu * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_cfg_tx_agg_align_usb_not_support_88xx( @@ -529,14 +546,12 @@ halmac_cfg_tx_agg_align_usb_not_support_88xx( PHALMAC_API pHalmac_api; VOID *pDriver_adapter = NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; - if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_API_INVALID; - halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h b/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h index c3e9cf9..36702c4 100644 --- a/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h +++ b/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_API_88XX_USB_H_ #define _HALMAC_API_88XX_USB_H_ diff --git a/hal/halmac/halmac_88xx/halmac_func_88xx.c b/hal/halmac/halmac_88xx/halmac_func_88xx.c index 612cd2c..55a6b07 100644 --- a/hal/halmac/halmac_88xx/halmac_func_88xx.c +++ b/hal/halmac/halmac_88xx/halmac_func_88xx.c @@ -1,58 +1,82 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "halmac_88xx_cfg.h" -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_dump_efuse_fw_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_dump_efuse_drv_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_update_eeprom_mask_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, INOUT PHALMAC_PG_EFUSE_INFO pPg_efuse_info, OUT u8 *pEeprom_mask_updated ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_check_efuse_enough_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, IN u8 *pEeprom_mask_updated ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_program_efuse_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, IN u8 *pEeprom_mask_updated ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS +halmac_pwr_sub_seq_parer_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 cut, + IN u8 fab, + IN u8 intf, + IN PHALMAC_WLAN_PWR_CFG pPwr_sub_seq_cfg +); + +static HALMAC_RET_STATUS halmac_parse_c2h_debug_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, IN u32 c2h_size ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_scan_status_rpt_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, IN u32 c2h_size ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_psd_data_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, IN u32 c2h_size ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_efuse_data_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -60,21 +84,14 @@ halmac_parse_efuse_data_88xx( ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, IN u32 c2h_size ); -HALMAC_RET_STATUS -halmac_parse_h2c_ack_physical_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_enqueue_para_buff_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN PHALMAC_PHY_PARAMETER_INFO para_info, @@ -82,89 +99,134 @@ halmac_enqueue_para_buff_88xx( OUT u8 *pEnd_cmd ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS +halmac_parse_h2c_ack_phy_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +static HALMAC_RET_STATUS halmac_parse_h2c_ack_cfg_para_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, IN u32 c2h_size ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_gen_cfg_para_h2c_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pH2c_buff ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_update_packet_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, IN u32 c2h_size ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_update_datapack_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, IN u32 c2h_size ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_run_datapack_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, IN u32 c2h_size ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_channel_switch_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, IN u32 c2h_size ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_iqk_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, IN u32 c2h_size ); -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_power_tracking_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, IN u32 c2h_size ); +VOID +halmac_init_offload_feature_state_machine_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + PHALMAC_STATE pState = &pHalmac_adapter->halmac_state; + + pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE; + pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->efuse_state_set.seq_num = pHalmac_adapter->h2c_packet_seq; + + pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE; + pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->cfg_para_state_set.seq_num = pHalmac_adapter->h2c_packet_seq; + + pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE; + pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->scan_state_set.seq_num = pHalmac_adapter->h2c_packet_seq; + + pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->update_packet_set.seq_num = pHalmac_adapter->h2c_packet_seq; + + pState->iqk_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->iqk_set.seq_num = pHalmac_adapter->h2c_packet_seq; + + pState->power_tracking_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->power_tracking_set.seq_num = pHalmac_adapter->h2c_packet_seq; + + pState->psd_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->psd_set.seq_num = pHalmac_adapter->h2c_packet_seq; + pState->psd_set.data_size = 0; + pState->psd_set.segment_size = 0; + pState->psd_set.pData = NULL; +} + HALMAC_RET_STATUS halmac_dump_efuse_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN HALMAC_EFUSE_READ_CFG cfg ) { + u32 chk_h2c_init; VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; pDriver_adapter = pHalmac_adapter->pDriver_adapter; *pProcess_status = HALMAC_CMD_PROCESS_SENDING; - if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT)) + if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; - if (HALMAC_EFUSE_R_AUTO == cfg) { - if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state) + if (cfg == HALMAC_EFUSE_R_AUTO) { + chk_h2c_init = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_PKT_READADDR); + if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state || 0 == chk_h2c_init) status = halmac_dump_efuse_drv_88xx(pHalmac_adapter); else status = halmac_dump_efuse_fw_88xx(pHalmac_adapter); - } else if (HALMAC_EFUSE_R_FW == cfg) { + } else if (cfg == HALMAC_EFUSE_R_FW) { status = halmac_dump_efuse_fw_88xx(pHalmac_adapter); } else { status = halmac_dump_efuse_drv_88xx(pHalmac_adapter); } - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_efuse error = %x\n", status); return status; } @@ -184,16 +246,16 @@ halmac_func_read_efuse_88xx( pDriver_adapter = pHalmac_adapter->pDriver_adapter; - if (NULL == pEfuse_map) { + if (pEfuse_map == NULL) { PLATFORM_MSG_PRINT(pHalmac_adapter->pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Malloc for dump efuse map error\n"); return HALMAC_RET_NULL_POINTER; } - if (_TRUE == pHalmac_adapter->hal_efuse_map_valid) + if (pHalmac_adapter->hal_efuse_map_valid == _TRUE) PLATFORM_RTL_MEMCPY(pDriver_adapter, pEfuse_map, pHalmac_adapter->pHalEfuse_map + offset, size); else - if (HALMAC_RET_SUCCESS != halmac_read_hw_efuse_88xx(pHalmac_adapter, offset, size, pEfuse_map)) - return HALMAC_RET_EFUSE_R_FAIL; + if (halmac_read_hw_efuse_88xx(pHalmac_adapter, offset, size, pEfuse_map) != HALMAC_RET_SUCCESS) + return HALMAC_RET_EFUSE_R_FAIL; return HALMAC_RET_SUCCESS; } @@ -228,15 +290,16 @@ halmac_read_hw_efuse_88xx( value32 = value32 | ((address & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR); HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EFUSE_CTRL, value32 & (~BIT_EF_FLAG)); - counter = 100; + counter = 1000000; do { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 1); tmp32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL); counter--; - if (0 == counter) { + if (counter == 0) { PLATFORM_MSG_PRINT(pHalmac_adapter->pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "HALMAC_RET_EFUSE_R_FAIL\n"); return HALMAC_RET_EFUSE_R_FAIL; } - } while (0 == (tmp32 & BIT_EF_FLAG)); + } while ((tmp32 & BIT_EF_FLAG) == 0); *(pEfuse_map + address - offset) = (u8)(tmp32 & BIT_MASK_EF_DATA); } @@ -244,7 +307,7 @@ halmac_read_hw_efuse_88xx( return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_dump_efuse_drv_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ) @@ -257,34 +320,38 @@ halmac_dump_efuse_drv_88xx( efuse_size = pHalmac_adapter->hw_config_info.efuse_size; - if (NULL == pHalmac_adapter->pHalEfuse_map) { + if (pHalmac_adapter->pHalEfuse_map == NULL) { pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); - if (NULL == pHalmac_adapter->pHalEfuse_map) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate efuse map Fail!!\n"); + if (pHalmac_adapter->pHalEfuse_map == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate efuse map Fail!!\n"); return HALMAC_RET_MALLOC_FAIL; } } - pEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); - if (NULL == pEfuse_map) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local efuse map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } + if (pHalmac_adapter->hal_efuse_map_valid == _FALSE) { + pEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); + if (pEfuse_map == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local efuse map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } - if (HALMAC_RET_SUCCESS != halmac_read_hw_efuse_88xx(pHalmac_adapter, 0, efuse_size, pEfuse_map)) - return HALMAC_RET_EFUSE_R_FAIL; + if (halmac_read_hw_efuse_88xx(pHalmac_adapter, 0, efuse_size, pEfuse_map) != HALMAC_RET_SUCCESS) { + PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); + return HALMAC_RET_EFUSE_R_FAIL; + } - PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); - PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pEfuse_map, efuse_size); - pHalmac_adapter->hal_efuse_map_valid = _TRUE; - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); + PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pEfuse_map, efuse_size); + pHalmac_adapter->hal_efuse_map_valid = _TRUE; + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); + PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); + } return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_dump_efuse_fw_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ) @@ -304,18 +371,19 @@ halmac_dump_efuse_fw_88xx( halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); pHalmac_adapter->halmac_state.efuse_state_set.seq_num = h2c_seq_mum; - if (NULL == pHalmac_adapter->pHalEfuse_map) { + if (pHalmac_adapter->pHalEfuse_map == NULL) { pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pHalmac_adapter->hw_config_info.efuse_size); - if (NULL == pHalmac_adapter->pHalEfuse_map) { + if (pHalmac_adapter->pHalEfuse_map == NULL) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac allocate efuse map Fail!!\n"); return HALMAC_RET_MALLOC_FAIL; } } - if (_FALSE == pHalmac_adapter->hal_efuse_map_valid) { + if (pHalmac_adapter->hal_efuse_map_valid == _FALSE) { status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_read_efuse_fw Fail = %x!!\n", status); + halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE); return status; } } @@ -334,13 +402,14 @@ halmac_func_write_efuse_88xx( u32 value32, tmp32, counter; VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; + u8 value_read = 0; pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); pHalmac_adapter->hal_efuse_map_valid = _FALSE; - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PMC_DBG_CTRL2 + 3, wite_protect_code); @@ -352,21 +421,31 @@ halmac_func_write_efuse_88xx( value32 = value32 | ((offset & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) | (value & BIT_MASK_EF_DATA); HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EFUSE_CTRL, value32 | BIT_EF_FLAG); - counter = 100; + counter = 1000000; do { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 1); tmp32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL); counter--; - if (0 == counter) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_write_efuse Fail !!\n"); + if (counter == 0) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_write_efuse Fail !!\n"); return HALMAC_RET_EFUSE_W_FAIL; } - } while (BIT_EF_FLAG == (tmp32 & BIT_EF_FLAG)); + } while ((tmp32 & BIT_EF_FLAG) == BIT_EF_FLAG); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PMC_DBG_CTRL2 + 3, 0x00); /* Disable 2.5V LDO */ HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3) & ~(BIT(7)))); + if (pHalmac_adapter->efuse_auto_check_en == 1) { + if (halmac_read_hw_efuse_88xx(pHalmac_adapter, offset, 1, &value_read) != HALMAC_RET_SUCCESS) + return HALMAC_RET_EFUSE_R_FAIL; + if (value_read != value) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_write_efuse Fail: result 0x%X != write value 0x%X !!\n", value_read, value); + return HALMAC_RET_EFUSE_W_FAIL; + } + } + return HALMAC_RET_SUCCESS; } @@ -384,7 +463,7 @@ halmac_func_switch_efuse_bank_88xx( pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_BUSY)) + if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_BUSY) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; reg_value = HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1); @@ -423,7 +502,7 @@ halmac_eeprom_parser_88xx( PLATFORM_RTL_MEMSET(pDriver_adapter, pLogical_efuse_map, 0xFF, eeprom_size); - while (1) { + do { value8 = *(pPhysical_efuse_map + efuse_index); efuse_read_header = value8; @@ -443,7 +522,7 @@ halmac_eeprom_parser_88xx( efuse_index++; - if (efuse_index >= pHalmac_adapter->hw_config_info.efuse_size - HALMAC_RESERVED_EFUSE_SIZE_88XX - 1) + if (efuse_index >= pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - 1) return HALMAC_RET_EEPROM_PARSING_FAIL; for (j = 0; j < 4; j++) { @@ -457,31 +536,29 @@ halmac_eeprom_parser_88xx( PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM header: 0x%X, 0x%X,\n", efuse_read_header, efuse_read_header2); else PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM header: 0x%X,\n", efuse_read_header); - eeprom_index++; - efuse_index = efuse_index + 2; return HALMAC_RET_EEPROM_PARSING_FAIL; - } else { - value8 = *(pPhysical_efuse_map + efuse_index); - *(pLogical_efuse_map + eeprom_index) = value8; + } - eeprom_index++; - efuse_index++; + value8 = *(pPhysical_efuse_map + efuse_index); + *(pLogical_efuse_map + eeprom_index) = value8; - if (efuse_index > pHalmac_adapter->hw_config_info.efuse_size - HALMAC_RESERVED_EFUSE_SIZE_88XX - 1) - return HALMAC_RET_EEPROM_PARSING_FAIL; + eeprom_index++; + efuse_index++; - value8 = *(pPhysical_efuse_map + efuse_index); - *(pLogical_efuse_map + eeprom_index) = value8; + if (efuse_index > pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - 1) + return HALMAC_RET_EEPROM_PARSING_FAIL; - efuse_index++; + value8 = *(pPhysical_efuse_map + efuse_index); + *(pLogical_efuse_map + eeprom_index) = value8; - if (efuse_index > pHalmac_adapter->hw_config_info.efuse_size - HALMAC_RESERVED_EFUSE_SIZE_88XX) - return HALMAC_RET_EEPROM_PARSING_FAIL; - } + efuse_index++; + + if (efuse_index > pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX) + return HALMAC_RET_EEPROM_PARSING_FAIL; } } - } + } while (1); pHalmac_adapter->efuse_end = efuse_index; @@ -502,36 +579,38 @@ halmac_read_logical_efuse_map_88xx( pDriver_adapter = pHalmac_adapter->pDriver_adapter; efuse_size = pHalmac_adapter->hw_config_info.efuse_size; - if (_FALSE == pHalmac_adapter->hal_efuse_map_valid) { + if (pHalmac_adapter->hal_efuse_map_valid == _FALSE) { pEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); - if (NULL == pEfuse_map) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local efuse map Fail!!\n"); + if (pEfuse_map == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local efuse map Fail!!\n"); return HALMAC_RET_MALLOC_FAIL; } - if (NULL == pHalmac_adapter->pHalEfuse_map) { + status = halmac_func_read_efuse_88xx(pHalmac_adapter, 0, efuse_size, pEfuse_map); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_read_efuse error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); + return status; + } + + if (pHalmac_adapter->pHalEfuse_map == NULL) { pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); - if (NULL == pHalmac_adapter->pHalEfuse_map) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate efuse map Fail!!\n"); + if (pHalmac_adapter->pHalEfuse_map == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate efuse map Fail!!\n"); + PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); return HALMAC_RET_MALLOC_FAIL; } } - status = halmac_func_read_efuse_88xx(pHalmac_adapter, 0, efuse_size, pEfuse_map); - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_efuse error = %x\n", status); - return status; - } - - PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pEfuse_map, efuse_size); pHalmac_adapter->hal_efuse_map_valid = _TRUE; - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); } - if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pMap)) + if (halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pMap) != HALMAC_RET_SUCCESS) return HALMAC_RET_EEPROM_PARSING_FAIL; return status; @@ -549,22 +628,23 @@ halmac_func_write_logical_efuse_88xx( u8 pg_efuse_header, pg_efuse_header2; u8 *pEeprom_map = NULL; u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; - u32 efuse_end; + u32 efuse_end, pg_efuse_num; VOID *pDriver_adapter = NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; pDriver_adapter = pHalmac_adapter->pDriver_adapter; pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); - if (NULL == pEeprom_map) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n"); + if (pEeprom_map == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); return HALMAC_RET_MALLOC_FAIL; } PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map); - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_logical_efuse_map_88xx error = %x\n", status); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_read_logical_efuse_map_88xx error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); return status; } @@ -589,18 +669,29 @@ halmac_func_write_logical_efuse_88xx( } if (offset > 0x7f) { - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_header2); - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 2, pg_efuse_byte1); + pg_efuse_num = 4; + if (pHalmac_adapter->hw_config_info.efuse_size <= (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX + pHalmac_adapter->efuse_end)) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return HALMAC_RET_EFUSE_NOT_ENOUGH; + } + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_header2); + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 2, pg_efuse_byte1); status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 3, pg_efuse_byte2); } else { - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_byte1); + pg_efuse_num = 3; + if (pHalmac_adapter->hw_config_info.efuse_size <= (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX + pHalmac_adapter->efuse_end)) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return HALMAC_RET_EFUSE_NOT_ENOUGH; + } + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_byte1); status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 2, pg_efuse_byte2); } - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_write_logical_efuse error = %x\n", status); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_write_logical_efuse error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); return status; } } @@ -623,30 +714,33 @@ halmac_func_pg_efuse_by_map_88xx( HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; pEeprom_mask_updated = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_mask_size); - if (NULL == pEeprom_mask_updated) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n"); + if (pEeprom_mask_updated == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); return HALMAC_RET_MALLOC_FAIL; } PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_mask_updated, 0x00, eeprom_mask_size); status = halmac_update_eeprom_mask_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated); - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_update_eeprom_mask_88xx error = %x\n", status); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_update_eeprom_mask_88xx error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size); return status; } status = halmac_check_efuse_enough_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated); - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_check_efuse_enough_88xx error = %x\n", status); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_check_efuse_enough_88xx error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size); return status; } status = halmac_program_efuse_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated); - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_program_efuse_88xx error = %x\n", status); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_program_efuse_88xx error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size); return status; } @@ -655,7 +749,7 @@ halmac_func_pg_efuse_by_map_88xx( return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_update_eeprom_mask_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, INOUT PHALMAC_PG_EFUSE_INFO pPg_efuse_info, @@ -674,8 +768,8 @@ halmac_update_eeprom_mask_88xx( pDriver_adapter = pHalmac_adapter->pDriver_adapter; pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); - if (NULL == pEeprom_map) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n"); + if (pEeprom_map == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); return HALMAC_RET_MALLOC_FAIL; } PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); @@ -684,8 +778,10 @@ halmac_update_eeprom_mask_88xx( status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map); - if (HALMAC_RET_SUCCESS != status) + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); return status; + } pEeprom_map_pg = pPg_efuse_info->pEfuse_map; pEeprom_mask = pPg_efuse_info->pEfuse_mask; @@ -738,7 +834,7 @@ halmac_update_eeprom_mask_88xx( return status; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_check_efuse_enough_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, @@ -800,13 +896,13 @@ halmac_check_efuse_enough_88xx( } } - if ((pHalmac_adapter->hw_config_info.efuse_size - pg_efuse_num - HALMAC_RESERVED_EFUSE_SIZE_88XX - pHalmac_adapter->efuse_end) <= 0) + if (pHalmac_adapter->hw_config_info.efuse_size <= (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX + pHalmac_adapter->efuse_end)) return HALMAC_RET_EFUSE_NOT_ENOUGH; return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_program_efuse_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, @@ -845,12 +941,12 @@ halmac_program_efuse_88xx( } if (tmp_eeprom_offset > 0x7f) { - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_header2); efuse_end = efuse_end + 2; for (j = 0; j < 4; j++) { if (((pre_word_enb >> j) & 0x1) > 0) { - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1))); + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1))); status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1) + 1)); efuse_end = efuse_end + 2; } @@ -860,7 +956,7 @@ halmac_program_efuse_88xx( efuse_end = efuse_end + 1; for (j = 0; j < 4; j++) { if (((pre_word_enb >> j) & 0x1) > 0) { - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1))); + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1))); status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1) + 1)); efuse_end = efuse_end + 2; } @@ -872,6 +968,39 @@ halmac_program_efuse_88xx( return status; } +HALMAC_RET_STATUS +halmac_update_fw_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHamacl_fw, + IN u32 halmac_fw_size +) +{ + PHALMAC_FW_VERSION pFw_info = &pHalmac_adapter->fw_version; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + pFw_info->version = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_VERSION_88XX))); + pFw_info->sub_version = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_SUBVERSION_88XX); + pFw_info->sub_index = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_SUBINDEX_88XX); + pFw_info->h2c_version = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX))); + pFw_info->build_time.month = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_MONTH_88XX); + pFw_info->build_time.date = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_DATE_88XX); + pFw_info->build_time.hour = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_HOUR_88XX); + pFw_info->build_time.min = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_MIN_88XX); + pFw_info->build_time.year = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_YEAR_88XX))); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "[TRACE]FW version : %X\n", pFw_info->version); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "[TRACE]FW sub version : %X\n", pFw_info->sub_version); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "[TRACE]FW sub index : %X\n", pFw_info->sub_index); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "[TRACE]FW build time : %d/%d/%d %d:%d\n", + pFw_info->build_time.year, pFw_info->build_time.month, + pFw_info->build_time.date, pFw_info->build_time.hour, + pFw_info->build_time.min); + + return HALMAC_RET_SUCCESS; +} + HALMAC_RET_STATUS halmac_dlfw_to_mem_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -897,19 +1026,19 @@ halmac_dlfw_to_mem_88xx( HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0CTRL, HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) | BIT_DDMACH0_RESET_CHKSUM_STS); - while (0 != pkt_size_tmp) { + while (pkt_size_tmp != 0) { if (pkt_size_tmp >= pHalmac_adapter->max_download_size) send_pkt_size = pHalmac_adapter->max_download_size; else send_pkt_size = pkt_size_tmp; - if (HALMAC_RET_SUCCESS != halmac_send_fwpkt_88xx(pHalmac_adapter, pCode_ptr + mem_offset, send_pkt_size)) { + if (halmac_send_fwpkt_88xx(pHalmac_adapter, pCode_ptr + mem_offset, send_pkt_size) != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_send_fwpkt_88xx fail!!"); return HALMAC_RET_DLFW_FAIL; } - if (HALMAC_RET_SUCCESS != halmac_iddma_dlfw_88xx(pHalmac_adapter, HALMAC_OCPBASE_TXBUF_88XX + pHalmac_adapter->hw_config_info.txdesc_size, - dest + mem_offset, send_pkt_size, first_part)) { + if (halmac_iddma_dlfw_88xx(pHalmac_adapter, HALMAC_OCPBASE_TXBUF_88XX + pHalmac_adapter->hw_config_info.txdesc_size, + dest + mem_offset, send_pkt_size, first_part) != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx fail!!"); return HALMAC_RET_DLFW_FAIL; } @@ -919,7 +1048,7 @@ halmac_dlfw_to_mem_88xx( pkt_size_tmp -= send_pkt_size; } - if (HALMAC_RET_SUCCESS != halmac_check_fw_chksum_88xx(pHalmac_adapter, dest)) { + if (halmac_check_fw_chksum_88xx(pHalmac_adapter, dest) != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pHalmac_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_check_fw_chksum_88xx fail!!"); return HALMAC_RET_DLFW_FAIL; } @@ -936,7 +1065,7 @@ halmac_send_fwpkt_88xx( { VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - if (HALMAC_RET_SUCCESS != halmac_download_rsvd_page_88xx(pHalmac_adapter, pRam_code, code_size)) { + if (halmac_download_rsvd_page_88xx(pHalmac_adapter, pRam_code, code_size) != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "PLATFORM_SEND_RSVD_PAGE 0 error!!\n"); return HALMAC_RET_DL_RSVD_PAGE_FAIL; } @@ -964,14 +1093,14 @@ halmac_iddma_dlfw_88xx( counter = HALMC_DDMA_POLLING_COUNT; while (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { counter--; - if (0 == counter) { + if (counter == 0) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx error-1!!\n"); return HALMAC_RET_DDMA_FAIL; } } ch0_control |= (length & BIT_MASK_DDMACH0_DLEN); - if (0 == first) + if (first == 0) ch0_control |= BIT_DDMACH0_CHKSUM_CONT; HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0SA, source); @@ -981,7 +1110,7 @@ halmac_iddma_dlfw_88xx( counter = HALMC_DDMA_POLLING_COUNT; while (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { counter--; - if (0 == counter) { + if (counter == 0) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx error-2!!\n"); return HALMAC_RET_DDMA_FAIL; } @@ -1017,17 +1146,17 @@ halmac_check_fw_chksum_88xx( PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_check_fw_chksum_88xx error!!\n"); return HALMAC_RET_FW_CHECKSUM_FAIL; - } else { - if (memory_address < HALMAC_OCPBASE_DMEM_88XX) { - mcu_fw_ctrl |= BIT_IMEM_DW_OK; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl | BIT_IMEM_CHKSUM_OK)); - } else { - mcu_fw_ctrl |= BIT_DMEM_DW_OK; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl | BIT_DMEM_CHKSUM_OK)); - } + } - return HALMAC_RET_SUCCESS; + if (memory_address < HALMAC_OCPBASE_DMEM_88XX) { + mcu_fw_ctrl |= BIT_IMEM_DW_OK; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl | BIT_IMEM_CHKSUM_OK)); + } else { + mcu_fw_ctrl |= BIT_DMEM_DW_OK; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl | BIT_DMEM_CHKSUM_OK)); } + + return HALMAC_RET_SUCCESS; } HALMAC_RET_STATUS @@ -1050,33 +1179,64 @@ halmac_dlfw_end_flow_88xx( HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & ~(BIT(0)))); + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RSV_CTRL + 1); + value8 = (u8)(value8 | BIT(0)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RSV_CTRL + 1, value8); + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1); value8 = (u8)(value8 | BIT(2)); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, value8); /* Release MCU reset */ PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Download Finish, Reset CPU\n"); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) | BIT_AUTO_INIT_LLT_V1)); - counter = 1000; - while (HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) & BIT_AUTO_INIT_LLT_V1) { + counter = 10000; + while (HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) != 0xC078) { + if (counter == 0) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Check 0x80 = 0xC078 fail\n"); + if (0xFAAAAA00 == (HALMAC_REG_READ_32(pHalmac_adapter, REG_FW_DBG7) & 0xFFFFFF00)) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Key fail\n"); + return HALMAC_RET_DLFW_FAIL; + } counter--; - if (counter == 0) - return HALMAC_RET_INIT_LLT_FAIL; + PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Reset LLT\n"); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1, 0xC00F0038); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Check 0x80 = 0xC078 counter = %d\n", counter); - counter = 10000; - while (0xC078 != HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL)) { + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_free_dl_fw_end_flow_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u32 counter; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + counter = 100; + while (HALMAC_REG_READ_8(pHalmac_adapter, REG_HMETFR + 3) != 0) { + counter--; if (counter == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Check 0x80 = 0xC078 fail\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]0x1CF != 0\n"); return HALMAC_RET_DLFW_FAIL; } + PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); + } + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_HMETFR + 3, ID_INFORM_DLEMEM_RDY); + + counter = 10000; + while (HALMAC_REG_READ_8(pHalmac_adapter, REG_C2HEVT_3 + 3) != ID_INFORM_DLEMEM_RDY) { counter--; + if (counter == 0) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]0x1AF != 0x80\n"); + return HALMAC_RET_DLFW_FAIL; + } PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Check 0x80 = 0xC078 counter = %d\n", counter); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_C2HEVT_3 + 3, 0); return HALMAC_RET_SUCCESS; } @@ -1084,85 +1244,136 @@ halmac_dlfw_end_flow_88xx( HALMAC_RET_STATUS halmac_pwr_seq_parser_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 CUT, - IN u8 FAB, - IN u8 INTF, - IN PHALMAC_WLAN_PWR_CFG PWR_SEQ_CFG + IN u8 cut, + IN u8 fab, + IN u8 intf, + IN PHALMAC_WLAN_PWR_CFG *ppPwr_seq_cfg ) { - u8 value; - u8 PollingBit = _FALSE; - u32 AryIdx = 0; - u32 PollingCount; + u32 seq_idx = 0; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + PHALMAC_WLAN_PWR_CFG pSeq_cmd; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + do { + pSeq_cmd = ppPwr_seq_cfg[seq_idx]; + + if (pSeq_cmd == NULL) + break; + + status = halmac_pwr_sub_seq_parer_88xx(pHalmac_adapter, cut, fab, intf, pSeq_cmd); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[Err]pwr sub seq parser fail, status = 0x%X!\n", status); + return status; + } + + seq_idx++; + } while (1); + + return status; +} + +static HALMAC_RET_STATUS +halmac_pwr_sub_seq_parer_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 cut, + IN u8 fab, + IN u8 intf, + IN PHALMAC_WLAN_PWR_CFG pPwr_sub_seq_cfg +) +{ + u8 value, flag; + u8 polling_bit; u32 offset; + u32 polling_count; + static u32 poll_to_static; VOID *pDriver_adapter = NULL; - HALMAC_WLAN_PWR_CFG PWR_SEQ_CMD; + PHALMAC_WLAN_PWR_CFG pSub_seq_cmd; PHALMAC_API pHalmac_api; pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - do { - PWR_SEQ_CMD = PWR_SEQ_CFG[AryIdx]; + pSub_seq_cmd = pPwr_sub_seq_cfg; - if ((PWR_SEQ_CMD.interface_msk & INTF) && (PWR_SEQ_CMD.fab_msk & FAB) && (PWR_SEQ_CMD.cut_msk & CUT)) { - switch (PWR_SEQ_CMD.cmd) { + do { + if ((pSub_seq_cmd->interface_msk & intf) && (pSub_seq_cmd->fab_msk & fab) && (pSub_seq_cmd->cut_msk & cut)) { + switch (pSub_seq_cmd->cmd) { case HALMAC_PWR_CMD_WRITE: - if (PWR_SEQ_CMD.base == HALMAC_PWR_BASEADDR_SDIO) - offset = PWR_SEQ_CMD.offset | SDIO_LOCAL_OFFSET; + if (pSub_seq_cmd->base == HALMAC_PWR_BASEADDR_SDIO) + offset = pSub_seq_cmd->offset | SDIO_LOCAL_OFFSET; else - offset = PWR_SEQ_CMD.offset; + offset = pSub_seq_cmd->offset; value = HALMAC_REG_READ_8(pHalmac_adapter, offset); - value = (u8)(value & (u8)(~(PWR_SEQ_CMD.msk))); - value = (u8)(value | (u8)(PWR_SEQ_CMD.value & PWR_SEQ_CMD.msk)); + value = (u8)(value & (u8)(~(pSub_seq_cmd->msk))); + value = (u8)(value | (u8)(pSub_seq_cmd->value & pSub_seq_cmd->msk)); HALMAC_REG_WRITE_8(pHalmac_adapter, offset, value); break; case HALMAC_PWR_CMD_POLLING: - PollingBit = 0; - PollingCount = HALMAC_POLLING_READY_TIMEOUT_COUNT; + polling_bit = 0; + polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT; + flag = 0; - if (PWR_SEQ_CMD.base == HALMAC_PWR_BASEADDR_SDIO) - offset = PWR_SEQ_CMD.offset | SDIO_LOCAL_OFFSET; + + if (pSub_seq_cmd->base == HALMAC_PWR_BASEADDR_SDIO) + offset = pSub_seq_cmd->offset | SDIO_LOCAL_OFFSET; else - offset = PWR_SEQ_CMD.offset; + offset = pSub_seq_cmd->offset; do { - PollingCount--; + polling_count--; value = HALMAC_REG_READ_8(pHalmac_adapter, offset); - value = (u8)(value & PWR_SEQ_CMD.msk); + value = (u8)(value & pSub_seq_cmd->msk); - if (value == (PWR_SEQ_CMD.value & PWR_SEQ_CMD.msk)) { - PollingBit = 1; + if (value == (pSub_seq_cmd->value & pSub_seq_cmd->msk)) { + polling_bit = 1; } else { - if (0 == PollingCount) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_pwr_seq_parser_88xx HALMAC_RET_PWRSEQ_POLLING_FAIL\n"); - return HALMAC_RET_PWRSEQ_POLLING_FAIL; + if (polling_count == 0) { + if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface && 0 == flag) { + /* For PCIE + USB package poll power bit timeout issue */ + poll_to_static++; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "[WARN]PCIE polling timeout : %d!!\n", poll_to_static); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_PW_CTRL) | BIT(3)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_PW_CTRL) & ~BIT(3)); + polling_bit = 0; + polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT; + flag = 1; + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd polling timeout!!\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd offset : %X!!\n", pSub_seq_cmd->offset); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd value : %X!!\n", pSub_seq_cmd->value); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd msk : %X!!\n", pSub_seq_cmd->msk); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Read offset = %X value = %X!!\n", offset, value); + return HALMAC_RET_PWRSEQ_POLLING_FAIL; + } } else { PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); } } - } while (!PollingBit); + } while (!polling_bit); break; case HALMAC_PWR_CMD_DELAY: - if (PWR_SEQ_CMD.value == HALMAC_PWRSEQ_DELAY_US) - PLATFORM_RTL_DELAY_US(pDriver_adapter, PWR_SEQ_CMD.offset); + if (pSub_seq_cmd->value == HALMAC_PWRSEQ_DELAY_US) + PLATFORM_RTL_DELAY_US(pDriver_adapter, pSub_seq_cmd->offset); else - PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000 * PWR_SEQ_CMD.offset); + PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000 * pSub_seq_cmd->offset); break; case HALMAC_PWR_CMD_READ: break; case HALMAC_PWR_CMD_END: return HALMAC_RET_SUCCESS; default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_pwr_seq_parser_88xx HALMAC_RET_PWRSEQ_CMD_INCORRECT\n"); return HALMAC_RET_PWRSEQ_CMD_INCORRECT; } } - AryIdx++; + pSub_seq_cmd++; } while (1); + return HALMAC_RET_SUCCESS; } @@ -1200,14 +1411,14 @@ halmac_send_h2c_pkt_88xx( while (pHalmac_adapter->h2c_buf_free_space <= HALMAC_H2C_CMD_SIZE_UNIT_88XX) { halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter); counter--; - if (0 == counter) { + if (counter == 0) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "h2c free space is not enough!!\n"); return HALMAC_RET_H2C_SPACE_FULL; } } /* Send TxDesc + H2C_CMD */ - if (_FALSE == PLATFORM_SEND_H2C_PKT(pDriver_adapter, pHal_h2c_cmd, size)) { + if (PLATFORM_SEND_H2C_PKT(pDriver_adapter, pHal_h2c_cmd, size) == _FALSE) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Send H2C_CMD pkt error!!\n"); return HALMAC_RET_SEND_H2C_FAIL; } @@ -1236,7 +1447,7 @@ halmac_download_rsvd_page_88xx( pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - if (0 == size) { + if (size == 0) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Rsvd page packet size is zero!!\n"); return HALMAC_RET_ZERO_LEN_RSVD_PACKET; } @@ -1260,17 +1471,17 @@ halmac_download_rsvd_page_88xx( value8 = (u8)(value8 & ~(BIT(6))); HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8); - if (_FALSE == PLATFORM_SEND_RSVD_PAGE(pDriver_adapter, pHal_buf, size)) { + if (PLATFORM_SEND_RSVD_PAGE(pDriver_adapter, pHal_buf, size) == _FALSE) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "PLATFORM_SEND_RSVD_PAGE 1 error!!\n"); status = HALMAC_RET_DL_RSVD_PAGE_FAIL; } /* Check Bcn_Valid_Bit */ - counter = 100; + counter = 1000; while (!(HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1) & BIT(7))) { PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); counter--; - if (0 == counter) { + if (counter == 0) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Polling Bcn_Valid_Fail error!!\n"); status = HALMAC_RET_POLLING_BCN_VALID_FAIL; break; @@ -1302,13 +1513,13 @@ halmac_set_h2c_header_88xx( H2C_CMD_HEADER_SET_CATEGORY(pHal_h2c_hdr, 0x00); H2C_CMD_HEADER_SET_TOTAL_LEN(pHal_h2c_hdr, 16); - PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->h2c_seq_mutex); H2C_CMD_HEADER_SET_SEQ_NUM(pHal_h2c_hdr, pHalmac_adapter->h2c_packet_seq); *seq = pHalmac_adapter->h2c_packet_seq; pHalmac_adapter->h2c_packet_seq++; - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->h2c_seq_mutex); - if (_TRUE == ack) + if (ack == _TRUE) H2C_CMD_HEADER_SET_ACK(pHal_h2c_hdr, _TRUE); return HALMAC_RET_SUCCESS; @@ -1332,68 +1543,18 @@ halmac_set_fw_offload_h2c_header_88xx( FW_OFFLOAD_H2C_SET_CATEGORY(pHal_h2c_hdr, 0x01); FW_OFFLOAD_H2C_SET_CMD_ID(pHal_h2c_hdr, 0xFF); - PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->h2c_seq_mutex); FW_OFFLOAD_H2C_SET_SEQ_NUM(pHal_h2c_hdr, pHalmac_adapter->h2c_packet_seq); *pSeq_num = pHalmac_adapter->h2c_packet_seq; pHalmac_adapter->h2c_packet_seq++; - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->h2c_seq_mutex); - if (_TRUE == pH2c_header_info->ack) + if (pH2c_header_info->ack == _TRUE) FW_OFFLOAD_H2C_SET_ACK(pHal_h2c_hdr, _TRUE); return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS -halmac_send_h2c_set_pwr_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_FWLPS_OPTION pHal_FwLps_Opt -) -{ - u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX]; - u8 *pH2c_header, *pH2c_cmd; - u16 seq = 0; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_set_pwr_mode_88xx!!\n"); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pH2c_header = h2c_buff; - pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX; - - PLATFORM_RTL_MEMSET(pDriver_adapter, h2c_buff, 0x00, HALMAC_H2C_CMD_SIZE_88XX); - - SET_PWR_MODE_SET_CMD_ID(pH2c_cmd, CMD_ID_SET_PWR_MODE); - SET_PWR_MODE_SET_CLASS(pH2c_cmd, CLASS_SET_PWR_MODE); - SET_PWR_MODE_SET_MODE(pH2c_cmd, pHal_FwLps_Opt->mode); - SET_PWR_MODE_SET_CLK_REQUEST(pH2c_cmd, pHal_FwLps_Opt->clk_request); - SET_PWR_MODE_SET_RLBM(pH2c_cmd, pHal_FwLps_Opt->rlbm); - SET_PWR_MODE_SET_SMART_PS(pH2c_cmd, pHal_FwLps_Opt->smart_ps); - SET_PWR_MODE_SET_AWAKE_INTERVAL(pH2c_cmd, pHal_FwLps_Opt->awake_interval); - SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(pH2c_cmd, pHal_FwLps_Opt->all_queue_uapsd); - SET_PWR_MODE_SET_PWR_STATE(pH2c_cmd, pHal_FwLps_Opt->pwr_state); - SET_PWR_MODE_SET_ANT_AUTO_SWITCH(pH2c_cmd, pHal_FwLps_Opt->ant_auto_switch); - SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(pH2c_cmd, pHal_FwLps_Opt->ps_allow_bt_high_Priority); - SET_PWR_MODE_SET_PROTECT_BCN(pH2c_cmd, pHal_FwLps_Opt->protect_bcn); - SET_PWR_MODE_SET_SILENCE_PERIOD(pH2c_cmd, pHal_FwLps_Opt->silence_period); - SET_PWR_MODE_SET_FAST_BT_CONNECT(pH2c_cmd, pHal_FwLps_Opt->fast_bt_connect); - SET_PWR_MODE_SET_TWO_ANTENNA_EN(pH2c_cmd, pHal_FwLps_Opt->two_antenna_en); - SET_PWR_MODE_SET_ADOPT_USER_SETTING(pH2c_cmd, pHal_FwLps_Opt->adopt_user_Setting); - SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(pH2c_cmd, pHal_FwLps_Opt->drv_bcn_early_shift); - - halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, &seq, _TRUE); - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, h2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_set_pwr_mode_88xx Fail = %x!!\n", status); - return status; - } - - return HALMAC_RET_SUCCESS; -} - HALMAC_RET_STATUS halmac_func_send_original_h2c_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -1405,11 +1566,9 @@ halmac_func_send_original_h2c_88xx( u8 H2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; u8 *pH2c_header, *pH2c_cmd; VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c ==========>\n"); @@ -1421,7 +1580,7 @@ halmac_func_send_original_h2c_88xx( status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, H2c_buff, HALMAC_H2C_CMD_SIZE_88XX, ack); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_original_h2c Fail = %x!!\n", status); return status; } @@ -1431,48 +1590,6 @@ halmac_func_send_original_h2c_88xx( return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS -halmac_media_status_rpt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 op_mode, - IN u8 mac_id_ind, - IN u8 mac_id, - IN u8 mac_id_end -) -{ - u8 H2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u8 *pH2c_header, *pH2c_cmd; - u16 seq = 0; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_set_pwr_mode_88xx!!\n"); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pH2c_header = H2c_buff; - pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX; - - PLATFORM_RTL_MEMSET(pDriver_adapter, H2c_buff, 0x00, HALMAC_H2C_CMD_SIZE_88XX); - - MEDIA_STATUS_RPT_SET_CMD_ID(pH2c_cmd, CMD_ID_MEDIA_STATUS_RPT); - MEDIA_STATUS_RPT_SET_CLASS(pH2c_cmd, CLASS_MEDIA_STATUS_RPT); - MEDIA_STATUS_RPT_SET_OP_MODE(pH2c_cmd, op_mode); - MEDIA_STATUS_RPT_SET_MACID_IN(pH2c_cmd, mac_id_ind); - MEDIA_STATUS_RPT_SET_MACID(pH2c_cmd, mac_id); - MEDIA_STATUS_RPT_SET_MACID_END(pH2c_cmd, mac_id_end); - - halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, &seq, _TRUE); - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, H2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_media_status_rpt_88xx Fail = %x!!\n", status); - return status; - } - - return HALMAC_RET_SUCCESS; -} - HALMAC_RET_STATUS halmac_send_h2c_update_packet_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -1495,7 +1612,7 @@ halmac_send_h2c_update_packet_88xx( ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pkt, pkt_size); - if (HALMAC_RET_SUCCESS != ret_status) { + if (ret_status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", ret_status); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); return ret_status; @@ -1515,8 +1632,9 @@ halmac_send_h2c_update_packet_88xx( ret_status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (HALMAC_RET_SUCCESS != ret_status) { + if (ret_status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_packet_88xx Fail = %x!!\n", ret_status); + halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_UPDATE_PACKET); return ret_status; } @@ -1542,19 +1660,19 @@ halmac_send_h2c_phy_parameter_88xx( pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - pConfig_para_info = &(pHalmac_adapter->config_para_info); + pConfig_para_info = &pHalmac_adapter->config_para_info; /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_phy_parameter_88xx!!\n"); */ - if (NULL == pConfig_para_info->pCfg_para_buf) { - if (_TRUE == full_fifo) + if (pConfig_para_info->pCfg_para_buf == NULL) { + if (full_fifo == _TRUE) pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX; else pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX; pConfig_para_info->pCfg_para_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pConfig_para_info->para_buf_size); - if (NULL != pConfig_para_info->pCfg_para_buf) { + if (pConfig_para_info->pCfg_para_buf != NULL) { PLATFORM_RTL_MEMSET(pDriver_adapter, pConfig_para_info->pCfg_para_buf, 0x00, pConfig_para_info->para_buf_size); pConfig_para_info->full_fifo_mode = full_fifo; pConfig_para_info->pPara_buf_w = pConfig_para_info->pCfg_para_buf; @@ -1568,87 +1686,88 @@ halmac_send_h2c_phy_parameter_88xx( } } - if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING)) + if (halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; halmac_enqueue_para_buff_88xx(pHalmac_adapter, para_info, pConfig_para_info->pPara_buf_w, &drv_trigger_send); - if (HALMAC_PARAMETER_CMD_END != para_info->cmd_id) { + if (para_info->cmd_id != HALMAC_PARAMETER_CMD_END) { pConfig_para_info->para_num++; pConfig_para_info->pPara_buf_w += HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; pConfig_para_info->avai_para_buf_size = pConfig_para_info->avai_para_buf_size - HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; } if (((pConfig_para_info->avai_para_buf_size - pHalmac_adapter->hw_config_info.txdesc_size) > HALMAC_FW_OFFLOAD_CMD_SIZE_88XX) && - (_FALSE == drv_trigger_send)) { + (drv_trigger_send == _FALSE)) { return HALMAC_RET_SUCCESS; - } else { - if (0 == pConfig_para_info->para_num) { - PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size); - pConfig_para_info->pCfg_para_buf = NULL; - pConfig_para_info->pPara_buf_w = NULL; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "no cfg parameter element!!\n"); - - if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE)) - return HALMAC_RET_ERROR_STATE; + } - return HALMAC_RET_SUCCESS; - } + if (pConfig_para_info->para_num == 0) { + PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size); + pConfig_para_info->pCfg_para_buf = NULL; + pConfig_para_info->pPara_buf_w = NULL; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "no cfg parameter element!!\n"); - if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT)) + if (halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; - pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_SENDING; + return HALMAC_RET_SUCCESS; + } + + if (halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; - if (_TRUE == pConfig_para_info->full_fifo_mode) - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0); - else - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_SENDING; - info_size = pConfig_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; + if (pConfig_para_info->full_fifo_mode == _TRUE) + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0); + else + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - status = halmac_download_rsvd_page_88xx(pHalmac_adapter, (u8 *)pConfig_para_info->pCfg_para_buf, info_size); + info_size = pConfig_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail!!\n"); - } else { - halmac_gen_cfg_para_h2c_88xx(pHalmac_adapter, pH2c_buff); + status = halmac_download_rsvd_page_88xx(pHalmac_adapter, (u8 *)pConfig_para_info->pCfg_para_buf, info_size); - h2c_header_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAMETER; - h2c_header_info.content_size = 4; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail!!\n"); + } else { + halmac_gen_cfg_para_h2c_88xx(pHalmac_adapter, pH2c_buff); - pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num = h2c_seq_mum; + h2c_header_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAMETER; + h2c_header_info.content_size = 4; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num = h2c_seq_mum; - if (HALMAC_RET_SUCCESS != status) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n"); + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "config parameter time = %d\n", HALMAC_REG_READ_32(pHalmac_adapter, REG_FW_DBG6)); + if (status != HALMAC_RET_SUCCESS) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n"); + halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_CFG_PARA); } + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "config parameter time = %d\n", HALMAC_REG_READ_32(pHalmac_adapter, REG_FW_DBG6)); + } - PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size); - pConfig_para_info->pCfg_para_buf = NULL; - pConfig_para_info->pPara_buf_w = NULL; + PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size); + pConfig_para_info->pCfg_para_buf = NULL; + pConfig_para_info->pPara_buf_w = NULL; - /* Restore bcn head */ - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + /* Restore bcn head */ + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE)) - return HALMAC_RET_ERROR_STATE; - } + if (halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; - if (_FALSE == drv_trigger_send) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Buffer full trigger sending H2C!!\n"); + if (drv_trigger_send == _FALSE) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Buffer full trigger sending H2C!!\n"); return HALMAC_RET_PARA_SENDING; } return status; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_enqueue_para_buff_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN PHALMAC_PHY_PARAMETER_INFO para_info, @@ -1657,7 +1776,7 @@ halmac_enqueue_para_buff_88xx( ) { VOID *pDriver_adapter = NULL; - PHALMAC_CONFIG_PARA_INFO pConfig_para_info = &(pHalmac_adapter->config_para_info); + PHALMAC_CONFIG_PARA_INFO pConfig_para_info = &pHalmac_adapter->config_para_info; *pEnd_cmd = _FALSE; @@ -1702,18 +1821,17 @@ halmac_enqueue_para_buff_88xx( return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_gen_cfg_para_h2c_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pH2c_buff ) { - VOID *pDriver_adapter = NULL; - PHALMAC_CONFIG_PARA_INFO pConfig_para_info = &(pHalmac_adapter->config_para_info); + PHALMAC_CONFIG_PARA_INFO pConfig_para_info = &pHalmac_adapter->config_para_info; CFG_PARAMETER_SET_NUM(pH2c_buff, pConfig_para_info->para_num); - if (_TRUE == pConfig_para_info->full_fifo_mode) { + if (pConfig_para_info->full_fifo_mode == _TRUE) { CFG_PARAMETER_SET_INIT_CASE(pH2c_buff, 0x1); CFG_PARAMETER_SET_PHY_PARAMETER_LOC(pH2c_buff, 0); } else { @@ -1723,153 +1841,7 @@ halmac_gen_cfg_para_h2c_88xx( return HALMAC_RET_SUCCESS; } -#if 0 -HALMAC_RET_STATUS -halmac_send_h2c_update_datapack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DATA_TYPE halmac_data_type, - IN PHALMAC_PHY_PARAMETER_INFO para_info -) -{ - u8 drv_trigger_send = _FALSE; - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u8 *pCurr_buf_w; - u16 h2c_seq_mum = 0; - u32 info_size = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - PHALMAC_CONFIG_PARA_INFO pConfig_para_info; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - pConfig_para_info = &(pHalmac_adapter->config_para_info); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_phy_parameter_88xx!!\n"); - - if (NULL == pConfig_para_info->pCfg_para_buf) {/*Buff null, allocate memory according to use mode*/ - /*else, only 4k reserved page is used*/ - pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX; - /* pConfig_para_info->datapack_segment =0; */ - - - pConfig_para_info->pCfg_para_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pConfig_para_info->para_buf_size); - if (NULL != pConfig_para_info->pCfg_para_buf) { - /*Reset buffer parameter*/ - PLATFORM_RTL_MEMSET(pDriver_adapter, pConfig_para_info->pCfg_para_buf, 0x00, pConfig_para_info->para_buf_size); - /* pConfig_para_info->full_fifo_mode = full_fifo; */ - pConfig_para_info->data_type = halmac_data_type; - pConfig_para_info->pPara_buf_w = pConfig_para_info->pCfg_para_buf; - pConfig_para_info->para_num = 0; - pConfig_para_info->avai_para_buf_size = pConfig_para_info->para_buf_size; - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Allocate pCfg_para_buf fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - } - - pCurr_buf_w = pConfig_para_info->pPara_buf_w; - - /*Start fill buffer content*/ - PHY_PARAMETER_INFO_SET_LENGTH(pCurr_buf_w, HALMAC_FW_OFFLOAD_CMD_SIZE_88XX);/* Each element is 12 Byte */ - PHY_PARAMETER_INFO_SET_IO_CMD(pCurr_buf_w, para_info->cmd_id); - - switch (para_info->cmd_id) { - case HALMAC_PARAMETER_CMD_BB_W8: - case HALMAC_PARAMETER_CMD_BB_W16: - case HALMAC_PARAMETER_CMD_BB_W32: - case HALMAC_PARAMETER_CMD_MAC_W8: - case HALMAC_PARAMETER_CMD_MAC_W16: - case HALMAC_PARAMETER_CMD_MAC_W32: - PHY_PARAMETER_INFO_SET_IO_ADDR(pCurr_buf_w, para_info->content.MAC_REG_W.offset); - PHY_PARAMETER_INFO_SET_DATA(pCurr_buf_w, para_info->content.MAC_REG_W.value); - PHY_PARAMETER_INFO_SET_MASK(pCurr_buf_w, para_info->content.MAC_REG_W.msk); - PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buf_w, para_info->content.MAC_REG_W.msk_en); - break; - case HALMAC_PARAMETER_CMD_RF_W: - PHY_PARAMETER_INFO_SET_RF_ADDR(pCurr_buf_w, para_info->content.RF_REG_W.offset); /* In rf register, the address is only 1 byte */ - PHY_PARAMETER_INFO_SET_RF_PATH(pCurr_buf_w, para_info->content.RF_REG_W.rf_path); - PHY_PARAMETER_INFO_SET_DATA(pCurr_buf_w, para_info->content.RF_REG_W.value); - PHY_PARAMETER_INFO_SET_MASK(pCurr_buf_w, para_info->content.RF_REG_W.msk); - PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buf_w, para_info->content.MAC_REG_W.msk_en); - break; - case HALMAC_PARAMETER_CMD_DELAY_US: - case HALMAC_PARAMETER_CMD_DELAY_MS: - PHY_PARAMETER_INFO_SET_DELAY_VALUE(pCurr_buf_w, para_info->content.DELAY_TIME.delay_time); - break; - - case HALMAC_PARAMETER_CMD_END: - /* PHY_PARAMETER_INFO_SET_MSK_EN(pHalmac_adapter->pPara_buf_w, 1); */ - drv_trigger_send = _TRUE; - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "illegal cmd_id!!\n"); - /* return _FALSE; */ - break; - } - - /*Update parameter buffer variable*/ - if (HALMAC_PARAMETER_CMD_END != para_info->cmd_id) { - pConfig_para_info->para_num++; - pConfig_para_info->pPara_buf_w += HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; - pConfig_para_info->avai_para_buf_size = pConfig_para_info->avai_para_buf_size - HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; - } - - if (((pConfig_para_info->avai_para_buf_size - pHalmac_adapter->hw_config_info.txdesc_size) > HALMAC_FW_OFFLOAD_CMD_SIZE_88XX) && (_FALSE == drv_trigger_send)) { - /*There are still space for parameter cmd, and driver does not trigger it to send, so keep it in buffer temporarily*/ - return HALMAC_RET_SUCCESS_ENQUEUE; - } else { - /*There is no space or driver trigger it to send*/ - - /*Update the bcn head(dma)*/ - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->h2c_extra_info_boundary & BIT_MASK_BCN_HEAD_1_V1)); - - /* Download to reserved page */ - info_size = pConfig_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; - status = halmac_download_rsvd_page_88xx(pHalmac_adapter, (u8 *)pConfig_para_info->pCfg_para_buf, info_size); - if (HALMAC_RET_SUCCESS != status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail!!\n"); - } else {/*download rsvd page ok, send h2c packet to fw*/ - /* Construct H2C Content */ - UPDATE_DATAPACK_SET_SIZE(pH2c_buff, pConfig_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX); - UPDATE_DATAPACK_SET_DATAPACK_ID(pH2c_buff, pConfig_para_info->data_type); - UPDATE_DATAPACK_SET_DATAPACK_LOC(pH2c_buff, pHalmac_adapter->h2c_extra_info_boundary - pHalmac_adapter->Tx_boundary); - UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(pH2c_buff, pConfig_para_info->datapack_segment); - UPDATE_DATAPACK_SET_END_SEGMENT(pH2c_buff, drv_trigger_send); - - /* Fill in H2C Header */ - h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_DATAPACK; - h2c_header_info.content_size = 8; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - - /* Send H2C Cmd Packet */ - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (HALMAC_RET_SUCCESS != status) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n"); - } - - PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size); - if (_TRUE == drv_trigger_send) - pConfig_para_info->datapack_segment = 0; - else - pConfig_para_info->datapack_segment++; - - pConfig_para_info->pCfg_para_buf = NULL; - pConfig_para_info->pPara_buf_w = NULL; - pConfig_para_info->para_num = 0; - pConfig_para_info->avai_para_buf_size = 0; - - /*Restore Register after FW handle the H2C packet*/ - - /*only set bcn head back*/ - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->Tx_boundary & BIT_MASK_BCN_HEAD_1_V1)); - } - - return status; -} -#endif + HALMAC_RET_STATUS halmac_send_h2c_run_datapack_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -1895,7 +1867,7 @@ halmac_send_h2c_run_datapack_88xx( status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); return status; } @@ -1930,7 +1902,7 @@ halmac_send_bt_coex_cmd_88xx( status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, ack); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); return status; } @@ -1951,24 +1923,24 @@ halmac_func_ctrl_ch_switch_88xx( PHALMAC_API pHalmac_api; HALMAC_H2C_HEADER_INFO h2c_header_info; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.scan_state_set.process_status); + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.scan_state_set.process_status; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch!!\n"); pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT)) + if (halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; *pProcess_status = HALMAC_CMD_PROCESS_SENDING; - if (0 != pCs_option->switch_en) { + if (pCs_option->switch_en != 0) { HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.total_size); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", status); HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); return status; @@ -1999,9 +1971,10 @@ halmac_func_ctrl_ch_switch_88xx( status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (HALMAC_RET_SUCCESS != status) + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); - + halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_CHANNEL_SWITCH); + } PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.buf_size); pHalmac_adapter->ch_sw_info.ch_info_buf = NULL; pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL; @@ -2011,7 +1984,7 @@ halmac_func_ctrl_ch_switch_88xx( pHalmac_adapter->ch_sw_info.total_size = 0; pHalmac_adapter->ch_sw_info.ch_num = 0; - if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_IDLE)) + if (halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) return HALMAC_RET_ERROR_STATE; return status; @@ -2044,7 +2017,7 @@ halmac_func_send_general_info_88xx( status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (HALMAC_RET_SUCCESS != status) + if (status != HALMAC_RET_SUCCESS) PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); return status; @@ -2083,7 +2056,7 @@ halmac_send_h2c_update_bcn_parse_info_88xx( status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail =%x !!\n", status); return status; } @@ -2113,7 +2086,7 @@ halmac_send_h2c_ps_tuning_para_88xx( status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _FALSE); - if (HALMAC_RET_SUCCESS != status) { + if (status != HALMAC_RET_SUCCESS) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); return status; } @@ -2139,7 +2112,7 @@ halmac_parse_c2h_packet_88xx( c2h_cmd = (u8)C2H_HDR_GET_CMD_ID(pC2h_buf); /* FW offload C2H cmd is 0xFF */ - if (0xFF != c2h_cmd) { + if (c2h_cmd != 0xFF) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H_PKT not for FwOffloadC2HFormat!!\n"); return HALMAC_RET_C2H_NOT_HANDLED; } @@ -2168,7 +2141,8 @@ halmac_parse_c2h_packet_88xx( status = halmac_parse_efuse_data_88xx(pHalmac_adapter, pC2h_buf, c2h_size); break; default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "c2h_sub_cmd_id switch case out of boundary!!\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "c2h_sub_cmd_id switch case out of boundary!!\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "[ERR]c2h pkt : %.8X %.8X!!\n", *(u32 *)pC2h_buf, *(u32 *)(pC2h_buf + 4)); status = HALMAC_RET_C2H_NOT_HANDLED; break; } @@ -2176,7 +2150,7 @@ halmac_parse_c2h_packet_88xx( return status; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_c2h_debug_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -2195,19 +2169,18 @@ halmac_parse_c2h_debug_88xx( dbg_content_length = (u8)C2H_HDR_GET_LEN((u8 *)pC2h_buf_local); - if (dbg_content_length > C2H_DBG_CONTENT_MAX_LENGTH) { + if (dbg_content_length > C2H_DBG_CONTENT_MAX_LENGTH) return HALMAC_RET_SUCCESS; - } else { - *(pC2h_buf_local + C2H_DBG_HEADER_LENGTH + dbg_content_length - 2) = '\n'; - dbg_seq_num = (u8)(*(pC2h_buf_local + C2H_DBG_HEADER_LENGTH)); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[RTKFW, SEQ=%d]: %s", dbg_seq_num, (char *)(pC2h_buf_local + C2H_DBG_HEADER_LENGTH + 1)); - } + + *(pC2h_buf_local + C2H_DBG_HEADER_LENGTH + dbg_content_length - 2) = '\n'; + dbg_seq_num = (u8)(*(pC2h_buf_local + C2H_DBG_HEADER_LENGTH)); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[RTKFW, SEQ=%d]: %s", dbg_seq_num, (char *)(pC2h_buf_local + C2H_DBG_HEADER_LENGTH + 1)); return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_scan_status_rpt_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -2216,7 +2189,7 @@ halmac_parse_scan_status_rpt_88xx( { u8 h2c_return_code; VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; + HALMAC_CMD_PROCESS_STATUS process_status; h2c_return_code = (u8)SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(pC2h_buf); process_status = (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) ? HALMAC_CMD_PROCESS_DONE : HALMAC_CMD_PROCESS_ERROR; @@ -2225,13 +2198,13 @@ halmac_parse_scan_status_rpt_88xx( pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "scan status : %X\n", process_status); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]scan status : %X\n", process_status); return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_psd_data_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -2241,18 +2214,18 @@ halmac_parse_psd_data_88xx( u8 segment_id = 0, segment_size = 0, h2c_seq = 0; u16 total_size; VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; - PHALMAC_PSD_STATE_SET pPsd_set = &(pHalmac_adapter->halmac_state.psd_set); + HALMAC_CMD_PROCESS_STATUS process_status; + PHALMAC_PSD_STATE_SET pPsd_set = &pHalmac_adapter->halmac_state.psd_set; h2c_seq = (u8)PSD_DATA_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pPsd_set->seq_num, h2c_seq); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pPsd_set->seq_num, h2c_seq); if (h2c_seq != pPsd_set->seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pPsd_set->seq_num, h2c_seq); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pPsd_set->seq_num, h2c_seq); return HALMAC_RET_SUCCESS; } - if (HALMAC_CMD_PROCESS_SENDING != pPsd_set->process_status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n"); + if (pPsd_set->process_status != HALMAC_CMD_PROCESS_SENDING) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); return HALMAC_RET_SUCCESS; } @@ -2261,15 +2234,15 @@ halmac_parse_psd_data_88xx( segment_size = (u8)PSD_DATA_GET_SEGMENT_SIZE(pC2h_buf); pPsd_set->data_size = total_size; - if (NULL == pPsd_set->pData) + if (pPsd_set->pData == NULL) pPsd_set->pData = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pPsd_set->data_size); - if (0 == segment_id) + if (segment_id == 0) pPsd_set->segment_size = segment_size; PLATFORM_RTL_MEMCPY(pDriver_adapter, pPsd_set->pData + segment_id * pPsd_set->segment_size, pC2h_buf + HALMAC_C2H_DATA_OFFSET_88XX, segment_size); - if (_FALSE == PSD_DATA_GET_END_SEGMENT(pC2h_buf)) + if (PSD_DATA_GET_END_SEGMENT(pC2h_buf) == _FALSE) return HALMAC_RET_SUCCESS; process_status = HALMAC_CMD_PROCESS_DONE; @@ -2280,7 +2253,7 @@ halmac_parse_psd_data_88xx( return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_efuse_data_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -2292,57 +2265,62 @@ halmac_parse_efuse_data_88xx( u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; u8 h2c_return_code = 0; VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; - - pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); - if (NULL == pEeprom_map) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); + HALMAC_CMD_PROCESS_STATUS process_status; h2c_seq = (u8)EFUSE_DATA_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); if (h2c_seq != pHalmac_adapter->halmac_state.efuse_state_set.seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); return HALMAC_RET_SUCCESS; } - if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.efuse_state_set.process_status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n"); + if (pHalmac_adapter->halmac_state.efuse_state_set.process_status != HALMAC_CMD_PROCESS_SENDING) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); return HALMAC_RET_SUCCESS; } - pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code = h2c_return_code; segment_id = (u8)EFUSE_DATA_GET_SEGMENT_ID(pC2h_buf); segment_size = (u8)EFUSE_DATA_GET_SEGMENT_SIZE(pC2h_buf); - if (0 == segment_id) + if (segment_id == 0) pHalmac_adapter->efuse_segment_size = segment_size; - PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); - PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map + segment_id * pHalmac_adapter->efuse_segment_size, \ + pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); + if (pEeprom_map == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); + + PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); + PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map + segment_id * pHalmac_adapter->efuse_segment_size, pC2h_buf + HALMAC_C2H_DATA_OFFSET_88XX, segment_size); - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - if (_FALSE == EFUSE_DATA_GET_END_SEGMENT(pC2h_buf)) + if (EFUSE_DATA_GET_END_SEGMENT(pC2h_buf) == _FALSE) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); return HALMAC_RET_SUCCESS; + } + + h2c_return_code = pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code; if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) { process_status = HALMAC_CMD_PROCESS_DONE; pHalmac_adapter->halmac_state.efuse_state_set.process_status = process_status; - PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); pHalmac_adapter->hal_efuse_map_valid = _TRUE; - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - if (1 == pHalmac_adapter->event_trigger.physical_efuse_map) { + if (pHalmac_adapter->event_trigger.physical_efuse_map == 1) { PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, process_status, pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size); pHalmac_adapter->event_trigger.physical_efuse_map = 0; } - if (1 == pHalmac_adapter->event_trigger.logical_efuse_map) { - if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map)) + if (pHalmac_adapter->event_trigger.logical_efuse_map == 1) { + if (halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map) != HALMAC_RET_SUCCESS) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); return HALMAC_RET_EEPROM_PARSING_FAIL; + } PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, process_status, pEeprom_map, eeprom_size); pHalmac_adapter->event_trigger.logical_efuse_map = 0; } @@ -2350,15 +2328,17 @@ halmac_parse_efuse_data_88xx( process_status = HALMAC_CMD_PROCESS_ERROR; pHalmac_adapter->halmac_state.efuse_state_set.process_status = process_status; - if (1 == pHalmac_adapter->event_trigger.physical_efuse_map) { - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, process_status, &(pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code), 1); + if (pHalmac_adapter->event_trigger.physical_efuse_map == 1) { + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, process_status, &pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code, 1); pHalmac_adapter->event_trigger.physical_efuse_map = 0; } - if (1 == pHalmac_adapter->event_trigger.logical_efuse_map) { - if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map)) + if (pHalmac_adapter->event_trigger.logical_efuse_map == 1) { + if (halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map) != HALMAC_RET_SUCCESS) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); return HALMAC_RET_EEPROM_PARSING_FAIL; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, process_status, &(pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code), 1); + } + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, process_status, &pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code, 1); pHalmac_adapter->event_trigger.logical_efuse_map = 0; } } @@ -2368,7 +2348,7 @@ halmac_parse_efuse_data_88xx( return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -2376,13 +2356,10 @@ halmac_parse_h2c_ack_88xx( ) { u8 h2c_cmd_id, h2c_sub_cmd_id; - u8 h2c_seq = 0, offset = 0, shift = 0; u8 h2c_return_code; VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Ack for C2H!!\n"); h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); @@ -2391,7 +2368,7 @@ halmac_parse_h2c_ack_88xx( h2c_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(pC2h_buf); - if (0xFF != h2c_cmd_id) { + if (h2c_cmd_id != 0xFF) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "original h2c ack is not handled!!\n"); status = HALMAC_RET_C2H_NOT_HANDLED; } else { @@ -2399,6 +2376,7 @@ halmac_parse_h2c_ack_88xx( switch (h2c_sub_cmd_id) { case H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK: + status = halmac_parse_h2c_ack_phy_efuse_88xx(pHalmac_adapter, pC2h_buf, c2h_size); break; case H2C_SUB_CMD_ID_CFG_PARAMETER_ACK: status = halmac_parse_h2c_ack_cfg_para_88xx(pHalmac_adapter, pC2h_buf, c2h_size); @@ -2424,7 +2402,7 @@ halmac_parse_h2c_ack_88xx( case H2C_SUB_CMD_ID_PSD_ACK: break; default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "h2c_sub_cmd_id switch case out of boundary!!\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "h2c_sub_cmd_id switch case out of boundary!!\n"); status = HALMAC_RET_C2H_NOT_HANDLED; break; } @@ -2433,7 +2411,36 @@ halmac_parse_h2c_ack_88xx( return status; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS +halmac_parse_h2c_ack_phy_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + u8 h2c_seq = 0; + u8 h2c_return_code; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); + if (h2c_seq != pHalmac_adapter->halmac_state.efuse_state_set.seq_num) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); + return HALMAC_RET_SUCCESS; + } + + if (pHalmac_adapter->halmac_state.efuse_state_set.process_status != HALMAC_CMD_PROCESS_SENDING) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); + return HALMAC_RET_SUCCESS; + } + + h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); + pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code = h2c_return_code; + + return HALMAC_RET_SUCCESS; +} + +static HALMAC_RET_STATUS halmac_parse_h2c_ack_cfg_para_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -2453,7 +2460,7 @@ halmac_parse_h2c_ack_cfg_para_88xx( return HALMAC_RET_SUCCESS; } - if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.cfg_para_state_set.process_status) { + if (pHalmac_adapter->halmac_state.cfg_para_state_set.process_status != HALMAC_CMD_PROCESS_SENDING) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n"); return HALMAC_RET_SUCCESS; } @@ -2469,21 +2476,20 @@ halmac_parse_h2c_ack_cfg_para_88xx( process_status = HALMAC_CMD_PROCESS_ERROR; } - if ((HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) && (HALMAC_CMD_PROCESS_ERROR != process_status)) { + if (((HALMAC_H2C_RETURN_CODE)h2c_return_code == HALMAC_H2C_RETURN_SUCCESS) && (process_status != HALMAC_CMD_PROCESS_ERROR)) { process_status = HALMAC_CMD_PROCESS_DONE; pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = process_status; PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CFG_PARA, process_status, NULL, 0); } else { process_status = HALMAC_CMD_PROCESS_ERROR; pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CFG_PARA, process_status, &(pHalmac_adapter->halmac_state.cfg_para_state_set.fw_return_code), 1); + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CFG_PARA, process_status, &pHalmac_adapter->halmac_state.cfg_para_state_set.fw_return_code, 1); } return HALMAC_RET_SUCCESS; } - -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_update_packet_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -2493,17 +2499,17 @@ halmac_parse_h2c_ack_update_packet_88xx( u8 h2c_seq = 0; u8 h2c_return_code; VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; + HALMAC_CMD_PROCESS_STATUS process_status; h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.update_packet_set.seq_num, h2c_seq); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.update_packet_set.seq_num, h2c_seq); if (h2c_seq != pHalmac_adapter->halmac_state.update_packet_set.seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.update_packet_set.seq_num, h2c_seq); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.update_packet_set.seq_num, h2c_seq); return HALMAC_RET_SUCCESS; } - if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.update_packet_set.process_status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n"); + if (pHalmac_adapter->halmac_state.update_packet_set.process_status != HALMAC_CMD_PROCESS_SENDING) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); return HALMAC_RET_SUCCESS; } @@ -2517,13 +2523,13 @@ halmac_parse_h2c_ack_update_packet_88xx( } else { process_status = HALMAC_CMD_PROCESS_ERROR; pHalmac_adapter->halmac_state.update_packet_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_PACKET, process_status, &(pHalmac_adapter->halmac_state.update_packet_set.fw_return_code), 1); + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_PACKET, process_status, &pHalmac_adapter->halmac_state.update_packet_set.fw_return_code, 1); } return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_update_datapack_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -2539,7 +2545,7 @@ halmac_parse_h2c_ack_update_datapack_88xx( } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_run_datapack_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -2555,7 +2561,7 @@ halmac_parse_h2c_ack_run_datapack_88xx( } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_channel_switch_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -2565,37 +2571,37 @@ halmac_parse_h2c_ack_channel_switch_88xx( u8 h2c_seq = 0; u8 h2c_return_code; VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; + HALMAC_CMD_PROCESS_STATUS process_status; h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.scan_state_set.seq_num, h2c_seq); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.scan_state_set.seq_num, h2c_seq); if (h2c_seq != pHalmac_adapter->halmac_state.scan_state_set.seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.scan_state_set.seq_num, h2c_seq); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.scan_state_set.seq_num, h2c_seq); return HALMAC_RET_SUCCESS; } - if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.scan_state_set.process_status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n"); + if (pHalmac_adapter->halmac_state.scan_state_set.process_status != HALMAC_CMD_PROCESS_SENDING) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); return HALMAC_RET_SUCCESS; } h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); pHalmac_adapter->halmac_state.scan_state_set.fw_return_code = h2c_return_code; - if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) { + if ((HALMAC_H2C_RETURN_CODE)h2c_return_code == HALMAC_H2C_RETURN_SUCCESS) { process_status = HALMAC_CMD_PROCESS_RCVD; pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status; PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, NULL, 0); } else { process_status = HALMAC_CMD_PROCESS_ERROR; pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, &(pHalmac_adapter->halmac_state.scan_state_set.fw_return_code), 1); + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, &pHalmac_adapter->halmac_state.scan_state_set.fw_return_code, 1); } return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_iqk_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -2605,37 +2611,37 @@ halmac_parse_h2c_ack_iqk_88xx( u8 h2c_seq = 0; u8 h2c_return_code; VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; + HALMAC_CMD_PROCESS_STATUS process_status; h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq); if (h2c_seq != pHalmac_adapter->halmac_state.iqk_set.seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq); return HALMAC_RET_SUCCESS; } - if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.iqk_set.process_status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n"); + if (pHalmac_adapter->halmac_state.iqk_set.process_status != HALMAC_CMD_PROCESS_SENDING) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); return HALMAC_RET_SUCCESS; } h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); pHalmac_adapter->halmac_state.iqk_set.fw_return_code = h2c_return_code; - if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) { + if ((HALMAC_H2C_RETURN_CODE)h2c_return_code == HALMAC_H2C_RETURN_SUCCESS) { process_status = HALMAC_CMD_PROCESS_DONE; pHalmac_adapter->halmac_state.iqk_set.process_status = process_status; PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_IQK, process_status, NULL, 0); } else { process_status = HALMAC_CMD_PROCESS_ERROR; pHalmac_adapter->halmac_state.iqk_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_IQK, process_status, &(pHalmac_adapter->halmac_state.iqk_set.fw_return_code), 1); + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_IQK, process_status, &pHalmac_adapter->halmac_state.iqk_set.fw_return_code, 1); } return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_parse_h2c_ack_power_tracking_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, IN u8 *pC2h_buf, @@ -2645,31 +2651,31 @@ halmac_parse_h2c_ack_power_tracking_88xx( u8 h2c_seq = 0; u8 h2c_return_code; VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; + HALMAC_CMD_PROCESS_STATUS process_status; h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.power_tracking_set.seq_num, h2c_seq); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.power_tracking_set.seq_num, h2c_seq); if (h2c_seq != pHalmac_adapter->halmac_state.power_tracking_set.seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.power_tracking_set.seq_num, h2c_seq); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.power_tracking_set.seq_num, h2c_seq); return HALMAC_RET_SUCCESS; } - if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.power_tracking_set.process_status) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n"); + if (pHalmac_adapter->halmac_state.power_tracking_set.process_status != HALMAC_CMD_PROCESS_SENDING) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); return HALMAC_RET_SUCCESS; } h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); pHalmac_adapter->halmac_state.power_tracking_set.fw_return_code = h2c_return_code; - if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) { + if ((HALMAC_H2C_RETURN_CODE)h2c_return_code == HALMAC_H2C_RETURN_SUCCESS) { process_status = HALMAC_CMD_PROCESS_DONE; pHalmac_adapter->halmac_state.power_tracking_set.process_status = process_status; PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_POWER_TRACKING, process_status, NULL, 0); } else { process_status = HALMAC_CMD_PROCESS_ERROR; pHalmac_adapter->halmac_state.power_tracking_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_POWER_TRACKING, process_status, &(pHalmac_adapter->halmac_state.power_tracking_set.fw_return_code), 1); + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_POWER_TRACKING, process_status, &pHalmac_adapter->halmac_state.power_tracking_set.fw_return_code, 1); } return HALMAC_RET_SUCCESS; @@ -2687,10 +2693,10 @@ halmac_convert_to_sdio_bus_offset_88xx( switch ((*halmac_offset) & 0xFFFF0000) { case WLAN_IOREG_OFFSET: - *halmac_offset = (WLAN_IOREG_DEVICE_ID << 13) | (*halmac_offset & HALMAC_WLAN_IOREG_MSK); + *halmac_offset = (HALMAC_SDIO_CMD_ADDR_MAC_REG << 13) | (*halmac_offset & HALMAC_WLAN_MAC_REG_MSK); break; case SDIO_LOCAL_OFFSET: - *halmac_offset = (SDIO_LOCAL_DEVICE_ID << 13) | (*halmac_offset & HALMAC_SDIO_LOCAL_MSK); + *halmac_offset = (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | (*halmac_offset & HALMAC_SDIO_LOCAL_MSK); break; default: *halmac_offset = 0xFFFFFFFF; @@ -2706,26 +2712,33 @@ halmac_update_sdio_free_page_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ) { - u32 free_page = 0, free_page2 = 0, oqt_free_page = 0; + u32 free_page = 0, free_page2 = 0, free_page3 = 0; VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; PHALMAC_SDIO_FREE_SPACE pSdio_free_space; + u8 data[12] = {0}; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_sdio_free_page_88xx ==========>\n"); - pSdio_free_space = &(pHalmac_adapter->sdio_free_space); + pSdio_free_space = &pHalmac_adapter->sdio_free_space; + + HALMAC_REG_SDIO_CMD53_READ_N(pHalmac_adapter, REG_SDIO_FREE_TXPG, 12, data); - free_page = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG); - free_page2 = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG2); + free_page = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24); + free_page2 = data[4] | (data[5] << 8) | (data[6] << 16) | (data[7] << 24); + free_page3 = data[8] | (data[9] << 8) | (data[10] << 16) | (data[11] << 24); pSdio_free_space->high_queue_number = (u16)BIT_GET_HIQ_FREEPG_V1(free_page); pSdio_free_space->normal_queue_number = (u16)BIT_GET_MID_FREEPG_V1(free_page); pSdio_free_space->low_queue_number = (u16)BIT_GET_LOW_FREEPG_V1(free_page2); pSdio_free_space->public_queue_number = (u16)BIT_GET_PUB_FREEPG_V1(free_page2); - pSdio_free_space->extra_queue_number = (u16)BIT_GET_EXQ_FREEPG_V1(oqt_free_page); + pSdio_free_space->extra_queue_number = (u16)BIT_GET_EXQ_FREEPG_V1(free_page3); + pSdio_free_space->ac_oqt_number = (u8)BIT_GET_AC_OQT_FREEPG_V1(free_page3); + pSdio_free_space->non_ac_oqt_number = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(free_page3); PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_sdio_free_page_88xx <==========\n"); @@ -2740,18 +2753,32 @@ halmac_update_oqt_free_space_88xx( VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; PHALMAC_SDIO_FREE_SPACE pSdio_free_space; + u8 value; + u32 oqt_free_page; pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_oqt_free_space_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_update_oqt_free_space_88xx ==========>\n"); - pSdio_free_space = &(pHalmac_adapter->sdio_free_space); + pSdio_free_space = &pHalmac_adapter->sdio_free_space; - pSdio_free_space->ac_oqt_number = HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_OQT_FREE_TXPG_V1 + 2); - /* pSdio_free_space->non_ac_oqt_number = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(oqt_free_page); */ + oqt_free_page = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_OQT_FREE_TXPG_V1); + pSdio_free_space->ac_oqt_number = (u8)BIT_GET_AC_OQT_FREEPG_V1(oqt_free_page); + pSdio_free_space->non_ac_oqt_number = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(oqt_free_page); + pSdio_free_space->ac_empty = 0; + if (pSdio_free_space->ac_oqt_number == HALMAC_OQT_ENTRY_AC_88XX) { + value = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPKT_EMPTY); + while (value > 0) { + value = value & (value - 1); + pSdio_free_space->ac_empty++; + }; + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "pSdio_free_space->ac_oqt_number %d != %d\n", + pSdio_free_space->ac_oqt_number, HALMAC_OQT_ENTRY_AC_88XX); + } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_oqt_free_space_88xx <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_update_oqt_free_space_88xx <==========\n"); return HALMAC_RET_SUCCESS; } @@ -2770,21 +2797,21 @@ halmac_transition_efuse_state_88xx( IN HALMAC_EFUSE_CMD_CONSTRUCT_STATE dest_state ) { - PHALMAC_EFUSE_STATE_SET pEfuse_state = &(pHalmac_adapter->halmac_state.efuse_state_set); + PHALMAC_EFUSE_STATE_SET pEfuse_state = &pHalmac_adapter->halmac_state.efuse_state_set; - if ((HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != pEfuse_state->efuse_cmd_construct_state) \ - && (HALMAC_EFUSE_CMD_CONSTRUCT_BUSY != pEfuse_state->efuse_cmd_construct_state) \ - && (HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT != pEfuse_state->efuse_cmd_construct_state)) + if ((pEfuse_state->efuse_cmd_construct_state != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) + && (pEfuse_state->efuse_cmd_construct_state != HALMAC_EFUSE_CMD_CONSTRUCT_BUSY) + && (pEfuse_state->efuse_cmd_construct_state != HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT)) return HALMAC_RET_ERROR_STATE; if (pEfuse_state->efuse_cmd_construct_state == dest_state) return HALMAC_RET_ERROR_STATE; - if (HALMAC_EFUSE_CMD_CONSTRUCT_BUSY == dest_state) { - if (HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT == pEfuse_state->efuse_cmd_construct_state) + if (dest_state == HALMAC_EFUSE_CMD_CONSTRUCT_BUSY) { + if (pEfuse_state->efuse_cmd_construct_state == HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT) return HALMAC_RET_ERROR_STATE; - } else if (HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT == dest_state) { - if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE == pEfuse_state->efuse_cmd_construct_state) + } else if (dest_state == HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT) { + if (pEfuse_state->efuse_cmd_construct_state == HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) return HALMAC_RET_ERROR_STATE; } @@ -2807,22 +2834,22 @@ halmac_transition_cfg_para_state_88xx( IN HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE dest_state ) { - PHALMAC_CFG_PARA_STATE_SET pCfg_para = &(pHalmac_adapter->halmac_state.cfg_para_state_set); + PHALMAC_CFG_PARA_STATE_SET pCfg_para = &pHalmac_adapter->halmac_state.cfg_para_state_set; - if ((HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE != pCfg_para->cfg_para_cmd_construct_state) && \ - (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING != pCfg_para->cfg_para_cmd_construct_state) && \ - (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT != pCfg_para->cfg_para_cmd_construct_state)) + if ((pCfg_para->cfg_para_cmd_construct_state != HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) && + (pCfg_para->cfg_para_cmd_construct_state != HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING) && + (pCfg_para->cfg_para_cmd_construct_state != HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT)) return HALMAC_RET_ERROR_STATE; - if (HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE == dest_state) { - if (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING == pCfg_para->cfg_para_cmd_construct_state) + if (dest_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) { + if (pCfg_para->cfg_para_cmd_construct_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING) return HALMAC_RET_ERROR_STATE; - } else if (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING == dest_state) { - if (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT == pCfg_para->cfg_para_cmd_construct_state) + } else if (dest_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING) { + if (pCfg_para->cfg_para_cmd_construct_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT) return HALMAC_RET_ERROR_STATE; - } else if (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT == dest_state) { - if ((HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE == pCfg_para->cfg_para_cmd_construct_state) \ - || (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT == pCfg_para->cfg_para_cmd_construct_state)) + } else if (dest_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT) { + if ((pCfg_para->cfg_para_cmd_construct_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) + || (pCfg_para->cfg_para_cmd_construct_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT)) return HALMAC_RET_ERROR_STATE; } @@ -2845,25 +2872,25 @@ halmac_transition_scan_state_88xx( IN HALMAC_SCAN_CMD_CONSTRUCT_STATE dest_state ) { - PHALMAC_SCAN_STATE_SET pScan = &(pHalmac_adapter->halmac_state.scan_state_set); + PHALMAC_SCAN_STATE_SET pScan = &pHalmac_adapter->halmac_state.scan_state_set; - if ((pScan->scan_cmd_construct_state > HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) || (pScan->scan_cmd_construct_state < HALMAC_SCAN_CMD_CONSTRUCT_IDLE)) + if (pScan->scan_cmd_construct_state > HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) return HALMAC_RET_ERROR_STATE; - if (HALMAC_SCAN_CMD_CONSTRUCT_IDLE == dest_state) { - if ((HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED == pScan->scan_cmd_construct_state) || - (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING == pScan->scan_cmd_construct_state)) + if (dest_state == HALMAC_SCAN_CMD_CONSTRUCT_IDLE) { + if ((pScan->scan_cmd_construct_state == HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) || + (pScan->scan_cmd_construct_state == HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING)) return HALMAC_RET_ERROR_STATE; - } else if (HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED == dest_state) { - if (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == pScan->scan_cmd_construct_state) + } else if (dest_state == HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) { + if (pScan->scan_cmd_construct_state == HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) return HALMAC_RET_ERROR_STATE; - } else if (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING == dest_state) { - if ((HALMAC_SCAN_CMD_CONSTRUCT_IDLE == pScan->scan_cmd_construct_state) || - (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == pScan->scan_cmd_construct_state)) + } else if (dest_state == HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) { + if ((pScan->scan_cmd_construct_state == HALMAC_SCAN_CMD_CONSTRUCT_IDLE) || + (pScan->scan_cmd_construct_state == HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT)) return HALMAC_RET_ERROR_STATE; - } else if (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == dest_state) { - if ((HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != pScan->scan_cmd_construct_state) && - (HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED != pScan->scan_cmd_construct_state)) + } else if (dest_state == HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) { + if ((pScan->scan_cmd_construct_state != HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) && + (pScan->scan_cmd_construct_state != HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED)) return HALMAC_RET_ERROR_STATE; } @@ -2880,7 +2907,7 @@ halmac_query_cfg_para_status_88xx( INOUT u32 *size ) { - PHALMAC_CFG_PARA_STATE_SET pCfg_para_state_set = &(pHalmac_adapter->halmac_state.cfg_para_state_set); + PHALMAC_CFG_PARA_STATE_SET pCfg_para_state_set = &pHalmac_adapter->halmac_state.cfg_para_state_set; *pProcess_status = pCfg_para_state_set->process_status; @@ -2896,19 +2923,19 @@ halmac_query_dump_physical_efuse_status_88xx( ) { VOID *pDriver_adapter = NULL; - PHALMAC_EFUSE_STATE_SET pEfuse_state_set = &(pHalmac_adapter->halmac_state.efuse_state_set); + PHALMAC_EFUSE_STATE_SET pEfuse_state_set = &pHalmac_adapter->halmac_state.efuse_state_set; pDriver_adapter = pHalmac_adapter->pDriver_adapter; *pProcess_status = pEfuse_state_set->process_status; - if (NULL == data) + if (data == NULL) return HALMAC_RET_NULL_POINTER; - if (NULL == size) + if (size == NULL) return HALMAC_RET_NULL_POINTER; - if (HALMAC_CMD_PROCESS_DONE == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_DONE) { if (*size < pHalmac_adapter->hw_config_info.efuse_size) { *size = pHalmac_adapter->hw_config_info.efuse_size; return HALMAC_RET_BUFFER_TOO_SMALL; @@ -2932,38 +2959,42 @@ halmac_query_dump_logical_efuse_status_88xx( u8 *pEeprom_map = NULL; u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; VOID *pDriver_adapter = NULL; - PHALMAC_EFUSE_STATE_SET pEfuse_state_set = &(pHalmac_adapter->halmac_state.efuse_state_set); + PHALMAC_EFUSE_STATE_SET pEfuse_state_set = &pHalmac_adapter->halmac_state.efuse_state_set; pDriver_adapter = pHalmac_adapter->pDriver_adapter; *pProcess_status = pEfuse_state_set->process_status; - pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); - if (NULL == pEeprom_map) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); - - if (NULL == data) + if (data == NULL) return HALMAC_RET_NULL_POINTER; - if (NULL == size) + if (size == NULL) return HALMAC_RET_NULL_POINTER; - if (HALMAC_CMD_PROCESS_DONE == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_DONE) { if (*size < eeprom_size) { *size = eeprom_size; return HALMAC_RET_BUFFER_TOO_SMALL; } *size = eeprom_size; - if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map)) + + pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); + if (pEeprom_map == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); + + if (halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map) != HALMAC_RET_SUCCESS) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); return HALMAC_RET_EEPROM_PARSING_FAIL; + } + PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pEeprom_map, *size); - } - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + } return HALMAC_RET_SUCCESS; } @@ -2976,7 +3007,7 @@ halmac_query_channel_switch_status_88xx( INOUT u32 *size ) { - PHALMAC_SCAN_STATE_SET pScan_state_set = &(pHalmac_adapter->halmac_state.scan_state_set); + PHALMAC_SCAN_STATE_SET pScan_state_set = &pHalmac_adapter->halmac_state.scan_state_set; *pProcess_status = pScan_state_set->process_status; @@ -2991,7 +3022,7 @@ halmac_query_update_packet_status_88xx( INOUT u32 *size ) { - PHALMAC_UPDATE_PACKET_STATE_SET pUpdate_packet_set = &(pHalmac_adapter->halmac_state.update_packet_set); + PHALMAC_UPDATE_PACKET_STATE_SET pUpdate_packet_set = &pHalmac_adapter->halmac_state.update_packet_set; *pProcess_status = pUpdate_packet_set->process_status; @@ -3006,7 +3037,7 @@ halmac_query_iqk_status_88xx( INOUT u32 *size ) { - PHALMAC_IQK_STATE_SET pIqk_set = &(pHalmac_adapter->halmac_state.iqk_set); + PHALMAC_IQK_STATE_SET pIqk_set = &pHalmac_adapter->halmac_state.iqk_set; *pProcess_status = pIqk_set->process_status; @@ -3021,7 +3052,7 @@ halmac_query_power_tracking_status_88xx( INOUT u32 *size ) { - PHALMAC_POWER_TRACKING_STATE_SET pPower_tracking_state_set = &(pHalmac_adapter->halmac_state.power_tracking_set);; + PHALMAC_POWER_TRACKING_STATE_SET pPower_tracking_state_set = &pHalmac_adapter->halmac_state.power_tracking_set; *pProcess_status = pPower_tracking_state_set->process_status; @@ -3037,19 +3068,19 @@ halmac_query_psd_status_88xx( ) { VOID *pDriver_adapter = NULL; - PHALMAC_PSD_STATE_SET pPsd_set = &(pHalmac_adapter->halmac_state.psd_set); + PHALMAC_PSD_STATE_SET pPsd_set = &pHalmac_adapter->halmac_state.psd_set; pDriver_adapter = pHalmac_adapter->pDriver_adapter; *pProcess_status = pPsd_set->process_status; - if (NULL == data) + if (data == NULL) return HALMAC_RET_NULL_POINTER; - if (NULL == size) + if (size == NULL) return HALMAC_RET_NULL_POINTER; - if (HALMAC_CMD_PROCESS_DONE == *pProcess_status) { + if (*pProcess_status == HALMAC_CMD_PROCESS_DONE) { if (*size < pPsd_set->data_size) { *size = pPsd_set->data_size; return HALMAC_RET_BUFFER_TOO_SMALL; @@ -3075,12 +3106,12 @@ halmac_verify_io_88xx( pDriver_adapter = pHalmac_adapter->pDriver_adapter; - if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { halmac_offset = REG_PAGE5_DUMMY; if (0 == (halmac_offset & 0xFFFF0000)) halmac_offset |= WLAN_IOREG_OFFSET; - halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); + ret_status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); /* Verify CMD52 R/W */ wvalue8 = 0xab; @@ -3103,7 +3134,7 @@ halmac_verify_io_88xx( value32 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset); - if (0xddccbbaa != value32) { + if (value32 != 0xddccbbaa) { PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd53 r fail : read = %X\n"); ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; } else { @@ -3160,23 +3191,14 @@ halmac_verify_send_rsvd_page_88xx( u32 i; u32 h2c_pkt_verify_size = 64, h2c_pkt_verify_payload = 0xab; VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; rsvd_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, h2c_pkt_verify_size); - if (NULL == rsvd_buf) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "rsvd buffer malloc fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - - rsvd_page = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); - - if (NULL == rsvd_page) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "rsvd page malloc fail!!\n"); + if (rsvd_buf == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]rsvd buffer malloc fail!!\n"); return HALMAC_RET_MALLOC_FAIL; } @@ -3184,27 +3206,38 @@ halmac_verify_send_rsvd_page_88xx( ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, rsvd_buf, h2c_pkt_verify_size); - if (HALMAC_RET_SUCCESS != ret_status) + if (ret_status != HALMAC_RET_SUCCESS) { + PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size); return ret_status; + } + + rsvd_page = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); + + if (rsvd_page == NULL) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]rsvd page malloc fail!!\n"); + PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size); + return HALMAC_RET_MALLOC_FAIL; + } PLATFORM_RTL_MEMSET(pDriver_adapter, rsvd_page, 0x00, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); - ret_status = halmac_dump_fifo_88xx(pHalmac_adapter, HAL_FIFO_SEL_RSVD_PAGE, rsvd_page, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); + ret_status = halmac_dump_fifo_88xx(pHalmac_adapter, HAL_FIFO_SEL_RSVD_PAGE, 0, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size, rsvd_page); - if (HALMAC_RET_SUCCESS != ret_status) + if (ret_status != HALMAC_RET_SUCCESS) { + PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size); + PLATFORM_RTL_FREE(pDriver_adapter, rsvd_page, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); return ret_status; + } for (i = 0; i < h2c_pkt_verify_size; i++) { if (*(rsvd_buf + i) != *(rsvd_page + (i + pHalmac_adapter->hw_config_info.txdesc_size))) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Compare RSVD page Fail\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]Compare RSVD page Fail\n"); ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; } } PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size); PLATFORM_RTL_FREE(pDriver_adapter, rsvd_page, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); - rsvd_buf = NULL; - rsvd_page = NULL; return ret_status; } @@ -3238,24 +3271,28 @@ halmac_buffer_read_88xx( pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - if (HAL_FIFO_SEL_RSVD_PAGE == halmac_fifo_sel) - offset = offset + (pHalmac_adapter->txff_allocation.rsvd_pg_bndy << 7); + if (halmac_fifo_sel == HAL_FIFO_SEL_RSVD_PAGE) + offset = offset + (pHalmac_adapter->txff_allocation.rsvd_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_88XX); start_page = offset >> 12; residue = offset & (4096 - 1); - if ((HAL_FIFO_SEL_TX == halmac_fifo_sel) || (HAL_FIFO_SEL_RSVD_PAGE == halmac_fifo_sel)) + if ((halmac_fifo_sel == HAL_FIFO_SEL_TX) || (halmac_fifo_sel == HAL_FIFO_SEL_RSVD_PAGE)) start_page += 0x780; - else if (HAL_FIFO_SEL_RX == halmac_fifo_sel) + else if (halmac_fifo_sel == HAL_FIFO_SEL_RX) start_page += 0x700; - else if (HAL_FIFO_SEL_REPORT == halmac_fifo_sel) + else if (halmac_fifo_sel == HAL_FIFO_SEL_REPORT) start_page += 0x660; - else if (HAL_FIFO_SEL_LLT == halmac_fifo_sel) + else if (halmac_fifo_sel == HAL_FIFO_SEL_LLT) start_page += 0x650; + else if (halmac_fifo_sel == HAL_FIFO_SEL_RXBUF_FW) + start_page += 0x680; + else + return HALMAC_RET_NOT_SUPPORT; value_read = HALMAC_REG_READ_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL); - while (1) { + do { HALMAC_REG_WRITE_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL, (u16)(start_page | (value_read & 0xF000))); for (i = 0x8000 + residue; i <= 0x8FFF; i += 4) { @@ -3268,7 +3305,7 @@ halmac_buffer_read_88xx( residue = 0; start_page++; - } + } while (1); HALMAC_BUF_READ_OK: HALMAC_REG_WRITE_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL, (u16)value_read); @@ -3297,127 +3334,767 @@ halmac_restore_mac_register_88xx( mac_value = pCurr_restore_info->value; value_length = pCurr_restore_info->length; - if (1 == value_length) + if (value_length == 1) HALMAC_REG_WRITE_8(pHalmac_adapter, mac_register, (u8)mac_value); - else if (2 == value_length) + else if (value_length == 2) HALMAC_REG_WRITE_16(pHalmac_adapter, mac_register, (u16)mac_value); - else if (4 == value_length) + else if (value_length == 4) HALMAC_REG_WRITE_32(pHalmac_adapter, mac_register, mac_value); pCurr_restore_info++; } } +HALMAC_RET_STATUS +halmac_set_usb_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_USB_MODE usb_mode +) +{ + u32 usb_temp; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_USB_MODE current_usb_mode; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + current_usb_mode = (HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2 + 3) == 0x20) ? HALMAC_USB_MODE_U3 : HALMAC_USB_MODE_U2; + + /*check if HW supports usb2_usb3 swtich*/ + usb_temp = HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL2); + if (_FALSE == (BIT_GET_USB23_SW_MODE_V1(usb_temp) | (usb_temp & BIT_USB3_USB2_TRANSITION))) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "HALMAC_HW_USB_MODE usb mode HW unsupport\n"); + return HALMAC_RET_USB2_3_SWITCH_UNSUPPORT; + } + + if (usb_mode == current_usb_mode) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "HALMAC_HW_USB_MODE usb mode unchange\n"); + return HALMAC_RET_USB_MODE_UNCHANGE; + } + + usb_temp &= ~(BIT_USB23_SW_MODE_V1(0x3)); + + if (usb_mode == HALMAC_USB_MODE_U2) { + /* usb3 to usb2 */ + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U2) | BIT_RSM_EN_V1); + } else { + /* usb2 to usb3 */ + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U3) | BIT_RSM_EN_V1); + } + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PAD_CTRL2 + 1, 4); /* set counter down timer 4x64 ms */ + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_16(pHalmac_adapter, REG_SYS_PW_CTRL) | BIT_APFM_OFFMAC); + PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL2) | BIT_NO_PDN_CHIPOFF_V1); + + return HALMAC_RET_SUCCESS; +} + VOID -halmac_api_record_id_88xx( +halmac_enable_bb_rf_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_API_ID api_id + IN u8 enable ) { - u8 array_wptr_last; + u8 value8; + u32 value32; + PHALMAC_API pHalmac_api; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - array_wptr_last = pHalmac_adapter->api_record.array_wptr; + if (enable == 1) { + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN); + value8 = value8 | BIT(0) | BIT(1); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN, value8); - if (array_wptr_last == API_ARRAY_SIZE - 1) - array_wptr_last = 0; - else if (HALMAC_API_STUFF == pHalmac_adapter->api_record.api_array[0]) - array_wptr_last = array_wptr_last; - else - array_wptr_last = array_wptr_last + 1; + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RF_CTRL); + value8 = value8 | BIT(0) | BIT(1) | BIT(2); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RF_CTRL, value8); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WLRF1); + value32 = value32 | BIT(24) | BIT(25) | BIT(26); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WLRF1, value32); + } else { + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN); + value8 = value8 & (~(BIT(0) | BIT(1))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN, value8); - pHalmac_adapter->api_record.api_array[array_wptr_last] = api_id; - pHalmac_adapter->api_record.array_wptr = array_wptr_last; + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RF_CTRL); + value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RF_CTRL, value8); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WLRF1); + value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26))); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WLRF1, value32); + } } VOID -halmac_get_hcpwm_88xx( +halmac_config_sdio_tx_page_threshold_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u8 *pHcpwm + IN PHALMAC_TX_PAGE_THRESHOLD_INFO pThreshold_info ) { + VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - u32 hcpwm_offset = 0; + u32 threshold = pThreshold_info->threshold; + pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) - hcpwm_offset = REG_PCIE_HCPWM1_V1; - else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) - hcpwm_offset = 0xFE57; - else if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) - hcpwm_offset = REG_SDIO_HCPWM1_V2; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_config_sdio_tx_page_threshold_88xx ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]queue %d, threshold 0x%X\n", pThreshold_info->dma_queue_sel, threshold); + + if (pThreshold_info->enable == 1) { + threshold = BIT(31) | threshold; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]enable\n"); + } else { + threshold = ~(BIT(31)) & threshold; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]disable\n"); + } + + switch (pThreshold_info->dma_queue_sel) { + case HALMAC_MAP2_HQ: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT1, threshold); + break; + case HALMAC_MAP2_NQ: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT2, threshold); + break; + case HALMAC_MAP2_LQ: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT3, threshold); + break; + case HALMAC_MAP2_EXQ: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT4, threshold); + break; + default: + break; + } + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_config_sdio_tx_page_threshold_88xx <==========\n"); +} + +VOID +halmac_config_ampdu_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_AMPDU_CONFIG pAmpdu_config +) +{ + PHALMAC_API pHalmac_api; - *pHcpwm = HALMAC_REG_READ_8(pHalmac_adapter, hcpwm_offset); + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PROT_MODE_CTRL + 2, pAmpdu_config->max_agg_num); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PROT_MODE_CTRL + 3, pAmpdu_config->max_agg_num); } VOID -halmac_get_hcpwm2_88xx( +halmac_rx_shift_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 enable +) +{ + PHALMAC_API pHalmac_api; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (enable == 1) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP, HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP) | BIT(1)); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP, HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP) & ~(BIT(1))); +} + +HALMAC_RET_STATUS +halmac_check_oqt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 tx_agg_num, + IN u8 *pHalmac_buf, + IN u8 macid_counter +) +{ + u32 counter = 10; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + /*S0, S1 are not allowed to use, 0x4E4[0] should be 0. Soar 20160323*/ + /*no need to check non_ac_oqt_number. HI and MGQ blocked will cause protocal issue before H_OQT being full*/ + switch ((HALMAC_QUEUE_SELECT)GET_TX_DESC_QSEL(pHalmac_buf)) { + case HALMAC_QUEUE_SELECT_VO: + case HALMAC_QUEUE_SELECT_VO_V2: + case HALMAC_QUEUE_SELECT_VI: + case HALMAC_QUEUE_SELECT_VI_V2: + case HALMAC_QUEUE_SELECT_BE: + case HALMAC_QUEUE_SELECT_BE_V2: + case HALMAC_QUEUE_SELECT_BK: + case HALMAC_QUEUE_SELECT_BK_V2: + if (tx_agg_num > HALMAC_OQT_ENTRY_AC_88XX) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_WARN, "tx_agg_num %d > HALMAC_OQT_ENTRY_AC_88XX %d\n", tx_agg_num, HALMAC_OQT_ENTRY_AC_88XX); + counter = 10; + do { + if (pHalmac_adapter->sdio_free_space.ac_empty >= macid_counter) { + pHalmac_adapter->sdio_free_space.ac_empty -= macid_counter; + break; + } + + if (pHalmac_adapter->sdio_free_space.ac_oqt_number >= tx_agg_num) { + pHalmac_adapter->sdio_free_space.ac_empty = 0; + pHalmac_adapter->sdio_free_space.ac_oqt_number -= (u8)tx_agg_num; + break; + } + + halmac_update_oqt_free_space_88xx(pHalmac_adapter); + + counter--; + if (counter == 0) + return HALMAC_RET_OQT_NOT_ENOUGH; + } while (1); + break; + case HALMAC_QUEUE_SELECT_MGNT: + case HALMAC_QUEUE_SELECT_HIGH: + if (tx_agg_num > HALMAC_OQT_ENTRY_NOAC_88XX) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_WARN, "tx_agg_num %d > HALMAC_OQT_ENTRY_NOAC_88XX %d\n", tx_agg_num, HALMAC_OQT_ENTRY_NOAC_88XX); + counter = 10; + do { + if (pHalmac_adapter->sdio_free_space.non_ac_oqt_number >= tx_agg_num) { + pHalmac_adapter->sdio_free_space.non_ac_oqt_number -= (u8)tx_agg_num; + break; + } + + halmac_update_oqt_free_space_88xx(pHalmac_adapter); + + counter--; + if (counter == 0) + return HALMAC_RET_OQT_NOT_ENOUGH; + } while (1); + break; + default: + break; + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_rqpn_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode, + IN PHALMAC_RQPN pRqpn_table +) +{ + u8 search_flag; + u32 i; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + search_flag = 0; + for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) { + if (halmac_trx_mode == pRqpn_table[i].mode) { + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = pRqpn_table[i].dma_map_vo; + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = pRqpn_table[i].dma_map_vi; + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = pRqpn_table[i].dma_map_be; + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = pRqpn_table[i].dma_map_bk; + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = pRqpn_table[i].dma_map_mg; + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = pRqpn_table[i].dma_map_hi; + search_flag = 1; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_rqpn_parser_88xx done\n"); + break; + } + } + + if (search_flag == 0) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_RET_TRX_MODE_NOT_SUPPORT 1 switch case not support\n"); + return HALMAC_RET_TRX_MODE_NOT_SUPPORT; + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_pg_num_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode, + IN PHALMAC_PG_NUM pPg_num_table +) +{ + u8 search_flag; + u16 HPQ_num = 0, LPQ_Nnum = 0, NPQ_num = 0, GAPQ_num = 0; + u16 EXPQ_num = 0, PUBQ_num = 0; + u32 i = 0; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + search_flag = 0; + for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) { + if (halmac_trx_mode == pPg_num_table[i].mode) { + HPQ_num = pPg_num_table[i].hq_num; + LPQ_Nnum = pPg_num_table[i].lq_num; + NPQ_num = pPg_num_table[i].nq_num; + EXPQ_num = pPg_num_table[i].exq_num; + GAPQ_num = pPg_num_table[i].gap_num; + PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num; + search_flag = 1; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pg_num_parser_88xx done\n"); + break; + } + } + + if (search_flag == 0) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_RET_TRX_MODE_NOT_SUPPORT 1 switch case not support\n"); + return HALMAC_RET_TRX_MODE_NOT_SUPPORT; + } + + if (pHalmac_adapter->txff_allocation.ac_q_pg_num < HPQ_num + LPQ_Nnum + NPQ_num + EXPQ_num + GAPQ_num) + return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL; + + pHalmac_adapter->txff_allocation.high_queue_pg_num = HPQ_num; + pHalmac_adapter->txff_allocation.low_queue_pg_num = LPQ_Nnum; + pHalmac_adapter->txff_allocation.normal_queue_pg_num = NPQ_num; + pHalmac_adapter->txff_allocation.extra_queue_pg_num = EXPQ_num; + pHalmac_adapter->txff_allocation.pub_queue_pg_num = PUBQ_num; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_intf_phy_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u16 *pHcpwm2 + IN PHALMAC_INTF_PHY_PARA pIntf_phy_para, + IN HALMAC_INTF_PHY_PLATFORM platform, + IN HAL_INTF_PHY intf_phy ) { + u16 value; + u16 curr_cut; + u16 offset; + u16 ip_sel; + PHALMAC_INTF_PHY_PARA pCurr_phy_para; PHALMAC_API pHalmac_api; - u32 hcpwm2_offset = 0; + VOID *pDriver_adapter = NULL; + u8 result = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + switch (pHalmac_adapter->chip_version) { + case HALMAC_CHIP_VER_A_CUT: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_A; + break; + case HALMAC_CHIP_VER_B_CUT: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_B; + break; + case HALMAC_CHIP_VER_C_CUT: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_C; + break; + case HALMAC_CHIP_VER_D_CUT: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_D; + break; + case HALMAC_CHIP_VER_E_CUT: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_E; + break; + case HALMAC_CHIP_VER_F_CUT: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_F; + break; + case HALMAC_CHIP_VER_TEST: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_TESTCHIP; + break; + default: + return HALMAC_RET_FAIL; + } + + pCurr_phy_para = pIntf_phy_para; + + do { + if ((pCurr_phy_para->cut & curr_cut) && (pCurr_phy_para->plaform & (u16)platform)) { + offset = pCurr_phy_para->offset; + value = pCurr_phy_para->value; + ip_sel = pCurr_phy_para->ip_sel; + + if (offset == 0xFFFF) + break; + + if (ip_sel == HALMAC_IP_SEL_MAC) { + HALMAC_REG_WRITE_8(pHalmac_adapter, (u32)offset, (u8)value); + } else if (intf_phy == HAL_INTF_PHY_USB2) { + result = halmac_usbphy_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_USB2); + + if (result != HALMAC_RET_SUCCESS) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Write USB2PHY fail!\n"); + + } else if (intf_phy == HAL_INTF_PHY_USB3) { + result = halmac_usbphy_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_USB3); + + if (result != HALMAC_RET_SUCCESS) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Write USB3PHY fail!\n"); + + } else if (intf_phy == HAL_INTF_PHY_PCIE_GEN1) { + if (ip_sel == HALMAC_IP_SEL_INTF_PHY) + result = halmac_mdio_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_PCIE_GEN1); + else + result = halmac_dbi_write8_88xx(pHalmac_adapter, offset, (u8)value); + + if (result != HALMAC_RET_SUCCESS) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "[ERR]MDIO write GEN1 fail!\n"); + } else if (intf_phy == HAL_INTF_PHY_PCIE_GEN2) { + if (ip_sel == HALMAC_IP_SEL_INTF_PHY) + result = halmac_mdio_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_PCIE_GEN2); + else + result = halmac_dbi_write8_88xx(pHalmac_adapter, offset, (u8)value); + + if (result != HALMAC_RET_SUCCESS) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "[ERR]MDIO write GEN2 fail!\n"); + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]Parse intf phy cfg error!\n"); + } + } + pCurr_phy_para++; + } while (1); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_dbi_write32_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 addr, + IN u32 data +) +{ + u8 tmp_u1b = 0; + u32 count = 0; + u16 write_addr = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) - hcpwm2_offset = REG_PCIE_HCPWM2_V1; - else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) - hcpwm2_offset = 0xFE34; - else if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) - hcpwm2_offset = REG_SDIO_HCPWM2_V2; + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DBI_WDATA_V1, data); + + write_addr = ((addr & 0x0ffc) | (0x000F << 12)); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, write_addr); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "[TRACE]WriteAddr = %x\n", write_addr); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x01); + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); - *pHcpwm2 = HALMAC_REG_READ_16(pHalmac_adapter, hcpwm2_offset); + count = 20; + while (tmp_u1b && (count != 0)) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); + count--; + } + + if (tmp_u1b) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "[ERR]DBI write fail!\n"); + return HALMAC_RET_FAIL; + } + + return HALMAC_RET_SUCCESS; } -VOID -halmac_set_hrpwm_88xx( +u32 +halmac_dbi_read32_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 addr +) +{ + u16 read_addr = addr & 0x0ffc; + u8 tmp_u1b = 0; + u32 count = 0; + u32 ret = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, read_addr); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x2); + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); + + count = 20; + while (tmp_u1b && (count != 0)) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); + count--; + } + + if (tmp_u1b) { + ret = 0xFFFF; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "[ERR]DBI read fail!\n"); + } else { + ret = HALMAC_REG_READ_32(pHalmac_adapter, REG_DBI_RDATA_V1); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "[TRACE]Read Value = %x\n", ret); + } + + return ret; +} + +HALMAC_RET_STATUS +halmac_dbi_write8_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 hrpwm + IN u16 addr, + IN u8 data ) { + u8 tmp_u1b = 0; + u32 count = 0; + u16 write_addr = 0; + u16 remainder = addr & (4 - 1); + VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - u32 hrpwm_offset = 0; - u8 hrpwm_original = 0; + pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) - hrpwm_offset = REG_PCIE_HRPWM1_V1; - else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) - hrpwm_offset = 0xFE58; - else if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) - hrpwm_offset = REG_SDIO_HRPWM1; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_WDATA_V1 + remainder, data); + + write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12))); - hrpwm_original = HALMAC_REG_READ_8(pHalmac_adapter, hrpwm_offset); - hrpwm = (hrpwm & 0x7F) | ((~hrpwm_original) & 0x80); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, write_addr); - HALMAC_REG_WRITE_8(pHalmac_adapter, hrpwm_offset, hrpwm); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "[TRACE]WriteAddr = %x\n", write_addr); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x01); + + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); + + count = 20; + while (tmp_u1b && (count != 0)) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); + count--; + } + + if (tmp_u1b) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "[ERR]DBI write fail!\n"); + return HALMAC_RET_FAIL; + } + + return HALMAC_RET_SUCCESS; } -VOID -halmac_set_hrpwm2_88xx( +u8 +halmac_dbi_read8_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 addr +) +{ + u16 read_addr = addr & 0x0ffc; + u8 tmp_u1b = 0; + u32 count = 0; + u8 ret = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, read_addr); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x2); + + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); + + count = 20; + while (tmp_u1b && (count != 0)) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); + count--; + } + + if (tmp_u1b) { + ret = 0xFF; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "[ERR]DBI read fail!\n"); + } else { + ret = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_RDATA_V1 + (addr & (4 - 1))); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "[TRACE]Read Value = %x\n", ret); + } + + return ret; +} + +HALMAC_RET_STATUS +halmac_mdio_write_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u16 data, + IN u8 speed +) +{ + u8 tmp_u1b = 0; + u32 count = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + u8 real_addr = 0; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MDIO_V1, data); + + real_addr = (addr & 0x1F); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, real_addr); + + if (speed == HAL_INTF_PHY_PCIE_GEN1) { + if (addr < 0x20) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x00); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x01); + } else if (speed == HAL_INTF_PHY_PCIE_GEN2) { + if (addr < 0x20) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x02); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x03); + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "Error Speed !\n"); + } + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) | BIT_MDIO_WFLAG_V1); + + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1; + count = 20; + + while (tmp_u1b && (count != 0)) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1; + count--; + } + + if (tmp_u1b) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "MDIO write fail!\n"); + return HALMAC_RET_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +u16 +halmac_mdio_read_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u8 speed + +) +{ + u16 ret = 0; + u8 tmp_u1b = 0; + u32 count = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + u8 real_addr = 0; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + real_addr = (addr & 0x1F); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, real_addr); + + if (speed == HAL_INTF_PHY_PCIE_GEN1) { + if (addr < 0x20) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x00); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x01); + } else if (speed == HAL_INTF_PHY_PCIE_GEN2) { + if (addr < 0x20) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x02); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x03); + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "Error Speed !\n"); + } + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) | BIT_MDIO_RFLAG_V1); + + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1; + count = 20; + + while (tmp_u1b && (count != 0)) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1; + count--; + } + + if (tmp_u1b) { + ret = 0xFFFF; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "MDIO read fail!\n"); + } else { + ret = HALMAC_REG_READ_16(pHalmac_adapter, REG_MDIO_V1 + 2); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_TRACE, "Read Value = %x\n", ret); + } + + return ret; +} + +HALMAC_RET_STATUS +halmac_usbphy_write_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN u16 hrpwm2 + IN u8 addr, + IN u16 data, + IN u8 speed ) { + VOID *pDriver_adapter = NULL; PHALMAC_API pHalmac_api; - u32 hrpwm2_offset = 0; - u16 hrpwm2_original = 0; + pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) - hrpwm2_offset = REG_PCIE_HRPWM2_V1; - else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) - hrpwm2_offset = 0xFE36; - else if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) - hrpwm2_offset = REG_SDIO_HRPWM2; + if (speed == HAL_INTF_PHY_USB3) { + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0d, (u8)data); + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0e, (u8)(data >> 8)); + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0c, addr | BIT(7)); + } else if (speed == HAL_INTF_PHY_USB2) { + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe41, (u8)data); + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe40, addr); + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe42, 0x81); + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Error USB Speed !\n"); + return HALMAC_RET_NOT_SUPPORT; + } - hrpwm2_original = HALMAC_REG_READ_16(pHalmac_adapter, hrpwm2_offset); - hrpwm2 = (hrpwm2 & 0x7FFF) | ((~hrpwm2_original) & 0x8000); + return HALMAC_RET_SUCCESS; +} - HALMAC_REG_WRITE_16(pHalmac_adapter, hrpwm2_offset, hrpwm2); +u16 +halmac_usbphy_read_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u8 speed +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + u16 value = 0; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (speed == HAL_INTF_PHY_USB3) { + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0c, addr | BIT(6)); + value = (u16)(HALMAC_REG_READ_32(pHalmac_adapter, 0xff0c) >> 8); + } else if (speed == HAL_INTF_PHY_USB2) { + if ((addr >= 0xE0) && (addr <= 0xFF)) + addr -= 0x20; + if ((addr >= 0xC0) && (addr <= 0xDF)) { + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe40, addr); + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe42, 0x81); + value = HALMAC_REG_READ_8(pHalmac_adapter, 0xfe43); + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Error USB2PHY offset!\n"); + return HALMAC_RET_NOT_SUPPORT; + } + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Error USB Speed !\n"); + return HALMAC_RET_NOT_SUPPORT; + } + + return value; } + diff --git a/hal/halmac/halmac_88xx/halmac_func_88xx.h b/hal/halmac/halmac_88xx/halmac_func_88xx.h index b085ed7..51bf8c0 100644 --- a/hal/halmac/halmac_88xx/halmac_func_88xx.h +++ b/hal/halmac/halmac_88xx/halmac_func_88xx.h @@ -1,8 +1,27 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_FUNC_88XX_H_ #define _HALMAC_FUNC_88XX_H_ #include "../halmac_type.h" +VOID +halmac_init_offload_feature_state_machine_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); HALMAC_RET_STATUS halmac_send_h2c_pkt_88xx( @@ -97,6 +116,13 @@ halmac_read_hw_efuse_88xx( OUT u8 *pEfuse_map ); +HALMAC_RET_STATUS +halmac_update_fw_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHamacl_fw, + IN u32 halmac_fw_size +); + HALMAC_RET_STATUS halmac_dlfw_to_mem_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -132,13 +158,19 @@ halmac_dlfw_end_flow_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ); +HALMAC_RET_STATUS +halmac_free_dl_fw_end_flow_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + HALMAC_RET_STATUS halmac_pwr_seq_parser_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 CUT, - IN u8 FAB, - IN u8 INTF, - IN PHALMAC_WLAN_PWR_CFG PWR_SEQ_CFG + IN u8 cut, + IN u8 fab, + IN u8 intf, + IN PHALMAC_WLAN_PWR_CFG *ppPwr_seq_cfg + ); HALMAC_RET_STATUS @@ -146,12 +178,6 @@ halmac_get_h2c_buff_free_space_88xx( IN PHALMAC_ADAPTER pHalmac_adapter ); -HALMAC_RET_STATUS -halmac_send_h2c_set_pwr_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_FWLPS_OPTION pHal_FwLps_Opt -); - HALMAC_RET_STATUS halmac_func_send_original_h2c_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -160,15 +186,6 @@ halmac_func_send_original_h2c_88xx( IN u8 ack ); -HALMAC_RET_STATUS -halmac_media_status_rpt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 op_mode, - IN u8 mac_id_ind, - IN u8 mac_id, - IN u8 mac_id_end -); - HALMAC_RET_STATUS halmac_send_h2c_update_datapack_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, @@ -387,34 +404,120 @@ halmac_restore_mac_register_88xx( IN u32 restore_num ); -VOID -halmac_api_record_id_88xx( +HALMAC_RET_STATUS +halmac_set_usb_mode_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_API_ID api_id + IN HALMAC_USB_MODE usb_mode ); VOID -halmac_get_hcpwm_88xx( +halmac_enable_bb_rf_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u8 *pHcpwm + IN u8 enable ); VOID -halmac_get_hcpwm2_88xx( +halmac_config_sdio_tx_page_threshold_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u16 *pHcpwm2 + IN PHALMAC_TX_PAGE_THRESHOLD_INFO pThreshold_info +); + +HALMAC_RET_STATUS +halmac_rqpn_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode, + IN PHALMAC_RQPN pPwr_seq_cfg +); + +HALMAC_RET_STATUS +halmac_check_oqt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 tx_agg_num, + IN u8 *pHalmac_buf, + IN u8 macid_counter +); + +HALMAC_RET_STATUS +halmac_pg_num_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode, + IN PHALMAC_PG_NUM pPg_num_table +); + +HALMAC_RET_STATUS +halmac_parse_intf_phy_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_INTF_PHY_PARA pIntf_phy_para, + IN HALMAC_INTF_PHY_PLATFORM platform, + IN HAL_INTF_PHY intf_phy +); + +HALMAC_RET_STATUS +halmac_dbi_write32_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 addr, + IN u32 data +); + +u32 +halmac_dbi_read32_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 addr +); + +HALMAC_RET_STATUS +halmac_dbi_write8_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 addr, + IN u8 data +); + +u8 +halmac_dbi_read8_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 addr +); + +u16 +halmac_mdio_read_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u8 speed + +); + +HALMAC_RET_STATUS +halmac_mdio_write_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u16 data, + IN u8 speed ); VOID -halmac_set_hrpwm_88xx( +halmac_config_ampdu_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 hrpwm + IN PHALMAC_AMPDU_CONFIG pAmpdu_config ); VOID -halmac_set_hrpwm2_88xx( +halmac_rx_shift_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 enable +); + +HALMAC_RET_STATUS +halmac_usbphy_write_88xx( IN PHALMAC_ADAPTER pHalmac_adapter, - IN u16 hrpwm2 + IN u8 addr, + IN u16 data, + IN u8 speed ); +u16 +halmac_usbphy_read_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u8 speed +); #endif /* _HALMAC_FUNC_88XX_H_ */ diff --git a/hal/halmac/halmac_api.c b/hal/halmac/halmac_api.c index 93b7b48..ac367d2 100644 --- a/hal/halmac/halmac_api.c +++ b/hal/halmac/halmac_api.c @@ -1,37 +1,87 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "halmac_2_platform.h" #include "halmac_type.h" #if HALMAC_PLATFORM_WINDOWS == 1 +#if HALMAC_8822B_SUPPORT #include "halmac_88xx/halmac_api_win8822b.h" #include "halmac_88xx/halmac_win8822b_cfg.h" +#endif +#if HALMAC_8821C_SUPPORT #include "halmac_88xx/halmac_api_win8821c.h" #include "halmac_88xx/halmac_win8821c_cfg.h" -#include "halmac_88xx/halmac_api_win8197f.h" -#include "halmac_88xx/halmac_win8197f_cfg.h" +#endif + #else #include "halmac_88xx/halmac_api_88xx.h" #include "halmac_88xx/halmac_88xx_cfg.h" #endif + +#if HALMAC_8822B_SUPPORT #include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h" +#endif +#if HALMAC_8821C_SUPPORT #include "halmac_88xx/halmac_8821c/halmac_8821c_cfg.h" -#include "halmac_88xx/halmac_8197f/halmac_8197f_cfg.h" - +#endif -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_check_platform_api( IN VOID *pDriver_adapter, IN HALMAC_INTERFACE halmac_interface, IN PHALMAC_PLATFORM_API pHalmac_platform_api ); +static HALMAC_RET_STATUS +halmac_get_chip_info( + IN VOID *pDriver_adapter, + IN PHALMAC_PLATFORM_API pHalmac_platform_api, + IN HALMAC_INTERFACE halmac_interface, + IN PHALMAC_ADAPTER pHalmac_adapter +); + +static u8 +platform_reg_read_8_sdio( + IN VOID *pDriver_adapter, + IN PHALMAC_PLATFORM_API pHalmac_platform_api, + IN u32 offset +); + +static HALMAC_RET_STATUS +plarform_reg_write_8_sdio( + IN VOID *pDriver_adapter, + IN PHALMAC_PLATFORM_API pHalmac_platform_api, + IN u32 offset, + IN u8 data +); + +static HALMAC_RET_STATUS +halmac_convert_to_sdio_bus_offset( + INOUT u32 *halmac_offset +); + /** * halmac_init_adapter() - init halmac_adapter - * @pDriver_adapter - * @pHalmac_platform_api : platform api for halmac used - * @halmac_interface : PCIE, USB, or SDIO - * @ppHalmac_adapter - * @ppHalmac_api - * Author : KaiYuan Chang + * @pDriver_adapter : the adapter of caller + * @pHalmac_platform_api : the platform APIs which is used in halmac APIs + * @halmac_interface : bus interface + * @ppHalmac_adapter : the adapter of halmac + * @ppHalmac_api : the function pointer of APIs, caller shall call APIs by function pointer + * Author : KaiYuan Chang / Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_init_adapter( @@ -44,10 +94,10 @@ halmac_init_adapter( { PHALMAC_ADAPTER pHalmac_adapter = (PHALMAC_ADAPTER)NULL; HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + u8 *pBuf = NULL; #if HALMAC_PLATFORM_WINDOWS == 1 u8 chip_id = 0; - u32 polling_count; #endif union { u32 i; @@ -55,27 +105,30 @@ halmac_init_adapter( } ENDIAN_CHECK = { 0x01000000 }; status = halmac_check_platform_api(pDriver_adapter, halmac_interface, pHalmac_platform_api); - if (HALMAC_RET_SUCCESS != status) + if (status != HALMAC_RET_SUCCESS) return status; - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, HALMAC_SVN_VER "\n"); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_MAJOR_VER = %x\n", HALMAC_MAJOR_VER); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_PROTOTYPE_VER = %x\n", HALMAC_PROTOTYPE_VER); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_MINOR_VER = %x\n", HALMAC_MINOR_VER); + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, HALMAC_SVN_VER "\n"); + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MAJOR_VER = %x\n", HALMAC_MAJOR_VER); + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PROTOTYPE_VER = %x\n", HALMAC_PROTOTYPE_VER); + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MINOR_VER = %x\n", HALMAC_MINOR_VER); + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PATCH_VER = %x\n", HALMAC_PATCH_VER); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_adapter_88xx ==========>\n"); + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_adapter_88xx ==========>\n"); /* Check endian setting - Little endian : 1, Big endian : 0*/ - if (HALMAC_SYSTEM_ENDIAN == ENDIAN_CHECK.x[0]) { + if (ENDIAN_CHECK.x[0] == HALMAC_SYSTEM_ENDIAN) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Endian setting Err!!\n"); - pHalmac_adapter = (PHALMAC_ADAPTER)NULL; return HALMAC_RET_ENDIAN_ERR; } - pHalmac_adapter = (PHALMAC_ADAPTER)pHalmac_platform_api->RTL_MALLOC(pDriver_adapter, sizeof(HALMAC_ADAPTER)); - if (NULL == pHalmac_adapter) { + pBuf = (u8 *)pHalmac_platform_api->RTL_MALLOC(pDriver_adapter, sizeof(HALMAC_ADAPTER)); + + if (pBuf == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Malloc HAL Adapter Err!!\n"); return HALMAC_RET_MALLOC_FAIL; } + pHalmac_platform_api->RTL_MEMSET(pDriver_adapter, pBuf, 0x00, sizeof(HALMAC_ADAPTER)); + pHalmac_adapter = (PHALMAC_ADAPTER)pBuf; /* return halmac adapter address to caller */ *ppHalmac_adapter = pHalmac_adapter; @@ -83,68 +136,53 @@ halmac_init_adapter( /* Record caller info */ pHalmac_adapter->pHalmac_platform_api = pHalmac_platform_api; pHalmac_adapter->pDriver_adapter = pDriver_adapter; + halmac_interface = (halmac_interface == HALMAC_INTERFACE_AXI) ? HALMAC_INTERFACE_PCIE : halmac_interface; pHalmac_adapter->halmac_interface = halmac_interface; - PLATFORM_MUTEX_INIT(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); - PLATFORM_MUTEX_INIT(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + PLATFORM_MUTEX_INIT(pDriver_adapter, &pHalmac_adapter->EfuseMutex); + PLATFORM_MUTEX_INIT(pDriver_adapter, &pHalmac_adapter->h2c_seq_mutex); + + /*Get Chip*/ + if (halmac_get_chip_info(pDriver_adapter, pHalmac_platform_api, halmac_interface, pHalmac_adapter) != HALMAC_RET_SUCCESS) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_RET_CHIP_NOT_SUPPORT\n"); + return HALMAC_RET_CHIP_NOT_SUPPORT; + } /* Assign function pointer to halmac API */ #if HALMAC_PLATFORM_WINDOWS == 0 halmac_init_adapter_para_88xx(pHalmac_adapter); status = halmac_mount_api_88xx(pHalmac_adapter); #else - /* Get Chip_id and Chip_version */ - if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { - chip_id = pHalmac_platform_api->SDIO_CMD52_READ(pDriver_adapter, REG_SYS_CFG2); - if (chip_id == 0xEA) - pHalmac_platform_api->SDIO_CMD52_WRITE(pDriver_adapter, REG_SDIO_HSUS_CTRL, pHalmac_platform_api->SDIO_CMD52_READ(pHalmac_adapter, REG_SDIO_HSUS_CTRL) & ~(BIT(0))); - - polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT; - while (!(pHalmac_platform_api->SDIO_CMD52_READ(pDriver_adapter, REG_SDIO_HSUS_CTRL) & 0x02)) { - polling_count--; - if (polling_count == 0) - return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL; - } - - chip_id = pHalmac_platform_api->SDIO_CMD52_READ(pDriver_adapter, REG_SYS_CFG2); - } else { - chip_id = pHalmac_platform_api->REG_READ_8(pDriver_adapter, REG_SYS_CFG2); - } #if HALMAC_8822B_SUPPORT - if (HALMAC_CHIP_ID_HW_DEF_8822B == chip_id) { + if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8822B) { halmac_init_adapter_para_win8822b(pHalmac_adapter); status = halmac_mount_api_win8822b(pHalmac_adapter); } #endif #if HALMAC_8821C_SUPPORT - if (HALMAC_CHIP_ID_HW_DEF_8821C == chip_id) { + if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) { halmac_init_adapter_para_win8821c(pHalmac_adapter); status = halmac_mount_api_win8821c(pHalmac_adapter); } #endif -#if HALMAC_8197F_SUPPORT - if (HALMAC_CHIP_ID_HW_DEF_8197F == chip_id) { - halmac_init_adapter_para_win8197f(pHalmac_adapter); - status = halmac_mount_api_win8197f(pHalmac_adapter); - } -#endif #endif /* Return halmac API function pointer */ *ppHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_adapter_88xx <==========\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_adapter_88xx <==========\n"); return status; } /** - * halmac_halt_api() - halt all halmac api - * @pHalmac_adapter + * halmac_halt_api() - stop halmac_api action + * @pHalmac_adapter : the adapter of halmac * Author : Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_halt_api( @@ -154,23 +192,24 @@ halmac_halt_api( VOID *pDriver_adapter = NULL; PHALMAC_PLATFORM_API pHalmac_platform_api = (PHALMAC_PLATFORM_API)NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; pHalmac_platform_api = pHalmac_adapter->pHalmac_platform_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_halt_api ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_halt_api ==========>\n"); pHalmac_adapter->halmac_state.api_state = HALMAC_API_STATE_HALT; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_halt_api ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_halt_api ==========>\n"); return HALMAC_RET_SUCCESS; } /** * halmac_deinit_adapter() - deinit halmac adapter - * @pHalmac_adapter - * Author : KaiYuan Chang + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang / Ivan Lin * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document */ HALMAC_RET_STATUS halmac_deinit_adapter( @@ -178,169 +217,156 @@ halmac_deinit_adapter( ) { VOID *pDriver_adapter = NULL; - PHALMAC_PLATFORM_API pHalmac_platform_api = (PHALMAC_PLATFORM_API)NULL; - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) return HALMAC_RET_ADAPTER_INVALID; pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_platform_api = pHalmac_adapter->pHalmac_platform_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_deinit_adapter_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_deinit_adapter_88xx ==========>\n"); - PLATFORM_MUTEX_DEINIT(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); - PLATFORM_MUTEX_DEINIT(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + PLATFORM_MUTEX_DEINIT(pDriver_adapter, &pHalmac_adapter->EfuseMutex); + PLATFORM_MUTEX_DEINIT(pDriver_adapter, &pHalmac_adapter->h2c_seq_mutex); - if (NULL != pHalmac_adapter->pHalEfuse_map) { + if (pHalmac_adapter->pHalEfuse_map != NULL) { PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size); pHalmac_adapter->pHalEfuse_map = (u8 *)NULL; } - if (NULL != pHalmac_adapter->halmac_state.psd_set.pData) { + if (pHalmac_adapter->halmac_state.psd_set.pData != NULL) { PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->halmac_state.psd_set.pData, pHalmac_adapter->halmac_state.psd_set.data_size); pHalmac_adapter->halmac_state.psd_set.pData = (u8 *)NULL; } - if (NULL != pHalmac_adapter->pHalmac_api) { + if (pHalmac_adapter->pHalmac_api != NULL) { PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->pHalmac_api, sizeof(HALMAC_API)); pHalmac_adapter->pHalmac_api = NULL; } - if (NULL != pHalmac_adapter) { - pHalmac_adapter->pHalAdapter_backup = NULL; - PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter, sizeof(HALMAC_ADAPTER)); - pHalmac_adapter = (PHALMAC_ADAPTER)NULL; - } + pHalmac_adapter->pHalAdapter_backup = NULL; + PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter, sizeof(HALMAC_ADAPTER)); return HALMAC_RET_SUCCESS; } -/** - * halmac_check_platform_api() - check platform api pointers - * @pDriver_adapter - * @halmac_interface : PCIE, USB or SDIO - * @pHalmac_platform_api - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - */ -HALMAC_RET_STATUS +static HALMAC_RET_STATUS halmac_check_platform_api( IN VOID *pDriver_adapter, IN HALMAC_INTERFACE halmac_interface, IN PHALMAC_PLATFORM_API pHalmac_platform_api ) { - VOID *pAdapter_Local = NULL; - - pAdapter_Local = pDriver_adapter; - - if (NULL == pHalmac_platform_api) + if (pHalmac_platform_api == NULL) return HALMAC_RET_PLATFORM_API_NULL; - if (NULL == pHalmac_platform_api->MSG_PRINT) + if (pHalmac_platform_api->MSG_PRINT == NULL) return HALMAC_RET_PLATFORM_API_NULL; - if (HALMAC_INTERFACE_SDIO == halmac_interface) { - if (NULL == pHalmac_platform_api->SDIO_CMD52_READ) { + if (halmac_interface == HALMAC_INTERFACE_SDIO) { + if (pHalmac_platform_api->SDIO_CMD52_READ == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD52_READ)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_8) { + if (pHalmac_platform_api->SDIO_CMD53_READ_8 == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_8)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_16) { + if (pHalmac_platform_api->SDIO_CMD53_READ_16 == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_16)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_32) { + if (pHalmac_platform_api->SDIO_CMD53_READ_32 == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_32)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD52_WRITE) { + if (pHalmac_platform_api->SDIO_CMD53_READ_N == NULL) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_N)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (pHalmac_platform_api->SDIO_CMD52_WRITE == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD52_WRITE)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_WRITE_8) { + if (pHalmac_platform_api->SDIO_CMD53_WRITE_8 == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_8)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_WRITE_16) { + if (pHalmac_platform_api->SDIO_CMD53_WRITE_16 == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_16)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_WRITE_32) { + if (pHalmac_platform_api->SDIO_CMD53_WRITE_32 == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_32)\n"); return HALMAC_RET_PLATFORM_API_NULL; } } - if ((HALMAC_INTERFACE_USB == halmac_interface) || (HALMAC_INTERFACE_PCIE == halmac_interface)) { - if (NULL == pHalmac_platform_api->REG_READ_8) { + if ((halmac_interface == HALMAC_INTERFACE_USB) || (halmac_interface == HALMAC_INTERFACE_PCIE)) { + if (pHalmac_platform_api->REG_READ_8 == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_8)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->REG_READ_16) { + if (pHalmac_platform_api->REG_READ_16 == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_16)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->REG_READ_32) { + if (pHalmac_platform_api->REG_READ_32 == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_32)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->REG_WRITE_8) { + if (pHalmac_platform_api->REG_WRITE_8 == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_8)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->REG_WRITE_16) { + if (pHalmac_platform_api->REG_WRITE_16 == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_16)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->REG_WRITE_32) { + if (pHalmac_platform_api->REG_WRITE_32 == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_32)\n"); return HALMAC_RET_PLATFORM_API_NULL; } } - if (NULL == pHalmac_platform_api->RTL_FREE) { + if (pHalmac_platform_api->RTL_FREE == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_FREE)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->RTL_MALLOC) { + if (pHalmac_platform_api->RTL_MALLOC == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MALLOC)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->RTL_MEMCPY) { + if (pHalmac_platform_api->RTL_MEMCPY == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MEMCPY)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->RTL_MEMSET) { + if (pHalmac_platform_api->RTL_MEMSET == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MEMSET)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->RTL_DELAY_US) { + if (pHalmac_platform_api->RTL_DELAY_US == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_DELAY_US)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->MUTEX_INIT) { + if (pHalmac_platform_api->MUTEX_INIT == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_INIT)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->MUTEX_DEINIT) { + if (pHalmac_platform_api->MUTEX_DEINIT == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_DEINIT)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->MUTEX_LOCK) { + if (pHalmac_platform_api->MUTEX_LOCK == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_LOCK)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->MUTEX_UNLOCK) { + if (pHalmac_platform_api->MUTEX_UNLOCK == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_UNLOCK)\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->EVENT_INDICATION) { + if (pHalmac_platform_api->EVENT_INDICATION == NULL) { pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->EVENT_INDICATION)\n"); return HALMAC_RET_PLATFORM_API_NULL; } @@ -350,9 +376,16 @@ halmac_check_platform_api( return HALMAC_RET_SUCCESS; } +/** + * halmac_get_version() - get HALMAC version + * @version : return version of major, prototype and minor information + * Author : KaiYuan Chang / Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ HALMAC_RET_STATUS halmac_get_version( - OUT HALMAC_VER * version + OUT HALMAC_VER *version ) { version->major_ver = (u8)HALMAC_MAJOR_VER; @@ -361,3 +394,127 @@ halmac_get_version( return HALMAC_RET_SUCCESS; } + +static HALMAC_RET_STATUS +halmac_get_chip_info( + IN VOID *pDriver_adapter, + IN PHALMAC_PLATFORM_API pHalmac_platform_api, + IN HALMAC_INTERFACE halmac_interface, + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + PHALMAC_API pHalmac_api = (PHALMAC_API)NULL; + u8 chip_id, chip_version; + u32 polling_count; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + /* Get Chip_id and Chip_version */ + if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { + plarform_reg_write_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SDIO_HSUS_CTRL, platform_reg_read_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SDIO_HSUS_CTRL) & ~(BIT(0))); + + polling_count = 10000; + while (!(platform_reg_read_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SDIO_HSUS_CTRL) & 0x02)) { + polling_count--; + if (polling_count == 0) + return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL; + } + + chip_id = platform_reg_read_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SYS_CFG2); + chip_version = platform_reg_read_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SYS_CFG1 + 1) >> 4; + } else { + chip_id = pHalmac_platform_api->REG_READ_8(pDriver_adapter, REG_SYS_CFG2); + chip_version = pHalmac_platform_api->REG_READ_8(pDriver_adapter, REG_SYS_CFG1 + 1) >> 4; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]Chip id : 0x%X\n", chip_id); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]Chip version : 0x%X\n", chip_version); + + pHalmac_adapter->chip_version = (HALMAC_CHIP_VER)chip_version; + + if (chip_id == HALMAC_CHIP_ID_HW_DEF_8822B) { + pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8822B; + } else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8821C) { + pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8821C; + } else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8814B) { + pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8814B; + } else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8197F) { + pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8197F; + } else { + pHalmac_adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE; + return HALMAC_RET_CHIP_NOT_SUPPORT; + } + + return HALMAC_RET_SUCCESS; +} + +static u8 +platform_reg_read_8_sdio( + IN VOID *pDriver_adapter, + IN PHALMAC_PLATFORM_API pHalmac_platform_api, + IN u32 offset +) +{ + u8 value8; + u32 halmac_offset = offset; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (0 == (halmac_offset & 0xFFFF0000)) + halmac_offset |= WLAN_IOREG_OFFSET; + + status = halmac_convert_to_sdio_bus_offset(&halmac_offset); + if (status != HALMAC_RET_SUCCESS) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "platform_reg_read_8_sdio error = %x\n", status); + return status; + } + + value8 = pHalmac_platform_api->SDIO_CMD52_READ(pDriver_adapter, halmac_offset); + + return value8; +} + +static HALMAC_RET_STATUS +plarform_reg_write_8_sdio( + IN VOID *pDriver_adapter, + IN PHALMAC_PLATFORM_API pHalmac_platform_api, + IN u32 offset, + IN u8 data +) +{ + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + u32 halmac_offset = offset; + + if (0 == (halmac_offset & 0xFFFF0000)) + halmac_offset |= WLAN_IOREG_OFFSET; + + status = halmac_convert_to_sdio_bus_offset(&halmac_offset); + + if (status != HALMAC_RET_SUCCESS) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_8_sdio_88xx error = %x\n", status); + return status; + } + pHalmac_platform_api->SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, data); + + return HALMAC_RET_SUCCESS; +} + + +static HALMAC_RET_STATUS +halmac_convert_to_sdio_bus_offset( + INOUT u32 *halmac_offset +) +{ + switch ((*halmac_offset) & 0xFFFF0000) { + case WLAN_IOREG_OFFSET: + *halmac_offset = (HALMAC_SDIO_CMD_ADDR_MAC_REG << 13) | (*halmac_offset & HALMAC_WLAN_MAC_REG_MSK); + break; + case SDIO_LOCAL_OFFSET: + *halmac_offset = (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | (*halmac_offset & HALMAC_SDIO_LOCAL_MSK); + break; + default: + *halmac_offset = 0xFFFFFFFF; + return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL; + } + + return HALMAC_RET_SUCCESS; +} diff --git a/hal/halmac/halmac_api.h b/hal/halmac/halmac_api.h index a10436e..8a1f35e 100644 --- a/hal/halmac/halmac_api.h +++ b/hal/halmac/halmac_api.h @@ -1,14 +1,27 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_API_H_ #define _HALMAC_API_H_ -#define HALMAC_SVN_VER "11974M" +#define HALMAC_SVN_VER "13348M" -/* major version, ver_1 for async_api */ -#define HALMAC_MAJOR_VER 0x0001 -/* For halmac_api num change or prototype change, increment prototype version */ -#define HALMAC_PROTOTYPE_VER 0x0002 -/* else increment minor version */ -#define HALMAC_MINOR_VER 0x0000 +#define HALMAC_MAJOR_VER 0x0001 /* major version, ver_1 for async_api */ +#define HALMAC_PROTOTYPE_VER 0x0003 /* For halmac_api num change or prototype change, increment prototype version */ +#define HALMAC_MINOR_VER 0x0009 /* else increment minor version */ +#define HALMAC_PATCH_VER 0x0000 /* patch version */ #include "halmac_2_platform.h" #include "halmac_hw_cfg.h" @@ -50,21 +63,29 @@ #include "halmac_tx_bd_chip.h" #include "halmac_rx_bd_chip.h" #if HALMAC_PLATFORM_WINDOWS == 1 + +#if HALMAC_8822B_SUPPORT #include "halmac_88xx/halmac_win8822b_cfg.h" +#endif +#if HALMAC_8821C_SUPPORT #include "halmac_88xx/halmac_win8821c_cfg.h" -#include "halmac_88xx/halmac_win8197f_cfg.h" +#endif + #else #include "halmac_88xx/halmac_88xx_cfg.h" #endif +#if HALMAC_8822B_SUPPORT #include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h" -#include "halmac_88xx/halmac_8821c/halmac_8821c_cfg.h" -#include "halmac_88xx/halmac_8197f/halmac_8197f_cfg.h" #include "halmac_reg_8822b.h" #include "halmac_bit_8822b.h" +#endif + +#if HALMAC_8821C_SUPPORT +#include "halmac_88xx/halmac_8821c/halmac_8821c_cfg.h" #include "halmac_reg_8821c.h" #include "halmac_bit_8821c.h" - +#endif HALMAC_RET_STATUS halmac_init_adapter( @@ -87,7 +108,7 @@ halmac_halt_api( HALMAC_RET_STATUS halmac_get_version( - OUT HALMAC_VER * version + OUT HALMAC_VER *version ); #endif diff --git a/hal/halmac/halmac_bit2.h b/hal/halmac/halmac_bit2.h index e5191d8..cda17c6 100644 --- a/hal/halmac/halmac_bit2.h +++ b/hal/halmac/halmac_bit2.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __RTL_WLAN_BITDEF_H__ #define __RTL_WLAN_BITDEF_H__ @@ -31,7 +46,7 @@ -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define BIT_SHIFT_WATCH_DOG_RECORD_V1 10 @@ -44,35 +59,41 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_EN_WATCH_DOG_V1 BIT(8) -#define BIT_SHIFT_NPQ_AVAL_PG 8 -#define BIT_MASK_NPQ_AVAL_PG 0xff -#define BIT_NPQ_AVAL_PG(x) (((x) & BIT_MASK_NPQ_AVAL_PG) << BIT_SHIFT_NPQ_AVAL_PG) -#define BIT_GET_NPQ_AVAL_PG(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG) & BIT_MASK_NPQ_AVAL_PG) +#endif +#if (HALMAC_8881A_SUPPORT) + +#define BIT_AFE_MBIAS BIT(1) + #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_EN_WATCH_DOG_V1 BIT(8) +#define BIT_ISO_MD2PP BIT(0) #endif -#if (HALMAC_8881A_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) +#define BIT_GET_R_WMAC_IPV6_MYIPAD(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD) -#define BIT_AFE_MBIAS BIT(1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_ISO_MD2PP BIT(0) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ @@ -86,7 +107,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -106,7 +127,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ @@ -116,7 +137,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -126,7 +147,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -147,7 +168,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -168,7 +189,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -178,7 +199,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ @@ -188,7 +209,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -198,7 +219,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ @@ -208,7 +229,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -218,7 +239,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ @@ -238,7 +259,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -248,7 +269,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ @@ -258,7 +279,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -268,7 +289,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ @@ -278,7 +299,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -288,7 +309,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -308,7 +329,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -318,7 +339,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ @@ -338,7 +359,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -348,7 +369,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ @@ -358,7 +379,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ @@ -368,7 +389,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ @@ -378,7 +399,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ @@ -389,7 +410,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ @@ -399,7 +420,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ @@ -419,7 +440,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ @@ -444,7 +465,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -455,7 +476,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -475,7 +496,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -495,7 +516,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -515,7 +536,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -535,7 +556,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -555,7 +576,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -565,7 +586,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -585,7 +606,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -596,7 +617,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -606,7 +627,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -627,7 +648,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -637,7 +658,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -647,7 +668,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -667,7 +688,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -678,7 +699,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -698,7 +719,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -718,7 +739,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -738,7 +759,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -758,7 +779,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -768,7 +789,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -788,7 +809,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ @@ -798,7 +819,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ @@ -818,7 +839,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ @@ -828,7 +849,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ @@ -848,7 +869,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ @@ -868,7 +889,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ @@ -879,7 +900,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ @@ -900,7 +921,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ @@ -926,7 +947,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ @@ -949,7 +970,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ @@ -969,7 +990,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ @@ -995,7 +1016,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ @@ -1015,7 +1036,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ @@ -1028,7 +1049,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_EE_VPD (Offset 0x000C) */ @@ -1068,7 +1089,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ @@ -1108,7 +1129,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ @@ -1144,7 +1165,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ @@ -1176,7 +1197,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ @@ -1201,7 +1222,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ @@ -1212,7 +1233,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ @@ -1237,7 +1258,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ @@ -1277,7 +1298,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ @@ -1322,7 +1343,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ @@ -1337,7 +1358,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ @@ -1362,7 +1383,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ @@ -1398,7 +1419,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ @@ -1408,7 +1429,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -1428,7 +1449,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1458,7 +1479,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -1470,7 +1491,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -1485,7 +1506,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1495,7 +1516,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1516,7 +1537,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1541,7 +1562,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1561,7 +1582,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -1576,7 +1597,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1596,7 +1617,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1616,7 +1637,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1651,7 +1672,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1661,7 +1682,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -1676,7 +1697,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1701,7 +1722,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1726,7 +1747,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1751,7 +1772,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -1766,7 +1787,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1811,7 +1832,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -1836,7 +1857,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -1872,7 +1893,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -1923,7 +1944,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1933,7 +1954,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -1948,7 +1969,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -1973,7 +1994,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -1988,7 +2009,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -2014,7 +2035,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -2029,7 +2050,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -2070,7 +2091,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -2080,7 +2101,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -2105,7 +2126,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ @@ -2130,7 +2151,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ @@ -2140,7 +2161,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ @@ -2160,7 +2181,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ @@ -2180,7 +2201,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ @@ -2192,7 +2213,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ @@ -2212,7 +2233,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ @@ -2227,7 +2248,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ @@ -2244,7 +2265,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ @@ -2259,7 +2280,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ @@ -2269,7 +2290,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ @@ -2297,7 +2318,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ @@ -2317,7 +2338,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ @@ -2327,7 +2348,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ @@ -2347,7 +2368,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ @@ -2367,7 +2388,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ @@ -2381,7 +2402,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_RX_REQ_LEN (Offset 0x1025001C) */ @@ -2396,7 +2417,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RF_CTRL (Offset 0x001F) */ @@ -2416,7 +2437,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RF_CTRL (Offset 0x001F) */ @@ -2436,7 +2457,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RF_CTRL (Offset 0x001F) */ @@ -2456,7 +2477,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_FREE_TXPG_SEQ_V1 (Offset 0x1025001F) */ @@ -2482,7 +2503,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ @@ -2497,7 +2518,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ @@ -2513,7 +2534,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ @@ -2523,7 +2544,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ @@ -2533,7 +2554,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ @@ -2548,7 +2569,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ @@ -2561,7 +2582,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ @@ -2571,7 +2592,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ @@ -2596,7 +2617,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ @@ -2623,7 +2644,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ @@ -2643,7 +2664,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ @@ -2664,7 +2685,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ @@ -2674,7 +2695,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ @@ -2704,7 +2725,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -2785,7 +2806,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -2831,7 +2852,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -2872,7 +2893,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -2887,7 +2908,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -2947,7 +2968,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -2962,7 +2983,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ @@ -3007,7 +3028,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -3042,7 +3063,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -3087,7 +3108,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -3117,7 +3138,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -3198,7 +3219,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -3213,7 +3234,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -3269,7 +3290,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -3349,7 +3370,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -3364,7 +3385,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ @@ -3374,7 +3395,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ @@ -3389,7 +3410,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3466,7 +3487,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3496,7 +3517,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ @@ -3521,7 +3542,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3548,7 +3569,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3588,7 +3609,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3618,7 +3639,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3654,7 +3675,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3715,7 +3736,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3755,7 +3776,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3771,7 +3792,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3796,7 +3817,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3911,7 +3932,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3946,7 +3967,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ @@ -3971,7 +3992,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ @@ -4202,7 +4223,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ @@ -4232,7 +4253,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ @@ -4273,7 +4294,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ @@ -4333,7 +4354,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ @@ -4373,7 +4394,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ @@ -4383,7 +4404,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ @@ -4411,7 +4432,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ @@ -4421,7 +4442,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ @@ -4431,7 +4452,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ @@ -4446,7 +4467,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ @@ -4467,7 +4488,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ @@ -4482,7 +4503,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ @@ -4508,7 +4529,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ @@ -4558,7 +4579,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ @@ -4583,7 +4604,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ @@ -4598,7 +4619,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ @@ -4633,7 +4654,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ @@ -4653,7 +4674,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ @@ -4668,7 +4689,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ @@ -4705,7 +4726,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ @@ -4731,7 +4752,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ @@ -4772,7 +4793,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ @@ -4812,7 +4833,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ @@ -4832,7 +4853,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ @@ -4842,7 +4863,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ @@ -4862,7 +4883,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ @@ -4878,7 +4899,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ @@ -4923,7 +4944,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ @@ -4953,7 +4974,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ @@ -4983,7 +5004,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ @@ -4995,6 +5016,22 @@ #define BIT_GET_SYSON_RCLK_SCALE(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE) +#endif + + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */ + +#define BIT_SYS_CLK BIT(0) + +#endif + + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + + /* 2 REG_CAL_TIMER (Offset 0x003C) */ @@ -5097,7 +5134,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ @@ -5117,7 +5154,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ @@ -5127,7 +5164,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ @@ -5137,7 +5174,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ @@ -5147,7 +5184,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ @@ -5177,7 +5214,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ @@ -5187,7 +5224,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ @@ -5202,7 +5239,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ @@ -5233,7 +5270,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ @@ -5244,7 +5281,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ @@ -5294,7 +5331,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ @@ -5304,7 +5341,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ @@ -5322,7 +5359,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ @@ -5342,7 +5379,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ @@ -5362,7 +5399,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ @@ -5377,7 +5414,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ @@ -5392,7 +5429,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */ @@ -5425,7 +5462,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_INDIRECT_REG_DATA (Offset 0x10250044) */ @@ -5440,7 +5477,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ @@ -5501,7 +5538,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ @@ -5521,7 +5558,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ @@ -5546,7 +5583,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ @@ -5661,7 +5698,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ @@ -5681,7 +5718,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ @@ -5711,7 +5748,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ @@ -5741,7 +5778,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ @@ -5781,7 +5818,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ @@ -5791,7 +5828,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ @@ -5821,7 +5858,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ @@ -5841,7 +5878,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ @@ -5868,7 +5905,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ @@ -5883,7 +5920,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ @@ -5904,7 +5941,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -5914,7 +5951,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -5934,7 +5971,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -5954,7 +5991,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -5977,7 +6014,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -5997,7 +6034,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6017,7 +6054,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6037,7 +6074,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6057,7 +6094,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6077,7 +6114,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6097,7 +6134,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6117,7 +6154,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6137,7 +6174,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6157,7 +6194,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6177,7 +6214,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6197,7 +6234,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6217,7 +6254,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6237,7 +6274,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6257,7 +6294,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6297,7 +6334,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6307,7 +6344,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6327,7 +6364,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6367,7 +6404,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6397,7 +6434,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6407,7 +6444,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6427,7 +6464,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6447,7 +6484,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6467,7 +6504,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ @@ -6487,7 +6524,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6497,7 +6534,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6517,7 +6554,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6537,7 +6574,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6560,7 +6597,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6580,7 +6617,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6600,7 +6637,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6620,7 +6657,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6640,7 +6677,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6660,7 +6697,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6680,7 +6717,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6700,7 +6737,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6720,7 +6757,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6740,7 +6777,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6760,7 +6797,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6780,7 +6817,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6800,7 +6837,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6820,7 +6857,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6840,7 +6877,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6890,7 +6927,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -6960,7 +6997,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -7010,7 +7047,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -7020,7 +7057,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -7040,7 +7077,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -7060,7 +7097,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -7080,7 +7117,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ @@ -7100,7 +7137,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ @@ -7132,7 +7169,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ @@ -7143,7 +7180,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ @@ -7164,7 +7201,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ @@ -7194,7 +7231,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ @@ -7214,7 +7251,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ @@ -7234,7 +7271,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ @@ -7254,7 +7291,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ @@ -7282,7 +7319,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ @@ -7305,7 +7342,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ @@ -7316,7 +7353,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ @@ -7326,6 +7363,21 @@ #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) + + +/* 2 REG_HSISR (Offset 0x005C) */ + + +#define BIT_SHIFT_NPQ_AVAL_PG 8 +#define BIT_MASK_NPQ_AVAL_PG 0xff +#define BIT_NPQ_AVAL_PG(x) (((x) & BIT_MASK_NPQ_AVAL_PG) << BIT_SHIFT_NPQ_AVAL_PG) +#define BIT_GET_NPQ_AVAL_PG(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG) & BIT_MASK_NPQ_AVAL_PG) + + +#endif + + #if (HALMAC_8197F_SUPPORT) @@ -7336,7 +7388,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ @@ -7366,7 +7418,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ @@ -7386,7 +7438,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ @@ -7406,7 +7458,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ @@ -7427,7 +7479,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */ @@ -7460,7 +7512,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_H2C (Offset 0x10250060) */ @@ -7475,7 +7527,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7496,7 +7548,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7507,7 +7559,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7527,7 +7579,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7547,7 +7599,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7557,7 +7609,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7577,7 +7629,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7597,7 +7649,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7617,7 +7669,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7638,7 +7690,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7683,7 +7735,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7693,7 +7745,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7723,7 +7775,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7743,7 +7795,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7773,7 +7825,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7793,7 +7845,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7823,7 +7875,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7853,7 +7905,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7873,7 +7925,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7893,7 +7945,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7923,7 +7975,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7953,7 +8005,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -7983,7 +8035,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -8013,7 +8065,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -8053,7 +8105,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ @@ -8073,7 +8125,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_C2H (Offset 0x10250064) */ @@ -8088,7 +8140,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8101,7 +8153,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8111,7 +8163,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8122,7 +8174,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8143,7 +8195,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8163,7 +8215,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8173,7 +8225,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8194,7 +8246,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8214,7 +8266,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8234,7 +8286,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8244,7 +8296,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8264,7 +8316,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8284,7 +8336,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8304,7 +8356,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8314,7 +8366,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8325,7 +8377,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8335,7 +8387,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8366,7 +8418,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8386,7 +8438,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8436,7 +8488,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8456,7 +8508,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8476,7 +8528,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8496,7 +8548,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8516,7 +8568,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ @@ -8584,7 +8636,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDM_DEBUG (Offset 0x006C) */ @@ -8618,7 +8670,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ @@ -8638,7 +8690,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ @@ -8659,7 +8711,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ @@ -8679,7 +8731,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ @@ -8702,7 +8754,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ @@ -8713,7 +8765,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ @@ -8733,7 +8785,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ @@ -8757,7 +8809,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ @@ -8783,7 +8835,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ @@ -8809,7 +8861,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ @@ -8829,7 +8881,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ @@ -8839,7 +8891,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ @@ -8871,7 +8923,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ @@ -8903,7 +8955,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ @@ -8923,7 +8975,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ @@ -8943,7 +8995,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ @@ -8963,7 +9015,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ @@ -8983,7 +9035,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ @@ -9003,7 +9055,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ @@ -9018,7 +9070,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ @@ -9038,7 +9090,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ @@ -9063,7 +9115,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ @@ -9083,7 +9135,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ @@ -9405,7 +9457,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9431,7 +9483,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9473,7 +9525,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9498,7 +9550,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9539,7 +9591,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9569,7 +9621,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9614,7 +9666,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9629,7 +9681,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9649,7 +9701,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9659,7 +9711,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9694,7 +9746,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9734,7 +9786,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9749,7 +9801,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ @@ -9779,7 +9831,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ @@ -9803,7 +9855,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ @@ -9828,7 +9880,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ @@ -9868,7 +9920,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ @@ -9878,7 +9930,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ @@ -9908,7 +9960,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ @@ -9917,6 +9969,7 @@ #define BIT_EMEM_DW_OK BIT(7) #define BIT_TOGGLING BIT(7) #define BIT_DMEM_CHKSUM_OK BIT(6) +#define BIT_ACK BIT(6) #endif @@ -9941,7 +9994,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ @@ -9971,7 +10024,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ @@ -10001,13 +10054,12 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_IMEM_DW_OK BIT(3) -#define BIT_WWLAN BIT(3) #endif @@ -10022,13 +10074,12 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2) -#define BIT_RPS_ST BIT(2) #endif @@ -10053,13 +10104,12 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1) -#define BIT_WLAN_TRX BIT(1) #endif @@ -10074,17 +10124,17 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */ -#define BIT_SYS_CLK BIT(0) +#define BIT_32K_PERMISSION BIT(0) #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MCU_TST_CFG (Offset 0x0084) */ @@ -10099,7 +10149,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */ @@ -10118,7 +10168,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ @@ -10129,7 +10179,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HMEBOX_E0_E1 (Offset 0x0088) */ @@ -10150,7 +10200,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_RESPONSE_TIMER (Offset 0x10250088) */ @@ -10181,7 +10231,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ @@ -10196,7 +10246,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HMEBOX_E2_E3 (Offset 0x008C) */ @@ -10217,7 +10267,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10227,7 +10277,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10237,7 +10287,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10257,7 +10307,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10277,7 +10327,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10298,7 +10348,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10308,7 +10358,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10328,7 +10378,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10348,7 +10398,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10368,7 +10418,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10391,7 +10441,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10419,7 +10469,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10436,7 +10486,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ @@ -10446,7 +10496,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_HSISR (Offset 0x10250090) */ @@ -10470,7 +10520,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ @@ -10480,7 +10530,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ @@ -10512,7 +10562,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ @@ -10542,7 +10592,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ @@ -10572,7 +10622,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ @@ -10602,7 +10652,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_DEBOUNCE_CTRL (Offset 0x0098) */ @@ -10634,7 +10684,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYSON_FSM_MON (Offset 0x00A0) */ @@ -10672,7 +10722,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ @@ -10687,7 +10737,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ @@ -10703,7 +10753,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ @@ -10719,7 +10769,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ @@ -10734,7 +10784,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ @@ -10744,7 +10794,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ @@ -10769,7 +10819,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ @@ -10784,7 +10834,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ @@ -10798,7 +10848,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ @@ -10818,7 +10868,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ @@ -10839,7 +10889,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ @@ -10860,7 +10910,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ @@ -10890,7 +10940,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ @@ -10910,7 +10960,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ @@ -10920,7 +10970,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ @@ -10938,7 +10988,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ @@ -10959,7 +11009,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ @@ -10969,7 +11019,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ @@ -11000,7 +11050,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ @@ -11010,7 +11060,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ @@ -11030,7 +11080,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ @@ -11050,7 +11100,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ @@ -11070,7 +11120,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ @@ -11090,7 +11140,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ @@ -11100,7 +11150,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ @@ -11119,7 +11169,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ @@ -11139,7 +11189,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ @@ -11149,7 +11199,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ @@ -11172,7 +11222,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ @@ -11186,7 +11236,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ @@ -11196,7 +11246,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ @@ -11206,7 +11256,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ @@ -11229,7 +11279,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ @@ -11239,7 +11289,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ @@ -11253,7 +11303,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ @@ -11267,7 +11317,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ @@ -11276,13 +11326,13 @@ #define BIT_HR_FF_UDN BIT(5) #define BIT_TXDMA_BUSY_ERR BIT(4) #define BIT_TXDMA_VLD_ERR BIT(3) -#define BIT_QSEL_UNKOWN_ERR BIT(2) +#define BIT_QSEL_UNKNOWN_ERR BIT(2) #define BIT_QSEL_MIS_ERR BIT(1) #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DBG_PORT_SEL (Offset 0x00C0) */ @@ -11297,7 +11347,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ @@ -11340,7 +11390,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ @@ -11361,7 +11411,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ @@ -11386,7 +11436,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ @@ -11406,7 +11456,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ @@ -11429,7 +11479,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ @@ -11459,7 +11509,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ @@ -11479,7 +11529,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ @@ -11499,7 +11549,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ @@ -11519,7 +11569,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ @@ -11539,7 +11589,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ @@ -11559,7 +11609,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ @@ -11569,7 +11619,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_CMD_ERR_CONTENT (Offset 0x102500C4) */ @@ -11612,7 +11662,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_CRC_ERR_IDX (Offset 0x102500C9) */ @@ -11644,7 +11694,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ @@ -11675,7 +11725,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ @@ -11701,7 +11751,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ @@ -11711,7 +11761,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ @@ -11750,7 +11800,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ @@ -11770,7 +11820,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ @@ -11790,7 +11840,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ @@ -11810,7 +11860,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ @@ -11830,7 +11880,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ @@ -11861,7 +11911,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ @@ -11881,7 +11931,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ @@ -11907,7 +11957,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ @@ -11918,7 +11968,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_RPT (Offset 0x00D4) */ @@ -11943,7 +11993,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ @@ -11964,7 +12014,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ @@ -11992,7 +12042,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ @@ -12028,7 +12078,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ @@ -12064,7 +12114,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ @@ -12094,7 +12144,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ @@ -12139,7 +12189,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ @@ -12149,7 +12199,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ @@ -12190,7 +12240,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ @@ -12205,7 +12255,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ @@ -12226,7 +12276,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ @@ -12255,7 +12305,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ @@ -12270,7 +12320,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ @@ -12304,7 +12354,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ @@ -12356,7 +12406,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WLRF1 (Offset 0x00EC) */ @@ -12407,7 +12457,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12422,7 +12472,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12448,7 +12498,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12458,7 +12508,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12478,7 +12528,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12489,7 +12539,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12514,7 +12564,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12544,7 +12594,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12569,7 +12619,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12579,7 +12629,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12592,7 +12642,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12612,7 +12662,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12632,7 +12682,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12642,7 +12692,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12662,7 +12712,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12672,7 +12722,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12692,7 +12742,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ @@ -12728,7 +12778,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ @@ -12750,7 +12800,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ @@ -12794,7 +12844,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ @@ -12821,7 +12871,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ @@ -12841,7 +12891,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ @@ -12862,7 +12912,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ @@ -12902,7 +12952,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ @@ -12933,7 +12983,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ @@ -12973,7 +13023,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS2 (Offset 0x00F8) */ @@ -13011,7 +13061,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ @@ -13021,7 +13071,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ @@ -13061,7 +13111,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ @@ -13108,7 +13158,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ @@ -13119,7 +13169,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ @@ -13139,7 +13189,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PKT_BUFF_ACCESS_CTRL (Offset 0x0106) */ @@ -13164,7 +13214,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ @@ -13203,7 +13253,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ @@ -13287,7 +13337,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ @@ -13317,7 +13367,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ @@ -13332,7 +13382,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ @@ -13374,7 +13424,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ @@ -13458,7 +13508,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ @@ -13487,7 +13537,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ @@ -13497,7 +13547,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ @@ -13519,7 +13569,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ @@ -13539,7 +13589,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ @@ -13559,7 +13609,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ @@ -13579,7 +13629,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ @@ -13608,7 +13658,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ @@ -13618,7 +13668,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ @@ -13640,7 +13690,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ @@ -13660,7 +13710,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ @@ -13680,7 +13730,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ @@ -13690,7 +13740,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CPWM (Offset 0x012C) */ @@ -13706,7 +13756,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13726,7 +13776,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13746,7 +13796,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13766,7 +13816,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13786,7 +13836,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13806,7 +13856,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13826,7 +13876,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13846,7 +13896,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13866,7 +13916,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13886,7 +13936,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13906,7 +13956,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13926,7 +13976,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13946,7 +13996,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13966,7 +14016,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -13986,7 +14036,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14006,7 +14056,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14036,7 +14086,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14056,7 +14106,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14076,7 +14126,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14096,7 +14146,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14126,7 +14176,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14146,7 +14196,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14166,7 +14216,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14186,7 +14236,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14206,7 +14256,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14226,7 +14276,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14246,7 +14296,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14266,7 +14316,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14286,7 +14336,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14306,7 +14356,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14326,7 +14376,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14346,7 +14396,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ @@ -14370,7 +14420,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14390,7 +14440,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14410,7 +14460,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14430,7 +14480,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14450,7 +14500,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14470,7 +14520,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14490,7 +14540,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14510,7 +14560,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14530,7 +14580,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14550,7 +14600,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14570,7 +14620,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14590,7 +14640,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14610,7 +14660,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14630,7 +14680,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14650,7 +14700,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14680,7 +14730,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14700,7 +14750,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14720,7 +14770,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14740,7 +14790,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14770,7 +14820,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14790,7 +14840,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14810,7 +14860,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14830,7 +14880,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14850,7 +14900,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14870,7 +14920,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14890,7 +14940,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14910,7 +14960,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14930,7 +14980,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14950,7 +15000,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14970,7 +15020,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -14990,7 +15040,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ @@ -15018,7 +15068,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15033,12 +15083,12 @@ /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_RETRIVE_BUFFERED_MSK BIT(22) +#define BIT_RETRIEVE_BUFFERED_MSK BIT(22) #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15058,7 +15108,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15078,7 +15128,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15098,7 +15148,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15118,7 +15168,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15138,7 +15188,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15158,7 +15208,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15178,7 +15228,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15198,7 +15248,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15218,7 +15268,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15242,7 +15292,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15262,7 +15312,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15282,7 +15332,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15302,7 +15352,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15322,7 +15372,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15342,7 +15392,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15362,7 +15412,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15382,7 +15432,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15402,7 +15452,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ @@ -15430,7 +15480,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15445,12 +15495,12 @@ /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_RETRIVE_BUFFERED_INT BIT(22) +#define BIT_RETRIEVE_BUFFERED_INT BIT(22) #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15470,7 +15520,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15490,7 +15540,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15510,7 +15560,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15530,7 +15580,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15550,7 +15600,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15570,7 +15620,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15590,7 +15640,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15610,7 +15660,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15630,7 +15680,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15654,7 +15704,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15674,7 +15724,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15694,7 +15744,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15714,7 +15764,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15734,7 +15784,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15754,7 +15804,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15774,7 +15824,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15794,7 +15844,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15814,7 +15864,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ @@ -15824,7 +15874,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ @@ -15849,7 +15899,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ @@ -15869,7 +15919,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ @@ -15889,7 +15939,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ @@ -15914,7 +15964,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ @@ -15929,7 +15979,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PKTBUF_DBG_DATA_L (Offset 0x0144) */ @@ -16048,7 +16098,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TC5_CTRL (Offset 0x0168) */ @@ -16058,7 +16108,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TC5_CTRL (Offset 0x0168) */ @@ -16085,7 +16135,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TC6_CTRL (Offset 0x016C) */ @@ -16095,7 +16145,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TC6_CTRL (Offset 0x016C) */ @@ -16133,7 +16183,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_FAIL (Offset 0x0170) */ @@ -16163,7 +16213,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ @@ -16190,7 +16240,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ @@ -16220,7 +16270,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_DONE (Offset 0x0178) */ @@ -16247,7 +16297,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_DONE (Offset 0x0178) */ @@ -16307,7 +16357,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */ @@ -16322,7 +16372,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AES_DECRPT_DATA (Offset 0x0180) */ @@ -16361,7 +16411,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TMETER (Offset 0x0190) */ @@ -16405,7 +16455,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ @@ -16436,7 +16486,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ @@ -16452,7 +16502,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ @@ -16462,7 +16512,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ @@ -16472,7 +16522,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ @@ -16505,7 +16555,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ @@ -16535,7 +16585,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_C2HEVT (Offset 0x01A0) */ @@ -16547,6 +16597,54 @@ #define BIT_GET_C2HEVT_MSG(x) (((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG) +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_C2HEVT (Offset 0x01A0) */ + + +#define BIT_SHIFT_C2HEVT_MSG_V1 0 +#define BIT_MASK_C2HEVT_MSG_V1 0xffffffffL +#define BIT_C2HEVT_MSG_V1(x) (((x) & BIT_MASK_C2HEVT_MSG_V1) << BIT_SHIFT_C2HEVT_MSG_V1) +#define BIT_GET_C2HEVT_MSG_V1(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_V1) & BIT_MASK_C2HEVT_MSG_V1) + + +/* 2 REG_C2HEVT_1 (Offset 0x01A4) */ + + +#define BIT_SHIFT_C2HEVT_MSG_1 0 +#define BIT_MASK_C2HEVT_MSG_1 0xffffffffL +#define BIT_C2HEVT_MSG_1(x) (((x) & BIT_MASK_C2HEVT_MSG_1) << BIT_SHIFT_C2HEVT_MSG_1) +#define BIT_GET_C2HEVT_MSG_1(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_1) & BIT_MASK_C2HEVT_MSG_1) + + +/* 2 REG_C2HEVT_2 (Offset 0x01A8) */ + + +#define BIT_SHIFT_C2HEVT_MSG_2 0 +#define BIT_MASK_C2HEVT_MSG_2 0xffffffffL +#define BIT_C2HEVT_MSG_2(x) (((x) & BIT_MASK_C2HEVT_MSG_2) << BIT_SHIFT_C2HEVT_MSG_2) +#define BIT_GET_C2HEVT_MSG_2(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_2) & BIT_MASK_C2HEVT_MSG_2) + + +/* 2 REG_C2HEVT_3 (Offset 0x01AC) */ + + +#define BIT_SHIFT_C2HEVT_MSG_3 0 +#define BIT_MASK_C2HEVT_MSG_3 0xffffffffL +#define BIT_C2HEVT_MSG_3(x) (((x) & BIT_MASK_C2HEVT_MSG_3) << BIT_SHIFT_C2HEVT_MSG_3) +#define BIT_GET_C2HEVT_MSG_3(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_3) & BIT_MASK_C2HEVT_MSG_3) + + +#endif + + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + + /* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ @@ -16556,6 +16654,36 @@ #define BIT_GET_SW_DEFINED_PAGE1(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1) +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ + + +#define BIT_SHIFT_SW_DEFINED_PAGE1_V1 0 +#define BIT_MASK_SW_DEFINED_PAGE1_V1 0xffffffffL +#define BIT_SW_DEFINED_PAGE1_V1(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1) << BIT_SHIFT_SW_DEFINED_PAGE1_V1) +#define BIT_GET_SW_DEFINED_PAGE1_V1(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1) & BIT_MASK_SW_DEFINED_PAGE1_V1) + + +/* 2 REG_SW_DEFINED_PAGE2 (Offset 0x01BC) */ + + +#define BIT_SHIFT_SW_DEFINED_PAGE2 0 +#define BIT_MASK_SW_DEFINED_PAGE2 0xffffffffL +#define BIT_SW_DEFINED_PAGE2(x) (((x) & BIT_MASK_SW_DEFINED_PAGE2) << BIT_SHIFT_SW_DEFINED_PAGE2) +#define BIT_GET_SW_DEFINED_PAGE2(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2) & BIT_MASK_SW_DEFINED_PAGE2) + + +#endif + + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + + /* 2 REG_MCUTST_I (Offset 0x01C0) */ @@ -16660,7 +16788,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LLT_INIT (Offset 0x01E0) */ @@ -16696,7 +16824,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LLT_INIT (Offset 0x01E0) */ @@ -16726,7 +16854,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LLT_INIT_ADDR (Offset 0x01E4) */ @@ -16741,7 +16869,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ @@ -16771,7 +16899,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ @@ -16807,7 +16935,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ @@ -16882,7 +17010,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ @@ -16918,7 +17046,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ @@ -16958,7 +17086,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ @@ -16995,7 +17123,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ @@ -17025,7 +17153,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ @@ -17056,7 +17184,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ @@ -17086,10 +17214,10 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ #define BIT_SHIFT_BLK_DESC_NUM 4 @@ -17101,7 +17229,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ @@ -17114,7 +17242,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ @@ -17125,7 +17253,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ @@ -17151,7 +17279,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ @@ -17196,7 +17324,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ @@ -17217,7 +17345,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ @@ -17227,7 +17355,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ @@ -17296,7 +17424,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TQPNT1 (Offset 0x0218) */ @@ -17332,7 +17460,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TQPNT1 (Offset 0x0218) */ @@ -17368,7 +17496,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TQPNT2 (Offset 0x021C) */ @@ -17404,7 +17532,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TQPNT2 (Offset 0x021C) */ @@ -17443,7 +17571,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TQPNT3 (Offset 0x0220) */ @@ -17475,7 +17603,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TQPNT4 (Offset 0x0224) */ @@ -17511,7 +17639,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TQPNT4 (Offset 0x0224) */ @@ -17538,7 +17666,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ @@ -17589,7 +17717,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ @@ -17604,7 +17732,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ @@ -17617,7 +17745,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ @@ -17633,7 +17761,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FIFOPAGE_INFO_1 (Offset 0x0230) */ @@ -17669,7 +17797,7 @@ #endif -#if (HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ @@ -17684,7 +17812,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ @@ -17729,7 +17857,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_H2C_HEAD (Offset 0x0244) */ @@ -17796,7 +17924,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ @@ -17857,7 +17985,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ @@ -17872,7 +18000,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ @@ -17887,7 +18015,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ @@ -17917,7 +18045,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ @@ -17932,7 +18060,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ @@ -17977,7 +18105,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXPKT_NUM (Offset 0x0284) */ @@ -17992,7 +18120,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RXPKT_NUM (Offset 0x0284) */ @@ -18007,7 +18135,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXPKT_NUM (Offset 0x0284) */ @@ -18036,7 +18164,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ @@ -18056,7 +18184,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ @@ -18066,7 +18194,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ @@ -18089,17 +18217,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ - -#define BIT_DMA_MODE BIT(1) - -#endif - - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ @@ -18118,7 +18236,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RXDMA_MODE (Offset 0x0290) */ @@ -18150,7 +18268,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_MODE (Offset 0x0290) */ @@ -18181,7 +18299,17 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ + +#define BIT_DMA_MODE BIT(1) + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_C2H_PKT (Offset 0x0294) */ @@ -18202,7 +18330,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_C2H_PKT (Offset 0x0294) */ @@ -18234,7 +18362,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWFF_C2H (Offset 0x0298) */ @@ -18274,7 +18402,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ @@ -18320,7 +18448,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ @@ -18340,7 +18468,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ @@ -18382,7 +18510,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ @@ -18422,7 +18550,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ @@ -18457,7 +18585,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ @@ -18477,7 +18605,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ @@ -18512,7 +18640,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_INT_MIG (Offset 0x0304) */ @@ -18686,7 +18814,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ @@ -18706,7 +18834,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ @@ -18737,7 +18865,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ @@ -18757,7 +18885,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ @@ -18772,7 +18900,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ @@ -18792,7 +18920,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ @@ -18813,7 +18941,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ @@ -18833,7 +18961,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ @@ -18854,7 +18982,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ @@ -18874,7 +19002,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ @@ -18895,7 +19023,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ @@ -18915,7 +19043,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ @@ -19085,7 +19213,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19106,7 +19234,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19127,7 +19255,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19149,7 +19277,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19171,7 +19299,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19192,7 +19320,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19213,7 +19341,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ @@ -19254,7 +19382,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19276,7 +19404,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19298,7 +19426,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19319,7 +19447,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19340,7 +19468,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19361,7 +19489,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19388,7 +19516,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19410,7 +19538,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19431,7 +19559,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19458,7 +19586,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19481,7 +19609,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19503,7 +19631,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ @@ -19524,7 +19652,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ @@ -19552,7 +19680,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */ @@ -19768,7 +19896,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_DBG_SEL_V1 (Offset 0x03D8) */ @@ -19786,7 +19914,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_HRPWM1_V1 (Offset 0x03D9) */ @@ -19816,7 +19944,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_HCPWM1_V1 (Offset 0x03DA) */ @@ -19846,7 +19974,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ @@ -19876,7 +20004,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ @@ -19896,7 +20024,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ @@ -19907,7 +20035,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_HRPWM2_V1 (Offset 0x03DC) */ @@ -19937,7 +20065,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_HCPWM2_V1 (Offset 0x03DE) */ @@ -19967,7 +20095,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_H2C_MSG_V1 (Offset 0x03E0) */ @@ -19982,7 +20110,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_C2H_MSG_V1 (Offset 0x03E4) */ @@ -20012,7 +20140,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_DBI_WDATA_V1 (Offset 0x03E8) */ @@ -20053,30 +20181,6 @@ #define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR) -#endif - - -#if (HALMAC_8192E_SUPPORT) - - -/* 2 REG_MDIO_V1 (Offset 0x03F4) */ - -#define BIT_ECRC_EN BIT(39) -#define BIT_MDIO_RFLAG BIT(38) -#define BIT_MDIO_WFLAG BIT(37) - -#define BIT_SHIFT_MDIO_ADDR (32 & CPU_OPT_WIDTH) -#define BIT_MASK_MDIO_ADDR 0x1f -#define BIT_MDIO_ADDR(x) (((x) & BIT_MASK_MDIO_ADDR) << BIT_SHIFT_MDIO_ADDR) -#define BIT_GET_MDIO_ADDR(x) (((x) >> BIT_SHIFT_MDIO_ADDR) & BIT_MASK_MDIO_ADDR) - - -#endif - - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - /* 2 REG_MDIO_V1 (Offset 0x03F4) */ @@ -20111,13 +20215,40 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ #define BIT_EN_WATCH_DOG BIT(8) +#endif + + +#if (HALMAC_8192E_SUPPORT) + + +/* 2 REG_MDIO2_V1 (Offset 0x03F8) */ + +#define BIT_ECRC_EN BIT(7) +#define BIT_MDIO_RFLAG BIT(6) +#define BIT_MDIO_WFLAG BIT(5) + +#define BIT_SHIFT_MDIO_ADDR 0 +#define BIT_MASK_MDIO_ADDR 0x1f +#define BIT_MDIO_ADDR(x) (((x) & BIT_MASK_MDIO_ADDR) << BIT_SHIFT_MDIO_ADDR) +#define BIT_GET_MDIO_ADDR(x) (((x) >> BIT_SHIFT_MDIO_ADDR) & BIT_MASK_MDIO_ADDR) + + +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ + + #define BIT_SHIFT_MDIO_REG_ADDR_V1 0 #define BIT_MASK_MDIO_REG_ADDR_V1 0x1f #define BIT_MDIO_REG_ADDR_V1(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1) @@ -20173,7 +20304,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ @@ -20207,7 +20338,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ @@ -20218,7 +20349,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q0_INFO (Offset 0x0400) */ @@ -20239,7 +20370,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q0_INFO (Offset 0x0400) */ @@ -20264,7 +20395,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q0_INFO (Offset 0x0400) */ @@ -20300,7 +20431,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q0_INFO (Offset 0x0400) */ @@ -20315,7 +20446,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q1_INFO (Offset 0x0404) */ @@ -20336,7 +20467,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q1_INFO (Offset 0x0404) */ @@ -20361,7 +20492,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q1_INFO (Offset 0x0404) */ @@ -20397,7 +20528,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q1_INFO (Offset 0x0404) */ @@ -20412,7 +20543,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q2_INFO (Offset 0x0408) */ @@ -20433,7 +20564,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q2_INFO (Offset 0x0408) */ @@ -20458,7 +20589,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q2_INFO (Offset 0x0408) */ @@ -20494,7 +20625,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q2_INFO (Offset 0x0408) */ @@ -20509,7 +20640,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q3_INFO (Offset 0x040C) */ @@ -20530,7 +20661,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q3_INFO (Offset 0x040C) */ @@ -20555,7 +20686,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q3_INFO (Offset 0x040C) */ @@ -20591,7 +20722,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q3_INFO (Offset 0x040C) */ @@ -20606,7 +20737,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_INFO (Offset 0x0410) */ @@ -20627,7 +20758,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MGQ_INFO (Offset 0x0410) */ @@ -20652,7 +20783,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MGQ_INFO (Offset 0x0410) */ @@ -20688,7 +20819,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MGQ_INFO (Offset 0x0410) */ @@ -20703,7 +20834,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIQ_INFO (Offset 0x0414) */ @@ -20724,7 +20855,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIQ_INFO (Offset 0x0414) */ @@ -20749,7 +20880,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIQ_INFO (Offset 0x0414) */ @@ -20785,7 +20916,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIQ_INFO (Offset 0x0414) */ @@ -20821,7 +20952,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCNQ_INFO (Offset 0x0418) */ @@ -20836,7 +20967,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXPKT_EMPTY (Offset 0x041A) */ @@ -20857,7 +20988,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ @@ -20867,7 +20998,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ @@ -20878,7 +21009,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ @@ -20904,7 +21035,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ @@ -20919,7 +21050,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ @@ -20943,7 +21074,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ @@ -20953,7 +21084,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ @@ -20973,7 +21104,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ @@ -21008,7 +21139,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_DATAFB_SEL (Offset 0x0423) */ @@ -21029,7 +21160,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_DATAFB_SEL (Offset 0x0423) */ @@ -21059,7 +21190,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCNQ_BDNY_V1 (Offset 0x0424) */ @@ -21089,7 +21220,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LIFETIME_EN (Offset 0x0426) */ @@ -21111,7 +21242,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LIFETIME_EN (Offset 0x0426) */ @@ -21121,7 +21252,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LIFETIME_EN (Offset 0x0426) */ @@ -21149,7 +21280,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SPEC_SIFS (Offset 0x0428) */ @@ -21201,7 +21332,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ @@ -21211,7 +21342,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ @@ -21221,7 +21352,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ @@ -21352,7 +21483,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RRSR (Offset 0x0440) */ @@ -21400,7 +21531,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CCK_CHECK (Offset 0x0454) */ @@ -21422,7 +21553,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AMPDU_MAX_TIME (Offset 0x0456) */ @@ -21437,7 +21568,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCNQ1_BDNY_V1 (Offset 0x0456) */ @@ -21467,7 +21598,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AMPDU_MAX_LENGTH (Offset 0x0458) */ @@ -21508,7 +21639,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_NDPA_RATE (Offset 0x045D) */ @@ -21523,7 +21654,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ @@ -21533,7 +21664,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ @@ -21543,7 +21674,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ @@ -21554,7 +21685,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ @@ -21564,7 +21695,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ @@ -21594,7 +21725,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ @@ -21604,7 +21735,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ @@ -21667,7 +21798,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ @@ -21682,7 +21813,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ @@ -21727,7 +21858,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ @@ -21742,7 +21873,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ @@ -21767,7 +21898,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ @@ -21803,7 +21934,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ @@ -21818,7 +21949,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q4_INFO (Offset 0x0468) */ @@ -21839,7 +21970,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q4_INFO (Offset 0x0468) */ @@ -21864,7 +21995,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q4_INFO (Offset 0x0468) */ @@ -21900,7 +22031,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q4_INFO (Offset 0x0468) */ @@ -21915,7 +22046,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q5_INFO (Offset 0x046C) */ @@ -21936,7 +22067,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q5_INFO (Offset 0x046C) */ @@ -21961,7 +22092,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q5_INFO (Offset 0x046C) */ @@ -21997,7 +22128,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q5_INFO (Offset 0x046C) */ @@ -22012,7 +22143,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q6_INFO (Offset 0x0470) */ @@ -22033,7 +22164,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q6_INFO (Offset 0x0470) */ @@ -22058,7 +22189,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q6_INFO (Offset 0x0470) */ @@ -22094,7 +22225,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q6_INFO (Offset 0x0470) */ @@ -22109,7 +22240,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q7_INFO (Offset 0x0474) */ @@ -22130,7 +22261,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q7_INFO (Offset 0x0474) */ @@ -22155,7 +22286,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q7_INFO (Offset 0x0474) */ @@ -22191,7 +22322,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q7_INFO (Offset 0x0474) */ @@ -22239,7 +22370,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ @@ -22269,7 +22400,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ @@ -22299,7 +22430,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ @@ -22329,7 +22460,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ @@ -22344,7 +22475,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_INIRTS_RATE_SEL (Offset 0x0480) */ @@ -22476,7 +22607,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ @@ -22521,7 +22652,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ @@ -22556,6 +22687,21 @@ #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ + + +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL 12 +#define BIT_MASK_BFRPT_PARA_USERID_SEL 0x7 +#define BIT_BFRPT_PARA_USERID_SEL(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL) << BIT_SHIFT_BFRPT_PARA_USERID_SEL) +#define BIT_GET_BFRPT_PARA_USERID_SEL(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL) & BIT_MASK_BFRPT_PARA_USERID_SEL) + + +#endif + + #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) @@ -22571,7 +22717,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ @@ -22601,7 +22747,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ @@ -22655,7 +22801,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ @@ -22672,7 +22818,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ @@ -22687,7 +22833,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ @@ -22697,7 +22843,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ @@ -22721,7 +22867,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ @@ -22740,7 +22886,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ @@ -22750,7 +22896,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ @@ -22815,7 +22961,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ @@ -22826,7 +22972,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ @@ -22892,7 +23038,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RA_TRY_RATE_AGG_LMT (Offset 0x04CF) */ @@ -22907,7 +23053,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MACID_SLEEP2 (Offset 0x04D0) */ @@ -22931,7 +23077,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HW_SEQ0 (Offset 0x04D8) */ @@ -22979,7 +23125,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HW_SEQ3 (Offset 0x04DE) */ @@ -23024,7 +23170,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ @@ -23039,7 +23185,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_NULL_PKT_STATUS (Offset 0x04E0) */ @@ -23050,7 +23196,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ @@ -23061,7 +23207,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ @@ -23076,7 +23222,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ @@ -23107,7 +23253,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ @@ -23132,7 +23278,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ @@ -23143,7 +23289,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BT_POLLUTE_PKT_CNT (Offset 0x04E8) */ @@ -23192,7 +23338,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CPUMGQ_TIMER_CTRL2 (Offset 0x04F4) */ @@ -23299,7 +23445,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MOREDATA (Offset 0x04FE) */ @@ -23311,7 +23457,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_EDCA_VO_PARAM (Offset 0x0500) */ @@ -23477,7 +23623,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ @@ -23497,7 +23643,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RD_CTRL (Offset 0x0524) */ @@ -23518,7 +23664,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RD_CTRL (Offset 0x0524) */ @@ -23567,7 +23713,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_P2PPS_CTRL (Offset 0x0527) */ @@ -23588,7 +23734,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ @@ -23608,7 +23754,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ @@ -23765,7 +23911,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ @@ -23795,7 +23941,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ @@ -23887,7 +24033,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BCN_CTRL (Offset 0x0550) */ @@ -23897,7 +24043,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL (Offset 0x0550) */ @@ -23907,7 +24053,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BCN_CTRL (Offset 0x0550) */ @@ -23928,7 +24074,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL (Offset 0x0550) */ @@ -23948,7 +24094,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL (Offset 0x0550) */ @@ -23969,7 +24115,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ @@ -23989,7 +24135,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ @@ -24009,7 +24155,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ @@ -24029,7 +24175,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ @@ -24059,7 +24205,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ @@ -24070,7 +24216,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBID_NUM (Offset 0x0552) */ @@ -24097,7 +24243,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ @@ -24117,7 +24263,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ @@ -24137,7 +24283,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ @@ -24157,7 +24303,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ @@ -24177,7 +24323,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ @@ -24187,7 +24333,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ @@ -24197,7 +24343,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ @@ -24227,7 +24373,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ @@ -24242,7 +24388,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ @@ -24290,7 +24436,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_ATIMWND (Offset 0x055A) */ @@ -24305,7 +24451,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_USTIME_TSF (Offset 0x055C) */ @@ -24344,6 +24490,12 @@ #define BIT_GET_OFDM_RXTSF_OFFSET(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET) +#endif + + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + + /* 2 REG_TSFTR (Offset 0x0560) */ @@ -24356,6 +24508,30 @@ #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_TSFTR (Offset 0x0560) */ + + +#define BIT_SHIFT_TSF_TIMER_V1 0 +#define BIT_MASK_TSF_TIMER_V1 0xffffffffL +#define BIT_TSF_TIMER_V1(x) (((x) & BIT_MASK_TSF_TIMER_V1) << BIT_SHIFT_TSF_TIMER_V1) +#define BIT_GET_TSF_TIMER_V1(x) (((x) >> BIT_SHIFT_TSF_TIMER_V1) & BIT_MASK_TSF_TIMER_V1) + + +/* 2 REG_TSFTR_1 (Offset 0x0564) */ + + +#define BIT_SHIFT_TSF_TIMER_V2 0 +#define BIT_MASK_TSF_TIMER_V2 0xffffffffL +#define BIT_TSF_TIMER_V2(x) (((x) & BIT_MASK_TSF_TIMER_V2) << BIT_SHIFT_TSF_TIMER_V2) +#define BIT_GET_TSF_TIMER_V2(x) (((x) >> BIT_SHIFT_TSF_TIMER_V2) & BIT_MASK_TSF_TIMER_V2) + + +#endif + + #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) @@ -24371,7 +24547,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FREERUN_CNT (Offset 0x0568) */ @@ -24386,6 +24562,30 @@ #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_FREERUN_CNT (Offset 0x0568) */ + + +#define BIT_SHIFT_FREERUN_CNT_V1 0 +#define BIT_MASK_FREERUN_CNT_V1 0xffffffffL +#define BIT_FREERUN_CNT_V1(x) (((x) & BIT_MASK_FREERUN_CNT_V1) << BIT_SHIFT_FREERUN_CNT_V1) +#define BIT_GET_FREERUN_CNT_V1(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V1) & BIT_MASK_FREERUN_CNT_V1) + + +/* 2 REG_FREERUN_CNT_1 (Offset 0x056C) */ + + +#define BIT_SHIFT_FREERUN_CNT_V2 0 +#define BIT_MASK_FREERUN_CNT_V2 0xffffffffL +#define BIT_FREERUN_CNT_V2(x) (((x) & BIT_MASK_FREERUN_CNT_V2) << BIT_SHIFT_FREERUN_CNT_V2) +#define BIT_GET_FREERUN_CNT_V2(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V2) & BIT_MASK_FREERUN_CNT_V2) + + +#endif + + #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) @@ -24401,7 +24601,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_ATIMWND1_V1 (Offset 0x0570) */ @@ -24425,7 +24625,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CTWND (Offset 0x0572) */ @@ -24468,7 +24668,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXCMD_TIMEOUT_PERIOD (Offset 0x0576) */ @@ -24494,7 +24694,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MISC_CTRL (Offset 0x0577) */ @@ -24519,7 +24719,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ @@ -24539,7 +24739,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ @@ -24556,7 +24756,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ @@ -24576,7 +24776,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ @@ -24593,7 +24793,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ @@ -24613,7 +24813,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ @@ -24624,7 +24824,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_EXTEND_CTRL (Offset 0x057B) */ @@ -24641,7 +24841,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ @@ -24706,7 +24906,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PS_TIMER0 (Offset 0x0580) */ @@ -24751,7 +24951,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PS_TIMER1 (Offset 0x0584) */ @@ -24781,7 +24981,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PS_TIMER2 (Offset 0x0588) */ @@ -24796,7 +24996,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TBTT_CTN_AREA (Offset 0x058C) */ @@ -24831,7 +25031,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXOP_MIN (Offset 0x0590) */ @@ -24855,7 +25055,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ @@ -24865,7 +25065,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ @@ -24928,7 +25128,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_ATIMWND2 (Offset 0x05A0) */ @@ -25091,7 +25291,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_EARLY_128US (Offset 0x05B1) */ @@ -25228,7 +25428,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ @@ -25265,7 +25465,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ @@ -25307,7 +25507,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_ACMHWCTRL (Offset 0x05C0) */ @@ -25384,7 +25584,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ @@ -25409,7 +25609,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ @@ -25421,6 +25621,12 @@ #define BIT_GET_TXCMD_SEG_SEL(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL) +#endif + + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + + /* 2 REG_NOA_PARAM (Offset 0x05E0) */ @@ -25451,6 +25657,48 @@ #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_NOA_PARAM (Offset 0x05E0) */ + + +#define BIT_SHIFT_NOA_DURATION_V1 0 +#define BIT_MASK_NOA_DURATION_V1 0xffffffffL +#define BIT_NOA_DURATION_V1(x) (((x) & BIT_MASK_NOA_DURATION_V1) << BIT_SHIFT_NOA_DURATION_V1) +#define BIT_GET_NOA_DURATION_V1(x) (((x) >> BIT_SHIFT_NOA_DURATION_V1) & BIT_MASK_NOA_DURATION_V1) + + +/* 2 REG_NOA_PARAM_1 (Offset 0x05E4) */ + + +#define BIT_SHIFT_NOA_INTERVAL_V1 0 +#define BIT_MASK_NOA_INTERVAL_V1 0xffffffffL +#define BIT_NOA_INTERVAL_V1(x) (((x) & BIT_MASK_NOA_INTERVAL_V1) << BIT_SHIFT_NOA_INTERVAL_V1) +#define BIT_GET_NOA_INTERVAL_V1(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_V1) & BIT_MASK_NOA_INTERVAL_V1) + + +/* 2 REG_NOA_PARAM_2 (Offset 0x05E8) */ + + +#define BIT_SHIFT_NOA_START_TIME_V1 0 +#define BIT_MASK_NOA_START_TIME_V1 0xffffffffL +#define BIT_NOA_START_TIME_V1(x) (((x) & BIT_MASK_NOA_START_TIME_V1) << BIT_SHIFT_NOA_START_TIME_V1) +#define BIT_GET_NOA_START_TIME_V1(x) (((x) >> BIT_SHIFT_NOA_START_TIME_V1) & BIT_MASK_NOA_START_TIME_V1) + + +/* 2 REG_NOA_PARAM_3 (Offset 0x05EC) */ + + +#define BIT_SHIFT_NOA_COUNT_V1 0 +#define BIT_MASK_NOA_COUNT_V1 0xffffffffL +#define BIT_NOA_COUNT_V1(x) (((x) & BIT_MASK_NOA_COUNT_V1) << BIT_SHIFT_NOA_COUNT_V1) +#define BIT_GET_NOA_COUNT_V1(x) (((x) >> BIT_SHIFT_NOA_COUNT_V1) & BIT_MASK_NOA_COUNT_V1) + + +#endif + + #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) @@ -25477,7 +25725,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_P2P_RST (Offset 0x05F0) */ @@ -25503,7 +25751,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ @@ -25529,7 +25777,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SCH_TXCMD (Offset 0x05F8) */ @@ -25574,7 +25822,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_CR (Offset 0x0600) */ @@ -25584,7 +25832,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ @@ -25594,7 +25842,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ @@ -25604,7 +25852,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ @@ -25621,7 +25869,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_FW_STS_FILTER (Offset 0x0602) */ @@ -25633,7 +25881,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ @@ -25649,7 +25897,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ @@ -25669,7 +25917,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ @@ -25704,7 +25952,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ @@ -25714,7 +25962,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ @@ -25727,7 +25975,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ @@ -25748,7 +25996,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ @@ -25758,7 +26006,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ @@ -25789,7 +26037,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ @@ -25803,7 +26051,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ @@ -25813,7 +26061,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ @@ -25844,7 +26092,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ @@ -25864,7 +26112,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ @@ -25874,7 +26122,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ @@ -25912,12 +26160,19 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ -#define BIT_BITMAP_VO BIT(7) +#define BIT_DATA_RPFM15EN BIT(15) +#define BIT_DATA_RPFM14EN BIT(14) +#define BIT_DATA_RPFM13EN BIT(13) +#define BIT_DATA_RPFM12EN BIT(12) +#define BIT_DATA_RPFM11EN BIT(11) +#define BIT_DATA_RPFM10EN BIT(10) +#define BIT_DATA_RPFM9EN BIT(9) +#define BIT_DATA_RPFM8EN BIT(8) #endif @@ -25932,22 +26187,13 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ #define BIT_PHYSTS_PER_PKT_MODE BIT(7) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ - -#define BIT_BITMAP_VI BIT(6) +#define BIT_DATA_RPFM7EN BIT(7) #endif @@ -25962,12 +26208,12 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ -#define BIT_BITMAP_BE BIT(5) +#define BIT_DATA_RPFM6EN BIT(6) #endif @@ -25982,19 +26228,16 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ -#define BIT_BITMAP_BK BIT(4) - -#define BIT_SHIFT_BITMAP_CONDITION 2 -#define BIT_MASK_BITMAP_CONDITION 0x3 -#define BIT_BITMAP_CONDITION(x) (((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION) -#define BIT_GET_BITMAP_CONDITION(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION) - -#define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1) +#define BIT_DATA_RPFM5EN BIT(5) +#define BIT_DATA_RPFM4EN BIT(4) +#define BIT_DATA_RPFM3EN BIT(3) +#define BIT_DATA_RPFM2EN BIT(2) +#define BIT_DATA_RPFM1EN BIT(1) #endif @@ -26014,7 +26257,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ @@ -26025,12 +26268,21 @@ #define BIT_DRVINFO_SZ_V1(x) (((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1) #define BIT_GET_DRVINFO_SZ_V1(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1) -#define BIT_BITMAP_FORCE BIT(0) #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ + +#define BIT_DATA_RPFM0EN BIT(0) + +#endif + + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MACID (Offset 0x0610) */ @@ -26085,7 +26337,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ @@ -26105,7 +26357,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ @@ -26135,7 +26387,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_TCR_TSFT_OFS (Offset 0x0630) */ @@ -26183,7 +26435,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_STMP_THSD (Offset 0x0634) */ @@ -26231,7 +26483,7 @@ #endif -#if (HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_USTIME_EDCA (Offset 0x0638) */ @@ -26246,7 +26498,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_ACKTO_CCK (Offset 0x0639) */ @@ -26261,7 +26513,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MAC_SPEC_SIFS (Offset 0x063A) */ @@ -26339,7 +26591,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_RPFM_MAP0 (Offset 0x0644) */ @@ -26385,7 +26637,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_NAV_CTRL (Offset 0x0650) */ @@ -26454,7 +26706,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ @@ -26470,7 +26722,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ @@ -26480,7 +26732,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TX_RX (Offset 0x0662) */ @@ -26494,10 +26746,25 @@ #define BIT_TXACT_IND BIT(1) #define BIT_RXACT_IND BIT(0) +/* 2 REG_WMAC_BITMAP_CTL (Offset 0x0663) */ + +#define BIT_BITMAP_VO BIT(7) +#define BIT_BITMAP_VI BIT(6) +#define BIT_BITMAP_BE BIT(5) +#define BIT_BITMAP_BK BIT(4) + +#define BIT_SHIFT_BITMAP_CONDITION 2 +#define BIT_MASK_BITMAP_CONDITION 0x3 +#define BIT_BITMAP_CONDITION(x) (((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION) +#define BIT_GET_BITMAP_CONDITION(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION) + +#define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1) +#define BIT_BITMAP_FORCE BIT(0) + #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ @@ -26527,7 +26794,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ @@ -26537,7 +26804,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ @@ -26562,7 +26829,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ @@ -26572,7 +26839,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ @@ -26592,7 +26859,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ @@ -26646,7 +26913,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ @@ -26658,7 +26925,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ @@ -26693,7 +26960,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ @@ -26705,7 +26972,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ @@ -26735,7 +27002,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ @@ -26765,7 +27032,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ @@ -26795,7 +27062,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ @@ -26815,7 +27082,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ @@ -26845,7 +27112,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ @@ -26860,7 +27127,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CAMCMD (Offset 0x0670) */ @@ -26872,7 +27139,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CAMCMD (Offset 0x0670) */ @@ -26903,7 +27170,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CAMCMD (Offset 0x0670) */ @@ -26933,7 +27200,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CAMWRITE (Offset 0x0674) */ @@ -26978,7 +27245,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ @@ -26988,7 +27255,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ @@ -27015,7 +27282,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SECCFG (Offset 0x0680) */ @@ -27036,7 +27303,7 @@ #endif -#if (HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SECCFG (Offset 0x0680) */ @@ -27046,7 +27313,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SECCFG (Offset 0x0680) */ @@ -27064,7 +27331,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RXFILTER_CATEGORY_1 (Offset 0x0682) */ @@ -27200,7 +27467,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ @@ -27215,7 +27482,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ @@ -27235,7 +27502,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ @@ -27245,7 +27512,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ @@ -27258,7 +27525,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_NAN_RX_TSF_FILTER (Offset 0x0691) */ @@ -27279,7 +27546,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PS_RX_INFO (Offset 0x0692) */ @@ -27320,7 +27587,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ @@ -27331,7 +27598,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ @@ -27341,7 +27608,7 @@ #endif -#if (HALMAC_8197F_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ @@ -27353,30 +27620,6 @@ #define BIT_GET_WKFCAM_ADDR_V2(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2) -#endif - - -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ - - -#define BIT_SHIFT_WKFCAM_ADDR_V1 7 -#define BIT_MASK_WKFCAM_ADDR_V1 0x1ff -#define BIT_WKFCAM_ADDR_V1(x) (((x) & BIT_MASK_WKFCAM_ADDR_V1) << BIT_SHIFT_WKFCAM_ADDR_V1) -#define BIT_GET_WKFCAM_ADDR_V1(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V1) & BIT_MASK_WKFCAM_ADDR_V1) - - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ - - #define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0 #define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff #define BIT_WKFCAM_CAM_NUM_V1(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1) @@ -27401,7 +27644,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WKFMCAM_RWD (Offset 0x069C) */ @@ -27421,7 +27664,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ @@ -27436,7 +27679,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ @@ -27447,7 +27690,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ @@ -27475,7 +27718,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RXFLTMAP1 (Offset 0x06A2) */ @@ -27490,7 +27733,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXFLTMAP (Offset 0x06A4) */ @@ -27538,7 +27781,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FLC_RPC (Offset 0x06AC) */ @@ -27579,7 +27822,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RXPKTMON_CTRL (Offset 0x06B0) */ @@ -27634,7 +27877,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_STATE_MON (Offset 0x06B4) */ @@ -27671,7 +27914,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_STATE_MON (Offset 0x06B4) */ @@ -27705,7 +27948,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ @@ -27715,7 +27958,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ @@ -27732,7 +27975,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */ @@ -27797,7 +28040,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RXCMD_0 (Offset 0x06D0) */ @@ -27858,7 +28101,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ @@ -27914,7 +28157,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ @@ -27929,7 +28172,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ @@ -27939,7 +28182,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ @@ -27961,7 +28204,28 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ + +#define BIT_CSI_FORCE_RATE_EN BIT(15) + +#define BIT_SHIFT_CSI_RSC 13 +#define BIT_MASK_CSI_RSC 0x3 +#define BIT_CSI_RSC(x) (((x) & BIT_MASK_CSI_RSC) << BIT_SHIFT_CSI_RSC) +#define BIT_GET_CSI_RSC(x) (((x) >> BIT_SHIFT_CSI_RSC) & BIT_MASK_CSI_RSC) + +#define BIT_CSI_GID_SEL BIT(12) +#define BIT_RDCSIMD_FLAG_TRIG_SEL BIT(11) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS BIT(10) +#define BIT_NDPVLD_PROTECT_RDRDY_DIS BIT(9) +#define BIT_RDCSI_EMPTY_APPZERO BIT(8) + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ @@ -27971,7 +28235,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ @@ -27988,7 +28252,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ @@ -27998,7 +28262,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ @@ -28023,7 +28287,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ @@ -28104,7 +28368,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ @@ -28140,7 +28404,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MACID1 (Offset 0x0700) */ @@ -28155,7 +28419,31 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_MACID1 (Offset 0x0700) */ + + +#define BIT_SHIFT_MACID1_0 0 +#define BIT_MASK_MACID1_0 0xffffffffL +#define BIT_MACID1_0(x) (((x) & BIT_MASK_MACID1_0) << BIT_SHIFT_MACID1_0) +#define BIT_GET_MACID1_0(x) (((x) >> BIT_SHIFT_MACID1_0) & BIT_MASK_MACID1_0) + + +/* 2 REG_MACID1_1 (Offset 0x0704) */ + + +#define BIT_SHIFT_MACID1_1 0 +#define BIT_MASK_MACID1_1 0xffff +#define BIT_MACID1_1(x) (((x) & BIT_MASK_MACID1_1) << BIT_SHIFT_MACID1_1) +#define BIT_GET_MACID1_1(x) (((x) >> BIT_SHIFT_MACID1_1) & BIT_MASK_MACID1_1) + + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BSSID1 (Offset 0x0708) */ @@ -28167,6 +28455,36 @@ #define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1) +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_BSSID1 (Offset 0x0708) */ + + +#define BIT_SHIFT_BSSID1_0 0 +#define BIT_MASK_BSSID1_0 0xffffffffL +#define BIT_BSSID1_0(x) (((x) & BIT_MASK_BSSID1_0) << BIT_SHIFT_BSSID1_0) +#define BIT_GET_BSSID1_0(x) (((x) >> BIT_SHIFT_BSSID1_0) & BIT_MASK_BSSID1_0) + + +/* 2 REG_BSSID1_1 (Offset 0x070C) */ + + +#define BIT_SHIFT_BSSID1_1 0 +#define BIT_MASK_BSSID1_1 0xffff +#define BIT_BSSID1_1(x) (((x) & BIT_MASK_BSSID1_1) << BIT_SHIFT_BSSID1_1) +#define BIT_GET_BSSID1_1(x) (((x) >> BIT_SHIFT_BSSID1_1) & BIT_MASK_BSSID1_1) + + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + /* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ @@ -28208,7 +28526,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */ @@ -28261,7 +28579,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ @@ -28276,7 +28594,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ @@ -28334,7 +28652,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_NS_ARP_CTRL (Offset 0x0720) */ @@ -28364,7 +28682,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_NS_ARP_INFO (Offset 0x0724) */ @@ -28396,7 +28714,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BEAMFORMING_INFO_NSARP_V1 (Offset 0x0728) */ @@ -28411,7 +28729,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ @@ -28423,16 +28741,52 @@ #define BIT_GET_BEAMFORMING_INFO(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO) -#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0 -#define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) -#define BIT_GET_R_WMAC_IPV6_MYIPAD(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD) +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_IPV6 (Offset 0x0730) */ + + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_0(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_0(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0) + + +/* 2 REG_IPV6_1 (Offset 0x0734) */ + + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_1(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_1(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1) + + +/* 2 REG_IPV6_2 (Offset 0x0738) */ + + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_2(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_2(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2) + + +/* 2 REG_IPV6_3 (Offset 0x073C) */ + + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_3(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_3(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3) #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG (Offset 0x0750) */ @@ -28475,6 +28829,12 @@ #define BIT_GET_R_BT_CNT_THR(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR) +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + + /* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ #define BIT_WLRX_TER_BY_CTL BIT(43) @@ -28487,7 +28847,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8822B_SUPPORT) /* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ @@ -28497,7 +28857,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ @@ -28515,6 +28875,28 @@ #define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1) +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_WLAN_ACT_MASK_CTRL_1 (Offset 0x076C) */ + +#define BIT_WLRX_TER_BY_CTL_1 BIT(11) +#define BIT_WLRX_TER_BY_AD_1 BIT(10) +#define BIT_ANT_DIVERSITY_SEL_1 BIT(9) +#define BIT_ANTSEL_FOR_BT_CTRL_EN_1 BIT(8) +#define BIT_WLACT_LOW_GNTWL_EN_1 BIT(2) +#define BIT_WLACT_HIGH_GNTBT_EN_1 BIT(1) +#define BIT_NAV_UPPER_1_V1 BIT(0) + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + /* 2 REG_BT_COEX_ENHANCED_INTR_CTRL (Offset 0x076E) */ @@ -28540,6 +28922,12 @@ #define BIT_WL_ACT_MASK_ENABLE BIT(1) #define BIT_ENHANCED_BT BIT(0) +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + + /* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ @@ -28555,6 +28943,15 @@ #define BIT_GET_STATIS_BT_LO_TX(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX) +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ + + #define BIT_SHIFT_STATIS_BT_HI_RX 16 #define BIT_MASK_STATIS_BT_HI_RX 0xffff #define BIT_STATIS_BT_HI_RX(x) (((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX) @@ -28567,6 +28964,33 @@ #define BIT_GET_STATIS_BT_HI_TX(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX) +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_BT_ACT_STATISTICS_1 (Offset 0x0774) */ + + +#define BIT_SHIFT_STATIS_BT_LO_RX_1 16 +#define BIT_MASK_STATIS_BT_LO_RX_1 0xffff +#define BIT_STATIS_BT_LO_RX_1(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_1) << BIT_SHIFT_STATIS_BT_LO_RX_1) +#define BIT_GET_STATIS_BT_LO_RX_1(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1) & BIT_MASK_STATIS_BT_LO_RX_1) + + +#define BIT_SHIFT_STATIS_BT_LO_TX_1 0 +#define BIT_MASK_STATIS_BT_LO_TX_1 0xffff +#define BIT_STATIS_BT_LO_TX_1(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_1) << BIT_SHIFT_STATIS_BT_LO_TX_1) +#define BIT_GET_STATIS_BT_LO_TX_1(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1) & BIT_MASK_STATIS_BT_LO_TX_1) + + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + /* 2 REG_BT_STATISTICS_CONTROL_REGISTER (Offset 0x0778) */ @@ -28659,6 +29083,12 @@ #define BIT_GET_WLAN_RPT_TO(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO) +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + + /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ @@ -28667,8 +29097,62 @@ #define BIT_ISOLATION_CHK(x) (((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK) #define BIT_GET_ISOLATION_CHK(x) (((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK) + +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ + + +#define BIT_SHIFT_ISOLATION_CHK_0 1 +#define BIT_MASK_ISOLATION_CHK_0 0x7fffff +#define BIT_ISOLATION_CHK_0(x) (((x) & BIT_MASK_ISOLATION_CHK_0) << BIT_SHIFT_ISOLATION_CHK_0) +#define BIT_GET_ISOLATION_CHK_0(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_0) & BIT_MASK_ISOLATION_CHK_0) + + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ + #define BIT_ISOLATION_EN BIT(0) +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 (Offset 0x0788) */ + + +#define BIT_SHIFT_ISOLATION_CHK_1 0 +#define BIT_MASK_ISOLATION_CHK_1 0xffffffffL +#define BIT_ISOLATION_CHK_1(x) (((x) & BIT_MASK_ISOLATION_CHK_1) << BIT_SHIFT_ISOLATION_CHK_1) +#define BIT_GET_ISOLATION_CHK_1(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_1) & BIT_MASK_ISOLATION_CHK_1) + + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 (Offset 0x078C) */ + + +#define BIT_SHIFT_ISOLATION_CHK_2 0 +#define BIT_MASK_ISOLATION_CHK_2 0xffffff +#define BIT_ISOLATION_CHK_2(x) (((x) & BIT_MASK_ISOLATION_CHK_2) << BIT_SHIFT_ISOLATION_CHK_2) +#define BIT_GET_ISOLATION_CHK_2(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_2) & BIT_MASK_ISOLATION_CHK_2) + + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + /* 2 REG_BT_INTERRUPT_STATUS_REGISTER (Offset 0x078F) */ #define BIT_BT_HID_ISR BIT(7) @@ -28888,6 +29372,12 @@ #define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L) +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + + /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ #define BIT_APPEND_MACID_IN_RESP_EN BIT(50) @@ -28903,7 +29393,34 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ + + +#define BIT_SHIFT_TRAIN_STA_ADDR_0 0 +#define BIT_MASK_TRAIN_STA_ADDR_0 0xffffffffL +#define BIT_TRAIN_STA_ADDR_0(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_0) << BIT_SHIFT_TRAIN_STA_ADDR_0) +#define BIT_GET_TRAIN_STA_ADDR_0(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0) & BIT_MASK_TRAIN_STA_ADDR_0) + + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 (Offset 0x07B4) */ + +#define BIT_APPEND_MACID_IN_RESP_EN_1 BIT(18) +#define BIT_ADDR2_MATCH_EN_1 BIT(17) +#define BIT_ANTTRN_EN_1 BIT(16) + +#define BIT_SHIFT_TRAIN_STA_ADDR_1 0 +#define BIT_MASK_TRAIN_STA_ADDR_1 0xffff +#define BIT_TRAIN_STA_ADDR_1(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_1) << BIT_SHIFT_TRAIN_STA_ADDR_1) +#define BIT_GET_TRAIN_STA_ADDR_1(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1) & BIT_MASK_TRAIN_STA_ADDR_1) + + +#endif + + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_PKTCNT_RWD (Offset 0x07B8) */ @@ -28931,7 +29448,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_IQ_DUMP (Offset 0x07C0) */ @@ -28981,6 +29498,15 @@ #define BIT_R_WMAC_CHK_CCK_LEN BIT(32) +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_IQ_DUMP (Offset 0x07C0) */ + + #define BIT_SHIFT_R_OFDM_LEN 26 #define BIT_MASK_R_OFDM_LEN 0x3f #define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN) @@ -29024,15 +29550,35 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_IQ_DUMP_1 (Offset 0x07C4) */ + + +#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1 0 +#define BIT_MASK_R_WMAC_MASK_LA_MAC_1 0xffffffffL +#define BIT_R_WMAC_MASK_LA_MAC_1(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) +#define BIT_GET_R_WMAC_MASK_LA_MAC_1(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) & BIT_MASK_R_WMAC_MASK_LA_MAC_1) + + +/* 2 REG_IQ_DUMP_2 (Offset 0x07C8) */ + + +#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2 0 +#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2 0xffffffffL +#define BIT_R_WMAC_MATCH_REF_MAC_2(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_2(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2) + + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ -#define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55) -#define BIT_R_WMAC_RXRST_DLY BIT(54) -#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53) -#define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52) #define BIT_RXFTM_TXACK_SC BIT(6) #define BIT_RXFTM_TXACK_BW BIT(5) #define BIT_RXFTM_EN BIT(3) @@ -29074,42 +29620,70 @@ #endif -#if (HALMAC_8197F_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +/* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */ -#define BIT_R_WMAC_RXHANG_EN BIT(15) -#endif +#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1 24 +#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 0xff +#define BIT_R_WMAC_RXFIFO_FULL_TH_1(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) +#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1 BIT(23) +#define BIT_R_WMAC_RXRST_DLY_1 BIT(22) +#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1 BIT(21) +#define BIT_R_WMAC_SRCH_TXRPT_UA1_1 BIT(20) +#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1 BIT(19) +#define BIT_R_WMAC_NDP_RST_1 BIT(18) +#define BIT_R_WMAC_POWINT_EN_1 BIT(17) +#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1 BIT(16) +#define BIT_R_WMAC_SRCH_TXRPT_MID_1 BIT(15) +#define BIT_R_WMAC_PFIN_TOEN_1 BIT(14) +#define BIT_R_WMAC_FIL_SECERR_1 BIT(13) +#define BIT_R_WMAC_FIL_CTLPKTLEN_1 BIT(12) +#define BIT_R_WMAC_FIL_FCTYPE_1 BIT(11) +#define BIT_R_WMAC_FIL_FCPROVER_1 BIT(10) +#define BIT_R_WMAC_PHYSTS_SNIF_1 BIT(9) +#define BIT_R_WMAC_PHYSTS_PLCP_1 BIT(8) +#define BIT_R_MAC_TCR_VBONF_RD_1 BIT(7) +#define BIT_R_WMAC_TCR_MPAR_NDP_1 BIT(6) +#define BIT_R_WMAC_NDP_FILTER_1 BIT(5) +#define BIT_R_WMAC_RXLEN_SEL_1 BIT(4) +#define BIT_R_WMAC_RXLEN_SEL1_1 BIT(3) +#define BIT_R_OFDM_FILTER_1 BIT(2) +#define BIT_R_WMAC_CHK_OFDM_LEN_1 BIT(1) +#define BIT_R_WMAC_CHK_CCK_LEN_1 BIT(0) -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_OPTION_FUNCTION_2 (Offset 0x07D8) */ -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2 0 +#define BIT_MASK_R_WMAC_RX_FIL_LEN_2 0xffff +#define BIT_R_WMAC_RX_FIL_LEN_2(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) +#define BIT_GET_R_WMAC_RX_FIL_LEN_2(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) -#define BIT_DATA_RPFM15EN BIT(15) #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ -#define BIT_R_WMAC_MHRDDY_LATCH BIT(14) +#define BIT_R_WMAC_RXHANG_EN BIT(15) #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ -#define BIT_DATA_RPFM14EN BIT(14) +#define BIT_R_WMAC_MHRDDY_LATCH BIT(14) #endif @@ -29124,18 +29698,17 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ #define BIT_R_WMAC_MHRDDY_CLR BIT(13) -#define BIT_DATA_RPFM13EN BIT(13) #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ @@ -29145,16 +29718,6 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - -#define BIT_DATA_RPFM12EN BIT(12) - -#endif - - #if (HALMAC_8197F_SUPPORT) @@ -29165,258 +29728,72 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ #define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) -#define BIT_DATA_RPFM11EN BIT(11) #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ #define BIT_R_CHK_DELIMIT_LEN BIT(10) - -#endif - - -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - -#define BIT_DATA_RPFM10EN BIT(10) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - #define BIT_R_REAPTER_ADDR_MATCH BIT(9) - -#endif - - -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - -#define BIT_DATA_RPFM9EN BIT(9) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - #define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8) - -#endif - - -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - -#define BIT_DATA_RPFM8EN BIT(8) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - #define BIT_R_LATCH_MACHRDY BIT(7) - -#endif - - -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - -#define BIT_DATA_RPFM7EN BIT(7) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - #define BIT_R_WMAC_RXFIL_REND BIT(6) - -#endif - - -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - -#define BIT_DATA_RPFM6EN BIT(6) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - #define BIT_R_WMAC_MPDURDY_CLR BIT(5) - -#endif - - -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - -#define BIT_DATA_RPFM5EN BIT(5) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - #define BIT_R_WMAC_CLRRXSEC BIT(4) - -#endif - - -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - -#define BIT_DATA_RPFM4EN BIT(4) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - #define BIT_R_WMAC_RXFIL_RDEL BIT(3) - -#endif - - -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - -#define BIT_DATA_RPFM3EN BIT(3) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - #define BIT_R_WMAC_RXFIL_FCSE BIT(2) - -#endif - - -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - -#define BIT_DATA_RPFM2EN BIT(2) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - #define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1) +#define BIT_R_WMAC_RXFIL_MASKM BIT(0) #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - -#define BIT_DATA_RPFM1EN BIT(1) - -#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_NDP_SIG (Offset 0x07E0) */ -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0 +#define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff +#define BIT_R_WMAC_TXNDP_SIGB(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB) +#define BIT_GET_R_WMAC_TXNDP_SIGB(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB) -#define BIT_R_WMAC_RXFIL_MASKM BIT(0) #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ - -#define BIT_DATA_RPFM0EN BIT(0) - -#endif +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH) +#define BIT_MASK_R_MAC_DEBUG 0xffffffffL +#define BIT_R_MAC_DEBUG(x) (((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG) +#define BIT_GET_R_MAC_DEBUG(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG) -/* 2 REG_NDP_SIG (Offset 0x07E0) */ +#endif -#define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0 -#define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff -#define BIT_R_WMAC_TXNDP_SIGB(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB) -#define BIT_GET_R_WMAC_TXNDP_SIGB(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ -#define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH) -#define BIT_MASK_R_MAC_DEBUG 0xffffffffL -#define BIT_R_MAC_DEBUG(x) (((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG) -#define BIT_GET_R_MAC_DEBUG(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG) - - #define BIT_SHIFT_R_MAC_DBG_SHIFT 8 #define BIT_MASK_R_MAC_DBG_SHIFT 0x7 #define BIT_R_MAC_DBG_SHIFT(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT) @@ -29432,7 +29809,16 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1 (Offset 0x07E8) */ + + +#define BIT_SHIFT_R_MAC_DEBUG_1 0 +#define BIT_MASK_R_MAC_DEBUG_1 0xffffffffL +#define BIT_R_MAC_DEBUG_1(x) (((x) & BIT_MASK_R_MAC_DEBUG_1) << BIT_SHIFT_R_MAC_DEBUG_1) +#define BIT_GET_R_MAC_DEBUG_1(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_1) & BIT_MASK_R_MAC_DEBUG_1) /* 2 REG_WSEC_OPTION (Offset 0x07EC) */ @@ -29498,7 +29884,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_CFG3 (Offset 0x1000) */ @@ -29518,7 +29904,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_CFG3 (Offset 0x1000) */ @@ -29543,7 +29929,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_CFG5 (Offset 0x1070) */ @@ -29556,7 +29942,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ @@ -29568,7 +29954,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ @@ -29578,7 +29964,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ @@ -29591,7 +29977,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ @@ -29606,7 +29992,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BOOT_REASON (Offset 0x1088) */ @@ -29649,7 +30035,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR2 (Offset 0x10B0) */ @@ -29711,7 +30097,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ @@ -29722,7 +30108,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ @@ -29746,7 +30132,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HISR3 (Offset 0x10BC) */ @@ -29757,7 +30143,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HISR3 (Offset 0x10BC) */ @@ -29781,7 +30167,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SW_MDIO (Offset 0x10C0) */ @@ -29809,7 +30195,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SW_FLUSH (Offset 0x10C4) */ @@ -29910,7 +30296,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_H2C_PKT_READADDR (Offset 0x10D0) */ @@ -29950,7 +30336,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ @@ -29986,7 +30372,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ @@ -30007,7 +30393,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FW_DBG0 (Offset 0x10E0) */ @@ -30128,7 +30514,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWFF (Offset 0x1114) */ @@ -30143,7 +30529,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWFF (Offset 0x1114) */ @@ -30169,7 +30555,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWFF (Offset 0x1114) */ @@ -30200,7 +30586,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE2IMR (Offset 0x1120) */ @@ -30210,7 +30596,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE2IMR (Offset 0x1120) */ @@ -30224,7 +30610,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE2IMR (Offset 0x1120) */ @@ -30253,7 +30639,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE2ISR (Offset 0x1124) */ @@ -30263,7 +30649,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE2ISR (Offset 0x1124) */ @@ -30277,7 +30663,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE2ISR (Offset 0x1124) */ @@ -30316,7 +30702,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ @@ -30336,7 +30722,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ @@ -30356,7 +30742,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ @@ -30376,7 +30762,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ @@ -30386,7 +30772,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ @@ -30430,7 +30816,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ @@ -30450,7 +30836,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ @@ -30470,7 +30856,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ @@ -30490,7 +30876,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ @@ -30500,7 +30886,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ @@ -30544,7 +30930,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30564,7 +30950,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30584,7 +30970,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30604,7 +30990,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30624,7 +31010,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30644,7 +31030,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30664,7 +31050,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30684,7 +31070,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30704,7 +31090,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30724,7 +31110,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30744,7 +31130,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30764,7 +31150,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30784,7 +31170,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30804,7 +31190,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30824,7 +31210,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30844,7 +31230,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30864,7 +31250,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30894,7 +31280,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30914,7 +31300,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30934,7 +31320,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ @@ -30954,7 +31340,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -30974,7 +31360,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -30994,7 +31380,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31014,7 +31400,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31034,7 +31420,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31054,7 +31440,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31074,7 +31460,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31094,7 +31480,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31114,7 +31500,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31134,7 +31520,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31154,7 +31540,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31174,7 +31560,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31194,7 +31580,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31214,7 +31600,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31234,7 +31620,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31254,7 +31640,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31274,7 +31660,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31304,7 +31690,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31324,7 +31710,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31344,7 +31730,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ @@ -31354,7 +31740,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT1IMR (Offset 0x1138) */ @@ -31368,7 +31754,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT1IMR (Offset 0x1138) */ @@ -31379,7 +31765,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT1IMR (Offset 0x1138) */ @@ -31412,7 +31798,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ @@ -31426,7 +31812,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ @@ -31437,7 +31823,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ @@ -31695,7 +32081,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31715,7 +32101,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31735,7 +32121,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31755,7 +32141,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31775,7 +32161,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31795,7 +32181,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31815,7 +32201,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31835,7 +32221,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31855,7 +32241,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31875,7 +32261,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31895,7 +32281,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31915,7 +32301,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31935,7 +32321,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31955,7 +32341,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31975,7 +32361,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -31995,7 +32381,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -32015,7 +32401,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -32035,7 +32421,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -32055,7 +32441,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -32075,7 +32461,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -32095,7 +32481,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -32115,7 +32501,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -32135,7 +32521,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -32155,7 +32541,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -32175,7 +32561,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -32195,7 +32581,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ @@ -32215,7 +32601,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32235,7 +32621,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32255,7 +32641,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32275,7 +32661,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32295,7 +32681,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32315,7 +32701,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32335,7 +32721,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32355,7 +32741,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32375,7 +32761,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32395,7 +32781,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32415,7 +32801,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32435,7 +32821,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32455,7 +32841,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32475,7 +32861,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32495,7 +32881,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32515,7 +32901,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32535,7 +32921,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32555,7 +32941,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32575,7 +32961,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32595,7 +32981,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32615,7 +33001,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32635,7 +33021,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32655,7 +33041,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32675,7 +33061,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32695,7 +33081,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32715,7 +33101,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ @@ -32725,7 +33111,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MSG2 (Offset 0x11F0) */ @@ -32945,15 +33331,6 @@ /* 2 REG_DDMA_CH5DA (Offset 0x1254) */ - -#define BIT_SHIFT_DDMACH5_DA 0 -#define BIT_MASK_DDMACH5_DA 0xffffffffL -#define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA) -#define BIT_GET_DDMACH5_DA(x) (((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA) - - -/* 2 REG_REG_DDMA_CH5CTRL (Offset 0x1258) */ - #define BIT_DDMACH5_OWN BIT(31) #define BIT_DDMACH5_CHKSUM_EN BIT(29) #define BIT_DDMACH5_DA_W_DISABLE BIT(28) @@ -32962,6 +33339,12 @@ #define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25) #define BIT_DDMACH5_CHKSUM_CONT BIT(24) +#define BIT_SHIFT_DDMACH5_DA 0 +#define BIT_MASK_DDMACH5_DA 0xffffffffL +#define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA) +#define BIT_GET_DDMACH5_DA(x) (((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA) + + #define BIT_SHIFT_DDMACH5_DLEN 0 #define BIT_MASK_DDMACH5_DLEN 0x3ffff #define BIT_DDMACH5_DLEN(x) (((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN) @@ -33013,7 +33396,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_STC_INT_CS (Offset 0x1300) */ @@ -33114,7 +33497,7 @@ #endif -#if (HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ @@ -33124,7 +33507,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ @@ -33185,8 +33568,51 @@ #define BIT_AXI_TXDMA_TIMEOUT_RE BIT(20) #define BIT_AXI_DECERR_W_RE BIT(19) #define BIT_AXI_DECERR_R_RE BIT(18) + +#endif + + +#if (HALMAC_8822B_SUPPORT) + + +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ + +#define BIT_CHANGE_PCIE_SPEED BIT(18) + +#endif + + +#if (HALMAC_8197F_SUPPORT) + + +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ + #define BIT_AXI_SLVERR_W_RE BIT(17) #define BIT_AXI_SLVERR_R_RE BIT(16) + +#endif + + +#if (HALMAC_8822B_SUPPORT) + + +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ + + +#define BIT_SHIFT_GEN1_GEN2 16 +#define BIT_MASK_GEN1_GEN2 0x3 +#define BIT_GEN1_GEN2(x) (((x) & BIT_MASK_GEN1_GEN2) << BIT_SHIFT_GEN1_GEN2) +#define BIT_GET_GEN1_GEN2(x) (((x) >> BIT_SHIFT_GEN1_GEN2) & BIT_MASK_GEN1_GEN2) + + +#endif + + +#if (HALMAC_8197F_SUPPORT) + + +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ + #define BIT_AXI_RXDMA_TIMEOUT_IE BIT(13) #define BIT_AXI_TXDMA_TIMEOUT_IE BIT(12) #define BIT_AXI_DECERR_W_IE BIT(11) @@ -33200,6 +33626,27 @@ #define BIT_AXI_SLVERR_W_FLAG BIT(1) #define BIT_AXI_SLVERR_R_FLAG BIT(0) +#endif + + +#if (HALMAC_8822B_SUPPORT) + + +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ + + +#define BIT_SHIFT_AUTO_HANG_RELEASE 0 +#define BIT_MASK_AUTO_HANG_RELEASE 0x7 +#define BIT_AUTO_HANG_RELEASE(x) (((x) & BIT_MASK_AUTO_HANG_RELEASE) << BIT_SHIFT_AUTO_HANG_RELEASE) +#define BIT_GET_AUTO_HANG_RELEASE(x) (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE) & BIT_MASK_AUTO_HANG_RELEASE) + + +#endif + + +#if (HALMAC_8197F_SUPPORT) + + /* 2 REG_AXI_EXCEPT_TIME (Offset 0x1354) */ @@ -33224,7 +33671,17 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8822B_SUPPORT) + + +/* 2 REG_OLD_DEHANG (Offset 0x13F4) */ + +#define BIT_OLD_DEHANG BIT(1) + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_Q0_Q1_INFO (Offset 0x1400) */ @@ -33320,7 +33777,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ @@ -33369,7 +33826,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ @@ -33384,7 +33841,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_USEREG_SETTING (Offset 0x1420) */ @@ -33601,7 +34058,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_R_MACID_RELEASE_SUCCESS_0 (Offset 0x1460) */ @@ -33741,7 +34198,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_MU_TX_CTL (Offset 0x14C0) */ @@ -33758,7 +34215,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MU_TX_CTL (Offset 0x14C0) */ @@ -33802,7 +34259,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CPUMGQ_TX_TIMER (Offset 0x1500) */ @@ -33912,7 +34369,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BCN_PSR_RPT2 (Offset 0x1600) */ @@ -34050,7 +34507,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ @@ -34064,6 +34521,286 @@ #define BIT_CLI0_PWRBIT_OW_EN BIT(1) #define BIT_CLI0_PWR_ST BIT(0) +/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ + +#define BIT_WMAC_RESP_NONSTA1_DIS BIT(7) + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ + +#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) + +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ + +#define BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ + + +#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4 +#define BIT_MASK_WMAC_TXMU_ACKPOLICY 0x3 +#define BIT_WMAC_TXMU_ACKPOLICY(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY) +#define BIT_GET_WMAC_TXMU_ACKPOLICY(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY) & BIT_MASK_WMAC_TXMU_ACKPOLICY) + + +#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL 1 +#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL 0x7 +#define BIT_WMAC_MU_BFEE_PORT_SEL(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) + +#define BIT_WMAC_MU_BFEE_DIS BIT(0) + +/* 2 REG_WMAC_PAUSE_BB_CLR_TH (Offset 0x167D) */ + + +#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH 0 +#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH 0xff +#define BIT_WMAC_PAUSE_BB_CLR_TH(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) + + +/* 2 REG_WMAC_MU_ARB (Offset 0x167E) */ + +#define BIT_WMAC_ARB_HW_ADAPT_EN BIT(7) +#define BIT_WMAC_ARB_SW_EN BIT(6) + +#define BIT_SHIFT_WMAC_ARB_SW_STATE 0 +#define BIT_MASK_WMAC_ARB_SW_STATE 0x3f +#define BIT_WMAC_ARB_SW_STATE(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE) << BIT_SHIFT_WMAC_ARB_SW_STATE) +#define BIT_GET_WMAC_ARB_SW_STATE(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE) & BIT_MASK_WMAC_ARB_SW_STATE) + + +/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ + + +#define BIT_SHIFT_WMAC_MU_DBGSEL 5 +#define BIT_MASK_WMAC_MU_DBGSEL 0x3 +#define BIT_WMAC_MU_DBGSEL(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL) << BIT_SHIFT_WMAC_MU_DBGSEL) +#define BIT_GET_WMAC_MU_DBGSEL(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL) & BIT_MASK_WMAC_MU_DBGSEL) + + +#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT 0 +#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT 0x1f +#define BIT_WMAC_MU_CPRD_TIMEOUT(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) + + +/* 2 REG_WMAC_MU_BF_CTL (Offset 0x1680) */ + +#define BIT_WMAC_INVLD_BFPRT_CHK BIT(15) +#define BIT_WMAC_RETXBFRPTSEQ_UPD BIT(14) + +#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL 12 +#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL 0x3 +#define BIT_WMAC_MU_BFRPTSEG_SEL(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) + + +#define BIT_SHIFT_WMAC_MU_BF_MYAID 0 +#define BIT_MASK_WMAC_MU_BF_MYAID 0xfff +#define BIT_WMAC_MU_BF_MYAID(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID) +#define BIT_GET_WMAC_MU_BF_MYAID(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID) + + +#define BIT_SHIFT_BFRPT_PARA 0 +#define BIT_MASK_BFRPT_PARA 0xfff +#define BIT_BFRPT_PARA(x) (((x) & BIT_MASK_BFRPT_PARA) << BIT_SHIFT_BFRPT_PARA) +#define BIT_GET_BFRPT_PARA(x) (((x) >> BIT_SHIFT_BFRPT_PARA) & BIT_MASK_BFRPT_PARA) + + +#endif + + +#if (HALMAC_8822B_SUPPORT) + + +/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ + + +#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL 12 +#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL 0x7 +#define BIT_BIT_BFRPT_PARA_USERID_SEL(x) (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) +#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL(x) (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) + + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ + +#define BIT_STATUS_BFEE2 BIT(10) +#define BIT_WMAC_MU_BFEE2_EN BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE2_AID 0 +#define BIT_MASK_WMAC_MU_BFEE2_AID 0x1ff +#define BIT_WMAC_MU_BFEE2_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID) +#define BIT_GET_WMAC_MU_BFEE2_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ + +#define BIT_STATUS_BFEE3 BIT(10) +#define BIT_WMAC_MU_BFEE3_EN BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE3_AID 0 +#define BIT_MASK_WMAC_MU_BFEE3_AID 0x1ff +#define BIT_WMAC_MU_BFEE3_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID) +#define BIT_GET_WMAC_MU_BFEE3_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4 (Offset 0x1688) */ + +#define BIT_STATUS_BFEE4 BIT(10) +#define BIT_WMAC_MU_BFEE4_EN BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE4_AID 0 +#define BIT_MASK_WMAC_MU_BFEE4_AID 0x1ff +#define BIT_WMAC_MU_BFEE4_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID) +#define BIT_GET_WMAC_MU_BFEE4_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID) + + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ + +#define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55) +#define BIT_R_WMAC_RXRST_DLY BIT(54) +#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53) +#define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52) +#define BIT_STATUS_BFEE5 BIT(10) + +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ + +#define BIT_BIT_STATUS_BFEE5 BIT(10) + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ + +#define BIT_WMAC_MU_BFEE5_EN BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE5_AID 0 +#define BIT_MASK_WMAC_MU_BFEE5_AID 0x1ff +#define BIT_WMAC_MU_BFEE5_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID) +#define BIT_GET_WMAC_MU_BFEE5_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6 (Offset 0x168C) */ + +#define BIT_STATUS_BFEE6 BIT(10) +#define BIT_WMAC_MU_BFEE6_EN BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE6_AID 0 +#define BIT_MASK_WMAC_MU_BFEE6_AID 0x1ff +#define BIT_WMAC_MU_BFEE6_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID) +#define BIT_GET_WMAC_MU_BFEE6_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ + +#define BIT_BIT_STATUS_BFEE4 BIT(10) +#define BIT_WMAC_MU_BFEE7_EN BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE7_AID 0 +#define BIT_MASK_WMAC_MU_BFEE7_AID 0x1ff +#define BIT_WMAC_MU_BFEE7_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID) +#define BIT_GET_WMAC_MU_BFEE7_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID) + + +/* 2 REG_WMAC_BB_STOP_RX_COUNTER (Offset 0x1690) */ + +#define BIT_RST_ALL_COUNTER BIT(31) + +#define BIT_SHIFT_ABORT_RX_VBON_COUNTER 16 +#define BIT_MASK_ABORT_RX_VBON_COUNTER 0xff +#define BIT_ABORT_RX_VBON_COUNTER(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER) << BIT_SHIFT_ABORT_RX_VBON_COUNTER) +#define BIT_GET_ABORT_RX_VBON_COUNTER(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) & BIT_MASK_ABORT_RX_VBON_COUNTER) + + +#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER 8 +#define BIT_MASK_ABORT_RX_RDRDY_COUNTER 0xff +#define BIT_ABORT_RX_RDRDY_COUNTER(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) + + +#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER 0 +#define BIT_MASK_VBON_EARLY_FALLING_COUNTER 0xff +#define BIT_VBON_EARLY_FALLING_COUNTER(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) + + +/* 2 REG_WMAC_PLCP_MONITOR (Offset 0x1694) */ + +#define BIT_WMAC_PLCP_TRX_SEL BIT(31) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL 28 +#define BIT_MASK_WMAC_PLCP_RDSIG_SEL 0x7 +#define BIT_WMAC_PLCP_RDSIG_SEL(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) + + +#define BIT_SHIFT_WMAC_RATE_IDX 24 +#define BIT_MASK_WMAC_RATE_IDX 0xf +#define BIT_WMAC_RATE_IDX(x) (((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX) +#define BIT_GET_WMAC_RATE_IDX(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX) + + +#define BIT_SHIFT_WMAC_PLCP_RDSIG 0 +#define BIT_MASK_WMAC_PLCP_RDSIG 0xffffff +#define BIT_WMAC_PLCP_RDSIG(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG) +#define BIT_GET_WMAC_PLCP_RDSIG(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG) + + +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + +/* 2 REG_WMAC_PLCP_MONITOR_MUTX (Offset 0x1698) */ + +#define BIT_WMAC_MUTX_IDX BIT(24) + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + + /* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */ @@ -34112,7 +34849,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */ diff --git a/hal/halmac/halmac_bit_8821c.h b/hal/halmac/halmac_bit_8821c.h index 5081766..880146b 100644 --- a/hal/halmac/halmac_bit_8821c.h +++ b/hal/halmac/halmac_bit_8821c.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __INC_HALMAC_BIT_8821C_H #define __INC_HALMAC_BIT_8821C_H @@ -95,11 +110,13 @@ #define BIT_GET_VPDIDX_8821C(x) (((x) >> BIT_SHIFT_VPDIDX_8821C) & BIT_MASK_VPDIDX_8821C) + #define BIT_SHIFT_EEM1_0_8821C 6 #define BIT_MASK_EEM1_0_8821C 0x3 #define BIT_EEM1_0_8821C(x) (((x) & BIT_MASK_EEM1_0_8821C) << BIT_SHIFT_EEM1_0_8821C) #define BIT_GET_EEM1_0_8821C(x) (((x) >> BIT_SHIFT_EEM1_0_8821C) & BIT_MASK_EEM1_0_8821C) + #define BIT_AUTOLOAD_SUS_8821C BIT(5) #define BIT_EERPOMSEL_8821C BIT(4) #define BIT_EECS_V1_8821C BIT(3) @@ -115,6 +132,7 @@ #define BIT_GET_VPD_DATA_8821C(x) (((x) >> BIT_SHIFT_VPD_DATA_8821C) & BIT_MASK_VPD_DATA_8821C) + /* 2 REG_SYS_SWR_CTRL1_8821C */ #define BIT_C2_L_BIT0_8821C BIT(31) @@ -124,11 +142,13 @@ #define BIT_GET_C1_L_8821C(x) (((x) >> BIT_SHIFT_C1_L_8821C) & BIT_MASK_C1_L_8821C) + #define BIT_SHIFT_REG_FREQ_L_8821C 25 #define BIT_MASK_REG_FREQ_L_8821C 0x7 #define BIT_REG_FREQ_L_8821C(x) (((x) & BIT_MASK_REG_FREQ_L_8821C) << BIT_SHIFT_REG_FREQ_L_8821C) #define BIT_GET_REG_FREQ_L_8821C(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8821C) & BIT_MASK_REG_FREQ_L_8821C) + #define BIT_REG_EN_DUTY_8821C BIT(24) #define BIT_SHIFT_REG_MODE_8821C 22 @@ -136,6 +156,7 @@ #define BIT_REG_MODE_8821C(x) (((x) & BIT_MASK_REG_MODE_8821C) << BIT_SHIFT_REG_MODE_8821C) #define BIT_GET_REG_MODE_8821C(x) (((x) >> BIT_SHIFT_REG_MODE_8821C) & BIT_MASK_REG_MODE_8821C) + #define BIT_REG_EN_SP_8821C BIT(21) #define BIT_REG_AUTO_L_8821C BIT(20) #define BIT_SW18_SELD_BIT0_8821C BIT(19) @@ -147,11 +168,13 @@ #define BIT_GET_OCP_L1_8821C(x) (((x) >> BIT_SHIFT_OCP_L1_8821C) & BIT_MASK_OCP_L1_8821C) + #define BIT_SHIFT_CF_L_8821C 13 #define BIT_MASK_CF_L_8821C 0x3 #define BIT_CF_L_8821C(x) (((x) & BIT_MASK_CF_L_8821C) << BIT_SHIFT_CF_L_8821C) #define BIT_GET_CF_L_8821C(x) (((x) >> BIT_SHIFT_CF_L_8821C) & BIT_MASK_CF_L_8821C) + #define BIT_SW18_FPWM_8821C BIT(11) #define BIT_SW18_SWEN_8821C BIT(9) #define BIT_SW18_LDEN_8821C BIT(8) @@ -168,29 +191,34 @@ #define BIT_GET_REG_DELAY_8821C(x) (((x) >> BIT_SHIFT_REG_DELAY_8821C) & BIT_MASK_REG_DELAY_8821C) + #define BIT_SHIFT_V15ADJ_L1_V1_8821C 24 #define BIT_MASK_V15ADJ_L1_V1_8821C 0x7 #define BIT_V15ADJ_L1_V1_8821C(x) (((x) & BIT_MASK_V15ADJ_L1_V1_8821C) << BIT_SHIFT_V15ADJ_L1_V1_8821C) #define BIT_GET_V15ADJ_L1_V1_8821C(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8821C) & BIT_MASK_V15ADJ_L1_V1_8821C) + #define BIT_SHIFT_VOL_L1_V1_8821C 20 #define BIT_MASK_VOL_L1_V1_8821C 0xf #define BIT_VOL_L1_V1_8821C(x) (((x) & BIT_MASK_VOL_L1_V1_8821C) << BIT_SHIFT_VOL_L1_V1_8821C) #define BIT_GET_VOL_L1_V1_8821C(x) (((x) >> BIT_SHIFT_VOL_L1_V1_8821C) & BIT_MASK_VOL_L1_V1_8821C) + #define BIT_SHIFT_IN_L1_V1_8821C 17 #define BIT_MASK_IN_L1_V1_8821C 0x7 #define BIT_IN_L1_V1_8821C(x) (((x) & BIT_MASK_IN_L1_V1_8821C) << BIT_SHIFT_IN_L1_V1_8821C) #define BIT_GET_IN_L1_V1_8821C(x) (((x) >> BIT_SHIFT_IN_L1_V1_8821C) & BIT_MASK_IN_L1_V1_8821C) + #define BIT_SHIFT_TBOX_L1_8821C 15 #define BIT_MASK_TBOX_L1_8821C 0x3 #define BIT_TBOX_L1_8821C(x) (((x) & BIT_MASK_TBOX_L1_8821C) << BIT_SHIFT_TBOX_L1_8821C) #define BIT_GET_TBOX_L1_8821C(x) (((x) >> BIT_SHIFT_TBOX_L1_8821C) & BIT_MASK_TBOX_L1_8821C) + #define BIT_SW18_SEL_8821C BIT(13) /* 2 REG_NOT_VALID_8821C */ @@ -202,23 +230,27 @@ #define BIT_GET_R3_L_8821C(x) (((x) >> BIT_SHIFT_R3_L_8821C) & BIT_MASK_R3_L_8821C) + #define BIT_SHIFT_SW18_R2_8821C 5 #define BIT_MASK_SW18_R2_8821C 0x3 #define BIT_SW18_R2_8821C(x) (((x) & BIT_MASK_SW18_R2_8821C) << BIT_SHIFT_SW18_R2_8821C) #define BIT_GET_SW18_R2_8821C(x) (((x) >> BIT_SHIFT_SW18_R2_8821C) & BIT_MASK_SW18_R2_8821C) + #define BIT_SHIFT_SW18_R1_8821C 3 #define BIT_MASK_SW18_R1_8821C 0x3 #define BIT_SW18_R1_8821C(x) (((x) & BIT_MASK_SW18_R1_8821C) << BIT_SHIFT_SW18_R1_8821C) #define BIT_GET_SW18_R1_8821C(x) (((x) >> BIT_SHIFT_SW18_R1_8821C) & BIT_MASK_SW18_R1_8821C) + #define BIT_SHIFT_C3_L_C3_8821C 1 #define BIT_MASK_C3_L_C3_8821C 0x3 #define BIT_C3_L_C3_8821C(x) (((x) & BIT_MASK_C3_L_C3_8821C) << BIT_SHIFT_C3_L_C3_8821C) #define BIT_GET_C3_L_C3_8821C(x) (((x) >> BIT_SHIFT_C3_L_C3_8821C) & BIT_MASK_C3_L_C3_8821C) + #define BIT_C2_L_BIT1_8821C BIT(0) /* 2 REG_SYS_SWR_CTRL3_8821C */ @@ -230,12 +262,14 @@ #define BIT_GET_SPS18_OCP_TH_8821C(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8821C) & BIT_MASK_SPS18_OCP_TH_8821C) + #define BIT_SHIFT_OCP_WINDOW_8821C 0 #define BIT_MASK_OCP_WINDOW_8821C 0xffff #define BIT_OCP_WINDOW_8821C(x) (((x) & BIT_MASK_OCP_WINDOW_8821C) << BIT_SHIFT_OCP_WINDOW_8821C) #define BIT_GET_OCP_WINDOW_8821C(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8821C) & BIT_MASK_OCP_WINDOW_8821C) + /* 2 REG_RSV_CTRL_8821C */ #define BIT_HREG_DBG_8821C BIT(23) #define BIT_WLMCUIOIF_8821C BIT(8) @@ -260,6 +294,7 @@ #define BIT_LPLDH12_RSV_8821C(x) (((x) & BIT_MASK_LPLDH12_RSV_8821C) << BIT_SHIFT_LPLDH12_RSV_8821C) #define BIT_GET_LPLDH12_RSV_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8821C) & BIT_MASK_LPLDH12_RSV_8821C) + #define BIT_LPLDH12_SLP_8821C BIT(28) #define BIT_SHIFT_LPLDH12_VADJ_8821C 24 @@ -267,6 +302,7 @@ #define BIT_LPLDH12_VADJ_8821C(x) (((x) & BIT_MASK_LPLDH12_VADJ_8821C) << BIT_SHIFT_LPLDH12_VADJ_8821C) #define BIT_GET_LPLDH12_VADJ_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8821C) & BIT_MASK_LPLDH12_VADJ_8821C) + #define BIT_PCIE_CALIB_EN_8821C BIT(17) #define BIT_LDH12_EN_8821C BIT(16) #define BIT_WLBBOFF_BIG_PWC_EN_8821C BIT(14) @@ -294,11 +330,13 @@ #define BIT_GET_XTAL_CAP_XI_8821C(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8821C) & BIT_MASK_XTAL_CAP_XI_8821C) + #define BIT_SHIFT_XTAL_DRV_DIGI_8821C 23 #define BIT_MASK_XTAL_DRV_DIGI_8821C 0x3 #define BIT_XTAL_DRV_DIGI_8821C(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8821C) << BIT_SHIFT_XTAL_DRV_DIGI_8821C) #define BIT_GET_XTAL_DRV_DIGI_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8821C) & BIT_MASK_XTAL_DRV_DIGI_8821C) + #define BIT_XTAL_DRV_USB_BIT1_8821C BIT(22) #define BIT_SHIFT_MAC_CLK_SEL_8821C 20 @@ -306,6 +344,7 @@ #define BIT_MAC_CLK_SEL_8821C(x) (((x) & BIT_MASK_MAC_CLK_SEL_8821C) << BIT_SHIFT_MAC_CLK_SEL_8821C) #define BIT_GET_MAC_CLK_SEL_8821C(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8821C) & BIT_MASK_MAC_CLK_SEL_8821C) + #define BIT_XTAL_DRV_USB_BIT0_8821C BIT(19) #define BIT_SHIFT_XTAL_DRV_AFE_8821C 17 @@ -314,17 +353,20 @@ #define BIT_GET_XTAL_DRV_AFE_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8821C) & BIT_MASK_XTAL_DRV_AFE_8821C) + #define BIT_SHIFT_XTAL_DRV_RF2_8821C 15 #define BIT_MASK_XTAL_DRV_RF2_8821C 0x3 #define BIT_XTAL_DRV_RF2_8821C(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8821C) << BIT_SHIFT_XTAL_DRV_RF2_8821C) #define BIT_GET_XTAL_DRV_RF2_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8821C) & BIT_MASK_XTAL_DRV_RF2_8821C) + #define BIT_SHIFT_XTAL_DRV_RF1_8821C 13 #define BIT_MASK_XTAL_DRV_RF1_8821C 0x3 #define BIT_XTAL_DRV_RF1_8821C(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8821C) << BIT_SHIFT_XTAL_DRV_RF1_8821C) #define BIT_GET_XTAL_DRV_RF1_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8821C) & BIT_MASK_XTAL_DRV_RF1_8821C) + #define BIT_XTAL_DELAY_DIGI_8821C BIT(12) #define BIT_XTAL_DELAY_USB_8821C BIT(11) #define BIT_XTAL_DELAY_AFE_8821C BIT(10) @@ -334,6 +376,7 @@ #define BIT_XTAL_LDO_VREF_8821C(x) (((x) & BIT_MASK_XTAL_LDO_VREF_8821C) << BIT_SHIFT_XTAL_LDO_VREF_8821C) #define BIT_GET_XTAL_LDO_VREF_8821C(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8821C) & BIT_MASK_XTAL_LDO_VREF_8821C) + #define BIT_XTAL_XQSEL_RF_8821C BIT(6) #define BIT_XTAL_XQSEL_8821C BIT(5) @@ -343,11 +386,13 @@ #define BIT_GET_XTAL_GMN_V2_8821C(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2_8821C) & BIT_MASK_XTAL_GMN_V2_8821C) + #define BIT_SHIFT_XTAL_GMP_V2_8821C 1 #define BIT_MASK_XTAL_GMP_V2_8821C 0x3 #define BIT_XTAL_GMP_V2_8821C(x) (((x) & BIT_MASK_XTAL_GMP_V2_8821C) << BIT_SHIFT_XTAL_GMP_V2_8821C) #define BIT_GET_XTAL_GMP_V2_8821C(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2_8821C) & BIT_MASK_XTAL_GMP_V2_8821C) + #define BIT_XTAL_EN_8821C BIT(0) /* 2 REG_AFE_CTRL2_8821C */ @@ -357,6 +402,7 @@ #define BIT_REG_C3_V4_8821C(x) (((x) & BIT_MASK_REG_C3_V4_8821C) << BIT_SHIFT_REG_C3_V4_8821C) #define BIT_GET_REG_C3_V4_8821C(x) (((x) >> BIT_SHIFT_REG_C3_V4_8821C) & BIT_MASK_REG_C3_V4_8821C) + #define BIT_REG_CP_BIT1_8821C BIT(29) #define BIT_SHIFT_REG_RS_V4_8821C 26 @@ -365,23 +411,27 @@ #define BIT_GET_REG_RS_V4_8821C(x) (((x) >> BIT_SHIFT_REG_RS_V4_8821C) & BIT_MASK_REG_RS_V4_8821C) + #define BIT_SHIFT_REG__CS_8821C 24 #define BIT_MASK_REG__CS_8821C 0x3 #define BIT_REG__CS_8821C(x) (((x) & BIT_MASK_REG__CS_8821C) << BIT_SHIFT_REG__CS_8821C) #define BIT_GET_REG__CS_8821C(x) (((x) >> BIT_SHIFT_REG__CS_8821C) & BIT_MASK_REG__CS_8821C) + #define BIT_SHIFT_REG_CP_OFFSET_8821C 21 #define BIT_MASK_REG_CP_OFFSET_8821C 0x7 #define BIT_REG_CP_OFFSET_8821C(x) (((x) & BIT_MASK_REG_CP_OFFSET_8821C) << BIT_SHIFT_REG_CP_OFFSET_8821C) #define BIT_GET_REG_CP_OFFSET_8821C(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_8821C) & BIT_MASK_REG_CP_OFFSET_8821C) + #define BIT_SHIFT_CP_BIAS_8821C 18 #define BIT_MASK_CP_BIAS_8821C 0x7 #define BIT_CP_BIAS_8821C(x) (((x) & BIT_MASK_CP_BIAS_8821C) << BIT_SHIFT_CP_BIAS_8821C) #define BIT_GET_CP_BIAS_8821C(x) (((x) >> BIT_SHIFT_CP_BIAS_8821C) & BIT_MASK_CP_BIAS_8821C) + #define BIT_REG_IDOUBLE_V2_8821C BIT(17) #define BIT_EN_SYN_8821C BIT(16) @@ -391,11 +441,13 @@ #define BIT_GET_MCCO_8821C(x) (((x) >> BIT_SHIFT_MCCO_8821C) & BIT_MASK_MCCO_8821C) + #define BIT_SHIFT_REG_LDO_SEL_8821C 12 #define BIT_MASK_REG_LDO_SEL_8821C 0x3 #define BIT_REG_LDO_SEL_8821C(x) (((x) & BIT_MASK_REG_LDO_SEL_8821C) << BIT_SHIFT_REG_LDO_SEL_8821C) #define BIT_GET_REG_LDO_SEL_8821C(x) (((x) >> BIT_SHIFT_REG_LDO_SEL_8821C) & BIT_MASK_REG_LDO_SEL_8821C) + #define BIT_REG_KVCO_V2_8821C BIT(10) #define BIT_AGPIO_GPO_8821C BIT(9) @@ -405,11 +457,13 @@ #define BIT_GET_AGPIO_DRV_8821C(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8821C) & BIT_MASK_AGPIO_DRV_8821C) + #define BIT_SHIFT_XTAL_CAP_XO_8821C 1 #define BIT_MASK_XTAL_CAP_XO_8821C 0x3f #define BIT_XTAL_CAP_XO_8821C(x) (((x) & BIT_MASK_XTAL_CAP_XO_8821C) << BIT_SHIFT_XTAL_CAP_XO_8821C) #define BIT_GET_XTAL_CAP_XO_8821C(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8821C) & BIT_MASK_XTAL_CAP_XO_8821C) + #define BIT_POW_PLL_8821C BIT(0) /* 2 REG_AFE_CTRL3_8821C */ @@ -419,6 +473,7 @@ #define BIT_PS_8821C(x) (((x) & BIT_MASK_PS_8821C) << BIT_SHIFT_PS_8821C) #define BIT_GET_PS_8821C(x) (((x) >> BIT_SHIFT_PS_8821C) & BIT_MASK_PS_8821C) + #define BIT_PSEN_8821C BIT(6) #define BIT_DOGENB_8821C BIT(5) #define BIT_REG_MBIAS_8821C BIT(4) @@ -428,6 +483,7 @@ #define BIT_REG_R3_V4_8821C(x) (((x) & BIT_MASK_REG_R3_V4_8821C) << BIT_SHIFT_REG_R3_V4_8821C) #define BIT_GET_REG_R3_V4_8821C(x) (((x) >> BIT_SHIFT_REG_R3_V4_8821C) & BIT_MASK_REG_R3_V4_8821C) + #define BIT_REG_CP_BIT0_8821C BIT(0) /* 2 REG_EFUSE_CTRL_8821C */ @@ -439,17 +495,20 @@ #define BIT_GET_EF_PGPD_8821C(x) (((x) >> BIT_SHIFT_EF_PGPD_8821C) & BIT_MASK_EF_PGPD_8821C) + #define BIT_SHIFT_EF_RDT_8821C 24 #define BIT_MASK_EF_RDT_8821C 0xf #define BIT_EF_RDT_8821C(x) (((x) & BIT_MASK_EF_RDT_8821C) << BIT_SHIFT_EF_RDT_8821C) #define BIT_GET_EF_RDT_8821C(x) (((x) >> BIT_SHIFT_EF_RDT_8821C) & BIT_MASK_EF_RDT_8821C) + #define BIT_SHIFT_EF_PGTS_8821C 20 #define BIT_MASK_EF_PGTS_8821C 0xf #define BIT_EF_PGTS_8821C(x) (((x) & BIT_MASK_EF_PGTS_8821C) << BIT_SHIFT_EF_PGTS_8821C) #define BIT_GET_EF_PGTS_8821C(x) (((x) >> BIT_SHIFT_EF_PGTS_8821C) & BIT_MASK_EF_PGTS_8821C) + #define BIT_EF_PDWN_8821C BIT(19) #define BIT_EF_ALDEN_8821C BIT(18) @@ -459,12 +518,14 @@ #define BIT_GET_EF_ADDR_8821C(x) (((x) >> BIT_SHIFT_EF_ADDR_8821C) & BIT_MASK_EF_ADDR_8821C) + #define BIT_SHIFT_EF_DATA_8821C 0 #define BIT_MASK_EF_DATA_8821C 0xff #define BIT_EF_DATA_8821C(x) (((x) & BIT_MASK_EF_DATA_8821C) << BIT_SHIFT_EF_DATA_8821C) #define BIT_GET_EF_DATA_8821C(x) (((x) >> BIT_SHIFT_EF_DATA_8821C) & BIT_MASK_EF_DATA_8821C) + /* 2 REG_LDO_EFUSE_CTRL_8821C */ #define BIT_LDOE25_EN_8821C BIT(31) @@ -473,6 +534,7 @@ #define BIT_LDOE25_V12ADJ_L_8821C(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8821C) << BIT_SHIFT_LDOE25_V12ADJ_L_8821C) #define BIT_GET_LDOE25_V12ADJ_L_8821C(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8821C) & BIT_MASK_LDOE25_V12ADJ_L_8821C) + #define BIT_EF_CRES_SEL_8821C BIT(26) #define BIT_SHIFT_EF_SCAN_START_V1_8821C 16 @@ -481,11 +543,13 @@ #define BIT_GET_EF_SCAN_START_V1_8821C(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8821C) & BIT_MASK_EF_SCAN_START_V1_8821C) + #define BIT_SHIFT_EF_SCAN_END_8821C 12 #define BIT_MASK_EF_SCAN_END_8821C 0xf #define BIT_EF_SCAN_END_8821C(x) (((x) & BIT_MASK_EF_SCAN_END_8821C) << BIT_SHIFT_EF_SCAN_END_8821C) #define BIT_GET_EF_SCAN_END_8821C(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8821C) & BIT_MASK_EF_SCAN_END_8821C) + #define BIT_EF_PD_DIS_8821C BIT(11) #define BIT_SHIFT_EF_CELL_SEL_8821C 8 @@ -493,6 +557,7 @@ #define BIT_EF_CELL_SEL_8821C(x) (((x) & BIT_MASK_EF_CELL_SEL_8821C) << BIT_SHIFT_EF_CELL_SEL_8821C) #define BIT_GET_EF_CELL_SEL_8821C(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8821C) & BIT_MASK_EF_CELL_SEL_8821C) + #define BIT_EF_TRPT_8821C BIT(7) #define BIT_SHIFT_EF_TTHD_8821C 0 @@ -501,6 +566,7 @@ #define BIT_GET_EF_TTHD_8821C(x) (((x) >> BIT_SHIFT_EF_TTHD_8821C) & BIT_MASK_EF_TTHD_8821C) + /* 2 REG_PWR_OPTION_CTRL_8821C */ #define BIT_SHIFT_DBG_SEL_V1_8821C 16 @@ -509,17 +575,20 @@ #define BIT_GET_DBG_SEL_V1_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8821C) & BIT_MASK_DBG_SEL_V1_8821C) + #define BIT_SHIFT_DBG_SEL_BYTE_8821C 14 #define BIT_MASK_DBG_SEL_BYTE_8821C 0x3 #define BIT_DBG_SEL_BYTE_8821C(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8821C) << BIT_SHIFT_DBG_SEL_BYTE_8821C) #define BIT_GET_DBG_SEL_BYTE_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8821C) & BIT_MASK_DBG_SEL_BYTE_8821C) + #define BIT_SHIFT_STD_L1_V1_8821C 12 #define BIT_MASK_STD_L1_V1_8821C 0x3 #define BIT_STD_L1_V1_8821C(x) (((x) & BIT_MASK_STD_L1_V1_8821C) << BIT_SHIFT_STD_L1_V1_8821C) #define BIT_GET_STD_L1_V1_8821C(x) (((x) >> BIT_SHIFT_STD_L1_V1_8821C) & BIT_MASK_STD_L1_V1_8821C) + #define BIT_SYSON_DBG_PAD_E2_8821C BIT(11) #define BIT_SYSON_LED_PAD_E2_8821C BIT(10) #define BIT_SYSON_GPEE_PAD_E2_8821C BIT(9) @@ -532,18 +601,21 @@ #define BIT_GET_SYSON_SPS0WWV_WT_8821C(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) & BIT_MASK_SYSON_SPS0WWV_WT_8821C) + #define BIT_SHIFT_SYSON_SPS0LDO_WT_8821C 2 #define BIT_MASK_SYSON_SPS0LDO_WT_8821C 0x3 #define BIT_SYSON_SPS0LDO_WT_8821C(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8821C) << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) #define BIT_GET_SYSON_SPS0LDO_WT_8821C(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) & BIT_MASK_SYSON_SPS0LDO_WT_8821C) + #define BIT_SHIFT_SYSON_RCLK_SCALE_8821C 0 #define BIT_MASK_SYSON_RCLK_SCALE_8821C 0x3 #define BIT_SYSON_RCLK_SCALE_8821C(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8821C) << BIT_SHIFT_SYSON_RCLK_SCALE_8821C) #define BIT_GET_SYSON_RCLK_SCALE_8821C(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8821C) & BIT_MASK_SYSON_RCLK_SCALE_8821C) + /* 2 REG_CAL_TIMER_8821C */ #define BIT_SHIFT_MATCH_CNT_8821C 8 @@ -552,12 +624,14 @@ #define BIT_GET_MATCH_CNT_8821C(x) (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C) + #define BIT_SHIFT_CAL_SCAL_8821C 0 #define BIT_MASK_CAL_SCAL_8821C 0xff #define BIT_CAL_SCAL_8821C(x) (((x) & BIT_MASK_CAL_SCAL_8821C) << BIT_SHIFT_CAL_SCAL_8821C) #define BIT_GET_CAL_SCAL_8821C(x) (((x) >> BIT_SHIFT_CAL_SCAL_8821C) & BIT_MASK_CAL_SCAL_8821C) + /* 2 REG_ACLK_MON_8821C */ #define BIT_SHIFT_RCLK_MON_8821C 5 @@ -565,6 +639,7 @@ #define BIT_RCLK_MON_8821C(x) (((x) & BIT_MASK_RCLK_MON_8821C) << BIT_SHIFT_RCLK_MON_8821C) #define BIT_GET_RCLK_MON_8821C(x) (((x) >> BIT_SHIFT_RCLK_MON_8821C) & BIT_MASK_RCLK_MON_8821C) + #define BIT_CAL_EN_8821C BIT(4) #define BIT_SHIFT_DPSTU_8821C 2 @@ -572,6 +647,7 @@ #define BIT_DPSTU_8821C(x) (((x) & BIT_MASK_DPSTU_8821C) << BIT_SHIFT_DPSTU_8821C) #define BIT_GET_DPSTU_8821C(x) (((x) >> BIT_SHIFT_DPSTU_8821C) & BIT_MASK_DPSTU_8821C) + #define BIT_SUS_16X_8821C BIT(1) /* 2 REG_GPIO_MUXCFG_8821C */ @@ -591,6 +667,7 @@ #define BIT_BTMODE_8821C(x) (((x) & BIT_MASK_BTMODE_8821C) << BIT_SHIFT_BTMODE_8821C) #define BIT_GET_BTMODE_8821C(x) (((x) >> BIT_SHIFT_BTMODE_8821C) & BIT_MASK_BTMODE_8821C) + #define BIT_ENBT_8821C BIT(5) #define BIT_EROM_EN_8821C BIT(4) #define BIT_WLRFE_6_7_EN_8821C BIT(3) @@ -602,6 +679,7 @@ #define BIT_GET_GPIOSEL_8821C(x) (((x) >> BIT_SHIFT_GPIOSEL_8821C) & BIT_MASK_GPIOSEL_8821C) + /* 2 REG_GPIO_PIN_CTRL_8821C */ #define BIT_SHIFT_GPIO_MOD_7_TO_0_8821C 24 @@ -610,24 +688,28 @@ #define BIT_GET_GPIO_MOD_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) & BIT_MASK_GPIO_MOD_7_TO_0_8821C) + #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C 16 #define BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C 0xff #define BIT_GPIO_IO_SEL_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) #define BIT_GET_GPIO_IO_SEL_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) + #define BIT_SHIFT_GPIO_OUT_7_TO_0_8821C 8 #define BIT_MASK_GPIO_OUT_7_TO_0_8821C 0xff #define BIT_GPIO_OUT_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8821C) << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) #define BIT_GET_GPIO_OUT_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) & BIT_MASK_GPIO_OUT_7_TO_0_8821C) + #define BIT_SHIFT_GPIO_IN_7_TO_0_8821C 0 #define BIT_MASK_GPIO_IN_7_TO_0_8821C 0xff #define BIT_GPIO_IN_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8821C) << BIT_SHIFT_GPIO_IN_7_TO_0_8821C) #define BIT_GET_GPIO_IN_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8821C) & BIT_MASK_GPIO_IN_7_TO_0_8821C) + /* 2 REG_GPIO_INTM_8821C */ #define BIT_SHIFT_MUXDBG_SEL_8821C 30 @@ -635,6 +717,7 @@ #define BIT_MUXDBG_SEL_8821C(x) (((x) & BIT_MASK_MUXDBG_SEL_8821C) << BIT_SHIFT_MUXDBG_SEL_8821C) #define BIT_GET_MUXDBG_SEL_8821C(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8821C) & BIT_MASK_MUXDBG_SEL_8821C) + #define BIT_EXTWOL_SEL_8821C BIT(17) #define BIT_EXTWOL_EN_8821C BIT(16) #define BIT_GPIOF_INT_MD_8821C BIT(15) @@ -674,6 +757,7 @@ #define BIT_LED2CM_8821C(x) (((x) & BIT_MASK_LED2CM_8821C) << BIT_SHIFT_LED2CM_8821C) #define BIT_GET_LED2CM_8821C(x) (((x) >> BIT_SHIFT_LED2CM_8821C) & BIT_MASK_LED2CM_8821C) + #define BIT_LED1DIS_8821C BIT(15) #define BIT_LED1PL_8821C BIT(12) #define BIT_LED1SV_8821C BIT(11) @@ -683,6 +767,7 @@ #define BIT_LED1CM_8821C(x) (((x) & BIT_MASK_LED1CM_8821C) << BIT_SHIFT_LED1CM_8821C) #define BIT_GET_LED1CM_8821C(x) (((x) >> BIT_SHIFT_LED1CM_8821C) & BIT_MASK_LED1CM_8821C) + #define BIT_LED0DIS_8821C BIT(7) #define BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C 5 @@ -690,6 +775,7 @@ #define BIT_AFE_LDO_SWR_CHECK_8821C(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) #define BIT_GET_AFE_LDO_SWR_CHECK_8821C(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C) + #define BIT_LED0PL_8821C BIT(4) #define BIT_LED0SV_8821C BIT(3) @@ -699,6 +785,7 @@ #define BIT_GET_LED0CM_8821C(x) (((x) >> BIT_SHIFT_LED0CM_8821C) & BIT_MASK_LED0CM_8821C) + /* 2 REG_FSIMR_8821C */ #define BIT_FS_PDNINT_EN_8821C BIT(31) #define BIT_NFC_INT_PAD_EN_8821C BIT(30) @@ -817,24 +904,28 @@ #define BIT_GET_GPIO_MOD_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) & BIT_MASK_GPIO_MOD_15_TO_8_8821C) + #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C 16 #define BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C 0xff #define BIT_GPIO_IO_SEL_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) #define BIT_GET_GPIO_IO_SEL_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) + #define BIT_SHIFT_GPIO_OUT_15_TO_8_8821C 8 #define BIT_MASK_GPIO_OUT_15_TO_8_8821C 0xff #define BIT_GPIO_OUT_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8821C) << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) #define BIT_GET_GPIO_OUT_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) & BIT_MASK_GPIO_OUT_15_TO_8_8821C) + #define BIT_SHIFT_GPIO_IN_15_TO_8_8821C 0 #define BIT_MASK_GPIO_IN_15_TO_8_8821C 0xff #define BIT_GPIO_IN_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8821C) << BIT_SHIFT_GPIO_IN_15_TO_8_8821C) #define BIT_GET_GPIO_IN_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8821C) & BIT_MASK_GPIO_IN_15_TO_8_8821C) + /* 2 REG_PAD_CTRL1_8821C */ #define BIT_PAPE_WLBT_SEL_8821C BIT(29) #define BIT_LNAON_WLBT_SEL_8821C BIT(28) @@ -853,6 +944,7 @@ #define BIT_BTGP_GPIO_SL_8821C(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8821C) << BIT_SHIFT_BTGP_GPIO_SL_8821C) #define BIT_GET_BTGP_GPIO_SL_8821C(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8821C) & BIT_MASK_BTGP_GPIO_SL_8821C) + #define BIT_PAD_SDIO_SR_8821C BIT(14) #define BIT_GPIO14_OUTPUT_PL_8821C BIT(13) #define BIT_HOST_WAKE_PAD_PULL_EN_8821C BIT(12) @@ -906,6 +998,7 @@ #define BIT_GET_WLCLK_PHASE_8821C(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8821C) & BIT_MASK_WLCLK_PHASE_8821C) + /* 2 REG_SYS_SDIO_CTRL_8821C */ #define BIT_DBG_GNT_WL_BT_8821C BIT(27) #define BIT_LTE_MUX_CTRL_PATH_8821C BIT(26) @@ -928,6 +1021,7 @@ #define BIT_TSFT_SEL_8821C(x) (((x) & BIT_MASK_TSFT_SEL_8821C) << BIT_SHIFT_TSFT_SEL_8821C) #define BIT_GET_TSFT_SEL_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_8821C) & BIT_MASK_TSFT_SEL_8821C) + #define BIT_USB_HOST_PWR_OFF_EN_8821C BIT(12) #define BIT_SYM_LPS_BLOCK_EN_8821C BIT(11) #define BIT_USB_LPM_ACT_EN_8821C BIT(10) @@ -939,6 +1033,7 @@ #define BIT_SDIO_PAD_E_8821C(x) (((x) & BIT_MASK_SDIO_PAD_E_8821C) << BIT_SHIFT_SDIO_PAD_E_8821C) #define BIT_GET_SDIO_PAD_E_8821C(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8821C) & BIT_MASK_SDIO_PAD_E_8821C) + #define BIT_USB_LPPLL_EN_8821C BIT(4) #define BIT_ROP_SW15_8821C BIT(2) #define BIT_PCI_CKRDY_OPT_8821C BIT(1) @@ -956,35 +1051,41 @@ #define BIT_GET_AUTO_ZCD_IN_CODE_8821C(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C) + #define BIT_SHIFT_ZCD_CODE_IN_L_8821C 16 #define BIT_MASK_ZCD_CODE_IN_L_8821C 0x1f #define BIT_ZCD_CODE_IN_L_8821C(x) (((x) & BIT_MASK_ZCD_CODE_IN_L_8821C) << BIT_SHIFT_ZCD_CODE_IN_L_8821C) #define BIT_GET_ZCD_CODE_IN_L_8821C(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8821C) & BIT_MASK_ZCD_CODE_IN_L_8821C) + #define BIT_SHIFT_LDO_HV5_DUMMY_8821C 14 #define BIT_MASK_LDO_HV5_DUMMY_8821C 0x3 #define BIT_LDO_HV5_DUMMY_8821C(x) (((x) & BIT_MASK_LDO_HV5_DUMMY_8821C) << BIT_SHIFT_LDO_HV5_DUMMY_8821C) #define BIT_GET_LDO_HV5_DUMMY_8821C(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8821C) & BIT_MASK_LDO_HV5_DUMMY_8821C) + #define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C 12 #define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C 0x3 #define BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) #define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) + #define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C 10 #define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C 0x3 #define BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) #define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) + #define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C 8 #define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C 0x3 #define BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) #define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) + #define BIT_REG_BYPASS_L_8821C BIT(7) #define BIT_REG_LDOF_L_8821C BIT(6) #define BIT_REG_OCPS_L_8821C BIT(5) @@ -995,6 +1096,7 @@ #define BIT_CFC_L_8821C(x) (((x) & BIT_MASK_CFC_L_8821C) << BIT_SHIFT_CFC_L_8821C) #define BIT_GET_CFC_L_8821C(x) (((x) >> BIT_SHIFT_CFC_L_8821C) & BIT_MASK_CFC_L_8821C) + #define BIT_REG_TYPE_L_8821C BIT(0) /* 2 REG_MCUFW_CTRL_8821C */ @@ -1004,6 +1106,7 @@ #define BIT_RPWM_8821C(x) (((x) & BIT_MASK_RPWM_8821C) << BIT_SHIFT_RPWM_8821C) #define BIT_GET_RPWM_8821C(x) (((x) >> BIT_SHIFT_RPWM_8821C) & BIT_MASK_RPWM_8821C) + #define BIT_ANA_PORT_EN_8821C BIT(22) #define BIT_MAC_PORT_EN_8821C BIT(21) #define BIT_BOOT_FSPI_EN_8821C BIT(20) @@ -1014,6 +1117,7 @@ #define BIT_ROM_PGE_8821C(x) (((x) & BIT_MASK_ROM_PGE_8821C) << BIT_SHIFT_ROM_PGE_8821C) #define BIT_GET_ROM_PGE_8821C(x) (((x) >> BIT_SHIFT_ROM_PGE_8821C) & BIT_MASK_ROM_PGE_8821C) + #define BIT_FW_INIT_RDY_8821C BIT(15) #define BIT_FW_DW_RDY_8821C BIT(14) @@ -1022,6 +1126,7 @@ #define BIT_CPU_CLK_SEL_8821C(x) (((x) & BIT_MASK_CPU_CLK_SEL_8821C) << BIT_SHIFT_CPU_CLK_SEL_8821C) #define BIT_GET_CPU_CLK_SEL_8821C(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8821C) & BIT_MASK_CPU_CLK_SEL_8821C) + #define BIT_CCLK_CHG_MASK_8821C BIT(11) #define BIT_EMEM__TXBUF_CHKSUM_OK_8821C BIT(10) #define BIT_EMEM_TXBUF_DW_RDY_8821C BIT(9) @@ -1043,6 +1148,7 @@ #define BIT_GET_LBKTST_8821C(x) (((x) >> BIT_SHIFT_LBKTST_8821C) & BIT_MASK_LBKTST_8821C) + /* 2 REG_HMEBOX_E0_E1_8821C */ #define BIT_SHIFT_HOST_MSG_E1_8821C 16 @@ -1051,12 +1157,14 @@ #define BIT_GET_HOST_MSG_E1_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8821C) & BIT_MASK_HOST_MSG_E1_8821C) + #define BIT_SHIFT_HOST_MSG_E0_8821C 0 #define BIT_MASK_HOST_MSG_E0_8821C 0xffff #define BIT_HOST_MSG_E0_8821C(x) (((x) & BIT_MASK_HOST_MSG_E0_8821C) << BIT_SHIFT_HOST_MSG_E0_8821C) #define BIT_GET_HOST_MSG_E0_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8821C) & BIT_MASK_HOST_MSG_E0_8821C) + /* 2 REG_HMEBOX_E2_E3_8821C */ #define BIT_SHIFT_HOST_MSG_E3_8821C 16 @@ -1065,12 +1173,14 @@ #define BIT_GET_HOST_MSG_E3_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8821C) & BIT_MASK_HOST_MSG_E3_8821C) + #define BIT_SHIFT_HOST_MSG_E2_8821C 0 #define BIT_MASK_HOST_MSG_E2_8821C 0xffff #define BIT_HOST_MSG_E2_8821C(x) (((x) & BIT_MASK_HOST_MSG_E2_8821C) << BIT_SHIFT_HOST_MSG_E2_8821C) #define BIT_GET_HOST_MSG_E2_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8821C) & BIT_MASK_HOST_MSG_E2_8821C) + /* 2 REG_WLLPS_CTRL_8821C */ #define BIT_WLLPSOP_EABM_8821C BIT(31) #define BIT_WLLPSOP_ACKF_8821C BIT(30) @@ -1090,11 +1200,13 @@ #define BIT_GET_LPLDH12_VADJ_STEP_DN_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) + #define BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C 8 #define BIT_MASK_V15ADJ_L1_STEP_DN_8821C 0x7 #define BIT_V15ADJ_L1_STEP_DN_8821C(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C) << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) #define BIT_GET_V15ADJ_L1_STEP_DN_8821C(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C) + #define BIT_REGU_32K_CLK_EN_8821C BIT(1) #define BIT_WL_LPS_EN_8821C BIT(0) @@ -1109,24 +1221,28 @@ #define BIT_GET_REF_SEL_8821C(x) (((x) >> BIT_SHIFT_REF_SEL_8821C) & BIT_MASK_REF_SEL_8821C) + #define BIT_SHIFT_F0F_SDM_8821C 12 #define BIT_MASK_F0F_SDM_8821C 0x1fff #define BIT_F0F_SDM_8821C(x) (((x) & BIT_MASK_F0F_SDM_8821C) << BIT_SHIFT_F0F_SDM_8821C) #define BIT_GET_F0F_SDM_8821C(x) (((x) >> BIT_SHIFT_F0F_SDM_8821C) & BIT_MASK_F0F_SDM_8821C) + #define BIT_SHIFT_F0N_SDM_8821C 9 #define BIT_MASK_F0N_SDM_8821C 0x7 #define BIT_F0N_SDM_8821C(x) (((x) & BIT_MASK_F0N_SDM_8821C) << BIT_SHIFT_F0N_SDM_8821C) #define BIT_GET_F0N_SDM_8821C(x) (((x) >> BIT_SHIFT_F0N_SDM_8821C) & BIT_MASK_F0N_SDM_8821C) + #define BIT_SHIFT_DIVN_SDM_8821C 3 #define BIT_MASK_DIVN_SDM_8821C 0x3f #define BIT_DIVN_SDM_8821C(x) (((x) & BIT_MASK_DIVN_SDM_8821C) << BIT_SHIFT_DIVN_SDM_8821C) #define BIT_GET_DIVN_SDM_8821C(x) (((x) >> BIT_SHIFT_DIVN_SDM_8821C) & BIT_MASK_DIVN_SDM_8821C) + /* 2 REG_GPIO_DEBOUNCE_CTRL_8821C */ #define BIT_WLGP_DBC1EN_8821C BIT(15) @@ -1135,6 +1251,7 @@ #define BIT_WLGP_DBC1_8821C(x) (((x) & BIT_MASK_WLGP_DBC1_8821C) << BIT_SHIFT_WLGP_DBC1_8821C) #define BIT_GET_WLGP_DBC1_8821C(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8821C) & BIT_MASK_WLGP_DBC1_8821C) + #define BIT_WLGP_DBC0EN_8821C BIT(7) #define BIT_SHIFT_WLGP_DBC0_8821C 0 @@ -1143,6 +1260,7 @@ #define BIT_GET_WLGP_DBC0_8821C(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8821C) & BIT_MASK_WLGP_DBC0_8821C) + /* 2 REG_RPWM2_8821C */ #define BIT_SHIFT_RPWM2_8821C 16 @@ -1151,6 +1269,7 @@ #define BIT_GET_RPWM2_8821C(x) (((x) >> BIT_SHIFT_RPWM2_8821C) & BIT_MASK_RPWM2_8821C) + /* 2 REG_SYSON_FSM_MON_8821C */ #define BIT_SHIFT_FSM_MON_SEL_8821C 24 @@ -1158,6 +1277,7 @@ #define BIT_FSM_MON_SEL_8821C(x) (((x) & BIT_MASK_FSM_MON_SEL_8821C) << BIT_SHIFT_FSM_MON_SEL_8821C) #define BIT_GET_FSM_MON_SEL_8821C(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8821C) & BIT_MASK_FSM_MON_SEL_8821C) + #define BIT_DOP_ELDO_8821C BIT(23) #define BIT_FSM_MON_UPD_8821C BIT(15) @@ -1167,6 +1287,7 @@ #define BIT_GET_FSM_PAR_8821C(x) (((x) >> BIT_SHIFT_FSM_PAR_8821C) & BIT_MASK_FSM_PAR_8821C) + /* 2 REG_AFE_CTRL6_8821C */ #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0 @@ -1175,6 +1296,7 @@ #define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) + /* 2 REG_PMC_DBG_CTRL1_8821C */ #define BIT_BT_INT_EN_8821C BIT(31) @@ -1183,6 +1305,7 @@ #define BIT_RD_WR_WIFI_BT_INFO_8821C(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) #define BIT_GET_RD_WR_WIFI_BT_INFO_8821C(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) + #define BIT_PMC_WR_OVF_8821C BIT(8) #define BIT_SHIFT_WLPMC_ERRINT_8821C 0 @@ -1191,6 +1314,7 @@ #define BIT_GET_WLPMC_ERRINT_8821C(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8821C) & BIT_MASK_WLPMC_ERRINT_8821C) + /* 2 REG_AFE_CTRL7_8821C */ #define BIT_SHIFT_SEL_V_8821C 30 @@ -1198,6 +1322,7 @@ #define BIT_SEL_V_8821C(x) (((x) & BIT_MASK_SEL_V_8821C) << BIT_SHIFT_SEL_V_8821C) #define BIT_GET_SEL_V_8821C(x) (((x) >> BIT_SHIFT_SEL_V_8821C) & BIT_MASK_SEL_V_8821C) + #define BIT_SEL_LDO_PC_8821C BIT(29) #define BIT_SHIFT_CK_MON_SEL_8821C 26 @@ -1205,6 +1330,7 @@ #define BIT_CK_MON_SEL_8821C(x) (((x) & BIT_MASK_CK_MON_SEL_8821C) << BIT_SHIFT_CK_MON_SEL_8821C) #define BIT_GET_CK_MON_SEL_8821C(x) (((x) >> BIT_SHIFT_CK_MON_SEL_8821C) & BIT_MASK_CK_MON_SEL_8821C) + #define BIT_CK_MON_EN_8821C BIT(25) #define BIT_FREF_EDGE_8821C BIT(24) #define BIT_CK320M_EN_8821C BIT(23) @@ -1335,6 +1461,7 @@ #define BIT_GET_DEBUG_ST_8821C(x) (((x) >> BIT_SHIFT_DEBUG_ST_8821C) & BIT_MASK_DEBUG_ST_8821C) + /* 2 REG_PAD_CTRL2_8821C */ #define BIT_USB3_USB2_TRANSITION_8821C BIT(20) @@ -1343,6 +1470,7 @@ #define BIT_USB23_SW_MODE_V1_8821C(x) (((x) & BIT_MASK_USB23_SW_MODE_V1_8821C) << BIT_SHIFT_USB23_SW_MODE_V1_8821C) #define BIT_GET_USB23_SW_MODE_V1_8821C(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8821C) & BIT_MASK_USB23_SW_MODE_V1_8821C) + #define BIT_NO_PDN_CHIPOFF_V1_8821C BIT(17) #define BIT_RSM_EN_V1_8821C BIT(16) @@ -1351,6 +1479,7 @@ #define BIT_MATCH_CNT_8821C(x) (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C) #define BIT_GET_MATCH_CNT_8821C(x) (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C) + #define BIT_LD_B12V_EN_8821C BIT(7) #define BIT_EECS_IOSEL_V1_8821C BIT(6) #define BIT_EECS_DATA_O_V1_8821C BIT(5) @@ -1368,6 +1497,7 @@ #define BIT_EFUSE_BURN_GNT_8821C(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8821C) << BIT_SHIFT_EFUSE_BURN_GNT_8821C) #define BIT_GET_EFUSE_BURN_GNT_8821C(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8821C) & BIT_MASK_EFUSE_BURN_GNT_8821C) + #define BIT_STOP_WL_PMC_8821C BIT(9) #define BIT_STOP_SYM_PMC_8821C BIT(8) #define BIT_BT_ACCESS_WL_PAGE0_8821C BIT(6) @@ -1382,6 +1512,7 @@ #define BIT_GET_SYSON_REG_ARB_8821C(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8821C) & BIT_MASK_SYSON_REG_ARB_8821C) + /* 2 REG_BIST_CTRL_8821C */ #define BIT_BIST_USB_DIS_8821C BIT(27) #define BIT_BIST_PCI_DIS_8821C BIT(26) @@ -1393,6 +1524,7 @@ #define BIT_BIST_RPT_SEL_8821C(x) (((x) & BIT_MASK_BIST_RPT_SEL_8821C) << BIT_SHIFT_BIST_RPT_SEL_8821C) #define BIT_GET_BIST_RPT_SEL_8821C(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8821C) & BIT_MASK_BIST_RPT_SEL_8821C) + #define BIT_BIST_RESUME_PS_8821C BIT(4) #define BIT_BIST_RESUME_8821C BIT(3) #define BIT_BIST_NORMAL_8821C BIT(2) @@ -1407,6 +1539,7 @@ #define BIT_GET_MBIST_REPORT_8821C(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8821C) & BIT_MASK_MBIST_REPORT_8821C) + /* 2 REG_MEM_CTRL_8821C */ #define BIT_UMEM_RME_8821C BIT(31) @@ -1416,42 +1549,49 @@ #define BIT_GET_BT_SPRAM_8821C(x) (((x) >> BIT_SHIFT_BT_SPRAM_8821C) & BIT_MASK_BT_SPRAM_8821C) + #define BIT_SHIFT_BT_ROM_8821C 24 #define BIT_MASK_BT_ROM_8821C 0xf #define BIT_BT_ROM_8821C(x) (((x) & BIT_MASK_BT_ROM_8821C) << BIT_SHIFT_BT_ROM_8821C) #define BIT_GET_BT_ROM_8821C(x) (((x) >> BIT_SHIFT_BT_ROM_8821C) & BIT_MASK_BT_ROM_8821C) + #define BIT_SHIFT_PCI_DPRAM_8821C 10 #define BIT_MASK_PCI_DPRAM_8821C 0x3 #define BIT_PCI_DPRAM_8821C(x) (((x) & BIT_MASK_PCI_DPRAM_8821C) << BIT_SHIFT_PCI_DPRAM_8821C) #define BIT_GET_PCI_DPRAM_8821C(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8821C) & BIT_MASK_PCI_DPRAM_8821C) + #define BIT_SHIFT_PCI_SPRAM_8821C 8 #define BIT_MASK_PCI_SPRAM_8821C 0x3 #define BIT_PCI_SPRAM_8821C(x) (((x) & BIT_MASK_PCI_SPRAM_8821C) << BIT_SHIFT_PCI_SPRAM_8821C) #define BIT_GET_PCI_SPRAM_8821C(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8821C) & BIT_MASK_PCI_SPRAM_8821C) + #define BIT_SHIFT_USB_SPRAM_8821C 6 #define BIT_MASK_USB_SPRAM_8821C 0x3 #define BIT_USB_SPRAM_8821C(x) (((x) & BIT_MASK_USB_SPRAM_8821C) << BIT_SHIFT_USB_SPRAM_8821C) #define BIT_GET_USB_SPRAM_8821C(x) (((x) >> BIT_SHIFT_USB_SPRAM_8821C) & BIT_MASK_USB_SPRAM_8821C) + #define BIT_SHIFT_USB_SPRF_8821C 4 #define BIT_MASK_USB_SPRF_8821C 0x3 #define BIT_USB_SPRF_8821C(x) (((x) & BIT_MASK_USB_SPRF_8821C) << BIT_SHIFT_USB_SPRF_8821C) #define BIT_GET_USB_SPRF_8821C(x) (((x) >> BIT_SHIFT_USB_SPRF_8821C) & BIT_MASK_USB_SPRF_8821C) + #define BIT_SHIFT_MCU_ROM_8821C 0 #define BIT_MASK_MCU_ROM_8821C 0xf #define BIT_MCU_ROM_8821C(x) (((x) & BIT_MASK_MCU_ROM_8821C) << BIT_SHIFT_MCU_ROM_8821C) #define BIT_GET_MCU_ROM_8821C(x) (((x) >> BIT_SHIFT_MCU_ROM_8821C) & BIT_MASK_MCU_ROM_8821C) + /* 2 REG_AFE_CTRL8_8821C */ #define BIT_SYN_AGPIO_8821C BIT(20) #define BIT_XTAL_LP_8821C BIT(4) @@ -1463,6 +1603,7 @@ #define BIT_GET_XTAL_SEL_TOK_8821C(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8821C) & BIT_MASK_XTAL_SEL_TOK_8821C) + /* 2 REG_USB_SIE_INTF_8821C */ #define BIT_RD_SEL_8821C BIT(31) #define BIT_USB_SIE_INTF_WE_V1_8821C BIT(30) @@ -1475,18 +1616,21 @@ #define BIT_GET_USB_SIE_INTF_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) + #define BIT_SHIFT_USB_SIE_INTF_RD_8821C 8 #define BIT_MASK_USB_SIE_INTF_RD_8821C 0xff #define BIT_USB_SIE_INTF_RD_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_RD_8821C) << BIT_SHIFT_USB_SIE_INTF_RD_8821C) #define BIT_GET_USB_SIE_INTF_RD_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8821C) & BIT_MASK_USB_SIE_INTF_RD_8821C) + #define BIT_SHIFT_USB_SIE_INTF_WD_8821C 0 #define BIT_MASK_USB_SIE_INTF_WD_8821C 0xff #define BIT_USB_SIE_INTF_WD_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_WD_8821C) << BIT_SHIFT_USB_SIE_INTF_WD_8821C) #define BIT_GET_USB_SIE_INTF_WD_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8821C) & BIT_MASK_USB_SIE_INTF_WD_8821C) + /* 2 REG_PCIE_MIO_INTF_8821C */ #define BIT_PCIE_MIO_BYIOREG_8821C BIT(13) #define BIT_PCIE_MIO_RE_8821C BIT(12) @@ -1497,12 +1641,14 @@ #define BIT_GET_PCIE_MIO_WE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8821C) & BIT_MASK_PCIE_MIO_WE_8821C) + #define BIT_SHIFT_PCIE_MIO_ADDR_8821C 0 #define BIT_MASK_PCIE_MIO_ADDR_8821C 0xff #define BIT_PCIE_MIO_ADDR_8821C(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8821C) << BIT_SHIFT_PCIE_MIO_ADDR_8821C) #define BIT_GET_PCIE_MIO_ADDR_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8821C) & BIT_MASK_PCIE_MIO_ADDR_8821C) + /* 2 REG_PCIE_MIO_INTD_8821C */ #define BIT_SHIFT_PCIE_MIO_DATA_8821C 0 @@ -1511,6 +1657,7 @@ #define BIT_GET_PCIE_MIO_DATA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8821C) & BIT_MASK_PCIE_MIO_DATA_8821C) + /* 2 REG_WLRF1_8821C */ #define BIT_SHIFT_WLRF1_CTRL_8821C 24 @@ -1519,6 +1666,7 @@ #define BIT_GET_WLRF1_CTRL_8821C(x) (((x) >> BIT_SHIFT_WLRF1_CTRL_8821C) & BIT_MASK_WLRF1_CTRL_8821C) + /* 2 REG_SYS_CFG1_8821C */ #define BIT_SHIFT_TRP_ICFG_8821C 28 @@ -1526,6 +1674,7 @@ #define BIT_TRP_ICFG_8821C(x) (((x) & BIT_MASK_TRP_ICFG_8821C) << BIT_SHIFT_TRP_ICFG_8821C) #define BIT_GET_TRP_ICFG_8821C(x) (((x) >> BIT_SHIFT_TRP_ICFG_8821C) & BIT_MASK_TRP_ICFG_8821C) + #define BIT_RF_TYPE_ID_8821C BIT(27) #define BIT_BD_HCI_SEL_8821C BIT(26) #define BIT_BD_PKG_SEL_8821C BIT(25) @@ -1540,11 +1689,13 @@ #define BIT_GET_VENDOR_ID_8821C(x) (((x) >> BIT_SHIFT_VENDOR_ID_8821C) & BIT_MASK_VENDOR_ID_8821C) + #define BIT_SHIFT_CHIP_VER_8821C 12 #define BIT_MASK_CHIP_VER_8821C 0xf #define BIT_CHIP_VER_8821C(x) (((x) & BIT_MASK_CHIP_VER_8821C) << BIT_SHIFT_CHIP_VER_8821C) #define BIT_GET_CHIP_VER_8821C(x) (((x) >> BIT_SHIFT_CHIP_VER_8821C) & BIT_MASK_CHIP_VER_8821C) + #define BIT_BD_MAC3_8821C BIT(11) #define BIT_BD_MAC1_8821C BIT(10) #define BIT_BD_MAC2_8821C BIT(9) @@ -1565,6 +1716,7 @@ #define BIT_RF_RL_ID_8821C(x) (((x) & BIT_MASK_RF_RL_ID_8821C) << BIT_SHIFT_RF_RL_ID_8821C) #define BIT_GET_RF_RL_ID_8821C(x) (((x) >> BIT_SHIFT_RF_RL_ID_8821C) & BIT_MASK_RF_RL_ID_8821C) + #define BIT_HPHY_ICFG_8821C BIT(19) #define BIT_SHIFT_SEL_0XC0_8821C 16 @@ -1572,6 +1724,7 @@ #define BIT_SEL_0XC0_8821C(x) (((x) & BIT_MASK_SEL_0XC0_8821C) << BIT_SHIFT_SEL_0XC0_8821C) #define BIT_GET_SEL_0XC0_8821C(x) (((x) >> BIT_SHIFT_SEL_0XC0_8821C) & BIT_MASK_SEL_0XC0_8821C) + #define BIT_USB_OPERATION_MODE_8821C BIT(10) #define BIT_BT_PDN_8821C BIT(9) #define BIT_AUTO_WLPON_8821C BIT(8) @@ -1584,18 +1737,21 @@ #define BIT_GET_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_HCI_SEL_8821C) & BIT_MASK_HCI_SEL_8821C) + #define BIT_SHIFT_PAD_HCI_SEL_8821C 2 #define BIT_MASK_PAD_HCI_SEL_8821C 0x3 #define BIT_PAD_HCI_SEL_8821C(x) (((x) & BIT_MASK_PAD_HCI_SEL_8821C) << BIT_SHIFT_PAD_HCI_SEL_8821C) #define BIT_GET_PAD_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_8821C) & BIT_MASK_PAD_HCI_SEL_8821C) + #define BIT_SHIFT_EFS_HCI_SEL_8821C 0 #define BIT_MASK_EFS_HCI_SEL_8821C 0x3 #define BIT_EFS_HCI_SEL_8821C(x) (((x) & BIT_MASK_EFS_HCI_SEL_8821C) << BIT_SHIFT_EFS_HCI_SEL_8821C) #define BIT_GET_EFS_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_8821C) & BIT_MASK_EFS_HCI_SEL_8821C) + /* 2 REG_SYS_STATUS2_8821C */ #define BIT_SIO_ALDN_8821C BIT(19) #define BIT_USB_ALDN_8821C BIT(18) @@ -1608,12 +1764,14 @@ #define BIT_GET_EPVID1_8821C(x) (((x) >> BIT_SHIFT_EPVID1_8821C) & BIT_MASK_EPVID1_8821C) + #define BIT_SHIFT_EPVID0_8821C 0 #define BIT_MASK_EPVID0_8821C 0xff #define BIT_EPVID0_8821C(x) (((x) & BIT_MASK_EPVID0_8821C) << BIT_SHIFT_EPVID0_8821C) #define BIT_GET_EPVID0_8821C(x) (((x) >> BIT_SHIFT_EPVID0_8821C) & BIT_MASK_EPVID0_8821C) + /* 2 REG_SYS_CFG2_8821C */ #define BIT_HCI_SEL_EMBEDED_8821C BIT(8) @@ -1623,6 +1781,7 @@ #define BIT_GET_HW_ID_8821C(x) (((x) >> BIT_SHIFT_HW_ID_8821C) & BIT_MASK_HW_ID_8821C) + /* 2 REG_SYS_CFG3_8821C */ #define BIT_PWC_MA33V_8821C BIT(15) #define BIT_PWC_MA12V_8821C BIT(14) @@ -1656,6 +1815,7 @@ #define BIT_GET_CPU_DMEM_CON_8821C(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8821C) & BIT_MASK_CPU_DMEM_CON_8821C) + /* 2 REG_BOOT_REASON_8821C */ #define BIT_SHIFT_BOOT_REASON_8821C 0 @@ -1664,6 +1824,7 @@ #define BIT_GET_BOOT_REASON_8821C(x) (((x) >> BIT_SHIFT_BOOT_REASON_8821C) & BIT_MASK_BOOT_REASON_8821C) + /* 2 REG_NFCPAD_CTRL_8821C */ #define BIT_PAD_SHUTDW_8821C BIT(18) #define BIT_SYSON_NFC_PAD_8821C BIT(17) @@ -1679,18 +1840,21 @@ #define BIT_GET_NFCPAD_IO_SEL_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8821C) & BIT_MASK_NFCPAD_IO_SEL_8821C) + #define BIT_SHIFT_NFCPAD_OUT_8821C 4 #define BIT_MASK_NFCPAD_OUT_8821C 0xf #define BIT_NFCPAD_OUT_8821C(x) (((x) & BIT_MASK_NFCPAD_OUT_8821C) << BIT_SHIFT_NFCPAD_OUT_8821C) #define BIT_GET_NFCPAD_OUT_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_OUT_8821C) & BIT_MASK_NFCPAD_OUT_8821C) + #define BIT_SHIFT_NFCPAD_IN_8821C 0 #define BIT_MASK_NFCPAD_IN_8821C 0xf #define BIT_NFCPAD_IN_8821C(x) (((x) & BIT_MASK_NFCPAD_IN_8821C) << BIT_SHIFT_NFCPAD_IN_8821C) #define BIT_GET_NFCPAD_IN_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_IN_8821C) & BIT_MASK_NFCPAD_IN_8821C) + /* 2 REG_HIMR2_8821C */ #define BIT_BCNDMAINT_P4_MSK_8821C BIT(31) #define BIT_BCNDMAINT_P3_MSK_8821C BIT(30) @@ -1813,6 +1977,7 @@ #define BIT_GET_H2C_PKT_READADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8821C) & BIT_MASK_H2C_PKT_READADDR_8821C) + /* 2 REG_H2C_PKT_WRITEADDR_8821C */ #define BIT_SHIFT_H2C_PKT_WRITEADDR_8821C 0 @@ -1821,6 +1986,7 @@ #define BIT_GET_H2C_PKT_WRITEADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) & BIT_MASK_H2C_PKT_WRITEADDR_8821C) + /* 2 REG_MEM_PWR_CRTL_8821C */ #define BIT_MEM_BB_SD_8821C BIT(17) #define BIT_MEM_BB_DS_8821C BIT(16) @@ -1844,6 +2010,7 @@ #define BIT_GET_FW_DBG0_8821C(x) (((x) >> BIT_SHIFT_FW_DBG0_8821C) & BIT_MASK_FW_DBG0_8821C) + /* 2 REG_FW_DBG1_8821C */ #define BIT_SHIFT_FW_DBG1_8821C 0 @@ -1852,6 +2019,7 @@ #define BIT_GET_FW_DBG1_8821C(x) (((x) >> BIT_SHIFT_FW_DBG1_8821C) & BIT_MASK_FW_DBG1_8821C) + /* 2 REG_FW_DBG2_8821C */ #define BIT_SHIFT_FW_DBG2_8821C 0 @@ -1860,6 +2028,7 @@ #define BIT_GET_FW_DBG2_8821C(x) (((x) >> BIT_SHIFT_FW_DBG2_8821C) & BIT_MASK_FW_DBG2_8821C) + /* 2 REG_FW_DBG3_8821C */ #define BIT_SHIFT_FW_DBG3_8821C 0 @@ -1868,6 +2037,7 @@ #define BIT_GET_FW_DBG3_8821C(x) (((x) >> BIT_SHIFT_FW_DBG3_8821C) & BIT_MASK_FW_DBG3_8821C) + /* 2 REG_FW_DBG4_8821C */ #define BIT_SHIFT_FW_DBG4_8821C 0 @@ -1876,6 +2046,7 @@ #define BIT_GET_FW_DBG4_8821C(x) (((x) >> BIT_SHIFT_FW_DBG4_8821C) & BIT_MASK_FW_DBG4_8821C) + /* 2 REG_FW_DBG5_8821C */ #define BIT_SHIFT_FW_DBG5_8821C 0 @@ -1884,6 +2055,7 @@ #define BIT_GET_FW_DBG5_8821C(x) (((x) >> BIT_SHIFT_FW_DBG5_8821C) & BIT_MASK_FW_DBG5_8821C) + /* 2 REG_FW_DBG6_8821C */ #define BIT_SHIFT_FW_DBG6_8821C 0 @@ -1892,6 +2064,7 @@ #define BIT_GET_FW_DBG6_8821C(x) (((x) >> BIT_SHIFT_FW_DBG6_8821C) & BIT_MASK_FW_DBG6_8821C) + /* 2 REG_FW_DBG7_8821C */ #define BIT_SHIFT_FW_DBG7_8821C 0 @@ -1900,6 +2073,7 @@ #define BIT_GET_FW_DBG7_8821C(x) (((x) >> BIT_SHIFT_FW_DBG7_8821C) & BIT_MASK_FW_DBG7_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_CR_8821C */ @@ -1910,17 +2084,20 @@ #define BIT_GET_LBMODE_8821C(x) (((x) >> BIT_SHIFT_LBMODE_8821C) & BIT_MASK_LBMODE_8821C) + #define BIT_SHIFT_NETYPE1_8821C 18 #define BIT_MASK_NETYPE1_8821C 0x3 #define BIT_NETYPE1_8821C(x) (((x) & BIT_MASK_NETYPE1_8821C) << BIT_SHIFT_NETYPE1_8821C) #define BIT_GET_NETYPE1_8821C(x) (((x) >> BIT_SHIFT_NETYPE1_8821C) & BIT_MASK_NETYPE1_8821C) + #define BIT_SHIFT_NETYPE0_8821C 16 #define BIT_MASK_NETYPE0_8821C 0x3 #define BIT_NETYPE0_8821C(x) (((x) & BIT_MASK_NETYPE0_8821C) << BIT_SHIFT_NETYPE0_8821C) #define BIT_GET_NETYPE0_8821C(x) (((x) >> BIT_SHIFT_NETYPE0_8821C) & BIT_MASK_NETYPE0_8821C) + #define BIT_I2C_MAILBOX_EN_8821C BIT(12) #define BIT_SHCUT_EN_8821C BIT(11) #define BIT_32K_CAL_TMR_EN_8821C BIT(10) @@ -1945,7 +2122,6 @@ #define BIT_GET_PKT_BUFF_ACCESS_CTRL_8821C(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) -/* 2 REG_NOT_VALID_8821C */ /* 2 REG_TSF_CLK_STATE_8821C */ #define BIT_TSF_CLK_STABLE_8821C BIT(15) @@ -1958,39 +2134,47 @@ #define BIT_GET_TXDMA_HIQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8821C) & BIT_MASK_TXDMA_HIQ_MAP_8821C) + #define BIT_SHIFT_TXDMA_MGQ_MAP_8821C 12 #define BIT_MASK_TXDMA_MGQ_MAP_8821C 0x3 #define BIT_TXDMA_MGQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8821C) << BIT_SHIFT_TXDMA_MGQ_MAP_8821C) #define BIT_GET_TXDMA_MGQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8821C) & BIT_MASK_TXDMA_MGQ_MAP_8821C) + #define BIT_SHIFT_TXDMA_BKQ_MAP_8821C 10 #define BIT_MASK_TXDMA_BKQ_MAP_8821C 0x3 #define BIT_TXDMA_BKQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8821C) << BIT_SHIFT_TXDMA_BKQ_MAP_8821C) #define BIT_GET_TXDMA_BKQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8821C) & BIT_MASK_TXDMA_BKQ_MAP_8821C) + #define BIT_SHIFT_TXDMA_BEQ_MAP_8821C 8 #define BIT_MASK_TXDMA_BEQ_MAP_8821C 0x3 #define BIT_TXDMA_BEQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8821C) << BIT_SHIFT_TXDMA_BEQ_MAP_8821C) #define BIT_GET_TXDMA_BEQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8821C) & BIT_MASK_TXDMA_BEQ_MAP_8821C) + #define BIT_SHIFT_TXDMA_VIQ_MAP_8821C 6 #define BIT_MASK_TXDMA_VIQ_MAP_8821C 0x3 #define BIT_TXDMA_VIQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8821C) << BIT_SHIFT_TXDMA_VIQ_MAP_8821C) #define BIT_GET_TXDMA_VIQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8821C) & BIT_MASK_TXDMA_VIQ_MAP_8821C) + #define BIT_SHIFT_TXDMA_VOQ_MAP_8821C 4 #define BIT_MASK_TXDMA_VOQ_MAP_8821C 0x3 #define BIT_TXDMA_VOQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8821C) << BIT_SHIFT_TXDMA_VOQ_MAP_8821C) #define BIT_GET_TXDMA_VOQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8821C) & BIT_MASK_TXDMA_VOQ_MAP_8821C) + #define BIT_RXDMA_AGG_EN_8821C BIT(2) #define BIT_RXSHFT_EN_8821C BIT(1) #define BIT_RXDMA_ARBBW_EN_8821C BIT(0) +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_TRXFF_BNDY_8821C */ #define BIT_SHIFT_RXFFOVFL_RSV_V2_8821C 8 @@ -1999,12 +2183,14 @@ #define BIT_GET_RXFFOVFL_RSV_V2_8821C(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) & BIT_MASK_RXFFOVFL_RSV_V2_8821C) + #define BIT_SHIFT_TXPKTBUF_PGBNDY_8821C 0 #define BIT_MASK_TXPKTBUF_PGBNDY_8821C 0xff #define BIT_TXPKTBUF_PGBNDY_8821C(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8821C) << BIT_SHIFT_TXPKTBUF_PGBNDY_8821C) #define BIT_GET_TXPKTBUF_PGBNDY_8821C(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8821C) & BIT_MASK_TXPKTBUF_PGBNDY_8821C) + /* 2 REG_PTA_I2C_MBOX_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -2015,11 +2201,13 @@ #define BIT_GET_I2C_M_STATUS_8821C(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8821C) & BIT_MASK_I2C_M_STATUS_8821C) + #define BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C 4 #define BIT_MASK_I2C_M_BUS_GNT_FW_8821C 0x7 #define BIT_I2C_M_BUS_GNT_FW_8821C(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) #define BIT_GET_I2C_M_BUS_GNT_FW_8821C(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C) + #define BIT_I2C_M_GNT_FW_8821C BIT(3) #define BIT_SHIFT_I2C_M_SPEED_8821C 1 @@ -2027,6 +2215,7 @@ #define BIT_I2C_M_SPEED_8821C(x) (((x) & BIT_MASK_I2C_M_SPEED_8821C) << BIT_SHIFT_I2C_M_SPEED_8821C) #define BIT_GET_I2C_M_SPEED_8821C(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8821C) & BIT_MASK_I2C_M_SPEED_8821C) + #define BIT_I2C_M_UNLOCK_8821C BIT(0) /* 2 REG_RXFF_BNDY_8821C */ @@ -2039,6 +2228,7 @@ #define BIT_GET_RXFF0_BNDY_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8821C) & BIT_MASK_RXFF0_BNDY_V2_8821C) + /* 2 REG_FE1IMR_8821C */ #define BIT_FS_RXDMA2_DONE_INT_EN_8821C BIT(28) #define BIT_FS_RXDONE3_INT_EN_8821C BIT(27) @@ -2108,6 +2298,7 @@ #define BIT_GET_CPWM_MOD_8821C(x) (((x) >> BIT_SHIFT_CPWM_MOD_8821C) & BIT_MASK_CPWM_MOD_8821C) + /* 2 REG_FWIMR_8821C */ #define BIT_FS_TXBCNOK_MB7_INT_EN_8821C BIT(31) #define BIT_FS_TXBCNOK_MB6_INT_EN_8821C BIT(30) @@ -2227,6 +2418,7 @@ #define BIT_PKTBUF_WRITE_EN_8821C(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8821C) << BIT_SHIFT_PKTBUF_WRITE_EN_8821C) #define BIT_GET_PKTBUF_WRITE_EN_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8821C) & BIT_MASK_PKTBUF_WRITE_EN_8821C) + #define BIT_TXRPTBUF_DBG_8821C BIT(23) /* 2 REG_NOT_VALID_8821C */ @@ -2239,6 +2431,7 @@ #define BIT_GET_PKTBUF_DBG_ADDR_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) & BIT_MASK_PKTBUF_DBG_ADDR_8821C) + /* 2 REG_PKTBUF_DBG_DATA_L_8821C */ #define BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C 0 @@ -2247,6 +2440,7 @@ #define BIT_GET_PKTBUF_DBG_DATA_L_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C) + /* 2 REG_PKTBUF_DBG_DATA_H_8821C */ #define BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C 0 @@ -2255,6 +2449,7 @@ #define BIT_GET_PKTBUF_DBG_DATA_H_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C) + /* 2 REG_CPWM2_8821C */ #define BIT_SHIFT_L0S_TO_RCVY_NUM_8821C 16 @@ -2262,6 +2457,7 @@ #define BIT_L0S_TO_RCVY_NUM_8821C(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8821C) << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) #define BIT_GET_L0S_TO_RCVY_NUM_8821C(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) & BIT_MASK_L0S_TO_RCVY_NUM_8821C) + #define BIT_CPWM2_TOGGLING_8821C BIT(15) #define BIT_SHIFT_CPWM2_MOD_8821C 0 @@ -2270,7 +2466,6 @@ #define BIT_GET_CPWM2_MOD_8821C(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8821C) & BIT_MASK_CPWM2_MOD_8821C) -/* 2 REG_NOT_VALID_8821C */ /* 2 REG_TC0_CTRL_8821C */ #define BIT_TC0INT_EN_8821C BIT(26) @@ -2283,6 +2478,7 @@ #define BIT_GET_TC0DATA_8821C(x) (((x) >> BIT_SHIFT_TC0DATA_8821C) & BIT_MASK_TC0DATA_8821C) + /* 2 REG_TC1_CTRL_8821C */ #define BIT_TC1INT_EN_8821C BIT(26) #define BIT_TC1MODE_8821C BIT(25) @@ -2294,6 +2490,7 @@ #define BIT_GET_TC1DATA_8821C(x) (((x) >> BIT_SHIFT_TC1DATA_8821C) & BIT_MASK_TC1DATA_8821C) + /* 2 REG_TC2_CTRL_8821C */ #define BIT_TC2INT_EN_8821C BIT(26) #define BIT_TC2MODE_8821C BIT(25) @@ -2305,6 +2502,7 @@ #define BIT_GET_TC2DATA_8821C(x) (((x) >> BIT_SHIFT_TC2DATA_8821C) & BIT_MASK_TC2DATA_8821C) + /* 2 REG_TC3_CTRL_8821C */ #define BIT_TC3INT_EN_8821C BIT(26) #define BIT_TC3MODE_8821C BIT(25) @@ -2316,6 +2514,7 @@ #define BIT_GET_TC3DATA_8821C(x) (((x) >> BIT_SHIFT_TC3DATA_8821C) & BIT_MASK_TC3DATA_8821C) + /* 2 REG_TC4_CTRL_8821C */ #define BIT_TC4INT_EN_8821C BIT(26) #define BIT_TC4MODE_8821C BIT(25) @@ -2327,6 +2526,7 @@ #define BIT_GET_TC4DATA_8821C(x) (((x) >> BIT_SHIFT_TC4DATA_8821C) & BIT_MASK_TC4DATA_8821C) + /* 2 REG_TCUNIT_BASE_8821C */ #define BIT_SHIFT_TCUNIT_BASE_8821C 0 @@ -2335,6 +2535,7 @@ #define BIT_GET_TCUNIT_BASE_8821C(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8821C) & BIT_MASK_TCUNIT_BASE_8821C) + /* 2 REG_TC5_CTRL_8821C */ #define BIT_TC5INT_EN_8821C BIT(26) #define BIT_TC5MODE_8821C BIT(25) @@ -2346,6 +2547,7 @@ #define BIT_GET_TC5DATA_8821C(x) (((x) >> BIT_SHIFT_TC5DATA_8821C) & BIT_MASK_TC5DATA_8821C) + /* 2 REG_TC6_CTRL_8821C */ #define BIT_TC6INT_EN_8821C BIT(26) #define BIT_TC6MODE_8821C BIT(25) @@ -2357,6 +2559,7 @@ #define BIT_GET_TC6DATA_8821C(x) (((x) >> BIT_SHIFT_TC6DATA_8821C) & BIT_MASK_TC6DATA_8821C) + /* 2 REG_MBIST_FAIL_8821C */ #define BIT_SHIFT_8051_MBIST_FAIL_8821C 26 @@ -2365,24 +2568,28 @@ #define BIT_GET_8051_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8821C) & BIT_MASK_8051_MBIST_FAIL_8821C) + #define BIT_SHIFT_USB_MBIST_FAIL_8821C 24 #define BIT_MASK_USB_MBIST_FAIL_8821C 0x3 #define BIT_USB_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8821C) << BIT_SHIFT_USB_MBIST_FAIL_8821C) #define BIT_GET_USB_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8821C) & BIT_MASK_USB_MBIST_FAIL_8821C) + #define BIT_SHIFT_PCIE_MBIST_FAIL_8821C 16 #define BIT_MASK_PCIE_MBIST_FAIL_8821C 0x3f #define BIT_PCIE_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8821C) << BIT_SHIFT_PCIE_MBIST_FAIL_8821C) #define BIT_GET_PCIE_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8821C) & BIT_MASK_PCIE_MBIST_FAIL_8821C) + #define BIT_SHIFT_MAC_MBIST_FAIL_8821C 0 #define BIT_MASK_MAC_MBIST_FAIL_8821C 0xfff #define BIT_MAC_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_8821C) << BIT_SHIFT_MAC_MBIST_FAIL_8821C) #define BIT_GET_MAC_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8821C) & BIT_MASK_MAC_MBIST_FAIL_8821C) + /* 2 REG_MBIST_START_PAUSE_8821C */ #define BIT_SHIFT_8051_MBIST_START_PAUSE_8821C 26 @@ -2391,24 +2598,28 @@ #define BIT_GET_8051_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8821C) & BIT_MASK_8051_MBIST_START_PAUSE_8821C) + #define BIT_SHIFT_USB_MBIST_START_PAUSE_8821C 24 #define BIT_MASK_USB_MBIST_START_PAUSE_8821C 0x3 #define BIT_USB_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8821C) << BIT_SHIFT_USB_MBIST_START_PAUSE_8821C) #define BIT_GET_USB_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8821C) & BIT_MASK_USB_MBIST_START_PAUSE_8821C) + #define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C 16 #define BIT_MASK_PCIE_MBIST_START_PAUSE_8821C 0x3f #define BIT_PCIE_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8821C) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C) #define BIT_GET_PCIE_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C) & BIT_MASK_PCIE_MBIST_START_PAUSE_8821C) + #define BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C 0 #define BIT_MASK_MAC_MBIST_START_PAUSE_8821C 0xfff #define BIT_MAC_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8821C) << BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C) #define BIT_GET_MAC_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C) & BIT_MASK_MAC_MBIST_START_PAUSE_8821C) + /* 2 REG_MBIST_DONE_8821C */ #define BIT_SHIFT_8051_MBIST_DONE_8821C 26 @@ -2417,24 +2628,28 @@ #define BIT_GET_8051_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8821C) & BIT_MASK_8051_MBIST_DONE_8821C) + #define BIT_SHIFT_USB_MBIST_DONE_8821C 24 #define BIT_MASK_USB_MBIST_DONE_8821C 0x3 #define BIT_USB_MBIST_DONE_8821C(x) (((x) & BIT_MASK_USB_MBIST_DONE_8821C) << BIT_SHIFT_USB_MBIST_DONE_8821C) #define BIT_GET_USB_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8821C) & BIT_MASK_USB_MBIST_DONE_8821C) + #define BIT_SHIFT_PCIE_MBIST_DONE_8821C 16 #define BIT_MASK_PCIE_MBIST_DONE_8821C 0x3f #define BIT_PCIE_MBIST_DONE_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8821C) << BIT_SHIFT_PCIE_MBIST_DONE_8821C) #define BIT_GET_PCIE_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8821C) & BIT_MASK_PCIE_MBIST_DONE_8821C) + #define BIT_SHIFT_MAC_MBIST_DONE_8821C 0 #define BIT_MASK_MAC_MBIST_DONE_8821C 0xfff #define BIT_MAC_MBIST_DONE_8821C(x) (((x) & BIT_MASK_MAC_MBIST_DONE_8821C) << BIT_SHIFT_MAC_MBIST_DONE_8821C) #define BIT_GET_MAC_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8821C) & BIT_MASK_MAC_MBIST_DONE_8821C) + /* 2 REG_MBIST_FAIL_NRML_8821C */ #define BIT_SHIFT_MBIST_FAIL_NRML_8821C 0 @@ -2443,6 +2658,7 @@ #define BIT_GET_MBIST_FAIL_NRML_8821C(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8821C) & BIT_MASK_MBIST_FAIL_NRML_8821C) + /* 2 REG_AES_DECRPT_DATA_8821C */ #define BIT_SHIFT_IPS_CFG_ADDR_8821C 0 @@ -2451,6 +2667,7 @@ #define BIT_GET_IPS_CFG_ADDR_8821C(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8821C) & BIT_MASK_IPS_CFG_ADDR_8821C) + /* 2 REG_AES_DECRPT_CFG_8821C */ #define BIT_SHIFT_IPS_CFG_DATA_8821C 0 @@ -2459,6 +2676,7 @@ #define BIT_GET_IPS_CFG_DATA_8821C(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8821C) & BIT_MASK_IPS_CFG_DATA_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -2472,17 +2690,20 @@ #define BIT_GET_TEMP_VALUE_8821C(x) (((x) >> BIT_SHIFT_TEMP_VALUE_8821C) & BIT_MASK_TEMP_VALUE_8821C) + #define BIT_SHIFT_REG_TMETER_TIMER_8821C 8 #define BIT_MASK_REG_TMETER_TIMER_8821C 0xfff #define BIT_REG_TMETER_TIMER_8821C(x) (((x) & BIT_MASK_REG_TMETER_TIMER_8821C) << BIT_SHIFT_REG_TMETER_TIMER_8821C) #define BIT_GET_REG_TMETER_TIMER_8821C(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8821C) & BIT_MASK_REG_TMETER_TIMER_8821C) + #define BIT_SHIFT_REG_TEMP_DELTA_8821C 2 #define BIT_MASK_REG_TEMP_DELTA_8821C 0x3f #define BIT_REG_TEMP_DELTA_8821C(x) (((x) & BIT_MASK_REG_TEMP_DELTA_8821C) << BIT_SHIFT_REG_TEMP_DELTA_8821C) #define BIT_GET_REG_TEMP_DELTA_8821C(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8821C) & BIT_MASK_REG_TEMP_DELTA_8821C) + #define BIT_REG_TMETER_EN_8821C BIT(0) /* 2 REG_OSC_32K_CTRL_8821C */ @@ -2493,11 +2714,13 @@ #define BIT_GET_OSC_32K_CLKGEN_0_8821C(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) & BIT_MASK_OSC_32K_CLKGEN_0_8821C) + #define BIT_SHIFT_OSC_32K_RES_COMP_8821C 4 #define BIT_MASK_OSC_32K_RES_COMP_8821C 0x3 #define BIT_OSC_32K_RES_COMP_8821C(x) (((x) & BIT_MASK_OSC_32K_RES_COMP_8821C) << BIT_SHIFT_OSC_32K_RES_COMP_8821C) #define BIT_GET_OSC_32K_RES_COMP_8821C(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8821C) & BIT_MASK_OSC_32K_RES_COMP_8821C) + #define BIT_OSC_32K_OUT_SEL_8821C BIT(3) #define BIT_ISO_WL_2_OSC_32K_8821C BIT(1) #define BIT_POW_CKGEN_8821C BIT(0) @@ -2512,28 +2735,72 @@ #define BIT_GET_CAL_32K_REG_ADDR_8821C(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8821C) & BIT_MASK_CAL_32K_REG_ADDR_8821C) + #define BIT_SHIFT_CAL_32K_REG_DATA_8821C 0 #define BIT_MASK_CAL_32K_REG_DATA_8821C 0xffff #define BIT_CAL_32K_REG_DATA_8821C(x) (((x) & BIT_MASK_CAL_32K_REG_DATA_8821C) << BIT_SHIFT_CAL_32K_REG_DATA_8821C) #define BIT_GET_CAL_32K_REG_DATA_8821C(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8821C) & BIT_MASK_CAL_32K_REG_DATA_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_C2HEVT_8821C */ -#define BIT_SHIFT_C2HEVT_MSG_8821C 0 -#define BIT_MASK_C2HEVT_MSG_8821C 0xffffffffffffffffffffffffffffffffL -#define BIT_C2HEVT_MSG_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_8821C) << BIT_SHIFT_C2HEVT_MSG_8821C) -#define BIT_GET_C2HEVT_MSG_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_8821C) & BIT_MASK_C2HEVT_MSG_8821C) +#define BIT_SHIFT_C2HEVT_MSG_V1_8821C 0 +#define BIT_MASK_C2HEVT_MSG_V1_8821C 0xffffffffL +#define BIT_C2HEVT_MSG_V1_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_V1_8821C) << BIT_SHIFT_C2HEVT_MSG_V1_8821C) +#define BIT_GET_C2HEVT_MSG_V1_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8821C) & BIT_MASK_C2HEVT_MSG_V1_8821C) + + + +/* 2 REG_C2HEVT_1_8821C */ + +#define BIT_SHIFT_C2HEVT_MSG_1_8821C 0 +#define BIT_MASK_C2HEVT_MSG_1_8821C 0xffffffffL +#define BIT_C2HEVT_MSG_1_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_1_8821C) << BIT_SHIFT_C2HEVT_MSG_1_8821C) +#define BIT_GET_C2HEVT_MSG_1_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8821C) & BIT_MASK_C2HEVT_MSG_1_8821C) + + + +/* 2 REG_C2HEVT_2_8821C */ + +#define BIT_SHIFT_C2HEVT_MSG_2_8821C 0 +#define BIT_MASK_C2HEVT_MSG_2_8821C 0xffffffffL +#define BIT_C2HEVT_MSG_2_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_2_8821C) << BIT_SHIFT_C2HEVT_MSG_2_8821C) +#define BIT_GET_C2HEVT_MSG_2_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8821C) & BIT_MASK_C2HEVT_MSG_2_8821C) + +/* 2 REG_C2HEVT_3_8821C */ + +#define BIT_SHIFT_C2HEVT_MSG_3_8821C 0 +#define BIT_MASK_C2HEVT_MSG_3_8821C 0xffffffffL +#define BIT_C2HEVT_MSG_3_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_3_8821C) << BIT_SHIFT_C2HEVT_MSG_3_8821C) +#define BIT_GET_C2HEVT_MSG_3_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8821C) & BIT_MASK_C2HEVT_MSG_3_8821C) + + + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_SW_DEFINED_PAGE1_8821C */ -#define BIT_SHIFT_SW_DEFINED_PAGE1_8821C 0 -#define BIT_MASK_SW_DEFINED_PAGE1_8821C 0xffffffffffffffffL -#define BIT_SW_DEFINED_PAGE1_8821C(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_8821C) << BIT_SHIFT_SW_DEFINED_PAGE1_8821C) -#define BIT_GET_SW_DEFINED_PAGE1_8821C(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8821C) & BIT_MASK_SW_DEFINED_PAGE1_8821C) +#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C 0 +#define BIT_MASK_SW_DEFINED_PAGE1_V1_8821C 0xffffffffL +#define BIT_SW_DEFINED_PAGE1_V1_8821C(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) +#define BIT_GET_SW_DEFINED_PAGE1_V1_8821C(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) + + + +/* 2 REG_SW_DEFINED_PAGE2_8821C */ + +#define BIT_SHIFT_SW_DEFINED_PAGE2_8821C 0 +#define BIT_MASK_SW_DEFINED_PAGE2_8821C 0xffffffffL +#define BIT_SW_DEFINED_PAGE2_8821C(x) (((x) & BIT_MASK_SW_DEFINED_PAGE2_8821C) << BIT_SHIFT_SW_DEFINED_PAGE2_8821C) +#define BIT_GET_SW_DEFINED_PAGE2_8821C(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8821C) & BIT_MASK_SW_DEFINED_PAGE2_8821C) + /* 2 REG_MCUTST_I_8821C */ @@ -2544,6 +2811,7 @@ #define BIT_GET_MCUDMSG_I_8821C(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8821C) & BIT_MASK_MCUDMSG_I_8821C) + /* 2 REG_MCUTST_II_8821C */ #define BIT_SHIFT_MCUDMSG_II_8821C 0 @@ -2552,6 +2820,7 @@ #define BIT_GET_MCUDMSG_II_8821C(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8821C) & BIT_MASK_MCUDMSG_II_8821C) + /* 2 REG_FMETHR_8821C */ #define BIT_FMSG_INT_8821C BIT(31) @@ -2561,6 +2830,7 @@ #define BIT_GET_FW_MSG_8821C(x) (((x) >> BIT_SHIFT_FW_MSG_8821C) & BIT_MASK_FW_MSG_8821C) + /* 2 REG_HMETFR_8821C */ #define BIT_SHIFT_HRCV_MSG_8821C 24 @@ -2568,6 +2838,7 @@ #define BIT_HRCV_MSG_8821C(x) (((x) & BIT_MASK_HRCV_MSG_8821C) << BIT_SHIFT_HRCV_MSG_8821C) #define BIT_GET_HRCV_MSG_8821C(x) (((x) >> BIT_SHIFT_HRCV_MSG_8821C) & BIT_MASK_HRCV_MSG_8821C) + #define BIT_INT_BOX3_8821C BIT(3) #define BIT_INT_BOX2_8821C BIT(2) #define BIT_INT_BOX1_8821C BIT(1) @@ -2581,6 +2852,7 @@ #define BIT_GET_HOST_MSG_0_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8821C) & BIT_MASK_HOST_MSG_0_8821C) + /* 2 REG_HMEBOX1_8821C */ #define BIT_SHIFT_HOST_MSG_1_8821C 0 @@ -2589,6 +2861,7 @@ #define BIT_GET_HOST_MSG_1_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8821C) & BIT_MASK_HOST_MSG_1_8821C) + /* 2 REG_HMEBOX2_8821C */ #define BIT_SHIFT_HOST_MSG_2_8821C 0 @@ -2597,6 +2870,7 @@ #define BIT_GET_HOST_MSG_2_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8821C) & BIT_MASK_HOST_MSG_2_8821C) + /* 2 REG_HMEBOX3_8821C */ #define BIT_SHIFT_HOST_MSG_3_8821C 0 @@ -2605,6 +2879,7 @@ #define BIT_GET_HOST_MSG_3_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8821C) & BIT_MASK_HOST_MSG_3_8821C) + /* 2 REG_LLT_INIT_8821C */ #define BIT_SHIFT_LLTE_RWM_8821C 30 @@ -2613,18 +2888,21 @@ #define BIT_GET_LLTE_RWM_8821C(x) (((x) >> BIT_SHIFT_LLTE_RWM_8821C) & BIT_MASK_LLTE_RWM_8821C) + #define BIT_SHIFT_LLTINI_PDATA_V1_8821C 16 #define BIT_MASK_LLTINI_PDATA_V1_8821C 0xfff #define BIT_LLTINI_PDATA_V1_8821C(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8821C) << BIT_SHIFT_LLTINI_PDATA_V1_8821C) #define BIT_GET_LLTINI_PDATA_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8821C) & BIT_MASK_LLTINI_PDATA_V1_8821C) + #define BIT_SHIFT_LLTINI_HDATA_V1_8821C 0 #define BIT_MASK_LLTINI_HDATA_V1_8821C 0xfff #define BIT_LLTINI_HDATA_V1_8821C(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8821C) << BIT_SHIFT_LLTINI_HDATA_V1_8821C) #define BIT_GET_LLTINI_HDATA_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8821C) & BIT_MASK_LLTINI_HDATA_V1_8821C) + /* 2 REG_LLT_INIT_ADDR_8821C */ #define BIT_SHIFT_LLTINI_ADDR_V1_8821C 0 @@ -2633,6 +2911,7 @@ #define BIT_GET_LLTINI_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8821C) & BIT_MASK_LLTINI_ADDR_V1_8821C) + /* 2 REG_BB_ACCESS_CTRL_8821C */ #define BIT_SHIFT_BB_WRITE_READ_8821C 30 @@ -2641,17 +2920,20 @@ #define BIT_GET_BB_WRITE_READ_8821C(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8821C) & BIT_MASK_BB_WRITE_READ_8821C) + #define BIT_SHIFT_BB_WRITE_EN_8821C 12 #define BIT_MASK_BB_WRITE_EN_8821C 0xf #define BIT_BB_WRITE_EN_8821C(x) (((x) & BIT_MASK_BB_WRITE_EN_8821C) << BIT_SHIFT_BB_WRITE_EN_8821C) #define BIT_GET_BB_WRITE_EN_8821C(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_8821C) & BIT_MASK_BB_WRITE_EN_8821C) + #define BIT_SHIFT_BB_ADDR_8821C 2 #define BIT_MASK_BB_ADDR_8821C 0x1ff #define BIT_BB_ADDR_8821C(x) (((x) & BIT_MASK_BB_ADDR_8821C) << BIT_SHIFT_BB_ADDR_8821C) #define BIT_GET_BB_ADDR_8821C(x) (((x) >> BIT_SHIFT_BB_ADDR_8821C) & BIT_MASK_BB_ADDR_8821C) + #define BIT_BB_ERRACC_8821C BIT(0) /* 2 REG_BB_ACCESS_DATA_8821C */ @@ -2662,6 +2944,7 @@ #define BIT_GET_BB_DATA_8821C(x) (((x) >> BIT_SHIFT_BB_DATA_8821C) & BIT_MASK_BB_DATA_8821C) + /* 2 REG_HMEBOX_E0_8821C */ #define BIT_SHIFT_HMEBOX_E0_8821C 0 @@ -2670,6 +2953,7 @@ #define BIT_GET_HMEBOX_E0_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8821C) & BIT_MASK_HMEBOX_E0_8821C) + /* 2 REG_HMEBOX_E1_8821C */ #define BIT_SHIFT_HMEBOX_E1_8821C 0 @@ -2678,6 +2962,7 @@ #define BIT_GET_HMEBOX_E1_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8821C) & BIT_MASK_HMEBOX_E1_8821C) + /* 2 REG_HMEBOX_E2_8821C */ #define BIT_SHIFT_HMEBOX_E2_8821C 0 @@ -2686,6 +2971,7 @@ #define BIT_GET_HMEBOX_E2_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8821C) & BIT_MASK_HMEBOX_E2_8821C) + /* 2 REG_HMEBOX_E3_8821C */ #define BIT_SHIFT_HMEBOX_E3_8821C 0 @@ -2694,7 +2980,6 @@ #define BIT_GET_HMEBOX_E3_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8821C) & BIT_MASK_HMEBOX_E3_8821C) -/* 2 REG_NOT_VALID_8821C */ /* 2 REG_CR_EXT_8821C */ @@ -2704,6 +2989,7 @@ #define BIT_GET_PHY_REQ_DELAY_8821C(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8821C) & BIT_MASK_PHY_REQ_DELAY_8821C) + /* 2 REG_NOT_VALID_8821C */ #define BIT_SPD_DOWN_8821C BIT(16) @@ -2715,18 +3001,29 @@ #define BIT_GET_NETYPE4_8821C(x) (((x) >> BIT_SHIFT_NETYPE4_8821C) & BIT_MASK_NETYPE4_8821C) + #define BIT_SHIFT_NETYPE3_8821C 2 #define BIT_MASK_NETYPE3_8821C 0x3 #define BIT_NETYPE3_8821C(x) (((x) & BIT_MASK_NETYPE3_8821C) << BIT_SHIFT_NETYPE3_8821C) #define BIT_GET_NETYPE3_8821C(x) (((x) >> BIT_SHIFT_NETYPE3_8821C) & BIT_MASK_NETYPE3_8821C) + #define BIT_SHIFT_NETYPE2_8821C 0 #define BIT_MASK_NETYPE2_8821C 0x3 #define BIT_NETYPE2_8821C(x) (((x) & BIT_MASK_NETYPE2_8821C) << BIT_SHIFT_NETYPE2_8821C) #define BIT_GET_NETYPE2_8821C(x) (((x) >> BIT_SHIFT_NETYPE2_8821C) & BIT_MASK_NETYPE2_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_FWFF_8821C */ #define BIT_SHIFT_PKTNUM_TH_V1_8821C 24 @@ -2735,18 +3032,21 @@ #define BIT_GET_PKTNUM_TH_V1_8821C(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8821C) & BIT_MASK_PKTNUM_TH_V1_8821C) + #define BIT_SHIFT_TIMER_TH_8821C 16 #define BIT_MASK_TIMER_TH_8821C 0xff #define BIT_TIMER_TH_8821C(x) (((x) & BIT_MASK_TIMER_TH_8821C) << BIT_SHIFT_TIMER_TH_8821C) #define BIT_GET_TIMER_TH_8821C(x) (((x) >> BIT_SHIFT_TIMER_TH_8821C) & BIT_MASK_TIMER_TH_8821C) + #define BIT_SHIFT_RXPKT1ENADDR_8821C 0 #define BIT_MASK_RXPKT1ENADDR_8821C 0xffff #define BIT_RXPKT1ENADDR_8821C(x) (((x) & BIT_MASK_RXPKT1ENADDR_8821C) << BIT_SHIFT_RXPKT1ENADDR_8821C) #define BIT_GET_RXPKT1ENADDR_8821C(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8821C) & BIT_MASK_RXPKT1ENADDR_8821C) + /* 2 REG_RXFF_PTR_V1_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -2757,6 +3057,7 @@ #define BIT_GET_RXFF0_RDPTR_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8821C) & BIT_MASK_RXFF0_RDPTR_V2_8821C) + /* 2 REG_RXFF_WTR_V1_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -2767,6 +3068,7 @@ #define BIT_GET_RXFF0_WTPTR_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8821C) & BIT_MASK_RXFF0_WTPTR_V2_8821C) + /* 2 REG_FE2IMR_8821C */ #define BIT__FE4ISR__IND_MSK_8821C BIT(29) #define BIT_FS_TXSC_DESC_DONE_INT_EN_8821C BIT(28) @@ -3003,6 +3305,7 @@ #define BIT_GET_MID_31TO0_8821C(x) (((x) >> BIT_SHIFT_MID_31TO0_8821C) & BIT_MASK_MID_31TO0_8821C) + /* 2 REG_SPWR1_8821C */ #define BIT_SHIFT_MID_63TO32_8821C 0 @@ -3011,6 +3314,7 @@ #define BIT_GET_MID_63TO32_8821C(x) (((x) >> BIT_SHIFT_MID_63TO32_8821C) & BIT_MASK_MID_63TO32_8821C) + /* 2 REG_SPWR2_8821C */ #define BIT_SHIFT_MID_95O64_8821C 0 @@ -3019,6 +3323,7 @@ #define BIT_GET_MID_95O64_8821C(x) (((x) >> BIT_SHIFT_MID_95O64_8821C) & BIT_MASK_MID_95O64_8821C) + /* 2 REG_SPWR3_8821C */ #define BIT_SHIFT_MID_127TO96_8821C 0 @@ -3027,6 +3332,7 @@ #define BIT_GET_MID_127TO96_8821C(x) (((x) >> BIT_SHIFT_MID_127TO96_8821C) & BIT_MASK_MID_127TO96_8821C) + /* 2 REG_POWSEQ_8821C */ #define BIT_SHIFT_SEQNUM_MID_8821C 16 @@ -3035,12 +3341,16 @@ #define BIT_GET_SEQNUM_MID_8821C(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8821C) & BIT_MASK_SEQNUM_MID_8821C) + #define BIT_SHIFT_REF_MID_8821C 0 #define BIT_MASK_REF_MID_8821C 0x7f #define BIT_REF_MID_8821C(x) (((x) & BIT_MASK_REF_MID_8821C) << BIT_SHIFT_REF_MID_8821C) #define BIT_GET_REF_MID_8821C(x) (((x) >> BIT_SHIFT_REF_MID_8821C) & BIT_MASK_REF_MID_8821C) + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_TC7_CTRL_V1_8821C */ #define BIT_TC7INT_EN_8821C BIT(26) #define BIT_TC7MODE_8821C BIT(25) @@ -3052,6 +3362,7 @@ #define BIT_GET_TC7DATA_8821C(x) (((x) >> BIT_SHIFT_TC7DATA_8821C) & BIT_MASK_TC7DATA_8821C) + /* 2 REG_TC8_CTRL_V1_8821C */ #define BIT_TC8INT_EN_8821C BIT(26) #define BIT_TC8MODE_8821C BIT(25) @@ -3063,6 +3374,71 @@ #define BIT_GET_TC8DATA_8821C(x) (((x) >> BIT_SHIFT_TC8DATA_8821C) & BIT_MASK_TC8DATA_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_FT2IMR_8821C */ #define BIT_FS_CLI3_RX_UAPSDMD1_EN_8821C BIT(31) #define BIT_FS_CLI3_RX_UAPSDMD0_EN_8821C BIT(30) @@ -3119,6 +3495,10 @@ #define BIT_FS_CLI0_TX_NULL1_INT_8821C BIT(1) #define BIT_FS_CLI0_TX_NULL0_INT_8821C BIT(0) +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_MSG2_8821C */ #define BIT_SHIFT_FW_MSG2_8821C 0 @@ -3127,6 +3507,7 @@ #define BIT_GET_FW_MSG2_8821C(x) (((x) >> BIT_SHIFT_FW_MSG2_8821C) & BIT_MASK_FW_MSG2_8821C) + /* 2 REG_MSG3_8821C */ #define BIT_SHIFT_FW_MSG3_8821C 0 @@ -3135,6 +3516,7 @@ #define BIT_GET_FW_MSG3_8821C(x) (((x) >> BIT_SHIFT_FW_MSG3_8821C) & BIT_MASK_FW_MSG3_8821C) + /* 2 REG_MSG4_8821C */ #define BIT_SHIFT_FW_MSG4_8821C 0 @@ -3143,6 +3525,7 @@ #define BIT_GET_FW_MSG4_8821C(x) (((x) >> BIT_SHIFT_FW_MSG4_8821C) & BIT_MASK_FW_MSG4_8821C) + /* 2 REG_MSG5_8821C */ #define BIT_SHIFT_FW_MSG5_8821C 0 @@ -3151,38 +3534,51 @@ #define BIT_GET_FW_MSG5_8821C(x) (((x) >> BIT_SHIFT_FW_MSG5_8821C) & BIT_MASK_FW_MSG5_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_FIFOPAGE_CTRL_1_8821C */ +/* 2 REG_NOT_VALID_8821C */ + #define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C 16 #define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C 0xff #define BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) #define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8821C(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) + +/* 2 REG_NOT_VALID_8821C */ + #define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C 0 #define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C 0xff #define BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) #define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8821C(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) + /* 2 REG_FIFOPAGE_CTRL_2_8821C */ #define BIT_BCN_VALID_1_V1_8821C BIT(31) +/* 2 REG_NOT_VALID_8821C */ + #define BIT_SHIFT_BCN_HEAD_1_V1_8821C 16 #define BIT_MASK_BCN_HEAD_1_V1_8821C 0xfff #define BIT_BCN_HEAD_1_V1_8821C(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8821C) << BIT_SHIFT_BCN_HEAD_1_V1_8821C) #define BIT_GET_BCN_HEAD_1_V1_8821C(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8821C) & BIT_MASK_BCN_HEAD_1_V1_8821C) + #define BIT_BCN_VALID_V1_8821C BIT(15) +/* 2 REG_NOT_VALID_8821C */ + #define BIT_SHIFT_BCN_HEAD_V1_8821C 0 #define BIT_MASK_BCN_HEAD_V1_8821C 0xfff #define BIT_BCN_HEAD_V1_8821C(x) (((x) & BIT_MASK_BCN_HEAD_V1_8821C) << BIT_SHIFT_BCN_HEAD_V1_8821C) #define BIT_GET_BCN_HEAD_V1_8821C(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8821C) & BIT_MASK_BCN_HEAD_V1_8821C) + /* 2 REG_AUTO_LLT_V1_8821C */ #define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 24 @@ -3191,17 +3587,20 @@ #define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) + #define BIT_SHIFT_LLT_FREE_PAGE_V1_8821C 8 #define BIT_MASK_LLT_FREE_PAGE_V1_8821C 0xffff #define BIT_LLT_FREE_PAGE_V1_8821C(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8821C) << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) #define BIT_GET_LLT_FREE_PAGE_V1_8821C(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) & BIT_MASK_LLT_FREE_PAGE_V1_8821C) + #define BIT_SHIFT_BLK_DESC_NUM_8821C 4 #define BIT_MASK_BLK_DESC_NUM_8821C 0xf #define BIT_BLK_DESC_NUM_8821C(x) (((x) & BIT_MASK_BLK_DESC_NUM_8821C) << BIT_SHIFT_BLK_DESC_NUM_8821C) #define BIT_GET_BLK_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8821C) & BIT_MASK_BLK_DESC_NUM_8821C) + #define BIT_R_BCN_HEAD_SEL_8821C BIT(3) #define BIT_R_EN_BCN_SW_HEAD_SEL_8821C BIT(2) #define BIT_LLT_DBG_SEL_8821C BIT(1) @@ -3218,6 +3617,9 @@ #define BIT_PG_UNDER_TH_V1_8821C(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8821C) << BIT_SHIFT_PG_UNDER_TH_V1_8821C) #define BIT_GET_PG_UNDER_TH_V1_8821C(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8821C) & BIT_MASK_PG_UNDER_TH_V1_8821C) + + +/* 2 REG_NOT_VALID_8821C */ #define BIT_SDIO_TXDESC_CHKSUM_EN_8821C BIT(13) #define BIT_RST_RDPTR_8821C BIT(12) #define BIT_RST_WRPTR_8821C BIT(11) @@ -3231,6 +3633,7 @@ #define BIT_GET_CHECK_OFFSET_8821C(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8821C) & BIT_MASK_CHECK_OFFSET_8821C) + /* 2 REG_TXDMA_STATUS_8821C */ #define BIT_TXPKTBUF_REQ_ERR_8821C BIT(18) #define BIT_HI_OQT_UDN_8821C BIT(17) @@ -3262,12 +3665,14 @@ #define BIT_GET_HPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) & BIT_MASK_HPQ_HIGH_TH_V1_8821C) + #define BIT_SHIFT_HPQ_LOW_TH_V1_8821C 0 #define BIT_MASK_HPQ_LOW_TH_V1_8821C 0xfff #define BIT_HPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8821C) << BIT_SHIFT_HPQ_LOW_TH_V1_8821C) #define BIT_GET_HPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8821C) & BIT_MASK_HPQ_LOW_TH_V1_8821C) + /* 2 REG_TQPNT2_8821C */ #define BIT_SHIFT_NPQ_HIGH_TH_V1_8821C 16 @@ -3276,12 +3681,14 @@ #define BIT_GET_NPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) & BIT_MASK_NPQ_HIGH_TH_V1_8821C) + #define BIT_SHIFT_NPQ_LOW_TH_V1_8821C 0 #define BIT_MASK_NPQ_LOW_TH_V1_8821C 0xfff #define BIT_NPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8821C) << BIT_SHIFT_NPQ_LOW_TH_V1_8821C) #define BIT_GET_NPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8821C) & BIT_MASK_NPQ_LOW_TH_V1_8821C) + /* 2 REG_TQPNT3_8821C */ #define BIT_SHIFT_LPQ_HIGH_TH_V1_8821C 16 @@ -3290,12 +3697,14 @@ #define BIT_GET_LPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) & BIT_MASK_LPQ_HIGH_TH_V1_8821C) + #define BIT_SHIFT_LPQ_LOW_TH_V1_8821C 0 #define BIT_MASK_LPQ_LOW_TH_V1_8821C 0xfff #define BIT_LPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8821C) << BIT_SHIFT_LPQ_LOW_TH_V1_8821C) #define BIT_GET_LPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8821C) & BIT_MASK_LPQ_LOW_TH_V1_8821C) + /* 2 REG_TQPNT4_8821C */ #define BIT_SHIFT_EXQ_HIGH_TH_V1_8821C 16 @@ -3304,12 +3713,14 @@ #define BIT_GET_EXQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) & BIT_MASK_EXQ_HIGH_TH_V1_8821C) + #define BIT_SHIFT_EXQ_LOW_TH_V1_8821C 0 #define BIT_MASK_EXQ_LOW_TH_V1_8821C 0xfff #define BIT_EXQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8821C) << BIT_SHIFT_EXQ_LOW_TH_V1_8821C) #define BIT_GET_EXQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8821C) & BIT_MASK_EXQ_LOW_TH_V1_8821C) + /* 2 REG_RQPN_CTRL_1_8821C */ #define BIT_SHIFT_TXPKTNUM_H_8821C 16 @@ -3318,12 +3729,14 @@ #define BIT_GET_TXPKTNUM_H_8821C(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8821C) & BIT_MASK_TXPKTNUM_H_8821C) + #define BIT_SHIFT_TXPKTNUM_V2_8821C 0 #define BIT_MASK_TXPKTNUM_V2_8821C 0xffff #define BIT_TXPKTNUM_V2_8821C(x) (((x) & BIT_MASK_TXPKTNUM_V2_8821C) << BIT_SHIFT_TXPKTNUM_V2_8821C) #define BIT_GET_TXPKTNUM_V2_8821C(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2_8821C) & BIT_MASK_TXPKTNUM_V2_8821C) + /* 2 REG_RQPN_CTRL_2_8821C */ #define BIT_LD_RQPN_8821C BIT(31) #define BIT_EXQ_PUBLIC_DIS_V1_8821C BIT(19) @@ -3338,6 +3751,7 @@ #define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8821C(x) (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) + /* 2 REG_FIFOPAGE_INFO_1_8821C */ #define BIT_SHIFT_HPQ_AVAL_PG_V1_8821C 16 @@ -3346,12 +3760,14 @@ #define BIT_GET_HPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) & BIT_MASK_HPQ_AVAL_PG_V1_8821C) + #define BIT_SHIFT_HPQ_V1_8821C 0 #define BIT_MASK_HPQ_V1_8821C 0xfff #define BIT_HPQ_V1_8821C(x) (((x) & BIT_MASK_HPQ_V1_8821C) << BIT_SHIFT_HPQ_V1_8821C) #define BIT_GET_HPQ_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_V1_8821C) & BIT_MASK_HPQ_V1_8821C) + /* 2 REG_FIFOPAGE_INFO_2_8821C */ #define BIT_SHIFT_LPQ_AVAL_PG_V1_8821C 16 @@ -3360,18 +3776,21 @@ #define BIT_GET_LPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) & BIT_MASK_LPQ_AVAL_PG_V1_8821C) + #define BIT_SHIFT_LPQ_V1_8821C 0 #define BIT_MASK_LPQ_V1_8821C 0xfff #define BIT_LPQ_V1_8821C(x) (((x) & BIT_MASK_LPQ_V1_8821C) << BIT_SHIFT_LPQ_V1_8821C) #define BIT_GET_LPQ_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_V1_8821C) & BIT_MASK_LPQ_V1_8821C) + /* 2 REG_FIFOPAGE_INFO_3_8821C */ -#define BIT_SHIFT_NPQ_AVAL_PG_8821C 8 -#define BIT_MASK_NPQ_AVAL_PG_8821C 0xff -#define BIT_NPQ_AVAL_PG_8821C(x) (((x) & BIT_MASK_NPQ_AVAL_PG_8821C) << BIT_SHIFT_NPQ_AVAL_PG_8821C) -#define BIT_GET_NPQ_AVAL_PG_8821C(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_8821C) & BIT_MASK_NPQ_AVAL_PG_8821C) +#define BIT_SHIFT_NPQ_AVAL_PG_V1_8821C 16 +#define BIT_MASK_NPQ_AVAL_PG_V1_8821C 0xfff +#define BIT_NPQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8821C) << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) +#define BIT_GET_NPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) & BIT_MASK_NPQ_AVAL_PG_V1_8821C) + #define BIT_SHIFT_NPQ_V1_8821C 0 @@ -3380,6 +3799,7 @@ #define BIT_GET_NPQ_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_V1_8821C) & BIT_MASK_NPQ_V1_8821C) + /* 2 REG_FIFOPAGE_INFO_4_8821C */ #define BIT_SHIFT_EXQ_AVAL_PG_V1_8821C 16 @@ -3388,12 +3808,14 @@ #define BIT_GET_EXQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) & BIT_MASK_EXQ_AVAL_PG_V1_8821C) + #define BIT_SHIFT_EXQ_V1_8821C 0 #define BIT_MASK_EXQ_V1_8821C 0xfff #define BIT_EXQ_V1_8821C(x) (((x) & BIT_MASK_EXQ_V1_8821C) << BIT_SHIFT_EXQ_V1_8821C) #define BIT_GET_EXQ_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_V1_8821C) & BIT_MASK_EXQ_V1_8821C) + /* 2 REG_FIFOPAGE_INFO_5_8821C */ #define BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C 16 @@ -3402,12 +3824,14 @@ #define BIT_GET_PUBQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C) + #define BIT_SHIFT_PUBQ_V1_8821C 0 #define BIT_MASK_PUBQ_V1_8821C 0xfff #define BIT_PUBQ_V1_8821C(x) (((x) & BIT_MASK_PUBQ_V1_8821C) << BIT_SHIFT_PUBQ_V1_8821C) #define BIT_GET_PUBQ_V1_8821C(x) (((x) >> BIT_SHIFT_PUBQ_V1_8821C) & BIT_MASK_PUBQ_V1_8821C) + /* 2 REG_H2C_HEAD_8821C */ #define BIT_SHIFT_H2C_HEAD_8821C 0 @@ -3416,6 +3840,7 @@ #define BIT_GET_H2C_HEAD_8821C(x) (((x) >> BIT_SHIFT_H2C_HEAD_8821C) & BIT_MASK_H2C_HEAD_8821C) + /* 2 REG_H2C_TAIL_8821C */ #define BIT_SHIFT_H2C_TAIL_8821C 0 @@ -3424,6 +3849,7 @@ #define BIT_GET_H2C_TAIL_8821C(x) (((x) >> BIT_SHIFT_H2C_TAIL_8821C) & BIT_MASK_H2C_TAIL_8821C) + /* 2 REG_H2C_READ_ADDR_8821C */ #define BIT_SHIFT_H2C_READ_ADDR_8821C 0 @@ -3432,6 +3858,7 @@ #define BIT_GET_H2C_READ_ADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8821C) & BIT_MASK_H2C_READ_ADDR_8821C) + /* 2 REG_H2C_WR_ADDR_8821C */ #define BIT_SHIFT_H2C_WR_ADDR_8821C 0 @@ -3440,6 +3867,7 @@ #define BIT_GET_H2C_WR_ADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8821C) & BIT_MASK_H2C_WR_ADDR_8821C) + /* 2 REG_H2C_INFO_8821C */ #define BIT_H2C_SPACE_VLD_8821C BIT(3) #define BIT_H2C_WR_ADDR_RST_8821C BIT(2) @@ -3450,6 +3878,7 @@ #define BIT_GET_H2C_LEN_SEL_8821C(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8821C) & BIT_MASK_H2C_LEN_SEL_8821C) + /* 2 REG_RXDMA_AGG_PG_TH_8821C */ #define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C 24 @@ -3458,24 +3887,28 @@ #define BIT_GET_RXDMA_AGG_OLD_MOD_8821C(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C) & BIT_MASK_RXDMA_AGG_OLD_MOD_8821C) + #define BIT_SHIFT_PKT_NUM_WOL_8821C 16 #define BIT_MASK_PKT_NUM_WOL_8821C 0xff #define BIT_PKT_NUM_WOL_8821C(x) (((x) & BIT_MASK_PKT_NUM_WOL_8821C) << BIT_SHIFT_PKT_NUM_WOL_8821C) #define BIT_GET_PKT_NUM_WOL_8821C(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8821C) & BIT_MASK_PKT_NUM_WOL_8821C) + #define BIT_SHIFT_DMA_AGG_TO_8821C 8 #define BIT_MASK_DMA_AGG_TO_8821C 0xf #define BIT_DMA_AGG_TO_8821C(x) (((x) & BIT_MASK_DMA_AGG_TO_8821C) << BIT_SHIFT_DMA_AGG_TO_8821C) #define BIT_GET_DMA_AGG_TO_8821C(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_8821C) & BIT_MASK_DMA_AGG_TO_8821C) + #define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C 0 #define BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C 0xf #define BIT_RXDMA_AGG_PG_TH_V1_8821C(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C) #define BIT_GET_RXDMA_AGG_PG_TH_V1_8821C(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C) + /* 2 REG_RXPKT_NUM_8821C */ #define BIT_SHIFT_RXPKT_NUM_8821C 24 @@ -3484,11 +3917,13 @@ #define BIT_GET_RXPKT_NUM_8821C(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8821C) & BIT_MASK_RXPKT_NUM_8821C) + #define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C 20 #define BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C 0xf #define BIT_FW_UPD_RDPTR19_TO_16_8821C(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) #define BIT_GET_FW_UPD_RDPTR19_TO_16_8821C(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) + #define BIT_RXDMA_REQ_8821C BIT(19) #define BIT_RW_RELEASE_EN_8821C BIT(18) #define BIT_RXDMA_IDLE_8821C BIT(17) @@ -3500,6 +3935,7 @@ #define BIT_GET_FW_UPD_RDPTR_8821C(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8821C) & BIT_MASK_FW_UPD_RDPTR_8821C) + /* 2 REG_RXDMA_STATUS_8821C */ #define BIT_C2H_PKT_OVF_8821C BIT(7) #define BIT_AGG_CONFGI_ISSUE_8821C BIT(6) @@ -3517,6 +3953,7 @@ #define BIT_GET_RDE_DEBUG_8821C(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8821C) & BIT_MASK_RDE_DEBUG_8821C) + /* 2 REG_RXDMA_MODE_8821C */ #define BIT_SHIFT_PKTNUM_TH_V2_8821C 24 @@ -3524,6 +3961,7 @@ #define BIT_PKTNUM_TH_V2_8821C(x) (((x) & BIT_MASK_PKTNUM_TH_V2_8821C) << BIT_SHIFT_PKTNUM_TH_V2_8821C) #define BIT_GET_PKTNUM_TH_V2_8821C(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8821C) & BIT_MASK_PKTNUM_TH_V2_8821C) + #define BIT_TXBA_BREAK_USBAGG_8821C BIT(23) #define BIT_SHIFT_PKTLEN_PARA_8821C 16 @@ -3532,11 +3970,6 @@ #define BIT_GET_PKTLEN_PARA_8821C(x) (((x) >> BIT_SHIFT_PKTLEN_PARA_8821C) & BIT_MASK_PKTLEN_PARA_8821C) -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ #define BIT_SHIFT_BURST_SIZE_8821C 4 #define BIT_MASK_BURST_SIZE_8821C 0x3 @@ -3544,11 +3977,13 @@ #define BIT_GET_BURST_SIZE_8821C(x) (((x) >> BIT_SHIFT_BURST_SIZE_8821C) & BIT_MASK_BURST_SIZE_8821C) + #define BIT_SHIFT_BURST_CNT_8821C 2 #define BIT_MASK_BURST_CNT_8821C 0x3 #define BIT_BURST_CNT_8821C(x) (((x) & BIT_MASK_BURST_CNT_8821C) << BIT_SHIFT_BURST_CNT_8821C) #define BIT_GET_BURST_CNT_8821C(x) (((x) >> BIT_SHIFT_BURST_CNT_8821C) & BIT_MASK_BURST_CNT_8821C) + #define BIT_DMA_MODE_8821C BIT(1) /* 2 REG_C2H_PKT_8821C */ @@ -3558,6 +3993,7 @@ #define BIT_R_C2H_STR_ADDR_16_TO_19_8821C(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) #define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8821C(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) + #define BIT_R_C2H_PKT_REQ_8821C BIT(16) #define BIT_SHIFT_R_C2H_STR_ADDR_8821C 0 @@ -3566,6 +4002,7 @@ #define BIT_GET_R_C2H_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8821C) & BIT_MASK_R_C2H_STR_ADDR_8821C) + /* 2 REG_FWFF_C2H_8821C */ #define BIT_SHIFT_C2H_DMA_ADDR_8821C 0 @@ -3574,6 +4011,7 @@ #define BIT_GET_C2H_DMA_ADDR_8821C(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8821C) & BIT_MASK_C2H_DMA_ADDR_8821C) + /* 2 REG_FWFF_CTRL_8821C */ #define BIT_FWFF_DMAPKT_REQ_8821C BIT(31) @@ -3583,12 +4021,14 @@ #define BIT_GET_FWFF_DMA_PKT_NUM_8821C(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C) + #define BIT_SHIFT_FWFF_STR_ADDR_8821C 0 #define BIT_MASK_FWFF_STR_ADDR_8821C 0xffff #define BIT_FWFF_STR_ADDR_8821C(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8821C) << BIT_SHIFT_FWFF_STR_ADDR_8821C) #define BIT_GET_FWFF_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8821C) & BIT_MASK_FWFF_STR_ADDR_8821C) + /* 2 REG_FWFF_PKT_INFO_8821C */ #define BIT_SHIFT_FWFF_PKT_QUEUED_8821C 16 @@ -3597,13 +4037,13 @@ #define BIT_GET_FWFF_PKT_QUEUED_8821C(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8821C) & BIT_MASK_FWFF_PKT_QUEUED_8821C) + #define BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C 0 #define BIT_MASK_FWFF_PKT_STR_ADDR_8821C 0xffff #define BIT_FWFF_PKT_STR_ADDR_8821C(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) #define BIT_GET_FWFF_PKT_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C) -/* 2 REG_NOT_VALID_8821C */ /* 2 REG_DDMA_CH0SA_8821C */ @@ -3613,6 +4053,7 @@ #define BIT_GET_DDMACH0_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8821C) & BIT_MASK_DDMACH0_SA_8821C) + /* 2 REG_DDMA_CH0DA_8821C */ #define BIT_SHIFT_DDMACH0_DA_8821C 0 @@ -3621,6 +4062,7 @@ #define BIT_GET_DDMACH0_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8821C) & BIT_MASK_DDMACH0_DA_8821C) + /* 2 REG_DDMA_CH0CTRL_8821C */ #define BIT_DDMACH0_OWN_8821C BIT(31) #define BIT_DDMACH0_CHKSUM_EN_8821C BIT(29) @@ -3636,6 +4078,7 @@ #define BIT_GET_DDMACH0_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8821C) & BIT_MASK_DDMACH0_DLEN_8821C) + /* 2 REG_DDMA_CH1SA_8821C */ #define BIT_SHIFT_DDMACH1_SA_8821C 0 @@ -3644,6 +4087,7 @@ #define BIT_GET_DDMACH1_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8821C) & BIT_MASK_DDMACH1_SA_8821C) + /* 2 REG_DDMA_CH1DA_8821C */ #define BIT_SHIFT_DDMACH1_DA_8821C 0 @@ -3652,6 +4096,7 @@ #define BIT_GET_DDMACH1_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8821C) & BIT_MASK_DDMACH1_DA_8821C) + /* 2 REG_DDMA_CH1CTRL_8821C */ #define BIT_DDMACH1_OWN_8821C BIT(31) #define BIT_DDMACH1_CHKSUM_EN_8821C BIT(29) @@ -3667,6 +4112,7 @@ #define BIT_GET_DDMACH1_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8821C) & BIT_MASK_DDMACH1_DLEN_8821C) + /* 2 REG_DDMA_CH2SA_8821C */ #define BIT_SHIFT_DDMACH2_SA_8821C 0 @@ -3675,6 +4121,7 @@ #define BIT_GET_DDMACH2_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8821C) & BIT_MASK_DDMACH2_SA_8821C) + /* 2 REG_DDMA_CH2DA_8821C */ #define BIT_SHIFT_DDMACH2_DA_8821C 0 @@ -3683,6 +4130,7 @@ #define BIT_GET_DDMACH2_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8821C) & BIT_MASK_DDMACH2_DA_8821C) + /* 2 REG_DDMA_CH2CTRL_8821C */ #define BIT_DDMACH2_OWN_8821C BIT(31) #define BIT_DDMACH2_CHKSUM_EN_8821C BIT(29) @@ -3698,6 +4146,7 @@ #define BIT_GET_DDMACH2_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8821C) & BIT_MASK_DDMACH2_DLEN_8821C) + /* 2 REG_DDMA_CH3SA_8821C */ #define BIT_SHIFT_DDMACH3_SA_8821C 0 @@ -3706,6 +4155,7 @@ #define BIT_GET_DDMACH3_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8821C) & BIT_MASK_DDMACH3_SA_8821C) + /* 2 REG_DDMA_CH3DA_8821C */ #define BIT_SHIFT_DDMACH3_DA_8821C 0 @@ -3714,6 +4164,7 @@ #define BIT_GET_DDMACH3_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8821C) & BIT_MASK_DDMACH3_DA_8821C) + /* 2 REG_DDMA_CH3CTRL_8821C */ #define BIT_DDMACH3_OWN_8821C BIT(31) #define BIT_DDMACH3_CHKSUM_EN_8821C BIT(29) @@ -3729,6 +4180,7 @@ #define BIT_GET_DDMACH3_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8821C) & BIT_MASK_DDMACH3_DLEN_8821C) + /* 2 REG_DDMA_CH4SA_8821C */ #define BIT_SHIFT_DDMACH4_SA_8821C 0 @@ -3737,6 +4189,7 @@ #define BIT_GET_DDMACH4_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8821C) & BIT_MASK_DDMACH4_SA_8821C) + /* 2 REG_DDMA_CH4DA_8821C */ #define BIT_SHIFT_DDMACH4_DA_8821C 0 @@ -3745,6 +4198,7 @@ #define BIT_GET_DDMACH4_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8821C) & BIT_MASK_DDMACH4_DA_8821C) + /* 2 REG_DDMA_CH4CTRL_8821C */ #define BIT_DDMACH4_OWN_8821C BIT(31) #define BIT_DDMACH4_CHKSUM_EN_8821C BIT(29) @@ -3760,6 +4214,7 @@ #define BIT_GET_DDMACH4_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8821C) & BIT_MASK_DDMACH4_DLEN_8821C) + /* 2 REG_DDMA_CH5SA_8821C */ #define BIT_SHIFT_DDMACH5_SA_8821C 0 @@ -3768,6 +4223,7 @@ #define BIT_GET_DDMACH5_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8821C) & BIT_MASK_DDMACH5_SA_8821C) + /* 2 REG_DDMA_CH5DA_8821C */ #define BIT_SHIFT_DDMACH5_DA_8821C 0 @@ -3776,7 +4232,8 @@ #define BIT_GET_DDMACH5_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8821C) & BIT_MASK_DDMACH5_DA_8821C) -/* 2 REG_REG_DDMA_CH5CTRL_8821C */ + +/* 2 REG_DDMA_CH5CTRL_8821C */ #define BIT_DDMACH5_OWN_8821C BIT(31) #define BIT_DDMACH5_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH5_DA_W_DISABLE_8821C BIT(28) @@ -3791,6 +4248,7 @@ #define BIT_GET_DDMACH5_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8821C) & BIT_MASK_DDMACH5_DLEN_8821C) + /* 2 REG_DDMA_INT_MSK_8821C */ #define BIT_DDMACH5_MSK_8821C BIT(5) #define BIT_DDMACH4_MSK_8821C BIT(4) @@ -3815,6 +4273,7 @@ #define BIT_GET_IDDMA0_CHKSUM_8821C(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8821C) & BIT_MASK_IDDMA0_CHKSUM_8821C) + /* 2 REG_DDMA_MONITOR_8821C */ #define BIT_IDDMA0_PERMU_UNDERFLOW_8821C BIT(14) #define BIT_IDDMA0_FIFO_UNDERFLOW_8821C BIT(13) @@ -3836,6 +4295,7 @@ #define BIT_PCIE_MAX_RXDMA_8821C(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA_8821C) << BIT_SHIFT_PCIE_MAX_RXDMA_8821C) #define BIT_GET_PCIE_MAX_RXDMA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8821C) & BIT_MASK_PCIE_MAX_RXDMA_8821C) + #define BIT_MULRW_8821C BIT(27) #define BIT_SHIFT_PCIE_MAX_TXDMA_8821C 24 @@ -3843,6 +4303,7 @@ #define BIT_PCIE_MAX_TXDMA_8821C(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA_8821C) << BIT_SHIFT_PCIE_MAX_TXDMA_8821C) #define BIT_GET_PCIE_MAX_TXDMA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8821C) & BIT_MASK_PCIE_MAX_TXDMA_8821C) + #define BIT_EN_CPL_TIMEOUT_PS_8821C BIT(22) #define BIT_REG_TXDMA_FAIL_PS_8821C BIT(21) #define BIT_PCIE_RST_TRXDMA_INTF_8821C BIT(20) @@ -3875,30 +4336,35 @@ #define BIT_GET_TXTTIMER_MATCH_NUM_8821C(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C) + #define BIT_SHIFT_TXPKT_NUM_MATCH_8821C 24 #define BIT_MASK_TXPKT_NUM_MATCH_8821C 0xf #define BIT_TXPKT_NUM_MATCH_8821C(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8821C) << BIT_SHIFT_TXPKT_NUM_MATCH_8821C) #define BIT_GET_TXPKT_NUM_MATCH_8821C(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8821C) & BIT_MASK_TXPKT_NUM_MATCH_8821C) + #define BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C 20 #define BIT_MASK_RXTTIMER_MATCH_NUM_8821C 0xf #define BIT_RXTTIMER_MATCH_NUM_8821C(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) #define BIT_GET_RXTTIMER_MATCH_NUM_8821C(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C) + #define BIT_SHIFT_RXPKT_NUM_MATCH_8821C 16 #define BIT_MASK_RXPKT_NUM_MATCH_8821C 0xf #define BIT_RXPKT_NUM_MATCH_8821C(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8821C) << BIT_SHIFT_RXPKT_NUM_MATCH_8821C) #define BIT_GET_RXPKT_NUM_MATCH_8821C(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8821C) & BIT_MASK_RXPKT_NUM_MATCH_8821C) + #define BIT_SHIFT_MIGRATE_TIMER_8821C 0 #define BIT_MASK_MIGRATE_TIMER_8821C 0xffff #define BIT_MIGRATE_TIMER_8821C(x) (((x) & BIT_MASK_MIGRATE_TIMER_8821C) << BIT_SHIFT_MIGRATE_TIMER_8821C) #define BIT_GET_MIGRATE_TIMER_8821C(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8821C) & BIT_MASK_MIGRATE_TIMER_8821C) + /* 2 REG_BCNQ_TXBD_DESA_8821C */ #define BIT_SHIFT_BCNQ_TXBD_DESA_8821C 0 @@ -3907,6 +4373,7 @@ #define BIT_GET_BCNQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8821C) & BIT_MASK_BCNQ_TXBD_DESA_8821C) + /* 2 REG_MGQ_TXBD_DESA_8821C */ #define BIT_SHIFT_MGQ_TXBD_DESA_8821C 0 @@ -3915,6 +4382,7 @@ #define BIT_GET_MGQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8821C) & BIT_MASK_MGQ_TXBD_DESA_8821C) + /* 2 REG_VOQ_TXBD_DESA_8821C */ #define BIT_SHIFT_VOQ_TXBD_DESA_8821C 0 @@ -3923,6 +4391,7 @@ #define BIT_GET_VOQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8821C) & BIT_MASK_VOQ_TXBD_DESA_8821C) + /* 2 REG_VIQ_TXBD_DESA_8821C */ #define BIT_SHIFT_VIQ_TXBD_DESA_8821C 0 @@ -3931,6 +4400,7 @@ #define BIT_GET_VIQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8821C) & BIT_MASK_VIQ_TXBD_DESA_8821C) + /* 2 REG_BEQ_TXBD_DESA_8821C */ #define BIT_SHIFT_BEQ_TXBD_DESA_8821C 0 @@ -3939,6 +4409,7 @@ #define BIT_GET_BEQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8821C) & BIT_MASK_BEQ_TXBD_DESA_8821C) + /* 2 REG_BKQ_TXBD_DESA_8821C */ #define BIT_SHIFT_BKQ_TXBD_DESA_8821C 0 @@ -3947,6 +4418,7 @@ #define BIT_GET_BKQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8821C) & BIT_MASK_BKQ_TXBD_DESA_8821C) + /* 2 REG_RXQ_RXBD_DESA_8821C */ #define BIT_SHIFT_RXQ_RXBD_DESA_8821C 0 @@ -3955,6 +4427,7 @@ #define BIT_GET_RXQ_RXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8821C) & BIT_MASK_RXQ_RXBD_DESA_8821C) + /* 2 REG_HI0Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI0Q_TXBD_DESA_8821C 0 @@ -3963,6 +4436,7 @@ #define BIT_GET_HI0Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8821C) & BIT_MASK_HI0Q_TXBD_DESA_8821C) + /* 2 REG_HI1Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI1Q_TXBD_DESA_8821C 0 @@ -3971,6 +4445,7 @@ #define BIT_GET_HI1Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8821C) & BIT_MASK_HI1Q_TXBD_DESA_8821C) + /* 2 REG_HI2Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI2Q_TXBD_DESA_8821C 0 @@ -3979,6 +4454,7 @@ #define BIT_GET_HI2Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8821C) & BIT_MASK_HI2Q_TXBD_DESA_8821C) + /* 2 REG_HI3Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI3Q_TXBD_DESA_8821C 0 @@ -3987,6 +4463,7 @@ #define BIT_GET_HI3Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8821C) & BIT_MASK_HI3Q_TXBD_DESA_8821C) + /* 2 REG_HI4Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI4Q_TXBD_DESA_8821C 0 @@ -3995,6 +4472,7 @@ #define BIT_GET_HI4Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8821C) & BIT_MASK_HI4Q_TXBD_DESA_8821C) + /* 2 REG_HI5Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI5Q_TXBD_DESA_8821C 0 @@ -4003,6 +4481,7 @@ #define BIT_GET_HI5Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8821C) & BIT_MASK_HI5Q_TXBD_DESA_8821C) + /* 2 REG_HI6Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI6Q_TXBD_DESA_8821C 0 @@ -4011,6 +4490,7 @@ #define BIT_GET_HI6Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8821C) & BIT_MASK_HI6Q_TXBD_DESA_8821C) + /* 2 REG_HI7Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI7Q_TXBD_DESA_8821C 0 @@ -4019,6 +4499,7 @@ #define BIT_GET_HI7Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8821C) & BIT_MASK_HI7Q_TXBD_DESA_8821C) + /* 2 REG_MGQ_TXBD_NUM_8821C */ #define BIT_PCIE_MGQ_FLAG_8821C BIT(14) @@ -4028,12 +4509,14 @@ #define BIT_GET_MGQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8821C) & BIT_MASK_MGQ_DESC_MODE_8821C) + #define BIT_SHIFT_MGQ_DESC_NUM_8821C 0 #define BIT_MASK_MGQ_DESC_NUM_8821C 0xfff #define BIT_MGQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8821C) << BIT_SHIFT_MGQ_DESC_NUM_8821C) #define BIT_GET_MGQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8821C) & BIT_MASK_MGQ_DESC_NUM_8821C) + /* 2 REG_RX_RXBD_NUM_8821C */ #define BIT_SYS_32_64_8821C BIT(15) @@ -4042,6 +4525,7 @@ #define BIT_BCNQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8821C) << BIT_SHIFT_BCNQ_DESC_MODE_8821C) #define BIT_GET_BCNQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8821C) & BIT_MASK_BCNQ_DESC_MODE_8821C) + #define BIT_PCIE_BCNQ_FLAG_8821C BIT(12) #define BIT_SHIFT_RXQ_DESC_NUM_8821C 0 @@ -4050,6 +4534,7 @@ #define BIT_GET_RXQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8821C) & BIT_MASK_RXQ_DESC_NUM_8821C) + /* 2 REG_VOQ_TXBD_NUM_8821C */ #define BIT_PCIE_VOQ_FLAG_8821C BIT(14) @@ -4059,12 +4544,14 @@ #define BIT_GET_VOQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8821C) & BIT_MASK_VOQ_DESC_MODE_8821C) + #define BIT_SHIFT_VOQ_DESC_NUM_8821C 0 #define BIT_MASK_VOQ_DESC_NUM_8821C 0xfff #define BIT_VOQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8821C) << BIT_SHIFT_VOQ_DESC_NUM_8821C) #define BIT_GET_VOQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8821C) & BIT_MASK_VOQ_DESC_NUM_8821C) + /* 2 REG_VIQ_TXBD_NUM_8821C */ #define BIT_PCIE_VIQ_FLAG_8821C BIT(14) @@ -4074,12 +4561,14 @@ #define BIT_GET_VIQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8821C) & BIT_MASK_VIQ_DESC_MODE_8821C) + #define BIT_SHIFT_VIQ_DESC_NUM_8821C 0 #define BIT_MASK_VIQ_DESC_NUM_8821C 0xfff #define BIT_VIQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8821C) << BIT_SHIFT_VIQ_DESC_NUM_8821C) #define BIT_GET_VIQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8821C) & BIT_MASK_VIQ_DESC_NUM_8821C) + /* 2 REG_BEQ_TXBD_NUM_8821C */ #define BIT_PCIE_BEQ_FLAG_8821C BIT(14) @@ -4089,12 +4578,14 @@ #define BIT_GET_BEQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8821C) & BIT_MASK_BEQ_DESC_MODE_8821C) + #define BIT_SHIFT_BEQ_DESC_NUM_8821C 0 #define BIT_MASK_BEQ_DESC_NUM_8821C 0xfff #define BIT_BEQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8821C) << BIT_SHIFT_BEQ_DESC_NUM_8821C) #define BIT_GET_BEQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8821C) & BIT_MASK_BEQ_DESC_NUM_8821C) + /* 2 REG_BKQ_TXBD_NUM_8821C */ #define BIT_PCIE_BKQ_FLAG_8821C BIT(14) @@ -4104,12 +4595,14 @@ #define BIT_GET_BKQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8821C) & BIT_MASK_BKQ_DESC_MODE_8821C) + #define BIT_SHIFT_BKQ_DESC_NUM_8821C 0 #define BIT_MASK_BKQ_DESC_NUM_8821C 0xfff #define BIT_BKQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8821C) << BIT_SHIFT_BKQ_DESC_NUM_8821C) #define BIT_GET_BKQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8821C) & BIT_MASK_BKQ_DESC_NUM_8821C) + /* 2 REG_HI0Q_TXBD_NUM_8821C */ #define BIT_HI0Q_FLAG_8821C BIT(14) @@ -4119,12 +4612,14 @@ #define BIT_GET_HI0Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8821C) & BIT_MASK_HI0Q_DESC_MODE_8821C) + #define BIT_SHIFT_HI0Q_DESC_NUM_8821C 0 #define BIT_MASK_HI0Q_DESC_NUM_8821C 0xfff #define BIT_HI0Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8821C) << BIT_SHIFT_HI0Q_DESC_NUM_8821C) #define BIT_GET_HI0Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8821C) & BIT_MASK_HI0Q_DESC_NUM_8821C) + /* 2 REG_HI1Q_TXBD_NUM_8821C */ #define BIT_HI1Q_FLAG_8821C BIT(14) @@ -4134,12 +4629,14 @@ #define BIT_GET_HI1Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8821C) & BIT_MASK_HI1Q_DESC_MODE_8821C) + #define BIT_SHIFT_HI1Q_DESC_NUM_8821C 0 #define BIT_MASK_HI1Q_DESC_NUM_8821C 0xfff #define BIT_HI1Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8821C) << BIT_SHIFT_HI1Q_DESC_NUM_8821C) #define BIT_GET_HI1Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8821C) & BIT_MASK_HI1Q_DESC_NUM_8821C) + /* 2 REG_HI2Q_TXBD_NUM_8821C */ #define BIT_HI2Q_FLAG_8821C BIT(14) @@ -4149,12 +4646,14 @@ #define BIT_GET_HI2Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8821C) & BIT_MASK_HI2Q_DESC_MODE_8821C) + #define BIT_SHIFT_HI2Q_DESC_NUM_8821C 0 #define BIT_MASK_HI2Q_DESC_NUM_8821C 0xfff #define BIT_HI2Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8821C) << BIT_SHIFT_HI2Q_DESC_NUM_8821C) #define BIT_GET_HI2Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8821C) & BIT_MASK_HI2Q_DESC_NUM_8821C) + /* 2 REG_HI3Q_TXBD_NUM_8821C */ #define BIT_HI3Q_FLAG_8821C BIT(14) @@ -4164,12 +4663,14 @@ #define BIT_GET_HI3Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8821C) & BIT_MASK_HI3Q_DESC_MODE_8821C) + #define BIT_SHIFT_HI3Q_DESC_NUM_8821C 0 #define BIT_MASK_HI3Q_DESC_NUM_8821C 0xfff #define BIT_HI3Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8821C) << BIT_SHIFT_HI3Q_DESC_NUM_8821C) #define BIT_GET_HI3Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8821C) & BIT_MASK_HI3Q_DESC_NUM_8821C) + /* 2 REG_HI4Q_TXBD_NUM_8821C */ #define BIT_HI4Q_FLAG_8821C BIT(14) @@ -4179,12 +4680,14 @@ #define BIT_GET_HI4Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8821C) & BIT_MASK_HI4Q_DESC_MODE_8821C) + #define BIT_SHIFT_HI4Q_DESC_NUM_8821C 0 #define BIT_MASK_HI4Q_DESC_NUM_8821C 0xfff #define BIT_HI4Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8821C) << BIT_SHIFT_HI4Q_DESC_NUM_8821C) #define BIT_GET_HI4Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8821C) & BIT_MASK_HI4Q_DESC_NUM_8821C) + /* 2 REG_HI5Q_TXBD_NUM_8821C */ #define BIT_HI5Q_FLAG_8821C BIT(14) @@ -4194,12 +4697,14 @@ #define BIT_GET_HI5Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8821C) & BIT_MASK_HI5Q_DESC_MODE_8821C) + #define BIT_SHIFT_HI5Q_DESC_NUM_8821C 0 #define BIT_MASK_HI5Q_DESC_NUM_8821C 0xfff #define BIT_HI5Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8821C) << BIT_SHIFT_HI5Q_DESC_NUM_8821C) #define BIT_GET_HI5Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8821C) & BIT_MASK_HI5Q_DESC_NUM_8821C) + /* 2 REG_HI6Q_TXBD_NUM_8821C */ #define BIT_HI6Q_FLAG_8821C BIT(14) @@ -4209,12 +4714,14 @@ #define BIT_GET_HI6Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8821C) & BIT_MASK_HI6Q_DESC_MODE_8821C) + #define BIT_SHIFT_HI6Q_DESC_NUM_8821C 0 #define BIT_MASK_HI6Q_DESC_NUM_8821C 0xfff #define BIT_HI6Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8821C) << BIT_SHIFT_HI6Q_DESC_NUM_8821C) #define BIT_GET_HI6Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8821C) & BIT_MASK_HI6Q_DESC_NUM_8821C) + /* 2 REG_HI7Q_TXBD_NUM_8821C */ #define BIT_HI7Q_FLAG_8821C BIT(14) @@ -4224,12 +4731,14 @@ #define BIT_GET_HI7Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8821C) & BIT_MASK_HI7Q_DESC_MODE_8821C) + #define BIT_SHIFT_HI7Q_DESC_NUM_8821C 0 #define BIT_MASK_HI7Q_DESC_NUM_8821C 0xfff #define BIT_HI7Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8821C) << BIT_SHIFT_HI7Q_DESC_NUM_8821C) #define BIT_GET_HI7Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8821C) & BIT_MASK_HI7Q_DESC_NUM_8821C) + /* 2 REG_TSFTIMER_HCI_8821C */ #define BIT_SHIFT_TSFT2_HCI_8821C 16 @@ -4238,12 +4747,14 @@ #define BIT_GET_TSFT2_HCI_8821C(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8821C) & BIT_MASK_TSFT2_HCI_8821C) + #define BIT_SHIFT_TSFT1_HCI_8821C 0 #define BIT_MASK_TSFT1_HCI_8821C 0xffff #define BIT_TSFT1_HCI_8821C(x) (((x) & BIT_MASK_TSFT1_HCI_8821C) << BIT_SHIFT_TSFT1_HCI_8821C) #define BIT_GET_TSFT1_HCI_8821C(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8821C) & BIT_MASK_TSFT1_HCI_8821C) + /* 2 REG_BD_RWPTR_CLR_8821C */ #define BIT_CLR_HI7Q_HW_IDX_8821C BIT(29) #define BIT_CLR_HI6Q_HW_IDX_8821C BIT(28) @@ -4282,12 +4793,14 @@ #define BIT_GET_VOQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8821C) & BIT_MASK_VOQ_HW_IDX_8821C) + #define BIT_SHIFT_VOQ_HOST_IDX_8821C 0 #define BIT_MASK_VOQ_HOST_IDX_8821C 0xfff #define BIT_VOQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8821C) << BIT_SHIFT_VOQ_HOST_IDX_8821C) #define BIT_GET_VOQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8821C) & BIT_MASK_VOQ_HOST_IDX_8821C) + /* 2 REG_VIQ_TXBD_IDX_8821C */ #define BIT_SHIFT_VIQ_HW_IDX_8821C 16 @@ -4296,12 +4809,14 @@ #define BIT_GET_VIQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8821C) & BIT_MASK_VIQ_HW_IDX_8821C) + #define BIT_SHIFT_VIQ_HOST_IDX_8821C 0 #define BIT_MASK_VIQ_HOST_IDX_8821C 0xfff #define BIT_VIQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8821C) << BIT_SHIFT_VIQ_HOST_IDX_8821C) #define BIT_GET_VIQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8821C) & BIT_MASK_VIQ_HOST_IDX_8821C) + /* 2 REG_BEQ_TXBD_IDX_8821C */ #define BIT_SHIFT_BEQ_HW_IDX_8821C 16 @@ -4310,12 +4825,14 @@ #define BIT_GET_BEQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8821C) & BIT_MASK_BEQ_HW_IDX_8821C) + #define BIT_SHIFT_BEQ_HOST_IDX_8821C 0 #define BIT_MASK_BEQ_HOST_IDX_8821C 0xfff #define BIT_BEQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8821C) << BIT_SHIFT_BEQ_HOST_IDX_8821C) #define BIT_GET_BEQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8821C) & BIT_MASK_BEQ_HOST_IDX_8821C) + /* 2 REG_BKQ_TXBD_IDX_8821C */ #define BIT_SHIFT_BKQ_HW_IDX_8821C 16 @@ -4324,12 +4841,14 @@ #define BIT_GET_BKQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8821C) & BIT_MASK_BKQ_HW_IDX_8821C) + #define BIT_SHIFT_BKQ_HOST_IDX_8821C 0 #define BIT_MASK_BKQ_HOST_IDX_8821C 0xfff #define BIT_BKQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8821C) << BIT_SHIFT_BKQ_HOST_IDX_8821C) #define BIT_GET_BKQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8821C) & BIT_MASK_BKQ_HOST_IDX_8821C) + /* 2 REG_MGQ_TXBD_IDX_8821C */ #define BIT_SHIFT_MGQ_HW_IDX_8821C 16 @@ -4338,12 +4857,14 @@ #define BIT_GET_MGQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8821C) & BIT_MASK_MGQ_HW_IDX_8821C) + #define BIT_SHIFT_MGQ_HOST_IDX_8821C 0 #define BIT_MASK_MGQ_HOST_IDX_8821C 0xfff #define BIT_MGQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8821C) << BIT_SHIFT_MGQ_HOST_IDX_8821C) #define BIT_GET_MGQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8821C) & BIT_MASK_MGQ_HOST_IDX_8821C) + /* 2 REG_RXQ_RXBD_IDX_8821C */ #define BIT_SHIFT_RXQ_HW_IDX_8821C 16 @@ -4352,12 +4873,14 @@ #define BIT_GET_RXQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8821C) & BIT_MASK_RXQ_HW_IDX_8821C) + #define BIT_SHIFT_RXQ_HOST_IDX_8821C 0 #define BIT_MASK_RXQ_HOST_IDX_8821C 0xfff #define BIT_RXQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8821C) << BIT_SHIFT_RXQ_HOST_IDX_8821C) #define BIT_GET_RXQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8821C) & BIT_MASK_RXQ_HOST_IDX_8821C) + /* 2 REG_HI0Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI0Q_HW_IDX_8821C 16 @@ -4366,12 +4889,14 @@ #define BIT_GET_HI0Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8821C) & BIT_MASK_HI0Q_HW_IDX_8821C) + #define BIT_SHIFT_HI0Q_HOST_IDX_8821C 0 #define BIT_MASK_HI0Q_HOST_IDX_8821C 0xfff #define BIT_HI0Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8821C) << BIT_SHIFT_HI0Q_HOST_IDX_8821C) #define BIT_GET_HI0Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8821C) & BIT_MASK_HI0Q_HOST_IDX_8821C) + /* 2 REG_HI1Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI1Q_HW_IDX_8821C 16 @@ -4380,12 +4905,14 @@ #define BIT_GET_HI1Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8821C) & BIT_MASK_HI1Q_HW_IDX_8821C) + #define BIT_SHIFT_HI1Q_HOST_IDX_8821C 0 #define BIT_MASK_HI1Q_HOST_IDX_8821C 0xfff #define BIT_HI1Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8821C) << BIT_SHIFT_HI1Q_HOST_IDX_8821C) #define BIT_GET_HI1Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8821C) & BIT_MASK_HI1Q_HOST_IDX_8821C) + /* 2 REG_HI2Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI2Q_HW_IDX_8821C 16 @@ -4394,12 +4921,14 @@ #define BIT_GET_HI2Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8821C) & BIT_MASK_HI2Q_HW_IDX_8821C) + #define BIT_SHIFT_HI2Q_HOST_IDX_8821C 0 #define BIT_MASK_HI2Q_HOST_IDX_8821C 0xfff #define BIT_HI2Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8821C) << BIT_SHIFT_HI2Q_HOST_IDX_8821C) #define BIT_GET_HI2Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8821C) & BIT_MASK_HI2Q_HOST_IDX_8821C) + /* 2 REG_HI3Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI3Q_HW_IDX_8821C 16 @@ -4408,12 +4937,14 @@ #define BIT_GET_HI3Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8821C) & BIT_MASK_HI3Q_HW_IDX_8821C) + #define BIT_SHIFT_HI3Q_HOST_IDX_8821C 0 #define BIT_MASK_HI3Q_HOST_IDX_8821C 0xfff #define BIT_HI3Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8821C) << BIT_SHIFT_HI3Q_HOST_IDX_8821C) #define BIT_GET_HI3Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8821C) & BIT_MASK_HI3Q_HOST_IDX_8821C) + /* 2 REG_HI4Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI4Q_HW_IDX_8821C 16 @@ -4422,12 +4953,14 @@ #define BIT_GET_HI4Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8821C) & BIT_MASK_HI4Q_HW_IDX_8821C) + #define BIT_SHIFT_HI4Q_HOST_IDX_8821C 0 #define BIT_MASK_HI4Q_HOST_IDX_8821C 0xfff #define BIT_HI4Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8821C) << BIT_SHIFT_HI4Q_HOST_IDX_8821C) #define BIT_GET_HI4Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8821C) & BIT_MASK_HI4Q_HOST_IDX_8821C) + /* 2 REG_HI5Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI5Q_HW_IDX_8821C 16 @@ -4436,12 +4969,14 @@ #define BIT_GET_HI5Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8821C) & BIT_MASK_HI5Q_HW_IDX_8821C) + #define BIT_SHIFT_HI5Q_HOST_IDX_8821C 0 #define BIT_MASK_HI5Q_HOST_IDX_8821C 0xfff #define BIT_HI5Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8821C) << BIT_SHIFT_HI5Q_HOST_IDX_8821C) #define BIT_GET_HI5Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8821C) & BIT_MASK_HI5Q_HOST_IDX_8821C) + /* 2 REG_HI6Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI6Q_HW_IDX_8821C 16 @@ -4450,12 +4985,14 @@ #define BIT_GET_HI6Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8821C) & BIT_MASK_HI6Q_HW_IDX_8821C) + #define BIT_SHIFT_HI6Q_HOST_IDX_8821C 0 #define BIT_MASK_HI6Q_HOST_IDX_8821C 0xfff #define BIT_HI6Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8821C) << BIT_SHIFT_HI6Q_HOST_IDX_8821C) #define BIT_GET_HI6Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8821C) & BIT_MASK_HI6Q_HOST_IDX_8821C) + /* 2 REG_HI7Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI7Q_HW_IDX_8821C 16 @@ -4464,12 +5001,14 @@ #define BIT_GET_HI7Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8821C) & BIT_MASK_HI7Q_HW_IDX_8821C) + #define BIT_SHIFT_HI7Q_HOST_IDX_8821C 0 #define BIT_MASK_HI7Q_HOST_IDX_8821C 0xfff #define BIT_HI7Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8821C) << BIT_SHIFT_HI7Q_HOST_IDX_8821C) #define BIT_GET_HI7Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8821C) & BIT_MASK_HI7Q_HOST_IDX_8821C) + /* 2 REG_DBG_SEL_V1_8821C */ #define BIT_SHIFT_DBG_SEL_8821C 0 @@ -4478,6 +5017,7 @@ #define BIT_GET_DBG_SEL_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_8821C) & BIT_MASK_DBG_SEL_8821C) + /* 2 REG_PCIE_HRPWM1_V1_8821C */ #define BIT_SHIFT_PCIE_HRPWM_8821C 0 @@ -4486,6 +5026,7 @@ #define BIT_GET_PCIE_HRPWM_8821C(x) (((x) >> BIT_SHIFT_PCIE_HRPWM_8821C) & BIT_MASK_PCIE_HRPWM_8821C) + /* 2 REG_PCIE_HCPWM1_V1_8821C */ #define BIT_SHIFT_PCIE_HCPWM_8821C 0 @@ -4494,6 +5035,7 @@ #define BIT_GET_PCIE_HCPWM_8821C(x) (((x) >> BIT_SHIFT_PCIE_HCPWM_8821C) & BIT_MASK_PCIE_HCPWM_8821C) + /* 2 REG_PCIE_CTRL2_8821C */ #define BIT_DIS_TXDMA_PRE_8821C BIT(7) #define BIT_DIS_RXDMA_PRE_8821C BIT(6) @@ -4503,6 +5045,7 @@ #define BIT_HPS_CLKR_PCIE_8821C(x) (((x) & BIT_MASK_HPS_CLKR_PCIE_8821C) << BIT_SHIFT_HPS_CLKR_PCIE_8821C) #define BIT_GET_HPS_CLKR_PCIE_8821C(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8821C) & BIT_MASK_HPS_CLKR_PCIE_8821C) + #define BIT_PCIE_INT_8821C BIT(3) #define BIT_TXFLAG_EXIT_L1_EN_8821C BIT(2) #define BIT_EN_RXDMA_ALIGN_8821C BIT(1) @@ -4516,6 +5059,7 @@ #define BIT_GET_PCIE_HRPWM2_8821C(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2_8821C) & BIT_MASK_PCIE_HRPWM2_8821C) + /* 2 REG_PCIE_HCPWM2_V1_8821C */ #define BIT_SHIFT_PCIE_HCPWM2_8821C 0 @@ -4524,6 +5068,7 @@ #define BIT_GET_PCIE_HCPWM2_8821C(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2_8821C) & BIT_MASK_PCIE_HCPWM2_8821C) + /* 2 REG_PCIE_H2C_MSG_V1_8821C */ #define BIT_SHIFT_DRV2FW_INFO_8821C 0 @@ -4532,6 +5077,7 @@ #define BIT_GET_DRV2FW_INFO_8821C(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8821C) & BIT_MASK_DRV2FW_INFO_8821C) + /* 2 REG_PCIE_C2H_MSG_V1_8821C */ #define BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C 0 @@ -4540,6 +5086,7 @@ #define BIT_GET_HCI_PCIE_C2H_MSG_8821C(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C) + /* 2 REG_DBI_WDATA_V1_8821C */ #define BIT_SHIFT_DBI_WDATA_8821C 0 @@ -4548,6 +5095,7 @@ #define BIT_GET_DBI_WDATA_8821C(x) (((x) >> BIT_SHIFT_DBI_WDATA_8821C) & BIT_MASK_DBI_WDATA_8821C) + /* 2 REG_DBI_RDATA_V1_8821C */ #define BIT_SHIFT_DBI_RDATA_8821C 0 @@ -4556,6 +5104,7 @@ #define BIT_GET_DBI_RDATA_8821C(x) (((x) >> BIT_SHIFT_DBI_RDATA_8821C) & BIT_MASK_DBI_RDATA_8821C) + /* 2 REG_DBI_FLAG_V1_8821C */ #define BIT_EN_STUCK_DBG_8821C BIT(26) #define BIT_RX_STUCK_8821C BIT(25) @@ -4569,12 +5118,14 @@ #define BIT_GET_DBI_WREN_8821C(x) (((x) >> BIT_SHIFT_DBI_WREN_8821C) & BIT_MASK_DBI_WREN_8821C) + #define BIT_SHIFT_DBI_ADDR_8821C 0 #define BIT_MASK_DBI_ADDR_8821C 0xfff #define BIT_DBI_ADDR_8821C(x) (((x) & BIT_MASK_DBI_ADDR_8821C) << BIT_SHIFT_DBI_ADDR_8821C) #define BIT_GET_DBI_ADDR_8821C(x) (((x) >> BIT_SHIFT_DBI_ADDR_8821C) & BIT_MASK_DBI_ADDR_8821C) + /* 2 REG_MDIO_V1_8821C */ #define BIT_SHIFT_MDIO_RDATA_8821C 16 @@ -4583,12 +5134,14 @@ #define BIT_GET_MDIO_RDATA_8821C(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8821C) & BIT_MASK_MDIO_RDATA_8821C) + #define BIT_SHIFT_MDIO_WDATA_8821C 0 #define BIT_MASK_MDIO_WDATA_8821C 0xffff #define BIT_MDIO_WDATA_8821C(x) (((x) & BIT_MASK_MDIO_WDATA_8821C) << BIT_SHIFT_MDIO_WDATA_8821C) #define BIT_GET_MDIO_WDATA_8821C(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8821C) & BIT_MASK_MDIO_WDATA_8821C) + /* 2 REG_PCIE_MIX_CFG_8821C */ #define BIT_SHIFT_MDIO_PHY_ADDR_8821C 24 @@ -4597,11 +5150,13 @@ #define BIT_GET_MDIO_PHY_ADDR_8821C(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8821C) & BIT_MASK_MDIO_PHY_ADDR_8821C) + #define BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C 10 #define BIT_MASK_WATCH_DOG_RECORD_V1_8821C 0x3fff #define BIT_WATCH_DOG_RECORD_V1_8821C(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) #define BIT_GET_WATCH_DOG_RECORD_V1_8821C(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C) + #define BIT_R_IO_TIMEOUT_FLAG_V1_8821C BIT(9) #define BIT_EN_WATCH_DOG_8821C BIT(8) #define BIT_ECRC_EN_V1_8821C BIT(7) @@ -4614,6 +5169,7 @@ #define BIT_GET_MDIO_REG_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) & BIT_MASK_MDIO_REG_ADDR_V1_8821C) + /* 2 REG_HCI_MIX_CFG_8821C */ #define BIT_HOST_GEN2_SUPPORT_8821C BIT(20) @@ -4623,11 +5179,13 @@ #define BIT_GET_TXDMA_ERR_FLAG_8821C(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8821C) & BIT_MASK_TXDMA_ERR_FLAG_8821C) + #define BIT_SHIFT_EARLY_MODE_SEL_8821C 12 #define BIT_MASK_EARLY_MODE_SEL_8821C 0xf #define BIT_EARLY_MODE_SEL_8821C(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8821C) << BIT_SHIFT_EARLY_MODE_SEL_8821C) #define BIT_GET_EARLY_MODE_SEL_8821C(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8821C) & BIT_MASK_EARLY_MODE_SEL_8821C) + #define BIT_EPHY_RX50_EN_8821C BIT(11) #define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C 8 @@ -4635,6 +5193,7 @@ #define BIT_MSI_TIMEOUT_ID_V1_8821C(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) #define BIT_GET_MSI_TIMEOUT_ID_V1_8821C(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) + #define BIT_RADDR_RD_8821C BIT(7) #define BIT_EN_MUL_TAG_8821C BIT(6) #define BIT_EN_EARLY_MODE_8821C BIT(5) @@ -4652,18 +5211,21 @@ #define BIT_GET_STC_INT_FLAG_8821C(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8821C) & BIT_MASK_STC_INT_FLAG_8821C) + #define BIT_SHIFT_STC_INT_IDX_8821C 8 #define BIT_MASK_STC_INT_IDX_8821C 0x7 #define BIT_STC_INT_IDX_8821C(x) (((x) & BIT_MASK_STC_INT_IDX_8821C) << BIT_SHIFT_STC_INT_IDX_8821C) #define BIT_GET_STC_INT_IDX_8821C(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8821C) & BIT_MASK_STC_INT_IDX_8821C) + #define BIT_SHIFT_STC_INT_REALTIME_CS_8821C 0 #define BIT_MASK_STC_INT_REALTIME_CS_8821C 0x3f #define BIT_STC_INT_REALTIME_CS_8821C(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8821C) << BIT_SHIFT_STC_INT_REALTIME_CS_8821C) #define BIT_GET_STC_INT_REALTIME_CS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8821C) & BIT_MASK_STC_INT_REALTIME_CS_8821C) + /* 2 REG_ST_INT_CFG_8821C(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */ #define BIT_STC_INT_GRP_EN_8821C BIT(31) @@ -4673,12 +5235,14 @@ #define BIT_GET_STC_INT_EXPECT_LS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8821C) & BIT_MASK_STC_INT_EXPECT_LS_8821C) + #define BIT_SHIFT_STC_INT_EXPECT_CS_8821C 0 #define BIT_MASK_STC_INT_EXPECT_CS_8821C 0x3f #define BIT_STC_INT_EXPECT_CS_8821C(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8821C) << BIT_SHIFT_STC_INT_EXPECT_CS_8821C) #define BIT_GET_STC_INT_EXPECT_CS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8821C) & BIT_MASK_STC_INT_EXPECT_CS_8821C) + /* 2 REG_CMU_DLY_CTRL_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */ #define BIT_CMU_DLY_EN_8821C BIT(31) #define BIT_CMU_DLY_MODE_8821C BIT(30) @@ -4689,6 +5253,7 @@ #define BIT_GET_CMU_DLY_PRE_DIV_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) & BIT_MASK_CMU_DLY_PRE_DIV_8821C) + /* 2 REG_CMU_DLY_CFG_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ #define BIT_SHIFT_CMU_DLY_LTR_A2I_8821C 24 @@ -4697,24 +5262,28 @@ #define BIT_GET_CMU_DLY_LTR_A2I_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) & BIT_MASK_CMU_DLY_LTR_A2I_8821C) + #define BIT_SHIFT_CMU_DLY_LTR_I2A_8821C 16 #define BIT_MASK_CMU_DLY_LTR_I2A_8821C 0xff #define BIT_CMU_DLY_LTR_I2A_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8821C) << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) #define BIT_GET_CMU_DLY_LTR_I2A_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) & BIT_MASK_CMU_DLY_LTR_I2A_8821C) + #define BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C 8 #define BIT_MASK_CMU_DLY_LTR_IDLE_8821C 0xff #define BIT_CMU_DLY_LTR_IDLE_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) #define BIT_GET_CMU_DLY_LTR_IDLE_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C) + #define BIT_SHIFT_CMU_DLY_LTR_ACT_8821C 0 #define BIT_MASK_CMU_DLY_LTR_ACT_8821C 0xff #define BIT_CMU_DLY_LTR_ACT_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8821C) << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) #define BIT_GET_CMU_DLY_LTR_ACT_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) & BIT_MASK_CMU_DLY_LTR_ACT_8821C) + /* 2 REG_H2CQ_TXBD_DESA_8821C */ #define BIT_SHIFT_H2CQ_TXBD_DESA_8821C 0 @@ -4723,6 +5292,7 @@ #define BIT_GET_H2CQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8821C) & BIT_MASK_H2CQ_TXBD_DESA_8821C) + /* 2 REG_H2CQ_TXBD_NUM_8821C */ #define BIT_PCIE_H2CQ_FLAG_8821C BIT(14) @@ -4732,12 +5302,14 @@ #define BIT_GET_H2CQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8821C) & BIT_MASK_H2CQ_DESC_MODE_8821C) + #define BIT_SHIFT_H2CQ_DESC_NUM_8821C 0 #define BIT_MASK_H2CQ_DESC_NUM_8821C 0xfff #define BIT_H2CQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8821C) << BIT_SHIFT_H2CQ_DESC_NUM_8821C) #define BIT_GET_H2CQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8821C) & BIT_MASK_H2CQ_DESC_NUM_8821C) + /* 2 REG_H2CQ_TXBD_IDX_8821C */ #define BIT_SHIFT_H2CQ_HW_IDX_8821C 16 @@ -4746,12 +5318,14 @@ #define BIT_GET_H2CQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8821C) & BIT_MASK_H2CQ_HW_IDX_8821C) + #define BIT_SHIFT_H2CQ_HOST_IDX_8821C 0 #define BIT_MASK_H2CQ_HOST_IDX_8821C 0xfff #define BIT_H2CQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8821C) << BIT_SHIFT_H2CQ_HOST_IDX_8821C) #define BIT_GET_H2CQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8821C) & BIT_MASK_H2CQ_HOST_IDX_8821C) + /* 2 REG_H2CQ_CSR_8821C[31:0] (H2CQ CONTROL AND STATUS) */ #define BIT_H2CQ_FULL_8821C BIT(31) #define BIT_CLR_H2CQ_HOST_IDX_8821C BIT(16) @@ -4765,11 +5339,13 @@ #define BIT_GET_QUEUEMACID_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) & BIT_MASK_QUEUEMACID_Q0_V1_8821C) + #define BIT_SHIFT_QUEUEAC_Q0_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q0_V1_8821C 0x3 #define BIT_QUEUEAC_Q0_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8821C) << BIT_SHIFT_QUEUEAC_Q0_V1_8821C) #define BIT_GET_QUEUEAC_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8821C) & BIT_MASK_QUEUEAC_Q0_V1_8821C) + #define BIT_TIDEMPTY_Q0_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q0_V2_8821C 11 @@ -4778,12 +5354,14 @@ #define BIT_GET_TAIL_PKT_Q0_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) & BIT_MASK_TAIL_PKT_Q0_V2_8821C) + #define BIT_SHIFT_HEAD_PKT_Q0_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q0_V1_8821C 0x7ff #define BIT_HEAD_PKT_Q0_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) #define BIT_GET_HEAD_PKT_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) & BIT_MASK_HEAD_PKT_Q0_V1_8821C) + /* 2 REG_Q1_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q1_V1_8821C 25 @@ -4792,11 +5370,13 @@ #define BIT_GET_QUEUEMACID_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) & BIT_MASK_QUEUEMACID_Q1_V1_8821C) + #define BIT_SHIFT_QUEUEAC_Q1_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q1_V1_8821C 0x3 #define BIT_QUEUEAC_Q1_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8821C) << BIT_SHIFT_QUEUEAC_Q1_V1_8821C) #define BIT_GET_QUEUEAC_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8821C) & BIT_MASK_QUEUEAC_Q1_V1_8821C) + #define BIT_TIDEMPTY_Q1_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q1_V2_8821C 11 @@ -4805,12 +5385,14 @@ #define BIT_GET_TAIL_PKT_Q1_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) & BIT_MASK_TAIL_PKT_Q1_V2_8821C) + #define BIT_SHIFT_HEAD_PKT_Q1_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q1_V1_8821C 0x7ff #define BIT_HEAD_PKT_Q1_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) #define BIT_GET_HEAD_PKT_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) & BIT_MASK_HEAD_PKT_Q1_V1_8821C) + /* 2 REG_Q2_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q2_V1_8821C 25 @@ -4819,11 +5401,13 @@ #define BIT_GET_QUEUEMACID_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) & BIT_MASK_QUEUEMACID_Q2_V1_8821C) + #define BIT_SHIFT_QUEUEAC_Q2_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q2_V1_8821C 0x3 #define BIT_QUEUEAC_Q2_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8821C) << BIT_SHIFT_QUEUEAC_Q2_V1_8821C) #define BIT_GET_QUEUEAC_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8821C) & BIT_MASK_QUEUEAC_Q2_V1_8821C) + #define BIT_TIDEMPTY_Q2_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q2_V2_8821C 11 @@ -4832,12 +5416,14 @@ #define BIT_GET_TAIL_PKT_Q2_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) & BIT_MASK_TAIL_PKT_Q2_V2_8821C) + #define BIT_SHIFT_HEAD_PKT_Q2_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q2_V1_8821C 0x7ff #define BIT_HEAD_PKT_Q2_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) #define BIT_GET_HEAD_PKT_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) & BIT_MASK_HEAD_PKT_Q2_V1_8821C) + /* 2 REG_Q3_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q3_V1_8821C 25 @@ -4846,11 +5432,13 @@ #define BIT_GET_QUEUEMACID_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) & BIT_MASK_QUEUEMACID_Q3_V1_8821C) + #define BIT_SHIFT_QUEUEAC_Q3_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q3_V1_8821C 0x3 #define BIT_QUEUEAC_Q3_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8821C) << BIT_SHIFT_QUEUEAC_Q3_V1_8821C) #define BIT_GET_QUEUEAC_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8821C) & BIT_MASK_QUEUEAC_Q3_V1_8821C) + #define BIT_TIDEMPTY_Q3_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q3_V2_8821C 11 @@ -4859,12 +5447,14 @@ #define BIT_GET_TAIL_PKT_Q3_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) & BIT_MASK_TAIL_PKT_Q3_V2_8821C) + #define BIT_SHIFT_HEAD_PKT_Q3_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q3_V1_8821C 0x7ff #define BIT_HEAD_PKT_Q3_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) #define BIT_GET_HEAD_PKT_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) & BIT_MASK_HEAD_PKT_Q3_V1_8821C) + /* 2 REG_MGQ_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C 25 @@ -4873,11 +5463,13 @@ #define BIT_GET_QUEUEMACID_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C) + #define BIT_SHIFT_QUEUEAC_MGQ_V1_8821C 23 #define BIT_MASK_QUEUEAC_MGQ_V1_8821C 0x3 #define BIT_QUEUEAC_MGQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8821C) << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) #define BIT_GET_QUEUEAC_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) & BIT_MASK_QUEUEAC_MGQ_V1_8821C) + #define BIT_TIDEMPTY_MGQ_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C 11 @@ -4886,12 +5478,14 @@ #define BIT_GET_TAIL_PKT_MGQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C) + #define BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C 0 #define BIT_MASK_HEAD_PKT_MGQ_V1_8821C 0x7ff #define BIT_HEAD_PKT_MGQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) #define BIT_GET_HEAD_PKT_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C) + /* 2 REG_HIQ_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C 25 @@ -4900,11 +5494,13 @@ #define BIT_GET_QUEUEMACID_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C) + #define BIT_SHIFT_QUEUEAC_HIQ_V1_8821C 23 #define BIT_MASK_QUEUEAC_HIQ_V1_8821C 0x3 #define BIT_QUEUEAC_HIQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8821C) << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) #define BIT_GET_QUEUEAC_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) & BIT_MASK_QUEUEAC_HIQ_V1_8821C) + #define BIT_TIDEMPTY_HIQ_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C 11 @@ -4913,12 +5509,14 @@ #define BIT_GET_TAIL_PKT_HIQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C) + #define BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C 0 #define BIT_MASK_HEAD_PKT_HIQ_V1_8821C 0x7ff #define BIT_HEAD_PKT_HIQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) #define BIT_GET_HEAD_PKT_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C) + /* 2 REG_BCNQ_INFO_8821C */ #define BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C 0 @@ -4927,6 +5525,7 @@ #define BIT_GET_BCNQ_HEAD_PG_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C) + /* 2 REG_TXPKT_EMPTY_8821C */ #define BIT_BCNQ_EMPTY_8821C BIT(11) #define BIT_HQQ_EMPTY_8821C BIT(10) @@ -4953,6 +5552,7 @@ #define BIT_GET_FW_FREE_TAIL_V1_8821C(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8821C) & BIT_MASK_FW_FREE_TAIL_V1_8821C) + /* 2 REG_FWHW_TXQ_CTRL_8821C */ #define BIT_RTS_LIMIT_IN_OFDM_8821C BIT(23) #define BIT_EN_BCNQ_DL_8821C BIT(22) @@ -4964,6 +5564,7 @@ #define BIT_EN_QUEUE_RPT_8821C(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8821C) << BIT_SHIFT_EN_QUEUE_RPT_8821C) #define BIT_GET_EN_QUEUE_RPT_8821C(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8821C) & BIT_MASK_EN_QUEUE_RPT_8821C) + #define BIT_EN_RTY_BK_8821C BIT(7) #define BIT_EN_USE_INI_RAT_8821C BIT(6) #define BIT_EN_RTS_NAV_BK_8821C BIT(5) @@ -4982,6 +5583,7 @@ #define BIT_GET__R_DATA_FALLBACK_SEL_8821C(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C) + /* 2 REG_BCNQ_BDNY_V1_8821C */ #define BIT_SHIFT_BCNQ_PGBNDY_V1_8821C 0 @@ -4990,6 +5592,7 @@ #define BIT_GET_BCNQ_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) & BIT_MASK_BCNQ_PGBNDY_V1_8821C) + /* 2 REG_LIFETIME_EN_8821C */ #define BIT_BT_INT_CPU_8821C BIT(7) #define BIT_BT_INT_PTA_8821C BIT(6) @@ -5009,12 +5612,14 @@ #define BIT_GET_SPEC_SIFS_OFDM_PTCL_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) + #define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C 0 #define BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C 0xff #define BIT_SPEC_SIFS_CCK_PTCL_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) #define BIT_GET_SPEC_SIFS_CCK_PTCL_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) + /* 2 REG_RETRY_LIMIT_8821C */ #define BIT_SHIFT_SRL_8821C 8 @@ -5023,12 +5628,14 @@ #define BIT_GET_SRL_8821C(x) (((x) >> BIT_SHIFT_SRL_8821C) & BIT_MASK_SRL_8821C) + #define BIT_SHIFT_LRL_8821C 0 #define BIT_MASK_LRL_8821C 0x3f #define BIT_LRL_8821C(x) (((x) & BIT_MASK_LRL_8821C) << BIT_SHIFT_LRL_8821C) #define BIT_GET_LRL_8821C(x) (((x) >> BIT_SHIFT_LRL_8821C) & BIT_MASK_LRL_8821C) + /* 2 REG_TXBF_CTRL_8821C */ #define BIT_R_ENABLE_NDPA_8821C BIT(31) #define BIT_USE_NDPA_PARAMETER_8821C BIT(30) @@ -5043,6 +5650,7 @@ #define BIT_R_TXBF1_AID_8821C(x) (((x) & BIT_MASK_R_TXBF1_AID_8821C) << BIT_SHIFT_R_TXBF1_AID_8821C) #define BIT_GET_R_TXBF1_AID_8821C(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8821C) & BIT_MASK_R_TXBF1_AID_8821C) + #define BIT_DIS_NDP_BFEN_8821C BIT(15) #define BIT_R_TXBCN_NOBLOCK_NDP_8821C BIT(14) #define BIT_R_TXBF0_80M_8821C BIT(11) @@ -5055,6 +5663,7 @@ #define BIT_GET_R_TXBF0_AID_8821C(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8821C) & BIT_MASK_R_TXBF0_AID_8821C) + /* 2 REG_DARFRC_8821C */ #define BIT_SHIFT_DARF_RC8_8821C (56 & CPU_OPT_WIDTH) @@ -5063,48 +5672,56 @@ #define BIT_GET_DARF_RC8_8821C(x) (((x) >> BIT_SHIFT_DARF_RC8_8821C) & BIT_MASK_DARF_RC8_8821C) + #define BIT_SHIFT_DARF_RC7_8821C (48 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC7_8821C 0x1f #define BIT_DARF_RC7_8821C(x) (((x) & BIT_MASK_DARF_RC7_8821C) << BIT_SHIFT_DARF_RC7_8821C) #define BIT_GET_DARF_RC7_8821C(x) (((x) >> BIT_SHIFT_DARF_RC7_8821C) & BIT_MASK_DARF_RC7_8821C) + #define BIT_SHIFT_DARF_RC6_8821C (40 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC6_8821C 0x1f #define BIT_DARF_RC6_8821C(x) (((x) & BIT_MASK_DARF_RC6_8821C) << BIT_SHIFT_DARF_RC6_8821C) #define BIT_GET_DARF_RC6_8821C(x) (((x) >> BIT_SHIFT_DARF_RC6_8821C) & BIT_MASK_DARF_RC6_8821C) + #define BIT_SHIFT_DARF_RC5_8821C (32 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC5_8821C 0x1f #define BIT_DARF_RC5_8821C(x) (((x) & BIT_MASK_DARF_RC5_8821C) << BIT_SHIFT_DARF_RC5_8821C) #define BIT_GET_DARF_RC5_8821C(x) (((x) >> BIT_SHIFT_DARF_RC5_8821C) & BIT_MASK_DARF_RC5_8821C) + #define BIT_SHIFT_DARF_RC4_8821C 24 #define BIT_MASK_DARF_RC4_8821C 0x1f #define BIT_DARF_RC4_8821C(x) (((x) & BIT_MASK_DARF_RC4_8821C) << BIT_SHIFT_DARF_RC4_8821C) #define BIT_GET_DARF_RC4_8821C(x) (((x) >> BIT_SHIFT_DARF_RC4_8821C) & BIT_MASK_DARF_RC4_8821C) + #define BIT_SHIFT_DARF_RC3_8821C 16 #define BIT_MASK_DARF_RC3_8821C 0x1f #define BIT_DARF_RC3_8821C(x) (((x) & BIT_MASK_DARF_RC3_8821C) << BIT_SHIFT_DARF_RC3_8821C) #define BIT_GET_DARF_RC3_8821C(x) (((x) >> BIT_SHIFT_DARF_RC3_8821C) & BIT_MASK_DARF_RC3_8821C) + #define BIT_SHIFT_DARF_RC2_8821C 8 #define BIT_MASK_DARF_RC2_8821C 0x1f #define BIT_DARF_RC2_8821C(x) (((x) & BIT_MASK_DARF_RC2_8821C) << BIT_SHIFT_DARF_RC2_8821C) #define BIT_GET_DARF_RC2_8821C(x) (((x) >> BIT_SHIFT_DARF_RC2_8821C) & BIT_MASK_DARF_RC2_8821C) + #define BIT_SHIFT_DARF_RC1_8821C 0 #define BIT_MASK_DARF_RC1_8821C 0x1f #define BIT_DARF_RC1_8821C(x) (((x) & BIT_MASK_DARF_RC1_8821C) << BIT_SHIFT_DARF_RC1_8821C) #define BIT_GET_DARF_RC1_8821C(x) (((x) >> BIT_SHIFT_DARF_RC1_8821C) & BIT_MASK_DARF_RC1_8821C) + /* 2 REG_RARFRC_8821C */ #define BIT_SHIFT_RARF_RC8_8821C (56 & CPU_OPT_WIDTH) @@ -5113,48 +5730,56 @@ #define BIT_GET_RARF_RC8_8821C(x) (((x) >> BIT_SHIFT_RARF_RC8_8821C) & BIT_MASK_RARF_RC8_8821C) + #define BIT_SHIFT_RARF_RC7_8821C (48 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC7_8821C 0x1f #define BIT_RARF_RC7_8821C(x) (((x) & BIT_MASK_RARF_RC7_8821C) << BIT_SHIFT_RARF_RC7_8821C) #define BIT_GET_RARF_RC7_8821C(x) (((x) >> BIT_SHIFT_RARF_RC7_8821C) & BIT_MASK_RARF_RC7_8821C) + #define BIT_SHIFT_RARF_RC6_8821C (40 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC6_8821C 0x1f #define BIT_RARF_RC6_8821C(x) (((x) & BIT_MASK_RARF_RC6_8821C) << BIT_SHIFT_RARF_RC6_8821C) #define BIT_GET_RARF_RC6_8821C(x) (((x) >> BIT_SHIFT_RARF_RC6_8821C) & BIT_MASK_RARF_RC6_8821C) + #define BIT_SHIFT_RARF_RC5_8821C (32 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC5_8821C 0x1f #define BIT_RARF_RC5_8821C(x) (((x) & BIT_MASK_RARF_RC5_8821C) << BIT_SHIFT_RARF_RC5_8821C) #define BIT_GET_RARF_RC5_8821C(x) (((x) >> BIT_SHIFT_RARF_RC5_8821C) & BIT_MASK_RARF_RC5_8821C) + #define BIT_SHIFT_RARF_RC4_8821C 24 #define BIT_MASK_RARF_RC4_8821C 0x1f #define BIT_RARF_RC4_8821C(x) (((x) & BIT_MASK_RARF_RC4_8821C) << BIT_SHIFT_RARF_RC4_8821C) #define BIT_GET_RARF_RC4_8821C(x) (((x) >> BIT_SHIFT_RARF_RC4_8821C) & BIT_MASK_RARF_RC4_8821C) + #define BIT_SHIFT_RARF_RC3_8821C 16 #define BIT_MASK_RARF_RC3_8821C 0x1f #define BIT_RARF_RC3_8821C(x) (((x) & BIT_MASK_RARF_RC3_8821C) << BIT_SHIFT_RARF_RC3_8821C) #define BIT_GET_RARF_RC3_8821C(x) (((x) >> BIT_SHIFT_RARF_RC3_8821C) & BIT_MASK_RARF_RC3_8821C) + #define BIT_SHIFT_RARF_RC2_8821C 8 #define BIT_MASK_RARF_RC2_8821C 0x1f #define BIT_RARF_RC2_8821C(x) (((x) & BIT_MASK_RARF_RC2_8821C) << BIT_SHIFT_RARF_RC2_8821C) #define BIT_GET_RARF_RC2_8821C(x) (((x) >> BIT_SHIFT_RARF_RC2_8821C) & BIT_MASK_RARF_RC2_8821C) + #define BIT_SHIFT_RARF_RC1_8821C 0 #define BIT_MASK_RARF_RC1_8821C 0x1f #define BIT_RARF_RC1_8821C(x) (((x) & BIT_MASK_RARF_RC1_8821C) << BIT_SHIFT_RARF_RC1_8821C) #define BIT_GET_RARF_RC1_8821C(x) (((x) >> BIT_SHIFT_RARF_RC1_8821C) & BIT_MASK_RARF_RC1_8821C) + /* 2 REG_RRSR_8821C */ #define BIT_SHIFT_RRSR_RSC_8821C 21 @@ -5162,6 +5787,7 @@ #define BIT_RRSR_RSC_8821C(x) (((x) & BIT_MASK_RRSR_RSC_8821C) << BIT_SHIFT_RRSR_RSC_8821C) #define BIT_GET_RRSR_RSC_8821C(x) (((x) >> BIT_SHIFT_RRSR_RSC_8821C) & BIT_MASK_RRSR_RSC_8821C) + #define BIT_RRSR_BW_8821C BIT(20) #define BIT_SHIFT_RRSC_BITMAP_8821C 0 @@ -5170,6 +5796,7 @@ #define BIT_GET_RRSC_BITMAP_8821C(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8821C) & BIT_MASK_RRSC_BITMAP_8821C) + /* 2 REG_ARFR0_8821C */ #define BIT_SHIFT_ARFR0_V1_8821C 0 @@ -5178,6 +5805,7 @@ #define BIT_GET_ARFR0_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR0_V1_8821C) & BIT_MASK_ARFR0_V1_8821C) + /* 2 REG_ARFR1_V1_8821C */ #define BIT_SHIFT_ARFR1_V1_8821C 0 @@ -5186,6 +5814,7 @@ #define BIT_GET_ARFR1_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR1_V1_8821C) & BIT_MASK_ARFR1_V1_8821C) + /* 2 REG_CCK_CHECK_8821C */ #define BIT_CHECK_CCK_EN_8821C BIT(7) #define BIT_EN_BCN_PKT_REL_8821C BIT(6) @@ -5204,6 +5833,7 @@ #define BIT_GET_AMPDU_MAX_TIME_8821C(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8821C) & BIT_MASK_AMPDU_MAX_TIME_8821C) + /* 2 REG_BCNQ1_BDNY_V1_8821C */ #define BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C 0 @@ -5212,6 +5842,7 @@ #define BIT_GET_BCNQ1_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C) + /* 2 REG_AMPDU_MAX_LENGTH_8821C */ #define BIT_SHIFT_AMPDU_MAX_LENGTH_8821C 0 @@ -5220,6 +5851,7 @@ #define BIT_GET_AMPDU_MAX_LENGTH_8821C(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) & BIT_MASK_AMPDU_MAX_LENGTH_8821C) + /* 2 REG_ACQ_STOP_8821C */ #define BIT_AC7Q_STOP_8821C BIT(7) #define BIT_AC6Q_STOP_8821C BIT(6) @@ -5238,6 +5870,7 @@ #define BIT_GET_R_NDPA_RATE_V1_8821C(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8821C) & BIT_MASK_R_NDPA_RATE_V1_8821C) + /* 2 REG_TX_HANG_CTRL_8821C */ #define BIT_R_EN_GNT_BT_AWAKE_8821C BIT(3) #define BIT_EN_EOF_V1_8821C BIT(2) @@ -5252,6 +5885,7 @@ #define BIT_BW_SIGTA_8821C(x) (((x) & BIT_MASK_BW_SIGTA_8821C) << BIT_SHIFT_BW_SIGTA_8821C) #define BIT_GET_BW_SIGTA_8821C(x) (((x) >> BIT_SHIFT_BW_SIGTA_8821C) & BIT_MASK_BW_SIGTA_8821C) + #define BIT_EN_BAR_SIGTA_8821C BIT(2) #define BIT_SHIFT_R_NDPA_BW_8821C 0 @@ -5260,6 +5894,7 @@ #define BIT_GET_R_NDPA_BW_8821C(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8821C) & BIT_MASK_R_NDPA_BW_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -5272,6 +5907,7 @@ #define BIT_GET_RD_RESP_PKT_TH_V1_8821C(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C) + /* 2 REG_CMDQ_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C 25 @@ -5280,11 +5916,13 @@ #define BIT_GET_QUEUEMACID_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) + #define BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C 23 #define BIT_MASK_QUEUEAC_CMDQ_V1_8821C 0x3 #define BIT_QUEUEAC_CMDQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C) << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) #define BIT_GET_QUEUEAC_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C) + #define BIT_TIDEMPTY_CMDQ_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C 11 @@ -5293,12 +5931,14 @@ #define BIT_GET_TAIL_PKT_CMDQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C) & BIT_MASK_TAIL_PKT_CMDQ_V2_8821C) + #define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C 0 #define BIT_MASK_HEAD_PKT_CMDQ_V1_8821C 0x7ff #define BIT_HEAD_PKT_CMDQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) #define BIT_GET_HEAD_PKT_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) + /* 2 REG_Q4_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q4_V1_8821C 25 @@ -5307,11 +5947,13 @@ #define BIT_GET_QUEUEMACID_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) & BIT_MASK_QUEUEMACID_Q4_V1_8821C) + #define BIT_SHIFT_QUEUEAC_Q4_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q4_V1_8821C 0x3 #define BIT_QUEUEAC_Q4_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8821C) << BIT_SHIFT_QUEUEAC_Q4_V1_8821C) #define BIT_GET_QUEUEAC_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8821C) & BIT_MASK_QUEUEAC_Q4_V1_8821C) + #define BIT_TIDEMPTY_Q4_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q4_V2_8821C 11 @@ -5320,12 +5962,14 @@ #define BIT_GET_TAIL_PKT_Q4_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) + #define BIT_SHIFT_HEAD_PKT_Q4_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q4_V1_8821C 0x7ff #define BIT_HEAD_PKT_Q4_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) #define BIT_GET_HEAD_PKT_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) & BIT_MASK_HEAD_PKT_Q4_V1_8821C) + /* 2 REG_Q5_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q5_V1_8821C 25 @@ -5334,11 +5978,13 @@ #define BIT_GET_QUEUEMACID_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) & BIT_MASK_QUEUEMACID_Q5_V1_8821C) + #define BIT_SHIFT_QUEUEAC_Q5_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q5_V1_8821C 0x3 #define BIT_QUEUEAC_Q5_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8821C) << BIT_SHIFT_QUEUEAC_Q5_V1_8821C) #define BIT_GET_QUEUEAC_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8821C) & BIT_MASK_QUEUEAC_Q5_V1_8821C) + #define BIT_TIDEMPTY_Q5_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q5_V2_8821C 11 @@ -5347,12 +5993,14 @@ #define BIT_GET_TAIL_PKT_Q5_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) & BIT_MASK_TAIL_PKT_Q5_V2_8821C) + #define BIT_SHIFT_HEAD_PKT_Q5_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q5_V1_8821C 0x7ff #define BIT_HEAD_PKT_Q5_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) #define BIT_GET_HEAD_PKT_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) & BIT_MASK_HEAD_PKT_Q5_V1_8821C) + /* 2 REG_Q6_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q6_V1_8821C 25 @@ -5361,11 +6009,13 @@ #define BIT_GET_QUEUEMACID_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) & BIT_MASK_QUEUEMACID_Q6_V1_8821C) + #define BIT_SHIFT_QUEUEAC_Q6_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q6_V1_8821C 0x3 #define BIT_QUEUEAC_Q6_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8821C) << BIT_SHIFT_QUEUEAC_Q6_V1_8821C) #define BIT_GET_QUEUEAC_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8821C) & BIT_MASK_QUEUEAC_Q6_V1_8821C) + #define BIT_TIDEMPTY_Q6_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q6_V2_8821C 11 @@ -5374,12 +6024,14 @@ #define BIT_GET_TAIL_PKT_Q6_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) & BIT_MASK_TAIL_PKT_Q6_V2_8821C) + #define BIT_SHIFT_HEAD_PKT_Q6_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q6_V1_8821C 0x7ff #define BIT_HEAD_PKT_Q6_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) #define BIT_GET_HEAD_PKT_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) & BIT_MASK_HEAD_PKT_Q6_V1_8821C) + /* 2 REG_Q7_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q7_V1_8821C 25 @@ -5388,11 +6040,13 @@ #define BIT_GET_QUEUEMACID_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) & BIT_MASK_QUEUEMACID_Q7_V1_8821C) + #define BIT_SHIFT_QUEUEAC_Q7_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q7_V1_8821C 0x3 #define BIT_QUEUEAC_Q7_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8821C) << BIT_SHIFT_QUEUEAC_Q7_V1_8821C) #define BIT_GET_QUEUEAC_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8821C) & BIT_MASK_QUEUEAC_Q7_V1_8821C) + #define BIT_TIDEMPTY_Q7_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q7_V2_8821C 11 @@ -5401,12 +6055,14 @@ #define BIT_GET_TAIL_PKT_Q7_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) & BIT_MASK_TAIL_PKT_Q7_V2_8821C) + #define BIT_SHIFT_HEAD_PKT_Q7_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q7_V1_8821C 0x7ff #define BIT_HEAD_PKT_Q7_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) #define BIT_GET_HEAD_PKT_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) & BIT_MASK_HEAD_PKT_Q7_V1_8821C) + /* 2 REG_WMAC_LBK_BUF_HD_V1_8821C */ #define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C 0 @@ -5415,6 +6071,7 @@ #define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8821C(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) + /* 2 REG_MGQ_BDNY_V1_8821C */ #define BIT_SHIFT_MGQ_PGBNDY_V1_8821C 0 @@ -5423,6 +6080,7 @@ #define BIT_GET_MGQ_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8821C) & BIT_MASK_MGQ_PGBNDY_V1_8821C) + /* 2 REG_TXRPT_CTRL_8821C */ #define BIT_SHIFT_TRXRPT_TIMER_TH_8821C 24 @@ -5431,24 +6089,28 @@ #define BIT_GET_TRXRPT_TIMER_TH_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8821C) & BIT_MASK_TRXRPT_TIMER_TH_8821C) + #define BIT_SHIFT_TRXRPT_LEN_TH_8821C 16 #define BIT_MASK_TRXRPT_LEN_TH_8821C 0xff #define BIT_TRXRPT_LEN_TH_8821C(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8821C) << BIT_SHIFT_TRXRPT_LEN_TH_8821C) #define BIT_GET_TRXRPT_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8821C) & BIT_MASK_TRXRPT_LEN_TH_8821C) + #define BIT_SHIFT_TRXRPT_READ_PTR_8821C 8 #define BIT_MASK_TRXRPT_READ_PTR_8821C 0xff #define BIT_TRXRPT_READ_PTR_8821C(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8821C) << BIT_SHIFT_TRXRPT_READ_PTR_8821C) #define BIT_GET_TRXRPT_READ_PTR_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8821C) & BIT_MASK_TRXRPT_READ_PTR_8821C) + #define BIT_SHIFT_TRXRPT_WRITE_PTR_8821C 0 #define BIT_MASK_TRXRPT_WRITE_PTR_8821C 0xff #define BIT_TRXRPT_WRITE_PTR_8821C(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8821C) << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) #define BIT_GET_TRXRPT_WRITE_PTR_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) & BIT_MASK_TRXRPT_WRITE_PTR_8821C) + /* 2 REG_INIRTS_RATE_SEL_8821C */ #define BIT_LEAG_RTS_BW_DUP_8821C BIT(5) @@ -5460,6 +6122,7 @@ #define BIT_GET_BASIC_CFEND_RATE_8821C(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8821C) & BIT_MASK_BASIC_CFEND_RATE_8821C) + /* 2 REG_STBC_CFEND_RATE_8821C */ #define BIT_SHIFT_STBC_CFEND_RATE_8821C 0 @@ -5468,6 +6131,7 @@ #define BIT_GET_STBC_CFEND_RATE_8821C(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8821C) & BIT_MASK_STBC_CFEND_RATE_8821C) + /* 2 REG_DATA_SC_8821C */ #define BIT_SHIFT_TXSC_40M_8821C 4 @@ -5476,12 +6140,14 @@ #define BIT_GET_TXSC_40M_8821C(x) (((x) >> BIT_SHIFT_TXSC_40M_8821C) & BIT_MASK_TXSC_40M_8821C) + #define BIT_SHIFT_TXSC_20M_8821C 0 #define BIT_MASK_TXSC_20M_8821C 0xf #define BIT_TXSC_20M_8821C(x) (((x) & BIT_MASK_TXSC_20M_8821C) << BIT_SHIFT_TXSC_20M_8821C) #define BIT_GET_TXSC_20M_8821C(x) (((x) >> BIT_SHIFT_TXSC_20M_8821C) & BIT_MASK_TXSC_20M_8821C) + /* 2 REG_MACID_SLEEP3_8821C */ #define BIT_SHIFT_MACID127_96_PKTSLEEP_8821C 0 @@ -5490,6 +6156,7 @@ #define BIT_GET_MACID127_96_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) & BIT_MASK_MACID127_96_PKTSLEEP_8821C) + /* 2 REG_MACID_SLEEP1_8821C */ #define BIT_SHIFT_MACID63_32_PKTSLEEP_8821C 0 @@ -5498,6 +6165,7 @@ #define BIT_GET_MACID63_32_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) & BIT_MASK_MACID63_32_PKTSLEEP_8821C) + /* 2 REG_ARFR2_V1_8821C */ #define BIT_SHIFT_ARFR2_V1_8821C 0 @@ -5506,6 +6174,7 @@ #define BIT_GET_ARFR2_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR2_V1_8821C) & BIT_MASK_ARFR2_V1_8821C) + /* 2 REG_ARFR3_V1_8821C */ #define BIT_SHIFT_ARFR3_V1_8821C 0 @@ -5514,6 +6183,7 @@ #define BIT_GET_ARFR3_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR3_V1_8821C) & BIT_MASK_ARFR3_V1_8821C) + /* 2 REG_ARFR4_8821C */ #define BIT_SHIFT_ARFR4_8821C 0 @@ -5522,6 +6192,7 @@ #define BIT_GET_ARFR4_8821C(x) (((x) >> BIT_SHIFT_ARFR4_8821C) & BIT_MASK_ARFR4_8821C) + /* 2 REG_ARFR5_8821C */ #define BIT_SHIFT_ARFR5_8821C 0 @@ -5530,6 +6201,7 @@ #define BIT_GET_ARFR5_8821C(x) (((x) >> BIT_SHIFT_ARFR5_8821C) & BIT_MASK_ARFR5_8821C) + /* 2 REG_TXRPT_START_OFFSET_8821C */ #define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C 24 @@ -5537,6 +6209,7 @@ #define BIT_R_MUTAB_TXRPT_OFFSET_8821C(x) (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) #define BIT_GET_R_MUTAB_TXRPT_OFFSET_8821C(x) (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) + #define BIT__R_RPTFIFO_1K_8821C BIT(16) #define BIT_SHIFT_MACID_CTRL_OFFSET_8821C 8 @@ -5545,12 +6218,14 @@ #define BIT_GET_MACID_CTRL_OFFSET_8821C(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8821C) & BIT_MASK_MACID_CTRL_OFFSET_8821C) + #define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C 0 #define BIT_MASK_AMPDU_TXRPT_OFFSET_8821C 0xff #define BIT_AMPDU_TXRPT_OFFSET_8821C(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) #define BIT_GET_AMPDU_TXRPT_OFFSET_8821C(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_POWER_STAGE1_8821C */ @@ -5569,6 +6244,7 @@ #define BIT_GET_POWER_STAGE1_8821C(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8821C) & BIT_MASK_POWER_STAGE1_8821C) + /* 2 REG_POWER_STAGE2_8821C */ #define BIT__R_CTRL_PKT_POW_ADJ_8821C BIT(24) @@ -5578,6 +6254,7 @@ #define BIT_GET_POWER_STAGE2_8821C(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8821C) & BIT_MASK_POWER_STAGE2_8821C) + /* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8821C */ #define BIT_SHIFT_PAD_NUM_THRES_8821C 24 @@ -5585,6 +6262,7 @@ #define BIT_PAD_NUM_THRES_8821C(x) (((x) & BIT_MASK_PAD_NUM_THRES_8821C) << BIT_SHIFT_PAD_NUM_THRES_8821C) #define BIT_GET_PAD_NUM_THRES_8821C(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8821C) & BIT_MASK_PAD_NUM_THRES_8821C) + #define BIT_R_DMA_THIS_QUEUE_BK_8821C BIT(23) #define BIT_R_DMA_THIS_QUEUE_BE_8821C BIT(22) #define BIT_R_DMA_THIS_QUEUE_VI_8821C BIT(21) @@ -5595,6 +6273,7 @@ #define BIT_R_TOTAL_LEN_TH_8821C(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8821C) << BIT_SHIFT_R_TOTAL_LEN_TH_8821C) #define BIT_GET_R_TOTAL_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8821C) & BIT_MASK_R_TOTAL_LEN_TH_8821C) + #define BIT_EN_NEW_EARLY_8821C BIT(7) #define BIT_PRE_TX_CMD_8821C BIT(6) @@ -5603,6 +6282,7 @@ #define BIT_NUM_SCL_EN_8821C(x) (((x) & BIT_MASK_NUM_SCL_EN_8821C) << BIT_SHIFT_NUM_SCL_EN_8821C) #define BIT_GET_NUM_SCL_EN_8821C(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8821C) & BIT_MASK_NUM_SCL_EN_8821C) + #define BIT_BK_EN_8821C BIT(3) #define BIT_BE_EN_8821C BIT(2) #define BIT_VI_EN_8821C BIT(1) @@ -5616,12 +6296,14 @@ #define BIT_GET_PKT_LIFTIME_BEBK_8821C(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) & BIT_MASK_PKT_LIFTIME_BEBK_8821C) + #define BIT_SHIFT_PKT_LIFTIME_VOVI_8821C 0 #define BIT_MASK_PKT_LIFTIME_VOVI_8821C 0xffff #define BIT_PKT_LIFTIME_VOVI_8821C(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8821C) << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) #define BIT_GET_PKT_LIFTIME_VOVI_8821C(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) & BIT_MASK_PKT_LIFTIME_VOVI_8821C) + /* 2 REG_STBC_SETTING_8821C */ #define BIT_SHIFT_CDEND_TXTIME_L_8821C 4 @@ -5630,18 +6312,21 @@ #define BIT_GET_CDEND_TXTIME_L_8821C(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8821C) & BIT_MASK_CDEND_TXTIME_L_8821C) + #define BIT_SHIFT_NESS_8821C 2 #define BIT_MASK_NESS_8821C 0x3 #define BIT_NESS_8821C(x) (((x) & BIT_MASK_NESS_8821C) << BIT_SHIFT_NESS_8821C) #define BIT_GET_NESS_8821C(x) (((x) >> BIT_SHIFT_NESS_8821C) & BIT_MASK_NESS_8821C) + #define BIT_SHIFT_STBC_CFEND_8821C 0 #define BIT_MASK_STBC_CFEND_8821C 0x3 #define BIT_STBC_CFEND_8821C(x) (((x) & BIT_MASK_STBC_CFEND_8821C) << BIT_SHIFT_STBC_CFEND_8821C) #define BIT_GET_STBC_CFEND_8821C(x) (((x) >> BIT_SHIFT_STBC_CFEND_8821C) & BIT_MASK_STBC_CFEND_8821C) + /* 2 REG_STBC_SETTING2_8821C */ #define BIT_SHIFT_CDEND_TXTIME_H_8821C 0 @@ -5650,6 +6335,7 @@ #define BIT_GET_CDEND_TXTIME_H_8821C(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8821C) & BIT_MASK_CDEND_TXTIME_H_8821C) + /* 2 REG_QUEUE_CTRL_8821C */ #define BIT_PTA_EDCCA_EN_8821C BIT(5) #define BIT_PTA_WL_TX_EN_8821C BIT(4) @@ -5669,24 +6355,28 @@ #define BIT_GET_RTS_MAX_AGG_NUM_8821C(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) & BIT_MASK_RTS_MAX_AGG_NUM_8821C) + #define BIT_SHIFT_MAX_AGG_NUM_8821C 16 #define BIT_MASK_MAX_AGG_NUM_8821C 0x3f #define BIT_MAX_AGG_NUM_8821C(x) (((x) & BIT_MASK_MAX_AGG_NUM_8821C) << BIT_SHIFT_MAX_AGG_NUM_8821C) #define BIT_GET_MAX_AGG_NUM_8821C(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8821C) & BIT_MASK_MAX_AGG_NUM_8821C) + #define BIT_SHIFT_RTS_TXTIME_TH_8821C 8 #define BIT_MASK_RTS_TXTIME_TH_8821C 0xff #define BIT_RTS_TXTIME_TH_8821C(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8821C) << BIT_SHIFT_RTS_TXTIME_TH_8821C) #define BIT_GET_RTS_TXTIME_TH_8821C(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8821C) & BIT_MASK_RTS_TXTIME_TH_8821C) + #define BIT_SHIFT_RTS_LEN_TH_8821C 0 #define BIT_MASK_RTS_LEN_TH_8821C 0xff #define BIT_RTS_LEN_TH_8821C(x) (((x) & BIT_MASK_RTS_LEN_TH_8821C) << BIT_SHIFT_RTS_LEN_TH_8821C) #define BIT_GET_RTS_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8821C) & BIT_MASK_RTS_LEN_TH_8821C) + /* 2 REG_BAR_MODE_CTRL_8821C */ #define BIT_SHIFT_BAR_RTY_LMT_8821C 16 @@ -5695,11 +6385,13 @@ #define BIT_GET_BAR_RTY_LMT_8821C(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8821C) & BIT_MASK_BAR_RTY_LMT_8821C) + #define BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C 8 #define BIT_MASK_BAR_PKT_TXTIME_TH_8821C 0xff #define BIT_BAR_PKT_TXTIME_TH_8821C(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) #define BIT_GET_BAR_PKT_TXTIME_TH_8821C(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C) + #define BIT_BAR_EN_V1_8821C BIT(6) #define BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C 0 @@ -5708,6 +6400,7 @@ #define BIT_GET_BAR_PKTNUM_TH_V1_8821C(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C) + /* 2 REG_RA_TRY_RATE_AGG_LMT_8821C */ #define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C 0 @@ -5716,6 +6409,7 @@ #define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8821C(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) + /* 2 REG_MACID_SLEEP2_8821C */ #define BIT_SHIFT_MACID95_64PKTSLEEP_8821C 0 @@ -5724,6 +6418,7 @@ #define BIT_GET_MACID95_64PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8821C) & BIT_MASK_MACID95_64PKTSLEEP_8821C) + /* 2 REG_MACID_SLEEP_8821C */ #define BIT_SHIFT_MACID31_0_PKTSLEEP_8821C 0 @@ -5732,6 +6427,7 @@ #define BIT_GET_MACID31_0_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) & BIT_MASK_MACID31_0_PKTSLEEP_8821C) + /* 2 REG_HW_SEQ0_8821C */ #define BIT_SHIFT_HW_SSN_SEQ0_8821C 0 @@ -5740,6 +6436,7 @@ #define BIT_GET_HW_SSN_SEQ0_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8821C) & BIT_MASK_HW_SSN_SEQ0_8821C) + /* 2 REG_HW_SEQ1_8821C */ #define BIT_SHIFT_HW_SSN_SEQ1_8821C 0 @@ -5748,6 +6445,7 @@ #define BIT_GET_HW_SSN_SEQ1_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8821C) & BIT_MASK_HW_SSN_SEQ1_8821C) + /* 2 REG_HW_SEQ2_8821C */ #define BIT_SHIFT_HW_SSN_SEQ2_8821C 0 @@ -5756,6 +6454,7 @@ #define BIT_GET_HW_SSN_SEQ2_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8821C) & BIT_MASK_HW_SSN_SEQ2_8821C) + /* 2 REG_HW_SEQ3_8821C */ #define BIT_SHIFT_HW_SSN_SEQ3_8821C 0 @@ -5764,6 +6463,7 @@ #define BIT_GET_HW_SSN_SEQ3_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8821C) & BIT_MASK_HW_SSN_SEQ3_8821C) + /* 2 REG_NULL_PKT_STATUS_V1_8821C */ #define BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C 2 @@ -5771,6 +6471,7 @@ #define BIT_PTCL_TOTAL_PG_V2_8821C(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C) << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) #define BIT_GET_PTCL_TOTAL_PG_V2_8821C(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C) + #define BIT_TX_NULL_1_8821C BIT(1) #define BIT_TX_NULL_0_8821C BIT(0) @@ -5806,6 +6507,7 @@ #define BIT_GET_BT_POLLUTE_PKT_CNT_8821C(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_PTCL_DBG_8821C */ @@ -5816,6 +6518,7 @@ #define BIT_GET_PTCL_DBG_8821C(x) (((x) >> BIT_SHIFT_PTCL_DBG_8821C) & BIT_MASK_PTCL_DBG_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_CPUMGQ_TIMER_CTRL2_8821C */ @@ -5825,6 +6528,7 @@ #define BIT_TRI_HEAD_ADDR_8821C(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8821C) << BIT_SHIFT_TRI_HEAD_ADDR_8821C) #define BIT_GET_TRI_HEAD_ADDR_8821C(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8821C) & BIT_MASK_TRI_HEAD_ADDR_8821C) + #define BIT_DROP_TH_EN_8821C BIT(8) #define BIT_SHIFT_DROP_TH_8821C 0 @@ -5833,6 +6537,7 @@ #define BIT_GET_DROP_TH_8821C(x) (((x) >> BIT_SHIFT_DROP_TH_8821C) & BIT_MASK_DROP_TH_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_DUMMY_PAGE4_V1_8821C */ @@ -5853,11 +6558,13 @@ #define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) + #define BIT_SHIFT_AC1_PKT_INFO_8821C 16 #define BIT_MASK_AC1_PKT_INFO_8821C 0xfff #define BIT_AC1_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC1_PKT_INFO_8821C) << BIT_SHIFT_AC1_PKT_INFO_8821C) #define BIT_GET_AC1_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8821C) & BIT_MASK_AC1_PKT_INFO_8821C) + #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8821C 12 @@ -5866,12 +6573,14 @@ #define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) + #define BIT_SHIFT_AC0_PKT_INFO_8821C 0 #define BIT_MASK_AC0_PKT_INFO_8821C 0xfff #define BIT_AC0_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC0_PKT_INFO_8821C) << BIT_SHIFT_AC0_PKT_INFO_8821C) #define BIT_GET_AC0_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8821C) & BIT_MASK_AC0_PKT_INFO_8821C) + /* 2 REG_Q2_Q3_INFO_8821C */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) @@ -5881,11 +6590,13 @@ #define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) + #define BIT_SHIFT_AC3_PKT_INFO_8821C 16 #define BIT_MASK_AC3_PKT_INFO_8821C 0xfff #define BIT_AC3_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC3_PKT_INFO_8821C) << BIT_SHIFT_AC3_PKT_INFO_8821C) #define BIT_GET_AC3_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8821C) & BIT_MASK_AC3_PKT_INFO_8821C) + #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8821C 12 @@ -5894,12 +6605,14 @@ #define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) + #define BIT_SHIFT_AC2_PKT_INFO_8821C 0 #define BIT_MASK_AC2_PKT_INFO_8821C 0xfff #define BIT_AC2_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC2_PKT_INFO_8821C) << BIT_SHIFT_AC2_PKT_INFO_8821C) #define BIT_GET_AC2_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8821C) & BIT_MASK_AC2_PKT_INFO_8821C) + /* 2 REG_Q4_Q5_INFO_8821C */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) @@ -5909,11 +6622,13 @@ #define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) + #define BIT_SHIFT_AC5_PKT_INFO_8821C 16 #define BIT_MASK_AC5_PKT_INFO_8821C 0xfff #define BIT_AC5_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC5_PKT_INFO_8821C) << BIT_SHIFT_AC5_PKT_INFO_8821C) #define BIT_GET_AC5_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8821C) & BIT_MASK_AC5_PKT_INFO_8821C) + #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8821C 12 @@ -5922,12 +6637,14 @@ #define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) + #define BIT_SHIFT_AC4_PKT_INFO_8821C 0 #define BIT_MASK_AC4_PKT_INFO_8821C 0xfff #define BIT_AC4_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC4_PKT_INFO_8821C) << BIT_SHIFT_AC4_PKT_INFO_8821C) #define BIT_GET_AC4_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8821C) & BIT_MASK_AC4_PKT_INFO_8821C) + /* 2 REG_Q6_Q7_INFO_8821C */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) @@ -5937,11 +6654,13 @@ #define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) + #define BIT_SHIFT_AC7_PKT_INFO_8821C 16 #define BIT_MASK_AC7_PKT_INFO_8821C 0xfff #define BIT_AC7_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC7_PKT_INFO_8821C) << BIT_SHIFT_AC7_PKT_INFO_8821C) #define BIT_GET_AC7_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8821C) & BIT_MASK_AC7_PKT_INFO_8821C) + #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8821C 12 @@ -5950,12 +6669,14 @@ #define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) + #define BIT_SHIFT_AC6_PKT_INFO_8821C 0 #define BIT_MASK_AC6_PKT_INFO_8821C 0xfff #define BIT_AC6_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC6_PKT_INFO_8821C) << BIT_SHIFT_AC6_PKT_INFO_8821C) #define BIT_GET_AC6_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8821C) & BIT_MASK_AC6_PKT_INFO_8821C) + /* 2 REG_MGQ_HIQ_INFO_8821C */ #define BIT_SHIFT_HIQ_PKT_INFO_8821C 16 @@ -5964,12 +6685,14 @@ #define BIT_GET_HIQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8821C) & BIT_MASK_HIQ_PKT_INFO_8821C) + #define BIT_SHIFT_MGQ_PKT_INFO_8821C 0 #define BIT_MASK_MGQ_PKT_INFO_8821C 0xfff #define BIT_MGQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8821C) << BIT_SHIFT_MGQ_PKT_INFO_8821C) #define BIT_GET_MGQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8821C) & BIT_MASK_MGQ_PKT_INFO_8821C) + /* 2 REG_CMDQ_BCNQ_INFO_8821C */ #define BIT_SHIFT_CMDQ_PKT_INFO_8821C 16 @@ -5978,12 +6701,14 @@ #define BIT_GET_CMDQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8821C) & BIT_MASK_CMDQ_PKT_INFO_8821C) + #define BIT_SHIFT_BCNQ_PKT_INFO_8821C 0 #define BIT_MASK_BCNQ_PKT_INFO_8821C 0xfff #define BIT_BCNQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_8821C) << BIT_SHIFT_BCNQ_PKT_INFO_8821C) #define BIT_GET_BCNQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8821C) & BIT_MASK_BCNQ_PKT_INFO_8821C) + /* 2 REG_USEREG_SETTING_8821C */ #define BIT_NDPA_USEREG_8821C BIT(21) @@ -5993,11 +6718,13 @@ #define BIT_GET_RETRY_USEREG_8821C(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8821C) & BIT_MASK_RETRY_USEREG_8821C) + #define BIT_SHIFT_TRYPKT_USEREG_8821C 17 #define BIT_MASK_TRYPKT_USEREG_8821C 0x3 #define BIT_TRYPKT_USEREG_8821C(x) (((x) & BIT_MASK_TRYPKT_USEREG_8821C) << BIT_SHIFT_TRYPKT_USEREG_8821C) #define BIT_GET_TRYPKT_USEREG_8821C(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8821C) & BIT_MASK_TRYPKT_USEREG_8821C) + #define BIT_CTLPKT_USEREG_8821C BIT(16) /* 2 REG_AESIV_SETTING_8821C */ @@ -6008,6 +6735,7 @@ #define BIT_GET_AESIV_OFFSET_8821C(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8821C) & BIT_MASK_AESIV_OFFSET_8821C) + /* 2 REG_BF0_TIME_SETTING_8821C */ #define BIT_BF0_TIMER_SET_8821C BIT(31) #define BIT_BF0_TIMER_CLR_8821C BIT(30) @@ -6020,12 +6748,14 @@ #define BIT_GET_BF0_PRETIME_OVER_8821C(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8821C) & BIT_MASK_BF0_PRETIME_OVER_8821C) + #define BIT_SHIFT_BF0_LIFETIME_8821C 0 #define BIT_MASK_BF0_LIFETIME_8821C 0xffff #define BIT_BF0_LIFETIME_8821C(x) (((x) & BIT_MASK_BF0_LIFETIME_8821C) << BIT_SHIFT_BF0_LIFETIME_8821C) #define BIT_GET_BF0_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8821C) & BIT_MASK_BF0_LIFETIME_8821C) + /* 2 REG_BF1_TIME_SETTING_8821C */ #define BIT_BF1_TIMER_SET_8821C BIT(31) #define BIT_BF1_TIMER_CLR_8821C BIT(30) @@ -6038,12 +6768,14 @@ #define BIT_GET_BF1_PRETIME_OVER_8821C(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8821C) & BIT_MASK_BF1_PRETIME_OVER_8821C) + #define BIT_SHIFT_BF1_LIFETIME_8821C 0 #define BIT_MASK_BF1_LIFETIME_8821C 0xffff #define BIT_BF1_LIFETIME_8821C(x) (((x) & BIT_MASK_BF1_LIFETIME_8821C) << BIT_SHIFT_BF1_LIFETIME_8821C) #define BIT_GET_BF1_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8821C) & BIT_MASK_BF1_LIFETIME_8821C) + /* 2 REG_BF_TIMEOUT_EN_8821C */ #define BIT_EN_VHT_LDPC_8821C BIT(9) #define BIT_EN_HT_LDPC_8821C BIT(8) @@ -6058,6 +6790,7 @@ #define BIT_GET_MACID31_0_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8821C) & BIT_MASK_MACID31_0_RELEASE_8821C) + /* 2 REG_MACID_RELEASE1_8821C */ #define BIT_SHIFT_MACID63_32_RELEASE_8821C 0 @@ -6066,6 +6799,7 @@ #define BIT_GET_MACID63_32_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8821C) & BIT_MASK_MACID63_32_RELEASE_8821C) + /* 2 REG_MACID_RELEASE2_8821C */ #define BIT_SHIFT_MACID95_64_RELEASE_8821C 0 @@ -6074,6 +6808,7 @@ #define BIT_GET_MACID95_64_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8821C) & BIT_MASK_MACID95_64_RELEASE_8821C) + /* 2 REG_MACID_RELEASE3_8821C */ #define BIT_SHIFT_MACID127_96_RELEASE_8821C 0 @@ -6082,6 +6817,7 @@ #define BIT_GET_MACID127_96_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8821C) & BIT_MASK_MACID127_96_RELEASE_8821C) + /* 2 REG_MACID_RELEASE_SETTING_8821C */ #define BIT_MACID_VALUE_8821C BIT(7) @@ -6091,6 +6827,7 @@ #define BIT_GET_MACID_OFFSET_8821C(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8821C) & BIT_MASK_MACID_OFFSET_8821C) + /* 2 REG_FAST_EDCA_VOVI_SETTING_8821C */ #define BIT_SHIFT_VI_FAST_EDCA_TO_8821C 24 @@ -6098,6 +6835,7 @@ #define BIT_VI_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8821C) << BIT_SHIFT_VI_FAST_EDCA_TO_8821C) #define BIT_GET_VI_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8821C) & BIT_MASK_VI_FAST_EDCA_TO_8821C) + #define BIT_VI_THRESHOLD_SEL_8821C BIT(23) #define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C 16 @@ -6106,11 +6844,13 @@ #define BIT_GET_VI_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) + #define BIT_SHIFT_VO_FAST_EDCA_TO_8821C 8 #define BIT_MASK_VO_FAST_EDCA_TO_8821C 0xff #define BIT_VO_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8821C) << BIT_SHIFT_VO_FAST_EDCA_TO_8821C) #define BIT_GET_VO_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8821C) & BIT_MASK_VO_FAST_EDCA_TO_8821C) + #define BIT_VO_THRESHOLD_SEL_8821C BIT(7) #define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C 0 @@ -6119,6 +6859,7 @@ #define BIT_GET_VO_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) + /* 2 REG_FAST_EDCA_BEBK_SETTING_8821C */ #define BIT_SHIFT_BK_FAST_EDCA_TO_8821C 24 @@ -6126,6 +6867,7 @@ #define BIT_BK_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8821C) << BIT_SHIFT_BK_FAST_EDCA_TO_8821C) #define BIT_GET_BK_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8821C) & BIT_MASK_BK_FAST_EDCA_TO_8821C) + #define BIT_BK_THRESHOLD_SEL_8821C BIT(23) #define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C 16 @@ -6134,11 +6876,13 @@ #define BIT_GET_BK_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) + #define BIT_SHIFT_BE_FAST_EDCA_TO_8821C 8 #define BIT_MASK_BE_FAST_EDCA_TO_8821C 0xff #define BIT_BE_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8821C) << BIT_SHIFT_BE_FAST_EDCA_TO_8821C) #define BIT_GET_BE_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8821C) & BIT_MASK_BE_FAST_EDCA_TO_8821C) + #define BIT_BE_THRESHOLD_SEL_8821C BIT(7) #define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C 0 @@ -6147,6 +6891,7 @@ #define BIT_GET_BE_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) + /* 2 REG_MACID_DROP0_8821C */ #define BIT_SHIFT_MACID31_0_DROP_8821C 0 @@ -6155,6 +6900,7 @@ #define BIT_GET_MACID31_0_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8821C) & BIT_MASK_MACID31_0_DROP_8821C) + /* 2 REG_MACID_DROP1_8821C */ #define BIT_SHIFT_MACID63_32_DROP_8821C 0 @@ -6163,6 +6909,7 @@ #define BIT_GET_MACID63_32_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8821C) & BIT_MASK_MACID63_32_DROP_8821C) + /* 2 REG_MACID_DROP2_8821C */ #define BIT_SHIFT_MACID95_64_DROP_8821C 0 @@ -6171,6 +6918,7 @@ #define BIT_GET_MACID95_64_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8821C) & BIT_MASK_MACID95_64_DROP_8821C) + /* 2 REG_MACID_DROP3_8821C */ #define BIT_SHIFT_MACID127_96_DROP_8821C 0 @@ -6179,6 +6927,7 @@ #define BIT_GET_MACID127_96_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8821C) & BIT_MASK_MACID127_96_DROP_8821C) + /* 2 REG_R_MACID_RELEASE_SUCCESS_0_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C 0 @@ -6187,6 +6936,7 @@ #define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) + /* 2 REG_R_MACID_RELEASE_SUCCESS_1_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C 0 @@ -6195,6 +6945,7 @@ #define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) + /* 2 REG_R_MACID_RELEASE_SUCCESS_2_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C 0 @@ -6203,6 +6954,7 @@ #define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) + /* 2 REG_R_MACID_RELEASE_SUCCESS_3_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C 0 @@ -6211,6 +6963,7 @@ #define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) + /* 2 REG_MGG_FIFO_CRTL_8821C */ #define BIT_R_MGG_FIFO_EN_8821C BIT(31) @@ -6220,17 +6973,20 @@ #define BIT_GET_R_MGG_FIFO_PG_SIZE_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C) + #define BIT_SHIFT_R_MGG_FIFO_START_PG_8821C 16 #define BIT_MASK_R_MGG_FIFO_START_PG_8821C 0xfff #define BIT_R_MGG_FIFO_START_PG_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8821C) << BIT_SHIFT_R_MGG_FIFO_START_PG_8821C) #define BIT_GET_R_MGG_FIFO_START_PG_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8821C) & BIT_MASK_R_MGG_FIFO_START_PG_8821C) + #define BIT_SHIFT_R_MGG_FIFO_SIZE_8821C 14 #define BIT_MASK_R_MGG_FIFO_SIZE_8821C 0x3 #define BIT_R_MGG_FIFO_SIZE_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8821C) << BIT_SHIFT_R_MGG_FIFO_SIZE_8821C) #define BIT_GET_R_MGG_FIFO_SIZE_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8821C) & BIT_MASK_R_MGG_FIFO_SIZE_8821C) + #define BIT_R_MGG_FIFO_PAUSE_8821C BIT(13) #define BIT_SHIFT_R_MGG_FIFO_RPTR_8821C 8 @@ -6238,6 +6994,7 @@ #define BIT_R_MGG_FIFO_RPTR_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8821C) << BIT_SHIFT_R_MGG_FIFO_RPTR_8821C) #define BIT_GET_R_MGG_FIFO_RPTR_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8821C) & BIT_MASK_R_MGG_FIFO_RPTR_8821C) + #define BIT_R_MGG_FIFO_OV_8821C BIT(7) #define BIT_R_MGG_FIFO_WPTR_ERROR_8821C BIT(6) #define BIT_R_EN_CPU_LIFETIME_8821C BIT(5) @@ -6248,6 +7005,7 @@ #define BIT_GET_R_MGG_FIFO_WPTR_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8821C) & BIT_MASK_R_MGG_FIFO_WPTR_8821C) + /* 2 REG_MGG_FIFO_INT_8821C */ #define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C 16 @@ -6256,12 +7014,14 @@ #define BIT_GET_R_MGG_FIFO_INT_FLAG_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C) + #define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C 0 #define BIT_MASK_R_MGG_FIFO_INT_MASK_8821C 0xffff #define BIT_R_MGG_FIFO_INT_MASK_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8821C) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C) #define BIT_GET_R_MGG_FIFO_INT_MASK_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C) & BIT_MASK_R_MGG_FIFO_INT_MASK_8821C) + /* 2 REG_MGG_FIFO_LIFETIME_8821C */ #define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C 16 @@ -6270,12 +7030,14 @@ #define BIT_GET_R_MGG_FIFO_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C) & BIT_MASK_R_MGG_FIFO_LIFETIME_8821C) + #define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C 0 #define BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C 0xffff #define BIT_R_MGG_FIFO_VALID_MAP_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C) #define BIT_GET_R_MGG_FIFO_VALID_MAP_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C) + /* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0 @@ -6284,7 +7046,8 @@ #define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) -/* 2 REG_MU_TX_CTL_8821C */ + +/* 2 REG_MU_TX_CTL_8821C (NOT SUPPORT) */ #define BIT_R_FORCE_P1_RATEDOWN_8821C BIT(11) #define BIT_SHIFT_R_MU_TAB_SEL_8821C 8 @@ -6292,6 +7055,7 @@ #define BIT_R_MU_TAB_SEL_8821C(x) (((x) & BIT_MASK_R_MU_TAB_SEL_8821C) << BIT_SHIFT_R_MU_TAB_SEL_8821C) #define BIT_GET_R_MU_TAB_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8821C) & BIT_MASK_R_MU_TAB_SEL_8821C) + #define BIT_R_EN_MU_MIMO_8821C BIT(7) #define BIT_R_EN_REVERS_GTAB_8821C BIT(6) @@ -6301,7 +7065,8 @@ #define BIT_GET_R_MU_TABLE_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8821C) & BIT_MASK_R_MU_TABLE_VALID_8821C) -/* 2 REG_MU_STA_GID_VLD_8821C */ + +/* 2 REG_MU_STA_GID_VLD_8821C (NOT SUPPORT) */ /* 2 REG_NOT_VALID_8821C */ @@ -6311,13 +7076,15 @@ #define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) + #define BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C 0 #define BIT_MASK_R_MU_STA_GTAB_VALID_8821C 0xffffffffL #define BIT_R_MU_STA_GTAB_VALID_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) #define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) -/* 2 REG_MU_STA_USER_POS_INFO_8821C */ + +/* 2 REG_MU_STA_USER_POS_INFO_8821C (NOT SUPPORT) */ /* 2 REG_NOT_VALID_8821C */ @@ -6327,13 +7094,15 @@ #define BIT_GET_R_MU_STA_GTAB_POSITION_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) + #define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C 0 #define BIT_MASK_R_MU_STA_GTAB_POSITION_8821C 0xffffffffffffffffL #define BIT_R_MU_STA_GTAB_POSITION_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) #define BIT_GET_R_MU_STA_GTAB_POSITION_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) -/* 2 REG_MU_TRX_DBG_CNT_8821C */ + +/* 2 REG_MU_TRX_DBG_CNT_8821C (NOT SUPPORT) */ #define BIT_MU_DNGCNT_RST_8821C BIT(20) #define BIT_SHIFT_MU_DBGCNT_SEL_8821C 16 @@ -6342,12 +7111,14 @@ #define BIT_GET_MU_DBGCNT_SEL_8821C(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8821C) & BIT_MASK_MU_DBGCNT_SEL_8821C) + #define BIT_SHIFT_MU_DNGCNT_8821C 0 #define BIT_MASK_MU_DNGCNT_8821C 0xffff #define BIT_MU_DNGCNT_8821C(x) (((x) & BIT_MASK_MU_DNGCNT_8821C) << BIT_SHIFT_MU_DNGCNT_8821C) #define BIT_GET_MU_DNGCNT_8821C(x) (((x) >> BIT_SHIFT_MU_DNGCNT_8821C) & BIT_MASK_MU_DNGCNT_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_EDCA_VO_PARAM_8821C */ @@ -6358,18 +7129,21 @@ #define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) + #define BIT_SHIFT_CW_8821C 8 #define BIT_MASK_CW_8821C 0xff #define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) #define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) + #define BIT_SHIFT_AIFS_8821C 0 #define BIT_MASK_AIFS_8821C 0xff #define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) #define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) + /* 2 REG_EDCA_VI_PARAM_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -6380,18 +7154,21 @@ #define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) + #define BIT_SHIFT_CW_8821C 8 #define BIT_MASK_CW_8821C 0xff #define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) #define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) + #define BIT_SHIFT_AIFS_8821C 0 #define BIT_MASK_AIFS_8821C 0xff #define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) #define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) + /* 2 REG_EDCA_BE_PARAM_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -6402,18 +7179,21 @@ #define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) + #define BIT_SHIFT_CW_8821C 8 #define BIT_MASK_CW_8821C 0xff #define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) #define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) + #define BIT_SHIFT_AIFS_8821C 0 #define BIT_MASK_AIFS_8821C 0xff #define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) #define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) + /* 2 REG_EDCA_BK_PARAM_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -6424,18 +7204,21 @@ #define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) + #define BIT_SHIFT_CW_8821C 8 #define BIT_MASK_CW_8821C 0xff #define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) #define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) + #define BIT_SHIFT_AIFS_8821C 0 #define BIT_MASK_AIFS_8821C 0xff #define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) #define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) + /* 2 REG_BCNTCFG_8821C */ #define BIT_SHIFT_BCNCW_MAX_8821C 12 @@ -6444,18 +7227,23 @@ #define BIT_GET_BCNCW_MAX_8821C(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8821C) & BIT_MASK_BCNCW_MAX_8821C) + #define BIT_SHIFT_BCNCW_MIN_8821C 8 #define BIT_MASK_BCNCW_MIN_8821C 0xf #define BIT_BCNCW_MIN_8821C(x) (((x) & BIT_MASK_BCNCW_MIN_8821C) << BIT_SHIFT_BCNCW_MIN_8821C) #define BIT_GET_BCNCW_MIN_8821C(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8821C) & BIT_MASK_BCNCW_MIN_8821C) + #define BIT_SHIFT_BCNIFS_8821C 0 #define BIT_MASK_BCNIFS_8821C 0xff #define BIT_BCNIFS_8821C(x) (((x) & BIT_MASK_BCNIFS_8821C) << BIT_SHIFT_BCNIFS_8821C) #define BIT_GET_BCNIFS_8821C(x) (((x) >> BIT_SHIFT_BCNIFS_8821C) & BIT_MASK_BCNIFS_8821C) + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_PIFS_8821C */ #define BIT_SHIFT_PIFS_8821C 0 @@ -6464,6 +7252,7 @@ #define BIT_GET_PIFS_8821C(x) (((x) >> BIT_SHIFT_PIFS_8821C) & BIT_MASK_PIFS_8821C) + /* 2 REG_RDG_PIFS_8821C */ #define BIT_SHIFT_RDG_PIFS_8821C 0 @@ -6472,6 +7261,7 @@ #define BIT_GET_RDG_PIFS_8821C(x) (((x) >> BIT_SHIFT_RDG_PIFS_8821C) & BIT_MASK_RDG_PIFS_8821C) + /* 2 REG_SIFS_8821C */ #define BIT_SHIFT_SIFS_OFDM_TRX_8821C 24 @@ -6480,24 +7270,28 @@ #define BIT_GET_SIFS_OFDM_TRX_8821C(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8821C) & BIT_MASK_SIFS_OFDM_TRX_8821C) + #define BIT_SHIFT_SIFS_CCK_TRX_8821C 16 #define BIT_MASK_SIFS_CCK_TRX_8821C 0xff #define BIT_SIFS_CCK_TRX_8821C(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8821C) << BIT_SHIFT_SIFS_CCK_TRX_8821C) #define BIT_GET_SIFS_CCK_TRX_8821C(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8821C) & BIT_MASK_SIFS_CCK_TRX_8821C) + #define BIT_SHIFT_SIFS_OFDM_CTX_8821C 8 #define BIT_MASK_SIFS_OFDM_CTX_8821C 0xff #define BIT_SIFS_OFDM_CTX_8821C(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8821C) << BIT_SHIFT_SIFS_OFDM_CTX_8821C) #define BIT_GET_SIFS_OFDM_CTX_8821C(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8821C) & BIT_MASK_SIFS_OFDM_CTX_8821C) + #define BIT_SHIFT_SIFS_CCK_CTX_8821C 0 #define BIT_MASK_SIFS_CCK_CTX_8821C 0xff #define BIT_SIFS_CCK_CTX_8821C(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8821C) << BIT_SHIFT_SIFS_CCK_CTX_8821C) #define BIT_GET_SIFS_CCK_CTX_8821C(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8821C) & BIT_MASK_SIFS_CCK_CTX_8821C) + /* 2 REG_TSFTR_SYN_OFFSET_8821C */ #define BIT_SHIFT_TSFTR_SNC_OFFSET_8821C 0 @@ -6506,6 +7300,7 @@ #define BIT_GET_TSFTR_SNC_OFFSET_8821C(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) & BIT_MASK_TSFTR_SNC_OFFSET_8821C) + /* 2 REG_AGGR_BREAK_TIME_8821C */ #define BIT_SHIFT_AGGR_BK_TIME_8821C 0 @@ -6514,6 +7309,7 @@ #define BIT_GET_AGGR_BK_TIME_8821C(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8821C) & BIT_MASK_AGGR_BK_TIME_8821C) + /* 2 REG_SLOT_8821C */ #define BIT_SHIFT_SLOT_8821C 0 @@ -6522,6 +7318,9 @@ #define BIT_GET_SLOT_8821C(x) (((x) >> BIT_SHIFT_SLOT_8821C) & BIT_MASK_SLOT_8821C) + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_TX_PTCL_CTRL_8821C */ #define BIT_DIS_EDCCA_8821C BIT(15) #define BIT_DIS_CCA_8821C BIT(14) @@ -6533,6 +7332,7 @@ #define BIT_TXQ_NAV_MSK_8821C(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8821C) << BIT_SHIFT_TXQ_NAV_MSK_8821C) #define BIT_GET_TXQ_NAV_MSK_8821C(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8821C) & BIT_MASK_TXQ_NAV_MSK_8821C) + #define BIT_DIS_CW_8821C BIT(7) #define BIT_NAV_END_TXOP_8821C BIT(6) #define BIT_RDG_END_TXOP_8821C BIT(5) @@ -6611,12 +7411,14 @@ #define BIT_GET_CCA_FILTER_THRS_8821C(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8821C) & BIT_MASK_CCA_FILTER_THRS_8821C) + #define BIT_SHIFT_EDCCA_THRS_8821C 0 #define BIT_MASK_EDCCA_THRS_8821C 0xff #define BIT_EDCCA_THRS_8821C(x) (((x) & BIT_MASK_EDCCA_THRS_8821C) << BIT_SHIFT_EDCCA_THRS_8821C) #define BIT_GET_EDCCA_THRS_8821C(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8821C) & BIT_MASK_EDCCA_THRS_8821C) + /* 2 REG_P2PPS_SPEC_STATE_8821C */ #define BIT_SPEC_POWER_STATE_8821C BIT(7) #define BIT_SPEC_CTWINDOW_ON_8821C BIT(6) @@ -6627,6 +7429,8 @@ #define BIT_SPEC_NOA0_OFF_PERIOD_8821C BIT(1) #define BIT_SPEC_FORCE_DOZE0_8821C BIT(0) +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_BAR_TX_CTRL_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -6637,6 +7441,17 @@ #define BIT_GET_P2PON_DIS_TXTIME_8821C(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8821C) & BIT_MASK_P2PON_DIS_TXTIME_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_TBTT_PROHIBIT_8821C */ #define BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C 8 @@ -6645,12 +7460,14 @@ #define BIT_GET_TBTT_HOLD_TIME_AP_8821C(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C) + #define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C 0 #define BIT_MASK_TBTT_PROHIBIT_SETUP_8821C 0xf #define BIT_TBTT_PROHIBIT_SETUP_8821C(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) #define BIT_GET_TBTT_PROHIBIT_SETUP_8821C(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) + /* 2 REG_P2PPS_STATE_8821C */ #define BIT_POWER_STATE_8821C BIT(7) #define BIT_CTWINDOW_ON_8821C BIT(6) @@ -6669,6 +7486,7 @@ #define BIT_GET_RD_NAV_PROT_NXT_8821C(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8821C) & BIT_MASK_RD_NAV_PROT_NXT_8821C) + /* 2 REG_NAV_PROT_LEN_8821C */ #define BIT_SHIFT_NAV_PROT_LEN_8821C 0 @@ -6677,6 +7495,11 @@ #define BIT_GET_NAV_PROT_LEN_8821C(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8821C) & BIT_MASK_NAV_PROT_LEN_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_BCN_CTRL_8821C */ #define BIT_DIS_RX_BSSID_FIT_8821C BIT(6) #define BIT_P0_EN_TXBCN_RPT_8821C BIT(5) @@ -6703,6 +7526,7 @@ #define BIT_GET_MBID_BCN_NUM_8821C(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8821C) & BIT_MASK_MBID_BCN_NUM_8821C) + /* 2 REG_DUAL_TSF_RST_8821C */ #define BIT_FREECNT_RST_8821C BIT(5) #define BIT_TSFTR_CLI3_RST_8821C BIT(4) @@ -6719,18 +7543,21 @@ #define BIT_GET_BCN_TIMER_SEL_FWRD_8821C(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) + #define BIT_SHIFT_BCN_SPACE_CLINT0_8821C 16 #define BIT_MASK_BCN_SPACE_CLINT0_8821C 0xfff #define BIT_BCN_SPACE_CLINT0_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8821C) << BIT_SHIFT_BCN_SPACE_CLINT0_8821C) #define BIT_GET_BCN_SPACE_CLINT0_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8821C) & BIT_MASK_BCN_SPACE_CLINT0_8821C) + #define BIT_SHIFT_BCN_SPACE0_8821C 0 #define BIT_MASK_BCN_SPACE0_8821C 0xffff #define BIT_BCN_SPACE0_8821C(x) (((x) & BIT_MASK_BCN_SPACE0_8821C) << BIT_SHIFT_BCN_SPACE0_8821C) #define BIT_GET_BCN_SPACE0_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8821C) & BIT_MASK_BCN_SPACE0_8821C) + /* 2 REG_DRVERLYINT_8821C */ #define BIT_SHIFT_DRVERLYITV_8821C 0 @@ -6739,6 +7566,7 @@ #define BIT_GET_DRVERLYITV_8821C(x) (((x) >> BIT_SHIFT_DRVERLYITV_8821C) & BIT_MASK_DRVERLYITV_8821C) + /* 2 REG_BCNDMATIM_8821C */ #define BIT_SHIFT_BCNDMATIM_8821C 0 @@ -6747,6 +7575,7 @@ #define BIT_GET_BCNDMATIM_8821C(x) (((x) >> BIT_SHIFT_BCNDMATIM_8821C) & BIT_MASK_BCNDMATIM_8821C) + /* 2 REG_ATIMWND_8821C */ #define BIT_SHIFT_ATIMWND0_8821C 0 @@ -6755,6 +7584,7 @@ #define BIT_GET_ATIMWND0_8821C(x) (((x) >> BIT_SHIFT_ATIMWND0_8821C) & BIT_MASK_ATIMWND0_8821C) + /* 2 REG_USTIME_TSF_8821C */ #define BIT_SHIFT_USTIME_TSF_V1_8821C 0 @@ -6763,6 +7593,7 @@ #define BIT_GET_USTIME_TSF_V1_8821C(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8821C) & BIT_MASK_USTIME_TSF_V1_8821C) + /* 2 REG_BCN_MAX_ERR_8821C */ #define BIT_SHIFT_BCN_MAX_ERR_8821C 0 @@ -6771,6 +7602,7 @@ #define BIT_GET_BCN_MAX_ERR_8821C(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8821C) & BIT_MASK_BCN_MAX_ERR_8821C) + /* 2 REG_RXTSF_OFFSET_CCK_8821C */ #define BIT_SHIFT_CCK_RXTSF_OFFSET_8821C 0 @@ -6779,6 +7611,7 @@ #define BIT_GET_CCK_RXTSF_OFFSET_8821C(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) & BIT_MASK_CCK_RXTSF_OFFSET_8821C) + /* 2 REG_RXTSF_OFFSET_OFDM_8821C */ #define BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C 0 @@ -6787,20 +7620,41 @@ #define BIT_GET_OFDM_RXTSF_OFFSET_8821C(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C) + /* 2 REG_TSFTR_8821C */ -#define BIT_SHIFT_TSF_TIMER_8821C 0 -#define BIT_MASK_TSF_TIMER_8821C 0xffffffffffffffffL -#define BIT_TSF_TIMER_8821C(x) (((x) & BIT_MASK_TSF_TIMER_8821C) << BIT_SHIFT_TSF_TIMER_8821C) -#define BIT_GET_TSF_TIMER_8821C(x) (((x) >> BIT_SHIFT_TSF_TIMER_8821C) & BIT_MASK_TSF_TIMER_8821C) +#define BIT_SHIFT_TSF_TIMER_V1_8821C 0 +#define BIT_MASK_TSF_TIMER_V1_8821C 0xffffffffL +#define BIT_TSF_TIMER_V1_8821C(x) (((x) & BIT_MASK_TSF_TIMER_V1_8821C) << BIT_SHIFT_TSF_TIMER_V1_8821C) +#define BIT_GET_TSF_TIMER_V1_8821C(x) (((x) >> BIT_SHIFT_TSF_TIMER_V1_8821C) & BIT_MASK_TSF_TIMER_V1_8821C) + + + +/* 2 REG_TSFTR_1_8821C */ + +#define BIT_SHIFT_TSF_TIMER_V2_8821C 0 +#define BIT_MASK_TSF_TIMER_V2_8821C 0xffffffffL +#define BIT_TSF_TIMER_V2_8821C(x) (((x) & BIT_MASK_TSF_TIMER_V2_8821C) << BIT_SHIFT_TSF_TIMER_V2_8821C) +#define BIT_GET_TSF_TIMER_V2_8821C(x) (((x) >> BIT_SHIFT_TSF_TIMER_V2_8821C) & BIT_MASK_TSF_TIMER_V2_8821C) + /* 2 REG_FREERUN_CNT_8821C */ -#define BIT_SHIFT_FREERUN_CNT_8821C 0 -#define BIT_MASK_FREERUN_CNT_8821C 0xffffffffffffffffL -#define BIT_FREERUN_CNT_8821C(x) (((x) & BIT_MASK_FREERUN_CNT_8821C) << BIT_SHIFT_FREERUN_CNT_8821C) -#define BIT_GET_FREERUN_CNT_8821C(x) (((x) >> BIT_SHIFT_FREERUN_CNT_8821C) & BIT_MASK_FREERUN_CNT_8821C) +#define BIT_SHIFT_FREERUN_CNT_V1_8821C 0 +#define BIT_MASK_FREERUN_CNT_V1_8821C 0xffffffffL +#define BIT_FREERUN_CNT_V1_8821C(x) (((x) & BIT_MASK_FREERUN_CNT_V1_8821C) << BIT_SHIFT_FREERUN_CNT_V1_8821C) +#define BIT_GET_FREERUN_CNT_V1_8821C(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8821C) & BIT_MASK_FREERUN_CNT_V1_8821C) + + + +/* 2 REG_FREERUN_CNT_1_8821C */ + +#define BIT_SHIFT_FREERUN_CNT_V2_8821C 0 +#define BIT_MASK_FREERUN_CNT_V2_8821C 0xffffffffL +#define BIT_FREERUN_CNT_V2_8821C(x) (((x) & BIT_MASK_FREERUN_CNT_V2_8821C) << BIT_SHIFT_FREERUN_CNT_V2_8821C) +#define BIT_GET_FREERUN_CNT_V2_8821C(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8821C) & BIT_MASK_FREERUN_CNT_V2_8821C) + /* 2 REG_ATIMWND1_V1_8821C */ @@ -6811,6 +7665,7 @@ #define BIT_GET_ATIMWND1_V1_8821C(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8821C) & BIT_MASK_ATIMWND1_V1_8821C) + /* 2 REG_TBTT_PROHIBIT_INFRA_8821C */ #define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C 0 @@ -6819,6 +7674,7 @@ #define BIT_GET_TBTT_PROHIBIT_INFRA_8821C(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) + /* 2 REG_CTWND_8821C */ #define BIT_SHIFT_CTWND_8821C 0 @@ -6827,6 +7683,7 @@ #define BIT_GET_CTWND_8821C(x) (((x) >> BIT_SHIFT_CTWND_8821C) & BIT_MASK_CTWND_8821C) + /* 2 REG_BCNIVLCUNT_8821C */ #define BIT_SHIFT_BCNIVLCUNT_8821C 0 @@ -6835,6 +7692,7 @@ #define BIT_GET_BCNIVLCUNT_8821C(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8821C) & BIT_MASK_BCNIVLCUNT_8821C) + /* 2 REG_BCNDROPCTRL_8821C */ #define BIT_BEACON_DROP_EN_8821C BIT(7) @@ -6844,6 +7702,7 @@ #define BIT_GET_BEACON_DROP_IVL_8821C(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8821C) & BIT_MASK_BEACON_DROP_IVL_8821C) + /* 2 REG_HGQ_TIMEOUT_PERIOD_8821C */ #define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C 0 @@ -6852,6 +7711,7 @@ #define BIT_GET_HGQ_TIMEOUT_PERIOD_8821C(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) + /* 2 REG_TXCMD_TIMEOUT_PERIOD_8821C */ #define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C 0 @@ -6860,6 +7720,7 @@ #define BIT_GET_TXCMD_TIMEOUT_PERIOD_8821C(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) + /* 2 REG_MISC_CTRL_8821C */ #define BIT_DIS_TRX_CAL_BCN_8821C BIT(5) #define BIT_DIS_TX_CAL_TBTT_8821C BIT(4) @@ -6872,6 +7733,7 @@ #define BIT_GET_DIS_SECONDARY_CCA_8821C(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8821C) & BIT_MASK_DIS_SECONDARY_CCA_8821C) + /* 2 REG_BCN_CTRL_CLINT1_8821C */ #define BIT_CLI1_DIS_RX_BSSID_FIT_8821C BIT(6) #define BIT_CLI1_DIS_TSF_UDT_8821C BIT(4) @@ -6906,6 +7768,7 @@ #define BIT_GET_PORT_SEL_8821C(x) (((x) >> BIT_SHIFT_PORT_SEL_8821C) & BIT_MASK_PORT_SEL_8821C) + /* 2 REG_P2PPS1_SPEC_STATE_8821C */ #define BIT_P2P1_SPEC_POWER_STATE_8821C BIT(7) #define BIT_P2P1_SPEC_CTWINDOW_ON_8821C BIT(6) @@ -6954,6 +7817,7 @@ #define BIT_GET_PSTIMER0_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8821C) & BIT_MASK_PSTIMER0_INT_8821C) + /* 2 REG_PS_TIMER1_8821C */ #define BIT_SHIFT_PSTIMER1_INT_8821C 5 @@ -6962,6 +7826,7 @@ #define BIT_GET_PSTIMER1_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8821C) & BIT_MASK_PSTIMER1_INT_8821C) + /* 2 REG_PS_TIMER2_8821C */ #define BIT_SHIFT_PSTIMER2_INT_8821C 5 @@ -6970,6 +7835,7 @@ #define BIT_GET_PSTIMER2_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8821C) & BIT_MASK_PSTIMER2_INT_8821C) + /* 2 REG_TBTT_CTN_AREA_8821C */ #define BIT_SHIFT_TBTT_CTN_AREA_8821C 0 @@ -6978,6 +7844,9 @@ #define BIT_GET_TBTT_CTN_AREA_8821C(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8821C) & BIT_MASK_TBTT_CTN_AREA_8821C) + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_FORCE_BCN_IFS_8821C */ #define BIT_SHIFT_FORCE_BCN_IFS_8821C 0 @@ -6986,6 +7855,9 @@ #define BIT_GET_FORCE_BCN_IFS_8821C(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8821C) & BIT_MASK_FORCE_BCN_IFS_8821C) + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_TXOP_MIN_8821C */ #define BIT_SHIFT_TXOP_MIN_8821C 0 @@ -6994,6 +7866,7 @@ #define BIT_GET_TXOP_MIN_8821C(x) (((x) >> BIT_SHIFT_TXOP_MIN_8821C) & BIT_MASK_TXOP_MIN_8821C) + /* 2 REG_PRE_BKF_TIME_8821C */ #define BIT_SHIFT_PRE_BKF_TIME_8821C 0 @@ -7002,12 +7875,19 @@ #define BIT_GET_PRE_BKF_TIME_8821C(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8821C) & BIT_MASK_PRE_BKF_TIME_8821C) + /* 2 REG_CROSS_TXOP_CTRL_8821C */ #define BIT_TXFAIL_BREACK_TXOP_EN_8821C BIT(3) #define BIT_DTIM_BYPASS_8821C BIT(2) #define BIT_RTS_NAV_TXOP_8821C BIT(1) #define BIT_NOT_CROSS_TXOP_8821C BIT(0) +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_ATIMWND2_8821C */ #define BIT_SHIFT_ATIMWND2_8821C 0 @@ -7016,6 +7896,7 @@ #define BIT_GET_ATIMWND2_8821C(x) (((x) >> BIT_SHIFT_ATIMWND2_8821C) & BIT_MASK_ATIMWND2_8821C) + /* 2 REG_ATIMWND3_8821C */ #define BIT_SHIFT_ATIMWND3_8821C 0 @@ -7024,6 +7905,7 @@ #define BIT_GET_ATIMWND3_8821C(x) (((x) >> BIT_SHIFT_ATIMWND3_8821C) & BIT_MASK_ATIMWND3_8821C) + /* 2 REG_ATIMWND4_8821C */ #define BIT_SHIFT_ATIMWND4_8821C 0 @@ -7032,6 +7914,7 @@ #define BIT_GET_ATIMWND4_8821C(x) (((x) >> BIT_SHIFT_ATIMWND4_8821C) & BIT_MASK_ATIMWND4_8821C) + /* 2 REG_ATIMWND5_8821C */ #define BIT_SHIFT_ATIMWND5_8821C 0 @@ -7040,6 +7923,7 @@ #define BIT_GET_ATIMWND5_8821C(x) (((x) >> BIT_SHIFT_ATIMWND5_8821C) & BIT_MASK_ATIMWND5_8821C) + /* 2 REG_ATIMWND6_8821C */ #define BIT_SHIFT_ATIMWND6_8821C 0 @@ -7048,6 +7932,7 @@ #define BIT_GET_ATIMWND6_8821C(x) (((x) >> BIT_SHIFT_ATIMWND6_8821C) & BIT_MASK_ATIMWND6_8821C) + /* 2 REG_ATIMWND7_8821C */ #define BIT_SHIFT_ATIMWND7_8821C 0 @@ -7056,6 +7941,7 @@ #define BIT_GET_ATIMWND7_8821C(x) (((x) >> BIT_SHIFT_ATIMWND7_8821C) & BIT_MASK_ATIMWND7_8821C) + /* 2 REG_ATIMUGT_8821C */ #define BIT_SHIFT_ATIM_URGENT_8821C 0 @@ -7064,6 +7950,7 @@ #define BIT_GET_ATIM_URGENT_8821C(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8821C) & BIT_MASK_ATIM_URGENT_8821C) + /* 2 REG_HIQ_NO_LMT_EN_8821C */ #define BIT_HIQ_NO_LMT_EN_VAP7_8821C BIT(7) #define BIT_HIQ_NO_LMT_EN_VAP6_8821C BIT(6) @@ -7082,6 +7969,7 @@ #define BIT_GET_DTIM_COUNT_ROOT_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8821C) & BIT_MASK_DTIM_COUNT_ROOT_8821C) + /* 2 REG_DTIM_COUNTER_VAP1_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP1_8821C 0 @@ -7090,6 +7978,7 @@ #define BIT_GET_DTIM_COUNT_VAP1_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8821C) & BIT_MASK_DTIM_COUNT_VAP1_8821C) + /* 2 REG_DTIM_COUNTER_VAP2_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP2_8821C 0 @@ -7098,6 +7987,7 @@ #define BIT_GET_DTIM_COUNT_VAP2_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8821C) & BIT_MASK_DTIM_COUNT_VAP2_8821C) + /* 2 REG_DTIM_COUNTER_VAP3_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP3_8821C 0 @@ -7106,6 +7996,7 @@ #define BIT_GET_DTIM_COUNT_VAP3_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8821C) & BIT_MASK_DTIM_COUNT_VAP3_8821C) + /* 2 REG_DTIM_COUNTER_VAP4_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP4_8821C 0 @@ -7114,6 +8005,7 @@ #define BIT_GET_DTIM_COUNT_VAP4_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8821C) & BIT_MASK_DTIM_COUNT_VAP4_8821C) + /* 2 REG_DTIM_COUNTER_VAP5_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP5_8821C 0 @@ -7122,6 +8014,7 @@ #define BIT_GET_DTIM_COUNT_VAP5_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8821C) & BIT_MASK_DTIM_COUNT_VAP5_8821C) + /* 2 REG_DTIM_COUNTER_VAP6_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP6_8821C 0 @@ -7130,6 +8023,7 @@ #define BIT_GET_DTIM_COUNT_VAP6_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8821C) & BIT_MASK_DTIM_COUNT_VAP6_8821C) + /* 2 REG_DTIM_COUNTER_VAP7_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP7_8821C 0 @@ -7138,6 +8032,7 @@ #define BIT_GET_DTIM_COUNT_VAP7_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8821C) & BIT_MASK_DTIM_COUNT_VAP7_8821C) + /* 2 REG_DIS_ATIM_8821C */ #define BIT_DIS_ATIM_VAP7_8821C BIT(7) #define BIT_DIS_ATIM_VAP6_8821C BIT(6) @@ -7156,12 +8051,14 @@ #define BIT_GET_TSFT_SEL_TIMER1_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8821C) & BIT_MASK_TSFT_SEL_TIMER1_8821C) + #define BIT_SHIFT_EARLY_128US_8821C 0 #define BIT_MASK_EARLY_128US_8821C 0x7 #define BIT_EARLY_128US_8821C(x) (((x) & BIT_MASK_EARLY_128US_8821C) << BIT_SHIFT_EARLY_128US_8821C) #define BIT_GET_EARLY_128US_8821C(x) (((x) >> BIT_SHIFT_EARLY_128US_8821C) & BIT_MASK_EARLY_128US_8821C) + /* 2 REG_P2PPS1_CTRL_8821C */ #define BIT_P2P1_CTW_ALLSTASLEEP_8821C BIT(7) #define BIT_P2P1_OFF_DISTX_EN_8821C BIT(6) @@ -7184,12 +8081,14 @@ #define BIT_GET_SYNC_CLI_SEL_8821C(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8821C) & BIT_MASK_SYNC_CLI_SEL_8821C) + #define BIT_SHIFT_TSFT_SEL_TIMER0_8821C 0 #define BIT_MASK_TSFT_SEL_TIMER0_8821C 0x7 #define BIT_TSFT_SEL_TIMER0_8821C(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8821C) << BIT_SHIFT_TSFT_SEL_TIMER0_8821C) #define BIT_GET_TSFT_SEL_TIMER0_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8821C) & BIT_MASK_TSFT_SEL_TIMER0_8821C) + /* 2 REG_NOA_UNIT_SEL_8821C */ #define BIT_SHIFT_NOA_UNIT2_SEL_8821C 8 @@ -7198,18 +8097,21 @@ #define BIT_GET_NOA_UNIT2_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8821C) & BIT_MASK_NOA_UNIT2_SEL_8821C) + #define BIT_SHIFT_NOA_UNIT1_SEL_8821C 4 #define BIT_MASK_NOA_UNIT1_SEL_8821C 0x7 #define BIT_NOA_UNIT1_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8821C) << BIT_SHIFT_NOA_UNIT1_SEL_8821C) #define BIT_GET_NOA_UNIT1_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8821C) & BIT_MASK_NOA_UNIT1_SEL_8821C) + #define BIT_SHIFT_NOA_UNIT0_SEL_8821C 0 #define BIT_MASK_NOA_UNIT0_SEL_8821C 0x7 #define BIT_NOA_UNIT0_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8821C) << BIT_SHIFT_NOA_UNIT0_SEL_8821C) #define BIT_GET_NOA_UNIT0_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8821C) & BIT_MASK_NOA_UNIT0_SEL_8821C) + /* 2 REG_P2POFF_DIS_TXTIME_8821C */ #define BIT_SHIFT_P2POFF_DIS_TXTIME_8821C 0 @@ -7218,6 +8120,7 @@ #define BIT_GET_P2POFF_DIS_TXTIME_8821C(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) & BIT_MASK_P2POFF_DIS_TXTIME_8821C) + /* 2 REG_MBSSID_BCN_SPACE2_8821C */ #define BIT_SHIFT_BCN_SPACE_CLINT2_8821C 16 @@ -7226,12 +8129,14 @@ #define BIT_GET_BCN_SPACE_CLINT2_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8821C) & BIT_MASK_BCN_SPACE_CLINT2_8821C) + #define BIT_SHIFT_BCN_SPACE_CLINT1_8821C 0 #define BIT_MASK_BCN_SPACE_CLINT1_8821C 0xfff #define BIT_BCN_SPACE_CLINT1_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8821C) << BIT_SHIFT_BCN_SPACE_CLINT1_8821C) #define BIT_GET_BCN_SPACE_CLINT1_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8821C) & BIT_MASK_BCN_SPACE_CLINT1_8821C) + /* 2 REG_MBSSID_BCN_SPACE3_8821C */ #define BIT_SHIFT_SUB_BCN_SPACE_8821C 16 @@ -7240,12 +8145,14 @@ #define BIT_GET_SUB_BCN_SPACE_8821C(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8821C) & BIT_MASK_SUB_BCN_SPACE_8821C) + #define BIT_SHIFT_BCN_SPACE_CLINT3_8821C 0 #define BIT_MASK_BCN_SPACE_CLINT3_8821C 0xfff #define BIT_BCN_SPACE_CLINT3_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8821C) << BIT_SHIFT_BCN_SPACE_CLINT3_8821C) #define BIT_GET_BCN_SPACE_CLINT3_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8821C) & BIT_MASK_BCN_SPACE_CLINT3_8821C) + /* 2 REG_ACMHWCTRL_8821C */ #define BIT_BEQ_ACM_STATUS_8821C BIT(7) #define BIT_VIQ_ACM_STATUS_8821C BIT(6) @@ -7268,6 +8175,7 @@ #define BIT_GET_AVGPERIOD_8821C(x) (((x) >> BIT_SHIFT_AVGPERIOD_8821C) & BIT_MASK_AVGPERIOD_8821C) + /* 2 REG_VO_ADMTIME_8821C */ #define BIT_SHIFT_VO_ADMITTED_TIME_8821C 0 @@ -7276,6 +8184,7 @@ #define BIT_GET_VO_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8821C) & BIT_MASK_VO_ADMITTED_TIME_8821C) + /* 2 REG_VI_ADMTIME_8821C */ #define BIT_SHIFT_VI_ADMITTED_TIME_8821C 0 @@ -7284,6 +8193,7 @@ #define BIT_GET_VI_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8821C) & BIT_MASK_VI_ADMITTED_TIME_8821C) + /* 2 REG_BE_ADMTIME_8821C */ #define BIT_SHIFT_BE_ADMITTED_TIME_8821C 0 @@ -7292,6 +8202,11 @@ #define BIT_GET_BE_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8821C) & BIT_MASK_BE_ADMITTED_TIME_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_EDCA_RANDOM_GEN_8821C */ #define BIT_SHIFT_RANDOM_GEN_8821C 0 @@ -7300,6 +8215,7 @@ #define BIT_GET_RANDOM_GEN_8821C(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8821C) & BIT_MASK_RANDOM_GEN_8821C) + /* 2 REG_TXCMD_NOA_SEL_8821C */ #define BIT_SHIFT_NOA_SEL_8821C 4 @@ -7308,39 +8224,57 @@ #define BIT_GET_NOA_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_SEL_8821C) & BIT_MASK_NOA_SEL_8821C) + #define BIT_SHIFT_TXCMD_SEG_SEL_8821C 0 #define BIT_MASK_TXCMD_SEG_SEL_8821C 0xf #define BIT_TXCMD_SEG_SEL_8821C(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8821C) << BIT_SHIFT_TXCMD_SEG_SEL_8821C) #define BIT_GET_TXCMD_SEG_SEL_8821C(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8821C) & BIT_MASK_TXCMD_SEG_SEL_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_NOA_PARAM_8821C */ -#define BIT_SHIFT_NOA_COUNT_8821C (96 & CPU_OPT_WIDTH) -#define BIT_MASK_NOA_COUNT_8821C 0xff -#define BIT_NOA_COUNT_8821C(x) (((x) & BIT_MASK_NOA_COUNT_8821C) << BIT_SHIFT_NOA_COUNT_8821C) -#define BIT_GET_NOA_COUNT_8821C(x) (((x) >> BIT_SHIFT_NOA_COUNT_8821C) & BIT_MASK_NOA_COUNT_8821C) +#define BIT_SHIFT_NOA_DURATION_V1_8821C 0 +#define BIT_MASK_NOA_DURATION_V1_8821C 0xffffffffL +#define BIT_NOA_DURATION_V1_8821C(x) (((x) & BIT_MASK_NOA_DURATION_V1_8821C) << BIT_SHIFT_NOA_DURATION_V1_8821C) +#define BIT_GET_NOA_DURATION_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_DURATION_V1_8821C) & BIT_MASK_NOA_DURATION_V1_8821C) -#define BIT_SHIFT_NOA_START_TIME_8821C (64 & CPU_OPT_WIDTH) -#define BIT_MASK_NOA_START_TIME_8821C 0xffffffffL -#define BIT_NOA_START_TIME_8821C(x) (((x) & BIT_MASK_NOA_START_TIME_8821C) << BIT_SHIFT_NOA_START_TIME_8821C) -#define BIT_GET_NOA_START_TIME_8821C(x) (((x) >> BIT_SHIFT_NOA_START_TIME_8821C) & BIT_MASK_NOA_START_TIME_8821C) +/* 2 REG_NOA_PARAM_1_8821C */ -#define BIT_SHIFT_NOA_INTERVAL_8821C (32 & CPU_OPT_WIDTH) -#define BIT_MASK_NOA_INTERVAL_8821C 0xffffffffL -#define BIT_NOA_INTERVAL_8821C(x) (((x) & BIT_MASK_NOA_INTERVAL_8821C) << BIT_SHIFT_NOA_INTERVAL_8821C) -#define BIT_GET_NOA_INTERVAL_8821C(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_8821C) & BIT_MASK_NOA_INTERVAL_8821C) +#define BIT_SHIFT_NOA_INTERVAL_V1_8821C 0 +#define BIT_MASK_NOA_INTERVAL_V1_8821C 0xffffffffL +#define BIT_NOA_INTERVAL_V1_8821C(x) (((x) & BIT_MASK_NOA_INTERVAL_V1_8821C) << BIT_SHIFT_NOA_INTERVAL_V1_8821C) +#define BIT_GET_NOA_INTERVAL_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8821C) & BIT_MASK_NOA_INTERVAL_V1_8821C) -#define BIT_SHIFT_NOA_DURATION_8821C 0 -#define BIT_MASK_NOA_DURATION_8821C 0xffffffffL -#define BIT_NOA_DURATION_8821C(x) (((x) & BIT_MASK_NOA_DURATION_8821C) << BIT_SHIFT_NOA_DURATION_8821C) -#define BIT_GET_NOA_DURATION_8821C(x) (((x) >> BIT_SHIFT_NOA_DURATION_8821C) & BIT_MASK_NOA_DURATION_8821C) + +/* 2 REG_NOA_PARAM_2_8821C */ + +#define BIT_SHIFT_NOA_START_TIME_V1_8821C 0 +#define BIT_MASK_NOA_START_TIME_V1_8821C 0xffffffffL +#define BIT_NOA_START_TIME_V1_8821C(x) (((x) & BIT_MASK_NOA_START_TIME_V1_8821C) << BIT_SHIFT_NOA_START_TIME_V1_8821C) +#define BIT_GET_NOA_START_TIME_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8821C) & BIT_MASK_NOA_START_TIME_V1_8821C) + + + +/* 2 REG_NOA_PARAM_3_8821C */ + +#define BIT_SHIFT_NOA_COUNT_V1_8821C 0 +#define BIT_MASK_NOA_COUNT_V1_8821C 0xffffffffL +#define BIT_NOA_COUNT_V1_8821C(x) (((x) & BIT_MASK_NOA_COUNT_V1_8821C) << BIT_SHIFT_NOA_COUNT_V1_8821C) +#define BIT_GET_NOA_COUNT_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_COUNT_V1_8821C) & BIT_MASK_NOA_COUNT_V1_8821C) -/* 2 REG_NOT_VALID_8821C */ /* 2 REG_P2P_RST_8821C */ #define BIT_P2P2_PWR_RST1_8821C BIT(5) @@ -7354,6 +8288,12 @@ #define BIT_SYNC_CLI_8821C BIT(1) #define BIT_SCHEDULER_RST_V1_8821C BIT(0) +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_SCH_TXCMD_8821C */ #define BIT_SHIFT_SCH_TXCMD_8821C 0 @@ -7362,6 +8302,7 @@ #define BIT_GET_SCH_TXCMD_8821C(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8821C) & BIT_MASK_SCH_TXCMD_8821C) + /* 2 REG_PAGE5_DUMMY_8821C */ /* 2 REG_CPUMGQ_TX_TIMER_8821C */ @@ -7372,6 +8313,7 @@ #define BIT_GET_CPUMGQ_TX_TIMER_V1_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) + /* 2 REG_PS_TIMER_A_8821C */ #define BIT_SHIFT_PS_TIMER_A_V1_8821C 0 @@ -7380,6 +8322,7 @@ #define BIT_GET_PS_TIMER_A_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8821C) & BIT_MASK_PS_TIMER_A_V1_8821C) + /* 2 REG_PS_TIMER_B_8821C */ #define BIT_SHIFT_PS_TIMER_B_V1_8821C 0 @@ -7388,6 +8331,7 @@ #define BIT_GET_PS_TIMER_B_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8821C) & BIT_MASK_PS_TIMER_B_V1_8821C) + /* 2 REG_PS_TIMER_C_8821C */ #define BIT_SHIFT_PS_TIMER_C_V1_8821C 0 @@ -7396,6 +8340,7 @@ #define BIT_GET_PS_TIMER_C_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8821C) & BIT_MASK_PS_TIMER_C_V1_8821C) + /* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8821C */ #define BIT_CPUMGQ_TIMER_EN_8821C BIT(31) #define BIT_CPUMGQ_TX_EN_8821C BIT(28) @@ -7405,6 +8350,7 @@ #define BIT_CPUMGQ_TIMER_TSF_SEL_8821C(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) #define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) + #define BIT_PS_TIMER_C_EN_8821C BIT(23) #define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C 16 @@ -7412,6 +8358,7 @@ #define BIT_PS_TIMER_C_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) #define BIT_GET_PS_TIMER_C_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) + #define BIT_PS_TIMER_B_EN_8821C BIT(15) #define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C 8 @@ -7419,6 +8366,7 @@ #define BIT_PS_TIMER_B_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) #define BIT_GET_PS_TIMER_B_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) + #define BIT_PS_TIMER_A_EN_8821C BIT(7) #define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C 0 @@ -7427,6 +8375,7 @@ #define BIT_GET_PS_TIMER_A_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) + /* 2 REG_CPUMGQ_TX_TIMER_EARLY_8821C */ #define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C 0 @@ -7435,6 +8384,7 @@ #define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) + /* 2 REG_PS_TIMER_A_EARLY_8821C */ #define BIT_SHIFT_PS_TIMER_A_EARLY_8821C 0 @@ -7443,6 +8393,7 @@ #define BIT_GET_PS_TIMER_A_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8821C) & BIT_MASK_PS_TIMER_A_EARLY_8821C) + /* 2 REG_PS_TIMER_B_EARLY_8821C */ #define BIT_SHIFT_PS_TIMER_B_EARLY_8821C 0 @@ -7451,6 +8402,7 @@ #define BIT_GET_PS_TIMER_B_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8821C) & BIT_MASK_PS_TIMER_B_EARLY_8821C) + /* 2 REG_PS_TIMER_C_EARLY_8821C */ #define BIT_SHIFT_PS_TIMER_C_EARLY_8821C 0 @@ -7459,6 +8411,123 @@ #define BIT_GET_PS_TIMER_C_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8821C) & BIT_MASK_PS_TIMER_C_EARLY_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_BWOPMODE_8821C (BW OPERATION MODE REGISTER) */ @@ -7475,6 +8544,7 @@ #define BIT_GET_APPEND_MHDR_LEN_8821C(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8821C) & BIT_MASK_APPEND_MHDR_LEN_8821C) + /* 2 REG_FW_STS_FILTER_8821C */ #define BIT_DATA_FW_STS_FILTER_8821C BIT(2) #define BIT_CTRL_FW_STS_FILTER_8821C BIT(1) @@ -7555,6 +8625,7 @@ #define BIT_GET_DRVINFO_SZ_V1_8821C(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8821C) & BIT_MASK_DRVINFO_SZ_V1_8821C) + /* 2 REG_RX_DLK_TIME_8821C (RX DEADLOCK TIME REGISTER) */ #define BIT_SHIFT_RX_DLK_TIME_8821C 0 @@ -7563,6 +8634,7 @@ #define BIT_GET_RX_DLK_TIME_8821C(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8821C) & BIT_MASK_RX_DLK_TIME_8821C) + /* 2 REG_RX_PKT_LIMIT_8821C (RX PACKET LENGTH LIMIT REGISTER) */ #define BIT_SHIFT_RXPKTLMT_8821C 0 @@ -7571,6 +8643,7 @@ #define BIT_GET_RXPKTLMT_8821C(x) (((x) >> BIT_SHIFT_RXPKTLMT_8821C) & BIT_MASK_RXPKTLMT_8821C) + /* 2 REG_MACID_8821C (MAC ID REGISTER) */ #define BIT_SHIFT_MACID_8821C 0 @@ -7579,6 +8652,7 @@ #define BIT_GET_MACID_8821C(x) (((x) >> BIT_SHIFT_MACID_8821C) & BIT_MASK_MACID_8821C) + /* 2 REG_BSSID_8821C (BSSID REGISTER) */ #define BIT_SHIFT_BSSID_8821C 0 @@ -7587,6 +8661,7 @@ #define BIT_GET_BSSID_8821C(x) (((x) >> BIT_SHIFT_BSSID_8821C) & BIT_MASK_BSSID_8821C) + /* 2 REG_MAR_8821C (MULTICAST ADDRESS REGISTER) */ #define BIT_SHIFT_MAR_8821C 0 @@ -7595,6 +8670,7 @@ #define BIT_GET_MAR_8821C(x) (((x) >> BIT_SHIFT_MAR_8821C) & BIT_MASK_MAR_8821C) + /* 2 REG_MBIDCAMCFG_1_8821C (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_SHIFT_MBIDCAM_RWDATA_L_8821C 0 @@ -7603,6 +8679,7 @@ #define BIT_GET_MBIDCAM_RWDATA_L_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) & BIT_MASK_MBIDCAM_RWDATA_L_8821C) + /* 2 REG_MBIDCAMCFG_2_8821C (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_MBIDCAM_POLL_8821C BIT(31) #define BIT_MBIDCAM_WT_EN_8821C BIT(30) @@ -7612,6 +8689,7 @@ #define BIT_MBIDCAM_ADDR_8821C(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8821C) << BIT_SHIFT_MBIDCAM_ADDR_8821C) #define BIT_GET_MBIDCAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8821C) & BIT_MASK_MBIDCAM_ADDR_8821C) + #define BIT_MBIDCAM_VALID_8821C BIT(23) #define BIT_LSIC_TXOP_EN_8821C BIT(17) #define BIT_CTS_EN_8821C BIT(16) @@ -7622,6 +8700,7 @@ #define BIT_GET_MBIDCAM_RWDATA_H_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) & BIT_MASK_MBIDCAM_RWDATA_H_8821C) + /* 2 REG_ZLD_NUM_8821C */ #define BIT_SHIFT_ZLD_NUM_8821C 0 @@ -7630,6 +8709,7 @@ #define BIT_GET_ZLD_NUM_8821C(x) (((x) >> BIT_SHIFT_ZLD_NUM_8821C) & BIT_MASK_ZLD_NUM_8821C) + /* 2 REG_UDF_THSD_8821C */ #define BIT_SHIFT_UDF_THSD_8821C 0 @@ -7638,6 +8718,7 @@ #define BIT_GET_UDF_THSD_8821C(x) (((x) >> BIT_SHIFT_UDF_THSD_8821C) & BIT_MASK_UDF_THSD_8821C) + /* 2 REG_WMAC_TCR_TSFT_OFS_8821C */ #define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C 0 @@ -7646,6 +8727,7 @@ #define BIT_GET_WMAC_TCR_TSFT_OFS_8821C(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) + /* 2 REG_MCU_TEST_2_V1_8821C */ #define BIT_SHIFT_MCU_RSVD_2_V1_8821C 0 @@ -7654,6 +8736,7 @@ #define BIT_GET_MCU_RSVD_2_V1_8821C(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8821C) & BIT_MASK_MCU_RSVD_2_V1_8821C) + /* 2 REG_WMAC_TXTIMEOUT_8821C */ #define BIT_SHIFT_WMAC_TXTIMEOUT_8821C 0 @@ -7662,6 +8745,7 @@ #define BIT_GET_WMAC_TXTIMEOUT_8821C(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8821C) & BIT_MASK_WMAC_TXTIMEOUT_8821C) + /* 2 REG_STMP_THSD_8821C */ #define BIT_SHIFT_STMP_THSD_8821C 0 @@ -7670,6 +8754,7 @@ #define BIT_GET_STMP_THSD_8821C(x) (((x) >> BIT_SHIFT_STMP_THSD_8821C) & BIT_MASK_STMP_THSD_8821C) + /* 2 REG_MAC_SPEC_SIFS_8821C (SPECIFICATION SIFS REGISTER) */ #define BIT_SHIFT_SPEC_SIFS_OFDM_8821C 8 @@ -7678,12 +8763,14 @@ #define BIT_GET_SPEC_SIFS_OFDM_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8821C) & BIT_MASK_SPEC_SIFS_OFDM_8821C) + #define BIT_SHIFT_SPEC_SIFS_CCK_8821C 0 #define BIT_MASK_SPEC_SIFS_CCK_8821C 0xff #define BIT_SPEC_SIFS_CCK_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_8821C) #define BIT_GET_SPEC_SIFS_CCK_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8821C) & BIT_MASK_SPEC_SIFS_CCK_8821C) + /* 2 REG_ACKTO_CCK_8821C (ACK TIMEOUT REGISTER FOR CCK RATE) */ #define BIT_SHIFT_ACKTO_CCK_8821C 0 @@ -7692,6 +8779,7 @@ #define BIT_GET_ACKTO_CCK_8821C(x) (((x) >> BIT_SHIFT_ACKTO_CCK_8821C) & BIT_MASK_ACKTO_CCK_8821C) + /* 2 REG_USTIME_EDCA_8821C (US TIME TUNING FOR EDCA REGISTER) */ #define BIT_SHIFT_USTIME_EDCA_V1_8821C 0 @@ -7700,6 +8788,7 @@ #define BIT_GET_USTIME_EDCA_V1_8821C(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8821C) & BIT_MASK_USTIME_EDCA_V1_8821C) + /* 2 REG_RESP_SIFS_OFDM_8821C (RESPONSE SIFS FOR OFDM REGISTER) */ #define BIT_SHIFT_SIFS_R2T_OFDM_8821C 8 @@ -7708,12 +8797,14 @@ #define BIT_GET_SIFS_R2T_OFDM_8821C(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8821C) & BIT_MASK_SIFS_R2T_OFDM_8821C) + #define BIT_SHIFT_SIFS_T2T_OFDM_8821C 0 #define BIT_MASK_SIFS_T2T_OFDM_8821C 0xff #define BIT_SIFS_T2T_OFDM_8821C(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8821C) << BIT_SHIFT_SIFS_T2T_OFDM_8821C) #define BIT_GET_SIFS_T2T_OFDM_8821C(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8821C) & BIT_MASK_SIFS_T2T_OFDM_8821C) + /* 2 REG_RESP_SIFS_CCK_8821C (RESPONSE SIFS FOR CCK REGISTER) */ #define BIT_SHIFT_SIFS_R2T_CCK_8821C 8 @@ -7722,12 +8813,14 @@ #define BIT_GET_SIFS_R2T_CCK_8821C(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8821C) & BIT_MASK_SIFS_R2T_CCK_8821C) + #define BIT_SHIFT_SIFS_T2T_CCK_8821C 0 #define BIT_MASK_SIFS_T2T_CCK_8821C 0xff #define BIT_SIFS_T2T_CCK_8821C(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8821C) << BIT_SHIFT_SIFS_T2T_CCK_8821C) #define BIT_GET_SIFS_T2T_CCK_8821C(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8821C) & BIT_MASK_SIFS_T2T_CCK_8821C) + /* 2 REG_EIFS_8821C (EIFS REGISTER) */ #define BIT_SHIFT_EIFS_8821C 0 @@ -7736,6 +8829,7 @@ #define BIT_GET_EIFS_8821C(x) (((x) >> BIT_SHIFT_EIFS_8821C) & BIT_MASK_EIFS_8821C) + /* 2 REG_CTS2TO_8821C (CTS2 TIMEOUT REGISTER) */ #define BIT_SHIFT_CTS2TO_8821C 0 @@ -7744,6 +8838,7 @@ #define BIT_GET_CTS2TO_8821C(x) (((x) >> BIT_SHIFT_CTS2TO_8821C) & BIT_MASK_CTS2TO_8821C) + /* 2 REG_ACKTO_8821C (ACK TIMEOUT REGISTER) */ #define BIT_SHIFT_ACKTO_8821C 0 @@ -7752,6 +8847,7 @@ #define BIT_GET_ACKTO_8821C(x) (((x) >> BIT_SHIFT_ACKTO_8821C) & BIT_MASK_ACKTO_8821C) + /* 2 REG_RPFM_MAP0_8821C (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 0) */ #define BIT_MGT_RPFM15EN_8821C BIT(15) #define BIT_MGT_RPFM14EN_8821C BIT(14) @@ -7799,6 +8895,7 @@ #define BIT_GET_RPFM_CAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8821C) & BIT_MASK_RPFM_CAM_ADDR_8821C) + /* 2 REG_RPFM_CAM_RWD_8821C (ACK TIMEOUT REGISTER) */ #define BIT_SHIFT_RPFM_CAM_RWD_8821C 0 @@ -7807,6 +8904,7 @@ #define BIT_GET_RPFM_CAM_RWD_8821C(x) (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8821C) & BIT_MASK_RPFM_CAM_RWD_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_NAV_CTRL_8821C (NAV CONTROL REGISTER) */ @@ -7817,18 +8915,21 @@ #define BIT_GET_NAV_UPPER_8821C(x) (((x) >> BIT_SHIFT_NAV_UPPER_8821C) & BIT_MASK_NAV_UPPER_8821C) + #define BIT_SHIFT_RXMYRTS_NAV_8821C 8 #define BIT_MASK_RXMYRTS_NAV_8821C 0xf #define BIT_RXMYRTS_NAV_8821C(x) (((x) & BIT_MASK_RXMYRTS_NAV_8821C) << BIT_SHIFT_RXMYRTS_NAV_8821C) #define BIT_GET_RXMYRTS_NAV_8821C(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8821C) & BIT_MASK_RXMYRTS_NAV_8821C) + #define BIT_SHIFT_RTSRST_8821C 0 #define BIT_MASK_RTSRST_8821C 0xff #define BIT_RTSRST_8821C(x) (((x) & BIT_MASK_RTSRST_8821C) << BIT_SHIFT_RTSRST_8821C) #define BIT_GET_RTSRST_8821C(x) (((x) >> BIT_SHIFT_RTSRST_8821C) & BIT_MASK_RTSRST_8821C) + /* 2 REG_BACAMCMD_8821C (BLOCK ACK CAM COMMAND REGISTER) */ #define BIT_BACAM_POLL_8821C BIT(31) #define BIT_BACAM_RST_8821C BIT(17) @@ -7840,12 +8941,14 @@ #define BIT_GET_TXSBM_8821C(x) (((x) >> BIT_SHIFT_TXSBM_8821C) & BIT_MASK_TXSBM_8821C) + #define BIT_SHIFT_BACAM_ADDR_8821C 0 #define BIT_MASK_BACAM_ADDR_8821C 0x3f #define BIT_BACAM_ADDR_8821C(x) (((x) & BIT_MASK_BACAM_ADDR_8821C) << BIT_SHIFT_BACAM_ADDR_8821C) #define BIT_GET_BACAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8821C) & BIT_MASK_BACAM_ADDR_8821C) + /* 2 REG_BACAMCONTENT_8821C (BLOCK ACK CAM CONTENT REGISTER) */ #define BIT_SHIFT_BA_CONTENT_H_8821C (32 & CPU_OPT_WIDTH) @@ -7854,13 +8957,15 @@ #define BIT_GET_BA_CONTENT_H_8821C(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8821C) & BIT_MASK_BA_CONTENT_H_8821C) + #define BIT_SHIFT_BA_CONTENT_L_8821C 0 #define BIT_MASK_BA_CONTENT_L_8821C 0xffffffffL #define BIT_BA_CONTENT_L_8821C(x) (((x) & BIT_MASK_BA_CONTENT_L_8821C) << BIT_SHIFT_BA_CONTENT_L_8821C) #define BIT_GET_BA_CONTENT_L_8821C(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8821C) & BIT_MASK_BA_CONTENT_L_8821C) -/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_WMAC_BITMAP_CTL_8821C */ #define BIT_BITMAP_VO_8821C BIT(7) #define BIT_BITMAP_VI_8821C BIT(6) #define BIT_BITMAP_BE_8821C BIT(5) @@ -7871,6 +8976,7 @@ #define BIT_BITMAP_CONDITION_8821C(x) (((x) & BIT_MASK_BITMAP_CONDITION_8821C) << BIT_SHIFT_BITMAP_CONDITION_8821C) #define BIT_GET_BITMAP_CONDITION_8821C(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8821C) & BIT_MASK_BITMAP_CONDITION_8821C) + #define BIT_BITMAP_SSNBK_COUNTER_CLR_8821C BIT(1) #define BIT_BITMAP_FORCE_8821C BIT(0) @@ -7881,6 +8987,7 @@ #define BIT_RXPKT_TYPE_8821C(x) (((x) & BIT_MASK_RXPKT_TYPE_8821C) << BIT_SHIFT_RXPKT_TYPE_8821C) #define BIT_GET_RXPKT_TYPE_8821C(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8821C) & BIT_MASK_RXPKT_TYPE_8821C) + #define BIT_TXACT_IND_8821C BIT(1) #define BIT_RXACT_IND_8821C BIT(0) @@ -7891,6 +8998,7 @@ #define BIT_BITMAP_SSNBK_COUNTER_8821C(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) #define BIT_GET_BITMAP_SSNBK_COUNTER_8821C(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) + #define BIT_BITMAP_EN_8821C BIT(1) #define BIT_WMAC_BACAM_RPMEN_8821C BIT(0) @@ -7902,6 +9010,7 @@ #define BIT_GET_LBDLY_8821C(x) (((x) >> BIT_SHIFT_LBDLY_8821C) & BIT_MASK_LBDLY_8821C) + /* 2 REG_RXERR_RPT_8821C (RX ERROR REPORT REGISTER) */ #define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C 28 @@ -7909,6 +9018,7 @@ #define BIT_RXERR_RPT_SEL_V1_3_0_8821C(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) #define BIT_GET_RXERR_RPT_SEL_V1_3_0_8821C(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) + #define BIT_RXERR_RPT_RST_8821C BIT(27) #define BIT_RXERR_RPT_SEL_V1_4_8821C BIT(26) #define BIT_W1S_8821C BIT(23) @@ -7920,18 +9030,21 @@ #define BIT_GET_UD_SUB_TYPE_8821C(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8821C) & BIT_MASK_UD_SUB_TYPE_8821C) + #define BIT_SHIFT_UD_TYPE_8821C 16 #define BIT_MASK_UD_TYPE_8821C 0x3 #define BIT_UD_TYPE_8821C(x) (((x) & BIT_MASK_UD_TYPE_8821C) << BIT_SHIFT_UD_TYPE_8821C) #define BIT_GET_UD_TYPE_8821C(x) (((x) >> BIT_SHIFT_UD_TYPE_8821C) & BIT_MASK_UD_TYPE_8821C) + #define BIT_SHIFT_RPT_COUNTER_8821C 0 #define BIT_MASK_RPT_COUNTER_8821C 0xffff #define BIT_RPT_COUNTER_8821C(x) (((x) & BIT_MASK_RPT_COUNTER_8821C) << BIT_SHIFT_RPT_COUNTER_8821C) #define BIT_GET_RPT_COUNTER_8821C(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8821C) & BIT_MASK_RPT_COUNTER_8821C) + /* 2 REG_WMAC_TRXPTCL_CTL_8821C (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ #define BIT_SHIFT_ACKBA_TYPSEL_8821C (60 & CPU_OPT_WIDTH) @@ -7940,23 +9053,27 @@ #define BIT_GET_ACKBA_TYPSEL_8821C(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8821C) & BIT_MASK_ACKBA_TYPSEL_8821C) + #define BIT_SHIFT_ACKBA_ACKPCHK_8821C (56 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBA_ACKPCHK_8821C 0xf #define BIT_ACKBA_ACKPCHK_8821C(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8821C) << BIT_SHIFT_ACKBA_ACKPCHK_8821C) #define BIT_GET_ACKBA_ACKPCHK_8821C(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8821C) & BIT_MASK_ACKBA_ACKPCHK_8821C) + #define BIT_SHIFT_ACKBAR_TYPESEL_8821C (48 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBAR_TYPESEL_8821C 0xff #define BIT_ACKBAR_TYPESEL_8821C(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8821C) << BIT_SHIFT_ACKBAR_TYPESEL_8821C) #define BIT_GET_ACKBAR_TYPESEL_8821C(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8821C) & BIT_MASK_ACKBAR_TYPESEL_8821C) + #define BIT_SHIFT_ACKBAR_ACKPCHK_8821C (44 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBAR_ACKPCHK_8821C 0xf #define BIT_ACKBAR_ACKPCHK_8821C(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8821C) << BIT_SHIFT_ACKBAR_ACKPCHK_8821C) #define BIT_GET_ACKBAR_ACKPCHK_8821C(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8821C) & BIT_MASK_ACKBAR_ACKPCHK_8821C) + #define BIT_RXBA_IGNOREA2_8821C BIT(42) #define BIT_EN_SAVE_ALL_TXOPADDR_8821C BIT(41) #define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8821C BIT(40) @@ -7982,6 +9099,7 @@ #define BIT_RESP_CHNBUSY_8821C(x) (((x) & BIT_MASK_RESP_CHNBUSY_8821C) << BIT_SHIFT_RESP_CHNBUSY_8821C) #define BIT_GET_RESP_CHNBUSY_8821C(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8821C) & BIT_MASK_RESP_CHNBUSY_8821C) + #define BIT_RESP_DCTS_EN_8821C BIT(19) #define BIT_RESP_DCFE_EN_8821C BIT(18) #define BIT_RESP_SPLCPEN_8821C BIT(17) @@ -7996,17 +9114,20 @@ #define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) + #define BIT_SHIFT_RFMOD_8821C 7 #define BIT_MASK_RFMOD_8821C 0x3 #define BIT_RFMOD_8821C(x) (((x) & BIT_MASK_RFMOD_8821C) << BIT_SHIFT_RFMOD_8821C) #define BIT_GET_RFMOD_8821C(x) (((x) >> BIT_SHIFT_RFMOD_8821C) & BIT_MASK_RFMOD_8821C) + #define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C 5 #define BIT_MASK_RESP_CTS_DYNBW_SEL_8821C 0x3 #define BIT_RESP_CTS_DYNBW_SEL_8821C(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) #define BIT_GET_RESP_CTS_DYNBW_SEL_8821C(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) + #define BIT_DLY_TX_WAIT_RXANTSEL_8821C BIT(4) #define BIT_TXRESP_BY_RXANTSEL_8821C BIT(3) @@ -8016,6 +9137,7 @@ #define BIT_GET_ORIG_DCTS_CHK_8821C(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8821C) & BIT_MASK_ORIG_DCTS_CHK_8821C) + /* 2 REG_CAMCMD_8821C (CAM COMMAND REGISTER) */ #define BIT_SECCAM_POLLING_8821C BIT(31) #define BIT_SECCAM_CLR_8821C BIT(30) @@ -8028,6 +9150,7 @@ #define BIT_GET_SECCAM_ADDR_V2_8821C(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8821C) & BIT_MASK_SECCAM_ADDR_V2_8821C) + /* 2 REG_CAMWRITE_8821C (CAM WRITE REGISTER) */ #define BIT_SHIFT_CAMW_DATA_8821C 0 @@ -8036,6 +9159,7 @@ #define BIT_GET_CAMW_DATA_8821C(x) (((x) >> BIT_SHIFT_CAMW_DATA_8821C) & BIT_MASK_CAMW_DATA_8821C) + /* 2 REG_CAMREAD_8821C (CAM READ REGISTER) */ #define BIT_SHIFT_CAMR_DATA_8821C 0 @@ -8044,6 +9168,7 @@ #define BIT_GET_CAMR_DATA_8821C(x) (((x) >> BIT_SHIFT_CAMR_DATA_8821C) & BIT_MASK_CAMR_DATA_8821C) + /* 2 REG_CAMDBG_8821C (CAM DEBUG REGISTER) */ #define BIT_SECCAM_INFO_8821C BIT(31) #define BIT_SEC_KEYFOUND_8821C BIT(15) @@ -8053,6 +9178,7 @@ #define BIT_CAMDBG_SEC_TYPE_8821C(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8821C) << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) #define BIT_GET_CAMDBG_SEC_TYPE_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) & BIT_MASK_CAMDBG_SEC_TYPE_8821C) + #define BIT_CAMDBG_EXT_SECTYPE_8821C BIT(11) #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C 5 @@ -8061,12 +9187,14 @@ #define BIT_GET_CAMDBG_MIC_KEY_IDX_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) + #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C 0 #define BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C 0x1f #define BIT_CAMDBG_SEC_KEY_IDX_8821C(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) #define BIT_GET_CAMDBG_SEC_KEY_IDX_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) + /* 2 REG_RXFILTER_ACTION_1_8821C */ #define BIT_SHIFT_RXFILTER_ACTION_1_8821C 0 @@ -8075,6 +9203,7 @@ #define BIT_GET_RXFILTER_ACTION_1_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8821C) & BIT_MASK_RXFILTER_ACTION_1_8821C) + /* 2 REG_RXFILTER_CATEGORY_1_8821C */ #define BIT_SHIFT_RXFILTER_CATEGORY_1_8821C 0 @@ -8083,6 +9212,7 @@ #define BIT_GET_RXFILTER_CATEGORY_1_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) & BIT_MASK_RXFILTER_CATEGORY_1_8821C) + /* 2 REG_SECCFG_8821C (SECURITY CONFIGURATION REGISTER) */ #define BIT_DIS_GCLK_WAPI_8821C BIT(15) #define BIT_DIS_GCLK_AES_8821C BIT(14) @@ -8108,6 +9238,7 @@ #define BIT_GET_RXFILTER_ACTION_3_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8821C) & BIT_MASK_RXFILTER_ACTION_3_8821C) + /* 2 REG_RXFILTER_CATEGORY_3_8821C */ #define BIT_SHIFT_RXFILTER_CATEGORY_3_8821C 0 @@ -8116,6 +9247,7 @@ #define BIT_GET_RXFILTER_CATEGORY_3_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) & BIT_MASK_RXFILTER_CATEGORY_3_8821C) + /* 2 REG_RXFILTER_ACTION_2_8821C */ #define BIT_SHIFT_RXFILTER_ACTION_2_8821C 0 @@ -8124,6 +9256,7 @@ #define BIT_GET_RXFILTER_ACTION_2_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8821C) & BIT_MASK_RXFILTER_ACTION_2_8821C) + /* 2 REG_RXFILTER_CATEGORY_2_8821C */ #define BIT_SHIFT_RXFILTER_CATEGORY_2_8821C 0 @@ -8132,6 +9265,7 @@ #define BIT_GET_RXFILTER_CATEGORY_2_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) & BIT_MASK_RXFILTER_CATEGORY_2_8821C) + /* 2 REG_RXFLTMAP4_8821C (RX FILTER MAP GROUP 4) */ #define BIT_CTRLFLT15EN_FW_8821C BIT(15) #define BIT_CTRLFLT14EN_FW_8821C BIT(14) @@ -8221,6 +9355,7 @@ #define BIT_PORTSEL__PS_RX_INFO_8821C(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) #define BIT_GET_PORTSEL__PS_RX_INFO_8821C(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C) + #define BIT_RXCTRLIN0_8821C BIT(4) #define BIT_RXMGTIN0_8821C BIT(3) #define BIT_RXDATAIN2_8821C BIT(2) @@ -8239,6 +9374,7 @@ #define BIT_PSF_BSSIDSEL_B2B1_8821C(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) #define BIT_GET_PSF_BSSIDSEL_B2B1_8821C(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) + #define BIT_WOWHCI_8821C BIT(5) #define BIT_PSF_BSSIDSEL_B0_8821C BIT(4) #define BIT_UWF_8821C BIT(3) @@ -8255,21 +9391,24 @@ #define BIT_GET_LPNAV_EARLY_8821C(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8821C) & BIT_MASK_LPNAV_EARLY_8821C) + #define BIT_SHIFT_LPNAV_TH_8821C 0 #define BIT_MASK_LPNAV_TH_8821C 0xffff #define BIT_LPNAV_TH_8821C(x) (((x) & BIT_MASK_LPNAV_TH_8821C) << BIT_SHIFT_LPNAV_TH_8821C) #define BIT_GET_LPNAV_TH_8821C(x) (((x) >> BIT_SHIFT_LPNAV_TH_8821C) & BIT_MASK_LPNAV_TH_8821C) + /* 2 REG_WKFMCAM_CMD_8821C (WAKEUP FRAME CAM COMMAND REGISTER) */ #define BIT_WKFCAM_POLLING_V1_8821C BIT(31) #define BIT_WKFCAM_CLR_V1_8821C BIT(30) #define BIT_WKFCAM_WE_8821C BIT(16) -#define BIT_SHIFT_WKFCAM_ADDR_V1_8821C 7 -#define BIT_MASK_WKFCAM_ADDR_V1_8821C 0x1ff -#define BIT_WKFCAM_ADDR_V1_8821C(x) (((x) & BIT_MASK_WKFCAM_ADDR_V1_8821C) << BIT_SHIFT_WKFCAM_ADDR_V1_8821C) -#define BIT_GET_WKFCAM_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V1_8821C) & BIT_MASK_WKFCAM_ADDR_V1_8821C) +#define BIT_SHIFT_WKFCAM_ADDR_V2_8821C 8 +#define BIT_MASK_WKFCAM_ADDR_V2_8821C 0xff +#define BIT_WKFCAM_ADDR_V2_8821C(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8821C) << BIT_SHIFT_WKFCAM_ADDR_V2_8821C) +#define BIT_GET_WKFCAM_ADDR_V2_8821C(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8821C) & BIT_MASK_WKFCAM_ADDR_V2_8821C) + #define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C 0 @@ -8278,6 +9417,7 @@ #define BIT_GET_WKFCAM_CAM_NUM_V1_8821C(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) + /* 2 REG_WKFMCAM_RWD_8821C (WAKEUP FRAME READ/WRITE DATA) */ #define BIT_SHIFT_WKFMCAM_RWD_8821C 0 @@ -8286,6 +9426,7 @@ #define BIT_GET_WKFMCAM_RWD_8821C(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8821C) & BIT_MASK_WKFMCAM_RWD_8821C) + /* 2 REG_RXFLTMAP1_8821C (RX FILTER MAP GROUP 1) */ #define BIT_CTRLFLT15EN_8821C BIT(15) #define BIT_CTRLFLT14EN_8821C BIT(14) @@ -8350,11 +9491,13 @@ #define BIT_GET_DTIM_CNT_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT_8821C) & BIT_MASK_DTIM_CNT_8821C) + #define BIT_SHIFT_DTIM_PERIOD_8821C 16 #define BIT_MASK_DTIM_PERIOD_8821C 0xff #define BIT_DTIM_PERIOD_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD_8821C) << BIT_SHIFT_DTIM_PERIOD_8821C) #define BIT_GET_DTIM_PERIOD_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8821C) & BIT_MASK_DTIM_PERIOD_8821C) + #define BIT_DTIM_8821C BIT(15) #define BIT_TIM_8821C BIT(14) @@ -8364,6 +9507,7 @@ #define BIT_GET_PS_AID_0_8821C(x) (((x) >> BIT_SHIFT_PS_AID_0_8821C) & BIT_MASK_PS_AID_0_8821C) + /* 2 REG_FLC_TRPC_8821C (TIMER OF FLC_RPC) */ #define BIT_FLC_RPCT_V1_8821C BIT(7) #define BIT_MODE_8821C BIT(6) @@ -8374,6 +9518,7 @@ #define BIT_GET_TRPCD_8821C(x) (((x) >> BIT_SHIFT_TRPCD_8821C) & BIT_MASK_TRPCD_8821C) + /* 2 REG_FLC_PTS_8821C (PKT TYPE SELECTION OF FLC_RPC T) */ #define BIT_CMF_8821C BIT(2) #define BIT_CCF_8821C BIT(1) @@ -8387,6 +9532,7 @@ #define BIT_GET_FLC_RPCT_8821C(x) (((x) >> BIT_SHIFT_FLC_RPCT_8821C) & BIT_MASK_FLC_RPCT_8821C) + /* 2 REG_FLC_RPC_8821C (FW LPS CONDITION -- RX PKT COUNTER) */ #define BIT_SHIFT_FLC_RPC_8821C 0 @@ -8395,6 +9541,7 @@ #define BIT_GET_FLC_RPC_8821C(x) (((x) >> BIT_SHIFT_FLC_RPC_8821C) & BIT_MASK_FLC_RPC_8821C) + /* 2 REG_RXPKTMON_CTRL_8821C */ #define BIT_SHIFT_RXBKQPKT_SEQ_8821C 20 @@ -8403,23 +9550,27 @@ #define BIT_GET_RXBKQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8821C) & BIT_MASK_RXBKQPKT_SEQ_8821C) + #define BIT_SHIFT_RXBEQPKT_SEQ_8821C 16 #define BIT_MASK_RXBEQPKT_SEQ_8821C 0xf #define BIT_RXBEQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8821C) << BIT_SHIFT_RXBEQPKT_SEQ_8821C) #define BIT_GET_RXBEQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8821C) & BIT_MASK_RXBEQPKT_SEQ_8821C) + #define BIT_SHIFT_RXVIQPKT_SEQ_8821C 12 #define BIT_MASK_RXVIQPKT_SEQ_8821C 0xf #define BIT_RXVIQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8821C) << BIT_SHIFT_RXVIQPKT_SEQ_8821C) #define BIT_GET_RXVIQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8821C) & BIT_MASK_RXVIQPKT_SEQ_8821C) + #define BIT_SHIFT_RXVOQPKT_SEQ_8821C 8 #define BIT_MASK_RXVOQPKT_SEQ_8821C 0xf #define BIT_RXVOQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8821C) << BIT_SHIFT_RXVOQPKT_SEQ_8821C) #define BIT_GET_RXVOQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8821C) & BIT_MASK_RXVOQPKT_SEQ_8821C) + #define BIT_RXBKQPKT_ERR_8821C BIT(7) #define BIT_RXBEQPKT_ERR_8821C BIT(6) #define BIT_RXVIQPKT_ERR_8821C BIT(5) @@ -8436,11 +9587,13 @@ #define BIT_GET_STATE_SEL_8821C(x) (((x) >> BIT_SHIFT_STATE_SEL_8821C) & BIT_MASK_STATE_SEL_8821C) + #define BIT_SHIFT_STATE_INFO_8821C 8 #define BIT_MASK_STATE_INFO_8821C 0xff #define BIT_STATE_INFO_8821C(x) (((x) & BIT_MASK_STATE_INFO_8821C) << BIT_SHIFT_STATE_INFO_8821C) #define BIT_GET_STATE_INFO_8821C(x) (((x) >> BIT_SHIFT_STATE_INFO_8821C) & BIT_MASK_STATE_INFO_8821C) + #define BIT_UPD_NXT_STATE_8821C BIT(7) #define BIT_SHIFT_CUR_STATE_8821C 0 @@ -8449,6 +9602,7 @@ #define BIT_GET_CUR_STATE_8821C(x) (((x) >> BIT_SHIFT_CUR_STATE_8821C) & BIT_MASK_CUR_STATE_8821C) + /* 2 REG_ERROR_MON_8821C */ #define BIT_MACRX_ERR_1_8821C BIT(17) #define BIT_MACRX_ERR_0_8821C BIT(16) @@ -8465,6 +9619,7 @@ #define BIT_INFO_INDEX_OFFSET_8821C(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8821C) << BIT_SHIFT_INFO_INDEX_OFFSET_8821C) #define BIT_GET_INFO_INDEX_OFFSET_8821C(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8821C) & BIT_MASK_INFO_INDEX_OFFSET_8821C) + #define BIT_WMAC_SRCH_FIFOFULL_8821C BIT(15) #define BIT_DIS_INFOSRCH_8821C BIT(14) #define BIT_DISABLE_B0_8821C BIT(13) @@ -8475,6 +9630,7 @@ #define BIT_GET_INFO_ADDR_OFFSET_8821C(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8821C) & BIT_MASK_INFO_ADDR_OFFSET_8821C) + /* 2 REG_BT_COEX_TABLE_8821C (BT-COEXISTENCE CONTROL REGISTER) */ #define BIT_PRI_MASK_RX_RESP_8821C BIT(126) #define BIT_PRI_MASK_RXOFDM_8821C BIT(125) @@ -8486,11 +9642,13 @@ #define BIT_GET_PRI_MASK_TXAC_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8821C) & BIT_MASK_PRI_MASK_TXAC_8821C) + #define BIT_SHIFT_PRI_MASK_NAV_8821C (109 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_NAV_8821C 0xff #define BIT_PRI_MASK_NAV_8821C(x) (((x) & BIT_MASK_PRI_MASK_NAV_8821C) << BIT_SHIFT_PRI_MASK_NAV_8821C) #define BIT_GET_PRI_MASK_NAV_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8821C) & BIT_MASK_PRI_MASK_NAV_8821C) + #define BIT_PRI_MASK_CCK_8821C BIT(108) #define BIT_PRI_MASK_OFDM_8821C BIT(107) #define BIT_PRI_MASK_RTY_8821C BIT(106) @@ -8501,11 +9659,13 @@ #define BIT_GET_PRI_MASK_NUM_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8821C) & BIT_MASK_PRI_MASK_NUM_8821C) + #define BIT_SHIFT_PRI_MASK_TYPE_8821C (98 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_TYPE_8821C 0xf #define BIT_PRI_MASK_TYPE_8821C(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8821C) << BIT_SHIFT_PRI_MASK_TYPE_8821C) #define BIT_GET_PRI_MASK_TYPE_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8821C) & BIT_MASK_PRI_MASK_TYPE_8821C) + #define BIT_OOB_8821C BIT(97) #define BIT_ANT_SEL_8821C BIT(96) @@ -8515,24 +9675,28 @@ #define BIT_GET_BREAK_TABLE_2_8821C(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8821C) & BIT_MASK_BREAK_TABLE_2_8821C) + #define BIT_SHIFT_BREAK_TABLE_1_8821C (64 & CPU_OPT_WIDTH) #define BIT_MASK_BREAK_TABLE_1_8821C 0xffff #define BIT_BREAK_TABLE_1_8821C(x) (((x) & BIT_MASK_BREAK_TABLE_1_8821C) << BIT_SHIFT_BREAK_TABLE_1_8821C) #define BIT_GET_BREAK_TABLE_1_8821C(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8821C) & BIT_MASK_BREAK_TABLE_1_8821C) + #define BIT_SHIFT_COEX_TABLE_2_8821C (32 & CPU_OPT_WIDTH) #define BIT_MASK_COEX_TABLE_2_8821C 0xffffffffL #define BIT_COEX_TABLE_2_8821C(x) (((x) & BIT_MASK_COEX_TABLE_2_8821C) << BIT_SHIFT_COEX_TABLE_2_8821C) #define BIT_GET_COEX_TABLE_2_8821C(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8821C) & BIT_MASK_COEX_TABLE_2_8821C) + #define BIT_SHIFT_COEX_TABLE_1_8821C 0 #define BIT_MASK_COEX_TABLE_1_8821C 0xffffffffL #define BIT_COEX_TABLE_1_8821C(x) (((x) & BIT_MASK_COEX_TABLE_1_8821C) << BIT_SHIFT_COEX_TABLE_1_8821C) #define BIT_GET_COEX_TABLE_1_8821C(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8821C) & BIT_MASK_COEX_TABLE_1_8821C) + /* 2 REG_RXCMD_0_8821C */ #define BIT_RXCMD_EN_8821C BIT(31) @@ -8542,6 +9706,7 @@ #define BIT_GET_RXCMD_INFO_8821C(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8821C) & BIT_MASK_RXCMD_INFO_8821C) + /* 2 REG_RXCMD_1_8821C */ #define BIT_SHIFT_RXCMD_PRD_8821C 0 @@ -8550,6 +9715,7 @@ #define BIT_GET_RXCMD_PRD_8821C(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8821C) & BIT_MASK_RXCMD_PRD_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_WMAC_RESP_TXINFO_8821C (RESPONSE TXINFO REGISTER) */ @@ -8560,30 +9726,35 @@ #define BIT_GET_WMAC_RESP_MFB_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8821C) & BIT_MASK_WMAC_RESP_MFB_8821C) + #define BIT_SHIFT_WMAC_ANTINF_SEL_8821C 23 #define BIT_MASK_WMAC_ANTINF_SEL_8821C 0x3 #define BIT_WMAC_ANTINF_SEL_8821C(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8821C) << BIT_SHIFT_WMAC_ANTINF_SEL_8821C) #define BIT_GET_WMAC_ANTINF_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8821C) & BIT_MASK_WMAC_ANTINF_SEL_8821C) + #define BIT_SHIFT_WMAC_ANTSEL_SEL_8821C 21 #define BIT_MASK_WMAC_ANTSEL_SEL_8821C 0x3 #define BIT_WMAC_ANTSEL_SEL_8821C(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8821C) << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) #define BIT_GET_WMAC_ANTSEL_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) & BIT_MASK_WMAC_ANTSEL_SEL_8821C) + #define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C 18 #define BIT_MASK_R_WMAC_RESP_TXPOWER_8821C 0x7 #define BIT_R_WMAC_RESP_TXPOWER_8821C(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) #define BIT_GET_R_WMAC_RESP_TXPOWER_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) + #define BIT_SHIFT_WMAC_RESP_TXANT_8821C 0 #define BIT_MASK_WMAC_RESP_TXANT_8821C 0x3ffff #define BIT_WMAC_RESP_TXANT_8821C(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8821C) << BIT_SHIFT_WMAC_RESP_TXANT_8821C) #define BIT_GET_WMAC_RESP_TXANT_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8821C) & BIT_MASK_WMAC_RESP_TXANT_8821C) + /* 2 REG_BBPSF_CTRL_8821C */ #define BIT_CTL_IDLE_CLR_CSI_RPT_8821C BIT(31) #define BIT_WMAC_USE_NDPARATE_8821C BIT(30) @@ -8594,11 +9765,26 @@ #define BIT_GET_WMAC_CSI_RATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8821C) & BIT_MASK_WMAC_CSI_RATE_8821C) + #define BIT_SHIFT_WMAC_RESP_TXRATE_8821C 16 #define BIT_MASK_WMAC_RESP_TXRATE_8821C 0xff #define BIT_WMAC_RESP_TXRATE_8821C(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8821C) << BIT_SHIFT_WMAC_RESP_TXRATE_8821C) #define BIT_GET_WMAC_RESP_TXRATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8821C) & BIT_MASK_WMAC_RESP_TXRATE_8821C) + +#define BIT_CSI_FORCE_RATE_EN_8821C BIT(15) + +#define BIT_SHIFT_CSI_RSC_8821C 13 +#define BIT_MASK_CSI_RSC_8821C 0x3 +#define BIT_CSI_RSC_8821C(x) (((x) & BIT_MASK_CSI_RSC_8821C) << BIT_SHIFT_CSI_RSC_8821C) +#define BIT_GET_CSI_RSC_8821C(x) (((x) >> BIT_SHIFT_CSI_RSC_8821C) & BIT_MASK_CSI_RSC_8821C) + + +#define BIT_CSI_GID_SEL_8821C BIT(12) +#define BIT_RDCSIMD_FLAG_TRIG_SEL_8821C BIT(11) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS_8821C BIT(10) +#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8821C BIT(9) +#define BIT_RDCSI_EMPTY_APPZERO_8821C BIT(8) #define BIT_BBPSF_MPDUCHKEN_8821C BIT(5) #define BIT_BBPSF_MHCHKEN_8821C BIT(4) #define BIT_BBPSF_ERRCHKEN_8821C BIT(3) @@ -8609,6 +9795,7 @@ #define BIT_GET_BBPSF_ERRTHR_8821C(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8821C) & BIT_MASK_BBPSF_ERRTHR_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_P2P_RX_BCN_NOA_8821C (P2P RX BEACON NOA REGISTER) */ @@ -8621,6 +9808,7 @@ #define BIT_GET_P2P_OUI_TYPE_8821C(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8821C) & BIT_MASK_P2P_OUI_TYPE_8821C) + /* 2 REG_ASSOCIATED_BFMER0_INFO_8821C (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ #define BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C (48 & CPU_OPT_WIDTH) @@ -8629,12 +9817,14 @@ #define BIT_GET_R_WMAC_TXCSI_AID0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C) + #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C 0xffffffffffffL #define BIT_R_WMAC_SOUNDING_RXADD_R0_8821C(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C) #define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C) + /* 2 REG_ASSOCIATED_BFMER1_INFO_8821C (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ #define BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C (48 & CPU_OPT_WIDTH) @@ -8643,12 +9833,14 @@ #define BIT_GET_R_WMAC_TXCSI_AID1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C) + #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C 0xffffffffffffL #define BIT_R_WMAC_SOUNDING_RXADD_R1_8821C(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C) #define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -8667,12 +9859,14 @@ #define BIT_GET_R_WMAC_BFINFO_20M_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) + #define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C 0 #define BIT_MASK_R_WMAC_BFINFO_20M_0_8821C 0xfff #define BIT_R_WMAC_BFINFO_20M_0_8821C(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) #define BIT_GET_R_WMAC_BFINFO_20M_0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) + /* 2 REG_TX_CSI_RPT_PARAM_BW40_8821C (TX CSI REPORT PARAMETER_BW40 REGISTER) */ #define BIT_SHIFT_WMAC_RESP_ANTCD_8821C 0 @@ -8681,6 +9875,7 @@ #define BIT_GET_WMAC_RESP_ANTCD_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8821C) & BIT_MASK_WMAC_RESP_ANTCD_8821C) + /* 2 REG_TX_CSI_RPT_PARAM_BW80_8821C (TX CSI REPORT PARAMETER_BW80 REGISTER) */ /* 2 REG_BCN_PSR_RPT2_8821C (BEACON PARSER REPORT REGISTER2) */ @@ -8691,11 +9886,13 @@ #define BIT_GET_DTIM_CNT2_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8821C) & BIT_MASK_DTIM_CNT2_8821C) + #define BIT_SHIFT_DTIM_PERIOD2_8821C 16 #define BIT_MASK_DTIM_PERIOD2_8821C 0xff #define BIT_DTIM_PERIOD2_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD2_8821C) << BIT_SHIFT_DTIM_PERIOD2_8821C) #define BIT_GET_DTIM_PERIOD2_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8821C) & BIT_MASK_DTIM_PERIOD2_8821C) + #define BIT_DTIM2_8821C BIT(15) #define BIT_TIM2_8821C BIT(14) @@ -8705,6 +9902,7 @@ #define BIT_GET_PS_AID_2_8821C(x) (((x) >> BIT_SHIFT_PS_AID_2_8821C) & BIT_MASK_PS_AID_2_8821C) + /* 2 REG_BCN_PSR_RPT3_8821C (BEACON PARSER REPORT REGISTER3) */ #define BIT_SHIFT_DTIM_CNT3_8821C 24 @@ -8713,11 +9911,13 @@ #define BIT_GET_DTIM_CNT3_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8821C) & BIT_MASK_DTIM_CNT3_8821C) + #define BIT_SHIFT_DTIM_PERIOD3_8821C 16 #define BIT_MASK_DTIM_PERIOD3_8821C 0xff #define BIT_DTIM_PERIOD3_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD3_8821C) << BIT_SHIFT_DTIM_PERIOD3_8821C) #define BIT_GET_DTIM_PERIOD3_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8821C) & BIT_MASK_DTIM_PERIOD3_8821C) + #define BIT_DTIM3_8821C BIT(15) #define BIT_TIM3_8821C BIT(14) @@ -8727,6 +9927,7 @@ #define BIT_GET_PS_AID_3_8821C(x) (((x) >> BIT_SHIFT_PS_AID_3_8821C) & BIT_MASK_PS_AID_3_8821C) + /* 2 REG_BCN_PSR_RPT4_8821C (BEACON PARSER REPORT REGISTER4) */ #define BIT_SHIFT_DTIM_CNT4_8821C 24 @@ -8735,11 +9936,13 @@ #define BIT_GET_DTIM_CNT4_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8821C) & BIT_MASK_DTIM_CNT4_8821C) + #define BIT_SHIFT_DTIM_PERIOD4_8821C 16 #define BIT_MASK_DTIM_PERIOD4_8821C 0xff #define BIT_DTIM_PERIOD4_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD4_8821C) << BIT_SHIFT_DTIM_PERIOD4_8821C) #define BIT_GET_DTIM_PERIOD4_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8821C) & BIT_MASK_DTIM_PERIOD4_8821C) + #define BIT_DTIM4_8821C BIT(15) #define BIT_TIM4_8821C BIT(14) @@ -8749,6 +9952,7 @@ #define BIT_GET_PS_AID_4_8821C(x) (((x) >> BIT_SHIFT_PS_AID_4_8821C) & BIT_MASK_PS_AID_4_8821C) + /* 2 REG_A1_ADDR_MASK_8821C (A1 ADDR MASK REGISTER) */ #define BIT_SHIFT_A1_ADDR_MASK_8821C 0 @@ -8757,6 +9961,7 @@ #define BIT_GET_A1_ADDR_MASK_8821C(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8821C) & BIT_MASK_A1_ADDR_MASK_8821C) + /* 2 REG_MACID2_8821C (MAC ID2 REGISTER) */ #define BIT_SHIFT_MACID2_8821C 0 @@ -8765,6 +9970,7 @@ #define BIT_GET_MACID2_8821C(x) (((x) >> BIT_SHIFT_MACID2_8821C) & BIT_MASK_MACID2_8821C) + /* 2 REG_BSSID2_8821C (BSSID2 REGISTER) */ #define BIT_SHIFT_BSSID2_8821C 0 @@ -8773,6 +9979,7 @@ #define BIT_GET_BSSID2_8821C(x) (((x) >> BIT_SHIFT_BSSID2_8821C) & BIT_MASK_BSSID2_8821C) + /* 2 REG_MACID3_8821C (MAC ID3 REGISTER) */ #define BIT_SHIFT_MACID3_8821C 0 @@ -8781,6 +9988,7 @@ #define BIT_GET_MACID3_8821C(x) (((x) >> BIT_SHIFT_MACID3_8821C) & BIT_MASK_MACID3_8821C) + /* 2 REG_BSSID3_8821C (BSSID3 REGISTER) */ #define BIT_SHIFT_BSSID3_8821C 0 @@ -8789,6 +9997,7 @@ #define BIT_GET_BSSID3_8821C(x) (((x) >> BIT_SHIFT_BSSID3_8821C) & BIT_MASK_BSSID3_8821C) + /* 2 REG_MACID4_8821C (MAC ID4 REGISTER) */ #define BIT_SHIFT_MACID4_8821C 0 @@ -8797,6 +10006,7 @@ #define BIT_GET_MACID4_8821C(x) (((x) >> BIT_SHIFT_MACID4_8821C) & BIT_MASK_MACID4_8821C) + /* 2 REG_BSSID4_8821C (BSSID4 REGISTER) */ #define BIT_SHIFT_BSSID4_8821C 0 @@ -8805,6 +10015,7 @@ #define BIT_GET_BSSID4_8821C(x) (((x) >> BIT_SHIFT_BSSID4_8821C) & BIT_MASK_BSSID4_8821C) + /* 2 REG_NOA_REPORT_8821C */ /* 2 REG_PWRBIT_SETTING_8821C */ @@ -8817,35 +10028,218 @@ #define BIT_CLI0_PWRBIT_OW_EN_8821C BIT(1) #define BIT_CLI0_PWR_ST_8821C BIT(0) -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_WMAC_MU_BF_OPTION_8821C */ +#define BIT_WMAC_RESP_NONSTA1_DIS_8821C BIT(7) +#define BIT_WMAC_TXMU_ACKPOLICY_EN_8821C BIT(6) -/* 2 REG_NOT_VALID_8821C */ +#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C 4 +#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C 0x3 +#define BIT_WMAC_TXMU_ACKPOLICY_8821C(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8821C(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) -/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_NOT_VALID_8821C */ +#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C 1 +#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C 0x7 +#define BIT_WMAC_MU_BFEE_PORT_SEL_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) -/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_NOT_VALID_8821C */ +#define BIT_WMAC_MU_BFEE_DIS_8821C BIT(0) -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8821C */ -/* 2 REG_NOT_VALID_8821C */ +#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C 0 +#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C 0xff +#define BIT_WMAC_PAUSE_BB_CLR_TH_8821C(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8821C(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) -/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_WMAC_MU_ARB_8821C */ +#define BIT_WMAC_ARB_HW_ADAPT_EN_8821C BIT(7) +#define BIT_WMAC_ARB_SW_EN_8821C BIT(6) -/* 2 REG_NOT_VALID_8821C */ +#define BIT_SHIFT_WMAC_ARB_SW_STATE_8821C 0 +#define BIT_MASK_WMAC_ARB_SW_STATE_8821C 0x3f +#define BIT_WMAC_ARB_SW_STATE_8821C(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8821C) << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) +#define BIT_GET_WMAC_ARB_SW_STATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) & BIT_MASK_WMAC_ARB_SW_STATE_8821C) + + + +/* 2 REG_WMAC_MU_OPTION_8821C */ + +#define BIT_SHIFT_WMAC_MU_DBGSEL_8821C 5 +#define BIT_MASK_WMAC_MU_DBGSEL_8821C 0x3 +#define BIT_WMAC_MU_DBGSEL_8821C(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8821C) << BIT_SHIFT_WMAC_MU_DBGSEL_8821C) +#define BIT_GET_WMAC_MU_DBGSEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8821C) & BIT_MASK_WMAC_MU_DBGSEL_8821C) + + + +#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C 0 +#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C 0x1f +#define BIT_WMAC_MU_CPRD_TIMEOUT_8821C(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) + + + +/* 2 REG_WMAC_MU_BF_CTL_8821C */ +#define BIT_WMAC_INVLD_BFPRT_CHK_8821C BIT(15) +#define BIT_WMAC_RETXBFRPTSEQ_UPD_8821C BIT(14) + +#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C 12 +#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C 0x3 +#define BIT_WMAC_MU_BFRPTSEG_SEL_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) + + + +#define BIT_SHIFT_WMAC_MU_BF_MYAID_8821C 0 +#define BIT_MASK_WMAC_MU_BF_MYAID_8821C 0xfff +#define BIT_WMAC_MU_BF_MYAID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8821C) << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) +#define BIT_GET_WMAC_MU_BF_MYAID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) & BIT_MASK_WMAC_MU_BF_MYAID_8821C) + + + +/* 2 REG_WMAC_MU_BIT_BFRPT_PARA_8821C */ + +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C 12 +#define BIT_MASK_BFRPT_PARA_USERID_SEL_8821C 0x7 +#define BIT_BFRPT_PARA_USERID_SEL_8821C(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) +#define BIT_GET_BFRPT_PARA_USERID_SEL_8821C(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) + + + +#define BIT_SHIFT_BFRPT_PARA_8821C 0 +#define BIT_MASK_BFRPT_PARA_8821C 0xfff +#define BIT_BFRPT_PARA_8821C(x) (((x) & BIT_MASK_BFRPT_PARA_8821C) << BIT_SHIFT_BFRPT_PARA_8821C) +#define BIT_GET_BFRPT_PARA_8821C(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8821C) & BIT_MASK_BFRPT_PARA_8821C) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C */ +#define BIT_STATUS_BFEE2_8821C BIT(10) +#define BIT_WMAC_MU_BFEE2_EN_8821C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C 0 +#define BIT_MASK_WMAC_MU_BFEE2_AID_8821C 0x1ff +#define BIT_WMAC_MU_BFEE2_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) +#define BIT_GET_WMAC_MU_BFEE2_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C */ +#define BIT_STATUS_BFEE3_8821C BIT(10) +#define BIT_WMAC_MU_BFEE3_EN_8821C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C 0 +#define BIT_MASK_WMAC_MU_BFEE3_AID_8821C 0x1ff +#define BIT_WMAC_MU_BFEE3_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) +#define BIT_GET_WMAC_MU_BFEE3_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C */ +#define BIT_STATUS_BFEE4_8821C BIT(10) +#define BIT_WMAC_MU_BFEE4_EN_8821C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C 0 +#define BIT_MASK_WMAC_MU_BFEE4_AID_8821C 0x1ff +#define BIT_WMAC_MU_BFEE4_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) +#define BIT_GET_WMAC_MU_BFEE4_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C */ +#define BIT_BIT_STATUS_BFEE5_8821C BIT(10) +#define BIT_WMAC_MU_BFEE5_EN_8821C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C 0 +#define BIT_MASK_WMAC_MU_BFEE5_AID_8821C 0x1ff +#define BIT_WMAC_MU_BFEE5_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) +#define BIT_GET_WMAC_MU_BFEE5_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C */ +#define BIT_STATUS_BFEE6_8821C BIT(10) +#define BIT_WMAC_MU_BFEE6_EN_8821C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C 0 +#define BIT_MASK_WMAC_MU_BFEE6_AID_8821C 0x1ff +#define BIT_WMAC_MU_BFEE6_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) +#define BIT_GET_WMAC_MU_BFEE6_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C */ +#define BIT_BIT_STATUS_BFEE4_8821C BIT(10) +#define BIT_WMAC_MU_BFEE7_EN_8821C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C 0 +#define BIT_MASK_WMAC_MU_BFEE7_AID_8821C 0x1ff +#define BIT_WMAC_MU_BFEE7_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) +#define BIT_GET_WMAC_MU_BFEE7_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C) + + + +/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8821C */ +#define BIT_RST_ALL_COUNTER_8821C BIT(31) + +#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C 16 +#define BIT_MASK_ABORT_RX_VBON_COUNTER_8821C 0xff +#define BIT_ABORT_RX_VBON_COUNTER_8821C(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8821C(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) + + + +#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C 8 +#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C 0xff +#define BIT_ABORT_RX_RDRDY_COUNTER_8821C(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8821C(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) + + + +#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C 0 +#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C 0xff +#define BIT_VBON_EARLY_FALLING_COUNTER_8821C(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8821C(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) + + + +/* 2 REG_WMAC_PLCP_MONITOR_8821C */ +#define BIT_WMAC_PLCP_TRX_SEL_8821C BIT(31) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C 28 +#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C 0x7 +#define BIT_WMAC_PLCP_RDSIG_SEL_8821C(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) + + + +#define BIT_SHIFT_WMAC_RATE_IDX_8821C 24 +#define BIT_MASK_WMAC_RATE_IDX_8821C 0xf +#define BIT_WMAC_RATE_IDX_8821C(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8821C) << BIT_SHIFT_WMAC_RATE_IDX_8821C) +#define BIT_GET_WMAC_RATE_IDX_8821C(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8821C) & BIT_MASK_WMAC_RATE_IDX_8821C) + + + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8821C(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) +#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) + + + +/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8821C */ +#define BIT_WMAC_MUTX_IDX_8821C BIT(24) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8821C(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) +#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) -/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_NOT_VALID_8821C */ /* 2 REG_TRANSMIT_ADDRSS_0_8821C (TA0 REGISTER) */ @@ -8855,6 +10249,7 @@ #define BIT_GET_TA0_8821C(x) (((x) >> BIT_SHIFT_TA0_8821C) & BIT_MASK_TA0_8821C) + /* 2 REG_TRANSMIT_ADDRSS_1_8821C (TA1 REGISTER) */ #define BIT_SHIFT_TA1_8821C 0 @@ -8863,6 +10258,7 @@ #define BIT_GET_TA1_8821C(x) (((x) >> BIT_SHIFT_TA1_8821C) & BIT_MASK_TA1_8821C) + /* 2 REG_TRANSMIT_ADDRSS_2_8821C (TA2 REGISTER) */ #define BIT_SHIFT_TA2_8821C 0 @@ -8871,6 +10267,7 @@ #define BIT_GET_TA2_8821C(x) (((x) >> BIT_SHIFT_TA2_8821C) & BIT_MASK_TA2_8821C) + /* 2 REG_TRANSMIT_ADDRSS_3_8821C (TA3 REGISTER) */ #define BIT_SHIFT_TA3_8821C 0 @@ -8879,6 +10276,7 @@ #define BIT_GET_TA3_8821C(x) (((x) >> BIT_SHIFT_TA3_8821C) & BIT_MASK_TA3_8821C) + /* 2 REG_TRANSMIT_ADDRSS_4_8821C (TA4 REGISTER) */ #define BIT_SHIFT_TA4_8821C 0 @@ -8887,22 +10285,43 @@ #define BIT_GET_TA4_8821C(x) (((x) >> BIT_SHIFT_TA4_8821C) & BIT_MASK_TA4_8821C) + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_MACID1_8821C */ -#define BIT_SHIFT_MACID1_8821C 0 -#define BIT_MASK_MACID1_8821C 0xffffffffffffL -#define BIT_MACID1_8821C(x) (((x) & BIT_MASK_MACID1_8821C) << BIT_SHIFT_MACID1_8821C) -#define BIT_GET_MACID1_8821C(x) (((x) >> BIT_SHIFT_MACID1_8821C) & BIT_MASK_MACID1_8821C) +#define BIT_SHIFT_MACID1_0_8821C 0 +#define BIT_MASK_MACID1_0_8821C 0xffffffffL +#define BIT_MACID1_0_8821C(x) (((x) & BIT_MASK_MACID1_0_8821C) << BIT_SHIFT_MACID1_0_8821C) +#define BIT_GET_MACID1_0_8821C(x) (((x) >> BIT_SHIFT_MACID1_0_8821C) & BIT_MASK_MACID1_0_8821C) + + + +/* 2 REG_MACID1_1_8821C */ + +#define BIT_SHIFT_MACID1_1_8821C 0 +#define BIT_MASK_MACID1_1_8821C 0xffff +#define BIT_MACID1_1_8821C(x) (((x) & BIT_MASK_MACID1_1_8821C) << BIT_SHIFT_MACID1_1_8821C) +#define BIT_GET_MACID1_1_8821C(x) (((x) >> BIT_SHIFT_MACID1_1_8821C) & BIT_MASK_MACID1_1_8821C) + /* 2 REG_BSSID1_8821C */ -#define BIT_SHIFT_BSSID1_8821C 0 -#define BIT_MASK_BSSID1_8821C 0xffffffffffffL -#define BIT_BSSID1_8821C(x) (((x) & BIT_MASK_BSSID1_8821C) << BIT_SHIFT_BSSID1_8821C) -#define BIT_GET_BSSID1_8821C(x) (((x) >> BIT_SHIFT_BSSID1_8821C) & BIT_MASK_BSSID1_8821C) +#define BIT_SHIFT_BSSID1_0_8821C 0 +#define BIT_MASK_BSSID1_0_8821C 0xffffffffL +#define BIT_BSSID1_0_8821C(x) (((x) & BIT_MASK_BSSID1_0_8821C) << BIT_SHIFT_BSSID1_0_8821C) +#define BIT_GET_BSSID1_0_8821C(x) (((x) >> BIT_SHIFT_BSSID1_0_8821C) & BIT_MASK_BSSID1_0_8821C) + + + +/* 2 REG_BSSID1_1_8821C */ + +#define BIT_SHIFT_BSSID1_1_8821C 0 +#define BIT_MASK_BSSID1_1_8821C 0xffff +#define BIT_BSSID1_1_8821C(x) (((x) & BIT_MASK_BSSID1_1_8821C) << BIT_SHIFT_BSSID1_1_8821C) +#define BIT_GET_BSSID1_1_8821C(x) (((x) >> BIT_SHIFT_BSSID1_1_8821C) & BIT_MASK_BSSID1_1_8821C) + /* 2 REG_BCN_PSR_RPT1_8821C */ @@ -8913,11 +10332,13 @@ #define BIT_GET_DTIM_CNT1_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8821C) & BIT_MASK_DTIM_CNT1_8821C) + #define BIT_SHIFT_DTIM_PERIOD1_8821C 16 #define BIT_MASK_DTIM_PERIOD1_8821C 0xff #define BIT_DTIM_PERIOD1_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD1_8821C) << BIT_SHIFT_DTIM_PERIOD1_8821C) #define BIT_GET_DTIM_PERIOD1_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8821C) & BIT_MASK_DTIM_PERIOD1_8821C) + #define BIT_DTIM1_8821C BIT(15) #define BIT_TIM1_8821C BIT(14) @@ -8927,6 +10348,7 @@ #define BIT_GET_PS_AID_1_8821C(x) (((x) >> BIT_SHIFT_PS_AID_1_8821C) & BIT_MASK_PS_AID_1_8821C) + /* 2 REG_ASSOCIATED_BFMEE_SEL_8821C */ #define BIT_TXUSER_ID1_8821C BIT(25) @@ -8935,6 +10357,7 @@ #define BIT_AID1_8821C(x) (((x) & BIT_MASK_AID1_8821C) << BIT_SHIFT_AID1_8821C) #define BIT_GET_AID1_8821C(x) (((x) >> BIT_SHIFT_AID1_8821C) & BIT_MASK_AID1_8821C) + #define BIT_TXUSER_ID0_8821C BIT(9) #define BIT_SHIFT_AID0_8821C 0 @@ -8943,6 +10366,7 @@ #define BIT_GET_AID0_8821C(x) (((x) >> BIT_SHIFT_AID0_8821C) & BIT_MASK_AID0_8821C) + /* 2 REG_SND_PTCL_CTRL_8821C */ #define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C 24 @@ -8951,17 +10375,20 @@ #define BIT_GET_NDP_RX_STANDBY_TIMER_8821C(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) + #define BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C 16 #define BIT_MASK_CSI_RPT_OFFSET_HT_8821C 0xff #define BIT_CSI_RPT_OFFSET_HT_8821C(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) #define BIT_GET_CSI_RPT_OFFSET_HT_8821C(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C) + #define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C 8 #define BIT_MASK_R_WMAC_VHT_CATEGORY_8821C 0xff #define BIT_R_WMAC_VHT_CATEGORY_8821C(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) #define BIT_GET_R_WMAC_VHT_CATEGORY_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) + #define BIT_R_WMAC_USE_NSTS_8821C BIT(7) #define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8821C BIT(6) #define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8821C BIT(5) @@ -8984,18 +10411,21 @@ #define BIT_GET_R_WMAC_NSARP_MODEN_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C) + #define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C 4 #define BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C 0x3 #define BIT_R_WMAC_NSARP_RSPFTP_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) #define BIT_GET_R_WMAC_NSARP_RSPFTP_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) + #define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C 0 #define BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C 0xf #define BIT_R_WMAC_NSARP_RSPSEC_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) #define BIT_GET_R_WMAC_NSARP_RSPSEC_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) + /* 2 REG_NS_ARP_INFO_8821C */ #define BIT_REQ_IS_MCNS_8821C BIT(23) #define BIT_REQ_IS_UCNS_8821C BIT(22) @@ -9009,18 +10439,21 @@ #define BIT_GET_EXPRSP_SECTYPE_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8821C) & BIT_MASK_EXPRSP_SECTYPE_8821C) + #define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C 8 #define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C 0xff #define BIT_EXPRSP_CHKSM_7_TO_0_8821C(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) #define BIT_GET_EXPRSP_CHKSM_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) + #define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C 0 #define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C 0xff #define BIT_EXPRSP_CHKSM_15_TO_8_8821C(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) #define BIT_GET_EXPRSP_CHKSM_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) + /* 2 REG_BEAMFORMING_INFO_NSARP_V1_8821C */ #define BIT_SHIFT_WMAC_ARPIP_8821C 0 @@ -9029,6 +10462,7 @@ #define BIT_GET_WMAC_ARPIP_8821C(x) (((x) >> BIT_SHIFT_WMAC_ARPIP_8821C) & BIT_MASK_WMAC_ARPIP_8821C) + /* 2 REG_BEAMFORMING_INFO_NSARP_8821C */ #define BIT_SHIFT_BEAMFORMING_INFO_8821C 0 @@ -9037,15 +10471,50 @@ #define BIT_GET_BEAMFORMING_INFO_8821C(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8821C) & BIT_MASK_BEAMFORMING_INFO_8821C) + +/* 2 REG_IPV6_8821C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_0_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) + + + +/* 2 REG_IPV6_1_8821C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_1_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) + + + +/* 2 REG_IPV6_2_8821C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_2_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) + + + +/* 2 REG_IPV6_3_8821C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_3_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) + + + /* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8821C 0 -#define BIT_MASK_R_WMAC_IPV6_MYIPAD_8821C 0xffffffffffffffffffffffffffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8821C) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_RSVD_0X740_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8821C */ @@ -9055,12 +10524,20 @@ #define BIT_GET_R_WMAC_CTX_SUBTYPE_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) + #define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C 0 #define BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C 0xf #define BIT_R_WMAC_RTX_SUBTYPE_8821C(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) #define BIT_GET_R_WMAC_RTX_SUBTYPE_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_WMAC_SWAES_CFG_8821C */ /* 2 REG_BT_COEX_V2_8821C */ @@ -9073,6 +10550,7 @@ #define BIT_GET_TIMER_8821C(x) (((x) >> BIT_SHIFT_TIMER_8821C) & BIT_MASK_TIMER_8821C) + /* 2 REG_BT_COEX_8821C */ #define BIT_R_GNT_BT_RFC_SW_8821C BIT(12) #define BIT_R_GNT_BT_RFC_SW_EN_8821C BIT(11) @@ -9086,14 +10564,8 @@ #define BIT_GET_R_BT_CNT_THR_8821C(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8821C) & BIT_MASK_R_BT_CNT_THR_8821C) + /* 2 REG_WLAN_ACT_MASK_CTRL_8821C */ -#define BIT_WLRX_TER_BY_CTL_8821C BIT(43) -#define BIT_WLRX_TER_BY_AD_8821C BIT(42) -#define BIT_ANT_DIVERSITY_SEL_8821C BIT(41) -#define BIT_ANTSEL_FOR_BT_CTRL_EN_8821C BIT(40) -#define BIT_WLACT_LOW_GNTWL_EN_8821C BIT(34) -#define BIT_WLACT_HIGH_GNTBT_EN_8821C BIT(33) -#define BIT_NAV_UPPER_V1_8821C BIT(32) #define BIT_SHIFT_RXMYRTS_NAV_V1_8821C 8 #define BIT_MASK_RXMYRTS_NAV_V1_8821C 0xff @@ -9101,12 +10573,23 @@ #define BIT_GET_RXMYRTS_NAV_V1_8821C(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8821C) & BIT_MASK_RXMYRTS_NAV_V1_8821C) + #define BIT_SHIFT_RTSRST_V1_8821C 0 #define BIT_MASK_RTSRST_V1_8821C 0xff #define BIT_RTSRST_V1_8821C(x) (((x) & BIT_MASK_RTSRST_V1_8821C) << BIT_SHIFT_RTSRST_V1_8821C) #define BIT_GET_RTSRST_V1_8821C(x) (((x) >> BIT_SHIFT_RTSRST_V1_8821C) & BIT_MASK_RTSRST_V1_8821C) + +/* 2 REG_WLAN_ACT_MASK_CTRL_1_8821C */ +#define BIT_WLRX_TER_BY_CTL_1_8821C BIT(11) +#define BIT_WLRX_TER_BY_AD_1_8821C BIT(10) +#define BIT_ANT_DIVERSITY_SEL_1_8821C BIT(9) +#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8821C BIT(8) +#define BIT_WLACT_LOW_GNTWL_EN_1_8821C BIT(2) +#define BIT_WLACT_HIGH_GNTBT_EN_1_8821C BIT(1) +#define BIT_NAV_UPPER_1_V1_8821C BIT(0) + /* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8821C */ #define BIT_SHIFT_BT_STAT_DELAY_8821C 12 @@ -9115,17 +10598,20 @@ #define BIT_GET_BT_STAT_DELAY_8821C(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8821C) & BIT_MASK_BT_STAT_DELAY_8821C) + #define BIT_SHIFT_BT_TRX_INIT_DETECT_8821C 8 #define BIT_MASK_BT_TRX_INIT_DETECT_8821C 0xf #define BIT_BT_TRX_INIT_DETECT_8821C(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8821C) << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) #define BIT_GET_BT_TRX_INIT_DETECT_8821C(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) & BIT_MASK_BT_TRX_INIT_DETECT_8821C) + #define BIT_SHIFT_BT_PRI_DETECT_TO_8821C 4 #define BIT_MASK_BT_PRI_DETECT_TO_8821C 0xf #define BIT_BT_PRI_DETECT_TO_8821C(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8821C) << BIT_SHIFT_BT_PRI_DETECT_TO_8821C) #define BIT_GET_BT_PRI_DETECT_TO_8821C(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8821C) & BIT_MASK_BT_PRI_DETECT_TO_8821C) + #define BIT_R_GRANTALL_WLMASK_8821C BIT(3) #define BIT_STATIS_BT_EN_8821C BIT(2) #define BIT_WL_ACT_MASK_ENABLE_8821C BIT(1) @@ -9133,30 +10619,36 @@ /* 2 REG_BT_ACT_STATISTICS_8821C */ -#define BIT_SHIFT_STATIS_BT_LO_RX_8821C (48 & CPU_OPT_WIDTH) -#define BIT_MASK_STATIS_BT_LO_RX_8821C 0xffff -#define BIT_STATIS_BT_LO_RX_8821C(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_8821C) << BIT_SHIFT_STATIS_BT_LO_RX_8821C) -#define BIT_GET_STATIS_BT_LO_RX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8821C) & BIT_MASK_STATIS_BT_LO_RX_8821C) - - -#define BIT_SHIFT_STATIS_BT_LO_TX_8821C (32 & CPU_OPT_WIDTH) -#define BIT_MASK_STATIS_BT_LO_TX_8821C 0xffff -#define BIT_STATIS_BT_LO_TX_8821C(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_8821C) << BIT_SHIFT_STATIS_BT_LO_TX_8821C) -#define BIT_GET_STATIS_BT_LO_TX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8821C) & BIT_MASK_STATIS_BT_LO_TX_8821C) - - #define BIT_SHIFT_STATIS_BT_HI_RX_8821C 16 #define BIT_MASK_STATIS_BT_HI_RX_8821C 0xffff #define BIT_STATIS_BT_HI_RX_8821C(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8821C) << BIT_SHIFT_STATIS_BT_HI_RX_8821C) #define BIT_GET_STATIS_BT_HI_RX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8821C) & BIT_MASK_STATIS_BT_HI_RX_8821C) + #define BIT_SHIFT_STATIS_BT_HI_TX_8821C 0 #define BIT_MASK_STATIS_BT_HI_TX_8821C 0xffff #define BIT_STATIS_BT_HI_TX_8821C(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8821C) << BIT_SHIFT_STATIS_BT_HI_TX_8821C) #define BIT_GET_STATIS_BT_HI_TX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8821C) & BIT_MASK_STATIS_BT_HI_TX_8821C) + +/* 2 REG_BT_ACT_STATISTICS_1_8821C */ + +#define BIT_SHIFT_STATIS_BT_LO_RX_1_8821C 16 +#define BIT_MASK_STATIS_BT_LO_RX_1_8821C 0xffff +#define BIT_STATIS_BT_LO_RX_1_8821C(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8821C) << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) +#define BIT_GET_STATIS_BT_LO_RX_1_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) & BIT_MASK_STATIS_BT_LO_RX_1_8821C) + + + +#define BIT_SHIFT_STATIS_BT_LO_TX_1_8821C 0 +#define BIT_MASK_STATIS_BT_LO_TX_1_8821C 0xffff +#define BIT_STATIS_BT_LO_TX_1_8821C(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8821C) << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) +#define BIT_GET_STATIS_BT_LO_TX_1_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) & BIT_MASK_STATIS_BT_LO_TX_1_8821C) + + + /* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8821C */ #define BIT_SHIFT_R_BT_CMD_RPT_8821C 16 @@ -9165,17 +10657,20 @@ #define BIT_GET_R_BT_CMD_RPT_8821C(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8821C) & BIT_MASK_R_BT_CMD_RPT_8821C) + #define BIT_SHIFT_R_RPT_FROM_BT_8821C 8 #define BIT_MASK_R_RPT_FROM_BT_8821C 0xff #define BIT_R_RPT_FROM_BT_8821C(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8821C) << BIT_SHIFT_R_RPT_FROM_BT_8821C) #define BIT_GET_R_RPT_FROM_BT_8821C(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8821C) & BIT_MASK_R_RPT_FROM_BT_8821C) + #define BIT_SHIFT_BT_HID_ISR_SET_8821C 6 #define BIT_MASK_BT_HID_ISR_SET_8821C 0x3 #define BIT_BT_HID_ISR_SET_8821C(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8821C) << BIT_SHIFT_BT_HID_ISR_SET_8821C) #define BIT_GET_BT_HID_ISR_SET_8821C(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8821C) & BIT_MASK_BT_HID_ISR_SET_8821C) + #define BIT_TDMA_BT_START_NOTIFY_8821C BIT(5) #define BIT_ENABLE_TDMA_FW_MODE_8821C BIT(4) #define BIT_ENABLE_PTA_TDMA_MODE_8821C BIT(3) @@ -9191,24 +10686,28 @@ #define BIT_GET_BT_PROFILE_8821C(x) (((x) >> BIT_SHIFT_BT_PROFILE_8821C) & BIT_MASK_BT_PROFILE_8821C) + #define BIT_SHIFT_BT_POWER_8821C 16 #define BIT_MASK_BT_POWER_8821C 0xff #define BIT_BT_POWER_8821C(x) (((x) & BIT_MASK_BT_POWER_8821C) << BIT_SHIFT_BT_POWER_8821C) #define BIT_GET_BT_POWER_8821C(x) (((x) >> BIT_SHIFT_BT_POWER_8821C) & BIT_MASK_BT_POWER_8821C) + #define BIT_SHIFT_BT_PREDECT_STATUS_8821C 8 #define BIT_MASK_BT_PREDECT_STATUS_8821C 0xff #define BIT_BT_PREDECT_STATUS_8821C(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8821C) << BIT_SHIFT_BT_PREDECT_STATUS_8821C) #define BIT_GET_BT_PREDECT_STATUS_8821C(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8821C) & BIT_MASK_BT_PREDECT_STATUS_8821C) + #define BIT_SHIFT_BT_CMD_INFO_8821C 0 #define BIT_MASK_BT_CMD_INFO_8821C 0xff #define BIT_BT_CMD_INFO_8821C(x) (((x) & BIT_MASK_BT_CMD_INFO_8821C) << BIT_SHIFT_BT_CMD_INFO_8821C) #define BIT_GET_BT_CMD_INFO_8821C(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8821C) & BIT_MASK_BT_CMD_INFO_8821C) + /* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8821C */ #define BIT_EN_MAC_NULL_PKT_NOTIFY_8821C BIT(31) #define BIT_EN_WLAN_RPT_AND_BT_QUERY_8821C BIT(30) @@ -9225,18 +10724,21 @@ #define BIT_GET_WLAN_RPT_DATA_8821C(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8821C) & BIT_MASK_WLAN_RPT_DATA_8821C) + #define BIT_SHIFT_CMD_ID_8821C 8 #define BIT_MASK_CMD_ID_8821C 0xff #define BIT_CMD_ID_8821C(x) (((x) & BIT_MASK_CMD_ID_8821C) << BIT_SHIFT_CMD_ID_8821C) #define BIT_GET_CMD_ID_8821C(x) (((x) >> BIT_SHIFT_CMD_ID_8821C) & BIT_MASK_CMD_ID_8821C) + #define BIT_SHIFT_BT_DATA_8821C 0 #define BIT_MASK_BT_DATA_8821C 0xff #define BIT_BT_DATA_8821C(x) (((x) & BIT_MASK_BT_DATA_8821C) << BIT_SHIFT_BT_DATA_8821C) #define BIT_GET_BT_DATA_8821C(x) (((x) >> BIT_SHIFT_BT_DATA_8821C) & BIT_MASK_BT_DATA_8821C) + /* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C */ #define BIT_SHIFT_WLAN_RPT_TO_8821C 0 @@ -9245,15 +10747,35 @@ #define BIT_GET_WLAN_RPT_TO_8821C(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8821C) & BIT_MASK_WLAN_RPT_TO_8821C) + /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C */ -#define BIT_SHIFT_ISOLATION_CHK_8821C 1 -#define BIT_MASK_ISOLATION_CHK_8821C 0x7fffffffffffffffffffL -#define BIT_ISOLATION_CHK_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_8821C) << BIT_SHIFT_ISOLATION_CHK_8821C) -#define BIT_GET_ISOLATION_CHK_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_8821C) & BIT_MASK_ISOLATION_CHK_8821C) +#define BIT_SHIFT_ISOLATION_CHK_0_8821C 1 +#define BIT_MASK_ISOLATION_CHK_0_8821C 0x7fffff +#define BIT_ISOLATION_CHK_0_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_0_8821C) << BIT_SHIFT_ISOLATION_CHK_0_8821C) +#define BIT_GET_ISOLATION_CHK_0_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8821C) & BIT_MASK_ISOLATION_CHK_0_8821C) + #define BIT_ISOLATION_EN_8821C BIT(0) +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8821C */ + +#define BIT_SHIFT_ISOLATION_CHK_1_8821C 0 +#define BIT_MASK_ISOLATION_CHK_1_8821C 0xffffffffL +#define BIT_ISOLATION_CHK_1_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_1_8821C) << BIT_SHIFT_ISOLATION_CHK_1_8821C) +#define BIT_GET_ISOLATION_CHK_1_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8821C) & BIT_MASK_ISOLATION_CHK_1_8821C) + + + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C */ + +#define BIT_SHIFT_ISOLATION_CHK_2_8821C 0 +#define BIT_MASK_ISOLATION_CHK_2_8821C 0xffffff +#define BIT_ISOLATION_CHK_2_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_2_8821C) << BIT_SHIFT_ISOLATION_CHK_2_8821C) +#define BIT_GET_ISOLATION_CHK_2_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8821C) & BIT_MASK_ISOLATION_CHK_2_8821C) + + + /* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8821C */ #define BIT_BT_HID_ISR_8821C BIT(7) #define BIT_BT_QUERY_ISR_8821C BIT(6) @@ -9272,12 +10794,14 @@ #define BIT_GET_BT_TIME_8821C(x) (((x) >> BIT_SHIFT_BT_TIME_8821C) & BIT_MASK_BT_TIME_8821C) + #define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C 0 #define BIT_MASK_BT_RPT_SAMPLE_RATE_8821C 0x3f #define BIT_BT_RPT_SAMPLE_RATE_8821C(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) #define BIT_GET_BT_RPT_SAMPLE_RATE_8821C(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) + /* 2 REG_BT_ACT_REGISTER_8821C */ #define BIT_SHIFT_BT_EISR_EN_8821C 16 @@ -9285,6 +10809,7 @@ #define BIT_BT_EISR_EN_8821C(x) (((x) & BIT_MASK_BT_EISR_EN_8821C) << BIT_SHIFT_BT_EISR_EN_8821C) #define BIT_GET_BT_EISR_EN_8821C(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8821C) & BIT_MASK_BT_EISR_EN_8821C) + #define BIT_BT_ACT_FALLING_ISR_8821C BIT(10) #define BIT_BT_ACT_RISING_ISR_8821C BIT(9) #define BIT_TDMA_TO_ISR_8821C BIT(8) @@ -9295,6 +10820,7 @@ #define BIT_GET_BT_CH_8821C(x) (((x) >> BIT_SHIFT_BT_CH_8821C) & BIT_MASK_BT_CH_8821C) + /* 2 REG_OBFF_CTRL_BASIC_8821C */ #define BIT_OBFF_EN_V1_8821C BIT(31) @@ -9303,6 +10829,7 @@ #define BIT_OBFF_STATE_V1_8821C(x) (((x) & BIT_MASK_OBFF_STATE_V1_8821C) << BIT_SHIFT_OBFF_STATE_V1_8821C) #define BIT_GET_OBFF_STATE_V1_8821C(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8821C) & BIT_MASK_OBFF_STATE_V1_8821C) + #define BIT_OBFF_ACT_RXDMA_EN_8821C BIT(27) #define BIT_OBFF_BLOCK_INT_EN_8821C BIT(26) #define BIT_OBFF_AUTOACT_EN_8821C BIT(25) @@ -9314,23 +10841,27 @@ #define BIT_GET_WAKE_MAX_PLS_8821C(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8821C) & BIT_MASK_WAKE_MAX_PLS_8821C) + #define BIT_SHIFT_WAKE_MIN_PLS_8821C 16 #define BIT_MASK_WAKE_MIN_PLS_8821C 0x7 #define BIT_WAKE_MIN_PLS_8821C(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8821C) << BIT_SHIFT_WAKE_MIN_PLS_8821C) #define BIT_GET_WAKE_MIN_PLS_8821C(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8821C) & BIT_MASK_WAKE_MIN_PLS_8821C) + #define BIT_SHIFT_WAKE_MAX_F2F_8821C 12 #define BIT_MASK_WAKE_MAX_F2F_8821C 0x7 #define BIT_WAKE_MAX_F2F_8821C(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8821C) << BIT_SHIFT_WAKE_MAX_F2F_8821C) #define BIT_GET_WAKE_MAX_F2F_8821C(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8821C) & BIT_MASK_WAKE_MAX_F2F_8821C) + #define BIT_SHIFT_WAKE_MIN_F2F_8821C 8 #define BIT_MASK_WAKE_MIN_F2F_8821C 0x7 #define BIT_WAKE_MIN_F2F_8821C(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8821C) << BIT_SHIFT_WAKE_MIN_F2F_8821C) #define BIT_GET_WAKE_MIN_F2F_8821C(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8821C) & BIT_MASK_WAKE_MIN_F2F_8821C) + #define BIT_APP_CPU_ACT_V1_8821C BIT(3) #define BIT_APP_OBFF_V1_8821C BIT(2) #define BIT_APP_IDLE_V1_8821C BIT(1) @@ -9344,24 +10875,28 @@ #define BIT_GET_RX_HIGH_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C) + #define BIT_SHIFT_RX_MED_TIMER_IDX_8821C 16 #define BIT_MASK_RX_MED_TIMER_IDX_8821C 0x7 #define BIT_RX_MED_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8821C) << BIT_SHIFT_RX_MED_TIMER_IDX_8821C) #define BIT_GET_RX_MED_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8821C) & BIT_MASK_RX_MED_TIMER_IDX_8821C) + #define BIT_SHIFT_RX_LOW_TIMER_IDX_8821C 8 #define BIT_MASK_RX_LOW_TIMER_IDX_8821C 0x7 #define BIT_RX_LOW_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8821C) << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) #define BIT_GET_RX_LOW_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) & BIT_MASK_RX_LOW_TIMER_IDX_8821C) + #define BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C 0 #define BIT_MASK_OBFF_INT_TIMER_IDX_8821C 0x7 #define BIT_OBFF_INT_TIMER_IDX_8821C(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) #define BIT_GET_OBFF_INT_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C) + /* 2 REG_LTR_CTRL_BASIC_8821C */ #define BIT_LTR_EN_V1_8821C BIT(31) #define BIT_LTR_HW_EN_V1_8821C BIT(30) @@ -9380,30 +10915,35 @@ #define BIT_GET_HIGH_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) + #define BIT_SHIFT_MED_RATE_TRIG_SEL_8821C 18 #define BIT_MASK_MED_RATE_TRIG_SEL_8821C 0x3 #define BIT_MED_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8821C) << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) #define BIT_GET_MED_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) & BIT_MASK_MED_RATE_TRIG_SEL_8821C) + #define BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C 16 #define BIT_MASK_LOW_RATE_TRIG_SEL_8821C 0x3 #define BIT_LOW_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) #define BIT_GET_LOW_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C) + #define BIT_SHIFT_HIGH_RATE_BD_IDX_8821C 8 #define BIT_MASK_HIGH_RATE_BD_IDX_8821C 0x7f #define BIT_HIGH_RATE_BD_IDX_8821C(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8821C) << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) #define BIT_GET_HIGH_RATE_BD_IDX_8821C(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) & BIT_MASK_HIGH_RATE_BD_IDX_8821C) + #define BIT_SHIFT_LOW_RATE_BD_IDX_8821C 0 #define BIT_MASK_LOW_RATE_BD_IDX_8821C 0x7f #define BIT_LOW_RATE_BD_IDX_8821C(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8821C) << BIT_SHIFT_LOW_RATE_BD_IDX_8821C) #define BIT_GET_LOW_RATE_BD_IDX_8821C(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8821C) & BIT_MASK_LOW_RATE_BD_IDX_8821C) + /* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8821C */ #define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C 24 @@ -9412,42 +10952,49 @@ #define BIT_GET_RX_EMPTY_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) + #define BIT_SHIFT_RX_AFULL_TH_IDX_8821C 20 #define BIT_MASK_RX_AFULL_TH_IDX_8821C 0x7 #define BIT_RX_AFULL_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8821C) << BIT_SHIFT_RX_AFULL_TH_IDX_8821C) #define BIT_GET_RX_AFULL_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8821C) & BIT_MASK_RX_AFULL_TH_IDX_8821C) + #define BIT_SHIFT_RX_HIGH_TH_IDX_8821C 16 #define BIT_MASK_RX_HIGH_TH_IDX_8821C 0x7 #define BIT_RX_HIGH_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8821C) << BIT_SHIFT_RX_HIGH_TH_IDX_8821C) #define BIT_GET_RX_HIGH_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8821C) & BIT_MASK_RX_HIGH_TH_IDX_8821C) + #define BIT_SHIFT_RX_MED_TH_IDX_8821C 12 #define BIT_MASK_RX_MED_TH_IDX_8821C 0x7 #define BIT_RX_MED_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8821C) << BIT_SHIFT_RX_MED_TH_IDX_8821C) #define BIT_GET_RX_MED_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8821C) & BIT_MASK_RX_MED_TH_IDX_8821C) + #define BIT_SHIFT_RX_LOW_TH_IDX_8821C 8 #define BIT_MASK_RX_LOW_TH_IDX_8821C 0x7 #define BIT_RX_LOW_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8821C) << BIT_SHIFT_RX_LOW_TH_IDX_8821C) #define BIT_GET_RX_LOW_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8821C) & BIT_MASK_RX_LOW_TH_IDX_8821C) + #define BIT_SHIFT_LTR_SPACE_IDX_8821C 4 #define BIT_MASK_LTR_SPACE_IDX_8821C 0x3 #define BIT_LTR_SPACE_IDX_8821C(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8821C) << BIT_SHIFT_LTR_SPACE_IDX_8821C) #define BIT_GET_LTR_SPACE_IDX_8821C(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8821C) & BIT_MASK_LTR_SPACE_IDX_8821C) + #define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C 0 #define BIT_MASK_LTR_IDLE_TIMER_IDX_8821C 0x7 #define BIT_LTR_IDLE_TIMER_IDX_8821C(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) #define BIT_GET_LTR_IDLE_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) + /* 2 REG_LTR_IDLE_LATENCY_V1_8821C */ #define BIT_SHIFT_LTR_IDLE_L_8821C 0 @@ -9456,6 +11003,7 @@ #define BIT_GET_LTR_IDLE_L_8821C(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8821C) & BIT_MASK_LTR_IDLE_L_8821C) + /* 2 REG_LTR_ACTIVE_LATENCY_V1_8821C */ #define BIT_SHIFT_LTR_ACT_L_8821C 0 @@ -9464,18 +11012,27 @@ #define BIT_GET_LTR_ACT_L_8821C(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8821C) & BIT_MASK_LTR_ACT_L_8821C) + /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C */ -#define BIT_APPEND_MACID_IN_RESP_EN_8821C BIT(50) -#define BIT_ADDR2_MATCH_EN_8821C BIT(49) -#define BIT_ANTTRN_EN_8821C BIT(48) -#define BIT_SHIFT_TRAIN_STA_ADDR_8821C 0 -#define BIT_MASK_TRAIN_STA_ADDR_8821C 0xffffffffffffL -#define BIT_TRAIN_STA_ADDR_8821C(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_8821C) << BIT_SHIFT_TRAIN_STA_ADDR_8821C) -#define BIT_GET_TRAIN_STA_ADDR_8821C(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8821C) & BIT_MASK_TRAIN_STA_ADDR_8821C) +#define BIT_SHIFT_TRAIN_STA_ADDR_0_8821C 0 +#define BIT_MASK_TRAIN_STA_ADDR_0_8821C 0xffffffffL +#define BIT_TRAIN_STA_ADDR_0_8821C(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8821C) << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) +#define BIT_GET_TRAIN_STA_ADDR_0_8821C(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) & BIT_MASK_TRAIN_STA_ADDR_0_8821C) + + + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C */ +#define BIT_APPEND_MACID_IN_RESP_EN_1_8821C BIT(18) +#define BIT_ADDR2_MATCH_EN_1_8821C BIT(17) +#define BIT_ANTTRN_EN_1_8821C BIT(16) + +#define BIT_SHIFT_TRAIN_STA_ADDR_1_8821C 0 +#define BIT_MASK_TRAIN_STA_ADDR_1_8821C 0xffff +#define BIT_TRAIN_STA_ADDR_1_8821C(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8821C) << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) +#define BIT_GET_TRAIN_STA_ADDR_1_8821C(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) & BIT_MASK_TRAIN_STA_ADDR_1_8821C) -/* 2 REG_RSVD_0X7B4_8821C */ /* 2 REG_WMAC_PKTCNT_RWD_8821C */ @@ -9484,6 +11041,7 @@ #define BIT_PKTCNT_BSSIDMAP_8821C(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8821C) << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) #define BIT_GET_PKTCNT_BSSIDMAP_8821C(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) & BIT_MASK_PKTCNT_BSSIDMAP_8821C) + #define BIT_PKTCNT_CNTRST_8821C BIT(1) #define BIT_PKTCNT_CNTEN_8821C BIT(0) @@ -9497,19 +11055,8 @@ #define BIT_GET_WMAC_PKTCNT_CFGAD_8821C(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) -/* 2 REG_IQ_DUMP_8821C */ - -#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8821C (64 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_MATCH_REF_MAC_8821C 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC_8821C(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8821C) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8821C) -#define BIT_GET_R_WMAC_MATCH_REF_MAC_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8821C) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8821C) - - -#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8821C (32 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_MASK_LA_MAC_8821C 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC_8821C(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8821C) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8821C) -#define BIT_GET_R_WMAC_MASK_LA_MAC_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8821C) & BIT_MASK_R_WMAC_MASK_LA_MAC_8821C) +/* 2 REG_IQ_DUMP_8821C */ #define BIT_SHIFT_DUMP_OK_ADDR_8821C 15 #define BIT_MASK_DUMP_OK_ADDR_8821C 0x1ffff @@ -9517,17 +11064,20 @@ #define BIT_GET_DUMP_OK_ADDR_8821C(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8821C) & BIT_MASK_DUMP_OK_ADDR_8821C) + #define BIT_SHIFT_R_TRIG_TIME_SEL_8821C 8 #define BIT_MASK_R_TRIG_TIME_SEL_8821C 0x7f #define BIT_R_TRIG_TIME_SEL_8821C(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8821C) << BIT_SHIFT_R_TRIG_TIME_SEL_8821C) #define BIT_GET_R_TRIG_TIME_SEL_8821C(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8821C) & BIT_MASK_R_TRIG_TIME_SEL_8821C) + #define BIT_SHIFT_R_MAC_TRIG_SEL_8821C 6 #define BIT_MASK_R_MAC_TRIG_SEL_8821C 0x3 #define BIT_R_MAC_TRIG_SEL_8821C(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8821C) << BIT_SHIFT_R_MAC_TRIG_SEL_8821C) #define BIT_GET_R_MAC_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8821C) & BIT_MASK_R_MAC_TRIG_SEL_8821C) + #define BIT_MAC_TRIG_REG_8821C BIT(5) #define BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C 3 @@ -9535,10 +11085,29 @@ #define BIT_R_LEVEL_PULSE_SEL_8821C(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) #define BIT_GET_R_LEVEL_PULSE_SEL_8821C(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C) + #define BIT_EN_LA_MAC_8821C BIT(2) #define BIT_R_EN_IQDUMP_8821C BIT(1) #define BIT_R_IQDATA_DUMP_8821C BIT(0) +/* 2 REG_IQ_DUMP_1_8821C */ + +#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C 0 +#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C 0xffffffffL +#define BIT_R_WMAC_MASK_LA_MAC_1_8821C(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) +#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) + + + +/* 2 REG_IQ_DUMP_2_8821C */ + +#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C 0 +#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C 0xffffffffL +#define BIT_R_WMAC_MATCH_REF_MAC_2_8821C(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) + + + /* 2 REG_WMAC_FTM_CTL_8821C */ #define BIT_RXFTM_TXACK_SC_8821C BIT(6) #define BIT_RXFTM_TXACK_BW_8821C BIT(5) @@ -9551,54 +11120,62 @@ /* 2 REG_WMAC_OPTION_FUNCTION_8821C */ -#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8821C (64 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_RX_FIL_LEN_8821C 0xffff -#define BIT_R_WMAC_RX_FIL_LEN_8821C(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8821C) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8821C) -#define BIT_GET_R_WMAC_RX_FIL_LEN_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8821C) & BIT_MASK_R_WMAC_RX_FIL_LEN_8821C) - - -#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8821C (56 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8821C 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH_8821C(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8821C) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8821C) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8821C) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8821C) - -#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8821C BIT(55) -#define BIT_R_WMAC_RXRST_DLY_8821C BIT(54) -#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_8821C BIT(53) -#define BIT_R_WMAC_SRCH_TXRPT_UA1_8821C BIT(52) -#define BIT_R_WMAC_SRCH_TXRPT_TYPE_8821C BIT(51) -#define BIT_R_WMAC_NDP_RST_8821C BIT(50) -#define BIT_R_WMAC_POWINT_EN_8821C BIT(49) -#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_8821C BIT(48) -#define BIT_R_WMAC_SRCH_TXRPT_MID_8821C BIT(47) -#define BIT_R_WMAC_PFIN_TOEN_8821C BIT(46) -#define BIT_R_WMAC_FIL_SECERR_8821C BIT(45) -#define BIT_R_WMAC_FIL_CTLPKTLEN_8821C BIT(44) -#define BIT_R_WMAC_FIL_FCTYPE_8821C BIT(43) -#define BIT_R_WMAC_FIL_FCPROVER_8821C BIT(42) -#define BIT_R_WMAC_PHYSTS_SNIF_8821C BIT(41) -#define BIT_R_WMAC_PHYSTS_PLCP_8821C BIT(40) -#define BIT_R_MAC_TCR_VBONF_RD_8821C BIT(39) -#define BIT_R_WMAC_TCR_MPAR_NDP_8821C BIT(38) -#define BIT_R_WMAC_NDP_FILTER_8821C BIT(37) -#define BIT_R_WMAC_RXLEN_SEL_8821C BIT(36) -#define BIT_R_WMAC_RXLEN_SEL1_8821C BIT(35) -#define BIT_R_OFDM_FILTER_8821C BIT(34) -#define BIT_R_WMAC_CHK_OFDM_LEN_8821C BIT(33) -#define BIT_R_WMAC_CHK_CCK_LEN_8821C BIT(32) - #define BIT_SHIFT_R_OFDM_LEN_8821C 26 #define BIT_MASK_R_OFDM_LEN_8821C 0x3f #define BIT_R_OFDM_LEN_8821C(x) (((x) & BIT_MASK_R_OFDM_LEN_8821C) << BIT_SHIFT_R_OFDM_LEN_8821C) #define BIT_GET_R_OFDM_LEN_8821C(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8821C) & BIT_MASK_R_OFDM_LEN_8821C) + #define BIT_SHIFT_R_CCK_LEN_8821C 0 #define BIT_MASK_R_CCK_LEN_8821C 0xffff #define BIT_R_CCK_LEN_8821C(x) (((x) & BIT_MASK_R_CCK_LEN_8821C) << BIT_SHIFT_R_CCK_LEN_8821C) #define BIT_GET_R_CCK_LEN_8821C(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8821C) & BIT_MASK_R_CCK_LEN_8821C) + +/* 2 REG_WMAC_OPTION_FUNCTION_1_8821C */ + +#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C 24 +#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C 0xff +#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) + + +#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8821C BIT(23) +#define BIT_R_WMAC_RXRST_DLY_1_8821C BIT(22) +#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8821C BIT(21) +#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8821C BIT(20) +#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8821C BIT(19) +#define BIT_R_WMAC_NDP_RST_1_8821C BIT(18) +#define BIT_R_WMAC_POWINT_EN_1_8821C BIT(17) +#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8821C BIT(16) +#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8821C BIT(15) +#define BIT_R_WMAC_PFIN_TOEN_1_8821C BIT(14) +#define BIT_R_WMAC_FIL_SECERR_1_8821C BIT(13) +#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8821C BIT(12) +#define BIT_R_WMAC_FIL_FCTYPE_1_8821C BIT(11) +#define BIT_R_WMAC_FIL_FCPROVER_1_8821C BIT(10) +#define BIT_R_WMAC_PHYSTS_SNIF_1_8821C BIT(9) +#define BIT_R_WMAC_PHYSTS_PLCP_1_8821C BIT(8) +#define BIT_R_MAC_TCR_VBONF_RD_1_8821C BIT(7) +#define BIT_R_WMAC_TCR_MPAR_NDP_1_8821C BIT(6) +#define BIT_R_WMAC_NDP_FILTER_1_8821C BIT(5) +#define BIT_R_WMAC_RXLEN_SEL_1_8821C BIT(4) +#define BIT_R_WMAC_RXLEN_SEL1_1_8821C BIT(3) +#define BIT_R_OFDM_FILTER_1_8821C BIT(2) +#define BIT_R_WMAC_CHK_OFDM_LEN_1_8821C BIT(1) +#define BIT_R_WMAC_CHK_CCK_LEN_1_8821C BIT(0) + +/* 2 REG_WMAC_OPTION_FUNCTION_2_8821C */ + +#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C 0 +#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C 0xffff +#define BIT_R_WMAC_RX_FIL_LEN_2_8821C(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) +#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) + + + /* 2 REG_RX_FILTER_FUNCTION_8821C */ #define BIT_R_WMAC_MHRDDY_LATCH_8821C BIT(14) #define BIT_R_WMAC_MHRDDY_CLR_8821C BIT(13) @@ -9616,6 +11193,8 @@ #define BIT_R_WMAC_RXFIL_MESH_DEL_8821C BIT(1) #define BIT_R_WMAC_RXFIL_MASKM_8821C BIT(0) +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_NDP_SIG_8821C */ #define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C 0 @@ -9624,13 +11203,8 @@ #define BIT_GET_R_WMAC_TXNDP_SIGB_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) -/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8821C */ - -#define BIT_SHIFT_R_MAC_DEBUG_8821C (32 & CPU_OPT_WIDTH) -#define BIT_MASK_R_MAC_DEBUG_8821C 0xffffffffL -#define BIT_R_MAC_DEBUG_8821C(x) (((x) & BIT_MASK_R_MAC_DEBUG_8821C) << BIT_SHIFT_R_MAC_DEBUG_8821C) -#define BIT_GET_R_MAC_DEBUG_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_8821C) & BIT_MASK_R_MAC_DEBUG_8821C) +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8821C */ #define BIT_SHIFT_R_MAC_DBG_SHIFT_8821C 8 #define BIT_MASK_R_MAC_DBG_SHIFT_8821C 0x7 @@ -9638,12 +11212,23 @@ #define BIT_GET_R_MAC_DBG_SHIFT_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) & BIT_MASK_R_MAC_DBG_SHIFT_8821C) + #define BIT_SHIFT_R_MAC_DBG_SEL_8821C 0 #define BIT_MASK_R_MAC_DBG_SEL_8821C 0x3 #define BIT_R_MAC_DBG_SEL_8821C(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8821C) << BIT_SHIFT_R_MAC_DBG_SEL_8821C) #define BIT_GET_R_MAC_DBG_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8821C) & BIT_MASK_R_MAC_DBG_SEL_8821C) + +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C */ + +#define BIT_SHIFT_R_MAC_DEBUG_1_8821C 0 +#define BIT_MASK_R_MAC_DEBUG_1_8821C 0xffffffffL +#define BIT_R_MAC_DEBUG_1_8821C(x) (((x) & BIT_MASK_R_MAC_DEBUG_1_8821C) << BIT_SHIFT_R_MAC_DEBUG_1_8821C) +#define BIT_GET_R_MAC_DEBUG_1_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8821C) & BIT_MASK_R_MAC_DEBUG_1_8821C) + + + /* 2 REG_WSEC_OPTION_8821C */ #define BIT_RXDEC_BM_MGNT_8821C BIT(22) #define BIT_TXENC_BM_MGNT_8821C BIT(21) @@ -9652,8 +11237,12 @@ /* 2 REG_RTS_ADDRESS_0_8821C */ +/* 2 REG_RTS_ADDRESS_0_1_8821C */ + /* 2 REG_RTS_ADDRESS_1_8821C */ +/* 2 REG_RTS_ADDRESS_1_1_8821C */ + /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8821C */ #define BIT_LTECOEX_ACCESS_START_V1_8821C BIT(31) #define BIT_LTECOEX_WRITE_MODE_V1_8821C BIT(30) @@ -9665,12 +11254,14 @@ #define BIT_GET_WRITE_BYTE_EN_V1_8821C(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) & BIT_MASK_WRITE_BYTE_EN_V1_8821C) + #define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C 0 #define BIT_MASK_LTECOEX_REG_ADDR_V1_8821C 0xffff #define BIT_LTECOEX_REG_ADDR_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) #define BIT_GET_LTECOEX_REG_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) + /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C */ #define BIT_SHIFT_LTECOEX_W_DATA_V1_8821C 0 @@ -9679,6 +11270,7 @@ #define BIT_GET_LTECOEX_W_DATA_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) & BIT_MASK_LTECOEX_W_DATA_V1_8821C) + /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C */ #define BIT_SHIFT_LTECOEX_R_DATA_V1_8821C 0 @@ -9687,6 +11279,127 @@ #define BIT_GET_LTECOEX_R_DATA_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) & BIT_MASK_LTECOEX_R_DATA_V1_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_NOT_VALID_8821C */ /* 2 REG_SDIO_TX_CTRL_8821C */ @@ -9696,6 +11409,7 @@ #define BIT_SDIO_INT_TIMEOUT_8821C(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8821C) << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) #define BIT_GET_SDIO_INT_TIMEOUT_8821C(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) & BIT_MASK_SDIO_INT_TIMEOUT_8821C) + #define BIT_IO_ERR_STATUS_8821C BIT(15) #define BIT_REPLY_ERRCRC_IN_DATA_8821C BIT(9) #define BIT_EN_CMD53_OVERLAP_8821C BIT(8) @@ -9766,6 +11480,7 @@ #define BIT_GET_RX_REQ_LEN_V1_8821C(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8821C) & BIT_MASK_RX_REQ_LEN_V1_8821C) + /* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8821C */ #define BIT_SHIFT_FREE_TXPG_SEQ_8821C 0 @@ -9774,6 +11489,7 @@ #define BIT_GET_FREE_TXPG_SEQ_8821C(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8821C) & BIT_MASK_FREE_TXPG_SEQ_8821C) + /* 2 REG_SDIO_FREE_TXPG_8821C */ #define BIT_SHIFT_MID_FREEPG_V1_8821C 16 @@ -9782,12 +11498,14 @@ #define BIT_GET_MID_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1_8821C) & BIT_MASK_MID_FREEPG_V1_8821C) + #define BIT_SHIFT_HIQ_FREEPG_V1_8821C 0 #define BIT_MASK_HIQ_FREEPG_V1_8821C 0xfff #define BIT_HIQ_FREEPG_V1_8821C(x) (((x) & BIT_MASK_HIQ_FREEPG_V1_8821C) << BIT_SHIFT_HIQ_FREEPG_V1_8821C) #define BIT_GET_HIQ_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8821C) & BIT_MASK_HIQ_FREEPG_V1_8821C) + /* 2 REG_SDIO_FREE_TXPG2_8821C */ #define BIT_SHIFT_PUB_FREEPG_V1_8821C 16 @@ -9796,12 +11514,14 @@ #define BIT_GET_PUB_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8821C) & BIT_MASK_PUB_FREEPG_V1_8821C) + #define BIT_SHIFT_LOW_FREEPG_V1_8821C 0 #define BIT_MASK_LOW_FREEPG_V1_8821C 0xfff #define BIT_LOW_FREEPG_V1_8821C(x) (((x) & BIT_MASK_LOW_FREEPG_V1_8821C) << BIT_SHIFT_LOW_FREEPG_V1_8821C) #define BIT_GET_LOW_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8821C) & BIT_MASK_LOW_FREEPG_V1_8821C) + /* 2 REG_SDIO_OQT_FREE_TXPG_V1_8821C */ #define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C 24 @@ -9810,18 +11530,21 @@ #define BIT_GET_NOAC_OQT_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) + #define BIT_SHIFT_AC_OQT_FREEPG_V1_8821C 16 #define BIT_MASK_AC_OQT_FREEPG_V1_8821C 0xff #define BIT_AC_OQT_FREEPG_V1_8821C(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8821C) << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) #define BIT_GET_AC_OQT_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) & BIT_MASK_AC_OQT_FREEPG_V1_8821C) + #define BIT_SHIFT_EXQ_FREEPG_V1_8821C 0 #define BIT_MASK_EXQ_FREEPG_V1_8821C 0xfff #define BIT_EXQ_FREEPG_V1_8821C(x) (((x) & BIT_MASK_EXQ_FREEPG_V1_8821C) << BIT_SHIFT_EXQ_FREEPG_V1_8821C) #define BIT_GET_EXQ_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8821C) & BIT_MASK_EXQ_FREEPG_V1_8821C) + /* 2 REG_SDIO_HTSFR_INFO_8821C */ #define BIT_SHIFT_HTSFR1_8821C 16 @@ -9830,17 +11553,17 @@ #define BIT_GET_HTSFR1_8821C(x) (((x) >> BIT_SHIFT_HTSFR1_8821C) & BIT_MASK_HTSFR1_8821C) + #define BIT_SHIFT_HTSFR0_8821C 0 #define BIT_MASK_HTSFR0_8821C 0xffff #define BIT_HTSFR0_8821C(x) (((x) & BIT_MASK_HTSFR0_8821C) << BIT_SHIFT_HTSFR0_8821C) #define BIT_GET_HTSFR0_8821C(x) (((x) >> BIT_SHIFT_HTSFR0_8821C) & BIT_MASK_HTSFR0_8821C) + /* 2 REG_SDIO_HCPWM1_V2_8821C */ #define BIT_TOGGLING_8821C BIT(7) -#define BIT_WWLAN_8821C BIT(3) -#define BIT_RPS_ST_8821C BIT(2) -#define BIT_WLAN_TRX_8821C BIT(1) +#define BIT_ACK_8821C BIT(6) #define BIT_SYS_CLK_8821C BIT(0) /* 2 REG_SDIO_HCPWM2_V2_8821C */ @@ -9856,12 +11579,14 @@ #define BIT_GET_INDIRECT_REG_SIZE_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8821C) & BIT_MASK_INDIRECT_REG_SIZE_8821C) + #define BIT_SHIFT_INDIRECT_REG_ADDR_8821C 0 #define BIT_MASK_INDIRECT_REG_ADDR_8821C 0xffff #define BIT_INDIRECT_REG_ADDR_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR_8821C) << BIT_SHIFT_INDIRECT_REG_ADDR_8821C) #define BIT_GET_INDIRECT_REG_ADDR_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8821C) & BIT_MASK_INDIRECT_REG_ADDR_8821C) + /* 2 REG_SDIO_INDIRECT_REG_DATA_8821C */ #define BIT_SHIFT_INDIRECT_REG_DATA_8821C 0 @@ -9870,6 +11595,7 @@ #define BIT_GET_INDIRECT_REG_DATA_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8821C) & BIT_MASK_INDIRECT_REG_DATA_8821C) + /* 2 REG_SDIO_H2C_8821C */ #define BIT_SHIFT_SDIO_H2C_MSG_8821C 0 @@ -9878,6 +11604,7 @@ #define BIT_GET_SDIO_H2C_MSG_8821C(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8821C) & BIT_MASK_SDIO_H2C_MSG_8821C) + /* 2 REG_SDIO_C2H_8821C */ #define BIT_SHIFT_SDIO_C2H_MSG_8821C 0 @@ -9886,12 +11613,11 @@ #define BIT_GET_SDIO_C2H_MSG_8821C(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8821C) & BIT_MASK_SDIO_C2H_MSG_8821C) + /* 2 REG_SDIO_HRPWM1_8821C */ #define BIT_TOGGLING_8821C BIT(7) -#define BIT_WWLAN_8821C BIT(3) -#define BIT_RPS_ST_8821C BIT(2) -#define BIT_WLAN_TRX_8821C BIT(1) -#define BIT_SYS_CLK_8821C BIT(0) +#define BIT_ACK_8821C BIT(6) +#define BIT_32K_PERMISSION_8821C BIT(0) /* 2 REG_SDIO_HRPWM2_8821C */ @@ -9918,6 +11644,7 @@ #define BIT_GET_CMDIN_2RESP_TIMER_8821C(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) & BIT_MASK_CMDIN_2RESP_TIMER_8821C) + /* 2 REG_SDIO_CMD_CRC_8821C */ #define BIT_SHIFT_SDIO_CMD_CRC_V1_8821C 0 @@ -9926,6 +11653,7 @@ #define BIT_GET_SDIO_CMD_CRC_V1_8821C(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) & BIT_MASK_SDIO_CMD_CRC_V1_8821C) + /* 2 REG_SDIO_HSISR_8821C */ #define BIT_DRV_WLAN_INT_CLR_8821C BIT(1) #define BIT_DRV_WLAN_INT_8821C BIT(0) @@ -9938,7 +11666,7 @@ #define BIT_HR_FF_UDN_8821C BIT(5) #define BIT_TXDMA_BUSY_ERR_8821C BIT(4) #define BIT_TXDMA_VLD_ERR_8821C BIT(3) -#define BIT_QSEL_UNKOWN_ERR_8821C BIT(2) +#define BIT_QSEL_UNKNOWN_ERR_8821C BIT(2) #define BIT_QSEL_MIS_ERR_8821C BIT(1) #define BIT_SDIO_OVERRD_ERR_8821C BIT(0) @@ -9950,6 +11678,7 @@ #define BIT_GET_CMD_CRC_ERR_CNT_8821C(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) & BIT_MASK_CMD_CRC_ERR_CNT_8821C) + /* 2 REG_SDIO_DATA_ERRCNT_8821C */ #define BIT_SHIFT_DATA_CRC_ERR_CNT_8821C 0 @@ -9958,6 +11687,7 @@ #define BIT_GET_DATA_CRC_ERR_CNT_8821C(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) & BIT_MASK_DATA_CRC_ERR_CNT_8821C) + /* 2 REG_SDIO_CMD_ERR_CONTENT_8821C */ #define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C 0 @@ -9966,6 +11696,7 @@ #define BIT_GET_SDIO_CMD_ERR_CONTENT_8821C(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) + /* 2 REG_SDIO_CRC_ERR_IDX_8821C */ #define BIT_D3_CRC_ERR_8821C BIT(4) #define BIT_D2_CRC_ERR_8821C BIT(3) @@ -9981,6 +11712,7 @@ #define BIT_GET_SDIO_DATA_CRC_8821C(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8821C) & BIT_MASK_SDIO_DATA_CRC_8821C) + /* 2 REG_SDIO_DATA_REPLY_TIME_8821C */ #define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C 0 @@ -9989,4 +11721,5 @@ #define BIT_GET_SDIO_DATA_REPLY_TIME_8821C(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) + #endif diff --git a/hal/halmac/halmac_bit_8822b.h b/hal/halmac/halmac_bit_8822b.h index 089f8d3..db8680b 100644 --- a/hal/halmac/halmac_bit_8822b.h +++ b/hal/halmac/halmac_bit_8822b.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __INC_HALMAC_BIT_8822B_H #define __INC_HALMAC_BIT_8822B_H @@ -95,11 +110,13 @@ #define BIT_GET_VPDIDX_8822B(x) (((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B) + #define BIT_SHIFT_EEM1_0_8822B 6 #define BIT_MASK_EEM1_0_8822B 0x3 #define BIT_EEM1_0_8822B(x) (((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B) #define BIT_GET_EEM1_0_8822B(x) (((x) >> BIT_SHIFT_EEM1_0_8822B) & BIT_MASK_EEM1_0_8822B) + #define BIT_AUTOLOAD_SUS_8822B BIT(5) #define BIT_EERPOMSEL_8822B BIT(4) #define BIT_EECS_V1_8822B BIT(3) @@ -115,6 +132,7 @@ #define BIT_GET_VPD_DATA_8822B(x) (((x) >> BIT_SHIFT_VPD_DATA_8822B) & BIT_MASK_VPD_DATA_8822B) + /* 2 REG_SYS_SWR_CTRL1_8822B */ #define BIT_C2_L_BIT0_8822B BIT(31) @@ -124,11 +142,13 @@ #define BIT_GET_C1_L_8822B(x) (((x) >> BIT_SHIFT_C1_L_8822B) & BIT_MASK_C1_L_8822B) + #define BIT_SHIFT_REG_FREQ_L_8822B 25 #define BIT_MASK_REG_FREQ_L_8822B 0x7 #define BIT_REG_FREQ_L_8822B(x) (((x) & BIT_MASK_REG_FREQ_L_8822B) << BIT_SHIFT_REG_FREQ_L_8822B) #define BIT_GET_REG_FREQ_L_8822B(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8822B) & BIT_MASK_REG_FREQ_L_8822B) + #define BIT_REG_EN_DUTY_8822B BIT(24) #define BIT_SHIFT_REG_MODE_8822B 22 @@ -136,6 +156,7 @@ #define BIT_REG_MODE_8822B(x) (((x) & BIT_MASK_REG_MODE_8822B) << BIT_SHIFT_REG_MODE_8822B) #define BIT_GET_REG_MODE_8822B(x) (((x) >> BIT_SHIFT_REG_MODE_8822B) & BIT_MASK_REG_MODE_8822B) + #define BIT_REG_EN_SP_8822B BIT(21) #define BIT_REG_AUTO_L_8822B BIT(20) #define BIT_SW18_SELD_BIT0_8822B BIT(19) @@ -147,11 +168,13 @@ #define BIT_GET_OCP_L1_8822B(x) (((x) >> BIT_SHIFT_OCP_L1_8822B) & BIT_MASK_OCP_L1_8822B) + #define BIT_SHIFT_CF_L_8822B 13 #define BIT_MASK_CF_L_8822B 0x3 #define BIT_CF_L_8822B(x) (((x) & BIT_MASK_CF_L_8822B) << BIT_SHIFT_CF_L_8822B) #define BIT_GET_CF_L_8822B(x) (((x) >> BIT_SHIFT_CF_L_8822B) & BIT_MASK_CF_L_8822B) + #define BIT_SW18_FPWM_8822B BIT(11) #define BIT_SW18_SWEN_8822B BIT(9) #define BIT_SW18_LDEN_8822B BIT(8) @@ -168,29 +191,34 @@ #define BIT_GET_REG_DELAY_8822B(x) (((x) >> BIT_SHIFT_REG_DELAY_8822B) & BIT_MASK_REG_DELAY_8822B) + #define BIT_SHIFT_V15ADJ_L1_V1_8822B 24 #define BIT_MASK_V15ADJ_L1_V1_8822B 0x7 #define BIT_V15ADJ_L1_V1_8822B(x) (((x) & BIT_MASK_V15ADJ_L1_V1_8822B) << BIT_SHIFT_V15ADJ_L1_V1_8822B) #define BIT_GET_V15ADJ_L1_V1_8822B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8822B) & BIT_MASK_V15ADJ_L1_V1_8822B) + #define BIT_SHIFT_VOL_L1_V1_8822B 20 #define BIT_MASK_VOL_L1_V1_8822B 0xf #define BIT_VOL_L1_V1_8822B(x) (((x) & BIT_MASK_VOL_L1_V1_8822B) << BIT_SHIFT_VOL_L1_V1_8822B) #define BIT_GET_VOL_L1_V1_8822B(x) (((x) >> BIT_SHIFT_VOL_L1_V1_8822B) & BIT_MASK_VOL_L1_V1_8822B) + #define BIT_SHIFT_IN_L1_V1_8822B 17 #define BIT_MASK_IN_L1_V1_8822B 0x7 #define BIT_IN_L1_V1_8822B(x) (((x) & BIT_MASK_IN_L1_V1_8822B) << BIT_SHIFT_IN_L1_V1_8822B) #define BIT_GET_IN_L1_V1_8822B(x) (((x) >> BIT_SHIFT_IN_L1_V1_8822B) & BIT_MASK_IN_L1_V1_8822B) + #define BIT_SHIFT_TBOX_L1_8822B 15 #define BIT_MASK_TBOX_L1_8822B 0x3 #define BIT_TBOX_L1_8822B(x) (((x) & BIT_MASK_TBOX_L1_8822B) << BIT_SHIFT_TBOX_L1_8822B) #define BIT_GET_TBOX_L1_8822B(x) (((x) >> BIT_SHIFT_TBOX_L1_8822B) & BIT_MASK_TBOX_L1_8822B) + #define BIT_SW18_SEL_8822B BIT(13) /* 2 REG_NOT_VALID_8822B */ @@ -202,23 +230,27 @@ #define BIT_GET_R3_L_8822B(x) (((x) >> BIT_SHIFT_R3_L_8822B) & BIT_MASK_R3_L_8822B) + #define BIT_SHIFT_SW18_R2_8822B 5 #define BIT_MASK_SW18_R2_8822B 0x3 #define BIT_SW18_R2_8822B(x) (((x) & BIT_MASK_SW18_R2_8822B) << BIT_SHIFT_SW18_R2_8822B) #define BIT_GET_SW18_R2_8822B(x) (((x) >> BIT_SHIFT_SW18_R2_8822B) & BIT_MASK_SW18_R2_8822B) + #define BIT_SHIFT_SW18_R1_8822B 3 #define BIT_MASK_SW18_R1_8822B 0x3 #define BIT_SW18_R1_8822B(x) (((x) & BIT_MASK_SW18_R1_8822B) << BIT_SHIFT_SW18_R1_8822B) #define BIT_GET_SW18_R1_8822B(x) (((x) >> BIT_SHIFT_SW18_R1_8822B) & BIT_MASK_SW18_R1_8822B) + #define BIT_SHIFT_C3_L_C3_8822B 1 #define BIT_MASK_C3_L_C3_8822B 0x3 #define BIT_C3_L_C3_8822B(x) (((x) & BIT_MASK_C3_L_C3_8822B) << BIT_SHIFT_C3_L_C3_8822B) #define BIT_GET_C3_L_C3_8822B(x) (((x) >> BIT_SHIFT_C3_L_C3_8822B) & BIT_MASK_C3_L_C3_8822B) + #define BIT_C2_L_BIT1_8822B BIT(0) /* 2 REG_SYS_SWR_CTRL3_8822B */ @@ -230,12 +262,14 @@ #define BIT_GET_SPS18_OCP_TH_8822B(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8822B) & BIT_MASK_SPS18_OCP_TH_8822B) + #define BIT_SHIFT_OCP_WINDOW_8822B 0 #define BIT_MASK_OCP_WINDOW_8822B 0xffff #define BIT_OCP_WINDOW_8822B(x) (((x) & BIT_MASK_OCP_WINDOW_8822B) << BIT_SHIFT_OCP_WINDOW_8822B) #define BIT_GET_OCP_WINDOW_8822B(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8822B) & BIT_MASK_OCP_WINDOW_8822B) + /* 2 REG_RSV_CTRL_8822B */ #define BIT_HREG_DBG_8822B BIT(23) #define BIT_WLMCUIOIF_8822B BIT(8) @@ -260,6 +294,7 @@ #define BIT_LPLDH12_RSV_8822B(x) (((x) & BIT_MASK_LPLDH12_RSV_8822B) << BIT_SHIFT_LPLDH12_RSV_8822B) #define BIT_GET_LPLDH12_RSV_8822B(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8822B) & BIT_MASK_LPLDH12_RSV_8822B) + #define BIT_LPLDH12_SLP_8822B BIT(28) #define BIT_SHIFT_LPLDH12_VADJ_8822B 24 @@ -267,6 +302,7 @@ #define BIT_LPLDH12_VADJ_8822B(x) (((x) & BIT_MASK_LPLDH12_VADJ_8822B) << BIT_SHIFT_LPLDH12_VADJ_8822B) #define BIT_GET_LPLDH12_VADJ_8822B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8822B) & BIT_MASK_LPLDH12_VADJ_8822B) + #define BIT_LDH12_EN_8822B BIT(16) #define BIT_WLBBOFF_BIG_PWC_EN_8822B BIT(14) #define BIT_WLBBOFF_SMALL_PWC_EN_8822B BIT(13) @@ -293,11 +329,13 @@ #define BIT_GET_XTAL_CAP_XI_8822B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8822B) & BIT_MASK_XTAL_CAP_XI_8822B) + #define BIT_SHIFT_XTAL_DRV_DIGI_8822B 23 #define BIT_MASK_XTAL_DRV_DIGI_8822B 0x3 #define BIT_XTAL_DRV_DIGI_8822B(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8822B) << BIT_SHIFT_XTAL_DRV_DIGI_8822B) #define BIT_GET_XTAL_DRV_DIGI_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8822B) & BIT_MASK_XTAL_DRV_DIGI_8822B) + #define BIT_XTAL_DRV_USB_BIT1_8822B BIT(22) #define BIT_SHIFT_MAC_CLK_SEL_8822B 20 @@ -305,6 +343,7 @@ #define BIT_MAC_CLK_SEL_8822B(x) (((x) & BIT_MASK_MAC_CLK_SEL_8822B) << BIT_SHIFT_MAC_CLK_SEL_8822B) #define BIT_GET_MAC_CLK_SEL_8822B(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8822B) & BIT_MASK_MAC_CLK_SEL_8822B) + #define BIT_XTAL_DRV_USB_BIT0_8822B BIT(19) #define BIT_SHIFT_XTAL_DRV_AFE_8822B 17 @@ -313,17 +352,20 @@ #define BIT_GET_XTAL_DRV_AFE_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8822B) & BIT_MASK_XTAL_DRV_AFE_8822B) + #define BIT_SHIFT_XTAL_DRV_RF2_8822B 15 #define BIT_MASK_XTAL_DRV_RF2_8822B 0x3 #define BIT_XTAL_DRV_RF2_8822B(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8822B) << BIT_SHIFT_XTAL_DRV_RF2_8822B) #define BIT_GET_XTAL_DRV_RF2_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8822B) & BIT_MASK_XTAL_DRV_RF2_8822B) + #define BIT_SHIFT_XTAL_DRV_RF1_8822B 13 #define BIT_MASK_XTAL_DRV_RF1_8822B 0x3 #define BIT_XTAL_DRV_RF1_8822B(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8822B) << BIT_SHIFT_XTAL_DRV_RF1_8822B) #define BIT_GET_XTAL_DRV_RF1_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822B) & BIT_MASK_XTAL_DRV_RF1_8822B) + #define BIT_XTAL_DELAY_DIGI_8822B BIT(12) #define BIT_XTAL_DELAY_USB_8822B BIT(11) #define BIT_XTAL_DELAY_AFE_8822B BIT(10) @@ -333,6 +375,7 @@ #define BIT_XTAL_LDO_VREF_8822B(x) (((x) & BIT_MASK_XTAL_LDO_VREF_8822B) << BIT_SHIFT_XTAL_LDO_VREF_8822B) #define BIT_GET_XTAL_LDO_VREF_8822B(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8822B) & BIT_MASK_XTAL_LDO_VREF_8822B) + #define BIT_XTAL_XQSEL_RF_8822B BIT(6) #define BIT_XTAL_XQSEL_8822B BIT(5) @@ -342,11 +385,13 @@ #define BIT_GET_XTAL_GMN_V2_8822B(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2_8822B) & BIT_MASK_XTAL_GMN_V2_8822B) + #define BIT_SHIFT_XTAL_GMP_V2_8822B 1 #define BIT_MASK_XTAL_GMP_V2_8822B 0x3 #define BIT_XTAL_GMP_V2_8822B(x) (((x) & BIT_MASK_XTAL_GMP_V2_8822B) << BIT_SHIFT_XTAL_GMP_V2_8822B) #define BIT_GET_XTAL_GMP_V2_8822B(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2_8822B) & BIT_MASK_XTAL_GMP_V2_8822B) + #define BIT_XTAL_EN_8822B BIT(0) /* 2 REG_AFE_CTRL2_8822B */ @@ -356,6 +401,7 @@ #define BIT_REG_C3_V4_8822B(x) (((x) & BIT_MASK_REG_C3_V4_8822B) << BIT_SHIFT_REG_C3_V4_8822B) #define BIT_GET_REG_C3_V4_8822B(x) (((x) >> BIT_SHIFT_REG_C3_V4_8822B) & BIT_MASK_REG_C3_V4_8822B) + #define BIT_REG_CP_BIT1_8822B BIT(29) #define BIT_SHIFT_REG_RS_V4_8822B 26 @@ -364,23 +410,27 @@ #define BIT_GET_REG_RS_V4_8822B(x) (((x) >> BIT_SHIFT_REG_RS_V4_8822B) & BIT_MASK_REG_RS_V4_8822B) + #define BIT_SHIFT_REG__CS_8822B 24 #define BIT_MASK_REG__CS_8822B 0x3 #define BIT_REG__CS_8822B(x) (((x) & BIT_MASK_REG__CS_8822B) << BIT_SHIFT_REG__CS_8822B) #define BIT_GET_REG__CS_8822B(x) (((x) >> BIT_SHIFT_REG__CS_8822B) & BIT_MASK_REG__CS_8822B) + #define BIT_SHIFT_REG_CP_OFFSET_8822B 21 #define BIT_MASK_REG_CP_OFFSET_8822B 0x7 #define BIT_REG_CP_OFFSET_8822B(x) (((x) & BIT_MASK_REG_CP_OFFSET_8822B) << BIT_SHIFT_REG_CP_OFFSET_8822B) #define BIT_GET_REG_CP_OFFSET_8822B(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_8822B) & BIT_MASK_REG_CP_OFFSET_8822B) + #define BIT_SHIFT_CP_BIAS_8822B 18 #define BIT_MASK_CP_BIAS_8822B 0x7 #define BIT_CP_BIAS_8822B(x) (((x) & BIT_MASK_CP_BIAS_8822B) << BIT_SHIFT_CP_BIAS_8822B) #define BIT_GET_CP_BIAS_8822B(x) (((x) >> BIT_SHIFT_CP_BIAS_8822B) & BIT_MASK_CP_BIAS_8822B) + #define BIT_REG_IDOUBLE_V2_8822B BIT(17) #define BIT_EN_SYN_8822B BIT(16) @@ -390,11 +440,13 @@ #define BIT_GET_MCCO_8822B(x) (((x) >> BIT_SHIFT_MCCO_8822B) & BIT_MASK_MCCO_8822B) + #define BIT_SHIFT_REG_LDO_SEL_8822B 12 #define BIT_MASK_REG_LDO_SEL_8822B 0x3 #define BIT_REG_LDO_SEL_8822B(x) (((x) & BIT_MASK_REG_LDO_SEL_8822B) << BIT_SHIFT_REG_LDO_SEL_8822B) #define BIT_GET_REG_LDO_SEL_8822B(x) (((x) >> BIT_SHIFT_REG_LDO_SEL_8822B) & BIT_MASK_REG_LDO_SEL_8822B) + #define BIT_REG_KVCO_V2_8822B BIT(10) #define BIT_AGPIO_GPO_8822B BIT(9) @@ -404,11 +456,13 @@ #define BIT_GET_AGPIO_DRV_8822B(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8822B) & BIT_MASK_AGPIO_DRV_8822B) + #define BIT_SHIFT_XTAL_CAP_XO_8822B 1 #define BIT_MASK_XTAL_CAP_XO_8822B 0x3f #define BIT_XTAL_CAP_XO_8822B(x) (((x) & BIT_MASK_XTAL_CAP_XO_8822B) << BIT_SHIFT_XTAL_CAP_XO_8822B) #define BIT_GET_XTAL_CAP_XO_8822B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8822B) & BIT_MASK_XTAL_CAP_XO_8822B) + #define BIT_POW_PLL_8822B BIT(0) /* 2 REG_AFE_CTRL3_8822B */ @@ -418,6 +472,7 @@ #define BIT_PS_8822B(x) (((x) & BIT_MASK_PS_8822B) << BIT_SHIFT_PS_8822B) #define BIT_GET_PS_8822B(x) (((x) >> BIT_SHIFT_PS_8822B) & BIT_MASK_PS_8822B) + #define BIT_PSEN_8822B BIT(6) #define BIT_DOGENB_8822B BIT(5) #define BIT_REG_MBIAS_8822B BIT(4) @@ -427,6 +482,7 @@ #define BIT_REG_R3_V4_8822B(x) (((x) & BIT_MASK_REG_R3_V4_8822B) << BIT_SHIFT_REG_R3_V4_8822B) #define BIT_GET_REG_R3_V4_8822B(x) (((x) >> BIT_SHIFT_REG_R3_V4_8822B) & BIT_MASK_REG_R3_V4_8822B) + #define BIT_REG_CP_BIT0_8822B BIT(0) /* 2 REG_EFUSE_CTRL_8822B */ @@ -438,17 +494,20 @@ #define BIT_GET_EF_PGPD_8822B(x) (((x) >> BIT_SHIFT_EF_PGPD_8822B) & BIT_MASK_EF_PGPD_8822B) + #define BIT_SHIFT_EF_RDT_8822B 24 #define BIT_MASK_EF_RDT_8822B 0xf #define BIT_EF_RDT_8822B(x) (((x) & BIT_MASK_EF_RDT_8822B) << BIT_SHIFT_EF_RDT_8822B) #define BIT_GET_EF_RDT_8822B(x) (((x) >> BIT_SHIFT_EF_RDT_8822B) & BIT_MASK_EF_RDT_8822B) + #define BIT_SHIFT_EF_PGTS_8822B 20 #define BIT_MASK_EF_PGTS_8822B 0xf #define BIT_EF_PGTS_8822B(x) (((x) & BIT_MASK_EF_PGTS_8822B) << BIT_SHIFT_EF_PGTS_8822B) #define BIT_GET_EF_PGTS_8822B(x) (((x) >> BIT_SHIFT_EF_PGTS_8822B) & BIT_MASK_EF_PGTS_8822B) + #define BIT_EF_PDWN_8822B BIT(19) #define BIT_EF_ALDEN_8822B BIT(18) @@ -458,12 +517,14 @@ #define BIT_GET_EF_ADDR_8822B(x) (((x) >> BIT_SHIFT_EF_ADDR_8822B) & BIT_MASK_EF_ADDR_8822B) + #define BIT_SHIFT_EF_DATA_8822B 0 #define BIT_MASK_EF_DATA_8822B 0xff #define BIT_EF_DATA_8822B(x) (((x) & BIT_MASK_EF_DATA_8822B) << BIT_SHIFT_EF_DATA_8822B) #define BIT_GET_EF_DATA_8822B(x) (((x) >> BIT_SHIFT_EF_DATA_8822B) & BIT_MASK_EF_DATA_8822B) + /* 2 REG_LDO_EFUSE_CTRL_8822B */ #define BIT_LDOE25_EN_8822B BIT(31) @@ -472,6 +533,7 @@ #define BIT_LDOE25_V12ADJ_L_8822B(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8822B) << BIT_SHIFT_LDOE25_V12ADJ_L_8822B) #define BIT_GET_LDOE25_V12ADJ_L_8822B(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8822B) & BIT_MASK_LDOE25_V12ADJ_L_8822B) + #define BIT_EF_CRES_SEL_8822B BIT(26) #define BIT_SHIFT_EF_SCAN_START_V1_8822B 16 @@ -480,11 +542,13 @@ #define BIT_GET_EF_SCAN_START_V1_8822B(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822B) & BIT_MASK_EF_SCAN_START_V1_8822B) + #define BIT_SHIFT_EF_SCAN_END_8822B 12 #define BIT_MASK_EF_SCAN_END_8822B 0xf #define BIT_EF_SCAN_END_8822B(x) (((x) & BIT_MASK_EF_SCAN_END_8822B) << BIT_SHIFT_EF_SCAN_END_8822B) #define BIT_GET_EF_SCAN_END_8822B(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8822B) & BIT_MASK_EF_SCAN_END_8822B) + #define BIT_EF_PD_DIS_8822B BIT(11) #define BIT_SHIFT_EF_CELL_SEL_8822B 8 @@ -492,6 +556,7 @@ #define BIT_EF_CELL_SEL_8822B(x) (((x) & BIT_MASK_EF_CELL_SEL_8822B) << BIT_SHIFT_EF_CELL_SEL_8822B) #define BIT_GET_EF_CELL_SEL_8822B(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8822B) & BIT_MASK_EF_CELL_SEL_8822B) + #define BIT_EF_TRPT_8822B BIT(7) #define BIT_SHIFT_EF_TTHD_8822B 0 @@ -500,6 +565,7 @@ #define BIT_GET_EF_TTHD_8822B(x) (((x) >> BIT_SHIFT_EF_TTHD_8822B) & BIT_MASK_EF_TTHD_8822B) + /* 2 REG_PWR_OPTION_CTRL_8822B */ #define BIT_SHIFT_DBG_SEL_V1_8822B 16 @@ -508,17 +574,20 @@ #define BIT_GET_DBG_SEL_V1_8822B(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8822B) & BIT_MASK_DBG_SEL_V1_8822B) + #define BIT_SHIFT_DBG_SEL_BYTE_8822B 14 #define BIT_MASK_DBG_SEL_BYTE_8822B 0x3 #define BIT_DBG_SEL_BYTE_8822B(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8822B) << BIT_SHIFT_DBG_SEL_BYTE_8822B) #define BIT_GET_DBG_SEL_BYTE_8822B(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822B) & BIT_MASK_DBG_SEL_BYTE_8822B) + #define BIT_SHIFT_STD_L1_V1_8822B 12 #define BIT_MASK_STD_L1_V1_8822B 0x3 #define BIT_STD_L1_V1_8822B(x) (((x) & BIT_MASK_STD_L1_V1_8822B) << BIT_SHIFT_STD_L1_V1_8822B) #define BIT_GET_STD_L1_V1_8822B(x) (((x) >> BIT_SHIFT_STD_L1_V1_8822B) & BIT_MASK_STD_L1_V1_8822B) + #define BIT_SYSON_DBG_PAD_E2_8822B BIT(11) #define BIT_SYSON_LED_PAD_E2_8822B BIT(10) #define BIT_SYSON_GPEE_PAD_E2_8822B BIT(9) @@ -531,18 +600,21 @@ #define BIT_GET_SYSON_SPS0WWV_WT_8822B(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) & BIT_MASK_SYSON_SPS0WWV_WT_8822B) + #define BIT_SHIFT_SYSON_SPS0LDO_WT_8822B 2 #define BIT_MASK_SYSON_SPS0LDO_WT_8822B 0x3 #define BIT_SYSON_SPS0LDO_WT_8822B(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822B) << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) #define BIT_GET_SYSON_SPS0LDO_WT_8822B(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) & BIT_MASK_SYSON_SPS0LDO_WT_8822B) + #define BIT_SHIFT_SYSON_RCLK_SCALE_8822B 0 #define BIT_MASK_SYSON_RCLK_SCALE_8822B 0x3 #define BIT_SYSON_RCLK_SCALE_8822B(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8822B) << BIT_SHIFT_SYSON_RCLK_SCALE_8822B) #define BIT_GET_SYSON_RCLK_SCALE_8822B(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822B) & BIT_MASK_SYSON_RCLK_SCALE_8822B) + /* 2 REG_CAL_TIMER_8822B */ #define BIT_SHIFT_MATCH_CNT_8822B 8 @@ -551,12 +623,14 @@ #define BIT_GET_MATCH_CNT_8822B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B) + #define BIT_SHIFT_CAL_SCAL_8822B 0 #define BIT_MASK_CAL_SCAL_8822B 0xff #define BIT_CAL_SCAL_8822B(x) (((x) & BIT_MASK_CAL_SCAL_8822B) << BIT_SHIFT_CAL_SCAL_8822B) #define BIT_GET_CAL_SCAL_8822B(x) (((x) >> BIT_SHIFT_CAL_SCAL_8822B) & BIT_MASK_CAL_SCAL_8822B) + /* 2 REG_ACLK_MON_8822B */ #define BIT_SHIFT_RCLK_MON_8822B 5 @@ -564,6 +638,7 @@ #define BIT_RCLK_MON_8822B(x) (((x) & BIT_MASK_RCLK_MON_8822B) << BIT_SHIFT_RCLK_MON_8822B) #define BIT_GET_RCLK_MON_8822B(x) (((x) >> BIT_SHIFT_RCLK_MON_8822B) & BIT_MASK_RCLK_MON_8822B) + #define BIT_CAL_EN_8822B BIT(4) #define BIT_SHIFT_DPSTU_8822B 2 @@ -571,6 +646,7 @@ #define BIT_DPSTU_8822B(x) (((x) & BIT_MASK_DPSTU_8822B) << BIT_SHIFT_DPSTU_8822B) #define BIT_GET_DPSTU_8822B(x) (((x) >> BIT_SHIFT_DPSTU_8822B) & BIT_MASK_DPSTU_8822B) + #define BIT_SUS_16X_8822B BIT(1) /* 2 REG_GPIO_MUXCFG_8822B */ @@ -590,6 +666,7 @@ #define BIT_BTMODE_8822B(x) (((x) & BIT_MASK_BTMODE_8822B) << BIT_SHIFT_BTMODE_8822B) #define BIT_GET_BTMODE_8822B(x) (((x) >> BIT_SHIFT_BTMODE_8822B) & BIT_MASK_BTMODE_8822B) + #define BIT_ENBT_8822B BIT(5) #define BIT_EROM_EN_8822B BIT(4) #define BIT_WLRFE_6_7_EN_8822B BIT(3) @@ -601,6 +678,7 @@ #define BIT_GET_GPIOSEL_8822B(x) (((x) >> BIT_SHIFT_GPIOSEL_8822B) & BIT_MASK_GPIOSEL_8822B) + /* 2 REG_GPIO_PIN_CTRL_8822B */ #define BIT_SHIFT_GPIO_MOD_7_TO_0_8822B 24 @@ -609,24 +687,28 @@ #define BIT_GET_GPIO_MOD_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) & BIT_MASK_GPIO_MOD_7_TO_0_8822B) + #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B 16 #define BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B 0xff #define BIT_GPIO_IO_SEL_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) #define BIT_GET_GPIO_IO_SEL_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) + #define BIT_SHIFT_GPIO_OUT_7_TO_0_8822B 8 #define BIT_MASK_GPIO_OUT_7_TO_0_8822B 0xff #define BIT_GPIO_OUT_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822B) << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) #define BIT_GET_GPIO_OUT_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) & BIT_MASK_GPIO_OUT_7_TO_0_8822B) + #define BIT_SHIFT_GPIO_IN_7_TO_0_8822B 0 #define BIT_MASK_GPIO_IN_7_TO_0_8822B 0xff #define BIT_GPIO_IN_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8822B) << BIT_SHIFT_GPIO_IN_7_TO_0_8822B) #define BIT_GET_GPIO_IN_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822B) & BIT_MASK_GPIO_IN_7_TO_0_8822B) + /* 2 REG_GPIO_INTM_8822B */ #define BIT_SHIFT_MUXDBG_SEL_8822B 30 @@ -634,6 +716,7 @@ #define BIT_MUXDBG_SEL_8822B(x) (((x) & BIT_MASK_MUXDBG_SEL_8822B) << BIT_SHIFT_MUXDBG_SEL_8822B) #define BIT_GET_MUXDBG_SEL_8822B(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8822B) & BIT_MASK_MUXDBG_SEL_8822B) + #define BIT_EXTWOL_SEL_8822B BIT(17) #define BIT_EXTWOL_EN_8822B BIT(16) #define BIT_GPIOF_INT_MD_8822B BIT(15) @@ -673,6 +756,7 @@ #define BIT_LED2CM_8822B(x) (((x) & BIT_MASK_LED2CM_8822B) << BIT_SHIFT_LED2CM_8822B) #define BIT_GET_LED2CM_8822B(x) (((x) >> BIT_SHIFT_LED2CM_8822B) & BIT_MASK_LED2CM_8822B) + #define BIT_LED1DIS_8822B BIT(15) #define BIT_LED1PL_8822B BIT(12) #define BIT_LED1SV_8822B BIT(11) @@ -682,6 +766,7 @@ #define BIT_LED1CM_8822B(x) (((x) & BIT_MASK_LED1CM_8822B) << BIT_SHIFT_LED1CM_8822B) #define BIT_GET_LED1CM_8822B(x) (((x) >> BIT_SHIFT_LED1CM_8822B) & BIT_MASK_LED1CM_8822B) + #define BIT_LED0DIS_8822B BIT(7) #define BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B 5 @@ -689,6 +774,7 @@ #define BIT_AFE_LDO_SWR_CHECK_8822B(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) #define BIT_GET_AFE_LDO_SWR_CHECK_8822B(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B) + #define BIT_LED0PL_8822B BIT(4) #define BIT_LED0SV_8822B BIT(3) @@ -698,6 +784,7 @@ #define BIT_GET_LED0CM_8822B(x) (((x) >> BIT_SHIFT_LED0CM_8822B) & BIT_MASK_LED0CM_8822B) + /* 2 REG_FSIMR_8822B */ #define BIT_FS_PDNINT_EN_8822B BIT(31) #define BIT_NFC_INT_PAD_EN_8822B BIT(30) @@ -814,24 +901,28 @@ #define BIT_GET_GPIO_MOD_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) & BIT_MASK_GPIO_MOD_15_TO_8_8822B) + #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B 16 #define BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B 0xff #define BIT_GPIO_IO_SEL_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) #define BIT_GET_GPIO_IO_SEL_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) + #define BIT_SHIFT_GPIO_OUT_15_TO_8_8822B 8 #define BIT_MASK_GPIO_OUT_15_TO_8_8822B 0xff #define BIT_GPIO_OUT_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822B) << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) #define BIT_GET_GPIO_OUT_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) & BIT_MASK_GPIO_OUT_15_TO_8_8822B) + #define BIT_SHIFT_GPIO_IN_15_TO_8_8822B 0 #define BIT_MASK_GPIO_IN_15_TO_8_8822B 0xff #define BIT_GPIO_IN_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8822B) << BIT_SHIFT_GPIO_IN_15_TO_8_8822B) #define BIT_GET_GPIO_IN_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822B) & BIT_MASK_GPIO_IN_15_TO_8_8822B) + /* 2 REG_PAD_CTRL1_8822B */ #define BIT_PAPE_WLBT_SEL_8822B BIT(29) #define BIT_LNAON_WLBT_SEL_8822B BIT(28) @@ -850,6 +941,7 @@ #define BIT_BTGP_GPIO_SL_8822B(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8822B) << BIT_SHIFT_BTGP_GPIO_SL_8822B) #define BIT_GET_BTGP_GPIO_SL_8822B(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822B) & BIT_MASK_BTGP_GPIO_SL_8822B) + #define BIT_PAD_SDIO_SR_8822B BIT(14) #define BIT_GPIO14_OUTPUT_PL_8822B BIT(13) #define BIT_HOST_WAKE_PAD_PULL_EN_8822B BIT(12) @@ -903,6 +995,7 @@ #define BIT_GET_WLCLK_PHASE_8822B(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8822B) & BIT_MASK_WLCLK_PHASE_8822B) + /* 2 REG_SYS_SDIO_CTRL_8822B */ #define BIT_DBG_GNT_WL_BT_8822B BIT(27) #define BIT_LTE_MUX_CTRL_PATH_8822B BIT(26) @@ -923,6 +1016,7 @@ #define BIT_TSFT_SEL_8822B(x) (((x) & BIT_MASK_TSFT_SEL_8822B) << BIT_SHIFT_TSFT_SEL_8822B) #define BIT_GET_TSFT_SEL_8822B(x) (((x) >> BIT_SHIFT_TSFT_SEL_8822B) & BIT_MASK_TSFT_SEL_8822B) + #define BIT_USB_HOST_PWR_OFF_EN_8822B BIT(12) #define BIT_SYM_LPS_BLOCK_EN_8822B BIT(11) #define BIT_USB_LPM_ACT_EN_8822B BIT(10) @@ -934,6 +1028,7 @@ #define BIT_SDIO_PAD_E_8822B(x) (((x) & BIT_MASK_SDIO_PAD_E_8822B) << BIT_SHIFT_SDIO_PAD_E_8822B) #define BIT_GET_SDIO_PAD_E_8822B(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8822B) & BIT_MASK_SDIO_PAD_E_8822B) + #define BIT_USB_LPPLL_EN_8822B BIT(4) #define BIT_ROP_SW15_8822B BIT(2) #define BIT_PCI_CKRDY_OPT_8822B BIT(1) @@ -951,35 +1046,41 @@ #define BIT_GET_AUTO_ZCD_IN_CODE_8822B(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B) + #define BIT_SHIFT_ZCD_CODE_IN_L_8822B 16 #define BIT_MASK_ZCD_CODE_IN_L_8822B 0x1f #define BIT_ZCD_CODE_IN_L_8822B(x) (((x) & BIT_MASK_ZCD_CODE_IN_L_8822B) << BIT_SHIFT_ZCD_CODE_IN_L_8822B) #define BIT_GET_ZCD_CODE_IN_L_8822B(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822B) & BIT_MASK_ZCD_CODE_IN_L_8822B) + #define BIT_SHIFT_LDO_HV5_DUMMY_8822B 14 #define BIT_MASK_LDO_HV5_DUMMY_8822B 0x3 #define BIT_LDO_HV5_DUMMY_8822B(x) (((x) & BIT_MASK_LDO_HV5_DUMMY_8822B) << BIT_SHIFT_LDO_HV5_DUMMY_8822B) #define BIT_GET_LDO_HV5_DUMMY_8822B(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8822B) & BIT_MASK_LDO_HV5_DUMMY_8822B) + #define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B 12 #define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B 0x3 #define BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) #define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) + #define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B 10 #define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B 0x3 #define BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) #define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) + #define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B 8 #define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B 0x3 #define BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) #define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8822B(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) + #define BIT_REG_BYPASS_L_8822B BIT(7) #define BIT_REG_LDOF_L_8822B BIT(6) #define BIT_REG_TYPE_L_V1_8822B BIT(5) @@ -990,6 +1091,7 @@ #define BIT_CFC_L_8822B(x) (((x) & BIT_MASK_CFC_L_8822B) << BIT_SHIFT_CFC_L_8822B) #define BIT_GET_CFC_L_8822B(x) (((x) >> BIT_SHIFT_CFC_L_8822B) & BIT_MASK_CFC_L_8822B) + #define BIT_REG_OCPS_L_V1_8822B BIT(0) /* 2 REG_MCUFW_CTRL_8822B */ @@ -999,6 +1101,7 @@ #define BIT_RPWM_8822B(x) (((x) & BIT_MASK_RPWM_8822B) << BIT_SHIFT_RPWM_8822B) #define BIT_GET_RPWM_8822B(x) (((x) >> BIT_SHIFT_RPWM_8822B) & BIT_MASK_RPWM_8822B) + #define BIT_ANA_PORT_EN_8822B BIT(22) #define BIT_MAC_PORT_EN_8822B BIT(21) #define BIT_BOOT_FSPI_EN_8822B BIT(20) @@ -1009,6 +1112,7 @@ #define BIT_ROM_PGE_8822B(x) (((x) & BIT_MASK_ROM_PGE_8822B) << BIT_SHIFT_ROM_PGE_8822B) #define BIT_GET_ROM_PGE_8822B(x) (((x) >> BIT_SHIFT_ROM_PGE_8822B) & BIT_MASK_ROM_PGE_8822B) + #define BIT_FW_INIT_RDY_8822B BIT(15) #define BIT_FW_DW_RDY_8822B BIT(14) @@ -1017,6 +1121,7 @@ #define BIT_CPU_CLK_SEL_8822B(x) (((x) & BIT_MASK_CPU_CLK_SEL_8822B) << BIT_SHIFT_CPU_CLK_SEL_8822B) #define BIT_GET_CPU_CLK_SEL_8822B(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8822B) & BIT_MASK_CPU_CLK_SEL_8822B) + #define BIT_CCLK_CHG_MASK_8822B BIT(11) #define BIT_EMEM__TXBUF_CHKSUM_OK_8822B BIT(10) #define BIT_EMEM_TXBUF_DW_RDY_8822B BIT(9) @@ -1038,6 +1143,7 @@ #define BIT_GET_LBKTST_8822B(x) (((x) >> BIT_SHIFT_LBKTST_8822B) & BIT_MASK_LBKTST_8822B) + /* 2 REG_HMEBOX_E0_E1_8822B */ #define BIT_SHIFT_HOST_MSG_E1_8822B 16 @@ -1046,12 +1152,14 @@ #define BIT_GET_HOST_MSG_E1_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8822B) & BIT_MASK_HOST_MSG_E1_8822B) + #define BIT_SHIFT_HOST_MSG_E0_8822B 0 #define BIT_MASK_HOST_MSG_E0_8822B 0xffff #define BIT_HOST_MSG_E0_8822B(x) (((x) & BIT_MASK_HOST_MSG_E0_8822B) << BIT_SHIFT_HOST_MSG_E0_8822B) #define BIT_GET_HOST_MSG_E0_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8822B) & BIT_MASK_HOST_MSG_E0_8822B) + /* 2 REG_HMEBOX_E2_E3_8822B */ #define BIT_SHIFT_HOST_MSG_E3_8822B 16 @@ -1060,12 +1168,14 @@ #define BIT_GET_HOST_MSG_E3_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8822B) & BIT_MASK_HOST_MSG_E3_8822B) + #define BIT_SHIFT_HOST_MSG_E2_8822B 0 #define BIT_MASK_HOST_MSG_E2_8822B 0xffff #define BIT_HOST_MSG_E2_8822B(x) (((x) & BIT_MASK_HOST_MSG_E2_8822B) << BIT_SHIFT_HOST_MSG_E2_8822B) #define BIT_GET_HOST_MSG_E2_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8822B) & BIT_MASK_HOST_MSG_E2_8822B) + /* 2 REG_WLLPS_CTRL_8822B */ #define BIT_WLLPSOP_EABM_8822B BIT(31) #define BIT_WLLPSOP_ACKF_8822B BIT(30) @@ -1085,11 +1195,13 @@ #define BIT_GET_LPLDH12_VADJ_STEP_DN_8822B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B) + #define BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B 8 #define BIT_MASK_V15ADJ_L1_STEP_DN_8822B 0x7 #define BIT_V15ADJ_L1_STEP_DN_8822B(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B) << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) #define BIT_GET_V15ADJ_L1_STEP_DN_8822B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B) + #define BIT_REGU_32K_CLK_EN_8822B BIT(1) #define BIT_WL_LPS_EN_8822B BIT(0) @@ -1104,24 +1216,28 @@ #define BIT_GET_REF_SEL_8822B(x) (((x) >> BIT_SHIFT_REF_SEL_8822B) & BIT_MASK_REF_SEL_8822B) + #define BIT_SHIFT_F0F_SDM_8822B 12 #define BIT_MASK_F0F_SDM_8822B 0x1fff #define BIT_F0F_SDM_8822B(x) (((x) & BIT_MASK_F0F_SDM_8822B) << BIT_SHIFT_F0F_SDM_8822B) #define BIT_GET_F0F_SDM_8822B(x) (((x) >> BIT_SHIFT_F0F_SDM_8822B) & BIT_MASK_F0F_SDM_8822B) + #define BIT_SHIFT_F0N_SDM_8822B 9 #define BIT_MASK_F0N_SDM_8822B 0x7 #define BIT_F0N_SDM_8822B(x) (((x) & BIT_MASK_F0N_SDM_8822B) << BIT_SHIFT_F0N_SDM_8822B) #define BIT_GET_F0N_SDM_8822B(x) (((x) >> BIT_SHIFT_F0N_SDM_8822B) & BIT_MASK_F0N_SDM_8822B) + #define BIT_SHIFT_DIVN_SDM_8822B 3 #define BIT_MASK_DIVN_SDM_8822B 0x3f #define BIT_DIVN_SDM_8822B(x) (((x) & BIT_MASK_DIVN_SDM_8822B) << BIT_SHIFT_DIVN_SDM_8822B) #define BIT_GET_DIVN_SDM_8822B(x) (((x) >> BIT_SHIFT_DIVN_SDM_8822B) & BIT_MASK_DIVN_SDM_8822B) + /* 2 REG_GPIO_DEBOUNCE_CTRL_8822B */ #define BIT_WLGP_DBC1EN_8822B BIT(15) @@ -1130,6 +1246,7 @@ #define BIT_WLGP_DBC1_8822B(x) (((x) & BIT_MASK_WLGP_DBC1_8822B) << BIT_SHIFT_WLGP_DBC1_8822B) #define BIT_GET_WLGP_DBC1_8822B(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8822B) & BIT_MASK_WLGP_DBC1_8822B) + #define BIT_WLGP_DBC0EN_8822B BIT(7) #define BIT_SHIFT_WLGP_DBC0_8822B 0 @@ -1138,6 +1255,7 @@ #define BIT_GET_WLGP_DBC0_8822B(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8822B) & BIT_MASK_WLGP_DBC0_8822B) + /* 2 REG_RPWM2_8822B */ #define BIT_SHIFT_RPWM2_8822B 16 @@ -1146,6 +1264,7 @@ #define BIT_GET_RPWM2_8822B(x) (((x) >> BIT_SHIFT_RPWM2_8822B) & BIT_MASK_RPWM2_8822B) + /* 2 REG_SYSON_FSM_MON_8822B */ #define BIT_SHIFT_FSM_MON_SEL_8822B 24 @@ -1153,6 +1272,7 @@ #define BIT_FSM_MON_SEL_8822B(x) (((x) & BIT_MASK_FSM_MON_SEL_8822B) << BIT_SHIFT_FSM_MON_SEL_8822B) #define BIT_GET_FSM_MON_SEL_8822B(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8822B) & BIT_MASK_FSM_MON_SEL_8822B) + #define BIT_DOP_ELDO_8822B BIT(23) #define BIT_FSM_MON_UPD_8822B BIT(15) @@ -1162,6 +1282,7 @@ #define BIT_GET_FSM_PAR_8822B(x) (((x) >> BIT_SHIFT_FSM_PAR_8822B) & BIT_MASK_FSM_PAR_8822B) + /* 2 REG_AFE_CTRL6_8822B */ #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0 @@ -1170,6 +1291,7 @@ #define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) + /* 2 REG_PMC_DBG_CTRL1_8822B */ #define BIT_BT_INT_EN_8822B BIT(31) @@ -1178,6 +1300,7 @@ #define BIT_RD_WR_WIFI_BT_INFO_8822B(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) #define BIT_GET_RD_WR_WIFI_BT_INFO_8822B(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) + #define BIT_PMC_WR_OVF_8822B BIT(8) #define BIT_SHIFT_WLPMC_ERRINT_8822B 0 @@ -1186,6 +1309,7 @@ #define BIT_GET_WLPMC_ERRINT_8822B(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8822B) & BIT_MASK_WLPMC_ERRINT_8822B) + /* 2 REG_AFE_CTRL7_8822B */ #define BIT_SHIFT_SEL_V_8822B 30 @@ -1193,6 +1317,7 @@ #define BIT_SEL_V_8822B(x) (((x) & BIT_MASK_SEL_V_8822B) << BIT_SHIFT_SEL_V_8822B) #define BIT_GET_SEL_V_8822B(x) (((x) >> BIT_SHIFT_SEL_V_8822B) & BIT_MASK_SEL_V_8822B) + #define BIT_SEL_LDO_PC_8822B BIT(29) #define BIT_SHIFT_CK_MON_SEL_8822B 26 @@ -1200,6 +1325,7 @@ #define BIT_CK_MON_SEL_8822B(x) (((x) & BIT_MASK_CK_MON_SEL_8822B) << BIT_SHIFT_CK_MON_SEL_8822B) #define BIT_GET_CK_MON_SEL_8822B(x) (((x) >> BIT_SHIFT_CK_MON_SEL_8822B) & BIT_MASK_CK_MON_SEL_8822B) + #define BIT_CK_MON_EN_8822B BIT(25) #define BIT_FREF_EDGE_8822B BIT(24) #define BIT_CK320M_EN_8822B BIT(23) @@ -1328,6 +1454,7 @@ #define BIT_GET_DEBUG_ST_8822B(x) (((x) >> BIT_SHIFT_DEBUG_ST_8822B) & BIT_MASK_DEBUG_ST_8822B) + /* 2 REG_PAD_CTRL2_8822B */ #define BIT_USB3_USB2_TRANSITION_8822B BIT(20) @@ -1336,6 +1463,7 @@ #define BIT_USB23_SW_MODE_V1_8822B(x) (((x) & BIT_MASK_USB23_SW_MODE_V1_8822B) << BIT_SHIFT_USB23_SW_MODE_V1_8822B) #define BIT_GET_USB23_SW_MODE_V1_8822B(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822B) & BIT_MASK_USB23_SW_MODE_V1_8822B) + #define BIT_NO_PDN_CHIPOFF_V1_8822B BIT(17) #define BIT_RSM_EN_V1_8822B BIT(16) @@ -1344,6 +1472,7 @@ #define BIT_MATCH_CNT_8822B(x) (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B) #define BIT_GET_MATCH_CNT_8822B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B) + #define BIT_LD_B12V_EN_8822B BIT(7) #define BIT_EECS_IOSEL_V1_8822B BIT(6) #define BIT_EECS_DATA_O_V1_8822B BIT(5) @@ -1361,6 +1490,7 @@ #define BIT_EFUSE_BURN_GNT_8822B(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8822B) << BIT_SHIFT_EFUSE_BURN_GNT_8822B) #define BIT_GET_EFUSE_BURN_GNT_8822B(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822B) & BIT_MASK_EFUSE_BURN_GNT_8822B) + #define BIT_STOP_WL_PMC_8822B BIT(9) #define BIT_STOP_SYM_PMC_8822B BIT(8) #define BIT_REG_RST_WLPMC_8822B BIT(5) @@ -1374,6 +1504,7 @@ #define BIT_GET_SYSON_REG_ARB_8822B(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8822B) & BIT_MASK_SYSON_REG_ARB_8822B) + /* 2 REG_BIST_CTRL_8822B */ #define BIT_BIST_USB_DIS_8822B BIT(27) #define BIT_BIST_PCI_DIS_8822B BIT(26) @@ -1385,6 +1516,7 @@ #define BIT_BIST_RPT_SEL_8822B(x) (((x) & BIT_MASK_BIST_RPT_SEL_8822B) << BIT_SHIFT_BIST_RPT_SEL_8822B) #define BIT_GET_BIST_RPT_SEL_8822B(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8822B) & BIT_MASK_BIST_RPT_SEL_8822B) + #define BIT_BIST_RESUME_PS_8822B BIT(4) #define BIT_BIST_RESUME_8822B BIT(3) #define BIT_BIST_NORMAL_8822B BIT(2) @@ -1399,6 +1531,7 @@ #define BIT_GET_MBIST_REPORT_8822B(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8822B) & BIT_MASK_MBIST_REPORT_8822B) + /* 2 REG_MEM_CTRL_8822B */ #define BIT_UMEM_RME_8822B BIT(31) @@ -1408,42 +1541,49 @@ #define BIT_GET_BT_SPRAM_8822B(x) (((x) >> BIT_SHIFT_BT_SPRAM_8822B) & BIT_MASK_BT_SPRAM_8822B) + #define BIT_SHIFT_BT_ROM_8822B 24 #define BIT_MASK_BT_ROM_8822B 0xf #define BIT_BT_ROM_8822B(x) (((x) & BIT_MASK_BT_ROM_8822B) << BIT_SHIFT_BT_ROM_8822B) #define BIT_GET_BT_ROM_8822B(x) (((x) >> BIT_SHIFT_BT_ROM_8822B) & BIT_MASK_BT_ROM_8822B) + #define BIT_SHIFT_PCI_DPRAM_8822B 10 #define BIT_MASK_PCI_DPRAM_8822B 0x3 #define BIT_PCI_DPRAM_8822B(x) (((x) & BIT_MASK_PCI_DPRAM_8822B) << BIT_SHIFT_PCI_DPRAM_8822B) #define BIT_GET_PCI_DPRAM_8822B(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8822B) & BIT_MASK_PCI_DPRAM_8822B) + #define BIT_SHIFT_PCI_SPRAM_8822B 8 #define BIT_MASK_PCI_SPRAM_8822B 0x3 #define BIT_PCI_SPRAM_8822B(x) (((x) & BIT_MASK_PCI_SPRAM_8822B) << BIT_SHIFT_PCI_SPRAM_8822B) #define BIT_GET_PCI_SPRAM_8822B(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8822B) & BIT_MASK_PCI_SPRAM_8822B) + #define BIT_SHIFT_USB_SPRAM_8822B 6 #define BIT_MASK_USB_SPRAM_8822B 0x3 #define BIT_USB_SPRAM_8822B(x) (((x) & BIT_MASK_USB_SPRAM_8822B) << BIT_SHIFT_USB_SPRAM_8822B) #define BIT_GET_USB_SPRAM_8822B(x) (((x) >> BIT_SHIFT_USB_SPRAM_8822B) & BIT_MASK_USB_SPRAM_8822B) + #define BIT_SHIFT_USB_SPRF_8822B 4 #define BIT_MASK_USB_SPRF_8822B 0x3 #define BIT_USB_SPRF_8822B(x) (((x) & BIT_MASK_USB_SPRF_8822B) << BIT_SHIFT_USB_SPRF_8822B) #define BIT_GET_USB_SPRF_8822B(x) (((x) >> BIT_SHIFT_USB_SPRF_8822B) & BIT_MASK_USB_SPRF_8822B) + #define BIT_SHIFT_MCU_ROM_8822B 0 #define BIT_MASK_MCU_ROM_8822B 0xf #define BIT_MCU_ROM_8822B(x) (((x) & BIT_MASK_MCU_ROM_8822B) << BIT_SHIFT_MCU_ROM_8822B) #define BIT_GET_MCU_ROM_8822B(x) (((x) >> BIT_SHIFT_MCU_ROM_8822B) & BIT_MASK_MCU_ROM_8822B) + /* 2 REG_AFE_CTRL8_8822B */ #define BIT_SYN_AGPIO_8822B BIT(20) #define BIT_XTAL_LP_8822B BIT(4) @@ -1455,6 +1595,7 @@ #define BIT_GET_XTAL_SEL_TOK_8822B(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8822B) & BIT_MASK_XTAL_SEL_TOK_8822B) + /* 2 REG_USB_SIE_INTF_8822B */ #define BIT_RD_SEL_8822B BIT(31) #define BIT_USB_SIE_INTF_WE_V1_8822B BIT(30) @@ -1467,18 +1608,21 @@ #define BIT_GET_USB_SIE_INTF_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B) + #define BIT_SHIFT_USB_SIE_INTF_RD_8822B 8 #define BIT_MASK_USB_SIE_INTF_RD_8822B 0xff #define BIT_USB_SIE_INTF_RD_8822B(x) (((x) & BIT_MASK_USB_SIE_INTF_RD_8822B) << BIT_SHIFT_USB_SIE_INTF_RD_8822B) #define BIT_GET_USB_SIE_INTF_RD_8822B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822B) & BIT_MASK_USB_SIE_INTF_RD_8822B) + #define BIT_SHIFT_USB_SIE_INTF_WD_8822B 0 #define BIT_MASK_USB_SIE_INTF_WD_8822B 0xff #define BIT_USB_SIE_INTF_WD_8822B(x) (((x) & BIT_MASK_USB_SIE_INTF_WD_8822B) << BIT_SHIFT_USB_SIE_INTF_WD_8822B) #define BIT_GET_USB_SIE_INTF_WD_8822B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822B) & BIT_MASK_USB_SIE_INTF_WD_8822B) + /* 2 REG_PCIE_MIO_INTF_8822B */ #define BIT_PCIE_MIO_BYIOREG_8822B BIT(13) #define BIT_PCIE_MIO_RE_8822B BIT(12) @@ -1489,12 +1633,14 @@ #define BIT_GET_PCIE_MIO_WE_8822B(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8822B) & BIT_MASK_PCIE_MIO_WE_8822B) + #define BIT_SHIFT_PCIE_MIO_ADDR_8822B 0 #define BIT_MASK_PCIE_MIO_ADDR_8822B 0xff #define BIT_PCIE_MIO_ADDR_8822B(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8822B) << BIT_SHIFT_PCIE_MIO_ADDR_8822B) #define BIT_GET_PCIE_MIO_ADDR_8822B(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822B) & BIT_MASK_PCIE_MIO_ADDR_8822B) + /* 2 REG_PCIE_MIO_INTD_8822B */ #define BIT_SHIFT_PCIE_MIO_DATA_8822B 0 @@ -1503,6 +1649,7 @@ #define BIT_GET_PCIE_MIO_DATA_8822B(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822B) & BIT_MASK_PCIE_MIO_DATA_8822B) + /* 2 REG_WLRF1_8822B */ #define BIT_SHIFT_WLRF1_CTRL_8822B 24 @@ -1511,6 +1658,7 @@ #define BIT_GET_WLRF1_CTRL_8822B(x) (((x) >> BIT_SHIFT_WLRF1_CTRL_8822B) & BIT_MASK_WLRF1_CTRL_8822B) + /* 2 REG_SYS_CFG1_8822B */ #define BIT_SHIFT_TRP_ICFG_8822B 28 @@ -1518,6 +1666,7 @@ #define BIT_TRP_ICFG_8822B(x) (((x) & BIT_MASK_TRP_ICFG_8822B) << BIT_SHIFT_TRP_ICFG_8822B) #define BIT_GET_TRP_ICFG_8822B(x) (((x) >> BIT_SHIFT_TRP_ICFG_8822B) & BIT_MASK_TRP_ICFG_8822B) + #define BIT_RF_TYPE_ID_8822B BIT(27) #define BIT_BD_HCI_SEL_8822B BIT(26) #define BIT_BD_PKG_SEL_8822B BIT(25) @@ -1532,11 +1681,13 @@ #define BIT_GET_VENDOR_ID_8822B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8822B) & BIT_MASK_VENDOR_ID_8822B) + #define BIT_SHIFT_CHIP_VER_8822B 12 #define BIT_MASK_CHIP_VER_8822B 0xf #define BIT_CHIP_VER_8822B(x) (((x) & BIT_MASK_CHIP_VER_8822B) << BIT_SHIFT_CHIP_VER_8822B) #define BIT_GET_CHIP_VER_8822B(x) (((x) >> BIT_SHIFT_CHIP_VER_8822B) & BIT_MASK_CHIP_VER_8822B) + #define BIT_BD_MAC3_8822B BIT(11) #define BIT_BD_MAC1_8822B BIT(10) #define BIT_BD_MAC2_8822B BIT(9) @@ -1557,6 +1708,7 @@ #define BIT_RF_RL_ID_8822B(x) (((x) & BIT_MASK_RF_RL_ID_8822B) << BIT_SHIFT_RF_RL_ID_8822B) #define BIT_GET_RF_RL_ID_8822B(x) (((x) >> BIT_SHIFT_RF_RL_ID_8822B) & BIT_MASK_RF_RL_ID_8822B) + #define BIT_HPHY_ICFG_8822B BIT(19) #define BIT_SHIFT_SEL_0XC0_8822B 16 @@ -1565,11 +1717,13 @@ #define BIT_GET_SEL_0XC0_8822B(x) (((x) >> BIT_SHIFT_SEL_0XC0_8822B) & BIT_MASK_SEL_0XC0_8822B) + #define BIT_SHIFT_HCI_SEL_V3_8822B 12 #define BIT_MASK_HCI_SEL_V3_8822B 0x7 #define BIT_HCI_SEL_V3_8822B(x) (((x) & BIT_MASK_HCI_SEL_V3_8822B) << BIT_SHIFT_HCI_SEL_V3_8822B) #define BIT_GET_HCI_SEL_V3_8822B(x) (((x) >> BIT_SHIFT_HCI_SEL_V3_8822B) & BIT_MASK_HCI_SEL_V3_8822B) + #define BIT_USB_OPERATION_MODE_8822B BIT(10) #define BIT_BT_PDN_8822B BIT(9) #define BIT_AUTO_WLPON_8822B BIT(8) @@ -1582,12 +1736,14 @@ #define BIT_GET_PAD_HCI_SEL_V1_8822B(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1_8822B) & BIT_MASK_PAD_HCI_SEL_V1_8822B) + #define BIT_SHIFT_EFS_HCI_SEL_V1_8822B 0 #define BIT_MASK_EFS_HCI_SEL_V1_8822B 0x7 #define BIT_EFS_HCI_SEL_V1_8822B(x) (((x) & BIT_MASK_EFS_HCI_SEL_V1_8822B) << BIT_SHIFT_EFS_HCI_SEL_V1_8822B) #define BIT_GET_EFS_HCI_SEL_V1_8822B(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822B) & BIT_MASK_EFS_HCI_SEL_V1_8822B) + /* 2 REG_SYS_STATUS2_8822B */ #define BIT_SIO_ALDN_8822B BIT(19) #define BIT_USB_ALDN_8822B BIT(18) @@ -1600,12 +1756,14 @@ #define BIT_GET_EPVID1_8822B(x) (((x) >> BIT_SHIFT_EPVID1_8822B) & BIT_MASK_EPVID1_8822B) + #define BIT_SHIFT_EPVID0_8822B 0 #define BIT_MASK_EPVID0_8822B 0xff #define BIT_EPVID0_8822B(x) (((x) & BIT_MASK_EPVID0_8822B) << BIT_SHIFT_EPVID0_8822B) #define BIT_GET_EPVID0_8822B(x) (((x) >> BIT_SHIFT_EPVID0_8822B) & BIT_MASK_EPVID0_8822B) + /* 2 REG_SYS_CFG2_8822B */ #define BIT_HCI_SEL_EMBEDED_8822B BIT(8) @@ -1615,6 +1773,7 @@ #define BIT_GET_HW_ID_8822B(x) (((x) >> BIT_SHIFT_HW_ID_8822B) & BIT_MASK_HW_ID_8822B) + /* 2 REG_SYS_CFG3_8822B */ #define BIT_PWC_MA33V_8822B BIT(15) #define BIT_PWC_MA12V_8822B BIT(14) @@ -1645,6 +1804,7 @@ #define BIT_GET_CPU_DMEM_CON_8822B(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8822B) & BIT_MASK_CPU_DMEM_CON_8822B) + /* 2 REG_BOOT_REASON_8822B */ #define BIT_SHIFT_BOOT_REASON_8822B 0 @@ -1653,6 +1813,7 @@ #define BIT_GET_BOOT_REASON_8822B(x) (((x) >> BIT_SHIFT_BOOT_REASON_8822B) & BIT_MASK_BOOT_REASON_8822B) + /* 2 REG_NFCPAD_CTRL_8822B */ #define BIT_PAD_SHUTDW_8822B BIT(18) #define BIT_SYSON_NFC_PAD_8822B BIT(17) @@ -1668,18 +1829,21 @@ #define BIT_GET_NFCPAD_IO_SEL_8822B(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8822B) & BIT_MASK_NFCPAD_IO_SEL_8822B) + #define BIT_SHIFT_NFCPAD_OUT_8822B 4 #define BIT_MASK_NFCPAD_OUT_8822B 0xf #define BIT_NFCPAD_OUT_8822B(x) (((x) & BIT_MASK_NFCPAD_OUT_8822B) << BIT_SHIFT_NFCPAD_OUT_8822B) #define BIT_GET_NFCPAD_OUT_8822B(x) (((x) >> BIT_SHIFT_NFCPAD_OUT_8822B) & BIT_MASK_NFCPAD_OUT_8822B) + #define BIT_SHIFT_NFCPAD_IN_8822B 0 #define BIT_MASK_NFCPAD_IN_8822B 0xf #define BIT_NFCPAD_IN_8822B(x) (((x) & BIT_MASK_NFCPAD_IN_8822B) << BIT_SHIFT_NFCPAD_IN_8822B) #define BIT_GET_NFCPAD_IN_8822B(x) (((x) >> BIT_SHIFT_NFCPAD_IN_8822B) & BIT_MASK_NFCPAD_IN_8822B) + /* 2 REG_HIMR2_8822B */ #define BIT_BCNDMAINT_P4_MSK_8822B BIT(31) #define BIT_BCNDMAINT_P3_MSK_8822B BIT(30) @@ -1802,6 +1966,7 @@ #define BIT_GET_H2C_PKT_READADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822B) & BIT_MASK_H2C_PKT_READADDR_8822B) + /* 2 REG_H2C_PKT_WRITEADDR_8822B */ #define BIT_SHIFT_H2C_PKT_WRITEADDR_8822B 0 @@ -1810,6 +1975,7 @@ #define BIT_GET_H2C_PKT_WRITEADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) & BIT_MASK_H2C_PKT_WRITEADDR_8822B) + /* 2 REG_MEM_PWR_CRTL_8822B */ #define BIT_MEM_BB_SD_8822B BIT(17) #define BIT_MEM_BB_DS_8822B BIT(16) @@ -1833,6 +1999,7 @@ #define BIT_GET_FW_DBG0_8822B(x) (((x) >> BIT_SHIFT_FW_DBG0_8822B) & BIT_MASK_FW_DBG0_8822B) + /* 2 REG_FW_DBG1_8822B */ #define BIT_SHIFT_FW_DBG1_8822B 0 @@ -1841,6 +2008,7 @@ #define BIT_GET_FW_DBG1_8822B(x) (((x) >> BIT_SHIFT_FW_DBG1_8822B) & BIT_MASK_FW_DBG1_8822B) + /* 2 REG_FW_DBG2_8822B */ #define BIT_SHIFT_FW_DBG2_8822B 0 @@ -1849,6 +2017,7 @@ #define BIT_GET_FW_DBG2_8822B(x) (((x) >> BIT_SHIFT_FW_DBG2_8822B) & BIT_MASK_FW_DBG2_8822B) + /* 2 REG_FW_DBG3_8822B */ #define BIT_SHIFT_FW_DBG3_8822B 0 @@ -1857,6 +2026,7 @@ #define BIT_GET_FW_DBG3_8822B(x) (((x) >> BIT_SHIFT_FW_DBG3_8822B) & BIT_MASK_FW_DBG3_8822B) + /* 2 REG_FW_DBG4_8822B */ #define BIT_SHIFT_FW_DBG4_8822B 0 @@ -1865,6 +2035,7 @@ #define BIT_GET_FW_DBG4_8822B(x) (((x) >> BIT_SHIFT_FW_DBG4_8822B) & BIT_MASK_FW_DBG4_8822B) + /* 2 REG_FW_DBG5_8822B */ #define BIT_SHIFT_FW_DBG5_8822B 0 @@ -1873,6 +2044,7 @@ #define BIT_GET_FW_DBG5_8822B(x) (((x) >> BIT_SHIFT_FW_DBG5_8822B) & BIT_MASK_FW_DBG5_8822B) + /* 2 REG_FW_DBG6_8822B */ #define BIT_SHIFT_FW_DBG6_8822B 0 @@ -1881,6 +2053,7 @@ #define BIT_GET_FW_DBG6_8822B(x) (((x) >> BIT_SHIFT_FW_DBG6_8822B) & BIT_MASK_FW_DBG6_8822B) + /* 2 REG_FW_DBG7_8822B */ #define BIT_SHIFT_FW_DBG7_8822B 0 @@ -1889,6 +2062,7 @@ #define BIT_GET_FW_DBG7_8822B(x) (((x) >> BIT_SHIFT_FW_DBG7_8822B) & BIT_MASK_FW_DBG7_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_CR_8822B */ @@ -1899,17 +2073,20 @@ #define BIT_GET_LBMODE_8822B(x) (((x) >> BIT_SHIFT_LBMODE_8822B) & BIT_MASK_LBMODE_8822B) + #define BIT_SHIFT_NETYPE1_8822B 18 #define BIT_MASK_NETYPE1_8822B 0x3 #define BIT_NETYPE1_8822B(x) (((x) & BIT_MASK_NETYPE1_8822B) << BIT_SHIFT_NETYPE1_8822B) #define BIT_GET_NETYPE1_8822B(x) (((x) >> BIT_SHIFT_NETYPE1_8822B) & BIT_MASK_NETYPE1_8822B) + #define BIT_SHIFT_NETYPE0_8822B 16 #define BIT_MASK_NETYPE0_8822B 0x3 #define BIT_NETYPE0_8822B(x) (((x) & BIT_MASK_NETYPE0_8822B) << BIT_SHIFT_NETYPE0_8822B) #define BIT_GET_NETYPE0_8822B(x) (((x) >> BIT_SHIFT_NETYPE0_8822B) & BIT_MASK_NETYPE0_8822B) + #define BIT_I2C_MAILBOX_EN_8822B BIT(12) #define BIT_SHCUT_EN_8822B BIT(11) #define BIT_32K_CAL_TMR_EN_8822B BIT(10) @@ -1924,6 +2101,15 @@ #define BIT_HCI_RXDMA_EN_8822B BIT(1) #define BIT_HCI_TXDMA_EN_8822B BIT(0) +/* 2 REG_PKT_BUFF_ACCESS_CTRL_8822B */ + +#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822B 0 +#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822B 0xff +#define BIT_PKT_BUFF_ACCESS_CTRL_8822B(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822B) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822B) +#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8822B(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822B) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822B) + + + /* 2 REG_TSF_CLK_STATE_8822B */ #define BIT_TSF_CLK_STABLE_8822B BIT(15) @@ -1935,35 +2121,41 @@ #define BIT_GET_TXDMA_HIQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822B) & BIT_MASK_TXDMA_HIQ_MAP_8822B) + #define BIT_SHIFT_TXDMA_MGQ_MAP_8822B 12 #define BIT_MASK_TXDMA_MGQ_MAP_8822B 0x3 #define BIT_TXDMA_MGQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8822B) << BIT_SHIFT_TXDMA_MGQ_MAP_8822B) #define BIT_GET_TXDMA_MGQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822B) & BIT_MASK_TXDMA_MGQ_MAP_8822B) + #define BIT_SHIFT_TXDMA_BKQ_MAP_8822B 10 #define BIT_MASK_TXDMA_BKQ_MAP_8822B 0x3 #define BIT_TXDMA_BKQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8822B) << BIT_SHIFT_TXDMA_BKQ_MAP_8822B) #define BIT_GET_TXDMA_BKQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822B) & BIT_MASK_TXDMA_BKQ_MAP_8822B) + #define BIT_SHIFT_TXDMA_BEQ_MAP_8822B 8 #define BIT_MASK_TXDMA_BEQ_MAP_8822B 0x3 #define BIT_TXDMA_BEQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8822B) << BIT_SHIFT_TXDMA_BEQ_MAP_8822B) #define BIT_GET_TXDMA_BEQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822B) & BIT_MASK_TXDMA_BEQ_MAP_8822B) + #define BIT_SHIFT_TXDMA_VIQ_MAP_8822B 6 #define BIT_MASK_TXDMA_VIQ_MAP_8822B 0x3 #define BIT_TXDMA_VIQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8822B) << BIT_SHIFT_TXDMA_VIQ_MAP_8822B) #define BIT_GET_TXDMA_VIQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822B) & BIT_MASK_TXDMA_VIQ_MAP_8822B) + #define BIT_SHIFT_TXDMA_VOQ_MAP_8822B 4 #define BIT_MASK_TXDMA_VOQ_MAP_8822B 0x3 #define BIT_TXDMA_VOQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8822B) << BIT_SHIFT_TXDMA_VOQ_MAP_8822B) #define BIT_GET_TXDMA_VOQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822B) & BIT_MASK_TXDMA_VOQ_MAP_8822B) + #define BIT_RXDMA_AGG_EN_8822B BIT(2) #define BIT_RXSHFT_EN_8822B BIT(1) #define BIT_RXDMA_ARBBW_EN_8822B BIT(0) @@ -1976,12 +2168,14 @@ #define BIT_GET_RXFFOVFL_RSV_V2_8822B(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) & BIT_MASK_RXFFOVFL_RSV_V2_8822B) + #define BIT_SHIFT_TXPKTBUF_PGBNDY_8822B 0 #define BIT_MASK_TXPKTBUF_PGBNDY_8822B 0xff #define BIT_TXPKTBUF_PGBNDY_8822B(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8822B) << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) #define BIT_GET_TXPKTBUF_PGBNDY_8822B(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) & BIT_MASK_TXPKTBUF_PGBNDY_8822B) + /* 2 REG_PTA_I2C_MBOX_8822B */ /* 2 REG_NOT_VALID_8822B */ @@ -1992,11 +2186,13 @@ #define BIT_GET_I2C_M_STATUS_8822B(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8822B) & BIT_MASK_I2C_M_STATUS_8822B) + #define BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B 4 #define BIT_MASK_I2C_M_BUS_GNT_FW_8822B 0x7 #define BIT_I2C_M_BUS_GNT_FW_8822B(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) #define BIT_GET_I2C_M_BUS_GNT_FW_8822B(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B) + #define BIT_I2C_M_GNT_FW_8822B BIT(3) #define BIT_SHIFT_I2C_M_SPEED_8822B 1 @@ -2004,6 +2200,7 @@ #define BIT_I2C_M_SPEED_8822B(x) (((x) & BIT_MASK_I2C_M_SPEED_8822B) << BIT_SHIFT_I2C_M_SPEED_8822B) #define BIT_GET_I2C_M_SPEED_8822B(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8822B) & BIT_MASK_I2C_M_SPEED_8822B) + #define BIT_I2C_M_UNLOCK_8822B BIT(0) /* 2 REG_RXFF_BNDY_8822B */ @@ -2016,6 +2213,7 @@ #define BIT_GET_RXFF0_BNDY_V2_8822B(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822B) & BIT_MASK_RXFF0_BNDY_V2_8822B) + /* 2 REG_FE1IMR_8822B */ #define BIT_FS_RXDMA2_DONE_INT_EN_8822B BIT(28) #define BIT_FS_RXDONE3_INT_EN_8822B BIT(27) @@ -2085,6 +2283,7 @@ #define BIT_GET_CPWM_MOD_8822B(x) (((x) >> BIT_SHIFT_CPWM_MOD_8822B) & BIT_MASK_CPWM_MOD_8822B) + /* 2 REG_FWIMR_8822B */ #define BIT_FS_TXBCNOK_MB7_INT_EN_8822B BIT(31) #define BIT_FS_TXBCNOK_MB6_INT_EN_8822B BIT(30) @@ -2204,6 +2403,7 @@ #define BIT_PKTBUF_WRITE_EN_8822B(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8822B) << BIT_SHIFT_PKTBUF_WRITE_EN_8822B) #define BIT_GET_PKTBUF_WRITE_EN_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822B) & BIT_MASK_PKTBUF_WRITE_EN_8822B) + #define BIT_TXRPTBUF_DBG_8822B BIT(23) /* 2 REG_NOT_VALID_8822B */ @@ -2216,6 +2416,7 @@ #define BIT_GET_PKTBUF_DBG_ADDR_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) & BIT_MASK_PKTBUF_DBG_ADDR_8822B) + /* 2 REG_PKTBUF_DBG_DATA_L_8822B */ #define BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B 0 @@ -2224,6 +2425,7 @@ #define BIT_GET_PKTBUF_DBG_DATA_L_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B) + /* 2 REG_PKTBUF_DBG_DATA_H_8822B */ #define BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B 0 @@ -2232,6 +2434,7 @@ #define BIT_GET_PKTBUF_DBG_DATA_H_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B) + /* 2 REG_CPWM2_8822B */ #define BIT_SHIFT_L0S_TO_RCVY_NUM_8822B 16 @@ -2239,6 +2442,7 @@ #define BIT_L0S_TO_RCVY_NUM_8822B(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822B) << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) #define BIT_GET_L0S_TO_RCVY_NUM_8822B(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) & BIT_MASK_L0S_TO_RCVY_NUM_8822B) + #define BIT_CPWM2_TOGGLING_8822B BIT(15) #define BIT_SHIFT_CPWM2_MOD_8822B 0 @@ -2247,6 +2451,7 @@ #define BIT_GET_CPWM2_MOD_8822B(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8822B) & BIT_MASK_CPWM2_MOD_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_TC0_CTRL_8822B */ @@ -2260,6 +2465,7 @@ #define BIT_GET_TC0DATA_8822B(x) (((x) >> BIT_SHIFT_TC0DATA_8822B) & BIT_MASK_TC0DATA_8822B) + /* 2 REG_TC1_CTRL_8822B */ #define BIT_TC1INT_EN_8822B BIT(26) #define BIT_TC1MODE_8822B BIT(25) @@ -2271,6 +2477,7 @@ #define BIT_GET_TC1DATA_8822B(x) (((x) >> BIT_SHIFT_TC1DATA_8822B) & BIT_MASK_TC1DATA_8822B) + /* 2 REG_TC2_CTRL_8822B */ #define BIT_TC2INT_EN_8822B BIT(26) #define BIT_TC2MODE_8822B BIT(25) @@ -2282,6 +2489,7 @@ #define BIT_GET_TC2DATA_8822B(x) (((x) >> BIT_SHIFT_TC2DATA_8822B) & BIT_MASK_TC2DATA_8822B) + /* 2 REG_TC3_CTRL_8822B */ #define BIT_TC3INT_EN_8822B BIT(26) #define BIT_TC3MODE_8822B BIT(25) @@ -2293,6 +2501,7 @@ #define BIT_GET_TC3DATA_8822B(x) (((x) >> BIT_SHIFT_TC3DATA_8822B) & BIT_MASK_TC3DATA_8822B) + /* 2 REG_TC4_CTRL_8822B */ #define BIT_TC4INT_EN_8822B BIT(26) #define BIT_TC4MODE_8822B BIT(25) @@ -2304,6 +2513,7 @@ #define BIT_GET_TC4DATA_8822B(x) (((x) >> BIT_SHIFT_TC4DATA_8822B) & BIT_MASK_TC4DATA_8822B) + /* 2 REG_TCUNIT_BASE_8822B */ #define BIT_SHIFT_TCUNIT_BASE_8822B 0 @@ -2312,6 +2522,7 @@ #define BIT_GET_TCUNIT_BASE_8822B(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8822B) & BIT_MASK_TCUNIT_BASE_8822B) + /* 2 REG_TC5_CTRL_8822B */ #define BIT_TC5INT_EN_8822B BIT(26) #define BIT_TC5MODE_8822B BIT(25) @@ -2323,6 +2534,7 @@ #define BIT_GET_TC5DATA_8822B(x) (((x) >> BIT_SHIFT_TC5DATA_8822B) & BIT_MASK_TC5DATA_8822B) + /* 2 REG_TC6_CTRL_8822B */ #define BIT_TC6INT_EN_8822B BIT(26) #define BIT_TC6MODE_8822B BIT(25) @@ -2334,6 +2546,7 @@ #define BIT_GET_TC6DATA_8822B(x) (((x) >> BIT_SHIFT_TC6DATA_8822B) & BIT_MASK_TC6DATA_8822B) + /* 2 REG_MBIST_FAIL_8822B */ #define BIT_SHIFT_8051_MBIST_FAIL_8822B 26 @@ -2342,24 +2555,28 @@ #define BIT_GET_8051_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8822B) & BIT_MASK_8051_MBIST_FAIL_8822B) + #define BIT_SHIFT_USB_MBIST_FAIL_8822B 24 #define BIT_MASK_USB_MBIST_FAIL_8822B 0x3 #define BIT_USB_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8822B) << BIT_SHIFT_USB_MBIST_FAIL_8822B) #define BIT_GET_USB_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8822B) & BIT_MASK_USB_MBIST_FAIL_8822B) + #define BIT_SHIFT_PCIE_MBIST_FAIL_8822B 16 #define BIT_MASK_PCIE_MBIST_FAIL_8822B 0x3f #define BIT_PCIE_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8822B) << BIT_SHIFT_PCIE_MBIST_FAIL_8822B) #define BIT_GET_PCIE_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8822B) & BIT_MASK_PCIE_MBIST_FAIL_8822B) + #define BIT_SHIFT_MAC_MBIST_FAIL_8822B 0 #define BIT_MASK_MAC_MBIST_FAIL_8822B 0xfff #define BIT_MAC_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_8822B) << BIT_SHIFT_MAC_MBIST_FAIL_8822B) #define BIT_GET_MAC_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8822B) & BIT_MASK_MAC_MBIST_FAIL_8822B) + /* 2 REG_MBIST_START_PAUSE_8822B */ #define BIT_SHIFT_8051_MBIST_START_PAUSE_8822B 26 @@ -2368,24 +2585,28 @@ #define BIT_GET_8051_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) & BIT_MASK_8051_MBIST_START_PAUSE_8822B) + #define BIT_SHIFT_USB_MBIST_START_PAUSE_8822B 24 #define BIT_MASK_USB_MBIST_START_PAUSE_8822B 0x3 #define BIT_USB_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8822B) << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) #define BIT_GET_USB_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) & BIT_MASK_USB_MBIST_START_PAUSE_8822B) + #define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B 16 #define BIT_MASK_PCIE_MBIST_START_PAUSE_8822B 0x3f #define BIT_PCIE_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) #define BIT_GET_PCIE_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) + #define BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B 0 #define BIT_MASK_MAC_MBIST_START_PAUSE_8822B 0xfff #define BIT_MAC_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B) << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) #define BIT_GET_MAC_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B) + /* 2 REG_MBIST_DONE_8822B */ #define BIT_SHIFT_8051_MBIST_DONE_8822B 26 @@ -2394,24 +2615,28 @@ #define BIT_GET_8051_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8822B) & BIT_MASK_8051_MBIST_DONE_8822B) + #define BIT_SHIFT_USB_MBIST_DONE_8822B 24 #define BIT_MASK_USB_MBIST_DONE_8822B 0x3 #define BIT_USB_MBIST_DONE_8822B(x) (((x) & BIT_MASK_USB_MBIST_DONE_8822B) << BIT_SHIFT_USB_MBIST_DONE_8822B) #define BIT_GET_USB_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8822B) & BIT_MASK_USB_MBIST_DONE_8822B) + #define BIT_SHIFT_PCIE_MBIST_DONE_8822B 16 #define BIT_MASK_PCIE_MBIST_DONE_8822B 0x3f #define BIT_PCIE_MBIST_DONE_8822B(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8822B) << BIT_SHIFT_PCIE_MBIST_DONE_8822B) #define BIT_GET_PCIE_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8822B) & BIT_MASK_PCIE_MBIST_DONE_8822B) + #define BIT_SHIFT_MAC_MBIST_DONE_8822B 0 #define BIT_MASK_MAC_MBIST_DONE_8822B 0xfff #define BIT_MAC_MBIST_DONE_8822B(x) (((x) & BIT_MASK_MAC_MBIST_DONE_8822B) << BIT_SHIFT_MAC_MBIST_DONE_8822B) #define BIT_GET_MAC_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8822B) & BIT_MASK_MAC_MBIST_DONE_8822B) + /* 2 REG_MBIST_FAIL_NRML_8822B */ #define BIT_SHIFT_MBIST_FAIL_NRML_8822B 0 @@ -2420,6 +2645,7 @@ #define BIT_GET_MBIST_FAIL_NRML_8822B(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8822B) & BIT_MASK_MBIST_FAIL_NRML_8822B) + /* 2 REG_AES_DECRPT_DATA_8822B */ #define BIT_SHIFT_IPS_CFG_ADDR_8822B 0 @@ -2428,6 +2654,7 @@ #define BIT_GET_IPS_CFG_ADDR_8822B(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822B) & BIT_MASK_IPS_CFG_ADDR_8822B) + /* 2 REG_AES_DECRPT_CFG_8822B */ #define BIT_SHIFT_IPS_CFG_DATA_8822B 0 @@ -2436,6 +2663,7 @@ #define BIT_GET_IPS_CFG_DATA_8822B(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8822B) & BIT_MASK_IPS_CFG_DATA_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_NOT_VALID_8822B */ @@ -2449,17 +2677,20 @@ #define BIT_GET_TEMP_VALUE_8822B(x) (((x) >> BIT_SHIFT_TEMP_VALUE_8822B) & BIT_MASK_TEMP_VALUE_8822B) + #define BIT_SHIFT_REG_TMETER_TIMER_8822B 8 #define BIT_MASK_REG_TMETER_TIMER_8822B 0xfff #define BIT_REG_TMETER_TIMER_8822B(x) (((x) & BIT_MASK_REG_TMETER_TIMER_8822B) << BIT_SHIFT_REG_TMETER_TIMER_8822B) #define BIT_GET_REG_TMETER_TIMER_8822B(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822B) & BIT_MASK_REG_TMETER_TIMER_8822B) + #define BIT_SHIFT_REG_TEMP_DELTA_8822B 2 #define BIT_MASK_REG_TEMP_DELTA_8822B 0x3f #define BIT_REG_TEMP_DELTA_8822B(x) (((x) & BIT_MASK_REG_TEMP_DELTA_8822B) << BIT_SHIFT_REG_TEMP_DELTA_8822B) #define BIT_GET_REG_TEMP_DELTA_8822B(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822B) & BIT_MASK_REG_TEMP_DELTA_8822B) + #define BIT_REG_TMETER_EN_8822B BIT(0) /* 2 REG_OSC_32K_CTRL_8822B */ @@ -2470,11 +2701,13 @@ #define BIT_GET_OSC_32K_CLKGEN_0_8822B(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) & BIT_MASK_OSC_32K_CLKGEN_0_8822B) + #define BIT_SHIFT_OSC_32K_RES_COMP_8822B 4 #define BIT_MASK_OSC_32K_RES_COMP_8822B 0x3 #define BIT_OSC_32K_RES_COMP_8822B(x) (((x) & BIT_MASK_OSC_32K_RES_COMP_8822B) << BIT_SHIFT_OSC_32K_RES_COMP_8822B) #define BIT_GET_OSC_32K_RES_COMP_8822B(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822B) & BIT_MASK_OSC_32K_RES_COMP_8822B) + #define BIT_OSC_32K_OUT_SEL_8822B BIT(3) #define BIT_ISO_WL_2_OSC_32K_8822B BIT(1) #define BIT_POW_CKGEN_8822B BIT(0) @@ -2489,12 +2722,14 @@ #define BIT_GET_CAL_32K_REG_ADDR_8822B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822B) & BIT_MASK_CAL_32K_REG_ADDR_8822B) + #define BIT_SHIFT_CAL_32K_REG_DATA_8822B 0 #define BIT_MASK_CAL_32K_REG_DATA_8822B 0xffff #define BIT_CAL_32K_REG_DATA_8822B(x) (((x) & BIT_MASK_CAL_32K_REG_DATA_8822B) << BIT_SHIFT_CAL_32K_REG_DATA_8822B) #define BIT_GET_CAL_32K_REG_DATA_8822B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822B) & BIT_MASK_CAL_32K_REG_DATA_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_C2HEVT_8822B */ @@ -2505,6 +2740,7 @@ #define BIT_GET_C2HEVT_MSG_8822B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_8822B) & BIT_MASK_C2HEVT_MSG_8822B) + /* 2 REG_SW_DEFINED_PAGE1_8822B */ #define BIT_SHIFT_SW_DEFINED_PAGE1_8822B 0 @@ -2513,6 +2749,7 @@ #define BIT_GET_SW_DEFINED_PAGE1_8822B(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8822B) & BIT_MASK_SW_DEFINED_PAGE1_8822B) + /* 2 REG_MCUTST_I_8822B */ #define BIT_SHIFT_MCUDMSG_I_8822B 0 @@ -2521,6 +2758,7 @@ #define BIT_GET_MCUDMSG_I_8822B(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8822B) & BIT_MASK_MCUDMSG_I_8822B) + /* 2 REG_MCUTST_II_8822B */ #define BIT_SHIFT_MCUDMSG_II_8822B 0 @@ -2529,6 +2767,7 @@ #define BIT_GET_MCUDMSG_II_8822B(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8822B) & BIT_MASK_MCUDMSG_II_8822B) + /* 2 REG_FMETHR_8822B */ #define BIT_FMSG_INT_8822B BIT(31) @@ -2538,6 +2777,7 @@ #define BIT_GET_FW_MSG_8822B(x) (((x) >> BIT_SHIFT_FW_MSG_8822B) & BIT_MASK_FW_MSG_8822B) + /* 2 REG_HMETFR_8822B */ #define BIT_SHIFT_HRCV_MSG_8822B 24 @@ -2545,6 +2785,7 @@ #define BIT_HRCV_MSG_8822B(x) (((x) & BIT_MASK_HRCV_MSG_8822B) << BIT_SHIFT_HRCV_MSG_8822B) #define BIT_GET_HRCV_MSG_8822B(x) (((x) >> BIT_SHIFT_HRCV_MSG_8822B) & BIT_MASK_HRCV_MSG_8822B) + #define BIT_INT_BOX3_8822B BIT(3) #define BIT_INT_BOX2_8822B BIT(2) #define BIT_INT_BOX1_8822B BIT(1) @@ -2558,6 +2799,7 @@ #define BIT_GET_HOST_MSG_0_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8822B) & BIT_MASK_HOST_MSG_0_8822B) + /* 2 REG_HMEBOX1_8822B */ #define BIT_SHIFT_HOST_MSG_1_8822B 0 @@ -2566,6 +2808,7 @@ #define BIT_GET_HOST_MSG_1_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8822B) & BIT_MASK_HOST_MSG_1_8822B) + /* 2 REG_HMEBOX2_8822B */ #define BIT_SHIFT_HOST_MSG_2_8822B 0 @@ -2574,6 +2817,7 @@ #define BIT_GET_HOST_MSG_2_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8822B) & BIT_MASK_HOST_MSG_2_8822B) + /* 2 REG_HMEBOX3_8822B */ #define BIT_SHIFT_HOST_MSG_3_8822B 0 @@ -2582,6 +2826,7 @@ #define BIT_GET_HOST_MSG_3_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8822B) & BIT_MASK_HOST_MSG_3_8822B) + /* 2 REG_LLT_INIT_8822B */ #define BIT_SHIFT_LLTE_RWM_8822B 30 @@ -2590,18 +2835,21 @@ #define BIT_GET_LLTE_RWM_8822B(x) (((x) >> BIT_SHIFT_LLTE_RWM_8822B) & BIT_MASK_LLTE_RWM_8822B) + #define BIT_SHIFT_LLTINI_PDATA_V1_8822B 16 #define BIT_MASK_LLTINI_PDATA_V1_8822B 0xfff #define BIT_LLTINI_PDATA_V1_8822B(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8822B) << BIT_SHIFT_LLTINI_PDATA_V1_8822B) #define BIT_GET_LLTINI_PDATA_V1_8822B(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8822B) & BIT_MASK_LLTINI_PDATA_V1_8822B) + #define BIT_SHIFT_LLTINI_HDATA_V1_8822B 0 #define BIT_MASK_LLTINI_HDATA_V1_8822B 0xfff #define BIT_LLTINI_HDATA_V1_8822B(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8822B) << BIT_SHIFT_LLTINI_HDATA_V1_8822B) #define BIT_GET_LLTINI_HDATA_V1_8822B(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8822B) & BIT_MASK_LLTINI_HDATA_V1_8822B) + /* 2 REG_LLT_INIT_ADDR_8822B */ #define BIT_SHIFT_LLTINI_ADDR_V1_8822B 0 @@ -2610,6 +2858,7 @@ #define BIT_GET_LLTINI_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8822B) & BIT_MASK_LLTINI_ADDR_V1_8822B) + /* 2 REG_BB_ACCESS_CTRL_8822B */ #define BIT_SHIFT_BB_WRITE_READ_8822B 30 @@ -2618,17 +2867,20 @@ #define BIT_GET_BB_WRITE_READ_8822B(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8822B) & BIT_MASK_BB_WRITE_READ_8822B) + #define BIT_SHIFT_BB_WRITE_EN_8822B 12 #define BIT_MASK_BB_WRITE_EN_8822B 0xf #define BIT_BB_WRITE_EN_8822B(x) (((x) & BIT_MASK_BB_WRITE_EN_8822B) << BIT_SHIFT_BB_WRITE_EN_8822B) #define BIT_GET_BB_WRITE_EN_8822B(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_8822B) & BIT_MASK_BB_WRITE_EN_8822B) + #define BIT_SHIFT_BB_ADDR_8822B 2 #define BIT_MASK_BB_ADDR_8822B 0x1ff #define BIT_BB_ADDR_8822B(x) (((x) & BIT_MASK_BB_ADDR_8822B) << BIT_SHIFT_BB_ADDR_8822B) #define BIT_GET_BB_ADDR_8822B(x) (((x) >> BIT_SHIFT_BB_ADDR_8822B) & BIT_MASK_BB_ADDR_8822B) + #define BIT_BB_ERRACC_8822B BIT(0) /* 2 REG_BB_ACCESS_DATA_8822B */ @@ -2639,6 +2891,7 @@ #define BIT_GET_BB_DATA_8822B(x) (((x) >> BIT_SHIFT_BB_DATA_8822B) & BIT_MASK_BB_DATA_8822B) + /* 2 REG_HMEBOX_E0_8822B */ #define BIT_SHIFT_HMEBOX_E0_8822B 0 @@ -2647,6 +2900,7 @@ #define BIT_GET_HMEBOX_E0_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8822B) & BIT_MASK_HMEBOX_E0_8822B) + /* 2 REG_HMEBOX_E1_8822B */ #define BIT_SHIFT_HMEBOX_E1_8822B 0 @@ -2655,6 +2909,7 @@ #define BIT_GET_HMEBOX_E1_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8822B) & BIT_MASK_HMEBOX_E1_8822B) + /* 2 REG_HMEBOX_E2_8822B */ #define BIT_SHIFT_HMEBOX_E2_8822B 0 @@ -2663,6 +2918,7 @@ #define BIT_GET_HMEBOX_E2_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8822B) & BIT_MASK_HMEBOX_E2_8822B) + /* 2 REG_HMEBOX_E3_8822B */ #define BIT_SHIFT_HMEBOX_E3_8822B 0 @@ -2671,6 +2927,7 @@ #define BIT_GET_HMEBOX_E3_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8822B) & BIT_MASK_HMEBOX_E3_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_CR_EXT_8822B */ @@ -2680,6 +2937,7 @@ #define BIT_PHY_REQ_DELAY_8822B(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8822B) << BIT_SHIFT_PHY_REQ_DELAY_8822B) #define BIT_GET_PHY_REQ_DELAY_8822B(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822B) & BIT_MASK_PHY_REQ_DELAY_8822B) + #define BIT_SPD_DOWN_8822B BIT(16) #define BIT_SHIFT_NETYPE4_8822B 4 @@ -2688,18 +2946,21 @@ #define BIT_GET_NETYPE4_8822B(x) (((x) >> BIT_SHIFT_NETYPE4_8822B) & BIT_MASK_NETYPE4_8822B) + #define BIT_SHIFT_NETYPE3_8822B 2 #define BIT_MASK_NETYPE3_8822B 0x3 #define BIT_NETYPE3_8822B(x) (((x) & BIT_MASK_NETYPE3_8822B) << BIT_SHIFT_NETYPE3_8822B) #define BIT_GET_NETYPE3_8822B(x) (((x) >> BIT_SHIFT_NETYPE3_8822B) & BIT_MASK_NETYPE3_8822B) + #define BIT_SHIFT_NETYPE2_8822B 0 #define BIT_MASK_NETYPE2_8822B 0x3 #define BIT_NETYPE2_8822B(x) (((x) & BIT_MASK_NETYPE2_8822B) << BIT_SHIFT_NETYPE2_8822B) #define BIT_GET_NETYPE2_8822B(x) (((x) >> BIT_SHIFT_NETYPE2_8822B) & BIT_MASK_NETYPE2_8822B) + /* 2 REG_FWFF_8822B */ #define BIT_SHIFT_PKTNUM_TH_V1_8822B 24 @@ -2708,18 +2969,21 @@ #define BIT_GET_PKTNUM_TH_V1_8822B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822B) & BIT_MASK_PKTNUM_TH_V1_8822B) + #define BIT_SHIFT_TIMER_TH_8822B 16 #define BIT_MASK_TIMER_TH_8822B 0xff #define BIT_TIMER_TH_8822B(x) (((x) & BIT_MASK_TIMER_TH_8822B) << BIT_SHIFT_TIMER_TH_8822B) #define BIT_GET_TIMER_TH_8822B(x) (((x) >> BIT_SHIFT_TIMER_TH_8822B) & BIT_MASK_TIMER_TH_8822B) + #define BIT_SHIFT_RXPKT1ENADDR_8822B 0 #define BIT_MASK_RXPKT1ENADDR_8822B 0xffff #define BIT_RXPKT1ENADDR_8822B(x) (((x) & BIT_MASK_RXPKT1ENADDR_8822B) << BIT_SHIFT_RXPKT1ENADDR_8822B) #define BIT_GET_RXPKT1ENADDR_8822B(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8822B) & BIT_MASK_RXPKT1ENADDR_8822B) + /* 2 REG_RXFF_PTR_V1_8822B */ /* 2 REG_NOT_VALID_8822B */ @@ -2730,6 +2994,7 @@ #define BIT_GET_RXFF0_RDPTR_V2_8822B(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822B) & BIT_MASK_RXFF0_RDPTR_V2_8822B) + /* 2 REG_RXFF_WTR_V1_8822B */ /* 2 REG_NOT_VALID_8822B */ @@ -2740,6 +3005,7 @@ #define BIT_GET_RXFF0_WTPTR_V2_8822B(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822B) & BIT_MASK_RXFF0_WTPTR_V2_8822B) + /* 2 REG_FE2IMR_8822B */ #define BIT__FE4ISR__IND_MSK_8822B BIT(29) #define BIT_FS_TXSC_DESC_DONE_INT_EN_8822B BIT(28) @@ -2976,6 +3242,7 @@ #define BIT_GET_MID_31TO0_8822B(x) (((x) >> BIT_SHIFT_MID_31TO0_8822B) & BIT_MASK_MID_31TO0_8822B) + /* 2 REG_SPWR1_8822B */ #define BIT_SHIFT_MID_63TO32_8822B 0 @@ -2984,6 +3251,7 @@ #define BIT_GET_MID_63TO32_8822B(x) (((x) >> BIT_SHIFT_MID_63TO32_8822B) & BIT_MASK_MID_63TO32_8822B) + /* 2 REG_SPWR2_8822B */ #define BIT_SHIFT_MID_95O64_8822B 0 @@ -2992,6 +3260,7 @@ #define BIT_GET_MID_95O64_8822B(x) (((x) >> BIT_SHIFT_MID_95O64_8822B) & BIT_MASK_MID_95O64_8822B) + /* 2 REG_SPWR3_8822B */ #define BIT_SHIFT_MID_127TO96_8822B 0 @@ -3000,6 +3269,7 @@ #define BIT_GET_MID_127TO96_8822B(x) (((x) >> BIT_SHIFT_MID_127TO96_8822B) & BIT_MASK_MID_127TO96_8822B) + /* 2 REG_POWSEQ_8822B */ #define BIT_SHIFT_SEQNUM_MID_8822B 16 @@ -3008,12 +3278,14 @@ #define BIT_GET_SEQNUM_MID_8822B(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8822B) & BIT_MASK_SEQNUM_MID_8822B) + #define BIT_SHIFT_REF_MID_8822B 0 #define BIT_MASK_REF_MID_8822B 0x7f #define BIT_REF_MID_8822B(x) (((x) & BIT_MASK_REF_MID_8822B) << BIT_SHIFT_REF_MID_8822B) #define BIT_GET_REF_MID_8822B(x) (((x) >> BIT_SHIFT_REF_MID_8822B) & BIT_MASK_REF_MID_8822B) + /* 2 REG_TC7_CTRL_V1_8822B */ #define BIT_TC7INT_EN_8822B BIT(26) #define BIT_TC7MODE_8822B BIT(25) @@ -3025,6 +3297,7 @@ #define BIT_GET_TC7DATA_8822B(x) (((x) >> BIT_SHIFT_TC7DATA_8822B) & BIT_MASK_TC7DATA_8822B) + /* 2 REG_TC8_CTRL_V1_8822B */ #define BIT_TC8INT_EN_8822B BIT(26) #define BIT_TC8MODE_8822B BIT(25) @@ -3036,6 +3309,7 @@ #define BIT_GET_TC8DATA_8822B(x) (((x) >> BIT_SHIFT_TC8DATA_8822B) & BIT_MASK_TC8DATA_8822B) + /* 2 REG_FT2IMR_8822B */ #define BIT_FS_CLI3_RX_UAPSDMD1_EN_8822B BIT(31) #define BIT_FS_CLI3_RX_UAPSDMD0_EN_8822B BIT(30) @@ -3100,6 +3374,7 @@ #define BIT_GET_FW_MSG2_8822B(x) (((x) >> BIT_SHIFT_FW_MSG2_8822B) & BIT_MASK_FW_MSG2_8822B) + /* 2 REG_MSG3_8822B */ #define BIT_SHIFT_FW_MSG3_8822B 0 @@ -3108,6 +3383,7 @@ #define BIT_GET_FW_MSG3_8822B(x) (((x) >> BIT_SHIFT_FW_MSG3_8822B) & BIT_MASK_FW_MSG3_8822B) + /* 2 REG_MSG4_8822B */ #define BIT_SHIFT_FW_MSG4_8822B 0 @@ -3116,6 +3392,7 @@ #define BIT_GET_FW_MSG4_8822B(x) (((x) >> BIT_SHIFT_FW_MSG4_8822B) & BIT_MASK_FW_MSG4_8822B) + /* 2 REG_MSG5_8822B */ #define BIT_SHIFT_FW_MSG5_8822B 0 @@ -3124,6 +3401,7 @@ #define BIT_GET_FW_MSG5_8822B(x) (((x) >> BIT_SHIFT_FW_MSG5_8822B) & BIT_MASK_FW_MSG5_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_FIFOPAGE_CTRL_1_8822B */ @@ -3134,12 +3412,14 @@ #define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822B(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B) + #define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B 0 #define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B 0xff #define BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) #define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822B(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) + /* 2 REG_FIFOPAGE_CTRL_2_8822B */ #define BIT_BCN_VALID_1_V1_8822B BIT(31) @@ -3148,6 +3428,7 @@ #define BIT_BCN_HEAD_1_V1_8822B(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8822B) << BIT_SHIFT_BCN_HEAD_1_V1_8822B) #define BIT_GET_BCN_HEAD_1_V1_8822B(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822B) & BIT_MASK_BCN_HEAD_1_V1_8822B) + #define BIT_BCN_VALID_V1_8822B BIT(15) #define BIT_SHIFT_BCN_HEAD_V1_8822B 0 @@ -3156,6 +3437,7 @@ #define BIT_GET_BCN_HEAD_V1_8822B(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8822B) & BIT_MASK_BCN_HEAD_V1_8822B) + /* 2 REG_AUTO_LLT_V1_8822B */ #define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 24 @@ -3164,17 +3446,20 @@ #define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) + #define BIT_SHIFT_LLT_FREE_PAGE_V1_8822B 8 #define BIT_MASK_LLT_FREE_PAGE_V1_8822B 0xffff #define BIT_LLT_FREE_PAGE_V1_8822B(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8822B) << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) #define BIT_GET_LLT_FREE_PAGE_V1_8822B(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) & BIT_MASK_LLT_FREE_PAGE_V1_8822B) + #define BIT_SHIFT_BLK_DESC_NUM_8822B 4 #define BIT_MASK_BLK_DESC_NUM_8822B 0xf #define BIT_BLK_DESC_NUM_8822B(x) (((x) & BIT_MASK_BLK_DESC_NUM_8822B) << BIT_SHIFT_BLK_DESC_NUM_8822B) #define BIT_GET_BLK_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8822B) & BIT_MASK_BLK_DESC_NUM_8822B) + #define BIT_R_BCN_HEAD_SEL_8822B BIT(3) #define BIT_R_EN_BCN_SW_HEAD_SEL_8822B BIT(2) #define BIT_LLT_DBG_SEL_8822B BIT(1) @@ -3191,6 +3476,7 @@ #define BIT_PG_UNDER_TH_V1_8822B(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8822B) << BIT_SHIFT_PG_UNDER_TH_V1_8822B) #define BIT_GET_PG_UNDER_TH_V1_8822B(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822B) & BIT_MASK_PG_UNDER_TH_V1_8822B) + #define BIT_RESTORE_H2C_ADDRESS_8822B BIT(15) #define BIT_SDIO_TXDESC_CHKSUM_EN_8822B BIT(13) #define BIT_RST_RDPTR_8822B BIT(12) @@ -3205,6 +3491,7 @@ #define BIT_GET_CHECK_OFFSET_8822B(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8822B) & BIT_MASK_CHECK_OFFSET_8822B) + /* 2 REG_TXDMA_STATUS_8822B */ #define BIT_HI_OQT_UDN_8822B BIT(17) #define BIT_HI_OQT_OVF_8822B BIT(16) @@ -3235,12 +3522,14 @@ #define BIT_GET_HPQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) & BIT_MASK_HPQ_HIGH_TH_V1_8822B) + #define BIT_SHIFT_HPQ_LOW_TH_V1_8822B 0 #define BIT_MASK_HPQ_LOW_TH_V1_8822B 0xfff #define BIT_HPQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8822B) << BIT_SHIFT_HPQ_LOW_TH_V1_8822B) #define BIT_GET_HPQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822B) & BIT_MASK_HPQ_LOW_TH_V1_8822B) + /* 2 REG_TQPNT2_8822B */ #define BIT_SHIFT_NPQ_HIGH_TH_V1_8822B 16 @@ -3249,12 +3538,14 @@ #define BIT_GET_NPQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) & BIT_MASK_NPQ_HIGH_TH_V1_8822B) + #define BIT_SHIFT_NPQ_LOW_TH_V1_8822B 0 #define BIT_MASK_NPQ_LOW_TH_V1_8822B 0xfff #define BIT_NPQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8822B) << BIT_SHIFT_NPQ_LOW_TH_V1_8822B) #define BIT_GET_NPQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822B) & BIT_MASK_NPQ_LOW_TH_V1_8822B) + /* 2 REG_TQPNT3_8822B */ #define BIT_SHIFT_LPQ_HIGH_TH_V1_8822B 16 @@ -3263,12 +3554,14 @@ #define BIT_GET_LPQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) & BIT_MASK_LPQ_HIGH_TH_V1_8822B) + #define BIT_SHIFT_LPQ_LOW_TH_V1_8822B 0 #define BIT_MASK_LPQ_LOW_TH_V1_8822B 0xfff #define BIT_LPQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8822B) << BIT_SHIFT_LPQ_LOW_TH_V1_8822B) #define BIT_GET_LPQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822B) & BIT_MASK_LPQ_LOW_TH_V1_8822B) + /* 2 REG_TQPNT4_8822B */ #define BIT_SHIFT_EXQ_HIGH_TH_V1_8822B 16 @@ -3277,12 +3570,14 @@ #define BIT_GET_EXQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) & BIT_MASK_EXQ_HIGH_TH_V1_8822B) + #define BIT_SHIFT_EXQ_LOW_TH_V1_8822B 0 #define BIT_MASK_EXQ_LOW_TH_V1_8822B 0xfff #define BIT_EXQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8822B) << BIT_SHIFT_EXQ_LOW_TH_V1_8822B) #define BIT_GET_EXQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822B) & BIT_MASK_EXQ_LOW_TH_V1_8822B) + /* 2 REG_RQPN_CTRL_1_8822B */ #define BIT_SHIFT_TXPKTNUM_H_8822B 16 @@ -3291,12 +3586,14 @@ #define BIT_GET_TXPKTNUM_H_8822B(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8822B) & BIT_MASK_TXPKTNUM_H_8822B) + #define BIT_SHIFT_TXPKTNUM_V2_8822B 0 #define BIT_MASK_TXPKTNUM_V2_8822B 0xffff #define BIT_TXPKTNUM_V2_8822B(x) (((x) & BIT_MASK_TXPKTNUM_V2_8822B) << BIT_SHIFT_TXPKTNUM_V2_8822B) #define BIT_GET_TXPKTNUM_V2_8822B(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2_8822B) & BIT_MASK_TXPKTNUM_V2_8822B) + /* 2 REG_RQPN_CTRL_2_8822B */ #define BIT_LD_RQPN_8822B BIT(31) #define BIT_EXQ_PUBLIC_DIS_V1_8822B BIT(19) @@ -3312,12 +3609,14 @@ #define BIT_GET_HPQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) & BIT_MASK_HPQ_AVAL_PG_V1_8822B) + #define BIT_SHIFT_HPQ_V1_8822B 0 #define BIT_MASK_HPQ_V1_8822B 0xfff #define BIT_HPQ_V1_8822B(x) (((x) & BIT_MASK_HPQ_V1_8822B) << BIT_SHIFT_HPQ_V1_8822B) #define BIT_GET_HPQ_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_V1_8822B) & BIT_MASK_HPQ_V1_8822B) + /* 2 REG_FIFOPAGE_INFO_2_8822B */ #define BIT_SHIFT_LPQ_AVAL_PG_V1_8822B 16 @@ -3326,12 +3625,14 @@ #define BIT_GET_LPQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) & BIT_MASK_LPQ_AVAL_PG_V1_8822B) + #define BIT_SHIFT_LPQ_V1_8822B 0 #define BIT_MASK_LPQ_V1_8822B 0xfff #define BIT_LPQ_V1_8822B(x) (((x) & BIT_MASK_LPQ_V1_8822B) << BIT_SHIFT_LPQ_V1_8822B) #define BIT_GET_LPQ_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_V1_8822B) & BIT_MASK_LPQ_V1_8822B) + /* 2 REG_FIFOPAGE_INFO_3_8822B */ #define BIT_SHIFT_NPQ_AVAL_PG_V1_8822B 16 @@ -3340,12 +3641,14 @@ #define BIT_GET_NPQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) & BIT_MASK_NPQ_AVAL_PG_V1_8822B) + #define BIT_SHIFT_NPQ_V1_8822B 0 #define BIT_MASK_NPQ_V1_8822B 0xfff #define BIT_NPQ_V1_8822B(x) (((x) & BIT_MASK_NPQ_V1_8822B) << BIT_SHIFT_NPQ_V1_8822B) #define BIT_GET_NPQ_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_V1_8822B) & BIT_MASK_NPQ_V1_8822B) + /* 2 REG_FIFOPAGE_INFO_4_8822B */ #define BIT_SHIFT_EXQ_AVAL_PG_V1_8822B 16 @@ -3354,12 +3657,14 @@ #define BIT_GET_EXQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) & BIT_MASK_EXQ_AVAL_PG_V1_8822B) + #define BIT_SHIFT_EXQ_V1_8822B 0 #define BIT_MASK_EXQ_V1_8822B 0xfff #define BIT_EXQ_V1_8822B(x) (((x) & BIT_MASK_EXQ_V1_8822B) << BIT_SHIFT_EXQ_V1_8822B) #define BIT_GET_EXQ_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_V1_8822B) & BIT_MASK_EXQ_V1_8822B) + /* 2 REG_FIFOPAGE_INFO_5_8822B */ #define BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B 16 @@ -3368,12 +3673,14 @@ #define BIT_GET_PUBQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B) + #define BIT_SHIFT_PUBQ_V1_8822B 0 #define BIT_MASK_PUBQ_V1_8822B 0xfff #define BIT_PUBQ_V1_8822B(x) (((x) & BIT_MASK_PUBQ_V1_8822B) << BIT_SHIFT_PUBQ_V1_8822B) #define BIT_GET_PUBQ_V1_8822B(x) (((x) >> BIT_SHIFT_PUBQ_V1_8822B) & BIT_MASK_PUBQ_V1_8822B) + /* 2 REG_H2C_HEAD_8822B */ #define BIT_SHIFT_H2C_HEAD_8822B 0 @@ -3382,6 +3689,7 @@ #define BIT_GET_H2C_HEAD_8822B(x) (((x) >> BIT_SHIFT_H2C_HEAD_8822B) & BIT_MASK_H2C_HEAD_8822B) + /* 2 REG_H2C_TAIL_8822B */ #define BIT_SHIFT_H2C_TAIL_8822B 0 @@ -3390,6 +3698,7 @@ #define BIT_GET_H2C_TAIL_8822B(x) (((x) >> BIT_SHIFT_H2C_TAIL_8822B) & BIT_MASK_H2C_TAIL_8822B) + /* 2 REG_H2C_READ_ADDR_8822B */ #define BIT_SHIFT_H2C_READ_ADDR_8822B 0 @@ -3398,6 +3707,7 @@ #define BIT_GET_H2C_READ_ADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8822B) & BIT_MASK_H2C_READ_ADDR_8822B) + /* 2 REG_H2C_WR_ADDR_8822B */ #define BIT_SHIFT_H2C_WR_ADDR_8822B 0 @@ -3406,6 +3716,7 @@ #define BIT_GET_H2C_WR_ADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8822B) & BIT_MASK_H2C_WR_ADDR_8822B) + /* 2 REG_H2C_INFO_8822B */ #define BIT_H2C_SPACE_VLD_8822B BIT(3) #define BIT_H2C_WR_ADDR_RST_8822B BIT(2) @@ -3416,6 +3727,7 @@ #define BIT_GET_H2C_LEN_SEL_8822B(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8822B) & BIT_MASK_H2C_LEN_SEL_8822B) + /* 2 REG_RXDMA_AGG_PG_TH_8822B */ #define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B 24 @@ -3424,24 +3736,28 @@ #define BIT_GET_RXDMA_AGG_OLD_MOD_8822B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B) & BIT_MASK_RXDMA_AGG_OLD_MOD_8822B) + #define BIT_SHIFT_PKT_NUM_WOL_8822B 16 #define BIT_MASK_PKT_NUM_WOL_8822B 0xff #define BIT_PKT_NUM_WOL_8822B(x) (((x) & BIT_MASK_PKT_NUM_WOL_8822B) << BIT_SHIFT_PKT_NUM_WOL_8822B) #define BIT_GET_PKT_NUM_WOL_8822B(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8822B) & BIT_MASK_PKT_NUM_WOL_8822B) + #define BIT_SHIFT_DMA_AGG_TO_8822B 8 #define BIT_MASK_DMA_AGG_TO_8822B 0xf #define BIT_DMA_AGG_TO_8822B(x) (((x) & BIT_MASK_DMA_AGG_TO_8822B) << BIT_SHIFT_DMA_AGG_TO_8822B) #define BIT_GET_DMA_AGG_TO_8822B(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_8822B) & BIT_MASK_DMA_AGG_TO_8822B) + #define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B 0 #define BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B 0xf #define BIT_RXDMA_AGG_PG_TH_V1_8822B(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B) #define BIT_GET_RXDMA_AGG_PG_TH_V1_8822B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B) + /* 2 REG_RXPKT_NUM_8822B */ #define BIT_SHIFT_RXPKT_NUM_8822B 24 @@ -3450,11 +3766,13 @@ #define BIT_GET_RXPKT_NUM_8822B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8822B) & BIT_MASK_RXPKT_NUM_8822B) + #define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B 20 #define BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B 0xf #define BIT_FW_UPD_RDPTR19_TO_16_8822B(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) #define BIT_GET_FW_UPD_RDPTR19_TO_16_8822B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) + #define BIT_RXDMA_REQ_8822B BIT(19) #define BIT_RW_RELEASE_EN_8822B BIT(18) #define BIT_RXDMA_IDLE_8822B BIT(17) @@ -3466,6 +3784,7 @@ #define BIT_GET_FW_UPD_RDPTR_8822B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822B) & BIT_MASK_FW_UPD_RDPTR_8822B) + /* 2 REG_RXDMA_STATUS_8822B */ #define BIT_C2H_PKT_OVF_8822B BIT(7) #define BIT_AGG_CONFGI_ISSUE_8822B BIT(6) @@ -3483,6 +3802,7 @@ #define BIT_GET_RDE_DEBUG_8822B(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8822B) & BIT_MASK_RDE_DEBUG_8822B) + /* 2 REG_RXDMA_MODE_8822B */ #define BIT_SHIFT_PKTNUM_TH_V2_8822B 24 @@ -3490,6 +3810,7 @@ #define BIT_PKTNUM_TH_V2_8822B(x) (((x) & BIT_MASK_PKTNUM_TH_V2_8822B) << BIT_SHIFT_PKTNUM_TH_V2_8822B) #define BIT_GET_PKTNUM_TH_V2_8822B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822B) & BIT_MASK_PKTNUM_TH_V2_8822B) + #define BIT_TXBA_BREAK_USBAGG_8822B BIT(23) #define BIT_SHIFT_PKTLEN_PARA_8822B 16 @@ -3498,6 +3819,7 @@ #define BIT_GET_PKTLEN_PARA_8822B(x) (((x) >> BIT_SHIFT_PKTLEN_PARA_8822B) & BIT_MASK_PKTLEN_PARA_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_NOT_VALID_8822B */ @@ -3510,11 +3832,13 @@ #define BIT_GET_BURST_SIZE_8822B(x) (((x) >> BIT_SHIFT_BURST_SIZE_8822B) & BIT_MASK_BURST_SIZE_8822B) + #define BIT_SHIFT_BURST_CNT_8822B 2 #define BIT_MASK_BURST_CNT_8822B 0x3 #define BIT_BURST_CNT_8822B(x) (((x) & BIT_MASK_BURST_CNT_8822B) << BIT_SHIFT_BURST_CNT_8822B) #define BIT_GET_BURST_CNT_8822B(x) (((x) >> BIT_SHIFT_BURST_CNT_8822B) & BIT_MASK_BURST_CNT_8822B) + #define BIT_DMA_MODE_8822B BIT(1) /* 2 REG_C2H_PKT_8822B */ @@ -3524,6 +3848,7 @@ #define BIT_R_C2H_STR_ADDR_16_TO_19_8822B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) #define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) + #define BIT_R_C2H_PKT_REQ_8822B BIT(16) #define BIT_SHIFT_R_C2H_STR_ADDR_8822B 0 @@ -3532,6 +3857,7 @@ #define BIT_GET_R_C2H_STR_ADDR_8822B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822B) & BIT_MASK_R_C2H_STR_ADDR_8822B) + /* 2 REG_FWFF_C2H_8822B */ #define BIT_SHIFT_C2H_DMA_ADDR_8822B 0 @@ -3540,6 +3866,7 @@ #define BIT_GET_C2H_DMA_ADDR_8822B(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822B) & BIT_MASK_C2H_DMA_ADDR_8822B) + /* 2 REG_FWFF_CTRL_8822B */ #define BIT_FWFF_DMAPKT_REQ_8822B BIT(31) @@ -3549,12 +3876,14 @@ #define BIT_GET_FWFF_DMA_PKT_NUM_8822B(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B) + #define BIT_SHIFT_FWFF_STR_ADDR_8822B 0 #define BIT_MASK_FWFF_STR_ADDR_8822B 0xffff #define BIT_FWFF_STR_ADDR_8822B(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8822B) << BIT_SHIFT_FWFF_STR_ADDR_8822B) #define BIT_GET_FWFF_STR_ADDR_8822B(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822B) & BIT_MASK_FWFF_STR_ADDR_8822B) + /* 2 REG_FWFF_PKT_INFO_8822B */ #define BIT_SHIFT_FWFF_PKT_QUEUED_8822B 16 @@ -3563,12 +3892,14 @@ #define BIT_GET_FWFF_PKT_QUEUED_8822B(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822B) & BIT_MASK_FWFF_PKT_QUEUED_8822B) + #define BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B 0 #define BIT_MASK_FWFF_PKT_STR_ADDR_8822B 0xffff #define BIT_FWFF_PKT_STR_ADDR_8822B(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) #define BIT_GET_FWFF_PKT_STR_ADDR_8822B(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_DDMA_CH0SA_8822B */ @@ -3579,6 +3910,7 @@ #define BIT_GET_DDMACH0_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8822B) & BIT_MASK_DDMACH0_SA_8822B) + /* 2 REG_DDMA_CH0DA_8822B */ #define BIT_SHIFT_DDMACH0_DA_8822B 0 @@ -3587,6 +3919,7 @@ #define BIT_GET_DDMACH0_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8822B) & BIT_MASK_DDMACH0_DA_8822B) + /* 2 REG_DDMA_CH0CTRL_8822B */ #define BIT_DDMACH0_OWN_8822B BIT(31) #define BIT_DDMACH0_CHKSUM_EN_8822B BIT(29) @@ -3602,6 +3935,7 @@ #define BIT_GET_DDMACH0_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8822B) & BIT_MASK_DDMACH0_DLEN_8822B) + /* 2 REG_DDMA_CH1SA_8822B */ #define BIT_SHIFT_DDMACH1_SA_8822B 0 @@ -3610,6 +3944,7 @@ #define BIT_GET_DDMACH1_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8822B) & BIT_MASK_DDMACH1_SA_8822B) + /* 2 REG_DDMA_CH1DA_8822B */ #define BIT_SHIFT_DDMACH1_DA_8822B 0 @@ -3618,6 +3953,7 @@ #define BIT_GET_DDMACH1_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8822B) & BIT_MASK_DDMACH1_DA_8822B) + /* 2 REG_DDMA_CH1CTRL_8822B */ #define BIT_DDMACH1_OWN_8822B BIT(31) #define BIT_DDMACH1_CHKSUM_EN_8822B BIT(29) @@ -3633,6 +3969,7 @@ #define BIT_GET_DDMACH1_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8822B) & BIT_MASK_DDMACH1_DLEN_8822B) + /* 2 REG_DDMA_CH2SA_8822B */ #define BIT_SHIFT_DDMACH2_SA_8822B 0 @@ -3641,6 +3978,7 @@ #define BIT_GET_DDMACH2_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8822B) & BIT_MASK_DDMACH2_SA_8822B) + /* 2 REG_DDMA_CH2DA_8822B */ #define BIT_SHIFT_DDMACH2_DA_8822B 0 @@ -3649,6 +3987,7 @@ #define BIT_GET_DDMACH2_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8822B) & BIT_MASK_DDMACH2_DA_8822B) + /* 2 REG_DDMA_CH2CTRL_8822B */ #define BIT_DDMACH2_OWN_8822B BIT(31) #define BIT_DDMACH2_CHKSUM_EN_8822B BIT(29) @@ -3664,6 +4003,7 @@ #define BIT_GET_DDMACH2_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8822B) & BIT_MASK_DDMACH2_DLEN_8822B) + /* 2 REG_DDMA_CH3SA_8822B */ #define BIT_SHIFT_DDMACH3_SA_8822B 0 @@ -3672,6 +4012,7 @@ #define BIT_GET_DDMACH3_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8822B) & BIT_MASK_DDMACH3_SA_8822B) + /* 2 REG_DDMA_CH3DA_8822B */ #define BIT_SHIFT_DDMACH3_DA_8822B 0 @@ -3680,6 +4021,7 @@ #define BIT_GET_DDMACH3_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8822B) & BIT_MASK_DDMACH3_DA_8822B) + /* 2 REG_DDMA_CH3CTRL_8822B */ #define BIT_DDMACH3_OWN_8822B BIT(31) #define BIT_DDMACH3_CHKSUM_EN_8822B BIT(29) @@ -3695,6 +4037,7 @@ #define BIT_GET_DDMACH3_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8822B) & BIT_MASK_DDMACH3_DLEN_8822B) + /* 2 REG_DDMA_CH4SA_8822B */ #define BIT_SHIFT_DDMACH4_SA_8822B 0 @@ -3703,6 +4046,7 @@ #define BIT_GET_DDMACH4_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8822B) & BIT_MASK_DDMACH4_SA_8822B) + /* 2 REG_DDMA_CH4DA_8822B */ #define BIT_SHIFT_DDMACH4_DA_8822B 0 @@ -3711,6 +4055,7 @@ #define BIT_GET_DDMACH4_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8822B) & BIT_MASK_DDMACH4_DA_8822B) + /* 2 REG_DDMA_CH4CTRL_8822B */ #define BIT_DDMACH4_OWN_8822B BIT(31) #define BIT_DDMACH4_CHKSUM_EN_8822B BIT(29) @@ -3726,6 +4071,7 @@ #define BIT_GET_DDMACH4_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8822B) & BIT_MASK_DDMACH4_DLEN_8822B) + /* 2 REG_DDMA_CH5SA_8822B */ #define BIT_SHIFT_DDMACH5_SA_8822B 0 @@ -3734,6 +4080,7 @@ #define BIT_GET_DDMACH5_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8822B) & BIT_MASK_DDMACH5_SA_8822B) + /* 2 REG_DDMA_CH5DA_8822B */ #define BIT_SHIFT_DDMACH5_DA_8822B 0 @@ -3742,6 +4089,7 @@ #define BIT_GET_DDMACH5_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8822B) & BIT_MASK_DDMACH5_DA_8822B) + /* 2 REG_REG_DDMA_CH5CTRL_8822B */ #define BIT_DDMACH5_OWN_8822B BIT(31) #define BIT_DDMACH5_CHKSUM_EN_8822B BIT(29) @@ -3757,6 +4105,7 @@ #define BIT_GET_DDMACH5_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8822B) & BIT_MASK_DDMACH5_DLEN_8822B) + /* 2 REG_DDMA_INT_MSK_8822B */ #define BIT_DDMACH5_MSK_8822B BIT(5) #define BIT_DDMACH4_MSK_8822B BIT(4) @@ -3781,6 +4130,7 @@ #define BIT_GET_IDDMA0_CHKSUM_8822B(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822B) & BIT_MASK_IDDMA0_CHKSUM_8822B) + /* 2 REG_DDMA_MONITOR_8822B */ #define BIT_IDDMA0_PERMU_UNDERFLOW_8822B BIT(14) #define BIT_IDDMA0_FIFO_UNDERFLOW_8822B BIT(13) @@ -3802,6 +4152,7 @@ #define BIT_PCIE_MAX_RXDMA_8822B(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA_8822B) << BIT_SHIFT_PCIE_MAX_RXDMA_8822B) #define BIT_GET_PCIE_MAX_RXDMA_8822B(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822B) & BIT_MASK_PCIE_MAX_RXDMA_8822B) + #define BIT_MULRW_8822B BIT(27) #define BIT_SHIFT_PCIE_MAX_TXDMA_8822B 24 @@ -3809,6 +4160,7 @@ #define BIT_PCIE_MAX_TXDMA_8822B(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA_8822B) << BIT_SHIFT_PCIE_MAX_TXDMA_8822B) #define BIT_GET_PCIE_MAX_TXDMA_8822B(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822B) & BIT_MASK_PCIE_MAX_TXDMA_8822B) + #define BIT_EN_CPL_TIMEOUT_PS_8822B BIT(22) #define BIT_REG_TXDMA_FAIL_PS_8822B BIT(21) #define BIT_PCIE_RST_TRXDMA_INTF_8822B BIT(20) @@ -3841,30 +4193,35 @@ #define BIT_GET_TXTTIMER_MATCH_NUM_8822B(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B) + #define BIT_SHIFT_TXPKT_NUM_MATCH_8822B 24 #define BIT_MASK_TXPKT_NUM_MATCH_8822B 0xf #define BIT_TXPKT_NUM_MATCH_8822B(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8822B) << BIT_SHIFT_TXPKT_NUM_MATCH_8822B) #define BIT_GET_TXPKT_NUM_MATCH_8822B(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8822B) & BIT_MASK_TXPKT_NUM_MATCH_8822B) + #define BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B 20 #define BIT_MASK_RXTTIMER_MATCH_NUM_8822B 0xf #define BIT_RXTTIMER_MATCH_NUM_8822B(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) #define BIT_GET_RXTTIMER_MATCH_NUM_8822B(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B) + #define BIT_SHIFT_RXPKT_NUM_MATCH_8822B 16 #define BIT_MASK_RXPKT_NUM_MATCH_8822B 0xf #define BIT_RXPKT_NUM_MATCH_8822B(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8822B) << BIT_SHIFT_RXPKT_NUM_MATCH_8822B) #define BIT_GET_RXPKT_NUM_MATCH_8822B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8822B) & BIT_MASK_RXPKT_NUM_MATCH_8822B) + #define BIT_SHIFT_MIGRATE_TIMER_8822B 0 #define BIT_MASK_MIGRATE_TIMER_8822B 0xffff #define BIT_MIGRATE_TIMER_8822B(x) (((x) & BIT_MASK_MIGRATE_TIMER_8822B) << BIT_SHIFT_MIGRATE_TIMER_8822B) #define BIT_GET_MIGRATE_TIMER_8822B(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8822B) & BIT_MASK_MIGRATE_TIMER_8822B) + /* 2 REG_BCNQ_TXBD_DESA_8822B */ #define BIT_SHIFT_BCNQ_TXBD_DESA_8822B 0 @@ -3873,6 +4230,7 @@ #define BIT_GET_BCNQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822B) & BIT_MASK_BCNQ_TXBD_DESA_8822B) + /* 2 REG_MGQ_TXBD_DESA_8822B */ #define BIT_SHIFT_MGQ_TXBD_DESA_8822B 0 @@ -3881,6 +4239,7 @@ #define BIT_GET_MGQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822B) & BIT_MASK_MGQ_TXBD_DESA_8822B) + /* 2 REG_VOQ_TXBD_DESA_8822B */ #define BIT_SHIFT_VOQ_TXBD_DESA_8822B 0 @@ -3889,6 +4248,7 @@ #define BIT_GET_VOQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822B) & BIT_MASK_VOQ_TXBD_DESA_8822B) + /* 2 REG_VIQ_TXBD_DESA_8822B */ #define BIT_SHIFT_VIQ_TXBD_DESA_8822B 0 @@ -3897,6 +4257,7 @@ #define BIT_GET_VIQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822B) & BIT_MASK_VIQ_TXBD_DESA_8822B) + /* 2 REG_BEQ_TXBD_DESA_8822B */ #define BIT_SHIFT_BEQ_TXBD_DESA_8822B 0 @@ -3905,6 +4266,7 @@ #define BIT_GET_BEQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822B) & BIT_MASK_BEQ_TXBD_DESA_8822B) + /* 2 REG_BKQ_TXBD_DESA_8822B */ #define BIT_SHIFT_BKQ_TXBD_DESA_8822B 0 @@ -3913,6 +4275,7 @@ #define BIT_GET_BKQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822B) & BIT_MASK_BKQ_TXBD_DESA_8822B) + /* 2 REG_RXQ_RXBD_DESA_8822B */ #define BIT_SHIFT_RXQ_RXBD_DESA_8822B 0 @@ -3921,6 +4284,7 @@ #define BIT_GET_RXQ_RXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822B) & BIT_MASK_RXQ_RXBD_DESA_8822B) + /* 2 REG_HI0Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI0Q_TXBD_DESA_8822B 0 @@ -3929,6 +4293,7 @@ #define BIT_GET_HI0Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822B) & BIT_MASK_HI0Q_TXBD_DESA_8822B) + /* 2 REG_HI1Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI1Q_TXBD_DESA_8822B 0 @@ -3937,6 +4302,7 @@ #define BIT_GET_HI1Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822B) & BIT_MASK_HI1Q_TXBD_DESA_8822B) + /* 2 REG_HI2Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI2Q_TXBD_DESA_8822B 0 @@ -3945,6 +4311,7 @@ #define BIT_GET_HI2Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822B) & BIT_MASK_HI2Q_TXBD_DESA_8822B) + /* 2 REG_HI3Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI3Q_TXBD_DESA_8822B 0 @@ -3953,6 +4320,7 @@ #define BIT_GET_HI3Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822B) & BIT_MASK_HI3Q_TXBD_DESA_8822B) + /* 2 REG_HI4Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI4Q_TXBD_DESA_8822B 0 @@ -3961,6 +4329,7 @@ #define BIT_GET_HI4Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822B) & BIT_MASK_HI4Q_TXBD_DESA_8822B) + /* 2 REG_HI5Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI5Q_TXBD_DESA_8822B 0 @@ -3969,6 +4338,7 @@ #define BIT_GET_HI5Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822B) & BIT_MASK_HI5Q_TXBD_DESA_8822B) + /* 2 REG_HI6Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI6Q_TXBD_DESA_8822B 0 @@ -3977,6 +4347,7 @@ #define BIT_GET_HI6Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822B) & BIT_MASK_HI6Q_TXBD_DESA_8822B) + /* 2 REG_HI7Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI7Q_TXBD_DESA_8822B 0 @@ -3985,6 +4356,7 @@ #define BIT_GET_HI7Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822B) & BIT_MASK_HI7Q_TXBD_DESA_8822B) + /* 2 REG_MGQ_TXBD_NUM_8822B */ #define BIT_PCIE_MGQ_FLAG_8822B BIT(14) @@ -3994,12 +4366,14 @@ #define BIT_GET_MGQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822B) & BIT_MASK_MGQ_DESC_MODE_8822B) + #define BIT_SHIFT_MGQ_DESC_NUM_8822B 0 #define BIT_MASK_MGQ_DESC_NUM_8822B 0xfff #define BIT_MGQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8822B) << BIT_SHIFT_MGQ_DESC_NUM_8822B) #define BIT_GET_MGQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822B) & BIT_MASK_MGQ_DESC_NUM_8822B) + /* 2 REG_RX_RXBD_NUM_8822B */ #define BIT_SYS_32_64_8822B BIT(15) @@ -4008,6 +4382,7 @@ #define BIT_BCNQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8822B) << BIT_SHIFT_BCNQ_DESC_MODE_8822B) #define BIT_GET_BCNQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822B) & BIT_MASK_BCNQ_DESC_MODE_8822B) + #define BIT_PCIE_BCNQ_FLAG_8822B BIT(12) #define BIT_SHIFT_RXQ_DESC_NUM_8822B 0 @@ -4016,6 +4391,7 @@ #define BIT_GET_RXQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822B) & BIT_MASK_RXQ_DESC_NUM_8822B) + /* 2 REG_VOQ_TXBD_NUM_8822B */ #define BIT_PCIE_VOQ_FLAG_8822B BIT(14) @@ -4025,12 +4401,14 @@ #define BIT_GET_VOQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822B) & BIT_MASK_VOQ_DESC_MODE_8822B) + #define BIT_SHIFT_VOQ_DESC_NUM_8822B 0 #define BIT_MASK_VOQ_DESC_NUM_8822B 0xfff #define BIT_VOQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8822B) << BIT_SHIFT_VOQ_DESC_NUM_8822B) #define BIT_GET_VOQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822B) & BIT_MASK_VOQ_DESC_NUM_8822B) + /* 2 REG_VIQ_TXBD_NUM_8822B */ #define BIT_PCIE_VIQ_FLAG_8822B BIT(14) @@ -4040,12 +4418,14 @@ #define BIT_GET_VIQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822B) & BIT_MASK_VIQ_DESC_MODE_8822B) + #define BIT_SHIFT_VIQ_DESC_NUM_8822B 0 #define BIT_MASK_VIQ_DESC_NUM_8822B 0xfff #define BIT_VIQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8822B) << BIT_SHIFT_VIQ_DESC_NUM_8822B) #define BIT_GET_VIQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822B) & BIT_MASK_VIQ_DESC_NUM_8822B) + /* 2 REG_BEQ_TXBD_NUM_8822B */ #define BIT_PCIE_BEQ_FLAG_8822B BIT(14) @@ -4055,12 +4435,14 @@ #define BIT_GET_BEQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822B) & BIT_MASK_BEQ_DESC_MODE_8822B) + #define BIT_SHIFT_BEQ_DESC_NUM_8822B 0 #define BIT_MASK_BEQ_DESC_NUM_8822B 0xfff #define BIT_BEQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8822B) << BIT_SHIFT_BEQ_DESC_NUM_8822B) #define BIT_GET_BEQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822B) & BIT_MASK_BEQ_DESC_NUM_8822B) + /* 2 REG_BKQ_TXBD_NUM_8822B */ #define BIT_PCIE_BKQ_FLAG_8822B BIT(14) @@ -4070,12 +4452,14 @@ #define BIT_GET_BKQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822B) & BIT_MASK_BKQ_DESC_MODE_8822B) + #define BIT_SHIFT_BKQ_DESC_NUM_8822B 0 #define BIT_MASK_BKQ_DESC_NUM_8822B 0xfff #define BIT_BKQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8822B) << BIT_SHIFT_BKQ_DESC_NUM_8822B) #define BIT_GET_BKQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822B) & BIT_MASK_BKQ_DESC_NUM_8822B) + /* 2 REG_HI0Q_TXBD_NUM_8822B */ #define BIT_HI0Q_FLAG_8822B BIT(14) @@ -4085,12 +4469,14 @@ #define BIT_GET_HI0Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822B) & BIT_MASK_HI0Q_DESC_MODE_8822B) + #define BIT_SHIFT_HI0Q_DESC_NUM_8822B 0 #define BIT_MASK_HI0Q_DESC_NUM_8822B 0xfff #define BIT_HI0Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8822B) << BIT_SHIFT_HI0Q_DESC_NUM_8822B) #define BIT_GET_HI0Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822B) & BIT_MASK_HI0Q_DESC_NUM_8822B) + /* 2 REG_HI1Q_TXBD_NUM_8822B */ #define BIT_HI1Q_FLAG_8822B BIT(14) @@ -4100,12 +4486,14 @@ #define BIT_GET_HI1Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822B) & BIT_MASK_HI1Q_DESC_MODE_8822B) + #define BIT_SHIFT_HI1Q_DESC_NUM_8822B 0 #define BIT_MASK_HI1Q_DESC_NUM_8822B 0xfff #define BIT_HI1Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8822B) << BIT_SHIFT_HI1Q_DESC_NUM_8822B) #define BIT_GET_HI1Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822B) & BIT_MASK_HI1Q_DESC_NUM_8822B) + /* 2 REG_HI2Q_TXBD_NUM_8822B */ #define BIT_HI2Q_FLAG_8822B BIT(14) @@ -4115,12 +4503,14 @@ #define BIT_GET_HI2Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822B) & BIT_MASK_HI2Q_DESC_MODE_8822B) + #define BIT_SHIFT_HI2Q_DESC_NUM_8822B 0 #define BIT_MASK_HI2Q_DESC_NUM_8822B 0xfff #define BIT_HI2Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8822B) << BIT_SHIFT_HI2Q_DESC_NUM_8822B) #define BIT_GET_HI2Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822B) & BIT_MASK_HI2Q_DESC_NUM_8822B) + /* 2 REG_HI3Q_TXBD_NUM_8822B */ #define BIT_HI3Q_FLAG_8822B BIT(14) @@ -4130,12 +4520,14 @@ #define BIT_GET_HI3Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822B) & BIT_MASK_HI3Q_DESC_MODE_8822B) + #define BIT_SHIFT_HI3Q_DESC_NUM_8822B 0 #define BIT_MASK_HI3Q_DESC_NUM_8822B 0xfff #define BIT_HI3Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8822B) << BIT_SHIFT_HI3Q_DESC_NUM_8822B) #define BIT_GET_HI3Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822B) & BIT_MASK_HI3Q_DESC_NUM_8822B) + /* 2 REG_HI4Q_TXBD_NUM_8822B */ #define BIT_HI4Q_FLAG_8822B BIT(14) @@ -4145,12 +4537,14 @@ #define BIT_GET_HI4Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822B) & BIT_MASK_HI4Q_DESC_MODE_8822B) + #define BIT_SHIFT_HI4Q_DESC_NUM_8822B 0 #define BIT_MASK_HI4Q_DESC_NUM_8822B 0xfff #define BIT_HI4Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8822B) << BIT_SHIFT_HI4Q_DESC_NUM_8822B) #define BIT_GET_HI4Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822B) & BIT_MASK_HI4Q_DESC_NUM_8822B) + /* 2 REG_HI5Q_TXBD_NUM_8822B */ #define BIT_HI5Q_FLAG_8822B BIT(14) @@ -4160,12 +4554,14 @@ #define BIT_GET_HI5Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822B) & BIT_MASK_HI5Q_DESC_MODE_8822B) + #define BIT_SHIFT_HI5Q_DESC_NUM_8822B 0 #define BIT_MASK_HI5Q_DESC_NUM_8822B 0xfff #define BIT_HI5Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8822B) << BIT_SHIFT_HI5Q_DESC_NUM_8822B) #define BIT_GET_HI5Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822B) & BIT_MASK_HI5Q_DESC_NUM_8822B) + /* 2 REG_HI6Q_TXBD_NUM_8822B */ #define BIT_HI6Q_FLAG_8822B BIT(14) @@ -4175,12 +4571,14 @@ #define BIT_GET_HI6Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822B) & BIT_MASK_HI6Q_DESC_MODE_8822B) + #define BIT_SHIFT_HI6Q_DESC_NUM_8822B 0 #define BIT_MASK_HI6Q_DESC_NUM_8822B 0xfff #define BIT_HI6Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8822B) << BIT_SHIFT_HI6Q_DESC_NUM_8822B) #define BIT_GET_HI6Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822B) & BIT_MASK_HI6Q_DESC_NUM_8822B) + /* 2 REG_HI7Q_TXBD_NUM_8822B */ #define BIT_HI7Q_FLAG_8822B BIT(14) @@ -4190,12 +4588,14 @@ #define BIT_GET_HI7Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822B) & BIT_MASK_HI7Q_DESC_MODE_8822B) + #define BIT_SHIFT_HI7Q_DESC_NUM_8822B 0 #define BIT_MASK_HI7Q_DESC_NUM_8822B 0xfff #define BIT_HI7Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8822B) << BIT_SHIFT_HI7Q_DESC_NUM_8822B) #define BIT_GET_HI7Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822B) & BIT_MASK_HI7Q_DESC_NUM_8822B) + /* 2 REG_TSFTIMER_HCI_8822B */ #define BIT_SHIFT_TSFT2_HCI_8822B 16 @@ -4204,12 +4604,14 @@ #define BIT_GET_TSFT2_HCI_8822B(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8822B) & BIT_MASK_TSFT2_HCI_8822B) + #define BIT_SHIFT_TSFT1_HCI_8822B 0 #define BIT_MASK_TSFT1_HCI_8822B 0xffff #define BIT_TSFT1_HCI_8822B(x) (((x) & BIT_MASK_TSFT1_HCI_8822B) << BIT_SHIFT_TSFT1_HCI_8822B) #define BIT_GET_TSFT1_HCI_8822B(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8822B) & BIT_MASK_TSFT1_HCI_8822B) + /* 2 REG_BD_RWPTR_CLR_8822B */ #define BIT_CLR_HI7Q_HW_IDX_8822B BIT(29) #define BIT_CLR_HI6Q_HW_IDX_8822B BIT(28) @@ -4248,12 +4650,14 @@ #define BIT_GET_VOQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8822B) & BIT_MASK_VOQ_HW_IDX_8822B) + #define BIT_SHIFT_VOQ_HOST_IDX_8822B 0 #define BIT_MASK_VOQ_HOST_IDX_8822B 0xfff #define BIT_VOQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8822B) << BIT_SHIFT_VOQ_HOST_IDX_8822B) #define BIT_GET_VOQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822B) & BIT_MASK_VOQ_HOST_IDX_8822B) + /* 2 REG_VIQ_TXBD_IDX_8822B */ #define BIT_SHIFT_VIQ_HW_IDX_8822B 16 @@ -4262,12 +4666,14 @@ #define BIT_GET_VIQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8822B) & BIT_MASK_VIQ_HW_IDX_8822B) + #define BIT_SHIFT_VIQ_HOST_IDX_8822B 0 #define BIT_MASK_VIQ_HOST_IDX_8822B 0xfff #define BIT_VIQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8822B) << BIT_SHIFT_VIQ_HOST_IDX_8822B) #define BIT_GET_VIQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822B) & BIT_MASK_VIQ_HOST_IDX_8822B) + /* 2 REG_BEQ_TXBD_IDX_8822B */ #define BIT_SHIFT_BEQ_HW_IDX_8822B 16 @@ -4276,12 +4682,14 @@ #define BIT_GET_BEQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8822B) & BIT_MASK_BEQ_HW_IDX_8822B) + #define BIT_SHIFT_BEQ_HOST_IDX_8822B 0 #define BIT_MASK_BEQ_HOST_IDX_8822B 0xfff #define BIT_BEQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8822B) << BIT_SHIFT_BEQ_HOST_IDX_8822B) #define BIT_GET_BEQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822B) & BIT_MASK_BEQ_HOST_IDX_8822B) + /* 2 REG_BKQ_TXBD_IDX_8822B */ #define BIT_SHIFT_BKQ_HW_IDX_8822B 16 @@ -4290,12 +4698,14 @@ #define BIT_GET_BKQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8822B) & BIT_MASK_BKQ_HW_IDX_8822B) + #define BIT_SHIFT_BKQ_HOST_IDX_8822B 0 #define BIT_MASK_BKQ_HOST_IDX_8822B 0xfff #define BIT_BKQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8822B) << BIT_SHIFT_BKQ_HOST_IDX_8822B) #define BIT_GET_BKQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822B) & BIT_MASK_BKQ_HOST_IDX_8822B) + /* 2 REG_MGQ_TXBD_IDX_8822B */ #define BIT_SHIFT_MGQ_HW_IDX_8822B 16 @@ -4304,12 +4714,14 @@ #define BIT_GET_MGQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8822B) & BIT_MASK_MGQ_HW_IDX_8822B) + #define BIT_SHIFT_MGQ_HOST_IDX_8822B 0 #define BIT_MASK_MGQ_HOST_IDX_8822B 0xfff #define BIT_MGQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8822B) << BIT_SHIFT_MGQ_HOST_IDX_8822B) #define BIT_GET_MGQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822B) & BIT_MASK_MGQ_HOST_IDX_8822B) + /* 2 REG_RXQ_RXBD_IDX_8822B */ #define BIT_SHIFT_RXQ_HW_IDX_8822B 16 @@ -4318,12 +4730,14 @@ #define BIT_GET_RXQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8822B) & BIT_MASK_RXQ_HW_IDX_8822B) + #define BIT_SHIFT_RXQ_HOST_IDX_8822B 0 #define BIT_MASK_RXQ_HOST_IDX_8822B 0xfff #define BIT_RXQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8822B) << BIT_SHIFT_RXQ_HOST_IDX_8822B) #define BIT_GET_RXQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822B) & BIT_MASK_RXQ_HOST_IDX_8822B) + /* 2 REG_HI0Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI0Q_HW_IDX_8822B 16 @@ -4332,12 +4746,14 @@ #define BIT_GET_HI0Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822B) & BIT_MASK_HI0Q_HW_IDX_8822B) + #define BIT_SHIFT_HI0Q_HOST_IDX_8822B 0 #define BIT_MASK_HI0Q_HOST_IDX_8822B 0xfff #define BIT_HI0Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8822B) << BIT_SHIFT_HI0Q_HOST_IDX_8822B) #define BIT_GET_HI0Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822B) & BIT_MASK_HI0Q_HOST_IDX_8822B) + /* 2 REG_HI1Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI1Q_HW_IDX_8822B 16 @@ -4346,12 +4762,14 @@ #define BIT_GET_HI1Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822B) & BIT_MASK_HI1Q_HW_IDX_8822B) + #define BIT_SHIFT_HI1Q_HOST_IDX_8822B 0 #define BIT_MASK_HI1Q_HOST_IDX_8822B 0xfff #define BIT_HI1Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8822B) << BIT_SHIFT_HI1Q_HOST_IDX_8822B) #define BIT_GET_HI1Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822B) & BIT_MASK_HI1Q_HOST_IDX_8822B) + /* 2 REG_HI2Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI2Q_HW_IDX_8822B 16 @@ -4360,12 +4778,14 @@ #define BIT_GET_HI2Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822B) & BIT_MASK_HI2Q_HW_IDX_8822B) + #define BIT_SHIFT_HI2Q_HOST_IDX_8822B 0 #define BIT_MASK_HI2Q_HOST_IDX_8822B 0xfff #define BIT_HI2Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8822B) << BIT_SHIFT_HI2Q_HOST_IDX_8822B) #define BIT_GET_HI2Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822B) & BIT_MASK_HI2Q_HOST_IDX_8822B) + /* 2 REG_HI3Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI3Q_HW_IDX_8822B 16 @@ -4374,12 +4794,14 @@ #define BIT_GET_HI3Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822B) & BIT_MASK_HI3Q_HW_IDX_8822B) + #define BIT_SHIFT_HI3Q_HOST_IDX_8822B 0 #define BIT_MASK_HI3Q_HOST_IDX_8822B 0xfff #define BIT_HI3Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8822B) << BIT_SHIFT_HI3Q_HOST_IDX_8822B) #define BIT_GET_HI3Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822B) & BIT_MASK_HI3Q_HOST_IDX_8822B) + /* 2 REG_HI4Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI4Q_HW_IDX_8822B 16 @@ -4388,12 +4810,14 @@ #define BIT_GET_HI4Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822B) & BIT_MASK_HI4Q_HW_IDX_8822B) + #define BIT_SHIFT_HI4Q_HOST_IDX_8822B 0 #define BIT_MASK_HI4Q_HOST_IDX_8822B 0xfff #define BIT_HI4Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8822B) << BIT_SHIFT_HI4Q_HOST_IDX_8822B) #define BIT_GET_HI4Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822B) & BIT_MASK_HI4Q_HOST_IDX_8822B) + /* 2 REG_HI5Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI5Q_HW_IDX_8822B 16 @@ -4402,12 +4826,14 @@ #define BIT_GET_HI5Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822B) & BIT_MASK_HI5Q_HW_IDX_8822B) + #define BIT_SHIFT_HI5Q_HOST_IDX_8822B 0 #define BIT_MASK_HI5Q_HOST_IDX_8822B 0xfff #define BIT_HI5Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8822B) << BIT_SHIFT_HI5Q_HOST_IDX_8822B) #define BIT_GET_HI5Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822B) & BIT_MASK_HI5Q_HOST_IDX_8822B) + /* 2 REG_HI6Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI6Q_HW_IDX_8822B 16 @@ -4416,12 +4842,14 @@ #define BIT_GET_HI6Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822B) & BIT_MASK_HI6Q_HW_IDX_8822B) + #define BIT_SHIFT_HI6Q_HOST_IDX_8822B 0 #define BIT_MASK_HI6Q_HOST_IDX_8822B 0xfff #define BIT_HI6Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8822B) << BIT_SHIFT_HI6Q_HOST_IDX_8822B) #define BIT_GET_HI6Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822B) & BIT_MASK_HI6Q_HOST_IDX_8822B) + /* 2 REG_HI7Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI7Q_HW_IDX_8822B 16 @@ -4430,12 +4858,14 @@ #define BIT_GET_HI7Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822B) & BIT_MASK_HI7Q_HW_IDX_8822B) + #define BIT_SHIFT_HI7Q_HOST_IDX_8822B 0 #define BIT_MASK_HI7Q_HOST_IDX_8822B 0xfff #define BIT_HI7Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8822B) << BIT_SHIFT_HI7Q_HOST_IDX_8822B) #define BIT_GET_HI7Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822B) & BIT_MASK_HI7Q_HOST_IDX_8822B) + /* 2 REG_DBG_SEL_V1_8822B */ #define BIT_SHIFT_DBG_SEL_8822B 0 @@ -4444,6 +4874,7 @@ #define BIT_GET_DBG_SEL_8822B(x) (((x) >> BIT_SHIFT_DBG_SEL_8822B) & BIT_MASK_DBG_SEL_8822B) + /* 2 REG_PCIE_HRPWM1_V1_8822B */ #define BIT_SHIFT_PCIE_HRPWM_8822B 0 @@ -4452,6 +4883,7 @@ #define BIT_GET_PCIE_HRPWM_8822B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM_8822B) & BIT_MASK_PCIE_HRPWM_8822B) + /* 2 REG_PCIE_HCPWM1_V1_8822B */ #define BIT_SHIFT_PCIE_HCPWM_8822B 0 @@ -4460,6 +4892,7 @@ #define BIT_GET_PCIE_HCPWM_8822B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM_8822B) & BIT_MASK_PCIE_HCPWM_8822B) + /* 2 REG_PCIE_CTRL2_8822B */ #define BIT_DIS_TXDMA_PRE_8822B BIT(7) #define BIT_DIS_RXDMA_PRE_8822B BIT(6) @@ -4469,6 +4902,7 @@ #define BIT_HPS_CLKR_PCIE_8822B(x) (((x) & BIT_MASK_HPS_CLKR_PCIE_8822B) << BIT_SHIFT_HPS_CLKR_PCIE_8822B) #define BIT_GET_HPS_CLKR_PCIE_8822B(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822B) & BIT_MASK_HPS_CLKR_PCIE_8822B) + #define BIT_PCIE_INT_8822B BIT(3) #define BIT_TXFLAG_EXIT_L1_EN_8822B BIT(2) #define BIT_EN_RXDMA_ALIGN_8822B BIT(1) @@ -4482,6 +4916,7 @@ #define BIT_GET_PCIE_HRPWM2_8822B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2_8822B) & BIT_MASK_PCIE_HRPWM2_8822B) + /* 2 REG_PCIE_HCPWM2_V1_8822B */ #define BIT_SHIFT_PCIE_HCPWM2_8822B 0 @@ -4490,6 +4925,7 @@ #define BIT_GET_PCIE_HCPWM2_8822B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2_8822B) & BIT_MASK_PCIE_HCPWM2_8822B) + /* 2 REG_PCIE_H2C_MSG_V1_8822B */ #define BIT_SHIFT_DRV2FW_INFO_8822B 0 @@ -4498,6 +4934,7 @@ #define BIT_GET_DRV2FW_INFO_8822B(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8822B) & BIT_MASK_DRV2FW_INFO_8822B) + /* 2 REG_PCIE_C2H_MSG_V1_8822B */ #define BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B 0 @@ -4506,6 +4943,7 @@ #define BIT_GET_HCI_PCIE_C2H_MSG_8822B(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B) + /* 2 REG_DBI_WDATA_V1_8822B */ #define BIT_SHIFT_DBI_WDATA_8822B 0 @@ -4514,6 +4952,7 @@ #define BIT_GET_DBI_WDATA_8822B(x) (((x) >> BIT_SHIFT_DBI_WDATA_8822B) & BIT_MASK_DBI_WDATA_8822B) + /* 2 REG_DBI_RDATA_V1_8822B */ #define BIT_SHIFT_DBI_RDATA_8822B 0 @@ -4522,6 +4961,7 @@ #define BIT_GET_DBI_RDATA_8822B(x) (((x) >> BIT_SHIFT_DBI_RDATA_8822B) & BIT_MASK_DBI_RDATA_8822B) + /* 2 REG_DBI_FLAG_V1_8822B */ #define BIT_EN_STUCK_DBG_8822B BIT(26) #define BIT_RX_STUCK_8822B BIT(25) @@ -4535,12 +4975,14 @@ #define BIT_GET_DBI_WREN_8822B(x) (((x) >> BIT_SHIFT_DBI_WREN_8822B) & BIT_MASK_DBI_WREN_8822B) + #define BIT_SHIFT_DBI_ADDR_8822B 0 #define BIT_MASK_DBI_ADDR_8822B 0xfff #define BIT_DBI_ADDR_8822B(x) (((x) & BIT_MASK_DBI_ADDR_8822B) << BIT_SHIFT_DBI_ADDR_8822B) #define BIT_GET_DBI_ADDR_8822B(x) (((x) >> BIT_SHIFT_DBI_ADDR_8822B) & BIT_MASK_DBI_ADDR_8822B) + /* 2 REG_MDIO_V1_8822B */ #define BIT_SHIFT_MDIO_RDATA_8822B 16 @@ -4549,12 +4991,14 @@ #define BIT_GET_MDIO_RDATA_8822B(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8822B) & BIT_MASK_MDIO_RDATA_8822B) + #define BIT_SHIFT_MDIO_WDATA_8822B 0 #define BIT_MASK_MDIO_WDATA_8822B 0xffff #define BIT_MDIO_WDATA_8822B(x) (((x) & BIT_MASK_MDIO_WDATA_8822B) << BIT_SHIFT_MDIO_WDATA_8822B) #define BIT_GET_MDIO_WDATA_8822B(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8822B) & BIT_MASK_MDIO_WDATA_8822B) + /* 2 REG_PCIE_MIX_CFG_8822B */ #define BIT_SHIFT_MDIO_PHY_ADDR_8822B 24 @@ -4563,11 +5007,13 @@ #define BIT_GET_MDIO_PHY_ADDR_8822B(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822B) & BIT_MASK_MDIO_PHY_ADDR_8822B) + #define BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B 10 #define BIT_MASK_WATCH_DOG_RECORD_V1_8822B 0x3fff #define BIT_WATCH_DOG_RECORD_V1_8822B(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) #define BIT_GET_WATCH_DOG_RECORD_V1_8822B(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B) + #define BIT_R_IO_TIMEOUT_FLAG_V1_8822B BIT(9) #define BIT_EN_WATCH_DOG_8822B BIT(8) #define BIT_ECRC_EN_V1_8822B BIT(7) @@ -4580,6 +5026,7 @@ #define BIT_GET_MDIO_REG_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) & BIT_MASK_MDIO_REG_ADDR_V1_8822B) + /* 2 REG_HCI_MIX_CFG_8822B */ #define BIT_HOST_GEN2_SUPPORT_8822B BIT(20) @@ -4589,11 +5036,13 @@ #define BIT_GET_TXDMA_ERR_FLAG_8822B(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8822B) & BIT_MASK_TXDMA_ERR_FLAG_8822B) + #define BIT_SHIFT_EARLY_MODE_SEL_8822B 12 #define BIT_MASK_EARLY_MODE_SEL_8822B 0xf #define BIT_EARLY_MODE_SEL_8822B(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8822B) << BIT_SHIFT_EARLY_MODE_SEL_8822B) #define BIT_GET_EARLY_MODE_SEL_8822B(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8822B) & BIT_MASK_EARLY_MODE_SEL_8822B) + #define BIT_EPHY_RX50_EN_8822B BIT(11) #define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B 8 @@ -4601,6 +5050,7 @@ #define BIT_MSI_TIMEOUT_ID_V1_8822B(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) #define BIT_GET_MSI_TIMEOUT_ID_V1_8822B(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) + #define BIT_RADDR_RD_8822B BIT(7) #define BIT_EN_MUL_TAG_8822B BIT(6) #define BIT_EN_EARLY_MODE_8822B BIT(5) @@ -4618,18 +5068,21 @@ #define BIT_GET_STC_INT_FLAG_8822B(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8822B) & BIT_MASK_STC_INT_FLAG_8822B) + #define BIT_SHIFT_STC_INT_IDX_8822B 8 #define BIT_MASK_STC_INT_IDX_8822B 0x7 #define BIT_STC_INT_IDX_8822B(x) (((x) & BIT_MASK_STC_INT_IDX_8822B) << BIT_SHIFT_STC_INT_IDX_8822B) #define BIT_GET_STC_INT_IDX_8822B(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8822B) & BIT_MASK_STC_INT_IDX_8822B) + #define BIT_SHIFT_STC_INT_REALTIME_CS_8822B 0 #define BIT_MASK_STC_INT_REALTIME_CS_8822B 0x3f #define BIT_STC_INT_REALTIME_CS_8822B(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8822B) << BIT_SHIFT_STC_INT_REALTIME_CS_8822B) #define BIT_GET_STC_INT_REALTIME_CS_8822B(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822B) & BIT_MASK_STC_INT_REALTIME_CS_8822B) + /* 2 REG_ST_INT_CFG_8822B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */ #define BIT_STC_INT_GRP_EN_8822B BIT(31) @@ -4639,12 +5092,14 @@ #define BIT_GET_STC_INT_EXPECT_LS_8822B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822B) & BIT_MASK_STC_INT_EXPECT_LS_8822B) + #define BIT_SHIFT_STC_INT_EXPECT_CS_8822B 0 #define BIT_MASK_STC_INT_EXPECT_CS_8822B 0x3f #define BIT_STC_INT_EXPECT_CS_8822B(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8822B) << BIT_SHIFT_STC_INT_EXPECT_CS_8822B) #define BIT_GET_STC_INT_EXPECT_CS_8822B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822B) & BIT_MASK_STC_INT_EXPECT_CS_8822B) + /* 2 REG_CMU_DLY_CTRL_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */ #define BIT_CMU_DLY_EN_8822B BIT(31) #define BIT_CMU_DLY_MODE_8822B BIT(30) @@ -4655,6 +5110,7 @@ #define BIT_GET_CMU_DLY_PRE_DIV_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) & BIT_MASK_CMU_DLY_PRE_DIV_8822B) + /* 2 REG_CMU_DLY_CFG_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ #define BIT_SHIFT_CMU_DLY_LTR_A2I_8822B 24 @@ -4663,24 +5119,28 @@ #define BIT_GET_CMU_DLY_LTR_A2I_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) & BIT_MASK_CMU_DLY_LTR_A2I_8822B) + #define BIT_SHIFT_CMU_DLY_LTR_I2A_8822B 16 #define BIT_MASK_CMU_DLY_LTR_I2A_8822B 0xff #define BIT_CMU_DLY_LTR_I2A_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8822B) << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) #define BIT_GET_CMU_DLY_LTR_I2A_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) & BIT_MASK_CMU_DLY_LTR_I2A_8822B) + #define BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B 8 #define BIT_MASK_CMU_DLY_LTR_IDLE_8822B 0xff #define BIT_CMU_DLY_LTR_IDLE_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) #define BIT_GET_CMU_DLY_LTR_IDLE_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B) + #define BIT_SHIFT_CMU_DLY_LTR_ACT_8822B 0 #define BIT_MASK_CMU_DLY_LTR_ACT_8822B 0xff #define BIT_CMU_DLY_LTR_ACT_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8822B) << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) #define BIT_GET_CMU_DLY_LTR_ACT_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) & BIT_MASK_CMU_DLY_LTR_ACT_8822B) + /* 2 REG_H2CQ_TXBD_DESA_8822B */ #define BIT_SHIFT_H2CQ_TXBD_DESA_8822B 0 @@ -4689,6 +5149,7 @@ #define BIT_GET_H2CQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822B) & BIT_MASK_H2CQ_TXBD_DESA_8822B) + /* 2 REG_H2CQ_TXBD_NUM_8822B */ #define BIT_PCIE_H2CQ_FLAG_8822B BIT(14) @@ -4698,12 +5159,14 @@ #define BIT_GET_H2CQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822B) & BIT_MASK_H2CQ_DESC_MODE_8822B) + #define BIT_SHIFT_H2CQ_DESC_NUM_8822B 0 #define BIT_MASK_H2CQ_DESC_NUM_8822B 0xfff #define BIT_H2CQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8822B) << BIT_SHIFT_H2CQ_DESC_NUM_8822B) #define BIT_GET_H2CQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822B) & BIT_MASK_H2CQ_DESC_NUM_8822B) + /* 2 REG_H2CQ_TXBD_IDX_8822B */ #define BIT_SHIFT_H2CQ_HW_IDX_8822B 16 @@ -4712,17 +5175,39 @@ #define BIT_GET_H2CQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822B) & BIT_MASK_H2CQ_HW_IDX_8822B) + #define BIT_SHIFT_H2CQ_HOST_IDX_8822B 0 #define BIT_MASK_H2CQ_HOST_IDX_8822B 0xfff #define BIT_H2CQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8822B) << BIT_SHIFT_H2CQ_HOST_IDX_8822B) #define BIT_GET_H2CQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822B) & BIT_MASK_H2CQ_HOST_IDX_8822B) + /* 2 REG_H2CQ_CSR_8822B[31:0] (H2CQ CONTROL AND STATUS) */ #define BIT_H2CQ_FULL_8822B BIT(31) #define BIT_CLR_H2CQ_HOST_IDX_8822B BIT(16) #define BIT_CLR_H2CQ_HW_IDX_8822B BIT(8) +/* 2 REG_CHANGE_PCIE_SPEED_8822B */ +#define BIT_CHANGE_PCIE_SPEED_8822B BIT(18) + +#define BIT_SHIFT_GEN1_GEN2_8822B 16 +#define BIT_MASK_GEN1_GEN2_8822B 0x3 +#define BIT_GEN1_GEN2_8822B(x) (((x) & BIT_MASK_GEN1_GEN2_8822B) << BIT_SHIFT_GEN1_GEN2_8822B) +#define BIT_GET_GEN1_GEN2_8822B(x) (((x) >> BIT_SHIFT_GEN1_GEN2_8822B) & BIT_MASK_GEN1_GEN2_8822B) + + + +#define BIT_SHIFT_AUTO_HANG_RELEASE_8822B 0 +#define BIT_MASK_AUTO_HANG_RELEASE_8822B 0x7 +#define BIT_AUTO_HANG_RELEASE_8822B(x) (((x) & BIT_MASK_AUTO_HANG_RELEASE_8822B) << BIT_SHIFT_AUTO_HANG_RELEASE_8822B) +#define BIT_GET_AUTO_HANG_RELEASE_8822B(x) (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE_8822B) & BIT_MASK_AUTO_HANG_RELEASE_8822B) + + + +/* 2 REG_OLD_DEHANG_8822B */ +#define BIT_OLD_DEHANG_8822B BIT(1) + /* 2 REG_Q0_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q0_V1_8822B 25 @@ -4731,11 +5216,13 @@ #define BIT_GET_QUEUEMACID_Q0_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) & BIT_MASK_QUEUEMACID_Q0_V1_8822B) + #define BIT_SHIFT_QUEUEAC_Q0_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q0_V1_8822B 0x3 #define BIT_QUEUEAC_Q0_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8822B) << BIT_SHIFT_QUEUEAC_Q0_V1_8822B) #define BIT_GET_QUEUEAC_Q0_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822B) & BIT_MASK_QUEUEAC_Q0_V1_8822B) + #define BIT_TIDEMPTY_Q0_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q0_V2_8822B 11 @@ -4744,12 +5231,14 @@ #define BIT_GET_TAIL_PKT_Q0_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) & BIT_MASK_TAIL_PKT_Q0_V2_8822B) + #define BIT_SHIFT_HEAD_PKT_Q0_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q0_V1_8822B 0x7ff #define BIT_HEAD_PKT_Q0_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) #define BIT_GET_HEAD_PKT_Q0_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) & BIT_MASK_HEAD_PKT_Q0_V1_8822B) + /* 2 REG_Q1_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q1_V1_8822B 25 @@ -4758,11 +5247,13 @@ #define BIT_GET_QUEUEMACID_Q1_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) & BIT_MASK_QUEUEMACID_Q1_V1_8822B) + #define BIT_SHIFT_QUEUEAC_Q1_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q1_V1_8822B 0x3 #define BIT_QUEUEAC_Q1_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8822B) << BIT_SHIFT_QUEUEAC_Q1_V1_8822B) #define BIT_GET_QUEUEAC_Q1_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822B) & BIT_MASK_QUEUEAC_Q1_V1_8822B) + #define BIT_TIDEMPTY_Q1_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q1_V2_8822B 11 @@ -4771,12 +5262,14 @@ #define BIT_GET_TAIL_PKT_Q1_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) & BIT_MASK_TAIL_PKT_Q1_V2_8822B) + #define BIT_SHIFT_HEAD_PKT_Q1_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q1_V1_8822B 0x7ff #define BIT_HEAD_PKT_Q1_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) #define BIT_GET_HEAD_PKT_Q1_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) & BIT_MASK_HEAD_PKT_Q1_V1_8822B) + /* 2 REG_Q2_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q2_V1_8822B 25 @@ -4785,11 +5278,13 @@ #define BIT_GET_QUEUEMACID_Q2_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) & BIT_MASK_QUEUEMACID_Q2_V1_8822B) + #define BIT_SHIFT_QUEUEAC_Q2_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q2_V1_8822B 0x3 #define BIT_QUEUEAC_Q2_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8822B) << BIT_SHIFT_QUEUEAC_Q2_V1_8822B) #define BIT_GET_QUEUEAC_Q2_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822B) & BIT_MASK_QUEUEAC_Q2_V1_8822B) + #define BIT_TIDEMPTY_Q2_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q2_V2_8822B 11 @@ -4798,12 +5293,14 @@ #define BIT_GET_TAIL_PKT_Q2_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) & BIT_MASK_TAIL_PKT_Q2_V2_8822B) + #define BIT_SHIFT_HEAD_PKT_Q2_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q2_V1_8822B 0x7ff #define BIT_HEAD_PKT_Q2_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) #define BIT_GET_HEAD_PKT_Q2_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) & BIT_MASK_HEAD_PKT_Q2_V1_8822B) + /* 2 REG_Q3_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q3_V1_8822B 25 @@ -4812,11 +5309,13 @@ #define BIT_GET_QUEUEMACID_Q3_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) & BIT_MASK_QUEUEMACID_Q3_V1_8822B) + #define BIT_SHIFT_QUEUEAC_Q3_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q3_V1_8822B 0x3 #define BIT_QUEUEAC_Q3_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8822B) << BIT_SHIFT_QUEUEAC_Q3_V1_8822B) #define BIT_GET_QUEUEAC_Q3_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822B) & BIT_MASK_QUEUEAC_Q3_V1_8822B) + #define BIT_TIDEMPTY_Q3_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q3_V2_8822B 11 @@ -4825,12 +5324,14 @@ #define BIT_GET_TAIL_PKT_Q3_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) & BIT_MASK_TAIL_PKT_Q3_V2_8822B) + #define BIT_SHIFT_HEAD_PKT_Q3_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q3_V1_8822B 0x7ff #define BIT_HEAD_PKT_Q3_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) #define BIT_GET_HEAD_PKT_Q3_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) & BIT_MASK_HEAD_PKT_Q3_V1_8822B) + /* 2 REG_MGQ_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B 25 @@ -4839,11 +5340,13 @@ #define BIT_GET_QUEUEMACID_MGQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B) + #define BIT_SHIFT_QUEUEAC_MGQ_V1_8822B 23 #define BIT_MASK_QUEUEAC_MGQ_V1_8822B 0x3 #define BIT_QUEUEAC_MGQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822B) << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) #define BIT_GET_QUEUEAC_MGQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) & BIT_MASK_QUEUEAC_MGQ_V1_8822B) + #define BIT_TIDEMPTY_MGQ_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B 11 @@ -4852,12 +5355,14 @@ #define BIT_GET_TAIL_PKT_MGQ_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B) + #define BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B 0 #define BIT_MASK_HEAD_PKT_MGQ_V1_8822B 0x7ff #define BIT_HEAD_PKT_MGQ_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) #define BIT_GET_HEAD_PKT_MGQ_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B) + /* 2 REG_HIQ_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B 25 @@ -4866,11 +5371,13 @@ #define BIT_GET_QUEUEMACID_HIQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B) + #define BIT_SHIFT_QUEUEAC_HIQ_V1_8822B 23 #define BIT_MASK_QUEUEAC_HIQ_V1_8822B 0x3 #define BIT_QUEUEAC_HIQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822B) << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) #define BIT_GET_QUEUEAC_HIQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) & BIT_MASK_QUEUEAC_HIQ_V1_8822B) + #define BIT_TIDEMPTY_HIQ_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B 11 @@ -4879,12 +5386,14 @@ #define BIT_GET_TAIL_PKT_HIQ_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B) + #define BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B 0 #define BIT_MASK_HEAD_PKT_HIQ_V1_8822B 0x7ff #define BIT_HEAD_PKT_HIQ_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) #define BIT_GET_HEAD_PKT_HIQ_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B) + /* 2 REG_BCNQ_INFO_8822B */ #define BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B 0 @@ -4893,6 +5402,7 @@ #define BIT_GET_BCNQ_HEAD_PG_V1_8822B(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B) + /* 2 REG_TXPKT_EMPTY_8822B */ #define BIT_BCNQ_EMPTY_8822B BIT(11) #define BIT_HQQ_EMPTY_8822B BIT(10) @@ -4919,6 +5429,7 @@ #define BIT_GET_FW_FREE_TAIL_V1_8822B(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822B) & BIT_MASK_FW_FREE_TAIL_V1_8822B) + /* 2 REG_FWHW_TXQ_CTRL_8822B */ #define BIT_RTS_LIMIT_IN_OFDM_8822B BIT(23) #define BIT_EN_BCNQ_DL_8822B BIT(22) @@ -4930,6 +5441,7 @@ #define BIT_EN_QUEUE_RPT_8822B(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8822B) << BIT_SHIFT_EN_QUEUE_RPT_8822B) #define BIT_GET_EN_QUEUE_RPT_8822B(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822B) & BIT_MASK_EN_QUEUE_RPT_8822B) + #define BIT_EN_RTY_BK_8822B BIT(7) #define BIT_EN_USE_INI_RAT_8822B BIT(6) #define BIT_EN_RTS_NAV_BK_8822B BIT(5) @@ -4948,6 +5460,7 @@ #define BIT_GET__R_DATA_FALLBACK_SEL_8822B(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B) + /* 2 REG_BCNQ_BDNY_V1_8822B */ #define BIT_SHIFT_BCNQ_PGBNDY_V1_8822B 0 @@ -4956,6 +5469,7 @@ #define BIT_GET_BCNQ_PGBNDY_V1_8822B(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) & BIT_MASK_BCNQ_PGBNDY_V1_8822B) + /* 2 REG_LIFETIME_EN_8822B */ #define BIT_BT_INT_CPU_8822B BIT(7) #define BIT_BT_INT_PTA_8822B BIT(6) @@ -4973,12 +5487,14 @@ #define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B) + #define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B 0 #define BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B 0xff #define BIT_SPEC_SIFS_CCK_PTCL_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) #define BIT_GET_SPEC_SIFS_CCK_PTCL_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) + /* 2 REG_RETRY_LIMIT_8822B */ #define BIT_SHIFT_SRL_8822B 8 @@ -4987,12 +5503,14 @@ #define BIT_GET_SRL_8822B(x) (((x) >> BIT_SHIFT_SRL_8822B) & BIT_MASK_SRL_8822B) + #define BIT_SHIFT_LRL_8822B 0 #define BIT_MASK_LRL_8822B 0x3f #define BIT_LRL_8822B(x) (((x) & BIT_MASK_LRL_8822B) << BIT_SHIFT_LRL_8822B) #define BIT_GET_LRL_8822B(x) (((x) >> BIT_SHIFT_LRL_8822B) & BIT_MASK_LRL_8822B) + /* 2 REG_TXBF_CTRL_8822B */ #define BIT_R_ENABLE_NDPA_8822B BIT(31) #define BIT_USE_NDPA_PARAMETER_8822B BIT(30) @@ -5007,6 +5525,7 @@ #define BIT_R_TXBF1_AID_8822B(x) (((x) & BIT_MASK_R_TXBF1_AID_8822B) << BIT_SHIFT_R_TXBF1_AID_8822B) #define BIT_GET_R_TXBF1_AID_8822B(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8822B) & BIT_MASK_R_TXBF1_AID_8822B) + #define BIT_DIS_NDP_BFEN_8822B BIT(15) #define BIT_R_TXBCN_NOBLOCK_NDP_8822B BIT(14) #define BIT_R_TXBF0_80M_8822B BIT(11) @@ -5019,6 +5538,7 @@ #define BIT_GET_R_TXBF0_AID_8822B(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8822B) & BIT_MASK_R_TXBF0_AID_8822B) + /* 2 REG_DARFRC_8822B */ #define BIT_SHIFT_DARF_RC8_8822B (56 & CPU_OPT_WIDTH) @@ -5027,48 +5547,56 @@ #define BIT_GET_DARF_RC8_8822B(x) (((x) >> BIT_SHIFT_DARF_RC8_8822B) & BIT_MASK_DARF_RC8_8822B) + #define BIT_SHIFT_DARF_RC7_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC7_8822B 0x1f #define BIT_DARF_RC7_8822B(x) (((x) & BIT_MASK_DARF_RC7_8822B) << BIT_SHIFT_DARF_RC7_8822B) #define BIT_GET_DARF_RC7_8822B(x) (((x) >> BIT_SHIFT_DARF_RC7_8822B) & BIT_MASK_DARF_RC7_8822B) + #define BIT_SHIFT_DARF_RC6_8822B (40 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC6_8822B 0x1f #define BIT_DARF_RC6_8822B(x) (((x) & BIT_MASK_DARF_RC6_8822B) << BIT_SHIFT_DARF_RC6_8822B) #define BIT_GET_DARF_RC6_8822B(x) (((x) >> BIT_SHIFT_DARF_RC6_8822B) & BIT_MASK_DARF_RC6_8822B) + #define BIT_SHIFT_DARF_RC5_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC5_8822B 0x1f #define BIT_DARF_RC5_8822B(x) (((x) & BIT_MASK_DARF_RC5_8822B) << BIT_SHIFT_DARF_RC5_8822B) #define BIT_GET_DARF_RC5_8822B(x) (((x) >> BIT_SHIFT_DARF_RC5_8822B) & BIT_MASK_DARF_RC5_8822B) + #define BIT_SHIFT_DARF_RC4_8822B 24 #define BIT_MASK_DARF_RC4_8822B 0x1f #define BIT_DARF_RC4_8822B(x) (((x) & BIT_MASK_DARF_RC4_8822B) << BIT_SHIFT_DARF_RC4_8822B) #define BIT_GET_DARF_RC4_8822B(x) (((x) >> BIT_SHIFT_DARF_RC4_8822B) & BIT_MASK_DARF_RC4_8822B) + #define BIT_SHIFT_DARF_RC3_8822B 16 #define BIT_MASK_DARF_RC3_8822B 0x1f #define BIT_DARF_RC3_8822B(x) (((x) & BIT_MASK_DARF_RC3_8822B) << BIT_SHIFT_DARF_RC3_8822B) #define BIT_GET_DARF_RC3_8822B(x) (((x) >> BIT_SHIFT_DARF_RC3_8822B) & BIT_MASK_DARF_RC3_8822B) + #define BIT_SHIFT_DARF_RC2_8822B 8 #define BIT_MASK_DARF_RC2_8822B 0x1f #define BIT_DARF_RC2_8822B(x) (((x) & BIT_MASK_DARF_RC2_8822B) << BIT_SHIFT_DARF_RC2_8822B) #define BIT_GET_DARF_RC2_8822B(x) (((x) >> BIT_SHIFT_DARF_RC2_8822B) & BIT_MASK_DARF_RC2_8822B) + #define BIT_SHIFT_DARF_RC1_8822B 0 #define BIT_MASK_DARF_RC1_8822B 0x1f #define BIT_DARF_RC1_8822B(x) (((x) & BIT_MASK_DARF_RC1_8822B) << BIT_SHIFT_DARF_RC1_8822B) #define BIT_GET_DARF_RC1_8822B(x) (((x) >> BIT_SHIFT_DARF_RC1_8822B) & BIT_MASK_DARF_RC1_8822B) + /* 2 REG_RARFRC_8822B */ #define BIT_SHIFT_RARF_RC8_8822B (56 & CPU_OPT_WIDTH) @@ -5077,48 +5605,56 @@ #define BIT_GET_RARF_RC8_8822B(x) (((x) >> BIT_SHIFT_RARF_RC8_8822B) & BIT_MASK_RARF_RC8_8822B) + #define BIT_SHIFT_RARF_RC7_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC7_8822B 0x1f #define BIT_RARF_RC7_8822B(x) (((x) & BIT_MASK_RARF_RC7_8822B) << BIT_SHIFT_RARF_RC7_8822B) #define BIT_GET_RARF_RC7_8822B(x) (((x) >> BIT_SHIFT_RARF_RC7_8822B) & BIT_MASK_RARF_RC7_8822B) + #define BIT_SHIFT_RARF_RC6_8822B (40 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC6_8822B 0x1f #define BIT_RARF_RC6_8822B(x) (((x) & BIT_MASK_RARF_RC6_8822B) << BIT_SHIFT_RARF_RC6_8822B) #define BIT_GET_RARF_RC6_8822B(x) (((x) >> BIT_SHIFT_RARF_RC6_8822B) & BIT_MASK_RARF_RC6_8822B) + #define BIT_SHIFT_RARF_RC5_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC5_8822B 0x1f #define BIT_RARF_RC5_8822B(x) (((x) & BIT_MASK_RARF_RC5_8822B) << BIT_SHIFT_RARF_RC5_8822B) #define BIT_GET_RARF_RC5_8822B(x) (((x) >> BIT_SHIFT_RARF_RC5_8822B) & BIT_MASK_RARF_RC5_8822B) + #define BIT_SHIFT_RARF_RC4_8822B 24 #define BIT_MASK_RARF_RC4_8822B 0x1f #define BIT_RARF_RC4_8822B(x) (((x) & BIT_MASK_RARF_RC4_8822B) << BIT_SHIFT_RARF_RC4_8822B) #define BIT_GET_RARF_RC4_8822B(x) (((x) >> BIT_SHIFT_RARF_RC4_8822B) & BIT_MASK_RARF_RC4_8822B) + #define BIT_SHIFT_RARF_RC3_8822B 16 #define BIT_MASK_RARF_RC3_8822B 0x1f #define BIT_RARF_RC3_8822B(x) (((x) & BIT_MASK_RARF_RC3_8822B) << BIT_SHIFT_RARF_RC3_8822B) #define BIT_GET_RARF_RC3_8822B(x) (((x) >> BIT_SHIFT_RARF_RC3_8822B) & BIT_MASK_RARF_RC3_8822B) + #define BIT_SHIFT_RARF_RC2_8822B 8 #define BIT_MASK_RARF_RC2_8822B 0x1f #define BIT_RARF_RC2_8822B(x) (((x) & BIT_MASK_RARF_RC2_8822B) << BIT_SHIFT_RARF_RC2_8822B) #define BIT_GET_RARF_RC2_8822B(x) (((x) >> BIT_SHIFT_RARF_RC2_8822B) & BIT_MASK_RARF_RC2_8822B) + #define BIT_SHIFT_RARF_RC1_8822B 0 #define BIT_MASK_RARF_RC1_8822B 0x1f #define BIT_RARF_RC1_8822B(x) (((x) & BIT_MASK_RARF_RC1_8822B) << BIT_SHIFT_RARF_RC1_8822B) #define BIT_GET_RARF_RC1_8822B(x) (((x) >> BIT_SHIFT_RARF_RC1_8822B) & BIT_MASK_RARF_RC1_8822B) + /* 2 REG_RRSR_8822B */ #define BIT_SHIFT_RRSR_RSC_8822B 21 @@ -5126,6 +5662,7 @@ #define BIT_RRSR_RSC_8822B(x) (((x) & BIT_MASK_RRSR_RSC_8822B) << BIT_SHIFT_RRSR_RSC_8822B) #define BIT_GET_RRSR_RSC_8822B(x) (((x) >> BIT_SHIFT_RRSR_RSC_8822B) & BIT_MASK_RRSR_RSC_8822B) + #define BIT_RRSR_BW_8822B BIT(20) #define BIT_SHIFT_RRSC_BITMAP_8822B 0 @@ -5134,6 +5671,7 @@ #define BIT_GET_RRSC_BITMAP_8822B(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8822B) & BIT_MASK_RRSC_BITMAP_8822B) + /* 2 REG_ARFR0_8822B */ #define BIT_SHIFT_ARFR0_V1_8822B 0 @@ -5142,6 +5680,7 @@ #define BIT_GET_ARFR0_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR0_V1_8822B) & BIT_MASK_ARFR0_V1_8822B) + /* 2 REG_ARFR1_V1_8822B */ #define BIT_SHIFT_ARFR1_V1_8822B 0 @@ -5150,6 +5689,7 @@ #define BIT_GET_ARFR1_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR1_V1_8822B) & BIT_MASK_ARFR1_V1_8822B) + /* 2 REG_CCK_CHECK_8822B */ #define BIT_CHECK_CCK_EN_8822B BIT(7) #define BIT_EN_BCN_PKT_REL_8822B BIT(6) @@ -5168,6 +5708,7 @@ #define BIT_GET_AMPDU_MAX_TIME_8822B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822B) & BIT_MASK_AMPDU_MAX_TIME_8822B) + /* 2 REG_BCNQ1_BDNY_V1_8822B */ #define BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B 0 @@ -5176,6 +5717,7 @@ #define BIT_GET_BCNQ1_PGBNDY_V1_8822B(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B) + /* 2 REG_AMPDU_MAX_LENGTH_8822B */ #define BIT_SHIFT_AMPDU_MAX_LENGTH_8822B 0 @@ -5184,6 +5726,7 @@ #define BIT_GET_AMPDU_MAX_LENGTH_8822B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) & BIT_MASK_AMPDU_MAX_LENGTH_8822B) + /* 2 REG_ACQ_STOP_8822B */ #define BIT_AC7Q_STOP_8822B BIT(7) #define BIT_AC6Q_STOP_8822B BIT(6) @@ -5202,6 +5745,7 @@ #define BIT_GET_R_NDPA_RATE_V1_8822B(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822B) & BIT_MASK_R_NDPA_RATE_V1_8822B) + /* 2 REG_TX_HANG_CTRL_8822B */ #define BIT_R_EN_GNT_BT_AWAKE_8822B BIT(3) #define BIT_EN_EOF_V1_8822B BIT(2) @@ -5216,6 +5760,7 @@ #define BIT_BW_SIGTA_8822B(x) (((x) & BIT_MASK_BW_SIGTA_8822B) << BIT_SHIFT_BW_SIGTA_8822B) #define BIT_GET_BW_SIGTA_8822B(x) (((x) >> BIT_SHIFT_BW_SIGTA_8822B) & BIT_MASK_BW_SIGTA_8822B) + #define BIT_EN_BAR_SIGTA_8822B BIT(2) #define BIT_SHIFT_R_NDPA_BW_8822B 0 @@ -5224,6 +5769,7 @@ #define BIT_GET_R_NDPA_BW_8822B(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8822B) & BIT_MASK_R_NDPA_BW_8822B) + /* 2 REG_RD_RESP_PKT_TH_8822B */ #define BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B 0 @@ -5232,6 +5778,7 @@ #define BIT_GET_RD_RESP_PKT_TH_V1_8822B(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B) + /* 2 REG_CMDQ_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B 25 @@ -5240,11 +5787,13 @@ #define BIT_GET_QUEUEMACID_CMDQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B) + #define BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B 23 #define BIT_MASK_QUEUEAC_CMDQ_V1_8822B 0x3 #define BIT_QUEUEAC_CMDQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B) << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) #define BIT_GET_QUEUEAC_CMDQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B) + #define BIT_TIDEMPTY_CMDQ_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B 11 @@ -5253,12 +5802,14 @@ #define BIT_GET_TAIL_PKT_CMDQ_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B) + #define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B 0 #define BIT_MASK_HEAD_PKT_CMDQ_V1_8822B 0x7ff #define BIT_HEAD_PKT_CMDQ_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) #define BIT_GET_HEAD_PKT_CMDQ_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) + /* 2 REG_Q4_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q4_V1_8822B 25 @@ -5267,11 +5818,13 @@ #define BIT_GET_QUEUEMACID_Q4_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) & BIT_MASK_QUEUEMACID_Q4_V1_8822B) + #define BIT_SHIFT_QUEUEAC_Q4_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q4_V1_8822B 0x3 #define BIT_QUEUEAC_Q4_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8822B) << BIT_SHIFT_QUEUEAC_Q4_V1_8822B) #define BIT_GET_QUEUEAC_Q4_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822B) & BIT_MASK_QUEUEAC_Q4_V1_8822B) + #define BIT_TIDEMPTY_Q4_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q4_V2_8822B 11 @@ -5280,12 +5833,14 @@ #define BIT_GET_TAIL_PKT_Q4_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) & BIT_MASK_TAIL_PKT_Q4_V2_8822B) + #define BIT_SHIFT_HEAD_PKT_Q4_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q4_V1_8822B 0x7ff #define BIT_HEAD_PKT_Q4_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) #define BIT_GET_HEAD_PKT_Q4_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) & BIT_MASK_HEAD_PKT_Q4_V1_8822B) + /* 2 REG_Q5_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q5_V1_8822B 25 @@ -5294,11 +5849,13 @@ #define BIT_GET_QUEUEMACID_Q5_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) & BIT_MASK_QUEUEMACID_Q5_V1_8822B) + #define BIT_SHIFT_QUEUEAC_Q5_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q5_V1_8822B 0x3 #define BIT_QUEUEAC_Q5_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8822B) << BIT_SHIFT_QUEUEAC_Q5_V1_8822B) #define BIT_GET_QUEUEAC_Q5_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822B) & BIT_MASK_QUEUEAC_Q5_V1_8822B) + #define BIT_TIDEMPTY_Q5_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q5_V2_8822B 11 @@ -5307,12 +5864,14 @@ #define BIT_GET_TAIL_PKT_Q5_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) & BIT_MASK_TAIL_PKT_Q5_V2_8822B) + #define BIT_SHIFT_HEAD_PKT_Q5_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q5_V1_8822B 0x7ff #define BIT_HEAD_PKT_Q5_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) #define BIT_GET_HEAD_PKT_Q5_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) & BIT_MASK_HEAD_PKT_Q5_V1_8822B) + /* 2 REG_Q6_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q6_V1_8822B 25 @@ -5321,11 +5880,13 @@ #define BIT_GET_QUEUEMACID_Q6_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) & BIT_MASK_QUEUEMACID_Q6_V1_8822B) + #define BIT_SHIFT_QUEUEAC_Q6_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q6_V1_8822B 0x3 #define BIT_QUEUEAC_Q6_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8822B) << BIT_SHIFT_QUEUEAC_Q6_V1_8822B) #define BIT_GET_QUEUEAC_Q6_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822B) & BIT_MASK_QUEUEAC_Q6_V1_8822B) + #define BIT_TIDEMPTY_Q6_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q6_V2_8822B 11 @@ -5334,12 +5895,14 @@ #define BIT_GET_TAIL_PKT_Q6_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) & BIT_MASK_TAIL_PKT_Q6_V2_8822B) + #define BIT_SHIFT_HEAD_PKT_Q6_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q6_V1_8822B 0x7ff #define BIT_HEAD_PKT_Q6_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) #define BIT_GET_HEAD_PKT_Q6_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) & BIT_MASK_HEAD_PKT_Q6_V1_8822B) + /* 2 REG_Q7_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q7_V1_8822B 25 @@ -5348,11 +5911,13 @@ #define BIT_GET_QUEUEMACID_Q7_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) & BIT_MASK_QUEUEMACID_Q7_V1_8822B) + #define BIT_SHIFT_QUEUEAC_Q7_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q7_V1_8822B 0x3 #define BIT_QUEUEAC_Q7_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8822B) << BIT_SHIFT_QUEUEAC_Q7_V1_8822B) #define BIT_GET_QUEUEAC_Q7_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822B) & BIT_MASK_QUEUEAC_Q7_V1_8822B) + #define BIT_TIDEMPTY_Q7_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q7_V2_8822B 11 @@ -5361,12 +5926,14 @@ #define BIT_GET_TAIL_PKT_Q7_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) & BIT_MASK_TAIL_PKT_Q7_V2_8822B) + #define BIT_SHIFT_HEAD_PKT_Q7_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q7_V1_8822B 0x7ff #define BIT_HEAD_PKT_Q7_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) #define BIT_GET_HEAD_PKT_Q7_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) & BIT_MASK_HEAD_PKT_Q7_V1_8822B) + /* 2 REG_WMAC_LBK_BUF_HD_V1_8822B */ #define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B 0 @@ -5375,6 +5942,7 @@ #define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822B(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B) + /* 2 REG_MGQ_BDNY_V1_8822B */ #define BIT_SHIFT_MGQ_PGBNDY_V1_8822B 0 @@ -5383,6 +5951,7 @@ #define BIT_GET_MGQ_PGBNDY_V1_8822B(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822B) & BIT_MASK_MGQ_PGBNDY_V1_8822B) + /* 2 REG_TXRPT_CTRL_8822B */ #define BIT_SHIFT_TRXRPT_TIMER_TH_8822B 24 @@ -5391,24 +5960,28 @@ #define BIT_GET_TRXRPT_TIMER_TH_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822B) & BIT_MASK_TRXRPT_TIMER_TH_8822B) + #define BIT_SHIFT_TRXRPT_LEN_TH_8822B 16 #define BIT_MASK_TRXRPT_LEN_TH_8822B 0xff #define BIT_TRXRPT_LEN_TH_8822B(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8822B) << BIT_SHIFT_TRXRPT_LEN_TH_8822B) #define BIT_GET_TRXRPT_LEN_TH_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822B) & BIT_MASK_TRXRPT_LEN_TH_8822B) + #define BIT_SHIFT_TRXRPT_READ_PTR_8822B 8 #define BIT_MASK_TRXRPT_READ_PTR_8822B 0xff #define BIT_TRXRPT_READ_PTR_8822B(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8822B) << BIT_SHIFT_TRXRPT_READ_PTR_8822B) #define BIT_GET_TRXRPT_READ_PTR_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822B) & BIT_MASK_TRXRPT_READ_PTR_8822B) + #define BIT_SHIFT_TRXRPT_WRITE_PTR_8822B 0 #define BIT_MASK_TRXRPT_WRITE_PTR_8822B 0xff #define BIT_TRXRPT_WRITE_PTR_8822B(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822B) << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) #define BIT_GET_TRXRPT_WRITE_PTR_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) & BIT_MASK_TRXRPT_WRITE_PTR_8822B) + /* 2 REG_INIRTS_RATE_SEL_8822B */ #define BIT_LEAG_RTS_BW_DUP_8822B BIT(5) @@ -5420,6 +5993,7 @@ #define BIT_GET_BASIC_CFEND_RATE_8822B(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822B) & BIT_MASK_BASIC_CFEND_RATE_8822B) + /* 2 REG_STBC_CFEND_RATE_8822B */ #define BIT_SHIFT_STBC_CFEND_RATE_8822B 0 @@ -5428,6 +6002,7 @@ #define BIT_GET_STBC_CFEND_RATE_8822B(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822B) & BIT_MASK_STBC_CFEND_RATE_8822B) + /* 2 REG_DATA_SC_8822B */ #define BIT_SHIFT_TXSC_40M_8822B 4 @@ -5436,12 +6011,14 @@ #define BIT_GET_TXSC_40M_8822B(x) (((x) >> BIT_SHIFT_TXSC_40M_8822B) & BIT_MASK_TXSC_40M_8822B) + #define BIT_SHIFT_TXSC_20M_8822B 0 #define BIT_MASK_TXSC_20M_8822B 0xf #define BIT_TXSC_20M_8822B(x) (((x) & BIT_MASK_TXSC_20M_8822B) << BIT_SHIFT_TXSC_20M_8822B) #define BIT_GET_TXSC_20M_8822B(x) (((x) >> BIT_SHIFT_TXSC_20M_8822B) & BIT_MASK_TXSC_20M_8822B) + /* 2 REG_MACID_SLEEP3_8822B */ #define BIT_SHIFT_MACID127_96_PKTSLEEP_8822B 0 @@ -5450,6 +6027,7 @@ #define BIT_GET_MACID127_96_PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) & BIT_MASK_MACID127_96_PKTSLEEP_8822B) + /* 2 REG_MACID_SLEEP1_8822B */ #define BIT_SHIFT_MACID63_32_PKTSLEEP_8822B 0 @@ -5458,6 +6036,7 @@ #define BIT_GET_MACID63_32_PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) & BIT_MASK_MACID63_32_PKTSLEEP_8822B) + /* 2 REG_ARFR2_V1_8822B */ #define BIT_SHIFT_ARFR2_V1_8822B 0 @@ -5466,6 +6045,7 @@ #define BIT_GET_ARFR2_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR2_V1_8822B) & BIT_MASK_ARFR2_V1_8822B) + /* 2 REG_ARFR3_V1_8822B */ #define BIT_SHIFT_ARFR3_V1_8822B 0 @@ -5474,6 +6054,7 @@ #define BIT_GET_ARFR3_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR3_V1_8822B) & BIT_MASK_ARFR3_V1_8822B) + /* 2 REG_ARFR4_8822B */ #define BIT_SHIFT_ARFR4_8822B 0 @@ -5482,6 +6063,7 @@ #define BIT_GET_ARFR4_8822B(x) (((x) >> BIT_SHIFT_ARFR4_8822B) & BIT_MASK_ARFR4_8822B) + /* 2 REG_ARFR5_8822B */ #define BIT_SHIFT_ARFR5_8822B 0 @@ -5490,6 +6072,7 @@ #define BIT_GET_ARFR5_8822B(x) (((x) >> BIT_SHIFT_ARFR5_8822B) & BIT_MASK_ARFR5_8822B) + /* 2 REG_TXRPT_START_OFFSET_8822B */ #define BIT_SHIFT_MACID_MURATE_OFFSET_8822B 24 @@ -5497,6 +6080,7 @@ #define BIT_MACID_MURATE_OFFSET_8822B(x) (((x) & BIT_MASK_MACID_MURATE_OFFSET_8822B) << BIT_SHIFT_MACID_MURATE_OFFSET_8822B) #define BIT_GET_MACID_MURATE_OFFSET_8822B(x) (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822B) & BIT_MASK_MACID_MURATE_OFFSET_8822B) + #define BIT_RPTFIFO_SIZE_OPT_8822B BIT(16) #define BIT_SHIFT_MACID_CTRL_OFFSET_8822B 8 @@ -5505,12 +6089,14 @@ #define BIT_GET_MACID_CTRL_OFFSET_8822B(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822B) & BIT_MASK_MACID_CTRL_OFFSET_8822B) + #define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B 0 #define BIT_MASK_AMPDU_TXRPT_OFFSET_8822B 0xff #define BIT_AMPDU_TXRPT_OFFSET_8822B(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) #define BIT_GET_AMPDU_TXRPT_OFFSET_8822B(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) + /* 2 REG_POWER_STAGE1_8822B */ #define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8822B BIT(31) #define BIT_PTA_WL_PRI_MASK_BCNQ_8822B BIT(30) @@ -5527,6 +6113,7 @@ #define BIT_GET_POWER_STAGE1_8822B(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8822B) & BIT_MASK_POWER_STAGE1_8822B) + /* 2 REG_POWER_STAGE2_8822B */ #define BIT__R_CTRL_PKT_POW_ADJ_8822B BIT(24) @@ -5536,6 +6123,7 @@ #define BIT_GET_POWER_STAGE2_8822B(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8822B) & BIT_MASK_POWER_STAGE2_8822B) + /* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8822B */ #define BIT_SHIFT_PAD_NUM_THRES_8822B 24 @@ -5543,6 +6131,7 @@ #define BIT_PAD_NUM_THRES_8822B(x) (((x) & BIT_MASK_PAD_NUM_THRES_8822B) << BIT_SHIFT_PAD_NUM_THRES_8822B) #define BIT_GET_PAD_NUM_THRES_8822B(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8822B) & BIT_MASK_PAD_NUM_THRES_8822B) + #define BIT_R_DMA_THIS_QUEUE_BK_8822B BIT(23) #define BIT_R_DMA_THIS_QUEUE_BE_8822B BIT(22) #define BIT_R_DMA_THIS_QUEUE_VI_8822B BIT(21) @@ -5553,6 +6142,7 @@ #define BIT_R_TOTAL_LEN_TH_8822B(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8822B) << BIT_SHIFT_R_TOTAL_LEN_TH_8822B) #define BIT_GET_R_TOTAL_LEN_TH_8822B(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822B) & BIT_MASK_R_TOTAL_LEN_TH_8822B) + #define BIT_EN_NEW_EARLY_8822B BIT(7) #define BIT_PRE_TX_CMD_8822B BIT(6) @@ -5561,6 +6151,7 @@ #define BIT_NUM_SCL_EN_8822B(x) (((x) & BIT_MASK_NUM_SCL_EN_8822B) << BIT_SHIFT_NUM_SCL_EN_8822B) #define BIT_GET_NUM_SCL_EN_8822B(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8822B) & BIT_MASK_NUM_SCL_EN_8822B) + #define BIT_BK_EN_8822B BIT(3) #define BIT_BE_EN_8822B BIT(2) #define BIT_VI_EN_8822B BIT(1) @@ -5574,12 +6165,14 @@ #define BIT_GET_PKT_LIFTIME_BEBK_8822B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) & BIT_MASK_PKT_LIFTIME_BEBK_8822B) + #define BIT_SHIFT_PKT_LIFTIME_VOVI_8822B 0 #define BIT_MASK_PKT_LIFTIME_VOVI_8822B 0xffff #define BIT_PKT_LIFTIME_VOVI_8822B(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822B) << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) #define BIT_GET_PKT_LIFTIME_VOVI_8822B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) & BIT_MASK_PKT_LIFTIME_VOVI_8822B) + /* 2 REG_STBC_SETTING_8822B */ #define BIT_SHIFT_CDEND_TXTIME_L_8822B 4 @@ -5588,18 +6181,21 @@ #define BIT_GET_CDEND_TXTIME_L_8822B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822B) & BIT_MASK_CDEND_TXTIME_L_8822B) + #define BIT_SHIFT_NESS_8822B 2 #define BIT_MASK_NESS_8822B 0x3 #define BIT_NESS_8822B(x) (((x) & BIT_MASK_NESS_8822B) << BIT_SHIFT_NESS_8822B) #define BIT_GET_NESS_8822B(x) (((x) >> BIT_SHIFT_NESS_8822B) & BIT_MASK_NESS_8822B) + #define BIT_SHIFT_STBC_CFEND_8822B 0 #define BIT_MASK_STBC_CFEND_8822B 0x3 #define BIT_STBC_CFEND_8822B(x) (((x) & BIT_MASK_STBC_CFEND_8822B) << BIT_SHIFT_STBC_CFEND_8822B) #define BIT_GET_STBC_CFEND_8822B(x) (((x) >> BIT_SHIFT_STBC_CFEND_8822B) & BIT_MASK_STBC_CFEND_8822B) + /* 2 REG_STBC_SETTING2_8822B */ #define BIT_SHIFT_CDEND_TXTIME_H_8822B 0 @@ -5608,6 +6204,7 @@ #define BIT_GET_CDEND_TXTIME_H_8822B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822B) & BIT_MASK_CDEND_TXTIME_H_8822B) + /* 2 REG_QUEUE_CTRL_8822B */ #define BIT_PTA_EDCCA_EN_8822B BIT(5) #define BIT_PTA_WL_TX_EN_8822B BIT(4) @@ -5627,24 +6224,28 @@ #define BIT_GET_RTS_MAX_AGG_NUM_8822B(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) & BIT_MASK_RTS_MAX_AGG_NUM_8822B) + #define BIT_SHIFT_MAX_AGG_NUM_8822B 16 #define BIT_MASK_MAX_AGG_NUM_8822B 0x3f #define BIT_MAX_AGG_NUM_8822B(x) (((x) & BIT_MASK_MAX_AGG_NUM_8822B) << BIT_SHIFT_MAX_AGG_NUM_8822B) #define BIT_GET_MAX_AGG_NUM_8822B(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8822B) & BIT_MASK_MAX_AGG_NUM_8822B) + #define BIT_SHIFT_RTS_TXTIME_TH_8822B 8 #define BIT_MASK_RTS_TXTIME_TH_8822B 0xff #define BIT_RTS_TXTIME_TH_8822B(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8822B) << BIT_SHIFT_RTS_TXTIME_TH_8822B) #define BIT_GET_RTS_TXTIME_TH_8822B(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822B) & BIT_MASK_RTS_TXTIME_TH_8822B) + #define BIT_SHIFT_RTS_LEN_TH_8822B 0 #define BIT_MASK_RTS_LEN_TH_8822B 0xff #define BIT_RTS_LEN_TH_8822B(x) (((x) & BIT_MASK_RTS_LEN_TH_8822B) << BIT_SHIFT_RTS_LEN_TH_8822B) #define BIT_GET_RTS_LEN_TH_8822B(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8822B) & BIT_MASK_RTS_LEN_TH_8822B) + /* 2 REG_BAR_MODE_CTRL_8822B */ #define BIT_SHIFT_BAR_RTY_LMT_8822B 16 @@ -5653,11 +6254,13 @@ #define BIT_GET_BAR_RTY_LMT_8822B(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8822B) & BIT_MASK_BAR_RTY_LMT_8822B) + #define BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B 8 #define BIT_MASK_BAR_PKT_TXTIME_TH_8822B 0xff #define BIT_BAR_PKT_TXTIME_TH_8822B(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) #define BIT_GET_BAR_PKT_TXTIME_TH_8822B(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B) + #define BIT_BAR_EN_V1_8822B BIT(6) #define BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B 0 @@ -5666,6 +6269,7 @@ #define BIT_GET_BAR_PKTNUM_TH_V1_8822B(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B) + /* 2 REG_RA_TRY_RATE_AGG_LMT_8822B */ #define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B 0 @@ -5674,6 +6278,7 @@ #define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822B(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B) + /* 2 REG_MACID_SLEEP2_8822B */ #define BIT_SHIFT_MACID95_64PKTSLEEP_8822B 0 @@ -5682,6 +6287,7 @@ #define BIT_GET_MACID95_64PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822B) & BIT_MASK_MACID95_64PKTSLEEP_8822B) + /* 2 REG_MACID_SLEEP_8822B */ #define BIT_SHIFT_MACID31_0_PKTSLEEP_8822B 0 @@ -5690,6 +6296,7 @@ #define BIT_GET_MACID31_0_PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) & BIT_MASK_MACID31_0_PKTSLEEP_8822B) + /* 2 REG_HW_SEQ0_8822B */ #define BIT_SHIFT_HW_SSN_SEQ0_8822B 0 @@ -5698,6 +6305,7 @@ #define BIT_GET_HW_SSN_SEQ0_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822B) & BIT_MASK_HW_SSN_SEQ0_8822B) + /* 2 REG_HW_SEQ1_8822B */ #define BIT_SHIFT_HW_SSN_SEQ1_8822B 0 @@ -5706,6 +6314,7 @@ #define BIT_GET_HW_SSN_SEQ1_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822B) & BIT_MASK_HW_SSN_SEQ1_8822B) + /* 2 REG_HW_SEQ2_8822B */ #define BIT_SHIFT_HW_SSN_SEQ2_8822B 0 @@ -5714,6 +6323,7 @@ #define BIT_GET_HW_SSN_SEQ2_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822B) & BIT_MASK_HW_SSN_SEQ2_8822B) + /* 2 REG_HW_SEQ3_8822B */ #define BIT_SHIFT_HW_SSN_SEQ3_8822B 0 @@ -5722,6 +6332,7 @@ #define BIT_GET_HW_SSN_SEQ3_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822B) & BIT_MASK_HW_SSN_SEQ3_8822B) + /* 2 REG_NULL_PKT_STATUS_V1_8822B */ #define BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B 2 @@ -5729,6 +6340,7 @@ #define BIT_PTCL_TOTAL_PG_V2_8822B(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B) << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) #define BIT_GET_PTCL_TOTAL_PG_V2_8822B(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B) + #define BIT_TX_NULL_1_8822B BIT(1) #define BIT_TX_NULL_0_8822B BIT(0) @@ -5764,6 +6376,7 @@ #define BIT_GET_BT_POLLUTE_PKT_CNT_8822B(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_PTCL_DBG_8822B */ @@ -5774,6 +6387,7 @@ #define BIT_GET_PTCL_DBG_8822B(x) (((x) >> BIT_SHIFT_PTCL_DBG_8822B) & BIT_MASK_PTCL_DBG_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_CPUMGQ_TIMER_CTRL2_8822B */ @@ -5783,6 +6397,7 @@ #define BIT_TRI_HEAD_ADDR_8822B(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8822B) << BIT_SHIFT_TRI_HEAD_ADDR_8822B) #define BIT_GET_TRI_HEAD_ADDR_8822B(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822B) & BIT_MASK_TRI_HEAD_ADDR_8822B) + #define BIT_DROP_TH_EN_8822B BIT(8) #define BIT_SHIFT_DROP_TH_8822B 0 @@ -5791,6 +6406,7 @@ #define BIT_GET_DROP_TH_8822B(x) (((x) >> BIT_SHIFT_DROP_TH_8822B) & BIT_MASK_DROP_TH_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_DUMMY_PAGE4_V1_8822B */ @@ -5813,11 +6429,13 @@ #define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) + #define BIT_SHIFT_AC1_PKT_INFO_8822B 16 #define BIT_MASK_AC1_PKT_INFO_8822B 0xfff #define BIT_AC1_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC1_PKT_INFO_8822B) << BIT_SHIFT_AC1_PKT_INFO_8822B) #define BIT_GET_AC1_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8822B) & BIT_MASK_AC1_PKT_INFO_8822B) + #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8822B 12 @@ -5826,12 +6444,14 @@ #define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) + #define BIT_SHIFT_AC0_PKT_INFO_8822B 0 #define BIT_MASK_AC0_PKT_INFO_8822B 0xfff #define BIT_AC0_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC0_PKT_INFO_8822B) << BIT_SHIFT_AC0_PKT_INFO_8822B) #define BIT_GET_AC0_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8822B) & BIT_MASK_AC0_PKT_INFO_8822B) + /* 2 REG_Q2_Q3_INFO_8822B */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31) @@ -5841,11 +6461,13 @@ #define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) + #define BIT_SHIFT_AC3_PKT_INFO_8822B 16 #define BIT_MASK_AC3_PKT_INFO_8822B 0xfff #define BIT_AC3_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC3_PKT_INFO_8822B) << BIT_SHIFT_AC3_PKT_INFO_8822B) #define BIT_GET_AC3_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8822B) & BIT_MASK_AC3_PKT_INFO_8822B) + #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8822B 12 @@ -5854,12 +6476,14 @@ #define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) + #define BIT_SHIFT_AC2_PKT_INFO_8822B 0 #define BIT_MASK_AC2_PKT_INFO_8822B 0xfff #define BIT_AC2_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC2_PKT_INFO_8822B) << BIT_SHIFT_AC2_PKT_INFO_8822B) #define BIT_GET_AC2_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8822B) & BIT_MASK_AC2_PKT_INFO_8822B) + /* 2 REG_Q4_Q5_INFO_8822B */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31) @@ -5869,11 +6493,13 @@ #define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) + #define BIT_SHIFT_AC5_PKT_INFO_8822B 16 #define BIT_MASK_AC5_PKT_INFO_8822B 0xfff #define BIT_AC5_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC5_PKT_INFO_8822B) << BIT_SHIFT_AC5_PKT_INFO_8822B) #define BIT_GET_AC5_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8822B) & BIT_MASK_AC5_PKT_INFO_8822B) + #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8822B 12 @@ -5882,12 +6508,14 @@ #define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) + #define BIT_SHIFT_AC4_PKT_INFO_8822B 0 #define BIT_MASK_AC4_PKT_INFO_8822B 0xfff #define BIT_AC4_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC4_PKT_INFO_8822B) << BIT_SHIFT_AC4_PKT_INFO_8822B) #define BIT_GET_AC4_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8822B) & BIT_MASK_AC4_PKT_INFO_8822B) + /* 2 REG_Q6_Q7_INFO_8822B */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31) @@ -5897,11 +6525,13 @@ #define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) + #define BIT_SHIFT_AC7_PKT_INFO_8822B 16 #define BIT_MASK_AC7_PKT_INFO_8822B 0xfff #define BIT_AC7_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC7_PKT_INFO_8822B) << BIT_SHIFT_AC7_PKT_INFO_8822B) #define BIT_GET_AC7_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8822B) & BIT_MASK_AC7_PKT_INFO_8822B) + #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8822B 12 @@ -5910,12 +6540,14 @@ #define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) + #define BIT_SHIFT_AC6_PKT_INFO_8822B 0 #define BIT_MASK_AC6_PKT_INFO_8822B 0xfff #define BIT_AC6_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC6_PKT_INFO_8822B) << BIT_SHIFT_AC6_PKT_INFO_8822B) #define BIT_GET_AC6_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8822B) & BIT_MASK_AC6_PKT_INFO_8822B) + /* 2 REG_MGQ_HIQ_INFO_8822B */ #define BIT_SHIFT_HIQ_PKT_INFO_8822B 16 @@ -5924,12 +6556,14 @@ #define BIT_GET_HIQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822B) & BIT_MASK_HIQ_PKT_INFO_8822B) + #define BIT_SHIFT_MGQ_PKT_INFO_8822B 0 #define BIT_MASK_MGQ_PKT_INFO_8822B 0xfff #define BIT_MGQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8822B) << BIT_SHIFT_MGQ_PKT_INFO_8822B) #define BIT_GET_MGQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822B) & BIT_MASK_MGQ_PKT_INFO_8822B) + /* 2 REG_CMDQ_BCNQ_INFO_8822B */ #define BIT_SHIFT_CMDQ_PKT_INFO_8822B 16 @@ -5938,12 +6572,14 @@ #define BIT_GET_CMDQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822B) & BIT_MASK_CMDQ_PKT_INFO_8822B) + #define BIT_SHIFT_BCNQ_PKT_INFO_8822B 0 #define BIT_MASK_BCNQ_PKT_INFO_8822B 0xfff #define BIT_BCNQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_8822B) << BIT_SHIFT_BCNQ_PKT_INFO_8822B) #define BIT_GET_BCNQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822B) & BIT_MASK_BCNQ_PKT_INFO_8822B) + /* 2 REG_USEREG_SETTING_8822B */ #define BIT_NDPA_USEREG_8822B BIT(21) @@ -5953,11 +6589,13 @@ #define BIT_GET_RETRY_USEREG_8822B(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8822B) & BIT_MASK_RETRY_USEREG_8822B) + #define BIT_SHIFT_TRYPKT_USEREG_8822B 17 #define BIT_MASK_TRYPKT_USEREG_8822B 0x3 #define BIT_TRYPKT_USEREG_8822B(x) (((x) & BIT_MASK_TRYPKT_USEREG_8822B) << BIT_SHIFT_TRYPKT_USEREG_8822B) #define BIT_GET_TRYPKT_USEREG_8822B(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8822B) & BIT_MASK_TRYPKT_USEREG_8822B) + #define BIT_CTLPKT_USEREG_8822B BIT(16) /* 2 REG_AESIV_SETTING_8822B */ @@ -5968,6 +6606,7 @@ #define BIT_GET_AESIV_OFFSET_8822B(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8822B) & BIT_MASK_AESIV_OFFSET_8822B) + /* 2 REG_BF0_TIME_SETTING_8822B */ #define BIT_BF0_TIMER_SET_8822B BIT(31) #define BIT_BF0_TIMER_CLR_8822B BIT(30) @@ -5980,12 +6619,14 @@ #define BIT_GET_BF0_PRETIME_OVER_8822B(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822B) & BIT_MASK_BF0_PRETIME_OVER_8822B) + #define BIT_SHIFT_BF0_LIFETIME_8822B 0 #define BIT_MASK_BF0_LIFETIME_8822B 0xffff #define BIT_BF0_LIFETIME_8822B(x) (((x) & BIT_MASK_BF0_LIFETIME_8822B) << BIT_SHIFT_BF0_LIFETIME_8822B) #define BIT_GET_BF0_LIFETIME_8822B(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8822B) & BIT_MASK_BF0_LIFETIME_8822B) + /* 2 REG_BF1_TIME_SETTING_8822B */ #define BIT_BF1_TIMER_SET_8822B BIT(31) #define BIT_BF1_TIMER_CLR_8822B BIT(30) @@ -5998,12 +6639,14 @@ #define BIT_GET_BF1_PRETIME_OVER_8822B(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822B) & BIT_MASK_BF1_PRETIME_OVER_8822B) + #define BIT_SHIFT_BF1_LIFETIME_8822B 0 #define BIT_MASK_BF1_LIFETIME_8822B 0xffff #define BIT_BF1_LIFETIME_8822B(x) (((x) & BIT_MASK_BF1_LIFETIME_8822B) << BIT_SHIFT_BF1_LIFETIME_8822B) #define BIT_GET_BF1_LIFETIME_8822B(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8822B) & BIT_MASK_BF1_LIFETIME_8822B) + /* 2 REG_BF_TIMEOUT_EN_8822B */ #define BIT_EN_VHT_LDPC_8822B BIT(9) #define BIT_EN_HT_LDPC_8822B BIT(8) @@ -6018,6 +6661,7 @@ #define BIT_GET_MACID31_0_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822B) & BIT_MASK_MACID31_0_RELEASE_8822B) + /* 2 REG_MACID_RELEASE1_8822B */ #define BIT_SHIFT_MACID63_32_RELEASE_8822B 0 @@ -6026,6 +6670,7 @@ #define BIT_GET_MACID63_32_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822B) & BIT_MASK_MACID63_32_RELEASE_8822B) + /* 2 REG_MACID_RELEASE2_8822B */ #define BIT_SHIFT_MACID95_64_RELEASE_8822B 0 @@ -6034,6 +6679,7 @@ #define BIT_GET_MACID95_64_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822B) & BIT_MASK_MACID95_64_RELEASE_8822B) + /* 2 REG_MACID_RELEASE3_8822B */ #define BIT_SHIFT_MACID127_96_RELEASE_8822B 0 @@ -6042,6 +6688,7 @@ #define BIT_GET_MACID127_96_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822B) & BIT_MASK_MACID127_96_RELEASE_8822B) + /* 2 REG_MACID_RELEASE_SETTING_8822B */ #define BIT_MACID_VALUE_8822B BIT(7) @@ -6051,6 +6698,7 @@ #define BIT_GET_MACID_OFFSET_8822B(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8822B) & BIT_MASK_MACID_OFFSET_8822B) + /* 2 REG_FAST_EDCA_VOVI_SETTING_8822B */ #define BIT_SHIFT_VI_FAST_EDCA_TO_8822B 24 @@ -6058,6 +6706,7 @@ #define BIT_VI_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8822B) << BIT_SHIFT_VI_FAST_EDCA_TO_8822B) #define BIT_GET_VI_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822B) & BIT_MASK_VI_FAST_EDCA_TO_8822B) + #define BIT_VI_THRESHOLD_SEL_8822B BIT(23) #define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B 16 @@ -6066,11 +6715,13 @@ #define BIT_GET_VI_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B) + #define BIT_SHIFT_VO_FAST_EDCA_TO_8822B 8 #define BIT_MASK_VO_FAST_EDCA_TO_8822B 0xff #define BIT_VO_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8822B) << BIT_SHIFT_VO_FAST_EDCA_TO_8822B) #define BIT_GET_VO_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822B) & BIT_MASK_VO_FAST_EDCA_TO_8822B) + #define BIT_VO_THRESHOLD_SEL_8822B BIT(7) #define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B 0 @@ -6079,6 +6730,7 @@ #define BIT_GET_VO_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B) + /* 2 REG_FAST_EDCA_BEBK_SETTING_8822B */ #define BIT_SHIFT_BK_FAST_EDCA_TO_8822B 24 @@ -6086,6 +6738,7 @@ #define BIT_BK_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8822B) << BIT_SHIFT_BK_FAST_EDCA_TO_8822B) #define BIT_GET_BK_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822B) & BIT_MASK_BK_FAST_EDCA_TO_8822B) + #define BIT_BK_THRESHOLD_SEL_8822B BIT(23) #define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B 16 @@ -6094,11 +6747,13 @@ #define BIT_GET_BK_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B) + #define BIT_SHIFT_BE_FAST_EDCA_TO_8822B 8 #define BIT_MASK_BE_FAST_EDCA_TO_8822B 0xff #define BIT_BE_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8822B) << BIT_SHIFT_BE_FAST_EDCA_TO_8822B) #define BIT_GET_BE_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822B) & BIT_MASK_BE_FAST_EDCA_TO_8822B) + #define BIT_BE_THRESHOLD_SEL_8822B BIT(7) #define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B 0 @@ -6107,6 +6762,7 @@ #define BIT_GET_BE_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B) + /* 2 REG_MACID_DROP0_8822B */ #define BIT_SHIFT_MACID31_0_DROP_8822B 0 @@ -6115,6 +6771,7 @@ #define BIT_GET_MACID31_0_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8822B) & BIT_MASK_MACID31_0_DROP_8822B) + /* 2 REG_MACID_DROP1_8822B */ #define BIT_SHIFT_MACID63_32_DROP_8822B 0 @@ -6123,6 +6780,7 @@ #define BIT_GET_MACID63_32_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8822B) & BIT_MASK_MACID63_32_DROP_8822B) + /* 2 REG_MACID_DROP2_8822B */ #define BIT_SHIFT_MACID95_64_DROP_8822B 0 @@ -6131,6 +6789,7 @@ #define BIT_GET_MACID95_64_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8822B) & BIT_MASK_MACID95_64_DROP_8822B) + /* 2 REG_MACID_DROP3_8822B */ #define BIT_SHIFT_MACID127_96_DROP_8822B 0 @@ -6139,6 +6798,7 @@ #define BIT_GET_MACID127_96_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8822B) & BIT_MASK_MACID127_96_DROP_8822B) + /* 2 REG_R_MACID_RELEASE_SUCCESS_0_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B 0 @@ -6147,6 +6807,7 @@ #define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B) + /* 2 REG_R_MACID_RELEASE_SUCCESS_1_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B 0 @@ -6155,6 +6816,7 @@ #define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B) + /* 2 REG_R_MACID_RELEASE_SUCCESS_2_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B 0 @@ -6163,6 +6825,7 @@ #define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B) + /* 2 REG_R_MACID_RELEASE_SUCCESS_3_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B 0 @@ -6171,6 +6834,7 @@ #define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B) + /* 2 REG_MGG_FIFO_CRTL_8822B */ #define BIT_R_MGG_FIFO_EN_8822B BIT(31) @@ -6180,17 +6844,20 @@ #define BIT_GET_R_MGG_FIFO_PG_SIZE_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B) + #define BIT_SHIFT_R_MGG_FIFO_START_PG_8822B 16 #define BIT_MASK_R_MGG_FIFO_START_PG_8822B 0xfff #define BIT_R_MGG_FIFO_START_PG_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8822B) << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) #define BIT_GET_R_MGG_FIFO_START_PG_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) & BIT_MASK_R_MGG_FIFO_START_PG_8822B) + #define BIT_SHIFT_R_MGG_FIFO_SIZE_8822B 14 #define BIT_MASK_R_MGG_FIFO_SIZE_8822B 0x3 #define BIT_R_MGG_FIFO_SIZE_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8822B) << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) #define BIT_GET_R_MGG_FIFO_SIZE_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) & BIT_MASK_R_MGG_FIFO_SIZE_8822B) + #define BIT_R_MGG_FIFO_PAUSE_8822B BIT(13) #define BIT_SHIFT_R_MGG_FIFO_RPTR_8822B 8 @@ -6198,6 +6865,7 @@ #define BIT_R_MGG_FIFO_RPTR_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8822B) << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) #define BIT_GET_R_MGG_FIFO_RPTR_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) & BIT_MASK_R_MGG_FIFO_RPTR_8822B) + #define BIT_R_MGG_FIFO_OV_8822B BIT(7) #define BIT_R_MGG_FIFO_WPTR_ERROR_8822B BIT(6) #define BIT_R_EN_CPU_LIFETIME_8822B BIT(5) @@ -6208,6 +6876,7 @@ #define BIT_GET_R_MGG_FIFO_WPTR_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) & BIT_MASK_R_MGG_FIFO_WPTR_8822B) + /* 2 REG_MGG_FIFO_INT_8822B */ #define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B 16 @@ -6216,12 +6885,14 @@ #define BIT_GET_R_MGG_FIFO_INT_FLAG_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B) + #define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B 0 #define BIT_MASK_R_MGG_FIFO_INT_MASK_8822B 0xffff #define BIT_R_MGG_FIFO_INT_MASK_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) #define BIT_GET_R_MGG_FIFO_INT_MASK_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) + /* 2 REG_MGG_FIFO_LIFETIME_8822B */ #define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B 16 @@ -6230,12 +6901,14 @@ #define BIT_GET_R_MGG_FIFO_LIFETIME_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B) + #define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B 0 #define BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B 0xffff #define BIT_R_MGG_FIFO_VALID_MAP_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) #define BIT_GET_R_MGG_FIFO_VALID_MAP_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) + /* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0 @@ -6244,6 +6917,7 @@ #define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) + /* 2 REG_MACID_SHCUT_OFFSET_8822B */ #define BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B 0 @@ -6252,6 +6926,7 @@ #define BIT_GET_MACID_SHCUT_OFFSET_V1_8822B(x) (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B) & BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B) + /* 2 REG_MU_TX_CTL_8822B */ #define BIT_R_EN_REVERS_GTAB_8822B BIT(6) @@ -6261,6 +6936,7 @@ #define BIT_GET_R_MU_TABLE_VALID_8822B(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) & BIT_MASK_R_MU_TABLE_VALID_8822B) + /* 2 REG_MU_STA_GID_VLD_8822B */ /* 2 REG_NOT_VALID_8822B */ @@ -6271,12 +6947,14 @@ #define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) + #define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0 #define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL #define BIT_R_MU_STA_GTAB_VALID_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) #define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) + /* 2 REG_MU_STA_USER_POS_INFO_8822B */ /* 2 REG_NOT_VALID_8822B */ @@ -6287,12 +6965,14 @@ #define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) + #define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0 #define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL #define BIT_R_MU_STA_GTAB_POSITION_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) #define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) + /* 2 REG_MU_TRX_DBG_CNT_8822B */ #define BIT_MU_DNGCNT_RST_8822B BIT(20) @@ -6302,12 +6982,14 @@ #define BIT_GET_MU_DBGCNT_SEL_8822B(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B) + #define BIT_SHIFT_MU_DNGCNT_8822B 0 #define BIT_MASK_MU_DNGCNT_8822B 0xffff #define BIT_MU_DNGCNT_8822B(x) (((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B) #define BIT_GET_MU_DNGCNT_8822B(x) (((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_EDCA_VO_PARAM_8822B */ @@ -6318,18 +7000,21 @@ #define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) + #define BIT_SHIFT_CW_8822B 8 #define BIT_MASK_CW_8822B 0xff #define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) #define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) + #define BIT_SHIFT_AIFS_8822B 0 #define BIT_MASK_AIFS_8822B 0xff #define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) #define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) + /* 2 REG_EDCA_VI_PARAM_8822B */ /* 2 REG_NOT_VALID_8822B */ @@ -6340,18 +7025,21 @@ #define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) + #define BIT_SHIFT_CW_8822B 8 #define BIT_MASK_CW_8822B 0xff #define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) #define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) + #define BIT_SHIFT_AIFS_8822B 0 #define BIT_MASK_AIFS_8822B 0xff #define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) #define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) + /* 2 REG_EDCA_BE_PARAM_8822B */ /* 2 REG_NOT_VALID_8822B */ @@ -6362,18 +7050,21 @@ #define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) + #define BIT_SHIFT_CW_8822B 8 #define BIT_MASK_CW_8822B 0xff #define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) #define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) + #define BIT_SHIFT_AIFS_8822B 0 #define BIT_MASK_AIFS_8822B 0xff #define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) #define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) + /* 2 REG_EDCA_BK_PARAM_8822B */ /* 2 REG_NOT_VALID_8822B */ @@ -6384,18 +7075,21 @@ #define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) + #define BIT_SHIFT_CW_8822B 8 #define BIT_MASK_CW_8822B 0xff #define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) #define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) + #define BIT_SHIFT_AIFS_8822B 0 #define BIT_MASK_AIFS_8822B 0xff #define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) #define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) + /* 2 REG_BCNTCFG_8822B */ #define BIT_SHIFT_BCNCW_MAX_8822B 12 @@ -6404,18 +7098,21 @@ #define BIT_GET_BCNCW_MAX_8822B(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8822B) & BIT_MASK_BCNCW_MAX_8822B) + #define BIT_SHIFT_BCNCW_MIN_8822B 8 #define BIT_MASK_BCNCW_MIN_8822B 0xf #define BIT_BCNCW_MIN_8822B(x) (((x) & BIT_MASK_BCNCW_MIN_8822B) << BIT_SHIFT_BCNCW_MIN_8822B) #define BIT_GET_BCNCW_MIN_8822B(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8822B) & BIT_MASK_BCNCW_MIN_8822B) + #define BIT_SHIFT_BCNIFS_8822B 0 #define BIT_MASK_BCNIFS_8822B 0xff #define BIT_BCNIFS_8822B(x) (((x) & BIT_MASK_BCNIFS_8822B) << BIT_SHIFT_BCNIFS_8822B) #define BIT_GET_BCNIFS_8822B(x) (((x) >> BIT_SHIFT_BCNIFS_8822B) & BIT_MASK_BCNIFS_8822B) + /* 2 REG_PIFS_8822B */ #define BIT_SHIFT_PIFS_8822B 0 @@ -6424,6 +7121,7 @@ #define BIT_GET_PIFS_8822B(x) (((x) >> BIT_SHIFT_PIFS_8822B) & BIT_MASK_PIFS_8822B) + /* 2 REG_RDG_PIFS_8822B */ #define BIT_SHIFT_RDG_PIFS_8822B 0 @@ -6432,6 +7130,7 @@ #define BIT_GET_RDG_PIFS_8822B(x) (((x) >> BIT_SHIFT_RDG_PIFS_8822B) & BIT_MASK_RDG_PIFS_8822B) + /* 2 REG_SIFS_8822B */ #define BIT_SHIFT_SIFS_OFDM_TRX_8822B 24 @@ -6440,24 +7139,28 @@ #define BIT_GET_SIFS_OFDM_TRX_8822B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822B) & BIT_MASK_SIFS_OFDM_TRX_8822B) + #define BIT_SHIFT_SIFS_CCK_TRX_8822B 16 #define BIT_MASK_SIFS_CCK_TRX_8822B 0xff #define BIT_SIFS_CCK_TRX_8822B(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8822B) << BIT_SHIFT_SIFS_CCK_TRX_8822B) #define BIT_GET_SIFS_CCK_TRX_8822B(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822B) & BIT_MASK_SIFS_CCK_TRX_8822B) + #define BIT_SHIFT_SIFS_OFDM_CTX_8822B 8 #define BIT_MASK_SIFS_OFDM_CTX_8822B 0xff #define BIT_SIFS_OFDM_CTX_8822B(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8822B) << BIT_SHIFT_SIFS_OFDM_CTX_8822B) #define BIT_GET_SIFS_OFDM_CTX_8822B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822B) & BIT_MASK_SIFS_OFDM_CTX_8822B) + #define BIT_SHIFT_SIFS_CCK_CTX_8822B 0 #define BIT_MASK_SIFS_CCK_CTX_8822B 0xff #define BIT_SIFS_CCK_CTX_8822B(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8822B) << BIT_SHIFT_SIFS_CCK_CTX_8822B) #define BIT_GET_SIFS_CCK_CTX_8822B(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822B) & BIT_MASK_SIFS_CCK_CTX_8822B) + /* 2 REG_TSFTR_SYN_OFFSET_8822B */ #define BIT_SHIFT_TSFTR_SNC_OFFSET_8822B 0 @@ -6466,6 +7169,7 @@ #define BIT_GET_TSFTR_SNC_OFFSET_8822B(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) & BIT_MASK_TSFTR_SNC_OFFSET_8822B) + /* 2 REG_AGGR_BREAK_TIME_8822B */ #define BIT_SHIFT_AGGR_BK_TIME_8822B 0 @@ -6474,6 +7178,7 @@ #define BIT_GET_AGGR_BK_TIME_8822B(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8822B) & BIT_MASK_AGGR_BK_TIME_8822B) + /* 2 REG_SLOT_8822B */ #define BIT_SHIFT_SLOT_8822B 0 @@ -6482,6 +7187,7 @@ #define BIT_GET_SLOT_8822B(x) (((x) >> BIT_SHIFT_SLOT_8822B) & BIT_MASK_SLOT_8822B) + /* 2 REG_TX_PTCL_CTRL_8822B */ #define BIT_DIS_EDCCA_8822B BIT(15) #define BIT_DIS_CCA_8822B BIT(14) @@ -6493,6 +7199,7 @@ #define BIT_TXQ_NAV_MSK_8822B(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8822B) << BIT_SHIFT_TXQ_NAV_MSK_8822B) #define BIT_GET_TXQ_NAV_MSK_8822B(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822B) & BIT_MASK_TXQ_NAV_MSK_8822B) + #define BIT_DIS_CW_8822B BIT(7) #define BIT_NAV_END_TXOP_8822B BIT(6) #define BIT_RDG_END_TXOP_8822B BIT(5) @@ -6571,12 +7278,14 @@ #define BIT_GET_CCA_FILTER_THRS_8822B(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822B) & BIT_MASK_CCA_FILTER_THRS_8822B) + #define BIT_SHIFT_EDCCA_THRS_8822B 0 #define BIT_MASK_EDCCA_THRS_8822B 0xff #define BIT_EDCCA_THRS_8822B(x) (((x) & BIT_MASK_EDCCA_THRS_8822B) << BIT_SHIFT_EDCCA_THRS_8822B) #define BIT_GET_EDCCA_THRS_8822B(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8822B) & BIT_MASK_EDCCA_THRS_8822B) + /* 2 REG_P2PPS_SPEC_STATE_8822B */ #define BIT_SPEC_POWER_STATE_8822B BIT(7) #define BIT_SPEC_CTWINDOW_ON_8822B BIT(6) @@ -6597,6 +7306,7 @@ #define BIT_GET_P2PON_DIS_TXTIME_8822B(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822B) & BIT_MASK_P2PON_DIS_TXTIME_8822B) + /* 2 REG_QUEUE_INCOL_THR_8822B */ #define BIT_SHIFT_BK_QUEUE_THR_8822B 24 @@ -6605,24 +7315,28 @@ #define BIT_GET_BK_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_BK_QUEUE_THR_8822B) & BIT_MASK_BK_QUEUE_THR_8822B) + #define BIT_SHIFT_BE_QUEUE_THR_8822B 16 #define BIT_MASK_BE_QUEUE_THR_8822B 0xff #define BIT_BE_QUEUE_THR_8822B(x) (((x) & BIT_MASK_BE_QUEUE_THR_8822B) << BIT_SHIFT_BE_QUEUE_THR_8822B) #define BIT_GET_BE_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_BE_QUEUE_THR_8822B) & BIT_MASK_BE_QUEUE_THR_8822B) + #define BIT_SHIFT_VI_QUEUE_THR_8822B 8 #define BIT_MASK_VI_QUEUE_THR_8822B 0xff #define BIT_VI_QUEUE_THR_8822B(x) (((x) & BIT_MASK_VI_QUEUE_THR_8822B) << BIT_SHIFT_VI_QUEUE_THR_8822B) #define BIT_GET_VI_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_VI_QUEUE_THR_8822B) & BIT_MASK_VI_QUEUE_THR_8822B) + #define BIT_SHIFT_VO_QUEUE_THR_8822B 0 #define BIT_MASK_VO_QUEUE_THR_8822B 0xff #define BIT_VO_QUEUE_THR_8822B(x) (((x) & BIT_MASK_VO_QUEUE_THR_8822B) << BIT_SHIFT_VO_QUEUE_THR_8822B) #define BIT_GET_VO_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_VO_QUEUE_THR_8822B) & BIT_MASK_VO_QUEUE_THR_8822B) + /* 2 REG_QUEUE_INCOL_EN_8822B */ #define BIT_QUEUE_INCOL_EN_8822B BIT(16) @@ -6632,24 +7346,28 @@ #define BIT_GET_BE_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_8822B) & BIT_MASK_BE_TRIGGER_NUM_8822B) + #define BIT_SHIFT_BK_TRIGGER_NUM_8822B 8 #define BIT_MASK_BK_TRIGGER_NUM_8822B 0xf #define BIT_BK_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_BK_TRIGGER_NUM_8822B) << BIT_SHIFT_BK_TRIGGER_NUM_8822B) #define BIT_GET_BK_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_8822B) & BIT_MASK_BK_TRIGGER_NUM_8822B) + #define BIT_SHIFT_VI_TRIGGER_NUM_8822B 4 #define BIT_MASK_VI_TRIGGER_NUM_8822B 0xf #define BIT_VI_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_VI_TRIGGER_NUM_8822B) << BIT_SHIFT_VI_TRIGGER_NUM_8822B) #define BIT_GET_VI_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8822B) & BIT_MASK_VI_TRIGGER_NUM_8822B) + #define BIT_SHIFT_VO_TRIGGER_NUM_8822B 0 #define BIT_MASK_VO_TRIGGER_NUM_8822B 0xf #define BIT_VO_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_VO_TRIGGER_NUM_8822B) << BIT_SHIFT_VO_TRIGGER_NUM_8822B) #define BIT_GET_VO_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8822B) & BIT_MASK_VO_TRIGGER_NUM_8822B) + /* 2 REG_TBTT_PROHIBIT_8822B */ #define BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B 8 @@ -6658,12 +7376,14 @@ #define BIT_GET_TBTT_HOLD_TIME_AP_8822B(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B) + #define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B 0 #define BIT_MASK_TBTT_PROHIBIT_SETUP_8822B 0xf #define BIT_TBTT_PROHIBIT_SETUP_8822B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) #define BIT_GET_TBTT_PROHIBIT_SETUP_8822B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) + /* 2 REG_P2PPS_STATE_8822B */ #define BIT_POWER_STATE_8822B BIT(7) #define BIT_CTWINDOW_ON_8822B BIT(6) @@ -6682,6 +7402,7 @@ #define BIT_GET_RD_NAV_PROT_NXT_8822B(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822B) & BIT_MASK_RD_NAV_PROT_NXT_8822B) + /* 2 REG_NAV_PROT_LEN_8822B */ #define BIT_SHIFT_NAV_PROT_LEN_8822B 0 @@ -6690,6 +7411,7 @@ #define BIT_GET_NAV_PROT_LEN_8822B(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8822B) & BIT_MASK_NAV_PROT_LEN_8822B) + /* 2 REG_BCN_CTRL_8822B */ #define BIT_DIS_RX_BSSID_FIT_8822B BIT(6) #define BIT_P0_EN_TXBCN_RPT_8822B BIT(5) @@ -6716,6 +7438,7 @@ #define BIT_GET_MBID_BCN_NUM_8822B(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8822B) & BIT_MASK_MBID_BCN_NUM_8822B) + /* 2 REG_DUAL_TSF_RST_8822B */ #define BIT_FREECNT_RST_8822B BIT(5) #define BIT_TSFTR_CLI3_RST_8822B BIT(4) @@ -6732,18 +7455,21 @@ #define BIT_GET_BCN_TIMER_SEL_FWRD_8822B(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B) + #define BIT_SHIFT_BCN_SPACE_CLINT0_8822B 16 #define BIT_MASK_BCN_SPACE_CLINT0_8822B 0xfff #define BIT_BCN_SPACE_CLINT0_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8822B) << BIT_SHIFT_BCN_SPACE_CLINT0_8822B) #define BIT_GET_BCN_SPACE_CLINT0_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822B) & BIT_MASK_BCN_SPACE_CLINT0_8822B) + #define BIT_SHIFT_BCN_SPACE0_8822B 0 #define BIT_MASK_BCN_SPACE0_8822B 0xffff #define BIT_BCN_SPACE0_8822B(x) (((x) & BIT_MASK_BCN_SPACE0_8822B) << BIT_SHIFT_BCN_SPACE0_8822B) #define BIT_GET_BCN_SPACE0_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8822B) & BIT_MASK_BCN_SPACE0_8822B) + /* 2 REG_DRVERLYINT_8822B */ #define BIT_SHIFT_DRVERLYITV_8822B 0 @@ -6752,6 +7478,7 @@ #define BIT_GET_DRVERLYITV_8822B(x) (((x) >> BIT_SHIFT_DRVERLYITV_8822B) & BIT_MASK_DRVERLYITV_8822B) + /* 2 REG_BCNDMATIM_8822B */ #define BIT_SHIFT_BCNDMATIM_8822B 0 @@ -6760,6 +7487,7 @@ #define BIT_GET_BCNDMATIM_8822B(x) (((x) >> BIT_SHIFT_BCNDMATIM_8822B) & BIT_MASK_BCNDMATIM_8822B) + /* 2 REG_ATIMWND_8822B */ #define BIT_SHIFT_ATIMWND0_8822B 0 @@ -6768,6 +7496,7 @@ #define BIT_GET_ATIMWND0_8822B(x) (((x) >> BIT_SHIFT_ATIMWND0_8822B) & BIT_MASK_ATIMWND0_8822B) + /* 2 REG_USTIME_TSF_8822B */ #define BIT_SHIFT_USTIME_TSF_V1_8822B 0 @@ -6776,6 +7505,7 @@ #define BIT_GET_USTIME_TSF_V1_8822B(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8822B) & BIT_MASK_USTIME_TSF_V1_8822B) + /* 2 REG_BCN_MAX_ERR_8822B */ #define BIT_SHIFT_BCN_MAX_ERR_8822B 0 @@ -6784,6 +7514,7 @@ #define BIT_GET_BCN_MAX_ERR_8822B(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8822B) & BIT_MASK_BCN_MAX_ERR_8822B) + /* 2 REG_RXTSF_OFFSET_CCK_8822B */ #define BIT_SHIFT_CCK_RXTSF_OFFSET_8822B 0 @@ -6792,6 +7523,7 @@ #define BIT_GET_CCK_RXTSF_OFFSET_8822B(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) & BIT_MASK_CCK_RXTSF_OFFSET_8822B) + /* 2 REG_RXTSF_OFFSET_OFDM_8822B */ #define BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B 0 @@ -6800,6 +7532,7 @@ #define BIT_GET_OFDM_RXTSF_OFFSET_8822B(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B) + /* 2 REG_TSFTR_8822B */ #define BIT_SHIFT_TSF_TIMER_8822B 0 @@ -6808,6 +7541,7 @@ #define BIT_GET_TSF_TIMER_8822B(x) (((x) >> BIT_SHIFT_TSF_TIMER_8822B) & BIT_MASK_TSF_TIMER_8822B) + /* 2 REG_FREERUN_CNT_8822B */ #define BIT_SHIFT_FREERUN_CNT_8822B 0 @@ -6816,6 +7550,7 @@ #define BIT_GET_FREERUN_CNT_8822B(x) (((x) >> BIT_SHIFT_FREERUN_CNT_8822B) & BIT_MASK_FREERUN_CNT_8822B) + /* 2 REG_ATIMWND1_V1_8822B */ #define BIT_SHIFT_ATIMWND1_V1_8822B 0 @@ -6824,6 +7559,7 @@ #define BIT_GET_ATIMWND1_V1_8822B(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8822B) & BIT_MASK_ATIMWND1_V1_8822B) + /* 2 REG_TBTT_PROHIBIT_INFRA_8822B */ #define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B 0 @@ -6832,6 +7568,7 @@ #define BIT_GET_TBTT_PROHIBIT_INFRA_8822B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B) + /* 2 REG_CTWND_8822B */ #define BIT_SHIFT_CTWND_8822B 0 @@ -6840,6 +7577,7 @@ #define BIT_GET_CTWND_8822B(x) (((x) >> BIT_SHIFT_CTWND_8822B) & BIT_MASK_CTWND_8822B) + /* 2 REG_BCNIVLCUNT_8822B */ #define BIT_SHIFT_BCNIVLCUNT_8822B 0 @@ -6848,6 +7586,7 @@ #define BIT_GET_BCNIVLCUNT_8822B(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8822B) & BIT_MASK_BCNIVLCUNT_8822B) + /* 2 REG_BCNDROPCTRL_8822B */ #define BIT_BEACON_DROP_EN_8822B BIT(7) @@ -6857,6 +7596,7 @@ #define BIT_GET_BEACON_DROP_IVL_8822B(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822B) & BIT_MASK_BEACON_DROP_IVL_8822B) + /* 2 REG_HGQ_TIMEOUT_PERIOD_8822B */ #define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B 0 @@ -6865,6 +7605,7 @@ #define BIT_GET_HGQ_TIMEOUT_PERIOD_8822B(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B) + /* 2 REG_TXCMD_TIMEOUT_PERIOD_8822B */ #define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B 0 @@ -6873,6 +7614,7 @@ #define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822B(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B) + /* 2 REG_MISC_CTRL_8822B */ #define BIT_DIS_TRX_CAL_BCN_8822B BIT(5) #define BIT_DIS_TX_CAL_TBTT_8822B BIT(4) @@ -6885,6 +7627,7 @@ #define BIT_GET_DIS_SECONDARY_CCA_8822B(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822B) & BIT_MASK_DIS_SECONDARY_CCA_8822B) + /* 2 REG_BCN_CTRL_CLINT1_8822B */ #define BIT_CLI1_DIS_RX_BSSID_FIT_8822B BIT(6) #define BIT_CLI1_DIS_TSF_UDT_8822B BIT(4) @@ -6919,6 +7662,7 @@ #define BIT_GET_PORT_SEL_8822B(x) (((x) >> BIT_SHIFT_PORT_SEL_8822B) & BIT_MASK_PORT_SEL_8822B) + /* 2 REG_P2PPS1_SPEC_STATE_8822B */ #define BIT_P2P1_SPEC_POWER_STATE_8822B BIT(7) #define BIT_P2P1_SPEC_CTWINDOW_ON_8822B BIT(6) @@ -6967,6 +7711,7 @@ #define BIT_GET_PSTIMER0_INT_8822B(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8822B) & BIT_MASK_PSTIMER0_INT_8822B) + /* 2 REG_PS_TIMER1_8822B */ #define BIT_SHIFT_PSTIMER1_INT_8822B 5 @@ -6975,6 +7720,7 @@ #define BIT_GET_PSTIMER1_INT_8822B(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8822B) & BIT_MASK_PSTIMER1_INT_8822B) + /* 2 REG_PS_TIMER2_8822B */ #define BIT_SHIFT_PSTIMER2_INT_8822B 5 @@ -6983,6 +7729,7 @@ #define BIT_GET_PSTIMER2_INT_8822B(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8822B) & BIT_MASK_PSTIMER2_INT_8822B) + /* 2 REG_TBTT_CTN_AREA_8822B */ #define BIT_SHIFT_TBTT_CTN_AREA_8822B 0 @@ -6991,6 +7738,7 @@ #define BIT_GET_TBTT_CTN_AREA_8822B(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822B) & BIT_MASK_TBTT_CTN_AREA_8822B) + /* 2 REG_FORCE_BCN_IFS_8822B */ #define BIT_SHIFT_FORCE_BCN_IFS_8822B 0 @@ -6999,6 +7747,7 @@ #define BIT_GET_FORCE_BCN_IFS_8822B(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822B) & BIT_MASK_FORCE_BCN_IFS_8822B) + /* 2 REG_TXOP_MIN_8822B */ #define BIT_SHIFT_TXOP_MIN_8822B 0 @@ -7007,6 +7756,7 @@ #define BIT_GET_TXOP_MIN_8822B(x) (((x) >> BIT_SHIFT_TXOP_MIN_8822B) & BIT_MASK_TXOP_MIN_8822B) + /* 2 REG_PRE_BKF_TIME_8822B */ #define BIT_SHIFT_PRE_BKF_TIME_8822B 0 @@ -7015,6 +7765,7 @@ #define BIT_GET_PRE_BKF_TIME_8822B(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8822B) & BIT_MASK_PRE_BKF_TIME_8822B) + /* 2 REG_CROSS_TXOP_CTRL_8822B */ #define BIT_DTIM_BYPASS_8822B BIT(2) #define BIT_RTS_NAV_TXOP_8822B BIT(1) @@ -7028,6 +7779,7 @@ #define BIT_GET_ATIMWND2_8822B(x) (((x) >> BIT_SHIFT_ATIMWND2_8822B) & BIT_MASK_ATIMWND2_8822B) + /* 2 REG_ATIMWND3_8822B */ #define BIT_SHIFT_ATIMWND3_8822B 0 @@ -7036,6 +7788,7 @@ #define BIT_GET_ATIMWND3_8822B(x) (((x) >> BIT_SHIFT_ATIMWND3_8822B) & BIT_MASK_ATIMWND3_8822B) + /* 2 REG_ATIMWND4_8822B */ #define BIT_SHIFT_ATIMWND4_8822B 0 @@ -7044,6 +7797,7 @@ #define BIT_GET_ATIMWND4_8822B(x) (((x) >> BIT_SHIFT_ATIMWND4_8822B) & BIT_MASK_ATIMWND4_8822B) + /* 2 REG_ATIMWND5_8822B */ #define BIT_SHIFT_ATIMWND5_8822B 0 @@ -7052,6 +7806,7 @@ #define BIT_GET_ATIMWND5_8822B(x) (((x) >> BIT_SHIFT_ATIMWND5_8822B) & BIT_MASK_ATIMWND5_8822B) + /* 2 REG_ATIMWND6_8822B */ #define BIT_SHIFT_ATIMWND6_8822B 0 @@ -7060,6 +7815,7 @@ #define BIT_GET_ATIMWND6_8822B(x) (((x) >> BIT_SHIFT_ATIMWND6_8822B) & BIT_MASK_ATIMWND6_8822B) + /* 2 REG_ATIMWND7_8822B */ #define BIT_SHIFT_ATIMWND7_8822B 0 @@ -7068,6 +7824,7 @@ #define BIT_GET_ATIMWND7_8822B(x) (((x) >> BIT_SHIFT_ATIMWND7_8822B) & BIT_MASK_ATIMWND7_8822B) + /* 2 REG_ATIMUGT_8822B */ #define BIT_SHIFT_ATIM_URGENT_8822B 0 @@ -7076,6 +7833,7 @@ #define BIT_GET_ATIM_URGENT_8822B(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8822B) & BIT_MASK_ATIM_URGENT_8822B) + /* 2 REG_HIQ_NO_LMT_EN_8822B */ #define BIT_HIQ_NO_LMT_EN_VAP7_8822B BIT(7) #define BIT_HIQ_NO_LMT_EN_VAP6_8822B BIT(6) @@ -7094,6 +7852,7 @@ #define BIT_GET_DTIM_COUNT_ROOT_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822B) & BIT_MASK_DTIM_COUNT_ROOT_8822B) + /* 2 REG_DTIM_COUNTER_VAP1_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP1_8822B 0 @@ -7102,6 +7861,7 @@ #define BIT_GET_DTIM_COUNT_VAP1_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822B) & BIT_MASK_DTIM_COUNT_VAP1_8822B) + /* 2 REG_DTIM_COUNTER_VAP2_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP2_8822B 0 @@ -7110,6 +7870,7 @@ #define BIT_GET_DTIM_COUNT_VAP2_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822B) & BIT_MASK_DTIM_COUNT_VAP2_8822B) + /* 2 REG_DTIM_COUNTER_VAP3_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP3_8822B 0 @@ -7118,6 +7879,7 @@ #define BIT_GET_DTIM_COUNT_VAP3_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822B) & BIT_MASK_DTIM_COUNT_VAP3_8822B) + /* 2 REG_DTIM_COUNTER_VAP4_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP4_8822B 0 @@ -7126,6 +7888,7 @@ #define BIT_GET_DTIM_COUNT_VAP4_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822B) & BIT_MASK_DTIM_COUNT_VAP4_8822B) + /* 2 REG_DTIM_COUNTER_VAP5_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP5_8822B 0 @@ -7134,6 +7897,7 @@ #define BIT_GET_DTIM_COUNT_VAP5_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822B) & BIT_MASK_DTIM_COUNT_VAP5_8822B) + /* 2 REG_DTIM_COUNTER_VAP6_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP6_8822B 0 @@ -7142,6 +7906,7 @@ #define BIT_GET_DTIM_COUNT_VAP6_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822B) & BIT_MASK_DTIM_COUNT_VAP6_8822B) + /* 2 REG_DTIM_COUNTER_VAP7_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP7_8822B 0 @@ -7150,6 +7915,7 @@ #define BIT_GET_DTIM_COUNT_VAP7_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822B) & BIT_MASK_DTIM_COUNT_VAP7_8822B) + /* 2 REG_DIS_ATIM_8822B */ #define BIT_DIS_ATIM_VAP7_8822B BIT(7) #define BIT_DIS_ATIM_VAP6_8822B BIT(6) @@ -7168,12 +7934,14 @@ #define BIT_GET_TSFT_SEL_TIMER1_8822B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822B) & BIT_MASK_TSFT_SEL_TIMER1_8822B) + #define BIT_SHIFT_EARLY_128US_8822B 0 #define BIT_MASK_EARLY_128US_8822B 0x7 #define BIT_EARLY_128US_8822B(x) (((x) & BIT_MASK_EARLY_128US_8822B) << BIT_SHIFT_EARLY_128US_8822B) #define BIT_GET_EARLY_128US_8822B(x) (((x) >> BIT_SHIFT_EARLY_128US_8822B) & BIT_MASK_EARLY_128US_8822B) + /* 2 REG_P2PPS1_CTRL_8822B */ #define BIT_P2P1_CTW_ALLSTASLEEP_8822B BIT(7) #define BIT_P2P1_OFF_DISTX_EN_8822B BIT(6) @@ -7196,12 +7964,14 @@ #define BIT_GET_SYNC_CLI_SEL_8822B(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822B) & BIT_MASK_SYNC_CLI_SEL_8822B) + #define BIT_SHIFT_TSFT_SEL_TIMER0_8822B 0 #define BIT_MASK_TSFT_SEL_TIMER0_8822B 0x7 #define BIT_TSFT_SEL_TIMER0_8822B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8822B) << BIT_SHIFT_TSFT_SEL_TIMER0_8822B) #define BIT_GET_TSFT_SEL_TIMER0_8822B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822B) & BIT_MASK_TSFT_SEL_TIMER0_8822B) + /* 2 REG_NOA_UNIT_SEL_8822B */ #define BIT_SHIFT_NOA_UNIT2_SEL_8822B 8 @@ -7210,18 +7980,21 @@ #define BIT_GET_NOA_UNIT2_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822B) & BIT_MASK_NOA_UNIT2_SEL_8822B) + #define BIT_SHIFT_NOA_UNIT1_SEL_8822B 4 #define BIT_MASK_NOA_UNIT1_SEL_8822B 0x7 #define BIT_NOA_UNIT1_SEL_8822B(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8822B) << BIT_SHIFT_NOA_UNIT1_SEL_8822B) #define BIT_GET_NOA_UNIT1_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822B) & BIT_MASK_NOA_UNIT1_SEL_8822B) + #define BIT_SHIFT_NOA_UNIT0_SEL_8822B 0 #define BIT_MASK_NOA_UNIT0_SEL_8822B 0x7 #define BIT_NOA_UNIT0_SEL_8822B(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8822B) << BIT_SHIFT_NOA_UNIT0_SEL_8822B) #define BIT_GET_NOA_UNIT0_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822B) & BIT_MASK_NOA_UNIT0_SEL_8822B) + /* 2 REG_P2POFF_DIS_TXTIME_8822B */ #define BIT_SHIFT_P2POFF_DIS_TXTIME_8822B 0 @@ -7230,6 +8003,7 @@ #define BIT_GET_P2POFF_DIS_TXTIME_8822B(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) & BIT_MASK_P2POFF_DIS_TXTIME_8822B) + /* 2 REG_MBSSID_BCN_SPACE2_8822B */ #define BIT_SHIFT_BCN_SPACE_CLINT2_8822B 16 @@ -7238,12 +8012,14 @@ #define BIT_GET_BCN_SPACE_CLINT2_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822B) & BIT_MASK_BCN_SPACE_CLINT2_8822B) + #define BIT_SHIFT_BCN_SPACE_CLINT1_8822B 0 #define BIT_MASK_BCN_SPACE_CLINT1_8822B 0xfff #define BIT_BCN_SPACE_CLINT1_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8822B) << BIT_SHIFT_BCN_SPACE_CLINT1_8822B) #define BIT_GET_BCN_SPACE_CLINT1_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822B) & BIT_MASK_BCN_SPACE_CLINT1_8822B) + /* 2 REG_MBSSID_BCN_SPACE3_8822B */ #define BIT_SHIFT_SUB_BCN_SPACE_8822B 16 @@ -7252,12 +8028,14 @@ #define BIT_GET_SUB_BCN_SPACE_8822B(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822B) & BIT_MASK_SUB_BCN_SPACE_8822B) + #define BIT_SHIFT_BCN_SPACE_CLINT3_8822B 0 #define BIT_MASK_BCN_SPACE_CLINT3_8822B 0xfff #define BIT_BCN_SPACE_CLINT3_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8822B) << BIT_SHIFT_BCN_SPACE_CLINT3_8822B) #define BIT_GET_BCN_SPACE_CLINT3_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822B) & BIT_MASK_BCN_SPACE_CLINT3_8822B) + /* 2 REG_ACMHWCTRL_8822B */ #define BIT_BEQ_ACM_STATUS_8822B BIT(7) #define BIT_VIQ_ACM_STATUS_8822B BIT(6) @@ -7280,6 +8058,7 @@ #define BIT_GET_AVGPERIOD_8822B(x) (((x) >> BIT_SHIFT_AVGPERIOD_8822B) & BIT_MASK_AVGPERIOD_8822B) + /* 2 REG_VO_ADMTIME_8822B */ #define BIT_SHIFT_VO_ADMITTED_TIME_8822B 0 @@ -7288,6 +8067,7 @@ #define BIT_GET_VO_ADMITTED_TIME_8822B(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822B) & BIT_MASK_VO_ADMITTED_TIME_8822B) + /* 2 REG_VI_ADMTIME_8822B */ #define BIT_SHIFT_VI_ADMITTED_TIME_8822B 0 @@ -7296,6 +8076,7 @@ #define BIT_GET_VI_ADMITTED_TIME_8822B(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822B) & BIT_MASK_VI_ADMITTED_TIME_8822B) + /* 2 REG_BE_ADMTIME_8822B */ #define BIT_SHIFT_BE_ADMITTED_TIME_8822B 0 @@ -7304,6 +8085,7 @@ #define BIT_GET_BE_ADMITTED_TIME_8822B(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822B) & BIT_MASK_BE_ADMITTED_TIME_8822B) + /* 2 REG_EDCA_RANDOM_GEN_8822B */ #define BIT_SHIFT_RANDOM_GEN_8822B 0 @@ -7312,6 +8094,7 @@ #define BIT_GET_RANDOM_GEN_8822B(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8822B) & BIT_MASK_RANDOM_GEN_8822B) + /* 2 REG_TXCMD_NOA_SEL_8822B */ #define BIT_SHIFT_NOA_SEL_8822B 4 @@ -7320,12 +8103,14 @@ #define BIT_GET_NOA_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_SEL_8822B) & BIT_MASK_NOA_SEL_8822B) + #define BIT_SHIFT_TXCMD_SEG_SEL_8822B 0 #define BIT_MASK_TXCMD_SEG_SEL_8822B 0xf #define BIT_TXCMD_SEG_SEL_8822B(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8822B) << BIT_SHIFT_TXCMD_SEG_SEL_8822B) #define BIT_GET_TXCMD_SEG_SEL_8822B(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822B) & BIT_MASK_TXCMD_SEG_SEL_8822B) + /* 2 REG_NOA_PARAM_8822B */ #define BIT_SHIFT_NOA_COUNT_8822B (96 & CPU_OPT_WIDTH) @@ -7334,24 +8119,28 @@ #define BIT_GET_NOA_COUNT_8822B(x) (((x) >> BIT_SHIFT_NOA_COUNT_8822B) & BIT_MASK_NOA_COUNT_8822B) + #define BIT_SHIFT_NOA_START_TIME_8822B (64 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_START_TIME_8822B 0xffffffffL #define BIT_NOA_START_TIME_8822B(x) (((x) & BIT_MASK_NOA_START_TIME_8822B) << BIT_SHIFT_NOA_START_TIME_8822B) #define BIT_GET_NOA_START_TIME_8822B(x) (((x) >> BIT_SHIFT_NOA_START_TIME_8822B) & BIT_MASK_NOA_START_TIME_8822B) + #define BIT_SHIFT_NOA_INTERVAL_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_INTERVAL_8822B 0xffffffffL #define BIT_NOA_INTERVAL_8822B(x) (((x) & BIT_MASK_NOA_INTERVAL_8822B) << BIT_SHIFT_NOA_INTERVAL_8822B) #define BIT_GET_NOA_INTERVAL_8822B(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_8822B) & BIT_MASK_NOA_INTERVAL_8822B) + #define BIT_SHIFT_NOA_DURATION_8822B 0 #define BIT_MASK_NOA_DURATION_8822B 0xffffffffL #define BIT_NOA_DURATION_8822B(x) (((x) & BIT_MASK_NOA_DURATION_8822B) << BIT_SHIFT_NOA_DURATION_8822B) #define BIT_GET_NOA_DURATION_8822B(x) (((x) >> BIT_SHIFT_NOA_DURATION_8822B) & BIT_MASK_NOA_DURATION_8822B) + /* 2 REG_P2P_RST_8822B */ #define BIT_P2P2_PWR_RST1_8822B BIT(5) #define BIT_P2P2_PWR_RST0_8822B BIT(4) @@ -7372,6 +8161,7 @@ #define BIT_GET_SCH_TXCMD_8822B(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8822B) & BIT_MASK_SCH_TXCMD_8822B) + /* 2 REG_PAGE5_DUMMY_8822B */ /* 2 REG_CPUMGQ_TX_TIMER_8822B */ @@ -7382,6 +8172,7 @@ #define BIT_GET_CPUMGQ_TX_TIMER_V1_8822B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B) + /* 2 REG_PS_TIMER_A_8822B */ #define BIT_SHIFT_PS_TIMER_A_V1_8822B 0 @@ -7390,6 +8181,7 @@ #define BIT_GET_PS_TIMER_A_V1_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822B) & BIT_MASK_PS_TIMER_A_V1_8822B) + /* 2 REG_PS_TIMER_B_8822B */ #define BIT_SHIFT_PS_TIMER_B_V1_8822B 0 @@ -7398,6 +8190,7 @@ #define BIT_GET_PS_TIMER_B_V1_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822B) & BIT_MASK_PS_TIMER_B_V1_8822B) + /* 2 REG_PS_TIMER_C_8822B */ #define BIT_SHIFT_PS_TIMER_C_V1_8822B 0 @@ -7406,6 +8199,7 @@ #define BIT_GET_PS_TIMER_C_V1_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822B) & BIT_MASK_PS_TIMER_C_V1_8822B) + /* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B */ #define BIT_CPUMGQ_TIMER_EN_8822B BIT(31) #define BIT_CPUMGQ_TX_EN_8822B BIT(28) @@ -7415,6 +8209,7 @@ #define BIT_CPUMGQ_TIMER_TSF_SEL_8822B(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) #define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) + #define BIT_PS_TIMER_C_EN_8822B BIT(23) #define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B 16 @@ -7422,6 +8217,7 @@ #define BIT_PS_TIMER_C_TSF_SEL_8822B(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) #define BIT_GET_PS_TIMER_C_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) + #define BIT_PS_TIMER_B_EN_8822B BIT(15) #define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B 8 @@ -7429,6 +8225,7 @@ #define BIT_PS_TIMER_B_TSF_SEL_8822B(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) #define BIT_GET_PS_TIMER_B_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) + #define BIT_PS_TIMER_A_EN_8822B BIT(7) #define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B 0 @@ -7437,6 +8234,7 @@ #define BIT_GET_PS_TIMER_A_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B) + /* 2 REG_CPUMGQ_TX_TIMER_EARLY_8822B */ #define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B 0 @@ -7445,6 +8243,7 @@ #define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B) + /* 2 REG_PS_TIMER_A_EARLY_8822B */ #define BIT_SHIFT_PS_TIMER_A_EARLY_8822B 0 @@ -7453,6 +8252,7 @@ #define BIT_GET_PS_TIMER_A_EARLY_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822B) & BIT_MASK_PS_TIMER_A_EARLY_8822B) + /* 2 REG_PS_TIMER_B_EARLY_8822B */ #define BIT_SHIFT_PS_TIMER_B_EARLY_8822B 0 @@ -7461,6 +8261,7 @@ #define BIT_GET_PS_TIMER_B_EARLY_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822B) & BIT_MASK_PS_TIMER_B_EARLY_8822B) + /* 2 REG_PS_TIMER_C_EARLY_8822B */ #define BIT_SHIFT_PS_TIMER_C_EARLY_8822B 0 @@ -7469,6 +8270,7 @@ #define BIT_GET_PS_TIMER_C_EARLY_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822B) & BIT_MASK_PS_TIMER_C_EARLY_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_BWOPMODE_8822B (BW OPERATION MODE REGISTER) */ @@ -7485,6 +8287,7 @@ #define BIT_GET_APPEND_MHDR_LEN_8822B(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822B) & BIT_MASK_APPEND_MHDR_LEN_8822B) + /* 2 REG_WMAC_CR_8822B (WMAC CR AND APSD CONTROL REGISTER) */ #define BIT_IC_MACPHY_M_8822B BIT(0) @@ -7560,6 +8363,7 @@ #define BIT_GET_DRVINFO_SZ_V1_8822B(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822B) & BIT_MASK_DRVINFO_SZ_V1_8822B) + /* 2 REG_RX_DLK_TIME_8822B (RX DEADLOCK TIME REGISTER) */ #define BIT_SHIFT_RX_DLK_TIME_8822B 0 @@ -7568,6 +8372,7 @@ #define BIT_GET_RX_DLK_TIME_8822B(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8822B) & BIT_MASK_RX_DLK_TIME_8822B) + /* 2 REG_RX_PKT_LIMIT_8822B (RX PACKET LENGTH LIMIT REGISTER) */ #define BIT_SHIFT_RXPKTLMT_8822B 0 @@ -7576,6 +8381,7 @@ #define BIT_GET_RXPKTLMT_8822B(x) (((x) >> BIT_SHIFT_RXPKTLMT_8822B) & BIT_MASK_RXPKTLMT_8822B) + /* 2 REG_MACID_8822B (MAC ID REGISTER) */ #define BIT_SHIFT_MACID_8822B 0 @@ -7584,6 +8390,7 @@ #define BIT_GET_MACID_8822B(x) (((x) >> BIT_SHIFT_MACID_8822B) & BIT_MASK_MACID_8822B) + /* 2 REG_BSSID_8822B (BSSID REGISTER) */ #define BIT_SHIFT_BSSID_8822B 0 @@ -7592,6 +8399,7 @@ #define BIT_GET_BSSID_8822B(x) (((x) >> BIT_SHIFT_BSSID_8822B) & BIT_MASK_BSSID_8822B) + /* 2 REG_MAR_8822B (MULTICAST ADDRESS REGISTER) */ #define BIT_SHIFT_MAR_8822B 0 @@ -7600,6 +8408,7 @@ #define BIT_GET_MAR_8822B(x) (((x) >> BIT_SHIFT_MAR_8822B) & BIT_MASK_MAR_8822B) + /* 2 REG_MBIDCAMCFG_1_8822B (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_SHIFT_MBIDCAM_RWDATA_L_8822B 0 @@ -7608,6 +8417,7 @@ #define BIT_GET_MBIDCAM_RWDATA_L_8822B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) & BIT_MASK_MBIDCAM_RWDATA_L_8822B) + /* 2 REG_MBIDCAMCFG_2_8822B (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_MBIDCAM_POLL_8822B BIT(31) #define BIT_MBIDCAM_WT_EN_8822B BIT(30) @@ -7617,6 +8427,7 @@ #define BIT_MBIDCAM_ADDR_8822B(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8822B) << BIT_SHIFT_MBIDCAM_ADDR_8822B) #define BIT_GET_MBIDCAM_ADDR_8822B(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8822B) & BIT_MASK_MBIDCAM_ADDR_8822B) + #define BIT_MBIDCAM_VALID_8822B BIT(23) #define BIT_LSIC_TXOP_EN_8822B BIT(17) #define BIT_CTS_EN_8822B BIT(16) @@ -7627,6 +8438,7 @@ #define BIT_GET_MBIDCAM_RWDATA_H_8822B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) & BIT_MASK_MBIDCAM_RWDATA_H_8822B) + /* 2 REG_ZLD_NUM_8822B */ #define BIT_SHIFT_ZLD_NUM_8822B 0 @@ -7635,6 +8447,7 @@ #define BIT_GET_ZLD_NUM_8822B(x) (((x) >> BIT_SHIFT_ZLD_NUM_8822B) & BIT_MASK_ZLD_NUM_8822B) + /* 2 REG_UDF_THSD_8822B */ #define BIT_SHIFT_UDF_THSD_8822B 0 @@ -7643,6 +8456,7 @@ #define BIT_GET_UDF_THSD_8822B(x) (((x) >> BIT_SHIFT_UDF_THSD_8822B) & BIT_MASK_UDF_THSD_8822B) + /* 2 REG_WMAC_TCR_TSFT_OFS_8822B */ #define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B 0 @@ -7651,6 +8465,7 @@ #define BIT_GET_WMAC_TCR_TSFT_OFS_8822B(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B) + /* 2 REG_MCU_TEST_2_V1_8822B */ #define BIT_SHIFT_MCU_RSVD_2_V1_8822B 0 @@ -7659,6 +8474,7 @@ #define BIT_GET_MCU_RSVD_2_V1_8822B(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8822B) & BIT_MASK_MCU_RSVD_2_V1_8822B) + /* 2 REG_WMAC_TXTIMEOUT_8822B */ #define BIT_SHIFT_WMAC_TXTIMEOUT_8822B 0 @@ -7667,6 +8483,7 @@ #define BIT_GET_WMAC_TXTIMEOUT_8822B(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822B) & BIT_MASK_WMAC_TXTIMEOUT_8822B) + /* 2 REG_STMP_THSD_8822B */ #define BIT_SHIFT_STMP_THSD_8822B 0 @@ -7675,6 +8492,7 @@ #define BIT_GET_STMP_THSD_8822B(x) (((x) >> BIT_SHIFT_STMP_THSD_8822B) & BIT_MASK_STMP_THSD_8822B) + /* 2 REG_MAC_SPEC_SIFS_8822B (SPECIFICATION SIFS REGISTER) */ #define BIT_SHIFT_SPEC_SIFS_OFDM_8822B 8 @@ -7683,12 +8501,14 @@ #define BIT_GET_SPEC_SIFS_OFDM_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822B) & BIT_MASK_SPEC_SIFS_OFDM_8822B) + #define BIT_SHIFT_SPEC_SIFS_CCK_8822B 0 #define BIT_MASK_SPEC_SIFS_CCK_8822B 0xff #define BIT_SPEC_SIFS_CCK_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_8822B) #define BIT_GET_SPEC_SIFS_CCK_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822B) & BIT_MASK_SPEC_SIFS_CCK_8822B) + /* 2 REG_USTIME_EDCA_8822B (US TIME TUNING FOR EDCA REGISTER) */ #define BIT_SHIFT_USTIME_EDCA_V1_8822B 0 @@ -7697,6 +8517,7 @@ #define BIT_GET_USTIME_EDCA_V1_8822B(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8822B) & BIT_MASK_USTIME_EDCA_V1_8822B) + /* 2 REG_RESP_SIFS_OFDM_8822B (RESPONSE SIFS FOR OFDM REGISTER) */ #define BIT_SHIFT_SIFS_R2T_OFDM_8822B 8 @@ -7705,12 +8526,14 @@ #define BIT_GET_SIFS_R2T_OFDM_8822B(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822B) & BIT_MASK_SIFS_R2T_OFDM_8822B) + #define BIT_SHIFT_SIFS_T2T_OFDM_8822B 0 #define BIT_MASK_SIFS_T2T_OFDM_8822B 0xff #define BIT_SIFS_T2T_OFDM_8822B(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8822B) << BIT_SHIFT_SIFS_T2T_OFDM_8822B) #define BIT_GET_SIFS_T2T_OFDM_8822B(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822B) & BIT_MASK_SIFS_T2T_OFDM_8822B) + /* 2 REG_RESP_SIFS_CCK_8822B (RESPONSE SIFS FOR CCK REGISTER) */ #define BIT_SHIFT_SIFS_R2T_CCK_8822B 8 @@ -7719,12 +8542,14 @@ #define BIT_GET_SIFS_R2T_CCK_8822B(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822B) & BIT_MASK_SIFS_R2T_CCK_8822B) + #define BIT_SHIFT_SIFS_T2T_CCK_8822B 0 #define BIT_MASK_SIFS_T2T_CCK_8822B 0xff #define BIT_SIFS_T2T_CCK_8822B(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8822B) << BIT_SHIFT_SIFS_T2T_CCK_8822B) #define BIT_GET_SIFS_T2T_CCK_8822B(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822B) & BIT_MASK_SIFS_T2T_CCK_8822B) + /* 2 REG_EIFS_8822B (EIFS REGISTER) */ #define BIT_SHIFT_EIFS_8822B 0 @@ -7733,6 +8558,7 @@ #define BIT_GET_EIFS_8822B(x) (((x) >> BIT_SHIFT_EIFS_8822B) & BIT_MASK_EIFS_8822B) + /* 2 REG_CTS2TO_8822B (CTS2 TIMEOUT REGISTER) */ #define BIT_SHIFT_CTS2TO_8822B 0 @@ -7741,6 +8567,7 @@ #define BIT_GET_CTS2TO_8822B(x) (((x) >> BIT_SHIFT_CTS2TO_8822B) & BIT_MASK_CTS2TO_8822B) + /* 2 REG_ACKTO_8822B (ACK TIMEOUT REGISTER) */ #define BIT_SHIFT_ACKTO_8822B 0 @@ -7749,6 +8576,7 @@ #define BIT_GET_ACKTO_8822B(x) (((x) >> BIT_SHIFT_ACKTO_8822B) & BIT_MASK_ACKTO_8822B) + /* 2 REG_NAV_CTRL_8822B (NAV CONTROL REGISTER) */ #define BIT_SHIFT_NAV_UPPER_8822B 16 @@ -7757,18 +8585,21 @@ #define BIT_GET_NAV_UPPER_8822B(x) (((x) >> BIT_SHIFT_NAV_UPPER_8822B) & BIT_MASK_NAV_UPPER_8822B) + #define BIT_SHIFT_RXMYRTS_NAV_8822B 8 #define BIT_MASK_RXMYRTS_NAV_8822B 0xf #define BIT_RXMYRTS_NAV_8822B(x) (((x) & BIT_MASK_RXMYRTS_NAV_8822B) << BIT_SHIFT_RXMYRTS_NAV_8822B) #define BIT_GET_RXMYRTS_NAV_8822B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8822B) & BIT_MASK_RXMYRTS_NAV_8822B) + #define BIT_SHIFT_RTSRST_8822B 0 #define BIT_MASK_RTSRST_8822B 0xff #define BIT_RTSRST_8822B(x) (((x) & BIT_MASK_RTSRST_8822B) << BIT_SHIFT_RTSRST_8822B) #define BIT_GET_RTSRST_8822B(x) (((x) >> BIT_SHIFT_RTSRST_8822B) & BIT_MASK_RTSRST_8822B) + /* 2 REG_BACAMCMD_8822B (BLOCK ACK CAM COMMAND REGISTER) */ #define BIT_BACAM_POLL_8822B BIT(31) #define BIT_BACAM_RST_8822B BIT(17) @@ -7780,12 +8611,14 @@ #define BIT_GET_TXSBM_8822B(x) (((x) >> BIT_SHIFT_TXSBM_8822B) & BIT_MASK_TXSBM_8822B) + #define BIT_SHIFT_BACAM_ADDR_8822B 0 #define BIT_MASK_BACAM_ADDR_8822B 0x3f #define BIT_BACAM_ADDR_8822B(x) (((x) & BIT_MASK_BACAM_ADDR_8822B) << BIT_SHIFT_BACAM_ADDR_8822B) #define BIT_GET_BACAM_ADDR_8822B(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8822B) & BIT_MASK_BACAM_ADDR_8822B) + /* 2 REG_BACAMCONTENT_8822B (BLOCK ACK CAM CONTENT REGISTER) */ #define BIT_SHIFT_BA_CONTENT_H_8822B (32 & CPU_OPT_WIDTH) @@ -7794,13 +8627,15 @@ #define BIT_GET_BA_CONTENT_H_8822B(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8822B) & BIT_MASK_BA_CONTENT_H_8822B) + #define BIT_SHIFT_BA_CONTENT_L_8822B 0 #define BIT_MASK_BA_CONTENT_L_8822B 0xffffffffL #define BIT_BA_CONTENT_L_8822B(x) (((x) & BIT_MASK_BA_CONTENT_L_8822B) << BIT_SHIFT_BA_CONTENT_L_8822B) #define BIT_GET_BA_CONTENT_L_8822B(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8822B) & BIT_MASK_BA_CONTENT_L_8822B) -/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_WMAC_BITMAP_CTL_8822B */ #define BIT_BITMAP_VO_8822B BIT(7) #define BIT_BITMAP_VI_8822B BIT(6) #define BIT_BITMAP_BE_8822B BIT(5) @@ -7811,6 +8646,7 @@ #define BIT_BITMAP_CONDITION_8822B(x) (((x) & BIT_MASK_BITMAP_CONDITION_8822B) << BIT_SHIFT_BITMAP_CONDITION_8822B) #define BIT_GET_BITMAP_CONDITION_8822B(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8822B) & BIT_MASK_BITMAP_CONDITION_8822B) + #define BIT_BITMAP_SSNBK_COUNTER_CLR_8822B BIT(1) #define BIT_BITMAP_FORCE_8822B BIT(0) @@ -7821,6 +8657,7 @@ #define BIT_RXPKT_TYPE_8822B(x) (((x) & BIT_MASK_RXPKT_TYPE_8822B) << BIT_SHIFT_RXPKT_TYPE_8822B) #define BIT_GET_RXPKT_TYPE_8822B(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8822B) & BIT_MASK_RXPKT_TYPE_8822B) + #define BIT_TXACT_IND_8822B BIT(1) #define BIT_RXACT_IND_8822B BIT(0) @@ -7831,6 +8668,7 @@ #define BIT_BITMAP_SSNBK_COUNTER_8822B(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) #define BIT_GET_BITMAP_SSNBK_COUNTER_8822B(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) + #define BIT_BITMAP_EN_8822B BIT(1) #define BIT_WMAC_BACAM_RPMEN_8822B BIT(0) @@ -7842,6 +8680,7 @@ #define BIT_GET_LBDLY_8822B(x) (((x) >> BIT_SHIFT_LBDLY_8822B) & BIT_MASK_LBDLY_8822B) + /* 2 REG_RXERR_RPT_8822B (RX ERROR REPORT REGISTER) */ #define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B 28 @@ -7849,6 +8688,7 @@ #define BIT_RXERR_RPT_SEL_V1_3_0_8822B(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) #define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822B(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) + #define BIT_RXERR_RPT_RST_8822B BIT(27) #define BIT_RXERR_RPT_SEL_V1_4_8822B BIT(26) #define BIT_W1S_8822B BIT(23) @@ -7860,18 +8700,21 @@ #define BIT_GET_UD_SUB_TYPE_8822B(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8822B) & BIT_MASK_UD_SUB_TYPE_8822B) + #define BIT_SHIFT_UD_TYPE_8822B 16 #define BIT_MASK_UD_TYPE_8822B 0x3 #define BIT_UD_TYPE_8822B(x) (((x) & BIT_MASK_UD_TYPE_8822B) << BIT_SHIFT_UD_TYPE_8822B) #define BIT_GET_UD_TYPE_8822B(x) (((x) >> BIT_SHIFT_UD_TYPE_8822B) & BIT_MASK_UD_TYPE_8822B) + #define BIT_SHIFT_RPT_COUNTER_8822B 0 #define BIT_MASK_RPT_COUNTER_8822B 0xffff #define BIT_RPT_COUNTER_8822B(x) (((x) & BIT_MASK_RPT_COUNTER_8822B) << BIT_SHIFT_RPT_COUNTER_8822B) #define BIT_GET_RPT_COUNTER_8822B(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8822B) & BIT_MASK_RPT_COUNTER_8822B) + /* 2 REG_WMAC_TRXPTCL_CTL_8822B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ #define BIT_SHIFT_ACKBA_TYPSEL_8822B (60 & CPU_OPT_WIDTH) @@ -7880,23 +8723,27 @@ #define BIT_GET_ACKBA_TYPSEL_8822B(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822B) & BIT_MASK_ACKBA_TYPSEL_8822B) + #define BIT_SHIFT_ACKBA_ACKPCHK_8822B (56 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBA_ACKPCHK_8822B 0xf #define BIT_ACKBA_ACKPCHK_8822B(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8822B) << BIT_SHIFT_ACKBA_ACKPCHK_8822B) #define BIT_GET_ACKBA_ACKPCHK_8822B(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822B) & BIT_MASK_ACKBA_ACKPCHK_8822B) + #define BIT_SHIFT_ACKBAR_TYPESEL_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBAR_TYPESEL_8822B 0xff #define BIT_ACKBAR_TYPESEL_8822B(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8822B) << BIT_SHIFT_ACKBAR_TYPESEL_8822B) #define BIT_GET_ACKBAR_TYPESEL_8822B(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822B) & BIT_MASK_ACKBAR_TYPESEL_8822B) + #define BIT_SHIFT_ACKBAR_ACKPCHK_8822B (44 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBAR_ACKPCHK_8822B 0xf #define BIT_ACKBAR_ACKPCHK_8822B(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8822B) << BIT_SHIFT_ACKBAR_ACKPCHK_8822B) #define BIT_GET_ACKBAR_ACKPCHK_8822B(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822B) & BIT_MASK_ACKBAR_ACKPCHK_8822B) + #define BIT_RXBA_IGNOREA2_8822B BIT(42) #define BIT_EN_SAVE_ALL_TXOPADDR_8822B BIT(41) #define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8822B BIT(40) @@ -7922,6 +8769,7 @@ #define BIT_RESP_CHNBUSY_8822B(x) (((x) & BIT_MASK_RESP_CHNBUSY_8822B) << BIT_SHIFT_RESP_CHNBUSY_8822B) #define BIT_GET_RESP_CHNBUSY_8822B(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8822B) & BIT_MASK_RESP_CHNBUSY_8822B) + #define BIT_RESP_DCTS_EN_8822B BIT(19) #define BIT_RESP_DCFE_EN_8822B BIT(18) #define BIT_RESP_SPLCPEN_8822B BIT(17) @@ -7936,17 +8784,20 @@ #define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B) + #define BIT_SHIFT_RFMOD_8822B 7 #define BIT_MASK_RFMOD_8822B 0x3 #define BIT_RFMOD_8822B(x) (((x) & BIT_MASK_RFMOD_8822B) << BIT_SHIFT_RFMOD_8822B) #define BIT_GET_RFMOD_8822B(x) (((x) >> BIT_SHIFT_RFMOD_8822B) & BIT_MASK_RFMOD_8822B) + #define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B 5 #define BIT_MASK_RESP_CTS_DYNBW_SEL_8822B 0x3 #define BIT_RESP_CTS_DYNBW_SEL_8822B(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) #define BIT_GET_RESP_CTS_DYNBW_SEL_8822B(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) + #define BIT_DLY_TX_WAIT_RXANTSEL_8822B BIT(4) #define BIT_TXRESP_BY_RXANTSEL_8822B BIT(3) @@ -7956,6 +8807,7 @@ #define BIT_GET_ORIG_DCTS_CHK_8822B(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822B) & BIT_MASK_ORIG_DCTS_CHK_8822B) + /* 2 REG_CAMCMD_8822B (CAM COMMAND REGISTER) */ #define BIT_SECCAM_POLLING_8822B BIT(31) #define BIT_SECCAM_CLR_8822B BIT(30) @@ -7968,6 +8820,7 @@ #define BIT_GET_SECCAM_ADDR_V2_8822B(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822B) & BIT_MASK_SECCAM_ADDR_V2_8822B) + /* 2 REG_CAMWRITE_8822B (CAM WRITE REGISTER) */ #define BIT_SHIFT_CAMW_DATA_8822B 0 @@ -7976,6 +8829,7 @@ #define BIT_GET_CAMW_DATA_8822B(x) (((x) >> BIT_SHIFT_CAMW_DATA_8822B) & BIT_MASK_CAMW_DATA_8822B) + /* 2 REG_CAMREAD_8822B (CAM READ REGISTER) */ #define BIT_SHIFT_CAMR_DATA_8822B 0 @@ -7984,6 +8838,7 @@ #define BIT_GET_CAMR_DATA_8822B(x) (((x) >> BIT_SHIFT_CAMR_DATA_8822B) & BIT_MASK_CAMR_DATA_8822B) + /* 2 REG_CAMDBG_8822B (CAM DEBUG REGISTER) */ #define BIT_SECCAM_INFO_8822B BIT(31) #define BIT_SEC_KEYFOUND_8822B BIT(15) @@ -7993,6 +8848,7 @@ #define BIT_CAMDBG_SEC_TYPE_8822B(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822B) << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) #define BIT_GET_CAMDBG_SEC_TYPE_8822B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) & BIT_MASK_CAMDBG_SEC_TYPE_8822B) + #define BIT_CAMDBG_EXT_SECTYPE_8822B BIT(11) #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B 5 @@ -8001,12 +8857,14 @@ #define BIT_GET_CAMDBG_MIC_KEY_IDX_8822B(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B) + #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B 0 #define BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B 0x1f #define BIT_CAMDBG_SEC_KEY_IDX_8822B(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) #define BIT_GET_CAMDBG_SEC_KEY_IDX_8822B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) + /* 2 REG_RXFILTER_ACTION_1_8822B */ #define BIT_SHIFT_RXFILTER_ACTION_1_8822B 0 @@ -8015,6 +8873,7 @@ #define BIT_GET_RXFILTER_ACTION_1_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822B) & BIT_MASK_RXFILTER_ACTION_1_8822B) + /* 2 REG_RXFILTER_CATEGORY_1_8822B */ #define BIT_SHIFT_RXFILTER_CATEGORY_1_8822B 0 @@ -8023,6 +8882,7 @@ #define BIT_GET_RXFILTER_CATEGORY_1_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) & BIT_MASK_RXFILTER_CATEGORY_1_8822B) + /* 2 REG_SECCFG_8822B (SECURITY CONFIGURATION REGISTER) */ #define BIT_DIS_GCLK_WAPI_8822B BIT(15) #define BIT_DIS_GCLK_AES_8822B BIT(14) @@ -8048,6 +8908,7 @@ #define BIT_GET_RXFILTER_ACTION_3_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822B) & BIT_MASK_RXFILTER_ACTION_3_8822B) + /* 2 REG_RXFILTER_CATEGORY_3_8822B */ #define BIT_SHIFT_RXFILTER_CATEGORY_3_8822B 0 @@ -8056,6 +8917,7 @@ #define BIT_GET_RXFILTER_CATEGORY_3_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) & BIT_MASK_RXFILTER_CATEGORY_3_8822B) + /* 2 REG_RXFILTER_ACTION_2_8822B */ #define BIT_SHIFT_RXFILTER_ACTION_2_8822B 0 @@ -8064,6 +8926,7 @@ #define BIT_GET_RXFILTER_ACTION_2_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822B) & BIT_MASK_RXFILTER_ACTION_2_8822B) + /* 2 REG_RXFILTER_CATEGORY_2_8822B */ #define BIT_SHIFT_RXFILTER_CATEGORY_2_8822B 0 @@ -8072,6 +8935,7 @@ #define BIT_GET_RXFILTER_CATEGORY_2_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) & BIT_MASK_RXFILTER_CATEGORY_2_8822B) + /* 2 REG_RXFLTMAP4_8822B (RX FILTER MAP GROUP 4) */ #define BIT_CTRLFLT15EN_FW_8822B BIT(15) #define BIT_CTRLFLT14EN_FW_8822B BIT(14) @@ -8161,6 +9025,7 @@ #define BIT_PORTSEL__PS_RX_INFO_8822B(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) #define BIT_GET_PORTSEL__PS_RX_INFO_8822B(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B) + #define BIT_RXCTRLIN0_8822B BIT(4) #define BIT_RXMGTIN0_8822B BIT(3) #define BIT_RXDATAIN2_8822B BIT(2) @@ -8179,6 +9044,7 @@ #define BIT_PSF_BSSIDSEL_B2B1_8822B(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) #define BIT_GET_PSF_BSSIDSEL_B2B1_8822B(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) + #define BIT_WOWHCI_8822B BIT(5) #define BIT_PSF_BSSIDSEL_B0_8822B BIT(4) #define BIT_UWF_8822B BIT(3) @@ -8195,21 +9061,24 @@ #define BIT_GET_LPNAV_EARLY_8822B(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8822B) & BIT_MASK_LPNAV_EARLY_8822B) + #define BIT_SHIFT_LPNAV_TH_8822B 0 #define BIT_MASK_LPNAV_TH_8822B 0xffff #define BIT_LPNAV_TH_8822B(x) (((x) & BIT_MASK_LPNAV_TH_8822B) << BIT_SHIFT_LPNAV_TH_8822B) #define BIT_GET_LPNAV_TH_8822B(x) (((x) >> BIT_SHIFT_LPNAV_TH_8822B) & BIT_MASK_LPNAV_TH_8822B) + /* 2 REG_WKFMCAM_CMD_8822B (WAKEUP FRAME CAM COMMAND REGISTER) */ #define BIT_WKFCAM_POLLING_V1_8822B BIT(31) #define BIT_WKFCAM_CLR_V1_8822B BIT(30) #define BIT_WKFCAM_WE_8822B BIT(16) -#define BIT_SHIFT_WKFCAM_ADDR_V1_8822B 7 -#define BIT_MASK_WKFCAM_ADDR_V1_8822B 0x1ff -#define BIT_WKFCAM_ADDR_V1_8822B(x) (((x) & BIT_MASK_WKFCAM_ADDR_V1_8822B) << BIT_SHIFT_WKFCAM_ADDR_V1_8822B) -#define BIT_GET_WKFCAM_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V1_8822B) & BIT_MASK_WKFCAM_ADDR_V1_8822B) +#define BIT_SHIFT_WKFCAM_ADDR_V2_8822B 8 +#define BIT_MASK_WKFCAM_ADDR_V2_8822B 0xff +#define BIT_WKFCAM_ADDR_V2_8822B(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8822B) << BIT_SHIFT_WKFCAM_ADDR_V2_8822B) +#define BIT_GET_WKFCAM_ADDR_V2_8822B(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822B) & BIT_MASK_WKFCAM_ADDR_V2_8822B) + #define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B 0 @@ -8218,6 +9087,7 @@ #define BIT_GET_WKFCAM_CAM_NUM_V1_8822B(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B) + /* 2 REG_WKFMCAM_RWD_8822B (WAKEUP FRAME READ/WRITE DATA) */ #define BIT_SHIFT_WKFMCAM_RWD_8822B 0 @@ -8226,6 +9096,7 @@ #define BIT_GET_WKFMCAM_RWD_8822B(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8822B) & BIT_MASK_WKFMCAM_RWD_8822B) + /* 2 REG_RXFLTMAP1_8822B (RX FILTER MAP GROUP 1) */ #define BIT_CTRLFLT15EN_8822B BIT(15) #define BIT_CTRLFLT14EN_8822B BIT(14) @@ -8290,11 +9161,13 @@ #define BIT_GET_DTIM_CNT_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT_8822B) & BIT_MASK_DTIM_CNT_8822B) + #define BIT_SHIFT_DTIM_PERIOD_8822B 16 #define BIT_MASK_DTIM_PERIOD_8822B 0xff #define BIT_DTIM_PERIOD_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD_8822B) << BIT_SHIFT_DTIM_PERIOD_8822B) #define BIT_GET_DTIM_PERIOD_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8822B) & BIT_MASK_DTIM_PERIOD_8822B) + #define BIT_DTIM_8822B BIT(15) #define BIT_TIM_8822B BIT(14) @@ -8304,6 +9177,7 @@ #define BIT_GET_PS_AID_0_8822B(x) (((x) >> BIT_SHIFT_PS_AID_0_8822B) & BIT_MASK_PS_AID_0_8822B) + /* 2 REG_FLC_TRPC_8822B (TIMER OF FLC_RPC) */ #define BIT_FLC_RPCT_V1_8822B BIT(7) #define BIT_MODE_8822B BIT(6) @@ -8314,6 +9188,7 @@ #define BIT_GET_TRPCD_8822B(x) (((x) >> BIT_SHIFT_TRPCD_8822B) & BIT_MASK_TRPCD_8822B) + /* 2 REG_FLC_PTS_8822B (PKT TYPE SELECTION OF FLC_RPC T) */ #define BIT_CMF_8822B BIT(2) #define BIT_CCF_8822B BIT(1) @@ -8327,6 +9202,7 @@ #define BIT_GET_FLC_RPCT_8822B(x) (((x) >> BIT_SHIFT_FLC_RPCT_8822B) & BIT_MASK_FLC_RPCT_8822B) + /* 2 REG_FLC_RPC_8822B (FW LPS CONDITION -- RX PKT COUNTER) */ #define BIT_SHIFT_FLC_RPC_8822B 0 @@ -8335,6 +9211,7 @@ #define BIT_GET_FLC_RPC_8822B(x) (((x) >> BIT_SHIFT_FLC_RPC_8822B) & BIT_MASK_FLC_RPC_8822B) + /* 2 REG_RXPKTMON_CTRL_8822B */ #define BIT_SHIFT_RXBKQPKT_SEQ_8822B 20 @@ -8343,23 +9220,27 @@ #define BIT_GET_RXBKQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822B) & BIT_MASK_RXBKQPKT_SEQ_8822B) + #define BIT_SHIFT_RXBEQPKT_SEQ_8822B 16 #define BIT_MASK_RXBEQPKT_SEQ_8822B 0xf #define BIT_RXBEQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8822B) << BIT_SHIFT_RXBEQPKT_SEQ_8822B) #define BIT_GET_RXBEQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822B) & BIT_MASK_RXBEQPKT_SEQ_8822B) + #define BIT_SHIFT_RXVIQPKT_SEQ_8822B 12 #define BIT_MASK_RXVIQPKT_SEQ_8822B 0xf #define BIT_RXVIQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8822B) << BIT_SHIFT_RXVIQPKT_SEQ_8822B) #define BIT_GET_RXVIQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822B) & BIT_MASK_RXVIQPKT_SEQ_8822B) + #define BIT_SHIFT_RXVOQPKT_SEQ_8822B 8 #define BIT_MASK_RXVOQPKT_SEQ_8822B 0xf #define BIT_RXVOQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8822B) << BIT_SHIFT_RXVOQPKT_SEQ_8822B) #define BIT_GET_RXVOQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822B) & BIT_MASK_RXVOQPKT_SEQ_8822B) + #define BIT_RXBKQPKT_ERR_8822B BIT(7) #define BIT_RXBEQPKT_ERR_8822B BIT(6) #define BIT_RXVIQPKT_ERR_8822B BIT(5) @@ -8376,11 +9257,13 @@ #define BIT_GET_STATE_SEL_8822B(x) (((x) >> BIT_SHIFT_STATE_SEL_8822B) & BIT_MASK_STATE_SEL_8822B) + #define BIT_SHIFT_STATE_INFO_8822B 8 #define BIT_MASK_STATE_INFO_8822B 0xff #define BIT_STATE_INFO_8822B(x) (((x) & BIT_MASK_STATE_INFO_8822B) << BIT_SHIFT_STATE_INFO_8822B) #define BIT_GET_STATE_INFO_8822B(x) (((x) >> BIT_SHIFT_STATE_INFO_8822B) & BIT_MASK_STATE_INFO_8822B) + #define BIT_UPD_NXT_STATE_8822B BIT(7) #define BIT_SHIFT_CUR_STATE_8822B 0 @@ -8389,6 +9272,7 @@ #define BIT_GET_CUR_STATE_8822B(x) (((x) >> BIT_SHIFT_CUR_STATE_8822B) & BIT_MASK_CUR_STATE_8822B) + /* 2 REG_ERROR_MON_8822B */ #define BIT_MACRX_ERR_1_8822B BIT(17) #define BIT_MACRX_ERR_0_8822B BIT(16) @@ -8405,6 +9289,7 @@ #define BIT_INFO_INDEX_OFFSET_8822B(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8822B) << BIT_SHIFT_INFO_INDEX_OFFSET_8822B) #define BIT_GET_INFO_INDEX_OFFSET_8822B(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822B) & BIT_MASK_INFO_INDEX_OFFSET_8822B) + #define BIT_WMAC_SRCH_FIFOFULL_8822B BIT(15) #define BIT_DIS_INFOSRCH_8822B BIT(14) #define BIT_DISABLE_B0_8822B BIT(13) @@ -8415,6 +9300,7 @@ #define BIT_GET_INFO_ADDR_OFFSET_8822B(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822B) & BIT_MASK_INFO_ADDR_OFFSET_8822B) + /* 2 REG_BT_COEX_TABLE_8822B (BT-COEXISTENCE CONTROL REGISTER) */ #define BIT_PRI_MASK_RX_RESP_8822B BIT(126) #define BIT_PRI_MASK_RXOFDM_8822B BIT(125) @@ -8426,11 +9312,13 @@ #define BIT_GET_PRI_MASK_TXAC_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822B) & BIT_MASK_PRI_MASK_TXAC_8822B) + #define BIT_SHIFT_PRI_MASK_NAV_8822B (109 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_NAV_8822B 0xff #define BIT_PRI_MASK_NAV_8822B(x) (((x) & BIT_MASK_PRI_MASK_NAV_8822B) << BIT_SHIFT_PRI_MASK_NAV_8822B) #define BIT_GET_PRI_MASK_NAV_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8822B) & BIT_MASK_PRI_MASK_NAV_8822B) + #define BIT_PRI_MASK_CCK_8822B BIT(108) #define BIT_PRI_MASK_OFDM_8822B BIT(107) #define BIT_PRI_MASK_RTY_8822B BIT(106) @@ -8441,11 +9329,13 @@ #define BIT_GET_PRI_MASK_NUM_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8822B) & BIT_MASK_PRI_MASK_NUM_8822B) + #define BIT_SHIFT_PRI_MASK_TYPE_8822B (98 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_TYPE_8822B 0xf #define BIT_PRI_MASK_TYPE_8822B(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8822B) << BIT_SHIFT_PRI_MASK_TYPE_8822B) #define BIT_GET_PRI_MASK_TYPE_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822B) & BIT_MASK_PRI_MASK_TYPE_8822B) + #define BIT_OOB_8822B BIT(97) #define BIT_ANT_SEL_8822B BIT(96) @@ -8455,24 +9345,28 @@ #define BIT_GET_BREAK_TABLE_2_8822B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8822B) & BIT_MASK_BREAK_TABLE_2_8822B) + #define BIT_SHIFT_BREAK_TABLE_1_8822B (64 & CPU_OPT_WIDTH) #define BIT_MASK_BREAK_TABLE_1_8822B 0xffff #define BIT_BREAK_TABLE_1_8822B(x) (((x) & BIT_MASK_BREAK_TABLE_1_8822B) << BIT_SHIFT_BREAK_TABLE_1_8822B) #define BIT_GET_BREAK_TABLE_1_8822B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8822B) & BIT_MASK_BREAK_TABLE_1_8822B) + #define BIT_SHIFT_COEX_TABLE_2_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_COEX_TABLE_2_8822B 0xffffffffL #define BIT_COEX_TABLE_2_8822B(x) (((x) & BIT_MASK_COEX_TABLE_2_8822B) << BIT_SHIFT_COEX_TABLE_2_8822B) #define BIT_GET_COEX_TABLE_2_8822B(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8822B) & BIT_MASK_COEX_TABLE_2_8822B) + #define BIT_SHIFT_COEX_TABLE_1_8822B 0 #define BIT_MASK_COEX_TABLE_1_8822B 0xffffffffL #define BIT_COEX_TABLE_1_8822B(x) (((x) & BIT_MASK_COEX_TABLE_1_8822B) << BIT_SHIFT_COEX_TABLE_1_8822B) #define BIT_GET_COEX_TABLE_1_8822B(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8822B) & BIT_MASK_COEX_TABLE_1_8822B) + /* 2 REG_RXCMD_0_8822B */ #define BIT_RXCMD_EN_8822B BIT(31) @@ -8482,6 +9376,7 @@ #define BIT_GET_RXCMD_INFO_8822B(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8822B) & BIT_MASK_RXCMD_INFO_8822B) + /* 2 REG_RXCMD_1_8822B */ #define BIT_SHIFT_RXCMD_PRD_8822B 0 @@ -8490,6 +9385,7 @@ #define BIT_GET_RXCMD_PRD_8822B(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8822B) & BIT_MASK_RXCMD_PRD_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_WMAC_RESP_TXINFO_8822B (RESPONSE TXINFO REGISTER) */ @@ -8500,30 +9396,35 @@ #define BIT_GET_WMAC_RESP_MFB_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822B) & BIT_MASK_WMAC_RESP_MFB_8822B) + #define BIT_SHIFT_WMAC_ANTINF_SEL_8822B 23 #define BIT_MASK_WMAC_ANTINF_SEL_8822B 0x3 #define BIT_WMAC_ANTINF_SEL_8822B(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8822B) << BIT_SHIFT_WMAC_ANTINF_SEL_8822B) #define BIT_GET_WMAC_ANTINF_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822B) & BIT_MASK_WMAC_ANTINF_SEL_8822B) + #define BIT_SHIFT_WMAC_ANTSEL_SEL_8822B 21 #define BIT_MASK_WMAC_ANTSEL_SEL_8822B 0x3 #define BIT_WMAC_ANTSEL_SEL_8822B(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822B) << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) #define BIT_GET_WMAC_ANTSEL_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) & BIT_MASK_WMAC_ANTSEL_SEL_8822B) + #define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B 18 #define BIT_MASK_R_WMAC_RESP_TXPOWER_8822B 0x7 #define BIT_R_WMAC_RESP_TXPOWER_8822B(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) #define BIT_GET_R_WMAC_RESP_TXPOWER_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) + #define BIT_SHIFT_WMAC_RESP_TXANT_8822B 0 #define BIT_MASK_WMAC_RESP_TXANT_8822B 0x3ffff #define BIT_WMAC_RESP_TXANT_8822B(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8822B) << BIT_SHIFT_WMAC_RESP_TXANT_8822B) #define BIT_GET_WMAC_RESP_TXANT_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8822B) & BIT_MASK_WMAC_RESP_TXANT_8822B) + /* 2 REG_BBPSF_CTRL_8822B */ #define BIT_CTL_IDLE_CLR_CSI_RPT_8822B BIT(31) #define BIT_WMAC_USE_NDPARATE_8822B BIT(30) @@ -8534,11 +9435,13 @@ #define BIT_GET_WMAC_CSI_RATE_8822B(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822B) & BIT_MASK_WMAC_CSI_RATE_8822B) + #define BIT_SHIFT_WMAC_RESP_TXRATE_8822B 16 #define BIT_MASK_WMAC_RESP_TXRATE_8822B 0xff #define BIT_WMAC_RESP_TXRATE_8822B(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8822B) << BIT_SHIFT_WMAC_RESP_TXRATE_8822B) #define BIT_GET_WMAC_RESP_TXRATE_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822B) & BIT_MASK_WMAC_RESP_TXRATE_8822B) + #define BIT_BBPSF_MPDUCHKEN_8822B BIT(5) #define BIT_BBPSF_MHCHKEN_8822B BIT(4) #define BIT_BBPSF_ERRCHKEN_8822B BIT(3) @@ -8549,6 +9452,7 @@ #define BIT_GET_BBPSF_ERRTHR_8822B(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8822B) & BIT_MASK_BBPSF_ERRTHR_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_P2P_RX_BCN_NOA_8822B (P2P RX BEACON NOA REGISTER) */ @@ -8561,6 +9465,7 @@ #define BIT_GET_P2P_OUI_TYPE_8822B(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822B) & BIT_MASK_P2P_OUI_TYPE_8822B) + /* 2 REG_ASSOCIATED_BFMER0_INFO_8822B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ #define BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B (48 & CPU_OPT_WIDTH) @@ -8569,12 +9474,14 @@ #define BIT_GET_R_WMAC_TXCSI_AID0_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B) + #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B 0xffffffffffffL #define BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) #define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) + /* 2 REG_ASSOCIATED_BFMER1_INFO_8822B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ #define BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B (48 & CPU_OPT_WIDTH) @@ -8583,12 +9490,14 @@ #define BIT_GET_R_WMAC_TXCSI_AID1_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B) + #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B 0xffffffffffffL #define BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) #define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) + /* 2 REG_TX_CSI_RPT_PARAM_BW20_8822B (TX CSI REPORT PARAMETER REGISTER) */ #define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B 16 @@ -8597,12 +9506,14 @@ #define BIT_GET_R_WMAC_BFINFO_20M_1_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B) + #define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B 0 #define BIT_MASK_R_WMAC_BFINFO_20M_0_8822B 0xfff #define BIT_R_WMAC_BFINFO_20M_0_8822B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) #define BIT_GET_R_WMAC_BFINFO_20M_0_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) + /* 2 REG_TX_CSI_RPT_PARAM_BW40_8822B (TX CSI REPORT PARAMETER_BW40 REGISTER) */ #define BIT_SHIFT_WMAC_RESP_ANTCD_8822B 0 @@ -8611,6 +9522,7 @@ #define BIT_GET_WMAC_RESP_ANTCD_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8822B) & BIT_MASK_WMAC_RESP_ANTCD_8822B) + /* 2 REG_TX_CSI_RPT_PARAM_BW80_8822B (TX CSI REPORT PARAMETER_BW80 REGISTER) */ /* 2 REG_BCN_PSR_RPT2_8822B (BEACON PARSER REPORT REGISTER2) */ @@ -8621,11 +9533,13 @@ #define BIT_GET_DTIM_CNT2_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8822B) & BIT_MASK_DTIM_CNT2_8822B) + #define BIT_SHIFT_DTIM_PERIOD2_8822B 16 #define BIT_MASK_DTIM_PERIOD2_8822B 0xff #define BIT_DTIM_PERIOD2_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD2_8822B) << BIT_SHIFT_DTIM_PERIOD2_8822B) #define BIT_GET_DTIM_PERIOD2_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8822B) & BIT_MASK_DTIM_PERIOD2_8822B) + #define BIT_DTIM2_8822B BIT(15) #define BIT_TIM2_8822B BIT(14) @@ -8635,6 +9549,7 @@ #define BIT_GET_PS_AID_2_8822B(x) (((x) >> BIT_SHIFT_PS_AID_2_8822B) & BIT_MASK_PS_AID_2_8822B) + /* 2 REG_BCN_PSR_RPT3_8822B (BEACON PARSER REPORT REGISTER3) */ #define BIT_SHIFT_DTIM_CNT3_8822B 24 @@ -8643,11 +9558,13 @@ #define BIT_GET_DTIM_CNT3_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8822B) & BIT_MASK_DTIM_CNT3_8822B) + #define BIT_SHIFT_DTIM_PERIOD3_8822B 16 #define BIT_MASK_DTIM_PERIOD3_8822B 0xff #define BIT_DTIM_PERIOD3_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD3_8822B) << BIT_SHIFT_DTIM_PERIOD3_8822B) #define BIT_GET_DTIM_PERIOD3_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8822B) & BIT_MASK_DTIM_PERIOD3_8822B) + #define BIT_DTIM3_8822B BIT(15) #define BIT_TIM3_8822B BIT(14) @@ -8657,6 +9574,7 @@ #define BIT_GET_PS_AID_3_8822B(x) (((x) >> BIT_SHIFT_PS_AID_3_8822B) & BIT_MASK_PS_AID_3_8822B) + /* 2 REG_BCN_PSR_RPT4_8822B (BEACON PARSER REPORT REGISTER4) */ #define BIT_SHIFT_DTIM_CNT4_8822B 24 @@ -8665,11 +9583,13 @@ #define BIT_GET_DTIM_CNT4_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8822B) & BIT_MASK_DTIM_CNT4_8822B) + #define BIT_SHIFT_DTIM_PERIOD4_8822B 16 #define BIT_MASK_DTIM_PERIOD4_8822B 0xff #define BIT_DTIM_PERIOD4_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD4_8822B) << BIT_SHIFT_DTIM_PERIOD4_8822B) #define BIT_GET_DTIM_PERIOD4_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8822B) & BIT_MASK_DTIM_PERIOD4_8822B) + #define BIT_DTIM4_8822B BIT(15) #define BIT_TIM4_8822B BIT(14) @@ -8679,6 +9599,7 @@ #define BIT_GET_PS_AID_4_8822B(x) (((x) >> BIT_SHIFT_PS_AID_4_8822B) & BIT_MASK_PS_AID_4_8822B) + /* 2 REG_A1_ADDR_MASK_8822B (A1 ADDR MASK REGISTER) */ #define BIT_SHIFT_A1_ADDR_MASK_8822B 0 @@ -8687,6 +9608,7 @@ #define BIT_GET_A1_ADDR_MASK_8822B(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8822B) & BIT_MASK_A1_ADDR_MASK_8822B) + /* 2 REG_MACID2_8822B (MAC ID2 REGISTER) */ #define BIT_SHIFT_MACID2_8822B 0 @@ -8695,6 +9617,7 @@ #define BIT_GET_MACID2_8822B(x) (((x) >> BIT_SHIFT_MACID2_8822B) & BIT_MASK_MACID2_8822B) + /* 2 REG_BSSID2_8822B (BSSID2 REGISTER) */ #define BIT_SHIFT_BSSID2_8822B 0 @@ -8703,6 +9626,7 @@ #define BIT_GET_BSSID2_8822B(x) (((x) >> BIT_SHIFT_BSSID2_8822B) & BIT_MASK_BSSID2_8822B) + /* 2 REG_MACID3_8822B (MAC ID3 REGISTER) */ #define BIT_SHIFT_MACID3_8822B 0 @@ -8711,6 +9635,7 @@ #define BIT_GET_MACID3_8822B(x) (((x) >> BIT_SHIFT_MACID3_8822B) & BIT_MASK_MACID3_8822B) + /* 2 REG_BSSID3_8822B (BSSID3 REGISTER) */ #define BIT_SHIFT_BSSID3_8822B 0 @@ -8719,6 +9644,7 @@ #define BIT_GET_BSSID3_8822B(x) (((x) >> BIT_SHIFT_BSSID3_8822B) & BIT_MASK_BSSID3_8822B) + /* 2 REG_MACID4_8822B (MAC ID4 REGISTER) */ #define BIT_SHIFT_MACID4_8822B 0 @@ -8727,6 +9653,7 @@ #define BIT_GET_MACID4_8822B(x) (((x) >> BIT_SHIFT_MACID4_8822B) & BIT_MASK_MACID4_8822B) + /* 2 REG_BSSID4_8822B (BSSID4 REGISTER) */ #define BIT_SHIFT_BSSID4_8822B 0 @@ -8735,6 +9662,7 @@ #define BIT_GET_BSSID4_8822B(x) (((x) >> BIT_SHIFT_BSSID4_8822B) & BIT_MASK_BSSID4_8822B) + /* 2 REG_NOA_REPORT_8822B */ /* 2 REG_PWRBIT_SETTING_8822B */ @@ -8747,35 +9675,218 @@ #define BIT_CLI0_PWRBIT_OW_EN_8822B BIT(1) #define BIT_CLI0_PWR_ST_8822B BIT(0) -/* 2 REG_NOT_VALID_8822B */ +/* 2 REG_WMAC_MU_BF_OPTION_8822B */ +#define BIT_WMAC_RESP_NONSTA1_DIS_8822B BIT(7) +#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN_8822B BIT(6) -/* 2 REG_NOT_VALID_8822B */ +#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B 4 +#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B 0x3 +#define BIT_WMAC_TXMU_ACKPOLICY_8822B(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822B(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B) -/* 2 REG_NOT_VALID_8822B */ -/* 2 REG_NOT_VALID_8822B */ -/* 2 REG_NOT_VALID_8822B */ +#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B 1 +#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B 0x7 +#define BIT_WMAC_MU_BFEE_PORT_SEL_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B) -/* 2 REG_NOT_VALID_8822B */ -/* 2 REG_NOT_VALID_8822B */ +#define BIT_WMAC_MU_BFEE_DIS_8822B BIT(0) /* 2 REG_NOT_VALID_8822B */ -/* 2 REG_NOT_VALID_8822B */ +#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B 0 +#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B 0xff +#define BIT_WMAC_PAUSE_BB_CLR_TH_8822B(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822B(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B) -/* 2 REG_NOT_VALID_8822B */ -/* 2 REG_NOT_VALID_8822B */ -/* 2 REG_NOT_VALID_8822B */ +/* 2 REG_WMAC_MU_ARB_8822B */ +#define BIT_WMAC_ARB_HW_ADAPT_EN_8822B BIT(7) +#define BIT_WMAC_ARB_SW_EN_8822B BIT(6) + +#define BIT_SHIFT_WMAC_ARB_SW_STATE_8822B 0 +#define BIT_MASK_WMAC_ARB_SW_STATE_8822B 0x3f +#define BIT_WMAC_ARB_SW_STATE_8822B(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8822B) << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) +#define BIT_GET_WMAC_ARB_SW_STATE_8822B(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) & BIT_MASK_WMAC_ARB_SW_STATE_8822B) + + + +/* 2 REG_WMAC_MU_OPTION_8822B */ + +#define BIT_SHIFT_WMAC_MU_DBGSEL_8822B 5 +#define BIT_MASK_WMAC_MU_DBGSEL_8822B 0x3 +#define BIT_WMAC_MU_DBGSEL_8822B(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8822B) << BIT_SHIFT_WMAC_MU_DBGSEL_8822B) +#define BIT_GET_WMAC_MU_DBGSEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8822B) & BIT_MASK_WMAC_MU_DBGSEL_8822B) + + + +#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B 0 +#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B 0x1f +#define BIT_WMAC_MU_CPRD_TIMEOUT_8822B(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B) + + + +/* 2 REG_WMAC_MU_BF_CTL_8822B */ +#define BIT_WMAC_INVLD_BFPRT_CHK_8822B BIT(15) +#define BIT_WMAC_RETXBFRPTSEQ_UPD_8822B BIT(14) + +#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B 12 +#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B 0x3 +#define BIT_WMAC_MU_BFRPTSEG_SEL_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B) + + + +#define BIT_SHIFT_WMAC_MU_BF_MYAID_8822B 0 +#define BIT_MASK_WMAC_MU_BF_MYAID_8822B 0xfff +#define BIT_WMAC_MU_BF_MYAID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822B) << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) +#define BIT_GET_WMAC_MU_BF_MYAID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) & BIT_MASK_WMAC_MU_BF_MYAID_8822B) + + + +/* 2 REG_WMAC_MU_BFRPT_PARA_8822B */ + +#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B 12 +#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B 0x7 +#define BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(x) (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B) << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) +#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL_8822B(x) (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B) + + + +#define BIT_SHIFT_BFRPT_PARA_8822B 0 +#define BIT_MASK_BFRPT_PARA_8822B 0xfff +#define BIT_BFRPT_PARA_8822B(x) (((x) & BIT_MASK_BFRPT_PARA_8822B) << BIT_SHIFT_BFRPT_PARA_8822B) +#define BIT_GET_BFRPT_PARA_8822B(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8822B) & BIT_MASK_BFRPT_PARA_8822B) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B */ +#define BIT_STATUS_BFEE2_8822B BIT(10) +#define BIT_WMAC_MU_BFEE2_EN_8822B BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B 0 +#define BIT_MASK_WMAC_MU_BFEE2_AID_8822B 0x1ff +#define BIT_WMAC_MU_BFEE2_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) +#define BIT_GET_WMAC_MU_BFEE2_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) & BIT_MASK_WMAC_MU_BFEE2_AID_8822B) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B */ +#define BIT_STATUS_BFEE3_8822B BIT(10) +#define BIT_WMAC_MU_BFEE3_EN_8822B BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B 0 +#define BIT_MASK_WMAC_MU_BFEE3_AID_8822B 0x1ff +#define BIT_WMAC_MU_BFEE3_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) +#define BIT_GET_WMAC_MU_BFEE3_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) & BIT_MASK_WMAC_MU_BFEE3_AID_8822B) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B */ +#define BIT_STATUS_BFEE4_8822B BIT(10) +#define BIT_WMAC_MU_BFEE4_EN_8822B BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B 0 +#define BIT_MASK_WMAC_MU_BFEE4_AID_8822B 0x1ff +#define BIT_WMAC_MU_BFEE4_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) +#define BIT_GET_WMAC_MU_BFEE4_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) & BIT_MASK_WMAC_MU_BFEE4_AID_8822B) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B */ +#define BIT_STATUS_BFEE5_8822B BIT(10) +#define BIT_WMAC_MU_BFEE5_EN_8822B BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B 0 +#define BIT_MASK_WMAC_MU_BFEE5_AID_8822B 0x1ff +#define BIT_WMAC_MU_BFEE5_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) +#define BIT_GET_WMAC_MU_BFEE5_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) & BIT_MASK_WMAC_MU_BFEE5_AID_8822B) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B */ +#define BIT_STATUS_BFEE6_8822B BIT(10) +#define BIT_WMAC_MU_BFEE6_EN_8822B BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B 0 +#define BIT_MASK_WMAC_MU_BFEE6_AID_8822B 0x1ff +#define BIT_WMAC_MU_BFEE6_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) +#define BIT_GET_WMAC_MU_BFEE6_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) & BIT_MASK_WMAC_MU_BFEE6_AID_8822B) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B */ +#define BIT_BIT_STATUS_BFEE4_8822B BIT(10) +#define BIT_WMAC_MU_BFEE7_EN_8822B BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B 0 +#define BIT_MASK_WMAC_MU_BFEE7_AID_8822B 0x1ff +#define BIT_WMAC_MU_BFEE7_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) +#define BIT_GET_WMAC_MU_BFEE7_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) & BIT_MASK_WMAC_MU_BFEE7_AID_8822B) + + /* 2 REG_NOT_VALID_8822B */ +#define BIT_RST_ALL_COUNTER_8822B BIT(31) + +#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B 16 +#define BIT_MASK_ABORT_RX_VBON_COUNTER_8822B 0xff +#define BIT_ABORT_RX_VBON_COUNTER_8822B(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822B) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8822B(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822B) + + + +#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B 8 +#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B 0xff +#define BIT_ABORT_RX_RDRDY_COUNTER_8822B(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822B(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B) + + + +#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B 0 +#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B 0xff +#define BIT_VBON_EARLY_FALLING_COUNTER_8822B(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822B(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B) + + /* 2 REG_NOT_VALID_8822B */ +#define BIT_WMAC_PLCP_TRX_SEL_8822B BIT(31) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B 28 +#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B 0x7 +#define BIT_WMAC_PLCP_RDSIG_SEL_8822B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B) + + + +#define BIT_SHIFT_WMAC_RATE_IDX_8822B 24 +#define BIT_MASK_WMAC_RATE_IDX_8822B 0xf +#define BIT_WMAC_RATE_IDX_8822B(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8822B) << BIT_SHIFT_WMAC_RATE_IDX_8822B) +#define BIT_GET_WMAC_RATE_IDX_8822B(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822B) & BIT_MASK_WMAC_RATE_IDX_8822B) + + + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8822B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) +#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) + + /* 2 REG_NOT_VALID_8822B */ +#define BIT_WMAC_MUTX_IDX_8822B BIT(24) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8822B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) +#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) + + /* 2 REG_TRANSMIT_ADDRSS_0_8822B (TA0 REGISTER) */ @@ -8785,6 +9896,7 @@ #define BIT_GET_TA0_8822B(x) (((x) >> BIT_SHIFT_TA0_8822B) & BIT_MASK_TA0_8822B) + /* 2 REG_TRANSMIT_ADDRSS_1_8822B (TA1 REGISTER) */ #define BIT_SHIFT_TA1_8822B 0 @@ -8793,6 +9905,7 @@ #define BIT_GET_TA1_8822B(x) (((x) >> BIT_SHIFT_TA1_8822B) & BIT_MASK_TA1_8822B) + /* 2 REG_TRANSMIT_ADDRSS_2_8822B (TA2 REGISTER) */ #define BIT_SHIFT_TA2_8822B 0 @@ -8801,6 +9914,7 @@ #define BIT_GET_TA2_8822B(x) (((x) >> BIT_SHIFT_TA2_8822B) & BIT_MASK_TA2_8822B) + /* 2 REG_TRANSMIT_ADDRSS_3_8822B (TA3 REGISTER) */ #define BIT_SHIFT_TA3_8822B 0 @@ -8809,6 +9923,7 @@ #define BIT_GET_TA3_8822B(x) (((x) >> BIT_SHIFT_TA3_8822B) & BIT_MASK_TA3_8822B) + /* 2 REG_TRANSMIT_ADDRSS_4_8822B (TA4 REGISTER) */ #define BIT_SHIFT_TA4_8822B 0 @@ -8817,6 +9932,7 @@ #define BIT_GET_TA4_8822B(x) (((x) >> BIT_SHIFT_TA4_8822B) & BIT_MASK_TA4_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_MACID1_8822B */ @@ -8827,6 +9943,7 @@ #define BIT_GET_MACID1_8822B(x) (((x) >> BIT_SHIFT_MACID1_8822B) & BIT_MASK_MACID1_8822B) + /* 2 REG_BSSID1_8822B */ #define BIT_SHIFT_BSSID1_8822B 0 @@ -8835,6 +9952,7 @@ #define BIT_GET_BSSID1_8822B(x) (((x) >> BIT_SHIFT_BSSID1_8822B) & BIT_MASK_BSSID1_8822B) + /* 2 REG_BCN_PSR_RPT1_8822B */ #define BIT_SHIFT_DTIM_CNT1_8822B 24 @@ -8843,11 +9961,13 @@ #define BIT_GET_DTIM_CNT1_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8822B) & BIT_MASK_DTIM_CNT1_8822B) + #define BIT_SHIFT_DTIM_PERIOD1_8822B 16 #define BIT_MASK_DTIM_PERIOD1_8822B 0xff #define BIT_DTIM_PERIOD1_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD1_8822B) << BIT_SHIFT_DTIM_PERIOD1_8822B) #define BIT_GET_DTIM_PERIOD1_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8822B) & BIT_MASK_DTIM_PERIOD1_8822B) + #define BIT_DTIM1_8822B BIT(15) #define BIT_TIM1_8822B BIT(14) @@ -8857,6 +9977,7 @@ #define BIT_GET_PS_AID_1_8822B(x) (((x) >> BIT_SHIFT_PS_AID_1_8822B) & BIT_MASK_PS_AID_1_8822B) + /* 2 REG_ASSOCIATED_BFMEE_SEL_8822B */ #define BIT_TXUSER_ID1_8822B BIT(25) @@ -8865,6 +9986,7 @@ #define BIT_AID1_8822B(x) (((x) & BIT_MASK_AID1_8822B) << BIT_SHIFT_AID1_8822B) #define BIT_GET_AID1_8822B(x) (((x) >> BIT_SHIFT_AID1_8822B) & BIT_MASK_AID1_8822B) + #define BIT_TXUSER_ID0_8822B BIT(9) #define BIT_SHIFT_AID0_8822B 0 @@ -8873,6 +9995,7 @@ #define BIT_GET_AID0_8822B(x) (((x) >> BIT_SHIFT_AID0_8822B) & BIT_MASK_AID0_8822B) + /* 2 REG_SND_PTCL_CTRL_8822B */ #define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B 24 @@ -8881,17 +10004,20 @@ #define BIT_GET_NDP_RX_STANDBY_TIMER_8822B(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B) + #define BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B 16 #define BIT_MASK_CSI_RPT_OFFSET_HT_8822B 0xff #define BIT_CSI_RPT_OFFSET_HT_8822B(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8822B) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B) #define BIT_GET_CSI_RPT_OFFSET_HT_8822B(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B) & BIT_MASK_CSI_RPT_OFFSET_HT_8822B) + #define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B 8 #define BIT_MASK_R_WMAC_VHT_CATEGORY_8822B 0xff #define BIT_R_WMAC_VHT_CATEGORY_8822B(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8822B) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B) #define BIT_GET_R_WMAC_VHT_CATEGORY_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B) & BIT_MASK_R_WMAC_VHT_CATEGORY_8822B) + #define BIT_R_WMAC_USE_NSTS_8822B BIT(7) #define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8822B BIT(6) #define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8822B BIT(5) @@ -8914,18 +10040,21 @@ #define BIT_GET_R_WMAC_NSARP_MODEN_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B) + #define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B 4 #define BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B 0x3 #define BIT_R_WMAC_NSARP_RSPFTP_8822B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) #define BIT_GET_R_WMAC_NSARP_RSPFTP_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) + #define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B 0 #define BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B 0xf #define BIT_R_WMAC_NSARP_RSPSEC_8822B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) #define BIT_GET_R_WMAC_NSARP_RSPSEC_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) + /* 2 REG_NS_ARP_INFO_8822B */ #define BIT_REQ_IS_MCNS_8822B BIT(23) #define BIT_REQ_IS_UCNS_8822B BIT(22) @@ -8939,18 +10068,21 @@ #define BIT_GET_EXPRSP_SECTYPE_8822B(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822B) & BIT_MASK_EXPRSP_SECTYPE_8822B) + #define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B 8 #define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B 0xff #define BIT_EXPRSP_CHKSM_7_TO_0_8822B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) #define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) + #define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B 0 #define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B 0xff #define BIT_EXPRSP_CHKSM_15_TO_8_8822B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) #define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) + /* 2 REG_BEAMFORMING_INFO_NSARP_V1_8822B */ #define BIT_SHIFT_WMAC_ARPIP_8822B 0 @@ -8959,6 +10091,7 @@ #define BIT_GET_WMAC_ARPIP_8822B(x) (((x) >> BIT_SHIFT_WMAC_ARPIP_8822B) & BIT_MASK_WMAC_ARPIP_8822B) + /* 2 REG_BEAMFORMING_INFO_NSARP_8822B */ #define BIT_SHIFT_BEAMFORMING_INFO_8822B 0 @@ -8967,6 +10100,7 @@ #define BIT_GET_BEAMFORMING_INFO_8822B(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8822B) & BIT_MASK_BEAMFORMING_INFO_8822B) + /* 2 REG_NOT_VALID_8822B */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B 0 @@ -8975,6 +10109,7 @@ #define BIT_GET_R_WMAC_IPV6_MYIPAD_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B) + /* 2 REG_RSVD_0X740_8822B */ /* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822B */ @@ -8985,12 +10120,14 @@ #define BIT_GET_R_WMAC_CTX_SUBTYPE_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B) + #define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B 0 #define BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B 0xf #define BIT_R_WMAC_RTX_SUBTYPE_8822B(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) #define BIT_GET_R_WMAC_RTX_SUBTYPE_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) + /* 2 REG_WMAC_SWAES_CFG_8822B */ /* 2 REG_BT_COEX_V2_8822B */ @@ -9003,6 +10140,7 @@ #define BIT_GET_TIMER_8822B(x) (((x) >> BIT_SHIFT_TIMER_8822B) & BIT_MASK_TIMER_8822B) + /* 2 REG_BT_COEX_8822B */ #define BIT_R_GNT_BT_RFC_SW_8822B BIT(12) #define BIT_R_GNT_BT_RFC_SW_EN_8822B BIT(11) @@ -9016,6 +10154,7 @@ #define BIT_GET_R_BT_CNT_THR_8822B(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8822B) & BIT_MASK_R_BT_CNT_THR_8822B) + /* 2 REG_WLAN_ACT_MASK_CTRL_8822B */ #define BIT_WLRX_TER_BY_CTL_8822B BIT(43) #define BIT_WLRX_TER_BY_AD_8822B BIT(42) @@ -9031,12 +10170,14 @@ #define BIT_GET_RXMYRTS_NAV_V1_8822B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822B) & BIT_MASK_RXMYRTS_NAV_V1_8822B) + #define BIT_SHIFT_RTSRST_V1_8822B 0 #define BIT_MASK_RTSRST_V1_8822B 0xff #define BIT_RTSRST_V1_8822B(x) (((x) & BIT_MASK_RTSRST_V1_8822B) << BIT_SHIFT_RTSRST_V1_8822B) #define BIT_GET_RTSRST_V1_8822B(x) (((x) >> BIT_SHIFT_RTSRST_V1_8822B) & BIT_MASK_RTSRST_V1_8822B) + /* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8822B */ #define BIT_SHIFT_BT_STAT_DELAY_8822B 12 @@ -9045,17 +10186,20 @@ #define BIT_GET_BT_STAT_DELAY_8822B(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8822B) & BIT_MASK_BT_STAT_DELAY_8822B) + #define BIT_SHIFT_BT_TRX_INIT_DETECT_8822B 8 #define BIT_MASK_BT_TRX_INIT_DETECT_8822B 0xf #define BIT_BT_TRX_INIT_DETECT_8822B(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822B) << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) #define BIT_GET_BT_TRX_INIT_DETECT_8822B(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) & BIT_MASK_BT_TRX_INIT_DETECT_8822B) + #define BIT_SHIFT_BT_PRI_DETECT_TO_8822B 4 #define BIT_MASK_BT_PRI_DETECT_TO_8822B 0xf #define BIT_BT_PRI_DETECT_TO_8822B(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8822B) << BIT_SHIFT_BT_PRI_DETECT_TO_8822B) #define BIT_GET_BT_PRI_DETECT_TO_8822B(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822B) & BIT_MASK_BT_PRI_DETECT_TO_8822B) + #define BIT_R_GRANTALL_WLMASK_8822B BIT(3) #define BIT_STATIS_BT_EN_8822B BIT(2) #define BIT_WL_ACT_MASK_ENABLE_8822B BIT(1) @@ -9069,24 +10213,28 @@ #define BIT_GET_STATIS_BT_LO_RX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8822B) & BIT_MASK_STATIS_BT_LO_RX_8822B) + #define BIT_SHIFT_STATIS_BT_LO_TX_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_STATIS_BT_LO_TX_8822B 0xffff #define BIT_STATIS_BT_LO_TX_8822B(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_8822B) << BIT_SHIFT_STATIS_BT_LO_TX_8822B) #define BIT_GET_STATIS_BT_LO_TX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8822B) & BIT_MASK_STATIS_BT_LO_TX_8822B) + #define BIT_SHIFT_STATIS_BT_HI_RX_8822B 16 #define BIT_MASK_STATIS_BT_HI_RX_8822B 0xffff #define BIT_STATIS_BT_HI_RX_8822B(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8822B) << BIT_SHIFT_STATIS_BT_HI_RX_8822B) #define BIT_GET_STATIS_BT_HI_RX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822B) & BIT_MASK_STATIS_BT_HI_RX_8822B) + #define BIT_SHIFT_STATIS_BT_HI_TX_8822B 0 #define BIT_MASK_STATIS_BT_HI_TX_8822B 0xffff #define BIT_STATIS_BT_HI_TX_8822B(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8822B) << BIT_SHIFT_STATIS_BT_HI_TX_8822B) #define BIT_GET_STATIS_BT_HI_TX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822B) & BIT_MASK_STATIS_BT_HI_TX_8822B) + /* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8822B */ #define BIT_SHIFT_R_BT_CMD_RPT_8822B 16 @@ -9095,17 +10243,20 @@ #define BIT_GET_R_BT_CMD_RPT_8822B(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822B) & BIT_MASK_R_BT_CMD_RPT_8822B) + #define BIT_SHIFT_R_RPT_FROM_BT_8822B 8 #define BIT_MASK_R_RPT_FROM_BT_8822B 0xff #define BIT_R_RPT_FROM_BT_8822B(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8822B) << BIT_SHIFT_R_RPT_FROM_BT_8822B) #define BIT_GET_R_RPT_FROM_BT_8822B(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822B) & BIT_MASK_R_RPT_FROM_BT_8822B) + #define BIT_SHIFT_BT_HID_ISR_SET_8822B 6 #define BIT_MASK_BT_HID_ISR_SET_8822B 0x3 #define BIT_BT_HID_ISR_SET_8822B(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8822B) << BIT_SHIFT_BT_HID_ISR_SET_8822B) #define BIT_GET_BT_HID_ISR_SET_8822B(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822B) & BIT_MASK_BT_HID_ISR_SET_8822B) + #define BIT_TDMA_BT_START_NOTIFY_8822B BIT(5) #define BIT_ENABLE_TDMA_FW_MODE_8822B BIT(4) #define BIT_ENABLE_PTA_TDMA_MODE_8822B BIT(3) @@ -9121,24 +10272,28 @@ #define BIT_GET_BT_PROFILE_8822B(x) (((x) >> BIT_SHIFT_BT_PROFILE_8822B) & BIT_MASK_BT_PROFILE_8822B) + #define BIT_SHIFT_BT_POWER_8822B 16 #define BIT_MASK_BT_POWER_8822B 0xff #define BIT_BT_POWER_8822B(x) (((x) & BIT_MASK_BT_POWER_8822B) << BIT_SHIFT_BT_POWER_8822B) #define BIT_GET_BT_POWER_8822B(x) (((x) >> BIT_SHIFT_BT_POWER_8822B) & BIT_MASK_BT_POWER_8822B) + #define BIT_SHIFT_BT_PREDECT_STATUS_8822B 8 #define BIT_MASK_BT_PREDECT_STATUS_8822B 0xff #define BIT_BT_PREDECT_STATUS_8822B(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8822B) << BIT_SHIFT_BT_PREDECT_STATUS_8822B) #define BIT_GET_BT_PREDECT_STATUS_8822B(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822B) & BIT_MASK_BT_PREDECT_STATUS_8822B) + #define BIT_SHIFT_BT_CMD_INFO_8822B 0 #define BIT_MASK_BT_CMD_INFO_8822B 0xff #define BIT_BT_CMD_INFO_8822B(x) (((x) & BIT_MASK_BT_CMD_INFO_8822B) << BIT_SHIFT_BT_CMD_INFO_8822B) #define BIT_GET_BT_CMD_INFO_8822B(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8822B) & BIT_MASK_BT_CMD_INFO_8822B) + /* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8822B */ #define BIT_EN_MAC_NULL_PKT_NOTIFY_8822B BIT(31) #define BIT_EN_WLAN_RPT_AND_BT_QUERY_8822B BIT(30) @@ -9155,18 +10310,21 @@ #define BIT_GET_WLAN_RPT_DATA_8822B(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822B) & BIT_MASK_WLAN_RPT_DATA_8822B) + #define BIT_SHIFT_CMD_ID_8822B 8 #define BIT_MASK_CMD_ID_8822B 0xff #define BIT_CMD_ID_8822B(x) (((x) & BIT_MASK_CMD_ID_8822B) << BIT_SHIFT_CMD_ID_8822B) #define BIT_GET_CMD_ID_8822B(x) (((x) >> BIT_SHIFT_CMD_ID_8822B) & BIT_MASK_CMD_ID_8822B) + #define BIT_SHIFT_BT_DATA_8822B 0 #define BIT_MASK_BT_DATA_8822B 0xff #define BIT_BT_DATA_8822B(x) (((x) & BIT_MASK_BT_DATA_8822B) << BIT_SHIFT_BT_DATA_8822B) #define BIT_GET_BT_DATA_8822B(x) (((x) >> BIT_SHIFT_BT_DATA_8822B) & BIT_MASK_BT_DATA_8822B) + /* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B */ #define BIT_SHIFT_WLAN_RPT_TO_8822B 0 @@ -9175,6 +10333,7 @@ #define BIT_GET_WLAN_RPT_TO_8822B(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8822B) & BIT_MASK_WLAN_RPT_TO_8822B) + /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B */ #define BIT_SHIFT_ISOLATION_CHK_8822B 1 @@ -9182,6 +10341,7 @@ #define BIT_ISOLATION_CHK_8822B(x) (((x) & BIT_MASK_ISOLATION_CHK_8822B) << BIT_SHIFT_ISOLATION_CHK_8822B) #define BIT_GET_ISOLATION_CHK_8822B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_8822B) & BIT_MASK_ISOLATION_CHK_8822B) + #define BIT_ISOLATION_EN_8822B BIT(0) /* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8822B */ @@ -9202,12 +10362,14 @@ #define BIT_GET_BT_TIME_8822B(x) (((x) >> BIT_SHIFT_BT_TIME_8822B) & BIT_MASK_BT_TIME_8822B) + #define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B 0 #define BIT_MASK_BT_RPT_SAMPLE_RATE_8822B 0x3f #define BIT_BT_RPT_SAMPLE_RATE_8822B(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) #define BIT_GET_BT_RPT_SAMPLE_RATE_8822B(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) + /* 2 REG_BT_ACT_REGISTER_8822B */ #define BIT_SHIFT_BT_EISR_EN_8822B 16 @@ -9215,6 +10377,7 @@ #define BIT_BT_EISR_EN_8822B(x) (((x) & BIT_MASK_BT_EISR_EN_8822B) << BIT_SHIFT_BT_EISR_EN_8822B) #define BIT_GET_BT_EISR_EN_8822B(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8822B) & BIT_MASK_BT_EISR_EN_8822B) + #define BIT_BT_ACT_FALLING_ISR_8822B BIT(10) #define BIT_BT_ACT_RISING_ISR_8822B BIT(9) #define BIT_TDMA_TO_ISR_8822B BIT(8) @@ -9225,6 +10388,7 @@ #define BIT_GET_BT_CH_8822B(x) (((x) >> BIT_SHIFT_BT_CH_8822B) & BIT_MASK_BT_CH_8822B) + /* 2 REG_OBFF_CTRL_BASIC_8822B */ #define BIT_OBFF_EN_V1_8822B BIT(31) @@ -9233,6 +10397,7 @@ #define BIT_OBFF_STATE_V1_8822B(x) (((x) & BIT_MASK_OBFF_STATE_V1_8822B) << BIT_SHIFT_OBFF_STATE_V1_8822B) #define BIT_GET_OBFF_STATE_V1_8822B(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8822B) & BIT_MASK_OBFF_STATE_V1_8822B) + #define BIT_OBFF_ACT_RXDMA_EN_8822B BIT(27) #define BIT_OBFF_BLOCK_INT_EN_8822B BIT(26) #define BIT_OBFF_AUTOACT_EN_8822B BIT(25) @@ -9244,23 +10409,27 @@ #define BIT_GET_WAKE_MAX_PLS_8822B(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822B) & BIT_MASK_WAKE_MAX_PLS_8822B) + #define BIT_SHIFT_WAKE_MIN_PLS_8822B 16 #define BIT_MASK_WAKE_MIN_PLS_8822B 0x7 #define BIT_WAKE_MIN_PLS_8822B(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8822B) << BIT_SHIFT_WAKE_MIN_PLS_8822B) #define BIT_GET_WAKE_MIN_PLS_8822B(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822B) & BIT_MASK_WAKE_MIN_PLS_8822B) + #define BIT_SHIFT_WAKE_MAX_F2F_8822B 12 #define BIT_MASK_WAKE_MAX_F2F_8822B 0x7 #define BIT_WAKE_MAX_F2F_8822B(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8822B) << BIT_SHIFT_WAKE_MAX_F2F_8822B) #define BIT_GET_WAKE_MAX_F2F_8822B(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822B) & BIT_MASK_WAKE_MAX_F2F_8822B) + #define BIT_SHIFT_WAKE_MIN_F2F_8822B 8 #define BIT_MASK_WAKE_MIN_F2F_8822B 0x7 #define BIT_WAKE_MIN_F2F_8822B(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8822B) << BIT_SHIFT_WAKE_MIN_F2F_8822B) #define BIT_GET_WAKE_MIN_F2F_8822B(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822B) & BIT_MASK_WAKE_MIN_F2F_8822B) + #define BIT_APP_CPU_ACT_V1_8822B BIT(3) #define BIT_APP_OBFF_V1_8822B BIT(2) #define BIT_APP_IDLE_V1_8822B BIT(1) @@ -9274,24 +10443,28 @@ #define BIT_GET_RX_HIGH_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B) + #define BIT_SHIFT_RX_MED_TIMER_IDX_8822B 16 #define BIT_MASK_RX_MED_TIMER_IDX_8822B 0x7 #define BIT_RX_MED_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8822B) << BIT_SHIFT_RX_MED_TIMER_IDX_8822B) #define BIT_GET_RX_MED_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822B) & BIT_MASK_RX_MED_TIMER_IDX_8822B) + #define BIT_SHIFT_RX_LOW_TIMER_IDX_8822B 8 #define BIT_MASK_RX_LOW_TIMER_IDX_8822B 0x7 #define BIT_RX_LOW_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822B) << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) #define BIT_GET_RX_LOW_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) & BIT_MASK_RX_LOW_TIMER_IDX_8822B) + #define BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B 0 #define BIT_MASK_OBFF_INT_TIMER_IDX_8822B 0x7 #define BIT_OBFF_INT_TIMER_IDX_8822B(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) #define BIT_GET_OBFF_INT_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B) + /* 2 REG_LTR_CTRL_BASIC_8822B */ #define BIT_LTR_EN_V1_8822B BIT(31) #define BIT_LTR_HW_EN_V1_8822B BIT(30) @@ -9310,30 +10483,35 @@ #define BIT_GET_HIGH_RATE_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B) + #define BIT_SHIFT_MED_RATE_TRIG_SEL_8822B 18 #define BIT_MASK_MED_RATE_TRIG_SEL_8822B 0x3 #define BIT_MED_RATE_TRIG_SEL_8822B(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822B) << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) #define BIT_GET_MED_RATE_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) & BIT_MASK_MED_RATE_TRIG_SEL_8822B) + #define BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B 16 #define BIT_MASK_LOW_RATE_TRIG_SEL_8822B 0x3 #define BIT_LOW_RATE_TRIG_SEL_8822B(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) #define BIT_GET_LOW_RATE_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B) + #define BIT_SHIFT_HIGH_RATE_BD_IDX_8822B 8 #define BIT_MASK_HIGH_RATE_BD_IDX_8822B 0x7f #define BIT_HIGH_RATE_BD_IDX_8822B(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822B) << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) #define BIT_GET_HIGH_RATE_BD_IDX_8822B(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) & BIT_MASK_HIGH_RATE_BD_IDX_8822B) + #define BIT_SHIFT_LOW_RATE_BD_IDX_8822B 0 #define BIT_MASK_LOW_RATE_BD_IDX_8822B 0x7f #define BIT_LOW_RATE_BD_IDX_8822B(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8822B) << BIT_SHIFT_LOW_RATE_BD_IDX_8822B) #define BIT_GET_LOW_RATE_BD_IDX_8822B(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822B) & BIT_MASK_LOW_RATE_BD_IDX_8822B) + /* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8822B */ #define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B 24 @@ -9342,42 +10520,49 @@ #define BIT_GET_RX_EMPTY_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B) + #define BIT_SHIFT_RX_AFULL_TH_IDX_8822B 20 #define BIT_MASK_RX_AFULL_TH_IDX_8822B 0x7 #define BIT_RX_AFULL_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8822B) << BIT_SHIFT_RX_AFULL_TH_IDX_8822B) #define BIT_GET_RX_AFULL_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822B) & BIT_MASK_RX_AFULL_TH_IDX_8822B) + #define BIT_SHIFT_RX_HIGH_TH_IDX_8822B 16 #define BIT_MASK_RX_HIGH_TH_IDX_8822B 0x7 #define BIT_RX_HIGH_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8822B) << BIT_SHIFT_RX_HIGH_TH_IDX_8822B) #define BIT_GET_RX_HIGH_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822B) & BIT_MASK_RX_HIGH_TH_IDX_8822B) + #define BIT_SHIFT_RX_MED_TH_IDX_8822B 12 #define BIT_MASK_RX_MED_TH_IDX_8822B 0x7 #define BIT_RX_MED_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8822B) << BIT_SHIFT_RX_MED_TH_IDX_8822B) #define BIT_GET_RX_MED_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822B) & BIT_MASK_RX_MED_TH_IDX_8822B) + #define BIT_SHIFT_RX_LOW_TH_IDX_8822B 8 #define BIT_MASK_RX_LOW_TH_IDX_8822B 0x7 #define BIT_RX_LOW_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8822B) << BIT_SHIFT_RX_LOW_TH_IDX_8822B) #define BIT_GET_RX_LOW_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822B) & BIT_MASK_RX_LOW_TH_IDX_8822B) + #define BIT_SHIFT_LTR_SPACE_IDX_8822B 4 #define BIT_MASK_LTR_SPACE_IDX_8822B 0x3 #define BIT_LTR_SPACE_IDX_8822B(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8822B) << BIT_SHIFT_LTR_SPACE_IDX_8822B) #define BIT_GET_LTR_SPACE_IDX_8822B(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822B) & BIT_MASK_LTR_SPACE_IDX_8822B) + #define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B 0 #define BIT_MASK_LTR_IDLE_TIMER_IDX_8822B 0x7 #define BIT_LTR_IDLE_TIMER_IDX_8822B(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) #define BIT_GET_LTR_IDLE_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) + /* 2 REG_LTR_IDLE_LATENCY_V1_8822B */ #define BIT_SHIFT_LTR_IDLE_L_8822B 0 @@ -9386,6 +10571,7 @@ #define BIT_GET_LTR_IDLE_L_8822B(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8822B) & BIT_MASK_LTR_IDLE_L_8822B) + /* 2 REG_LTR_ACTIVE_LATENCY_V1_8822B */ #define BIT_SHIFT_LTR_ACT_L_8822B 0 @@ -9394,6 +10580,7 @@ #define BIT_GET_LTR_ACT_L_8822B(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8822B) & BIT_MASK_LTR_ACT_L_8822B) + /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B */ #define BIT_APPEND_MACID_IN_RESP_EN_8822B BIT(50) #define BIT_ADDR2_MATCH_EN_8822B BIT(49) @@ -9405,6 +10592,7 @@ #define BIT_GET_TRAIN_STA_ADDR_8822B(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8822B) & BIT_MASK_TRAIN_STA_ADDR_8822B) + /* 2 REG_RSVD_0X7B4_8822B */ /* 2 REG_WMAC_PKTCNT_RWD_8822B */ @@ -9414,6 +10602,7 @@ #define BIT_PKTCNT_BSSIDMAP_8822B(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822B) << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) #define BIT_GET_PKTCNT_BSSIDMAP_8822B(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) & BIT_MASK_PKTCNT_BSSIDMAP_8822B) + #define BIT_PKTCNT_CNTRST_8822B BIT(1) #define BIT_PKTCNT_CNTEN_8822B BIT(0) @@ -9427,6 +10616,7 @@ #define BIT_GET_WMAC_PKTCNT_CFGAD_8822B(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B) + /* 2 REG_IQ_DUMP_8822B */ #define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B (64 & CPU_OPT_WIDTH) @@ -9435,29 +10625,34 @@ #define BIT_GET_R_WMAC_MATCH_REF_MAC_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B) + #define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_MASK_LA_MAC_8822B 0xffffffffL #define BIT_R_WMAC_MASK_LA_MAC_8822B(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) #define BIT_GET_R_WMAC_MASK_LA_MAC_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) + #define BIT_SHIFT_DUMP_OK_ADDR_8822B 15 #define BIT_MASK_DUMP_OK_ADDR_8822B 0x1ffff #define BIT_DUMP_OK_ADDR_8822B(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8822B) << BIT_SHIFT_DUMP_OK_ADDR_8822B) #define BIT_GET_DUMP_OK_ADDR_8822B(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822B) & BIT_MASK_DUMP_OK_ADDR_8822B) + #define BIT_SHIFT_R_TRIG_TIME_SEL_8822B 8 #define BIT_MASK_R_TRIG_TIME_SEL_8822B 0x7f #define BIT_R_TRIG_TIME_SEL_8822B(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8822B) << BIT_SHIFT_R_TRIG_TIME_SEL_8822B) #define BIT_GET_R_TRIG_TIME_SEL_8822B(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822B) & BIT_MASK_R_TRIG_TIME_SEL_8822B) + #define BIT_SHIFT_R_MAC_TRIG_SEL_8822B 6 #define BIT_MASK_R_MAC_TRIG_SEL_8822B 0x3 #define BIT_R_MAC_TRIG_SEL_8822B(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8822B) << BIT_SHIFT_R_MAC_TRIG_SEL_8822B) #define BIT_GET_R_MAC_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822B) & BIT_MASK_R_MAC_TRIG_SEL_8822B) + #define BIT_MAC_TRIG_REG_8822B BIT(5) #define BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B 3 @@ -9465,6 +10660,7 @@ #define BIT_R_LEVEL_PULSE_SEL_8822B(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) #define BIT_GET_R_LEVEL_PULSE_SEL_8822B(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B) + #define BIT_EN_LA_MAC_8822B BIT(2) #define BIT_R_EN_IQDUMP_8822B BIT(1) #define BIT_R_IQDATA_DUMP_8822B BIT(0) @@ -9487,11 +10683,13 @@ #define BIT_GET_R_WMAC_RX_FIL_LEN_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B) + #define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B (56 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B 0xff #define BIT_R_WMAC_RXFIFO_FULL_TH_8822B(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) #define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) + #define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8822B BIT(55) #define BIT_R_WMAC_RXRST_DLY_8822B BIT(54) #define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_8822B BIT(53) @@ -9523,12 +10721,14 @@ #define BIT_GET_R_OFDM_LEN_8822B(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8822B) & BIT_MASK_R_OFDM_LEN_8822B) + #define BIT_SHIFT_R_CCK_LEN_8822B 0 #define BIT_MASK_R_CCK_LEN_8822B 0xffff #define BIT_R_CCK_LEN_8822B(x) (((x) & BIT_MASK_R_CCK_LEN_8822B) << BIT_SHIFT_R_CCK_LEN_8822B) #define BIT_GET_R_CCK_LEN_8822B(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8822B) & BIT_MASK_R_CCK_LEN_8822B) + /* 2 REG_RX_FILTER_FUNCTION_8822B */ #define BIT_R_WMAC_MHRDDY_LATCH_8822B BIT(14) #define BIT_R_WMAC_MHRDDY_CLR_8822B BIT(13) @@ -9554,6 +10754,7 @@ #define BIT_GET_R_WMAC_TXNDP_SIGB_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B) + /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8822B */ #define BIT_SHIFT_R_MAC_DEBUG_8822B (32 & CPU_OPT_WIDTH) @@ -9562,18 +10763,21 @@ #define BIT_GET_R_MAC_DEBUG_8822B(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_8822B) & BIT_MASK_R_MAC_DEBUG_8822B) + #define BIT_SHIFT_R_MAC_DBG_SHIFT_8822B 8 #define BIT_MASK_R_MAC_DBG_SHIFT_8822B 0x7 #define BIT_R_MAC_DBG_SHIFT_8822B(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822B) << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) #define BIT_GET_R_MAC_DBG_SHIFT_8822B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) & BIT_MASK_R_MAC_DBG_SHIFT_8822B) + #define BIT_SHIFT_R_MAC_DBG_SEL_8822B 0 #define BIT_MASK_R_MAC_DBG_SEL_8822B 0x3 #define BIT_R_MAC_DBG_SEL_8822B(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8822B) << BIT_SHIFT_R_MAC_DBG_SEL_8822B) #define BIT_GET_R_MAC_DBG_SEL_8822B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822B) & BIT_MASK_R_MAC_DBG_SEL_8822B) + /* 2 REG_RTS_ADDRESS_0_8822B */ /* 2 REG_RTS_ADDRESS_1_8822B */ @@ -9607,12 +10811,14 @@ #define BIT_GET_WRITE_BYTE_EN_V1_8822B(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) & BIT_MASK_WRITE_BYTE_EN_V1_8822B) + #define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B 0 #define BIT_MASK_LTECOEX_REG_ADDR_V1_8822B 0xffff #define BIT_LTECOEX_REG_ADDR_V1_8822B(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) #define BIT_GET_LTECOEX_REG_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) + /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B */ #define BIT_SHIFT_LTECOEX_W_DATA_V1_8822B 0 @@ -9621,6 +10827,7 @@ #define BIT_GET_LTECOEX_W_DATA_V1_8822B(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) & BIT_MASK_LTECOEX_W_DATA_V1_8822B) + /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B */ #define BIT_SHIFT_LTECOEX_R_DATA_V1_8822B 0 @@ -9629,6 +10836,7 @@ #define BIT_GET_LTECOEX_R_DATA_V1_8822B(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) & BIT_MASK_LTECOEX_R_DATA_V1_8822B) + /* 2 REG_NOT_VALID_8822B */ /* 2 REG_SDIO_TX_CTRL_8822B */ @@ -9638,6 +10846,7 @@ #define BIT_SDIO_INT_TIMEOUT_8822B(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822B) << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) #define BIT_GET_SDIO_INT_TIMEOUT_8822B(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) & BIT_MASK_SDIO_INT_TIMEOUT_8822B) + #define BIT_IO_ERR_STATUS_8822B BIT(15) #define BIT_REPLY_ERRCRC_IN_DATA_8822B BIT(9) #define BIT_EN_CMD53_OVERLAP_8822B BIT(8) @@ -9708,6 +10917,7 @@ #define BIT_GET_RX_REQ_LEN_V1_8822B(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822B) & BIT_MASK_RX_REQ_LEN_V1_8822B) + /* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8822B */ #define BIT_SHIFT_FREE_TXPG_SEQ_8822B 0 @@ -9716,6 +10926,7 @@ #define BIT_GET_FREE_TXPG_SEQ_8822B(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822B) & BIT_MASK_FREE_TXPG_SEQ_8822B) + /* 2 REG_SDIO_FREE_TXPG_8822B */ #define BIT_SHIFT_MID_FREEPG_V1_8822B 16 @@ -9724,12 +10935,14 @@ #define BIT_GET_MID_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1_8822B) & BIT_MASK_MID_FREEPG_V1_8822B) + #define BIT_SHIFT_HIQ_FREEPG_V1_8822B 0 #define BIT_MASK_HIQ_FREEPG_V1_8822B 0xfff #define BIT_HIQ_FREEPG_V1_8822B(x) (((x) & BIT_MASK_HIQ_FREEPG_V1_8822B) << BIT_SHIFT_HIQ_FREEPG_V1_8822B) #define BIT_GET_HIQ_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822B) & BIT_MASK_HIQ_FREEPG_V1_8822B) + /* 2 REG_SDIO_FREE_TXPG2_8822B */ #define BIT_SHIFT_PUB_FREEPG_V1_8822B 16 @@ -9738,12 +10951,14 @@ #define BIT_GET_PUB_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822B) & BIT_MASK_PUB_FREEPG_V1_8822B) + #define BIT_SHIFT_LOW_FREEPG_V1_8822B 0 #define BIT_MASK_LOW_FREEPG_V1_8822B 0xfff #define BIT_LOW_FREEPG_V1_8822B(x) (((x) & BIT_MASK_LOW_FREEPG_V1_8822B) << BIT_SHIFT_LOW_FREEPG_V1_8822B) #define BIT_GET_LOW_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822B) & BIT_MASK_LOW_FREEPG_V1_8822B) + /* 2 REG_SDIO_OQT_FREE_TXPG_V1_8822B */ #define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B 24 @@ -9752,18 +10967,21 @@ #define BIT_GET_NOAC_OQT_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B) + #define BIT_SHIFT_AC_OQT_FREEPG_V1_8822B 16 #define BIT_MASK_AC_OQT_FREEPG_V1_8822B 0xff #define BIT_AC_OQT_FREEPG_V1_8822B(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822B) << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) #define BIT_GET_AC_OQT_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) & BIT_MASK_AC_OQT_FREEPG_V1_8822B) + #define BIT_SHIFT_EXQ_FREEPG_V1_8822B 0 #define BIT_MASK_EXQ_FREEPG_V1_8822B 0xfff #define BIT_EXQ_FREEPG_V1_8822B(x) (((x) & BIT_MASK_EXQ_FREEPG_V1_8822B) << BIT_SHIFT_EXQ_FREEPG_V1_8822B) #define BIT_GET_EXQ_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822B) & BIT_MASK_EXQ_FREEPG_V1_8822B) + /* 2 REG_SDIO_HTSFR_INFO_8822B */ #define BIT_SHIFT_HTSFR1_8822B 16 @@ -9772,17 +10990,17 @@ #define BIT_GET_HTSFR1_8822B(x) (((x) >> BIT_SHIFT_HTSFR1_8822B) & BIT_MASK_HTSFR1_8822B) + #define BIT_SHIFT_HTSFR0_8822B 0 #define BIT_MASK_HTSFR0_8822B 0xffff #define BIT_HTSFR0_8822B(x) (((x) & BIT_MASK_HTSFR0_8822B) << BIT_SHIFT_HTSFR0_8822B) #define BIT_GET_HTSFR0_8822B(x) (((x) >> BIT_SHIFT_HTSFR0_8822B) & BIT_MASK_HTSFR0_8822B) + /* 2 REG_SDIO_HCPWM1_V2_8822B */ #define BIT_TOGGLING_8822B BIT(7) -#define BIT_WWLAN_8822B BIT(3) -#define BIT_RPS_ST_8822B BIT(2) -#define BIT_WLAN_TRX_8822B BIT(1) +#define BIT_ACK_8822B BIT(6) #define BIT_SYS_CLK_8822B BIT(0) /* 2 REG_SDIO_HCPWM2_V2_8822B */ @@ -9798,12 +11016,14 @@ #define BIT_GET_INDIRECT_REG_SIZE_8822B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822B) & BIT_MASK_INDIRECT_REG_SIZE_8822B) + #define BIT_SHIFT_INDIRECT_REG_ADDR_8822B 0 #define BIT_MASK_INDIRECT_REG_ADDR_8822B 0xffff #define BIT_INDIRECT_REG_ADDR_8822B(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR_8822B) << BIT_SHIFT_INDIRECT_REG_ADDR_8822B) #define BIT_GET_INDIRECT_REG_ADDR_8822B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822B) & BIT_MASK_INDIRECT_REG_ADDR_8822B) + /* 2 REG_SDIO_INDIRECT_REG_DATA_8822B */ #define BIT_SHIFT_INDIRECT_REG_DATA_8822B 0 @@ -9812,6 +11032,7 @@ #define BIT_GET_INDIRECT_REG_DATA_8822B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822B) & BIT_MASK_INDIRECT_REG_DATA_8822B) + /* 2 REG_SDIO_H2C_8822B */ #define BIT_SHIFT_SDIO_H2C_MSG_8822B 0 @@ -9820,6 +11041,7 @@ #define BIT_GET_SDIO_H2C_MSG_8822B(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822B) & BIT_MASK_SDIO_H2C_MSG_8822B) + /* 2 REG_SDIO_C2H_8822B */ #define BIT_SHIFT_SDIO_C2H_MSG_8822B 0 @@ -9828,12 +11050,11 @@ #define BIT_GET_SDIO_C2H_MSG_8822B(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822B) & BIT_MASK_SDIO_C2H_MSG_8822B) + /* 2 REG_SDIO_HRPWM1_8822B */ #define BIT_TOGGLING_8822B BIT(7) -#define BIT_WWLAN_8822B BIT(3) -#define BIT_RPS_ST_8822B BIT(2) -#define BIT_WLAN_TRX_8822B BIT(1) -#define BIT_SYS_CLK_8822B BIT(0) +#define BIT_ACK_8822B BIT(6) +#define BIT_32K_PERMISSION_8822B BIT(0) /* 2 REG_SDIO_HRPWM2_8822B */ @@ -9860,6 +11081,7 @@ #define BIT_GET_CMDIN_2RESP_TIMER_8822B(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) & BIT_MASK_CMDIN_2RESP_TIMER_8822B) + /* 2 REG_SDIO_CMD_CRC_8822B */ #define BIT_SHIFT_SDIO_CMD_CRC_V1_8822B 0 @@ -9868,6 +11090,7 @@ #define BIT_GET_SDIO_CMD_CRC_V1_8822B(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) & BIT_MASK_SDIO_CMD_CRC_V1_8822B) + /* 2 REG_SDIO_HSISR_8822B */ #define BIT_DRV_WLAN_INT_CLR_8822B BIT(1) #define BIT_DRV_WLAN_INT_8822B BIT(0) @@ -9880,7 +11103,7 @@ #define BIT_HR_FF_UDN_8822B BIT(5) #define BIT_TXDMA_BUSY_ERR_8822B BIT(4) #define BIT_TXDMA_VLD_ERR_8822B BIT(3) -#define BIT_QSEL_UNKOWN_ERR_8822B BIT(2) +#define BIT_QSEL_UNKNOWN_ERR_8822B BIT(2) #define BIT_QSEL_MIS_ERR_8822B BIT(1) #define BIT_SDIO_OVERRD_ERR_8822B BIT(0) @@ -9892,6 +11115,7 @@ #define BIT_GET_CMD_CRC_ERR_CNT_8822B(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) & BIT_MASK_CMD_CRC_ERR_CNT_8822B) + /* 2 REG_SDIO_DATA_ERRCNT_8822B */ #define BIT_SHIFT_DATA_CRC_ERR_CNT_8822B 0 @@ -9900,6 +11124,7 @@ #define BIT_GET_DATA_CRC_ERR_CNT_8822B(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) & BIT_MASK_DATA_CRC_ERR_CNT_8822B) + /* 2 REG_SDIO_CMD_ERR_CONTENT_8822B */ #define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B 0 @@ -9908,6 +11133,7 @@ #define BIT_GET_SDIO_CMD_ERR_CONTENT_8822B(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B) + /* 2 REG_SDIO_CRC_ERR_IDX_8822B */ #define BIT_D3_CRC_ERR_8822B BIT(4) #define BIT_D2_CRC_ERR_8822B BIT(3) @@ -9923,6 +11149,7 @@ #define BIT_GET_SDIO_DATA_CRC_8822B(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822B) & BIT_MASK_SDIO_DATA_CRC_8822B) + /* 2 REG_SDIO_DATA_REPLY_TIME_8822B */ #define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B 0 @@ -9931,4 +11158,5 @@ #define BIT_GET_SDIO_DATA_REPLY_TIME_8822B(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B) + #endif diff --git a/hal/halmac/halmac_fw_info.h b/hal/halmac/halmac_fw_info.h index 4b821db..5d2a0a7 100644 --- a/hal/halmac/halmac_fw_info.h +++ b/hal/halmac/halmac_fw_info.h @@ -1,13 +1,28 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_FW_INFO_H_ #define _HALMAC_FW_INFO_H_ -#define H2C_FORMAT_VERSION 4 +#define H2C_FORMAT_VERSION 6 #define H2C_ACK_HDR_CONTENT_LENGTH 8 #define CFG_PARAMETER_ACK_CONTENT_LENGTH 16 #define SCAN_STATUS_RPT_CONTENT_LENGTH 4 #define C2H_DBG_HEADER_LENGTH 4 -#define C2H_DBG_CONTENT_MAX_LENGTH 228 +#define C2H_DBG_CONTENT_MAX_LENGTH 228 #define C2H_DBG_CONTENT_SEQ_OFFSET 1 diff --git a/hal/halmac/halmac_fw_offload_c2h_ap.h b/hal/halmac/halmac_fw_offload_c2h_ap.h index b2f9ecb..ddd3fbe 100644 --- a/hal/halmac/halmac_fw_offload_c2h_ap.h +++ b/hal/halmac/halmac_fw_offload_c2h_ap.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_ #define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_ #define C2H_SUB_CMD_ID_C2H_DBG 0X00 @@ -16,6 +31,20 @@ #define C2H_SUB_CMD_ID_PSD_ACK 0X01 #define C2H_SUB_CMD_ID_PSD_DATA 0X04 #define C2H_SUB_CMD_ID_EFUSE_DATA 0X05 +#define C2H_SUB_CMD_ID_IQK_DATA 0X06 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A +#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B +#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C +#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E +#define C2H_SUB_CMD_ID_CCX_RPT 0X0F +#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10 +#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11 +#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C +#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D #define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER #define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX #define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE @@ -26,6 +55,7 @@ #define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK #define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING #define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD +#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT #define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF #define H2C_CMD_ID_BT_COEX_ACK 0XFF #define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF @@ -36,6 +66,7 @@ #define H2C_CMD_ID_IQK_ACK 0XFF #define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF #define H2C_CMD_ID_PSD_ACK 0XFF +#define H2C_CMD_ID_CCX_RPT 0XFF #define C2H_HDR_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) #define C2H_HDR_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) #define C2H_HDR_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) @@ -117,4 +148,25 @@ #define EFUSE_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8) #define EFUSE_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value) #define EFUSE_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value) +#define IQK_DATA_GET_SEGMENT_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 7) +#define IQK_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 7, __Value) +#define IQK_DATA_SET_SEGMENT_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 7, __Value) +#define IQK_DATA_GET_END_SEGMENT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 7, 1) +#define IQK_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 7, 1, __Value) +#define IQK_DATA_SET_END_SEGMENT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 7, 1, __Value) +#define IQK_DATA_GET_SEGMENT_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) +#define IQK_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) +#define IQK_DATA_SET_SEGMENT_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) +#define IQK_DATA_GET_TOTAL_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) +#define IQK_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) +#define IQK_DATA_SET_TOTAL_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) +#define IQK_DATA_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 0, 16) +#define IQK_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 0, 16, __Value) +#define IQK_DATA_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 0, 16, __Value) +#define IQK_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8) +#define IQK_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value) +#define IQK_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value) +#define CCX_RPT_GET_CCX_RPT(__pC2H) GET_C2H_FIELD(__pC2H + 0X4, 0, 129) +#define CCX_RPT_SET_CCX_RPT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X4, 0, 129, __Value) +#define CCX_RPT_SET_CCX_RPT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X4, 0, 129, __Value) #endif diff --git a/hal/halmac/halmac_fw_offload_c2h_nic.h b/hal/halmac/halmac_fw_offload_c2h_nic.h index ff73963..cbef4dd 100644 --- a/hal/halmac/halmac_fw_offload_c2h_nic.h +++ b/hal/halmac/halmac_fw_offload_c2h_nic.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_ #define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_ #define C2H_SUB_CMD_ID_C2H_DBG 0X00 @@ -16,6 +31,20 @@ #define C2H_SUB_CMD_ID_PSD_ACK 0X01 #define C2H_SUB_CMD_ID_PSD_DATA 0X04 #define C2H_SUB_CMD_ID_EFUSE_DATA 0X05 +#define C2H_SUB_CMD_ID_IQK_DATA 0X06 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A +#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B +#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C +#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E +#define C2H_SUB_CMD_ID_CCX_RPT 0X0F +#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10 +#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11 +#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C +#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D #define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER #define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX #define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE @@ -26,6 +55,7 @@ #define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK #define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING #define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD +#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT #define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF #define H2C_CMD_ID_BT_COEX_ACK 0XFF #define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF @@ -36,6 +66,7 @@ #define H2C_CMD_ID_IQK_ACK 0XFF #define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF #define H2C_CMD_ID_PSD_ACK 0XFF +#define H2C_CMD_ID_CCX_RPT 0XFF #define C2H_HDR_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) #define C2H_HDR_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) #define C2H_HDR_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) @@ -90,4 +121,18 @@ #define EFUSE_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value) #define EFUSE_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8) #define EFUSE_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value) +#define IQK_DATA_GET_SEGMENT_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 7) +#define IQK_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 7, __Value) +#define IQK_DATA_GET_END_SEGMENT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 7, 1) +#define IQK_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 7, 1, __Value) +#define IQK_DATA_GET_SEGMENT_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) +#define IQK_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) +#define IQK_DATA_GET_TOTAL_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) +#define IQK_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) +#define IQK_DATA_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 0, 16) +#define IQK_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value) +#define IQK_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8) +#define IQK_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value) +#define CCX_RPT_GET_CCX_RPT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X4, 0, 129) +#define CCX_RPT_SET_CCX_RPT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X4, 0, 129, __Value) #endif diff --git a/hal/halmac/halmac_fw_offload_h2c_ap.h b/hal/halmac/halmac_fw_offload_h2c_ap.h index 8e5e6a1..e7caaab 100644 --- a/hal/halmac/halmac_fw_offload_h2c_ap.h +++ b/hal/halmac/halmac_fw_offload_h2c_ap.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_ #define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_ #define CMD_ID_FW_OFFLOAD_H2C 0XFF @@ -13,7 +28,11 @@ #define CMD_ID_IQK 0XFF #define CMD_ID_POWER_TRACKING 0XFF #define CMD_ID_PSD 0XFF +#define CMD_ID_P2PPS 0XFF #define CMD_ID_BT_COEX 0XFF +#define CMD_ID_NAN_CTRL 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF #define CATEGORY_H2C_CMD_HEADER 0X00 #define CATEGORY_FW_OFFLOAD_H2C 0X01 #define CATEGORY_CHANNEL_SWITCH 0X01 @@ -28,7 +47,11 @@ #define CATEGORY_IQK 0X01 #define CATEGORY_POWER_TRACKING 0X01 #define CATEGORY_PSD 0X01 +#define CATEGORY_P2PPS 0X01 #define CATEGORY_BT_COEX 0X01 +#define CATEGORY_NAN_CTRL 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01 #define SUB_CMD_ID_CHANNEL_SWITCH 0X02 #define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03 #define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05 @@ -41,7 +64,11 @@ #define SUB_CMD_ID_IQK 0X0E #define SUB_CMD_ID_POWER_TRACKING 0X0F #define SUB_CMD_ID_PSD 0X10 +#define SUB_CMD_ID_P2PPS 0X24 #define SUB_CMD_ID_BT_COEX 0X60 +#define SUB_CMD_ID_NAN_CTRL 0XB2 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5 #define H2C_CMD_HEADER_GET_CATEGORY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 7) #define H2C_CMD_HEADER_SET_CATEGORY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 7, __Value) #define H2C_CMD_HEADER_SET_CATEGORY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 7, __Value) @@ -174,18 +201,12 @@ #define DOWNLOAD_FLASH_GET_LOCATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 16) #define DOWNLOAD_FLASH_SET_LOCATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 16, __Value) #define DOWNLOAD_FLASH_SET_LOCATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 16, __Value) -#define DOWNLOAD_FLASH_GET_START_ADDR(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 32) -#define DOWNLOAD_FLASH_SET_START_ADDR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 32, __Value) -#define DOWNLOAD_FLASH_SET_START_ADDR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 32, __Value) -#define DOWNLOAD_FLASH_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 16) -#define DOWNLOAD_FLASH_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 16, __Value) -#define DOWNLOAD_FLASH_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 16, __Value) -#define DOWNLOAD_FLASH_GET_SEGMENT_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 16, 7) -#define DOWNLOAD_FLASH_SET_SEGMENT_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 16, 7, __Value) -#define DOWNLOAD_FLASH_SET_SEGMENT_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 16, 7, __Value) -#define DOWNLOAD_FLASH_GET_END_SEGMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 23, 1) -#define DOWNLOAD_FLASH_SET_END_SEGMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 23, 1, __Value) -#define DOWNLOAD_FLASH_SET_END_SEGMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 23, 1, __Value) +#define DOWNLOAD_FLASH_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 32) +#define DOWNLOAD_FLASH_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 32, __Value) +#define DOWNLOAD_FLASH_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 32, __Value) +#define DOWNLOAD_FLASH_GET_START_ADDR(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) +#define DOWNLOAD_FLASH_SET_START_ADDR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) +#define DOWNLOAD_FLASH_SET_START_ADDR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) #define UPDATE_PACKET_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) #define UPDATE_PACKET_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) #define UPDATE_PACKET_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) @@ -207,6 +228,9 @@ #define IQK_GET_CLEAR(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) #define IQK_SET_CLEAR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) #define IQK_SET_CLEAR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) +#define IQK_GET_SEGMENT_IQK(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) +#define IQK_SET_SEGMENT_IQK(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) +#define IQK_SET_SEGMENT_IQK_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) #define POWER_TRACKING_GET_ENABLE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) #define POWER_TRACKING_SET_ENABLE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) #define POWER_TRACKING_SET_ENABLE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) @@ -267,7 +291,145 @@ #define PSD_GET_END_PSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 16) #define PSD_SET_END_PSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 16, __Value) #define PSD_SET_END_PSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 16, __Value) +#define P2PPS_GET_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) +#define P2PPS_SET_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) +#define P2PPS_SET_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) +#define P2PPS_GET_ROLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) +#define P2PPS_SET_ROLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) +#define P2PPS_SET_ROLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) +#define P2PPS_GET_CTWINDOW_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 2, 1) +#define P2PPS_SET_CTWINDOW_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 2, 1, __Value) +#define P2PPS_SET_CTWINDOW_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 2, 1, __Value) +#define P2PPS_GET_NOA_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 3, 1) +#define P2PPS_SET_NOA_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 3, 1, __Value) +#define P2PPS_SET_NOA_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 3, 1, __Value) +#define P2PPS_GET_NOA_SEL(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 4, 1) +#define P2PPS_SET_NOA_SEL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 4, 1, __Value) +#define P2PPS_SET_NOA_SEL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 4, 1, __Value) +#define P2PPS_GET_ALLSTASLEEP(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 5, 1) +#define P2PPS_SET_ALLSTASLEEP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 5, 1, __Value) +#define P2PPS_SET_ALLSTASLEEP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 5, 1, __Value) +#define P2PPS_GET_DISCOVERY(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 6, 1) +#define P2PPS_SET_DISCOVERY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 6, 1, __Value) +#define P2PPS_SET_DISCOVERY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 6, 1, __Value) +#define P2PPS_GET_P2P_PORT_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) +#define P2PPS_SET_P2P_PORT_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) +#define P2PPS_SET_P2P_PORT_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) +#define P2PPS_GET_P2P_GROUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) +#define P2PPS_SET_P2P_GROUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) +#define P2PPS_SET_P2P_GROUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) +#define P2PPS_GET_P2P_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) +#define P2PPS_SET_P2P_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) +#define P2PPS_SET_P2P_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) +#define P2PPS_GET_CTWINDOW_LENGTH(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) +#define P2PPS_SET_CTWINDOW_LENGTH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define P2PPS_SET_CTWINDOW_LENGTH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define P2PPS_GET_NOA_DURATION_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) +#define P2PPS_SET_NOA_DURATION_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) +#define P2PPS_SET_NOA_DURATION_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) +#define P2PPS_GET_NOA_INTERVAL_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 32) +#define P2PPS_SET_NOA_INTERVAL_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 32, __Value) +#define P2PPS_SET_NOA_INTERVAL_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 32, __Value) +#define P2PPS_GET_NOA_START_TIME_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 32) +#define P2PPS_SET_NOA_START_TIME_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 32, __Value) +#define P2PPS_SET_NOA_START_TIME_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 32, __Value) +#define P2PPS_GET_NOA_COUNT_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 32) +#define P2PPS_SET_NOA_COUNT_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 32, __Value) +#define P2PPS_SET_NOA_COUNT_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 32, __Value) #define BT_COEX_GET_DATA_START(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) #define BT_COEX_SET_DATA_START(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) #define BT_COEX_SET_DATA_START_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CTRL_GET_NAN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 2) +#define NAN_CTRL_SET_NAN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 2, __Value) +#define NAN_CTRL_SET_NAN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 2, __Value) +#define NAN_CTRL_GET_SUPPORT_BAND(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 2) +#define NAN_CTRL_SET_SUPPORT_BAND(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 2, __Value) +#define NAN_CTRL_SET_SUPPORT_BAND_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 2, __Value) +#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 10, 1) +#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 10, 1, __Value) +#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 10, 1, __Value) +#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 11, 1) +#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 11, 1, __Value) +#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 11, 1, __Value) +#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) +#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) +#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) +#define NAN_CTRL_GET_CHANNEL_2G(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) +#define NAN_CTRL_SET_CHANNEL_2G(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) +#define NAN_CTRL_SET_CHANNEL_2G_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) +#define NAN_CTRL_GET_CHANNEL_5G(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) +#define NAN_CTRL_SET_CHANNEL_5G(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define NAN_CTRL_SET_CHANNEL_5G_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 16, 16, __Value) #endif diff --git a/hal/halmac/halmac_fw_offload_h2c_nic.h b/hal/halmac/halmac_fw_offload_h2c_nic.h index 83f5740..a885c85 100644 --- a/hal/halmac/halmac_fw_offload_h2c_nic.h +++ b/hal/halmac/halmac_fw_offload_h2c_nic.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_ #define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_ #define CMD_ID_FW_OFFLOAD_H2C 0XFF @@ -13,7 +28,11 @@ #define CMD_ID_IQK 0XFF #define CMD_ID_POWER_TRACKING 0XFF #define CMD_ID_PSD 0XFF +#define CMD_ID_P2PPS 0XFF #define CMD_ID_BT_COEX 0XFF +#define CMD_ID_NAN_CTRL 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF #define CATEGORY_H2C_CMD_HEADER 0X00 #define CATEGORY_FW_OFFLOAD_H2C 0X01 #define CATEGORY_CHANNEL_SWITCH 0X01 @@ -28,7 +47,11 @@ #define CATEGORY_IQK 0X01 #define CATEGORY_POWER_TRACKING 0X01 #define CATEGORY_PSD 0X01 +#define CATEGORY_P2PPS 0X01 #define CATEGORY_BT_COEX 0X01 +#define CATEGORY_NAN_CTRL 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01 #define SUB_CMD_ID_CHANNEL_SWITCH 0X02 #define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03 #define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05 @@ -41,7 +64,11 @@ #define SUB_CMD_ID_IQK 0X0E #define SUB_CMD_ID_POWER_TRACKING 0X0F #define SUB_CMD_ID_PSD 0X10 +#define SUB_CMD_ID_P2PPS 0X24 #define SUB_CMD_ID_BT_COEX 0X60 +#define SUB_CMD_ID_NAN_CTRL 0XB2 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5 #define H2C_CMD_HEADER_GET_CATEGORY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 7) #define H2C_CMD_HEADER_SET_CATEGORY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 7, __Value) #define H2C_CMD_HEADER_GET_ACK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 7, 1) @@ -148,6 +175,8 @@ #define GENERAL_INFO_SET_FW_TX_BOUNDARY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) #define IQK_GET_CLEAR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) #define IQK_SET_CLEAR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) +#define IQK_GET_SEGMENT_IQK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) +#define IQK_SET_SEGMENT_IQK(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) #define POWER_TRACKING_GET_ENABLE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) #define POWER_TRACKING_SET_ENABLE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) #define POWER_TRACKING_GET_ENABLE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) @@ -188,6 +217,98 @@ #define PSD_SET_START_PSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) #define PSD_GET_END_PSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 16) #define PSD_SET_END_PSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 16, __Value) +#define P2PPS_GET_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) +#define P2PPS_SET_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) +#define P2PPS_GET_ROLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) +#define P2PPS_SET_ROLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) +#define P2PPS_GET_CTWINDOW_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 2, 1) +#define P2PPS_SET_CTWINDOW_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 2, 1, __Value) +#define P2PPS_GET_NOA_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 3, 1) +#define P2PPS_SET_NOA_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 3, 1, __Value) +#define P2PPS_GET_NOA_SEL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 4, 1) +#define P2PPS_SET_NOA_SEL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 4, 1, __Value) +#define P2PPS_GET_ALLSTASLEEP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 5, 1) +#define P2PPS_SET_ALLSTASLEEP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 5, 1, __Value) +#define P2PPS_GET_DISCOVERY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 6, 1) +#define P2PPS_SET_DISCOVERY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 6, 1, __Value) +#define P2PPS_GET_P2P_PORT_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) +#define P2PPS_SET_P2P_PORT_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) +#define P2PPS_GET_P2P_GROUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) +#define P2PPS_SET_P2P_GROUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) +#define P2PPS_GET_P2P_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) +#define P2PPS_SET_P2P_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) +#define P2PPS_GET_CTWINDOW_LENGTH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) +#define P2PPS_SET_CTWINDOW_LENGTH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) +#define P2PPS_GET_NOA_DURATION_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) +#define P2PPS_SET_NOA_DURATION_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) +#define P2PPS_GET_NOA_INTERVAL_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 32) +#define P2PPS_SET_NOA_INTERVAL_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 32, __Value) +#define P2PPS_GET_NOA_START_TIME_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 32) +#define P2PPS_SET_NOA_START_TIME_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 32, __Value) +#define P2PPS_GET_NOA_COUNT_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 32) +#define P2PPS_SET_NOA_COUNT_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 32, __Value) #define BT_COEX_GET_DATA_START(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) #define BT_COEX_SET_DATA_START(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CTRL_GET_NAN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 2) +#define NAN_CTRL_SET_NAN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 2, __Value) +#define NAN_CTRL_GET_SUPPORT_BAND(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 2) +#define NAN_CTRL_SET_SUPPORT_BAND(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 2, __Value) +#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 10, 1) +#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 10, 1, __Value) +#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 11, 1) +#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 11, 1, __Value) +#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) +#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) +#define NAN_CTRL_GET_CHANNEL_2G(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) +#define NAN_CTRL_SET_CHANNEL_2G(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) +#define NAN_CTRL_GET_CHANNEL_5G(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) +#define NAN_CTRL_SET_CHANNEL_5G(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 16, 16, __Value) #endif diff --git a/hal/halmac/halmac_h2c_extra_info_ap.h b/hal/halmac/halmac_h2c_extra_info_ap.h index f19324a..c9510f5 100644 --- a/hal/halmac/halmac_h2c_extra_info_ap.h +++ b/hal/halmac/halmac_h2c_extra_info_ap.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_ #define _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_ #define PHY_PARAMETER_INFO_GET_LENGTH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 8) diff --git a/hal/halmac/halmac_h2c_extra_info_nic.h b/hal/halmac/halmac_h2c_extra_info_nic.h index 20bfb5a..41e4e96 100644 --- a/hal/halmac/halmac_h2c_extra_info_nic.h +++ b/hal/halmac/halmac_h2c_extra_info_nic.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_ #define _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_ #define PHY_PARAMETER_INFO_GET_LENGTH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 8) diff --git a/hal/halmac/halmac_hw_cfg.h b/hal/halmac/halmac_hw_cfg.h index 60a346a..b63cf18 100644 --- a/hal/halmac/halmac_hw_cfg.h +++ b/hal/halmac/halmac_hw_cfg.h @@ -1,35 +1,159 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __HALMAC__HW_CFG_H__ #define __HALMAC__HW_CFG_H__ +#include /* CONFIG_[IC] */ + #ifndef BIT - #define BIT(x) (1 << (x)) + #define BIT(x) (1 << (x)) #endif +#ifdef CONFIG_RTL8723A +#define HALMAC_8723A_SUPPORT 1 +#else #define HALMAC_8723A_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8188E +#define HALMAC_8188E_SUPPORT 1 +#else #define HALMAC_8188E_SUPPORT 0 -#define HALMAC_8821A_SUPPORT 0 -#define HALMAC_8723B_SUPPORT 0 -#define HALMAC_8812A_SUPPORT 0 -#define HALMAC_8192E_SUPPORT 0 -#define HALMAC_8881A_SUPPORT 0 -#define HALMAC_8821B_SUPPORT 0 -#define HALMAC_8814A_SUPPORT 0 -#define HALMAC_8814B_SUPPORT 0 -#define HALMAC_8881A_SUPPORT 0 -#define HALMAC_8703B_SUPPORT 0 -#define HALMAC_8723D_SUPPORT 0 -#define HALMAC_8188F_SUPPORT 0 -#define HALMAC_8821BMP_SUPPORT 0 -#define HALMAC_8814AMP_SUPPORT 0 -#define HALMAC_8195A_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8821A +#define HALMAC_8821A_SUPPORT 1 +#else +#define HALMAC_8821A_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8723B +#define HALMAC_8723B_SUPPORT 1 +#else +#define HALMAC_8723B_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8812A +#define HALMAC_8812A_SUPPORT 1 +#else +#define HALMAC_8812A_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8192E +#define HALMAC_8192E_SUPPORT 1 +#else +#define HALMAC_8192E_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8881A +#define HALMAC_8881A_SUPPORT 1 +#else +#define HALMAC_8881A_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8821B +#define HALMAC_8821B_SUPPORT 1 +#else #define HALMAC_8821B_SUPPORT 0 -#define HALMAC_8196F_SUPPORT 0 -#define HALMAC_8197F_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8814A +#define HALMAC_8814A_SUPPORT 1 +#else +#define HALMAC_8814A_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8814B +#define HALMAC_8814B_SUPPORT 1 +#else +#define HALMAC_8814B_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8881A +#define HALMAC_8881A_SUPPORT 1 +#else +#define HALMAC_8881A_SUPPORT 0 +#endif +#ifdef CONFIG_RTL8703B +#define HALMAC_8703B_SUPPORT 1 +#else +#define HALMAC_8703B_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8723D +#define HALMAC_8723D_SUPPORT 1 +#else +#define HALMAC_8723D_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8188F +#define HALMAC_8188F_SUPPORT 1 +#else +#define HALMAC_8188F_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8821BMP +#define HALMAC_8821BMP_SUPPORT 1 +#else +#define HALMAC_8821BMP_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8814AMP +#define HALMAC_8814AMP_SUPPORT 1 +#else +#define HALMAC_8814AMP_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8195A +#define HALMAC_8195A_SUPPORT 1 +#else +#define HALMAC_8195A_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8821B +#define HALMAC_8821B_SUPPORT 1 +#else +#define HALMAC_8821B_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8196F +#define HALMAC_8196F_SUPPORT 1 +#else +#define HALMAC_8196F_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8197F +#define HALMAC_8197F_SUPPORT 1 +#else +#define HALMAC_8197F_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8821C +#define HALMAC_8821C_SUPPORT 1 +#else #define HALMAC_8821C_SUPPORT 0 -#define HALMAC_8822B_SUPPORT 1 +#endif +#ifdef CONFIG_RTL8822B +#define HALMAC_8822B_SUPPORT 1 +#else +#define HALMAC_8822B_SUPPORT 0 #endif +#endif /* __HALMAC__HW_CFG_H__ */ diff --git a/hal/halmac/halmac_original_c2h_ap.h b/hal/halmac/halmac_original_c2h_ap.h index 433da10..731702a 100644 --- a/hal/halmac/halmac_original_c2h_ap.h +++ b/hal/halmac/halmac_original_c2h_ap.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_ #define _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_ #define CMD_ID_C2H 0X00 diff --git a/hal/halmac/halmac_original_c2h_nic.h b/hal/halmac/halmac_original_c2h_nic.h index b72c1ce..cd587da 100644 --- a/hal/halmac/halmac_original_c2h_nic.h +++ b/hal/halmac/halmac_original_c2h_nic.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_ #define _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_ #define CMD_ID_C2H 0X00 diff --git a/hal/halmac/halmac_original_h2c_ap.h b/hal/halmac/halmac_original_h2c_ap.h index 248ffad..c5100a7 100644 --- a/hal/halmac/halmac_original_h2c_ap.h +++ b/hal/halmac/halmac_original_h2c_ap.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_ #define _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_ #define CMD_ID_ORIGINAL_H2C 0X00 @@ -24,10 +39,11 @@ #define CMD_ID_AP_REQ_TXRPT 0X03 #define CMD_ID_INIT_RATE_COLLECTION 0X04 #define CMD_ID_IQK_OFFLOAD 0X05 -#define CMD_ID_RA_PARA_ADJUST 0X06 +#define CMD_ID_MACID_CFG_3SS 0X06 +#define CMD_ID_RA_PARA_ADJUST 0X07 #define CMD_ID_WWLAN 0X00 #define CMD_ID_REMOTE_WAKE_CTRL 0X01 -#define CMD_ID_AOAC_BLOBAL_INFO 0X02 +#define CMD_ID_AOAC_GLOBAL_INFO 0X02 #define CMD_ID_AOAC_RSVD_PAGE 0X03 #define CMD_ID_AOAC_RSVD_PAGE2 0X04 #define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05 @@ -48,33 +64,34 @@ #define CLASS_PS_TUNING_PARA_II 0X01 #define CLASS_PS_LPS_PARA 0X01 #define CLASS_P2P_PS_OFFLOAD 0X01 -#define CLASS_PS_SCAN_EN 0X0 -#define CLASS_SAP_PS 0X0 -#define CLASS_INACTIVE_PS 0X0 +#define CLASS_PS_SCAN_EN 0X1 +#define CLASS_SAP_PS 0X1 +#define CLASS_INACTIVE_PS 0X1 #define CLASS_MACID_CFG 0X2 #define CLASS_TXBF 0X2 #define CLASS_RSSI_SETTING 0X2 #define CLASS_AP_REQ_TXRPT 0X2 #define CLASS_INIT_RATE_COLLECTION 0X2 #define CLASS_IQK_OFFLOAD 0X2 +#define CLASS_MACID_CFG_3SS 0X2 #define CLASS_RA_PARA_ADJUST 0X02 #define CLASS_WWLAN 0X4 #define CLASS_REMOTE_WAKE_CTRL 0X4 -#define CLASS_AOAC_BLOBAL_INFO 0X04 +#define CLASS_AOAC_GLOBAL_INFO 0X04 #define CLASS_AOAC_RSVD_PAGE 0X04 #define CLASS_AOAC_RSVD_PAGE2 0X04 #define CLASS_D0_SCAN_OFFLOAD_INFO 0X04 #define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04 #define CLASS_AOAC_RSVD_PAGE3 0X04 -#define ORIGINAL_H2C_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define ORIGINAL_H2C_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define ORIGINAL_H2C_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define ORIGINAL_H2C_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define ORIGINAL_H2C_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define ORIGINAL_H2C_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define ORIGINAL_H2C_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define ORIGINAL_H2C_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define ORIGINAL_H2C_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define H2C2H_LB_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define H2C2H_LB_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define H2C2H_LB_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define H2C2H_LB_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define H2C2H_LB_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define H2C2H_LB_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define H2C2H_LB_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define H2C2H_LB_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define H2C2H_LB_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -87,9 +104,9 @@ #define H2C2H_LB_GET_PAYLOAD2(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 32) #define H2C2H_LB_SET_PAYLOAD2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 32, __Value) #define H2C2H_LB_SET_PAYLOAD2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 32, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define D0_SCAN_OFFLOAD_CTRL_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -117,9 +134,9 @@ #define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) #define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) #define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RSVD_PAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define RSVD_PAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define RSVD_PAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define RSVD_PAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define RSVD_PAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define RSVD_PAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -144,9 +161,9 @@ #define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) #define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) #define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define MEDIA_STATUS_RPT_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define MEDIA_STATUS_RPT_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define MEDIA_STATUS_RPT_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define MEDIA_STATUS_RPT_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define MEDIA_STATUS_RPT_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define MEDIA_STATUS_RPT_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define MEDIA_STATUS_RPT_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define MEDIA_STATUS_RPT_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define MEDIA_STATUS_RPT_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -162,9 +179,9 @@ #define MEDIA_STATUS_RPT_GET_MACID_END(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) #define MEDIA_STATUS_RPT_SET_MACID_END(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) #define MEDIA_STATUS_RPT_SET_MACID_END_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define KEEP_ALIVE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define KEEP_ALIVE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define KEEP_ALIVE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define KEEP_ALIVE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define KEEP_ALIVE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define KEEP_ALIVE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define KEEP_ALIVE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define KEEP_ALIVE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define KEEP_ALIVE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -180,9 +197,9 @@ #define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) #define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) #define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define DISCONNECT_DECISION_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define DISCONNECT_DECISION_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define DISCONNECT_DECISION_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define DISCONNECT_DECISION_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define DISCONNECT_DECISION_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define DISCONNECT_DECISION_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define DISCONNECT_DECISION_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define DISCONNECT_DECISION_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define DISCONNECT_DECISION_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -207,9 +224,9 @@ #define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) #define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) #define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AP_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define AP_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define AP_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define AP_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define AP_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AP_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define AP_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define AP_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define AP_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -270,9 +287,9 @@ #define AP_OFFLOAD_GET_LEN_IV_GRP(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) #define AP_OFFLOAD_SET_LEN_IV_GRP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) #define AP_OFFLOAD_SET_LEN_IV_GRP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define BCN_RSVDPAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define BCN_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define BCN_RSVDPAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define BCN_RSVDPAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define BCN_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define BCN_RSVDPAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define BCN_RSVDPAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define BCN_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define BCN_RSVDPAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -291,9 +308,9 @@ #define BCN_RSVDPAGE_GET_LOC_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) #define BCN_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) #define BCN_RSVDPAGE_SET_LOC_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define PROBE_RSP_RSVDPAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PROBE_RSP_RSVDPAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define PROBE_RSP_RSVDPAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define PROBE_RSP_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define PROBE_RSP_RSVDPAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -312,9 +329,9 @@ #define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) #define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) #define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define SET_PWR_MODE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define SET_PWR_MODE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define SET_PWR_MODE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define SET_PWR_MODE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define SET_PWR_MODE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define SET_PWR_MODE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define SET_PWR_MODE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define SET_PWR_MODE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define SET_PWR_MODE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -336,6 +353,12 @@ #define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 1) #define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 1, __Value) #define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 1, __Value) +#define SET_PWR_MODE_GET_BCN_EARLY_RPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 2, 1) +#define SET_PWR_MODE_SET_BCN_EARLY_RPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 2, 1, __Value) +#define SET_PWR_MODE_SET_BCN_EARLY_RPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 2, 1, __Value) +#define SET_PWR_MODE_GET_PORT_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 5, 3) +#define SET_PWR_MODE_SET_PORT_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 5, 3, __Value) +#define SET_PWR_MODE_SET_PORT_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 5, 3, __Value) #define SET_PWR_MODE_GET_PWR_STATE(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) #define SET_PWR_MODE_SET_PWR_STATE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) #define SET_PWR_MODE_SET_PWR_STATE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) @@ -369,9 +392,9 @@ #define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 28, 4) #define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 28, 4, __Value) #define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 28, 4, __Value) -#define PS_TUNING_PARA_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define PS_TUNING_PARA_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define PS_TUNING_PARA_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define PS_TUNING_PARA_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define PS_TUNING_PARA_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PS_TUNING_PARA_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define PS_TUNING_PARA_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define PS_TUNING_PARA_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define PS_TUNING_PARA_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -387,9 +410,9 @@ #define PS_TUNING_PARA_GET_ADOPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) #define PS_TUNING_PARA_SET_ADOPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) #define PS_TUNING_PARA_SET_ADOPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define PS_TUNING_PARA_II_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define PS_TUNING_PARA_II_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define PS_TUNING_PARA_II_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define PS_TUNING_PARA_II_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define PS_TUNING_PARA_II_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PS_TUNING_PARA_II_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define PS_TUNING_PARA_II_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define PS_TUNING_PARA_II_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define PS_TUNING_PARA_II_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -402,18 +425,18 @@ #define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) #define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) #define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define PS_LPS_PARA_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define PS_LPS_PARA_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define PS_LPS_PARA_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define PS_LPS_PARA_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define PS_LPS_PARA_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PS_LPS_PARA_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define PS_LPS_PARA_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define PS_LPS_PARA_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define PS_LPS_PARA_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) #define PS_LPS_PARA_GET_LPS_CONTROL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) #define PS_LPS_PARA_SET_LPS_CONTROL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) #define PS_LPS_PARA_SET_LPS_CONTROL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define P2P_PS_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define P2P_PS_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define P2P_PS_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define P2P_PS_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define P2P_PS_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define P2P_PS_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define P2P_PS_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define P2P_PS_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define P2P_PS_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -438,18 +461,18 @@ #define P2P_PS_OFFLOAD_GET_DISCOVERY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1) #define P2P_PS_OFFLOAD_SET_DISCOVERY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value) #define P2P_PS_OFFLOAD_SET_DISCOVERY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value) -#define PS_SCAN_EN_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define PS_SCAN_EN_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define PS_SCAN_EN_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define PS_SCAN_EN_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define PS_SCAN_EN_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PS_SCAN_EN_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define PS_SCAN_EN_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define PS_SCAN_EN_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define PS_SCAN_EN_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) #define PS_SCAN_EN_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) #define PS_SCAN_EN_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) #define PS_SCAN_EN_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define SAP_PS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define SAP_PS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define SAP_PS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define SAP_PS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define SAP_PS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define SAP_PS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define SAP_PS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define SAP_PS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define SAP_PS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -468,9 +491,9 @@ #define SAP_PS_GET_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) #define SAP_PS_SET_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) #define SAP_PS_SET_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define INACTIVE_PS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define INACTIVE_PS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define INACTIVE_PS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define INACTIVE_PS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define INACTIVE_PS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define INACTIVE_PS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define INACTIVE_PS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define INACTIVE_PS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define INACTIVE_PS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -486,9 +509,9 @@ #define INACTIVE_PS_GET_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) #define INACTIVE_PS_SET_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) #define INACTIVE_PS_SET_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define MACID_CFG_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define MACID_CFG_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define MACID_CFG_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define MACID_CFG_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define MACID_CFG_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define MACID_CFG_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define MACID_CFG_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define MACID_CFG_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define MACID_CFG_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -498,6 +521,9 @@ #define MACID_CFG_GET_RATE_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 5) #define MACID_CFG_SET_RATE_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 5, __Value) #define MACID_CFG_SET_RATE_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 5, __Value) +#define MACID_CFG_GET_INIT_RATE_LV(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 21, 2) +#define MACID_CFG_SET_INIT_RATE_LV(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 21, 2, __Value) +#define MACID_CFG_SET_INIT_RATE_LV_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 21, 2, __Value) #define MACID_CFG_GET_SGI(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 23, 1) #define MACID_CFG_SET_SGI(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 23, 1, __Value) #define MACID_CFG_SET_SGI_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 23, 1, __Value) @@ -531,9 +557,9 @@ #define MACID_CFG_GET_RATE_MASK31_24(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) #define MACID_CFG_SET_RATE_MASK31_24(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) #define MACID_CFG_SET_RATE_MASK31_24_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define TXBF_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define TXBF_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define TXBF_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define TXBF_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define TXBF_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define TXBF_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define TXBF_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define TXBF_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define TXBF_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -546,9 +572,9 @@ #define TXBF_GET_PERIOD_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) #define TXBF_SET_PERIOD_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) #define TXBF_SET_PERIOD_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define RSSI_SETTING_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define RSSI_SETTING_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define RSSI_SETTING_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define RSSI_SETTING_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define RSSI_SETTING_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define RSSI_SETTING_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define RSSI_SETTING_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define RSSI_SETTING_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define RSSI_SETTING_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -561,9 +587,9 @@ #define RSSI_SETTING_GET_RA_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) #define RSSI_SETTING_SET_RA_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) #define RSSI_SETTING_SET_RA_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AP_REQ_TXRPT_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define AP_REQ_TXRPT_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define AP_REQ_TXRPT_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define AP_REQ_TXRPT_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define AP_REQ_TXRPT_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define AP_REQ_TXRPT_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define AP_REQ_TXRPT_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -579,9 +605,9 @@ #define AP_REQ_TXRPT_GET_RTY_CNT_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 25, 1) #define AP_REQ_TXRPT_SET_RTY_CNT_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 25, 1, __Value) #define AP_REQ_TXRPT_SET_RTY_CNT_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 25, 1, __Value) -#define INIT_RATE_COLLECTION_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define INIT_RATE_COLLECTION_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define INIT_RATE_COLLECTION_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define INIT_RATE_COLLECTION_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define INIT_RATE_COLLECTION_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define INIT_RATE_COLLECTION_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define INIT_RATE_COLLECTION_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define INIT_RATE_COLLECTION_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define INIT_RATE_COLLECTION_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -606,9 +632,9 @@ #define INIT_RATE_COLLECTION_GET_STA7_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) #define INIT_RATE_COLLECTION_SET_STA7_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) #define INIT_RATE_COLLECTION_SET_STA7_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define IQK_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define IQK_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define IQK_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define IQK_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define IQK_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define IQK_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define IQK_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define IQK_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define IQK_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -621,9 +647,24 @@ #define IQK_OFFLOAD_GET_EXTPALNA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) #define IQK_OFFLOAD_SET_EXTPALNA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) #define IQK_OFFLOAD_SET_EXTPALNA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define RA_PARA_ADJUST_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define RA_PARA_ADJUST_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define RA_PARA_ADJUST_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define MACID_CFG_3SS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define MACID_CFG_3SS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define MACID_CFG_3SS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define MACID_CFG_3SS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define MACID_CFG_3SS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define MACID_CFG_3SS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define MACID_CFG_3SS_GET_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define MACID_CFG_3SS_SET_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define MACID_CFG_3SS_SET_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define MACID_CFG_3SS_GET_RATE_MASK_39_32(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_39_32(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define MACID_CFG_3SS_SET_RATE_MASK_39_32_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define MACID_CFG_3SS_GET_RATE_MASK_47_40(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_47_40(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) +#define MACID_CFG_3SS_SET_RATE_MASK_47_40_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) +#define RA_PARA_ADJUST_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define RA_PARA_ADJUST_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define RA_PARA_ADJUST_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define RA_PARA_ADJUST_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define RA_PARA_ADJUST_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define RA_PARA_ADJUST_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -645,9 +686,9 @@ #define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) #define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) #define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define WWLAN_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define WWLAN_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define WWLAN_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define WWLAN_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define WWLAN_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define WWLAN_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define WWLAN_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define WWLAN_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define WWLAN_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -699,9 +740,9 @@ #define WWLAN_GET_GPIO_DURATION_MS(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 10, 1) #define WWLAN_SET_GPIO_DURATION_MS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 10, 1, __Value) #define WWLAN_SET_GPIO_DURATION_MS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 10, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define REMOTE_WAKE_CTRL_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define REMOTE_WAKE_CTRL_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define REMOTE_WAKE_CTRL_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define REMOTE_WAKE_CTRL_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define REMOTE_WAKE_CTRL_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define REMOTE_WAKE_CTRL_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define REMOTE_WAKE_CTRL_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define REMOTE_WAKE_CTRL_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -747,21 +788,21 @@ #define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 29, 1) #define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 29, 1, __Value) #define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 29, 1, __Value) -#define AOAC_BLOBAL_INFO_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define AOAC_BLOBAL_INFO_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define AOAC_BLOBAL_INFO_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) -#define AOAC_BLOBAL_INFO_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AOAC_BLOBAL_INFO_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_BLOBAL_INFO_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_BLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define AOAC_BLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_BLOBAL_INFO_SET_PAIR_WISE_ENC_ALG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_BLOBAL_INFO_GET_GROUP_ENC_ALG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define AOAC_BLOBAL_INFO_SET_GROUP_ENC_ALG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_BLOBAL_INFO_SET_GROUP_ENC_ALG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define AOAC_RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define AOAC_RSVD_PAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define AOAC_GLOBAL_INFO_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define AOAC_GLOBAL_INFO_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_GLOBAL_INFO_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_GLOBAL_INFO_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define AOAC_GLOBAL_INFO_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_GLOBAL_INFO_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_RSVD_PAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define AOAC_RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_RSVD_PAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define AOAC_RSVD_PAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define AOAC_RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define AOAC_RSVD_PAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -786,9 +827,9 @@ #define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) #define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) #define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define AOAC_RSVD_PAGE2_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define AOAC_RSVD_PAGE2_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define AOAC_RSVD_PAGE2_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define AOAC_RSVD_PAGE2_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_RSVD_PAGE2_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define AOAC_RSVD_PAGE2_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define AOAC_RSVD_PAGE2_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define AOAC_RSVD_PAGE2_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -813,18 +854,18 @@ #define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) #define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) #define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define D0_SCAN_OFFLOAD_INFO_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define D0_SCAN_OFFLOAD_INFO_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define D0_SCAN_OFFLOAD_INFO_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) #define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) #define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) #define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define CHANNEL_SWITCH_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) @@ -837,9 +878,9 @@ #define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) #define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) #define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE3_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4) -#define AOAC_RSVD_PAGE3_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value) -#define AOAC_RSVD_PAGE3_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value) +#define AOAC_RSVD_PAGE3_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define AOAC_RSVD_PAGE3_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_RSVD_PAGE3_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) #define AOAC_RSVD_PAGE3_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) #define AOAC_RSVD_PAGE3_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) #define AOAC_RSVD_PAGE3_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) diff --git a/hal/halmac/halmac_original_h2c_nic.h b/hal/halmac/halmac_original_h2c_nic.h index a42022d..b6ae5f0 100644 --- a/hal/halmac/halmac_original_h2c_nic.h +++ b/hal/halmac/halmac_original_h2c_nic.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_ #define _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_ #define CMD_ID_ORIGINAL_H2C 0X00 @@ -24,10 +39,11 @@ #define CMD_ID_AP_REQ_TXRPT 0X03 #define CMD_ID_INIT_RATE_COLLECTION 0X04 #define CMD_ID_IQK_OFFLOAD 0X05 -#define CMD_ID_RA_PARA_ADJUST 0X06 +#define CMD_ID_MACID_CFG_3SS 0X06 +#define CMD_ID_RA_PARA_ADJUST 0X07 #define CMD_ID_WWLAN 0X00 #define CMD_ID_REMOTE_WAKE_CTRL 0X01 -#define CMD_ID_AOAC_BLOBAL_INFO 0X02 +#define CMD_ID_AOAC_GLOBAL_INFO 0X02 #define CMD_ID_AOAC_RSVD_PAGE 0X03 #define CMD_ID_AOAC_RSVD_PAGE2 0X04 #define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05 @@ -48,30 +64,31 @@ #define CLASS_PS_TUNING_PARA_II 0X01 #define CLASS_PS_LPS_PARA 0X01 #define CLASS_P2P_PS_OFFLOAD 0X01 -#define CLASS_PS_SCAN_EN 0X0 -#define CLASS_SAP_PS 0X0 -#define CLASS_INACTIVE_PS 0X0 +#define CLASS_PS_SCAN_EN 0X1 +#define CLASS_SAP_PS 0X1 +#define CLASS_INACTIVE_PS 0X1 #define CLASS_MACID_CFG 0X2 #define CLASS_TXBF 0X2 #define CLASS_RSSI_SETTING 0X2 #define CLASS_AP_REQ_TXRPT 0X2 #define CLASS_INIT_RATE_COLLECTION 0X2 #define CLASS_IQK_OFFLOAD 0X2 +#define CLASS_MACID_CFG_3SS 0X2 #define CLASS_RA_PARA_ADJUST 0X02 #define CLASS_WWLAN 0X4 #define CLASS_REMOTE_WAKE_CTRL 0X4 -#define CLASS_AOAC_BLOBAL_INFO 0X04 +#define CLASS_AOAC_GLOBAL_INFO 0X04 #define CLASS_AOAC_RSVD_PAGE 0X04 #define CLASS_AOAC_RSVD_PAGE2 0X04 #define CLASS_D0_SCAN_OFFLOAD_INFO 0X04 #define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04 #define CLASS_AOAC_RSVD_PAGE3 0X04 -#define ORIGINAL_H2C_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define ORIGINAL_H2C_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define ORIGINAL_H2C_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define ORIGINAL_H2C_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define ORIGINAL_H2C_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define ORIGINAL_H2C_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define H2C2H_LB_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define H2C2H_LB_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define H2C2H_LB_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define H2C2H_LB_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define H2C2H_LB_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define H2C2H_LB_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define H2C2H_LB_GET_SEQ(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -80,8 +97,8 @@ #define H2C2H_LB_SET_PAYLOAD1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 16, __Value) #define H2C2H_LB_GET_PAYLOAD2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 32) #define H2C2H_LB_SET_PAYLOAD2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 32, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) @@ -100,8 +117,8 @@ #define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) #define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) #define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define RSVD_PAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define RSVD_PAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define RSVD_PAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define RSVD_PAGE_GET_LOC_PROBE_RSP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -118,8 +135,8 @@ #define RSVD_PAGE_SET_LOC_CTS2SELF(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) #define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) #define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define MEDIA_STATUS_RPT_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define MEDIA_STATUS_RPT_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define MEDIA_STATUS_RPT_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define MEDIA_STATUS_RPT_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define MEDIA_STATUS_RPT_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define MEDIA_STATUS_RPT_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define MEDIA_STATUS_RPT_GET_OP_MODE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) @@ -130,8 +147,8 @@ #define MEDIA_STATUS_RPT_SET_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) #define MEDIA_STATUS_RPT_GET_MACID_END(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) #define MEDIA_STATUS_RPT_SET_MACID_END(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define KEEP_ALIVE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define KEEP_ALIVE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define KEEP_ALIVE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define KEEP_ALIVE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define KEEP_ALIVE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define KEEP_ALIVE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define KEEP_ALIVE_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) @@ -142,8 +159,8 @@ #define KEEP_ALIVE_SET_PKT_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) #define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) #define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define DISCONNECT_DECISION_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define DISCONNECT_DECISION_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define DISCONNECT_DECISION_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define DISCONNECT_DECISION_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define DISCONNECT_DECISION_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define DISCONNECT_DECISION_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define DISCONNECT_DECISION_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) @@ -160,8 +177,8 @@ #define DISCONNECT_DECISION_SET_TRY_PKT_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) #define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) #define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define AP_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define AP_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define AP_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define AP_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define AP_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define AP_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define AP_OFFLOAD_GET_ON(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) @@ -202,8 +219,8 @@ #define AP_OFFLOAD_SET_LEN_IV_PAIR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) #define AP_OFFLOAD_GET_LEN_IV_GRP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) #define AP_OFFLOAD_SET_LEN_IV_GRP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define BCN_RSVDPAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define BCN_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define BCN_RSVDPAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define BCN_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define BCN_RSVDPAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define BCN_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define BCN_RSVDPAGE_GET_LOC_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -216,8 +233,8 @@ #define BCN_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) #define BCN_RSVDPAGE_GET_LOC_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) #define BCN_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define PROBE_RSP_RSVDPAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define PROBE_RSP_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -230,8 +247,8 @@ #define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) #define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) #define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define SET_PWR_MODE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define SET_PWR_MODE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define SET_PWR_MODE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define SET_PWR_MODE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define SET_PWR_MODE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define SET_PWR_MODE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define SET_PWR_MODE_GET_MODE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7) @@ -272,8 +289,8 @@ #define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 25, 3, __Value) #define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 28, 4) #define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 28, 4, __Value) -#define PS_TUNING_PARA_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define PS_TUNING_PARA_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define PS_TUNING_PARA_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define PS_TUNING_PARA_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define PS_TUNING_PARA_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define PS_TUNING_PARA_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define PS_TUNING_PARA_GET_BCN_TO_LIMIT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7) @@ -284,8 +301,8 @@ #define PS_TUNING_PARA_SET_PS_TIME_OUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 4, __Value) #define PS_TUNING_PARA_GET_ADOPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) #define PS_TUNING_PARA_SET_ADOPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define PS_TUNING_PARA_II_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define PS_TUNING_PARA_II_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define PS_TUNING_PARA_II_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define PS_TUNING_PARA_II_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define PS_TUNING_PARA_II_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define PS_TUNING_PARA_II_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7) @@ -294,14 +311,14 @@ #define PS_TUNING_PARA_II_SET_ADOPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) #define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) #define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define PS_LPS_PARA_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define PS_LPS_PARA_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define PS_LPS_PARA_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define PS_LPS_PARA_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define PS_LPS_PARA_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define PS_LPS_PARA_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define PS_LPS_PARA_GET_LPS_CONTROL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) #define PS_LPS_PARA_SET_LPS_CONTROL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define P2P_PS_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define P2P_PS_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define P2P_PS_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define P2P_PS_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define P2P_PS_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define P2P_PS_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) @@ -318,14 +335,14 @@ #define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value) #define P2P_PS_OFFLOAD_GET_DISCOVERY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1) #define P2P_PS_OFFLOAD_SET_DISCOVERY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value) -#define PS_SCAN_EN_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define PS_SCAN_EN_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define PS_SCAN_EN_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define PS_SCAN_EN_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define PS_SCAN_EN_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define PS_SCAN_EN_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define PS_SCAN_EN_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) #define PS_SCAN_EN_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define SAP_PS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define SAP_PS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define SAP_PS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define SAP_PS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define SAP_PS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define SAP_PS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define SAP_PS_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) @@ -338,8 +355,8 @@ #define SAP_PS_SET_MANUAL_32K(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) #define SAP_PS_GET_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) #define SAP_PS_SET_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define INACTIVE_PS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define INACTIVE_PS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define INACTIVE_PS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define INACTIVE_PS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define INACTIVE_PS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define INACTIVE_PS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define INACTIVE_PS_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) @@ -350,8 +367,8 @@ #define INACTIVE_PS_SET_FREQUENCY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) #define INACTIVE_PS_GET_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) #define INACTIVE_PS_SET_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define MACID_CFG_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define MACID_CFG_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define MACID_CFG_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define MACID_CFG_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define MACID_CFG_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define MACID_CFG_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define MACID_CFG_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -380,8 +397,8 @@ #define MACID_CFG_SET_RATE_MASK23_16(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) #define MACID_CFG_GET_RATE_MASK31_24(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) #define MACID_CFG_SET_RATE_MASK31_24(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define TXBF_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define TXBF_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define TXBF_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define TXBF_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define TXBF_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define TXBF_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define TXBF_GET_NDPA0_HEAD_PAGE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -390,8 +407,8 @@ #define TXBF_SET_NDPA1_HEAD_PAGE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) #define TXBF_GET_PERIOD_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) #define TXBF_SET_PERIOD_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define RSSI_SETTING_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define RSSI_SETTING_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define RSSI_SETTING_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define RSSI_SETTING_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define RSSI_SETTING_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define RSSI_SETTING_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define RSSI_SETTING_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -400,8 +417,8 @@ #define RSSI_SETTING_SET_RSSI(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 7, __Value) #define RSSI_SETTING_GET_RA_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) #define RSSI_SETTING_SET_RA_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define AP_REQ_TXRPT_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define AP_REQ_TXRPT_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define AP_REQ_TXRPT_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define AP_REQ_TXRPT_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define AP_REQ_TXRPT_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define AP_REQ_TXRPT_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define AP_REQ_TXRPT_GET_STA1_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -412,8 +429,8 @@ #define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value) #define AP_REQ_TXRPT_GET_RTY_CNT_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 25, 1) #define AP_REQ_TXRPT_SET_RTY_CNT_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 25, 1, __Value) -#define INIT_RATE_COLLECTION_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define INIT_RATE_COLLECTION_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define INIT_RATE_COLLECTION_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define INIT_RATE_COLLECTION_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define INIT_RATE_COLLECTION_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define INIT_RATE_COLLECTION_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define INIT_RATE_COLLECTION_GET_STA1_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -430,8 +447,8 @@ #define INIT_RATE_COLLECTION_SET_STA6_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) #define INIT_RATE_COLLECTION_GET_STA7_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) #define INIT_RATE_COLLECTION_SET_STA7_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define IQK_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define IQK_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define IQK_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define IQK_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define IQK_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define IQK_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define IQK_OFFLOAD_GET_CHANNEL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -440,8 +457,18 @@ #define IQK_OFFLOAD_SET_BWBAND(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) #define IQK_OFFLOAD_GET_EXTPALNA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) #define IQK_OFFLOAD_SET_EXTPALNA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define RA_PARA_ADJUST_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define RA_PARA_ADJUST_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define MACID_CFG_3SS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define MACID_CFG_3SS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define MACID_CFG_3SS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define MACID_CFG_3SS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define MACID_CFG_3SS_GET_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define MACID_CFG_3SS_SET_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define MACID_CFG_3SS_GET_RATE_MASK_39_32(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_39_32(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define MACID_CFG_3SS_GET_RATE_MASK_47_40(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_47_40(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) +#define RA_PARA_ADJUST_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define RA_PARA_ADJUST_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define RA_PARA_ADJUST_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define RA_PARA_ADJUST_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define RA_PARA_ADJUST_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -456,8 +483,8 @@ #define RA_PARA_ADJUST_SET_VALUE_BYTE1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) #define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) #define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define WWLAN_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define WWLAN_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define WWLAN_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define WWLAN_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define WWLAN_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define WWLAN_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define WWLAN_GET_FUNC_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) @@ -492,8 +519,8 @@ #define WWLAN_SET_HST2DEV_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 9, 1, __Value) #define WWLAN_GET_GPIO_DURATION_MS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 10, 1) #define WWLAN_SET_GPIO_DURATION_MS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 10, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define REMOTE_WAKE_CTRL_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define REMOTE_WAKE_CTRL_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define REMOTE_WAKE_CTRL_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define REMOTE_WAKE_CTRL_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define REMOTE_WAKE_CTRL_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) @@ -524,16 +551,16 @@ #define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 1, __Value) #define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 29, 1) #define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 29, 1, __Value) -#define AOAC_BLOBAL_INFO_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define AOAC_BLOBAL_INFO_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) -#define AOAC_BLOBAL_INFO_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AOAC_BLOBAL_INFO_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_BLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define AOAC_BLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_BLOBAL_INFO_GET_GROUP_ENC_ALG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define AOAC_BLOBAL_INFO_SET_GROUP_ENC_ALG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define AOAC_RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define AOAC_GLOBAL_INFO_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define AOAC_GLOBAL_INFO_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_GLOBAL_INFO_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define AOAC_GLOBAL_INFO_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_RSVD_PAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define AOAC_RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define AOAC_RSVD_PAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define AOAC_RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -550,8 +577,8 @@ #define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) #define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) #define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define AOAC_RSVD_PAGE2_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define AOAC_RSVD_PAGE2_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define AOAC_RSVD_PAGE2_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define AOAC_RSVD_PAGE2_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define AOAC_RSVD_PAGE2_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -568,14 +595,14 @@ #define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) #define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) #define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define D0_SCAN_OFFLOAD_INFO_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define D0_SCAN_OFFLOAD_INFO_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) #define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) @@ -584,8 +611,8 @@ #define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) #define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) #define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE3_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4) -#define AOAC_RSVD_PAGE3_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value) +#define AOAC_RSVD_PAGE3_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define AOAC_RSVD_PAGE3_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) #define AOAC_RSVD_PAGE3_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) #define AOAC_RSVD_PAGE3_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) #define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) diff --git a/hal/halmac/halmac_pcie_reg.h b/hal/halmac/halmac_pcie_reg.h index 8808e7b..a8a4ee4 100644 --- a/hal/halmac/halmac_pcie_reg.h +++ b/hal/halmac/halmac_pcie_reg.h @@ -1,8 +1,30 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __HALMAC_PCIE_REG_H__ #define __HALMAC_PCIE_REG_H__ +/* PCIE PHY register */ +#define CLKCAL_CTRL_PHYPARA 0x00 +#define CLKCAL_SET_PHYPARA 0x20 +#define CLKCAL_TRG_VAL_PHYPARA 0x21 +#define PCIE_L1_BACKDOOR 0x719 - - +/* PCIE MAC register */ +#define LINK_CTRL2_REG_OFFSET 0xA0 +#define GEN2_CTRL_OFFSET 0x80C +#define LINK_STATUS_REG_OFFSET 0x82 #endif/* __HALMAC_PCIE_REG_H__ */ diff --git a/hal/halmac/halmac_pwr_seq_cmd.h b/hal/halmac/halmac_pwr_seq_cmd.h index 0367fe3..5834f01 100644 --- a/hal/halmac/halmac_pwr_seq_cmd.h +++ b/hal/halmac/halmac_pwr_seq_cmd.h @@ -1,10 +1,25 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef HALMAC_POWER_SEQUENCE_CMD #define HALMAC_POWER_SEQUENCE_CMD #include "halmac_2_platform.h" #include "halmac_type.h" -#define HALMAC_POLLING_READY_TIMEOUT_COUNT 10000 +#define HALMAC_POLLING_READY_TIMEOUT_COUNT 20000 /* * The value of cmd : 4 bits @@ -64,14 +79,14 @@ #define HALMAC_PWR_INTF_SDIO_MSK BIT(0) #define HALMAC_PWR_INTF_USB_MSK BIT(1) #define HALMAC_PWR_INTF_PCI_MSK BIT(2) -#define HALMAC_PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) +#define HALMAC_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) /* * The value of fab_msk : 4 bits */ #define HALMAC_PWR_FAB_TSMC_MSK BIT(0) #define HALMAC_PWR_FAB_UMC_MSK BIT(1) -#define HALMAC_PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) +#define HALMAC_PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) /* * The value of cut_msk : 8 bits diff --git a/hal/halmac/halmac_reg2.h b/hal/halmac/halmac_reg2.h index 9f0c31c..f04e7bc 100644 --- a/hal/halmac/halmac_reg2.h +++ b/hal/halmac/halmac_reg2.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __HALMAC_COM_REG_H__ #define __HALMAC_COM_REG_H__ /*-------------------------Modification Log----------------------------------- @@ -16,21 +31,21 @@ -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_SYS_ISO_CTRL 0x0000 #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_TX_CTRL 0x10250000 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_SYS_FUNC_EN 0x0002 #define REG_SYS_PW_CTRL 0x0004 @@ -43,42 +58,42 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_HIMR 0x10250014 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_SYS_SWR_CTRL3 0x0018 #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_HISR 0x10250018 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_RSV_CTRL 0x001C #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_RX_REQ_LEN 0x1025001C #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_RF_CTRL 0x001F @@ -92,56 +107,56 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_AFE_LDO_CTRL 0x0020 #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_FREE_TXPG 0x10250020 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_AFE_CTRL1 0x0024 #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_FREE_TXPG2 0x10250024 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_AFE_CTRL2 0x0028 #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_AFE_CTRL3 0x002C #define REG_EFUSE_CTRL 0x0030 @@ -149,14 +164,14 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_HTSFR_INFO 0x10250030 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_LDO_EFUSE_CTRL 0x0034 #define REG_PWR_OPTION_CTRL 0x0038 @@ -164,7 +179,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_HCPWM1_V2 0x10250038 #define REG_SDIO_HCPWM2_V2 0x1025003A @@ -172,7 +187,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_CAL_TIMER 0x003C #define REG_ACLK_MON 0x003E @@ -181,28 +196,28 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_INDIRECT_REG_CFG 0x10250040 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_GPIO_PIN_CTRL 0x0044 #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_INDIRECT_REG_DATA 0x10250044 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_GPIO_INTM 0x0048 #define REG_LED_CFG 0x004C @@ -215,35 +230,35 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_H2C 0x10250060 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PAD_CTRL1 0x0064 #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_C2H 0x10250064 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_WL_BT_PWR_CTRL 0x0068 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_SDM_DEBUG 0x006C @@ -257,7 +272,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_SYS_SDIO_CTRL 0x0070 @@ -271,14 +286,14 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_HCI_OPT_CTRL 0x0074 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_AFE_CTRL4 0x0078 @@ -292,7 +307,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_LDO_SWR_CTRL 0x007C @@ -306,14 +321,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_MCUFW_CTRL 0x0080 #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_HRPWM1 0x10250080 #define REG_SDIO_HRPWM2 0x10250082 @@ -321,14 +336,14 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_MCU_TST_CFG 0x0084 #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_HPS_CLKR 0x10250084 #define REG_SDIO_BUS_CTRL 0x10250085 @@ -336,35 +351,35 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_HSUS_CTRL 0x10250086 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_HMEBOX_E0_E1 0x0088 #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_RESPONSE_TIMER 0x10250088 #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_CMD_CRC 0x1025008A #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_HMEBOX_E2_E3 0x008C #define REG_WLLPS_CTRL 0x0090 @@ -372,7 +387,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_HSISR 0x10250090 #define REG_SDIO_HSIMR 0x10250091 @@ -380,14 +395,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_AFE_CTRL5 0x0094 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_GPIO_DEBOUNCE_CTRL 0x0098 #define REG_RPWM2 0x009C @@ -396,28 +411,28 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_AFE_CTRL6 0x00A4 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PMC_DBG_CTRL1 0x00A8 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_AFE_CTRL7 0x00AC #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_HIMR0 0x00B0 #define REG_HISR0 0x00B4 @@ -428,7 +443,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_ERR_RPT 0x102500C0 #define REG_SDIO_CMD_ERRCNT 0x102500C1 @@ -437,14 +452,14 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PAD_CTRL2 0x00C4 #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_CMD_ERR_CONTENT 0x102500C4 @@ -458,7 +473,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SDIO_CRC_ERR_IDX 0x102500C9 #define REG_SDIO_DATA_CRC 0x102500CA @@ -467,7 +482,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PMC_DBG_CTRL2 0x00CC #define REG_BIST_CTRL 0x00D0 @@ -477,7 +492,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_AFE_CTRL8 0x00DC @@ -491,7 +506,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_USB_SIE_INTF 0x00E0 #define REG_PCIE_MIO_INTF 0x00E4 @@ -500,7 +515,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_WLRF1 0x00EC @@ -514,7 +529,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_SYS_CFG1 0x00F0 #define REG_SYS_STATUS1 0x00F4 @@ -525,14 +540,14 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PKT_BUFF_ACCESS_CTRL 0x0106 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_TSF_CLK_STATE 0x0108 #define REG_TXDMA_PQ_MAP 0x010C @@ -541,7 +556,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PTA_I2C_MBOX 0x0118 @@ -562,7 +577,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_RXFF_BNDY 0x011C @@ -576,7 +591,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_FE1IMR 0x0120 @@ -590,14 +605,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_FE1ISR 0x0124 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_CPWM 0x012C #define REG_FWIMR 0x0130 @@ -630,14 +645,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_MBIST_FAIL_NRML 0x017C #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_AES_DECRPT_DATA 0x0180 #define REG_AES_DECRPT_CFG 0x0184 @@ -652,7 +667,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_TMETER 0x0190 #define REG_OSC_32K_CTRL 0x0194 @@ -662,6 +677,15 @@ #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_C2HEVT_1 0x01A4 +#define REG_C2HEVT_2 0x01A8 +#define REG_C2HEVT_3 0x01AC + +#endif + + #if (HALMAC_8814A_SUPPORT) #define REG_TC7_CTRL 0x01B0 @@ -670,9 +694,22 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_SW_DEFINED_PAGE1 0x01B8 + +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_SW_DEFINED_PAGE2 0x01BC + +#endif + + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + #define REG_MCUTST_I 0x01C0 #define REG_MCUTST_II 0x01C4 #define REG_FMETHR 0x01C8 @@ -693,14 +730,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_LLT_INIT_ADDR 0x01E4 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_BB_ACCESS_CTRL 0x01E8 #define REG_BB_ACCESS_DATA 0x01EC @@ -719,7 +756,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_FIFOPAGE_CTRL_1 0x0200 @@ -733,7 +770,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_FIFOPAGE_CTRL_2 0x0204 @@ -747,14 +784,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_AUTO_LLT_V1 0x0208 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_TXDMA_OFFSET_CHK 0x020C #define REG_TXDMA_STATUS 0x0210 @@ -769,14 +806,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_TX_DMA_DBG 0x0214 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_TQPNT1 0x0218 #define REG_TQPNT2 0x021C @@ -791,7 +828,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_TQPNT3 0x0220 @@ -805,7 +842,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_TQPNT4 0x0224 @@ -819,7 +856,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_RQPN_CTRL_1 0x0228 #define REG_RQPN_CTRL_2 0x022C @@ -832,7 +869,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_H2C_HEAD 0x0244 #define REG_H2C_TAIL 0x0248 @@ -843,7 +880,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_RXDMA_AGG_PG_TH 0x0280 #define REG_RXPKT_NUM 0x0284 @@ -855,7 +892,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_FWFF_C2H 0x0298 #define REG_FWFF_CTRL 0x029C @@ -871,7 +908,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_PCIE_CTRL 0x0300 @@ -892,7 +929,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_INT_MIG 0x0304 #define REG_BCNQ_TXBD_DESA 0x0308 @@ -944,14 +981,14 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_DBG_SEL_V1 0x03D8 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PCIE_HRPWM1_V1 0x03D9 @@ -965,7 +1002,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PCIE_HCPWM1_V1 0x03DA @@ -979,7 +1016,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_PCIE_CTRL2 0x03DB @@ -1000,7 +1037,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PCIE_HRPWM2_V1 0x03DC @@ -1014,7 +1051,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PCIE_HCPWM2_V1 0x03DE @@ -1028,7 +1065,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PCIE_H2C_MSG_V1 0x03E0 @@ -1042,7 +1079,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PCIE_C2H_MSG_V1 0x03E4 @@ -1056,7 +1093,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_DBI_WDATA_V1 0x03E8 @@ -1070,7 +1107,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_DBI_RDATA_V1 0x03EC @@ -1084,7 +1121,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_DBI_FLAG_V1 0x03F0 @@ -1105,13 +1142,20 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_MDIO_V1 0x03F4 #endif +#if (HALMAC_8192E_SUPPORT) + +#define REG_MDIO2_V1 0x03F8 + +#endif + + #if (HALMAC_8197F_SUPPORT) #define REG_WDT_CFG 0x03F8 @@ -1119,7 +1163,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_PCIE_MIX_CFG 0x03F8 @@ -1133,7 +1177,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_HCI_MIX_CFG 0x03FC @@ -1147,7 +1191,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_Q0_INFO 0x0400 #define REG_Q1_INFO 0x0404 @@ -1170,7 +1214,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_DATAFB_SEL 0x0423 @@ -1184,7 +1228,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BCNQ_BDNY_V1 0x0424 @@ -1198,7 +1242,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_LIFETIME_EN 0x0426 @@ -1212,7 +1256,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_SPEC_SIFS 0x0428 #define REG_RETRY_LIMIT 0x042A @@ -1234,7 +1278,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_AMPDU_MAX_TIME_V1 0x0455 @@ -1248,7 +1292,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BCNQ1_BDNY_V1 0x0456 @@ -1262,7 +1306,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_AMPDU_MAX_LENGTH 0x0458 #define REG_ACQ_STOP 0x045C @@ -1277,14 +1321,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_NDPA_RATE 0x045D #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_TX_HANG_CTRL 0x045E #define REG_NDPA_OPT_CTRL 0x045F @@ -1299,7 +1343,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_RD_RESP_PKT_TH 0x0463 #define REG_CMDQ_INFO 0x0464 @@ -1311,7 +1355,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WMAC_LBK_BUF_HD_V1 0x0478 #define REG_MGQ_BDNY_V1 0x047A @@ -1319,7 +1363,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_TXRPT_CTRL 0x047C #define REG_INIRTS_RATE_SEL 0x0480 @@ -1344,21 +1388,21 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_POWER_STAGE1 0x04B4 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_POWER_STAGE2 0x04B8 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC #define REG_PKT_LIFE_TIME 0x04C0 @@ -1375,7 +1419,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_HW_SEQ0 0x04D8 #define REG_HW_SEQ1 0x04DA @@ -1399,14 +1443,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_NULL_PKT_STATUS_V1 0x04E0 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PTCL_ERR_STATUS 0x04E2 @@ -1420,7 +1464,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_NULL_PKT_STATUS_EXTEND 0x04E3 @@ -1434,14 +1478,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_VIDEO_ENHANCEMENT_FUN 0x04E4 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BT_POLLUTE_PKT_CNT 0x04E8 #define REG_PTCL_DBG 0x04EC @@ -1463,7 +1507,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_CPUMGQ_TIMER_CTRL2 0x04F4 @@ -1477,7 +1521,7 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_DUMMY_PAGE4_V1 0x04FC #define REG_MOREDATA 0x04FE @@ -1485,7 +1529,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_EDCA_VO_PARAM 0x0500 #define REG_EDCA_VI_PARAM 0x0504 @@ -1510,7 +1554,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BAR_TX_CTRL 0x0530 @@ -1525,7 +1569,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_TBTT_PROHIBIT 0x0540 #define REG_P2PPS_STATE 0x0543 @@ -1543,7 +1587,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_BCN_CTRL 0x0550 @@ -1557,14 +1601,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BCN_CTRL_CLINT0 0x0551 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_MBID_NUM 0x0552 #define REG_DUAL_TSF_RST 0x0553 @@ -1581,6 +1625,13 @@ #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_TSFTR_1 0x0564 + +#endif + + #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_TSFTR1 0x0568 @@ -1588,13 +1639,20 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_FREERUN_CNT 0x0568 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_FREERUN_CNT_1 0x056C + +#endif + + #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_ATIMWND1 0x0570 @@ -1602,21 +1660,21 @@ #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_ATIMWND1_V1 0x0570 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_TBTT_PROHIBIT_INFRA 0x0571 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_CTWND 0x0572 #define REG_BCNIVLCUNT 0x0573 @@ -1626,7 +1684,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_TXCMD_TIMEOUT_PERIOD 0x0576 #define REG_MISC_CTRL 0x0577 @@ -1637,14 +1695,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_EXTEND_CTRL 0x057B #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_P2PPS1_SPEC_STATE 0x057C #define REG_P2PPS1_STATE 0x057D @@ -1661,7 +1719,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_PS_TIMER0 0x0580 @@ -1675,7 +1733,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_PS_TIMER1 0x0584 @@ -1689,14 +1747,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_PS_TIMER2 0x0588 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_TBTT_CTN_AREA 0x058C #define REG_FORCE_BCN_IFS 0x058E @@ -1718,7 +1776,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_ATIMWND2 0x05A0 #define REG_ATIMWND3 0x05A1 @@ -1741,7 +1799,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_EARLY_128US 0x05B1 #define REG_P2PPS1_CTRL 0x05B2 @@ -1755,7 +1813,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_ACMHWCTRL 0x05C0 #define REG_ACMRSTCTRL 0x05C1 @@ -1770,6 +1828,15 @@ #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_NOA_PARAM_1 0x05E4 +#define REG_NOA_PARAM_2 0x05E8 +#define REG_NOA_PARAM_3 0x05EC + +#endif + + #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_NOA_SUBIE 0x05ED @@ -1777,7 +1844,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_P2P_RST 0x05F0 #define REG_SCHEDULER_RST 0x05F1 @@ -1785,7 +1852,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_SCH_TXCMD 0x05F8 #define REG_PAGE5_DUMMY 0x05FC @@ -1794,28 +1861,28 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WMAC_FWPKT_CR 0x0601 #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) #define REG_FW_STS_FILTER 0x0602 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BWOPMODE 0x0603 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_TCR 0x0604 #define REG_RCR 0x0608 @@ -1838,7 +1905,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WMAC_TCR_TSFT_OFS 0x0630 #define REG_UDF_THSD 0x0632 @@ -1854,7 +1921,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_STMP_THSD 0x0634 #define REG_WMAC_TXTIMEOUT 0x0635 @@ -1863,21 +1930,21 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_USTIME_EDCA 0x0638 #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) #define REG_ACKTO_CCK 0x0639 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_MAC_SPEC_SIFS 0x063A #define REG_RESP_SIFS_CCK 0x063C @@ -1889,7 +1956,7 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) #define REG_RPFM_MAP0 0x0644 #define REG_RPFM_MAP1 0x0646 @@ -1899,7 +1966,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_NAV_CTRL 0x0650 #define REG_BACAMCMD 0x0654 @@ -1909,21 +1976,28 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WMAC_BACAM_RPMEN 0x0661 #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_TX_RX 0x0662 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_WMAC_BITMAP_CTL 0x0663 + +#endif + + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_RXERR_RPT 0x0664 #define REG_WMAC_TRXPTCL_CTL 0x0668 @@ -1936,7 +2010,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_RXFILTER_CATEGORY_1 0x0682 #define REG_RXFILTER_ACTION_1 0x0683 @@ -1952,21 +2026,21 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_WOW_CTRL 0x0690 #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_NAN_RX_TSF_FILTER 0x0691 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_PS_RX_INFO 0x0692 #define REG_WMMPS_UAPSD_TID 0x0693 @@ -1982,7 +2056,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WKFMCAM_CMD 0x0698 #define REG_WKFMCAM_RWD 0x069C @@ -1990,7 +2064,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_RXFLTMAP0 0x06A0 #define REG_RXFLTMAP1 0x06A2 @@ -2000,7 +2074,7 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_FLC_RPC 0x06AC #define REG_FLC_RPCT 0x06AD @@ -2010,21 +2084,21 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_RXPKTMON_CTRL 0x06B0 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_STATE_MON 0x06B4 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_ERROR_MON 0x06B8 #define REG_SEARCH_MACID 0x06BC @@ -2032,14 +2106,14 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_BT_COEX_TABLE 0x06C0 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_RXCMD_0 0x06D0 #define REG_RXCMD_1 0x06D4 @@ -2047,21 +2121,21 @@ #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_WMAC_RESP_TXINFO 0x06D8 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BBPSF_CTRL 0x06DC #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_P2P_RX_BCN_NOA 0x06E0 #define REG_ASSOCIATED_BFMER0_INFO 0x06E4 @@ -2074,14 +2148,28 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_MACID1_1 0x0704 + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BSSID1 0x0708 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_BSSID1_1 0x070C + +#endif + + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_BCN_PSR_RPT1 0x0710 #define REG_ASSOCIATED_BFMEE_SEL 0x0714 @@ -2100,7 +2188,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BEAMFORMING_INFO_NSARP_V1 0x0728 @@ -2114,7 +2202,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BEAMFORMING_INFO_NSARP 0x072C @@ -2128,28 +2216,38 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_IPV6 0x0730 +#define REG_IPV6_1 0x0734 +#define REG_IPV6_2 0x0738 +#define REG_IPV6_3 0x073C + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WMAC_SWAES_CFG 0x0760 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BT_COEX_V2 0x0762 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_BT_COEX 0x0764 @@ -2163,13 +2261,20 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WLAN_ACT_MASK_CTRL 0x0768 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_WLAN_ACT_MASK_CTRL_1 0x076C + +#endif + + #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_BT_STATISTICS_CTRL 0x076E @@ -2178,20 +2283,27 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_BT_ACT_STATISTICS 0x0770 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_BT_ACT_STATISTICS_1 0x0774 + +#endif + + #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_BT_STATISTICS_OTH_CTRL 0x0778 @@ -2199,7 +2311,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778 @@ -2213,7 +2325,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BT_STATUS_REPORT_REGISTER 0x077C @@ -2228,7 +2340,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780 @@ -2244,7 +2356,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784 @@ -2258,13 +2370,21 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 0x0788 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 0x078C + +#endif + + #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_BT_ISR_STA 0x078F @@ -2272,7 +2392,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F @@ -2286,7 +2406,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BT_TDMA_TIME_REGISTER 0x0790 @@ -2300,7 +2420,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BT_ACT_REGISTER 0x0794 @@ -2315,7 +2435,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_OBFF_CTRL_BASIC 0x0798 @@ -2329,7 +2449,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_OBFF_CTRL2_TIMER 0x079C @@ -2343,7 +2463,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_LTR_CTRL_BASIC 0x07A0 @@ -2357,7 +2477,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4 @@ -2371,7 +2491,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_LTR_IDLE_LATENCY_V1 0x07A8 #define REG_LTR_ACTIVE_LATENCY_V1 0x07AC @@ -2386,14 +2506,21 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0 #endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 0x07B4 + +#endif + + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) #define REG_WMAC_PKTCNT_RWD 0x07B8 #define REG_WMAC_PKTCNT_CTRL 0x07BC @@ -2401,21 +2528,29 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_IQ_DUMP 0x07C0 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_IQ_DUMP_1 0x07C4 +#define REG_IQ_DUMP_2 0x07C8 + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WMAC_FTM_CTL 0x07CC #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WMAC_IQ_MDPK_FUNC 0x07CE @@ -2436,21 +2571,29 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WMAC_OPTION_FUNCTION 0x07D0 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_WMAC_OPTION_FUNCTION_1 0x07D4 +#define REG_WMAC_OPTION_FUNCTION_2 0x07D8 + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_RX_FILTER_FUNCTION 0x07DA #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_NDP_SIG 0x07E0 #define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4 @@ -2465,6 +2608,13 @@ #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_TXCMD_INFO_FOR_RSP_PKT_1 0x07E8 + +#endif + + #if (HALMAC_8197F_SUPPORT) #define REG_SEC_OPT_V2 0x07EC @@ -2472,14 +2622,14 @@ #endif -#if (HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) #define REG_WSEC_OPTION 0x07EC #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_RTS_ADDRESS_0 0x07F0 @@ -2493,7 +2643,14 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_RTS_ADDRESS_0_1 0x07F4 + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_RTS_ADDRESS_1 0x07F8 @@ -2507,6 +2664,13 @@ #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_RTS_ADDRESS_1_1 0x07FC + +#endif + + #if (HALMAC_8822B_SUPPORT) #define REG__RPFM_MAP1 0x07FE @@ -2514,7 +2678,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SYS_CFG3 0x1000 #define REG_SYS_CFG4 0x1034 @@ -2522,21 +2686,21 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_SYS_CFG5 0x1070 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_CPU_DMEM_CON 0x1080 #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BOOT_REASON 0x1088 #define REG_NFCPAD_CTRL 0x10A8 @@ -2544,7 +2708,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_HIMR2 0x10B0 #define REG_HISR2 0x10B4 @@ -2565,7 +2729,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_H2C_PKT_READADDR 0x10D0 #define REG_H2C_PKT_WRITEADDR 0x10D4 @@ -2580,7 +2744,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_MEM_PWR_CRTL 0x10D8 @@ -2594,7 +2758,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_FW_DBG0 0x10E0 #define REG_FW_DBG1 0x10E4 @@ -2610,7 +2774,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_RXFF_PTR_V1 0x1118 #define REG_RXFF_WTR_V1 0x111C @@ -2618,7 +2782,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_FE2IMR 0x1120 #define REG_FE2ISR 0x1124 @@ -2637,7 +2801,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_TC7_CTRL_V1 0x1158 #define REG_TC8_CTRL_V1 0x115C @@ -2667,7 +2831,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_FT2IMR 0x11E0 #define REG_FT2ISR 0x11E4 @@ -2675,7 +2839,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_MSG2 0x11F0 #define REG_MSG3 0x11F4 @@ -2698,7 +2862,26 @@ #define REG_DDMA_CH4CTRL 0x1248 #define REG_DDMA_CH5SA 0x1250 #define REG_DDMA_CH5DA 0x1254 + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + #define REG_REG_DDMA_CH5CTRL 0x1258 + +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_DDMA_CH5CTRL 0x1258 + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + #define REG_DDMA_INT_MSK 0x12E0 #define REG_DDMA_CHSTATUS 0x12E8 #define REG_DDMA_CHKSUM 0x12F0 @@ -2707,7 +2890,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_STC_INT_CS 0x1300 #define REG_ST_INT_CFG 0x1304 @@ -2724,12 +2907,32 @@ #if (HALMAC_8197F_SUPPORT) #define REG_AXI_EXCEPT_CS 0x1350 + +#endif + + +#if (HALMAC_8822B_SUPPORT) + +#define REG_CHANGE_PCIE_SPEED 0x1350 + +#endif + + +#if (HALMAC_8197F_SUPPORT) + #define REG_AXI_EXCEPT_TIME 0x1354 #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8822B_SUPPORT) + +#define REG_OLD_DEHANG 0x13F4 + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_Q0_Q1_INFO 0x1400 #define REG_Q2_Q3_INFO 0x1404 @@ -2757,7 +2960,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_R_MACID_RELEASE_SUCCESS_0 0x1460 #define REG_R_MACID_RELEASE_SUCCESS_1 0x1464 @@ -2797,7 +3000,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_MU_TX_CTL 0x14C0 #define REG_MU_STA_GID_VLD 0x14C4 @@ -2807,7 +3010,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_CPUMGQ_TX_TIMER 0x1500 #define REG_PS_TIMER_A 0x1504 @@ -2822,7 +3025,7 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_BCN_PSR_RPT2 0x1600 #define REG_BCN_PSR_RPT3 0x1604 @@ -2838,10 +3041,68 @@ #endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_NOA_REPORT 0x1650 #define REG_PWRBIT_SETTING 0x1660 +#define REG_WMAC_MU_BF_OPTION 0x167C + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_WMAC_PAUSE_BB_CLR_TH 0x167D + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_WMAC_MU_ARB 0x167E +#define REG_WMAC_MU_OPTION 0x167F +#define REG_WMAC_MU_BF_CTL 0x1680 + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_WMAC_MU_BFRPT_PARA 0x1682 + +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_WMAC_MU_BIT_BFRPT_PARA 0x1682 + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684 +#define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686 +#define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688 +#define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A +#define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C +#define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E + +#endif + + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define REG_WMAC_BB_STOP_RX_COUNTER 0x1690 +#define REG_WMAC_PLCP_MONITOR 0x1694 +#define REG_WMAC_PLCP_MONITOR_MUTX 0x1698 + +#endif + + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + #define REG_TRANSMIT_ADDRSS_0 0x16A0 #define REG_TRANSMIT_ADDRSS_1 0x16A8 #define REG_TRANSMIT_ADDRSS_2 0x16B0 @@ -2851,7 +3112,7 @@ #endif -#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 diff --git a/hal/halmac/halmac_reg_8821c.h b/hal/halmac/halmac_reg_8821c.h index e49ef56..d7198fd 100644 --- a/hal/halmac/halmac_reg_8821c.h +++ b/hal/halmac/halmac_reg_8821c.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __INC_HALMAC_REG_8821C_H #define __INC_HALMAC_REG_8821C_H @@ -127,7 +142,11 @@ #define REG_OSC_32K_CTRL_8821C 0x0194 #define REG_32K_CAL_REG1_8821C 0x0198 #define REG_C2HEVT_8821C 0x01A0 +#define REG_C2HEVT_1_8821C 0x01A4 +#define REG_C2HEVT_2_8821C 0x01A8 +#define REG_C2HEVT_3_8821C 0x01AC #define REG_SW_DEFINED_PAGE1_8821C 0x01B8 +#define REG_SW_DEFINED_PAGE2_8821C 0x01BC #define REG_MCUTST_I_8821C 0x01C0 #define REG_MCUTST_II_8821C 0x01C4 #define REG_FMETHR_8821C 0x01C8 @@ -217,7 +236,7 @@ #define REG_DDMA_CH4CTRL_8821C 0x1248 #define REG_DDMA_CH5SA_8821C 0x1250 #define REG_DDMA_CH5DA_8821C 0x1254 -#define REG_REG_DDMA_CH5CTRL_8821C 0x1258 +#define REG_DDMA_CH5CTRL_8821C 0x1258 #define REG_DDMA_INT_MSK_8821C 0x12E0 #define REG_DDMA_CHSTATUS_8821C 0x12E8 #define REG_DDMA_CHKSUM_8821C 0x12F0 @@ -437,7 +456,9 @@ #define REG_RXTSF_OFFSET_CCK_8821C 0x055E #define REG_RXTSF_OFFSET_OFDM_8821C 0x055F #define REG_TSFTR_8821C 0x0560 +#define REG_TSFTR_1_8821C 0x0564 #define REG_FREERUN_CNT_8821C 0x0568 +#define REG_FREERUN_CNT_1_8821C 0x056C #define REG_ATIMWND1_V1_8821C 0x0570 #define REG_TBTT_PROHIBIT_INFRA_8821C 0x0571 #define REG_CTWND_8821C 0x0572 @@ -496,6 +517,9 @@ #define REG_EDCA_RANDOM_GEN_8821C 0x05CC #define REG_TXCMD_NOA_SEL_8821C 0x05CF #define REG_NOA_PARAM_8821C 0x05E0 +#define REG_NOA_PARAM_1_8821C 0x05E4 +#define REG_NOA_PARAM_2_8821C 0x05E8 +#define REG_NOA_PARAM_3_8821C 0x05EC #define REG_P2P_RST_8821C 0x05F0 #define REG_SCHEDULER_RST_8821C 0x05F1 #define REG_SCH_TXCMD_8821C 0x05F8 @@ -547,6 +571,7 @@ #define REG_LBDLY_8821C 0x0660 #define REG_WMAC_BACAM_RPMEN_8821C 0x0661 #define REG_TX_RX_8821C 0x0662 +#define REG_WMAC_BITMAP_CTL_8821C 0x0663 #define REG_RXERR_RPT_8821C 0x0664 #define REG_WMAC_TRXPTCL_CTL_8821C 0x0668 #define REG_CAMCMD_8821C 0x0670 @@ -606,13 +631,30 @@ #define REG_BSSID4_8821C 0x1648 #define REG_NOA_REPORT_8821C 0x1650 #define REG_PWRBIT_SETTING_8821C 0x1660 +#define REG_WMAC_MU_BF_OPTION_8821C 0x167C +#define REG_WMAC_PAUSE_BB_CLR_TH_8821C 0x167D +#define REG_WMAC_MU_ARB_8821C 0x167E +#define REG_WMAC_MU_OPTION_8821C 0x167F +#define REG_WMAC_MU_BF_CTL_8821C 0x1680 +#define REG_WMAC_MU_BIT_BFRPT_PARA_8821C 0x1682 +#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C 0x1684 +#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C 0x1686 +#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C 0x1688 +#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C 0x168A +#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C 0x168C +#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C 0x168E +#define REG_WMAC_BB_STOP_RX_COUNTER_8821C 0x1690 +#define REG_WMAC_PLCP_MONITOR_8821C 0x1694 +#define REG_WMAC_PLCP_MONITOR_MUTX_8821C 0x1698 #define REG_TRANSMIT_ADDRSS_0_8821C 0x16A0 #define REG_TRANSMIT_ADDRSS_1_8821C 0x16A8 #define REG_TRANSMIT_ADDRSS_2_8821C 0x16B0 #define REG_TRANSMIT_ADDRSS_3_8821C 0x16B8 #define REG_TRANSMIT_ADDRSS_4_8821C 0x16C0 #define REG_MACID1_8821C 0x0700 +#define REG_MACID1_1_8821C 0x0704 #define REG_BSSID1_8821C 0x0708 +#define REG_BSSID1_1_8821C 0x070C #define REG_BCN_PSR_RPT1_8821C 0x0710 #define REG_ASSOCIATED_BFMEE_SEL_8821C 0x0714 #define REG_SND_PTCL_CTRL_8821C 0x0718 @@ -621,18 +663,26 @@ #define REG_NS_ARP_INFO_8821C 0x0724 #define REG_BEAMFORMING_INFO_NSARP_V1_8821C 0x0728 #define REG_BEAMFORMING_INFO_NSARP_8821C 0x072C +#define REG_IPV6_8821C 0x0730 +#define REG_IPV6_1_8821C 0x0734 +#define REG_IPV6_2_8821C 0x0738 +#define REG_IPV6_3_8821C 0x073C #define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8821C 0x0750 #define REG_WMAC_SWAES_CFG_8821C 0x0760 #define REG_BT_COEX_V2_8821C 0x0762 #define REG_BT_COEX_8821C 0x0764 #define REG_WLAN_ACT_MASK_CTRL_8821C 0x0768 +#define REG_WLAN_ACT_MASK_CTRL_1_8821C 0x076C #define REG_BT_COEX_ENHANCED_INTR_CTRL_8821C 0x076E #define REG_BT_ACT_STATISTICS_8821C 0x0770 +#define REG_BT_ACT_STATISTICS_1_8821C 0x0774 #define REG_BT_STATISTICS_CONTROL_REGISTER_8821C 0x0778 #define REG_BT_STATUS_REPORT_REGISTER_8821C 0x077C #define REG_BT_INTERRUPT_CONTROL_REGISTER_8821C 0x0780 #define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C 0x0784 #define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C 0x0785 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8821C 0x0788 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C 0x078C #define REG_BT_INTERRUPT_STATUS_REGISTER_8821C 0x078F #define REG_BT_TDMA_TIME_REGISTER_8821C 0x0790 #define REG_BT_ACT_REGISTER_8821C 0x0794 @@ -643,18 +693,26 @@ #define REG_LTR_IDLE_LATENCY_V1_8821C 0x07A8 #define REG_LTR_ACTIVE_LATENCY_V1_8821C 0x07AC #define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C 0x07B0 +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C 0x07B4 #define REG_WMAC_PKTCNT_RWD_8821C 0x07B8 #define REG_WMAC_PKTCNT_CTRL_8821C 0x07BC #define REG_IQ_DUMP_8821C 0x07C0 +#define REG_IQ_DUMP_1_8821C 0x07C4 +#define REG_IQ_DUMP_2_8821C 0x07C8 #define REG_WMAC_FTM_CTL_8821C 0x07CC #define REG_WMAC_IQ_MDPK_FUNC_8821C 0x07CE #define REG_WMAC_OPTION_FUNCTION_8821C 0x07D0 +#define REG_WMAC_OPTION_FUNCTION_1_8821C 0x07D4 +#define REG_WMAC_OPTION_FUNCTION_2_8821C 0x07D8 #define REG_RX_FILTER_FUNCTION_8821C 0x07DA #define REG_NDP_SIG_8821C 0x07E0 #define REG_TXCMD_INFO_FOR_RSP_PKT_8821C 0x07E4 +#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C 0x07E8 #define REG_WSEC_OPTION_8821C 0x07EC #define REG_RTS_ADDRESS_0_8821C 0x07F0 +#define REG_RTS_ADDRESS_0_1_8821C 0x07F4 #define REG_RTS_ADDRESS_1_8821C 0x07F8 +#define REG_RTS_ADDRESS_1_1_8821C 0x07FC #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8821C 0x1700 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C 0x1704 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C 0x1708 diff --git a/hal/halmac/halmac_reg_8822b.h b/hal/halmac/halmac_reg_8822b.h index 0f9f929..b2913c3 100644 --- a/hal/halmac/halmac_reg_8822b.h +++ b/hal/halmac/halmac_reg_8822b.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __INC_HALMAC_REG_8822B_H #define __INC_HALMAC_REG_8822B_H @@ -92,6 +107,7 @@ #define REG_FW_DBG6_8822B 0x10F8 #define REG_FW_DBG7_8822B 0x10FC #define REG_CR_8822B 0x0100 +#define REG_PKT_BUFF_ACCESS_CTRL_8822B 0x0106 #define REG_TSF_CLK_STATE_8822B 0x0108 #define REG_TXDMA_PQ_MAP_8822B 0x010C #define REG_TRXFF_BNDY_8822B 0x0114 @@ -290,6 +306,8 @@ #define REG_H2CQ_TXBD_NUM_8822B 0x1328 #define REG_H2CQ_TXBD_IDX_8822B 0x132C #define REG_H2CQ_CSR_8822B 0x1330 +#define REG_CHANGE_PCIE_SPEED_8822B 0x1350 +#define REG_OLD_DEHANG_8822B 0x13F4 #define REG_Q0_INFO_8822B 0x0400 #define REG_Q1_INFO_8822B 0x0404 #define REG_Q2_INFO_8822B 0x0408 @@ -543,6 +561,7 @@ #define REG_LBDLY_8822B 0x0660 #define REG_WMAC_BACAM_RPMEN_8822B 0x0661 #define REG_TX_RX_8822B 0x0662 +#define REG_WMAC_BITMAP_CTL_8822B 0x0663 #define REG_RXERR_RPT_8822B 0x0664 #define REG_WMAC_TRXPTCL_CTL_8822B 0x0668 #define REG_CAMCMD_8822B 0x0670 @@ -602,6 +621,17 @@ #define REG_BSSID4_8822B 0x1648 #define REG_NOA_REPORT_8822B 0x1650 #define REG_PWRBIT_SETTING_8822B 0x1660 +#define REG_WMAC_MU_BF_OPTION_8822B 0x167C +#define REG_WMAC_MU_ARB_8822B 0x167E +#define REG_WMAC_MU_OPTION_8822B 0x167F +#define REG_WMAC_MU_BF_CTL_8822B 0x1680 +#define REG_WMAC_MU_BFRPT_PARA_8822B 0x1682 +#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B 0x1684 +#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B 0x1686 +#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B 0x1688 +#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B 0x168A +#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B 0x168C +#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B 0x168E #define REG_TRANSMIT_ADDRSS_0_8822B 0x16A0 #define REG_TRANSMIT_ADDRSS_1_8822B 0x16A8 #define REG_TRANSMIT_ADDRSS_2_8822B 0x16B0 diff --git a/hal/halmac/halmac_rx_bd_ap.h b/hal/halmac/halmac_rx_bd_ap.h index 5bb01c0..6da7e4b 100644 --- a/hal/halmac/halmac_rx_bd_ap.h +++ b/hal/halmac/halmac_rx_bd_ap.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_RX_BD_AP_H_ #define _HALMAC_RX_BD_AP_H_ #if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) diff --git a/hal/halmac/halmac_rx_bd_chip.h b/hal/halmac/halmac_rx_bd_chip.h index 601f11c..5270e07 100644 --- a/hal/halmac/halmac_rx_bd_chip.h +++ b/hal/halmac/halmac_rx_bd_chip.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_RX_BD_CHIP_H_ #define _HALMAC_RX_BD_CHIP_H_ #if (HALMAC_8814A_SUPPORT) diff --git a/hal/halmac/halmac_rx_bd_nic.h b/hal/halmac/halmac_rx_bd_nic.h index dc7d5cd..73ce816 100644 --- a/hal/halmac/halmac_rx_bd_nic.h +++ b/hal/halmac/halmac_rx_bd_nic.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_RX_BD_NIC_H_ #define _HALMAC_RX_BD_NIC_H_ #if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) diff --git a/hal/halmac/halmac_rx_desc_ap.h b/hal/halmac/halmac_rx_desc_ap.h index 386e418..556a67c 100644 --- a/hal/halmac/halmac_rx_desc_ap.h +++ b/hal/halmac/halmac_rx_desc_ap.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_RX_DESC_AP_H_ #define _HALMAC_RX_DESC_AP_H_ #if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) @@ -50,6 +65,17 @@ /*RXDESC_WORD2*/ #define GET_RX_DESC_FCS_OK(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 31) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define GET_RX_DESC_PPDU_CNT(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x3, 29) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) + #define GET_RX_DESC_C2H(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 28) #define GET_RX_DESC_HWRSVD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xf, 24) #define GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x3f, 18) @@ -62,6 +88,18 @@ #define GET_RX_DESC_MAGIC_WAKE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 31) #define GET_RX_DESC_UNICAST_WAKE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 30) #define GET_RX_DESC_PATTERN_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 29) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 28) +#define GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0xf, 24) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) + #define GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0xff, 16) #define GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x3, 12) #define GET_RX_DESC_EOSP(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 11) @@ -106,3 +144,4 @@ #endif + diff --git a/hal/halmac/halmac_rx_desc_chip.h b/hal/halmac/halmac_rx_desc_chip.h index 43d8057..b2dfdf5 100644 --- a/hal/halmac/halmac_rx_desc_chip.h +++ b/hal/halmac/halmac_rx_desc_chip.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_RX_DESC_CHIP_H_ #define _HALMAC_RX_DESC_CHIP_H_ #if (HALMAC_8814A_SUPPORT) @@ -114,6 +129,7 @@ /*RXDESC_WORD2*/ #define GET_RX_DESC_FCS_OK_8822B(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) +#define GET_RX_DESC_PPDU_CNT_8822B(__pRxDesc) GET_RX_DESC_PPDU_CNT(__pRxDesc) #define GET_RX_DESC_C2H_8822B(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) #define GET_RX_DESC_HWRSVD_8822B(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) #define GET_RX_DESC_WLANHD_IV_LEN_8822B(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) @@ -126,6 +142,8 @@ #define GET_RX_DESC_MAGIC_WAKE_8822B(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) #define GET_RX_DESC_UNICAST_WAKE_8822B(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) #define GET_RX_DESC_PATTERN_MATCH_8822B(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8822B(__pRxDesc) GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8822B(__pRxDesc) GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) #define GET_RX_DESC_DMA_AGG_NUM_8822B(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) #define GET_RX_DESC_BSSID_FIT_1_0_8822B(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) #define GET_RX_DESC_EOSP_8822B(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) @@ -262,6 +280,7 @@ /*RXDESC_WORD2*/ #define GET_RX_DESC_FCS_OK_8821C(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) +#define GET_RX_DESC_PPDU_CNT_8821C(__pRxDesc) GET_RX_DESC_PPDU_CNT(__pRxDesc) #define GET_RX_DESC_C2H_8821C(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) #define GET_RX_DESC_HWRSVD_8821C(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) #define GET_RX_DESC_WLANHD_IV_LEN_8821C(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) @@ -274,6 +293,8 @@ #define GET_RX_DESC_MAGIC_WAKE_8821C(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) #define GET_RX_DESC_UNICAST_WAKE_8821C(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) #define GET_RX_DESC_PATTERN_MATCH_8821C(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8821C(__pRxDesc) GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8821C(__pRxDesc) GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) #define GET_RX_DESC_DMA_AGG_NUM_8821C(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) #define GET_RX_DESC_BSSID_FIT_1_0_8821C(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) #define GET_RX_DESC_EOSP_8821C(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) @@ -366,3 +387,4 @@ #endif + diff --git a/hal/halmac/halmac_rx_desc_nic.h b/hal/halmac/halmac_rx_desc_nic.h index 7722df1..2e9209e 100644 --- a/hal/halmac/halmac_rx_desc_nic.h +++ b/hal/halmac/halmac_rx_desc_nic.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_RX_DESC_NIC_H_ #define _HALMAC_RX_DESC_NIC_H_ #if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) @@ -50,6 +65,17 @@ /*RXDESC_WORD2*/ #define GET_RX_DESC_FCS_OK(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 31, 1) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define GET_RX_DESC_PPDU_CNT(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 29, 2) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) + #define GET_RX_DESC_C2H(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 28, 1) #define GET_RX_DESC_HWRSVD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 24, 4) #define GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 18, 6) @@ -62,6 +88,18 @@ #define GET_RX_DESC_MAGIC_WAKE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 31, 1) #define GET_RX_DESC_UNICAST_WAKE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 30, 1) #define GET_RX_DESC_PATTERN_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 29, 1) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) + +#define GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 28, 1) +#define GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 24, 4) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) + #define GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 16, 8) #define GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 12, 2) #define GET_RX_DESC_EOSP(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 11, 1) @@ -106,3 +144,4 @@ #endif + diff --git a/hal/halmac/halmac_sdio_reg.h b/hal/halmac/halmac_sdio_reg.h index 18dfbe5..2a47d6f 100644 --- a/hal/halmac/halmac_sdio_reg.h +++ b/hal/halmac/halmac_sdio_reg.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __HALMAC_SDIO_REG_H__ #define __HALMAC_SDIO_REG_H__ @@ -5,7 +20,8 @@ #define HALMAC_SDIO_4BYTE_LEN_MASK 0x1FFF #define HALMAC_SDIO_LOCAL_MSK 0x0FFF -#define HALMAC_WLAN_IOREG_MSK 0xFFFF +#define HALMAC_WLAN_MAC_REG_MSK 0xFFFF +#define HALMAC_WLAN_IOREG_MSK 0xFFFF /* Sdio Address for SDIO Local Reg, TRX FIFO, MAC Reg */ typedef enum { @@ -18,25 +34,20 @@ typedef enum { HALMAC_SDIO_CMD_ADDR_RXFF = 7, } HALMAC_SDIO_CMD_ADDR; - -#if 1 -#define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */ -#define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */ -#define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */ -#define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */ -#define WLAN_TX_EPQ_DEVICE_ID 3 /* 0b[16], 110b[15:13] */ -#define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ -#define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ - /* IO Bus domain address mapping */ -#define SDIO_LOCAL_OFFSET 0x10250000 -#define WLAN_IOREG_OFFSET 0x10260000 -#define FW_FIFO_OFFSET 0x10270000 -#define TX_HIQ_OFFSET 0x10310000 -#define TX_MIQ_OFFSET 0x10320000 -#define TX_LOQ_OFFSET 0x10330000 -#define TX_EXQ_OFFSET 0x10350000 -#define RX_RXOFF_OFFSET 0x10340000 +#define SDIO_LOCAL_OFFSET 0x10250000 +#define WLAN_IOREG_OFFSET 0x10260000 +#define FW_FIFO_OFFSET 0x10270000 +#define TX_HIQ_OFFSET 0x10310000 +#define TX_MIQ_OFFSET 0x10320000 +#define TX_LOQ_OFFSET 0x10330000 +#define TX_EXQ_OFFSET 0x10350000 +#define RX_RXOFF_OFFSET 0x10340000 + +/* Get TX WLAN FIFO information in CMD53 addr */ +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) +#define GET_WLAN_TXFF_DEVICE_ID(__pCmd53_addr) LE_BITS_TO_4BYTE((u32 *)__pCmd53_addr, 13, 4) +#define GET_WLAN_TXFF_PKT_SIZE(__pCmd53_addr) (LE_BITS_TO_4BYTE((u32 *)__pCmd53_addr, 0, 13) << 2) #endif #endif/* __HALMAC_SDIO_REG_H__ */ diff --git a/hal/halmac/halmac_tx_bd_ap.h b/hal/halmac/halmac_tx_bd_ap.h index 1cff6b1..3b9c21a 100644 --- a/hal/halmac/halmac_tx_bd_ap.h +++ b/hal/halmac/halmac_tx_bd_ap.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_TX_BD_AP_H_ #define _HALMAC_TX_BD_AP_H_ #if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) diff --git a/hal/halmac/halmac_tx_bd_chip.h b/hal/halmac/halmac_tx_bd_chip.h index 17004bc..0ebf93c 100644 --- a/hal/halmac/halmac_tx_bd_chip.h +++ b/hal/halmac/halmac_tx_bd_chip.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_TX_BD_CHIP_H_ #define _HALMAC_TX_BD_CHIP_H_ #if (HALMAC_8814A_SUPPORT) diff --git a/hal/halmac/halmac_tx_bd_nic.h b/hal/halmac/halmac_tx_bd_nic.h index 1d53acc..94e4480 100644 --- a/hal/halmac/halmac_tx_bd_nic.h +++ b/hal/halmac/halmac_tx_bd_nic.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_TX_BD_NIC_H_ #define _HALMAC_TX_BD_NIC_H_ #if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) diff --git a/hal/halmac/halmac_tx_desc_ap.h b/hal/halmac/halmac_tx_desc_ap.h index e9c1e59..de2cdd6 100644 --- a/hal/halmac/halmac_tx_desc_ap.h +++ b/hal/halmac/halmac_tx_desc_ap.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_TX_DESC_AP_H_ #define _HALMAC_TX_DESC_AP_H_ #if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) diff --git a/hal/halmac/halmac_tx_desc_chip.h b/hal/halmac/halmac_tx_desc_chip.h index d15b6cf..e778594 100644 --- a/hal/halmac/halmac_tx_desc_chip.h +++ b/hal/halmac/halmac_tx_desc_chip.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_TX_DESC_CHIP_H_ #define _HALMAC_TX_DESC_CHIP_H_ #if (HALMAC_8814A_SUPPORT) diff --git a/hal/halmac/halmac_tx_desc_nic.h b/hal/halmac/halmac_tx_desc_nic.h index 94eefbe..4e82378 100644 --- a/hal/halmac/halmac_tx_desc_nic.h +++ b/hal/halmac/halmac_tx_desc_nic.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_TX_DESC_NIC_H_ #define _HALMAC_TX_DESC_NIC_H_ #if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) diff --git a/hal/halmac/halmac_type.h b/hal/halmac/halmac_type.h index f99adba..4f36f3e 100644 --- a/hal/halmac/halmac_type.h +++ b/hal/halmac/halmac_type.h @@ -1,10 +1,25 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_TYPE_H_ #define _HALMAC_TYPE_H_ #include "halmac_2_platform.h" #include "halmac_hw_cfg.h" #include "halmac_fw_info.h" - +#include "halmac_intf_phy_cmd.h" #define IN #define OUT @@ -21,11 +36,16 @@ #define HALMC_DDMA_POLLING_COUNT 1000 #define API_ARRAY_SIZE 32 +#ifndef HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE +#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 48 +#endif + /* platform api */ #define PLATFORM_SDIO_CMD52_READ pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_READ #define PLATFORM_SDIO_CMD53_READ_8 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_8 #define PLATFORM_SDIO_CMD53_READ_16 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_16 #define PLATFORM_SDIO_CMD53_READ_32 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_32 +#define PLATFORM_SDIO_CMD53_READ_N pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_N #define PLATFORM_SDIO_CMD52_WRITE pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_WRITE #define PLATFORM_SDIO_CMD53_WRITE_8 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_8 #define PLATFORM_SDIO_CMD53_WRITE_16 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_16 @@ -58,7 +78,7 @@ #if HALMAC_DBG_MSG_ENABLE #define PLATFORM_MSG_PRINT pHalmac_adapter->pHalmac_platform_api->MSG_PRINT #else -#define PLATFORM_MSG_PRINT(pDriver_adapter, msg_type, msg_level, fmt, ...) +#define PLATFORM_MSG_PRINT(pDriver_adapter, msg_type, msg_level, fmt, ...) do {} while (0) #endif #if HALMAC_PLATFORM_TESTPROGRAM @@ -74,6 +94,7 @@ #define HALMAC_REG_WRITE_8 pHalmac_api->halmac_reg_write_8 #define HALMAC_REG_WRITE_16 pHalmac_api->halmac_reg_write_16 #define HALMAC_REG_WRITE_32 pHalmac_api->halmac_reg_write_32 +#define HALMAC_REG_SDIO_CMD53_READ_N pHalmac_api->halmac_reg_sdio_cmd53_read_n /* Swap Little-endian <-> Big-endia*/ #define SWAP32(x) ((u32)( \ @@ -256,6 +277,10 @@ #define BIT(x) (1 << (x)) #endif +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#endif + /* HALMAC API return status*/ typedef enum _HALMAC_RET_STATUS { HALMAC_RET_SUCCESS = 0x00, @@ -344,6 +369,19 @@ typedef enum _HALMAC_RET_STATUS { HALMAC_RET_USB_MODE_UNCHANGE = 0x53, HALMAC_RET_NO_DLFW = 0x54, HALMAC_RET_USB2_3_SWITCH_UNSUPPORT = 0x55, + HALMAC_RET_BIP_NO_SUPPORT = 0x56, + HALMAC_RET_ENTRY_INDEX_ERROR = 0x57, + HALMAC_RET_ENTRY_KEY_ID_ERROR = 0x58, + HALMAC_RET_DRV_DL_ERR = 0x59, + HALMAC_RET_OQT_NOT_ENOUGH = 0x5A, + HALMAC_RET_PWR_UNCHANGE = 0x5B, + HALMAC_RET_WRONG_INTF = 0x5C, + HALMAC_RET_FW_NO_SUPPORT = 0x60, + HALMAC_RET_TXFIFO_NO_EMPTY = 0x61, + HALMAC_RET_SDIO_CLOCK_ERR = 0x62, + HALMAC_RET_GET_PINMUX_ERR = 0x63, + HALMAC_RET_PINMUX_USED = 0x64, + HALMAC_RET_WRONG_GPIO = 0x65, } HALMAC_RET_STATUS; typedef enum _HALMAC_MAC_CLOCK_HW_DEF { @@ -352,22 +390,11 @@ typedef enum _HALMAC_MAC_CLOCK_HW_DEF { HALMAC_MAC_CLOCK_HW_DEF_20M = 2, } HALMAC_MAC_CLOCK_HW_DEF; -/* Rx aggregation parameters */ -typedef enum _HALMAC_NORMAL_RXAGG_TH_TO { - HALMAC_NORMAL_RXAGG_THRESHOLD = 0xFF, - HALMAC_NORMAL_RXAGG_TIMEOUT = 0x01, -} HALMAC_NORMAL_RXAGG_TH_TO; - -typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO { - HALMAC_LOOPBACK_RXAGG_THRESHOLD = 0xFF, - HALMAC_LOOPBACK_RXAGG_TIMEOUT = 0x01, -} HALMAC_LOOPBACK_RXAGG_TH_TO; - /* Chip ID*/ typedef enum _HALMAC_CHIP_ID { HALMAC_CHIP_ID_8822B = 0, HALMAC_CHIP_ID_8821C = 1, - HALMAC_CHIP_ID_8824B = 2, + HALMAC_CHIP_ID_8814B = 2, HALMAC_CHIP_ID_8197F = 3, HALMAC_CHIP_ID_UNDEFINE = 0x7F, } HALMAC_CHIP_ID; @@ -388,6 +415,7 @@ typedef enum _HALMAC_CHIP_ID_HW_DEF { HALMAC_CHIP_ID_HW_DEF_8192F = 0x0D, HALMAC_CHIP_ID_HW_DEF_8197F = 0x0E, HALMAC_CHIP_ID_HW_DEF_8723D = 0x0F, + HALMAC_CHIP_ID_HW_DEF_8814B = 0x10, HALMAC_CHIP_ID_HW_DEF_UNDEFINE = 0x7F, HALMAC_CHIP_ID_HW_DEF_PS = 0xEA, } HALMAC_CHIP_ID_HW_DEF; @@ -430,6 +458,12 @@ typedef enum _HALMAC_DMA_MAPPING { HALMAC_DMA_MAPPING_UNDEFINE = 0x7F, } HALMAC_DMA_MAPPING; +#define HALMAC_MAP2_HQ HALMAC_DMA_MAPPING_HIGH +#define HALMAC_MAP2_NQ HALMAC_DMA_MAPPING_NORMAL +#define HALMAC_MAP2_LQ HALMAC_DMA_MAPPING_LOW +#define HALMAC_MAP2_EXQ HALMAC_DMA_MAPPING_EXTRA +#define HALMAC_MAP2_UNDEF HALMAC_DMA_MAPPING_UNDEFINE + /* TXDESC queue select TID */ typedef enum _HALMAC_TXDESC_QUEUE_TID { HALMAC_TXDESC_QSEL_TID0 = 0, @@ -484,6 +518,13 @@ typedef enum { HALMAC_QUEUE_SELECT_UNDEFINE = 0x7F, } HALMAC_QUEUE_SELECT; +typedef enum _HALMAC_ACQ_ID { + HALMAC_ACQ_ID_VO = 0, + HALMAC_ACQ_ID_VI = 1, + HALMAC_ACQ_ID_BE = 2, + HALMAC_ACQ_ID_BK = 3, + HALMAC_ACQ_ID_MAX = 0x7F, +} HALMAC_ACQ_ID; /* USB burst size */ typedef enum _HALMAC_USB_BURST_SIZE { @@ -499,6 +540,7 @@ typedef enum _HALMAC_INTERFACE { HALMAC_INTERFACE_PCIE = 0x0, HALMAC_INTERFACE_USB = 0x1, HALMAC_INTERFACE_SDIO = 0x2, + HALMAC_INTERFACE_AXI = 0x3, HALMAC_INTERFACE_UNDEFINE = 0x7F, } HALMAC_INTERFACE; @@ -519,7 +561,6 @@ typedef struct _HALMAC_RXAGG_CFG { HALMAC_RXAGG_TH threshold; } HALMAC_RXAGG_CFG, *PHALMAC_RXAGG_CFG; - typedef enum _HALMAC_MAC_POWER { HALMAC_MAC_POWER_OFF = 0x0, HALMAC_MAC_POWER_ON = 0x1, @@ -540,6 +581,8 @@ typedef enum _HALMAC_TRX_MODE { HALMAC_TRX_MODE_P2P = 0x3, HALMAC_TRX_MODE_LOOPBACK = 0x4, HALMAC_TRX_MODE_DELAY_LOOPBACK = 0x5, + HALMAC_TRX_MODE_MAX = 0x6, + HALMAC_TRX_MODE_WMM_LINUX = 0x7E, HALMAC_TRX_MODE_UNDEFINE = 0x7F, } HALMAC_TRX_MODE; @@ -570,6 +613,10 @@ typedef enum _HALMAC_EFUSE_READ_CFG { HALMAC_EFUSE_R_UNDEFINE = 0x7F, } HALMAC_EFUSE_READ_CFG; +typedef enum _HALMAC_DLFW_MEM { + HALMAC_DLFW_MEM_EMEM = 0x00, + HALMAC_DLFW_MEM_UNDEFINE = 0x7F, +} HALMAC_DLFW_MEM; typedef struct _HALMAC_TX_DESC { u32 Dword0; @@ -595,34 +642,6 @@ typedef struct _HALMAC_RX_DESC { u32 Dword5; } HALMAC_RX_DESC, *PHALMAC_RX_DESC; -typedef struct _HALMAC_FWLPS_OPTION { - u8 mode; - u8 clk_request; - u8 rlbm; - u8 smart_ps; - u8 awake_interval; - u8 all_queue_uapsd; - u8 pwr_state; - u8 low_pwr_rx_beacon; - u8 ant_auto_switch; - u8 ps_allow_bt_high_Priority; - u8 protect_bcn; - u8 silence_period; - u8 fast_bt_connect; - u8 two_antenna_en; - u8 adopt_user_Setting; - u8 drv_bcn_early_shift; - u8 enter_32K; -} HALMAC_FWLPS_OPTION, *PHALMAC_FWLPS_OPTION; - -typedef struct _HALMAC_FWIPS_OPTION { - u8 adopt_user_Setting; -} HALMAC_FWIPS_OPTION, *PHALMAC_FWIPS_OPTION; - -typedef struct _HALMAC_WOWLAN_OPTION { - u8 adopt_user_Setting; -} HALMAC_WOWLAN_OPTION, *PHALMAC_WOWLAN_OPTION; - typedef struct _HALMAC_BCN_IE_INFO { u8 func_en; u8 size_th; @@ -728,7 +747,13 @@ typedef struct _HALMAC_HW_CONFIG_INFO { u32 rx_fifo_size; /* Record rx fifo size */ u8 txdesc_size; /* Record tx desc size */ u8 rxdesc_size; /* Record rx desc size */ + u32 page_size; /* Record page size */ + u16 tx_align_size; + u8 page_size_2_power; u8 cam_entry_num; /* Record CAM entry number */ + u8 ac_oqt_size; + u8 non_ac_oqt_size; + u8 ac_queue_num; } HALMAC_HW_CONFIG_INFO, *PHALMAC_HW_CONFIG_INFO; typedef struct _HALMAC_SDIO_FREE_SPACE { @@ -739,6 +764,7 @@ typedef struct _HALMAC_SDIO_FREE_SPACE { u16 extra_queue_number; /* Free space of EXBQ */ u8 ac_oqt_number; u8 non_ac_oqt_number; + u8 ac_empty; } HALMAC_SDIO_FREE_SPACE, *PHALMAC_SDIO_FREE_SPACE; typedef enum _HAL_FIFO_SEL { @@ -747,6 +773,7 @@ typedef enum _HAL_FIFO_SEL { HAL_FIFO_SEL_RSVD_PAGE, HAL_FIFO_SEL_REPORT, HAL_FIFO_SEL_LLT, + HAL_FIFO_SEL_RXBUF_FW, } HAL_FIFO_SEL; typedef enum _HALMAC_DRV_INFO { @@ -757,18 +784,6 @@ typedef enum _HALMAC_DRV_INFO { HALMAC_DRV_INFO_UNDEFINE, } HALMAC_DRV_INFO; -typedef struct _HALMAC_BT_COEX_CMD { - u8 element_id; - u8 op_code; - u8 op_code_ver; - u8 req_num; - u8 data0; - u8 data1; - u8 data2; - u8 data3; - u8 data4; -} HALMAC_BT_COEX_CMD, *PHALMAC_BT_COEX_CMD; - typedef enum _HALMAC_PRI_CH_IDX { HALMAC_CH_IDX_UNDEFINE = 0, HALMAC_CH_IDX_1 = 1, @@ -816,10 +831,20 @@ typedef struct _HALMAC_CH_SWITCH_OPTION { u8 phase_2_period; } HALMAC_CH_SWITCH_OPTION, *PHALMAC_CH_SWITCH_OPTION; +typedef struct _HALMAC_FW_BUILD_TIME { + u16 year; + u8 month; + u8 date; + u8 hour; + u8 min; +} HALMAC_FW_BUILD_TIME, *PHALMAC_FW_BUILD_TIME; + typedef struct _HALMAC_FW_VERSION { u16 version; u8 sub_version; u8 sub_index; + u16 h2c_version; + HALMAC_FW_BUILD_TIME build_time; } HALMAC_FW_VERSION, *PHALMAC_FW_VERSION; typedef enum _HALMAC_RF_TYPE { @@ -970,6 +995,29 @@ typedef enum _HALMAC_SND_PKT_SEL { HALMAC_FINAL_BFRPTPOLL, } HALMAC_SND_PKT_SEL; +typedef enum _HAL_SECURITY_TYPE { + HAL_SECURITY_TYPE_NONE = 0, + HAL_SECURITY_TYPE_WEP40 = 1, + HAL_SECURITY_TYPE_WEP104 = 2, + HAL_SECURITY_TYPE_TKIP = 3, + HAL_SECURITY_TYPE_AES128 = 4, + HAL_SECURITY_TYPE_WAPI = 5, + HAL_SECURITY_TYPE_AES256 = 6, + HAL_SECURITY_TYPE_GCMP128 = 7, + HAL_SECURITY_TYPE_GCMP256 = 8, + HAL_SECURITY_TYPE_GCMSMS4 = 9, + HAL_SECURITY_TYPE_BIP = 10, + HAL_SECURITY_TYPE_UNDEFINE = 0x7F, +} HAL_SECURITY_TYPE; + +typedef enum _HAL_INTF_PHY { + HAL_INTF_PHY_USB2 = 0, + HAL_INTF_PHY_USB3 = 1, + HAL_INTF_PHY_PCIE_GEN1 = 2, + HAL_INTF_PHY_PCIE_GEN2 = 3, + HAL_INTF_PHY_UNDEFINE = 0x7F, +} HAL_INTF_PHY; + #if HALMAC_PLATFORM_TESTPROGRAM typedef enum _HALMAC_PWR_SEQ_ID { @@ -991,22 +1039,6 @@ typedef enum _HAL_TX_ID { HAL_TX_ID_MAX } HAL_TX_ID; -typedef enum _HAL_QSEL { - HAL_QSEL_TID0, - HAL_QSEL_TID1, - HAL_QSEL_TID2, - HAL_QSEL_TID3, - HAL_QSEL_TID4, - HAL_QSEL_TID5, - HAL_QSEL_TID6, - HAL_QSEL_TID7, - - HAL_QSEL_BEACON = 0x10, - HAL_QSEL_HIGH = 0x11, - HAL_QSEL_MGT = 0x12, - HAL_QSEL_CMD = 0x13 -} HAL_QSEL; - typedef enum _HAL_RTS_MODE { HAL_RTS_MODE_NONE, HAL_RTS_MODE_CTS2SELF, @@ -1025,33 +1057,12 @@ typedef enum _HAL_RTS_SHORT { HAL_RTS_SHORT_LONG, } HAL_RTS_SHORT; -typedef enum _HAL_SECURITY_TYPE { - HAL_SECURITY_TYPE_NONE = 0, - HAL_SECURITY_TYPE_WEP40 = 1, - HAL_SECURITY_TYPE_WEP104 = 2, - HAL_SECURITY_TYPE_TKIP = 3, - HAL_SECURITY_TYPE_AES128 = 4, - HAL_SECURITY_TYPE_WAPI = 5, - HAL_SECURITY_TYPE_AES256 = 6, - HAL_SECURITY_TYPE_GCMP128 = 7, - HAL_SECURITY_TYPE_GCMP256 = 8, - HAL_SECURITY_TYPE_GCMSMS4 = 9, - HAL_SECURITY_TYPE_BIP = 10, - HAL_SECURITY_TYPE_UNDEFINE = 0x7F, -} HAL_SECURITY_TYPE; - typedef enum _HAL_SECURITY_METHOD { HAL_SECURITY_METHOD_HW = 0, HAL_SECURITY_METHOD_SW = 1, HAL_SECURITY_METHOD_UNDEFINE = 0x7F, } HAL_SECURITY_METHOD; -typedef struct _HAL_SECURITY_INFO { - HAL_SECURITY_TYPE type; - HAL_SECURITY_METHOD tx_method; - HAL_SECURITY_METHOD rx_method; -} HAL_SECURITY_INFO, *PHAL_SECURITY_INFO; - typedef struct _HAL_TXDESC_INFO { u32 txdesc_length; u32 packet_size; /* payload + wlheader */ @@ -1139,35 +1150,10 @@ typedef struct _HALMAC_CHIP_TYPE { HALMAC_CHIP_VER chip_version; } HALMAC_CHIP_TYPE, *PHALMAC_CHIP_TYPE; -typedef struct _HALMAC_CAM_ENTRY_FORMAT { - u16 key_id : 2; - u16 type : 3; - u16 mic : 1; - u16 grp : 1; - u16 spp_mode : 1; - u16 rpt_md : 1; - u16 ext_sectype : 1; - u16 mgnt : 1; - u16 rsvd1 : 4; - u16 valid : 1; - u8 mac_address[6]; - u32 key[4]; - u32 rsvd[2]; -} HALMAC_CAM_ENTRY_FORMAT, *PHALMAC_CAM_ENTRY_FORMAT; - -typedef struct _HALMAC_CAM_ENTRY_INFO { - HAL_SECURITY_TYPE security_type; - u32 key[4]; - u32 key_ext[4]; - u8 mac_address[6]; - u8 unicast; - u8 key_id; - u8 valid; -} HALMAC_CAM_ENTRY_INFO, *PHALMAC_CAM_ENTRY_INFO; - #endif /* End of test program */ typedef enum _HALMAC_DBG_MSG_INFO { + HALMAC_DBG_ALWAYS, HALMAC_DBG_ERR, HALMAC_DBG_WARN, HALMAC_DBG_TRACE, @@ -1181,6 +1167,9 @@ typedef enum _HALMAC_DBG_MSG_TYPE { HALMAC_MSG_PWR, HALMAC_MSG_SND, HALMAC_MSG_COMMON, + HALMAC_MSG_DBI, + HALMAC_MSG_MDIO, + HALMAC_MSG_USB } HALMAC_DBG_MSG_TYPE; typedef enum _HALMAC_CMD_PROCESS_STATUS { @@ -1212,6 +1201,54 @@ typedef enum _HALMAC_DRV_RSVD_PG_NUM { HALMAC_RSVD_PG_NUM32, /* 4K */ } HALMAC_DRV_RSVD_PG_NUM; +typedef enum _HALMAC_PCIE_CFG { + HALMAC_PCIE_GEN1, + HALMAC_PCIE_GEN2, + HALMAC_PCIE_CFG_UNDEFINE, +} HALMAC_PCIE_CFG; + +typedef enum _HALMAC_PORTID { + HALMAC_PORTID0 = 0, + HALMAC_PORTID1 = 1, + HALMAC_PORTID2 = 2, + HALMAC_PORTID3 = 3, + HALMAC_PORTID4 = 4, + HALMAC_PORTIDMAX +} HALMAC_PORTID; + +typedef struct _HALMAC_P2PPS { + /*DW0*/ + u8 offload_en:1; + u8 role:1; + u8 ctwindow_en:1; + u8 noa_en:1; + u8 noa_sel:1; + u8 all_sta_sleep:1; + u8 discovery:1; + u8 rsvd2:1; + u8 p2p_port_id; + u8 p2p_group; + u8 p2p_macid; + + /*DW1*/ + u8 ctwindow_length; + u8 rsvd3; + u8 rsvd4; + u8 rsvd5; + + /*DW2*/ + u32 noa_duration_para; + + /*DW3*/ + u32 noa_interval_para; + + /*DW4*/ + u32 noa_start_time_para; + + /*DW5*/ + u32 noa_count_para; +} HALMAC_P2PPS, *PHALMAC_P2PPS; + /* Platform API setting */ typedef struct _HALMAC_PLATFORM_API { @@ -1220,6 +1257,7 @@ typedef struct _HALMAC_PLATFORM_API { u8 (*SDIO_CMD53_READ_8)(VOID *pDriver_adapter, u32 offset); u16 (*SDIO_CMD53_READ_16)(VOID *pDriver_adapter, u32 offset); u32 (*SDIO_CMD53_READ_32)(VOID *pDriver_adapter, u32 offset); + u8 (*SDIO_CMD53_READ_N)(VOID *pDriver_adapter, u32 offset, u32 size, u8 *data); VOID (*SDIO_CMD52_WRITE)(VOID *pDriver_adapter, u32 offset, u8 value); VOID (*SDIO_CMD53_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value); VOID (*SDIO_CMD53_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value); @@ -1248,6 +1286,7 @@ typedef struct _HALMAC_PLATFORM_API { u8 (*MUTEX_UNLOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); u8 (*MSG_PRINT)(VOID *pDriver_adapter, u32 msg_type, u8 msg_level, s8 *fmt, ...); + u8 (*BUFF_PRINT)(VOID *pDriver_adapter, u32 msg_type, u8 msg_level, s8 *buf, u32 size); u8 (*EVENT_INDICATION)(VOID *pDriver_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS process_status, u8 *buf, u32 size); @@ -1264,23 +1303,10 @@ typedef struct _HALMAC_PLATFORM_API { /*1->Little endian 0->Big endian*/ #if HALMAC_SYSTEM_ENDIAN -/* User can not use members in Address_L_H, use Address[6] is mandatory */ -typedef union _HALMAC_WLAN_ADDR { - u8 Address[6]; /* WLAN address (MACID, BSSID, Brodcast ID). Address[0] is lowest, Address[5] is highest*/ - struct { - union { - u32 Address_Low; - u8 Address_Low_B[4]; - }; - union { - u16 Address_High; - u8 Address_High_B[2]; - }; - } Address_L_H; -} HALMAC_WLAN_ADDR, *PHALMAC_WLAN_ADDR; - #else +#endif + /* User can not use members in Address_L_H, use Address[6] is mandatory */ typedef union _HALMAC_WLAN_ADDR { u8 Address[6]; /* WLAN address (MACID, BSSID, Brodcast ID). Address[0] is lowest, Address[5] is highest*/ @@ -1296,8 +1322,6 @@ typedef union _HALMAC_WLAN_ADDR { } Address_L_H; } HALMAC_WLAN_ADDR, *PHALMAC_WLAN_ADDR; -#endif - typedef enum _HALMAC_SND_ROLE { HAL_BFER = 0, HAL_BFEE = 1, @@ -1309,7 +1333,6 @@ typedef enum _HALMAC_CSI_SEG_LEN { HAL_CSI_SEG_11K = 2, } HALMAC_CSI_SEG_LEN; - typedef struct _HALMAC_CFG_MUMIMO_PARA { HALMAC_SND_ROLE role; u8 sounding_sts[6]; @@ -1323,7 +1346,7 @@ typedef struct _HALMAC_SU_BFER_INIT_PARA { u8 userid; u16 paid; u16 csi_para; - PHALMAC_WLAN_ADDR pbfer_address; + HALMAC_WLAN_ADDR bfer_address; } HALMAC_SU_BFER_INIT_PARA, *PHALMAC_SU_BFER_INIT_PARA; typedef struct _HALMAC_MU_BFEE_INIT_PARA { @@ -1338,7 +1361,7 @@ typedef struct _HALMAC_MU_BFER_INIT_PARA { u16 csi_para; u16 my_aid; HALMAC_CSI_SEG_LEN csi_length_sel; - PHALMAC_WLAN_ADDR pbfer_address; + HALMAC_WLAN_ADDR bfer_address; } HALMAC_MU_BFER_INIT_PARA, *PHALMAC_MU_BFER_INIT_PARA; typedef struct _HALMAC_SND_INFO { @@ -1394,6 +1417,12 @@ typedef enum _HALMAC_DLFW_STATE { HALMAC_DLFW_UNDEFINED = 0x7F, } HALMAC_DLFW_STATE; +typedef enum _HALMAC_GPIO_CFG_STATE { + HALMAC_GPIO_CFG_STATE_IDLE = 0, + HALMAC_GPIO_CFG_STATE_BUSY = 1, + HALMAC_GPIO_CFG_STATE_UNDEFINED = 0x7F, +} HALMAC_GPIO_CFG_STATE; + typedef enum _HALMAC_EFUSE_CMD_CONSTRUCT_STATE { HALMAC_EFUSE_CMD_CONSTRUCT_IDLE = 0, HALMAC_EFUSE_CMD_CONSTRUCT_BUSY = 1, @@ -1485,6 +1514,7 @@ typedef struct _HALMAC_STATE { HALMAC_MAC_POWER mac_power; /* 0 : power off, 1 : power on*/ HALMAC_PS_STATE ps_state; /* power saving state */ HALMAC_DLFW_STATE dlfw_state; /* download FW state */ + HALMAC_GPIO_CFG_STATE gpio_cfg_state; /* gpio state */ } HALMAC_STATE, *PHALMAC_STATE; typedef struct _HALMAC_VER { @@ -1575,24 +1605,20 @@ typedef enum _HALMAC_API_ID { HALMAC_API_SU_BFEE_ENTRY_DEL = 0x4B, HALMAC_API_MU_BFER_ENTRY_DEL = 0x4C, HALMAC_API_MU_BFEE_ENTRY_DEL = 0x4D, - HALMAC_API_ADD_CH_INFO = 0x4E, HALMAC_API_ADD_EXTRA_CH_INFO = 0x4F, HALMAC_API_CTRL_CH_SWITCH = 0x50, HALMAC_API_CLEAR_CH_INFO = 0x51, - HALMAC_API_SEND_GENERAL_INFO = 0x52, HALMAC_API_START_IQK = 0x53, HALMAC_API_CTRL_PWR_TRACKING = 0x54, HALMAC_API_PSD = 0x55, HALMAC_API_CFG_TX_AGG_ALIGN = 0x56, - HALMAC_API_QUERY_STATE = 0x57, HALMAC_API_RESET_FEATURE = 0x58, HALMAC_API_CHECK_FW_STATUS = 0x59, HALMAC_API_DUMP_FW_DMEM = 0x5A, HALMAC_API_CFG_MAX_DL_SIZE = 0x5B, - HALMAC_API_INIT_OBJ = 0x5C, HALMAC_API_DEINIT_OBJ = 0x5D, HALMAC_API_CFG_LA_MODE = 0x5E, @@ -1602,15 +1628,45 @@ typedef enum _HALMAC_API_ID { HALMAC_API_SWITCH_EFUSE_BANK = 0x62, HALMAC_API_WRITE_EFUSE_BT = 0x63, HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64, + HALMAC_API_DL_DRV_RSVD_PG = 0x65, + HALMAC_API_PCIE_SWITCH = 0x66, + HALMAC_API_PHY_CFG = 0x67, + HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE = 0x68, + HALMAC_API_CFG_CSI_RATE = 0x69, + HALMAC_API_P2PPS = 0x6A, + HALMAC_API_CFG_TX_ADDR = 0x6B, + HALMAC_API_CFG_NET_TYPE = 0x6C, + HALMAC_API_CFG_TSF_RESET = 0x6D, + HALMAC_API_CFG_BCN_SPACE = 0x6E, + HALMAC_API_CFG_BCN_CTRL = 0x6F, + HALMAC_API_CFG_SIDEBAND_INT = 0x70, + HALMAC_API_REGISTER_API = 0x71, + HALMAC_API_FREE_DOWNLOAD_FIRMWARE = 0x72, + HALMAC_API_GET_FW_VERSION = 0x73, + HALMAC_API_GET_EFUSE_AVAL_SIZE = 0x74, + HALMAC_API_CHK_TXDESC = 0x75, + HALMAC_API_SDIO_CMD53_4BYTE = 0x76, + HALMAC_API_CFG_TRANS_ADDR = 0x77, + HALMAC_API_INTF_INTEGRA_TUNING = 0x78, + HALMAC_API_TXFIFO_IS_EMPTY = 0x79, + HALMAC_API_DOWNLOAD_FLASH = 0x7A, + HALMAC_API_READ_FLASH = 0x7B, + HALMAC_API_ERASE_FLASH = 0x7C, + HALMAC_API_CHECK_FLASH = 0x7D, + HALMAC_API_SDIO_HW_INFO = 0x80, + HALMAC_API_READ_EFUSE_BT = 0x81, + HALMAC_API_CFG_EFUSE_AUTO_CHECK = 0x82, + HALMAC_API_CFG_PINMUX_GET_FUNC = 0x83, + HALMAC_API_CFG_PINMUX_SET_FUNC = 0x84, + HALMAC_API_CFG_PINMUX_FREE_FUNC = 0x85, + HALMAC_API_CFG_PINMUX_WL_LED_MODE = 0x86, + HALMAC_API_CFG_PINMUX_WL_LED_SW_CTRL = 0x87, + HALMAC_API_CFG_PINMUX_SDIO_INT_POLARITY = 0x88, + HALMAC_API_CFG_PINMUX_GPIO_MODE = 0x89, + HALMAC_API_CFG_PINMUX_GPIO_OUTPUT = 0x90, HALMAC_API_MAX } HALMAC_API_ID; - -typedef struct _HALMAC_API_RECORD { - HALMAC_API_ID api_array[API_ARRAY_SIZE]; - u8 array_wptr; -} HALMAC_API_RECORD, *PHALMAC_API_RECORD; - typedef enum _HALMAC_LA_MODE { HALMAC_LA_MODE_DISABLE = 0, HALMAC_LA_MODE_PARTIAL = 1, @@ -1618,33 +1674,63 @@ typedef enum _HALMAC_LA_MODE { HALMAC_LA_MODE_UNDEFINE = 0x7F, } HALMAC_LA_MODE; +typedef enum _HALMAC_RX_FIFO_EXPANDING_MODE { + HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE = 0, + HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK = 1, + HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK = 2, + HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK = 3, + HALMAC_RX_FIFO_EXPANDING_MODE_UNDEFINE = 0x7F, +} HALMAC_RX_FIFO_EXPANDING_MODE; + +typedef enum _HALMAC_SDIO_CMD53_4BYTE_MODE { + HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE = 0, + HALMAC_SDIO_CMD53_4BYTE_MODE_RW = 1, + HALMAC_SDIO_CMD53_4BYTE_MODE_R = 2, + HALMAC_SDIO_CMD53_4BYTE_MODE_W = 3, + HALMAC_SDIO_CMD53_4BYTE_MODE_UNDEFINE = 0x7F, +} HALMAC_SDIO_CMD53_4BYTE_MODE; + typedef enum _HALMAC_USB_MODE { HALMAC_USB_MODE_U2 = 1, HALMAC_USB_MODE_U3 = 2, } HALMAC_USB_MODE; typedef enum _HALMAC_HW_ID { - HALMAC_HW_RQPN_MAPPING = 0, - HALMAC_HW_EFUSE_SIZE = 1, - HALMAC_HW_EEPROM_SIZE = 2, - HALMAC_HW_TXFIFO_SIZE = 3, - HALMAC_HW_RSVD_PG_BNDY = 4, - HALMAC_HW_CAM_ENTRY_NUM = 5, - HALMAC_HW_HRPWM = 6, - HALMAC_HW_HCPWM = 7, - HALMAC_HW_HRPWM2 = 8, - HALMAC_HW_HCPWM2 = 9, - HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 10, - HALMAC_HW_TXFF_ALLOCATION = 11, - HALMAC_HW_USB_MODE = 12, - HALMAC_HW_SEQ_EN = 13, - HALMAC_HW_BANDWIDTH = 14, - HALMAC_HW_CHANNEL = 15, - HALMAC_HW_PRI_CHANNEL_IDX = 16, - HALMAC_HW_EN_BB_RF = 17, - HALMAC_HW_BT_BANK_EFUSE_SIZE = 18, - HALMAC_HW_BT_BANK1_EFUSE_SIZE = 19, - HALMAC_HW_BT_BANK2_EFUSE_SIZE = 20, + /* Get HW value */ + HALMAC_HW_RQPN_MAPPING = 0x00, + HALMAC_HW_EFUSE_SIZE = 0x01, + HALMAC_HW_EEPROM_SIZE = 0x02, + HALMAC_HW_BT_BANK_EFUSE_SIZE = 0x03, + HALMAC_HW_BT_BANK1_EFUSE_SIZE = 0x04, + HALMAC_HW_BT_BANK2_EFUSE_SIZE = 0x05, + HALMAC_HW_TXFIFO_SIZE = 0x06, + HALMAC_HW_RSVD_PG_BNDY = 0x07, + HALMAC_HW_CAM_ENTRY_NUM = 0x08, + HALMAC_HW_IC_VERSION = 0x09, + HALMAC_HW_PAGE_SIZE = 0x0A, + HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0B, + HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0C, + HALMAC_HW_DRV_INFO_SIZE = 0x0D, + HALMAC_HW_TXFF_ALLOCATION = 0x0E, + HALMAC_HW_RSVD_EFUSE_SIZE = 0x0F, + HALMAC_HW_FW_HDR_SIZE = 0x10, + HALMAC_HW_TX_DESC_SIZE = 0x11, + HALMAC_HW_RX_DESC_SIZE = 0x12, + HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x13, + HALMAC_HW_AC_OQT_SIZE = 0x14, + HALMAC_HW_NON_AC_OQT_SIZE = 0x15, + HALMAC_HW_AC_QUEUE_NUM = 0x16, + /* Set HW value */ + HALMAC_HW_USB_MODE = 0x60, + HALMAC_HW_SEQ_EN = 0x61, + HALMAC_HW_BANDWIDTH = 0x62, + HALMAC_HW_CHANNEL = 0x63, + HALMAC_HW_PRI_CHANNEL_IDX = 0x64, + HALMAC_HW_EN_BB_RF = 0x65, + HALMAC_HW_SDIO_TX_PAGE_THRESHOLD = 0x66, + HALMAC_HW_AMPDU_CONFIG = 0x67, + HALMAC_HW_RX_SHIFT = 0x68, + HALMAC_HW_ID_UNDEFINE = 0x7F, } HALMAC_HW_ID; typedef enum _HALMAC_EFUSE_BANK { @@ -1656,6 +1742,42 @@ typedef enum _HALMAC_EFUSE_BANK { HALMAC_EFUSE_BANK_UNDEFINE = 0X7F, } HALMAC_EFUSE_BANK; +typedef enum _HALMAC_SDIO_SPEC_VER { + HALMAC_SDIO_SPEC_VER_2_00 = 0, + HALMAC_SDIO_SPEC_VER_3_00 = 1, + HALMAC_SDIO_SPEC_VER_UNDEFINE = 0X7F, +} HALMAC_SDIO_SPEC_VER; + +typedef enum _HALMAC_GPIO_FUNC { + HALMAC_GPIO_FUNC_WL_LED = 0, + HALMAC_GPIO_FUNC_SDIO_INT = 1, + HALMAC_GPIO_FUNC_SW_IO_0 = 2, + HALMAC_GPIO_FUNC_SW_IO_1 = 3, + HALMAC_GPIO_FUNC_SW_IO_2 = 4, + HALMAC_GPIO_FUNC_SW_IO_3 = 5, + HALMAC_GPIO_FUNC_SW_IO_4 = 6, + HALMAC_GPIO_FUNC_SW_IO_5 = 7, + HALMAC_GPIO_FUNC_SW_IO_6 = 8, + HALMAC_GPIO_FUNC_SW_IO_7 = 9, + HALMAC_GPIO_FUNC_SW_IO_8 = 10, + HALMAC_GPIO_FUNC_SW_IO_9 = 11, + HALMAC_GPIO_FUNC_SW_IO_10 = 12, + HALMAC_GPIO_FUNC_SW_IO_11 = 13, + HALMAC_GPIO_FUNC_SW_IO_12 = 14, + HALMAC_GPIO_FUNC_SW_IO_13 = 15, + HALMAC_GPIO_FUNC_SW_IO_14 = 16, + HALMAC_GPIO_FUNC_SW_IO_15 = 17, + HALMAC_GPIO_FUNC_UNDEFINE = 0X7F, +} HALMAC_GPIO_FUNC; + +typedef enum _HALMAC_WLLED_MODE { + HALMAC_WLLED_MODE_TRX = 0, + HALMAC_WLLED_MODE_TX = 1, + HALMAC_WLLED_MODE_RX = 2, + HALMAC_WLLED_MODE_SW_CTRL = 3, + HALMAC_WLLED_MODE_UNDEFINE = 0X7F, +} HALMAC_WLLED_MODE; + typedef struct _HALMAC_TXFF_ALLOCATION { u16 tx_fifo_pg_num; u16 rsvd_pg_num; @@ -1673,6 +1795,7 @@ typedef struct _HALMAC_TXFF_ALLOCATION { u16 rsvd_cpu_instr_pg_bndy; u16 rsvd_fw_txbuff_pg_bndy; HALMAC_LA_MODE la_mode; + HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode; } HALMAC_TXFF_ALLOCATION, *PHALMAC_TXFF_ALLOCATION; typedef struct _HALMAC_RQPN_MAP { @@ -1684,12 +1807,122 @@ typedef struct _HALMAC_RQPN_MAP { HALMAC_DMA_MAPPING dma_map_hi; } HALMAC_RQPN_MAP, *PHALMAC_RQPN_MAP; +typedef struct _HALMAC_SECURITY_SETTING { + u8 tx_encryption; + u8 rx_decryption; + u8 bip_enable; +} HALMAC_SECURITY_SETTING, *PHALMAC_SECURITY_SETTING; + +typedef struct _HALMAC_CAM_ENTRY_INFO { + HAL_SECURITY_TYPE security_type; + u32 key[4]; + u32 key_ext[4]; + u8 mac_address[6]; + u8 unicast; + u8 key_id; + u8 valid; +} HALMAC_CAM_ENTRY_INFO, *PHALMAC_CAM_ENTRY_INFO; + +typedef struct _HALMAC_CAM_ENTRY_FORMAT { + u16 key_id : 2; + u16 type : 3; + u16 mic : 1; + u16 grp : 1; + u16 spp_mode : 1; + u16 rpt_md : 1; + u16 ext_sectype : 1; + u16 mgnt : 1; + u16 rsvd1 : 4; + u16 valid : 1; + u8 mac_address[6]; + u32 key[4]; + u32 rsvd[2]; +} HALMAC_CAM_ENTRY_FORMAT, *PHALMAC_CAM_ENTRY_FORMAT; + +typedef struct _HALMAC_TX_PAGE_THRESHOLD_INFO { + u32 threshold; + HALMAC_DMA_MAPPING dma_queue_sel; + u8 enable; +} HALMAC_TX_PAGE_THRESHOLD_INFO, *PHALMAC_TX_PAGE_THRESHOLD_INFO; + +typedef struct _HALMAC_AMPDU_CONFIG { + u8 max_agg_num; +} HALMAC_AMPDU_CONFIG, *PHALMAC_AMPDU_CONFIG; + +typedef struct _HALMAC_RQPN_ { + HALMAC_TRX_MODE mode; + HALMAC_DMA_MAPPING dma_map_vo; + HALMAC_DMA_MAPPING dma_map_vi; + HALMAC_DMA_MAPPING dma_map_be; + HALMAC_DMA_MAPPING dma_map_bk; + HALMAC_DMA_MAPPING dma_map_mg; + HALMAC_DMA_MAPPING dma_map_hi; +} HALMAC_RQPN, *PHALMAC_RQPN; + +typedef struct _HALMAC_PG_NUM_ { + HALMAC_TRX_MODE mode; + u16 hq_num; + u16 nq_num; + u16 lq_num; + u16 exq_num; + u16 gap_num;/*used for loopback mode*/ +} HALMAC_PG_NUM, *PHALMAC_PG_NUM; + +typedef struct _HALMAC_INTF_PHY_PARA_ { + u16 offset; + u16 value; + u16 ip_sel; + u16 cut; + u16 plaform; +} HALMAC_INTF_PHY_PARA, *PHALMAC_INTF_PHY_PARA; + +typedef struct _HALMAC_IQK_PARA_ { + u8 clear; + u8 segment_iqk; +} HALMAC_IQK_PARA, *PHALMAC_IQK_PARA; + +typedef struct _HALMAC_SDIO_HW_INFO { + HALMAC_SDIO_SPEC_VER spec_ver; + u32 clock_speed; + u8 io_hi_speed_flag; /* Halmac internal use */ +} HALMAC_SDIO_HW_INFO, *PHALMAC_SDIO_HW_INFO; + +typedef struct _HALMAC_EDCA_PARA { + u8 aifs; + u8 cw; + u16 txop_limit; +} HALMAC_EDCA_PARA, *PHALMAC_EDCA_PARA; + +typedef struct _HALMAC_PINMUX_INFO { + /* byte0 */ + u8 wl_led:1; + u8 sdio_int:1; + u8 rsvd1:6; + /* byte1 */ + u8 sw_io_0:1; + u8 sw_io_1:1; + u8 sw_io_2:1; + u8 sw_io_3:1; + u8 sw_io_4:1; + u8 sw_io_5:1; + u8 sw_io_6:1; + u8 sw_io_7:1; + /* byte2 */ + u8 sw_io_8:1; + u8 sw_io_9:1; + u8 sw_io_10:1; + u8 sw_io_11:1; + u8 sw_io_12:1; + u8 sw_io_13:1; + u8 sw_io_14:1; + u8 sw_io_15:1; +} HALMAC_PINMUX_INFO, *PHALMAC_PINMUX_INFO; + /* Hal mac adapter */ typedef struct _HALMAC_ADAPTER { HALMAC_DMA_MAPPING halmac_ptcl_queue[HALMAC_PTCL_QUEUE_NUM]; /* Dma mapping of protocol queues */ - HALMAC_FWLPS_OPTION fwlps_option; /* low power state option */ - HALMAC_WLAN_ADDR pHal_mac_addr[2]; /* mac address information, suppot 2 ports */ - HALMAC_WLAN_ADDR pHal_bss_addr[2]; /* bss address information, suppot 2 ports */ + HALMAC_WLAN_ADDR pHal_mac_addr[HALMAC_PORTIDMAX]; /* mac address information, suppot 2 ports */ + HALMAC_WLAN_ADDR pHal_bss_addr[HALMAC_PORTIDMAX]; /* bss address information, suppot 2 ports */ HALMAC_MUTEX h2c_seq_mutex; /* Protect h2c_packet_seq packet*/ HALMAC_MUTEX EfuseMutex; /* Protect Efuse map memory of halmac_adapter */ HALMAC_CONFIG_PARA_INFO config_para_info; @@ -1698,6 +1931,7 @@ typedef struct _HALMAC_ADAPTER { HALMAC_HW_CONFIG_INFO hw_config_info; /* HW related information */ HALMAC_SDIO_FREE_SPACE sdio_free_space; HALMAC_SND_INFO snd_info; + HALMAC_PINMUX_INFO pinmux_info; VOID *pHalAdapter_backup; /* Backup HalAdapter address */ VOID *pDriver_adapter; /* Driver or FW adapter address. Do not write this memory*/ u8 *pHalEfuse_map; @@ -1721,9 +1955,12 @@ typedef struct _HALMAC_ADAPTER { u8 rpwm_record; /* record rpwm value */ u8 low_clk; /*LPS 32K or IPS 32K*/ u8 halmac_bulkout_num; /* USB bulkout num */ - HALMAC_API_RECORD api_record; /* API record */ u8 gen_info_valid; HALMAC_GENERAL_INFO general_info; + u8 drv_info_size; + HALMAC_SDIO_CMD53_4BYTE_MODE sdio_cmd53_4byte; + HALMAC_SDIO_HW_INFO sdio_hw_info; + u8 efuse_auto_check_en; #if HALMAC_PLATFORM_TESTPROGRAM HALMAC_TXAGG_BUFF_INFO halmac_tx_buf_info[4]; HALMAC_MUTEX agg_buff_mutex; /*used for tx_agg_buffer */ @@ -1733,10 +1970,11 @@ typedef struct _HALMAC_ADAPTER { } HALMAC_ADAPTER, *PHALMAC_ADAPTER; -/* Fuction pointer of Hal mac API */ +/* Function pointer of Hal mac API */ typedef struct _HALMAC_API { HALMAC_RET_STATUS (*halmac_mac_power_switch)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_MAC_POWER halmac_power); HALMAC_RET_STATUS (*halmac_download_firmware)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size); + HALMAC_RET_STATUS (*halmac_free_download_firmware)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DLFW_MEM dlfw_mem, u8 *pHamacl_fw, u32 halmac_fw_size); HALMAC_RET_STATUS (*halmac_get_fw_version)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FW_VERSION pFw_version); HALMAC_RET_STATUS (*halmac_cfg_mac_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address); HALMAC_RET_STATUS (*halmac_cfg_bssid)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address); @@ -1762,24 +2000,21 @@ typedef struct _HALMAC_API { HALMAC_RET_STATUS (*halmac_deinit_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter); HALMAC_RET_STATUS (*halmac_deinit_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter); HALMAC_RET_STATUS (*halmac_get_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size); + HALMAC_RET_STATUS (*halmac_get_efuse_available_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size); HALMAC_RET_STATUS (*halmac_dump_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg); HALMAC_RET_STATUS (*halmac_dump_efuse_map_bt)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank, u32 bt_efuse_map_size, u8 *pBT_efuse_map); HALMAC_RET_STATUS (*halmac_write_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value); HALMAC_RET_STATUS (*halmac_read_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue); HALMAC_RET_STATUS (*halmac_switch_efuse_bank)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank); HALMAC_RET_STATUS (*halmac_write_efuse_bt)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value, HALMAC_EFUSE_BANK halmac_efues_bank); + HALMAC_RET_STATUS (*halmac_read_efuse_bt)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue, HALMAC_EFUSE_BANK halmac_efues_bank); + HALMAC_RET_STATUS (*halmac_cfg_efuse_auto_check)(PHALMAC_ADAPTER pHalmac_adapter, u8 enable); HALMAC_RET_STATUS (*halmac_get_logical_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size); HALMAC_RET_STATUS (*halmac_dump_logical_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg); HALMAC_RET_STATUS (*halmac_write_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value); HALMAC_RET_STATUS (*halmac_read_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue); HALMAC_RET_STATUS (*halmac_pg_efuse_by_map)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PG_EFUSE_INFO pPg_efuse_info, HALMAC_EFUSE_READ_CFG cfg); HALMAC_RET_STATUS (*halmac_get_c2h_info)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size); - HALMAC_RET_STATUS (*halmac_cfg_fwlps_option)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FWLPS_OPTION pLps_option); - HALMAC_RET_STATUS (*halmac_cfg_fwips_option)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FWIPS_OPTION pIps_option); - HALMAC_RET_STATUS (*halmac_enter_wowlan)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_WOWLAN_OPTION pWowlan_option); - HALMAC_RET_STATUS (*halmac_leave_wowlan)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_enter_ps)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PS_STATE ps_state); - HALMAC_RET_STATUS (*halmac_leave_ps)(PHALMAC_ADAPTER pHalmac_adapter); HALMAC_RET_STATUS (*halmac_h2c_lb)(PHALMAC_ADAPTER pHalmac_adapter); HALMAC_RET_STATUS (*halmac_debug)(PHALMAC_ADAPTER pHalmac_adapter); HALMAC_RET_STATUS (*halmac_cfg_parameter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PHY_PARAMETER_INFO para_info, u8 full_fifo); @@ -1790,6 +2025,8 @@ typedef struct _HALMAC_API { u16 (*halmac_reg_read_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); HALMAC_RET_STATUS (*halmac_reg_write_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u16 halmac_data); u32 (*halmac_reg_read_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); + u32 (*halmac_reg_read_indirect_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); + u8 (*halmac_reg_sdio_cmd53_read_n)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_size, u8 *halmac_data); HALMAC_RET_STATUS (*halmac_reg_write_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_data); HALMAC_RET_STATUS (*halmac_tx_allowed_sdio)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size); HALMAC_RET_STATUS (*halmac_set_bulkout_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 bulkout_num); @@ -1803,7 +2040,7 @@ typedef struct _HALMAC_API { HALMAC_RET_STATUS (*halmac_send_bt_coex)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBt_buf, u32 bt_size, u8 ack); HALMAC_RET_STATUS (*halmac_verify_platform_api)(PHALMAC_ADAPTER pHalmac_adapte); u32 (*halmac_get_fifo_size)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel); - HALMAC_RET_STATUS (*halmac_dump_fifo)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel, u8 *pFifo_map, u32 halmac_fifo_dump_size); + HALMAC_RET_STATUS (*halmac_dump_fifo)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel, u32 halmac_start_addr, u32 halmac_fifo_dump_size, u8 *pFifo_map); HALMAC_RET_STATUS (*halmac_cfg_txbf)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, HALMAC_BW bw, u8 txbf_en); HALMAC_RET_STATUS (*halmac_cfg_mumimo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CFG_MUMIMO_PARA pCfgmu); HALMAC_RET_STATUS (*halmac_cfg_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role, HALMAC_DATA_RATE datarate); @@ -1819,9 +2056,10 @@ typedef struct _HALMAC_API { HALMAC_RET_STATUS (*halmac_add_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_INFO pCh_info); HALMAC_RET_STATUS (*halmac_add_extra_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_EXTRA_INFO pCh_extra_info); HALMAC_RET_STATUS (*halmac_ctrl_ch_switch)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_SWITCH_OPTION pCs_option); + HALMAC_RET_STATUS (*halmac_p2pps)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_P2PPS pP2PPS); HALMAC_RET_STATUS (*halmac_clear_ch_info)(PHALMAC_ADAPTER pHalmac_adapter); HALMAC_RET_STATUS (*halmac_send_general_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_GENERAL_INFO pgGeneral_info); - HALMAC_RET_STATUS (*halmac_start_iqk)(PHALMAC_ADAPTER pHalmac_adapter, u8 clear); + HALMAC_RET_STATUS (*halmac_start_iqk)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_IQK_PARA pIqk_para); HALMAC_RET_STATUS (*halmac_ctrl_pwr_tracking)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt); HALMAC_RET_STATUS (*halmac_psd)(PHALMAC_ADAPTER pHalmac_adapter, u16 start_psd, u16 end_psd); HALMAC_RET_STATUS (*halmac_cfg_tx_agg_align)(PHALMAC_ADAPTER pHalmac_adapter, u8 enable, u16 align_size); @@ -1831,11 +2069,39 @@ typedef struct _HALMAC_API { HALMAC_RET_STATUS (*halmac_dump_fw_dmem)(PHALMAC_ADAPTER pHalmac_adapter, u8 *dmem, u32 *size); HALMAC_RET_STATUS (*halmac_cfg_max_dl_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 size); HALMAC_RET_STATUS (*halmac_cfg_la_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_LA_MODE la_mode); + HALMAC_RET_STATUS (*halmac_cfg_rx_fifo_expanding_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode); + HALMAC_RET_STATUS (*halmac_config_security)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SECURITY_SETTING pSec_setting); + u8 (*halmac_get_used_cam_entry_num)(PHALMAC_ADAPTER pHalmac_adapter, HAL_SECURITY_TYPE sec_type); + HALMAC_RET_STATUS (*halmac_write_cam)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_INFO pCam_entry_info); + HALMAC_RET_STATUS (*halmac_read_cam_entry)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_FORMAT pContent); + HALMAC_RET_STATUS (*halmac_clear_cam_entry)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index); HALMAC_RET_STATUS (*halmac_get_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue); HALMAC_RET_STATUS (*halmac_set_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue); HALMAC_RET_STATUS (*halmac_cfg_drv_rsvd_pg_num)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_RSVD_PG_NUM pg_num); - HALMAC_RET_STATUS (*halmac_get_chip_version)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_VER *version); + HALMAC_RET_STATUS (*halmac_get_chip_version)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_VER version); HALMAC_RET_STATUS (*halmac_chk_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size); + HALMAC_RET_STATUS (*halmac_dl_drv_rsvd_page)(PHALMAC_ADAPTER pHalmac_adapter, u8 pg_offset, u8 *pHal_buf, u32 size); + HALMAC_RET_STATUS (*halmac_pcie_switch)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PCIE_CFG pcie_cfg); + HALMAC_RET_STATUS (*halmac_phy_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_INTF_PHY_PLATFORM platform); + HALMAC_RET_STATUS (*halmac_cfg_csi_rate)(PHALMAC_ADAPTER pHalmac_adapter, u8 rssi, u8 current_rate, u8 fixrate_en, u8 *new_rate); + HALMAC_RET_STATUS (*halmac_sdio_cmd53_4byte)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SDIO_CMD53_4BYTE_MODE cmd53_4byte_mode); + HALMAC_RET_STATUS (*halmac_sdio_hw_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SDIO_HW_INFO pSdio_hw_info); + HALMAC_RET_STATUS (*halmac_interface_integration_tuning)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS (*halmac_txfifo_is_empty)(PHALMAC_ADAPTER pHalmac_adapter, u32 chk_num); + HALMAC_RET_STATUS (*halmac_download_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address); + HALMAC_RET_STATUS (*halmac_read_flash)(PHALMAC_ADAPTER pHalmac_adapter, u32 addr); + HALMAC_RET_STATUS (*halmac_erase_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 erase_cmd, u32 addr); + HALMAC_RET_STATUS (*halmac_check_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_fw, u32 halmac_fw_size, u32 addr); + HALMAC_RET_STATUS (*halmac_cfg_edca_para)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_ACQ_ID acq_id, PHALMAC_EDCA_PARA pEdca_para); + HALMAC_RET_STATUS (*halmac_pinmux_get_func)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_GPIO_FUNC gpio_func, u8 *pEnable); + HALMAC_RET_STATUS (*halmac_pinmux_set_func)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_GPIO_FUNC gpio_func); + HALMAC_RET_STATUS (*halmac_pinmux_free_func)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_GPIO_FUNC gpio_func); + HALMAC_RET_STATUS (*halmac_pinmux_wl_led_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_WLLED_MODE wlled_mode); + VOID (*halmac_pinmux_wl_led_sw_ctrl)(PHALMAC_ADAPTER pHalmac_adapter, u8 led_on); + VOID (*halmac_pinmux_sdio_int_polarity)(PHALMAC_ADAPTER pHalmac_adapter, u8 low_active); + HALMAC_RET_STATUS (*halmac_pinmux_gpio_mode)(PHALMAC_ADAPTER pHalmac_adapter, u8 gpio_id, u8 output); + HALMAC_RET_STATUS (*halmac_pinmux_gpio_output)(PHALMAC_ADAPTER pHalmac_adapter, u8 gpio_id, u8 high); + HALMAC_RET_STATUS (*halmac_pinmux_pin_status)(PHALMAC_ADAPTER pHalmac_adapter, u8 gpio_id, u8 *pHigh); #if HALMAC_PLATFORM_TESTPROGRAM HALMAC_RET_STATUS (*halmac_gen_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pPcket_buffer, PHAL_TXDESC_INFO pTxdesc_info); HALMAC_RET_STATUS (*halmac_txdesc_parser)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pTxdesc, PHAL_TXDESC_PARSER pTxdesc_parser); @@ -1854,9 +2120,6 @@ typedef struct _HALMAC_API { HALMAC_RET_STATUS (*halmac_init_crystal_capacity)(PHALMAC_ADAPTER pHalmac_adapter); HALMAC_RET_STATUS (*halmac_trx_antenna_setting)(PHALMAC_ADAPTER pHalmac_adapter); HALMAC_RET_STATUS (*halmac_himr_setting_sdio)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SDIO_HIMR_INFO sdio_himr_sdio); - HALMAC_RET_STATUS (*halmac_config_security)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_SECURITY_INFO pSecurity_info); - HALMAC_RET_STATUS (*halmac_write_cam)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_INFO pCam_entry_info); - HALMAC_RET_STATUS (*halmac_read_cam)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_FORMAT pContent); HALMAC_RET_STATUS (*halmac_dump_cam_table)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_num, PHALMAC_CAM_ENTRY_FORMAT pCam_table); HALMAC_RET_STATUS (*halmac_load_cam_table)(PHALMAC_ADAPTER pHalmac_adapter, u8 entry_num, PHALMAC_CAM_ENTRY_FORMAT pCam_table); HALMAC_RET_STATUS (*halmac_send_beacon)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_BEACON_INFO pbeacon_info); @@ -1864,19 +2127,21 @@ typedef struct _HALMAC_API { HALMAC_RET_STATUS (*halmac_send_control)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_CTRL_INFO pctrl_info); HALMAC_RET_STATUS (*halmac_send_hiqueue)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_HIGH_QUEUE_INFO pHigh_info); HALMAC_RET_STATUS (*halmac_run_pwrseq)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PWR_SEQ_ID seq); - HALMAC_RET_STATUS (*halmac_media_status_rpt)(PHALMAC_ADAPTER pHalmac_adapter, u8 op_mode, u8 mac_id_ind, u8 mac_id, u8 mac_id_end); HALMAC_RET_STATUS (*halmac_stop_beacon)(PHALMAC_ADAPTER pHalmac_adapter); HALMAC_RET_STATUS (*halmac_check_trx_status)(PHALMAC_ADAPTER pHalmac_adapter); HALMAC_RET_STATUS (*halmac_set_agg_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 agg_num); HALMAC_RET_STATUS (*halmac_timer_10ms)(PHALMAC_ADAPTER pHalmac_adapter); HALMAC_RET_STATUS (*halmac_download_firmware_fpag)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 iram_address); HALMAC_RET_STATUS (*halmac_download_rom_fpga)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address); - HALMAC_RET_STATUS (*halmac_download_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address); - HALMAC_RET_STATUS (*halmac_erase_flash)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_check_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size); HALMAC_RET_STATUS (*halmac_send_nlo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_NLO_CFG pNlo_cfg); HALMAC_RET_STATUS (*halmac_get_chip_type)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CHIP_TYPE pChip_type); u32 (*halmac_get_rx_agg_num)(PHALMAC_ADAPTER pHalmac_adapter, u32 pkt_size, u8 *pPkt_buff); + u8 (*halmac_check_rx_scsi_resp)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pRxdesc, PHAL_RXDESC_PARSER pRxdesc_parser); + VOID (*halmac_get_hcpwm)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHcpwm); + VOID (*halmac_get_hcpwm2)(PHALMAC_ADAPTER pHalmac_adapter, u16 *pHcpwm2); + VOID (*halmac_set_hrpwm)(PHALMAC_ADAPTER pHalmac_adapter, u8 hrpwm); + VOID (*halmac_set_hrpwm2)(PHALMAC_ADAPTER pHalmac_adapter, u16 hrpwm2); + HALMAC_RET_STATUS (*halmac_coex_cfg)(PHALMAC_ADAPTER pHalmac_adapter); #endif } HALMAC_API, *PHALMAC_API; @@ -1887,7 +2152,7 @@ halmac_adapter_validate( PHALMAC_ADAPTER pHalmac_adapter ) { - if ((NULL == pHalmac_adapter) || (pHalmac_adapter->pHalAdapter_backup != pHalmac_adapter)) + if ((pHalmac_adapter == NULL) || (pHalmac_adapter->pHalAdapter_backup != pHalmac_adapter)) return HALMAC_RET_ADAPTER_INVALID; return HALMAC_RET_SUCCESS; @@ -1898,7 +2163,7 @@ halmac_api_validate( PHALMAC_ADAPTER pHalmac_adapter ) { - if (HALMAC_API_STATE_INIT != pHalmac_adapter->halmac_state.api_state) + if (pHalmac_adapter->halmac_state.api_state != HALMAC_API_STATE_INIT) return HALMAC_RET_API_INVALID; return HALMAC_RET_SUCCESS; @@ -1909,7 +2174,7 @@ halmac_fw_validate( PHALMAC_ADAPTER pHalmac_adapter ) { - if (HALMAC_DLFW_DONE != pHalmac_adapter->halmac_state.dlfw_state && HALMAC_GEN_INFO_SENT != pHalmac_adapter->halmac_state.dlfw_state) + if (pHalmac_adapter->halmac_state.dlfw_state != HALMAC_DLFW_DONE && pHalmac_adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT) return HALMAC_RET_NO_DLFW; return HALMAC_RET_SUCCESS; diff --git a/hal/halmac/halmac_usb_reg.h b/hal/halmac/halmac_usb_reg.h index 1ff9bde..b984670 100644 --- a/hal/halmac/halmac_usb_reg.h +++ b/hal/halmac/halmac_usb_reg.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __HALMAC_USB_REG_H__ #define __HALMAC_USB_REG_H__ diff --git a/hal/led/hal_usb_led.c b/hal/led/hal_usb_led.c index 72bacf6..41f1f6a 100644 --- a/hal/led/hal_usb_led.c +++ b/hal/led/hal_usb_led.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #include @@ -38,10 +33,8 @@ SwLedBlink( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { SwLedOff(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } /* Determine if we shall change LED state again. */ @@ -140,10 +133,8 @@ SwLedBlink1( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { SwLedOff(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } @@ -154,14 +145,12 @@ SwLedBlink1( pLed1->bSWLedCtrl = _TRUE; } else if (!pLed1->bLedOn) SwLedOn(padapter, pLed1); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (): turn on pLed1\n")); } else { if (!pLed1->bSWLedCtrl) { SwLedOff(padapter, pLed1); pLed1->bSWLedCtrl = _TRUE; } else if (pLed1->bLedOn) SwLedOff(padapter, pLed1); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (): turn off pLed1\n")); } } @@ -198,7 +187,6 @@ SwLedBlink1( else pLed->BlinkingLedState = RTW_LED_ON; _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) { pLed->bLedNoLinkBlinkInProgress = _TRUE; @@ -208,7 +196,6 @@ SwLedBlink1( else pLed->BlinkingLedState = RTW_LED_ON; _set_timer(&(pLed->BlinkTimer), uLedBlinkNoLinkInterval); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } pLed->bLedScanBlinkInProgress = _FALSE; } else { @@ -239,7 +226,6 @@ SwLedBlink1( else pLed->BlinkingLedState = RTW_LED_ON; _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) { pLed->bLedNoLinkBlinkInProgress = _TRUE; pLed->CurrLedState = LED_BLINK_SLOWLY; @@ -248,7 +234,6 @@ SwLedBlink1( else pLed->BlinkingLedState = RTW_LED_ON; _set_timer(&(pLed->BlinkTimer), uLedBlinkNoLinkInterval); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } pLed->BlinkTimes = 0; pLed->bLedBlinkInProgress = _FALSE; @@ -292,7 +277,6 @@ SwLedBlink1( else pLed->BlinkingLedState = RTW_LED_ON; _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } pLed->bLedWPSBlinkInProgress = _FALSE; } @@ -316,10 +300,8 @@ SwLedBlink2( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { SwLedOff(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } switch (pLed->CurrLedState) { @@ -335,13 +317,11 @@ SwLedBlink2( pLed->CurrLedState = RTW_LED_ON; pLed->BlinkingLedState = RTW_LED_ON; SwLedOn(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("stop scan blink CurrLedState %d\n", pLed->CurrLedState)); } else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) { pLed->CurrLedState = RTW_LED_OFF; pLed->BlinkingLedState = RTW_LED_OFF; SwLedOff(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("stop scan blink CurrLedState %d\n", pLed->CurrLedState)); } pLed->bLedScanBlinkInProgress = _FALSE; } else { @@ -368,13 +348,11 @@ SwLedBlink2( pLed->CurrLedState = RTW_LED_ON; pLed->BlinkingLedState = RTW_LED_ON; SwLedOn(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("stop CurrLedState %d\n", pLed->CurrLedState)); } else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) { pLed->CurrLedState = RTW_LED_OFF; pLed->BlinkingLedState = RTW_LED_OFF; SwLedOff(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("stop CurrLedState %d\n", pLed->CurrLedState)); } pLed->bLedBlinkInProgress = _FALSE; } else { @@ -408,11 +386,9 @@ SwLedBlink3( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { if (pLed->CurrLedState != LED_BLINK_WPS_STOP) SwLedOff(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } switch (pLed->CurrLedState) { @@ -430,14 +406,12 @@ SwLedBlink3( if (!pLed->bLedOn) SwLedOn(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) { pLed->CurrLedState = RTW_LED_OFF; pLed->BlinkingLedState = RTW_LED_OFF; if (pLed->bLedOn) SwLedOff(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } pLed->bLedScanBlinkInProgress = _FALSE; } else { @@ -467,7 +441,6 @@ SwLedBlink3( if (!pLed->bLedOn) SwLedOn(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) { pLed->CurrLedState = RTW_LED_OFF; pLed->BlinkingLedState = RTW_LED_OFF; @@ -476,7 +449,6 @@ SwLedBlink3( SwLedOff(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } pLed->bLedBlinkInProgress = _FALSE; } else { @@ -515,7 +487,6 @@ SwLedBlink3( pLed->CurrLedState = RTW_LED_ON; pLed->BlinkingLedState = RTW_LED_ON; SwLedOn(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } pLed->bLedWPSBlinkInProgress = _FALSE; } @@ -543,10 +514,8 @@ SwLedBlink4( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { SwLedOff(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } if (!pLed1->bLedWPSBlinkInProgress && pLed1->BlinkingLedState == LED_UNKNOWN) { @@ -699,7 +668,6 @@ SwLedBlink4( pLed->bLedBlinkInProgress = _FALSE; } else { if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) { - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("RFOff Status\n")); SwLedOff(padapter, pLed); } else { if (pLed->bLedOn) @@ -716,7 +684,6 @@ SwLedBlink4( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SwLedBlink4 CurrLedState %d\n", pLed->CurrLedState)); } @@ -733,10 +700,8 @@ SwLedBlink5( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { SwLedOff(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } switch (pLed->CurrLedState) { @@ -809,7 +774,6 @@ SwLedBlink5( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SwLedBlink5 CurrLedState %d\n", pLed->CurrLedState)); } @@ -826,13 +790,10 @@ SwLedBlink6( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { SwLedOff(padapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("<==== blink6\n")); } void @@ -847,11 +808,9 @@ SwLedBlink7( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { if (pLed->CurrLedState != LED_BLINK_WPS_STOP) SwLedOff(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } switch (pLed->CurrLedState) { @@ -869,14 +828,12 @@ SwLedBlink7( if (!pLed->bLedOn) SwLedOn(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) { pLed->CurrLedState = RTW_LED_OFF; pLed->BlinkingLedState = RTW_LED_OFF; if (pLed->bLedOn) SwLedOff(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } pLed->bLedScanBlinkInProgress = _FALSE; } else { @@ -915,7 +872,6 @@ SwLedBlink7( pLed->CurrLedState = RTW_LED_ON; pLed->BlinkingLedState = RTW_LED_ON; SwLedOn(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } pLed->bLedWPSBlinkInProgress = _FALSE; } @@ -926,7 +882,6 @@ SwLedBlink7( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("<==== blink7\n")); } @@ -940,13 +895,10 @@ SwLedBlink8( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes blink8(%d): turn on\n", pLed->BlinkTimes)); } else { SwLedOff(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes blink8(%d): turn off\n", pLed->BlinkTimes)); } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("<==== blink8\n")); } @@ -963,10 +915,8 @@ SwLedBlink9( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { SwLedOff(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } /* RTW_INFO("%s, pLed->CurrLedState=%d, pLed->BlinkingLedState=%d\n", __FUNCTION__, pLed->CurrLedState, pLed->BlinkingLedState); */ @@ -1011,7 +961,6 @@ SwLedBlink9( pLed->CurrLedState = LED_BLINK_SLOWLY; _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) { pLed->bLedNoLinkBlinkInProgress = _TRUE; pLed->CurrLedState = LED_BLINK_SLOWLY; @@ -1020,7 +969,6 @@ SwLedBlink9( else pLed->BlinkingLedState = RTW_LED_ON; _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } pLed->BlinkTimes = 0; pLed->bLedBlinkInProgress = _FALSE; @@ -1140,7 +1088,6 @@ SwLedBlink9( pLed->bLedBlinkInProgress = _FALSE; } else { if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) { - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("RFOff Status\n")); SwLedOff(Adapter, pLed); } else { if (IS_HARDWARE_TYPE_8812AU(Adapter)) @@ -1189,7 +1136,6 @@ SwLedBlink9( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SwLedBlink9 CurrLedState %d\n", pLed->CurrLedState)); } /* page added for Netgear A6200V2. 20120827 */ @@ -1205,10 +1151,8 @@ SwLedBlink10( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { SwLedOff(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } @@ -1253,7 +1197,6 @@ SwLedBlink10( pLed->BlinkingLedState = RTW_LED_OFF; _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } pLed->BlinkTimes = 0; pLed->bLedBlinkInProgress = _FALSE; @@ -1345,7 +1288,6 @@ SwLedBlink10( pLed->bLedBlinkInProgress = _FALSE; } else { if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) { - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("RFOff Status\n")); SwLedOff(Adapter, pLed); } else { if (IS_HARDWARE_TYPE_8812AU(Adapter)) @@ -1394,7 +1336,6 @@ SwLedBlink10( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SwLedBlink10 CurrLedState %d\n", pLed->CurrLedState)); } @@ -1410,10 +1351,8 @@ SwLedBlink11( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { SwLedOff(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } switch (pLed->CurrLedState) { @@ -1469,7 +1408,6 @@ SwLedBlink11( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SwLedBlink5 CurrLedState %d\n", pLed->CurrLedState)); } void @@ -1484,10 +1422,8 @@ SwLedBlink12( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%ld): turn on\n", pLed->BlinkTimes)); } else { SwLedOff(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%ld): turn off\n", pLed->BlinkTimes)); } switch (pLed->CurrLedState) { @@ -1538,7 +1474,6 @@ SwLedBlink12( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SwLedBlink8 CurrLedState %d\n", pLed->CurrLedState)); } @@ -1556,14 +1491,10 @@ SwLedBlink13( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { if (pLed->CurrLedState != LED_BLINK_WPS_STOP) SwLedOff(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("!!! SwLedBlink13 CurrLedState %d, bLedWPSBlinkInProgress %d, bLedBlinkInProgress %d\n", pLed->CurrLedState, pLed->bLedWPSBlinkInProgress, - pLed->bLedBlinkInProgress)); switch (pLed->CurrLedState) { case LED_BLINK_LINK_IN_PROCESS: if (!pLed->bLedWPSBlinkInProgress) @@ -1605,7 +1536,6 @@ SwLedBlink13( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("<==== blink13\n")); } @@ -1622,14 +1552,10 @@ SwLedBlink14( /* Change LED according to BlinkingLedState specified. */ if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { if (pLed->CurrLedState != LED_BLINK_WPS_STOP) SwLedOff(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("!!! SwLedBlink14 CurrLedState %d, bLedWPSBlinkInProgress %d, bLedBlinkInProgress %d\n", pLed->CurrLedState, pLed->bLedWPSBlinkInProgress, - pLed->bLedBlinkInProgress)); switch (pLed->CurrLedState) { case LED_BLINK_TXRX: pLed->BlinkTimes--; @@ -1668,7 +1594,6 @@ SwLedBlink14( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("<==== blink14\n")); } VOID @@ -1684,14 +1609,10 @@ SwLedBlink15( if (pLed->BlinkingLedState == RTW_LED_ON) { SwLedOn(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); } else { if (pLed->CurrLedState != LED_BLINK_WPS_STOP) SwLedOff(Adapter, pLed); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("!!! SwLedBlink15 CurrLedState %d, bLedWPSBlinkInProgress %d, bLedBlinkInProgress %d\n", pLed->CurrLedState, pLed->bLedWPSBlinkInProgress, - pLed->bLedBlinkInProgress)); switch (pLed->CurrLedState) { case LED_BLINK_WPS: if (pLed->bLedOn) { @@ -1704,7 +1625,6 @@ SwLedBlink15( break; case LED_BLINK_WPS_STOP: /* WPS success */ - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("blink15, LED_BLINK_WPS_STOP BlinkingLedState %d\n", pLed->BlinkingLedState)); if (pLed->BlinkingLedState == RTW_LED_OFF) { pLed->bLedWPSBlinkInProgress = _FALSE; @@ -1719,7 +1639,6 @@ SwLedBlink15( case LED_BLINK_NO_LINK: { static BOOLEAN bLedOn = _TRUE; - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("blink15, LED_NO_LINK_BLINK bLedOn %d\n", bLedOn)); if (bLedOn) { bLedOn = _FALSE; pLed->BlinkingLedState = RTW_LED_OFF; @@ -1734,7 +1653,6 @@ SwLedBlink15( case LED_BLINK_LINK_IDEL: { static BOOLEAN bLedOn = _TRUE; - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("blink15, LED_BLINK_LINK_IDEL bLedOn %d\n", bLedOn)); if (bLedOn) { bLedOn = _FALSE; pLed->BlinkingLedState = RTW_LED_OFF; @@ -1750,7 +1668,6 @@ SwLedBlink15( case LED_BLINK_SCAN: { static u8 BlinkTime = 0; - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("blink15, LED_SCAN_BLINK bLedOn %d\n", BlinkTime)); if (BlinkTime % 2 == 0) pLed->BlinkingLedState = RTW_LED_ON; else @@ -1805,7 +1722,6 @@ SwLedBlink15( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("<==== blink15\n")); } /* @@ -1894,7 +1810,6 @@ void BlinkHandler(PLED_USB pLed) break; default: - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("BlinkWorkItemCallback 0x%x\n", ledpriv->LedStrategy)); /* SwLedBlink(pLed); */ break; } @@ -2036,7 +1951,6 @@ SwLedControlMode0( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led %d\n", pLed->CurrLedState)); } @@ -2275,7 +2189,6 @@ SwLedControlMode1( } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led %d\n", pLed->CurrLedState)); } /* Arcadyan/Sitecom , added by chiyoko, 20090216 */ @@ -2372,7 +2285,6 @@ SwLedControlMode2( pLed->CurrLedState = RTW_LED_ON; pLed->BlinkingLedState = RTW_LED_ON; _set_timer(&(pLed->BlinkTimer), 0); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } break; @@ -2381,7 +2293,6 @@ SwLedControlMode2( pLed->CurrLedState = RTW_LED_OFF; pLed->BlinkingLedState = RTW_LED_OFF; _set_timer(&(pLed->BlinkTimer), 0); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); break; case LED_CTL_START_TO_LINK: @@ -2417,7 +2328,6 @@ SwLedControlMode2( } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } /* COREGA, added by chiyoko, 20090316 */ @@ -2572,7 +2482,6 @@ SwLedControlMode3( } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState)); } @@ -2877,7 +2786,6 @@ SwLedControlMode4( } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led %d\n", pLed->CurrLedState)); } @@ -2959,7 +2867,6 @@ SwLedControlMode5( } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led %d\n", pLed->CurrLedState)); } /* WNC-Corega, added by chiyoko, 20090902 */ @@ -2991,7 +2898,6 @@ SwLedControlMode6( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("ledcontrol 6 Led %d\n", pLed0->CurrLedState)); } /* Netgear, added by sinda, 2011/11/11 */ @@ -3132,7 +3038,6 @@ SwLedControlMode7( } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("LEd control mode 7 CurrLedState %d\n", pLed->CurrLedState)); } void @@ -3168,7 +3073,6 @@ SwLedControlMode8( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 8 %d\n", pLed0->CurrLedState)); } @@ -3472,7 +3376,6 @@ SwLedControlMode9( } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 9 Led %d\n", pLed->CurrLedState)); } /* page added for Netgear A6200V2, 20120827 */ @@ -3505,7 +3408,7 @@ SwLedControlMode10( if (pLed->bLedWPSBlinkInProgress == _TRUE || pLed1->bLedWPSBlinkInProgress == _TRUE) ; else { - if (pHalData->CurrentBandType == BAND_ON_2_4G) + if (pHalData->current_band_type == BAND_ON_2_4G) /* LED0 settings */ { pLed->CurrLedState = RTW_LED_ON; @@ -3519,7 +3422,7 @@ SwLedControlMode10( pLed1->CurrLedState = RTW_LED_OFF; pLed1->BlinkingLedState = RTW_LED_OFF; _set_timer(&(pLed1->BlinkTimer), 0); - } else if (pHalData->CurrentBandType == BAND_ON_5G) + } else if (pHalData->current_band_type == BAND_ON_5G) /* LED1 settings */ { pLed1->CurrLedState = RTW_LED_ON; @@ -3615,7 +3518,7 @@ SwLedControlMode10( break; case LED_CTL_STOP_WPS: /* WPS connect success */ - if (pHalData->CurrentBandType == BAND_ON_2_4G) + if (pHalData->current_band_type == BAND_ON_2_4G) /* LED0 settings */ { pLed->bLedWPSBlinkInProgress = _FALSE; @@ -3630,7 +3533,7 @@ SwLedControlMode10( pLed1->CurrLedState = RTW_LED_OFF; pLed1->BlinkingLedState = RTW_LED_OFF; _set_timer(&(pLed1->BlinkTimer), 0); - } else if (pHalData->CurrentBandType == BAND_ON_5G) + } else if (pHalData->current_band_type == BAND_ON_5G) /* LED1 settings */ { pLed1->bLedWPSBlinkInProgress = _FALSE; @@ -3671,7 +3574,6 @@ SwLedControlMode10( } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 10 Led %d\n", pLed->CurrLedState)); } /* Edimax-ASUS, added by Page, 20121221 */ @@ -3770,7 +3672,6 @@ SwLedControlMode11( } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led mode 1 CurrLedState %d\n", pLed->CurrLedState)); } /* page added for NEC */ @@ -3852,7 +3753,6 @@ SwLedControlMode12( } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SWLed12 %d\n", pLed->CurrLedState)); } /* Maddest add for NETGEAR R6100 */ @@ -3867,7 +3767,6 @@ SwLedControlMode13( struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; PLED_USB pLed = &(ledpriv->SwLed0); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 13 CurrLedState %d, LedAction %d\n", pLed->CurrLedState, LedAction)); switch (LedAction) { case LED_CTL_LINK: if (pLed->bLedWPSBlinkInProgress) @@ -4013,10 +3912,8 @@ SwLedControlMode14( struct led_priv *ledpriv = &(Adapter->ledpriv); PLED_USB pLed = &(ledpriv->SwLed0); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 14 CurrLedState %d, LedAction %d\n", pLed->CurrLedState, LedAction)); switch (LedAction) { case LED_CTL_POWER_OFF: - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 14 LED_CTL_POWER_OFF\n")); pLed->CurrLedState = RTW_LED_OFF; pLed->BlinkingLedState = RTW_LED_OFF; if (pLed->bLedBlinkInProgress) { @@ -4027,7 +3924,6 @@ SwLedControlMode14( break; case LED_CTL_POWER_ON: - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 14 LED_CTL_POWER_ON\n")); SwLedOn(Adapter, pLed); break; @@ -4076,11 +3972,9 @@ SwLedControlMode15( struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; PLED_USB pLed = &(ledpriv->SwLed0); - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 15 CurrLedState %d, LedAction %d\n", pLed->CurrLedState, LedAction)); switch (LedAction) { case LED_CTL_START_WPS: /* wait until xinpin finish */ case LED_CTL_START_WPS_BOTTON: - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 15 LED_CTL_START_WPS\n")); if (pLed->bLedWPSBlinkInProgress == _FALSE) { if (pLed->bLedBlinkInProgress == _TRUE) { _cancel_timer_ex(&(pLed->BlinkTimer)); @@ -4103,7 +3997,6 @@ SwLedControlMode15( break; case LED_CTL_STOP_WPS: - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 15 LED_CTL_STOP_WPS\n")); if (pLed->bLedWPSBlinkInProgress) _cancel_timer_ex(&(pLed->BlinkTimer)); @@ -4119,7 +4012,6 @@ SwLedControlMode15( case LED_CTL_STOP_WPS_FAIL: case LED_CTL_STOP_WPS_FAIL_OVERLAP: /* WPS session overlap */ - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 15 LED_CTL_STOP_WPS_FAIL\n")); if (pLed->bLedWPSBlinkInProgress) { _cancel_timer_ex(&(pLed->BlinkTimer)); pLed->bLedWPSBlinkInProgress = _FALSE; @@ -4131,7 +4023,6 @@ SwLedControlMode15( break; case LED_CTL_NO_LINK: - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 15 LED_CTL_NO_LINK\n")); if (pLed->bLedWPSBlinkInProgress) return; @@ -4164,7 +4055,6 @@ SwLedControlMode15( break; case LED_CTL_LINK: - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 15 LED_CTL_LINK\n")); if (pLed->bLedWPSBlinkInProgress) return; @@ -4332,7 +4222,6 @@ LedControlUSB( break; } - RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("LedStrategy:%d, LedAction %d\n", ledpriv->LedStrategy, LedAction)); } /* @@ -4373,7 +4262,7 @@ InitLed( pLed->LedPin = LedPin; ResetLedStatus(pLed); - _init_timer(&(pLed->BlinkTimer), padapter->pnetdev, BlinkTimerCallback, pLed); + rtw_init_timer(&(pLed->BlinkTimer), padapter, BlinkTimerCallback, pLed); _init_workitem(&(pLed->BlinkWorkItem), BlinkWorkItemCallback, pLed); } diff --git a/hal/phydm/halhwimg.h b/hal/phydm/halhwimg.h index 4c5c881..e8f5802 100644 --- a/hal/phydm/halhwimg.h +++ b/hal/phydm/halhwimg.h @@ -1,123 +1,137 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #pragma once #ifndef __INC_HW_IMG_H #define __INC_HW_IMG_H -// -// 2011/03/15 MH Add for different IC HW image file selection. code size consideration. -// +/* + * 2011/03/15 MH Add for different IC HW image file selection. code size consideration. + * */ #if RT_PLATFORM == PLATFORM_LINUX #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - // For 92C - #define RTL8192CE_HWIMG_SUPPORT 1 - #define RTL8192CE_TEST_HWIMG_SUPPORT 0 - #define RTL8192CU_HWIMG_SUPPORT 0 - #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + /* For 92C */ + #define RTL8192CE_HWIMG_SUPPORT 1 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 0 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + /* For 92D */ + #define RTL8192DE_HWIMG_SUPPORT 1 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 0 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + /* For 8723 */ + #define RTL8723E_HWIMG_SUPPORT 1 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 0 + + /* For 88E */ + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 - // For 92D - #define RTL8192DE_HWIMG_SUPPORT 1 - #define RTL8192DE_TEST_HWIMG_SUPPORT 0 - #define RTL8192DU_HWIMG_SUPPORT 0 - #define RTL8192DU_TEST_HWIMG_SUPPORT 0 - - // For 8723 - #define RTL8723E_HWIMG_SUPPORT 1 - #define RTL8723U_HWIMG_SUPPORT 0 - #define RTL8723S_HWIMG_SUPPORT 0 - - //For 88E - #define RTL8188EE_HWIMG_SUPPORT 0 - #define RTL8188EU_HWIMG_SUPPORT 0 - #define RTL8188ES_HWIMG_SUPPORT 0 - #elif (DEV_BUS_TYPE == RT_USB_INTERFACE) - // For 92C - #define RTL8192CE_HWIMG_SUPPORT 0 - #define RTL8192CE_TEST_HWIMG_SUPPORT 0 - #define RTL8192CU_HWIMG_SUPPORT 1 - #define RTL8192CU_TEST_HWIMG_SUPPORT 0 - - //For 92D - #define RTL8192DE_HWIMG_SUPPORT 0 - #define RTL8192DE_TEST_HWIMG_SUPPORT 0 - #define RTL8192DU_HWIMG_SUPPORT 1 - #define RTL8192DU_TEST_HWIMG_SUPPORT 0 - - // For 8723 - #define RTL8723E_HWIMG_SUPPORT 0 - #define RTL8723U_HWIMG_SUPPORT 1 - #define RTL8723S_HWIMG_SUPPORT 0 - - //For 88E - #define RTL8188EE_HWIMG_SUPPORT 0 - #define RTL8188EU_HWIMG_SUPPORT 0 - #define RTL8188ES_HWIMG_SUPPORT 0 - + /* For 92C */ + #define RTL8192CE_HWIMG_SUPPORT 0 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 1 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + /* For 92D */ + #define RTL8192DE_HWIMG_SUPPORT 0 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 1 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + /* For 8723 */ + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 1 + #define RTL8723S_HWIMG_SUPPORT 0 + + /* For 88E */ + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + #elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE) - // For 92C - #define RTL8192CE_HWIMG_SUPPORT 0 - #define RTL8192CE_TEST_HWIMG_SUPPORT 0 - #define RTL8192CU_HWIMG_SUPPORT 1 - #define RTL8192CU_TEST_HWIMG_SUPPORT 0 - - //For 92D - #define RTL8192DE_HWIMG_SUPPORT 0 - #define RTL8192DE_TEST_HWIMG_SUPPORT 0 - #define RTL8192DU_HWIMG_SUPPORT 1 - #define RTL8192DU_TEST_HWIMG_SUPPORT 0 - - // For 8723 - #define RTL8723E_HWIMG_SUPPORT 0 - #define RTL8723U_HWIMG_SUPPORT 0 - #define RTL8723S_HWIMG_SUPPORT 1 - - //For 88E - #define RTL8188EE_HWIMG_SUPPORT 0 - #define RTL8188EU_HWIMG_SUPPORT 0 - #define RTL8188ES_HWIMG_SUPPORT 0 + /* For 92C */ + #define RTL8192CE_HWIMG_SUPPORT 0 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 1 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + /* For 92D */ + #define RTL8192DE_HWIMG_SUPPORT 0 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 1 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + /* For 8723 */ + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 1 + + /* For 88E */ + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 #endif -#else // PLATFORM_WINDOWS & MacOSX +#else /* PLATFORM_WINDOWS & MacOSX */ -//For 92C -#define RTL8192CE_HWIMG_SUPPORT 1 -#define RTL8192CE_TEST_HWIMG_SUPPORT 1 -#define RTL8192CU_HWIMG_SUPPORT 1 -#define RTL8192CU_TEST_HWIMG_SUPPORT 1 + /* For 92C */ + #define RTL8192CE_HWIMG_SUPPORT 1 + #define RTL8192CE_TEST_HWIMG_SUPPORT 1 + #define RTL8192CU_HWIMG_SUPPORT 1 + #define RTL8192CU_TEST_HWIMG_SUPPORT 1 -// For 92D -#define RTL8192DE_HWIMG_SUPPORT 1 -#define RTL8192DE_TEST_HWIMG_SUPPORT 1 -#define RTL8192DU_HWIMG_SUPPORT 1 -#define RTL8192DU_TEST_HWIMG_SUPPORT 1 + /* For 92D */ + #define RTL8192DE_HWIMG_SUPPORT 1 + #define RTL8192DE_TEST_HWIMG_SUPPORT 1 + #define RTL8192DU_HWIMG_SUPPORT 1 + #define RTL8192DU_TEST_HWIMG_SUPPORT 1 #if defined(UNDER_CE) - // For 8723 - #define RTL8723E_HWIMG_SUPPORT 0 - #define RTL8723U_HWIMG_SUPPORT 0 - #define RTL8723S_HWIMG_SUPPORT 1 - - // For 88E - #define RTL8188EE_HWIMG_SUPPORT 0 - #define RTL8188EU_HWIMG_SUPPORT 0 - #define RTL8188ES_HWIMG_SUPPORT 0 - - #else - - // For 8723 - #define RTL8723E_HWIMG_SUPPORT 1 - //#define RTL_8723E_TEST_HWIMG_SUPPORT 1 - #define RTL8723U_HWIMG_SUPPORT 1 - //#define RTL_8723U_TEST_HWIMG_SUPPORT 1 - #define RTL8723S_HWIMG_SUPPORT 1 - //#define RTL_8723S_TEST_HWIMG_SUPPORT 1 - - //For 88E - #define RTL8188EE_HWIMG_SUPPORT 1 - #define RTL8188EU_HWIMG_SUPPORT 1 - #define RTL8188ES_HWIMG_SUPPORT 1 + /* For 8723 */ + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 1 + + /* For 88E */ + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #else + + /* For 8723 */ + #define RTL8723E_HWIMG_SUPPORT 1 + /* #define RTL_8723E_TEST_HWIMG_SUPPORT 1 */ + #define RTL8723U_HWIMG_SUPPORT 1 + /* #define RTL_8723U_TEST_HWIMG_SUPPORT 1 */ + #define RTL8723S_HWIMG_SUPPORT 1 + /* #define RTL_8723S_TEST_HWIMG_SUPPORT 1 */ + + /* For 88E */ + #define RTL8188EE_HWIMG_SUPPORT 1 + #define RTL8188EU_HWIMG_SUPPORT 1 + #define RTL8188ES_HWIMG_SUPPORT 1 #endif #endif -#endif //__INC_HW_IMG_H +#endif /* __INC_HW_IMG_H */ diff --git a/hal/phydm/mp_precomp.h b/hal/phydm/mp_precomp.h index 2e950cb..99ca5f4 100644 --- a/hal/phydm/mp_precomp.h +++ b/hal/phydm/mp_precomp.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,10 +11,4 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - + *****************************************************************************/ diff --git a/hal/phydm/phydm.c b/hal/phydm/phydm.c index 5f98239..e8b6983 100644 --- a/hal/phydm/phydm.c +++ b/hal/phydm/phydm.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,21 +11,16 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" -const u2Byte dB_Invert_Table[12][8] = { +const u16 db_invert_table[12][8] = { { 1, 1, 1, 2, 2, 2, 2, 3}, { 3, 3, 4, 4, 4, 5, 6, 6}, { 7, 8, 9, 10, 11, 13, 14, 16}, @@ -40,85 +35,88 @@ const u2Byte dB_Invert_Table[12][8] = { { 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} }; +const u16 phy_rate_table[] = { /*20M*/ + 1, 2, 5, 11, + 6, 9, 12, 18, 24, 36, 48, 54, + 6, 13, 19, 26, 39, 52, 58, 65, /*MCS0~7*/ + 13, 26, 39, 52, 78, 104, 117, 130 /*MCS8~15*/ +}; -//============================================================ -// Local Function predefine. -//============================================================ +/* ************************************************************ + * Local Function predefine. + * ************************************************************ */ /* START------------COMMON INFO RELATED--------------- */ -VOID -odm_GlobalAdapterCheck( - IN VOID - ); +void +odm_global_adapter_check( + void +); -//move to odm_PowerTacking.h by YuChen +/* move to odm_PowerTacking.h by YuChen */ -VOID -odm_UpdatePowerTrainingState( - IN PDM_ODM_T pDM_Odm +void +odm_update_power_training_state( + struct PHY_DM_STRUCT *p_dm_odm ); -//============================================================ -//3 Export Interface -//============================================================ +/* ************************************************************ + * 3 Export Interface + * ************************************************************ */ /*Y = 10*log(X)*/ -s4Byte -ODM_PWdB_Conversion( - IN s4Byte X, - IN u4Byte TotalBit, - IN u4Byte DecimalBit - ) +s32 +odm_pwdb_conversion( + s32 X, + u32 total_bit, + u32 decimal_bit +) { - s4Byte Y, integer = 0, decimal = 0; - u4Byte i; + s32 Y, integer = 0, decimal = 0; + u32 i; - if(X == 0) - X = 1; // log2(x), x can't be 0 + if (X == 0) + X = 1; /* log2(x), x can't be 0 */ - for(i = (TotalBit-1); i > 0; i--) - { - if(X & BIT(i)) - { + for (i = (total_bit - 1); i > 0; i--) { + if (X & BIT(i)) { integer = i; - if(i > 0) - decimal = (X & BIT(i-1))?2:0; //decimal is 0.5dB*3=1.5dB~=2dB + if (i > 0) + decimal = (X & BIT(i - 1)) ? 2 : 0; /* decimal is 0.5dB*3=1.5dB~=2dB */ break; } } - - Y = 3*(integer-DecimalBit)+decimal; //10*log(x)=3*log2(x), + + Y = 3 * (integer - decimal_bit) + decimal; /* 10*log(x)=3*log2(x), */ return Y; } -s4Byte -ODM_SignConversion( - IN s4Byte value, - IN u4Byte TotalBit - ) +s32 +odm_sign_conversion( + s32 value, + u32 total_bit +) { - if(value&BIT(TotalBit-1)) - value -= BIT(TotalBit); + if (value & BIT(total_bit - 1)) + value -= BIT(total_bit); return value; } void -phydm_seq_sorting( - IN PVOID pDM_VOID, - IN OUT u4Byte *p_value, - IN OUT u4Byte *rank_idx, - IN OUT u4Byte *p_idx_out, - IN u1Byte seq_length +phydm_seq_sorting( + void *p_dm_void, + u32 *p_value, + u32 *rank_idx, + u32 *p_idx_out, + u8 seq_length ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0 , j = 0; - u4Byte tmp_a, tmp_b; - u4Byte tmp_idx_a, tmp_idx_b; + u8 i = 0, j = 0; + u32 tmp_a, tmp_b; + u32 tmp_idx_a, tmp_idx_b; for (i = 0; i < seq_length; i++) { rank_idx[i] = i; @@ -126,191 +124,193 @@ phydm_seq_sorting( } for (i = 0; i < (seq_length - 1); i++) { - + for (j = 0; j < (seq_length - 1 - i); j++) { - + tmp_a = p_value[j]; - tmp_b = p_value[j+1]; + tmp_b = p_value[j + 1]; tmp_idx_a = rank_idx[j]; - tmp_idx_b = rank_idx[j+1]; + tmp_idx_b = rank_idx[j + 1]; if (tmp_a < tmp_b) { p_value[j] = tmp_b; - p_value[j+1] = tmp_a; - + p_value[j + 1] = tmp_a; + rank_idx[j] = tmp_idx_b; - rank_idx[j+1] = tmp_idx_a; + rank_idx[j + 1] = tmp_idx_a; } - } + } } for (i = 0; i < seq_length; i++) { - p_idx_out[rank_idx[i]] = i+1; + p_idx_out[rank_idx[i]] = i + 1; /**/ } - - + + } -VOID -ODM_InitMpDriverStatus( - IN PDM_ODM_T pDM_Odm +#if 0/*(DM_ODM_SUPPORT_TYPE & ODM_WIN)*/ +void +odm_init_mp_driver_status( + struct PHY_DM_STRUCT *p_dm_odm ) { -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - - // Decide when compile time - #if(MP_DRIVER == 1) - pDM_Odm->mp_mode = TRUE; + /* Decide when compile time */ + #if (MP_DRIVER == 1) + p_dm_odm->mp_mode = true; #else - pDM_Odm->mp_mode = FALSE; + p_dm_odm->mp_mode = false; #endif -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - - PADAPTER Adapter = pDM_Odm->Adapter; + odm_cmn_info_hook(p_dm_odm, ODM_CMNINFO_MP_MODE, &(p_dm_odm->mp_mode)); +} +#endif - // Update information every period - pDM_Odm->mp_mode = (BOOLEAN)Adapter->registrypriv.mp_mode; +void +phydm_init_trx_antenna_setting( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + /*#if (RTL8814A_SUPPORT == 1)*/ -#else + if (p_dm_odm->support_ic_type & (ODM_RTL8814A)) { + u8 rx_ant = 0, tx_ant = 0; - prtl8192cd_priv priv = pDM_Odm->priv; + rx_ant = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_RX_PATH, p_dm_odm), ODM_BIT(BB_RX_PATH, p_dm_odm)); + tx_ant = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_TX_PATH, p_dm_odm), ODM_BIT(BB_TX_PATH, p_dm_odm)); + p_dm_odm->tx_ant_status = (tx_ant & 0xf); + p_dm_odm->rx_ant_status = (rx_ant & 0xf); + } else if (p_dm_odm->support_ic_type & (ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B)) {/* JJ ADD 20161014 */ + p_dm_odm->tx_ant_status = 0x1; + p_dm_odm->rx_ant_status = 0x1; - pDM_Odm->mp_mode = (BOOLEAN)priv->pshare->rf_ft_var.mp_specific; - -#endif + } + /*#endif*/ } -VOID -ODM_UpdateMpDriverStatus( - IN PDM_ODM_T pDM_Odm +void +phydm_traffic_load_decision( + void *p_dm_void ) { -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - // Do nothing. + /*---TP & Trafic-load calculation---*/ -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; + if (p_dm_odm->last_tx_ok_cnt > (*(p_dm_odm->p_num_tx_bytes_unicast))) + p_dm_odm->last_tx_ok_cnt = (*(p_dm_odm->p_num_tx_bytes_unicast)); - // Update information erery period - pDM_Odm->mp_mode = (BOOLEAN)Adapter->registrypriv.mp_mode; + if (p_dm_odm->last_rx_ok_cnt > (*(p_dm_odm->p_num_rx_bytes_unicast))) + p_dm_odm->last_rx_ok_cnt = (*(p_dm_odm->p_num_rx_bytes_unicast)); -#else - - // Do nothing. + p_dm_odm->cur_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast) - p_dm_odm->last_tx_ok_cnt; + p_dm_odm->cur_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast) - p_dm_odm->last_rx_ok_cnt; + p_dm_odm->last_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast); + p_dm_odm->last_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast); +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + p_dm_odm->tx_tp = ((p_dm_odm->tx_tp) >> 1) + (u32)(((p_dm_odm->cur_tx_ok_cnt) >> 17) >> 1); /* <<3(8bit), >>20(10^6,M)*/ + p_dm_odm->rx_tp = ((p_dm_odm->rx_tp) >> 1) + (u32)(((p_dm_odm->cur_rx_ok_cnt) >> 17) >> 1); /* <<3(8bit), >>20(10^6,M)*/ +#else + p_dm_odm->tx_tp = ((p_dm_odm->tx_tp) >> 1) + (u32)(((p_dm_odm->cur_tx_ok_cnt) >> 18) >> 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ + p_dm_odm->rx_tp = ((p_dm_odm->rx_tp) >> 1) + (u32)(((p_dm_odm->cur_rx_ok_cnt) >> 18) >> 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ #endif -} + p_dm_odm->total_tp = p_dm_odm->tx_tp + p_dm_odm->rx_tp; -VOID -PHYDM_InitTRXAntennaSetting( - IN PDM_ODM_T pDM_Odm -) -{ -/*#if (RTL8814A_SUPPORT == 1)*/ + if (p_dm_odm->total_tp == 0) + p_dm_odm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD; + else + p_dm_odm->consecutive_idlel_time = 0; + /* + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n", + p_dm_odm->cur_tx_ok_cnt, p_dm_odm->cur_rx_ok_cnt, p_dm_odm->last_tx_ok_cnt, p_dm_odm->last_rx_ok_cnt)); - if (pDM_Odm->SupportICType & (ODM_RTL8814A)) { - u1Byte RxAnt = 0, TxAnt = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("tx_tp = %d, rx_tp = %d\n", + p_dm_odm->tx_tp, p_dm_odm->rx_tp)); + */ - RxAnt = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_RX_PATH, pDM_Odm), ODM_BIT(BB_RX_PATH, pDM_Odm)); - TxAnt = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_TX_PATH, pDM_Odm), ODM_BIT(BB_TX_PATH, pDM_Odm)); - pDM_Odm->TXAntStatus = (TxAnt & 0xf); - pDM_Odm->RXAntStatus = (RxAnt & 0xf); - } else if (pDM_Odm->SupportICType & (ODM_RTL8723D | ODM_RTL8821C)) { - pDM_Odm->TXAntStatus = 0x1; - pDM_Odm->RXAntStatus = 0x1; - - } -/*#endif*/ -} + p_dm_odm->pre_traffic_load = p_dm_odm->traffic_load; -void -phydm_traffic_load_decision( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - - /*---trafic load decision---*/ - pDM_Odm->curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_Odm->lastTxOkCnt; - pDM_Odm->curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_Odm->lastRxOkCnt; - pDM_Odm->lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); - pDM_Odm->lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); - - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - pDM_Odm->tx_tp = ((pDM_Odm->tx_tp)>>1) + (u4Byte)(((pDM_Odm->curTxOkCnt)>>17)>>1); /* <<3(8bit), >>20(10^6,M)*/ - pDM_Odm->rx_tp = ((pDM_Odm->rx_tp)>>1) + (u4Byte)(((pDM_Odm->curRxOkCnt)>>17)>>1); /* <<3(8bit), >>20(10^6,M)*/ - #else - pDM_Odm->tx_tp = ((pDM_Odm->tx_tp)>>1) + (u4Byte)(((pDM_Odm->curTxOkCnt)>>18)>>1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ - pDM_Odm->rx_tp = ((pDM_Odm->rx_tp)>>1) + (u4Byte)(((pDM_Odm->curRxOkCnt)>>18)>>1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ - #endif - pDM_Odm->total_tp = pDM_Odm->tx_tp + pDM_Odm->rx_tp; - + if (p_dm_odm->cur_tx_ok_cnt > 1875000 || p_dm_odm->cur_rx_ok_cnt > 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/ - pDM_Odm->pre_TrafficLoad = pDM_Odm->TrafficLoad; - - if (pDM_Odm->curTxOkCnt > 1875000 || pDM_Odm->curRxOkCnt > 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/ - - pDM_Odm->TrafficLoad = TRAFFIC_HIGH; + p_dm_odm->traffic_load = TRAFFIC_HIGH; /**/ - } else if (pDM_Odm->curTxOkCnt > 500000 || pDM_Odm->curRxOkCnt > 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/ - - pDM_Odm->TrafficLoad = TRAFFIC_MID; + } else if (p_dm_odm->cur_tx_ok_cnt > 500000 || p_dm_odm->cur_rx_ok_cnt > 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/ + + p_dm_odm->traffic_load = TRAFFIC_MID; /**/ - } else if (pDM_Odm->curTxOkCnt > 100000 || pDM_Odm->curRxOkCnt > 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/ - - pDM_Odm->TrafficLoad = TRAFFIC_LOW; + } else if (p_dm_odm->cur_tx_ok_cnt > 100000 || p_dm_odm->cur_rx_ok_cnt > 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/ + + p_dm_odm->traffic_load = TRAFFIC_LOW; /**/ } else { - - pDM_Odm->TrafficLoad = TRAFFIC_ULTRA_LOW; + + p_dm_odm->traffic_load = TRAFFIC_ULTRA_LOW; /**/ } } -VOID +void phydm_config_ofdm_tx_path( - IN PDM_ODM_T pDM_Odm, - IN u4Byte path + struct PHY_DM_STRUCT *p_dm_odm, + u32 path ) { - u1Byte ofdm_rx_path; +#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) + u8 ofdm_tx_path = 0x33; +#endif + +#if (RTL8192E_SUPPORT == 1) + if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { - #if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType & (ODM_RTL8192E)) { - if (path == PHYDM_A) { - ODM_SetBBReg(pDM_Odm, 0x90c , bMaskDWord, 0x81321311); + odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x81121111); /**/ } else if (path == PHYDM_B) { - ODM_SetBBReg(pDM_Odm, 0x90c , bMaskDWord, 0x82321322); + odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x82221222); /**/ } else if (path == PHYDM_AB) { - ODM_SetBBReg(pDM_Odm, 0x90c , bMaskDWord, 0x83321333); + odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x83321333); /**/ } - - + + } - #endif +#endif + +#if (RTL8812A_SUPPORT == 1) + if (p_dm_odm->support_ic_type & (ODM_RTL8812)) { + + if (path == PHYDM_A) { + ofdm_tx_path = 0x11; + /**/ + } else if (path == PHYDM_B) { + ofdm_tx_path = 0x22; + /**/ + } else if (path == PHYDM_AB) { + ofdm_tx_path = 0x33; + /**/ + } + + odm_set_bb_reg(p_dm_odm, 0x80c, 0xff00, ofdm_tx_path); + } +#endif } -VOID +void phydm_config_ofdm_rx_path( - IN PDM_ODM_T pDM_Odm, - IN u4Byte path + struct PHY_DM_STRUCT *p_dm_odm, + u32 path ) { - u1Byte ofdm_rx_path = 0; + u8 ofdm_rx_path = 0; - #if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType & (ODM_RTL8192E)) { - + + if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { +#if (RTL8192E_SUPPORT == 1) if (path == PHYDM_A) { ofdm_rx_path = 1; /**/ @@ -321,46 +321,65 @@ phydm_config_ofdm_rx_path( ofdm_rx_path = 3; /**/ } - - ODM_SetBBReg(pDM_Odm, 0xC04 , 0xff, (((ofdm_rx_path)<<4)|ofdm_rx_path)); - ODM_SetBBReg(pDM_Odm, 0xD04 , 0xf, ofdm_rx_path); + + odm_set_bb_reg(p_dm_odm, 0xC04, 0xff, (((ofdm_rx_path) << 4) | ofdm_rx_path)); + odm_set_bb_reg(p_dm_odm, 0xD04, 0xf, ofdm_rx_path); +#endif } - #endif +#if (RTL8812A_SUPPORT || RTL8822B_SUPPORT) + else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) { + + if (path == PHYDM_A) { + ofdm_rx_path = 1; + /**/ + } else if (path == PHYDM_B) { + ofdm_rx_path = 2; + /**/ + } else if (path == PHYDM_AB) { + ofdm_rx_path = 3; + /**/ + } + + odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, ((ofdm_rx_path << 4) | ofdm_rx_path)); + } +#endif } -VOID +void phydm_config_cck_rx_antenna_init( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ) { - #if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType & (ODM_RTL8192E)) { - +#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) + if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) { + /*CCK 2R CCA parameters*/ - ODM_SetBBReg(pDM_Odm, 0xa2c , BIT18, 1); /*enable 2R Rx path*/ - ODM_SetBBReg(pDM_Odm, 0xa2c , BIT22, 1); /*enable 2R MRC*/ - ODM_SetBBReg(pDM_Odm, 0xa84 , BIT28, 1); /*1. pdx1[5:0] > 2*PD_lim 2. RXIQ_3 = 0 ( signed )*/ - ODM_SetBBReg(pDM_Odm, 0xa70 , BIT7, 0); /*Concurrent CCA at LSB & USB*/ - ODM_SetBBReg(pDM_Odm, 0xa74 , BIT8, 0); /*RX path diversity enable*/ - ODM_SetBBReg(pDM_Odm, 0xa08 , BIT28, 1); /* r_cck_2nd_sel_eco*/ - ODM_SetBBReg(pDM_Odm, 0xa14 , BIT7, 0); /* r_en_mrc_antsel*/ + odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(18), 1); /*enable 2R Rx path*/ + odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(22), 1); /*enable 2R MRC*/ + odm_set_bb_reg(p_dm_odm, 0xa84, BIT(28), 1); /*1. pdx1[5:0] > 2*PD_lim 2. RXIQ_3 = 0 ( signed )*/ + odm_set_bb_reg(p_dm_odm, 0xa70, BIT(7), 0); /*Concurrent CCA at LSB & USB*/ + odm_set_bb_reg(p_dm_odm, 0xa74, BIT(8), 0); /*RX path diversity enable*/ + odm_set_bb_reg(p_dm_odm, 0xa08, BIT(28), 1); /* r_cck_2nd_sel_eco*/ + odm_set_bb_reg(p_dm_odm, 0xa14, BIT(7), 0); /* r_en_mrc_antsel*/ } - #endif +#endif } -VOID +void phydm_config_cck_rx_path( - IN PDM_ODM_T pDM_Odm, - IN u1Byte path, - IN u1Byte path_div_en + struct PHY_DM_STRUCT *p_dm_odm, + u8 path, + u8 path_div_en ) { - u1Byte path_div_select = 0; - u1Byte cck_1_path = 0, cck_2_path = 0; +#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) + u8 path_div_select = 0; + u8 cck_1_path = 0, cck_2_path = 0; +#endif + +#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) + if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) { - #if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType & (ODM_RTL8192E)) { - if (path == PHYDM_A) { path_div_select = 0; cck_1_path = 0; @@ -368,1977 +387,2870 @@ phydm_config_cck_rx_path( } else if (path == PHYDM_B) { path_div_select = 0; cck_1_path = 1; - cck_2_path = 1; + cck_2_path = 1; } else if (path == PHYDM_AB) { - + if (path_div_en == CCA_PATHDIV_ENABLE) path_div_select = 1; - + cck_1_path = 0; - cck_2_path = 1; - + cck_2_path = 1; + } - - ODM_SetBBReg(pDM_Odm, 0xa04 , (BIT27|BIT26), cck_1_path); - ODM_SetBBReg(pDM_Odm, 0xa04 , (BIT25|BIT24), cck_2_path); - ODM_SetBBReg(pDM_Odm, 0xa74 , BIT8, path_div_select); - + + odm_set_bb_reg(p_dm_odm, 0xa04, (BIT(27) | BIT(26)), cck_1_path); + odm_set_bb_reg(p_dm_odm, 0xa04, (BIT(25) | BIT(24)), cck_2_path); + odm_set_bb_reg(p_dm_odm, 0xa74, BIT(8), path_div_select); + } - #endif +#endif } -VOID +void phydm_config_trx_path( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte pre_support_ability; - u4Byte used = *_used; - u4Byte out_len = *_out_len; + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 used = *_used; + u32 out_len = *_out_len; /* CCK */ if (dm_value[0] == 0) { - + if (dm_value[1] == 1) { /*TX*/ if (dm_value[2] == 1) - ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x8); + odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x8); else if (dm_value[2] == 2) - ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x4); + odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x4); else if (dm_value[2] == 3) - ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0xc); + odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0xc); } else if (dm_value[1] == 2) { /*RX*/ - - phydm_config_cck_rx_antenna_init(pDM_Odm); - - if (dm_value[2] == 1) { - phydm_config_cck_rx_path(pDM_Odm, PHYDM_A, CCA_PATHDIV_DISABLE); - } else if (dm_value[2] == 2) { - phydm_config_cck_rx_path(pDM_Odm, PHYDM_B, CCA_PATHDIV_DISABLE); - } else if (dm_value[2] == 3) { + + phydm_config_cck_rx_antenna_init(p_dm_odm); + + if (dm_value[2] == 1) + phydm_config_cck_rx_path(p_dm_odm, PHYDM_A, CCA_PATHDIV_DISABLE); + else if (dm_value[2] == 2) + phydm_config_cck_rx_path(p_dm_odm, PHYDM_B, CCA_PATHDIV_DISABLE); + else if (dm_value[2] == 3) { if (dm_value[3] == 1) /*enable path diversity*/ - phydm_config_cck_rx_path(pDM_Odm, PHYDM_AB, CCA_PATHDIV_ENABLE); + phydm_config_cck_rx_path(p_dm_odm, PHYDM_AB, CCA_PATHDIV_ENABLE); else - phydm_config_cck_rx_path(pDM_Odm, PHYDM_B, CCA_PATHDIV_DISABLE); + phydm_config_cck_rx_path(p_dm_odm, PHYDM_B, CCA_PATHDIV_DISABLE); } } - } + } /* OFDM */ else if (dm_value[0] == 1) { if (dm_value[1] == 1) { /*TX*/ - phydm_config_ofdm_tx_path(pDM_Odm, dm_value[2]); + phydm_config_ofdm_tx_path(p_dm_odm, dm_value[2]); /**/ } else if (dm_value[1] == 2) { /*RX*/ - phydm_config_ofdm_rx_path(pDM_Odm, dm_value[2]); + phydm_config_ofdm_rx_path(p_dm_odm, dm_value[2]); /**/ } } - PHYDM_SNPRINTF((output+used, out_len-used, "PHYDM Set Path [%s] [%s] = [%s%s%s%s]\n", - (dm_value[0] == 1) ? "CCK" : "OFDM", - (dm_value[1] == 1) ? "TX" : "RX", - (dm_value[2] & 0x1)?"A":"", - (dm_value[2] & 0x2)?"B":"", - (dm_value[2] & 0x4)?"C":"", - (dm_value[2] & 0x8)?"D":"" - )); - + PHYDM_SNPRINTF((output + used, out_len - used, "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n", + (dm_value[0] == 1) ? "OFDM" : "CCK", + (dm_value[1] == 1) ? "TX" : "RX", + (dm_value[2] & 0x1) ? "A" : "", + (dm_value[2] & 0x2) ? "B" : "", + (dm_value[2] & 0x4) ? "C" : "", + (dm_value[2] & 0x8) ? "D" : "" + )); + } -VOID -phydm_Init_cck_setting( - IN PDM_ODM_T pDM_Odm +void +phydm_init_cck_setting( + struct PHY_DM_STRUCT *p_dm_odm ) { - u4Byte value_824,value_82c; +#if (RTL8192E_SUPPORT == 1) + u32 value_824, value_82c; +#endif - pDM_Odm->bCckHighPower = (BOOLEAN) ODM_GetBBReg(pDM_Odm, ODM_REG(CCK_RPT_FORMAT,pDM_Odm), ODM_BIT(CCK_RPT_FORMAT,pDM_Odm)); + p_dm_odm->is_cck_high_power = (boolean) odm_get_bb_reg(p_dm_odm, ODM_REG(CCK_RPT_FORMAT, p_dm_odm), ODM_BIT(CCK_RPT_FORMAT, p_dm_odm)); + +#if (RTL8192E_SUPPORT == 1) + if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + phydm_config_cck_rx_antenna_init(p_dm_odm); + phydm_config_cck_rx_path(p_dm_odm, PHYDM_A, CCA_PATHDIV_DISABLE); +#endif - #if (RTL8192E_SUPPORT == 1) - if(pDM_Odm->SupportICType & (ODM_RTL8192E)) - { - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - phydm_config_cck_rx_antenna_init(pDM_Odm); - phydm_config_cck_rx_path(pDM_Odm, PHYDM_A, CCA_PATHDIV_DISABLE); - #endif - /* 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting should be equal or CCK RSSI report may be incorrect */ - value_824 = ODM_GetBBReg(pDM_Odm, 0x824, BIT9); - value_82c = ODM_GetBBReg(pDM_Odm, 0x82c, BIT9); - - if(value_824 != value_82c) - { - ODM_SetBBReg(pDM_Odm, 0x82c , BIT9, value_824); - } - ODM_SetBBReg(pDM_Odm, 0xa80 , BIT7, value_824); - pDM_Odm->cck_agc_report_type = (BOOLEAN)value_824; + value_824 = odm_get_bb_reg(p_dm_odm, 0x824, BIT(9)); + value_82c = odm_get_bb_reg(p_dm_odm, 0x82c, BIT(9)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("cck_agc_report_type = (( %d )), ExtLNAGain = (( %d ))\n", pDM_Odm->cck_agc_report_type, pDM_Odm->ExtLNAGain)); + if (value_824 != value_82c) + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(9), value_824); + odm_set_bb_reg(p_dm_odm, 0xa80, BIT(7), value_824); + p_dm_odm->cck_agc_report_type = (boolean)value_824; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("cck_agc_report_type = (( %d )), ext_lna_gain = (( %d ))\n", p_dm_odm->cck_agc_report_type, p_dm_odm->ext_lna_gain)); } - #endif - -#if ((RTL8703B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1)) - if (pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723D)) { +#endif +/* JJ ADD 20161014 */ +#if ((RTL8703B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8710B_SUPPORT == 1)) + if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { - pDM_Odm->cck_agc_report_type = ODM_GetBBReg(pDM_Odm, 0x950, BIT11) ? 1 : 0; /*1: 4bit LNA , 0: 3bit LNA */ - - if (pDM_Odm->cck_agc_report_type != 1) { - DbgPrint("[Warning] 8703B/8723D CCK should be 4bit LNA, ie. 0x950[11] = 1\n"); + p_dm_odm->cck_agc_report_type = odm_get_bb_reg(p_dm_odm, 0x950, BIT(11)) ? 1 : 0; /*1: 4bit LNA, 0: 3bit LNA */ + + if (p_dm_odm->cck_agc_report_type != 1) { + dbg_print("[Warning] 8703B/8723D/8710B CCK should be 4bit LNA, ie. 0x950[11] = 1\n"); /**/ } } #endif - -#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - - if (pDM_Odm->SupportICType & (ODM_RTL8723D|ODM_RTL8822B|ODM_RTL8197F)) { - pDM_Odm->cck_new_agc = ODM_GetBBReg(pDM_Odm, 0xa9c, BIT17)?TRUE:FALSE; /*1: new agc 0: old agc*/ - } else +/* JJ ADD 20161014 */ +#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8710B_SUPPORT == 1)) + if (p_dm_odm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8710B)) + p_dm_odm->cck_new_agc = odm_get_bb_reg(p_dm_odm, 0xa9c, BIT(17)) ? true : false; /*1: new agc 0: old agc*/ + else #endif - pDM_Odm->cck_new_agc = FALSE; - + p_dm_odm->cck_new_agc = false; + } -VOID -PHYDM_InitSoftMLSetting( - IN PDM_ODM_T pDM_Odm + +void +phydm_dynamicsoftmletting( + struct PHY_DM_STRUCT *p_dm_odm ) { + + u32 ret_val; + #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->mp_mode == FALSE) { - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ODM_SetBBReg(pDM_Odm, 0x19a8, bMaskDWord, 0xc10a0000); + if (*(p_dm_odm->p_mp_mode) == false) { + if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + + if ((!p_dm_odm->is_linked)|(p_dm_odm->bLinkedcmw500)) + return; + + if (true == p_dm_odm->bsomlenabled) { + ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_TRACE,("PHYDM_DynamicSoftMLSetting(): SoML has been enable, skip dynamic SoML switch\n")); + return; + } + + ret_val = odm_get_bb_reg(p_dm_odm, 0xf8c, MASKBYTE0); + ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_TRACE,("PHYDM_DynamicSoftMLSetting(): Read 0xF8C = 0x%08X\n",ret_val)); + + if (ret_val < 0x16) { + ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_LOUD,("PHYDM_DynamicSoftMLSetting(): 0xF8C(== 0x%08X) < 0x16, enable SoML\n",ret_val)); + phydm_somlrxhp_setting(p_dm_odm, true); + /* odm_set_bb_reg(p_dm_odm, 0x19a8, MASKDWORD, 0xc10a0000); */ + p_dm_odm->bsomlenabled = true; + } + } } #endif + } -VOID -PHYDM_InitHwInfoByRfe( - IN PDM_ODM_T pDM_Odm + +void +phydm_init_soft_ml_setting( + struct PHY_DM_STRUCT *p_dm_odm ) { #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8822B) - phydm_init_hw_info_by_rfe_type_8822b(pDM_Odm); + if (*(p_dm_odm->p_mp_mode) == false) { + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + /*odm_set_bb_reg(p_dm_odm, 0x19a8, MASKDWORD, 0xd10a0000);*/ + phydm_somlrxhp_setting(p_dm_odm, true); + p_dm_odm->bsomlenabled = true; + } +#endif +#if (RTL8821C_SUPPORT == 1) + if (*(p_dm_odm->p_mp_mode) == false) { + if (p_dm_odm->support_ic_type & ODM_RTL8821C) + odm_set_bb_reg(p_dm_odm, 0x19a8, BIT(31)|BIT(30)|BIT(29)|BIT(28), 0xd); + } #endif } -VOID -odm_CommonInfoSelfInit( - IN PDM_ODM_T pDM_Odm - ) +void +phydm_init_hw_info_by_rfe( + struct PHY_DM_STRUCT *p_dm_odm +) { - phydm_Init_cck_setting(pDM_Odm); - pDM_Odm->RFPathRxEnable = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(BB_RX_PATH,pDM_Odm), ODM_BIT(BB_RX_PATH,pDM_Odm)); -#if (DM_ODM_SUPPORT_TYPE != ODM_CE) - pDM_Odm->pbNet_closed = &pDM_Odm->BOOLEAN_temp; +#if (RTL8822B_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + phydm_init_hw_info_by_rfe_type_8822b(p_dm_odm); #endif +#if (RTL8821C_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8821C) + phydm_init_hw_info_by_rfe_type_8821c(p_dm_odm); +#endif +#if (RTL8197F_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8197F) + phydm_init_hw_info_by_rfe_type_8197f(p_dm_odm); +#endif +} - PHYDM_InitDebugSetting(pDM_Odm); - ODM_InitMpDriverStatus(pDM_Odm); - PHYDM_InitTRXAntennaSetting(pDM_Odm); - PHYDM_InitSoftMLSetting(pDM_Odm); - - pDM_Odm->TxRate = 0xFF; - - pDM_Odm->number_linked_client = 0; - pDM_Odm->pre_number_linked_client = 0; - pDM_Odm->number_active_client = 0; - pDM_Odm->pre_number_active_client = 0; +void +odm_common_info_self_init( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + phydm_init_cck_setting(p_dm_odm); + p_dm_odm->rf_path_rx_enable = (u8) odm_get_bb_reg(p_dm_odm, ODM_REG(BB_RX_PATH, p_dm_odm), ODM_BIT(BB_RX_PATH, p_dm_odm)); +#if (DM_ODM_SUPPORT_TYPE != ODM_CE) + p_dm_odm->p_is_net_closed = &p_dm_odm->BOOLEAN_temp; - pDM_Odm->lastTxOkCnt = 0; - pDM_Odm->lastRxOkCnt = 0; - pDM_Odm->tx_tp = 0; - pDM_Odm->rx_tp = 0; - pDM_Odm->total_tp = 0; - pDM_Odm->TrafficLoad = TRAFFIC_LOW; + phydm_init_debug_setting(p_dm_odm); +#endif + phydm_init_trx_antenna_setting(p_dm_odm); + phydm_init_soft_ml_setting(p_dm_odm); + + p_dm_odm->phydm_period = PHYDM_WATCH_DOG_PERIOD; + p_dm_odm->phydm_sys_up_time = 0; + + if (p_dm_odm->support_ic_type & ODM_IC_1SS) + p_dm_odm->num_rf_path = 1; + else if (p_dm_odm->support_ic_type & ODM_IC_2SS) + p_dm_odm->num_rf_path = 2; + else if (p_dm_odm->support_ic_type & ODM_IC_3SS) + p_dm_odm->num_rf_path = 3; + else if (p_dm_odm->support_ic_type & ODM_IC_4SS) + p_dm_odm->num_rf_path = 4; + + p_dm_odm->tx_rate = 0xFF; + p_dm_odm->rssi_min_by_path = 0xFF; + + p_dm_odm->number_linked_client = 0; + p_dm_odm->pre_number_linked_client = 0; + p_dm_odm->number_active_client = 0; + p_dm_odm->pre_number_active_client = 0; + + p_dm_odm->last_tx_ok_cnt = 0; + p_dm_odm->last_rx_ok_cnt = 0; + p_dm_odm->tx_tp = 0; + p_dm_odm->rx_tp = 0; + p_dm_odm->total_tp = 0; + p_dm_odm->traffic_load = TRAFFIC_LOW; + + p_dm_odm->nbi_set_result = 0; + p_dm_odm->is_init_hw_info_by_rfe = false; + p_dm_odm->pre_dbg_priority = BB_DBGPORT_RELEASE; + p_dm_odm->tp_active_th = 5; - pDM_Odm->nbi_set_result = 0; - } -VOID -odm_CommonInfoSelfUpdate( - IN PDM_ODM_T pDM_Odm - ) +void +odm_common_info_self_update( + struct PHY_DM_STRUCT *p_dm_odm +) { - u1Byte EntryCnt = 0, num_active_client = 0; - u4Byte i, OneEntry_MACID = 0, ma_rx_tp = 0; - PSTA_INFO_T pEntry; + u8 entry_cnt = 0, num_active_client = 0; + u32 i, one_entry_macid = 0; + u32 ma_rx_tp = 0; + struct sta_info *p_entry; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + struct _ADAPTER *adapter = p_dm_odm->adapter; + PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; - pEntry = pDM_Odm->pODM_StaInfo[0]; - if (pMgntInfo->mAssoc) { - pEntry->bUsed = TRUE; + p_entry = p_dm_odm->p_odm_sta_info[0]; + if (p_mgnt_info->mAssoc) { + p_entry->bUsed = true; for (i = 0; i < 6; i++) - pEntry->MacAddr[i] = pMgntInfo->Bssid[i]; - } else if (GetFirstClientPort(Adapter)) { - PADAPTER pClientAdapter = GetFirstClientPort(Adapter); + p_entry->MacAddr[i] = p_mgnt_info->Bssid[i]; + } else if (GetFirstClientPort(adapter)) { + struct _ADAPTER *p_client_adapter = GetFirstClientPort(adapter); - pEntry->bUsed = TRUE; + p_entry->bUsed = true; for (i = 0; i < 6; i++) - pEntry->MacAddr[i] = pClientAdapter->MgntInfo.Bssid[i]; + p_entry->MacAddr[i] = p_client_adapter->MgntInfo.Bssid[i]; } else { - pEntry->bUsed = FALSE; + p_entry->bUsed = false; for (i = 0; i < 6; i++) - pEntry->MacAddr[i] = 0; + p_entry->MacAddr[i] = 0; } - //STA mode is linked to AP - if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[0]) && !ACTING_AS_AP(Adapter)) - pDM_Odm->bsta_state = TRUE; + /* STA mode is linked to AP */ + if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[0]) && !ACTING_AS_AP(adapter)) + p_dm_odm->bsta_state = true; else - pDM_Odm->bsta_state = FALSE; + p_dm_odm->bsta_state = false; #endif -/* THis variable cannot be used because it is wrong*/ + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + p_entry = p_dm_odm->p_odm_sta_info[i]; + if (IS_STA_VALID(p_entry)) { + entry_cnt++; + if (entry_cnt == 1) + one_entry_macid = i; + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) - { - if (*(pDM_Odm->pSecChOffset) == 1) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; - else if (*(pDM_Odm->pSecChOffset) == 2) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; - } else if (*(pDM_Odm->pBandWidth) == ODM_BW80M) { - if (*(pDM_Odm->pSecChOffset) == 1) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 6; - else if (*(pDM_Odm->pSecChOffset) == 2) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 6; - } else - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); -#else - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { - if (*(pDM_Odm->pSecChOffset) == 1) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; - else if (*(pDM_Odm->pSecChOffset) == 2) - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; - } else - pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); + ma_rx_tp = (p_entry->rx_byte_cnt_low_maw) >> 17; /* low moving average RX TP ( bit /sec), , <<3(8bit), >>20(10^6,M)*/ + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("ClientTP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp)); + + if (ma_rx_tp > ACTIVE_TP_THRESHOLD) + num_active_client++; #endif + } + } - for (i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pEntry)) - { - EntryCnt++; - if(EntryCnt==1) - { - OneEntry_MACID=i; - } + if (entry_cnt == 1) { + p_dm_odm->is_one_entry_only = true; + p_dm_odm->one_entry_macid = one_entry_macid; + p_dm_odm->one_entry_tp = ma_rx_tp; - #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - ma_rx_tp = (pEntry->rx_byte_cnt_LowMAW)<<3; /* low moving average RX TP ( bit /sec)*/ + p_dm_odm->tp_active_occur = 0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("ClientTP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp)); - - if (ma_rx_tp > ACTIVE_TP_THRESHOLD) - num_active_client++; - #endif - } - } - - if(EntryCnt == 1) - { - pDM_Odm->bOneEntryOnly = TRUE; - pDM_Odm->OneEntry_MACID=OneEntry_MACID; - } - else - pDM_Odm->bOneEntryOnly = FALSE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n", + p_dm_odm->one_entry_tp, p_dm_odm->pre_one_entry_tp)); - pDM_Odm->pre_number_linked_client = pDM_Odm->number_linked_client; - pDM_Odm->pre_number_active_client = pDM_Odm->number_active_client; - - pDM_Odm->number_linked_client = EntryCnt; - pDM_Odm->number_active_client = num_active_client; + if ((p_dm_odm->one_entry_tp > p_dm_odm->pre_one_entry_tp) && (p_dm_odm->pre_one_entry_tp <= 2)) { + if ((p_dm_odm->one_entry_tp - p_dm_odm->pre_one_entry_tp) > p_dm_odm->tp_active_th) + p_dm_odm->tp_active_occur = 1; + } + p_dm_odm->pre_one_entry_tp = p_dm_odm->one_entry_tp; + } else + p_dm_odm->is_one_entry_only = false; - /* Update MP driver status*/ - ODM_UpdateMpDriverStatus(pDM_Odm); + p_dm_odm->pre_number_linked_client = p_dm_odm->number_linked_client; + p_dm_odm->pre_number_active_client = p_dm_odm->number_active_client; + + p_dm_odm->number_linked_client = entry_cnt; + p_dm_odm->number_active_client = num_active_client; /*Traffic load information update*/ - phydm_traffic_load_decision(pDM_Odm); + phydm_traffic_load_decision(p_dm_odm); + + p_dm_odm->phydm_sys_up_time += p_dm_odm->phydm_period; } -VOID -odm_CommonInfoSelfReset( - IN PDM_ODM_T pDM_Odm - ) +void +odm_common_info_self_reset( + struct PHY_DM_STRUCT *p_dm_odm +) { -#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pDM_Odm->PhyDbgInfo.NumQryBeaconPkt = 0; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + p_dm_odm->phy_dbg_info.num_qry_beacon_pkt = 0; #endif } -PVOID -PhyDM_Get_Structure( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Structure_Type +void * +phydm_get_structure( + struct PHY_DM_STRUCT *p_dm_odm, + u8 structure_type ) { - PVOID pStruct = NULL; + void *p_struct = NULL; #if RTL8195A_SUPPORT - switch (Structure_Type){ - case PHYDM_FALSEALMCNT: - pStruct = &FalseAlmCnt; + switch (structure_type) { + case PHYDM_FALSEALMCNT: + p_struct = &false_alm_cnt; break; - - case PHYDM_CFOTRACK: - pStruct = &DM_CfoTrack; + + case PHYDM_CFOTRACK: + p_struct = &dm_cfo_track; break; - case PHYDM_ADAPTIVITY: - pStruct = &(pDM_Odm->Adaptivity); + case PHYDM_ADAPTIVITY: + p_struct = &(p_dm_odm->adaptivity); break; - - default: + + default: break; } #else - switch (Structure_Type){ - case PHYDM_FALSEALMCNT: - pStruct = &(pDM_Odm->FalseAlmCnt); + switch (structure_type) { + case PHYDM_FALSEALMCNT: + p_struct = &(p_dm_odm->false_alm_cnt); break; - - case PHYDM_CFOTRACK: - pStruct = &(pDM_Odm->DM_CfoTrack); + + case PHYDM_CFOTRACK: + p_struct = &(p_dm_odm->dm_cfo_track); break; - case PHYDM_ADAPTIVITY: - pStruct = &(pDM_Odm->Adaptivity); + case PHYDM_ADAPTIVITY: + p_struct = &(p_dm_odm->adaptivity); break; - - default: + + default: break; } #endif - return pStruct; + return p_struct; } -VOID -odm_HWSetting( - IN PDM_ODM_T pDM_Odm - ) +void +odm_hw_setting( + struct PHY_DM_STRUCT *p_dm_odm +) { #if (RTL8821A_SUPPORT == 1) - if(pDM_Odm->SupportICType & ODM_RTL8821) - odm_HWSetting_8821A(pDM_Odm); + if (p_dm_odm->support_ic_type & ODM_RTL8821) + odm_hw_setting_8821a(p_dm_odm); #endif #if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8814A) - phydm_hwsetting_8814a(pDM_Odm); + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + phydm_hwsetting_8814a(p_dm_odm); #endif -} - -// -// 2011/09/21 MH Add to describe different team necessary resource allocate?? -// -VOID -ODM_DMInit( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); -#endif - - odm_CommonInfoSelfInit(pDM_Odm); - odm_DIGInit(pDM_Odm); - Phydm_NHMCounterStatisticsInit(pDM_Odm); - Phydm_AdaptivityInit(pDM_Odm); - phydm_ra_info_init(pDM_Odm); - odm_RateAdaptiveMaskInit(pDM_Odm); - ODM_CfoTrackingInit(pDM_Odm); - ODM_EdcaTurboInit(pDM_Odm); - odm_RSSIMonitorInit(pDM_Odm); - phydm_rf_init(pDM_Odm); - odm_TXPowerTrackingInit(pDM_Odm); - odm_AntennaDiversityInit(pDM_Odm); - odm_AutoChannelSelectInit(pDM_Odm); - odm_PathDiversityInit(pDM_Odm); - odm_DynamicTxPowerInit(pDM_Odm); - phydm_initRaInfo(pDM_Odm); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#ifdef BEAMFORMING_VERSION_1 - if (pHalData->BeamformingVersion == BEAMFORMING_VERSION_1) +#if (RTL8822B_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + phydm_hwsetting_8822b(p_dm_odm); #endif - { - phydm_Beamforming_Init(pDM_Odm); - } -#endif - - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - odm_DynamicBBPowerSavingInit(pDM_Odm); -#if (RTL8188E_SUPPORT == 1) - if(pDM_Odm->SupportICType==ODM_RTL8188E) - { - ODM_PrimaryCCA_Init(pDM_Odm); - ODM_RAInfo_Init_all(pDM_Odm); - } +#if (RTL8197F_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8197F) + phydm_hwsetting_8197f(p_dm_odm); #endif +} -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - - #if (RTL8723B_SUPPORT == 1) - if(pDM_Odm->SupportICType == ODM_RTL8723B) - odm_SwAntDetectInit(pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +u32 +phydm_supportability_init_win( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 support_ability = 0; + + switch (p_dm_odm->support_ic_type) { + + /*---------------N Series--------------------*/ + #if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT | + ODM_BB_PRIMARY_CCA; + break; #endif #if (RTL8192E_SUPPORT == 1) - if(pDM_Odm->SupportICType==ODM_RTL8192E) - odm_PrimaryCCA_Check_Init(pDM_Odm); + case ODM_RTL8192E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT | + ODM_BB_PRIMARY_CCA; + break; #endif -#endif - - } + #if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8703B_SUPPORT == 1) + case ODM_RTL8703B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8723D_SUPPORT == 1) + case ODM_RTL8723D: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /* ODM_BB_PWR_TRAIN | */ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8710B_SUPPORT == 1) + case ODM_RTL8710B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + #if (RTL8188F_SUPPORT == 1) + case ODM_RTL8188F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + /*---------------AC Series-------------------*/ + + #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + case ODM_RTL8812: + case ODM_RTL8821: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8814A_SUPPORT == 1) + case ODM_RTL8814A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT | + ODM_BB_DYNAMIC_PSDTOOL; + break; + #endif + + #if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + + dbg_print("[Warning] Supportability Init Warning !!!\n"); + break; + + } + + /*[Config Antenna Diveristy]*/ + if (*(p_dm_odm->p_enable_antdiv)) + support_ability |= ODM_BB_ANT_DIV; + + /*[Config Adaptivity]*/ + if (*(p_dm_odm->p_enable_adaptivity)) + support_ability |= ODM_BB_ADAPTIVITY; + + return support_ability; } +#endif -VOID -ODM_DMReset( - IN PDM_ODM_T pDM_Odm - ) +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +u32 +phydm_supportability_init_ce( + void *p_dm_void +) { - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 support_ability = 0; + + switch (p_dm_odm->support_ic_type) { + + /*---------------N Series--------------------*/ + #if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT | + ODM_BB_PRIMARY_CCA; + break; + #endif + + #if (RTL8192E_SUPPORT == 1) + case ODM_RTL8192E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8703B_SUPPORT == 1) + case ODM_RTL8703B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8723D_SUPPORT == 1) + case ODM_RTL8723D: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /* ODM_BB_PWR_TRAIN | */ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8710B_SUPPORT == 1) + case ODM_RTL8710B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8188F_SUPPORT == 1) + case ODM_RTL8188F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + /*---------------AC Series-------------------*/ + + #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + case ODM_RTL8812: + case ODM_RTL8821: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8814A_SUPPORT == 1) + case ODM_RTL8814A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT | + ODM_BB_DYNAMIC_PSDTOOL; + break; + #endif + + #if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + + dbg_print("[Warning] Supportability Init Warning !!!\n"); + break; - ODM_AntDivReset(pDM_Odm); - phydm_setEDCCAThresholdAPI(pDM_Odm, pDM_DigTable->CurIGValue); + } + + /*[Config Antenna Diveristy]*/ + if (*(p_dm_odm->p_enable_antdiv)) + support_ability |= ODM_BB_ANT_DIV; + + /*[Config Adaptivity]*/ + if (*(p_dm_odm->p_enable_adaptivity)) + support_ability |= ODM_BB_ADAPTIVITY; + + return support_ability; } +#endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +u32 +phydm_supportability_init_ap( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 support_ability = 0; + + switch (p_dm_odm->support_ic_type) { + + /*---------------N Series--------------------*/ + #if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT | + ODM_BB_PRIMARY_CCA; + break; + #endif -VOID -phydm_support_ability_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte pre_support_ability; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - pre_support_ability = pDM_Odm->SupportAbility ; - PHYDM_SNPRINTF((output+used, out_len-used,"\n%s\n", "================================")); - if(dm_value[0] == 100) + #if (RTL8192E_SUPPORT == 1) + case ODM_RTL8192E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if ((RTL8198F_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + case ODM_RTL8198F: + case ODM_RTL8197F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + /*---------------AC Series-------------------*/ + + #if (RTL8881A_SUPPORT == 1) + case ODM_RTL8881A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8814A_SUPPORT == 1) + case ODM_RTL8814A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT | + ODM_BB_DYNAMIC_PSDTOOL; + break; + #endif + + #if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + + break; + #endif + + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + + dbg_print("[Warning] Supportability Init Warning !!!\n"); + break; + + } + + #if 0 + /*[Config Antenna Diveristy]*/ + if (*(p_dm_odm->p_enable_antdiv)) + support_ability |= ODM_BB_ANT_DIV; + + /*[Config Adaptivity]*/ + if (*(p_dm_odm->p_enable_adaptivity)) + support_ability |= ODM_BB_ADAPTIVITY; + #endif + + return support_ability; +} +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT)) +u32 +phydm_supportability_init_iot( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 support_ability = 0; + + switch (p_dm_odm->support_ic_type) { + + #if (RTL8710B_SUPPORT == 1) + case ODM_RTL8710B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + #if (RTL8195A_SUPPORT == 1) + case ODM_RTL8195A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + break; + #endif + + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT; + + dbg_print("[Warning] Supportability Init Warning !!!\n"); + break; + + } + + /*[Config Antenna Diveristy]*/ + if (*(p_dm_odm->p_enable_antdiv)) + support_ability |= ODM_BB_ANT_DIV; + + /*[Config Adaptivity]*/ + if (*(p_dm_odm->p_enable_adaptivity)) + support_ability |= ODM_BB_ADAPTIVITY; + + return support_ability; +} +#endif + +void +phydm_fwoffload_ability_init( + struct PHY_DM_STRUCT *p_dm_odm, + enum phydm_offload_ability offload_ability +) +{ + + switch (offload_ability) { + + case PHYDM_PHY_PARAM_OFFLOAD: + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + p_dm_odm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD; + break; + + case PHYDM_RF_IQK_OFFLOAD: + p_dm_odm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD; + break; + + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("fwofflad, wrong init type!!\n")); + break; + + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("fw_offload_ability = %x\n", p_dm_odm->fw_offload_ability)); + +} +void +phydm_fwoffload_ability_clear( + struct PHY_DM_STRUCT *p_dm_odm, + enum phydm_offload_ability offload_ability +) +{ + + switch (offload_ability) { + + case PHYDM_PHY_PARAM_OFFLOAD: + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + p_dm_odm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD); + break; + + case PHYDM_RF_IQK_OFFLOAD: + p_dm_odm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD); + break; + + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("fwofflad, wrong init type!!\n")); + break; + + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("fw_offload_ability = %x\n", p_dm_odm->fw_offload_ability)); + +} + +void +phydm_supportability_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 support_ability; + + if (*(p_dm_odm->p_mp_mode) == true) { + support_ability = 0; + /**/ + } else { + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + support_ability = phydm_supportability_init_win(p_dm_odm); + #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + support_ability = phydm_supportability_init_ap(p_dm_odm); + #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) + support_ability = phydm_supportability_init_ce(p_dm_odm); + #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) + support_ability = phydm_supportability_init_iot(p_dm_odm); + #endif + } + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ABILITY, support_ability); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IC = ((0x%x)), Supportability Init = ((0x%x))\n", p_dm_odm->support_ic_type, p_dm_odm->support_ability)); +} + + +void +phydm_dm_early_init( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + /*odm_init_mp_driver_status(p_dm_odm);*/ + halrf_init(p_dm_odm); + #endif +} + +void +odm_dm_init( + struct PHY_DM_STRUCT *p_dm_odm +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); +#endif + + halrf_init(p_dm_odm); + phydm_supportability_init(p_dm_odm); + odm_common_info_self_init(p_dm_odm); + odm_dig_init(p_dm_odm); + phydm_nhm_counter_statistics_init(p_dm_odm); + phydm_adaptivity_init(p_dm_odm); + phydm_ra_info_init(p_dm_odm); + odm_rate_adaptive_mask_init(p_dm_odm); + odm_cfo_tracking_init(p_dm_odm); + odm_rssi_monitor_init(p_dm_odm); + phydm_rf_init(p_dm_odm); + odm_txpowertracking_init(p_dm_odm); + phydm_dc_cancellation(p_dm_odm); +#if (PHYDM_TXA_CALIBRATION == 1) + phydm_txcurrentcalibration(p_dm_odm); + phydm_get_pa_bias_offset(p_dm_odm); +#endif + odm_antenna_diversity_init(p_dm_odm); +#if (CONFIG_DYNAMIC_RX_PATH == 1) + phydm_dynamic_rx_path_init(p_dm_odm); +#endif + odm_auto_channel_select_init(p_dm_odm); + odm_path_diversity_init(p_dm_odm); + odm_dynamic_tx_power_init(p_dm_odm); + phydm_init_ra_info(p_dm_odm); +#if (PHYDM_LA_MODE_SUPPORT == 1) + adc_smp_init(p_dm_odm); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #ifdef BEAMFORMING_VERSION_1 + if (p_hal_data->beamforming_version == BEAMFORMING_VERSION_1) + #endif { - PHYDM_SNPRINTF((output+used, out_len-used, "[Supportability] PhyDM Selection\n")); - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================")); - PHYDM_SNPRINTF((output+used, out_len-used, "00. (( %s ))DIG\n", ((pDM_Odm->SupportAbility & ODM_BB_DIG)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "01. (( %s ))RA_MASK\n", ((pDM_Odm->SupportAbility & ODM_BB_RA_MASK)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "02. (( %s ))DYNAMIC_TXPWR\n", ((pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "03. (( %s ))FA_CNT\n", ((pDM_Odm->SupportAbility & ODM_BB_FA_CNT)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "04. (( %s ))RSSI_MONITOR\n", ((pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "05. (( %s ))CCK_PD\n", ((pDM_Odm->SupportAbility & ODM_BB_CCK_PD)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "06. (( %s ))ANT_DIV\n", ((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "08. (( %s ))PWR_TRAIN\n", ((pDM_Odm->SupportAbility & ODM_BB_PWR_TRAIN)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "09. (( %s ))RATE_ADAPTIVE\n", ((pDM_Odm->SupportAbility & ODM_BB_RATE_ADAPTIVE)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "10. (( %s ))PATH_DIV\n", ((pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "13. (( %s ))ADAPTIVITY\n", ((pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "14. (( %s ))CFO_TRACKING\n", ((pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "15. (( %s ))NHM_CNT\n", ((pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "16. (( %s ))PRIMARY_CCA\n", ((pDM_Odm->SupportAbility & ODM_BB_PRIMARY_CCA)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "17. (( %s ))TXBF\n", ((pDM_Odm->SupportAbility & ODM_BB_TXBF)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "18. (( %s ))DYNAMIC_ARFR\n", ((pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_ARFR)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "20. (( %s ))EDCA_TURBO\n", ((pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "21. (( %s ))EARLY_MODE\n", ((pDM_Odm->SupportAbility & ODM_MAC_EARLY_MODE)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "24. (( %s ))TX_PWR_TRACK\n", ((pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "25. (( %s ))RX_GAIN_TRACK\n", ((pDM_Odm->SupportAbility & ODM_RF_RX_GAIN_TRACK)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used, "26. (( %s ))RF_CALIBRATION\n", ((pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)?("V"):(".")))); - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================")); + phydm_beamforming_init(p_dm_odm); + } +#endif + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + #if (defined(CONFIG_BB_POWER_SAVING)) + odm_dynamic_bb_power_saving_init(p_dm_odm); + #endif + + #if (RTL8188E_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + odm_primary_cca_init(p_dm_odm); + odm_ra_info_init_all(p_dm_odm); + } + #endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + + #if (RTL8723B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8723B) + odm_sw_ant_detect_init(p_dm_odm); + #endif + + #if (RTL8192E_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8192E) + odm_primary_cca_check_init(p_dm_odm); + #endif + +#endif + + } + + #if (CONFIG_PSD_TOOL == 1) + phydm_psd_init(p_dm_odm); + #endif + +} + +void +odm_dm_reset( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + + odm_ant_div_reset(p_dm_odm); + phydm_set_edcca_threshold_api(p_dm_odm, p_dm_dig_table->cur_ig_value); +} + +void +phydm_primary_cca( + struct PHY_DM_STRUCT *p_dm_odm +) +{ +#if PHYDM_PRIMARY_CCA + + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + #if (RTL8188E_SUPPORT == 1) + odm_dynamic_primary_cca_8188e(p_dm_odm); + #endif + } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + #if (RTL8192E_SUPPORT == 1) + odm_dynamic_primary_cca_check_8192e(p_dm_odm); + #endif + } + +#endif +} + +void +phydm_support_ability_debug( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 pre_support_ability; + u32 used = *_used; + u32 out_len = *_out_len; + + pre_support_ability = p_dm_odm->support_ability ; + PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); + if (dm_value[0] == 100) { + PHYDM_SNPRINTF((output + used, out_len - used, "[Supportability] PhyDM Selection\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((p_dm_odm->support_ability & ODM_BB_DIG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((p_dm_odm->support_ability & ODM_BB_RA_MASK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((p_dm_odm->support_ability & ODM_BB_FA_CNT) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))CCK_PD\n", ((p_dm_odm->support_ability & ODM_BB_CCK_PD) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))PWR_TRAIN\n", ((p_dm_odm->support_ability & ODM_BB_PWR_TRAIN) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((p_dm_odm->support_ability & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((p_dm_odm->support_ability & ODM_BB_PATH_DIV) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "13. (( %s ))ADAPTIVITY\n", ((p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))struct _CFO_TRACKING_\n", ((p_dm_odm->support_ability & ODM_BB_CFO_TRACKING) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))NHM_CNT\n", ((p_dm_odm->support_ability & ODM_BB_NHM_CNT) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))PRIMARY_CCA\n", ((p_dm_odm->support_ability & ODM_BB_PRIMARY_CCA) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))TXBF\n", ((p_dm_odm->support_ability & ODM_BB_TXBF) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))DYNAMIC_ARFR\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "19. (( %s ))DYNAMIC_PSD_TOOL\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_PSDTOOL) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "20. (( %s ))EDCA_TURBO\n", ((p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "21. (( %s ))DYNAMIC_RX_PATH\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); } /* else if(dm_value[0] == 101) { - pDM_Odm->SupportAbility = 0 ; - DbgPrint("Disable all SupportAbility components \n"); - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "Disable all SupportAbility components")); + p_dm_odm->support_ability = 0 ; + dbg_print("Disable all support_ability components\n"); + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "Disable all support_ability components")); } */ - else - { + else { - if(dm_value[1] == 1) //enable - { - pDM_Odm->SupportAbility |= BIT(dm_value[0]) ; - if(BIT(dm_value[0]) & ODM_BB_PATH_DIV) - { - odm_PathDiversityInit(pDM_Odm); - } - } - else if(dm_value[1] == 2) //disable - { - pDM_Odm->SupportAbility &= ~(BIT(dm_value[0])) ; - } - else - { - //DbgPrint("\n[Warning!!!] 1:enable, 2:disable \n\n"); - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "[Warning!!!] 1:enable, 2:disable")); + if (dm_value[1] == 1) { /* enable */ + p_dm_odm->support_ability |= BIT(dm_value[0]) ; + if (BIT(dm_value[0]) & ODM_BB_PATH_DIV) + odm_path_diversity_init(p_dm_odm); + } else if (dm_value[1] == 2) /* disable */ + p_dm_odm->support_ability &= ~(BIT(dm_value[0])) ; + else { + /* dbg_print("\n[Warning!!!] 1:enable, 2:disable \n\n"); */ + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); } } - PHYDM_SNPRINTF((output+used, out_len-used,"pre-SupportAbility = 0x%x\n", pre_support_ability )); - PHYDM_SNPRINTF((output+used, out_len-used,"Curr-SupportAbility = 0x%x\n", pDM_Odm->SupportAbility )); - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================")); + PHYDM_SNPRINTF((output + used, out_len - used, "pre-support_ability = 0x%x\n", pre_support_ability)); + PHYDM_SNPRINTF((output + used, out_len - used, "Curr-support_ability = 0x%x\n", p_dm_odm->support_ability)); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); } #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -// -//tmp modify for LC Only -// -VOID -ODM_DMWatchdog_LPS( - IN PDM_ODM_T pDM_Odm - ) -{ - odm_CommonInfoSelfUpdate(pDM_Odm); - odm_FalseAlarmCounterStatistics(pDM_Odm); - odm_RSSIMonitorCheck(pDM_Odm); - odm_DIGbyRSSI_LPS(pDM_Odm); - odm_CCKPacketDetectionThresh(pDM_Odm); - odm_CommonInfoSelfReset(pDM_Odm); - - if(*(pDM_Odm->pbPowerSaving)==TRUE) +/* + * tmp modify for LC Only + * */ +void +odm_dm_watchdog_lps( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + odm_common_info_self_update(p_dm_odm); + odm_false_alarm_counter_statistics(p_dm_odm); + odm_rssi_monitor_check(p_dm_odm); + odm_dig_by_rssi_lps(p_dm_odm); +#if PHYDM_SUPPORT_CCKPD + odm_cck_packet_detection_thresh(p_dm_odm); +#endif + odm_common_info_self_reset(p_dm_odm); + + if (*(p_dm_odm->p_is_power_saving) == true) return; } #endif -// -// 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. -// You can not add any dummy function here, be care, you can only use DM structure -// to perform any new ODM_DM. -// -VOID -ODM_DMWatchdog( - IN PDM_ODM_T pDM_Odm - ) + +void +phydm_watchdog_mp( + struct PHY_DM_STRUCT *p_dm_odm +) { - odm_CommonInfoSelfUpdate(pDM_Odm); - phydm_BasicDbgMessage(pDM_Odm); - odm_HWSetting(pDM_Odm); +#if (CONFIG_DYNAMIC_RX_PATH == 1) + phydm_dynamic_rx_path_caller(p_dm_odm); +#endif +} +/* + * 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. + * You can not add any dummy function here, be care, you can only use DM structure + * to perform any new ODM_DM. + * */ +void +odm_dm_watchdog( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + odm_common_info_self_update(p_dm_odm); + phydm_basic_dbg_message(p_dm_odm); + odm_hw_setting(p_dm_odm); #if (DM_ODM_SUPPORT_TYPE == ODM_AP) { - prtl8192cd_priv priv = pDM_Odm->priv; - if( (priv->auto_channel != 0) && (priv->auto_channel != 2) )//if ACS running, do not do FA/CCA counter read - return; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + if ((priv->auto_channel != 0) && (priv->auto_channel != 2)) /* if struct _ACS_ running, do not do FA/CCA counter read */ + return; } -#endif - odm_FalseAlarmCounterStatistics(pDM_Odm); - phydm_NoisyDetection(pDM_Odm); - - odm_RSSIMonitorCheck(pDM_Odm); +#endif + odm_false_alarm_counter_statistics(p_dm_odm); + phydm_noisy_detection(p_dm_odm); - if(*(pDM_Odm->pbPowerSaving) == TRUE) - { - odm_DIGbyRSSI_LPS(pDM_Odm); - { - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - Phydm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue); - } - #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - odm_AntennaDiversity(pDM_Odm); /*enable AntDiv in PS mode, request from SD4 Jeff*/ - #endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("DMWatchdog in power saving mode\n")); + odm_rssi_monitor_check(p_dm_odm); + + if (*(p_dm_odm->p_is_power_saving) == true) { + odm_dig_by_rssi_lps(p_dm_odm); + phydm_adaptivity(p_dm_odm); +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + odm_antenna_diversity(p_dm_odm); /*enable AntDiv in PS mode, request from SD4 Jeff*/ +#endif + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("DMWatchdog in power saving mode\n")); return; } - - Phydm_CheckAdaptivity(pDM_Odm); - odm_UpdatePowerTrainingState(pDM_Odm); - odm_DIG(pDM_Odm); - { - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - Phydm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue); - } - odm_CCKPacketDetectionThresh(pDM_Odm); - - phydm_ra_info_watchdog(pDM_Odm); - odm_EdcaTurboCheck(pDM_Odm); - odm_PathDiversity(pDM_Odm); - ODM_CfoTracking(pDM_Odm); - odm_DynamicTxPower(pDM_Odm); - odm_AntennaDiversity(pDM_Odm); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - phydm_Beamforming_Watchdog(pDM_Odm); -#endif - phydm_rf_watchdog(pDM_Odm); - - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - -#if (RTL8188E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188E) - ODM_DynamicPrimaryCCA(pDM_Odm); + phydm_check_adaptivity(p_dm_odm); + odm_update_power_training_state(p_dm_odm); + odm_DIG(p_dm_odm); + phydm_adaptivity(p_dm_odm); +#if PHYDM_SUPPORT_CCKPD + odm_cck_packet_detection_thresh(p_dm_odm); #endif -#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + phydm_ra_info_watchdog(p_dm_odm); + phydm_receiver_blocking(p_dm_odm); + odm_path_diversity(p_dm_odm); + odm_cfo_tracking(p_dm_odm); + odm_dynamic_tx_power(p_dm_odm); + odm_antenna_diversity(p_dm_odm); +#if (CONFIG_DYNAMIC_RX_PATH == 1) + phydm_dynamic_rx_path(p_dm_odm); +#endif - #if (RTL8192E_SUPPORT == 1) - if(pDM_Odm->SupportICType==ODM_RTL8192E) - odm_DynamicPrimaryCCA_Check(pDM_Odm); - #endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + phydm_beamforming_watchdog(p_dm_odm); #endif - } + + halrf_watchdog(p_dm_odm); + phydm_primary_cca(p_dm_odm); #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - odm_dtc(pDM_Odm); + odm_dtc(p_dm_odm); #endif - odm_CommonInfoSelfReset(pDM_Odm); - + odm_common_info_self_reset(p_dm_odm); + } -// -// Init /.. Fixed HW value. Only init time. -// -VOID -ODM_CmnInfoInit( - IN PDM_ODM_T pDM_Odm, - IN ODM_CMNINFO_E CmnInfo, - IN u4Byte Value - ) +/* + * Init /.. Fixed HW value. Only init time. + * */ +void +odm_cmn_info_init( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_cmninfo_e cmn_info, + u32 value +) { - // - // This section is used for init value - // - switch (CmnInfo) - { - // - // Fixed ODM value. - // - case ODM_CMNINFO_ABILITY: - pDM_Odm->SupportAbility = (u4Byte)Value; - break; + /* */ + /* This section is used for init value */ + /* */ + switch (cmn_info) { + /* */ + /* Fixed ODM value. */ + /* */ + case ODM_CMNINFO_ABILITY: + p_dm_odm->support_ability = (u32)value; + break; - case ODM_CMNINFO_RF_TYPE: - pDM_Odm->RFType = (u1Byte)Value; - break; + case ODM_CMNINFO_RF_TYPE: + p_dm_odm->rf_type = (u8)value; + break; - case ODM_CMNINFO_PLATFORM: - pDM_Odm->SupportPlatform = (u1Byte)Value; - break; + case ODM_CMNINFO_PLATFORM: + p_dm_odm->support_platform = (u8)value; + break; - case ODM_CMNINFO_INTERFACE: - pDM_Odm->SupportInterface = (u1Byte)Value; - break; + case ODM_CMNINFO_INTERFACE: + p_dm_odm->support_interface = (u8)value; + break; - case ODM_CMNINFO_MP_TEST_CHIP: - pDM_Odm->bIsMPChip= (u1Byte)Value; - break; - - case ODM_CMNINFO_IC_TYPE: - pDM_Odm->SupportICType = Value; - break; + case ODM_CMNINFO_MP_TEST_CHIP: + p_dm_odm->is_mp_chip = (u8)value; + break; - case ODM_CMNINFO_CUT_VER: - pDM_Odm->CutVersion = (u1Byte)Value; - break; + case ODM_CMNINFO_IC_TYPE: + p_dm_odm->support_ic_type = value; + break; - case ODM_CMNINFO_FAB_VER: - pDM_Odm->FabVersion = (u1Byte)Value; - break; + case ODM_CMNINFO_CUT_VER: + p_dm_odm->cut_version = (u8)value; + break; - case ODM_CMNINFO_RFE_TYPE: - pDM_Odm->RFEType = (u1Byte)Value; - PHYDM_InitHwInfoByRfe(pDM_Odm); - break; + case ODM_CMNINFO_FAB_VER: + p_dm_odm->fab_version = (u8)value; + break; - case ODM_CMNINFO_RF_ANTENNA_TYPE: - pDM_Odm->AntDivType= (u1Byte)Value; - break; - - case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH: - pDM_Odm->with_extenal_ant_switch = (u1Byte)Value; - break; - - case ODM_CMNINFO_BE_FIX_TX_ANT: - pDM_Odm->DM_FatTable.b_fix_tx_ant = (u1Byte)Value; - break; + case ODM_CMNINFO_RFE_TYPE: + p_dm_odm->rfe_type = (u8)value; + phydm_init_hw_info_by_rfe(p_dm_odm); + break; - case ODM_CMNINFO_BOARD_TYPE: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->BoardType = (u1Byte)Value; - break; + case ODM_CMNINFO_RF_ANTENNA_TYPE: + p_dm_odm->ant_div_type = (u8)value; + break; - case ODM_CMNINFO_PACKAGE_TYPE: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->PackageType = (u1Byte)Value; - break; + case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH: + p_dm_odm->with_extenal_ant_switch = (u8)value; + break; - case ODM_CMNINFO_EXT_LNA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->ExtLNA = (u1Byte)Value; - break; + case ODM_CMNINFO_BE_FIX_TX_ANT: + p_dm_odm->dm_fat_table.b_fix_tx_ant = (u8)value; + break; - case ODM_CMNINFO_5G_EXT_LNA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->ExtLNA5G = (u1Byte)Value; - break; + case ODM_CMNINFO_BOARD_TYPE: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->board_type = (u8)value; + break; - case ODM_CMNINFO_EXT_PA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->ExtPA = (u1Byte)Value; - break; + case ODM_CMNINFO_PACKAGE_TYPE: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->package_type = (u8)value; + break; - case ODM_CMNINFO_5G_EXT_PA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->ExtPA5G = (u1Byte)Value; - break; + case ODM_CMNINFO_EXT_LNA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->ext_lna = (u8)value; + break; - case ODM_CMNINFO_GPA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->TypeGPA = (u2Byte)Value; - break; - - case ODM_CMNINFO_APA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->TypeAPA = (u2Byte)Value; - break; - - case ODM_CMNINFO_GLNA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->TypeGLNA = (u2Byte)Value; - break; - - case ODM_CMNINFO_ALNA: - if (!pDM_Odm->bInitHwInfoByRfe) - pDM_Odm->TypeALNA = (u2Byte)Value; - break; + case ODM_CMNINFO_5G_EXT_LNA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->ext_lna_5g = (u8)value; + break; - case ODM_CMNINFO_EXT_TRSW: - pDM_Odm->ExtTRSW = (u1Byte)Value; - break; - case ODM_CMNINFO_EXT_LNA_GAIN: - pDM_Odm->ExtLNAGain = (u1Byte)Value; - break; - case ODM_CMNINFO_PATCH_ID: - pDM_Odm->PatchID = (u1Byte)Value; - break; - case ODM_CMNINFO_BINHCT_TEST: - pDM_Odm->bInHctTest = (BOOLEAN)Value; - break; - case ODM_CMNINFO_BWIFI_TEST: - pDM_Odm->WIFITest = (u1Byte)Value; - break; - case ODM_CMNINFO_SMART_CONCURRENT: - pDM_Odm->bDualMacSmartConcurrent = (BOOLEAN )Value; - break; - case ODM_CMNINFO_DOMAIN_CODE_2G: - pDM_Odm->odm_Regulation2_4G = (u1Byte)Value; - break; - case ODM_CMNINFO_DOMAIN_CODE_5G: - pDM_Odm->odm_Regulation5G = (u1Byte)Value; - break; - case ODM_CMNINFO_CONFIG_BB_RF: - pDM_Odm->ConfigBBRF = (BOOLEAN)Value; - break; - case ODM_CMNINFO_IQKFWOFFLOAD: - pDM_Odm->IQKFWOffload = (u1Byte)Value; - break; - case ODM_CMNINFO_IQKPAOFF: - pDM_Odm->RFCalibrateInfo.bIQKPAoff = (BOOLEAN )Value; - break; - case ODM_CMNINFO_REGRFKFREEENABLE: - pDM_Odm->RFCalibrateInfo.RegRfKFreeEnable = (u1Byte)Value; - break; - case ODM_CMNINFO_RFKFREEENABLE: - pDM_Odm->RFCalibrateInfo.RfKFreeEnable = (u1Byte)Value; - break; + case ODM_CMNINFO_EXT_PA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->ext_pa = (u8)value; + break; + + case ODM_CMNINFO_5G_EXT_PA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->ext_pa_5g = (u8)value; + break; + + case ODM_CMNINFO_GPA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->type_gpa = (u16)value; + break; + + case ODM_CMNINFO_APA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->type_apa = (u16)value; + break; + + case ODM_CMNINFO_GLNA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->type_glna = (u16)value; + break; + + case ODM_CMNINFO_ALNA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->type_alna = (u16)value; + break; + + case ODM_CMNINFO_EXT_TRSW: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->ext_trsw = (u8)value; + break; + case ODM_CMNINFO_EXT_LNA_GAIN: + p_dm_odm->ext_lna_gain = (u8)value; + break; + case ODM_CMNINFO_PATCH_ID: + p_dm_odm->patch_id = (u8)value; + break; + case ODM_CMNINFO_BINHCT_TEST: + p_dm_odm->is_in_hct_test = (boolean)value; + break; + case ODM_CMNINFO_BWIFI_TEST: + p_dm_odm->wifi_test = (u8)value; + break; + case ODM_CMNINFO_SMART_CONCURRENT: + p_dm_odm->is_dual_mac_smart_concurrent = (boolean)value; + break; + case ODM_CMNINFO_DOMAIN_CODE_2G: + p_dm_odm->odm_regulation_2_4g = (u8)value; + break; + case ODM_CMNINFO_DOMAIN_CODE_5G: + p_dm_odm->odm_regulation_5g = (u8)value; + break; + case ODM_CMNINFO_CONFIG_BB_RF: + p_dm_odm->config_bbrf = (boolean)value; + break; + case ODM_CMNINFO_IQKFWOFFLOAD: + p_dm_odm->iqk_fw_offload = (u8)value; + break; + case ODM_CMNINFO_IQKPAOFF: + p_dm_odm->rf_calibrate_info.is_iqk_pa_off = (boolean)value; + break; + case ODM_CMNINFO_REGRFKFREEENABLE: + p_dm_odm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value; + break; + case ODM_CMNINFO_RFKFREEENABLE: + p_dm_odm->rf_calibrate_info.rf_kfree_enable = (u8)value; + break; + case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE: + p_dm_odm->normal_rx_path = (u8)value; + break; + case ODM_CMNINFO_EFUSE0X3D8: + p_dm_odm->efuse0x3d8 = (u8)value; + break; + case ODM_CMNINFO_EFUSE0X3D7: + p_dm_odm->efuse0x3d7 = (u8)value; + break; + case ODM_CMNINFO_ADVANCE_OTA: + p_dm_odm->p_advance_ota = (u8)value; + break; #ifdef CONFIG_PHYDM_DFS_MASTER - case ODM_CMNINFO_DFS_REGION_DOMAIN: - pDM_Odm->DFS_RegionDomain = (u1Byte)Value; - break; + case ODM_CMNINFO_DFS_REGION_DOMAIN: + p_dm_odm->dfs_region_domain = (u8)value; + break; #endif - //To remove the compiler warning, must add an empty default statement to handle the other values. - default: - //do nothing - break; - + case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING: + p_dm_odm->soft_ap_special_setting = (u32)value; + break; + + case ODM_CMNINFO_DPK_EN: + /*p_dm_odm->dpk_en = (u1Byte)value;*/ + halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_DPK_EN, (u64)value); + break; + + case ODM_CMNINFO_HP_HWID: + p_dm_odm->is_hp_hw_id = (boolean)value; + break; + /* To remove the compiler warning, must add an empty default statement to handle the other values. */ + default: + /* do nothing */ + break; + } } -VOID -ODM_CmnInfoHook( - IN PDM_ODM_T pDM_Odm, - IN ODM_CMNINFO_E CmnInfo, - IN PVOID pValue - ) +void +odm_cmn_info_hook( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_cmninfo_e cmn_info, + void *p_value +) { - // - // Hook call by reference pointer. - // - switch (CmnInfo) - { - // - // Dynamic call by reference pointer. - // - case ODM_CMNINFO_MAC_PHY_MODE: - pDM_Odm->pMacPhyMode = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_TX_UNI: - pDM_Odm->pNumTxBytesUnicast = (u8Byte *)pValue; - break; + /* */ + /* Hook call by reference pointer. */ + /* */ + switch (cmn_info) { + /* */ + /* Dynamic call by reference pointer. */ + /* */ + case ODM_CMNINFO_MAC_PHY_MODE: + p_dm_odm->p_mac_phy_mode = (u8 *)p_value; + break; + + case ODM_CMNINFO_TX_UNI: + p_dm_odm->p_num_tx_bytes_unicast = (u64 *)p_value; + break; + + case ODM_CMNINFO_RX_UNI: + p_dm_odm->p_num_rx_bytes_unicast = (u64 *)p_value; + break; + + case ODM_CMNINFO_WM_MODE: + p_dm_odm->p_wireless_mode = (u8 *)p_value; + break; + + case ODM_CMNINFO_BAND: + p_dm_odm->p_band_type = (u8 *)p_value; + break; + + case ODM_CMNINFO_SEC_CHNL_OFFSET: + p_dm_odm->p_sec_ch_offset = (u8 *)p_value; + break; + + case ODM_CMNINFO_SEC_MODE: + p_dm_odm->p_security = (u8 *)p_value; + break; + + case ODM_CMNINFO_BW: + p_dm_odm->p_band_width = (u8 *)p_value; + break; + + case ODM_CMNINFO_CHNL: + p_dm_odm->p_channel = (u8 *)p_value; + break; + + case ODM_CMNINFO_DMSP_GET_VALUE: + p_dm_odm->p_is_get_value_from_other_mac = (boolean *)p_value; + break; + + case ODM_CMNINFO_BUDDY_ADAPTOR: + p_dm_odm->p_buddy_adapter = (struct _ADAPTER **)p_value; + break; + + case ODM_CMNINFO_DMSP_IS_MASTER: + p_dm_odm->p_is_master_of_dmsp = (boolean *)p_value; + break; + + case ODM_CMNINFO_SCAN: + p_dm_odm->p_is_scan_in_process = (boolean *)p_value; + break; + + case ODM_CMNINFO_POWER_SAVING: + p_dm_odm->p_is_power_saving = (boolean *)p_value; + break; + + case ODM_CMNINFO_ONE_PATH_CCA: + p_dm_odm->p_one_path_cca = (u8 *)p_value; + break; + + case ODM_CMNINFO_DRV_STOP: + p_dm_odm->p_is_driver_stopped = (boolean *)p_value; + break; + + case ODM_CMNINFO_PNP_IN: + p_dm_odm->p_is_driver_is_going_to_pnp_set_power_sleep = (boolean *)p_value; + break; + + case ODM_CMNINFO_INIT_ON: + p_dm_odm->pinit_adpt_in_progress = (boolean *)p_value; + break; + + case ODM_CMNINFO_ANT_TEST: + p_dm_odm->p_antenna_test = (u8 *)p_value; + break; + + case ODM_CMNINFO_NET_CLOSED: + p_dm_odm->p_is_net_closed = (boolean *)p_value; + break; + + case ODM_CMNINFO_FORCED_RATE: + p_dm_odm->p_forced_data_rate = (u16 *)p_value; + break; + case ODM_CMNINFO_ANT_DIV: + p_dm_odm->p_enable_antdiv = (u8 *)p_value; + break; + case ODM_CMNINFO_ADAPTIVITY: + p_dm_odm->p_enable_adaptivity = (u8 *)p_value; + break; + case ODM_CMNINFO_FORCED_IGI_LB: + p_dm_odm->pu1_forced_igi_lb = (u8 *)p_value; + break; + + case ODM_CMNINFO_P2P_LINK: + p_dm_odm->dm_dig_table.is_p2p_in_process = (u8 *)p_value; + break; + + case ODM_CMNINFO_IS1ANTENNA: + p_dm_odm->p_is_1_antenna = (boolean *)p_value; + break; + + case ODM_CMNINFO_RFDEFAULTPATH: + p_dm_odm->p_rf_default_path = (u8 *)p_value; + break; + + case ODM_CMNINFO_FCS_MODE: + p_dm_odm->p_is_fcs_mode_enable = (boolean *)p_value; + break; + /*add by YuChen for beamforming PhyDM*/ + case ODM_CMNINFO_HUBUSBMODE: + p_dm_odm->hub_usb_mode = (u8 *)p_value; + break; + case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS: + p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = (boolean *)p_value; + break; + case ODM_CMNINFO_TX_TP: + p_dm_odm->p_current_tx_tp = (u32 *)p_value; + break; + case ODM_CMNINFO_RX_TP: + p_dm_odm->p_current_rx_tp = (u32 *)p_value; + break; + case ODM_CMNINFO_SOUNDING_SEQ: + p_dm_odm->p_sounding_seq = (u8 *)p_value; + break; +#ifdef CONFIG_PHYDM_DFS_MASTER + case ODM_CMNINFO_DFS_MASTER_ENABLE: + p_dm_odm->dfs_master_enabled = (u8 *)p_value; + break; +#endif + case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC: + p_dm_odm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)p_value; + break; + case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA: + p_dm_odm->dm_fat_table.p_default_s0_s1 = (u8 *)p_value; + break; + case ODM_CMNINFO_SOFT_AP_MODE: + p_dm_odm->p_soft_ap_mode = (u32 *)p_value; + break; + case ODM_CMNINFO_MP_MODE: + p_dm_odm->p_mp_mode = (u8 *)p_value; + break; + default: + /*do nothing*/ + break; + + } + +} +/* + * Update band/CHannel/.. The values are dynamic but non-per-packet. + * */ +void +odm_cmn_info_update( + struct PHY_DM_STRUCT *p_dm_odm, + u32 cmn_info, + u64 value +) +{ + /* */ + /* This init variable may be changed in run time. */ + /* */ + switch (cmn_info) { + case ODM_CMNINFO_LINK_IN_PROGRESS: + p_dm_odm->is_link_in_process = (boolean)value; + break; + + case ODM_CMNINFO_ABILITY: + p_dm_odm->support_ability = (u32)value; + break; + + case ODM_CMNINFO_RF_TYPE: + p_dm_odm->rf_type = (u8)value; + break; + + case ODM_CMNINFO_WIFI_DIRECT: + p_dm_odm->is_wifi_direct = (boolean)value; + break; + + case ODM_CMNINFO_WIFI_DISPLAY: + p_dm_odm->is_wifi_display = (boolean)value; + break; + + case ODM_CMNINFO_LINK: + p_dm_odm->is_linked = (boolean)value; + break; + + case ODM_CMNINFO_CMW500LINK: + p_dm_odm->bLinkedcmw500 = (boolean)value; + break; + + case ODM_CMNINFO_LPSPG: + p_dm_odm->is_in_lps_pg = (boolean)value; + break; + + case ODM_CMNINFO_STATION_STATE: + p_dm_odm->bsta_state = (boolean)value; + break; - case ODM_CMNINFO_RX_UNI: - pDM_Odm->pNumRxBytesUnicast = (u8Byte *)pValue; - break; + case ODM_CMNINFO_RSSI_MIN: + p_dm_odm->rssi_min = (u8)value; + break; - case ODM_CMNINFO_WM_MODE: - pDM_Odm->pWirelessMode = (u1Byte *)pValue; - break; + case ODM_CMNINFO_RSSI_MIN_BY_PATH: + p_dm_odm->rssi_min_by_path = (u8)value; + break; - case ODM_CMNINFO_BAND: - pDM_Odm->pBandType = (u1Byte *)pValue; - break; + case ODM_CMNINFO_DBG_COMP: + p_dm_odm->debug_components = (u32)value; + break; - case ODM_CMNINFO_SEC_CHNL_OFFSET: - pDM_Odm->pSecChOffset = (u1Byte *)pValue; - break; + case ODM_CMNINFO_DBG_LEVEL: + p_dm_odm->debug_level = (u32)value; + break; + case ODM_CMNINFO_RA_THRESHOLD_HIGH: + p_dm_odm->rate_adaptive.high_rssi_thresh = (u8)value; + break; - case ODM_CMNINFO_SEC_MODE: - pDM_Odm->pSecurity = (u1Byte *)pValue; - break; + case ODM_CMNINFO_RA_THRESHOLD_LOW: + p_dm_odm->rate_adaptive.low_rssi_thresh = (u8)value; + break; +#if defined(BT_SUPPORT) && (BT_SUPPORT == 1) + /* The following is for BT HS mode and BT coexist mechanism. */ + case ODM_CMNINFO_BT_ENABLED: + p_dm_odm->is_bt_enabled = (boolean)value; + break; - case ODM_CMNINFO_BW: - pDM_Odm->pBandWidth = (u1Byte *)pValue; - break; + case ODM_CMNINFO_BT_HS_CONNECT_PROCESS: + p_dm_odm->is_bt_connect_process = (boolean)value; + break; - case ODM_CMNINFO_CHNL: - pDM_Odm->pChannel = (u1Byte *)pValue; - break; - - case ODM_CMNINFO_DMSP_GET_VALUE: - pDM_Odm->pbGetValueFromOtherMac = (BOOLEAN *)pValue; - break; + case ODM_CMNINFO_BT_HS_RSSI: + p_dm_odm->bt_hs_rssi = (u8)value; + break; - case ODM_CMNINFO_BUDDY_ADAPTOR: - pDM_Odm->pBuddyAdapter = (PADAPTER *)pValue; - break; + case ODM_CMNINFO_BT_OPERATION: + p_dm_odm->is_bt_hs_operation = (boolean)value; + break; - case ODM_CMNINFO_DMSP_IS_MASTER: - pDM_Odm->pbMasterOfDMSP = (BOOLEAN *)pValue; - break; + case ODM_CMNINFO_BT_LIMITED_DIG: + p_dm_odm->is_bt_limited_dig = (boolean)value; + break; - case ODM_CMNINFO_SCAN: - pDM_Odm->pbScanInProcess = (BOOLEAN *)pValue; - break; + case ODM_CMNINFO_BT_DIG: + p_dm_odm->bt_hs_dig_val = (u8)value; + break; - case ODM_CMNINFO_POWER_SAVING: - pDM_Odm->pbPowerSaving = (BOOLEAN *)pValue; - break; + case ODM_CMNINFO_BT_BUSY: + p_dm_odm->is_bt_busy = (boolean)value; + break; - case ODM_CMNINFO_ONE_PATH_CCA: - pDM_Odm->pOnePathCCA = (u1Byte *)pValue; - break; + case ODM_CMNINFO_BT_DISABLE_EDCA: + p_dm_odm->is_bt_disable_edca_turbo = (boolean)value; + break; +#endif - case ODM_CMNINFO_DRV_STOP: - pDM_Odm->pbDriverStopped = (BOOLEAN *)pValue; - break; + case ODM_CMNINFO_AP_TOTAL_NUM: + p_dm_odm->ap_total_num = (u8)value; + break; - case ODM_CMNINFO_PNP_IN: - pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (BOOLEAN *)pValue; - break; + case ODM_CMNINFO_POWER_TRAINING: + p_dm_odm->is_disable_power_training = (boolean)value; + break; - case ODM_CMNINFO_INIT_ON: - pDM_Odm->pinit_adpt_in_progress = (BOOLEAN *)pValue; - break; +#ifdef CONFIG_PHYDM_DFS_MASTER + case ODM_CMNINFO_DFS_REGION_DOMAIN: + p_dm_odm->dfs_region_domain = (u8)value; + break; +#endif - case ODM_CMNINFO_ANT_TEST: - pDM_Odm->pAntennaTest = (u1Byte *)pValue; - break; +#if 0 + case ODM_CMNINFO_OP_MODE: + p_dm_odm->op_mode = (u8)value; + break; - case ODM_CMNINFO_NET_CLOSED: - pDM_Odm->pbNet_closed = (BOOLEAN *)pValue; - break; + case ODM_CMNINFO_WM_MODE: + p_dm_odm->wireless_mode = (u8)value; + break; - case ODM_CMNINFO_FORCED_RATE: - pDM_Odm->pForcedDataRate = (pu2Byte)pValue; - break; + case ODM_CMNINFO_BAND: + p_dm_odm->band_type = (u8)value; + break; - case ODM_CMNINFO_FORCED_IGI_LB: - pDM_Odm->pu1ForcedIgiLb = (u1Byte *)pValue; - break; + case ODM_CMNINFO_SEC_CHNL_OFFSET: + p_dm_odm->sec_ch_offset = (u8)value; + break; - case ODM_CMNINFO_P2P_LINK: - pDM_Odm->DM_DigTable.bP2PInProcess = (u1Byte *)pValue; - break; + case ODM_CMNINFO_SEC_MODE: + p_dm_odm->security = (u8)value; + break; - case ODM_CMNINFO_IS1ANTENNA: - pDM_Odm->pIs1Antenna = (BOOLEAN *)pValue; - break; - - case ODM_CMNINFO_RFDEFAULTPATH: - pDM_Odm->pRFDefaultPath= (u1Byte *)pValue; - break; + case ODM_CMNINFO_BW: + p_dm_odm->band_width = (u8)value; + break; - case ODM_CMNINFO_FCS_MODE: - pDM_Odm->pIsFcsModeEnable = (BOOLEAN *)pValue; - break; - /*add by YuChen for beamforming PhyDM*/ - case ODM_CMNINFO_HUBUSBMODE: - pDM_Odm->HubUsbMode = (u1Byte *)pValue; - break; - case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS: - pDM_Odm->pbFwDwRsvdPageInProgress = (BOOLEAN *)pValue; - break; - case ODM_CMNINFO_TX_TP: - pDM_Odm->pCurrentTxTP = (u4Byte *)pValue; - break; - case ODM_CMNINFO_RX_TP: - pDM_Odm->pCurrentRxTP = (u4Byte *)pValue; - break; - case ODM_CMNINFO_SOUNDING_SEQ: - pDM_Odm->pSoundingSeq = (u1Byte *)pValue; - break; -#ifdef CONFIG_PHYDM_DFS_MASTER - case ODM_CMNINFO_DFS_MASTER_ENABLE: - pDM_Odm->dfs_master_enabled = (u1Byte *)pValue; - break; + case ODM_CMNINFO_CHNL: + p_dm_odm->channel = (u8)value; + break; #endif - case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC: - pDM_Odm->DM_FatTable.pForceTxAntByDesc = (u1Byte *)pValue; - break; - //case ODM_CMNINFO_RTSTA_AID: - // pDM_Odm->pAidMap = (u1Byte *)pValue; - // break; - - //case ODM_CMNINFO_BT_COEXIST: - // pDM_Odm->BTCoexist = (BOOLEAN *)pValue; - - //case ODM_CMNINFO_STA_STATUS: - //pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue; - //break; - - //case ODM_CMNINFO_PHY_STATUS: - // pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue; - // break; - - //case ODM_CMNINFO_MAC_STATUS: - // pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue; - // break; - //To remove the compiler warning, must add an empty default statement to handle the other values. - default: - //do nothing - break; - + default: + /* do nothing */ + break; } -} - -VOID -ODM_CmnInfoPtrArrayHook( - IN PDM_ODM_T pDM_Odm, - IN ODM_CMNINFO_E CmnInfo, - IN u2Byte Index, - IN PVOID pValue - ) -{ - // - // Hook call by reference pointer. - // - switch (CmnInfo) - { - // - // Dynamic call by reference pointer. - // - case ODM_CMNINFO_STA_STATUS: - pDM_Odm->pODM_StaInfo[Index] = (PSTA_INFO_T)pValue; - - if (IS_STA_VALID(pDM_Odm->pODM_StaInfo[Index])) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->AssociatedMacId] = Index; /*AssociatedMacId are unique bttween different Adapter*/ - #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->aid] = Index; - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->mac_id] = Index; - #endif - - break; - //To remove the compiler warning, must add an empty default statement to handle the other values. - default: - //do nothing - break; - } - } - -// -// Update Band/CHannel/.. The values are dynamic but non-per-packet. -// -VOID -ODM_CmnInfoUpdate( - IN PDM_ODM_T pDM_Odm, - IN u4Byte CmnInfo, - IN u8Byte Value - ) +u32 +phydm_cmn_info_query( + struct PHY_DM_STRUCT *p_dm_odm, + enum phydm_info_query_e info_type +) { - // - // This init variable may be changed in run time. - // - switch (CmnInfo) - { - case ODM_CMNINFO_LINK_IN_PROGRESS: - pDM_Odm->bLinkInProcess = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_ABILITY: - pDM_Odm->SupportAbility = (u4Byte)Value; - break; - - case ODM_CMNINFO_RF_TYPE: - pDM_Odm->RFType = (u1Byte)Value; - break; - - case ODM_CMNINFO_WIFI_DIRECT: - pDM_Odm->bWIFI_Direct = (BOOLEAN)Value; - break; + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - case ODM_CMNINFO_WIFI_DISPLAY: - pDM_Odm->bWIFI_Display = (BOOLEAN)Value; - break; + switch (info_type) { + case PHYDM_INFO_FA_OFDM: + return false_alm_cnt->cnt_ofdm_fail; - case ODM_CMNINFO_LINK: - pDM_Odm->bLinked = (BOOLEAN)Value; - break; + case PHYDM_INFO_FA_CCK: + return false_alm_cnt->cnt_cck_fail; - case ODM_CMNINFO_STATION_STATE: - pDM_Odm->bsta_state = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_RSSI_MIN: - pDM_Odm->RSSI_Min= (u1Byte)Value; - break; + case PHYDM_INFO_FA_TOTAL: + return false_alm_cnt->cnt_all; - case ODM_CMNINFO_DBG_COMP: - pDM_Odm->DebugComponents = (u4Byte)Value; - break; + case PHYDM_INFO_CCA_OFDM: + return false_alm_cnt->cnt_ofdm_cca; - case ODM_CMNINFO_DBG_LEVEL: - pDM_Odm->DebugLevel = (u4Byte)Value; - break; - case ODM_CMNINFO_RA_THRESHOLD_HIGH: - pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value; - break; + case PHYDM_INFO_CCA_CCK: + return false_alm_cnt->cnt_cck_cca; - case ODM_CMNINFO_RA_THRESHOLD_LOW: - pDM_Odm->RateAdaptive.LowRSSIThresh = (u1Byte)Value; - break; -#if defined(BT_SUPPORT) && (BT_SUPPORT == 1) - // The following is for BT HS mode and BT coexist mechanism. - case ODM_CMNINFO_BT_ENABLED: - pDM_Odm->bBtEnabled = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_BT_HS_CONNECT_PROCESS: - pDM_Odm->bBtConnectProcess = (BOOLEAN)Value; - break; - - case ODM_CMNINFO_BT_HS_RSSI: - pDM_Odm->btHsRssi = (u1Byte)Value; - break; - - case ODM_CMNINFO_BT_OPERATION: - pDM_Odm->bBtHsOperation = (BOOLEAN)Value; - break; + case PHYDM_INFO_CCA_ALL: + return false_alm_cnt->cnt_cca_all; - case ODM_CMNINFO_BT_LIMITED_DIG: - pDM_Odm->bBtLimitedDig = (BOOLEAN)Value; - break; + case PHYDM_INFO_CRC32_OK_VHT: + return false_alm_cnt->cnt_vht_crc32_ok; - case ODM_CMNINFO_BT_DIG: - pDM_Odm->btHsDigVal = (u1Byte)Value; - break; - - case ODM_CMNINFO_BT_BUSY: - pDM_Odm->bBtBusy = (BOOLEAN)Value; - break; + case PHYDM_INFO_CRC32_OK_HT: + return false_alm_cnt->cnt_ht_crc32_ok; - case ODM_CMNINFO_BT_DISABLE_EDCA: - pDM_Odm->bBtDisableEdcaTurbo = (BOOLEAN)Value; - break; -#endif + case PHYDM_INFO_CRC32_OK_LEGACY: + return false_alm_cnt->cnt_ofdm_crc32_ok; -#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 -#ifdef UNIVERSAL_REPEATER - case ODM_CMNINFO_VXD_LINK: - pDM_Odm->VXD_bLinked= (BOOLEAN)Value; - break; -#endif -#endif + case PHYDM_INFO_CRC32_OK_CCK: + return false_alm_cnt->cnt_cck_crc32_ok; - case ODM_CMNINFO_AP_TOTAL_NUM: - pDM_Odm->APTotalNum = (u1Byte)Value; - break; + case PHYDM_INFO_CRC32_ERROR_VHT: + return false_alm_cnt->cnt_vht_crc32_error; - case ODM_CMNINFO_POWER_TRAINING: - pDM_Odm->bDisablePowerTraining = (BOOLEAN)Value; - break; + case PHYDM_INFO_CRC32_ERROR_HT: + return false_alm_cnt->cnt_ht_crc32_error; -#ifdef CONFIG_PHYDM_DFS_MASTER - case ODM_CMNINFO_DFS_REGION_DOMAIN: - pDM_Odm->DFS_RegionDomain = (u1Byte)Value; - break; -#endif + case PHYDM_INFO_CRC32_ERROR_LEGACY: + return false_alm_cnt->cnt_ofdm_crc32_error; -/* - case ODM_CMNINFO_OP_MODE: - pDM_Odm->OPMode = (u1Byte)Value; - break; + case PHYDM_INFO_CRC32_ERROR_CCK: + return false_alm_cnt->cnt_cck_crc32_error; - case ODM_CMNINFO_WM_MODE: - pDM_Odm->WirelessMode = (u1Byte)Value; - break; + case PHYDM_INFO_EDCCA_FLAG: + return false_alm_cnt->edcca_flag; - case ODM_CMNINFO_BAND: - pDM_Odm->BandType = (u1Byte)Value; - break; + case PHYDM_INFO_OFDM_ENABLE: + return false_alm_cnt->ofdm_block_enable; - case ODM_CMNINFO_SEC_CHNL_OFFSET: - pDM_Odm->SecChOffset = (u1Byte)Value; - break; + case PHYDM_INFO_CCK_ENABLE: + return false_alm_cnt->cck_block_enable; - case ODM_CMNINFO_SEC_MODE: - pDM_Odm->Security = (u1Byte)Value; - break; + case PHYDM_INFO_DBG_PORT_0: + return false_alm_cnt->dbg_port0; + + case PHYDM_INFO_CRC32_OK_HT_AGG: + return false_alm_cnt->cnt_ht_crc32_ok_agg; + + case PHYDM_INFO_CRC32_ERROR_HT_AGG: + return false_alm_cnt->cnt_ht_crc32_error_agg; + - case ODM_CMNINFO_BW: - pDM_Odm->BandWidth = (u1Byte)Value; - break; + default: + return 0xffffffff; - case ODM_CMNINFO_CHNL: - pDM_Odm->Channel = (u1Byte)Value; - break; -*/ - default: - //do nothing - break; } - - } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ) +void +odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm) { - PADAPTER pAdapter = pDM_Odm->Adapter; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; #if USE_WORKITEM - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - ODM_InitializeWorkItem( pDM_Odm, - &pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchWorkitem, - (RT_WORKITEM_CALL_BACK)ODM_SW_AntDiv_WorkitemCallback, - (PVOID)pAdapter, - "AntennaSwitchWorkitem"); - #endif - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - ODM_InitializeWorkItem(pDM_Odm, - &pDM_Odm->dm_sat_table.hl_smart_antenna_workitem, - (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback, - (PVOID)pAdapter, - "hl_smart_ant_workitem"); - - ODM_InitializeWorkItem(pDM_Odm, - &pDM_Odm->dm_sat_table.hl_smart_antenna_decision_workitem, - (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback, - (PVOID)pAdapter, - "hl_smart_ant_decision_workitem"); - #endif - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->PathDivSwitchWorkitem), - (RT_WORKITEM_CALL_BACK)odm_PathDivChkAntSwitchWorkitemCallback, - (PVOID)pAdapter, + +#if CONFIG_DYNAMIC_RX_PATH + odm_initialize_work_item(p_dm_odm, + &p_dm_odm->dm_drp_table.phydm_dynamic_rx_path_workitem, + (RT_WORKITEM_CALL_BACK)phydm_dynamic_rx_path_workitem_callback, + (void *)p_adapter, + "DynamicRxPathWorkitem"); + +#endif +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_initialize_work_item(p_dm_odm, + &p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_workitem, + (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback, + (void *)p_adapter, + "AntennaSwitchWorkitem"); +#endif +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) + odm_initialize_work_item(p_dm_odm, + &p_dm_odm->dm_sat_table.hl_smart_antenna_workitem, + (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback, + (void *)p_adapter, + "hl_smart_ant_workitem"); + + odm_initialize_work_item(p_dm_odm, + &p_dm_odm->dm_sat_table.hl_smart_antenna_decision_workitem, + (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback, + (void *)p_adapter, + "hl_smart_ant_decision_workitem"); +#endif + + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->path_div_switch_workitem), + (RT_WORKITEM_CALL_BACK)odm_path_div_chk_ant_switch_workitem_callback, + (void *)p_adapter, "SWAS_WorkItem"); - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->CCKPathDiversityWorkitem), - (RT_WORKITEM_CALL_BACK)odm_CCKTXPathDiversityWorkItemCallback, - (PVOID)pAdapter, + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->cck_path_diversity_workitem), + (RT_WORKITEM_CALL_BACK)odm_cck_tx_path_diversity_work_item_callback, + (void *)p_adapter, "CCKTXPathDiversityWorkItem"); - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->MPT_DIGWorkitem), - (RT_WORKITEM_CALL_BACK)odm_MPT_DIGWorkItemCallback, - (PVOID)pAdapter, - "MPT_DIGWorkitem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->RaRptWorkitem), - (RT_WORKITEM_CALL_BACK)ODM_UpdateInitRateWorkItemCallback, - (PVOID)pAdapter, - "RaRptWorkitem"); - -#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->FastAntTrainingWorkitem), - (RT_WORKITEM_CALL_BACK)odm_FastAntTrainingWorkItemCallback, - (PVOID)pAdapter, - "FastAntTrainingWorkitem"); + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->mpt_dig_workitem), + (RT_WORKITEM_CALL_BACK)odm_mpt_dig_work_item_callback, + (void *)p_adapter, + "mpt_dig_workitem"); + + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->ra_rpt_workitem), + (RT_WORKITEM_CALL_BACK)odm_update_init_rate_work_item_callback, + (void *)p_adapter, + "ra_rpt_workitem"); + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->fast_ant_training_workitem), + (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback, + (void *)p_adapter, + "fast_ant_training_workitem"); #endif #endif /*#if USE_WORKITEM*/ #if (BEAMFORMING_SUPPORT == 1) - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_EnterWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_EnterWorkItemCallback, - (PVOID)pAdapter, - "Txbf_EnterWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_LeaveWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_LeaveWorkItemCallback, - (PVOID)pAdapter, - "Txbf_LeaveWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_FwNdpaWorkItemCallback, - (PVOID)pAdapter, - "Txbf_FwNdpaWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ClkWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_ClkWorkItemCallback, - (PVOID)pAdapter, - "Txbf_ClkWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_RateWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_RateWorkItemCallback, - (PVOID)pAdapter, - "Txbf_RateWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_StatusWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_StatusWorkItemCallback, - (PVOID)pAdapter, - "Txbf_StatusWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ResetTxPathWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_ResetTxPathWorkItemCallback, - (PVOID)pAdapter, - "Txbf_ResetTxPathWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_GetTxRateWorkItem), - (RT_WORKITEM_CALL_BACK)halComTxbf_GetTxRateWorkItemCallback, - (PVOID)pAdapter, - "Txbf_GetTxRateWorkItem"); -#endif - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->Adaptivity.phydm_pauseEDCCAWorkItem), - (RT_WORKITEM_CALL_BACK)phydm_pauseEDCCA_WorkItemCallback, - (PVOID)pAdapter, - "phydm_pauseEDCCAWorkItem"); - - ODM_InitializeWorkItem( - pDM_Odm, - &(pDM_Odm->Adaptivity.phydm_resumeEDCCAWorkItem), - (RT_WORKITEM_CALL_BACK)phydm_resumeEDCCA_WorkItemCallback, - (PVOID)pAdapter, - "phydm_resumeEDCCAWorkItem"); - -} - -VOID -ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ) + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->beamforming_info.txbf_info.txbf_enter_work_item), + (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback, + (void *)p_adapter, + "txbf_enter_work_item"); + + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->beamforming_info.txbf_info.txbf_leave_work_item), + (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback, + (void *)p_adapter, + "txbf_leave_work_item"); + + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item), + (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback, + (void *)p_adapter, + "txbf_fw_ndpa_work_item"); + + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->beamforming_info.txbf_info.txbf_clk_work_item), + (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback, + (void *)p_adapter, + "txbf_clk_work_item"); + + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->beamforming_info.txbf_info.txbf_rate_work_item), + (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback, + (void *)p_adapter, + "txbf_rate_work_item"); + + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->beamforming_info.txbf_info.txbf_status_work_item), + (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback, + (void *)p_adapter, + "txbf_status_work_item"); + + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item), + (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback, + (void *)p_adapter, + "txbf_reset_tx_path_work_item"); + + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item), + (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback, + (void *)p_adapter, + "txbf_get_tx_rate_work_item"); +#endif + + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->adaptivity.phydm_pause_edcca_work_item), + (RT_WORKITEM_CALL_BACK)phydm_pause_edcca_work_item_callback, + (void *)p_adapter, + "phydm_pause_edcca_work_item"); + + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->adaptivity.phydm_resume_edcca_work_item), + (RT_WORKITEM_CALL_BACK)phydm_resume_edcca_work_item_callback, + (void *)p_adapter, + "phydm_resume_edcca_work_item"); + +#if (PHYDM_LA_MODE_SUPPORT == 1) + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->adcsmp.adc_smp_work_item), + (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback, + (void *)p_adapter, + "adc_smp_work_item"); + + odm_initialize_work_item( + p_dm_odm, + &(p_dm_odm->adcsmp.adc_smp_work_item_1), + (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback, + (void *)p_adapter, + "adc_smp_work_item_1"); +#endif + +} + +void +odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm_odm) { #if USE_WORKITEM #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - ODM_FreeWorkItem(&(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchWorkitem)); + odm_free_work_item(&(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_workitem)); +#endif + +#if CONFIG_DYNAMIC_RX_PATH + odm_free_work_item(&(p_dm_odm->dm_drp_table.phydm_dynamic_rx_path_workitem)); #endif -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - ODM_FreeWorkItem(&(pDM_Odm->dm_sat_table.hl_smart_antenna_workitem)); - ODM_FreeWorkItem(&(pDM_Odm->dm_sat_table.hl_smart_antenna_decision_workitem)); + + +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) + odm_free_work_item(&(p_dm_odm->dm_sat_table.hl_smart_antenna_workitem)); + odm_free_work_item(&(p_dm_odm->dm_sat_table.hl_smart_antenna_decision_workitem)); #endif - ODM_FreeWorkItem(&(pDM_Odm->PathDivSwitchWorkitem)); - ODM_FreeWorkItem(&(pDM_Odm->CCKPathDiversityWorkitem)); + odm_free_work_item(&(p_dm_odm->path_div_switch_workitem)); + odm_free_work_item(&(p_dm_odm->cck_path_diversity_workitem)); #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - ODM_FreeWorkItem(&(pDM_Odm->FastAntTrainingWorkitem)); + odm_free_work_item(&(p_dm_odm->fast_ant_training_workitem)); #endif - ODM_FreeWorkItem(&(pDM_Odm->MPT_DIGWorkitem)); - ODM_FreeWorkItem(&(pDM_Odm->RaRptWorkitem)); - /*ODM_FreeWorkItem((&pDM_Odm->sbdcnt_workitem));*/ + odm_free_work_item(&(p_dm_odm->mpt_dig_workitem)); + odm_free_work_item(&(p_dm_odm->ra_rpt_workitem)); + /*odm_free_work_item((&p_dm_odm->sbdcnt_workitem));*/ #endif #if (BEAMFORMING_SUPPORT == 1) - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_EnterWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_LeaveWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ClkWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_RateWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_StatusWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ResetTxPathWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_GetTxRateWorkItem)); + odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_enter_work_item)); + odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_leave_work_item)); + odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item)); + odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_clk_work_item)); + odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_rate_work_item)); + odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_status_work_item)); + odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item)); + odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item)); #endif - ODM_FreeWorkItem((&pDM_Odm->Adaptivity.phydm_pauseEDCCAWorkItem)); - ODM_FreeWorkItem((&pDM_Odm->Adaptivity.phydm_resumeEDCCAWorkItem)); + odm_free_work_item((&p_dm_odm->adaptivity.phydm_pause_edcca_work_item)); + odm_free_work_item((&p_dm_odm->adaptivity.phydm_resume_edcca_work_item)); + +#if (PHYDM_LA_MODE_SUPPORT == 1) + odm_free_work_item((&p_dm_odm->adcsmp.adc_smp_work_item)); + odm_free_work_item((&p_dm_odm->adcsmp.adc_smp_work_item_1)); +#endif } #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ -/* -VOID +#if 0 +void odm_FindMinimumRSSI( - IN PDM_ODM_T pDM_Odm - ) + struct PHY_DM_STRUCT *p_dm_odm +) { - u4Byte i; - u1Byte RSSI_Min = 0xFF; - - for(i=0; ipODM_StaInfo[i] != NULL) - if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) ) - { - if(pDM_Odm->pODM_StaInfo[i]->RSSI_Ave < RSSI_Min) - { - RSSI_Min = pDM_Odm->pODM_StaInfo[i]->RSSI_Ave; - } + u32 i; + u8 rssi_min = 0xFF; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + /* if(p_dm_odm->p_odm_sta_info[i] != NULL) */ + if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[i])) { + if (p_dm_odm->p_odm_sta_info[i]->rssi_ave < rssi_min) + rssi_min = p_dm_odm->p_odm_sta_info[i]->rssi_ave; } } - pDM_Odm->RSSI_Min = RSSI_Min; + p_dm_odm->rssi_min = rssi_min; } -VOID +void odm_IsLinked( - IN PDM_ODM_T pDM_Odm - ) + struct PHY_DM_STRUCT *p_dm_odm +) { - u4Byte i; - BOOLEAN Linked = FALSE; - - for(i=0; ipODM_StaInfo[i]) ) - { - Linked = TRUE; - break; - } - + u32 i; + boolean Linked = false; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[i])) { + Linked = true; + break; + } + } - pDM_Odm->bLinked = Linked; + p_dm_odm->is_linked = Linked; } -*/ +#endif -VOID -ODM_InitAllTimers( - IN PDM_ODM_T pDM_Odm - ) +void +odm_init_all_timers( + struct PHY_DM_STRUCT *p_dm_odm +) { #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_AntDivTimers(pDM_Odm,INIT_ANTDIV_TIMMER); + odm_ant_div_timers(p_dm_odm, INIT_ANTDIV_TIMMER); +#endif + +#if (CONFIG_DYNAMIC_RX_PATH == 1) + phydm_dynamic_rx_path_timers(p_dm_odm, INIT_DRP_TIMMER); #endif #if (DM_ODM_SUPPORT_TYPE == ODM_AP) #ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, - (RT_TIMER_CALL_BACK)odm_MPT_DIGCallback, NULL, "MPT_DIGTimer"); + if (*(p_dm_odm->p_mp_mode)) + odm_initialize_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer, + (void *)odm_mpt_dig_callback, NULL, "mpt_dig_timer"); #endif -#elif(DM_ODM_SUPPORT_TYPE == ODM_WIN) - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, - (RT_TIMER_CALL_BACK)odm_MPT_DIGCallback, NULL, "MPT_DIGTimer"); +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + odm_initialize_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer, + (void *)odm_mpt_dig_callback, NULL, "mpt_dig_timer"); #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer, - (RT_TIMER_CALL_BACK)odm_PathDivChkAntSwitchCallback, NULL, "PathDivTimer"); - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, - (RT_TIMER_CALL_BACK)odm_CCKTXPathDiversityCallback, NULL, "CCKPathDiversityTimer"); - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer, - (RT_TIMER_CALL_BACK)phydm_sbd_callback, NULL, "SbdTimer"); + odm_initialize_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer, + (void *)odm_path_div_chk_ant_switch_callback, NULL, "PathDivTimer"); + odm_initialize_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer, + (void *)odm_cck_tx_path_diversity_callback, NULL, "cck_path_diversity_timer"); + odm_initialize_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer, + (void *)phydm_sbd_callback, NULL, "SbdTimer"); #if (BEAMFORMING_SUPPORT == 1) - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer, - (RT_TIMER_CALL_BACK)halComTxbf_FwNdpaTimerCallback, NULL, "Txbf_FwNdpaTimer"); + odm_initialize_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer, + (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL, "txbf_fw_ndpa_timer"); #endif #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (BEAMFORMING_SUPPORT == 1) - ODM_InitializeTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer, - (RT_TIMER_CALL_BACK)Beamforming_SWTimerCallback, NULL, "BeamformingTimer"); + odm_initialize_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer, + (void *)beamforming_sw_timer_callback, NULL, "beamforming_timer"); #endif #endif } -VOID -ODM_CancelAllTimers( - IN PDM_ODM_T pDM_Odm - ) +void +odm_cancel_all_timers( + struct PHY_DM_STRUCT *p_dm_odm +) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - // - // 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in - // win7 platform. - // - HAL_ADAPTER_STS_CHK(pDM_Odm) -#endif + /* */ + /* 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in */ + /* win7 platform. */ + /* */ + HAL_ADAPTER_STS_CHK(p_dm_odm); +#endif #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_AntDivTimers(pDM_Odm,CANCEL_ANTDIV_TIMMER); + odm_ant_div_timers(p_dm_odm, CANCEL_ANTDIV_TIMMER); +#endif + +#if (CONFIG_DYNAMIC_RX_PATH == 1) + phydm_dynamic_rx_path_timers(p_dm_odm, CANCEL_DRP_TIMMER); #endif #if (DM_ODM_SUPPORT_TYPE == ODM_AP) #ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); + if (*(p_dm_odm->p_mp_mode)) + odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); #endif #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); + odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - ODM_CancelTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer); - ODM_CancelTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer); - ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); - ODM_CancelTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer); + odm_cancel_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer); + odm_cancel_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer); + odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); + odm_cancel_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer); #if (BEAMFORMING_SUPPORT == 1) - ODM_CancelTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer); + odm_cancel_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer); #endif #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (BEAMFORMING_SUPPORT == 1) - ODM_CancelTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer); + odm_cancel_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer); #endif #endif } -VOID -ODM_ReleaseAllTimers( - IN PDM_ODM_T pDM_Odm - ) +void +odm_release_all_timers( + struct PHY_DM_STRUCT *p_dm_odm +) { #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_AntDivTimers(pDM_Odm,RELEASE_ANTDIV_TIMMER); + odm_ant_div_timers(p_dm_odm, RELEASE_ANTDIV_TIMMER); +#endif + +#if (CONFIG_DYNAMIC_RX_PATH == 1) + phydm_dynamic_rx_path_timers(p_dm_odm, RELEASE_DRP_TIMMER); #endif #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - #ifdef MP_TEST - if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); - #endif -#elif(DM_ODM_SUPPORT_TYPE == ODM_WIN) -ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); +#ifdef MP_TEST + if (*(p_dm_odm->p_mp_mode)) + odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); +#endif +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer); - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer); - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer); + odm_release_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer); + odm_release_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer); + odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); + odm_release_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer); #if (BEAMFORMING_SUPPORT == 1) - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer); + odm_release_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer); #endif #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (BEAMFORMING_SUPPORT == 1) - ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer); + odm_release_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer); #endif #endif } -//3============================================================ -//3 Tx Power Tracking -//3============================================================ +/* 3============================================================ + * 3 Tx Power Tracking + * 3============================================================ */ #if (DM_ODM_SUPPORT_TYPE == ODM_AP) -VOID -ODM_InitAllThreads( - IN PDM_ODM_T pDM_Odm - ) +void +odm_init_all_threads( + struct PHY_DM_STRUCT *p_dm_odm +) { - #ifdef TPT_THREAD - kTPT_task_init(pDM_Odm->priv); - #endif +#ifdef TPT_THREAD + k_tpt_task_init(p_dm_odm->priv); +#endif } -VOID -ODM_StopAllThreads( - IN PDM_ODM_T pDM_Odm - ) +void +odm_stop_all_threads( + struct PHY_DM_STRUCT *p_dm_odm +) { - #ifdef TPT_THREAD - kTPT_task_stop(pDM_Odm->priv); - #endif +#ifdef TPT_THREAD + k_tpt_task_stop(p_dm_odm->priv); +#endif } -#endif +#endif -#if( DM_ODM_SUPPORT_TYPE == ODM_WIN) -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +/* + * 2011/07/26 MH Add an API for testing IQK fail case. + * */ +boolean +odm_check_power_status( + struct _ADAPTER *adapter) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + RT_RF_POWER_STATE rt_state; + PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter\n")); - return TRUE; + /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */ + if (p_mgnt_info->init_adpt_in_progress == true) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("odm_check_power_status Return true, due to initadapter\n")); + return true; } - - // - // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; + + /* */ + /* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */ + /* */ + adapter->HalFunc.GetHwRegHandler(adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state)); + if (adapter->bDriverStopped || adapter->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n", + adapter->bDriverStopped, adapter->bDriverIsGoingToPnpSetPowerSleep, rt_state)); + return false; } - return TRUE; + return true; } -#elif( DM_ODM_SUPPORT_TYPE == ODM_AP) -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter) +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) +boolean +odm_check_power_status( + struct _ADAPTER *adapter) { - /* - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_RF_POWER_STATE rtState; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - - // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. - if (pMgntInfo->init_adpt_in_progress == TRUE) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); - return TRUE; +#if 0 + /* HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); */ + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + RT_RF_POWER_STATE rt_state; + PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); + + /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */ + if (p_mgnt_info->init_adpt_in_progress == true) { + ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return true, due to initadapter")); + return true; } - // - // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. - // - Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); - if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) - { - ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", - Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); - return FALSE; + /* */ + /* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */ + /* */ + phydm_get_hw_reg_interface(p_dm_odm, HW_VAR_RF_STATE, (u8 *)(&rt_state)); + if (adapter->is_driver_stopped || adapter->is_driver_is_going_to_pnp_set_power_sleep || rt_state == eRfOff) { + ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n", + adapter->is_driver_stopped, adapter->is_driver_is_going_to_pnp_set_power_sleep, rt_state)); + return false; } - */ - return TRUE; -} -#endif - -// need to ODM CE Platform -//move to here for ANT detection mechanism using - -#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN)||(DM_ODM_SUPPORT_TYPE == ODM_CE)) -u4Byte -GetPSDData( - IN PDM_ODM_T pDM_Odm, - unsigned int point, - u1Byte initial_gain_psd) -{ - //unsigned int val, rfval; - //int psd_report; - u4Byte psd_report; - - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //Debug Message - //val = PHY_QueryBBReg(Adapter,0x908, bMaskDWord); - //DbgPrint("Reg908 = 0x%x\n",val); - //val = PHY_QueryBBReg(Adapter,0xDF4, bMaskDWord); - //rfval = PHY_QueryRFReg(Adapter, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask); - //DbgPrint("RegDF4 = 0x%x, RFReg00 = 0x%x\n",val, rfval); - //DbgPrint("PHYTXON = %x, OFDMCCA_PP = %x, CCKCCA_PP = %x, RFReg00 = %x\n", - //(val&BIT25)>>25, (val&BIT14)>>14, (val&BIT15)>>15, rfval); - - //Set DCO frequency index, offset=(40MHz/SamplePts)*point - ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); - - //Start PSD calculation, Reg808[22]=0->1 - ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); - //Need to wait for HW PSD report - ODM_StallExecution(1000); - ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0); - //Read PSD report, Reg8B4[15:0] - psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF; - -#if 1//(DEV_BUS_TYPE == RT_PCI_INTERFACE) && ( (RT_PLATFORM == PLATFORM_LINUX) || (RT_PLATFORM == PLATFORM_MACOSX)) - psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report))+(u4Byte)(initial_gain_psd-0x1c); -#else - psd_report = (int) (20*log10((double)psd_report))+(int)(initial_gain_psd-0x1c); #endif - - return psd_report; - + return true; } #endif -u4Byte -odm_ConvertTo_dB( - u4Byte Value) +/* need to ODM CE Platform + * move to here for ANT detection mechanism using */ + +u32 +odm_convert_to_db( + u32 value) { - u1Byte i; - u1Byte j; - u4Byte dB; + u8 i; + u8 j; + u32 dB; - Value = Value & 0xFFFF; + value = value & 0xFFFF; - for (i = 0; i < 12; i++) - { - if (Value <= dB_Invert_Table[i][7]) - { + for (i = 0; i < 12; i++) { + if (value <= db_invert_table[i][7]) break; - } } - if (i >= 12) - { - return (96); // maximum 96 dB + if (i >= 12) { + return 96; /* maximum 96 dB */ } - for (j = 0; j < 8; j++) - { - if (Value <= dB_Invert_Table[i][j]) - { + for (j = 0; j < 8; j++) { + if (value <= db_invert_table[i][j]) break; - } } dB = (i << 3) + j + 1; - return (dB); + return dB; } -u4Byte -odm_ConvertTo_linear( - u4Byte Value) +u32 +odm_convert_to_linear( + u32 value) { - u1Byte i; - u1Byte j; - u4Byte linear; - - /* 1dB~96dB */ - - Value = Value & 0xFF; - - i = (u1Byte)((Value - 1) >> 3); - j = (u1Byte)(Value - 1) - (i << 3); + u8 i; + u8 j; + u32 linear; - linear = dB_Invert_Table[i][j]; + /* 1dB~96dB */ - return (linear); -} + value = value & 0xFF; -// -// ODM multi-port consideration, added by Roger, 2013.10.01. -// -VOID -ODM_AsocEntry_Init( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER pLoopAdapter = GetDefaultAdapter(pDM_Odm->Adapter); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pLoopAdapter); - PDM_ODM_T pDM_OutSrc = &pHalData->DM_OutSrc; - u1Byte TotalAssocEntryNum = 0; - u1Byte index = 0; - u1Byte adaptercount = 0; - - ODM_CmnInfoPtrArrayHook(pDM_OutSrc, ODM_CMNINFO_STA_STATUS, 0, &pLoopAdapter->MgntInfo.DefaultPort[0]); - pLoopAdapter->MgntInfo.DefaultPort[0].MultiPortStationIdx = TotalAssocEntryNum; - - adaptercount += 1; - RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount)); - pLoopAdapter = GetNextExtAdapter(pLoopAdapter); - TotalAssocEntryNum +=1; + i = (u8)((value - 1) >> 3); + j = (u8)(value - 1) - (i << 3); - while(pLoopAdapter) - { - for (index = 0; index MgntInfo.AsocEntry[index]); - pLoopAdapter->MgntInfo.AsocEntry[index].MultiPortStationIdx = TotalAssocEntryNum+index; - } - - TotalAssocEntryNum+= index; - if(IS_HARDWARE_TYPE_8188E((pDM_Odm->Adapter))) - pLoopAdapter->RASupport = TRUE; - adaptercount += 1; - RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount)); - pLoopAdapter = GetNextExtAdapter(pLoopAdapter); - } + linear = db_invert_table[i][j]; - RT_TRACE(COMP_INIT, DBG_LOUD, ("TotalAssocEntryNum = %d\n", TotalAssocEntryNum)); - if (TotalAssocEntryNum < (ODM_ASSOCIATE_ENTRY_NUM-1)) { - - RT_TRACE(COMP_INIT, DBG_LOUD, ("In hook null\n")); - for (index = TotalAssocEntryNum; index < ODM_ASSOCIATE_ENTRY_NUM; index++) - ODM_CmnInfoPtrArrayHook(pDM_OutSrc, ODM_CMNINFO_STA_STATUS, index, NULL); - } -#endif + return linear; } #if (DM_ODM_SUPPORT_TYPE == ODM_CE) /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */ -void odm_dtc(PDM_ODM_T pDM_Odm) +void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm) { #ifdef CONFIG_DM_RESP_TXAGC - #define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */ - #define DTC_DWN_BASE (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */ +#define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */ +#define DTC_DWN_BASE (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */ /* RSSI vs TX power step mapping: decade TX power */ - static const u8 dtc_table_down[]={ + static const u8 dtc_table_down[] = { DTC_BASE, - (DTC_BASE+5), - (DTC_BASE+10), - (DTC_BASE+15), - (DTC_BASE+20), - (DTC_BASE+25) + (DTC_BASE + 5), + (DTC_BASE + 10), + (DTC_BASE + 15), + (DTC_BASE + 20), + (DTC_BASE + 25) }; /* RSSI vs TX power step mapping: increase TX power */ - static const u8 dtc_table_up[]={ + static const u8 dtc_table_up[] = { DTC_DWN_BASE, - (DTC_DWN_BASE-5), - (DTC_DWN_BASE-10), - (DTC_DWN_BASE-15), - (DTC_DWN_BASE-15), - (DTC_DWN_BASE-20), - (DTC_DWN_BASE-20), - (DTC_DWN_BASE-25), - (DTC_DWN_BASE-25), - (DTC_DWN_BASE-30), - (DTC_DWN_BASE-35) + (DTC_DWN_BASE - 5), + (DTC_DWN_BASE - 10), + (DTC_DWN_BASE - 15), + (DTC_DWN_BASE - 15), + (DTC_DWN_BASE - 20), + (DTC_DWN_BASE - 20), + (DTC_DWN_BASE - 25), + (DTC_DWN_BASE - 25), + (DTC_DWN_BASE - 30), + (DTC_DWN_BASE - 35) }; u8 i; - u8 dtc_steps=0; + u8 dtc_steps = 0; u8 sign; - u8 resp_txagc=0; + u8 resp_txagc = 0; - #if 0 +#if 0 /* As DIG is disabled, DTC is also disable */ - if(!(pDM_Odm->SupportAbility & ODM_XXXXXX)) + if (!(p_dm_odm->support_ability & ODM_XXXXXX)) return; - #endif +#endif - if (DTC_BASE < pDM_Odm->RSSI_Min) { + if (DTC_BASE < p_dm_odm->rssi_min) { /* need to decade the CTS TX power */ sign = 1; - for (i=0;i= pDM_Odm->RSSI_Min) || (dtc_steps >= 6)) + for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) { + if ((dtc_table_down[i] >= p_dm_odm->rssi_min) || (dtc_steps >= 6)) break; else dtc_steps++; } } #if 0 - else if (DTC_DWN_BASE > pDM_Odm->RSSI_Min) - { + else if (DTC_DWN_BASE > p_dm_odm->rssi_min) { /* needs to increase the CTS TX power */ sign = 0; dtc_steps = 1; - for (i=0;iRSSI_Min) || (dtc_steps>=10)) + for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) { + if ((dtc_table_up[i] <= p_dm_odm->rssi_min) || (dtc_steps >= 10)) break; else dtc_steps++; } } #endif - else - { + else { sign = 0; dtc_steps = 0; } resp_txagc = dtc_steps | (sign << 4); resp_txagc = resp_txagc | (resp_txagc << 5); - ODM_Write1Byte(pDM_Odm, 0x06d9, resp_txagc); + odm_write_1byte(p_dm_odm, 0x06d9, resp_txagc); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PWR_TRAIN, ODM_DBG_LOUD, ("%s RSSI_Min:%u, set RESP_TXAGC to %s %u\n", - __func__, pDM_Odm->RSSI_Min, sign ? "minus" : "plus", dtc_steps)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PWR_TRAIN, ODM_DBG_LOUD, ("%s rssi_min:%u, set RESP_TXAGC to %s %u\n", + __func__, p_dm_odm->rssi_min, sign ? "minus" : "plus", dtc_steps)); #endif /* CONFIG_RESP_TXAGC_ADJUST */ } #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ -VOID -odm_UpdatePowerTrainingState( - IN PDM_ODM_T pDM_Odm - ) +void +odm_update_power_training_state( + struct PHY_DM_STRUCT *p_dm_odm +) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT); - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u4Byte score = 0; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u32 score = 0; - if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_TRAIN)) + if (!(p_dm_odm->support_ability & ODM_BB_PWR_TRAIN)) return; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState()============>\n")); - pDM_Odm->bChangeState = FALSE; - - // Debug command - if(pDM_Odm->ForcePowerTrainingState) - { - if(pDM_Odm->ForcePowerTrainingState == 1 && !pDM_Odm->bDisablePowerTraining) - { - pDM_Odm->bChangeState = TRUE; - pDM_Odm->bDisablePowerTraining = TRUE; - } - else if(pDM_Odm->ForcePowerTrainingState == 2 && pDM_Odm->bDisablePowerTraining) - { - pDM_Odm->bChangeState = TRUE; - pDM_Odm->bDisablePowerTraining = FALSE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state()============>\n")); + p_dm_odm->is_change_state = false; + + /* Debug command */ + if (p_dm_odm->force_power_training_state) { + if (p_dm_odm->force_power_training_state == 1 && !p_dm_odm->is_disable_power_training) { + p_dm_odm->is_change_state = true; + p_dm_odm->is_disable_power_training = true; + } else if (p_dm_odm->force_power_training_state == 2 && p_dm_odm->is_disable_power_training) { + p_dm_odm->is_change_state = true; + p_dm_odm->is_disable_power_training = false; } - pDM_Odm->PT_score = 0; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): ForcePowerTrainingState = %d\n", - pDM_Odm->ForcePowerTrainingState)); + p_dm_odm->PT_score = 0; + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; + p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): force_power_training_state = %d\n", + p_dm_odm->force_power_training_state)); return; } - - if(!pDM_Odm->bLinked) + + if (!p_dm_odm->is_linked) return; - - // First connect - if((pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE)) - { - pDM_Odm->PT_score = 0; - pDM_Odm->bChangeState = TRUE; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): First Connect\n")); + + /* First connect */ + if ((p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == false)) { + p_dm_odm->PT_score = 0; + p_dm_odm->is_change_state = true; + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; + p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): First Connect\n")); return; } - // Compute score - if(pDM_Odm->NHM_cnt_0 >= 215) + /* Compute score */ + if (p_dm_odm->nhm_cnt_0 >= 215) score = 2; - else if(pDM_Odm->NHM_cnt_0 >= 190) - score = 1; // unknow state - else - { - u4Byte RX_Pkt_Cnt; - - RX_Pkt_Cnt = (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM) + (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK); - - if((FalseAlmCnt->Cnt_CCA_all > 31 && RX_Pkt_Cnt > 31) && (FalseAlmCnt->Cnt_CCA_all >= RX_Pkt_Cnt)) - { - if((RX_Pkt_Cnt + (RX_Pkt_Cnt >> 1)) <= FalseAlmCnt->Cnt_CCA_all) + else if (p_dm_odm->nhm_cnt_0 >= 190) + score = 1; /* unknow state */ + else { + u32 rx_pkt_cnt; + + rx_pkt_cnt = (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm) + (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_cck); + + if ((false_alm_cnt->cnt_cca_all > 31 && rx_pkt_cnt > 31) && (false_alm_cnt->cnt_cca_all >= rx_pkt_cnt)) { + if ((rx_pkt_cnt + (rx_pkt_cnt >> 1)) <= false_alm_cnt->cnt_cca_all) score = 0; - else if((RX_Pkt_Cnt + (RX_Pkt_Cnt >> 2)) <= FalseAlmCnt->Cnt_CCA_all) + else if ((rx_pkt_cnt + (rx_pkt_cnt >> 2)) <= false_alm_cnt->cnt_cca_all) score = 1; else score = 2; } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): RX_Pkt_Cnt = %d, Cnt_CCA_all = %d\n", - RX_Pkt_Cnt, FalseAlmCnt->Cnt_CCA_all)); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): NumQryPhyStatusOFDM = %d, NumQryPhyStatusCCK = %d\n", - (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM), (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): NHM_cnt_0 = %d, score = %d\n", - pDM_Odm->NHM_cnt_0, score)); - - // smoothing - pDM_Odm->PT_score = (score << 4) + (pDM_Odm->PT_score>>1) + (pDM_Odm->PT_score>>2); - score = (pDM_Odm->PT_score + 32) >> 6; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): PT_score = %d, score after smoothing = %d\n", - pDM_Odm->PT_score, score)); - - // Mode decision - if(score == 2) - { - if(pDM_Odm->bDisablePowerTraining) - { - pDM_Odm->bChangeState = TRUE; - pDM_Odm->bDisablePowerTraining = FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Change state\n")); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Enable Power Training\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): rx_pkt_cnt = %d, cnt_cca_all = %d\n", + rx_pkt_cnt, false_alm_cnt->cnt_cca_all)); } - else if(score == 0) - { - if(!pDM_Odm->bDisablePowerTraining) - { - pDM_Odm->bChangeState = TRUE; - pDM_Odm->bDisablePowerTraining = TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Change state\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): num_qry_phy_status_ofdm = %d, num_qry_phy_status_cck = %d\n", + (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm), (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_cck))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): nhm_cnt_0 = %d, score = %d\n", + p_dm_odm->nhm_cnt_0, score)); + + /* smoothing */ + p_dm_odm->PT_score = (score << 4) + (p_dm_odm->PT_score >> 1) + (p_dm_odm->PT_score >> 2); + score = (p_dm_odm->PT_score + 32) >> 6; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): PT_score = %d, score after smoothing = %d\n", + p_dm_odm->PT_score, score)); + + /* mode decision */ + if (score == 2) { + if (p_dm_odm->is_disable_power_training) { + p_dm_odm->is_change_state = true; + p_dm_odm->is_disable_power_training = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Change state\n")); } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Disable Power Training\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Enable Power Training\n")); + } else if (score == 0) { + if (!p_dm_odm->is_disable_power_training) { + p_dm_odm->is_change_state = true; + p_dm_odm->is_disable_power_training = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Change state\n")); + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Disable Power Training\n")); } - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; + p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; #endif } @@ -2350,303 +3262,335 @@ odm_UpdatePowerTrainingState( /*#define TARGET_CHNL_NUM_2G_5G 59*/ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -u1Byte GetRightChnlPlaceforIQK(u1Byte chnl) +u8 get_right_chnl_place_for_iqk(u8 chnl) { - u1Byte channel_all[TARGET_CHNL_NUM_2G_5G] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, - 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165}; - u1Byte place = chnl; + u8 channel_all[TARGET_CHNL_NUM_2G_5G] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, + 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165 + }; + u8 place = chnl; + - if (chnl > 14) { for (place = 14; place < sizeof(channel_all); place++) { if (channel_all[place] == chnl) - return place-13; + return place - 13; } } - + return 0; } #endif /*===========================================================*/ -VOID -phydm_NoisyDetection( - IN PDM_ODM_T pDM_Odm - ) +void +phydm_noisy_detection( + struct PHY_DM_STRUCT *p_dm_odm +) { - u4Byte Total_FA_Cnt, Total_CCA_Cnt; - u4Byte Score = 0, i, Score_Smooth; - - Total_CCA_Cnt = pDM_Odm->FalseAlmCnt.Cnt_CCA_all; - Total_FA_Cnt = pDM_Odm->FalseAlmCnt.Cnt_all; + u32 total_fa_cnt, total_cca_cnt; + u32 score = 0, i, score_smooth; -/* - if( Total_FA_Cnt*16>=Total_CCA_Cnt*14 ) // 87.5 - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*12 ) // 75 - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*10 ) // 56.25 - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*8 ) // 50 + total_cca_cnt = p_dm_odm->false_alm_cnt.cnt_cca_all; + total_fa_cnt = p_dm_odm->false_alm_cnt.cnt_all; + +#if 0 + if (total_fa_cnt * 16 >= total_cca_cnt * 14) /* 87.5 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /* 75 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /* 56.25 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /* 50 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /* 43.75 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /* 37.5 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /* 31.25% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /* 25% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /* 18.75% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /* 12.5% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /* 6.25% */ + ; +#endif + for (i = 0; i <= 16; i++) { + if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) { + score = 16 - i; + break; + } + } - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*7 ) // 43.75 + /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */ + p_dm_odm->noisy_decision_smooth = (p_dm_odm->noisy_decision_smooth >> 1) + (score << 2); - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*6 ) // 37.5 + /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */ + score_smooth = (total_cca_cnt >= 300) ? ((p_dm_odm->noisy_decision_smooth + 3) >> 3) : 0; - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*5 ) // 31.25% - - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*4 ) // 25% + p_dm_odm->noisy_decision = (score_smooth >= 3) ? 1 : 0; +#if 0 + switch (score_smooth) { + case 0: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=0%%\n")); + break; + case 1: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=6.25%%\n")); + break; + case 2: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=12.5%%\n")); + break; + case 3: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=18.75%%\n")); + break; + case 4: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=25%%\n")); + break; + case 5: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=31.25%%\n")); + break; + case 6: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=37.5%%\n")); + break; + case 7: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=43.75%%\n")); + break; + case 8: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=50%%\n")); + break; + case 9: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=56.25%%\n")); + break; + case 10: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=62.5%%\n")); + break; + case 11: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=68.75%%\n")); + break; + case 12: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=75%%\n")); + break; + case 13: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=81.25%%\n")); + break; + case 14: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=87.5%%\n")); + break; + case 15: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=93.75%%\n")); + break; + case 16: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] total_fa_cnt/total_cca_cnt=100%%\n")); + break; + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Unknown value!! Need Check!!\n")); + } +#endif + ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, + ("[NoisyDetection] total_cca_cnt=%d, total_fa_cnt=%d, noisy_decision_smooth=%d, score=%d, score_smooth=%d, p_dm_odm->noisy_decision=%d\n", + total_cca_cnt, total_fa_cnt, p_dm_odm->noisy_decision_smooth, score, score_smooth, p_dm_odm->noisy_decision)); - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*3 ) // 18.75% +} - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*2 ) // 12.5% +void +phydm_set_ext_switch( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 ext_ant_switch = dm_value[0]; - else if( Total_FA_Cnt*16>=Total_CCA_Cnt*1 ) // 6.25% -*/ - for(i=0;i<=16;i++) - { - if( Total_FA_Cnt*16>=Total_CCA_Cnt*(16-i) ) - { - Score = 16-i; - break; - } - } + if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { - // NoisyDecision_Smooth = NoisyDecision_Smooth>>1 + (Score<<3)>>1; - pDM_Odm->NoisyDecision_Smooth = (pDM_Odm->NoisyDecision_Smooth>>1) + (Score<<2); + /*Output Pin Settings*/ + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /*select DPDT_P and DPDT_N as output pin*/ + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /*by WLAN control*/ - // Round the NoisyDecision_Smooth: +"3" comes from (2^3)/2-1 - Score_Smooth = (Total_CCA_Cnt>=300)?((pDM_Odm->NoisyDecision_Smooth+3)>>3):0; + odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/ + odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/ - pDM_Odm->NoisyDecision = (Score_Smooth>=3)?1:0; -/* - switch(Score_Smooth) - { - case 0: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=0%%\n")); - break; - case 1: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=6.25%%\n")); - break; - case 2: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=12.5%%\n")); - break; - case 3: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=18.75%%\n")); - break; - case 4: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=25%%\n")); - break; - case 5: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=31.25%%\n")); - break; - case 6: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=37.5%%\n")); - break; - case 7: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=43.75%%\n")); - break; - case 8: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=50%%\n")); - break; - case 9: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=56.25%%\n")); - break; - case 10: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=62.5%%\n")); - break; - case 11: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=68.75%%\n")); - break; - case 12: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=75%%\n")); - break; - case 13: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=81.25%%\n")); - break; - case 14: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=87.5%%\n")); - break; - case 15: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=93.75%%\n")); - break; - case 16: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=100%%\n")); - break; - default: - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Unknown Value!! Need Check!!\n")); - } -*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, - ("[NoisyDetection] Total_CCA_Cnt=%d, Total_FA_Cnt=%d, NoisyDecision_Smooth=%d, Score=%d, Score_Smooth=%d, pDM_Odm->NoisyDecision=%d\n", - Total_CCA_Cnt, Total_FA_Cnt, pDM_Odm->NoisyDecision_Smooth, Score, Score_Smooth, pDM_Odm->NoisyDecision)); - + if (ext_ant_switch == MAIN_ANT) { + odm_set_bb_reg(p_dm_odm, 0xCB4, (BIT(29) | BIT(28)), 1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("***8821A set ant switch = 2b'01 (Main)\n")); + } else if (ext_ant_switch == AUX_ANT) { + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29) | BIT(28), 2); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("***8821A set ant switch = 2b'10 (Aux)\n")); + } + } } -VOID +void phydm_csi_mask_enable( - IN PVOID pDM_VOID, - IN u4Byte enable + void *p_dm_void, + u32 enable ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte reg_value = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 reg_value = 0; reg_value = (enable == CSI_MASK_ENABLE) ? 1 : 0; - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, reg_value); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", reg_value)); - - } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0xD2C, BIT(28), reg_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", reg_value)); - ODM_SetBBReg(pDM_Odm, 0x874, BIT0, reg_value); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", reg_value)); + } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0x874, BIT(0), reg_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", reg_value)); } - + } -VOID +void phydm_clean_all_csi_mask( - IN PVOID pDM_VOID + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0xD4c, bMaskDWord, 0); - - } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - ODM_SetBBReg(pDM_Odm, 0x880, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x884, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x888, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x88c, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x890, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x894, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x898, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x89c, bMaskDWord, 0); + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0xD40, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0xD44, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0xD48, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0xD4c, MASKDWORD, 0); + + } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0x880, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x884, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x888, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x88c, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x890, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x894, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x898, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x89c, MASKDWORD, 0); } } -VOID +void phydm_set_csi_mask_reg( - IN PVOID pDM_VOID, - IN u4Byte tone_idx_tmp, - IN u1Byte tone_direction + void *p_dm_void, + u32 tone_idx_tmp, + u8 tone_direction ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte byte_offset, bit_offset; - u4Byte target_reg; - u1Byte reg_tmp_value; - u4Byte tone_num = 64; - u4Byte tone_num_shift = 0; - u4Byte csi_mask_reg_p = 0, csi_mask_reg_n = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 byte_offset, bit_offset; + u32 target_reg; + u8 reg_tmp_value; + u32 tone_num = 64; + u32 tone_num_shift = 0; + u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0; /* calculate real tone idx*/ if ((tone_idx_tmp % 10) >= 5) tone_idx_tmp += 10; - tone_idx_tmp = (tone_idx_tmp/10); + tone_idx_tmp = (tone_idx_tmp / 10); - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { tone_num = 64; csi_mask_reg_p = 0xD40; - csi_mask_reg_n = 0xD48; - - } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + csi_mask_reg_n = 0xD48; + + } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { tone_num = 128; csi_mask_reg_p = 0x880; - csi_mask_reg_n = 0x890; + csi_mask_reg_n = 0x890; } - + if (tone_direction == FREQ_POSITIVE) { if (tone_idx_tmp >= (tone_num - 1)) tone_idx_tmp = (tone_num - 1); - - byte_offset = (u1Byte)(tone_idx_tmp >> 3); - bit_offset = (u1Byte)(tone_idx_tmp & 0x7); + + byte_offset = (u8)(tone_idx_tmp >> 3); + bit_offset = (u8)(tone_idx_tmp & 0x7); target_reg = csi_mask_reg_p + byte_offset; - + } else { tone_num_shift = tone_num; - + if (tone_idx_tmp >= tone_num) tone_idx_tmp = tone_num; tone_idx_tmp = tone_num - tone_idx_tmp; - - byte_offset = (u1Byte)(tone_idx_tmp >> 3); - bit_offset = (u1Byte)(tone_idx_tmp & 0x7); + + byte_offset = (u8)(tone_idx_tmp >> 3); + bit_offset = (u8)(tone_idx_tmp & 0x7); target_reg = csi_mask_reg_n + byte_offset; } - - reg_tmp_value = ODM_Read1Byte(pDM_Odm, target_reg); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); + + reg_tmp_value = odm_read_1byte(p_dm_odm, target_reg); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); reg_tmp_value |= BIT(bit_offset); - ODM_Write1Byte(pDM_Odm, target_reg, reg_tmp_value); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); + odm_write_1byte(p_dm_odm, target_reg, reg_tmp_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); } -VOID +void phydm_set_nbi_reg( - IN PVOID pDM_VOID, - IN u4Byte tone_idx_tmp, - IN u4Byte bw + void *p_dm_void, + u32 tone_idx_tmp, + u32 bw ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte nbi_table_128[NBI_TABLE_SIZE_128] = {25, 55, 85, 115, 135, 155, 185, 205, 225, 245, /*1~10*/ /*tone_idx X 10*/ - 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/ - 485, 505, 525, 555, 585, 615, 635}; /*21~27*/ - - u4Byte nbi_table_256[NBI_TABLE_SIZE_256] = { 25, 55, 85, 115, 135, 155, 175, 195, 225, 245, /*1~10*/ - 265, 285, 305, 325, 345, 365, 385, 405, 425, 445, /*11~20*/ - 465, 485, 505, 525, 545, 565, 585, 605, 625, 645, /*21~30*/ - 665, 695, 715, 735, 755, 775, 795, 815, 835, 855, /*31~40*/ - 875, 895, 915, 935, 955, 975, 995, 1015, 1035, 1055, /*41~50*/ - 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275}; /*51~59*/ - - u4Byte reg_idx = 0; - u4Byte i; - u1Byte nbi_table_idx = FFT_128_TYPE; - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 nbi_table_128[NBI_TABLE_SIZE_128] = {25, 55, 85, 115, 135, 155, 185, 205, 225, 245, /*1~10*/ /*tone_idx X 10*/ + 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/ + 485, 505, 525, 555, 585, 615, 635 + }; /*21~27*/ + + u32 nbi_table_256[NBI_TABLE_SIZE_256] = { 25, 55, 85, 115, 135, 155, 175, 195, 225, 245, /*1~10*/ + 265, 285, 305, 325, 345, 365, 385, 405, 425, 445, /*11~20*/ + 465, 485, 505, 525, 545, 565, 585, 605, 625, 645, /*21~30*/ + 665, 695, 715, 735, 755, 775, 795, 815, 835, 855, /*31~40*/ + 875, 895, 915, 935, 955, 975, 995, 1015, 1035, 1055, /*41~50*/ + 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275 + }; /*51~59*/ + + u32 reg_idx = 0; + u32 i; + u8 nbi_table_idx = FFT_128_TYPE; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + nbi_table_idx = FFT_128_TYPE; - } else if (pDM_Odm->SupportICType & ODM_IC_11AC_1_SERIES) { - + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_1_SERIES) + nbi_table_idx = FFT_256_TYPE; - } else if (pDM_Odm->SupportICType & ODM_IC_11AC_2_SERIES) { - + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_2_SERIES) { + if (bw == 80) nbi_table_idx = FFT_256_TYPE; else /*20M, 40M*/ @@ -2654,97 +3598,101 @@ phydm_set_nbi_reg( } if (nbi_table_idx == FFT_128_TYPE) { - + for (i = 0; i < NBI_TABLE_SIZE_128; i++) { if (tone_idx_tmp < nbi_table_128[i]) { - reg_idx = i+1; + reg_idx = i + 1; break; } } - + } else if (nbi_table_idx == FFT_256_TYPE) { for (i = 0; i < NBI_TABLE_SIZE_256; i++) { if (tone_idx_tmp < nbi_table_256[i]) { - reg_idx = i+1; + reg_idx = i + 1; break; } - } + } } - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - ODM_SetBBReg(pDM_Odm, 0xc40, 0x1f000000, reg_idx); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", reg_idx)); + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(p_dm_odm, 0xc40, 0x1f000000, reg_idx); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", reg_idx)); /**/ } else { - ODM_SetBBReg(pDM_Odm, 0x87c, 0xfc000, reg_idx); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", reg_idx)); + odm_set_bb_reg(p_dm_odm, 0x87c, 0xfc000, reg_idx); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", reg_idx)); /**/ } } -VOID +void phydm_nbi_enable( - IN PVOID pDM_VOID, - IN u4Byte enable + void *p_dm_void, + u32 enable ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte reg_value = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 reg_value = 0; reg_value = (enable == NBI_ENABLE) ? 1 : 0; - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - ODM_SetBBReg(pDM_Odm, 0xc40, BIT9, reg_value); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value)); - - } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0xc40, BIT(9), reg_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value)); - ODM_SetBBReg(pDM_Odm, 0x87c, BIT13, reg_value); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value)); + } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + if (p_dm_odm->support_ic_type & (ODM_RTL8822B|ODM_RTL8821C)) { + odm_set_bb_reg(p_dm_odm, 0xc20, BIT(28), reg_value); + if (p_dm_odm->rf_type > ODM_1T1R) + odm_set_bb_reg(p_dm_odm, 0xe20, BIT(28), reg_value); + } else + odm_set_bb_reg(p_dm_odm, 0x87c, BIT(13), reg_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value)); } } -u1Byte +u8 phydm_calculate_fc( - IN PVOID pDM_VOID, - IN u4Byte channel, - IN u4Byte bw, - IN u4Byte Second_ch, - IN OUT u4Byte *fc_in + void *p_dm_void, + u32 channel, + u32 bw, + u32 second_ch, + u32 *fc_in ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte fc = *fc_in; - u4Byte start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173}; - u4Byte start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, 149, 165}; - pu4Byte p_start_ch = &(start_ch_per_40m[0]); - u4Byte num_start_channel = NUM_START_CH_40M; - u4Byte channel_offset = 0; - u4Byte i; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 fc = *fc_in; + u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173}; + u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, 149, 165}; + u32 *p_start_ch = &(start_ch_per_40m[0]); + u32 num_start_channel = NUM_START_CH_40M; + u32 channel_offset = 0; + u32 i; /*2.4G*/ if (channel <= 14 && channel > 0) { - if (bw == 80) { + if (bw == 80) return SET_ERROR; - } - fc = 2412 + (channel - 1)*5; + fc = 2412 + (channel - 1) * 5; + + if (bw == 40 && (second_ch == PHYDM_ABOVE)) { - if (bw == 40 && (Second_ch == PHYDM_ABOVE)) { - if (channel >= 10) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error Setting\n", channel, Second_ch)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch)); return SET_ERROR; } fc += 10; - } else if (bw == 40 && (Second_ch == PHYDM_BELOW)) { - + } else if (bw == 40 && (second_ch == PHYDM_BELOW)) { + if (channel <= 2) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error Setting\n", channel, Second_ch)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch)); return SET_ERROR; } fc -= 10; @@ -2754,7 +3702,7 @@ phydm_calculate_fc( else if (channel >= 36 && channel <= 177) { if (bw != 20) { - + if (bw == 40) { num_start_channel = NUM_START_CH_40M; p_start_ch = &(start_ch_per_40m[0]); @@ -2766,53 +3714,53 @@ phydm_calculate_fc( } for (i = 0; i < num_start_channel; i++) { - - if (channel < p_start_ch[i+1]) { + + if (channel < p_start_ch[i + 1]) { channel = p_start_ch[i] + channel_offset; break; } } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Mod_CH = ((%d))\n", channel)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Mod_CH = ((%d))\n", channel)); } - - fc = 5180 + (channel-36)*5; - + + fc = 5180 + (channel - 36) * 5; + } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)) Error Setting\n", channel)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)) Error setting\n", channel)); return SET_ERROR; } - + *fc_in = fc; - + return SET_SUCCESS; } -u1Byte +u8 phydm_calculate_intf_distance( - IN PVOID pDM_VOID, - IN u4Byte bw, - IN u4Byte fc, - IN u4Byte f_interference, - IN OUT u4Byte *p_tone_idx_tmp_in + void *p_dm_void, + u32 bw, + u32 fc, + u32 f_interference, + u32 *p_tone_idx_tmp_in ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte bw_up, bw_low; - u4Byte int_distance; - u4Byte tone_idx_tmp; - u1Byte set_result = SET_NO_NEED; - - bw_up = fc + bw/2; - bw_low = fc - bw/2; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 bw_up, bw_low; + u32 int_distance; + u32 tone_idx_tmp; + u8 set_result = SET_NO_NEED; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, fc, bw_up, f_interference)); + bw_up = fc + bw / 2; + bw_low = fc - bw / 2; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, fc, bw_up, f_interference)); if ((f_interference >= bw_low) && (f_interference <= bw_up)) { int_distance = (fc >= f_interference) ? (fc - f_interference) : (f_interference - fc); - tone_idx_tmp = (int_distance<<5); /* =10*(int_distance /0.3125) */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", int_distance, (tone_idx_tmp/10), (tone_idx_tmp%10))); + tone_idx_tmp = (int_distance << 5); /* =10*(int_distance /0.3125) */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", int_distance, (tone_idx_tmp / 10), (tone_idx_tmp % 10))); *p_tone_idx_tmp_in = tone_idx_tmp; set_result = SET_SUCCESS; } @@ -2822,42 +3770,41 @@ phydm_calculate_intf_distance( } -u1Byte +u8 phydm_csi_mask_setting( - IN PVOID pDM_VOID, - IN u4Byte enable, - IN u4Byte channel, - IN u4Byte bw, - IN u4Byte f_interference, - IN u4Byte Second_ch + void *p_dm_void, + u32 enable, + u32 channel, + u32 bw, + u32 f_interference, + u32 second_ch ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte fc; - u4Byte int_distance; - u1Byte tone_direction; - u4Byte tone_idx_tmp; - u1Byte set_result = SET_SUCCESS; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 fc; + u8 tone_direction; + u32 tone_idx_tmp; + u8 set_result = SET_SUCCESS; if (enable == CSI_MASK_DISABLE) { set_result = SET_SUCCESS; - phydm_clean_all_csi_mask(pDM_Odm); - + phydm_clean_all_csi_mask(p_dm_odm); + } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, (((bw == 20) || (channel > 14)) ? "Don't care" : (Second_ch == PHYDM_ABOVE) ? "H" : "L"))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, (((bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L"))); /*calculate fc*/ - if (phydm_calculate_fc(pDM_Odm, channel, bw, Second_ch, &fc) == SET_ERROR) + if (phydm_calculate_fc(p_dm_odm, channel, bw, second_ch, &fc) == SET_ERROR) set_result = SET_ERROR; - + else { /*calculate interference distance*/ - if (phydm_calculate_intf_distance(pDM_Odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { - + if (phydm_calculate_intf_distance(p_dm_odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { + tone_direction = (f_interference >= fc) ? FREQ_POSITIVE : FREQ_NEGATIVE; - phydm_set_csi_mask_reg(pDM_Odm, tone_idx_tmp, tone_direction); + phydm_set_csi_mask_reg(p_dm_odm, tone_idx_tmp, tone_direction); set_result = SET_SUCCESS; } else set_result = SET_NO_NEED; @@ -2865,47 +3812,45 @@ phydm_csi_mask_setting( } if (set_result == SET_SUCCESS) - phydm_csi_mask_enable(pDM_Odm, enable); + phydm_csi_mask_enable(p_dm_odm, enable); else - phydm_csi_mask_enable(pDM_Odm, CSI_MASK_DISABLE); + phydm_csi_mask_enable(p_dm_odm, CSI_MASK_DISABLE); return set_result; } -u1Byte +u8 phydm_nbi_setting( - IN PVOID pDM_VOID, - IN u4Byte enable, - IN u4Byte channel, - IN u4Byte bw, - IN u4Byte f_interference, - IN u4Byte Second_ch + void *p_dm_void, + u32 enable, + u32 channel, + u32 bw, + u32 f_interference, + u32 second_ch ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte fc; - u4Byte int_distance; - u4Byte tone_idx_tmp; - u1Byte set_result = SET_SUCCESS; - u4Byte bw_max = 40; - - if (enable == NBI_DISABLE) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 fc; + u32 tone_idx_tmp; + u8 set_result = SET_SUCCESS; + + if (enable == NBI_DISABLE) set_result = SET_SUCCESS; - + else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, (((Second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : (Second_ch == PHYDM_ABOVE) ? "H" : "L"))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L"))); /*calculate fc*/ - if (phydm_calculate_fc(pDM_Odm, channel, bw, Second_ch, &fc) == SET_ERROR) + if (phydm_calculate_fc(p_dm_odm, channel, bw, second_ch, &fc) == SET_ERROR) set_result = SET_ERROR; - + else { /*calculate interference distance*/ - if (phydm_calculate_intf_distance(pDM_Odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { - - phydm_set_nbi_reg(pDM_Odm, tone_idx_tmp, bw); + if (phydm_calculate_intf_distance(p_dm_odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { + + phydm_set_nbi_reg(p_dm_odm, tone_idx_tmp, bw); set_result = SET_SUCCESS; } else set_result = SET_NO_NEED; @@ -2913,86 +3858,286 @@ phydm_nbi_setting( } if (set_result == SET_SUCCESS) - phydm_nbi_enable(pDM_Odm, enable); + phydm_nbi_enable(p_dm_odm, enable); else - phydm_nbi_enable(pDM_Odm, NBI_DISABLE); + phydm_nbi_enable(p_dm_odm, NBI_DISABLE); return set_result; } -VOID +void phydm_api_debug( - IN PVOID pDM_VOID, - IN u4Byte function_map, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - u4Byte channel = dm_value[1]; - u4Byte bw = dm_value[2]; - u4Byte f_interference = dm_value[3]; - u4Byte Second_ch = dm_value[4]; - u1Byte set_result = 0; + void *p_dm_void, + u32 function_map, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 channel = dm_value[1]; + u32 bw = dm_value[2]; + u32 f_interference = dm_value[3]; + u32 second_ch = dm_value[4]; + u8 set_result = 0; /*PHYDM_API_NBI*/ /*-------------------------------------------------------------------------------------------------------------------------------*/ if (function_map == PHYDM_API_NBI) { - + if (dm_value[0] == 100) { - - PHYDM_SNPRINTF((output+used, out_len-used, "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); + + PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); return; - + } else if (dm_value[0] == NBI_ENABLE) { - - PHYDM_SNPRINTF((output+used, out_len-used, "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, ((Second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : ((Second_ch == PHYDM_ABOVE) ? "H" : "L"))); - set_result = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, channel, bw, f_interference, Second_ch); - + + PHYDM_SNPRINTF((output + used, out_len - used, "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, ((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : ((second_ch == PHYDM_ABOVE) ? "H" : "L"))); + set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, bw, f_interference, second_ch); + } else if (dm_value[0] == NBI_DISABLE) { - - PHYDM_SNPRINTF((output+used, out_len-used, "[Disable NBI]\n")); - set_result = phydm_nbi_setting(pDM_Odm, NBI_DISABLE, channel, bw, f_interference, Second_ch); - - } else { - + + PHYDM_SNPRINTF((output + used, out_len - used, "[Disable NBI]\n")); + set_result = phydm_nbi_setting(p_dm_odm, NBI_DISABLE, channel, bw, f_interference, second_ch); + + } else + set_result = SET_ERROR; - } - PHYDM_SNPRINTF((output+used, out_len-used, "[NBI set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); - - } - + PHYDM_SNPRINTF((output + used, out_len - used, "[NBI set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); + + } + /*PHYDM_CSI_MASK*/ /*-------------------------------------------------------------------------------------------------------------------------------*/ else if (function_map == PHYDM_API_CSI_MASK) { - + if (dm_value[0] == 100) { - - PHYDM_SNPRINTF((output+used, out_len-used, "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); + + PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); return; - + } else if (dm_value[0] == CSI_MASK_ENABLE) { - - PHYDM_SNPRINTF((output+used, out_len-used, "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, (channel > 14)?"Don't care":(((Second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "H" : "L"))); - set_result = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, channel, bw, f_interference, Second_ch); - + + PHYDM_SNPRINTF((output + used, out_len - used, "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, (channel > 14) ? "Don't care" : (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "H" : "L"))); + set_result = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, channel, bw, f_interference, second_ch); + } else if (dm_value[0] == CSI_MASK_DISABLE) { - - PHYDM_SNPRINTF((output+used, out_len-used, "[Disable CSI MASK]\n")); - set_result = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_DISABLE, channel, bw, f_interference, Second_ch); - + + PHYDM_SNPRINTF((output + used, out_len - used, "[Disable CSI MASK]\n")); + set_result = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_DISABLE, channel, bw, f_interference, second_ch); + + } else + + set_result = SET_ERROR; + PHYDM_SNPRINTF((output + used, out_len - used, "[CSI MASK set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); + } +} + +void +phydm_stop_ck320( + void *p_dm_void, + u8 enable +) { + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 reg_value = (enable == true) ? 1 : 0; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, 0x8b4, BIT(6), reg_value); + /**/ + } else { + + if (p_dm_odm->support_ic_type & ODM_IC_N_2SS) { /*N-2SS*/ + odm_set_bb_reg(p_dm_odm, 0x87c, BIT(29), reg_value); + /**/ + } else { /*N-1SS*/ + odm_set_bb_reg(p_dm_odm, 0x87c, BIT(31), reg_value); + /**/ + } + } +} + + +/*<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/ +void +phydm_dc_cancellation( + struct PHY_DM_STRUCT *p_dm_odm + +) +{ +#if PHYDM_DC_CANCELLATION + u32 offset_i_hex[ODM_RF_PATH_MAX] = {0}; + u32 offset_q_hex[ODM_RF_PATH_MAX] = {0}; + u32 reg_value32[ODM_RF_PATH_MAX] = {0}; + u8 det_num = 0; + + if (!(p_dm_odm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT)) + return; + + /*DC_Estimation (only for 2x2 ic now) */ + +for (det_num = 0; det_num < ODM_RF_PATH_MAX; det_num++) { + if (p_dm_odm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) { + if (!phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_2, 0x235)) {/*set debug port to 0x235*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[DC Cancellation] Set Debug port Fail")); + return; + } + } else if (p_dm_odm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) { + /* Path-a */ + if (det_num == 0) { + if (!phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_2, 0x200)) {/*set debug port to 0x200*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[DC Cancellation] Set Debug port Fail")); + return; + } + phydm_bb_dbg_port_header_sel(p_dm_odm, 0x0); + /* Path-b */ + } else if (det_num == 1) { + + if (!(p_dm_odm->support_ic_type & ODM_RTL8822B)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[DC Cancellation] Only one-path now")); + break; + } + + if (!phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_2, 0x202)) {/*set debug port to 0x200*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[DC Cancellation] Set Debug port Fail")); + return; + } + phydm_bb_dbg_port_header_sel(p_dm_odm, 0x0); + } + } + + //odm_set_bb_reg(p_dm_odm, 0x908, bMaskDWord, 0x235); + //odm_set_bb_reg(p_dm_odm, 0xa78, BIT(3), 0x1); + odm_write_dig(p_dm_odm, 0x7E); + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(p_dm_odm, 0x88c, BIT(21)|BIT(20), 0x3); + } else { + odm_set_bb_reg(p_dm_odm, 0xc00, BIT(1)|BIT(0), 0x0); + odm_set_bb_reg(p_dm_odm, 0xe00, BIT(1)|BIT(0), 0x0); + } + odm_set_bb_reg(p_dm_odm, 0xa78, MASKBYTE1, 0x0); /*disable CCK DCNF*/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, (" DC cancellation Begin!!!")); + +#if 0 + + odm_set_bb_reg(p_dm_odm, 0x87c, BIT(31), 0x1); /*stop ck320*/ + offset_i_hex = odm_get_bb_reg(p_dm_odm, 0xDF4, 0xffc0000); + offset_q_hex = odm_get_bb_reg(p_dm_odm, 0xDF4, 0x3ff00); + odm_set_bb_reg(p_dm_odm, 0x87c, BIT(31), 0x0); /*start ck320*/ + +#else + + phydm_stop_ck320(p_dm_odm, true); /*stop ck320*/ + + /* the same debug port both for path-a and path-b*/ + if (det_num == 0) + reg_value32[det_num] = phydm_get_bb_dbg_port_value(p_dm_odm); + else if (det_num == 1) + reg_value32[det_num] = phydm_get_bb_dbg_port_value(p_dm_odm); + + phydm_stop_ck320(p_dm_odm, false); /*start ck320*/ + +#endif + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(p_dm_odm, 0x88c, BIT(21)|BIT(20), 0x0); } else { + odm_set_bb_reg(p_dm_odm, 0xc00, BIT(1)|BIT(0), 0x3); + odm_set_bb_reg(p_dm_odm, 0xe00, BIT(1)|BIT(0), 0x3); + } + odm_write_dig(p_dm_odm, 0x20); + phydm_release_bb_dbg_port(p_dm_odm); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, (" DC cancellation OK!!!")); +} - set_result = SET_ERROR; + /*DC_Cancellation*/ + odm_set_bb_reg(p_dm_odm, 0xa9c, BIT(20), 0x1); /*DC compensation to CCK data path*/ + if (p_dm_odm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) { + offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18; + offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8; + + /*Before filling into registers, offset should be multiplexed (-1)*/ + offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ? (0x400 - offset_i_hex[1]) : (0x1ff - offset_i_hex[1]); + offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ? (0x400 - offset_q_hex[1]) : (0x1ff - offset_q_hex[1]); + + odm_set_bb_reg(p_dm_odm, 0x950, 0x1ff, offset_i_hex[1]); + odm_set_bb_reg(p_dm_odm, 0x950, 0x1ff0000, offset_q_hex[1]); + } else if (p_dm_odm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) { + + /* Path-a */ + offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10; + offset_q_hex[0] = reg_value32[0] & 0x3ff; + + /*Before filling into registers, offset should be multiplexed (-1)*/ + offset_i_hex[0] = 0x400 - offset_i_hex[0]; + offset_q_hex[0] = 0x400 - offset_q_hex[0]; + + odm_set_bb_reg(p_dm_odm, 0xc10, 0x3c000000, ((0x3c0 & offset_i_hex[0]) >> 6)); + odm_set_bb_reg(p_dm_odm, 0xc10, 0xfc00, (0x3f & offset_i_hex[0])); + odm_set_bb_reg(p_dm_odm, 0xc14, 0x3c000000, ((0x3c0 & offset_q_hex[0]) >> 6)); + odm_set_bb_reg(p_dm_odm, 0xc14, 0xfc00, (0x3f & offset_q_hex[0])); + + /* Path-b */ + if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + + offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10; + offset_q_hex[1] = reg_value32[1] & 0x3ff; + + /*Before filling into registers, offset should be multiplexed (-1)*/ + offset_i_hex[1] = 0x400 - offset_i_hex[1]; + offset_q_hex[1] = 0x400 - offset_q_hex[1]; + + odm_set_bb_reg(p_dm_odm, 0xe10, 0x3c000000, ((0x3c0 & offset_i_hex[1]) >> 6)); + odm_set_bb_reg(p_dm_odm, 0xe10, 0xfc00, (0x3f & offset_i_hex[1])); + odm_set_bb_reg(p_dm_odm, 0xe14, 0x3c000000, ((0x3c0 & offset_q_hex[1]) >> 6)); + odm_set_bb_reg(p_dm_odm, 0xe14, 0xfc00, (0x3f & offset_q_hex[1])); } - PHYDM_SNPRINTF((output+used, out_len-used, "[CSI MASK set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); } +#endif } +void +phydm_receiver_blocking( + void *p_dm_void +) +{ +#ifdef CONFIG_RECEIVER_BLOCKING + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 channel = *p_dm_odm->p_channel; + u8 bw = *p_dm_odm->p_band_width; + u8 set_result = 0; + + if (!(p_dm_odm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT)) + return; + + if (p_dm_odm->consecutive_idlel_time > 10 && *p_dm_odm->p_mp_mode == false && p_dm_odm->adaptivity_enable == true) { + if ((bw == ODM_BW20M) && (channel == 1) && !p_dm_odm->is_nbi_enable) { + set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 2410, PHYDM_DONT_CARE); + p_dm_odm->is_nbi_enable = true; + } else if ((bw == ODM_BW20M) && (channel == 13) && !p_dm_odm->is_nbi_enable) { + set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 2473, PHYDM_DONT_CARE); + p_dm_odm->is_nbi_enable = true; + } else { + if (p_dm_odm->is_nbi_enable && channel != 1 && channel != 13) { + phydm_nbi_enable(p_dm_odm, NBI_DISABLE); + p_dm_odm->is_nbi_enable = false; + } + } + } else { + if (p_dm_odm->is_nbi_enable) { + phydm_nbi_enable(p_dm_odm, NBI_DISABLE); + p_dm_odm->is_nbi_enable = false; + } + } + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, + ("[NBI set result: %s]\n", (set_result == SET_SUCCESS ? "Success" : (set_result == SET_NO_NEED ? "No need" : "Error")))); +#endif +} diff --git a/hal/phydm/phydm.h b/hal/phydm/phydm.h index 442c3b7..25aff31 100644 --- a/hal/phydm/phydm.h +++ b/hal/phydm/phydm.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,23 +11,17 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HALDMOUTSRC_H__ #define __HALDMOUTSRC_H__ -//============================================================ -// include files -//============================================================ +/*============================================================*/ +/*include files*/ +/*============================================================*/ #include "phydm_pre_define.h" #include "phydm_dig.h" -#include "phydm_edcaturbocheck.h" #include "phydm_pathdiv.h" #include "phydm_antdiv.h" #include "phydm_antdect.h" @@ -37,36 +31,40 @@ #include "phydm_cfotracking.h" #include "phydm_acs.h" #include "phydm_adaptivity.h" -#include "phydm_iqk.h" #include "phydm_dfs.h" #include "phydm_ccx.h" #include "txbf/phydm_hal_txbf_api.h" -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) -#include "phydm_beamforming.h" +#include "phydm_adc_sampling.h" +#include "phydm_dynamic_rx_path.h" +#include "phydm_psd.h" +#include "halrf/halrf_iqk.h" +#include "halrf/halrf.h" + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) + #include "phydm_beamforming.h" #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#include "halphyrf_ap.h" -#include "phydm_adc_sampling.h" + #include "halrf/halphyrf_ap.h" #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -#include "phydm_noisemonitor.h" -#include "halphyrf_ce.h" + #include "phydm_noisemonitor.h" + #include "halrf/halphyrf_ce.h" #endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) -#include "halphyrf_win.h" -#include "phydm_noisemonitor.h" +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + #include "halrf/halphyrf_win.h" + #include "phydm_noisemonitor.h" #endif -//============================================================ -// Definition -//============================================================ -// -// 2011/09/22 MH Define all team supprt ability. -// +extern const u16 phy_rate_table[28]; + +/*============================================================*/ +/*Definition */ +/*============================================================*/ /* Traffic load decision */ #define TRAFFIC_ULTRA_LOW 1 @@ -106,273 +104,181 @@ #define FREQ_NEGATIVE 2 - -//============================================================ -// structure and define -//============================================================ - -// -// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. -// We need to remove to other position??? -// -#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) -typedef struct rtl8192cd_priv { - u1Byte temp; - -}rtl8192cd_priv, *prtl8192cd_priv; -#endif - - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -typedef struct _ADAPTER{ - u1Byte temp; - #ifdef AP_BUILD_WORKAROUND - HAL_DATA_TYPE* temp2; - prtl8192cd_priv priv; - #endif -}ADAPTER, *PADAPTER; -#endif - #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - -typedef struct _WLAN_STA{ - u1Byte temp; -} WLAN_STA, *PRT_WLAN_STA; - + #define PHYDM_WATCH_DOG_PERIOD 1 +#else + #define PHYDM_WATCH_DOG_PERIOD 2 #endif -typedef struct _Dynamic_Primary_CCA{ - u1Byte PriCCA_flag; - u1Byte intf_flag; - u1Byte intf_type; - u1Byte DupRTS_flag; - u1Byte Monitor_flag; - u1Byte CH_offset; - u1Byte MF_state; -}Pri_CCA_T, *pPri_CCA_T; - - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - #ifdef ADSL_AP_BUILD_WORKAROUND - #define MAX_TOLERANCE 5 - #define IQK_DELAY_TIME 1 /*ms*/ - #endif -#endif /*#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))*/ +/*============================================================*/ +/*structure and define*/ +/*============================================================*/ + +struct _dynamic_primary_cca { + u8 pri_cca_flag; + u8 intf_flag; + u8 intf_type; + u8 dup_rts_flag; + u8 monitor_flag; + u8 ch_offset; + u8 mf_state; +}; -#define DM_Type_ByFW 0 -#define DM_Type_ByDriver 1 +#define dm_type_by_fw 0 +#define dm_type_by_driver 1 -// -// Declare for common info -// +/*Declare for common info*/ #define IQK_THRESHOLD 8 #define DPK_THRESHOLD 4 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -__PACK typedef struct _ODM_Phy_Status_Info_ -{ - u1Byte RxPWDBAll; - u1Byte SignalQuality; /* in 0-100 index. */ - u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ - s1Byte RxMIMOSignalQuality[4]; /* EVM */ - s1Byte RxSNR[4]; /* per-path's SNR */ +__PACK struct _odm_phy_status_info_ { + u8 rx_pwdb_all; + u8 signal_quality; /* in 0-100 index. */ + u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ + u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */ + s8 rx_mimo_signal_quality[4]; /* EVM */ + s8 rx_snr[4]; /* per-path's SNR */ #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u1Byte RxCount:2; /* RX path counter---*/ - u1Byte BandWidth:2; - u1Byte rxsc:4; /* sub-channel---*/ + u8 rx_count:2; /* RX path counter---*/ + u8 band_width:2; + u8 rxsc:4; /* sub-channel---*/ #else - u1Byte BandWidth; + u8 band_width; #endif #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u1Byte channel; /* channel number---*/ - BOOLEAN bMuPacket; /* is MU packet or not---*/ - BOOLEAN bBeamformed; /* BF packet---*/ + u8 channel; /* channel number---*/ + boolean is_mu_packet; /* is MU packet or not---*/ + boolean is_beamformed; /* BF packet---*/ #endif -} __WLAN_ATTRIB_PACK__ ODM_PHY_INFO_T, *PODM_PHY_INFO_T; +}; -typedef struct _ODM_Phy_Status_Info_Append_ -{ - u1Byte MAC_CRC32; +struct _odm_phy_status_info_append_ { + u8 MAC_CRC32; -}ODM_PHY_INFO_Append_T,*PODM_PHY_INFO_Append_T; +}; #else -typedef struct _ODM_Phy_Status_Info_ -{ - // - // Be care, if you want to add any element please insert between - // RxPWDBAll & SignalStrength. - // +struct _odm_phy_status_info_ { + /* */ + /* Be care, if you want to add any element please both add at outer_driver & phydm */ + + /* WIN in _RT_RFD_STATUS*/ #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - u4Byte RxPWDBAll; + u32 rx_pwdb_all; /*in new Phy-status IC, represent the max PWDB among all path*/ #else - u1Byte RxPWDBAll; + u8 rx_pwdb_all; #endif - u1Byte SignalQuality; /* in 0-100 index. */ - s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */ - u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ - u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ - s2Byte Cfo_short[4]; /* per-path's Cfo_short */ - s2Byte Cfo_tail[4]; /* per-path's Cfo_tail */ - s1Byte RxPower; /* in dBm Translate from PWdB */ - s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ - u1Byte BTRxRSSIPercentage; - u1Byte SignalStrength; /* in 0-100 index. */ - s1Byte RxPwr[4]; /* per-path's pwdb */ - s1Byte RxSNR[4]; /* per-path's SNR */ + u8 signal_quality; /* in 0-100 index. */ + s8 rx_mimo_signal_quality[4]; /* per-path's EVM translate to 0~100% */ + u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */ + u8 rx_mimo_signal_strength[4]; /* RSSI in 0~100 index */ + s16 cfo_short[4]; /* per-path's cfo_short */ + s16 cfo_tail[4]; /* per-path's cfo_tail */ + s8 rx_power; /* in dBm Translate from PWdB */ + s8 recv_signal_power; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ + u8 bt_rx_rssi_percentage; + u8 signal_strength; /* in 0-100 index. */ + s8 rx_pwr[4]; /* per-path's pwdb */ + s8 rx_snr[4]; /* per-path's SNR */ + /* s8 BB_Backup[13]; backup reg. */ #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u1Byte RxCount:2; /* RX path counter---*/ - u1Byte BandWidth:2; - u1Byte rxsc:4; /* sub-channel---*/ + u8 rx_count:2; /* RX path counter---*/ + u8 band_width:2; + u8 rxsc:4; /* sub-channel---*/ #else - u1Byte BandWidth; + u8 band_width; #endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - u1Byte btCoexPwrAdjust; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + u8 bt_coex_pwr_adjust; #endif #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u1Byte channel; /* channel number---*/ - BOOLEAN bMuPacket; /* is MU packet or not---*/ - BOOLEAN bBeamformed; /* BF packet---*/ + u8 channel; /* channel number---*/ + boolean is_mu_packet; /* is MU packet or not---*/ + boolean is_beamformed; /* BF packet---*/ #endif -}ODM_PHY_INFO_T,*PODM_PHY_INFO_T; +}; #endif -typedef struct _ODM_Per_Pkt_Info_ -{ - //u1Byte Rate; - u1Byte DataRate; - u1Byte StationID; - BOOLEAN bPacketMatchBSSID; - BOOLEAN bPacketToSelf; - BOOLEAN bPacketBeacon; - BOOLEAN bToSelf; -}ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T; +struct _odm_per_pkt_info_ { + u8 data_rate; + u8 station_id; + boolean is_packet_match_bssid; + boolean is_packet_to_self; + boolean is_packet_beacon; + boolean is_to_self; + u8 ppdu_cnt; +}; -typedef struct _ODM_Phy_Dbg_Info_ -{ - //ODM Write,debug info - s1Byte RxSNRdB[4]; - u4Byte NumQryPhyStatus; - u4Byte NumQryPhyStatusCCK; - u4Byte NumQryPhyStatusOFDM; +struct _odm_phy_dbg_info_ { + /*ODM Write,debug info*/ + s8 rx_snr_db[4]; + u32 num_qry_phy_status; + u32 num_qry_phy_status_cck; + u32 num_qry_phy_status_ofdm; #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u4Byte NumQryMuPkt; - u4Byte NumQryBfPkt; - u4Byte NumQryMuVhtPkt[40]; - u4Byte NumQryVhtPkt[40]; + u32 num_qry_mu_pkt; + u32 num_qry_bf_pkt; + u32 num_qry_mu_vht_pkt[40]; + boolean is_ldpc_pkt; + boolean is_stbc_pkt; + u8 num_of_ppdu[4]; + u8 gid_num[4]; #endif - u1Byte NumQryBeaconPkt; - //Others - s4Byte RxEVM[4]; - -}ODM_PHY_DBG_INFO_T; - - -typedef struct _ODM_Mac_Status_Info_ -{ - u1Byte test; + u8 num_qry_beacon_pkt; + /* Others */ + s32 rx_evm[4]; + + u16 num_qry_legacy_pkt[12]; + u16 num_qry_ht_pkt[32]; + u8 ht_pkt_not_zero; + #if ODM_IC_11AC_SERIES_SUPPORT + u16 num_qry_vht_pkt[40]; + u8 vht_pkt_not_zero; + #endif -}ODM_MAC_INFO; - -// -// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T -// Please declare below ODM relative info in your STA info structure. -// -#if 1 -typedef struct _ODM_STA_INFO{ - // Driver Write - BOOLEAN bUsed; // record the sta status link or not? - //u1Byte WirelessMode; // - u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E - - // ODM Write - //1 PHY_STATUS_INFO - u1Byte RSSI_Path[4]; // - u1Byte RSSI_Ave; - u1Byte RXEVM[4]; - u1Byte RXSNR[4]; - - // ODM Write - //1 TX_INFO (may changed by IC) - //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. -#if 0 - u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit - u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit - u1Byte ANTSEL_C; //only in Jagar: 4bit - u1Byte ANTSEL_D; //only in Jagar: 4bit - u1Byte TX_ANTL; //not in Jagar: 2bit - u1Byte TX_ANT_HT; //not in Jagar: 2bit - u1Byte TX_ANT_CCK; //not in Jagar: 2bit - u1Byte TXAGC_A; //not in Jagar: 4bit - u1Byte TXAGC_B; //not in Jagar: 4bit - u1Byte TXPWR_OFFSET; //only in Jagar: 3bit - u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK -#endif - - // - // Please use compile flag to disabe the strcutrue for other IC except 88E. - // Move To lower layer. - // - // ODM Write Wilson will handle this part(said by Luke.Lee) - //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer. -#if 0 - //1 For 88E RA (don't redefine the naming) - u1Byte rate_id; - u1Byte rate_SGI; - u1Byte rssi_sta_ra; - u1Byte SGI_enable; - u1Byte Decision_rate; - u1Byte Pre_rate; - u1Byte Active; - - // Driver write Wilson handle. - //1 TX_RPT (don't redefine the naming) - u2Byte RTY[4]; // ??? - u2Byte TOTAL; // ??? - u2Byte DROP; // ??? - // - // Please use compile flag to disabe the strcutrue for other IC except 88E. - // -#endif + u8 rssi_cck_avg; + u32 rssi_cck_sum; + u32 rssi_cck_cnt; + u8 rssi_ofdm_avg; + u32 rssi_ofdm_sum; + u32 rssi_ofdm_cnt; + u8 rssi_1ss_avg; + u32 rssi_1ss_sum; + u32 rssi_1ss_cnt; + u8 rssi_2ss_avg[2]; + u32 rssi_2ss_sum[2]; + u32 rssi_2ss_cnt; + u8 rssi_3ss_avg[3]; + u32 rssi_3ss_sum[3]; + u32 rssi_3ss_cnt; + u8 rssi_4ss_avg[4]; + u32 rssi_4ss_sum[4]; + u32 rssi_4ss_cnt; -}ODM_STA_INFO_T, *PODM_STA_INFO_T; -#endif +}; -// -// 2011/10/20 MH Define Common info enum for all team. -// -typedef enum _ODM_Common_Info_Definition -{ -//-------------REMOVED CASE-----------// - //ODM_CMNINFO_CCK_HP, - //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? - //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E - //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E -//-------------REMOVED CASE-----------// - - // - // Fixed value: - // - - //-----------HOOK BEFORE REG INIT-----------// +enum odm_cmninfo_e { + /*Fixed value*/ + /*-----------HOOK BEFORE REG INIT-----------*/ ODM_CMNINFO_PLATFORM = 0, - ODM_CMNINFO_ABILITY, // ODM_ABILITY_E - ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E + ODM_CMNINFO_ABILITY, + ODM_CMNINFO_INTERFACE, ODM_CMNINFO_MP_TEST_CHIP, - ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E - ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E - ODM_CMNINFO_FAB_VER, // ODM_FAB_E - ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E? - ODM_CMNINFO_RFE_TYPE, - ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E + ODM_CMNINFO_IC_TYPE, + ODM_CMNINFO_CUT_VER, + ODM_CMNINFO_FAB_VER, + ODM_CMNINFO_RF_TYPE, + ODM_CMNINFO_RFE_TYPE, + ODM_CMNINFO_DPK_EN, + ODM_CMNINFO_BOARD_TYPE, ODM_CMNINFO_PACKAGE_TYPE, - ODM_CMNINFO_EXT_LNA, // TRUE - ODM_CMNINFO_5G_EXT_LNA, + ODM_CMNINFO_EXT_LNA, + ODM_CMNINFO_5G_EXT_LNA, ODM_CMNINFO_EXT_PA, ODM_CMNINFO_5G_EXT_PA, ODM_CMNINFO_GPA, @@ -381,7 +287,7 @@ typedef enum _ODM_Common_Info_Definition ODM_CMNINFO_ALNA, ODM_CMNINFO_EXT_TRSW, ODM_CMNINFO_EXT_LNA_GAIN, - ODM_CMNINFO_PATCH_ID, //CUSTOMER ID + ODM_CMNINFO_PATCH_ID, ODM_CMNINFO_BINHCT_TEST, ODM_CMNINFO_BWIFI_TEST, ODM_CMNINFO_SMART_CONCURRENT, @@ -397,36 +303,40 @@ typedef enum _ODM_Common_Info_Definition ODM_CMNINFO_SOUNDING_SEQ, ODM_CMNINFO_REGRFKFREEENABLE, ODM_CMNINFO_RFKFREEENABLE, - //-----------HOOK BEFORE REG INIT-----------// - - - // - // Dynamic value: - // -//--------- POINTER REFERENCE-----------// - ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E + ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, + ODM_CMNINFO_EFUSE0X3D8, + ODM_CMNINFO_EFUSE0X3D7, + ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING, + ODM_CMNINFO_HP_HWID, + ODM_CMNINFO_ADVANCE_OTA, + /*-----------HOOK BEFORE REG INIT-----------*/ + + /*Dynamic value:*/ + + /*--------- POINTER REFERENCE-----------*/ + ODM_CMNINFO_MAC_PHY_MODE, ODM_CMNINFO_TX_UNI, ODM_CMNINFO_RX_UNI, - ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E - ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E - ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E - ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E - ODM_CMNINFO_BW, // ODM_BW_E + ODM_CMNINFO_WM_MODE, + ODM_CMNINFO_BAND, + ODM_CMNINFO_SEC_CHNL_OFFSET, + ODM_CMNINFO_SEC_MODE, + ODM_CMNINFO_BW, ODM_CMNINFO_CHNL, ODM_CMNINFO_FORCED_RATE, - + ODM_CMNINFO_ANT_DIV, + ODM_CMNINFO_ADAPTIVITY, ODM_CMNINFO_DMSP_GET_VALUE, ODM_CMNINFO_BUDDY_ADAPTOR, ODM_CMNINFO_DMSP_IS_MASTER, ODM_CMNINFO_SCAN, ODM_CMNINFO_POWER_SAVING, - ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E + ODM_CMNINFO_ONE_PATH_CCA, ODM_CMNINFO_DRV_STOP, ODM_CMNINFO_PNP_IN, ODM_CMNINFO_INIT_ON, ODM_CMNINFO_ANT_TEST, ODM_CMNINFO_NET_CLOSED, - //ODM_CMNINFO_RTSTA_AID, // For win driver only? ODM_CMNINFO_FORCED_IGI_LB, ODM_CMNINFO_P2P_LINK, ODM_CMNINFO_FCS_MODE, @@ -434,659 +344,631 @@ typedef enum _ODM_Common_Info_Definition ODM_CMNINFO_RFDEFAULTPATH, ODM_CMNINFO_DFS_MASTER_ENABLE, ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, -//--------- POINTER REFERENCE-----------// + ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA, + ODM_CMNINFO_SOFT_AP_MODE, + ODM_CMNINFO_MP_MODE, + /*--------- POINTER REFERENCE-----------*/ -//------------CALL BY VALUE-------------// + /*------------CALL BY VALUE-------------*/ ODM_CMNINFO_WIFI_DIRECT, ODM_CMNINFO_WIFI_DISPLAY, - ODM_CMNINFO_LINK_IN_PROGRESS, + ODM_CMNINFO_LINK_IN_PROGRESS, ODM_CMNINFO_LINK, + ODM_CMNINFO_CMW500LINK, + ODM_CMNINFO_LPSPG, ODM_CMNINFO_STATION_STATE, ODM_CMNINFO_RSSI_MIN, - ODM_CMNINFO_DBG_COMP, /* u4SByte*/ - ODM_CMNINFO_DBG_LEVEL, /* u4Byte*/ - ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u1Byte*/ - ODM_CMNINFO_RA_THRESHOLD_LOW, /* u1Byte*/ - ODM_CMNINFO_RF_ANTENNA_TYPE, /* u1Byte*/ + ODM_CMNINFO_RSSI_MIN_BY_PATH, + ODM_CMNINFO_DBG_COMP, + ODM_CMNINFO_DBG_LEVEL, + ODM_CMNINFO_RA_THRESHOLD_HIGH, + ODM_CMNINFO_RA_THRESHOLD_LOW, + ODM_CMNINFO_RF_ANTENNA_TYPE, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, ODM_CMNINFO_BE_FIX_TX_ANT, ODM_CMNINFO_BT_ENABLED, ODM_CMNINFO_BT_HS_CONNECT_PROCESS, ODM_CMNINFO_BT_HS_RSSI, ODM_CMNINFO_BT_OPERATION, - ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not + ODM_CMNINFO_BT_LIMITED_DIG, ODM_CMNINFO_BT_DIG, - ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil + ODM_CMNINFO_BT_BUSY, ODM_CMNINFO_BT_DISABLE_EDCA, -#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 -#ifdef UNIVERSAL_REPEATER - ODM_CMNINFO_VXD_LINK, -#endif -#endif ODM_CMNINFO_AP_TOTAL_NUM, ODM_CMNINFO_POWER_TRAINING, ODM_CMNINFO_DFS_REGION_DOMAIN, -//------------CALL BY VALUE-------------// + /*------------CALL BY VALUE-------------*/ - // - // Dynamic ptr array hook itms. - // + /*Dynamic ptr array hook itms.*/ ODM_CMNINFO_STA_STATUS, - ODM_CMNINFO_PHY_STATUS, - ODM_CMNINFO_MAC_STATUS, - ODM_CMNINFO_MAX, +}; + -}ODM_CMNINFO_E; +enum phydm_info_query_e { + PHYDM_INFO_FA_OFDM, + PHYDM_INFO_FA_CCK, + PHYDM_INFO_FA_TOTAL, + PHYDM_INFO_CCA_OFDM, + PHYDM_INFO_CCA_CCK, + PHYDM_INFO_CCA_ALL, + PHYDM_INFO_CRC32_OK_VHT, + PHYDM_INFO_CRC32_OK_HT, + PHYDM_INFO_CRC32_OK_LEGACY, + PHYDM_INFO_CRC32_OK_CCK, + PHYDM_INFO_CRC32_ERROR_VHT, + PHYDM_INFO_CRC32_ERROR_HT, + PHYDM_INFO_CRC32_ERROR_LEGACY, + PHYDM_INFO_CRC32_ERROR_CCK, + PHYDM_INFO_EDCCA_FLAG, + PHYDM_INFO_OFDM_ENABLE, + PHYDM_INFO_CCK_ENABLE, + PHYDM_INFO_CRC32_OK_HT_AGG, + PHYDM_INFO_CRC32_ERROR_HT_AGG, + PHYDM_INFO_DBG_PORT_0 +}; -typedef enum _PHYDM_API_Definition { +enum phydm_api_e { PHYDM_API_NBI = 1, PHYDM_API_CSI_MASK, - -} PHYDM_API_E; - - -// -// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY -// -typedef enum _ODM_Support_Ability_Definition -{ - // - // BB ODM section BIT 0-19 - // - ODM_BB_DIG = BIT0, - ODM_BB_RA_MASK = BIT1, - ODM_BB_DYNAMIC_TXPWR = BIT2, - ODM_BB_FA_CNT = BIT3, - ODM_BB_RSSI_MONITOR = BIT4, - ODM_BB_CCK_PD = BIT5, - ODM_BB_ANT_DIV = BIT6, - ODM_BB_PWR_TRAIN = BIT8, - ODM_BB_RATE_ADAPTIVE = BIT9, - ODM_BB_PATH_DIV = BIT10, - ODM_BB_ADAPTIVITY = BIT13, - ODM_BB_CFO_TRACKING = BIT14, - ODM_BB_NHM_CNT = BIT15, - ODM_BB_PRIMARY_CCA = BIT16, - ODM_BB_TXBF = BIT17, - ODM_BB_DYNAMIC_ARFR = BIT18, - - // - // MAC DM section BIT 20-23 - // - ODM_MAC_EDCA_TURBO = BIT20, - ODM_MAC_EARLY_MODE = BIT21, - - // - // RF ODM section BIT 24-31 - // - ODM_RF_TX_PWR_TRACK = BIT24, - ODM_RF_RX_GAIN_TRACK = BIT25, - ODM_RF_CALIBRATION = BIT26, - -}ODM_ABILITY_E; +}; +enum odm_ability_e { + + ODM_BB_DIG = BIT(0), + ODM_BB_RA_MASK = BIT(1), + ODM_BB_DYNAMIC_TXPWR = BIT(2), + ODM_BB_FA_CNT = BIT(3), + ODM_BB_RSSI_MONITOR = BIT(4), + ODM_BB_CCK_PD = BIT(5), + ODM_BB_ANT_DIV = BIT(6), + /*BIT(7),*/ + ODM_BB_PWR_TRAIN = BIT(8), + ODM_BB_RATE_ADAPTIVE = BIT(9), + ODM_BB_PATH_DIV = BIT(10), + /*BIT(11),*/ + /*BIT(12),*/ + ODM_BB_ADAPTIVITY = BIT(13), + ODM_BB_CFO_TRACKING = BIT(14), + ODM_BB_NHM_CNT = BIT(15), + ODM_BB_PRIMARY_CCA = BIT(16), + ODM_BB_TXBF = BIT(17), + ODM_BB_DYNAMIC_ARFR = BIT(18), + ODM_BB_DYNAMIC_PSDTOOL = BIT(19), + ODM_MAC_EDCA_TURBO = BIT(20), + ODM_BB_DYNAMIC_RX_PATH = BIT(21), +}; -// ODM_CMNINFO_ONE_PATH_CCA -typedef enum tag_CCA_Path -{ +/*ODM_CMNINFO_ONE_PATH_CCA*/ +enum odm_cca_path_e { ODM_CCA_2R = 0, ODM_CCA_1R_A = 1, ODM_CCA_1R_B = 2, -}ODM_CCA_PATH_E; +}; -typedef enum CCA_PATHDIV_EN { - CCA_PATHDIV_DISABLE = 0, - CCA_PATHDIV_ENABLE = 1, +enum cca_pathdiv_en_e { + CCA_PATHDIV_DISABLE = 0, + CCA_PATHDIV_ENABLE = 1, -} CCA_PATHDIV_EN_E; +}; +enum phydm_offload_ability { + PHYDM_PHY_PARAM_OFFLOAD = BIT(0), + PHYDM_RF_IQK_OFFLOAD = BIT(1), +}; -typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{ - PHY_REG_PG_RELATIVE_VALUE = 0, - PHY_REG_PG_EXACT_VALUE = 1 -} PHY_REG_PG_TYPE; -// -// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. -// -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if (RT_PLATFORM != PLATFORM_LINUX) -typedef -#endif - -struct DM_Out_Source_Dynamic_Mechanism_Structure -#else// for AP,ADSL,CE Team -typedef struct DM_Out_Source_Dynamic_Mechanism_Structure +enum phy_reg_pg_type { + PHY_REG_PG_RELATIVE_VALUE = 0, + PHY_REG_PG_EXACT_VALUE = 1 +}; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (RT_PLATFORM != PLATFORM_LINUX) + typedef + #endif + + struct PHY_DM_STRUCT +#else/*for AP,ADSL,CE Team*/ + struct PHY_DM_STRUCT #endif { - // Add for different team use temporarily - // - PADAPTER Adapter; // For CE/NIC team - prtl8192cd_priv priv; // For AP/ADSL team - // WHen you use Adapter or priv pointer, you must make sure the pointer is ready. - BOOLEAN odm_ready; - -#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - rtl8192cd_priv fake_priv; -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - // ADSL_AP_BUILD_WORKAROUND - ADAPTER fake_adapter; -#endif + /*Add for different team use temporarily*/ + struct _ADAPTER *adapter; /*For CE/NIC team*/ + struct rtl8192cd_priv *priv; /*For AP/ADSL team*/ + /*WHen you use adapter or priv pointer, you must make sure the pointer is ready.*/ + boolean odm_ready; + enum phy_reg_pg_type phy_reg_pg_value_type; + u8 phy_reg_pg_version; + u32 debug_components; + u32 fw_debug_components; + u32 debug_level; + u32 num_qry_phy_status_all; /*CCK + OFDM*/ + u32 last_num_qry_phy_status_all; + u32 rx_pwdb_ave; + u8 times_2g; + boolean is_init_hw_info_by_rfe; + + /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ + boolean is_cck_high_power; + u8 rf_path_rx_enable; + /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ + + /* COMMON INFORMATION */ + + /*Init value*/ + /*-----------HOOK BEFORE REG INIT-----------*/ + + u8 support_platform;/*PHYDM Platform info WIN/AP/CE = 1/2/3 */ + u8 normal_rx_path; + u32 support_ability; /*PHYDM function Supportability*/ + u8 support_interface;/*PHYDM PCIE/USB/SDIO = 1/2/3*/ + u32 support_ic_type; /*PHYDM supported IC*/ + u8 cut_version; /*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ + u8 fab_version; /*Fab version TSMC/UMC = 0/1*/ + u8 rf_type; /*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/ + u8 rfe_type; + u8 board_type; + u8 package_type; + u16 type_glna; + u16 type_gpa; + u16 type_alna; + u16 type_apa; + u8 ext_lna; /*with 2G external LNA NO/Yes = 0/1*/ + u8 ext_lna_5g; /*with 5G external LNA NO/Yes = 0/1*/ + u8 ext_pa; /*with 2G external PNA NO/Yes = 0/1*/ + u8 ext_pa_5g; /*with 5G external PNA NO/Yes = 0/1*/ + u8 efuse0x3d7; /*with Efuse number*/ + u8 efuse0x3d8; + u8 ext_trsw; /*with external TRSW NO/Yes = 0/1*/ + u8 ext_lna_gain; /*gain of external lna*/ + u8 patch_id; /*Customer ID*/ + boolean is_in_hct_test; + u8 wifi_test; + boolean is_dual_mac_smart_concurrent; + u32 bk_support_ability; /*SD4 only*/ + u8 with_extenal_ant_switch; + boolean config_bbrf; + u8 odm_regulation_2_4g; + u8 odm_regulation_5g; + u8 iqk_fw_offload; + boolean cck_new_agc; + u8 phydm_period; + u32 phydm_sys_up_time; + u8 num_rf_path; + u32 soft_ap_special_setting; + u8 rfe_hwsetting_band; + u8 p_advance_ota; + u8 u1_byte_temp; + boolean is_hp_hw_id; + boolean BOOLEAN_temp; + u8 is_nbi_enable; + u16 fw_offload_ability; +/*-----------HOOK BEFORE REG INIT-----------*/ +/*===========================================================*/ +/*====[ CALL BY Reference ]=========================================*/ +/*===========================================================*/ - PHY_REG_PG_TYPE PhyRegPgValueType; - u1Byte PhyRegPgVersion; - - u4Byte DebugComponents; - u4Byte DebugLevel; + struct _ADAPTER *PADAPTER_temp; + + u8 *p_mac_phy_mode; /*MAC PHY mode SMSP/DMSP/DMDP = 0/1/2*/ + u64 *p_num_tx_bytes_unicast; /*TX Unicast byte count*/ + u64 *p_num_rx_bytes_unicast; /*RX Unicast byte count*/ + u8 *p_wireless_mode; /*Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3*/ + u8 *p_band_type; /*Frequence band 2.4G/5G = 0/1*/ + u8 *p_sec_ch_offset; /*Secondary channel offset don't_care/below/above = 0/1/2*/ + u8 *p_security; /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/ + u8 *p_band_width; /*BW info 20M/40M/80M = 0/1/2*/ + u8 *p_channel; /*central channel number*/ + boolean *p_is_get_value_from_other_mac; /*Common info for 92D DMSP*/ + struct _ADAPTER **p_buddy_adapter; + boolean *p_is_master_of_dmsp; /* MAC0: master, MAC1: slave */ + boolean *p_is_scan_in_process; /*Common info for status*/ + boolean *p_is_power_saving; + u8 *p_one_path_cca; /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path_e.*/ + u8 *p_antenna_test; + boolean *p_is_net_closed; + u8 *pu1_forced_igi_lb; + boolean *p_is_fcs_mode_enable; + /*--------- For 8723B IQK-------------------------------------*/ + boolean *p_is_1_antenna; + u8 *p_rf_default_path; /* 0:S1, 1:S0 */ + /*-----------------------------------------------------------*/ + + u16 *p_forced_data_rate; + u8 *p_enable_antdiv; + u8 *p_enable_adaptivity; + u8 *hub_usb_mode; /*1: USB 2.0, 2: USB 3.0*/ + boolean *p_is_fw_dw_rsvd_page_in_progress; + u32 *p_current_tx_tp; + u32 *p_current_rx_tp; + u8 *p_sounding_seq; + u32 *p_soft_ap_mode; + u8 *p_mp_mode; + +/*===========================================================*/ +/*====[ CALL BY VALUE ]===========================================*/ +/*===========================================================*/ - u4Byte NumQryPhyStatusAll; //CCK + OFDM - u4Byte LastNumQryPhyStatusAll; - u4Byte RxPWDBAve; - BOOLEAN MPDIG_2G; //off MPDIG - u1Byte Times_2G; - BOOLEAN bInitHwInfoByRfe; + boolean is_link_in_process; + boolean is_wifi_direct; + boolean is_wifi_display; + boolean is_linked; + boolean bLinkedcmw500; + boolean is_in_lps_pg; + boolean bsta_state; + u8 rssi_min; + u8 rssi_min_by_path; + boolean is_mp_chip; + boolean is_one_entry_only; + u32 one_entry_macid; + u32 one_entry_tp; + u32 pre_one_entry_tp; + u8 pre_number_linked_client; + u8 number_linked_client; + u8 pre_number_active_client; + u8 number_active_client; -//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// - BOOLEAN bCckHighPower; - u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE - u1Byte ControlChannel; -//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// - -//--------REMOVED COMMON INFO----------// - //u1Byte PseudoMacPhyMode; - //BOOLEAN *BTCoexist; - //BOOLEAN PseudoBtCoexist; - //u1Byte OPMode; - //BOOLEAN bAPMode; - //BOOLEAN bClientMode; - //BOOLEAN bAdHocMode; - //BOOLEAN bSlaveOfDMSP; -//--------REMOVED COMMON INFO----------// - - -//1 COMMON INFORMATION - - // - // Init Value - // -//-----------HOOK BEFORE REG INIT-----------// - // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 - u1Byte SupportPlatform; - // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K - u4Byte SupportAbility; - // ODM PCIE/USB/SDIO = 1/2/3 - u1Byte SupportInterface; - // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... - u4Byte SupportICType; - // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... - u1Byte CutVersion; - // Fab Version TSMC/UMC = 0/1 - u1Byte FabVersion; - // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... - u1Byte RFType; - u1Byte RFEType; - // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... - u1Byte BoardType; - u1Byte PackageType; - u2Byte TypeGLNA; - u2Byte TypeGPA; - u2Byte TypeALNA; - u2Byte TypeAPA; - // with external LNA NO/Yes = 0/1 - u1Byte ExtLNA; // 2G - u1Byte ExtLNA5G; //5G - // with external PA NO/Yes = 0/1 - u1Byte ExtPA; // 2G - u1Byte ExtPA5G; //5G - // with external TRSW NO/Yes = 0/1 - u1Byte ExtTRSW; - u1Byte ExtLNAGain; // 2G - u1Byte PatchID; //Customer ID - BOOLEAN bInHctTest; - u1Byte WIFITest; - - BOOLEAN bDualMacSmartConcurrent; - u4Byte BK_SupportAbility; - u1Byte AntDivType; - u1Byte with_extenal_ant_switch; - BOOLEAN ConfigBBRF; - u1Byte odm_Regulation2_4G; - u1Byte odm_Regulation5G; - u1Byte IQKFWOffload; - BOOLEAN cck_new_agc; -//-----------HOOK BEFORE REG INIT-----------// - - // - // Dynamic Value - // -//--------- POINTER REFERENCE-----------// - - u1Byte u1Byte_temp; - BOOLEAN BOOLEAN_temp; - PADAPTER PADAPTER_temp; + /*---Common info for BTDM-------------------------------------*/ + boolean is_bt_enabled; /*BT is enabled*/ + boolean is_bt_connect_process; /*BT HS is under connection progress.*/ + u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/ + boolean is_bt_hs_operation; /*BT HS mode is under progress*/ + u8 bt_hs_dig_val; /*use BT rssi to decide the DIG value*/ + boolean is_bt_disable_edca_turbo; /*Under some condition, don't enable the EDCA Turbo*/ + boolean is_bt_busy; /*BT is busy.*/ + boolean is_bt_limited_dig; /*BT is busy.*/ + boolean is_disable_phy_api; + /*-----------------------------------------------------------*/ + u8 RSSI_A; + u8 RSSI_B; + u8 RSSI_C; + u8 RSSI_D; + u64 RSSI_TRSW; + u64 RSSI_TRSW_H; + u64 RSSI_TRSW_L; + u64 RSSI_TRSW_iso; + u8 tx_ant_status; + u8 rx_ant_status; + u8 cck_lna_idx; + u8 cck_vga_idx; + u8 curr_station_id; + u8 ofdm_agc_idx[4]; + u8 rx_rate; + u8 rate_ss; + u8 tx_rate; + u8 linked_interval; + u8 pre_channel; + u32 txagc_offset_value_a; + boolean is_txagc_offset_positive_a; + u32 txagc_offset_value_b; + boolean is_txagc_offset_positive_b; + /*[traffic]*/ + u8 traffic_load; + u8 pre_traffic_load; + u32 tx_tp; + u32 rx_tp; + u32 total_tp; + u64 cur_tx_ok_cnt; + u64 cur_rx_ok_cnt; + u64 last_tx_ok_cnt; + u64 last_rx_ok_cnt; + u16 consecutive_idlel_time; /*unit: second*/ + /*---------------------------*/ + u32 bb_swing_offset_a; + boolean is_bb_swing_offset_positive_a; + u32 bb_swing_offset_b; + boolean is_bb_swing_offset_positive_b; + + /*[DIG]*/ + boolean MPDIG_2G; /*off MPDIG*/ + u8 igi_lower_bound; + u8 igi_upper_bound; + u8 dm_dig_max_TH; + u8 dm_dig_min_TH; + boolean is_dm_initial_gain_enable; + /*---------------------------*/ + + /*[AntDiv]*/ + u8 ant_div_type; + u8 antdiv_rssi; + u8 fat_comb_a; + u8 fat_comb_b; + u8 antdiv_intvl; + u8 ant_type; + u8 pre_ant_type; + u8 antdiv_period; + u8 evm_antdiv_period; + u8 antdiv_select; + u8 antdiv_train_num;/*training time for each antenna in EVM method*/ + u8 stop_antdiv_rssi_th; + u16 stop_antdiv_tp_diff_th; + u16 stop_antdiv_tp_th; + u8 antdiv_tp_period; + u16 tp_active_th; + u8 tp_active_occur; + u8 path_select; + u8 antdiv_evm_en; + u8 bdc_holdstate; + /*---------------------------*/ - // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 - u1Byte *pMacPhyMode; - //TX Unicast byte count - u8Byte *pNumTxBytesUnicast; - //RX Unicast byte count - u8Byte *pNumRxBytesUnicast; - // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 - u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E - // Frequence band 2.4G/5G = 0/1 - u1Byte *pBandType; - // Secondary channel offset don't_care/below/above = 0/1/2 - u1Byte *pSecChOffset; - // Security mode Open/WEP/AES/TKIP = 0/1/2/3 - u1Byte *pSecurity; - // BW info 20M/40M/80M = 0/1/2 - u1Byte *pBandWidth; - // Central channel location Ch1/Ch2/.... - u1Byte *pChannel; //central channel number - BOOLEAN DPK_Done; - // Common info for 92D DMSP + u8 ndpa_period; + boolean h2c_rarpt_connect; + boolean cck_agc_report_type; + u8 print_agc; + u8 la_mode; + /*---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/ + u8 current_rf_set_8821c; + u8 default_rf_set_8821c; + u8 current_ant_num_8821c; + u8 default_ant_num_8821c; + /*-----------------------------------------------------------*/ + /*---For Adaptivtiy---------------------------------------------*/ + u16 nhm_cnt_0; + u16 nhm_cnt_1; + s8 TH_L2H_default; + s8 th_edcca_hl_diff_default; + s8 th_l2h_ini; + s8 th_edcca_hl_diff; + s8 th_l2h_ini_mode2; + s8 th_edcca_hl_diff_mode2; + boolean carrier_sense_enable; + u8 adaptivity_igi_upper; + boolean adaptivity_flag; + u8 dc_backoff; + boolean adaptivity_enable; + u8 ap_total_num; + boolean edcca_enable; + /*-----------------------------------------------------------*/ - BOOLEAN *pbGetValueFromOtherMac; - PADAPTER *pBuddyAdapter; - BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave - // Common info for Status - BOOLEAN *pbScanInProcess; - BOOLEAN *pbPowerSaving; - // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. - u1Byte *pOnePathCCA; - //pMgntInfo->AntennaTest - u1Byte *pAntennaTest; - BOOLEAN *pbNet_closed; - //u1Byte *pAidMap; - u1Byte *pu1ForcedIgiLb; - BOOLEAN *pIsFcsModeEnable; -/*--------- For 8723B IQK-----------*/ - BOOLEAN *pIs1Antenna; - u1Byte *pRFDefaultPath; - // 0:S1, 1:S0 + u8 pre_dbg_priority; + u8 nbi_set_result; + u8 csi_set_result; + u8 csi_set_result_2; + + u8 c2h_cmd_start; + u8 fw_debug_trace[60]; + u8 pre_c2h_seq; + boolean fw_buff_is_enpty; + u32 data_frame_num; + + /*--- for noise detection ---------------------------------------*/ + boolean is_noisy_state; + boolean noisy_decision; /*b_noisy*/ + boolean pre_b_noisy; + u32 noisy_decision_smooth; + /*-----------------------------------------------------------*/ -//--------- POINTER REFERENCE-----------// - pu2Byte pForcedDataRate; - pu1Byte HubUsbMode; - BOOLEAN *pbFwDwRsvdPageInProgress; - u4Byte *pCurrentTxTP; - u4Byte *pCurrentRxTP; - u1Byte *pSoundingSeq; -//------------CALL BY VALUE-------------// - BOOLEAN bLinkInProcess; - BOOLEAN bWIFI_Direct; - BOOLEAN bWIFI_Display; - BOOLEAN bLinked; - BOOLEAN bsta_state; -#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 -#ifdef UNIVERSAL_REPEATER - BOOLEAN VXD_bLinked; + boolean is_disable_dym_ecs; + boolean is_disable_dym_ant_weighting; + struct sta_info *p_odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];/*_ODM_STA_INFO, 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??*/ + struct cmn_sta_info *p_phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; + u16 platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/* platform_macid_table[platform_macid] = phydm_macid */ + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + s32 accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM]; #endif -#endif // for repeater mode add by YuChen 2014.06.23 - u1Byte RSSI_Min; - u1Byte InterfaceIndex; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/ - BOOLEAN bIsMPChip; - BOOLEAN bOneEntryOnly; - BOOLEAN mp_mode; - u4Byte OneEntry_MACID; - u1Byte pre_number_linked_client; - u1Byte number_linked_client; - u1Byte pre_number_active_client; - u1Byte number_active_client; - // Common info for BTDM - BOOLEAN bBtEnabled; // BT is enabled - BOOLEAN bBtConnectProcess; // BT HS is under connection progress. - u1Byte btHsRssi; // BT HS mode wifi rssi value. - BOOLEAN bBtHsOperation; // BT HS mode is under progress - u1Byte btHsDigVal; // use BT rssi to decide the DIG value - BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo - BOOLEAN bBtBusy; // BT is busy. - BOOLEAN bBtLimitedDig; // BT is busy. - BOOLEAN bDisablePhyApi; -//------------CALL BY VALUE-------------// - u1Byte RSSI_A; - u1Byte RSSI_B; - u1Byte RSSI_C; - u1Byte RSSI_D; - u8Byte RSSI_TRSW; - u8Byte RSSI_TRSW_H; - u8Byte RSSI_TRSW_L; - u8Byte RSSI_TRSW_iso; - u1Byte TXAntStatus; - u1Byte RXAntStatus; - u1Byte cck_lna_idx; - u1Byte cck_vga_idx; - u1Byte curr_station_id; - u1Byte ofdm_agc_idx[4]; - - u1Byte RxRate; - BOOLEAN bNoisyState; - u1Byte TxRate; - u1Byte LinkedInterval; - u1Byte preChannel; - u4Byte TxagcOffsetValueA; - BOOLEAN IsTxagcOffsetPositiveA; - u4Byte TxagcOffsetValueB; - BOOLEAN IsTxagcOffsetPositiveB; - u4Byte tx_tp; - u4Byte rx_tp; - u4Byte total_tp; - u8Byte curTxOkCnt; - u8Byte curRxOkCnt; - u8Byte lastTxOkCnt; - u8Byte lastRxOkCnt; - u4Byte BbSwingOffsetA; - BOOLEAN IsBbSwingOffsetPositiveA; - u4Byte BbSwingOffsetB; - BOOLEAN IsBbSwingOffsetPositiveB; - u1Byte IGI_LowerBound; - u1Byte IGI_UpperBound; - u1Byte antdiv_rssi; - u1Byte fat_comb_a; - u1Byte fat_comb_b; - u1Byte antdiv_intvl; - u1Byte AntType; - u1Byte pre_AntType; - u1Byte antdiv_period; - u1Byte evm_antdiv_period; - u1Byte antdiv_select; - u1Byte path_select; - u1Byte antdiv_evm_en; - u1Byte bdc_holdstate; - u1Byte NdpaPeriod; - BOOLEAN H2C_RARpt_connect; - BOOLEAN cck_agc_report_type; - - u1Byte dm_dig_max_TH; - u1Byte dm_dig_min_TH; - u1Byte print_agc; - u1Byte TrafficLoad; - u1Byte pre_TrafficLoad; - - - //For Adaptivtiy - u2Byte NHM_cnt_0; - u2Byte NHM_cnt_1; - s1Byte TH_L2H_default; - s1Byte TH_EDCCA_HL_diff_default; - s1Byte TH_L2H_ini; - s1Byte TH_EDCCA_HL_diff; - s1Byte TH_L2H_ini_mode2; - s1Byte TH_EDCCA_HL_diff_mode2; - BOOLEAN Carrier_Sense_enable; - u1Byte Adaptivity_IGI_upper; - BOOLEAN adaptivity_flag; - u1Byte DCbackoff; - BOOLEAN Adaptivity_enable; - u1Byte APTotalNum; - BOOLEAN EDCCA_enable; - ADAPTIVITY_STATISTICS Adaptivity; - //For Adaptivtiy - u1Byte LastUSBHub; - u1Byte TxBfDataRate; - - u1Byte nbi_set_result; + +#if (RATE_ADAPTIVE_SUPPORT == 1) + u16 currmin_rpt_time; + struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM]; + /*Use mac_id as array index. STA mac_id=0, VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/ +#endif + boolean ra_support88e; /*2012/02/14 MH Add to share 88E ra with other SW team.We need to colelct all support abilit to a proper area.*/ + boolean *p_is_driver_stopped; + boolean *p_is_driver_is_going_to_pnp_set_power_sleep; + boolean *pinit_adpt_in_progress; + boolean is_user_assign_level; + u8 RSSI_BT; /*come from BT*/ + + /*---PSD Relative ---------------------------------------------*/ + boolean is_psd_in_process; + boolean is_psd_active; + /*-----------------------------------------------------------*/ - u1Byte c2h_cmd_start; - u1Byte fw_debug_trace[60]; - u1Byte pre_c2h_seq; - BOOLEAN fw_buff_is_enpty; - u4Byte data_frame_num; - - /*for noise detection*/ - BOOLEAN NoisyDecision; /*b_noisy*/ - BOOLEAN pre_b_noisy; - u4Byte NoisyDecision_Smooth; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM]; + u8 is_use_ra_mask; /*for rate adaptive, in fact, 88c/92c fw will handle this*/ + boolean bsomlenabled; /* for dynamic SoML control */ + boolean bhtstfenabled; /* for dynamic HTSTF gain control */ + u32 n_iqk_cnt; + u32 n_iqk_ok_cnt; + u32 n_iqk_fail_cnt; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + u8 force_power_training_state; /*Power Training*/ + boolean is_change_state; + u32 PT_score; + u64 ofdm_rx_cnt; + u64 cck_rx_cnt; #endif - // - //2 Define STA info. - // _ODM_STA_INFO - // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? - PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; - u2Byte platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; /* platform_macid_table[platform_macid] = phydm_macid */ -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - s4Byte AccumulatePWDB[ODM_ASSOCIATE_ENTRY_NUM]; + boolean is_disable_power_training; + u8 dynamic_tx_high_power_lvl; + u8 last_dtp_lvl; + u32 tx_agc_ofdm_18_6; + u8 rx_pkt_type; + +#ifdef CONFIG_PHYDM_DFS_MASTER + u8 dfs_region_domain; + u8 *dfs_master_enabled; + /*---phydm_radar_detect_with_dbg_parm start --------------------*/ + u8 radar_detect_dbg_parm_en; + u32 radar_detect_reg_918; + u32 radar_detect_reg_91c; + u32 radar_detect_reg_920; + u32 radar_detect_reg_924; + /*-----------------------------------------------------------*/ #endif -#if (RATE_ADAPTIVE_SUPPORT == 1) - u2Byte CurrminRptTime; - ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119 +/*=== PHYDM Timer ========================================== (start)*/ + + struct timer_list mpt_dig_timer; /*MPT DIG timer*/ + struct timer_list path_div_switch_timer; + struct timer_list cck_path_diversity_timer; /*2011.09.27 add for path Diversity*/ + struct timer_list fast_ant_training_timer; +#ifdef ODM_EVM_ENHANCE_ANTDIV + struct timer_list evm_fast_ant_training_timer; #endif - // - // 2012/02/14 MH Add to share 88E ra with other SW team. - // We need to colelct all support abilit to a proper area. - // - BOOLEAN RaSupport88E; + struct timer_list sbdcnt_timer; - // Define ........... - // Latest packet phy info (ODM write) - ODM_PHY_DBG_INFO_T PhyDbgInfo; - //PHY_INFO_88E PhyInfo; +/*=== PHYDM Workitem ======================================= (start)*/ - // Latest packet phy info (ODM write) - ODM_MAC_INFO *pMacInfo; - //MAC_INFO_88E MacInfo; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if USE_WORKITEM + RT_WORK_ITEM path_div_switch_workitem; + RT_WORK_ITEM cck_path_diversity_workitem; + RT_WORK_ITEM fast_ant_training_workitem; + RT_WORK_ITEM mpt_dig_workitem; + RT_WORK_ITEM ra_rpt_workitem; + RT_WORK_ITEM sbdcnt_workitem; +#endif +#endif - // Different Team independt structure?? - // - //TX_RTP_CMN TX_retrpo; - //TX_RTP_88E TX_retrpo; - //TX_RTP_8195 TX_retrpo; +/*=== PHYDM Structure ======================================== (start)*/ + struct _ADAPTIVITY_STATISTICS adaptivity; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) + struct _ODM_NOISE_MONITOR_ noise_level; +#endif - // - //ODM Structure - // + struct _odm_phy_dbg_info_ phy_dbg_info; #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - BDC_T DM_BdcTable; - #endif - - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - SAT_T dm_sat_table; - #endif - -#endif - FAT_T DM_FatTable; - DIG_T DM_DigTable; - - PS_T DM_PSTable; - Pri_CCA_T DM_PriCCA; - RA_T DM_RA_Table; - FALSE_ALARM_STATISTICS FalseAlmCnt; - FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; - SWAT_T DM_SWAT_Table; - CFO_TRACKING DM_CfoTrack; - ACS DM_ACS; - CCX_INFO DM_CCX_INFO; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - RT_ADCSMP adcsmp; + struct _BF_DIV_COEX_ dm_bdc_table; #endif -#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - IQK_INFO IQK_info; +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) + struct _SMART_ANTENNA_TRAINNING_ dm_sat_table; #endif -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - //Path Div Struct - PATHDIV_PARA pathIQK; #endif -#if(defined(CONFIG_PATH_DIVERSITY)) - PATHDIV_T DM_PathDiv; + struct _FAST_ANTENNA_TRAINNING_ dm_fat_table; + struct _dynamic_initial_gain_threshold_ dm_dig_table; + +#if (defined(CONFIG_BB_POWER_SAVING)) + struct _dynamic_power_saving dm_ps_table; +#endif + + struct _dynamic_primary_cca dm_pri_cca; + struct _rate_adaptive_table_ dm_ra_table; + struct _FALSE_ALARM_STATISTICS false_alm_cnt; + struct _FALSE_ALARM_STATISTICS flase_alm_cnt_buddy_adapter; + struct _sw_antenna_switch_ dm_swat_table; + struct _CFO_TRACKING_ dm_cfo_track; + struct _ACS_ dm_acs; + struct _CCX_INFO dm_ccx_info; + struct _hal_rf_ rf_table; /*for HALRF function*/ + struct _ODM_RATE_ADAPTIVE rate_adaptive; + struct odm_rf_calibration_structure rf_calibrate_info; + struct odm_power_trim_data power_trim_data; +#if (RTL8822B_SUPPORT == 1) + struct phydm_rtl8822b_struct phydm_rtl8822b; #endif +#if (CONFIG_PSD_TOOL == 1) + struct _PHYDM_PSD_ dm_psd_table; +#endif - EDCA_T DM_EDCA_Table; - u4Byte WMMEDCA_BE; - - // Copy from SD4 structure - // - // ================================================== - // - - //common - //u1Byte DM_Type; - //u1Byte PSD_Report_RXHP[80]; // Add By Gary - //u1Byte PSD_func_flag; // Add By Gary - //for DIG - //u1Byte bDMInitialGainEnable; - //u1Byte binitialized; // for dm_initial_gain_Multi_STA use. - - BOOLEAN *pbDriverStopped; - BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; - BOOLEAN *pinit_adpt_in_progress; - - //PSD - BOOLEAN bUserAssignLevel; - u1Byte RSSI_BT; /*come from BT*/ - BOOLEAN bPSDinProcess; - BOOLEAN bPSDactive; - BOOLEAN bDMInitialGainEnable; - - //MPT DIG - RT_TIMER MPT_DIGTimer; - - //for rate adaptive, in fact, 88c/92c fw will handle this - u1Byte bUseRAMask; +#if (PHYDM_LA_MODE_SUPPORT == 1) + struct _RT_ADCSMP adcsmp; +#endif - ODM_RATE_ADAPTIVE RateAdaptive; - #if (defined(CONFIG_ANT_DETECTION)) - ANT_DETECTED_INFO AntDetectedInfo; /* Antenna detected information for RSSI tool*/ - #endif - ODM_RF_CAL_T RFCalibrateInfo; - u4Byte nIQK_Cnt; - u4Byte nIQK_OK_Cnt; - u4Byte nIQK_Fail_Cnt; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - // - // Power Training - // - u1Byte ForcePowerTrainingState; - BOOLEAN bChangeState; - u4Byte PT_score; - u8Byte OFDM_RX_Cnt; - u8Byte CCK_RX_Cnt; +#if (CONFIG_DYNAMIC_RX_PATH == 1) + struct _DYNAMIC_RX_PATH_ dm_drp_table; #endif - BOOLEAN bDisablePowerTraining; - u1Byte DynamicTxHighPowerLvl; - u1Byte LastDTPLvl; - u4Byte tx_agc_ofdm_18_6; - u1Byte rx_pkt_type; - - // - // ODM system resource. - // - - // ODM relative time. - RT_TIMER PathDivSwitchTimer; - //2011.09.27 add for Path Diversity - RT_TIMER CCKPathDiversityTimer; - RT_TIMER FastAntTrainingTimer; - #ifdef ODM_EVM_ENHANCE_ANTDIV - RT_TIMER EVM_FastAntTrainingTimer; - #endif - RT_TIMER sbdcnt_timer; - // ODM relative workitem. -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#if USE_WORKITEM - RT_WORK_ITEM PathDivSwitchWorkitem; - RT_WORK_ITEM CCKPathDiversityWorkitem; - RT_WORK_ITEM FastAntTrainingWorkitem; - RT_WORK_ITEM MPT_DIGWorkitem; - RT_WORK_ITEM RaRptWorkitem; - RT_WORK_ITEM sbdcnt_workitem; +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + struct _IQK_INFORMATION IQK_info; #endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _path_div_parameter_define_ path_iqk; +#endif + +#if (defined(CONFIG_PATH_DIVERSITY)) + struct _ODM_PATH_DIVERSITY_ dm_path_div; +#endif + +#if (defined(CONFIG_ANT_DETECTION)) + struct _ANT_DETECTED_INFO ant_detected_info; /* Antenna detected information for RSSI tool*/ #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (BEAMFORMING_SUPPORT == 1) - RT_BEAMFORMING_INFO BeamformingInfo; -#endif + struct _RT_BEAMFORMING_INFO beamforming_info; #endif - -#ifdef CONFIG_PHYDM_DFS_MASTER - u1Byte DFS_RegionDomain; - pu1Byte dfs_master_enabled; - - /*====== phydm_radar_detect_with_dbg_parm start ======*/ - u1Byte radar_detect_dbg_parm_en; - u4Byte radar_detect_reg_918; - u4Byte radar_detect_reg_91c; - u4Byte radar_detect_reg_920; - u4Byte radar_detect_reg_924; - /*====== phydm_radar_detect_with_dbg_parm end ======*/ #endif -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - +/*==========================================================*/ + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (RT_PLATFORM != PLATFORM_LINUX) -} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure +}PHY_DM_STRUCT; /*DM_Dynamic_Mechanism_Structure*/ #else }; -#endif +#endif -#else// for AP,ADSL,CE Team -} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure +#else /*for AP,CE Team*/ +}; #endif -typedef enum _PHYDM_STRUCTURE_TYPE{ +enum phydm_adv_ota { + PHYDM_PATHB_1RCCA = BIT(0), + PHYDM_HP_OTA_SETTING_A = BIT(1), + PHYDM_HP_OTA_SETTING_B = BIT(2), + PHYDM_ASUS_OTA_SETTING = BIT(3), + PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4), + +}; + +enum phydm_structure_type { PHYDM_FALSEALMCNT, PHYDM_CFOTRACK, PHYDM_ADAPTIVITY, PHYDM_ROMINFO, - -}PHYDM_STRUCTURE_TYPE; - +}; - typedef enum _ODM_RF_CONTENT{ +enum odm_rf_content { odm_radioa_txt = 0x1000, odm_radiob_txt = 0x1001, odm_radioc_txt = 0x1002, odm_radiod_txt = 0x1003 -} ODM_RF_CONTENT; +}; -typedef enum _ODM_BB_Config_Type{ - CONFIG_BB_PHY_REG, - CONFIG_BB_AGC_TAB, +enum odm_bb_config_type { + CONFIG_BB_PHY_REG, + CONFIG_BB_AGC_TAB, CONFIG_BB_AGC_TAB_2G, - CONFIG_BB_AGC_TAB_5G, + CONFIG_BB_AGC_TAB_5G, CONFIG_BB_PHY_REG_PG, CONFIG_BB_PHY_REG_MP, CONFIG_BB_AGC_TAB_DIFF, -} ODM_BB_Config_Type, *PODM_BB_Config_Type; +}; -typedef enum _ODM_RF_Config_Type{ +enum odm_rf_config_type { CONFIG_RF_RADIO, - CONFIG_RF_TXPWR_LMT, -} ODM_RF_Config_Type, *PODM_RF_Config_Type; - -typedef enum _ODM_FW_Config_Type{ - CONFIG_FW_NIC, - CONFIG_FW_NIC_2, - CONFIG_FW_AP, - CONFIG_FW_AP_2, - CONFIG_FW_MP, - CONFIG_FW_WoWLAN, - CONFIG_FW_WoWLAN_2, - CONFIG_FW_AP_WoWLAN, - CONFIG_FW_BT, -} ODM_FW_Config_Type; - -// Status code + CONFIG_RF_TXPWR_LMT, +}; + +enum odm_fw_config_type { + CONFIG_FW_NIC, + CONFIG_FW_NIC_2, + CONFIG_FW_AP, + CONFIG_FW_AP_2, + CONFIG_FW_MP, + CONFIG_FW_WOWLAN, + CONFIG_FW_WOWLAN_2, + CONFIG_FW_AP_WOWLAN, + CONFIG_FW_BT, +}; + +/*status code*/ #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) -typedef enum _RT_STATUS{ +enum rt_status { RT_STATUS_SUCCESS, RT_STATUS_FAILURE, RT_STATUS_PENDING, @@ -1095,303 +977,345 @@ typedef enum _RT_STATUS{ RT_STATUS_INVALID_PARAMETER, RT_STATUS_NOT_SUPPORT, RT_STATUS_OS_API_FAILED, -}RT_STATUS,*PRT_STATUS; -#endif // end of RT_STATUS definition +}; +#endif /*end of enum rt_status definition*/ #ifdef REMOVE_PACK -#pragma pack() + #pragma pack() #endif -//3=========================================================== -//3 AGC RX High Power Mode -//3=========================================================== -#define LNA_Low_Gain_1 0x64 -#define LNA_Low_Gain_2 0x5A -#define LNA_Low_Gain_3 0x58 - -#define FA_RXHP_TH1 5000 -#define FA_RXHP_TH2 1500 -#define FA_RXHP_TH3 800 -#define FA_RXHP_TH4 600 -#define FA_RXHP_TH5 500 +/*===========================================================*/ +/*AGC RX High Power mode*/ +/*===========================================================*/ +#define lna_low_gain_1 0x64 +#define lna_low_gain_2 0x5A +#define lna_low_gain_3 0x58 + +#define FA_RXHP_TH1 5000 +#define FA_RXHP_TH2 1500 +#define FA_RXHP_TH3 800 +#define FA_RXHP_TH4 600 +#define FA_RXHP_TH5 500 + +enum dm_1r_cca_e { + CCA_1R = 0, + CCA_2R = 1, + CCA_MAX = 2, +}; -typedef enum tag_1R_CCA_Type_Definition -{ - CCA_1R =0, - CCA_2R = 1, - CCA_MAX = 2, -}DM_1R_CCA_E; +enum dm_rf_e { + rf_save = 0, + rf_normal = 1, + RF_MAX = 2, +}; -typedef enum tag_RF_Type_Definition -{ - RF_Save =0, - RF_Normal = 1, - RF_MAX = 2, -}DM_RF_E; - -// -// check Sta pointer valid or not -// +/*check Sta pointer valid or not*/ #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#define IS_STA_VALID(pSta) (pSta && pSta->expire_to) + #define IS_STA_VALID(p_sta) (p_sta && p_sta->expire_to) #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#define IS_STA_VALID(pSta) (pSta && pSta->bUsed) + #define IS_STA_VALID(p_sta) (p_sta && p_sta->bUsed) #else -#define IS_STA_VALID(pSta) (pSta) + #define IS_STA_VALID(p_sta) (p_sta) #endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP)) - -BOOLEAN -ODM_CheckPowerStatus( - IN PADAPTER Adapter - ); +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP)) +boolean +odm_check_power_status( + struct _ADAPTER *adapter +); #endif +u32 odm_convert_to_db(u32 value); +u32 odm_convert_to_linear(u32 value); -u4Byte odm_ConvertTo_dB(u4Byte Value); - -u4Byte odm_ConvertTo_linear(u4Byte Value); +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +void +odm_dm_watchdog_lps( + struct PHY_DM_STRUCT *p_dm_odm +); +#endif -#if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) +s32 +odm_pwdb_conversion( + s32 X, + u32 total_bit, + u32 decimal_bit +); -u4Byte -GetPSDData( - PDM_ODM_T pDM_Odm, - unsigned int point, - u1Byte initial_gain_psd); +s32 +odm_sign_conversion( + s32 value, + u32 total_bit +); -#endif +void +phydm_txcurrentcalibration( + struct PHY_DM_STRUCT *p_dm_odm +); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -VOID -ODM_DMWatchdog_LPS( - IN PDM_ODM_T pDM_Odm +void +phydm_seq_sorting( + void *p_dm_void, + u32 *p_value, + u32 *rank_idx, + u32 *p_idx_out, + u8 seq_length ); -#endif +void +phydm_dm_early_init( + struct PHY_DM_STRUCT *p_dm_odm +); -s4Byte -ODM_PWdB_Conversion( - IN s4Byte X, - IN u4Byte TotalBit, - IN u4Byte DecimalBit - ); +void +odm_dm_init( + struct PHY_DM_STRUCT *p_dm_odm +); -s4Byte -ODM_SignConversion( - IN s4Byte value, - IN u4Byte TotalBit - ); +void +odm_dm_reset( + struct PHY_DM_STRUCT *p_dm_odm +); void -phydm_seq_sorting( - IN PVOID pDM_VOID, - IN OUT u4Byte *p_value, - IN OUT u4Byte *rank_idx, - IN OUT u4Byte *p_idx_out, - IN u1Byte seq_length +phydm_fwoffload_ability_init( + struct PHY_DM_STRUCT *p_dm_odm, + enum phydm_offload_ability offload_ability ); -VOID -ODM_DMInit( - IN PDM_ODM_T pDM_Odm +void +phydm_fwoffload_ability_clear( + struct PHY_DM_STRUCT *p_dm_odm, + enum phydm_offload_ability offload_ability ); -VOID -ODM_DMReset( - IN PDM_ODM_T pDM_Odm - ); -VOID +void phydm_support_ability_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ); - -VOID + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +void +phydm_config_ofdm_rx_path( + struct PHY_DM_STRUCT *p_dm_odm, + u32 path +); + +void phydm_config_trx_path( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ); - -VOID -ODM_DMWatchdog( - IN PDM_ODM_T pDM_Odm // For common use in the future - ); - -VOID -ODM_CmnInfoInit( - IN PDM_ODM_T pDM_Odm, - IN ODM_CMNINFO_E CmnInfo, - IN u4Byte Value - ); - -VOID -ODM_CmnInfoHook( - IN PDM_ODM_T pDM_Odm, - IN ODM_CMNINFO_E CmnInfo, - IN PVOID pValue - ); - -VOID -ODM_CmnInfoPtrArrayHook( - IN PDM_ODM_T pDM_Odm, - IN ODM_CMNINFO_E CmnInfo, - IN u2Byte Index, - IN PVOID pValue - ); - -VOID -ODM_CmnInfoUpdate( - IN PDM_ODM_T pDM_Odm, - IN u4Byte CmnInfo, - IN u8Byte Value - ); - -#if(DM_ODM_SUPPORT_TYPE==ODM_AP) -VOID -ODM_InitAllThreads( - IN PDM_ODM_T pDM_Odm - ); - -VOID -ODM_StopAllThreads( - IN PDM_ODM_T pDM_Odm - ); -#endif + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); -VOID -ODM_InitAllTimers( - IN PDM_ODM_T pDM_Odm - ); +void +odm_dm_watchdog( + struct PHY_DM_STRUCT *p_dm_odm +); -VOID -ODM_CancelAllTimers( - IN PDM_ODM_T pDM_Odm - ); +void +phydm_watchdog_mp( + struct PHY_DM_STRUCT *p_dm_odm +); -VOID -ODM_ReleaseAllTimers( - IN PDM_ODM_T pDM_Odm - ); +void +odm_cmn_info_init( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_cmninfo_e cmn_info, + u32 value +); +void +odm_cmn_info_hook( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_cmninfo_e cmn_info, + void *p_value +); +void +odm_cmn_info_update( + struct PHY_DM_STRUCT *p_dm_odm, + u32 cmn_info, + u64 value +); +u32 +phydm_cmn_info_query( + struct PHY_DM_STRUCT *p_dm_odm, + enum phydm_info_query_e info_type +); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ); -VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ); +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +void +odm_init_all_threads( + struct PHY_DM_STRUCT *p_dm_odm +); +void +odm_stop_all_threads( + struct PHY_DM_STRUCT *p_dm_odm +); +#endif +void +odm_init_all_timers( + struct PHY_DM_STRUCT *p_dm_odm +); -u8Byte -PlatformDivision64( - IN u8Byte x, - IN u8Byte y +void +odm_cancel_all_timers( + struct PHY_DM_STRUCT *p_dm_odm ); -//==================================================== -//3 PathDiV End -//==================================================== +void +odm_release_all_timers( + struct PHY_DM_STRUCT *p_dm_odm +); -#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm); +void odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm_odm); -typedef enum tag_DIG_Connect_Definition -{ - DIG_STA_DISCONNECT = 0, - DIG_STA_CONNECT = 1, - DIG_STA_BEFORE_CONNECT = 2, - DIG_MultiSTA_DISCONNECT = 3, - DIG_MultiSTA_CONNECT = 4, - DIG_CONNECT_MAX -}DM_DIG_CONNECT_E; +u64 +platform_division64( + u64 x, + u64 y +); +#define dm_change_dynamic_init_gain_thresh odm_change_dynamic_init_gain_thresh -// -// 2012/01/12 MH Check afapter status. Temp fix BSOD. -// -#define HAL_ADAPTER_STS_CHK(pDM_Odm)\ - if (pDM_Odm->Adapter == NULL)\ - {\ - return;\ - }\ +enum dm_dig_connect_e { + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + DIG_MULTI_STA_DISCONNECT = 3, + DIG_MULTI_STA_CONNECT = 4, + DIG_CONNECT_MAX +}; -#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +/*2012/01/12 MH Check afapter status. Temp fix BSOD.*/ -VOID -ODM_AsocEntry_Init( - IN PDM_ODM_T pDM_Odm - ); +#define HAL_ADAPTER_STS_CHK(p_dm_odm) do {\ + if (p_dm_odm->adapter == NULL) { \ + \ + return;\ + } \ + } while (0) +#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ -PVOID -PhyDM_Get_Structure( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Structure_Type +void * +phydm_get_structure( + struct PHY_DM_STRUCT *p_dm_odm, + u8 structure_type ); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) ||(DM_ODM_SUPPORT_TYPE == ODM_CE) -/*===========================================================*/ -/* The following is for compile only*/ -/*===========================================================*/ - -#define IS_HARDWARE_TYPE_8723A(_Adapter) FALSE -#define IS_HARDWARE_TYPE_8723AE(_Adapter) FALSE -#define IS_HARDWARE_TYPE_8192C(_Adapter) FALSE -#define IS_HARDWARE_TYPE_8192D(_Adapter) FALSE -#define RF_T_METER_92D 0x42 +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) || (DM_ODM_SUPPORT_TYPE == ODM_CE) + /*===========================================================*/ + /* The following is for compile only*/ + /*===========================================================*/ + + #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + #define IS_HARDWARE_TYPE_8188E(_adapter) false + #define IS_HARDWARE_TYPE_8188F(_adapter) false + #define IS_HARDWARE_TYPE_8703B(_adapter) false + #define IS_HARDWARE_TYPE_8723D(_adapter) false + #define IS_HARDWARE_TYPE_8821C(_adapter) false + #define IS_HARDWARE_TYPE_8812AU(_adapter) false + #define IS_HARDWARE_TYPE_8814A(_adapter) false + #define IS_HARDWARE_TYPE_8814AU(_adapter) false + #define IS_HARDWARE_TYPE_8814AE(_adapter) false + #define IS_HARDWARE_TYPE_8814AS(_adapter) false + #define IS_HARDWARE_TYPE_8723BU(_adapter) false + #define IS_HARDWARE_TYPE_8822BU(_adapter) false + #define IS_HARDWARE_TYPE_8822BS(_adapter) false + #define IS_HARDWARE_TYPE_JAGUAR(_Adapter) \ + (IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter)) + #else + #define IS_HARDWARE_TYPE_8723A(_adapter) false + #endif + #define IS_HARDWARE_TYPE_8723AE(_adapter) false + #define IS_HARDWARE_TYPE_8192C(_adapter) false + #define IS_HARDWARE_TYPE_8192D(_adapter) false + #define RF_T_METER_92D 0x42 -#define GET_RX_STATUS_DESC_RX_MCS(__pRxStatusDesc) LE_BITS_TO_1BYTE( __pRxStatusDesc+12, 0, 6) + #define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc) LE_BITS_TO_1BYTE(__prx_status_desc+12, 0, 6) -#define rConfig_ram64x16 0xb2c + #define REG_CONFIG_RAM64X16 0xb2c -#define TARGET_CHNL_NUM_2G_5G 59 + #define TARGET_CHNL_NUM_2G_5G 59 -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -u1Byte GetRightChnlPlaceforIQK(u1Byte chnl); -#endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + u8 get_right_chnl_place_for_iqk(u8 chnl); + #endif -//=========================================================== + /* *********************************************************** */ #endif #if (DM_ODM_SUPPORT_TYPE == ODM_CE) -void odm_dtc(PDM_ODM_T pDM_Odm); -#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ - - -VOID phydm_NoisyDetection(IN PDM_ODM_T pDM_Odm ); + void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm); +#endif +void phydm_noisy_detection( + struct PHY_DM_STRUCT *p_dm_odm +); -#endif +void +phydm_set_ext_switch( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); -VOID +void phydm_api_debug( - IN PVOID pDM_VOID, - IN u4Byte function_map, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len + void *p_dm_void, + u32 function_map, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +u8 +phydm_csi_mask_setting( + void *p_dm_void, + u32 enable, + u32 channel, + u32 bw, + u32 f_interference, + u32 Second_ch ); -u1Byte +u8 phydm_nbi_setting( - IN PVOID pDM_VOID, - IN u4Byte enable, - IN u4Byte channel, - IN u4Byte bw, - IN u4Byte f_interference, - IN u4Byte Second_ch + void *p_dm_void, + u32 enable, + u32 channel, + u32 bw, + u32 f_interference, + u32 second_ch +); + +void +phydm_dc_cancellation( + struct PHY_DM_STRUCT *p_dm_odm ); +void +phydm_receiver_blocking( + void *p_dm_void +); +#endif diff --git a/hal/phydm/phydm_acs.c b/hal/phydm/phydm_acs.c index 021702c..47f2ebf 100644 --- a/hal/phydm/phydm_acs.c +++ b/hal/phydm/phydm_acs.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,488 +11,443 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" -u1Byte -ODM_GetAutoChannelSelectResult( - IN PVOID pDM_VOID, - IN u1Byte Band +u8 +odm_get_auto_channel_select_result( + void *p_dm_void, + u8 band ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PACS pACS = &pDM_Odm->DM_ACS; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(Band == ODM_BAND_2_4G) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_2G(%d)\n", pACS->CleanChannel_2G)); - return (u1Byte)pACS->CleanChannel_2G; - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_5G(%d)\n", pACS->CleanChannel_5G)); - return (u1Byte)pACS->CleanChannel_5G; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (band == ODM_BAND_2_4G) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[struct _ACS_] odm_get_auto_channel_select_result(): clean_channel_2g(%d)\n", p_acs->clean_channel_2g)); + return (u8)p_acs->clean_channel_2g; + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[struct _ACS_] odm_get_auto_channel_select_result(): clean_channel_5g(%d)\n", p_acs->clean_channel_5g)); + return (u8)p_acs->clean_channel_5g; } #else - return (u1Byte)pACS->CleanChannel_2G; + return (u8)p_acs->clean_channel_2g; #endif } -VOID -odm_AutoChannelSelectSetting( - IN PVOID pDM_VOID, - IN BOOLEAN IsEnable +void +odm_auto_channel_select_setting( + void *p_dm_void, + boolean is_enable ) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte period = 0x2710;// 40ms in default - u2Byte NHMType = 0x7; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u16 period = 0x2710;/* 40ms in default */ + u16 nhm_type = 0x7; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSetting()=========> \n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select_setting()=========>\n")); - if(IsEnable) - {//20 ms + if (is_enable) { + /* 20 ms */ period = 0x1388; - NHMType = 0x1; + nhm_type = 0x1; } - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - { - //PHY parameters initialize for ac series - ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+2, period); //0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms - //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, NHMType); //0x994[9:8]=3 enable CCX - } - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - //PHY parameters initialize for n series - ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11N+2, period); //0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms - //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, NHMType); //0x890[9:8]=3 enable CCX + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + /* PHY parameters initialize for ac series */ + odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, period); /* 0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms */ + /* odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8)|BIT9|BIT10, nhm_type); */ /* 0x994[9:8]=3 enable CCX */ + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + /* PHY parameters initialize for n series */ + odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11N + 2, period); /* 0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms */ + /* odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10)|BIT9|BIT8, nhm_type); */ /* 0x890[9:8]=3 enable CCX */ } #endif } -VOID -odm_AutoChannelSelectInit( - IN PVOID pDM_VOID +void +odm_auto_channel_select_init( + void *p_dm_void ) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PACS pACS = &pDM_Odm->DM_ACS; - u1Byte i; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + u8 i; - if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) + if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) return; - if(pACS->bForceACSResult) + if (p_acs->is_force_acs_result) return; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectInit()=========> \n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select_init()=========>\n")); - pACS->CleanChannel_2G = 1; - pACS->CleanChannel_5G = 36; + p_acs->clean_channel_2g = 1; + p_acs->clean_channel_5g = 36; - for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) - { - pACS->Channel_Info_2G[0][i] = 0; - pACS->Channel_Info_2G[1][i] = 0; + for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) { + p_acs->channel_info_2g[0][i] = 0; + p_acs->channel_info_2g[1][i] = 0; } - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - { - for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) - { - pACS->Channel_Info_5G[0][i] = 0; - pACS->Channel_Info_5G[1][i] = 0; + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) { + p_acs->channel_info_5g[0][i] = 0; + p_acs->channel_info_5g[1][i] = 0; } } #endif } -VOID -odm_AutoChannelSelectReset( - IN PVOID pDM_VOID +void +odm_auto_channel_select_reset( + void *p_dm_void ) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PACS pACS = &pDM_Odm->DM_ACS; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ACS_ *p_acs = &p_dm_odm->dm_acs; - if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) + if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) return; - if(pACS->bForceACSResult) + if (p_acs->is_force_acs_result) return; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectReset()=========> \n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select_reset()=========>\n")); - odm_AutoChannelSelectSetting(pDM_Odm,TRUE);// for 20ms measurement - Phydm_NHMCounterStatisticsReset(pDM_Odm); + odm_auto_channel_select_setting(p_dm_odm, true); /* for 20ms measurement */ + phydm_nhm_counter_statistics_reset(p_dm_odm); #endif } -VOID -odm_AutoChannelSelect( - IN PVOID pDM_VOID, - IN u1Byte Channel +void +odm_auto_channel_select( + void *p_dm_void, + u8 channel ) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PACS pACS = &pDM_Odm->DM_ACS; - u1Byte ChannelIDX = 0, SearchIDX = 0; - u2Byte MaxScore=0; - - if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Return: SupportAbility ODM_BB_NHM_CNT is disabled\n")); +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + u8 channel_idx = 0, search_idx = 0; + u16 max_score = 0; + + if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_auto_channel_select(): Return: support_ability ODM_BB_NHM_CNT is disabled\n")); return; } - if(pACS->bForceACSResult) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Force 2G clean channel = %d, 5G clean channel = %d\n", - pACS->CleanChannel_2G, pACS->CleanChannel_5G)); + if (p_acs->is_force_acs_result) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_auto_channel_select(): Force 2G clean channel = %d, 5G clean channel = %d\n", + p_acs->clean_channel_2g, p_acs->clean_channel_5g)); return; } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel = %d=========> \n", Channel)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select(): channel = %d=========>\n", channel)); - Phydm_GetNHMCounterStatistics(pDM_Odm); - odm_AutoChannelSelectSetting(pDM_Odm,FALSE); + phydm_get_nhm_counter_statistics(p_dm_odm); + odm_auto_channel_select_setting(p_dm_odm, false); - if(Channel >=1 && Channel <=14) - { - ChannelIDX = Channel - 1; - pACS->Channel_Info_2G[1][ChannelIDX]++; - - if(pACS->Channel_Info_2G[1][ChannelIDX] >= 2) - pACS->Channel_Info_2G[0][ChannelIDX] = (pACS->Channel_Info_2G[0][ChannelIDX] >> 1) + - (pACS->Channel_Info_2G[0][ChannelIDX] >> 2) + (pDM_Odm->NHM_cnt_0>>2); + if (channel >= 1 && channel <= 14) { + channel_idx = channel - 1; + p_acs->channel_info_2g[1][channel_idx]++; + + if (p_acs->channel_info_2g[1][channel_idx] >= 2) + p_acs->channel_info_2g[0][channel_idx] = (p_acs->channel_info_2g[0][channel_idx] >> 1) + + (p_acs->channel_info_2g[0][channel_idx] >> 2) + (p_dm_odm->nhm_cnt_0 >> 2); else - pACS->Channel_Info_2G[0][ChannelIDX] = pDM_Odm->NHM_cnt_0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): NHM_cnt_0 = %d \n", pDM_Odm->NHM_cnt_0)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", ChannelIDX, pACS->Channel_Info_2G[0][ChannelIDX], ChannelIDX, pACS->Channel_Info_2G[1][ChannelIDX])); + p_acs->channel_info_2g[0][channel_idx] = p_dm_odm->nhm_cnt_0; - for(SearchIDX = 0; SearchIDX < ODM_MAX_CHANNEL_2G; SearchIDX++) - { - if(pACS->Channel_Info_2G[1][SearchIDX] != 0) - { - if(pACS->Channel_Info_2G[0][SearchIDX] >= MaxScore) - { - MaxScore = pACS->Channel_Info_2G[0][SearchIDX]; - pACS->CleanChannel_2G = SearchIDX+1; - } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select(): nhm_cnt_0 = %d\n", p_dm_odm->nhm_cnt_0)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", channel_idx, p_acs->channel_info_2g[0][channel_idx], channel_idx, p_acs->channel_info_2g[1][channel_idx])); + + for (search_idx = 0; search_idx < ODM_MAX_CHANNEL_2G; search_idx++) { + if (p_acs->channel_info_2g[1][search_idx] != 0 && p_acs->channel_info_2g[0][search_idx] >= max_score) { + max_score = p_acs->channel_info_2g[0][search_idx]; + p_acs->clean_channel_2g = search_idx + 1; } } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_AutoChannelSelect(): 2G: CleanChannel_2G = %d, MaxScore = %d \n", - pACS->CleanChannel_2G, MaxScore)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_auto_channel_select(): 2G: clean_channel_2g = %d, max_score = %d\n", + p_acs->clean_channel_2g, max_score)); - } - else if(Channel >= 36) - { - // Need to do - pACS->CleanChannel_5G = Channel; + } else if (channel >= 36) { + /* Need to do */ + p_acs->clean_channel_5g = channel; } #endif } -#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -phydm_AutoChannelSelectSettingAP( - IN PVOID pDM_VOID, - IN u4Byte setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING - IN u4Byte acs_step +void +phydm_auto_channel_select_setting_ap( + void *p_dm_void, + u32 setting, /* 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING */ + u32 acs_step ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - prtl8192cd_priv priv = pDM_Odm->priv; - PACS pACS = &pDM_Odm->DM_ACS; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSettingAP()=========> \n")); - - //3 Store Default Setting - if(setting == STORE_DEFAULT_NHM_SETTING) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("STORE_DEFAULT_NHM_SETTING\n")); - - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) // store Reg0x990, Reg0x994, Reg0x998, Reg0x99C, Reg0x9a0 - { - pACS->Reg0x990 = ODM_Read4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC); // Reg0x990 - pACS->Reg0x994 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC); // Reg0x994 - pACS->Reg0x998 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC); // Reg0x998 - pACS->Reg0x99C = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC); // Reg0x99c - pACS->Reg0x9A0 = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC); // Reg0x9a0, u1Byte - } - else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - pACS->Reg0x890 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N); // Reg0x890 - pACS->Reg0x894 = ODM_Read4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11N); // Reg0x894 - pACS->Reg0x898 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N); // Reg0x898 - pACS->Reg0x89C = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N); // Reg0x89c - pACS->Reg0xE28 = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N); // Reg0xe28, u1Byte - } - } - - //3 Restore Default Setting - else if(setting == RESTORE_DEFAULT_NHM_SETTING) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("RESTORE_DEFAULT_NHM_SETTING\n")); - - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) // store Reg0x990, Reg0x994, Reg0x998, Reg0x99C, Reg0x9a0 - { - ODM_Write4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, pACS->Reg0x990); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, pACS->Reg0x994); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, pACS->Reg0x998); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, pACS->Reg0x99C); - ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC, pACS->Reg0x9A0); - } - else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, pACS->Reg0x890); - ODM_Write4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, pACS->Reg0x894); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, pACS->Reg0x898); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, pACS->Reg0x89C); - ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N, pACS->Reg0xE28); - } - } - - //3 ACS Setting - else if(setting == ACS_NHM_SETTING) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("ACS_NHM_SETTING\n")); - u2Byte period; - period = 0x61a8; - pACS->ACS_Step = acs_step; - - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - { - //4 Set NHM period, 0x990[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms - ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+2, period); - //4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC,BIT8|BIT9|BIT10, 3); - - if(pACS->ACS_Step == 0) - { - //4 Set IGI - ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); - if (get_rf_mimo_mode(priv) != MIMO_1T1R) - ODM_SetBBReg(pDM_Odm,0xe50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); - - //4 Set ACS NHM threshold - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x82786e64); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff8c); - ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC, 0xff); - ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff); - - } - else if(pACS->ACS_Step == 1) - { - //4 Set IGI - ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); - if (get_rf_mimo_mode(priv) != MIMO_1T1R) - ODM_SetBBReg(pDM_Odm,0xe50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); - - //4 Set ACS NHM threshold - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x5a50463c); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff64); - - } - - } - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - //4 Set NHM period, 0x894[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms - ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+2, period); - //4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N,BIT8|BIT9|BIT10, 3); - - if(pACS->ACS_Step == 0) - { - //4 Set IGI - ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); - if (get_rf_mimo_mode(priv) != MIMO_1T1R) - ODM_SetBBReg(pDM_Odm,0xc58,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); - - //4 Set ACS NHM threshold - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x82786e64); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff8c); - ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N, 0xff); - ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff); - - } - else if(pACS->ACS_Step == 1) - { - //4 Set IGI - ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); - if (get_rf_mimo_mode(priv) != MIMO_1T1R) - ODM_SetBBReg(pDM_Odm,0xc58,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); - - //4 Set ACS NHM threshold - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x5a50463c); - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff64); - - } - } - } - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSettingAP()=========>\n")); + + /* 3 Store Default setting */ + if (setting == STORE_DEFAULT_NHM_SETTING) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("STORE_DEFAULT_NHM_SETTING\n")); + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { /* store reg0x990, reg0x994, reg0x998, reg0x99c, Reg0x9a0 */ + p_acs->reg0x990 = odm_read_4byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC); /* reg0x990 */ + p_acs->reg0x994 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC); /* reg0x994 */ + p_acs->reg0x998 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC); /* reg0x998 */ + p_acs->reg0x99c = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC); /* Reg0x99c */ + p_acs->reg0x9a0 = odm_read_1byte(p_dm_odm, ODM_REG_NHM_TH8_11AC); /* Reg0x9a0, u8 */ + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + p_acs->reg0x890 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N); /* reg0x890 */ + p_acs->reg0x894 = odm_read_4byte(p_dm_odm, ODM_REG_CCX_PERIOD_11N); /* reg0x894 */ + p_acs->reg0x898 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N); /* reg0x898 */ + p_acs->reg0x89c = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N); /* Reg0x89c */ + p_acs->reg0xe28 = odm_read_1byte(p_dm_odm, ODM_REG_NHM_TH8_11N); /* Reg0xe28, u8 */ + } + } + + /* 3 Restore Default setting */ + else if (setting == RESTORE_DEFAULT_NHM_SETTING) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("RESTORE_DEFAULT_NHM_SETTING\n")); + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { /* store reg0x990, reg0x994, reg0x998, reg0x99c, Reg0x9a0 */ + odm_write_4byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, p_acs->reg0x990); + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, p_acs->reg0x994); + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, p_acs->reg0x998); + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, p_acs->reg0x99c); + odm_write_1byte(p_dm_odm, ODM_REG_NHM_TH8_11AC, p_acs->reg0x9a0); + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, p_acs->reg0x890); + odm_write_4byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, p_acs->reg0x894); + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, p_acs->reg0x898); + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, p_acs->reg0x89c); + odm_write_1byte(p_dm_odm, ODM_REG_NHM_TH8_11N, p_acs->reg0xe28); + } + } + + /* 3 struct _ACS_ setting */ + else if (setting == ACS_NHM_SETTING) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("ACS_NHM_SETTING\n")); + u16 period; + period = 0x61a8; + p_acs->acs_step = acs_step; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + /* 4 Set NHM period, 0x990[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms */ + odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, period); + /* 4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 */ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8) | BIT(9) | BIT(10), 3); + + if (p_acs->acs_step == 0) { + /* 4 Set IGI */ + odm_set_bb_reg(p_dm_odm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E); + if (get_rf_mimo_mode(priv) != MIMO_1T1R) + odm_set_bb_reg(p_dm_odm, 0xe50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E); + + /* 4 Set struct _ACS_ NHM threshold */ + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x82786e64); + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff8c); + odm_write_1byte(p_dm_odm, ODM_REG_NHM_TH8_11AC, 0xff); + odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); + + } else if (p_acs->acs_step == 1) { + /* 4 Set IGI */ + odm_set_bb_reg(p_dm_odm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A); + if (get_rf_mimo_mode(priv) != MIMO_1T1R) + odm_set_bb_reg(p_dm_odm, 0xe50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A); + + /* 4 Set struct _ACS_ NHM threshold */ + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x5a50463c); + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff64); + + } + + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + /* 4 Set NHM period, 0x894[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms */ + odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, period); + /* 4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 */ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(8) | BIT(9) | BIT(10), 3); + + if (p_acs->acs_step == 0) { + /* 4 Set IGI */ + odm_set_bb_reg(p_dm_odm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E); + if (get_rf_mimo_mode(priv) != MIMO_1T1R) + odm_set_bb_reg(p_dm_odm, 0xc58, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E); + + /* 4 Set struct _ACS_ NHM threshold */ + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x82786e64); + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff8c); + odm_write_1byte(p_dm_odm, ODM_REG_NHM_TH8_11N, 0xff); + odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); + + } else if (p_acs->acs_step == 1) { + /* 4 Set IGI */ + odm_set_bb_reg(p_dm_odm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A); + if (get_rf_mimo_mode(priv) != MIMO_1T1R) + odm_set_bb_reg(p_dm_odm, 0xc58, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A); + + /* 4 Set struct _ACS_ NHM threshold */ + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x5a50463c); + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff64); + + } + } + } + } -VOID -phydm_GetNHMStatisticsAP( - IN PVOID pDM_VOID, - IN u4Byte idx, // @ 2G, Real channel number = idx+1 - IN u4Byte acs_step +void +phydm_get_nhm_statistics_ap( + void *p_dm_void, + u32 idx, /* @ 2G, Real channel number = idx+1 */ + u32 acs_step ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - prtl8192cd_priv priv = pDM_Odm->priv; - PACS pACS = &pDM_Odm->DM_ACS; - u4Byte value32 = 0; - u1Byte i; - - pACS->ACS_Step = acs_step; - - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { - //4 Check if NHM result is ready - for (i=0; i<20; i++) { - - ODM_delay_ms(1); - if ( ODM_GetBBReg(pDM_Odm,rFPGA0_PSDReport,BIT17) ) - break; - } - - //4 Get NHM Statistics - if ( pACS->ACS_Step==1 ) { - - value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT7_TO_CNT4_11N); - - pACS->NHM_Cnt[idx][9] = (value32 & bMaskByte1) >> 8; - pACS->NHM_Cnt[idx][8] = (value32 & bMaskByte0); - - value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11N); // ODM_REG_NHM_CNT3_TO_CNT0_11N - - pACS->NHM_Cnt[idx][7] = (value32 & bMaskByte3) >> 24; - pACS->NHM_Cnt[idx][6] = (value32 & bMaskByte2) >> 16; - pACS->NHM_Cnt[idx][5] = (value32 & bMaskByte1) >> 8; - - } else if (pACS->ACS_Step==2) { - - value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11N); // ODM_REG_NHM_CNT3_TO_CNT0_11N - - pACS->NHM_Cnt[idx][4] = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); - pACS->NHM_Cnt[idx][3] = (value32 & bMaskByte3) >> 24; - pACS->NHM_Cnt[idx][2] = (value32 & bMaskByte2) >> 16; - pACS->NHM_Cnt[idx][1] = (value32 & bMaskByte1) >> 8; - pACS->NHM_Cnt[idx][0] = (value32 & bMaskByte0); - } - } - else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - { - //4 Check if NHM result is ready - for (i=0; i<20; i++) { - - ODM_delay_ms(1); - if (ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC, BIT16)) - break; - } - - if ( pACS->ACS_Step==1 ) { - - value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT7_TO_CNT4_11AC); - - pACS->NHM_Cnt[idx][9] = (value32 & bMaskByte1) >> 8; - pACS->NHM_Cnt[idx][8] = (value32 & bMaskByte0); - - value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11AC); // ODM_REG_NHM_CNT3_TO_CNT0_11AC - - pACS->NHM_Cnt[idx][7] = (value32 & bMaskByte3) >> 24; - pACS->NHM_Cnt[idx][6] = (value32 & bMaskByte2) >> 16; - pACS->NHM_Cnt[idx][5] = (value32 & bMaskByte1) >> 8; - - } else if (pACS->ACS_Step==2) { - - value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11AC); // ODM_REG_NHM_CNT3_TO_CNT0_11AC - - pACS->NHM_Cnt[idx][4] = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); - pACS->NHM_Cnt[idx][3] = (value32 & bMaskByte3) >> 24; - pACS->NHM_Cnt[idx][2] = (value32 & bMaskByte2) >> 16; - pACS->NHM_Cnt[idx][1] = (value32 & bMaskByte1) >> 8; - pACS->NHM_Cnt[idx][0] = (value32 & bMaskByte0); - } - } + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + u32 value32 = 0; + u8 i; + + p_acs->acs_step = acs_step; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + /* 4 Check if NHM result is ready */ + for (i = 0; i < 20; i++) { + + ODM_delay_ms(1); + if (odm_get_bb_reg(p_dm_odm, REG_FPGA0_PSD_REPORT, BIT(17))) + break; + } + + /* 4 Get NHM Statistics */ + if (p_acs->acs_step == 1) { + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); + + p_acs->nhm_cnt[idx][9] = (value32 & MASKBYTE1) >> 8; + p_acs->nhm_cnt[idx][8] = (value32 & MASKBYTE0); + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11N); /* ODM_REG_NHM_CNT3_TO_CNT0_11N */ + + p_acs->nhm_cnt[idx][7] = (value32 & MASKBYTE3) >> 24; + p_acs->nhm_cnt[idx][6] = (value32 & MASKBYTE2) >> 16; + p_acs->nhm_cnt[idx][5] = (value32 & MASKBYTE1) >> 8; + + } else if (p_acs->acs_step == 2) { + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11N); /* ODM_REG_NHM_CNT3_TO_CNT0_11N */ + + p_acs->nhm_cnt[idx][4] = odm_read_1byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); + p_acs->nhm_cnt[idx][3] = (value32 & MASKBYTE3) >> 24; + p_acs->nhm_cnt[idx][2] = (value32 & MASKBYTE2) >> 16; + p_acs->nhm_cnt[idx][1] = (value32 & MASKBYTE1) >> 8; + p_acs->nhm_cnt[idx][0] = (value32 & MASKBYTE0); + } + } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + /* 4 Check if NHM result is ready */ + for (i = 0; i < 20; i++) { + + ODM_delay_ms(1); + if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(16))) + break; + } + + if (p_acs->acs_step == 1) { + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); + + p_acs->nhm_cnt[idx][9] = (value32 & MASKBYTE1) >> 8; + p_acs->nhm_cnt[idx][8] = (value32 & MASKBYTE0); + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11AC); /* ODM_REG_NHM_CNT3_TO_CNT0_11AC */ + + p_acs->nhm_cnt[idx][7] = (value32 & MASKBYTE3) >> 24; + p_acs->nhm_cnt[idx][6] = (value32 & MASKBYTE2) >> 16; + p_acs->nhm_cnt[idx][5] = (value32 & MASKBYTE1) >> 8; + + } else if (p_acs->acs_step == 2) { + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11AC); /* ODM_REG_NHM_CNT3_TO_CNT0_11AC */ + + p_acs->nhm_cnt[idx][4] = odm_read_1byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); + p_acs->nhm_cnt[idx][3] = (value32 & MASKBYTE3) >> 24; + p_acs->nhm_cnt[idx][2] = (value32 & MASKBYTE2) >> 16; + p_acs->nhm_cnt[idx][1] = (value32 & MASKBYTE1) >> 8; + p_acs->nhm_cnt[idx][0] = (value32 & MASKBYTE0); + } + } } -//#define ACS_DEBUG_INFO //acs debug default off -/* -int phydm_AutoChannelSelectAP( - IN PVOID pDM_VOID, - IN u4Byte ACS_Type, // 0: RXCount_Type, 1:NHM_Type - IN u4Byte available_chnl_num // amount of all channels - ) +/* #define ACS_DEBUG_INFO */ /* acs debug default off */ +#if 0 +int phydm_AutoChannelSelectAP( + void *p_dm_void, + u32 ACS_Type, /* 0: RXCount_Type, 1:NHM_Type */ + u32 available_chnl_num /* amount of all channels */ +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PACS pACS = &pDM_Odm->DM_ACS; - prtl8192cd_priv priv = pDM_Odm->priv; - - static u4Byte score2G[MAX_2G_CHANNEL_NUM], score5G[MAX_5G_CHANNEL_NUM]; - u4Byte score[MAX_BSS_NUM], use_nhm = 0; - u4Byte minScore=0xffffffff; - u4Byte tmpScore, tmpIdx=0; - u4Byte traffic_check = 0; - u4Byte fa_count_weighting = 1; - int i, j, idx=0, idx_2G_end=-1, idx_5G_begin=-1, minChan=0; - struct bss_desc *pBss=NULL; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + + static u32 score2G[MAX_2G_CHANNEL_NUM], score5G[MAX_5G_CHANNEL_NUM]; + u32 score[MAX_BSS_NUM], use_nhm = 0; + u32 minScore = 0xffffffff; + u32 tmpScore, tmpIdx = 0; + u32 traffic_check = 0; + u32 fa_count_weighting = 1; + int i, j, idx = 0, idx_2G_end = -1, idx_5G_begin = -1, minChan = 0; + struct bss_desc *pBss = NULL; #ifdef _DEBUG_RTL8192CD_ char tmpbuf[400]; - int len=0; + int len = 0; #endif memset(score2G, '\0', sizeof(score2G)); memset(score5G, '\0', sizeof(score5G)); - for (i=0; iavailable_chnl_num; i++) { + for (i = 0; i < priv->available_chnl_num; i++) { if (priv->available_chnl[i] <= 14) idx_2G_end = i; else break; } - for (i=0; iavailable_chnl_num; i++) { + for (i = 0; i < priv->available_chnl_num; i++) { if (priv->available_chnl[i] > 14) { idx_5G_begin = i; break; } } -// DELETE + /* DELETE */ #ifndef CONFIG_RTL_NEW_AUTOCH - for (i=0; isite_survey->count; i++) { + for (i = 0; i < priv->site_survey->count; i++) { pBss = &priv->site_survey->bss[i]; - for (idx=0; idxavailable_chnl_num; idx++) { + for (idx = 0; idx < priv->available_chnl_num; idx++) { if (pBss->channel == priv->available_chnl[idx]) { if (pBss->channel <= 14) - setChannelScore(idx, score2G, 0, MAX_2G_CHANNEL_NUM-1); + setChannelScore(idx, score2G, 0, MAX_2G_CHANNEL_NUM - 1); else score5G[idx - idx_5G_begin] += 5; break; @@ -502,42 +457,41 @@ int phydm_AutoChannelSelectAP( #endif if (idx_2G_end >= 0) - for (i=0; i<=idx_2G_end; i++) + for (i = 0; i <= idx_2G_end; i++) score[i] = score2G[i]; if (idx_5G_begin >= 0) - for (i=idx_5G_begin; iavailable_chnl_num; i++) + for (i = idx_5G_begin; i < priv->available_chnl_num; i++) score[i] = score5G[i - idx_5G_begin]; - + #ifdef CONFIG_RTL_NEW_AUTOCH { - u4Byte y, ch_begin=0, ch_end= priv->available_chnl_num; + u32 y, ch_begin = 0, ch_end = priv->available_chnl_num; + + u32 do_ap_check = 1, ap_ratio = 0; - u4Byte do_ap_check = 1, ap_ratio = 0; - - if (idx_2G_end >= 0) - ch_end = idx_2G_end+1; - if (idx_5G_begin >= 0) + if (idx_2G_end >= 0) + ch_end = idx_2G_end + 1; + if (idx_5G_begin >= 0) ch_begin = idx_5G_begin; -#ifdef ACS_DEBUG_INFO//for debug +#ifdef ACS_DEBUG_INFO/* for debug */ printk("\n"); - for (y=ch_begin; yavailable_chnl[y], - priv->chnl_ss_mac_rx_count[y], - priv->chnl_ss_mac_rx_count_40M[y], - priv->chnl_ss_fa_count[y], - score[y]); + priv->available_chnl[y], + priv->chnl_ss_mac_rx_count[y], + priv->chnl_ss_mac_rx_count_40M[y], + priv->chnl_ss_fa_count[y], + score[y]); printk("\n"); #endif #if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_WLAN_HAL_8192EE) - if( pDM_Odm->SupportICType&(ODM_RTL8188E|ODM_RTL8192E)&& priv->pmib->dot11RFEntry.acs_type ) - { - u4Byte tmp_score[MAX_BSS_NUM]; + if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E) && priv->pmib->dot11RFEntry.acs_type) { + u32 tmp_score[MAX_BSS_NUM]; memcpy(tmp_score, score, sizeof(score)); if (find_clean_channel(priv, ch_begin, ch_end, tmp_score)) { - //memcpy(score, tmp_score, sizeof(score)); + /* memcpy(score, tmp_score, sizeof(score)); */ #ifdef _DEBUG_RTL8192CD_ printk("!! Found clean channel, select minimum FA channel\n"); #endif @@ -548,152 +502,151 @@ int phydm_AutoChannelSelectAP( #endif use_nhm = 1; USE_CLN_CH: - for (y=ch_begin; ynhm_cnt[y][i]; - for (j=0; jnhm_cnt[y][i]; + for (j = 0; j < i; j++) val32 *= 3; score[y] += val32; } -#ifdef _DEBUG_RTL8192CD_ - printk("nhm_cnt_%d: H<-[ %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d]->L, score: %d\n", - y+1, priv->nhm_cnt[y][9], priv->nhm_cnt[y][8], priv->nhm_cnt[y][7], - priv->nhm_cnt[y][6], priv->nhm_cnt[y][5], priv->nhm_cnt[y][4], - priv->nhm_cnt[y][3], priv->nhm_cnt[y][2], priv->nhm_cnt[y][1], - priv->nhm_cnt[y][0], score[y]); +#ifdef _DEBUG_RTL8192CD_ + printk("nhm_cnt_%d: H<-[ %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d]->L, score: %d\n", + y + 1, priv->nhm_cnt[y][9], priv->nhm_cnt[y][8], priv->nhm_cnt[y][7], + priv->nhm_cnt[y][6], priv->nhm_cnt[y][5], priv->nhm_cnt[y][4], + priv->nhm_cnt[y][3], priv->nhm_cnt[y][2], priv->nhm_cnt[y][1], + priv->nhm_cnt[y][0], score[y]); #endif } if (!use_nhm) memcpy(score, tmp_score, sizeof(score)); - + goto choose_ch; } #endif - // For each channel, weighting behind channels with MAC RX counter - //For each channel, weighting the channel with FA counter + /* For each channel, weighting behind channels with MAC RX counter */ + /* For each channel, weighting the channel with FA counter */ - for (y=ch_begin; ychnl_ss_mac_rx_count[y]; if (priv->chnl_ss_mac_rx_count[y] > 30) do_ap_check = 0; - if( priv->chnl_ss_mac_rx_count[y] > MAC_RX_COUNT_THRESHOLD ) + if (priv->chnl_ss_mac_rx_count[y] > MAC_RX_COUNT_THRESHOLD) traffic_check = 1; - + #ifdef RTK_5G_SUPPORT - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) + if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) #endif { - if ((int)(y-4) >= (int)ch_begin) - score[y-4] += 2 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y-3) >= (int)ch_begin) - score[y-3] += 8 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y-2) >= (int)ch_begin) - score[y-2] += 8 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y-1) >= (int)ch_begin) - score[y-1] += 10 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y+1) < (int)ch_end) - score[y+1] += 10 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y+2) < (int)ch_end) - score[y+2] += 8 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y+3) < (int)ch_end) - score[y+3] += 8 * priv->chnl_ss_mac_rx_count[y]; - if ((int)(y+4) < (int)ch_end) - score[y+4] += 2 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y - 4) >= (int)ch_begin) + score[y - 4] += 2 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y - 3) >= (int)ch_begin) + score[y - 3] += 8 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y - 2) >= (int)ch_begin) + score[y - 2] += 8 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y - 1) >= (int)ch_begin) + score[y - 1] += 10 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y + 1) < (int)ch_end) + score[y + 1] += 10 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y + 2) < (int)ch_end) + score[y + 2] += 8 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y + 3) < (int)ch_end) + score[y + 3] += 8 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y + 4) < (int)ch_end) + score[y + 4] += 2 * priv->chnl_ss_mac_rx_count[y]; } - //this is for CH_LOAD caculation - if( priv->chnl_ss_cca_count[y] > priv->chnl_ss_fa_count[y]) - priv->chnl_ss_cca_count[y]-= priv->chnl_ss_fa_count[y]; + /* this is for CH_LOAD caculation */ + if (priv->chnl_ss_cca_count[y] > priv->chnl_ss_fa_count[y]) + priv->chnl_ss_cca_count[y] -= priv->chnl_ss_fa_count[y]; else priv->chnl_ss_cca_count[y] = 0; } -#ifdef ACS_DEBUG_INFO//for debug +#ifdef ACS_DEBUG_INFO/* for debug */ printk("\n"); - for (y=ch_begin; yavailable_chnl[y], score[y]); + for (y = ch_begin; y < ch_end; y++) + printk("2. after 20M check: chnl[%d] score[%d]\n", priv->available_chnl[y], score[y]); printk("\n"); -#endif +#endif - for (y=ch_begin; ychnl_ss_mac_rx_count_40M[y]) { score[y] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; if (priv->chnl_ss_mac_rx_count_40M[y] > 30) do_ap_check = 0; - if( priv->chnl_ss_mac_rx_count_40M[y] > MAC_RX_COUNT_THRESHOLD ) + if (priv->chnl_ss_mac_rx_count_40M[y] > MAC_RX_COUNT_THRESHOLD) traffic_check = 1; - + #ifdef RTK_5G_SUPPORT - if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) + if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) #endif { - if ((int)(y-6) >= (int)ch_begin) - score[y-6] += 1 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y-5) >= (int)ch_begin) - score[y-5] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y-4) >= (int)ch_begin) - score[y-4] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y-3) >= (int)ch_begin) - score[y-3] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y-2) >= (int)ch_begin) - score[y-2] += (5 * priv->chnl_ss_mac_rx_count_40M[y])/2; - if ((int)(y-1) >= (int)ch_begin) - score[y-1] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y+1) < (int)ch_end) - score[y+1] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y+2) < (int)ch_end) - score[y+2] += (5 * priv->chnl_ss_mac_rx_count_40M[y])/2; - if ((int)(y+3) < (int)ch_end) - score[y+3] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y+4) < (int)ch_end) - score[y+4] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y+5) < (int)ch_end) - score[y+5] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; - if ((int)(y+6) < (int)ch_end) - score[y+6] += 1 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y - 6) >= (int)ch_begin) + score[y - 6] += 1 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y - 5) >= (int)ch_begin) + score[y - 5] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y - 4) >= (int)ch_begin) + score[y - 4] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y - 3) >= (int)ch_begin) + score[y - 3] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y - 2) >= (int)ch_begin) + score[y - 2] += (5 * priv->chnl_ss_mac_rx_count_40M[y]) / 2; + if ((int)(y - 1) >= (int)ch_begin) + score[y - 1] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y + 1) < (int)ch_end) + score[y + 1] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y + 2) < (int)ch_end) + score[y + 2] += (5 * priv->chnl_ss_mac_rx_count_40M[y]) / 2; + if ((int)(y + 3) < (int)ch_end) + score[y + 3] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y + 4) < (int)ch_end) + score[y + 4] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y + 5) < (int)ch_end) + score[y + 5] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y + 6) < (int)ch_end) + score[y + 6] += 1 * priv->chnl_ss_mac_rx_count_40M[y]; } } } -#ifdef ACS_DEBUG_INFO//for debug +#ifdef ACS_DEBUG_INFO/* for debug */ printk("\n"); - for (y=ch_begin; yavailable_chnl[y], score[y]); + for (y = ch_begin; y < ch_end; y++) + printk("3. after 40M check: chnl[%d] score[%d]\n", priv->available_chnl[y], score[y]); printk("\n"); printk("4. do_ap_check=%d traffic_check=%d\n", do_ap_check, traffic_check); printk("\n"); #endif - if( traffic_check == 0) + if (traffic_check == 0) fa_count_weighting = 5; else fa_count_weighting = 1; - for (y=ch_begin; ychnl_ss_fa_count[y]; - } -#ifdef ACS_DEBUG_INFO//for debug +#ifdef ACS_DEBUG_INFO/* for debug */ printk("\n"); - for (y=ch_begin; yavailable_chnl[y], score[y]); + for (y = ch_begin; y < ch_end; y++) + printk("5. after fa check: chnl[%d] score[%d]\n", priv->available_chnl[y], score[y]); printk("\n"); -#endif +#endif if (do_ap_check) { - for (i=0; isite_survey->count; i++) { + for (i = 0; i < priv->site_survey->count; i++) { pBss = &priv->site_survey->bss[i]; - for (y=ch_begin; ychannel == priv->available_chnl[y]) { if (pBss->channel <= 14) { -#ifdef ACS_DEBUG_INFO//for debug - printk("\n"); - printk("chnl[%d] has ap rssi=%d bw[0x%02x]\n", - pBss->channel, pBss->rssi, pBss->t_stamp[1]); - printk("\n"); +#ifdef ACS_DEBUG_INFO/* for debug */ + printk("\n"); + printk("chnl[%d] has ap rssi=%d bw[0x%02x]\n", + pBss->channel, pBss->rssi, pBss->t_stamp[1]); + printk("\n"); #endif if (pBss->rssi > 60) ap_ratio = 4; @@ -701,86 +654,81 @@ int phydm_AutoChannelSelectAP( ap_ratio = 2; else ap_ratio = 1; - + if ((pBss->t_stamp[1] & 0x6) == 0) { score[y] += 50 * ap_ratio; - if ((int)(y-4) >= (int)ch_begin) - score[y-4] += 10 * ap_ratio; - if ((int)(y-3) >= (int)ch_begin) - score[y-3] += 20 * ap_ratio; - if ((int)(y-2) >= (int)ch_begin) - score[y-2] += 30 * ap_ratio; - if ((int)(y-1) >= (int)ch_begin) - score[y-1] += 40 * ap_ratio; - if ((int)(y+1) < (int)ch_end) - score[y+1] += 40 * ap_ratio; - if ((int)(y+2) < (int)ch_end) - score[y+2] += 30 * ap_ratio; - if ((int)(y+3) < (int)ch_end) - score[y+3] += 20 * ap_ratio; - if ((int)(y+4) < (int)ch_end) - score[y+4] += 10 * ap_ratio; - } - else if ((pBss->t_stamp[1] & 0x4) == 0) { + if ((int)(y - 4) >= (int)ch_begin) + score[y - 4] += 10 * ap_ratio; + if ((int)(y - 3) >= (int)ch_begin) + score[y - 3] += 20 * ap_ratio; + if ((int)(y - 2) >= (int)ch_begin) + score[y - 2] += 30 * ap_ratio; + if ((int)(y - 1) >= (int)ch_begin) + score[y - 1] += 40 * ap_ratio; + if ((int)(y + 1) < (int)ch_end) + score[y + 1] += 40 * ap_ratio; + if ((int)(y + 2) < (int)ch_end) + score[y + 2] += 30 * ap_ratio; + if ((int)(y + 3) < (int)ch_end) + score[y + 3] += 20 * ap_ratio; + if ((int)(y + 4) < (int)ch_end) + score[y + 4] += 10 * ap_ratio; + } else if ((pBss->t_stamp[1] & 0x4) == 0) { score[y] += 50 * ap_ratio; - if ((int)(y-3) >= (int)ch_begin) - score[y-3] += 20 * ap_ratio; - if ((int)(y-2) >= (int)ch_begin) - score[y-2] += 30 * ap_ratio; - if ((int)(y-1) >= (int)ch_begin) - score[y-1] += 40 * ap_ratio; - if ((int)(y+1) < (int)ch_end) - score[y+1] += 50 * ap_ratio; - if ((int)(y+2) < (int)ch_end) - score[y+2] += 50 * ap_ratio; - if ((int)(y+3) < (int)ch_end) - score[y+3] += 50 * ap_ratio; - if ((int)(y+4) < (int)ch_end) - score[y+4] += 50 * ap_ratio; - if ((int)(y+5) < (int)ch_end) - score[y+5] += 40 * ap_ratio; - if ((int)(y+6) < (int)ch_end) - score[y+6] += 30 * ap_ratio; - if ((int)(y+7) < (int)ch_end) - score[y+7] += 20 * ap_ratio; - } - else { + if ((int)(y - 3) >= (int)ch_begin) + score[y - 3] += 20 * ap_ratio; + if ((int)(y - 2) >= (int)ch_begin) + score[y - 2] += 30 * ap_ratio; + if ((int)(y - 1) >= (int)ch_begin) + score[y - 1] += 40 * ap_ratio; + if ((int)(y + 1) < (int)ch_end) + score[y + 1] += 50 * ap_ratio; + if ((int)(y + 2) < (int)ch_end) + score[y + 2] += 50 * ap_ratio; + if ((int)(y + 3) < (int)ch_end) + score[y + 3] += 50 * ap_ratio; + if ((int)(y + 4) < (int)ch_end) + score[y + 4] += 50 * ap_ratio; + if ((int)(y + 5) < (int)ch_end) + score[y + 5] += 40 * ap_ratio; + if ((int)(y + 6) < (int)ch_end) + score[y + 6] += 30 * ap_ratio; + if ((int)(y + 7) < (int)ch_end) + score[y + 7] += 20 * ap_ratio; + } else { score[y] += 50 * ap_ratio; - if ((int)(y-7) >= (int)ch_begin) - score[y-7] += 20 * ap_ratio; - if ((int)(y-6) >= (int)ch_begin) - score[y-6] += 30 * ap_ratio; - if ((int)(y-5) >= (int)ch_begin) - score[y-5] += 40 * ap_ratio; - if ((int)(y-4) >= (int)ch_begin) - score[y-4] += 50 * ap_ratio; - if ((int)(y-3) >= (int)ch_begin) - score[y-3] += 50 * ap_ratio; - if ((int)(y-2) >= (int)ch_begin) - score[y-2] += 50 * ap_ratio; - if ((int)(y-1) >= (int)ch_begin) - score[y-1] += 50 * ap_ratio; - if ((int)(y+1) < (int)ch_end) - score[y+1] += 40 * ap_ratio; - if ((int)(y+2) < (int)ch_end) - score[y+2] += 30 * ap_ratio; - if ((int)(y+3) < (int)ch_end) - score[y+3] += 20 * ap_ratio; - } - } - else { - if ((pBss->t_stamp[1] & 0x6) == 0) { - score[y] += 500; + if ((int)(y - 7) >= (int)ch_begin) + score[y - 7] += 20 * ap_ratio; + if ((int)(y - 6) >= (int)ch_begin) + score[y - 6] += 30 * ap_ratio; + if ((int)(y - 5) >= (int)ch_begin) + score[y - 5] += 40 * ap_ratio; + if ((int)(y - 4) >= (int)ch_begin) + score[y - 4] += 50 * ap_ratio; + if ((int)(y - 3) >= (int)ch_begin) + score[y - 3] += 50 * ap_ratio; + if ((int)(y - 2) >= (int)ch_begin) + score[y - 2] += 50 * ap_ratio; + if ((int)(y - 1) >= (int)ch_begin) + score[y - 1] += 50 * ap_ratio; + if ((int)(y + 1) < (int)ch_end) + score[y + 1] += 40 * ap_ratio; + if ((int)(y + 2) < (int)ch_end) + score[y + 2] += 30 * ap_ratio; + if ((int)(y + 3) < (int)ch_end) + score[y + 3] += 20 * ap_ratio; } + } else { + if ((pBss->t_stamp[1] & 0x6) == 0) + score[y] += 500; else if ((pBss->t_stamp[1] & 0x4) == 0) { score[y] += 500; - if ((int)(y+1) < (int)ch_end) - score[y+1] += 500; - } - else { + if ((int)(y + 1) < (int)ch_end) + score[y + 1] += 500; + } else { score[y] += 500; - if ((int)(y-1) >= (int)ch_begin) - score[y-1] += 500; + if ((int)(y - 1) >= (int)ch_begin) + score[y - 1] += 500; } } break; @@ -789,78 +737,75 @@ int phydm_AutoChannelSelectAP( } } -#ifdef ACS_DEBUG_INFO//for debug +#ifdef ACS_DEBUG_INFO/* for debug */ printk("\n"); - for (y=ch_begin; yavailable_chnl[y],score[y]); + for (y = ch_begin; y < ch_end; y++) + printk("6. after ap check: chnl[%d]:%d\n", priv->available_chnl[y], score[y]); printk("\n"); -#endif +#endif -#ifdef SS_CH_LOAD_PROC +#ifdef SS_CH_LOAD_PROC - // caculate noise level -- suggested by wilson - for (y=ch_begin; ychnl_ss_fa_count[y]>1000) { + /* caculate noise level -- suggested by wilson */ + for (y = ch_begin; y < ch_end; y++) { + int fa_lv = 0, cca_lv = 0; + if (priv->chnl_ss_fa_count[y] > 1000) fa_lv = 100; - } else if (priv->chnl_ss_fa_count[y]>500) { - fa_lv = 34 * (priv->chnl_ss_fa_count[y]-500) / 500 + 66; - } else if (priv->chnl_ss_fa_count[y]>200) { + else if (priv->chnl_ss_fa_count[y] > 500) + fa_lv = 34 * (priv->chnl_ss_fa_count[y] - 500) / 500 + 66; + else if (priv->chnl_ss_fa_count[y] > 200) fa_lv = 33 * (priv->chnl_ss_fa_count[y] - 200) / 300 + 33; - } else if (priv->chnl_ss_fa_count[y]>100) { + else if (priv->chnl_ss_fa_count[y] > 100) fa_lv = 18 * (priv->chnl_ss_fa_count[y] - 100) / 100 + 15; - } else { + else fa_lv = 15 * priv->chnl_ss_fa_count[y] / 100; - } - if (priv->chnl_ss_cca_count[y]>400) { + if (priv->chnl_ss_cca_count[y] > 400) cca_lv = 100; - } else if (priv->chnl_ss_cca_count[y]>200) { + else if (priv->chnl_ss_cca_count[y] > 200) cca_lv = 34 * (priv->chnl_ss_cca_count[y] - 200) / 200 + 66; - } else if (priv->chnl_ss_cca_count[y]>80) { + else if (priv->chnl_ss_cca_count[y] > 80) cca_lv = 33 * (priv->chnl_ss_cca_count[y] - 80) / 120 + 33; - } else if (priv->chnl_ss_cca_count[y]>40) { + else if (priv->chnl_ss_cca_count[y] > 40) cca_lv = 18 * (priv->chnl_ss_cca_count[y] - 40) / 40 + 15; - } else { + else cca_lv = 15 * priv->chnl_ss_cca_count[y] / 40; - } - priv->chnl_ss_load[y] = (((fa_lv > cca_lv)? fa_lv : cca_lv)*75+((score[y]>100)?100:score[y])*25)/100; - - DEBUG_INFO("ch:%d f=%d (%d), c=%d (%d), fl=%d, cl=%d, sc=%d, cu=%d\n", - priv->available_chnl[y], - priv->chnl_ss_fa_count[y], fa_thd, - priv->chnl_ss_cca_count[y], cca_thd, - fa_lv, - cca_lv, - score[y], - priv->chnl_ss_load[y]); - - } -#endif + priv->chnl_ss_load[y] = (((fa_lv > cca_lv) ? fa_lv : cca_lv) * 75 + ((score[y] > 100) ? 100 : score[y]) * 25) / 100; + + DEBUG_INFO("ch:%d f=%d (%d), c=%d (%d), fl=%d, cl=%d, sc=%d, cu=%d\n", + priv->available_chnl[y], + priv->chnl_ss_fa_count[y], fa_thd, + priv->chnl_ss_cca_count[y], cca_thd, + fa_lv, + cca_lv, + score[y], + priv->chnl_ss_load[y]); + + } +#endif } #endif choose_ch: #ifdef DFS - // heavy weighted DFS channel - if (idx_5G_begin >= 0){ - for (i=idx_5G_begin; iavailable_chnl_num; i++) { - if (!priv->pmib->dot11DFSEntry.disable_DFS && is_DFS_channel(priv->available_chnl[i]) - && (score[i]!= 0xffffffff)){ - score[i] += 1600; + /* heavy weighted DFS channel */ + if (idx_5G_begin >= 0) { + for (i = idx_5G_begin; i < priv->available_chnl_num; i++) { + if (!priv->pmib->dot11DFSEntry.disable_DFS && is_DFS_channel(priv->available_chnl[i]) + && (score[i] != 0xffffffff)) + score[i] += 1600; } } - } #endif -//prevent Auto Channel selecting wrong channel in 40M mode----------------- + /* prevent Auto channel selecting wrong channel in 40M mode----------------- */ if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) - && priv->pshare->is_40m_bw) { + && priv->pshare->is_40m_bw) { #if 0 if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 1) { - //Upper Primary Channel, cannot select the two lowest channels + /* Upper Primary channel, cannot select the two lowest channels */ if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) { score[0] = 0xffffffff; score[1] = 0xffffffff; @@ -873,13 +818,12 @@ int phydm_AutoChannelSelectAP( score[11] = 0xffffffff; } -// if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { -// score[idx_5G_begin] = 0xffffffff; -// score[idx_5G_begin + 1] = 0xffffffff; -// } - } - else if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 2) { - //Lower Primary Channel, cannot select the two highest channels + /* if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { */ + /* score[idx_5G_begin] = 0xffffffff; */ + /* score[idx_5G_begin + 1] = 0xffffffff; */ + /* } */ + } else if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 2) { + /* Lower Primary channel, cannot select the two highest channels */ if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) { score[0] = 0xffffffff; score[1] = 0xffffffff; @@ -892,33 +836,33 @@ int phydm_AutoChannelSelectAP( score[9] = 0xffffffff; } -// if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { -// score[priv->available_chnl_num - 2] = 0xffffffff; -// score[priv->available_chnl_num - 1] = 0xffffffff; -// } + /* if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { */ + /* score[priv->available_chnl_num - 2] = 0xffffffff; */ + /* score[priv->available_chnl_num - 1] = 0xffffffff; */ + /* } */ } #endif - for (i=0; i<=idx_2G_end; ++i) + for (i = 0; i <= idx_2G_end; ++i) if (priv->available_chnl[i] == 14) - score[i] = 0xffffffff; // mask chan14 + score[i] = 0xffffffff; /* mask chan14 */ #ifdef RTK_5G_SUPPORT if (idx_5G_begin >= 0) { - for (i=idx_5G_begin; iavailable_chnl_num; i++) { + for (i = idx_5G_begin; i < priv->available_chnl_num; i++) { int ch = priv->available_chnl[i]; - if(priv->available_chnl[i] > 144) + if (priv->available_chnl[i] > 144) --ch; - if((ch%4) || ch==140 || ch == 164 ) //mask ch 140, ch 165, ch 184... + if ((ch % 4) || ch == 140 || ch == 164) /* mask ch 140, ch 165, ch 184... */ score[i] = 0xffffffff; } } #endif - + } if (priv->pmib->dot11RFEntry.disable_ch1213) { - for (i=0; i<=idx_2G_end; ++i) { + for (i = 0; i <= idx_2G_end; ++i) { int ch = priv->available_chnl[i]; if ((ch == 12) || (ch == 13)) score[i] = 0xffffffff; @@ -926,33 +870,31 @@ int phydm_AutoChannelSelectAP( } if (((priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_GLOBAL) || - (priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_WORLD_WIDE)) && - (idx_2G_end >= 11) && (idx_2G_end < 14)) { - score[13] = 0xffffffff; // mask chan14 - score[12] = 0xffffffff; // mask chan13 - score[11] = 0xffffffff; // mask chan12 + (priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_WORLD_WIDE)) && + (idx_2G_end >= 11) && (idx_2G_end < 14)) { + score[13] = 0xffffffff; /* mask chan14 */ + score[12] = 0xffffffff; /* mask chan13 */ + score[11] = 0xffffffff; /* mask chan12 */ } - -//------------------------------------------------------------------ + + /* ------------------------------------------------------------------ */ #ifdef _DEBUG_RTL8192CD_ - for (i=0; iavailable_chnl_num; i++) { - len += sprintf(tmpbuf+len, "ch%d:%u ", priv->available_chnl[i], score[i]); - } + for (i = 0; i < priv->available_chnl_num; i++) + len += sprintf(tmpbuf + len, "ch%d:%u ", priv->available_chnl[i], score[i]); strcat(tmpbuf, "\n"); panic_printk("%s", tmpbuf); #endif - if ( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) - && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) - { - for (i=0; iavailable_chnl_num; i++) { + if ((*p_dm_odm->p_band_type == ODM_BAND_5G) + && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) { + for (i = 0; i < priv->available_chnl_num; i++) { if (is80MChannel(priv->available_chnl, priv->available_chnl_num, priv->available_chnl[i])) { tmpScore = 0; - for (j=0; j<4; j++) { - if ((tmpScore != 0xffffffff) && (score[i+j] != 0xffffffff)) - tmpScore += score[i+j]; + for (j = 0; j < 4; j++) { + if ((tmpScore != 0xffffffff) && (score[i + j] != 0xffffffff)) + tmpScore += score[i + j]; else tmpScore = 0xffffffff; } @@ -961,10 +903,10 @@ int phydm_AutoChannelSelectAP( minScore = tmpScore; tmpScore = 0xffffffff; - for (j=0; j<4; j++) { - if (score[i+j] < tmpScore) { - tmpScore = score[i+j]; - tmpIdx = i+j; + for (j = 0; j < 4; j++) { + if (score[i + j] < tmpScore) { + tmpScore = score[i + j]; + tmpIdx = i + j; } } @@ -974,37 +916,35 @@ int phydm_AutoChannelSelectAP( } } if (minScore == 0xffffffff) { - // there is no 80M channels + /* there is no 80M channels */ priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; - for (i=0; iavailable_chnl_num; i++) { + for (i = 0; i < priv->available_chnl_num; i++) { if (score[i] < minScore) { minScore = score[i]; idx = i; } } } - } - else if( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) - && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40)) - { - for (i=0; iavailable_chnl_num; i++) { - if(is40MChannel(priv->available_chnl,priv->available_chnl_num,priv->available_chnl[i])) { + } else if ((*p_dm_odm->p_band_type == ODM_BAND_5G) + && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40)) { + for (i = 0; i < priv->available_chnl_num; i++) { + if (is40MChannel(priv->available_chnl, priv->available_chnl_num, priv->available_chnl[i])) { tmpScore = 0; - for(j=0;j<2;j++) { - if ((tmpScore != 0xffffffff) && (score[i+j] != 0xffffffff)) - tmpScore += score[i+j]; + for (j = 0; j < 2; j++) { + if ((tmpScore != 0xffffffff) && (score[i + j] != 0xffffffff)) + tmpScore += score[i + j]; else tmpScore = 0xffffffff; } tmpScore = tmpScore / 2; - if(minScore > tmpScore) { + if (minScore > tmpScore) { minScore = tmpScore; tmpScore = 0xffffffff; - for (j=0; j<2; j++) { - if (score[i+j] < tmpScore) { - tmpScore = score[i+j]; - tmpIdx = i+j; + for (j = 0; j < 2; j++) { + if (score[i + j] < tmpScore) { + tmpScore = score[i + j]; + tmpIdx = i + j; } } @@ -1014,40 +954,35 @@ int phydm_AutoChannelSelectAP( } } if (minScore == 0xffffffff) { - // there is no 40M channels + /* there is no 40M channels */ priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; - for (i=0; iavailable_chnl_num; i++) { + for (i = 0; i < priv->available_chnl_num; i++) { if (score[i] < minScore) { minScore = score[i]; idx = i; } } } - } - else if( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) - && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) - && (priv->available_chnl_num >= 8) ) - { - u4Byte groupScore[14]; - - memset(groupScore, 0xff , sizeof(groupScore)); - for (i=0; iavailable_chnl_num-4; i++) { - if (score[i] != 0xffffffff && score[i+4] != 0xffffffff) { - groupScore[i] = score[i] + score[i+4]; - DEBUG_INFO("groupScore, ch %d,%d: %d\n", i+1, i+5, groupScore[i]); + } else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) + && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) + && (priv->available_chnl_num >= 8)) { + u32 groupScore[14]; + + memset(groupScore, 0xff, sizeof(groupScore)); + for (i = 0; i < priv->available_chnl_num - 4; i++) { + if (score[i] != 0xffffffff && score[i + 4] != 0xffffffff) { + groupScore[i] = score[i] + score[i + 4]; + DEBUG_INFO("groupScore, ch %d,%d: %d\n", i + 1, i + 5, groupScore[i]); if (groupScore[i] < minScore) { #ifdef AUTOCH_SS_SPEEDUP - if(priv->pmib->miscEntry.autoch_1611_enable) - { - if(priv->available_chnl[i]==1 || priv->available_chnl[i]==6 || priv->available_chnl[i]==11) - { + if (priv->pmib->miscEntry.autoch_1611_enable) { + if (priv->available_chnl[i] == 1 || priv->available_chnl[i] == 6 || priv->available_chnl[i] == 11) { minScore = groupScore[i]; idx = i; } - } - else + } else #endif - { + { minScore = groupScore[i]; idx = i; } @@ -1055,31 +990,26 @@ int phydm_AutoChannelSelectAP( } } - if (score[idx] < score[idx+4]) { + if (score[idx] < score[idx + 4]) { GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; - priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; } else { idx = idx + 4; GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; - priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; } - } - else - { - for (i=0; iavailable_chnl_num; i++) { + } else { + for (i = 0; i < priv->available_chnl_num; i++) { if (score[i] < minScore) { #ifdef AUTOCH_SS_SPEEDUP - if(priv->pmib->miscEntry.autoch_1611_enable) - { - if(priv->available_chnl[i]==1 || priv->available_chnl[i]==6 || priv->available_chnl[i]==11) - { + if (priv->pmib->miscEntry.autoch_1611_enable) { + if (priv->available_chnl[i] == 1 || priv->available_chnl[i] == 6 || priv->available_chnl[i] == 11) { minScore = score[i]; idx = i; } - } - else + } else #endif - { + { minScore = score[i]; idx = i; } @@ -1088,34 +1018,34 @@ int phydm_AutoChannelSelectAP( } if (IS_A_CUT_8881A(priv) && - (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) { + (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) { if ((priv->available_chnl[idx] == 36) || - (priv->available_chnl[idx] == 52) || - (priv->available_chnl[idx] == 100) || - (priv->available_chnl[idx] == 116) || - (priv->available_chnl[idx] == 132) || - (priv->available_chnl[idx] == 149) || - (priv->available_chnl[idx] == 165)) + (priv->available_chnl[idx] == 52) || + (priv->available_chnl[idx] == 100) || + (priv->available_chnl[idx] == 116) || + (priv->available_chnl[idx] == 132) || + (priv->available_chnl[idx] == 149) || + (priv->available_chnl[idx] == 165)) idx++; else if ((priv->available_chnl[idx] == 48) || - (priv->available_chnl[idx] == 64) || - (priv->available_chnl[idx] == 112) || - (priv->available_chnl[idx] == 128) || - (priv->available_chnl[idx] == 144) || - (priv->available_chnl[idx] == 161) || - (priv->available_chnl[idx] == 177)) + (priv->available_chnl[idx] == 64) || + (priv->available_chnl[idx] == 112) || + (priv->available_chnl[idx] == 128) || + (priv->available_chnl[idx] == 144) || + (priv->available_chnl[idx] == 161) || + (priv->available_chnl[idx] == 177)) idx--; } minChan = priv->available_chnl[idx]; - // skip channel 14 if don't support ofdm + /* skip channel 14 if don't support ofdm */ if ((priv->pmib->dot11RFEntry.disable_ch14_ofdm) && - (minChan == 14)) { + (minChan == 14)) { score[idx] = 0xffffffff; - + minScore = 0xffffffff; - for (i=0; iavailable_chnl_num; i++) { + for (i = 0; i < priv->available_chnl_num; i++) { if (score[i] < minScore) { minScore = score[i]; idx = i; @@ -1125,25 +1055,20 @@ int phydm_AutoChannelSelectAP( } #if 0 - //Check if selected channel available for 80M/40M BW or NOT ? - if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) - { - if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80) - { - if(!is80MChannel(priv->available_chnl,priv->available_chnl_num,minChan)) - { - //printk("BW=80M, selected channel = %d is unavaliable! reduce to 40M\n", minChan); - //priv->pmib->dot11nConfigEntry.dot11nUse40M = HT_CHANNEL_WIDTH_20_40; + /* Check if selected channel available for 80M/40M BW or NOT ? */ + if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + if (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80) { + if (!is80MChannel(priv->available_chnl, priv->available_chnl_num, minChan)) { + + /* priv->pmib->dot11n_config_entry.dot11nUse40M = HT_CHANNEL_WIDTH_20_40; */ priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20_40; } } - - if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) - { - if(!is40MChannel(priv->available_chnl,priv->available_chnl_num,minChan)) - { - //printk("BW=40M, selected channel = %d is unavaliable! reduce to 20M\n", minChan); - //priv->pmib->dot11nConfigEntry.dot11nUse40M = HT_CHANNEL_WIDTH_20; + + if (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) { + if (!is40MChannel(priv->available_chnl, priv->available_chnl_num, minChan)) { + + /* priv->pmib->dot11n_config_entry.dot11nUse40M = HT_CHANNEL_WIDTH_20; */ priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; } } @@ -1154,13 +1079,13 @@ int phydm_AutoChannelSelectAP( RTL_W32(RXERR_RPT, RXERR_RPT_RST); #endif -// auto adjust contro-sideband + /* auto adjust contro-sideband */ if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) - && (priv->pshare->is_40m_bw ==1 || priv->pshare->is_40m_bw ==2)) { + && (priv->pshare->is_40m_bw == 1 || priv->pshare->is_40m_bw == 2)) { #ifdef RTK_5G_SUPPORT - if (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) { - if( (minChan>144) ? ((minChan-1)%8) : (minChan%8)) { + if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + if ((minChan > 144) ? ((minChan - 1) % 8) : (minChan % 8)) { GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; } else { @@ -1169,7 +1094,7 @@ int phydm_AutoChannelSelectAP( } } else -#endif +#endif { #if 0 #ifdef CONFIG_RTL_NEW_AUTOCH @@ -1180,8 +1105,8 @@ int phydm_AutoChannelSelectAP( else ch_max = priv->available_chnl[idx_2G_end]; - if ((minChan >= 5) && (minChan <= (ch_max-5))) { - if (score[minChan+4] > score[minChan-4]) { // what if some channels were cancelled? + if ((minChan >= 5) && (minChan <= (ch_max - 5))) { + if (score[minChan + 4] > score[minChan - 4]) { /* what if some channels were cancelled? */ GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; } else { @@ -1194,8 +1119,7 @@ int phydm_AutoChannelSelectAP( if (minChan < 5) { GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; - } - else if (minChan > 7) { + } else if (minChan > 7) { GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; } @@ -1203,7 +1127,7 @@ int phydm_AutoChannelSelectAP( #endif } } -//----------------------- + /* ----------------------- */ #if defined(__ECOS) && defined(CONFIG_SDIO_HCI) panic_printk("Auto channel choose ch:%d\n", minChan); @@ -1212,15 +1136,12 @@ int phydm_AutoChannelSelectAP( panic_printk("Auto channel choose ch:%d\n", minChan); #endif #endif -#ifdef ACS_DEBUG_INFO//for debug +#ifdef ACS_DEBUG_INFO/* for debug */ printk("7. minChan:%d 2nd_offset:%d\n", minChan, priv->pshare->offset_2nd_chan); #endif return minChan; } -*/ - #endif - - +#endif diff --git a/hal/phydm/phydm_acs.h b/hal/phydm/phydm_acs.h index a12e120..e54d686 100644 --- a/hal/phydm/phydm_acs.h +++ b/hal/phydm/phydm_acs.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,13 +11,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - + *****************************************************************************/ + #ifndef __PHYDMACS_H__ #define __PHYDMACS_H__ @@ -27,80 +22,79 @@ #define ODM_MAX_CHANNEL_2G 14 #define ODM_MAX_CHANNEL_5G 24 -// For phydm_AutoChannelSelectSettingAP() +/* For phydm_auto_channel_select_setting_ap() */ #define STORE_DEFAULT_NHM_SETTING 0 #define RESTORE_DEFAULT_NHM_SETTING 1 #define ACS_NHM_SETTING 2 -typedef struct _ACS_ -{ - BOOLEAN bForceACSResult; - u1Byte CleanChannel_2G; - u1Byte CleanChannel_5G; - u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times - u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G]; - -#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) - u1Byte ACS_Step; - // NHM Count 0-11 - u1Byte NHM_Cnt[14][11]; - - // AC-Series, for storing previous setting - u4Byte Reg0x990; - u4Byte Reg0x994; - u4Byte Reg0x998; - u4Byte Reg0x99C; - u1Byte Reg0x9A0; // u1Byte - - // N-Series, for storing previous setting - u4Byte Reg0x890; - u4Byte Reg0x894; - u4Byte Reg0x898; - u4Byte Reg0x89C; - u1Byte Reg0xE28; // u1Byte +struct _ACS_ { + boolean is_force_acs_result; + u8 clean_channel_2g; + u8 clean_channel_5g; + u16 channel_info_2g[2][ODM_MAX_CHANNEL_2G]; /* Channel_Info[1]: channel score, Channel_Info[2]:Channel_Scan_Times */ + u16 channel_info_5g[2][ODM_MAX_CHANNEL_5G]; + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + u8 acs_step; + /* NHM count 0-11 */ + u8 nhm_cnt[14][11]; + + /* AC-Series, for storing previous setting */ + u32 reg0x990; + u32 reg0x994; + u32 reg0x998; + u32 reg0x99c; + u8 reg0x9a0; /* u8 */ + + /* N-Series, for storing previous setting */ + u32 reg0x890; + u32 reg0x894; + u32 reg0x898; + u32 reg0x89c; + u8 reg0xe28; /* u8 */ #endif -}ACS, *PACS; +}; -VOID -odm_AutoChannelSelectInit( - IN PVOID pDM_VOID +void +odm_auto_channel_select_init( + void *p_dm_void ); -VOID -odm_AutoChannelSelectReset( - IN PVOID pDM_VOID +void +odm_auto_channel_select_reset( + void *p_dm_void ); -VOID -odm_AutoChannelSelect( - IN PVOID pDM_VOID, - IN u1Byte Channel +void +odm_auto_channel_select( + void *p_dm_void, + u8 channel ); -u1Byte -ODM_GetAutoChannelSelectResult( - IN PVOID pDM_VOID, - IN u1Byte Band +u8 +odm_get_auto_channel_select_result( + void *p_dm_void, + u8 band ); -#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -phydm_AutoChannelSelectSettingAP( - IN PVOID pDM_VOID, - IN u4Byte Setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING - IN u4Byte acs_step +void +phydm_auto_channel_select_setting_ap( + void *p_dm_void, + u32 setting, /* 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING */ + u32 acs_step ); -VOID -phydm_GetNHMStatisticsAP( - IN PVOID pDM_VOID, - IN u4Byte idx, // @ 2G, Real channel number = idx+1 - IN u4Byte acs_step +void +phydm_get_nhm_statistics_ap( + void *p_dm_void, + u32 idx, /* @ 2G, Real channel number = idx+1 */ + u32 acs_step ); -#endif //#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) +#endif /* #if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) */ -#endif //#ifndef __PHYDMACS_H__ \ No newline at end of file +#endif /* #ifndef __PHYDMACS_H__ */ diff --git a/hal/phydm/phydm_adaptivity.c b/hal/phydm/phydm_adaptivity.c index 956147a..8cf5e5c 100644 --- a/hal/phydm/phydm_adaptivity.c +++ b/hal/phydm/phydm_adaptivity.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,988 +11,800 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if WPP_SOFTWARE_TRACE -#include "PhyDM_Adaptivity.tmh" -#endif + #if WPP_SOFTWARE_TRACE + #include "PhyDM_Adaptivity.tmh" + #endif #endif -VOID -Phydm_CheckAdaptivity( - IN PVOID pDM_VOID +void +phydm_check_adaptivity( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); - - if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) { + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + + if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (pDM_Odm->APTotalNum > Adaptivity->APNumTH) { - pDM_Odm->Adaptivity_enable = FALSE; - pDM_Odm->adaptivity_flag = FALSE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", Adaptivity->APNumTH)); - } else + if (p_dm_odm->ap_total_num > adaptivity->ap_num_th) { + p_dm_odm->adaptivity_enable = false; + p_dm_odm->adaptivity_flag = false; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", adaptivity->ap_num_th)); + } else { #endif - { - if (Adaptivity->DynamicLinkAdaptivity || Adaptivity->AcsForAdaptivity) { - if (pDM_Odm->bLinked && Adaptivity->bCheck == FALSE) { - Phydm_NHMCounterStatistics(pDM_Odm); - Phydm_CheckEnvironment(pDM_Odm); - } else if (!pDM_Odm->bLinked) - Adaptivity->bCheck = FALSE; + if (adaptivity->dynamic_link_adaptivity || adaptivity->acs_for_adaptivity) { + if (p_dm_odm->is_linked && adaptivity->is_check == false) { + phydm_nhm_counter_statistics(p_dm_odm); + phydm_check_environment(p_dm_odm); + } else if (!p_dm_odm->is_linked) + adaptivity->is_check = false; } else { - pDM_Odm->Adaptivity_enable = TRUE; + p_dm_odm->adaptivity_enable = true; - if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) - pDM_Odm->adaptivity_flag = FALSE; + if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) + p_dm_odm->adaptivity_flag = false; else - pDM_Odm->adaptivity_flag = TRUE; + p_dm_odm->adaptivity_flag = true; } +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) } +#endif } else { - pDM_Odm->Adaptivity_enable = FALSE; - pDM_Odm->adaptivity_flag = FALSE; + p_dm_odm->adaptivity_enable = false; + p_dm_odm->adaptivity_flag = false; } - - - } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -BOOLEAN -Phydm_CheckChannelPlan( - IN PVOID pDM_VOID +boolean +phydm_check_channel_plan( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER pAdapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); - - if (pMgntInfo->RegEnableAdaptivity == 2) { - if (pDM_Odm->Carrier_Sense_enable == FALSE) { /*check domain Code for Adaptivity or CarrierSense*/ - if ((*pDM_Odm->pBandType == ODM_BAND_5G) && - !(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G)); - pDM_Odm->Adaptivity_enable = FALSE; - pDM_Odm->adaptivity_flag = FALSE; - return TRUE; - } else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) && - !(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G)); - pDM_Odm->Adaptivity_enable = FALSE; - pDM_Odm->adaptivity_flag = FALSE; - return TRUE; - - } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n")); - pDM_Odm->Adaptivity_enable = FALSE; - pDM_Odm->adaptivity_flag = FALSE; - return TRUE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + PMGNT_INFO p_mgnt_info = &(p_adapter->MgntInfo); + + if (p_mgnt_info->RegEnableAdaptivity == 2) { + if (p_dm_odm->carrier_sense_enable == false) { /*check domain Code for adaptivity or CarrierSense*/ + if ((*p_dm_odm->p_band_type == ODM_BAND_5G) && + !(p_dm_odm->odm_regulation_5g == REGULATION_ETSI || p_dm_odm->odm_regulation_5g == REGULATION_WW)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity skip 5G domain code : %d\n", p_dm_odm->odm_regulation_5g)); + p_dm_odm->adaptivity_enable = false; + p_dm_odm->adaptivity_flag = false; + return true; + } else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) && + !(p_dm_odm->odm_regulation_2_4g == REGULATION_ETSI || p_dm_odm->odm_regulation_2_4g == REGULATION_WW)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity skip 2.4G domain code : %d\n", p_dm_odm->odm_regulation_2_4g)); + p_dm_odm->adaptivity_enable = false; + p_dm_odm->adaptivity_flag = false; + return true; + + } else if ((*p_dm_odm->p_band_type != ODM_BAND_2_4G) && (*p_dm_odm->p_band_type != ODM_BAND_5G)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity neither 2G nor 5G band, return\n")); + p_dm_odm->adaptivity_enable = false; + p_dm_odm->adaptivity_flag = false; + return true; } } else { - if ((*pDM_Odm->pBandType == ODM_BAND_5G) && - !(pDM_Odm->odm_Regulation5G == REGULATION_MKK || pDM_Odm->odm_Regulation5G == REGULATION_WW)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G)); - pDM_Odm->Adaptivity_enable = FALSE; - pDM_Odm->adaptivity_flag = FALSE; - return TRUE; + if ((*p_dm_odm->p_band_type == ODM_BAND_5G) && + !(p_dm_odm->odm_regulation_5g == REGULATION_MKK || p_dm_odm->odm_regulation_5g == REGULATION_WW)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", p_dm_odm->odm_regulation_5g)); + p_dm_odm->adaptivity_enable = false; + p_dm_odm->adaptivity_flag = false; + return true; } - else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) && - !(pDM_Odm->odm_Regulation2_4G == REGULATION_MKK || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G)); - pDM_Odm->Adaptivity_enable = FALSE; - pDM_Odm->adaptivity_flag = FALSE; - return TRUE; - - } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n")); - pDM_Odm->Adaptivity_enable = FALSE; - pDM_Odm->adaptivity_flag = FALSE; - return TRUE; + else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) && + !(p_dm_odm->odm_regulation_2_4g == REGULATION_MKK || p_dm_odm->odm_regulation_2_4g == REGULATION_WW)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", p_dm_odm->odm_regulation_2_4g)); + p_dm_odm->adaptivity_enable = false; + p_dm_odm->adaptivity_flag = false; + return true; + + } else if ((*p_dm_odm->p_band_type != ODM_BAND_2_4G) && (*p_dm_odm->p_band_type != ODM_BAND_5G)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n")); + p_dm_odm->adaptivity_enable = false; + p_dm_odm->adaptivity_flag = false; + return true; } } } - return FALSE; - -} -#endif - -VOID -Phydm_NHMCounterStatisticsInit( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - /*PHY parameters initialize for n series*/ - ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11N+ 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ - ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/ - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/ - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); /*0xe28[7:0]=0xff th_8*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10 | BIT9 | BIT8, 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); /*0xc0c[7]=1 max power among all RX ants*/ - } -#if (RTL8195A_SUPPORT == 0) - else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - /*PHY parameters initialize for ac series*/ - ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+ 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ - ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/ - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/ - ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); /*0x9a0[7:0]=0xff th_8*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8 | BIT9 | BIT10, 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); /*0x9e8[7]=1 max power among all RX ants*/ - - } -#endif -} - -VOID -Phydm_NHMCounterStatistics( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) - return; + return false; - /*Get NHM report*/ - Phydm_GetNHMCounterStatistics(pDM_Odm); - - /*Reset NHM counter*/ - Phydm_NHMCounterStatisticsReset(pDM_Odm); } - -VOID -Phydm_GetNHMCounterStatistics( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32 = 0; -#if (RTL8195A_SUPPORT == 0) - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord); - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) #endif - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord); - pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0); - pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1) >> 8); - -} - -VOID -Phydm_NHMCounterStatisticsReset( - IN PVOID pDM_VOID +void +phydm_set_edcca_threshold( + void *p_dm_void, + s8 H2L, + s8 L2H ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1); - } + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)L2H | (u8)H2L << 16)); #if (RTL8195A_SUPPORT == 0) - else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1); - } - + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)L2H | (u8)H2L << 8)); #endif } -VOID -Phydm_SetEDCCAThreshold( - IN PVOID pDM_VOID, - IN s1Byte H2L, - IN s1Byte L2H +void +phydm_set_lna( + void *p_dm_void, + enum phydm_set_lna type ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)((u1Byte)L2H|(u1Byte)H2L<<16)); -#if (RTL8195A_SUPPORT == 0) - else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)((u1Byte)L2H|(u1Byte)H2L<<8)); -#endif - -} - -VOID -Phydm_SetLNA( - IN PVOID pDM_VOID, - IN PhyDM_set_LNA type -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8192E)) { - if (type == PhyDM_disable_LNA) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - if (pDM_Odm->RFType > ODM_1T1R) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E)) { + if (type == phydm_disable_lna) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + if (p_dm_odm->rf_type > ODM_1T1R) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); } - } else if (type == PhyDM_enable_LNA) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - if (pDM_Odm->RFType > ODM_1T1R) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + } else if (type == phydm_enable_lna) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + if (p_dm_odm->rf_type > ODM_1T1R) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); } } - } else if (pDM_Odm->SupportICType & ODM_RTL8723B) { - if (type == PhyDM_disable_LNA) { + } else if (p_dm_odm->support_ic_type & ODM_RTL8723B) { + if (type == phydm_disable_lna) { /*S0*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); /*S1*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0); - } else if (type == PhyDM_enable_LNA) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0); + } else if (type == phydm_enable_lna) { /*S0*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); /*S1*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0); } - - } else if (pDM_Odm->SupportICType & ODM_RTL8812) { - if (type == PhyDM_disable_LNA) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - if (pDM_Odm->RFType > ODM_1T1R) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); - } - } else if (type == PhyDM_enable_LNA) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - if (pDM_Odm->RFType > ODM_1T1R) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); - } + + } else if (p_dm_odm->support_ic_type & ODM_RTL8812) { + if (type == phydm_disable_lna) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + if (p_dm_odm->rf_type > ODM_1T1R) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + } + } else if (type == phydm_enable_lna) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + if (p_dm_odm->rf_type > ODM_1T1R) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + } } - } else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A)) { - if (type == PhyDM_disable_LNA) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - } else if (type == PhyDM_enable_LNA) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { + if (type == phydm_disable_lna) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + } else if (type == phydm_enable_lna) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); } } } -VOID -Phydm_SetTRxMux( - IN PVOID pDM_VOID, - IN PhyDM_Trx_MUX_Type txMode, - IN PhyDM_Trx_MUX_Type rxMode +void +phydm_set_trx_mux( + void *p_dm_void, + enum phydm_trx_mux_type tx_mode, + enum phydm_trx_mux_type rx_mode ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/ - if (pDM_Odm->RFType > ODM_1T1R) { - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(3) | BIT(2) | BIT(1), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(22) | BIT(21) | BIT(20), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ + if (p_dm_odm->rf_type > ODM_1T1R) { + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(3) | BIT(2) | BIT(1), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(22) | BIT(21) | BIT(20), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ } } #if (RTL8195A_SUPPORT == 0) - else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/ - if (pDM_Odm->RFType > ODM_1T1R) { - ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/ + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ + if (p_dm_odm->rf_type > ODM_1T1R) { + odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC_B, BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC_B, BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ } } #endif } -VOID -Phydm_MACEDCCAState( - IN PVOID pDM_VOID, - IN PhyDM_MACEDCCA_Type State +void +phydm_mac_edcca_state( + void *p_dm_void, + enum phydm_mac_edcca_type state ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if (State == PhyDM_IGNORE_EDCCA) { - ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1); /*ignore EDCCA reg520[15]=1*/ -/* ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0); *//*reg524[11]=0*/ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + if (state == phydm_ignore_edcca) { + odm_set_mac_reg(p_dm_odm, REG_TX_PTCL_CTRL, BIT(15), 1); /*ignore EDCCA reg520[15]=1*/ + /* odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 0); */ /*reg524[11]=0*/ } else { /*don't set MAC ignore EDCCA signal*/ - ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); /*don't ignore EDCCA reg520[15]=0*/ -/* ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); *//*reg524[11]=1 */ + odm_set_mac_reg(p_dm_odm, REG_TX_PTCL_CTRL, BIT(15), 0); /*don't ignore EDCCA reg520[15]=0*/ + /* odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 1); */ /*reg524[11]=1 */ } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d\n", State)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable state = %d\n", state)); } -BOOLEAN -Phydm_CalNHMcnt( - IN PVOID pDM_VOID +void +phydm_check_environment( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte Base = 0; - - Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1; - - if (Base != 0) { - pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base; - pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base; - } - if ((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100) - return TRUE; /*clean environment*/ - else - return FALSE; /*noisy environment*/ - -} - - -VOID -Phydm_CheckEnvironment( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); - BOOLEAN isCleanEnvironment = FALSE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + boolean is_clean_environment = false; #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - prtl8192cd_priv priv = pDM_Odm->priv; + struct rtl8192cd_priv *priv = p_dm_odm->priv; #endif - if (Adaptivity->bFirstLink == TRUE) { - if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) - pDM_Odm->adaptivity_flag = FALSE; + if (adaptivity->is_first_link == true) { + if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) + p_dm_odm->adaptivity_flag = false; else - pDM_Odm->adaptivity_flag = TRUE; + p_dm_odm->adaptivity_flag = true; - Adaptivity->bFirstLink = FALSE; + adaptivity->is_first_link = false; return; - } else { - if (Adaptivity->NHMWait < 3) { /*Start enter NHM after 4 NHMWait*/ - Adaptivity->NHMWait++; - Phydm_NHMCounterStatistics(pDM_Odm); - return; - } else { - Phydm_NHMCounterStatistics(pDM_Odm); - isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm); - if (isCleanEnvironment == TRUE) { - pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup; /*adaptivity mode*/ - pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup; + } - pDM_Odm->Adaptivity_enable = TRUE; + if (adaptivity->nhm_wait < 3) { /*Start enter NHM after 4 nhm_wait*/ + adaptivity->nhm_wait++; + phydm_nhm_counter_statistics(p_dm_odm); + return; + } - if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) - pDM_Odm->adaptivity_flag = FALSE; - else - pDM_Odm->adaptivity_flag = TRUE; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - priv->pshare->rf_ft_var.isCleanEnvironment = TRUE; -#endif - } else { - if (!Adaptivity->AcsForAdaptivity) { - pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; /*mode2*/ - pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2; + phydm_nhm_counter_statistics(p_dm_odm); + is_clean_environment = phydm_cal_nhm_cnt(p_dm_odm); + + if (is_clean_environment == true) { + p_dm_odm->th_l2h_ini = adaptivity->th_l2h_ini_backup; /*adaptivity mode*/ + p_dm_odm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup; - pDM_Odm->adaptivity_flag = FALSE; - pDM_Odm->Adaptivity_enable = FALSE; - } + p_dm_odm->adaptivity_enable = true; + + if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) + p_dm_odm->adaptivity_flag = false; + else + p_dm_odm->adaptivity_flag = true; #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - priv->pshare->rf_ft_var.isCleanEnvironment = FALSE; + priv->pshare->rf_ft_var.is_clean_environment = true; #endif - } - Adaptivity->NHMWait = 0; - Adaptivity->bFirstLink = TRUE; - Adaptivity->bCheck = TRUE; - } + } else { + if (!adaptivity->acs_for_adaptivity) { + p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2; /*mode2*/ + p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2; + p_dm_odm->adaptivity_flag = false; + p_dm_odm->adaptivity_enable = false; + } +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + priv->pshare->rf_ft_var.is_clean_environment = false; +#endif } + adaptivity->nhm_wait = 0; + adaptivity->is_first_link = true; + adaptivity->is_check = true; } -VOID -Phydm_SearchPwdBLowerBound( - IN PVOID pDM_VOID +void +phydm_search_pwdb_lower_bound( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); - u4Byte value32 = 0; - u1Byte cnt; - u1Byte txEdcca1 = 0, txEdcca0 = 0; - BOOLEAN bAdjust = TRUE; - s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32; - s1Byte Diff; - u1Byte IGI = Adaptivity->IGI_Base + 30 + (u1Byte)pDM_Odm->TH_L2H_ini - (u1Byte)pDM_Odm->TH_EDCCA_HL_diff; - - if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) - Phydm_SetLNA(pDM_Odm, PhyDM_disable_LNA); - else { - Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE); - odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e); - } + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + u32 value32 = 0, reg_value32 = 0; + u8 cnt, try_count = 0; + u8 tx_edcca1 = 0; + boolean is_adjust = true; + s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32; + s8 diff; + u8 IGI = adaptivity->igi_base + 30 + (u8)p_dm_odm->th_l2h_ini - (u8)p_dm_odm->th_edcca_hl_diff; + + if (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) + phydm_set_lna(p_dm_odm, phydm_disable_lna); + + diff = igi_target - (s8)IGI; + th_l2h_dmc = p_dm_odm->th_l2h_ini + diff; + if (th_l2h_dmc > 10) + th_l2h_dmc = 10; + + th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + ODM_delay_ms(30); + + while (is_adjust) { + + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/ + reg_value32 = phydm_get_bb_dbg_port_value(p_dm_odm); + + while (reg_value32 & BIT(3) && try_count < 3) { + ODM_delay_ms(3); + try_count = try_count + 1; + reg_value32 = phydm_get_bb_dbg_port_value(p_dm_odm); + } + phydm_release_bb_dbg_port(p_dm_odm); + try_count = 0; + } - Diff = IGI_target - (s1Byte)IGI; - TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff; - if (TH_L2H_dmc > 10) - TH_L2H_dmc = 10; - TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; + for (cnt = 0; cnt < 20; cnt++) { - Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc); - ODM_delay_ms(5); + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) { + value32 = phydm_get_bb_dbg_port_value(p_dm_odm); + phydm_release_bb_dbg_port(p_dm_odm); + } - while (bAdjust) { - for (cnt = 0; cnt < 20; cnt++) { - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord); -#if (RTL8195A_SUPPORT == 0) - else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord); -#endif - if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E))) - txEdcca1 = txEdcca1 + 1; - else if (value32 & BIT29) - txEdcca1 = txEdcca1 + 1; - else - txEdcca0 = txEdcca0 + 1; + if (value32 & BIT(30) && (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))) + tx_edcca1 = tx_edcca1 + 1; + else if (value32 & BIT(29)) + tx_edcca1 = tx_edcca1 + 1; } - if (txEdcca1 > 1) { + if (tx_edcca1 > 1) { IGI = IGI - 1; - TH_L2H_dmc = TH_L2H_dmc + 1; - if (TH_L2H_dmc > 10) - TH_L2H_dmc = 10; - TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; - - Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc); - if (TH_L2H_dmc == 10) { - bAdjust = FALSE; - Adaptivity->H2L_lb = TH_H2L_dmc; - Adaptivity->L2H_lb = TH_L2H_dmc; - pDM_Odm->Adaptivity_IGI_upper = IGI; - } + th_l2h_dmc = th_l2h_dmc + 1; + if (th_l2h_dmc > 10) + th_l2h_dmc = 10; - txEdcca1 = 0; - txEdcca0 = 0; + th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + tx_edcca1 = 0; + if (th_l2h_dmc == 10) + is_adjust = false; + + } else + is_adjust = false; - } else { - bAdjust = FALSE; - Adaptivity->H2L_lb = TH_H2L_dmc; - Adaptivity->L2H_lb = TH_L2H_dmc; - pDM_Odm->Adaptivity_IGI_upper = IGI; - txEdcca1 = 0; - txEdcca0 = 0; - } } - pDM_Odm->Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper - pDM_Odm->DCbackoff; - Adaptivity->H2L_lb = Adaptivity->H2L_lb + pDM_Odm->DCbackoff; - Adaptivity->L2H_lb = Adaptivity->L2H_lb + pDM_Odm->DCbackoff; + p_dm_odm->adaptivity_igi_upper = IGI - p_dm_odm->dc_backoff; + adaptivity->h2l_lb = th_h2l_dmc + p_dm_odm->dc_backoff; + adaptivity->l2h_lb = th_l2h_dmc + p_dm_odm->dc_backoff; - if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) - Phydm_SetLNA(pDM_Odm, PhyDM_enable_LNA); - else { - Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE); - odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE); - } - - Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); /*resume to no link state*/ + if (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) + phydm_set_lna(p_dm_odm, phydm_enable_lna); + + phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f); /*resume to no link state*/ } -BOOLEAN -phydm_reSearchCondition( - IN PVOID pDM_VOID +boolean +phydm_re_search_condition( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - /*PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);*/ - u1Byte Adaptivity_IGI_upper; - /*s1Byte TH_L2H_dmc, IGI_target = 0x32;*/ - /*s1Byte Diff;*/ - - Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper + pDM_Odm->DCbackoff; - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 adaptivity_igi_upper; + /*s8 TH_L2H_dmc, IGI_target = 0x32;*/ + /*s8 diff;*/ + + adaptivity_igi_upper = p_dm_odm->adaptivity_igi_upper + p_dm_odm->dc_backoff; + /*TH_L2H_dmc = 10;*/ - /*Diff = TH_L2H_dmc - pDM_Odm->TH_L2H_ini;*/ - /*lowest_IGI_upper = IGI_target - Diff;*/ + /*diff = TH_L2H_dmc - p_dm_odm->TH_L2H_ini;*/ + /*lowest_IGI_upper = IGI_target - diff;*/ + /*if ((adaptivity_igi_upper - lowest_IGI_upper) <= 5)*/ - /*if ((Adaptivity_IGI_upper - lowest_IGI_upper) <= 5)*/ - if (Adaptivity_IGI_upper <= 0x26) - return TRUE; + if (adaptivity_igi_upper <= 0x26) + return true; else - return FALSE; - + return false; } -VOID -phydm_adaptivityInfoInit( - IN PVOID pDM_VOID, - IN PHYDM_ADAPINFO_E CmnInfo, - IN u4Byte Value - ) +void +phydm_adaptivity_info_init( + void *p_dm_void, + enum phydm_adapinfo_e cmn_info, + u32 value +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); - switch (CmnInfo) { + switch (cmn_info) { case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE: - pDM_Odm->Carrier_Sense_enable = (BOOLEAN)Value; - break; + p_dm_odm->carrier_sense_enable = (boolean)value; + break; case PHYDM_ADAPINFO_DCBACKOFF: - pDM_Odm->DCbackoff = (u1Byte)Value; - break; + p_dm_odm->dc_backoff = (u8)value; + break; case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY: - Adaptivity->DynamicLinkAdaptivity = (BOOLEAN)Value; - break; + adaptivity->dynamic_link_adaptivity = (boolean)value; + break; case PHYDM_ADAPINFO_TH_L2H_INI: - pDM_Odm->TH_L2H_ini = (s1Byte)Value; - break; + p_dm_odm->th_l2h_ini = (s8)value; + break; case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF: - pDM_Odm->TH_EDCCA_HL_diff = (s1Byte)Value; - break; + p_dm_odm->th_edcca_hl_diff = (s8)value; + break; case PHYDM_ADAPINFO_AP_NUM_TH: - Adaptivity->APNumTH = (u1Byte)Value; - break; + adaptivity->ap_num_th = (u8)value; + break; default: - break; - + break; + } } -VOID -Phydm_AdaptivityInit( - IN PVOID pDM_VOID +void +phydm_adaptivity_init( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); - s1Byte IGItarget = 0x32; - /*pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;*/ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + s8 igi_target = 0x32; + /*struct _dynamic_initial_gain_threshold_* p_dm_dig_table = &p_dm_odm->dm_dig_table;*/ -#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) - if (pDM_Odm->Carrier_Sense_enable == FALSE) { - if (pDM_Odm->TH_L2H_ini == 0) - pDM_Odm->TH_L2H_ini = 0xf5; + if (p_dm_odm->carrier_sense_enable == false) { + if (p_dm_odm->th_l2h_ini == 0) + phydm_set_l2h_th_ini(p_dm_odm); } else - pDM_Odm->TH_L2H_ini = 0xa; + p_dm_odm->th_l2h_ini = 0xa; - if (pDM_Odm->TH_EDCCA_HL_diff == 0) - pDM_Odm->TH_EDCCA_HL_diff = 7; -#if(DM_ODM_SUPPORT_TYPE & (ODM_CE)) - if (pDM_Odm->WIFITest == TRUE || pDM_Odm->mp_mode == TRUE) + if (p_dm_odm->th_edcca_hl_diff == 0) + p_dm_odm->th_edcca_hl_diff = 7; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + if (p_dm_odm->wifi_test == true || *(p_dm_odm->p_mp_mode) == true) #else - if ((pDM_Odm->WIFITest & RT_WIFI_LOGO) == TRUE) + if ((p_dm_odm->wifi_test & RT_WIFI_LOGO) == true) #endif - pDM_Odm->EDCCA_enable = FALSE; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/ + p_dm_odm->edcca_enable = false; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/ else - pDM_Odm->EDCCA_enable = TRUE; + p_dm_odm->edcca_enable = true; #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) - prtl8192cd_priv priv = pDM_Odm->priv; + struct rtl8192cd_priv *priv = p_dm_odm->priv; - if (pDM_Odm->Carrier_Sense_enable) { - pDM_Odm->TH_L2H_ini = 0xa; - pDM_Odm->TH_EDCCA_HL_diff = 7; + if (p_dm_odm->carrier_sense_enable) { + p_dm_odm->th_l2h_ini = 0xa; + p_dm_odm->th_edcca_hl_diff = 7; } else { - pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_default; /*set by mib*/ - pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_default; + p_dm_odm->th_l2h_ini = p_dm_odm->TH_L2H_default; /*set by mib*/ + p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_default; } if (priv->pshare->rf_ft_var.adaptivity_enable == 3) - Adaptivity->AcsForAdaptivity = TRUE; - else - Adaptivity->AcsForAdaptivity = FALSE; + adaptivity->acs_for_adaptivity = true; + else + adaptivity->acs_for_adaptivity = false; if (priv->pshare->rf_ft_var.adaptivity_enable == 2) - Adaptivity->DynamicLinkAdaptivity = TRUE; + adaptivity->dynamic_link_adaptivity = true; else - Adaptivity->DynamicLinkAdaptivity = FALSE; - - priv->pshare->rf_ft_var.isCleanEnvironment = FALSE; - -#endif - - pDM_Odm->Adaptivity_IGI_upper = 0; - pDM_Odm->Adaptivity_enable = FALSE; /*use this flag to decide enable or disable*/ - - pDM_Odm->TH_L2H_ini_mode2 = 20; - pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8; - Adaptivity->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini; - Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff; - - Adaptivity->IGI_Base = 0x32; - Adaptivity->IGI_target = 0x1c; - Adaptivity->H2L_lb = 0; - Adaptivity->L2H_lb = 0; - Adaptivity->NHMWait = 0; - Adaptivity->bCheck = FALSE; - Adaptivity->bFirstLink = TRUE; - Adaptivity->AdajustIGILevel = 0; - Adaptivity->bStopEDCCA = FALSE; - Adaptivity->backupH2L = 0; - Adaptivity->backupL2H = 0; - - Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA); - - /*Search pwdB lower bound*/ - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208); -#if (RTL8195A_SUPPORT == 0) - else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209); + adaptivity->dynamic_link_adaptivity = false; + + priv->pshare->rf_ft_var.is_clean_environment = false; + +#endif + + p_dm_odm->adaptivity_igi_upper = 0; + p_dm_odm->adaptivity_enable = false; /*use this flag to decide enable or disable*/ + + p_dm_odm->th_l2h_ini_mode2 = 20; + p_dm_odm->th_edcca_hl_diff_mode2 = 8; + adaptivity->debug_mode = false; + adaptivity->th_l2h_ini_backup = p_dm_odm->th_l2h_ini; + adaptivity->th_edcca_hl_diff_backup = p_dm_odm->th_edcca_hl_diff; + + adaptivity->igi_base = 0x32; + adaptivity->igi_target = 0x1c; + adaptivity->h2l_lb = 0; + adaptivity->l2h_lb = 0; + adaptivity->nhm_wait = 0; + adaptivity->is_check = false; + adaptivity->is_first_link = true; + adaptivity->adajust_igi_level = 0; + adaptivity->is_stop_edcca = false; + adaptivity->backup_h2l = 0; + adaptivity->backup_l2h = 0; + adaptivity->adaptivity_dbg_port = (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) ? 0x208 : 0x209; + + phydm_mac_edcca_state(p_dm_odm, phydm_dont_ignore_edcca); + + if (p_dm_odm->support_ic_type & ODM_IC_11N_GAIN_IDX_EDCCA) { + /*odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT(12) | BIT(11) | BIT(10), 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ + if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1); /*set to page B1*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DCNF_97F, BIT(27) | BIT(26), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0); +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + if (priv->pshare->rf_ft_var.adaptivity_enable == 1) + odm_set_bb_reg(p_dm_odm, 0xce8, BIT(13), 0x1); /*0: mean, 1:max pwdB*/ #endif - - if (pDM_Odm->SupportICType & ODM_IC_11N_GAIN_IDX_EDCCA) { - /*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT12 | BIT11 | BIT10, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ - if (pDM_Odm->SupportICType & ODM_RTL8197F) { - ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_B1_97F, BIT30, 0x1); /*set to page B1*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DCNF_97F, BIT27 | BIT26, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_B1_97F, BIT30, 0x0); } else - ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DCNF_11N, BIT21 | BIT20, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DCNF_11N, BIT(21) | BIT(20), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ } #if (RTL8195A_SUPPORT == 0) - if (pDM_Odm->SupportICType & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/ - /*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30 | BIT29 | BIT28, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29 | BIT28, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + if (p_dm_odm->support_ic_type & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/ + /*odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DOWN_OPT, BIT(30) | BIT(29) | BIT(28), 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT(29) | BIT(28), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ } - if (!(pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) { - Phydm_SearchPwdBLowerBound(pDM_Odm); - if (phydm_reSearchCondition(pDM_Odm)) - Phydm_SearchPwdBLowerBound(pDM_Odm); - } + if (!(p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) { + phydm_search_pwdb_lower_bound(p_dm_odm); + if (phydm_re_search_condition(p_dm_odm)) + phydm_search_pwdb_lower_bound(p_dm_odm); + } else + phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f); /*resume to no link state*/ #endif + /*forgetting factor setting*/ + phydm_set_forgetting_factor(p_dm_odm); -/*we need to consider PwdB upper bound for 8814 later IC*/ - Adaptivity->AdajustIGILevel = (u1Byte)((pDM_Odm->TH_L2H_ini + IGItarget) - PwdBUpperBound + DFIRloss); /*IGI = L2H - PwdB - DFIRloss*/ + /*we need to consider PwdB upper bound for 8814 later IC*/ + adaptivity->adajust_igi_level = (u8)((p_dm_odm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x, Adaptivity->AdajustIGILevel = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, Adaptivity->AdajustIGILevel)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("th_l2h_ini = 0x%x, th_edcca_hl_diff = 0x%x, adaptivity->adajust_igi_level = 0x%x\n", p_dm_odm->th_l2h_ini, p_dm_odm->th_edcca_hl_diff, adaptivity->adajust_igi_level)); /*Check this later on Windows*/ - /*phydm_setEDCCAThresholdAPI(pDM_Odm, pDM_DigTable->CurIGValue);*/ + /*phydm_set_edcca_threshold_api(p_dm_odm, p_dm_dig_table->cur_ig_value);*/ } -VOID -Phydm_Adaptivity( - IN PVOID pDM_VOID, - IN u1Byte IGI +void +phydm_adaptivity( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - s1Byte TH_L2H_dmc, TH_H2L_dmc; - s1Byte Diff = 0, IGI_target; - PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u8 igi = p_dm_dig_table->cur_ig_value; + s8 th_l2h_dmc, th_h2l_dmc; + s8 diff = 0, igi_target = 0x32; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER pAdapter = pDM_Odm->Adapter; - BOOLEAN bFwCurrentInPSMode = FALSE; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + boolean is_fw_current_in_ps_mode = false; + u8 disable_ap_adapt_setting; - pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode)); + p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_FW_PSMODE_STATUS, (u8 *)(&is_fw_current_in_ps_mode)); /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/ - if (bFwCurrentInPSMode) + if (is_fw_current_in_ps_mode) return; #endif - if ((pDM_Odm->EDCCA_enable == FALSE) || (Adaptivity->bStopEDCCA == TRUE)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n")); + if ((p_dm_odm->edcca_enable == false) || (adaptivity->is_stop_edcca == true)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n")); return; } - if (!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n")); - pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; - pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2; + if ((!(p_dm_odm->support_ability & ODM_BB_ADAPTIVITY)) && adaptivity->debug_mode == false) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n")); + p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2; + p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2; } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - else{ - if (Phydm_CheckChannelPlan(pDM_Odm) || (pDM_Odm->APTotalNum > Adaptivity->APNumTH)) { - pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; - pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2; + else if (adaptivity->debug_mode == false) { + disable_ap_adapt_setting = false; + if (p_dm_odm->p_soft_ap_mode != NULL) { + if (*(p_dm_odm->p_soft_ap_mode) != 0 && (p_dm_odm->soft_ap_special_setting & BIT(0))) + disable_ap_adapt_setting = true; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("p_dm_odm->soft_ap_special_setting = %x, *(p_dm_odm->p_soft_ap_mode) = %d, disable_ap_adapt_setting = %d\n", p_dm_odm->soft_ap_special_setting, *(p_dm_odm->p_soft_ap_mode), disable_ap_adapt_setting)); + } + if (phydm_check_channel_plan(p_dm_odm) || (p_dm_odm->ap_total_num > adaptivity->ap_num_th) || disable_ap_adapt_setting) { + p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2; + p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2; } else { - pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup; - pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup; + p_dm_odm->th_l2h_ini = adaptivity->th_l2h_ini_backup; + p_dm_odm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup; } } #endif - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n")); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n", - Adaptivity->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff)); + else if (adaptivity->debug_mode == true) { + p_dm_odm->th_l2h_ini = adaptivity->th_l2h_ini_debug; + p_dm_odm->th_edcca_hl_diff = 7; + adaptivity->adajust_igi_level = (u8)((p_dm_odm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/ + } + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n")); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n", + adaptivity->igi_base, p_dm_odm->th_l2h_ini, p_dm_odm->th_edcca_hl_diff)); #if (RTL8195A_SUPPORT == 0) - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { /*fix AC series when enable EDCCA hang issue*/ - ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 1); /*ADC_mask disable*/ - ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); /*ADC_mask enable*/ + odm_set_bb_reg(p_dm_odm, 0x800, BIT(10), 1); /*ADC_mask disable*/ + odm_set_bb_reg(p_dm_odm, 0x800, BIT(10), 0); /*ADC_mask enable*/ } #endif - if (*pDM_Odm->pBandWidth == ODM_BW20M) /*CHANNEL_WIDTH_20*/ - IGI_target = Adaptivity->IGI_Base; - else if (*pDM_Odm->pBandWidth == ODM_BW40M) - IGI_target = Adaptivity->IGI_Base + 2; -#if (RTL8195A_SUPPORT == 0) - else if (*pDM_Odm->pBandWidth == ODM_BW80M) - IGI_target = Adaptivity->IGI_Base + 2; -#endif - else - IGI_target = Adaptivity->IGI_Base; - Adaptivity->IGI_target = (u1Byte) IGI_target; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, DynamicLinkAdaptivity = %d, AcsForAdaptivity = %d\n", - (*pDM_Odm->pBandWidth == ODM_BW80M) ? "80M" : ((*pDM_Odm->pBandWidth == ODM_BW40M) ? "40M" : "20M"), IGI_target, Adaptivity->DynamicLinkAdaptivity, Adaptivity->AcsForAdaptivity)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, Adaptivity->AdajustIGILevel= 0x%x, adaptivity_flag = %d, Adaptivity_enable = %d\n", - pDM_Odm->RSSI_Min, Adaptivity->AdajustIGILevel, pDM_Odm->adaptivity_flag, pDM_Odm->Adaptivity_enable)); + igi_target = adaptivity->igi_base; + adaptivity->igi_target = (u8) igi_target; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("band_width=%s, igi_target=0x%x, dynamic_link_adaptivity = %d, acs_for_adaptivity = %d\n", + (*p_dm_odm->p_band_width == ODM_BW80M) ? "80M" : ((*p_dm_odm->p_band_width == ODM_BW40M) ? "40M" : "20M"), igi_target, adaptivity->dynamic_link_adaptivity, adaptivity->acs_for_adaptivity)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, adaptivity->adajust_igi_level= 0x%x, adaptivity_flag = %d, adaptivity_enable = %d\n", + p_dm_odm->rssi_min, adaptivity->adajust_igi_level, p_dm_odm->adaptivity_flag, p_dm_odm->adaptivity_enable)); - if ((Adaptivity->DynamicLinkAdaptivity == TRUE) && (!pDM_Odm->bLinked) && (pDM_Odm->Adaptivity_enable == FALSE)) { - Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n")); + if ((adaptivity->dynamic_link_adaptivity == true) && (!p_dm_odm->is_linked) && (p_dm_odm->adaptivity_enable == false)) { + phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n")); return; } - if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { - if ((Adaptivity->AdajustIGILevel > IGI) && (pDM_Odm->Adaptivity_enable == TRUE)) - Diff = Adaptivity->AdajustIGILevel - IGI; - - TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target; - TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; + if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { + if ((adaptivity->adajust_igi_level > igi) && (p_dm_odm->adaptivity_enable == true)) + diff = adaptivity->adajust_igi_level - igi; + else if (p_dm_odm->adaptivity_enable == false) + diff = 0x3e - igi; + + th_l2h_dmc = p_dm_odm->th_l2h_ini - diff + igi_target; + th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; } #if (RTL8195A_SUPPORT == 0) else { - Diff = IGI_target - (s1Byte)IGI; - TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff; - if (TH_L2H_dmc > 10 && (pDM_Odm->Adaptivity_enable == TRUE)) - TH_L2H_dmc = 10; + diff = igi_target - (s8)igi; + th_l2h_dmc = p_dm_odm->th_l2h_ini + diff; + if (th_l2h_dmc > 10 && (p_dm_odm->adaptivity_enable == true)) + th_l2h_dmc = 10; - TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; + th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; /*replace lower bound to prevent EDCCA always equal 1*/ - if (TH_H2L_dmc < Adaptivity->H2L_lb) - TH_H2L_dmc = Adaptivity->H2L_lb; - if (TH_L2H_dmc < Adaptivity->L2H_lb) - TH_L2H_dmc = Adaptivity->L2H_lb; + if (th_h2l_dmc < adaptivity->h2l_lb) + th_h2l_dmc = adaptivity->h2l_lb; + if (th_l2h_dmc < adaptivity->l2h_lb) + th_l2h_dmc = adaptivity->l2h_lb; } #endif - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb)); - - Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc); - - if (pDM_Odm->Adaptivity_enable == TRUE) - ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); - - return; -} + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", igi, th_l2h_dmc, th_h2l_dmc)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", p_dm_odm->adaptivity_igi_upper, adaptivity->h2l_lb, adaptivity->l2h_lb)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("debug_mode = %d\n", adaptivity->debug_mode)); + phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + if (p_dm_odm->adaptivity_enable == true) + odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 1); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + return; +} -VOID -Phydm_AdaptivityBSOD( - IN PVOID pDM_VOID +/*This API is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/ +void +phydm_pause_edcca( + void *p_dm_void, + boolean is_pasue_edcca ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER pAdapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); - u1Byte count = 0; - u4Byte u4Value; - - /* - 1. turn off RF (TRX Mux in standby mode) - 2. H2C mac id drop - 3. ignore EDCCA - 4. wait for clear FIFO - 5. don't ignore EDCCA - 6. turn on RF (TRX Mux in TRx mdoe) - 7. H2C mac id resume - */ - - RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n")); - - pAdapter->dropPktByMacIdCnt++; - pMgntInfo->bDropPktInProgress = TRUE; - - pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_MAX_Q_PAGE_NUM, (pu1Byte)(&u4Value)); - RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page Number = 0x%08x\n", u4Value)); - pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value)); - RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value)); - - /*Standby mode*/ - Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE); - ODM_Write_DIG(pDM_Odm, 0x20); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u8 IGI = p_dm_dig_table->cur_ig_value; + s8 diff = 0; - /*H2C mac id drop*/ - MacIdIndicateDisconnect(pAdapter); + if (is_pasue_edcca) { + adaptivity->is_stop_edcca = true; - /*Ignore EDCCA*/ - Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA); + if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { + if (adaptivity->adajust_igi_level > IGI) + diff = adaptivity->adajust_igi_level - IGI; - delay_ms(50); - count = 5; - - /*Resume EDCCA*/ - Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA); - - /*Turn on TRx mode*/ - Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE); - ODM_Write_DIG(pDM_Odm, 0x20); - - /*Resume H2C macid*/ - MacIdRecoverMediaStatus(pAdapter); - - pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value)); - RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value)); - - pMgntInfo->bDropPktInProgress = FALSE; - RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10)); - -} + adaptivity->backup_l2h = p_dm_odm->th_l2h_ini - diff + adaptivity->igi_target; + adaptivity->backup_h2l = adaptivity->backup_l2h - p_dm_odm->th_edcca_hl_diff; + } +#if (RTL8195A_SUPPORT == 0) + else { + diff = adaptivity->igi_target - (s8)IGI; + adaptivity->backup_l2h = p_dm_odm->th_l2h_ini + diff; + if (adaptivity->backup_l2h > 10) + adaptivity->backup_l2h = 10; -#endif + adaptivity->backup_h2l = adaptivity->backup_l2h - p_dm_odm->th_edcca_hl_diff; -/*This API is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/ -VOID -phydm_pauseEDCCA( - IN PVOID pDM_VOID, - IN BOOLEAN bPasueEDCCA -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte IGI = pDM_DigTable->CurIGValue; - s1Byte Diff = 0; - - if (bPasueEDCCA) { - Adaptivity->bStopEDCCA = TRUE; - - if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { - if (Adaptivity->AdajustIGILevel > IGI) - Diff = Adaptivity->AdajustIGILevel - IGI; - - Adaptivity->backupL2H = pDM_Odm->TH_L2H_ini - Diff + Adaptivity->IGI_target; - Adaptivity->backupH2L = Adaptivity->backupL2H - pDM_Odm->TH_EDCCA_HL_diff; - } -#if (RTL8195A_SUPPORT == 0) - else { - Diff = Adaptivity->IGI_target - (s1Byte)IGI; - Adaptivity->backupL2H = pDM_Odm->TH_L2H_ini + Diff; - if (Adaptivity->backupL2H > 10) - Adaptivity->backupL2H = 10; - - Adaptivity->backupH2L = Adaptivity->backupL2H - pDM_Odm->TH_EDCCA_HL_diff; - - /*replace lower bound to prevent EDCCA always equal 1*/ - if (Adaptivity->backupH2L < Adaptivity->H2L_lb) - Adaptivity->backupH2L = Adaptivity->H2L_lb; - if (Adaptivity->backupL2H < Adaptivity->L2H_lb) - Adaptivity->backupL2H = Adaptivity->L2H_lb; - } + /*replace lower bound to prevent EDCCA always equal 1*/ + if (adaptivity->backup_h2l < adaptivity->h2l_lb) + adaptivity->backup_h2l = adaptivity->h2l_lb; + if (adaptivity->backup_l2h < adaptivity->l2h_lb) + adaptivity->backup_l2h = adaptivity->l2h_lb; + } #endif - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", Adaptivity->backupL2H, Adaptivity->backupH2L, IGI)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI)); /*Disable EDCCA*/ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (PlatformIsWorkItemScheduled(&(Adaptivity->phydm_pauseEDCCAWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(Adaptivity->phydm_pauseEDCCAWorkItem)); + if (odm_is_work_item_scheduled(&(adaptivity->phydm_pause_edcca_work_item)) == false) + odm_schedule_work_item(&(adaptivity->phydm_pause_edcca_work_item)); #else - phydm_pauseEDCCA_WorkItemCallback(pDM_Odm); + phydm_pause_edcca_work_item_callback(p_dm_odm); #endif - + } else { - Adaptivity->bStopEDCCA = FALSE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", Adaptivity->backupL2H, Adaptivity->backupH2L, IGI)); + adaptivity->is_stop_edcca = false; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI)); /*Resume EDCCA*/ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (PlatformIsWorkItemScheduled(&(Adaptivity->phydm_resumeEDCCAWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(Adaptivity->phydm_resumeEDCCAWorkItem)); + if (odm_is_work_item_scheduled(&(adaptivity->phydm_resume_edcca_work_item)) == false) + odm_schedule_work_item(&(adaptivity->phydm_resume_edcca_work_item)); #else - phydm_resumeEDCCA_WorkItemCallback(pDM_Odm); + phydm_resume_edcca_work_item_callback(p_dm_odm); #endif } @@ -1000,98 +812,167 @@ phydm_pauseEDCCA( } -VOID -phydm_pauseEDCCA_WorkItemCallback( +void +phydm_pause_edcca_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; #else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #endif - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)(0x7f|0x7f<<16)); + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16)); #if (RTL8195A_SUPPORT == 0) - else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)(0x7f|0x7f<<8)); + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)(0x7f | 0x7f << 8)); #endif } -VOID -phydm_resumeEDCCA_WorkItemCallback( +void +phydm_resume_edcca_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; #else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #endif - PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); - - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)((u1Byte)Adaptivity->backupL2H|(u1Byte)Adaptivity->backupH2L<<16)); + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 16)); #if (RTL8195A_SUPPORT == 0) - else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)((u1Byte)Adaptivity->backupL2H|(u1Byte)Adaptivity->backupH2L<<8)); + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 8)); #endif } -VOID -phydm_setEDCCAThresholdAPI( - IN PVOID pDM_VOID, - IN u1Byte IGI +void +phydm_set_edcca_threshold_api( + void *p_dm_void, + u8 IGI ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); - s1Byte TH_L2H_dmc, TH_H2L_dmc; - s1Byte Diff = 0, IGI_target = 0x32; - - if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) { - if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { - if (Adaptivity->AdajustIGILevel > IGI) - Diff = Adaptivity->AdajustIGILevel - IGI; - - TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target; - TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + s8 th_l2h_dmc, th_h2l_dmc; + s8 diff = 0, igi_target = 0x32; + + if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) { + if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { + if (adaptivity->adajust_igi_level > IGI) + diff = adaptivity->adajust_igi_level - IGI; + + th_l2h_dmc = p_dm_odm->th_l2h_ini - diff + igi_target; + th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; } #if (RTL8195A_SUPPORT == 0) else { - Diff = IGI_target - (s1Byte)IGI; - TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff; - if (TH_L2H_dmc > 10) - TH_L2H_dmc = 10; + diff = igi_target - (s8)IGI; + th_l2h_dmc = p_dm_odm->th_l2h_ini + diff; + if (th_l2h_dmc > 10) + th_l2h_dmc = 10; - TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; + th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; /*replace lower bound to prevent EDCCA always equal 1*/ - if (TH_H2L_dmc < Adaptivity->H2L_lb) - TH_H2L_dmc = Adaptivity->H2L_lb; - if (TH_L2H_dmc < Adaptivity->L2H_lb) - TH_L2H_dmc = Adaptivity->L2H_lb; + if (th_h2l_dmc < adaptivity->h2l_lb) + th_h2l_dmc = adaptivity->h2l_lb; + if (th_l2h_dmc < adaptivity->l2h_lb) + th_l2h_dmc = adaptivity->l2h_lb; } #endif - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI, th_l2h_dmc, th_h2l_dmc)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", p_dm_odm->adaptivity_igi_upper, adaptivity->h2l_lb, adaptivity->l2h_lb)); - Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc); + phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); } +} +void +phydm_adaptivity_debug( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + u32 used = *_used; + u32 out_len = *_out_len; + u32 reg_value32; + s8 h2l_diff = 0; + + if (dm_value[0] == PHYDM_ADAPT_DEBUG) { + PHYDM_SNPRINTF((output + used, out_len - used, "Adaptivity Debug Mode ===>\n")); + adaptivity->debug_mode = true; + adaptivity->th_l2h_ini_debug = (s8)dm_value[1]; + PHYDM_SNPRINTF((output + used, out_len - used, "th_l2h_ini_debug = %d\n", adaptivity->th_l2h_ini_debug)); + } else if (dm_value[0] == PHYDM_ADAPT_RESUME) { + PHYDM_SNPRINTF((output + used, out_len - used, "===> Adaptivity Resume\n")); + adaptivity->debug_mode = false; + } else if (dm_value[0] == PHYDM_ADAPT_MSG) { + PHYDM_SNPRINTF((output + used, out_len - used, "debug_mode = %s, th_l2h_ini = %d\n", (adaptivity->debug_mode ? "TRUE" : "FALSE"), p_dm_odm->th_l2h_ini)); + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + reg_value32 = odm_get_bb_reg(p_dm_odm, 0xc4c, MASKDWORD); + h2l_diff = (s8)(0x000000ff & reg_value32) - (s8)((0x00ff0000 & reg_value32)>>16); + } +#if (RTL8195A_SUPPORT == 0) + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + reg_value32 = odm_get_bb_reg(p_dm_odm, 0x8a4, MASKDWORD); + h2l_diff = (s8)(0x000000ff & reg_value32) - (s8)((0x0000ff00 & reg_value32)>>8); + } +#endif + if (h2l_diff == 7) + PHYDM_SNPRINTF((output + used, out_len - used, "adaptivity is enabled\n")); + else + PHYDM_SNPRINTF((output + used, out_len - used, "adaptivity is disabled\n")); + } + +} + +void +phydm_set_l2h_th_ini( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (p_dm_odm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) + p_dm_odm->th_l2h_ini = 0xf2; + else + p_dm_odm->th_l2h_ini = 0xef; + } else + p_dm_odm->th_l2h_ini = 0xf5; } +void +phydm_set_forgetting_factor( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) + odm_set_bb_reg(p_dm_odm, 0x8a0, BIT(1) | BIT(0), 0); +} diff --git a/hal/phydm/phydm_adaptivity.h b/hal/phydm/phydm_adaptivity.h index e2ca0d6..05e7923 100644 --- a/hal/phydm/phydm_adaptivity.h +++ b/hal/phydm/phydm_adaptivity.h @@ -1,8 +1,7 @@ - /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -12,33 +11,28 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - + *****************************************************************************/ + #ifndef __PHYDMADAPTIVITY_H__ #define __PHYDMADAPTIVITY_H__ -#define ADAPTIVITY_VERSION "9.3.3" /*20151230 changed by Kevin, modify 0x524[11] when adaptivity is enabled*/ +#define ADAPTIVITY_VERSION "9.5.2" /*20170330 changed by Kevin, change th_l2h_ini setting for 5G: v2.1.0*/ -#define PwdBUpperBound 7 -#define DFIRloss 5 +#define pwdb_upper_bound 7 +#define dfir_loss 7 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) -typedef enum _tag_PhyDM_REGULATION_Type { +enum phydm_regulation_type { REGULATION_FCC = 0, REGULATION_MKK = 1, REGULATION_ETSI = 2, - REGULATION_WW = 3, - + REGULATION_WW = 3, + MAX_REGULATION_NUM = 4 -} PhyDM_REGULATION_TYPE; +}; #endif -typedef enum _PHYDM_ADAPTIVITY_Info_Definition { +enum phydm_adapinfo_e { PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0, PHYDM_ADAPINFO_DCBACKOFF, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, @@ -46,177 +40,159 @@ typedef enum _PHYDM_ADAPTIVITY_Info_Definition { PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, PHYDM_ADAPINFO_AP_NUM_TH -} PHYDM_ADAPINFO_E; - - - -typedef enum tag_PhyDM_set_LNA { - PhyDM_disable_LNA = 0, - PhyDM_enable_LNA = 1, -} PhyDM_set_LNA; - - -typedef enum tag_PhyDM_TRx_MUX_Type -{ - PhyDM_SHUTDOWN = 0, - PhyDM_STANDBY_MODE = 1, - PhyDM_TX_MODE = 2, - PhyDM_RX_MODE = 3 -}PhyDM_Trx_MUX_Type; - -typedef enum tag_PhyDM_MACEDCCA_Type -{ - PhyDM_IGNORE_EDCCA = 0, - PhyDM_DONT_IGNORE_EDCCA = 1 -}PhyDM_MACEDCCA_Type; - -typedef struct _ADAPTIVITY_STATISTICS { - s1Byte TH_L2H_ini_backup; - s1Byte TH_EDCCA_HL_diff_backup; - s1Byte IGI_Base; - u1Byte IGI_target; - u1Byte NHMWait; - s1Byte H2L_lb; - s1Byte L2H_lb; - BOOLEAN bFirstLink; - BOOLEAN bCheck; - BOOLEAN DynamicLinkAdaptivity; - u1Byte APNumTH; - u1Byte AdajustIGILevel; - BOOLEAN AcsForAdaptivity; - s1Byte backupL2H; - s1Byte backupH2L; - BOOLEAN bStopEDCCA; -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_WORK_ITEM phydm_pauseEDCCAWorkItem; - RT_WORK_ITEM phydm_resumeEDCCAWorkItem; +}; + + + +enum phydm_set_lna { + phydm_disable_lna = 0, + phydm_enable_lna = 1, +}; + + +enum phydm_trx_mux_type { + phydm_shutdown = 0, + phydm_standby_mode = 1, + phydm_tx_mode = 2, + phydm_rx_mode = 3 +}; + +enum phydm_mac_edcca_type { + phydm_ignore_edcca = 0, + phydm_dont_ignore_edcca = 1 +}; + +enum phydm_adaptivity_mode { + PHYDM_ADAPT_MSG = 0, + PHYDM_ADAPT_DEBUG = 1, + PHYDM_ADAPT_RESUME = 2 +}; + +struct _ADAPTIVITY_STATISTICS { + s8 th_l2h_ini_backup; + s8 th_edcca_hl_diff_backup; + s8 igi_base; + u8 igi_target; + u8 nhm_wait; + s8 h2l_lb; + s8 l2h_lb; + boolean is_first_link; + boolean is_check; + boolean dynamic_link_adaptivity; + u8 ap_num_th; + u8 adajust_igi_level; + boolean acs_for_adaptivity; + s8 backup_l2h; + s8 backup_h2l; + boolean is_stop_edcca; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_WORK_ITEM phydm_pause_edcca_work_item; + RT_WORK_ITEM phydm_resume_edcca_work_item; #endif -} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS; - -VOID -phydm_pauseEDCCA( - IN PVOID pDM_VOID, - IN BOOLEAN bPasueEDCCA + u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/ + u8 debug_mode; + s8 th_l2h_ini_debug; +}; + +void +phydm_pause_edcca( + void *p_dm_void, + boolean is_pasue_edcca ); -VOID -Phydm_CheckAdaptivity( - IN PVOID pDM_VOID - ); - -VOID -Phydm_CheckEnvironment( - IN PVOID pDM_VOID - ); - -VOID -Phydm_NHMCounterStatisticsInit( - IN PVOID pDM_VOID - ); - -VOID -Phydm_NHMCounterStatistics( - IN PVOID pDM_VOID - ); - -VOID -Phydm_NHMCounterStatisticsReset( - IN PVOID pDM_VOID +void +phydm_check_adaptivity( + void *p_dm_void ); -VOID -Phydm_GetNHMCounterStatistics( - IN PVOID pDM_VOID +void +phydm_check_environment( + void *p_dm_void ); -VOID -Phydm_MACEDCCAState( - IN PVOID pDM_VOID, - IN PhyDM_MACEDCCA_Type State +void +phydm_mac_edcca_state( + void *p_dm_void, + enum phydm_mac_edcca_type state ); -VOID -Phydm_SetEDCCAThreshold( - IN PVOID pDM_VOID, - IN s1Byte H2L, - IN s1Byte L2H +void +phydm_set_edcca_threshold( + void *p_dm_void, + s8 H2L, + s8 L2H ); -VOID -Phydm_SetTRxMux( - IN PVOID pDM_VOID, - IN PhyDM_Trx_MUX_Type txMode, - IN PhyDM_Trx_MUX_Type rxMode -); - -BOOLEAN -Phydm_CalNHMcnt( - IN PVOID pDM_VOID +void +phydm_set_trx_mux( + void *p_dm_void, + enum phydm_trx_mux_type tx_mode, + enum phydm_trx_mux_type rx_mode ); -VOID -Phydm_SearchPwdBLowerBound( - IN PVOID pDM_VOID +void +phydm_search_pwdb_lower_bound( + void *p_dm_void ); -VOID -phydm_adaptivityInfoInit( - IN PVOID pDM_VOID, - IN PHYDM_ADAPINFO_E CmnInfo, - IN u4Byte Value - ); - -VOID -Phydm_AdaptivityInit( - IN PVOID pDM_VOID - ); - -VOID -Phydm_Adaptivity( - IN PVOID pDM_VOID, - IN u1Byte IGI - ); - -VOID -phydm_setEDCCAThresholdAPI( - IN PVOID pDM_VOID, - IN u1Byte IGI +void +phydm_adaptivity_info_init( + void *p_dm_void, + enum phydm_adapinfo_e cmn_info, + u32 value ); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -Phydm_DisableEDCCA( - IN PVOID pDM_VOID +void +phydm_adaptivity_init( + void *p_dm_void ); -VOID -Phydm_DynamicEDCCA( - IN PVOID pDM_VOID +void +phydm_adaptivity( + void *p_dm_void ); -VOID -Phydm_AdaptivityBSOD( - IN PVOID pDM_VOID +void +phydm_set_edcca_threshold_api( + void *p_dm_void, + u8 IGI ); -#endif - -VOID -phydm_pauseEDCCA_WorkItemCallback( +void +phydm_pause_edcca_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ); +); -VOID -phydm_resumeEDCCA_WorkItemCallback( +void +phydm_resume_edcca_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ); +); + +void +phydm_adaptivity_debug( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +void +phydm_set_l2h_th_ini( + void *p_dm_void +); + +void +phydm_set_forgetting_factor( + void *p_dm_void +); #endif diff --git a/hal/phydm/phydm_adc_sampling.c b/hal/phydm/phydm_adc_sampling.c index 388c942..0e7cf21 100644 --- a/hal/phydm/phydm_adc_sampling.c +++ b/hal/phydm/phydm_adc_sampling.c @@ -1,426 +1,765 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" -#include "rtl8197f/Hal8197FPhyReg.h" -#if ((RTL8197F_SUPPORT == 1)||(RTL8822B_SUPPORT == 1)) -#include "WlanHAL/HalMac88XX/halmac_reg2.h" -#else -#include "WlanHAL/HalHeader/HalComReg.h" + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #if ((RTL8197F_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) + #include "rtl8197f/Hal8197FPhyReg.h" + #include "WlanHAL/HalMac88XX/halmac_reg2.h" + #else + #include "WlanHAL/HalHeader/HalComReg.h" + #endif #endif #if (PHYDM_LA_MODE_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -BOOLEAN -ADCSmp_BufferAllocate( - IN PADAPTER Adapter, - IN PRT_ADCSMP AdcSmp - ) -{ - PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); - if (ADCSmpBuf->Length == 0) { - if (PlatformAllocateMemoryWithZero(Adapter, (void **)&(ADCSmpBuf->Octet), 0x10000) == RT_STATUS_SUCCESS) - ADCSmpBuf->Length = 0x10000; - else - return FALSE; - } +#if WPP_SOFTWARE_TRACE + #include "phydm_adc_sampling.tmh" +#endif - return TRUE; -} #endif -VOID -ADCSmp_GetTxPktBuf( - IN PVOID pDM_VOID, - IN PRT_ADCSMP_STRING ADCSmpBuf - ) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +boolean +phydm_la_buffer_allocate( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte i = 0, value32, DataL = 0, DataH = 0; - u4Byte Addr, Finish_Addr; - u4Byte End_Addr = (ADCSmpBuf->start_pos + ADCSmpBuf->buffer_size)-1; /*End_Addr = 0x3ffff;*/ - BOOLEAN bRoundUp; - static u4Byte page = 0xFF; - - - PlatformZeroMemory(ADCSmpBuf->Octet, ADCSmpBuf->Length); - - ODM_Write1Byte(pDM_Odm, REG_PKT_BUFF_ACCESS_CTRL, 0x69); - /*PlatformEFIOWrite1Byte(Adapter, REG_PKT_BUFF_ACCESS_CTRL_8814A, 0x69);*/ - /*0x106[7:0]=0x69: access TXPKT Buffer*/ - /* 0xA5: access RXPKT Buffer*/ - /* 0x7F: access TXREPORT buffer*/ - - DbgPrint("%s\n", __func__); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; +#endif + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + boolean ret = false; - value32 = ODM_Read4Byte(pDM_Odm, REG_IQ_DUMP); - bRoundUp = (BOOLEAN)((value32 & BIT31) >> 31); - Finish_Addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/ + dbg_print("[LA mode BufferAllocate]\n"); - if (bRoundUp) - Addr = (Finish_Addr+1)<<3; - else - Addr = ADCSmpBuf->start_pos; + if (adc_smp_buf->length == 0) { - DbgPrint("bRoundUp = %d, Finish_Addr=0x%x, value32=0x%x\n", bRoundUp, Finish_Addr, value32); - DbgPrint("End_Addr = %x, ADCSmpBuf->start_pos = 0x%x, ADCSmpBuf->buffer_size = 0x%x\n", End_Addr, ADCSmpBuf->start_pos, ADCSmpBuf->buffer_size); +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (PlatformAllocateMemoryWithZero(adapter, (void **)&(adc_smp_buf->octet), adc_smp_buf->buffer_size) != RT_STATUS_SUCCESS) { +#else + odm_allocate_memory(p_dm_odm, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size); + if (!adc_smp_buf->octet) { +#endif + ret = false; + } else + adc_smp_buf->length = adc_smp_buf->buffer_size; + ret = true; + } -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - watchdog_stop(pDM_Odm->priv); + return ret; +} #endif - if (pDM_Odm->SupportICType & ODM_RTL8197F) { - for (Addr = 0x0, i = 0; Addr < End_Addr; Addr += 8, i += 2) { /*64K byte*/ - if ((Addr&0xfff) == 0) - ODM_Write2Byte(pDM_Odm, REG_PKTBUF_DBG_CTRL, 0x780+(Addr >> 12)); - DataL = ODM_Read4Byte(pDM_Odm, 0x8000+(Addr&0xfff)); - DataH = ODM_Read4Byte(pDM_Odm, 0x8000+(Addr&0xfff)+4); +void +phydm_la_get_tx_pkt_buf( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + u32 i = 0, value32, data_l = 0, data_h = 0; + u32 addr, finish_addr; + u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) - 1; /*end_addr = 0x3ffff;*/ + boolean is_round_up; + static u32 page = 0xFF; + u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0; + u8 backup_dma = 0; + + odm_memory_set(p_dm_odm, adc_smp_buf->octet, 0, adc_smp_buf->length); + odm_write_1byte(p_dm_odm, 0x0106, 0x69); + + dbg_print("GetTxPktBuf\n"); + + value32 = odm_read_4byte(p_dm_odm, 0x7c0); + is_round_up = (boolean)((value32 & BIT(31)) >> 31); + finish_addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/ + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #if (RTL8197F_SUPPORT) + if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + odm_set_bb_reg(p_dm_odm, 0x7c0, BIT(0), 0x0); + + /*Stop DMA*/ + backup_dma = odm_get_mac_reg(p_dm_odm, 0x300, MASKLWORD); + odm_set_mac_reg(p_dm_odm, 0x300, 0x7fff, 0x7fff); + + /*move LA mode content from IMEM to TxPktBuffer + Source : OCPBASE_IMEM 0x00000000 + Destination : OCPBASE_TXBUF 0x18780000 + Length : 64K*/ + GET_HAL_INTERFACE(p_dm_odm->priv)->init_ddma_handler(p_dm_odm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000); + } + #endif + #endif + + if (is_round_up) { + addr = (finish_addr + 1) << 3; + dbg_print("is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n", is_round_up, finish_addr, value32); + smp_number = ((adc_smp_buf->buffer_size) >> 3); /*Byte to 8Byte (64bit)*/ + } else { + addr = adc_smp_buf->start_pos; + addr_8byte = addr >> 3; + + if (addr_8byte > finish_addr) + smp_number = addr_8byte - finish_addr; + else + smp_number = finish_addr - addr_8byte; - DbgPrint("%08x%08x\n", DataH, DataL); + dbg_print("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", is_round_up, finish_addr, addr_8byte, smp_number); + + } + /* + dbg_print("is_round_up = %d, finish_addr=0x%x, value32=0x%x\n", is_round_up, finish_addr, value32); + dbg_print("end_addr = %x, adc_smp_buf->start_pos = 0x%x, adc_smp_buf->buffer_size = 0x%x\n", end_addr, adc_smp_buf->start_pos, adc_smp_buf->buffer_size); + */ + + if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) { /*64K byte*/ + if ((addr & 0xfff) == 0) + odm_set_bb_reg(p_dm_odm, 0x0140, MASKLWORD, 0x780 + (addr >> 12)); + data_l = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff), MASKDWORD); + data_h = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD); + + dbg_print("%08x%08x\n", data_h, data_l); } } else { - while (Addr != (Finish_Addr<<3)) { - if (page != (Addr >> 12)) { - /*Reg140=0x780+(Addr>>12), Addr=0x30~0x3F, total 16 pages*/ - page = (Addr >> 12); - ODM_Write2Byte(pDM_Odm, REG_PKTBUF_DBG_CTRL, 0x780+page); + + i = 0; + while (addr != (finish_addr << 3)) { + if (page != (addr >> 12)) { + /*Reg140=0x780+(addr>>12), addr=0x30~0x3F, total 16 pages*/ + page = (addr >> 12); } - /*pDataL = 0x8000+(Addr&0xfff);*/ - DataL = ODM_Read4Byte(pDM_Odm, 0x8000+(Addr&0xfff)); - DataH = ODM_Read4Byte(pDM_Odm, 0x8000+(Addr&0xfff)+4); - - /*ADCSmpBuf->Octet[i] = DataH;*/ - /*ADCSmpBuf->Octet[i+1] = DataL;*/ - /*DbgPrint("%08x%08x\n", ADCSmpBuf->Octet[i], ADCSmpBuf->Octet[i+1]);*/ - DbgPrint("%08x%08x\n", DataH, DataL); + odm_set_bb_reg(p_dm_odm, 0x0140, MASKLWORD, 0x780 + page); + + /*pDataL = 0x8000+(addr&0xfff);*/ + data_l = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff), MASKDWORD); + data_h = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD); + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + adc_smp_buf->octet[i] = data_h; + adc_smp_buf->octet[i + 1] = data_l; + #endif + + #if DBG /*WIN driver check build*/ + dbg_print("%08x%08x\n", data_h, data_l); + #else /*WIN driver free build*/ + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1])); + #endif + #endif + i = i + 2; - - if ((Addr+8) >= End_Addr) - Addr = ADCSmpBuf->start_pos; + + if ((addr + 8) >= end_addr) + addr = adc_smp_buf->start_pos; else - Addr = Addr + 8; + addr = addr + 8; + + smp_cnt++; + if (smp_cnt >= (smp_number - 1)) + break; } + dbg_print("smp_cnt = ((%d))\n", smp_cnt); + + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("smp_cnt = ((%d))\n", smp_cnt)); + #endif } - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - watchdog_resume(pDM_Odm->priv); -#endif -} + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #if (RTL8197F_SUPPORT) + if (p_dm_odm->support_ic_type & ODM_RTL8197F) + odm_set_mac_reg(p_dm_odm, 0x300, 0x7fff, backup_dma); /*Resume DMA*/ + #endif + #endif +} -VOID -ADCSmp_Start( - IN PVOID pDM_VOID, - IN PRT_ADCSMP AdcSmp - ) +void +phydm_la_mode_set_mac_iq_dump( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte tmpU1b; - PRT_ADCSMP_STRING Buffer = &(AdcSmp->ADCSmpBuf); - RT_ADCSMP_TRIG_SIG_SEL TrigSigSel = AdcSmp->ADCSmpTrigSigSel; - u1Byte backup_DMA; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + u32 reg_value; - DbgPrint("%s\n", __func__); + odm_write_1byte(p_dm_odm, 0x7c0, 0); /*clear all 0x7c0*/ + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/ - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ODM_SetBBReg(pDM_Odm, r_dma_trigger_8197F, 0xf00, AdcSmp->ADCSmpDmaDataSigSel); /*0x9A0[11:8]*/ - else - ODM_SetBBReg(pDM_Odm , ODM_ADC_TRIGGER_Jaguar2, 0xf00, AdcSmp->ADCSmpDmaDataSigSel); /*0x95C[11:8]*/ + if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) { - ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP+1, AdcSmp->ADCSmpTriggerTime); + adc_smp->is_bb_trigger = 0; + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(2), 1); /*polling bit for MAC mode*/ + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(4) | BIT(3), adc_smp->la_trigger_edge); /*trigger mode for MAC*/ + dbg_print("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n", adc_smp->la_mac_mask_or_hdr_sel, adc_smp->la_trig_sig_sel, adc_smp->la_dbg_port); + /*[Set MAC Debug Port]*/ + odm_set_mac_reg(p_dm_odm, 0xF4, BIT(16), 1); + odm_set_mac_reg(p_dm_odm, 0x38, 0xff0000, adc_smp->la_dbg_port); + odm_set_mac_reg(p_dm_odm, 0x7c4, MASKDWORD, adc_smp->la_mac_mask_or_hdr_sel); + odm_set_mac_reg(p_dm_odm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel); - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ODM_SetBBReg(pDM_Odm, r_reset_cfo_rpt_ctrl_8197F, BIT26, 0x1); - else { /*for 8814A and 8822B?*/ - ODM_Write1Byte(pDM_Odm, 0x198c, 0x7); - ODM_Write1Byte(pDM_Odm, 0x8b4, 0x80); - } - - if (AdcSmp->ADCSmpTrigSel == ADCSMP_MAC_TRIG) { /* trigger by MAC*/ - if (TrigSigSel == ADCSMP_TRIG_REG) { /* manual trigger 0x7C0[5] = 0 -> 1*/ - ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP, 0xCB); /*0x7C0[7:0]=8'b1100_1011*/ - ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP, 0xEB); /*0x7C0[7:0]=8'b1110_1011*/ - } else if (TrigSigSel == ADCSMP_TRIG_CCA) - ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP, 0x8B); /*0x7C0[7:0]=8'b1000_1011*/ - else if (TrigSigSel == ADCSMP_TRIG_CRCFAIL) - ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP, 0x4B); /*0x7C0[7:0]=8'b0100_1011*/ - else if (TrigSigSel == ADCSMP_TRIG_CRCOK) - ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP, 0x0B); /*0x7C0[7:0]=8'b0000_1011*/ - } else { /*trigger by BB*/ - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ODM_SetBBReg(pDM_Odm, r_dma_trigger_8197F, 0x1f, TrigSigSel); /*0x9A0[4:0]*/ - else - ODM_SetBBReg(pDM_Odm , ODM_ADC_TRIGGER_Jaguar2, 0x1f, TrigSigSel); /*0x95C[4:0], 0x1F: trigger by CCA*/ - ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP, 0x03); /*0x7C0[7:0]=8'b0000_0011*/ + } else { + + adc_smp->is_bb_trigger = 1; + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(1), 1); /*polling bit for BB ADC mode*/ + + if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) { + + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(3), 1); /*polling bit for MAC trigger event*/ + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(7) | BIT(6), adc_smp->la_trig_sig_sel); + + if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG) + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(5), 1); /* manual trigger 0x7C0[5] = 0->1*/ + } } - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - watchdog_stop(pDM_Odm->priv); + + reg_value = odm_get_bb_reg(p_dm_odm, 0x7c0, 0xff); + dbg_print("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value); +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value)); #endif - /*Polling*/ - do { - tmpU1b = ODM_Read1Byte(pDM_Odm, REG_IQ_DUMP); +} + +void +phydm_adc_smp_start( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + u8 tmp_u1b; + u8 while_cnt = 0; + u8 polling_ok = false, target_polling_bit; + + phydm_la_mode_bb_setting(p_dm_odm); + phydm_la_mode_set_trigger_time(p_dm_odm, adc_smp->la_trigger_time); + + if (p_dm_odm->support_ic_type & ODM_RTL8197F) + odm_set_bb_reg(p_dm_odm, 0xd00, BIT(26), 0x1); + else { /*for 8814A and 8822B?*/ + odm_write_1byte(p_dm_odm, 0x8b4, 0x80); + /* odm_set_bb_reg(p_dm_odm, 0x8b4, BIT(7), 1); */ + } + + phydm_la_mode_set_mac_iq_dump(p_dm_odm); + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + watchdog_stop(p_dm_odm->priv); + #endif - if (AdcSmp->ADCSmpState != ADCSMP_STATE_SET) { - DbgPrint("ADCSmpState != ADCSMP_STATE_SET\n"); + target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2); + do { /*Polling time always use 100ms, when it exceed 2s, break while loop*/ + tmp_u1b = odm_read_1byte(p_dm_odm, 0x7c0); + + if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) { + dbg_print("[state Error] adc_smp_state != ADCSMP_STATE_SET\n"); break; - - } else if (tmpU1b & BIT1) { - ODM_delay_us(AdcSmp->ADCSmpPollingTime); + + } else if (tmp_u1b & target_polling_bit) { + ODM_delay_ms(100); + while_cnt = while_cnt + 1; continue; } else { - DbgPrint("%s Query OK\n", __func__); - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ODM_SetBBReg(pDM_Odm, REG_IQ_DUMP, BIT0, 0x0); + dbg_print("[LA Query OK] polling_bit=((0x%x))\n", target_polling_bit); + polling_ok = true; break; } - } while (1); - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - watchdog_resume(pDM_Odm->priv); -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) { - /*Stop DMA*/ - backup_DMA = ODM_GetMACReg(pDM_Odm, 0x300, bMaskLWord); - ODM_SetMACReg(pDM_Odm, 0x300, 0x7fff, backup_DMA|0x7fff); - - /*move LA mode content from IMEM to TxPktBuffer - Src : OCPBASE_IMEM 0x00000000 - Dest : OCPBASE_TXBUF 0x18780000 - Len : 64K*/ - GET_HAL_INTERFACE(pDM_Odm->priv)->InitDDMAHandler(pDM_Odm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000); + } while (while_cnt < 20); + + if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) { + + if (polling_ok) + phydm_la_get_tx_pkt_buf(p_dm_odm); + else + dbg_print("[Polling timeout]\n"); } -#endif -#endif - if (AdcSmp->ADCSmpState == ADCSMP_STATE_SET) - ADCSmp_GetTxPktBuf(pDM_Odm, Buffer); + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + watchdog_resume(p_dm_odm->priv); + #endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ODM_SetMACReg(pDM_Odm, 0x300, 0x7fff, backup_DMA); /*Resume DMA*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) + adc_smp->adc_smp_state = ADCSMP_STATE_QUERY; #endif + dbg_print("[LA mode] LA_pattern_count = ((%d))\n", adc_smp->la_count); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (AdcSmp->ADCSmpState == ADCSMP_STATE_SET) - AdcSmp->ADCSmpState = ADCSMP_STATE_QUERY; + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("[LA mode] la_count = ((%d))\n", adc_smp->la_count)); #endif - DbgPrint("%s Status %d\n", __func__, AdcSmp->ADCSmpState); + + adc_smp_stop(p_dm_odm); + + if (adc_smp->la_count == 0) { + dbg_print("LA Dump finished ---------->\n\n\n"); + phydm_release_bb_dbg_port(p_dm_odm); + + if ((p_dm_odm->support_ic_type & ODM_RTL8821C) && (p_dm_odm->cut_version >= ODM_CUT_B)) { + odm_set_bb_reg(p_dm_odm, 0x95c, BIT(23), 0); + } + + } else { + adc_smp->la_count--; + dbg_print("LA Dump more ---------->\n\n\n"); + adc_smp_set(p_dm_odm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel, adc_smp->la_dma_type, adc_smp->la_trigger_time, 0); + } + } #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -VOID -ADCSmpWorkItemCallback( - IN PVOID pContext - ) +void +adc_smp_work_item_callback( + void *p_context +) { - PADAPTER Adapter = (PADAPTER)pContext; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PRT_ADCSMP AdcSmp = &(pHalData->ADCSmp); + struct _ADAPTER *adapter = (struct _ADAPTER *)p_context; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - ADCSmp_Start(Adapter, AdcSmp); + dbg_print("[WorkItem Call back] LA_State=((%d))\n", adc_smp->adc_smp_state); + phydm_adc_smp_start(p_dm_odm); } #endif -VOID -ADCSmp_Set( - IN PVOID pDM_VOID, - IN RT_ADCSMP_TRIG_SEL TrigSel, - IN RT_ADCSMP_TRIG_SIG_SEL TrigSigSel, - IN u1Byte DmaDataSigSel, - IN u1Byte TriggerTime, - IN u2Byte PollingTime - ) +void +adc_smp_set( + void *p_dm_void, + u8 trig_mode, + u32 trig_sig_sel, + u8 dma_data_sig_sel, + u32 trigger_time, + u16 polling_time +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN retValue = TRUE; - - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); -/* - DbgPrint("%s\n ADCSmpState %d ADCSmpTrigSig %d ADCSmpTrigSigSel %d\n", - __FUNCTION__, AdcSmp->ADCSmpState, TrigSel, TrigSigSel); - - DbgPrint("ADCSmpDmaDataSigSel %d, ADCSmpTriggerTime %d ADCSmpPollingTime %d\n", - DmaDataSigSel, TriggerTime, PollingTime); -*/ - AdcSmp->ADCSmpTrigSel = TrigSel; - AdcSmp->ADCSmpTrigSigSel = TrigSigSel; - AdcSmp->ADCSmpDmaDataSigSel = DmaDataSigSel; - AdcSmp->ADCSmpTriggerTime = TriggerTime; - AdcSmp->ADCSmpPollingTime = PollingTime; - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (AdcSmp->ADCSmpState != ADCSMP_STATE_IDLE) - retValue = FALSE; - else if (AdcSmp->ADCSmpBuf.Length == 0) - retValue = ADCSmp_BufferAllocate(pDM_Odm, AdcSmp); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + boolean is_set_success = true; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + + adc_smp->la_trig_mode = trig_mode; + adc_smp->la_trig_sig_sel = trig_sig_sel; + adc_smp->la_dma_type = dma_data_sig_sel; + adc_smp->la_trigger_time = trigger_time; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE) + is_set_success = false; + else if (adc_smp->adc_smp_buf.length == 0) + is_set_success = phydm_la_buffer_allocate(p_dm_odm); #endif - if (retValue) { - AdcSmp->ADCSmpState = ADCSMP_STATE_SET; + if (is_set_success) { + adc_smp->adc_smp_state = ADCSMP_STATE_SET; + + dbg_print("[LA Set Success] LA_State=((%d))\n", adc_smp->adc_smp_state); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformScheduleWorkItem(&(pHalData->ADCSmpWorkItem)); -#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) - ADCSmp_Start(pDM_Odm, AdcSmp); + + dbg_print("ADCSmp_work_item_index = ((%d))\n", adc_smp->la_work_item_index); + if (adc_smp->la_work_item_index != 0) { + odm_schedule_work_item(&(adc_smp->adc_smp_work_item_1)); + adc_smp->la_work_item_index = 0; + } else { + odm_schedule_work_item(&(adc_smp->adc_smp_work_item)); + adc_smp->la_work_item_index = 1; + } +#else + phydm_adc_smp_start(p_dm_odm); #endif - } + } else + dbg_print("[LA Set Fail] LA_State=((%d))\n", adc_smp->adc_smp_state); + - DbgPrint("ADCSmpState %d Return Status %d\n", AdcSmp->ADCSmpState, retValue); } #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -RT_STATUS -ADCSmp_Query( - IN PADAPTER Adapter, - IN ULONG InformationBufferLength, - OUT PVOID InformationBuffer, - OUT PULONG BytesWritten - ) +enum rt_status +adc_smp_query( + void *p_dm_void, + ULONG information_buffer_length, + void *information_buffer, + PULONG bytes_written +) { - RT_STATUS retStatus = RT_STATUS_SUCCESS; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PRT_ADCSMP AdcSmp = &(pHalData->ADCSmp); - PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); - - DbgPrint("%s ADCSmpState %d", __func__, AdcSmp->ADCSmpState); - - if (InformationBufferLength != ADCSmpBuf->buffer_size) { - *BytesWritten = 0; - retStatus = RT_STATUS_RESOURCE; - } else if (ADCSmpBuf->Length != ADCSmpBuf->buffer_size) { - *BytesWritten = 0; - retStatus = RT_STATUS_RESOURCE; - } else if (AdcSmp->ADCSmpState != ADCSMP_STATE_QUERY) { - *BytesWritten = 0; - retStatus = RT_STATUS_PENDING; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + enum rt_status ret_status = RT_STATUS_SUCCESS; + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + + dbg_print("[%s] LA_State=((%d))", __func__, adc_smp->adc_smp_state); + + if (information_buffer_length != adc_smp_buf->buffer_size) { + *bytes_written = 0; + ret_status = RT_STATUS_RESOURCE; + } else if (adc_smp_buf->length != adc_smp_buf->buffer_size) { + *bytes_written = 0; + ret_status = RT_STATUS_RESOURCE; + } else if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) { + *bytes_written = 0; + ret_status = RT_STATUS_PENDING; } else { - PlatformMoveMemory(InformationBuffer, ADCSmpBuf->Octet, ADCSmpBuf->buffer_size); - *BytesWritten = ADCSmpBuf->buffer_size; + odm_move_memory(p_dm_odm, information_buffer, adc_smp_buf->octet, adc_smp_buf->buffer_size); + *bytes_written = adc_smp_buf->buffer_size; - AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE; + adc_smp->adc_smp_state = ADCSMP_STATE_IDLE; } - DbgPrint("Return Status %d\n", retStatus); + dbg_print("Return status %d\n", ret_status); - return retStatus; + return ret_status; } -#endif - -VOID -ADCSmp_Stop( - IN PVOID pDM_VOID - ) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +void +adc_smp_query( + void *p_dm_void, + void *output, + u32 out_len, + u32 *pused +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - - AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + u32 used = *pused; + u32 i; + /* struct timespec t; */ + /* rtw_get_current_timespec(&t); */ + + dbg_print("%s adc_smp_state %d", __func__, adc_smp->adc_smp_state); + + for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) { + PHYDM_SNPRINTF((output + used, out_len - used, + "%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1])); + } - DbgPrint("%s status %d\n", __func__, AdcSmp->ADCSmpState); + PHYDM_SNPRINTF((output + used, out_len - used, "\n")); + /* PHYDM_SNPRINTF((output+used, out_len-used, "\n[%lu.%06lu]\n", t.tv_sec, t.tv_nsec)); */ + *pused = used; } +s32 +adc_smp_get_sample_counts( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + + return (adc_smp_buf->length >> 2) - 2; +} +s32 +adc_smp_query_single_data( + void *p_dm_void, + void *output, + u32 out_len, + u32 index +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + u32 used = 0; + + /* dbg_print("%s adc_smp_state %d\n", __func__, adc_smp->adc_smp_state); */ + if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) { + PHYDM_SNPRINTF((output + used, out_len - used, + "Error: la data is not ready yet ...\n")); + return -1; + } + if (index < ((adc_smp_buf->length >> 2) - 2)) { + PHYDM_SNPRINTF((output + used, out_len - used, "%08x%08x\n", + adc_smp_buf->octet[index], adc_smp_buf->octet[index + 1])); + } + return 0; +} -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -u1Byte ADC_buffer[0x20000]; #endif -VOID -ADCSmp_Init( - IN PVOID pDM_VOID - ) +void +adc_smp_stop( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); - - AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE; - - if (pDM_Odm->SupportICType & ODM_RTL8814A) { - ADCSmpBuf->start_pos = 0x30000; - ADCSmpBuf->buffer_size = 0x10000; - } else if (pDM_Odm->SupportICType & ODM_RTL8822B) { - ADCSmpBuf->start_pos = 0x20000; - ADCSmpBuf->buffer_size = 0x20000; - } else if (pDM_Odm->SupportICType & ODM_RTL8197F) { - ADCSmpBuf->start_pos = 0x00000; - ADCSmpBuf->buffer_size = 0x10000; - } - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformInitializeWorkItem( - Adapter, - &(pHalData->ADCSmpWorkItem), - (RT_WORKITEM_CALL_BACK)ADCSmpWorkItemCallback, - (PVOID)Adapter, - "ADCSmpWorkItem"); -#endif + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + + adc_smp->adc_smp_state = ADCSMP_STATE_IDLE; + dbg_print("[LA_Stop] LA_state = ((%d))\n", adc_smp->adc_smp_state); } -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -VOID -ADCSmp_DeInit( - PADAPTER Adapter - ) +void +adc_smp_init( + void *p_dm_void +) { - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PRT_ADCSMP AdcSmp = &(pHalData->ADCSmp); - PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + + adc_smp->adc_smp_state = ADCSMP_STATE_IDLE; + + if (p_dm_odm->support_ic_type & ODM_RTL8814A) { + adc_smp_buf->start_pos = 0x30000; + adc_smp_buf->buffer_size = 0x10000; + } else if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + adc_smp_buf->start_pos = 0x20000; + adc_smp_buf->buffer_size = 0x20000; + } else if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + adc_smp_buf->start_pos = 0x00000; + adc_smp_buf->buffer_size = 0x10000; + } else if (p_dm_odm->support_ic_type & ODM_RTL8821C) { + adc_smp_buf->start_pos = 0x8000; + adc_smp_buf->buffer_size = 0x8000; + } - ADCSmp_Stop(Adapter); +} + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +void +adc_smp_de_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); - PlatformFreeWorkItem(&(pHalData->ADCSmpWorkItem)); + adc_smp_stop(p_dm_odm); - if (ADCSmpBuf->Length != 0x0) { - PlatformFreeMemory(ADCSmpBuf->Octet, ADCSmpBuf->Length); - ADCSmpBuf->Length = 0x0; + if (adc_smp_buf->length != 0x0) { + odm_free_memory(p_dm_odm, adc_smp_buf->octet, adc_smp_buf->length); + adc_smp_buf->length = 0x0; } -} +} + +#endif -VOID -Dump_MAC( - PADAPTER Adapter - ) +void +phydm_la_mode_bb_setting( + void *p_dm_void +) { + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - u4Byte Addr = 0; - - for (Addr = 0; Addr < 0x1A3D; Addr++) - DbgPrint("%04x %04x\n", Addr, PlatformEFIORead4Byte(Adapter, Addr)); -} + u8 trig_mode = adc_smp->la_trig_mode; + u32 trig_sig_sel = adc_smp->la_trig_sig_sel; + u32 dbg_port = adc_smp->la_dbg_port; + u8 is_trigger_edge = adc_smp->la_trigger_edge; + u8 sampling_rate = adc_smp->la_smp_rate; + u8 la_dma_type = adc_smp->la_dma_type; + u32 dbg_port_header_sel = 0; + dbg_print("1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n", + trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel, la_dma_type); -VOID -Dump_BB( - PADAPTER Adapter - ) -{ - u4Byte Addr = 0; - - for (Addr = 0; Addr < 0x1AFD; Addr++) - DbgPrint("%04x %04x\n", Addr, PHY_QueryBBReg(Adapter, Addr, bMaskDWord)); -} +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("1. [LA mode bb_setting]trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n", + trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel, la_dma_type)); +#endif + if (trig_mode == PHYDM_MAC_TRIG) + trig_sig_sel = 0; /*ignore this setting*/ -VOID -Dump_RF( - PADAPTER Adapter - ) -{ - u1Byte Addr = 0, Path = 0; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + /*set BB debug port*/ + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_3, dbg_port)) { + dbg_print("Set dbg_port((0x%x)) success\n", dbg_port); + } - for (Path = ODM_RF_PATH_A; Path < pHalData->NumTotalRFPath; Path++) { - for (Addr = 0; Addr < 0xF6; Addr++) - DbgPrint("%04x %04x\n", Addr, PHY_QueryRFReg(Adapter, Path, Addr, bRFRegOffsetMask)); + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + if (trig_mode == PHYDM_ADC_RF0_TRIG) + dbg_port_header_sel = 9; /*DBGOUT_RFC_a[31:0]*/ + else if (trig_mode == PHYDM_ADC_RF1_TRIG) + dbg_port_header_sel = 8; /*DBGOUT_RFC_b[31:0]*/ + else if ((trig_mode == PHYDM_ADC_BB_TRIG) || (trig_mode == PHYDM_ADC_MAC_TRIG)) { + + if (adc_smp->la_mac_mask_or_hdr_sel <= 0xf) { + dbg_port_header_sel = adc_smp->la_mac_mask_or_hdr_sel; + } else { + dbg_port_header_sel = 0; + } + } + + phydm_bb_dbg_port_header_sel(p_dm_odm, dbg_port_header_sel); + + odm_set_bb_reg(p_dm_odm, 0x95c, 0xf00, la_dma_type); /*0x95C[11:8]*/ + odm_set_bb_reg(p_dm_odm, 0x95C, 0x1f, trig_sig_sel); /*0x95C[4:0], BB debug port bit*/ + odm_set_bb_reg(p_dm_odm, 0x95C, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/ + odm_set_bb_reg(p_dm_odm, 0x95c, 0xe0, sampling_rate); + /* (0:) '80MHz' + (1:) '40MHz' + (2:) '20MHz' + (3:) '10MHz' + (4:) '5MHz' + (5:) '2.5MHz' + (6:) '1.25MHz' + (7:) '160MHz (for BW160 ic)' + */ + if ((p_dm_odm->support_ic_type & ODM_RTL8821C) && (p_dm_odm->cut_version >= ODM_CUT_B)) { + odm_set_bb_reg(p_dm_odm, 0x95c, BIT(23), 1); + } + } else { + + odm_set_bb_reg(p_dm_odm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/ + odm_set_bb_reg(p_dm_odm, 0x9a0, 0x1f, trig_sig_sel); /*0x9A0[4:0], BB debug port bit*/ + odm_set_bb_reg(p_dm_odm, 0x9A0, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/ + odm_set_bb_reg(p_dm_odm, 0x9A0, 0xe0, sampling_rate); + /* (0:) '80MHz' + (1:) '40MHz' + (2:) '20MHz' + (3:) '10MHz' + (4:) '5MHz' + (5:) '2.5MHz' + (6:) '1.25MHz' + (7:) '160MHz (for BW160 ic)' + */ } } + +void +phydm_la_mode_set_trigger_time( + void *p_dm_void, + u32 trigger_time_mu_sec +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 trigger_time_unit_num; + u32 time_unit = 0; + + if (trigger_time_mu_sec < 128) { + time_unit = 0; /*unit: 1mu sec*/ + } else if (trigger_time_mu_sec < 256) { + time_unit = 1; /*unit: 2mu sec*/ + } else if (trigger_time_mu_sec < 512) { + time_unit = 2; /*unit: 4mu sec*/ + } else if (trigger_time_mu_sec < 1024) { + time_unit = 3; /*unit: 8mu sec*/ + } else if (trigger_time_mu_sec < 2048) { + time_unit = 4; /*unit: 16mu sec*/ + } else if (trigger_time_mu_sec < 4096) { + time_unit = 5; /*unit: 32mu sec*/ + } else if (trigger_time_mu_sec < 8192) { + time_unit = 6; /*unit: 64mu sec*/ + } + + trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit); + + dbg_print("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit); +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit)); #endif + odm_set_mac_reg(p_dm_odm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit); + odm_set_mac_reg(p_dm_odm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f)); + +} + + +void +phydm_lamode_trigger_setting( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + u8 trig_mode, dma_data_sig_sel; + u32 trig_sig_sel; + boolean is_enable_la_mode; + u32 trigger_time_mu_sec; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + if (p_dm_odm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) { + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + is_enable_la_mode = (boolean)var1[0]; + /*dbg_print("echo cmd input_num = %d\n", input_num);*/ + + if ((strcmp(input[1], help) == 0)) { + PHYDM_SNPRINTF((output + used, out_len - used, "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n")); + /**/ + } else if ((is_enable_la_mode == 1)) { + + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); + + trig_mode = (u8)var1[1]; + + if (trig_mode == PHYDM_MAC_TRIG) + PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]); + else + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + trig_sig_sel = var1[2]; + + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]); + PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]); + PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]); + PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]); + PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]); + PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]); + PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]); + + dma_data_sig_sel = (u8)var1[3]; + trigger_time_mu_sec = var1[4]; /*unit: us*/ + + adc_smp->la_mac_mask_or_hdr_sel = var1[5]; + adc_smp->la_dbg_port = var1[6]; + adc_smp->la_trigger_edge = (u8) var1[7]; + adc_smp->la_smp_rate = (u8)(var1[8] & 0x7); + adc_smp->la_count = var1[9]; + + + dbg_print("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]); +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9])); #endif + PHYDM_SNPRINTF((output + used, out_len - used, "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n", trig_mode, trig_sig_sel, dma_data_sig_sel)); + PHYDM_SNPRINTF((output + used, out_len - used, "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n", trigger_time_mu_sec, adc_smp->la_mac_mask_or_hdr_sel, adc_smp->la_dbg_port)); + PHYDM_SNPRINTF((output + used, out_len - used, "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n", adc_smp->la_trigger_edge, (80 >> adc_smp->la_smp_rate), adc_smp->la_count)); + + adc_smp_set(p_dm_odm, trig_mode, trig_sig_sel, dma_data_sig_sel, trigger_time_mu_sec, 0); + + } else { + adc_smp_stop(p_dm_odm); + PHYDM_SNPRINTF((output + used, out_len - used, "Disable LA mode\n")); + } + } +} + +#endif /*endif PHYDM_LA_MODE_SUPPORT == 1*/ diff --git a/hal/phydm/phydm_adc_sampling.h b/hal/phydm/phydm_adc_sampling.h index 330a3ce..ecc9701 100644 --- a/hal/phydm/phydm_adc_sampling.h +++ b/hal/phydm/phydm_adc_sampling.h @@ -1,101 +1,161 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __INC_ADCSMP_H #define __INC_ADCSMP_H -typedef struct _RT_ADCSMP_STRING { - pu4Byte Octet; - u4Byte Length; - u4Byte buffer_size; - u4Byte start_pos; -} RT_ADCSMP_STRING, *PRT_ADCSMP_STRING; - - -typedef enum _RT_ADCSMP_TRIG_SEL { - ADCSMP_BB_TRIG, - ADCSMP_MAC_TRIG, -} RT_ADCSMP_TRIG_SEL, *PRT_ADCSMP_TRIG_SEL; - - -typedef enum _RT_ADCSMP_TRIG_SIG_SEL { - ADCSMP_TRIG_CRCOK, - ADCSMP_TRIG_CRCFAIL, - ADCSMP_TRIG_CCA, - ADCSMP_TRIG_REG, -} RT_ADCSMP_TRIG_SIG_SEL, *PRT_ADCSMP_TRIG_SIG_SEL; - - -typedef enum _RT_ADCSMP_STATE { - ADCSMP_STATE_IDLE, - ADCSMP_STATE_SET, - ADCSMP_STATE_QUERY, -} RT_ADCSMP_STATE, *PRT_ADCSMP_STATE; - - -typedef struct _RT_ADCSMP { - RT_ADCSMP_STRING ADCSmpBuf; - RT_ADCSMP_STATE ADCSmpState; - RT_ADCSMP_TRIG_SEL ADCSmpTrigSel; - RT_ADCSMP_TRIG_SIG_SEL ADCSmpTrigSigSel; - u1Byte ADCSmpDmaDataSigSel; - u1Byte ADCSmpTriggerTime; - u2Byte ADCSmpPollingTime; -} RT_ADCSMP, *PRT_ADCSMP; +#define DYNAMIC_LA_MODE "2.0" /*2017.02.06 Dino */ + +#if (PHYDM_LA_MODE_SUPPORT == 1) + +struct _RT_ADCSMP_STRING { + u32 *octet; + u32 length; + u32 buffer_size; + u32 start_pos; +}; + + +enum rt_adcsmp_trig_sel { + PHYDM_ADC_BB_TRIG = 0, + PHYDM_ADC_MAC_TRIG = 1, + PHYDM_ADC_RF0_TRIG = 2, + PHYDM_ADC_RF1_TRIG = 3, + PHYDM_MAC_TRIG = 4 +}; + + +enum rt_adcsmp_trig_sig_sel { + ADCSMP_TRIG_CRCOK = 0, + ADCSMP_TRIG_CRCFAIL = 1, + ADCSMP_TRIG_CCA = 2, + ADCSMP_TRIG_REG = 3 +}; + + +enum rt_adcsmp_state { + ADCSMP_STATE_IDLE = 0, + ADCSMP_STATE_SET = 1, + ADCSMP_STATE_QUERY = 2 +}; + + +struct _RT_ADCSMP { + struct _RT_ADCSMP_STRING adc_smp_buf; + enum rt_adcsmp_state adc_smp_state; + u8 la_trig_mode; + u32 la_trig_sig_sel; + u8 la_dma_type; + u32 la_trigger_time; + u32 la_mac_mask_or_hdr_sel; /*1.BB mode: for debug port header sel; 2.MAC mode: for reference mask*/ + u32 la_dbg_port; + u8 la_trigger_edge; + u8 la_smp_rate; + u32 la_count; + u8 is_bb_trigger; + u8 la_work_item_index; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_WORK_ITEM adc_smp_work_item; + RT_WORK_ITEM adc_smp_work_item_1; +#endif +}; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -VOID -ADCSmpWorkItemCallback( - IN PVOID pContext +void +adc_smp_work_item_callback( + void *p_context ); #endif -VOID -ADCSmp_Set( - IN PVOID pDM_VOID, - IN RT_ADCSMP_TRIG_SEL TrigSel, - IN RT_ADCSMP_TRIG_SIG_SEL TrigSigSel, - IN u1Byte DmaDataSigSel, - IN u1Byte TriggerTime, - IN u2Byte PollingTime +void +adc_smp_set( + void *p_dm_void, + u8 trig_mode, + u32 trig_sig_sel, + u8 dma_data_sig_sel, + u32 trigger_time, + u16 polling_time ); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -RT_STATUS -ADCSmp_Query( - IN PADAPTER Adapter, - IN ULONG InformationBufferLength, - OUT PVOID InformationBuffer, - OUT PULONG BytesWritten +enum rt_status +adc_smp_query( + void *p_dm_void, + ULONG information_buffer_length, + void *information_buffer, + PULONG bytes_written ); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +void +adc_smp_query( + void *p_dm_void, + void *output, + u32 out_len, + u32 *pused +); + +s32 +adc_smp_get_sample_counts( + void *p_dm_void +); + +s32 +adc_smp_query_single_data( + void *p_dm_void, + void *output, + u32 out_len, + u32 index +); + #endif -VOID -ADCSmp_Stop( - IN PVOID pDM_VOID +void +adc_smp_stop( + void *p_dm_void ); -VOID -ADCSmp_Init( - IN PVOID pDM_VOID +void +adc_smp_init( + void *p_dm_void ); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -VOID -ADCSmp_DeInit( - PADAPTER Adapter +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +void +adc_smp_de_init( + void *p_dm_void ); +#endif -VOID -Dump_MAC( - PADAPTER Adapter +void +phydm_la_mode_bb_setting( + void *p_dm_void ); -VOID -Dump_BB( - PADAPTER Adapter +void +phydm_la_mode_set_trigger_time( + void *p_dm_void, + u32 trigger_time_mu_sec ); -VOID -Dump_RF( - PADAPTER Adapter +void +phydm_lamode_trigger_setting( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num ); #endif #endif - diff --git a/hal/phydm/phydm_antdect.c b/hal/phydm/phydm_antdect.c index afa478c..7980967 100644 --- a/hal/phydm/phydm_antdect.c +++ b/hal/phydm/phydm_antdect.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,696 +11,608 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" -//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) -#if(defined(CONFIG_ANT_DETECTION)) - -//IS_ANT_DETECT_SUPPORT_SINGLE_TONE(Adapter) -//IS_ANT_DETECT_SUPPORT_RSSI(Adapter) -//IS_ANT_DETECT_SUPPORT_PSD(Adapter) - -//1 [1. Single Tone Method] =================================================== - -// -// Description: -// Set Single/Dual Antenna default setting for products that do not do detection in advance. -// -// Added by Joseph, 2012.03.22 -// -VOID -ODM_SingleDualAntennaDefaultSetting( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - PADAPTER pAdapter = pDM_Odm->Adapter; +/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */ +#if (defined(CONFIG_ANT_DETECTION)) - u1Byte btAntNum=BT_GetPgAntNum(pAdapter); - // Set default antenna A and B status - if(btAntNum == 2) - { - pDM_SWAT_Table->ANTA_ON=TRUE; - pDM_SWAT_Table->ANTB_ON=TRUE; - - } - else if(btAntNum == 1) - {// Set antenna A as default - pDM_SWAT_Table->ANTA_ON=TRUE; - pDM_SWAT_Table->ANTB_ON=FALSE; - - } - else - { - RT_ASSERT(FALSE, ("Incorrect antenna number!!\n")); - } +/* IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter) + * IS_ANT_DETECT_SUPPORT_RSSI(adapter) + * IS_ANT_DETECT_SUPPORT_PSD(adapter) */ + +/* 1 [1. Single Tone method] =================================================== */ + +/* + * Description: + * Set Single/Dual Antenna default setting for products that do not do detection in advance. + * + * Added by Joseph, 2012.03.22 + * */ +void +odm_single_dual_antenna_default_setting( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + + u8 bt_ant_num = BT_GetPgAntNum(p_adapter); + /* Set default antenna A and B status */ + if (bt_ant_num == 2) { + p_dm_swat_table->ANTA_ON = true; + p_dm_swat_table->ANTB_ON = true; + + } else if (bt_ant_num == 1) { + /* Set antenna A as default */ + p_dm_swat_table->ANTA_ON = true; + p_dm_swat_table->ANTB_ON = false; + + } else + RT_ASSERT(false, ("Incorrect antenna number!!\n")); } -//2 8723A ANT DETECT -// -// Description: -// Implement IQK single tone for RF DPK loopback and BB PSD scanning. -// This function is cooperated with BB team Neil. -// -// Added by Roger, 2011.12.15 -// -BOOLEAN -ODM_SingleDualAntennaDetection( - IN PVOID pDM_VOID, - IN u1Byte mode - ) +/* 2 8723A ANT DETECT + * + * Description: + * Implement IQK single tone for RF DPK loopback and BB PSD scanning. + * This function is cooperated with BB team Neil. + * + * Added by Roger, 2011.12.15 + * */ +boolean +odm_single_dual_antenna_detection( + void *p_dm_void, + u8 mode +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER pAdapter = pDM_Odm->Adapter; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - u4Byte CurrentChannel,RfLoopReg; - u1Byte n; - u4Byte Reg88c, Regc08, Reg874, Regc50, Reg948, Regb2c, Reg92c, Reg930, Reg064, AFE_rRx_Wait_CCA; - u1Byte initial_gain = 0x5a; - u4Byte PSD_report_tmp; - u4Byte AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0; - BOOLEAN bResult = TRUE; - u4Byte AFE_Backup[16]; - u4Byte AFE_REG_8723A[16] = { - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN, - rFPGA0_XCD_SwitchControl, rBlue_Tooth}; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection()============>\n")); - - - if (!(pDM_Odm->SupportICType & ODM_RTL8723B)) - return bResult; - - // Retrieve antenna detection registry info, added by Roger, 2012.11.27. - if(!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(pAdapter)) - return bResult; - - //1 Backup Current RF/BB Settings - - CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); - RfLoopReg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask); - if (pDM_Odm->SupportICType & ODM_RTL8723B) { - Reg92c = ODM_GetBBReg(pDM_Odm, rDPDT_control, bMaskDWord); - Reg930 = ODM_GetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord); - Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord); - Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord); - Reg064 = ODM_GetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29); - ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x1); - ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, 0xff, 0x77); - ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, 0x1); //dbg 7 - ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0x3c0, 0x0);//dbg 8 - ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x0); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + u32 current_channel, rf_loop_reg; + u8 n; + u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca; + u8 initial_gain = 0x5a; + u32 PSD_report_tmp; + u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0; + boolean is_result = true; + u32 afe_backup[16]; + u32 AFE_REG_8723A[16] = { + REG_RX_WAIT_CCA, REG_TX_CCK_RFON, + REG_TX_CCK_BBON, REG_TX_OFDM_RFON, + REG_TX_OFDM_BBON, REG_TX_TO_RX, + REG_TX_TO_TX, REG_RX_CCK, + REG_RX_OFDM, REG_RX_WAIT_RIFS, + REG_RX_TO_RX, REG_STANDBY, + REG_SLEEP, REG_PMPD_ANAEN, + REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH + }; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection()============>\n")); + + + if (!(p_dm_odm->support_ic_type & ODM_RTL8723B)) + return is_result; + + /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */ + if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(p_adapter)) + return is_result; + + /* 1 Backup Current RF/BB Settings */ + + current_channel = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK); + rf_loop_reg = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK); + if (p_dm_odm->support_ic_type & ODM_RTL8723B) { + reg92c = odm_get_bb_reg(p_dm_odm, REG_DPDT_CONTROL, MASKDWORD); + reg930 = odm_get_bb_reg(p_dm_odm, rfe_ctrl_anta_src, MASKDWORD); + reg948 = odm_get_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD); + regb2c = odm_get_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD); + reg064 = odm_get_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29)); + odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, 0x3, 0x1); + odm_set_bb_reg(p_dm_odm, rfe_ctrl_anta_src, 0xff, 0x77); + odm_set_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* dbg 7 */ + odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0);/* dbg 8 */ + odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x0); } - ODM_StallExecution(10); - - //Store A Path Register 88c, c08, 874, c50 - Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord); - Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord); - Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord); - Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); - - // Store AFE Registers - if (pDM_Odm->SupportICType & ODM_RTL8723B) - AFE_rRx_Wait_CCA = ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA,bMaskDWord); - - //Set PSD 128 pts - ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pts - - // To SET CH1 to do - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x7401); //Channel 1 - - // AFE all on step - if (pDM_Odm->SupportICType & ODM_RTL8723B) - ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x01c00016); - - // 3 wire Disable - ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0); - - //BB IQK Setting - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000); - - //IQK setting tone@ 4.34Mhz - ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C); - ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - - //Page B init - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000); - ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); - ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); - if (pDM_Odm->SupportICType & ODM_RTL8723B) { - ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150016); - ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150016); + odm_stall_execution(10); + + /* Store A path Register 88c, c08, 874, c50 */ + reg88c = odm_get_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD); + regc08 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD); + reg874 = odm_get_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD); + regc50 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD); + + /* Store AFE Registers */ + if (p_dm_odm->support_ic_type & ODM_RTL8723B) + afe_rrx_wait_cca = odm_get_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD); + + /* Set PSD 128 pts */ + odm_set_bb_reg(p_dm_odm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pts */ + + /* To SET CH1 to do */ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* channel 1 */ + + /* AFE all on step */ + if (p_dm_odm->support_ic_type & ODM_RTL8723B) + odm_set_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016); + + /* 3 wire Disable */ + odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0); + + /* BB IQK setting */ + odm_set_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4); + odm_set_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000); + + /* IQK setting tone@ 4.34Mhz */ + odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C); + odm_set_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD, 0x01007c00); + + /* Page B init */ + odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000); + odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000); + odm_set_bb_reg(p_dm_odm, REG_RX_IQK, MASKDWORD, 0x01004800); + odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f); + if (p_dm_odm->support_ic_type & ODM_RTL8723B) { + odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016); + odm_set_bb_reg(p_dm_odm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016); } - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0); - ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7f, initial_gain); - - //IQK Single tone start - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - ODM_StallExecution(10000); - - // PSD report of antenna A - PSD_report_tmp=0x0; - for (n=0;n<2;n++) - { - PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); - if(PSD_report_tmp >AntA_report) - AntA_report=PSD_report_tmp; + odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0); + odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain); + + /* IQK Single tone start */ + odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x808000); + odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000); + odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000); + + odm_stall_execution(10000); + + /* PSD report of antenna A */ + PSD_report_tmp = 0x0; + for (n = 0; n < 2; n++) { + PSD_report_tmp = phydm_get_psd_data(p_dm_odm, 14, initial_gain); + if (PSD_report_tmp > ant_a_report) + ant_a_report = PSD_report_tmp; } - // change to Antenna B - if (pDM_Odm->SupportICType & ODM_RTL8723B) { - //ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x2); - ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280); - ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1); + /* change to Antenna B */ + if (p_dm_odm->support_ic_type & ODM_RTL8723B) { + /* odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, 0x3, 0x2); */ + odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280); + odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x1); } - ODM_StallExecution(10); + odm_stall_execution(10); - // PSD report of antenna B - PSD_report_tmp=0x0; - for (n=0;n<2;n++) - { - PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); - if(PSD_report_tmp > AntB_report) - AntB_report=PSD_report_tmp; + /* PSD report of antenna B */ + PSD_report_tmp = 0x0; + for (n = 0; n < 2; n++) { + PSD_report_tmp = phydm_get_psd_data(p_dm_odm, 14, initial_gain); + if (PSD_report_tmp > ant_b_report) + ant_b_report = PSD_report_tmp; } - //Close IQK Single Tone function - ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + /* Close IQK Single Tone function */ + odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000); - //1 Return to antanna A - if (pDM_Odm->SupportICType & ODM_RTL8723B) { - // external DPDT - ODM_SetBBReg(pDM_Odm, rDPDT_control, bMaskDWord, Reg92c); + /* 1 Return to antanna A */ + if (p_dm_odm->support_ic_type & ODM_RTL8723B) { + /* external DPDT */ + odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, MASKDWORD, reg92c); - //internal S0/S1 - ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948); - ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c); - ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord, Reg930); - ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, Reg064); + /* internal S0/S1 */ + odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948); + odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c); + odm_set_bb_reg(p_dm_odm, rfe_ctrl_anta_src, MASKDWORD, reg930); + odm_set_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064); } - - ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c); - ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08); - ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874); - ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40); - ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg); - - //Reload AFE Registers - if (pDM_Odm->SupportICType & ODM_RTL8723B) - ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, AFE_rRx_Wait_CCA); - - if (pDM_Odm->SupportICType & ODM_RTL8723B) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report)); - - //2 Test Ant B based on Ant A is ON - if((AntA_report >= 100) && (AntB_report >= 100) && (AntA_report <= 135) && (AntB_report <= 135)) - { - u1Byte TH1=2, TH2=6; - - if((AntA_report - AntB_report < TH1) || (AntB_report - AntA_report < TH1)) - { - pDM_SWAT_Table->ANTA_ON=TRUE; - pDM_SWAT_Table->ANTB_ON=TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Dual Antenna\n")); - } - else if(((AntA_report - AntB_report >= TH1) && (AntA_report - AntB_report <= TH2)) || - ((AntB_report - AntA_report >= TH1) && (AntB_report - AntA_report <= TH2))) - { - pDM_SWAT_Table->ANTA_ON=FALSE; - pDM_SWAT_Table->ANTB_ON=FALSE; - bResult = FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); - } - else - { - pDM_SWAT_Table->ANTA_ON = TRUE; - pDM_SWAT_Table->ANTB_ON=FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Single Antenna\n")); + + odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c); + odm_set_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08); + odm_set_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874); + odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40); + odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_loop_reg); + + /* Reload AFE Registers */ + if (p_dm_odm->support_ic_type & ODM_RTL8723B) + odm_set_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca); + + if (p_dm_odm->support_ic_type & ODM_RTL8723B) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, ant_a_report)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, ant_b_report)); + + /* 2 Test ant B based on ant A is ON */ + if ((ant_a_report >= 100) && (ant_b_report >= 100) && (ant_a_report <= 135) && (ant_b_report <= 135)) { + u8 TH1 = 2, TH2 = 6; + + if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) { + p_dm_swat_table->ANTA_ON = true; + p_dm_swat_table->ANTB_ON = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Dual Antenna\n")); + } else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) || + ((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) { + p_dm_swat_table->ANTA_ON = false; + p_dm_swat_table->ANTB_ON = false; + is_result = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Need to check again\n")); + } else { + p_dm_swat_table->ANTA_ON = true; + p_dm_swat_table->ANTB_ON = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Single Antenna\n")); } - pDM_Odm->AntDetectedInfo.bAntDetected= TRUE; - pDM_Odm->AntDetectedInfo.dBForAntA = AntA_report; - pDM_Odm->AntDetectedInfo.dBForAntB = AntB_report; - pDM_Odm->AntDetectedInfo.dBForAntO = AntO_report; - - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("return FALSE!!\n")); - bResult = FALSE; + p_dm_odm->ant_detected_info.is_ant_detected = true; + p_dm_odm->ant_detected_info.db_for_ant_a = ant_a_report; + p_dm_odm->ant_detected_info.db_for_ant_b = ant_b_report; + p_dm_odm->ant_detected_info.db_for_ant_o = ant_0_report; + + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("return false!!\n")); + is_result = false; } } - return bResult; + return is_result; } -//1 [2. Scan AP RSSI Method] ================================================== +/* 1 [2. Scan AP RSSI method] ================================================== */ -BOOLEAN -ODM_SwAntDivCheckBeforeLink( - IN PVOID pDM_VOID - ) +boolean +odm_sw_ant_div_check_before_link( + void *p_dm_void +) { #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter); - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - s1Byte Score = 0; - PRT_WLAN_BSS pTmpBssDesc, pTestBssDesc; - u1Byte power_target_L = 9, power_target_H = 16; - u1Byte tmp_power_diff = 0,power_diff = 0,avg_power_diff = 0,max_power_diff = 0,min_power_diff = 0xff; - u2Byte index, counter = 0; - static u1Byte ScanChannel; - u4Byte tmp_SWAS_NoLink_BK_Reg948; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", pDM_Odm->DM_SWAT_Table.ANTA_ON, pDM_Odm->DM_SWAT_Table.ANTB_ON)); - - //if(HP id) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + s8 score = 0; + PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc; + u8 power_target_L = 9, power_target_H = 16; + u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff; + u16 index, counter = 0; + static u8 scan_channel; + u32 tmp_swas_no_link_bk_reg948; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", p_dm_odm->dm_swat_table.ANTA_ON, p_dm_odm->dm_swat_table.ANTB_ON)); + + /* if(HP id) */ { - if(pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult==TRUE && pDM_Odm->SupportICType == ODM_RTL8723B) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n")); - return FALSE; + if (p_dm_odm->dm_swat_table.rssi_ant_dect_result == true && p_dm_odm->support_ic_type == ODM_RTL8723B) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n")); + return false; } - - if(pDM_Odm->SupportICType == ODM_RTL8723B) - { - if(pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 == 0xff) - pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch ); + + if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (p_dm_swat_table->swas_no_link_bk_reg948 == 0xff) + p_dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(p_dm_odm, REG_S0_S1_PATH_SWITCH); } } - if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413 - { // The ODM structure is not initialized. - return FALSE; + if (p_dm_odm->adapter == NULL) { /* For BSOD when plug/unplug fast. //By YJ,120413 */ + /* The ODM structure is not initialized. */ + return false; } - // Retrieve antenna detection registry info, added by Roger, 2012.11.27. - if(!IS_ANT_DETECT_SUPPORT_RSSI(Adapter)) - { - return FALSE; - } + /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */ + if (!IS_ANT_DETECT_SUPPORT_RSSI(adapter)) + return false; else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI Method\n")); - } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI method\n")); - // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. - PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK); - if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect) - { - PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("ODM_SwAntDivCheckBeforeLink(): RFChangeInProgress(%x), eRFPowerState(%x)\n", - pMgntInfo->RFChangeInProgress, pHalData->eRFPowerState)); - - pDM_SWAT_Table->SWAS_NoLink_State = 0; - - return FALSE; - } - else - { - PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("pDM_SWAT_Table->SWAS_NoLink_State = %d\n", pDM_SWAT_Table->SWAS_NoLink_State)); - //1 Run AntDiv mechanism "Before Link" part. - if(pDM_SWAT_Table->SWAS_NoLink_State == 0) - { - //1 Prepare to do Scan again to check current antenna state. - - // Set check state to next step. - pDM_SWAT_Table->SWAS_NoLink_State = 1; - - // Copy Current Scan list. - pMgntInfo->tmpNumBssDesc = pMgntInfo->NumBssDesc; - PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC); - - // Go back to scan function again. - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Scan one more time\n")); - pMgntInfo->ScanStep=0; - pMgntInfo->bScanAntDetect = TRUE; - ScanChannel = odm_SwAntDivSelectScanChnl(Adapter); - - - if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821)) - { - if(pDM_FatTable->RxIdleAnt == MAIN_ANT) - ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); + /* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */ + odm_acquire_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK); + if (p_hal_data->eRFPowerState != eRfOn || p_mgnt_info->RFChangeInProgress || p_mgnt_info->bMediaConnect) { + odm_release_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("odm_sw_ant_div_check_before_link(): rf_change_in_progress(%x), e_rf_power_state(%x)\n", + p_mgnt_info->RFChangeInProgress, p_hal_data->eRFPowerState)); + + p_dm_swat_table->swas_no_link_state = 0; + + return false; + } else + odm_release_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->swas_no_link_state = %d\n", p_dm_swat_table->swas_no_link_state)); + /* 1 Run AntDiv mechanism "Before Link" part. */ + if (p_dm_swat_table->swas_no_link_state == 0) { + /* 1 Prepare to do Scan again to check current antenna state. */ + + /* Set check state to next step. */ + p_dm_swat_table->swas_no_link_state = 1; + + /* Copy Current Scan list. */ + p_mgnt_info->tmpNumBssDesc = p_mgnt_info->NumBssDesc; + PlatformMoveMemory((void *)adapter->MgntInfo.tmpbssDesc, (void *)p_mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC); + + /* Go back to scan function again. */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Scan one more time\n")); + p_mgnt_info->ScanStep = 0; + p_mgnt_info->bScanAntDetect = true; + scan_channel = odm_sw_ant_div_select_scan_chnl(adapter); + + + if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) { + if (p_dm_fat_table->rx_idle_ant == MAIN_ANT) + odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); else - ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); - if(ScanChannel == 0) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("ODM_SwAntDivCheckBeforeLink(): No AP List Avaiable, Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT")); - - if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode)) - { - pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - } - else - { - pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); + if (scan_channel == 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("odm_sw_ant_div_check_before_link(): No AP List Avaiable, Using ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT")); + + if (IS_5G_WIRELESS_MODE(p_mgnt_info->dot11CurrentWirelessMode)) { + p_dm_swat_table->ant_5g = p_dm_fat_table->rx_idle_ant; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_5g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + } else { + p_dm_swat_table->ant_2g = p_dm_fat_table->rx_idle_ant; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_2g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); } - return FALSE; + return false; } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("ODM_SwAntDivCheckBeforeLink: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT"))); - } else if (pDM_Odm->SupportICType & (ODM_RTL8723B)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("odm_sw_ant_div_check_before_link: Change to %s for testing.\n", ((p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"))); + } else if (p_dm_odm->support_ic_type & (ODM_RTL8723B)) { /*Switch Antenna to another one.*/ - - tmp_SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch); - - if ((pDM_SWAT_Table->CurAntenna == MAIN_ANT) && (tmp_SWAS_NoLink_BK_Reg948 == 0x200)) { - ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280); - ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1); - pDM_SWAT_Table->CurAntenna = AUX_ANT; + + tmp_swas_no_link_bk_reg948 = odm_read_4byte(p_dm_odm, REG_S0_S1_PATH_SWITCH); + + if ((p_dm_swat_table->cur_antenna == MAIN_ANT) && (tmp_swas_no_link_bk_reg948 == 0x200)) { + odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280); + odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x1); + p_dm_swat_table->cur_antenna = AUX_ANT; } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_SWAS_NoLink_BK_Reg948)); - return FALSE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_swas_no_link_bk_reg948)); + return false; } - ODM_StallExecution(10); + odm_stall_execution(10); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Change to (( %s-ant)) for testing.\n", (pDM_SWAT_Table->CurAntenna == MAIN_ANT)?"MAIN":"AUX")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Change to (( %s-ant)) for testing.\n", (p_dm_swat_table->cur_antenna == MAIN_ANT) ? "MAIN" : "AUX")); } - - odm_SwAntDivConstructScanChnl(Adapter, ScanChannel); - PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); - return TRUE; - } - else //pDM_SWAT_Table->SWAS_NoLink_State == 1 - { - //1 ScanComple() is called after antenna swiched. - //1 Check scan result and determine which antenna is going - //1 to be used. - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" tmpNumBssDesc= (( %d )) \n",pMgntInfo->tmpNumBssDesc));// debug for Dino - - for(index = 0; index < pMgntInfo->tmpNumBssDesc; index++) - { - pTmpBssDesc = &(pMgntInfo->tmpbssDesc[index]); // Antenna 1 - pTestBssDesc = &(pMgntInfo->bssDesc[index]); // Antenna 2 - - if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): ERROR!! This shall not happen.\n")); + odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel); + PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5); + + return true; + } else { /* p_dm_swat_table->swas_no_link_state == 1 */ + /* 1 ScanComple() is called after antenna swiched. */ + /* 1 Check scan result and determine which antenna is going */ + /* 1 to be used. */ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" tmp_num_bss_desc= (( %d ))\n", p_mgnt_info->tmpNumBssDesc)); /* debug for Dino */ + + for (index = 0; index < p_mgnt_info->tmpNumBssDesc; index++) { + p_tmp_bss_desc = &(p_mgnt_info->tmpbssDesc[index]); /* Antenna 1 */ + p_test_bss_desc = &(p_mgnt_info->bssDesc[index]); /* Antenna 2 */ + + if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): ERROR!! This shall not happen.\n")); continue; } - if(pDM_Odm->SupportICType != ODM_RTL8723B) - { - if(pTmpBssDesc->ChannelNumber == ScanChannel) - { - if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score++\n")); - RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); - - Score++; - PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); - } - else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score--\n")); - RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); - Score--; - } - else - { - if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp < 5000) - { - RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("The 2nd Antenna didn't get this AP\n\n")); + if (p_dm_odm->support_ic_type != ODM_RTL8723B) { + if (p_tmp_bss_desc->ChannelNumber == scan_channel) { + if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Compare scan entry: score++\n")); + RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); + + score++; + PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS)); + } else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Compare scan entry: score--\n")); + RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); + score--; + } else { + if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) { + RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("The 2nd Antenna didn't get this AP\n\n")); } } } - } - else // 8723B - { - if(pTmpBssDesc->ChannelNumber == ScanChannel) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ChannelNumber == ScanChannel -> (( %d )) \n", pTmpBssDesc->ChannelNumber )); - - if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) // Pow(Ant1) > Pow(Ant2) - { + } else { /* 8723B */ + if (p_tmp_bss_desc->ChannelNumber == scan_channel) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber)); + + if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */ counter++; - tmp_power_diff=(u1Byte)(pTmpBssDesc->RecvSignalPower - pTestBssDesc->RecvSignalPower); - power_diff = power_diff + tmp_power_diff; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); - ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf); - ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf); - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d)) \n", tmp_power_diff,max_power_diff,min_power_diff)); - if(tmp_power_diff > max_power_diff) - max_power_diff=tmp_power_diff; - if(tmp_power_diff < min_power_diff) - min_power_diff=tmp_power_diff; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d)) \n",max_power_diff,min_power_diff)); - - PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); - } - else if(pTestBssDesc->RecvSignalPower > pTmpBssDesc->RecvSignalPower) // Pow(Ant1) < Pow(Ant2) - { + tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower); + power_diff = power_diff + tmp_power_diff; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf); + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf); + + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff)); */ + if (tmp_power_diff > max_power_diff) + max_power_diff = tmp_power_diff; + if (tmp_power_diff < min_power_diff) + min_power_diff = tmp_power_diff; + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff)); */ + + PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS)); + } else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */ counter++; - tmp_power_diff=(u1Byte)(pTestBssDesc->RecvSignalPower - pTmpBssDesc->RecvSignalPower); - power_diff = power_diff + tmp_power_diff; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); - ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf); - ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf); - if(tmp_power_diff > max_power_diff) - max_power_diff=tmp_power_diff; - if(tmp_power_diff < min_power_diff) - min_power_diff=tmp_power_diff; - } - else // Pow(Ant1) = Pow(Ant2) - { - if(pTestBssDesc->bdTstamp > pTmpBssDesc->bdTstamp) // Stamp(Ant1) < Stamp(Ant2) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000)); - if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp > 5000) - { - counter++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); - ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf); - ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf); + tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower); + power_diff = power_diff + tmp_power_diff; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf); + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf); + if (tmp_power_diff > max_power_diff) + max_power_diff = tmp_power_diff; + if (tmp_power_diff < min_power_diff) + min_power_diff = tmp_power_diff; + } else { /* Pow(Ant1) = Pow(Ant2) */ + if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000)); + if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) { + counter++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf); + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf); min_power_diff = 0; - } + } + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000)); } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000)); - } } } } - } - if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821)) - { - if(pMgntInfo->NumBssDesc!=0 && Score<0) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("ODM_SwAntDivCheckBeforeLink(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("ODM_SwAntDivCheckBeforeLink(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT")); + if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) { + if (p_mgnt_info->NumBssDesc != 0 && score < 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("odm_sw_ant_div_check_before_link(): Using ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("odm_sw_ant_div_check_before_link(): Remain ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT")); - if(pDM_FatTable->RxIdleAnt == MAIN_ANT) - ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); + if (p_dm_fat_table->rx_idle_ant == MAIN_ANT) + odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); else - ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); + odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); } - - if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode)) - { - pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - } - else - { - pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - } - } - else if(pDM_Odm->SupportICType == ODM_RTL8723B) - { - if(counter == 0) - { - if(pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec == FALSE) - { - pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = TRUE; - pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again \n")); - - //3 [ Scan again ] - odm_SwAntDivConstructScanChnl(Adapter, ScanChannel); - PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); - return TRUE; - } - else// Pre_Aux_FailDetec == TRUE - { - //2 [ Single Antenna ] - pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE; - pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Still cannot find any AP ]] \n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); - } - pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter++; + + if (IS_5G_WIRELESS_MODE(p_mgnt_info->dot11CurrentWirelessMode)) { + p_dm_swat_table->ant_5g = p_dm_fat_table->rx_idle_ant; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_5g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + } else { + p_dm_swat_table->ant_2g = p_dm_fat_table->rx_idle_ant; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_2g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); } - else - { - pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE; - - if(counter==3) - { - avg_power_diff = ((power_diff-max_power_diff - min_power_diff)>>1)+ ((max_power_diff + min_power_diff)>>2); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff)); - } - else if(counter>=4) - { - avg_power_diff=(power_diff-max_power_diff - min_power_diff) / (counter - 2); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff)); - + } else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (counter == 0) { + if (p_dm_odm->dm_swat_table.pre_aux_fail_detec == false) { + p_dm_odm->dm_swat_table.pre_aux_fail_detec = true; + p_dm_odm->dm_swat_table.rssi_ant_dect_result = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n")); + + /* 3 [ Scan again ] */ + odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel); + PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5); + return true; + } else { /* pre_aux_fail_detec == true */ + /* 2 [ Single Antenna ] */ + p_dm_odm->dm_swat_table.pre_aux_fail_detec = false; + p_dm_odm->dm_swat_table.rssi_ant_dect_result = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter=(( 0 )) , [[ Still cannot find any AP ]]\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n")); } - else//counter==1,2 - { - avg_power_diff=power_diff/counter; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d )) \n", avg_power_diff,counter, power_diff)); + p_dm_odm->dm_swat_table.aux_fail_detec_counter++; + } else { + p_dm_odm->dm_swat_table.pre_aux_fail_detec = false; + + if (counter == 3) { + avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff)); + } else if (counter >= 4) { + avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff)); + + } else { /* counter==1,2 */ + avg_power_diff = power_diff / counter; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff)); } - //2 [ Retry ] - if( (avg_power_diff >=power_target_L) && (avg_power_diff <=power_target_H) ) - { - pDM_Odm->DM_SWAT_Table.Retry_Counter++; - - if(pDM_Odm->DM_SWAT_Table.Retry_Counter<=3) - { - pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]] \n", avg_power_diff)); - - //3 [ Scan again ] - odm_SwAntDivConstructScanChnl(Adapter, ScanChannel); - PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); - return TRUE; + /* 2 [ Retry ] */ + if ((avg_power_diff >= power_target_L) && (avg_power_diff <= power_target_H)) { + p_dm_odm->dm_swat_table.retry_counter++; + + if (p_dm_odm->dm_swat_table.retry_counter <= 3) { + p_dm_odm->dm_swat_table.rssi_ant_dect_result = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff)); + + /* 3 [ Scan again ] */ + odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel); + PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5); + return true; + } else { + p_dm_odm->dm_swat_table.rssi_ant_dect_result = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( retry_counter > 3 ))\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n")); } - else - { - pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( Retry_Counter > 3 )) \n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); - } - + } - //2 [ Dual Antenna ] - else if( (pMgntInfo->NumBssDesc != 0) && (avg_power_diff < power_target_L) ) - { - pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; - if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE) - { - pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; - pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE; + /* 2 [ Dual Antenna ] */ + else if ((p_mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) { + p_dm_odm->dm_swat_table.rssi_ant_dect_result = true; + if (p_dm_odm->dm_swat_table.ANTB_ON == false) { + p_dm_odm->dm_swat_table.ANTA_ON = true; + p_dm_odm->dm_swat_table.ANTB_ON = true; } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n")); - pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter++; - - // set bt coexDM from 1ant coexDM to 2ant coexDM - BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 2); - - //3 [ Init antenna diversity ] - pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; - ODM_AntDivInit(pDM_Odm); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Dual antenna\n")); + p_dm_odm->dm_swat_table.dual_ant_counter++; + + /* set bt coexDM from 1ant coexDM to 2ant coexDM */ + BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); + + /* 3 [ Init antenna diversity ] */ + p_dm_odm->support_ability |= ODM_BB_ANT_DIV; + odm_ant_div_init(p_dm_odm); } - //2 [ Single Antenna ] - else if(avg_power_diff > power_target_H) - { - pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; - if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE) - { - pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; - pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE; - //BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 1); + /* 2 [ Single Antenna ] */ + else if (avg_power_diff > power_target_H) { + p_dm_odm->dm_swat_table.rssi_ant_dect_result = true; + if (p_dm_odm->dm_swat_table.ANTB_ON == true) { + p_dm_odm->dm_swat_table.ANTA_ON = true; + p_dm_odm->dm_swat_table.ANTB_ON = false; + /* bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */ } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); - pDM_Odm->DM_SWAT_Table.Single_Ant_Counter++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n")); + p_dm_odm->dm_swat_table.single_ant_counter++; } } - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bResult=(( %d ))\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Dual_Ant_Counter = (( %d )), Single_Ant_Counter = (( %d )) , Retry_Counter = (( %d )) , Aux_FailDetec_Counter = (( %d ))\n\n\n", - pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter,pDM_Odm->DM_SWAT_Table.Single_Ant_Counter,pDM_Odm->DM_SWAT_Table.Retry_Counter,pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter)); + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_result=(( %d ))\n",p_dm_odm->dm_swat_table.rssi_ant_dect_result)); */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n", + p_dm_odm->dm_swat_table.dual_ant_counter, p_dm_odm->dm_swat_table.single_ant_counter, p_dm_odm->dm_swat_table.retry_counter, p_dm_odm->dm_swat_table.aux_fail_detec_counter)); + + /* 2 recover the antenna setting */ + + if (p_dm_odm->dm_swat_table.ANTB_ON == false) + odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, (p_dm_swat_table->swas_no_link_bk_reg948)); - //2 recover the antenna setting + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_result=(( %d )), Recover Reg[948]= (( %x )) \n\n", p_dm_odm->dm_swat_table.rssi_ant_dect_result, p_dm_swat_table->swas_no_link_bk_reg948)); - if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE) - ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, (pDM_SWAT_Table->SWAS_NoLink_BK_Reg948)); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("bResult=(( %d )), Recover Reg[948]= (( %x )) \n\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult, pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 )); - } - - // Check state reset to default and wait for next time. - pDM_SWAT_Table->SWAS_NoLink_State = 0; - pMgntInfo->bScanAntDetect = FALSE; - return FALSE; + /* Check state reset to default and wait for next time. */ + p_dm_swat_table->swas_no_link_state = 0; + p_mgnt_info->bScanAntDetect = false; + + return false; } #else - return FALSE; + return false; #endif -return FALSE; + return false; } @@ -708,257 +620,219 @@ return FALSE; -//1 [3. PSD Method] ========================================================== - +/* 1 [3. PSD method] ========================================================== */ +void +odm_single_dual_antenna_detection_psd( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 channel_ori; + u8 initial_gain = 0x36; + u8 tone_idx; + u8 tone_lenth_1 = 7, tone_lenth_2 = 4; + u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56}; + u16 tone_idx_2[4] = {8, 24, 40, 56}; + u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0}; + /* u8 tone_lenth_1=4, tone_lenth_2=2; */ + /* u16 tone_idx_1[4]={88, 120, 24, 56}; */ + /* u16 tone_idx_2[2]={ 24, 56}; */ + /* u32 psd_report_main[6]={0}, psd_report_aux[6]={0}; */ + + u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0; + u32 PSD_power_threshold; + u32 main_psd_result = 0, aux_psd_result = 0; + u32 regc50, reg948, regb2c, regc14, reg908; + u32 i = 0, test_num = 8; + + + if (p_dm_odm->support_ic_type != ODM_RTL8723B) + return; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection_psd()============>\n")); + /* 2 [ Backup Current RF/BB Settings ] */ -u4Byte -odm_GetPSDData( - IN PVOID pDM_VOID, - IN u2Byte point, - IN u1Byte initial_gain) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte psd_report; - - ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); - ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); //Start PSD calculation, Reg808[22]=0->1 - ODM_StallExecution(150);//Wait for HW PSD report - ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);//Stop PSD calculation, Reg808[22]=1->0 - psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;//Read PSD report, Reg8B4[15:0] - - psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report));//+(u4Byte)(initial_gain); - return psd_report; -} + channel_ori = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK); + reg948 = odm_get_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD); + regb2c = odm_get_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD); + regc50 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD); + regc14 = odm_get_bb_reg(p_dm_odm, 0xc14, MASKDWORD); + reg908 = odm_get_bb_reg(p_dm_odm, 0x908, MASKDWORD); + /* 2 [ setting for doing PSD function (CH4)] */ + odm_set_bb_reg(p_dm_odm, REG_FPGA0_RFMOD, BIT(24), 0); /* disable whole CCK block */ + odm_write_1byte(p_dm_odm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */ + odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */ - -VOID -ODM_SingleDualAntennaDetection_PSD( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte Channel_ori; - u1Byte initial_gain = 0x36; - u1Byte tone_idx; - u1Byte Tone_lenth_1=7, Tone_lenth_2=4; - u2Byte Tone_idx_1[7]={88, 104, 120, 8, 24, 40, 56}; - u2Byte Tone_idx_2[4]={8, 24, 40, 56}; - u4Byte PSD_report_Main[11]={0}, PSD_report_Aux[11]={0}; - //u1Byte Tone_lenth_1=4, Tone_lenth_2=2; - //u2Byte Tone_idx_1[4]={88, 120, 24, 56}; - //u2Byte Tone_idx_2[2]={ 24, 56}; - //u4Byte PSD_report_Main[6]={0}, PSD_report_Aux[6]={0}; - - u4Byte PSD_report_temp,MAX_PSD_report_Main=0,MAX_PSD_report_Aux=0; - u4Byte PSD_power_threshold; - u4Byte Main_psd_result=0, Aux_psd_result=0; - u4Byte Regc50, Reg948, Regb2c,Regc14,Reg908; - u4Byte i=0,test_num=8; - - - if(pDM_Odm->SupportICType != ODM_RTL8723B) - return; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection_PSD()============> \n")); - - //2 [ Backup Current RF/BB Settings ] - - Channel_ori = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); - Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord); - Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord); - Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); - Regc14 = ODM_GetBBReg(pDM_Odm, 0xc14, bMaskDWord); - Reg908 = ODM_GetBBReg(pDM_Odm, 0x908, bMaskDWord); - - //2 [ Setting for doing PSD function (CH4)] - ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); //disable whole CCK block - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // Turn off TX -> Pause TX Queue - ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); // [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] - - // PHYTXON while loop - ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, 0x803); - while (ODM_GetBBReg(pDM_Odm, 0xdf4, BIT6)) - { + /* PHYTXON while loop */ + odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, 0x803); + while (odm_get_bb_reg(p_dm_odm, 0xdf4, BIT(6))) { i++; - if (i > 1000000) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i)); + if (i > 1000000) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i)); break; } } - - ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH4 & 40M - ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf - ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pt //Set PSD 128 ptss - ODM_StallExecution(3000); - - - //2 [ Doing PSD Function in (CH4)] - - //Antenna A - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n")); - ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200); - ODM_StallExecution(10); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n")); - for (i=0;iPSD_report_Main[tone_idx] ) - PSD_report_Main[tone_idx]+=PSD_report_temp; + + odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, initial_gain); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */ + odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ + odm_set_bb_reg(p_dm_odm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */ + odm_stall_execution(3000); + + + /* 2 [ Doing PSD Function in (CH4)] */ + + /* Antenna A */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n")); + odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x200); + odm_stall_execution(10); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n")); + for (i = 0; i < test_num; i++) { + for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) { + PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_1[tone_idx], initial_gain); + /* if( PSD_report_temp>psd_report_main[tone_idx] ) */ + psd_report_main[tone_idx] += PSD_report_temp; } } - //Antenna B - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n")); - ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280); - ODM_StallExecution(10); - for (i=0;iPSD_report_Aux[tone_idx] ) - PSD_report_Aux[tone_idx]+=PSD_report_temp; + /* Antenna B */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n")); + odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x280); + odm_stall_execution(10); + for (i = 0; i < test_num; i++) { + for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) { + PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_1[tone_idx], initial_gain); + /* if( PSD_report_temp>psd_report_aux[tone_idx] ) */ + psd_report_aux[tone_idx] += PSD_report_temp; } } - //2 [ Doing PSD Function in (CH8)] - - ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0 - ODM_StallExecution(3000); - - ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH8 & 40M - - ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf - ODM_StallExecution(3000); - - //Antenna A - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n")); - ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200); - ODM_StallExecution(10); - - for (i=0;iPSD_report_Main[tone_idx] ) - PSD_report_Main[Tone_lenth_1+tone_idx]+=PSD_report_temp; + /* 2 [ Doing PSD Function in (CH8)] */ + + odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ + odm_stall_execution(3000); + + odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, initial_gain); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */ + + odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ + odm_stall_execution(3000); + + /* Antenna A */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n")); + odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x200); + odm_stall_execution(10); + + for (i = 0; i < test_num; i++) { + for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) { + PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_2[tone_idx], initial_gain); + /* if( PSD_report_temp>psd_report_main[tone_idx] ) */ + psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp; } } - //Antenna B - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n")); - ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280); - ODM_StallExecution(10); + /* Antenna B */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n")); + odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x280); + odm_stall_execution(10); - for (i=0;iPSD_report_Aux[tone_idx] ) - PSD_report_Aux[Tone_lenth_1+tone_idx]+=PSD_report_temp; + for (i = 0; i < test_num; i++) { + for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) { + PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_2[tone_idx], initial_gain); + /* if( PSD_report_temp>psd_report_aux[tone_idx] ) */ + psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp; } } - //2 [ Calculate Result ] + /* 2 [ Calculate Result ] */ - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL) \n")); - for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Main[tone_idx] )); - Main_psd_result+= PSD_report_Main[tone_idx]; - if(PSD_report_Main[tone_idx]>MAX_PSD_report_Main) - MAX_PSD_report_Main=PSD_report_Main[tone_idx]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL)\n")); + for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_main[tone_idx])); + main_psd_result += psd_report_main[tone_idx]; + if (psd_report_main[tone_idx] > max_psd_report_main) + max_psd_report_main = psd_report_main[tone_idx]; } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", Main_psd_result)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", MAX_PSD_report_Main)); - + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", main_psd_result)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", max_psd_report_main)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL) \n")); - for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Aux[tone_idx] )); - Aux_psd_result+= PSD_report_Aux[tone_idx]; - if(PSD_report_Aux[tone_idx]>MAX_PSD_report_Aux) - MAX_PSD_report_Aux=PSD_report_Aux[tone_idx]; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL)\n")); + for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_aux[tone_idx])); + aux_psd_result += psd_report_aux[tone_idx]; + if (psd_report_aux[tone_idx] > max_psd_report_aux) + max_psd_report_aux = psd_report_aux[tone_idx]; } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", Aux_psd_result)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", MAX_PSD_report_Aux)); - - //Main_psd_result=Main_psd_result-MAX_PSD_report_Main; - //Aux_psd_result=Aux_psd_result-MAX_PSD_report_Aux; - PSD_power_threshold=(Main_psd_result*7)>>3; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result , Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", Main_psd_result, Aux_psd_result,PSD_power_threshold)); - - //3 [ Dual Antenna ] - if(Aux_psd_result >= PSD_power_threshold ) - { - if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE) - { - pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; - pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n")); - - // set bt coexDM from 1ant coexDM to 2ant coexDM - //BT_SetBtCoexAntNum(pAdapter, BT_COEX_ANT_TYPE_DETECTED, 2); - - // Init antenna diversity - pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; - ODM_AntDivInit(pDM_Odm); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", aux_psd_result)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", max_psd_report_aux)); + + /* main_psd_result=main_psd_result-max_psd_report_main; */ + /* aux_psd_result=aux_psd_result-max_psd_report_aux; */ + PSD_power_threshold = (main_psd_result * 7) >> 3; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", main_psd_result, aux_psd_result, PSD_power_threshold)); + + /* 3 [ Dual Antenna ] */ + if (aux_psd_result >= PSD_power_threshold) { + if (p_dm_odm->dm_swat_table.ANTB_ON == false) { + p_dm_odm->dm_swat_table.ANTA_ON = true; + p_dm_odm->dm_swat_table.ANTB_ON = true; } - //3 [ Single Antenna ] - else - { - if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE) - { - pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; - pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Dual antenna\n")); + + /* set bt coexDM from 1ant coexDM to 2ant coexDM */ + /* bt_set_bt_coex_ant_num(p_adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */ + + /* Init antenna diversity */ + p_dm_odm->support_ability |= ODM_BB_ANT_DIV; + odm_ant_div_init(p_dm_odm); + } + /* 3 [ Single Antenna ] */ + else { + if (p_dm_odm->dm_swat_table.ANTB_ON == true) { + p_dm_odm->dm_swat_table.ANTA_ON = true; + p_dm_odm->dm_swat_table.ANTB_ON = false; } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n")); } - //2 [ Recover all parameters ] - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,Channel_ori); - ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0 - ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, Regc50); - - ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948); - ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c); - - ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); //enable whole CCK block - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x0); //Turn on TX // Resume TX Queue - ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, Regc14); // [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] - ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, Reg908); - + /* 2 [ Recover all parameters ] */ + + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori); + odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ + odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, regc50); + + odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948); + odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c); + + odm_set_bb_reg(p_dm_odm, REG_FPGA0_RFMOD, BIT(24), 1); /* enable whole CCK block */ + odm_write_1byte(p_dm_odm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */ + odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, regc14); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */ + odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, reg908); + return; } #endif void -odm_SwAntDetectInit( - IN PVOID pDM_VOID - ) +odm_sw_ant_detect_init( + void *p_dm_void +) { -#if(defined(CONFIG_ANT_DETECTION)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - - //pDM_SWAT_Table->PreAntenna = MAIN_ANT; - //pDM_SWAT_Table->CurAntenna = MAIN_ANT; - pDM_SWAT_Table->SWAS_NoLink_State = 0; - pDM_SWAT_Table->Pre_Aux_FailDetec = FALSE; - pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = 0xff; +#if (defined(CONFIG_ANT_DETECTION)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + + /* p_dm_swat_table->pre_antenna = MAIN_ANT; */ + /* p_dm_swat_table->cur_antenna = MAIN_ANT; */ + p_dm_swat_table->swas_no_link_state = 0; + p_dm_swat_table->pre_aux_fail_detec = false; + p_dm_swat_table->swas_no_link_bk_reg948 = 0xff; + + #if (CONFIG_PSD_TOOL == 1) + phydm_psd_init(p_dm_odm); + #endif #endif } - diff --git a/hal/phydm/phydm_antdect.h b/hal/phydm/phydm_antdect.h index 8cf60e8..74627fc 100644 --- a/hal/phydm/phydm_antdect.h +++ b/hal/phydm/phydm_antdect.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,88 +11,80 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - + *****************************************************************************/ + #ifndef __PHYDMANTDECT_H__ #define __PHYDMANTDECT_H__ #define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/ -#if(defined(CONFIG_ANT_DETECTION)) -//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) -//ANT Test -#define ANTTESTALL 0x00 /*Ant A or B will be Testing*/ -#define ANTTESTA 0x01 /*Ant A will be Testing*/ -#define ANTTESTB 0x02 /*Ant B will be testing*/ +#if (defined(CONFIG_ANT_DETECTION)) +/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */ +/* ANT Test */ +#define ANTTESTALL 0x00 /*ant A or B will be Testing*/ +#define ANTTESTA 0x01 /*ant A will be Testing*/ +#define ANTTESTB 0x02 /*ant B will be testing*/ -#define MAX_ANTENNA_DETECTION_CNT 10 +#define MAX_ANTENNA_DETECTION_CNT 10 -typedef struct _ANT_DETECTED_INFO{ - BOOLEAN bAntDetected; - u4Byte dBForAntA; - u4Byte dBForAntB; - u4Byte dBForAntO; -}ANT_DETECTED_INFO, *PANT_DETECTED_INFO; +struct _ANT_DETECTED_INFO { + boolean is_ant_detected; + u32 db_for_ant_a; + u32 db_for_ant_b; + u32 db_for_ant_o; +}; -typedef enum tag_SW_Antenna_Switch_Definition -{ - Antenna_A = 1, - Antenna_B = 2, - Antenna_MAX = 3, -}DM_SWAS_E; +enum dm_swas_e { + antenna_a = 1, + antenna_b = 2, + antenna_max = 3, +}; -//1 [1. Single Tone Method] =================================================== +/* 1 [1. Single Tone method] =================================================== */ -VOID -ODM_SingleDualAntennaDefaultSetting( - IN PVOID pDM_VOID - ); +void +odm_single_dual_antenna_default_setting( + void *p_dm_void +); -BOOLEAN -ODM_SingleDualAntennaDetection( - IN PVOID pDM_VOID, - IN u1Byte mode - ); +boolean +odm_single_dual_antenna_detection( + void *p_dm_void, + u8 mode +); -//1 [2. Scan AP RSSI Method] ================================================== +/* 1 [2. Scan AP RSSI method] ================================================== */ -#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink +#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link -BOOLEAN -ODM_SwAntDivCheckBeforeLink( - IN PVOID pDM_VOID - ); +boolean +odm_sw_ant_div_check_before_link( + void *p_dm_void +); -//1 [3. PSD Method] ========================================================== +/* 1 [3. PSD method] ========================================================== */ -VOID -ODM_SingleDualAntennaDetection_PSD( - IN PVOID pDM_VOID +void +odm_single_dual_antenna_detection_psd( + void *p_dm_void ); #endif -VOID -odm_SwAntDetectInit( - IN PVOID pDM_VOID - ); +void +odm_sw_ant_detect_init( + void *p_dm_void +); #endif - - diff --git a/hal/phydm/phydm_antdiv.c b/hal/phydm/phydm_antdiv.c index e155f5c..0d79db8 100644 --- a/hal/phydm/phydm_antdiv.c +++ b/hal/phydm/phydm_antdiv.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,1516 +11,1448 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" -//====================================================== -// when antenna test utility is on or some testing need to disable antenna diversity -// call this function to disable all ODM related mechanisms which will switch antenna. -//====================================================== -VOID -ODM_StopAntennaSwitchDm( - IN PVOID pDM_VOID - ) +/* ****************************************************** + * when antenna test utility is on or some testing need to disable antenna diversity + * call this function to disable all ODM related mechanisms which will switch antenna. + * ****************************************************** */ +void +odm_stop_antenna_switch_dm( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - // disable ODM antenna diversity - pDM_Odm->SupportAbility &= ~ODM_BB_ANT_DIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("STOP Antenna Diversity \n")); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + /* disable ODM antenna diversity */ + p_dm_odm->support_ability &= ~ODM_BB_ANT_DIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("STOP Antenna Diversity\n")); } -VOID +void phydm_enable_antenna_diversity( - IN PVOID pDM_VOID - ) + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AntDiv is enabled & Re-Init AntDiv\n")); - odm_AntennaDiversityInit(pDM_Odm); + p_dm_odm->support_ability |= ODM_BB_ANT_DIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AntDiv is enabled & Re-Init AntDiv\n")); + odm_antenna_diversity_init(p_dm_odm); } -VOID -ODM_SetAntConfig( - IN PVOID pDM_VOID, - IN u1Byte antSetting // 0=A, 1=B, 2=C, .... - ) +void +odm_set_ant_config( + void *p_dm_void, + u8 ant_setting /* 0=A, 1=B, 2=C, .... */ +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if (pDM_Odm->SupportICType == ODM_RTL8723B) { - if (antSetting == 0) /* ant A*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); - else if (antSetting == 1) - ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); - } else if (pDM_Odm->SupportICType == ODM_RTL8723D) { - if (antSetting == 0) /* ant A*/ - ODM_SetBBReg(pDM_Odm, 0x948, bMaskLWord, 0x0000); - else if (antSetting == 1) - ODM_SetBBReg(pDM_Odm, 0x948, bMaskLWord, 0x0280); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (ant_setting == 0) /* ant A*/ + odm_set_bb_reg(p_dm_odm, 0x948, MASKDWORD, 0x00000000); + else if (ant_setting == 1) + odm_set_bb_reg(p_dm_odm, 0x948, MASKDWORD, 0x00000280); + } else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (ant_setting == 0) /* ant A*/ + odm_set_bb_reg(p_dm_odm, 0x948, MASKLWORD, 0x0000); + else if (ant_setting == 1) + odm_set_bb_reg(p_dm_odm, 0x948, MASKLWORD, 0x0280); } } -//====================================================== +/* ****************************************************** */ -VOID -ODM_SwAntDivRestAfterLink( - IN PVOID pDM_VOID - ) +void +odm_sw_ant_div_rest_after_link( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u4Byte i; +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + u32 i; - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { - - pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; - pDM_SWAT_Table->RSSI_Trying = 0; - pDM_SWAT_Table->Double_chk_flag= 0; - - pDM_FatTable->RxIdleAnt=MAIN_ANT; - - for (i=0; iMainAnt_Sum[i] = 0; - pDM_FatTable->AuxAnt_Sum[i] = 0; - pDM_FatTable->MainAnt_Cnt[i] = 0; - pDM_FatTable->AuxAnt_Cnt[i] = 0; - } + if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { + + p_dm_swat_table->try_flag = SWAW_STEP_INIT; + p_dm_swat_table->rssi_trying = 0; + p_dm_swat_table->double_chk_flag = 0; + p_dm_fat_table->rx_idle_ant = MAIN_ANT; + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + phydm_antdiv_reset_statistic(p_dm_odm, i); } + +#endif } #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) -VOID -odm_AntDiv_on_off( - IN PVOID pDM_VOID , - IN u1Byte swch - ) +void +phydm_antdiv_reset_statistic( + void *p_dm_void, + u32 macid +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - if(pDM_FatTable->AntDiv_OnOff != swch) - { - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + + p_dm_fat_table->main_ant_sum[macid] = 0; + p_dm_fat_table->aux_ant_sum[macid] = 0; + p_dm_fat_table->main_ant_cnt[macid] = 0; + p_dm_fat_table->aux_ant_cnt[macid] = 0; + p_dm_fat_table->main_ant_sum_cck[macid] = 0; + p_dm_fat_table->aux_ant_sum_cck[macid] = 0; + p_dm_fat_table->main_ant_cnt_cck[macid] = 0; + p_dm_fat_table->aux_ant_cnt_cck[macid] = 0; +} + +void +odm_ant_div_on_off( + void *p_dm_void, + u8 swch +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + + if (p_dm_fat_table->ant_div_on_off != swch) { + if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) return; - if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF")); - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); - ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); - - } - else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF")); - if (pDM_Odm->SupportICType == ODM_RTL8812) { - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable - ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable + if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF")); + odm_set_bb_reg(p_dm_odm, 0xc50, BIT(7), swch); + odm_set_bb_reg(p_dm_odm, 0xa00, BIT(15), swch); + +#if (RTL8723D_SUPPORT == 1) + /*Mingzhi 2017-05-08*/ + if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (swch == ANTDIV_ON) { + odm_set_bb_reg(p_dm_odm, 0xce0, BIT(1), 1); + odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 1); /*1:HW ctrl 0:SW ctrl*/ + } else { + odm_set_bb_reg(p_dm_odm, 0xce0, BIT(1), 0); + odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0); /*1:HW ctrl 0:SW ctrl*/ + } + } +#endif + + } else if (p_dm_odm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF")); + if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) { + odm_set_bb_reg(p_dm_odm, 0xc50, BIT(7), swch); /* OFDM AntDiv function block enable */ + odm_set_bb_reg(p_dm_odm, 0xa00, BIT(15), swch); /* CCK AntDiv function block enable */ } else { - ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, swch); //OFDM AntDiv function block enable - - if( (pDM_Odm->CutVersion >= ODM_CUT_C) && (pDM_Odm->SupportICType == ODM_RTL8821) && ( pDM_Odm->AntDivType != S0S1_SW_ANTDIV)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF")); - ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, swch); - ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, swch); //CCK AntDiv function block enable + odm_set_bb_reg(p_dm_odm, 0x8D4, BIT(24), swch); /* OFDM AntDiv function block enable */ + + if ((p_dm_odm->cut_version >= ODM_CUT_C) && (p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->ant_div_type != S0S1_SW_ANTDIV)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF")); + odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), swch); + odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */ + } else if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF")); + odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), swch); + odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */ } - } + } } } - pDM_FatTable->AntDiv_OnOff =swch; - + p_dm_fat_table->ant_div_on_off = swch; + } -VOID -phydm_FastTraining_enable( - IN PVOID pDM_VOID, - IN u1Byte swch - ) +void +phydm_fast_training_enable( + void *p_dm_void, + u8 swch +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte enable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 enable; if (swch == FAT_ON) - enable=1; + enable = 1; else - enable=0; + enable = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fast Ant Training_en = ((%d))\n", enable)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fast ant Training_en = ((%d))\n", enable)); - if (pDM_Odm->SupportICType == ODM_RTL8188E) { - ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, enable); /*enable fast training*/ + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + odm_set_bb_reg(p_dm_odm, 0xe08, BIT(16), enable); /*enable fast training*/ /**/ - } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { - ODM_SetBBReg(pDM_Odm, 0xB34 , BIT28, enable); /*enable fast training (path-A)*/ - /*ODM_SetBBReg(pDM_Odm, 0xB34 , BIT29, enable);*/ /*enable fast training (path-B)*/ - } else if (pDM_Odm->SupportICType == ODM_RTL8821) { - ODM_SetBBReg(pDM_Odm, 0x900 , BIT19, enable); /*enable fast training */ + } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(p_dm_odm, 0xB34, BIT(28), enable); /*enable fast training (path-A)*/ + /*odm_set_bb_reg(p_dm_odm, 0xB34, BIT(29), enable);*/ /*enable fast training (path-B)*/ + } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) { + odm_set_bb_reg(p_dm_odm, 0x900, BIT(19), enable); /*enable fast training */ /**/ } } -phydm_keep_RxAckAnt_By_TxAnt_time( - IN PVOID pDM_VOID, - IN u4Byte time - ) +void +phydm_keep_rx_ack_ant_by_tx_ant_time( + void *p_dm_void, + u32 time +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/ - if (pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) { - - ODM_SetBBReg(pDM_Odm, 0xE20, BIT23|BIT22|BIT21|BIT20, time); + if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { + + odm_set_bb_reg(p_dm_odm, 0xE20, BIT(23) | BIT(22) | BIT(21) | BIT(20), time); /**/ - } else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) { + } else if (p_dm_odm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { - ODM_SetBBReg(pDM_Odm, 0x818, BIT23|BIT22|BIT21|BIT20, time); + odm_set_bb_reg(p_dm_odm, 0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), time); /**/ } } -VOID -odm_Tx_By_TxDesc_or_Reg( - IN PVOID pDM_VOID, - IN u1Byte swch - ) +void +odm_tx_by_tx_desc_or_reg( + void *p_dm_void, + u8 swch +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u1Byte enable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + u8 enable; - if (pDM_FatTable->b_fix_tx_ant == NO_FIX_TX_ANT) + if (p_dm_fat_table->b_fix_tx_ant == NO_FIX_TX_ANT) enable = (swch == TX_BY_DESC) ? 1 : 0; else enable = 0;/*Force TX by Reg*/ - if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) - { - if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) - { - ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, enable); - } - else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) - { - ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, enable); - } + if (p_dm_odm->ant_div_type != CGCS_RX_HW_ANTDIV) { + if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) + odm_set_bb_reg(p_dm_odm, 0x80c, BIT(21), enable); + else if (p_dm_odm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) + odm_set_bb_reg(p_dm_odm, 0x900, BIT(18), enable); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv] TX_Ant_BY (( %s ))\n", (enable == TX_BY_DESC) ? "DESC":"REG")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv] TX_Ant_BY (( %s ))\n", (enable == TX_BY_DESC) ? "DESC" : "REG")); } } -VOID -ODM_UpdateRxIdleAnt( - IN PVOID pDM_VOID, - IN u1Byte Ant - ) +void +odm_update_rx_idle_ant( + void *p_dm_void, + u8 ant +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u4Byte DefaultAnt, OptionalAnt, value32, Default_tx_Ant; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + u32 default_ant, optional_ant, value32, default_tx_ant; - if(pDM_FatTable->RxIdleAnt != Ant) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + if (p_dm_fat_table->rx_idle_ant != ant) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - if(!(pDM_Odm->SupportICType & ODM_RTL8723B)) - pDM_FatTable->RxIdleAnt = Ant; + if (!(p_dm_odm->support_ic_type & ODM_RTL8723B)) + p_dm_fat_table->rx_idle_ant = ant; - if(Ant == MAIN_ANT) - { - DefaultAnt = ANT1_2G; - OptionalAnt = ANT2_2G; - } - else - { - DefaultAnt = ANT2_2G; - OptionalAnt = ANT1_2G; + if (ant == MAIN_ANT) { + default_ant = ANT1_2G; + optional_ant = ANT2_2G; + } else { + default_ant = ANT2_2G; + optional_ant = ANT1_2G; } - - if (pDM_FatTable->b_fix_tx_ant != NO_FIX_TX_ANT) - Default_tx_Ant = (pDM_FatTable->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1; + + if (p_dm_fat_table->b_fix_tx_ant != NO_FIX_TX_ANT) + default_tx_ant = (p_dm_fat_table->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1; else - Default_tx_Ant = DefaultAnt; - - if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) - { - if(pDM_Odm->SupportICType==ODM_RTL8192E) - { - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, OptionalAnt);//Optional RX - ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt);//Default TX + default_tx_ant = default_ant; + + if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { + if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(p_dm_odm, 0xB38, BIT(5) | BIT4 | BIT3, default_ant); /* Default RX */ + odm_set_bb_reg(p_dm_odm, 0xB38, BIT(8) | BIT7 | BIT6, optional_ant); /* Optional RX */ + odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, default_ant); /* Default TX */ } - #if (RTL8723B_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8723B) { - - value32 = ODM_GetBBReg(pDM_Odm, 0x948, 0xFFF); - - if(value32 !=0x280) - ODM_UpdateRxIdleAnt_8723B(pDM_Odm, Ant, DefaultAnt, OptionalAnt); +#if (RTL8723B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + + value32 = odm_get_bb_reg(p_dm_odm, 0x948, 0xFFF); + + if (value32 != 0x280) + odm_update_rx_idle_ant_8723b(p_dm_odm, ant, default_ant, optional_ant); else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n")); } - #endif +#endif +#if (RTL8723D_SUPPORT == 1) /*Mingzhi 2017-05-08*/ + else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + phydm_set_tx_ant_pwr_8723d(p_dm_odm, ant); + odm_update_rx_idle_ant_8723d(p_dm_odm, ant, default_ant, optional_ant); + } +#endif else { /*8188E & 8188F*/ - - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - #if (RTL8723D_SUPPORT == 1) - phydm_set_tx_ant_pwr_8723d(pDM_Odm, Ant); - #endif - } - #if (RTL8188F_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8188F) { - phydm_update_rx_idle_antenna_8188F(pDM_Odm, DefaultAnt); - /**/ +#if (RTL8188F_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + phydm_update_rx_idle_antenna_8188F(p_dm_odm, default_ant); } - #endif - - ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); /*Default RX*/ - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); /*Optional RX*/ - ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, Default_tx_Ant); /*Default TX*/ +#endif + + odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT4 | BIT3, default_ant); /*Default RX*/ + odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT7 | BIT6, optional_ant); /*Optional RX*/ + odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, default_tx_ant); /*Default TX*/ } - } - else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) - { - u2Byte value16 = ODM_Read2Byte(pDM_Odm, ODM_REG_TRMUX_11AC+2); - // - // 2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt - // incorrect 0xc08 bit0-15 .We still not know why it is changed. - // - value16 &= ~(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3); - value16 |= ((u2Byte)DefaultAnt <<3); - value16 |= ((u2Byte)OptionalAnt <<6); - value16 |= ((u2Byte)DefaultAnt <<9); - ODM_Write2Byte(pDM_Odm, ODM_REG_TRMUX_11AC+2, value16); - /* - ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT21|BIT20|BIT19, DefaultAnt); //Default RX - ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT24|BIT23|BIT22, OptionalAnt);//Optional RX - ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT27|BIT26|BIT25, DefaultAnt); //Default TX - */ + } else if (p_dm_odm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { + u16 value16 = odm_read_2byte(p_dm_odm, ODM_REG_TRMUX_11AC + 2); + /* */ + /* 2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt */ + /* incorrect 0xc08 bit0-15 .We still not know why it is changed. */ + /* */ + value16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3)); + value16 |= ((u16)default_ant << 3); + value16 |= ((u16)optional_ant << 6); + value16 |= ((u16)default_ant << 9); + odm_write_2byte(p_dm_odm, ODM_REG_TRMUX_11AC + 2, value16); +#if 0 + odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(21) | BIT20 | BIT19, default_ant); /* Default RX */ + odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(24) | BIT23 | BIT22, optional_ant); /* Optional RX */ + odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(27) | BIT26 | BIT25, default_ant); /* Default TX */ +#endif } - if (pDM_Odm->SupportICType == ODM_RTL8188E) - { - ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT7|BIT6, Default_tx_Ant); /*PathA Resp Tx*/ + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(7) | BIT6, default_tx_ant); /*PathA Resp Tx*/ /**/ - } - else - { - ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT10|BIT9|BIT8, Default_tx_Ant); /*PathA Resp Tx*/ + } else { + odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(10) | BIT9 | BIT8, default_tx_ant); /*PathA Resp Tx*/ /**/ - } + } - } - else// pDM_FatTable->RxIdleAnt == Ant - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Stay in Ori-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - pDM_FatTable->RxIdleAnt = Ant; + } else { /* p_dm_fat_table->rx_idle_ant == ant */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Stay in Ori-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + p_dm_fat_table->rx_idle_ant = ant; } } -VOID -odm_UpdateTxAnt( - IN PVOID pDM_VOID, - IN u1Byte Ant, - IN u4Byte MacId - ) +void +odm_update_tx_ant( + void *p_dm_void, + u8 ant, + u32 mac_id +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u1Byte TxAnt; - - if (pDM_FatTable->b_fix_tx_ant != NO_FIX_TX_ANT) - Ant = (pDM_FatTable->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT; - - if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV) - { - TxAnt=Ant; - } - else - { - if(Ant == MAIN_ANT) - TxAnt = ANT1_2G; - else - TxAnt = ANT2_2G; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + u8 tx_ant; + + if (p_dm_fat_table->b_fix_tx_ant != NO_FIX_TX_ANT) + ant = (p_dm_fat_table->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT; + + if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) + tx_ant = ant; + else { + if (ant == MAIN_ANT) + tx_ant = ANT1_2G; + else + tx_ant = ANT2_2G; } - - pDM_FatTable->antsel_a[MacId] = TxAnt&BIT0; - pDM_FatTable->antsel_b[MacId] = (TxAnt&BIT1)>>1; - pDM_FatTable->antsel_c[MacId] = (TxAnt&BIT2)>>2; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Set TX-DESC value]: MacID:(( %d )), TxAnt = (( %s ))\n", MacId, (Ant == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] )); - + + p_dm_fat_table->antsel_a[mac_id] = tx_ant & BIT(0); + p_dm_fat_table->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1; + p_dm_fat_table->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Set TX-DESC value]: mac_id:(( %d )), tx_ant = (( %s ))\n", mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",p_dm_fat_table->antsel_c[mac_id] , p_dm_fat_table->antsel_b[mac_id] , p_dm_fat_table->antsel_a[mac_id] )); */ + } #ifdef BEAMFORMING_SUPPORT -#if(DM_ODM_SUPPORT_TYPE == ODM_AP) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -VOID -odm_BDC_Init( - IN PVOID pDM_VOID - ) +void +odm_bdc_init( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pBDC_T pDM_BdcTable=&pDM_Odm->DM_BdcTable; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[ BDC Initialization......] \n")); - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - pDM_BdcTable->BDC_Mode=BDC_MODE_NULL; - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDCcoexType_wBfer=0; - pDM_Odm->bdc_holdstate=0xff; - - if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - ODM_SetBBReg(pDM_Odm, 0xd7c , 0x0FFFFFFF, 0x1081008); - ODM_SetBBReg(pDM_Odm, 0xd80 , 0x0FFFFFFF, 0); - } - else if(pDM_Odm->SupportICType == ODM_RTL8812) - { - ODM_SetBBReg(pDM_Odm, 0x9b0 , 0x0FFFFFFF, 0x1081008); //0x9b0[30:0] = 01081008 - ODM_SetBBReg(pDM_Odm, 0x9b4 , 0x0FFFFFFF, 0); //0x9b4[31:0] = 00000000 + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[ BDC Initialization......]\n")); + p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + p_dm_bdc_table->bdc_mode = BDC_MODE_NULL; + p_dm_bdc_table->bdc_try_flag = 0; + p_dm_bdc_table->bd_ccoex_type_wbfer = 0; + p_dm_odm->bdc_holdstate = 0xff; + + if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(p_dm_odm, 0xd7c, 0x0FFFFFFF, 0x1081008); + odm_set_bb_reg(p_dm_odm, 0xd80, 0x0FFFFFFF, 0); + } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { + odm_set_bb_reg(p_dm_odm, 0x9b0, 0x0FFFFFFF, 0x1081008); /* 0x9b0[30:0] = 01081008 */ + odm_set_bb_reg(p_dm_odm, 0x9b4, 0x0FFFFFFF, 0); /* 0x9b4[31:0] = 00000000 */ } - + } -VOID +void odm_CSI_on_off( - IN PVOID pDM_VOID, - IN u1Byte CSI_en - ) + void *p_dm_void, + u8 CSI_en +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if(CSI_en==CSI_ON) - { - if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - ODM_SetMACReg(pDM_Odm, 0xd84 , BIT11, 1); //0xd84[11]=1 + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + if (CSI_en == CSI_ON) { + if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + odm_set_mac_reg(p_dm_odm, 0xd84, BIT(11), 1); /* 0xd84[11]=1 */ + } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { + odm_set_mac_reg(p_dm_odm, 0x9b0, BIT(31), 1); /* 0x9b0[31]=1 */ } - else if(pDM_Odm->SupportICType == ODM_RTL8812) - { - ODM_SetMACReg(pDM_Odm, 0x9b0 , BIT31, 1); //0x9b0[31]=1 + + } else if (CSI_en == CSI_OFF) { + if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + odm_set_mac_reg(p_dm_odm, 0xd84, BIT(11), 0); /* 0xd84[11]=0 */ + } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { + odm_set_mac_reg(p_dm_odm, 0x9b0, BIT(31), 0); /* 0x9b0[31]=0 */ } - } - else if(CSI_en==CSI_OFF) - { - if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - ODM_SetMACReg(pDM_Odm, 0xd84 , BIT11, 0); //0xd84[11]=0 - } - else if(pDM_Odm->SupportICType == ODM_RTL8812) - { - ODM_SetMACReg(pDM_Odm, 0x9b0 , BIT31, 0); //0x9b0[31]=0 - } - } } -VOID -odm_BDCcoexType_withBferClient( - IN PVOID pDM_VOID, - IN u1Byte swch - ) +void +odm_bd_ccoex_type_with_bfer_client( + void *p_dm_void, + u8 swch +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; - u1Byte BDCcoexType_wBfer; - - if(swch==DIVON_CSIOFF) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 1] {DIV,CSI} ={1,0} \n")); - BDCcoexType_wBfer=1; - - if(BDCcoexType_wBfer != pDM_BdcTable->BDCcoexType_wBfer) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); - odm_CSI_on_off(pDM_Odm,CSI_OFF); - pDM_BdcTable->BDCcoexType_wBfer=1; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; + u8 bd_ccoex_type_wbfer; + + if (swch == DIVON_CSIOFF) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 1] {DIV,CSI} ={1,0}\n")); + bd_ccoex_type_wbfer = 1; + + if (bd_ccoex_type_wbfer != p_dm_bdc_table->bd_ccoex_type_wbfer) { + odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); + odm_CSI_on_off(p_dm_odm, CSI_OFF); + p_dm_bdc_table->bd_ccoex_type_wbfer = 1; } - } - else if(swch==DIVOFF_CSION) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 2] {DIV,CSI} ={0,1}\n")); - BDCcoexType_wBfer=2; - - if(BDCcoexType_wBfer != pDM_BdcTable->BDCcoexType_wBfer) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - odm_CSI_on_off(pDM_Odm,CSI_ON); - pDM_BdcTable->BDCcoexType_wBfer=2; + } else if (swch == DIVOFF_CSION) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 2] {DIV,CSI} ={0,1}\n")); + bd_ccoex_type_wbfer = 2; + + if (bd_ccoex_type_wbfer != p_dm_bdc_table->bd_ccoex_type_wbfer) { + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + odm_CSI_on_off(p_dm_odm, CSI_ON); + p_dm_bdc_table->bd_ccoex_type_wbfer = 2; } } } -VOID -odm_BF_AntDiv_ModeArbitration( - IN PVOID pDM_VOID - ) +void +odm_bf_ant_div_mode_arbitration( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; - u1Byte current_BDC_Mode; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; + u8 current_bdc_mode; - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n")); - - //2 Mode 1 - if((pDM_BdcTable->num_Txbfee_Client !=0) && (pDM_BdcTable->num_Txbfer_Client == 0)) - { - current_BDC_Mode=BDC_MODE_1; - - if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) - { - pDM_BdcTable->BDC_Mode=BDC_MODE_1; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - pDM_BdcTable->BDC_RxIdleUpdate_counter=1; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode1 ))\n")); - } +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode1 ))\n")); - } - //2 Mode 2 - else if((pDM_BdcTable->num_Txbfee_Client ==0) && (pDM_BdcTable->num_Txbfer_Client != 0)) - { - current_BDC_Mode=BDC_MODE_2; - - if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) - { - pDM_BdcTable->BDC_Mode=BDC_MODE_2; - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - pDM_BdcTable->BDC_Try_flag=0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode2 ))\n")); - - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode2 ))\n")); + /* 2 mode 1 */ + if ((p_dm_bdc_table->num_txbfee_client != 0) && (p_dm_bdc_table->num_txbfer_client == 0)) { + current_bdc_mode = BDC_MODE_1; + + if (current_bdc_mode != p_dm_bdc_table->bdc_mode) { + p_dm_bdc_table->bdc_mode = BDC_MODE_1; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + p_dm_bdc_table->bdc_rx_idle_update_counter = 1; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode1 ))\n")); } - //2 Mode 3 - else if((pDM_BdcTable->num_Txbfee_Client !=0) && (pDM_BdcTable->num_Txbfer_Client != 0)) - { - current_BDC_Mode=BDC_MODE_3; - - if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) - { - pDM_BdcTable->BDC_Mode=BDC_MODE_3; - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_RxIdleUpdate_counter=1; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode3 ))\n")); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode3 ))\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance mode] : (( Mode1 ))\n")); + } + /* 2 mode 2 */ + else if ((p_dm_bdc_table->num_txbfee_client == 0) && (p_dm_bdc_table->num_txbfer_client != 0)) { + current_bdc_mode = BDC_MODE_2; + + if (current_bdc_mode != p_dm_bdc_table->bdc_mode) { + p_dm_bdc_table->bdc_mode = BDC_MODE_2; + p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + p_dm_bdc_table->bdc_try_flag = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode2 ))\n")); + + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance mode] : (( Mode2 ))\n")); + } + /* 2 mode 3 */ + else if ((p_dm_bdc_table->num_txbfee_client != 0) && (p_dm_bdc_table->num_txbfer_client != 0)) { + current_bdc_mode = BDC_MODE_3; + + if (current_bdc_mode != p_dm_bdc_table->bdc_mode) { + p_dm_bdc_table->bdc_mode = BDC_MODE_3; + p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + p_dm_bdc_table->bdc_try_flag = 0; + p_dm_bdc_table->bdc_rx_idle_update_counter = 1; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode3 ))\n")); } - //2 Mode 4 - else if((pDM_BdcTable->num_Txbfee_Client ==0) && (pDM_BdcTable->num_Txbfer_Client == 0)) - { - current_BDC_Mode=BDC_MODE_4; - - if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) - { - pDM_BdcTable->BDC_Mode=BDC_MODE_4; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode4 ))\n")); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode4 ))\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance mode] : (( Mode3 ))\n")); + } + /* 2 mode 4 */ + else if ((p_dm_bdc_table->num_txbfee_client == 0) && (p_dm_bdc_table->num_txbfer_client == 0)) { + current_bdc_mode = BDC_MODE_4; + + if (current_bdc_mode != p_dm_bdc_table->bdc_mode) { + p_dm_bdc_table->bdc_mode = BDC_MODE_4; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode4 ))\n")); } - #endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance mode] : (( Mode4 ))\n")); + } +#endif } -VOID -odm_DivTrainState_setting( - IN PVOID pDM_VOID - ) +void +odm_div_train_state_setting( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pBDC_T pDM_BdcTable=&pDM_Odm->DM_BdcTable; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE] \n")); - pDM_BdcTable->BDC_Try_counter =2; - pDM_BdcTable->BDC_Try_flag=1; - pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE]\n")); + p_dm_bdc_table->bdc_try_counter = 2; + p_dm_bdc_table->bdc_try_flag = 1; + p_dm_bdc_table->BDC_state = bdc_bfer_train_state; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); } -VOID -odm_BDCcoex_BFeeRxDiv_Arbitration( - IN PVOID pDM_VOID +void +odm_bd_ccoex_bfee_rx_div_arbitration( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; - BOOLEAN StopBF_flag; - u1Byte BDC_active_Mode; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; + boolean stop_bf_flag; + u8 bdc_active_mode; - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BFee, num_BFer , num_Client} = (( %d , %d , %d)) \n",pDM_BdcTable->num_Txbfee_Client,pDM_BdcTable->num_Txbfer_Client,pDM_BdcTable->num_Client)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BF_tars, num_DIV_tars } = (( %d , %d )) \n",pDM_BdcTable->num_BfTar , pDM_BdcTable->num_DivTar )); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BFee, num_BFer, num_client} = (( %d , %d , %d))\n", p_dm_bdc_table->num_txbfee_client, p_dm_bdc_table->num_txbfer_client, p_dm_bdc_table->num_client)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BF_tars, num_DIV_tars } = (( %d , %d ))\n", p_dm_bdc_table->num_bf_tar, p_dm_bdc_table->num_div_tar)); - //2 [ MIB control ] - if (pDM_Odm->bdc_holdstate==2) - { - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ BF STATE] \n")); - return; - } - else if (pDM_Odm->bdc_holdstate==1) - { - pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE] \n")); - return; - } + /* 2 [ MIB control ] */ + if (p_dm_odm->bdc_holdstate == 2) { + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); + p_dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ BF STATE]\n")); + return; + } else if (p_dm_odm->bdc_holdstate == 1) { + p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE]\n")); + return; + } - //------------------------------------------------------------ + /* ------------------------------------------------------------ */ - - //2 Mode 2 & 3 - if(pDM_BdcTable->BDC_Mode==BDC_MODE_2 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n{ Try_flag , Try_counter } = { %d , %d } \n",pDM_BdcTable->BDC_Try_flag,pDM_BdcTable->BDC_Try_counter)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDCcoexType = (( %d )) \n\n", pDM_BdcTable->BDCcoexType_wBfer)); - - // All Client have Bfer-Cap------------------------------- - if(pDM_BdcTable->num_Txbfer_Client == pDM_BdcTable->num_Client) //BFer STA Only?: yes - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( Yes ))\n")); - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - return; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( No ))\n")); - } - // - if(pDM_BdcTable->bAll_BFSta_Idle==FALSE && pDM_BdcTable->bAll_DivSta_Idle==TRUE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All DIV-STA are idle, but BF-STA not\n")); - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - return; + /* 2 mode 2 & 3 */ + if (p_dm_bdc_table->bdc_mode == BDC_MODE_2 || p_dm_bdc_table->bdc_mode == BDC_MODE_3) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n{ Try_flag, Try_counter } = { %d , %d }\n", p_dm_bdc_table->bdc_try_flag, p_dm_bdc_table->bdc_try_counter)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDCcoexType = (( %d )) \n\n", p_dm_bdc_table->bd_ccoex_type_wbfer)); + + /* All Client have Bfer-Cap------------------------------- */ + if (p_dm_bdc_table->num_txbfer_client == p_dm_bdc_table->num_client) { /* BFer STA Only?: yes */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( Yes ))\n")); + p_dm_bdc_table->bdc_try_flag = 0; + p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); + return; + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( No ))\n")); + /* */ + if (p_dm_bdc_table->is_all_bf_sta_idle == false && p_dm_bdc_table->is_all_div_sta_idle == true) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All DIV-STA are idle, but BF-STA not\n")); + p_dm_bdc_table->bdc_try_flag = 0; + p_dm_bdc_table->BDC_state = bdc_bfer_train_state; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); + return; + } else if (p_dm_bdc_table->is_all_bf_sta_idle == true && p_dm_bdc_table->is_all_div_sta_idle == false) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All BF-STA are idle, but DIV-STA not\n")); + p_dm_bdc_table->bdc_try_flag = 0; + p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + return; + } + + /* Select active mode-------------------------------------- */ + if (p_dm_bdc_table->num_bf_tar == 0) { /* Selsect_1, Selsect_2 */ + if (p_dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 1 ))\n")); + p_dm_bdc_table->bdc_active_mode = 1; + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 2 ))\n")); + p_dm_bdc_table->bdc_active_mode = 2; } - else if(pDM_BdcTable->bAll_BFSta_Idle==TRUE && pDM_BdcTable->bAll_DivSta_Idle==FALSE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All BF-STA are idle, but DIV-STA not\n")); - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + p_dm_bdc_table->bdc_try_flag = 0; + p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + return; + } else { /* num_bf_tar > 0 */ + if (p_dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 3 ))\n")); + p_dm_bdc_table->bdc_active_mode = 3; + p_dm_bdc_table->bdc_try_flag = 0; + p_dm_bdc_table->BDC_state = bdc_bfer_train_state; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); return; - } + } else { /* Selsect_4 */ + bdc_active_mode = 4; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 4 ))\n")); - //Select active mode-------------------------------------- - if(pDM_BdcTable->num_BfTar ==0) // Selsect_1, Selsect_2 - { - if(pDM_BdcTable->num_DivTar ==0) // Selsect_3 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 1 )) \n")); - pDM_BdcTable->BDC_active_Mode=1; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 2 ))\n")); - pDM_BdcTable->BDC_active_Mode=2; - } - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - return; - } - else // num_BfTar > 0 - { - if(pDM_BdcTable->num_DivTar ==0) // Selsect_3 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 3 ))\n")); - pDM_BdcTable->BDC_active_Mode=3; - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + if (bdc_active_mode != p_dm_bdc_table->bdc_active_mode) { + p_dm_bdc_table->bdc_active_mode = 4; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to active mode (( 4 )) & return!!!\n")); return; } - else // Selsect_4 - { - BDC_active_Mode=4; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 4 ))\n")); - - if(BDC_active_Mode!=pDM_BdcTable->BDC_active_Mode) - { - pDM_BdcTable->BDC_active_Mode=4; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to active mode (( 4 )) & return!!! \n")); - return; - } - } } + } #if 1 - if (pDM_Odm->bdc_holdstate==0xff) - { - pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE] \n")); + if (p_dm_odm->bdc_holdstate == 0xff) { + p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE]\n")); return; } #endif - // Does Client number changed ? ------------------------------- - if(pDM_BdcTable->num_Client !=pDM_BdcTable->pre_num_Client) - { - pDM_BdcTable->BDC_Try_flag=0; - pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE )) \n")); + /* Does Client number changed ? ------------------------------- */ + if (p_dm_bdc_table->num_client != p_dm_bdc_table->pre_num_client) { + p_dm_bdc_table->bdc_try_flag = 0; + p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE ))\n")); + } + p_dm_bdc_table->pre_num_client = p_dm_bdc_table->num_client; + + if (p_dm_bdc_table->bdc_try_flag == 0) { + /* 2 DIV_TRAIN_STATE (mode 2-0) */ + if (p_dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE) + odm_div_train_state_setting(p_dm_odm); + /* 2 BFer_TRAIN_STATE (mode 2-1) */ + else if (p_dm_bdc_table->BDC_state == bdc_bfer_train_state) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-1. BFer_TRAIN_STATE ]*****\n")); + + /* if(p_dm_bdc_table->num_bf_tar==0) */ + /* { */ + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n")); */ + /* odm_div_train_state_setting( p_dm_odm); */ + /* } */ + /* else */ /* num_bf_tar != 0 */ + /* { */ + p_dm_bdc_table->bdc_try_counter = 2; + p_dm_bdc_table->bdc_try_flag = 1; + p_dm_bdc_table->BDC_state = BDC_DECISION_STATE; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n")); + /* } */ } - pDM_BdcTable->pre_num_Client=pDM_BdcTable->num_Client; - - if( pDM_BdcTable->BDC_Try_flag==0) - { - //2 DIV_TRAIN_STATE (Mode 2-0) - if(pDM_BdcTable->BDC_state==BDC_DIV_TRAIN_STATE) - { - odm_DivTrainState_setting( pDM_Odm); - } - //2 BFer_TRAIN_STATE (Mode 2-1) - else if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-1. BFer_TRAIN_STATE ]***** \n")); - - //if(pDM_BdcTable->num_BfTar==0) - //{ - // ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BFer_TRAIN_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); - // odm_DivTrainState_setting( pDM_Odm); - //} - //else //num_BfTar != 0 - //{ - pDM_BdcTable->BDC_Try_counter=2; - pDM_BdcTable->BDC_Try_flag=1; - pDM_BdcTable->BDC_state=BDC_DECISION_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), [ BDC_BFer_TRAIN_STATE ] >> [BDC_DECISION_STATE] \n")); - //} + /* 2 DECISION_STATE (mode 2-2) */ + else if (p_dm_bdc_table->BDC_state == BDC_DECISION_STATE) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-2. DECISION_STATE]*****\n")); + /* if(p_dm_bdc_table->num_bf_tar==0) */ + /* { */ + /* ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */ + /* odm_div_train_state_setting( p_dm_odm); */ + /* } */ + /* else */ /* num_bf_tar != 0 */ + /* { */ + if (p_dm_bdc_table->BF_pass == false || p_dm_bdc_table->DIV_pass == false) + stop_bf_flag = true; + else + stop_bf_flag = false; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, stop_bf_flag } = { %d, %d, %d }\n", p_dm_bdc_table->BF_pass, p_dm_bdc_table->DIV_pass, stop_bf_flag)); + + if (stop_bf_flag == true) { /* DIV_en */ + p_dm_bdc_table->bdc_hold_counter = 10; /* 20 */ + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ stop_bf_flag= ((true)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n")); + } else { /* BF_en */ + p_dm_bdc_table->bdc_hold_counter = 10; /* 20 */ + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); + p_dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[stop_bf_flag= ((false)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n")); } - //2 DECISION_STATE (Mode 2-2) - else if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-2. DECISION_STATE]***** \n")); - //if(pDM_BdcTable->num_BfTar==0) - //{ - // ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); - // odm_DivTrainState_setting( pDM_Odm); - //} - //else //num_BfTar != 0 - //{ - if(pDM_BdcTable->BF_pass==FALSE || pDM_BdcTable->DIV_pass == FALSE) - StopBF_flag=TRUE; - else - StopBF_flag=FALSE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, StopBF_flag } = { %d, %d, %d } \n" ,pDM_BdcTable->BF_pass,pDM_BdcTable->DIV_pass,StopBF_flag)); - - if(StopBF_flag==TRUE) //DIV_en - { - pDM_BdcTable->BDC_Hold_counter=10; //20 - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ StopBF_flag= ((TRUE)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE] \n")); - } - else //BF_en - { - pDM_BdcTable->BDC_Hold_counter=10; //20 - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[StopBF_flag= ((FALSE)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE] \n")); - } - //} + /* } */ + } + /* 2 BF-HOLD_STATE (mode 2-3) */ + else if (p_dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-3. BF_HOLD_STATE ]*****\n")); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bdc_hold_counter = (( %d ))\n", p_dm_bdc_table->bdc_hold_counter)); + + if (p_dm_bdc_table->bdc_hold_counter == 1) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); + odm_div_train_state_setting(p_dm_odm); + } else { + p_dm_bdc_table->bdc_hold_counter--; + + /* if(p_dm_bdc_table->num_bf_tar==0) */ + /* { */ + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */ + /* odm_div_train_state_setting( p_dm_odm); */ + /* } */ + /* else */ /* num_bf_tar != 0 */ + /* { */ + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes ))\n")); */ + p_dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n")); + /* } */ } - //2 BF-HOLD_STATE (Mode 2-3) - else if(pDM_BdcTable->BDC_state==BDC_BF_HOLD_STATE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-3. BF_HOLD_STATE ]*****\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDC_Hold_counter = (( %d )) \n",pDM_BdcTable->BDC_Hold_counter )); + } + /* 2 DIV-HOLD_STATE (mode 2-4) */ + else if (p_dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-4. DIV_HOLD_STATE ]*****\n")); - if(pDM_BdcTable->BDC_Hold_counter==1) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); - odm_DivTrainState_setting( pDM_Odm); - } - else - { - pDM_BdcTable->BDC_Hold_counter--; - - //if(pDM_BdcTable->num_BfTar==0) - //{ - // ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); - // odm_DivTrainState_setting( pDM_Odm); - //} - //else //num_BfTar != 0 - //{ - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes ))\n")); - pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE] \n")); - //} - } - + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bdc_hold_counter = (( %d ))\n", p_dm_bdc_table->bdc_hold_counter)); + + if (p_dm_bdc_table->bdc_hold_counter == 1) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); + odm_div_train_state_setting(p_dm_odm); + } else { + p_dm_bdc_table->bdc_hold_counter--; + p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n")); } - //2 DIV-HOLD_STATE (Mode 2-4) - else if(pDM_BdcTable->BDC_state==BDC_DIV_HOLD_STATE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-4. DIV_HOLD_STATE ]*****\n")); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDC_Hold_counter = (( %d )) \n",pDM_BdcTable->BDC_Hold_counter )); - - if(pDM_BdcTable->BDC_Hold_counter==1) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); - odm_DivTrainState_setting( pDM_Odm); - } - else - { - pDM_BdcTable->BDC_Hold_counter--; - pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; - odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE] \n")); - } - - } - + } - else if( pDM_BdcTable->BDC_Try_flag==1) - { - //2 Set Training Counter - if(pDM_BdcTable->BDC_Try_counter >1) - { - pDM_BdcTable->BDC_Try_counter--; - if(pDM_BdcTable->BDC_Try_counter ==1) - pDM_BdcTable->BDC_Try_flag=0; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training !!\n")); - //return ; - } - + + } else if (p_dm_bdc_table->bdc_try_flag == 1) { + /* 2 Set Training counter */ + if (p_dm_bdc_table->bdc_try_counter > 1) { + p_dm_bdc_table->bdc_try_counter--; + if (p_dm_bdc_table->bdc_try_counter == 1) + p_dm_bdc_table->bdc_try_flag = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training !!\n")); + /* return ; */ } - + } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[end]\n")); + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[end]\n")); + +#endif /* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ - #endif //#if(DM_ODM_SUPPORT_TYPE == ODM_AP) - } #endif -#endif //#ifdef BEAMFORMING_SUPPORT +#endif /* #ifdef BEAMFORMING_SUPPORT */ #if (RTL8188E_SUPPORT == 1) -VOID -odm_RX_HWAntDiv_Init_88E( - IN PVOID pDM_VOID +void +odm_rx_hw_ant_div_init_88e( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 value32; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - if(pDM_Odm->mp_mode == TRUE) - { - ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS - return; +#if 0 + if (*(p_dm_odm->p_mp_mode) == true) { + odm_set_bb_reg(p_dm_odm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */ + odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* 1:CG, 0:CS */ + return; } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n")); - - //MAC Setting - value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); - ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output - //Pin Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only - //OFDM Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); - //CCK Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples - - ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0001); //antenna mapping table +#endif - pDM_FatTable->enable_ctrl_frame_antdiv = 1; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n")); + + /* MAC setting */ + value32 = odm_get_mac_reg(p_dm_odm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD); + odm_set_mac_reg(p_dm_odm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + /* Pin Settings */ + odm_set_bb_reg(p_dm_odm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT8, 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ + odm_set_bb_reg(p_dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ + odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ + odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */ + /* OFDM Settings */ + odm_set_bb_reg(p_dm_odm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); + /* CCK Settings */ + odm_set_bb_reg(p_dm_odm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + + odm_set_bb_reg(p_dm_odm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001); /* antenna mapping table */ + + p_dm_fat_table->enable_ctrl_frame_antdiv = 1; } -VOID -odm_TRX_HWAntDiv_Init_88E( - IN PVOID pDM_VOID +void +odm_trx_hw_ant_div_init_88e( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - if(pDM_Odm->mp_mode == TRUE) - { - ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1) - return; - } + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 value32; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV (SPDT)]\n")); - - //MAC Setting - value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); - ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output - //Pin Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only - //OFDM Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); - //CCK Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples - - //antenna mapping table - if(!pDM_Odm->bIsMPChip) //testchip - { - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 +#if 0 + if (*(p_dm_odm->p_mp_mode) == true) { + odm_set_bb_reg(p_dm_odm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */ + odm_set_bb_reg(p_dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT4 | BIT3, 0); /* Default RX (0/1) */ + return; } - else //MPchip - ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/ +#endif - pDM_FatTable->enable_ctrl_frame_antdiv = 1; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV (SPDT)]\n")); + + /* MAC setting */ + value32 = odm_get_mac_reg(p_dm_odm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD); + odm_set_mac_reg(p_dm_odm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + /* Pin Settings */ + odm_set_bb_reg(p_dm_odm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT8, 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ + odm_set_bb_reg(p_dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ + odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ + odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */ + /* OFDM Settings */ + odm_set_bb_reg(p_dm_odm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); + /* CCK Settings */ + odm_set_bb_reg(p_dm_odm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + + /* antenna mapping table */ + if (!p_dm_odm->is_mp_chip) { /* testchip */ + odm_set_bb_reg(p_dm_odm, ODM_REG_RX_DEFUALT_A_11N, BIT(10) | BIT9 | BIT8, 1); /* Reg858[10:8]=3'b001 */ + odm_set_bb_reg(p_dm_odm, ODM_REG_RX_DEFUALT_A_11N, BIT(13) | BIT12 | BIT11, 2); /* Reg858[13:11]=3'b010 */ + } else /* MPchip */ + odm_set_bb_reg(p_dm_odm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/ + + p_dm_fat_table->enable_ctrl_frame_antdiv = 1; } -#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) -VOID -odm_Smart_HWAntDiv_Init_88E( - IN PVOID pDM_VOID +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) +void +odm_smart_hw_ant_div_init_88e( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32, i; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 value32, i; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n")); - - if(pDM_Odm->mp_mode == TRUE) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n")); + +#if 0 + if (*(p_dm_odm->p_mp_mode) == true) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("p_dm_odm->ant_div_type: %d\n", p_dm_odm->ant_div_type)); return; } +#endif - pDM_FatTable->TrainIdx = 0; - pDM_FatTable->FAT_State = FAT_PREPARE_STATE; - - pDM_Odm->fat_comb_a=5; - pDM_Odm->antdiv_intvl = 0x64; // 100ms + p_dm_fat_table->train_idx = 0; + p_dm_fat_table->fat_state = FAT_PREPARE_STATE; - for(i=0; i<6; i++) - { - pDM_FatTable->Bssid[i] = 0; - } - for(i=0; i< (pDM_Odm->fat_comb_a) ; i++) - { - pDM_FatTable->antSumRSSI[i] = 0; - pDM_FatTable->antRSSIcnt[i] = 0; - pDM_FatTable->antAveRSSI[i] = 0; - } + p_dm_odm->fat_comb_a = 5; + p_dm_odm->antdiv_intvl = 0x64; /* 100ms */ - //MAC Setting - value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord); - ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output - value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord); - ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match - //value32 = PlatformEFIORead4Byte(Adapter, 0x7B4); - //PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet - - //Match MAC ADDR - ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0); - ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0); - - ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW - ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW - ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch - ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 0); //Regb2c[31]=1'b1 //output at CS only - ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0); - - //antenna mapping table - if(pDM_Odm->fat_comb_a == 2) - { - if(!pDM_Odm->bIsMPChip) //testchip - { - ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 - ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 - } - else //MPchip - { - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1); - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); - } + for (i = 0; i < 6; i++) + p_dm_fat_table->bssid[i] = 0; + for (i = 0; i < (p_dm_odm->fat_comb_a) ; i++) { + p_dm_fat_table->ant_sum_rssi[i] = 0; + p_dm_fat_table->ant_rssi_cnt[i] = 0; + p_dm_fat_table->ant_ave_rssi[i] = 0; } - else - { - if(!pDM_Odm->bIsMPChip) //testchip - { - ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000 - ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0); - ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111 + + /* MAC setting */ + value32 = odm_get_mac_reg(p_dm_odm, 0x4c, MASKDWORD); + odm_set_mac_reg(p_dm_odm, 0x4c, MASKDWORD, value32 | (BIT(23) | BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + value32 = odm_get_mac_reg(p_dm_odm, 0x7B4, MASKDWORD); + odm_set_mac_reg(p_dm_odm, 0x7b4, MASKDWORD, value32 | (BIT(16) | BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */ + /* value32 = platform_efio_read_4byte(adapter, 0x7B4); */ + /* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18)); */ /* append MACID in reponse packet */ + + /* Match MAC ADDR */ + odm_set_mac_reg(p_dm_odm, 0x7b4, 0xFFFF, 0); + odm_set_mac_reg(p_dm_odm, 0x7b0, MASKDWORD, 0); + + odm_set_bb_reg(p_dm_odm, 0x870, BIT(9) | BIT8, 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ + odm_set_bb_reg(p_dm_odm, 0x864, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ + odm_set_bb_reg(p_dm_odm, 0xb2c, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ + odm_set_bb_reg(p_dm_odm, 0xb2c, BIT(31), 0); /* regb2c[31]=1'b1 */ /* output at CS only */ + odm_set_bb_reg(p_dm_odm, 0xca4, MASKDWORD, 0x000000a0); + + /* antenna mapping table */ + if (p_dm_odm->fat_comb_a == 2) { + if (!p_dm_odm->is_mp_chip) { /* testchip */ + odm_set_bb_reg(p_dm_odm, 0x858, BIT(10) | BIT9 | BIT8, 1); /* Reg858[10:8]=3'b001 */ + odm_set_bb_reg(p_dm_odm, 0x858, BIT(13) | BIT12 | BIT11, 2); /* Reg858[13:11]=3'b010 */ + } else { /* MPchip */ + odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 1); + odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 2); } - else //MPchip - { - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 4); // 0: 3b'000 - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); // 1: 3b'001 - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 0); // 2: 3b'010 - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 1); // 3: 3b'011 - ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 3); // 4: 3b'100 - ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5); // 5: 3b'101 - ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6); // 6: 3b'110 - ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 255); // 7: 3b'111 + } else { + if (!p_dm_odm->is_mp_chip) { /* testchip */ + odm_set_bb_reg(p_dm_odm, 0x858, BIT(10) | BIT9 | BIT8, 0); /* Reg858[10:8]=3'b000 */ + odm_set_bb_reg(p_dm_odm, 0x858, BIT(13) | BIT12 | BIT11, 1); /* Reg858[13:11]=3'b001 */ + odm_set_bb_reg(p_dm_odm, 0x878, BIT(16), 0); + odm_set_bb_reg(p_dm_odm, 0x858, BIT(15) | BIT14, 2); /* (Reg878[0],Reg858[14:15])=3'b010 */ + odm_set_bb_reg(p_dm_odm, 0x878, BIT(19) | BIT18 | BIT17, 3); /* Reg878[3:1]=3b'011 */ + odm_set_bb_reg(p_dm_odm, 0x878, BIT(22) | BIT21 | BIT20, 4); /* Reg878[6:4]=3b'100 */ + odm_set_bb_reg(p_dm_odm, 0x878, BIT(25) | BIT24 | BIT23, 5); /* Reg878[9:7]=3b'101 */ + odm_set_bb_reg(p_dm_odm, 0x878, BIT(28) | BIT27 | BIT26, 6); /* Reg878[12:10]=3b'110 */ + odm_set_bb_reg(p_dm_odm, 0x878, BIT(31) | BIT30 | BIT29, 7); /* Reg878[15:13]=3b'111 */ + } else { /* MPchip */ + odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 4); /* 0: 3b'000 */ + odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 2); /* 1: 3b'001 */ + odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE2, 0); /* 2: 3b'010 */ + odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE3, 1); /* 3: 3b'011 */ + odm_set_bb_reg(p_dm_odm, 0x918, MASKBYTE0, 3); /* 4: 3b'100 */ + odm_set_bb_reg(p_dm_odm, 0x918, MASKBYTE1, 5); /* 5: 3b'101 */ + odm_set_bb_reg(p_dm_odm, 0x918, MASKBYTE2, 6); /* 6: 3b'110 */ + odm_set_bb_reg(p_dm_odm, 0x918, MASKBYTE3, 255); /* 7: 3b'111 */ } } - //Default Ant Setting when no fast training - ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX - ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 0);//Default TX - - //Enter Traing state - ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (pDM_Odm->fat_comb_a-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1 - - //SW Control - //PHY_SetBBReg(Adapter, 0x864 , BIT10, 1); - //PHY_SetBBReg(Adapter, 0x870 , BIT9, 1); - //PHY_SetBBReg(Adapter, 0x870 , BIT8, 1); - //PHY_SetBBReg(Adapter, 0x864 , BIT11, 1); - //PHY_SetBBReg(Adapter, 0x860 , BIT9, 0); - //PHY_SetBBReg(Adapter, 0x860 , BIT8, 0); + /* Default ant setting when no fast training */ + odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT4 | BIT3, 0); /* Default RX */ + odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT7 | BIT6, 1); /* Optional RX */ + odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, 0); /* Default TX */ + + /* Enter Traing state */ + odm_set_bb_reg(p_dm_odm, 0x864, BIT(2) | BIT1 | BIT0, (p_dm_odm->fat_comb_a - 1)); /* reg864[2:0]=3'd6 */ /* ant combination=reg864[2:0]+1 */ + + /* SW Control */ + /* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */ + /* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */ + /* phy_set_bb_reg(adapter, 0x870, BIT8, 1); */ + /* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */ + /* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */ + /* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */ } #endif -#endif //#if (RTL8188E_SUPPORT == 1) +#endif /* #if (RTL8188E_SUPPORT == 1) */ #if (RTL8192E_SUPPORT == 1) -VOID -odm_RX_HWAntDiv_Init_92E( - IN PVOID pDM_VOID +void +odm_rx_hw_ant_div_init_92e( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - if(pDM_Odm->mp_mode == TRUE) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9] - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + +#if 0 + if (*(p_dm_odm->p_mp_mode) == true) { + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + odm_set_bb_reg(p_dm_odm, 0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ + odm_set_bb_reg(p_dm_odm, 0xc50, BIT(9), 1); /* 1:CG, 0:CS */ return; } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n")); - - //Pin Settings - ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0);//Reg870[8]=1'b0, // "antsel" is controled by HWs - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 1); //Regc50[8]=1'b1 //" CS/CG switching" is controled by HWs - - //Mapping table - ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table - - //OFDM Settings - ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias - - //CCK Settings - ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2 - ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 - ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue - ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples - - #ifdef ODM_EVM_ENHANCE_ANTDIV - //EVM enhance AntDiv method init---------------------------------------------------------------------- - pDM_FatTable->EVM_method_enable=0; - pDM_FatTable->FAT_State = NORMAL_STATE_MIAN; - pDM_Odm->antdiv_intvl = 0x64; - ODM_SetBBReg(pDM_Odm, 0x910 , 0x3f, 0xf ); - pDM_Odm->antdiv_evm_en=1; - //pDM_Odm->antdiv_period=1; - pDM_Odm->evm_antdiv_period = 3; +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n")); + + /* Pin Settings */ + odm_set_bb_reg(p_dm_odm, 0x870, BIT(8), 0);/* reg870[8]=1'b0, */ /* "antsel" is controled by HWs */ + odm_set_bb_reg(p_dm_odm, 0xc50, BIT(8), 1); /* regc50[8]=1'b1 */ /* " CS/CG switching" is controled by HWs */ + + /* Mapping table */ + odm_set_bb_reg(p_dm_odm, 0x914, 0xFFFF, 0x0100); /* antenna mapping table */ + + /* OFDM Settings */ + odm_set_bb_reg(p_dm_odm, 0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(p_dm_odm, 0xca4, 0x7FF000, 0x0); /* bias */ + + /* CCK Settings */ + odm_set_bb_reg(p_dm_odm, 0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(p_dm_odm, 0xb34, BIT(30), 0); /* (92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(p_dm_odm, 0xa74, BIT(7), 1); /* Fix CCK PHY status report issue */ + odm_set_bb_reg(p_dm_odm, 0xa0c, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(p_dm_odm); +#endif - #endif - } -VOID -odm_TRX_HWAntDiv_Init_92E( - IN PVOID pDM_VOID +void +odm_trx_hw_ant_div_init_92e( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - if(pDM_Odm->mp_mode == TRUE) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9] - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + +#if 0 + if (*(p_dm_odm->p_mp_mode) == true) { + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + odm_set_bb_reg(p_dm_odm, 0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ + odm_set_bb_reg(p_dm_odm, 0xc50, BIT(9), 1); /* 1:CG, 0:CS */ return; } +#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n")); - - //3 --RFE pin setting--------- - //[MAC] - ODM_SetMACReg(pDM_Odm, 0x38, BIT11, 1); //DBG PAD Driving control (GPIO 8) - ODM_SetMACReg(pDM_Odm, 0x4c, BIT23, 0); //path-A , RFE_CTRL_3 - ODM_SetMACReg(pDM_Odm, 0x4c, BIT29, 1); //path-A , RFE_CTRL_8 - //[BB] - ODM_SetBBReg(pDM_Odm, 0x944 , BIT3, 1); //RFE_buffer - ODM_SetBBReg(pDM_Odm, 0x944 , BIT8, 1); - ODM_SetBBReg(pDM_Odm, 0x940 , BIT7|BIT6, 0x0); // r_rfe_path_sel_ (RFE_CTRL_3) - ODM_SetBBReg(pDM_Odm, 0x940 , BIT17|BIT16, 0x0); // r_rfe_path_sel_ (RFE_CTRL_8) - ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); //RFE_buffer - ODM_SetBBReg(pDM_Odm, 0x92C , BIT3, 0); //rfe_inv (RFE_CTRL_3) - ODM_SetBBReg(pDM_Odm, 0x92C , BIT8, 1); //rfe_inv (RFE_CTRL_8) - ODM_SetBBReg(pDM_Odm, 0x930 , 0xF000, 0x8); //path-A , RFE_CTRL_3 - ODM_SetBBReg(pDM_Odm, 0x934 , 0xF, 0x8); //path-A , RFE_CTRL_8 - //3 ------------------------- - - //Pin Settings - ODM_SetBBReg(pDM_Odm, 0xC50 , BIT8, 0); //path-A //disable CS/CG switch + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => ant_div_type=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n")); + + /* 3 --RFE pin setting--------- */ + /* [MAC] */ + odm_set_mac_reg(p_dm_odm, 0x38, BIT(11), 1); /* DBG PAD Driving control (GPIO 8) */ + odm_set_mac_reg(p_dm_odm, 0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */ + odm_set_mac_reg(p_dm_odm, 0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */ + /* [BB] */ + odm_set_bb_reg(p_dm_odm, 0x944, BIT(3), 1); /* RFE_buffer */ + odm_set_bb_reg(p_dm_odm, 0x944, BIT(8), 1); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(7) | BIT6, 0x0); /* r_rfe_path_sel_ (RFE_CTRL_3) */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(17) | BIT16, 0x0); /* r_rfe_path_sel_ (RFE_CTRL_8) */ + odm_set_bb_reg(p_dm_odm, 0x944, BIT(31), 0); /* RFE_buffer */ + odm_set_bb_reg(p_dm_odm, 0x92C, BIT(3), 0); /* rfe_inv (RFE_CTRL_3) */ + odm_set_bb_reg(p_dm_odm, 0x92C, BIT(8), 1); /* rfe_inv (RFE_CTRL_8) */ + odm_set_bb_reg(p_dm_odm, 0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */ + odm_set_bb_reg(p_dm_odm, 0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */ + /* 3 ------------------------- */ + + /* Pin Settings */ + odm_set_bb_reg(p_dm_odm, 0xC50, BIT(8), 0); /* path-A */ /* disable CS/CG switch */ -/* Let it follows PHY_REG for bit9 setting - if(pDM_Odm->priv->pshare->rf_ft_var.use_ext_pa || pDM_Odm->priv->pshare->rf_ft_var.use_ext_lna) - ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 1);//path-A //output at CS +#if 0 + /* Let it follows PHY_REG for bit9 setting */ + if (p_dm_odm->priv->pshare->rf_ft_var.use_ext_pa || p_dm_odm->priv->pshare->rf_ft_var.use_ext_lna) + odm_set_bb_reg(p_dm_odm, 0xC50, BIT(9), 1);/* path-A //output at CS */ else - ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 0); //path-A //output at CG ->normal power -*/ - - ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); //path-A //antsel antselb by HW - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT10, 0); //path-A //antsel2 by HW - - //Mapping table - ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table - - //OFDM Settings - ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias - - //CCK Settings - ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2 - ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 - ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue - ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples - - #ifdef ODM_EVM_ENHANCE_ANTDIV - //EVM enhance AntDiv method init---------------------------------------------------------------------- - pDM_FatTable->EVM_method_enable=0; - pDM_FatTable->FAT_State = NORMAL_STATE_MIAN; - pDM_Odm->antdiv_intvl = 0x64; - ODM_SetBBReg(pDM_Odm, 0x910 , 0x3f, 0xf ); - pDM_Odm->antdiv_evm_en=1; - //pDM_Odm->antdiv_period=1; - pDM_Odm->evm_antdiv_period = 3; - #endif + odm_set_bb_reg(p_dm_odm, 0xC50, BIT(9), 0); /* path-A //output at CG ->normal power */ +#endif + + odm_set_bb_reg(p_dm_odm, 0x870, BIT(9) | BIT8, 0); /* path-A */ /* antsel antselb by HW */ + odm_set_bb_reg(p_dm_odm, 0xB38, BIT(10), 0); /* path-A */ /* antsel2 by HW */ + + /* Mapping table */ + odm_set_bb_reg(p_dm_odm, 0x914, 0xFFFF, 0x0100); /* antenna mapping table */ + + /* OFDM Settings */ + odm_set_bb_reg(p_dm_odm, 0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(p_dm_odm, 0xca4, 0x7FF000, 0x0); /* bias */ + + /* CCK Settings */ + odm_set_bb_reg(p_dm_odm, 0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(p_dm_odm, 0xb34, BIT(30), 0); /* (92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(p_dm_odm, 0xa74, BIT(7), 1); /* Fix CCK PHY status report issue */ + odm_set_bb_reg(p_dm_odm, 0xa0c, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(p_dm_odm); +#endif } -#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) -VOID -odm_Smart_HWAntDiv_Init_92E( - IN PVOID pDM_VOID +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) +void +odm_smart_hw_ant_div_init_92e( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n")); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n")); } #endif -#endif //#if (RTL8192E_SUPPORT == 1) +#endif /* #if (RTL8192E_SUPPORT == 1) */ #if (RTL8723D_SUPPORT == 1) -VOID -odm_TRX_HWAntDiv_Init_8723D( - IN PVOID pDM_VOID +void +odm_trx_hw_ant_div_init_8723d( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723D] AntDiv_Init => AntDivType=[S0S1_HW_TRX_AntDiv]\n")); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723D] AntDiv_Init => ant_div_type=[S0S1_HW_TRX_AntDiv]\n")); /*BT Coexistence*/ /*keep antsel_map when GNT_BT = 1*/ - ODM_SetBBReg(pDM_Odm, 0x864, BIT12, 1); - /* //Disable hw antsw & fast_train.antsw when GNT_BT=1*/ - ODM_SetBBReg(pDM_Odm, 0x874 , BIT23, 0); - /*//Disable hw antsw & fast_train.antsw when BT TX/RX*/ - ODM_SetBBReg(pDM_Odm, 0xE64 , 0xFFFF0000, 0x000c); + odm_set_bb_reg(p_dm_odm, 0x864, BIT(12), 1); + /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + odm_set_bb_reg(p_dm_odm, 0x874, BIT(23), 0); + /* Disable hw antsw & fast_train.antsw when BT TX/RX */ + odm_set_bb_reg(p_dm_odm, 0xE64, 0xFFFF0000, 0x000c); - ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); + odm_set_bb_reg(p_dm_odm, 0x870, BIT(9) | BIT(8), 0); /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/ - /*ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0);*/ - /*ODM_SetBBReg(pDM_Odm, 0x948 , BIT8, 0);*/ + /*odm_set_bb_reg(p_dm_odm, 0x948, BIT6, 0);*/ + /*odm_set_bb_reg(p_dm_odm, 0x948, BIT8, 0);*/ /*GNT_WL tx*/ - ODM_SetBBReg(pDM_Odm, 0x950 , BIT29, 0); - - + odm_set_bb_reg(p_dm_odm, 0x950, BIT(29), 0); + + /*Mapping Table*/ - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 3); - ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); - - /* //Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0]*/ - ODM_SetBBReg(pDM_Odm, 0xCcc, BIT12, 0); - /* //Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable*/ - ODM_SetBBReg(pDM_Odm, 0xCcc , 0x0F, 0x01); - /*//High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable*/ - ODM_SetBBReg(pDM_Odm, 0xCcc , 0xF0, 0x0); - /* //b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK )*/ - ODM_SetBBReg(pDM_Odm, 0xAbc , 0xFF, 0x06); - /* //High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK )*/ - ODM_SetBBReg(pDM_Odm, 0xAbc , 0xFF00, 0x00); - - + odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 0); + odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 3); + /* odm_set_bb_reg(p_dm_odm, 0x864, BIT5|BIT4|BIT3, 0); */ + /* odm_set_bb_reg(p_dm_odm, 0x864, BIT8|BIT7|BIT6, 1); */ + + /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */ + odm_set_bb_reg(p_dm_odm, 0xCcc, BIT(12), 0); + /* Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */ + odm_set_bb_reg(p_dm_odm, 0xCcc, 0x0F, 0x01); + /* High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */ + odm_set_bb_reg(p_dm_odm, 0xCcc, 0xF0, 0x0); + /* b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */ + odm_set_bb_reg(p_dm_odm, 0xAbc, 0xFF, 0x06); + /* High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */ + odm_set_bb_reg(p_dm_odm, 0xAbc, 0xFF00, 0x00); + + /*OFDM HW AntDiv Parameters*/ - ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF, 0xa0); - ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF000, 0x00); - ODM_SetBBReg(pDM_Odm, 0xC5C , BIT20|BIT19|BIT18, 0x04); - + odm_set_bb_reg(p_dm_odm, 0xCA4, 0x7FF, 0xa0); + odm_set_bb_reg(p_dm_odm, 0xCA4, 0x7FF000, 0x00); + odm_set_bb_reg(p_dm_odm, 0xC5C, BIT(20) | BIT(19) | BIT(18), 0x04); + /*CCK HW AntDiv Parameters*/ - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); - ODM_SetBBReg(pDM_Odm, 0xAA8 , BIT8, 0); - - ODM_SetBBReg(pDM_Odm, 0xA0C , 0x0F, 0xf); - ODM_SetBBReg(pDM_Odm, 0xA14 , 0x1F, 0x8); - ODM_SetBBReg(pDM_Odm, 0xA10 , BIT13, 0x1); - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT8, 0x0); - ODM_SetBBReg(pDM_Odm, 0xB34 , BIT30, 0x1); - + odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); + odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); + odm_set_bb_reg(p_dm_odm, 0xAA8, BIT(8), 0); + + odm_set_bb_reg(p_dm_odm, 0xA0C, 0x0F, 0xf); + odm_set_bb_reg(p_dm_odm, 0xA14, 0x1F, 0x8); + odm_set_bb_reg(p_dm_odm, 0xA10, BIT(13), 0x1); + odm_set_bb_reg(p_dm_odm, 0xA74, BIT(8), 0x0); + odm_set_bb_reg(p_dm_odm, 0xB34, BIT(30), 0x1); + /*disable antenna training */ - ODM_SetBBReg(pDM_Odm, 0xE08 , BIT16, 0); - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); + odm_set_bb_reg(p_dm_odm, 0xE08, BIT(16), 0); + odm_set_bb_reg(p_dm_odm, 0xc50, BIT(8), 0); + +} +/*Mingzhi 2017-05-08*/ +void +odm_update_rx_idle_ant_8723d( + void *p_dm_void, + u8 ant, + u32 default_ant, + u32 optional_ant +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + u8 count = 0; + u8 u1_temp; + u8 h2c_parameter; + + +/* odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0x1); */ + odm_set_bb_reg(p_dm_odm, 0x948, BIT(7), default_ant); + odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/ + odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/ + odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*Default TX*/ + p_dm_fat_table->rx_idle_ant = ant; } -VOID +void phydm_set_tx_ant_pwr_8723d( - IN PVOID pDM_VOID, - IN u1Byte Ant + void *p_dm_void, + u8 ant ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + + p_dm_fat_table->rx_idle_ant = ant; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + p_adapter->HalFunc.SetTxPowerLevelHandler(p_adapter, *p_dm_odm->p_channel); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_hal_set_tx_power_level(p_adapter, *p_dm_odm->p_channel); +#endif - pDM_FatTable->RxIdleAnt = Ant; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel); - #elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel); - #endif - } #endif #if (RTL8723B_SUPPORT == 1) -VOID -odm_TRX_HWAntDiv_Init_8723B( - IN PVOID pDM_VOID +void +odm_trx_hw_ant_div_init_8723b( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV(DPDT)]\n")); - - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1); - - //OFDM HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF, 0xa0); //thershold - ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF000, 0x00); //bias - - //CCK HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples - - //BT Coexistence - ODM_SetBBReg(pDM_Odm, 0x864, BIT12, 0); //keep antsel_map when GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x874 , BIT23, 0); //Disable hw antsw & fast_train.antsw when GNT_BT=1 + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n")); - //Output Pin Settings - ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0); // - - ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0); //WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) - ODM_SetBBReg(pDM_Odm, 0x948 , BIT7, 0); - - ODM_SetMACReg(pDM_Odm, 0x40 , BIT3, 1); - ODM_SetMACReg(pDM_Odm, 0x38 , BIT11, 1); - ODM_SetMACReg(pDM_Odm, 0x4C , BIT24|BIT23, 2); //select DPDT_P and DPDT_N as output pin - - ODM_SetBBReg(pDM_Odm, 0x944 , BIT0|BIT1, 3); //in/out - ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); // + /* Mapping Table */ + odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 0); + odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 1); + + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(p_dm_odm, 0xCA4, 0x7FF, 0xa0); /* thershold */ + odm_set_bb_reg(p_dm_odm, 0xCA4, 0x7FF000, 0x00); /* bias */ + + /* CCK HW AntDiv Parameters */ + odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + + /* BT Coexistence */ + odm_set_bb_reg(p_dm_odm, 0x864, BIT(12), 0); /* keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(p_dm_odm, 0x874, BIT(23), 0); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ - ODM_SetBBReg(pDM_Odm, 0x92C , BIT1, 0); //DPDT_P non-inverse - ODM_SetBBReg(pDM_Odm, 0x92C , BIT0, 1); //DPDT_N inverse + /* Output Pin Settings */ + odm_set_bb_reg(p_dm_odm, 0x870, BIT(8), 0); - ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0] + odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0); /* WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) */ + odm_set_bb_reg(p_dm_odm, 0x948, BIT(7), 0); - //2 [--For HW Bug Setting] - if(pDM_Odm->AntType == ODM_AUTO_ANT) - ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable + odm_set_mac_reg(p_dm_odm, 0x40, BIT(3), 1); + odm_set_mac_reg(p_dm_odm, 0x38, BIT(11), 1); + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24) | BIT23, 2); /* select DPDT_P and DPDT_N as output pin */ + + odm_set_bb_reg(p_dm_odm, 0x944, BIT(0) | BIT1, 3); /* in/out */ + odm_set_bb_reg(p_dm_odm, 0x944, BIT(31), 0); + + odm_set_bb_reg(p_dm_odm, 0x92C, BIT(1), 0); /* DPDT_P non-inverse */ + odm_set_bb_reg(p_dm_odm, 0x92C, BIT(0), 1); /* DPDT_N inverse */ + + odm_set_bb_reg(p_dm_odm, 0x930, 0xF0, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(p_dm_odm, 0x930, 0xF, 8); /* DPDT_N = ANTSEL[0] */ + + /* 2 [--For HW Bug setting] */ + if (p_dm_odm->ant_type == ODM_AUTO_ANT) + odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ } - -VOID -odm_S0S1_SWAntDiv_Init_8723B( - IN PVOID pDM_VOID + +void +odm_s0s1_sw_ant_div_init_8723b( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv] \n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n")); - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1); - - //Output Pin Settings - //ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); - ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); + /* Mapping Table */ + odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 0); + odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 1); - pDM_FatTable->bBecomeLinked =FALSE; - pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; - pDM_SWAT_Table->Double_chk_flag = 0; - - //2 [--For HW Bug Setting] - ODM_SetBBReg(pDM_Odm, 0x80C , BIT21, 0); //TX Ant by Reg + /* Output Pin Settings */ + /* odm_set_bb_reg(p_dm_odm, 0x948, BIT6, 0x1); */ + odm_set_bb_reg(p_dm_odm, 0x870, BIT(9) | BIT(8), 0); + + p_dm_fat_table->is_become_linked = false; + p_dm_swat_table->try_flag = SWAW_STEP_INIT; + p_dm_swat_table->double_chk_flag = 0; + + /* 2 [--For HW Bug setting] */ + odm_set_bb_reg(p_dm_odm, 0x80C, BIT(21), 0); /* TX ant by Reg */ } -VOID -ODM_UpdateRxIdleAnt_8723B( - IN PVOID pDM_VOID, - IN u1Byte Ant, - IN u4Byte DefaultAnt, - IN u4Byte OptionalAnt +void +odm_update_rx_idle_ant_8723b( + void *p_dm_void, + u8 ant, + u32 default_ant, + u32 optional_ant ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u1Byte count=0; - u1Byte u1Temp; - u1Byte H2C_Parameter; - - if ((!pDM_Odm->bLinked) && (pDM_Odm->AntType == ODM_AUTO_ANT)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to no link\n")); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + u8 count = 0; + u8 u1_temp; + u8 h2c_parameter; + + if ((!p_dm_odm->is_linked) && (p_dm_odm->ant_type == ODM_AUTO_ANT)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n")); return; } #if 0 - // Send H2C command to FW - // Enable wifi calibration - H2C_Parameter = TRUE; - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_WIFI_CALIBRATION, 1, &H2C_Parameter); - - // Check if H2C command sucess or not (0x1e6) - u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e6); - while((u1Temp != 0x1) && (count < 100)) - { - ODM_delay_us(10); - u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e6); + /* Send H2C command to FW */ + /* Enable wifi calibration */ + h2c_parameter = true; + odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); + + /* Check if H2C command sucess or not (0x1e6) */ + u1_temp = odm_read_1byte(p_dm_odm, 0x1e6); + while ((u1_temp != 0x1) && (count < 100)) { + ODM_delay_us(10); + u1_temp = odm_read_1byte(p_dm_odm, 0x1e6); count++; } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: H2C command status = %d, count = %d\n", u1Temp, count)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n", u1_temp, count)); - if(u1Temp == 0x1) - { - // Check if BT is doing IQK (0x1e7) + if (u1_temp == 0x1) { + /* Check if BT is doing IQK (0x1e7) */ count = 0; - u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e7); - while((!(u1Temp & BIT0)) && (count < 100)) - { - ODM_delay_us(50); - u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e7); + u1_temp = odm_read_1byte(p_dm_odm, 0x1e7); + while ((!(u1_temp & BIT(0))) && (count < 100)) { + ODM_delay_us(50); + u1_temp = odm_read_1byte(p_dm_odm, 0x1e7); count++; } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: BT IQK status = %d, count = %d\n", u1Temp, count)); - - if(u1Temp & BIT0) - { - ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); - ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt); - ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX - ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); //Default TX - pDM_FatTable->RxIdleAnt = Ant; - - // Set TX AGC by S0/S1 - // Need to consider Linux driver + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n", u1_temp, count)); + + if (u1_temp & BIT(0)) { + odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0x1); + odm_set_bb_reg(p_dm_odm, 0x948, BIT(9), default_ant); + odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT4 | BIT3, default_ant); /* Default RX */ + odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT7 | BIT6, optional_ant); /* Optional RX */ + odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, default_ant); /* Default TX */ + p_dm_fat_table->rx_idle_ant = ant; + + /* Set TX AGC by S0/S1 */ + /* Need to consider Linux driver */ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel); -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel); + p_adapter->hal_func.set_tx_power_level_handler(p_adapter, *p_dm_odm->p_channel); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_hal_set_tx_power_level(p_adapter, *p_dm_odm->p_channel); #endif - // Set IQC by S0/S1 - ODM_SetIQCbyRFpath(pDM_Odm,DefaultAnt); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Sucess to set RX antenna\n")); - } - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to BT IQK\n")); - } - else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to H2C command fail\n")); - - // Send H2C command to FW - // Disable wifi calibration - H2C_Parameter = FALSE; - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_WIFI_CALIBRATION, 1, &H2C_Parameter); + /* Set IQC by S0/S1 */ + odm_set_iqc_by_rfpath(p_dm_odm, default_ant); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Sucess to set RX antenna\n")); + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n")); + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n")); + + /* Send H2C command to FW */ + /* Disable wifi calibration */ + h2c_parameter = false; + odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); #else - ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); - ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt); - ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); /*Default RX*/ - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); /*Optional RX*/ - ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); /*Default TX*/ - pDM_FatTable->RxIdleAnt = Ant; + odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0x1); + odm_set_bb_reg(p_dm_odm, 0x948, BIT(9), default_ant); + odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT4 | BIT3, default_ant); /*Default RX*/ + odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT7 | BIT6, optional_ant); /*Optional RX*/ + odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, default_ant); /*Default TX*/ + p_dm_fat_table->rx_idle_ant = ant; /* Set TX AGC by S0/S1 */ /* Need to consider Linux driver */ - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel); - #elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel); - #endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + p_adapter->HalFunc.SetTxPowerLevelHandler(p_adapter, *p_dm_odm->p_channel); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_hal_set_tx_power_level(p_adapter, *p_dm_odm->p_channel); +#endif /* Set IQC by S0/S1 */ - ODM_SetIQCbyRFpath(pDM_Odm, DefaultAnt); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Success to set RX antenna\n")); + odm_set_iqc_by_rfpath(p_dm_odm, default_ant); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n")); #endif } -BOOLEAN -phydm_IsBtEnable_8723b( - IN PVOID pDM_VOID +boolean +phydm_is_bt_enable_8723b( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte bt_state; - /*u4Byte reg75;*/ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 bt_state; + /*u32 reg75;*/ - /*reg75 = ODM_GetBBReg(pDM_Odm, 0x74 , BIT8);*/ - /*ODM_SetBBReg(pDM_Odm, 0x74 , BIT8, 0x0);*/ - ODM_SetBBReg(pDM_Odm, 0xa0 , BIT24|BIT25|BIT26, 0x5); - bt_state = ODM_GetBBReg(pDM_Odm, 0xa0 , (BIT3|BIT2|BIT1|BIT0)); - /*ODM_SetBBReg(pDM_Odm, 0x74 , BIT8, reg75);*/ + /*reg75 = odm_get_bb_reg(p_dm_odm, 0x74, BIT8);*/ + /*odm_set_bb_reg(p_dm_odm, 0x74, BIT8, 0x0);*/ + odm_set_bb_reg(p_dm_odm, 0xa0, BIT(24) | BIT(25) | BIT(26), 0x5); + bt_state = odm_get_bb_reg(p_dm_odm, 0xa0, (BIT(3) | BIT(2) | BIT(1) | BIT(0))); + /*odm_set_bb_reg(p_dm_odm, 0x74, BIT8, reg75);*/ if ((bt_state == 4) || (bt_state == 7) || (bt_state == 9) || (bt_state == 13)) - return TRUE; + return true; else - return FALSE; + return false; } -#endif //#if (RTL8723B_SUPPORT == 1) +#endif /* #if (RTL8723B_SUPPORT == 1) */ #if (RTL8821A_SUPPORT == 1) #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 -VOID +void phydm_hl_smart_ant_type1_init_8821a( - IN PVOID pDM_VOID - ) + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u4Byte value32; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A SmartAnt_Init => AntDivType=[Hong-Lin Smart Ant Type1]\n")); - - /*---------------------------------------- - GPIO 2-3 for Beam control - reg0x66[2]=0 - reg0x44[27:26] = 0 - reg0x44[23:16] //enable_output for P_GPIO[7:0] - reg0x44[15:8] //output_value for P_GPIO[7:0] - reg0x40[1:0] = 0 //GPIO function - ------------------------------------------*/ - - /*GPIO Setting*/ - ODM_SetMACReg(pDM_Odm, 0x64 , BIT18, 0); - ODM_SetMACReg(pDM_Odm, 0x44 , BIT27|BIT26, 0); - ODM_SetMACReg(pDM_Odm, 0x44 , BIT19|BIT18, 0x3); /*enable_output for P_GPIO[3:2]*/ - /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT11|BIT10, 0);*/ /*output value*/ - ODM_SetMACReg(pDM_Odm, 0x40 , BIT1|BIT0, 0); /*GPIO function*/ - - /*Hong_lin smart antenna HW Setting*/ - pdm_sat_table->data_codeword_bit_num = 24;/*max=32*/ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + u32 value32; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A SmartAnt_Init => ant_div_type=[Hong-Lin Smart ant Type1]\n")); + +#if 0 + /* ---------------------------------------- */ + /* GPIO 2-3 for Beam control */ + /* reg0x66[2]=0 */ + /* reg0x44[27:26] = 0 */ + /* reg0x44[23:16] enable_output for P_GPIO[7:0] */ + /* reg0x44[15:8] output_value for P_GPIO[7:0] */ + /* reg0x40[1:0] = 0 GPIO function */ + /* ------------------------------------------ */ +#endif + + /*GPIO setting*/ + odm_set_mac_reg(p_dm_odm, 0x64, BIT(18), 0); + odm_set_mac_reg(p_dm_odm, 0x44, BIT(27) | BIT(26), 0); + odm_set_mac_reg(p_dm_odm, 0x44, BIT(19) | BIT18, 0x3); /*enable_output for P_GPIO[3:2]*/ + /*odm_set_mac_reg(p_dm_odm, 0x44, BIT(11)|BIT10, 0);*/ /*output value*/ + odm_set_mac_reg(p_dm_odm, 0x40, BIT(1) | BIT0, 0); /*GPIO function*/ + + /*Hong_lin smart antenna HW setting*/ + pdm_sat_table->rfu_codeword_total_bit_num = 24;/*max=32*/ + pdm_sat_table->rfu_each_ant_bit_num = 4; pdm_sat_table->beam_patten_num_each_ant = 4; - #if DEV_BUS_TYPE == RT_SDIO_INTERFACE +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE pdm_sat_table->latch_time = 100; /*mu sec*/ - #elif DEV_BUS_TYPE == RT_USB_INTERFACE +#elif DEV_BUS_TYPE == RT_USB_INTERFACE pdm_sat_table->latch_time = 100; /*mu sec*/ - #endif +#endif pdm_sat_table->pkt_skip_statistic_en = 0; - + pdm_sat_table->ant_num = 1;/*max=8*/ pdm_sat_table->ant_num_total = NUM_ANTENNA_8821A; pdm_sat_table->first_train_ant = MAIN_ANT; - + pdm_sat_table->rfu_codeword_table[0] = 0x0; pdm_sat_table->rfu_codeword_table[1] = 0x4; pdm_sat_table->rfu_codeword_table[2] = 0x8; @@ -1541,3283 +1473,4359 @@ phydm_hl_smart_ant_type1_init_8821a( /*set default beam*/ pdm_sat_table->fast_training_beam_num = 0; pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - phydm_set_all_ant_same_beam_num(pDM_Odm); + phydm_set_all_ant_same_beam_num(p_dm_odm); - pDM_FatTable->FAT_State = FAT_BEFORE_LINK_STATE; + p_dm_fat_table->fat_state = FAT_BEFORE_LINK_STATE; - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskDWord, 0x01000100); - ODM_SetBBReg(pDM_Odm, 0xCA8 , bMaskDWord, 0x01000100); + odm_set_bb_reg(p_dm_odm, 0xCA4, MASKDWORD, 0x01000100); + odm_set_bb_reg(p_dm_odm, 0xCA8, MASKDWORD, 0x01000100); - /*[BB] FAT Setting*/ - ODM_SetBBReg(pDM_Odm, 0xc08 , BIT18|BIT17|BIT16, pdm_sat_table->ant_num); - ODM_SetBBReg(pDM_Odm, 0xc08 , BIT31, 0); /*increase ant num every FAT period 0:+1, 1+2*/ - ODM_SetBBReg(pDM_Odm, 0x8c4 , BIT2|BIT1, 1); /*change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/ - ODM_SetBBReg(pDM_Odm, 0x8c4 , BIT0, 1); /*FAT_watchdog_en*/ - - value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord); - ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /*Reg7B4[16]=1 enable antenna training */ - /*Reg7B4[17]=1 enable match MAC Addr*/ - ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);/*Match MAC ADDR*/ - ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0); + /*[BB] FAT setting*/ + odm_set_bb_reg(p_dm_odm, 0xc08, BIT(18) | BIT(17) | BIT(16), pdm_sat_table->ant_num); + odm_set_bb_reg(p_dm_odm, 0xc08, BIT(31), 0); /*increase ant num every FAT period 0:+1, 1+2*/ + odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(2) | BIT1, 1); /*change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/ + odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(0), 1); /*FAT_watchdog_en*/ + + value32 = odm_get_mac_reg(p_dm_odm, 0x7B4, MASKDWORD); + odm_set_mac_reg(p_dm_odm, 0x7b4, MASKDWORD, value32 | (BIT(16) | BIT17)); /*Reg7B4[16]=1 enable antenna training */ + /*Reg7B4[17]=1 enable match MAC addr*/ + odm_set_mac_reg(p_dm_odm, 0x7b4, 0xFFFF, 0);/*Match MAC ADDR*/ + odm_set_mac_reg(p_dm_odm, 0x7b0, MASKDWORD, 0); } #endif -VOID -odm_TRX_HWAntDiv_Init_8821A( - IN PVOID pDM_VOID - ) +void +odm_trx_hw_ant_div_init_8821a( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n")); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - //Output Pin Settings - ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n")); - ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control - ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control + /* Output Pin Settings */ + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(25), 0); - ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745); - ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0); - - ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin - ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control - ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse - - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); - - //OFDM HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias - - //CCK HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + odm_set_mac_reg(p_dm_odm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(p_dm_odm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ - ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit - ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable + odm_set_bb_reg(p_dm_odm, 0xCB8, BIT(16), 0); - //BT Coexistence - ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1 + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /* by WLAN control */ + odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ - ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + /* Mapping Table */ + odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); + odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); - //response TX ant by RX ant - ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1); - -} + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x10); /* bias */ -VOID -odm_S0S1_SWAntDiv_Init_8821A( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + /* CCK HW AntDiv Parameters */ + odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv]\n")); + odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ - //Output Pin Settings - ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); + /* BT Coexistence */ + odm_set_bb_reg(p_dm_odm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(p_dm_odm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ - ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control - ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control + odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ - ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745); - ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0); - - ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin - ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control - ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse - - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); - - //OFDM HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias - - //CCK HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + /* response TX ant by RX ant */ + odm_set_mac_reg(p_dm_odm, 0x668, BIT(3), 1); - ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit - ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable +} - //BT Coexistence - ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1 +void +odm_s0s1_sw_ant_div_init_8821a( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n")); - //response TX ant by RX ant - ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1); + /* Output Pin Settings */ + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(25), 0); + odm_set_mac_reg(p_dm_odm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(p_dm_odm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ - ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); - - pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; - pDM_SWAT_Table->Double_chk_flag = 0; - pDM_SWAT_Table->CurAntenna = MAIN_ANT; - pDM_SWAT_Table->PreAntenna = MAIN_ANT; - pDM_SWAT_Table->SWAS_NoLink_State = 0; + odm_set_bb_reg(p_dm_odm, 0xCB8, BIT(16), 0); -} -#endif //#if (RTL8821A_SUPPORT == 1) + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /* by WLAN control */ + odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ -#if (RTL8821C_SUPPORT == 1) -VOID -odm_TRX_HWAntDiv_Init_8821C( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821C AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n")); - //Output Pin Settings - ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); + /* Mapping Table */ + odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); + odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); - ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control - ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x10); /* bias */ - ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745); - ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0); - - ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin - ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control - ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse - - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); - - //OFDM HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias - - //CCK HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + /* CCK HW AntDiv Parameters */ + odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ - ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit - ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable + odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ - //BT Coexistence - ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1 - ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1 + /* BT Coexistence */ + odm_set_bb_reg(p_dm_odm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(p_dm_odm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ - //Timming issue - ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); /*keep antidx after tx for ACK ( unit x 3.2 mu sec)*/ - ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ - //response TX ant by RX ant - ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1); - -} -#endif //#if (RTL8821C_SUPPORT == 1) + /* response TX ant by RX ant */ + odm_set_mac_reg(p_dm_odm, 0x668, BIT(3), 1); -#if (RTL8881A_SUPPORT == 1) -VOID -odm_TRX_HWAntDiv_Init_8881A( - IN PVOID pDM_VOID - ) + odm_set_bb_reg(p_dm_odm, 0x900, BIT(18), 0); + + p_dm_swat_table->try_flag = SWAW_STEP_INIT; + p_dm_swat_table->double_chk_flag = 0; + p_dm_swat_table->cur_antenna = MAIN_ANT; + p_dm_swat_table->pre_antenna = MAIN_ANT; + p_dm_swat_table->swas_no_link_state = 0; + +} +#endif /* #if (RTL8821A_SUPPORT == 1) */ + +#if (RTL8822B_SUPPORT == 1) +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 +void +phydm_hl_smart_ant_type2_init_8822b( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n")); - - //Output Pin Settings - // [SPDT related] - ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); - ODM_SetMACReg(pDM_Odm, 0x4C , BIT26, 0); - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT22, 0); - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT24, 1); - ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF00, 8); // DPDT_P = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000, 8); // DPDT_N = ANTSEL[0] + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + u8 j; + u8 rfu_codeword_table_init_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = { + {1, 1},/*0*/ + {1, 2}, + {2, 1}, + {2, 2}, + {4, 0}, + {5, 0}, + {6, 0}, + {7, 0}, + {8, 0},/*8*/ + {9, 0}, + {0xa, 0}, + {0xb, 0}, + {0xc, 0}, + {0xd, 0}, + {0xe, 0}, + {0xf, 0} + }; + u8 rfu_codeword_table_init_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] ={ + #if 1 + {9, 1},/*0*/ + {9, 9}, + {1, 9}, + {9, 6}, + {2, 1}, + {2, 9}, + {9, 2}, + {2, 2},/*8*/ + {6, 1}, + {6, 9}, + {2, 9}, + {2, 2}, + {6, 2}, + {6, 6}, + {2, 6}, + {1, 1} + #else + {1, 1},/*0*/ + {9, 1}, + {9, 9}, + {1, 9}, + {1, 2}, + {9, 2}, + {9, 6}, + {1, 6}, + {2, 1},/*8*/ + {6, 1}, + {6, 9}, + {2, 9}, + {2, 2}, + {6, 2}, + {6, 6}, + {2, 6} + #endif + }; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***RTK 8822B SmartAnt_Init: Hong-Bo SmrtAnt Type2]\n")); + + /* ---------------------------------------- */ + /* GPIO 0-1 for Beam control */ + /* reg0x66[2:0]=0 */ + /* reg0x44[25:24] = 0 */ + /* reg0x44[23:16] enable_output for P_GPIO[7:0] */ + /* reg0x44[15:8] output_value for P_GPIO[7:0] */ + /* reg0x40[1:0] = 0 GPIO function */ + /* ------------------------------------------ */ + + odm_move_memory(p_dm_odm, pdm_sat_table->rfu_codeword_table_2g, rfu_codeword_table_init_2g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B)); + odm_move_memory(p_dm_odm, pdm_sat_table->rfu_codeword_table_5g, rfu_codeword_table_init_5g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B)); + + /*GPIO setting*/ + odm_set_mac_reg(p_dm_odm, 0x64, (BIT(18) | BIT(17) | BIT(16)), 0); + odm_set_mac_reg(p_dm_odm, 0x44, BIT(25) | BIT24, 0); /*config P_GPIO[3:2] to data port*/ + odm_set_mac_reg(p_dm_odm, 0x44, BIT(17) | BIT16, 0x3); /*enable_output for P_GPIO[3:2]*/ + /*odm_set_mac_reg(p_dm_odm, 0x44, BIT(9)|BIT8, 0);*/ /*P_GPIO[3:2] output value*/ + odm_set_mac_reg(p_dm_odm, 0x40, BIT(1) | BIT0, 0); /*GPIO function*/ + + /*Hong_lin smart antenna HW setting*/ + pdm_sat_table->rfu_protocol_type = 2; + pdm_sat_table->rfu_protocol_delay_time = 45; - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); - - //OFDM HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias - ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + pdm_sat_table->rfu_codeword_total_bit_num = 16;/*max=32bit*/ + pdm_sat_table->rfu_each_ant_bit_num = 4; - //CCK HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + pdm_sat_table->total_beam_set_num = 4; + pdm_sat_table->total_beam_set_num_2g = 4; + pdm_sat_table->total_beam_set_num_5g = 8; - //2 [--For HW Bug Setting] +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + pdm_sat_table->latch_time = 100; /*mu sec*/ +#elif DEV_BUS_TYPE == RT_USB_INTERFACE + pdm_sat_table->latch_time = 100; /*mu sec*/ +#endif + pdm_sat_table->pkt_skip_statistic_en = 0; - ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug -} + pdm_sat_table->ant_num = 2; + pdm_sat_table->ant_num_total = MAX_PATH_NUM_8822B; + pdm_sat_table->first_train_ant = MAIN_ANT; -#endif //#if (RTL8881A_SUPPORT == 1) -#if (RTL8812A_SUPPORT == 1) -VOID -odm_TRX_HWAntDiv_Init_8812A( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n")); - - //3 //3 --RFE pin setting--------- - //[BB] - ODM_SetBBReg(pDM_Odm, 0x900 , BIT10|BIT9|BIT8, 0x0); //disable SW switch - ODM_SetBBReg(pDM_Odm, 0x900 , BIT17|BIT16, 0x0); - ODM_SetBBReg(pDM_Odm, 0x974 , BIT7|BIT6, 0x3); // in/out - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT26, 0); - ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT27, 1); - ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF000000, 8); // DPDT_P = ANTSEL[0] - ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000000, 8); // DPDT_N = ANTSEL[0] - //3 ------------------------- - - //Mapping Table - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); - ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); - - //OFDM HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold - ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias - ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns - - //CCK HW AntDiv Parameters - ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M - ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + pdm_sat_table->fix_beam_pattern_en = 0; + pdm_sat_table->decision_holding_period = 0; + + /*beam training setting*/ + pdm_sat_table->pkt_counter = 0; + pdm_sat_table->per_beam_training_pkt_num = 10; - //2 [--For HW Bug Setting] + /*set default beam*/ + pdm_sat_table->fast_training_beam_num = 0; + pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug + for (j = 0; j < SUPPORT_BEAM_SET_PATTERN_NUM; j++) { + + pdm_sat_table->beam_set_avg_rssi_pre[j] = 0; + pdm_sat_table->beam_set_train_val_diff[j] = 0; + pdm_sat_table->beam_set_train_cnt[j] = 0; + } + phydm_set_rfu_beam_pattern_type2(p_dm_odm); + p_dm_fat_table->fat_state = FAT_BEFORE_LINK_STATE; } +#endif +#endif -#endif //#if (RTL8812A_SUPPORT == 1) -#if (RTL8188F_SUPPORT == 1) -VOID -odm_S0S1_SWAntDiv_Init_8188F( - IN PVOID pDM_VOID +#if (RTL8821C_SUPPORT == 1) +void +odm_trx_hw_ant_div_init_8821c( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188F AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv]\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821C AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n")); + /* Output Pin Settings */ + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(25), 0); + odm_set_mac_reg(p_dm_odm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(p_dm_odm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ - /*GPIO Setting*/ - /*ODM_SetMACReg(pDM_Odm, 0x64 , BIT18, 0); */ - /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT28|BIT27, 0);*/ - ODM_SetMACReg(pDM_Odm, 0x44 , BIT20|BIT19, 0x3); /*enable_output for P_GPIO[4:3]*/ - /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT12|BIT11, 0);*/ /*output value*/ - /*ODM_SetMACReg(pDM_Odm, 0x40 , BIT1|BIT0, 0);*/ /*GPIO function*/ + odm_set_bb_reg(p_dm_odm, 0xCB8, BIT(16), 0); - pDM_FatTable->bBecomeLinked = FALSE; - pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; - pDM_SWAT_Table->Double_chk_flag = 0; -} + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /* by WLAN control */ + odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ -VOID -phydm_update_rx_idle_antenna_8188F( - IN PVOID pDM_VOID, - IN u4Byte default_ant -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte codeword; + /* Mapping Table */ + odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); + odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); - if (default_ant == ANT1_2G) - codeword = 1; /*2'b01*/ - else - codeword = 2;/*2'b10*/ - - ODM_SetMACReg(pDM_Odm, 0x44 , (BIT12|BIT11), codeword); /*GPIO[4:3] output value*/ -} + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x10); /* bias */ -#endif + /* CCK HW AntDiv Parameters */ + odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ + /* BT Coexistence */ + odm_set_bb_reg(p_dm_odm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(p_dm_odm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + + /* Timming issue */ + odm_set_bb_reg(p_dm_odm, 0x818, BIT(23) | BIT22 | BIT21 | BIT20, 0); /*keep antidx after tx for ACK ( unit x 3.2 mu sec)*/ + odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ + + /* response TX ant by RX ant */ + odm_set_mac_reg(p_dm_odm, 0x668, BIT(3), 1); + +} +#endif /* #if (RTL8821C_SUPPORT == 1) */ -#ifdef ODM_EVM_ENHANCE_ANTDIV -VOID -odm_EVM_FastAnt_Reset( - IN PVOID pDM_VOID - ) +#if (RTL8881A_SUPPORT == 1) +void +odm_trx_hw_ant_div_init_8881a( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - pDM_FatTable->EVM_method_enable=0; - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); - pDM_FatTable->FAT_State = NORMAL_STATE_MIAN; - pDM_Odm->antdiv_period=0; - ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 0); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n")); + + /* Output Pin Settings */ + /* [SPDT related] */ + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(25), 0); + odm_set_mac_reg(p_dm_odm, 0x4C, BIT(26), 0); + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(31), 0); /* delay buffer */ + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(22), 0); + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(24), 1); + odm_set_bb_reg(p_dm_odm, 0xCB0, 0xF00, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(p_dm_odm, 0xCB0, 0xF0000, 8); /* DPDT_N = ANTSEL[0] */ + + /* Mapping Table */ + odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); + odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); + + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x0); /* bias */ + odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ + + /* CCK HW AntDiv Parameters */ + odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + + /* 2 [--For HW Bug setting] */ + + odm_set_bb_reg(p_dm_odm, 0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */ } +#endif /* #if (RTL8881A_SUPPORT == 1) */ + -VOID -odm_EVM_Enhance_AntDiv( - IN PVOID pDM_VOID - ) +#if (RTL8812A_SUPPORT == 1) +void +odm_trx_hw_ant_div_init_8812a( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte Main_RSSI, Aux_RSSI ; - u4Byte Main_CRC_utility=0,Aux_CRC_utility=0,utility_ratio=1; - u4Byte Main_EVM, Aux_EVM,Diff_RSSI=0,diff_EVM=0; - u1Byte score_EVM=0,score_CRC=0; - u1Byte rssi_larger_ant = 0; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u4Byte value32, i; - BOOLEAN Main_above1=FALSE,Aux_above1=FALSE; - BOOLEAN Force_antenna=FALSE; - PSTA_INFO_T pEntry; - pDM_FatTable->TargetAnt_enhance=0xFF; - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n")); + + /* 3 */ /* 3 --RFE pin setting--------- */ + /* [BB] */ + odm_set_bb_reg(p_dm_odm, 0x900, BIT(10) | BIT9 | BIT8, 0x0); /* disable SW switch */ + odm_set_bb_reg(p_dm_odm, 0x900, BIT(17) | BIT(16), 0x0); + odm_set_bb_reg(p_dm_odm, 0x974, BIT(7) | BIT6, 0x3); /* in/out */ + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(31), 0); /* delay buffer */ + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(26), 0); + odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(27), 1); + odm_set_bb_reg(p_dm_odm, 0xCB0, 0xF000000, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(p_dm_odm, 0xCB0, 0xF0000000, 8); /* DPDT_N = ANTSEL[0] */ + /* 3 ------------------------- */ + + /* Mapping Table */ + odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); + odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); + + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x0); /* bias */ + odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ + + /* CCK HW AntDiv Parameters */ + odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + + /* 2 [--For HW Bug setting] */ + + odm_set_bb_reg(p_dm_odm, 0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */ + +} + +#endif /* #if (RTL8812A_SUPPORT == 1) */ + +#if (RTL8188F_SUPPORT == 1) +void +odm_s0s1_sw_ant_div_init_8188f( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188F AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n")); + + + /*GPIO setting*/ + /*odm_set_mac_reg(p_dm_odm, 0x64, BIT18, 0); */ + /*odm_set_mac_reg(p_dm_odm, 0x44, BIT28|BIT27, 0);*/ + /*odm_set_mac_reg(p_dm_odm, 0x44, BIT(20) | BIT19, 0x3);*/ /*enable_output for P_GPIO[4:3]*/ + /*odm_set_mac_reg(p_dm_odm, 0x44, BIT(12)|BIT11, 0);*/ /*output value*/ + /*odm_set_mac_reg(p_dm_odm, 0x40, BIT(1)|BIT0, 0);*/ /*GPIO function*/ + + if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (p_dm_odm->support_interface == ODM_ITRF_USB) + odm_set_mac_reg(p_dm_odm, 0x44, BIT(20) | BIT19, 0x3); /*enable_output for P_GPIO[4:3]*/ + else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + odm_set_mac_reg(p_dm_odm, 0x44, BIT(18), 0x1); /*enable_output for P_GPIO[2]*/ + } - if((pDM_Odm->SupportICType & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) - { - if(pDM_Odm->bOneEntryOnly) - { - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[One Client only] \n")); - i = pDM_Odm->OneEntry_MACID; + p_dm_fat_table->is_become_linked = false; + p_dm_swat_table->try_flag = SWAW_STEP_INIT; + p_dm_swat_table->double_chk_flag = 0; +} - Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; - Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; +void +phydm_update_rx_idle_antenna_8188F( + void *p_dm_void, + u32 default_ant +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 codeword; - if((Main_RSSI==0 && Aux_RSSI !=0 && Aux_RSSI>=FORCE_RSSI_DIFF) || (Main_RSSI!=0 && Aux_RSSI==0 && Main_RSSI>=FORCE_RSSI_DIFF)) - { - Diff_RSSI=FORCE_RSSI_DIFF; - } - else if(Main_RSSI!=0 && Aux_RSSI !=0) - { - Diff_RSSI = (Main_RSSI>=Aux_RSSI)?(Main_RSSI-Aux_RSSI):(Aux_RSSI-Main_RSSI); + if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (p_dm_odm->support_interface == ODM_ITRF_USB) { + if (default_ant == ANT1_2G) + codeword = 1; /*2'b01*/ + else + codeword = 2;/*2'b10*/ + odm_set_mac_reg(p_dm_odm, 0x44, (BIT(12) | BIT11), codeword); /*GPIO[4:3] output value*/ + } else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) { + if (default_ant == ANT1_2G) { + codeword = 0; /*1'b0*/ + odm_set_bb_reg(p_dm_odm, 0x870, BIT(9)|BIT8, 0x3); + odm_set_bb_reg(p_dm_odm, 0x860, BIT(9)|BIT8, 0x1); + } else { + codeword = 1;/*1'b1*/ + odm_set_bb_reg(p_dm_odm, 0x870, BIT(9)|BIT8, 0x3); + odm_set_bb_reg(p_dm_odm, 0x860, BIT(9)|BIT8, 0x2); } - - if (Main_RSSI >= Aux_RSSI) + odm_set_mac_reg(p_dm_odm, 0x44, BIT(10), codeword); /*GPIO[2] output value*/ + } + } +} +#endif + + + +#ifdef ODM_EVM_ENHANCE_ANTDIV +void +phydm_evm_sw_antdiv_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + + /*EVM enhance AntDiv method init----------------------------------------------------------------------*/ + p_dm_fat_table->EVM_method_enable = 0; + p_dm_fat_table->fat_state = NORMAL_STATE_MIAN; + p_dm_fat_table->fat_state_cnt = 0; + p_dm_fat_table->pre_antdiv_rssi = 0; + + p_dm_odm->antdiv_intvl = 30; + p_dm_odm->antdiv_train_num = 2; + odm_set_bb_reg(p_dm_odm, 0x910, 0x3f, 0xf); + p_dm_odm->antdiv_evm_en = 1; + /*p_dm_odm->antdiv_period=1;*/ + p_dm_odm->evm_antdiv_period = 3; + p_dm_odm->stop_antdiv_rssi_th = 3; + p_dm_odm->stop_antdiv_tp_th = 80; + p_dm_odm->antdiv_tp_period = 3; + p_dm_odm->stop_antdiv_tp_diff_th = 5; +} + +void +odm_evm_fast_ant_reset( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + + p_dm_fat_table->EVM_method_enable = 0; + odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); + p_dm_fat_table->fat_state = NORMAL_STATE_MIAN; + p_dm_fat_table->fat_state_cnt = 0; + p_dm_odm->antdiv_period = 0; + odm_set_mac_reg(p_dm_odm, 0x608, BIT(8), 0); +} + + +void +odm_evm_enhance_ant_div( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 main_rssi, aux_rssi ; + u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1; + u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0; + u32 main_2ss_evm[2], aux_2ss_evm[2]; + u32 main_1ss_evm, aux_1ss_evm; + u32 main_2ss_evm_sum, aux_2ss_evm_sum; + u8 score_EVM = 0, score_CRC = 0; + u8 rssi_larger_ant = 0; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + u32 value32, i; + boolean main_above1 = false, aux_above1 = false; + boolean force_antenna = false; + struct sta_info *p_entry; + u32 antdiv_tp_main_avg, antdiv_tp_aux_avg; + u8 curr_rssi, rssi_diff; + u32 tp_diff; + u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0; + u8 target_ant_evm_1ss, target_ant_evm_2ss; + u8 decision_evm_ss; + u8 next_ant; + + p_dm_fat_table->target_ant_enhance = 0xFF; + + if ((p_dm_odm->support_ic_type & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) { + if (p_dm_odm->is_one_entry_only) { + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[One Client only]\n")); */ + i = p_dm_odm->one_entry_macid; + p_entry = p_dm_odm->p_odm_sta_info[i]; + + main_rssi = (p_dm_fat_table->main_ant_cnt[i] != 0) ? (p_dm_fat_table->main_ant_sum[i] / p_dm_fat_table->main_ant_cnt[i]) : 0; + aux_rssi = (p_dm_fat_table->aux_ant_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_sum[i] / p_dm_fat_table->aux_ant_cnt[i]) : 0; + + if ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF)) + diff_rssi = FORCE_RSSI_DIFF; + else if (main_rssi != 0 && aux_rssi != 0) + diff_rssi = (main_rssi >= aux_rssi) ? (main_rssi - aux_rssi) : (aux_rssi - main_rssi); + + if (main_rssi >= aux_rssi) rssi_larger_ant = MAIN_ANT; else rssi_larger_ant = AUX_ANT; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Main_Cnt = (( %d )) , Main_RSSI= (( %d ))\n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Aux_Cnt = (( %d )) , Aux_RSSI = (( %d ))\n", pDM_FatTable->AuxAnt_Cnt[i], Aux_RSSI)); - - if( ((Main_RSSI>=Evm_RSSI_TH_High||Aux_RSSI>=Evm_RSSI_TH_High )|| (pDM_FatTable->EVM_method_enable==1) ) - //&& (Diff_RSSI <= FORCE_RSSI_DIFF + 1) - ) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[> TH_H || EVM_method_enable==1] && ")); - - if(((Main_RSSI>=Evm_RSSI_TH_Low)||(Aux_RSSI>=Evm_RSSI_TH_Low) )) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[> TH_L ] \n")); - - //2 [ Normal state Main] - if(pDM_FatTable->FAT_State == NORMAL_STATE_MIAN) - { - - pDM_FatTable->EVM_method_enable=1; - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - pDM_Odm->antdiv_period = pDM_Odm->evm_antdiv_period; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ start training: MIAN] \n")); - pDM_FatTable->MainAntEVM_Sum[i] = 0; - pDM_FatTable->AuxAntEVM_Sum[i] = 0; - pDM_FatTable->MainAntEVM_Cnt[i] = 0; - pDM_FatTable->AuxAntEVM_Cnt[i] = 0; - - pDM_FatTable->FAT_State = NORMAL_STATE_AUX; - ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 1); //Accept CRC32 Error packets. - ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); - - pDM_FatTable->CRC32_Ok_Cnt=0; - pDM_FatTable->CRC32_Fail_Cnt=0; - ODM_SetTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //m - } - //2 [ Normal state Aux ] - else if(pDM_FatTable->FAT_State == NORMAL_STATE_AUX) - { - pDM_FatTable->MainCRC32_Ok_Cnt=pDM_FatTable->CRC32_Ok_Cnt; - pDM_FatTable->MainCRC32_Fail_Cnt=pDM_FatTable->CRC32_Fail_Cnt; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ start training: AUX] \n")); - pDM_FatTable->FAT_State = TRAINING_STATE; - ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); - - pDM_FatTable->CRC32_Ok_Cnt=0; - pDM_FatTable->CRC32_Fail_Cnt=0; - ODM_SetTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //ms - } - else if(pDM_FatTable->FAT_State == TRAINING_STATE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Training state ] \n")); - pDM_FatTable->FAT_State = NORMAL_STATE_MIAN; - - //3 [CRC32 statistic] - pDM_FatTable->AuxCRC32_Ok_Cnt=pDM_FatTable->CRC32_Ok_Cnt; - pDM_FatTable->AuxCRC32_Fail_Cnt=pDM_FatTable->CRC32_Fail_Cnt; - - if ((pDM_FatTable->MainCRC32_Ok_Cnt > ((pDM_FatTable->AuxCRC32_Ok_Cnt)<<1)) || ((Diff_RSSI >= 20) && (rssi_larger_ant == MAIN_ANT))) { - pDM_FatTable->TargetAnt_CRC32=MAIN_ANT; - Force_antenna=TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Main\n")); - } else if ((pDM_FatTable->AuxCRC32_Ok_Cnt > ((pDM_FatTable->MainCRC32_Ok_Cnt)<<1)) || ((Diff_RSSI >= 20) && (rssi_larger_ant == AUX_ANT))) { - pDM_FatTable->TargetAnt_CRC32=AUX_ANT; - Force_antenna=TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Aux\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Main_Cnt=(( %d )), main_rssi=(( %d ))\n", p_dm_fat_table->main_ant_cnt[i], main_rssi)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n", p_dm_fat_table->aux_ant_cnt[i], aux_rssi)); + + if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || (p_dm_fat_table->EVM_method_enable == 1)) + /* && (diff_rssi <= FORCE_RSSI_DIFF + 1) */ + ) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("> TH_H || EVM_method_enable==1\n")); + + if (((main_rssi >= evm_rssi_th_low) || (aux_rssi >= evm_rssi_th_low))) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("> TH_L, fat_state_cnt =((%d))\n", p_dm_fat_table->fat_state_cnt)); + + /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/ + if (p_dm_fat_table->fat_state_cnt < ((p_dm_odm->antdiv_train_num)<<1)) { + + if (p_dm_fat_table->fat_state_cnt == 0) { + /*Reset EVM 1SS Method */ + p_dm_fat_table->main_ant_evm_sum[i] = 0; + p_dm_fat_table->aux_ant_evm_sum[i] = 0; + p_dm_fat_table->main_ant_evm_cnt[i] = 0; + p_dm_fat_table->aux_ant_evm_cnt[i] = 0; + /*Reset EVM 2SS Method */ + p_dm_fat_table->main_ant_evm_2ss_sum[i][0] = 0; + p_dm_fat_table->main_ant_evm_2ss_sum[i][1] = 0; + p_dm_fat_table->aux_ant_evm_2ss_sum[i][0] = 0; + p_dm_fat_table->aux_ant_evm_2ss_sum[i][1] = 0; + p_dm_fat_table->main_ant_evm_2ss_cnt[i] = 0; + p_dm_fat_table->aux_ant_evm_2ss_cnt[i] = 0; + #if 0 + /*Reset TP Method */ + p_dm_fat_table->antdiv_tp_main = 0; + p_dm_fat_table->antdiv_tp_aux = 0; + p_dm_fat_table->antdiv_tp_main_cnt = 0; + p_dm_fat_table->antdiv_tp_aux_cnt = 0; + #endif + /*Reset CRC Method */ + p_dm_fat_table->main_crc32_ok_cnt = 0; + p_dm_fat_table->main_crc32_fail_cnt = 0; + p_dm_fat_table->aux_crc32_ok_cnt = 0; + p_dm_fat_table->aux_crc32_fail_cnt = 0; + + #if SKIP_EVM_ANTDIV_TRAINING_PATCH + if ((*p_dm_odm->p_band_width == ODM_BW20M) && (p_entry->rf_mimo_mode == MIMO_2T2R)) { + /*1. Skip training: RSSI*/ + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt)); + curr_rssi = (u8)((p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi); + rssi_diff = (curr_rssi > p_dm_fat_table->pre_antdiv_rssi) ? (curr_rssi - p_dm_fat_table->pre_antdiv_rssi) : (p_dm_fat_table->pre_antdiv_rssi - curr_rssi); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, p_dm_fat_table->pre_antdiv_rssi)); + + p_dm_fat_table->pre_antdiv_rssi = curr_rssi; + if ((rssi_diff < (p_dm_odm->stop_antdiv_rssi_th)) && (curr_rssi != 0)) + rssi_return = 1; + + /*2. Skip training: TP Diff*/ + tp_diff = (p_dm_odm->rx_tp > p_dm_fat_table->pre_antdiv_tp) ? (p_dm_odm->rx_tp - p_dm_fat_table->pre_antdiv_tp) : (p_dm_fat_table->pre_antdiv_tp - p_dm_odm->rx_tp); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", p_dm_odm->rx_tp, p_dm_fat_table->pre_antdiv_tp)); + p_dm_fat_table->pre_antdiv_tp = p_dm_odm->rx_tp; + if ((tp_diff < (u32)(p_dm_odm->stop_antdiv_tp_diff_th) && (p_dm_odm->rx_tp != 0))) + tp_diff_return = 1; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[3] tp_return, curr_rx_tp=((%d))\n", p_dm_odm->rx_tp)); + /*3. Skip training: TP*/ + if (p_dm_odm->rx_tp >= (u32)(p_dm_odm->stop_antdiv_tp_th)) + tp_return = 1; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return)); + /*4. Joint Return Decision*/ + if (tp_return) { + if (tp_diff_return || rssi_diff) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***Return EVM SW AntDiv\n")); + return; + } + } + } + #endif + + p_dm_fat_table->EVM_method_enable = 1; + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + p_dm_odm->antdiv_period = p_dm_odm->evm_antdiv_period; + odm_set_mac_reg(p_dm_odm, 0x608, BIT8, 1); /*RCR accepts CRC32-Error packets*/ + } - else + + + p_dm_fat_table->fat_state_cnt++; + next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + odm_update_rx_idle_ant(p_dm_odm, next_ant); + odm_set_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer, p_dm_odm->antdiv_intvl); //ms + + } + /*Decision state: 4==============================================================*/ + else { + + p_dm_fat_table->fat_state_cnt = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Decisoin state ]\n")); + + /* 3 [CRC32 statistic] */ + #if 0 + if ((p_dm_fat_table->main_crc32_ok_cnt > ((p_dm_fat_table->aux_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == MAIN_ANT))) { + p_dm_fat_table->target_ant_crc32 = MAIN_ANT; + force_antenna = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Main\n")); + } else if ((p_dm_fat_table->aux_crc32_ok_cnt > ((p_dm_fat_table->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) { + p_dm_fat_table->target_ant_crc32 = AUX_ANT; + force_antenna = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Aux\n")); + } else + #endif { - if(pDM_FatTable->MainCRC32_Fail_Cnt<=5) - pDM_FatTable->MainCRC32_Fail_Cnt=5; - - if(pDM_FatTable->AuxCRC32_Fail_Cnt<=5) - pDM_FatTable->AuxCRC32_Fail_Cnt=5; - - if(pDM_FatTable->MainCRC32_Ok_Cnt >pDM_FatTable->MainCRC32_Fail_Cnt ) - Main_above1=TRUE; - - if(pDM_FatTable->AuxCRC32_Ok_Cnt >pDM_FatTable->AuxCRC32_Fail_Cnt ) - Aux_above1=TRUE; - - if(Main_above1==TRUE && Aux_above1==FALSE) - { - Force_antenna=TRUE; - pDM_FatTable->TargetAnt_CRC32=MAIN_ANT; - } - else if(Main_above1==FALSE && Aux_above1==TRUE) - { - Force_antenna=TRUE; - pDM_FatTable->TargetAnt_CRC32=AUX_ANT; - } - else if(Main_above1==TRUE && Aux_above1==TRUE) - { - Main_CRC_utility=((pDM_FatTable->MainCRC32_Ok_Cnt)<<7)/pDM_FatTable->MainCRC32_Fail_Cnt; - Aux_CRC_utility=((pDM_FatTable->AuxCRC32_Ok_Cnt)<<7)/pDM_FatTable->AuxCRC32_Fail_Cnt; - pDM_FatTable->TargetAnt_CRC32 = (Main_CRC_utility==Aux_CRC_utility)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_CRC_utility>=Aux_CRC_utility)?MAIN_ANT:AUX_ANT); - - if(Main_CRC_utility!=0 && Aux_CRC_utility!=0) - { - if(Main_CRC_utility>=Aux_CRC_utility) - utility_ratio=(Main_CRC_utility<<1)/Aux_CRC_utility; + if (p_dm_fat_table->main_crc32_fail_cnt <= 5) + p_dm_fat_table->main_crc32_fail_cnt = 5; + + if (p_dm_fat_table->aux_crc32_fail_cnt <= 5) + p_dm_fat_table->aux_crc32_fail_cnt = 5; + + if (p_dm_fat_table->main_crc32_ok_cnt > p_dm_fat_table->main_crc32_fail_cnt) + main_above1 = true; + + if (p_dm_fat_table->aux_crc32_ok_cnt > p_dm_fat_table->aux_crc32_fail_cnt) + aux_above1 = true; + + if (main_above1 == true && aux_above1 == false) { + force_antenna = true; + p_dm_fat_table->target_ant_crc32 = MAIN_ANT; + } else if (main_above1 == false && aux_above1 == true) { + force_antenna = true; + p_dm_fat_table->target_ant_crc32 = AUX_ANT; + } else if (main_above1 == true && aux_above1 == true) { + main_crc_utility = ((p_dm_fat_table->main_crc32_ok_cnt) << 7) / p_dm_fat_table->main_crc32_fail_cnt; + aux_crc_utility = ((p_dm_fat_table->aux_crc32_ok_cnt) << 7) / p_dm_fat_table->aux_crc32_fail_cnt; + p_dm_fat_table->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT); + + if (main_crc_utility != 0 && aux_crc_utility != 0) { + if (main_crc_utility >= aux_crc_utility) + utility_ratio = (main_crc_utility << 1) / aux_crc_utility; else - utility_ratio=(Aux_CRC_utility<<1)/Main_CRC_utility; + utility_ratio = (aux_crc_utility << 1) / main_crc_utility; } - } - else if(Main_above1==FALSE && Aux_above1==FALSE) - { - if(pDM_FatTable->MainCRC32_Ok_Cnt==0) - pDM_FatTable->MainCRC32_Ok_Cnt=1; - if(pDM_FatTable->AuxCRC32_Ok_Cnt==0) - pDM_FatTable->AuxCRC32_Ok_Cnt=1; - - Main_CRC_utility=((pDM_FatTable->MainCRC32_Fail_Cnt)<<7)/pDM_FatTable->MainCRC32_Ok_Cnt; - Aux_CRC_utility=((pDM_FatTable->AuxCRC32_Fail_Cnt)<<7)/pDM_FatTable->AuxCRC32_Ok_Cnt; - pDM_FatTable->TargetAnt_CRC32 = (Main_CRC_utility==Aux_CRC_utility)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_CRC_utility<=Aux_CRC_utility)?MAIN_ANT:AUX_ANT); - - if(Main_CRC_utility!=0 && Aux_CRC_utility!=0) - { - if(Main_CRC_utility>=Aux_CRC_utility) - utility_ratio=(Main_CRC_utility<<1)/(Aux_CRC_utility); + } else if (main_above1 == false && aux_above1 == false) { + if (p_dm_fat_table->main_crc32_ok_cnt == 0) + p_dm_fat_table->main_crc32_ok_cnt = 1; + if (p_dm_fat_table->aux_crc32_ok_cnt == 0) + p_dm_fat_table->aux_crc32_ok_cnt = 1; + + main_crc_utility = ((p_dm_fat_table->main_crc32_fail_cnt) << 7) / p_dm_fat_table->main_crc32_ok_cnt; + aux_crc_utility = ((p_dm_fat_table->aux_crc32_fail_cnt) << 7) / p_dm_fat_table->aux_crc32_ok_cnt; + p_dm_fat_table->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT); + + if (main_crc_utility != 0 && aux_crc_utility != 0) { + if (main_crc_utility >= aux_crc_utility) + utility_ratio = (main_crc_utility << 1) / (aux_crc_utility); else - utility_ratio=(Aux_CRC_utility<<1)/(Main_CRC_utility); + utility_ratio = (aux_crc_utility << 1) / (main_crc_utility); } } } - ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 0);//NOT Accept CRC32 Error packets. - - //3 [EVM statistic] - Main_EVM = (pDM_FatTable->MainAntEVM_Cnt[i]!=0)?(pDM_FatTable->MainAntEVM_Sum[i]/pDM_FatTable->MainAntEVM_Cnt[i]):0; - Aux_EVM = (pDM_FatTable->AuxAntEVM_Cnt[i]!=0)?(pDM_FatTable->AuxAntEVM_Sum[i]/pDM_FatTable->AuxAntEVM_Cnt[i]):0; - pDM_FatTable->TargetAnt_EVM = (Main_EVM==Aux_EVM)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_EVM>=Aux_EVM)?MAIN_ANT:AUX_ANT); + odm_set_mac_reg(p_dm_odm, 0x608, BIT(8), 0);/* NOT Accept CRC32 Error packets. */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", p_dm_fat_table->main_crc32_ok_cnt, p_dm_fat_table->main_crc32_fail_cnt, main_crc_utility)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", p_dm_fat_table->aux_crc32_ok_cnt, p_dm_fat_table->aux_crc32_fail_cnt, aux_crc_utility)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***1.TargetAnt_CRC32 = ((%s))\n", (p_dm_fat_table->target_ant_crc32 == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + + /* 3 [EVM statistic] */ + /*1SS EVM*/ + main_1ss_evm = (p_dm_fat_table->main_ant_evm_cnt[i] != 0) ? (p_dm_fat_table->main_ant_evm_sum[i] / p_dm_fat_table->main_ant_evm_cnt[i]) : 0; + aux_1ss_evm = (p_dm_fat_table->aux_ant_evm_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_evm_sum[i] / p_dm_fat_table->aux_ant_evm_cnt[i]) : 0; + target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Main1ss_EVM= (( %d ))\n", p_dm_fat_table->main_ant_evm_cnt[i], main_1ss_evm)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Aux_1ss_EVM = (( %d ))\n", p_dm_fat_table->main_ant_evm_cnt[i], aux_1ss_evm)); + + /*2SS EVM*/ + main_2ss_evm[0] = (p_dm_fat_table->main_ant_evm_2ss_cnt[i] != 0) ? (p_dm_fat_table->main_ant_evm_2ss_sum[i][0] / p_dm_fat_table->main_ant_evm_2ss_cnt[i]) : 0; + main_2ss_evm[1] = (p_dm_fat_table->main_ant_evm_2ss_cnt[i] != 0) ? (p_dm_fat_table->main_ant_evm_2ss_sum[i][1] / p_dm_fat_table->main_ant_evm_2ss_cnt[i]) : 0; + main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1]; + + aux_2ss_evm[0] = (p_dm_fat_table->aux_ant_evm_2ss_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_evm_2ss_sum[i][0] / p_dm_fat_table->aux_ant_evm_2ss_cnt[i]) : 0; + aux_2ss_evm[1] = (p_dm_fat_table->aux_ant_evm_2ss_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_evm_2ss_sum[i][1] / p_dm_fat_table->aux_ant_evm_2ss_cnt[i]) : 0; + aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1]; + + target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", + p_dm_fat_table->main_ant_evm_2ss_cnt[i], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", + p_dm_fat_table->aux_ant_evm_2ss_cnt[i], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum)); + + if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) { + decision_evm_ss = 2; + main_evm = main_2ss_evm_sum; + aux_evm = aux_2ss_evm_sum; + p_dm_fat_table->target_ant_evm = target_ant_evm_2ss; + } else { + decision_evm_ss = 1; + main_evm = main_1ss_evm; + aux_evm = aux_1ss_evm; + p_dm_fat_table->target_ant_evm = target_ant_evm_1ss; + } - if((Main_EVM==0 || Aux_EVM==0)) - diff_EVM=0; - else if(Main_EVM>=Aux_EVM) - diff_EVM=Main_EVM-Aux_EVM; + if ((main_evm == 0 || aux_evm == 0)) + diff_EVM = 100; + else if (main_evm >= aux_evm) + diff_EVM = main_evm - aux_evm; else - diff_EVM=Aux_EVM-Main_EVM; - - //2 [ Decision state ] - if (pDM_FatTable->TargetAnt_EVM == pDM_FatTable->TargetAnt_CRC32) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - - if ((utility_ratio < 2 && Force_antenna == FALSE) && diff_EVM <= 30) - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->pre_TargetAnt_enhance; + diff_EVM = aux_evm - main_evm; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (p_dm_fat_table->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + + + //3 [TP statistic] + antdiv_tp_main_avg = (p_dm_fat_table->antdiv_tp_main_cnt != 0) ? (p_dm_fat_table->antdiv_tp_main / p_dm_fat_table->antdiv_tp_main_cnt) : 0; + antdiv_tp_aux_avg = (p_dm_fat_table->antdiv_tp_aux_cnt != 0) ? (p_dm_fat_table->antdiv_tp_aux / p_dm_fat_table->antdiv_tp_aux_cnt) : 0; + p_dm_fat_table->target_ant_tp = (antdiv_tp_main_avg == antdiv_tp_aux_avg) ? (p_dm_fat_table->pre_target_ant_enhance) : ((antdiv_tp_main_avg >= antdiv_tp_aux_avg) ? MAIN_ANT : AUX_ANT); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Main_TP = ((%d))\n", p_dm_fat_table->antdiv_tp_main_cnt, antdiv_tp_main_avg)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Aux_TP = ((%d))\n", p_dm_fat_table->antdiv_tp_aux_cnt, antdiv_tp_aux_avg)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***3.TargetAnt_TP = ((%s))\n", (p_dm_fat_table->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + + /*Reset TP Method */ + p_dm_fat_table->antdiv_tp_main = 0; + p_dm_fat_table->antdiv_tp_aux = 0; + p_dm_fat_table->antdiv_tp_main_cnt = 0; + p_dm_fat_table->antdiv_tp_aux_cnt = 0; + + /* 2 [ Decision state ] */ + if (p_dm_fat_table->target_ant_evm == p_dm_fat_table->target_ant_crc32) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + + if ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30) + p_dm_fat_table->target_ant_enhance = p_dm_fat_table->pre_target_ant_enhance; else - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_EVM; - } else if ((diff_EVM <= 50 && (utility_ratio > 4 && Force_antenna == FALSE)) || (Force_antenna == TRUE)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_CRC32; - } else if (diff_EVM >= 100) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_EVM; - } else if (utility_ratio >= 6 && Force_antenna == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_CRC32; + p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_evm; + } + #if 0 + else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_crc32; + } + #endif + else if (diff_EVM >= 20) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_evm; + } else if (utility_ratio >= 6 && force_antenna == false) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_crc32; } else { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - - if (Force_antenna == TRUE) - score_CRC = 3; - else if (utility_ratio >= 3) /*>0.5*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + + if (force_antenna == true) + score_CRC = 2; + else if (utility_ratio >= 5) /*>2.5*/ score_CRC = 2; - else if (utility_ratio >= 2) /*>1*/ + else if (utility_ratio >= 4) /*>2*/ score_CRC = 1; else score_CRC = 0; - - if (diff_EVM >= 100) + + if (diff_EVM >= 15) + score_EVM = 3; + else if (diff_EVM >= 10) score_EVM = 2; - else if (diff_EVM >= 50) + else if (diff_EVM >= 5) score_EVM = 1; else score_EVM = 0; if (score_CRC > score_EVM) - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_CRC32; + p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_crc32; else if (score_CRC < score_EVM) - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_EVM; + p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_evm; else - pDM_FatTable->TargetAnt_enhance = pDM_FatTable->pre_TargetAnt_enhance; - } - pDM_FatTable->pre_TargetAnt_enhance=pDM_FatTable->TargetAnt_enhance; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MainEVM_Cnt = (( %d )) , Main_EVM= (( %d )) \n",i, pDM_FatTable->MainAntEVM_Cnt[i], Main_EVM)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : AuxEVM_Cnt = (( %d )) , Aux_EVM = (( %d )) \n" ,i, pDM_FatTable->AuxAntEVM_Cnt[i] , Aux_EVM)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** TargetAnt_EVM = (( %s ))\n", ( pDM_FatTable->TargetAnt_EVM ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("M_CRC_Ok = (( %d )) , M_CRC_Fail = (( %d )), Main_CRC_utility = (( %d )) \n" , pDM_FatTable->MainCRC32_Ok_Cnt, pDM_FatTable->MainCRC32_Fail_Cnt,Main_CRC_utility)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("A_CRC_Ok = (( %d )) , A_CRC_Fail = (( %d )), Aux_CRC_utility = (( %d )) \n" , pDM_FatTable->AuxCRC32_Ok_Cnt, pDM_FatTable->AuxCRC32_Fail_Cnt,Aux_CRC_utility)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** TargetAnt_CRC32 = (( %s ))\n", ( pDM_FatTable->TargetAnt_CRC32 ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("****** TargetAnt_enhance = (( %s ))******\n", ( pDM_FatTable->TargetAnt_enhance ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - - + p_dm_fat_table->target_ant_enhance = p_dm_fat_table->pre_target_ant_enhance; + } + p_dm_fat_table->pre_target_ant_enhance = p_dm_fat_table->target_ant_enhance; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** 4.TargetAnt_enhance = (( %s ))******\n", (p_dm_fat_table->target_ant_enhance == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + + } + } else { /* RSSI< = evm_rssi_th_low */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ TH_L ]\n")); + odm_evm_fast_ant_reset(p_dm_odm); } - else // RSSI< = Evm_RSSI_TH_Low - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ TH_L ] \n")); - odm_EVM_FastAnt_Reset(pDM_Odm); - } - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[escape from> TH_H || EVM_method_enable==1] \n")); - odm_EVM_FastAnt_Reset(pDM_Odm); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[escape from> TH_H || EVM_method_enable==1]\n")); + odm_evm_fast_ant_reset(p_dm_odm); } + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[multi-Client]\n")); + odm_evm_fast_ant_reset(p_dm_odm); } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[multi-Client] \n")); - odm_EVM_FastAnt_Reset(pDM_Odm); - } } } -VOID -odm_EVM_FastAntTrainingCallback( - IN PVOID pDM_VOID - ) +void +odm_evm_fast_ant_training_callback( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_EVM_FastAntTrainingCallback****** \n")); - odm_HW_AntDiv(pDM_Odm); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******AntDiv_Callback******\n")); + odm_hw_ant_div(p_dm_odm); } #endif -VOID -odm_HW_AntDiv( - IN PVOID pDM_VOID - ) +void +odm_hw_ant_div( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte i,MinMaxRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMaxRSSI; - u4Byte Main_RSSI, Aux_RSSI; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u1Byte RxIdleAnt = pDM_FatTable->RxIdleAnt, TargetAnt = 7; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - PSTA_INFO_T pEntry; - - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; - u4Byte TH1=500000; - u4Byte TH2=10000000; - u4Byte MA_rx_Temp, degrade_TP_temp, improve_TP_temp; - u1Byte Monitor_RSSI_threshold=30; - - pDM_BdcTable->BF_pass=TRUE; - pDM_BdcTable->DIV_pass=TRUE; - pDM_BdcTable->bAll_DivSta_Idle=TRUE; - pDM_BdcTable->bAll_BFSta_Idle=TRUE; - pDM_BdcTable->num_BfTar=0 ; - pDM_BdcTable->num_DivTar=0; - pDM_BdcTable->num_Client=0; - #endif - #endif + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0, local_max_rssi; + u32 main_rssi, aux_rssi, mian_cnt, aux_cnt; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + u8 rx_idle_ant = p_dm_fat_table->rx_idle_ant, target_ant = 7; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct sta_info *p_entry; + +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; + u32 TH1 = 500000; + u32 TH2 = 10000000; + u32 ma_rx_temp, degrade_TP_temp, improve_TP_temp; + u8 monitor_rssi_threshold = 30; + + p_dm_bdc_table->BF_pass = true; + p_dm_bdc_table->DIV_pass = true; + p_dm_bdc_table->is_all_div_sta_idle = true; + p_dm_bdc_table->is_all_bf_sta_idle = true; + p_dm_bdc_table->num_bf_tar = 0 ; + p_dm_bdc_table->num_div_tar = 0; + p_dm_bdc_table->num_client = 0; +#endif +#endif - if(!pDM_Odm->bLinked) //bLinked==False - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - - if(pDM_FatTable->bBecomeLinked == TRUE) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - pDM_Odm->antdiv_period=0; + if (!p_dm_odm->is_linked) { /* is_linked==False */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + if (p_dm_fat_table->is_become_linked == true) { + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + p_dm_odm->antdiv_period = 0; + + p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; } return; - } - else - { - if(pDM_FatTable->bBecomeLinked ==FALSE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); - /*odm_Tx_By_TxDesc_or_Reg(pDM_Odm , TX_BY_DESC);*/ - - //if(pDM_Odm->SupportICType == ODM_RTL8821 ) - //ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable - - //#if(DM_ODM_SUPPORT_TYPE == ODM_AP) - //else if(pDM_Odm->SupportICType == ODM_RTL8881A) - // ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable - //#endif - - //else if(pDM_Odm->SupportICType == ODM_RTL8723B ||pDM_Odm->SupportICType == ODM_RTL8812) - //ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function disable - - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } else { + if (p_dm_fat_table->is_become_linked == false) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); + odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); + /*odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC);*/ - if(pDM_Odm->SupportICType==ODM_RTL8723B && pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - { - ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0] // for 8723B AntDiv function patch. BB Dino 130412 - ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0] + /* if(p_dm_odm->support_ic_type == ODM_RTL8821 ) */ + /* odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); */ /* CCK AntDiv function disable */ + + /* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ + /* else if(p_dm_odm->support_ic_type == ODM_RTL8881A) */ + /* odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); */ /* CCK AntDiv function disable */ + /* #endif */ + + /* else if(p_dm_odm->support_ic_type == ODM_RTL8723B ||p_dm_odm->support_ic_type == ODM_RTL8812) */ + /* odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); */ /* CCK AntDiv function disable */ + + p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + + if (p_dm_odm->support_ic_type == ODM_RTL8723B && p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_set_bb_reg(p_dm_odm, 0x930, 0xF0, 8); /* DPDT_P = ANTSEL[0] */ /* for 8723B AntDiv function patch. BB Dino 130412 */ + odm_set_bb_reg(p_dm_odm, 0x930, 0xF, 8); /* DPDT_N = ANTSEL[0] */ } - - //2 BDC Init - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - odm_BDC_Init(pDM_Odm); - #endif - #endif - - #ifdef ODM_EVM_ENHANCE_ANTDIV - odm_EVM_FastAnt_Reset(pDM_Odm); - #endif - } - } - if (*(pDM_FatTable->pForceTxAntByDesc) == FALSE) { - if (pDM_Odm->bOneEntryOnly == TRUE) - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - else - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + /* 2 BDC Init */ +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + odm_bdc_init(p_dm_odm); +#endif +#endif + +#ifdef ODM_EVM_ENHANCE_ANTDIV + odm_evm_fast_ant_reset(p_dm_odm); +#endif + } } - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n AntDiv Start =>\n")); + if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) { + if (p_dm_odm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + else + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); + } - #ifdef ODM_EVM_ENHANCE_ANTDIV - if(pDM_Odm->antdiv_evm_en==1) - { - odm_EVM_Enhance_AntDiv(pDM_Odm); - if(pDM_FatTable->FAT_State !=NORMAL_STATE_MIAN) +#ifdef ODM_EVM_ENHANCE_ANTDIV + if (p_dm_odm->antdiv_evm_en == 1) { + odm_evm_enhance_ant_div(p_dm_odm); + if (p_dm_fat_table->fat_state_cnt != 0) return; - } - else - { - odm_EVM_FastAnt_Reset(pDM_Odm); - } - #endif - - //2 BDC Mode Arbitration - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - if(pDM_Odm->antdiv_evm_en == 0 ||pDM_FatTable->EVM_method_enable==0) - { - odm_BF_AntDiv_ModeArbitration(pDM_Odm); - } - #endif - #endif + } else + odm_evm_fast_ant_reset(p_dm_odm); +#endif - for (i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pEntry)) - { - //2 Caculate RSSI per Antenna - Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; - Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; - TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_FatTable->RxIdleAnt:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT); - - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** SupportICType=[%d] \n",pDM_Odm->SupportICType)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n",i, pDM_FatTable->MainAnt_Cnt[i], Main_RSSI)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n" ,i, pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI)); - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2, - // ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0))); - - LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI; - //2 Select MaxRSSI for DIG - if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40)) - AntDivMaxRSSI = LocalMaxRSSI; - if(LocalMaxRSSI > MaxRSSI) - MaxRSSI = LocalMaxRSSI; - - //2 Select RX Idle Antenna - if ( (LocalMaxRSSI != 0) && (LocalMaxRSSI < MinMaxRSSI) ) - { - RxIdleAnt = TargetAnt; - MinMaxRSSI = LocalMaxRSSI; + /* 2 BDC mode Arbitration */ +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (p_dm_odm->antdiv_evm_en == 0 || p_dm_fat_table->EVM_method_enable == 0) + odm_bf_ant_div_mode_arbitration(p_dm_odm); +#endif +#endif + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + p_entry = p_dm_odm->p_odm_sta_info[i]; + if (IS_STA_VALID(p_entry)) { + /* 2 Caculate RSSI per Antenna */ + if ((p_dm_fat_table->main_ant_cnt[i] != 0) || (p_dm_fat_table->aux_ant_cnt[i] != 0)) { + mian_cnt = p_dm_fat_table->main_ant_cnt[i]; + aux_cnt = p_dm_fat_table->aux_ant_cnt[i]; + main_rssi = (mian_cnt != 0) ? (p_dm_fat_table->main_ant_sum[i] / mian_cnt) : 0; + aux_rssi = (aux_cnt != 0) ? (p_dm_fat_table->aux_ant_sum[i] / aux_cnt) : 0; + target_ant = (mian_cnt == aux_cnt) ? p_dm_fat_table->rx_idle_ant : ((mian_cnt >= aux_cnt) ? MAIN_ANT : AUX_ANT); /*Use counter number for OFDM*/ + + } else { /*CCK only case*/ + mian_cnt = p_dm_fat_table->main_ant_cnt_cck[i]; + aux_cnt = p_dm_fat_table->aux_ant_cnt_cck[i]; + main_rssi = (mian_cnt != 0) ? (p_dm_fat_table->main_ant_sum_cck[i] / mian_cnt) : 0; + aux_rssi = (aux_cnt != 0) ? (p_dm_fat_table->aux_ant_sum_cck[i] / aux_cnt) : 0; + target_ant = (main_rssi == aux_rssi) ? p_dm_fat_table->rx_idle_ant : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); /*Use RSSI for CCK only case*/ } - #ifdef ODM_EVM_ENHANCE_ANTDIV - if(pDM_Odm->antdiv_evm_en==1) - { - if(pDM_FatTable->TargetAnt_enhance!=0xFF) - { - TargetAnt=pDM_FatTable->TargetAnt_enhance; - RxIdleAnt = pDM_FatTable->TargetAnt_enhance; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Main_Cnt = (( %d )) , CCK_Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", i, p_dm_fat_table->main_ant_cnt[i], p_dm_fat_table->main_ant_cnt_cck[i], main_rssi)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Aux_Cnt = (( %d )) , CCK_Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", i, p_dm_fat_table->aux_ant_cnt[i], p_dm_fat_table->aux_ant_cnt_cck[i], aux_rssi)); + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i ,( target_ant ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); */ + + local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi; + /* 2 Select max_rssi for DIG */ + if ((local_max_rssi > ant_div_max_rssi) && (local_max_rssi < 40)) + ant_div_max_rssi = local_max_rssi; + if (local_max_rssi > max_rssi) + max_rssi = local_max_rssi; + + /* 2 Select RX Idle Antenna */ + if ((local_max_rssi != 0) && (local_max_rssi < min_max_rssi)) { + rx_idle_ant = target_ant; + min_max_rssi = local_max_rssi; + } + +#ifdef ODM_EVM_ENHANCE_ANTDIV + if (p_dm_odm->antdiv_evm_en == 1) { + if (p_dm_fat_table->target_ant_enhance != 0xFF) { + target_ant = p_dm_fat_table->target_ant_enhance; + rx_idle_ant = p_dm_fat_table->target_ant_enhance; } } - #endif +#endif - //2 Select TX Antenna - if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) - { - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - if(pDM_BdcTable->w_BFee_Client[i]==0) - #endif - #endif - { - odm_UpdateTxAnt(pDM_Odm, TargetAnt, i); - } + /* 2 Select TX Antenna */ + if (p_dm_odm->ant_div_type != CGCS_RX_HW_ANTDIV) { +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (p_dm_bdc_table->w_bfee_client[i] == 0) +#endif +#endif + { + odm_update_tx_ant(p_dm_odm, target_ant, i); + } } - //------------------------------------------------------------ + /* ------------------------------------------------------------ */ - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - pDM_BdcTable->num_Client++; + p_dm_bdc_table->num_client++; - if(pDM_BdcTable->BDC_Mode==BDC_MODE_2 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3) - { - //2 Byte Counter + if (p_dm_bdc_table->bdc_mode == BDC_MODE_2 || p_dm_bdc_table->bdc_mode == BDC_MODE_3) { + /* 2 Byte counter */ - MA_rx_Temp= (pEntry->rx_byte_cnt_LowMAW)<<3 ; // RX TP ( bit /sec) - - if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) - { - pDM_BdcTable->MA_rx_TP_DIV[i]= MA_rx_Temp ; - } + ma_rx_temp = (p_entry->rx_byte_cnt_low_maw) << 3 ; /* RX TP ( bit /sec) */ + + if (p_dm_bdc_table->BDC_state == bdc_bfer_train_state) + p_dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp ; else - { - pDM_BdcTable->MA_rx_TP[i] =MA_rx_Temp ; - } + p_dm_bdc_table->MA_rx_TP[i] = ma_rx_temp ; - if( (MA_rx_Temp < TH2) && (MA_rx_Temp > TH1) && (LocalMaxRSSI<=Monitor_RSSI_threshold)) - { - if(pDM_BdcTable->w_BFer_Client[i]==1) // Bfer_Target - { - pDM_BdcTable->num_BfTar++; - - if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE && pDM_BdcTable->BDC_Try_flag==0) - { - improve_TP_temp = (pDM_BdcTable->MA_rx_TP_DIV[i] * 9)>>3 ; //* 1.125 - pDM_BdcTable->BF_pass = (pDM_BdcTable->MA_rx_TP[i] > improve_TP_temp)?TRUE:FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP,improve_TP_temp , MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d } \n" ,i,pDM_BdcTable->MA_rx_TP[i],improve_TP_temp,pDM_BdcTable->MA_rx_TP_DIV[i], pDM_BdcTable->BF_pass )); - } - } - else// DIV_Target - { - pDM_BdcTable->num_DivTar++; - - if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE && pDM_BdcTable->BDC_Try_flag==0) - { - degrade_TP_temp=(pDM_BdcTable->MA_rx_TP_DIV[i]*5)>>3;//* 0.625 - pDM_BdcTable->DIV_pass = (pDM_BdcTable->MA_rx_TP[i] >degrade_TP_temp)?TRUE:FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp , MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d } \n" ,i,pDM_BdcTable->MA_rx_TP[i],degrade_TP_temp,pDM_BdcTable->MA_rx_TP_DIV[i], pDM_BdcTable->DIV_pass )); - } - } - } + if ((ma_rx_temp < TH2) && (ma_rx_temp > TH1) && (local_max_rssi <= monitor_rssi_threshold)) { + if (p_dm_bdc_table->w_bfer_client[i] == 1) { /* Bfer_Target */ + p_dm_bdc_table->num_bf_tar++; - if(MA_rx_Temp > TH1) - { - if(pDM_BdcTable->w_BFer_Client[i]==1) // Bfer_Target - { - pDM_BdcTable->bAll_BFSta_Idle=FALSE; - } - else// DIV_Target - { - pDM_BdcTable->bAll_DivSta_Idle=FALSE; + if (p_dm_bdc_table->BDC_state == BDC_DECISION_STATE && p_dm_bdc_table->bdc_try_flag == 0) { + improve_TP_temp = (p_dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3 ; /* * 1.125 */ + p_dm_bdc_table->BF_pass = (p_dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d }\n", i, p_dm_bdc_table->MA_rx_TP[i], improve_TP_temp, p_dm_bdc_table->MA_rx_TP_DIV[i], p_dm_bdc_table->BF_pass)); + } + } else { /* DIV_Target */ + p_dm_bdc_table->num_div_tar++; + + if (p_dm_bdc_table->BDC_state == BDC_DECISION_STATE && p_dm_bdc_table->bdc_try_flag == 0) { + degrade_TP_temp = (p_dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* * 0.625 */ + p_dm_bdc_table->DIV_pass = (p_dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d }\n", i, p_dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, p_dm_bdc_table->MA_rx_TP_DIV[i], p_dm_bdc_table->DIV_pass)); + } } } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { BFmeeCap , BFmerCap} = { %d , %d } \n" ,i, pDM_BdcTable->w_BFee_Client[i] , pDM_BdcTable->w_BFer_Client[i])); - if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP_DIV = (( %d )) \n",i,pDM_BdcTable->MA_rx_TP_DIV[i] )); - + if (ma_rx_temp > TH1) { + if (p_dm_bdc_table->w_bfer_client[i] == 1) /* Bfer_Target */ + p_dm_bdc_table->is_all_bf_sta_idle = false; + else/* DIV_Target */ + p_dm_bdc_table->is_all_div_sta_idle = false; } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { BFmeeCap, BFmerCap} = { %d , %d }\n", i, p_dm_bdc_table->w_bfee_client[i], p_dm_bdc_table->w_bfer_client[i])); + + if (p_dm_bdc_table->BDC_state == bdc_bfer_train_state) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP_DIV = (( %d ))\n", i, p_dm_bdc_table->MA_rx_TP_DIV[i])); + else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP = (( %d )) \n",i,pDM_BdcTable->MA_rx_TP[i] )); - } - + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP = (( %d ))\n", i, p_dm_bdc_table->MA_rx_TP[i])); + } - #endif - #endif +#endif +#endif } - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - if(pDM_BdcTable->BDC_Try_flag==0) - #endif - #endif +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (p_dm_bdc_table->bdc_try_flag == 0) +#endif +#endif { - pDM_FatTable->MainAnt_Sum[i] = 0; - pDM_FatTable->AuxAnt_Sum[i] = 0; - pDM_FatTable->MainAnt_Cnt[i] = 0; - pDM_FatTable->AuxAnt_Cnt[i] = 0; - } + phydm_antdiv_reset_statistic(p_dm_odm, i); + } } - - - //2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP ) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** RxIdleAnt = (( %s ))\n\n", ( RxIdleAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - if(pDM_BdcTable->BDC_Mode==BDC_MODE_1 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** BDC_RxIdleUpdate_counter = (( %d ))\n", pDM_BdcTable->BDC_RxIdleUpdate_counter)); - - if(pDM_BdcTable->BDC_RxIdleUpdate_counter==1) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***Update RxIdle Antenna!!! \n")); - pDM_BdcTable->BDC_RxIdleUpdate_counter=30; - ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); - } - else - { - pDM_BdcTable->BDC_RxIdleUpdate_counter--; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n")); - } - } - else - #endif - #endif - ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); - #else - - ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); - - #endif//#if(DM_ODM_SUPPORT_TYPE == ODM_AP) + /* 2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** rx_idle_ant = (( %s ))\n", (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - //2 BDC Main Algorithm - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - if(pDM_Odm->antdiv_evm_en ==0 ||pDM_FatTable->EVM_method_enable==0) - { - odm_BDCcoex_BFeeRxDiv_Arbitration(pDM_Odm); - } - #endif - #endif +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (p_dm_bdc_table->bdc_mode == BDC_MODE_1 || p_dm_bdc_table->bdc_mode == BDC_MODE_3) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** bdc_rx_idle_update_counter = (( %d ))\n", p_dm_bdc_table->bdc_rx_idle_update_counter)); - if(AntDivMaxRSSI == 0) - pDM_DigTable->AntDiv_RSSI_max = pDM_Odm->RSSI_Min; - else - pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI; - - pDM_DigTable->RSSI_max = MaxRSSI; + if (p_dm_bdc_table->bdc_rx_idle_update_counter == 1) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***Update RxIdle Antenna!!!\n")); + p_dm_bdc_table->bdc_rx_idle_update_counter = 30; + odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); + } else { + p_dm_bdc_table->bdc_rx_idle_update_counter--; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n")); + } + } else +#endif +#endif + odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); +#else + + odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); + +#endif/* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ + + + + /* 2 BDC Main Algorithm */ +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (p_dm_odm->antdiv_evm_en == 0 || p_dm_fat_table->EVM_method_enable == 0) + odm_bd_ccoex_bfee_rx_div_arbitration(p_dm_odm); +#endif +#endif + + if (ant_div_max_rssi == 0) + p_dm_dig_table->ant_div_rssi_max = p_dm_odm->rssi_min; + else + p_dm_dig_table->ant_div_rssi_max = ant_div_max_rssi; + + p_dm_dig_table->RSSI_max = max_rssi; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***AntDiv End***\n\n")); } #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY -VOID -odm_S0S1_SWAntDiv_Reset( - IN PVOID pDM_VOID +void +odm_s0s1_sw_ant_div_reset( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - pDM_FatTable->bBecomeLinked = FALSE; - pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; - pDM_SWAT_Table->Double_chk_flag = 0; + p_dm_fat_table->is_become_linked = false; + p_dm_swat_table->try_flag = SWAW_STEP_INIT; + p_dm_swat_table->double_chk_flag = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SWAntDiv_Reset(): pDM_FatTable->bBecomeLinked = %d\n", pDM_FatTable->bBecomeLinked)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_s0s1_sw_ant_div_reset(): p_dm_fat_table->is_become_linked = %d\n", p_dm_fat_table->is_become_linked)); } -VOID -odm_S0S1_SwAntDiv( - IN PVOID pDM_VOID, - IN u1Byte Step - ) +void +odm_s0s1_sw_ant_div( + void *p_dm_void, + u8 step +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - u4Byte i, MinMaxRSSI = 0xFF, LocalMaxRSSI, LocalMinRSSI; - u4Byte Main_RSSI, Aux_RSSI; - u1Byte HighTraffic_TrainTime_U = 0x32, HighTraffic_TrainTime_L = 0, Train_time_temp; - u1Byte LowTraffic_TrainTime_U = 200, LowTraffic_TrainTime_L = 0; - u1Byte RxIdleAnt = pDM_SWAT_Table->PreAntenna, TargetAnt, nextAnt = 0; - PSTA_INFO_T pEntry = NULL; - u4Byte value32; - - - if(!pDM_Odm->bLinked) //bLinked==False - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - if(pDM_FatTable->bBecomeLinked == TRUE) - { - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - if (pDM_Odm->SupportICType == ODM_RTL8723B) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); - ODM_SetBBReg(pDM_Odm, 0x948 , (BIT9|BIT8|BIT7|BIT6), 0x0); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + u32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi; + u32 main_rssi, aux_rssi; + u8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0, train_time_temp; + u8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0; + u8 rx_idle_ant = p_dm_swat_table->pre_antenna, target_ant, next_ant = 0; + struct sta_info *p_entry = NULL; + u32 value32; + u32 main_ant_sum; + u32 aux_ant_sum; + u32 main_ant_cnt; + u32 aux_ant_cnt; + + + if (!p_dm_odm->is_linked) { /* is_linked==False */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + if (p_dm_fat_table->is_become_linked == true) { + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); + odm_set_bb_reg(p_dm_odm, 0x948, (BIT(9) | BIT(8) | BIT(7) | BIT(6)), 0x0); } - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; } return; - } - else - { - if(pDM_FatTable->bBecomeLinked ==FALSE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); - - if(pDM_Odm->SupportICType == ODM_RTL8723B) - { - value32 = ODM_GetBBReg(pDM_Odm, 0x864, BIT5|BIT4|BIT3); + } else { + if (p_dm_fat_table->is_become_linked == false) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); - #if (RTL8723B_SUPPORT == 1) - if (value32 == 0x0) - ODM_UpdateRxIdleAnt_8723B(pDM_Odm, MAIN_ANT, ANT1_2G, ANT2_2G); - else if (value32 == 0x1) - ODM_UpdateRxIdleAnt_8723B(pDM_Odm, AUX_ANT, ANT2_2G, ANT1_2G); - #endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B: First link! Force antenna to %s\n",(value32 == 0x0?"MAIN":"AUX") )); - } - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + value32 = odm_get_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT(4) | BIT(3)); + +#if (RTL8723B_SUPPORT == 1) + if (value32 == 0x0) + odm_update_rx_idle_ant_8723b(p_dm_odm, MAIN_ANT, ANT1_2G, ANT2_2G); + else if (value32 == 0x1) + odm_update_rx_idle_ant_8723b(p_dm_odm, AUX_ANT, ANT2_2G, ANT1_2G); +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B: First link! Force antenna to %s\n", (value32 == 0x0 ? "MAIN" : "AUX"))); + } + p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; } } - if (*(pDM_FatTable->pForceTxAntByDesc) == FALSE) { - if (pDM_Odm->bOneEntryOnly == TRUE) - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) { + if (p_dm_odm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); else - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[%d] { try_flag=(( %d )), Step=(( %d )), Double_chk_flag = (( %d )) }\n", - __LINE__,pDM_SWAT_Table->try_flag,Step,pDM_SWAT_Table->Double_chk_flag)); - // Handling step mismatch condition. - // Peak step is not finished at last time. Recover the variable and check again. - if( Step != pDM_SWAT_Table->try_flag ) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Step != try_flag] Need to Reset After Link\n")); - ODM_SwAntDivRestAfterLink(pDM_Odm); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n", + __LINE__, p_dm_swat_table->try_flag, step, p_dm_swat_table->double_chk_flag)); + + /* Handling step mismatch condition. */ + /* Peak step is not finished at last time. Recover the variable and check again. */ + if (step != p_dm_swat_table->try_flag) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[step != try_flag] Need to Reset After Link\n")); + odm_sw_ant_div_rest_after_link(p_dm_odm); } - if (pDM_SWAT_Table->try_flag == SWAW_STEP_INIT) { - - pDM_SWAT_Table->try_flag = SWAW_STEP_PEEK; - pDM_SWAT_Table->Train_time_flag=0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag = 0] Prepare for peek!\n\n")); + if (p_dm_swat_table->try_flag == SWAW_STEP_INIT) { + + p_dm_swat_table->try_flag = SWAW_STEP_PEEK; + p_dm_swat_table->train_time_flag = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag = 0] Prepare for peek!\n\n")); return; - + } else { - - //1 Normal State (Begin Trying) - if (pDM_SWAT_Table->try_flag == SWAW_STEP_PEEK) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), TrafficLoad = (%d))\n", pDM_Odm->curTxOkCnt, pDM_Odm->curRxOkCnt, pDM_Odm->TrafficLoad)); - - if (pDM_Odm->TrafficLoad == TRAFFIC_HIGH) - { - Train_time_temp = pDM_SWAT_Table->Train_time ; - - if(pDM_SWAT_Table->Train_time_flag==3) - { - HighTraffic_TrainTime_L=0xa; - - if(Train_time_temp<=16) - Train_time_temp=HighTraffic_TrainTime_L; + + /* 1 Normal state (Begin Trying) */ + if (p_dm_swat_table->try_flag == SWAW_STEP_PEEK) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n", p_dm_odm->cur_tx_ok_cnt, p_dm_odm->cur_rx_ok_cnt, p_dm_odm->traffic_load)); + + if (p_dm_odm->traffic_load == TRAFFIC_HIGH) { + train_time_temp = p_dm_swat_table->train_time ; + + if (p_dm_swat_table->train_time_flag == 3) { + high_traffic_train_time_l = 0xa; + + if (train_time_temp <= 16) + train_time_temp = high_traffic_train_time_l; else - Train_time_temp-=16; - - } - else if(pDM_SWAT_Table->Train_time_flag==2) - { - Train_time_temp-=8; - HighTraffic_TrainTime_L=0xf; - } - else if(pDM_SWAT_Table->Train_time_flag==1) - { - Train_time_temp-=4; - HighTraffic_TrainTime_L=0x1e; + train_time_temp -= 16; + + } else if (p_dm_swat_table->train_time_flag == 2) { + train_time_temp -= 8; + high_traffic_train_time_l = 0xf; + } else if (p_dm_swat_table->train_time_flag == 1) { + train_time_temp -= 4; + high_traffic_train_time_l = 0x1e; + } else if (p_dm_swat_table->train_time_flag == 0) { + train_time_temp += 8; + high_traffic_train_time_l = 0x28; } - else if(pDM_SWAT_Table->Train_time_flag==0) - { - Train_time_temp+=8; - HighTraffic_TrainTime_L=0x28; + + if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + high_traffic_train_time_l += 0xa; } - - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Train_time_temp = ((%d))\n",Train_time_temp)); + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** train_time_temp = ((%d))\n",train_time_temp)); */ - //-- - if(Train_time_temp > HighTraffic_TrainTime_U) - Train_time_temp=HighTraffic_TrainTime_U; - - else if(Train_time_temp < HighTraffic_TrainTime_L) - Train_time_temp=HighTraffic_TrainTime_L; + /* -- */ + if (train_time_temp > high_traffic_train_time_u) + train_time_temp = high_traffic_train_time_u; - pDM_SWAT_Table->Train_time = Train_time_temp; /*10ms~200ms*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Train_time_flag=((%d)), Train_time=((%d))\n", pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time)); + else if (train_time_temp < high_traffic_train_time_l) + train_time_temp = high_traffic_train_time_l; - } else if ((pDM_Odm->TrafficLoad == TRAFFIC_MID) || (pDM_Odm->TrafficLoad == TRAFFIC_LOW)) { - - Train_time_temp=pDM_SWAT_Table->Train_time ; - - if(pDM_SWAT_Table->Train_time_flag==3) - { - LowTraffic_TrainTime_L=10; - if(Train_time_temp<50) - Train_time_temp=LowTraffic_TrainTime_L; + p_dm_swat_table->train_time = train_time_temp; /*10ms~200ms*/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("train_time_flag=((%d)), train_time=((%d))\n", p_dm_swat_table->train_time_flag, p_dm_swat_table->train_time)); + + } else if ((p_dm_odm->traffic_load == TRAFFIC_MID) || (p_dm_odm->traffic_load == TRAFFIC_LOW)) { + + train_time_temp = p_dm_swat_table->train_time ; + + if (p_dm_swat_table->train_time_flag == 3) { + low_traffic_train_time_l = 10; + if (train_time_temp < 50) + train_time_temp = low_traffic_train_time_l; else - Train_time_temp-=50; - } - else if(pDM_SWAT_Table->Train_time_flag==2) - { - Train_time_temp-=30; - LowTraffic_TrainTime_L=36; - } - else if(pDM_SWAT_Table->Train_time_flag==1) - { - Train_time_temp-=10; - LowTraffic_TrainTime_L=40; + train_time_temp -= 50; + } else if (p_dm_swat_table->train_time_flag == 2) { + train_time_temp -= 30; + low_traffic_train_time_l = 36; + } else if (p_dm_swat_table->train_time_flag == 1) { + train_time_temp -= 10; + low_traffic_train_time_l = 40; } else { - - Train_time_temp += 10; - LowTraffic_TrainTime_L = 50; + + train_time_temp += 10; + low_traffic_train_time_l = 50; } - - //-- - if(Train_time_temp >= LowTraffic_TrainTime_U) - Train_time_temp=LowTraffic_TrainTime_U; - - else if(Train_time_temp <= LowTraffic_TrainTime_L) - Train_time_temp=LowTraffic_TrainTime_L; - pDM_SWAT_Table->Train_time = Train_time_temp; /*10ms~200ms*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Train_time_flag=((%d)) , Train_time=((%d))\n", pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time)); + if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + low_traffic_train_time_l += 10; + } + + /* -- */ + if (train_time_temp >= low_traffic_train_time_u) + train_time_temp = low_traffic_train_time_u; + + else if (train_time_temp <= low_traffic_train_time_l) + train_time_temp = low_traffic_train_time_l; + + p_dm_swat_table->train_time = train_time_temp; /*10ms~200ms*/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("train_time_flag=((%d)) , train_time=((%d))\n", p_dm_swat_table->train_time_flag, p_dm_swat_table->train_time)); } else { - pDM_SWAT_Table->Train_time = 0xc8; /*200ms*/ + p_dm_swat_table->train_time = 0xc8; /*200ms*/ } - - //----------------- - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Current MinMaxRSSI is ((%d))\n", pDM_FatTable->MinMaxRSSI)); - //---reset index--- - if (pDM_SWAT_Table->reset_idx >= RSSI_CHECK_RESET_PERIOD) { - - pDM_FatTable->MinMaxRSSI = 0; - pDM_SWAT_Table->reset_idx = 0; + /* ----------------- */ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Current min_max_rssi is ((%d))\n", p_dm_fat_table->min_max_rssi)); + + /* ---reset index--- */ + if (p_dm_swat_table->reset_idx >= RSSI_CHECK_RESET_PERIOD) { + + p_dm_fat_table->min_max_rssi = 0; + p_dm_swat_table->reset_idx = 0; } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reset_idx = (( %d ))\n", pDM_SWAT_Table->reset_idx)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reset_idx = (( %d ))\n", p_dm_swat_table->reset_idx)); - pDM_SWAT_Table->reset_idx++; + p_dm_swat_table->reset_idx++; - //---double check flag--- - if ((pDM_FatTable->MinMaxRSSI > RSSI_CHECK_THRESHOLD) && (pDM_SWAT_Table->Double_chk_flag == 0)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" MinMaxRSSI is ((%d)), and > %d\n", - pDM_FatTable->MinMaxRSSI, RSSI_CHECK_THRESHOLD)); + /* ---double check flag--- */ + if ((p_dm_fat_table->min_max_rssi > RSSI_CHECK_THRESHOLD) && (p_dm_swat_table->double_chk_flag == 0)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" min_max_rssi is ((%d)), and > %d\n", + p_dm_fat_table->min_max_rssi, RSSI_CHECK_THRESHOLD)); - pDM_SWAT_Table->Double_chk_flag =1; - pDM_SWAT_Table->try_flag = SWAW_STEP_DETERMINE; - pDM_SWAT_Table->RSSI_Trying = 0; + p_dm_swat_table->double_chk_flag = 1; + p_dm_swat_table->try_flag = SWAW_STEP_DETERMINE; + p_dm_swat_table->rssi_trying = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Test the current Ant for (( %d )) ms again\n", pDM_SWAT_Table->Train_time)); - ODM_UpdateRxIdleAnt(pDM_Odm, pDM_FatTable->RxIdleAnt); - ODM_SetTimer(pDM_Odm, &(pDM_SWAT_Table->phydm_SwAntennaSwitchTimer), pDM_SWAT_Table->Train_time); /*ms*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Test the current ant for (( %d )) ms again\n", p_dm_swat_table->train_time)); + odm_update_rx_idle_ant(p_dm_odm, p_dm_fat_table->rx_idle_ant); + odm_set_timer(p_dm_odm, &(p_dm_swat_table->phydm_sw_antenna_switch_timer), p_dm_swat_table->train_time); /*ms*/ return; } - - nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT; - pDM_SWAT_Table->try_flag = SWAW_STEP_DETERMINE; - - if(pDM_SWAT_Table->reset_idx<=1) - pDM_SWAT_Table->RSSI_Trying = 2; + next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + + p_dm_swat_table->try_flag = SWAW_STEP_DETERMINE; + + if (p_dm_swat_table->reset_idx <= 1) + p_dm_swat_table->rssi_trying = 2; else - pDM_SWAT_Table->RSSI_Trying = 1; + p_dm_swat_table->rssi_trying = 1; - odm_S0S1_SwAntDivByCtrlFrame(pDM_Odm, SWAW_STEP_PEEK); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=1] Normal State: Begin Trying!!\n")); - - } else if ((pDM_SWAT_Table->try_flag == SWAW_STEP_DETERMINE) && (pDM_SWAT_Table->Double_chk_flag == 0)) { - - nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT; - pDM_SWAT_Table->RSSI_Trying--; + odm_s0s1_sw_ant_div_by_ctrl_frame(p_dm_odm, SWAW_STEP_PEEK); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=1] Normal state: Begin Trying!!\n")); + + } else if ((p_dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (p_dm_swat_table->double_chk_flag == 0)) { + + next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + p_dm_swat_table->rssi_trying--; } - - //1 Decision State - if ((pDM_SWAT_Table->try_flag == SWAW_STEP_DETERMINE) && (pDM_SWAT_Table->RSSI_Trying == 0)) { - - BOOLEAN bByCtrlFrame = FALSE; - u8Byte pkt_cnt_total = 0; - - for (i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pEntry)) - { - //2 Caculate RSSI per Antenna - Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; - Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; - - if(pDM_FatTable->MainAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_main>=1) - Main_RSSI=0; - - if(pDM_FatTable->AuxAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_aux>=1) - Aux_RSSI=0; - - TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT); - LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI; - LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d )) \n", pDM_FatTable->CCK_counter_main, pDM_FatTable->CCK_counter_aux)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d )) \n", pDM_FatTable->OFDM_counter_main, pDM_FatTable->OFDM_counter_aux)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n", pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI )); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); - - //2 Select RX Idle Antenna - - if (LocalMaxRSSI != 0 && LocalMaxRSSI < MinMaxRSSI) - { - RxIdleAnt = TargetAnt; - MinMaxRSSI = LocalMaxRSSI; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** LocalMaxRSSI-LocalMinRSSI = ((%d))\n",(LocalMaxRSSI-LocalMinRSSI))); - - if((LocalMaxRSSI-LocalMinRSSI)>8) - { - if(LocalMinRSSI != 0) - pDM_SWAT_Table->Train_time_flag=3; - else - { - if (MinMaxRSSI > RSSI_CHECK_THRESHOLD) - pDM_SWAT_Table->Train_time_flag=0; + + /* 1 Decision state */ + if ((p_dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (p_dm_swat_table->rssi_trying == 0)) { + + boolean is_by_ctrl_frame = false; + u64 pkt_cnt_total = 0; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + p_entry = p_dm_odm->p_odm_sta_info[i]; + if (IS_STA_VALID(p_entry)) { + /* 2 Caculate RSSI per Antenna */ + + main_ant_sum = (u32)p_dm_fat_table->main_ant_sum[i] + (u32)p_dm_fat_table->main_ant_sum_cck[i]; + aux_ant_sum = (u32)p_dm_fat_table->aux_ant_sum[i] + (u32)p_dm_fat_table->aux_ant_sum_cck[i]; + main_ant_cnt = (u32)p_dm_fat_table->main_ant_cnt[i] + (u32)p_dm_fat_table->main_ant_cnt_cck[i]; + aux_ant_cnt = (u32)p_dm_fat_table->aux_ant_cnt[i] + (u32)p_dm_fat_table->aux_ant_cnt_cck[i]; + + main_rssi = (main_ant_cnt != 0) ? (main_ant_sum / main_ant_cnt) : 0; + aux_rssi = (aux_ant_cnt != 0) ? (aux_ant_sum / aux_ant_cnt) : 0; + + if (p_dm_fat_table->main_ant_cnt[i] <= 1 && p_dm_fat_table->main_ant_cnt_cck[i] >= 1) + main_rssi = 0; + + if (p_dm_fat_table->aux_ant_cnt[i] <= 1 && p_dm_fat_table->aux_ant_cnt_cck[i] >= 1) + aux_rssi = 0; + + target_ant = (main_rssi == aux_rssi) ? p_dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); + local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi; + local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d ))\n", p_dm_fat_table->main_ant_cnt_cck[i], p_dm_fat_table->aux_ant_cnt_cck[i])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d ))\n", p_dm_fat_table->main_ant_cnt[i], p_dm_fat_table->aux_ant_cnt[i])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", main_ant_cnt, main_rssi)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", aux_ant_cnt, aux_rssi)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i, (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + + /* 2 Select RX Idle Antenna */ + + if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) { + rx_idle_ant = target_ant; + min_max_rssi = local_max_rssi; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** local_max_rssi-local_min_rssi = ((%d))\n", (local_max_rssi - local_min_rssi))); + + if ((local_max_rssi - local_min_rssi) > 8) { + if (local_min_rssi != 0) + p_dm_swat_table->train_time_flag = 3; + else { + if (min_max_rssi > RSSI_CHECK_THRESHOLD) + p_dm_swat_table->train_time_flag = 0; else - pDM_SWAT_Table->Train_time_flag=3; + p_dm_swat_table->train_time_flag = 3; } - } - else if((LocalMaxRSSI-LocalMinRSSI)>5) - pDM_SWAT_Table->Train_time_flag=2; - else if((LocalMaxRSSI-LocalMinRSSI)>2) - pDM_SWAT_Table->Train_time_flag=1; + } else if ((local_max_rssi - local_min_rssi) > 5) + p_dm_swat_table->train_time_flag = 2; + else if ((local_max_rssi - local_min_rssi) > 2) + p_dm_swat_table->train_time_flag = 1; else - pDM_SWAT_Table->Train_time_flag=0; - + p_dm_swat_table->train_time_flag = 0; + } - - //2 Select TX Antenna - if(TargetAnt == MAIN_ANT) - pDM_FatTable->antsel_a[i] = ANT1_2G; + + /* 2 Select TX Antenna */ + if (target_ant == MAIN_ANT) + p_dm_fat_table->antsel_a[i] = ANT1_2G; else - pDM_FatTable->antsel_a[i] = ANT2_2G; - + p_dm_fat_table->antsel_a[i] = ANT2_2G; + } - pDM_FatTable->MainAnt_Sum[i] = 0; - pDM_FatTable->AuxAnt_Sum[i] = 0; - pDM_FatTable->MainAnt_Cnt[i] = 0; - pDM_FatTable->AuxAnt_Cnt[i] = 0; + phydm_antdiv_reset_statistic(p_dm_odm, i); + pkt_cnt_total += (main_ant_cnt + aux_ant_cnt); } - if(pDM_SWAT_Table->bSWAntDivByCtrlFrame) - { - odm_S0S1_SwAntDivByCtrlFrame(pDM_Odm, SWAW_STEP_DETERMINE); - bByCtrlFrame = TRUE; + if (p_dm_swat_table->is_sw_ant_div_by_ctrl_frame) { + odm_s0s1_sw_ant_div_by_ctrl_frame(p_dm_odm, SWAW_STEP_DETERMINE); + is_by_ctrl_frame = true; } - pkt_cnt_total = pDM_FatTable->CCK_counter_main + pDM_FatTable->CCK_counter_aux + - pDM_FatTable->OFDM_counter_main + pDM_FatTable->OFDM_counter_aux; - pDM_FatTable->CCK_counter_main=0; - pDM_FatTable->CCK_counter_aux=0; - pDM_FatTable->OFDM_counter_main=0; - pDM_FatTable->OFDM_counter_aux=0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Control frame packet counter = %d, Data frame packet counter = %llu\n", - pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame, pkt_cnt_total)); - - if(MinMaxRSSI == 0xff || ((pkt_cnt_total < (pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame >> 1)) && pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 2)) - { - MinMaxRSSI = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Check RSSI of control frame because MinMaxRSSI == 0xff\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("bByCtrlFrame = %d\n", bByCtrlFrame)); - - if(bByCtrlFrame) - { - Main_RSSI = (pDM_FatTable->MainAnt_CtrlFrame_Cnt!=0)?(pDM_FatTable->MainAnt_CtrlFrame_Sum/pDM_FatTable->MainAnt_CtrlFrame_Cnt):0; - Aux_RSSI = (pDM_FatTable->AuxAnt_CtrlFrame_Cnt!=0)?(pDM_FatTable->AuxAnt_CtrlFrame_Sum/pDM_FatTable->AuxAnt_CtrlFrame_Cnt):0; - - if(pDM_FatTable->MainAnt_CtrlFrame_Cnt<=1 && pDM_FatTable->CCK_CtrlFrame_Cnt_main>=1) - Main_RSSI=0; - - if(pDM_FatTable->AuxAnt_CtrlFrame_Cnt<=1 && pDM_FatTable->CCK_CtrlFrame_Cnt_aux>=1) - Aux_RSSI=0; - - if (Main_RSSI != 0 || Aux_RSSI != 0) - { - RxIdleAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT); - LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI; - LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI; - - if((LocalMaxRSSI-LocalMinRSSI)>8) - pDM_SWAT_Table->Train_time_flag=3; - else if((LocalMaxRSSI-LocalMinRSSI)>5) - pDM_SWAT_Table->Train_time_flag=2; - else if((LocalMaxRSSI-LocalMinRSSI)>2) - pDM_SWAT_Table->Train_time_flag=1; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Control frame packet counter = %d, data frame packet counter = %llu\n", + p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame, pkt_cnt_total)); + + if (min_max_rssi == 0xff || ((pkt_cnt_total < (p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) && p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 2)) { + min_max_rssi = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Check RSSI of control frame because min_max_rssi == 0xff\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_by_ctrl_frame = %d\n", is_by_ctrl_frame)); + + if (is_by_ctrl_frame) { + main_rssi = (p_dm_fat_table->main_ant_ctrl_frame_cnt != 0) ? (p_dm_fat_table->main_ant_ctrl_frame_sum / p_dm_fat_table->main_ant_ctrl_frame_cnt) : 0; + aux_rssi = (p_dm_fat_table->aux_ant_ctrl_frame_cnt != 0) ? (p_dm_fat_table->aux_ant_ctrl_frame_sum / p_dm_fat_table->aux_ant_ctrl_frame_cnt) : 0; + + if (p_dm_fat_table->main_ant_ctrl_frame_cnt <= 1 && p_dm_fat_table->cck_ctrl_frame_cnt_main >= 1) + main_rssi = 0; + + if (p_dm_fat_table->aux_ant_ctrl_frame_cnt <= 1 && p_dm_fat_table->cck_ctrl_frame_cnt_aux >= 1) + aux_rssi = 0; + + if (main_rssi != 0 || aux_rssi != 0) { + rx_idle_ant = (main_rssi == aux_rssi) ? p_dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); + local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi; + local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi; + + if ((local_max_rssi - local_min_rssi) > 8) + p_dm_swat_table->train_time_flag = 3; + else if ((local_max_rssi - local_min_rssi) > 5) + p_dm_swat_table->train_time_flag = 2; + else if ((local_max_rssi - local_min_rssi) > 2) + p_dm_swat_table->train_time_flag = 1; else - pDM_SWAT_Table->Train_time_flag=0; + p_dm_swat_table->train_time_flag = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Control frame: Main_RSSI = %d, Aux_RSSI = %d\n", Main_RSSI, Aux_RSSI)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("RxIdleAnt decided by control frame = %s\n", (RxIdleAnt == MAIN_ANT?"MAIN":"AUX"))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Control frame: main_rssi = %d, aux_rssi = %d\n", main_rssi, aux_rssi)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("rx_idle_ant decided by control frame = %s\n", (rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"))); } } } - pDM_FatTable->MinMaxRSSI = MinMaxRSSI; - pDM_SWAT_Table->try_flag = SWAW_STEP_PEEK; - - if( pDM_SWAT_Table->Double_chk_flag==1) - { - pDM_SWAT_Table->Double_chk_flag=0; - - if (pDM_FatTable->MinMaxRSSI > RSSI_CHECK_THRESHOLD) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] MinMaxRSSI ((%d)) > %d again!!\n", - pDM_FatTable->MinMaxRSSI, RSSI_CHECK_THRESHOLD)); - - ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[reset try_flag = 0] Training accomplished !!!]\n\n\n")); + p_dm_fat_table->min_max_rssi = min_max_rssi; + p_dm_swat_table->try_flag = SWAW_STEP_PEEK; + + if (p_dm_swat_table->double_chk_flag == 1) { + p_dm_swat_table->double_chk_flag = 0; + + if (p_dm_fat_table->min_max_rssi > RSSI_CHECK_THRESHOLD) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] min_max_rssi ((%d)) > %d again!!\n", + p_dm_fat_table->min_max_rssi, RSSI_CHECK_THRESHOLD)); + + odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[reset try_flag = 0] Training accomplished !!!]\n\n\n")); return; - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] MinMaxRSSI ((%d)) <= %d !!\n", - pDM_FatTable->MinMaxRSSI, RSSI_CHECK_THRESHOLD)); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] min_max_rssi ((%d)) <= %d !!\n", + p_dm_fat_table->min_max_rssi, RSSI_CHECK_THRESHOLD)); - nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT; - pDM_SWAT_Table->try_flag = SWAW_STEP_PEEK; - pDM_SWAT_Table->reset_idx = RSSI_CHECK_RESET_PERIOD; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=0] Normal State: Need to tryg again!!\n\n\n")); + next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + p_dm_swat_table->try_flag = SWAW_STEP_PEEK; + p_dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=0] Normal state: Need to tryg again!!\n\n\n")); return; } - } - else - { - if (pDM_FatTable->MinMaxRSSI < RSSI_CHECK_THRESHOLD) - pDM_SWAT_Table->reset_idx = RSSI_CHECK_RESET_PERIOD; - - pDM_SWAT_Table->PreAntenna =RxIdleAnt; - ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt ); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[reset try_flag = 0] Training accomplished !!!] \n\n\n")); + } else { + if (p_dm_fat_table->min_max_rssi < RSSI_CHECK_THRESHOLD) + p_dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD; + + p_dm_swat_table->pre_antenna = rx_idle_ant; + odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[reset try_flag = 0] Training accomplished !!!] \n\n\n")); return; } - + } } - //1 4.Change TRX antenna + /* 1 4.Change TRX antenna */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = (( %d )), Ant: (( %s )) >>> (( %s )) \n", - pDM_SWAT_Table->RSSI_Trying, (pDM_FatTable->RxIdleAnt == MAIN_ANT?"MAIN":"AUX"),(nextAnt == MAIN_ANT?"MAIN":"AUX"))); - - ODM_UpdateRxIdleAnt(pDM_Odm, nextAnt); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("rssi_trying = (( %d )), ant: (( %s )) >>> (( %s ))\n", + p_dm_swat_table->rssi_trying, (p_dm_fat_table->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"), (next_ant == MAIN_ANT ? "MAIN" : "AUX"))); - //1 5.Reset Statistics + odm_update_rx_idle_ant(p_dm_odm, next_ant); - pDM_FatTable->RxIdleAnt = nextAnt; + /* 1 5.Reset Statistics */ - //1 6.Set next timer (Trying State) - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test ((%s)) Ant for (( %d )) ms\n", (nextAnt == MAIN_ANT?"MAIN":"AUX"), pDM_SWAT_Table->Train_time)); - ODM_SetTimer(pDM_Odm, &(pDM_SWAT_Table->phydm_SwAntennaSwitchTimer), pDM_SWAT_Table->Train_time); /*ms*/ + p_dm_fat_table->rx_idle_ant = next_ant; + + if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (p_dm_odm->support_interface == ODM_ITRF_SDIO) { + + ODM_delay_us(200); + + if (p_dm_fat_table->rx_idle_ant == MAIN_ANT) { + p_dm_fat_table->main_ant_sum[0] = 0; + p_dm_fat_table->main_ant_cnt[0] = 0; + p_dm_fat_table->main_ant_sum_cck[0] = 0; + p_dm_fat_table->main_ant_cnt_cck[0] = 0; + } else { + p_dm_fat_table->aux_ant_sum[0] = 0; + p_dm_fat_table->aux_ant_cnt[0] = 0; + p_dm_fat_table->aux_ant_sum_cck[0] = 0; + p_dm_fat_table->aux_ant_cnt_cck[0] = 0; + } + } + } + + /* 1 6.Set next timer (Trying state) */ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test ((%s)) ant for (( %d )) ms\n", (next_ant == MAIN_ANT ? "MAIN" : "AUX"), p_dm_swat_table->train_time)); + odm_set_timer(p_dm_odm, &(p_dm_swat_table->phydm_sw_antenna_switch_timer), p_dm_swat_table->train_time); /*ms*/ } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -ODM_SW_AntDiv_Callback( - PRT_TIMER pTimer +void +odm_sw_antdiv_callback( + struct timer_list *p_timer ) { - PADAPTER Adapter = (PADAPTER)pTimer->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - pSWAT_T pDM_SWAT_Table = &pHalData->DM_OutSrc.DM_SWAT_Table; + struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct _sw_antenna_switch_ *p_dm_swat_table = &p_hal_data->DM_OutSrc.dm_swat_table; - #if DEV_BUS_TYPE==RT_PCI_INTERFACE - #if USE_WORKITEM - ODM_ScheduleWorkItem(&pDM_SWAT_Table->phydm_SwAntennaSwitchWorkitem); - #else - { - //DbgPrint("SW_antdiv_Callback"); - odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE); - } - #endif - #else - ODM_ScheduleWorkItem(&pDM_SWAT_Table->phydm_SwAntennaSwitchWorkitem); - #endif +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +#if USE_WORKITEM + odm_schedule_work_item(&p_dm_swat_table->phydm_sw_antenna_switch_workitem); +#else + { + /* dbg_print("SW_antdiv_Callback"); */ + odm_s0s1_sw_ant_div(&p_hal_data->DM_OutSrc, SWAW_STEP_DETERMINE); + } +#endif +#else + odm_schedule_work_item(&p_dm_swat_table->phydm_sw_antenna_switch_workitem); +#endif } -VOID -ODM_SW_AntDiv_WorkitemCallback( - IN PVOID pContext - ) +void +odm_sw_antdiv_workitem_callback( + void *p_context +) { - PADAPTER pAdapter = (PADAPTER)pContext; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - //DbgPrint("SW_antdiv_Workitem_Callback"); - odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE); + struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + + /* dbg_print("SW_antdiv_Workitem_Callback"); */ + odm_s0s1_sw_ant_div(&p_hal_data->DM_OutSrc, SWAW_STEP_DETERMINE); } #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -VOID -ODM_SW_AntDiv_WorkitemCallback( - IN PVOID pContext +void +odm_sw_antdiv_workitem_callback( + void *p_context ) { - PADAPTER - pAdapter = (PADAPTER)pContext; + struct _ADAPTER * + p_adapter = (struct _ADAPTER *)p_context; HAL_DATA_TYPE - *pHalData = GET_HAL_DATA(pAdapter); + *p_hal_data = GET_HAL_DATA(p_adapter); - /*DbgPrint("SW_antdiv_Workitem_Callback");*/ - odm_S0S1_SwAntDiv(&pHalData->odmpriv, SWAW_STEP_DETERMINE); + /*dbg_print("SW_antdiv_Workitem_Callback");*/ + odm_s0s1_sw_ant_div(&p_hal_data->odmpriv, SWAW_STEP_DETERMINE); } -VOID -ODM_SW_AntDiv_Callback(void *FunctionContext) +void +odm_sw_antdiv_callback(void *function_context) { - PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; - PADAPTER padapter = pDM_Odm->Adapter; - if(padapter->net_closed == _TRUE) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)function_context; + struct _ADAPTER *padapter = p_dm_odm->adapter; + if (padapter->net_closed == _TRUE) return; - - #if 0 /* Can't do I/O in timer callback*/ - odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_DETERMINE); - #else - rtw_run_in_thread_cmd(padapter, ODM_SW_AntDiv_WorkitemCallback, padapter); - #endif + +#if 0 /* Can't do I/O in timer callback*/ + odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_DETERMINE); +#else + rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter); +#endif } #endif -VOID -odm_S0S1_SwAntDivByCtrlFrame( - IN PVOID pDM_VOID, - IN u1Byte Step - ) +void +odm_s0s1_sw_ant_div_by_ctrl_frame( + void *p_dm_void, + u8 step +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - switch(Step) - { - case SWAW_STEP_PEEK: - pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame = 0; - pDM_SWAT_Table->bSWAntDivByCtrlFrame = TRUE; - pDM_FatTable->MainAnt_CtrlFrame_Cnt = 0; - pDM_FatTable->AuxAnt_CtrlFrame_Cnt = 0; - pDM_FatTable->MainAnt_CtrlFrame_Sum = 0; - pDM_FatTable->AuxAnt_CtrlFrame_Sum = 0; - pDM_FatTable->CCK_CtrlFrame_Cnt_main = 0; - pDM_FatTable->CCK_CtrlFrame_Cnt_aux = 0; - pDM_FatTable->OFDM_CtrlFrame_Cnt_main = 0; - pDM_FatTable->OFDM_CtrlFrame_Cnt_aux = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n")); - break; - case SWAW_STEP_DETERMINE: - pDM_SWAT_Table->bSWAntDivByCtrlFrame = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Stop peek\n")); - break; - default: - pDM_SWAT_Table->bSWAntDivByCtrlFrame = FALSE; - break; - } + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + + switch (step) { + case SWAW_STEP_PEEK: + p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame = 0; + p_dm_swat_table->is_sw_ant_div_by_ctrl_frame = true; + p_dm_fat_table->main_ant_ctrl_frame_cnt = 0; + p_dm_fat_table->aux_ant_ctrl_frame_cnt = 0; + p_dm_fat_table->main_ant_ctrl_frame_sum = 0; + p_dm_fat_table->aux_ant_ctrl_frame_sum = 0; + p_dm_fat_table->cck_ctrl_frame_cnt_main = 0; + p_dm_fat_table->cck_ctrl_frame_cnt_aux = 0; + p_dm_fat_table->ofdm_ctrl_frame_cnt_main = 0; + p_dm_fat_table->ofdm_ctrl_frame_cnt_aux = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n")); + break; + case SWAW_STEP_DETERMINE: + p_dm_swat_table->is_sw_ant_div_by_ctrl_frame = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Stop peek\n")); + break; + default: + p_dm_swat_table->is_sw_ant_div_by_ctrl_frame = false; + break; + } } -VOID -odm_AntselStatisticsOfCtrlFrame( - IN PVOID pDM_VOID, - IN u1Byte antsel_tr_mux, - IN u4Byte RxPWDBAll - - ) +void +odm_antsel_statistics_of_ctrl_frame( + void *p_dm_void, + u8 antsel_tr_mux, + u32 rx_pwdb_all + +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - if(antsel_tr_mux == ANT1_2G) - { - pDM_FatTable->MainAnt_CtrlFrame_Sum+=RxPWDBAll; - pDM_FatTable->MainAnt_CtrlFrame_Cnt++; - } - else - { - pDM_FatTable->AuxAnt_CtrlFrame_Sum+=RxPWDBAll; - pDM_FatTable->AuxAnt_CtrlFrame_Cnt++; + if (antsel_tr_mux == ANT1_2G) { + p_dm_fat_table->main_ant_ctrl_frame_sum += rx_pwdb_all; + p_dm_fat_table->main_ant_ctrl_frame_cnt++; + } else { + p_dm_fat_table->aux_ant_ctrl_frame_sum += rx_pwdb_all; + p_dm_fat_table->aux_ant_ctrl_frame_cnt++; } } -VOID -odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI( - IN PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN PVOID p_pkt_info_void - //IN PODM_PHY_INFO_T pPhyInfo, - //IN PODM_PACKET_INFO_T pPktinfo - ) +void +odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi( + void *p_dm_void, + void *p_phy_info_void, + void *p_pkt_info_void + /* struct _odm_phy_status_info_* p_phy_info, */ + /* struct _odm_per_pkt_info_* p_pktinfo */ +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; - PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - BOOLEAN isCCKrate; - - if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; + struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + boolean is_cck_rate; + + if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) return; - if(pDM_Odm->AntDivType != S0S1_SW_ANTDIV) + if (p_dm_odm->ant_div_type != S0S1_SW_ANTDIV) return; - // In try state - if(!pDM_SWAT_Table->bSWAntDivByCtrlFrame) + /* In try state */ + if (!p_dm_swat_table->is_sw_ant_div_by_ctrl_frame) return; - // No HW error and match receiver address - if(!pPktinfo->bToSelf) + /* No HW error and match receiver address */ + if (!p_pktinfo->is_to_self) return; - - pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame++; - isCCKrate = ((pPktinfo->DataRate >= DESC_RATE1M ) && (pPktinfo->DataRate <= DESC_RATE11M ))?TRUE :FALSE; - if(isCCKrate) - { - pDM_FatTable->antsel_rx_keep_0 = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ANT1_2G : ANT2_2G; + p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame++; + is_cck_rate = ((p_pktinfo->data_rate >= DESC_RATE1M) && (p_pktinfo->data_rate <= DESC_RATE11M)) ? true : false; - if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G) - pDM_FatTable->CCK_CtrlFrame_Cnt_main++; + if (is_cck_rate) { + p_dm_fat_table->antsel_rx_keep_0 = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; + + if (p_dm_fat_table->antsel_rx_keep_0 == ANT1_2G) + p_dm_fat_table->cck_ctrl_frame_cnt_main++; else - pDM_FatTable->CCK_CtrlFrame_Cnt_aux++; + p_dm_fat_table->cck_ctrl_frame_cnt_aux++; - odm_AntselStatisticsOfCtrlFrame(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]); - } - else - { - if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G) - pDM_FatTable->OFDM_CtrlFrame_Cnt_main++; + odm_antsel_statistics_of_ctrl_frame(p_dm_odm, p_dm_fat_table->antsel_rx_keep_0, p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]); + } else { + p_dm_fat_table->antsel_rx_keep_0 = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; + + if (p_dm_fat_table->antsel_rx_keep_0 == ANT1_2G) + p_dm_fat_table->ofdm_ctrl_frame_cnt_main++; else - pDM_FatTable->OFDM_CtrlFrame_Cnt_aux++; + p_dm_fat_table->ofdm_ctrl_frame_cnt_aux++; - odm_AntselStatisticsOfCtrlFrame(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPhyInfo->RxPWDBAll); + odm_antsel_statistics_of_ctrl_frame(p_dm_odm, p_dm_fat_table->antsel_rx_keep_0, p_phy_info->rx_pwdb_all); } } -#endif //#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) +#endif /* #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) */ -VOID -odm_SetNextMACAddrTarget( - IN PVOID pDM_VOID - ) +void +odm_set_next_mac_addr_target( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - PSTA_INFO_T pEntry; - u4Byte value32, i; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct sta_info *p_entry; + u32 value32, i; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SetNextMACAddrTarget() ==>\n")); - - if (pDM_Odm->bLinked) - { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_set_next_mac_addr_target() ==>\n")); + + if (p_dm_odm->is_linked) { for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - - if ((pDM_FatTable->TrainIdx+1) == ODM_ASSOCIATE_ENTRY_NUM) - pDM_FatTable->TrainIdx = 0; + + if ((p_dm_fat_table->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM) + p_dm_fat_table->train_idx = 0; else - pDM_FatTable->TrainIdx++; - - pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx]; - - if (IS_STA_VALID(pEntry)) { - - /*Match MAC ADDR*/ - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - value32 = (pEntry->hwaddr[5]<<8)|pEntry->hwaddr[4]; - #else - value32 = (pEntry->MacAddr[5]<<8)|pEntry->MacAddr[4]; - #endif - - ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);/*0x7b4~0x7b5*/ - - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - value32 = (pEntry->hwaddr[3]<<24)|(pEntry->hwaddr[2]<<16) |(pEntry->hwaddr[1]<<8) |pEntry->hwaddr[0]; - #else - value32 = (pEntry->MacAddr[3]<<24)|(pEntry->MacAddr[2]<<16) |(pEntry->MacAddr[1]<<8) |pEntry->MacAddr[0]; - #endif - ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);/*0x7b0~0x7b3*/ + p_dm_fat_table->train_idx++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->TrainIdx=%d\n", pDM_FatTable->TrainIdx)); - - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n", - pEntry->hwaddr[5], pEntry->hwaddr[4], pEntry->hwaddr[3], pEntry->hwaddr[2], pEntry->hwaddr[1], pEntry->hwaddr[0])); - #else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n", - pEntry->MacAddr[5], pEntry->MacAddr[4], pEntry->MacAddr[3], pEntry->MacAddr[2], pEntry->MacAddr[1], pEntry->MacAddr[0])); - #endif + p_entry = p_dm_odm->p_odm_sta_info[p_dm_fat_table->train_idx]; - break; - } - } - } + if (IS_STA_VALID(p_entry)) { -#if 0 - // - //2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn - // - #if( DM_ODM_SUPPORT_TYPE & ODM_WIN) - { - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - - for (i=0; i<6; i++) - { - Bssid[i] = pMgntInfo->Bssid[i]; - //DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]); + /*Match MAC ADDR*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + value32 = (p_entry->hwaddr[5] << 8) | p_entry->hwaddr[4]; +#else + value32 = (p_entry->MacAddr[5] << 8) | p_entry->MacAddr[4]; +#endif + + odm_set_mac_reg(p_dm_odm, 0x7b4, 0xFFFF, value32);/*0x7b4~0x7b5*/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + value32 = (p_entry->hwaddr[3] << 24) | (p_entry->hwaddr[2] << 16) | (p_entry->hwaddr[1] << 8) | p_entry->hwaddr[0]; +#else + value32 = (p_entry->MacAddr[3] << 24) | (p_entry->MacAddr[2] << 16) | (p_entry->MacAddr[1] << 8) | p_entry->MacAddr[0]; +#endif + odm_set_mac_reg(p_dm_odm, 0x7b0, MASKDWORD, value32);/*0x7b0~0x7b3*/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_fat_table->train_idx=%d\n", p_dm_fat_table->train_idx)); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC addr = %x:%x:%x:%x:%x:%x\n", + p_entry->hwaddr[5], p_entry->hwaddr[4], p_entry->hwaddr[3], p_entry->hwaddr[2], p_entry->hwaddr[1], p_entry->hwaddr[0])); +#else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC addr = %x:%x:%x:%x:%x:%x\n", + p_entry->MacAddr[5], p_entry->MacAddr[4], p_entry->MacAddr[3], p_entry->MacAddr[2], p_entry->MacAddr[1], p_entry->MacAddr[0])); +#endif + + break; + } } } - #endif - //odm_SetNextMACAddrTarget(pDM_Odm); - - //1 Select MAC Address Filter - for (i=0; i<6; i++) +#if 0 + /* */ + /* 2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn */ + /* */ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) { - if(Bssid[i] != pDM_FatTable->Bssid[i]) - { - bMatchBSSID = FALSE; + struct _ADAPTER *adapter = p_dm_odm->adapter; + PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; + + for (i = 0; i < 6; i++) { + bssid[i] = p_mgnt_info->bssid[i]; + /* dbg_print("bssid[%d]=%x\n", i, bssid[i]); */ + } + } +#endif + + /* odm_set_next_mac_addr_target(p_dm_odm); */ + + /* 1 Select MAC Address Filter */ + for (i = 0; i < 6; i++) { + if (bssid[i] != p_dm_fat_table->bssid[i]) { + is_match_bssid = false; break; } } - if(bMatchBSSID == FALSE) - { - //Match MAC ADDR - value32 = (Bssid[5]<<8)|Bssid[4]; - ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32); - value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0]; - ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32); + if (is_match_bssid == false) { + /* Match MAC ADDR */ + value32 = (bssid[5] << 8) | bssid[4]; + odm_set_mac_reg(p_dm_odm, 0x7b4, 0xFFFF, value32); + value32 = (bssid[3] << 24) | (bssid[2] << 16) | (bssid[1] << 8) | bssid[0]; + odm_set_mac_reg(p_dm_odm, 0x7b0, MASKDWORD, value32); } - return bMatchBSSID; + return is_match_bssid; #endif - + } #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) -VOID -odm_FastAntTraining( - IN PVOID pDM_VOID - ) +void +odm_fast_ant_training( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - u4Byte MaxRSSI_pathA=0, Pckcnt_pathA=0; - u1Byte i,TargetAnt_pathA=0; - BOOLEAN bPktFilterMacth_pathA = FALSE; - #if(RTL8192E_SUPPORT == 1) - u4Byte MaxRSSI_pathB=0, Pckcnt_pathB=0; - u1Byte TargetAnt_pathB=0; - BOOLEAN bPktFilterMacth_pathB = FALSE; - #endif + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + + u32 max_rssi_path_a = 0, pckcnt_path_a = 0; + u8 i, target_ant_path_a = 0; + boolean is_pkt_filter_macth_path_a = false; +#if (RTL8192E_SUPPORT == 1) + u32 max_rssi_path_b = 0, pckcnt_path_b = 0; + u8 target_ant_path_b = 0; + boolean is_pkt_filter_macth_path_b = false; +#endif - if(!pDM_Odm->bLinked) //bLinked==False - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - - if(pDM_FatTable->bBecomeLinked == TRUE) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - phydm_FastTraining_enable(pDM_Odm , FAT_OFF); - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + if (!p_dm_odm->is_linked) { /* is_linked==False */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + + if (p_dm_fat_table->is_become_linked == true) { + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + phydm_fast_training_enable(p_dm_odm, FAT_OFF); + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; } return; - } - else - { - if(pDM_FatTable->bBecomeLinked ==FALSE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked!!!]\n")); - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } else { + if (p_dm_fat_table->is_become_linked == false) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked!!!]\n")); + p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; } } - if (*(pDM_FatTable->pForceTxAntByDesc) == FALSE) { - if (pDM_Odm->bOneEntryOnly == TRUE) - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) { + if (p_dm_odm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); else - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); } - - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, ((pDM_Odm->fat_comb_a)-1)); - } - #if(RTL8192E_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT2|BIT1|BIT0, ((pDM_Odm->fat_comb_a)-1) ); //path-A // ant combination=regB38[2:0]+1 - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT18|BIT17|BIT16, ((pDM_Odm->fat_comb_b)-1) ); //path-B // ant combination=regB38[18:16]+1 - } - #endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n")); + if (p_dm_odm->support_ic_type == ODM_RTL8188E) + odm_set_bb_reg(p_dm_odm, 0x864, BIT(2) | BIT(1) | BIT(0), ((p_dm_odm->fat_comb_a) - 1)); +#if (RTL8192E_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(p_dm_odm, 0xB38, BIT(2) | BIT1 | BIT0, ((p_dm_odm->fat_comb_a) - 1)); /* path-A */ /* ant combination=regB38[2:0]+1 */ + odm_set_bb_reg(p_dm_odm, 0xB38, BIT(18) | BIT17 | BIT16, ((p_dm_odm->fat_comb_b) - 1)); /* path-B */ /* ant combination=regB38[18:16]+1 */ + } +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_fast_ant_training()\n")); - //1 TRAINING STATE - if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE) - { - //2 Caculate RSSI per Antenna + /* 1 TRAINING STATE */ + if (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) { + /* 2 Caculate RSSI per Antenna */ - //3 [path-A]--------------------------- - for (i=0; i<(pDM_Odm->fat_comb_a); i++) // i : antenna index - { - if(pDM_FatTable->antRSSIcnt[i] == 0) - pDM_FatTable->antAveRSSI[i] = 0; - else - { - pDM_FatTable->antAveRSSI[i] = pDM_FatTable->antSumRSSI[i] /pDM_FatTable->antRSSIcnt[i]; - bPktFilterMacth_pathA = TRUE; - } - - if(pDM_FatTable->antAveRSSI[i] > MaxRSSI_pathA) - { - MaxRSSI_pathA = pDM_FatTable->antAveRSSI[i]; - Pckcnt_pathA = pDM_FatTable ->antRSSIcnt[i]; - TargetAnt_pathA = i ; + /* 3 [path-A]--------------------------- */ + for (i = 0; i < (p_dm_odm->fat_comb_a); i++) { /* i : antenna index */ + if (p_dm_fat_table->ant_rssi_cnt[i] == 0) + p_dm_fat_table->ant_ave_rssi[i] = 0; + else { + p_dm_fat_table->ant_ave_rssi[i] = p_dm_fat_table->ant_sum_rssi[i] / p_dm_fat_table->ant_rssi_cnt[i]; + is_pkt_filter_macth_path_a = true; } - else if(pDM_FatTable->antAveRSSI[i] == MaxRSSI_pathA) - { - if( (pDM_FatTable->antRSSIcnt[i] ) > Pckcnt_pathA) - { - MaxRSSI_pathA = pDM_FatTable->antAveRSSI[i]; - Pckcnt_pathA = pDM_FatTable ->antRSSIcnt[i]; - TargetAnt_pathA = i ; - } + + if (p_dm_fat_table->ant_ave_rssi[i] > max_rssi_path_a) { + max_rssi_path_a = p_dm_fat_table->ant_ave_rssi[i]; + pckcnt_path_a = p_dm_fat_table->ant_rssi_cnt[i]; + target_ant_path_a = i ; + } else if (p_dm_fat_table->ant_ave_rssi[i] == max_rssi_path_a) { + if ((p_dm_fat_table->ant_rssi_cnt[i]) > pckcnt_path_a) { + max_rssi_path_a = p_dm_fat_table->ant_ave_rssi[i]; + pckcnt_path_a = p_dm_fat_table->ant_rssi_cnt[i]; + target_ant_path_a = i ; + } } - ODM_RT_TRACE("*** Ant-Index : [ %d ], Counter = (( %d )), Avg RSSI = (( %d )) \n", i, pDM_FatTable->antRSSIcnt[i], pDM_FatTable->antAveRSSI[i] ); + ODM_RT_TRACE("*** ant-index : [ %d ], counter = (( %d )), Avg RSSI = (( %d ))\n", i, p_dm_fat_table->ant_rssi_cnt[i], p_dm_fat_table->ant_ave_rssi[i]); } - /* - #if(RTL8192E_SUPPORT == 1) - //3 [path-B]--------------------------- - for (i=0; i<(pDM_Odm->fat_comb_b); i++) - { - if(pDM_FatTable->antRSSIcnt_pathB[i] == 0) - pDM_FatTable->antAveRSSI_pathB[i] = 0; - else // (antRSSIcnt[i] != 0) - { - pDM_FatTable->antAveRSSI_pathB[i] = pDM_FatTable->antSumRSSI_pathB[i] /pDM_FatTable->antRSSIcnt_pathB[i]; - bPktFilterMacth_pathB = TRUE; +#if 0 +#if (RTL8192E_SUPPORT == 1) + /* 3 [path-B]--------------------------- */ + for (i = 0; i < (p_dm_odm->fat_comb_b); i++) { + if (p_dm_fat_table->antRSSIcnt_pathB[i] == 0) + p_dm_fat_table->antAveRSSI_pathB[i] = 0; + else { /* (ant_rssi_cnt[i] != 0) */ + p_dm_fat_table->antAveRSSI_pathB[i] = p_dm_fat_table->antSumRSSI_pathB[i] / p_dm_fat_table->antRSSIcnt_pathB[i]; + is_pkt_filter_macth_path_b = true; } - if(pDM_FatTable->antAveRSSI_pathB[i] > MaxRSSI_pathB) - { - MaxRSSI_pathB = pDM_FatTable->antAveRSSI_pathB[i]; - Pckcnt_pathB = pDM_FatTable ->antRSSIcnt_pathB[i]; - TargetAnt_pathB = (u1Byte) i; + if (p_dm_fat_table->antAveRSSI_pathB[i] > max_rssi_path_b) { + max_rssi_path_b = p_dm_fat_table->antAveRSSI_pathB[i]; + pckcnt_path_b = p_dm_fat_table->antRSSIcnt_pathB[i]; + target_ant_path_b = (u8) i; } - if(pDM_FatTable->antAveRSSI_pathB[i] == MaxRSSI_pathB) - { - if(pDM_FatTable ->antRSSIcnt_pathB > Pckcnt_pathB) - { - MaxRSSI_pathB = pDM_FatTable->antAveRSSI_pathB[i]; - TargetAnt_pathB = (u1Byte) i; - } - } - if (pDM_Odm->fat_print_rssi==1) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{Path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d )) \n", - i, pDM_FatTable->antSumRSSI_pathB[i], i, pDM_FatTable->antRSSIcnt_pathB[i], i, pDM_FatTable->antAveRSSI_pathB[i])); + if (p_dm_fat_table->antAveRSSI_pathB[i] == max_rssi_path_b) { + if (p_dm_fat_table->antRSSIcnt_pathB > pckcnt_path_b) { + max_rssi_path_b = p_dm_fat_table->antAveRSSI_pathB[i]; + target_ant_path_b = (u8) i; + } + } + if (p_dm_odm->fat_print_rssi == 1) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d ))\n", + i, p_dm_fat_table->antSumRSSI_pathB[i], i, p_dm_fat_table->antRSSIcnt_pathB[i], i, p_dm_fat_table->antAveRSSI_pathB[i])); } } - #endif - */ +#endif +#endif - //1 DECISION STATE + /* 1 DECISION STATE */ - //2 Select TRX Antenna + /* 2 Select TRX Antenna */ - phydm_FastTraining_enable(pDM_Odm, FAT_OFF); + phydm_fast_training_enable(p_dm_odm, FAT_OFF); - //3 [path-A]--------------------------- - if(bPktFilterMacth_pathA == FALSE) - { - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{Path-A}: None Packet is matched\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{Path-A}: None Packet is matched\n")); - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - } - else - { - ODM_RT_TRACE("TargetAnt_pathA = (( %d )) , MaxRSSI_pathA = (( %d )) \n",TargetAnt_pathA,MaxRSSI_pathA); + /* 3 [path-A]--------------------------- */ + if (is_pkt_filter_macth_path_a == false) { + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{path-A}: None Packet is matched\n")); */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{path-A}: None Packet is matched\n")); + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + } else { + ODM_RT_TRACE("target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n", target_ant_path_a, max_rssi_path_a); - //3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt_pathA); - } - else if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, TargetAnt_pathA);//Optional RX [pth-A] + /* 3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT */ + if (p_dm_odm->support_ic_type == ODM_RTL8188E) + odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); + else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(p_dm_odm, 0xB38, BIT(8) | BIT7 | BIT6, target_ant_path_a); /* Optional RX [pth-A] */ } - //3 [ update TX ant ] - odm_UpdateTxAnt(pDM_Odm, TargetAnt_pathA, (pDM_FatTable->TrainIdx)); + /* 3 [ update TX ant ] */ + odm_update_tx_ant(p_dm_odm, target_ant_path_a, (p_dm_fat_table->train_idx)); - if(TargetAnt_pathA == 0) - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - } - /* - #if(RTL8192E_SUPPORT == 1) - //3 [path-B]--------------------------- - if(bPktFilterMacth_pathB == FALSE) - { - if (pDM_Odm->fat_print_rssi==1) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***[%d]{Path-B}: None Packet is matched\n\n\n",__LINE__)); - } + if (target_ant_path_a == 0) + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); } - else - { - if (pDM_Odm->fat_print_rssi==1) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - (" ***TargetAnt_pathB = (( %d )) *** MaxRSSI = (( %d ))***\n\n\n",TargetAnt_pathB,MaxRSSI_pathB)); +#if 0 +#if (RTL8192E_SUPPORT == 1) + /* 3 [path-B]--------------------------- */ + if (is_pkt_filter_macth_path_b == false) { + if (p_dm_odm->fat_print_rssi == 1) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***[%d]{path-B}: None Packet is matched\n\n\n", __LINE__)); + } else { + if (p_dm_odm->fat_print_rssi == 1) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + (" ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n", target_ant_path_b, max_rssi_path_b)); } - ODM_SetBBReg(pDM_Odm, 0xB38 , BIT21|BIT20|BIT19, TargetAnt_pathB); //Default RX is Omni, Optional RX is the best decision by FAT - ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info + odm_set_bb_reg(p_dm_odm, 0xB38, BIT(21) | BIT20 | BIT19, target_ant_path_b); /* Default RX is Omni, Optional RX is the best decision by FAT */ + odm_set_bb_reg(p_dm_odm, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 //from TX Info */ - pDM_FatTable->antsel_pathB[pDM_FatTable->TrainIdx] = TargetAnt_pathB; + p_dm_fat_table->antsel_pathB[p_dm_fat_table->train_idx] = target_ant_path_b; } - #endif - */ +#endif +#endif - //2 Reset Counter - for(i=0; i<(pDM_Odm->fat_comb_a); i++) - { - pDM_FatTable->antSumRSSI[i] = 0; - pDM_FatTable->antRSSIcnt[i] = 0; + /* 2 Reset counter */ + for (i = 0; i < (p_dm_odm->fat_comb_a); i++) { + p_dm_fat_table->ant_sum_rssi[i] = 0; + p_dm_fat_table->ant_rssi_cnt[i] = 0; } /* - #if(RTL8192E_SUPPORT == 1) - for(i=0; i<=(pDM_Odm->fat_comb_b); i++) + #if (RTL8192E_SUPPORT == 1) + for(i=0; i<=(p_dm_odm->fat_comb_b); i++) { - pDM_FatTable->antSumRSSI_pathB[i] = 0; - pDM_FatTable->antRSSIcnt_pathB[i] = 0; + p_dm_fat_table->antSumRSSI_pathB[i] = 0; + p_dm_fat_table->antRSSIcnt_pathB[i] = 0; } #endif */ - - pDM_FatTable->FAT_State = FAT_PREPARE_STATE; + + p_dm_fat_table->fat_state = FAT_PREPARE_STATE; return; } - //1 NORMAL STATE - if (pDM_FatTable->FAT_State == FAT_PREPARE_STATE) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Start Prepare State ]\n")); + /* 1 NORMAL STATE */ + if (p_dm_fat_table->fat_state == FAT_PREPARE_STATE) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Start Prepare state ]\n")); - odm_SetNextMACAddrTarget(pDM_Odm); + odm_set_next_mac_addr_target(p_dm_odm); - //2 Prepare Training - pDM_FatTable->FAT_State = FAT_TRAINING_STATE; - phydm_FastTraining_enable(pDM_Odm , FAT_ON); - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); //enable HW AntDiv - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Start Training State]\n")); + /* 2 Prepare Training */ + p_dm_fat_table->fat_state = FAT_TRAINING_STATE; + phydm_fast_training_enable(p_dm_odm, FAT_ON); + odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); /* enable HW AntDiv */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Start Training state]\n")); - ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //ms + odm_set_timer(p_dm_odm, &p_dm_odm->fast_ant_training_timer, p_dm_odm->antdiv_intvl); /* ms */ } - + } -VOID -odm_FastAntTrainingCallback( - IN PVOID pDM_VOID - ) +void +odm_fast_ant_training_callback( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER padapter = pDM_Odm->Adapter; - if(padapter->net_closed == _TRUE) - return; - //if(*pDM_Odm->pbNet_closed == TRUE) - // return; + struct _ADAPTER *padapter = p_dm_odm->adapter; + if (padapter->net_closed == _TRUE) + return; + /* if(*p_dm_odm->p_is_net_closed == true) */ + /* return; */ #endif #if USE_WORKITEM - ODM_ScheduleWorkItem(&pDM_Odm->FastAntTrainingWorkitem); + odm_schedule_work_item(&p_dm_odm->fast_ant_training_workitem); #else - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_FastAntTrainingCallback****** \n")); - odm_FastAntTraining(pDM_Odm); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_fast_ant_training_callback******\n")); + odm_fast_ant_training(p_dm_odm); #endif } -VOID -odm_FastAntTrainingWorkItemCallback( - IN PVOID pDM_VOID - ) +void +odm_fast_ant_training_work_item_callback( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_FastAntTrainingWorkItemCallback****** \n")); - odm_FastAntTraining(pDM_Odm); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_fast_ant_training_work_item_callback******\n")); + odm_fast_ant_training(p_dm_odm); } #endif -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 -u4Byte -phydm_construct_hl_beam_codeword( - IN PVOID pDM_VOID, - IN u4Byte *beam_pattern_idx, - IN u4Byte ant_num - ) +u32 +phydm_construct_hb_rfu_codeword_type2( + void *p_dm_void, + u32 beam_set_idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - u4Byte codeword = 0; - u4Byte data_tmp; - u4Byte i; - u4Byte break_counter = 0; - - if (ant_num < 8) { - for (i = 0; i < (pdm_sat_table->ant_num_total); i++) { - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] ));*/ - if ((i < (pdm_sat_table->first_train_ant-1)) || (break_counter >= (pdm_sat_table->ant_num))) { - data_tmp = 0; - /**/ - } else { - - break_counter++; - - if (beam_pattern_idx[i] == 0) { - - if (*pDM_Odm->pBandType == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[0]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[0]; - - } else if (beam_pattern_idx[i] == 1) { - - - if (*pDM_Odm->pBandType == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[1]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[1]; - - } else if (beam_pattern_idx[i] == 2) { + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + u32 sync_codeword = 0x7f; + u32 codeword = 0; + u32 data_tmp = 0; + u32 i; - if (*pDM_Odm->pBandType == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[2]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[2]; - - } else if (beam_pattern_idx[i] == 3) { - - if (*pDM_Odm->pBandType == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[3]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[3]; - } - } + for (i = 0; i < pdm_sat_table->ant_num_total; i++) { + if (*p_dm_odm->p_band_type == ODM_BAND_5G) + data_tmp = pdm_sat_table->rfu_codeword_table_5g[beam_set_idx][i]; + else + data_tmp = pdm_sat_table->rfu_codeword_table_2g[beam_set_idx][i]; - codeword |= (data_tmp<<(i*4)); - - } + codeword |= (data_tmp << (i * pdm_sat_table->rfu_each_ant_bit_num)); } + codeword = (codeword<<8) | sync_codeword; + return codeword; } -VOID -phydm_update_beam_pattern( - IN PVOID pDM_VOID, - IN u4Byte codeword, - IN u4Byte codeword_length - ) +void +phydm_update_beam_pattern_type2( + void *p_dm_void, + u32 codeword, + u32 codeword_length +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - u1Byte i; - BOOLEAN beam_ctrl_signal; - u4Byte one = 0x1; - u4Byte reg44_tmp_p, reg44_tmp_n, reg44_ori; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set Beam Pattern =0x%x\n", codeword)); - - reg44_ori = ODM_GetMACReg(pDM_Odm, 0x44, bMaskDWord); - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_ori =0x%x\n", reg44_ori));*/ - - for (i = 0; i <= (codeword_length-1); i++) { - beam_ctrl_signal = (BOOLEAN)((codeword&BIT(i)) >> i); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + u8 i; + boolean beam_ctrl_signal; + u32 one = 0x1; + u32 reg44_tmp_p, reg44_tmp_n, reg44_ori; + u8 devide_num = 4; - if (pDM_Odm->DebugComponents & ODM_COMP_ANT_DIV) { - - if (i == (codeword_length-1)) { - DbgPrint("%d ]\n", beam_ctrl_signal); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set codeword = ((0x%x))\n", codeword)); + + reg44_ori = odm_get_mac_reg(p_dm_odm, 0x44, MASKDWORD); + reg44_tmp_p = reg44_ori; + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_ori =0x%x\n", reg44_ori));*/ + + /*devide_num = (pdm_sat_table->rfu_protocol_type == 2) ? 8 : 4;*/ + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i); + + #if 1 + if (p_dm_odm->debug_components & ODM_COMP_ANT_DIV) { + + if (i == (codeword_length - 1)) { + dbg_print("%d ]\n", beam_ctrl_signal); /**/ } else if (i == 0) { - DbgPrint("Send codeword[1:24] ---> [ %d ", beam_ctrl_signal); + dbg_print("Start sending codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal); /**/ - } else if ((i % 4) == 3) { - DbgPrint("%d | ", beam_ctrl_signal); + } else if ((i % devide_num) == (devide_num-1)) { + dbg_print("%d | ", beam_ctrl_signal); /**/ } else { - DbgPrint("%d ", beam_ctrl_signal); + dbg_print("%d ", beam_ctrl_signal); /**/ } } + #endif - #if 1 - reg44_tmp_p = reg44_ori & (~(BIT11|BIT10)); /*clean bit 10 & 11*/ - reg44_tmp_p |= ((1<<11) | (beam_ctrl_signal<<10)); - reg44_tmp_n = reg44_ori & (~(BIT11|BIT10)); + if (p_dm_odm->support_ic_type == ODM_RTL8821) { + #if (RTL8821A_SUPPORT == 1) + reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT10)); /*clean bit 10 & 11*/ + reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10)); + reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10))); + + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n));*/ + odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); + odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_n); + #endif + } + #if (RTL8822B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n));*/ - ODM_SetMACReg(pDM_Odm, 0x44 , bMaskDWord, reg44_tmp_p); - ODM_SetMACReg(pDM_Odm, 0x44 , bMaskDWord, reg44_tmp_n); - #else - ODM_SetMACReg(pDM_Odm, 0x44 , BIT11|BIT10, ((1<<1) | beam_ctrl_signal)); - ODM_SetMACReg(pDM_Odm, 0x44 , BIT11, 0); - #endif + if (pdm_sat_table->rfu_protocol_type == 2) { + reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*clean bit 8*/ + reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*get new clk high/low, exclusive-or*/ + + + reg44_tmp_p |= (beam_ctrl_signal << 8); + + odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(pdm_sat_table->rfu_protocol_delay_time); + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal));*/ + + } else { + reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT8)); /*clean bit 9 & 8*/ + reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8)); + reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8))); + + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n)); */ + odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(10); + odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_n); + ODM_delay_us(10); + } + } + #endif } } -VOID -phydm_update_rx_idle_beam( - IN PVOID pDM_VOID - ) +void +phydm_update_rx_idle_beam_type2( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - u4Byte i; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + u32 i; - pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(pDM_Odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set target beam_pattern codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); + pdm_sat_table->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(p_dm_odm, pdm_sat_table->rx_idle_beam_set_idx); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Beam ] BeamSet idx = ((%d))\n", pdm_sat_table->rx_idle_beam_set_idx)); + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern_type2(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); +#else + odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); + /*odm_stall_execution(1);*/ +#endif - for (i = 0; i < (pdm_sat_table->ant_num); i++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i, pdm_sat_table->rx_idle_beam[i])); - /**/ - } - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); - #else - ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_workitem); - /*ODM_StallExecution(1);*/ - #endif - pdm_sat_table->pre_codeword = pdm_sat_table->update_beam_codeword; } -VOID -phydm_hl_smart_ant_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) + +void +phydm_hl_smart_ant_debug_type2( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - u4Byte used = *_used; - u4Byte out_len = *_out_len; - u4Byte one = 0x1; - u4Byte codeword_length = pdm_sat_table->data_codeword_bit_num; - u4Byte beam_ctrl_signal, i; - - if (dm_value[0] == 1) { /*fix beam pattern*/ - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + u32 used = *_used; + u32 out_len = *_out_len; + u32 one = 0x1; + u32 codeword_length = pdm_sat_table->rfu_codeword_total_bit_num; + u32 beam_ctrl_signal, i; + u8 devide_num = 4; + char help[] = "-h"; + u32 dm_value[10] = {0}; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]); + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]); + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &dm_value[3]); + PHYDM_SSCANF(input[5], DCMD_DECIMAL, &dm_value[4]); + + + if (strcmp(input[1], help) == 0) { + PHYDM_SNPRINTF((output + used, out_len - used, " 1 {fix_en} {codeword(Hex)}\n")); + PHYDM_SNPRINTF((output + used, out_len - used, " 3 {Fix_training_num_en} {Per_beam_training_pkt_num} {Decision_holding_period}\n")); + PHYDM_SNPRINTF((output + used, out_len - used, " 5 {0:show, 1:2G, 2:5G} {beam_num} {idxA(Hex)} {idxB(Hex)}\n")); + PHYDM_SNPRINTF((output + used, out_len - used, " 7 {0:show, 1:2G, 2:5G} {total_beam_set_num}\n")); + PHYDM_SNPRINTF((output + used, out_len - used, " 8 {0:show, 1:set} {RFU delay time(us)}\n")); + + } else if (dm_value[0] == 1) { /*fix beam pattern*/ + pdm_sat_table->fix_beam_pattern_en = dm_value[1]; - + if (pdm_sat_table->fix_beam_pattern_en == 1) { - + + PHYDM_SSCANF(input[3], DCMD_HEX, &dm_value[2]); pdm_sat_table->fix_beam_pattern_codeword = dm_value[2]; - if (pdm_sat_table->fix_beam_pattern_codeword > (one<fix_beam_pattern_codeword > (one << codeword_length)) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n", pdm_sat_table->fix_beam_pattern_codeword, codeword_length)); + (pdm_sat_table->fix_beam_pattern_codeword) &= 0xffffff; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Auto modify to (0x%x)\n", pdm_sat_table->fix_beam_pattern_codeword)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Auto modify to (0x%x)\n", pdm_sat_table->fix_beam_pattern_codeword)); } - + pdm_sat_table->update_beam_codeword = pdm_sat_table->fix_beam_pattern_codeword; /*---------------------------------------------------------*/ - PHYDM_SNPRINTF((output+used, out_len-used, "Fix Beam Pattern\n")); - for (i = 0; i <= (codeword_length-1); i++) { - beam_ctrl_signal = (BOOLEAN)((pdm_sat_table->update_beam_codeword&BIT(i)) >> i); - - if (i == (codeword_length-1)) { - PHYDM_SNPRINTF((output+used, out_len-used, "%d]\n", beam_ctrl_signal)); + PHYDM_SNPRINTF((output + used, out_len - used, "Fix Beam Pattern\n")); + + /*devide_num = (pdm_sat_table->rfu_protocol_type == 2) ? 8 : 4;*/ + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((pdm_sat_table->update_beam_codeword & BIT(i)) >> i); + + if (i == (codeword_length - 1)) { + PHYDM_SNPRINTF((output + used, out_len - used, "%d]\n", beam_ctrl_signal)); /**/ } else if (i == 0) { - PHYDM_SNPRINTF((output+used, out_len-used, "Send Codeword[1:24] to RFU -> [%d", beam_ctrl_signal)); + PHYDM_SNPRINTF((output + used, out_len - used, "Send Codeword[1:%d] to RFU -> [%d", pdm_sat_table->rfu_codeword_total_bit_num, beam_ctrl_signal)); /**/ - } else if ((i % 4) == 3) { - PHYDM_SNPRINTF((output+used, out_len-used, "%d|", beam_ctrl_signal)); + } else if ((i % devide_num) == (devide_num-1)) { + PHYDM_SNPRINTF((output + used, out_len - used, "%d|", beam_ctrl_signal)); /**/ } else { - PHYDM_SNPRINTF((output+used, out_len-used, "%d", beam_ctrl_signal)); + PHYDM_SNPRINTF((output + used, out_len - used, "%d", beam_ctrl_signal)); /**/ } } /*---------------------------------------------------------*/ - + #if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); + phydm_update_beam_pattern_type2(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); #else - ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_workitem); - /*ODM_StallExecution(1);*/ + odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); + /*odm_stall_execution(1);*/ #endif - } else if (pdm_sat_table->fix_beam_pattern_en == 0) { - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Smart Antenna: Enable\n")); - } - + } else if (pdm_sat_table->fix_beam_pattern_en == 0) + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Smart Antenna: Enable\n")); + } else if (dm_value[0] == 2) { /*set latch time*/ - + pdm_sat_table->latch_time = dm_value[1]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] latch_time =0x%x\n", pdm_sat_table->latch_time)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] latch_time =0x%x\n", pdm_sat_table->latch_time)); } else if (dm_value[0] == 3) { - + pdm_sat_table->fix_training_num_en = dm_value[1]; - + if (pdm_sat_table->fix_training_num_en == 1) { - pdm_sat_table->per_beam_training_pkt_num = (u1Byte)dm_value[2]; - pdm_sat_table->decision_holding_period = (u1Byte)dm_value[3]; - - PHYDM_SNPRINTF((output+used, out_len-used, "[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", + pdm_sat_table->per_beam_training_pkt_num = (u8)dm_value[2]; + pdm_sat_table->decision_holding_period = (u8)dm_value[3]; + + PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); } else if (pdm_sat_table->fix_training_num_en == 0) { - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] AUTO per_beam_training_pkt_num\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] AUTO per_beam_training_pkt_num\n")); /**/ } } else if (dm_value[0] == 4) { - + #if 0 if (dm_value[1] == 1) { pdm_sat_table->ant_num = 1; pdm_sat_table->first_train_ant = MAIN_ANT; - + } else if (dm_value[1] == 2) { pdm_sat_table->ant_num = 1; pdm_sat_table->first_train_ant = AUX_ANT; - + } else if (dm_value[1] == 3) { pdm_sat_table->ant_num = 2; pdm_sat_table->first_train_ant = MAIN_ANT; } - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Set Ant Num = (( %d )), first_train_ant = (( %d ))\n", - pdm_sat_table->ant_num, (pdm_sat_table->first_train_ant-1))); - } else if (dm_value[0] == 5) { + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set ant Num = (( %d )), first_train_ant = (( %d ))\n", + pdm_sat_table->ant_num, (pdm_sat_table->first_train_ant - 1))); + #endif + } else if (dm_value[0] == 5) { /*set beam set table*/ - if (dm_value[1] <= 3) { - pdm_sat_table->rfu_codeword_table[dm_value[1]] = dm_value[2]; - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", - dm_value[1], dm_value[2])); - } else { - for (i = 0; i < 4; i++) { - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", - i, pdm_sat_table->rfu_codeword_table[i])); + PHYDM_SSCANF(input[4], DCMD_HEX, &dm_value[3]); + PHYDM_SSCANF(input[5], DCMD_HEX, &dm_value[4]); + + if (dm_value[1] == 1) { /*2G*/ + if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { + pdm_sat_table->rfu_codeword_table_2g[dm_value[2] ][0] = (u8)dm_value[3]; + pdm_sat_table->rfu_codeword_table_2g[dm_value[2] ][1] = (u8)dm_value[4]; + PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Set 2G Table[%d] = [A:0x%x, B:0x%x]\n",dm_value[2], dm_value[3], dm_value[4])); + } + + } else if (dm_value[1] == 2) { /*5G*/ + if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { + pdm_sat_table->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3]; + pdm_sat_table->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4]; + PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",dm_value[2], dm_value[3], dm_value[4])); + } + } else if (dm_value[1] == 0) { + PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] 2G Beam Table==============>\n")); + for (i = 0; i < pdm_sat_table->total_beam_set_num_2g; i++) { + PHYDM_SNPRINTF((output + used, out_len - used, "2G Table[%d] = [A:0x%x, B:0x%x]\n", + i, pdm_sat_table->rfu_codeword_table_2g[i][0], pdm_sat_table->rfu_codeword_table_2g[i][1])); + } + PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] 5G Beam Table==============>\n")); + for (i = 0; i < pdm_sat_table->total_beam_set_num_5g; i++) { + PHYDM_SNPRINTF((output + used, out_len - used, "5G Table[%d] = [A:0x%x, B:0x%x]\n", + i, pdm_sat_table->rfu_codeword_table_5g[i][0], pdm_sat_table->rfu_codeword_table_5g[i][1])); } } - } else if (dm_value[0] == 6) { - if (dm_value[1] <= 3) { - pdm_sat_table->rfu_codeword_table_5g[dm_value[1]] = dm_value[2]; - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", - dm_value[1], dm_value[2])); + } else if (dm_value[0] == 6) { + #if 0 + if (dm_value[1] == 0) { + if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { + pdm_sat_table->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3]; + pdm_sat_table->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4]; + PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",dm_value[2], dm_value[3], dm_value[4])); + } } else { - for (i = 0; i < 4; i++) { - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", - i, pdm_sat_table->rfu_codeword_table_5g[i])); + for (i = 0; i < pdm_sat_table->total_beam_set_num_5g; i++) { + PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Read 5G Table[%d] = [A:0x%x, B:0x%x]\n", + i, pdm_sat_table->rfu_codeword_table_5g[i][0], pdm_sat_table->rfu_codeword_table_5g[i][1])); } } + #endif } else if (dm_value[0] == 7) { - if (dm_value[1] <= 4) { - - pdm_sat_table->beam_patten_num_each_ant = dm_value[1]; - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Set Beam number = (( %d ))\n", - pdm_sat_table->beam_patten_num_each_ant)); - } else { - - PHYDM_SNPRINTF((output+used, out_len-used, "[ SmartAnt ] Show Beam number = (( %d ))\n", - pdm_sat_table->beam_patten_num_each_ant)); + if (dm_value[1] == 1) { + + pdm_sat_table->total_beam_set_num_2g = (u8)(dm_value[2]); + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] total_beam_set_num_2g = ((%d))\n", pdm_sat_table->total_beam_set_num_2g)); + + } else if (dm_value[1] == 2) { + + pdm_sat_table->total_beam_set_num_5g = (u8)(dm_value[2]); + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] total_beam_set_num_5g = ((%d))\n", pdm_sat_table->total_beam_set_num_5g)); + } else if (dm_value[1] == 0) { + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Show total_beam_set_num{2g,5g} = {%d,%d}\n", + pdm_sat_table->total_beam_set_num_2g, pdm_sat_table->total_beam_set_num_5g)); } + + } else if (dm_value[0] == 8) { + + if (dm_value[1] == 1) { + pdm_sat_table->rfu_protocol_delay_time = (u16)(dm_value[2]); + PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Set rfu_protocol_delay_time = ((%d))\n", pdm_sat_table->rfu_protocol_delay_time)); + } else if (dm_value[1] == 0) { + PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Read rfu_protocol_delay_time = ((%d))\n", pdm_sat_table->rfu_protocol_delay_time)); + } } - -} +} void -phydm_set_all_ant_same_beam_num( - IN PVOID pDM_VOID - ) +phydm_set_rfu_beam_pattern_type2( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) { /*2Ant for 8821A*/ - - pdm_sat_table->rx_idle_beam[0] = pdm_sat_table->fast_training_beam_num; - pdm_sat_table->rx_idle_beam[1] = pdm_sat_table->fast_training_beam_num; - } - - pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(pDM_Odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); + if (p_dm_odm->ant_div_type != HL_SW_SMART_ANT_TYPE2) + return; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training beam_set index = (( 0x%x ))\n", pdm_sat_table->fast_training_beam_num)); + pdm_sat_table->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(p_dm_odm, pdm_sat_table->fast_training_beam_num); #if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); + phydm_update_beam_pattern_type2(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); #else - ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_workitem); - /*ODM_StallExecution(1);*/ + odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); + /*odm_stall_execution(1);*/ #endif } -VOID -odm_FastAntTraining_hl_smart_antenna_type1( - IN PVOID pDM_VOID - ) +void +phydm_fast_ant_training_hl_smart_antenna_type2( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - pFAT_T pDM_FatTable = &(pDM_Odm->DM_FatTable); - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - u4Byte codeword = 0, i, j; - u4Byte TargetAnt; - u4Byte avg_rssi_tmp, avg_rssi_tmp_ma; - u4Byte target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0}; - u4Byte max_beam_ant_rssi = 0; - u4Byte target_ant_beam[SUPPORT_RF_PATH_NUM] = {0}; - u4Byte beam_tmp; - u1Byte next_ant; - u4Byte rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; - u4Byte rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; - u4Byte rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0}; - u1Byte per_beam_rssi_diff_tmp = 0, training_pkt_num_offset; - u4Byte break_counter = 0; - u4Byte used_ant; - - - if (!pDM_Odm->bLinked) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - - if (pDM_FatTable->bBecomeLinked == TRUE) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Link -> no Link\n")); - pDM_FatTable->FAT_State = FAT_BEFORE_LINK_STATE; - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", pDM_FatTable->FAT_State)); - - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &(p_dm_odm->dm_fat_table); + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + u32 codeword = 0; + u8 i = 0, j=0; + u8 avg_rssi_tmp; + u8 avg_rssi_tmp_ma; + u8 max_beam_ant_rssi = 0; + u8 rssi_target_beam = 0, target_beam_max_rssi = 0; + u8 evm1ss_target_beam = 0, evm2ss_target_beam = 0; + u32 target_beam_max_evm1ss = 0, target_beam_max_evm2ss = 0; + u32 beam_tmp; + u8 per_beam_val_diff_tmp = 0, training_pkt_num_offset; + u32 avg_evm2ss[2] = {0}, avg_evm2ss_sum = 0; + u32 avg_evm1ss = 0; + u32 beam_path_evm_2ss_cnt_all = 0; /*sum of all 2SS-pattern cnt*/ + u32 beam_path_evm_1ss_cnt_all = 0; /*sum of all 1SS-pattern cnt*/ + u8 decision_type; + + if (!p_dm_odm->is_linked) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + + if (p_dm_fat_table->is_become_linked == true) { + + pdm_sat_table->decision_holding_period = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Link->no Link\n")); + p_dm_fat_table->fat_state = FAT_BEFORE_LINK_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", p_dm_fat_table->fat_state)); + p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; } return; - + } else { - if (pDM_FatTable->bBecomeLinked == FALSE) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); - - pDM_FatTable->FAT_State = FAT_PREPARE_STATE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", pDM_FatTable->FAT_State)); - + if (p_dm_fat_table->is_become_linked == false) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); + + p_dm_fat_table->fat_state = FAT_PREPARE_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", p_dm_fat_table->fat_state)); + /*pdm_sat_table->fast_training_beam_num = 0;*/ - /*phydm_set_all_ant_same_beam_num(pDM_Odm);*/ - - pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + /*phydm_set_rfu_beam_pattern_type2(p_dm_odm);*/ + + p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; } } - if (*(pDM_FatTable->pForceTxAntByDesc) == FALSE) { - if (pDM_Odm->bOneEntryOnly == TRUE) - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - else - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); - } - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("HL Smart Ant Training: State (( %d ))\n", pDM_FatTable->FAT_State));*/ + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("HL Smart ant Training: state (( %d ))\n", p_dm_fat_table->fat_state));*/ /* [DECISION STATE] */ /*=======================================================================================*/ - if (pDM_FatTable->FAT_State == FAT_DECISION_STATE) { + if (p_dm_fat_table->fat_state == FAT_DECISION_STATE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 3. In Decision State]\n")); - phydm_FastTraining_enable(pDM_Odm , FAT_OFF); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 3. In Decision state]\n")); - break_counter = 0; /*compute target beam in each antenna*/ - for (i = (pdm_sat_table->first_train_ant-1); i < pdm_sat_table->ant_num_total; i++) { - for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { - if (pdm_sat_table->pkt_rssi_cnt[i][j] == 0) { - avg_rssi_tmp = pdm_sat_table->pkt_rssi_pre[i][j]; - avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; - avg_rssi_tmp_ma = avg_rssi_tmp; - } else { - avg_rssi_tmp = (pdm_sat_table->pkt_rssi_sum[i][j]) / (pdm_sat_table->pkt_rssi_cnt[i][j]); - avg_rssi_tmp_ma = (avg_rssi_tmp + pdm_sat_table->pkt_rssi_pre[i][j])>>1; - } + for (j = 0; j < (pdm_sat_table->total_beam_set_num); j++) { - rssi_sorting_seq[j] = avg_rssi_tmp; - pdm_sat_table->pkt_rssi_pre[i][j] = avg_rssi_tmp; + /*[Decision1: RSSI]-------------------------------------------------------------------*/ + if (pdm_sat_table->statistic_pkt_cnt[j] == 0) { /*if new RSSI = 0 -> MA_RSSI-=2*/ + avg_rssi_tmp = pdm_sat_table->beam_set_avg_rssi_pre[j]; + avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; + avg_rssi_tmp_ma = avg_rssi_tmp; + } else { + avg_rssi_tmp = (u8)((pdm_sat_table->beam_set_rssi_avg_sum[j]) / (pdm_sat_table->statistic_pkt_cnt[j])); + avg_rssi_tmp_ma = (avg_rssi_tmp + pdm_sat_table->beam_set_avg_rssi_pre[j]) >> 1; + } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n", - i, j, pdm_sat_table->pkt_rssi_cnt[i][j], avg_rssi_tmp_ma, avg_rssi_tmp)); - - if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) { - target_ant_beam[i] = j; - target_ant_beam_max_rssi[i] = avg_rssi_tmp; - } + pdm_sat_table->beam_set_avg_rssi_pre[j] = avg_rssi_tmp; - /*reset counter value*/ - pdm_sat_table->pkt_rssi_sum[i][j] = 0; - pdm_sat_table->pkt_rssi_cnt[i][j] = 0; - + if (avg_rssi_tmp > target_beam_max_rssi) { + rssi_target_beam = j; + target_beam_max_rssi = avg_rssi_tmp; } - pdm_sat_table->rx_idle_beam[i] = target_ant_beam[i]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("---------> Target of Ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n", - i, target_ant_beam[i], target_ant_beam_max_rssi[i])); - /*sorting*/ - /* - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3])); - */ + /*[Decision2: EVM 2ss]-------------------------------------------------------------------*/ + if (pdm_sat_table->beam_path_evm_2ss_cnt[j] != 0) { + avg_evm2ss[0] = pdm_sat_table->beam_path_evm_2ss_sum[j][0] / pdm_sat_table->beam_path_evm_2ss_cnt[j]; + avg_evm2ss[1] = pdm_sat_table->beam_path_evm_2ss_sum[j][1] / pdm_sat_table->beam_path_evm_2ss_cnt[j]; + avg_evm2ss_sum = avg_evm2ss[0] + avg_evm2ss[1]; + beam_path_evm_2ss_cnt_all += pdm_sat_table->beam_path_evm_2ss_cnt[j]; - /*phydm_seq_sorting(pDM_Odm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/ - - /* - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rank_idx_seq = [%d, %d, %d, %d]\n", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rank_idx_out = [%d, %d, %d, %d]\n", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3])); - */ + pdm_sat_table->beam_set_avg_evm_2ss_pre[j] = (u8)avg_evm2ss_sum; + } - if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) { - TargetAnt = i; - max_beam_ant_rssi = target_ant_beam_max_rssi[i]; - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Target of Ant = (( %d )) max_beam_ant_rssi = (( %d ))\n", - TargetAnt, max_beam_ant_rssi));*/ + if (avg_evm2ss_sum > target_beam_max_evm2ss) { + evm2ss_target_beam = j; + target_beam_max_evm2ss = avg_evm2ss_sum; } - break_counter++; - if (break_counter >= (pdm_sat_table->ant_num)) - break; + + /*[Decision3: EVM 1ss]-------------------------------------------------------------------*/ + if (pdm_sat_table->beam_path_evm_1ss_cnt[j] != 0) { + avg_evm1ss = pdm_sat_table->beam_path_evm_1ss_sum[j] / pdm_sat_table->beam_path_evm_1ss_cnt[j]; + beam_path_evm_1ss_cnt_all += pdm_sat_table->beam_path_evm_1ss_cnt[j]; + + pdm_sat_table->beam_set_avg_evm_1ss_pre[j] = (u8)avg_evm1ss; + } + + if (avg_evm1ss > target_beam_max_evm1ss) { + evm1ss_target_beam = j; + target_beam_max_evm1ss = avg_evm1ss; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Beam[%d] Pkt_cnt=(( %d )), avg{MA,rssi}={%d, %d}, EVM1={%d}, EVM2={%d, %d, %d}\n", + j, pdm_sat_table->statistic_pkt_cnt[j], avg_rssi_tmp_ma, avg_rssi_tmp, avg_evm1ss, avg_evm2ss[0], avg_evm2ss[1], avg_evm2ss_sum)); + + /*reset counter value*/ + pdm_sat_table->beam_set_rssi_avg_sum[j] = 0; + pdm_sat_table->beam_path_rssi_sum[j][0] = 0; + pdm_sat_table->beam_path_rssi_sum[j][1] = 0; + pdm_sat_table->statistic_pkt_cnt[j] = 0; + + pdm_sat_table->beam_path_evm_2ss_sum[j][0] = 0; + pdm_sat_table->beam_path_evm_2ss_sum[j][1] = 0; + pdm_sat_table->beam_path_evm_2ss_cnt[j] = 0; + + pdm_sat_table->beam_path_evm_1ss_sum[j] = 0; + pdm_sat_table->beam_path_evm_1ss_cnt[j] = 0; } - #ifdef CONFIG_FAT_PATCH - break_counter = 0; - for (i = (pdm_sat_table->first_train_ant-1); i < pdm_sat_table->ant_num_total; i++) { - for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { - - per_beam_rssi_diff_tmp = (u1Byte)(max_beam_ant_rssi - pdm_sat_table->pkt_rssi_pre[i][j]); - pdm_sat_table->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant[%d], Beam[%d]: RSSI_diff= ((%d))\n", - i, j, per_beam_rssi_diff_tmp)); + /*[Joint Decision]-------------------------------------------------------------------*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--->1.[RSSI] Target Beam(( %d )) RSSI_max=((%d))\n", rssi_target_beam, target_beam_max_rssi)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--->2.[Evm2SS] Target Beam(( %d )) EVM2SS_max=((%d))\n", evm2ss_target_beam, target_beam_max_evm2ss)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--->3.[Evm1SS] Target Beam(( %d )) EVM1SS_max=((%d))\n", evm1ss_target_beam, target_beam_max_evm1ss)); + + if (target_beam_max_rssi <= 10) { + pdm_sat_table->rx_idle_beam_set_idx = rssi_target_beam; + decision_type = 1; + } else { + if (beam_path_evm_2ss_cnt_all != 0) { + pdm_sat_table->rx_idle_beam_set_idx = evm2ss_target_beam; + decision_type = 2; + } else if (beam_path_evm_1ss_cnt_all != 0) { + pdm_sat_table->rx_idle_beam_set_idx = evm1ss_target_beam; + decision_type = 3; + } else { + pdm_sat_table->rx_idle_beam_set_idx = rssi_target_beam; + decision_type = 1; } - break_counter++; - if (break_counter >= (pdm_sat_table->ant_num)) - break; } - #endif - if (TargetAnt == 0) - TargetAnt = MAIN_ANT; - else if (TargetAnt == 1) - TargetAnt = AUX_ANT; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("---> Decision_type=((%d)), Final Target Beam(( %d ))\n", decision_type, pdm_sat_table->rx_idle_beam_set_idx )); - if (pdm_sat_table->ant_num > 1) { - /* [ update RX ant ]*/ - ODM_UpdateRxIdleAnt(pDM_Odm, (u1Byte)TargetAnt); + /*Calculate packet counter offset*/ + for (j = 0; j < (pdm_sat_table->total_beam_set_num); j++) { - /* [ update TX ant ]*/ - odm_UpdateTxAnt(pDM_Odm, (u1Byte)TargetAnt, (pDM_FatTable->TrainIdx)); + if (decision_type == 1) { + per_beam_val_diff_tmp = target_beam_max_rssi - pdm_sat_table->beam_set_avg_rssi_pre[j]; + + } else if (decision_type == 2) { + per_beam_val_diff_tmp = ((u8)target_beam_max_evm2ss - pdm_sat_table->beam_set_avg_evm_2ss_pre[j]) >> 1; + } else if (decision_type == 3) { + per_beam_val_diff_tmp = (u8)target_beam_max_evm1ss - pdm_sat_table->beam_set_avg_evm_1ss_pre[j]; + } + pdm_sat_table->beam_set_train_val_diff[j] = per_beam_val_diff_tmp; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Beam_Set[%d]: diff= ((%d))\n", j, per_beam_val_diff_tmp)); } - - /*set beam in each antenna*/ - phydm_update_rx_idle_beam(pDM_Odm); - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); - pDM_FatTable->FAT_State = FAT_PREPARE_STATE; + /*set beam in each antenna*/ + phydm_update_rx_idle_beam_type2(p_dm_odm); + p_dm_fat_table->fat_state = FAT_PREPARE_STATE; - } + } /* [TRAINING STATE] */ - else if (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2. In Training State]\n")); + else if (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2. In Training state]\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n", + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("curr_beam_idx = (( %d )), pre_beam_idx = (( %d ))\n", pdm_sat_table->fast_training_beam_num, pdm_sat_table->pre_fast_training_beam_num)); - - if (pdm_sat_table->fast_training_beam_num > pdm_sat_table->pre_fast_training_beam_num) { - + + if (pdm_sat_table->fast_training_beam_num > pdm_sat_table->pre_fast_training_beam_num) + pdm_sat_table->force_update_beam_en = 0; - } else { - + else { + pdm_sat_table->force_update_beam_en = 1; - + pdm_sat_table->pkt_counter = 0; beam_tmp = pdm_sat_table->fast_training_beam_num; - if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant-1)) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", pdm_sat_table->fast_training_beam_num)); - pDM_FatTable->FAT_State = FAT_DECISION_STATE; - odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); + if (pdm_sat_table->fast_training_beam_num >= ((u32)pdm_sat_table->total_beam_set_num - 1)) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", pdm_sat_table->fast_training_beam_num)); + p_dm_fat_table->fat_state = FAT_DECISION_STATE; + phydm_fast_ant_training_hl_smart_antenna_type2(p_dm_odm); } else { pdm_sat_table->fast_training_beam_num++; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - phydm_set_all_ant_same_beam_num(pDM_Odm); - pDM_FatTable->FAT_State = FAT_TRAINING_STATE; - + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); + phydm_set_rfu_beam_pattern_type2(p_dm_odm); + p_dm_fat_table->fat_state = FAT_TRAINING_STATE; + } } pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Pre_Beam =(( %d ))\n", pdm_sat_table->pre_fast_training_beam_num)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Pre_Beam =(( %d ))\n", pdm_sat_table->pre_fast_training_beam_num)); } - /* [Prepare State] */ + /* [Prepare state] */ /*=======================================================================================*/ - else if (pDM_FatTable->FAT_State == FAT_PREPARE_STATE) { + else if (p_dm_fat_table->fat_state == FAT_PREPARE_STATE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n\n[ 1. In Prepare State]\n")); - - if (pDM_Odm->pre_TrafficLoad == (pDM_Odm->TrafficLoad)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n\n[ 1. In Prepare state]\n")); + + if (p_dm_odm->pre_traffic_load == (p_dm_odm->traffic_load)) { if (pdm_sat_table->decision_holding_period != 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Holding_period = (( %d )), return!!!\n", pdm_sat_table->decision_holding_period)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Holding_period = (( %d )), return!!!\n", pdm_sat_table->decision_holding_period)); pdm_sat_table->decision_holding_period--; return; } } - - + /* Set training packet number*/ if (pdm_sat_table->fix_training_num_en == 0) { - switch (pDM_Odm->TrafficLoad) { + switch (p_dm_odm->traffic_load) { - case TRAFFIC_HIGH: + case TRAFFIC_HIGH: pdm_sat_table->per_beam_training_pkt_num = 8; pdm_sat_table->decision_holding_period = 2; break; - case TRAFFIC_MID: + case TRAFFIC_MID: pdm_sat_table->per_beam_training_pkt_num = 6; pdm_sat_table->decision_holding_period = 3; break; - case TRAFFIC_LOW: + case TRAFFIC_LOW: pdm_sat_table->per_beam_training_pkt_num = 3; /*ping 60000*/ pdm_sat_table->decision_holding_period = 4; break; - case TRAFFIC_ULTRA_LOW: + case TRAFFIC_ULTRA_LOW: pdm_sat_table->per_beam_training_pkt_num = 1; pdm_sat_table->decision_holding_period = 6; break; default: - break; + break; } } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\n", - pdm_sat_table->fix_training_num_en , pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); - - - #ifdef CONFIG_FAT_PATCH - break_counter = 0; - for (i = (pdm_sat_table->first_train_ant-1); i < pdm_sat_table->ant_num_total; i++) { - for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { - - per_beam_rssi_diff_tmp = pdm_sat_table->beam_train_rssi_diff[i][j]; - training_pkt_num_offset = per_beam_rssi_diff_tmp; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TrafficLoad = (( %d )), Fix_beam = (( %d )), per_beam_training_pkt_num = (( %d )), decision_holding_period = ((%d))\n", + p_dm_odm->traffic_load, pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); - if ((pdm_sat_table->per_beam_training_pkt_num) > training_pkt_num_offset) - pdm_sat_table->beam_train_cnt[i][j] = pdm_sat_table->per_beam_training_pkt_num - training_pkt_num_offset; - else - pdm_sat_table->beam_train_cnt[i][j] = 1; - - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant[%d]: Beam_num-(( %d )) training_pkt_num = ((%d))\n", - i, j, pdm_sat_table->beam_train_cnt[i][j])); - } - break_counter++; - if (break_counter >= (pdm_sat_table->ant_num)) - break; + /*Beam_set number*/ + if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + pdm_sat_table->total_beam_set_num = pdm_sat_table->total_beam_set_num_5g; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("5G beam_set num = ((%d))\n", pdm_sat_table->total_beam_set_num)); + } else { + pdm_sat_table->total_beam_set_num = pdm_sat_table->total_beam_set_num_2g; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("2G beam_set num = ((%d))\n", pdm_sat_table->total_beam_set_num)); } - - - phydm_FastTraining_enable(pDM_Odm , FAT_OFF); - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->update_beam_idx = 0; - if (*pDM_Odm->pBandType == ODM_BAND_5G) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set 5G ant\n")); - /*used_ant = (pdm_sat_table->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/ - used_ant = pdm_sat_table->first_train_ant; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set 2.4G ant\n")); - used_ant = pdm_sat_table->first_train_ant; - } + for (j = 0; j < (pdm_sat_table->total_beam_set_num); j++) { - ODM_UpdateRxIdleAnt(pDM_Odm, (u1Byte)used_ant); + training_pkt_num_offset = pdm_sat_table->beam_set_train_val_diff[j]; - #else - /* Set training MAC Addr. of target */ - odm_SetNextMACAddrTarget(pDM_Odm); - phydm_FastTraining_enable(pDM_Odm , FAT_ON); - #endif + if ((pdm_sat_table->per_beam_training_pkt_num) > training_pkt_num_offset) + pdm_sat_table->beam_set_train_cnt[j] = pdm_sat_table->per_beam_training_pkt_num - training_pkt_num_offset; + else + pdm_sat_table->beam_set_train_cnt[j] = 1; - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Beam_Set[ %d ] training_pkt_offset = ((%d)), training_pkt_num = ((%d))\n", + j, pdm_sat_table->beam_set_train_val_diff[j], pdm_sat_table->beam_set_train_cnt[j])); + } + + pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; + pdm_sat_table->update_beam_idx = 0; pdm_sat_table->pkt_counter = 0; + pdm_sat_table->fast_training_beam_num = 0; - phydm_set_all_ant_same_beam_num(pDM_Odm); + phydm_set_rfu_beam_pattern_type2(p_dm_odm); pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - pDM_FatTable->FAT_State = FAT_TRAINING_STATE; + p_dm_fat_table->fat_state = FAT_TRAINING_STATE; } - + } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID +void phydm_beam_switch_workitem_callback( - IN PVOID pContext - ) + void *p_context +) { - PADAPTER pAdapter = (PADAPTER)pContext; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - #if DEV_BUS_TYPE != RT_PCI_INTERFACE +#if DEV_BUS_TYPE != RT_PCI_INTERFACE pdm_sat_table->pkt_skip_statistic_en = 1; - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en)); - - phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); +#endif + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en)); + + phydm_update_beam_pattern_type2(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); - #if DEV_BUS_TYPE != RT_PCI_INTERFACE - /*ODM_StallExecution(pdm_sat_table->latch_time);*/ +#if DEV_BUS_TYPE != RT_PCI_INTERFACE + /*odm_stall_execution(pdm_sat_table->latch_time);*/ pdm_sat_table->pkt_skip_statistic_en = 0; - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en, pdm_sat_table->latch_time)); +#endif + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en, pdm_sat_table->latch_time)); } -VOID +void phydm_beam_decision_workitem_callback( - IN PVOID pContext - ) + void *p_context +) { - PADAPTER pAdapter = (PADAPTER)pContext; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam decision Workitem Callback\n")); - odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); + struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam decision Workitem Callback\n")); + phydm_fast_ant_training_hl_smart_antenna_type2(p_dm_odm); } #endif -#endif /*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ +#elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) -VOID -ODM_AntDivInit( - IN PVOID pDM_VOID - ) +u32 +phydm_construct_hl_beam_codeword( + void *p_dm_void, + u32 *beam_pattern_idx, + u32 ant_num +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + u32 codeword = 0; + u32 data_tmp; + u32 i; + u32 break_counter = 0; + if (ant_num < 8) { + for (i = 0; i < (pdm_sat_table->ant_num_total); i++) { + /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] ));*/ + if ((i < (pdm_sat_table->first_train_ant - 1)) || (break_counter >= (pdm_sat_table->ant_num))) { + data_tmp = 0; + /**/ + } else { - if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] Not Support Antenna Diversity Function\n")); - return; - } - //--- -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n")); - if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC)) - return; - } - else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n")); - if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC)) - return; - } - else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n")); - } + break_counter++; -#endif - //--- + if (beam_pattern_idx[i] == 0) { - //2 [--General---] - pDM_Odm->antdiv_period=0; + if (*p_dm_odm->p_band_type == ODM_BAND_5G) + data_tmp = pdm_sat_table->rfu_codeword_table_5g[0]; + else + data_tmp = pdm_sat_table->rfu_codeword_table[0]; - pDM_FatTable->bBecomeLinked =FALSE; - pDM_FatTable->AntDiv_OnOff =0xff; + } else if (beam_pattern_idx[i] == 1) { - //3 - AP - - #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - - #if (BEAMFORMING_SUPPORT == 1) - #if(DM_ODM_SUPPORT_TYPE == ODM_AP) - odm_BDC_Init(pDM_Odm); - #endif - #endif - - //3 - WIN - - #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pDM_SWAT_Table->Ant5G = MAIN_ANT; - pDM_SWAT_Table->Ant2G = MAIN_ANT; - pDM_FatTable->CCK_counter_main=0; - pDM_FatTable->CCK_counter_aux=0; - pDM_FatTable->OFDM_counter_main=0; - pDM_FatTable->OFDM_counter_aux=0; - #endif - //2 [---Set MAIN_ANT as default antenna if Auto-Ant enable---] - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + if (*p_dm_odm->p_band_type == ODM_BAND_5G) + data_tmp = pdm_sat_table->rfu_codeword_table_5g[1]; + else + data_tmp = pdm_sat_table->rfu_codeword_table[1]; - pDM_Odm->AntType = ODM_AUTO_ANT; + } else if (beam_pattern_idx[i] == 2) { - pDM_FatTable->RxIdleAnt = 0xff; /*to make RX-idle-antenna will be updated absolutly*/ - ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); - phydm_keep_RxAckAnt_By_TxAnt_time( pDM_Odm, 5); /* Timming issue: keep Rx ant after tx for ACK ( 5 x 3.2 mu = 16mu sec)*/ - - //2 [---Set TX Antenna---] - pDM_FatTable->ForceTxAntByDesc = 0; - pDM_FatTable->pForceTxAntByDesc = &(pDM_FatTable->ForceTxAntByDesc); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("pForceTxAntByDesc = %d\n", *pDM_FatTable->pForceTxAntByDesc)); + if (*p_dm_odm->p_band_type == ODM_BAND_5G) + data_tmp = pdm_sat_table->rfu_codeword_table_5g[2]; + else + data_tmp = pdm_sat_table->rfu_codeword_table[2]; - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + } else if (beam_pattern_idx[i] == 3) { - - //2 [--88E---] - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - #if (RTL8188E_SUPPORT == 1) - //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + if (*p_dm_odm->p_band_type == ODM_BAND_5G) + data_tmp = pdm_sat_table->rfu_codeword_table_5g[3]; + else + data_tmp = pdm_sat_table->rfu_codeword_table[3]; + } + } - if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 88E Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - - if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - odm_RX_HWAntDiv_Init_88E(pDM_Odm); - else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - odm_TRX_HWAntDiv_Init_88E(pDM_Odm); - #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) - odm_Smart_HWAntDiv_Init_88E(pDM_Odm); - #endif - #endif - } - - //2 [--92E---] - #if (RTL8192E_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; - - if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8192E Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - - if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) - odm_RX_HWAntDiv_Init_92E(pDM_Odm); - else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - odm_TRX_HWAntDiv_Init_92E(pDM_Odm); - #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) - odm_Smart_HWAntDiv_Init_92E(pDM_Odm); - #endif - - } - #endif - - //2 [--8723B---] - #if (RTL8723B_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8723B) - { - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - - if(pDM_Odm->AntDivType != S0S1_SW_ANTDIV && pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8723B Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - - if( pDM_Odm->AntDivType==S0S1_SW_ANTDIV) - odm_S0S1_SWAntDiv_Init_8723B(pDM_Odm); - else if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV) - odm_TRX_HWAntDiv_Init_8723B(pDM_Odm); - } - #endif - /*2 [--8723D---]*/ - #if (RTL8723D_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8723D) { - if (pDM_Odm->AntDivType == S0S1_TRX_HW_ANTDIV) - odm_TRX_HWAntDiv_Init_8723D(pDM_Odm); - else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8723D Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - } - #endif - //2 [--8811A 8821A---] - #if (RTL8821A_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8821) - { - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - pDM_Odm->AntDivType = HL_SW_SMART_ANT_TYPE1; - - if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) { - - odm_TRX_HWAntDiv_Init_8821A(pDM_Odm); - phydm_hl_smart_ant_type1_init_8821a(pDM_Odm); - } else - #endif - { - /*pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;*/ - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - - if (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV && pDM_Odm->AntDivType != S0S1_SW_ANTDIV) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821A & 8811A Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - odm_TRX_HWAntDiv_Init_8821A(pDM_Odm); - else if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) - odm_S0S1_SWAntDiv_Init_8821A(pDM_Odm); + codeword |= (data_tmp << (i * 4)); + } } - #endif - - //2 [--8821C---] - #if (RTL8821C_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8821C) - { - pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - if (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV ) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821C Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + + return codeword; +} + +void +phydm_update_beam_pattern( + void *p_dm_void, + u32 codeword, + u32 codeword_length +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + u8 i; + boolean beam_ctrl_signal; + u32 one = 0x1; + u32 reg44_tmp_p, reg44_tmp_n, reg44_ori; + u8 devide_num = 4; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set Beam Pattern =0x%x\n", codeword)); + + reg44_ori = odm_get_mac_reg(p_dm_odm, 0x44, MASKDWORD); + reg44_tmp_p = reg44_ori; + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_ori =0x%x\n", reg44_ori));*/ + + devide_num = (pdm_sat_table->rfu_protocol_type == 2) ? 6 : 4; + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i); + + if (p_dm_odm->debug_components & ODM_COMP_ANT_DIV) { + + if (i == (codeword_length - 1)) { + dbg_print("%d ]\n", beam_ctrl_signal); + /**/ + } else if (i == 0) { + dbg_print("Send codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal); + /**/ + } else if ((i % devide_num) == (devide_num-1)) { + dbg_print("%d | ", beam_ctrl_signal); + /**/ + } else { + dbg_print("%d ", beam_ctrl_signal); + /**/ + } + } + + if (p_dm_odm->support_ic_type == ODM_RTL8821) { + #if (RTL8821A_SUPPORT == 1) + reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT10)); /*clean bit 10 & 11*/ + reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10)); + reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10))); + + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n));*/ + odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); + odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_n); + #endif + } + #if (RTL8822B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + + if (pdm_sat_table->rfu_protocol_type == 2) { + + reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*clean bit 8*/ + reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*get new clk high/low, exclusive-or*/ + + + reg44_tmp_p |= (beam_ctrl_signal << 8); + + odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(10); + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal));*/ + + } else { + reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT8)); /*clean bit 9 & 8*/ + reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8)); + reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8))); + + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n)); */ + odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(10); + odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_n); + ODM_delay_us(10); + } + } + #endif + } +} + +void +phydm_update_rx_idle_beam( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + u32 i; + + pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(p_dm_odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set target beam_pattern codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); + + for (i = 0; i < (pdm_sat_table->ant_num); i++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i, pdm_sat_table->rx_idle_beam[i])); + /**/ + } + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); +#else + odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); + /*odm_stall_execution(1);*/ +#endif + + pdm_sat_table->pre_codeword = pdm_sat_table->update_beam_codeword; +} + +void +phydm_hl_smart_ant_debug( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + u32 used = *_used; + u32 out_len = *_out_len; + u32 one = 0x1; + u32 codeword_length = pdm_sat_table->rfu_codeword_total_bit_num; + u32 beam_ctrl_signal, i; + u8 devide_num = 4; + + if (dm_value[0] == 1) { /*fix beam pattern*/ + + pdm_sat_table->fix_beam_pattern_en = dm_value[1]; + + if (pdm_sat_table->fix_beam_pattern_en == 1) { + + pdm_sat_table->fix_beam_pattern_codeword = dm_value[2]; + + if (pdm_sat_table->fix_beam_pattern_codeword > (one << codeword_length)) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n", + pdm_sat_table->fix_beam_pattern_codeword, codeword_length)); + + (pdm_sat_table->fix_beam_pattern_codeword) &= 0xffffff; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Auto modify to (0x%x)\n", pdm_sat_table->fix_beam_pattern_codeword)); + } + + pdm_sat_table->update_beam_codeword = pdm_sat_table->fix_beam_pattern_codeword; + + /*---------------------------------------------------------*/ + PHYDM_SNPRINTF((output + used, out_len - used, "Fix Beam Pattern\n")); + + devide_num = (pdm_sat_table->rfu_protocol_type == 2) ? 6 : 4; + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((pdm_sat_table->update_beam_codeword & BIT(i)) >> i); + + if (i == (codeword_length - 1)) { + PHYDM_SNPRINTF((output + used, out_len - used, "%d]\n", beam_ctrl_signal)); + /**/ + } else if (i == 0) { + PHYDM_SNPRINTF((output + used, out_len - used, "Send Codeword[1:24] to RFU -> [%d", beam_ctrl_signal)); + /**/ + } else if ((i % devide_num) == (devide_num-1)) { + PHYDM_SNPRINTF((output + used, out_len - used, "%d|", beam_ctrl_signal)); + /**/ + } else { + PHYDM_SNPRINTF((output + used, out_len - used, "%d", beam_ctrl_signal)); + /**/ + } + } + /*---------------------------------------------------------*/ + + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); +#else + odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); + /*odm_stall_execution(1);*/ +#endif + } else if (pdm_sat_table->fix_beam_pattern_en == 0) + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Smart Antenna: Enable\n")); + + } else if (dm_value[0] == 2) { /*set latch time*/ + + pdm_sat_table->latch_time = dm_value[1]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] latch_time =0x%x\n", pdm_sat_table->latch_time)); + } else if (dm_value[0] == 3) { + + pdm_sat_table->fix_training_num_en = dm_value[1]; + + if (pdm_sat_table->fix_training_num_en == 1) { + pdm_sat_table->per_beam_training_pkt_num = (u8)dm_value[2]; + pdm_sat_table->decision_holding_period = (u8)dm_value[3]; + + PHYDM_SNPRINTF((output + used, out_len - used, "[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", + pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); + + } else if (pdm_sat_table->fix_training_num_en == 0) { + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] AUTO per_beam_training_pkt_num\n")); + /**/ + } + } else if (dm_value[0] == 4) { + + if (dm_value[1] == 1) { + pdm_sat_table->ant_num = 1; + pdm_sat_table->first_train_ant = MAIN_ANT; + + } else if (dm_value[1] == 2) { + pdm_sat_table->ant_num = 1; + pdm_sat_table->first_train_ant = AUX_ANT; + + } else if (dm_value[1] == 3) { + pdm_sat_table->ant_num = 2; + pdm_sat_table->first_train_ant = MAIN_ANT; + } + + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set ant Num = (( %d )), first_train_ant = (( %d ))\n", + pdm_sat_table->ant_num, (pdm_sat_table->first_train_ant - 1))); + } else if (dm_value[0] == 5) { + + if (dm_value[1] <= 3) { + pdm_sat_table->rfu_codeword_table[dm_value[1]] = dm_value[2]; + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", + dm_value[1], dm_value[2])); + } else { + for (i = 0; i < 4; i++) { + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", + i, pdm_sat_table->rfu_codeword_table[i])); + } + } + } else if (dm_value[0] == 6) { + + if (dm_value[1] <= 3) { + pdm_sat_table->rfu_codeword_table_5g[dm_value[1]] = dm_value[2]; + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", + dm_value[1], dm_value[2])); + } else { + for (i = 0; i < 4; i++) { + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", + i, pdm_sat_table->rfu_codeword_table_5g[i])); + } + } + } else if (dm_value[0] == 7) { + + if (dm_value[1] <= 4) { + + pdm_sat_table->beam_patten_num_each_ant = dm_value[1]; + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set Beam number = (( %d ))\n", + pdm_sat_table->beam_patten_num_each_ant)); + } else { + + PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Show Beam number = (( %d ))\n", + pdm_sat_table->beam_patten_num_each_ant)); + } + } + +} + + +void +phydm_set_all_ant_same_beam_num( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + + if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { /*2ant for 8821A*/ + + pdm_sat_table->rx_idle_beam[0] = pdm_sat_table->fast_training_beam_num; + pdm_sat_table->rx_idle_beam[1] = pdm_sat_table->fast_training_beam_num; + } + + pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(p_dm_odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); +#else + odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); + /*odm_stall_execution(1);*/ +#endif +} + +void +odm_fast_ant_training_hl_smart_antenna_type1( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &(p_dm_odm->dm_fat_table); + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + u32 codeword = 0, i, j; + u32 target_ant; + u32 avg_rssi_tmp, avg_rssi_tmp_ma; + u32 target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0}; + u32 max_beam_ant_rssi = 0; + u32 target_ant_beam[SUPPORT_RF_PATH_NUM] = {0}; + u32 beam_tmp; + u8 next_ant; + u32 rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u32 rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u32 rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u8 per_beam_rssi_diff_tmp = 0, training_pkt_num_offset; + u32 break_counter = 0; + u32 used_ant; + + + if (!p_dm_odm->is_linked) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + + if (p_dm_fat_table->is_become_linked == true) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Link->no Link\n")); + p_dm_fat_table->fat_state = FAT_BEFORE_LINK_STATE; + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", p_dm_fat_table->fat_state)); + + p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + } + return; + + } else { + if (p_dm_fat_table->is_become_linked == false) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); + + p_dm_fat_table->fat_state = FAT_PREPARE_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", p_dm_fat_table->fat_state)); + + /*pdm_sat_table->fast_training_beam_num = 0;*/ + /*phydm_set_all_ant_same_beam_num(p_dm_odm);*/ + + p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + } + } + + if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) { + if (p_dm_odm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + else + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); + } + + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("HL Smart ant Training: state (( %d ))\n", p_dm_fat_table->fat_state));*/ + + /* [DECISION STATE] */ + /*=======================================================================================*/ + if (p_dm_fat_table->fat_state == FAT_DECISION_STATE) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 3. In Decision state]\n")); + phydm_fast_training_enable(p_dm_odm, FAT_OFF); + + break_counter = 0; + /*compute target beam in each antenna*/ + for (i = (pdm_sat_table->first_train_ant - 1); i < pdm_sat_table->ant_num_total; i++) { + for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { + + if (pdm_sat_table->pkt_rssi_cnt[i][j] == 0) { + avg_rssi_tmp = pdm_sat_table->pkt_rssi_pre[i][j]; + avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; + avg_rssi_tmp_ma = avg_rssi_tmp; + } else { + avg_rssi_tmp = (pdm_sat_table->pkt_rssi_sum[i][j]) / (pdm_sat_table->pkt_rssi_cnt[i][j]); + avg_rssi_tmp_ma = (avg_rssi_tmp + pdm_sat_table->pkt_rssi_pre[i][j]) >> 1; + } + + rssi_sorting_seq[j] = avg_rssi_tmp; + pdm_sat_table->pkt_rssi_pre[i][j] = avg_rssi_tmp; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n", + i, j, pdm_sat_table->pkt_rssi_cnt[i][j], avg_rssi_tmp_ma, avg_rssi_tmp)); + + if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) { + target_ant_beam[i] = j; + target_ant_beam_max_rssi[i] = avg_rssi_tmp; + } + + /*reset counter value*/ + pdm_sat_table->pkt_rssi_sum[i][j] = 0; + pdm_sat_table->pkt_rssi_cnt[i][j] = 0; + + } + pdm_sat_table->rx_idle_beam[i] = target_ant_beam[i]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("---------> Target of ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n", + i, target_ant_beam[i], target_ant_beam_max_rssi[i])); + + /*sorting*/ + /* + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3])); + */ + + /*phydm_seq_sorting(p_dm_odm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/ + + /* + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rank_idx_seq = [%d, %d, %d, %d]\n", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rank_idx_out = [%d, %d, %d, %d]\n", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3])); + */ + + if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) { + target_ant = i; + max_beam_ant_rssi = target_ant_beam_max_rssi[i]; + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Target of ant = (( %d )) max_beam_ant_rssi = (( %d ))\n", + target_ant, max_beam_ant_rssi));*/ + } + break_counter++; + if (break_counter >= (pdm_sat_table->ant_num)) + break; + } + +#ifdef CONFIG_FAT_PATCH + break_counter = 0; + for (i = (pdm_sat_table->first_train_ant - 1); i < pdm_sat_table->ant_num_total; i++) { + for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { + + per_beam_rssi_diff_tmp = (u8)(max_beam_ant_rssi - pdm_sat_table->pkt_rssi_pre[i][j]); + pdm_sat_table->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ant[%d], Beam[%d]: RSSI_diff= ((%d))\n", + i, j, per_beam_rssi_diff_tmp)); + } + break_counter++; + if (break_counter >= (pdm_sat_table->ant_num)) + break; + } +#endif + + if (target_ant == 0) + target_ant = MAIN_ANT; + else if (target_ant == 1) + target_ant = AUX_ANT; + + if (pdm_sat_table->ant_num > 1) { + /* [ update RX ant ]*/ + odm_update_rx_idle_ant(p_dm_odm, (u8)target_ant); + + /* [ update TX ant ]*/ + odm_update_tx_ant(p_dm_odm, (u8)target_ant, (p_dm_fat_table->train_idx)); + } + + /*set beam in each antenna*/ + phydm_update_rx_idle_beam(p_dm_odm); + + odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); + p_dm_fat_table->fat_state = FAT_PREPARE_STATE; + return; + + } + /* [TRAINING STATE] */ + else if (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2. In Training state]\n")); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n", + pdm_sat_table->fast_training_beam_num, pdm_sat_table->pre_fast_training_beam_num)); + + if (pdm_sat_table->fast_training_beam_num > pdm_sat_table->pre_fast_training_beam_num) + + pdm_sat_table->force_update_beam_en = 0; + + else { + + pdm_sat_table->force_update_beam_en = 1; + + pdm_sat_table->pkt_counter = 0; + beam_tmp = pdm_sat_table->fast_training_beam_num; + if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant - 1)) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", pdm_sat_table->fast_training_beam_num)); + p_dm_fat_table->fat_state = FAT_DECISION_STATE; + odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); + + } else { + pdm_sat_table->fast_training_beam_num++; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); + phydm_set_all_ant_same_beam_num(p_dm_odm); + p_dm_fat_table->fat_state = FAT_TRAINING_STATE; + + } + } + pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[prepare state] Update Pre_Beam =(( %d ))\n", pdm_sat_table->pre_fast_training_beam_num)); + } + /* [Prepare state] */ + /*=======================================================================================*/ + else if (p_dm_fat_table->fat_state == FAT_PREPARE_STATE) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n\n[ 1. In Prepare state]\n")); + + if (p_dm_odm->pre_traffic_load == (p_dm_odm->traffic_load)) { + if (pdm_sat_table->decision_holding_period != 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Holding_period = (( %d )), return!!!\n", pdm_sat_table->decision_holding_period)); + pdm_sat_table->decision_holding_period--; + return; + } + } + + + /* Set training packet number*/ + if (pdm_sat_table->fix_training_num_en == 0) { + + switch (p_dm_odm->traffic_load) { + + case TRAFFIC_HIGH: + pdm_sat_table->per_beam_training_pkt_num = 8; + pdm_sat_table->decision_holding_period = 2; + break; + case TRAFFIC_MID: + pdm_sat_table->per_beam_training_pkt_num = 6; + pdm_sat_table->decision_holding_period = 3; + break; + case TRAFFIC_LOW: + pdm_sat_table->per_beam_training_pkt_num = 3; /*ping 60000*/ + pdm_sat_table->decision_holding_period = 4; + break; + case TRAFFIC_ULTRA_LOW: + pdm_sat_table->per_beam_training_pkt_num = 1; + pdm_sat_table->decision_holding_period = 6; + break; + default: + break; + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\n", + pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); + + +#ifdef CONFIG_FAT_PATCH + break_counter = 0; + for (i = (pdm_sat_table->first_train_ant - 1); i < pdm_sat_table->ant_num_total; i++) { + for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { + + per_beam_rssi_diff_tmp = pdm_sat_table->beam_train_rssi_diff[i][j]; + training_pkt_num_offset = per_beam_rssi_diff_tmp; + + if ((pdm_sat_table->per_beam_training_pkt_num) > training_pkt_num_offset) + pdm_sat_table->beam_train_cnt[i][j] = pdm_sat_table->per_beam_training_pkt_num - training_pkt_num_offset; + else + pdm_sat_table->beam_train_cnt[i][j] = 1; + + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ant[%d]: Beam_num-(( %d )) training_pkt_num = ((%d))\n", + i, j, pdm_sat_table->beam_train_cnt[i][j])); + } + break_counter++; + if (break_counter >= (pdm_sat_table->ant_num)) + break; + } + + + phydm_fast_training_enable(p_dm_odm, FAT_OFF); + pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; + pdm_sat_table->update_beam_idx = 0; + + if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set 5G ant\n")); + /*used_ant = (pdm_sat_table->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/ + used_ant = pdm_sat_table->first_train_ant; + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set 2.4G ant\n")); + used_ant = pdm_sat_table->first_train_ant; + } + + odm_update_rx_idle_ant(p_dm_odm, (u8)used_ant); + +#else + /* Set training MAC addr. of target */ + odm_set_next_mac_addr_target(p_dm_odm); + phydm_fast_training_enable(p_dm_odm, FAT_ON); +#endif + + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + pdm_sat_table->pkt_counter = 0; + pdm_sat_table->fast_training_beam_num = 0; + phydm_set_all_ant_same_beam_num(p_dm_odm); + pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; + p_dm_fat_table->fat_state = FAT_TRAINING_STATE; + } + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void +phydm_beam_switch_workitem_callback( + void *p_context +) +{ + struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE + pdm_sat_table->pkt_skip_statistic_en = 1; +#endif + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en)); + + phydm_update_beam_pattern(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE + /*odm_stall_execution(pdm_sat_table->latch_time);*/ + pdm_sat_table->pkt_skip_statistic_en = 0; +#endif + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en, pdm_sat_table->latch_time)); +} + +void +phydm_beam_decision_workitem_callback( + void *p_context +) +{ + struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam decision Workitem Callback\n")); + odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); +} +#endif + +#endif /*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ + +void +odm_ant_div_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + + + if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] Not Support Antenna Diversity Function\n")); + return; + } + /* --- */ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_2G) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n")); + if (!(p_dm_odm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)) + return; + } else if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_5G) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n")); + if (!(p_dm_odm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)) + return; + } else if (p_dm_fat_table->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G)) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n")); + +#endif + /* --- */ + + /* 2 [--General---] */ + p_dm_odm->antdiv_period = 0; + + p_dm_fat_table->is_become_linked = false; + p_dm_fat_table->ant_div_on_off = 0xff; + + /* 3 - AP - */ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + odm_bdc_init(p_dm_odm); +#endif +#endif + + /* 3 - WIN - */ +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + p_dm_swat_table->ant_5g = MAIN_ANT; + p_dm_swat_table->ant_2g = MAIN_ANT; +#endif + + /* 2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */ + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + + p_dm_odm->ant_type = ODM_AUTO_ANT; + + p_dm_fat_table->rx_idle_ant = 0xff; /*to make RX-idle-antenna will be updated absolutly*/ + odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); + phydm_keep_rx_ack_ant_by_tx_ant_time(p_dm_odm, 0); /* Timming issue: keep Rx ant after tx for ACK ( 5 x 3.2 mu = 16mu sec)*/ + + /* 2 [---Set TX Antenna---] */ + if (p_dm_fat_table->p_force_tx_ant_by_desc == NULL) { + p_dm_fat_table->force_tx_ant_by_desc = 0; + p_dm_fat_table->p_force_tx_ant_by_desc = &(p_dm_fat_table->force_tx_ant_by_desc); + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_force_tx_ant_by_desc = %d\n", *p_dm_fat_table->p_force_tx_ant_by_desc)); + + if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == true) + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); + else + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + + + /* 2 [--88E---] */ + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + /* p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ + /* p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; */ + + if ((p_dm_odm->ant_div_type != CGCS_RX_HW_ANTDIV) && (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) && (p_dm_odm->ant_div_type != CG_TRX_SMART_ANTDIV)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 88E Not Supprrt This AntDiv type\n")); + p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + + if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_rx_hw_ant_div_init_88e(p_dm_odm); + else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_88e(p_dm_odm); +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + else if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_smart_hw_ant_div_init_88e(p_dm_odm); +#endif +#endif + } + + /* 2 [--92E---] */ +#if (RTL8192E_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + /* p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ + /* p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; */ + + if ((p_dm_odm->ant_div_type != CGCS_RX_HW_ANTDIV) && (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) && (p_dm_odm->ant_div_type != CG_TRX_SMART_ANTDIV)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8192E Not Supprrt This AntDiv type\n")); + p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + + if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_rx_hw_ant_div_init_92e(p_dm_odm); + else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_92e(p_dm_odm); +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + else if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_smart_hw_ant_div_init_92e(p_dm_odm); +#endif + + } +#endif + + /* 2 [--8723B---] */ +#if (RTL8723B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; + /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ + + if (p_dm_odm->ant_div_type != S0S1_SW_ANTDIV && p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8723B Not Supprrt This AntDiv type\n")); + p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + + if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) + odm_s0s1_sw_ant_div_init_8723b(p_dm_odm); + else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8723b(p_dm_odm); + } +#endif + /*2 [--8723D---]*/ +#if (RTL8723D_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (p_dm_fat_table->p_default_s0_s1 == NULL) { + p_dm_fat_table->default_s0_s1 = 1; + p_dm_fat_table->p_default_s0_s1 = &(p_dm_fat_table->default_s0_s1); + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("default_s0_s1 = %d\n", *p_dm_fat_table->p_default_s0_s1)); + + if (*(p_dm_fat_table->p_default_s0_s1) == true) + odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); + else + odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); + + if (p_dm_odm->ant_div_type == S0S1_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8723d(p_dm_odm); + else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8723D Not Supprrt This AntDiv type\n")); + p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); return; } - odm_TRX_HWAntDiv_Init_8821C(pDM_Odm); + } - #endif - - //2 [--8881A---] - #if (RTL8881A_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8881A) - { - //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - - if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { - - odm_TRX_HWAntDiv_Init_8881A(pDM_Odm); - /**/ - } else { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8881A Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); +#endif + /* 2 [--8811A 8821A---] */ +#if (RTL8821A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8821) { + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + p_dm_odm->ant_div_type = HL_SW_SMART_ANT_TYPE1; + + if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { + + odm_trx_hw_ant_div_init_8821a(p_dm_odm); + phydm_hl_smart_ant_type1_init_8821a(p_dm_odm); + } else + #endif + { + /*p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV;*/ + p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; + + if (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV && p_dm_odm->ant_div_type != S0S1_SW_ANTDIV) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821A & 8811A Not Supprrt This AntDiv type\n")); + p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); return; } + if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8821a(p_dm_odm); + else if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) + odm_s0s1_sw_ant_div_init_8821a(p_dm_odm); + } + } +#endif - odm_TRX_HWAntDiv_Init_8881A(pDM_Odm); + /* 2 [--8821C---] */ +#if (RTL8821C_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; + if (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821C Not Supprrt This AntDiv type\n")); + p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + odm_trx_hw_ant_div_init_8821c(p_dm_odm); } - #endif - - //2 [--8812---] - #if (RTL8812A_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8812) - { - //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - - if( pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8812A Not Supprrt This AntDiv Type\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - return; - } - odm_TRX_HWAntDiv_Init_8812A(pDM_Odm); +#endif + + /* 2 [--8881A---] */ +#if (RTL8881A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8881A) { + /* p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ + + if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) { + + odm_trx_hw_ant_div_init_8881a(p_dm_odm); + /**/ + } else { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8881A Not Supprrt This AntDiv type\n")); + p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + + odm_trx_hw_ant_div_init_8881a(p_dm_odm); } - #endif +#endif + + /* 2 [--8812---] */ +#if (RTL8812A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8812) { + /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ + + if (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8812A Not Supprrt This AntDiv type\n")); + p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + odm_trx_hw_ant_div_init_8812a(p_dm_odm); + } +#endif /*[--8188F---]*/ - #if (RTL8188F_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8188F) { - - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - odm_S0S1_SWAntDiv_Init_8188F(pDM_Odm); +#if (RTL8188F_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + + p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; + odm_s0s1_sw_ant_div_init_8188f(p_dm_odm); } - #endif +#endif + + /*[--8822B---]*/ +#if (RTL8822B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + p_dm_odm->ant_div_type = HL_SW_SMART_ANT_TYPE2; + + if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE2) + phydm_hl_smart_ant_type2_init_8822b(p_dm_odm); + #endif + } +#endif + /* - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** SupportICType=[%lu]\n",pDM_Odm->SupportICType)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv SupportAbility=[%lu]\n",(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)>>6)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv Type=[%d]\n",pDM_Odm->AntDivType)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** support_ic_type=[%lu]\n",p_dm_odm->support_ic_type)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv support_ability=[%lu]\n",(p_dm_odm->support_ability & ODM_BB_ANT_DIV)>>6)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv type=[%d]\n",p_dm_odm->ant_div_type)); */ } -VOID -ODM_AntDiv( - IN PVOID pDM_VOID - ) +void +odm_ant_div( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER pAdapter = pDM_Odm->Adapter; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - #endif + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); +#endif - if(*pDM_Odm->pBandType == ODM_BAND_5G ) - { - if(pDM_FatTable->idx_AntDiv_counter_5G < pDM_Odm->antdiv_period ) - { - pDM_FatTable->idx_AntDiv_counter_5G++; - return; +#ifdef ODM_EVM_ENHANCE_ANTDIV + + if (p_dm_odm->is_linked) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tp_active_occur=((%d)), EVM_method_enable=((%d))\n", + p_dm_odm->tp_active_occur, p_dm_fat_table->EVM_method_enable)); + + if ((p_dm_odm->tp_active_occur == 1) && (p_dm_fat_table->EVM_method_enable == 1)) { + + p_dm_fat_table->idx_ant_div_counter_5g = p_dm_odm->antdiv_period; + p_dm_fat_table->idx_ant_div_counter_2g = p_dm_odm->antdiv_period; } - else - pDM_FatTable->idx_AntDiv_counter_5G=0; } - else if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) - { - if(pDM_FatTable->idx_AntDiv_counter_2G < pDM_Odm->antdiv_period ) - { - pDM_FatTable->idx_AntDiv_counter_2G++; +#endif + + if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + if (p_dm_fat_table->idx_ant_div_counter_5g < p_dm_odm->antdiv_period) { + p_dm_fat_table->idx_ant_div_counter_5g++; return; - } - else - pDM_FatTable->idx_AntDiv_counter_2G=0; + } else + p_dm_fat_table->idx_ant_div_counter_5g = 0; + } else if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { + if (p_dm_fat_table->idx_ant_div_counter_2g < p_dm_odm->antdiv_period) { + p_dm_fat_table->idx_ant_div_counter_2g++; + return; + } else + p_dm_fat_table->idx_ant_div_counter_2g = 0; } - - //---------- - if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] Not Support Antenna Diversity Function\n")); + + /* ---------- */ + if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] Not Support Antenna Diversity Function\n")); return; } - //---------- + /* ---------- */ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (pDM_FatTable->enable_ctrl_frame_antdiv) { - - if ((pDM_Odm->data_frame_num <= 10) && (pDM_Odm->bLinked)) - pDM_FatTable->use_ctrl_frame_antdiv = 1; + if (p_dm_fat_table->enable_ctrl_frame_antdiv) { + + if ((p_dm_odm->data_frame_num <= 10) && (p_dm_odm->is_linked)) + p_dm_fat_table->use_ctrl_frame_antdiv = 1; else - pDM_FatTable->use_ctrl_frame_antdiv = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n", pDM_FatTable->use_ctrl_frame_antdiv, pDM_Odm->data_frame_num)); - pDM_Odm->data_frame_num = 0; + p_dm_fat_table->use_ctrl_frame_antdiv = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n", p_dm_fat_table->use_ctrl_frame_antdiv, p_dm_odm->data_frame_num)); + p_dm_odm->data_frame_num = 0; } - if(pAdapter->MgntInfo.AntennaTest) + if (p_adapter->MgntInfo.AntennaTest) return; - - { - #if (BEAMFORMING_SUPPORT == 1) - BEAMFORMING_CAP BeamformCap = (pDM_Odm->BeamformingInfo.BeamformCap); - - if( BeamformCap & BEAMFORMEE_CAP ) // BFmee On && Div On -> Div Off - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ AntDiv : OFF ] BFmee ==1 \n")); - if(pDM_FatTable->fix_ant_bfee == 0) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - pDM_FatTable->fix_ant_bfee = 1; + + { +#if (BEAMFORMING_SUPPORT == 1) + enum beamforming_cap beamform_cap = (p_dm_odm->beamforming_info.beamform_cap); + + if (beamform_cap & BEAMFORMEE_CAP) { /* BFmee On && Div On->Div Off */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ AntDiv : OFF ] BFmee ==1\n")); + if (p_dm_fat_table->fix_ant_bfee == 0) { + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + p_dm_fat_table->fix_ant_bfee = 1; } return; - } - else // BFmee Off && Div Off -> Div On - { - if((pDM_FatTable->fix_ant_bfee == 1) && pDM_Odm->bLinked) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ AntDiv : ON ] BFmee ==0\n")); - if((pDM_Odm->AntDivType!=S0S1_SW_ANTDIV) ) - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + } else { /* BFmee Off && Div Off->Div On */ + if ((p_dm_fat_table->fix_ant_bfee == 1) && p_dm_odm->is_linked) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ AntDiv : ON ] BFmee ==0\n")); + if ((p_dm_odm->ant_div_type != S0S1_SW_ANTDIV)) + odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - pDM_FatTable->fix_ant_bfee = 0; + p_dm_fat_table->fix_ant_bfee = 0; } } - #endif +#endif } #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - //----------just for fool proof + /* ----------just for fool proof */ - if(pDM_Odm->antdiv_rssi) - pDM_Odm->DebugComponents |= ODM_COMP_ANT_DIV; + if (p_dm_odm->antdiv_rssi) + p_dm_odm->debug_components |= ODM_COMP_ANT_DIV; else - pDM_Odm->DebugComponents &= ~ODM_COMP_ANT_DIV; + p_dm_odm->debug_components &= ~ODM_COMP_ANT_DIV; - if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G) - { - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G AntDiv Running ]\n")); - if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC)) + if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_2G) { + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G AntDiv Running ]\n")); */ + if (!(p_dm_odm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)) return; - } - else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G) - { - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 5G AntDiv Running ]\n")); - if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC)) + } else if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_5G) { + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 5G AntDiv Running ]\n")); */ + if (!(p_dm_odm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)) return; } - //else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) - //{ - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G & 5G AntDiv Running ]\n")); - //} + /* else if(p_dm_fat_table->ant_div_2g_5g == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) */ + /* { */ + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G & 5G AntDiv Running ]\n")); */ + /* } */ #endif - //---------- + /* ---------- */ - if (pDM_Odm->antdiv_select==1) - pDM_Odm->AntType = ODM_FIX_MAIN_ANT; - else if (pDM_Odm->antdiv_select==2) - pDM_Odm->AntType = ODM_FIX_AUX_ANT; - else //if (pDM_Odm->antdiv_select==0) - pDM_Odm->AntType = ODM_AUTO_ANT; + if (p_dm_odm->antdiv_select == 1) + p_dm_odm->ant_type = ODM_FIX_MAIN_ANT; + else if (p_dm_odm->antdiv_select == 2) + p_dm_odm->ant_type = ODM_FIX_AUX_ANT; + else /* if (p_dm_odm->antdiv_select==0) */ + p_dm_odm->ant_type = ODM_AUTO_ANT; - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("AntType= (( %d )) , pre_AntType= (( %d )) \n",pDM_Odm->AntType,pDM_Odm->pre_AntType)); - - if(pDM_Odm->AntType != ODM_AUTO_ANT) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix Antenna at (( %s ))\n",(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)?"MAIN":"AUX")); - - if(pDM_Odm->AntType != pDM_Odm->pre_AntType) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); - - if(pDM_Odm->AntType == ODM_FIX_MAIN_ANT) - ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); - else if(pDM_Odm->AntType == ODM_FIX_AUX_ANT) - ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("ant_type= (( %d )) , pre_ant_type= (( %d ))\n",p_dm_odm->ant_type,p_dm_odm->pre_ant_type)); */ + + if (p_dm_odm->ant_type != ODM_AUTO_ANT) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix Antenna at (( %s ))\n", (p_dm_odm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX")); + + if (p_dm_odm->ant_type != p_dm_odm->pre_ant_type) { + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + + if (p_dm_odm->ant_type == ODM_FIX_MAIN_ANT) + odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); + else if (p_dm_odm->ant_type == ODM_FIX_AUX_ANT) + odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); } - pDM_Odm->pre_AntType=pDM_Odm->AntType; + p_dm_odm->pre_ant_type = p_dm_odm->ant_type; return; - } - else - { - if(pDM_Odm->AntType != pDM_Odm->pre_AntType) - { - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); - odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + } else { + if (p_dm_odm->ant_type != p_dm_odm->pre_ant_type) { + odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); + odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); } - pDM_Odm->pre_AntType=pDM_Odm->AntType; + p_dm_odm->pre_ant_type = p_dm_odm->ant_type; } - - - //3 ----------------------------------------------------------------------------------------------------------- - //2 [--88E---] - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - #if (RTL8188E_SUPPORT == 1) - if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV ||pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV) - odm_HW_AntDiv(pDM_Odm); - #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV) - odm_FastAntTraining(pDM_Odm); - #endif - - #endif + + /* 3 ----------------------------------------------------------------------------------------------------------- */ + /* 2 [--88E---] */ + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV || p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_hw_ant_div(p_dm_odm); + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + else if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_fast_ant_training(p_dm_odm); +#endif + +#endif } - //2 [--92E---] - #if (RTL8192E_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV || pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV) - odm_HW_AntDiv(pDM_Odm); - - #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV) - odm_FastAntTraining(pDM_Odm); - #endif - + /* 2 [--92E---] */ +#if (RTL8192E_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV || p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(p_dm_odm); + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + else if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_fast_ant_training(p_dm_odm); +#endif + } - #endif +#endif - #if (RTL8723B_SUPPORT == 1) - //2 [--8723B---] - else if(pDM_Odm->SupportICType == ODM_RTL8723B) - { - if (phydm_IsBtEnable_8723b(pDM_Odm)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BT is enable!!!]\n")); - if (pDM_FatTable->bBecomeLinked == TRUE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); - if (pDM_Odm->SupportICType == ODM_RTL8723B) - ODM_SetBBReg(pDM_Odm, 0x948 , BIT9|BIT8|BIT7|BIT6, 0x0); - - pDM_FatTable->bBecomeLinked = FALSE; +#if (RTL8723B_SUPPORT == 1) + /* 2 [--8723B---] */ + else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (phydm_is_bt_enable_8723b(p_dm_odm)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BT is enable!!!]\n")); + if (p_dm_fat_table->is_become_linked == true) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); + if (p_dm_odm->support_ic_type == ODM_RTL8723B) + odm_set_bb_reg(p_dm_odm, 0x948, BIT(9) | BIT(8) | BIT(7) | BIT(6), 0x0); + + p_dm_fat_table->is_become_linked = false; } } else { - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { - - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEEK); - #endif - } else if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - odm_HW_AntDiv(pDM_Odm); + if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_PEEK); +#endif + } else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(p_dm_odm); } } - #endif - /*8723D*/ - #if (RTL8723D_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8723D) { - - odm_HW_AntDiv(pDM_Odm); +#endif + /*8723D*/ +#if (RTL8723D_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + + odm_hw_ant_div(p_dm_odm); /**/ } - #endif - - //2 [--8821A---] - #if (RTL8821A_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8821) - { +#endif + + /* 2 [--8821A---] */ +#if (RTL8821A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8821) { #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) { + if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { if (pdm_sat_table->fix_beam_pattern_en != 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", pdm_sat_table->fix_beam_pattern_codeword)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", pdm_sat_table->fix_beam_pattern_codeword)); /*return;*/ } else { - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] AntDivType = HL_SW_SMART_ANT_TYPE1\n"));*/ - odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] ant_div_type = HL_SW_SMART_ANT_TYPE1\n"));*/ + odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); } - } else + } else #endif { - if (!pDM_Odm->bBtEnabled) /*BT disabled*/ - { - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { - pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n")); - /*ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 1); */ - if (pDM_FatTable->bBecomeLinked == TRUE) - odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + if (!p_dm_odm->is_bt_enabled) { /*BT disabled*/ + if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { + p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n")); + /*odm_set_bb_reg(p_dm_odm, 0x8D4, BIT24, 1); */ + if (p_dm_fat_table->is_become_linked == true) + odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); } - + } else { /*BT enabled*/ + + if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) { + p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n")); + /*odm_set_bb_reg(p_dm_odm, 0x8D4, BIT24, 0);*/ + odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + } + } + + if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_PEEK); +#endif + } else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(p_dm_odm); + } + } +#endif + + /* 2 [--8821C---] */ +#if (RTL8821C_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8821C) + odm_hw_ant_div(p_dm_odm); +#endif + + /* 2 [--8881A---] */ +#if (RTL8881A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8881A) + odm_hw_ant_div(p_dm_odm); +#endif + + /* 2 [--8812A---] */ +#if (RTL8812A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8812) + odm_hw_ant_div(p_dm_odm); +#endif + +#if (RTL8188F_SUPPORT == 1) + /* [--8188F---]*/ + else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_PEEK); +#endif + } +#endif + + /* [--8822B---]*/ +#if (RTL8822B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE2) { + + if (pdm_sat_table->fix_beam_pattern_en != 0) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", pdm_sat_table->fix_beam_pattern_codeword)); + else + phydm_fast_ant_training_hl_smart_antenna_type2(p_dm_odm); + } + #endif + } +#endif + + +} + + +void +odm_antsel_statistics( + void *p_dm_void, + void *p_phy_info_void, + u8 antsel_tr_mux, + u32 mac_id, + u32 utility, + u8 method, + u8 is_cck_rate + +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; + + if (method == RSSI_METHOD) { + + if (is_cck_rate) { + if (antsel_tr_mux == ANT1_2G) { + if (p_dm_fat_table->main_ant_sum_cck[mac_id] > 65435) /*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/ + return; + + p_dm_fat_table->main_ant_sum_cck[mac_id] += (u16)utility; + p_dm_fat_table->main_ant_cnt_cck[mac_id]++; + } else { + if (p_dm_fat_table->aux_ant_sum_cck[mac_id] > 65435) + return; + + p_dm_fat_table->aux_ant_sum_cck[mac_id] += (u16)utility; + p_dm_fat_table->aux_ant_cnt_cck[mac_id]++; + } + + } else { /*ofdm rate*/ + + if (antsel_tr_mux == ANT1_2G) { + if (p_dm_fat_table->main_ant_sum[mac_id] > 65435) + return; + + p_dm_fat_table->main_ant_sum[mac_id] += (u16)utility; + p_dm_fat_table->main_ant_cnt[mac_id]++; + } else { + if (p_dm_fat_table->aux_ant_sum[mac_id] > 65435) + return; + + p_dm_fat_table->aux_ant_sum[mac_id] += (u16)utility; + p_dm_fat_table->aux_ant_cnt[mac_id]++; + } + } + } +#ifdef ODM_EVM_ENHANCE_ANTDIV + else if (method == EVM_METHOD) { + if (p_dm_odm->rate_ss == 1) { + + if (antsel_tr_mux == ANT1_2G) { + p_dm_fat_table->main_ant_evm_sum[mac_id] += ((p_phy_info->rx_mimo_evm_dbm[0])<<5); + p_dm_fat_table->main_ant_evm_cnt[mac_id]++; + } else { + p_dm_fat_table->aux_ant_evm_sum[mac_id] += ((p_phy_info->rx_mimo_evm_dbm[0])<<5); + p_dm_fat_table->aux_ant_evm_cnt[mac_id]++; + } + + } else {/*>= 2SS*/ + + if (antsel_tr_mux == ANT1_2G) { + + p_dm_fat_table->main_ant_evm_2ss_sum[mac_id][0] += (p_phy_info->rx_mimo_evm_dbm[0]<<5); + p_dm_fat_table->main_ant_evm_2ss_sum[mac_id][1] += (p_phy_info->rx_mimo_evm_dbm[1]<<5); + p_dm_fat_table->main_ant_evm_2ss_cnt[mac_id]++; + + } else { + + p_dm_fat_table->aux_ant_evm_2ss_sum[mac_id][0] += (p_phy_info->rx_mimo_evm_dbm[0]<<5); + p_dm_fat_table->aux_ant_evm_2ss_sum[mac_id][1] += (p_phy_info->rx_mimo_evm_dbm[1]<<5); + p_dm_fat_table->aux_ant_evm_2ss_cnt[mac_id]++; + } + } + + } else if (method == CRC32_METHOD) { + + if (antsel_tr_mux == ANT1_2G) { + p_dm_fat_table->main_crc32_ok_cnt += utility; + p_dm_fat_table->main_crc32_fail_cnt++; + } else { + p_dm_fat_table->aux_crc32_ok_cnt += utility; + p_dm_fat_table->aux_crc32_fail_cnt++; + } + + } else if (method == TP_METHOD) { + if (((utility <= ODM_RATEMCS15) && (utility >= ODM_RATEMCS0)) && + (p_dm_fat_table->fat_state_cnt <= p_dm_odm->antdiv_tp_period) + ) { + + if (antsel_tr_mux == ANT1_2G) { + p_dm_fat_table->antdiv_tp_main += (phy_rate_table[utility])<<5; + p_dm_fat_table->antdiv_tp_main_cnt++; + } else { + p_dm_fat_table->antdiv_tp_aux += (phy_rate_table[utility])<<5; + p_dm_fat_table->antdiv_tp_aux_cnt++; + } + } + } +#endif +} + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 +void +phydm_process_rssi_for_hb_smtant_type2( + void *p_dm_void, + void *p_phy_info_void, + void *p_pkt_info_void, + u8 rssi_avg +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; + struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + u8 train_pkt_number; + u32 beam_tmp; + u8 is_cck_rate; + u8 rx_power_ant0 = p_phy_info->rx_mimo_signal_strength[0]; + u8 rx_power_ant1 = p_phy_info->rx_mimo_signal_strength[1]; + u8 rx_evm_ant0 = p_phy_info->rx_mimo_evm_dbm[0]; + u8 rx_evm_ant1 = p_phy_info->rx_mimo_evm_dbm[1]; + u8 rate_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); + + is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? TRUE : FALSE; + + + /*[Beacon]*/ + if (p_pktinfo->is_packet_beacon) { + + pdm_sat_table->beacon_counter++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MatchBSSID_beacon_counter = ((%d))\n", pdm_sat_table->beacon_counter)); + + if (pdm_sat_table->beacon_counter >= pdm_sat_table->pre_beacon_counter + 2) { + + pdm_sat_table->update_beam_idx++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", + pdm_sat_table->pre_beacon_counter, pdm_sat_table->pkt_counter, pdm_sat_table->update_beam_idx)); - if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n")); - /*ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 0);*/ - odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); - } + pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; + pdm_sat_table->pkt_counter = 0; + } + } + /*[data]*/ + else if (p_pktinfo->is_packet_to_self) { + + if (pdm_sat_table->pkt_skip_statistic_en == 0) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ID[%d] pkt_cnt=((%d)): Beam_set = ((%d)), RSSI{A,B,avg} = {%d, %d, %d}\n", + p_pktinfo->station_id, pdm_sat_table->pkt_counter, pdm_sat_table->fast_training_beam_num, rx_power_ant0, rx_power_ant1, rssi_avg)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Rate_ss = ((%d)), EVM{A,B} = {%d, %d}, RX Rate =", rate_ss, rx_evm_ant0, rx_evm_ant1)); + phydm_print_rate(p_dm_odm, p_dm_odm->rx_rate, ODM_COMP_ANT_DIV); + + + if (pdm_sat_table->pkt_counter >= 1) /*packet skip count*/ + { + pdm_sat_table->beam_set_rssi_avg_sum[pdm_sat_table->fast_training_beam_num] += rssi_avg; + pdm_sat_table->statistic_pkt_cnt[pdm_sat_table->fast_training_beam_num]++; + + pdm_sat_table->beam_path_rssi_sum[pdm_sat_table->fast_training_beam_num][0] += rx_power_ant0; + pdm_sat_table->beam_path_rssi_sum[pdm_sat_table->fast_training_beam_num][1] += rx_power_ant1; + + if (rate_ss == 2) { + pdm_sat_table->beam_path_evm_2ss_sum[pdm_sat_table->fast_training_beam_num][0] += rx_evm_ant0; + pdm_sat_table->beam_path_evm_2ss_sum[pdm_sat_table->fast_training_beam_num][1] += rx_evm_ant1; + pdm_sat_table->beam_path_evm_2ss_cnt[pdm_sat_table->fast_training_beam_num]++; + } else { + pdm_sat_table->beam_path_evm_1ss_sum[pdm_sat_table->fast_training_beam_num] += rx_evm_ant0; + pdm_sat_table->beam_path_evm_1ss_cnt[pdm_sat_table->fast_training_beam_num]++; + } } + + pdm_sat_table->pkt_counter++; - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { + train_pkt_number = pdm_sat_table->beam_set_train_cnt[pdm_sat_table->fast_training_beam_num]; - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEEK); - #endif - } else if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - odm_HW_AntDiv(pDM_Odm); + if (pdm_sat_table->pkt_counter >= train_pkt_number) { + + pdm_sat_table->update_beam_idx++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), Update_new_beam = ((%d))\n", + pdm_sat_table->pre_beacon_counter, pdm_sat_table->update_beam_idx)); + + pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; + pdm_sat_table->pkt_counter = 0; + } } } - #endif - //2 [--8821C---] - #if (RTL8821C_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8821C) - { - odm_HW_AntDiv(pDM_Odm); - } - #endif - - //2 [--8881A---] - #if (RTL8881A_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8881A) - odm_HW_AntDiv(pDM_Odm); - #endif - - //2 [--8812A---] - #if (RTL8812A_SUPPORT == 1) - else if(pDM_Odm->SupportICType == ODM_RTL8812) - odm_HW_AntDiv(pDM_Odm); - #endif + if (pdm_sat_table->update_beam_idx > 0) { + + pdm_sat_table->update_beam_idx = 0; - #if (RTL8188F_SUPPORT == 1) - /* [--8188F---]*/ - else if (pDM_Odm->SupportICType == ODM_RTL8188F) { - - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEEK); - #endif - } - #endif + if (pdm_sat_table->fast_training_beam_num >= ((u32)pdm_sat_table->total_beam_set_num - 1)) { -} + p_dm_fat_table->fat_state = FAT_DECISION_STATE; + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_fast_ant_training_hl_smart_antenna_type2(p_dm_odm); /*go to make decision*/ + #else + odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_decision_workitem); + #endif -VOID -odm_AntselStatistics( - IN PVOID pDM_VOID, - IN u1Byte antsel_tr_mux, - IN u4Byte MacId, - IN u4Byte utility, - IN u1Byte method - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - if(method==RSSI_METHOD) - { - if(antsel_tr_mux == ANT1_2G) - { - pDM_FatTable->MainAnt_Sum[MacId]+=utility; - pDM_FatTable->MainAnt_Cnt[MacId]++; - } - else - { - pDM_FatTable->AuxAnt_Sum[MacId]+=utility; - pDM_FatTable->AuxAnt_Cnt[MacId]++; - } - } - #ifdef ODM_EVM_ENHANCE_ANTDIV - else if(method==EVM_METHOD) - { - if(antsel_tr_mux == ANT1_2G) - { - pDM_FatTable->MainAntEVM_Sum[MacId]+=(utility<<5); - pDM_FatTable->MainAntEVM_Cnt[MacId]++; - } - else - { - pDM_FatTable->AuxAntEVM_Sum[MacId]+=(utility<<5); - pDM_FatTable->AuxAntEVM_Cnt[MacId]++; + } else { + beam_tmp = pdm_sat_table->fast_training_beam_num; + pdm_sat_table->fast_training_beam_num++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); + phydm_set_rfu_beam_pattern_type2(p_dm_odm); + pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; + + p_dm_fat_table->fat_state = FAT_TRAINING_STATE; } } - else if(method==CRC32_METHOD) - { - if(utility==0) - pDM_FatTable->CRC32_Fail_Cnt++; - else - pDM_FatTable->CRC32_Ok_Cnt+=utility; - } - #endif + } +#endif - -VOID -ODM_Process_RSSIForAntDiv( - IN OUT PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN PVOID p_pkt_info_void - //IN PODM_PHY_INFO_T pPhyInfo, - //IN PODM_PACKET_INFO_T pPktinfo - ) +void +odm_process_rssi_for_ant_div( + void *p_dm_void, + void *p_phy_info_void, + void *p_pkt_info_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; - PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void; - u1Byte isCCKrate=0,CCKMaxRate=ODM_RATE11M; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); - u4Byte beam_tmp; - u1Byte next_ant; - u1Byte train_pkt_number; - #endif + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; + struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) + struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + u32 beam_tmp; + u8 next_ant; + u8 train_pkt_number; +#endif + u8 is_cck_rate = FALSE; + u8 rx_power_ant0 = p_phy_info->rx_mimo_signal_strength[0]; + u8 rx_power_ant1 = p_phy_info->rx_mimo_signal_strength[1]; + u8 rx_evm_ant0 = p_phy_info->rx_mimo_signal_quality[0]; + u8 rx_evm_ant1 = p_phy_info->rx_mimo_signal_quality[1]; + u8 rssi_avg; - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - u4Byte RxPower_Ant0, RxPower_Ant1; - u4Byte RxEVM_Ant0, RxEVM_Ant1; - #else - u1Byte RxPower_Ant0, RxPower_Ant1; - u1Byte RxEVM_Ant0, RxEVM_Ant1; - #endif + is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? TRUE : FALSE; - CCKMaxRate=ODM_RATE11M; - isCCKrate = (pPktinfo->DataRate <= CCKMaxRate)?TRUE:FALSE; - - if ((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8812)) && (pPktinfo->DataRate > CCKMaxRate)) - { - RxPower_Ant0 = pPhyInfo->RxMIMOSignalStrength[0]; - RxPower_Ant1= pPhyInfo->RxMIMOSignalStrength[1]; + if ((p_dm_odm->support_ic_type & ODM_IC_2SS) && (!is_cck_rate)) { - RxEVM_Ant0 =pPhyInfo->RxMIMOSignalQuality[0]; - RxEVM_Ant1 =pPhyInfo->RxMIMOSignalQuality[1]; + if (rx_power_ant1 < 100) + rssi_avg = (u8)odm_convert_to_db((odm_convert_to_linear(rx_power_ant0) + odm_convert_to_linear(rx_power_ant1))>>1); /*averaged PWDB*/ + + } else { + rx_power_ant0 = (u8)p_phy_info->rx_pwdb_all; + rssi_avg = rx_power_ant0; } - else - RxPower_Ant0=pPhyInfo->RxPWDBAll; + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + if ((p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) { + /*for 8822B*/ + phydm_process_rssi_for_hb_smtant_type2(p_dm_odm, p_phy_info, p_pktinfo, rssi_avg); + } else +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 +#ifdef CONFIG_FAT_PATCH + if ((p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) && (p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) { - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - #ifdef CONFIG_FAT_PATCH - if ((pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) && (pDM_FatTable->FAT_State == FAT_TRAINING_STATE)) { + /*[Beacon]*/ + if (p_pktinfo->is_packet_beacon) { - /*[Beacon]*/ - if (pPktinfo->bPacketBeacon) { - pdm_sat_table->beacon_counter++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MatchBSSID_beacon_counter = ((%d))\n", pdm_sat_table->beacon_counter)); - + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MatchBSSID_beacon_counter = ((%d))\n", pdm_sat_table->beacon_counter)); + if (pdm_sat_table->beacon_counter >= pdm_sat_table->pre_beacon_counter + 2) { if (pdm_sat_table->ant_num > 1) { - next_ant = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - ODM_UpdateRxIdleAnt(pDM_Odm, next_ant); + next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + odm_update_rx_idle_ant(p_dm_odm, next_ant); } pdm_sat_table->update_beam_idx++; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", pdm_sat_table->pre_beacon_counter, pdm_sat_table->pkt_counter, pdm_sat_table->update_beam_idx)); pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; pdm_sat_table->pkt_counter = 0; } - } - /*[Data]*/ - else if (pPktinfo->bPacketToSelf) { - + } + /*[data]*/ + else if (p_pktinfo->is_packet_to_self) { + if (pdm_sat_table->pkt_skip_statistic_en == 0) { /* - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", - pPktinfo->StationID, pDM_FatTable->antsel_rx_keep_0, pDM_FatTable->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + p_pktinfo->station_id, p_dm_fat_table->antsel_rx_keep_0, p_dm_fat_table->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, rx_power_ant0)); */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n", - pPktinfo->StationID, pdm_sat_table->pkt_counter, pDM_FatTable->antsel_rx_keep_0, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n", + p_pktinfo->station_id, pdm_sat_table->pkt_counter, p_dm_fat_table->antsel_rx_keep_0, pdm_sat_table->fast_training_beam_num, rx_power_ant0)); - pdm_sat_table->pkt_rssi_sum[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += RxPower_Ant0; - pdm_sat_table->pkt_rssi_cnt[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; + pdm_sat_table->pkt_rssi_sum[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += rx_power_ant0; + pdm_sat_table->pkt_rssi_cnt[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; pdm_sat_table->pkt_counter++; #if 1 - train_pkt_number = pdm_sat_table->beam_train_cnt[pDM_FatTable->RxIdleAnt-1][pdm_sat_table->fast_training_beam_num]; + train_pkt_number = pdm_sat_table->beam_train_cnt[p_dm_fat_table->rx_idle_ant - 1][pdm_sat_table->fast_training_beam_num]; #else train_pkt_number = pdm_sat_table->per_beam_training_pkt_num; #endif - + /*Swich Antenna erery N pkts*/ if (pdm_sat_table->pkt_counter == train_pkt_number) { if (pdm_sat_table->ant_num > 1) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number)); - next_ant = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - ODM_UpdateRxIdleAnt(pDM_Odm, next_ant); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number)); + next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + odm_update_rx_idle_ant(p_dm_odm, next_ant); } pdm_sat_table->update_beam_idx++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n", + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n", pdm_sat_table->pre_beacon_counter, pdm_sat_table->update_beam_idx)); pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; @@ -4825,543 +5833,514 @@ ODM_Process_RSSIForAntDiv( } } } - + /*Swich Beam after switch "pdm_sat_table->ant_num" antennas*/ if (pdm_sat_table->update_beam_idx == pdm_sat_table->ant_num) { - + pdm_sat_table->update_beam_idx = 0; pdm_sat_table->pkt_counter = 0; beam_tmp = pdm_sat_table->fast_training_beam_num; - - if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant-1)) { - - pDM_FatTable->FAT_State = FAT_DECISION_STATE; - + + if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant - 1)) { + + p_dm_fat_table->fat_state = FAT_DECISION_STATE; + #if DEV_BUS_TYPE == RT_PCI_INTERFACE - odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); + odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); #else - ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_decision_workitem); + odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_decision_workitem); #endif } else { pdm_sat_table->fast_training_beam_num++; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - phydm_set_all_ant_same_beam_num(pDM_Odm); - - pDM_FatTable->FAT_State = FAT_TRAINING_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); + phydm_set_all_ant_same_beam_num(p_dm_odm); + + p_dm_fat_table->fat_state = FAT_TRAINING_STATE; } } - - } - #else - if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) - { - if ((pDM_Odm->SupportICType & ODM_HL_SMART_ANT_TYPE1_SUPPORT) && - (pPktinfo->bPacketToSelf) && - (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) - ) { - + } +#else + + if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { + if ((p_dm_odm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) && + (p_pktinfo->is_packet_to_self) && + (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) + ) { + if (pdm_sat_table->pkt_skip_statistic_en == 0) { /* - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", - pPktinfo->StationID, pDM_FatTable->antsel_rx_keep_0, pDM_FatTable->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + p_pktinfo->station_id, p_dm_fat_table->antsel_rx_keep_0, p_dm_fat_table->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, rx_power_ant0)); */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), bPacketToSelf = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", - pPktinfo->StationID, pDM_FatTable->antsel_rx_keep_0, pPktinfo->bPacketToSelf, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + p_pktinfo->station_id, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->is_packet_to_self, pdm_sat_table->fast_training_beam_num, rx_power_ant0)); - - pdm_sat_table->pkt_rssi_sum[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += RxPower_Ant0; - pdm_sat_table->pkt_rssi_cnt[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; + + pdm_sat_table->pkt_rssi_sum[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += rx_power_ant0; + pdm_sat_table->pkt_rssi_cnt[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; pdm_sat_table->pkt_counter++; - + /*swich beam every N pkt*/ if ((pdm_sat_table->pkt_counter) >= (pdm_sat_table->per_beam_training_pkt_num)) { pdm_sat_table->pkt_counter = 0; beam_tmp = pdm_sat_table->fast_training_beam_num; - - if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant-1)) { - - pDM_FatTable->FAT_State = FAT_DECISION_STATE; - + + if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant - 1)) { + + p_dm_fat_table->fat_state = FAT_DECISION_STATE; + #if DEV_BUS_TYPE == RT_PCI_INTERFACE - odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); + odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); #else - ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_decision_workitem); + odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_decision_workitem); #endif } else { pdm_sat_table->fast_training_beam_num++; - phydm_set_all_ant_same_beam_num(pDM_Odm); - - pDM_FatTable->FAT_State = FAT_TRAINING_STATE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); + phydm_set_all_ant_same_beam_num(p_dm_odm); + + p_dm_fat_table->fat_state = FAT_TRAINING_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); } } } } } - #endif - else - #endif - if (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) { - if( (pDM_Odm->SupportICType & ODM_SMART_ANT_SUPPORT) && (pPktinfo->bPacketToSelf) && (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) )//(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon)) - { - u1Byte antsel_tr_mux; - antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0; - pDM_FatTable->antSumRSSI[antsel_tr_mux] += RxPower_Ant0; - pDM_FatTable->antRSSIcnt[antsel_tr_mux]++; - } - } - else //AntDivType != CG_TRX_SMART_ANTDIV - { - if ((pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) && (pPktinfo->bPacketToSelf || pDM_FatTable->use_ctrl_frame_antdiv)) - { - if(pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E) - { - odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID,RxPower_Ant0,RSSI_METHOD); - - #ifdef ODM_EVM_ENHANCE_ANTDIV - if(!isCCKrate) - { - odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID,RxEVM_Ant0,EVM_METHOD); - } - #endif +#endif + else +#endif + if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) { + if ((p_dm_odm->support_ic_type & ODM_SMART_ANT_SUPPORT) && (p_pktinfo->is_packet_to_self) && (p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) { /* (p_pktinfo->is_packet_match_bssid && (!p_pktinfo->is_packet_beacon)) */ + u8 antsel_tr_mux; + antsel_tr_mux = (p_dm_fat_table->antsel_rx_keep_2 << 2) | (p_dm_fat_table->antsel_rx_keep_1 << 1) | p_dm_fat_table->antsel_rx_keep_0; + p_dm_fat_table->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0; + p_dm_fat_table->ant_rssi_cnt[antsel_tr_mux]++; } - else// SupportICType == ODM_RTL8821 and ODM_RTL8723B and ODM_RTL8812) - { - if(isCCKrate && (pDM_Odm->AntDivType == S0S1_SW_ANTDIV)) - { - pDM_FatTable->antsel_rx_keep_0 = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ANT1_2G : ANT2_2G; + } else { /* ant_div_type != CG_TRX_SMART_ANTDIV */ + if ((p_dm_odm->support_ic_type & ODM_ANTDIV_SUPPORT) && (p_pktinfo->is_packet_to_self || p_dm_fat_table->use_ctrl_frame_antdiv)) { + if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { - if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G) - pDM_FatTable->CCK_counter_main++; - else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G) - pDM_FatTable->CCK_counter_aux++; + if (is_cck_rate || (p_dm_odm->support_ic_type == ODM_RTL8188F)) + p_dm_fat_table->antsel_rx_keep_0 = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; - odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0,RSSI_METHOD); - } - else - { - if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G) - pDM_FatTable->OFDM_counter_main++; - else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G) - pDM_FatTable->OFDM_counter_aux++; - odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0,RSSI_METHOD); + odm_antsel_statistics(p_dm_odm, p_phy_info, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_power_ant0, RSSI_METHOD, is_cck_rate); + + } else { + + odm_antsel_statistics(p_dm_odm, p_phy_info, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_power_ant0, RSSI_METHOD, is_cck_rate); + + #ifdef ODM_EVM_ENHANCE_ANTDIV + if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + if (!is_cck_rate) { + odm_antsel_statistics(p_dm_odm, p_phy_info, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_evm_ant0, EVM_METHOD, is_cck_rate); + odm_antsel_statistics(p_dm_odm, p_phy_info, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_evm_ant0, TP_METHOD, is_cck_rate); + } + + } + #endif } } } - } - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll)); - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0)); + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("is_cck_rate=%d, PWDB_ALL=%d\n",is_cck_rate, p_phy_info->rx_pwdb_all)); */ + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",p_dm_fat_table->antsel_rx_keep_2, p_dm_fat_table->antsel_rx_keep_1, p_dm_fat_table->antsel_rx_keep_0)); */ } -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -VOID -ODM_SetTxAntByTxInfo( - IN PVOID pDM_VOID, - IN pu1Byte pDesc, - IN u1Byte macId +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +void +odm_set_tx_ant_by_tx_info( + void *p_dm_void, + u8 *p_desc, + u8 mac_id - ) +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) return; - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) return; - if (pDM_Odm->SupportICType == ODM_RTL8723B) { + if (p_dm_odm->support_ic_type == ODM_RTL8723B) { #if (RTL8723B_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_8723B(pDesc, pDM_FatTable->antsel_a[macId]); - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723B] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", - macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/ + SET_TX_DESC_ANTSEL_A_8723B(p_desc, p_dm_fat_table->antsel_a[mac_id]); + /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/ #endif - } else if (pDM_Odm->SupportICType == ODM_RTL8821) { + } else if (p_dm_odm->support_ic_type == ODM_RTL8821) { #if (RTL8821A_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_8812(pDesc, pDM_FatTable->antsel_a[macId]); - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821A] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", - macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/ + SET_TX_DESC_ANTSEL_A_8812(p_desc, p_dm_fat_table->antsel_a[mac_id]); + /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/ #endif - } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { + } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { #if (RTL8188E_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]); - SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]); - SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]); - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8188E] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", - macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/ + SET_TX_DESC_ANTSEL_A_88E(p_desc, p_dm_fat_table->antsel_a[mac_id]); + SET_TX_DESC_ANTSEL_B_88E(p_desc, p_dm_fat_table->antsel_b[mac_id]); + SET_TX_DESC_ANTSEL_C_88E(p_desc, p_dm_fat_table->antsel_c[mac_id]); + /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/ +#endif + } else if (p_dm_odm->support_ic_type == ODM_RTL8821C) { +#if (RTL8821C_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_8821C(p_desc, p_dm_fat_table->antsel_a[mac_id]); + /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/ #endif } } -#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) -VOID -ODM_SetTxAntByTxInfo( +void +odm_set_tx_ant_by_tx_info( struct rtl8192cd_priv *priv, struct tx_desc *pdesc, - unsigned short aid + unsigned short aid ) { - PDM_ODM_T pDM_Odm = &(priv->pshare->_dmODM); - pFAT_T pDM_FatTable = &priv->pshare->_dmODM.DM_FatTable; - u4Byte SupportICType = priv->pshare->_dmODM.SupportICType; + struct PHY_DM_STRUCT *p_dm_odm = GET_PDM_ODM(priv);/*&(priv->pshare->_dmODM);*/ + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &(p_dm_odm->dm_fat_table); - if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) return; - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) return; - if (SupportICType == ODM_RTL8881A) { + if (p_dm_odm->support_ic_type == ODM_RTL8881A) { /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__); */ - pdesc->Dword6 &= set_desc(~(BIT(18)|BIT(17)|BIT(16))); - pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16); - } else if (SupportICType == ODM_RTL8192E) { + pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16))); + pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_a[aid] << 16); + } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */ - pdesc->Dword6 &= set_desc(~(BIT(18)|BIT(17)|BIT(16))); - pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16); - } else if (SupportICType == ODM_RTL8188E) { + pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16))); + pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_a[aid] << 16); + } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/ pdesc->Dword2 &= set_desc(~BIT(24)); pdesc->Dword2 &= set_desc(~BIT(25)); pdesc->Dword7 &= set_desc(~BIT(29)); - pdesc->Dword2 |= set_desc(pDM_FatTable->antsel_a[aid]<<24); - pdesc->Dword2 |= set_desc(pDM_FatTable->antsel_b[aid]<<25); - pdesc->Dword7 |= set_desc(pDM_FatTable->antsel_c[aid]<<29); - - - } else if (SupportICType == ODM_RTL8812) { + pdesc->Dword2 |= set_desc(p_dm_fat_table->antsel_a[aid] << 24); + pdesc->Dword2 |= set_desc(p_dm_fat_table->antsel_b[aid] << 25); + pdesc->Dword7 |= set_desc(p_dm_fat_table->antsel_c[aid] << 29); + + + } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { /*[path-A]*/ /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/ - + pdesc->Dword6 &= set_desc(~BIT(16)); pdesc->Dword6 &= set_desc(~BIT(17)); pdesc->Dword6 &= set_desc(~BIT(18)); - pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16); - pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_b[aid]<<17); - pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_c[aid]<<18); - + pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_a[aid] << 16); + pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_b[aid] << 17); + pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_c[aid] << 18); + } } #if 1 /*def CONFIG_WLAN_HAL*/ -VOID -ODM_SetTxAntByTxInfo_HAL( +void +odm_set_tx_ant_by_tx_info_hal( struct rtl8192cd_priv *priv, - PVOID pdesc_data, - u2Byte aid + void *pdesc_data, + u16 aid ) { - PDM_ODM_T pDM_Odm = &(priv->pshare->_dmODM); - pFAT_T pDM_FatTable = &priv->pshare->_dmODM.DM_FatTable; - u4Byte SupportICType = priv->pshare->_dmODM.SupportICType; + struct PHY_DM_STRUCT *p_dm_odm = GET_PDM_ODM(priv);/*&(priv->pshare->_dmODM);*/ + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &(p_dm_odm->dm_fat_table); PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data; - if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) return; - if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) return; - - if (SupportICType == ODM_RTL8881A || SupportICType == ODM_RTL8192E || SupportICType == ODM_RTL8814A) { - /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_HAL******\n",__FUNCTION__,__LINE__);*/ - pdescdata->antSel = 1; - pdescdata->antSel_A = pDM_FatTable->antsel_a[aid]; + + if (p_dm_odm->support_ic_type & (ODM_RTL8881A |ODM_RTL8192E |ODM_RTL8814A)) { + /*panic_printk("[%s] [%d] ******odm_set_tx_ant_by_tx_info_hal******\n",__FUNCTION__,__LINE__);*/ + pdescdata->ant_sel = 1; + pdescdata->ant_sel_a = p_dm_fat_table->antsel_a[aid]; } } -#endif /*#ifdef CONFIG_WLAN_HAL*/ +#endif /*#ifdef CONFIG_WLAN_HAL*/ #endif -VOID -ODM_AntDiv_Config( - IN PVOID pDM_VOID - ) +void +odm_ant_div_config( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - ODM_RT_TRACE (pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("WIN Config Antenna Diversity\n")); - /* - if(pDM_Odm->SupportICType==ODM_RTL8723B) - { - if((!pDM_Odm->DM_SWAT_Table.ANTA_ON || !pDM_Odm->DM_SWAT_Table.ANTB_ON)) - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - } - */ - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - - pDM_Odm->AntDivType = S0S1_TRX_HW_ANTDIV; - /**/ - } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("WIN Config Antenna Diversity\n")); + /* + if(p_dm_odm->support_ic_type==ODM_RTL8723B) + { + if((!p_dm_odm->dm_swat_table.ANTA_ON || !p_dm_odm->dm_swat_table.ANTB_ON)) + p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + } + */ + if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + + p_dm_odm->ant_div_type = S0S1_TRX_HW_ANTDIV; + /**/ + } #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CE Config Antenna Diversity\n")); - - if(pDM_Odm->SupportICType==ODM_RTL8723B) - { - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - - - } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CE Config Antenna Diversity\n")); + + if (p_dm_odm->support_ic_type == ODM_RTL8723B) + p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; + + #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AP Config Antenna Diversity\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AP Config Antenna Diversity\n")); + + /* 2 [ NOT_SUPPORT_ANTDIV ] */ +#if (defined(CONFIG_NOT_SUPPORT_ANTDIV)) + p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n")); + + /* 2 [ 2G&5G_SUPPORT_ANTDIV ] */ +#elif (defined(CONFIG_2G5G_SUPPORT_ANTDIV)) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n")); + p_dm_fat_table->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G); + + if (p_dm_odm->support_ic_type & ODM_ANTDIV_SUPPORT) + p_dm_odm->support_ability |= ODM_BB_ANT_DIV; + if (*p_dm_odm->p_band_type == ODM_BAND_5G) { +#if (defined(CONFIG_5G_CGCS_RX_DIVERSITY)) + p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n")); + panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); +#elif (defined(CONFIG_5G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) + p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n")); + panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); +#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) + p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CG_SMART_ANTDIV\n")); +#elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY)) + p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n")); +#endif + } else if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { +#if (defined(CONFIG_2G_CGCS_RX_DIVERSITY)) + p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n")); +#elif (defined(CONFIG_2G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) + p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n")); +#elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n")); +#elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY)) + p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n")); +#endif + } - //2 [ NOT_SUPPORT_ANTDIV ] - #if(defined(CONFIG_NOT_SUPPORT_ANTDIV)) - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n")); - - //2 [ 2G&5G_SUPPORT_ANTDIV ] - #elif(defined(CONFIG_2G5G_SUPPORT_ANTDIV)) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously \n")); - pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_2G|ODM_ANTDIV_5G); - - if(pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) - pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; - if(*pDM_Odm->pBandType == ODM_BAND_5G ) - { - #if ( defined(CONFIG_5G_CGCS_RX_DIVERSITY) ) - pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); - panic_printk("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"); - #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY)||defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) - pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); - panic_printk("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"); - #elif( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_SMART_ANTDIV\n")); - #elif( defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = S0S1_SW_ANTDIV\n")); - #endif - } - else if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) - { - #if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) ) - pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); - #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) - pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); - #elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_SMART_ANTDIV\n")); - #elif( defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = S0S1_SW_ANTDIV\n")); - #endif - } - - //2 [ 5G_SUPPORT_ANTDIV ] - #elif(defined(CONFIG_5G_SUPPORT_ANTDIV)) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n")); - panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"); - pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_5G); - if(*pDM_Odm->pBandType == ODM_BAND_5G ) - { - if(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC) - pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; - #if ( defined(CONFIG_5G_CGCS_RX_DIVERSITY) ) - pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); - panic_printk("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"); - #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY) ) - pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - panic_printk("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); - #elif( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_SMART_ANTDIV\n")); - #elif( defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = S0S1_SW_ANTDIV\n")); - #endif - } - else if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 2G AntDivType\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - } - - //2 [ 2G_SUPPORT_ANTDIV ] - #elif(defined(CONFIG_2G_SUPPORT_ANTDIV)) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n")); - pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_2G); - if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) - { - if(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC) - pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; - #if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) ) - pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); - #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) ) - pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); - #elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_SMART_ANTDIV\n")); - #elif( defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY) ) - pDM_Odm->AntDivType = S0S1_SW_ANTDIV; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = S0S1_SW_ANTDIV\n")); - #endif - } - else if(*pDM_Odm->pBandType == ODM_BAND_5G ) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 5G AntDivType\n")); - pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); - } - #endif -#endif + /* 2 [ 5G_SUPPORT_ANTDIV ] */ +#elif (defined(CONFIG_5G_SUPPORT_ANTDIV)) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n")); + panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"); + p_dm_fat_table->ant_div_2g_5g = (ODM_ANTDIV_5G); + if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + if (p_dm_odm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC) + p_dm_odm->support_ability |= ODM_BB_ANT_DIV; +#if (defined(CONFIG_5G_CGCS_RX_DIVERSITY)) + p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n")); + panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); +#elif (defined(CONFIG_5G_CG_TRX_DIVERSITY)) + p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; + panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n")); +#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) + p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CG_SMART_ANTDIV\n")); +#elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY)) + p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n")); +#endif + } else if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Not Support 2G ant_div_type\n")); + p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + } + + /* 2 [ 2G_SUPPORT_ANTDIV ] */ +#elif (defined(CONFIG_2G_SUPPORT_ANTDIV)) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n")); + p_dm_fat_table->ant_div_2g_5g = (ODM_ANTDIV_2G); + if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { + if (p_dm_odm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC) + p_dm_odm->support_ability |= ODM_BB_ANT_DIV; +#if (defined(CONFIG_2G_CGCS_RX_DIVERSITY)) + p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n")); +#elif (defined(CONFIG_2G_CG_TRX_DIVERSITY)) + p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n")); +#elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n")); +#elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY)) + p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n")); +#endif + } else if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Not Support 5G ant_div_type\n")); + p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + } +#endif +#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n", ((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) ? 1 : 0))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv Config Info] be_fix_tx_ant = ((%d))\n", pDM_Odm->DM_FatTable.b_fix_tx_ant)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n", ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv Config Info] be_fix_tx_ant = ((%d))\n", p_dm_odm->dm_fat_table.b_fix_tx_ant)); } -VOID -ODM_AntDivTimers( - IN PVOID pDM_VOID, - IN u1Byte state - ) +void +odm_ant_div_timers( + void *p_dm_void, + u8 state +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if(state==INIT_ANTDIV_TIMMER) - { - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - ODM_InitializeTimer(pDM_Odm, &(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchTimer), - (RT_TIMER_CALL_BACK)ODM_SW_AntDiv_Callback, NULL, "phydm_SwAntennaSwitchTimer"); - #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - ODM_InitializeTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, - (RT_TIMER_CALL_BACK)odm_FastAntTrainingCallback, NULL, "FastAntTrainingTimer"); - #endif + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + if (state == INIT_ANTDIV_TIMMER) { +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_initialize_timer(p_dm_odm, &(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_timer), + (void *)odm_sw_antdiv_callback, NULL, "phydm_sw_antenna_switch_timer"); +#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + odm_initialize_timer(p_dm_odm, &p_dm_odm->fast_ant_training_timer, + (void *)odm_fast_ant_training_callback, NULL, "fast_ant_training_timer"); +#endif - #ifdef ODM_EVM_ENHANCE_ANTDIV - ODM_InitializeTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, - (RT_TIMER_CALL_BACK)odm_EVM_FastAntTrainingCallback, NULL, "EVM_FastAntTrainingTimer"); - #endif - } - else if(state==CANCEL_ANTDIV_TIMMER) - { - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - ODM_CancelTimer(pDM_Odm, &(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchTimer)); - #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - ODM_CancelTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); - #endif +#ifdef ODM_EVM_ENHANCE_ANTDIV + odm_initialize_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer, + (void *)odm_evm_fast_ant_training_callback, NULL, "evm_fast_ant_training_timer"); +#endif + } else if (state == CANCEL_ANTDIV_TIMMER) { +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_cancel_timer(p_dm_odm, &(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_timer)); +#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + odm_cancel_timer(p_dm_odm, &p_dm_odm->fast_ant_training_timer); +#endif - #ifdef ODM_EVM_ENHANCE_ANTDIV - ODM_CancelTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer); - #endif - } - else if(state==RELEASE_ANTDIV_TIMMER) - { - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - ODM_ReleaseTimer(pDM_Odm, &(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchTimer)); - #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) - ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); - #endif +#ifdef ODM_EVM_ENHANCE_ANTDIV + odm_cancel_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer); +#endif + } else if (state == RELEASE_ANTDIV_TIMMER) { +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_release_timer(p_dm_odm, &(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_timer)); +#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + odm_release_timer(p_dm_odm, &p_dm_odm->fast_ant_training_timer); +#endif - #ifdef ODM_EVM_ENHANCE_ANTDIV - ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer); - #endif +#ifdef ODM_EVM_ENHANCE_ANTDIV + odm_release_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer); +#endif } } -VOID +void phydm_antdiv_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - /*pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;*/ - u4Byte used = *_used; - u4Byte out_len = *_out_len; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + /*struct _FAST_ANTENNA_TRAINNING_* p_dm_fat_table = &p_dm_odm->dm_fat_table;*/ + u32 used = *_used; + u32 out_len = *_out_len; if (dm_value[0] == 1) { /*fixed or auto antenna*/ - + if (dm_value[1] == 0) { - pDM_Odm->antdiv_select = 0; - PHYDM_SNPRINTF((output+used, out_len-used, "AntDiv: Auto\n")); + p_dm_odm->antdiv_select = 0; + PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv: Auto\n")); } else if (dm_value[1] == 1) { - pDM_Odm->antdiv_select = 1; - PHYDM_SNPRINTF((output+used, out_len-used, "AntDiv: Fix MAin\n")); + p_dm_odm->antdiv_select = 1; + PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv: Fix MAin\n")); } else if (dm_value[1] == 2) { - pDM_Odm->antdiv_select = 2; - PHYDM_SNPRINTF((output+used, out_len-used, "AntDiv: Fix Aux\n")); + p_dm_odm->antdiv_select = 2; + PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv: Fix Aux\n")); } } else if (dm_value[0] == 2) { /*dynamic period for AntDiv*/ - - pDM_Odm->antdiv_period = (u1Byte)dm_value[1]; - PHYDM_SNPRINTF((output+used, out_len-used, "AntDiv_period = ((%d))\n", pDM_Odm->antdiv_period)); - } + + p_dm_odm->antdiv_period = (u8)dm_value[1]; + PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv_period = ((%d))\n", p_dm_odm->antdiv_period)); + } } #endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/ -VOID -ODM_AntDivReset( - IN PVOID pDM_VOID - ) +void +odm_ant_div_reset( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) - { - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_S0S1_SWAntDiv_Reset(pDM_Odm); - #endif + if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div_reset(p_dm_odm); +#endif } } -VOID -odm_AntennaDiversityInit( - IN PVOID pDM_VOID - ) +void +odm_antenna_diversity_init( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if(pDM_Odm->mp_mode == TRUE) +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + +#if 0 + if (*(p_dm_odm->p_mp_mode) == true) return; - - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_AntDiv_Config(pDM_Odm); - ODM_AntDivInit(pDM_Odm); - #endif +#endif + + odm_ant_div_config(p_dm_odm); + odm_ant_div_init(p_dm_odm); +#endif } -VOID -odm_AntennaDiversity( - IN PVOID pDM_VOID - ) +void +odm_antenna_diversity( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if(pDM_Odm->mp_mode == TRUE) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + if (*(p_dm_odm->p_mp_mode) == true) return; - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_AntDiv(pDM_Odm); - #endif +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + odm_ant_div(p_dm_odm); +#endif } - - diff --git a/hal/phydm/phydm_antdiv.h b/hal/phydm/phydm_antdiv.h index 356c730..175b59d 100644 --- a/hal/phydm/phydm_antdiv.h +++ b/hal/phydm/phydm_antdiv.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PHYDMANTDIV_H__ #define __PHYDMANTDIV_H__ @@ -26,7 +21,7 @@ /*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/ /*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/ /*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/ -/*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT, +/*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT, because antenna diversity only works when BT is disable or radio off*/ /*#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/ /*#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/ @@ -35,44 +30,46 @@ /*#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */ #define ANTDIV_VERSION "3.9" /*2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */ -//1 ============================================================ -//1 Definition -//1 ============================================================ +/* 1 ============================================================ + * 1 Definition + * 1 ============================================================ */ #define ANTDIV_INIT 0xff -#define MAIN_ANT 1 /*Ant A or Ant Main or S1*/ -#define AUX_ANT 2 /*AntB or Ant Aux or S0*/ +#define MAIN_ANT 1 /*ant A or ant Main or S1*/ +#define AUX_ANT 2 /*AntB or ant Aux or S0*/ #define MAX_ANT 3 /* 3 for AP using*/ -#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */ -#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */ +#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */ +#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */ /*smart antenna*/ #define SUPPORT_RF_PATH_NUM 4 #define SUPPORT_BEAM_PATTERN_NUM 4 #define NUM_ANTENNA_8821A 2 +#define SUPPORT_BEAM_SET_PATTERN_NUM 16 + #define NO_FIX_TX_ANT 0 #define FIX_TX_AT_MAIN 1 #define FIX_AUX_AT_MAIN 2 -//Antenna Diversty Control Type +/* Antenna Diversty Control type */ #define ODM_AUTO_ANT 0 #define ODM_FIX_MAIN_ANT 1 #define ODM_FIX_AUX_ANT 2 -#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8188F|ODM_RTL8723D) -#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821C) -#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT|ODM_AC_ANTDIV_SUPPORT) -#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E) -#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821) +#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A) +#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B) +#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT) +#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E) +#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B) -#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A|ODM_RTL8188F|ODM_RTL8723D) -#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821C) +#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D) +#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C) #define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E) -#define ODM_ANTDIV_2G BIT0 -#define ODM_ANTDIV_5G BIT1 +#define ODM_ANTDIV_2G BIT(0) +#define ODM_ANTDIV_5G BIT(1) #define ANTDIV_ON 1 #define ANTDIV_OFF 0 @@ -83,9 +80,10 @@ #define TX_BY_DESC 1 #define TX_BY_REG 0 -#define RSSI_METHOD 0 +#define RSSI_METHOD 0 #define EVM_METHOD 1 #define CRC32_METHOD 2 +#define TP_METHOD 3 #define INIT_ANTDIV_TIMMER 0 #define CANCEL_ANTDIV_TIMMER 1 @@ -94,8 +92,8 @@ #define CRC32_FAIL 1 #define CRC32_OK 0 -#define Evm_RSSI_TH_High 25 -#define Evm_RSSI_TH_Low 20 +#define evm_rssi_th_high 25 +#define evm_rssi_th_low 20 #define NORMAL_STATE_MIAN 1 #define NORMAL_STATE_AUX 2 @@ -110,7 +108,7 @@ #define DIVOFF_CSION 2 #define BDC_DIV_TRAIN_STATE 0 -#define BDC_BFer_TRAIN_STATE 1 +#define bdc_bfer_train_state 1 #define BDC_DECISION_STATE 2 #define BDC_BF_HOLD_STATE 3 #define BDC_DIV_HOLD_STATE 4 @@ -132,210 +130,263 @@ /*Hong Lin Smart antenna*/ #define HL_SMTANT_2WIRE_DATA_LEN 24 -//1 ============================================================ -//1 structure -//1 ============================================================ - +/* 1 ============================================================ + * 1 structure + * 1 ============================================================ */ + + +struct _sw_antenna_switch_ { + u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/ + u8 try_flag; + s32 pre_rssi; + u8 cur_antenna; + u8 pre_antenna; + u8 rssi_trying; + u8 reset_idx; + u8 train_time; + u8 train_time_flag; /*base on RSSI difference between two antennas*/ + struct timer_list phydm_sw_antenna_switch_timer; + u32 pkt_cnt_sw_ant_div_by_ctrl_frame; + boolean is_sw_ant_div_by_ctrl_frame; -typedef struct _SW_Antenna_Switch_ -{ - u1Byte Double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/ - u1Byte try_flag; - s4Byte PreRSSI; - u1Byte CurAntenna; - u1Byte PreAntenna; - u1Byte RSSI_Trying; - u1Byte reset_idx; - u1Byte Train_time; - u1Byte Train_time_flag; /*base on RSSI difference between two antennas*/ - RT_TIMER phydm_SwAntennaSwitchTimer; - u4Byte PktCnt_SWAntDivByCtrlFrame; - BOOLEAN bSWAntDivByCtrlFrame; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if USE_WORKITEM - RT_WORK_ITEM phydm_SwAntennaSwitchWorkitem; - #endif - #endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if USE_WORKITEM + RT_WORK_ITEM phydm_sw_antenna_switch_workitem; +#endif +#endif /* AntDect (Before link Antenna Switch check) need to be moved*/ - u2Byte Single_Ant_Counter; - u2Byte Dual_Ant_Counter; - u2Byte Aux_FailDetec_Counter; - u2Byte Retry_Counter; - u1Byte SWAS_NoLink_State; - u4Byte SWAS_NoLink_BK_Reg948; - BOOLEAN ANTA_ON; /*To indicate Ant A is or not*/ - BOOLEAN ANTB_ON; /*To indicate Ant B is on or not*/ - BOOLEAN Pre_Aux_FailDetec; - BOOLEAN RSSI_AntDect_bResult; - u1Byte Ant5G; - u1Byte Ant2G; + u16 single_ant_counter; + u16 dual_ant_counter; + u16 aux_fail_detec_counter; + u16 retry_counter; + u8 swas_no_link_state; + u32 swas_no_link_bk_reg948; + boolean ANTA_ON; /*To indicate ant A is or not*/ + boolean ANTB_ON; /*To indicate ant B is on or not*/ + boolean pre_aux_fail_detec; + boolean rssi_ant_dect_result; + u8 ant_5g; + u8 ant_2g; - -}SWAT_T, *pSWAT_T; + +}; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) -typedef struct _BF_DIV_COEX_ -{ - BOOLEAN w_BFer_Client[ODM_ASSOCIATE_ENTRY_NUM]; - BOOLEAN w_BFee_Client[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; - - u1Byte BDCcoexType_wBfer; - u1Byte num_Txbfee_Client; - u1Byte num_Txbfer_Client; - u1Byte BDC_Try_counter; - u1Byte BDC_Hold_counter; - u1Byte BDC_Mode; - u1Byte BDC_active_Mode; - u1Byte BDC_state; - u1Byte BDC_RxIdleUpdate_counter; - u1Byte num_Client; - u1Byte pre_num_Client; - u1Byte num_BfTar; - u1Byte num_DivTar; - - BOOLEAN bAll_DivSta_Idle; - BOOLEAN bAll_BFSta_Idle; - BOOLEAN BDC_Try_flag; - BOOLEAN BF_pass; - BOOLEAN DIV_pass; -}BDC_T,*pBDC_T; +struct _BF_DIV_COEX_ { + boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM]; + boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM]; + u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; + u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; + + u8 bd_ccoex_type_wbfer; + u8 num_txbfee_client; + u8 num_txbfer_client; + u8 bdc_try_counter; + u8 bdc_hold_counter; + u8 bdc_mode; + u8 bdc_active_mode; + u8 BDC_state; + u8 bdc_rx_idle_update_counter; + u8 num_client; + u8 pre_num_client; + u8 num_bf_tar; + u8 num_div_tar; + + boolean is_all_div_sta_idle; + boolean is_all_bf_sta_idle; + boolean bdc_try_flag; + boolean BF_pass; + boolean DIV_pass; +}; #endif #endif -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 -typedef struct _SMART_ANTENNA_TRAINNING_ { - u4Byte latch_time; - BOOLEAN pkt_skip_statistic_en; - u4Byte fix_beam_pattern_en; - u4Byte fix_training_num_en; - u4Byte fix_beam_pattern_codeword; - u4Byte update_beam_codeword; - u4Byte ant_num; /*number of used smart beam antenna*/ - u4Byte ant_num_total;/*number of total smart beam antenna*/ - u4Byte first_train_ant; /*decide witch antenna to train first*/ - u4Byte rfu_codeword_table[4]; /*2G beam truth table*/ - u4Byte rfu_codeword_table_5g[4]; /*5G beam truth table*/ - u4Byte beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/ - u4Byte data_codeword_bit_num; - u1Byte per_beam_training_pkt_num; - u1Byte decision_holding_period; - u1Byte pkt_counter; - u4Byte fast_training_beam_num; - u4Byte pre_fast_training_beam_num; - u4Byte pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; - u1Byte beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; - u1Byte beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; - u4Byte pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM]; - u4Byte pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM]; - u4Byte rx_idle_beam[SUPPORT_RF_PATH_NUM]; - u4Byte pre_codeword; - BOOLEAN force_update_beam_en; - u4Byte beacon_counter; - u4Byte pre_beacon_counter; - u1Byte update_beam_idx; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) +struct _SMART_ANTENNA_TRAINNING_ { + u32 latch_time; + boolean pkt_skip_statistic_en; + u32 fix_beam_pattern_en; + u32 fix_training_num_en; + u32 fix_beam_pattern_codeword; + u32 update_beam_codeword; + u32 ant_num; /*number of "used" smart beam antenna*/ + u32 ant_num_total;/*number of "total" smart beam antenna*/ + u32 first_train_ant; /*decide witch antenna to train first*/ + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + u32 pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];/*rssi of each path with a certain beam pattern*/ + u8 beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u8 beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u32 rfu_codeword_table[4]; /*2G beam truth table*/ + u32 rfu_codeword_table_5g[4]; /*5G beam truth table*/ + u32 beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/ + u32 rx_idle_beam[SUPPORT_RF_PATH_NUM]; + u32 pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM]; + u32 pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM]; + #endif + + u32 fast_training_beam_num;/*current training beam_set index*/ + u32 pre_fast_training_beam_num;/*pre training beam_set index*/ + u32 rfu_codeword_total_bit_num; /* total bit number of RFU protocol*/ + u32 rfu_each_ant_bit_num; /* bit number of RFU protocol for each ant*/ + u8 per_beam_training_pkt_num; + u8 decision_holding_period; + + + u32 pre_codeword; + boolean force_update_beam_en; + u32 beacon_counter; + u32 pre_beacon_counter; + u8 pkt_counter; /*packet number that each beam-set should be colected in training state*/ + u8 update_beam_idx; /*the index announce that the beam can be updated*/ + u8 rfu_protocol_type; + u16 rfu_protocol_delay_time; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) RT_WORK_ITEM hl_smart_antenna_workitem; - RT_WORK_ITEM hl_smart_antenna_decision_workitem; + RT_WORK_ITEM hl_smart_antenna_decision_workitem; #endif -} SAT_T, *pSAT_T; -#endif -typedef struct _FAST_ANTENNA_TRAINNING_ -{ - u1Byte Bssid[6]; - u1Byte antsel_rx_keep_0; - u1Byte antsel_rx_keep_1; - u1Byte antsel_rx_keep_2; - u1Byte antsel_rx_keep_3; - u4Byte antSumRSSI[7]; - u4Byte antRSSIcnt[7]; - u4Byte antAveRSSI[7]; - u1Byte FAT_State; - u4Byte TrainIdx; - u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; - u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; - u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - u1Byte RxIdleAnt; - u1Byte AntDiv_OnOff; - BOOLEAN bBecomeLinked; - u4Byte MinMaxRSSI; - u1Byte idx_AntDiv_counter_2G; - u1Byte idx_AntDiv_counter_5G; - u1Byte AntDiv_2G_5G; - u4Byte CCK_counter_main; - u4Byte CCK_counter_aux; - u4Byte OFDM_counter_main; - u4Byte OFDM_counter_aux; - - #ifdef ODM_EVM_ENHANCE_ANTDIV - u4Byte MainAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte AuxAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte MainAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte AuxAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - BOOLEAN EVM_method_enable; - u1Byte TargetAnt_EVM; - u1Byte TargetAnt_CRC32; - u1Byte TargetAnt_enhance; - u1Byte pre_TargetAnt_enhance; - u2Byte Main_MPDU_OK_cnt; - u2Byte Aux_MPDU_OK_cnt; - - u4Byte CRC32_Ok_Cnt; - u4Byte CRC32_Fail_Cnt; - u4Byte MainCRC32_Ok_Cnt; - u4Byte AuxCRC32_Ok_Cnt; - u4Byte MainCRC32_Fail_Cnt; - u4Byte AuxCRC32_Fail_Cnt; - #endif - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - u4Byte CCK_CtrlFrame_Cnt_main; - u4Byte CCK_CtrlFrame_Cnt_aux; - u4Byte OFDM_CtrlFrame_Cnt_main; - u4Byte OFDM_CtrlFrame_Cnt_aux; - u4Byte MainAnt_CtrlFrame_Sum; - u4Byte AuxAnt_CtrlFrame_Sum; - u4Byte MainAnt_CtrlFrame_Cnt; - u4Byte AuxAnt_CtrlFrame_Cnt; + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + u8 beam_set_avg_rssi_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; /*avg pre_rssi of each beam set*/ + u8 beam_set_train_val_diff[SUPPORT_BEAM_SET_PATTERN_NUM]; /*rssi of a beam pattern set, ex: a set = {ant1_beam=1, ant2_beam=3}*/ + u8 beam_set_train_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*training pkt num of each beam set*/ + u32 beam_set_rssi_avg_sum[SUPPORT_BEAM_SET_PATTERN_NUM]; /*RSSI_sum of avg(pathA,pathB) for each beam-set)*/ + u32 beam_path_rssi_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*RSSI_sum of each path for each beam-set)*/ + + u8 beam_set_avg_evm_2ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; + u32 beam_path_evm_2ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*2SS evm_sum of each path for each beam-set)*/ + u32 beam_path_evm_2ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; + + u8 beam_set_avg_evm_1ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; + u32 beam_path_evm_1ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM];/*1SS evm_sum of each path for each beam-set)*/ + u32 beam_path_evm_1ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; + + u32 statistic_pkt_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*statistic_pkt_cnt for SmtAnt make decision*/ + + u8 total_beam_set_num; /*number of beam set can be switched*/ + u8 total_beam_set_num_2g;/*number of beam set can be switched in 2G*/ + u8 total_beam_set_num_5g;/*number of beam set can be switched in 5G*/ + + u8 rfu_codeword_table_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*2G beam truth table*/ + u8 rfu_codeword_table_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*5G beam truth table*/ + u8 rx_idle_beam_set_idx; /*the filanl decsion result*/ #endif - u1Byte b_fix_tx_ant; - BOOLEAN fix_ant_bfee; - BOOLEAN enable_ctrl_frame_antdiv; - BOOLEAN use_ctrl_frame_antdiv; - u1Byte hw_antsw_occur; - u1Byte *pForceTxAntByDesc; - u1Byte ForceTxAntByDesc; /*A temp value, will hook to driver team's outer parameter later*/ -}FAT_T,*pFAT_T; + +}; +#endif + +struct _FAST_ANTENNA_TRAINNING_ { + u8 bssid[6]; + u8 antsel_rx_keep_0; + u8 antsel_rx_keep_1; + u8 antsel_rx_keep_2; + u8 antsel_rx_keep_3; + u32 ant_sum_rssi[7]; + u32 ant_rssi_cnt[7]; + u32 ant_ave_rssi[7]; + u8 fat_state; + u8 fat_state_cnt; + u32 train_idx; + u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; + u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; + u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; + u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u8 rx_idle_ant; + u8 ant_div_on_off; + boolean is_become_linked; + u32 min_max_rssi; + u8 idx_ant_div_counter_2g; + u8 idx_ant_div_counter_5g; + u8 ant_div_2g_5g; -//1 ============================================================ -//1 enumeration -//1 ============================================================ +#ifdef ODM_EVM_ENHANCE_ANTDIV + /*For 1SS RX phy rate*/ + u32 main_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u32 aux_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u32 main_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u32 aux_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + + /*For 2SS RX phy rate*/ + u32 main_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*2SS with A1+B*/ + u32 aux_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*2SS with A2+B*/ + u32 main_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u32 aux_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + + boolean EVM_method_enable; + u8 target_ant_evm; + u8 target_ant_crc32; + u8 target_ant_tp; + u8 target_ant_enhance; + u8 pre_target_ant_enhance; + u16 main_mpdu_ok_cnt; + u16 aux_mpdu_ok_cnt; + + u32 crc32_ok_cnt; + u32 crc32_fail_cnt; + u32 main_crc32_ok_cnt; + u32 aux_crc32_ok_cnt; + u32 main_crc32_fail_cnt; + u32 aux_crc32_fail_cnt; + + u32 antdiv_tp_main; + u32 antdiv_tp_aux; + u32 antdiv_tp_main_cnt; + u32 antdiv_tp_aux_cnt; + + u8 pre_antdiv_rssi; + u8 pre_antdiv_tp; +#endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + u32 cck_ctrl_frame_cnt_main; + u32 cck_ctrl_frame_cnt_aux; + u32 ofdm_ctrl_frame_cnt_main; + u32 ofdm_ctrl_frame_cnt_aux; + u32 main_ant_ctrl_frame_sum; + u32 aux_ant_ctrl_frame_sum; + u32 main_ant_ctrl_frame_cnt; + u32 aux_ant_ctrl_frame_cnt; +#endif + u8 b_fix_tx_ant; + boolean fix_ant_bfee; + boolean enable_ctrl_frame_antdiv; + boolean use_ctrl_frame_antdiv; + u8 hw_antsw_occur; + u8 *p_force_tx_ant_by_desc; + u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's outer parameter later*/ + u8 *p_default_s0_s1; + u8 default_s0_s1; +}; +/* 1 ============================================================ + * 1 enumeration + * 1 ============================================================ */ -typedef enum _FAT_STATE /*Fast antenna training*/ + + +enum fat_state_e /*Fast antenna training*/ { FAT_BEFORE_LINK_STATE = 0, FAT_PREPARE_STATE = 1, FAT_TRAINING_STATE = 2, FAT_DECISION_STATE = 3 -}FAT_STATE_E, *PFAT_STATE_E; +}; -typedef enum _ANT_DIV_TYPE -{ - NO_ANTDIV = 0xFF, +enum ant_div_type_e { + NO_ANTDIV = 0xFF, CG_TRX_HW_ANTDIV = 0x01, CGCS_RX_HW_ANTDIV = 0x02, FIXED_HW_ANTDIV = 0x03, @@ -343,70 +394,85 @@ typedef enum _ANT_DIV_TYPE CGCS_RX_SW_ANTDIV = 0x05, S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/ S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/ - HL_SW_SMART_ANT_TYPE1 = 0x10 /*Hong-Lin Smart antenna use for 8821AE which is a 2 Ant. entitys, and each Ant. is equipped with 4 antenna patterns*/ -}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E; + HL_SW_SMART_ANT_TYPE1 = 0x10, /*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and each ant. is equipped with 4 antenna patterns*/ + HL_SW_SMART_ANT_TYPE2 = 0x11 /*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/ +}; -//1 ============================================================ -//1 function prototype -//1 ============================================================ +/* 1 ============================================================ + * 1 function prototype + * 1 ============================================================ */ -VOID -ODM_StopAntennaSwitchDm( - IN PVOID pDM_VOID - ); +void +odm_stop_antenna_switch_dm( + void *p_dm_void +); -VOID +void phydm_enable_antenna_diversity( - IN PVOID pDM_VOID - ); + void *p_dm_void +); -VOID -ODM_SetAntConfig( - IN PVOID pDM_VOID, - IN u1Byte antSetting // 0=A, 1=B, 2=C, .... - ); +void +odm_set_ant_config( + void *p_dm_void, + u8 ant_setting /* 0=A, 1=B, 2=C, .... */ +); -#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink +#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link -VOID ODM_SwAntDivRestAfterLink( - IN PVOID pDM_VOID - ); +void odm_sw_ant_div_rest_after_link( + void *p_dm_void +); #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) -VOID -ODM_UpdateRxIdleAnt( - IN PVOID pDM_VOID, - IN u1Byte Ant +void +phydm_antdiv_reset_statistic( + void *p_dm_void, + u32 macid +); + +void +odm_update_rx_idle_ant( + void *p_dm_void, + u8 ant ); #if (RTL8723B_SUPPORT == 1) -VOID -ODM_UpdateRxIdleAnt_8723B( - IN PVOID pDM_VOID, - IN u1Byte Ant, - IN u4Byte DefaultAnt, - IN u4Byte OptionalAnt +void +odm_update_rx_idle_ant_8723b( + void *p_dm_void, + u8 ant, + u32 default_ant, + u32 optional_ant ); #endif #if (RTL8188F_SUPPORT == 1) -VOID +void phydm_update_rx_idle_antenna_8188F( - IN PVOID pDM_VOID, - IN u4Byte default_ant + void *p_dm_void, + u32 default_ant ); #endif #if (RTL8723D_SUPPORT == 1) -VOID +void phydm_set_tx_ant_pwr_8723d( - IN PVOID pDM_VOID, - IN u1Byte Ant + void *p_dm_void, + u8 ant +); + +void +odm_update_rx_idle_ant_8723d( + void *p_dm_void, + u8 ant, + u32 default_ant, + u32 optional_ant ); #endif @@ -414,212 +480,253 @@ phydm_set_tx_ant_pwr_8723d( #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -ODM_SW_AntDiv_Callback( - IN PRT_TIMER pTimer - ); +void +odm_sw_antdiv_callback( + struct timer_list *p_timer +); -VOID -ODM_SW_AntDiv_WorkitemCallback( - IN PVOID pContext - ); +void +odm_sw_antdiv_workitem_callback( + void *p_context +); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -VOID -ODM_SW_AntDiv_WorkitemCallback( - IN PVOID pContext +void +odm_sw_antdiv_workitem_callback( + void *p_context ); -VOID -ODM_SW_AntDiv_Callback( - void *FunctionContext - ); +void +odm_sw_antdiv_callback( + void *function_context +); #endif -VOID -odm_S0S1_SwAntDivByCtrlFrame( - IN PVOID pDM_VOID, - IN u1Byte Step +void +odm_s0s1_sw_ant_div_by_ctrl_frame( + void *p_dm_void, + u8 step ); -VOID -odm_AntselStatisticsOfCtrlFrame( - IN PVOID pDM_VOID, - IN u1Byte antsel_tr_mux, - IN u4Byte RxPWDBAll +void +odm_antsel_statistics_of_ctrl_frame( + void *p_dm_void, + u8 antsel_tr_mux, + u32 rx_pwdb_all ); -VOID -odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI( - IN PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN PVOID p_pkt_info_void +void +odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi( + void *p_dm_void, + void *p_phy_info_void, + void *p_pkt_info_void ); #endif #ifdef ODM_EVM_ENHANCE_ANTDIV VOID -odm_EVM_FastAntTrainingCallback( - IN PVOID pDM_VOID +phydm_evm_sw_antdiv_init( + void *p_dm_void +); + +void +odm_evm_fast_ant_training_callback( + void *p_dm_void ); #endif -VOID -odm_HW_AntDiv( - IN PVOID pDM_VOID +void +odm_hw_ant_div( + void *p_dm_void ); -#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) -VOID -odm_FastAntTraining( - IN PVOID pDM_VOID +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) +void +odm_fast_ant_training( + void *p_dm_void ); -VOID -odm_FastAntTrainingCallback( - IN PVOID pDM_VOID +void +odm_fast_ant_training_callback( + void *p_dm_void ); -VOID -odm_FastAntTrainingWorkItemCallback( - IN PVOID pDM_VOID +void +odm_fast_ant_training_work_item_callback( + void *p_dm_void ); #endif -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID +void phydm_beam_switch_workitem_callback( - IN PVOID pContext - ); + void *p_context +); -VOID +void phydm_beam_decision_workitem_callback( - IN PVOID pContext - ); + void *p_context +); #endif -VOID + + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + +void +phydm_update_beam_pattern_type2( + void *p_dm_void, + u32 codeword, + u32 codeword_length +); + +void +phydm_set_rfu_beam_pattern_type2( + void *p_dm_void +); + +void +phydm_hl_smart_ant_debug_type2( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); + +#elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) + +void phydm_update_beam_pattern( - IN PVOID pDM_VOID, - IN u4Byte codeword, - IN u4Byte codeword_length - ); + void *p_dm_void, + u32 codeword, + u32 codeword_length +); void phydm_set_all_ant_same_beam_num( - IN PVOID pDM_VOID - ); + void *p_dm_void +); -VOID +void phydm_hl_smart_ant_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num ); -#endif/*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ +#endif -VOID -ODM_AntDivInit( - IN PVOID pDM_VOID + +#endif/*#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))*/ + +void +odm_ant_div_init( + void *p_dm_void ); -VOID -ODM_AntDiv( - IN PVOID pDM_VOID +void +odm_ant_div( + void *p_dm_void ); -VOID -odm_AntselStatistics( - IN PVOID pDM_VOID, - IN u1Byte antsel_tr_mux, - IN u4Byte MacId, - IN u4Byte utility, - IN u1Byte method +void +odm_antsel_statistics( + void *p_dm_void, + void *p_phy_info_void, + u8 antsel_tr_mux, + u32 mac_id, + u32 utility, + u8 method, + u8 is_cck_rate ); -VOID -ODM_Process_RSSIForAntDiv( - IN OUT PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN PVOID p_pkt_info_void +void +odm_process_rssi_for_ant_div( + void *p_dm_void, + void *p_phy_info_void, + void *p_pkt_info_void ); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -VOID -ODM_SetTxAntByTxInfo( - IN PVOID pDM_VOID, - IN pu1Byte pDesc, - IN u1Byte macId +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +void +odm_set_tx_ant_by_tx_info( + void *p_dm_void, + u8 *p_desc, + u8 mac_id ); -#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) -VOID -ODM_SetTxAntByTxInfo( +struct tx_desc; /*declared tx_desc here or compile error happened when enabled 8822B*/ + +void +odm_set_tx_ant_by_tx_info( struct rtl8192cd_priv *priv, - struct tx_desc *pdesc, - unsigned short aid + struct tx_desc *pdesc, + unsigned short aid ); #if 1/*def def CONFIG_WLAN_HAL*/ -VOID -ODM_SetTxAntByTxInfo_HAL( +void +odm_set_tx_ant_by_tx_info_hal( struct rtl8192cd_priv *priv, - PVOID pdesc_data, - u2Byte aid + void *pdesc_data, + u16 aid ); -#endif /*#ifdef CONFIG_WLAN_HAL*/ +#endif /*#ifdef CONFIG_WLAN_HAL*/ #endif -VOID -ODM_AntDiv_Config( - IN PVOID pDM_VOID +void +odm_ant_div_config( + void *p_dm_void ); -VOID -ODM_AntDivTimers( - IN PVOID pDM_VOID, - IN u1Byte state +void +odm_ant_div_timers( + void *p_dm_void, + u8 state ); -VOID +void phydm_antdiv_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len ); #endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/ -VOID -ODM_AntDivReset( - IN PVOID pDM_VOID +void +odm_ant_div_reset( + void *p_dm_void ); -VOID -odm_AntennaDiversityInit( - IN PVOID pDM_VOID +void +odm_antenna_diversity_init( + void *p_dm_void ); -VOID -odm_AntennaDiversity( - IN PVOID pDM_VOID +void +odm_antenna_diversity( + void *p_dm_void ); #endif /*#ifndef __ODMANTDIV_H__*/ diff --git a/hal/phydm/phydm_beamforming.c b/hal/phydm/phydm_beamforming.c index 8c4ef07..0587e3b 100644 --- a/hal/phydm/phydm_beamforming.c +++ b/hal/phydm/phydm_beamforming.c @@ -1,219 +1,161 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#if WPP_SOFTWARE_TRACE -#include "phydm_beamforming.tmh" -#endif + #if WPP_SOFTWARE_TRACE + #include "phydm_beamforming.tmh" + #endif #endif #if (BEAMFORMING_SUPPORT == 1) -PRT_BEAMFORM_STAINFO -phydm_staInfoInit( - IN PDM_ODM_T pDM_Odm, - IN u2Byte staIdx - ) +struct _RT_BEAMFORM_STAINFO * +phydm_sta_info_init( + struct PHY_DM_STRUCT *p_dm_odm, + u16 sta_idx +) { - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORM_STAINFO pEntry = &(pBeamInfo->BeamformSTAinfo); - PSTA_INFO_T pSTA = pDM_Odm->pODM_StaInfo[staIdx]; - PADAPTER Adapter = pDM_Odm->Adapter; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORM_STAINFO *p_entry = &(p_beam_info->beamform_sta_info); + struct sta_info *p_sta = p_dm_odm->p_odm_sta_info[sta_idx]; + struct _ADAPTER *adapter = p_dm_odm->adapter; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo); - PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo); + PMGNT_INFO p_MgntInfo = &adapter->MgntInfo; + PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo); + PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo); + u1Byte iotpeer = 0; - ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, Adapter->CurrentAddress, 6); - - pEntry->HtBeamformCap = pHTInfo->HtBeamformCap; - pEntry->VhtBeamformCap = pVHTInfo->VhtBeamformCap; + iotpeer = p_MgntInfo->IOTPeer; + odm_move_memory(p_dm_odm, p_entry->my_mac_addr, adapter->CurrentAddress, 6); + p_entry->ht_beamform_cap = p_ht_info->HtBeamformCap; + p_entry->vht_beamform_cap = p_vht_info->VhtBeamformCap; + /*IBSS, AP mode*/ - if (staIdx != 0) { - pEntry->AID = pSTA->AID; - pEntry->RA = pSTA->MacAddr; - pEntry->MacID = pSTA->AssociatedMacId; - pEntry->WirelessMode = pSTA->WirelessMode; - pEntry->BW = pSTA->BandWidth; - pEntry->CurBeamform = pSTA->HTInfo.HtCurBeamform; + if (sta_idx != 0) { + p_entry->aid = p_sta->AID; + p_entry->ra = p_sta->MacAddr; + p_entry->mac_id = p_sta->AssociatedMacId; + p_entry->wireless_mode = p_sta->WirelessMode; + p_entry->bw = p_sta->BandWidth; + p_entry->cur_beamform = p_sta->HTInfo.HtCurBeamform; } else {/*client mode*/ - pEntry->AID = pMgntInfo->mAId; - pEntry->RA = pMgntInfo->Bssid; - pEntry->MacID = pMgntInfo->mMacId; - pEntry->WirelessMode = pMgntInfo->dot11CurrentWirelessMode; - pEntry->BW = pMgntInfo->dot11CurrentChannelBandWidth; - pEntry->CurBeamform = pHTInfo->HtCurBeamform; - } - - if ((pEntry->WirelessMode & WIRELESS_MODE_AC_5G) || (pEntry->WirelessMode & WIRELESS_MODE_AC_24G)) { - if (staIdx != 0) - pEntry->CurBeamformVHT = pSTA->VHTInfo.VhtCurBeamform; + p_entry->aid = p_MgntInfo->mAId; + p_entry->ra = p_MgntInfo->Bssid; + p_entry->mac_id = p_MgntInfo->mMacId; + p_entry->wireless_mode = p_MgntInfo->dot11CurrentWirelessMode; + p_entry->bw = p_MgntInfo->dot11CurrentChannelBandWidth; + p_entry->cur_beamform = p_ht_info->HtCurBeamform; + } + + if ((p_entry->wireless_mode & WIRELESS_MODE_AC_5G) || (p_entry->wireless_mode & WIRELESS_MODE_AC_24G)) { + if (sta_idx != 0) + p_entry->cur_beamform_vht = p_sta->VHTInfo.VhtCurBeamform; else - pEntry->CurBeamformVHT = pVHTInfo->VhtCurBeamform; - } - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("pSTA->wireless_mode = 0x%x, staidx = %d\n", pSTA->WirelessMode, staIdx)); + p_entry->cur_beamform_vht = p_vht_info->VhtCurBeamform; + } + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("p_sta->wireless_mode = 0x%x, staidx = %d\n", p_sta->WirelessMode, sta_idx)); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!IS_STA_VALID(pSTA)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s => sta_info(mac_id:%d) failed\n", __func__, staIdx)); + if (!IS_STA_VALID(p_sta)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s => sta_info(mac_id:%d) failed\n", __func__, sta_idx)); rtw_warn_on(1); - return pEntry; + return p_entry; } - ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, adapter_mac_addr(pSTA->padapter), 6); - pEntry->HtBeamformCap = pSTA->htpriv.beamform_cap; - - pEntry->AID = pSTA->aid; - pEntry->RA = pSTA->hwaddr; - pEntry->MacID = pSTA->mac_id; - pEntry->WirelessMode = pSTA->wireless_mode; - pEntry->BW = pSTA->bw_mode; - - pEntry->CurBeamform = pSTA->htpriv.beamform_cap; + odm_move_memory(p_dm_odm, p_entry->my_mac_addr, adapter_mac_addr(p_sta->padapter), 6); + #ifdef CONFIG_80211N_HT + p_entry->ht_beamform_cap = p_sta->htpriv.beamform_cap; + #endif + + p_entry->aid = p_sta->aid; + p_entry->ra = p_sta->hwaddr; + p_entry->mac_id = p_sta->mac_id; + p_entry->wireless_mode = p_sta->wireless_mode; + p_entry->bw = p_sta->bw_mode; + #ifdef CONFIG_80211N_HT + p_entry->cur_beamform = p_sta->htpriv.beamform_cap; + #endif #if ODM_IC_11AC_SERIES_SUPPORT - if ((pEntry->WirelessMode & WIRELESS_MODE_AC_5G) || (pEntry->WirelessMode & WIRELESS_MODE_AC_24G)) { - pEntry->CurBeamformVHT = pSTA->vhtpriv.beamform_cap; - pEntry->VhtBeamformCap = pSTA->vhtpriv.beamform_cap; + if ((p_entry->wireless_mode & WIRELESS_MODE_AC_5G) || (p_entry->wireless_mode & WIRELESS_MODE_AC_24G)) { + p_entry->cur_beamform_vht = p_sta->vhtpriv.beamform_cap; + p_entry->vht_beamform_cap = p_sta->vhtpriv.beamform_cap; } #endif - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("pSTA->wireless_mode = 0x%x, staidx = %d\n", pSTA->wireless_mode, staIdx)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("p_sta->wireless_mode = 0x%x, staidx = %d\n", p_sta->wireless_mode, sta_idx)); #endif - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("pEntry->CurBeamform = 0x%x, pEntry->CurBeamformVHT = 0x%x\n", pEntry->CurBeamform, pEntry->CurBeamformVHT)); - return pEntry; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("p_entry->cur_beamform = 0x%x, p_entry->cur_beamform_vht = 0x%x\n", p_entry->cur_beamform, p_entry->cur_beamform_vht)); + return p_entry; } -void phydm_staInfoUpdate( - IN PDM_ODM_T pDM_Odm, - IN u2Byte staIdx, - PRT_BEAMFORMEE_ENTRY pBeamformEntry - ) -{ - PSTA_INFO_T pSTA = pDM_Odm->pODM_StaInfo[staIdx]; - - if (!IS_STA_VALID(pSTA)) - return; - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - pSTA->txbf_paid = pBeamformEntry->P_AID; - pSTA->txbf_gid = pBeamformEntry->G_ID; -#endif -} - - -u1Byte -Beamforming_GetHTNDPTxRate( - IN PVOID pDM_VOID, - u1Byte CompSteeringNumofBFer +void phydm_sta_info_update( + struct PHY_DM_STRUCT *p_dm_odm, + u16 sta_idx, + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Nr_index = 0; - u1Byte NDPTxRate; - /*Find Nr*/ - - if (pDM_Odm->SupportICType & ODM_RTL8814A) - Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), CompSteeringNumofBFer); - else - Nr_index = TxBF_Nr(1, CompSteeringNumofBFer); - - switch (Nr_index) { - case 1: - NDPTxRate = MGN_MCS8; - break; - - case 2: - NDPTxRate = MGN_MCS16; - break; + struct sta_info *p_sta = p_dm_odm->p_odm_sta_info[sta_idx]; - case 3: - NDPTxRate = MGN_MCS24; - break; - - default: - NDPTxRate = MGN_MCS8; - break; - } - -return NDPTxRate; + if (!IS_STA_VALID(p_sta)) + return; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + p_sta->txbf_paid = p_beamform_entry->p_aid; + p_sta->txbf_gid = p_beamform_entry->g_id; +#endif } -u1Byte -Beamforming_GetVHTNDPTxRate( - IN PVOID pDM_VOID, - u1Byte CompSteeringNumofBFer +struct _RT_BEAMFORMEE_ENTRY * +phydm_beamforming_get_bfee_entry_by_addr( + void *p_dm_void, + u8 *RA, + u8 *idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Nr_index = 0; - u1Byte NDPTxRate; - /*Find Nr*/ - if (pDM_Odm->SupportICType & ODM_RTL8814A) - Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), CompSteeringNumofBFer); - else - Nr_index = TxBF_Nr(1, CompSteeringNumofBFer); - - switch (Nr_index) { - case 1: - NDPTxRate = MGN_VHT2SS_MCS0; - break; - - case 2: - NDPTxRate = MGN_VHT3SS_MCS0; - break; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - case 3: - NDPTxRate = MGN_VHT4SS_MCS0; - break; - - default: - NDPTxRate = MGN_VHT2SS_MCS0; - break; - } - -return NDPTxRate; - -} - - -PRT_BEAMFORMEE_ENTRY -phydm_Beamforming_GetBFeeEntryByAddr( - IN PVOID pDM_VOID, - IN pu1Byte RA, - OUT pu1Byte Idx - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformeeEntry[i].bUsed && (eqMacAddr(RA, pBeamInfo->BeamformeeEntry[i].MacAddr))) { - *Idx = i; - return &(pBeamInfo->BeamformeeEntry[i]); + if (p_beam_info->beamformee_entry[i].is_used && (eq_mac_addr(RA, p_beam_info->beamformee_entry[i].mac_addr))) { + *idx = i; + return &(p_beam_info->beamformee_entry[i]); } } return NULL; } -PRT_BEAMFORMER_ENTRY -phydm_Beamforming_GetBFerEntryByAddr( - IN PVOID pDM_VOID, - IN pu1Byte TA, - OUT pu1Byte Idx - ) +struct _RT_BEAMFORMER_ENTRY * +phydm_beamforming_get_bfer_entry_by_addr( + void *p_dm_void, + u8 *TA, + u8 *idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformerEntry[i].bUsed && (eqMacAddr(TA, pBeamInfo->BeamformerEntry[i].MacAddr))) { - *Idx = i; - return &(pBeamInfo->BeamformerEntry[i]); + if (p_beam_info->beamformer_entry[i].is_used && (eq_mac_addr(TA, p_beam_info->beamformer_entry[i].mac_addr))) { + *idx = i; + return &(p_beam_info->beamformer_entry[i]); } } @@ -221,21 +163,21 @@ phydm_Beamforming_GetBFerEntryByAddr( } -PRT_BEAMFORMEE_ENTRY -phydm_Beamforming_GetEntryByMacId( - IN PVOID pDM_VOID, - IN u1Byte MacId, - OUT pu1Byte Idx - ) +struct _RT_BEAMFORMEE_ENTRY * +phydm_beamforming_get_entry_by_mac_id( + void *p_dm_void, + u8 mac_id, + u8 *idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformeeEntry[i].bUsed && (MacId == pBeamInfo->BeamformeeEntry[i].MacId)) { - *Idx = i; - return &(pBeamInfo->BeamformeeEntry[i]); + if (p_beam_info->beamformee_entry[i].is_used && (mac_id == p_beam_info->beamformee_entry[i].mac_id)) { + *idx = i; + return &(p_beam_info->beamformee_entry[i]); } } @@ -243,95 +185,95 @@ phydm_Beamforming_GetEntryByMacId( } -BEAMFORMING_CAP -phydm_Beamforming_GetEntryBeamCapByMacId( - IN PVOID pDM_VOID, - IN u1Byte MacId - ) +enum beamforming_cap +phydm_beamforming_get_entry_beam_cap_by_mac_id( + void *p_dm_void, + u8 mac_id +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - BEAMFORMING_CAP BeamformEntryCap = BEAMFORMING_CAP_NONE; - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + enum beamforming_cap beamform_entry_cap = BEAMFORMING_CAP_NONE; + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformeeEntry[i].bUsed && (MacId == pBeamInfo->BeamformeeEntry[i].MacId)) { - BeamformEntryCap = pBeamInfo->BeamformeeEntry[i].BeamformEntryCap; + if (p_beam_info->beamformee_entry[i].is_used && (mac_id == p_beam_info->beamformee_entry[i].mac_id)) { + beamform_entry_cap = p_beam_info->beamformee_entry[i].beamform_entry_cap; i = BEAMFORMEE_ENTRY_NUM; } } - return BeamformEntryCap; + return beamform_entry_cap; } -PRT_BEAMFORMEE_ENTRY -phydm_Beamforming_GetFreeBFeeEntry( - IN PVOID pDM_VOID, - OUT pu1Byte Idx - ) +struct _RT_BEAMFORMEE_ENTRY * +phydm_beamforming_get_free_bfee_entry( + void *p_dm_void, + u8 *idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformeeEntry[i].bUsed == FALSE) { - *Idx = i; - return &(pBeamInfo->BeamformeeEntry[i]); - } + if (p_beam_info->beamformee_entry[i].is_used == false) { + *idx = i; + return &(p_beam_info->beamformee_entry[i]); + } } return NULL; } -PRT_BEAMFORMER_ENTRY -phydm_Beamforming_GetFreeBFerEntry( - IN PVOID pDM_VOID, - OUT pu1Byte Idx - ) +struct _RT_BEAMFORMER_ENTRY * +phydm_beamforming_get_free_bfer_entry( + void *p_dm_void, + u8 *idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s ===>\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s ===>\n", __func__)); for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformerEntry[i].bUsed == FALSE) { - *Idx = i; - return &(pBeamInfo->BeamformerEntry[i]); - } + if (p_beam_info->beamformer_entry[i].is_used == false) { + *idx = i; + return &(p_beam_info->beamformer_entry[i]); + } } return NULL; } /* -// Description: Get the first entry index of MU Beamformee. -// -// Return Value: Index of the first MU sta. -// -// 2015.05.25. Created by tynli. -// -*/ -u1Byte -phydm_Beamforming_GetFirstMUBFeeEntryIdx( - IN PVOID pDM_VOID - ) + * Description: Get the first entry index of MU Beamformee. + * + * Return value: index of the first MU sta. + * + * 2015.05.25. Created by tynli. + * + */ +u8 +phydm_beamforming_get_first_mu_bfee_entry_idx( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte idx = 0xFF; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - BOOLEAN bFound = FALSE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 idx = 0xFF; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + boolean is_found = false; for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - if (pBeamInfo->BeamformeeEntry[idx].bUsed && pBeamInfo->BeamformeeEntry[idx].is_mu_sta) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d!\n", __func__, idx)); - bFound = TRUE; + if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].is_mu_sta) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d!\n", __func__, idx)); + is_found = true; break; - } + } } - if (!bFound) + if (!is_found) idx = 0xFF; return idx; @@ -339,1428 +281,1418 @@ phydm_Beamforming_GetFirstMUBFeeEntryIdx( /*Add SU BFee and MU BFee*/ -PRT_BEAMFORMEE_ENTRY -Beamforming_AddBFeeEntry( - IN PVOID pDM_VOID, - IN PRT_BEAMFORM_STAINFO pSTA, - IN BEAMFORMING_CAP BeamformCap, - IN u1Byte NumofSoundingDim, - IN u1Byte CompSteeringNumofBFer, - OUT pu1Byte Idx - ) +struct _RT_BEAMFORMEE_ENTRY * +beamforming_add_bfee_entry( + void *p_dm_void, + struct _RT_BEAMFORM_STAINFO *p_sta, + enum beamforming_cap beamform_cap, + u8 num_of_sounding_dim, + u8 comp_steering_num_of_bfer, + u8 *idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMEE_ENTRY pEntry = phydm_Beamforming_GetFreeBFeeEntry(pDM_Odm, Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (pEntry != NULL) { - pEntry->bUsed = TRUE; - pEntry->AID = pSTA->AID; - pEntry->MacId = pSTA->MacID; - pEntry->SoundBW = pSTA->BW; - ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, pSTA->MyMacAddr, 6); - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) { + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMEE_ENTRY *p_entry = phydm_beamforming_get_free_bfee_entry(p_dm_odm, idx); + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (p_entry != NULL) { + p_entry->is_used = true; + p_entry->aid = p_sta->aid; + p_entry->mac_id = p_sta->mac_id; + p_entry->sound_bw = p_sta->bw; + odm_move_memory(p_dm_odm, p_entry->my_mac_addr, p_sta->my_mac_addr, 6); + + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ap)) { /*BSSID[44:47] xor BSSID[40:43]*/ - u2Byte BSSID = ((pSTA->MyMacAddr[5] & 0xf0) >> 4) ^ (pSTA->MyMacAddr[5] & 0xf); + u16 bssid = ((p_sta->my_mac_addr[5] & 0xf0) >> 4) ^ (p_sta->my_mac_addr[5] & 0xf); /*(dec(A) + dec(B)*32) mod 512*/ - pEntry->P_AID = (pSTA->AID + BSSID * 32) & 0x1ff; - pEntry->G_ID = 63; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to STA=%d\n", __func__, pEntry->P_AID)); - } else if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) { + p_entry->p_aid = (p_sta->aid + bssid * 32) & 0x1ff; + p_entry->g_id = 63; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to STA=%d\n", __func__, p_entry->p_aid)); + } else if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) { /*ad hoc mode*/ - pEntry->P_AID = 0; - pEntry->G_ID = 63; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID as IBSS=%d\n", __func__, pEntry->P_AID)); + p_entry->p_aid = 0; + p_entry->g_id = 63; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID as IBSS=%d\n", __func__, p_entry->p_aid)); } else { /*client mode*/ - pEntry->P_AID = pSTA->RA[5]; + p_entry->p_aid = p_sta->ra[5]; /*BSSID[39:47]*/ - pEntry->P_AID = (pEntry->P_AID << 1) | (pSTA->RA[4] >> 7); - pEntry->G_ID = 0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to AP=0x%X\n", __func__, pEntry->P_AID)); + p_entry->p_aid = (p_entry->p_aid << 1) | (p_sta->ra[4] >> 7); + p_entry->g_id = 0; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to AP=0x%X\n", __func__, p_entry->p_aid)); } - cpMacAddr(pEntry->MacAddr, pSTA->RA); - pEntry->bTxBF = FALSE; - pEntry->bSound = FALSE; - pEntry->SoundPeriod = 400; - pEntry->BeamformEntryCap = BeamformCap; - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - -/* pEntry->LogSeq = 0xff; Move to Beamforming_AddBFerEntry*/ -/* pEntry->LogRetryCnt = 0; Move to Beamforming_AddBFerEntry*/ -/* pEntry->LogSuccessCnt = 0; Move to Beamforming_AddBFerEntry*/ - - pEntry->LogStatusFailCnt = 0; - - pEntry->NumofSoundingDim = NumofSoundingDim; - pEntry->CompSteeringNumofBFer = CompSteeringNumofBFer; - - if (BeamformCap & BEAMFORMER_CAP_VHT_MU) { - pDM_Odm->BeamformingInfo.beamformee_mu_cnt += 1; - pEntry->is_mu_sta = TRUE; - pDM_Odm->BeamformingInfo.FirstMUBFeeIndex = phydm_Beamforming_GetFirstMUBFeeEntryIdx(pDM_Odm); - } else if (BeamformCap & (BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) { - pDM_Odm->BeamformingInfo.beamformee_su_cnt += 1; - pEntry->is_mu_sta = FALSE; + cp_mac_addr(p_entry->mac_addr, p_sta->ra); + p_entry->is_txbf = false; + p_entry->is_sound = false; + p_entry->sound_period = 400; + p_entry->beamform_entry_cap = beamform_cap; + p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + + /* p_entry->log_seq = 0xff; Move to beamforming_add_bfer_entry*/ + /* p_entry->log_retry_cnt = 0; Move to beamforming_add_bfer_entry*/ + /* p_entry->LogSuccessCnt = 0; Move to beamforming_add_bfer_entry*/ + + p_entry->log_status_fail_cnt = 0; + + p_entry->num_of_sounding_dim = num_of_sounding_dim; + p_entry->comp_steering_num_of_bfer = comp_steering_num_of_bfer; + + if (beamform_cap & BEAMFORMER_CAP_VHT_MU) { + p_dm_odm->beamforming_info.beamformee_mu_cnt += 1; + p_entry->is_mu_sta = true; + p_dm_odm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(p_dm_odm); + } else if (beamform_cap & (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) { + p_dm_odm->beamforming_info.beamformee_su_cnt += 1; + p_entry->is_mu_sta = false; } - return pEntry; - } - else + return p_entry; + } else return NULL; } /*Add SU BFee and MU BFer*/ -PRT_BEAMFORMER_ENTRY -Beamforming_AddBFerEntry( - IN PVOID pDM_VOID, - IN PRT_BEAMFORM_STAINFO pSTA, - IN BEAMFORMING_CAP BeamformCap, - IN u1Byte NumofSoundingDim, - OUT pu1Byte Idx - ) +struct _RT_BEAMFORMER_ENTRY * +beamforming_add_bfer_entry( + void *p_dm_void, + struct _RT_BEAMFORM_STAINFO *p_sta, + enum beamforming_cap beamform_cap, + u8 num_of_sounding_dim, + u8 *idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMER_ENTRY pEntry = phydm_Beamforming_GetFreeBFerEntry(pDM_Odm, Idx); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMER_ENTRY *p_entry = phydm_beamforming_get_free_bfer_entry(p_dm_odm, idx); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - if (pEntry != NULL) { - pEntry->bUsed = TRUE; - ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, pSTA->MyMacAddr, 6); - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) { + if (p_entry != NULL) { + p_entry->is_used = true; + odm_move_memory(p_dm_odm, p_entry->my_mac_addr, p_sta->my_mac_addr, 6); + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ap)) { /*BSSID[44:47] xor BSSID[40:43]*/ - u2Byte BSSID = ((pSTA->MyMacAddr[5] & 0xf0) >> 4) ^ (pSTA->MyMacAddr[5] & 0xf); - - pEntry->P_AID = (pSTA->AID + BSSID * 32) & 0x1ff; - pEntry->G_ID = 63; + u16 bssid = ((p_sta->my_mac_addr[5] & 0xf0) >> 4) ^ (p_sta->my_mac_addr[5] & 0xf); + + p_entry->p_aid = (p_sta->aid + bssid * 32) & 0x1ff; + p_entry->g_id = 63; /*(dec(A) + dec(B)*32) mod 512*/ - } else if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) { - pEntry->P_AID = 0; - pEntry->G_ID = 63; + } else if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) { + p_entry->p_aid = 0; + p_entry->g_id = 63; } else { - pEntry->P_AID = pSTA->RA[5]; + p_entry->p_aid = p_sta->ra[5]; /*BSSID[39:47]*/ - pEntry->P_AID = (pEntry->P_AID << 1) | (pSTA->RA[4] >> 7); - pEntry->G_ID = 0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: P_AID addressed to AP=0x%X\n", __func__, pEntry->P_AID)); + p_entry->p_aid = (p_entry->p_aid << 1) | (p_sta->ra[4] >> 7); + p_entry->g_id = 0; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: P_AID addressed to AP=0x%X\n", __func__, p_entry->p_aid)); } - - cpMacAddr(pEntry->MacAddr, pSTA->RA); - pEntry->BeamformEntryCap = BeamformCap; - - pEntry->PreLogSeq = 0; /*Modified by Jeffery @2015-04-13*/ - pEntry->LogSeq = 0; /*Modified by Jeffery @2014-10-29*/ - pEntry->LogRetryCnt = 0; /*Modified by Jeffery @2014-10-29*/ - pEntry->LogSuccess = 0; /*LogSuccess is NOT needed to be accumulated, so LogSuccessCnt->LogSuccess, 2015-04-13, Jeffery*/ - pEntry->ClockResetTimes = 0; /*Modified by Jeffery @2015-04-13*/ - - pEntry->NumofSoundingDim = NumofSoundingDim; - - if (BeamformCap & BEAMFORMEE_CAP_VHT_MU) { - pDM_Odm->BeamformingInfo.beamformer_mu_cnt += 1; - pEntry->is_mu_ap = TRUE; - pEntry->AID = pSTA->AID; - } else if (BeamformCap & (BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) { - pDM_Odm->BeamformingInfo.beamformer_su_cnt += 1; - pEntry->is_mu_ap = FALSE; + + cp_mac_addr(p_entry->mac_addr, p_sta->ra); + p_entry->beamform_entry_cap = beamform_cap; + + p_entry->pre_log_seq = 0; /*Modified by Jeffery @2015-04-13*/ + p_entry->log_seq = 0; /*Modified by Jeffery @2014-10-29*/ + p_entry->log_retry_cnt = 0; /*Modified by Jeffery @2014-10-29*/ + p_entry->log_success = 0; /*log_success is NOT needed to be accumulated, so LogSuccessCnt->log_success, 2015-04-13, Jeffery*/ + p_entry->clock_reset_times = 0; /*Modified by Jeffery @2015-04-13*/ + + p_entry->num_of_sounding_dim = num_of_sounding_dim; + + if (beamform_cap & BEAMFORMEE_CAP_VHT_MU) { + p_dm_odm->beamforming_info.beamformer_mu_cnt += 1; + p_entry->is_mu_ap = true; + p_entry->aid = p_sta->aid; + } else if (beamform_cap & (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) { + p_dm_odm->beamforming_info.beamformer_su_cnt += 1; + p_entry->is_mu_ap = false; } - return pEntry; - } - else + return p_entry; + } else return NULL; } #if 0 -BOOLEAN -Beamforming_RemoveEntry( - IN PADAPTER Adapter, - IN pu1Byte RA, - OUT pu1Byte Idx - ) +boolean +beamforming_remove_entry( + struct _ADAPTER *adapter, + u8 *RA, + u8 *idx +) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + + struct _RT_BEAMFORMER_ENTRY *p_bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(p_dm_odm, RA, idx); + struct _RT_BEAMFORMEE_ENTRY *p_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, idx); + boolean ret = false; - PRT_BEAMFORMER_ENTRY pBFerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, RA, Idx); - PRT_BEAMFORMEE_ENTRY pEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, Idx); - BOOLEAN ret = FALSE; - RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s Start!\n", __func__)); - RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, pBFerEntry=0x%x\n", __func__, pBFerEntry)); - RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, pEntry=0x%x\n", __func__, pEntry)); - - if (pEntry != NULL) { - pEntry->bUsed = FALSE; - pEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; - /*pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/ - pEntry->bBeamformingInProgress = FALSE; - ret = TRUE; - } - if (pBFerEntry != NULL) { - pBFerEntry->bUsed = FALSE; - pBFerEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; - ret = TRUE; + RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, p_bfer_entry=0x%x\n", __func__, p_bfer_entry)); + RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, p_entry=0x%x\n", __func__, p_entry)); + + if (p_entry != NULL) { + p_entry->is_used = false; + p_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + /*p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/ + p_entry->is_beamforming_in_progress = false; + ret = true; + } + if (p_bfer_entry != NULL) { + p_bfer_entry->is_used = false; + p_bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + ret = true; } return ret; } #endif -/* Used for BeamformingStart_V1 */ -VOID -phydm_Beamforming_NDPARate( - IN PVOID pDM_VOID, - CHANNEL_WIDTH BW, - u1Byte Rate +/* Used for beamforming_start_v1 */ +void +phydm_beamforming_ndpa_rate( + void *p_dm_void, + CHANNEL_WIDTH BW, + u8 rate ) { - u2Byte NDPARate = Rate; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + u16 ndpa_rate = rate; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - if (NDPARate == 0) { - if(pDM_Odm->RSSI_Min > 30) // link RSSI > 30% - NDPARate = ODM_RATE24M; + if (ndpa_rate == 0) { + if (p_dm_odm->rssi_min > 30) /* link RSSI > 30% */ + ndpa_rate = ODM_RATE24M; else - NDPARate = ODM_RATE6M; + ndpa_rate = ODM_RATE6M; } - if (NDPARate < ODM_RATEMCS0) + if (ndpa_rate < ODM_RATEMCS0) BW = (CHANNEL_WIDTH)ODM_BW20M; - NDPARate = (NDPARate << 8) | BW; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_RATE, (pu1Byte)&NDPARate); + ndpa_rate = (ndpa_rate << 8) | BW; + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate); } -/* Used for BeamformingStart_SW and BeamformingStart_FW */ -VOID -phydm_Beamforming_DymNDPARate( - IN PVOID pDM_VOID +/* Used for beamforming_start_sw and beamforming_start_fw */ +void +phydm_beamforming_dym_ndpa_rate( + void *p_dm_void ) { - u2Byte NDPARate = ODM_RATE6M, BW; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (pDM_Odm->RSSI_Min > 30) /*link RSSI > 30%*/ - NDPARate = ODM_RATE24M; - else - NDPARate = ODM_RATE6M; + u16 ndpa_rate = ODM_RATE6M, BW; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + ndpa_rate = ODM_RATE6M; BW = ODM_BW20M; - NDPARate = NDPARate << 8 | BW; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_RATE, (pu1Byte)&NDPARate); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, NDPA Rate = 0x%X\n", __func__, NDPARate)); + + ndpa_rate = ndpa_rate << 8 | BW; + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, NDPA rate = 0x%X\n", __func__, ndpa_rate)); } -/* -* SW Sounding : SW Timer unit 1ms -* HW Timer unit (1/32000) s 32k is clock. +/* +* SW Sounding : SW Timer unit 1ms +* HW Timer unit (1/32000) s 32k is clock. * FW Sounding : FW Timer unit 10ms */ -VOID -Beamforming_DymPeriod( - IN PVOID pDM_VOID, - IN u8 status +void +beamforming_dym_period( + void *p_dm_void, + u8 status ) { - u1Byte Idx; - BOOLEAN bChangePeriod = FALSE; - u2Byte SoundPeriod_SW, SoundPeriod_FW; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u8 idx; + boolean is_change_period = false; + u16 sound_period_sw, sound_period_fw; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - PRT_BEAMFORMEE_ENTRY pBeamformEntry; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); - PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); + struct _RT_BEAMFORMEE_ENTRY *p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - //3 TODO per-client throughput caculation. + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - if ((*(pDM_Odm->pCurrentTxTP) + *(pDM_Odm->pCurrentRxTP) > 2) && ((pEntry->LogStatusFailCnt <= 20) || status)) { - SoundPeriod_SW = 40; /* 40ms */ - SoundPeriod_FW = 40; /* From H2C cmd, unit = 10ms */ + /* 3 TODO per-client throughput caculation. */ + + if ((*(p_dm_odm->p_current_tx_tp) + *(p_dm_odm->p_current_rx_tp) > 2) && ((p_entry->log_status_fail_cnt <= 20) || status)) { + sound_period_sw = 40; /* 40ms */ + sound_period_fw = 40; /* From H2C cmd, unit = 10ms */ } else { - SoundPeriod_SW = 4000;/* 4s */ - SoundPeriod_FW = 400; + sound_period_sw = 4000;/* 4s */ + sound_period_fw = 400; } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]SoundPeriod_SW=%d, SoundPeriod_FW=%d\n", __func__, SoundPeriod_SW, SoundPeriod_FW)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]sound_period_sw=%d, sound_period_fw=%d\n", __func__, sound_period_sw, sound_period_fw)); + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + p_beamform_entry = p_beam_info->beamformee_entry + idx; - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - pBeamformEntry = pBeamInfo->BeamformeeEntry+Idx; - - if (pBeamformEntry->DefaultCSICnt > 20) { + if (p_beamform_entry->default_csi_cnt > 20) { /*Modified by David*/ - SoundPeriod_SW = 4000; - SoundPeriod_FW = 400; + sound_period_sw = 4000; + sound_period_fw = 400; } - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Period = %d\n", __func__, SoundPeriod_SW)); - if (pBeamformEntry->BeamformEntryCap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { - if (pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER) { - if (pBeamformEntry->SoundPeriod != SoundPeriod_FW) { - pBeamformEntry->SoundPeriod = SoundPeriod_FW; - bChangePeriod = TRUE; /*Only FW sounding need to send H2C packet to change sound period. */ + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] period = %d\n", __func__, sound_period_sw)); + if (p_beamform_entry->beamform_entry_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { + if (p_sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_FW_HT_TIMER) { + if (p_beamform_entry->sound_period != sound_period_fw) { + p_beamform_entry->sound_period = sound_period_fw; + is_change_period = true; /*Only FW sounding need to send H2C packet to change sound period. */ } - } else if (pBeamformEntry->SoundPeriod != SoundPeriod_SW) { - pBeamformEntry->SoundPeriod = SoundPeriod_SW; - } + } else if (p_beamform_entry->sound_period != sound_period_sw) + p_beamform_entry->sound_period = sound_period_sw; } } - if (bChangePeriod) - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_FW_NDPA, (pu1Byte)&Idx); + if (is_change_period) + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); } -BOOLEAN -Beamforming_SendHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW, - IN u1Byte QIdx - ) +boolean +beamforming_send_ht_ndpa_packet( + void *p_dm_void, + u8 *RA, + CHANNEL_WIDTH BW, + u8 q_idx +) { - BOOLEAN ret = TRUE; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + boolean ret = true; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (QIdx == BEACON_QUEUE) - ret = SendFWHTNDPAPacket(pDM_Odm, RA, BW); + if (q_idx == BEACON_QUEUE) + ret = send_fw_ht_ndpa_packet(p_dm_odm, RA, BW); else - ret = SendSWHTNDPAPacket(pDM_Odm, RA, BW); + ret = send_sw_ht_ndpa_packet(p_dm_odm, RA, BW); return ret; } -BOOLEAN -Beamforming_SendVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW, - IN u1Byte QIdx - ) +boolean +beamforming_send_vht_ndpa_packet( + void *p_dm_void, + u8 *RA, + u16 AID, + CHANNEL_WIDTH BW, + u8 q_idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN ret = TRUE; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + boolean ret = true; - HalComTxbf_Set(pDM_Odm, TXBF_SET_GET_TX_RATE, NULL); + hal_com_txbf_set(p_dm_odm, TXBF_SET_GET_TX_RATE, NULL); - if ((pDM_Odm->TxBfDataRate >= ODM_RATEVHTSS3MCS7) && (pDM_Odm->TxBfDataRate <= ODM_RATEVHTSS3MCS9) && (pBeamInfo->snding3SS == FALSE)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: 3SS VHT 789 don't sounding\n", __func__)); + if ((p_beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7) && (p_beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9) && (p_beam_info->snding3ss == false)) + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: 3SS VHT 789 don't sounding\n", __func__)); - } else { - if (QIdx == BEACON_QUEUE) /* Send to reserved page => FW NDPA */ - ret = SendFWVHTNDPAPacket(pDM_Odm, RA, AID, BW); + else { + if (q_idx == BEACON_QUEUE) /* Send to reserved page => FW NDPA */ + ret = send_fw_vht_ndpa_packet(p_dm_odm, RA, AID, BW); else { #ifdef SUPPORT_MU_BF - #if (SUPPORT_MU_BF == 1) - pBeamInfo->is_mu_sounding = TRUE; - ret = SendSWVHTMUNDPAPacket(pDM_Odm, BW); - #else - pBeamInfo->is_mu_sounding = FALSE; - ret = SendSWVHTNDPAPacket(pDM_Odm, RA, AID, BW); - #endif +#if (SUPPORT_MU_BF == 1) + p_beam_info->is_mu_sounding = true; + ret = send_sw_vht_mu_ndpa_packet(p_dm_odm, BW); +#else + p_beam_info->is_mu_sounding = false; + ret = send_sw_vht_ndpa_packet(p_dm_odm, RA, AID, BW); +#endif #else - pBeamInfo->is_mu_sounding = FALSE; - ret = SendSWVHTNDPAPacket(pDM_Odm, RA, AID, BW); + p_beam_info->is_mu_sounding = false; + ret = send_sw_vht_ndpa_packet(p_dm_odm, RA, AID, BW); #endif } } - return ret; + return ret; } -BEAMFORMING_NOTIFY_STATE -phydm_beamfomring_bSounding( - IN PVOID pDM_VOID, - PRT_BEAMFORMING_INFO pBeamInfo, - pu1Byte Idx - ) +enum beamforming_notify_state +phydm_beamfomring_is_sounding( + void *p_dm_void, + struct _RT_BEAMFORMING_INFO *p_beam_info, + u8 *idx +) { - BEAMFORMING_NOTIFY_STATE bSounding = BEAMFORMING_NOTIFY_NONE; - RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - /*if(( Beamforming_GetBeamCap(pBeamInfo) & BEAMFORMER_CAP) == 0)*/ - /*bSounding = BEAMFORMING_NOTIFY_RESET;*/ - if (BeamOidInfo.SoundOidMode == SOUNDING_STOP_All_TIMER) - bSounding = BEAMFORMING_NOTIFY_RESET; + /*if(( Beamforming_GetBeamCap(p_beam_info) & BEAMFORMER_CAP) == 0)*/ + /*is_sounding = BEAMFORMING_NOTIFY_RESET;*/ + if (beam_oid_info.sound_oid_mode == sounding_stop_all_timer) + is_sounding = BEAMFORMING_NOTIFY_RESET; else { - u1Byte i; + u8 i; for (i = 0 ; i < BEAMFORMEE_ENTRY_NUM ; i++) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: BFee Entry %d bUsed=%d, bSound=%d\n", __func__, i, pBeamInfo->BeamformeeEntry[i].bUsed, pBeamInfo->BeamformeeEntry[i].bSound)); - if (pBeamInfo->BeamformeeEntry[i].bUsed && (!pBeamInfo->BeamformeeEntry[i].bSound)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Add BFee entry %d\n", __func__, i)); - *Idx = i; - if (pBeamInfo->BeamformeeEntry[i].is_mu_sta) - bSounding = BEAMFORMEE_NOTIFY_ADD_MU; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: BFee Entry %d is_used=%d, is_sound=%d\n", __func__, i, p_beam_info->beamformee_entry[i].is_used, p_beam_info->beamformee_entry[i].is_sound)); + if (p_beam_info->beamformee_entry[i].is_used && (!p_beam_info->beamformee_entry[i].is_sound)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Add BFee entry %d\n", __func__, i)); + *idx = i; + if (p_beam_info->beamformee_entry[i].is_mu_sta) + is_sounding = BEAMFORMEE_NOTIFY_ADD_MU; else - bSounding = BEAMFORMEE_NOTIFY_ADD_SU; + is_sounding = BEAMFORMEE_NOTIFY_ADD_SU; } - if ((!pBeamInfo->BeamformeeEntry[i].bUsed) && pBeamInfo->BeamformeeEntry[i].bSound) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Delete BFee entry %d\n", __func__, i)); - *Idx = i; - if (pBeamInfo->BeamformeeEntry[i].is_mu_sta) - bSounding = BEAMFORMEE_NOTIFY_DELETE_MU; + if ((!p_beam_info->beamformee_entry[i].is_used) && p_beam_info->beamformee_entry[i].is_sound) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Delete BFee entry %d\n", __func__, i)); + *idx = i; + if (p_beam_info->beamformee_entry[i].is_mu_sta) + is_sounding = BEAMFORMEE_NOTIFY_DELETE_MU; else - bSounding = BEAMFORMEE_NOTIFY_DELETE_SU; + is_sounding = BEAMFORMEE_NOTIFY_DELETE_SU; } } } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, bSounding = %d\n", __func__, bSounding)); - return bSounding; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, is_sounding = %d\n", __func__, is_sounding)); + return is_sounding; } -//This function is unused -u1Byte -phydm_beamforming_SoundingIdx( - IN PVOID pDM_VOID, - PRT_BEAMFORMING_INFO pBeamInfo - ) +/* This function is unused */ +u8 +phydm_beamforming_sounding_idx( + void *p_dm_void, + struct _RT_BEAMFORMING_INFO *p_beam_info +) { - u1Byte Idx = 0; - RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u8 idx = 0; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - if (BeamOidInfo.SoundOidMode == SOUNDING_SW_HT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_SW_VHT_TIMER || - BeamOidInfo.SoundOidMode == SOUNDING_HW_HT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_HW_VHT_TIMER) - Idx = BeamOidInfo.SoundOidIdx; + if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER || + beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER) + idx = beam_oid_info.sound_oid_idx; else { - u1Byte i; + u8 i; for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (pBeamInfo->BeamformeeEntry[i].bUsed && (FALSE == pBeamInfo->BeamformeeEntry[i].bSound)) { - Idx = i; + if (p_beam_info->beamformee_entry[i].is_used && (false == p_beam_info->beamformee_entry[i].is_sound)) { + idx = i; break; } } } - return Idx; + return idx; } -SOUNDING_MODE -phydm_beamforming_SoundingMode( - IN PVOID pDM_VOID, - PRT_BEAMFORMING_INFO pBeamInfo, - u1Byte Idx - ) +enum sounding_mode +phydm_beamforming_sounding_mode( + void *p_dm_void, + struct _RT_BEAMFORMING_INFO *p_beam_info, + u8 idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte SupportInterface = pDM_Odm->SupportInterface; - - RT_BEAMFORMEE_ENTRY BeamEntry = pBeamInfo->BeamformeeEntry[Idx]; - RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; - SOUNDING_MODE Mode = BeamOidInfo.SoundOidMode; - - if (BeamOidInfo.SoundOidMode == SOUNDING_SW_VHT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_HW_VHT_TIMER) { - if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) - Mode = BeamOidInfo.SoundOidMode; - else - Mode = SOUNDING_STOP_All_TIMER; - } else if (BeamOidInfo.SoundOidMode == SOUNDING_SW_HT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_HW_HT_TIMER) { - if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT) - Mode = BeamOidInfo.SoundOidMode; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 support_interface = p_dm_odm->support_interface; + + struct _RT_BEAMFORMEE_ENTRY beam_entry = p_beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; + enum sounding_mode mode = beam_oid_info.sound_oid_mode; + + if (beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER) { + if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) + mode = beam_oid_info.sound_oid_mode; else - Mode = SOUNDING_STOP_All_TIMER; - } else if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) { - if ((SupportInterface == ODM_ITRF_USB) && !(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B))) - Mode = SOUNDING_FW_VHT_TIMER; + mode = sounding_stop_all_timer; + } else if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER) { + if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) + mode = beam_oid_info.sound_oid_mode; else - Mode = SOUNDING_SW_VHT_TIMER; - } else if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT) { - if ((SupportInterface == ODM_ITRF_USB) && !(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B))) - Mode = SOUNDING_FW_HT_TIMER; + mode = sounding_stop_all_timer; + } else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) { + if ((support_interface == ODM_ITRF_USB) && !(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) + mode = SOUNDING_FW_VHT_TIMER; else - Mode = SOUNDING_SW_HT_TIMER; - } else - Mode = SOUNDING_STOP_All_TIMER; + mode = SOUNDING_SW_VHT_TIMER; + } else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) { + if ((support_interface == ODM_ITRF_USB) && !(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) + mode = SOUNDING_FW_HT_TIMER; + else + mode = SOUNDING_SW_HT_TIMER; + } else + mode = sounding_stop_all_timer; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SupportInterface=%d, Mode=%d\n", __func__, SupportInterface, Mode)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] support_interface=%d, mode=%d\n", __func__, support_interface, mode)); - return Mode; + return mode; } -u2Byte -phydm_beamforming_SoundingTime( - IN PVOID pDM_VOID, - PRT_BEAMFORMING_INFO pBeamInfo, - SOUNDING_MODE Mode, - u1Byte Idx - ) +u16 +phydm_beamforming_sounding_time( + void *p_dm_void, + struct _RT_BEAMFORMING_INFO *p_beam_info, + enum sounding_mode mode, + u8 idx +) { - u2Byte SoundingTime = 0xffff; - RT_BEAMFORMEE_ENTRY BeamEntry = pBeamInfo->BeamformeeEntry[Idx]; - RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u16 sounding_time = 0xffff; + struct _RT_BEAMFORMEE_ENTRY beam_entry = p_beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - if (Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_HW_VHT_TIMER) - SoundingTime = BeamOidInfo.SoundOidPeriod * 32; - else if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_SW_VHT_TIMER) + if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER) + sounding_time = beam_oid_info.sound_oid_period * 32; + else if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER) /*Modified by David*/ - SoundingTime = BeamEntry.SoundPeriod; /*BeamOidInfo.SoundOidPeriod;*/ + sounding_time = beam_entry.sound_period; /*beam_oid_info.sound_oid_period;*/ else - SoundingTime = BeamEntry.SoundPeriod; + sounding_time = beam_entry.sound_period; - return SoundingTime; + return sounding_time; } CHANNEL_WIDTH -phydm_beamforming_SoundingBW( - IN PVOID pDM_VOID, - PRT_BEAMFORMING_INFO pBeamInfo, - SOUNDING_MODE Mode, - u1Byte Idx - ) +phydm_beamforming_sounding_bw( + void *p_dm_void, + struct _RT_BEAMFORMING_INFO *p_beam_info, + enum sounding_mode mode, + u8 idx +) { - CHANNEL_WIDTH SoundingBW = CHANNEL_WIDTH_20; - RT_BEAMFORMEE_ENTRY BeamEntry = pBeamInfo->BeamformeeEntry[Idx]; - RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_HW_VHT_TIMER) - SoundingBW = BeamOidInfo.SoundOidBW; - else if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_SW_VHT_TIMER) + CHANNEL_WIDTH sounding_bw = CHANNEL_WIDTH_20; + struct _RT_BEAMFORMEE_ENTRY beam_entry = p_beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER) + sounding_bw = beam_oid_info.sound_oid_bw; + else if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER) /*Modified by David*/ - SoundingBW = BeamEntry.SoundBW; /*BeamOidInfo.SoundOidBW;*/ - else - SoundingBW = BeamEntry.SoundBW; + sounding_bw = beam_entry.sound_bw; /*beam_oid_info.sound_oid_bw;*/ + else + sounding_bw = beam_entry.sound_bw; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, SoundingBW=0x%X\n", __func__, SoundingBW)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, sounding_bw=0x%X\n", __func__, sounding_bw)); - return SoundingBW; + return sounding_bw; } -BOOLEAN -phydm_Beamforming_SelectBeamEntry( - IN PVOID pDM_VOID, - PRT_BEAMFORMING_INFO pBeamInfo - ) +boolean +phydm_beamforming_select_beam_entry( + void *p_dm_void, + struct _RT_BEAMFORMING_INFO *p_beam_info +) { - PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - /*pEntry.bSound is different between first and latter NDPA, and should not be used as BFee entry selection*/ - /*BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed SoundIdx.*/ - pSoundInfo->SoundIdx = phydm_beamforming_SoundingIdx(pDM_Odm, pBeamInfo); - /*pSoundInfo->SoundIdx = 0;*/ + /*p_entry.is_sound is different between first and latter NDPA, and should not be used as BFee entry selection*/ + /*BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed sound_idx.*/ + p_sound_info->sound_idx = phydm_beamforming_sounding_idx(p_dm_odm, p_beam_info); + /*p_sound_info->sound_idx = 0;*/ - if (pSoundInfo->SoundIdx < BEAMFORMEE_ENTRY_NUM) - pSoundInfo->SoundMode = phydm_beamforming_SoundingMode(pDM_Odm, pBeamInfo, pSoundInfo->SoundIdx); + if (p_sound_info->sound_idx < BEAMFORMEE_ENTRY_NUM) + p_sound_info->sound_mode = phydm_beamforming_sounding_mode(p_dm_odm, p_beam_info, p_sound_info->sound_idx); else - pSoundInfo->SoundMode = SOUNDING_STOP_All_TIMER; - - if (SOUNDING_STOP_All_TIMER == pSoundInfo->SoundMode) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Return because of SOUNDING_STOP_All_TIMER\n", __func__)); - return FALSE; + p_sound_info->sound_mode = sounding_stop_all_timer; + + if (sounding_stop_all_timer == p_sound_info->sound_mode) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Return because of sounding_stop_all_timer\n", __func__)); + return false; } else { - pSoundInfo->SoundBW = phydm_beamforming_SoundingBW(pDM_Odm, pBeamInfo, pSoundInfo->SoundMode, pSoundInfo->SoundIdx ); - pSoundInfo->SoundPeriod = phydm_beamforming_SoundingTime(pDM_Odm, pBeamInfo, pSoundInfo->SoundMode, pSoundInfo->SoundIdx ); - return TRUE; + p_sound_info->sound_bw = phydm_beamforming_sounding_bw(p_dm_odm, p_beam_info, p_sound_info->sound_mode, p_sound_info->sound_idx); + p_sound_info->sound_period = phydm_beamforming_sounding_time(p_dm_odm, p_beam_info, p_sound_info->sound_mode, p_sound_info->sound_idx); + return true; } } /*SU BFee Entry Only*/ -BOOLEAN -phydm_beamforming_StartPeriod( - IN PVOID pDM_VOID - ) +boolean +phydm_beamforming_start_period( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - BOOLEAN Ret = TRUE; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); - - phydm_Beamforming_DymNDPARate(pDM_Odm); - - phydm_Beamforming_SelectBeamEntry(pDM_Odm, pBeamInfo); // Modified - - if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) - ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, pSoundInfo->SoundPeriod); - else if (pSoundInfo->SoundMode == SOUNDING_HW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_HW_HT_TIMER || - pSoundInfo->SoundMode == SOUNDING_AUTO_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_AUTO_HT_TIMER) { - HAL_HW_TIMER_TYPE TimerType = HAL_TIMER_TXBF; - u4Byte val = (pSoundInfo->SoundPeriod | (TimerType<<16)); - - //HW timer stop: All IC has the same setting - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_STOP, (pu1Byte)(&TimerType)); - //ODM_Write1Byte(pDM_Odm, 0x15F, 0); - //HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_INIT, (pu1Byte)(&val)); - //ODM_Write1Byte(pDM_Odm, 0x164, 1); - //ODM_Write4Byte(pDM_Odm, 0x15C, val); - //HW timer start: All IC has the same setting - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_START, (pu1Byte)(&TimerType)); - //ODM_Write1Byte(pDM_Odm, 0x15F, 0x5); - } else if (pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER) - Ret = BeamformingStart_FW(pDM_Odm, pSoundInfo->SoundIdx); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + boolean ret = true; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); + + phydm_beamforming_dym_ndpa_rate(p_dm_odm); + + phydm_beamforming_select_beam_entry(p_dm_odm, p_beam_info); /* Modified */ + + if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_set_timer(p_dm_odm, &p_beam_info->beamforming_timer, p_sound_info->sound_period); + else if (p_sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_HW_HT_TIMER || + p_sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) { + HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF; + u32 val = (p_sound_info->sound_period | (timer_type << 16)); + + /* HW timer stop: All IC has the same setting */ + phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type)); + /* odm_write_1byte(p_dm_odm, 0x15F, 0); */ + /* HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes */ + phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_INIT, (u8 *)(&val)); + /* odm_write_1byte(p_dm_odm, 0x164, 1); */ + /* odm_write_4byte(p_dm_odm, 0x15C, val); */ + /* HW timer start: All IC has the same setting */ + phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_START, (u8 *)(&timer_type)); + /* odm_write_1byte(p_dm_odm, 0x15F, 0x5); */ + } else if (p_sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_FW_HT_TIMER) + ret = beamforming_start_fw(p_dm_odm, p_sound_info->sound_idx); else - Ret = FALSE; + ret = false; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SoundIdx=%d, SoundMode=%d, SoundBW=%d, SoundPeriod=%d\n", __func__, - pSoundInfo->SoundIdx, pSoundInfo->SoundMode, pSoundInfo->SoundBW, pSoundInfo->SoundPeriod)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] sound_idx=%d, sound_mode=%d, sound_bw=%d, sound_period=%d\n", __func__, + p_sound_info->sound_idx, p_sound_info->sound_mode, p_sound_info->sound_bw, p_sound_info->sound_period)); - return Ret; + return ret; } -// Used after Beamforming_Leave, and will clear the setting of the "already deleted" entry -/*SU BFee Entry Only*/ -VOID -phydm_beamforming_EndPeriod_SW( - IN PVOID pDM_VOID - ) +/* Used after beamforming_leave, and will clear the setting of the "already deleted" entry + *SU BFee Entry Only*/ +void +phydm_beamforming_end_period_sw( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); - - HAL_HW_TIMER_TYPE TimerType = HAL_TIMER_TXBF; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); + + HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) - ODM_CancelTimer(pDM_Odm, &pBeamInfo->BeamformingTimer); - else if (pSoundInfo->SoundMode == SOUNDING_HW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_HW_HT_TIMER || - pSoundInfo->SoundMode == SOUNDING_AUTO_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_AUTO_HT_TIMER) + if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_cancel_timer(p_dm_odm, &p_beam_info->beamforming_timer); + else if (p_sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_HW_HT_TIMER || + p_sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) /*HW timer stop: All IC has the same setting*/ - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_STOP, (pu1Byte)(&TimerType)); - /*ODM_Write1Byte(pDM_Odm, 0x15F, 0);*/ + phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type)); + /*odm_write_1byte(p_dm_odm, 0x15F, 0);*/ } -VOID -phydm_beamforming_EndPeriod_FW( - IN PVOID pDM_VOID - ) +void +phydm_beamforming_end_period_fw( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 idx = 0; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_FW_NDPA, (pu1Byte)&Idx); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]\n", __func__)); + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]\n", __func__)); } /*SU BFee Entry Only*/ -VOID -phydm_beamforming_ClearEntry_SW( - IN PVOID pDM_VOID, - BOOLEAN IsDelete, - u1Byte DeleteIdx - ) +void +phydm_beamforming_clear_entry_sw( + void *p_dm_void, + boolean is_delete, + u8 delete_idx +) { - u1Byte Idx = 0; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - if (IsDelete) { - if (DeleteIdx < BEAMFORMEE_ENTRY_NUM) { - pBeamformEntry = pBeamInfo->BeamformeeEntry + DeleteIdx; - if (!((!pBeamformEntry->bUsed) && pBeamformEntry->bSound)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW DeleteIdx is wrong!!!!!\n", __func__)); + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + + if (is_delete) { + if (delete_idx < BEAMFORMEE_ENTRY_NUM) { + p_beamform_entry = p_beam_info->beamformee_entry + delete_idx; + if (!((!p_beamform_entry->is_used) && p_beamform_entry->is_sound)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW delete_idx is wrong!!!!!\n", __func__)); return; } } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW delete BFee entry %d\n", __func__, DeleteIdx)); - if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) { - pBeamformEntry->bBeamformingInProgress = FALSE; - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - } else if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&DeleteIdx); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW delete BFee entry %d\n", __func__, delete_idx)); + if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) { + p_beamform_entry->is_beamforming_in_progress = false; + p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + } else if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&delete_idx); } - pBeamformEntry->bSound = FALSE; + p_beamform_entry->is_sound = false; } else { - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - pBeamformEntry = pBeamInfo->BeamformeeEntry+Idx; - - /*Used after bSounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ - /*This function is mainly used in case "BeamOidInfo.SoundOidMode == SOUNDING_STOP_All_TIMER".*/ - /*However, setting oid doesn't delete entries (bUsed is still TRUE), new entries may fail to be added in.*/ - - if (pBeamformEntry->bSound) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW reset BFee entry %d\n", __func__, Idx)); - /* - * If End procedure is + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + p_beamform_entry = p_beam_info->beamformee_entry + idx; + + /*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ + /*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/ + /*However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/ + + if (p_beamform_entry->is_sound) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW reset BFee entry %d\n", __func__, idx)); + /* + * If End procedure is * 1. Between (Send NDPA, C2H packet return), reset state to initialized. - * After C2H packet return , status bit will be set to zero. + * After C2H packet return , status bit will be set to zero. * * 2. After C2H packet, then reset state to initialized and clear status bit. */ - if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) - phydm_Beamforming_End_SW(pDM_Odm, 0); - else if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&Idx); + if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) + phydm_beamforming_end_sw(p_dm_odm, 0); + else if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx); } - pBeamformEntry->bSound = FALSE; + p_beamform_entry->is_sound = false; } } } } -VOID -phydm_beamforming_ClearEntry_FW( - IN PVOID pDM_VOID, - BOOLEAN IsDelete, - u1Byte DeleteIdx - ) +void +phydm_beamforming_clear_entry_fw( + void *p_dm_void, + boolean is_delete, + u8 delete_idx +) { - u1Byte Idx = 0; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - if (IsDelete) { - if (DeleteIdx < BEAMFORMEE_ENTRY_NUM) { - pBeamformEntry = pBeamInfo->BeamformeeEntry + DeleteIdx; + if (is_delete) { + if (delete_idx < BEAMFORMEE_ENTRY_NUM) { + p_beamform_entry = p_beam_info->beamformee_entry + delete_idx; - if (!((!pBeamformEntry->bUsed) && pBeamformEntry->bSound)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] FW DeleteIdx is wrong!!!!!\n", __func__)); + if (!((!p_beamform_entry->is_used) && p_beamform_entry->is_sound)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] FW delete_idx is wrong!!!!!\n", __func__)); return; } } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: FW delete BFee entry %d\n", __func__, DeleteIdx)); - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - pBeamformEntry->bSound = FALSE; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: FW delete BFee entry %d\n", __func__, delete_idx)); + p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + p_beamform_entry->is_sound = false; } else { - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - pBeamformEntry = pBeamInfo->BeamformeeEntry+Idx; - - /*Used after bSounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ - /*This function is mainly used in case "BeamOidInfo.SoundOidMode == SOUNDING_STOP_All_TIMER".*/ - /*However, setting oid doesn't delete entries (bUsed is still TRUE), new entries may fail to be added in.*/ - - if (pBeamformEntry->bSound) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]FW reset BFee entry %d\n", __func__, Idx)); - /* - * If End procedure is + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + p_beamform_entry = p_beam_info->beamformee_entry + idx; + + /*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ + /*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/ + /*However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/ + + if (p_beamform_entry->is_sound) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]FW reset BFee entry %d\n", __func__, idx)); + /* + * If End procedure is * 1. Between (Send NDPA, C2H packet return), reset state to initialized. - * After C2H packet return , status bit will be set to zero. + * After C2H packet return , status bit will be set to zero. * * 2. After C2H packet, then reset state to initialized and clear status bit. */ - - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; - pBeamformEntry->bSound = FALSE; + + p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + p_beamform_entry->is_sound = false; } } } } /* -* Called : -* 1. Add and delete entry : Beamforming_Enter/Beamforming_Leave +* Called : +* 1. Add and delete entry : beamforming_enter/beamforming_leave * 2. FW trigger : Beamforming_SetTxBFen -* 3. Set OID_RT_BEAMFORMING_PERIOD : BeamformingControl_V2 +* 3. Set OID_RT_BEAMFORMING_PERIOD : beamforming_control_v2 */ -VOID -phydm_Beamforming_Notify( - IN PVOID pDM_VOID - ) +void +phydm_beamforming_notify( + void *p_dm_void +) { - u1Byte Idx=BEAMFORMEE_ENTRY_NUM; - BEAMFORMING_NOTIFY_STATE bSounding = BEAMFORMING_NOTIFY_NONE; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + u8 idx = BEAMFORMEE_ENTRY_NUM; + enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - bSounding = phydm_beamfomring_bSounding(pDM_Odm, pBeamInfo, &Idx); + is_sounding = phydm_beamfomring_is_sounding(p_dm_odm, p_beam_info, &idx); + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Before notify, is_sounding=%d, idx=%d\n", __func__, is_sounding, idx)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: p_beam_info->beamformee_su_cnt = %d\n", __func__, p_beam_info->beamformee_su_cnt)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Before notify, bSounding=%d, Idx=%d\n", __func__, bSounding, Idx)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: pBeamInfo->beamformee_su_cnt = %d\n", __func__, pBeamInfo->beamformee_su_cnt)); - - switch (bSounding) { + switch (is_sounding) { case BEAMFORMEE_NOTIFY_ADD_SU: - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_SU\n", __func__)); - phydm_beamforming_StartPeriod(pDM_Odm); - break; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_SU\n", __func__)); + phydm_beamforming_start_period(p_dm_odm); + break; case BEAMFORMEE_NOTIFY_DELETE_SU: - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_SU\n", __func__)); - if (pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER) { - phydm_beamforming_ClearEntry_FW(pDM_Odm, TRUE, Idx); - if (pBeamInfo->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ - phydm_beamforming_EndPeriod_FW(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_SU\n", __func__)); + if (p_sound_info->sound_mode == SOUNDING_FW_HT_TIMER || p_sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) { + phydm_beamforming_clear_entry_fw(p_dm_odm, true, idx); + if (p_beam_info->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ + phydm_beamforming_end_period_fw(p_dm_odm); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); } } else { - phydm_beamforming_ClearEntry_SW(pDM_Odm, TRUE, Idx); - if (pBeamInfo->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ - phydm_beamforming_EndPeriod_SW(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); + phydm_beamforming_clear_entry_sw(p_dm_odm, true, idx); + if (p_beam_info->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ + phydm_beamforming_end_period_sw(p_dm_odm); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); } } - break; + break; case BEAMFORMEE_NOTIFY_ADD_MU: - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_MU\n", __func__)); - if (pBeamInfo->beamformee_mu_cnt == 2) { - /*if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) - ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, pSoundInfo->SoundPeriod);*/ - ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, 1000); /*Do MU sounding every 1sec*/ + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_MU\n", __func__)); + if (p_beam_info->beamformee_mu_cnt == 2) { + /*if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_set_timer(p_dm_odm, &p_beam_info->beamforming_timer, p_sound_info->sound_period);*/ + odm_set_timer(p_dm_odm, &p_beam_info->beamforming_timer, 1000); /*Do MU sounding every 1sec*/ } else - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less or larger than 2 MU STAs, not to set timer\n", __func__)); - break; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less or larger than 2 MU STAs, not to set timer\n", __func__)); + break; case BEAMFORMEE_NOTIFY_DELETE_MU: - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_MU\n", __func__)); - if (pBeamInfo->beamformee_mu_cnt == 1) { - /*if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER)*/{ - ODM_CancelTimer(pDM_Odm, &pBeamInfo->BeamformingTimer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less than 2 MU STAs, stop sounding\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_MU\n", __func__)); + if (p_beam_info->beamformee_mu_cnt == 1) { + /*if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER)*/{ + odm_cancel_timer(p_dm_odm, &p_beam_info->beamforming_timer); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less than 2 MU STAs, stop sounding\n", __func__)); } } - break; + break; case BEAMFORMING_NOTIFY_RESET: - if (pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER) { - phydm_beamforming_ClearEntry_FW(pDM_Odm, FALSE, Idx); - phydm_beamforming_EndPeriod_FW(pDM_Odm); + if (p_sound_info->sound_mode == SOUNDING_FW_HT_TIMER || p_sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) { + phydm_beamforming_clear_entry_fw(p_dm_odm, false, idx); + phydm_beamforming_end_period_fw(p_dm_odm); } else { - phydm_beamforming_ClearEntry_SW(pDM_Odm, FALSE, Idx); - phydm_beamforming_EndPeriod_SW(pDM_Odm); + phydm_beamforming_clear_entry_sw(p_dm_odm, false, idx); + phydm_beamforming_end_period_sw(p_dm_odm); } - break; + break; default: - break; + break; } } -BOOLEAN -Beamforming_InitEntry( - IN PVOID pDM_VOID, - IN u2Byte staIdx, - pu1Byte BFerBFeeIdx - ) +boolean +beamforming_init_entry( + void *p_dm_void, + u16 sta_idx, + u8 *bfer_bfee_idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; - PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL; - PRT_BEAMFORM_STAINFO pSTA = NULL; - BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; - u1Byte BFerIdx=0xF, BFeeIdx=0xF; - u1Byte NumofSoundingDim = 0, CompSteeringNumofBFer = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; + struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry = NULL; + struct _RT_BEAMFORM_STAINFO *p_sta = NULL; + enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; + u8 bfer_idx = 0xF, bfee_idx = 0xF; + u8 num_of_sounding_dim = 0, comp_steering_num_of_bfer = 0; - pSTA = phydm_staInfoInit(pDM_Odm, staIdx); + p_sta = phydm_sta_info_init(p_dm_odm, sta_idx); /*The current setting does not support Beaforming*/ - if (BEAMFORMING_CAP_NONE == pSTA->HtBeamformCap && BEAMFORMING_CAP_NONE == pSTA->VhtBeamformCap) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("The configuration disabled Beamforming! Skip...\n")); - return FALSE; + if (BEAMFORMING_CAP_NONE == p_sta->ht_beamform_cap && BEAMFORMING_CAP_NONE == p_sta->vht_beamform_cap) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("The configuration disabled Beamforming! Skip...\n")); + return false; } - if (pSTA->WirelessMode < WIRELESS_MODE_N_24G) - return FALSE; + if (p_sta->wireless_mode < WIRELESS_MODE_N_24G) + return false; else { - if (pSTA->WirelessMode & WIRELESS_MODE_N_5G || pSTA->WirelessMode & WIRELESS_MODE_N_24G) {/*HT*/ - if (TEST_FLAG(pSTA->CurBeamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {/*We are Beamformee because the STA is Beamformer*/ - BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMEE_CAP_HT_EXPLICIT); - NumofSoundingDim = (pSTA->CurBeamform&BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP)>>6; + if (p_sta->wireless_mode & WIRELESS_MODE_N_5G || p_sta->wireless_mode & WIRELESS_MODE_N_24G) {/*HT*/ + if (TEST_FLAG(p_sta->cur_beamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {/*We are Beamformee because the STA is Beamformer*/ + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_HT_EXPLICIT); + num_of_sounding_dim = (p_sta->cur_beamform & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6; } /*We are Beamformer because the STA is Beamformee*/ - if (TEST_FLAG(pSTA->CurBeamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) || - TEST_FLAG(pSTA->HtBeamformCap, BEAMFORMING_HT_BEAMFORMER_TEST)) { - BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMER_CAP_HT_EXPLICIT); - CompSteeringNumofBFer = (pSTA->CurBeamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM)>>4; + if (TEST_FLAG(p_sta->cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) || + TEST_FLAG(p_sta->ht_beamform_cap, BEAMFORMING_HT_BEAMFORMER_TEST)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT); + comp_steering_num_of_bfer = (p_sta->cur_beamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4; } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT CurBeamform=0x%X, BeamformCap=0x%X\n", __func__, pSTA->CurBeamform, BeamformCap)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT NumofSoundingDim=%d, CompSteeringNumofBFer=%d\n", __func__, NumofSoundingDim, CompSteeringNumofBFer)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT cur_beamform=0x%X, beamform_cap=0x%X\n", __func__, p_sta->cur_beamform, beamform_cap)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT num_of_sounding_dim=%d, comp_steering_num_of_bfer=%d\n", __func__, num_of_sounding_dim, comp_steering_num_of_bfer)); } -#if (ODM_IC_11AC_SERIES_SUPPORT == 1) - if (pSTA->WirelessMode & WIRELESS_MODE_AC_5G || pSTA->WirelessMode & WIRELESS_MODE_AC_24G) { /*VHT*/ +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + if (p_sta->wireless_mode & WIRELESS_MODE_AC_5G || p_sta->wireless_mode & WIRELESS_MODE_AC_24G) { /*VHT*/ /* We are Beamformee because the STA is SU Beamformer*/ - if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { - BeamformCap =(BEAMFORMING_CAP)(BeamformCap |BEAMFORMEE_CAP_VHT_SU); - NumofSoundingDim = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM)>>12; + if (TEST_FLAG(p_sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_SU); + num_of_sounding_dim = (p_sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; } /* We are Beamformer because the STA is SU Beamformee*/ - if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) || - TEST_FLAG(pSTA->VhtBeamformCap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { - BeamformCap =(BEAMFORMING_CAP)(BeamformCap |BEAMFORMER_CAP_VHT_SU); - CompSteeringNumofBFer = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMER_STS_CAP)>>8; + if (TEST_FLAG(p_sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) || + TEST_FLAG(p_sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_SU); + comp_steering_num_of_bfer = (p_sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; } /* We are Beamformee because the STA is MU Beamformer*/ - if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { - BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMEE_CAP_VHT_MU); - NumofSoundingDim = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM)>>12; + if (TEST_FLAG(p_sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_MU); + num_of_sounding_dim = (p_sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; } /* We are Beamformer because the STA is MU Beamformee*/ - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) { /* Only AP mode supports to act an MU beamformer */ - if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) || - TEST_FLAG(pSTA->VhtBeamformCap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { - BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMER_CAP_VHT_MU); - CompSteeringNumofBFer = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMER_STS_CAP)>>8; + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ap)) { /* Only AP mode supports to act an MU beamformer */ + if (TEST_FLAG(p_sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) || + TEST_FLAG(p_sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_MU); + comp_steering_num_of_bfer = (p_sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; } } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT CurBeamformVHT=0x%X, BeamformCap=0x%X\n", __func__, pSTA->CurBeamformVHT, BeamformCap)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT NumofSoundingDim=0x%X, CompSteeringNumofBFer=0x%X\n", __func__, NumofSoundingDim, CompSteeringNumofBFer)); - + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT cur_beamform_vht=0x%X, beamform_cap=0x%X\n", __func__, p_sta->cur_beamform_vht, beamform_cap)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT num_of_sounding_dim=0x%X, comp_steering_num_of_bfer=0x%X\n", __func__, num_of_sounding_dim, comp_steering_num_of_bfer)); + } #endif } - if(BeamformCap == BEAMFORMING_CAP_NONE) - return FALSE; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Self BF Entry Cap = 0x%02X\n", __func__, BeamformCap)); + if (beamform_cap == BEAMFORMING_CAP_NONE) + return false; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Self BF Entry Cap = 0x%02X\n", __func__, beamform_cap)); /*We are BFee, so the entry is BFer*/ - if (BeamformCap & (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) { - pBeamformerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, pSTA->RA, &BFerIdx); - - if (pBeamformerEntry == NULL) { - pBeamformerEntry = Beamforming_AddBFerEntry(pDM_Odm, pSTA, BeamformCap, NumofSoundingDim , &BFerIdx); - if (pBeamformerEntry == NULL) - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Not enough BFer entry!!!!!\n", __func__)); + if (beamform_cap & (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) { + p_beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(p_dm_odm, p_sta->ra, &bfer_idx); + + if (p_beamformer_entry == NULL) { + p_beamformer_entry = beamforming_add_bfer_entry(p_dm_odm, p_sta, beamform_cap, num_of_sounding_dim, &bfer_idx); + if (p_beamformer_entry == NULL) + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Not enough BFer entry!!!!!\n", __func__)); } } /*We are BFer, so the entry is BFee*/ - if (BeamformCap & (BEAMFORMER_CAP_VHT_MU | BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) { - pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, pSTA->RA, &BFeeIdx); + if (beamform_cap & (BEAMFORMER_CAP_VHT_MU | BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) { + p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, p_sta->ra, &bfee_idx); /*¦pªGBFeeIdx = 0xF «h¥Nªí¥Ø«eentry·í¤¤¨S¦³¬Û¦PªºMACID¦b¤º*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BFee entry 0x%X by address\n", __func__, BFeeIdx)); - if (pBeamformEntry == NULL) { - pBeamformEntry = Beamforming_AddBFeeEntry(pDM_Odm, pSTA, BeamformCap, NumofSoundingDim, CompSteeringNumofBFer, &BFeeIdx); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: pSTA->AID=%d, pSTA->MacID=%d\n", __func__, pSTA->AID, pSTA->MacID)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BFee entry 0x%X by address\n", __func__, bfee_idx)); + if (p_beamform_entry == NULL) { + p_beamform_entry = beamforming_add_bfee_entry(p_dm_odm, p_sta, beamform_cap, num_of_sounding_dim, comp_steering_num_of_bfer, &bfee_idx); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: p_sta->AID=%d, p_sta->mac_id=%d\n", __func__, p_sta->aid, p_sta->mac_id)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: Add BFee entry %d\n", __func__, BFeeIdx)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: Add BFee entry %d\n", __func__, bfee_idx)); - if (pBeamformEntry == NULL) - return FALSE; + if (p_beamform_entry == NULL) + return false; else - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; } else { /*Entry has been created. If entry is initialing or progressing then errors occur.*/ - if (pBeamformEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_INITIALIZED && - pBeamformEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSED) { - return FALSE; - } else - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + if (p_beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && + p_beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) + return false; + else + p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; } - pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; - phydm_staInfoUpdate(pDM_Odm, staIdx, pBeamformEntry); + p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + phydm_sta_info_update(p_dm_odm, sta_idx, p_beamform_entry); } - *BFerBFeeIdx = (BFerIdx<<4) | BFeeIdx; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End: BFerIdx=0x%X, BFeeIdx=0x%X, BFerBFeeIdx=0x%X\n", __func__, BFerIdx, BFeeIdx, *BFerBFeeIdx)); + *bfer_bfee_idx = (bfer_idx << 4) | bfee_idx; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End: bfer_idx=0x%X, bfee_idx=0x%X, bfer_bfee_idx=0x%X\n", __func__, bfer_idx, bfee_idx, *bfer_bfee_idx)); - return TRUE; + return true; } -VOID -Beamforming_DeInitEntry( - IN PVOID pDM_VOID, - pu1Byte RA - ) +void +beamforming_deinit_entry( + void *p_dm_void, + u8 *RA +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx = 0; - - PRT_BEAMFORMER_ENTRY pBFerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, RA, &Idx); - PRT_BEAMFORMEE_ENTRY pBFeeEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - BOOLEAN ret = FALSE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 idx = 0; + + struct _RT_BEAMFORMER_ENTRY *p_bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(p_dm_odm, RA, &idx); + struct _RT_BEAMFORMEE_ENTRY *p_bfee_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + boolean ret = false; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (p_bfee_entry != NULL) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, p_bfee_entry\n", __func__)); + p_bfee_entry->is_used = false; + p_bfee_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + p_bfee_entry->is_beamforming_in_progress = false; + if (p_bfee_entry->is_mu_sta) { + p_dm_odm->beamforming_info.beamformee_mu_cnt -= 1; + p_dm_odm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(p_dm_odm); + } else + p_dm_odm->beamforming_info.beamformee_su_cnt -= 1; + ret = true; + } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (pBFeeEntry != NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, pBFeeEntry\n", __func__)); - pBFeeEntry->bUsed = FALSE; - pBFeeEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; - pBFeeEntry->bBeamformingInProgress = FALSE; - if (pBFeeEntry->is_mu_sta) { - pDM_Odm->BeamformingInfo.beamformee_mu_cnt -= 1; - pDM_Odm->BeamformingInfo.FirstMUBFeeIndex = phydm_Beamforming_GetFirstMUBFeeEntryIdx(pDM_Odm); - } else { - pDM_Odm->BeamformingInfo.beamformee_su_cnt -= 1; - } - ret = TRUE; - } - - if (pBFerEntry != NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, pBFerEntry\n", __func__)); - pBFerEntry->bUsed = FALSE; - pBFerEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; - if (pBFerEntry->is_mu_ap) - pDM_Odm->BeamformingInfo.beamformer_mu_cnt -= 1; + if (p_bfer_entry != NULL) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, p_bfer_entry\n", __func__)); + p_bfer_entry->is_used = false; + p_bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + if (p_bfer_entry->is_mu_ap) + p_dm_odm->beamforming_info.beamformer_mu_cnt -= 1; else - pDM_Odm->BeamformingInfo.beamformer_su_cnt -= 1; - ret = TRUE; + p_dm_odm->beamforming_info.beamformer_su_cnt -= 1; + ret = true; } - if (ret == TRUE) - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_LEAVE, (pu1Byte)&Idx); + if (ret == true) + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_LEAVE, (u8 *)&idx); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, Idx = 0x%X\n", __func__, Idx)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, idx = 0x%X\n", __func__, idx)); } -BOOLEAN -BeamformingStart_V1( - IN PVOID pDM_VOID, - pu1Byte RA, - BOOLEAN Mode, +boolean +beamforming_start_v1( + void *p_dm_void, + u8 *RA, + boolean mode, CHANNEL_WIDTH BW, - u1Byte Rate - ) + u8 rate +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx = 0; - PRT_BEAMFORMEE_ENTRY pEntry; - BOOLEAN ret = TRUE; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - - pEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *p_entry; + boolean ret = true; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + + p_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); - if (pEntry->bUsed == FALSE) { - pEntry->bBeamformingInProgress = FALSE; - return FALSE; + if (p_entry->is_used == false) { + p_entry->is_beamforming_in_progress = false; + return false; } else { - if (pEntry->bBeamformingInProgress) - return FALSE; + if (p_entry->is_beamforming_in_progress) + return false; - pEntry->bBeamformingInProgress = TRUE; + p_entry->is_beamforming_in_progress = true; - if (Mode == 1) { - if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT)) { - pEntry->bBeamformingInProgress = FALSE; - return FALSE; + if (mode == 1) { + if (!(p_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) { + p_entry->is_beamforming_in_progress = false; + return false; } - } else if (Mode == 0) { - if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)) { - pEntry->bBeamformingInProgress = FALSE; - return FALSE; + } else if (mode == 0) { + if (!(p_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) { + p_entry->is_beamforming_in_progress = false; + return false; } } - if (pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_INITIALIZED && pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSED) { - pEntry->bBeamformingInProgress = FALSE; - return FALSE; + if (p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + p_entry->is_beamforming_in_progress = false; + return false; } else { - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSING; - pEntry->bSound = TRUE; + p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + p_entry->is_sound = true; } } - pEntry->SoundBW = BW; - pBeamInfo->BeamformeeCurIdx = Idx; - phydm_Beamforming_NDPARate(pDM_Odm, BW, Rate); - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&Idx); + p_entry->sound_bw = BW; + p_beam_info->beamformee_cur_idx = idx; + phydm_beamforming_ndpa_rate(p_dm_odm, BW, rate); + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx); - if (Mode == 1) - ret = Beamforming_SendHTNDPAPacket(pDM_Odm, RA, BW, NORMAL_QUEUE); + if (mode == 1) + ret = beamforming_send_ht_ndpa_packet(p_dm_odm, RA, BW, NORMAL_QUEUE); else - ret = Beamforming_SendVHTNDPAPacket(pDM_Odm, RA, pEntry->AID, BW, NORMAL_QUEUE); + ret = beamforming_send_vht_ndpa_packet(p_dm_odm, RA, p_entry->aid, BW, NORMAL_QUEUE); - if (ret == FALSE) { - Beamforming_Leave(pDM_Odm, RA); - pEntry->bBeamformingInProgress = FALSE; - return FALSE; + if (ret == false) { + beamforming_leave(p_dm_odm, RA); + p_entry->is_beamforming_in_progress = false; + return false; } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Idx %d\n", __func__, Idx)); - return TRUE; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s idx %d\n", __func__, idx)); + return true; } -BOOLEAN -BeamformingStart_SW( - IN PVOID pDM_VOID, - u1Byte Idx, - u1Byte Mode, +boolean +beamforming_start_sw( + void *p_dm_void, + u8 idx, + u8 mode, CHANNEL_WIDTH BW - ) +) { - pu1Byte RA = NULL; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMEE_ENTRY pEntry; - BOOLEAN ret = TRUE; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + u8 *ra = NULL; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMEE_ENTRY *p_entry; + boolean ret = true; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - if (pBeamInfo->is_mu_sounding) { - pBeamInfo->is_mu_sounding_in_progress = TRUE; - pEntry = &(pBeamInfo->BeamformeeEntry[Idx]); - RA = pEntry->MacAddr; + if (p_beam_info->is_mu_sounding) { + p_beam_info->is_mu_sounding_in_progress = true; + p_entry = &(p_beam_info->beamformee_entry[idx]); + ra = p_entry->mac_addr; } else { - pEntry = &(pBeamInfo->BeamformeeEntry[Idx]); + p_entry = &(p_beam_info->beamformee_entry[idx]); - if (pEntry->bUsed == FALSE) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for Idx =%d\n", Idx)); - pEntry->bBeamformingInProgress = FALSE; - return FALSE; + if (p_entry->is_used == false) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for idx =%d\n", idx)); + p_entry->is_beamforming_in_progress = false; + return false; } else { - if (pEntry->bBeamformingInProgress) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("bBeamformingInProgress, skip...\n")); - return FALSE; + if (p_entry->is_beamforming_in_progress) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("is_beamforming_in_progress, skip...\n")); + return false; } - pEntry->bBeamformingInProgress = TRUE; - RA = pEntry->MacAddr; - - if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_AUTO_HT_TIMER) { - if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT)) { - pEntry->bBeamformingInProgress = FALSE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n", __func__)); - return FALSE; + p_entry->is_beamforming_in_progress = true; + ra = p_entry->mac_addr; + + if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) { + if (!(p_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) { + p_entry->is_beamforming_in_progress = false; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n", __func__)); + return false; } - } else if (Mode == SOUNDING_SW_VHT_TIMER || Mode == SOUNDING_HW_VHT_TIMER || Mode == SOUNDING_AUTO_VHT_TIMER) { - if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)) { - pEntry->bBeamformingInProgress = FALSE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n", __func__)); - return FALSE; + } else if (mode == SOUNDING_SW_VHT_TIMER || mode == SOUNDING_HW_VHT_TIMER || mode == SOUNDING_AUTO_VHT_TIMER) { + if (!(p_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) { + p_entry->is_beamforming_in_progress = false; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n", __func__)); + return false; } } - if (pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_INITIALIZED && pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSED) { - pEntry->bBeamformingInProgress = FALSE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by incorrect BeamformEntryState(%d) <==\n", __func__, pEntry->BeamformEntryState)); - return FALSE; + if (p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + p_entry->is_beamforming_in_progress = false; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by incorrect beamform_entry_state(%d) <==\n", __func__, p_entry->beamform_entry_state)); + return false; } else { - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSING; - pEntry->bSound = TRUE; + p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + p_entry->is_sound = true; } } - pBeamInfo->BeamformeeCurIdx = Idx; + p_beam_info->beamformee_cur_idx = idx; } - + /*2014.12.22 Luke: Need to be checked*/ - /*GET_TXBF_INFO(Adapter)->fTxbfSet(Adapter, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&Idx);*/ + /*GET_TXBF_INFO(adapter)->fTxbfSet(adapter, TXBF_SET_SOUNDING_STATUS, (u8*)&idx);*/ - if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_AUTO_HT_TIMER) - ret = Beamforming_SendHTNDPAPacket(pDM_Odm, RA , BW, NORMAL_QUEUE); + if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) + ret = beamforming_send_ht_ndpa_packet(p_dm_odm, ra, BW, NORMAL_QUEUE); else - ret = Beamforming_SendVHTNDPAPacket(pDM_Odm, RA , pEntry->AID, BW, NORMAL_QUEUE); + ret = beamforming_send_vht_ndpa_packet(p_dm_odm, ra, p_entry->aid, BW, NORMAL_QUEUE); - if (ret == FALSE) { - Beamforming_Leave(pDM_Odm, RA); - pEntry->bBeamformingInProgress = FALSE; - return FALSE; + if (ret == false) { + beamforming_leave(p_dm_odm, ra); + p_entry->is_beamforming_in_progress = false; + return false; } - + /*-------------------------- - // Send BF Report Poll for MU BF + * Send BF Report Poll for MU BF --------------------------*/ #ifdef SUPPORT_MU_BF #if (SUPPORT_MU_BF == 1) -{ - u1Byte idx, PollSTACnt = 0; - BOOLEAN bGetFirstBFee = FALSE; - - if (pBeamInfo->beamformee_mu_cnt > 1) { /* More than 1 MU STA*/ - - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - pEntry = &(pBeamInfo->BeamformeeEntry[idx]); - if (pEntry->is_mu_sta) { - if (bGetFirstBFee) { - PollSTACnt++; - if (PollSTACnt == (pBeamInfo->beamformee_mu_cnt - 1))/* The last STA*/ - SendSWVHTBFReportPoll(pDM_Odm, pEntry->MacAddr, TRUE); - else - SendSWVHTBFReportPoll(pDM_Odm, pEntry->MacAddr, FALSE); - } else { - bGetFirstBFee = TRUE; + { + u8 idx, poll_sta_cnt = 0; + boolean is_get_first_bfee = false; + + if (p_beam_info->beamformee_mu_cnt > 1) { /* More than 1 MU STA*/ + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + p_entry = &(p_beam_info->beamformee_entry[idx]); + if (p_entry->is_mu_sta) { + if (is_get_first_bfee) { + poll_sta_cnt++; + if (poll_sta_cnt == (p_beam_info->beamformee_mu_cnt - 1))/* The last STA*/ + send_sw_vht_bf_report_poll(p_dm_odm, p_entry->mac_addr, true); + else + send_sw_vht_bf_report_poll(p_dm_odm, p_entry->mac_addr, false); + } else + is_get_first_bfee = true; } } } } -} #endif #endif - return TRUE; + return true; } -BOOLEAN -BeamformingStart_FW( - IN PVOID pDM_VOID, - u1Byte Idx - ) +boolean +beamforming_start_fw( + void *p_dm_void, + u8 idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMEE_ENTRY pEntry; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - - pEntry = &(pBeamInfo->BeamformeeEntry[Idx]); - if (pEntry->bUsed == FALSE) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for Idx =%d\n", Idx)); - return FALSE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMEE_ENTRY *p_entry; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + + p_entry = &(p_beam_info->beamformee_entry[idx]); + if (p_entry->is_used == false) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for idx =%d\n", idx)); + return false; } - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSING; - pEntry->bSound = TRUE; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_FW_NDPA, (pu1Byte)&Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, Idx=0x%X\n", __func__, Idx)); - return TRUE; + p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + p_entry->is_sound = true; + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, idx=0x%X\n", __func__, idx)); + return true; } -VOID -Beamforming_CheckSoundingSuccess( - IN PVOID pDM_VOID, - BOOLEAN Status +void +beamforming_check_sounding_success( + void *p_dm_void, + boolean status ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[David]@%s Start!\n", __func__)); - - if (Status == 1) { - if (pEntry->LogStatusFailCnt == 21) - Beamforming_DymPeriod(pDM_Odm, Status); - pEntry->LogStatusFailCnt = 0; - } else if (pEntry->LogStatusFailCnt <= 20) { - pEntry->LogStatusFailCnt++; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s LogStatusFailCnt %d\n", __func__, pEntry->LogStatusFailCnt)); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[David]@%s Start!\n", __func__)); + + if (status == 1) { + if (p_entry->log_status_fail_cnt == 21) + beamforming_dym_period(p_dm_odm, status); + p_entry->log_status_fail_cnt = 0; + } else if (p_entry->log_status_fail_cnt <= 20) { + p_entry->log_status_fail_cnt++; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s log_status_fail_cnt %d\n", __func__, p_entry->log_status_fail_cnt)); } - if (pEntry->LogStatusFailCnt > 20) { - pEntry->LogStatusFailCnt = 21; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s LogStatusFailCnt > 20, Stop SOUNDING\n", __func__)); - Beamforming_DymPeriod(pDM_Odm, Status); + if (p_entry->log_status_fail_cnt > 20) { + p_entry->log_status_fail_cnt = 21; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s log_status_fail_cnt > 20, Stop SOUNDING\n", __func__)); + beamforming_dym_period(p_dm_odm, status); } } -VOID -phydm_Beamforming_End_SW( - IN PVOID pDM_VOID, - BOOLEAN Status - ) +void +phydm_beamforming_end_sw( + void *p_dm_void, + boolean status +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); - - if (pBeamInfo->is_mu_sounding) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: MU sounding done\n", __func__)); - pBeamInfo->is_mu_sounding_in_progress = FALSE; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); + + if (p_beam_info->is_mu_sounding) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: MU sounding done\n", __func__)); + p_beam_info->is_mu_sounding_in_progress = false; + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&(p_beam_info->beamformee_cur_idx)); } else { - if (pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSING) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamformStatus %d\n", __func__, pEntry->BeamformEntryState)); + if (p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSING) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamformStatus %d\n", __func__, p_entry->beamform_entry_state)); return; } - if ((pDM_Odm->TxBfDataRate >= ODM_RATEVHTSS3MCS7) && (pDM_Odm->TxBfDataRate <= ODM_RATEVHTSS3MCS9) && (pBeamInfo->snding3SS == FALSE)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] VHT3SS 7,8,9, do not apply V matrix.\n", __func__)); - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); - } else if (Status == 1) { - pEntry->LogStatusFailCnt = 0; - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); + if ((p_beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7) && (p_beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9) && (p_beam_info->snding3ss == false)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] VHT3SS 7,8,9, do not apply V matrix.\n", __func__)); + p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&(p_beam_info->beamformee_cur_idx)); + } else if (status == 1) { + p_entry->log_status_fail_cnt = 0; + p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&(p_beam_info->beamformee_cur_idx)); } else { - pEntry->LogStatusFailCnt++; - pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; - HalComTxbf_Set(pDM_Odm, TXBF_SET_TX_PATH_RESET, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] LogStatusFailCnt %d\n", __func__, pEntry->LogStatusFailCnt)); + p_entry->log_status_fail_cnt++; + p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + hal_com_txbf_set(p_dm_odm, TXBF_SET_TX_PATH_RESET, (u8 *)&(p_beam_info->beamformee_cur_idx)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] log_status_fail_cnt %d\n", __func__, p_entry->log_status_fail_cnt)); } - - if (pEntry->LogStatusFailCnt > 50) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s LogStatusFailCnt > 50, Stop SOUNDING\n", __func__)); - pEntry->bSound = FALSE; - Beamforming_DeInitEntry(pDM_Odm, pEntry->MacAddr); + + if (p_entry->log_status_fail_cnt > 50) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s log_status_fail_cnt > 50, Stop SOUNDING\n", __func__)); + p_entry->is_sound = false; + beamforming_deinit_entry(p_dm_odm, p_entry->mac_addr); /*Modified by David - Every action of deleting entry should follow by Notify*/ - phydm_Beamforming_Notify(pDM_Odm); - } - - pEntry->bBeamformingInProgress = FALSE; + phydm_beamforming_notify(p_dm_odm); + } + + p_entry->is_beamforming_in_progress = false; } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Status=%d\n", __func__, Status)); -} + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: status=%d\n", __func__, status)); +} -VOID -Beamforming_TimerCallback( +void +beamforming_timer_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PVOID pDM_VOID -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - IN PVOID pContext + void *p_dm_void +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + void *p_context #endif - ) +) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER Adapter = (PADAPTER)pContext; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct _ADAPTER *adapter = (struct _ADAPTER *)p_context; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; #endif - BOOLEAN ret = FALSE; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); - PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); - BOOLEAN bBeamformingInProgress; + boolean ret = false; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); + struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); + boolean is_beamforming_in_progress; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - if (pBeamInfo->is_mu_sounding) - bBeamformingInProgress = pBeamInfo->is_mu_sounding_in_progress; + if (p_beam_info->is_mu_sounding) + is_beamforming_in_progress = p_beam_info->is_mu_sounding_in_progress; else - bBeamformingInProgress = pEntry->bBeamformingInProgress; + is_beamforming_in_progress = p_entry->is_beamforming_in_progress; - if (bBeamformingInProgress) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("bBeamformingInProgress, reset it\n")); - phydm_Beamforming_End_SW(pDM_Odm, 0); - } + if (is_beamforming_in_progress) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("is_beamforming_in_progress, reset it\n")); + phydm_beamforming_end_sw(p_dm_odm, 0); + } - ret = phydm_Beamforming_SelectBeamEntry(pDM_Odm, pBeamInfo); + ret = phydm_beamforming_select_beam_entry(p_dm_odm, p_beam_info); #if (SUPPORT_MU_BF == 1) - if (ret && pBeamInfo->beamformee_mu_cnt > 1) + if (ret && p_beam_info->beamformee_mu_cnt > 1) ret = 1; else ret = 0; #endif if (ret) - ret = BeamformingStart_SW(pDM_Odm, pSoundInfo->SoundIdx, pSoundInfo->SoundMode, pSoundInfo->SoundBW); + ret = beamforming_start_sw(p_dm_odm, p_sound_info->sound_idx, p_sound_info->sound_mode, p_sound_info->sound_bw); else - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Error value return from BeamformingStart_V2\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Error value return from BeamformingStart_V2\n", __func__)); - if ((pBeamInfo->beamformee_su_cnt != 0) || (pBeamInfo->beamformee_mu_cnt > 1)) { - if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) - ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, pSoundInfo->SoundPeriod); + if ((p_beam_info->beamformee_su_cnt != 0) || (p_beam_info->beamformee_mu_cnt > 1)) { + if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_set_timer(p_dm_odm, &p_beam_info->beamforming_timer, p_sound_info->sound_period); else { - u4Byte val = (pSoundInfo->SoundPeriod << 16) | HAL_TIMER_TXBF; - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_RESTART, (pu1Byte)(&val)); + u32 val = (p_sound_info->sound_period << 16) | HAL_TIMER_TXBF; + phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_RESTART, (u8 *)(&val)); } } } -VOID -Beamforming_SWTimerCallback( +void +beamforming_sw_timer_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PRT_TIMER pTimer -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - void *FunctionContext + struct timer_list *p_timer +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + void *function_context #endif - ) +) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = (PADAPTER)pTimer->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - Beamforming_TimerCallback(pDM_Odm); -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)FunctionContext; - PADAPTER Adapter = pDM_Odm->Adapter; + struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + beamforming_timer_callback(p_dm_odm); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)function_context; + struct _ADAPTER *adapter = p_dm_odm->adapter; - if (Adapter->net_closed == TRUE) + if (adapter->net_closed == true) return; - rtw_run_in_thread_cmd(Adapter, Beamforming_TimerCallback, Adapter); + rtw_run_in_thread_cmd(adapter, beamforming_timer_callback, adapter); #endif - + } -VOID -phydm_Beamforming_Init( - IN PVOID pDM_VOID - ) +void +phydm_beamforming_init( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMING_OID_INFO pBeamOidInfo = &(pBeamInfo->BeamformingOidInfo); - - pBeamOidInfo->SoundOidMode = SOUNDING_STOP_OID_TIMER; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Mode (%d)\n", __func__, pBeamOidInfo->SoundOidMode)); - - pBeamInfo->beamformee_su_cnt = 0; - pBeamInfo->beamformer_su_cnt = 0; - pBeamInfo->beamformee_mu_cnt = 0; - pBeamInfo->beamformer_mu_cnt = 0; - pBeamInfo->beamformee_mu_reg_maping = 0; - pBeamInfo->mu_ap_index = 0; - pBeamInfo->is_mu_sounding = FALSE; - pBeamInfo->FirstMUBFeeIndex = 0xFF; - pBeamInfo->applyVmatrix = TRUE; - pBeamInfo->snding3SS = FALSE; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pBeamInfo->SourceAdapter = pDM_Odm->Adapter; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_OID_INFO *p_beam_oid_info = &(p_beam_info->beamforming_oid_info); + + p_beam_oid_info->sound_oid_mode = SOUNDING_STOP_OID_TIMER; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s mode (%d)\n", __func__, p_beam_oid_info->sound_oid_mode)); + + p_beam_info->beamformee_su_cnt = 0; + p_beam_info->beamformer_su_cnt = 0; + p_beam_info->beamformee_mu_cnt = 0; + p_beam_info->beamformer_mu_cnt = 0; + p_beam_info->beamformee_mu_reg_maping = 0; + p_beam_info->mu_ap_index = 0; + p_beam_info->is_mu_sounding = false; + p_beam_info->first_mu_bfee_index = 0xFF; + p_beam_info->apply_v_matrix = true; + p_beam_info->snding3ss = false; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + p_beam_info->source_adapter = p_dm_odm->adapter; #endif - halComTxbf_beamformInit(pDM_Odm); -} + hal_com_txbf_beamform_init(p_dm_odm); +} -BOOLEAN -phydm_actingDetermine( - IN PVOID pDM_VOID, - IN PHYDM_ACTING_TYPE type - ) +boolean +phydm_acting_determine( + void *p_dm_void, + enum phydm_acting_type type +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN ret = FALSE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + boolean ret = false; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->BeamformingInfo.SourceAdapter; + struct _ADAPTER *adapter = p_dm_odm->beamforming_info.source_adapter; #else - PADAPTER Adapter = pDM_Odm->Adapter; + struct _ADAPTER *adapter = p_dm_odm->adapter; #endif #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (type == PhyDM_ACTING_AS_AP) - ret = ACTING_AS_AP(Adapter); - else if (type == PhyDM_ACTING_AS_IBSS) - ret = ACTING_AS_IBSS(Adapter); + if (type == phydm_acting_as_ap) + ret = ACTING_AS_AP(adapter); + else if (type == phydm_acting_as_ibss) + ret = ACTING_AS_IBSS(adapter); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - if (type == PhyDM_ACTING_AS_AP) + if (type == phydm_acting_as_ap) ret = check_fwstate(pmlmepriv, WIFI_AP_STATE); - else if (type == PhyDM_ACTING_AS_IBSS) + else if (type == phydm_acting_as_ibss) ret = check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); #endif @@ -1768,191 +1700,189 @@ phydm_actingDetermine( } -VOID -Beamforming_Enter( - IN PVOID pDM_VOID, - IN u2Byte staIdx +void +beamforming_enter( + void *p_dm_void, + u16 sta_idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte BFerBFeeIdx = 0xff; - - if (Beamforming_InitEntry(pDM_Odm, staIdx, &BFerBFeeIdx)) - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_ENTER, (pu1Byte)&BFerBFeeIdx); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 bfer_bfee_idx = 0xff; + + if (beamforming_init_entry(p_dm_odm, sta_idx, &bfer_bfee_idx)) + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_ENTER, (u8 *)&bfer_bfee_idx); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!\n", __func__)); } -VOID -Beamforming_Leave( - IN PVOID pDM_VOID, - pu1Byte RA - ) +void +beamforming_leave( + void *p_dm_void, + u8 *RA +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; if (RA != NULL) { - Beamforming_DeInitEntry(pDM_Odm, RA); - phydm_Beamforming_Notify(pDM_Odm); + beamforming_deinit_entry(p_dm_odm, RA); + phydm_beamforming_notify(p_dm_odm); } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!!\n", __func__)); } #if 0 -//Nobody calls this function -VOID -phydm_Beamforming_SetTxBFen( - IN PVOID pDM_VOID, - u1Byte MacId, - BOOLEAN bTxBF - ) +/* Nobody calls this function */ +void +phydm_beamforming_set_txbf_en( + void *p_dm_void, + u8 mac_id, + boolean is_txbf +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx = 0; - PRT_BEAMFORMEE_ENTRY pEntry; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *p_entry; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - pEntry = phydm_Beamforming_GetEntryByMacId(pDM_Odm, MacId, &Idx); + p_entry = phydm_beamforming_get_entry_by_mac_id(p_dm_odm, mac_id, &idx); - if(pEntry == NULL) + if (p_entry == NULL) return; else - pEntry->bTxBF = bTxBF; + p_entry->is_txbf = is_txbf; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s MacId %d TxBF %d\n", __func__, pEntry->MacId, pEntry->bTxBF)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s mac_id %d TxBF %d\n", __func__, p_entry->mac_id, p_entry->is_txbf)); - phydm_Beamforming_Notify(pDM_Odm); + phydm_beamforming_notify(p_dm_odm); } #endif -BEAMFORMING_CAP -phydm_Beamforming_GetBeamCap( - IN PVOID pDM_VOID, - IN PRT_BEAMFORMING_INFO pBeamInfo - ) +enum beamforming_cap +phydm_beamforming_get_beam_cap( + void *p_dm_void, + struct _RT_BEAMFORMING_INFO *p_beam_info +) { - u1Byte i; - BOOLEAN bSelfBeamformer = FALSE; - BOOLEAN bSelfBeamformee = FALSE; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - RT_BEAMFORMER_ENTRY BeamformerEntry; - BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u8 i; + boolean is_self_beamformer = false; + boolean is_self_beamformee = false; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - BeamformeeEntry = pBeamInfo->BeamformeeEntry[i]; + beamformee_entry = p_beam_info->beamformee_entry[i]; - if (BeamformeeEntry.bUsed) { - bSelfBeamformer = TRUE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFee entry %d bUsed=TRUE\n", __func__, i)); + if (beamformee_entry.is_used) { + is_self_beamformer = true; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFee entry %d is_used=true\n", __func__, i)); break; } } for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { - BeamformerEntry = pBeamInfo->BeamformerEntry[i]; + beamformer_entry = p_beam_info->beamformer_entry[i]; - if (BeamformerEntry.bUsed) { - bSelfBeamformee = TRUE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: BFer entry %d bUsed=TRUE\n", __func__, i)); + if (beamformer_entry.is_used) { + is_self_beamformee = true; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: BFer entry %d is_used=true\n", __func__, i)); break; } } - if (bSelfBeamformer) - BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMER_CAP); - if (bSelfBeamformee) - BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMEE_CAP); + if (is_self_beamformer) + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP); + if (is_self_beamformee) + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP); - return BeamformCap; + return beamform_cap; } -BOOLEAN -BeamformingControl_V1( - IN PVOID pDM_VOID, - pu1Byte RA, - u1Byte AID, - u1Byte Mode, +boolean +beamforming_control_v1( + void *p_dm_void, + u8 *RA, + u8 AID, + u8 mode, CHANNEL_WIDTH BW, - u1Byte Rate - ) + u8 rate +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN ret = TRUE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + boolean ret = true; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("AID (%d), Mode (%d), BW (%d)\n", AID, Mode, BW)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("AID (%d), mode (%d), BW (%d)\n", AID, mode, BW)); - switch (Mode) { + switch (mode) { case 0: - ret = BeamformingStart_V1(pDM_Odm, RA, 0, BW, Rate); - break; + ret = beamforming_start_v1(p_dm_odm, RA, 0, BW, rate); + break; case 1: - ret = BeamformingStart_V1(pDM_Odm, RA, 1, BW, Rate); - break; + ret = beamforming_start_v1(p_dm_odm, RA, 1, BW, rate); + break; case 2: - phydm_Beamforming_NDPARate(pDM_Odm, BW, Rate); - ret = Beamforming_SendVHTNDPAPacket(pDM_Odm, RA, AID, BW, NORMAL_QUEUE); - break; + phydm_beamforming_ndpa_rate(p_dm_odm, BW, rate); + ret = beamforming_send_vht_ndpa_packet(p_dm_odm, RA, AID, BW, NORMAL_QUEUE); + break; case 3: - phydm_Beamforming_NDPARate(pDM_Odm, BW, Rate); - ret = Beamforming_SendHTNDPAPacket(pDM_Odm, RA, BW, NORMAL_QUEUE); - break; + phydm_beamforming_ndpa_rate(p_dm_odm, BW, rate); + ret = beamforming_send_ht_ndpa_packet(p_dm_odm, RA, BW, NORMAL_QUEUE); + break; } return ret; } /*Only OID uses this function*/ -BOOLEAN -phydm_BeamformingControl_V2( - IN PVOID pDM_VOID, - u1Byte Idx, - u1Byte Mode, +boolean +phydm_beamforming_control_v2( + void *p_dm_void, + u8 idx, + u8 mode, CHANNEL_WIDTH BW, - u2Byte Period - ) + u16 period +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMING_OID_INFO pBeamOidInfo = &(pBeamInfo->BeamformingOidInfo); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_OID_INFO *p_beam_oid_info = &(p_beam_info->beamforming_oid_info); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Idx (%d), Mode (%d), BW (%d), Period (%d)\n", Idx, Mode, BW, Period)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("idx (%d), mode (%d), BW (%d), period (%d)\n", idx, mode, BW, period)); - pBeamOidInfo->SoundOidIdx = Idx; - pBeamOidInfo->SoundOidMode = (SOUNDING_MODE) Mode; - pBeamOidInfo->SoundOidBW = BW; - pBeamOidInfo->SoundOidPeriod = Period; + p_beam_oid_info->sound_oid_idx = idx; + p_beam_oid_info->sound_oid_mode = (enum sounding_mode) mode; + p_beam_oid_info->sound_oid_bw = BW; + p_beam_oid_info->sound_oid_period = period; - phydm_Beamforming_Notify(pDM_Odm); + phydm_beamforming_notify(p_dm_odm); - return TRUE; + return true; } -VOID -phydm_Beamforming_Watchdog( - IN PVOID pDM_VOID +void +phydm_beamforming_watchdog( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("%s Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("%s Start!\n", __func__)); - if (pBeamInfo->beamformee_su_cnt == 0) + if (p_beam_info->beamformee_su_cnt == 0) return; - Beamforming_DymPeriod(pDM_Odm,0); - phydm_Beamforming_DymNDPARate(pDM_Odm); - + beamforming_dym_period(p_dm_odm, 0); } diff --git a/hal/phydm/phydm_beamforming.h b/hal/phydm/phydm_beamforming.h index 9f3e924..2d3479b 100644 --- a/hal/phydm/phydm_beamforming.h +++ b/hal/phydm/phydm_beamforming.h @@ -1,8 +1,22 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __INC_PHYDM_BEAMFORMING_H #define __INC_PHYDM_BEAMFORMING_H #ifndef BEAMFORMING_SUPPORT -#define BEAMFORMING_SUPPORT 0 + #define BEAMFORMING_SUPPORT 0 #endif /*Beamforming Related*/ @@ -15,37 +29,44 @@ #if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#define eq_mac_addr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) +#define cp_mac_addr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5]) + +#endif + #define MAX_BEAMFORMEE_SU 2 #define MAX_BEAMFORMER_SU 2 #if (RTL8822B_SUPPORT == 1) -#define MAX_BEAMFORMEE_MU 6 -#define MAX_BEAMFORMER_MU 1 + #define MAX_BEAMFORMEE_MU 6 + #define MAX_BEAMFORMER_MU 1 #else -#define MAX_BEAMFORMEE_MU 0 -#define MAX_BEAMFORMER_MU 0 + #define MAX_BEAMFORMEE_MU 0 + #define MAX_BEAMFORMER_MU 0 #endif #define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU) #define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU) #if (DM_ODM_SUPPORT_TYPE == ODM_CE) -/*for different naming between WIN and CE*/ -#define BEACON_QUEUE BCN_QUEUE_INX -#define NORMAL_QUEUE MGT_QUEUE_INX -#define RT_DISABLE_FUNC RTW_DISABLE_FUNC -#define RT_ENABLE_FUNC RTW_ENABLE_FUNC + /*for different naming between WIN and CE*/ + #define BEACON_QUEUE BCN_QUEUE_INX + #define NORMAL_QUEUE MGT_QUEUE_INX + #define RT_DISABLE_FUNC RTW_DISABLE_FUNC + #define RT_ENABLE_FUNC RTW_ENABLE_FUNC #endif -typedef enum _BEAMFORMING_ENTRY_STATE { - BEAMFORMING_ENTRY_STATE_UNINITIALIZE, - BEAMFORMING_ENTRY_STATE_INITIALIZEING, - BEAMFORMING_ENTRY_STATE_INITIALIZED, - BEAMFORMING_ENTRY_STATE_PROGRESSING, - BEAMFORMING_ENTRY_STATE_PROGRESSED -} BEAMFORMING_ENTRY_STATE, *PBEAMFORMING_ENTRY_STATE; +enum beamforming_entry_state { + BEAMFORMING_ENTRY_STATE_UNINITIALIZE, + BEAMFORMING_ENTRY_STATE_INITIALIZEING, + BEAMFORMING_ENTRY_STATE_INITIALIZED, + BEAMFORMING_ENTRY_STATE_PROGRESSING, + BEAMFORMING_ENTRY_STATE_PROGRESSED +}; -typedef enum _BEAMFORMING_NOTIFY_STATE { +enum beamforming_notify_state { BEAMFORMING_NOTIFY_NONE, BEAMFORMING_NOTIFY_ADD, BEAMFORMING_NOTIFY_DELETE, @@ -54,325 +75,320 @@ typedef enum _BEAMFORMING_NOTIFY_STATE { BEAMFORMEE_NOTIFY_ADD_MU, BEAMFORMEE_NOTIFY_DELETE_MU, BEAMFORMING_NOTIFY_RESET -} BEAMFORMING_NOTIFY_STATE, *PBEAMFORMING_NOTIFY_STATE; +}; -typedef enum _BEAMFORMING_CAP { +enum beamforming_cap { BEAMFORMING_CAP_NONE = 0x0, - BEAMFORMER_CAP_HT_EXPLICIT = BIT1, - BEAMFORMEE_CAP_HT_EXPLICIT = BIT2, - BEAMFORMER_CAP_VHT_SU = BIT5, /* Self has er Cap, because Reg er & peer ee */ - BEAMFORMEE_CAP_VHT_SU = BIT6, /* Self has ee Cap, because Reg ee & peer er */ - BEAMFORMER_CAP_VHT_MU = BIT7, /* Self has er Cap, because Reg er & peer ee */ - BEAMFORMEE_CAP_VHT_MU = BIT8, /* Self has ee Cap, because Reg ee & peer er */ - BEAMFORMER_CAP = BIT9, - BEAMFORMEE_CAP = BIT10, -}BEAMFORMING_CAP, *PBEAMFORMING_CAP; - - -typedef enum _SOUNDING_MODE { + BEAMFORMER_CAP_HT_EXPLICIT = BIT(1), + BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2), + BEAMFORMER_CAP_VHT_SU = BIT(5), /* Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_SU = BIT(6), /* Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP_VHT_MU = BIT(7), /* Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_MU = BIT(8), /* Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP = BIT(9), + BEAMFORMEE_CAP = BIT(10), +}; + + +enum sounding_mode { SOUNDING_SW_VHT_TIMER = 0x0, - SOUNDING_SW_HT_TIMER = 0x1, - SOUNDING_STOP_All_TIMER = 0x2, - SOUNDING_HW_VHT_TIMER = 0x3, + SOUNDING_SW_HT_TIMER = 0x1, + sounding_stop_all_timer = 0x2, + SOUNDING_HW_VHT_TIMER = 0x3, SOUNDING_HW_HT_TIMER = 0x4, - SOUNDING_STOP_OID_TIMER = 0x5, + SOUNDING_STOP_OID_TIMER = 0x5, SOUNDING_AUTO_VHT_TIMER = 0x6, SOUNDING_AUTO_HT_TIMER = 0x7, SOUNDING_FW_VHT_TIMER = 0x8, SOUNDING_FW_HT_TIMER = 0x9, -}SOUNDING_MODE, *PSOUNDING_MODE; - -typedef struct _RT_BEAMFORM_STAINFO { - pu1Byte RA; - u2Byte AID; - u2Byte MacID; - u1Byte MyMacAddr[6]; - WIRELESS_MODE WirelessMode; - CHANNEL_WIDTH BW; - BEAMFORMING_CAP BeamformCap; - u1Byte HtBeamformCap; - u2Byte VhtBeamformCap; - u1Byte CurBeamform; - u2Byte CurBeamformVHT; -} RT_BEAMFORM_STAINFO, *PRT_BEAMFORM_STAINFO; - - -typedef struct _RT_BEAMFORMEE_ENTRY { - BOOLEAN bUsed; - BOOLEAN bTxBF; - BOOLEAN bSound; - u2Byte AID; /*Used to construct AID field of NDPA packet.*/ - u2Byte MacId; /*Used to Set Reg42C in IBSS mode. */ - u2Byte P_AID; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ - u2Byte G_ID; /*Used to fill Tx DESC*/ - u1Byte MyMacAddr[6]; - u1Byte MacAddr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/ - CHANNEL_WIDTH SoundBW; /*Sounding BandWidth*/ - u2Byte SoundPeriod; - BEAMFORMING_CAP BeamformEntryCap; - BEAMFORMING_ENTRY_STATE BeamformEntryState; - BOOLEAN bBeamformingInProgress; - /*u1Byte LogSeq; // Move to _RT_BEAMFORMER_ENTRY*/ - /*u2Byte LogRetryCnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/ - /*u2Byte LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/ - u2Byte LogStatusFailCnt:5; // 0~21 - u2Byte DefaultCSICnt:5; // 0~21 - u1Byte CSIMatrix[327]; - u2Byte CSIMatrixLen; - u1Byte NumofSoundingDim; - u1Byte CompSteeringNumofBFer; - u1Byte su_reg_index; +}; + +struct _RT_BEAMFORM_STAINFO { + u8 *ra; + u16 aid; + u16 mac_id; + u8 my_mac_addr[6]; + WIRELESS_MODE wireless_mode; + CHANNEL_WIDTH bw; + enum beamforming_cap beamform_cap; + u8 ht_beamform_cap; + u16 vht_beamform_cap; + u8 cur_beamform; + u16 cur_beamform_vht; +}; + + +struct _RT_BEAMFORMEE_ENTRY { + boolean is_used; + boolean is_txbf; + boolean is_sound; + u16 aid; /*Used to construct AID field of NDPA packet.*/ + u16 mac_id; /*Used to Set Reg42C in IBSS mode. */ + u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ + u16 g_id; /*Used to fill Tx DESC*/ + u8 my_mac_addr[6]; + u8 mac_addr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/ + CHANNEL_WIDTH sound_bw; /*Sounding band_width*/ + u16 sound_period; + enum beamforming_cap beamform_entry_cap; + enum beamforming_entry_state beamform_entry_state; + boolean is_beamforming_in_progress; + /*u8 log_seq; // Move to _RT_BEAMFORMER_ENTRY*/ + /*u16 log_retry_cnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/ + /*u16 LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/ + u16 log_status_fail_cnt:5; /* 0~21 */ + u16 default_csi_cnt:5; /* 0~21 */ + u8 csi_matrix[327]; + u16 csi_matrix_len; + u8 num_of_sounding_dim; + u8 comp_steering_num_of_bfer; + u8 su_reg_index; /*For MU-MIMO*/ - BOOLEAN is_mu_sta; - u1Byte mu_reg_index; - u1Byte gid_valid[8]; - u1Byte user_position[16]; -} RT_BEAMFORMEE_ENTRY, *PRT_BEAMFORMEE_ENTRY; - -typedef struct _RT_BEAMFORMER_ENTRY { - BOOLEAN bUsed; + boolean is_mu_sta; + u8 mu_reg_index; + u8 gid_valid[8]; + u8 user_position[16]; +}; + +struct _RT_BEAMFORMER_ENTRY { + boolean is_used; /*P_AID of BFer entry is probably not used*/ - u2Byte P_AID; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ - u2Byte G_ID; - u1Byte MyMacAddr[6]; - u1Byte MacAddr[6]; - BEAMFORMING_CAP BeamformEntryCap; - u1Byte NumofSoundingDim; - u1Byte ClockResetTimes; /*Modified by Jeffery @2015-04-10*/ - u1Byte PreLogSeq; /*Modified by Jeffery @2015-03-30*/ - u1Byte LogSeq; /*Modified by Jeffery @2014-10-29*/ - u2Byte LogRetryCnt:3; /*Modified by Jeffery @2014-10-29*/ - u2Byte LogSuccess:2; /*Modified by Jeffery @2014-10-29*/ - u1Byte su_reg_index; - /*For MU-MIMO*/ - BOOLEAN is_mu_ap; - u1Byte gid_valid[8]; - u1Byte user_position[16]; - u2Byte AID; -} RT_BEAMFORMER_ENTRY, *PRT_BEAMFORMER_ENTRY; - -typedef struct _RT_SOUNDING_INFO { - u1Byte SoundIdx; - CHANNEL_WIDTH SoundBW; - SOUNDING_MODE SoundMode; - u2Byte SoundPeriod; -} RT_SOUNDING_INFO, *PRT_SOUNDING_INFO; - - - -typedef struct _RT_BEAMFORMING_OID_INFO { - u1Byte SoundOidIdx; - CHANNEL_WIDTH SoundOidBW; - SOUNDING_MODE SoundOidMode; - u2Byte SoundOidPeriod; -} RT_BEAMFORMING_OID_INFO, *PRT_BEAMFORMING_OID_INFO; - - -typedef struct _RT_BEAMFORMING_INFO { - BEAMFORMING_CAP BeamformCap; - RT_BEAMFORMEE_ENTRY BeamformeeEntry[BEAMFORMEE_ENTRY_NUM]; - RT_BEAMFORMER_ENTRY BeamformerEntry[BEAMFORMER_ENTRY_NUM]; - RT_BEAMFORM_STAINFO BeamformSTAinfo; - u1Byte BeamformeeCurIdx; - RT_TIMER BeamformingTimer; - RT_TIMER mu_timer; - RT_SOUNDING_INFO SoundingInfo; - RT_BEAMFORMING_OID_INFO BeamformingOidInfo; - HAL_TXBF_INFO TxbfInfo; - u1Byte SoundingSequence; - u1Byte beamformee_su_cnt; - u1Byte beamformer_su_cnt; - u4Byte beamformee_su_reg_maping; - u4Byte beamformer_su_reg_maping; + u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ + u16 g_id; + u8 my_mac_addr[6]; + u8 mac_addr[6]; + enum beamforming_cap beamform_entry_cap; + u8 num_of_sounding_dim; + u8 clock_reset_times; /*Modified by Jeffery @2015-04-10*/ + u8 pre_log_seq; /*Modified by Jeffery @2015-03-30*/ + u8 log_seq; /*Modified by Jeffery @2014-10-29*/ + u16 log_retry_cnt:3; /*Modified by Jeffery @2014-10-29*/ + u16 log_success:2; /*Modified by Jeffery @2014-10-29*/ + u8 su_reg_index; + /*For MU-MIMO*/ + boolean is_mu_ap; + u8 gid_valid[8]; + u8 user_position[16]; + u16 aid; +}; + +struct _RT_SOUNDING_INFO { + u8 sound_idx; + CHANNEL_WIDTH sound_bw; + enum sounding_mode sound_mode; + u16 sound_period; +}; + + + +struct _RT_BEAMFORMING_OID_INFO { + u8 sound_oid_idx; + CHANNEL_WIDTH sound_oid_bw; + enum sounding_mode sound_oid_mode; + u16 sound_oid_period; +}; + + +struct _RT_BEAMFORMING_INFO { + enum beamforming_cap beamform_cap; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM]; + struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM]; + struct _RT_BEAMFORM_STAINFO beamform_sta_info; + u8 beamformee_cur_idx; + #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + struct legacy_timer_emu beamforming_timer; + struct legacy_timer_emu mu_timer; + #else + struct timer_list beamforming_timer; + struct timer_list mu_timer;i + #endif + struct _RT_SOUNDING_INFO sounding_info; + struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info; + struct _HAL_TXBF_INFO txbf_info; + u8 sounding_sequence; + u8 beamformee_su_cnt; + u8 beamformer_su_cnt; + u32 beamformee_su_reg_maping; + u32 beamformer_su_reg_maping; /*For MU-MINO*/ - u1Byte beamformee_mu_cnt; - u1Byte beamformer_mu_cnt; - u4Byte beamformee_mu_reg_maping; - u1Byte mu_ap_index; - BOOLEAN is_mu_sounding; - u1Byte FirstMUBFeeIndex; - BOOLEAN is_mu_sounding_in_progress; - BOOLEAN dbg_disable_mu_tx; - BOOLEAN applyVmatrix; - BOOLEAN snding3SS; + u8 beamformee_mu_cnt; + u8 beamformer_mu_cnt; + u32 beamformee_mu_reg_maping; + u8 mu_ap_index; + boolean is_mu_sounding; + u8 first_mu_bfee_index; + boolean is_mu_sounding_in_progress; + boolean dbg_disable_mu_tx; + boolean apply_v_matrix; + boolean snding3ss; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER SourceAdapter; + struct _ADAPTER *source_adapter; #endif /* Control register */ - u4Byte RegMUTxCtrl; /* For USB/SDIO interfaces aync I/O */ -} RT_BEAMFORMING_INFO, *PRT_BEAMFORMING_INFO; - - -typedef struct _RT_NDPA_STA_INFO { - u2Byte AID:12; - u2Byte FeedbackType:1; - u2Byte NcIndex:3; -} RT_NDPA_STA_INFO, *PRT_NDPA_STA_INFO; - -typedef enum _PHYDM_ACTING_TYPE { - PhyDM_ACTING_AS_IBSS = 0, - PhyDM_ACTING_AS_AP = 1 -} PHYDM_ACTING_TYPE; - - -BEAMFORMING_CAP -phydm_Beamforming_GetEntryBeamCapByMacId( - IN PVOID pDM_VOID, - IN u1Byte MacId - ); - -PRT_BEAMFORMEE_ENTRY -phydm_Beamforming_GetBFeeEntryByAddr( - IN PVOID pDM_VOID, - IN pu1Byte RA, - OUT pu1Byte Idx - ); - -PRT_BEAMFORMER_ENTRY -phydm_Beamforming_GetBFerEntryByAddr( - IN PVOID pDM_VOID, - IN pu1Byte TA, - OUT pu1Byte Idx - ); - -u1Byte -Beamforming_GetHTNDPTxRate( - IN PVOID pDM_VOID, - u1Byte CompSteeringNumofBFer + u32 reg_mu_tx_ctrl; /* For USB/SDIO interfaces aync I/O */ + u8 tx_bf_data_rate; + u8 last_usb_hub; +}; + + +struct _RT_NDPA_STA_INFO { + u16 aid:12; + u16 feedback_type:1; + u16 nc_index:3; +}; + +enum phydm_acting_type { + phydm_acting_as_ibss = 0, + phydm_acting_as_ap = 1 +}; + + +enum beamforming_cap +phydm_beamforming_get_entry_beam_cap_by_mac_id( + void *p_dm_void, + u8 mac_id +); + +struct _RT_BEAMFORMEE_ENTRY * +phydm_beamforming_get_bfee_entry_by_addr( + void *p_dm_void, + u8 *RA, + u8 *idx +); + +struct _RT_BEAMFORMER_ENTRY * +phydm_beamforming_get_bfer_entry_by_addr( + void *p_dm_void, + u8 *TA, + u8 *idx +); + +void +phydm_beamforming_notify( + void *p_dm_void +); + +boolean +phydm_acting_determine( + void *p_dm_void, + enum phydm_acting_type type ); -u1Byte -Beamforming_GetVHTNDPTxRate( - IN PVOID pDM_VOID, - u1Byte CompSteeringNumofBFer +void +beamforming_enter( + void *p_dm_void, + u16 sta_idx ); -VOID -phydm_Beamforming_Notify( - IN PVOID pDM_VOID - ); - -BOOLEAN -phydm_actingDetermine( - IN PVOID pDM_VOID, - IN PHYDM_ACTING_TYPE type - ); - -VOID -Beamforming_Enter( - IN PVOID pDM_VOID, - IN u2Byte staIdx - ); - -VOID -Beamforming_Leave( - IN PVOID pDM_VOID, - pu1Byte RA - ); - -BOOLEAN -BeamformingStart_FW( - IN PVOID pDM_VOID, - u1Byte Idx - ); - -VOID -Beamforming_CheckSoundingSuccess( - IN PVOID pDM_VOID, - BOOLEAN Status +void +beamforming_leave( + void *p_dm_void, + u8 *RA ); -VOID -phydm_Beamforming_End_SW( - IN PVOID pDM_VOID, - BOOLEAN Status - ); +boolean +beamforming_start_fw( + void *p_dm_void, + u8 idx +); + +void +beamforming_check_sounding_success( + void *p_dm_void, + boolean status +); + +void +phydm_beamforming_end_sw( + void *p_dm_void, + boolean status +); -VOID -Beamforming_TimerCallback( - IN PVOID pDM_VOID - ); +void +beamforming_timer_callback( + void *p_dm_void +); -VOID -phydm_Beamforming_Init( - IN PVOID pDM_VOID - ); +void +phydm_beamforming_init( + void *p_dm_void +); -BEAMFORMING_CAP -phydm_Beamforming_GetBeamCap( - IN PVOID pDM_VOID, - IN PRT_BEAMFORMING_INFO pBeamInfo - ); +enum beamforming_cap +phydm_beamforming_get_beam_cap( + void *p_dm_void, + struct _RT_BEAMFORMING_INFO *p_beam_info +); -BOOLEAN -BeamformingControl_V1( - IN PVOID pDM_VOID, - pu1Byte RA, - u1Byte AID, - u1Byte Mode, +boolean +beamforming_control_v1( + void *p_dm_void, + u8 *RA, + u8 AID, + u8 mode, CHANNEL_WIDTH BW, - u1Byte Rate - ); + u8 rate +); -BOOLEAN -phydm_BeamformingControl_V2( - IN PVOID pDM_VOID, - u1Byte Idx, - u1Byte Mode, +boolean +phydm_beamforming_control_v2( + void *p_dm_void, + u8 idx, + u8 mode, CHANNEL_WIDTH BW, - u2Byte Period - ); + u16 period +); -VOID -phydm_Beamforming_Watchdog( - IN PVOID pDM_VOID - ); +void +phydm_beamforming_watchdog( + void *p_dm_void +); -VOID -Beamforming_SWTimerCallback( +void +beamforming_sw_timer_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PRT_TIMER pTimer -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - void *FunctionContext + struct timer_list *p_timer +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + void *function_context #endif - ); - -BOOLEAN -Beamforming_SendHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW, - IN u1Byte QIdx - ); - - -BOOLEAN -Beamforming_SendVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW, - IN u1Byte QIdx - ); +); + +boolean +beamforming_send_ht_ndpa_packet( + void *p_dm_void, + u8 *RA, + CHANNEL_WIDTH BW, + u8 q_idx +); + + +boolean +beamforming_send_vht_ndpa_packet( + void *p_dm_void, + u8 *RA, + u16 AID, + CHANNEL_WIDTH BW, + u8 q_idx +); #else -#define Beamforming_GidPAid(Adapter, pTcb) -#define phydm_actingDetermine(pDM_Odm, type) FALSE -#define Beamforming_Enter(pDM_Odm, staIdx) -#define Beamforming_Leave(pDM_Odm, RA) -#define Beamforming_End_FW(pDMOdm) -#define BeamformingControl_V1(pDM_Odm, RA, AID, Mode, BW, Rate) TRUE -#define BeamformingControl_V2(pDM_Odm, Idx, Mode, BW, Period) TRUE -#define phydm_Beamforming_End_SW(pDM_Odm, _Status) -#define Beamforming_TimerCallback(pDM_Odm) -#define phydm_Beamforming_Init(pDM_Odm) -#define phydm_BeamformingControl_V2(pDM_Odm, _Idx, _Mode, _BW, _Period) FALSE -#define Beamforming_Watchdog(pDM_Odm) -#define phydm_Beamforming_Watchdog(pDM_Odm) +#define beamforming_gid_paid(adapter, p_tcb) +#define phydm_acting_determine(p_dm_odm, type) false +#define beamforming_enter(p_dm_odm, sta_idx) +#define beamforming_leave(p_dm_odm, RA) +#define beamforming_end_fw(p_dm_odm) +#define beamforming_control_v1(p_dm_odm, RA, AID, mode, BW, rate) true +#define beamforming_control_v2(p_dm_odm, idx, mode, BW, period) true +#define phydm_beamforming_end_sw(p_dm_odm, _status) +#define beamforming_timer_callback(p_dm_odm) +#define phydm_beamforming_init(p_dm_odm) +#define phydm_beamforming_control_v2(p_dm_odm, _idx, _mode, _BW, _period) false +#define beamforming_watchdog(p_dm_odm) +#define phydm_beamforming_watchdog(p_dm_odm) #endif diff --git a/hal/phydm/phydm_ccx.c b/hal/phydm/phydm_ccx.c index 9ee5fea..388a2a4 100644 --- a/hal/phydm/phydm_ccx.c +++ b/hal/phydm/phydm_ccx.c @@ -1,400 +1,512 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" /*Set NHM period, threshold, disable ignore cca or not, disable ignore txon or not*/ -VOID -phydm_NHMsetting( - IN PVOID pDM_VOID, - u1Byte NHMsetting +void +phydm_nhm_counter_statistics_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + /*PHY parameters initialize for n series*/ + odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11N + 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ + odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/ + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/ + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_FPGA0_IQK_11N, MASKBYTE0, 0xff); /*0xe28[7:0]=0xff th_8*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10) | BIT(9) | BIT(8), 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(7), 0x1); /*0xc0c[7]=1 max power among all RX ants*/ + } +#if (RTL8195A_SUPPORT == 0) + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + /*PHY parameters initialize for ac series*/ + odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ + odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/ + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/ + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, 0xff); /*0x9a0[7:0]=0xff th_8*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8) | BIT(9) | BIT(10), 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_9E8_11AC, BIT(0), 0x1); /*0x9e8[7]=1 max power among all RX ants*/ + + } +#endif +} + +void +phydm_nhm_counter_statistics( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) + return; + + /*Get NHM report*/ + phydm_get_nhm_counter_statistics(p_dm_odm); + + /*Reset NHM counter*/ + phydm_nhm_counter_statistics_reset(p_dm_odm); +} + +void +phydm_get_nhm_counter_statistics( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 value32 = 0; +#if (RTL8195A_SUPPORT == 0) + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_CNT_11AC, MASKDWORD); + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) +#endif + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_CNT_11N, MASKDWORD); + + p_dm_odm->nhm_cnt_0 = (u8)(value32 & MASKBYTE0); + p_dm_odm->nhm_cnt_1 = (u8)((value32 & MASKBYTE1) >> 8); + +} + +void +phydm_nhm_counter_statistics_reset( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1); + } +#if (RTL8195A_SUPPORT == 0) + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1); + } + +#endif + +} + +boolean +phydm_cal_nhm_cnt( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u16 base = 0; + + base = p_dm_odm->nhm_cnt_0 + p_dm_odm->nhm_cnt_1; + + if (base != 0) { + p_dm_odm->nhm_cnt_0 = ((p_dm_odm->nhm_cnt_0) << 8) / base; + p_dm_odm->nhm_cnt_1 = ((p_dm_odm->nhm_cnt_1) << 8) / base; + } + if ((p_dm_odm->nhm_cnt_0 - p_dm_odm->nhm_cnt_1) >= 100) + return true; /*clean environment*/ + else + return false; /*noisy environment*/ +} + +void +phydm_nhm_setting( + void *p_dm_void, + u8 nhm_setting ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + if (nhm_setting == SET_NHM_SETTING) { - if (NHMsetting == SET_NHM_SETTING){ - /*Set inexclude_cca, inexclude_txon*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT9, CCX_INFO->NHM_inexclude_cca); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT10, CCX_INFO->NHM_inexclude_txon); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->nhm_inexclude_cca); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->nhm_inexclude_txon); /*Set NHM period*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskHWord, CCX_INFO->NHM_period); + odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->NHM_period); /*Set NHM threshold*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0, CCX_INFO->NHM_th[0]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1, CCX_INFO->NHM_th[1]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2, CCX_INFO->NHM_th[2]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3, CCX_INFO->NHM_th[3]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0, CCX_INFO->NHM_th[4]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1, CCX_INFO->NHM_th[5]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2, CCX_INFO->NHM_th[6]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3, CCX_INFO->NHM_th[7]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, CCX_INFO->NHM_th[8]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2, CCX_INFO->NHM_th[9]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3, CCX_INFO->NHM_th[10]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->NHM_th[0]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->NHM_th[1]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->NHM_th[2]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->NHM_th[3]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->NHM_th[4]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->NHM_th[5]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->NHM_th[6]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->NHM_th[7]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->NHM_th[8]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->NHM_th[9]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->NHM_th[10]); /*CCX EN*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8, CCX_EN); - - } - else if (NHMsetting == STORE_NHM_SETTING) { + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8), CCX_EN); + + } else if (nhm_setting == STORE_NHM_SETTING) { /*Store pervious disable_ignore_cca, disable_ignore_txon*/ - CCX_INFO->NHM_inexclude_cca_restore = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT9); - CCX_INFO->NHM_inexclude_txon_restore = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT10); + ccx_info->NHM_inexclude_cca_restore = (enum nhm_inexclude_cca)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9)); + ccx_info->NHM_inexclude_txon_restore = (enum nhm_inexclude_txon)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10)); /*Store pervious NHM period*/ - CCX_INFO->NHM_period_restore = (u2Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskHWord); + ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD); /*Store NHM threshold*/ - CCX_INFO->NHM_th_restore[0] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0); - CCX_INFO->NHM_th_restore[1] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1); - CCX_INFO->NHM_th_restore[2] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2); - CCX_INFO->NHM_th_restore[3] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3); - CCX_INFO->NHM_th_restore[4] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0); - CCX_INFO->NHM_th_restore[5] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1); - CCX_INFO->NHM_th_restore[6] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2); - CCX_INFO->NHM_th_restore[7] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3); - CCX_INFO->NHM_th_restore[8] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0); - CCX_INFO->NHM_th_restore[9] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2); - CCX_INFO->NHM_th_restore[10] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3); - } - else if (NHMsetting == RESTORE_NHM_SETTING) { + ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0); + ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1); + ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2); + ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3); + ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0); + ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1); + ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2); + ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3); + ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0); + ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2); + ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3); + } else if (nhm_setting == RESTORE_NHM_SETTING) { /*Set disable_ignore_cca, disable_ignore_txon*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT9, CCX_INFO->NHM_inexclude_cca_restore); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT10, CCX_INFO->NHM_inexclude_txon_restore); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->NHM_inexclude_cca_restore); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->NHM_inexclude_txon_restore); /*Set NHM period*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskHWord, CCX_INFO->NHM_period); + odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->NHM_period); /*Set NHM threshold*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte0, CCX_INFO->NHM_th_restore[0]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte1, CCX_INFO->NHM_th_restore[1]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte2, CCX_INFO->NHM_th_restore[2]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, bMaskByte3, CCX_INFO->NHM_th_restore[3]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte0, CCX_INFO->NHM_th_restore[4]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte1, CCX_INFO->NHM_th_restore[5]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte2, CCX_INFO->NHM_th_restore[6]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, bMaskByte3, CCX_INFO->NHM_th_restore[7]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, CCX_INFO->NHM_th_restore[8]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte2, CCX_INFO->NHM_th_restore[9]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, bMaskByte3, CCX_INFO->NHM_th_restore[10]); - } - else + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->NHM_th_restore[0]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->NHM_th_restore[1]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->NHM_th_restore[2]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->NHM_th_restore[3]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->NHM_th_restore[4]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->NHM_th_restore[5]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->NHM_th_restore[6]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->NHM_th_restore[7]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->NHM_th_restore[8]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->NHM_th_restore[9]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->NHM_th_restore[10]); + } else return; } - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + if (nhm_setting == SET_NHM_SETTING) { - if (NHMsetting == SET_NHM_SETTING){ - /*Set disable_ignore_cca, disable_ignore_txon*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT9, CCX_INFO->NHM_inexclude_cca); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10, CCX_INFO->NHM_inexclude_txon); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->nhm_inexclude_cca); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->nhm_inexclude_txon); - /*Set NHM period*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskHWord, CCX_INFO->NHM_period); + /*Set NHM period*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->NHM_period); /*Set NHM threshold*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0, CCX_INFO->NHM_th[0]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1, CCX_INFO->NHM_th[1]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2, CCX_INFO->NHM_th[2]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3, CCX_INFO->NHM_th[3]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0, CCX_INFO->NHM_th[4]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1, CCX_INFO->NHM_th[5]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2, CCX_INFO->NHM_th[6]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3, CCX_INFO->NHM_th[7]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0, CCX_INFO->NHM_th[8]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2, CCX_INFO->NHM_th[9]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3, CCX_INFO->NHM_th[10]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->NHM_th[0]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->NHM_th[1]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->NHM_th[2]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->NHM_th[3]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->NHM_th[4]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->NHM_th[5]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->NHM_th[6]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->NHM_th[7]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->NHM_th[8]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->NHM_th[9]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->NHM_th[10]); /*CCX EN*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT8, CCX_EN); - } - else if (NHMsetting == STORE_NHM_SETTING) { + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(8), CCX_EN); + } else if (nhm_setting == STORE_NHM_SETTING) { /*Store pervious disable_ignore_cca, disable_ignore_txon*/ - CCX_INFO->NHM_inexclude_cca_restore = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT9); - CCX_INFO->NHM_inexclude_txon_restore= (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10); + ccx_info->NHM_inexclude_cca_restore = (enum nhm_inexclude_cca)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9)); + ccx_info->NHM_inexclude_txon_restore = (enum nhm_inexclude_txon)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10)); /*Store pervious NHM period*/ - CCX_INFO->NHM_period_restore= (u2Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskHWord); + ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD); /*Store NHM threshold*/ - CCX_INFO->NHM_th_restore[0] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0); - CCX_INFO->NHM_th_restore[1] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1); - CCX_INFO->NHM_th_restore[2] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2); - CCX_INFO->NHM_th_restore[3] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3); - CCX_INFO->NHM_th_restore[4] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0); - CCX_INFO->NHM_th_restore[5] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1); - CCX_INFO->NHM_th_restore[6] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2); - CCX_INFO->NHM_th_restore[7] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3); - CCX_INFO->NHM_th_restore[8] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0); - CCX_INFO->NHM_th_restore[9] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2); - CCX_INFO->NHM_th_restore[10] = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3); - - } - else if (NHMsetting == RESTORE_NHM_SETTING) { + ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0); + ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1); + ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2); + ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3); + ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0); + ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1); + ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2); + ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3); + ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0); + ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2); + ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3); + + } else if (nhm_setting == RESTORE_NHM_SETTING) { /*Set disable_ignore_cca, disable_ignore_txon*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT9, CCX_INFO->NHM_inexclude_cca_restore); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10, CCX_INFO->NHM_inexclude_txon_restore); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->NHM_inexclude_cca_restore); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->NHM_inexclude_txon_restore); /*Set NHM period*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskHWord, CCX_INFO->NHM_period_restore); + odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->NHM_period_restore); /*Set NHM threshold*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte0, CCX_INFO->NHM_th_restore[0]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte1, CCX_INFO->NHM_th_restore[1]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte2, CCX_INFO->NHM_th_restore[2]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, bMaskByte3, CCX_INFO->NHM_th_restore[3]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte0, CCX_INFO->NHM_th_restore[4]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte1, CCX_INFO->NHM_th_restore[5]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte2, CCX_INFO->NHM_th_restore[6]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, bMaskByte3, CCX_INFO->NHM_th_restore[7]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11N, bMaskByte0, CCX_INFO->NHM_th_restore[8]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte2, CCX_INFO->NHM_th_restore[9]); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, bMaskByte3, CCX_INFO->NHM_th_restore[10]); - } - else + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->NHM_th_restore[0]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->NHM_th_restore[1]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->NHM_th_restore[2]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->NHM_th_restore[3]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->NHM_th_restore[4]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->NHM_th_restore[5]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->NHM_th_restore[6]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->NHM_th_restore[7]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->NHM_th_restore[8]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->NHM_th_restore[9]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->NHM_th_restore[10]); + } else return; - + } } -VOID -phydm_NHMtrigger( - IN PVOID pDM_VOID +void +phydm_nhm_trigger( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { /*Trigger NHM*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1); - } - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1); + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { /*Trigger NHM*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1); } } -VOID -phydm_getNHMresult( - IN PVOID pDM_VOID +void +phydm_get_nhm_result( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT_11AC); - CCX_INFO->NHM_result[0] = (u1Byte)(value32 & bMaskByte0); - CCX_INFO->NHM_result[1] = (u1Byte)((value32 & bMaskByte1) >> 8); - CCX_INFO->NHM_result[2] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[3] = (u1Byte)((value32 & bMaskByte3) >> 24); - - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); - CCX_INFO->NHM_result[4] = (u1Byte)(value32 & bMaskByte0); - CCX_INFO->NHM_result[5] = (u1Byte)((value32 & bMaskByte1) >> 8); - CCX_INFO->NHM_result[6] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[7] = (u1Byte)((value32 & bMaskByte3) >> 24); - - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT11_TO_CNT8_11AC); - CCX_INFO->NHM_result[8] = (u1Byte)(value32 & bMaskByte0); - CCX_INFO->NHM_result[9] = (u1Byte)((value32 & bMaskByte1) >> 8); - CCX_INFO->NHM_result[10] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[11] = (u1Byte)((value32 & bMaskByte3) >> 24); - - /*Get NHM duration*/ - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC); - CCX_INFO->NHM_duration = (u2Byte)(value32 & bMaskLWord); - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 value32; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11AC); + ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0); + ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24); + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); + ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0); + ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24); + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT11_TO_CNT8_11AC); + ccx_info->NHM_result[8] = (u8)(value32 & MASKBYTE0); + ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24); + + /*Get NHM duration*/ + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC); + ccx_info->NHM_duration = (u16)(value32 & MASKLWORD); + } - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT_11N); - CCX_INFO->NHM_result[0] = (u1Byte)(value32 & bMaskByte0); - CCX_INFO->NHM_result[1] = (u1Byte)((value32 & bMaskByte1) >> 8); - CCX_INFO->NHM_result[2] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[3] = (u1Byte)((value32 & bMaskByte3) >> 24); + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11N); + ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0); + ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24); - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); - CCX_INFO->NHM_result[4] = (u1Byte)(value32 & bMaskByte0); - CCX_INFO->NHM_result[5] = (u1Byte)((value32 & bMaskByte1) >> 8); - CCX_INFO->NHM_result[6] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[7] = (u1Byte)((value32 & bMaskByte3) >> 24); + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); + ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0); + ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24); - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT9_TO_CNT8_11N); - CCX_INFO->NHM_result[8] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[9] = (u1Byte)((value32 & bMaskByte3) >> 24); + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT9_TO_CNT8_11N); + ccx_info->NHM_result[8] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE3) >> 24); - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); - CCX_INFO->NHM_result[10] = (u1Byte)((value32 & bMaskByte2) >> 16); - CCX_INFO->NHM_result[11] = (u1Byte)((value32 & bMaskByte3) >> 24); + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); + ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24); - /*Get NHM duration*/ - value32 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); - CCX_INFO->NHM_duration = (u2Byte)(value32 & bMaskLWord); + /*Get NHM duration*/ + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); + ccx_info->NHM_duration = (u16)(value32 & MASKLWORD); } } -BOOLEAN -phydm_checkNHMready( - IN PVOID pDM_VOID +boolean +phydm_check_nhm_ready( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32 = 0; - u1Byte i; - BOOLEAN ret = FALSE; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 value32 = 0; + u8 i; + boolean ret = false; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); - - for (i = 0; i < 200; i ++) { + for (i = 0; i < 200; i++) { ODM_delay_ms(1); - if (ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC, BIT17)) { + if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(17))) { ret = 1; break; } } } - - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_READY_11N, bMaskDWord); - - for (i = 0; i < 200; i ++) { + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_READY_11N, MASKDWORD); + + for (i = 0; i < 200; i++) { ODM_delay_ms(1); - if (ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC, BIT17) ) { + if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(17))) { ret = 1; break; } - } + } } return ret; } -VOID -phydm_storeNHMsetting( - IN PVOID pDM_VOID +void +phydm_store_nhm_setting( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - } - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - - } } -VOID -phydm_CLMsetting( - IN PVOID pDM_VOID +void +phydm_clm_setting( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKLWORD, ccx_info->CLM_period); /*4us sample 1 time*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(8), 0x1); /*Enable CCX for CLM*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, bMaskLWord, CCX_INFO->CLM_period); /*4us sample 1 time*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT8, 0x1); /*Enable CCX for CLM*/ - - } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - ODM_SetBBReg(pDM_Odm, ODM_REG_CCX_PERIOD_11N, bMaskLWord, CCX_INFO->CLM_period); /*4us sample 1 time*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT8, 0x1); /*Enable CCX for CLM*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKLWORD, ccx_info->CLM_period); /*4us sample 1 time*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(8), 0x1); /*Enable CCX for CLM*/ } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM period = %dus\n", __func__, CCX_INFO->CLM_period*4)); - + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM period = %dus\n", __func__, ccx_info->CLM_period * 4)); + } -VOID -phydm_CLMtrigger( - IN PVOID pDM_VOID +void +phydm_clm_trigger( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT0, 0x0); /*Trigger CLM*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT0, 0x1); - } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT0, 0x0); /*Trigger CLM*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT0, 0x1); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(0), 0x0); /*Trigger CLM*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(0), 0x1); + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(0), 0x0); /*Trigger CLM*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(0), 0x1); } } -BOOLEAN -phydm_checkCLMready( - IN PVOID pDM_VOID +boolean +phydm_check_clm_ready( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte value32 = 0; - BOOLEAN ret = FALSE; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); /*make sure CLM calc is ready*/ - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_READY_11N, bMaskDWord); /*make sure CLM calc is ready*/ - - if ((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (value32 & BIT16)) - ret = TRUE; - else if ((pDM_Odm->SupportICType & ODM_IC_11N_SERIES) && (value32 & BIT17)) - ret = TRUE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 value32 = 0; + boolean ret = false; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); /*make sure CLM calc is ready*/ + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_READY_11N, MASKDWORD); /*make sure CLM calc is ready*/ + + if ((p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) && (value32 & BIT(16))) + ret = true; + else if ((p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) && (value32 & BIT(16))) + ret = true; else - ret = FALSE; + ret = false; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM ready = %d\n", __func__, ret)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM ready = %d\n", __func__, ret)); return ret; } void -phydm_getCLMresult( - IN PVOID pDM_VOID +phydm_get_clm_result( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + + u32 value32 = 0; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); /*read CLM calc result*/ + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11N, MASKDWORD); /*read CLM calc result*/ - u4Byte value32 = 0; - u2Byte results = 0; - - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); /*read CLM calc result*/ - else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11N, bMaskDWord); /*read CLM calc result*/ + ccx_info->CLM_result = (u16)(value32 & MASKLWORD); - CCX_INFO->CLM_result = (u2Byte)(value32 & bMaskLWord); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM result = %dus\n", __func__, ccx_info->CLM_result * 4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM result = %dus\n", __func__, CCX_INFO->CLM_result*4)); - } diff --git a/hal/phydm/phydm_ccx.h b/hal/phydm/phydm_ccx.h index 623b84d..af0a617 100644 --- a/hal/phydm/phydm_ccx.h +++ b/hal/phydm/phydm_ccx.h @@ -1,101 +1,140 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __PHYDMCCX_H__ #define __PHYDMCCX_H__ #define CCX_EN 1 -#define SET_NHM_SETTING 0 -#define STORE_NHM_SETTING 1 -#define RESTORE_NHM_SETTING 2 +#define SET_NHM_SETTING 0 +#define STORE_NHM_SETTING 1 +#define RESTORE_NHM_SETTING 2 /* -#define NHM_EXCLUDE_CCA 0 -#define NHM_INCLUDE_CCA 1 -#define NHM_EXCLUDE_TXON 0 +#define NHM_EXCLUDE_CCA 0 +#define NHM_INCLUDE_CCA 1 +#define NHM_EXCLUDE_TXON 0 #define NHM_INCLUDE_TXON 1 */ -typedef enum NHM_inexclude_cca { +enum nhm_inexclude_cca { NHM_EXCLUDE_CCA, NHM_INCLUDE_CCA -}NHM_INEXCLUDE_CCA; +}; -typedef enum NHM_inexclude_txon { +enum nhm_inexclude_txon { NHM_EXCLUDE_TXON, NHM_INCLUDE_TXON -}NHM_INEXCLUDE_TXON; +}; -typedef struct _CCX_INFO{ +struct _CCX_INFO { /*Settings*/ - u1Byte NHM_th[11]; - u2Byte NHM_period; /* 4us per unit */ - u2Byte CLM_period; /* 4us per unit */ - NHM_INEXCLUDE_TXON NHM_inexclude_txon; - NHM_INEXCLUDE_CCA NHM_inexclude_cca; + u8 NHM_th[11]; + u16 NHM_period; /* 4us per unit */ + u16 CLM_period; /* 4us per unit */ + enum nhm_inexclude_txon nhm_inexclude_txon; + enum nhm_inexclude_cca nhm_inexclude_cca; /*Previous Settings*/ - u1Byte NHM_th_restore[11]; - u2Byte NHM_period_restore; /* 4us per unit */ - u2Byte CLM_period_restore; /* 4us per unit */ - NHM_INEXCLUDE_TXON NHM_inexclude_txon_restore; - NHM_INEXCLUDE_CCA NHM_inexclude_cca_restore; - + u8 NHM_th_restore[11]; + u16 NHM_period_restore; /* 4us per unit */ + u16 CLM_period_restore; /* 4us per unit */ + enum nhm_inexclude_txon NHM_inexclude_txon_restore; + enum nhm_inexclude_cca NHM_inexclude_cca_restore; + /*Report*/ - u1Byte NHM_result[12]; - u2Byte NHM_duration; - u2Byte CLM_result; + u8 NHM_result[12]; + u16 NHM_duration; + u16 CLM_result; + + boolean echo_NHM_en; + boolean echo_CLM_en; + u8 echo_IGI; - BOOLEAN echo_NHM_en; - BOOLEAN echo_CLM_en; - u1Byte echo_IGI; - -}CCX_INFO, *PCCX_INFO; +}; /*NHM*/ -VOID -phydm_NHMsetting( - IN PVOID pDM_VOID, - u1Byte NHMsetting +void +phydm_nhm_counter_statistics_init( + void *p_dm_void +); + +void +phydm_nhm_counter_statistics( + void *p_dm_void +); + +void +phydm_nhm_counter_statistics_reset( + void *p_dm_void +); + +void +phydm_get_nhm_counter_statistics( + void *p_dm_void +); + +boolean +phydm_cal_nhm_cnt( + void *p_dm_void +); + +void +phydm_nhm_setting( + void *p_dm_void, + u8 nhm_setting ); -VOID -phydm_NHMtrigger( - IN PVOID pDM_VOID +void +phydm_nhm_trigger( + void *p_dm_void ); -VOID -phydm_getNHMresult( - IN PVOID pDM_VOID +void +phydm_get_nhm_result( + void *p_dm_void ); -BOOLEAN -phydm_checkNHMready( - IN PVOID pDM_VOID +boolean +phydm_check_nhm_ready( + void *p_dm_void ); /*CLM*/ -VOID -phydm_CLMsetting( - IN PVOID pDM_VOID +void +phydm_clm_setting( + void *p_dm_void ); -VOID -phydm_CLMtrigger( - IN PVOID pDM_VOID +void +phydm_clm_trigger( + void *p_dm_void ); -BOOLEAN -phydm_checkCLMready( - IN PVOID pDM_VOID +boolean +phydm_check_clm_ready( + void *p_dm_void ); -VOID -phydm_getCLMresult( - IN PVOID pDM_VOID +void +phydm_get_clm_result( + void *p_dm_void ); diff --git a/hal/phydm/phydm_cfotracking.c b/hal/phydm/phydm_cfotracking.c index 53c533d..40c5a02 100644 --- a/hal/phydm/phydm_cfotracking.c +++ b/hal/phydm/phydm_cfotracking.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,328 +11,372 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" -VOID -odm_SetCrystalCap( - IN PVOID pDM_VOID, - IN u1Byte CrystalCap +void +phydm_set_crystal_cap( + void *p_dm_void, + u8 crystal_cap ) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); - if(pCfoTrack->CrystalCap == CrystalCap) + if (p_cfo_track->crystal_cap == crystal_cap) return; - pCfoTrack->CrystalCap = CrystalCap; - - if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8188F)) { - /* write 0x24[22:17] = 0x24[16:11] = CrystalCap */ - CrystalCap = CrystalCap & 0x3F; - ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x007ff800, (CrystalCap|(CrystalCap << 6))); - } else if (pDM_Odm->SupportICType & ODM_RTL8812) { - /* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */ - CrystalCap = CrystalCap & 0x3F; - ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap|(CrystalCap << 6))); - } else if ((pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723B|ODM_RTL8192E|ODM_RTL8821))) { - /* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */ - CrystalCap = CrystalCap & 0x3F; - ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap|(CrystalCap << 6))); - } else if (pDM_Odm->SupportICType & ODM_RTL8814A) { - /* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap */ - CrystalCap = CrystalCap & 0x3F; - ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap|(CrystalCap << 6))); - } else if (pDM_Odm->SupportICType & ODM_RTL8822B) { - /* write 0x24[30:25] = 0x28[6:1] = CrystalCap */ - CrystalCap = CrystalCap & 0x3F; - ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7e000000, CrystalCap); - ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7e, CrystalCap); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): Use default setting.\n")); - ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap|(CrystalCap << 6))); + crystal_cap = crystal_cap & 0x3F; + p_cfo_track->crystal_cap = crystal_cap; + + if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) { + #if (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) + /* write 0x24[22:17] = 0x24[16:11] = crystal_cap */ + odm_set_bb_reg(p_dm_odm, REG_AFE_XTAL_CTRL, 0x007ff800, (crystal_cap | (crystal_cap << 6))); + #endif + } + #if (RTL8812A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type & ODM_RTL8812) { + + /* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */ + odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6))); + + } + #endif + #if (RTL8703B_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) + else if ((p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8723D))) { + + /* 0x2C[23:18] = 0x2C[17:12] = crystal_cap */ + odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6))); + + } + #endif + #if (RTL8814A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type & ODM_RTL8814A) { + + /* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */ + odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6))); + + } + #endif + #if (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) + else if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8197F)) { + + /* write 0x24[30:25] = 0x28[6:1] = crystal_cap */ + odm_set_bb_reg(p_dm_odm, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); + odm_set_bb_reg(p_dm_odm, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); + } + #endif + #if (RTL8710B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type & (ODM_RTL8710B)) { + + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + /* write 0x60[29:24] = 0x60[23:18] = crystal_cap */ + HAL_SetSYSOnReg(p_dm_odm->adapter, REG_SYS_XTAL_CTRL0, 0x3FFC0000, (crystal_cap | (crystal_cap << 6))); + #endif + } + #endif + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("Set rystal_cap = 0x%x\n", p_cfo_track->crystal_cap)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): CrystalCap = 0x%x\n", CrystalCap)); -#endif } -u1Byte -odm_GetDefaultCrytaltalCap( - IN PVOID pDM_VOID +u8 +odm_get_default_crytaltal_cap( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte CrystalCap = 0x20; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 crystal_cap = 0x20; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); - CrystalCap = pHalData->CrystalCap; + crystal_cap = rtlefuse->crystalcap; +#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + + crystal_cap = p_hal_data->crystal_cap; #else - prtl8192cd_priv priv = pDM_Odm->priv; + struct rtl8192cd_priv *priv = p_dm_odm->priv; - if(priv->pmib->dot11RFEntry.xcap > 0) - CrystalCap = priv->pmib->dot11RFEntry.xcap; + if (priv->pmib->dot11RFEntry.xcap > 0) + crystal_cap = priv->pmib->dot11RFEntry.xcap; #endif - CrystalCap = CrystalCap & 0x3f; + crystal_cap = crystal_cap & 0x3f; - return CrystalCap; + return crystal_cap; } -VOID -odm_SetATCStatus( - IN PVOID pDM_VOID, - IN BOOLEAN ATCStatus +void +odm_set_atc_status( + void *p_dm_void, + boolean atc_status ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); - if(pCfoTrack->bATCStatus == ATCStatus) + if (p_cfo_track->is_atc_status == atc_status) return; - - ODM_SetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm), ATCStatus); - pCfoTrack->bATCStatus = ATCStatus; + + odm_set_bb_reg(p_dm_odm, ODM_REG(BB_ATC, p_dm_odm), ODM_BIT(BB_ATC, p_dm_odm), atc_status); + p_cfo_track->is_atc_status = atc_status; } -BOOLEAN -odm_GetATCStatus( - IN PVOID pDM_VOID +boolean +odm_get_atc_status( + void *p_dm_void ) { - BOOLEAN ATCStatus; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + boolean atc_status; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ATCStatus = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm)); - return ATCStatus; + atc_status = (boolean)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_ATC, p_dm_odm), ODM_BIT(BB_ATC, p_dm_odm)); + return atc_status; } -VOID -ODM_CfoTrackingReset( - IN PVOID pDM_VOID +void +odm_cfo_tracking_reset( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); - - pCfoTrack->DefXCap = odm_GetDefaultCrytaltalCap(pDM_Odm); - pCfoTrack->bAdjust = TRUE; - - if(pCfoTrack->CrystalCap > pCfoTrack->DefXCap) - { - odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap - 1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, - ("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap)); - } else if (pCfoTrack->CrystalCap < pCfoTrack->DefXCap) - { - odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap + 1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, - ("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap)); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + + p_cfo_track->def_x_cap = odm_get_default_crytaltal_cap(p_dm_odm); + p_cfo_track->is_adjust = true; + + if (p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) { + phydm_set_crystal_cap(p_dm_odm, p_cfo_track->crystal_cap - 1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, + ("odm_cfo_tracking_reset(): approch default value (0x%x)\n", p_cfo_track->crystal_cap)); + } else if (p_cfo_track->crystal_cap < p_cfo_track->def_x_cap) { + phydm_set_crystal_cap(p_dm_odm, p_cfo_track->crystal_cap + 1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, + ("odm_cfo_tracking_reset(): approch default value (0x%x)\n", p_cfo_track->crystal_cap)); } - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - odm_SetATCStatus(pDM_Odm, TRUE); - #endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + odm_set_atc_status(p_dm_odm, true); +#endif } -VOID -ODM_CfoTrackingInit( - IN PVOID pDM_VOID +void +odm_cfo_tracking_init( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); - pCfoTrack->DefXCap = pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm); - pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm); - pCfoTrack->bAdjust = TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========>\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x\n", pCfoTrack->bATCStatus, pCfoTrack->DefXCap)); + p_cfo_track->def_x_cap = p_cfo_track->crystal_cap = odm_get_default_crytaltal_cap(p_dm_odm); + p_cfo_track->is_atc_status = odm_get_atc_status(p_dm_odm); + p_cfo_track->is_adjust = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========>\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): is_atc_status = %d, crystal_cap = 0x%x\n", p_cfo_track->is_atc_status, p_cfo_track->def_x_cap)); #if RTL8822B_SUPPORT /* Crystal cap. control by WiFi */ - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ODM_SetBBReg(pDM_Odm, 0x10, 0x40, 0x1); + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(p_dm_odm, 0x10, 0x40, 0x1); +#endif + +#if RTL8821C_SUPPORT + /* Crystal cap. control by WiFi */ + if (p_dm_odm->support_ic_type & ODM_RTL8821C) + odm_set_bb_reg(p_dm_odm, 0x10, 0x40, 0x1); #endif } -VOID -ODM_CfoTracking( - IN PVOID pDM_VOID +void +odm_cfo_tracking( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); - int CFO_kHz_A, CFO_kHz_B, CFO_ave = 0; - int CFO_ave_diff; - int CrystalCap = (int)pCfoTrack->CrystalCap; - u1Byte Adjust_Xtal = 1; - - //4 Support ability - if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled\n")); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + s32 CFO_ave = 0; + u32 CFO_rpt_sum, cfo_khz_avg[4] = {0}; + s32 CFO_ave_diff; + s8 crystal_cap = p_cfo_track->crystal_cap; + u8 adjust_xtal = 1, i, valid_path_cnt = 0; + + /* 4 Support ability */ + if (!(p_dm_odm->support_ability & ODM_BB_CFO_TRACKING)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Return: support_ability ODM_BB_CFO_TRACKING is disabled\n")); return; } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking()=========> \n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking()=========>\n")); - if(!pDM_Odm->bLinked || !pDM_Odm->bOneEntryOnly) - { - //4 No link or more than one entry - ODM_CfoTrackingReset(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Reset: bLinked = %d, bOneEntryOnly = %d\n", - pDM_Odm->bLinked, pDM_Odm->bOneEntryOnly)); - } - else - { - //3 1. CFO Tracking - //4 1.1 No new packet - if(pCfoTrack->packetCount == pCfoTrack->packetCount_pre) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): packet counter doesn't change\n")); + if (!p_dm_odm->is_linked || !p_dm_odm->is_one_entry_only) { + /* 4 No link or more than one entry */ + odm_cfo_tracking_reset(p_dm_odm); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Reset: is_linked = %d, is_one_entry_only = %d\n", + p_dm_odm->is_linked, p_dm_odm->is_one_entry_only)); + } else { + /* 3 1. CFO Tracking */ + /* 4 1.1 No new packet */ + if (p_cfo_track->packet_count == p_cfo_track->packet_count_pre) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): packet counter doesn't change\n")); return; } - pCfoTrack->packetCount_pre = pCfoTrack->packetCount; - - //4 1.2 Calculate CFO - CFO_kHz_A = (int)((pCfoTrack->CFO_tail[0] * 3125) / 10)>>7; /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */ - CFO_kHz_B = (int)((pCfoTrack->CFO_tail[1] * 3125) / 10)>>7; - - if(pDM_Odm->RFType < ODM_2T2R) - CFO_ave = CFO_kHz_A; - else - CFO_ave = (int)(CFO_kHz_A + CFO_kHz_B) >> 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): CFO_kHz_A = %dkHz, CFO_kHz_B = %dkHz, CFO_ave = %dkHz\n", - CFO_kHz_A, CFO_kHz_B, CFO_ave)); - - //4 1.3 Avoid abnormal large CFO - CFO_ave_diff = (pCfoTrack->CFO_ave_pre >= CFO_ave)?(pCfoTrack->CFO_ave_pre - CFO_ave):(CFO_ave - pCfoTrack->CFO_ave_pre); - if(CFO_ave_diff > 20 && pCfoTrack->largeCFOHit == 0 && !pCfoTrack->bAdjust) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): first large CFO hit\n")); - pCfoTrack->largeCFOHit = 1; - return; + p_cfo_track->packet_count_pre = p_cfo_track->packet_count; + + /* 4 1.2 Calculate CFO */ + for (i = 0; i < p_dm_odm->num_rf_path; i++) { + + if (p_cfo_track->CFO_cnt[i] == 0) + continue; + + valid_path_cnt++; + CFO_rpt_sum = (u32)((p_cfo_track->CFO_tail[i] < 0) ? (0 - p_cfo_track->CFO_tail[i]) : p_cfo_track->CFO_tail[i]); + cfo_khz_avg[i] = CFO_HW_RPT_2_MHZ(CFO_rpt_sum) / p_cfo_track->CFO_cnt[i]; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[path %d] CFO_rpt_sum = (( %d )), CFO_cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n", + i, CFO_rpt_sum, p_cfo_track->CFO_cnt[i], ((p_cfo_track->CFO_tail[i] < 0) ? "-" : " "), cfo_khz_avg[i])); } - else - pCfoTrack->largeCFOHit = 0; - pCfoTrack->CFO_ave_pre = CFO_ave; - - //4 1.4 Dynamic Xtal threshold - if(pCfoTrack->bAdjust == FALSE) - { - if(CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH)) - pCfoTrack->bAdjust = TRUE; + + for (i = 0; i < valid_path_cnt; i++) { + + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("path [%d], p_cfo_track->CFO_tail = %d\n", i, p_cfo_track->CFO_tail[i])); */ + if (p_cfo_track->CFO_tail[i] < 0) { + CFO_ave += (0 - (s32)cfo_khz_avg[i]); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("CFO_ave = %d\n", CFO_ave)); */ + } else + CFO_ave += (s32)cfo_khz_avg[i]; } - else - { - if(CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW)) - pCfoTrack->bAdjust = FALSE; + + if (valid_path_cnt >= 2) + CFO_ave = CFO_ave / valid_path_cnt; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("valid_path_cnt = ((%d)), CFO_ave = ((%d kHz))\n", valid_path_cnt, CFO_ave)); + + /*reset counter*/ + for (i = 0; i < p_dm_odm->num_rf_path; i++) { + p_cfo_track->CFO_tail[i] = 0; + p_cfo_track->CFO_cnt[i] = 0; } -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - //4 1.5 BT case: Disable CFO tracking - if(pDM_Odm->bBtEnabled) - { - pCfoTrack->bAdjust = FALSE; - odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable CFO tracking for BT!!\n")); + /* 4 1.3 Avoid abnormal large CFO */ + CFO_ave_diff = (p_cfo_track->CFO_ave_pre >= CFO_ave) ? (p_cfo_track->CFO_ave_pre - CFO_ave) : (CFO_ave - p_cfo_track->CFO_ave_pre); + if (CFO_ave_diff > 20 && p_cfo_track->large_cfo_hit == 0 && !p_cfo_track->is_adjust) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): first large CFO hit\n")); + p_cfo_track->large_cfo_hit = 1; + return; + } else + p_cfo_track->large_cfo_hit = 0; + p_cfo_track->CFO_ave_pre = CFO_ave; + + /* 4 1.4 Dynamic Xtal threshold */ + if (p_cfo_track->is_adjust == false) { + if (CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH)) + p_cfo_track->is_adjust = true; + } else { + if (CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW)) + p_cfo_track->is_adjust = false; } -/* - //4 1.6 Big jump - if(pCfoTrack->bAdjust) - { - if(CFO_ave > CFO_TH_XTAL_LOW) - Adjust_Xtal = Adjust_Xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2); - else if(CFO_ave < (-CFO_TH_XTAL_LOW)) - Adjust_Xtal = Adjust_Xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap offset = %d\n", Adjust_Xtal)); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + /* 4 1.5 BT case: Disable CFO tracking */ + if (p_dm_odm->is_bt_enabled) { + p_cfo_track->is_adjust = false; + phydm_set_crystal_cap(p_dm_odm, p_cfo_track->def_x_cap); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Disable CFO tracking for BT!!\n")); + } +#if 0 + /* 4 1.6 Big jump */ + if (p_cfo_track->is_adjust) { + if (CFO_ave > CFO_TH_XTAL_LOW) + adjust_xtal = adjust_xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2); + else if (CFO_ave < (-CFO_TH_XTAL_LOW)) + adjust_xtal = adjust_xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Crystal cap offset = %d\n", adjust_xtal)); } -*/ #endif - - //4 1.7 Adjust Crystal Cap. - if(pCfoTrack->bAdjust) - { - if(CFO_ave > CFO_TH_XTAL_LOW) - CrystalCap = CrystalCap + Adjust_Xtal; - else if(CFO_ave < (-CFO_TH_XTAL_LOW)) - CrystalCap = CrystalCap - Adjust_Xtal; - - if(CrystalCap > 0x3f) - CrystalCap = 0x3f; - else if (CrystalCap < 0) - CrystalCap = 0; - - odm_SetCrystalCap(pDM_Odm, (u1Byte)CrystalCap); +#endif + + /* 4 1.7 Adjust Crystal Cap. */ + if (p_cfo_track->is_adjust) { + if (CFO_ave > CFO_TH_XTAL_LOW) + crystal_cap = crystal_cap + adjust_xtal; + else if (CFO_ave < (-CFO_TH_XTAL_LOW)) + crystal_cap = crystal_cap - adjust_xtal; + + if (crystal_cap > 0x3f) + crystal_cap = 0x3f; + else if (crystal_cap < 0) + crystal_cap = 0; + + phydm_set_crystal_cap(p_dm_odm, (u8)crystal_cap); } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n", - pCfoTrack->CrystalCap, pCfoTrack->DefXCap)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n", + p_cfo_track->crystal_cap, p_cfo_track->def_x_cap)); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) return; - - //3 2. Dynamic ATC switch - if(CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC) - { - odm_SetATCStatus(pDM_Odm, FALSE); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable ATC!!\n")); - } - else - { - odm_SetATCStatus(pDM_Odm, TRUE); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Enable ATC!!\n")); + + /* 3 2. Dynamic ATC switch */ + if (CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC) { + odm_set_atc_status(p_dm_odm, false); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Disable ATC!!\n")); + } else { + odm_set_atc_status(p_dm_odm, true); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Enable ATC!!\n")); } #endif } } -VOID -ODM_ParsingCFO( - IN PVOID pDM_VOID, - IN PVOID pPktinfo_VOID, - IN s1Byte* pcfotail - ) +void +odm_parsing_cfo( + void *p_dm_void, + void *p_pktinfo_void, + s8 *pcfotail, + u8 num_ss +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_PACKET_INFO_T pPktinfo = (PODM_PACKET_INFO_T)pPktinfo_VOID; - PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); - u1Byte i; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pktinfo_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + u8 i; - if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) + if (!(p_dm_odm->support_ability & ODM_BB_CFO_TRACKING)) return; -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(pPktinfo->bPacketMatchBSSID) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (p_pktinfo->is_packet_match_bssid) #else - if(pPktinfo->StationID != 0) + if (p_pktinfo->station_id != 0) #endif - { - //3 Update CFO report for path-A & path-B - // Only paht-A and path-B have CFO tail and short CFO - for(i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++) - { - pCfoTrack->CFO_tail[i] = (int)pcfotail[i]; - } - - //3 Update packet counter - if(pCfoTrack->packetCount == 0xffffffff) - pCfoTrack->packetCount = 0; + { + if (num_ss > p_dm_odm->num_rf_path) /*For fool proof*/ + num_ss = p_dm_odm->num_rf_path; + + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("num_ss = ((%d)), p_dm_odm->num_rf_path = ((%d))\n", num_ss, p_dm_odm->num_rf_path));*/ + + + /* 3 Update CFO report for path-A & path-B */ + /* Only paht-A and path-B have CFO tail and short CFO */ + for (i = 0; i < num_ss; i++) { + p_cfo_track->CFO_tail[i] += pcfotail[i]; + p_cfo_track->CFO_cnt[i]++; + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n", + p_pktinfo->station_id, i, p_pktinfo->data_rate, pcfotail[i], p_cfo_track->CFO_tail[i], p_cfo_track->CFO_cnt[i])); + */ + } + + /* 3 Update packet counter */ + if (p_cfo_track->packet_count == 0xffffffff) + p_cfo_track->packet_count = 0; else - pCfoTrack->packetCount++; + p_cfo_track->packet_count++; } } - diff --git a/hal/phydm/phydm_cfotracking.h b/hal/phydm/phydm_cfotracking.h index 32fa611..4dbaeb7 100644 --- a/hal/phydm/phydm_cfotracking.h +++ b/hal/phydm/phydm_cfotracking.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,58 +11,60 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PHYDMCFOTRACK_H__ #define __PHYDMCFOTRACK_H__ #define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/ -#define CFO_TH_XTAL_HIGH 20 // kHz -#define CFO_TH_XTAL_LOW 10 // kHz -#define CFO_TH_ATC 80 // kHz +#define CFO_TH_XTAL_HIGH 20 /* kHz */ +#define CFO_TH_XTAL_LOW 10 /* kHz */ +#define CFO_TH_ATC 80 /* kHz */ -typedef struct _CFO_TRACKING_ -{ - BOOLEAN bATCStatus; - BOOLEAN largeCFOHit; - BOOLEAN bAdjust; - u1Byte CrystalCap; - u1Byte DefXCap; - int CFO_tail[2]; - int CFO_ave_pre; - u4Byte packetCount; - u4Byte packetCount_pre; +struct _CFO_TRACKING_ { + boolean is_atc_status; + boolean large_cfo_hit; + boolean is_adjust; + u8 crystal_cap; + u8 def_x_cap; + s32 CFO_tail[4]; + u32 CFO_cnt[4]; + s32 CFO_ave_pre; + u32 packet_count; + u32 packet_count_pre; - BOOLEAN bForceXtalCap; - BOOLEAN bReset; -}CFO_TRACKING, *PCFO_TRACKING; + boolean is_force_xtal_cap; + boolean is_reset; +}; + +void +phydm_set_crystal_cap( + void *p_dm_void, + u8 crystal_cap +); -VOID -ODM_CfoTrackingReset( - IN PVOID pDM_VOID +void +odm_cfo_tracking_reset( + void *p_dm_void ); -VOID -ODM_CfoTrackingInit( - IN PVOID pDM_VOID +void +odm_cfo_tracking_init( + void *p_dm_void ); -VOID -ODM_CfoTracking( - IN PVOID pDM_VOID +void +odm_cfo_tracking( + void *p_dm_void ); -VOID -ODM_ParsingCFO( - IN PVOID pDM_VOID, - IN PVOID pPktinfo_VOID, - IN s1Byte* pcfotail +void +odm_parsing_cfo( + void *p_dm_void, + void *p_pktinfo_void, + s8 *pcfotail, + u8 num_ss ); -#endif \ No newline at end of file +#endif diff --git a/hal/phydm/phydm_debug.c b/hal/phydm/phydm_debug.c index dddb637..31958ce 100644 --- a/hal/phydm/phydm_debug.c +++ b/hal/phydm/phydm_debug.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,327 +11,601 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" -VOID -PHYDM_InitDebugSetting( - IN PDM_ODM_T pDM_Odm +void +phydm_init_debug_setting( + struct PHY_DM_STRUCT *p_dm_odm ) { - pDM_Odm->DebugLevel = ODM_DBG_TRACE; + p_dm_odm->debug_level = ODM_DBG_TRACE; - pDM_Odm->DebugComponents = + p_dm_odm->fw_debug_components = 0; + p_dm_odm->debug_components = \ #if DBG -/*BB Functions*/ -/* ODM_COMP_DIG |*/ -/* ODM_COMP_RA_MASK |*/ -/* ODM_COMP_DYNAMIC_TXPWR |*/ -/* ODM_COMP_FA_CNT |*/ -/* ODM_COMP_RSSI_MONITOR |*/ -/* ODM_COMP_SNIFFER |*/ -/* ODM_COMP_ANT_DIV |*/ -/* ODM_COMP_NOISY_DETECT |*/ -/* ODM_COMP_RATE_ADAPTIVE |*/ -/* ODM_COMP_PATH_DIV |*/ -/* ODM_COMP_DYNAMIC_PRICCA |*/ -/* ODM_COMP_MP |*/ -/* ODM_COMP_CFO_TRACKING |*/ -/* ODM_COMP_ACS |*/ -/* PHYDM_COMP_ADAPTIVITY |*/ -/* PHYDM_COMP_RA_DBG |*/ -/* PHYDM_COMP_TXBF |*/ - -/*MAC Functions*/ -/* ODM_COMP_EDCA_TURBO |*/ -/* ODM_FW_DEBUG_TRACE |*/ - -/*RF Functions*/ -/* ODM_COMP_TX_PWR_TRACK |*/ -/* ODM_COMP_RX_GAIN_TRACK |*/ -/* ODM_COMP_CALIBRATION |*/ - -/*Common*/ -/* ODM_PHY_CONFIG |*/ -/* ODM_COMP_INIT |*/ -/* ODM_COMP_COMMON |*/ -/* ODM_COMP_API |*/ + /*BB Functions*/ + /* ODM_COMP_DIG |*/ + /* ODM_COMP_RA_MASK |*/ + /* ODM_COMP_DYNAMIC_TXPWR |*/ + /* ODM_COMP_FA_CNT |*/ + /* ODM_COMP_RSSI_MONITOR |*/ + /* ODM_COMP_SNIFFER |*/ + /* ODM_COMP_ANT_DIV |*/ + /* ODM_COMP_NOISY_DETECT |*/ + /* ODM_COMP_RATE_ADAPTIVE |*/ + /* ODM_COMP_PATH_DIV |*/ + /* ODM_COMP_DYNAMIC_PRICCA |*/ + /* ODM_COMP_MP |*/ + /* ODM_COMP_CFO_TRACKING |*/ + /* ODM_COMP_ACS |*/ + /* PHYDM_COMP_ADAPTIVITY |*/ + /* PHYDM_COMP_RA_DBG |*/ + /* PHYDM_COMP_TXBF |*/ + + /*MAC Functions*/ + /* ODM_COMP_EDCA_TURBO |*/ + /* ODM_COMP_DYNAMIC_RX_PATH |*/ + /* ODM_FW_DEBUG_TRACE |*/ + + /*RF Functions*/ + /* ODM_COMP_TX_PWR_TRACK |*/ + /* ODM_COMP_CALIBRATION |*/ + + /*Common*/ + /* ODM_PHY_CONFIG |*/ + /* ODM_COMP_INIT |*/ + /* ODM_COMP_COMMON |*/ + /* ODM_COMP_API |*/ #endif 0; - pDM_Odm->fw_buff_is_enpty = TRUE; - pDM_Odm->pre_c2h_seq = 0; + p_dm_odm->fw_buff_is_enpty = true; + p_dm_odm->pre_c2h_seq = 0; +} + +void +phydm_bb_dbg_port_header_sel( + void *p_dm_void, + u32 header_idx +) { + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0x8f8, (BIT(25) | BIT(24) | BIT(23) | BIT(22)), header_idx); + + /* + header_idx: + (0:) '{ofdm_dbg[31:0]}' + (1:) '{cca,crc32_fail,dbg_ofdm[29:0]}' + (2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}' + (3:) '{cca,crc32_ok,dbg_ofdm[29:0]}' + (4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}' + (5:) '{dbg_iqk_anta}' + (6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}' + (7:) '{dbg_iqk_antb}' + (8:) '{DBGOUT_RFC_b[31:0]}' + (9:) '{DBGOUT_RFC_a[31:0]}' + (a:) '{dbg_ofdm}' + (b:) '{dbg_cck}' + */ + } +} + +void +phydm_bb_dbg_port_clock_en( + void *p_dm_void, + u8 enable +) { + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 reg_value = 0; + + if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814A | ODM_RTL8814B)) { + + reg_value = (enable == true) ? 0x7 : 0; + odm_set_bb_reg(p_dm_odm, 0x198c, 0x7, reg_value); /*enable/disable debug port clock, for power saving*/ + } +} + +u8 +phydm_set_bb_dbg_port( + void *p_dm_void, + u8 curr_dbg_priority, + u32 debug_port +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 dbg_port_result = false; + + if (curr_dbg_priority > p_dm_odm->pre_dbg_priority) { + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + phydm_bb_dbg_port_clock_en(p_dm_odm, TRUE); + + odm_set_bb_reg(p_dm_odm, 0x8fc, MASKDWORD, debug_port); + /**/ + } else /*if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)*/ { + odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, debug_port); + /**/ + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("DbgPort set success, Reg((0x%x)), Cur_priority=((%d)), Pre_priority=((%d))\n", debug_port, curr_dbg_priority, p_dm_odm->pre_dbg_priority)); + p_dm_odm->pre_dbg_priority = curr_dbg_priority; + dbg_port_result = true; + } + + return dbg_port_result; +} + +void +phydm_release_bb_dbg_port( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + phydm_bb_dbg_port_clock_en(p_dm_odm, FALSE); + phydm_bb_dbg_port_header_sel(p_dm_odm, 0); + + p_dm_odm->pre_dbg_priority = BB_DBGPORT_RELEASE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Release BB dbg_port\n")); } -VOID -phydm_BB_RxHang_Info( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len +u32 +phydm_get_bb_dbg_port_value( + void *p_dm_void ) { - u4Byte value32 = 0; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte used = *_used; - u4Byte out_len = *_out_len; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 dbg_port_value = 0; - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + dbg_port_value = odm_get_bb_reg(p_dm_odm, 0xfa0, MASKDWORD); + /**/ + } else /*if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)*/ { + dbg_port_value = odm_get_bb_reg(p_dm_odm, 0xdf4, MASKDWORD); + /**/ + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("dbg_port_value = 0x%x\n", dbg_port_value)); + return dbg_port_value; +} + +#if CONFIG_PHYDM_DEBUG_FUNCTION +void +phydm_bb_rx_hang_info( + void *p_dm_void, + u32 *_used, + char *output, + u32 *_out_len +) +{ + u32 value32 = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) return; - value32 = ODM_GetBBReg(pDM_Odm, 0xF80 , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, 0xF80, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32)); - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ODM_SetBBReg(pDM_Odm, 0x198c , BIT2|BIT1|BIT0, 7); + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(p_dm_odm, 0x198c, BIT(2) | BIT(1) | BIT(0), 7); /* dbg_port = basic state machine */ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x000); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "basic state machine", value32)); } /* dbg_port = state machine */ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x007); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "state machine", value32)); } /* dbg_port = CCA-related*/ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x204); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "CCA-related", value32)); } /* dbg_port = edcca/rxd*/ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x278); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "edcca/rxd", value32)); } /* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x290); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx_state/mux_state/ADC_MASK_OFDM", value32)); } /* dbg_port = bf-related*/ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x2B2); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "bf-related", value32)); } /* dbg_port = bf-related*/ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x2B8); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "bf-related", value32)); } /* dbg_port = txon/rxd*/ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xA03); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "txon/rxd", value32)); } /* dbg_port = l_rate/l_length*/ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xA0B); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "l_rate/l_length", value32)); } /* dbg_port = rxd/rxd_hit*/ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xA0D); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32)); } /* dbg_port = dis_cca*/ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAA0); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "dis_cca", value32)); } /* dbg_port = tx*/ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAB0); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "tx", value32)); } /* dbg_port = rx plcp*/ { - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD0); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD1); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD2); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD3); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); } } -VOID -phydm_BB_Debug_Info( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len +void +phydm_bb_debug_info_n_series( + void *p_dm_void, + u32 *_used, + char *output, + u32 *_out_len ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + u32 value32 = 0, value32_1 = 0; + u8 rf_gain_a = 0, rf_gain_b = 0, rf_gain_c = 0, rf_gain_d = 0; + u8 rx_snr_a = 0, rx_snr_b = 0, rx_snr_c = 0, rx_snr_d = 0; + + s8 rxevm_0 = 0, rxevm_1 = 0; + s32 short_cfo_a = 0, short_cfo_b = 0, long_cfo_a = 0, long_cfo_b = 0; + s32 scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0; + s32 cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a = 0, acq_cfo_b = 0; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s\n", "BB Report Info")); + + /*AGC result*/ + value32 = odm_get_bb_reg(p_dm_odm, 0xdd0, MASKDWORD); + rf_gain_a = (u8)(value32 & 0x3f); + rf_gain_a = rf_gain_a << 1; + + rf_gain_b = (u8)((value32 >> 8) & 0x3f); + rf_gain_b = rf_gain_b << 1; + + rf_gain_c = (u8)((value32 >> 16) & 0x3f); + rf_gain_c = rf_gain_c << 1; + + rf_gain_d = (u8)((value32 >> 24) & 0x3f); + rf_gain_d = rf_gain_d << 1; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", rf_gain_a, rf_gain_b, rf_gain_c, rf_gain_d)); + + /*SNR report*/ + value32 = odm_get_bb_reg(p_dm_odm, 0xdd4, MASKDWORD); + rx_snr_a = (u8)(value32 & 0xff); + rx_snr_a = rx_snr_a >> 1; + + rx_snr_b = (u8)((value32 >> 8) & 0xff); + rx_snr_b = rx_snr_b >> 1; + + rx_snr_c = (u8)((value32 >> 16) & 0xff); + rx_snr_c = rx_snr_c >> 1; + + rx_snr_d = (u8)((value32 >> 24) & 0xff); + rx_snr_d = rx_snr_d >> 1; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d)); + + /* PostFFT related info*/ + value32 = odm_get_bb_reg(p_dm_odm, 0xdd8, MASKDWORD); + + rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_0 /= 2; + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24); + rxevm_1 /= 2; + if (rxevm_1 < -63) + rxevm_1 = 0; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "RXEVM (1ss/2ss)", rxevm_0, rxevm_1)); + + /*CFO Report Info*/ + odm_set_bb_reg(p_dm_odm, 0xd00, BIT(26), 1); + + /*Short CFO*/ + value32 = odm_get_bb_reg(p_dm_odm, 0xdac, MASKDWORD); + value32_1 = odm_get_bb_reg(p_dm_odm, 0xdb0, MASKDWORD); + + short_cfo_b = (s32)(value32 & 0xfff); /*S(12,11)*/ + short_cfo_a = (s32)((value32 & 0x0fff0000) >> 16); + + long_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/ + long_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16); + + /*SFO 2's to dec*/ + if (short_cfo_a > 2047) + short_cfo_a = short_cfo_a - 4096; + if (short_cfo_b > 2047) + short_cfo_b = short_cfo_b - 4096; + + short_cfo_a = (short_cfo_a * 312500) / 2048; + short_cfo_b = (short_cfo_b * 312500) / 2048; + + /*LFO 2's to dec*/ + + if (long_cfo_a > 4095) + long_cfo_a = long_cfo_a - 8192; + + if (long_cfo_b > 4095) + long_cfo_b = long_cfo_b - 8192; + + long_cfo_a = long_cfo_a * 312500 / 4096; + long_cfo_b = long_cfo_b * 312500 / 4096; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "CFO Report Info")); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Short CFO(Hz) ", short_cfo_a, short_cfo_b)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Long CFO(Hz) ", long_cfo_a, long_cfo_b)); + + /*SCFO*/ + value32 = odm_get_bb_reg(p_dm_odm, 0xdb8, MASKDWORD); + value32_1 = odm_get_bb_reg(p_dm_odm, 0xdb4, MASKDWORD); + + scfo_b = (s32)(value32 & 0x7ff); /*S(11,10)*/ + scfo_a = (s32)((value32 & 0x07ff0000) >> 16); + + if (scfo_a > 1023) + scfo_a = scfo_a - 2048; + + if (scfo_b > 1023) + scfo_b = scfo_b - 2048; + + scfo_a = scfo_a * 312500 / 1024; + scfo_b = scfo_b * 312500 / 1024; + + avg_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/ + avg_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16); + + if (avg_cfo_a > 4095) + avg_cfo_a = avg_cfo_a - 8192; + + if (avg_cfo_b > 4095) + avg_cfo_b = avg_cfo_b - 8192; + + avg_cfo_a = avg_cfo_a * 312500 / 4096; + avg_cfo_b = avg_cfo_b * 312500 / 4096; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "value SCFO(Hz) ", scfo_a, scfo_b)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Avg CFO(Hz) ", avg_cfo_a, avg_cfo_b)); + + value32 = odm_get_bb_reg(p_dm_odm, 0xdbc, MASKDWORD); + value32_1 = odm_get_bb_reg(p_dm_odm, 0xde0, MASKDWORD); + + cfo_end_b = (s32)(value32 & 0x1fff); /*S(13,12)*/ + cfo_end_a = (s32)((value32 & 0x1fff0000) >> 16); + + if (cfo_end_a > 4095) + cfo_end_a = cfo_end_a - 8192; + + if (cfo_end_b > 4095) + cfo_end_b = cfo_end_b - 8192; + + cfo_end_a = cfo_end_a * 312500 / 4096; + cfo_end_b = cfo_end_b * 312500 / 4096; + + acq_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/ + acq_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16); + + if (acq_cfo_a > 4095) + acq_cfo_a = acq_cfo_a - 8192; + + if (acq_cfo_b > 4095) + acq_cfo_b = acq_cfo_b - 8192; + + acq_cfo_a = acq_cfo_a * 312500 / 4096; + acq_cfo_b = acq_cfo_b * 312500 / 4096; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "End CFO(Hz) ", cfo_end_a, cfo_end_b)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "ACQ CFO(Hz) ", acq_cfo_a, acq_cfo_b)); + +} + + +void +phydm_bb_debug_info( + void *p_dm_void, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + char *tmp_string = NULL; - u1Byte RX_HT_BW, RX_VHT_BW, RXSC, RX_HT, RX_BW; - static u1Byte vRX_BW ; - u4Byte value32, value32_1, value32_2, value32_3; - s4Byte SFO_A, SFO_B, SFO_C, SFO_D; - s4Byte LFO_A, LFO_B, LFO_C, LFO_D; - static u1Byte MCSS, Tail, Parity, rsv, vrsv, idx, smooth, htsound, agg, stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, vNsts, vtxops, vrsv2, vbrsv, bf, vbcrc; - static u2Byte HLength, htcrc8, Length; - static u2Byte vpaid; - static u2Byte vLength, vhtcrc8, vMCSS, vTail, vbTail; - static u1Byte HMCSS, HRX_BW; - - u1Byte pwDB; - s1Byte RXEVM_0, RXEVM_1, RXEVM_2 ; - u1Byte RF_gain_pathA, RF_gain_pathB, RF_gain_pathC, RF_gain_pathD; - u1Byte RX_SNR_pathA, RX_SNR_pathB, RX_SNR_pathC, RX_SNR_pathD; - s4Byte sig_power; + u8 RX_HT_BW, RX_VHT_BW, RXSC, RX_HT, RX_BW; + static u8 v_rx_bw ; + u32 value32, value32_1, value32_2, value32_3; + s32 SFO_A, SFO_B, SFO_C, SFO_D; + s32 LFO_A, LFO_B, LFO_C, LFO_D; + static u8 MCSS, tail, parity, rsv, vrsv, idx, smooth, htsound, agg, stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts, vtxops, vrsv2, vbrsv, bf, vbcrc; + static u16 h_length, htcrc8, length; + static u16 vpaid; + static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail; + static u8 HMCSS, HRX_BW; + + u8 pwdb; + s8 RXEVM_0, RXEVM_1, RXEVM_2 ; + u8 rf_gain_path_a, rf_gain_path_b, rf_gain_path_c, rf_gain_path_d; + u8 rx_snr_path_a, rx_snr_path_b, rx_snr_path_c, rx_snr_path_d; + s32 sig_power; const char *L_rate[8] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M"}; - /* - const double evm_comp_20M = 0.579919469776867; //10*log10(64.0/56.0) - const double evm_comp_40M = 0.503051183113957; //10*log10(128.0/114.0) - const double evm_comp_80M = 0.244245993314183; //10*log10(256.0/242.0) - const double evm_comp_160M = 0.244245993314183; //10*log10(512.0/484.0) - */ +#if 0 + const double evm_comp_20M = 0.579919469776867; /* 10*log10(64.0/56.0) */ + const double evm_comp_40M = 0.503051183113957; /* 10*log10(128.0/114.0) */ + const double evm_comp_80M = 0.244245993314183; /* 10*log10(256.0/242.0) */ + const double evm_comp_160M = 0.244245993314183; /* 10*log10(512.0/484.0) */ +#endif - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + phydm_bb_debug_info_n_series(p_dm_odm, &used, output, &out_len); return; + } PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s\n", "BB Report Info")); - /*BW & Mode Detection*/ - - value32 = ODM_GetBBReg(pDM_Odm, 0xf80 , bMaskDWord); + /*BW & mode Detection*/ + + value32 = odm_get_bb_reg(p_dm_odm, 0xf80, MASKDWORD); value32_2 = value32; - RX_HT_BW = (u1Byte)(value32 & 0x1); - RX_VHT_BW = (u1Byte)((value32 >> 1) & 0x3); - RXSC = (u1Byte)(value32 & 0x78); + RX_HT_BW = (u8)(value32 & 0x1); + RX_VHT_BW = (u8)((value32 >> 1) & 0x3); + RXSC = (u8)(value32 & 0x78); value32_1 = (value32 & 0x180) >> 7; - RX_HT = (u1Byte)(value32_1); + RX_HT = (u8)(value32_1); RX_BW = 0; if (RX_HT == 2) { - if (RX_VHT_BW == 0) { + if (RX_VHT_BW == 0) tmp_string = "20M"; - } else if (RX_VHT_BW == 1) { + else if (RX_VHT_BW == 1) tmp_string = "40M"; - } else { + else tmp_string = "80M"; - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s %s", "Mode", "VHT", tmp_string)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s %s", "mode", "VHT", tmp_string)); RX_BW = RX_VHT_BW; } else if (RX_HT == 1) { - if (RX_HT_BW == 0) { + if (RX_HT_BW == 0) tmp_string = "20M"; - } else if (RX_HT_BW == 1) { + else if (RX_HT_BW == 1) tmp_string = "40M"; - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s %s", "Mode", "HT", tmp_string)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s %s", "mode", "HT", tmp_string)); RX_BW = RX_HT_BW; - } else { - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s", "Mode", "Legacy")); - } + } else + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s", "mode", "Legacy")); if (RX_HT != 0) { if (RXSC == 0) @@ -353,64 +627,64 @@ phydm_BB_Debug_Info( /* RX signal power and AGC related info*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xF90 , bMaskDWord); - pwDB = (u1Byte)((value32 & bMaskByte1) >> 8); - pwDB = pwDB >> 1; - sig_power = -110 + pwDB; + value32 = odm_get_bb_reg(p_dm_odm, 0xF90, MASKDWORD); + pwdb = (u8)((value32 & MASKBYTE1) >> 8); + pwdb = pwdb >> 1; + sig_power = -110 + pwdb; PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", sig_power)); - value32 = ODM_GetBBReg(pDM_Odm, 0xd14 , bMaskDWord); - RX_SNR_pathA = (u1Byte)(value32 & 0xFF) >> 1; - RF_gain_pathA = (s1Byte)((value32 & bMaskByte1) >> 8); - RF_gain_pathA *= 2; - value32 = ODM_GetBBReg(pDM_Odm, 0xd54 , bMaskDWord); - RX_SNR_pathB = (u1Byte)(value32 & 0xFF) >> 1; - RF_gain_pathB = (s1Byte)((value32 & bMaskByte1) >> 8); - RF_gain_pathB *= 2; - value32 = ODM_GetBBReg(pDM_Odm, 0xd94 , bMaskDWord); - RX_SNR_pathC = (u1Byte)(value32 & 0xFF) >> 1; - RF_gain_pathC = (s1Byte)((value32 & bMaskByte1) >> 8); - RF_gain_pathC *= 2; - value32 = ODM_GetBBReg(pDM_Odm, 0xdd4 , bMaskDWord); - RX_SNR_pathD = (u1Byte)(value32 & 0xFF) >> 1; - RF_gain_pathD = (s1Byte)((value32 & bMaskByte1) >> 8); - RF_gain_pathD *= 2; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", RF_gain_pathA, RF_gain_pathB, RF_gain_pathC, RF_gain_pathD)); - - - /* RX Counter related info*/ - - value32 = ODM_GetBBReg(pDM_Odm, 0xF08, bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM CCA Counter", ((value32&0xFFFF0000)>>16))); - - value32 = ODM_GetBBReg(pDM_Odm, 0xFD0, bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM SBD Fail Counter", value32&0xFFFF)); + value32 = odm_get_bb_reg(p_dm_odm, 0xd14, MASKDWORD); + rx_snr_path_a = (u8)(value32 & 0xFF) >> 1; + rf_gain_path_a = (s8)((value32 & MASKBYTE1) >> 8); + rf_gain_path_a *= 2; + value32 = odm_get_bb_reg(p_dm_odm, 0xd54, MASKDWORD); + rx_snr_path_b = (u8)(value32 & 0xFF) >> 1; + rf_gain_path_b = (s8)((value32 & MASKBYTE1) >> 8); + rf_gain_path_b *= 2; + value32 = odm_get_bb_reg(p_dm_odm, 0xd94, MASKDWORD); + rx_snr_path_c = (u8)(value32 & 0xFF) >> 1; + rf_gain_path_c = (s8)((value32 & MASKBYTE1) >> 8); + rf_gain_path_c *= 2; + value32 = odm_get_bb_reg(p_dm_odm, 0xdd4, MASKDWORD); + rx_snr_path_d = (u8)(value32 & 0xFF) >> 1; + rf_gain_path_d = (s8)((value32 & MASKBYTE1) >> 8); + rf_gain_path_d *= 2; + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", rf_gain_path_a, rf_gain_path_b, rf_gain_path_c, rf_gain_path_d)); + + + /* RX counter related info*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xFC4, bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail Counter", value32&0xFFFF, ((value32&0xFFFF0000)>>16))); + value32 = odm_get_bb_reg(p_dm_odm, 0xF08, MASKDWORD); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM CCA counter", ((value32 & 0xFFFF0000) >> 16))); - value32 = ODM_GetBBReg(pDM_Odm, 0xFCC, bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "CCK CCA Counter", value32&0xFFFF)); + value32 = odm_get_bb_reg(p_dm_odm, 0xFD0, MASKDWORD); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM SBD Fail counter", value32 & 0xFFFF)); - value32 = ODM_GetBBReg(pDM_Odm, 0xFBC, bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "LSIG (Parity Fail/Rate Illegal) Counter", value32&0xFFFF, ((value32&0xFFFF0000)>>16))); + value32 = odm_get_bb_reg(p_dm_odm, 0xFC4, MASKDWORD); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail counter", value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16))); - value32_1 = ODM_GetBBReg(pDM_Odm, 0xFC8, bMaskDWord); - value32_2 = ODM_GetBBReg(pDM_Odm, 0xFC0, bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT counter", ((value32_2&0xFFFF0000)>>16), value32_1&0xFFFF)); + value32 = odm_get_bb_reg(p_dm_odm, 0xFCC, MASKDWORD); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "CCK CCA counter", value32 & 0xFFFF)); + + value32 = odm_get_bb_reg(p_dm_odm, 0xFBC, MASKDWORD); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "LSIG (parity Fail/rate Illegal) counter", value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16))); + + value32_1 = odm_get_bb_reg(p_dm_odm, 0xFC8, MASKDWORD); + value32_2 = odm_get_bb_reg(p_dm_odm, 0xFC0, MASKDWORD); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT counter", ((value32_2 & 0xFFFF0000) >> 16), value32_1 & 0xFFFF)); /* PostFFT related info*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xF8c , bMaskDWord); - RXEVM_0 = (s1Byte)((value32 & bMaskByte2) >> 16); + value32 = odm_get_bb_reg(p_dm_odm, 0xF8c, MASKDWORD); + RXEVM_0 = (s8)((value32 & MASKBYTE2) >> 16); RXEVM_0 /= 2; if (RXEVM_0 < -63) RXEVM_0 = 0; - RXEVM_1 = (s1Byte)((value32 & bMaskByte3) >> 24); + RXEVM_1 = (s8)((value32 & MASKBYTE3) >> 24); RXEVM_1 /= 2; - value32 = ODM_GetBBReg(pDM_Odm, 0xF88 , bMaskDWord); - RXEVM_2 = (s1Byte)((value32 & bMaskByte2) >> 16); + value32 = odm_get_bb_reg(p_dm_odm, 0xF88, MASKDWORD); + RXEVM_2 = (s8)((value32 & MASKBYTE2) >> 16); RXEVM_2 /= 2; if (RXEVM_1 < -63) @@ -419,33 +693,33 @@ phydm_BB_Debug_Info( RXEVM_2 = 0; PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", RXEVM_0, RXEVM_1, RXEVM_2)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", RX_SNR_pathA, RX_SNR_pathB, RX_SNR_pathC, RX_SNR_pathD)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", rx_snr_path_a, rx_snr_path_b, rx_snr_path_c, rx_snr_path_d)); - value32 = ODM_GetBBReg(pDM_Odm, 0xF8C , bMaskDWord); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32&0xFFFF, ((value32&0xFFFF0000)>>16))); + value32 = odm_get_bb_reg(p_dm_odm, 0xF8C, MASKDWORD); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16))); - /*BW & Mode Detection*/ + /*BW & mode Detection*/ - /*Reset Page F Counter*/ - ODM_SetBBReg(pDM_Odm, 0xB58 , BIT0, 1); - ODM_SetBBReg(pDM_Odm, 0xB58 , BIT0, 0); + /*Reset Page F counter*/ + odm_set_bb_reg(p_dm_odm, 0xB58, BIT(0), 1); + odm_set_bb_reg(p_dm_odm, 0xB58, BIT(0), 0); /*CFO Report Info*/ /*Short CFO*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xd0c , bMaskDWord); - value32_1 = ODM_GetBBReg(pDM_Odm, 0xd4c , bMaskDWord); - value32_2 = ODM_GetBBReg(pDM_Odm, 0xd8c , bMaskDWord); - value32_3 = ODM_GetBBReg(pDM_Odm, 0xdcc , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, 0xd0c, MASKDWORD); + value32_1 = odm_get_bb_reg(p_dm_odm, 0xd4c, MASKDWORD); + value32_2 = odm_get_bb_reg(p_dm_odm, 0xd8c, MASKDWORD); + value32_3 = odm_get_bb_reg(p_dm_odm, 0xdcc, MASKDWORD); - SFO_A = (s4Byte)(value32 & 0xfff); - SFO_B = (s4Byte)(value32_1 & 0xfff); - SFO_C = (s4Byte)(value32_2 & 0xfff); - SFO_D = (s4Byte)(value32_3 & 0xfff); + SFO_A = (s32)(value32 & 0xfff); + SFO_B = (s32)(value32_1 & 0xfff); + SFO_C = (s32)(value32_2 & 0xfff); + SFO_D = (s32)(value32_3 & 0xfff); - LFO_A = (s4Byte)(value32 >> 16); - LFO_B = (s4Byte)(value32_1 >> 16); - LFO_C = (s4Byte)(value32_2 >> 16); - LFO_D = (s4Byte)(value32_3 >> 16); + LFO_A = (s32)(value32 >> 16); + LFO_B = (s32)(value32_1 >> 16); + LFO_C = (s32)(value32_2 >> 16); + LFO_D = (s32)(value32_3 >> 16); /*SFO 2's to dec*/ if (SFO_A > 2047) @@ -483,15 +757,15 @@ phydm_BB_Debug_Info( PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "Long CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); /*SCFO*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xd10 , bMaskDWord); - value32_1 = ODM_GetBBReg(pDM_Odm, 0xd50 , bMaskDWord); - value32_2 = ODM_GetBBReg(pDM_Odm, 0xd90 , bMaskDWord); - value32_3 = ODM_GetBBReg(pDM_Odm, 0xdd0 , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, 0xd10, MASKDWORD); + value32_1 = odm_get_bb_reg(p_dm_odm, 0xd50, MASKDWORD); + value32_2 = odm_get_bb_reg(p_dm_odm, 0xd90, MASKDWORD); + value32_3 = odm_get_bb_reg(p_dm_odm, 0xdd0, MASKDWORD); - SFO_A = (s4Byte)(value32 & 0x7ff); - SFO_B = (s4Byte)(value32_1 & 0x7ff); - SFO_C = (s4Byte)(value32_2 & 0x7ff); - SFO_D = (s4Byte)(value32_3 & 0x7ff); + SFO_A = (s32)(value32 & 0x7ff); + SFO_B = (s32)(value32_1 & 0x7ff); + SFO_C = (s32)(value32_2 & 0x7ff); + SFO_D = (s32)(value32_3 & 0x7ff); if (SFO_A > 1023) SFO_A = SFO_A - 2048; @@ -510,10 +784,10 @@ phydm_BB_Debug_Info( SFO_C = SFO_C * 312500 / 1024; SFO_D = SFO_D * 312500 / 1024; - LFO_A = (s4Byte)(value32 >> 16); - LFO_B = (s4Byte)(value32_1 >> 16); - LFO_C = (s4Byte)(value32_2 >> 16); - LFO_D = (s4Byte)(value32_3 >> 16); + LFO_A = (s32)(value32 >> 16); + LFO_B = (s32)(value32_1 >> 16); + LFO_C = (s32)(value32_2 >> 16); + LFO_D = (s32)(value32_3 >> 16); if (LFO_A > 4095) LFO_A = LFO_A - 8192; @@ -530,19 +804,19 @@ phydm_BB_Debug_Info( LFO_B = LFO_B * 312500 / 4096; LFO_C = LFO_C * 312500 / 4096; LFO_D = LFO_D * 312500 / 4096; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "Value SCFO(Hz) ", SFO_A, SFO_B, SFO_C, SFO_D)); + + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "value SCFO(Hz) ", SFO_A, SFO_B, SFO_C, SFO_D)); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "ACQ CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); - value32 = ODM_GetBBReg(pDM_Odm, 0xd14 , bMaskDWord); - value32_1 = ODM_GetBBReg(pDM_Odm, 0xd54 , bMaskDWord); - value32_2 = ODM_GetBBReg(pDM_Odm, 0xd94 , bMaskDWord); - value32_3 = ODM_GetBBReg(pDM_Odm, 0xdd4 , bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, 0xd14, MASKDWORD); + value32_1 = odm_get_bb_reg(p_dm_odm, 0xd54, MASKDWORD); + value32_2 = odm_get_bb_reg(p_dm_odm, 0xd94, MASKDWORD); + value32_3 = odm_get_bb_reg(p_dm_odm, 0xdd4, MASKDWORD); - LFO_A = (s4Byte)(value32 >> 16); - LFO_B = (s4Byte)(value32_1 >> 16); - LFO_C = (s4Byte)(value32_2 >> 16); - LFO_D = (s4Byte)(value32_3 >> 16); + LFO_A = (s32)(value32 >> 16); + LFO_B = (s32)(value32_1 >> 16); + LFO_C = (s32)(value32_2 >> 16); + LFO_D = (s32)(value32_3 >> 16); if (LFO_A > 4095) LFO_A = LFO_A - 8192; @@ -563,13 +837,13 @@ phydm_BB_Debug_Info( PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "End CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); - value32 = ODM_GetBBReg(pDM_Odm, 0xf20 , bMaskDWord); /*L SIG*/ + value32 = odm_get_bb_reg(p_dm_odm, 0xf20, MASKDWORD); /*L SIG*/ - Tail = (u1Byte)((value32 & 0xfc0000) >> 16); - Parity = (u1Byte)((value32 & 0x20000) >> 16); - Length = (u2Byte)((value32 & 0x1ffe00) >> 8); - rsv = (u1Byte)(value32 & 0x10); - MCSS = (u1Byte)(value32 & 0x0f); + tail = (u8)((value32 & 0xfc0000) >> 16); + parity = (u8)((value32 & 0x20000) >> 16); + length = (u16)((value32 & 0x1ffe00) >> 8); + rsv = (u8)(value32 & 0x10); + MCSS = (u8)(value32 & 0x0f); switch (MCSS) { case 0x0b: @@ -600,512 +874,723 @@ phydm_BB_Debug_Info( } PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "L-SIG")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s : %s", "Rate", L_rate[idx])); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x", "Rsv/Length/Parity", rsv, RX_BW, Length)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s : %s", "rate", L_rate[idx])); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x", "Rsv/length/parity", rsv, RX_BW, length)); - value32 = ODM_GetBBReg(pDM_Odm, 0xf2c , bMaskDWord); /*HT SIG*/ + value32 = odm_get_bb_reg(p_dm_odm, 0xf2c, MASKDWORD); /*HT SIG*/ if (RX_HT == 1) { - HMCSS = (u1Byte)(value32 & 0x7F); - HRX_BW = (u1Byte)(value32 & 0x80); - HLength = (u2Byte)((value32 >> 8) & 0xffff); + HMCSS = (u8)(value32 & 0x7F); + HRX_BW = (u8)(value32 & 0x80); + h_length = (u16)((value32 >> 8) & 0xffff); } PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "HT-SIG1")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x", "MCS/BW/Length", HMCSS, HRX_BW, HLength)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x", "MCS/BW/length", HMCSS, HRX_BW, h_length)); - value32 = ODM_GetBBReg(pDM_Odm, 0xf30 , bMaskDWord); /*HT SIG*/ + value32 = odm_get_bb_reg(p_dm_odm, 0xf30, MASKDWORD); /*HT SIG*/ if (RX_HT == 1) { - smooth = (u1Byte)(value32 & 0x01); - htsound = (u1Byte)(value32 & 0x02); - rsv = (u1Byte)(value32 & 0x04); - agg = (u1Byte)(value32 & 0x08); - stbc = (u1Byte)(value32 & 0x30); - fec = (u1Byte)(value32 & 0x40); - sgi = (u1Byte)(value32 & 0x80); - htltf = (u1Byte)((value32 & 0x300) >> 8); - htcrc8 = (u2Byte)((value32 & 0x3fc00) >> 8); - Tail = (u1Byte)((value32 & 0xfc0000) >> 16); + smooth = (u8)(value32 & 0x01); + htsound = (u8)(value32 & 0x02); + rsv = (u8)(value32 & 0x04); + agg = (u8)(value32 & 0x08); + stbc = (u8)(value32 & 0x30); + fec = (u8)(value32 & 0x40); + sgi = (u8)(value32 & 0x80); + htltf = (u8)((value32 & 0x300) >> 8); + htcrc8 = (u16)((value32 & 0x3fc00) >> 8); + tail = (u8)((value32 & 0xfc0000) >> 16); } PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "HT-SIG2")); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x", "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", smooth, htsound, rsv, agg, stbc, fec)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x", "SGI/E-HT-LTFs/CRC/Tail", sgi, htltf, htcrc8, Tail)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x", "SGI/E-HT-LTFs/CRC/tail", sgi, htltf, htcrc8, tail)); - value32 = ODM_GetBBReg(pDM_Odm, 0xf2c , bMaskDWord); /*VHT SIG A1*/ + value32 = odm_get_bb_reg(p_dm_odm, 0xf2c, MASKDWORD); /*VHT SIG A1*/ if (RX_HT == 2) { - /* value32 = ODM_GetBBReg(pDM_Odm, 0xf2c ,bMaskDWord);*/ - vRX_BW = (u1Byte)(value32 & 0x03); - vrsv = (u1Byte)(value32 & 0x04); - vstbc = (u1Byte)(value32 & 0x08); - vgid = (u1Byte)((value32 & 0x3f0) >> 4); - vNsts = (u1Byte)(((value32 & 0x1c00) >> 8) + 1); - vpaid = (u2Byte)(value32 & 0x3fe); - vtxops = (u1Byte)((value32 & 0x400000) >> 20); - vrsv2 = (u1Byte)((value32 & 0x800000) >> 20); + /* value32 = odm_get_bb_reg(p_dm_odm, 0xf2c,MASKDWORD);*/ + v_rx_bw = (u8)(value32 & 0x03); + vrsv = (u8)(value32 & 0x04); + vstbc = (u8)(value32 & 0x08); + vgid = (u8)((value32 & 0x3f0) >> 4); + v_nsts = (u8)(((value32 & 0x1c00) >> 8) + 1); + vpaid = (u16)(value32 & 0x3fe); + vtxops = (u8)((value32 & 0x400000) >> 20); + vrsv2 = (u8)((value32 & 0x800000) >> 20); } PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-A1")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x", "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", vRX_BW, vrsv, vstbc, vgid, vNsts, vpaid, vtxops, vrsv2)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x", "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw, vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2)); - value32 = ODM_GetBBReg(pDM_Odm, 0xf30 , bMaskDWord); /*VHT SIG*/ + value32 = odm_get_bb_reg(p_dm_odm, 0xf30, MASKDWORD); /*VHT SIG*/ if (RX_HT == 2) { - /*value32 = ODM_GetBBReg(pDM_Odm, 0xf30 ,bMaskDWord); */ /*VHT SIG*/ + /*value32 = odm_get_bb_reg(p_dm_odm, 0xf30,MASKDWORD); */ /*VHT SIG*/ - //sgi=(u1Byte)(value32&0x01); - sgiext = (u1Byte)(value32 & 0x03); - //fec = (u1Byte)(value32&0x04); - fecext = (u1Byte)(value32 & 0x0C); + /* sgi=(u8)(value32&0x01); */ + sgiext = (u8)(value32 & 0x03); + /* fec = (u8)(value32&0x04); */ + fecext = (u8)(value32 & 0x0C); - vMCSS = (u1Byte)(value32 & 0xf0); - bf = (u1Byte)((value32 & 0x100) >> 8); - vrsv = (u1Byte)((value32 & 0x200) >> 8); - vhtcrc8 = (u2Byte)((value32 & 0x3fc00) >> 8); - vTail = (u1Byte)((value32 & 0xfc0000) >> 16); + v_mcss = (u8)(value32 & 0xf0); + bf = (u8)((value32 & 0x100) >> 8); + vrsv = (u8)((value32 & 0x200) >> 8); + vhtcrc8 = (u16)((value32 & 0x3fc00) >> 8); + v_tail = (u8)((value32 & 0xfc0000) >> 16); } PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-A2")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x", "SGI/FEC/MCS/BF/Rsv/CRC/Tail", sgiext, fecext, vMCSS, bf, vrsv, vhtcrc8, vTail)); - - value32 = ODM_GetBBReg(pDM_Odm, 0xf34 , bMaskDWord); /*VHT SIG*/ + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x", "SGI/FEC/MCS/BF/Rsv/CRC/tail", sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail)); + + value32 = odm_get_bb_reg(p_dm_odm, 0xf34, MASKDWORD); /*VHT SIG*/ { - vLength = (u2Byte)(value32 & 0x1fffff); - vbrsv = (u1Byte)((value32 & 0x600000) >> 20); - vbTail = (u2Byte)((value32 & 0x1f800000) >> 20); - vbcrc = (u1Byte)((value32 & 0x80000000) >> 28); + v_length = (u16)(value32 & 0x1fffff); + vbrsv = (u8)((value32 & 0x600000) >> 20); + vb_tail = (u16)((value32 & 0x1f800000) >> 20); + vbcrc = (u8)((value32 & 0x80000000) >> 28); } PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-B")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x", "Length/Rsv/Tail/CRC", vLength, vbrsv, vbTail, vbcrc)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x", "length/Rsv/tail/CRC", v_length, vbrsv, vb_tail, vbcrc)); /*for Condition number*/ - if (pDM_Odm->SupportICType & ODM_RTL8822B) { - s4Byte condition_num = 0; + if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + s32 condition_num = 0; char *factor = NULL; - - ODM_SetBBReg(pDM_Odm, 0x1988 , BIT22, 0x1); /*enable report condition number*/ - condition_num = ODM_GetBBReg(pDM_Odm, 0xf84, bMaskDWord); + odm_set_bb_reg(p_dm_odm, 0x1988, BIT(22), 0x1); /*enable report condition number*/ + + condition_num = odm_get_bb_reg(p_dm_odm, 0xf84, MASKDWORD); condition_num = (condition_num & 0x3ffff) >> 4; - if (*pDM_Odm->pBandWidth == ODM_BW80M) + if (*p_dm_odm->p_band_width == ODM_BW80M) factor = "256/234"; - else if (*pDM_Odm->pBandWidth == ODM_BW40M) + else if (*p_dm_odm->p_band_width == ODM_BW40M) factor = "128/108"; - else if (*pDM_Odm->pBandWidth == ODM_BW20M) { + else if (*p_dm_odm->p_band_width == ODM_BW20M) { if (RX_HT != 2 || RX_HT != 1) factor = "64/52"; /*HT or VHT*/ else factor = "64/48"; /*legacy*/ } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d (factor = %s)", "Condition Number", condition_num, factor)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d (factor = %s)", "Condition number", condition_num, factor)); } + *_used = used; + *_out_len = out_len; } +#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#if CONFIG_PHYDM_DEBUG_FUNCTION void phydm_sbd_check( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ) { - static u4Byte pkt_cnt = 0; - static BOOLEAN sbd_state = 0; - u4Byte sym_count, count, value32; + static u32 pkt_cnt = 0; + static boolean sbd_state = 0; + u32 sym_count, count, value32; if (sbd_state == 0) { pkt_cnt++; if (pkt_cnt % 5 == 0) { /*read SBD conter once every 5 packets*/ - ODM_SetTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer, 0); /*ms*/ + odm_set_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer, 0); /*ms*/ sbd_state = 1; } } else { /*read counter*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xF98, bMaskDWord); + value32 = odm_get_bb_reg(p_dm_odm, 0xF98, MASKDWORD); sym_count = (value32 & 0x7C000000) >> 26; count = (value32 & 0x3F00000) >> 20; - DbgPrint("#SBD# sym_count %d count %d\n", sym_count, count); + dbg_print("#SBD# sym_count %d count %d\n", sym_count, count); sbd_state = 0; } } +#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ void phydm_sbd_callback( - PRT_TIMER pTimer + struct timer_list *p_timer ) { - PADAPTER Adapter = (PADAPTER)pTimer->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#if CONFIG_PHYDM_DEBUG_FUNCTION + struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; #if USE_WORKITEM - ODM_ScheduleWorkItem(&pDM_Odm->sbdcnt_workitem); + odm_schedule_work_item(&p_dm_odm->sbdcnt_workitem); #else - phydm_sbd_check(pDM_Odm); + phydm_sbd_check(p_dm_odm); #endif +#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ } void phydm_sbd_workitem_callback( - IN PVOID pContext + void *p_context ) { - PADAPTER pAdapter = (PADAPTER)pContext; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#if CONFIG_PHYDM_DEBUG_FUNCTION + struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - phydm_sbd_check(pDM_Odm); + phydm_sbd_check(p_dm_odm); +#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ } #endif -VOID -phydm_BasicDbgMessage + +void +phydm_rx_rate_distribution +( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _odm_phy_dbg_info_ *p_dbg = &(p_dm_odm->phy_dbg_info); + u8 i = 0, j = 0; + u8 rate_num = 1, rate_ss_shift = 0; + + if (p_dm_odm->support_ic_type & ODM_IC_4SS) + rate_num = 4; + else if (p_dm_odm->support_ic_type & ODM_IC_3SS) + rate_num = 3; + else if (p_dm_odm->support_ic_type & ODM_IC_2SS) + rate_num = 2; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[RxRate Cnt] =============> \n")); + + /*======CCK=============================================================*/ + if (*(p_dm_odm->p_channel) <= 14) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* CCK = {%d, %d, %d, %d}\n", + p_dbg->num_qry_legacy_pkt[0], + p_dbg->num_qry_legacy_pkt[1], + p_dbg->num_qry_legacy_pkt[2], + p_dbg->num_qry_legacy_pkt[3] + )); + } + /*======OFDM============================================================*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + p_dbg->num_qry_legacy_pkt[4], p_dbg->num_qry_legacy_pkt[5], + p_dbg->num_qry_legacy_pkt[6], p_dbg->num_qry_legacy_pkt[7], + p_dbg->num_qry_legacy_pkt[8], p_dbg->num_qry_legacy_pkt[9], + p_dbg->num_qry_legacy_pkt[10], p_dbg->num_qry_legacy_pkt[11])); + + for (j = 0; j < 11; j++) { + p_dbg->num_qry_legacy_pkt[j] = 0; + } + + /*======HT==============================================================*/ + if (p_dbg->ht_pkt_not_zero) { + + for (i = 0; i < rate_num; i++) { + + rate_ss_shift = (i << 3); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (rate_ss_shift), (rate_ss_shift+7), + p_dbg->num_qry_ht_pkt[rate_ss_shift + 0], p_dbg->num_qry_ht_pkt[rate_ss_shift + 1], + p_dbg->num_qry_ht_pkt[rate_ss_shift + 2], p_dbg->num_qry_ht_pkt[rate_ss_shift + 3], + p_dbg->num_qry_ht_pkt[rate_ss_shift + 4], p_dbg->num_qry_ht_pkt[rate_ss_shift + 5], + p_dbg->num_qry_ht_pkt[rate_ss_shift + 6], p_dbg->num_qry_ht_pkt[rate_ss_shift + 7])); + + for (j = 0; j < 8; j++) { + p_dbg->num_qry_ht_pkt[rate_ss_shift + j] = 0; + } + p_dbg->ht_pkt_not_zero = false; + } + } + +#if ODM_IC_11AC_SERIES_SUPPORT + /*======VHT=============================================================*/ + if (p_dbg->vht_pkt_not_zero){ + + for (i = 0; i < rate_num; i++) { + + rate_ss_shift = 10 * i; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + p_dbg->num_qry_vht_pkt[rate_ss_shift + 0], p_dbg->num_qry_vht_pkt[rate_ss_shift + 1], + p_dbg->num_qry_vht_pkt[rate_ss_shift + 2], p_dbg->num_qry_vht_pkt[rate_ss_shift + 3], + p_dbg->num_qry_vht_pkt[rate_ss_shift + 4], p_dbg->num_qry_vht_pkt[rate_ss_shift + 5], + p_dbg->num_qry_vht_pkt[rate_ss_shift + 6], p_dbg->num_qry_vht_pkt[rate_ss_shift + 7], + p_dbg->num_qry_vht_pkt[rate_ss_shift + 8], p_dbg->num_qry_vht_pkt[rate_ss_shift + 9])); + + for (j = 0; j < 10; j++) { + p_dbg->num_qry_vht_pkt[rate_ss_shift + j] = 0; + } + p_dbg->vht_pkt_not_zero = false; + } + } +#endif + +} + +void +phydm_show_avg_rssi ( - IN PVOID pDM_VOID + void *p_dm_void ) { -#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(pDM_Odm , PHYDM_FALSEALMCNT); - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u2Byte macid, phydm_macid, client_cnt = 0; - PSTA_INFO_T pEntry; - s4Byte ret_val = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _odm_phy_dbg_info_ *p_dbg = &(p_dm_odm->phy_dbg_info); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[Avg RSSI] ==============> \n")); + + p_dbg->rssi_cck_avg = (u8)((p_dbg->rssi_cck_cnt != 0) ? (p_dbg->rssi_cck_sum/p_dbg->rssi_cck_cnt) : 0); + p_dbg->rssi_ofdm_avg = (u8)((p_dbg->rssi_ofdm_cnt != 0) ? (p_dbg->rssi_ofdm_sum/p_dbg->rssi_ofdm_cnt) : 0); + p_dbg->rssi_1ss_avg = (u8)((p_dbg->rssi_1ss_cnt != 0) ? (p_dbg->rssi_1ss_sum/p_dbg->rssi_1ss_cnt) : 0); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[PHYDM Common MSG]-------------->\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* cck Cnt= ((%d)) avg_RSSI:{%d}\n", p_dbg->rssi_cck_cnt, p_dbg->rssi_cck_avg)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* ofdm Cnt= ((%d)) avg_RSSI:{%d}\n", p_dbg->rssi_ofdm_cnt, p_dbg->rssi_ofdm_avg)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* 1-ss Cnt= ((%d)) avg_RSSI:{%d}\n", p_dbg->rssi_1ss_cnt, p_dbg->rssi_1ss_avg)); + + if (p_dm_odm->support_ic_type & (ODM_IC_2SS |ODM_IC_3SS |ODM_IC_4SS)) { + + p_dbg->rssi_2ss_avg[0] = (u8)((p_dbg->rssi_2ss_cnt != 0) ? (p_dbg->rssi_2ss_sum[0] /p_dbg->rssi_2ss_cnt) : 0); + p_dbg->rssi_2ss_avg[1] = (u8)((p_dbg->rssi_2ss_cnt != 0) ? (p_dbg->rssi_2ss_sum[1] /p_dbg->rssi_2ss_cnt) : 0); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* 2-ss Cnt= ((%d)) avg_RSSI:{%d, %d}\n", + p_dbg->rssi_2ss_cnt, p_dbg->rssi_2ss_avg[0], p_dbg->rssi_2ss_avg[1])); + } + if (p_dm_odm->support_ic_type & (ODM_IC_3SS |ODM_IC_4SS)) { - if (pDM_Odm->bLinked) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Curr_STA_ID = 0x%x\n", pDM_Odm->curr_station_id)); + p_dbg->rssi_3ss_avg[0] = (u8)((p_dbg->rssi_3ss_cnt != 0) ? (p_dbg->rssi_3ss_sum[0] /p_dbg->rssi_3ss_cnt) : 0); + p_dbg->rssi_3ss_avg[1] = (u8)((p_dbg->rssi_3ss_cnt != 0) ? (p_dbg->rssi_3ss_sum[1] /p_dbg->rssi_3ss_cnt) : 0); + p_dbg->rssi_3ss_avg[2] = (u8)((p_dbg->rssi_3ss_cnt != 0) ? (p_dbg->rssi_3ss_sum[2] /p_dbg->rssi_3ss_cnt) : 0); - /*Print RX Rate*/ - if (pDM_Odm->RxRate <= ODM_RATE11M) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCK AGC Report] LNA_idx = 0x%x, VGA_idx = 0x%x\n", - pDM_Odm->cck_lna_idx, pDM_Odm->cck_vga_idx)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* 3-ss Cnt= ((%d)) avg_RSSI:{%d, %d, %d}\n", + p_dbg->rssi_3ss_cnt, p_dbg->rssi_3ss_avg[0], p_dbg->rssi_3ss_avg[1], p_dbg->rssi_3ss_avg[2])); + } + if (p_dm_odm->support_ic_type & ODM_IC_4SS) { + + p_dbg->rssi_4ss_avg[0] = (u8)((p_dbg->rssi_4ss_cnt != 0) ? (p_dbg->rssi_4ss_sum[0] /p_dbg->rssi_4ss_cnt) : 0); + p_dbg->rssi_4ss_avg[1] = (u8)((p_dbg->rssi_4ss_cnt != 0) ? (p_dbg->rssi_4ss_sum[1] /p_dbg->rssi_4ss_cnt) : 0); + p_dbg->rssi_4ss_avg[2] = (u8)((p_dbg->rssi_4ss_cnt != 0) ? (p_dbg->rssi_4ss_sum[2] /p_dbg->rssi_4ss_cnt) : 0); + p_dbg->rssi_4ss_avg[3] = (u8)((p_dbg->rssi_4ss_cnt != 0) ? (p_dbg->rssi_4ss_sum[3] /p_dbg->rssi_4ss_cnt) : 0); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* 4-ss Cnt= ((%d)) avg_RSSI:{%d, %d, %d, %d}\n", + p_dbg->rssi_4ss_cnt, p_dbg->rssi_4ss_avg[0], p_dbg->rssi_4ss_avg[1], p_dbg->rssi_4ss_avg[2], p_dbg->rssi_4ss_avg[3])); + } + + phydm_reset_avg_rssi_for_ss(p_dm_odm); +} + +void +phydm_basic_dbg_message +( + void *p_dm_void +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u16 macid, phydm_macid, client_cnt = 0; + struct sta_info *p_entry; + s32 tmp_val = 0; + u8 tmp_val_u1 = 0; + + if (!(ODM_COMP_COMMON & p_dm_odm->debug_components)) + return; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[PHYDM Common MSG] System up time: ((%d sec))----->\n", p_dm_odm->phydm_sys_up_time)); + + if (p_dm_odm->is_linked) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ID=((%d)), BW=((%d)), CH=((%d))\n", p_dm_odm->curr_station_id, 20<<(*(p_dm_odm->p_band_width)), *(p_dm_odm->p_channel))); + + + if ((p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) || p_dm_odm->rx_rate > ODM_RATE11M) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}\n", + p_dm_odm->ofdm_agc_idx[0], p_dm_odm->ofdm_agc_idx[1], p_dm_odm->ofdm_agc_idx[2], p_dm_odm->ofdm_agc_idx[3])); } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM AGC Report] { 0x%x, 0x%x, 0x%x, 0x%x }\n", - pDM_Odm->ofdm_agc_idx[0], pDM_Odm->ofdm_agc_idx[1], pDM_Odm->ofdm_agc_idx[2], pDM_Odm->ofdm_agc_idx[3])); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCK AGC Idx] {LNA, VGA}={0x%x, 0x%x}\n", + p_dm_odm->cck_lna_idx, p_dm_odm->cck_vga_idx)); } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI: { %d, %d, %d, %d }, RxRate:", - (pDM_Odm->RSSI_A == 0xff) ? 0 : pDM_Odm->RSSI_A , - (pDM_Odm->RSSI_B == 0xff) ? 0 : pDM_Odm->RSSI_B , - (pDM_Odm->RSSI_C == 0xff) ? 0 : pDM_Odm->RSSI_C, - (pDM_Odm->RSSI_D == 0xff) ? 0 : pDM_Odm->RSSI_D)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI:{%d, %d, %d, %d}, RxRate:", + (p_dm_odm->RSSI_A == 0xff) ? 0 : p_dm_odm->RSSI_A, + (p_dm_odm->RSSI_B == 0xff) ? 0 : p_dm_odm->RSSI_B, + (p_dm_odm->RSSI_C == 0xff) ? 0 : p_dm_odm->RSSI_C, + (p_dm_odm->RSSI_D == 0xff) ? 0 : p_dm_odm->RSSI_D)); - phydm_print_rate(pDM_Odm, pDM_Odm->RxRate, ODM_COMP_COMMON); - - /*Print TX Rate*/ + phydm_print_rate(p_dm_odm, p_dm_odm->rx_rate, ODM_COMP_COMMON); + + phydm_rx_rate_distribution(p_dm_odm); + phydm_show_avg_rssi(p_dm_odm); + + /*Print TX rate*/ for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { - - pEntry = pDM_Odm->pODM_StaInfo[macid]; - if (IS_STA_VALID(pEntry)) { - - phydm_macid = (pDM_Odm->platform2phydm_macid_table[macid]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TXRate [%d]:", macid)); - phydm_print_rate(pDM_Odm, pRA_Table->link_tx_rate[macid], ODM_COMP_COMMON); - - client_cnt++; - - if (client_cnt == pDM_Odm->number_linked_client) - break; + + p_entry = p_dm_odm->p_odm_sta_info[macid]; + if (!IS_STA_VALID(p_entry)) { + continue; } + + phydm_macid = (p_dm_odm->platform2phydm_macid_table[macid]); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TxRate[%d]:", macid)); + phydm_print_rate(p_dm_odm, p_ra_table->link_tx_rate[macid], ODM_COMP_COMMON); + + client_cnt++; + + if (client_cnt >= p_dm_odm->number_linked_client) + break; } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TP { TX, RX, total} = {%d, %d, %d }Mbps, TrafficLoad = (%d))\n", - pDM_Odm->tx_tp, pDM_Odm->rx_tp, pDM_Odm->total_tp, pDM_Odm->TrafficLoad)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))\n", + p_dm_odm->tx_tp, p_dm_odm->rx_tp, p_dm_odm->total_tp, p_dm_odm->traffic_load)); + + tmp_val_u1 = (p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) ? (p_cfo_track->crystal_cap - p_cfo_track->def_x_cap) : (p_cfo_track->def_x_cap - p_cfo_track->crystal_cap); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CFO_avg = ((%d kHz)) , CFO_tracking = ((%s%d))\n", + p_cfo_track->CFO_ave_pre, ((p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) ? "+" : "-"), tmp_val_u1)); /* Condition number */ - if (pDM_Odm->SupportICType == ODM_RTL8822B) { -#if (RTL8822B_SUPPORT == 1) - ret_val = phydm_get_condition_number_8822B(pDM_Odm); -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Condition number = %d\n", ret_val)); + #if (RTL8822B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + tmp_val = phydm_get_condition_number_8822B(p_dm_odm); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Condi_Num=((%d))\n", tmp_val)); } - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("No Link !!!\n")); - } + #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - FalseAlmCnt->Cnt_CCK_CCA, FalseAlmCnt->Cnt_OFDM_CCA, FalseAlmCnt->Cnt_CCA_all)); + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + /*STBC or LDPC pkt*/ + if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Coding: LDPC=((%s)), STBC=((%s))\n", (p_dm_odm->phy_dbg_info.is_ldpc_pkt) ? "Y" : "N", (p_dm_odm->phy_dbg_info.is_stbc_pkt) ? "Y" : "N")); + #endif + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("No Link !!!\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_all)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n", - FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal, FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail, FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked = %d, Num_client = %d, RSSI_Min = %d, CurrentIGI = 0x%x, bNoisy=%d\n\n", - pDM_Odm->bLinked, pDM_Odm->number_linked_client, pDM_Odm->RSSI_Min, pDM_DigTable->CurIGValue, pDM_Odm->NoisyDecision)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all)); -/* - temp_reg = ODM_GetBBReg(pDM_Odm, 0xDD0, bMaskByte0); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xDD0 = 0x%x\n",temp_reg)); - - temp_reg = ODM_GetBBReg(pDM_Odm, 0xDDc, bMaskByte1); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xDDD = 0x%x\n",temp_reg)); - - temp_reg = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskByte0); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xC50 = 0x%x\n",temp_reg)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all)); + + #if (ODM_IC_11N_SERIES_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n", + false_alm_cnt->cnt_parity_fail, false_alm_cnt->cnt_rate_illegal, false_alm_cnt->cnt_crc8_fail, false_alm_cnt->cnt_mcs_fail, false_alm_cnt->cnt_fast_fsync, false_alm_cnt->cnt_sb_search_fail)); + } + #endif - temp_reg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, 0x3fe0); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RF 0x0[13:5] = 0x%x\n\n",temp_reg)); -*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\n\n", + p_dm_odm->is_linked, p_dm_odm->number_linked_client, p_dm_odm->rssi_min, p_dm_dig_table->cur_ig_value, p_dm_odm->noisy_decision)); #endif } -VOID phydm_BasicProfile( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len +void phydm_basic_profile( + void *p_dm_void, + u32 *_used, + char *output, + u32 *_out_len ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - char *Cut = NULL; - char *ICType = NULL; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - u4Byte commit_ver = 0; - u4Byte date = 0; +#if CONFIG_PHYDM_DEBUG_FUNCTION + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + char *cut = NULL; + char *ic_type = NULL; + u32 used = *_used; + u32 out_len = *_out_len; + u32 date = 0; char *commit_by = NULL; - u4Byte release_ver = 0; + u32 release_ver = 0; PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% Basic Profile %")); - if (pDM_Odm->SupportICType == ODM_RTL8188E) { - #if (RTL8188E_SUPPORT == 1) - ICType = "RTL8188E"; + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + ic_type = "RTL8188E"; date = RELEASE_DATE_8188E; commit_by = COMMIT_BY_8188E; release_ver = RELEASE_VERSION_8188E; - #endif +#endif } - #if (RTL8812A_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8812) { - ICType = "RTL8812A"; +#if (RTL8812A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8812) { + ic_type = "RTL8812A"; date = RELEASE_DATE_8812A; commit_by = COMMIT_BY_8812A; release_ver = RELEASE_VERSION_8812A; } - #endif - #if (RTL8821A_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8821) { - ICType = "RTL8821A"; +#endif +#if (RTL8821A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8821) { + ic_type = "RTL8821A"; date = RELEASE_DATE_8821A; commit_by = COMMIT_BY_8821A; release_ver = RELEASE_VERSION_8821A; } - #endif - #if (RTL8192E_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8192E) { - ICType = "RTL8192E"; +#endif +#if (RTL8192E_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + ic_type = "RTL8192E"; date = RELEASE_DATE_8192E; commit_by = COMMIT_BY_8192E; release_ver = RELEASE_VERSION_8192E; } - #endif - #if (RTL8723B_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8723B) { - ICType = "RTL8723B"; +#endif +#if (RTL8723B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + ic_type = "RTL8723B"; date = RELEASE_DATE_8723B; commit_by = COMMIT_BY_8723B; release_ver = RELEASE_VERSION_8723B; } - #endif - #if (RTL8814A_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8814A) { - ICType = "RTL8814A"; +#endif +#if (RTL8814A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8814A) { + ic_type = "RTL8814A"; date = RELEASE_DATE_8814A; commit_by = COMMIT_BY_8814A; release_ver = RELEASE_VERSION_8814A; } - #endif - #if (RTL8881A_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8881A) { - ICType = "RTL8881A"; +#endif +#if (RTL8881A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8881A) { + ic_type = "RTL8881A"; /**/ } - #endif - #if (RTL8822B_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8822B) { - ICType = "RTL8822B"; +#endif +#if (RTL8822B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + ic_type = "RTL8822B"; date = RELEASE_DATE_8822B; commit_by = COMMIT_BY_8822B; release_ver = RELEASE_VERSION_8822B; } - #endif - #if (RTL8197F_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8197F) { - ICType = "RTL8197F"; +#endif +#if (RTL8197F_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8197F) { + ic_type = "RTL8197F"; date = RELEASE_DATE_8197F; commit_by = COMMIT_BY_8197F; release_ver = RELEASE_VERSION_8197F; } - #endif +#endif - #if (RTL8703B_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8703B) { - - ICType = "RTL8703B"; +#if (RTL8703B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8703B) { + + ic_type = "RTL8703B"; date = RELEASE_DATE_8703B; commit_by = COMMIT_BY_8703B; release_ver = RELEASE_VERSION_8703B; - - } - #endif - #if (RTL8195A_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8195A) { - ICType = "RTL8195A"; - /**/ + } - #endif - #if (RTL8188F_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8188F) { - ICType = "RTL8188F"; +#endif +#if (RTL8195A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8195A) { + ic_type = "RTL8195A"; + /**/ + } +#endif +#if (RTL8188F_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + ic_type = "RTL8188F"; date = RELEASE_DATE_8188F; commit_by = COMMIT_BY_8188F; release_ver = RELEASE_VERSION_8188F; } - #endif - #if (RTL8723D_SUPPORT == 1) - else if (pDM_Odm->SupportICType == ODM_RTL8723D) { - ICType = "RTL8723D"; - /**/ +#endif +#if (RTL8723D_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + ic_type = "RTL8723D"; + date = RELEASE_DATE_8723D; + commit_by = COMMIT_BY_8723D; + release_ver = RELEASE_VERSION_8723D; + /**/ } - #endif - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s (MP Chip: %s)\n", "IC Type", ICType, pDM_Odm->bIsMPChip ? "Yes" : "No")); - - if (pDM_Odm->CutVersion == ODM_CUT_A) - Cut = "A"; - else if (pDM_Odm->CutVersion == ODM_CUT_B) - Cut = "B"; - else if (pDM_Odm->CutVersion == ODM_CUT_C) - Cut = "C"; - else if (pDM_Odm->CutVersion == ODM_CUT_D) - Cut = "D"; - else if (pDM_Odm->CutVersion == ODM_CUT_E) - Cut = "E"; - else if (pDM_Odm->CutVersion == ODM_CUT_F) - Cut = "F"; - else if (pDM_Odm->CutVersion == ODM_CUT_I) - Cut = "I"; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Cut Version", Cut)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Version", ODM_GetHWImgVersion(pDM_Odm))); +#endif + +/* JJ ADD 20161014 */ +#if (RTL8710B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + ic_type = "RTL8710B"; + date = RELEASE_DATE_8710B; + commit_by = COMMIT_BY_8710B; + release_ver = RELEASE_VERSION_8710B; + /**/ + } +#endif + +#if (RTL8821C_SUPPORT == 1) + else if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + ic_type = "RTL8821C"; + date = RELEASE_DATE_8821C; + commit_by = COMMIT_BY_8821C; + release_ver = RELEASE_VERSION_8821C; + } +#endif + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s (MP Chip: %s)\n", "IC type", ic_type, p_dm_odm->is_mp_chip ? "Yes" : "No")); + + if (p_dm_odm->cut_version == ODM_CUT_A) + cut = "A"; + else if (p_dm_odm->cut_version == ODM_CUT_B) + cut = "B"; + else if (p_dm_odm->cut_version == ODM_CUT_C) + cut = "C"; + else if (p_dm_odm->cut_version == ODM_CUT_D) + cut = "D"; + else if (p_dm_odm->cut_version == ODM_CUT_E) + cut = "E"; + else if (p_dm_odm->cut_version == ODM_CUT_F) + cut = "F"; + else if (p_dm_odm->cut_version == ODM_CUT_I) + cut = "I"; + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "cut version", cut)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter version", odm_get_hw_img_version(p_dm_odm))); PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Commit date", date)); PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY Parameter Commit by", commit_by)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Release Version", release_ver)); - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Release version", release_ver)); + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) { - PADAPTER Adapter = pDM_Odm->Adapter; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW Version", Adapter->MgntInfo.FirmwareVersion, Adapter->MgntInfo.FirmwareSubVersion)); + struct _ADAPTER *adapter = p_dm_odm->adapter; + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", adapter->MgntInfo.FirmwareVersion, adapter->MgntInfo.FirmwareSubVersion)); } #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) { - struct rtl8192cd_priv *priv = pDM_Odm->priv; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW Version", priv->pshare->fw_version, priv->pshare->fw_sub_version)); + struct rtl8192cd_priv *priv = p_dm_odm->priv; + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", priv->pshare->fw_version, priv->pshare->fw_sub_version)); + } +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + { + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_hal *rtlhal = rtl_hal(rtlpriv); + + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", rtlhal->fw_version, rtlhal->fw_subversion)); } #else { - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW Version", pHalData->FirmwareVersion, pHalData->FirmwareSubVersion)); + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", p_hal_data->firmware_version, p_hal_data->firmware_sub_version)); } #endif - //1 PHY DM Version List - PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% PHYDM Version %")); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Code Base", PHYDM_CODE_BASE)); + /* 1 PHY DM version List */ + PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% PHYDM version %")); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Code base", PHYDM_CODE_BASE)); PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Release Date", PHYDM_RELEASE_DATE)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Adaptivity", ADAPTIVITY_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "adaptivity", ADAPTIVITY_VERSION)); PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "DIG", DIG_VERSION)); PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic BB PowerSaving", DYNAMIC_BBPWRSAV_VERSION)); PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "CFO Tracking", CFO_TRACKING_VERSION)); PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Diversity", ANTDIV_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Power Tracking", POWRTRACKING_VERSION)); PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic TxPower", DYNAMIC_TXPWR_VERSION)); PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "RA Info", RAINFO_VERSION)); -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Detection", ANTDECT_VERSION)); #endif - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Auto Channel Selection", ACS_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "EDCA Turbo", EDCATURBO_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Path Diversity", PATHDIV_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Auto channel Selection", ACS_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "path Diversity", PATHDIV_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "LA mode", DYNAMIC_LA_MODE)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic RX path", DYNAMIC_RX_PATH_VERSION)); -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8822B) +#if (RTL8822B_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8822B) PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8822B", PHY_CONFIG_VERSION_8822B)); - + #endif -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) +#if (RTL8197F_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8197F) PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8197F", PHY_CONFIG_VERSION_8197F)); #endif *_used = used; *_out_len = out_len; - +#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ } -VOID +#if CONFIG_PHYDM_DEBUG_FUNCTION +void phydm_fw_trace_en_h2c( - IN PVOID pDM_VOID, - IN BOOLEAN enable, - IN u4Byte monitor_mode, - IN u4Byte macid + void *p_dm_void, + boolean enable, + u32 fw_debug_component, + u32 monitor_mode, + u32 macid ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte H2C_Parameter[3] = {0}; - - H2C_Parameter[0] = enable; - H2C_Parameter[1] = (u1Byte)monitor_mode; - H2C_Parameter[2] = (u1Byte)macid; - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("---->\n")); - if (monitor_mode == 0){ - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d ))\n", enable)); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 h2c_parameter[7] = {0}; + u8 cmd_length; + + if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { + + h2c_parameter[0] = enable; + h2c_parameter[1] = (u8)(fw_debug_component & MASKBYTE0); + h2c_parameter[2] = (u8)((fw_debug_component & MASKBYTE1) >> 8); + h2c_parameter[3] = (u8)((fw_debug_component & MASKBYTE2) >> 16); + h2c_parameter[4] = (u8)((fw_debug_component & MASKBYTE3) >> 24); + h2c_parameter[5] = (u8)monitor_mode; + h2c_parameter[6] = (u8)macid; + cmd_length = 7; + } else { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n", enable, monitor_mode, macid)); + + h2c_parameter[0] = enable; + h2c_parameter[1] = (u8)monitor_mode; + h2c_parameter[2] = (u8)macid; + cmd_length = 3; } - ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_FW_TRACE_EN, 3, H2C_Parameter); + + + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("---->\n")); + if (monitor_mode == 0) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d ))\n", enable)); + else + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n", enable, monitor_mode, macid)); + odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter); } #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) -BOOLEAN +boolean phydm_api_set_txagc( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate, - IN BOOLEAN bSingleRate - ) + struct PHY_DM_STRUCT *p_dm_odm, + u32 power_index, + enum odm_rf_radio_path_e path, + u8 hw_rate, + boolean is_single_rate +) { - BOOLEAN ret = FALSE; - + boolean ret = false; + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + u8 i; + #endif + #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8821C)) { - if (bSingleRate) { + if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + if (is_single_rate) { #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) - ret = phydm_write_txagc_1byte_8822b(pDM_Odm, PowerIndex, Path, HwRate); + if (p_dm_odm->support_ic_type == ODM_RTL8822B) + ret = phydm_write_txagc_1byte_8822b(p_dm_odm, power_index, path, hw_rate); #endif #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - ret = phydm_write_txagc_1byte_8821c(pDM_Odm, PowerIndex, Path, HwRate); + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + ret = phydm_write_txagc_1byte_8821c(p_dm_odm, power_index, path, hw_rate); #endif #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - SetCurrentTxAGC(pDM_Odm->priv, Path, HwRate, (u1Byte)PowerIndex); + set_current_tx_agc(p_dm_odm->priv, path, hw_rate, (u8)power_index); #endif } else { - u1Byte i; + #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) - ret = config_phydm_write_txagc_8822b(pDM_Odm, PowerIndex, Path, HwRate); + if (p_dm_odm->support_ic_type == ODM_RTL8822B) + ret = config_phydm_write_txagc_8822b(p_dm_odm, power_index, path, hw_rate); #endif #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - ret = config_phydm_write_txagc_8821c(pDM_Odm, PowerIndex, Path, HwRate); + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + ret = config_phydm_write_txagc_8821c(p_dm_odm, power_index, path, hw_rate); #endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) for (i = 0; i < 4; i++) - SetCurrentTxAGC(pDM_Odm->priv, Path, (HwRate + i), (u1Byte)PowerIndex); + set_current_tx_agc(p_dm_odm->priv, path, (hw_rate + i), (u8)power_index); #endif } } @@ -1113,111 +1598,111 @@ phydm_api_set_txagc( #if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ret = config_phydm_write_txagc_8197f(pDM_Odm, PowerIndex, Path, HwRate); + if (p_dm_odm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_write_txagc_8197f(p_dm_odm, power_index, path, hw_rate); #endif return ret; } -u1Byte +u8 phydm_api_get_txagc( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e path, + u8 hw_rate +) { - u1Byte ret = 0; - + u8 ret = 0; + #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ret = config_phydm_read_txagc_8822b(pDM_Odm, Path, HwRate); + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + ret = config_phydm_read_txagc_8822b(p_dm_odm, path, hw_rate); #endif #if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ret = config_phydm_read_txagc_8197f(pDM_Odm, Path, HwRate); + if (p_dm_odm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_read_txagc_8197f(p_dm_odm, path, hw_rate); #endif #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8821C) - ret = config_phydm_read_txagc_8821c(pDM_Odm, Path, HwRate); + if (p_dm_odm->support_ic_type & ODM_RTL8821C) + ret = config_phydm_read_txagc_8821c(p_dm_odm, path, hw_rate); #endif return ret; } -BOOLEAN +boolean phydm_api_switch_bw_channel( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ) + struct PHY_DM_STRUCT *p_dm_odm, + u8 central_ch, + u8 primary_ch_idx, + enum odm_bw_e bandwidth +) { - BOOLEAN ret = FALSE; - + boolean ret = false; + #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ret = config_phydm_switch_channel_bw_8822b(pDM_Odm, central_ch, primary_ch_idx, bandwidth); + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + ret = config_phydm_switch_channel_bw_8822b(p_dm_odm, central_ch, primary_ch_idx, bandwidth); #endif #if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ret = config_phydm_switch_channel_bw_8197f(pDM_Odm, central_ch, primary_ch_idx, bandwidth); + if (p_dm_odm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_switch_channel_bw_8197f(p_dm_odm, central_ch, primary_ch_idx, bandwidth); #endif #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8821C) - ret = config_phydm_switch_channel_bw_8821c(pDM_Odm, central_ch, primary_ch_idx, bandwidth); + if (p_dm_odm->support_ic_type & ODM_RTL8821C) + ret = config_phydm_switch_channel_bw_8821c(p_dm_odm, central_ch, primary_ch_idx, bandwidth); #endif return ret; } -BOOLEAN +boolean phydm_api_trx_mode( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_PATH_E TxPath, - IN ODM_RF_PATH_E RxPath, - IN BOOLEAN bTx2Path - ) + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_path_e tx_path, + enum odm_rf_path_e rx_path, + boolean is_tx2_path +) { - BOOLEAN ret = FALSE; - + boolean ret = false; + #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ret = config_phydm_trx_mode_8822b(pDM_Odm, TxPath, RxPath, bTx2Path); + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + ret = config_phydm_trx_mode_8822b(p_dm_odm, tx_path, rx_path, is_tx2_path); #endif #if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - ret = config_phydm_trx_mode_8197f(pDM_Odm, TxPath, RxPath, bTx2Path); + if (p_dm_odm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_trx_mode_8197f(p_dm_odm, tx_path, rx_path, is_tx2_path); #endif return ret; } #endif -VOID +void phydm_get_per_path_txagc( - IN PVOID pDM_VOID, - IN u1Byte path, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len + void *p_dm_void, + u8 path, + u32 *_used, + char *output, + u32 *_out_len ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte rate_idx; - u1Byte txagc; - u4Byte used = *_used; - u4Byte out_len = *_out_len; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 rate_idx; + u8 txagc; + u32 used = *_used; + u32 out_len = *_out_len; #if ((RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - if (((pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F)) && (path <= ODM_RF_PATH_B)) || - ((pDM_Odm->SupportICType & (ODM_RTL8821C)) && (path <= ODM_RF_PATH_A))) { + if (((p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) && (path <= ODM_RF_PATH_B)) || + ((p_dm_odm->support_ic_type & (ODM_RTL8821C)) && (path <= ODM_RF_PATH_A))) { for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) { if (rate_idx == ODM_RATE1M) PHYDM_SNPRINTF((output + used, out_len - used, " %-35s\n", "CCK====>")); @@ -1239,8 +1724,8 @@ phydm_get_per_path_txagc( PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 3ss====>")); else if (rate_idx == ODM_RATEVHTSS4MCS0) PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 4ss====>")); - - txagc = phydm_api_get_txagc(pDM_Odm, (ODM_RF_RADIO_PATH_E) path, rate_idx); + + txagc = phydm_api_get_txagc(p_dm_odm, (enum odm_rf_radio_path_e) path, rate_idx); if (config_phydm_read_txagc_check(txagc)) PHYDM_SNPRINTF((output + used, out_len - used, " 0x%02x ", txagc)); else @@ -1251,334 +1736,412 @@ phydm_get_per_path_txagc( } -VOID +void phydm_get_txagc( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len + void *p_dm_void, + u32 *_used, + char *output, + u32 *_out_len ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - /* Path-A */ - PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "Path-A====================")); - phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_A, _used, output, _out_len); - - /* Path-B */ - PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "Path-B====================")); - phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_B, _used, output, _out_len); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + /* path-A */ + PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "path-A====================")); + phydm_get_per_path_txagc(p_dm_odm, ODM_RF_PATH_A, _used, output, _out_len); + + /* path-B */ + PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "path-B====================")); + phydm_get_per_path_txagc(p_dm_odm, ODM_RF_PATH_B, _used, output, _out_len); - /* Path-C */ - PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "Path-C====================")); - phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_C, _used, output, _out_len); + /* path-C */ + PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "path-C====================")); + phydm_get_per_path_txagc(p_dm_odm, ODM_RF_PATH_C, _used, output, _out_len); - /* Path-D */ - PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "Path-D====================")); - phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_D, _used, output, _out_len); + /* path-D */ + PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "path-D====================")); + phydm_get_per_path_txagc(p_dm_odm, ODM_RF_PATH_D, _used, output, _out_len); } -VOID +void phydm_set_txagc( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte used = *_used; - u4Byte out_len = *_out_len; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 used = *_used; + u32 out_len = *_out_len; -/*dm_value[1] = Path*/ -/*dm_value[2] = HwRate*/ -/*dm_value[3] = PowerIndex*/ + /*dm_value[1] = path*/ + /*dm_value[2] = hw_rate*/ + /*dm_value[3] = power_index*/ #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C)) { + if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)) { if (dm_value[1] <= 1) { - if ((u1Byte)dm_value[2] != 0xff) { - if (phydm_api_set_txagc(pDM_Odm, dm_value[3], (ODM_RF_RADIO_PATH_E) dm_value[1], (u1Byte)dm_value[2], TRUE)) + if ((u8)dm_value[2] != 0xff) { + if (phydm_api_set_txagc(p_dm_odm, dm_value[3], (enum odm_rf_radio_path_e) dm_value[1], (u8)dm_value[2], true)) PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s%x\n", "Write path-", dm_value[1], "rate index-0x", dm_value[2], " = 0x", dm_value[3])); else PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s\n", "Write path-", (dm_value[1] & 0x1), "rate index-0x", (dm_value[2] & 0x7f), " fail")); } else { - u1Byte i; - u4Byte power_index; - BOOLEAN status = TRUE; + u8 i; + u32 power_index; + boolean status = true; power_index = (dm_value[3] & 0x3f); - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8821C)) { - power_index = (power_index << 24)|(power_index << 16)|(power_index << 8)|(power_index); + if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + power_index = (power_index << 24) | (power_index << 16) | (power_index << 8) | (power_index); for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4) - status = (status & phydm_api_set_txagc(pDM_Odm, power_index, (ODM_RF_RADIO_PATH_E) dm_value[1], i, FALSE)); - } else if (pDM_Odm->SupportICType & ODM_RTL8197F) { + status = (status & phydm_api_set_txagc(p_dm_odm, power_index, (enum odm_rf_radio_path_e) dm_value[1], i, false)); + } else if (p_dm_odm->support_ic_type & ODM_RTL8197F) { for (i = 0; i <= ODM_RATEMCS15; i++) - status = (status & phydm_api_set_txagc(pDM_Odm, power_index, (ODM_RF_RADIO_PATH_E) dm_value[1], i, FALSE)); + status = (status & phydm_api_set_txagc(p_dm_odm, power_index, (enum odm_rf_radio_path_e) dm_value[1], i, false)); } if (status) PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x\n", "Write all TXAGC of path-", dm_value[1], " = 0x", dm_value[3])); else - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s\n", "Write all TXAGC of path-", dm_value[1], " fail")); + PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s\n", "Write all TXAGC of path-", dm_value[1], " fail")); } - } else { + } else PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s\n", "Write path-", (dm_value[1] & 0x1), "rate index-0x", (dm_value[2] & 0x7f), " fail")); - } } #endif } -VOID -odm_debug_trace( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len +void +phydm_debug_trace( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte pre_debug_components, one = 1; - u4Byte used = *_used; - u4Byte out_len = *_out_len; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 pre_debug_components, one = 1; + u32 used = *_used; + u32 out_len = *_out_len; - pre_debug_components = pDM_Odm->DebugComponents; + pre_debug_components = p_dm_odm->debug_components; PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); if (dm_value[0] == 100) { PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Debug Message] PhyDM Selection")); PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((pDM_Odm->DebugComponents & ODM_COMP_DIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((pDM_Odm->DebugComponents & ODM_COMP_RA_MASK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((pDM_Odm->DebugComponents & ODM_COMP_DYNAMIC_TXPWR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((pDM_Odm->DebugComponents & ODM_COMP_FA_CNT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((pDM_Odm->DebugComponents & ODM_COMP_RSSI_MONITOR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))SNIFFER\n", ((pDM_Odm->DebugComponents & ODM_COMP_SNIFFER) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((pDM_Odm->DebugComponents & ODM_COMP_ANT_DIV) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "07. (( %s ))DFS\n", ((pDM_Odm->DebugComponents & ODM_COMP_DFS) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))NOISY_DETECT\n", ((pDM_Odm->DebugComponents & ODM_COMP_NOISY_DETECT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((pDM_Odm->DebugComponents & ODM_COMP_RATE_ADAPTIVE) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((pDM_Odm->DebugComponents & ODM_COMP_PATH_DIV) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "12. (( %s ))DYNAMIC_PRICCA\n", ((pDM_Odm->DebugComponents & ODM_COMP_DYNAMIC_PRICCA) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))MP\n", ((pDM_Odm->DebugComponents & ODM_COMP_MP) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))CFO_TRACKING\n", ((pDM_Odm->DebugComponents & ODM_COMP_CFO_TRACKING) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))ACS\n", ((pDM_Odm->DebugComponents & ODM_COMP_ACS) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))ADAPTIVITY\n", ((pDM_Odm->DebugComponents & PHYDM_COMP_ADAPTIVITY) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))RA_DBG\n", ((pDM_Odm->DebugComponents & PHYDM_COMP_RA_DBG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "19. (( %s ))TXBF\n", ((pDM_Odm->DebugComponents & PHYDM_COMP_TXBF) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "20. (( %s ))EDCA_TURBO\n", ((pDM_Odm->DebugComponents & ODM_COMP_EDCA_TURBO) ? ("V") : (".")))); - - PHYDM_SNPRINTF((output + used, out_len - used, "22. (( %s ))FW_DEBUG_TRACE\n", ((pDM_Odm->DebugComponents & ODM_FW_DEBUG_TRACE) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "24. (( %s ))TX_PWR_TRACK\n", ((pDM_Odm->DebugComponents & ODM_COMP_TX_PWR_TRACK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "25. (( %s ))RX_GAIN_TRACK\n", ((pDM_Odm->DebugComponents & ODM_COMP_RX_GAIN_TRACK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "26. (( %s ))CALIBRATION\n", ((pDM_Odm->DebugComponents & ODM_COMP_CALIBRATION) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "28. (( %s ))PHY_CONFIG\n", ((pDM_Odm->DebugComponents & ODM_PHY_CONFIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "29. (( %s ))INIT\n", ((pDM_Odm->DebugComponents & ODM_COMP_INIT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "30. (( %s ))COMMON\n", ((pDM_Odm->DebugComponents & ODM_COMP_COMMON) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "31. (( %s ))API\n", ((pDM_Odm->DebugComponents & ODM_COMP_API) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((p_dm_odm->debug_components & ODM_COMP_DIG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((p_dm_odm->debug_components & ODM_COMP_RA_MASK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((p_dm_odm->debug_components & ODM_COMP_DYNAMIC_TXPWR) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((p_dm_odm->debug_components & ODM_COMP_FA_CNT) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((p_dm_odm->debug_components & ODM_COMP_RSSI_MONITOR) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))SNIFFER\n", ((p_dm_odm->debug_components & ODM_COMP_SNIFFER) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((p_dm_odm->debug_components & ODM_COMP_ANT_DIV) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "07. (( %s ))DFS\n", ((p_dm_odm->debug_components & ODM_COMP_DFS) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))NOISY_DETECT\n", ((p_dm_odm->debug_components & ODM_COMP_NOISY_DETECT) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((p_dm_odm->debug_components & ODM_COMP_RATE_ADAPTIVE) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((p_dm_odm->debug_components & ODM_COMP_PATH_DIV) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "12. (( %s ))DYNAMIC_PRICCA\n", ((p_dm_odm->debug_components & ODM_COMP_DYNAMIC_PRICCA) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))MP\n", ((p_dm_odm->debug_components & ODM_COMP_MP) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))CFO_TRACKING\n", ((p_dm_odm->debug_components & ODM_COMP_CFO_TRACKING) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))ACS\n", ((p_dm_odm->debug_components & ODM_COMP_ACS) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))ADAPTIVITY\n", ((p_dm_odm->debug_components & PHYDM_COMP_ADAPTIVITY) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))RA_DBG\n", ((p_dm_odm->debug_components & PHYDM_COMP_RA_DBG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "19. (( %s ))TXBF\n", ((p_dm_odm->debug_components & PHYDM_COMP_TXBF) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "22. (( %s ))FW_DEBUG_TRACE\n", ((p_dm_odm->debug_components & ODM_FW_DEBUG_TRACE) ? ("V") : (".")))); + + PHYDM_SNPRINTF((output + used, out_len - used, "24. (( %s ))TX_PWR_TRACK\n", ((p_dm_odm->debug_components & ODM_COMP_TX_PWR_TRACK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "26. (( %s ))CALIBRATION\n", ((p_dm_odm->debug_components & ODM_COMP_CALIBRATION) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "28. (( %s ))PHY_CONFIG\n", ((p_dm_odm->debug_components & ODM_PHY_CONFIG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "29. (( %s ))INIT\n", ((p_dm_odm->debug_components & ODM_COMP_INIT) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "30. (( %s ))COMMON\n", ((p_dm_odm->debug_components & ODM_COMP_COMMON) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "31. (( %s ))API\n", ((p_dm_odm->debug_components & ODM_COMP_API) ? ("V") : (".")))); PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); } else if (dm_value[0] == 101) { - pDM_Odm->DebugComponents = 0; + p_dm_odm->debug_components = 0; PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Disable all debug components")); } else { - if (dm_value[1] == 1) { /*enable*/ - pDM_Odm->DebugComponents |= (one << dm_value[0]); - - if (dm_value[0] == 22) { /*FW trace function*/ - phydm_fw_trace_en_h2c(pDM_Odm, 1, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ - } - } else if (dm_value[1] == 2) { /*disable*/ - pDM_Odm->DebugComponents &= ~(one << dm_value[0]); - - if (dm_value[0] == 22) { /*FW trace function*/ - phydm_fw_trace_en_h2c(pDM_Odm, 0, dm_value[2], dm_value[3]); /*H2C to disable C2H Msg*/ - } - } else + if (dm_value[1] == 1) /*enable*/ + p_dm_odm->debug_components |= (one << dm_value[0]); + else if (dm_value[1] == 2) /*disable*/ + p_dm_odm->debug_components &= ~(one << dm_value[0]); + else PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); } PHYDM_SNPRINTF((output + used, out_len - used, "pre-DbgComponents = 0x%x\n", pre_debug_components)); - PHYDM_SNPRINTF((output + used, out_len - used, "Curr-DbgComponents = 0x%x\n", pDM_Odm->DebugComponents)); + PHYDM_SNPRINTF((output + used, out_len - used, "Curr-DbgComponents = 0x%x\n", p_dm_odm->debug_components)); PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); } -VOID -phydm_DumpBbReg( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) +void +phydm_fw_debug_trace( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte Addr = 0; - u4Byte used = *_used; - u4Byte out_len = *_out_len; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 pre_fw_debug_components, one = 1; + u32 used = *_used; + u32 out_len = *_out_len; + + pre_fw_debug_components = p_dm_odm->fw_debug_components; + + PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); + if (dm_value[0] == 100) { + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[FW Debug Component]")); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))RA\n", ((p_dm_odm->fw_debug_components & PHYDM_FW_COMP_RA) ? ("V") : (".")))); + + if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { + PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))MU\n", ((p_dm_odm->fw_debug_components & PHYDM_FW_COMP_MU) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))path Div\n", ((p_dm_odm->fw_debug_components & PHYDM_FW_COMP_PHY_CONFIG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))Phy Config\n", ((p_dm_odm->fw_debug_components & PHYDM_FW_COMP_PHY_CONFIG) ? ("V") : (".")))); + } + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + + } else { + if (dm_value[0] == 101) { + p_dm_odm->fw_debug_components = 0; + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Clear all fw debug components")); + } else { + if (dm_value[1] == 1) /*enable*/ + p_dm_odm->fw_debug_components |= (one << dm_value[0]); + else if (dm_value[1] == 2) /*disable*/ + p_dm_odm->fw_debug_components &= ~(one << dm_value[0]); + else + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); + } + + if (p_dm_odm->fw_debug_components == 0) { + p_dm_odm->debug_components &= ~ODM_FW_DEBUG_TRACE; + phydm_fw_trace_en_h2c(p_dm_odm, false, p_dm_odm->fw_debug_components, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ + } else { + p_dm_odm->debug_components |= ODM_FW_DEBUG_TRACE; + phydm_fw_trace_en_h2c(p_dm_odm, true, p_dm_odm->fw_debug_components, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ + } + } +} + +void +phydm_dump_bb_reg( + void *p_dm_void, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 addr = 0; + u32 used = *_used; + u32 out_len = *_out_len; + - /* BB Reg, For Nseries IC we only need to dump page8 to pageF using 3 digits*/ - for (Addr = 0x800; Addr < 0xfff; Addr += 4) { - if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%03x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + for (addr = 0x800; addr < 0xfff; addr += 4) { + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%03x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); else - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); } - if (pDM_Odm->SupportICType & (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C)) { + if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C)) { - if (pDM_Odm->RFType > ODM_2T2R) { - for (Addr = 0x1800; Addr < 0x18ff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + if (p_dm_odm->rf_type > ODM_2T2R) { + for (addr = 0x1800; addr < 0x18ff; addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); } - if (pDM_Odm->RFType > ODM_3T3R) { - for (Addr = 0x1a00; Addr < 0x1aff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + if (p_dm_odm->rf_type > ODM_3T3R) { + for (addr = 0x1a00; addr < 0x1aff; addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); } - for (Addr = 0x1900; Addr < 0x19ff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + for (addr = 0x1900; addr < 0x19ff; addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); - for (Addr = 0x1c00; Addr < 0x1cff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + for (addr = 0x1c00; addr < 0x1cff; addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); - for (Addr = 0x1f00; Addr < 0x1fff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + for (addr = 0x1f00; addr < 0x1fff; addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); } } -VOID -phydm_DumpAllReg( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) +void +phydm_dump_all_reg( + void *p_dm_void, + u32 *_used, + char *output, + u32 *_out_len +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte Addr = 0; - u4Byte used = *_used; - u4Byte out_len = *_out_len; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 addr = 0; + u32 used = *_used; + u32 out_len = *_out_len; /* dump MAC register */ - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "MAC==========\n")); - for (Addr = 0; Addr < 0x7ff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "MAC==========\n")); + for (addr = 0; addr < 0x7ff; addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); - for (Addr = 0x1000; Addr < 0x17ff; Addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%04x 0x%08x,\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord))); + for (addr = 0x1000; addr < 0x17ff; addr += 4) + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); /* dump BB register */ - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "BB==========\n")); - phydm_DumpBbReg(pDM_Odm, &used, output, &out_len); + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "BB==========\n")); + phydm_dump_bb_reg(p_dm_odm, &used, output, &out_len); /* dump RF register */ - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "RF-A==========\n")); - for (Addr = 0; Addr < 0xFF; Addr++) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%02x 0x%05x,\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Addr, bRFRegOffsetMask))); + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "RF-A==========\n")); + for (addr = 0; addr < 0xFF; addr++) + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%02x 0x%05x\n", addr, odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, addr, RFREGOFFSETMASK))); - if (pDM_Odm->RFType > ODM_1T1R) { - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "RF-B==========\n")); - for (Addr = 0; Addr < 0xFF; Addr++) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%02x 0x%05x,\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, Addr, bRFRegOffsetMask))); + if (p_dm_odm->rf_type > ODM_1T1R) { + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "RF-B==========\n")); + for (addr = 0; addr < 0xFF; addr++) + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%02x 0x%05x\n", addr, odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_B, addr, RFREGOFFSETMASK))); } - if (pDM_Odm->RFType > ODM_2T2R) { - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "RF-C==========\n")); - for (Addr = 0; Addr < 0xFF; Addr++) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%02x 0x%05x,\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_C, Addr, bRFRegOffsetMask))); + if (p_dm_odm->rf_type > ODM_2T2R) { + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "RF-C==========\n")); + for (addr = 0; addr < 0xFF; addr++) + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%02x 0x%05x\n", addr, odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_C, addr, RFREGOFFSETMASK))); } - if (pDM_Odm->RFType > ODM_3T3R) { - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "RF-D==========\n")); - for (Addr = 0; Addr < 0xFF; Addr++) - PHYDM_VAST_INFO_SNPRINTF((output+used, out_len-used, "0x%02x 0x%05x,\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_D, Addr, bRFRegOffsetMask))); + if (p_dm_odm->rf_type > ODM_3T3R) { + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "RF-D==========\n")); + for (addr = 0; addr < 0xFF; addr++) + PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%02x 0x%05x\n", addr, odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_D, addr, RFREGOFFSETMASK))); } } -VOID -phydm_EnableBigJump( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN state - ) +void +phydm_enable_big_jump( + struct PHY_DM_STRUCT *p_dm_odm, + boolean state +) { #if (RTL8822B_SUPPORT == 1) - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - if (state == FALSE) { - pDM_Odm->DM_DigTable.enableAdjustBigJump = FALSE; - ODM_SetBBReg(pDM_Odm, 0x8c8, 0xfe, ((pDM_DigTable->bigJumpStep3<<5)|(pDM_DigTable->bigJumpStep2<<3)|pDM_DigTable->bigJumpStep1)); + if (state == false) { + p_dm_odm->dm_dig_table.enable_adjust_big_jump = false; + odm_set_bb_reg(p_dm_odm, 0x8c8, 0xfe, ((p_dm_dig_table->big_jump_step3 << 5) | (p_dm_dig_table->big_jump_step2 << 3) | p_dm_dig_table->big_jump_step1)); } else - pDM_Odm->DM_DigTable.enableAdjustBigJump = TRUE; + p_dm_odm->dm_dig_table.enable_adjust_big_jump = true; #endif } -#if (RTL8822B_SUPPORT == 1) +#if (RTL8822B_SUPPORT == 1 | RTL8821C_SUPPORT == 1 | RTL8814B_SUPPORT == 1) -VOID -phydm_showRxRate( - IN PDM_ODM_T pDM_Odm, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) +void +phydm_show_rx_rate( + struct PHY_DM_STRUCT *p_dm_odm, + u32 *_used, + char *output, + u32 *_out_len +) { - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - PHYDM_SNPRINTF((output+used, out_len-used, "=====Rx SU Rate Statistics=====\n")); - PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[0], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[1], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[2], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[3])); - PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[4], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[5], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[6], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[7])); - PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS8 = %d, 1SS MCS9 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[8], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[9])); - PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[10], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[11], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[12], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[13])); - PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[14], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[15], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[16], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[17])); - PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS8 = %d, 2SS MCS9 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[18], pDM_Odm->PhyDbgInfo.NumQryVhtPkt[19])); - - PHYDM_SNPRINTF((output+used, out_len-used, "=====Rx MU Rate Statistics=====\n")); - PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[0], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[1], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[2], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[3])); - PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[4], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[5], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[6], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[7])); - PHYDM_SNPRINTF((output+used, out_len-used, "1SS MCS8 = %d, 1SS MCS9 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[8], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[9])); - PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[10], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[11], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[12], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[13])); - PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[14], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[15], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[16], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[17])); - PHYDM_SNPRINTF((output+used, out_len-used, "2SS MCS8 = %d, 2SS MCS9 = %d\n", - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[18], pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[19])); + u32 used = *_used; + u32 out_len = *_out_len; + + PHYDM_SNPRINTF((output + used, out_len - used, "=====Rx SU rate Statistics=====\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", + p_dm_odm->phy_dbg_info.num_qry_vht_pkt[0], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[1], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[2], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[3])); + PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", + p_dm_odm->phy_dbg_info.num_qry_vht_pkt[4], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[5], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[6], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[7])); + PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS8 = %d, 1SS MCS9 = %d\n", + p_dm_odm->phy_dbg_info.num_qry_vht_pkt[8], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[9])); + PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", + p_dm_odm->phy_dbg_info.num_qry_vht_pkt[10], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[11], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[12], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[13])); + PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", + p_dm_odm->phy_dbg_info.num_qry_vht_pkt[14], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[15], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[16], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[17])); + PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS8 = %d, 2SS MCS9 = %d\n", + p_dm_odm->phy_dbg_info.num_qry_vht_pkt[18], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[19])); + + PHYDM_SNPRINTF((output + used, out_len - used, "=====Rx MU rate Statistics=====\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", + p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[0], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[1], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[2], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[3])); + PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", + p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[4], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[5], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[6], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[7])); + PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS8 = %d, 1SS MCS9 = %d\n", + p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[8], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[9])); + PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", + p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[10], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[11], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[12], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[13])); + PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", + p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[14], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[15], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[16], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[17])); + PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS8 = %d, 2SS MCS9 = %d\n", + p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[18], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[19])); } #endif +void +phydm_parameter_adjust( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + if ((strcmp(input[1], help) == 0)) { + PHYDM_SNPRINTF((output + used, out_len - used, "1. X_cap = ((0x%x))\n", p_cfo_track->crystal_cap)); + + } else { + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 0) { + + PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]); + phydm_set_crystal_cap(p_dm_odm, (u8)var1[1]); + PHYDM_SNPRINTF((output + used, out_len - used, "X_cap = ((0x%x))\n", p_cfo_track->crystal_cap)); + } + } +} struct _PHYDM_COMMAND { char name[16]; - u1Byte id; + u8 id; }; enum PHYDM_CMD_ID { + PHYDM_HELP, PHYDM_DEMO, PHYDM_RA, PHYDM_PROFILE, PHYDM_ANTDIV, PHYDM_PATHDIV, PHYDM_DEBUG, + PHYDM_FW_DEBUG, PHYDM_SUPPORT_ABILITY, + PHYDM_RF_SUPPORTABILITY, + PHYDM_RF_PROFILE, PHYDM_GET_TXAGC, PHYDM_SET_TXAGC, PHYDM_SMART_ANT, @@ -1586,7 +2149,6 @@ enum PHYDM_CMD_ID { PHYDM_TRX_PATH, PHYDM_LA_MODE, PHYDM_DUMP_REG, - PHYDM_MU_MIMO, PHYDM_HANG, PHYDM_BIG_JUMP, PHYDM_SHOW_RXRATE, @@ -1597,17 +2159,30 @@ enum PHYDM_CMD_ID { PHYDM_NHM, PHYDM_CLM, PHYDM_BB_INFO, - PHYDM_TXBF + PHYDM_TXBF, + PHYDM_PAUSE_DIG_EN, + PHYDM_H2C, + PHYDM_ANT_SWITCH, + PHYDM_DYNAMIC_RA_PATH, + PHYDM_PSD, + PHYDM_DEBUG_PORT, + PHYDM_HTSTF_CONTROL, + PHYDM_TUNE_PARAMETER, + PHYDM_ADAPTIVITY_DEBUG }; struct _PHYDM_COMMAND phy_dm_ary[] = { - {"demo", PHYDM_DEMO}, + {"-h", PHYDM_HELP}, /*do not move this element to other position*/ + {"demo", PHYDM_DEMO}, /*do not move this element to other position*/ {"ra", PHYDM_RA}, {"profile", PHYDM_PROFILE}, {"antdiv", PHYDM_ANTDIV}, {"pathdiv", PHYDM_PATHDIV}, {"dbg", PHYDM_DEBUG}, + {"fw_dbg", PHYDM_FW_DEBUG}, {"ability", PHYDM_SUPPORT_ABILITY}, + {"rf_ability", PHYDM_RF_SUPPORTABILITY}, + {"rf_profile", PHYDM_RF_PROFILE}, {"get_txagc", PHYDM_GET_TXAGC}, {"set_txagc", PHYDM_SET_TXAGC}, {"smtant", PHYDM_SMART_ANT}, @@ -1615,7 +2190,6 @@ struct _PHYDM_COMMAND phy_dm_ary[] = { {"trxpath", PHYDM_TRX_PATH}, {"lamode", PHYDM_LA_MODE}, {"dumpreg", PHYDM_DUMP_REG}, - {"mu", PHYDM_MU_MIMO}, {"hang", PHYDM_HANG}, {"bigjump", PHYDM_BIG_JUMP}, {"rxrate", PHYDM_SHOW_RXRATE}, @@ -1626,23 +2200,36 @@ struct _PHYDM_COMMAND phy_dm_ary[] = { {"nhm", PHYDM_NHM}, {"clm", PHYDM_CLM}, {"bbinfo", PHYDM_BB_INFO}, - {"txbf", PHYDM_TXBF} + {"txbf", PHYDM_TXBF}, + {"pause_dig", PHYDM_PAUSE_DIG_EN}, + {"h2c", PHYDM_H2C}, + {"ant_switch", PHYDM_ANT_SWITCH}, + {"drp", PHYDM_DYNAMIC_RA_PATH}, + {"psd", PHYDM_PSD}, + {"dbgport", PHYDM_DEBUG_PORT}, + {"htstf", PHYDM_HTSTF_CONTROL}, + {"tune_para", PHYDM_TUNE_PARAMETER}, + {"adapt_debug", PHYDM_ADAPTIVITY_DEBUG} }; -VOID +#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ + +void phydm_cmd_parser( - IN PDM_ODM_T pDM_Odm, - IN char input[][MAX_ARGV], - IN u4Byte input_num, - IN u1Byte flag, - OUT char *output, - IN u4Byte out_len + struct PHY_DM_STRUCT *p_dm_odm, + char input[][MAX_ARGV], + u32 input_num, + u8 flag, + char *output, + u32 out_len ) { - u4Byte used = 0; - u1Byte id = 0; +#if CONFIG_PHYDM_DEBUG_FUNCTION + u32 used = 0; + u8 id = 0; int var1[10] = {0}; - int i, input_idx = 0; + int i, input_idx = 0, phydm_ary_size; + char help[] = "-h"; if (flag == 0) { PHYDM_SNPRINTF((output + used, out_len - used, "GET, nothing to print\n")); @@ -1651,36 +2238,48 @@ phydm_cmd_parser( PHYDM_SNPRINTF((output + used, out_len - used, "\n")); - //Parsing Cmd ID + /* Parsing Cmd ID */ if (input_num) { - int n, i; - n = sizeof(phy_dm_ary) / sizeof(struct _PHYDM_COMMAND); - for (i = 0; i < n; i++) { + phydm_ary_size = sizeof(phy_dm_ary) / sizeof(struct _PHYDM_COMMAND); + for (i = 0; i < phydm_ary_size; i++) { if (strcmp(phy_dm_ary[i].name, input[0]) == 0) { id = phy_dm_ary[i].id; break; } } - if (i == n) { + if (i == phydm_ary_size) { PHYDM_SNPRINTF((output + used, out_len - used, "SET, command not found!\n")); return; } } switch (id) { - case PHYDM_DEMO: /*echo demo 10 0x3a z abcde >cmd*/ - { - u4Byte directory = 0; -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) - char char_temp; + + case PHYDM_HELP: + { + PHYDM_SNPRINTF((output + used, out_len - used, "BB cmd ==>\n")); + for (i = 0; i < phydm_ary_size - 2; i++) { + + PHYDM_SNPRINTF((output + used, out_len - used, " %-5d: %s\n", i, phy_dm_ary[i + 2].name)); + /**/ + } + } + break; + + case PHYDM_DEMO: { /*echo demo 10 0x3a z abcde >cmd*/ + u32 directory = 0; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) + char char_temp; #else - u4Byte char_temp = ' '; + u32 char_temp = ' '; #endif + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory); - PHYDM_SNPRINTF((output + used, out_len - used, "Decimal Value = %d\n", directory)); + PHYDM_SNPRINTF((output + used, out_len - used, "Decimal value = %d\n", directory)); PHYDM_SSCANF(input[2], DCMD_HEX, &directory); - PHYDM_SNPRINTF((output + used, out_len - used, "Hex Value = 0x%x\n", directory)); + PHYDM_SNPRINTF((output + used, out_len - used, "Hex value = 0x%x\n", directory)); PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp); PHYDM_SNPRINTF((output + used, out_len - used, "Char = %c\n", char_temp)); PHYDM_SNPRINTF((output + used, out_len - used, "String = %s\n", input[4])); @@ -1693,39 +2292,39 @@ phydm_cmd_parser( if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - /*PHYDM_SNPRINTF((output + used, out_len - used, "new SET, RA_var[%d]= (( %d ))\n", i , var1[i]));*/ + /*PHYDM_SNPRINTF((output + used, out_len - used, "new SET, RA_var[%d]= (( %d ))\n", i, var1[i]));*/ input_idx++; } } if (input_idx >= 1) { /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_RA_debug\n"));*/ - #if (defined(CONFIG_RA_DBG_CMD)) - odm_RA_debug((PVOID)pDM_Odm, (pu4Byte) var1); - #else - phydm_RA_debug_PCR(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - #endif +#if (defined(CONFIG_RA_DBG_CMD)) + odm_RA_debug((void *)p_dm_odm, (u32 *) var1); +#else + phydm_RA_debug_PCR(p_dm_odm, (u32 *)var1, &used, output, &out_len); +#endif } break; - + case PHYDM_ANTDIV: for (i = 0; i < 5; i++) { if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i , var1[i]));*/ + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i, var1[i]));*/ input_idx++; } } if (input_idx >= 1) { /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - phydm_antdiv_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - #endif +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + phydm_antdiv_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); +#endif } break; @@ -1736,7 +2335,7 @@ phydm_cmd_parser( if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i , var1[i]));*/ + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i, var1[i]));*/ input_idx++; } } @@ -1744,7 +2343,7 @@ phydm_cmd_parser( if (input_idx >= 1) { /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ #if (defined(CONFIG_PATH_DIVERSITY)) - odm_pathdiv_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + odm_pathdiv_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); #endif } @@ -1756,16 +2355,30 @@ phydm_cmd_parser( if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, Debug_var[%d]= (( %d ))\n", i , var1[i]));*/ + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, Debug_var[%d]= (( %d ))\n", i, var1[i]));*/ input_idx++; } } if (input_idx >= 1) { /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_debug_comp\n"));*/ - odm_debug_trace(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + phydm_debug_trace(p_dm_odm, (u32 *)var1, &used, output, &out_len); + } + + + break; + + case PHYDM_FW_DEBUG: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + input_idx++; + } } + if (input_idx >= 1) + phydm_fw_debug_trace(p_dm_odm, (u32 *)var1, &used, output, &out_len); break; @@ -1775,17 +2388,25 @@ phydm_cmd_parser( if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, support ablity_var[%d]= (( %d ))\n", i , var1[i]));*/ + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, support ablity_var[%d]= (( %d ))\n", i, var1[i]));*/ input_idx++; } } if (input_idx >= 1) { /*PHYDM_SNPRINTF((output+used, out_len-used, "support ablity\n"));*/ - phydm_support_ability_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + phydm_support_ability_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); } break; + + case PHYDM_RF_SUPPORTABILITY: + halrf_support_ability_debug(p_dm_odm, &input[0], &used, output, &out_len); + break; + + case PHYDM_RF_PROFILE: + phydm_rf_basic_profile(p_dm_odm, &used, output, &out_len); + break; case PHYDM_SMART_ANT: @@ -1797,300 +2418,192 @@ phydm_cmd_parser( } if (input_idx >= 1) { - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - phydm_hl_smart_ant_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - #endif - #endif +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + phydm_hl_smart_ant_debug_type2(p_dm_odm, &input[0], &used, output, &out_len, input_num); + #elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) + phydm_hl_smart_ant_debug(p_dm_odm, &input[0], &used, output, &out_len, input_num); + #endif +#endif } break; case PHYDM_API: #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - { - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F | ODM_RTL8821C)) { - BOOLEAN bEnableDbgMode; - u1Byte central_ch, primary_ch_idx, bandwidth; - - for (i = 0; i < 4; i++) { - if (input[i + 1]) - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - } - - bEnableDbgMode = (BOOLEAN)var1[0]; - central_ch = (u1Byte) var1[1]; - primary_ch_idx = (u1Byte) var1[2]; - bandwidth = (ODM_BW_E) var1[3]; - - if (bEnableDbgMode) { - pDM_Odm->bDisablePhyApi = FALSE; - phydm_api_switch_bw_channel(pDM_Odm, central_ch, primary_ch_idx, (ODM_BW_E) bandwidth); - pDM_Odm->bDisablePhyApi = TRUE; - PHYDM_SNPRINTF((output+used, out_len-used, "central_ch = %d, primary_ch_idx = %d, bandwidth = %d\n", central_ch, primary_ch_idx, bandwidth)); - } else { - pDM_Odm->bDisablePhyApi = FALSE; - PHYDM_SNPRINTF((output+used, out_len-used, "Disable API debug mode\n")); - } - } else - PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support PHYDM API function\n")); - } + { + if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)) { + boolean is_enable_dbg_mode; + u8 central_ch, primary_ch_idx, bandwidth; + + for (i = 0; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + is_enable_dbg_mode = (boolean)var1[0]; + central_ch = (u8) var1[1]; + primary_ch_idx = (u8) var1[2]; + bandwidth = (enum odm_bw_e) var1[3]; + + if (is_enable_dbg_mode) { + p_dm_odm->is_disable_phy_api = false; + phydm_api_switch_bw_channel(p_dm_odm, central_ch, primary_ch_idx, (enum odm_bw_e) bandwidth); + p_dm_odm->is_disable_phy_api = true; + PHYDM_SNPRINTF((output + used, out_len - used, "central_ch = %d, primary_ch_idx = %d, bandwidth = %d\n", central_ch, primary_ch_idx, bandwidth)); + } else { + p_dm_odm->is_disable_phy_api = false; + PHYDM_SNPRINTF((output + used, out_len - used, "Disable API debug mode\n")); + } + } else + PHYDM_SNPRINTF((output + used, out_len - used, "This IC doesn't support PHYDM API function\n")); + } #else - PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support PHYDM API function\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "This IC doesn't support PHYDM API function\n")); #endif - break; - - case PHYDM_PROFILE: /*echo profile, >cmd*/ - phydm_BasicProfile(pDM_Odm, &used, output, &out_len); + break; + + case PHYDM_PROFILE: + phydm_basic_profile(p_dm_odm, &used, output, &out_len); break; case PHYDM_GET_TXAGC: - phydm_get_txagc(pDM_Odm, &used, output, &out_len); + phydm_get_txagc(p_dm_odm, &used, output, &out_len); break; - + case PHYDM_SET_TXAGC: { - BOOLEAN bEnableDbgMode; - + boolean is_enable_dbg_mode; + for (i = 0; i < 5; i++) { if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); input_idx++; } } - bEnableDbgMode = (BOOLEAN)var1[0]; - if (bEnableDbgMode) { - pDM_Odm->bDisablePhyApi = FALSE; - phydm_set_txagc(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); - pDM_Odm->bDisablePhyApi = TRUE; + if ((strcmp(input[1], help) == 0)) { + PHYDM_SNPRINTF((output + used, out_len - used, "{En} {pathA~D(0~3)} {rate_idx(Hex), All_rate:0xff} {txagc_idx (Hex)}\n")); + /**/ + } else { - pDM_Odm->bDisablePhyApi = FALSE; - PHYDM_SNPRINTF((output+used, out_len-used, "Disable API debug mode\n")); + + is_enable_dbg_mode = (boolean)var1[0]; + if (is_enable_dbg_mode) { + p_dm_odm->is_disable_phy_api = false; + phydm_set_txagc(p_dm_odm, (u32 *)var1, &used, output, &out_len); + p_dm_odm->is_disable_phy_api = true; + } else { + p_dm_odm->is_disable_phy_api = false; + PHYDM_SNPRINTF((output + used, out_len - used, "Disable API debug mode\n")); + } } } - break; - + break; + case PHYDM_TRX_PATH: for (i = 0; i < 4; i++) { if (input[i + 1]) PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); } - #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F)) { - u1Byte TxPath, RxPath; - BOOLEAN bEnableDbgMode, bTx2Path; - - bEnableDbgMode = (BOOLEAN)var1[0]; - TxPath = (u1Byte) var1[1]; - RxPath = (u1Byte) var1[2]; - bTx2Path = (BOOLEAN) var1[3]; - - if (bEnableDbgMode) { - pDM_Odm->bDisablePhyApi = FALSE; - phydm_api_trx_mode(pDM_Odm, (ODM_RF_PATH_E) TxPath, (ODM_RF_PATH_E) RxPath, bTx2Path); - pDM_Odm->bDisablePhyApi = TRUE; - PHYDM_SNPRINTF((output+used, out_len-used, "TxPath = 0x%x, RxPath = 0x%x, bTx2Path = %d\n", TxPath, RxPath, bTx2Path)); +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) { + u8 tx_path, rx_path; + boolean is_enable_dbg_mode, is_tx2_path; + + is_enable_dbg_mode = (boolean)var1[0]; + tx_path = (u8) var1[1]; + rx_path = (u8) var1[2]; + is_tx2_path = (boolean) var1[3]; + + if (is_enable_dbg_mode) { + p_dm_odm->is_disable_phy_api = false; + phydm_api_trx_mode(p_dm_odm, (enum odm_rf_path_e) tx_path, (enum odm_rf_path_e) rx_path, is_tx2_path); + p_dm_odm->is_disable_phy_api = true; + PHYDM_SNPRINTF((output + used, out_len - used, "tx_path = 0x%x, rx_path = 0x%x, is_tx2_path = %d\n", tx_path, rx_path, is_tx2_path)); } else { - pDM_Odm->bDisablePhyApi = FALSE; - PHYDM_SNPRINTF((output+used, out_len-used, "Disable API debug mode\n")); + p_dm_odm->is_disable_phy_api = false; + PHYDM_SNPRINTF((output + used, out_len - used, "Disable API debug mode\n")); } } else - #endif - phydm_config_trx_path(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); +#endif + phydm_config_trx_path(p_dm_odm, (u32 *)var1, &used, output, &out_len); break; case PHYDM_LA_MODE: -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP)) -#if ((RTL8822B_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - { - if (pDM_Odm->SupportICType & PHYDM_IC_SUPPORT_LA_MODE) { - u2Byte PollingTime; - u1Byte TrigSel, TrigSigSel, DmaDataSigSel, TriggerTime; - BOOLEAN bEnableLaMode, bTriggerEdge; - u4Byte DbgPort; - - for (i = 0; i < 6; i++) { - if (input[i + 1]) - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - } - bEnableLaMode = (BOOLEAN)var1[0]; - if (bEnableLaMode) { - TrigSel = (u1Byte)var1[1]; /*0: BB, 1: MAC*/ - TrigSigSel = (u1Byte)var1[2]; - DmaDataSigSel = (u1Byte)var1[3]; - TriggerTime = (u1Byte)var1[4]; /*unit: us*/ - PollingTime = (((u1Byte)var1[5]) << 6); /*unit: ms*/ - PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]); - PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]); - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { - DbgPort = (u4Byte)var1[6]; - ODM_SetBBReg(pDM_Odm, 0x198C , BIT2|BIT1|BIT0, 7); /*disable dbg clk gating*/ - ODM_SetBBReg(pDM_Odm, 0x8FC, bMaskDWord, DbgPort); - bTriggerEdge = (BOOLEAN) var1[7]; - ODM_SetBBReg(pDM_Odm, 0x95C , BIT31, bTriggerEdge); /*0: posedge, 1: negedge*/ - } else { - DbgPort = (u4Byte)var1[6]; - ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, DbgPort); - bTriggerEdge = (BOOLEAN) var1[7]; - ODM_SetBBReg(pDM_Odm, 0x9A0 , BIT31, bTriggerEdge); /*0: posedge, 1: negedge*/ - } -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - ADCSmp_Set(pDM_Odm->Adapter, (RT_ADCSMP_TRIG_SEL) TrigSel, (RT_ADCSMP_TRIG_SIG_SEL) TrigSigSel, DmaDataSigSel, TriggerTime, PollingTime); -#else - ADCSmp_Set(pDM_Odm, (RT_ADCSMP_TRIG_SEL) TrigSel, (RT_ADCSMP_TRIG_SIG_SEL) TrigSigSel, DmaDataSigSel, TriggerTime, PollingTime); -#endif - PHYDM_SNPRINTF((output+used, out_len-used, "TrigSel = %d, TrigSigSel = %d, DmaDataSigSel = %d\n", TrigSel, TrigSigSel, DmaDataSigSel)); - PHYDM_SNPRINTF((output+used, out_len-used, "TriggerTime = %d, PollingTime = %d\n", TriggerTime, PollingTime)); - } else { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - ADCSmp_Stop(pDM_Odm->Adapter); -#else - ADCSmp_Stop(pDM_Odm); -#endif - PHYDM_SNPRINTF((output+used, out_len-used, "Disable LA mode\n")); - } - } else - PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support LA mode\n")); - } -#else - PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support LA mode\n")); -#endif +#if (PHYDM_LA_MODE_SUPPORT == 1) + p_dm_odm->support_ability &= ~(ODM_BB_FA_CNT); + phydm_lamode_trigger_setting(p_dm_odm, &input[0], &used, output, &out_len, input_num); + p_dm_odm->support_ability |= ODM_BB_FA_CNT; #else - PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support LA mode\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "This IC doesn't support LA mode\n")); #endif + break; case PHYDM_DUMP_REG: { - u1Byte type = 0; - + u8 type = 0; + if (input[1]) { PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - type = (u1Byte)var1[0]; + type = (u8)var1[0]; } if (type == 0) - phydm_DumpBbReg(pDM_Odm, &used, output, &out_len); + phydm_dump_bb_reg(p_dm_odm, &used, output, &out_len); else if (type == 1) - phydm_DumpAllReg(pDM_Odm, &used, output, &out_len); + phydm_dump_all_reg(p_dm_odm, &used, output, &out_len); } - break; - - case PHYDM_MU_MIMO: -#if (RTL8822B_SUPPORT == 1) - - if (input[1]) - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - else - var1[0] = 0; - - if (var1[0] == 1) { - int index, ptr; - u4Byte Dword_H, Dword_L; - - PHYDM_SNPRINTF((output+used, out_len-used, "Get MU BFee CSI\n")); - ODM_SetBBReg(pDM_Odm, 0x9e8, BIT17|BIT16, 2); /*Read BFee*/ - ODM_SetBBReg(pDM_Odm, 0x1910, BIT15, 1); /*Select BFee's CSI report*/ - ODM_SetBBReg(pDM_Odm, 0x19b8, BIT6, 1); /*set as CSI report*/ - ODM_SetBBReg(pDM_Odm, 0x19a8, 0xFFFF, 0xFFFF); /*disable gated_clk*/ - - for (index = 0; index < 80; index++) { - ptr = index + 256; - if (ptr > 311) - ptr -= 312; - ODM_SetBBReg(pDM_Odm, 0x1910, 0x03FF0000, ptr); /*Select Address*/ - Dword_H = ODM_GetBBReg(pDM_Odm, 0xF74, bMaskDWord); - Dword_L = ODM_GetBBReg(pDM_Odm, 0xF5C, bMaskDWord); - if (index % 2 == 0) - PHYDM_SNPRINTF((output+used, out_len-used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", - Dword_L & bMaskByte0, (Dword_L & bMaskByte1) >> 8, (Dword_L & bMaskByte2) >> 16, (Dword_L & bMaskByte3) >> 24, - Dword_H & bMaskByte0, (Dword_H & bMaskByte1) >> 8, (Dword_H & bMaskByte2) >> 16, (Dword_H & bMaskByte3) >> 24)); - else - PHYDM_SNPRINTF((output+used, out_len-used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", - Dword_L & bMaskByte0, (Dword_L & bMaskByte1) >> 8, (Dword_L & bMaskByte2) >> 16, (Dword_L & bMaskByte3) >> 24, - Dword_H & bMaskByte0, (Dword_H & bMaskByte1) >> 8, (Dword_H & bMaskByte2) >> 16, (Dword_H & bMaskByte3) >> 24)); - } - } else if (var1[0] == 2) { - int index, ptr; - u4Byte Dword_H, Dword_L; - - PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); - PHYDM_SNPRINTF((output+used, out_len-used, "Get MU BFer's STA%d CSI\n", var1[1])); - ODM_SetBBReg(pDM_Odm, 0x9e8, BIT24, 0); /*Read BFer*/ - ODM_SetBBReg(pDM_Odm, 0x9e8, BIT25, 1); /*enable Read/Write RAM*/ - ODM_SetBBReg(pDM_Odm, 0x9e8, BIT30|BIT29|BIT28, var1[1]); /*read which STA's CSI report*/ - ODM_SetBBReg(pDM_Odm, 0x1910, BIT15, 0); /*select BFer's CSI*/ - ODM_SetBBReg(pDM_Odm, 0x19e0, 0x00003FC0, 0xFF); /*disable gated_clk*/ - - for (index = 0; index < 80; index++) { - ptr = index + 256; - if (ptr > 311) - ptr -= 312; - ODM_SetBBReg(pDM_Odm, 0x1910, 0x03FF0000, ptr); /*Select Address*/ - Dword_H = ODM_GetBBReg(pDM_Odm, 0xF74, bMaskDWord); - Dword_L = ODM_GetBBReg(pDM_Odm, 0xF5C, bMaskDWord); - if (index % 2 == 0) - PHYDM_SNPRINTF((output+used, out_len-used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", - Dword_L & bMaskByte0, (Dword_L & bMaskByte1) >> 8, (Dword_L & bMaskByte2) >> 16, (Dword_L & bMaskByte3) >> 24, - Dword_H & bMaskByte0, (Dword_H & bMaskByte1) >> 8, (Dword_H & bMaskByte2) >> 16, (Dword_H & bMaskByte3) >> 24)); - else - PHYDM_SNPRINTF((output+used, out_len-used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", - Dword_L & bMaskByte0, (Dword_L & bMaskByte1) >> 8, (Dword_L & bMaskByte2) >> 16, (Dword_L & bMaskByte3) >> 24, - Dword_H & bMaskByte0, (Dword_H & bMaskByte1) >> 8, (Dword_H & bMaskByte2) >> 16, (Dword_H & bMaskByte3) >> 24)); - - PHYDM_SNPRINTF((output+used, out_len-used, "ptr=%d : 0x%8x %8x\n", ptr, Dword_H, Dword_L)); - } - - } -#endif - break; + break; case PHYDM_BIG_JUMP: { #if (RTL8822B_SUPPORT == 1) - if (input[1]) { - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - phydm_EnableBigJump(pDM_Odm, (BOOLEAN)(var1[0])); + if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + if (input[1]) { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + phydm_enable_big_jump(p_dm_odm, (boolean)(var1[0])); + } else + PHYDM_SNPRINTF((output + used, out_len - used, "unknown command!\n")); } else - PHYDM_SNPRINTF((output + used, out_len - used, "unknown command!\n")); -#else - PHYDM_SNPRINTF((output + used, out_len - used, "The command is only for 8822B!\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "The command is only for 8822B!\n")); #endif break; } - + case PHYDM_HANG: - phydm_BB_RxHang_Info(pDM_Odm, &used, output, &out_len); + phydm_bb_rx_hang_info(p_dm_odm, &used, output, &out_len); break; case PHYDM_SHOW_RXRATE: -#if (RTL8822B_SUPPORT == 1) - { - u1Byte rate_idx; - - if (input[1]) - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); +#if (RTL8822B_SUPPORT == 1 | RTL8821C_SUPPORT == 1 | RTL8814B_SUPPORT == 1) + if (p_dm_odm->support_ic_type & PHYDM_IC_SUPPORT_MU_BFEE) { + u8 rate_idx; + + if (input[1]) + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - if (var1[0] == 1) - phydm_showRxRate(pDM_Odm, &used, output, &out_len); - else { - PHYDM_SNPRINTF((output+used, out_len-used, "Reset Rx rate counter\n")); + if (var1[0] == 1) + phydm_show_rx_rate(p_dm_odm, &used, output, &out_len); + else { + PHYDM_SNPRINTF((output + used, out_len - used, "Reset Rx rate counter\n")); - for (rate_idx = 0; rate_idx < 40; rate_idx++) { - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[rate_idx] = 0; - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[rate_idx] = 0; + for (rate_idx = 0; rate_idx < 40; rate_idx++) { + p_dm_odm->phy_dbg_info.num_qry_vht_pkt[rate_idx] = 0; + p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[rate_idx] = 0; + } } } - } #endif - break; + break; case PHYDM_NBI_EN: - + for (i = 0; i < 5; i++) { if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); @@ -2099,8 +2612,8 @@ phydm_cmd_parser( } if (input_idx >= 1) { - - phydm_api_debug(pDM_Odm, PHYDM_API_NBI, (u4Byte *)var1, &used, output, &out_len); + + phydm_api_debug(p_dm_odm, PHYDM_API_NBI, (u32 *)var1, &used, output, &out_len); /**/ } @@ -2108,7 +2621,7 @@ phydm_cmd_parser( break; case PHYDM_CSI_MASK_EN: - + for (i = 0; i < 5; i++) { if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); @@ -2117,143 +2630,139 @@ phydm_cmd_parser( } if (input_idx >= 1) { - - phydm_api_debug(pDM_Odm, PHYDM_API_CSI_MASK, (u4Byte *)var1, &used, output, &out_len); + + phydm_api_debug(p_dm_odm, PHYDM_API_CSI_MASK, (u32 *)var1, &used, output, &out_len); /**/ } - break; + break; case PHYDM_DFS: #if (DM_ODM_SUPPORT_TYPE & ODM_CE) - { - u4Byte var[6] = {0}; + { + u32 var[6] = {0}; - for (i = 0; i < 6; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var[i]); - input_idx++; + for (i = 0; i < 6; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var[i]); + input_idx++; + } } + + if (input_idx >= 1) + phydm_dfs_debug(p_dm_odm, var, &used, output, &out_len); } - - if (input_idx >= 1) - phydm_dfs_debug(pDM_Odm, var, &used, output, &out_len); - } #endif break; case PHYDM_IQK: #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_IQCalibrate(pDM_Odm->priv); + phy_iq_calibrate(p_dm_odm->priv); PHYDM_SNPRINTF((output + used, out_len - used, "IQK !!\n")); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PHY_IQCalibrate(pDM_Odm->Adapter, FALSE); + PHY_IQCalibrate(p_dm_odm->adapter, false); PHYDM_SNPRINTF((output + used, out_len - used, "IQK !!\n")); #endif break; case PHYDM_NHM: - { - u1Byte target_rssi; - u4Byte value32; - u2Byte nhm_period = 0xC350; //200ms - u1Byte IGI; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + { + u8 target_rssi; + u16 nhm_period = 0xC350; /* 200ms */ + u8 IGI; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - if(input_num == 1) { + if (input_num == 1) { - CCX_INFO->echo_NHM_en = FALSE; + ccx_info->echo_NHM_en = false; PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger NHM: echo nhm 1\n")); PHYDM_SNPRINTF((output + used, out_len - used, "\r (Exclude CCA)\n")); PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger NHM: echo nhm 2\n")); PHYDM_SNPRINTF((output + used, out_len - used, "\r (Include CCA)\n")); PHYDM_SNPRINTF((output + used, out_len - used, "\r Get NHM results: echo nhm 3\n")); - + return; } /* NMH trigger */ if ((var1[0] <= 2) && (var1[0] != 0)) { - CCX_INFO->echo_NHM_en = TRUE; - CCX_INFO->echo_IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + ccx_info->echo_NHM_en = true; + ccx_info->echo_IGI = (u8)odm_get_bb_reg(p_dm_odm, 0xC50, MASKBYTE0); - target_rssi = CCX_INFO->echo_IGI - 10; + target_rssi = ccx_info->echo_IGI - 10; - CCX_INFO->NHM_th[0] = (target_rssi -15 + 10) * 2; + ccx_info->NHM_th[0] = (target_rssi - 15 + 10) * 2; - for(i = 1; i <= 10; i ++) { - CCX_INFO->NHM_th[i] = CCX_INFO->NHM_th[0] + 6 * i; - } + for (i = 1; i <= 10; i++) + ccx_info->NHM_th[i] = ccx_info->NHM_th[0] + 6 * i; - //4 1. store previous NHM setting - phydm_NHMsetting(pDM_Odm, STORE_NHM_SETTING); + /* 4 1. store previous NHM setting */ + phydm_nhm_setting(p_dm_odm, STORE_NHM_SETTING); - //4 2. Set NHM period, 0x990[31:16]=0xC350, Time duration for NHM unit: 4us, 0xC350=200ms - CCX_INFO->NHM_period = nhm_period; + /* 4 2. Set NHM period, 0x990[31:16]=0xC350, Time duration for NHM unit: 4us, 0xC350=200ms */ + ccx_info->NHM_period = nhm_period; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Monitor NHM for %d us", nhm_period*4)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Monitor NHM for %d us", nhm_period * 4)); - //4 3. Set NHM inexclude_txon, inexclude_cca, ccx_en + /* 4 3. Set NHM inexclude_txon, inexclude_cca, ccx_en */ - - CCX_INFO->NHM_inexclude_cca = (var1[0] == 1) ? NHM_EXCLUDE_CCA : NHM_INCLUDE_CCA; - CCX_INFO->NHM_inexclude_txon = NHM_EXCLUDE_TXON; - - phydm_NHMsetting(pDM_Odm, SET_NHM_SETTING); - for(i = 0; i <= 10; i ++) { - - if (i == 5) { - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x, echo_IGI = 0x%x", i, CCX_INFO->NHM_th[i], CCX_INFO->echo_IGI)); - } + ccx_info->nhm_inexclude_cca = (var1[0] == 1) ? NHM_EXCLUDE_CCA : NHM_INCLUDE_CCA; + ccx_info->nhm_inexclude_txon = NHM_EXCLUDE_TXON; + + phydm_nhm_setting(p_dm_odm, SET_NHM_SETTING); + + for (i = 0; i <= 10; i++) { + + if (i == 5) + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x, echo_IGI = 0x%x", i, ccx_info->NHM_th[i], ccx_info->echo_IGI)); else if (i == 10) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x\n", i, CCX_INFO->NHM_th[i])); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x\n", i, ccx_info->NHM_th[i])); else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x", i, CCX_INFO->NHM_th[i])); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x", i, ccx_info->NHM_th[i])); } - //4 4. Trigger NHM - phydm_NHMtrigger(pDM_Odm); + /* 4 4. Trigger NHM */ + phydm_nhm_trigger(p_dm_odm); } - + /*Get NHM results*/ else if (var1[0] == 3) { - IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + IGI = (u8)odm_get_bb_reg(p_dm_odm, 0xC50, MASKBYTE0); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Cur_IGI = 0x%x", IGI)); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Cur_IGI = 0x%x", IGI)); - phydm_getNHMresult(pDM_Odm); - - //4 Resotre NHM setting - phydm_NHMsetting(pDM_Odm, RESTORE_NHM_SETTING); - - for(i = 0; i <= 11; i++) { - - if (i == 5) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d, echo_IGI = 0x%x", i, CCX_INFO->NHM_result[i], CCX_INFO->echo_IGI)); + phydm_get_nhm_result(p_dm_odm); + + /* 4 Resotre NHM setting */ + phydm_nhm_setting(p_dm_odm, RESTORE_NHM_SETTING); + + for (i = 0; i <= 11; i++) { + + if (i == 5) + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d, echo_IGI = 0x%x", i, ccx_info->NHM_result[i], ccx_info->echo_IGI)); else if (i == 11) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d\n", i, CCX_INFO->NHM_result[i])); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d\n", i, ccx_info->NHM_result[i])); else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d", i, CCX_INFO->NHM_result[i])); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d", i, ccx_info->NHM_result[i])); } - - CCX_INFO->echo_NHM_en = FALSE; - } - else { - - CCX_INFO->echo_NHM_en = FALSE; + + ccx_info->echo_NHM_en = false; + } else { + + ccx_info->echo_NHM_en = false; PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger NHM: echo nhm 1\n")); PHYDM_SNPRINTF((output + used, out_len - used, "\r (Exclude CCA)\n")); PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger NHM: echo nhm 2\n")); PHYDM_SNPRINTF((output + used, out_len - used, "\r (Include CCA)\n")); PHYDM_SNPRINTF((output + used, out_len - used, "\r Get NHM results: echo nhm 3\n")); - + return; } } @@ -2261,14 +2770,14 @@ phydm_cmd_parser( case PHYDM_CLM: { - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - //PHYDM_SNPRINTF((output + used, out_len - used, "\r\n input_num = %d\n", input_num)); + /* PHYDM_SNPRINTF((output + used, out_len - used, "\r\n input_num = %d\n", input_num)); */ if (input_num == 1) { - CCX_INFO->echo_CLM_en = FALSE; + ccx_info->echo_CLM_en = false; PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger CLM: echo clm 1\n")); PHYDM_SNPRINTF((output + used, out_len - used, "\r Get CLM results: echo clm 2\n")); return; @@ -2277,62 +2786,66 @@ phydm_cmd_parser( /* Set & trigger CLM */ if (var1[0] == 1) { - CCX_INFO->echo_CLM_en = TRUE; - CCX_INFO->CLM_period = 0xC350; /*100ms*/ - phydm_CLMsetting(pDM_Odm); - phydm_CLMtrigger(pDM_Odm); + ccx_info->echo_CLM_en = true; + ccx_info->CLM_period = 0xC350; /*100ms*/ + phydm_clm_setting(p_dm_odm); + phydm_clm_trigger(p_dm_odm); PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Monitor CLM for 200ms\n")); } - + /* Get CLM results */ else if (var1[0] == 2) { - CCX_INFO->echo_CLM_en = FALSE; - phydm_getCLMresult(pDM_Odm); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n CLM_result = %d us\n", CCX_INFO->CLM_result*4)); - + ccx_info->echo_CLM_en = false; + phydm_get_clm_result(p_dm_odm); + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n CLM_result = %d us\n", ccx_info->CLM_result * 4)); + } else { - CCX_INFO->echo_CLM_en = FALSE; + ccx_info->echo_CLM_en = false; PHYDM_SNPRINTF((output + used, out_len - used, "\n\r Error command !\n")); PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger CLM: echo clm 1\n")); PHYDM_SNPRINTF((output + used, out_len - used, "\r Get CLM results: echo clm 2\n")); } } - break; - + break; + case PHYDM_BB_INFO: { - s4Byte value32 = 0; - - phydm_BB_Debug_Info(pDM_Odm, &used, output, &out_len); + s32 value32 = 0; + + phydm_bb_debug_info(p_dm_odm, &used, output, &out_len); - if (pDM_Odm->SupportICType & ODM_RTL8822B && input[1]) { + if (p_dm_odm->support_ic_type & ODM_RTL8822B && input[1]) { PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - ODM_SetBBReg(pDM_Odm, 0x1988, 0x003fff00, var1[0]); - value32 = ODM_GetBBReg(pDM_Odm, 0xf84, bMaskDWord); - value32 = (value32 & 0xff000000)>>24; + odm_set_bb_reg(p_dm_odm, 0x1988, 0x003fff00, var1[0]); + value32 = odm_get_bb_reg(p_dm_odm, 0xf84, MASKDWORD); + value32 = (value32 & 0xff000000) >> 24; PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = condition num = %d, subcarriers = %d\n", "Over condition num subcarrier", var1[0], value32)); - ODM_SetBBReg(pDM_Odm, 0x1988 , BIT22, 0x0); /*disable report condition number*/ + odm_set_bb_reg(p_dm_odm, 0x1988, BIT(22), 0x0); /*disable report condition number*/ } } - break; + break; case PHYDM_TXBF: { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (BEAMFORMING_SUPPORT == 1) - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - if (var1[0] == 1) { - pBeamformingInfo->applyVmatrix = TRUE; - pBeamformingInfo->snding3SS = FALSE; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n apply V matrix and 3SS 789 dont snding\n")); - } else if (var1[0] == 0) { - pBeamformingInfo->applyVmatrix = FALSE; - pBeamformingInfo->snding3SS = TRUE; + if (var1[0] == 0) { + p_beamforming_info->apply_v_matrix = false; + p_beamforming_info->snding3ss = true; PHYDM_SNPRINTF((output + used, out_len - used, "\r\n dont apply V matrix and 3SS 789 snding\n")); + } else if (var1[0] == 1) { + p_beamforming_info->apply_v_matrix = true; + p_beamforming_info->snding3ss = true; + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n apply V matrix and 3SS 789 snding\n")); + } else if (var1[0] == 2) { + p_beamforming_info->apply_v_matrix = true; + p_beamforming_info->snding3ss = false; + PHYDM_SNPRINTF((output + used, out_len - used, "\r\n default txbf setting\n")); } else PHYDM_SNPRINTF((output + used, out_len - used, "\r\n unknown cmd!!\n")); #else @@ -2340,6 +2853,143 @@ phydm_cmd_parser( #endif #endif } + break; + + case PHYDM_PAUSE_DIG_EN: + + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) { + if (var1[0] == 0) { + odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_7, (u8)var1[1]); + PHYDM_SNPRINTF((output + used, out_len - used, "Set IGI_value = ((%x))\n", var1[1])); + } else if (var1[0] == 1) { + odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_7, (u8)var1[1]); + PHYDM_SNPRINTF((output + used, out_len - used, "Resume IGI_value\n")); + } else + PHYDM_SNPRINTF((output + used, out_len - used, "echo (1:pause, 2resume) (IGI_value)\n")); + } + + break; + + case PHYDM_H2C: + + for (i = 0; i < 8; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) + phydm_h2C_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); + + + break; + + case PHYDM_ANT_SWITCH: + + for (i = 0; i < 8; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) { + +#if (RTL8821A_SUPPORT == 1) + phydm_set_ext_switch(p_dm_odm, (u32 *)var1, &used, output, &out_len); +#else + PHYDM_SNPRINTF((output + used, out_len - used, "Not Support IC")); +#endif + } + + + break; + + case PHYDM_DYNAMIC_RA_PATH: + +#if (CONFIG_DYNAMIC_RX_PATH == 1) + for (i = 0; i < 8; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) + phydm_drp_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); + +#else + PHYDM_SNPRINTF((output + used, out_len - used, "Not Support IC")); +#endif + + break; + + case PHYDM_PSD: + + #if (CONFIG_PSD_TOOL== 1) + phydm_psd_debug(p_dm_odm, &input[0], &used, output, &out_len, input_num); + #endif + + break; + + case PHYDM_DEBUG_PORT: + { + u32 dbg_port_value; + + PHYDM_SSCANF(input[1], DCMD_HEX, &var1[0]); + + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_3, var1[0])) {/*set debug port to 0x0*/ + + dbg_port_value = phydm_get_bb_dbg_port_value(p_dm_odm); + phydm_release_bb_dbg_port(p_dm_odm); + + PHYDM_SNPRINTF((output + used, out_len - used, "Debug Port[0x%x] = ((0x%x))\n", var1[1], dbg_port_value)); + } + } + break; + + case PHYDM_HTSTF_CONTROL: + { + if (input[1]) + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 1) { + /* phydm_dynamic_switch_htstf_mumimo_8822b(p_dm_odm);*/ + p_dm_odm->bhtstfenabled = TRUE; + PHYDM_SNPRINTF((output + used, out_len - used, "Dynamic HT-STF Gain Control is Enable\n")); + } + else { + p_dm_odm->bhtstfenabled = FALSE; + PHYDM_SNPRINTF((output + used, out_len - used, "Dynamic HT-STF Gain Control is Disable\n")); + } + } + break; + + case PHYDM_TUNE_PARAMETER: + phydm_parameter_adjust(p_dm_odm, &input[0], &used, output, &out_len, input_num); + break; + + case PHYDM_ADAPTIVITY_DEBUG: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) + phydm_adaptivity_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); + break; default: @@ -2347,6 +2997,7 @@ phydm_cmd_parser( break; } +#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ } #ifdef __ECOS @@ -2366,361 +3017,349 @@ char *strsep(char **s, const char *ct) } #endif -#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) -s4Byte +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) +s32 phydm_cmd( - IN PDM_ODM_T pDM_Odm, - IN char *input, - IN u4Byte in_len, - IN u1Byte flag, - OUT char *output, - IN u4Byte out_len + struct PHY_DM_STRUCT *p_dm_odm, + char *input, + u32 in_len, + u8 flag, + char *output, + u32 out_len ) { char *token; - u4Byte Argc = 0; - char Argv[MAX_ARGC][MAX_ARGV]; + u32 argc = 0; + char argv[MAX_ARGC][MAX_ARGV]; do { token = strsep(&input, ", "); if (token) { - strcpy(Argv[Argc], token); - Argc++; + strcpy(argv[argc], token); + argc++; } else break; - } while (Argc < MAX_ARGC); + } while (argc < MAX_ARGC); - if (Argc == 1) - Argv[0][strlen(Argv[0]) - 1] = '\0'; + if (argc == 1) + argv[0][strlen(argv[0]) - 1] = '\0'; - phydm_cmd_parser(pDM_Odm, Argv, Argc, flag, output, out_len); + phydm_cmd_parser(p_dm_odm, argv, argc, flag, output, out_len); return 0; } #endif -VOID +void phydm_fw_trace_handler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if CONFIG_PHYDM_DEBUG_FUNCTION + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - /*u1Byte debug_trace_11byte[60];*/ - u1Byte freg_num, c2h_seq, buf_0 = 0; + /*u8 debug_trace_11byte[60];*/ + u8 freg_num, c2h_seq, buf_0 = 0; - if (!(pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES)) + if (!(p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES)) return; - if (CmdLen > 12) + if (cmd_len > 12) return; - - buf_0 = CmdBuf[0]; + + buf_0 = cmd_buf[0]; freg_num = (buf_0 & 0xf); c2h_seq = (buf_0 & 0xf0) >> 4; - /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] freg_num = (( %d )), c2h_seq = (( %d ))\n", freg_num,c2h_seq ));*/ + /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] freg_num = (( %d )), c2h_seq = (( %d ))\n", freg_num,c2h_seq ));*/ - /*strncpy(debug_trace_11byte,&CmdBuf[1],(CmdLen-1));*/ - /*debug_trace_11byte[CmdLen-1] = '\0';*/ - /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] %s\n", debug_trace_11byte));*/ - /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] CmdLen = (( %d ))\n", CmdLen));*/ - /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] c2h_cmd_start = (( %d ))\n", pDM_Odm->c2h_cmd_start));*/ + /*strncpy(debug_trace_11byte,&cmd_buf[1],(cmd_len-1));*/ + /*debug_trace_11byte[cmd_len-1] = '\0';*/ + /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] %s\n", debug_trace_11byte));*/ + /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] cmd_len = (( %d ))\n", cmd_len));*/ + /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] c2h_cmd_start = (( %d ))\n", p_dm_odm->c2h_cmd_start));*/ - /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("pre_seq = (( %d )), current_seq = (( %d ))\n", pDM_Odm->pre_c2h_seq, c2h_seq));*/ - /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("fw_buff_is_enpty = (( %d ))\n", pDM_Odm->fw_buff_is_enpty));*/ + /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("pre_seq = (( %d )), current_seq = (( %d ))\n", p_dm_odm->pre_c2h_seq, c2h_seq));*/ + /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("fw_buff_is_enpty = (( %d ))\n", p_dm_odm->fw_buff_is_enpty));*/ - if ((c2h_seq != pDM_Odm->pre_c2h_seq) && pDM_Odm->fw_buff_is_enpty == FALSE) { - pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start] = '\0'; - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue Overflow] %s\n", pDM_Odm->fw_debug_trace)); - pDM_Odm->c2h_cmd_start = 0; + if ((c2h_seq != p_dm_odm->pre_c2h_seq) && p_dm_odm->fw_buff_is_enpty == false) { + p_dm_odm->fw_debug_trace[p_dm_odm->c2h_cmd_start] = '\0'; + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue Overflow] %s\n", p_dm_odm->fw_debug_trace)); + p_dm_odm->c2h_cmd_start = 0; } - if ((CmdLen - 1) > (60 - pDM_Odm->c2h_cmd_start)) { - pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start] = '\0'; - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue error: wrong C2H length] %s\n", pDM_Odm->fw_debug_trace)); - pDM_Odm->c2h_cmd_start = 0; + if ((cmd_len - 1) > (60 - p_dm_odm->c2h_cmd_start)) { + p_dm_odm->fw_debug_trace[p_dm_odm->c2h_cmd_start] = '\0'; + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue error: wrong C2H length] %s\n", p_dm_odm->fw_debug_trace)); + p_dm_odm->c2h_cmd_start = 0; return; } - strncpy((char *)&(pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start]), (char *)&CmdBuf[1], (CmdLen-1)); - pDM_Odm->c2h_cmd_start += (CmdLen - 1); - pDM_Odm->fw_buff_is_enpty = FALSE; - - if (freg_num == 0 || pDM_Odm->c2h_cmd_start >= 60) { - if (pDM_Odm->c2h_cmd_start < 60) - pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start] = '\0'; + strncpy((char *)&(p_dm_odm->fw_debug_trace[p_dm_odm->c2h_cmd_start]), (char *)&cmd_buf[1], (cmd_len - 1)); + p_dm_odm->c2h_cmd_start += (cmd_len - 1); + p_dm_odm->fw_buff_is_enpty = false; + + if (freg_num == 0 || p_dm_odm->c2h_cmd_start >= 60) { + if (p_dm_odm->c2h_cmd_start < 60) + p_dm_odm->fw_debug_trace[p_dm_odm->c2h_cmd_start] = '\0'; else - pDM_Odm->fw_debug_trace[59] = '\0'; + p_dm_odm->fw_debug_trace[59] = '\0'; - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", pDM_Odm->fw_debug_trace)); - /*DbgPrint("[FW DBG Msg] %s\n", pDM_Odm->fw_debug_trace);*/ - pDM_Odm->c2h_cmd_start = 0; - pDM_Odm->fw_buff_is_enpty = TRUE; + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", p_dm_odm->fw_debug_trace)); + /*dbg_print("[FW DBG Msg] %s\n", p_dm_odm->fw_debug_trace);*/ + p_dm_odm->c2h_cmd_start = 0; + p_dm_odm->fw_buff_is_enpty = true; } - pDM_Odm->pre_c2h_seq = c2h_seq; + p_dm_odm->pre_c2h_seq = c2h_seq; +#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ } -VOID +void phydm_fw_trace_handler_code( - IN PVOID pDM_VOID, - IN pu1Byte Buffer, - IN u1Byte CmdLen + void *p_dm_void, + u8 *buffer, + u8 cmd_len ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte function = Buffer[0]; - u1Byte dbg_num = Buffer[1]; - u2Byte content_0 = (((u2Byte)Buffer[3])<<8)|((u2Byte)Buffer[2]); - u2Byte content_1 = (((u2Byte)Buffer[5])<<8)|((u2Byte)Buffer[4]); - u2Byte content_2 = (((u2Byte)Buffer[7])<<8)|((u2Byte)Buffer[6]); - u2Byte content_3 = (((u2Byte)Buffer[9])<<8)|((u2Byte)Buffer[8]); - u2Byte content_4 = (((u2Byte)Buffer[11])<<8)|((u2Byte)Buffer[10]); - - if(CmdLen >12) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW Msg] Invalid cmd length (( %d )) >12 \n", CmdLen)); - } - - //ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW Msg] Func=((%d)), num=((%d)), ct_0=((%d)), ct_1=((%d)), ct_2=((%d)), ct_3=((%d)), ct_4=((%d))\n", - // function, dbg_num, content_0, content_1, content_2, content_3, content_4)); - +#if CONFIG_PHYDM_DEBUG_FUNCTION + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 function = buffer[0]; + u8 dbg_num = buffer[1]; + u16 content_0 = (((u16)buffer[3]) << 8) | ((u16)buffer[2]); + u16 content_1 = (((u16)buffer[5]) << 8) | ((u16)buffer[4]); + u16 content_2 = (((u16)buffer[7]) << 8) | ((u16)buffer[6]); + u16 content_3 = (((u16)buffer[9]) << 8) | ((u16)buffer[8]); + u16 content_4 = (((u16)buffer[11]) << 8) | ((u16)buffer[10]); + + if (cmd_len > 12) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Msg] Invalid cmd length (( %d )) >12\n", cmd_len)); + + /* ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW Msg] Func=((%d)), num=((%d)), ct_0=((%d)), ct_1=((%d)), ct_2=((%d)), ct_3=((%d)), ct_4=((%d))\n", */ + /* function, dbg_num, content_0, content_1, content_2, content_3, content_4)); */ + /*--------------------------------------------*/ #if (CONFIG_RA_FW_DBG_CODE) - if(function == RATE_DECISION) { - if(dbg_num == 0) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RA_CNT=((%d)) Max_device=((%d))--------------------------->\n", content_1, content_2)); - } else if(content_0 == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)), try_bit=((0x%x))\n", content_1, content_2, content_3, content_4)); - } else if(content_0 == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Check RA total=((%d)), drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n", content_1, content_2, content_3, content_4)); - } - } else if(dbg_num == 1) { - if (content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\n", content_1, content_2, content_3, content_4)); - } else if (content_0 == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))", content_1, content_2, content_3, content_4)); - phydm_print_rate(pDM_Odm, (u1Byte)content_4, ODM_FW_DEBUG_TRACE); - } else if (content_0 == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] penality_idx=(( %d ))\n", content_1)); - } else if (content_0 == 4) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RSSI=(( %d )), ra_stage = (( %d ))\n", content_1, content_2)); - } + if (function == RATE_DECISION) { + if (dbg_num == 0) { + if (content_0 == 1) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RA_CNT=((%d)) Max_device=((%d))--------------------------->\n", content_1, content_2)); + else if (content_0 == 2) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)), try_bit=((0x%x))\n", content_1, content_2, content_3, content_4)); + else if (content_0 == 3) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Check RA total=((%d)), drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n", content_1, content_2, content_3, content_4)); + } else if (dbg_num == 1) { + if (content_0 == 1) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\n", content_1, content_2, content_3, content_4)); + else if (content_0 == 2) { + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))", content_1, content_2, content_3, content_4)); + phydm_print_rate(p_dm_odm, (u8)content_4, ODM_FW_DEBUG_TRACE); + } else if (content_0 == 3) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] penality_idx=(( %d ))\n", content_1)); + else if (content_0 == 4) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RSSI=(( %d )), ra_stage = (( %d ))\n", content_1, content_2)); } - - else if(dbg_num == 3) { + + else if (dbg_num == 3) { if (content_0 == 1) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( DOWN )) total=((%d)), total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( DOWN )) total=((%d)), total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); else if (content_0 == 2) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) total_acc=((%d)), total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) total_acc=((%d)), total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); else if (content_0 == 3) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) ((Rate Down Hold)) RA_CNT=((%d))\n", content_1)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) ((rate Down Hold)) RA_CNT=((%d))\n", content_1)); else if (content_0 == 4) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) ((tota_accl<5 skip)) RA_CNT=((%d))\n", content_1)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) ((tota_accl<5 skip)) RA_CNT=((%d))\n", content_1)); else if (content_0 == 8) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n", content_1)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n", content_1)); } else if (dbg_num == 4) { if (content_0 == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RER_CNT PCR_ori =(( %d )), ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\n", content_1, content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RER_CNT PCR_ori =(( %d )), ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\n", content_1, content_2, content_3, content_4)); /**/ } else if (content_0 == 4) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\n", ((content_1) ? "+" : "-"), content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\n", ((content_1) ? "+" : "-"), content_2, content_3, content_4)); /**/ } else if (content_0 == 5) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\n", content_1, content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\n", content_1, content_2, content_3, content_4)); /**/ } } - - else if(dbg_num == 5) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] (( UP)) Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\n", content_1, content_2, content_3, content_4)); - } else if(content_0 == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((DOWN)) Nsc=(( %d )), N_Low=(( %d ))\n", content_1, content_2)); - } else if(content_0 == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((HOLD)) Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n", content_1, content_2, content_3, content_4)); - } - } - else if(dbg_num == 0x60) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) macid=((%d)), BUPDATE[macid]=((%d))\n", content_1, content_2)); - } else if(content_0 == 4) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n", content_1, content_2, content_3, content_4)); - } else if(content_0 == 5) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n", content_1, content_2, content_3, content_4)); - } + + else if (dbg_num == 5) { + if (content_0 == 1) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] (( UP)) Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\n", content_1, content_2, content_3, content_4)); + else if (content_0 == 2) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((DOWN)) Nsc=(( %d )), N_Low=(( %d ))\n", content_1, content_2)); + else if (content_0 == 3) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((HOLD)) Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n", content_1, content_2, content_3, content_4)); + } else if (dbg_num == 0x60) { + if (content_0 == 1) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) macid=((%d)), BUPDATE[macid]=((%d))\n", content_1, content_2)); + else if (content_0 == 4) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n", content_1, content_2, content_3, content_4)); + else if (content_0 == 5) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n", content_1, content_2, content_3, content_4)); } - } + } /*--------------------------------------------*/ - else if (function == INIT_RA_TABLE){ - if(dbg_num == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n", content_0)); - } - - } + else if (function == INIT_RA_TABLE) { + if (dbg_num == 3) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n", content_0)); + + } /*--------------------------------------------*/ else if (function == RATE_UP) { - if(dbg_num == 2) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Highest rate -> return)), macid=((%d)) Nsc=((%d))\n", content_1, content_2)); - } - } else if(dbg_num == 5) { + if (dbg_num == 2) { + if (content_0 == 1) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Highest rate->return)), macid=((%d)) Nsc=((%d))\n", content_1, content_2)); + } else if (dbg_num == 5) { if (content_0 == 0) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)), SGI=((%d))\n", content_1, content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)), SGI=((%d))\n", content_1, content_2, content_3, content_4)); else if (content_0 == 1) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n", content_1, content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n", content_1, content_2, content_3, content_4)); } - - } + + } /*--------------------------------------------*/ else if (function == RATE_DOWN) { - if(dbg_num == 5) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDownStep] ((Rate Down)), macid=((%d)), rate1=((0x%x)), rate2=((0x%x)), BW=((%d))\n", content_1, content_2, content_3, content_4)); - } + if (dbg_num == 5) { + if (content_0 == 1) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDownStep] ((rate Down)), macid=((%d)), rate1=((0x%x)), rate2=((0x%x)), BW=((%d))\n", content_1, content_2, content_3, content_4)); } } else if (function == TRY_DONE) { if (dbg_num == 1) { if (content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n", content_1, content_2)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n", content_1, content_2)); /**/ } } else if (dbg_num == 2) { if (content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try)) macid=((%d)), Try_Done_cnt=((%d)), rate_2=((%d)), try_succes=((%d))\n", content_1, content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try)) macid=((%d)), Try_Done_cnt=((%d)), rate_2=((%d)), try_succes=((%d))\n", content_1, content_2, content_3, content_4)); /**/ } } - } + } /*--------------------------------------------*/ else if (function == RA_H2C) { if (dbg_num == 1) { if (content_0 == 0) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x49] fw_trace_en=((%d)), mode =((%d)), macid=((%d))\n", content_1, content_2, content_3)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x49] fw_trace_en=((%d)), mode =((%d)), macid=((%d))\n", content_1, content_2, content_3)); /**/ - /*C2H_RA_Dbg_code(F_RA_H2C,1,0, SysMib.ODM.DEBUG.fw_trace_en, mode, macid , 0); //RA MASK*/ + /*C2H_RA_Dbg_code(F_RA_H2C,1,0, SysMib.ODM.DEBUG.fw_trace_en, mode, macid, 0); //RA MASK*/ } - #if 0 +#if 0 else if (dbg_num == 2) { - + if (content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] MACID=((%d)), Rate ID=((%d)), SGI=((%d)), BW=((%d))\n", content_1, content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] MACID=((%d)), rate ID=((%d)), SGI=((%d)), BW=((%d))\n", content_1, content_2, content_3, content_4)); /**/ } else if (content_0 == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] VHT_en=((%d)), Disable_PowerTraining=((%d)), Disable_RA=((%d)), No_Update=((%d))\n", content_1, content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] VHT_en=((%d)), Disable_PowerTraining=((%d)), Disable_RA=((%d)), No_Update=((%d))\n", content_1, content_2, content_3, content_4)); /**/ } else if (content_0 == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] RA_MSK=[%x | %x | %x | %x ]\n", content_1, content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] RA_MSK=[%x | %x | %x | %x ]\n", content_1, content_2, content_3, content_4)); /**/ } } - #endif +#endif } } /*--------------------------------------------*/ else if (function == F_RATE_AP_RPT) { - if(dbg_num == 1) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] ((1)), SPE_STATIS=((0x%x))---------->\n", content_3)); - } - } else if(dbg_num == 2) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] RTY_all=((%d))\n", content_1)); - } - } else if(dbg_num == 3) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); - } - } else if(dbg_num == 4) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); - } - } else if(dbg_num == 5) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); - } - } else if(dbg_num == 6) { - if(content_0 == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d],, PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); - } + if (dbg_num == 1) { + if (content_0 == 1) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] ((1)), SPE_STATIS=((0x%x))---------->\n", content_3)); + } else if (dbg_num == 2) { + if (content_0 == 1) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] RTY_all=((%d))\n", content_1)); + } else if (dbg_num == 3) { + if (content_0 == 1) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); + } else if (dbg_num == 4) { + if (content_0 == 1) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); + } else if (dbg_num == 5) { + if (content_0 == 1) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); + } else if (dbg_num == 6) { + if (content_0 == 1) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d],, PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); } } else { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4)); /**/ } #else - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4)); #endif /*--------------------------------------------*/ - +#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ } -VOID +void phydm_fw_trace_handler_8051( - IN PVOID pDM_VOID, - IN pu1Byte Buffer, - IN u1Byte CmdLen + void *p_dm_void, + u8 *buffer, + u8 cmd_len ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if CONFIG_PHYDM_DEBUG_FUNCTION + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if 0 - if (CmdLen >= 3) - CmdBuf[CmdLen - 1] = '\0'; - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", &(CmdBuf[3]))); + if (cmd_len >= 3) + cmd_buf[cmd_len - 1] = '\0'; + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", &(cmd_buf[3]))); #else int i = 0; - u1Byte Extend_c2hSubID = 0, Extend_c2hDbgLen = 0, Extend_c2hDbgSeq = 0; - u1Byte fw_debug_trace[128]; - pu1Byte Extend_c2hDbgContent = 0; + u8 extend_c2h_sub_id = 0, extend_c2h_dbg_len = 0, extend_c2h_dbg_seq = 0; + u8 fw_debug_trace[128]; + u8 *extend_c2h_dbg_content = 0; - if (CmdLen > 127) + if (cmd_len > 127) return; - Extend_c2hSubID = Buffer[0]; - Extend_c2hDbgLen = Buffer[1]; - Extend_c2hDbgContent = Buffer + 2; /*DbgSeq+DbgContent for show HEX*/ + extend_c2h_sub_id = buffer[0]; + extend_c2h_dbg_len = buffer[1]; + extend_c2h_dbg_content = buffer + 2; /*DbgSeq+DbgContent for show HEX*/ - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_DISP(FC2H, C2H_Summary, ("[Extend C2H packet], Extend_c2hSubId=0x%x, Extend_c2hDbgLen=%d\n", - Extend_c2hSubID, Extend_c2hDbgLen)); - - RT_DISP_DATA(FC2H, C2H_Summary, "[Extend C2H packet], Content Hex:", Extend_c2hDbgContent, CmdLen-2); - #endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISP(FC2H, C2H_Summary, ("[Extend C2H packet], Extend_c2hSubId=0x%x, extend_c2h_dbg_len=%d\n", + extend_c2h_sub_id, extend_c2h_dbg_len)); -GoBackforAggreDbgPkt: + RT_DISP_DATA(FC2H, C2H_Summary, "[Extend C2H packet], Content Hex:", extend_c2h_dbg_content, cmd_len - 2); +#endif + +go_backfor_aggre_dbg_pkt: i = 0; - Extend_c2hDbgSeq = Buffer[2]; - Extend_c2hDbgContent = Buffer + 3; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_DISP(FC2H, C2H_Summary, ("[RTKFW, SEQ= %d] :", Extend_c2hDbgSeq)); - #endif + extend_c2h_dbg_seq = buffer[2]; + extend_c2h_dbg_content = buffer + 3; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISP(FC2H, C2H_Summary, ("[RTKFW, SEQ= %d] :", extend_c2h_dbg_seq)); +#endif for (; ; i++) { - fw_debug_trace[i] = Extend_c2hDbgContent[i]; - if (Extend_c2hDbgContent[i + 1] == '\0') { + fw_debug_trace[i] = extend_c2h_dbg_content[i]; + if (extend_c2h_dbg_content[i + 1] == '\0') { fw_debug_trace[i + 1] = '\0'; - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); break; - } else if (Extend_c2hDbgContent[i] == '\n') { + } else if (extend_c2h_dbg_content[i] == '\n') { fw_debug_trace[i + 1] = '\0'; - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); - Buffer = Extend_c2hDbgContent + i + 3; - goto GoBackforAggreDbgPkt; + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); + buffer = extend_c2h_dbg_content + i + 3; + goto go_backfor_aggre_dbg_pkt; } } #endif +#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ } - - diff --git a/hal/phydm/phydm_debug.h b/hal/phydm/phydm_debug.h index c06cc00..5cd1ecf 100644 --- a/hal/phydm/phydm_debug.h +++ b/hal/phydm/phydm_debug.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __ODM_DBG_H__ @@ -25,97 +20,105 @@ /*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/ /*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/ #define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/ -//----------------------------------------------------------------------------- -// Define the debug levels -// -// 1. DBG_TRACE and DBG_LOUD are used for normal cases. -// So that, they can help SW engineer to develope or trace states changed -// and also help HW enginner to trace every operation to and from HW, -// e.g IO, Tx, Rx. -// -// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, -// which help us to debug SW or HW. -// -//----------------------------------------------------------------------------- -// -// Never used in a call to ODM_RT_TRACE()! -// +/* ----------------------------------------------------------------------------- + * Define the debug levels + * + * 1. DBG_TRACE and DBG_LOUD are used for normal cases. + * So that, they can help SW engineer to develope or trace states changed + * and also help HW enginner to trace every operation to and from HW, + * e.g IO, Tx, Rx. + * + * 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, + * which help us to debug SW or HW. + * + * ----------------------------------------------------------------------------- + * + * Never used in a call to ODM_RT_TRACE()! + * */ #define ODM_DBG_OFF 1 -// -// Fatal bug. -// For example, Tx/Rx/IO locked up, OS hangs, memory access violation, -// resource allocation failed, unexpected HW behavior, HW BUG and so on. -// +/* + * Fatal bug. + * For example, Tx/Rx/IO locked up, OS hangs, memory access violation, + * resource allocation failed, unexpected HW behavior, HW BUG and so on. + * */ #define ODM_DBG_SERIOUS 2 -// -// Abnormal, rare, or unexpeted cases. -// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. -// +/* + * Abnormal, rare, or unexpeted cases. + * For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. + * */ #define ODM_DBG_WARNING 3 -// -// Normal case with useful information about current SW or HW state. -// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, -// SW protocol state change, dynamic mechanism state change and so on. -// +/* + * Normal case with useful information about current SW or HW state. + * For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, + * SW protocol state change, dynamic mechanism state change and so on. + * */ #define ODM_DBG_LOUD 4 -// -// Normal case with detail execution flow or information. -// +/* + * Normal case with detail execution flow or information. + * */ #define ODM_DBG_TRACE 5 /*FW DBG MSG*/ -#define RATE_DECISION BIT0 -#define INIT_RA_TABLE BIT1 -#define RATE_UP BIT2 -#define RATE_DOWN BIT3 -#define TRY_DONE BIT4 -#define RA_H2C BIT5 -#define F_RATE_AP_RPT BIT7 - -//----------------------------------------------------------------------------- -// Define the tracing components -// -//----------------------------------------------------------------------------- -//BB Functions -#define ODM_COMP_DIG BIT0 -#define ODM_COMP_RA_MASK BIT1 -#define ODM_COMP_DYNAMIC_TXPWR BIT2 -#define ODM_COMP_FA_CNT BIT3 -#define ODM_COMP_RSSI_MONITOR BIT4 -#define ODM_COMP_SNIFFER BIT5 -#define ODM_COMP_ANT_DIV BIT6 -#define ODM_COMP_DFS BIT7 -#define ODM_COMP_NOISY_DETECT BIT8 -#define ODM_COMP_RATE_ADAPTIVE BIT9 -#define ODM_COMP_PATH_DIV BIT10 -#define ODM_COMP_CCX BIT11 - -#define ODM_COMP_DYNAMIC_PRICCA BIT12 - /*BIT13 TBD*/ -#define ODM_COMP_MP BIT14 -#define ODM_COMP_CFO_TRACKING BIT15 -#define ODM_COMP_ACS BIT16 -#define PHYDM_COMP_ADAPTIVITY BIT17 -#define PHYDM_COMP_RA_DBG BIT18 -#define PHYDM_COMP_TXBF BIT19 -//MAC Functions -#define ODM_COMP_EDCA_TURBO BIT20 - /*BIT21 TBD*/ -#define ODM_FW_DEBUG_TRACE BIT22 -//RF Functions - /*BIT23 TBD*/ -#define ODM_COMP_TX_PWR_TRACK BIT24 -#define ODM_COMP_RX_GAIN_TRACK BIT25 -#define ODM_COMP_CALIBRATION BIT26 -//Common Functions -#define ODM_PHY_CONFIG BIT28 -#define ODM_COMP_INIT BIT29 -#define ODM_COMP_COMMON BIT30 -#define ODM_COMP_API BIT31 +#define RATE_DECISION BIT(0) +#define INIT_RA_TABLE BIT(1) +#define RATE_UP BIT(2) +#define RATE_DOWN BIT(3) +#define TRY_DONE BIT(4) +#define RA_H2C BIT(5) +#define F_RATE_AP_RPT BIT(7) + +/* ----------------------------------------------------------------------------- + * Define the tracing components + * + * ----------------------------------------------------------------------------- + *BB FW Functions*/ +#define PHYDM_FW_COMP_RA BIT(0) +#define PHYDM_FW_COMP_MU BIT(1) +#define PHYDM_FW_COMP_PATH_DIV BIT(2) +#define PHYDM_FW_COMP_PHY_CONFIG BIT(3) + + +/*BB Driver Functions*/ +#define ODM_COMP_DIG BIT(0) +#define ODM_COMP_RA_MASK BIT(1) +#define ODM_COMP_DYNAMIC_TXPWR BIT(2) +#define ODM_COMP_FA_CNT BIT(3) +#define ODM_COMP_RSSI_MONITOR BIT(4) +#define ODM_COMP_SNIFFER BIT(5) +#define ODM_COMP_ANT_DIV BIT(6) +#define ODM_COMP_DFS BIT(7) +#define ODM_COMP_NOISY_DETECT BIT(8) +#define ODM_COMP_RATE_ADAPTIVE BIT(9) +#define ODM_COMP_PATH_DIV BIT(10) +#define ODM_COMP_CCX BIT(11) + +#define ODM_COMP_DYNAMIC_PRICCA BIT(12) +/*BIT13 TBD*/ +#define ODM_COMP_MP BIT(14) +#define ODM_COMP_CFO_TRACKING BIT(15) +#define ODM_COMP_ACS BIT(16) +#define PHYDM_COMP_ADAPTIVITY BIT(17) +#define PHYDM_COMP_RA_DBG BIT(18) +#define PHYDM_COMP_TXBF BIT(19) +/* MAC Functions */ +#define ODM_COMP_EDCA_TURBO BIT(20) +#define ODM_COMP_DYNAMIC_RX_PATH BIT(21) +#define ODM_FW_DEBUG_TRACE BIT(22) +/* RF Functions */ +/*BIT23 TBD*/ +#define ODM_COMP_TX_PWR_TRACK BIT(24) +/*BIT25 TBD*/ +#define ODM_COMP_CALIBRATION BIT(26) +/* Common Functions */ +/*BIT27 TBD*/ +#define ODM_PHY_CONFIG BIT(28) +#define ODM_COMP_INIT BIT(29) +#define ODM_COMP_COMMON BIT(30) +#define ODM_COMP_API BIT(31) /*------------------------Export Marco Definition---------------------------*/ @@ -123,14 +126,24 @@ #define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define RT_PRINTK DbgPrint + #define dbg_print DbgPrint + #define dcmd_printf DCMD_Printf + #define dcmd_scanf DCMD_Scanf + #define RT_PRINTK dbg_print +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + #define dbg_print(args...) + #define RT_PRINTK(fmt, args...) \ + RT_TRACE(((struct rtl_priv *)p_dm_odm->adapter), \ + COMP_PHYDM, DBG_DMESG, fmt, ## args) + #define RT_DISP(dbgtype, dbgflag, printstr) #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #define DbgPrint printk - #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); + #define dbg_print printk + #define RT_PRINTK(fmt, args...) dbg_print(fmt, ## args) #define RT_DISP(dbgtype, dbgflag, printstr) #else - #define DbgPrint panic_printk - #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); + #define dbg_print panic_printk + /*#define RT_PRINTK(fmt, args...) dbg_print("%s(): " fmt, __FUNCTION__, ## args);*/ + #define RT_PRINTK(args...) dbg_print(args) #endif #ifndef ASSERT @@ -138,97 +151,130 @@ #endif #if DBG -#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ +#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt) \ do { \ - if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel || level == ODM_DBG_SERIOUS)) \ - { \ - if (pDM_Odm->SupportICType == ODM_RTL8188E) \ - DbgPrint("[PhyDM-8188E] "); \ - else if(pDM_Odm->SupportICType == ODM_RTL8192E) \ - DbgPrint("[PhyDM-8192E] "); \ - else if(pDM_Odm->SupportICType == ODM_RTL8812) \ - DbgPrint("[PhyDM-8812A] "); \ - else if(pDM_Odm->SupportICType == ODM_RTL8821) \ - DbgPrint("[PhyDM-8821A] "); \ - else if(pDM_Odm->SupportICType == ODM_RTL8814A) \ - DbgPrint("[PhyDM-8814A] "); \ - else if(pDM_Odm->SupportICType == ODM_RTL8703B) \ - DbgPrint("[PhyDM-8703B] "); \ - else if(pDM_Odm->SupportICType == ODM_RTL8822B) \ - DbgPrint("[PhyDM-8822B] "); \ - else if (pDM_Odm->SupportICType == ODM_RTL8188F) \ - DbgPrint("[PhyDM-8188F] "); \ + if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level || level == ODM_DBG_SERIOUS)) { \ + \ + if (p_dm_odm->support_ic_type == ODM_RTL8188E) \ + dbg_print("[PhyDM-8188E] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8192E) \ + dbg_print("[PhyDM-8192E] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8812) \ + dbg_print("[PhyDM-8812A] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8821) \ + dbg_print("[PhyDM-8821A] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8814A) \ + dbg_print("[PhyDM-8814A] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8703B) \ + dbg_print("[PhyDM-8703B] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8822B) \ + dbg_print("[PhyDM-8822B] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8188F) \ + dbg_print("[PhyDM-8188F] "); \ RT_PRINTK fmt; \ } \ } while (0) -#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \ - if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ - { \ +#define ODM_RT_TRACE_F(p_dm_odm, comp, level, fmt) do {\ + if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level)) { \ + \ RT_PRINTK fmt; \ - } + } \ + } while (0) + -#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ - if(!(expr)) { \ - DbgPrint( "Assertion failed! %s at ......\n", #expr); \ - DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \ +#define ODM_RT_ASSERT(p_dm_odm, expr, fmt) do {\ + if (!(expr)) { \ + dbg_print("Assertion failed! %s at ......\n", #expr); \ + dbg_print(" ......%s,%s, line=%d\n", __FILE__, __FUNCTION__, __LINE__); \ RT_PRINTK fmt; \ - ASSERT(FALSE); \ - } -#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); } -#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); } -#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); } - -#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \ - if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ - { \ - int __i; \ - pu1Byte __ptr = (pu1Byte)ptr; \ - DbgPrint("[ODM] "); \ - DbgPrint(title_str); \ - DbgPrint(" "); \ - for( __i=0; __i<6; __i++ ) \ - DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \ - DbgPrint("\n"); \ - } + ASSERT(false); \ + } \ + } while (0) + +#define ODM_dbg_enter() { dbg_print(" == > %s\n", __FUNCTION__); } +#define ODM_dbg_exit() { dbg_print("< == %s\n", __FUNCTION__); } +#define ODM_dbg_trace(str) { dbg_print("%s:%s\n", __FUNCTION__, str); } + +#define ODM_PRINT_ADDR(p_dm_odm, comp, level, title_str, ptr) do {\ + if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level)) { \ + \ + int __i; \ + u8 *__ptr = (u8 *)ptr; \ + dbg_print("[ODM] "); \ + dbg_print(title_str); \ + dbg_print(" "); \ + for (__i = 0; __i < 6; __i++) \ + dbg_print("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \ + dbg_print("\n"); \ + } \ + } while (0) + #else -#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) -#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) -#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) +#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt) +#define ODM_RT_TRACE_F(p_dm_odm, comp, level, fmt) +#define ODM_RT_ASSERT(p_dm_odm, expr, fmt) #define ODM_dbg_enter() #define ODM_dbg_exit() #define ODM_dbg_trace(str) -#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) +#define ODM_PRINT_ADDR(p_dm_odm, comp, level, title_str, ptr) #endif +#define BB_DBGPORT_PRIORITY_3 3 /*Debug function (the highest priority)*/ +#define BB_DBGPORT_PRIORITY_2 2 /*Check hang function & Strong function*/ +#define BB_DBGPORT_PRIORITY_1 1 /*Watch dog function*/ +#define BB_DBGPORT_RELEASE 0 /*Init value (the lowest priority)*/ -VOID -PHYDM_InitDebugSetting(IN PDM_ODM_T pDM_Odm); +void +phydm_init_debug_setting(struct PHY_DM_STRUCT *p_dm_odm); -VOID phydm_BasicDbgMessage( IN PVOID pDM_VOID); +void +phydm_bb_dbg_port_header_sel( + void *p_dm_void, + u32 header_idx +); + +u8 +phydm_set_bb_dbg_port( + void *p_dm_void, + u8 curr_dbg_priority, + u32 debug_port +); + +void +phydm_release_bb_dbg_port( + void *p_dm_void +); + +u32 +phydm_get_bb_dbg_port_value( + void *p_dm_void +); + +void phydm_basic_dbg_message(void *p_dm_void); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #define PHYDM_DBGPRINT 0 -#define PHYDM_SSCANF(x, y, z) DCMD_Scanf(x, y, z) +#define PHYDM_SSCANF(x, y, z) dcmd_scanf(x, y, z) #define PHYDM_VAST_INFO_SNPRINTF PHYDM_SNPRINTF #if (PHYDM_DBGPRINT == 1) #define PHYDM_SNPRINTF(msg) \ - do {\ - rsprintf msg;\ - DbgPrint(output);\ - } while (0) + do {\ + rsprintf msg;\ + dbg_print(output);\ + } while (0) #else #define PHYDM_SNPRINTF(msg) \ - do {\ - rsprintf msg;\ - DCMD_Printf(output);\ - } while (0) + do {\ + rsprintf msg;\ + dcmd_printf(output);\ + } while (0) #endif #else #if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__) -#define PHYDM_DBGPRINT 0 + #define PHYDM_DBGPRINT 0 #else -#define PHYDM_DBGPRINT 1 + #define PHYDM_DBGPRINT 1 #endif #define MAX_ARGC 20 #define MAX_ARGV 16 @@ -239,96 +285,104 @@ VOID phydm_BasicDbgMessage( IN PVOID pDM_VOID); #define PHYDM_SSCANF(x, y, z) sscanf(x, y, z) #define PHYDM_VAST_INFO_SNPRINTF(msg)\ - do {\ - snprintf msg;\ - DbgPrint(output);\ - } while (0) + do {\ + snprintf msg;\ + dbg_print(output);\ + } while (0) #if (PHYDM_DBGPRINT == 1) #define PHYDM_SNPRINTF(msg)\ - do {\ - snprintf msg;\ - DbgPrint(output);\ - } while (0) + do {\ + snprintf msg;\ + dbg_print(output);\ + } while (0) #else #define PHYDM_SNPRINTF(msg)\ - do {\ - if(out_len > used)\ - used+=snprintf msg;\ - } while (0) + do {\ + if (out_len > used)\ + used += snprintf msg;\ + } while (0) #endif #endif -VOID phydm_BasicProfile( - IN PVOID pDM_VOID, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ); -#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) -s4Byte +void phydm_basic_profile( + void *p_dm_void, + u32 *_used, + char *output, + u32 *_out_len +); +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) +s32 phydm_cmd( - IN PDM_ODM_T pDM_Odm, - IN char *input, - IN u4Byte in_len, - IN u1Byte flag, - OUT char *output, - IN u4Byte out_len + struct PHY_DM_STRUCT *p_dm_odm, + char *input, + u32 in_len, + u8 flag, + char *output, + u32 out_len ); #endif -VOID +void phydm_cmd_parser( - IN PDM_ODM_T pDM_Odm, - IN char input[][16], - IN u4Byte input_num, - IN u1Byte flag, - OUT char *output, - IN u4Byte out_len + struct PHY_DM_STRUCT *p_dm_odm, + char input[][16], + u32 input_num, + u8 flag, + char *output, + u32 out_len +); + +boolean +phydm_api_trx_mode( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_path_e tx_path, + enum odm_rf_path_e rx_path, + boolean is_tx2_path ); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void phydm_sbd_check( - IN PDM_ODM_T pDM_Odm - ); + struct PHY_DM_STRUCT *p_dm_odm +); void phydm_sbd_callback( - PRT_TIMER pTimer - ); + struct timer_list *p_timer +); void phydm_sbd_workitem_callback( - IN PVOID pContext - ); + void *p_context +); #endif -VOID +void phydm_fw_trace_en_h2c( - IN PVOID pDM_VOID, - IN BOOLEAN enable, - IN u4Byte monitor_mode, - IN u4Byte macid + void *p_dm_void, + boolean enable, + u32 fw_debug_component, + u32 monitor_mode, + u32 macid ); -VOID +void phydm_fw_trace_handler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len ); -VOID +void phydm_fw_trace_handler_code( - IN PVOID pDM_VOID, - IN pu1Byte Buffer, - IN u1Byte CmdLen + void *p_dm_void, + u8 *buffer, + u8 cmd_len ); -VOID +void phydm_fw_trace_handler_8051( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len ); -#endif // __ODM_DBG_H__ - +#endif /* __ODM_DBG_H__ */ diff --git a/hal/phydm/phydm_dfs.c b/hal/phydm/phydm_dfs.c index b648231..297f973 100644 --- a/hal/phydm/phydm_dfs.c +++ b/hal/phydm/phydm_dfs.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* ============================================================ @@ -28,231 +23,247 @@ #include "phydm_precomp.h" #if defined(CONFIG_PHYDM_DFS_MASTER) -VOID phydm_radar_detect_reset(PVOID pDM_VOID) +void phydm_radar_detect_reset(void *p_dm_void) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0); - ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 1); + odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 0); + odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 1); } -VOID phydm_radar_detect_disable(PVOID pDM_VOID) +void phydm_radar_detect_disable(void *p_dm_void) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0); + odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 0); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("\n")); } -static VOID phydm_radar_detect_with_dbg_parm(PVOID pDM_VOID) +static void phydm_radar_detect_with_dbg_parm(void *p_dm_void) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, pDM_Odm->radar_detect_reg_918); - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, pDM_Odm->radar_detect_reg_91c); - ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, pDM_Odm->radar_detect_reg_920); - ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, pDM_Odm->radar_detect_reg_924); + odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, p_dm_odm->radar_detect_reg_918); + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, p_dm_odm->radar_detect_reg_91c); + odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, p_dm_odm->radar_detect_reg_920); + odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, p_dm_odm->radar_detect_reg_924); } /* Init radar detection parameters, called after ch, bw is set */ -VOID phydm_radar_detect_enable(PVOID pDM_VOID) +void phydm_radar_detect_enable(void *p_dm_void) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte region_domain = pDM_Odm->DFS_RegionDomain; - u1Byte c_channel = *(pDM_Odm->pChannel); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 region_domain = p_dm_odm->dfs_region_domain; + u8 c_channel = *(p_dm_odm->p_channel); + u8 band_width = *(p_dm_odm->p_band_width); + u8 enable = 0; if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n")); - return; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n")); + goto exit; } - if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) { + if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) { - ODM_SetBBReg(pDM_Odm, 0x814, 0x3fffffff, 0x04cc4d10); - ODM_SetBBReg(pDM_Odm, 0x834, bMaskByte0, 0x06); + odm_set_bb_reg(p_dm_odm, 0x814, 0x3fffffff, 0x04cc4d10); + odm_set_bb_reg(p_dm_odm, 0x834, MASKBYTE0, 0x06); - if (pDM_Odm->radar_detect_dbg_parm_en) { - phydm_radar_detect_with_dbg_parm(pDM_Odm); + if (p_dm_odm->radar_detect_dbg_parm_en) { + phydm_radar_detect_with_dbg_parm(p_dm_odm); + enable = 1; goto exit; } if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { - ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c17ecdf); - ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x01528500); - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0fa21a20); - ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0f69204); + odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c17ecdf); + odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x01528500); + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0fa21a20); + odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0f69204); } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) { - ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x01528500); - ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67234); + odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x01528500); + odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67234); if (c_channel >= 52 && c_channel <= 64) { - ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16ecdf); - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0f141a20); + odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16ecdf); + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0f141a20); } else { - ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16acdf); - if (pDM_Odm->pBandWidth == ODM_BW20M) - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x64721a20); + odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16acdf); + if (band_width == ODM_BW20M) + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64721a20); else - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68721a20); + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68721a20); } } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { - ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16acdf); - ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x01528500); - ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67231); - if (pDM_Odm->pBandWidth == ODM_BW20M) - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x64741a20); + odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16acdf); + odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x01528500); + odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67231); + if (band_width == ODM_BW20M) + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64741a20); else - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68741a20); + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68741a20); + } else { /* not supported */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported DFS_RegionDomain:%d\n", region_domain)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported dfs_region_domain:%d\n", region_domain)); + goto exit; } - } else if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) { - - ODM_SetBBReg(pDM_Odm, 0x814, 0x3fffffff, 0x04cc4d10); - ODM_SetBBReg(pDM_Odm, 0x834, bMaskByte0, 0x06); - + } else if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) { + + odm_set_bb_reg(p_dm_odm, 0x814, 0x3fffffff, 0x04cc4d10); + odm_set_bb_reg(p_dm_odm, 0x834, MASKBYTE0, 0x06); + /* 8822B only, when BW = 20M, DFIR output is 40Mhz, but DFS input is 80MMHz, so it need to upgrade to 80MHz */ - if (pDM_Odm->SupportICType & ODM_RTL8822B) { - if (pDM_Odm->pBandWidth == ODM_BW20M) - ODM_SetBBReg(pDM_Odm, 0x1984, BIT26, 1); + if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + if (band_width == ODM_BW20M) + odm_set_bb_reg(p_dm_odm, 0x1984, BIT(26), 1); else - ODM_SetBBReg(pDM_Odm, 0x1984, BIT26, 0); + odm_set_bb_reg(p_dm_odm, 0x1984, BIT(26), 0); } - if (pDM_Odm->radar_detect_dbg_parm_en) { - phydm_radar_detect_with_dbg_parm(pDM_Odm); + if (p_dm_odm->radar_detect_dbg_parm_en) { + phydm_radar_detect_with_dbg_parm(p_dm_odm); + enable = 1; goto exit; } if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { - ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16acdf); - ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x095a8500); - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0fa21a20); - ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0f57204); + odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16acdf); + odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x095a8500); + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0fa21a20); + odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0f57204); } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) { - ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x095a8500); - ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67234); + odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x095a8500); + odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67234); if (c_channel >= 52 && c_channel <= 64) { - ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16ecdf); - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0f141a20); + odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16ecdf); + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0f141a20); } else { - ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c166cdf); - if (pDM_Odm->pBandWidth == ODM_BW20M) - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x64721a20); + odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c166cdf); + if (band_width == ODM_BW20M) + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64721a20); else - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68721a20); + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68721a20); } + } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { - ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c166cdf); - ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x095a8500); - ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67231); - if (pDM_Odm->pBandWidth == ODM_BW20M) - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x64741a20); + odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c166cdf); + odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x095a8500); + odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67231); + if (band_width == ODM_BW20M) + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64741a20); else - ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68741a20); + odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68741a20); + } else { /* not supported */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported DFS_RegionDomain:%d\n", region_domain)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported dfs_region_domain:%d\n", region_domain)); + goto exit; } } else { /* not supported IC type*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported IC Type:%d\n", pDM_Odm->SupportICType)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported IC type:%d\n", p_dm_odm->support_ic_type)); + goto exit; } + enable = 1; + exit: - phydm_radar_detect_reset(pDM_Odm); + if (enable) { + phydm_radar_detect_reset(p_dm_odm); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("on cch:%u, bw:%u\n", c_channel, band_width)); + } else + phydm_radar_detect_disable(p_dm_odm); } -BOOLEAN phydm_radar_detect(PVOID pDM_VOID) +boolean phydm_radar_detect(void *p_dm_void) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN enable_DFS = FALSE; - BOOLEAN radar_detected = FALSE; - u1Byte region_domain = pDM_Odm->DFS_RegionDomain; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + boolean enable_DFS = false; + boolean radar_detected = false; + u8 region_domain = p_dm_odm->dfs_region_domain; if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n")); - return FALSE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n")); + return false; } - if (ODM_GetBBReg(pDM_Odm , 0x924, BIT15)) - enable_DFS = TRUE; + if (odm_get_bb_reg(p_dm_odm, 0x924, BIT(15))) + enable_DFS = true; - if ((ODM_GetBBReg(pDM_Odm , 0xf98, BIT17)) - || (!(region_domain == PHYDM_DFS_DOMAIN_ETSI) && (ODM_GetBBReg(pDM_Odm , 0xf98, BIT19)))) - radar_detected = TRUE; + if ((odm_get_bb_reg(p_dm_odm, 0xf98, BIT(17))) + || (!(region_domain == PHYDM_DFS_DOMAIN_ETSI) && (odm_get_bb_reg(p_dm_odm, 0xf98, BIT(19))))) + radar_detected = true; if (enable_DFS && radar_detected) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD , ("Radar detect: enable_DFS:%d, radar_detected:%d\n" , enable_DFS, radar_detected)); - phydm_radar_detect_reset(pDM_Odm); + phydm_radar_detect_reset(p_dm_odm); } exit: - return (enable_DFS && radar_detected); + return enable_DFS && radar_detected; } #endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ -BOOLEAN +boolean phydm_dfs_master_enabled( - IN PVOID pDM_VOID - ) + void *p_dm_void +) { #ifdef CONFIG_PHYDM_DFS_MASTER - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - return *pDM_Odm->dfs_master_enabled ? TRUE : FALSE; + return *p_dm_odm->dfs_master_enabled ? true : false; #else - return FALSE; + return false; #endif } -VOID +void phydm_dfs_debug( - IN PVOID pDM_VOID, - IN u4Byte *const argv, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) + void *p_dm_void, + u32 *const argv, + u32 *_used, + char *output, + u32 *_out_len +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte used = *_used; - u4Byte out_len = *_out_len; +#if defined(CONFIG_PHYDM_DFS_MASTER) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 used = *_used; + u32 out_len = *_out_len; switch (argv[0]) { case 1: - #if defined(CONFIG_PHYDM_DFS_MASTER) /* set dbg parameters for radar detection instead of the default value */ if (argv[1] == 1) { - pDM_Odm->radar_detect_reg_918 = argv[2]; - pDM_Odm->radar_detect_reg_91c = argv[3]; - pDM_Odm->radar_detect_reg_920 = argv[4]; - pDM_Odm->radar_detect_reg_924 = argv[5]; - pDM_Odm->radar_detect_dbg_parm_en = 1; - - PHYDM_SNPRINTF((output+used, out_len-used, "Radar detection with dbg parameter\n")); - PHYDM_SNPRINTF((output+used, out_len-used, "reg918:0x%08X\n", pDM_Odm->radar_detect_reg_918)); - PHYDM_SNPRINTF((output+used, out_len-used, "reg91c:0x%08X\n", pDM_Odm->radar_detect_reg_91c)); - PHYDM_SNPRINTF((output+used, out_len-used, "reg920:0x%08X\n", pDM_Odm->radar_detect_reg_920)); - PHYDM_SNPRINTF((output+used, out_len-used, "reg924:0x%08X\n", pDM_Odm->radar_detect_reg_924)); + p_dm_odm->radar_detect_reg_918 = argv[2]; + p_dm_odm->radar_detect_reg_91c = argv[3]; + p_dm_odm->radar_detect_reg_920 = argv[4]; + p_dm_odm->radar_detect_reg_924 = argv[5]; + p_dm_odm->radar_detect_dbg_parm_en = 1; + + PHYDM_SNPRINTF((output + used, out_len - used, "Radar detection with dbg parameter\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "reg918:0x%08X\n", p_dm_odm->radar_detect_reg_918)); + PHYDM_SNPRINTF((output + used, out_len - used, "reg91c:0x%08X\n", p_dm_odm->radar_detect_reg_91c)); + PHYDM_SNPRINTF((output + used, out_len - used, "reg920:0x%08X\n", p_dm_odm->radar_detect_reg_920)); + PHYDM_SNPRINTF((output + used, out_len - used, "reg924:0x%08X\n", p_dm_odm->radar_detect_reg_924)); } else { - pDM_Odm->radar_detect_dbg_parm_en = 0; - PHYDM_SNPRINTF((output+used, out_len-used, "Radar detection with default parameter\n")); + p_dm_odm->radar_detect_dbg_parm_en = 0; + PHYDM_SNPRINTF((output + used, out_len - used, "Radar detection with default parameter\n")); } - phydm_radar_detect_enable(pDM_Odm); - #endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ + phydm_radar_detect_enable(p_dm_odm); break; default: break; } +#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ } - diff --git a/hal/phydm/phydm_dfs.h b/hal/phydm/phydm_dfs.h index 9a625bb..6856e25 100644 --- a/hal/phydm/phydm_dfs.h +++ b/hal/phydm/phydm_dfs.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PHYDM_DFS_H__ #define __PHYDM_DFS_H__ @@ -24,7 +19,7 @@ #define DFS_VERSION "0.0" /* ============================================================ - Definition + Definition ============================================================ */ @@ -39,38 +34,37 @@ ============================================================ */ -typedef enum _tag_PhyDM_DFS_REGION_DOMAIN { +enum phydm_dfs_region_domain { PHYDM_DFS_DOMAIN_UNKNOWN = 0, PHYDM_DFS_DOMAIN_FCC = 1, PHYDM_DFS_DOMAIN_MKK = 2, PHYDM_DFS_DOMAIN_ETSI = 3, -} PHYDM_DFS_REGION_DOMAIN; +}; -/* +/* ============================================================ function prototype ============================================================ */ #if defined(CONFIG_PHYDM_DFS_MASTER) -VOID phydm_radar_detect_reset(PVOID pDM_VOID); -VOID phydm_radar_detect_disable(PVOID pDM_VOID); -VOID phydm_radar_detect_enable(PVOID pDM_VOID); -BOOLEAN phydm_radar_detect(PVOID pDM_VOID); + void phydm_radar_detect_reset(void *p_dm_void); + void phydm_radar_detect_disable(void *p_dm_void); + void phydm_radar_detect_enable(void *p_dm_void); + boolean phydm_radar_detect(void *p_dm_void); #endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ -BOOLEAN +boolean phydm_dfs_master_enabled( - IN PVOID pDM_VOID - ); + void *p_dm_void +); -VOID +void phydm_dfs_debug( - IN PVOID pDM_VOID, - IN u4Byte *const argv, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ); + void *p_dm_void, + u32 *const argv, + u32 *_used, + char *output, + u32 *_out_len +); #endif /*#ifndef __PHYDM_DFS_H__ */ - diff --git a/hal/phydm/phydm_dig.c b/hal/phydm/phydm_dig.c index 1c1a077..ccaae50 100644 --- a/hal/phydm/phydm_dig.c +++ b/hal/phydm/phydm_dig.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,99 +11,84 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" -VOID -ODM_ChangeDynamicInitGainThresh( - IN PVOID pDM_VOID, - IN u4Byte DM_Type, - IN u4Byte DM_Value - ) +void +odm_change_dynamic_init_gain_thresh( + void *p_dm_void, + u32 dm_type, + u32 dm_value +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - - if (DM_Type == DIG_TYPE_THRESH_HIGH) - { - pDM_DigTable->RssiHighThresh = DM_Value; - } - else if (DM_Type == DIG_TYPE_THRESH_LOW) - { - pDM_DigTable->RssiLowThresh = DM_Value; - } - else if (DM_Type == DIG_TYPE_ENABLE) - { - pDM_DigTable->Dig_Enable_Flag = TRUE; - } - else if (DM_Type == DIG_TYPE_DISABLE) - { - pDM_DigTable->Dig_Enable_Flag = FALSE; - } - else if (DM_Type == DIG_TYPE_BACKOFF) - { - if(DM_Value > 30) - DM_Value = 30; - pDM_DigTable->BackoffVal = (u1Byte)DM_Value; - } - else if(DM_Type == DIG_TYPE_RX_GAIN_MIN) - { - if(DM_Value == 0) - DM_Value = 0x1; - pDM_DigTable->rx_gain_range_min = (u1Byte)DM_Value; - } - else if(DM_Type == DIG_TYPE_RX_GAIN_MAX) - { - if(DM_Value > 0x50) - DM_Value = 0x50; - pDM_DigTable->rx_gain_range_max = (u1Byte)DM_Value; - } -} // DM_ChangeDynamicInitGainThresh // - -int -getIGIForDiff(int value_IGI) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + + if (dm_type == DIG_TYPE_THRESH_HIGH) + p_dm_dig_table->rssi_high_thresh = dm_value; + else if (dm_type == DIG_TYPE_THRESH_LOW) + p_dm_dig_table->rssi_low_thresh = dm_value; + else if (dm_type == DIG_TYPE_ENABLE) + p_dm_dig_table->dig_enable_flag = true; + else if (dm_type == DIG_TYPE_DISABLE) + p_dm_dig_table->dig_enable_flag = false; + else if (dm_type == DIG_TYPE_BACKOFF) { + if (dm_value > 30) + dm_value = 30; + p_dm_dig_table->backoff_val = (u8)dm_value; + } else if (dm_type == DIG_TYPE_RX_GAIN_MIN) { + if (dm_value == 0) + dm_value = 0x1; + p_dm_dig_table->rx_gain_range_min = (u8)dm_value; + } else if (dm_type == DIG_TYPE_RX_GAIN_MAX) { + if (dm_value > 0x50) + dm_value = 0x50; + p_dm_dig_table->rx_gain_range_max = (u8)dm_value; + } +} /* dm_change_dynamic_init_gain_thresh */ + +int +get_igi_for_diff(int value_IGI) { - #define ONERCCA_LOW_TH 0x30 - #define ONERCCA_LOW_DIFF 8 +#define ONERCCA_LOW_TH 0x30 +#define ONERCCA_LOW_DIFF 8 if (value_IGI < ONERCCA_LOW_TH) { if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) return ONERCCA_LOW_TH; else return value_IGI + ONERCCA_LOW_DIFF; - } else { + } else return value_IGI; - } } -VOID -odm_FAThresholdCheck( - IN PVOID pDM_VOID, - IN BOOLEAN bDFSBand, - IN BOOLEAN bPerformance, - IN u4Byte RxTp, - IN u4Byte TxTp, - OUT u4Byte* dm_FA_thres - ) +void +odm_fa_threshold_check( + void *p_dm_void, + boolean is_dfs_band, + boolean is_performance, + u32 rx_tp, + u32 tx_tp, + u32 *dm_FA_thres +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if(pDM_Odm->bLinked && (bPerformance||bDFSBand)) - { + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->is_linked && (is_performance || is_dfs_band)) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) /*For AP*/ - if ((RxTp>>2) > TxTp && RxTp < 10000 && RxTp > 500) { /*10Mbps & 0.5Mbps*/ +#if (DIG_HW == 1) + dm_FA_thres[0] = p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_th1; + dm_FA_thres[1] = p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_th2; + dm_FA_thres[2] = p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_th3; +#else + if ((rx_tp >> 2) > tx_tp && rx_tp < 10000 && rx_tp > 500) { /*10Mbps & 0.5Mbps*/ dm_FA_thres[0] = 0x080; dm_FA_thres[1] = 0x100; dm_FA_thres[2] = 0x200; @@ -112,6 +97,7 @@ odm_FAThresholdCheck( dm_FA_thres[1] = 0x200; dm_FA_thres[2] = 0x300; } +#endif #else /*For NIC*/ dm_FA_thres[0] = DM_DIG_FA_TH0; @@ -119,15 +105,13 @@ odm_FAThresholdCheck( dm_FA_thres[2] = DM_DIG_FA_TH2; #endif } else { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) - if(bDFSBand) - { - // For DFS band and no link +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + if (is_dfs_band) { + /* For DFS band and no link */ dm_FA_thres[0] = 250; dm_FA_thres[1] = 1000; dm_FA_thres[2] = 2000; - } - else + } else #endif { dm_FA_thres[0] = 2000; @@ -138,464 +122,440 @@ odm_FAThresholdCheck( return; } -u1Byte -odm_ForbiddenIGICheck( - IN PVOID pDM_VOID, - IN u1Byte DIG_Dynamic_MIN, - IN u1Byte CurrentIGI - ) +u8 +odm_forbidden_igi_check( + void *p_dm_void, + u8 dig_dynamic_min, + u8 current_igi +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - u1Byte rx_gain_range_min = pDM_DigTable->rx_gain_range_min; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + u8 rx_gain_range_min = p_dm_dig_table->rx_gain_range_min; - if (pDM_DigTable->LargeFA_Timeout) { - if (--pDM_DigTable->LargeFA_Timeout == 0) - pDM_DigTable->LargeFAHit = 0; + if (p_dm_dig_table->large_fa_timeout) { + if (--p_dm_dig_table->large_fa_timeout == 0) + p_dm_dig_table->large_fa_hit = 0; } - if (pFalseAlmCnt->Cnt_all > 10000) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case.\n")); + if (p_false_alm_cnt->cnt_all > 10000) { - if(pDM_DigTable->LargeFAHit != 3) - pDM_DigTable->LargeFAHit++; - - if(pDM_DigTable->ForbiddenIGI < CurrentIGI)//if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue) - { - pDM_DigTable->ForbiddenIGI = CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue; - pDM_DigTable->LargeFAHit = 1; - pDM_DigTable->LargeFA_Timeout = LARGE_FA_TIMEOUT; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case.\n")); + + if (p_dm_dig_table->large_fa_hit != 3) + p_dm_dig_table->large_fa_hit++; + + if (p_dm_dig_table->forbidden_igi < current_igi) { /* if(p_dm_dig_table->forbidden_igi < p_dm_dig_table->cur_ig_value) */ + p_dm_dig_table->forbidden_igi = current_igi;/* p_dm_dig_table->forbidden_igi = p_dm_dig_table->cur_ig_value; */ + p_dm_dig_table->large_fa_hit = 1; + p_dm_dig_table->large_fa_timeout = LARGE_FA_TIMEOUT; } - if(pDM_DigTable->LargeFAHit >= 3) - { - if((pDM_DigTable->ForbiddenIGI + 2) > pDM_DigTable->rx_gain_range_max) - rx_gain_range_min = pDM_DigTable->rx_gain_range_max; + if (p_dm_dig_table->large_fa_hit >= 3) { + if ((p_dm_dig_table->forbidden_igi + 2) > p_dm_dig_table->rx_gain_range_max) + rx_gain_range_min = p_dm_dig_table->rx_gain_range_max; else - rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 2); - pDM_DigTable->Recover_cnt = 1800; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case: Recover_cnt = %d\n", pDM_DigTable->Recover_cnt)); + rx_gain_range_min = (p_dm_dig_table->forbidden_igi + 2); + p_dm_dig_table->recover_cnt = 1800; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case: recover_cnt = %d\n", p_dm_dig_table->recover_cnt)); } } - else if (pFalseAlmCnt->Cnt_all > 2000) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnormally false alarm case.\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Cnt_all=%d, Cnt_all_pre=%d, CurrentIGI=0x%x, PreIGValue=0x%x\n", - pFalseAlmCnt->Cnt_all, pFalseAlmCnt->Cnt_all_pre, CurrentIGI, pDM_DigTable->PreIGValue)); - - /* pFalseAlmCnt->Cnt_all = 1.1875*pFalseAlmCnt->Cnt_all_pre */ - if ((pFalseAlmCnt->Cnt_all > (pFalseAlmCnt->Cnt_all_pre + (pFalseAlmCnt->Cnt_all_pre >> 3) + (pFalseAlmCnt->Cnt_all_pre >> 4))) && (CurrentIGI < pDM_DigTable->PreIGValue)) { - if (pDM_DigTable->LargeFAHit != 3) - pDM_DigTable->LargeFAHit++; - - if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { /*if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue)*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Updating ForbiddenIGI by CurrentIGI, ForbiddenIGI=0x%x, CurrentIGI=0x%x\n", - pDM_DigTable->ForbiddenIGI, CurrentIGI)); - - pDM_DigTable->ForbiddenIGI = CurrentIGI; /*pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue;*/ - pDM_DigTable->LargeFAHit = 1; - pDM_DigTable->LargeFA_Timeout = LARGE_FA_TIMEOUT; + else if (p_false_alm_cnt->cnt_all > 2000) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnormally false alarm case.\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("cnt_all=%d, cnt_all_pre=%d, current_igi=0x%x, pre_ig_value=0x%x\n", + p_false_alm_cnt->cnt_all, p_false_alm_cnt->cnt_all_pre, current_igi, p_dm_dig_table->pre_ig_value)); + + /* p_false_alm_cnt->cnt_all = 1.1875*p_false_alm_cnt->cnt_all_pre */ + if ((p_false_alm_cnt->cnt_all > (p_false_alm_cnt->cnt_all_pre + (p_false_alm_cnt->cnt_all_pre >> 3) + (p_false_alm_cnt->cnt_all_pre >> 4))) && (current_igi < p_dm_dig_table->pre_ig_value)) { + if (p_dm_dig_table->large_fa_hit != 3) + p_dm_dig_table->large_fa_hit++; + + if (p_dm_dig_table->forbidden_igi < current_igi) { /*if(p_dm_dig_table->forbidden_igi < p_dm_dig_table->cur_ig_value)*/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Updating forbidden_igi by current_igi, forbidden_igi=0x%x, current_igi=0x%x\n", + p_dm_dig_table->forbidden_igi, current_igi)); + + p_dm_dig_table->forbidden_igi = current_igi; /*p_dm_dig_table->forbidden_igi = p_dm_dig_table->cur_ig_value;*/ + p_dm_dig_table->large_fa_hit = 1; + p_dm_dig_table->large_fa_timeout = LARGE_FA_TIMEOUT; } - + } - - if (pDM_DigTable->LargeFAHit >= 3) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("FaHit is greater than 3, rx_gain_range_max=0x%x, rx_gain_range_min=0x%x, ForbiddenIGI=0x%x\n", - pDM_DigTable->rx_gain_range_max, rx_gain_range_min, pDM_DigTable->ForbiddenIGI)); - if ((pDM_DigTable->ForbiddenIGI + 1) > pDM_DigTable->rx_gain_range_max) - rx_gain_range_min = pDM_DigTable->rx_gain_range_max; + if (p_dm_dig_table->large_fa_hit >= 3) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("FaHit is greater than 3, rx_gain_range_max=0x%x, rx_gain_range_min=0x%x, forbidden_igi=0x%x\n", + p_dm_dig_table->rx_gain_range_max, rx_gain_range_min, p_dm_dig_table->forbidden_igi)); + + if ((p_dm_dig_table->forbidden_igi + 1) > p_dm_dig_table->rx_gain_range_max) + rx_gain_range_min = p_dm_dig_table->rx_gain_range_max; else - rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); + rx_gain_range_min = (p_dm_dig_table->forbidden_igi + 1); - pDM_DigTable->Recover_cnt = 1200; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnormally false alarm case: Recover_cnt = %d, rx_gain_range_min = 0x%x\n", pDM_DigTable->Recover_cnt, rx_gain_range_min)); + p_dm_dig_table->recover_cnt = 1200; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnormally false alarm case: recover_cnt = %d, rx_gain_range_min = 0x%x\n", p_dm_dig_table->recover_cnt, rx_gain_range_min)); } - } - - else - { - if (pDM_DigTable->Recover_cnt != 0) { - - pDM_DigTable->Recover_cnt --; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Recover_cnt = %d\n", pDM_DigTable->Recover_cnt)); - } - else - { - if(pDM_DigTable->LargeFAHit < 3) - { - if((pDM_DigTable->ForbiddenIGI - 2) < DIG_Dynamic_MIN) //DM_DIG_MIN) - { - pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; //DM_DIG_MIN; - rx_gain_range_min = DIG_Dynamic_MIN; //DM_DIG_MIN; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); - } - else - { - if (pDM_DigTable->LargeFAHit == 0) { - pDM_DigTable->ForbiddenIGI -= 2; - rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 2); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); + } + + else { + if (p_dm_dig_table->recover_cnt != 0) { + + p_dm_dig_table->recover_cnt--; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: recover_cnt = %d\n", p_dm_dig_table->recover_cnt)); + } else { + if (p_dm_dig_table->large_fa_hit < 3) { + if ((p_dm_dig_table->forbidden_igi - 2) < dig_dynamic_min) { /* DM_DIG_MIN) */ + p_dm_dig_table->forbidden_igi = dig_dynamic_min; /* DM_DIG_MIN; */ + rx_gain_range_min = dig_dynamic_min; /* DM_DIG_MIN; */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); + } else { + if (p_dm_dig_table->large_fa_hit == 0) { + p_dm_dig_table->forbidden_igi -= 2; + rx_gain_range_min = (p_dm_dig_table->forbidden_igi + 2); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); + } } - } - } - else - { - pDM_DigTable->LargeFAHit = 0; - } + } else + p_dm_dig_table->large_fa_hit = 0; } } - + return rx_gain_range_min; } -VOID -odm_InbandNoiseCalculate ( - IN PVOID pDM_VOID - ) +void +odm_inband_noise_calculate( + void *p_dm_void +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte IGIBackup, TimeCnt = 0, ValidCnt = 0; - BOOLEAN bTimeout = TRUE; - s1Byte sNoise_A, sNoise_B; - s4Byte NoiseRpt_A = 0,NoiseRpt_B = 0; - u4Byte tmp = 0; - static u1Byte failCnt = 0; - - if(!(pDM_Odm->SupportICType & (ODM_RTL8192E))) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u8 igi_backup, time_cnt = 0, valid_cnt = 0; + boolean is_timeout = true; + s8 s_noise_a, s_noise_b; + s32 noise_rpt_a = 0, noise_rpt_b = 0; + u32 tmp = 0; + static u8 fail_cnt = 0; + + if (!(p_dm_odm->support_ic_type & (ODM_RTL8192E))) return; - if(pDM_Odm->RFType == ODM_1T1R || *(pDM_Odm->pOnePathCCA) != ODM_CCA_2R) + if (p_dm_odm->rf_type == ODM_1T1R || *(p_dm_odm->p_one_path_cca) != ODM_CCA_2R) return; - if(!pDM_DigTable->bNoiseEst) + if (!p_dm_dig_table->is_noise_est) return; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_InbandNoiseEstimate()========>\n")); - - //1 Set initial gain. - IGIBackup = pDM_DigTable->CurIGValue; - pDM_DigTable->IGIOffset_A = 0; - pDM_DigTable->IGIOffset_B = 0; - ODM_Write_DIG(pDM_Odm, 0x24); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_InbandNoiseEstimate()========>\n")); + + /* 1 Set initial gain. */ + igi_backup = p_dm_dig_table->cur_ig_value; + p_dm_dig_table->igi_offset_a = 0; + p_dm_dig_table->igi_offset_b = 0; + odm_write_dig(p_dm_odm, 0x24); - //1 Update idle time power report - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT25, 0x0); + /* 1 Update idle time power report */ + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(p_dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT(25), 0x0); delay_ms(2); - //1 Get noise power level - while(1) - { - //2 Read Noise Floor Report - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - tmp = ODM_GetBBReg(pDM_Odm, 0x8f8, bMaskLWord); + /* 1 Get noise power level */ + while (1) { + /* 2 Read Noise Floor Report */ + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + tmp = odm_get_bb_reg(p_dm_odm, 0x8f8, MASKLWORD); - sNoise_A = (s1Byte)(tmp & 0xff); - sNoise_B = (s1Byte)((tmp & 0xff00)>>8); + s_noise_a = (s8)(tmp & 0xff); + s_noise_b = (s8)((tmp & 0xff00) >> 8); - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("sNoise_A = %d, sNoise_B = %d\n",sNoise_A, sNoise_B)); + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("s_noise_a = %d, s_noise_b = %d\n",s_noise_a, s_noise_b)); */ - if((sNoise_A < 20 && sNoise_A >= -70) && (sNoise_B < 20 && sNoise_B >= -70)) - { - ValidCnt++; - NoiseRpt_A += sNoise_A; - NoiseRpt_B += sNoise_B; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("sNoise_A = %d, sNoise_B = %d\n",sNoise_A, sNoise_B)); + if ((s_noise_a < 20 && s_noise_a >= -70) && (s_noise_b < 20 && s_noise_b >= -70)) { + valid_cnt++; + noise_rpt_a += s_noise_a; + noise_rpt_b += s_noise_b; + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("s_noise_a = %d, s_noise_b = %d\n",s_noise_a, s_noise_b)); */ } - TimeCnt++; - bTimeout = (TimeCnt >= 150)?TRUE:FALSE; - - if(ValidCnt == 20 || bTimeout) + time_cnt++; + is_timeout = (time_cnt >= 150) ? true : false; + + if (valid_cnt == 20 || is_timeout) break; delay_ms(2); - + } - //1 Keep idle time power report - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT25, 0x1); + /* 1 Keep idle time power report */ + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(p_dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT(25), 0x1); - //1 Recover IGI - ODM_Write_DIG(pDM_Odm, IGIBackup); - - //1 Calculate Noise Floor - if(ValidCnt != 0) - { - NoiseRpt_A /= (ValidCnt<<1); - NoiseRpt_B /= (ValidCnt<<1); + /* 1 Recover IGI */ + odm_write_dig(p_dm_odm, igi_backup); + + /* 1 Calculate Noise Floor */ + if (valid_cnt != 0) { + noise_rpt_a /= (valid_cnt << 1); + noise_rpt_b /= (valid_cnt << 1); } - - if(bTimeout) - { - NoiseRpt_A = 0; - NoiseRpt_B = 0; - failCnt ++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Noise estimate fail time = %d\n", failCnt)); - - if(failCnt == 3) - { - failCnt = 0; - pDM_DigTable->bNoiseEst = FALSE; + if (is_timeout) { + noise_rpt_a = 0; + noise_rpt_b = 0; + + fail_cnt++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Noise estimate fail time = %d\n", fail_cnt)); + + if (fail_cnt == 3) { + fail_cnt = 0; + p_dm_dig_table->is_noise_est = false; } - } - else - { - NoiseRpt_A = -110 + 0x24 + NoiseRpt_A -6; - NoiseRpt_B = -110 + 0x24 + NoiseRpt_B -6; - pDM_DigTable->bNoiseEst = FALSE; - failCnt = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("NoiseRpt_A = %d, NoiseRpt_B = %d\n", NoiseRpt_A, NoiseRpt_B)); + } else { + noise_rpt_a = -110 + 0x24 + noise_rpt_a - 6; + noise_rpt_b = -110 + 0x24 + noise_rpt_b - 6; + p_dm_dig_table->is_noise_est = false; + fail_cnt = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("noise_rpt_a = %d, noise_rpt_b = %d\n", noise_rpt_a, noise_rpt_b)); } - //1 Calculate IGI Offset - if(NoiseRpt_A > NoiseRpt_B) - { - pDM_DigTable->IGIOffset_A = NoiseRpt_A - NoiseRpt_B; - pDM_DigTable->IGIOffset_B = 0; - } - else - { - pDM_DigTable->IGIOffset_A = 0; - pDM_DigTable->IGIOffset_B = NoiseRpt_B - NoiseRpt_A; + /* 1 Calculate IGI Offset */ + if (noise_rpt_a > noise_rpt_b) { + p_dm_dig_table->igi_offset_a = noise_rpt_a - noise_rpt_b; + p_dm_dig_table->igi_offset_b = 0; + } else { + p_dm_dig_table->igi_offset_a = 0; + p_dm_dig_table->igi_offset_b = noise_rpt_b - noise_rpt_a; } #endif return; } -VOID -odm_DigForBtHsMode( - IN PVOID pDM_VOID - ) +void +odm_dig_for_bt_hs_mode( + void *p_dm_void +) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable=&pDM_Odm->DM_DigTable; - u1Byte digForBtHs=0; - u1Byte digUpBound=0x5a; - - if (pDM_Odm->bBtConnectProcess) { - digForBtHs = 0x22; - } else { - // - // Decide DIG value by BT HS RSSI. - // - digForBtHs = pDM_Odm->btHsRssi+4; - - //DIG Bound - if(digForBtHs > digUpBound) - digForBtHs = digUpBound; - if(digForBtHs < 0x1c) - digForBtHs = 0x1c; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u8 dig_for_bt_hs = 0; + u8 dig_up_bound = 0x5a; + + if (p_dm_odm->is_bt_connect_process) + dig_for_bt_hs = 0x22; + else { + /* */ + /* Decide DIG value by BT HS RSSI. */ + /* */ + dig_for_bt_hs = p_dm_odm->bt_hs_rssi + 4; - // update Current IGI - pDM_DigTable->BT30_CurIGI = digForBtHs; + /* DIG Bound */ + if (dig_for_bt_hs > dig_up_bound) + dig_for_bt_hs = dig_up_bound; + if (dig_for_bt_hs < 0x1c) + dig_for_bt_hs = 0x1c; + + /* update Current IGI */ + p_dm_dig_table->bt30_cur_igi = dig_for_bt_hs; } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DigForBtHsMode() : set DigValue=0x%x\n", digForBtHs)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_for_bt_hs_mode() : set DigValue=0x%x\n", dig_for_bt_hs)); #endif } -VOID -phydm_setBigJumpStep( - IN PVOID pDM_VOID, - IN u1Byte CurrentIGI +void +phydm_set_big_jump_step( + void *p_dm_void, + u8 current_igi ) { #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte step1[8] = {24, 30, 40, 50, 60, 70, 80, 90}; - u1Byte i; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90}; + u8 i; - if (pDM_DigTable->enableAdjustBigJump == 0) + if (p_dm_dig_table->enable_adjust_big_jump == 0) return; - for (i = 0; i <= pDM_DigTable->bigJumpStep1; i++) { - if ((CurrentIGI + step1[i]) > pDM_DigTable->bigJumpLmt[pDM_DigTable->agcTableIdx]) { + for (i = 0; i <= p_dm_dig_table->big_jump_step1; i++) { + if ((current_igi + step1[i]) > p_dm_dig_table->big_jump_lmt[p_dm_dig_table->agc_table_idx]) { if (i != 0) i = i - 1; break; - } else if (i == pDM_DigTable->bigJumpStep1) + } else if (i == p_dm_dig_table->big_jump_step1) break; } - if (pDM_Odm->SupportICType & ODM_RTL8822B) - ODM_SetBBReg(pDM_Odm, 0x8c8, 0xe, i); - else if (pDM_Odm->SupportICType & ODM_RTL8197F) - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_setBigJumpStep(): bigjump = %d (ori = 0x%d), LMT=0x%x\n", i, pDM_DigTable->bigJumpStep1, pDM_DigTable->bigJumpLmt[pDM_DigTable->agcTableIdx])); + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(p_dm_odm, 0x8c8, 0xe, i); + else if (p_dm_odm->support_ic_type & ODM_RTL8197F) + odm_set_bb_reg(p_dm_odm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_set_big_jump_step(): bigjump = %d (ori = 0x%x), LMT=0x%x\n", i, p_dm_dig_table->big_jump_step1, p_dm_dig_table->big_jump_lmt[p_dm_dig_table->agc_table_idx])); #endif } -VOID -ODM_Write_DIG( - IN PVOID pDM_VOID, - IN u1Byte CurrentIGI - ) +void +odm_write_dig( + void *p_dm_void, + u8 current_igi +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - if (pDM_DigTable->bStopDIG) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG(): Stop Writing IGI\n")); + if (p_dm_dig_table->is_stop_dig) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_write_dig(): Stop Writing IGI\n")); return; } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_Write_DIG(): ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n", - ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("odm_write_dig(): ODM_REG(IGI_A,p_dm_odm)=0x%x, ODM_BIT(IGI,p_dm_odm)=0x%x\n", + ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm))); - //1 Check initial gain by upper bound - if ((!pDM_DigTable->bPSDInProgress) && pDM_Odm->bLinked) - { - if (CurrentIGI > pDM_DigTable->rx_gain_range_max) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_Write_DIG(): CurrentIGI(0x%02x) is larger than upper bound !!\n", CurrentIGI)); - CurrentIGI = pDM_DigTable->rx_gain_range_max; + /* 1 Check initial gain by upper bound */ + if ((!p_dm_dig_table->is_psd_in_progress) && p_dm_odm->is_linked) { + if (current_igi > p_dm_dig_table->rx_gain_range_max) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("odm_write_dig(): current_igi(0x%02x) is larger than upper bound !!\n", current_igi)); + current_igi = p_dm_dig_table->rx_gain_range_max; } - if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY && pDM_Odm->adaptivity_flag == TRUE) - { - if(CurrentIGI > pDM_Odm->Adaptivity_IGI_upper) - CurrentIGI = pDM_Odm->Adaptivity_IGI_upper; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG(): Adaptivity case: Force upper bound to 0x%x !!!!!!\n", CurrentIGI)); + if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY && p_dm_odm->adaptivity_flag == true) { + if (current_igi > p_dm_odm->adaptivity_igi_upper) + current_igi = p_dm_odm->adaptivity_igi_upper; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_write_dig(): adaptivity case: Force upper bound to 0x%x !!!!!!\n", current_igi)); } } - if(pDM_DigTable->CurIGValue != CurrentIGI) - { + if (p_dm_dig_table->cur_ig_value != current_igi) { -#if (RTL8822B_SUPPORT == 1 | RTL8197F_SUPPORT == 1) +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) /* Modify big jump step for 8822B and 8197F */ - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F)) - phydm_setBigJumpStep(pDM_Odm, CurrentIGI); + if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) + phydm_set_big_jump_step(p_dm_odm, current_igi); #endif #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) /* Set IGI value of CCK for new CCK AGC */ - if (pDM_Odm->cck_new_agc) { - if (pDM_Odm->SupportICType & ODM_IC_PHY_STATUE_NEW_TYPE) - ODM_SetBBReg(pDM_Odm, 0xa0c, 0x00003f00, (CurrentIGI>>1)); + if (p_dm_odm->cck_new_agc) { + if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) + odm_set_bb_reg(p_dm_odm, 0xa0c, 0x00003f00, (current_igi >> 1)); } #endif /*Add by YuChen for USB IO too slow issue*/ - if ((pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) && (CurrentIGI > pDM_DigTable->CurIGValue)) - Phydm_Adaptivity(pDM_Odm, CurrentIGI); + if ((p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) && (current_igi > p_dm_dig_table->cur_ig_value)) { + p_dm_dig_table->cur_ig_value = current_igi; + phydm_adaptivity(p_dm_odm); + } - //1 Set IGI value - if (pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE)) { - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + /* 1 Set IGI value */ + if (p_dm_odm->support_platform & (ODM_WIN | ODM_CE)) { + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - if(pDM_Odm->RFType > ODM_1T1R) - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + if (p_dm_odm->rf_type > ODM_1T1R) + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); #if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8814A) { - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_C,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_D,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + if (p_dm_odm->support_ic_type & ODM_RTL8814A) { + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_C, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_D, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); } #endif - } else if (pDM_Odm->SupportPlatform & (ODM_AP)) { - switch(*(pDM_Odm->pOnePathCCA)) - { - case ODM_CCA_2R: - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - - if(pDM_Odm->RFType > ODM_1T1R) - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8814A) { - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_C,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_D,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - } + } else if (p_dm_odm->support_platform & (ODM_AP)) { + switch (*(p_dm_odm->p_one_path_cca)) { + case ODM_CCA_2R: + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + + if (p_dm_odm->rf_type > ODM_1T1R) + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); +#if (RTL8814A_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8814A) { + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_C, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_D, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + } #endif - break; - case ODM_CCA_1R_A: - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - if(pDM_Odm->RFType != ODM_1T1R) - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI)); - break; - case ODM_CCA_1R_B: - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI)); - if(pDM_Odm->RFType != ODM_1T1R) - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); - break; + break; + case ODM_CCA_1R_A: + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + if (p_dm_odm->rf_type != ODM_1T1R) + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), get_igi_for_diff(current_igi)); + break; + case ODM_CCA_1R_B: + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), get_igi_for_diff(current_igi)); + if (p_dm_odm->rf_type != ODM_1T1R) + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + break; } } - pDM_DigTable->CurIGValue = CurrentIGI; + p_dm_dig_table->cur_ig_value = current_igi; } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_Write_DIG(): CurrentIGI(0x%02x).\n", CurrentIGI)); - + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("odm_write_dig(): current_igi(0x%02x).\n", current_igi)); + } -VOID -odm_PauseDIG( - IN PVOID pDM_VOID, - IN PHYDM_PAUSE_TYPE PauseType, - IN PHYDM_PAUSE_LEVEL pause_level, - IN u1Byte IGIValue +void +odm_pause_dig( + void *p_dm_void, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_level, + u8 igi_value ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG()=========> level = %d\n", pause_level)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig()=========> level = %d\n", pause_level)); - if ((pDM_DigTable->pause_dig_level == 0) && (!(pDM_Odm->SupportAbility & ODM_BB_DIG) || !(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_PauseDIG(): Return: SupportAbility DIG or FA is disabled !!\n")); + if ((p_dm_dig_table->pause_dig_level == 0) && (!(p_dm_odm->support_ability & ODM_BB_DIG) || !(p_dm_odm->support_ability & ODM_BB_FA_CNT))) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_pause_dig(): Return: support_ability DIG or FA is disabled !!\n")); return; } if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_PauseDIG(): Return: Wrong pause level !!\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_pause_dig(): Return: Wrong pause level !!\n")); return; } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_dig_level, IGIValue)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - pDM_DigTable->pause_dig_value[7], pDM_DigTable->pause_dig_value[6], pDM_DigTable->pause_dig_value[5], pDM_DigTable->pause_dig_value[4], - pDM_DigTable->pause_dig_value[3], pDM_DigTable->pause_dig_value[2], pDM_DigTable->pause_dig_value[1], pDM_DigTable->pause_dig_value[0])); - - switch (PauseType) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_dig_level, igi_value)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + p_dm_dig_table->pause_dig_value[7], p_dm_dig_table->pause_dig_value[6], p_dm_dig_table->pause_dig_value[5], p_dm_dig_table->pause_dig_value[4], + p_dm_dig_table->pause_dig_value[3], p_dm_dig_table->pause_dig_value[2], p_dm_dig_table->pause_dig_value[1], p_dm_dig_table->pause_dig_value[0])); + + switch (pause_type) { /* Pause DIG */ case PHYDM_PAUSE: { /* Disable DIG */ - ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility & (~ODM_BB_DIG)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Pause DIG !!\n")); - + p_dm_odm->support_ability &= ~ODM_BB_DIG; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Pause DIG !!\n")); + /* Backup IGI value */ - if (pDM_DigTable->pause_dig_level == 0) { - pDM_DigTable->IGIBackup = pDM_DigTable->CurIGValue; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Backup IGI = 0x%x, new IGI = 0x%x\n", pDM_DigTable->IGIBackup, IGIValue)); + if (p_dm_dig_table->pause_dig_level == 0) { + p_dm_dig_table->igi_backup = p_dm_dig_table->cur_ig_value; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Backup IGI = 0x%x, new IGI = 0x%x\n", p_dm_dig_table->igi_backup, igi_value)); } /* Record IGI value */ - pDM_DigTable->pause_dig_value[pause_level] = IGIValue; + p_dm_dig_table->pause_dig_value[pause_level] = igi_value; /* Update pause level */ - pDM_DigTable->pause_dig_level = (pDM_DigTable->pause_dig_level | BIT(pause_level)); + p_dm_dig_table->pause_dig_level = (p_dm_dig_table->pause_dig_level | BIT(pause_level)); /* Write new IGI value */ - if (BIT(pause_level + 1) > pDM_DigTable->pause_dig_level) { - ODM_Write_DIG(pDM_Odm, IGIValue); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): IGI of higher level = 0x%x\n", IGIValue)); + if (BIT(pause_level + 1) > p_dm_dig_table->pause_dig_level) { + odm_write_dig(p_dm_odm, igi_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): IGI of higher level = 0x%x\n", igi_value)); } break; } @@ -603,1421 +563,1507 @@ odm_PauseDIG( case PHYDM_RESUME: { /* check if the level is illegal or not */ - if ((pDM_DigTable->pause_dig_level & (BIT(pause_level))) != 0) { - pDM_DigTable->pause_dig_level = pDM_DigTable->pause_dig_level & (~(BIT(pause_level))); - pDM_DigTable->pause_dig_value[pause_level] = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Resume DIG !!\n")); + if ((p_dm_dig_table->pause_dig_level & (BIT(pause_level))) != 0) { + p_dm_dig_table->pause_dig_level = p_dm_dig_table->pause_dig_level & (~(BIT(pause_level))); + p_dm_dig_table->pause_dig_value[pause_level] = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Resume DIG !!\n")); } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Wrong resume level !!\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Wrong resume level !!\n")); break; } /* Resume DIG */ - if (pDM_DigTable->pause_dig_level == 0) { + if (p_dm_dig_table->pause_dig_level == 0) { /* Write backup IGI value */ - ODM_Write_DIG(pDM_Odm, pDM_DigTable->IGIBackup); - pDM_DigTable->bIgnoreDIG = TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Write original IGI = 0x%x\n", pDM_DigTable->IGIBackup)); + odm_write_dig(p_dm_odm, p_dm_dig_table->igi_backup); + p_dm_dig_table->is_ignore_dig = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Write original IGI = 0x%x\n", p_dm_dig_table->igi_backup)); /* Enable DIG */ - ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility | ODM_BB_DIG); + p_dm_odm->support_ability |= ODM_BB_DIG; break; } - if (BIT(pause_level) > pDM_DigTable->pause_dig_level) { - s1Byte max_level; - + if (BIT(pause_level) > p_dm_dig_table->pause_dig_level) { + s8 max_level; + /* Calculate the maximum level now */ for (max_level = (pause_level - 1); max_level >= 0; max_level--) { - if ((pDM_DigTable->pause_dig_level & BIT(max_level)) > 0) + if ((p_dm_dig_table->pause_dig_level & BIT(max_level)) > 0) break; } - + /* write IGI of lower level */ - ODM_Write_DIG(pDM_Odm, pDM_DigTable->pause_dig_value[max_level]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Write IGI (0x%x) of level (%d)\n", - pDM_DigTable->pause_dig_value[max_level], max_level)); + odm_write_dig(p_dm_odm, p_dm_dig_table->pause_dig_value[max_level]); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Write IGI (0x%x) of level (%d)\n", + p_dm_dig_table->pause_dig_value[max_level], max_level)); break; } break; } default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Wrong type !!\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Wrong type !!\n")); break; } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_dig_level, IGIValue)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - pDM_DigTable->pause_dig_value[7], pDM_DigTable->pause_dig_value[6], pDM_DigTable->pause_dig_value[5], pDM_DigTable->pause_dig_value[4], - pDM_DigTable->pause_dig_value[3], pDM_DigTable->pause_dig_value[2], pDM_DigTable->pause_dig_value[1], pDM_DigTable->pause_dig_value[0])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_dig_level, igi_value)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + p_dm_dig_table->pause_dig_value[7], p_dm_dig_table->pause_dig_value[6], p_dm_dig_table->pause_dig_value[5], p_dm_dig_table->pause_dig_value[4], + p_dm_dig_table->pause_dig_value[3], p_dm_dig_table->pause_dig_value[2], p_dm_dig_table->pause_dig_value[1], p_dm_dig_table->pause_dig_value[0])); } -BOOLEAN -odm_DigAbort( - IN PVOID pDM_VOID - ) +boolean +odm_dig_abort( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER pAdapter = pDM_Odm->Adapter; + struct rtl8192cd_priv *priv = p_dm_odm->priv; +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *p_adapter = p_dm_odm->adapter; #endif - //SupportAbility - if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: SupportAbility ODM_BB_FA_CNT is disabled\n")); - return TRUE; + /* support_ability */ + if (!(p_dm_odm->support_ability & ODM_BB_FA_CNT)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: support_ability ODM_BB_FA_CNT is disabled\n")); + return true; } - //SupportAbility - if(!(pDM_Odm->SupportAbility & ODM_BB_DIG)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: SupportAbility ODM_BB_DIG is disabled\n")); - return TRUE; + /* support_ability */ + if (!(p_dm_odm->support_ability & ODM_BB_DIG)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: support_ability ODM_BB_DIG is disabled\n")); + return true; } - //ScanInProcess - if(*(pDM_Odm->pbScanInProcess)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: In Scan Progress \n")); - return TRUE; + /* ScanInProcess */ + if (*(p_dm_odm->p_is_scan_in_process)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: In Scan Progress\n")); + return true; } - if(pDM_DigTable->bIgnoreDIG) - { - pDM_DigTable->bIgnoreDIG = FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Ignore DIG \n")); - return TRUE; + if (p_dm_dig_table->is_ignore_dig) { + p_dm_dig_table->is_ignore_dig = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Ignore DIG\n")); + return true; } - //add by Neil Chen to avoid PSD is processing - if(pDM_Odm->bDMInitialGainEnable == FALSE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: PSD is Processing \n")); - return TRUE; + /* add by Neil Chen to avoid PSD is processing */ + if (p_dm_odm->is_dm_initial_gain_enable == false) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: PSD is Processing\n")); + return true; } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if OS_WIN_FROM_WIN7(OS_VERSION) - if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Is AP mode or In HCT Test \n")); - return TRUE; +#if OS_WIN_FROM_WIN7(OS_VERSION) + if (IsAPModeExist(p_adapter) && p_adapter->bInHctTest) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Is AP mode or In HCT Test\n")); + return true; } - #endif +#endif - if(pDM_Odm->bBtHsOperation) - { - odm_DigForBtHsMode(pDM_Odm); - } + if (p_dm_odm->is_bt_hs_operation) + odm_dig_for_bt_hs_mode(p_dm_odm); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - if((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0)) - { - printk("pDM_Odm->RSSI_Min=%d \n",pDM_Odm->RSSI_Min); - ODM_Write_DIG(pDM_Odm,pDM_Odm->Adapter->registrypriv.force_igi); - return TRUE; +#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + if ((p_dm_odm->is_linked) && (p_dm_odm->adapter->registrypriv.force_igi != 0)) { + printk("p_dm_odm->rssi_min=%d\n", p_dm_odm->rssi_min); + odm_write_dig(p_dm_odm, p_dm_odm->adapter->registrypriv.force_igi); + return true; } - #endif +#endif #else - if (!(priv->up_time > 5)) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Not In DIG Operation Period \n")); - return TRUE; + if (!(priv->up_time > 5)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Not In DIG operation period\n")); + return true; } #endif - return FALSE; + return false; } -VOID -odm_DIGInit( - IN PVOID pDM_VOID - ) +void +odm_dig_init( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); -#endif - u4Byte ret_value; - u1Byte i; - - pDM_DigTable->bStopDIG = FALSE; - pDM_DigTable->bIgnoreDIG = FALSE; - pDM_DigTable->bPSDInProgress = FALSE; - pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm)); - pDM_DigTable->PreIGValue = 0; - pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; - pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; - pDM_DigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW; - pDM_DigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH; - pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; - pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; - pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; - pDM_DigTable->PreCCK_CCAThres = 0xFF; - pDM_DigTable->CurCCK_CCAThres = 0x83; - pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; - pDM_DigTable->LargeFAHit = 0; - pDM_DigTable->LargeFA_Timeout = 0; - pDM_DigTable->Recover_cnt = 0; - pDM_DigTable->bMediaConnect_0 = FALSE; - pDM_DigTable->bMediaConnect_1 = FALSE; - - //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error - pDM_Odm->bDMInitialGainEnable = TRUE; - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - pDM_DigTable->DIG_Dynamic_MIN_0 = 0x25; - pDM_DigTable->DIG_Dynamic_MIN_1 = 0x25; - - // For AP\ ADSL modified DIG - pDM_DigTable->bTpTarget = FALSE; - pDM_DigTable->bNoiseEst = TRUE; - pDM_DigTable->IGIOffset_A = 0; - pDM_DigTable->IGIOffset_B = 0; - pDM_DigTable->TpTrainTH_min = 0; + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); +#endif + u32 ret_value; + u8 i; + + p_dm_dig_table->is_stop_dig = false; + p_dm_dig_table->is_ignore_dig = false; + p_dm_dig_table->is_psd_in_progress = false; + p_dm_dig_table->cur_ig_value = (u8) odm_get_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm)); + p_dm_dig_table->pre_ig_value = 0; + p_dm_dig_table->rssi_low_thresh = DM_DIG_THRESH_LOW; + p_dm_dig_table->rssi_high_thresh = DM_DIG_THRESH_HIGH; + p_dm_dig_table->fa_low_thresh = DM_FALSEALARM_THRESH_LOW; + p_dm_dig_table->fa_high_thresh = DM_FALSEALARM_THRESH_HIGH; + p_dm_dig_table->backoff_val = DM_DIG_BACKOFF_DEFAULT; + p_dm_dig_table->backoff_val_range_max = DM_DIG_BACKOFF_MAX; + p_dm_dig_table->backoff_val_range_min = DM_DIG_BACKOFF_MIN; + #if PHYDM_SUPPORT_CCKPD + p_dm_dig_table->pre_cck_cca_thres = 0xFF; + p_dm_dig_table->cur_cck_cca_thres = 0x83; + #endif + p_dm_dig_table->forbidden_igi = DM_DIG_MIN_NIC; + p_dm_dig_table->large_fa_hit = 0; + p_dm_dig_table->large_fa_timeout = 0; + p_dm_dig_table->recover_cnt = 0; + p_dm_dig_table->is_media_connect_0 = false; + p_dm_dig_table->is_media_connect_1 = false; - // For RTL8881A - FalseAlmCnt->Cnt_Ofdm_fail_pre = 0; + /* To Initialize p_dm_odm->is_dm_initial_gain_enable == false to avoid DIG error */ + p_dm_odm->is_dm_initial_gain_enable = true; - //Dyanmic EDCCA - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - { - ODM_SetBBReg(pDM_Odm, 0xC50, 0xFFFF0000, 0xfafd); - } +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + p_dm_dig_table->dig_dynamic_min_0 = 0x25; + p_dm_dig_table->dig_dynamic_min_1 = 0x25; + + /* For AP\ ADSL modified DIG */ + p_dm_dig_table->is_tp_target = false; + p_dm_dig_table->is_noise_est = true; + p_dm_dig_table->igi_offset_a = 0; + p_dm_dig_table->igi_offset_b = 0; + p_dm_dig_table->tp_train_th_min = 0; + + /* For RTL8881A */ + false_alm_cnt->cnt_ofdm_fail_pre = 0; + + /* Dyanmic EDCCA */ + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(p_dm_odm, 0xC50, 0xFFFF0000, 0xfafd); #else - pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; - pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; + p_dm_dig_table->dig_dynamic_min_0 = DM_DIG_MIN_NIC; + p_dm_dig_table->dig_dynamic_min_1 = DM_DIG_MIN_NIC; - //To Initi BT30 IGI - pDM_DigTable->BT30_CurIGI=0x32; + /* To Initi BT30 IGI */ + p_dm_dig_table->bt30_cur_igi = 0x32; - ODM_Memory_Set(pDM_Odm, pDM_DigTable->pause_dig_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); - pDM_DigTable->pause_dig_level = 0; - ODM_Memory_Set(pDM_Odm, pDM_DigTable->pause_cckpd_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); - pDM_DigTable->pause_cckpd_level = 0; + odm_memory_set(p_dm_odm, p_dm_dig_table->pause_dig_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); + p_dm_dig_table->pause_dig_level = 0; + #if PHYDM_SUPPORT_CCKPD + odm_memory_set(p_dm_odm, p_dm_dig_table->pause_cckpd_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); + p_dm_dig_table->pause_cckpd_level = 0; + #endif #endif - if(pDM_Odm->BoardType & (ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA)) - { - pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; - pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; - } - else - { - pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; - pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; + if (p_dm_odm->board_type & (ODM_BOARD_EXT_PA | ODM_BOARD_EXT_LNA)) { + p_dm_dig_table->rx_gain_range_max = DM_DIG_MAX_NIC; + p_dm_dig_table->rx_gain_range_min = DM_DIG_MIN_NIC; + } else { + p_dm_dig_table->rx_gain_range_max = DM_DIG_MAX_NIC; + p_dm_dig_table->rx_gain_range_min = DM_DIG_MIN_NIC; } #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - pDM_DigTable->enableAdjustBigJump = 1; - if (pDM_Odm->SupportICType & ODM_RTL8822B) { - ret_value = ODM_GetBBReg(pDM_Odm, 0x8c8, bMaskLWord); - pDM_DigTable->bigJumpStep1 = (u1Byte)(ret_value & 0xe) >> 1; - pDM_DigTable->bigJumpStep2 = (u1Byte)(ret_value & 0x30)>>4; - pDM_DigTable->bigJumpStep3 = (u1Byte)(ret_value & 0xc0)>>6; - - } else if (pDM_Odm->SupportICType & ODM_RTL8197F) { - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_BB_AGC_SET_2_11N, bMaskLWord); - pDM_DigTable->bigJumpStep1 = (u1Byte)(ret_value & 0xe) >> 1; - pDM_DigTable->bigJumpStep2 = (u1Byte)(ret_value & 0x30)>>4; - pDM_DigTable->bigJumpStep3 = (u1Byte)(ret_value & 0xc0)>>6; - } - if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8197F)) { - for (i = 0; i < sizeof(pDM_DigTable->bigJumpLmt); i++) { - if (pDM_DigTable->bigJumpLmt[i] == 0) - pDM_DigTable->bigJumpLmt[i] = 0x64; /* Set -10dBm as default value */ + p_dm_dig_table->enable_adjust_big_jump = 1; + if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + ret_value = odm_get_bb_reg(p_dm_odm, 0x8c8, MASKLWORD); + p_dm_dig_table->big_jump_step1 = (u8)(ret_value & 0xe) >> 1; + p_dm_dig_table->big_jump_step2 = (u8)(ret_value & 0x30) >> 4; + p_dm_dig_table->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6; + + } else if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_BB_AGC_SET_2_11N, MASKLWORD); + p_dm_dig_table->big_jump_step1 = (u8)(ret_value & 0xe) >> 1; + p_dm_dig_table->big_jump_step2 = (u8)(ret_value & 0x30) >> 4; + p_dm_dig_table->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6; + } + if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) { + for (i = 0; i < sizeof(p_dm_dig_table->big_jump_lmt); i++) { + if (p_dm_dig_table->big_jump_lmt[i] == 0) + p_dm_dig_table->big_jump_lmt[i] = 0x64; /* Set -10dBm as default value */ } } #endif + + +#if (DIG_HW == 1) + p_dm_dig_table->pre_rssi_min = 0; +#endif } -VOID +void odm_DIG( - IN PVOID pDM_VOID - ) + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - PSTA_INFO_T pEntry; -#endif - - // Common parameters - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - BOOLEAN FirstConnect,FirstDisConnect; - u1Byte DIG_MaxOfMin, DIG_Dynamic_MIN; - u1Byte dm_dig_max, dm_dig_min; - u1Byte CurrentIGI = pDM_DigTable->CurIGValue; - u1Byte offset; - u4Byte dm_FA_thres[3]; - u4Byte TxTp = 0, RxTp = 0; - BOOLEAN DIG_GoUpCheck = TRUE; - BOOLEAN bDFSBand = FALSE; - BOOLEAN bPerformance = TRUE, bFirstTpTarget = FALSE, bFirstCoverage = FALSE; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct sta_info *p_entry; +#endif + + /* Common parameters */ + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + boolean first_connect, first_dis_connect; + u8 dig_max_of_min, dig_dynamic_min; + u8 dm_dig_max, dm_dig_min; + u8 current_igi = p_dm_dig_table->cur_ig_value; + u8 offset; + u32 dm_FA_thres[3]; + u32 tx_tp = 0, rx_tp = 0; + boolean is_dfs_band = false; + boolean is_performance = true, is_first_tp_target = false, is_first_coverage = false; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u4Byte TpTrainTH_MIN = DM_DIG_TP_Target_TH0; - static u1Byte TimeCnt = 0; - u1Byte i; + u32 tp_train_th_min = dm_dig_tp_target_th0; + static u8 time_cnt = 0; + u8 i; +#endif +#if (DIG_HW == 1) + boolean dig_go_up_check = true; + u8 step_size_1 = 0, step_size_2 = 0, step_size_3 = 0; #endif - if(odm_DigAbort(pDM_Odm) == TRUE) + if (odm_dig_abort(p_dm_odm) == true) return; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()===========================>\n\n")); - + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG Start===>\n")); - //1 Update status +#if (DIG_HW == 1) + if (p_dm_odm->is_linked) { + if (p_dm_dig_table->pre_rssi_min <= p_dm_odm->rssi_min) { + step_size_1 = 2; + step_size_2 = 1; + step_size_3 = 2; + } else { + step_size_1 = 4; + step_size_2 = 2; + step_size_3 = 2; + } + p_dm_dig_table->pre_rssi_min = p_dm_odm->rssi_min; + } else { + step_size_1 = 2; + step_size_2 = 1; + step_size_3 = 2; + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("rssi_min = %d, pre_rssi_min = %d\n", p_dm_odm->rssi_min, p_dm_dig_table->pre_rssi_min)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("step_size_1 = %d, step_size_2 = %d, step_size_3 = %d\n", step_size_1, step_size_2, step_size_3)); +#endif + + /* 1 Update status */ { - DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; - FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); - FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); + dig_dynamic_min = p_dm_dig_table->dig_dynamic_min_0; + first_connect = (p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == false); + first_dis_connect = (!p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == true); } #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - //1 Noise Floor Estimate - //pDM_DigTable->bNoiseEst = (FirstConnect)?TRUE:pDM_DigTable->bNoiseEst; - //odm_InbandNoiseCalculate (pDM_Odm); - - //1 Mode decision - if(pDM_Odm->bLinked) - { - //2 Calculate total TP - for (i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pEntry)) - { - RxTp += (u4Byte)(pEntry->rx_byte_cnt_LowMAW>>7); - TxTp += (u4Byte)(pEntry->tx_byte_cnt_LowMAW>>7); //Kbps + /* 1 Noise Floor Estimate */ + /* p_dm_dig_table->is_noise_est = (first_connect)?true:p_dm_dig_table->is_noise_est; */ + /* odm_inband_noise_calculate (p_dm_odm); */ + + /* 1 mode decision */ + if (p_dm_odm->is_linked) { + /* 2 Calculate total TP */ + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + p_entry = p_dm_odm->p_odm_sta_info[i]; + if (IS_STA_VALID(p_entry)) { + rx_tp += (u32)(p_entry->rx_byte_cnt_low_maw >> 7); + tx_tp += (u32)(p_entry->tx_byte_cnt_low_maw >> 7); /* Kbps */ } } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TX TP = %dkbps, RX TP = %dkbps\n", TxTp, RxTp)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: TX TP = %dkbps, RX TP = %dkbps\n", tx_tp, rx_tp)); } - switch(pDM_Odm->priv->pshare->rf_ft_var.dig_cov_enable) + switch (p_dm_odm->priv->pshare->rf_ft_var.dig_cov_enable) { + case 0: { - case 0: - { - bPerformance = TRUE; - break; - } - case 1: - { - bPerformance = FALSE; - break; - } - case 2: - { - if(pDM_Odm->bLinked) - { - if(pDM_DigTable->TpTrainTH_min > DM_DIG_TP_Target_TH0) - TpTrainTH_MIN = pDM_DigTable->TpTrainTH_min; - - if(pDM_DigTable->TpTrainTH_min > DM_DIG_TP_Target_TH1) - TpTrainTH_MIN = DM_DIG_TP_Target_TH1; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TP training mode lower bound = %dkbps\n", TpTrainTH_MIN)); - - //2 Decide DIG mode by total TP - if((TxTp + RxTp) > DM_DIG_TP_Target_TH1) // change to performance mode - { - bFirstTpTarget = (!pDM_DigTable->bTpTarget)?TRUE:FALSE; - pDM_DigTable->bTpTarget = TRUE; - bPerformance = TRUE; - } - else if((TxTp + RxTp) < TpTrainTH_MIN) // change to coverage mode - { - bFirstCoverage = (pDM_DigTable->bTpTarget)?TRUE:FALSE; - - if(TimeCnt < DM_DIG_TP_Training_Period) - { - pDM_DigTable->bTpTarget = FALSE; - bPerformance = FALSE; - TimeCnt++; - } - else - { - pDM_DigTable->bTpTarget = TRUE; - bPerformance = TRUE; - bFirstTpTarget = TRUE; - TimeCnt = 0; - } + is_performance = true; + break; + } + case 1: + { + is_performance = false; + break; + } + case 2: + { + if (p_dm_odm->is_linked) { + if (p_dm_dig_table->tp_train_th_min > dm_dig_tp_target_th0) + tp_train_th_min = p_dm_dig_table->tp_train_th_min; + + if (p_dm_dig_table->tp_train_th_min > dm_dig_tp_target_th1) + tp_train_th_min = dm_dig_tp_target_th1; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: TP training mode lower bound = %dkbps\n", tp_train_th_min)); + + /* 2 Decide DIG mode by total TP */ + if ((tx_tp + rx_tp) > dm_dig_tp_target_th1) { /* change to performance mode */ + is_first_tp_target = (!p_dm_dig_table->is_tp_target) ? true : false; + p_dm_dig_table->is_tp_target = true; + is_performance = true; + } else if ((tx_tp + rx_tp) < tp_train_th_min) { /* change to coverage mode */ + is_first_coverage = (p_dm_dig_table->is_tp_target) ? true : false; + + if (time_cnt < dm_dig_tp_training_period) { + p_dm_dig_table->is_tp_target = false; + is_performance = false; + time_cnt++; + } else { + p_dm_dig_table->is_tp_target = true; + is_performance = true; + is_first_tp_target = true; + time_cnt = 0; } - else // remain previous mode - { - bPerformance = pDM_DigTable->bTpTarget; - - if(!bPerformance) - { - if(TimeCnt < DM_DIG_TP_Training_Period) - TimeCnt++; - else - { - pDM_DigTable->bTpTarget = TRUE; - bPerformance = TRUE; - bFirstTpTarget = TRUE; - TimeCnt = 0; - } + } else { /* remain previous mode */ + is_performance = p_dm_dig_table->is_tp_target; + + if (!is_performance) { + if (time_cnt < dm_dig_tp_training_period) + time_cnt++; + else { + p_dm_dig_table->is_tp_target = true; + is_performance = true; + is_first_tp_target = true; + time_cnt = 0; } } + } - if(!bPerformance) - pDM_DigTable->TpTrainTH_min = RxTp + TxTp; + if (!is_performance) + p_dm_dig_table->tp_train_th_min = rx_tp + tx_tp; - } - else - { - bPerformance = FALSE; - pDM_DigTable->TpTrainTH_min = 0; - } - break; + } else { + is_performance = false; + p_dm_dig_table->tp_train_th_min = 0; } - default: - bPerformance = TRUE; + break; + } + default: + is_performance = true; } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("====== DIG mode = %d ======\n", pDM_Odm->priv->pshare->rf_ft_var.dig_cov_enable)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("====== bPerformance = %d ======\n", bPerformance)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("====== DIG mode = %d ======\n", p_dm_odm->priv->pshare->rf_ft_var.dig_cov_enable)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("====== is_performance = %d ======\n", is_performance)); #endif - //1 Boundary Decision + /* 1 Boundary Decision */ { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - //2 For AP\ADSL - if(!bPerformance) - { + /* 2 For AP\ADSL */ + if (!is_performance) { dm_dig_max = DM_DIG_MAX_AP_COVERAGR; dm_dig_min = DM_DIG_MIN_AP_COVERAGE; - DIG_MaxOfMin = DM_DIG_MAX_OF_MIN_COVERAGE; - } - else - { - if (pDM_Odm->RFType == ODM_1T1R) +#if (DIG_HW == 1) + dig_max_of_min = DM_DIG_MIN_AP_COVERAGE; +#else + dig_max_of_min = DM_DIG_MAX_OF_MIN_COVERAGE; +#endif + + } else { + if (p_dm_odm->rf_type == ODM_1T1R) dm_dig_max = DM_DIG_MAX_AP - 6; else dm_dig_max = DM_DIG_MAX_AP; - dm_dig_min = DM_DIG_MIN_AP; - DIG_MaxOfMin = DM_DIG_MAX_OF_MIN; + + if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) && (p_dm_odm->support_ic_type & ODM_RTL8814A)) /* for 2G 8814 */ + dm_dig_min = 0x1c; + else if (p_dm_odm->support_ic_type & ODM_RTL8197F) + dm_dig_min = 0x1e; + else + dm_dig_min = DM_DIG_MIN_AP; + +#if (DIG_HW == 1) + dig_max_of_min = DM_DIG_MIN_AP_COVERAGE; +#else + dig_max_of_min = DM_DIG_MAX_OF_MIN; +#endif + } - - //4 TX2path - if (priv->pmib->dot11RFEntry.tx2path && !bDFSBand && (*(pDM_Odm->pWirelessMode) == ODM_WM_B)) - dm_dig_max = 0x2A; + + /* 4 TX2path */ + if (priv->pmib->dot11RFEntry.tx2path && !is_dfs_band && (*(p_dm_odm->p_wireless_mode) == ODM_WM_B)) + dm_dig_max = 0x2A; #if RTL8192E_SUPPORT #ifdef HIGH_POWER_EXT_LNA - if ((pDM_Odm->SupportICType & (ODM_RTL8192E)) && (pDM_Odm->ExtLNA)) - dm_dig_max = 0x42; + if ((p_dm_odm->support_ic_type & (ODM_RTL8192E)) && (p_dm_odm->ext_lna)) + dm_dig_max = 0x42; #endif #endif - if (pDM_Odm->IGI_LowerBound) { - if (dm_dig_min < pDM_Odm->IGI_LowerBound) - dm_dig_min = pDM_Odm->IGI_LowerBound; - if (DIG_MaxOfMin < pDM_Odm->IGI_LowerBound) - DIG_MaxOfMin = pDM_Odm->IGI_LowerBound; - } - if (pDM_Odm->IGI_UpperBound) { - if (dm_dig_max > pDM_Odm->IGI_UpperBound) - dm_dig_max = pDM_Odm->IGI_UpperBound; - if (DIG_MaxOfMin > pDM_Odm->IGI_UpperBound) - DIG_MaxOfMin = pDM_Odm->IGI_UpperBound; + if (p_dm_odm->igi_lower_bound) { + if (dm_dig_min < p_dm_odm->igi_lower_bound) + dm_dig_min = p_dm_odm->igi_lower_bound; + if (dig_max_of_min < p_dm_odm->igi_lower_bound) + dig_max_of_min = p_dm_odm->igi_lower_bound; + } + if (p_dm_odm->igi_upper_bound) { + if (dm_dig_max > p_dm_odm->igi_upper_bound) + dm_dig_max = p_dm_odm->igi_upper_bound; + if (dig_max_of_min > p_dm_odm->igi_upper_bound) + dig_max_of_min = p_dm_odm->igi_upper_bound; } #else - //2 For WIN\CE - if(pDM_Odm->SupportICType >= ODM_RTL8188E) + /* 2 For WIN\CE */ + if (p_dm_odm->support_ic_type >= ODM_RTL8188E) dm_dig_max = 0x5A; else dm_dig_max = DM_DIG_MAX_NIC; - - if(pDM_Odm->SupportICType != ODM_RTL8821) + + if (p_dm_odm->support_ic_type != ODM_RTL8821) dm_dig_min = DM_DIG_MIN_NIC; else dm_dig_min = 0x1C; - DIG_MaxOfMin = DM_DIG_MAX_AP; + dig_max_of_min = DM_DIG_MAX_AP; #endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) /* Modify lower bound for DFS band */ - if ((((*pDM_Odm->pChannel >= 52) && (*pDM_Odm->pChannel <= 64)) || - ((*pDM_Odm->pChannel >= 100) && (*pDM_Odm->pChannel <= 140))) - #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - && phydm_dfs_master_enabled(pDM_Odm) == TRUE - #endif - ) { - bDFSBand = TRUE; - if (*pDM_Odm->pBandWidth == ODM_BW20M) - dm_dig_min = DM_DIG_MIN_AP_DFS+2; + if ((((*p_dm_odm->p_channel >= 52) && (*p_dm_odm->p_channel <= 64)) || + ((*p_dm_odm->p_channel >= 100) && (*p_dm_odm->p_channel <= 140))) +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + && phydm_dfs_master_enabled(p_dm_odm) == true +#endif + ) { + is_dfs_band = true; + if (*p_dm_odm->p_band_width == ODM_BW20M) + dm_dig_min = DM_DIG_MIN_AP_DFS + 2; else dm_dig_min = DM_DIG_MIN_AP_DFS; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): ====== In DFS band ======\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: ====== In DFS band ======\n")); } #endif } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Absolutly upper bound = 0x%x, lower bound = 0x%x\n",dm_dig_max, dm_dig_min)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Absolutly upper bound = 0x%x, lower bound = 0x%x\n", dm_dig_max, dm_dig_min)); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if (pDM_Odm->pu1ForcedIgiLb && (0 < *pDM_Odm->pu1ForcedIgiLb)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Force IGI lb to: 0x%02x !!!!!!\n", *pDM_Odm->pu1ForcedIgiLb)); - dm_dig_min = *pDM_Odm->pu1ForcedIgiLb; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (p_dm_odm->pu1_forced_igi_lb && (0 < *p_dm_odm->pu1_forced_igi_lb)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Force IGI lb to: 0x%02x\n", *p_dm_odm->pu1_forced_igi_lb)); + dm_dig_min = *p_dm_odm->pu1_forced_igi_lb; dm_dig_max = (dm_dig_min <= dm_dig_max) ? (dm_dig_max) : (dm_dig_min + 1); } #endif - //1 Adjust boundary by RSSI - if(pDM_Odm->bLinked && bPerformance) - { - //2 Modify DIG upper bound + /* 1 Adjust boundary by RSSI */ + if (p_dm_odm->is_linked && is_performance) { + /* 2 Modify DIG upper bound */ #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) offset = 15; #else - //4 Modify DIG upper bound for 92E, 8723A\B, 8821 & 8812 BT - if ((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8812|ODM_RTL8821)) && (pDM_Odm->bBtLimitedDig == 1)) - { + /* 4 Modify DIG upper bound for 92E, 8723A\B, 8821 & 8812 BT */ + if ((p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821)) && (p_dm_odm->is_bt_limited_dig == 1)) { offset = 10; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Coex. case: Force upper bound to RSSI + %d !!!!!!\n", offset)); - } - else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Coex. case: Force upper bound to RSSI + %d\n", offset)); + } else offset = 15; #endif - if((pDM_Odm->RSSI_Min + offset) > dm_dig_max ) - pDM_DigTable->rx_gain_range_max = dm_dig_max; - else if((pDM_Odm->RSSI_Min + offset) < dm_dig_min ) - pDM_DigTable->rx_gain_range_max = dm_dig_min; + if ((p_dm_odm->rssi_min + offset) > dm_dig_max) + p_dm_dig_table->rx_gain_range_max = dm_dig_max; + else if ((p_dm_odm->rssi_min + offset) < dm_dig_min) + p_dm_dig_table->rx_gain_range_max = dm_dig_min; else - pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + offset; + p_dm_dig_table->rx_gain_range_max = p_dm_odm->rssi_min + offset; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - //2 Modify DIG lower bound - //if(pDM_Odm->bOneEntryOnly) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + /* 2 Modify DIG lower bound */ + /* if(p_dm_odm->is_one_entry_only) */ { - if(pDM_Odm->RSSI_Min < dm_dig_min) - DIG_Dynamic_MIN = dm_dig_min; - else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) - DIG_Dynamic_MIN = DIG_MaxOfMin; + if (p_dm_odm->rssi_min < dm_dig_min) + dig_dynamic_min = dm_dig_min; + else if (p_dm_odm->rssi_min > dig_max_of_min) + dig_dynamic_min = dig_max_of_min; else - DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; + dig_dynamic_min = p_dm_odm->rssi_min; #if (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (bDFSBand) { - DIG_Dynamic_MIN = dm_dig_min; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DFS band: Force lower bound to 0x%x after link !!!!!!\n", dm_dig_min)); + if (is_dfs_band) { + dig_dynamic_min = dm_dig_min; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); } #endif } #else { - //4 For AP + /* 4 For AP */ #ifdef __ECOS HAL_REORDER_BARRIER(); #else rmb(); #endif - if (bDFSBand) - { - DIG_Dynamic_MIN = dm_dig_min; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DFS band: Force lower bound to 0x%x after link !!!!!!\n", dm_dig_min)); - } - else - { - if(pDM_Odm->RSSI_Min < dm_dig_min) - DIG_Dynamic_MIN = dm_dig_min; - else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) - DIG_Dynamic_MIN = DIG_MaxOfMin; + if (is_dfs_band) { + dig_dynamic_min = dm_dig_min; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); + } else { + if (p_dm_odm->rssi_min < dm_dig_min) + dig_dynamic_min = dm_dig_min; + else if (p_dm_odm->rssi_min > dig_max_of_min) + dig_dynamic_min = dig_max_of_min; else - DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; + dig_dynamic_min = p_dm_odm->rssi_min; } } #endif - } - else - { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) - if(bPerformance && bDFSBand) - { - pDM_DigTable->rx_gain_range_max = 0x28; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DFS band: Force upper bound to 0x%x before link !!!!!!\n", pDM_DigTable->rx_gain_range_max)); - } - else + } else { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + if (is_performance && is_dfs_band) { + p_dm_dig_table->rx_gain_range_max = 0x28; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: Force upper bound to 0x%x before link\n", p_dm_dig_table->rx_gain_range_max)); + } else #endif { - if (bPerformance) - pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_OF_MIN; + if (is_performance) + p_dm_dig_table->rx_gain_range_max = DM_DIG_MAX_OF_MIN; else - pDM_DigTable->rx_gain_range_max = dm_dig_max; + p_dm_dig_table->rx_gain_range_max = dm_dig_max; } - DIG_Dynamic_MIN = dm_dig_min; + dig_dynamic_min = dm_dig_min; } - - //1 Force Lower Bound for AntDiv - if(pDM_Odm->bLinked && !pDM_Odm->bOneEntryOnly) - { - if((pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) && (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) - { - if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV || pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) { - if (pDM_DigTable->AntDiv_RSSI_max > DIG_MaxOfMin) - DIG_Dynamic_MIN = DIG_MaxOfMin; + + /* 1 Force Lower Bound for AntDiv */ + if (p_dm_odm->is_linked && !p_dm_odm->is_one_entry_only) { + if ((p_dm_odm->support_ic_type & ODM_ANTDIV_SUPPORT) && (p_dm_odm->support_ability & ODM_BB_ANT_DIV)) { + if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV || p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) { + if (p_dm_dig_table->ant_div_rssi_max > dig_max_of_min) + dig_dynamic_min = dig_max_of_min; else - DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Antenna diversity case: Force lower bound to 0x%x !!!!!!\n", DIG_Dynamic_MIN)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Antenna diversity case: RSSI_max = 0x%x !!!!!!\n", pDM_DigTable->AntDiv_RSSI_max)); + dig_dynamic_min = (u8) p_dm_dig_table->ant_div_rssi_max; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: AntDiv case: Force lower bound to 0x%x\n", dig_dynamic_min)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: AntDiv case: RSSI_max = 0x%x\n", p_dm_dig_table->ant_div_rssi_max)); } } } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust boundary by RSSI Upper bound = 0x%x, Lower bound = 0x%x\n", - pDM_DigTable->rx_gain_range_max, DIG_Dynamic_MIN)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Link status: bLinked = %d, RSSI = %d, bFirstConnect = %d, bFirsrDisConnect = %d\n\n", - pDM_Odm->bLinked, pDM_Odm->RSSI_Min, FirstConnect, FirstDisConnect)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Adjust boundary by RSSI Upper bound = 0x%x, Lower bound = 0x%x\n", + p_dm_dig_table->rx_gain_range_max, dig_dynamic_min)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Link status: is_linked = %d, RSSI = %d, bFirstConnect = %d, bFirsrDisConnect = %d\n", + p_dm_odm->is_linked, p_dm_odm->rssi_min, first_connect, first_dis_connect)); - //1 Modify DIG lower bound, deal with abnormal case - //2 Abnormal false alarm case -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) - if(bDFSBand) - { - pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; - } + /* 1 Modify DIG lower bound, deal with abnormal case */ + /* 2 Abnormal false alarm case */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + if (is_dfs_band) + p_dm_dig_table->rx_gain_range_min = dig_dynamic_min; else #endif { - if(!pDM_Odm->bLinked) - { - pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; - - if (FirstDisConnect) - pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; - } - else - pDM_DigTable->rx_gain_range_min = odm_ForbiddenIGICheck(pDM_Odm, DIG_Dynamic_MIN, CurrentIGI); - } - - //2 Abnormal # beacon case -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(pDM_Odm->bLinked && !FirstConnect) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Beacon Num (%d)\n", pDM_Odm->PhyDbgInfo.NumQryBeaconPkt)); - if((pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 5) && (pDM_Odm->bsta_state)) - { - pDM_DigTable->rx_gain_range_min = 0x1c; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnrormal #beacon (%d) case in STA mode: Force lower bound to 0x%x !!!!!!\n\n", - pDM_Odm->PhyDbgInfo.NumQryBeaconPkt, pDM_DigTable->rx_gain_range_min)); + if (!p_dm_odm->is_linked) { + p_dm_dig_table->rx_gain_range_min = dig_dynamic_min; + + if (first_dis_connect) + p_dm_dig_table->forbidden_igi = dig_dynamic_min; + } else + p_dm_dig_table->rx_gain_range_min = odm_forbidden_igi_check(p_dm_odm, dig_dynamic_min, current_igi); + } + + /* 2 Abnormal # beacon case */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (p_dm_odm->is_linked && !first_connect) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Beacon Num (%d)\n", p_dm_odm->phy_dbg_info.num_qry_beacon_pkt)); +#if (RTL8723D_SUPPORT == 1) + if (p_dm_odm->support_ic_type != ODM_RTL8723D) { + if ((p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 5) && (p_dm_odm->bsta_state)) { + p_dm_dig_table->rx_gain_range_min = 0x1c; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnrormal #beacon (%d) case in STA mode: Force lower bound to 0x%x\n", + p_dm_odm->phy_dbg_info.num_qry_beacon_pkt, p_dm_dig_table->rx_gain_range_min)); + } } +#endif } #endif - //2 Abnormal lower bound case - if(pDM_DigTable->rx_gain_range_min > pDM_DigTable->rx_gain_range_max) - { - pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnrormal lower bound case: Force lower bound to 0x%x !!!!!!\n\n",pDM_DigTable->rx_gain_range_min)); + /* 2 Abnormal lower bound case */ + if (p_dm_dig_table->rx_gain_range_min > p_dm_dig_table->rx_gain_range_max) { + p_dm_dig_table->rx_gain_range_min = p_dm_dig_table->rx_gain_range_max; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnrormal lower bound case: Force lower bound to 0x%x\n", p_dm_dig_table->rx_gain_range_min)); } - - //1 False alarm threshold decision - odm_FAThresholdCheck(pDM_Odm, bDFSBand, bPerformance, RxTp, TxTp, dm_FA_thres); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): False alarm threshold = %d, %d, %d \n\n", dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); - //1 Adjust initial gain by false alarm - if(pDM_Odm->bLinked && bPerformance) - { - //2 After link - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust IGI after link\n")); + /* 1 False alarm threshold decision */ + odm_fa_threshold_check(p_dm_odm, is_dfs_band, is_performance, rx_tp, tx_tp, dm_FA_thres); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: False alarm threshold = %d, %d, %d\n", dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); - if(bFirstTpTarget || (FirstConnect && bPerformance)) - { - pDM_DigTable->LargeFAHit = 0; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE)) - if(bDFSBand) - { - if(pDM_Odm->RSSI_Min > 0x28) - CurrentIGI = 0x28; + /* 1 Adjust initial gain by false alarm */ + if (p_dm_odm->is_linked && is_performance) { + /* 2 After link */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Adjust IGI after link\n")); + + if (is_first_tp_target || (first_connect && is_performance)) { + p_dm_dig_table->large_fa_hit = 0; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + if (is_dfs_band) { + if (p_dm_odm->rssi_min > 0x28) + current_igi = 0x28; else - CurrentIGI = pDM_Odm->RSSI_Min; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DFS band: One-shot to 0x28 upmost!!!!!!\n")); - } - else + current_igi = p_dm_odm->rssi_min; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: One-shot to 0x28 upmost\n")); + } else #endif { - if(pDM_Odm->RSSI_Min < DIG_MaxOfMin) - { - if(CurrentIGI < pDM_Odm->RSSI_Min) - CurrentIGI = pDM_Odm->RSSI_Min; - } - else - { - if(CurrentIGI < DIG_MaxOfMin) - CurrentIGI = DIG_MaxOfMin; + if (p_dm_odm->rssi_min < dig_max_of_min) { + if (current_igi < p_dm_odm->rssi_min) + current_igi = p_dm_odm->rssi_min; + } else { + if (current_igi < dig_max_of_min) + current_igi = dig_max_of_min; } -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -#if (RTL8812A_SUPPORT==1) - if(pDM_Odm->SupportICType == ODM_RTL8812) - ODM_ConfigBBWithHeaderFile(pDM_Odm, CONFIG_BB_AGC_TAB_DIFF); +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (RTL8812A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8812) + odm_config_bb_with_header_file(p_dm_odm, CONFIG_BB_AGC_TAB_DIFF); #endif #endif } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First connect case: IGI does on-shot to 0x%x\n", CurrentIGI)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First connect case: IGI does on-shot to 0x%x\n", current_igi)); - } - else - { - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + } else { +#if ((DM_ODM_SUPPORT_TYPE & (ODM_AP)) && (DIG_HW == 1)) if (priv->pshare->rf_ft_var.dig_upcheck_enable) - DIG_GoUpCheck = phydm_DIG_GoUpCheck(pDM_Odm); -#endif - - if((pFalseAlmCnt->Cnt_all > dm_FA_thres[2]) && DIG_GoUpCheck) - CurrentIGI = CurrentIGI + 4; - else if ((pFalseAlmCnt->Cnt_all > dm_FA_thres[1]) && DIG_GoUpCheck) - CurrentIGI = CurrentIGI + 2; - else if(pFalseAlmCnt->Cnt_all < dm_FA_thres[0]) - CurrentIGI = CurrentIGI - 2; - - //4 Abnormal # beacon case -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if((pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 5) && (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH1) && (pDM_Odm->bsta_state)) - { - CurrentIGI = pDM_DigTable->rx_gain_range_min; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n", - pDM_Odm->PhyDbgInfo.NumQryBeaconPkt, CurrentIGI)); + dig_go_up_check = phydm_dig_go_up_check(p_dm_odm); +#endif + +#if (DIG_HW == 1) + if ((p_false_alm_cnt->cnt_all > dm_FA_thres[2]) && dig_go_up_check) + current_igi = current_igi + step_size_1; + else if ((p_false_alm_cnt->cnt_all > dm_FA_thres[1]) && dig_go_up_check) + current_igi = current_igi + step_size_2; + else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) + current_igi = current_igi - step_size_3; +#else + if (p_false_alm_cnt->cnt_all > dm_FA_thres[2]) + current_igi = current_igi + 4; + else if (p_false_alm_cnt->cnt_all > dm_FA_thres[1]) + current_igi = current_igi + 2; + else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) + current_igi = current_igi - 2; +#endif + + /* 4 Abnormal # beacon case */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if ((p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 5) && (p_false_alm_cnt->cnt_all < DM_DIG_FA_TH1) && (p_dm_odm->bsta_state)) { + current_igi = p_dm_dig_table->rx_gain_range_min; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n", + p_dm_odm->phy_dbg_info.num_qry_beacon_pkt, current_igi)); } #endif } - } - else - { - //2 Before link - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust IGI before link\n")); - - if(FirstDisConnect || bFirstCoverage) - { - CurrentIGI = dm_dig_min; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First disconnect case: IGI does on-shot to lower bound\n")); - } - else - { + } else { + /* 2 Before link */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Adjust IGI before link\n")); -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if (first_dis_connect || is_first_coverage) { + current_igi = dm_dig_min; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First disconnect case: IGI does on-shot to lower bound\n")); + } else { + +#if ((DM_ODM_SUPPORT_TYPE & (ODM_AP)) && (DIG_HW == 1)) if (priv->pshare->rf_ft_var.dig_upcheck_enable) - DIG_GoUpCheck = phydm_DIG_GoUpCheck(pDM_Odm); + dig_go_up_check = phydm_dig_go_up_check(p_dm_odm); +#endif + +#if (DIG_HW == 1) + if ((p_false_alm_cnt->cnt_all > dm_FA_thres[2]) && dig_go_up_check) + current_igi = current_igi + step_size_1; + else if ((p_false_alm_cnt->cnt_all > dm_FA_thres[1]) && dig_go_up_check) + current_igi = current_igi + step_size_2; + else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) + current_igi = current_igi - step_size_3; +#else + if (p_false_alm_cnt->cnt_all > dm_FA_thres[2]) + current_igi = current_igi + 4; + else if (p_false_alm_cnt->cnt_all > dm_FA_thres[1]) + current_igi = current_igi + 2; + else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) + current_igi = current_igi - 2; #endif - - if((pFalseAlmCnt->Cnt_all > dm_FA_thres[2]) && DIG_GoUpCheck) - CurrentIGI = CurrentIGI + 4; - else if ((pFalseAlmCnt->Cnt_all > dm_FA_thres[1]) && DIG_GoUpCheck) - CurrentIGI = CurrentIGI + 2; - else if(pFalseAlmCnt->Cnt_all < dm_FA_thres[0]) - CurrentIGI = CurrentIGI - 2; } } - //1 Check initial gain by upper/lower bound - if(CurrentIGI < pDM_DigTable->rx_gain_range_min) - CurrentIGI = pDM_DigTable->rx_gain_range_min; - - if(CurrentIGI > pDM_DigTable->rx_gain_range_max) - CurrentIGI = pDM_DigTable->rx_gain_range_max; + /* 1 Check initial gain by upper/lower bound */ + if (current_igi < p_dm_dig_table->rx_gain_range_min) + current_igi = p_dm_dig_table->rx_gain_range_min; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x, TotalFA = %d\n\n", CurrentIGI, pFalseAlmCnt->Cnt_all)); + if (current_igi > p_dm_dig_table->rx_gain_range_max) + current_igi = p_dm_dig_table->rx_gain_range_max; - //1 Update status + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: cur_ig_value=0x%x, TotalFA = %d\n", current_igi, p_false_alm_cnt->cnt_all)); + + /* 1 Update status */ { #if ((DM_ODM_SUPPORT_TYPE & ODM_WIN) || ((DM_ODM_SUPPORT_TYPE & ODM_CE) && (ODM_CONFIG_BT_COEXIST == 1))) - if(pDM_Odm->bBtHsOperation) - { - if(pDM_Odm->bLinked) - { - if(pDM_DigTable->BT30_CurIGI > (CurrentIGI)) - ODM_Write_DIG(pDM_Odm, CurrentIGI); + if (p_dm_odm->is_bt_hs_operation) { + if (p_dm_odm->is_linked) { + if (p_dm_dig_table->bt30_cur_igi > (current_igi)) + odm_write_dig(p_dm_odm, current_igi); else - ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI); - - pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; - pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; - } - else - { - if(pDM_Odm->bLinkInProcess) - ODM_Write_DIG(pDM_Odm, 0x1c); - else if(pDM_Odm->bBtConnectProcess) - ODM_Write_DIG(pDM_Odm, 0x28); + odm_write_dig(p_dm_odm, p_dm_dig_table->bt30_cur_igi); + + p_dm_dig_table->is_media_connect_0 = p_dm_odm->is_linked; + p_dm_dig_table->dig_dynamic_min_0 = dig_dynamic_min; + } else { + if (p_dm_odm->is_link_in_process) + odm_write_dig(p_dm_odm, 0x1c); + else if (p_dm_odm->is_bt_connect_process) + odm_write_dig(p_dm_odm, 0x28); else - ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + odm_write_dig(p_dm_odm, p_dm_dig_table->bt30_cur_igi);/* odm_write_dig(p_dm_odm, p_dm_dig_table->cur_ig_value); */ } - } - else // BT is not using + } else /* BT is not using */ #endif { - ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); - pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; - pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; + odm_write_dig(p_dm_odm, current_igi);/* odm_write_dig(p_dm_odm, p_dm_dig_table->cur_ig_value); */ + p_dm_dig_table->is_media_connect_0 = p_dm_odm->is_linked; + p_dm_dig_table->dig_dynamic_min_0 = dig_dynamic_min; } } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG end\n")); } -VOID -odm_DIGbyRSSI_LPS( - IN PVOID pDM_VOID - ) +void +odm_dig_by_rssi_lps( + void *p_dm_void +) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - u1Byte RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C - u1Byte CurrentIGI=pDM_Odm->RSSI_Min; + u8 rssi_lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */ + u8 current_igi = p_dm_odm->rssi_min; - if(odm_DigAbort(pDM_Odm) == TRUE) + if (odm_dig_abort(p_dm_odm) == true) return; - CurrentIGI=CurrentIGI+RSSI_OFFSET_DIG; + current_igi = current_igi + RSSI_OFFSET_DIG; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS()==>\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps()==>\n")); - // Using FW PS mode to make IGI - //Adjust by FA in LPS MODE - if(pFalseAlmCnt->Cnt_all> DM_DIG_FA_TH2_LPS) - CurrentIGI = CurrentIGI+4; - else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS) - CurrentIGI = CurrentIGI+2; - else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS) - CurrentIGI = CurrentIGI-2; + /* Using FW PS mode to make IGI */ + /* Adjust by FA in LPS MODE */ + if (p_false_alm_cnt->cnt_all > DM_DIG_FA_TH2_LPS) + current_igi = current_igi + 4; + else if (p_false_alm_cnt->cnt_all > DM_DIG_FA_TH1_LPS) + current_igi = current_igi + 2; + else if (p_false_alm_cnt->cnt_all < DM_DIG_FA_TH0_LPS) + current_igi = current_igi - 2; - //Lower bound checking + /* Lower bound checking */ - //RSSI Lower bound check - if((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC) - RSSI_Lower =(pDM_Odm->RSSI_Min-10); + /* RSSI Lower bound check */ + if ((p_dm_odm->rssi_min - 10) > DM_DIG_MIN_NIC) + rssi_lower = (p_dm_odm->rssi_min - 10); else - RSSI_Lower =DM_DIG_MIN_NIC; + rssi_lower = DM_DIG_MIN_NIC; - //Upper and Lower Bound checking - if(CurrentIGI > DM_DIG_MAX_NIC) - CurrentIGI = DM_DIG_MAX_NIC; - else if(CurrentIGI < RSSI_Lower) - CurrentIGI = RSSI_Lower; + /* Upper and Lower Bound checking */ + if (current_igi > DM_DIG_MAX_NIC) + current_igi = DM_DIG_MAX_NIC; + else if (current_igi < rssi_lower) + current_igi = rssi_lower; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): pFalseAlmCnt->Cnt_all = %d\n",pFalseAlmCnt->Cnt_all)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): pDM_Odm->RSSI_Min = %d\n",pDM_Odm->RSSI_Min)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): CurrentIGI = 0x%x\n",CurrentIGI)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps(): p_false_alm_cnt->cnt_all = %d\n", p_false_alm_cnt->cnt_all)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps(): p_dm_odm->rssi_min = %d\n", p_dm_odm->rssi_min)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps(): current_igi = 0x%x\n", current_igi)); - ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + odm_write_dig(p_dm_odm, current_igi);/* odm_write_dig(p_dm_odm, p_dm_dig_table->cur_ig_value); */ #endif } -//3============================================================ -//3 FASLE ALARM CHECK -//3============================================================ +/* 3============================================================ + * 3 FASLE ALARM CHECK + * 3============================================================ */ -VOID -odm_FalseAlarmCounterStatistics( - IN PVOID pDM_VOID - ) +void +odm_false_alarm_counter_statistics( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - u4Byte ret_value; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + u32 ret_value; #if (DM_ODM_SUPPORT_TYPE == ODM_AP) -//Mark there, and check this in odm_DMWatchDog -#if 0 //(DM_ODM_SUPPORT_TYPE == ODM_AP) - prtl8192cd_priv priv = pDM_Odm->priv; - if( (priv->auto_channel != 0) && (priv->auto_channel != 2) ) + /* Mark there, and check this in odm_DMWatchDog */ +#if 0 /* (DM_ODM_SUPPORT_TYPE == ODM_AP) */ + struct rtl8192cd_priv *priv = p_dm_odm->priv; + if ((priv->auto_channel != 0) && (priv->auto_channel != 2)) return; #endif #endif - if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) + if (!(p_dm_odm->support_ability & ODM_BB_FA_CNT)) return; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics()======>\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("FA_Counter()======>\n")); -#if (ODM_IC_11N_SERIES_SUPPORT == 1) - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) - { +#if (ODM_IC_11N_SERIES_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - //hold ofdm counter - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); //hold page C counter - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); //hold page D counter - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); - FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); - FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); + /* hold ofdm counter */ + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */ + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */ + + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD); + false_alm_cnt->cnt_fast_fsync = (ret_value & 0xffff); + false_alm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); - FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); - FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD); + false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff); + false_alm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); - FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); - FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD); + false_alm_cnt->cnt_rate_illegal = (ret_value & 0xffff); + false_alm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); - FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD); + false_alm_cnt->cnt_mcs_fail = (ret_value & 0xffff); - FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + - FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + - FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; + false_alm_cnt->cnt_ofdm_fail = false_alm_cnt->cnt_parity_fail + false_alm_cnt->cnt_rate_illegal + + false_alm_cnt->cnt_crc8_fail + false_alm_cnt->cnt_mcs_fail + + false_alm_cnt->cnt_fast_fsync + false_alm_cnt->cnt_sb_search_fail; /* read CCK CRC32 counter */ - FalseAlmCnt->cnt_cck_crc32_error = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CRC32_ERROR_CNT_11N, bMaskDWord); - FalseAlmCnt->cnt_cck_crc32_ok= ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CRC32_OK_CNT_11N, bMaskDWord); + false_alm_cnt->cnt_cck_crc32_error = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CRC32_ERROR_CNT_11N, MASKDWORD); + false_alm_cnt->cnt_cck_crc32_ok = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CRC32_OK_CNT_11N, MASKDWORD); /* read OFDM CRC32 counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_CRC32_CNT_11N, bMaskDWord); - FalseAlmCnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->cnt_ofdm_crc32_ok= ret_value & 0xffff; + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD); + false_alm_cnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff; /* read HT CRC32 counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_HT_CRC32_CNT_11N, bMaskDWord); - FalseAlmCnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->cnt_ht_crc32_ok= ret_value & 0xffff; + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD); + false_alm_cnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff; /* read VHT CRC32 counter */ - FalseAlmCnt->cnt_vht_crc32_error = 0; - FalseAlmCnt->cnt_vht_crc32_ok= 0; + false_alm_cnt->cnt_vht_crc32_error = 0; + false_alm_cnt->cnt_vht_crc32_ok = 0; + +#if (RTL8723D_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + /* read HT CRC32 agg counter */ + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_HT_CRC32_CNT_11N_AGG, MASKDWORD); + false_alm_cnt->cnt_ht_crc32_error_agg = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_ht_crc32_ok_agg= ret_value & 0xffff; + } +#endif + -#if (RTL8188E_SUPPORT==1) - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord); - FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); - FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); +#if (RTL8188E_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_SC_CNT_11N, MASKDWORD); + false_alm_cnt->cnt_bw_lsc = (ret_value & 0xffff); + false_alm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16); } #endif { - //hold cck counter - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1); - - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); - FalseAlmCnt->Cnt_Cck_fail = ret_value; + /* hold cck counter */ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1); + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1); + + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0); + false_alm_cnt->cnt_cck_fail = ret_value; - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); - FalseAlmCnt->Cnt_Cck_fail += (ret_value& 0xff)<<8; + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3); + false_alm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); - FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) |((ret_value&0xFF00)>>8); + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD); + false_alm_cnt->cnt_cck_cca = ((ret_value & 0xFF) << 8) | ((ret_value & 0xFF00) >> 8); } - - FalseAlmCnt->Cnt_all_pre = FalseAlmCnt->Cnt_all; - - FalseAlmCnt->Cnt_all = ( FalseAlmCnt->Cnt_Fast_Fsync + - FalseAlmCnt->Cnt_SB_Search_fail + - FalseAlmCnt->Cnt_Parity_Fail + - FalseAlmCnt->Cnt_Rate_Illegal + - FalseAlmCnt->Cnt_Crc8_fail + - FalseAlmCnt->Cnt_Mcs_fail + - FalseAlmCnt->Cnt_Cck_fail); - FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; + false_alm_cnt->cnt_all_pre = false_alm_cnt->cnt_all; - if (pDM_Odm->SupportICType >= ODM_RTL8188E) { + false_alm_cnt->cnt_all = (false_alm_cnt->cnt_fast_fsync + + false_alm_cnt->cnt_sb_search_fail + + false_alm_cnt->cnt_parity_fail + + false_alm_cnt->cnt_rate_illegal + + false_alm_cnt->cnt_crc8_fail + + false_alm_cnt->cnt_mcs_fail + + false_alm_cnt->cnt_cck_fail); + + false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_ofdm_cca + false_alm_cnt->cnt_cck_cca; + + if (p_dm_odm->support_ic_type >= ODM_RTL8188E) { /*reset false alarm counter registers*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1); - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1); - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1); + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1); + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0); /*update ofdm counter*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /*update page C counter*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /*update page D counter*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0); /*update page C counter*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0); /*update page D counter*/ /*reset CCK CCA counter*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2); + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 2); /*reset CCK FA counter*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2); + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2); /*reset CRC32 counter*/ - ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_F_RST_11N, BIT16, 1); - ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_F_RST_11N, BIT16, 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_F_RST_11N, BIT(16), 1); + odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_F_RST_11N, BIT(16), 0); } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n", + false_alm_cnt->cnt_parity_fail, false_alm_cnt->cnt_rate_illegal, false_alm_cnt->cnt_crc8_fail, false_alm_cnt->cnt_mcs_fail, false_alm_cnt->cnt_fast_fsync, false_alm_cnt->cnt_sb_search_fail)); - /* Get debug port 0 */ - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x0); - FalseAlmCnt->dbg_port0 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord); - - /* Get EDCCA flag */ - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208); - FalseAlmCnt->edcca_flag = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, BIT30); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", - FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", - FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", - FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); } #endif -#if (ODM_IC_11AC_SERIES_SUPPORT == 1) - if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - { - u4Byte CCKenable; - +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + u32 cck_enable; + /* read OFDM FA counter */ - FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord); + false_alm_cnt->cnt_ofdm_fail = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_11AC, MASKLWORD); /* Read CCK FA counter */ - FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord); + false_alm_cnt->cnt_cck_fail = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_FA_11AC, MASKLWORD); /* read CCK/OFDM CCA counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11AC, bMaskDWord); - FalseAlmCnt->Cnt_OFDM_CCA = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->Cnt_CCK_CCA = ret_value & 0xffff; + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD); + false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_cck_cca = ret_value & 0xffff; /* read CCK CRC32 counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CRC32_CNT_11AC, bMaskDWord); - FalseAlmCnt->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->cnt_cck_crc32_ok= ret_value & 0xffff; + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD); + false_alm_cnt->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_cck_crc32_ok = ret_value & 0xffff; /* read OFDM CRC32 counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_CRC32_CNT_11AC, bMaskDWord); - FalseAlmCnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->cnt_ofdm_crc32_ok= ret_value & 0xffff; + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD); + false_alm_cnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff; /* read HT CRC32 counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_HT_CRC32_CNT_11AC, bMaskDWord); - FalseAlmCnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->cnt_ht_crc32_ok= ret_value & 0xffff; + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD); + false_alm_cnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff; /* read VHT CRC32 counter */ - ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_VHT_CRC32_CNT_11AC, bMaskDWord); - FalseAlmCnt->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16; - FalseAlmCnt->cnt_vht_crc32_ok= ret_value & 0xffff; + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD); + false_alm_cnt->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_vht_crc32_ok = ret_value & 0xffff; -#if (RTL8881A_SUPPORT==1) +#if (RTL8881A_SUPPORT == 1) /* For 8881A */ - if(pDM_Odm->SupportICType == ODM_RTL8881A) - { - u4Byte Cnt_Ofdm_fail_temp = 0; - - if(FalseAlmCnt->Cnt_Ofdm_fail >= FalseAlmCnt->Cnt_Ofdm_fail_pre) - { - Cnt_Ofdm_fail_temp = FalseAlmCnt->Cnt_Ofdm_fail_pre; - FalseAlmCnt->Cnt_Ofdm_fail_pre = FalseAlmCnt->Cnt_Ofdm_fail; - FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Ofdm_fail - Cnt_Ofdm_fail_temp; - } - else - FalseAlmCnt->Cnt_Ofdm_fail_pre = FalseAlmCnt->Cnt_Ofdm_fail; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail_pre)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail_pre=%d\n", Cnt_Ofdm_fail_temp)); - + if (p_dm_odm->support_ic_type == ODM_RTL8881A) { + u32 cnt_ofdm_fail_temp = 0; + + if (false_alm_cnt->cnt_ofdm_fail >= false_alm_cnt->cnt_ofdm_fail_pre) { + cnt_ofdm_fail_temp = false_alm_cnt->cnt_ofdm_fail_pre; + false_alm_cnt->cnt_ofdm_fail_pre = false_alm_cnt->cnt_ofdm_fail; + false_alm_cnt->cnt_ofdm_fail = false_alm_cnt->cnt_ofdm_fail - cnt_ofdm_fail_temp; + } else + false_alm_cnt->cnt_ofdm_fail_pre = false_alm_cnt->cnt_ofdm_fail; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_false_alarm_counter_statistics(): cnt_ofdm_fail=%d\n", false_alm_cnt->cnt_ofdm_fail_pre)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_false_alarm_counter_statistics(): cnt_ofdm_fail_pre=%d\n", cnt_ofdm_fail_temp)); + /* Reset FA counter by enable/disable OFDM */ - if(FalseAlmCnt->Cnt_Ofdm_fail_pre >= 0x7fff) - { - // reset OFDM - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT29,0); - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT29,1); - FalseAlmCnt->Cnt_Ofdm_fail_pre = 0; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Reset false alarm counter\n")); + if (false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) { + /* reset OFDM */ + odm_set_bb_reg(p_dm_odm, ODM_REG_BB_RX_PATH_11AC, BIT(29), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_BB_RX_PATH_11AC, BIT(29), 1); + false_alm_cnt->cnt_ofdm_fail_pre = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_false_alarm_counter_statistics(): Reset false alarm counter\n")); } } #endif /* reset OFDM FA coutner */ - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1); - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 1); + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 0); /* reset CCK FA counter */ - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0); - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1); + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 1); /* reset CCA counter */ - ODM_SetBBReg(pDM_Odm, ODM_REG_RST_RPT_11AC, BIT0, 1); - ODM_SetBBReg(pDM_Odm, ODM_REG_RST_RPT_11AC, BIT0, 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_RST_RPT_11AC, BIT(0), 1); + odm_set_bb_reg(p_dm_odm, ODM_REG_RST_RPT_11AC, BIT(0), 0); - CCKenable = ODM_GetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT28); - if(CCKenable)//if(*pDM_Odm->pBandType == ODM_BAND_2_4G) - { - FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail; - FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_CCK_CCA + FalseAlmCnt->Cnt_OFDM_CCA; + cck_enable = odm_get_bb_reg(p_dm_odm, ODM_REG_BB_RX_PATH_11AC, BIT(28)); + if (cck_enable) { /* if(*p_dm_odm->p_band_type == ODM_BAND_2_4G) */ + false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail + false_alm_cnt->cnt_cck_fail; + false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_cck_cca + false_alm_cnt->cnt_ofdm_cca; + } else { + false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail; + false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_ofdm_cca; } - else - { - FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail; - FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA; + } +#endif + if (p_dm_odm->support_ic_type != ODM_RTL8723D) { + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/ + false_alm_cnt->dbg_port0 = phydm_get_bb_dbg_port_value(p_dm_odm); + phydm_release_bb_dbg_port(p_dm_odm); } - /* Get debug port 0 */ - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x0); - FalseAlmCnt->dbg_port0 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord); - - /* Get EDCCA flag */ - ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209); - FalseAlmCnt->edcca_flag = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, BIT30); - + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) { + if (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E)) + false_alm_cnt->edcca_flag = (boolean)((phydm_get_bb_dbg_port_value(p_dm_odm) & BIT(30)) >> 30); + else + false_alm_cnt->edcca_flag = (boolean)((phydm_get_bb_dbg_port_value(p_dm_odm) & BIT(29)) >> 29); + phydm_release_bb_dbg_port(p_dm_odm); + } } -#endif + false_alm_cnt->cnt_crc32_error_all = false_alm_cnt->cnt_vht_crc32_error + false_alm_cnt->cnt_ht_crc32_error + false_alm_cnt->cnt_ofdm_crc32_error + false_alm_cnt->cnt_cck_crc32_error; + false_alm_cnt->cnt_crc32_ok_all = false_alm_cnt->cnt_vht_crc32_ok + false_alm_cnt->cnt_ht_crc32_ok + false_alm_cnt->cnt_ofdm_crc32_ok + false_alm_cnt->cnt_cck_crc32_ok; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all)); - FalseAlmCnt->cnt_crc32_error_all = FalseAlmCnt->cnt_vht_crc32_error + FalseAlmCnt->cnt_ht_crc32_error + FalseAlmCnt->cnt_ofdm_crc32_error + FalseAlmCnt->cnt_cck_crc32_error; - FalseAlmCnt->cnt_crc32_ok_all = FalseAlmCnt->cnt_vht_crc32_ok + FalseAlmCnt->cnt_ht_crc32_ok + FalseAlmCnt->cnt_ofdm_crc32_ok + FalseAlmCnt->cnt_cck_crc32_ok; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_OFDM_CCA=%d\n", FalseAlmCnt->Cnt_OFDM_CCA)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_CCK_CCA=%d\n", FalseAlmCnt->Cnt_CCK_CCA)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_CCA_all=%d\n", FalseAlmCnt->Cnt_CCA_all)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): CCK CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_cck_crc32_error, FalseAlmCnt->cnt_cck_crc32_ok)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): OFDM CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_ofdm_crc32_error, FalseAlmCnt->cnt_ofdm_crc32_ok)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): HT CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_ht_crc32_error, FalseAlmCnt->cnt_ht_crc32_ok)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): VHT CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_vht_crc32_error, FalseAlmCnt->cnt_vht_crc32_ok)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Total CRC32 fail: %d, ok: %d\n", FalseAlmCnt->cnt_crc32_error_all, FalseAlmCnt->cnt_crc32_ok_all)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): dbg port 0x0 = 0x%x, EDCCA = %d\n\n", FalseAlmCnt->dbg_port0, FalseAlmCnt->edcca_flag)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[CCK] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_cck_crc32_error, false_alm_cnt->cnt_cck_crc32_ok)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[OFDM]CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_ofdm_crc32_error, false_alm_cnt->cnt_ofdm_crc32_ok)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[ HT ] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_ht_crc32_error, false_alm_cnt->cnt_ht_crc32_ok)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[VHT] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_vht_crc32_error, false_alm_cnt->cnt_vht_crc32_ok)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[VHT] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_crc32_error_all, false_alm_cnt->cnt_crc32_ok_all)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n\n", false_alm_cnt->dbg_port0, false_alm_cnt->edcca_flag)); } -//3============================================================ -//3 CCK Packet Detect Threshold -//3============================================================ +/* 3============================================================ + * 3 CCK Packet Detect threshold + * 3============================================================ */ -VOID -odm_PauseCCKPacketDetection( - IN PVOID pDM_VOID, - IN PHYDM_PAUSE_TYPE PauseType, - IN PHYDM_PAUSE_LEVEL pause_level, - IN u1Byte CCKPDThreshold +void +odm_pause_cck_packet_detection( + void *p_dm_void, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_level, + u8 cck_pd_threshold ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; +#if PHYDM_SUPPORT_CCKPD + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection()=========> level = %d\n", pause_level)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection()=========> level = %d\n", pause_level)); - if ((pDM_DigTable->pause_cckpd_level == 0) && (!(pDM_Odm->SupportAbility & ODM_BB_CCK_PD) || !(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Return: SupportAbility ODM_BB_CCK_PD or ODM_BB_FA_CNT is disabled\n")); + if ((p_dm_dig_table->pause_cckpd_level == 0) && (!(p_dm_odm->support_ability & ODM_BB_CCK_PD) || !(p_dm_odm->support_ability & ODM_BB_FA_CNT))) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Return: support_ability ODM_BB_CCK_PD or ODM_BB_FA_CNT is disabled\n")); return; } if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_PauseCCKPacketDetection(): Return: Wrong pause level !!\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_pause_cck_packet_detection(): Return: Wrong pause level !!\n")); return; } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_cckpd_level, CCKPDThreshold)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - pDM_DigTable->pause_cckpd_value[7], pDM_DigTable->pause_cckpd_value[6], pDM_DigTable->pause_cckpd_value[5], pDM_DigTable->pause_cckpd_value[4], - pDM_DigTable->pause_cckpd_value[3], pDM_DigTable->pause_cckpd_value[2], pDM_DigTable->pause_cckpd_value[1], pDM_DigTable->pause_cckpd_value[0])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_cckpd_level, cck_pd_threshold)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + p_dm_dig_table->pause_cckpd_value[7], p_dm_dig_table->pause_cckpd_value[6], p_dm_dig_table->pause_cckpd_value[5], p_dm_dig_table->pause_cckpd_value[4], + p_dm_dig_table->pause_cckpd_value[3], p_dm_dig_table->pause_cckpd_value[2], p_dm_dig_table->pause_cckpd_value[1], p_dm_dig_table->pause_cckpd_value[0])); - switch (PauseType) { - /* Pause CCK Packet Detection Threshold */ + switch (pause_type) { + /* Pause CCK Packet Detection threshold */ case PHYDM_PAUSE: { /* Disable CCK PD */ - ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility & (~ODM_BB_CCK_PD)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Pause CCK packet detection threshold !!\n")); + p_dm_odm->support_ability &= ~ODM_BB_CCK_PD; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Pause CCK packet detection threshold !!\n")); /* Backup original CCK PD threshold decided by CCK PD mechanism */ - if (pDM_DigTable->pause_cckpd_level == 0) { - pDM_DigTable->CCKPDBackup = pDM_DigTable->CurCCK_CCAThres; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_PauseCCKPacketDetection(): Backup CCKPD = 0x%x, new CCKPD = 0x%x\n", pDM_DigTable->CCKPDBackup, CCKPDThreshold)); + if (p_dm_dig_table->pause_cckpd_level == 0) { + p_dm_dig_table->cck_pd_backup = p_dm_dig_table->cur_cck_cca_thres; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_pause_cck_packet_detection(): Backup CCKPD = 0x%x, new CCKPD = 0x%x\n", p_dm_dig_table->cck_pd_backup, cck_pd_threshold)); } /* Update pause level */ - pDM_DigTable->pause_cckpd_level = (pDM_DigTable->pause_cckpd_level | BIT(pause_level)); + p_dm_dig_table->pause_cckpd_level = (p_dm_dig_table->pause_cckpd_level | BIT(pause_level)); /* Record CCK PD threshold */ - pDM_DigTable->pause_cckpd_value[pause_level] = CCKPDThreshold; + p_dm_dig_table->pause_cckpd_value[pause_level] = cck_pd_threshold; /* Write new CCK PD threshold */ - if (BIT(pause_level + 1) > pDM_DigTable->pause_cckpd_level) { - ODM_Write_CCK_CCA_Thres(pDM_Odm, CCKPDThreshold); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): CCKPD of higher level = 0x%x\n", CCKPDThreshold)); + if (BIT(pause_level + 1) > p_dm_dig_table->pause_cckpd_level) { + odm_write_cck_cca_thres(p_dm_odm, cck_pd_threshold); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): CCKPD of higher level = 0x%x\n", cck_pd_threshold)); } break; } - /* Resume CCK Packet Detection Threshold */ + /* Resume CCK Packet Detection threshold */ case PHYDM_RESUME: - { + { /* check if the level is illegal or not */ - if ((pDM_DigTable->pause_cckpd_level & (BIT(pause_level))) != 0) { - pDM_DigTable->pause_cckpd_level = pDM_DigTable->pause_cckpd_level & (~(BIT(pause_level))); - pDM_DigTable->pause_cckpd_value[pause_level] = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Resume CCK PD !!\n")); + if ((p_dm_dig_table->pause_cckpd_level & (BIT(pause_level))) != 0) { + p_dm_dig_table->pause_cckpd_level = p_dm_dig_table->pause_cckpd_level & (~(BIT(pause_level))); + p_dm_dig_table->pause_cckpd_value[pause_level] = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Resume CCK PD !!\n")); } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Wrong resume level !!\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Wrong resume level !!\n")); break; } /* Resume DIG */ - if (pDM_DigTable->pause_cckpd_level == 0) { + if (p_dm_dig_table->pause_cckpd_level == 0) { /* Write backup IGI value */ - ODM_Write_CCK_CCA_Thres(pDM_Odm, pDM_DigTable->CCKPDBackup); - /* pDM_DigTable->bIgnoreDIG = TRUE; */ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Write original CCKPD = 0x%x\n", pDM_DigTable->CCKPDBackup)); + odm_write_cck_cca_thres(p_dm_odm, p_dm_dig_table->cck_pd_backup); + /* p_dm_dig_table->is_ignore_dig = true; */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Write original CCKPD = 0x%x\n", p_dm_dig_table->cck_pd_backup)); /* Enable DIG */ - ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility | ODM_BB_CCK_PD); + p_dm_odm->support_ability |= ODM_BB_CCK_PD; break; } - if (BIT(pause_level) > pDM_DigTable->pause_cckpd_level) { - s1Byte max_level; - + if (BIT(pause_level) > p_dm_dig_table->pause_cckpd_level) { + s8 max_level; + /* Calculate the maximum level now */ for (max_level = (pause_level - 1); max_level >= 0; max_level--) { - if ((pDM_DigTable->pause_cckpd_level & BIT(max_level)) > 0) + if ((p_dm_dig_table->pause_cckpd_level & BIT(max_level)) > 0) break; } - + /* write CCKPD of lower level */ - ODM_Write_CCK_CCA_Thres(pDM_Odm, pDM_DigTable->pause_cckpd_value[max_level]); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Write CCKPD (0x%x) of level (%d)\n", - pDM_DigTable->pause_cckpd_value[max_level], max_level)); + odm_write_cck_cca_thres(p_dm_odm, p_dm_dig_table->pause_cckpd_value[max_level]); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Write CCKPD (0x%x) of level (%d)\n", + p_dm_dig_table->pause_cckpd_value[max_level], max_level)); break; } break; } default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Wrong type !!\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Wrong type !!\n")); break; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_cckpd_level, CCKPDThreshold)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - pDM_DigTable->pause_cckpd_value[7], pDM_DigTable->pause_cckpd_value[6], pDM_DigTable->pause_cckpd_value[5], pDM_DigTable->pause_cckpd_value[4], - pDM_DigTable->pause_cckpd_value[3], pDM_DigTable->pause_cckpd_value[2], pDM_DigTable->pause_cckpd_value[1], pDM_DigTable->pause_cckpd_value[0])); -} + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_cckpd_level, cck_pd_threshold)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + p_dm_dig_table->pause_cckpd_value[7], p_dm_dig_table->pause_cckpd_value[6], p_dm_dig_table->pause_cckpd_value[5], p_dm_dig_table->pause_cckpd_value[4], + p_dm_dig_table->pause_cckpd_value[3], p_dm_dig_table->pause_cckpd_value[2], p_dm_dig_table->pause_cckpd_value[1], p_dm_dig_table->pause_cckpd_value[0])); +#endif +} -VOID -odm_CCKPacketDetectionThresh( - IN PVOID pDM_VOID - ) +#if PHYDM_SUPPORT_CCKPD +void +odm_cck_packet_detection_thresh( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - u1Byte CurCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres, RSSI_thd = 35; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + u8 cur_cck_cca_thres = p_dm_dig_table->cur_cck_cca_thres, RSSI_thd = 35; +#if (RTL8197F_SUPPORT == 1) + u8 pd_th = 0, cs_ration = 0; +#endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -//modify by Guo.Mingzhi 2011-12-29 - if (pDM_Odm->bDualMacSmartConcurrent == TRUE) -// if (pDM_Odm->bDualMacSmartConcurrent == FALSE) + /* modify by Guo.Mingzhi 2011-12-29 */ + if (p_dm_odm->is_dual_mac_smart_concurrent == true) return; - if(pDM_Odm->bBtHsOperation) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() write 0xcd for BT HS mode!!\n")); - ODM_Write_CCK_CCA_Thres(pDM_Odm, 0xcd); + + if (p_dm_odm->is_bt_hs_operation) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: 0xcd for BT HS mode!!\n")); + odm_write_cck_cca_thres(p_dm_odm, 0xcd); return; } #endif - if((!(pDM_Odm->SupportAbility & ODM_BB_CCK_PD)) ||(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() return==========\n")); -#ifdef MCR_WIRELESS_EXTEND - ODM_Write_CCK_CCA_Thres(pDM_Odm, 0x43); -#endif + if ((!(p_dm_odm->support_ability & ODM_BB_CCK_PD)) || (!(p_dm_odm->support_ability & ODM_BB_FA_CNT))) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: return==========\n")); + #ifdef MCR_WIRELESS_EXTEND + odm_write_cck_cca_thres(p_dm_odm, 0x43); + #endif return; } -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(pDM_Odm->ExtLNA) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (p_dm_odm->ext_lna) return; #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() ==========>\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: ==========>\n")); - if (pDM_DigTable->cckFaMa == 0xffffffff) - pDM_DigTable->cckFaMa = FalseAlmCnt->Cnt_Cck_fail; + if (p_dm_dig_table->cck_fa_ma == 0xffffffff) + p_dm_dig_table->cck_fa_ma = false_alm_cnt->cnt_cck_fail; else - pDM_DigTable->cckFaMa = ((pDM_DigTable->cckFaMa<<1) + pDM_DigTable->cckFaMa + FalseAlmCnt->Cnt_Cck_fail) >> 2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh(): CCK FA moving average = %d\n", pDM_DigTable->cckFaMa)); - - if (pDM_Odm->bLinked) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if (pDM_Odm->RSSI_Min > (RSSI_thd + 14)) - CurCCK_CCAThres = 0xed; - else if (pDM_Odm->RSSI_Min > (RSSI_thd + 6)) - CurCCK_CCAThres = 0xdd; - else if (pDM_Odm->RSSI_Min > RSSI_thd) - CurCCK_CCAThres = 0xcd; - else if (pDM_Odm->RSSI_Min > 20) { - if (pDM_DigTable->cckFaMa > ((DM_DIG_FA_TH1>>1) + (DM_DIG_FA_TH1>>3))) - CurCCK_CCAThres = 0xcd; - else if (pDM_DigTable->cckFaMa < (DM_DIG_FA_TH0>>1)) - CurCCK_CCAThres = 0x83; - } else if (pDM_Odm->RSSI_Min > 7) - CurCCK_CCAThres = 0x83; + p_dm_dig_table->cck_fa_ma = ((p_dm_dig_table->cck_fa_ma << 1) + p_dm_dig_table->cck_fa_ma + false_alm_cnt->cnt_cck_fail) >> 2; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: CCK FA moving average = %d\n", p_dm_dig_table->cck_fa_ma)); + + if (p_dm_odm->is_linked) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + + #if 0 /*for [PCIE-1596]*/ + if (p_dm_odm->rssi_min > (RSSI_thd + 14)) + cur_cck_cca_thres = 0xed; + else if (p_dm_odm->rssi_min > (RSSI_thd + 6)) + cur_cck_cca_thres = 0xdd; else - CurCCK_CCAThres = 0x40; -#else - if (pDM_DigTable->CurIGValue > (0x24 + 14)) - CurCCK_CCAThres = 0xed; - else if (pDM_DigTable->CurIGValue > (0x24 + 6)) - CurCCK_CCAThres = 0xdd; - else if (pDM_DigTable->CurIGValue > 0x24) - CurCCK_CCAThres = 0xcd; + #endif + /*Add hp_hw_id condition due to 22B LPS power consumption issue and [PCIE-1596]*/ + if (p_dm_odm->is_hp_hw_id && (p_dm_odm->traffic_load == TRAFFIC_ULTRA_LOW)) + cur_cck_cca_thres = 0x40; else { - if (pDM_DigTable->cckFaMa > 0x400) - CurCCK_CCAThres = 0x83; - else if (pDM_DigTable->cckFaMa < 0x200) - CurCCK_CCAThres = 0x40; + if (p_dm_odm->rssi_min > RSSI_thd) + cur_cck_cca_thres = 0xcd; + else if (p_dm_odm->rssi_min > 20) { + if (p_dm_dig_table->cck_fa_ma > ((DM_DIG_FA_TH1 >> 1) + (DM_DIG_FA_TH1 >> 3))) + cur_cck_cca_thres = 0xcd; + else if (p_dm_dig_table->cck_fa_ma < (DM_DIG_FA_TH0 >> 1)) + cur_cck_cca_thres = 0x83; + } else if (p_dm_odm->rssi_min > 3) { + if(p_dm_odm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) { /*for ASUS OTA test*/ + if (p_dm_dig_table->cck_fa_ma > 200) + cur_cck_cca_thres = 0xc3; + else + cur_cck_cca_thres = 0x83; + } else if (p_dm_odm->rssi_min > 7) + cur_cck_cca_thres = 0x83; + } else + cur_cck_cca_thres = 0x40; + } + +#else /*ODM_AP*/ + + if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + if ((p_dm_dig_table->cur_ig_value > (0x24 + 14)) || (p_dm_odm->rssi_min > 32)) + cur_cck_cca_thres = 0xed; + else if ((p_dm_dig_table->cur_ig_value > (0x24 + 6)) || (p_dm_odm->rssi_min > 32)) + cur_cck_cca_thres = 0xdd; + else if ((p_dm_dig_table->cur_ig_value > 0x24) || (p_dm_odm->rssi_min > 24 && p_dm_odm->rssi_min <= 30)) + cur_cck_cca_thres = 0xcd; + else if ((p_dm_dig_table->cur_ig_value <= 0x24) || (p_dm_odm->rssi_min < 22)) { + if (p_dm_dig_table->cck_fa_ma > 0x400) + cur_cck_cca_thres = 0x83; + else if (p_dm_dig_table->cck_fa_ma < 0x200) + cur_cck_cca_thres = 0x40; + } + } else { + if (p_dm_dig_table->cur_ig_value > (0x24 + 14)) + cur_cck_cca_thres = 0xed; + else if (p_dm_dig_table->cur_ig_value > (0x24 + 6)) + cur_cck_cca_thres = 0xdd; + else if (p_dm_dig_table->cur_ig_value > 0x24) + cur_cck_cca_thres = 0xcd; + else { + #if 0 + if (p_dm_dig_table->cck_fa_ma > 0x400) + cur_cck_cca_thres = 0x83; + else if (p_dm_dig_table->cck_fa_ma < 0x200) + cur_cck_cca_thres = 0x40; + #else + cur_cck_cca_thres = 0x83; + #endif + } } #endif } else { - if (pDM_DigTable->cckFaMa > 0x400) - CurCCK_CCAThres = 0x83; - else if (pDM_DigTable->cckFaMa < 0x200) - CurCCK_CCAThres = 0x40; - } - ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); + if (p_dm_dig_table->cck_fa_ma > 0x400) + cur_cck_cca_thres = 0x83; + else if (p_dm_dig_table->cck_fa_ma < 0x200) + cur_cck_cca_thres = 0x40; + } + + #if (RTL8197F_SUPPORT == 1) + /*Add by Yu Chen 20160902, pd_th for 0xa0a, cs_ration for 0xaaa*/ + if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + switch (cur_cck_cca_thres) { + case 0xed: + cs_ration = p_dm_dig_table->aaa_default + AAA_BASE + AAA_STEP*2; + pd_th = 0xd; + break; + + case 0xdd: + cs_ration = p_dm_dig_table->aaa_default + AAA_BASE + AAA_STEP; + pd_th = 0xd; + break; + + case 0xcd: + cs_ration = p_dm_dig_table->aaa_default + AAA_BASE; + pd_th = 0xd; + break; + + case 0x83: + cs_ration = p_dm_dig_table->aaa_default + AAA_STEP; + pd_th = 0x7; + break; + + case 0x40: + cs_ration = p_dm_dig_table->aaa_default; + pd_th = 0x3; + break; + + default: + cs_ration = p_dm_dig_table->aaa_default; + pd_th = 0x3; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("cck pd use default\n")); + break; + } + } + #endif /*#if (RTL8197F_SUPPORT == 1)*/ + + #if (RTL8197F_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + odm_set_bb_reg(p_dm_odm, 0xa08, 0xf0000, pd_th); + odm_set_bb_reg(p_dm_odm, 0xaa8, 0x1f0000, cs_ration); + } else + #endif + { + odm_write_cck_cca_thres(p_dm_odm, cur_cck_cca_thres); + } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() CurCCK_CCAThres = 0x%x\n", CurCCK_CCAThres)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: cck_cca_th=((0x%x))\n\n", cur_cck_cca_thres)); } +#endif -VOID -ODM_Write_CCK_CCA_Thres( - IN PVOID pDM_VOID, - IN u1Byte CurCCK_CCAThres - ) +void +odm_write_cck_cca_thres( + void *p_dm_void, + u8 cur_cck_cca_thres +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; +#if PHYDM_SUPPORT_CCKPD + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - if(pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres) //modify by Guo.Mingzhi 2012-01-03 - { - ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA,pDM_Odm), CurCCK_CCAThres); - pDM_DigTable->cckFaMa = 0xffffffff; + if (p_dm_dig_table->cur_cck_cca_thres != cur_cck_cca_thres) { /* modify by Guo.Mingzhi 2012-01-03 */ + odm_write_1byte(p_dm_odm, ODM_REG(CCK_CCA, p_dm_odm), cur_cck_cca_thres); + p_dm_dig_table->cck_fa_ma = 0xffffffff; + +#if (RTL8723D_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8723D) { /* modify by David_Ding for 8723D no Beacon issue */ + if (cur_cck_cca_thres == 0x40) + odm_write_1byte(p_dm_odm, 0xAAA, 0x0C); + else + odm_write_1byte(p_dm_odm, 0xAAA, 0x10); + } +#endif } - pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; - pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; + p_dm_dig_table->pre_cck_cca_thres = p_dm_dig_table->cur_cck_cca_thres; + p_dm_dig_table->cur_cck_cca_thres = cur_cck_cca_thres; +#endif } -BOOLEAN -phydm_DIG_GoUpCheck( - IN PVOID pDM_VOID - ) +boolean +phydm_dig_go_up_check( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PCCX_INFO CCX_INFO = &pDM_Odm->DM_CCX_INFO; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte CurIGValue = pDM_DigTable->CurIGValue; - u1Byte max_DIG_cover_bond; - u1Byte current_IGI_MaxUp_resolution; - u1Byte rx_gain_range_max; - u1Byte i = 0; - - u4Byte total_NHM_cnt; - u4Byte DIG_cover_cnt; - u4Byte over_DIG_cover_cnt; - BOOLEAN ret = TRUE; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u8 cur_ig_value = p_dm_dig_table->cur_ig_value; + u8 max_DIG_cover_bond; + u8 current_igi_max_up_resolution; + u8 rx_gain_range_max; + u8 i = 0; + + u32 total_NHM_cnt; + u32 DIG_cover_cnt; + u32 over_DIG_cover_cnt; +#endif + boolean ret = true; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; + struct rtl8192cd_priv *priv = p_dm_odm->priv; max_DIG_cover_bond = DM_DIG_MAX_AP - priv->pshare->rf_ft_var.dig_upcheck_initial_value; - current_IGI_MaxUp_resolution = CurIGValue + 6; - rx_gain_range_max = pDM_DigTable->rx_gain_range_max; - - phydm_getNHMresult(pDM_Odm); + current_igi_max_up_resolution = cur_ig_value + 6; + rx_gain_range_max = p_dm_dig_table->rx_gain_range_max; - total_NHM_cnt = CCX_INFO->NHM_result[0] + CCX_INFO->NHM_result[1]; + phydm_get_nhm_result(p_dm_odm); + + total_NHM_cnt = ccx_info->NHM_result[0] + ccx_info->NHM_result[1]; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): *****Get NHM results*****\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): *****Get NHM results*****\n")); - if (total_NHM_cnt != 0) { - /* CurIGValue < max_DIG_cover_bond - 6 */ - if (pDM_DigTable->DIG_GoUpCheck_Level == DIG_GOUPCHECK_LEVEL_0) { - DIG_cover_cnt = CCX_INFO->NHM_result[1]; - ret = ((priv->pshare->rf_ft_var.dig_level0_ratio_reciprocal * DIG_cover_cnt) >= total_NHM_cnt) ? TRUE : FALSE; + /* cur_ig_value < max_DIG_cover_bond - 6 */ + if (p_dm_dig_table->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_0) { + DIG_cover_cnt = ccx_info->NHM_result[1]; + ret = ((priv->pshare->rf_ft_var.dig_level0_ratio_reciprocal * DIG_cover_cnt) >= total_NHM_cnt) ? true : false; } - /* (max_DIG_cover_bond - 6) <= CurIGValue < DM_DIG_MAX_AP */ - else if (pDM_DigTable->DIG_GoUpCheck_Level == DIG_GOUPCHECK_LEVEL_1) { - over_DIG_cover_cnt = CCX_INFO->NHM_result[1]; - ret = (priv->pshare->rf_ft_var.dig_level1_ratio_reciprocal * over_DIG_cover_cnt < total_NHM_cnt) ? TRUE : FALSE; + /* (max_DIG_cover_bond - 6) <= cur_ig_value < DM_DIG_MAX_AP */ + else if (p_dm_dig_table->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_1) { + over_DIG_cover_cnt = ccx_info->NHM_result[1]; + ret = (priv->pshare->rf_ft_var.dig_level1_ratio_reciprocal * over_DIG_cover_cnt < total_NHM_cnt) ? true : false; if (!ret) { - /* update pDM_DigTable->rx_gain_range_max */ - pDM_DigTable->rx_gain_range_max = (rx_gain_range_max >= max_DIG_cover_bond - 6) ? (max_DIG_cover_bond - 6) : rx_gain_range_max; + /* update p_dm_dig_table->rx_gain_range_max */ + p_dm_dig_table->rx_gain_range_max = (rx_gain_range_max >= max_DIG_cover_bond - 6) ? (max_DIG_cover_bond - 6) : rx_gain_range_max; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): Noise power is beyond DIG can filter, lock rx_gain_range_max to 0x%x\n", - pDM_DigTable->rx_gain_range_max)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): Noise power is beyond DIG can filter, lock rx_gain_range_max to 0x%x\n", + p_dm_dig_table->rx_gain_range_max)); } } - - /* CurIGValue > DM_DIG_MAX_AP, foolproof */ - else if (pDM_DigTable->DIG_GoUpCheck_Level == DIG_GOUPCHECK_LEVEL_2) { - ret = TRUE; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): DIG_GoUpCheck_level = %d\n, current_IGI_MaxUp_resolution = 0x%x\n, max_DIG_cover_bond = 0x%x\n, rx_gain_range_max = 0x%x, ret = %d\n", - pDM_DigTable->DIG_GoUpCheck_Level, - current_IGI_MaxUp_resolution, - max_DIG_cover_bond, - pDM_DigTable->rx_gain_range_max, - ret)); + /* cur_ig_value > DM_DIG_MAX_AP, foolproof */ + else if (p_dm_dig_table->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_2) + ret = true; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): NHM_result = %d, %d, %d, %d\n", - CCX_INFO->NHM_result[0], CCX_INFO->NHM_result[1], CCX_INFO->NHM_result[2], CCX_INFO->NHM_result[3])); - - } - else - ret = TRUE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): DIG_GoUpCheck_level = %d\n, current_igi_max_up_resolution = 0x%x\n, max_DIG_cover_bond = 0x%x\n, rx_gain_range_max = 0x%x, ret = %d\n", + p_dm_dig_table->dig_go_up_check_level, + current_igi_max_up_resolution, + max_DIG_cover_bond, + p_dm_dig_table->rx_gain_range_max, + ret)); - for (i = 0 ; i <= 10 ; i ++) { - CCX_INFO->NHM_th[i] = 0xFF; - } - - if (CurIGValue < max_DIG_cover_bond - 6){ - CCX_INFO->NHM_th[0] = 2 * (CurIGValue - priv->pshare->rf_ft_var.dig_upcheck_initial_value); - pDM_DigTable->DIG_GoUpCheck_Level = DIG_GOUPCHECK_LEVEL_0; - } - else if (CurIGValue <= DM_DIG_MAX_AP) { - CCX_INFO->NHM_th[0] = 2 * max_DIG_cover_bond; - pDM_DigTable->DIG_GoUpCheck_Level = DIG_GOUPCHECK_LEVEL_1; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): NHM_result = %d, %d, %d, %d\n", + ccx_info->NHM_result[0], ccx_info->NHM_result[1], ccx_info->NHM_result[2], ccx_info->NHM_result[3])); + + } else + ret = true; + + for (i = 0 ; i <= 10 ; i++) + ccx_info->NHM_th[i] = 0xFF; + + if (cur_ig_value < max_DIG_cover_bond - 6) { + ccx_info->NHM_th[0] = 2 * (cur_ig_value - priv->pshare->rf_ft_var.dig_upcheck_initial_value); + p_dm_dig_table->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_0; + } else if (cur_ig_value <= DM_DIG_MAX_AP) { + ccx_info->NHM_th[0] = 2 * max_DIG_cover_bond; + p_dm_dig_table->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_1; } - /* CurIGValue > DM_DIG_MAX_AP, foolproof */ + /* cur_ig_value > DM_DIG_MAX_AP, foolproof */ else { - pDM_DigTable->DIG_GoUpCheck_Level = DIG_GOUPCHECK_LEVEL_2; - ret = TRUE; + p_dm_dig_table->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_2; + ret = true; } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): *****Set NHM settings*****\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): DIG_GoUpCheck_level = %d\n", - pDM_DigTable->DIG_GoUpCheck_Level)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_DIG_GoUpCheck(): NHM_th = 0x%x, 0x%x, 0x%x\n", - CCX_INFO->NHM_th[0], CCX_INFO->NHM_th[1], CCX_INFO->NHM_th[2])); - - CCX_INFO->NHM_inexclude_cca = NHM_EXCLUDE_CCA; - CCX_INFO->NHM_inexclude_txon = NHM_EXCLUDE_TXON; - CCX_INFO->NHM_period = 0xC350; - phydm_NHMsetting(pDM_Odm, SET_NHM_SETTING); - phydm_NHMtrigger(pDM_Odm); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): *****Set NHM settings*****\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): DIG_GoUpCheck_level = %d\n", + p_dm_dig_table->dig_go_up_check_level)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): NHM_th = 0x%x, 0x%x, 0x%x\n", + ccx_info->NHM_th[0], ccx_info->NHM_th[1], ccx_info->NHM_th[2])); + + ccx_info->nhm_inexclude_cca = NHM_EXCLUDE_CCA; + ccx_info->nhm_inexclude_txon = NHM_EXCLUDE_TXON; + ccx_info->NHM_period = 0xC350; + + phydm_nhm_setting(p_dm_odm, SET_NHM_SETTING); + phydm_nhm_trigger(p_dm_odm); #endif return ret; @@ -2025,253 +2071,233 @@ phydm_DIG_GoUpCheck( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -// <20130108, Kordan> E.g., With LNA used, we make the Rx power smaller to have a better EVM. (Asked by Willis) -VOID -odm_RFEControl( - IN PDM_ODM_T pDM_Odm, - IN u8Byte RSSIVal - ) +/* <20130108, Kordan> E.g., With LNA used, we make the Rx power smaller to have a better EVM. (Asked by Willis) */ +void +odm_rfe_control( + struct PHY_DM_STRUCT *p_dm_odm, + u64 rssi_val +) { - PADAPTER Adapter = (PADAPTER)pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - static u1Byte TRSW_HighPwr = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X, pHalData->RFEType = %d\n", - RSSIVal, TRSW_HighPwr, pHalData->RFEType )); - - if (pHalData->RFEType == 3) { - - pDM_Odm->RSSI_TRSW = RSSIVal; - - if (pDM_Odm->RSSI_TRSW >= pDM_Odm->RSSI_TRSW_H) - { - TRSW_HighPwr = 1; // Switch to - PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); // Set ANTSW=1/ANTSWB=0 for SW control - PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); // Set ANTSW=1/ANTSWB=0 for SW control - - } - else if (pDM_Odm->RSSI_TRSW <= pDM_Odm->RSSI_TRSW_L) - { - TRSW_HighPwr = 0; // Switched back - PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); // Set ANTSW=1/ANTSWB=0 for SW control - PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x0); // Set ANTSW=1/ANTSWB=0 for SW control - - } - } + struct _ADAPTER *adapter = (struct _ADAPTER *)p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + static u8 trsw_high_pwr = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L) = (%d, %d)\n", pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(RSSIVal, RSSIVal, pDM_Odm->RSSI_TRSW_iso) = (%d, %d, %d)\n", - RSSIVal, pDM_Odm->RSSI_TRSW_iso, pDM_Odm->RSSI_TRSW)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("<=== odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X\n", RSSIVal, TRSW_HighPwr)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> odm_rfe_control, RSSI = %d, trsw_high_pwr = 0x%X, p_dm_odm->rfe_type = %d\n", + rssi_val, trsw_high_pwr, p_dm_odm->rfe_type)); + + if (p_dm_odm->rfe_type == 3) { + + p_dm_odm->RSSI_TRSW = rssi_val; + + if (p_dm_odm->RSSI_TRSW >= p_dm_odm->RSSI_TRSW_H) { + trsw_high_pwr = 1; /* Switch to */ + odm_set_bb_reg(p_dm_odm, REG_ANTSEL_SW_JAGUAR, BIT(1) | BIT0, 0x1); /* Set ANTSW=1/ANTSWB=0 for SW control */ + odm_set_bb_reg(p_dm_odm, REG_ANTSEL_SW_JAGUAR, BIT(9) | BIT8, 0x3); /* Set ANTSW=1/ANTSWB=0 for SW control */ + + } else if (p_dm_odm->RSSI_TRSW <= p_dm_odm->RSSI_TRSW_L) { + trsw_high_pwr = 0; /* Switched back */ + odm_set_bb_reg(p_dm_odm, REG_ANTSEL_SW_JAGUAR, BIT(1) | BIT0, 0x1); /* Set ANTSW=1/ANTSWB=0 for SW control */ + odm_set_bb_reg(p_dm_odm, REG_ANTSEL_SW_JAGUAR, BIT(9) | BIT8, 0x0); /* Set ANTSW=1/ANTSWB=0 for SW control */ + + } + } + + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(p_dm_odm->RSSI_TRSW_H, p_dm_odm->RSSI_TRSW_L) = (%d, %d)\n", p_dm_odm->RSSI_TRSW_H, p_dm_odm->RSSI_TRSW_L)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(rssi_val, rssi_val, p_dm_odm->RSSI_TRSW_iso) = (%d, %d, %d)\n", + rssi_val, p_dm_odm->RSSI_TRSW_iso, p_dm_odm->RSSI_TRSW)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("<=== odm_rfe_control, RSSI = %d, trsw_high_pwr = 0x%X\n", rssi_val, trsw_high_pwr)); } -VOID -odm_MPT_DIGWorkItemCallback( - IN PVOID pContext - ) +void +odm_mpt_dig_work_item_callback( + void *p_context +) { - PADAPTER Adapter = (PADAPTER)pContext; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + struct _ADAPTER *adapter = (struct _ADAPTER *)p_context; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - ODM_MPT_DIG(pDM_Odm); + ODM_MPT_DIG(p_dm_odm); } -VOID -odm_MPT_DIGCallback( - PRT_TIMER pTimer +void +odm_mpt_dig_callback( + struct timer_list *p_timer ) { - PADAPTER Adapter = (PADAPTER)pTimer->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - #if DEV_BUS_TYPE==RT_PCI_INTERFACE - #if USE_WORKITEM - PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem); - #else - ODM_MPT_DIG(pDM_Odm); - #endif - #else - PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem); - #endif +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +#if USE_WORKITEM + odm_schedule_work_item(&p_dm_odm->mpt_dig_workitem); +#else + ODM_MPT_DIG(p_dm_odm); +#endif +#else + odm_schedule_work_item(&p_dm_odm->mpt_dig_workitem); +#endif } #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -VOID -odm_MPT_DIGCallback( - IN PVOID pDM_VOID +void +odm_mpt_dig_callback( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if USE_WORKITEM - PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem); + odm_schedule_work_item(&p_dm_odm->mpt_dig_workitem); #else - ODM_MPT_DIG(pDM_Odm); + ODM_MPT_DIG(p_dm_odm); #endif } #endif #if (DM_ODM_SUPPORT_TYPE != ODM_CE) -VOID -odm_MPT_Write_DIG( - IN PVOID pDM_VOID, - IN u1Byte CurIGValue +void +odm_mpt_write_dig( + void *p_dm_void, + u8 cur_ig_value ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_A,pDM_Odm), CurIGValue); + odm_write_1byte(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), cur_ig_value); #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) /* Set IGI value of CCK for new CCK AGC */ - if (pDM_Odm->cck_new_agc) { - if (pDM_Odm->SupportICType & ODM_IC_PHY_STATUE_NEW_TYPE) - ODM_SetBBReg(pDM_Odm, 0xa0c, 0x00003f00, (CurIGValue>>1)); - } + if (p_dm_odm->cck_new_agc) { + if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) + odm_set_bb_reg(p_dm_odm, 0xa0c, 0x00003f00, (cur_ig_value >> 1)); + } #endif - - if(pDM_Odm->RFType > ODM_1T1R) - ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_B,pDM_Odm), CurIGValue); - if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (pDM_Odm->RFType > ODM_2T2R)) - { - ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_C,pDM_Odm), CurIGValue); - ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_D,pDM_Odm), CurIGValue); + if (p_dm_odm->rf_type > ODM_1T1R) + odm_write_1byte(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), cur_ig_value); + + if ((p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) && (p_dm_odm->rf_type > ODM_2T2R)) { + odm_write_1byte(p_dm_odm, ODM_REG(IGI_C, p_dm_odm), cur_ig_value); + odm_write_1byte(p_dm_odm, ODM_REG(IGI_D, p_dm_odm), cur_ig_value); } - pDM_DigTable->CurIGValue = CurIGValue; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurIGValue = 0x%x\n", CurIGValue)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("pDM_Odm->RFType = 0x%x\n", pDM_Odm->RFType)); + p_dm_dig_table->cur_ig_value = cur_ig_value; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("cur_ig_value = 0x%x\n", cur_ig_value)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("p_dm_odm->rf_type = 0x%x\n", p_dm_odm->rf_type)); } -VOID +void ODM_MPT_DIG( - IN PVOID pDM_VOID - ) + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); - u1Byte CurrentIGI = pDM_DigTable->CurIGValue; - u1Byte DIG_Upper = 0x40, DIG_Lower = 0x20; - u4Byte RXOK_cal; - u4Byte RxPWDBAve_final; - u1Byte IGI_A = 0x20, IGI_B = 0x20; - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + u8 current_igi = p_dm_dig_table->cur_ig_value; + u8 dig_upper = 0x40, dig_lower = 0x20; + u32 rx_ok_cal; + u32 rx_pwdb_ave_final; + u8 IGI_A = 0x20, IGI_B = 0x20; + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if ODM_FIX_2G_DIG +#if ODM_FIX_2G_DIG IGI_A = 0x22; - IGI_B = 0x24; - #endif - + IGI_B = 0x24; +#endif + #else - if (!(pDM_Odm->priv->pshare->rf_ft_var.mp_specific && pDM_Odm->priv->pshare->mp_dig_on)) + if (!(*(p_dm_odm->p_mp_mode) && p_dm_odm->priv->pshare->mp_dig_on)) return; - if (*pDM_Odm->pBandType == ODM_BAND_5G) - DIG_Lower = 0x22; + if (*p_dm_odm->p_band_type == ODM_BAND_5G) + dig_lower = 0x22; #endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("===> ODM_MPT_DIG, pBandType = %d\n", *pDM_Odm->pBandType)); - + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> ODM_MPT_DIG, p_band_type = %d\n", *p_dm_odm->p_band_type)); + #if (ODM_FIX_2G_DIG || (DM_ODM_SUPPORT_TYPE & ODM_AP)) - if (*pDM_Odm->pBandType == ODM_BAND_5G || (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B))) // for 5G or 8814 + if (*p_dm_odm->p_band_type == ODM_BAND_5G || (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) /* for 5G or 8814 */ #else - if (1) // for both 2G/5G + if (1) /* for both 2G/5G */ #endif - { - odm_FalseAlarmCounterStatistics(pDM_Odm); + { + odm_false_alarm_counter_statistics(p_dm_odm); - RXOK_cal = pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM; - RxPWDBAve_final = (RXOK_cal != 0)?pDM_Odm->RxPWDBAve/RXOK_cal:0; + rx_ok_cal = p_dm_odm->phy_dbg_info.num_qry_phy_status_cck + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm; + rx_pwdb_ave_final = (rx_ok_cal != 0) ? p_dm_odm->rx_pwdb_ave / rx_ok_cal : 0; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; - pDM_Odm->RxPWDBAve = 0; - pDM_Odm->MPDIG_2G = FALSE; + p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; + p_dm_odm->rx_pwdb_ave = 0; + p_dm_odm->MPDIG_2G = false; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pDM_Odm->Times_2G = 0; + p_dm_odm->times_2g = 0; #endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("RX OK = %d\n", RXOK_cal)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("RSSI = %d\n", RxPWDBAve_final)); - - if (RXOK_cal >= 70 && RxPWDBAve_final <= 40) - { - if (CurrentIGI > 0x24) - odm_MPT_Write_DIG(pDM_Odm, 0x24); - } - else - { - if(pFalseAlmCnt->Cnt_all > 1000){ - CurrentIGI = CurrentIGI + 8; - } - else if(pFalseAlmCnt->Cnt_all > 200){ - CurrentIGI = CurrentIGI + 4; - } - else if (pFalseAlmCnt->Cnt_all > 50){ - CurrentIGI = CurrentIGI + 2; - } - else if (pFalseAlmCnt->Cnt_all < 2){ - CurrentIGI = CurrentIGI - 2; - } - - if (CurrentIGI < DIG_Lower ){ - CurrentIGI = DIG_Lower; - } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("RX OK = %d\n", rx_ok_cal)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("RSSI = %d\n", rx_pwdb_ave_final)); - if(CurrentIGI > DIG_Upper){ - CurrentIGI = DIG_Upper; - } + if (rx_ok_cal >= 70 && rx_pwdb_ave_final <= 40) { + if (current_igi > 0x24) + odm_mpt_write_dig(p_dm_odm, 0x24); + } else { + if (p_false_alm_cnt->cnt_all > 1000) + current_igi = current_igi + 8; + else if (p_false_alm_cnt->cnt_all > 200) + current_igi = current_igi + 4; + else if (p_false_alm_cnt->cnt_all > 50) + current_igi = current_igi + 2; + else if (p_false_alm_cnt->cnt_all < 2) + current_igi = current_igi - 2; + + if (current_igi < dig_lower) + current_igi = dig_lower; + + if (current_igi > dig_upper) + current_igi = dig_upper; - odm_MPT_Write_DIG(pDM_Odm, CurrentIGI); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG = 0x%x, Cnt_all = %d, Cnt_Ofdm_fail = %d, Cnt_Cck_fail = %d\n", - CurrentIGI, pFalseAlmCnt->Cnt_all, pFalseAlmCnt->Cnt_Ofdm_fail, pFalseAlmCnt->Cnt_Cck_fail)); + odm_mpt_write_dig(p_dm_odm, current_igi); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG = 0x%x, cnt_all = %d, cnt_ofdm_fail = %d, cnt_cck_fail = %d\n", + current_igi, p_false_alm_cnt->cnt_all, p_false_alm_cnt->cnt_ofdm_fail, p_false_alm_cnt->cnt_cck_fail)); } - } - else - { - if(pDM_Odm->MPDIG_2G == FALSE) - { - if((pDM_Odm->SupportPlatform & ODM_WIN) && !(pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B))) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("===> Fix IGI\n")); - ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_A,pDM_Odm), IGI_A); - ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_B,pDM_Odm), IGI_B); - pDM_DigTable->CurIGValue = IGI_B; - } - else - odm_MPT_Write_DIG(pDM_Odm, IGI_A); + } else { + if (p_dm_odm->MPDIG_2G == false) { + if ((p_dm_odm->support_platform & ODM_WIN) && !(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> Fix IGI\n")); + odm_write_1byte(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), IGI_A); + odm_write_1byte(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), IGI_B); + p_dm_dig_table->cur_ig_value = IGI_B; + } else + odm_mpt_write_dig(p_dm_odm, IGI_A); } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pDM_Odm->Times_2G++; + p_dm_odm->times_2g++; - if (pDM_Odm->Times_2G == 3) + if (p_dm_odm->times_2g == 3) #endif { - pDM_Odm->MPDIG_2G = TRUE; + p_dm_odm->MPDIG_2G = true; } } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (pDM_Odm->SupportICType == ODM_RTL8812) - odm_RFEControl(pDM_Odm, RxPWDBAve_final); + if (p_dm_odm->support_ic_type == ODM_RTL8812) + odm_rfe_control(p_dm_odm, rx_pwdb_ave_final); #endif - ODM_SetTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, 700); + odm_set_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer, 700); } #endif - - diff --git a/hal/phydm/phydm_dig.h b/hal/phydm/phydm_dig.h index f70acd0..77ece7c 100644 --- a/hal/phydm/phydm_dig.h +++ b/hal/phydm/phydm_dig.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,198 +11,201 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - + *****************************************************************************/ + #ifndef __PHYDMDIG_H__ #define __PHYDMDIG_H__ -#define DIG_VERSION "1.22" /* 2016.04.28 Stanley. Add CRC32 information in FA statistic */ +#define DIG_VERSION "1.32" /* 2016.09.02 YuChen. add CCK PD for 8197F*/ +#define DIG_HW 0 /* Pause DIG & CCKPD */ #define DM_DIG_MAX_PAUSE_TYPE 0x7 -typedef enum tag_DIG_GoUpCheck_Level { +enum dig_goupcheck_level { DIG_GOUPCHECK_LEVEL_0, DIG_GOUPCHECK_LEVEL_1, DIG_GOUPCHECK_LEVEL_2 - -} DIG_GOUPCHECK_LEVEL; -typedef struct _Dynamic_Initial_Gain_Threshold_ -{ - BOOLEAN bStopDIG; // for debug - BOOLEAN bIgnoreDIG; - BOOLEAN bPSDInProgress; - - u1Byte Dig_Enable_Flag; - u1Byte Dig_Ext_Port_Stage; - - int RssiLowThresh; - int RssiHighThresh; - - u4Byte FALowThresh; - u4Byte FAHighThresh; - - u1Byte CurSTAConnectState; - u1Byte PreSTAConnectState; - u1Byte CurMultiSTAConnectState; - - u1Byte PreIGValue; - u1Byte CurIGValue; - u1Byte BackupIGValue; //MP DIG - u1Byte BT30_CurIGI; - u1Byte IGIBackup; - - s1Byte BackoffVal; - s1Byte BackoffVal_range_max; - s1Byte BackoffVal_range_min; - u1Byte rx_gain_range_max; - u1Byte rx_gain_range_min; - u1Byte Rssi_val_min; - - u1Byte PreCCK_CCAThres; - u1Byte CurCCK_CCAThres; - u1Byte PreCCKPDState; - u1Byte CurCCKPDState; - u1Byte CCKPDBackup; - u1Byte pause_cckpd_level; - u1Byte pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1]; - - u1Byte LargeFAHit; - u1Byte LargeFA_Timeout; /*if (LargeFAHit), monitor "LargeFA_Timeout" sec, if timeout, LargeFAHit=0*/ - u1Byte ForbiddenIGI; - u4Byte Recover_cnt; - - u1Byte DIG_Dynamic_MIN_0; - u1Byte DIG_Dynamic_MIN_1; - BOOLEAN bMediaConnect_0; - BOOLEAN bMediaConnect_1; - - u4Byte AntDiv_RSSI_max; - u4Byte RSSI_max; - - u1Byte *bP2PInProcess; - - u1Byte pause_dig_level; - u1Byte pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1]; - - u4Byte cckFaMa; - DIG_GOUPCHECK_LEVEL DIG_GoUpCheck_Level; +}; + +struct _dynamic_initial_gain_threshold_ { + boolean is_stop_dig; /* for debug */ + boolean is_ignore_dig; + boolean is_psd_in_progress; + + u8 dig_enable_flag; + u8 dig_ext_port_stage; + + int rssi_low_thresh; + int rssi_high_thresh; + + u32 fa_low_thresh; + u32 fa_high_thresh; + + u8 cur_sta_connect_state; + u8 pre_sta_connect_state; + u8 cur_multi_sta_connect_state; + + u8 pre_ig_value; + u8 cur_ig_value; + u8 backup_ig_value; /* MP DIG */ + u8 bt30_cur_igi; + u8 igi_backup; + + s8 backoff_val; + s8 backoff_val_range_max; + s8 backoff_val_range_min; + u8 rx_gain_range_max; + u8 rx_gain_range_min; + u8 rssi_val_min; + +#if PHYDM_SUPPORT_CCKPD + u8 pre_cck_cca_thres; + u8 cur_cck_cca_thres; + u32 cck_fa_ma; + u8 pre_cck_pd_state; + u8 cur_cck_pd_state; + u8 cck_pd_backup; + u8 pause_cckpd_level; + u8 pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1]; +#endif + + u8 large_fa_hit; + u8 large_fa_timeout; /*if (large_fa_hit), monitor "large_fa_timeout" sec, if timeout, large_fa_hit=0*/ + u8 forbidden_igi; + u32 recover_cnt; + + u8 dig_dynamic_min_0; + u8 dig_dynamic_min_1; + boolean is_media_connect_0; + boolean is_media_connect_1; + + u32 ant_div_rssi_max; + u32 RSSI_max; + + u8 *is_p2p_in_process; + + u8 pause_dig_level; + u8 pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1]; + + enum dig_goupcheck_level dig_go_up_check_level; + u8 aaa_default; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - BOOLEAN bTpTarget; - BOOLEAN bNoiseEst; - u4Byte TpTrainTH_min; - u1Byte IGIOffset_A; - u1Byte IGIOffset_B; + boolean is_tp_target; + boolean is_noise_est; + u32 tp_train_th_min; + u8 igi_offset_a; + u8 igi_offset_b; #endif #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - u1Byte rfGainIdx; - u1Byte agcTableIdx; - u1Byte bigJumpLmt[16]; - u1Byte enableAdjustBigJump:1; - u1Byte bigJumpStep1:3; - u1Byte bigJumpStep2:2; - u1Byte bigJumpStep3:2; + u8 rf_gain_idx; + u8 agc_table_idx; + u8 big_jump_lmt[16]; + u8 enable_adjust_big_jump:1; + u8 big_jump_step1:3; + u8 big_jump_step2:2; + u8 big_jump_step3:2; #endif -}DIG_T,*pDIG_T; - -typedef struct _FALSE_ALARM_STATISTICS{ - u4Byte Cnt_Parity_Fail; - u4Byte Cnt_Rate_Illegal; - u4Byte Cnt_Crc8_fail; - u4Byte Cnt_Mcs_fail; - u4Byte Cnt_Ofdm_fail; - u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A - u4Byte Cnt_Cck_fail; - u4Byte Cnt_all; - u4Byte Cnt_all_pre; - u4Byte Cnt_Fast_Fsync; - u4Byte Cnt_SB_Search_fail; - u4Byte Cnt_OFDM_CCA; - u4Byte Cnt_CCK_CCA; - u4Byte Cnt_CCA_all; - u4Byte Cnt_BW_USC; //Gary - u4Byte Cnt_BW_LSC; //Gary - u4Byte cnt_cck_crc32_error; - u4Byte cnt_cck_crc32_ok; - u4Byte cnt_ofdm_crc32_error; - u4Byte cnt_ofdm_crc32_ok; - u4Byte cnt_ht_crc32_error; - u4Byte cnt_ht_crc32_ok; - u4Byte cnt_vht_crc32_error; - u4Byte cnt_vht_crc32_ok; - u4Byte cnt_crc32_error_all; - u4Byte cnt_crc32_ok_all; - BOOLEAN cck_block_enable; - BOOLEAN ofdm_block_enable; - u4Byte dbg_port0; - BOOLEAN edcca_flag; -}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; - -typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition -{ + +#if (DIG_HW == 1) + u8 pre_rssi_min; +#endif +}; + +struct _FALSE_ALARM_STATISTICS { + u32 cnt_parity_fail; + u32 cnt_rate_illegal; + u32 cnt_crc8_fail; + u32 cnt_mcs_fail; + u32 cnt_ofdm_fail; + u32 cnt_ofdm_fail_pre; /* For RTL8881A */ + u32 cnt_cck_fail; + u32 cnt_all; + u32 cnt_all_pre; + u32 cnt_fast_fsync; + u32 cnt_sb_search_fail; + u32 cnt_ofdm_cca; + u32 cnt_cck_cca; + u32 cnt_cca_all; + u32 cnt_bw_usc; /* Gary */ + u32 cnt_bw_lsc; /* Gary */ + u32 cnt_cck_crc32_error; + u32 cnt_cck_crc32_ok; + u32 cnt_ofdm_crc32_error; + u32 cnt_ofdm_crc32_ok; + u32 cnt_ht_crc32_error; + u32 cnt_ht_crc32_ok; + u32 cnt_ht_crc32_error_agg; + u32 cnt_ht_crc32_ok_agg; + u32 cnt_vht_crc32_error; + u32 cnt_vht_crc32_ok; + u32 cnt_crc32_error_all; + u32 cnt_crc32_ok_all; + boolean cck_block_enable; + boolean ofdm_block_enable; + u32 dbg_port0; + boolean edcca_flag; +}; + +enum dm_dig_op_e { DIG_TYPE_THRESH_HIGH = 0, DIG_TYPE_THRESH_LOW = 1, DIG_TYPE_BACKOFF = 2, DIG_TYPE_RX_GAIN_MIN = 3, DIG_TYPE_RX_GAIN_MAX = 4, - DIG_TYPE_ENABLE = 5, - DIG_TYPE_DISABLE = 6, + DIG_TYPE_ENABLE = 5, + DIG_TYPE_DISABLE = 6, DIG_OP_TYPE_MAX -}DM_DIG_OP_E; +}; /* -typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition +enum dm_cck_pdth_e { CCK_PD_STAGE_LowRssi = 0, CCK_PD_STAGE_HighRssi = 1, CCK_PD_STAGE_MAX = 3, -}DM_CCK_PDTH_E; +}; -typedef enum tag_DIG_EXT_PORT_ALGO_Definition +enum dm_dig_ext_port_alg_e { DIG_EXT_PORT_STAGE_0 = 0, DIG_EXT_PORT_STAGE_1 = 1, DIG_EXT_PORT_STAGE_2 = 2, DIG_EXT_PORT_STAGE_3 = 3, DIG_EXT_PORT_STAGE_MAX = 4, -}DM_DIG_EXT_PORT_ALG_E; +}; -typedef enum tag_DIG_Connect_Definition +enum dm_dig_connect_e { - DIG_STA_DISCONNECT = 0, + DIG_STA_DISCONNECT = 0, DIG_STA_CONNECT = 1, DIG_STA_BEFORE_CONNECT = 2, - DIG_MultiSTA_DISCONNECT = 3, - DIG_MultiSTA_CONNECT = 4, + dig_multi_sta_disconnect = 3, + dig_multi_sta_connect = 4, DIG_CONNECT_MAX -}DM_DIG_CONNECT_E; +}; -#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} +#define DM_MultiSTA_InitGainChangeNotify(Event) {dm_dig_table.cur_multi_sta_connect_state = Event;} #define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \ - DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT) + DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_connect) #define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \ - DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT) + DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_disconnect) */ -typedef enum tag_PHYDM_Pause_Type { - PHYDM_PAUSE = BIT0, - PHYDM_RESUME = BIT1 -} PHYDM_PAUSE_TYPE; +enum phydm_pause_type { + PHYDM_PAUSE = BIT(0), + PHYDM_RESUME = BIT(1) +}; -typedef enum tag_PHYDM_Pause_Level { -/* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */ +enum phydm_pause_level { + /* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */ PHYDM_PAUSE_LEVEL_0 = 0, PHYDM_PAUSE_LEVEL_1 = 1, PHYDM_PAUSE_LEVEL_2 = 2, @@ -211,7 +214,15 @@ typedef enum tag_PHYDM_Pause_Level { PHYDM_PAUSE_LEVEL_5 = 5, PHYDM_PAUSE_LEVEL_6 = 6, PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */ -} PHYDM_PAUSE_LEVEL; +}; + +/*CCK PD*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #if (RTL8197F_SUPPORT == 1) + #define AAA_BASE p_dm_odm->priv->pshare->rf_ft_var.dbg_aaa_base /*4*/ + #define AAA_STEP p_dm_odm->priv->pshare->rf_ft_var.dbg_aaa_step /*2*/ + #endif +#endif #define DM_DIG_THRESH_HIGH 40 #define DM_DIG_THRESH_LOW 35 @@ -223,9 +234,14 @@ typedef enum tag_PHYDM_Pause_Level { #define DM_DIG_MIN_NIC 0x20 #define DM_DIG_MAX_OF_MIN_NIC 0x3e +#if (DIG_HW == 1) +#define DM_DIG_MAX_AP p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_upper /* 0x3e */ +#define DM_DIG_MIN_AP ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) ? 0x1c : 0x20)/* 0x1c */ +#else #define DM_DIG_MAX_AP 0x3e #define DM_DIG_MIN_AP 0x20 -#define DM_DIG_MAX_OF_MIN 0x2A //0x32 +#endif +#define DM_DIG_MAX_OF_MIN 0x2A /* 0x32 */ #define DM_DIG_MIN_AP_DFS 0x20 #define DM_DIG_MAX_NIC_HP 0x46 @@ -235,30 +251,34 @@ typedef enum tag_PHYDM_Pause_Level { #define DM_DIG_MIN_AP_HP 0x30 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#define DM_DIG_MAX_AP_COVERAGR 0x26 -#define DM_DIG_MIN_AP_COVERAGE 0x1c -#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22 + #define DM_DIG_MAX_AP_COVERAGR 0x26 +#if (DIG_HW == 1) + #define DM_DIG_MIN_AP_COVERAGE ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) ? 0x1c : 0x20) +#else + #define DM_DIG_MIN_AP_COVERAGE 0x1c +#endif + #define DM_DIG_MAX_OF_MIN_COVERAGE 0x22 -#define DM_DIG_TP_Target_TH0 500 -#define DM_DIG_TP_Target_TH1 1000 -#define DM_DIG_TP_Training_Period 10 + #define dm_dig_tp_target_th0 500 + #define dm_dig_tp_target_th1 1000 + #define dm_dig_tp_training_period 10 #endif -//vivi 92c&92d has different definition, 20110504 -//this is for 92c +/* vivi 92c&92d has different definition, 20110504 + * this is for 92c */ #if (DM_ODM_SUPPORT_TYPE & ODM_CE) #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - #define DM_DIG_FA_TH0 0x80//0x20 + #define DM_DIG_FA_TH0 0x80/* 0x20 */ #else - #define DM_DIG_FA_TH0 0x200//0x20 + #define DM_DIG_FA_TH0 0x200/* 0x20 */ #endif #else - #define DM_DIG_FA_TH0 0x200//0x20 + #define DM_DIG_FA_TH0 0x200/* 0x20 */ #endif #define DM_DIG_FA_TH1 0x300 #define DM_DIG_FA_TH2 0x400 -//this is for 92d +/* this is for 92d */ #define DM_DIG_FA_TH0_92D 0x100 #define DM_DIG_FA_TH1_92D 0x400 #define DM_DIG_FA_TH2_92D 0x600 @@ -267,102 +287,102 @@ typedef enum tag_PHYDM_Pause_Level { #define DM_DIG_BACKOFF_MIN -4 #define DM_DIG_BACKOFF_DEFAULT 10 -#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps -#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps -#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps -#define RSSI_OFFSET_DIG 0x05 +#define DM_DIG_FA_TH0_LPS 4 /* -> 4 in lps */ +#define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */ +#define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */ +#define RSSI_OFFSET_DIG 0x05 #define LARGE_FA_TIMEOUT 60 -VOID -ODM_ChangeDynamicInitGainThresh( - IN PVOID pDM_VOID, - IN u4Byte DM_Type, - IN u4Byte DM_Value - ); - -VOID -ODM_Write_DIG( - IN PVOID pDM_VOID, - IN u1Byte CurrentIGI - ); - -VOID -odm_PauseDIG( - IN PVOID pDM_VOID, - IN PHYDM_PAUSE_TYPE PauseType, - IN PHYDM_PAUSE_LEVEL pause_level, - IN u1Byte IGIValue - ); - -VOID -odm_DIGInit( - IN PVOID pDM_VOID - ); - -VOID +void +odm_change_dynamic_init_gain_thresh( + void *p_dm_void, + u32 dm_type, + u32 dm_value +); + +void +odm_write_dig( + void *p_dm_void, + u8 current_igi +); + +void +odm_pause_dig( + void *p_dm_void, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_level, + u8 igi_value +); + +void +odm_dig_init( + void *p_dm_void +); + +void odm_DIG( - IN PVOID pDM_VOID - ); - -VOID -odm_DIGbyRSSI_LPS( - IN PVOID pDM_VOID - ); - -VOID -odm_FalseAlarmCounterStatistics( - IN PVOID pDM_VOID - ); - -VOID -odm_PauseCCKPacketDetection( - IN PVOID pDM_VOID, - IN PHYDM_PAUSE_TYPE PauseType, - IN PHYDM_PAUSE_LEVEL pause_level, - IN u1Byte CCKPDThreshold - ); - -VOID -odm_CCKPacketDetectionThresh( - IN PVOID pDM_VOID - ); - -VOID -ODM_Write_CCK_CCA_Thres( - IN PVOID pDM_VOID, - IN u1Byte CurCCK_CCAThres - ); - -BOOLEAN -phydm_DIG_GoUpCheck( - IN PVOID pDM_VOID - ); + void *p_dm_void +); + +void +odm_dig_by_rssi_lps( + void *p_dm_void +); + +void +odm_false_alarm_counter_statistics( + void *p_dm_void +); + +void +odm_pause_cck_packet_detection( + void *p_dm_void, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_level, + u8 cck_pd_threshold +); + +void +odm_cck_packet_detection_thresh( + void *p_dm_void +); + +void +odm_write_cck_cca_thres( + void *p_dm_void, + u8 cur_cck_cca_thres +); + +boolean +phydm_dig_go_up_check( + void *p_dm_void +); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -odm_MPT_DIGCallback( - PRT_TIMER pTimer +void +odm_mpt_dig_callback( + struct timer_list *p_timer ); -VOID -odm_MPT_DIGWorkItemCallback( - IN PVOID pContext - ); +void +odm_mpt_dig_work_item_callback( + void *p_context +); #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -VOID -odm_MPT_DIGCallback( - IN PVOID pDM_VOID +void +odm_mpt_dig_callback( + void *p_dm_void ); #endif #if (DM_ODM_SUPPORT_TYPE != ODM_CE) -VOID +void ODM_MPT_DIG( - IN PVOID pDM_VOID + void *p_dm_void ); #endif diff --git a/hal/phydm/phydm_dynamicbbpowersaving.c b/hal/phydm/phydm_dynamicbbpowersaving.c index 79da6d9..fc2ec27 100644 --- a/hal/phydm/phydm_dynamicbbpowersaving.c +++ b/hal/phydm/phydm_dynamicbbpowersaving.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,111 +11,96 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" -VOID -odm_DynamicBBPowerSavingInit( - IN PVOID pDM_VOID - ) +#if (defined(CONFIG_BB_POWER_SAVING)) + +void +odm_dynamic_bb_power_saving_init( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_power_saving *p_dm_ps_table = &p_dm_odm->dm_ps_table; - pDM_PSTable->PreCCAState = CCA_MAX; - pDM_PSTable->CurCCAState = CCA_MAX; - pDM_PSTable->PreRFState = RF_MAX; - pDM_PSTable->CurRFState = RF_MAX; - pDM_PSTable->Rssi_val_min = 0; - pDM_PSTable->initialize = 0; + p_dm_ps_table->pre_cca_state = CCA_MAX; + p_dm_ps_table->cur_cca_state = CCA_MAX; + p_dm_ps_table->pre_rf_state = RF_MAX; + p_dm_ps_table->cur_rf_state = RF_MAX; + p_dm_ps_table->rssi_val_min = 0; + p_dm_ps_table->initialize = 0; } void -ODM_RF_Saving( - IN PVOID pDM_VOID, - IN u1Byte bForceInNormal - ) +odm_rf_saving( + void *p_dm_void, + u8 is_force_in_normal +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (DM_ODM_SUPPORT_TYPE != ODM_AP) - pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; - u1Byte Rssi_Up_bound = 30 ; - u1Byte Rssi_Low_bound = 25; + struct _dynamic_power_saving *p_dm_ps_table = &p_dm_odm->dm_ps_table; + u8 rssi_up_bound = 30 ; + u8 rssi_low_bound = 25; #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV - { - Rssi_Up_bound = 50 ; - Rssi_Low_bound = 45; + if (p_dm_odm->patch_id == 40) { /* RT_CID_819x_FUNAI_TV */ + rssi_up_bound = 50 ; + rssi_low_bound = 45; } #endif - if(pDM_PSTable->initialize == 0){ - - pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14; - pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3; - pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24; - pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12; - //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); - pDM_PSTable->initialize = 1; + if (p_dm_ps_table->initialize == 0) { + + p_dm_ps_table->reg874 = (odm_get_bb_reg(p_dm_odm, 0x874, MASKDWORD) & 0x1CC000) >> 14; + p_dm_ps_table->regc70 = (odm_get_bb_reg(p_dm_odm, 0xc70, MASKDWORD) & BIT(3)) >> 3; + p_dm_ps_table->reg85c = (odm_get_bb_reg(p_dm_odm, 0x85c, MASKDWORD) & 0xFF000000) >> 24; + p_dm_ps_table->rega74 = (odm_get_bb_reg(p_dm_odm, 0xa74, MASKDWORD) & 0xF000) >> 12; + /* Reg818 = phy_query_bb_reg(p_adapter, 0x818, MASKDWORD); */ + p_dm_ps_table->initialize = 1; } - if(!bForceInNormal) - { - if(pDM_Odm->RSSI_Min != 0xFF) - { - if(pDM_PSTable->PreRFState == RF_Normal) - { - if(pDM_Odm->RSSI_Min >= Rssi_Up_bound) - pDM_PSTable->CurRFState = RF_Save; + if (!is_force_in_normal) { + if (p_dm_odm->rssi_min != 0xFF) { + if (p_dm_ps_table->pre_rf_state == rf_normal) { + if (p_dm_odm->rssi_min >= rssi_up_bound) + p_dm_ps_table->cur_rf_state = rf_save; else - pDM_PSTable->CurRFState = RF_Normal; - } - else{ - if(pDM_Odm->RSSI_Min <= Rssi_Low_bound) - pDM_PSTable->CurRFState = RF_Normal; + p_dm_ps_table->cur_rf_state = rf_normal; + } else { + if (p_dm_odm->rssi_min <= rssi_low_bound) + p_dm_ps_table->cur_rf_state = rf_normal; else - pDM_PSTable->CurRFState = RF_Save; + p_dm_ps_table->cur_rf_state = rf_save; } + } else + p_dm_ps_table->cur_rf_state = RF_MAX; + } else + p_dm_ps_table->cur_rf_state = rf_normal; + + if (p_dm_ps_table->pre_rf_state != p_dm_ps_table->cur_rf_state) { + if (p_dm_ps_table->cur_rf_state == rf_save) { + odm_set_bb_reg(p_dm_odm, 0x874, 0x1C0000, 0x2); /* reg874[20:18]=3'b010 */ + odm_set_bb_reg(p_dm_odm, 0xc70, BIT(3), 0); /* regc70[3]=1'b0 */ + odm_set_bb_reg(p_dm_odm, 0x85c, 0xFF000000, 0x63); /* reg85c[31:24]=0x63 */ + odm_set_bb_reg(p_dm_odm, 0x874, 0xC000, 0x2); /* reg874[15:14]=2'b10 */ + odm_set_bb_reg(p_dm_odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ + odm_set_bb_reg(p_dm_odm, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */ + odm_set_bb_reg(p_dm_odm, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */ + } else { + odm_set_bb_reg(p_dm_odm, 0x874, 0x1CC000, p_dm_ps_table->reg874); + odm_set_bb_reg(p_dm_odm, 0xc70, BIT(3), p_dm_ps_table->regc70); + odm_set_bb_reg(p_dm_odm, 0x85c, 0xFF000000, p_dm_ps_table->reg85c); + odm_set_bb_reg(p_dm_odm, 0xa74, 0xF000, p_dm_ps_table->rega74); + odm_set_bb_reg(p_dm_odm, 0x818, BIT(28), 0x0); } - else - pDM_PSTable->CurRFState=RF_MAX; - } - else - { - pDM_PSTable->CurRFState = RF_Normal; - } - - if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) - { - if(pDM_PSTable->CurRFState == RF_Save) - { - ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); //Reg874[20:18]=3'b010 - ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0 - ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63 - ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10 - ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3 - ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0 - ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1 - } - else - { - ODM_SetBBReg(pDM_Odm, 0x874 , 0x1CC000, pDM_PSTable->Reg874); - ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70); - ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); - ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74); - ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0); - } - pDM_PSTable->PreRFState =pDM_PSTable->CurRFState; + p_dm_ps_table->pre_rf_state = p_dm_ps_table->cur_rf_state; } -#endif +#endif } +#endif diff --git a/hal/phydm/phydm_dynamicbbpowersaving.h b/hal/phydm/phydm_dynamicbbpowersaving.h index ce13e2e..0c4a236 100644 --- a/hal/phydm/phydm_dynamicbbpowersaving.h +++ b/hal/phydm/phydm_dynamicbbpowersaving.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,43 +11,42 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - + *****************************************************************************/ + #ifndef __PHYDMDYNAMICBBPOWERSAVING_H__ #define __PHYDMDYNAMICBBPOWERSAVING_H__ #define DYNAMIC_BBPWRSAV_VERSION "1.1" -typedef struct _Dynamic_Power_Saving_ -{ - u1Byte PreCCAState; - u1Byte CurCCAState; +#if (defined(CONFIG_BB_POWER_SAVING)) + +struct _dynamic_power_saving { + u8 pre_cca_state; + u8 cur_cca_state; - u1Byte PreRFState; - u1Byte CurRFState; + u8 pre_rf_state; + u8 cur_rf_state; - int Rssi_val_min; - - u1Byte initialize; - u4Byte Reg874,RegC70,Reg85C,RegA74; - -}PS_T,*pPS_T; + int rssi_val_min; -#define dm_RF_Saving ODM_RF_Saving + u8 initialize; + u32 reg874, regc70, reg85c, rega74; -void ODM_RF_Saving( - IN PVOID pDM_VOID, - IN u1Byte bForceInNormal +}; + +#define dm_rf_saving odm_rf_saving + +void odm_rf_saving( + void *p_dm_void, + u8 is_force_in_normal ); -VOID -odm_DynamicBBPowerSavingInit( - IN PVOID pDM_VOID - ); +void +odm_dynamic_bb_power_saving_init( + void *p_dm_void +); +#else +#define dm_rf_saving(p_dm_void, is_force_in_normal) +#endif #endif diff --git a/hal/phydm/phydm_dynamictxpower.c b/hal/phydm/phydm_dynamictxpower.c index 44899bd..3474fa6 100644 --- a/hal/phydm/phydm_dynamictxpower.c +++ b/hal/phydm/phydm_dynamictxpower.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,181 +11,174 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" -VOID -odm_DynamicTxPowerInit( - IN PVOID pDM_VOID - ) +void +odm_dynamic_tx_power_init( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct _ADAPTER *adapter = p_dm_odm->adapter; + PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - /*if (!IS_HARDWARE_TYPE_8814A(Adapter)) {*/ - /* ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, */ - /* ("odm_DynamicTxPowerInit DynamicTxPowerEnable=%d\n", pMgntInfo->bDynamicTxPowerEnable));*/ + /*if (!IS_HARDWARE_TYPE_8814A(adapter)) {*/ + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, */ + /* ("odm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->is_dynamic_tx_power_enable));*/ /* return;*/ /*} else*/ { - pMgntInfo->bDynamicTxPowerEnable = TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, - ("odm_DynamicTxPowerInit DynamicTxPowerEnable=%d\n", pMgntInfo->bDynamicTxPowerEnable)); + p_mgnt_info->bDynamicTxPowerEnable = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, + ("odm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->bDynamicTxPowerEnable)); } - - #if DEV_BUS_TYPE==RT_USB_INTERFACE - if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power) - { - odm_DynamicTxPowerSavePowerIndex(pDM_Odm); - pMgntInfo->bDynamicTxPowerEnable = TRUE; - } - else - #else - //so 92c pci do not need dynamic tx power? vivi check it later - pMgntInfo->bDynamicTxPowerEnable = FALSE; - #endif - - - pHalData->LastDTPLvl = TxHighPwrLevel_Normal; - pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; - + +#if DEV_BUS_TYPE == RT_USB_INTERFACE + if (RT_GetInterfaceSelection(adapter) == INTF_SEL1_USB_High_Power) { + odm_dynamic_tx_power_save_power_index(p_dm_odm); + p_mgnt_info->bDynamicTxPowerEnable = true; + } else +#else + /* so 92c pci do not need dynamic tx power? vivi check it later */ + p_mgnt_info->bDynamicTxPowerEnable = false; +#endif + + + p_hal_data->LastDTPLvl = tx_high_pwr_level_normal; + p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - pDM_Odm->LastDTPLvl = TxHighPwrLevel_Normal; - pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; - pDM_Odm->tx_agc_ofdm_18_6 = ODM_GetBBReg(pDM_Odm, 0xC24, bMaskDWord); /*TXAGC {18M 12M 9M 6M}*/ + p_dm_odm->last_dtp_lvl = tx_high_pwr_level_normal; + p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal; + p_dm_odm->tx_agc_ofdm_18_6 = odm_get_bb_reg(p_dm_odm, 0xC24, MASKDWORD); /*TXAGC {18M 12M 9M 6M}*/ #endif - + } -VOID -odm_DynamicTxPowerSavePowerIndex( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - u1Byte index; - u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - for(index = 0; index< 6; index++) - pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]); - - +void +odm_dynamic_tx_power_save_power_index( + void *p_dm_void +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 index; + u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + for (index = 0; index < 6; index++) + p_hal_data->PowerIndex_backup[index] = PlatformEFIORead1Byte(adapter, power_index_reg[index]); + + #endif #endif } -VOID -odm_DynamicTxPowerRestorePowerIndex( - IN PVOID pDM_VOID - ) +void +odm_dynamic_tx_power_restore_power_index( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - u1Byte index; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - for(index = 0; index< 6; index++) - PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 index; + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; + + for (index = 0; index < 6; index++) + PlatformEFIOWrite1Byte(adapter, power_index_reg[index], p_hal_data->PowerIndex_backup[index]); + -#endif #endif } -VOID -odm_DynamicTxPowerWritePowerIndex( - IN PVOID pDM_VOID, - IN u1Byte Value) +void +odm_dynamic_tx_power_write_power_index( + void *p_dm_void, + u8 value) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte index; - u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; - - for(index = 0; index< 6; index++) - //PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value); - ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 index; + u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; + + for (index = 0; index < 6; index++) + /* platform_efio_write_1byte(adapter, power_index_reg[index], value); */ + odm_write_1byte(p_dm_odm, power_index_reg[index], value); } -VOID -odm_DynamicTxPowerNIC_CE( - IN PVOID pDM_VOID - ) +void +odm_dynamic_tx_power_nic_ce( + void *p_dm_void +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) #if (RTL8821A_SUPPORT == 1) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte val; - u1Byte rssi_tmp = pDM_Odm->RSSI_Min; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 val; + u8 rssi_tmp = p_dm_odm->rssi_min; - if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) + if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR)) return; if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { - pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; + p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level2; /**/ } else if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL1) { - pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level1; /**/ - } else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) { - pDM_Odm->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + } else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { + p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal; /**/ } - if (pDM_Odm->LastDTPLvl != pDM_Odm->DynamicTxHighPowerLvl) { + if (p_dm_odm->last_dtp_lvl != p_dm_odm->dynamic_tx_high_power_lvl) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("update_DTP_lv: ((%d)) -> ((%d))\n", pDM_Odm->LastDTPLvl, pDM_Odm->DynamicTxHighPowerLvl)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("update_DTP_lv: ((%d)) -> ((%d))\n", p_dm_odm->last_dtp_lvl, p_dm_odm->dynamic_tx_high_power_lvl)); - pDM_Odm->LastDTPLvl = pDM_Odm->DynamicTxHighPowerLvl; + p_dm_odm->last_dtp_lvl = p_dm_odm->dynamic_tx_high_power_lvl; - if (pDM_Odm->SupportICType & (ODM_RTL8821)) { + if (p_dm_odm->support_ic_type & (ODM_RTL8821)) { - if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) { + if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level2) { - ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 1); /* Resp TXAGC offset = -3dB*/ + odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/ - val = pDM_Odm->tx_agc_ofdm_18_6 & 0xff; + val = p_dm_odm->tx_agc_ofdm_18_6 & 0xff; if (val >= 0x20) val -= 0x16; - ODM_SetBBReg(pDM_Odm, 0xC24, 0xff, val); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 2\n")); - } else if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { + odm_set_bb_reg(p_dm_odm, 0xC24, 0xff, val); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 2\n")); + } else if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level1) { - ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 1); /* Resp TXAGC offset = -3dB*/ + odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/ - val = pDM_Odm->tx_agc_ofdm_18_6 & 0xff; + val = p_dm_odm->tx_agc_ofdm_18_6 & 0xff; if (val >= 0x20) val -= 0x10; - ODM_SetBBReg(pDM_Odm, 0xC24, 0xff, val); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 1\n")); - } else if (pDM_Odm->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) { - - ODM_SetMACReg(pDM_Odm, 0x6D8, BIT20|BIT19|BIT18, 0); /* Resp TXAGC offset = 0dB*/ - ODM_SetBBReg(pDM_Odm, 0xC24, bMaskDWord, pDM_Odm->tx_agc_ofdm_18_6); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: normal\n")); + odm_set_bb_reg(p_dm_odm, 0xC24, 0xff, val); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 1\n")); + } else if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_normal) { + + odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 0); /* Resp TXAGC offset = 0dB*/ + odm_set_bb_reg(p_dm_odm, 0xC24, MASKDWORD, p_dm_odm->tx_agc_ofdm_18_6); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: normal\n")); } } } @@ -195,93 +188,92 @@ odm_DynamicTxPowerNIC_CE( } -VOID -odm_DynamicTxPower( - IN PVOID pDM_VOID - ) +void +odm_dynamic_tx_power( + void *p_dm_void +) { - // - // For AP/ADSL use prtl8192cd_priv - // For CE/NIC use PADAPTER - // - //PADAPTER pAdapter = pDM_Odm->Adapter; -// prtl8192cd_priv priv = pDM_Odm->priv; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) + /* */ + /* For AP/ADSL use struct rtl8192cd_priv* */ + /* For CE/NIC use struct _ADAPTER* */ + /* */ + /* struct _ADAPTER* p_adapter = p_dm_odm->adapter; + * struct rtl8192cd_priv* priv = p_dm_odm->priv; */ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR)) return; - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // - switch (pDM_Odm->SupportPlatform) - { - case ODM_WIN: - odm_DynamicTxPowerNIC(pDM_Odm); - break; - case ODM_CE: - odm_DynamicTxPowerNIC_CE(pDM_Odm); - break; - case ODM_AP: - odm_DynamicTxPowerAP(pDM_Odm); - break; - default: - break; + /* */ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ + /* */ + switch (p_dm_odm->support_platform) { + case ODM_WIN: + odm_dynamic_tx_power_nic(p_dm_odm); + break; + case ODM_CE: + odm_dynamic_tx_power_nic_ce(p_dm_odm); + break; + case ODM_AP: + odm_dynamic_tx_power_ap(p_dm_odm); + break; + default: + break; } - + } -VOID -odm_DynamicTxPowerNIC( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) +void +odm_dynamic_tx_power_nic( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR)) return; - + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (pDM_Odm->SupportICType == ODM_RTL8814A) { - odm_DynamicTxPower_8814A(pDM_Odm); - } else if (pDM_Odm->SupportICType & ODM_RTL8821) { - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter); - - if (pMgntInfo->RegRspPwr == 1) { - if (pDM_Odm->RSSI_Min > 60) - ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 1); /*Resp TXAGC offset = -3dB*/ - else if (pDM_Odm->RSSI_Min < 55) - ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 0); /*Resp TXAGC offset = 0dB*/ + if (p_dm_odm->support_ic_type == ODM_RTL8814A) + odm_dynamic_tx_power_8814a(p_dm_odm); + else if (p_dm_odm->support_ic_type & ODM_RTL8821) { + struct _ADAPTER *adapter = p_dm_odm->adapter; + PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(adapter); + + if (p_mgnt_info->RegRspPwr == 1) { + if (p_dm_odm->rssi_min > 60) + odm_set_mac_reg(p_dm_odm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 1); /*Resp TXAGC offset = -3dB*/ + else if (p_dm_odm->rssi_min < 55) + odm_set_mac_reg(p_dm_odm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 0); /*Resp TXAGC offset = 0dB*/ } } -#endif +#endif } -VOID -odm_DynamicTxPowerAP( - IN PVOID pDM_VOID +void +odm_dynamic_tx_power_ap( + void *p_dm_void - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +) +{ #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -//#if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1)) + /* #if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1)) */ - prtl8192cd_priv priv = pDM_Odm->priv; - s4Byte i; - s2Byte pwr_thd = 63; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + s32 i; + s16 pwr_thd = 63; - if(!priv->pshare->rf_ft_var.tx_pwr_ctrl) + if (!priv->pshare->rf_ft_var.tx_pwr_ctrl) return; - -#if ((RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1)) - if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A)) + +#if ((RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) + if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8822B)) pwr_thd = TX_POWER_NEAR_FIELD_THRESH_LVL1; #endif @@ -289,93 +281,91 @@ odm_DynamicTxPowerAP( * Check if station is near by to use lower tx power */ - if ((priv->up_time % 3) == 0 ) { - int disable_pwr_ctrl = ((pDM_Odm->FalseAlmCnt.Cnt_all > 1000 ) || ((pDM_Odm->FalseAlmCnt.Cnt_all > 300 ) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0; - - for(i=0; ipODM_StaInfo[i]; - if(IS_STA_VALID(pstat) ) { - if(disable_pwr_ctrl) - pstat->hp_level = 0; - else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd)) + if ((priv->up_time % 3) == 0) { + int disable_pwr_ctrl = ((p_dm_odm->false_alm_cnt.cnt_all > 1000) || ((p_dm_odm->false_alm_cnt.cnt_all > 300) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + struct sta_info *pstat = p_dm_odm->p_odm_sta_info[i]; + if (IS_STA_VALID(pstat)) { + if (disable_pwr_ctrl) + pstat->hp_level = 0; + else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd)) pstat->hp_level = 1; - else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd-8))) + else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd - 8))) pstat->hp_level = 0; } } #if defined(CONFIG_WLAN_HAL_8192EE) if (GET_CHIP_VER(priv) == VERSION_8192E) { - if( !disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff) ) { - if(pDM_Odm->RSSI_Min > pwr_thd) - RRSR_power_control_11n(priv, 1 ); - else if(pDM_Odm->RSSI_Min < (pwr_thd-8)) - RRSR_power_control_11n(priv, 0 ); - } else { - RRSR_power_control_11n(priv, 0 ); - } + if (!disable_pwr_ctrl && (p_dm_odm->rssi_min != 0xff)) { + if (p_dm_odm->rssi_min > pwr_thd) + RRSR_power_control_11n(priv, 1); + else if (p_dm_odm->rssi_min < (pwr_thd - 8)) + RRSR_power_control_11n(priv, 0); + } else + RRSR_power_control_11n(priv, 0); } -#endif +#endif #ifdef CONFIG_WLAN_HAL_8814AE if (GET_CHIP_VER(priv) == VERSION_8814A) { - if (!disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff)) { - if (pDM_Odm->RSSI_Min > pwr_thd) + if (!disable_pwr_ctrl && (p_dm_odm->rssi_min != 0xff)) { + if (p_dm_odm->rssi_min > pwr_thd) RRSR_power_control_14(priv, 1); - else if (pDM_Odm->RSSI_Min < (pwr_thd-8)) - RRSR_power_control_14(priv, 0); - } else { + else if (p_dm_odm->rssi_min < (pwr_thd - 8)) RRSR_power_control_14(priv, 0); - } + } else + RRSR_power_control_14(priv, 0); } -#endif +#endif } -//#endif + /* #endif */ -#endif +#endif } -VOID -odm_DynamicTxPower_8821( - IN PVOID pDM_VOID, - IN pu1Byte pDesc, - IN u1Byte macId - ) +void +odm_dynamic_tx_power_8821( + void *p_dm_void, + u8 *p_desc, + u8 mac_id +) { #if (RTL8821A_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PSTA_INFO_T pEntry; - u1Byte reg0xc56_byte; - u1Byte txpwr_offset = 0; - - pEntry = pDM_Odm->pODM_StaInfo[macId]; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct sta_info *p_entry; + u8 reg0xc56_byte; + u8 txpwr_offset = 0; + + p_entry = p_dm_odm->p_odm_sta_info[mac_id]; - reg0xc56_byte = ODM_Read1Byte(pDM_Odm, 0xc56); + reg0xc56_byte = odm_read_1byte(p_dm_odm, 0xc56); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("reg0xc56_byte=%d\n", reg0xc56_byte)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("reg0xc56_byte=%d\n", reg0xc56_byte)); - if (pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB > 85) { + if (p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb > 85) { /* Avoid TXAGC error after TX power offset is applied. For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB ) Total power = 6-11= -5( overflow!! ), PA may be burned ! so txpwr_offset should be adjusted by Reg0xc56*/ - + if (reg0xc56_byte < 7) txpwr_offset = 1; else if (reg0xc56_byte < 11) txpwr_offset = 2; else txpwr_offset = 3; - - SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset)); - } else{ - SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset)); + SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb, txpwr_offset)); + + } else { + SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb, txpwr_offset)); } #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ @@ -383,72 +373,72 @@ odm_DynamicTxPower_8821( } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -odm_DynamicTxPower_8814A( - IN PVOID pDM_VOID - ) +void +odm_dynamic_tx_power_8814a( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - s4Byte UndecoratedSmoothedPWDB; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, - ("TxLevel=%d pMgntInfo->IOTAction=%x pMgntInfo->bDynamicTxPowerEnable=%d\n", - pHalData->DynamicTxHighPowerLvl, pMgntInfo->IOTAction, pMgntInfo->bDynamicTxPowerEnable)); - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + s32 undecorated_smoothed_pwdb; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, + ("TxLevel=%d p_mgnt_info->iot_action=%x p_mgnt_info->is_dynamic_tx_power_enable=%d\n", + p_hal_data->DynamicTxHighPowerLvl, p_mgnt_info->IOTAction, p_mgnt_info->bDynamicTxPowerEnable)); + /*STA not connected and AP not connected*/ - if ((!pMgntInfo->bMediaConnect) && (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any reset power lvl\n")); - pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + if ((!p_mgnt_info->bMediaConnect) && (p_hal_data->EntryMinUndecoratedSmoothedPWDB == 0)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any reset power lvl\n")); + p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; return; } - if ((pMgntInfo->bDynamicTxPowerEnable != TRUE) || pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) { - pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; - } else { - if (pMgntInfo->bMediaConnect) { /*Default port*/ - if (ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter)) { - UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", UndecoratedSmoothedPWDB)); + if ((p_mgnt_info->bDynamicTxPowerEnable != true) || p_mgnt_info->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) + p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; + else { + if (p_mgnt_info->bMediaConnect) { /*Default port*/ + if (ACTING_AS_AP(adapter) || ACTING_AS_IBSS(adapter)) { + undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", undecorated_smoothed_pwdb)); } else { - UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB)); + undecorated_smoothed_pwdb = p_hal_data->UndecoratedSmoothedPWDB; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", undecorated_smoothed_pwdb)); } } else {/*associated entry pwdb*/ - UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB)); - } + undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", undecorated_smoothed_pwdb)); + } /*Should we separate as 2.4G/5G band?*/ - - if (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { - pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); - } else if ((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && - (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) { - pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); - } else if (UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) { - pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); + + if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { + p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level2; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_level1 (TxPwr=0x0)\n")); + } else if ((undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) && + (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) { + p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level1; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_level1 (TxPwr=0x10)\n")); + } else if (undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { + p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_normal\n")); } } - if (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8814A() Channel = %d\n" , pHalData->CurrentChannel)); - odm_SetTxPowerLevel8814(Adapter, pHalData->CurrentChannel, pHalData->DynamicTxHighPowerLvl); + if (p_hal_data->DynamicTxHighPowerLvl != p_hal_data->LastDTPLvl) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8814a() channel = %d\n", p_hal_data->CurrentChannel)); + odm_set_tx_power_level8814(adapter, p_hal_data->CurrentChannel, p_hal_data->DynamicTxHighPowerLvl); } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, - ("odm_DynamicTxPower_8814A() Channel = %d TXpower lvl=%d/%d\n" , - pHalData->CurrentChannel, pHalData->LastDTPLvl, pHalData->DynamicTxHighPowerLvl)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, + ("odm_dynamic_tx_power_8814a() channel = %d TXpower lvl=%d/%d\n", + p_hal_data->CurrentChannel, p_hal_data->LastDTPLvl, p_hal_data->DynamicTxHighPowerLvl)); - pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl; + p_hal_data->LastDTPLvl = p_hal_data->DynamicTxHighPowerLvl; } @@ -458,85 +448,83 @@ odm_DynamicTxPower_8814A( /*For normal driver we always use the FW method to configure TX power index to reduce I/O transaction.*/ /**/ /**/ -VOID -odm_SetTxPowerLevel8814( - IN PADAPTER Adapter, - IN u1Byte Channel, - IN u1Byte PwrLvl - ) +void +odm_set_tx_power_level8814( + struct _ADAPTER *adapter, + u8 channel, + u8 pwr_lvl +) { #if (DEV_BUS_TYPE == RT_USB_INTERFACE) - u4Byte i, j, k = 0; - u4Byte value[264] = {0}; - u4Byte path = 0, PowerIndex, txagc_table_wd = 0x00801000; - - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - u1Byte jaguar2Rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}, - {MGN_6M, MGN_9M, MGN_12M, MGN_18M}, - {MGN_24M, MGN_36M, MGN_48M, MGN_54M}, - {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3}, - {MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}, - {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11}, - {MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}, - {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19}, - {MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}, - {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3}, - {MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7}, - {MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1}, - {MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5}, - {MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9}, - {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3}, - {MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7}, - {MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0} }; - + u32 i, j, k = 0; + u32 value[264] = {0}; + u32 path = 0, power_index, txagc_table_wd = 0x00801000; + + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + + u8 jaguar2_rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}, + {MGN_6M, MGN_9M, MGN_12M, MGN_18M}, + {MGN_24M, MGN_36M, MGN_48M, MGN_54M}, + {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3}, + {MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}, + {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11}, + {MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}, + {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19}, + {MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}, + {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3}, + {MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7}, + {MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1}, + {MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5}, + {MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9}, + {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3}, + {MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7}, + {MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0} + }; + for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) { - - u1Byte usb_host = UsbModeQueryHubUsbType(Adapter); - u1Byte usb_rfset = UsbModeQueryRfSet(Adapter); - u1Byte usb_rf_type = RT_GetRFType(Adapter); - + + u8 usb_host = UsbModeQueryHubUsbType(adapter); + u8 usb_rfset = UsbModeQueryRfSet(adapter); + u8 usb_rf_type = RT_GetRFType(adapter); + for (i = 0; i <= 16; i++) { for (j = 0; j <= 3; j++) { - if (jaguar2Rates[i][j] == 0) + if (jaguar2_rates[i][j] == 0) continue; - + txagc_table_wd = 0x00801000; - PowerIndex = (u4Byte) PHY_GetTxPowerIndex(Adapter, (u1Byte)path, jaguar2Rates[i][j], pHalData->CurrentChannelBW, Channel); + power_index = (u32) PHY_GetTxPowerIndex(adapter, (u8)path, jaguar2_rates[i][j], p_hal_data->CurrentChannelBW, channel); /*for Query bus type to recude tx power.*/ - if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(Adapter) && usb_rf_type == RF_3T3R) { - if (Channel <= 14) { - if (PowerIndex >= 16) - PowerIndex -= 16; + if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(adapter) && usb_rf_type == RF_3T3R) { + if (channel <= 14) { + if (power_index >= 16) + power_index -= 16; else - PowerIndex = 0; + power_index = 0; } else - PowerIndex = 0; + power_index = 0; } - if (PwrLvl == TxHighPwrLevel_Level1) { - if (PowerIndex >= 0x10) - PowerIndex -= 0x10; + if (pwr_lvl == tx_high_pwr_level_level1) { + if (power_index >= 0x10) + power_index -= 0x10; else - PowerIndex = 0; - } else if (PwrLvl == TxHighPwrLevel_Level2) { - PowerIndex = 0; - } - - txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2Rates[i][j]) | (PowerIndex << 24); + power_index = 0; + } else if (pwr_lvl == tx_high_pwr_level_level2) + power_index = 0; - PHY_SetTxPowerIndexShadow(Adapter, (u1Byte)PowerIndex, (u1Byte)path, jaguar2Rates[i][j]); + txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2_rates[i][j]) | (power_index << 24); + + PHY_SetTxPowerIndexShadow(adapter, (u8)power_index, (u8)path, jaguar2_rates[i][j]); value[k++] = txagc_table_wd; } } } - if (Adapter->MgntInfo.bScanInProgress == FALSE && Adapter->MgntInfo.RegFWOffload == 2) - HalDownloadTxPowerLevel8814(Adapter, value); + if (adapter->MgntInfo.bScanInProgress == false && adapter->MgntInfo.RegFWOffload == 2) + HalDownloadTxPowerLevel8814(adapter, value); #endif } #endif - - diff --git a/hal/phydm/phydm_dynamictxpower.h b/hal/phydm/phydm_dynamictxpower.h index 0e47fc2..36b004c 100644 --- a/hal/phydm/phydm_dynamictxpower.h +++ b/hal/phydm/phydm_dynamictxpower.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,13 +11,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - + *****************************************************************************/ + #ifndef __PHYDMDYNAMICTXPOWER_H__ #define __PHYDMDYNAMICTXPOWER_H__ @@ -37,74 +32,74 @@ #define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 #endif -#define TxHighPwrLevel_Normal 0 -#define TxHighPwrLevel_Level1 1 -#define TxHighPwrLevel_Level2 2 - -#define TxHighPwrLevel_BT1 3 -#define TxHighPwrLevel_BT2 4 -#define TxHighPwrLevel_15 5 -#define TxHighPwrLevel_35 6 -#define TxHighPwrLevel_50 7 -#define TxHighPwrLevel_70 8 -#define TxHighPwrLevel_100 9 - -VOID -odm_DynamicTxPowerInit( - IN PVOID pDM_VOID - ); - -VOID -odm_DynamicTxPowerRestorePowerIndex( - IN PVOID pDM_VOID - ); - -VOID -odm_DynamicTxPowerNIC( - IN PVOID pDM_VOID - ); - -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -VOID -odm_DynamicTxPowerSavePowerIndex( - IN PVOID pDM_VOID - ); - -VOID -odm_DynamicTxPowerWritePowerIndex( - IN PVOID pDM_VOID, - IN u1Byte Value); - -VOID -odm_DynamicTxPower_8821( - IN PVOID pDM_VOID, - IN pu1Byte pDesc, - IN u1Byte macId - ); +#define tx_high_pwr_level_normal 0 +#define tx_high_pwr_level_level1 1 +#define tx_high_pwr_level_level2 2 + +#define tx_high_pwr_level_bt1 3 +#define tx_high_pwr_level_bt2 4 +#define tx_high_pwr_level_15 5 +#define tx_high_pwr_level_35 6 +#define tx_high_pwr_level_50 7 +#define tx_high_pwr_level_70 8 +#define tx_high_pwr_level_100 9 + +void +odm_dynamic_tx_power_init( + void *p_dm_void +); + +void +odm_dynamic_tx_power_restore_power_index( + void *p_dm_void +); + +void +odm_dynamic_tx_power_nic( + void *p_dm_void +); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +void +odm_dynamic_tx_power_save_power_index( + void *p_dm_void +); + +void +odm_dynamic_tx_power_write_power_index( + void *p_dm_void, + u8 value); + +void +odm_dynamic_tx_power_8821( + void *p_dm_void, + u8 *p_desc, + u8 mac_id +); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -odm_DynamicTxPower_8814A( - IN PVOID pDM_VOID - ); - - -VOID -odm_SetTxPowerLevel8814( - IN PADAPTER Adapter, - IN u1Byte Channel, - IN u1Byte PwrLvl - ); +void +odm_dynamic_tx_power_8814a( + void *p_dm_void +); + + +void +odm_set_tx_power_level8814( + struct _ADAPTER *adapter, + u8 channel, + u8 pwr_lvl +); #endif #endif -VOID -odm_DynamicTxPower( - IN PVOID pDM_VOID - ); +void +odm_dynamic_tx_power( + void *p_dm_void +); -VOID -odm_DynamicTxPowerAP( - IN PVOID pDM_VOID - ); +void +odm_dynamic_tx_power_ap( + void *p_dm_void +); #endif diff --git a/hal/phydm/phydm_features.h b/hal/phydm/phydm_features.h index ae384d3..325e7c1 100644 --- a/hal/phydm/phydm_features.h +++ b/hal/phydm/phydm_features.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,32 +11,74 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PHYDM_FEATURES_H__ #define __PHYDM_FEATURES +#define ODM_DC_CANCELLATION_SUPPORT (ODM_RTL8188F | ODM_RTL8710B) +#define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E) + +#if ((RTL8814A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + #define PHYDM_LA_MODE_SUPPORT 1 +#else + #define PHYDM_LA_MODE_SUPPORT 0 +#endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + #if (RTL8822B_SUPPORT == 1) + #define PHYDM_TXA_CALIBRATION 1 + #else + #define PHYDM_TXA_CALIBRATION 0 + #endif + + #if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) + #define PHYDM_PRIMARY_CCA 1 + #else + #define PHYDM_PRIMARY_CCA 0 + #endif + + + #if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822B_SUPPORT == 1) + #define PHYDM_DC_CANCELLATION 1 + #else + #define PHYDM_DC_CANCELLATION 0 + #endif + + #define CONFIG_PSD_TOOL 1 + /*phydm debyg report & tools*/ + #define CONFIG_PHYDM_DEBUG_FUNCTION 1 + /*Antenna Diversity*/ #define CONFIG_PHYDM_ANTENNA_DIVERSITY #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY - + #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) - #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY #endif - + #if (RTL8821A_SUPPORT == 1) - /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ - #define CONFIG_FAT_PATCH + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #define CONFIG_FAT_PATCH + #endif + + #if (RTL8822B_SUPPORT == 1) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ #endif + #endif - + + #if (RTL8822B_SUPPORT == 1) + #define CONFIG_DYNAMIC_RX_PATH 0 + #else + #define CONFIG_DYNAMIC_RX_PATH 0 + #endif + + #if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) + #define CONFIG_RECEIVER_BLOCKING + #endif + #define PHYDM_SUPPORT_CCKPD 1 #define RA_MASK_PHYDMLIZE_WIN 1 /*#define CONFIG_PATH_DIVERSITY*/ /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ @@ -44,25 +86,57 @@ /*#define CONFIG_RA_DBG_CMD*/ #define CONFIG_RA_FW_DBG_CODE 1 /*#define CONFIG_PHYDM_RX_SNIFFER_PARSING*/ + #define CONFIG_BB_POWER_SAVING + #define CONFIG_BB_TXBF_API #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #if (RTL8822B_SUPPORT == 1) + #define PHYDM_TXA_CALIBRATION 1 + #else + #define PHYDM_TXA_CALIBRATION 0 + #endif + + #if (RTL8188E_SUPPORT == 1) + #define PHYDM_PRIMARY_CCA 1 + #else + #define PHYDM_PRIMARY_CCA 0 + #endif + + #define CONFIG_PSD_TOOL 0 + /*phydm debyg report & tools*/ + #if defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION) + #define CONFIG_PHYDM_DEBUG_FUNCTION 0 + #else + #define CONFIG_PHYDM_DEBUG_FUNCTION 1 + #endif + + #if (RTL8822B_SUPPORT == 1) + #define CONFIG_DYNAMIC_RX_PATH 0 + #else + #define CONFIG_DYNAMIC_RX_PATH 0 + #endif + + #define PHYDM_SUPPORT_CCKPD 1 #define RA_MASK_PHYDMLIZE_AP 1 /* #define CONFIG_RA_DBG_CMD*/ #define CONFIG_RA_FW_DBG_CODE 0 - + /*#define CONFIG_PATH_DIVERSITY*/ /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ #define CONFIG_RA_DYNAMIC_RATE_ID - + /*#define CONFIG_BB_POWER_SAVING*/ + #define CONFIG_BB_TXBF_API + /* [ Configure Antenna Diversity ] */ #if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) - #define CONFIG_PHYDM_ANTENNA_DIVERSITY + #define CONFIG_PHYDM_ANTENNA_DIVERSITY #define ODM_EVM_ENHANCE_ANTDIV + #define SKIP_EVM_ANTDIV_TRAINING_PATCH 1 /*----------*/ - + #if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) #define CONFIG_NO_2G_DIVERSITY #endif @@ -78,49 +152,87 @@ #endif #if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) #define CONFIG_NO_5G_DIVERSITY - #endif - /*----------*/ + #endif + /*----------*/ #if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) - #define CONFIG_NOT_SUPPORT_ANTDIV + #define CONFIG_NOT_SUPPORT_ANTDIV #elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) #define CONFIG_2G_SUPPORT_ANTDIV #elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) #define CONFIG_5G_SUPPORT_ANTDIV #elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY)) - #define CONFIG_2G5G_SUPPORT_ANTDIV + #define CONFIG_2G5G_SUPPORT_ANTDIV #endif - /*----------*/ + /*----------*/ #endif #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #if (RTL8822B_SUPPORT == 1) + #define PHYDM_TXA_CALIBRATION 1 + #else + #define PHYDM_TXA_CALIBRATION 0 + #endif + + #if (RTL8192E_SUPPORT == 1) + #define PHYDM_PRIMARY_CCA 1 + #else + #define PHYDM_PRIMARY_CCA 0 + #endif + + #if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + #define PHYDM_DC_CANCELLATION 1 + #else + #define PHYDM_DC_CANCELLATION 0 + #endif + + #define CONFIG_PSD_TOOL 1 + /*phydm debyg report & tools*/ + #define CONFIG_PHYDM_DEBUG_FUNCTION 1 + + #if (RTL8822B_SUPPORT == 1) + #define CONFIG_DYNAMIC_RX_PATH 0 + #else + #define CONFIG_DYNAMIC_RX_PATH 0 + #endif + + #define PHYDM_SUPPORT_CCKPD 1 #define RA_MASK_PHYDMLIZE_CE 1 /*Antenna Diversity*/ #ifdef CONFIG_ANTENNA_DIVERSITY #define CONFIG_PHYDM_ANTENNA_DIVERSITY - + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY - + #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) - #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY #endif - + #if (RTL8821A_SUPPORT == 1) - /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT == 1) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ #endif #endif #endif - + #ifdef CONFIG_DFS_MASTER #define CONFIG_PHYDM_DFS_MASTER #endif + #if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) + #define CONFIG_RECEIVER_BLOCKING + #endif /*#define CONFIG_RA_DBG_CMD*/ #define CONFIG_RA_FW_DBG_CODE 0 /*#define CONFIG_ANT_DETECTION*/ /*#define CONFIG_PATH_DIVERSITY*/ /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + #define CONFIG_BB_POWER_SAVING + #define CONFIG_BB_TXBF_API #ifdef CONFIG_BT_COEXIST #define BT_SUPPORT 1 @@ -130,4 +242,10 @@ #endif + /*20170103 YuChen add for FW API*/ + #define PHYDM_FW_API_ENABLE_8822B 1 + #define PHYDM_FW_API_FUNC_ENABLE_8822B 1 + #define PHYDM_FW_API_ENABLE_8821C 1 + #define PHYDM_FW_API_FUNC_ENABLE_8821C 1 + #endif diff --git a/hal/phydm/phydm_hwconfig.c b/hal/phydm/phydm_hwconfig.c index adb3984..1aa3a94 100644 --- a/hal/phydm/phydm_hwconfig.c +++ b/hal/phydm/phydm_hwconfig.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,326 +11,416 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" -#define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig_MP_##ic##txt(pDM_Odm)) -#define READ_AND_CONFIG_TC(ic, txt) (ODM_ReadAndConfig_TC_##ic##txt(pDM_Odm)) +#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(p_dm_odm)) +#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(p_dm_odm)) #if (PHYDM_TESTCHIP_SUPPORT == 1) #define READ_AND_CONFIG(ic, txt) do {\ - if (pDM_Odm->bIsMPChip)\ - READ_AND_CONFIG_MP(ic,txt);\ - else\ - READ_AND_CONFIG_TC(ic,txt);\ - } while(0) + if (p_dm_odm->is_mp_chip)\ + READ_AND_CONFIG_MP(ic, txt);\ + else\ + READ_AND_CONFIG_TC(ic, txt);\ + } while (0) #else - #define READ_AND_CONFIG READ_AND_CONFIG_MP +#define READ_AND_CONFIG READ_AND_CONFIG_MP #endif -#define READ_FIRMWARE_MP(ic, txt) (ODM_ReadFirmware_MP_##ic##txt(pDM_Odm, pFirmware, pSize)) -#define READ_FIRMWARE_TC(ic, txt) (ODM_ReadFirmware_TC_##ic##txt(pDM_Odm, pFirmware, pSize)) +#define READ_FIRMWARE_MP(ic, txt) (odm_read_firmware_mp_##ic##txt(p_dm_odm, p_firmware, p_size)) +#define READ_FIRMWARE_TC(ic, txt) (odm_read_firmware_tc_##ic##txt(p_dm_odm, p_firmware, p_size)) #if (PHYDM_TESTCHIP_SUPPORT == 1) #define READ_FIRMWARE(ic, txt) do {\ - if (pDM_Odm->bIsMPChip)\ - READ_FIRMWARE_MP(ic,txt);\ - else\ - READ_FIRMWARE_TC(ic,txt);\ - } while(0) + if (p_dm_odm->is_mp_chip)\ + READ_FIRMWARE_MP(ic, txt);\ + else\ + READ_FIRMWARE_TC(ic, txt);\ + } while (0) #else #define READ_FIRMWARE READ_FIRMWARE_MP #endif - -#define GET_VERSION_MP(ic, txt) (ODM_GetVersion_MP_##ic##txt()) -#define GET_VERSION_TC(ic, txt) (ODM_GetVersion_TC_##ic##txt()) -#define GET_VERSION(ic, txt) (pDM_Odm->bIsMPChip?GET_VERSION_MP(ic,txt):GET_VERSION_TC(ic,txt)) -u1Byte -odm_QueryRxPwrPercentage( - IN s1Byte AntPower - ) +#define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt()) +#define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt()) + +#if (PHYDM_TESTCHIP_SUPPORT == 1) + #define GET_VERSION(ic, txt) (p_dm_odm->is_mp_chip ? GET_VERSION_MP(ic, txt) : GET_VERSION_TC(ic, txt)) +#else + #define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt) +#endif + +void +phydm_rx_statistic_cal( + struct PHY_DM_STRUCT *p_phydm, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo +) +{ +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + struct _phy_status_rpt_jaguar2_type1 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type1 *)p_phy_status; +#endif + u8 date_rate = (p_pktinfo->data_rate & 0x7f); + + if (date_rate <= ODM_RATE54M) { + + p_phydm->phy_dbg_info.num_qry_legacy_pkt[date_rate]++; + /**/ + } else if (date_rate <= ODM_RATEMCS31) { + + p_phydm->phy_dbg_info.num_qry_ht_pkt[date_rate - ODM_RATEMCS0]++; + p_phydm->phy_dbg_info.ht_pkt_not_zero = true; + + } + #if ODM_IC_11AC_SERIES_SUPPORT + else if (date_rate <= ODM_RATEVHTSS4MCS9) { + + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63) && (p_phydm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE)) { + + p_phydm->phy_dbg_info.num_qry_mu_vht_pkt[date_rate - ODM_RATEVHTSS1MCS0]++; + p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate | BIT(7); + p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid; + + } else + #endif + { + p_phydm->phy_dbg_info.num_qry_vht_pkt[date_rate - ODM_RATEVHTSS1MCS0]++; + p_phydm->phy_dbg_info.vht_pkt_not_zero = true; + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate; + p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid; + #endif + } + } + #endif +} + +void +phydm_reset_avg_rssi_for_ss( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + p_dm_odm->phy_dbg_info.rssi_cck_sum = 0; + p_dm_odm->phy_dbg_info.rssi_cck_cnt = 0; + + p_dm_odm->phy_dbg_info.rssi_ofdm_sum = 0; + p_dm_odm->phy_dbg_info.rssi_ofdm_cnt = 0; + + p_dm_odm->phy_dbg_info.rssi_1ss_sum = 0; + p_dm_odm->phy_dbg_info.rssi_1ss_cnt = 0; + + p_dm_odm->phy_dbg_info.rssi_2ss_sum[0] = 0; + p_dm_odm->phy_dbg_info.rssi_2ss_sum[1] = 0; + p_dm_odm->phy_dbg_info.rssi_2ss_cnt = 0; + + p_dm_odm->phy_dbg_info.rssi_3ss_sum[0] = 0; + p_dm_odm->phy_dbg_info.rssi_3ss_sum[1] = 0; + p_dm_odm->phy_dbg_info.rssi_3ss_sum[2] = 0; + p_dm_odm->phy_dbg_info.rssi_3ss_cnt = 0; + + p_dm_odm->phy_dbg_info.rssi_4ss_sum[0] = 0; + p_dm_odm->phy_dbg_info.rssi_4ss_sum[1] = 0; + p_dm_odm->phy_dbg_info.rssi_4ss_sum[2] = 0; + p_dm_odm->phy_dbg_info.rssi_4ss_sum[3] = 0; + p_dm_odm->phy_dbg_info.rssi_4ss_cnt = 0; + +} + +void +phydm_avg_rssi_for_ss( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + struct _odm_per_pkt_info_ *p_pktinfo +) { - if ((AntPower <= -100) || (AntPower >= 20)) + u8 rate_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); + + if (p_pktinfo->data_rate <= ODM_RATE11M) { + p_dm_odm->phy_dbg_info.rssi_cck_sum += p_phy_info->rx_mimo_signal_strength[0]; + p_dm_odm->phy_dbg_info.rssi_cck_cnt++; + } else if (p_pktinfo->data_rate <= ODM_RATE54M) { + p_dm_odm->phy_dbg_info.rssi_ofdm_sum += p_phy_info->rx_mimo_signal_strength[0]; + p_dm_odm->phy_dbg_info.rssi_ofdm_cnt++; + } else if (rate_ss == 1) { + p_dm_odm->phy_dbg_info.rssi_1ss_sum += p_phy_info->rx_mimo_signal_strength[0]; + p_dm_odm->phy_dbg_info.rssi_1ss_cnt++; + } else if (rate_ss == 2) { + p_dm_odm->phy_dbg_info.rssi_2ss_sum[0] += p_phy_info->rx_mimo_signal_strength[0]; + p_dm_odm->phy_dbg_info.rssi_2ss_sum[1] += p_phy_info->rx_mimo_signal_strength[1]; + p_dm_odm->phy_dbg_info.rssi_2ss_cnt++; + } else if (rate_ss == 3) { + p_dm_odm->phy_dbg_info.rssi_3ss_sum[0] += p_phy_info->rx_mimo_signal_strength[0]; + p_dm_odm->phy_dbg_info.rssi_3ss_sum[1] += p_phy_info->rx_mimo_signal_strength[1]; + p_dm_odm->phy_dbg_info.rssi_3ss_sum[2] += p_phy_info->rx_mimo_signal_strength[2]; + p_dm_odm->phy_dbg_info.rssi_3ss_cnt++; + } else if (rate_ss == 4) { + p_dm_odm->phy_dbg_info.rssi_4ss_sum[0] += p_phy_info->rx_mimo_signal_strength[0]; + p_dm_odm->phy_dbg_info.rssi_4ss_sum[1] += p_phy_info->rx_mimo_signal_strength[1]; + p_dm_odm->phy_dbg_info.rssi_4ss_sum[2] += p_phy_info->rx_mimo_signal_strength[2]; + p_dm_odm->phy_dbg_info.rssi_4ss_sum[3] += p_phy_info->rx_mimo_signal_strength[3]; + p_dm_odm->phy_dbg_info.rssi_4ss_cnt++; + } +} + +u8 phydm_get_signal_quality(struct _odm_phy_status_info_ *p_phy_info,struct PHY_DM_STRUCT *p_dm_odm, struct _phy_status_rpt_8192cd *p_phy_sta_rpt) +{ + u8 SQ_rpt; + if (p_phy_info->rx_pwdb_all > 40 && !p_dm_odm->is_in_hct_test) + return 100; + else { + SQ_rpt = p_phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all; + + if (SQ_rpt > 64) + return 0; + else if (SQ_rpt < 20) + return 100; + else + return ((64 - SQ_rpt) * 100) / 44; + + } +} + +u8 +odm_query_rx_pwr_percentage( + s8 ant_power +) +{ + if ((ant_power <= -100) || (ant_power >= 20)) return 0; - else if (AntPower >= 0) + else if (ant_power >= 0) return 100; else - return (100 + AntPower); + return 100 + ant_power; } -// -// 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. -// IF other SW team do not support the feature, remove this section.?? -// -s4Byte -odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo( - IN OUT PDM_ODM_T pDM_Odm, - s4Byte CurrSig +/* + * 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. + * IF other SW team do not support the feature, remove this section.?? + * */ +s32 +odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_lenovo( + struct PHY_DM_STRUCT *p_dm_odm, + s32 curr_sig ) -{ - s4Byte RetSig = 0; +{ + s32 ret_sig = 0; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - //if(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + /* if(p_dm_odm->support_interface == ODM_ITRF_PCIE) */ { - // Step 1. Scale mapping. - // 20100611 Joseph: Re-tunning RSSI presentation for Lenovo. - // 20100426 Joseph: Modify Signal strength mapping. - // This modification makes the RSSI indication similar to Intel solution. - // 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE. - if (CurrSig >= 54 && CurrSig <= 100) - RetSig = 100; - else if (CurrSig >= 42 && CurrSig <= 53) - RetSig = 95; - else if (CurrSig >= 36 && CurrSig <= 41) - RetSig = 74 + ((CurrSig - 36) * 20) / 6; - else if (CurrSig >= 33 && CurrSig <= 35) - RetSig = 65 + ((CurrSig - 33) * 8) / 2; - else if (CurrSig >= 18 && CurrSig <= 32) - RetSig = 62 + ((CurrSig - 18) * 2) / 15; - else if (CurrSig >= 15 && CurrSig <= 17) - RetSig = 33 + ((CurrSig - 15) * 28) / 2; - else if (CurrSig >= 10 && CurrSig <= 14) - RetSig = 39; - else if (CurrSig >= 8 && CurrSig <= 9) - RetSig = 33; - else if (CurrSig <= 8) - RetSig = 19; - } -#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) - return RetSig; + /* step 1. Scale mapping. */ + /* 20100611 Joseph: Re-tunning RSSI presentation for Lenovo. */ + /* 20100426 Joseph: Modify Signal strength mapping. */ + /* This modification makes the RSSI indication similar to Intel solution. */ + /* 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE. */ + if (curr_sig >= 54 && curr_sig <= 100) + ret_sig = 100; + else if (curr_sig >= 42 && curr_sig <= 53) + ret_sig = 95; + else if (curr_sig >= 36 && curr_sig <= 41) + ret_sig = 74 + ((curr_sig - 36) * 20) / 6; + else if (curr_sig >= 33 && curr_sig <= 35) + ret_sig = 65 + ((curr_sig - 33) * 8) / 2; + else if (curr_sig >= 18 && curr_sig <= 32) + ret_sig = 62 + ((curr_sig - 18) * 2) / 15; + else if (curr_sig >= 15 && curr_sig <= 17) + ret_sig = 33 + ((curr_sig - 15) * 28) / 2; + else if (curr_sig >= 10 && curr_sig <= 14) + ret_sig = 39; + else if (curr_sig >= 8 && curr_sig <= 9) + ret_sig = 33; + else if (curr_sig <= 8) + ret_sig = 19; + } +#endif /* ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ + return ret_sig; } -s4Byte -odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore( - IN OUT PDM_ODM_T pDM_Odm, - s4Byte CurrSig +s32 +odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_netcore( + struct PHY_DM_STRUCT *p_dm_odm, + s32 curr_sig ) { - s4Byte RetSig = 0; + s32 ret_sig = 0; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - //if(pDM_Odm->SupportInterface == ODM_ITRF_USB) + /* if(p_dm_odm->support_interface == ODM_ITRF_USB) */ { - // Netcore request this modification because 2009.04.13 SU driver use it. - if (CurrSig >= 31 && CurrSig <= 100) - RetSig = 100; - else if (CurrSig >= 21 && CurrSig <= 30) - RetSig = 90 + ((CurrSig - 20) / 1); - else if (CurrSig >= 11 && CurrSig <= 20) - RetSig = 80 + ((CurrSig - 10) / 1); - else if (CurrSig >= 7 && CurrSig <= 10) - RetSig = 69 + (CurrSig - 7); - else if (CurrSig == 6) - RetSig = 54; - else if (CurrSig == 5) - RetSig = 45; - else if (CurrSig == 4) - RetSig = 36; - else if (CurrSig == 3) - RetSig = 27; - else if (CurrSig == 2) - RetSig = 18; - else if (CurrSig == 1) - RetSig = 9; + /* Netcore request this modification because 2009.04.13 SU driver use it. */ + if (curr_sig >= 31 && curr_sig <= 100) + ret_sig = 100; + else if (curr_sig >= 21 && curr_sig <= 30) + ret_sig = 90 + ((curr_sig - 20) / 1); + else if (curr_sig >= 11 && curr_sig <= 20) + ret_sig = 80 + ((curr_sig - 10) / 1); + else if (curr_sig >= 7 && curr_sig <= 10) + ret_sig = 69 + (curr_sig - 7); + else if (curr_sig == 6) + ret_sig = 54; + else if (curr_sig == 5) + ret_sig = 45; + else if (curr_sig == 4) + ret_sig = 36; + else if (curr_sig == 3) + ret_sig = 27; + else if (curr_sig == 2) + ret_sig = 18; + else if (curr_sig == 1) + ret_sig = 9; else - RetSig = CurrSig; + ret_sig = curr_sig; } -#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) - return RetSig; +#endif /* ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ + return ret_sig; } -s4Byte -odm_SignalScaleMapping_92CSeries( - IN OUT PDM_ODM_T pDM_Odm, - IN s4Byte CurrSig +s32 +odm_signal_scale_mapping_92c_series( + struct PHY_DM_STRUCT *p_dm_odm, + s32 curr_sig ) { - s4Byte RetSig = 0; -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - { - // Step 1. Scale mapping. - if(CurrSig >= 61 && CurrSig <= 100) - { - RetSig = 90 + ((CurrSig - 60) / 4); - } - else if(CurrSig >= 41 && CurrSig <= 60) - { - RetSig = 78 + ((CurrSig - 40) / 2); - } - else if(CurrSig >= 31 && CurrSig <= 40) - { - RetSig = 66 + (CurrSig - 30); - } - else if(CurrSig >= 21 && CurrSig <= 30) - { - RetSig = 54 + (CurrSig - 20); - } - else if(CurrSig >= 5 && CurrSig <= 20) - { - RetSig = 42 + (((CurrSig - 5) * 2) / 3); - } - else if(CurrSig == 4) - { - RetSig = 36; - } - else if(CurrSig == 3) - { - RetSig = 27; - } - else if(CurrSig == 2) - { - RetSig = 18; - } - else if(CurrSig == 1) - { - RetSig = 9; - } + s32 ret_sig = 0; +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + if (p_dm_odm->support_interface == ODM_ITRF_PCIE) { + /* step 1. Scale mapping. */ + if (curr_sig >= 61 && curr_sig <= 100) + ret_sig = 90 + ((curr_sig - 60) / 4); + else if (curr_sig >= 41 && curr_sig <= 60) + ret_sig = 78 + ((curr_sig - 40) / 2); + else if (curr_sig >= 31 && curr_sig <= 40) + ret_sig = 66 + (curr_sig - 30); + else if (curr_sig >= 21 && curr_sig <= 30) + ret_sig = 54 + (curr_sig - 20); + else if (curr_sig >= 5 && curr_sig <= 20) + ret_sig = 42 + (((curr_sig - 5) * 2) / 3); + else if (curr_sig == 4) + ret_sig = 36; + else if (curr_sig == 3) + ret_sig = 27; + else if (curr_sig == 2) + ret_sig = 18; + else if (curr_sig == 1) + ret_sig = 9; else - { - RetSig = CurrSig; - } - } -#endif - -#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) ||(DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - if((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO)) - { - if(CurrSig >= 51 && CurrSig <= 100) - { - RetSig = 100; - } - else if(CurrSig >= 41 && CurrSig <= 50) - { - RetSig = 80 + ((CurrSig - 40)*2); - } - else if(CurrSig >= 31 && CurrSig <= 40) - { - RetSig = 66 + (CurrSig - 30); - } - else if(CurrSig >= 21 && CurrSig <= 30) - { - RetSig = 54 + (CurrSig - 20); - } - else if(CurrSig >= 10 && CurrSig <= 20) - { - RetSig = 42 + (((CurrSig - 10) * 2) / 3); - } - else if(CurrSig >= 5 && CurrSig <= 9) - { - RetSig = 22 + (((CurrSig - 5) * 3) / 2); - } - else if(CurrSig >= 1 && CurrSig <= 4) - { - RetSig = 6 + (((CurrSig - 1) * 3) / 2); - } + ret_sig = curr_sig; + } +#endif + +#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + if ((p_dm_odm->support_interface == ODM_ITRF_USB) || (p_dm_odm->support_interface == ODM_ITRF_SDIO)) { + if (curr_sig >= 51 && curr_sig <= 100) + ret_sig = 100; + else if (curr_sig >= 41 && curr_sig <= 50) + ret_sig = 80 + ((curr_sig - 40) * 2); + else if (curr_sig >= 31 && curr_sig <= 40) + ret_sig = 66 + (curr_sig - 30); + else if (curr_sig >= 21 && curr_sig <= 30) + ret_sig = 54 + (curr_sig - 20); + else if (curr_sig >= 10 && curr_sig <= 20) + ret_sig = 42 + (((curr_sig - 10) * 2) / 3); + else if (curr_sig >= 5 && curr_sig <= 9) + ret_sig = 22 + (((curr_sig - 5) * 3) / 2); + else if (curr_sig >= 1 && curr_sig <= 4) + ret_sig = 6 + (((curr_sig - 1) * 3) / 2); else - { - RetSig = CurrSig; - } + ret_sig = curr_sig; } #endif - return RetSig; + return ret_sig; } -s4Byte -odm_SignalScaleMapping( - IN OUT PDM_ODM_T pDM_Odm, - IN s4Byte CurrSig +s32 +odm_signal_scale_mapping( + struct PHY_DM_STRUCT *p_dm_odm, + s32 curr_sig ) -{ +{ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if( (pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && //USB & SDIO - (pDM_Odm->PatchID==10))//pMgntInfo->CustomerID == RT_CID_819x_Netcore - { - return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(pDM_Odm,CurrSig); - } - else if( (pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) && - (pDM_Odm->PatchID==19))//pMgntInfo->CustomerID == RT_CID_819x_Lenovo) - { - return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(pDM_Odm, CurrSig); - }else + if ((p_dm_odm->support_platform == ODM_WIN) && + (p_dm_odm->support_interface != ODM_ITRF_PCIE) && /* USB & SDIO */ + (p_dm_odm->patch_id == 10)) /* p_mgnt_info->customer_id == RT_CID_819x_Netcore */ + return odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_netcore(p_dm_odm, curr_sig); + else if ((p_dm_odm->support_platform == ODM_WIN) && + (p_dm_odm->support_interface == ODM_ITRF_PCIE) && + (p_dm_odm->patch_id == 19)) /* p_mgnt_info->customer_id == RT_CID_819X_LENOVO) */ + return odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_lenovo(p_dm_odm, curr_sig); + else #endif - { -#ifdef CONFIG_SIGNAL_SCALE_MAPPING - return odm_SignalScaleMapping_92CSeries(pDM_Odm,CurrSig); + { +#ifdef CONFIG_SIGNAL_SCALE_MAPPING + return odm_signal_scale_mapping_92c_series(p_dm_odm, curr_sig); #else - return CurrSig; + return curr_sig; #endif } - + } -static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo( - IN PDM_ODM_T pDM_Odm, - IN u1Byte isCCKrate, - IN u1Byte PWDB_ALL, - IN u1Byte path, - IN u1Byte RSSI +static u8 odm_sq_process_patch_rt_cid_819x_lenovo( + struct PHY_DM_STRUCT *p_dm_odm, + u8 is_cck_rate, + u8 PWDB_ALL, + u8 path, + u8 RSSI ) { - u1Byte SQ = 0; -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + u8 SQ = 0; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + if (is_cck_rate) { + + if (IS_HARDWARE_TYPE_8192E(p_dm_odm->adapter)) { + + /* */ + /* Expected signal strength and bars indication at Lenovo lab. 2013.04.11 */ + /* 802.11n, 802.11b, 802.11g only at channel 6 */ + /* */ + /* Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm) */ + /* 50 5 -49 */ + /* 55 5 -49 */ + /* 60 5 -50 */ + /* 65 5 -51 */ + /* 70 5 -52 */ + /* 75 5 -54 */ + /* 80 5 -55 */ + /* 85 4 -60 */ + /* 90 3 -63 */ + /* 95 3 -65 */ + /* 100 2 -67 */ + /* 102 2 -67 */ + /* 104 1 -70 */ + /* */ - if(isCCKrate){ - - if (IS_HARDWARE_TYPE_8192E(pDM_Odm->Adapter)) { - - // - // Expected signal strength and bars indication at Lenovo lab. 2013.04.11 - // 802.11n, 802.11b, 802.11g only at channel 6 - // - // Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm) - // 50 5 -49 - // 55 5 -49 - // 60 5 -50 - // 65 5 -51 - // 70 5 -52 - // 75 5 -54 - // 80 5 -55 - // 85 4 -60 - // 90 3 -63 - // 95 3 -65 - // 100 2 -67 - // 102 2 -67 - // 104 1 -70 - // - - if(PWDB_ALL >= 50) + if (PWDB_ALL >= 50) SQ = 100; - else if(PWDB_ALL >= 35 && PWDB_ALL < 50) + else if (PWDB_ALL >= 35 && PWDB_ALL < 50) SQ = 80; - else if(PWDB_ALL >= 31 && PWDB_ALL < 35) + else if (PWDB_ALL >= 31 && PWDB_ALL < 35) SQ = 60; - else if(PWDB_ALL >= 22 && PWDB_ALL < 31) + else if (PWDB_ALL >= 22 && PWDB_ALL < 31) SQ = 40; - else if(PWDB_ALL >= 18 && PWDB_ALL < 22) + else if (PWDB_ALL >= 18 && PWDB_ALL < 22) SQ = 20; else SQ = 10; } else { if (PWDB_ALL >= 50) SQ = 100; - else if (PWDB_ALL >= 35 && PWDB_ALL < 50) + else if (PWDB_ALL >= 35 && PWDB_ALL < 50) SQ = 80; else if (PWDB_ALL >= 22 && PWDB_ALL < 35) SQ = 60; @@ -339,136 +429,134 @@ static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo( else SQ = 10; } - - } - else - {//OFDM rate - if (IS_HARDWARE_TYPE_8192E(pDM_Odm->Adapter)) { - if(RSSI >= 45) + } else { + /* OFDM rate */ + + if (IS_HARDWARE_TYPE_8192E(p_dm_odm->adapter)) { + if (RSSI >= 45) SQ = 100; - else if(RSSI >= 22 && RSSI < 45) + else if (RSSI >= 22 && RSSI < 45) SQ = 80; - else if(RSSI >= 18 && RSSI < 22) + else if (RSSI >= 18 && RSSI < 22) SQ = 40; else - SQ = 20; + SQ = 20; } else { - if(RSSI >= 45) - SQ = 100; - else if(RSSI >= 22 && RSSI < 45) - SQ = 80; - else if(RSSI >= 18 && RSSI < 22) - SQ = 40; - else - SQ = 20; + if (RSSI >= 45) + SQ = 100; + else if (RSSI >= 22 && RSSI < 45) + SQ = 80; + else if (RSSI >= 18 && RSSI < 22) + SQ = 40; + else + SQ = 20; } } - RT_TRACE(COMP_DBG, DBG_TRACE, ("isCCKrate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", isCCKrate, PWDB_ALL, RSSI, SQ)); - + RT_TRACE(COMP_DBG, DBG_TRACE, ("is_cck_rate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", is_cck_rate, PWDB_ALL, RSSI, SQ)); + #endif return SQ; } -static u1Byte odm_SQ_process_patch_RT_CID_819x_Acer( - IN PDM_ODM_T pDM_Odm, - IN u1Byte isCCKrate, - IN u1Byte PWDB_ALL, - IN u1Byte path, - IN u1Byte RSSI +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +static u8 odm_sq_process_patch_rt_cid_819x_acer( + struct PHY_DM_STRUCT *p_dm_odm, + u8 is_cck_rate, + u8 PWDB_ALL, + u8 path, + u8 RSSI ) { - u1Byte SQ = 0; - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + u8 SQ = 0; - if(isCCKrate){ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE(COMP_DBG, DBG_WARNING, ("odm_SQ_process_patch_RT_Acer\n")); - -#if OS_WIN_FROM_WIN8(OS_VERSION) + if (is_cck_rate) { - if(PWDB_ALL >= 50) - SQ = 100; - else if(PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if(PWDB_ALL >= 30 && PWDB_ALL < 35) - SQ = 60; - else if(PWDB_ALL >= 25 && PWDB_ALL < 30) - SQ = 40; - else if(PWDB_ALL >= 20 && PWDB_ALL < 25) - SQ = 20; - else - SQ = 10; + RT_TRACE(COMP_DBG, DBG_WARNING, ("odm_SQ_process_patch_RT_Acer\n")); + +#if OS_WIN_FROM_WIN8(OS_VERSION) + + if (PWDB_ALL >= 50) + SQ = 100; + else if (PWDB_ALL >= 35 && PWDB_ALL < 50) + SQ = 80; + else if (PWDB_ALL >= 30 && PWDB_ALL < 35) + SQ = 60; + else if (PWDB_ALL >= 25 && PWDB_ALL < 30) + SQ = 40; + else if (PWDB_ALL >= 20 && PWDB_ALL < 25) + SQ = 20; + else + SQ = 10; #else - if(PWDB_ALL >= 50) + if (PWDB_ALL >= 50) + SQ = 100; + else if (PWDB_ALL >= 35 && PWDB_ALL < 50) + SQ = 80; + else if (PWDB_ALL >= 30 && PWDB_ALL < 35) + SQ = 60; + else if (PWDB_ALL >= 25 && PWDB_ALL < 30) + SQ = 40; + else if (PWDB_ALL >= 20 && PWDB_ALL < 25) + SQ = 20; + else + SQ = 10; + + if (PWDB_ALL == 0) /* Abnormal case, do not indicate the value above 20 on Win7 */ + SQ = 20; +#endif + + + + } else { + /* OFDM rate */ + + if (IS_HARDWARE_TYPE_8192E(p_dm_odm->adapter)) { + if (RSSI >= 45) SQ = 100; - else if(PWDB_ALL >= 35 && PWDB_ALL < 50) + else if (RSSI >= 22 && RSSI < 45) SQ = 80; - else if(PWDB_ALL >= 30 && PWDB_ALL < 35) - SQ = 60; - else if(PWDB_ALL >= 25 && PWDB_ALL < 30) + else if (RSSI >= 18 && RSSI < 22) SQ = 40; - else if(PWDB_ALL >= 20 && PWDB_ALL < 25) - SQ = 20; else - SQ = 10; - - if(PWDB_ALL == 0)// Abnormal case, do not indicate the value above 20 on Win7 SQ = 20; -#endif - - - - } - else - {//OFDM rate - - if (IS_HARDWARE_TYPE_8192E(pDM_Odm->Adapter)) { - if(RSSI >= 45) + } else { + if (RSSI >= 35) SQ = 100; - else if(RSSI >= 22 && RSSI < 45) + else if (RSSI >= 30 && RSSI < 35) SQ = 80; - else if(RSSI >= 18 && RSSI < 22) + else if (RSSI >= 25 && RSSI < 30) SQ = 40; else - SQ = 20; - } - else - { - if(RSSI >= 35) - SQ = 100; - else if(RSSI >= 30 && RSSI < 35) - SQ = 80; - else if(RSSI >= 25 && RSSI < 30) - SQ = 40; - else - SQ = 20; - } + SQ = 20; + } } - RT_TRACE(COMP_DBG, DBG_LOUD, ("isCCKrate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", isCCKrate, PWDB_ALL, RSSI, SQ)); - + RT_TRACE(COMP_DBG, DBG_LOUD, ("is_cck_rate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", is_cck_rate, PWDB_ALL, RSSI, SQ)); + #endif return SQ; } - -static u1Byte -odm_EVMdbToPercentage( - IN s1Byte Value - ) +#endif + +static u8 +odm_evm_db_to_percentage( + s8 value +) { - // - // -33dB~0dB to 0%~99% - // - s1Byte ret_val; - - ret_val = Value; + /* */ + /* -33dB~0dB to 0%~99% */ + /* */ + s8 ret_val; + + ret_val = value; ret_val /= 2; - /*DbgPrint("Value=%d\n", Value);*/ - /*ODM_RT_DISP(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x\n", ret_val, ret_val));*/ + /*dbg_print("value=%d\n", value);*/ + /*ODM_RT_DISP(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C value=%d / %x\n", ret_val, ret_val));*/ #ifdef ODM_EVM_ENHANCE_ANTDIV if (ret_val >= 0) ret_val = 0; @@ -492,61 +580,83 @@ odm_EVMdbToPercentage( ret_val = 100; #endif - return (u1Byte)ret_val; + return (u8)ret_val; } - -static u1Byte -odm_EVMdbm_JaguarSeries( - IN s1Byte Value - ) + +static u8 +odm_evm_dbm_jaguar_series( + s8 value +) { - s1Byte ret_val = Value; - - // -33dB~0dB to 33dB ~ 0dB - if(ret_val == -128) + s8 ret_val = value; + + /* -33dB~0dB to 33dB ~ 0dB */ + if (ret_val == -128) ret_val = 127; else if (ret_val < 0) ret_val = 0 - ret_val; - + ret_val = ret_val >> 1; - return (u1Byte)ret_val; + return (u8)ret_val; } -static s2Byte -odm_Cfo( - IN s1Byte Value +static s16 +odm_cfo( + s8 value ) { - s2Byte ret_val; + s16 ret_val; - if (Value < 0) - { - ret_val = 0 - Value; - ret_val = (ret_val << 1) + (ret_val >> 1) ; // *2.5~=312.5/2^7 - ret_val = ret_val | BIT12; // set bit12 as 1 for negative cfo - } - else - { - ret_val = Value; - ret_val = (ret_val << 1) + (ret_val>>1) ; // *2.5~=312.5/2^7 + if (value < 0) { + ret_val = 0 - value; + ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */ + ret_val = ret_val | BIT(12); /* set bit12 as 1 for negative cfo */ + } else { + ret_val = value; + ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */ } return ret_val; } -#if(ODM_IC_11N_SERIES_SUPPORT == 1) +u8 +phydm_rate_to_num_ss( + struct PHY_DM_STRUCT *p_dm_odm, + u8 data_rate +) +{ + u8 num_ss = 1; + + if (data_rate <= ODM_RATE54M) + num_ss = 1; + else if (data_rate <= ODM_RATEMCS31) + num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1; + else if (data_rate <= ODM_RATEVHTSS1MCS9) + num_ss = 1; + else if (data_rate <= ODM_RATEVHTSS2MCS9) + num_ss = 2; + else if (data_rate <= ODM_RATEVHTSS3MCS9) + num_ss = 3; + else if (data_rate <= ODM_RATEVHTSS4MCS9) + num_ss = 4; + + return num_ss; +} + +#if (ODM_IC_11N_SERIES_SUPPORT == 1) -s1Byte +#if (RTL8703B_SUPPORT == 1) +s8 odm_CCKRSSI_8703B( - IN u2Byte LNA_idx, - IN u1Byte VGA_idx - ) + u16 LNA_idx, + u8 VGA_idx +) { - s1Byte rx_pwr_all = 0x00; - + s8 rx_pwr_all = 0x00; + switch (LNA_idx) { case 0xf: rx_pwr_all = -48 - (2 * VGA_idx); - break; + break; case 0xb: rx_pwr_all = -42 - (2 * VGA_idx); /*TBD*/ break; @@ -556,456 +666,479 @@ odm_CCKRSSI_8703B( case 8: rx_pwr_all = -32 - (2 * VGA_idx); break; - case 7: + case 7: rx_pwr_all = -19 - (2 * VGA_idx); - break; - case 4: + break; + case 4: rx_pwr_all = -6 - (2 * VGA_idx); break; - case 0: + case 0: rx_pwr_all = -2 - (2 * VGA_idx); break; default: - /*rx_pwr_all = -53+(2*(31-VGA_idx));*/ - /*DbgPrint("wrong LNA index\n");*/ + /*rx_pwr_all = -53+(2*(31-VGA_idx));*/ + /*dbg_print("wrong LNA index\n");*/ break; - + } return rx_pwr_all; } +#endif + +#if (RTL8195A_SUPPORT == 1) +s8 +odm_CCKRSSI_8195A( + struct PHY_DM_STRUCT *p_dm_odm, + u16 LNA_idx, + u8 VGA_idx +) +{ + s8 rx_pwr_all = 0; + s8 lna_gain = 0; + s8 lna_gain_table_0[8] = {0, -8, -15, -22, -29, -36, -45, -54}; + s8 lna_gain_table_1[8] = {0, -8, -15, -22, -29, -36, -45, -54};/*use 8195A to calibrate this table. 2016.06.24, Dino*/ + + if (p_dm_odm->cck_agc_report_type == 0) + lna_gain = lna_gain_table_0[LNA_idx]; + else + lna_gain = lna_gain_table_1[LNA_idx]; + + rx_pwr_all = lna_gain - (2 * VGA_idx); -s1Byte + return rx_pwr_all; +} +#endif + +#if (RTL8192E_SUPPORT == 1) +s8 odm_CCKRSSI_8192E( - IN OUT PDM_ODM_T pDM_Odm, - IN u2Byte LNA_idx, - IN u1Byte VGA_idx - ) + struct PHY_DM_STRUCT *p_dm_odm, + u16 LNA_idx, + u8 VGA_idx +) { - s1Byte rx_pwr_all = 0; - s1Byte lna_gain = 0; - s1Byte lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44}; - s1Byte lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36};/*use 8192EU to calibrate this table. 2015.12.15, Dino*/ + s8 rx_pwr_all = 0; + s8 lna_gain = 0; + s8 lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44}; + s8 lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36};/*use 8192EU to calibrate this table. 2015.12.15, Dino*/ - if (pDM_Odm->cck_agc_report_type == 0) + if (p_dm_odm->cck_agc_report_type == 0) lna_gain = lna_gain_table_0[LNA_idx]; else lna_gain = lna_gain_table_1[LNA_idx]; rx_pwr_all = lna_gain - (2 * VGA_idx); - + return rx_pwr_all; } +#endif -s1Byte +#if (RTL8188E_SUPPORT == 1) +s8 odm_CCKRSSI_8188E( - IN OUT PDM_ODM_T pDM_Odm, - IN u2Byte LNA_idx, - IN u1Byte VGA_idx - ) + struct PHY_DM_STRUCT *p_dm_odm, + u16 LNA_idx, + u8 VGA_idx +) { - s1Byte rx_pwr_all = 0; - s1Byte lna_gain = 0; - s1Byte lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41};/*only use lna0/1/2/3/7*/ - s1Byte lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; /*only use lna3 /7*/ + s8 rx_pwr_all = 0; + s8 lna_gain = 0; + s8 lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41};/*only use lna0/1/2/3/7*/ + s8 lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; /*only use lna3 /7*/ - if (pDM_Odm->CutVersion >= ODM_CUT_I) /*SMIC*/ + if (p_dm_odm->cut_version >= ODM_CUT_I) /*SMIC*/ lna_gain = lna_gain_table_0[LNA_idx]; - else /*TSMC*/ + else /*TSMC*/ lna_gain = lna_gain_table_1[LNA_idx]; - + rx_pwr_all = lna_gain - (2 * VGA_idx); - + return rx_pwr_all; } +#endif -VOID -odm_RxPhyStatus92CSeries_Parsing( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo - ) -{ - SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - u1Byte i, Max_spatial_stream; - s1Byte rx_pwr[4], rx_pwr_all=0; - u1Byte EVM, PWDB_ALL = 0, PWDB_ALL_BT; - u1Byte RSSI, total_rssi=0; - BOOLEAN isCCKrate=FALSE; - u1Byte rf_rx_num = 0; - u1Byte cck_highpwr = 0; - u1Byte LNA_idx = 0; - u1Byte VGA_idx = 0; - u1Byte cck_agc_rpt; - PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus; - - isCCKrate = (pPktinfo->DataRate <= ODM_RATE11M) ? TRUE : FALSE; - - if (pPktinfo->bToSelf) - pDM_Odm->curr_station_id = pPktinfo->StationID; - - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; +void +odm_rx_phy_status92c_series_parsing( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo +) +{ + u8 i, max_spatial_stream; + s8 rx_pwr[4], rx_pwr_all = 0; + u8 EVM, PWDB_ALL = 0, PWDB_ALL_BT; + u8 RSSI, total_rssi = 0; + boolean is_cck_rate = false; + u8 rf_rx_num = 0; + u8 LNA_idx = 0; + u8 VGA_idx = 0; + u8 cck_agc_rpt; + u8 num_ss; + u8 stream_rxevm_tmp = 0; + struct _phy_status_rpt_8192cd *p_phy_sta_rpt = (struct _phy_status_rpt_8192cd *)p_phy_status; + is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false; + p_dm_odm->rate_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); - if(isCCKrate) - { - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; - cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ; - - if (pDM_Odm->SupportICType & (ODM_RTL8703B)) { - - #if (RTL8703B_SUPPORT == 1) - if (pDM_Odm->cck_agc_report_type == 1) { /*4 bit LNA*/ + if (p_pktinfo->is_to_self) + p_dm_odm->curr_station_id = p_pktinfo->station_id; + + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1; + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1; + + + if (is_cck_rate) { + p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++; + cck_agc_rpt = p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a ; + + if (p_dm_odm->support_ic_type & (ODM_RTL8703B)) { + +#if (RTL8703B_SUPPORT == 1) + if (p_dm_odm->cck_agc_report_type == 1) { /*4 bit LNA*/ + + u8 cck_agc_rpt_b = (p_phy_sta_rpt->cck_rpt_b_ofdm_cfosho_b & BIT(7)) ? 1 : 0; - u1Byte cck_agc_rpt_b = (pPhyStaRpt->cck_rpt_b_ofdm_cfosho_b & BIT7) ? 1 : 0; - LNA_idx = (cck_agc_rpt_b << 3) | ((cck_agc_rpt & 0xE0) >> 5); VGA_idx = (cck_agc_rpt & 0x1F); - - rx_pwr_all = odm_CCKRSSI_8703B(LNA_idx, VGA_idx); + + rx_pwr_all = odm_CCKRSSI_8703B(LNA_idx, VGA_idx); } - #endif +#endif } else { /*3 bit LNA*/ - - LNA_idx = ((cck_agc_rpt & 0xE0) >>5); + + LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); VGA_idx = (cck_agc_rpt & 0x1F); - - if (pDM_Odm->SupportICType & (ODM_RTL8188E)) { - - #if (RTL8188E_SUPPORT == 1) - rx_pwr_all = odm_CCKRSSI_8188E(pDM_Odm, LNA_idx, VGA_idx); + + if (p_dm_odm->support_ic_type & (ODM_RTL8188E)) { + +#if (RTL8188E_SUPPORT == 1) + rx_pwr_all = odm_CCKRSSI_8188E(p_dm_odm, LNA_idx, VGA_idx); /**/ - #endif - } - #if (RTL8192E_SUPPORT == 1) - else if (pDM_Odm->SupportICType & (ODM_RTL8192E)) { - - rx_pwr_all = odm_CCKRSSI_8192E(pDM_Odm, LNA_idx, VGA_idx); +#endif + } +#if (RTL8192E_SUPPORT == 1) + else if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { + + rx_pwr_all = odm_CCKRSSI_8192E(p_dm_odm, LNA_idx, VGA_idx); /**/ } - #endif - #if (RTL8723B_SUPPORT == 1) - else if (pDM_Odm->SupportICType & (ODM_RTL8723B)) { - - rx_pwr_all = odm_CCKRSSI_8723B(LNA_idx,VGA_idx); +#endif +#if (RTL8723B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type & (ODM_RTL8723B)) { + + rx_pwr_all = odm_CCKRSSI_8723B(LNA_idx, VGA_idx); /**/ - } - #endif - #if (RTL8188F_SUPPORT == 1) - else if (pDM_Odm->SupportICType & (ODM_RTL8188F)) { - + } +#endif +#if (RTL8188F_SUPPORT == 1) + else if (p_dm_odm->support_ic_type & (ODM_RTL8188F)) { + rx_pwr_all = odm_CCKRSSI_8188F(LNA_idx, VGA_idx); /**/ } - #endif +#endif +#if (RTL8195A_SUPPORT == 1) + else if (p_dm_odm->support_ic_type & (ODM_RTL8195A)) { + + rx_pwr_all = odm_CCKRSSI_8195A(LNA_idx, VGA_idx); + /**/ + } +#endif } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ExtLNAGain (( %d )), LNA_idx: (( 0x%x )), VGA_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n", - pDM_Odm->ExtLNAGain, LNA_idx, VGA_idx, rx_pwr_all)); - - if (pDM_Odm->BoardType & ODM_BOARD_EXT_LNA) - rx_pwr_all -= pDM_Odm->ExtLNAGain; - PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); - - if (pPktinfo->bToSelf) { - pDM_Odm->cck_lna_idx = LNA_idx; - pDM_Odm->cck_vga_idx = VGA_idx; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ext_lna_gain (( %d )), LNA_idx: (( 0x%x )), VGA_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n", + p_dm_odm->ext_lna_gain, LNA_idx, VGA_idx, rx_pwr_all)); + + if (p_dm_odm->board_type & ODM_BOARD_EXT_LNA) + rx_pwr_all -= p_dm_odm->ext_lna_gain; + + PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); + + if (p_pktinfo->is_to_self) { + p_dm_odm->cck_lna_idx = LNA_idx; + p_dm_odm->cck_vga_idx = VGA_idx; } - pPhyInfo->RxPWDBAll = PWDB_ALL; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->BTRxRSSIPercentage = PWDB_ALL; - pPhyInfo->RecvSignalPower = rx_pwr_all; -#endif - // - // (3) Get Signal Quality (EVM) - // - //if(pPktinfo->bPacketMatchBSSID) + p_phy_info->rx_pwdb_all = PWDB_ALL; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + p_phy_info->bt_rx_rssi_percentage = PWDB_ALL; + p_phy_info->recv_signal_power = rx_pwr_all; +#endif + /* */ + /* (3) Get Signal Quality (EVM) */ + /* */ + /* if(p_pktinfo->is_packet_match_bssid) */ { - u1Byte SQ,SQ_rpt; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if((pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->PatchID==RT_CID_819x_Lenovo)){ - SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0); - }else if((pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->PatchID==RT_CID_819x_Acer)) - { - SQ = odm_SQ_process_patch_RT_CID_819x_Acer(pDM_Odm,isCCKrate,PWDB_ALL,0,0); - }else + u8 SQ; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if ((p_dm_odm->support_platform == ODM_WIN) && + (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) + SQ = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, 0, 0); + else if ((p_dm_odm->support_platform == ODM_WIN) && + (p_dm_odm->patch_id == RT_CID_819X_ACER)) + SQ = odm_sq_process_patch_rt_cid_819x_acer(p_dm_odm, is_cck_rate, PWDB_ALL, 0, 0); + else #endif - if(pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest){ - SQ = 100; - } - else{ - SQ_rpt = pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all; - - if(SQ_rpt > 64) - SQ = 0; - else if (SQ_rpt < 20) - SQ = 100; - else - SQ = ((64-SQ_rpt) * 100) / 44; - - } - - //DbgPrint("cck SQ = %d\n", SQ); - pPhyInfo->SignalQuality = SQ; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; + SQ = phydm_get_signal_quality(p_phy_info, p_dm_odm, p_phy_sta_rpt); + + /* dbg_print("cck SQ = %d\n", SQ); */ + p_phy_info->signal_quality = SQ; + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = SQ; + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1; } for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) { if (i == 0) - pPhyInfo->RxMIMOSignalStrength[0] = PWDB_ALL; + p_phy_info->rx_mimo_signal_strength[0] = PWDB_ALL; else - pPhyInfo->RxMIMOSignalStrength[1] = 0; + p_phy_info->rx_mimo_signal_strength[1] = 0; } - } - else //2 is OFDM rate - { - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + } else { /* 2 is OFDM rate */ + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; - // - // (1)Get RSSI for HT rate - // - - for(i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) - { - // 2008/01/30 MH we will judge RF RX path now. - if (pDM_Odm->RFPathRxEnable & BIT(i)) + /* */ + /* (1)Get RSSI for HT rate */ + /* */ + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) { + /* 2008/01/30 MH we will judge RF RX path now. */ + if (p_dm_odm->rf_path_rx_enable & BIT(i)) rf_rx_num++; - //else - //continue; + /* else */ + /* continue; */ - rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain& 0x3F)*2) - 110; - - if (pPktinfo->bToSelf) { - pDM_Odm->ofdm_agc_idx[i] = (pPhyStaRpt->path_agc[i].gain & 0x3F); + rx_pwr[i] = ((p_phy_sta_rpt->path_agc[i].gain & 0x3F) * 2) - 110; + + if (p_pktinfo->is_to_self) { + p_dm_odm->ofdm_agc_idx[i] = (p_phy_sta_rpt->path_agc[i].gain & 0x3F); /**/ } - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->RxPwr[i] = rx_pwr[i]; - #endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + p_phy_info->rx_pwr[i] = rx_pwr[i]; +#endif /* Translate DBM to percentage. */ - RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]); + RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]); total_rssi += RSSI; - //RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); - - pPhyInfo->RxMIMOSignalStrength[i] =(u1Byte) RSSI; + /* RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); */ + + p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI; + +#if (DM_ODM_SUPPORT_TYPE & (/*ODM_WIN|*/ODM_CE|ODM_AP)) + /* Get Rx snr value in DB */ + p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = (s32)(p_phy_sta_rpt->path_rxsnr[i] / 2); +#endif - #if (DM_ODM_SUPPORT_TYPE & (/*ODM_WIN|*/ODM_CE|ODM_AP)) - //Get Rx snr value in DB - pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s4Byte)(pPhyStaRpt->path_rxsnr[i]/2); - #endif - /* Record Signal Strength for next packet */ - //if(pPktinfo->bPacketMatchBSSID) - { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if((pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->PatchID==RT_CID_819x_Lenovo)) - { - if(i==ODM_RF_PATH_A) - pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,i,RSSI); - - } - else if((pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->PatchID==RT_CID_819x_Acer)) - { - pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Acer(pDM_Odm,isCCKrate,PWDB_ALL,0,RSSI); - } -#endif + /* if(p_pktinfo->is_packet_match_bssid) */ + { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if ((p_dm_odm->support_platform == ODM_WIN) && + (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) { + if (i == ODM_RF_PATH_A) + p_phy_info->signal_quality = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, i, RSSI); + + } else if ((p_dm_odm->support_platform == ODM_WIN) && + (p_dm_odm->patch_id == RT_CID_819X_ACER)) + p_phy_info->signal_quality = odm_sq_process_patch_rt_cid_819x_acer(p_dm_odm, is_cck_rate, PWDB_ALL, 0, RSSI); +#endif } } - - - // - // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) - // - rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1 )& 0x7f) -110; - - PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); - - - pPhyInfo->RxPWDBAll = PWDB_ALL; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",pPhyInfo->RxPWDBAll)); - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT; - pPhyInfo->RxPower = rx_pwr_all; - pPhyInfo->RecvSignalPower = rx_pwr_all; - #endif - - if((pDM_Odm->SupportPlatform == ODM_WIN) &&(pDM_Odm->PatchID==19)){ - //do nothing - }else if((pDM_Odm->SupportPlatform == ODM_WIN) &&(pDM_Odm->PatchID==25)){ - //do nothing - } - else{//pMgntInfo->CustomerID != RT_CID_819x_Lenovo - // - // (3)EVM of HT rate - // - if(pPktinfo->DataRate >=ODM_RATEMCS8 && pPktinfo->DataRate <=ODM_RATEMCS15) - Max_spatial_stream = 2; //both spatial stream make sense + + + /* */ + /* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */ + /* */ + rx_pwr_all = (((p_phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all) >> 1) & 0x7f) - 110; + + PWDB_ALL_BT = PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); + + + p_phy_info->rx_pwdb_all = PWDB_ALL; + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all)); */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + p_phy_info->bt_rx_rssi_percentage = PWDB_ALL_BT; + p_phy_info->rx_power = rx_pwr_all; + p_phy_info->recv_signal_power = rx_pwr_all; +#endif + + if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 19)) { + /* do nothing */ + } else if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 25)) { + /* do nothing */ + } else { /* p_mgnt_info->customer_id != RT_CID_819X_LENOVO */ + /* */ + /* (3)EVM of HT rate */ + /* */ + if (p_pktinfo->data_rate >= ODM_RATEMCS8 && p_pktinfo->data_rate <= ODM_RATEMCS15) + max_spatial_stream = 2; /* both spatial stream make sense */ else - Max_spatial_stream = 1; //only spatial stream 1 makes sense + max_spatial_stream = 1; /* only spatial stream 1 makes sense */ - for(i=0; i>= 1" because the compilor of free build environment - // fill most significant bit to "zero" when doing shifting operation which may change a negative - // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. - EVM = odm_EVMdbToPercentage( (pPhyStaRpt->stream_rxevm[i] )); //dbm + for (i = 0; i < max_spatial_stream; i++) { + /* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */ + /* fill most significant bit to "zero" when doing shifting operation which may change a negative */ + /* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */ + EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->stream_rxevm[i])); /* dbm */ - //GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM)); - - //if(pPktinfo->bPacketMatchBSSID) + /* GET_RX_STATUS_DESC_RX_MCS(p_desc), p_drv_info->rxevm[i], "%", EVM)); */ +#if 0 + /* if(p_pktinfo->is_packet_match_bssid) */ { - if(i==ODM_RF_PATH_A) // Fill value in RFD, Get the first spatial stream only - { - pPhyInfo->SignalQuality = (u1Byte)(EVM & 0xff); - } - pPhyInfo->RxMIMOSignalQuality[i] = (u1Byte)(EVM & 0xff); +#endif + if (i == ODM_RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */ + p_phy_info->signal_quality = (u8)(EVM & 0xff); + p_phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff); + + if (p_phy_sta_rpt->stream_rxevm[i] < 0) + stream_rxevm_tmp = (u8)(0 - (p_phy_sta_rpt->stream_rxevm[i])); + + if (stream_rxevm_tmp == 64) + stream_rxevm_tmp = 0; + + p_phy_info->rx_mimo_evm_dbm[i] = stream_rxevm_tmp; +#if 0 } +#endif } } - ODM_ParsingCFO(pDM_Odm, pPktinfo, pPhyStaRpt->path_cfotail); - + num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); + odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->path_cfotail, num_ss); + } -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - //UI BSS List signal strength(in percentage), make it good looking, from 0~100. - //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). - if(isCCKrate) - { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + /* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */ + /* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */ + if (is_cck_rate) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - // 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ - pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, PWDB_ALL, TRUE, TRUE); + /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */ + p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, PWDB_ALL, true, true); #else - pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/*PWDB_ALL;*/ + p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, PWDB_ALL));/*PWDB_ALL;*/ #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ - } - else - { - if (rf_rx_num != 0) - { - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - // 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ - pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, (total_rssi /= rf_rx_num), TRUE, FALSE); - #else - pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, total_rssi /= rf_rx_num)); - #endif + } else { + if (rf_rx_num != 0) { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */ + p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, (total_rssi /= rf_rx_num), true, false); +#else + p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, total_rssi /= rf_rx_num)); +#endif } } #endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))*/ - //DbgPrint("isCCKrate = %d, pPhyInfo->RxPWDBAll = %d, pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a = 0x%x\n", - //isCCKrate, pPhyInfo->RxPWDBAll, pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a); + /* dbg_print("is_cck_rate = %d, p_phy_info->rx_pwdb_all = %d, p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a = 0x%x\n", */ + /* is_cck_rate, p_phy_info->rx_pwdb_all, p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a); */ - //For 92C/92D HW (Hybrid) Antenna Diversity -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - //For 88E HW Antenna Diversity - pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->ant_sel; - pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->ant_sel_b; - pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antsel_rx_keep_2; + /* For 92C/92D HW (Hybrid) Antenna Diversity */ +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + /* For 88E HW Antenna Diversity */ + p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->ant_sel; + p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->ant_sel_b; + p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antsel_rx_keep_2; #endif + + if (p_pktinfo->is_packet_match_bssid) { + phydm_avg_rssi_for_ss(p_dm_odm, p_phy_info, p_pktinfo); + phydm_rx_statistic_cal(p_dm_odm, p_phy_status, p_pktinfo); + } + } #endif #if ODM_IC_11AC_SERIES_SUPPORT -VOID -odm_RxPhyBWJaguarSeries_Parsing( - OUT PODM_PHY_INFO_T pPhyInfo, - IN PODM_PACKET_INFO_T pPktinfo, - IN PPHY_STATUS_RPT_8812_T pPhyStaRpt +void +odm_rx_phy_bw_jaguar_series_parsing( + struct _odm_phy_status_info_ *p_phy_info, + struct _odm_per_pkt_info_ *p_pktinfo, + struct _phy_status_rpt_8812 *p_phy_sta_rpt ) { - if(pPktinfo->DataRate <= ODM_RATE54M) { - switch (pPhyStaRpt->r_RFMOD) { + if (p_pktinfo->data_rate <= ODM_RATE54M) { + switch (p_phy_sta_rpt->r_RFMOD) { case 1: - if (pPhyStaRpt->sub_chnl == 0) - pPhyInfo->BandWidth = 1; + if (p_phy_sta_rpt->sub_chnl == 0) + p_phy_info->band_width = 1; else - pPhyInfo->BandWidth = 0; + p_phy_info->band_width = 0; break; case 2: - if (pPhyStaRpt->sub_chnl == 0) - pPhyInfo->BandWidth = 2; - else if (pPhyStaRpt->sub_chnl == 9 || pPhyStaRpt->sub_chnl == 10) - pPhyInfo->BandWidth = 1; + if (p_phy_sta_rpt->sub_chnl == 0) + p_phy_info->band_width = 2; + else if (p_phy_sta_rpt->sub_chnl == 9 || p_phy_sta_rpt->sub_chnl == 10) + p_phy_info->band_width = 1; else - pPhyInfo->BandWidth = 0; + p_phy_info->band_width = 0; break; default: case 0: - pPhyInfo->BandWidth = 0; + p_phy_info->band_width = 0; break; } } } -VOID -odm_RxPhyStatusJaguarSeries_Parsing( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo +void +odm_rx_phy_status_jaguar_series_parsing( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo ) { - u1Byte i, Max_spatial_stream; - s1Byte rx_pwr[4], rx_pwr_all = 0; - u1Byte EVM, EVMdbm, PWDB_ALL = 0, PWDB_ALL_BT; - u1Byte RSSI, avg_rssi = 0, best_rssi = 0, second_rssi = 0; - u1Byte isCCKrate = 0; - u1Byte rf_rx_num = 0; - u1Byte cck_highpwr = 0; - u1Byte LNA_idx, VGA_idx; - PPHY_STATUS_RPT_8812_T pPhyStaRpt = (PPHY_STATUS_RPT_8812_T)pPhyStatus; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - - odm_RxPhyBWJaguarSeries_Parsing(pPhyInfo, pPktinfo, pPhyStaRpt); - - if (pPktinfo->DataRate <= ODM_RATE11M) - isCCKrate = TRUE; - else - isCCKrate = FALSE; - - if (pPktinfo->bToSelf) - pDM_Odm->curr_station_id = pPktinfo->StationID; + u8 i, max_spatial_stream; + s8 rx_pwr[4], rx_pwr_all = 0; + u8 EVM = 0, evm_dbm, PWDB_ALL = 0, PWDB_ALL_BT; + u8 RSSI, avg_rssi = 0, best_rssi = 0, second_rssi = 0; + u8 is_cck_rate = 0; + u8 rf_rx_num = 0; + u8 cck_highpwr = 0; + u8 LNA_idx, VGA_idx; + struct _phy_status_rpt_8812 *p_phy_sta_rpt = (struct _phy_status_rpt_8812 *)p_phy_status; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + u8 num_ss; + + odm_rx_phy_bw_jaguar_series_parsing(p_phy_info, p_pktinfo, p_phy_sta_rpt); + + is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false; + p_dm_odm->rate_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); + + if (p_pktinfo->is_to_self) + p_dm_odm->curr_station_id = p_pktinfo->station_id; else - pDM_Odm->curr_station_id = 0xff; + p_dm_odm->curr_station_id = 0xff; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_C] = -1; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_D] = -1; + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1; + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1; + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_C] = -1; + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_D] = -1; - if (isCCKrate) { - u1Byte cck_agc_rpt; - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; + if (is_cck_rate) { + u8 cck_agc_rpt; + p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++; /*(1)Hardware does not provide RSSI for CCK*/ /*(2)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ - /*if(pHalData->eRFPowerState == eRfOn)*/ - cck_highpwr = pDM_Odm->bCckHighPower; + /*if(p_hal_data->e_rf_power_state == e_rf_on)*/ + cck_highpwr = p_dm_odm->is_cck_high_power; /*else*/ - /*cck_highpwr = FALSE;*/ + /*cck_highpwr = false;*/ - cck_agc_rpt = pPhyStaRpt->cfosho[0] ; + cck_agc_rpt = p_phy_sta_rpt->cfosho[0] ; LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); VGA_idx = (cck_agc_rpt & 0x1F); - if (pDM_Odm->SupportICType == ODM_RTL8812) { + if (p_dm_odm->support_ic_type == ODM_RTL8812) { switch (LNA_idx) { case 7: if (VGA_idx <= 27) @@ -1039,13 +1172,13 @@ odm_RxPhyStatusJaguarSeries_Parsing( rx_pwr_all = 14 - 2 * VGA_idx; break; default: - /*DbgPrint("CCK Exception default\n");*/ + /*dbg_print("CCK Exception default\n");*/ break; } rx_pwr_all += 6; - PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - if (cck_highpwr == FALSE) { + if (cck_highpwr == false) { if (PWDB_ALL >= 80) PWDB_ALL = ((PWDB_ALL - 80) << 1) + ((PWDB_ALL - 80) >> 1) + 80; else if ((PWDB_ALL <= 78) && (PWDB_ALL >= 20)) @@ -1053,87 +1186,87 @@ odm_RxPhyStatusJaguarSeries_Parsing( if (PWDB_ALL > 100) PWDB_ALL = 100; } - } else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A)) { - s1Byte Pout = -6; + } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { + s8 pout = -6; switch (LNA_idx) { case 5: - rx_pwr_all = Pout - 32 - (2 * VGA_idx); + rx_pwr_all = pout - 32 - (2 * VGA_idx); break; case 4: - rx_pwr_all = Pout - 24 - (2 * VGA_idx); + rx_pwr_all = pout - 24 - (2 * VGA_idx); break; case 2: - rx_pwr_all = Pout - 11 - (2 * VGA_idx); + rx_pwr_all = pout - 11 - (2 * VGA_idx); break; case 1: - rx_pwr_all = Pout + 5 - (2 * VGA_idx); + rx_pwr_all = pout + 5 - (2 * VGA_idx); break; case 0: - rx_pwr_all = Pout + 21 - (2 * VGA_idx); + rx_pwr_all = pout + 21 - (2 * VGA_idx); break; } - PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); - } else if (pDM_Odm->SupportICType == ODM_RTL8814A || pDM_Odm->SupportICType == ODM_RTL8822B) { - s1Byte Pout = -6; + PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); + } else if (p_dm_odm->support_ic_type == ODM_RTL8814A || p_dm_odm->support_ic_type == ODM_RTL8822B) { + s8 pout = -6; switch (LNA_idx) { /*CCK only use LNA: 2, 3, 5, 7*/ case 7: - rx_pwr_all = Pout - 32 - (2 * VGA_idx); + rx_pwr_all = pout - 32 - (2 * VGA_idx); break; case 5: - rx_pwr_all = Pout - 22 - (2 * VGA_idx); + rx_pwr_all = pout - 22 - (2 * VGA_idx); break; case 3: - rx_pwr_all = Pout - 2 - (2 * VGA_idx); + rx_pwr_all = pout - 2 - (2 * VGA_idx); break; case 2: - rx_pwr_all = Pout + 5 - (2 * VGA_idx); + rx_pwr_all = pout + 5 - (2 * VGA_idx); break; /*case 6:*/ - /*rx_pwr_all = Pout -26 - (2*VGA_idx);*/ + /*rx_pwr_all = pout -26 - (2*VGA_idx);*/ /*break;*/ /*case 4:*/ - /*rx_pwr_all = Pout - 8 - (2*VGA_idx);*/ + /*rx_pwr_all = pout - 8 - (2*VGA_idx);*/ /*break;*/ /*case 1:*/ - /*rx_pwr_all = Pout + 21 - (2*VGA_idx);*/ + /*rx_pwr_all = pout + 21 - (2*VGA_idx);*/ /*break;*/ /*case 0:*/ - /*rx_pwr_all = Pout + 10 - (2*VGA_idx);*/ -/* // break;*/ + /*rx_pwr_all = pout + 10 - (2*VGA_idx);*/ + /* break; */ default: -/* //DbgPrint("CCK Exception default\n");*/ + /* dbg_print("CCK Exception default\n"); */ break; } - PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); } - pDM_Odm->cck_lna_idx = LNA_idx; - pDM_Odm->cck_vga_idx = VGA_idx; - pPhyInfo->RxPWDBAll = PWDB_ALL; -/* //if(pPktinfo->StationID == 0)*/ -/* //{*/ -/* // DbgPrint("CCK: LNA_idx = %d, VGA_idx = %d, pPhyInfo->RxPWDBAll = %d\n",*/ -/* // LNA_idx, VGA_idx, pPhyInfo->RxPWDBAll);*/ -/* //}*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->BTRxRSSIPercentage = PWDB_ALL; - pPhyInfo->RecvSignalPower = rx_pwr_all; + p_dm_odm->cck_lna_idx = LNA_idx; + p_dm_odm->cck_vga_idx = VGA_idx; + p_phy_info->rx_pwdb_all = PWDB_ALL; + /* if(p_pktinfo->station_id == 0) */ + /* { */ + /* dbg_print("CCK: LNA_idx = %d, VGA_idx = %d, p_phy_info->rx_pwdb_all = %d\n", */ + /* LNA_idx, VGA_idx, p_phy_info->rx_pwdb_all); */ + /* } */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + p_phy_info->bt_rx_rssi_percentage = PWDB_ALL; + p_phy_info->recv_signal_power = rx_pwr_all; #endif /*(3) Get Signal Quality (EVM)*/ - /*if (pPktinfo->bPacketMatchBSSID)*/ + /*if (p_pktinfo->is_packet_match_bssid)*/ { - u1Byte SQ, SQ_rpt; + u8 SQ, SQ_rpt; - if ((pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->PatchID == RT_CID_819x_Lenovo)) { - SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm, isCCKrate, PWDB_ALL, 0, 0); - } else if (pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest) { + if ((p_dm_odm->support_platform == ODM_WIN) && + (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) + SQ = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, 0, 0); + else if (p_phy_info->rx_pwdb_all > 40 && !p_dm_odm->is_in_hct_test) SQ = 100; - } else { - SQ_rpt = pPhyStaRpt->pwdb_all; + else { + SQ_rpt = p_phy_sta_rpt->pwdb_all; if (SQ_rpt > 64) SQ = 0; @@ -1143,48 +1276,52 @@ odm_RxPhyStatusJaguarSeries_Parsing( SQ = ((64 - SQ_rpt) * 100) / 44; } -/* //DbgPrint("cck SQ = %d\n", SQ);*/ - pPhyInfo->SignalQuality = SQ; - pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ; + /* dbg_print("cck SQ = %d\n", SQ); */ + p_phy_info->signal_quality = SQ; + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = SQ; } for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { if (i == 0) - pPhyInfo->RxMIMOSignalStrength[0] = PWDB_ALL; + p_phy_info->rx_mimo_signal_strength[0] = PWDB_ALL; else - pPhyInfo->RxMIMOSignalStrength[i] = 0; + p_phy_info->rx_mimo_signal_strength[i] = 0; } - } else { + } else { /*is OFDM rate*/ - pDM_FatTable->hw_antsw_occur = pPhyStaRpt->hw_antsw_occur; - - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + p_dm_fat_table->hw_antsw_occur = p_phy_sta_rpt->hw_antsw_occur; + + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; /*(1)Get RSSI for OFDM rate*/ for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { /*2008/01/30 MH we will judge RF RX path now.*/ -/* //DbgPrint("pDM_Odm->RFPathRxEnable = %x\n", pDM_Odm->RFPathRxEnable);*/ - if (pDM_Odm->RFPathRxEnable & BIT(i)) + /* dbg_print("p_dm_odm->rf_path_rx_enable = %x\n", p_dm_odm->rf_path_rx_enable); */ + if (p_dm_odm->rf_path_rx_enable & BIT(i)) rf_rx_num++; -/* //else*/ -/* //continue;*/ + /* else */ + /* continue; */ /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ -/* //if((pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) && (!pDM_Odm->bIsMPChip))*/ - if (i < ODM_RF_PATH_C) - rx_pwr[i] = (pPhyStaRpt->gain_trsw[i] & 0x7F) - 110; - else - rx_pwr[i] = (pPhyStaRpt->gain_trsw_cd[i - 2] & 0x7F) - 110; -/* //else*/ - /*rx_pwr[i] = ((pPhyStaRpt->gain_trsw[i]& 0x3F)*2) - 110; OLD FORMULA*/ + /* if((p_dm_odm->support_ic_type & (ODM_RTL8812|ODM_RTL8821)) && (!p_dm_odm->is_mp_chip)) */ + if (i < ODM_RF_PATH_C) { + rx_pwr[i] = (p_phy_sta_rpt->gain_trsw[i] & 0x7F) - 110; + + if (p_pktinfo->is_to_self) + p_dm_odm->ofdm_agc_idx[i] = p_phy_sta_rpt->gain_trsw[i]; + + } else + rx_pwr[i] = (p_phy_sta_rpt->gain_trsw_cd[i - 2] & 0x7F) - 110; + /* else */ + /*rx_pwr[i] = ((p_phy_sta_rpt->gain_trsw[i]& 0x3F)*2) - 110; OLD FORMULA*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->RxPwr[i] = rx_pwr[i]; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + p_phy_info->rx_pwr[i] = rx_pwr[i]; #endif /* Translate DBM to percentage. */ - RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]); - + RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]); + /*total_rssi += RSSI;*/ /*Get the best two RSSI*/ if (RSSI > best_rssi && RSSI > second_rssi) { @@ -1195,29 +1332,29 @@ odm_RxPhyStatusJaguarSeries_Parsing( /*RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI));*/ - pPhyInfo->RxMIMOSignalStrength[i] = (u1Byte) RSSI; + p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI; /*Get Rx snr value in DB*/ if (i < ODM_RF_PATH_C) - pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = pPhyStaRpt->rxsnr[i] / 2; - else if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) - pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = pPhyStaRpt->csi_current[i - 2] / 2; + p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->rxsnr[i] / 2; + else if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) + p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->csi_current[i - 2] / 2; #if (DM_ODM_SUPPORT_TYPE != ODM_AP) /*(2) CFO_short & CFO_tail*/ if (i < ODM_RF_PATH_C) { - pPhyInfo->Cfo_short[i] = odm_Cfo((pPhyStaRpt->cfosho[i])); - pPhyInfo->Cfo_tail[i] = odm_Cfo((pPhyStaRpt->cfotail[i])); + p_phy_info->cfo_short[i] = odm_cfo((p_phy_sta_rpt->cfosho[i])); + p_phy_info->cfo_tail[i] = odm_cfo((p_phy_sta_rpt->cfotail[i])); } #endif /* Record Signal Strength for next packet */ - if (pPktinfo->bPacketMatchBSSID) { + if (p_pktinfo->is_packet_match_bssid) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if ((pDM_Odm->SupportPlatform == ODM_WIN) && - (pDM_Odm->PatchID == RT_CID_819x_Lenovo)) { + if ((p_dm_odm->support_platform == ODM_WIN) && + (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) { if (i == ODM_RF_PATH_A) - pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm, isCCKrate, PWDB_ALL, i, RSSI); + p_phy_info->signal_quality = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, i, RSSI); } #endif @@ -1227,337 +1364,336 @@ odm_RxPhyStatusJaguarSeries_Parsing( /*(3)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ - if ((pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) && (!pDM_Odm->bIsMPChip)) - rx_pwr_all = (pPhyStaRpt->pwdb_all & 0x7f) - 110; + if ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) && (!p_dm_odm->is_mp_chip)) + rx_pwr_all = (p_phy_sta_rpt->pwdb_all & 0x7f) - 110; else - rx_pwr_all = (((pPhyStaRpt->pwdb_all) >> 1) & 0x7f) - 110; /*OLD FORMULA*/ + rx_pwr_all = (((p_phy_sta_rpt->pwdb_all) >> 1) & 0x7f) - 110; /*OLD FORMULA*/ - PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + PWDB_ALL_BT = PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - pPhyInfo->RxPWDBAll = PWDB_ALL; - /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",pPhyInfo->RxPWDBAll));*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT; - pPhyInfo->RxPower = rx_pwr_all; - pPhyInfo->RecvSignalPower = rx_pwr_all; + p_phy_info->rx_pwdb_all = PWDB_ALL; + /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all));*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + p_phy_info->bt_rx_rssi_percentage = PWDB_ALL_BT; + p_phy_info->rx_power = rx_pwr_all; + p_phy_info->recv_signal_power = rx_pwr_all; #endif - if ((pDM_Odm->SupportPlatform == ODM_WIN) && (pDM_Odm->PatchID == 19)) { + if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 19)) { /*do nothing*/ } else { - /*pMgntInfo->CustomerID != RT_CID_819x_Lenovo*/ + /*p_mgnt_info->customer_id != RT_CID_819X_LENOVO*/ /*(4)EVM of OFDM rate*/ - - if ((pPktinfo->DataRate >= ODM_RATEMCS8) && - (pPktinfo->DataRate <= ODM_RATEMCS15)) - Max_spatial_stream = 2; - else if ((pPktinfo->DataRate >= ODM_RATEVHTSS2MCS0) && - (pPktinfo->DataRate <= ODM_RATEVHTSS2MCS9)) - Max_spatial_stream = 2; - else if ((pPktinfo->DataRate >= ODM_RATEMCS16) && - (pPktinfo->DataRate <= ODM_RATEMCS23)) - Max_spatial_stream = 3; - else if ((pPktinfo->DataRate >= ODM_RATEVHTSS3MCS0) && - (pPktinfo->DataRate <= ODM_RATEVHTSS3MCS9)) - Max_spatial_stream = 3; + + if ((p_pktinfo->data_rate >= ODM_RATEMCS8) && + (p_pktinfo->data_rate <= ODM_RATEMCS15)) + max_spatial_stream = 2; + else if ((p_pktinfo->data_rate >= ODM_RATEVHTSS2MCS0) && + (p_pktinfo->data_rate <= ODM_RATEVHTSS2MCS9)) + max_spatial_stream = 2; + else if ((p_pktinfo->data_rate >= ODM_RATEMCS16) && + (p_pktinfo->data_rate <= ODM_RATEMCS23)) + max_spatial_stream = 3; + else if ((p_pktinfo->data_rate >= ODM_RATEVHTSS3MCS0) && + (p_pktinfo->data_rate <= ODM_RATEVHTSS3MCS9)) + max_spatial_stream = 3; else - Max_spatial_stream = 1; + max_spatial_stream = 1; - /*if (pPktinfo->bPacketMatchBSSID) */ + /*if (p_pktinfo->is_packet_match_bssid) */ { - /*DbgPrint("pPktinfo->DataRate = %d\n", pPktinfo->DataRate);*/ + /*dbg_print("p_pktinfo->data_rate = %d\n", p_pktinfo->data_rate);*/ - for (i = 0; i < Max_spatial_stream; i++) { + for (i = 0; i < max_spatial_stream; i++) { /*Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment*/ /*fill most significant bit to "zero" when doing shifting operation which may change a negative*/ /*value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.*/ - if (pPktinfo->DataRate >= ODM_RATE6M && pPktinfo->DataRate <= ODM_RATE54M) { + if (p_pktinfo->data_rate >= ODM_RATE6M && p_pktinfo->data_rate <= ODM_RATE54M) { if (i == ODM_RF_PATH_A) { - EVM = odm_EVMdbToPercentage((pPhyStaRpt->sigevm)); /*dbm*/ + EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->sigevm)); /*dbm*/ EVM += 20; if (EVM > 100) EVM = 100; } } else { if (i < ODM_RF_PATH_C) { - if (pPhyStaRpt->rxevm[i] == -128) - pPhyStaRpt->rxevm[i] = -25; - EVM = odm_EVMdbToPercentage((pPhyStaRpt->rxevm[i])); /*dbm*/ + if (p_phy_sta_rpt->rxevm[i] == -128) + p_phy_sta_rpt->rxevm[i] = -25; + EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->rxevm[i])); /*dbm*/ } else { - if (pPhyStaRpt->rxevm_cd[i - 2] == -128){ - pPhyStaRpt->rxevm_cd[i - 2] = -25; - } - EVM = odm_EVMdbToPercentage((pPhyStaRpt->rxevm_cd[i - 2])); /*dbm*/ + if (p_phy_sta_rpt->rxevm_cd[i - 2] == -128) + p_phy_sta_rpt->rxevm_cd[i - 2] = -25; + EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->rxevm_cd[i - 2])); /*dbm*/ } } if (i < ODM_RF_PATH_C) - EVMdbm = odm_EVMdbm_JaguarSeries(pPhyStaRpt->rxevm[i]); + evm_dbm = odm_evm_dbm_jaguar_series(p_phy_sta_rpt->rxevm[i]); else - EVMdbm = odm_EVMdbm_JaguarSeries(pPhyStaRpt->rxevm_cd[i - 2]); + evm_dbm = odm_evm_dbm_jaguar_series(p_phy_sta_rpt->rxevm_cd[i - 2]); /*RT_DISP(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",*/ - /*pPktinfo->DataRate, pPhyStaRpt->rxevm[i], "%", EVM));*/ + /*p_pktinfo->data_rate, p_phy_sta_rpt->rxevm[i], "%", EVM));*/ { - if (i == ODM_RF_PATH_A) { + if (i == ODM_RF_PATH_A) { /*Fill value in RFD, Get the first spatial stream only*/ - pPhyInfo->SignalQuality = EVM; + p_phy_info->signal_quality = EVM; } - pPhyInfo->RxMIMOSignalQuality[i] = EVM; + p_phy_info->rx_mimo_signal_quality[i] = EVM; #if (DM_ODM_SUPPORT_TYPE != ODM_AP) - pPhyInfo->RxMIMOEVMdbm[i] = EVMdbm; + p_phy_info->rx_mimo_evm_dbm[i] = evm_dbm; #endif } } } } - ODM_ParsingCFO(pDM_Odm, pPktinfo, pPhyStaRpt->cfotail); + num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); + odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->cfotail, num_ss); } -/* //DbgPrint("isCCKrate= %d, pPhyInfo->SignalStrength=%d % PWDB_AL=%d rf_rx_num=%d\n", isCCKrate, pPhyInfo->SignalStrength, PWDB_ALL, rf_rx_num);*/ + /* dbg_print("is_cck_rate= %d, p_phy_info->signal_strength=%d % PWDB_AL=%d rf_rx_num=%d\n", is_cck_rate, p_phy_info->signal_strength, PWDB_ALL, rf_rx_num); */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) /*UI BSS List signal strength(in percentage), make it good looking, from 0~100.*/ /*It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().*/ - if (isCCKrate) { + if (is_cck_rate) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ - pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, PWDB_ALL, FALSE, TRUE); + p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, PWDB_ALL, false, true); #else - pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/*PWDB_ALL;*/ + p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, PWDB_ALL));/*PWDB_ALL;*/ #endif - } else { + } else { if (rf_rx_num != 0) { /* 2015/01 Sean, use the best two RSSI only, suggested by Ynlin and ChenYu.*/ if (rf_rx_num == 1) avg_rssi = best_rssi; else - avg_rssi = (best_rssi + second_rssi)/2; + avg_rssi = (best_rssi + second_rssi) / 2; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ - pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, avg_rssi, FALSE, FALSE); + /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ + p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, avg_rssi, false, false); #else - pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, avg_rssi)); + p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, avg_rssi)); #endif } } #endif - pDM_Odm->RxPWDBAve = pDM_Odm->RxPWDBAve + pPhyInfo->RxPWDBAll; - - pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->antidx_anta; - pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->antidx_antb; - pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antidx_antc; - pDM_Odm->DM_FatTable.antsel_rx_keep_3 = pPhyStaRpt->antidx_antd; - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antidx_anta = ((%d)), MatchBSSID = ((%d))\n", pPktinfo->StationID, pPhyStaRpt->antidx_anta, pPktinfo->bPacketMatchBSSID));*/ - - -/* DbgPrint("pPhyStaRpt->antidx_anta = %d, pPhyStaRpt->antidx_antb = %d\n",*/ -/* pPhyStaRpt->antidx_anta, pPhyStaRpt->antidx_antb);*/ -/* DbgPrint("----------------------------\n");*/ -/* DbgPrint("pPktinfo->StationID=%d, pPktinfo->DataRate=0x%x\n",pPktinfo->StationID, pPktinfo->DataRate);*/ -/* DbgPrint("pPhyStaRpt->r_RFMOD = %d\n", pPhyStaRpt->r_RFMOD);*/ -/* DbgPrint("pPhyStaRpt->gain_trsw[0]=0x%x, pPhyStaRpt->gain_trsw[1]=0x%x\n",*/ -/* pPhyStaRpt->gain_trsw[0],pPhyStaRpt->gain_trsw[1]);*/ -/* DbgPrint("pPhyStaRpt->gain_trsw[2]=0x%x, pPhyStaRpt->gain_trsw[3]=0x%x\n",*/ -/* pPhyStaRpt->gain_trsw_cd[0],pPhyStaRpt->gain_trsw_cd[1]);*/ -/* DbgPrint("pPhyStaRpt->pwdb_all = 0x%x, pPhyInfo->RxPWDBAll = %d\n", pPhyStaRpt->pwdb_all, pPhyInfo->RxPWDBAll);*/ -/* DbgPrint("pPhyStaRpt->cfotail[i] = 0x%x, pPhyStaRpt->CFO_tail[i] = 0x%x\n", pPhyStaRpt->cfotail[0], pPhyStaRpt->cfotail[1]);*/ -/* DbgPrint("pPhyStaRpt->rxevm[0] = %d, pPhyStaRpt->rxevm[1] = %d\n", pPhyStaRpt->rxevm[0], pPhyStaRpt->rxevm[1]);*/ -/* DbgPrint("pPhyStaRpt->rxevm[2] = %d, pPhyStaRpt->rxevm[3] = %d\n", pPhyStaRpt->rxevm_cd[0], pPhyStaRpt->rxevm_cd[1]);*/ -/* DbgPrint("pPhyInfo->RxMIMOSignalStrength[0]=%d, pPhyInfo->RxMIMOSignalStrength[1]=%d, RxPWDBAll=%d\n",*/ -/* pPhyInfo->RxMIMOSignalStrength[0], pPhyInfo->RxMIMOSignalStrength[1], pPhyInfo->RxPWDBAll);*/ -/* DbgPrint("pPhyInfo->RxMIMOSignalStrength[2]=%d, pPhyInfo->RxMIMOSignalStrength[3]=%d\n",*/ -/* pPhyInfo->RxMIMOSignalStrength[2], pPhyInfo->RxMIMOSignalStrength[3]);*/ -/* DbgPrint("ppPhyInfo->RxMIMOSignalQuality[0]=%d, pPhyInfo->RxMIMOSignalQuality[1]=%d\n",*/ -/* pPhyInfo->RxMIMOSignalQuality[0], pPhyInfo->RxMIMOSignalQuality[1]);*/ -/* DbgPrint("ppPhyInfo->RxMIMOSignalQuality[2]=%d, pPhyInfo->RxMIMOSignalQuality[3]=%d\n",*/ -/* pPhyInfo->RxMIMOSignalQuality[2], pPhyInfo->RxMIMOSignalQuality[3]);*/ + p_dm_odm->rx_pwdb_ave = p_dm_odm->rx_pwdb_ave + p_phy_info->rx_pwdb_all; + + p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_anta; + p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_antb; + p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_antc; + p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_antd; + + if (p_pktinfo->is_packet_match_bssid) { + phydm_avg_rssi_for_ss(p_dm_odm, p_phy_info, p_pktinfo); + phydm_rx_statistic_cal(p_dm_odm, p_phy_status, p_pktinfo); + } + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antidx_anta = ((%d)), MatchBSSID = ((%d))\n", p_pktinfo->station_id, p_phy_sta_rpt->antidx_anta, p_pktinfo->is_packet_match_bssid));*/ + + + /* dbg_print("p_phy_sta_rpt->antidx_anta = %d, p_phy_sta_rpt->antidx_antb = %d\n",*/ + /* p_phy_sta_rpt->antidx_anta, p_phy_sta_rpt->antidx_antb);*/ + /* dbg_print("----------------------------\n");*/ + /* dbg_print("p_pktinfo->station_id=%d, p_pktinfo->data_rate=0x%x\n",p_pktinfo->station_id, p_pktinfo->data_rate);*/ + /* dbg_print("p_phy_sta_rpt->r_RFMOD = %d\n", p_phy_sta_rpt->r_RFMOD);*/ + /* dbg_print("p_phy_sta_rpt->gain_trsw[0]=0x%x, p_phy_sta_rpt->gain_trsw[1]=0x%x\n",*/ + /* p_phy_sta_rpt->gain_trsw[0],p_phy_sta_rpt->gain_trsw[1]);*/ + /* dbg_print("p_phy_sta_rpt->gain_trsw[2]=0x%x, p_phy_sta_rpt->gain_trsw[3]=0x%x\n",*/ + /* p_phy_sta_rpt->gain_trsw_cd[0],p_phy_sta_rpt->gain_trsw_cd[1]);*/ + /* dbg_print("p_phy_sta_rpt->pwdb_all = 0x%x, p_phy_info->rx_pwdb_all = %d\n", p_phy_sta_rpt->pwdb_all, p_phy_info->rx_pwdb_all);*/ + /* dbg_print("p_phy_sta_rpt->cfotail[i] = 0x%x, p_phy_sta_rpt->CFO_tail[i] = 0x%x\n", p_phy_sta_rpt->cfotail[0], p_phy_sta_rpt->cfotail[1]);*/ + /* dbg_print("p_phy_sta_rpt->rxevm[0] = %d, p_phy_sta_rpt->rxevm[1] = %d\n", p_phy_sta_rpt->rxevm[0], p_phy_sta_rpt->rxevm[1]);*/ + /* dbg_print("p_phy_sta_rpt->rxevm[2] = %d, p_phy_sta_rpt->rxevm[3] = %d\n", p_phy_sta_rpt->rxevm_cd[0], p_phy_sta_rpt->rxevm_cd[1]);*/ + /* dbg_print("p_phy_info->rx_mimo_signal_strength[0]=%d, p_phy_info->rx_mimo_signal_strength[1]=%d, rx_pwdb_all=%d\n",*/ + /* p_phy_info->rx_mimo_signal_strength[0], p_phy_info->rx_mimo_signal_strength[1], p_phy_info->rx_pwdb_all);*/ + /* dbg_print("p_phy_info->rx_mimo_signal_strength[2]=%d, p_phy_info->rx_mimo_signal_strength[3]=%d\n",*/ + /* p_phy_info->rx_mimo_signal_strength[2], p_phy_info->rx_mimo_signal_strength[3]);*/ + /* dbg_print("ppPhyInfo->rx_mimo_signal_quality[0]=%d, p_phy_info->rx_mimo_signal_quality[1]=%d\n",*/ + /* p_phy_info->rx_mimo_signal_quality[0], p_phy_info->rx_mimo_signal_quality[1]);*/ + /* dbg_print("ppPhyInfo->rx_mimo_signal_quality[2]=%d, p_phy_info->rx_mimo_signal_quality[3]=%d\n",*/ + /* p_phy_info->rx_mimo_signal_quality[2], p_phy_info->rx_mimo_signal_quality[3]);*/ } #endif -VOID +void phydm_reset_rssi_for_dm( - IN OUT PDM_ODM_T pDM_Odm, - IN u1Byte station_id - ) + struct PHY_DM_STRUCT *p_dm_odm, + u8 station_id +) { - PSTA_INFO_T pEntry; - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - #endif + struct sta_info *p_entry; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); +#endif - pEntry = pDM_Odm->pODM_StaInfo[station_id]; + p_entry = p_dm_odm->p_odm_sta_info[station_id]; - if (!IS_STA_VALID(pEntry)) { + if (!IS_STA_VALID(p_entry)) { /**/ return; } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("Reset RSSI for macid = (( %d ))\n", station_id)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("Reset RSSI for macid = (( %d ))\n", station_id)); - - pEntry->rssi_stat.UndecoratedSmoothedCCK = -1; - pEntry->rssi_stat.UndecoratedSmoothedOFDM = -1; - pEntry->rssi_stat.UndecoratedSmoothedPWDB = -1; - pEntry->rssi_stat.OFDM_pkt = 0; - pEntry->rssi_stat.CCK_pkt = 0; - pEntry->rssi_stat.CCK_sum_power = 0; - pEntry->rssi_stat.bsend_rssi = RA_RSSI_STATE_INIT; - pEntry->rssi_stat.PacketMap = 0; - pEntry->rssi_stat.ValidBit = 0; - - /*in WIN Driver: sta_ID==0 -> pEntry==NULL -> default port HAL_Data*/ - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - pEntry->bUsed = 0; - if (station_id == 0) { - - pHalData->UndecoratedSmoothedPWDB = -1; + + p_entry->rssi_stat.undecorated_smoothed_cck = -1; + p_entry->rssi_stat.undecorated_smoothed_ofdm = -1; + p_entry->rssi_stat.undecorated_smoothed_pwdb = -1; + p_entry->rssi_stat.ofdm_pkt = 0; + p_entry->rssi_stat.cck_pkt = 0; + p_entry->rssi_stat.cck_sum_power = 0; + p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT; + p_entry->rssi_stat.packet_map = 0; + p_entry->rssi_stat.valid_bit = 0; + + /*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + p_entry->bUsed = 0; + if (station_id == 0) { + + p_hal_data->UndecoratedSmoothedPWDB = -1; /**/ } - #endif +#endif } -VOID -odm_Init_RSSIForDM( - IN OUT PDM_ODM_T pDM_Odm - ) +void +odm_init_rssi_for_dm( + struct PHY_DM_STRUCT *p_dm_odm +) { } -VOID -odm_Process_RSSIForDM( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN PODM_PACKET_INFO_T pPktinfo - ) +void +odm_process_rssi_for_dm( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + struct _odm_per_pkt_info_ *p_pktinfo +) { - - s4Byte UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK, UndecoratedSmoothedOFDM, RSSI_Ave, CCK_pkt; - u1Byte i, isCCKrate=0; - u1Byte RSSI_max, RSSI_min; - u4Byte Weighting=0; - u1Byte send_rssi_2_fw = 0; - PSTA_INFO_T pEntry; - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - #endif - if (pPktinfo->StationID >= ODM_ASSOCIATE_ENTRY_NUM) + s32 undecorated_smoothed_pwdb, undecorated_smoothed_cck, undecorated_smoothed_ofdm, rssi_ave; + u8 i, is_cck_rate = 0; + u8 RSSI_max, RSSI_min; + u32 weighting = 0; + u8 send_rssi_2_fw = 0; + struct sta_info *p_entry; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); +#endif + + if (p_pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) return; - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(pDM_Odm, pPhyInfo, pPktinfo); - #endif +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(p_dm_odm, p_phy_info, p_pktinfo); +#endif + + /* */ + /* 2012/05/30 MH/Luke.Lee Add some description */ + /* In windows driver: AP/IBSS mode STA */ + /* */ + /* if (p_dm_odm->support_platform == ODM_WIN) */ + /* { */ + /* p_entry = p_dm_odm->p_odm_sta_info[p_dm_odm->pAidMap[p_pktinfo->station_id-1]]; */ + /* } */ + /* else */ + p_entry = p_dm_odm->p_odm_sta_info[p_pktinfo->station_id]; - // - // 2012/05/30 MH/Luke.Lee Add some description - // In windows driver: AP/IBSS mode STA - // - //if (pDM_Odm->SupportPlatform == ODM_WIN) - //{ - // pEntry = pDM_Odm->pODM_StaInfo[pDM_Odm->pAidMap[pPktinfo->StationID-1]]; - //} - //else - pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID]; - - if (!IS_STA_VALID(pEntry)) { + if (!IS_STA_VALID(p_entry)) { return; /**/ } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - if ((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) && - (pDM_FatTable->enable_ctrl_frame_antdiv) - ) - { - if (pPktinfo->bPacketMatchBSSID) - pDM_Odm->data_frame_num++; - - if ((pDM_FatTable->use_ctrl_frame_antdiv)) { - if (!pPktinfo->bToSelf)/*data frame + CTRL frame*/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) && + (p_dm_fat_table->enable_ctrl_frame_antdiv) + ) { + if (p_pktinfo->is_packet_match_bssid) + p_dm_odm->data_frame_num++; + + if ((p_dm_fat_table->use_ctrl_frame_antdiv)) { + if (!p_pktinfo->is_to_self)/*data frame + CTRL frame*/ return; } else { - if ((!pPktinfo->bPacketMatchBSSID))/*data frame only*/ + if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/ return; - } + } } else #endif { - if ((!pPktinfo->bPacketMatchBSSID))/*data frame only*/ + if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/ return; } - if(pPktinfo->bPacketBeacon) - pDM_Odm->PhyDbgInfo.NumQryBeaconPkt++; - - isCCKrate = (pPktinfo->DataRate <= ODM_RATE11M )?TRUE :FALSE; - pDM_Odm->RxRate = pPktinfo->DataRate; + if (p_pktinfo->is_packet_beacon) + p_dm_odm->phy_dbg_info.num_qry_beacon_pkt++; - //--------------Statistic for antenna/path diversity------------------ - if(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) - { - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_Process_RSSIForAntDiv(pDM_Odm,pPhyInfo,pPktinfo); - #endif - } - #if(defined(CONFIG_PATH_DIVERSITY)) - else if(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV) - { - phydm_process_rssi_for_path_div(pDM_Odm,pPhyInfo,pPktinfo); + is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false; + p_dm_odm->rx_rate = p_pktinfo->data_rate; + + /* --------------Statistic for antenna/path diversity------------------ */ + if (p_dm_odm->support_ability & ODM_BB_ANT_DIV) { +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + odm_process_rssi_for_ant_div(p_dm_odm, p_phy_info, p_pktinfo); +#endif } - #endif - //-----------------Smart Antenna Debug Message------------------// - - UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK; - UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM; - UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; - - if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) - { +#if (defined(CONFIG_PATH_DIVERSITY)) + else if (p_dm_odm->support_ability & ODM_BB_PATH_DIV) + phydm_process_rssi_for_path_div(p_dm_odm, p_phy_info, p_pktinfo); +#endif + /* -----------------Smart Antenna Debug Message------------------ */ - if(!isCCKrate)//ofdm rate - { + undecorated_smoothed_cck = p_entry->rssi_stat.undecorated_smoothed_cck; + undecorated_smoothed_ofdm = p_entry->rssi_stat.undecorated_smoothed_ofdm; + undecorated_smoothed_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; + + if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_beacon) { + + if (!is_cck_rate) { /* ofdm rate */ #if (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B)) { - u1Byte RX_count = 0; - u4Byte RSSI_linear = 0; + if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) { + u8 RX_count = 0; + u32 RSSI_linear = 0; - if (pDM_Odm->RXAntStatus & ODM_RF_A) { - pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + if (p_dm_odm->rx_ant_status & ODM_RF_A) { + p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; RX_count++; - RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]); + RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]); } else - pDM_Odm->RSSI_A = 0; + p_dm_odm->RSSI_A = 0; - if (pDM_Odm->RXAntStatus & ODM_RF_B) { - pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + if (p_dm_odm->rx_ant_status & ODM_RF_B) { + p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; RX_count++; - RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]); + RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]); } else - pDM_Odm->RSSI_B = 0; - - if (pDM_Odm->RXAntStatus & ODM_RF_C) { - pDM_Odm->RSSI_C = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_C]; + p_dm_odm->RSSI_B = 0; + + if (p_dm_odm->rx_ant_status & ODM_RF_C) { + p_dm_odm->RSSI_C = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C]; RX_count++; - RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_C]); + RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C]); } else - pDM_Odm->RSSI_C = 0; + p_dm_odm->RSSI_C = 0; - if (pDM_Odm->RXAntStatus & ODM_RF_D) { - pDM_Odm->RSSI_D = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_D]; + if (p_dm_odm->rx_ant_status & ODM_RF_D) { + p_dm_odm->RSSI_D = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D]; RX_count++; - RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_D]); + RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D]); } else - pDM_Odm->RSSI_D = 0; + p_dm_odm->RSSI_D = 0; /* Calculate average RSSI */ switch (RX_count) { @@ -1570,1555 +1706,1736 @@ odm_Process_RSSIForDM( case 4: RSSI_linear = (RSSI_linear >> 2); break; - } - RSSI_Ave = odm_ConvertTo_dB(RSSI_linear); + } + rssi_ave = odm_convert_to_db(RSSI_linear); } else #endif { - if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0) { - RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; - pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; - pDM_Odm->RSSI_B = 0; + if (p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B] == 0) { + rssi_ave = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; + p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; + p_dm_odm->RSSI_B = 0; } else { - /*DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d\n",*/ - /*pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]);*/ - pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; - pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; - - if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A] > pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]) { - RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; - RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + /*dbg_print("p_rfd->status.rx_mimo_signal_strength[0] = %d, p_rfd->status.rx_mimo_signal_strength[1] = %d\n",*/ + /*p_rfd->status.rx_mimo_signal_strength[0], p_rfd->status.rx_mimo_signal_strength[1]);*/ + p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; + p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; + + if (p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A] > p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]) { + RSSI_max = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; + RSSI_min = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; } else { - RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; - RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + RSSI_max = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; + RSSI_min = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; } if ((RSSI_max - RSSI_min) < 3) - RSSI_Ave = RSSI_max; + rssi_ave = RSSI_max; else if ((RSSI_max - RSSI_min) < 6) - RSSI_Ave = RSSI_max - 1; + rssi_ave = RSSI_max - 1; else if ((RSSI_max - RSSI_min) < 10) - RSSI_Ave = RSSI_max - 2; + rssi_ave = RSSI_max - 2; else - RSSI_Ave = RSSI_max - 3; + rssi_ave = RSSI_max - 3; } } - - //1 Process OFDM RSSI - if(UndecoratedSmoothedOFDM <= 0) // initialize - { - UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_INIT: (( %d ))\n", UndecoratedSmoothedOFDM)); - } - else - { - if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedOFDM) - { - UndecoratedSmoothedOFDM = - ( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) + - (RSSI_Ave)) /(Rx_Smooth_Factor); - UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM + 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_1: (( %d ))\n", UndecoratedSmoothedOFDM)); - } - else - { - UndecoratedSmoothedOFDM = - ( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) + - (RSSI_Ave)) /(Rx_Smooth_Factor); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_2: (( %d ))\n", UndecoratedSmoothedOFDM)); + + /* 1 Process OFDM RSSI */ + if (undecorated_smoothed_ofdm <= 0) { /* initialize */ + undecorated_smoothed_ofdm = p_phy_info->rx_pwdb_all; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_INIT: (( %d ))\n", undecorated_smoothed_ofdm)); + } else { + if (p_phy_info->rx_pwdb_all > (u32)undecorated_smoothed_ofdm) { + undecorated_smoothed_ofdm = + (((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) + + (rssi_ave)) / (RX_SMOOTH_FACTOR); + undecorated_smoothed_ofdm = undecorated_smoothed_ofdm + 1; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_1: (( %d ))\n", undecorated_smoothed_ofdm)); + } else { + undecorated_smoothed_ofdm = + (((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) + + (rssi_ave)) / (RX_SMOOTH_FACTOR); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_2: (( %d ))\n", undecorated_smoothed_ofdm)); } - } - if (pEntry->rssi_stat.OFDM_pkt != 64) { + } + if (p_entry->rssi_stat.ofdm_pkt != 64) { i = 63; - pEntry->rssi_stat.OFDM_pkt -= (u1Byte)(((pEntry->rssi_stat.PacketMap>>i)&BIT0)-1); + p_entry->rssi_stat.ofdm_pkt -= (u8)(((p_entry->rssi_stat.packet_map >> i) & BIT(0)) - 1); } - pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0; - - } - else - { - RSSI_Ave = pPhyInfo->RxPWDBAll; - pDM_Odm->RSSI_A = (u1Byte) pPhyInfo->RxPWDBAll; - pDM_Odm->RSSI_B = 0xFF; - pDM_Odm->RSSI_C = 0xFF; - pDM_Odm->RSSI_D = 0xFF; + p_entry->rssi_stat.packet_map = (p_entry->rssi_stat.packet_map << 1) | BIT(0); - if (pEntry->rssi_stat.CCK_pkt <= 63) - pEntry->rssi_stat.CCK_pkt++; - - //1 Process CCK RSSI - if(UndecoratedSmoothedCCK <= 0) // initialize - { - UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll; - pEntry->rssi_stat.CCK_sum_power = (u2Byte)pPhyInfo->RxPWDBAll ; /*reset*/ - pEntry->rssi_stat.CCK_pkt = 1; /*reset*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_INIT: (( %d ))\n", UndecoratedSmoothedCCK)); - } else if (pEntry->rssi_stat.CCK_pkt <= CCK_RSSI_INIT_COUNT) { - - pEntry->rssi_stat.CCK_sum_power = pEntry->rssi_stat.CCK_sum_power + (u2Byte)pPhyInfo->RxPWDBAll; - UndecoratedSmoothedCCK = pEntry->rssi_stat.CCK_sum_power/pEntry->rssi_stat.CCK_pkt; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_0: (( %d )), SumPow = (( %d )), CCK_pkt = (( %d ))\n", - UndecoratedSmoothedCCK, pEntry->rssi_stat.CCK_sum_power, pEntry->rssi_stat.CCK_pkt)); - } - else - { - if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedCCK) - { - UndecoratedSmoothedCCK = - ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + - (pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor); - UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_1: (( %d ))\n", UndecoratedSmoothedCCK)); - } - else - { - UndecoratedSmoothedCCK = - ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + - (pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_2: (( %d ))\n", UndecoratedSmoothedCCK)); + } else { + rssi_ave = p_phy_info->rx_pwdb_all; + p_dm_odm->RSSI_A = (u8) p_phy_info->rx_pwdb_all; + p_dm_odm->RSSI_B = 0xFF; + p_dm_odm->RSSI_C = 0xFF; + p_dm_odm->RSSI_D = 0xFF; + + if (p_entry->rssi_stat.cck_pkt <= 63) + p_entry->rssi_stat.cck_pkt++; + + /* 1 Process CCK RSSI */ + if (undecorated_smoothed_cck <= 0) { /* initialize */ + undecorated_smoothed_cck = p_phy_info->rx_pwdb_all; + p_entry->rssi_stat.cck_sum_power = (u16)p_phy_info->rx_pwdb_all ; /*reset*/ + p_entry->rssi_stat.cck_pkt = 1; /*reset*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_INIT: (( %d ))\n", undecorated_smoothed_cck)); + } else if (p_entry->rssi_stat.cck_pkt <= CCK_RSSI_INIT_COUNT) { + + p_entry->rssi_stat.cck_sum_power = p_entry->rssi_stat.cck_sum_power + (u16)p_phy_info->rx_pwdb_all; + undecorated_smoothed_cck = p_entry->rssi_stat.cck_sum_power / p_entry->rssi_stat.cck_pkt; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_0: (( %d )), SumPow = (( %d )), cck_pkt = (( %d ))\n", + undecorated_smoothed_cck, p_entry->rssi_stat.cck_sum_power, p_entry->rssi_stat.cck_pkt)); + } else { + if (p_phy_info->rx_pwdb_all > (u32)undecorated_smoothed_cck) { + undecorated_smoothed_cck = + (((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) + + (p_phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); + undecorated_smoothed_cck = undecorated_smoothed_cck + 1; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_1: (( %d ))\n", undecorated_smoothed_cck)); + } else { + undecorated_smoothed_cck = + (((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) + + (p_phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_2: (( %d ))\n", undecorated_smoothed_cck)); } } i = 63; - pEntry->rssi_stat.OFDM_pkt -= (u1Byte)((pEntry->rssi_stat.PacketMap>>i)&BIT0); - pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap<<1; + p_entry->rssi_stat.ofdm_pkt -= (u8)((p_entry->rssi_stat.packet_map >> i) & BIT(0)); + p_entry->rssi_stat.packet_map = p_entry->rssi_stat.packet_map << 1; } - //if(pEntry) + /* if(p_entry) */ { - //2011.07.28 LukeLee: modified to prevent unstable CCK RSSI - if (pEntry->rssi_stat.OFDM_pkt == 64) { /* speed up when all packets are OFDM*/ - UndecoratedSmoothedPWDB = UndecoratedSmoothedOFDM; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_0[%d] = (( %d ))\n", pPktinfo->StationID, UndecoratedSmoothedCCK)); + /* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */ + if (p_entry->rssi_stat.ofdm_pkt == 64) { /* speed up when all packets are OFDM*/ + undecorated_smoothed_pwdb = undecorated_smoothed_ofdm; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_0[%d] = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck)); } else { - if (pEntry->rssi_stat.ValidBit < 64) - pEntry->rssi_stat.ValidBit++; + if (p_entry->rssi_stat.valid_bit < 64) + p_entry->rssi_stat.valid_bit++; - if (pEntry->rssi_stat.ValidBit == 64) { - Weighting = ((pEntry->rssi_stat.OFDM_pkt) > 4) ? 64 : (pEntry->rssi_stat.OFDM_pkt<<4); - UndecoratedSmoothedPWDB = (Weighting*UndecoratedSmoothedOFDM+(64-Weighting)*UndecoratedSmoothedCCK)>>6; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_1[%d] = (( %d )), W = (( %d ))\n", pPktinfo->StationID, UndecoratedSmoothedCCK, Weighting)); + if (p_entry->rssi_stat.valid_bit == 64) { + weighting = ((p_entry->rssi_stat.ofdm_pkt) > 4) ? 64 : (p_entry->rssi_stat.ofdm_pkt << 4); + undecorated_smoothed_pwdb = (weighting * undecorated_smoothed_ofdm + (64 - weighting) * undecorated_smoothed_cck) >> 6; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_1[%d] = (( %d )), W = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck, weighting)); } else { - if (pEntry->rssi_stat.ValidBit != 0) - UndecoratedSmoothedPWDB = (pEntry->rssi_stat.OFDM_pkt*UndecoratedSmoothedOFDM+(pEntry->rssi_stat.ValidBit-pEntry->rssi_stat.OFDM_pkt)*UndecoratedSmoothedCCK)/pEntry->rssi_stat.ValidBit; + if (p_entry->rssi_stat.valid_bit != 0) + undecorated_smoothed_pwdb = (p_entry->rssi_stat.ofdm_pkt * undecorated_smoothed_ofdm + (p_entry->rssi_stat.valid_bit - p_entry->rssi_stat.ofdm_pkt) * undecorated_smoothed_cck) / p_entry->rssi_stat.valid_bit; else - UndecoratedSmoothedPWDB = 0; + undecorated_smoothed_pwdb = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_2[%d] = (( %d )), OFDM_pkt = (( %d )), Valid_Bit = (( %d ))\n", pPktinfo->StationID, UndecoratedSmoothedCCK, pEntry->rssi_stat.OFDM_pkt, pEntry->rssi_stat.ValidBit)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_2[%d] = (( %d )), ofdm_pkt = (( %d )), Valid_Bit = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck, p_entry->rssi_stat.ofdm_pkt, p_entry->rssi_stat.valid_bit)); } } - - - if ((pEntry->rssi_stat.OFDM_pkt >= 1 || pEntry->rssi_stat.CCK_pkt >= 5) && (pEntry->rssi_stat.bsend_rssi == RA_RSSI_STATE_INIT)) { - + + + if ((p_entry->rssi_stat.ofdm_pkt >= 1 || p_entry->rssi_stat.cck_pkt >= 5) && (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_INIT)) { + send_rssi_2_fw = 1; - pEntry->rssi_stat.bsend_rssi = RA_RSSI_STATE_SEND; + p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_SEND; } - pEntry->rssi_stat.UndecoratedSmoothedCCK = UndecoratedSmoothedCCK; - pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM; - pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; + p_entry->rssi_stat.undecorated_smoothed_cck = undecorated_smoothed_cck; + p_entry->rssi_stat.undecorated_smoothed_ofdm = undecorated_smoothed_ofdm; + p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb; - - if (send_rssi_2_fw) /* Trigger init rate by RSSI */ { - - if (pEntry->rssi_stat.OFDM_pkt != 0) - pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedOFDM; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("[Send to FW] PWDB = (( %d )), OFDM_pkt = (( %d )), CCK_pkt = (( %d ))\n", - UndecoratedSmoothedPWDB, pEntry->rssi_stat.OFDM_pkt, pEntry->rssi_stat.CCK_pkt)); - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - phydm_ra_rssi_rpt_wk(pDM_Odm); - #endif + if (send_rssi_2_fw) { /* Trigger init rate by RSSI */ + + if (p_entry->rssi_stat.ofdm_pkt != 0) + p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_ofdm; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("[Send to FW] PWDB = (( %d )), ofdm_pkt = (( %d )), cck_pkt = (( %d ))\n", + undecorated_smoothed_pwdb, p_entry->rssi_stat.ofdm_pkt, p_entry->rssi_stat.cck_pkt)); + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#ifndef DM_ODM_CE_MAC80211 + phydm_ra_rssi_rpt_wk(p_dm_odm); +#endif +#endif } - - /*in WIN Driver: sta_ID==0 -> pEntry==NULL -> default port HAL_Data*/ - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - - if (pPktinfo->StationID == 0) { - /**/ - pHalData->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; - } - #endif - - //DbgPrint("OFDM_pkt=%d, Weighting=%d\n", OFDM_pkt, Weighting); - //DbgPrint("UndecoratedSmoothedOFDM=%d, UndecoratedSmoothedPWDB=%d, UndecoratedSmoothedCCK=%d\n", - // UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK); - + + /*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + + if (p_pktinfo->station_id == 0) { + /**/ + p_hal_data->UndecoratedSmoothedPWDB = undecorated_smoothed_pwdb; + } +#endif + + /* dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt, weighting); */ + /* dbg_print("undecorated_smoothed_ofdm=%d, undecorated_smoothed_pwdb=%d, undecorated_smoothed_cck=%d\n", */ + /* undecorated_smoothed_ofdm, undecorated_smoothed_pwdb, undecorated_smoothed_cck); */ + } - + } } -#if(ODM_IC_11N_SERIES_SUPPORT ==1) -// -// Endianness before calling this API -// -VOID -ODM_PhyStatusQuery_92CSeries( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo - ) +#if (ODM_IC_11N_SERIES_SUPPORT == 1) +/* + * Endianness before calling this API + * */ +void +odm_phy_status_query_92c_series( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo +) { - odm_RxPhyStatus92CSeries_Parsing(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo); - odm_Process_RSSIForDM(pDM_Odm, pPhyInfo, pPktinfo); + odm_rx_phy_status92c_series_parsing(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); + odm_process_rssi_for_dm(p_dm_odm, p_phy_info, p_pktinfo); } #endif -// -// Endianness before calling this API -// +/* + * Endianness before calling this API + * */ #if ODM_IC_11AC_SERIES_SUPPORT -VOID -ODM_PhyStatusQuery_JaguarSeries( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo - ) +void +odm_phy_status_query_jaguar_series( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo +) { - odm_RxPhyStatusJaguarSeries_Parsing(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo); - odm_Process_RSSIForDM(pDM_Odm, pPhyInfo, pPktinfo); - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /*phydm_sbd_check(pDM_Odm);*/ - #endif + odm_rx_phy_status_jaguar_series_parsing(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); + odm_process_rssi_for_dm(p_dm_odm, p_phy_info, p_pktinfo); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /*phydm_sbd_check(p_dm_odm);*/ +#endif } #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID +void phydm_normal_driver_rx_sniffer( - IN OUT PDM_ODM_T pDM_Odm, - IN pu1Byte pDesc, - IN PRT_RFD_STATUS pRtRfdStatus, - IN pu1Byte pDrvInfo, - IN u1Byte PHYStatus - ) + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_desc, + PRT_RFD_STATUS p_rt_rfd_status, + u8 *p_drv_info, + u8 phy_status +) { - #if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING)) - u4Byte *pMsg; - u2Byte seq_num; - pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; +#if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING)) + u32 *p_msg; + u16 seq_num; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - if (pRtRfdStatus->PacketReportType != NORMAL_RX) + if (p_rt_rfd_status->packet_report_type != NORMAL_RX) return; - - if (!pDM_Odm->bLinked) { - if (pRtRfdStatus->bHwError) + + if (!p_dm_odm->is_linked) { + if (p_rt_rfd_status->is_hw_error) return; } - if (!(pDM_FatTable->FAT_State == FAT_TRAINING_STATE)) + if (!(p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) return; - - if (PHYStatus == TRUE) { - if ((pDM_Odm->rx_pkt_type == Type_BlockAck) || (pDM_Odm->rx_pkt_type == Type_RTS) || (pDM_Odm->rx_pkt_type == Type_CTS)) + if (phy_status == true) { + + if ((p_dm_odm->rx_pkt_type == type_block_ack) || (p_dm_odm->rx_pkt_type == type_rts) || (p_dm_odm->rx_pkt_type == type_cts)) seq_num = 0; else - seq_num = pRtRfdStatus->Seq_Num; - - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s , Rate=0x%02x , L=%04d , %s , %s", - seq_num, - /*pRtRfdStatus->MacID,*/ - ((pRtRfdStatus->bCRC) ? "C" : (pRtRfdStatus->bIsAMPDU) ? "A" : "_"), - pRtRfdStatus->DataRate, - pRtRfdStatus->Length, - ((pRtRfdStatus->BandWidth == 0) ? "20M":((pRtRfdStatus->BandWidth == 1) ? "40M" : "80M")), - ((pRtRfdStatus->bLDPC) ? "LDP" : "BCC") - )); - - if (pDM_Odm->rx_pkt_type == Type_Asoc_Req) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_REQ")); + seq_num = p_rt_rfd_status->seq_num; + + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s, rate=0x%02x, L=%04d , %s , %s", + seq_num, + /*p_rt_rfd_status->mac_id,*/ + ((p_rt_rfd_status->is_crc) ? "C" : (p_rt_rfd_status->is_ampdu) ? "A" : "_"), + p_rt_rfd_status->data_rate, + p_rt_rfd_status->length, + ((p_rt_rfd_status->band_width == 0) ? "20M" : ((p_rt_rfd_status->band_width == 1) ? "40M" : "80M")), + ((p_rt_rfd_status->is_ldpc) ? "LDP" : "BCC") + )); + + if (p_dm_odm->rx_pkt_type == type_asoc_req) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_REQ")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Asoc_Rsp) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_RSP")); + } else if (p_dm_odm->rx_pkt_type == type_asoc_rsp) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_RSP")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Probe_Req) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_REQ")); + } else if (p_dm_odm->rx_pkt_type == type_probe_req) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_REQ")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Probe_Rsp) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_RSP")); + } else if (p_dm_odm->rx_pkt_type == type_probe_rsp) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_RSP")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Deauth) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "DEAUTH")); + } else if (p_dm_odm->rx_pkt_type == type_deauth) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "DEAUTH")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Beacon) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BEACON")); + } else if (p_dm_odm->rx_pkt_type == type_beacon) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BEACON")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_BlockAckReq) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BA_REQ")); + } else if (p_dm_odm->rx_pkt_type == type_block_ack_req) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BA_REQ")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_RTS) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__RTS_")); + } else if (p_dm_odm->rx_pkt_type == type_rts) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__RTS_")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_CTS) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__CTS_")); + } else if (p_dm_odm->rx_pkt_type == type_cts) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__CTS_")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Ack) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__ACK_")); + } else if (p_dm_odm->rx_pkt_type == type_ack) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__ACK_")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_BlockAck) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__BA__")); + } else if (p_dm_odm->rx_pkt_type == type_block_ack) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__BA__")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Data) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "_DATA_")); + } else if (p_dm_odm->rx_pkt_type == type_data) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "_DATA_")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_Data_Ack) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "Data_Ack")); + } else if (p_dm_odm->rx_pkt_type == type_data_ack) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "Data_Ack")); /**/ - } else if (pDM_Odm->rx_pkt_type == Type_QosData) { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "QoS_Data")); + } else if (p_dm_odm->rx_pkt_type == type_qos_data) { + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "QoS_Data")); /**/ } else { - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [0x%x]", pDM_Odm->rx_pkt_type)); + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [0x%x]", p_dm_odm->rx_pkt_type)); /**/ } - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [RSSI=%d,%d,%d,%d ]", - pDM_Odm->RSSI_A, - pDM_Odm->RSSI_B, - pDM_Odm->RSSI_C, - pDM_Odm->RSSI_D - )); - - pMsg = (pu4Byte)pDrvInfo; - - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n", - pMsg[6], pMsg[5], pMsg[4], pMsg[3], pMsg[2], pMsg[1], pMsg[1])); + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [RSSI=%d,%d,%d,%d ]", + p_dm_odm->RSSI_A, + p_dm_odm->RSSI_B, + p_dm_odm->RSSI_C, + p_dm_odm->RSSI_D + )); + + p_msg = (u32 *)p_drv_info; + + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n", + p_msg[6], p_msg[5], p_msg[4], p_msg[3], p_msg[2], p_msg[1], p_msg[1])); } else { - - ODM_RT_TRACE_F(pDM_Odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s , Rate=0x%02x , L=%04d , %s , %s\n", - pRtRfdStatus->Seq_Num, - /*pRtRfdStatus->MacID,*/ - ((pRtRfdStatus->bCRC) ? "C" : (pRtRfdStatus->bIsAMPDU) ? "A" : "_"), - pRtRfdStatus->DataRate, - pRtRfdStatus->Length, - ((pRtRfdStatus->BandWidth == 0) ? "20M" : ((pRtRfdStatus->BandWidth == 1) ? "40M" : "80M")), - ((pRtRfdStatus->bLDPC) ? "LDP" : "BCC") - )); + + ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n", + p_rt_rfd_status->seq_num, + /*p_rt_rfd_status->mac_id,*/ + ((p_rt_rfd_status->is_crc) ? "C" : (p_rt_rfd_status->is_ampdu) ? "A" : "_"), + p_rt_rfd_status->data_rate, + p_rt_rfd_status->length, + ((p_rt_rfd_status->band_width == 0) ? "20M" : ((p_rt_rfd_status->band_width == 1) ? "40M" : "80M")), + ((p_rt_rfd_status->is_ldpc) ? "LDP" : "BCC") + )); } - #endif +#endif } #endif -VOID -ODM_PhyStatusQuery( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo - ) +void +odm_phy_status_query( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo +) { -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_IC_PHY_STATUE_NEW_TYPE) { - phydm_RxPhyStatusNewType(pDM_Odm, pPhyStatus, pPktinfo, pPhyInfo); - return; + + if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) { + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + phydm_rx_phy_status_new_type(p_dm_odm, p_phy_status, p_pktinfo, p_phy_info); + #endif } -#endif -#if ODM_IC_11AC_SERIES_SUPPORT - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - ODM_PhyStatusQuery_JaguarSeries(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo); -#endif + #if ODM_IC_11AC_SERIES_SUPPORT + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + odm_phy_status_query_jaguar_series(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); + #endif -#if ODM_IC_11N_SERIES_SUPPORT - if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES ) - ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo); -#endif + #if ODM_IC_11N_SERIES_SUPPORT + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + odm_phy_status_query_92c_series(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); + #endif } - -// For future use. -VOID -ODM_MacStatusQuery( - IN OUT PDM_ODM_T pDM_Odm, - IN pu1Byte pMacStatus, - IN u1Byte MacID, - IN BOOLEAN bPacketMatchBSSID, - IN BOOLEAN bPacketToSelf, - IN BOOLEAN bPacketBeacon - ) + +/* For future use. */ +void +odm_mac_status_query( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_mac_status, + u8 mac_id, + boolean is_packet_match_bssid, + boolean is_packet_to_self, + boolean is_packet_beacon +) { - // 2011/10/19 Driver team will handle in the future. - + /* 2011/10/19 Driver team will handle in the future. */ + } -// -// If you want to add a new IC, Please follow below template and generate a new one. -// -// +/* + * If you want to add a new IC, Please follow below template and generate a new one. + * + * */ -HAL_STATUS -ODM_ConfigRFWithHeaderFile( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_Config_Type ConfigType, - IN ODM_RF_RADIO_PATH_E eRFPath - ) +enum hal_status +odm_config_rf_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_config_type config_type, + enum odm_rf_radio_path_e e_rf_path +) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); #endif + enum hal_status result = HAL_STATUS_SUCCESS; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===>ODM_ConfigRFWithHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n", - pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===>odm_config_rf_with_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", + p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type)); -//1 AP doesn't use PHYDM power tracking table in these ICs -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + /* 1 AP doesn't use PHYDM power tracking table in these ICs */ +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - { - if(ConfigType == CONFIG_RF_RADIO) { - if(eRFPath == ODM_RF_PATH_A){ - READ_AND_CONFIG_MP(8812A,_RadioA); - } - else if(eRFPath == ODM_RF_PATH_B){ - READ_AND_CONFIG_MP(8812A,_RadioB); - } - } - else if(ConfigType == CONFIG_RF_TXPWR_LMT) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - if ((pHalData->EEPROMSVID == 0x17AA && pHalData->EEPROMSMID == 0xA811) || - (pHalData->EEPROMSVID == 0x10EC && pHalData->EEPROMSMID == 0xA812) || - (pHalData->EEPROMSVID == 0x10EC && pHalData->EEPROMSMID == 0x8812)) - READ_AND_CONFIG_MP(8812A,_TXPWR_LMT_HM812A03); + if (p_dm_odm->support_ic_type == ODM_RTL8812) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8812a, _radioa); + else if (e_rf_path == ODM_RF_PATH_B) + READ_AND_CONFIG_MP(8812a, _radiob); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + if ((p_hal_data->EEPROMSVID == 0x17AA && p_hal_data->EEPROMSMID == 0xA811) || + (p_hal_data->EEPROMSVID == 0x10EC && p_hal_data->EEPROMSMID == 0xA812) || + (p_hal_data->EEPROMSVID == 0x10EC && p_hal_data->EEPROMSMID == 0x8812)) + READ_AND_CONFIG_MP(8812a, _txpwr_lmt_hm812a03); else - #endif - READ_AND_CONFIG_MP(8812A,_TXPWR_LMT); +#endif + READ_AND_CONFIG_MP(8812a, _txpwr_lmt); } } #endif #if (RTL8821A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821) - { - if(ConfigType == CONFIG_RF_RADIO) { - if(eRFPath == ODM_RF_PATH_A){ - READ_AND_CONFIG_MP(8821A,_RadioA); - } - } - else if(ConfigType == CONFIG_RF_TXPWR_LMT) { - if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { - if (pDM_Odm->ExtPA5G || pDM_Odm->ExtLNA5G) - READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8811AU_FEM); + if (p_dm_odm->support_ic_type == ODM_RTL8821) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8821a, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + if (p_dm_odm->support_interface == ODM_ITRF_USB) { + if (p_dm_odm->ext_pa_5g || p_dm_odm->ext_lna_5g) + READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_fem); else - READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8811AU_IPA); - } - else { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (pMgntInfo->CustomerID == RT_CID_8821AE_ASUS_MB) - READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8821A_SAR_8mm); - else if (pMgntInfo->CustomerID == RT_CID_ASUS_NB) - READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8821A_SAR_5mm); + READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_ipa); + } else { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (p_mgnt_info->CustomerID == RT_CID_8821AE_ASUS_MB) + READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_8mm); + else if (p_mgnt_info->CustomerID == RT_CID_ASUS_NB) + READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_5mm); else - #endif - READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8821A); +#endif + READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a); } } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigRFWithHeaderFile\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigRFWithHeaderFile\n")); } #endif #if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8192E) - { - if(ConfigType == CONFIG_RF_RADIO) { - if(eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8192E,_RadioA); - else if(eRFPath == ODM_RF_PATH_B) - READ_AND_CONFIG_MP(8192E,_RadioB); - } else if (ConfigType == CONFIG_RF_TXPWR_LMT) { + if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8192e, _radioa); + else if (e_rf_path == ODM_RF_PATH_B) + READ_AND_CONFIG_MP(8192e, _radiob); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) /*Refine by Vincent Lan for 5mm SAR pwr limit*/ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - if ((pHalData->EEPROMSVID == 0x11AD && pHalData->EEPROMSMID == 0x8192) || - (pHalData->EEPROMSVID == 0x11AD && pHalData->EEPROMSMID == 0x8193)) - READ_AND_CONFIG_MP(8192E, _TXPWR_LMT_8192E_SAR_5mm); + if ((p_hal_data->EEPROMSVID == 0x11AD && p_hal_data->EEPROMSMID == 0x8192) || + (p_hal_data->EEPROMSVID == 0x11AD && p_hal_data->EEPROMSMID == 0x8193)) + READ_AND_CONFIG_MP(8192e, _txpwr_lmt_8192e_sar_5mm); else -#endif - READ_AND_CONFIG_MP(8192E, _TXPWR_LMT); +#endif + READ_AND_CONFIG_MP(8192e, _txpwr_lmt); } } #endif #if (RTL8723D_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - if (ConfigType == CONFIG_RF_RADIO) { - if (eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8723D, _RadioA); - } else if (ConfigType == CONFIG_RF_TXPWR_LMT) - READ_AND_CONFIG_MP(8723D, _TXPWR_LMT); + if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8723d, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8723d, _txpwr_lmt); + } +#endif +/* JJ ADD 20161014 */ +#if (RTL8710B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8710b, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8710b, _txpwr_lmt); } #endif -#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) -//1 All platforms support +#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ + + /* 1 All platforms support */ #if (RTL8188E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188E) - { - if(ConfigType == CONFIG_RF_RADIO) { - if(eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8188E,_RadioA); - } - else if(ConfigType == CONFIG_RF_TXPWR_LMT) - READ_AND_CONFIG_MP(8188E,_TXPWR_LMT); + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8188e, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8188e, _txpwr_lmt); } #endif #if (RTL8723B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723B) { - if (ConfigType == CONFIG_RF_RADIO) - READ_AND_CONFIG_MP(8723B, _RadioA); - else if (ConfigType == CONFIG_RF_TXPWR_LMT) - READ_AND_CONFIG_MP(8723B, _TXPWR_LMT); + if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (config_type == CONFIG_RF_RADIO) + READ_AND_CONFIG_MP(8723b, _radioa); + else if (config_type == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8723b, _txpwr_lmt); } #endif #if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A) - { - if(ConfigType == CONFIG_RF_RADIO) { - if(eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8814A,_RadioA); - else if(eRFPath == ODM_RF_PATH_B) - READ_AND_CONFIG_MP(8814A,_RadioB); - else if(eRFPath == ODM_RF_PATH_C) - READ_AND_CONFIG_MP(8814A,_RadioC); - else if(eRFPath == ODM_RF_PATH_D) - READ_AND_CONFIG_MP(8814A,_RadioD); - } - else if(ConfigType == CONFIG_RF_TXPWR_LMT) - READ_AND_CONFIG_MP(8814A,_TXPWR_LMT); + if (p_dm_odm->support_ic_type == ODM_RTL8814A) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8814a, _radioa); + else if (e_rf_path == ODM_RF_PATH_B) + READ_AND_CONFIG_MP(8814a, _radiob); + else if (e_rf_path == ODM_RF_PATH_C) + READ_AND_CONFIG_MP(8814a, _radioc); + else if (e_rf_path == ODM_RF_PATH_D) + READ_AND_CONFIG_MP(8814a, _radiod); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + if (p_dm_odm->rfe_type == 0) + READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type0); + else if (p_dm_odm->rfe_type == 1) + READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type1); + else if (p_dm_odm->rfe_type == 2) + READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type2); + else if (p_dm_odm->rfe_type == 3) + READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type3); + else if (p_dm_odm->rfe_type == 5) + READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type5); + else if (p_dm_odm->rfe_type == 7) + READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type7); + else + READ_AND_CONFIG_MP(8814a,_txpwr_lmt); + } } #endif #if (RTL8703B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8703B) { - if (ConfigType == CONFIG_RF_RADIO) { - if (eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8703B, _RadioA); - } + if (p_dm_odm->support_ic_type == ODM_RTL8703B) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8703b, _radioa); + } } #endif #if (RTL8188F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188F) { - if (ConfigType == CONFIG_RF_RADIO) { - if (eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8188F, _RadioA); - } else if (ConfigType == CONFIG_RF_TXPWR_LMT) - READ_AND_CONFIG_MP(8188F, _TXPWR_LMT); + if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8188f, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8188f, _txpwr_lmt); } #endif #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) { - if (ConfigType == CONFIG_RF_RADIO) { - if (eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8822B, _RadioA); - else if (eRFPath == ODM_RF_PATH_B) - READ_AND_CONFIG_MP(8822B, _RadioB); - } + if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8822b, _radioa); + else if (e_rf_path == ODM_RF_PATH_B) + READ_AND_CONFIG_MP(8822b, _radiob); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + if (p_dm_odm->rfe_type == 5) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type5); + else + READ_AND_CONFIG_MP(8822b, _txpwr_lmt); } + } #endif #if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8197F) { - if (ConfigType == CONFIG_RF_RADIO) { - if (eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_MP(8197F, _RadioA); - else if (eRFPath == ODM_RF_PATH_B) - READ_AND_CONFIG_MP(8197F, _RadioB); - } + if (p_dm_odm->support_ic_type == ODM_RTL8197F) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8197f, _radioa); + else if (e_rf_path == ODM_RF_PATH_B) + READ_AND_CONFIG_MP(8197f, _radiob); } + } #endif #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) { - if (ConfigType == CONFIG_RF_RADIO) { - if (eRFPath == ODM_RF_PATH_A) - READ_AND_CONFIG_TC(8821C, _RadioA); - } else if (ConfigType == CONFIG_RF_TXPWR_LMT) - READ_AND_CONFIG_TC(8821C, _TXPWR_LMT); - } + if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG(8821c, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG(8821c, _txpwr_lmt); + } #endif - return HAL_STATUS_SUCCESS; + if (config_type == CONFIG_RF_RADIO) { + if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + + result = phydm_set_reg_by_fw(p_dm_odm, + PHYDM_HALMAC_CMD_END, + 0, + 0, + 0, + 0, + 0); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("rf param offload end!result = %d", result)); + } + } + + return result; } -HAL_STATUS -ODM_ConfigRFWithTxPwrTrackHeaderFile( - IN PDM_ODM_T pDM_Odm - ) +enum hal_status +odm_config_rf_with_tx_pwr_track_header_file( + struct PHY_DM_STRUCT *p_dm_odm +) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===>ODM_ConfigRFWithTxPwrTrackHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n", - pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===>odm_config_rf_with_tx_pwr_track_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n", + p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type)); -//1 AP doesn't use PHYDM power tracking table in these ICs -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + /* 1 AP doesn't use PHYDM power tracking table in these ICs */ +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if RTL8821A_SUPPORT - if(pDM_Odm->SupportICType == ODM_RTL8821) - { - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8821A,_TxPowerTrack_PCIE); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8821A,_TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8821A,_TxPowerTrack_SDIO); - } -#endif -#if RTL8812A_SUPPORT - if(pDM_Odm->SupportICType == ODM_RTL8812) - { - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8812A,_TxPowerTrack_PCIE); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { - if (pDM_Odm->RFEType == 3 && pDM_Odm->bIsMPChip) - READ_AND_CONFIG_MP(8812A,_TxPowerTrack_RFE3); + if (p_dm_odm->support_ic_type == ODM_RTL8821) { + if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8821a, _txpowertrack_pcie); + else if (p_dm_odm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8821a, _txpowertrack_usb); + else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8821a, _txpowertrack_sdio); + } +#endif +#if RTL8812A_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8812) { + if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8812a, _txpowertrack_pcie); + else if (p_dm_odm->support_interface == ODM_ITRF_USB) { + if (p_dm_odm->rfe_type == 3 && p_dm_odm->is_mp_chip) + READ_AND_CONFIG_MP(8812a, _txpowertrack_rfe3); else - READ_AND_CONFIG_MP(8812A,_TxPowerTrack_USB); + READ_AND_CONFIG_MP(8812a, _txpowertrack_usb); } - - } -#endif -#if RTL8192E_SUPPORT - if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8192E,_TxPowerTrack_PCIE); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8192E,_TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8192E,_TxPowerTrack_SDIO); + } #endif -#if RTL8723D_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8723D, _TxPowerTrack_PCIE); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8723D, _TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8723D, _TxPowerTrack_SDIO); - - READ_AND_CONFIG_MP(8723D, _TxXtalTrack); +#if RTL8192E_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8192e, _txpowertrack_pcie); + else if (p_dm_odm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8192e, _txpowertrack_usb); + else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8192e, _txpowertrack_sdio); } #endif -#if RTL8188E_SUPPORT - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - if (PHY_QueryMacReg(pDM_Odm->Adapter, 0xF0, 0xF000) >= 8) { /*if 0xF0[15:12] >= 8, SMIC*/ - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8188E, _TxPowerTrack_PCIE_ICUT); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8188E, _TxPowerTrack_USB_ICUT); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8188E, _TxPowerTrack_SDIO_ICUT); +#if RTL8723D_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8723d, _txpowertrack_pcie); + else if (p_dm_odm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8723d, _txpowertrack_usb); + else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8723d, _txpowertrack_sdio); + + READ_AND_CONFIG_MP(8723d, _txxtaltrack); + } +#endif +/* JJ ADD 20161014 */ +#if RTL8710B_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8710b, _txpowertrack_pcie); + else if (p_dm_odm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8710b, _txpowertrack_usb); + else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8710b, _txpowertrack_sdio); + + READ_AND_CONFIG_MP(8710b, _txxtaltrack); + } +#endif + +#if RTL8188E_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + if (odm_get_mac_reg(p_dm_odm, 0xF0, 0xF000) >= 8) { /*if 0xF0[15:12] >= 8, SMIC*/ + if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie_icut); + else if (p_dm_odm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8188e, _txpowertrack_usb_icut); + else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio_icut); } else { /*else 0xF0[15:12] < 8, TSMC*/ - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8188E, _TxPowerTrack_PCIE); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8188E, _TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8188E, _TxPowerTrack_SDIO); + if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie); + else if (p_dm_odm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8188e, _txpowertrack_usb); + else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio); } - + } #endif -#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) +#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ -//1 All platforms support + /* 1 All platforms support */ #if RTL8723B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8723B) { - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8723B, _TxPowerTrack_PCIE); - else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8723B, _TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8723B, _TxPowerTrack_SDIO); - } -#endif + if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8723b, _txpowertrack_pcie); + else if (p_dm_odm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8723b, _txpowertrack_usb); + else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8723b, _txpowertrack_sdio); + } +#endif #if RTL8814A_SUPPORT - if(pDM_Odm->SupportICType == ODM_RTL8814A) - { - if(pDM_Odm->RFEType == 0) - READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type0); - else if(pDM_Odm->RFEType == 2) - READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type2); - else if (pDM_Odm->RFEType == 5) - READ_AND_CONFIG_MP(8814A, _TxPowerTrack_Type5); + if (p_dm_odm->support_ic_type == ODM_RTL8814A) { + if (p_dm_odm->rfe_type == 0) + READ_AND_CONFIG_MP(8814a, _txpowertrack_type0); + else if (p_dm_odm->rfe_type == 2) + READ_AND_CONFIG_MP(8814a, _txpowertrack_type2); + else if (p_dm_odm->rfe_type == 5) + READ_AND_CONFIG_MP(8814a, _txpowertrack_type5); else - READ_AND_CONFIG_MP(8814A,_TxPowerTrack); - - READ_AND_CONFIG_MP(8814A, _TxPowerTSSI); + READ_AND_CONFIG_MP(8814a, _txpowertrack); + + READ_AND_CONFIG_MP(8814a, _txpowertssi); } #endif #if RTL8703B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8703B) { - if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8703B, _TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8703B, _TxPowerTrack_SDIO); + if (p_dm_odm->support_ic_type == ODM_RTL8703B) { + if (p_dm_odm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8703b, _txpowertrack_usb); + else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8703b, _txpowertrack_sdio); - READ_AND_CONFIG_MP(8703B, _TxXtalTrack); + READ_AND_CONFIG_MP(8703b, _txxtaltrack); } #endif #if RTL8188F_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8188F) { - if (pDM_Odm->SupportInterface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8188F, _TxPowerTrack_USB); - else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8188F, _TxPowerTrack_SDIO); + if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (p_dm_odm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8188f, _txpowertrack_usb); + else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8188f, _txpowertrack_sdio); } #endif #if RTL8822B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8822B) { - if (pDM_Odm->RFEType == 0) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type0); - else if (pDM_Odm->RFEType == 1) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type1); - else if ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5)) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_Type3_Type5); - else if (pDM_Odm->RFEType == 6) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type6); - else if (pDM_Odm->RFEType == 7) - READ_AND_CONFIG_MP(8822B, _TxPowerTrack_type7); + if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + if (p_dm_odm->rfe_type == 0) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type0); + else if (p_dm_odm->rfe_type == 1) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type1); + else if (p_dm_odm->rfe_type == 2) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type2); + else if ((p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5)) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type3_type5); + else if (p_dm_odm->rfe_type == 4) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type4); + else if (p_dm_odm->rfe_type == 6) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type6); + else if (p_dm_odm->rfe_type == 7) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type7); + else if (p_dm_odm->rfe_type == 8) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type8); + else if (p_dm_odm->rfe_type == 9) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type9); + else if (p_dm_odm->rfe_type == 10) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type10); + else if (p_dm_odm->rfe_type == 11) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type11); + else if (p_dm_odm->rfe_type == 12) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type12); else - READ_AND_CONFIG_MP(8822B, _TxPowerTrack); + READ_AND_CONFIG_MP(8822b, _txpowertrack); } #endif #if RTL8197F_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8197F) { - if (pDM_Odm->RFEType == 0) - READ_AND_CONFIG_MP(8197F, _TxPowerTrack_Type0); - else if (pDM_Odm->RFEType == 1) - READ_AND_CONFIG_MP(8197F, _TxPowerTrack_Type1); + if (p_dm_odm->support_ic_type == ODM_RTL8197F) { + if (p_dm_odm->rfe_type == 0) + READ_AND_CONFIG_MP(8197f, _txpowertrack_type0); + else if (p_dm_odm->rfe_type == 1) + READ_AND_CONFIG_MP(8197f, _txpowertrack_type1); else - READ_AND_CONFIG_MP(8197F, _TxPowerTrack); + READ_AND_CONFIG_MP(8197f, _txpowertrack); } -#endif +#endif #if RTL8821C_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8821C) - READ_AND_CONFIG_TC(8821C, _TxPowerTrack); + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + READ_AND_CONFIG(8821c, _txpowertrack); #endif return HAL_STATUS_SUCCESS; } -HAL_STATUS -ODM_ConfigBBWithHeaderFile( - IN PDM_ODM_T pDM_Odm, - IN ODM_BB_Config_Type ConfigType - ) +enum hal_status +odm_config_bb_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_bb_config_type config_type +) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); #endif + enum hal_status result = HAL_STATUS_SUCCESS; -//1 AP doesn't use PHYDM initialization in these ICs -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) -#if (RTL8812A_SUPPORT == 1) - if(pDM_Odm->SupportICType == ODM_RTL8812) - { - if (ConfigType == CONFIG_BB_PHY_REG) { - READ_AND_CONFIG_MP(8812A, _PHY_REG); - } else if (ConfigType == CONFIG_BB_AGC_TAB) { - READ_AND_CONFIG_MP(8812A, _AGC_TAB); - } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { - if (pDM_Odm->RFEType == 3 && pDM_Odm->bIsMPChip) - READ_AND_CONFIG_MP(8812A, _PHY_REG_PG_ASUS); - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - else if (pMgntInfo->CustomerID == RT_CID_WNC_NEC && pDM_Odm->bIsMPChip) - READ_AND_CONFIG_MP(8812A, _PHY_REG_PG_NEC); - #if RT_PLATFORM == PLATFORM_MACOSX + /* 1 AP doesn't use PHYDM initialization in these ICs */ +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8812A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8812) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8812a, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8812a, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (p_dm_odm->rfe_type == 3 && p_dm_odm->is_mp_chip) + READ_AND_CONFIG_MP(8812a, _phy_reg_pg_asus); +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + else if (p_mgnt_info->CustomerID == RT_CID_WNC_NEC && p_dm_odm->is_mp_chip) + READ_AND_CONFIG_MP(8812a, _phy_reg_pg_nec); +#if RT_PLATFORM == PLATFORM_MACOSX /*{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/ - else if (pMgntInfo->CustomerID == RT_CID_DNI_BUFFALO) - READ_AND_CONFIG_MP(8812A, _PHY_REG_PG_DNI); + else if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) + READ_AND_CONFIG_MP(8812a, _phy_reg_pg_dni); /* TP-Link T4UH, Isaiah 2015-03-16*/ - else if (pMgntInfo->CustomerID == RT_CID_TPLINK_HPWR) { - DbgPrint("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n"); - READ_AND_CONFIG_MP(8812A, _PHY_REG_PG_TPLINK); + else if (p_mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) { + dbg_print("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n"); + READ_AND_CONFIG_MP(8812a, _phy_reg_pg_tplink); } - #endif - #endif +#endif +#endif else - READ_AND_CONFIG_MP(8812A, _PHY_REG_PG); + READ_AND_CONFIG_MP(8812a, _phy_reg_pg); + } else if (config_type == CONFIG_BB_PHY_REG_MP) + READ_AND_CONFIG_MP(8812a, _phy_reg_mp); + else if (config_type == CONFIG_BB_AGC_TAB_DIFF) { + p_dm_odm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD; + /*AGC_TAB DIFF dont support FW offload*/ + if ((36 <= *p_dm_odm->p_channel) && (*p_dm_odm->p_channel <= 64)) + AGC_DIFF_CONFIG_MP(8812a, lb); + else if (100 <= *p_dm_odm->p_channel) + AGC_DIFF_CONFIG_MP(8812a, hb); } - else if(ConfigType == CONFIG_BB_PHY_REG_MP){ - READ_AND_CONFIG_MP(8812A,_PHY_REG_MP); - } - else if(ConfigType == CONFIG_BB_AGC_TAB_DIFF) - { - if ((36 <= *pDM_Odm->pChannel) && (*pDM_Odm->pChannel <= 64)) - AGC_DIFF_CONFIG_MP(8812A,LB); - else if (100 <= *pDM_Odm->pChannel) - AGC_DIFF_CONFIG_MP(8812A,HB); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8812AGCTABArray\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8812PHY_REGArray\n")); - } -#endif -#if (RTL8821A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821) { - if (ConfigType == CONFIG_BB_PHY_REG) { - READ_AND_CONFIG_MP(8821A, _PHY_REG); - } else if (ConfigType == CONFIG_BB_AGC_TAB) { - READ_AND_CONFIG_MP(8821A, _AGC_TAB); - } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - if ((pHalData->EEPROMSVID == 0x1043 && pHalData->EEPROMSMID == 0x207F)) - READ_AND_CONFIG_MP(8821A, _PHY_REG_PG_E202SA); + } +#endif +#if (RTL8821A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8821) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8821a, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8821a, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + + if ((p_hal_data->EEPROMSVID == 0x1043 && p_hal_data->EEPROMSMID == 0x207F)) + READ_AND_CONFIG_MP(8821a, _phy_reg_pg_e202_sa); else - #endif - #if (RT_PLATFORM == PLATFORM_MACOSX) - /*{1827}{1022} for BUFFALO power by rate table. Isaiah 2013-10-18*/ - if (pMgntInfo->CustomerID == RT_CID_DNI_BUFFALO) { - /*{1024} for BUFFALO power by rate table. (JP/US)*/ - if (pMgntInfo->ChannelPlan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G) - READ_AND_CONFIG_MP(8821A, _PHY_REG_PG_DNI_US); - else - READ_AND_CONFIG_MP(8821A, _PHY_REG_PG_DNI_JP); - } else - #endif - #endif - READ_AND_CONFIG_MP(8821A,_PHY_REG_PG); - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8821AGCTABArray\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8821PHY_REGArray\n")); - } #endif -#if (RTL8192E_SUPPORT == 1) - if(pDM_Odm->SupportICType == ODM_RTL8192E) - { - if(ConfigType == CONFIG_BB_PHY_REG){ - READ_AND_CONFIG_MP(8192E,_PHY_REG); - }else if(ConfigType == CONFIG_BB_AGC_TAB){ - READ_AND_CONFIG_MP(8192E,_AGC_TAB); - }else if(ConfigType == CONFIG_BB_PHY_REG_PG){ - READ_AND_CONFIG_MP(8192E,_PHY_REG_PG); +#if (RT_PLATFORM == PLATFORM_MACOSX) + /*{1827}{1022} for BUFFALO power by rate table. Isaiah 2013-10-18*/ + if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) { + /*{1024} for BUFFALO power by rate table. (JP/US)*/ + if (p_mgnt_info->channel_plan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G) + READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us); + else + READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp); + } else +#endif +#endif + READ_AND_CONFIG_MP(8821a, _phy_reg_pg); } } #endif +#if (RTL8192E_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8192e, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8192e, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8192e, _phy_reg_pg); + } +#endif #if (RTL8723D_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - if (ConfigType == CONFIG_BB_PHY_REG) - READ_AND_CONFIG_MP(8723D, _PHY_REG); - else if (ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG_MP(8723D, _AGC_TAB); - else if (ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8723D, _PHY_REG_PG); + if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8723d, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8723d, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8723d, _phy_reg_pg); + } +#endif +/* JJ ADD 20161014 */ +#if (RTL8710B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8710b, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8710b, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8710b, _phy_reg_pg); } #endif -#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) +#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ -//1 All platforms support + + /* 1 All platforms support */ #if (RTL8188E_SUPPORT == 1) - if(pDM_Odm->SupportICType == ODM_RTL8188E) - { - if(ConfigType == CONFIG_BB_PHY_REG) - READ_AND_CONFIG_MP(8188E,_PHY_REG); - else if(ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG_MP(8188E,_AGC_TAB); - else if(ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8188E,_PHY_REG_PG); + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8188e, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8188e, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8188e, _phy_reg_pg); } #endif #if (RTL8723B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723B) { - if (ConfigType == CONFIG_BB_PHY_REG) { - READ_AND_CONFIG_MP(8723B, _PHY_REG); - } else if (ConfigType == CONFIG_BB_AGC_TAB) { - READ_AND_CONFIG_MP(8723B, _AGC_TAB); - } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { - READ_AND_CONFIG_MP(8723B, _PHY_REG_PG); - } + if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8723b, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8723b, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8723b, _phy_reg_pg); } #endif #if (RTL8814A_SUPPORT == 1) - if(pDM_Odm->SupportICType == ODM_RTL8814A) - { - if(ConfigType == CONFIG_BB_PHY_REG){ - READ_AND_CONFIG_MP(8814A,_PHY_REG); - }else if(ConfigType == CONFIG_BB_AGC_TAB){ - READ_AND_CONFIG_MP(8814A,_AGC_TAB); - }else if(ConfigType == CONFIG_BB_PHY_REG_PG){ - READ_AND_CONFIG_MP(8814A,_PHY_REG_PG); - }else if(ConfigType == CONFIG_BB_PHY_REG_MP){ - READ_AND_CONFIG_MP(8814A,_PHY_REG_MP); + if (p_dm_odm->support_ic_type == ODM_RTL8814A) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8814a, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8814a, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (p_dm_odm->rfe_type == 0) + READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type0); + else if (p_dm_odm->rfe_type == 2) + READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type2); + else if (p_dm_odm->rfe_type == 3) + READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type3); + else if (p_dm_odm->rfe_type == 4) + READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type4); + else if (p_dm_odm->rfe_type == 5) + READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type5); + else if (p_dm_odm->rfe_type == 7) + READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type7); + else + READ_AND_CONFIG_MP(8814a,_phy_reg_pg); } + else if (config_type == CONFIG_BB_PHY_REG_MP) + READ_AND_CONFIG_MP(8814a, _phy_reg_mp); } #endif #if (RTL8703B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8703B) { - if (ConfigType == CONFIG_BB_PHY_REG) - READ_AND_CONFIG_MP(8703B, _PHY_REG); - else if (ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG_MP(8703B, _AGC_TAB); - else if (ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8703B, _PHY_REG_PG); + if (p_dm_odm->support_ic_type == ODM_RTL8703B) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8703b, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8703b, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8703b, _phy_reg_pg); } #endif #if (RTL8188F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188F) { - if (ConfigType == CONFIG_BB_PHY_REG) - READ_AND_CONFIG_MP(8188F, _PHY_REG); - else if (ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG_MP(8188F, _AGC_TAB); - else if (ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8188F, _PHY_REG_PG); + if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8188f, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8188f, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8188f, _phy_reg_pg); } #endif #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) { - if (ConfigType == CONFIG_BB_PHY_REG) - READ_AND_CONFIG_MP(8822B, _PHY_REG); - else if (ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG_MP(8822B, _AGC_TAB); - else if (ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8822B, _PHY_REG_PG); - /*else if (ConfigType == CONFIG_BB_PHY_REG_MP)*/ - /*READ_AND_CONFIG_MP(8822B, _PHY_REG_MP);*/ + if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8822b, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8822b, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg); } #endif #if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8197F) { - if (ConfigType == CONFIG_BB_PHY_REG) { - READ_AND_CONFIG_MP(8197F, _PHY_REG); - if (pDM_Odm->CutVersion == ODM_CUT_A) - phydm_phypara_a_cut(pDM_Odm); - } else if (ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG_MP(8197F, _AGC_TAB); -/* else if(ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8197F, _PHY_REG_PG); - else if(ConfigType == CONFIG_BB_PHY_REG_MP) - READ_AND_CONFIG_MP(8197F, _PHY_REG_MP); */ - } -#endif - -#if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - { - if (ConfigType == CONFIG_BB_PHY_REG) { - READ_AND_CONFIG_TC(8821C, _PHY_REG); - } else if (ConfigType == CONFIG_BB_AGC_TAB) { - READ_AND_CONFIG_TC(8821C, _AGC_TAB); - } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { - READ_AND_CONFIG_TC(8821C, _PHY_REG_PG); + if (p_dm_odm->support_ic_type == ODM_RTL8197F) { + if (config_type == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG_MP(8197f, _phy_reg); + if (p_dm_odm->cut_version == ODM_CUT_A) + phydm_phypara_a_cut(p_dm_odm); + } else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8197f, _agc_tab); + } +#endif + +#if (RTL8821C_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG(8821c, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) { + READ_AND_CONFIG(8821c, _agc_tab); + /* According to RFEtype, choosing correct AGC table*/ + if (p_dm_odm->default_rf_set_8821c == SWITCH_TO_BTG) + AGC_DIFF_CONFIG_MP(8821c, btg); + } else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG(8821c, _phy_reg_pg); + else if (config_type == CONFIG_BB_AGC_TAB_DIFF) { + p_dm_odm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD; + /*AGC_TAB DIFF dont support FW offload*/ + if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_BTG) + AGC_DIFF_CONFIG_MP(8821c, btg); + else if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_WLG) + AGC_DIFF_CONFIG_MP(8821c, wlg); } - } + } #endif #if (RTL8195A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8195A) - { - if(ConfigType == CONFIG_BB_PHY_REG) - READ_AND_CONFIG(8195A, _PHY_REG); - else if(ConfigType == CONFIG_BB_AGC_TAB) - READ_AND_CONFIG(8195A, _AGC_TAB); - else if(ConfigType == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG(8195A, _PHY_REG_PG); + if (p_dm_odm->support_ic_type == ODM_RTL8195A) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG(8195a, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG(8195a, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG(8195a, _phy_reg_pg); } #endif - return HAL_STATUS_SUCCESS; -} + if (config_type == CONFIG_BB_PHY_REG || config_type == CONFIG_BB_AGC_TAB) + if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { -HAL_STATUS -ODM_ConfigMACWithHeaderFile( - IN PDM_ODM_T pDM_Odm - ) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; -#endif + result = phydm_set_reg_by_fw(p_dm_odm, + PHYDM_HALMAC_CMD_END, + 0, + 0, + 0, + 0, + 0); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("phy param offload end!result = %d", result)); + } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===>ODM_ConfigMACWithHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n", - pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType)); + return result; +} -//1 AP doesn't use PHYDM initialization in these ICs -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +enum hal_status +odm_config_mac_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + enum hal_status result = HAL_STATUS_SUCCESS; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===>odm_config_mac_with_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", + p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type)); + + /* 1 AP doesn't use PHYDM initialization in these ICs */ +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812){ - READ_AND_CONFIG_MP(8812A, _MAC_REG); - } + if (p_dm_odm->support_ic_type == ODM_RTL8812) + READ_AND_CONFIG_MP(8812a, _mac_reg); #endif #if (RTL8821A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821){ - READ_AND_CONFIG_MP(8821A, _MAC_REG); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigMACwithHeaderFile\n")); - } + if (p_dm_odm->support_ic_type == ODM_RTL8821) + READ_AND_CONFIG_MP(8821a, _mac_reg); #endif -#if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8192E){ - READ_AND_CONFIG_MP(8192E, _MAC_REG); - } +#if (RTL8192E_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8192E) + READ_AND_CONFIG_MP(8192e, _mac_reg); +#endif +#if (RTL8723D_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8723D) + READ_AND_CONFIG_MP(8723d, _mac_reg); #endif -#if (RTL8723D_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723D) - READ_AND_CONFIG_MP(8723D, _MAC_REG); +/* JJ ADD 20161014 */ +#if (RTL8710B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8710B) + READ_AND_CONFIG_MP(8710b, _mac_reg); #endif -#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) -//1 All platforms support -#if (RTL8188E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188E){ - READ_AND_CONFIG_MP(8188E, _MAC_REG); - } +#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ + + /* 1 All platforms support */ +#if (RTL8188E_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8188E) + READ_AND_CONFIG_MP(8188e, _mac_reg); #endif -#if (RTL8723B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723B) { - READ_AND_CONFIG_MP(8723B, _MAC_REG); - } +#if (RTL8723B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8723B) + READ_AND_CONFIG_MP(8723b, _mac_reg); #endif -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A){ - READ_AND_CONFIG_MP(8814A, _MAC_REG); - } +#if (RTL8814A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8814A) + READ_AND_CONFIG_MP(8814a, _mac_reg); #endif -#if (RTL8703B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8703B) - READ_AND_CONFIG_MP(8703B, _MAC_REG); +#if (RTL8703B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8703B) + READ_AND_CONFIG_MP(8703b, _mac_reg); #endif -#if (RTL8188F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188F) - READ_AND_CONFIG_MP(8188F, _MAC_REG); +#if (RTL8188F_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8188F) + READ_AND_CONFIG_MP(8188f, _mac_reg); #endif -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) - READ_AND_CONFIG_MP(8822B, _MAC_REG); +#if (RTL8822B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8822B) + READ_AND_CONFIG_MP(8822b, _mac_reg); #endif -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8197F) - READ_AND_CONFIG_MP(8197F, _MAC_REG); +#if (RTL8197F_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8197F) + READ_AND_CONFIG_MP(8197f, _mac_reg); #endif #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - READ_AND_CONFIG_TC(8821C, _MAC_REG); + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + READ_AND_CONFIG(8821c, _mac_reg); #endif -#if (RTL8195A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8195A) - READ_AND_CONFIG_MP(8195A, _MAC_REG); +#if (RTL8195A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8195A) + READ_AND_CONFIG_MP(8195a, _mac_reg); #endif - return HAL_STATUS_SUCCESS; -} + if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { -HAL_STATUS -ODM_ConfigFWWithHeaderFile( - IN PDM_ODM_T pDM_Odm, - IN ODM_FW_Config_Type ConfigType, - OUT u1Byte *pFirmware, - OUT u4Byte *pSize - ) + result = phydm_set_reg_by_fw(p_dm_odm, + PHYDM_HALMAC_CMD_END, + 0, + 0, + 0, + 0, + 0); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("mac param offload end!result = %d", result)); + } + + return result; +} + +enum hal_status +odm_config_fw_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_fw_config_type config_type, + u8 *p_firmware, + u32 *p_size +) { -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#if (RTL8188E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188E) - { - #ifdef CONFIG_SFW_SUPPORTED - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8188E_T,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8188E_T,_FW_WoWLAN); - else if(ConfigType == CONFIG_FW_NIC_2) - READ_FIRMWARE_MP(8188E_S,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN_2) - READ_FIRMWARE_MP(8188E_S,_FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - if (ConfigType == CONFIG_FW_AP) - READ_FIRMWARE_MP(8188E_T,_FW_AP); - else if (ConfigType == CONFIG_FW_AP_2) - READ_FIRMWARE_MP(8188E_S,_FW_AP); - #endif //CONFIG_AP_WOWLAN - #else - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8188E_T,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8188E_T,_FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP) - READ_FIRMWARE_MP(8188E_T,_FW_AP); - #endif //CONFIG_AP_WOWLAN - #endif +#if (RTL8188E_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { +#ifdef CONFIG_SFW_SUPPORTED + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8188e_t, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) + READ_FIRMWARE_MP(8188e_t, _fw_wowlan); + else if (config_type == CONFIG_FW_NIC_2) + READ_FIRMWARE_MP(8188e_s, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN_2) + READ_FIRMWARE_MP(8188e_s, _fw_wowlan); +#ifdef CONFIG_AP_WOWLAN + if (config_type == CONFIG_FW_AP) + READ_FIRMWARE_MP(8188e_t, _fw_ap); + else if (config_type == CONFIG_FW_AP_2) + READ_FIRMWARE_MP(8188e_s, _fw_ap); +#endif /* CONFIG_AP_WOWLAN */ +#else + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8188e_t, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) + READ_FIRMWARE_MP(8188e_t, _fw_wowlan); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == CONFIG_FW_AP) + READ_FIRMWARE_MP(8188e_t, _fw_ap); +#endif /* CONFIG_AP_WOWLAN */ +#endif } #endif -#if (RTL8723B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723B) - { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8723B,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8723B,_FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE(8723B,_FW_AP_WoWLAN); - #endif - +#if (RTL8723B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8723b, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) + READ_FIRMWARE_MP(8723b, _fw_wowlan); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == config_fw_ap_wowlan) + READ_FIRMWARE(8723b, _fw_ap); +#endif + } -#endif //#if (RTL8723B_SUPPORT == 1) +#endif /* #if (RTL8723B_SUPPORT == 1) */ #if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8812A,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8812A,_FW_WoWLAN); - else if (ConfigType == CONFIG_FW_BT) - READ_FIRMWARE_MP(8812A,_FW_NIC_BT); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE(8812A,_FW_AP); - #endif + if (p_dm_odm->support_ic_type == ODM_RTL8812) { + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8812a, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) + READ_FIRMWARE_MP(8812a, _fw_wowlan); + else if (config_type == CONFIG_FW_BT) + READ_FIRMWARE_MP(8812a, _fw_nic_bt); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == config_fw_ap_wowlan) + READ_FIRMWARE(8812a, _fw_ap); +#endif } #endif #if (RTL8821A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821){ - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8821A,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8821A,_FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE_MP(8821A , _FW_AP); - #endif /*CONFIG_AP_WOWLAN*/ - else if (ConfigType == CONFIG_FW_BT) - READ_FIRMWARE_MP(8821A,_FW_NIC_BT); + if (p_dm_odm->support_ic_type == ODM_RTL8821) { + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8821a, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) + READ_FIRMWARE_MP(8821a, _fw_wowlan); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == config_fw_ap_wowlan) + READ_FIRMWARE_MP(8821a, _fw_ap); +#endif /*CONFIG_AP_WOWLAN*/ + else if (config_type == CONFIG_FW_BT) + READ_FIRMWARE_MP(8821a, _fw_nic_bt); } #endif #if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8192E) - { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8192E,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8192E,_FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE_MP(8192E,_FW_AP); - #endif + if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8192e, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) + READ_FIRMWARE_MP(8192e, _fw_wowlan); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == config_fw_ap_wowlan) + READ_FIRMWARE_MP(8192e, _fw_ap); +#endif } #endif #if (RTL8723D_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - if (ConfigType == CONFIG_FW_NIC) { - READ_FIRMWARE_MP(8723D, _FW_NIC); - } else if (ConfigType == CONFIG_FW_WoWLAN) { - READ_FIRMWARE_MP(8723D, _FW_WoWLAN); + if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8723d, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) { + READ_FIRMWARE_MP(8723d, _fw_wowlan); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == config_fw_ap_wowlan) + READ_FIRMWARE_MP(8723d, _fw_ap); +#endif } } #endif -/*#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A) - { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8814A, _FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8814A, _FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE_MP(8814A, _FW_AP); - #endif - } -#endif */ +/* JJ ADD 20161014 */ +#if (RTL8710B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8710b, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) { + READ_FIRMWARE_MP(8710b, _fw_wowlan); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == config_fw_ap_wowlan) + READ_FIRMWARE_MP(8710b, _fw_ap); +#endif + } + } +#endif #if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A) - { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8814A,_FW_NIC); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE_MP(8814A,_FW_AP); - #endif + if (p_dm_odm->support_ic_type == ODM_RTL8814A) { + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8814a, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) + READ_FIRMWARE_MP(8814a, _fw_wowlan); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == config_fw_ap_wowlan) + READ_FIRMWARE_MP(8814a, _fw_ap); +#endif } #endif #if (RTL8703B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8703B) { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8703B, _FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8703B, _FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE(8703B, _FW_AP_WoWLAN); - #endif + if (p_dm_odm->support_ic_type == ODM_RTL8703B) { + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8703b, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) + READ_FIRMWARE_MP(8703b, _fw_wowlan); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == config_fw_ap_wowlan) + READ_FIRMWARE(8703b, _fw_ap); +#endif } #endif #if (RTL8188F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188F) { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8188F, _FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8188F, _FW_WoWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP) - READ_FIRMWARE_MP(8188F, _FW_AP); - #endif + if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8188f, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) + READ_FIRMWARE_MP(8188f, _fw_wowlan); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == CONFIG_FW_AP) + READ_FIRMWARE_MP(8188f, _fw_ap); +#endif } #endif #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) { - - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8822B,_FW_NIC); - else if (ConfigType == CONFIG_FW_WoWLAN) - READ_FIRMWARE_MP(8822B, _FW_WOWLAN); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE(8822B,_FW_AP); - #endif + if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8822b, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) + READ_FIRMWARE_MP(8822b, _fw_wowlan); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == config_fw_ap_wowlan) + READ_FIRMWARE(8822b, _fw_ap); +#endif } #endif #if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8197F) { - if (ConfigType == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8197F, _FW_NIC); - #ifdef CONFIG_AP_WOWLAN - else if (ConfigType == CONFIG_FW_AP_WoWLAN) - READ_FIRMWARE(8197F , _FW_AP); - #endif + if (p_dm_odm->support_ic_type == ODM_RTL8197F) { + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8197f, _fw_nic); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == config_fw_ap_wowlan) + READ_FIRMWARE(8197f, _fw_ap); +#endif + } +#endif + +#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN)) +#if (RTL8821C_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + if (config_type == CONFIG_FW_NIC) + READ_FIRMWARE_MP(8821c, _fw_nic); + else if (config_type == CONFIG_FW_WOWLAN) + READ_FIRMWARE_MP(8821c, _fw_wowlan); +#ifdef CONFIG_AP_WOWLAN + else if (config_type == config_fw_ap_wowlan) + READ_FIRMWARE_MP(8821c, _fw_ap); +#endif /*CONFIG_AP_WOWLAN*/ } #endif +#endif -#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) - return HAL_STATUS_SUCCESS; -} +#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ + return HAL_STATUS_SUCCESS; +} -u4Byte -ODM_GetHWImgVersion( - IN PDM_ODM_T pDM_Odm - ) +u32 +odm_get_hw_img_version( + struct PHY_DM_STRUCT *p_dm_odm +) { - u4Byte Version=0; + u32 version = 0; -//1 AP doesn't use PHYDM initialization in these ICs + /* 1 AP doesn't use PHYDM initialization in these ICs */ #if (DM_ODM_SUPPORT_TYPE != ODM_AP) -#if (RTL8821A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821) - Version = GET_VERSION_MP(8821A,_MAC_REG); +#if (RTL8821A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8821) + version = GET_VERSION_MP(8821a, _mac_reg); +#endif +#if (RTL8192E_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8192E) + version = GET_VERSION_MP(8192e, _mac_reg); #endif -#if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8192E) - Version = GET_VERSION_MP(8192E,_MAC_REG); +#if (RTL8812A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8812) + version = GET_VERSION_MP(8812a, _mac_reg); #endif -#if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - Version = GET_VERSION_MP(8812A,_MAC_REG); +#if (RTL8723D_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8723D) + version = GET_VERSION_MP(8723d, _mac_reg); #endif -#if (RTL8723D_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723D) - Version = GET_VERSION_MP(8723D, _MAC_REG); +/* JJ ADD 20161014 */ +#if (RTL8710B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8710B) + version = GET_VERSION_MP(8710b, _mac_reg); #endif -#endif //(DM_ODM_SUPPORT_TYPE != ODM_AP) -/*1 All platforms support*/ -#if (RTL8188E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188E) - Version = GET_VERSION_MP(8188E,_MAC_REG); +#endif /* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ + + /*1 All platforms support*/ +#if (RTL8188E_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8188E) + version = GET_VERSION_MP(8188e, _mac_reg); #endif -#if (RTL8723B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8723B) - Version = GET_VERSION_MP(8723B, _MAC_REG); +#if (RTL8723B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8723B) + version = GET_VERSION_MP(8723b, _mac_reg); #endif -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A) - Version = GET_VERSION_MP(8814A,_MAC_REG); +#if (RTL8814A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8814A) + version = GET_VERSION_MP(8814a, _mac_reg); #endif -#if (RTL8703B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8703B) - Version = GET_VERSION_MP(8703B, _MAC_REG); +#if (RTL8703B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8703B) + version = GET_VERSION_MP(8703b, _mac_reg); #endif -#if (RTL8188F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188F) - Version = GET_VERSION_MP(8188F, _MAC_REG); +#if (RTL8188F_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8188F) + version = GET_VERSION_MP(8188f, _mac_reg); #endif -#if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) - Version = GET_VERSION_MP(8822B, _MAC_REG); +#if (RTL8822B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8822B) + version = GET_VERSION_MP(8822b, _mac_reg); #endif -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8197F) - Version = GET_VERSION_MP(8197F, _MAC_REG); +#if (RTL8197F_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8197F) + version = GET_VERSION_MP(8197f, _mac_reg); #endif -#if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - Version = GET_VERSION_TC(8821C, _MAC_REG); +#if (RTL8821C_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + version = GET_VERSION(8821c, _mac_reg); #endif - return Version; + return version; } #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) /* For 8822B only!! need to move to FW finally */ /*==============================================*/ -VOID -phydm_ResetPhyInfo( - IN PDM_ODM_T pPhydm, - OUT PODM_PHY_INFO_T pPhyInfo +boolean +phydm_query_is_mu_api( + struct PHY_DM_STRUCT *p_phydm, + u8 ppdu_idx, + u8 *p_data_rate, + u8 *p_gid ) { - pPhyInfo->RxPWDBAll = 0; - pPhyInfo->SignalQuality = 0; - pPhyInfo->BandWidth = 0; - pPhyInfo->RxCount = 0; - ODM_Memory_Set(pPhydm, pPhyInfo->RxMIMOSignalQuality, 0 , 4); - ODM_Memory_Set(pPhydm, pPhyInfo->RxMIMOSignalStrength, 0, 4); - ODM_Memory_Set(pPhydm, pPhyInfo->RxSNR, 0, 4); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->RxPower = -110; - pPhyInfo->RecvSignalPower = -110; - pPhyInfo->BTRxRSSIPercentage = 0; - pPhyInfo->SignalStrength = 0; - pPhyInfo->btCoexPwrAdjust = 0; - pPhyInfo->channel = 0; - pPhyInfo->bMuPacket = 0; - pPhyInfo->bBeamformed = 0; - pPhyInfo->rxsc = 0; - ODM_Memory_Set(pPhydm, pPhyInfo->RxPwr, -110, 4); - ODM_Memory_Set(pPhydm, pPhyInfo->RxMIMOEVMdbm, 0, 4); - ODM_Memory_Set(pPhydm, pPhyInfo->Cfo_short, 0, 8); - ODM_Memory_Set(pPhydm, pPhyInfo->Cfo_tail, 0, 8); -#endif + u8 data_rate = 0, gid = 0; + boolean is_mu = false; + + data_rate = p_phydm->phy_dbg_info.num_of_ppdu[ppdu_idx]; + gid = p_phydm->phy_dbg_info.gid_num[ppdu_idx]; + + if (data_rate & BIT(7)) { + is_mu = true; + data_rate = data_rate & ~(BIT(7)); + } else + is_mu = false; + + *p_data_rate = data_rate; + *p_gid = gid; + + return is_mu; + +} + +void +phydm_reset_phy_info( + struct PHY_DM_STRUCT *p_phydm, + struct _odm_phy_status_info_ *p_phy_info +) +{ + p_phy_info->rx_pwdb_all = 0; + p_phy_info->signal_quality = 0; + p_phy_info->band_width = 0; + p_phy_info->rx_count = 0; + odm_memory_set(p_phydm, p_phy_info->rx_mimo_signal_quality, 0, 4); + odm_memory_set(p_phydm, p_phy_info->rx_mimo_signal_strength, 0, 4); + odm_memory_set(p_phydm, p_phy_info->rx_snr, 0, 4); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + p_phy_info->rx_power = -110; + p_phy_info->recv_signal_power = -110; + p_phy_info->bt_rx_rssi_percentage = 0; + p_phy_info->signal_strength = 0; + p_phy_info->bt_coex_pwr_adjust = 0; + p_phy_info->channel = 0; + p_phy_info->is_mu_packet = 0; + p_phy_info->is_beamformed = 0; + p_phy_info->rxsc = 0; + odm_memory_set(p_phydm, p_phy_info->rx_pwr, -110, 4); + /*odm_memory_set(p_phydm, p_phy_info->rx_mimo_evm_dbm, 0, 4);*/ + odm_memory_set(p_phydm, p_phy_info->cfo_short, 0, 8); + odm_memory_set(p_phydm, p_phy_info->cfo_tail, 0, 8); +#endif + odm_memory_set(p_phydm, p_phy_info->rx_mimo_evm_dbm, 0, 4); } -VOID -phydm_SetPerPathPhyInfo( - IN u1Byte RxPath, - IN s1Byte RxPwr, - IN s1Byte RxEVM, - IN s1Byte Cfo_tail, - IN s1Byte RxSNR, - OUT PODM_PHY_INFO_T pPhyInfo +void +phydm_set_per_path_phy_info( + u8 rx_path, + s8 rx_pwr, + s8 rx_evm, + s8 cfo_tail, + s8 rx_snr, + struct _odm_phy_status_info_ *p_phy_info ) { - u1Byte EVMdBm = 0; - u1Byte EVMPercentage = 0; + u8 evm_dbm = 0; + u8 evm_percentage = 0; /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */ - - if (RxEVM < 0) { + + if (rx_evm < 0) { /* Calculate EVM in dBm */ - EVMdBm = ((u1Byte)(0 - RxEVM) >> 1); + evm_dbm = ((u8)(0 - rx_evm) >> 1); /* Calculate EVM in percentage */ - if (EVMdBm >= 33) - EVMPercentage = 100; - else - EVMPercentage = (EVMdBm << 1) + (EVMdBm); + if (evm_dbm >= 34) + evm_percentage = 100; + else + evm_percentage = (evm_dbm << 1) + (evm_dbm); } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->RxPwr[RxPath] = RxPwr; - pPhyInfo->RxMIMOEVMdbm[RxPath] = EVMdBm; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + p_phy_info->rx_pwr[rx_path] = rx_pwr; /* CFO = CFO_tail * 312.5 / 2^7 ~= CFO tail * 39/512 (kHz)*/ - pPhyInfo->Cfo_tail[RxPath] = Cfo_tail; - pPhyInfo->Cfo_tail[RxPath] = ((pPhyInfo->Cfo_tail[RxPath] << 5) + (pPhyInfo->Cfo_tail[RxPath] << 2) + - (pPhyInfo->Cfo_tail[RxPath] << 1) + (pPhyInfo->Cfo_tail[RxPath])) >> 9; + p_phy_info->cfo_tail[rx_path] = cfo_tail; + p_phy_info->cfo_tail[rx_path] = ((p_phy_info->cfo_tail[rx_path] << 5) + (p_phy_info->cfo_tail[rx_path] << 2) + + (p_phy_info->cfo_tail[rx_path] << 1) + (p_phy_info->cfo_tail[rx_path])) >> 9; #endif + if (evm_dbm == 64) + evm_dbm = 0; /*if 1SS rate, evm_dbm [2nd stream] =64*/ + + p_phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm; - pPhyInfo->RxMIMOSignalStrength[RxPath] = odm_QueryRxPwrPercentage(RxPwr); - pPhyInfo->RxMIMOSignalQuality[RxPath] = EVMPercentage; - pPhyInfo->RxSNR[RxPath] = RxSNR >> 1; + p_phy_info->rx_mimo_signal_strength[rx_path] = odm_query_rx_pwr_percentage(rx_pwr); + p_phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage; + p_phy_info->rx_snr[rx_path] = rx_snr >> 1; -/* - //if (pPktinfo->bPacketMatchBSSID) +#if 0 + /* if (p_pktinfo->is_packet_match_bssid) */ { - DbgPrint("Path (%d)--------\n", RxPath); - DbgPrint("RxPwr = %d, Signal strength = %d\n", pPhyInfo->RxPwr[RxPath], pPhyInfo->RxMIMOSignalStrength[RxPath]); - DbgPrint("EVMdBm = %d, Signal quality = %d\n", pPhyInfo->RxMIMOEVMdbm[RxPath], pPhyInfo->RxMIMOSignalQuality[RxPath]); - DbgPrint("CFO = %d, SNR = %d\n", pPhyInfo->Cfo_tail[RxPath], pPhyInfo->RxSNR[RxPath]); - } -*/ + dbg_print("path (%d)--------\n", rx_path); + dbg_print("rx_pwr = %d, Signal strength = %d\n", p_phy_info->rx_pwr[rx_path], p_phy_info->rx_mimo_signal_strength[rx_path]); + dbg_print("evm_dbm = %d, Signal quality = %d\n", p_phy_info->rx_mimo_evm_dbm[rx_path], p_phy_info->rx_mimo_signal_quality[rx_path]); + dbg_print("CFO = %d, SNR = %d\n", p_phy_info->cfo_tail[rx_path], p_phy_info->rx_snr[rx_path]); + } +#endif } -VOID -phydm_SetCommonPhyInfo( - IN s1Byte RxPower, - IN u1Byte channel, - IN BOOLEAN bBeamformed, - IN BOOLEAN bMuPacket, - IN u1Byte bandwidth, - IN u1Byte signalQuality, - IN u1Byte rxsc, - OUT PODM_PHY_INFO_T pPhyInfo +void +phydm_set_common_phy_info( + s8 rx_power, + u8 channel, + boolean is_beamformed, + boolean is_mu_packet, + u8 bandwidth, + u8 signal_quality, + u8 rxsc, + struct _odm_phy_status_info_ *p_phy_info ) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - pPhyInfo->RxPower = RxPower; /* RSSI in dB */ - pPhyInfo->RecvSignalPower = RxPower; /* RSSI in dB */ - pPhyInfo->channel = channel; /* channel number */ - pPhyInfo->bBeamformed = bBeamformed; /* apply BF */ - pPhyInfo->bMuPacket = bMuPacket; /* MU packet */ - pPhyInfo->rxsc = rxsc; -#endif - pPhyInfo->RxPWDBAll = odm_QueryRxPwrPercentage(RxPower); /* RSSI in percentage */ - pPhyInfo->SignalQuality = signalQuality; /* signal quality */ - pPhyInfo->BandWidth = bandwidth; /* bandwidth */ - -/* - //if (pPktinfo->bPacketMatchBSSID) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + p_phy_info->rx_power = rx_power; /* RSSI in dB */ + p_phy_info->recv_signal_power = rx_power; /* RSSI in dB */ + p_phy_info->channel = channel; /* channel number */ + p_phy_info->is_beamformed = is_beamformed; /* apply BF */ + p_phy_info->is_mu_packet = is_mu_packet; /* MU packet */ + p_phy_info->rxsc = rxsc; +#endif + p_phy_info->rx_pwdb_all = odm_query_rx_pwr_percentage(rx_power); /* RSSI in percentage */ + p_phy_info->signal_quality = signal_quality; /* signal quality */ + p_phy_info->band_width = bandwidth; /* bandwidth */ + +#if 0 + /* if (p_pktinfo->is_packet_match_bssid) */ { - DbgPrint("RxPWDBAll = %d, RxPower = %d, RecvSignalPower = %d\n", pPhyInfo->RxPWDBAll, pPhyInfo->RxPower, pPhyInfo->RecvSignalPower); - DbgPrint("SignalQuality = %d\n", pPhyInfo->SignalQuality); - DbgPrint("bBeamformed = %d, bMuPacket = %d, RxCount = %d\n", pPhyInfo->bBeamformed, pPhyInfo->bMuPacket, pPhyInfo->RxCount + 1); - DbgPrint("channel = %d, rxsc = %d, BandWidth = %d\n", channel, rxsc, bandwidth); + dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", p_phy_info->rx_pwdb_all, p_phy_info->rx_power, p_phy_info->recv_signal_power); + dbg_print("signal_quality = %d\n", p_phy_info->signal_quality); + dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", p_phy_info->is_beamformed, p_phy_info->is_mu_packet, p_phy_info->rx_count + 1); + dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel, rxsc, bandwidth); } -*/ +#endif } -VOID -phydm_GetRxPhyStatusType0( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo, - OUT PODM_PHY_INFO_T pPhyInfo +void +phydm_get_rx_phy_status_type0( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo, + struct _odm_phy_status_info_ *p_phy_info ) { - /* Type 0 is used for cck packet */ + /* type 0 is used for cck packet */ + + struct _phy_status_rpt_jaguar2_type0 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type0 *)p_phy_status; + u8 SQ = 0; + s8 rx_power = p_phy_sta_rpt->pwdb - 110; + + - PPHY_STATUS_RPT_JAGUAR2_TYPE0 pPhyStaRpt = (PPHY_STATUS_RPT_JAGUAR2_TYPE0)pPhyStatus; - u1Byte i, SQ = 0; - s1Byte RxPower = pPhyStaRpt->pwdb - 110; + if (p_dm_odm->support_ic_type & ODM_RTL8723D) { +#if (RTL8723D_SUPPORT == 1) + rx_power = p_phy_sta_rpt->pwdb - 97; +#endif + } +#if (RTL8710B_SUPPORT == 1) + else if (p_dm_odm->support_ic_type & ODM_RTL8710B) + rx_power = p_phy_sta_rpt->pwdb - 97; +#endif + +#if (RTL8821C_SUPPORT == 1) + else if (p_dm_odm->support_ic_type & ODM_RTL8821C) { + if (p_phy_sta_rpt->pwdb >= -57) + rx_power = p_phy_sta_rpt->pwdb - 100; + else + rx_power = p_phy_sta_rpt->pwdb - 102; + } +#endif + + if (p_pktinfo->is_to_self) { + p_dm_odm->ofdm_agc_idx[0] = p_phy_sta_rpt->pwdb; + p_dm_odm->ofdm_agc_idx[1] = 0; + p_dm_odm->ofdm_agc_idx[2] = 0; + p_dm_odm->ofdm_agc_idx[3] = 0; + } + /* Calculate Signal Quality*/ - if (pPktinfo->bPacketMatchBSSID) { - if (pPhyStaRpt->signal_quality >= 64) + if (p_pktinfo->is_packet_match_bssid) { + if (p_phy_sta_rpt->signal_quality >= 64) SQ = 0; - else if (pPhyStaRpt->signal_quality <= 20) + else if (p_phy_sta_rpt->signal_quality <= 20) SQ = 100; else { /* mapping to 2~99% */ - SQ = 64 - pPhyStaRpt->signal_quality; + SQ = 64 - p_phy_sta_rpt->signal_quality; SQ = ((SQ << 3) + SQ) >> 2; } } /* Modify CCK PWDB if old AGC */ - if (pDM_Odm->cck_new_agc == FALSE) { - u1Byte LNA_idx, VGA_idx; + if (p_dm_odm->cck_new_agc == false) { + u8 lna_idx, vga_idx; -#if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - LNA_idx = pPhyStaRpt->lna_l; +#if (RTL8197F_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8197F) + lna_idx = p_phy_sta_rpt->lna_l; else #endif - LNA_idx = ((pPhyStaRpt->lna_h << 3) | pPhyStaRpt->lna_l); - VGA_idx = pPhyStaRpt->vga; - + lna_idx = ((p_phy_sta_rpt->lna_h << 3) | p_phy_sta_rpt->lna_l); + vga_idx = p_phy_sta_rpt->vga; + #if (RTL8723D_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8723D) - RxPower = odm_CCKRSSI_8723D(LNA_idx, VGA_idx); + if (p_dm_odm->support_ic_type & ODM_RTL8723D) + rx_power = odm_cckrssi_8723d(lna_idx, vga_idx); +#endif +/* JJ ADD 20161014 */ +#if (RTL8710B_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8710B) + rx_power = odm_cckrssi_8710b(lna_idx, vga_idx); #endif + #if (RTL8822B_SUPPORT == 1) /* Need to do !! */ - /*if (pDM_Odm->SupportICType & ODM_RTL8822B) */ - /*RxPower = odm_CCKRSSI_8822B(LNA_idx, VGA_idx);*/ + /*if (p_dm_odm->support_ic_type & ODM_RTL8822B) */ + /*rx_power = odm_CCKRSSI_8822B(LNA_idx, VGA_idx);*/ #endif #if (RTL8197F_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8197F) - RxPower = odm_CCKRSSI_8197F(pDM_Odm, LNA_idx, VGA_idx); + if (p_dm_odm->support_ic_type & ODM_RTL8197F) + rx_power = odm_cckrssi_8197f(p_dm_odm, lna_idx, vga_idx); #endif } /* Update CCK packet counter */ - pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; + p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++; + + /*CCK no STBC and LDPC*/ + p_dm_odm->phy_dbg_info.is_ldpc_pkt = false; + p_dm_odm->phy_dbg_info.is_stbc_pkt = false; /* Update Common information */ - phydm_SetCommonPhyInfo(RxPower, pPhyStaRpt->channel, FALSE, - FALSE, ODM_BW20M, SQ, pPhyStaRpt->rxsc, pPhyInfo); + phydm_set_common_phy_info(rx_power, p_phy_sta_rpt->channel, false, + false, ODM_BW20M, SQ, p_phy_sta_rpt->rxsc, p_phy_info); /* Update CCK pwdb */ - phydm_SetPerPathPhyInfo(ODM_RF_PATH_A, RxPower, 0, 0, 0, pPhyInfo); /* Update per-path information */ - - pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->antidx_a; - pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->antidx_b; - pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antidx_c; - pDM_Odm->DM_FatTable.antsel_rx_keep_3 = pPhyStaRpt->antidx_d; -/* - //if (pPktinfo->bPacketMatchBSSID) + phydm_set_per_path_phy_info(ODM_RF_PATH_A, rx_power, 0, 0, 0, p_phy_info); /* Update per-path information */ + + p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_a; + p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b; + p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c; + p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d; +#if 0 + /* if (p_pktinfo->is_packet_match_bssid) */ { - DbgPrint("pwdb = 0x%x, MP gain index = 0x%x, TRSW = 0x%x\n", pPhyStaRpt->pwdb, pPhyStaRpt->gain, pPhyStaRpt->trsw); - DbgPrint("channel = %d, band = %d, rxsc = %d\n", pPhyStaRpt->channel, pPhyStaRpt->band, pPhyStaRpt->rxsc); - DbgPrint("agc_table = 0x%x, agc_rpt 0x%x, bb_power = 0x%x\n", pPhyStaRpt->agc_table, pPhyStaRpt->agc_rpt, pPhyStaRpt->bb_power); - DbgPrint("length = %d, SQ = %d\n", pPhyStaRpt->length, pPhyStaRpt->signal_quality); - DbgPrint("antidx a = 0x%x, b = 0x%x, c = 0x%x, d = 0x%x\n", pPhyStaRpt->antidx_a, pPhyStaRpt->antidx_b, pPhyStaRpt->antidx_c, pPhyStaRpt->antidx_d); - DbgPrint("rsvd_0 = 0x%x, rsvd_1 = 0x%x, rsvd_2 = 0x%x\n", pPhyStaRpt->rsvd_0, pPhyStaRpt->rsvd_1, pPhyStaRpt->rsvd_2); - DbgPrint("rsvd_3 = 0x%x, rsvd_4 = 0x%x, rsvd_5 = 0x%x\n", pPhyStaRpt->rsvd_3, pPhyStaRpt->rsvd_4, pPhyStaRpt->rsvd_5); - DbgPrint("rsvd_6 = 0x%x, rsvd_7 = 0x%x, rsvd_8 = 0x%x\n", pPhyStaRpt->rsvd_6, pPhyStaRpt->rsvd_7, pPhyStaRpt->rsvd_8); - } -*/ + dbg_print("pwdb = 0x%x, MP gain index = 0x%x, TRSW = 0x%x\n", p_phy_sta_rpt->pwdb, p_phy_sta_rpt->gain, p_phy_sta_rpt->trsw); + dbg_print("channel = %d, band = %d, rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->rxsc); + dbg_print("agc_table = 0x%x, agc_rpt 0x%x, bb_power = 0x%x\n", p_phy_sta_rpt->agc_table, p_phy_sta_rpt->agc_rpt, p_phy_sta_rpt->bb_power); + dbg_print("length = %d, SQ = %d\n", p_phy_sta_rpt->length, p_phy_sta_rpt->signal_quality); + dbg_print("antidx a = 0x%x, b = 0x%x, c = 0x%x, d = 0x%x\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d); + dbg_print("rsvd_0 = 0x%x, rsvd_1 = 0x%x, rsvd_2 = 0x%x\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2); + dbg_print("rsvd_3 = 0x%x, rsvd_4 = 0x%x, rsvd_5 = 0x%x\n", p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5); + dbg_print("rsvd_6 = 0x%x, rsvd_7 = 0x%x, rsvd_8 = 0x%x\n", p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7, p_phy_sta_rpt->rsvd_8); + } +#endif } -VOID -phydm_GetRxPhyStatusType1( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo, - OUT PODM_PHY_INFO_T pPhyInfo +void +phydm_get_rx_phy_status_type1( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo, + struct _odm_phy_status_info_ *p_phy_info ) { - /* Type 1 is used for ofdm packet */ + /* type 1 is used for ofdm packet */ - PPHY_STATUS_RPT_JAGUAR2_TYPE1 pPhyStaRpt = (PPHY_STATUS_RPT_JAGUAR2_TYPE1)pPhyStatus; - s1Byte rx_pwr_db = -120; - u1Byte i, rxsc, bw = ODM_BW20M, RxCount = 0; - BOOLEAN bMU; + struct _phy_status_rpt_jaguar2_type1 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type1 *)p_phy_status; + s8 rx_pwr_db = -120; + u8 i, rxsc, bw = ODM_BW20M, rx_count = 0; + boolean is_mu; + u8 num_ss; /* Update OFDM packet counter */ - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; /* Update per-path information */ for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (pDM_Odm->RXAntStatus & BIT(i)) { - s1Byte rx_path_pwr_db; + if (p_dm_odm->rx_ant_status & BIT(i)) { + s8 rx_path_pwr_db; /* RX path counter */ - RxCount++; + rx_count++; /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ /* EVM report is reported by stream, not path */ - rx_path_pwr_db = pPhyStaRpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ - phydm_SetPerPathPhyInfo(i, rx_path_pwr_db, pPhyStaRpt->rxevm[RxCount - 1], - pPhyStaRpt->cfo_tail[i], pPhyStaRpt->rxsnr[i], pPhyInfo); + rx_path_pwr_db = p_phy_sta_rpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ + + if (p_pktinfo->is_to_self) + p_dm_odm->ofdm_agc_idx[i] = p_phy_sta_rpt->pwdb[i]; + + phydm_set_per_path_phy_info(i, rx_path_pwr_db, p_phy_sta_rpt->rxevm[rx_count - 1], + p_phy_sta_rpt->cfo_tail[i], p_phy_sta_rpt->rxsnr[i], p_phy_info); /* search maximum pwdb */ if (rx_path_pwr_db > rx_pwr_db) @@ -3127,27 +3444,31 @@ phydm_GetRxPhyStatusType1( } /* mapping RX counter from 1~4 to 0~3 */ - if (RxCount > 0) - pPhyInfo->RxCount = RxCount - 1; - + if (rx_count > 0) + p_phy_info->rx_count = rx_count - 1; + /* Check if MU packet or not */ - if ((pPhyStaRpt->gid != 0) && (pPhyStaRpt->gid != 63)) { - bMU = TRUE; - pDM_Odm->PhyDbgInfo.NumQryMuPkt++; + if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63)) { + is_mu = true; + p_dm_odm->phy_dbg_info.num_qry_mu_pkt++; } else - bMU = FALSE; + is_mu = false; - /* Count BF packet */ - pDM_Odm->PhyDbgInfo.NumQryBfPkt = pDM_Odm->PhyDbgInfo.NumQryBfPkt + pPhyStaRpt->beamformed; + /* count BF packet */ + p_dm_odm->phy_dbg_info.num_qry_bf_pkt = p_dm_odm->phy_dbg_info.num_qry_bf_pkt + p_phy_sta_rpt->beamformed; + + /*STBC or LDPC pkt*/ + p_dm_odm->phy_dbg_info.is_ldpc_pkt = p_phy_sta_rpt->ldpc; + p_dm_odm->phy_dbg_info.is_stbc_pkt = p_phy_sta_rpt->stbc; /* Check sub-channel */ - if ((pPktinfo->DataRate > ODM_RATE11M) && (pPktinfo->DataRate < ODM_RATEMCS0)) - rxsc = pPhyStaRpt->l_rxsc; + if ((p_pktinfo->data_rate > ODM_RATE11M) && (p_pktinfo->data_rate < ODM_RATEMCS0)) + rxsc = p_phy_sta_rpt->l_rxsc; else - rxsc = pPhyStaRpt->ht_rxsc; + rxsc = p_phy_sta_rpt->ht_rxsc; /* Check RX bandwidth */ - if (pDM_Odm->SupportICType & ODM_RTL8822B) { + if (p_dm_odm->support_ic_type & ODM_RTL8822B) { if ((rxsc >= 1) && (rxsc <= 8)) bw = ODM_BW20M; else if ((rxsc >= 9) && (rxsc <= 12)) @@ -3155,9 +3476,9 @@ phydm_GetRxPhyStatusType1( else if (rxsc >= 13) bw = ODM_BW80M; else - bw = pPhyStaRpt->rf_mode; - } else if (pDM_Odm->SupportICType & (ODM_RTL8197F|ODM_RTL8723D)) { - if (pPhyStaRpt->rf_mode == 0) + bw = p_phy_sta_rpt->rf_mode; + } else if (p_dm_odm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D | ODM_RTL8710B)) {/* JJ ADD 20161014 */ + if (p_phy_sta_rpt->rf_mode == 0) bw = ODM_BW20M; else if ((rxsc == 1) || (rxsc == 2)) bw = ODM_BW20M; @@ -3166,81 +3487,78 @@ phydm_GetRxPhyStatusType1( } /* Update packet information */ - phydm_SetCommonPhyInfo(rx_pwr_db, pPhyStaRpt->channel, (BOOLEAN)pPhyStaRpt->beamformed, - bMU, bw, odm_EVMdbToPercentage(pPhyStaRpt->rxevm[0]), rxsc, pPhyInfo); - ODM_ParsingCFO(pDM_Odm, pPktinfo, pPhyStaRpt->cfo_tail); - pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->antidx_a; - pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->antidx_b; - pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antidx_c; - pDM_Odm->DM_FatTable.antsel_rx_keep_3 = pPhyStaRpt->antidx_d; - - if (pPktinfo->bPacketMatchBSSID) { -/* - DbgPrint("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d, rf_mode = %d\n", pPhyStaRpt->channel, pPhyStaRpt->band, pPhyStaRpt->l_rxsc, pPhyStaRpt->ht_rxsc, pPhyStaRpt->rf_mode); - DbgPrint("Antidx A = %d, B = %d, C = %d, D = %d\n", pPhyStaRpt->antidx_a, pPhyStaRpt->antidx_b, pPhyStaRpt->antidx_c, pPhyStaRpt->antidx_d); - DbgPrint("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->pwdb[0], pPhyStaRpt->pwdb[1], pPhyStaRpt->pwdb[2], pPhyStaRpt->pwdb[3]); - DbgPrint("EVM A: %d, B: %d, C: %d, D: %d\n", pPhyStaRpt->rxevm[0], pPhyStaRpt->rxevm[1], pPhyStaRpt->rxevm[2], pPhyStaRpt->rxevm[3]); - DbgPrint("SNR A: %d, B: %d, C: %d, D: %d\n", pPhyStaRpt->rxsnr[0], pPhyStaRpt->rxsnr[1], pPhyStaRpt->rxsnr[2], pPhyStaRpt->rxsnr[3]); - DbgPrint("CFO A: %d, B: %d, C: %d, D: %d\n", pPhyStaRpt->cfo_tail[0], pPhyStaRpt->cfo_tail[1], pPhyStaRpt->cfo_tail[2], pPhyStaRpt->cfo_tail[3]); - DbgPrint("paid = %d, gid = %d, length = %d\n", (pPhyStaRpt->paid + (pPhyStaRpt->paid_msb<<8)), pPhyStaRpt->gid, pPhyStaRpt->lsig_length); - DbgPrint("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", pPhyStaRpt->ldpc, pPhyStaRpt->stbc, pPhyStaRpt->beamformed, pPhyStaRpt->gnt_bt, pPhyStaRpt->hw_antsw_occu); - DbgPrint("NBI: %d, pos: %d\n", pPhyStaRpt->nb_intf_flag, (pPhyStaRpt->intf_pos + (pPhyStaRpt->intf_pos_msb<<8))); - DbgPrint("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", pPhyStaRpt->rsvd_0, pPhyStaRpt->rsvd_1, pPhyStaRpt->rsvd_2, pPhyStaRpt->rsvd_3, pPhyStaRpt->rsvd_4, pPhyStaRpt->rsvd_5); -*/ - if ((pPhyStaRpt->gid != 0) && (pPhyStaRpt->gid != 63)) { - if (pPktinfo->DataRate >= ODM_RATEVHTSS1MCS0) - pDM_Odm->PhyDbgInfo.NumQryMuVhtPkt[pPktinfo->DataRate - 0x2C]++; - } else { - if (pPktinfo->DataRate >= ODM_RATEVHTSS1MCS0) - pDM_Odm->PhyDbgInfo.NumQryVhtPkt[pPktinfo->DataRate - 0x2C]++; - } + phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (boolean)p_phy_sta_rpt->beamformed, + is_mu, bw, odm_evm_db_to_percentage(p_phy_sta_rpt->rxevm[0]), rxsc, p_phy_info); + + num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); + + odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->cfo_tail, num_ss); + p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_a; + p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b; + p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c; + p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d; + + #if 0 + if (p_pktinfo->is_packet_match_bssid) { + + dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d, rf_mode = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc, p_phy_sta_rpt->rf_mode); + dbg_print("Antidx A = %d, B = %d, C = %d, D = %d\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d); + dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]); + dbg_print("EVM A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->rxevm[0], p_phy_sta_rpt->rxevm[1], p_phy_sta_rpt->rxevm[2], p_phy_sta_rpt->rxevm[3]); + dbg_print("SNR A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->rxsnr[0], p_phy_sta_rpt->rxsnr[1], p_phy_sta_rpt->rxsnr[2], p_phy_sta_rpt->rxsnr[3]); + dbg_print("CFO A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->cfo_tail[0], p_phy_sta_rpt->cfo_tail[1], p_phy_sta_rpt->cfo_tail[2], p_phy_sta_rpt->cfo_tail[3]); + dbg_print("paid = %d, gid = %d, length = %d\n", (p_phy_sta_rpt->paid + (p_phy_sta_rpt->paid_msb<<8)), p_phy_sta_rpt->gid, p_phy_sta_rpt->lsig_length); + dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu); + dbg_print("NBI: %d, pos: %d\n", p_phy_sta_rpt->nb_intf_flag, (p_phy_sta_rpt->intf_pos + (p_phy_sta_rpt->intf_pos_msb<<8))); + dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5); + } -/* - DbgPrint("phydm_GetRxPhyStatusType1 pPktinfo->bPacketMatchBSSID = %d\n", pPktinfo->bPacketMatchBSSID); - DbgPrint("pPktinfo->DataRate = 0x%x\n", pPktinfo->DataRate); -*/ + + dbg_print("phydm_get_rx_phy_status_type1 p_pktinfo->is_packet_match_bssid = %d\n", p_pktinfo->is_packet_match_bssid); + dbg_print("p_pktinfo->data_rate = 0x%x\n", p_pktinfo->data_rate); + #endif } -VOID -phydm_GetRxPhyStatusType2( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo, - OUT PODM_PHY_INFO_T pPhyInfo +void +phydm_get_rx_phy_status_type2( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo, + struct _odm_phy_status_info_ *p_phy_info ) { - PPHY_STATUS_RPT_JAGUAR2_TYPE2 pPhyStaRpt = (PPHY_STATUS_RPT_JAGUAR2_TYPE2)pPhyStatus; - s1Byte rx_pwr_db = -120; - u1Byte i, rxsc, bw = ODM_BW20M, RxCount = 0; + struct _phy_status_rpt_jaguar2_type2 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type2 *)p_phy_status; + s8 rx_pwr_db = -120; + u8 i, rxsc, bw = ODM_BW20M, rx_count = 0; /* Update OFDM packet counter */ - pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; /* Update per-path information */ for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (pDM_Odm->RXAntStatus & BIT(i)) { - s1Byte rx_path_pwr_db; + if (p_dm_odm->rx_ant_status & BIT(i)) { + s8 rx_path_pwr_db; /* RX path counter */ - RxCount++; + rx_count++; /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ #if (RTL8197F_SUPPORT == 1) - if ((pDM_Odm->SupportICType & ODM_RTL8197F) && (pPhyStaRpt->pwdb[i] == 0x7f)) { /*for 97f workaround*/ - - if (i == ODM_RF_PATH_A) { - rx_path_pwr_db = (pPhyStaRpt->gain_a)<<1; - rx_path_pwr_db = rx_path_pwr_db - 110; - } else if (i == ODM_RF_PATH_B) { - rx_path_pwr_db = (pPhyStaRpt->gain_b)<<1; - rx_path_pwr_db = rx_path_pwr_db - 110; + if ((p_dm_odm->support_ic_type & ODM_RTL8197F) && (p_phy_sta_rpt->pwdb[i] == 0x7f)) { /*for 97f workaround*/ + + if (i == ODM_RF_PATH_A) { + rx_path_pwr_db = (p_phy_sta_rpt->gain_a) << 1; + rx_path_pwr_db = rx_path_pwr_db - 110; + } else if (i == ODM_RF_PATH_B) { + rx_path_pwr_db = (p_phy_sta_rpt->gain_b) << 1; + rx_path_pwr_db = rx_path_pwr_db - 110; + } else + rx_path_pwr_db = 0; } else - rx_path_pwr_db = 0; - } else #endif - rx_path_pwr_db = pPhyStaRpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ - - phydm_SetPerPathPhyInfo(i, rx_path_pwr_db, 0, 0, 0, pPhyInfo); + rx_path_pwr_db = p_phy_sta_rpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ + + phydm_set_per_path_phy_info(i, rx_path_pwr_db, 0, 0, 0, p_phy_info); /* search maximum pwdb */ if (rx_path_pwr_db > rx_pwr_db) @@ -3249,19 +3567,23 @@ phydm_GetRxPhyStatusType2( } /* mapping RX counter from 1~4 to 0~3 */ - if (RxCount > 0) - pPhyInfo->RxCount = RxCount - 1; - + if (rx_count > 0) + p_phy_info->rx_count = rx_count - 1; + /* Check RX sub-channel */ - if ((pPktinfo->DataRate > ODM_RATE11M) && (pPktinfo->DataRate < ODM_RATEMCS0)) - rxsc = pPhyStaRpt->l_rxsc; + if ((p_pktinfo->data_rate > ODM_RATE11M) && (p_pktinfo->data_rate < ODM_RATEMCS0)) + rxsc = p_phy_sta_rpt->l_rxsc; else - rxsc = pPhyStaRpt->ht_rxsc; + rxsc = p_phy_sta_rpt->ht_rxsc; + + /*STBC or LDPC pkt*/ + p_dm_odm->phy_dbg_info.is_ldpc_pkt = p_phy_sta_rpt->ldpc; + p_dm_odm->phy_dbg_info.is_stbc_pkt = p_phy_sta_rpt->stbc; /* Check RX bandwidth */ /* the BW information of sc=0 is useless, because there is no information of RF mode*/ - if (pDM_Odm->SupportICType & ODM_RTL8822B) { + if (p_dm_odm->support_ic_type & ODM_RTL8822B) { if ((rxsc >= 1) && (rxsc <= 8)) bw = ODM_BW20M; else if ((rxsc >= 9) && (rxsc <= 12)) @@ -3270,7 +3592,7 @@ phydm_GetRxPhyStatusType2( bw = ODM_BW80M; else bw = ODM_BW20M; - } else if (pDM_Odm->SupportICType & (ODM_RTL8197F|ODM_RTL8723D)) { + } else if (p_dm_odm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D | ODM_RTL8710B)) {/* JJ ADD 20161014 */ if (rxsc == 3) bw = ODM_BW40M; else if ((rxsc == 1) || (rxsc == 2)) @@ -3280,89 +3602,99 @@ phydm_GetRxPhyStatusType2( } /* Update packet information */ - phydm_SetCommonPhyInfo(rx_pwr_db, pPhyStaRpt->channel, (BOOLEAN)pPhyStaRpt->beamformed, - FALSE, bw, 0, rxsc, pPhyInfo); + phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (boolean)p_phy_sta_rpt->beamformed, + false, bw, 0, rxsc, p_phy_info); -/* - //if (pPktinfo->bPacketMatchBSSID) +#if 0 + /* if (p_pktinfo->is_packet_match_bssid) */ { - DbgPrint("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d\n", pPhyStaRpt->channel, pPhyStaRpt->band, pPhyStaRpt->l_rxsc, pPhyStaRpt->ht_rxsc); - DbgPrint("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->pwdb[0], pPhyStaRpt->pwdb[1], pPhyStaRpt->pwdb[2], pPhyStaRpt->pwdb[3]); - DbgPrint("Agc table A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->agc_table_a, pPhyStaRpt->agc_table_b, pPhyStaRpt->agc_table_c, pPhyStaRpt->agc_table_d); - DbgPrint("Gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->gain_a, pPhyStaRpt->gain_b, pPhyStaRpt->gain_c, pPhyStaRpt->gain_d); - DbgPrint("TRSW A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->trsw_a, pPhyStaRpt->trsw_b, pPhyStaRpt->trsw_c, pPhyStaRpt->trsw_d); - DbgPrint("AAGC step A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->aagc_step_a, pPhyStaRpt->aagc_step_b, pPhyStaRpt->aagc_step_c, pPhyStaRpt->aagc_step_d); - DbgPrint("HT AAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->ht_aagc_gain[0], pPhyStaRpt->ht_aagc_gain[1], pPhyStaRpt->ht_aagc_gain[2], pPhyStaRpt->ht_aagc_gain[3]); - DbgPrint("DAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->dagc_gain[0], pPhyStaRpt->dagc_gain[1], pPhyStaRpt->dagc_gain[2], pPhyStaRpt->dagc_gain[3]); - DbgPrint("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", pPhyStaRpt->ldpc, pPhyStaRpt->stbc, pPhyStaRpt->beamformed, pPhyStaRpt->gnt_bt, pPhyStaRpt->hw_antsw_occu); - DbgPrint("counter: %d, syn_count: %d\n", pPhyStaRpt->counter, pPhyStaRpt->syn_count); - DbgPrint("cnt_cca2agc_rdy: %d, cnt_pw2cca: %d, shift_l_map\n", pPhyStaRpt->cnt_cca2agc_rdy, pPhyStaRpt->cnt_pw2cca, pPhyStaRpt->shift_l_map); - DbgPrint("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", pPhyStaRpt->rsvd_0, pPhyStaRpt->rsvd_1, pPhyStaRpt->rsvd_2, pPhyStaRpt->rsvd_3, pPhyStaRpt->rsvd_4); - DbgPrint("rsvd_5 = %d, rsvd_6 = %d, rsvd_6 = %d\n", pPhyStaRpt->rsvd_5, pPhyStaRpt->rsvd_6, pPhyStaRpt->rsvd_7); - } -*/ + dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc); + dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]); + dbg_print("Agc table A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->agc_table_a, p_phy_sta_rpt->agc_table_b, p_phy_sta_rpt->agc_table_c, p_phy_sta_rpt->agc_table_d); + dbg_print("Gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->gain_a, p_phy_sta_rpt->gain_b, p_phy_sta_rpt->gain_c, p_phy_sta_rpt->gain_d); + dbg_print("TRSW A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->trsw_a, p_phy_sta_rpt->trsw_b, p_phy_sta_rpt->trsw_c, p_phy_sta_rpt->trsw_d); + dbg_print("AAGC step A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->aagc_step_a, p_phy_sta_rpt->aagc_step_b, p_phy_sta_rpt->aagc_step_c, p_phy_sta_rpt->aagc_step_d); + dbg_print("HT AAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->ht_aagc_gain[0], p_phy_sta_rpt->ht_aagc_gain[1], p_phy_sta_rpt->ht_aagc_gain[2], p_phy_sta_rpt->ht_aagc_gain[3]); + dbg_print("DAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->dagc_gain[0], p_phy_sta_rpt->dagc_gain[1], p_phy_sta_rpt->dagc_gain[2], p_phy_sta_rpt->dagc_gain[3]); + dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu); + dbg_print("counter: %d, syn_count: %d\n", p_phy_sta_rpt->counter, p_phy_sta_rpt->syn_count); + dbg_print("cnt_cca2agc_rdy: %d, cnt_pw2cca: %d, shift_l_map\n", p_phy_sta_rpt->cnt_cca2agc_rdy, p_phy_sta_rpt->cnt_pw2cca, p_phy_sta_rpt->shift_l_map); + dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4); + dbg_print("rsvd_5 = %d, rsvd_6 = %d, rsvd_6 = %d\n", p_phy_sta_rpt->rsvd_5, p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7); + } +#endif } -VOID -phydm_GetRxPhyStatusType5( - IN pu1Byte pPhyStatus +void +phydm_get_rx_phy_status_type5( + u8 *p_phy_status ) { -/* - DbgPrint("DW0: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 3), *(pPhyStatus + 2), *(pPhyStatus + 1), *(pPhyStatus + 0)); - DbgPrint("DW1: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 7), *(pPhyStatus + 6), *(pPhyStatus + 5), *(pPhyStatus + 4)); - DbgPrint("DW2: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 11), *(pPhyStatus + 10), *(pPhyStatus + 9), *(pPhyStatus + 8)); - DbgPrint("DW3: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 15), *(pPhyStatus + 14), *(pPhyStatus + 13), *(pPhyStatus + 12)); - DbgPrint("DW4: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 19), *(pPhyStatus + 18), *(pPhyStatus + 17), *(pPhyStatus + 16)); - DbgPrint("DW5: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 23), *(pPhyStatus + 22), *(pPhyStatus + 21), *(pPhyStatus + 20)); - DbgPrint("DW6: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 27), *(pPhyStatus + 26), *(pPhyStatus + 25), *(pPhyStatus + 24)); -*/ + /* + dbg_print("DW0: 0x%02x%02x%02x%02x\n", *(p_phy_status + 3), *(p_phy_status + 2), *(p_phy_status + 1), *(p_phy_status + 0)); + dbg_print("DW1: 0x%02x%02x%02x%02x\n", *(p_phy_status + 7), *(p_phy_status + 6), *(p_phy_status + 5), *(p_phy_status + 4)); + dbg_print("DW2: 0x%02x%02x%02x%02x\n", *(p_phy_status + 11), *(p_phy_status + 10), *(p_phy_status + 9), *(p_phy_status + 8)); + dbg_print("DW3: 0x%02x%02x%02x%02x\n", *(p_phy_status + 15), *(p_phy_status + 14), *(p_phy_status + 13), *(p_phy_status + 12)); + dbg_print("DW4: 0x%02x%02x%02x%02x\n", *(p_phy_status + 19), *(p_phy_status + 18), *(p_phy_status + 17), *(p_phy_status + 16)); + dbg_print("DW5: 0x%02x%02x%02x%02x\n", *(p_phy_status + 23), *(p_phy_status + 22), *(p_phy_status + 21), *(p_phy_status + 20)); + dbg_print("DW6: 0x%02x%02x%02x%02x\n", *(p_phy_status + 27), *(p_phy_status + 26), *(p_phy_status + 25), *(p_phy_status + 24)); + */ } -VOID -phydm_Process_RSSIForDMNewType( - IN OUT PDM_ODM_T pDM_Odm, - IN PODM_PHY_INFO_T pPhyInfo, - IN PODM_PACKET_INFO_T pPktinfo - ) +void +phydm_process_rssi_for_dm_new_type( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + struct _odm_per_pkt_info_ *p_pktinfo +) { - s4Byte UndecoratedSmoothedPWDB, AccumulatePWDB; - u4Byte RSSI_Ave; - u1Byte i; - PSTA_INFO_T pEntry; - u1Byte scaling_factor = 4; - - if (pPktinfo->StationID >= ODM_ASSOCIATE_ENTRY_NUM) + s32 undecorated_smoothed_pwdb, accumulate_pwdb; + u32 rssi_ave; + u8 i; + struct sta_info *p_entry; + u8 scaling_factor = 4; + + if (p_pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) return; - pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID]; + p_entry = p_dm_odm->p_odm_sta_info[p_pktinfo->station_id]; - if (!IS_STA_VALID(pEntry)) + if (!IS_STA_VALID(p_entry)) return; - if ((!pPktinfo->bPacketMatchBSSID))/*data frame only*/ + if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/ return; - if (pPktinfo->bPacketBeacon) - pDM_Odm->PhyDbgInfo.NumQryBeaconPkt++; - - if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) { - u4Byte RSSI_linear = 0; + if (p_pktinfo->is_packet_beacon) + p_dm_odm->phy_dbg_info.num_qry_beacon_pkt++; + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + if (p_dm_odm->support_ability & ODM_BB_ANT_DIV) + odm_process_rssi_for_ant_div(p_dm_odm, p_phy_info, p_pktinfo); +#endif + +#if (CONFIG_DYNAMIC_RX_PATH == 1) + phydm_process_phy_status_for_dynamic_rx_path(p_dm_odm, p_phy_info, p_pktinfo); + dbg_print("====>\n"); +#endif + + if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_beacon) { + u32 RSSI_linear = 0; - pDM_Odm->RxRate = pPktinfo->DataRate; - UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; - AccumulatePWDB = pDM_Odm->AccumulatePWDB[pPktinfo->StationID]; - pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; - pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; - pDM_Odm->RSSI_C = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_C]; - pDM_Odm->RSSI_D = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_D]; + p_dm_odm->rx_rate = p_pktinfo->data_rate; + undecorated_smoothed_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; + accumulate_pwdb = p_dm_odm->accumulate_pwdb[p_pktinfo->station_id]; + p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; + p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; + p_dm_odm->RSSI_C = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C]; + p_dm_odm->RSSI_D = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D]; for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (pPhyInfo->RxMIMOSignalStrength[i] != 0) - RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[i]); + if (p_phy_info->rx_mimo_signal_strength[i] != 0) + RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[i]); } - switch (pPhyInfo->RxCount + 1) { + switch (p_phy_info->rx_count + 1) { case 2: RSSI_linear = (RSSI_linear >> 1); break; @@ -3373,168 +3705,169 @@ phydm_Process_RSSIForDMNewType( RSSI_linear = (RSSI_linear >> 2); break; } - RSSI_Ave = odm_ConvertTo_dB(RSSI_linear); + rssi_ave = odm_convert_to_db(RSSI_linear); - if (UndecoratedSmoothedPWDB <= 0) { - AccumulatePWDB = (pPhyInfo->RxPWDBAll << scaling_factor); - UndecoratedSmoothedPWDB = pPhyInfo->RxPWDBAll; + if (undecorated_smoothed_pwdb <= 0) { + accumulate_pwdb = (p_phy_info->rx_pwdb_all << scaling_factor); + undecorated_smoothed_pwdb = p_phy_info->rx_pwdb_all; } else { - AccumulatePWDB = AccumulatePWDB - (AccumulatePWDB>>scaling_factor) + RSSI_Ave; - UndecoratedSmoothedPWDB = (AccumulatePWDB + (1<<(scaling_factor - 1)))>>scaling_factor; + accumulate_pwdb = accumulate_pwdb - (accumulate_pwdb >> scaling_factor) + rssi_ave; + undecorated_smoothed_pwdb = (accumulate_pwdb + (1 << (scaling_factor - 1))) >> scaling_factor; } #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == -1) - phydm_ra_rssi_rpt_wk(pDM_Odm); +#ifndef DM_ODM_CE_MAC80211 + if (p_entry->rssi_stat.undecorated_smoothed_pwdb == -1) + phydm_ra_rssi_rpt_wk(p_dm_odm); #endif - pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; - pDM_Odm->AccumulatePWDB[pPktinfo->StationID] = AccumulatePWDB; +#endif + p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb; + p_dm_odm->accumulate_pwdb[p_pktinfo->station_id] = accumulate_pwdb; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - if (pPktinfo->StationID == 0) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); - - pHalData->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if (p_pktinfo->station_id == 0) { + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); + + p_hal_data->UndecoratedSmoothedPWDB = undecorated_smoothed_pwdb; } #endif } } -VOID -phydm_RxPhyStatusNewType( - IN PDM_ODM_T pPhydm, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo, - OUT PODM_PHY_INFO_T pPhyInfo +void +phydm_rx_phy_status_new_type( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo, + struct _odm_phy_status_info_ *p_phy_info ) { - u1Byte phy_status_type = (*pPhyStatus & 0xf); + u8 phy_status_type = (*p_phy_status & 0xf); + + /*dbg_print("phydm_rx_phy_status_new_type================> (page: %d)\n", phy_status_type);*/ - /*DbgPrint("phydm_RxPhyStatusNewType================> (page: %d)\n", phy_status_type);*/ - /* Memory reset */ - phydm_ResetPhyInfo(pPhydm, pPhyInfo); + phydm_reset_phy_info(p_dm_odm, p_phy_info); + p_dm_odm->rate_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); /* Phy status parsing */ switch (phy_status_type) { case 0: { - phydm_GetRxPhyStatusType0(pPhydm, pPhyStatus, pPktinfo, pPhyInfo); + phydm_get_rx_phy_status_type0(p_dm_odm, p_phy_status, p_pktinfo, p_phy_info); break; } case 1: { - phydm_GetRxPhyStatusType1(pPhydm, pPhyStatus, pPktinfo, pPhyInfo); + phydm_get_rx_phy_status_type1(p_dm_odm, p_phy_status, p_pktinfo, p_phy_info); break; } case 2: { - phydm_GetRxPhyStatusType2(pPhydm, pPhyStatus, pPktinfo, pPhyInfo); + phydm_get_rx_phy_status_type2(p_dm_odm, p_phy_status, p_pktinfo, p_phy_info); break; } -/* +#if 0 case 5: { - phydm_GetRxPhyStatusType5(pPhyStatus); + phydm_get_rx_phy_status_type5(p_phy_status); return; } -*/ +#endif default: return; } + + if (p_pktinfo->is_packet_match_bssid) { + phydm_avg_rssi_for_ss(p_dm_odm, p_phy_info, p_pktinfo); + phydm_rx_statistic_cal(p_dm_odm, p_phy_status, p_pktinfo); + } - #if RTL8723D_SUPPORT == 1 - if (pPhydm->SupportAbility & ODM_BB_ANT_DIV) { - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ODM_Process_RSSIForAntDiv(pPhydm, pPhyInfo, pPktinfo); - #endif - } - #endif - /* Update signal strength to UI, and pPhyInfo->RxPWDBAll is the maximum RSSI of all path */ + /* Update signal strength to UI, and p_phy_info->rx_pwdb_all is the maximum RSSI of all path */ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pPhyInfo->SignalStrength = SignalScaleProc(pPhydm->Adapter, pPhyInfo->RxPWDBAll, FALSE, FALSE); + p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, p_phy_info->rx_pwdb_all, false, false); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pPhydm, pPhyInfo->RxPWDBAll)); + p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, p_phy_info->rx_pwdb_all)); #endif /* Calculate average RSSI and smoothed RSSI */ - phydm_Process_RSSIForDMNewType(pPhydm, pPhyInfo, pPktinfo); + phydm_process_rssi_for_dm_new_type(p_dm_odm, p_phy_info, p_pktinfo); } /*==============================================*/ #endif -u4Byte +u32 query_phydm_trx_capability( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ) { - u4Byte value32 = 0xFFFFFFFF; + u32 value32 = 0xFFFFFFFF; - #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - value32 = query_phydm_trx_capability_8821c(pDM_Odm); - #endif +#if (RTL8821C_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_trx_capability_8821c(p_dm_odm); +#endif return value32; } -u4Byte +u32 query_phydm_stbc_capability( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ) { - u4Byte value32 = 0xFFFFFFFF; + u32 value32 = 0xFFFFFFFF; - #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - value32 = query_phydm_stbc_capability_8821c(pDM_Odm); - #endif +#if (RTL8821C_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_stbc_capability_8821c(p_dm_odm); +#endif return value32; } -u4Byte +u32 query_phydm_ldpc_capability( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ) { - u4Byte value32 = 0xFFFFFFFF; + u32 value32 = 0xFFFFFFFF; - #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - value32 = query_phydm_ldpc_capability_8821c(pDM_Odm); - #endif +#if (RTL8821C_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_ldpc_capability_8821c(p_dm_odm); +#endif return value32; } -u4Byte +u32 query_phydm_txbf_parameters( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ) { - u4Byte value32 = 0xFFFFFFFF; + u32 value32 = 0xFFFFFFFF; - #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - value32 = query_phydm_txbf_parameters_8821c(pDM_Odm); - #endif +#if (RTL8821C_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_txbf_parameters_8821c(p_dm_odm); +#endif return value32; } -u4Byte +u32 query_phydm_txbf_capability( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ) { - u4Byte value32 = 0xFFFFFFFF; + u32 value32 = 0xFFFFFFFF; - #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - value32 = query_phydm_txbf_capability_8821c(pDM_Odm); - #endif +#if (RTL8821C_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_txbf_capability_8821c(p_dm_odm); +#endif return value32; } diff --git a/hal/phydm/phydm_hwconfig.h b/hal/phydm/phydm_hwconfig.h index 9379732..ff317f0 100644 --- a/hal/phydm/phydm_hwconfig.h +++ b/hal/phydm/phydm_hwconfig.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,555 +11,570 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HALHWOUTSRC_H__ #define __HALHWOUTSRC_H__ -/*--------------------------Define -------------------------------------------*/ +/*--------------------------Define -------------------------------------------*/ #define CCK_RSSI_INIT_COUNT 5 #define RA_RSSI_STATE_INIT 0 #define RA_RSSI_STATE_SEND 1 #define RA_RSSI_STATE_HOLD 2 -#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \ - sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte))) -#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \ - sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte))) +#define CFO_HW_RPT_2_MHZ(val) ((val<<1) + (val>>1)) +/* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */ + +#define AGC_DIFF_CONFIG_MP(ic, band) (odm_read_and_config_mp_##ic##_agc_tab_diff(p_dm_odm, array_mp_##ic##_agc_tab_diff_##band, \ + sizeof(array_mp_##ic##_agc_tab_diff_##band)/sizeof(u32))) +#define AGC_DIFF_CONFIG_TC(ic, band) (odm_read_and_config_tc_##ic##_agc_tab_diff(p_dm_odm, array_tc_##ic##_agc_tab_diff_##band, \ + sizeof(array_tc_##ic##_agc_tab_diff_##band)/sizeof(u32))) #define AGC_DIFF_CONFIG(ic, band) do {\ - if (pDM_Odm->bIsMPChip)\ - AGC_DIFF_CONFIG_MP(ic,band);\ - else\ - AGC_DIFF_CONFIG_TC(ic,band);\ - } while(0) - - -//============================================================ -// structure and define -//============================================================ - -__PACK typedef struct _Phy_Rx_AGC_Info -{ - #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte gain:7,trsw:1; - #else - u1Byte trsw:1,gain:7; - #endif -} __WLAN_ATTRIB_PACK__ PHY_RX_AGC_INFO_T, *pPHY_RX_AGC_INFO_T; - -__PACK typedef struct _Phy_Status_Rpt_8192cd { - PHY_RX_AGC_INFO_T path_agc[2]; - u1Byte ch_corr[2]; - u1Byte cck_sig_qual_ofdm_pwdb_all; - u1Byte cck_agc_rpt_ofdm_cfosho_a; - u1Byte cck_rpt_b_ofdm_cfosho_b; - u1Byte rsvd_1;/*ch_corr_msb;*/ - u1Byte noise_power_db_msb; - s1Byte path_cfotail[2]; - u1Byte pcts_mask[2]; - s1Byte stream_rxevm[2]; - u1Byte path_rxsnr[2]; - u1Byte noise_power_db_lsb; - u1Byte rsvd_2[3]; - u1Byte stream_csi[2]; - u1Byte stream_target_csi[2]; - s1Byte sig_evm; - u1Byte rsvd_3; + if (p_dm_odm->is_mp_chip)\ + AGC_DIFF_CONFIG_MP(ic, band);\ + else\ + AGC_DIFF_CONFIG_TC(ic, band);\ + } while (0) + + +/* ************************************************************ + * structure and define + * ************************************************************ */ + +__PACK struct _phy_rx_agc_info { +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain: 7, trsw: 1; +#else + u8 trsw: 1, gain: 7; +#endif +}; + +__PACK struct _phy_status_rpt_8192cd { + struct _phy_rx_agc_info path_agc[2]; + u8 ch_corr[2]; + u8 cck_sig_qual_ofdm_pwdb_all; + u8 cck_agc_rpt_ofdm_cfosho_a; + u8 cck_rpt_b_ofdm_cfosho_b; + u8 rsvd_1;/*ch_corr_msb;*/ + u8 noise_power_db_msb; + s8 path_cfotail[2]; + u8 pcts_mask[2]; + s8 stream_rxevm[2]; + u8 path_rxsnr[2]; + u8 noise_power_db_lsb; + u8 rsvd_2[3]; + u8 stream_csi[2]; + u8 stream_target_csi[2]; + s8 sig_evm; + u8 rsvd_3; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/ - u1Byte sgi_en: 1; - u1Byte rxsc: 2; - u1Byte idle_long: 1; - u1Byte r_ant_train_en: 1; - u1Byte ant_sel_b: 1; - u1Byte ant_sel: 1; + u8 antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/ + u8 sgi_en: 1; + u8 rxsc: 2; + u8 idle_long: 1; + u8 r_ant_train_en: 1; + u8 ant_sel_b: 1; + u8 ant_sel: 1; #else /*_BIG_ENDIAN_ */ - u1Byte ant_sel: 1; - u1Byte ant_sel_b: 1; - u1Byte r_ant_train_en: 1; - u1Byte idle_long: 1; - u1Byte rxsc: 2; - u1Byte sgi_en: 1; - u1Byte antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/ + u8 ant_sel: 1; + u8 ant_sel_b: 1; + u8 r_ant_train_en: 1; + u8 idle_long: 1; + u8 rxsc: 2; + u8 sgi_en: 1; + u8 antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/ #endif -} __WLAN_ATTRIB_PACK__ PHY_STATUS_RPT_8192CD_T, *PPHY_STATUS_RPT_8192CD_T; +}; -typedef struct _Phy_Status_Rpt_8812 { -/* DWORD 0*/ - u1Byte gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ - u1Byte chl_num_LSB; /*channel number[7:0]*/ +struct _phy_status_rpt_8812 { + /* DWORD 0*/ + u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ + u8 chl_num_LSB; /*channel number[7:0]*/ #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte chl_num_MSB: 2; /*channel number[9:8]*/ - u1Byte sub_chnl: 4; /*sub-channel location[3:0]*/ - u1Byte r_RFMOD: 2; /*RF mode[1:0]*/ + u8 chl_num_MSB: 2; /*channel number[9:8]*/ + u8 sub_chnl: 4; /*sub-channel location[3:0]*/ + u8 r_RFMOD: 2; /*RF mode[1:0]*/ #else /*_BIG_ENDIAN_ */ - u1Byte r_RFMOD: 2; - u1Byte sub_chnl: 4; - u1Byte chl_num_MSB: 2; + u8 r_RFMOD: 2; + u8 sub_chnl: 4; + u8 chl_num_MSB: 2; #endif -/* DWORD 1*/ - u1Byte pwdb_all; /*CCK signal quality / OFDM pwdb all*/ - s1Byte cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM Path-A and Path-B short CFO*/ + /* DWORD 1*/ + u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/ + s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/ #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) /*this should be checked again because the definition of 8812 and 8814 is different*/ -/* u1Byte r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/ -/* u1Byte cck_rx_path:4; cck rx path[3:0]*/ - u1Byte resvd_0: 6; - u1Byte bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/ + /* u8 r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/ + /* u8 cck_rx_path:4; cck rx path[3:0]*/ + u8 resvd_0: 6; + u8 bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/ #else /*_BIG_ENDIAN_*/ - u1Byte bt_RF_ch_MSB: 2; - u1Byte resvd_0: 6; + u8 bt_RF_ch_MSB: 2; + u8 resvd_0: 6; #endif -/* DWORD 2*/ + /* DWORD 2*/ #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/ - u1Byte ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/ - u1Byte bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ + u8 ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/ + u8 ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/ + u8 bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ #else /*_BIG_ENDIAN_ */ - u1Byte bt_RF_ch_LSB: 6; - u1Byte ant_div_sw_b: 1; - u1Byte ant_div_sw_a: 1; + u8 bt_RF_ch_LSB: 6; + u8 ant_div_sw_b: 1; + u8 ant_div_sw_a: 1; #endif - s1Byte cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ - u1Byte PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ - u1Byte PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ + s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ + u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ + u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ -/* DWORD 3*/ - s1Byte rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ - s1Byte rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ + /* DWORD 3*/ + s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ + s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ -/* DWORD 4*/ - u1Byte PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ + /* DWORD 4*/ + u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/ - u1Byte pcts_rpt_valid: 1; /*pcts_rpt_valid*/ - u1Byte resvd_1: 1; /*1'b0*/ + u8 PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/ + u8 pcts_rpt_valid: 1; /*pcts_rpt_valid*/ + u8 resvd_1: 1; /*1'b0*/ #else /*_BIG_ENDIAN_*/ - u1Byte resvd_1: 1; - u1Byte pcts_rpt_valid: 1; - u1Byte PCTS_MSK_RPT_3: 6; + u8 resvd_1: 1; + u8 pcts_rpt_valid: 1; + u8 PCTS_MSK_RPT_3: 6; #endif - s1Byte rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/ + s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/ -/* DWORD 5*/ - u1Byte csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/ - u1Byte gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/ + /* DWORD 5*/ + u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/ + u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/ -/* DWORD 6*/ - s1Byte sigevm; /*signal field EVM*/ + /* DWORD 6*/ + s8 sigevm; /*signal field EVM*/ #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/ - u1Byte antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/ - u1Byte dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/ - u1Byte GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/ + u8 antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/ + u8 antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/ + u8 dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/ + u8 GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/ #else /*_BIG_ENDIAN_*/ - u1Byte GNT_BT_keep: 1; - u1Byte dpdt_ctrl_keep: 1; - u1Byte antidx_antd: 3; - u1Byte antidx_antc: 3; + u8 GNT_BT_keep: 1; + u8 dpdt_ctrl_keep: 1; + u8 antidx_antd: 3; + u8 antidx_antc: 3; #endif #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte antidx_anta: 3; /*antidx_anta[2:0]*/ - u1Byte antidx_antb: 3; /*antidx_antb[2:0]*/ - u1Byte hw_antsw_occur: 2; /*1'b0*/ + u8 antidx_anta: 3; /*antidx_anta[2:0]*/ + u8 antidx_antb: 3; /*antidx_antb[2:0]*/ + u8 hw_antsw_occur: 2; /*1'b0*/ #else /*_BIG_ENDIAN_*/ - u1Byte hw_antsw_occur: 2; - u1Byte antidx_antb: 3; - u1Byte antidx_anta: 3; + u8 hw_antsw_occur: 2; + u8 antidx_antb: 3; + u8 antidx_anta: 3; #endif -} PHY_STATUS_RPT_8812_T, *PPHY_STATUS_RPT_8812_T; +}; + +void +phydm_reset_avg_rssi_for_ss( + struct PHY_DM_STRUCT *p_dm_odm +); -VOID +void phydm_reset_rssi_for_dm( - IN OUT PDM_ODM_T pDM_Odm, - IN u1Byte station_id + struct PHY_DM_STRUCT *p_dm_odm, + u8 station_id +); + +u8 +phydm_rate_to_num_ss( + struct PHY_DM_STRUCT *p_dm_odm, + u8 data_rate ); -VOID -odm_Init_RSSIForDM( - IN OUT PDM_ODM_T pDM_Odm +void +odm_init_rssi_for_dm( + struct PHY_DM_STRUCT *p_dm_odm ); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID +void phydm_normal_driver_rx_sniffer( - IN OUT PDM_ODM_T pDM_Odm, - IN pu1Byte pDesc, - IN PRT_RFD_STATUS pRtRfdStatus, - IN pu1Byte pDrvInfo, - IN u1Byte PHYStatus - ); + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_desc, + PRT_RFD_STATUS p_rt_rfd_status, + u8 *p_drv_info, + u8 phy_status +); #endif -VOID -ODM_PhyStatusQuery( - IN OUT PDM_ODM_T pDM_Odm, - OUT PODM_PHY_INFO_T pPhyInfo, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo - ); - -VOID -ODM_MacStatusQuery( - IN OUT PDM_ODM_T pDM_Odm, - IN pu1Byte pMacStatus, - IN u1Byte MacID, - IN BOOLEAN bPacketMatchBSSID, - IN BOOLEAN bPacketToSelf, - IN BOOLEAN bPacketBeacon - ); - -HAL_STATUS -ODM_ConfigRFWithTxPwrTrackHeaderFile( - IN PDM_ODM_T pDM_Odm - ); - -HAL_STATUS -ODM_ConfigRFWithHeaderFile( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_Config_Type ConfigType, - IN ODM_RF_RADIO_PATH_E eRFPath - ); - -HAL_STATUS -ODM_ConfigBBWithHeaderFile( - IN PDM_ODM_T pDM_Odm, - IN ODM_BB_Config_Type ConfigType - ); - -HAL_STATUS -ODM_ConfigMACWithHeaderFile( - IN PDM_ODM_T pDM_Odm - ); - -HAL_STATUS -ODM_ConfigFWWithHeaderFile( - IN PDM_ODM_T pDM_Odm, - IN ODM_FW_Config_Type ConfigType, - OUT u1Byte *pFirmware, - OUT u4Byte *pSize - ); - -u4Byte -ODM_GetHWImgVersion( - IN PDM_ODM_T pDM_Odm - ); - -s4Byte -odm_SignalScaleMapping( - IN OUT PDM_ODM_T pDM_Odm, - IN s4Byte CurrSig - ); +void +odm_phy_status_query( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo +); + +void +odm_mac_status_query( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_mac_status, + u8 mac_id, + boolean is_packet_match_bssid, + boolean is_packet_to_self, + boolean is_packet_beacon +); + +enum hal_status +odm_config_rf_with_tx_pwr_track_header_file( + struct PHY_DM_STRUCT *p_dm_odm +); + +enum hal_status +odm_config_rf_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_config_type config_type, + enum odm_rf_radio_path_e e_rf_path +); + +enum hal_status +odm_config_bb_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_bb_config_type config_type +); + +enum hal_status +odm_config_mac_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm +); + +enum hal_status +odm_config_fw_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_fw_config_type config_type, + u8 *p_firmware, + u32 *p_size +); + +u32 +odm_get_hw_img_version( + struct PHY_DM_STRUCT *p_dm_odm +); + +s32 +odm_signal_scale_mapping( + struct PHY_DM_STRUCT *p_dm_odm, + s32 curr_sig +); #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) /*For 8822B only!! need to move to FW finally */ /*==============================================*/ -VOID -phydm_RxPhyStatusNewType( - IN PDM_ODM_T pPhydm, - IN pu1Byte pPhyStatus, - IN PODM_PACKET_INFO_T pPktinfo, - OUT PODM_PHY_INFO_T pPhyInfo +void +phydm_rx_phy_status_new_type( + struct PHY_DM_STRUCT *p_phydm, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo, + struct _odm_phy_status_info_ *p_phy_info ); -typedef struct _Phy_Status_Rpt_Jaguar2_Type0 { +boolean +phydm_query_is_mu_api( + struct PHY_DM_STRUCT *p_phydm, + u8 ppdu_idx, + u8 *p_data_rate, + u8 *p_gid +); + +struct _phy_status_rpt_jaguar2_type0 { /* DW0 */ - u1Byte page_num; - u1Byte pwdb; + u8 page_num; + u8 pwdb; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte gain: 6; - u1Byte rsvd_0: 1; - u1Byte trsw: 1; + u8 gain: 6; + u8 rsvd_0: 1; + u8 trsw: 1; #else - u1Byte trsw: 1; - u1Byte rsvd_0: 1; - u1Byte gain: 6; + u8 trsw: 1; + u8 rsvd_0: 1; + u8 gain: 6; #endif - u1Byte rsvd_1; + u8 rsvd_1; /* DW1 */ - u1Byte rsvd_2; + u8 rsvd_2; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte rxsc: 4; - u1Byte agc_table: 4; + u8 rxsc: 4; + u8 agc_table: 4; #else - u1Byte agc_table: 4; - u1Byte rxsc: 4; + u8 agc_table: 4; + u8 rxsc: 4; #endif - u1Byte channel; - u1Byte band; + u8 channel; + u8 band; /* DW2 */ - u2Byte length; + u16 length; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte antidx_a: 3; - u1Byte antidx_b: 3; - u1Byte rsvd_3: 2; - u1Byte antidx_c: 3; - u1Byte antidx_d: 3; - u1Byte rsvd_4:2; + u8 antidx_a: 3; + u8 antidx_b: 3; + u8 rsvd_3: 2; + u8 antidx_c: 3; + u8 antidx_d: 3; + u8 rsvd_4:2; #else - u1Byte rsvd_3: 2; - u1Byte antidx_b: 3; - u1Byte antidx_a: 3; - u1Byte rsvd_4:2; - u1Byte antidx_d: 3; - u1Byte antidx_c: 3; + u8 rsvd_3: 2; + u8 antidx_b: 3; + u8 antidx_a: 3; + u8 rsvd_4:2; + u8 antidx_d: 3; + u8 antidx_c: 3; #endif /* DW3 */ - u1Byte signal_quality; + u8 signal_quality; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte vga:5; - u1Byte lna_l:3; - u1Byte bb_power:6; - u1Byte rsvd_9:1; - u1Byte lna_h:1; + u8 vga:5; + u8 lna_l:3; + u8 bb_power:6; + u8 rsvd_9:1; + u8 lna_h:1; #else - u1Byte lna_l:3; - u1Byte vga:5; - u1Byte lna_h:1; - u1Byte rsvd_9:1; - u1Byte bb_power:6; + u8 lna_l:3; + u8 vga:5; + u8 lna_h:1; + u8 rsvd_9:1; + u8 bb_power:6; #endif - u1Byte rsvd_5; + u8 rsvd_5; /* DW4 */ - u4Byte rsvd_6; + u32 rsvd_6; /* DW5 */ - u4Byte rsvd_7; + u32 rsvd_7; /* DW6 */ - u4Byte rsvd_8; -} PHY_STATUS_RPT_JAGUAR2_TYPE0, *PPHY_STATUS_RPT_JAGUAR2_TYPE0; + u32 rsvd_8; +}; -typedef struct _Phy_Status_Rpt_Jaguar2_Type1 { +struct _phy_status_rpt_jaguar2_type1 { /* DW0 and DW1 */ - u1Byte page_num; - u1Byte pwdb[4]; + u8 page_num; + u8 pwdb[4]; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte l_rxsc: 4; - u1Byte ht_rxsc: 4; + u8 l_rxsc: 4; + u8 ht_rxsc: 4; #else - u1Byte ht_rxsc: 4; - u1Byte l_rxsc: 4; + u8 ht_rxsc: 4; + u8 l_rxsc: 4; #endif - u1Byte channel; + u8 channel; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte band: 2; - u1Byte rsvd_0: 1; - u1Byte hw_antsw_occu: 1; - u1Byte gnt_bt: 1; - u1Byte ldpc: 1; - u1Byte stbc: 1; - u1Byte beamformed: 1; + u8 band: 2; + u8 rsvd_0: 1; + u8 hw_antsw_occu: 1; + u8 gnt_bt: 1; + u8 ldpc: 1; + u8 stbc: 1; + u8 beamformed: 1; #else - u1Byte beamformed: 1; - u1Byte stbc: 1; - u1Byte ldpc: 1; - u1Byte gnt_bt: 1; - u1Byte hw_antsw_occu: 1; - u1Byte rsvd_0: 1; - u1Byte band: 2; + u8 beamformed: 1; + u8 stbc: 1; + u8 ldpc: 1; + u8 gnt_bt: 1; + u8 hw_antsw_occu: 1; + u8 rsvd_0: 1; + u8 band: 2; #endif /* DW2 */ - u2Byte lsig_length; + u16 lsig_length; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte antidx_a: 3; - u1Byte antidx_b: 3; - u1Byte rsvd_1: 2; - u1Byte antidx_c: 3; - u1Byte antidx_d: 3; - u1Byte rsvd_2: 2; + u8 antidx_a: 3; + u8 antidx_b: 3; + u8 rsvd_1: 2; + u8 antidx_c: 3; + u8 antidx_d: 3; + u8 rsvd_2: 2; #else - u1Byte rsvd_1: 2; - u1Byte antidx_b: 3; - u1Byte antidx_a: 3; - u1Byte rsvd_2: 2; - u1Byte antidx_d: 3; - u1Byte antidx_c: 3; + u8 rsvd_1: 2; + u8 antidx_b: 3; + u8 antidx_a: 3; + u8 rsvd_2: 2; + u8 antidx_d: 3; + u8 antidx_c: 3; #endif /* DW3 */ - u1Byte paid; + u8 paid; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte paid_msb: 1; - u1Byte gid: 6; - u1Byte rsvd_3: 1; + u8 paid_msb: 1; + u8 gid: 6; + u8 rsvd_3: 1; #else - u1Byte rsvd_3: 1; - u1Byte gid: 6; - u1Byte paid_msb: 1; + u8 rsvd_3: 1; + u8 gid: 6; + u8 paid_msb: 1; #endif - u1Byte intf_pos; + u8 intf_pos; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte intf_pos_msb: 1; - u1Byte rsvd_4: 2; - u1Byte nb_intf_flag: 1; - u1Byte rf_mode: 2; - u1Byte rsvd_5: 2; + u8 intf_pos_msb: 1; + u8 rsvd_4: 2; + u8 nb_intf_flag: 1; + u8 rf_mode: 2; + u8 rsvd_5: 2; #else - u1Byte rsvd_5: 2; - u1Byte rf_mode: 2; - u1Byte nb_intf_flag: 1; - u1Byte rsvd_4: 2; - u1Byte intf_pos_msb: 1; + u8 rsvd_5: 2; + u8 rf_mode: 2; + u8 nb_intf_flag: 1; + u8 rsvd_4: 2; + u8 intf_pos_msb: 1; #endif /* DW4 */ - s1Byte rxevm[4]; /* s(8,1) */ + s8 rxevm[4]; /* s(8,1) */ /* DW5 */ - s1Byte cfo_tail[4]; /* s(8,7) */ + s8 cfo_tail[4]; /* s(8,7) */ /* DW6 */ - s1Byte rxsnr[4]; /* s(8,1) */ -} PHY_STATUS_RPT_JAGUAR2_TYPE1, *PPHY_STATUS_RPT_JAGUAR2_TYPE1; + s8 rxsnr[4]; /* s(8,1) */ +}; -typedef struct _Phy_Status_Rpt_Jaguar2_Type2 { +struct _phy_status_rpt_jaguar2_type2 { /* DW0 ane DW1 */ - u1Byte page_num; - u1Byte pwdb[4]; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte l_rxsc: 4; - u1Byte ht_rxsc: 4; + u8 page_num; + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc: 4; + u8 ht_rxsc: 4; #else - u1Byte ht_rxsc: 4; - u1Byte l_rxsc: 4; + u8 ht_rxsc: 4; + u8 l_rxsc: 4; #endif - u1Byte channel; + u8 channel; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte band: 2; - u1Byte rsvd_0: 1; - u1Byte hw_antsw_occu: 1; - u1Byte gnt_bt: 1; - u1Byte ldpc: 1; - u1Byte stbc: 1; - u1Byte beamformed: 1; + u8 band: 2; + u8 rsvd_0: 1; + u8 hw_antsw_occu: 1; + u8 gnt_bt: 1; + u8 ldpc: 1; + u8 stbc: 1; + u8 beamformed: 1; #else - u1Byte beamformed: 1; - u1Byte stbc: 1; - u1Byte ldpc: 1; - u1Byte gnt_bt: 1; - u1Byte hw_antsw_occu: 1; - u1Byte rsvd_0: 1; - u1Byte band: 2; + u8 beamformed: 1; + u8 stbc: 1; + u8 ldpc: 1; + u8 gnt_bt: 1; + u8 hw_antsw_occu: 1; + u8 rsvd_0: 1; + u8 band: 2; #endif /* DW2 */ #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte shift_l_map: 6; - u1Byte rsvd_1: 2; + u8 shift_l_map: 6; + u8 rsvd_1: 2; #else - u1Byte rsvd_1: 2; - u1Byte shift_l_map: 6; + u8 rsvd_1: 2; + u8 shift_l_map: 6; #endif - u1Byte cnt_pw2cca; + u8 cnt_pw2cca; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte agc_table_a: 4; - u1Byte agc_table_b: 4; - u1Byte agc_table_c: 4; - u1Byte agc_table_d: 4; + u8 agc_table_a: 4; + u8 agc_table_b: 4; + u8 agc_table_c: 4; + u8 agc_table_d: 4; #else - u1Byte agc_table_b: 4; - u1Byte agc_table_a: 4; - u1Byte agc_table_d: 4; - u1Byte agc_table_c: 4; + u8 agc_table_b: 4; + u8 agc_table_a: 4; + u8 agc_table_d: 4; + u8 agc_table_c: 4; #endif /* DW3 ~ DW6*/ - u1Byte cnt_cca2agc_rdy; + u8 cnt_cca2agc_rdy; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte gain_a: 6; - u1Byte rsvd_2: 1; - u1Byte trsw_a: 1; - u1Byte gain_b: 6; - u1Byte rsvd_3: 1; - u1Byte trsw_b: 1; - u1Byte gain_c: 6; - u1Byte rsvd_4: 1; - u1Byte trsw_c: 1; - u1Byte gain_d: 6; - u1Byte rsvd_5: 1; - u1Byte trsw_d: 1; - u1Byte aagc_step_a: 2; - u1Byte aagc_step_b: 2; - u1Byte aagc_step_c: 2; - u1Byte aagc_step_d: 2; + u8 gain_a: 6; + u8 rsvd_2: 1; + u8 trsw_a: 1; + u8 gain_b: 6; + u8 rsvd_3: 1; + u8 trsw_b: 1; + u8 gain_c: 6; + u8 rsvd_4: 1; + u8 trsw_c: 1; + u8 gain_d: 6; + u8 rsvd_5: 1; + u8 trsw_d: 1; + u8 aagc_step_a: 2; + u8 aagc_step_b: 2; + u8 aagc_step_c: 2; + u8 aagc_step_d: 2; #else - u1Byte trsw_a: 1; - u1Byte rsvd_2: 1; - u1Byte gain_a: 6; - u1Byte trsw_b: 1; - u1Byte rsvd_3: 1; - u1Byte gain_b: 6; - u1Byte trsw_c: 1; - u1Byte rsvd_4: 1; - u1Byte gain_c: 6; - u1Byte trsw_d: 1; - u1Byte rsvd_5: 1; - u1Byte gain_d: 6; - u1Byte aagc_step_d: 2; - u1Byte aagc_step_c: 2; - u1Byte aagc_step_b: 2; - u1Byte aagc_step_a: 2; + u8 trsw_a: 1; + u8 rsvd_2: 1; + u8 gain_a: 6; + u8 trsw_b: 1; + u8 rsvd_3: 1; + u8 gain_b: 6; + u8 trsw_c: 1; + u8 rsvd_4: 1; + u8 gain_c: 6; + u8 trsw_d: 1; + u8 rsvd_5: 1; + u8 gain_d: 6; + u8 aagc_step_d: 2; + u8 aagc_step_c: 2; + u8 aagc_step_b: 2; + u8 aagc_step_a: 2; #endif - u1Byte ht_aagc_gain[4]; - u1Byte dagc_gain[4]; + u8 ht_aagc_gain[4]; + u8 dagc_gain[4]; #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u1Byte counter: 6; - u1Byte rsvd_6: 2; - u1Byte syn_count: 5; - u1Byte rsvd_7:3; + u8 counter: 6; + u8 rsvd_6: 2; + u8 syn_count: 5; + u8 rsvd_7:3; #else - u1Byte rsvd_6: 2; - u1Byte counter: 6; - u1Byte rsvd_7:3; - u1Byte syn_count: 5; + u8 rsvd_6: 2; + u8 counter: 6; + u8 rsvd_7:3; + u8 syn_count: 5; #endif -} PHY_STATUS_RPT_JAGUAR2_TYPE2, *PPHY_STATUS_RPT_JAGUAR2_TYPE2; +}; /*==============================================*/ #endif /*#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)*/ -u4Byte +u32 query_phydm_trx_capability( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte +u32 query_phydm_stbc_capability( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte +u32 query_phydm_ldpc_capability( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte +u32 query_phydm_txbf_parameters( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte +u32 query_phydm_txbf_capability( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ); #endif /*#ifndef __HALHWOUTSRC_H__*/ - diff --git a/hal/phydm/phydm_interface.c b/hal/phydm/phydm_interface.c index ffe9b24..1392300 100644 --- a/hal/phydm/phydm_interface.c +++ b/hal/phydm/phydm_interface.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,917 +11,1053 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" -// -// ODM IO Relative API. -// +/* + * ODM IO Relative API. + * */ -u1Byte -ODM_Read1Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr - ) +u8 +odm_read_1byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - return RTL_R8(RegAddr); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - return rtw_read8(Adapter,RegAddr); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - return PlatformEFIORead1Byte(Adapter, RegAddr); -#endif + struct rtl8192cd_priv *priv = p_dm_odm->priv; + return RTL_R8(reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + + return rtl_read_byte(rtlpriv, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct _ADAPTER *adapter = p_dm_odm->adapter; + return rtw_read8(adapter, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + return PlatformEFIORead1Byte(adapter, reg_addr); +#endif } -u2Byte -ODM_Read2Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr - ) +u16 +odm_read_2byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - return RTL_R16(RegAddr); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - return rtw_read16(Adapter,RegAddr); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - return PlatformEFIORead2Byte(Adapter, RegAddr); -#endif + struct rtl8192cd_priv *priv = p_dm_odm->priv; + return RTL_R16(reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + + return rtl_read_word(rtlpriv, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct _ADAPTER *adapter = p_dm_odm->adapter; + return rtw_read16(adapter, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + return PlatformEFIORead2Byte(adapter, reg_addr); +#endif } -u4Byte -ODM_Read4Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr - ) +u32 +odm_read_4byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - return RTL_R32(RegAddr); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - return rtw_read32(Adapter,RegAddr); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - return PlatformEFIORead4Byte(Adapter, RegAddr); -#endif + struct rtl8192cd_priv *priv = p_dm_odm->priv; + return RTL_R32(reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + + return rtl_read_dword(rtlpriv, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct _ADAPTER *adapter = p_dm_odm->adapter; + return rtw_read32(adapter, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + return PlatformEFIORead4Byte(adapter, reg_addr); +#endif } -VOID -ODM_Write1Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u1Byte Data - ) +void +odm_write_1byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u8 data +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - RTL_W8(RegAddr, Data); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - rtw_write8(Adapter,RegAddr, Data); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformEFIOWrite1Byte(Adapter, RegAddr, Data); + struct rtl8192cd_priv *priv = p_dm_odm->priv; + RTL_W8(reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + + rtl_write_byte(rtlpriv, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct _ADAPTER *adapter = p_dm_odm->adapter; + rtw_write8(adapter, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PlatformEFIOWrite1Byte(adapter, reg_addr, data); #endif - + } -VOID -ODM_Write2Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u2Byte Data - ) +void +odm_write_2byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u16 data +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - RTL_W16(RegAddr, Data); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - rtw_write16(Adapter,RegAddr, Data); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformEFIOWrite2Byte(Adapter, RegAddr, Data); -#endif + struct rtl8192cd_priv *priv = p_dm_odm->priv; + RTL_W16(reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + + rtl_write_word(rtlpriv, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct _ADAPTER *adapter = p_dm_odm->adapter; + rtw_write16(adapter, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PlatformEFIOWrite2Byte(adapter, reg_addr, data); +#endif } -VOID -ODM_Write4Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte Data - ) +void +odm_write_4byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 data +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - prtl8192cd_priv priv = pDM_Odm->priv; - RTL_W32(RegAddr, Data); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - rtw_write32(Adapter,RegAddr, Data); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformEFIOWrite4Byte(Adapter, RegAddr, Data); -#endif + struct rtl8192cd_priv *priv = p_dm_odm->priv; + RTL_W32(reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + + rtl_write_dword(rtlpriv, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct _ADAPTER *adapter = p_dm_odm->adapter; + rtw_write32(adapter, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PlatformEFIOWrite4Byte(adapter, reg_addr, data); +#endif } -VOID -ODM_SetMACReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ) +void +odm_set_mac_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask, + u32 data +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data); -#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - PADAPTER Adapter = pDM_Odm->Adapter; - PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); -#endif + phy_set_bb_reg(p_dm_odm->priv, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PHY_SetBBReg(adapter, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + + rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data); +#else + phy_set_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask, data); +#endif } -u4Byte -ODM_GetMACReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask - ) +u32 +odm_get_mac_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask); -#elif(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - return PHY_QueryMacReg(pDM_Odm->Adapter, RegAddr, BitMask); -#endif + return phy_query_bb_reg(p_dm_odm->priv, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + return PHY_QueryMacReg(p_dm_odm->adapter, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + + return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask); +#else + return phy_query_mac_reg(p_dm_odm->adapter, reg_addr, bit_mask); +#endif } -VOID -ODM_SetBBReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ) +void +odm_set_bb_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask, + u32 data +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data); -#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - PADAPTER Adapter = pDM_Odm->Adapter; - PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); -#endif + phy_set_bb_reg(p_dm_odm->priv, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PHY_SetBBReg(adapter, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + + rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data); +#else + phy_set_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask, data); +#endif } -u4Byte -ODM_GetBBReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask - ) +u32 +odm_get_bb_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask); -#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - PADAPTER Adapter = pDM_Odm->Adapter; - return PHY_QueryBBReg(Adapter, RegAddr, BitMask); -#endif + return phy_query_bb_reg(p_dm_odm->priv, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + return PHY_QueryBBReg(adapter, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + + return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask); +#else + return phy_query_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask); +#endif } -VOID -ODM_SetRFReg( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ) +void +odm_set_rf_reg( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e e_rf_path, + u32 reg_addr, + u32 bit_mask, + u32 data +) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data); + phy_set_rf_reg(p_dm_odm->priv, e_rf_path, reg_addr, bit_mask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data); + struct _ADAPTER *adapter = p_dm_odm->adapter; + PHY_SetRFReg(adapter, e_rf_path, reg_addr, bit_mask, data); ODM_delay_us(2); - + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + + rtl_set_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PHY_SetRFReg(pDM_Odm->Adapter, eRFPath, RegAddr, BitMask, Data); -#endif + phy_set_rf_reg(p_dm_odm->adapter, e_rf_path, reg_addr, bit_mask, data); +#endif } -u4Byte -ODM_GetRFReg( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ) +u32 +odm_get_rf_reg( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e e_rf_path, + u32 reg_addr, + u32 bit_mask +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return PHY_QueryRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, 1); -#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) - PADAPTER Adapter = pDM_Odm->Adapter; - return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask); -#endif + return phy_query_rf_reg(p_dm_odm->priv, e_rf_path, reg_addr, bit_mask, 1); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + return PHY_QueryRFReg(adapter, e_rf_path, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + + return rtl_get_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask); +#else + return phy_query_rf_reg(p_dm_odm->adapter, e_rf_path, reg_addr, bit_mask); +#endif } +enum hal_status +phydm_set_reg_by_fw( + struct PHY_DM_STRUCT *p_dm_odm, + enum phydm_halmac_param config_type, + u32 offset, + u32 data, + u32 mask, + enum odm_rf_radio_path_e e_rf_path, + u32 delay_time +) +{ + enum hal_status stat = HAL_STATUS_SUCCESS; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + stat = HAL_MAC_Config_PHY_WriteNByte(p_dm_odm, + config_type, + offset, + data, + mask, + e_rf_path, + delay_time); +#elif (0)/*(DM_ODM_SUPPORT_TYPE & ODM_CE)*/ + return rtw_phydm_cfg_phy_para(p_dm_odm, + config_type, + offset, + data, + mask, + e_rf_path, + delay_time); +#endif + return stat; +} -// -// ODM Memory relative API. -// -VOID -ODM_AllocateMemory( - IN PDM_ODM_T pDM_Odm, - OUT PVOID *pPtr, - IN u4Byte length - ) +/* + * ODM Memory relative API. + * */ +void +odm_allocate_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void **p_ptr, + u32 length +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - *pPtr = kmalloc(length, GFP_ATOMIC); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) - *pPtr = rtw_zvmalloc(length); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformAllocateMemory(Adapter, pPtr, length); -#endif -} - -// length could be ignored, used to detect memory leakage. -VOID -ODM_FreeMemory( - IN PDM_ODM_T pDM_Odm, - OUT PVOID pPtr, - IN u4Byte length - ) + *p_ptr = kmalloc(length, GFP_ATOMIC); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + *p_ptr = kmalloc(length, GFP_ATOMIC); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + *p_ptr = rtw_zvmalloc(length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PlatformAllocateMemory(adapter, p_ptr, length); +#endif +} + +/* length could be ignored, used to detect memory leakage. */ +void +odm_free_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void *p_ptr, + u32 length +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - kfree(pPtr); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) - rtw_vmfree(pPtr, length); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - //PADAPTER Adapter = pDM_Odm->Adapter; - PlatformFreeMemory(pPtr, length); -#endif -} - -VOID -ODM_MoveMemory( - IN PDM_ODM_T pDM_Odm, - OUT PVOID pDest, - IN PVOID pSrc, - IN u4Byte Length - ) + kfree(p_ptr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + kfree(p_ptr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_vmfree(p_ptr, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + /* struct _ADAPTER* adapter = p_dm_odm->adapter; */ + PlatformFreeMemory(p_ptr, length); +#endif +} + +void +odm_move_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void *p_dest, + void *p_src, + u32 length +) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - memcpy(pDest, pSrc, Length); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) - _rtw_memcpy(pDest, pSrc, Length); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformMoveMemory(pDest, pSrc, Length); -#endif + memcpy(p_dest, p_src, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + memcpy(p_dest, p_src, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + _rtw_memcpy(p_dest, p_src, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformMoveMemory(p_dest, p_src, length); +#endif } -void ODM_Memory_Set( - IN PDM_ODM_T pDM_Odm, - IN PVOID pbuf, - IN s1Byte value, - IN u4Byte length +void odm_memory_set( + struct PHY_DM_STRUCT *p_dm_odm, + void *pbuf, + s8 value, + u32 length ) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) memset(pbuf, value, length); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) - _rtw_memset(pbuf,value, length); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformFillMemory(pbuf,length,value); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + memset(pbuf, value, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + _rtw_memset(pbuf, value, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformFillMemory(pbuf, length, value); #endif } -s4Byte ODM_CompareMemory( - IN PDM_ODM_T pDM_Odm, - IN PVOID pBuf1, - IN PVOID pBuf2, - IN u4Byte length - ) +s32 odm_compare_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void *p_buf1, + void *p_buf2, + u32 length +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return memcmp(pBuf1,pBuf2,length); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) - return _rtw_memcmp(pBuf1,pBuf2,length); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - return PlatformCompareMemory(pBuf1,pBuf2,length); -#endif + return memcmp(p_buf1, p_buf2, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + return memcmp(p_buf1, p_buf2, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return _rtw_memcmp(p_buf1, p_buf2, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + return PlatformCompareMemory(p_buf1, p_buf2, length); +#endif } -// -// ODM MISC relative API. -// -VOID -ODM_AcquireSpinLock( - IN PDM_ODM_T pDM_Odm, - IN RT_SPINLOCK_TYPE type - ) +/* + * ODM MISC relative API. + * */ +void +odm_acquire_spin_lock( + struct PHY_DM_STRUCT *p_dm_odm, + enum rt_spinlock_type type +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - rtw_odm_acquirespinlock(Adapter, type); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformAcquireSpinLock(Adapter, type); -#endif -} -VOID -ODM_ReleaseSpinLock( - IN PDM_ODM_T pDM_Odm, - IN RT_SPINLOCK_TYPE type - ) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct _ADAPTER *adapter = p_dm_odm->adapter; + rtw_odm_acquirespinlock(adapter, type); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PlatformAcquireSpinLock(adapter, type); +#endif +} +void +odm_release_spin_lock( + struct PHY_DM_STRUCT *p_dm_odm, + enum rt_spinlock_type type +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) - PADAPTER Adapter = pDM_Odm->Adapter; - rtw_odm_releasespinlock(Adapter, type); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformReleaseSpinLock(Adapter, type); -#endif -} - -// -// Work item relative API. FOr MP driver only~! -// -VOID -ODM_InitializeWorkItem( - IN PDM_ODM_T pDM_Odm, - IN PRT_WORK_ITEM pRtWorkItem, - IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, - IN PVOID pContext, - IN const char* szID - ) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct _ADAPTER *adapter = p_dm_odm->adapter; + rtw_odm_releasespinlock(adapter, type); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PlatformReleaseSpinLock(adapter, type); +#endif +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +/* + * Work item relative API. FOr MP driver only~! + * */ +void +odm_initialize_work_item( + struct PHY_DM_STRUCT *p_dm_odm, + PRT_WORK_ITEM p_rt_work_item, + RT_WORKITEM_CALL_BACK rt_work_item_callback, + void *p_context, + const char *sz_id +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformInitializeWorkItem(Adapter, pRtWorkItem, RtWorkItemCallback, pContext, szID); -#endif + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PlatformInitializeWorkItem(adapter, p_rt_work_item, rt_work_item_callback, p_context, sz_id); +#endif } -VOID -ODM_StartWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ) +void +odm_start_work_item( + PRT_WORK_ITEM p_rt_work_item +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformStartWorkItem(pRtWorkItem); -#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStartWorkItem(p_rt_work_item); +#endif } -VOID -ODM_StopWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ) +void +odm_stop_work_item( + PRT_WORK_ITEM p_rt_work_item +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformStopWorkItem(pRtWorkItem); -#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStopWorkItem(p_rt_work_item); +#endif } -VOID -ODM_FreeWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ) +void +odm_free_work_item( + PRT_WORK_ITEM p_rt_work_item +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformFreeWorkItem(pRtWorkItem); -#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformFreeWorkItem(p_rt_work_item); +#endif } -VOID -ODM_ScheduleWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ) +void +odm_schedule_work_item( + PRT_WORK_ITEM p_rt_work_item +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformScheduleWorkItem(pRtWorkItem); -#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformScheduleWorkItem(p_rt_work_item); +#endif } -VOID -ODM_IsWorkItemScheduled( - IN PRT_WORK_ITEM pRtWorkItem - ) +boolean +odm_is_work_item_scheduled( + PRT_WORK_ITEM p_rt_work_item +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformIsWorkItemScheduled(pRtWorkItem); -#endif -} +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + return PlatformIsWorkItemScheduled(p_rt_work_item); +#endif +} +#endif -// -// ODM Timer relative API. -// -VOID -ODM_StallExecution( - IN u4Byte usDelay - ) +/* + * ODM Timer relative API. + * */ +void +odm_stall_execution( + u32 us_delay +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_udelay_os(usDelay); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformStallExecution(usDelay); -#endif + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + udelay(us_delay); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_udelay_os(us_delay); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStallExecution(us_delay); +#endif } -VOID -ODM_delay_ms(IN u4Byte ms) +void +ODM_delay_ms(u32 ms) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) delay_ms(ms); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + mdelay(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) rtw_mdelay_os(ms); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) delay_ms(ms); -#endif +#endif } -VOID -ODM_delay_us(IN u4Byte us) +void +ODM_delay_us(u32 us) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) delay_us(us); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + udelay(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) rtw_udelay_os(us); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) PlatformStallExecution(us); -#endif +#endif } -VOID -ODM_sleep_ms(IN u4Byte ms) +void +ODM_sleep_ms(u32 ms) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + msleep(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) rtw_msleep_os(ms); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#endif } -VOID -ODM_sleep_us(IN u4Byte us) +void +ODM_sleep_us(u32 us) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + usleep_range(us, us + 1); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) rtw_usleep_os(us); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#endif } -VOID -ODM_SetTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer, - IN u4Byte msDelay - ) +void +odm_set_timer( + struct PHY_DM_STRUCT *p_dm_odm, + #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + struct legacy_timer_emu *p_timer, + #else + struct timer_list *p_timer, + #endif + u32 ms_delay +) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - mod_timer(pTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(msDelay)); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - _set_timer(pTimer,msDelay ); //ms -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformSetTimer(Adapter, pTimer, msDelay); -#endif - -} - -VOID -ODM_InitializeTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer, - IN RT_TIMER_CALL_BACK CallBackFunc, - IN PVOID pContext, - IN const char* szID - ) + mod_timer(p_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay)); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + mod_timer(p_timer, jiffies + msecs_to_jiffies(ms_delay)); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + _set_timer(p_timer, ms_delay); /* ms */ +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PlatformSetTimer(adapter, p_timer, ms_delay); +#endif + +} + +void +odm_initialize_timer( + struct PHY_DM_STRUCT *p_dm_odm, + #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + struct legacy_timer_emu *p_timer, + #else + struct timer_list *p_timer, + #endif + void *call_back_func, + void *p_context, + const char *sz_id +) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - init_timer(pTimer); - pTimer->function = CallBackFunc; - pTimer->data = (unsigned long)pDM_Odm; - /*mod_timer(pTimer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */ -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - _init_timer(pTimer,Adapter->pnetdev,CallBackFunc,pDM_Odm); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformInitializeTimer(Adapter, pTimer, CallBackFunc,pContext,szID); -#endif -} - - -VOID -ODM_CancelTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer - ) + init_timer(p_timer); + p_timer->function = call_back_func; + p_timer->data = (unsigned long)p_dm_odm; + /*mod_timer(p_timer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */ +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + init_timer(p_timer); + p_timer->function = call_back_func; + p_timer->data = (unsigned long)p_dm_odm; + /*mod_timer(p_timer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */ +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct _ADAPTER *adapter = p_dm_odm->adapter; + _init_timer(p_timer, adapter->pnetdev, call_back_func, p_dm_odm); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PlatformInitializeTimer(adapter, p_timer, call_back_func, p_context, sz_id); +#endif +} + + +void +odm_cancel_timer( + struct PHY_DM_STRUCT *p_dm_odm, + #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + struct legacy_timer_emu *p_timer + #else + struct timer_list *p_timer + #endif +) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - del_timer(pTimer); -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - _cancel_timer_ex(pTimer); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PlatformCancelTimer(Adapter, pTimer); + del_timer(p_timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + del_timer(p_timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + _cancel_timer_ex(p_timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PlatformCancelTimer(adapter, p_timer); #endif } -VOID -ODM_ReleaseTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer - ) +void +odm_release_timer( + struct PHY_DM_STRUCT *p_dm_odm, + #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + struct legacy_timer_emu *p_timer + #else + struct timer_list *p_timer + #endif +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; + struct _ADAPTER *adapter = p_dm_odm->adapter; - // <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm. - // Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail. - if (pTimer == 0) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>ODM_ReleaseTimer(), The timer is NULL! Please check it!\n")); - return; - } - - PlatformReleaseTimer(Adapter, pTimer); + /* <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm. + * Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail. */ + if (p_timer == 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>odm_release_timer(), The timer is NULL! Please check it!\n")); + return; + } + + PlatformReleaseTimer(adapter, p_timer); #endif } -u1Byte +u8 phydm_trans_h2c_id( - IN PDM_ODM_T pDM_Odm, - IN u1Byte phydm_h2c_id + struct PHY_DM_STRUCT *p_dm_odm, + u8 phydm_h2c_id ) { - u1Byte platform_h2c_id=0xff; + u8 platform_h2c_id = phydm_h2c_id; - - switch(phydm_h2c_id) - { - //1 [0] - case ODM_H2C_RSSI_REPORT: - - #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - if(pDM_Odm->SupportICType == ODM_RTL8188E) - platform_h2c_id = H2C_88E_RSSI_REPORT; - else if(pDM_Odm->SupportICType == ODM_RTL8814A) - platform_h2c_id =H2C_8814A_RSSI_REPORT; - else - platform_h2c_id = H2C_RSSI_REPORT; - - #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - platform_h2c_id = H2C_RSSI_SETTING; - - #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + switch (phydm_h2c_id) { + /* 1 [0] */ + case ODM_H2C_RSSI_REPORT: + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (p_dm_odm->support_ic_type == ODM_RTL8188E) + platform_h2c_id = H2C_88E_RSSI_REPORT; + else if (p_dm_odm->support_ic_type == ODM_RTL8814A) + platform_h2c_id = H2C_8814A_RSSI_REPORT; + else + platform_h2c_id = H2C_RSSI_REPORT; + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + platform_h2c_id = H2C_RSSI_SETTING; + +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) - platform_h2c_id = H2C_88XX_RSSI_REPORT; - else - #endif - #if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - platform_h2c_id = H2C_8812_RSSI_REPORT; - else - #endif - {} - #endif - - break; - - //1 [3] - case ODM_H2C_WIFI_CALIBRATION: - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - platform_h2c_id =H2C_WIFI_CALIBRATION; - - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - #if (RTL8723B_SUPPORT == 1) - platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION; - #endif - - #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) - #endif - break; - - - //1 [4] - case ODM_H2C_IQ_CALIBRATION: - #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - platform_h2c_id =H2C_IQ_CALIBRATION; - - #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - #if((RTL8812A_SUPPORT==1) ||(RTL8821A_SUPPORT==1)) - platform_h2c_id = H2C_8812_IQ_CALIBRATION; - #endif - #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) - #endif - - break; - //1 [5] - case ODM_H2C_RA_PARA_ADJUST: - - #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) - platform_h2c_id =H2C_8814A_RA_PARA_ADJUST; - else - platform_h2c_id = H2C_RA_PARA_ADJUST; - #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - #if((RTL8812A_SUPPORT==1) ||(RTL8821A_SUPPORT==1)) - platform_h2c_id = H2C_8812_RA_PARA_ADJUST; - #elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) - platform_h2c_id = H2C_RA_PARA_ADJUST; - #elif(RTL8192E_SUPPORT==1) - platform_h2c_id =H2C_8192E_RA_PARA_ADJUST; - #elif(RTL8723B_SUPPORT==1) - platform_h2c_id =H2C_8723B_RA_PARA_ADJUST; - #endif - - #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) -#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) - platform_h2c_id = H2C_88XX_RA_PARA_ADJUST; + if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) + platform_h2c_id = H2C_88XX_RSSI_REPORT; + else +#endif +#if (RTL8812A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8812) + platform_h2c_id = H2C_8812_RSSI_REPORT; else - #endif - #if(RTL8812A_SUPPORT==1) - if(pDM_Odm->SupportICType == ODM_RTL8812) - platform_h2c_id = H2C_8812_RA_PARA_ADJUST; +#endif + {} +#endif + + break; + + /* 1 [3] */ + case ODM_H2C_WIFI_CALIBRATION: +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + platform_h2c_id = H2C_WIFI_CALIBRATION; + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if (RTL8723B_SUPPORT == 1) + platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION; +#endif + +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +#endif + break; + + + /* 1 [4] */ + case ODM_H2C_IQ_CALIBRATION: +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + platform_h2c_id = H2C_IQ_CALIBRATION; + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + platform_h2c_id = H2C_8812_IQ_CALIBRATION; +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +#endif + + break; + /* 1 [5] */ + case ODM_H2C_RA_PARA_ADJUST: + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) + platform_h2c_id = H2C_8814A_RA_PARA_ADJUST; + else + platform_h2c_id = H2C_RA_PARA_ADJUST; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + platform_h2c_id = H2C_8812_RA_PARA_ADJUST; +#elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) + platform_h2c_id = H2C_RA_PARA_ADJUST; +#elif (RTL8192E_SUPPORT == 1) + platform_h2c_id = H2C_8192E_RA_PARA_ADJUST; +#elif (RTL8723B_SUPPORT == 1) + platform_h2c_id = H2C_8723B_RA_PARA_ADJUST; +#endif + +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) + platform_h2c_id = H2C_88XX_RA_PARA_ADJUST; + else +#endif +#if (RTL8812A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8812) + platform_h2c_id = H2C_8812_RA_PARA_ADJUST; else - #endif - {} - #endif - - break; - - - //1 [6] - case PHYDM_H2C_DYNAMIC_TX_PATH: - - #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - if(pDM_Odm->SupportICType == ODM_RTL8814A) - { - platform_h2c_id =H2C_8814A_DYNAMIC_TX_PATH; - } - #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - #if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A) - platform_h2c_id = H2C_DYNAMIC_TX_PATH; - #endif - #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) - #if(RTL8814A_SUPPORT==1) - if( pDM_Odm->SupportICType == ODM_RTL8814A) - { - platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH; - } - #endif - - #endif - - break; - - /* [7]*/ - case PHYDM_H2C_FW_TRACE_EN: - - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B)) - platform_h2c_id = H2C_8814A_FW_TRACE_EN; - else - platform_h2c_id = H2C_FW_TRACE_EN; - - #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - - - #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) +#endif + {} +#endif + + break; + + + /* 1 [6] */ + case PHYDM_H2C_DYNAMIC_TX_PATH: + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (p_dm_odm->support_ic_type == ODM_RTL8814A) + platform_h2c_id = H2C_8814A_DYNAMIC_TX_PATH; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if (RTL8814A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8814A) + platform_h2c_id = H2C_DYNAMIC_TX_PATH; +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +#if (RTL8814A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8814A) + platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH; +#endif + +#endif + + break; + + /* [7]*/ + case PHYDM_H2C_FW_TRACE_EN: + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) + platform_h2c_id = H2C_8814A_FW_TRACE_EN; + else + platform_h2c_id = H2C_FW_TRACE_EN; + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + + platform_h2c_id = 0x49; + +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) - platform_h2c_id = H2C_88XX_FW_TRACE_EN; - else - #endif - #if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - platform_h2c_id = H2C_8812_FW_TRACE_EN; + if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) + platform_h2c_id = H2C_88XX_FW_TRACE_EN; + else +#endif +#if (RTL8812A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8812) + platform_h2c_id = H2C_8812_FW_TRACE_EN; else - #endif - {} +#endif + {} - #endif - - break; +#endif + + break; - case PHYDM_H2C_TXBF: + case PHYDM_H2C_TXBF: #if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) - platform_h2c_id = 0x41; /*H2C_TxBF*/ + platform_h2c_id = 0x41; /*H2C_TxBF*/ #endif break; - case PHYDM_H2C_MU: -#if (RTL8822B_SUPPORT == 1) - platform_h2c_id = 0x4a; /*H2C_MU*/ -#endif + case PHYDM_H2C_MU: +#if (RTL8822B_SUPPORT == 1) + platform_h2c_id = 0x4a; /*H2C_MU*/ +#endif break; - default: - platform_h2c_id=0xff; - break; - } - + default: + platform_h2c_id = phydm_h2c_id; + break; + } + return platform_h2c_id; - + } /*ODM FW relative API.*/ -VOID -ODM_FillH2CCmd( - IN PDM_ODM_T pDM_Odm, - IN u1Byte phydm_h2c_id, - IN u4Byte CmdLen, - IN pu1Byte pCmdBuffer +void +odm_fill_h2c_cmd( + struct PHY_DM_STRUCT *p_dm_odm, + u8 phydm_h2c_id, + u32 cmd_len, + u8 *p_cmd_buffer ) { - PADAPTER Adapter = pDM_Odm->Adapter; - u1Byte platform_h2c_id; +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; +#else + struct _ADAPTER *adapter = p_dm_odm->adapter; +#endif + u8 platform_h2c_id; - platform_h2c_id=phydm_trans_h2c_id(pDM_Odm, phydm_h2c_id); + platform_h2c_id = phydm_trans_h2c_id(p_dm_odm, phydm_h2c_id); - if (platform_h2c_id == 0xff) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Wrong H2C CMD-ID !! platform_h2c_id==0xff , PHYDM_ElementID=((%d ))\n", phydm_h2c_id)); - return; - } + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] platform_h2c_id = ((0x%x))\n", platform_h2c_id)); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (pDM_Odm->SupportICType == ODM_RTL8188E) { - if (!pDM_Odm->RaSupport88E) - FillH2CCmd88E(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); - } else if (pDM_Odm->SupportICType == ODM_RTL8814A) - FillH2CCmd8814A(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); - else if (pDM_Odm->SupportICType == ODM_RTL8822B) + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + if (!p_dm_odm->ra_support88e) + FillH2CCmd88E(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); + } else if (p_dm_odm->support_ic_type == ODM_RTL8814A) + FillH2CCmd8814A(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); + else if (p_dm_odm->support_ic_type == ODM_RTL8822B) #if (RTL8822B_SUPPORT == 1) - FillH2CCmd8822B(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); -#endif - else - FillH2CCmd(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); - -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_hal_fill_h2c_cmd(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); - -#elif(DM_ODM_SUPPORT_TYPE & ODM_AP) -#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) - GET_HAL_INTERFACE(pDM_Odm->priv)->FillH2CCmdHandler(pDM_Odm->priv, platform_h2c_id, CmdLen, pCmdBuffer); - else + FillH2CCmd8822B(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); +#endif + else + FillH2CCmd(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#ifdef DM_ODM_CE_MAC80211 + rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, platform_h2c_id, + cmd_len, p_cmd_buffer); +#else + + rtw_hal_fill_h2c_cmd(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); +#endif + +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) + GET_HAL_INTERFACE(p_dm_odm->priv)->fill_h2c_cmd_handler(p_dm_odm->priv, platform_h2c_id, cmd_len, p_cmd_buffer); + else #endif -#if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - FillH2CCmd8812(pDM_Odm->priv, platform_h2c_id, CmdLen, pCmdBuffer); +#if (RTL8812A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8812) + fill_h2c_cmd8812(p_dm_odm->priv, platform_h2c_id, cmd_len, p_cmd_buffer); else #endif {} #endif } -u1Byte +u8 phydm_c2H_content_parsing( - IN PVOID pDM_VOID, - IN u1Byte c2hCmdId, - IN u1Byte c2hCmdLen, - IN pu1Byte tmpBuf + void *p_dm_void, + u8 c2h_cmd_id, + u8 c2h_cmd_len, + u8 *tmp_buf ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - #endif - u1Byte Extend_c2hSubID = 0; - u1Byte find_c2h_cmd = TRUE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; +#endif + u8 extend_c2h_sub_id = 0; + u8 find_c2h_cmd = true; - switch (c2hCmdId) { + switch (c2h_cmd_id) { case PHYDM_C2H_DBG: - phydm_fw_trace_handler(pDM_Odm, tmpBuf, c2hCmdLen); + phydm_fw_trace_handler(p_dm_odm, tmp_buf, c2h_cmd_len); break; case PHYDM_C2H_RA_RPT: - phydm_c2h_ra_report_handler(pDM_Odm, tmpBuf, c2hCmdLen); + phydm_c2h_ra_report_handler(p_dm_odm, tmp_buf, c2h_cmd_len); break; case PHYDM_C2H_RA_PARA_RPT: - ODM_C2HRaParaReportHandler(pDM_Odm, tmpBuf, c2hCmdLen); + odm_c2h_ra_para_report_handler(p_dm_odm, tmp_buf, c2h_cmd_len); break; - + case PHYDM_C2H_DYNAMIC_TX_PATH_RPT: - if (pDM_Odm->SupportICType & (ODM_RTL8814A)) - phydm_c2h_dtp_handler(pDM_Odm, tmpBuf, c2hCmdLen); + if (p_dm_odm->support_ic_type & (ODM_RTL8814A)) + phydm_c2h_dtp_handler(p_dm_odm, tmp_buf, c2h_cmd_len); break; - + case PHYDM_C2H_IQK_FINISH: - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) { - +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) { + RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n")); - PlatformAcquireSpinLock(Adapter, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - PlatformReleaseSpinLock(Adapter, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = 0; - pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime(pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); + odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + p_dm_odm->rf_calibrate_info.iqk_progressing_time = 0; + p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); } - - #endif + +#endif break; case PHYDM_C2H_DBG_CODE: - phydm_fw_trace_handler_code(pDM_Odm, tmpBuf, c2hCmdLen); - break; + phydm_fw_trace_handler_code(p_dm_odm, tmp_buf, c2h_cmd_len); + break; case PHYDM_C2H_EXTEND: - Extend_c2hSubID= tmpBuf[0]; - if (Extend_c2hSubID == PHYDM_EXTEND_C2H_DBG_PRINT) - phydm_fw_trace_handler_8051(pDM_Odm, tmpBuf, c2hCmdLen); - + extend_c2h_sub_id = tmp_buf[0]; + if (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT) + phydm_fw_trace_handler_8051(p_dm_odm, tmp_buf, c2h_cmd_len); + break; default: - find_c2h_cmd = FALSE; + find_c2h_cmd = false; break; } @@ -929,33 +1065,234 @@ phydm_c2H_content_parsing( } -u8Byte -ODM_GetCurrentTime( - IN PDM_ODM_T pDM_Odm - ) +u64 +odm_get_current_time( + struct PHY_DM_STRUCT *p_dm_odm +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) return 0; -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - return (u8Byte)rtw_get_current_time(); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + return jiffies; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return (u64)rtw_get_current_time(); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) return PlatformGetCurrentTime(); #endif } -u8Byte -ODM_GetProgressingTime( - IN PDM_ODM_T pDM_Odm, - IN u8Byte Start_Time - ) +u64 +odm_get_progressing_time( + struct PHY_DM_STRUCT *p_dm_odm, + u64 start_time +) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) return 0; -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - return rtw_get_passing_time_ms((u4Byte)Start_Time); -#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) - return ((PlatformGetCurrentTime() - Start_Time)>>10); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + return jiffies_to_msecs(jiffies - (u32)start_time); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return rtw_get_passing_time_ms((u32)start_time); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + return ((PlatformGetCurrentTime() - start_time) >> 10); #endif } +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) && !defined(DM_ODM_CE_MAC80211) + +void +phydm_set_hw_reg_handler_interface ( + struct PHY_DM_STRUCT *p_dm_odm, + u8 RegName, + u8 *val + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + struct _ADAPTER *adapter = p_dm_odm->adapter; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + adapter->HalFunc.SetHwRegHandler(adapter, RegName, val); +#else + adapter->hal_func.set_hw_reg_handler(adapter, RegName, val); +#endif + +#endif + +} + +void +phydm_get_hal_def_var_handler_interface ( + struct PHY_DM_STRUCT *p_dm_odm, + enum _HAL_DEF_VARIABLE e_variable, + void *p_value + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + struct _ADAPTER *adapter = p_dm_odm->adapter; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + adapter->HalFunc.GetHalDefVarHandler(adapter, e_variable, p_value); +#else + adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, p_value); +#endif + +#endif +} + +#endif + +void +odm_set_tx_power_index_by_rate_section ( + struct PHY_DM_STRUCT *p_dm_odm, + u8 RFPath, + u8 Channel, + u8 RateSection + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PHY_SetTxPowerIndexByRateSection(adapter, RFPath, Channel, RateSection); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = p_dm_odm->adapter; + + phy_set_tx_power_index_by_rs(adapter, Channel, RFPath, RateSection); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + phy_set_tx_power_index_by_rate_section(p_dm_odm->adapter, RFPath, Channel, RateSection); +#endif +} + + +u8 +odm_get_tx_power_index ( + struct PHY_DM_STRUCT *p_dm_odm, + u8 RFPath, + u8 tx_rate, + u8 band_width, + u8 Channel + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + return PHY_GetTxPowerIndex(p_dm_odm->adapter, RFPath, tx_rate, band_width, Channel); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = p_dm_odm->adapter; + return phy_get_tx_power_index(adapter, (enum odm_rf_radio_path_e)RFPath, tx_rate, band_width, Channel); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return phy_get_tx_power_index(p_dm_odm->adapter, RFPath, tx_rate, band_width, Channel); +#endif +} + + + +u8 +odm_efuse_one_byte_read( + struct PHY_DM_STRUCT *p_dm_odm, + u16 addr, + u8 *data, + boolean b_pseu_do_test + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + + return (u8)EFUSE_OneByteRead(adapter, addr, data, b_pseu_do_test); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = p_dm_odm->adapter; + + return efuse_onebyte_read(adapter, addr, data, b_pseu_do_test); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return efuse_onebyte_read(p_dm_odm->adapter, addr, data, b_pseu_do_test); +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) + /*ReadEFuseByte(p_dm_odm->priv, addr, data);*/ + /*return true;*/ +#endif +} + + + +void +odm_efuse_logical_map_read( + struct PHY_DM_STRUCT *p_dm_odm, + u8 type, + u16 offset, + u32 *data +) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + + EFUSE_ShadowRead(adapter, type, offset, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + efuse_logical_map_read(p_dm_odm->adapter, type, offset, data); +#endif +} + +enum hal_status +odm_iq_calibrate_by_fw( + struct PHY_DM_STRUCT *p_dm_odm, + u8 clear, + u8 segment + ) +{ + enum hal_status iqk_result = HAL_STATUS_FAILURE; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + + if (HAL_MAC_FWIQK_Trigger(&GET_HAL_MAC_INFO(adapter), clear, segment) == 0) + iqk_result = HAL_STATUS_SUCCESS; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + #ifdef RTW_HALMAC + #include "../hal_halmac.h" + struct _ADAPTER *adapter = p_dm_odm->adapter; + + if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0) + iqk_result = HAL_STATUS_SUCCESS; + #endif +#endif + return iqk_result; +} + +void +odm_cmn_info_ptr_array_hook( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_cmninfo_e cmn_info, + u16 index, + void *p_value +) +{ + switch (cmn_info) { + /*Dynamic call by reference pointer. */ + case ODM_CMNINFO_STA_STATUS: + p_dm_odm->p_odm_sta_info[index] = (struct sta_info *)p_value; + + if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[index])) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->AssociatedMacId] = index; /*associated_mac_id are unique bttween different adapter*/ +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->aid] = index; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + p_dm_odm->platform2phydm_macid_table[index] = index; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->mac_id] = index; +#endif + break; + /* To remove the compiler warning, must add an empty default statement to handle the other values. */ + default: + /* do nothing */ + break; + } + +} + +void +phydm_cmn_sta_info_hook( + struct PHY_DM_STRUCT *p_dm_odm, + u8 mac_id, + struct cmn_sta_info *pcmn_sta_info +) +{ + p_dm_odm->p_phydm_sta_info[mac_id] = pcmn_sta_info; + +} diff --git a/hal/phydm/phydm_interface.h b/hal/phydm/phydm_interface.h index 5e3154e..05101ce 100644 --- a/hal/phydm/phydm_interface.h +++ b/hal/phydm/phydm_interface.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __ODM_INTERFACE_H__ @@ -24,26 +19,26 @@ #define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/ -// -// =========== Constant/Structure/Enum/... Define -// +/* + * =========== Constant/Structure/Enum/... Define + * */ -// -// =========== Macro Define -// +/* + * =========== Macro Define + * */ #define _reg_all(_name) ODM_##_name #define _reg_ic(_name, _ic) ODM_##_name##_ic #define _bit_all(_name) BIT_##_name #define _bit_ic(_name, _ic) BIT_##_name##_ic -// _cat: implemented by Token-Pasting Operator. +/* _cat: implemented by Token-Pasting Operator. */ #if 0 #define _cat(_name, _ic_type, _func) \ - ( \ - _func##_all(_name) \ + (\ + _func##_all(_name) \ ) #endif @@ -52,62 +47,61 @@ #define ODM_REG_DIG_11N 0xC50 #define ODM_REG_DIG_11AC 0xDDD -ODM_REG(DIG,_pDM_Odm) +ODM_REG(DIG,_pdm_odm) =====================================*/ -#define _reg_11N(_name) ODM_REG_##_name##_11N +#define _reg_11N(_name) ODM_REG_##_name##_11N #define _reg_11AC(_name) ODM_REG_##_name##_11AC -#define _bit_11N(_name) ODM_BIT_##_name##_11N +#define _bit_11N(_name) ODM_BIT_##_name##_11N #define _bit_11AC(_name) ODM_BIT_##_name##_11AC #ifdef __ECOS #define _rtk_cat(_name, _ic_type, _func) \ - ( \ - ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ - _func##_11AC(_name) \ + (\ + ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ + _func##_11AC(_name) \ ) #else #define _cat(_name, _ic_type, _func) \ - ( \ - ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ - _func##_11AC(_name) \ + (\ + ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ + _func##_11AC(_name) \ ) #endif -/* -// only sample code -//#define _cat(_name, _ic_type, _func) \ -// ( \ -// ((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \ -// _func##_ic(_name, _8195) \ -// ) -*/ - -// _name: name of register or bit. -// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" -// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. +/* + * only sample code + *#define _cat(_name, _ic_type, _func) \ + * ( \ + * ((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) : \ + * _func##_ic(_name, _8195) \ + * ) + */ + +/* _name: name of register or bit. + * Example: "ODM_REG(R_A_AGC_CORE1, p_dm_odm)" + * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on support_ic_type. */ #ifdef __ECOS -#define ODM_REG(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _reg) -#define ODM_BIT(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _bit) + #define ODM_REG(_name, _pdm_odm) _rtk_cat(_name, _pdm_odm->support_ic_type, _reg) + #define ODM_BIT(_name, _pdm_odm) _rtk_cat(_name, _pdm_odm->support_ic_type, _bit) #else -#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) -#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) + #define ODM_REG(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _reg) + #define ODM_BIT(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _bit) #endif -typedef enum _PHYDM_H2C_CMD { - ODM_H2C_RSSI_REPORT = 0, - ODM_H2C_PSD_RESULT = 1, - ODM_H2C_PathDiv = 2, - ODM_H2C_WIFI_CALIBRATION = 3, - ODM_H2C_IQ_CALIBRATION = 4, - ODM_H2C_RA_PARA_ADJUST = 5, - PHYDM_H2C_DYNAMIC_TX_PATH = 6, - PHYDM_H2C_FW_TRACE_EN = 7, - PHYDM_H2C_TXBF = 8, - PHYDM_H2C_MU = 9, +enum phydm_h2c_cmd { + PHYDM_H2C_TXBF = 0x41, + ODM_H2C_RSSI_REPORT = 0x42, + ODM_H2C_IQ_CALIBRATION = 0x45, + ODM_H2C_RA_PARA_ADJUST = 0x47, + PHYDM_H2C_DYNAMIC_TX_PATH = 0x48, + PHYDM_H2C_FW_TRACE_EN = 0x49, + ODM_H2C_WIFI_CALIBRATION = 0x6d, + PHYDM_H2C_MU = 0x4a, + PHYDM_H2C_FW_GENERAL_INIT = 0x4c, ODM_MAX_H2CCMD -}PHYDM_H2C_CMD; +}; -typedef enum _PHYDM_C2H_EVT { +enum phydm_c2h_evt { PHYDM_C2H_DBG = 0, PHYDM_C2H_LB = 1, PHYDM_C2H_XBF = 2, @@ -115,314 +109,397 @@ typedef enum _PHYDM_C2H_EVT { PHYDM_C2H_INFO = 9, PHYDM_C2H_BT_MP = 11, PHYDM_C2H_RA_RPT = 12, - PHYDM_C2H_RA_PARA_RPT=14, + PHYDM_C2H_RA_PARA_RPT = 14, PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, PHYDM_C2H_IQK_FINISH = 17, /*0x11*/ PHYDM_C2H_DBG_CODE = 0xFE, PHYDM_C2H_EXTEND = 0xFF, -}PHYDM_C2H_EVT; +}; -typedef enum _PHYDM_EXTEND_C2H_EVT { +enum phydm_extend_c2h_evt { PHYDM_EXTEND_C2H_DBG_PRINT = 0 -}PHYDM_EXTEND_C2H_EVT; +}; +enum phydm_halmac_param { + PHYDM_HALMAC_CMD_MAC_W8 = 0, + PHYDM_HALMAC_CMD_MAC_W16 = 1, + PHYDM_HALMAC_CMD_MAC_W32 = 2, + PHYDM_HALMAC_CMD_BB_W8, + PHYDM_HALMAC_CMD_BB_W16, + PHYDM_HALMAC_CMD_BB_W32, + PHYDM_HALMAC_CMD_RF_W, + PHYDM_HALMAC_CMD_DELAY_US, + PHYDM_HALMAC_CMD_DELAY_MS, + PHYDM_HALMAC_CMD_END = 0XFF, +}; -// -// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. -// Suggest HW team to use thread instead of workitem. Windows also support the feature. -// -#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) -typedef void *PRT_WORK_ITEM ; -typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE; -typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext); +/* + * =========== Extern Variable ??? It should be forbidden. + * */ -#if 0 -typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE; - -typedef struct _RT_WORK_ITEM -{ - - RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object. - PVOID Adapter; // Pointer to Adapter object. - PVOID pContext; // Parameter to passed to CallBackFunc(). - RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem. - u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled. - PVOID pPlatformExt; // Pointer to platform-dependent extension. - BOOLEAN bFree; - char szID[36]; // An identity string of this workitem. -}RT_WORK_ITEM, *PRT_WORK_ITEM; -#endif +/* + * =========== EXtern Function Prototype + * */ -#endif +u8 +odm_read_1byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr +); -// -// =========== Extern Variable ??? It should be forbidden. -// +u16 +odm_read_2byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr +); +u32 +odm_read_4byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr +); -// -// =========== EXtern Function Prototype -// +void +odm_write_1byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u8 data +); +void +odm_write_2byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u16 data +); -u1Byte -ODM_Read1Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr - ); +void +odm_write_4byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 data +); -u2Byte -ODM_Read2Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr - ); +void +odm_set_mac_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask, + u32 data +); -u4Byte -ODM_Read4Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr - ); +u32 +odm_get_mac_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask +); -VOID -ODM_Write1Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u1Byte Data - ); +void +odm_set_bb_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask, + u32 data +); -VOID -ODM_Write2Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u2Byte Data - ); +u32 +odm_get_bb_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask +); -VOID -ODM_Write4Byte( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte Data - ); +void +odm_set_rf_reg( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e e_rf_path, + u32 reg_addr, + u32 bit_mask, + u32 data +); -VOID -ODM_SetMACReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ); +u32 +odm_get_rf_reg( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e e_rf_path, + u32 reg_addr, + u32 bit_mask +); -u4Byte -ODM_GetMACReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask - ); -VOID -ODM_SetBBReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ); +enum hal_status +phydm_set_reg_by_fw( + struct PHY_DM_STRUCT *p_dm_odm, + enum phydm_halmac_param config_type, + u32 offset, + u32 data, + u32 mask, + enum odm_rf_radio_path_e e_rf_path, + u32 delay_time +); -u4Byte -ODM_GetBBReg( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RegAddr, - IN u4Byte BitMask - ); +/* + * Memory Relative Function. + * */ +void +odm_allocate_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void **p_ptr, + u32 length +); +void +odm_free_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void *p_ptr, + u32 length +); -VOID -ODM_SetRFReg( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ); +void +odm_move_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void *p_dest, + void *p_src, + u32 length +); -u4Byte -ODM_GetRFReg( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ); +s32 odm_compare_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void *p_buf1, + void *p_buf2, + u32 length +); +void odm_memory_set +(struct PHY_DM_STRUCT *p_dm_odm, + void *pbuf, + s8 value, + u32 length); + +/* + * ODM MISC-spin lock relative API. + * */ +void +odm_acquire_spin_lock( + struct PHY_DM_STRUCT *p_dm_odm, + enum rt_spinlock_type type +); -// -// Memory Relative Function. -// -VOID -ODM_AllocateMemory( - IN PDM_ODM_T pDM_Odm, - OUT PVOID *pPtr, - IN u4Byte length - ); -VOID -ODM_FreeMemory( - IN PDM_ODM_T pDM_Odm, - OUT PVOID pPtr, - IN u4Byte length - ); +void +odm_release_spin_lock( + struct PHY_DM_STRUCT *p_dm_odm, + enum rt_spinlock_type type +); -VOID -ODM_MoveMemory( - IN PDM_ODM_T pDM_Odm, - OUT PVOID pDest, - IN PVOID pSrc, - IN u4Byte Length - ); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +/* + * ODM MISC-workitem relative API. + * */ +void +odm_initialize_work_item( + struct PHY_DM_STRUCT *p_dm_odm, + PRT_WORK_ITEM p_rt_work_item, + RT_WORKITEM_CALL_BACK rt_work_item_callback, + void *p_context, + const char *sz_id +); -s4Byte ODM_CompareMemory( - IN PDM_ODM_T pDM_Odm, - IN PVOID pBuf1, - IN PVOID pBuf2, - IN u4Byte length - ); - -void ODM_Memory_Set - (IN PDM_ODM_T pDM_Odm, - IN PVOID pbuf, - IN s1Byte value, - IN u4Byte length); - -// -// ODM MISC-spin lock relative API. -// -VOID -ODM_AcquireSpinLock( - IN PDM_ODM_T pDM_Odm, - IN RT_SPINLOCK_TYPE type - ); +void +odm_start_work_item( + PRT_WORK_ITEM p_rt_work_item +); -VOID -ODM_ReleaseSpinLock( - IN PDM_ODM_T pDM_Odm, - IN RT_SPINLOCK_TYPE type - ); +void +odm_stop_work_item( + PRT_WORK_ITEM p_rt_work_item +); +void +odm_free_work_item( + PRT_WORK_ITEM p_rt_work_item +); -// -// ODM MISC-workitem relative API. -// -VOID -ODM_InitializeWorkItem( - IN PDM_ODM_T pDM_Odm, - IN PRT_WORK_ITEM pRtWorkItem, - IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, - IN PVOID pContext, - IN const char* szID - ); +void +odm_schedule_work_item( + PRT_WORK_ITEM p_rt_work_item +); -VOID -ODM_StartWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ); +boolean +odm_is_work_item_scheduled( + PRT_WORK_ITEM p_rt_work_item +); +#endif -VOID -ODM_StopWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ); +/* + * ODM Timer relative API. + * */ +void +odm_stall_execution( + u32 us_delay +); -VOID -ODM_FreeWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ); +void +ODM_delay_ms(u32 ms); -VOID -ODM_ScheduleWorkItem( - IN PRT_WORK_ITEM pRtWorkItem - ); -VOID -ODM_IsWorkItemScheduled( - IN PRT_WORK_ITEM pRtWorkItem - ); -// -// ODM Timer relative API. -// -VOID -ODM_StallExecution( - IN u4Byte usDelay - ); +void +ODM_delay_us(u32 us); -VOID -ODM_delay_ms(IN u4Byte ms); +void +ODM_sleep_ms(u32 ms); +void +ODM_sleep_us(u32 us); +void +odm_set_timer( + struct PHY_DM_STRUCT *p_dm_odm, + #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + struct legacy_timer_emu *p_timer, + #else + struct timer_list *p_timer, + #endif + u32 ms_delay +); -VOID -ODM_delay_us(IN u4Byte us); +void +odm_initialize_timer( + struct PHY_DM_STRUCT *p_dm_odm, + #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + struct legacy_timer_emu *p_timer, + #else + struct timer_list *p_timer, + #endif + void *call_back_func, + void *p_context, + const char *sz_id +); -VOID -ODM_sleep_ms(IN u4Byte ms); +void +odm_cancel_timer( + struct PHY_DM_STRUCT *p_dm_odm, + #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + struct legacy_timer_emu *p_timer + #else + struct timer_list *p_timer + #endif +); -VOID -ODM_sleep_us(IN u4Byte us); +void +odm_release_timer( + struct PHY_DM_STRUCT *p_dm_odm, + #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + struct legacy_timer_emu *p_timer + #else + struct timer_list *p_timer + #endif +); -VOID -ODM_SetTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer, - IN u4Byte msDelay - ); +/* + * ODM FW relative API. + * */ +void +odm_fill_h2c_cmd( + struct PHY_DM_STRUCT *p_dm_odm, + u8 element_id, + u32 cmd_len, + u8 *p_cmd_buffer +); -VOID -ODM_InitializeTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer, - IN RT_TIMER_CALL_BACK CallBackFunc, - IN PVOID pContext, - IN const char* szID - ); +u8 +phydm_c2H_content_parsing( + void *p_dm_void, + u8 c2h_cmd_id, + u8 c2h_cmd_len, + u8 *tmp_buf +); + +u64 +odm_get_current_time( + struct PHY_DM_STRUCT *p_dm_odm +); +u64 +odm_get_progressing_time( + struct PHY_DM_STRUCT *p_dm_odm, + u64 start_time +); -VOID -ODM_CancelTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) && !defined(DM_ODM_CE_MAC80211) + +void +phydm_set_hw_reg_handler_interface ( + struct PHY_DM_STRUCT *p_dm_odm, + u8 reg_Name, + u8 *val ); -VOID -ODM_ReleaseTimer( - IN PDM_ODM_T pDM_Odm, - IN PRT_TIMER pTimer +void +phydm_get_hal_def_var_handler_interface ( + struct PHY_DM_STRUCT *p_dm_odm, + enum _HAL_DEF_VARIABLE e_variable, + void *p_value ); -// -// ODM FW relative API. -// -VOID -ODM_FillH2CCmd( - IN PDM_ODM_T pDM_Odm, - IN u1Byte ElementID, - IN u4Byte CmdLen, - IN pu1Byte pCmdBuffer +#endif + +void +odm_set_tx_power_index_by_rate_section ( + struct PHY_DM_STRUCT *p_dm_odm, + u8 RFPath, + u8 Channel, + u8 RateSection ); -u1Byte -phydm_c2H_content_parsing( - IN PVOID pDM_VOID, - IN u1Byte c2hCmdId, - IN u1Byte c2hCmdLen, - IN pu1Byte tmpBuf +u8 +odm_get_tx_power_index ( + struct PHY_DM_STRUCT *p_dm_odm, + u8 RFPath, + u8 tx_rate, + u8 band_width, + u8 Channel ); -u8Byte -ODM_GetCurrentTime( - IN PDM_ODM_T pDM_Odm - ); -u8Byte -ODM_GetProgressingTime( - IN PDM_ODM_T pDM_Odm, - IN u8Byte Start_Time - ); +u8 +odm_efuse_one_byte_read( + struct PHY_DM_STRUCT *p_dm_odm, + u16 addr, + u8 *data, + boolean b_pseu_do_test +); + +void +odm_efuse_logical_map_read( + struct PHY_DM_STRUCT *p_dm_odm, + u8 type, + u16 offset, + u32 *data +); + +enum hal_status +odm_iq_calibrate_by_fw( + struct PHY_DM_STRUCT *p_dm_odm, + u8 clear, + u8 segment +); + +void +odm_cmn_info_ptr_array_hook( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_cmninfo_e cmn_info, + u16 index, + void *p_value +); + +void +phydm_cmn_sta_info_hook( + struct PHY_DM_STRUCT *p_dm_odm, + u8 index, + struct cmn_sta_info *pcmn_sta_info +); -#endif // __ODM_INTERFACE_H__ +#endif /* __ODM_INTERFACE_H__ */ diff --git a/hal/phydm/phydm_noisemonitor.c b/hal/phydm/phydm_noisemonitor.c index 24646ae..8a34ba1 100644 --- a/hal/phydm/phydm_noisemonitor.c +++ b/hal/phydm/phydm_noisemonitor.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,295 +11,283 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" #include "phydm_noisemonitor.h" -//================================================= -// This function is for inband noise test utility only -// To obtain the inband noise level(dbm), do the following. -// 1. disable DIG and Power Saving -// 2. Set initial gain = 0x1a -// 3. Stop updating idle time pwer report (for driver read) -// - 0x80c[25] -// -//================================================= +/* ************************************************* + * This function is for inband noise test utility only + * To obtain the inband noise level(dbm), do the following. + * 1. disable DIG and Power Saving + * 2. Set initial gain = 0x1a + * 3. Stop updating idle time pwer report (for driver read) + * - 0x80c[25] + * + * ************************************************* */ + +#define VALID_MIN -35 +#define VALID_MAX 10 +#define VALID_CNT 5 -#define Valid_Min -35 -#define Valid_Max 10 -#define ValidCnt 5 +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) +void phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path) +{ + u8 rf_path; + + for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { + /* printk("%s PATH_%d - sum = %d, VALID_CNT = %d\n",__FUNCTION__,rf_path,noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]); */ + if (noise_data->valid_cnt[rf_path]) + noise_data->sum[rf_path] /= noise_data->valid_cnt[rf_path]; + else + noise_data->sum[rf_path] = 0; + } +} -s2Byte odm_InbandNoise_Monitor_NSeries(PDM_ODM_T pDM_Odm,u8 bPauseDIG,u8 IGIValue,u32 max_time) +s16 odm_inband_noise_monitor_n_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_dig, u8 igi_value, u32 max_time) { - u4Byte tmp4b; - u1Byte max_rf_path=0,rf_path; - u1Byte reg_c50, reg_c58,valid_done=0; + u32 tmp4b; + u8 max_rf_path = 0, rf_path; + u8 reg_c50, reg_c58, valid_done = 0; struct noise_level noise_data; - u8Byte start = 0, func_start = 0, func_end = 0; + u64 start = 0, func_start = 0, func_end = 0; + + func_start = odm_get_current_time(p_dm_odm); + p_dm_odm->noise_level.noise_all = 0; - func_start = ODM_GetCurrentTime(pDM_Odm); - pDM_Odm->noise_level.noise_all = 0; - - if((pDM_Odm->RFType == ODM_1T2R) ||(pDM_Odm->RFType == ODM_2T2R)) + if ((p_dm_odm->rf_type == ODM_1T2R) || (p_dm_odm->rf_type == ODM_2T2R)) max_rf_path = 2; else max_rf_path = 1; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("odm_DebugControlInbandNoise_Nseries() ==> \n")); - - ODM_Memory_Set(pDM_Odm,&noise_data,0,sizeof(struct noise_level)); - - // - // Step 1. Disable DIG && Set initial gain. - // - - if(bPauseDIG) - { - odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue); - } - // - // Step 2. Disable all power save for read registers - // - //dcmd_DebugControlPowerSave(pAdapter, PSDisable); - - // - // Step 3. Get noise power level - // - start = ODM_GetCurrentTime(pDM_Odm); - while(1) - { - - //Stop updating idle time pwer report (for driver read) - ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 1); - - //Read Noise Floor Report - tmp4b = ODM_GetBBReg(pDM_Odm, 0x8f8,bMaskDWord ); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b)); - - //ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, TestInitialGain); - //if(max_rf_path == 2) - // ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, TestInitialGain); - - //update idle time pwer report per 5us - ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 0); - - noise_data.value[ODM_RF_PATH_A] = (u1Byte)(tmp4b&0xff); - noise_data.value[ODM_RF_PATH_B] = (u1Byte)((tmp4b&0xff00)>>8); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n", + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() ==>\n")); + + odm_memory_set(p_dm_odm, &noise_data, 0, sizeof(struct noise_level)); + + /* */ + /* step 1. Disable DIG && Set initial gain. */ + /* */ + + if (is_pause_dig) + odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value); + /* */ + /* step 2. Disable all power save for read registers */ + /* */ + /* dcmd_DebugControlPowerSave(p_adapter, PSDisable); */ + + /* */ + /* step 3. Get noise power level */ + /* */ + start = odm_get_current_time(p_dm_odm); + while (1) { + + /* Stop updating idle time pwer report (for driver read) */ + odm_set_bb_reg(p_dm_odm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1); + + /* Read Noise Floor Report */ + tmp4b = odm_get_bb_reg(p_dm_odm, 0x8f8, MASKDWORD); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b)); + + /* odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0, TestInitialGain); */ + /* if(max_rf_path == 2) */ + /* odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0, TestInitialGain); */ + + /* update idle time pwer report per 5us */ + odm_set_bb_reg(p_dm_odm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0); + + noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b & 0xff); + noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n", noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B])); - for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) - { - noise_data.sval[rf_path] = (s1Byte)noise_data.value[rf_path]; + for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { + noise_data.sval[rf_path] = (s8)noise_data.value[rf_path]; noise_data.sval[rf_path] /= 2; - } - - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("sval_a = %d, sval_b = %d\n", + } + + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("sval_a = %d, sval_b = %d\n", noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B])); - //ODM_delay_ms(10); - //ODM_sleep_ms(10); - - for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) - { - if( (noise_data.valid_cnt[rf_path] < ValidCnt) && (noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min)) - { - noise_data.valid_cnt[rf_path]++; - noise_data.sum[rf_path] += noise_data.sval[rf_path]; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("RF_Path:%d Valid sval = %d\n", rf_path,noise_data.sval[rf_path])); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Sum of sval = %d, \n", noise_data.sum[rf_path])); - if(noise_data.valid_cnt[rf_path] == ValidCnt) - { - valid_done++; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("After divided, RF_Path:%d ,sum = %d \n", rf_path,noise_data.sum[rf_path])); - } - + /* ODM_delay_ms(10); */ + /* ODM_sleep_ms(10); */ + + for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { + if (!(noise_data.valid_cnt[rf_path] < VALID_CNT) || !(noise_data.sval[rf_path] < VALID_MAX && noise_data.sval[rf_path] >= VALID_MIN)) { + continue; } - - } - //printk("####### valid_done:%d #############\n",valid_done); - if ((valid_done==max_rf_path) || (ODM_GetProgressingTime(pDM_Odm,start) > max_time)) - { - for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) - { - //printk("%s PATH_%d - sum = %d, valid_cnt = %d \n",__FUNCTION__,rf_path,noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]); - if(noise_data.valid_cnt[rf_path]) - noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path]; - else - noise_data.sum[rf_path] = 0; + noise_data.valid_cnt[rf_path]++; + noise_data.sum[rf_path] += noise_data.sval[rf_path]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("rf_path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", noise_data.sum[rf_path])); + if (noise_data.valid_cnt[rf_path] == VALID_CNT) { + valid_done++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, rf_path:%d,sum = %d\n", rf_path, noise_data.sum[rf_path])); } + + } + + /* printk("####### valid_done:%d #############\n",valid_done); */ + if ((valid_done == max_rf_path) || (odm_get_progressing_time(p_dm_odm, start) > max_time)) { + phydm_set_noise_data_sum(&noise_data, max_rf_path); break; } } - reg_c50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0); - reg_c50 &= ~BIT7; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XAAGCCore1, reg_c50, reg_c50)); - pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = (u1Byte)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]); - pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A]; - - if(max_rf_path == 2){ - reg_c58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0); - reg_c58 &= ~BIT7; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XBAGCCore1, reg_c58, reg_c58)); - pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = (u1Byte)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]); - pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B]; + reg_c50 = (u8)odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0); + reg_c50 &= ~BIT(7); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", REG_OFDM_0_XA_AGC_CORE1, reg_c50, reg_c50)); + p_dm_odm->noise_level.noise[ODM_RF_PATH_A] = (s8)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]); + p_dm_odm->noise_level.noise_all += p_dm_odm->noise_level.noise[ODM_RF_PATH_A]; + + if (max_rf_path == 2) { + reg_c58 = (u8)odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0); + reg_c58 &= ~BIT(7); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", REG_OFDM_0_XB_AGC_CORE1, reg_c58, reg_c58)); + p_dm_odm->noise_level.noise[ODM_RF_PATH_B] = (s8)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]); + p_dm_odm->noise_level.noise_all += p_dm_odm->noise_level.noise[ODM_RF_PATH_B]; } - pDM_Odm->noise_level.noise_all /= max_rf_path; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("noise_a = %d, noise_b = %d\n", - pDM_Odm->noise_level.noise[ODM_RF_PATH_A], - pDM_Odm->noise_level.noise[ODM_RF_PATH_B])); - - // - // Step 4. Recover the Dig - // - if(bPauseDIG) - { - odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue); - } - func_end = ODM_GetProgressingTime(pDM_Odm,func_start) ; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n")); - return pDM_Odm->noise_level.noise_all; + p_dm_odm->noise_level.noise_all /= max_rf_path; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise_a = %d, noise_b = %d\n", + p_dm_odm->noise_level.noise[ODM_RF_PATH_A], + p_dm_odm->noise_level.noise[ODM_RF_PATH_B])); + + /* */ + /* step 4. Recover the Dig */ + /* */ + if (is_pause_dig) + odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value); + func_end = odm_get_progressing_time(p_dm_odm, func_start) ; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n")); + return p_dm_odm->noise_level.noise_all; } -s2Byte -odm_InbandNoise_Monitor_ACSeries(PDM_ODM_T pDM_Odm, u8 bPauseDIG, u8 IGIValue, u32 max_time - ) +s16 +odm_inband_noise_monitor_ac_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_dig, u8 igi_value, u32 max_time + ) { - s4Byte rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/ - s4Byte value32, pwdb_A = 0, sval, noise, sum; - BOOLEAN pd_flag; - u1Byte i, valid_cnt; - u8Byte start = 0, func_start = 0, func_end = 0; + s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/ + s32 value32, pwdb_A = 0, sval, noise, sum; + boolean pd_flag; + u8 valid_cnt; + u64 start = 0, func_start = 0, func_end = 0; - if (!(pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A))) + if (!(p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A))) return 0; - - func_start = ODM_GetCurrentTime(pDM_Odm); - pDM_Odm->noise_level.noise_all = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() ==>\n")); - - /* Step 1. Disable DIG && Set initial gain. */ - if (bPauseDIG) - odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue); - - /* Step 2. Disable all power save for read registers */ - /*dcmd_DebugControlPowerSave(pAdapter, PSDisable); */ - - /* Step 3. Get noise power level */ - start = ODM_GetCurrentTime(pDM_Odm); + + func_start = odm_get_current_time(p_dm_odm); + p_dm_odm->noise_level.noise_all = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_inband_noise_monitor_ac_series() ==>\n")); + + /* step 1. Disable DIG && Set initial gain. */ + if (is_pause_dig) + odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value); + + /* step 2. Disable all power save for read registers */ + /*dcmd_DebugControlPowerSave(p_adapter, PSDisable); */ + + /* step 3. Get noise power level */ + start = odm_get_current_time(p_dm_odm); /* reset counters */ sum = 0; valid_cnt = 0; - /* Step 3. Get noise power level */ + /* step 3. Get noise power level */ while (1) { /*Set IGI=0x1C */ - ODM_Write_DIG(pDM_Odm, 0x1C); + odm_write_dig(p_dm_odm, 0x1C); /*stop CK320&CK88 */ - ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 1); - /*Read Path-A */ - ODM_SetBBReg(pDM_Odm, 0x8FC, bMaskDWord, 0x200); /*set debug port*/ - value32 = ODM_GetBBReg(pDM_Odm, 0xFA0, bMaskDWord); /*read debug port*/ - + odm_set_bb_reg(p_dm_odm, 0x8B4, BIT(6), 1); + /*Read path-A */ + odm_set_bb_reg(p_dm_odm, 0x8FC, MASKDWORD, 0x200); /*set debug port*/ + value32 = odm_get_bb_reg(p_dm_odm, 0xFA0, MASKDWORD); /*read debug port*/ + rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/ rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/ - pd_flag = (BOOLEAN) ((value32 & BIT31) >> 31); + pd_flag = (boolean)((value32 & BIT(31)) >> 31); /*Not in packet detection period or Tx state */ if ((!pd_flag) || (rxi_buf_anta != 0x200)) { /*sign conversion*/ - rxi_buf_anta = ODM_SignConversion(rxi_buf_anta, 10); - rxq_buf_anta = ODM_SignConversion(rxq_buf_anta, 10); + rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10); + rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10); - pwdb_A = ODM_PWdB_Conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/ + pwdb_A = odm_pwdb_conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF)); } /*Start CK320&CK88*/ - ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 0); + odm_set_bb_reg(p_dm_odm, 0x8B4, BIT(6), 0); /*BB Reset*/ - ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) & (~BIT0)); - ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) | BIT0); + odm_write_1byte(p_dm_odm, 0x02, odm_read_1byte(p_dm_odm, 0x02) & (~BIT(0))); + odm_write_1byte(p_dm_odm, 0x02, odm_read_1byte(p_dm_odm, 0x02) | BIT(0)); /*PMAC Reset*/ - ODM_Write1Byte(pDM_Odm, 0xB03, ODM_Read1Byte(pDM_Odm, 0xB03) & (~BIT0)); - ODM_Write1Byte(pDM_Odm, 0xB03, ODM_Read1Byte(pDM_Odm, 0xB03) | BIT0); + odm_write_1byte(p_dm_odm, 0xB03, odm_read_1byte(p_dm_odm, 0xB03) & (~BIT(0))); + odm_write_1byte(p_dm_odm, 0xB03, odm_read_1byte(p_dm_odm, 0xB03) | BIT(0)); /*CCK Reset*/ - if (ODM_Read1Byte(pDM_Odm, 0x80B) & BIT4) { - ODM_Write1Byte(pDM_Odm, 0x80B, ODM_Read1Byte(pDM_Odm, 0x80B) & (~BIT4)); - ODM_Write1Byte(pDM_Odm, 0x80B, ODM_Read1Byte(pDM_Odm, 0x80B) | BIT4); + if (odm_read_1byte(p_dm_odm, 0x80B) & BIT(4)) { + odm_write_1byte(p_dm_odm, 0x80B, odm_read_1byte(p_dm_odm, 0x80B) & (~BIT(4))); + odm_write_1byte(p_dm_odm, 0x80B, odm_read_1byte(p_dm_odm, 0x80B) | BIT(4)); } sval = pwdb_A; - if (sval < 0 && sval >= -27) { - if (valid_cnt < ValidCnt) { - valid_cnt++; - sum += sval; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Valid sval = %d\n", sval)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", sum)); - if ((valid_cnt >= ValidCnt) || (ODM_GetProgressingTime(pDM_Odm, start) > max_time)) { - sum /= valid_cnt; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, sum = %d\n", sum)); - break; - } + if ((sval < 0 && sval >= -27) && (valid_cnt < VALID_CNT)){ + valid_cnt++; + sum += sval; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Valid sval = %d\n", sval)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", sum)); + if ((valid_cnt >= VALID_CNT) || (odm_get_progressing_time(p_dm_odm, start) > max_time)) { + sum /= VALID_CNT; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, sum = %d\n", sum)); + break; } } } - /*ADC backoff is 12dB,*/ + /*ADC backoff is 12dB,*/ /*Ptarget=0x1C-110=-82dBm*/ - noise = sum + 12 + 0x1C - 110; - + noise = sum + 12 + 0x1C - 110; + /*Offset*/ noise = noise - 3; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise = %d\n", noise)); - pDM_Odm->noise_level.noise_all = (s2Byte)noise; - - /* Step 4. Recover the Dig*/ - if (bPauseDIG) - odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue); - - func_end = ODM_GetProgressingTime(pDM_Odm, func_start); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() <==\n")); - - return pDM_Odm->noise_level.noise_all; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise = %d\n", noise)); + p_dm_odm->noise_level.noise_all = (s16)noise; + + /* step 4. Recover the Dig*/ + if (is_pause_dig) + odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value); + + func_end = odm_get_progressing_time(p_dm_odm, func_start); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_inband_noise_monitor_ac_series() <==\n")); + + return p_dm_odm->noise_level.noise_all; } -s2Byte -ODM_InbandNoise_Monitor(PVOID pDM_VOID, u8 bPauseDIG, u8 IGIValue, u32 max_time) +s16 +odm_inband_noise_monitor(void *p_dm_void, u8 is_pause_dig, u8 igi_value, u32 max_time) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - return odm_InbandNoise_Monitor_ACSeries(pDM_Odm, bPauseDIG, IGIValue, max_time); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + return odm_inband_noise_monitor_ac_series(p_dm_odm, is_pause_dig, igi_value, max_time); else - return odm_InbandNoise_Monitor_NSeries(pDM_Odm, bPauseDIG, IGIValue, max_time); + return odm_inband_noise_monitor_n_series(p_dm_odm, is_pause_dig, igi_value, max_time); } #endif - - diff --git a/hal/phydm/phydm_noisemonitor.h b/hal/phydm/phydm_noisemonitor.h index 022cefe..05b2e50 100644 --- a/hal/phydm/phydm_noisemonitor.h +++ b/hal/phydm/phydm_noisemonitor.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,39 +11,32 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * *****************************************************************************/ #ifndef __ODMNOISEMONITOR_H__ #define __ODMNOISEMONITOR_H__ -#define ODM_MAX_CHANNEL_NUM 38//14+24 -struct noise_level -{ - //u1Byte value_a, value_b; - u1Byte value[MAX_RF_PATH]; - //s1Byte sval_a, sval_b; - s1Byte sval[MAX_RF_PATH]; - - //s4Byte noise_a=0, noise_b=0,sum_a=0, sum_b=0; - //s4Byte noise[ODM_RF_PATH_MAX]; - s4Byte sum[MAX_RF_PATH]; - //u1Byte valid_cnt_a=0, valid_cnt_b=0, - u1Byte valid[MAX_RF_PATH]; - u1Byte valid_cnt[MAX_RF_PATH]; +#define ODM_MAX_CHANNEL_NUM 38/* 14+24 */ +struct noise_level { + /* u8 value_a, value_b; */ + u8 value[MAX_RF_PATH]; + /* s8 sval_a, sval_b; */ + s8 sval[MAX_RF_PATH]; + + /* s32 noise_a=0, noise_b=0,sum_a=0, sum_b=0; */ + /* s32 noise[ODM_RF_PATH_MAX]; */ + s32 sum[MAX_RF_PATH]; + /* u8 valid_cnt_a=0, valid_cnt_b=0, */ + u8 valid[MAX_RF_PATH]; + u8 valid_cnt[MAX_RF_PATH]; }; -typedef struct _ODM_NOISE_MONITOR_ -{ - s1Byte noise[MAX_RF_PATH]; - s2Byte noise_all; -}ODM_NOISE_MONITOR; +struct _ODM_NOISE_MONITOR_ { + s8 noise[MAX_RF_PATH]; + s16 noise_all; +}; -s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time); +s16 odm_inband_noise_monitor(void *p_dm_void, u8 is_pause_dig, u8 igi_value, u32 max_time); #endif diff --git a/hal/phydm/phydm_pathdiv.c b/hal/phydm/phydm_pathdiv.c index 96faddf..9a2ada6 100644 --- a/hal/phydm/phydm_pathdiv.c +++ b/hal/phydm/phydm_pathdiv.c @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,748 +11,627 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" -#if(defined(CONFIG_PATH_DIVERSITY)) +#if (defined(CONFIG_PATH_DIVERSITY)) #if RTL8814A_SUPPORT -VOID +void phydm_dtp_fix_tx_path( - IN PVOID pDM_VOID, - IN u1Byte path - ) + void *p_dm_void, + u8 path +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; - u1Byte i,num_enable_path=0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div; + u8 i, num_enable_path = 0; - if(path==pDM_PathDiv->pre_tx_path) - { + if (path == p_dm_path_div->pre_tx_path) return; - } else - { - pDM_PathDiv->pre_tx_path=path; - } + p_dm_path_div->pre_tx_path = path; - ODM_SetBBReg( pDM_Odm, 0x93c, BIT18|BIT19, 3); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(18) | BIT(19), 3); - for(i=0; i<4; i++) - { - if(path&BIT(i)) + for (i = 0; i < 4; i++) { + if (path & BIT(i)) num_enable_path++; } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Number of trun-on path : (( %d ))\n", num_enable_path)); - - if(num_enable_path == 1) - { - ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path); - - if(path==PHYDM_A)//1-1 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A ))\n")); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - } - else if(path==PHYDM_B)//1-2 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B ))\n")); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); - } - else if(path==PHYDM_C)//1-3 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C ))\n")); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 0); - - } - else if(path==PHYDM_D)//1-4 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( D ))\n")); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 0); - } - - } - else if(num_enable_path == 2) - { - ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path); - ODM_SetBBReg( pDM_Odm, 0x940, 0xf0, path); - - if(path==PHYDM_AB)//2-1 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1); - } - else if(path==PHYDM_AC)//2-2 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); - } - else if(path==PHYDM_AD)//2-3 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A D ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1); - } - else if(path==PHYDM_BC)//2-4 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); - } - else if(path==PHYDM_BD)//2-5 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B D ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1); - } - else if(path==PHYDM_CD)//2-6 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C D ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" number of trun-on path : (( %d ))\n", num_enable_path)); + + if (num_enable_path == 1) { + odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path); + + if (path == PHYDM_A) { /* 1-1 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A ))\n")); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); + } else if (path == PHYDM_B) { /* 1-2 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B ))\n")); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0); + } else if (path == PHYDM_C) { /* 1-3 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C ))\n")); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 0); + + } else if (path == PHYDM_D) { /* 1-4 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( D ))\n")); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 0); } - } - else if(num_enable_path == 3) - { - ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path); - ODM_SetBBReg( pDM_Odm, 0x940, 0xf0, path); - ODM_SetBBReg( pDM_Odm, 0x940, 0xf0000, path); - - if(path==PHYDM_ABC)//3-1 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B C))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 2); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 2); - //set for 3ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 2); + } else if (num_enable_path == 2) { + odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path); + odm_set_bb_reg(p_dm_odm, 0x940, 0xf0, path); + + if (path == PHYDM_AB) { /* 2-1 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B ))\n")); + /* set for 1ss */ + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1); + /* set for 2ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1); + } else if (path == PHYDM_AC) { /* 2-2 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C ))\n")); + /* set for 1ss */ + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1); + /* set for 2ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1); + } else if (path == PHYDM_AD) { /* 2-3 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A D ))\n")); + /* set for 1ss */ + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1); + /* set for 2ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1); + } else if (path == PHYDM_BC) { /* 2-4 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C ))\n")); + /* set for 1ss */ + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1); + /* set for 2ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1); + } else if (path == PHYDM_BD) { /* 2-5 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B D ))\n")); + /* set for 1ss */ + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1); + /* set for 2ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1); + } else if (path == PHYDM_CD) { /* 2-6 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C D ))\n")); + /* set for 1ss */ + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 0); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1); + /* set for 2ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1); } - else if(path==PHYDM_ABD)//3-2 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B D ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2); - //set for 3ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2); + } else if (num_enable_path == 3) { + odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path); + odm_set_bb_reg(p_dm_odm, 0x940, 0xf0, path); + odm_set_bb_reg(p_dm_odm, 0x940, 0xf0000, path); + + if (path == PHYDM_ABC) { /* 3-1 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B C))\n")); + /* set for 1ss */ + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 2); + /* set for 2ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 2); + /* set for 3ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 1); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 2); + } else if (path == PHYDM_ABD) { /* 3-2 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B D ))\n")); + /* set for 1ss */ + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2); + /* set for 2ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2); + /* set for 3ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 1); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2); + + } else if (path == PHYDM_ACD) { /* 3-3 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C D ))\n")); + /* set for 1ss */ + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2); + /* set for 2ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2); + /* set for 3ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 1); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2); + } else if (path == PHYDM_BCD) { /* 3-4 */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C D))\n")); + /* set for 1ss */ + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1); + odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2); + /* set for 2ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2); + /* set for 3ss */ + odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 0); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 1); + odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2); } - else if(path==PHYDM_ACD)//3-3 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C D ))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2); - //set for 3ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2); - } - else if(path==PHYDM_BCD)//3-4 - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C D))\n")); - //set for 1ss - ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); - ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2); - //set for 2ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2); - //set for 3ss - ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 0); - ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 1); - ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2); - } - } - else if(num_enable_path == 4) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path ((A B C D))\n")); - } + } else if (num_enable_path == 4) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path ((A B C D))\n")); } -VOID +void phydm_find_default_path( - IN PVOID pDM_VOID - ) + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; - u4Byte rssi_avg_a=0, rssi_avg_b=0, rssi_avg_c=0, rssi_avg_d=0, rssi_avg_bcd=0; - u4Byte rssi_total_a=0, rssi_total_b=0, rssi_total_c=0, rssi_total_d=0; - - //2 Default Path Selection By RSSI - - rssi_avg_a = (pDM_PathDiv->path_a_cnt_all > 0)? (pDM_PathDiv->path_a_sum_all / pDM_PathDiv->path_a_cnt_all) :0 ; - rssi_avg_b = (pDM_PathDiv->path_b_cnt_all > 0)? (pDM_PathDiv->path_b_sum_all / pDM_PathDiv->path_b_cnt_all) :0 ; - rssi_avg_c = (pDM_PathDiv->path_c_cnt_all > 0)? (pDM_PathDiv->path_c_sum_all / pDM_PathDiv->path_c_cnt_all) :0 ; - rssi_avg_d = (pDM_PathDiv->path_d_cnt_all > 0)? (pDM_PathDiv->path_d_sum_all / pDM_PathDiv->path_d_cnt_all) :0 ; - - - pDM_PathDiv->path_a_sum_all = 0; - pDM_PathDiv->path_a_cnt_all = 0; - pDM_PathDiv->path_b_sum_all = 0; - pDM_PathDiv->path_b_cnt_all = 0; - pDM_PathDiv->path_c_sum_all = 0; - pDM_PathDiv->path_c_cnt_all = 0; - pDM_PathDiv->path_d_sum_all = 0; - pDM_PathDiv->path_d_cnt_all = 0; - - if(pDM_PathDiv->use_path_a_as_default_ant == 1) - { - rssi_avg_bcd=(rssi_avg_b+rssi_avg_c+rssi_avg_d)/3; - - if( (rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd ) - { - pDM_PathDiv->is_pathA_exist=TRUE; - pDM_PathDiv->default_path=PATH_A; - } + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div; + u32 rssi_avg_a = 0, rssi_avg_b = 0, rssi_avg_c = 0, rssi_avg_d = 0, rssi_avg_bcd = 0; + u32 rssi_total_a = 0, rssi_total_b = 0, rssi_total_c = 0, rssi_total_d = 0; + + /* 2 Default path Selection By RSSI */ + + rssi_avg_a = (p_dm_path_div->path_a_cnt_all > 0) ? (p_dm_path_div->path_a_sum_all / p_dm_path_div->path_a_cnt_all) : 0 ; + rssi_avg_b = (p_dm_path_div->path_b_cnt_all > 0) ? (p_dm_path_div->path_b_sum_all / p_dm_path_div->path_b_cnt_all) : 0 ; + rssi_avg_c = (p_dm_path_div->path_c_cnt_all > 0) ? (p_dm_path_div->path_c_sum_all / p_dm_path_div->path_c_cnt_all) : 0 ; + rssi_avg_d = (p_dm_path_div->path_d_cnt_all > 0) ? (p_dm_path_div->path_d_sum_all / p_dm_path_div->path_d_cnt_all) : 0 ; + + + p_dm_path_div->path_a_sum_all = 0; + p_dm_path_div->path_a_cnt_all = 0; + p_dm_path_div->path_b_sum_all = 0; + p_dm_path_div->path_b_cnt_all = 0; + p_dm_path_div->path_c_sum_all = 0; + p_dm_path_div->path_c_cnt_all = 0; + p_dm_path_div->path_d_sum_all = 0; + p_dm_path_div->path_d_cnt_all = 0; + + if (p_dm_path_div->use_path_a_as_default_ant == 1) { + rssi_avg_bcd = (rssi_avg_b + rssi_avg_c + rssi_avg_d) / 3; + + if ((rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd) { + p_dm_path_div->is_path_a_exist = true; + p_dm_path_div->default_path = PATH_A; + } else + p_dm_path_div->is_path_a_exist = false; + } else { + if ((rssi_avg_a >= rssi_avg_b) && (rssi_avg_a >= rssi_avg_c) && (rssi_avg_a >= rssi_avg_d)) + p_dm_path_div->default_path = PATH_A; + else if ((rssi_avg_b >= rssi_avg_c) && (rssi_avg_b >= rssi_avg_d)) + p_dm_path_div->default_path = PATH_B; + else if (rssi_avg_c >= rssi_avg_d) + p_dm_path_div->default_path = PATH_C; else - { - pDM_PathDiv->is_pathA_exist=FALSE; - } - } - else - { - if( (rssi_avg_a >=rssi_avg_b) && (rssi_avg_a >=rssi_avg_c)&&(rssi_avg_a >=rssi_avg_d)) - pDM_PathDiv->default_path=PATH_A; - else if( (rssi_avg_b >=rssi_avg_c)&&(rssi_avg_b >=rssi_avg_d)) - pDM_PathDiv->default_path=PATH_B; - else if( rssi_avg_c >=rssi_avg_d) - pDM_PathDiv->default_path=PATH_C; - else - pDM_PathDiv->default_path=PATH_D; + p_dm_path_div->default_path = PATH_D; } } -VOID +void phydm_candidate_dtp_update( - IN PVOID pDM_VOID - ) + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; - - pDM_PathDiv->num_candidate=3; - - if(pDM_PathDiv->use_path_a_as_default_ant == 1) - { - if(pDM_PathDiv->num_tx_path==3) - { - if(pDM_PathDiv->is_pathA_exist) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; - pDM_PathDiv->ant_candidate_2 = PHYDM_ABD; - pDM_PathDiv->ant_candidate_3 = PHYDM_ACD; - } - else // use path BCD - { - pDM_PathDiv->num_candidate=1; - phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BCD); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div; + + p_dm_path_div->num_candidate = 3; + + if (p_dm_path_div->use_path_a_as_default_ant == 1) { + if (p_dm_path_div->num_tx_path == 3) { + if (p_dm_path_div->is_path_a_exist) { + p_dm_path_div->ant_candidate_1 = PHYDM_ABC; + p_dm_path_div->ant_candidate_2 = PHYDM_ABD; + p_dm_path_div->ant_candidate_3 = PHYDM_ACD; + } else { /* use path BCD */ + p_dm_path_div->num_candidate = 1; + phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BCD); return; } - } - else if(pDM_PathDiv->num_tx_path==2) - { - if(pDM_PathDiv->is_pathA_exist) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_AB; - pDM_PathDiv->ant_candidate_2 = PHYDM_AC; - pDM_PathDiv->ant_candidate_3 = PHYDM_AD; + } else if (p_dm_path_div->num_tx_path == 2) { + if (p_dm_path_div->is_path_a_exist) { + p_dm_path_div->ant_candidate_1 = PHYDM_AB; + p_dm_path_div->ant_candidate_2 = PHYDM_AC; + p_dm_path_div->ant_candidate_3 = PHYDM_AD; + } else { + p_dm_path_div->ant_candidate_1 = PHYDM_BC; + p_dm_path_div->ant_candidate_2 = PHYDM_BD; + p_dm_path_div->ant_candidate_3 = PHYDM_CD; } - else - { - pDM_PathDiv->ant_candidate_1 = PHYDM_BC; - pDM_PathDiv->ant_candidate_2 = PHYDM_BD; - pDM_PathDiv->ant_candidate_3 = PHYDM_CD; - } } - } - else - { - //2 3 TX Mode - if(pDM_PathDiv->num_tx_path==3)//choose 3 ant form 4 - { - if(pDM_PathDiv->default_path == PATH_A) //choose 2 ant form 3 - { - pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; - pDM_PathDiv->ant_candidate_2 = PHYDM_ABD; - pDM_PathDiv->ant_candidate_3 = PHYDM_ACD; - } - else if(pDM_PathDiv->default_path==PATH_B) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; - pDM_PathDiv->ant_candidate_2 = PHYDM_ABD; - pDM_PathDiv->ant_candidate_3 = PHYDM_BCD; - } - else if(pDM_PathDiv->default_path == PATH_C) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; - pDM_PathDiv->ant_candidate_2 = PHYDM_ACD; - pDM_PathDiv->ant_candidate_3 = PHYDM_BCD; - } - else if(pDM_PathDiv->default_path == PATH_D) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_ABD; - pDM_PathDiv->ant_candidate_2 = PHYDM_ACD; - pDM_PathDiv->ant_candidate_3 = PHYDM_BCD; + } else { + /* 2 3 TX mode */ + if (p_dm_path_div->num_tx_path == 3) { /* choose 3 ant form 4 */ + if (p_dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */ + p_dm_path_div->ant_candidate_1 = PHYDM_ABC; + p_dm_path_div->ant_candidate_2 = PHYDM_ABD; + p_dm_path_div->ant_candidate_3 = PHYDM_ACD; + } else if (p_dm_path_div->default_path == PATH_B) { + p_dm_path_div->ant_candidate_1 = PHYDM_ABC; + p_dm_path_div->ant_candidate_2 = PHYDM_ABD; + p_dm_path_div->ant_candidate_3 = PHYDM_BCD; + } else if (p_dm_path_div->default_path == PATH_C) { + p_dm_path_div->ant_candidate_1 = PHYDM_ABC; + p_dm_path_div->ant_candidate_2 = PHYDM_ACD; + p_dm_path_div->ant_candidate_3 = PHYDM_BCD; + } else if (p_dm_path_div->default_path == PATH_D) { + p_dm_path_div->ant_candidate_1 = PHYDM_ABD; + p_dm_path_div->ant_candidate_2 = PHYDM_ACD; + p_dm_path_div->ant_candidate_3 = PHYDM_BCD; } } - - //2 2 TX Mode - else if(pDM_PathDiv->num_tx_path==2)//choose 2 ant form 4 - { - if(pDM_PathDiv->default_path == PATH_A) //choose 2 ant form 3 - { - pDM_PathDiv->ant_candidate_1 = PHYDM_AB; - pDM_PathDiv->ant_candidate_2 = PHYDM_AC; - pDM_PathDiv->ant_candidate_3 = PHYDM_AD; - } - else if(pDM_PathDiv->default_path==PATH_B) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_AB; - pDM_PathDiv->ant_candidate_2 = PHYDM_BC; - pDM_PathDiv->ant_candidate_3 = PHYDM_BD; - } - else if(pDM_PathDiv->default_path == PATH_C) - { - pDM_PathDiv->ant_candidate_1 = PHYDM_AC; - pDM_PathDiv->ant_candidate_2 = PHYDM_BC; - pDM_PathDiv->ant_candidate_3 = PHYDM_CD; - } - else if(pDM_PathDiv->default_path == PATH_D) - { - pDM_PathDiv->ant_candidate_1= PHYDM_AD; - pDM_PathDiv->ant_candidate_2 = PHYDM_BD; - pDM_PathDiv->ant_candidate_3= PHYDM_CD; + + /* 2 2 TX mode */ + else if (p_dm_path_div->num_tx_path == 2) { /* choose 2 ant form 4 */ + if (p_dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */ + p_dm_path_div->ant_candidate_1 = PHYDM_AB; + p_dm_path_div->ant_candidate_2 = PHYDM_AC; + p_dm_path_div->ant_candidate_3 = PHYDM_AD; + } else if (p_dm_path_div->default_path == PATH_B) { + p_dm_path_div->ant_candidate_1 = PHYDM_AB; + p_dm_path_div->ant_candidate_2 = PHYDM_BC; + p_dm_path_div->ant_candidate_3 = PHYDM_BD; + } else if (p_dm_path_div->default_path == PATH_C) { + p_dm_path_div->ant_candidate_1 = PHYDM_AC; + p_dm_path_div->ant_candidate_2 = PHYDM_BC; + p_dm_path_div->ant_candidate_3 = PHYDM_CD; + } else if (p_dm_path_div->default_path == PATH_D) { + p_dm_path_div->ant_candidate_1 = PHYDM_AD; + p_dm_path_div->ant_candidate_2 = PHYDM_BD; + p_dm_path_div->ant_candidate_3 = PHYDM_CD; } } } } -VOID +void phydm_dynamic_tx_path( - IN PVOID pDM_VOID + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; - - PSTA_INFO_T pEntry; - u4Byte i; - u1Byte num_client=0; - u1Byte H2C_Parameter[6] ={0}; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div; + struct sta_info *p_entry; + u32 i; + u8 num_client = 0; + u8 h2c_parameter[6] = {0}; - if(!pDM_Odm->bLinked) //bLinked==False - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("DTP_8814 [No Link!!!]\n")); - - if(pDM_PathDiv->bBecomeLinked == TRUE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be disconnected]----->\n")); - pDM_PathDiv->bBecomeLinked = pDM_Odm->bLinked; + + if (!p_dm_odm->is_linked) { /* is_linked==False */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("DTP_8814 [No Link!!!]\n")); + + if (p_dm_path_div->is_become_linked == true) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be disconnected]----->\n")); + p_dm_path_div->is_become_linked = p_dm_odm->is_linked; } return; - } - else - { - if(pDM_PathDiv->bBecomeLinked ==FALSE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be Linked !!!]----->\n")); - pDM_PathDiv->bBecomeLinked = pDM_Odm->bLinked; - } - } - - //2 [Period CTRL] - if(pDM_PathDiv->dtp_period >=2) - { - pDM_PathDiv->dtp_period=0; + } else { + if (p_dm_path_div->is_become_linked == false) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be Linked !!!]----->\n")); + p_dm_path_div->is_become_linked = p_dm_odm->is_linked; + } } - else - { - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",pDM_PathDiv->dtp_period)); - pDM_PathDiv->dtp_period++; + + /* 2 [period CTRL] */ + if (p_dm_path_div->dtp_period >= 2) + p_dm_path_div->dtp_period = 0; + else { + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",p_dm_path_div->dtp_period)); */ + p_dm_path_div->dtp_period++; return; } - - //2 [Fix Path] - if (pDM_Odm->path_select != PHYDM_AUTO_PATH) - { + + /* 2 [Fix path] */ + if (p_dm_odm->path_select != PHYDM_AUTO_PATH) return; - } - - //2 [Check Bfer] - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if (BEAMFORMING_SUPPORT == 1) + + /* 2 [Check Bfer] */ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if (BEAMFORMING_SUPPORT == 1) { - BEAMFORMING_CAP BeamformCap = (pDM_Odm->BeamformingInfo.BeamformCap); - - if( BeamformCap & BEAMFORMER_CAP ) // BFmer On && Div On -> Div Off - { - if( pDM_PathDiv->fix_path_bfer == 0) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("[ PathDiv : OFF ] BFmer ==1 \n")); - pDM_PathDiv->fix_path_bfer = 1 ; + enum beamforming_cap beamform_cap = (p_dm_odm->beamforming_info.beamform_cap); + + if (beamform_cap & BEAMFORMER_CAP) { /* BFmer On && Div On->Div Off */ + if (p_dm_path_div->fix_path_bfer == 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[ PathDiv : OFF ] BFmer ==1\n")); + p_dm_path_div->fix_path_bfer = 1 ; } return; - } - else // BFmer Off && Div Off -> Div On - { - if( pDM_PathDiv->fix_path_bfer == 1 ) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("[ PathDiv : ON ] BFmer ==0 \n")); - pDM_PathDiv->fix_path_bfer = 0; + } else { /* BFmer Off && Div Off->Div On */ + if (p_dm_path_div->fix_path_bfer == 1) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[ PathDiv : ON ] BFmer ==0\n")); + p_dm_path_div->fix_path_bfer = 0; } } } - #endif - #endif +#endif +#endif - if(pDM_PathDiv->use_path_a_as_default_ant ==1) - { - phydm_find_default_path(pDM_Odm); - phydm_candidate_dtp_update(pDM_Odm); - } - else - { - if( pDM_PathDiv->dtp_state == PHYDM_DTP_INIT) - { - phydm_find_default_path(pDM_Odm); - phydm_candidate_dtp_update(pDM_Odm); - pDM_PathDiv->dtp_state = PHYDM_DTP_RUNNING_1; + if (p_dm_path_div->use_path_a_as_default_ant == 1) { + phydm_find_default_path(p_dm_odm); + phydm_candidate_dtp_update(p_dm_odm); + } else { + if (p_dm_path_div->phydm_dtp_state == PHYDM_DTP_INIT) { + phydm_find_default_path(p_dm_odm); + phydm_candidate_dtp_update(p_dm_odm); + p_dm_path_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1; } - - else if( pDM_PathDiv->dtp_state == PHYDM_DTP_RUNNING_1) - { - pDM_PathDiv->dtp_check_patha_counter++; - - if(pDM_PathDiv->dtp_check_patha_counter>=NUM_RESET_DTP_PERIOD) - { - pDM_PathDiv->dtp_check_patha_counter=0; - pDM_PathDiv->dtp_state = PHYDM_DTP_INIT; + + else if (p_dm_path_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) { + p_dm_path_div->dtp_check_patha_counter++; + + if (p_dm_path_div->dtp_check_patha_counter >= NUM_RESET_DTP_PERIOD) { + p_dm_path_div->dtp_check_patha_counter = 0; + p_dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT; } - //2 Search space update - else - { - // 1. find the worst candidate - + /* 2 Search space update */ + else { + /* 1. find the worst candidate */ + - // 2. repalce the worst candidate + /* 2. repalce the worst candidate */ } } } - //2 Dynamic Path Selection H2C + /* 2 Dynamic path Selection H2C */ - if(pDM_PathDiv->num_candidate == 1) - { + if (p_dm_path_div->num_candidate == 1) return; - } - else - { - H2C_Parameter[0] = pDM_PathDiv->num_candidate; - H2C_Parameter[1] = pDM_PathDiv->num_tx_path; - H2C_Parameter[2] = pDM_PathDiv->ant_candidate_1; - H2C_Parameter[3] = pDM_PathDiv->ant_candidate_2; - H2C_Parameter[4] = pDM_PathDiv->ant_candidate_3; - - ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, H2C_Parameter); + else { + h2c_parameter[0] = p_dm_path_div->num_candidate; + h2c_parameter[1] = p_dm_path_div->num_tx_path; + h2c_parameter[2] = p_dm_path_div->ant_candidate_1; + h2c_parameter[3] = p_dm_path_div->ant_candidate_2; + h2c_parameter[4] = p_dm_path_div->ant_candidate_3; + + odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter); } } -VOID +void phydm_dynamic_tx_path_init( - IN PVOID pDM_VOID - ) + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); - PADAPTER pAdapter = pDM_Odm->Adapter; - #if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT) - USB_MODE_MECH *pUsbModeMech = &pAdapter->UsbModeMechanism; - #endif - u1Byte search_space_2[NUM_CHOOSE2_FROM4]= {PHYDM_AB, PHYDM_AC, PHYDM_AD, PHYDM_BC, PHYDM_BD, PHYDM_CD }; - u1Byte search_space_3[NUM_CHOOSE3_FROM4]= {PHYDM_BCD, PHYDM_ACD, PHYDM_ABD, PHYDM_ABC}; - - #if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT) - pDM_PathDiv->is_u3_mode = (pUsbModeMech->CurUsbMode==USB_MODE_U3)? 1 : 0 ; - #else - pDM_PathDiv->is_u3_mode = 1; - #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Dynamic TX Path Init 8814\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("is_u3_mode = (( %d ))\n", pDM_PathDiv->is_u3_mode)); - - memcpy(&(pDM_PathDiv->search_space_2[0]), &(search_space_2[0]), NUM_CHOOSE2_FROM4); - memcpy(&(pDM_PathDiv->search_space_3[0]), &(search_space_3[0]), NUM_CHOOSE3_FROM4); - - pDM_PathDiv->use_path_a_as_default_ant= 1; - pDM_PathDiv->dtp_state = PHYDM_DTP_INIT; - pDM_Odm->path_select = PHYDM_AUTO_PATH; - pDM_PathDiv->path_div_type = PHYDM_4R_PATH_DIV; - - - if(pDM_PathDiv->is_u3_mode ) - { - pDM_PathDiv->num_tx_path=3; - phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BCD);/* 3TX Set Init TX Path*/ - - } - else - { - pDM_PathDiv->num_tx_path=2; - phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BC);/* 2TX // Set Init TX Path*/ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div); + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + u8 search_space_2[NUM_CHOOSE2_FROM4] = {PHYDM_AB, PHYDM_AC, PHYDM_AD, PHYDM_BC, PHYDM_BD, PHYDM_CD }; + u8 search_space_3[NUM_CHOOSE3_FROM4] = {PHYDM_BCD, PHYDM_ACD, PHYDM_ABD, PHYDM_ABC}; + +#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT) + p_dm_path_div->is_u3_mode = (*p_dm_odm->hub_usb_mode == 2) ? 1 : 0 ; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[WIN USB] is_u3_mode = (( %d ))\n", p_dm_path_div->is_u3_mode)); +#else + p_dm_path_div->is_u3_mode = 1; +#endif + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Dynamic TX path Init 8814\n")); + + memcpy(&(p_dm_path_div->search_space_2[0]), &(search_space_2[0]), NUM_CHOOSE2_FROM4); + memcpy(&(p_dm_path_div->search_space_3[0]), &(search_space_3[0]), NUM_CHOOSE3_FROM4); + + p_dm_path_div->use_path_a_as_default_ant = 1; + p_dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT; + p_dm_odm->path_select = PHYDM_AUTO_PATH; + p_dm_path_div->phydm_path_div_type = PHYDM_4R_PATH_DIV; + + + if (p_dm_path_div->is_u3_mode) { + p_dm_path_div->num_tx_path = 3; + phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BCD);/* 3TX Set Init TX path*/ + + } else { + p_dm_path_div->num_tx_path = 2; + phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BC);/* 2TX // Set Init TX path*/ } - + } -VOID -phydm_process_rssi_for_path_div( - IN OUT PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN PVOID p_pkt_info_void - ) +void +phydm_process_rssi_for_path_div( + void *p_dm_void, + void *p_phy_info_void, + void *p_pkt_info_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; - PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void; - pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; + struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; + struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div); + + if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_match_bssid) { + if (p_pktinfo->data_rate > ODM_RATE11M) { + if (p_dm_path_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) { +#if RTL8814A_SUPPORT + if (p_dm_odm->support_ic_type & ODM_RTL8814A) { + p_dm_path_div->path_a_sum_all += p_phy_info->rx_mimo_signal_strength[0]; + p_dm_path_div->path_a_cnt_all++; - if(pPktinfo->bPacketToSelf || pPktinfo->bPacketMatchBSSID) - { - if(pPktinfo->DataRate > ODM_RATE11M) - { - if(pDM_PathDiv->path_div_type == PHYDM_4R_PATH_DIV) - { - #if RTL8814A_SUPPORT - if(pDM_Odm->SupportICType & ODM_RTL8814A) - { - pDM_PathDiv->path_a_sum_all+=pPhyInfo->RxMIMOSignalStrength[0]; - pDM_PathDiv->path_a_cnt_all++; - - pDM_PathDiv->path_b_sum_all+=pPhyInfo->RxMIMOSignalStrength[1]; - pDM_PathDiv->path_b_cnt_all++; - - pDM_PathDiv->path_c_sum_all+=pPhyInfo->RxMIMOSignalStrength[2]; - pDM_PathDiv->path_c_cnt_all++; - - pDM_PathDiv->path_d_sum_all+=pPhyInfo->RxMIMOSignalStrength[3]; - pDM_PathDiv->path_d_cnt_all++; + p_dm_path_div->path_b_sum_all += p_phy_info->rx_mimo_signal_strength[1]; + p_dm_path_div->path_b_cnt_all++; + + p_dm_path_div->path_c_sum_all += p_phy_info->rx_mimo_signal_strength[2]; + p_dm_path_div->path_c_cnt_all++; + + p_dm_path_div->path_d_sum_all += p_phy_info->rx_mimo_signal_strength[3]; + p_dm_path_div->path_d_cnt_all++; } - #endif - } - else - { - pDM_PathDiv->PathA_Sum[pPktinfo->StationID]+=pPhyInfo->RxMIMOSignalStrength[0]; - pDM_PathDiv->PathA_Cnt[pPktinfo->StationID]++; +#endif + } else { + p_dm_path_div->path_a_sum[p_pktinfo->station_id] += p_phy_info->rx_mimo_signal_strength[0]; + p_dm_path_div->path_a_cnt[p_pktinfo->station_id]++; - pDM_PathDiv->PathB_Sum[pPktinfo->StationID]+=pPhyInfo->RxMIMOSignalStrength[1]; - pDM_PathDiv->PathB_Cnt[pPktinfo->StationID]++; + p_dm_path_div->path_b_sum[p_pktinfo->station_id] += p_phy_info->rx_mimo_signal_strength[1]; + p_dm_path_div->path_b_cnt[p_pktinfo->station_id]++; } } } - - + + } -#endif //#if RTL8814A_SUPPORT +#endif /* #if RTL8814A_SUPPORT */ -VOID +void odm_pathdiv_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ) + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); - u4Byte used = *_used; - u4Byte out_len = *_out_len; - - pDM_Odm->path_select = (dm_value[0] & 0xf); - PHYDM_SNPRINTF((output+used, out_len-used,"Path_select = (( 0x%x ))\n",pDM_Odm->path_select )); - - //2 [Fix Path] - if (pDM_Odm->path_select != PHYDM_AUTO_PATH) - { - PHYDM_SNPRINTF((output+used, out_len-used,"Trun on path [%s%s%s%s]\n", - ((pDM_Odm->path_select) & 0x1)?"A":"", - ((pDM_Odm->path_select) & 0x2)?"B":"", - ((pDM_Odm->path_select) & 0x4)?"C":"", - ((pDM_Odm->path_select) & 0x8)?"D":"" )); - - phydm_dtp_fix_tx_path( pDM_Odm, pDM_Odm->path_select ); - } - else - { - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n","Auto Path")); - } + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div); + u32 used = *_used; + u32 out_len = *_out_len; + + p_dm_odm->path_select = (dm_value[0] & 0xf); + PHYDM_SNPRINTF((output + used, out_len - used, "Path_select = (( 0x%x ))\n", p_dm_odm->path_select)); + + /* 2 [Fix path] */ + if (p_dm_odm->path_select != PHYDM_AUTO_PATH) { + PHYDM_SNPRINTF((output + used, out_len - used, "Trun on path [%s%s%s%s]\n", + ((p_dm_odm->path_select) & 0x1) ? "A" : "", + ((p_dm_odm->path_select) & 0x2) ? "B" : "", + ((p_dm_odm->path_select) & 0x4) ? "C" : "", + ((p_dm_odm->path_select) & 0x8) ? "D" : "")); + + phydm_dtp_fix_tx_path(p_dm_odm, p_dm_odm->path_select); + } else + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Auto path")); } -#endif // #if(defined(CONFIG_PATH_DIVERSITY)) +#endif /* #if(defined(CONFIG_PATH_DIVERSITY)) */ -VOID +void phydm_c2h_dtp_handler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len ) { -#if(defined(CONFIG_PATH_DIVERSITY)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); +#if (defined(CONFIG_PATH_DIVERSITY)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div); - u1Byte macid = CmdBuf[0]; - u1Byte target = CmdBuf[1]; - u1Byte nsc_1 = CmdBuf[2]; - u1Byte nsc_2 = CmdBuf[3]; - u1Byte nsc_3 = CmdBuf[4]; + u8 macid = cmd_buf[0]; + u8 target = cmd_buf[1]; + u8 nsc_1 = cmd_buf[2]; + u8 nsc_2 = cmd_buf[3]; + u8 nsc_3 = cmd_buf[4]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Target_candidate = (( %d ))\n", target)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Target_candidate = (( %d ))\n", target)); /* if( (nsc_1 >= nsc_2) && (nsc_1 >= nsc_3)) { - phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_1); + phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_1); } - else if( nsc_2 >= nsc_3) + else if( nsc_2 >= nsc_3) { - phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_2); + phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_2); } else { - phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_3); + phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_3); } */ -#endif +#endif } -VOID -odm_PathDiversity( - IN PVOID pDM_VOID +void +odm_path_diversity( + void *p_dm_void ) { -#if(defined(CONFIG_PATH_DIVERSITY)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n")); +#if (defined(CONFIG_PATH_DIVERSITY)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + if (!(p_dm_odm->support_ability & ODM_BB_PATH_DIV)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Return: Not Support PathDiv\n")); return; } - #if RTL8812A_SUPPORT +#if RTL8812A_SUPPORT - if(pDM_Odm->SupportICType & ODM_RTL8812) - ODM_PathDiversity_8812A(pDM_Odm); - else - #endif + if (p_dm_odm->support_ic_type & ODM_RTL8812) + odm_path_diversity_8812a(p_dm_odm); + else +#endif - #if RTL8814A_SUPPORT - if(pDM_Odm->SupportICType & ODM_RTL8814A) - phydm_dynamic_tx_path(pDM_Odm); +#if RTL8814A_SUPPORT + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + phydm_dynamic_tx_path(p_dm_odm); else - #endif - {} +#endif + {} #endif } -VOID -odm_PathDiversityInit( - IN PVOID pDM_VOID +void +odm_path_diversity_init( + void *p_dm_void ) { -#if(defined(CONFIG_PATH_DIVERSITY)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (defined(CONFIG_PATH_DIVERSITY)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - /*pDM_Odm->SupportAbility |= ODM_BB_PATH_DIV;*/ - - if(pDM_Odm->mp_mode == TRUE) + /*p_dm_odm->support_ability |= ODM_BB_PATH_DIV;*/ + + if (*(p_dm_odm->p_mp_mode) == true) return; - if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n")); + if (!(p_dm_odm->support_ability & ODM_BB_PATH_DIV)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Return: Not Support PathDiv\n")); return; } #if RTL8812A_SUPPORT - if(pDM_Odm->SupportICType & ODM_RTL8812) - ODM_PathDiversityInit_8812A(pDM_Odm); - else - #endif + if (p_dm_odm->support_ic_type & ODM_RTL8812) + odm_path_diversity_init_8812a(p_dm_odm); + else +#endif - #if RTL8814A_SUPPORT - if(pDM_Odm->SupportICType & ODM_RTL8814A) - phydm_dynamic_tx_path_init(pDM_Odm); +#if RTL8814A_SUPPORT + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + phydm_dynamic_tx_path_init(p_dm_odm); else - #endif +#endif {} #endif } @@ -760,51 +639,50 @@ odm_PathDiversityInit( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -// -// 2011/12/02 MH Copy from MP oursrc for temporarily test. -// +/* + * 2011/12/02 MH Copy from MP oursrc for temporarily test. + * */ -VOID -odm_PathDivChkAntSwitchCallback( - PRT_TIMER pTimer +void +odm_path_div_chk_ant_switch_callback( + struct timer_list *p_timer ) { } -VOID -odm_PathDivChkAntSwitchWorkitemCallback( - IN PVOID pContext - ) +void +odm_path_div_chk_ant_switch_workitem_callback( + void *p_context +) { } -VOID -odm_CCKTXPathDiversityCallback( - PRT_TIMER pTimer +void +odm_cck_tx_path_diversity_callback( + struct timer_list *p_timer ) { } -VOID -odm_CCKTXPathDiversityWorkItemCallback( - IN PVOID pContext - ) +void +odm_cck_tx_path_diversity_work_item_callback( + void *p_context +) { } -u1Byte -odm_SwAntDivSelectScanChnl( - IN PADAPTER Adapter - ) +u8 +odm_sw_ant_div_select_scan_chnl( + struct _ADAPTER *adapter +) { return 0; } -VOID -odm_SwAntDivConstructScanChnl( - IN PADAPTER Adapter, - IN u1Byte ScanChnl - ) +void +odm_sw_ant_div_construct_scan_chnl( + struct _ADAPTER *adapter, + u8 scan_chnl +) { } -#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - +#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ diff --git a/hal/phydm/phydm_pathdiv.h b/hal/phydm/phydm_pathdiv.h index 4ce4214..e12b56f 100644 --- a/hal/phydm/phydm_pathdiv.h +++ b/hal/phydm/phydm_pathdiv.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,23 +11,18 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - + *****************************************************************************/ + #ifndef __PHYDMPATHDIV_H__ #define __PHYDMPATHDIV_H__ /*#define PATHDIV_VERSION "2.0" //2014.11.04*/ #define PATHDIV_VERSION "3.1" /*2015.07.29 by YuChen*/ -#if(defined(CONFIG_PATH_DIVERSITY)) -#define USE_PATH_A_AS_DEFAULT_ANT //for 8814 dynamic TX path selection +#if (defined(CONFIG_PATH_DIVERSITY)) +#define USE_PATH_A_AS_DEFAULT_ANT /* for 8814 dynamic TX path selection */ #define NUM_RESET_DTP_PERIOD 5 -#define ANT_DECT_RSSI_TH 3 +#define ANT_DECT_RSSI_TH 3 #define PATH_A 1 #define PATH_B 2 @@ -41,284 +36,279 @@ #define NUM_CHOOSE3_FROM4 4 -#define PHYDM_A BIT0 -#define PHYDM_B BIT1 -#define PHYDM_C BIT2 -#define PHYDM_D BIT3 -#define PHYDM_AB (BIT0 | BIT1) // 0 -#define PHYDM_AC (BIT0 | BIT2) // 1 -#define PHYDM_AD (BIT0 | BIT3) // 2 -#define PHYDM_BC (BIT1 | BIT2) // 3 -#define PHYDM_BD (BIT1 | BIT3) // 4 -#define PHYDM_CD (BIT2 | BIT3) // 5 +#define PHYDM_A BIT(0) +#define PHYDM_B BIT(1) +#define PHYDM_C BIT(2) +#define PHYDM_D BIT(3) +#define PHYDM_AB (BIT(0) | BIT1) /* 0 */ +#define PHYDM_AC (BIT(0) | BIT2) /* 1 */ +#define PHYDM_AD (BIT(0) | BIT3) /* 2 */ +#define PHYDM_BC (BIT(1) | BIT2) /* 3 */ +#define PHYDM_BD (BIT(1) | BIT3) /* 4 */ +#define PHYDM_CD (BIT(2) | BIT3) /* 5 */ -#define PHYDM_ABC (BIT0 | BIT1 | BIT2) /* 0*/ -#define PHYDM_ABD (BIT0 | BIT1 | BIT3) /* 1*/ -#define PHYDM_ACD (BIT0 | BIT2 | BIT3) /* 2*/ -#define PHYDM_BCD (BIT1 | BIT2 | BIT3) /* 3*/ +#define PHYDM_ABC (BIT(0) | BIT1 | BIT2) /* 0*/ +#define PHYDM_ABD (BIT(0) | BIT1 | BIT3) /* 1*/ +#define PHYDM_ACD (BIT(0) | BIT2 | BIT3) /* 2*/ +#define PHYDM_BCD (BIT(1) | BIT2 | BIT3) /* 3*/ -#define PHYDM_ABCD (BIT0 | BIT1 | BIT2 | BIT3) +#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3)) -typedef enum dtp_state -{ - PHYDM_DTP_INIT=1, +enum phydm_dtp_state { + PHYDM_DTP_INIT = 1, PHYDM_DTP_RUNNING_1 -}PHYDM_DTP_STATE; +}; -typedef enum path_div_type -{ +enum phydm_path_div_type { PHYDM_2R_PATH_DIV = 1, PHYDM_4R_PATH_DIV = 2 -}PHYDM_PATH_DIV_TYPE; - -VOID -phydm_process_rssi_for_path_div( - IN OUT PVOID pDM_VOID, - IN PVOID p_phy_info_void, - IN PVOID p_pkt_info_void - ); - -typedef struct _ODM_PATH_DIVERSITY_ -{ - u1Byte RespTxPath; - u1Byte PathSel[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; - u4Byte PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; - u2Byte PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - u2Byte PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; - u1Byte path_div_type; - #if RTL8814A_SUPPORT - - u4Byte path_a_sum_all; - u4Byte path_b_sum_all; - u4Byte path_c_sum_all; - u4Byte path_d_sum_all; - - u4Byte path_a_cnt_all; - u4Byte path_b_cnt_all; - u4Byte path_c_cnt_all; - u4Byte path_d_cnt_all; - - u1Byte dtp_period; - BOOLEAN bBecomeLinked; - BOOLEAN is_u3_mode; - u1Byte num_tx_path; - u1Byte default_path; - u1Byte num_candidate; - u1Byte ant_candidate_1; - u1Byte ant_candidate_2; - u1Byte ant_candidate_3; - u1Byte dtp_state; - u1Byte dtp_check_patha_counter; - BOOLEAN fix_path_bfer; - u1Byte search_space_2[NUM_CHOOSE2_FROM4]; - u1Byte search_space_3[NUM_CHOOSE3_FROM4]; - - u1Byte pre_tx_path; - u1Byte use_path_a_as_default_ant; - BOOLEAN is_pathA_exist; - - #endif -}PATHDIV_T, *pPATHDIV_T; - - -#endif //#if(defined(CONFIG_PATH_DIVERSITY)) - -VOID +}; + +void +phydm_process_rssi_for_path_div( + void *p_dm_void, + void *p_phy_info_void, + void *p_pkt_info_void +); + +struct _ODM_PATH_DIVERSITY_ { + u8 resp_tx_path; + u8 path_sel[ODM_ASSOCIATE_ENTRY_NUM]; + u32 path_a_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u32 path_b_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u16 path_a_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u16 path_b_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u8 phydm_path_div_type; +#if RTL8814A_SUPPORT + + u32 path_a_sum_all; + u32 path_b_sum_all; + u32 path_c_sum_all; + u32 path_d_sum_all; + + u32 path_a_cnt_all; + u32 path_b_cnt_all; + u32 path_c_cnt_all; + u32 path_d_cnt_all; + + u8 dtp_period; + boolean is_become_linked; + boolean is_u3_mode; + u8 num_tx_path; + u8 default_path; + u8 num_candidate; + u8 ant_candidate_1; + u8 ant_candidate_2; + u8 ant_candidate_3; + u8 phydm_dtp_state; + u8 dtp_check_patha_counter; + boolean fix_path_bfer; + u8 search_space_2[NUM_CHOOSE2_FROM4]; + u8 search_space_3[NUM_CHOOSE3_FROM4]; + + u8 pre_tx_path; + u8 use_path_a_as_default_ant; + boolean is_path_a_exist; + +#endif +}; + + +#endif /* #if(defined(CONFIG_PATH_DIVERSITY)) */ + +void phydm_c2h_dtp_handler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen - ); - -VOID -odm_PathDiversityInit( - IN PVOID pDM_VOID - ); - -VOID -odm_PathDiversity( - IN PVOID pDM_VOID - ); - -VOID + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len +); + +void +odm_path_diversity_init( + void *p_dm_void +); + +void +odm_path_diversity( + void *p_dm_void +); + +void odm_pathdiv_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len - ); - + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); -//1 [OLD IC]-------------------------------------------------------------------------------- +/* 1 [OLD IC]-------------------------------------------------------------------------------- */ -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) -//#define PATHDIV_ENABLE 1 -#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi -#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +/* #define PATHDIV_ENABLE 1 */ +#define dm_path_div_rssi_check odm_path_div_chk_per_pkt_rssi +#define path_div_check_before_link8192c odm_path_diversity_before_link92c -typedef struct _PathDiv_Parameter_define_ -{ - u4Byte org_5g_RegE30; - u4Byte org_5g_RegC14; - u4Byte org_5g_RegCA0; - u4Byte swt_5g_RegE30; - u4Byte swt_5g_RegC14; - u4Byte swt_5g_RegCA0; - //for 2G IQK information - u4Byte org_2g_RegC80; - u4Byte org_2g_RegC4C; - u4Byte org_2g_RegC94; - u4Byte org_2g_RegC14; - u4Byte org_2g_RegCA0; - - u4Byte swt_2g_RegC80; - u4Byte swt_2g_RegC4C; - u4Byte swt_2g_RegC94; - u4Byte swt_2g_RegC14; - u4Byte swt_2g_RegCA0; -}PATHDIV_PARA,*pPATHDIV_PARA; - -VOID -odm_PathDiversityInit_92C( - IN PADAPTER Adapter - ); - -VOID -odm_2TPathDiversityInit_92C( - IN PADAPTER Adapter - ); - -VOID -odm_1TPathDiversityInit_92C( - IN PADAPTER Adapter - ); - -BOOLEAN -odm_IsConnected_92C( - IN PADAPTER Adapter - ); - -BOOLEAN -ODM_PathDiversityBeforeLink92C( - //IN PADAPTER Adapter - IN PDM_ODM_T pDM_Odm - ); - -VOID -odm_PathDiversityAfterLink_92C( - IN PADAPTER Adapter - ); - -VOID -odm_SetRespPath_92C( - IN PADAPTER Adapter, - IN u1Byte DefaultRespPath - ); - -VOID -odm_OFDMTXPathDiversity_92C( - IN PADAPTER Adapter - ); - -VOID -odm_CCKTXPathDiversity_92C( - IN PADAPTER Adapter - ); - -VOID -odm_ResetPathDiversity_92C( - IN PADAPTER Adapter - ); - -VOID -odm_CCKTXPathDiversityCallback( - PRT_TIMER pTimer - ); - -VOID -odm_CCKTXPathDiversityWorkItemCallback( - IN PVOID pContext - ); - -VOID -odm_PathDivChkAntSwitchCallback( - PRT_TIMER pTimer - ); - -VOID -odm_PathDivChkAntSwitchWorkitemCallback( - IN PVOID pContext - ); - - -VOID -odm_PathDivChkAntSwitch( - PDM_ODM_T pDM_Odm - ); - -VOID -ODM_CCKPathDiversityChkPerPktRssi( - PADAPTER Adapter, - BOOLEAN bIsDefPort, - BOOLEAN bMatchBSSID, - PRT_WLAN_STA pEntry, - PRT_RFD pRfd, - pu1Byte pDesc - ); - -VOID -ODM_PathDivChkPerPktRssi( - PADAPTER Adapter, - BOOLEAN bIsDefPort, - BOOLEAN bMatchBSSID, - PRT_WLAN_STA pEntry, - PRT_RFD pRfd - ); - -VOID -ODM_PathDivRestAfterLink( - IN PDM_ODM_T pDM_Odm - ); - -VOID -ODM_FillTXPathInTXDESC( - IN PADAPTER Adapter, - IN PRT_TCB pTcb, - IN pu1Byte pDesc - ); - -VOID -odm_PathDivInit_92D( - IN PDM_ODM_T pDM_Odm - ); - -u1Byte -odm_SwAntDivSelectScanChnl( - IN PADAPTER Adapter - ); - -VOID -odm_SwAntDivConstructScanChnl( - IN PADAPTER Adapter, - IN u1Byte ScanChnl - ); - - #endif //#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - - - #endif //#ifndef __ODMPATHDIV_H__ +struct _path_div_parameter_define_ { + u32 org_5g_rege30; + u32 org_5g_regc14; + u32 org_5g_regca0; + u32 swt_5g_rege30; + u32 swt_5g_regc14; + u32 swt_5g_regca0; + /* for 2G IQK information */ + u32 org_2g_regc80; + u32 org_2g_regc4c; + u32 org_2g_regc94; + u32 org_2g_regc14; + u32 org_2g_regca0; + + u32 swt_2g_regc80; + u32 swt_2g_regc4c; + u32 swt_2g_regc94; + u32 swt_2g_regc14; + u32 swt_2g_regca0; +}; + +void +odm_path_diversity_init_92c( + struct _ADAPTER *adapter +); + +void +odm_2t_path_diversity_init_92c( + struct _ADAPTER *adapter +); + +void +odm_1t_path_diversity_init_92c( + struct _ADAPTER *adapter +); + +boolean +odm_is_connected_92c( + struct _ADAPTER *adapter +); + +boolean +odm_path_diversity_before_link92c( + /* struct _ADAPTER* adapter */ + struct PHY_DM_STRUCT *p_dm_odm +); + +void +odm_path_diversity_after_link_92c( + struct _ADAPTER *adapter +); + +void +odm_set_resp_path_92c( + struct _ADAPTER *adapter, + u8 default_resp_path +); + +void +odm_ofdm_tx_path_diversity_92c( + struct _ADAPTER *adapter +); + +void +odm_cck_tx_path_diversity_92c( + struct _ADAPTER *adapter +); + +void +odm_reset_path_diversity_92c( + struct _ADAPTER *adapter +); + +void +odm_cck_tx_path_diversity_callback( + struct timer_list *p_timer +); + +void +odm_cck_tx_path_diversity_work_item_callback( + void *p_context +); + +void +odm_path_div_chk_ant_switch_callback( + struct timer_list *p_timer +); + +void +odm_path_div_chk_ant_switch_workitem_callback( + void *p_context +); + + +void +odm_path_div_chk_ant_switch( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +odm_cck_path_diversity_chk_per_pkt_rssi( + struct _ADAPTER *adapter, + boolean is_def_port, + boolean is_match_bssid, + struct _WLAN_STA *p_entry, + PRT_RFD p_rfd, + u8 *p_desc +); + +void +odm_path_div_chk_per_pkt_rssi( + struct _ADAPTER *adapter, + boolean is_def_port, + boolean is_match_bssid, + struct _WLAN_STA *p_entry, + PRT_RFD p_rfd +); + +void +odm_path_div_rest_after_link( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +odm_fill_tx_path_in_txdesc( + struct _ADAPTER *adapter, + PRT_TCB p_tcb, + u8 *p_desc +); + +void +odm_path_div_init_92d( + struct PHY_DM_STRUCT *p_dm_odm +); + +u8 +odm_sw_ant_div_select_scan_chnl( + struct _ADAPTER *adapter +); + +void +odm_sw_ant_div_construct_scan_chnl( + struct _ADAPTER *adapter, + u8 scan_chnl +); + +#endif /* #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) */ + + +#endif /* #ifndef __ODMPATHDIV_H__ */ diff --git a/hal/phydm/phydm_pre_define.h b/hal/phydm/phydm_pre_define.h index 2092314..95a8708 100644 --- a/hal/phydm/phydm_pre_define.h +++ b/hal/phydm/phydm_pre_define.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,25 +11,20 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PHYDMPREDEFINE_H__ #define __PHYDMPREDEFINE_H__ -//1 ============================================================ -//1 Definition -//1 ============================================================ +/* 1 ============================================================ + * 1 Definition + * 1 ============================================================ */ -#define PHYDM_CODE_BASE "PHYDM_008" -#define PHYDM_RELEASE_DATE "20160518" +#define PHYDM_CODE_BASE "PHYDM_v017" +#define PHYDM_RELEASE_DATE "20170306" -//Max path of IC +/* Max path of IC */ #define MAX_PATH_NUM_8188E 1 #define MAX_PATH_NUM_8192E 2 #define MAX_PATH_NUM_8723B 1 @@ -42,31 +37,38 @@ #define MAX_PATH_NUM_8188F 1 #define MAX_PATH_NUM_8723D 1 #define MAX_PATH_NUM_8197F 2 +#define MAX_PATH_NUM_8821C 1 +/* JJ ADD 20161014 */ +#define MAX_PATH_NUM_8710B 1 -//Max RF path +/* Max RF path */ #define ODM_RF_PATH_MAX 2 #define ODM_RF_PATH_MAX_JAGUAR 4 /*Bit define path*/ -#define PHYDM_A BIT0 -#define PHYDM_B BIT1 -#define PHYDM_C BIT2 -#define PHYDM_D BIT3 -#define PHYDM_AB (BIT0 | BIT1) -#define PHYDM_AC (BIT0 | BIT2) -#define PHYDM_AD (BIT0 | BIT3) -#define PHYDM_BC (BIT1 | BIT2) -#define PHYDM_BD (BIT1 | BIT3) -#define PHYDM_CD (BIT2 | BIT3) -#define PHYDM_ABC (BIT0 | BIT1 | BIT2) -#define PHYDM_ABD (BIT0 | BIT1 | BIT3) -#define PHYDM_ACD (BIT0 | BIT2 | BIT3) -#define PHYDM_BCD (BIT1 | BIT2 | BIT3) -#define PHYDM_ABCD (BIT0 | BIT1 | BIT2 | BIT3) - -//number of entry -#if(DM_ODM_SUPPORT_TYPE & (ODM_CE)) - #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of AsocEntry[].*/ +#define PHYDM_A BIT(0) +#define PHYDM_B BIT(1) +#define PHYDM_C BIT(2) +#define PHYDM_D BIT(3) +#define PHYDM_AB (BIT(0) | BIT(1)) +#define PHYDM_AC (BIT(0) | BIT(2)) +#define PHYDM_AD (BIT(0) | BIT(3)) +#define PHYDM_BC (BIT(1) | BIT(2)) +#define PHYDM_BD (BIT(1) | BIT(3)) +#define PHYDM_CD (BIT(2) | BIT(3)) +#define PHYDM_ABC (BIT(0) | BIT(1) | BIT(2)) +#define PHYDM_ABD (BIT(0) | BIT(1) | BIT(3)) +#define PHYDM_ACD (BIT(0) | BIT(2) | BIT(3)) +#define PHYDM_BCD (BIT(1) | BIT(2) | BIT(3)) +#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +/* number of entry */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + #ifdef DM_ODM_CE_MAC80211 + /* defined in wifi.h (32+1) */ + #else + #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of asoc_entry[].*/ + #endif #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM #elif(DM_ODM_SUPPORT_TYPE & (ODM_AP)) #define ASSOCIATE_ENTRY_NUM NUM_STAT @@ -75,59 +77,100 @@ #define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1) #endif +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + #define RX_SMOOTH_FACTOR 20 +#endif + /* -----MGN rate--------------------------------- */ -#define ODM_MGN_1M 0x02 -#define ODM_MGN_2M 0x04 -#define ODM_MGN_5_5M 0x0b -#define ODM_MGN_11M 0x16 - -#define ODM_MGN_6M 0x0c -#define ODM_MGN_9M 0x12 -#define ODM_MGN_12M 0x18 -#define ODM_MGN_18M 0x24 -#define ODM_MGN_24M 0x30 -#define ODM_MGN_36M 0x48 -#define ODM_MGN_48M 0x60 -#define ODM_MGN_54M 0x6c - -/*TxHT = 1*/ -#define ODM_MGN_MCS0 0x80 -#define ODM_MGN_MCS1 0x81 -#define ODM_MGN_MCS2 0x82 -#define ODM_MGN_MCS3 0x83 -#define ODM_MGN_MCS4 0x84 -#define ODM_MGN_MCS5 0x85 -#define ODM_MGN_MCS6 0x86 -#define ODM_MGN_MCS7 0x87 -#define ODM_MGN_MCS8 0x88 -#define ODM_MGN_MCS9 0x89 -#define ODM_MGN_MCS10 0x8a -#define ODM_MGN_MCS11 0x8b -#define ODM_MGN_MCS12 0x8c -#define ODM_MGN_MCS13 0x8d -#define ODM_MGN_MCS14 0x8e -#define ODM_MGN_MCS15 0x8f -#define ODM_MGN_VHT1SS_MCS0 0x90 -#define ODM_MGN_VHT1SS_MCS1 0x91 -#define ODM_MGN_VHT1SS_MCS2 0x92 -#define ODM_MGN_VHT1SS_MCS3 0x93 -#define ODM_MGN_VHT1SS_MCS4 0x94 -#define ODM_MGN_VHT1SS_MCS5 0x95 -#define ODM_MGN_VHT1SS_MCS6 0x96 -#define ODM_MGN_VHT1SS_MCS7 0x97 -#define ODM_MGN_VHT1SS_MCS8 0x98 -#define ODM_MGN_VHT1SS_MCS9 0x99 -#define ODM_MGN_VHT2SS_MCS0 0x9a -#define ODM_MGN_VHT2SS_MCS1 0x9b -#define ODM_MGN_VHT2SS_MCS2 0x9c -#define ODM_MGN_VHT2SS_MCS3 0x9d -#define ODM_MGN_VHT2SS_MCS4 0x9e -#define ODM_MGN_VHT2SS_MCS5 0x9f -#define ODM_MGN_VHT2SS_MCS6 0xa0 -#define ODM_MGN_VHT2SS_MCS7 0xa1 -#define ODM_MGN_VHT2SS_MCS8 0xa2 -#define ODM_MGN_VHT2SS_MCS9 0xa3 +enum ODM_MGN_RATE { + ODM_MGN_1M = 0x02, + ODM_MGN_2M = 0x04, + ODM_MGN_5_5M = 0x0B, + ODM_MGN_6M = 0x0C, + ODM_MGN_9M = 0x12, + ODM_MGN_11M = 0x16, + ODM_MGN_12M = 0x18, + ODM_MGN_18M = 0x24, + ODM_MGN_24M = 0x30, + ODM_MGN_36M = 0x48, + ODM_MGN_48M = 0x60, + ODM_MGN_54M = 0x6C, + ODM_MGN_MCS32 = 0x7F, + ODM_MGN_MCS0, + ODM_MGN_MCS1, + ODM_MGN_MCS2, + ODM_MGN_MCS3, + ODM_MGN_MCS4, + ODM_MGN_MCS5, + ODM_MGN_MCS6, + ODM_MGN_MCS7, + ODM_MGN_MCS8, + ODM_MGN_MCS9, + ODM_MGN_MCS10, + ODM_MGN_MCS11, + ODM_MGN_MCS12, + ODM_MGN_MCS13, + ODM_MGN_MCS14, + ODM_MGN_MCS15, + ODM_MGN_MCS16, + ODM_MGN_MCS17, + ODM_MGN_MCS18, + ODM_MGN_MCS19, + ODM_MGN_MCS20, + ODM_MGN_MCS21, + ODM_MGN_MCS22, + ODM_MGN_MCS23, + ODM_MGN_MCS24, + ODM_MGN_MCS25, + ODM_MGN_MCS26, + ODM_MGN_MCS27, + ODM_MGN_MCS28, + ODM_MGN_MCS29, + ODM_MGN_MCS30, + ODM_MGN_MCS31, + ODM_MGN_VHT1SS_MCS0, + ODM_MGN_VHT1SS_MCS1, + ODM_MGN_VHT1SS_MCS2, + ODM_MGN_VHT1SS_MCS3, + ODM_MGN_VHT1SS_MCS4, + ODM_MGN_VHT1SS_MCS5, + ODM_MGN_VHT1SS_MCS6, + ODM_MGN_VHT1SS_MCS7, + ODM_MGN_VHT1SS_MCS8, + ODM_MGN_VHT1SS_MCS9, + ODM_MGN_VHT2SS_MCS0, + ODM_MGN_VHT2SS_MCS1, + ODM_MGN_VHT2SS_MCS2, + ODM_MGN_VHT2SS_MCS3, + ODM_MGN_VHT2SS_MCS4, + ODM_MGN_VHT2SS_MCS5, + ODM_MGN_VHT2SS_MCS6, + ODM_MGN_VHT2SS_MCS7, + ODM_MGN_VHT2SS_MCS8, + ODM_MGN_VHT2SS_MCS9, + ODM_MGN_VHT3SS_MCS0, + ODM_MGN_VHT3SS_MCS1, + ODM_MGN_VHT3SS_MCS2, + ODM_MGN_VHT3SS_MCS3, + ODM_MGN_VHT3SS_MCS4, + ODM_MGN_VHT3SS_MCS5, + ODM_MGN_VHT3SS_MCS6, + ODM_MGN_VHT3SS_MCS7, + ODM_MGN_VHT3SS_MCS8, + ODM_MGN_VHT3SS_MCS9, + ODM_MGN_VHT4SS_MCS0, + ODM_MGN_VHT4SS_MCS1, + ODM_MGN_VHT4SS_MCS2, + ODM_MGN_VHT4SS_MCS3, + ODM_MGN_VHT4SS_MCS4, + ODM_MGN_VHT4SS_MCS5, + ODM_MGN_VHT4SS_MCS6, + ODM_MGN_VHT4SS_MCS7, + ODM_MGN_VHT4SS_MCS8, + ODM_MGN_VHT4SS_MCS9, + ODM_MGN_UNKNOWN +}; #define ODM_MGN_MCS0_SG 0xc0 #define ODM_MGN_MCS1_SG 0xc1 @@ -152,21 +195,21 @@ #define ODM_RATEMCS32 0x20 -// CCK Rates, TxHT = 0 +/* CCK Rates, TxHT = 0 */ #define ODM_RATE1M 0x00 #define ODM_RATE2M 0x01 #define ODM_RATE5_5M 0x02 -#define ODM_RATE11M 0x03 -// OFDM Rates, TxHT = 0 +#define ODM_RATE11M 0x03 +/* OFDM Rates, TxHT = 0 */ #define ODM_RATE6M 0x04 #define ODM_RATE9M 0x05 -#define ODM_RATE12M 0x06 -#define ODM_RATE18M 0x07 -#define ODM_RATE24M 0x08 -#define ODM_RATE36M 0x09 -#define ODM_RATE48M 0x0A -#define ODM_RATE54M 0x0B -// MCS Rates, TxHT = 1 +#define ODM_RATE12M 0x06 +#define ODM_RATE18M 0x07 +#define ODM_RATE24M 0x08 +#define ODM_RATE36M 0x09 +#define ODM_RATE48M 0x0A +#define ODM_RATE54M 0x0B +/* MCS Rates, TxHT = 1 */ #define ODM_RATEMCS0 0x0C #define ODM_RATEMCS1 0x0D #define ODM_RATEMCS2 0x0E @@ -245,13 +288,13 @@ #else #if (RTL8192E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) #define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1) - #elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) + #elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) #define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1) - #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) + #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1) #elif (RTL8812A_SUPPORT == 1) #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1) - #elif(RTL8814A_SUPPORT == 1) + #elif (RTL8814A_SUPPORT == 1) #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1) #else #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) @@ -259,154 +302,170 @@ #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#define CONFIG_SFW_SUPPORTED + #define CONFIG_SFW_SUPPORTED #endif -//1 ============================================================ -//1 enumeration -//1 ============================================================ - - -// ODM_CMNINFO_INTERFACE -typedef enum tag_ODM_Support_Interface_Definition -{ - ODM_ITRF_PCIE = 0x1, - ODM_ITRF_USB = 0x2, - ODM_ITRF_SDIO = 0x4, - ODM_ITRF_ALL = 0x7, -}ODM_INTERFACE_E; - -// ODM_CMNINFO_IC_TYPE -typedef enum tag_ODM_Support_IC_Type_Definition -{ - ODM_RTL8188E = BIT0, - ODM_RTL8812 = BIT1, - ODM_RTL8821 = BIT2, - ODM_RTL8192E = BIT3, - ODM_RTL8723B = BIT4, - ODM_RTL8814A = BIT5, - ODM_RTL8881A = BIT6, - ODM_RTL8822B = BIT7, - ODM_RTL8703B = BIT8, - ODM_RTL8195A = BIT9, - ODM_RTL8188F = BIT10, - ODM_RTL8723D = BIT11, - ODM_RTL8197F = BIT12, - ODM_RTL8821C = BIT13, -}ODM_IC_TYPE_E; - - -#define ODM_IC_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | ODM_RTL8195A) -#define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B) +/* 1 ============================================================ + * 1 enumeration + * 1 ============================================================ */ + + +/* ODM_CMNINFO_INTERFACE */ +enum odm_interface_e { + ODM_ITRF_PCIE = 0x1, + ODM_ITRF_USB = 0x2, + ODM_ITRF_SDIO = 0x4, + ODM_ITRF_ALL = 0x7, +}; + +/* ODM_CMNINFO_IC_TYPE */ +enum odm_ic_type_e { + ODM_RTL8188E = BIT(0), + ODM_RTL8812 = BIT(1), + ODM_RTL8821 = BIT(2), + ODM_RTL8192E = BIT(3), + ODM_RTL8723B = BIT(4), + ODM_RTL8814A = BIT(5), + ODM_RTL8881A = BIT(6), + ODM_RTL8822B = BIT(7), + ODM_RTL8703B = BIT(8), + ODM_RTL8195A = BIT(9), + ODM_RTL8188F = BIT(10), + ODM_RTL8723D = BIT(11), + ODM_RTL8197F = BIT(12), + ODM_RTL8821C = BIT(13), + ODM_RTL8814B = BIT(14), + ODM_RTL8198F = BIT(15), + ODM_RTL8710B = BIT(16), + ODM_RTL8192F = BIT(17), + ODM_RTL8822C = BIT(18) +}; + +/*========[Run time ic flag] ===============================================================================]*/ + +#define ODM_IC_N_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F) +#define ODM_IC_AC_2SS (ODM_RTL8812 | ODM_RTL8822B | ODM_RTL8822C) + +#define ODM_IC_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | ODM_RTL8195A | ODM_RTL8710B) +#define ODM_IC_2SS (ODM_IC_N_2SS | ODM_IC_AC_2SS) #define ODM_IC_3SS (ODM_RTL8814A) +#define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F) +#define ODM_IC_11N_SERIES (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B) +#define ODM_IC_11AC_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8821C) -#define ODM_IC_11N_SERIES (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8197F) -#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B|ODM_RTL8821C) -#define ODM_IC_11AC_1_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8881A) -#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8821C) -#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C) -#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A|ODM_RTL8703B|ODM_RTL8188F|ODM_RTL8723D|ODM_RTL8197F) -#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8821C) -#define ODM_IC_PHY_STATUE_NEW_TYPE (ODM_RTL8197F|ODM_RTL8822B|ODM_RTL8723D|ODM_RTL8821C) +#define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A) +#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C) -#define PHYDM_IC_8051_SERIES (ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F) -#define PHYDM_IC_3081_SERIES (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C) +#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) +#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B) +#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C) +#define ODM_IC_PHY_STATUE_NEW_TYPE (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B) -#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8197F|ODM_RTL8821C) +#define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F) +#define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) +#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) +#define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B) +#define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B) + + +/*========[AC/N Support] ===============================================================================]*/ #if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#ifdef RTK_AC_SUPPORT -#define ODM_IC_11AC_SERIES_SUPPORT 1 -#else -#define ODM_IC_11AC_SERIES_SUPPORT 0 -#endif + #ifdef RTK_AC_SUPPORT + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #else + #define ODM_IC_11AC_SERIES_SUPPORT 0 + #endif -#define ODM_IC_11N_SERIES_SUPPORT 1 -#define ODM_CONFIG_BT_COEXIST 0 + #define ODM_IC_11N_SERIES_SUPPORT 1 + #define ODM_CONFIG_BT_COEXIST 0 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#define ODM_IC_11AC_SERIES_SUPPORT 1 -#define ODM_IC_11N_SERIES_SUPPORT 1 -#define ODM_CONFIG_BT_COEXIST 1 + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #define ODM_IC_11N_SERIES_SUPPORT 1 + #define ODM_CONFIG_BT_COEXIST 1 -#else +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) -#if ((RTL8188E_SUPPORT == 1) || \ -(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \ -(RTL8188F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) -#define ODM_IC_11N_SERIES_SUPPORT 1 -#define ODM_IC_11AC_SERIES_SUPPORT 0 -#else -#define ODM_IC_11N_SERIES_SUPPORT 0 -#define ODM_IC_11AC_SERIES_SUPPORT 1 -#endif + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #define ODM_IC_11N_SERIES_SUPPORT 1 + #define ODM_CONFIG_BT_COEXIST 1 -#ifdef CONFIG_BT_COEXIST -#define ODM_CONFIG_BT_COEXIST 1 #else -#define ODM_CONFIG_BT_COEXIST 0 -#endif -#endif + #if ((RTL8188E_SUPPORT == 1) || \ + (RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \ + (RTL8188F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8710B_SUPPORT == 1)) + #define ODM_IC_11N_SERIES_SUPPORT 1 + #define ODM_IC_11AC_SERIES_SUPPORT 0 + #else + #define ODM_IC_11N_SERIES_SUPPORT 0 + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #endif + + #ifdef CONFIG_BT_COEXIST + #define ODM_CONFIG_BT_COEXIST 1 + #else + #define ODM_CONFIG_BT_COEXIST 0 + #endif -#if ((RTL8814A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) -#define PHYDM_LA_MODE_SUPPORT 1 -#else -#define PHYDM_LA_MODE_SUPPORT 0 #endif -#if ((RTL8197F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) -#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1 + +/*========[New Phy-Status Support] =========================================================================]*/ + +#if ((RTL8197F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8710B_SUPPORT == 1) ) + #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1 #else -#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0 + #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0 #endif -//ODM_CMNINFO_CUT_VER -typedef enum tag_ODM_Cut_Version_Definition -{ - ODM_CUT_A = 0, - ODM_CUT_B = 1, - ODM_CUT_C = 2, - ODM_CUT_D = 3, - ODM_CUT_E = 4, - ODM_CUT_F = 5, - - ODM_CUT_I = 8, - ODM_CUT_J = 9, - ODM_CUT_K = 10, - ODM_CUT_TEST = 15, -}ODM_CUT_VERSION_E; - -// ODM_CMNINFO_FAB_VER -typedef enum tag_ODM_Fab_Version_Definition -{ - ODM_TSMC = 0, - ODM_UMC = 1, -}ODM_FAB_E; - -// ODM_CMNINFO_RF_TYPE -// -// For example 1T2R (A+AB = BIT0|BIT4|BIT5) -// -typedef enum tag_ODM_RF_Path_Bit_Definition -{ - ODM_RF_A = BIT0, - ODM_RF_B = BIT1, - ODM_RF_C = BIT2, - ODM_RF_D = BIT3, -}ODM_RF_PATH_E; - -typedef enum tag_PHYDM_RF_TX_NUM { +/*==================================================================================================]*/ + + +/* ODM_CMNINFO_CUT_VER */ +enum odm_cut_version_e { + ODM_CUT_A = 0, + ODM_CUT_B = 1, + ODM_CUT_C = 2, + ODM_CUT_D = 3, + ODM_CUT_E = 4, + ODM_CUT_F = 5, + + ODM_CUT_I = 8, + ODM_CUT_J = 9, + ODM_CUT_K = 10, + ODM_CUT_TEST = 15, +}; + +/* ODM_CMNINFO_FAB_VER */ +enum odm_fab_e { + ODM_TSMC = 0, + ODM_UMC = 1, +}; + +/* ODM_CMNINFO_RF_TYPE + * + * For example 1T2R (A+AB = BIT(0)|BIT(4)|BIT(5)) + * */ +enum odm_rf_path_e { + ODM_RF_A = BIT(0), + ODM_RF_B = BIT(1), + ODM_RF_C = BIT(2), + ODM_RF_D = BIT(3), +}; + +enum odm_rf_tx_num_e { ODM_1T = 1, ODM_2T = 2, ODM_3T = 3, ODM_4T = 4, -} ODM_RF_TX_NUM_E; +}; -typedef enum tag_ODM_RF_Type_Definition { +enum odm_rf_type_e { ODM_1T1R, ODM_1T2R, ODM_2T2R, @@ -417,143 +476,133 @@ typedef enum tag_ODM_RF_Type_Definition { ODM_3T4R, ODM_4T4R, ODM_XTXR -}ODM_RF_TYPE_E; +}; -typedef enum tag_ODM_MAC_PHY_Mode_Definition -{ +enum odm_mac_phy_mode_e { ODM_SMSP = 0, ODM_DMSP = 1, ODM_DMDP = 2, -}ODM_MAC_PHY_MODE_E; - - -typedef enum tag_BT_Coexist_Definition -{ - ODM_BT_BUSY = 1, - ODM_BT_ON = 2, - ODM_BT_OFF = 3, - ODM_BT_NONE = 4, -}ODM_BT_COEXIST_E; - -// ODM_CMNINFO_OP_MODE -typedef enum tag_Operation_Mode_Definition -{ - ODM_NO_LINK = BIT0, - ODM_LINK = BIT1, - ODM_SCAN = BIT2, - ODM_POWERSAVE = BIT3, - ODM_AP_MODE = BIT4, - ODM_CLIENT_MODE = BIT5, - ODM_AD_HOC = BIT6, - ODM_WIFI_DIRECT = BIT7, - ODM_WIFI_DISPLAY = BIT8, -}ODM_OPERATION_MODE_E; - -// ODM_CMNINFO_WM_MODE +}; + + +enum odm_bt_coexist_e { + ODM_BT_BUSY = 1, + ODM_BT_ON = 2, + ODM_BT_OFF = 3, + ODM_BT_NONE = 4, +}; + +/* ODM_CMNINFO_OP_MODE */ +enum odm_operation_mode_e { + ODM_NO_LINK = BIT(0), + ODM_LINK = BIT(1), + ODM_SCAN = BIT(2), + ODM_POWERSAVE = BIT(3), + ODM_AP_MODE = BIT(4), + ODM_CLIENT_MODE = BIT(5), + ODM_AD_HOC = BIT(6), + ODM_WIFI_DIRECT = BIT(7), + ODM_WIFI_DISPLAY = BIT(8), +}; + +/* ODM_CMNINFO_WM_MODE */ #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -typedef enum tag_Wireless_Mode_Definition -{ +enum odm_wireless_mode_e { ODM_WM_UNKNOW = 0x0, - ODM_WM_B = BIT0, - ODM_WM_G = BIT1, - ODM_WM_A = BIT2, - ODM_WM_N24G = BIT3, - ODM_WM_N5G = BIT4, - ODM_WM_AUTO = BIT5, - ODM_WM_AC = BIT6, -}ODM_WIRELESS_MODE_E; + ODM_WM_B = BIT(0), + ODM_WM_G = BIT(1), + ODM_WM_A = BIT(2), + ODM_WM_N24G = BIT(3), + ODM_WM_N5G = BIT(4), + ODM_WM_AUTO = BIT(5), + ODM_WM_AC = BIT(6), +}; #else -typedef enum tag_Wireless_Mode_Definition -{ +enum odm_wireless_mode_e { ODM_WM_UNKNOWN = 0x00,/*0x0*/ - ODM_WM_A = BIT0, /* 0x1*/ - ODM_WM_B = BIT1, /* 0x2*/ - ODM_WM_G = BIT2,/* 0x4*/ - ODM_WM_AUTO = BIT3,/* 0x8*/ - ODM_WM_N24G = BIT4,/* 0x10*/ - ODM_WM_N5G = BIT5,/* 0x20*/ - ODM_WM_AC_5G = BIT6,/* 0x40*/ - ODM_WM_AC_24G = BIT7,/* 0x80*/ - ODM_WM_AC_ONLY = BIT8,/* 0x100*/ - ODM_WM_MAX = BIT11/* 0x800*/ - -}ODM_WIRELESS_MODE_E; + ODM_WM_A = BIT(0), /* 0x1*/ + ODM_WM_B = BIT(1), /* 0x2*/ + ODM_WM_G = BIT(2),/* 0x4*/ + ODM_WM_AUTO = BIT(3),/* 0x8*/ + ODM_WM_N24G = BIT(4),/* 0x10*/ + ODM_WM_N5G = BIT(5),/* 0x20*/ + ODM_WM_AC_5G = BIT(6),/* 0x40*/ + ODM_WM_AC_24G = BIT(7),/* 0x80*/ + ODM_WM_AC_ONLY = BIT(8),/* 0x100*/ + ODM_WM_MAX = BIT(11)/* 0x800*/ + +}; #endif -// ODM_CMNINFO_BAND -typedef enum tag_Band_Type_Definition -{ +/* ODM_CMNINFO_BAND */ +enum odm_band_type_e { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - ODM_BAND_2_4G = BIT0, - ODM_BAND_5G = BIT1, + ODM_BAND_2_4G = BIT(0), + ODM_BAND_5G = BIT(1), #else ODM_BAND_2_4G = 0, ODM_BAND_5G, ODM_BAND_ON_BOTH, ODM_BANDMAX #endif -}ODM_BAND_TYPE_E; +}; -// ODM_CMNINFO_SEC_CHNL_OFFSET -typedef enum tag_Secondary_Channel_Offset_Definition { +/* ODM_CMNINFO_SEC_CHNL_OFFSET */ +enum phydm_sec_chnl_offset_e { PHYDM_DONT_CARE = 0, PHYDM_BELOW = 1, PHYDM_ABOVE = 2 -} PHYDM_SEC_CHNL_OFFSET_E; - -// ODM_CMNINFO_SEC_MODE -typedef enum tag_Security_Definition -{ - ODM_SEC_OPEN = 0, - ODM_SEC_WEP40 = 1, - ODM_SEC_TKIP = 2, - ODM_SEC_RESERVE = 3, - ODM_SEC_AESCCMP = 4, - ODM_SEC_WEP104 = 5, - ODM_WEP_WPA_MIXED = 6, // WEP + WPA - ODM_SEC_SMS4 = 7, -}ODM_SECURITY_E; - -// ODM_CMNINFO_BW -typedef enum tag_Bandwidth_Definition -{ - ODM_BW20M = 0, - ODM_BW40M = 1, - ODM_BW80M = 2, - ODM_BW160M = 3, +}; + +/* ODM_CMNINFO_SEC_MODE */ +enum odm_security_e { + ODM_SEC_OPEN = 0, + ODM_SEC_WEP40 = 1, + ODM_SEC_TKIP = 2, + ODM_SEC_RESERVE = 3, + ODM_SEC_AESCCMP = 4, + ODM_SEC_WEP104 = 5, + ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ + ODM_SEC_SMS4 = 7, +}; + +/* ODM_CMNINFO_BW */ +enum odm_bw_e { + ODM_BW20M = 0, + ODM_BW40M = 1, + ODM_BW80M = 2, + ODM_BW160M = 3, ODM_BW5M = 4, ODM_BW10M = 5, ODM_BW_MAX = 6 -}ODM_BW_E; - -// ODM_CMNINFO_CHNL - -// ODM_CMNINFO_BOARD_TYPE -typedef enum tag_Board_Definition -{ - ODM_BOARD_DEFAULT = 0, // The DEFAULT case. - ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card. - ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card - ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT - ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA - ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA - ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW - ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA - ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA -}ODM_BOARD_TYPE_E; - -typedef enum tag_ODM_Package_Definition -{ - ODM_PACKAGE_DEFAULT = 0, - ODM_PACKAGE_QFN68 = BIT(0), - ODM_PACKAGE_TFBGA90 = BIT(1), - ODM_PACKAGE_TFBGA79 = BIT(2), -}ODM_Package_TYPE_E; - -typedef enum tag_ODM_TYPE_GPA_Definition { +}; + +/* ODM_CMNINFO_CHNL */ + +/* ODM_CMNINFO_BOARD_TYPE */ +enum odm_board_type_e { + ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ + ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */ + ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */ + ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */ + ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */ + ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ + ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */ + ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */ + ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ +}; + +enum odm_package_type_e { + ODM_PACKAGE_DEFAULT = 0, + ODM_PACKAGE_QFN68 = BIT(0), + ODM_PACKAGE_TFBGA90 = BIT(1), + ODM_PACKAGE_TFBGA79 = BIT(2), +}; + +enum odm_type_gpa_e { TYPE_GPA0 = 0x0000, TYPE_GPA1 = 0x0055, TYPE_GPA2 = 0x00AA, @@ -570,9 +619,9 @@ typedef enum tag_ODM_TYPE_GPA_Definition { TYPE_GPA13 = 0xFF55, TYPE_GPA14 = 0xFFAA, TYPE_GPA15 = 0xFFFF, -}ODM_TYPE_GPA_E; +}; -typedef enum tag_ODM_TYPE_APA_Definition { +enum odm_type_apa_e { TYPE_APA0 = 0x0000, TYPE_APA1 = 0x0055, TYPE_APA2 = 0x00AA, @@ -589,9 +638,9 @@ typedef enum tag_ODM_TYPE_APA_Definition { TYPE_APA13 = 0xFF55, TYPE_APA14 = 0xFFAA, TYPE_APA15 = 0xFFFF, -}ODM_TYPE_APA_E; +}; -typedef enum tag_ODM_TYPE_GLNA_Definition { +enum odm_type_glna_e { TYPE_GLNA0 = 0x0000, TYPE_GLNA1 = 0x0055, TYPE_GLNA2 = 0x00AA, @@ -608,9 +657,9 @@ typedef enum tag_ODM_TYPE_GLNA_Definition { TYPE_GLNA13 = 0xFF55, TYPE_GLNA14 = 0xFFAA, TYPE_GLNA15 = 0xFFFF, -}ODM_TYPE_GLNA_E; +}; -typedef enum tag_ODM_TYPE_ALNA_Definition { +enum odm_type_alna_e { TYPE_ALNA0 = 0x0000, TYPE_ALNA1 = 0x0055, TYPE_ALNA2 = 0x00AA, @@ -627,30 +676,31 @@ typedef enum tag_ODM_TYPE_ALNA_Definition { TYPE_ALNA13 = 0xFF55, TYPE_ALNA14 = 0xFFAA, TYPE_ALNA15 = 0xFFFF, -}ODM_TYPE_ALNA_E; - - -typedef enum _ODM_RF_RADIO_PATH { - ODM_RF_PATH_A = 0, //Radio Path A - ODM_RF_PATH_B = 1, //Radio Path B - ODM_RF_PATH_C = 2, //Radio Path C - ODM_RF_PATH_D = 3, //Radio Path D - ODM_RF_PATH_AB, - ODM_RF_PATH_AC, - ODM_RF_PATH_AD, - ODM_RF_PATH_BC, - ODM_RF_PATH_BD, - ODM_RF_PATH_CD, - ODM_RF_PATH_ABC, - ODM_RF_PATH_ACD, - ODM_RF_PATH_BCD, - ODM_RF_PATH_ABCD, - // ODM_RF_PATH_MAX, //Max RF number 90 support -} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E; - -typedef enum _ODM_PARAMETER_INIT { +}; + + +enum odm_rf_radio_path_e { + ODM_RF_PATH_A = 0, /* Radio path A */ + ODM_RF_PATH_B = 1, /* Radio path B */ + ODM_RF_PATH_C = 2, /* Radio path C */ + ODM_RF_PATH_D = 3, /* Radio path D */ + ODM_RF_PATH_AB, + ODM_RF_PATH_AC, + ODM_RF_PATH_AD, + ODM_RF_PATH_BC, + ODM_RF_PATH_BD, + ODM_RF_PATH_CD, + ODM_RF_PATH_ABC, + ODM_RF_PATH_ACD, + ODM_RF_PATH_BCD, + ODM_RF_PATH_ABCD, + /* ODM_RF_PATH_MAX, */ /* Max RF number 90 support */ +}; + +enum odm_parameter_init_e { ODM_PRE_SETTING = 0, ODM_POST_SETTING = 1, -} ODM_PARAMETER_INIT_E; + ODM_INIT_FW_SETTING +}; #endif diff --git a/hal/phydm/phydm_precomp.h b/hal/phydm/phydm_precomp.h index 2942692..a2b8a90 100644 --- a/hal/phydm/phydm_precomp.h +++ b/hal/phydm/phydm_precomp.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,25 +11,22 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __ODM_PRECOMP_H__ #define __ODM_PRECOMP_H__ #include "phydm_types.h" +#include "phydm_features.h" +#include "halrf/halrf_features.h" #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting. + #include "Precomp.h" /* We need to include mp_precomp.h due to batch file setting. */ #else -#define TEST_FALG___ 1 + #define TEST_FALG___ 1 #endif -//2 Config Flags and Structs - defined by each ODM Type +/* 2 Config Flags and Structs - defined by each ODM type */ #if (DM_ODM_SUPPORT_TYPE == ODM_AP) #include "../8192cd_cfg.h" @@ -38,17 +35,19 @@ #include "../8192cd.h" #include "../8192cd_util.h" #ifdef _BIG_ENDIAN_ - #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG #else - #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE #endif - #ifdef AP_BUILD_WORKAROUND #include "../8192cd_headers.h" - #include "../8192cd_debug.h" - #endif + #include "../8192cd_debug.h" -#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef DM_ODM_CE_MAC80211 + #include "../wifi.h" + #include "rtl_phydm.h" + #endif #define __PACK #define __WLAN_ATTRIB_PACK__ #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) @@ -58,291 +57,347 @@ #define __WLAN_ATTRIB_PACK__ #endif -//2 OutSrc Header Files - -#include "phydm.h" +/* 2 OutSrc Header Files */ + +#include "phydm.h" #include "phydm_hwconfig.h" #include "phydm_debug.h" #include "phydm_regdefine11ac.h" #include "phydm_regdefine11n.h" #include "phydm_interface.h" #include "phydm_reg.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#include "phydm_adc_sampling.h" -#endif +#include "phydm_adc_sampling.h" -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) -VOID -PHY_SetTxPowerLimit( - IN PDM_ODM_T pDM_Odm, - IN u8 *Regulation, - IN u8 *Band, - IN u8 *Bandwidth, - IN u8 *RateSection, - IN u8 *RfPath, - IN u8 *Channel, - IN u8 *PowerLimit +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && !defined(DM_ODM_CE_MAC80211) + +void +phy_set_tx_power_limit( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *regulation, + u8 *band, + u8 *bandwidth, + u8 *rate_section, + u8 *rf_path, + u8 *channel, + u8 *power_limit ); - #endif #if (DM_ODM_SUPPORT_TYPE & ODM_AP) -#define RTL8703B_SUPPORT 0 -#define RTL8188F_SUPPORT 0 -#define RTL8723D_SUPPORT 0 + #define RTL8703B_SUPPORT 0 + #define RTL8188F_SUPPORT 0 + #define RTL8723D_SUPPORT 0 #endif -#if RTL8188E_SUPPORT == 1 -#define RTL8188E_T_SUPPORT 1 -#ifdef CONFIG_SFW_SUPPORTED -#define RTL8188E_S_SUPPORT 1 -#else -#define RTL8188E_S_SUPPORT 0 -#endif +/* JJ ADD 20161014 */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP|ODM_IOT)) +#define RTL8710B_SUPPORT 0 #endif -#if (RTL8188E_SUPPORT==1) -#include "rtl8188e/hal8188erateadaptive.h"//for RA,Power training -#include "rtl8188e/halhwimg8188e_mac.h" -#include "rtl8188e/halhwimg8188e_rf.h" -#include "rtl8188e/halhwimg8188e_bb.h" -#include "rtl8188e/halhwimg8188e_t_fw.h" -#include "rtl8188e/halhwimg8188e_s_fw.h" -#include "rtl8188e/phydm_regconfig8188e.h" -#include "rtl8188e/phydm_rtl8188e.h" -#include "rtl8188e/hal8188ereg.h" -#include "rtl8188e/version_rtl8188e.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8188e_hal.h" - #include "rtl8188e/halphyrf_8188e_ce.h" -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8188e/halphyrf_8188e_win.h" -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "rtl8188e/halphyrf_8188e_ap.h" +#if RTL8188E_SUPPORT == 1 + #define RTL8188E_T_SUPPORT 1 + #ifdef CONFIG_SFW_SUPPORTED + #define RTL8188E_S_SUPPORT 1 + #else + #define RTL8188E_S_SUPPORT 0 + #endif #endif -#endif //88E END -#if (RTL8192E_SUPPORT==1) +#if (RTL8188E_SUPPORT == 1) + #include "rtl8188e/hal8188erateadaptive.h" /* for RA,Power training */ + #include "rtl8188e/halhwimg8188e_mac.h" + #include "rtl8188e/halhwimg8188e_rf.h" + #include "rtl8188e/halhwimg8188e_bb.h" + #include "rtl8188e/halhwimg8188e_t_fw.h" + #include "rtl8188e/halhwimg8188e_s_fw.h" + #include "rtl8188e/phydm_regconfig8188e.h" + #include "rtl8188e/phydm_rtl8188e.h" + #include "rtl8188e/hal8188ereg.h" + #include "rtl8188e/version_rtl8188e.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8188e_hal.h" + #include "halrf/rtl8188e/halrf_8188e_ce.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8188e/halrf_8188e_win.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "halrf/rtl8188e/halrf_8188e_ap.h" + #endif +#endif /* 88E END */ + +#if (RTL8192E_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8192e/halphyrf_8192e_win.h" /*FOR_8192E_IQK*/ + #include "halrf/rtl8192e/halrf_8192e_win.h" /*FOR_8192E_IQK*/ #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "rtl8192e/halphyrf_8192e_ap.h" /*FOR_8192E_IQK*/ + #include "halrf/rtl8192e/halrf_8192e_ap.h" /*FOR_8192E_IQK*/ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8192e/halphyrf_8192e_ce.h" /*FOR_8192E_IQK*/ + #include "halrf/rtl8192e/halrf_8192e_ce.h" /*FOR_8192E_IQK*/ + #endif + + #include "rtl8192e/phydm_rtl8192e.h" /* FOR_8192E_IQK */ + #include "rtl8192e/version_rtl8192e.h" + #if (DM_ODM_SUPPORT_TYPE != ODM_AP) + #include "rtl8192e/halhwimg8192e_bb.h" + #include "rtl8192e/halhwimg8192e_mac.h" + #include "rtl8192e/halhwimg8192e_rf.h" + #include "rtl8192e/phydm_regconfig8192e.h" + #include "rtl8192e/halhwimg8192e_fw.h" + #include "rtl8192e/hal8192ereg.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8192e_hal.h" + #endif +#endif /* 92E END */ + +#if (RTL8812A_SUPPORT == 1) + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8812a/halrf_8812a_win.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "halrf/rtl8812a/halrf_8812a_ap.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "halrf/rtl8812a/halrf_8812a_ce.h" + #endif + + /* #include "halrf/rtl8812a/halrf_8812a.h" */ /* FOR_8812_IQK */ + #if (DM_ODM_SUPPORT_TYPE != ODM_AP) + #include "rtl8812a/halhwimg8812a_bb.h" + #include "rtl8812a/halhwimg8812a_mac.h" + #include "rtl8812a/halhwimg8812a_rf.h" + #include "rtl8812a/phydm_regconfig8812a.h" + #include "rtl8812a/halhwimg8812a_fw.h" + #include "rtl8812a/phydm_rtl8812a.h" + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8812a_hal.h" #endif - -#include "rtl8192e/phydm_rtl8192e.h" //FOR_8192E_IQK -#include "rtl8192e/version_rtl8192e.h" -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - #include "rtl8192e/halhwimg8192e_bb.h" - #include "rtl8192e/halhwimg8192e_mac.h" - #include "rtl8192e/halhwimg8192e_rf.h" - #include "rtl8192e/phydm_regconfig8192e.h" - #include "rtl8192e/halhwimg8192e_fw.h" - #include "rtl8192e/hal8192ereg.h" -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8192e_hal.h" -#endif -#endif //92E END - -#if (RTL8812A_SUPPORT==1) - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8812a/halphyrf_8812a_win.h" - #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "rtl8812a/halphyrf_8812a_ap.h" - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8812a/halphyrf_8812a_ce.h" - #endif - - //#include "rtl8812a/HalPhyRf_8812A.h" //FOR_8812_IQK - #if (DM_ODM_SUPPORT_TYPE != ODM_AP) - #include "rtl8812a/halhwimg8812a_bb.h" - #include "rtl8812a/halhwimg8812a_mac.h" - #include "rtl8812a/halhwimg8812a_rf.h" - #include "rtl8812a/phydm_regconfig8812a.h" - #include "rtl8812a/halhwimg8812a_fw.h" - #include "rtl8812a/phydm_rtl8812a.h" - #endif - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8812a_hal.h" - #endif #include "rtl8812a/version_rtl8812a.h" -#endif //8812 END +#endif /* 8812 END */ -#if (RTL8814A_SUPPORT==1) +#if (RTL8814A_SUPPORT == 1) -#include "rtl8814a/halhwimg8814a_mac.h" -#include "rtl8814a/halhwimg8814a_rf.h" -#include "rtl8814a/halhwimg8814a_bb.h" -#include "rtl8814a/version_rtl8814a.h" -#include "rtl8814a/phydm_rtl8814a.h" -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - #include "rtl8814a/halhwimg8814a_fw.h" -#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8814a/halphyrf_8814a_win.h" -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8814a/halphyrf_8814a_ce.h" -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "rtl8814a/halphyrf_8814a_ap.h" -#endif + #include "rtl8814a/halhwimg8814a_mac.h" + #include "rtl8814a/halhwimg8814a_rf.h" + #include "rtl8814a/halhwimg8814a_bb.h" + #include "rtl8814a/version_rtl8814a.h" + #include "rtl8814a/phydm_rtl8814a.h" + #if (DM_ODM_SUPPORT_TYPE != ODM_AP) + #include "rtl8814a/halhwimg8814a_fw.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8814a/halrf_8814a_win.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "halrf/rtl8814a/halrf_8814a_ce.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "halrf/rtl8814a/halrf_8814a_ap.h" + #endif #include "rtl8814a/phydm_regconfig8814a.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8814a_hal.h" - #include "rtl8814a/phydm_iqk_8814a.h" -#endif -#endif //8814 END + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8814a_hal.h" + #include "halrf/rtl8814a/halrf_iqk_8814a.h" + #endif +#endif /* 8814 END */ -#if (RTL8881A_SUPPORT==1)//FOR_8881_IQK -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#include "rtl8821a/phydm_iqk_8821a_win.h" -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -#include "rtl8821a/phydm_iqk_8821a_ce.h" -#else -#include "rtl8821a/phydm_iqk_8821a_ap.h" -#endif -//#include "rtl8881a/HalHWImg8881A_BB.h" -//#include "rtl8881a/HalHWImg8881A_MAC.h" -//#include "rtl8881a/HalHWImg8881A_RF.h" -//#include "rtl8881a/odm_RegConfig8881A.h" +#if (RTL8881A_SUPPORT == 1)/* FOR_8881_IQK */ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8821a/halrf_iqk_8821a_win.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "halrf/rtl8821a/halrf_iqk_8821a_ce.h" + #else + #include "halrf/rtl8821a/halrf_iqk_8821a_ap.h" + #endif + /* #include "rtl8881a/HalHWImg8881A_BB.h" */ + /* #include "rtl8881a/HalHWImg8881A_MAC.h" */ + /* #include "rtl8881a/HalHWImg8881A_RF.h" */ + /* #include "rtl8881a/odm_RegConfig8881A.h" */ #endif -#if (RTL8723B_SUPPORT==1) -#include "rtl8723b/halhwimg8723b_mac.h" -#include "rtl8723b/halhwimg8723b_rf.h" -#include "rtl8723b/halhwimg8723b_bb.h" -#include "rtl8723b/halhwimg8723b_fw.h" -#include "rtl8723b/phydm_regconfig8723b.h" -#include "rtl8723b/phydm_rtl8723b.h" -#include "rtl8723b/hal8723breg.h" -#include "rtl8723b/version_rtl8723b.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8723b/halphyrf_8723b_win.h" -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8723b/halphyrf_8723b_ce.h" - #include "rtl8723b/halhwimg8723b_mp.h" - #include "rtl8723b_hal.h" -#else - #include "rtl8723b/halphyrf_8723b_ap.h" -#endif +#if (RTL8723B_SUPPORT == 1) + #include "rtl8723b/halhwimg8723b_mac.h" + #include "rtl8723b/halhwimg8723b_rf.h" + #include "rtl8723b/halhwimg8723b_bb.h" + #include "rtl8723b/halhwimg8723b_fw.h" + #include "rtl8723b/phydm_regconfig8723b.h" + #include "rtl8723b/phydm_rtl8723b.h" + #include "rtl8723b/hal8723breg.h" + #include "rtl8723b/version_rtl8723b.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8723b/halrf_8723b_win.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "halrf/rtl8723b/halrf_8723b_ce.h" + #include "rtl8723b/halhwimg8723b_mp.h" + #include "rtl8723b_hal.h" + #else + #include "halrf/rtl8723b/halrf_8723b_ap.h" + #endif #endif -#if (RTL8821A_SUPPORT==1) -#include "rtl8821a/halhwimg8821a_mac.h" -#include "rtl8821a/halhwimg8821a_rf.h" -#include "rtl8821a/halhwimg8821a_bb.h" -#include "rtl8821a/halhwimg8821a_fw.h" -#include "rtl8821a/phydm_regconfig8821a.h" -#include "rtl8821a/phydm_rtl8821a.h" -#include "rtl8821a/version_rtl8821a.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8821a/halphyrf_8821a_win.h" -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8821a/halphyrf_8821a_ce.h" - #include "rtl8821a/phydm_iqk_8821a_ce.h"/*for IQK*/ - #include "rtl8812a/halphyrf_8812a_ce.h"/*for IQK,LCK,Power-tracking*/ - #include "rtl8812a_hal.h" -#else -#endif +#if (RTL8821A_SUPPORT == 1) + #include "rtl8821a/halhwimg8821a_mac.h" + #include "rtl8821a/halhwimg8821a_rf.h" + #include "rtl8821a/halhwimg8821a_bb.h" + #include "rtl8821a/halhwimg8821a_fw.h" + #include "rtl8821a/phydm_regconfig8821a.h" + #include "rtl8821a/phydm_rtl8821a.h" + #include "rtl8821a/version_rtl8821a.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8821a/halrf_8821a_win.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "halrf/rtl8821a/halrf_8821a_ce.h" + #include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"/*for IQK*/ + #include "halrf/rtl8812a/halrf_8812a_ce.h"/*for IQK,LCK,Power-tracking*/ + #include "rtl8812a_hal.h" + #else + #endif #endif -#if (RTL8822B_SUPPORT==1) -#include "rtl8822b/halhwimg8822b_mac.h" -#include "rtl8822b/halhwimg8822b_rf.h" -#include "rtl8822b/halhwimg8822b_bb.h" -#include "rtl8822b/halhwimg8822b_fw.h" -#include "rtl8822b/phydm_regconfig8822b.h" -#include "rtl8822b/halphyrf_8822b.h" -#include "rtl8822b/phydm_rtl8822b.h" -#include "rtl8822b/phydm_hal_api8822b.h" -#include "rtl8822b/version_rtl8822b.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#include "../halmac/halmac_reg2.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -#include /* struct HAL_DATA_TYPE */ -#include /* Rx_Smooth_Factor, reg definition and etc.*/ -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) -#endif +#define LDPC_HT_ENABLE_RX BIT(0) +#define LDPC_HT_ENABLE_TX BIT(1) +#define LDPC_HT_TEST_TX_ENABLE BIT(2) +#define LDPC_HT_CAP_TX BIT(3) -#endif +#define STBC_HT_ENABLE_RX BIT(0) +#define STBC_HT_ENABLE_TX BIT(1) +#define STBC_HT_TEST_TX_ENABLE BIT(2) +#define STBC_HT_CAP_TX BIT(3) -#if (RTL8703B_SUPPORT==1) -#include "rtl8703b/phydm_regconfig8703b.h" -#include "rtl8703b/halhwimg8703b_mac.h" -#include "rtl8703b/halhwimg8703b_rf.h" -#include "rtl8703b/halhwimg8703b_bb.h" -#include "rtl8703b/halhwimg8703b_fw.h" -#include "rtl8703b/halphyrf_8703b.h" -#include "rtl8703b/version_rtl8703b.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -#include "rtl8703b_hal.h" -#endif -#endif -#if (RTL8188F_SUPPORT == 1) -#include "rtl8188f/halhwimg8188f_mac.h" -#include "rtl8188f/halhwimg8188f_rf.h" -#include "rtl8188f/halhwimg8188f_bb.h" -#include "rtl8188f/halhwimg8188f_fw.h" -#include "rtl8188f/hal8188freg.h" -#include "rtl8188f/phydm_rtl8188f.h" -#include "rtl8188f/phydm_regconfig8188f.h" -#include "rtl8188f/halphyrf_8188f.h" /* for IQK,LCK,Power-tracking */ -#include "rtl8188f/version_rtl8188f.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -#include "rtl8188f_hal.h" +#define LDPC_VHT_ENABLE_RX BIT(0) +#define LDPC_VHT_ENABLE_TX BIT(1) +#define LDPC_VHT_TEST_TX_ENABLE BIT(2) +#define LDPC_VHT_CAP_TX BIT(3) + +#define STBC_VHT_ENABLE_RX BIT(0) +#define STBC_VHT_ENABLE_TX BIT(1) +#define STBC_VHT_TEST_TX_ENABLE BIT(2) +#define STBC_VHT_CAP_TX BIT(3) #endif + + +#if (RTL8822B_SUPPORT == 1) + #include "rtl8822b/halhwimg8822b_mac.h" + #include "rtl8822b/halhwimg8822b_rf.h" + #include "rtl8822b/halhwimg8822b_bb.h" + #include "rtl8822b/halhwimg8822b_fw.h" + #include "rtl8822b/phydm_regconfig8822b.h" + #include "halrf/rtl8822b/halrf_8822b.h" + #include "rtl8822b/phydm_rtl8822b.h" + #include "rtl8822b/phydm_hal_api8822b.h" + #include "rtl8822b/version_rtl8822b.h" + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef DM_ODM_CE_MAC80211 + #include "../halmac/halmac_reg_8822b.h" + #else + #include /* struct HAL_DATA_TYPE */ + #include /* RX_SMOOTH_FACTOR, reg definition and etc.*/ + #endif + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #endif + #endif -#if (RTL8723D_SUPPORT==1) - #if (DM_ODM_SUPPORT_TYPE != ODM_AP) - - #include "rtl8723d/halhwimg8723d_bb.h" - #include "rtl8723d/halhwimg8723d_mac.h" - #include "rtl8723d/halhwimg8723d_rf.h" - #include "rtl8723d/phydm_regconfig8723d.h" - #include "rtl8723d/halhwimg8723d_fw.h" - #include "rtl8723d/hal8723dreg.h" - #include "rtl8723d/phydm_rtl8723d.h" - #include "rtl8723d/halphyrf_8723d.h" - #include "rtl8723d/version_rtl8723d.h" - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8723d_hal.h" - #endif -#endif //8723D End - -#if (RTL8197F_SUPPORT == 1) -#include "rtl8197f/halhwimg8197f_mac.h" -#include "rtl8197f/halhwimg8197f_rf.h" -#include "rtl8197f/halhwimg8197f_bb.h" -#include "rtl8197f/phydm_hal_api8197f.h" -#include "rtl8197f/version_rtl8197f.h" -#include "rtl8197f/phydm_rtl8197f.h" -#include "rtl8197f/phydm_regconfig8197f.h" -#include "rtl8197f/halphyrf_8197f.h" -#include "rtl8197f/phydm_iqk_8197f.h" +#if (RTL8703B_SUPPORT == 1) + #include "rtl8703b/phydm_regconfig8703b.h" + #include "rtl8703b/halhwimg8703b_mac.h" + #include "rtl8703b/halhwimg8703b_rf.h" + #include "rtl8703b/halhwimg8703b_bb.h" + #include "rtl8703b/halhwimg8703b_fw.h" + #include "halrf/rtl8703b/halrf_8703b.h" + #include "rtl8703b/version_rtl8703b.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8703b_hal.h" + #endif #endif -#if (RTL8821C_SUPPORT==1) -#include "rtl8821c/phydm_hal_api8821c.h" -#include "rtl8821c/halhwimg8821c_testchip_mac.h" -#include "rtl8821c/halhwimg8821c_testchip_rf.h" -#include "rtl8821c/halhwimg8821c_testchip_bb.h" -#include "rtl8821c/phydm_regconfig8821c.h" -#include "rtl8821c/version_rtl8821c.h" -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8821c_hal.h" +#if (RTL8188F_SUPPORT == 1) + #include "rtl8188f/halhwimg8188f_mac.h" + #include "rtl8188f/halhwimg8188f_rf.h" + #include "rtl8188f/halhwimg8188f_bb.h" + #include "rtl8188f/halhwimg8188f_fw.h" + #include "rtl8188f/hal8188freg.h" + #include "rtl8188f/phydm_rtl8188f.h" + #include "rtl8188f/phydm_regconfig8188f.h" + #include "halrf/rtl8188f/halrf_8188f.h" /* for IQK,LCK,Power-tracking */ + #include "rtl8188f/version_rtl8188f.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8188f_hal.h" + #endif #endif + +#if (RTL8723D_SUPPORT == 1) + #if (DM_ODM_SUPPORT_TYPE != ODM_AP) + + #include "rtl8723d/halhwimg8723d_bb.h" + #include "rtl8723d/halhwimg8723d_mac.h" + #include "rtl8723d/halhwimg8723d_rf.h" + #include "rtl8723d/phydm_regconfig8723d.h" + #include "rtl8723d/halhwimg8723d_fw.h" + #include "rtl8723d/hal8723dreg.h" + #include "rtl8723d/phydm_rtl8723d.h" + #include "halrf/rtl8723d/halrf_8723d.h" + #include "rtl8723d/version_rtl8723d.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8723d_hal.h" + #endif +#endif /* 8723D End */ + +/* JJ ADD 20161014 */ +#if (RTL8710B_SUPPORT == 1) + #if (DM_ODM_SUPPORT_TYPE != ODM_AP) + + #include "rtl8710b/halhwimg8710b_bb.h" + #include "rtl8710b/halhwimg8710b_mac.h" + #include "rtl8710b/halhwimg8710b_rf.h" + #include "rtl8710b/phydm_regconfig8710b.h" + #include "rtl8710b/halhwimg8710b_fw.h" + #include "rtl8710b/hal8710breg.h" + #include "rtl8710b/phydm_rtl8710b.h" + #include "halrf/rtl8710b/halrf_8710b.h" + #include "rtl8710b/version_rtl8710b.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8710b_hal.h" + #endif +#endif /* 8710B End */ + +#if (RTL8197F_SUPPORT == 1) + #include "rtl8197f/halhwimg8197f_mac.h" + #include "rtl8197f/halhwimg8197f_rf.h" + #include "rtl8197f/halhwimg8197f_bb.h" + #include "rtl8197f/phydm_hal_api8197f.h" + #include "rtl8197f/version_rtl8197f.h" + #include "rtl8197f/phydm_rtl8197f.h" + #include "rtl8197f/phydm_regconfig8197f.h" + #include "halrf/rtl8197f/halrf_8197f.h" + #include "halrf/rtl8197f/halrf_iqk_8197f.h" #endif -#endif // __ODM_PRECOMP_H__ +#if (RTL8821C_SUPPORT == 1) + #include "rtl8821c/phydm_hal_api8821c.h" + #include "rtl8821c/halhwimg8821c_testchip_mac.h" + #include "rtl8821c/halhwimg8821c_testchip_rf.h" + #include "rtl8821c/halhwimg8821c_testchip_bb.h" + #include "rtl8821c/halhwimg8821c_mac.h" + #include "rtl8821c/halhwimg8821c_rf.h" + #include "rtl8821c/halhwimg8821c_bb.h" + #include "rtl8821c/halhwimg8821c_fw.h" + #include "rtl8821c/phydm_regconfig8821c.h" + #include "halrf/rtl8821c/halrf_8821c.h" + #include "rtl8821c/version_rtl8821c.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8821c_hal.h" + #endif +#endif +#endif /* __ODM_PRECOMP_H__ */ diff --git a/hal/phydm/phydm_rainfo.c b/hal/phydm/phydm_rainfo.c index fbe32a4..991cecf 100644 --- a/hal/phydm/phydm_rainfo.c +++ b/hal/phydm/phydm_rainfo.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,1381 +11,1511 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ -//============================================================ -// include files -//============================================================ +/* ************************************************************ + * include files + * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" +void +phydm_h2C_debug( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 h2c_parameter[H2C_MAX_LENGTH] = {0}; + u8 phydm_h2c_id = (u8)dm_value[0]; + u8 i; + u32 used = *_used; + u32 out_len = *_out_len; + + PHYDM_SNPRINTF((output + used, out_len - used, "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id)); + for (i = 0; i < H2C_MAX_LENGTH; i++) { + + h2c_parameter[i] = (u8)dm_value[i + 1]; + PHYDM_SNPRINTF((output + used, out_len - used, "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i])); + } + + odm_fill_h2c_cmd(p_dm_odm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter); + +} + #if (defined(CONFIG_RA_DBG_CMD)) -VOID -odm_RA_ParaAdjust_Send_H2C( - IN PVOID pDM_VOID +void +odm_ra_para_adjust_send_h2c( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte H2C_Parameter[6] = {0}; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u8 h2c_parameter[6] = {0}; - H2C_Parameter[0] = RA_FIRST_MACID; + h2c_parameter[0] = RA_FIRST_MACID; - if (pRA_Table->RA_Para_feedback_req) { /*H2C_Parameter[5]=1 ; ask FW for all RA parameters*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Ask FW for RA parameter\n")); - H2C_Parameter[5] |= BIT1; /*ask FW to report RA parameters*/ - H2C_Parameter[1] = pRA_Table->para_idx; /*pRA_Table->para_idx;*/ - pRA_Table->RA_Para_feedback_req = 0; + if (p_ra_table->ra_para_feedback_req) { /*h2c_parameter[5]=1 ; ask FW for all RA parameters*/ + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Ask FW for RA parameter\n")); + h2c_parameter[5] |= BIT(1); /*ask FW to report RA parameters*/ + h2c_parameter[1] = p_ra_table->para_idx; /*p_ra_table->para_idx;*/ + p_ra_table->ra_para_feedback_req = 0; } else { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Send H2C to FW for modifying RA parameter\n")); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Send H2C to FW for modifying RA parameter\n")); - H2C_Parameter[1] = pRA_Table->para_idx; - H2C_Parameter[2] = pRA_Table->rate_idx; + h2c_parameter[1] = p_ra_table->para_idx; + h2c_parameter[2] = p_ra_table->rate_idx; /* [8 bit]*/ - if (pRA_Table->para_idx == RADBG_RTY_PENALTY || pRA_Table->para_idx == RADBG_RATE_UP_RTY_RATIO || pRA_Table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { - H2C_Parameter[3] = pRA_Table->value; - H2C_Parameter[4] = 0; + if (p_ra_table->para_idx == RADBG_RTY_PENALTY || p_ra_table->para_idx == RADBG_RATE_UP_RTY_RATIO || p_ra_table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { + h2c_parameter[3] = p_ra_table->value; + h2c_parameter[4] = 0; } /* [16 bit]*/ else { - H2C_Parameter[3] = (u1Byte)(((pRA_Table->value_16) & 0xf0) >> 4); /*byte1*/ - H2C_Parameter[4] = (u1Byte)((pRA_Table->value_16) & 0x0f); /*byte0*/ + h2c_parameter[3] = (u8)(((p_ra_table->value_16) & 0xf0) >> 4); /*byte1*/ + h2c_parameter[4] = (u8)((p_ra_table->value_16) & 0x0f); /*byte0*/ } } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[1] = 0x%x\n", H2C_Parameter[1])); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[2] = 0x%x\n", H2C_Parameter[2])); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[3] = 0x%x\n", H2C_Parameter[3])); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[4] = 0x%x\n", H2C_Parameter[4])); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[5] = 0x%x\n", H2C_Parameter[5])); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[1] = 0x%x\n", h2c_parameter[1])); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[2] = 0x%x\n", h2c_parameter[2])); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[3] = 0x%x\n", h2c_parameter[3])); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[4] = 0x%x\n", h2c_parameter[4])); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[5] = 0x%x\n", h2c_parameter[5])); - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RA_PARA_ADJUST, 6, H2C_Parameter); + odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RA_PARA_ADJUST, 6, h2c_parameter); } -VOID -odm_RA_ParaAdjust( - IN PVOID pDM_VOID +void +odm_ra_para_adjust( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte rate_idx = pRA_Table->rate_idx; - u1Byte value = pRA_Table->value; - u1Byte Pre_value = 0xff; - - if (pRA_Table->para_idx == RADBG_RTY_PENALTY) { - Pre_value = pRA_Table->RTY_P[rate_idx]; - pRA_Table->RTY_P[rate_idx] = value; - pRA_Table->RTY_P_modify_note[rate_idx] = 1; - } else if (pRA_Table->para_idx == RADBG_N_HIGH) { - - } else if (pRA_Table->para_idx == RADBG_N_LOW) { - - } else if (pRA_Table->para_idx == RADBG_RATE_UP_RTY_RATIO) { - Pre_value = pRA_Table->RATE_UP_RTY_RATIO[rate_idx]; - pRA_Table->RATE_UP_RTY_RATIO[rate_idx] = value; - pRA_Table->RATE_UP_RTY_RATIO_modify_note[rate_idx] = 1; - } else if (pRA_Table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { - Pre_value = pRA_Table->RATE_DOWN_RTY_RATIO[rate_idx]; - pRA_Table->RATE_DOWN_RTY_RATIO[rate_idx] = value; - pRA_Table->RATE_DOWN_RTY_RATIO_modify_note[rate_idx] = 1; - } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("Change RA Papa[%d], Rate[ %d ], ((%d)) -> ((%d))\n", pRA_Table->para_idx, rate_idx, Pre_value, value)); - odm_RA_ParaAdjust_Send_H2C(pDM_Odm); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u8 rate_idx = p_ra_table->rate_idx; + u8 value = p_ra_table->value; + u8 pre_value = 0xff; + + if (p_ra_table->para_idx == RADBG_RTY_PENALTY) { + pre_value = p_ra_table->RTY_P[rate_idx]; + p_ra_table->RTY_P[rate_idx] = value; + p_ra_table->RTY_P_modify_note[rate_idx] = 1; + } else if (p_ra_table->para_idx == RADBG_N_HIGH) { + + } else if (p_ra_table->para_idx == RADBG_N_LOW) { + + } else if (p_ra_table->para_idx == RADBG_RATE_UP_RTY_RATIO) { + pre_value = p_ra_table->RATE_UP_RTY_RATIO[rate_idx]; + p_ra_table->RATE_UP_RTY_RATIO[rate_idx] = value; + p_ra_table->RATE_UP_RTY_RATIO_modify_note[rate_idx] = 1; + } else if (p_ra_table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { + pre_value = p_ra_table->RATE_DOWN_RTY_RATIO[rate_idx]; + p_ra_table->RATE_DOWN_RTY_RATIO[rate_idx] = value; + p_ra_table->RATE_DOWN_RTY_RATIO_modify_note[rate_idx] = 1; + } + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("Change RA Papa[%d], rate[ %d ], ((%d)) -> ((%d))\n", p_ra_table->para_idx, rate_idx, pre_value, value)); + odm_ra_para_adjust_send_h2c(p_dm_odm); } -VOID +void phydm_ra_print_msg( - IN PVOID pDM_VOID, - IN u1Byte *value, - IN u1Byte *value_default, - IN u1Byte *modify_note + void *p_dm_void, + u8 *value, + u8 *value_default, + u8 *modify_note ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u4Byte i; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u32 i; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate index| |Current-value| |Default-value| |Modify?|\n")); - for (i = 0 ; i <= (pRA_Table->rate_length); i++) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |Current-value| |Default-value| |Modify?|\n")); + for (i = 0 ; i <= (p_ra_table->rate_length); i++) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %20d %25d %20s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %20d %25d %20s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); #else - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %10d %14d %14s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %10d %14d %14s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); #endif } } -VOID +void odm_RA_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value + void *p_dm_void, + u32 *const dm_value ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - pRA_Table->is_ra_dbg_init = FALSE; + p_ra_table->is_ra_dbg_init = false; if (dm_value[0] == 100) { /*1 Print RA Parameters*/ - u1Byte default_pointer_value; - u1Byte *pvalue; - u1Byte *pvalue_default; - u1Byte *pmodify_note; + u8 default_pointer_value; + u8 *pvalue; + u8 *pvalue_default; + u8 *pmodify_note; pvalue = pvalue_default = pmodify_note = &default_pointer_value; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n")); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n")); if (dm_value[1] == RADBG_RTY_PENALTY) { /* [1]*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [1] RTY_PENALTY\n")); - pvalue = &(pRA_Table->RTY_P[0]); - pvalue_default = &(pRA_Table->RTY_P_default[0]); - pmodify_note = (u1Byte *)&(pRA_Table->RTY_P_modify_note[0]); - } else if (dm_value[1] == RADBG_N_HIGH) { /* [2]*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [2] N_HIGH\n")); - - } else if (dm_value[1] == RADBG_N_LOW) { /*[3]*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [3] N_LOW\n")); - - } else if (dm_value[1] == RADBG_RATE_UP_RTY_RATIO) { /* [8]*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [8] RATE_UP_RTY_RATIO\n")); - pvalue = &(pRA_Table->RATE_UP_RTY_RATIO[0]); - pvalue_default = &(pRA_Table->RATE_UP_RTY_RATIO_default[0]); - pmodify_note = (u1Byte *)&(pRA_Table->RATE_UP_RTY_RATIO_modify_note[0]); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [1] RTY_PENALTY\n")); + pvalue = &(p_ra_table->RTY_P[0]); + pvalue_default = &(p_ra_table->RTY_P_default[0]); + pmodify_note = (u8 *)&(p_ra_table->RTY_P_modify_note[0]); + } else if (dm_value[1] == RADBG_N_HIGH) /* [2]*/ + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [2] N_HIGH\n")); + + else if (dm_value[1] == RADBG_N_LOW) /*[3]*/ + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [3] N_LOW\n")); + + else if (dm_value[1] == RADBG_RATE_UP_RTY_RATIO) { /* [8]*/ + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [8] RATE_UP_RTY_RATIO\n")); + pvalue = &(p_ra_table->RATE_UP_RTY_RATIO[0]); + pvalue_default = &(p_ra_table->RATE_UP_RTY_RATIO_default[0]); + pmodify_note = (u8 *)&(p_ra_table->RATE_UP_RTY_RATIO_modify_note[0]); } else if (dm_value[1] == RADBG_RATE_DOWN_RTY_RATIO) { /* [9]*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [9] RATE_DOWN_RTY_RATIO\n")); - pvalue = &(pRA_Table->RATE_DOWN_RTY_RATIO[0]); - pvalue_default = &(pRA_Table->RATE_DOWN_RTY_RATIO_default[0]); - pmodify_note = (u1Byte *)&(pRA_Table->RATE_DOWN_RTY_RATIO_modify_note[0]); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [9] RATE_DOWN_RTY_RATIO\n")); + pvalue = &(p_ra_table->RATE_DOWN_RTY_RATIO[0]); + pvalue_default = &(p_ra_table->RATE_DOWN_RTY_RATIO_default[0]); + pmodify_note = (u8 *)&(p_ra_table->RATE_DOWN_RTY_RATIO_modify_note[0]); } - phydm_ra_print_msg(pDM_Odm, pvalue, pvalue_default, pmodify_note); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n\n")); + phydm_ra_print_msg(p_dm_odm, pvalue, pvalue_default, pmodify_note); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n\n")); } else if (dm_value[0] == 101) { - pRA_Table->para_idx = (u1Byte)dm_value[1]; + p_ra_table->para_idx = (u8)dm_value[1]; - pRA_Table->RA_Para_feedback_req = 1; - odm_RA_ParaAdjust_Send_H2C(pDM_Odm); + p_ra_table->ra_para_feedback_req = 1; + odm_ra_para_adjust_send_h2c(p_dm_odm); } else { - pRA_Table->para_idx = (u1Byte)dm_value[0]; - pRA_Table->rate_idx = (u1Byte)dm_value[1]; - pRA_Table->value = (u1Byte)dm_value[2]; + p_ra_table->para_idx = (u8)dm_value[0]; + p_ra_table->rate_idx = (u8)dm_value[1]; + p_ra_table->value = (u8)dm_value[2]; - odm_RA_ParaAdjust(pDM_Odm); + odm_ra_para_adjust(p_dm_odm); } } -VOID -odm_RA_ParaAdjust_init( - IN PVOID pDM_VOID +void +odm_ra_para_adjust_init( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte i; - u1Byte ra_para_pool_u8[3] = { RADBG_RTY_PENALTY, RADBG_RATE_UP_RTY_RATIO, RADBG_RATE_DOWN_RTY_RATIO}; - u1Byte RateSize_HT_1ss = 20, RateSize_HT_2ss = 28, RateSize_HT_3ss = 36; /*4+8+8+8+8 =36*/ - u1Byte RateSize_VHT_1ss = 10, RateSize_VHT_2ss = 20, RateSize_VHT_3ss = 30; /*10 + 10 +10 =30*/ - /* - RTY_PENALTY = 1, //u8 - N_HIGH = 2, - N_LOW = 3, - RATE_UP_TABLE = 4, - RATE_DOWN_TABLE = 5, - TRYING_NECESSARY = 6, - DROPING_NECESSARY = 7, - RATE_UP_RTY_RATIO = 8, //u8 - RATE_DOWN_RTY_RATIO= 9, //u8 - ALL_PARA = 0xff - - */ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("odm_RA_ParaAdjust_init\n")); - - if (pDM_Odm->SupportICType & (ODM_RTL8188F | ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8723D)) - pRA_Table->rate_length = RateSize_HT_1ss; - else if (pDM_Odm->SupportICType & (ODM_RTL8192E | ODM_RTL8197F)) - pRA_Table->rate_length = RateSize_HT_2ss; - else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8821C)) - pRA_Table->rate_length = RateSize_HT_1ss + RateSize_VHT_1ss; - else if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8822B)) - pRA_Table->rate_length = RateSize_HT_2ss + RateSize_VHT_2ss; - else if (pDM_Odm->SupportICType == ODM_RTL8814A) - pRA_Table->rate_length = RateSize_HT_3ss + RateSize_VHT_3ss; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u8 i; + u8 ra_para_pool_u8[3] = { RADBG_RTY_PENALTY, RADBG_RATE_UP_RTY_RATIO, RADBG_RATE_DOWN_RTY_RATIO}; + u8 rate_size_ht_1ss = 20, rate_size_ht_2ss = 28, rate_size_ht_3ss = 36; /*4+8+8+8+8 =36*/ + u8 rate_size_vht_1ss = 10, rate_size_vht_2ss = 20, rate_size_vht_3ss = 30; /*10 + 10 +10 =30*/ +#if 0 + /* RTY_PENALTY = 1, u8 */ + /* N_HIGH = 2, */ + /* N_LOW = 3, */ + /* RATE_UP_TABLE = 4, */ + /* RATE_DOWN_TABLE = 5, */ + /* TRYING_NECESSARY = 6, */ + /* DROPING_NECESSARY = 7, */ + /* RATE_UP_RTY_RATIO = 8, u8 */ + /* RATE_DOWN_RTY_RATIO= 9, u8 */ + /* ALL_PARA = 0xff */ + +#endif + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("odm_ra_para_adjust_init\n")); + +/* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type & (ODM_RTL8188F | ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8723D | ODM_RTL8710B)) + p_ra_table->rate_length = rate_size_ht_1ss; + else if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) + p_ra_table->rate_length = rate_size_ht_2ss; + else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8821C)) + p_ra_table->rate_length = rate_size_ht_1ss + rate_size_vht_1ss; + else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) + p_ra_table->rate_length = rate_size_ht_2ss + rate_size_vht_2ss; + else if (p_dm_odm->support_ic_type == ODM_RTL8814A) + p_ra_table->rate_length = rate_size_ht_3ss + rate_size_vht_3ss; else - pRA_Table->rate_length = RateSize_HT_1ss; + p_ra_table->rate_length = rate_size_ht_1ss; - pRA_Table->is_ra_dbg_init = TRUE; + p_ra_table->is_ra_dbg_init = true; for (i = 0; i < 3; i++) { - pRA_Table->RA_Para_feedback_req = 1; - pRA_Table->para_idx = ra_para_pool_u8[i]; - odm_RA_ParaAdjust_Send_H2C(pDM_Odm); + p_ra_table->ra_para_feedback_req = 1; + p_ra_table->para_idx = ra_para_pool_u8[i]; + odm_ra_para_adjust_send_h2c(p_dm_odm); } } #else -VOID +void phydm_RA_debug_PCR( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u4Byte used = *_used; - u4Byte out_len = *_out_len; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u32 used = *_used; + u32 out_len = *_out_len; if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output+used, out_len-used, "[Get] PCR RA_threshold_offset = (( %s%d ))\n", ((pRA_Table->RA_threshold_offset == 0) ? " " : ((pRA_Table->RA_offset_direction) ? "+" : "-")), pRA_Table->RA_threshold_offset)); + PHYDM_SNPRINTF((output + used, out_len - used, "[Get] PCR RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); /**/ } else if (dm_value[0] == 0) { - pRA_Table->RA_offset_direction = 0; - pRA_Table->RA_threshold_offset = (u1Byte)dm_value[1]; - PHYDM_SNPRINTF((output+used, out_len-used, "[Set] PCR RA_threshold_offset = (( -%d ))\n", pRA_Table->RA_threshold_offset)); + p_ra_table->RA_offset_direction = 0; + p_ra_table->RA_threshold_offset = (u8)dm_value[1]; + PHYDM_SNPRINTF((output + used, out_len - used, "[Set] PCR RA_threshold_offset = (( -%d ))\n", p_ra_table->RA_threshold_offset)); } else if (dm_value[0] == 1) { - pRA_Table->RA_offset_direction = 1; - pRA_Table->RA_threshold_offset = (u1Byte)dm_value[1]; - PHYDM_SNPRINTF((output+used, out_len-used, "[Set] PCR RA_threshold_offset = (( +%d ))\n", pRA_Table->RA_threshold_offset)); + p_ra_table->RA_offset_direction = 1; + p_ra_table->RA_threshold_offset = (u8)dm_value[1]; + PHYDM_SNPRINTF((output + used, out_len - used, "[Set] PCR RA_threshold_offset = (( +%d ))\n", p_ra_table->RA_threshold_offset)); } else { - PHYDM_SNPRINTF((output+used, out_len-used, "[Set] Error\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "[Set] Error\n")); /**/ } - + } #endif /*#if (defined(CONFIG_RA_DBG_CMD))*/ -VOID -ODM_C2HRaParaReportHandler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen +void +odm_c2h_ra_para_report_handler( + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if (defined(CONFIG_RA_DBG_CMD)) + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; +#endif - u1Byte para_idx = CmdBuf[0]; /*Retry Penalty, NH, NL*/ - u1Byte RateTypeStart = CmdBuf[1]; - u1Byte RateTypeLength = CmdLen - 2; - u1Byte i; + u8 para_idx = cmd_buf[0]; /*Retry Penalty, NH, NL*/ +#if (defined(CONFIG_RA_DBG_CMD)) + u8 rate_type_start = cmd_buf[1]; + u8 rate_type_length = cmd_len - 2; +#endif + u8 i; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[ From FW C2H RA Para ] CmdBuf[0]= (( %d ))\n", CmdBuf[0])); - + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[ From FW C2H RA Para ] cmd_buf[0]= (( %d ))\n", cmd_buf[0])); + #if (defined(CONFIG_RA_DBG_CMD)) if (para_idx == RADBG_RTY_PENALTY) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |RTY Penality Index|\n")); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |RTY Penality index|\n")); - for (i = 0 ; i < (RateTypeLength) ; i++) { - if (pRA_Table->is_ra_dbg_init) - pRA_Table->RTY_P_default[RateTypeStart + i] = CmdBuf[2 + i]; + for (i = 0 ; i < (rate_type_length) ; i++) { + if (p_ra_table->is_ra_dbg_init) + p_ra_table->RTY_P_default[rate_type_start + i] = cmd_buf[2 + i]; - pRA_Table->RTY_P[RateTypeStart + i] = CmdBuf[2 + i]; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d \n", (RateTypeStart + i), pRA_Table->RTY_P[RateTypeStart + i])); + p_ra_table->RTY_P[rate_type_start + i] = cmd_buf[2 + i]; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (rate_type_start + i), p_ra_table->RTY_P[rate_type_start + i])); } } else if (para_idx == RADBG_N_HIGH) { /**/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |N-High|\n")); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |N-High|\n")); } else if (para_idx == RADBG_N_LOW) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |N-Low|\n")); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |N-Low|\n")); /**/ - } - else if (para_idx == RADBG_RATE_UP_RTY_RATIO) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |Rate Up RTY Ratio|\n")); + } else if (para_idx == RADBG_RATE_UP_RTY_RATIO) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |rate Up RTY Ratio|\n")); - for (i = 0; i < (RateTypeLength); i++) { - if (pRA_Table->is_ra_dbg_init) - pRA_Table->RATE_UP_RTY_RATIO_default[RateTypeStart + i] = CmdBuf[2 + i]; + for (i = 0; i < (rate_type_length); i++) { + if (p_ra_table->is_ra_dbg_init) + p_ra_table->RATE_UP_RTY_RATIO_default[rate_type_start + i] = cmd_buf[2 + i]; - pRA_Table->RATE_UP_RTY_RATIO[RateTypeStart + i] = CmdBuf[2 + i]; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (RateTypeStart + i), pRA_Table->RATE_UP_RTY_RATIO[RateTypeStart + i])); + p_ra_table->RATE_UP_RTY_RATIO[rate_type_start + i] = cmd_buf[2 + i]; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (rate_type_start + i), p_ra_table->RATE_UP_RTY_RATIO[rate_type_start + i])); } } else if (para_idx == RADBG_RATE_DOWN_RTY_RATIO) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |Rate Down RTY Ratio|\n")); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |rate Down RTY Ratio|\n")); - for (i = 0; i < (RateTypeLength); i++) { - if (pRA_Table->is_ra_dbg_init) - pRA_Table->RATE_DOWN_RTY_RATIO_default[RateTypeStart + i] = CmdBuf[2 + i]; + for (i = 0; i < (rate_type_length); i++) { + if (p_ra_table->is_ra_dbg_init) + p_ra_table->RATE_DOWN_RTY_RATIO_default[rate_type_start + i] = cmd_buf[2 + i]; - pRA_Table->RATE_DOWN_RTY_RATIO[RateTypeStart + i] = CmdBuf[2 + i]; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (RateTypeStart + i), pRA_Table->RATE_DOWN_RTY_RATIO[RateTypeStart + i])); - } - } else -#endif - if (para_idx == RADBG_DEBUG_MONITOR1) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - if (pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) { - - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", CmdBuf[1])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Rate =", CmdBuf[2] & 0x7f)); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI =", (CmdBuf[2] & 0x80) >> 7)); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW =", CmdBuf[3])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW_max =", CmdBuf[4])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate0 =", CmdBuf[5])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate1 =", CmdBuf[6])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", CmdBuf[7])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", CmdBuf[8])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI_support =", CmdBuf[9])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "try_ness =", CmdBuf[10])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "pre_rate =", CmdBuf[11])); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", CmdBuf[1])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x\n", "BW =", CmdBuf[2])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", CmdBuf[3])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", CmdBuf[4])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Hightest Rate =", CmdBuf[5])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Lowest Rate =", CmdBuf[6])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "SGI_support =", CmdBuf[7])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Rate_ID =", CmdBuf[8]));; + p_ra_table->RATE_DOWN_RTY_RATIO[rate_type_start + i] = cmd_buf[2 + i]; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (rate_type_start + i), p_ra_table->RATE_DOWN_RTY_RATIO[rate_type_start + i])); } - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - } else if (para_idx == RADBG_DEBUG_MONITOR2) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - if (pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RateID =", CmdBuf[1])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest_rate =", CmdBuf[2])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "lowest_rate =", CmdBuf[3])); - - for (i = 4; i <= 11; i++) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("RAMASK = 0x%x\n", CmdBuf[i])); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x%x %x%x %x%x %x%x\n", "RA Mask:", - CmdBuf[8], CmdBuf[7], CmdBuf[6], CmdBuf[5], CmdBuf[4], CmdBuf[3], CmdBuf[2], CmdBuf[1])); - } - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - } else if (para_idx == RADBG_DEBUG_MONITOR3) { + } else +#endif + if (para_idx == RADBG_DEBUG_MONITOR1) { + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { + + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", cmd_buf[1])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "rate =", cmd_buf[2] & 0x7f)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI =", (cmd_buf[2] & 0x80) >> 7)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW =", cmd_buf[3])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW_max =", cmd_buf[4])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate0 =", cmd_buf[5])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate1 =", cmd_buf[6])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", cmd_buf[7])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", cmd_buf[8])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI_support =", cmd_buf[9])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "try_ness =", cmd_buf[10])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "pre_rate =", cmd_buf[11])); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", cmd_buf[1])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x\n", "BW =", cmd_buf[2])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", cmd_buf[3])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", cmd_buf[4])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Hightest rate =", cmd_buf[5])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Lowest rate =", cmd_buf[6])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "SGI_support =", cmd_buf[7])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Rate_ID =", cmd_buf[8]));; + } + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + } else if (para_idx == RADBG_DEBUG_MONITOR2) { + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "rate_id =", cmd_buf[1])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest_rate =", cmd_buf[2])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "lowest_rate =", cmd_buf[3])); + + for (i = 4; i <= 11; i++) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("RAMASK = 0x%x\n", cmd_buf[i])); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x%x %x%x %x%x %x%x\n", "RA Mask:", + cmd_buf[8], cmd_buf[7], cmd_buf[6], cmd_buf[5], cmd_buf[4], cmd_buf[3], cmd_buf[2], cmd_buf[1])); + } + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + } else if (para_idx == RADBG_DEBUG_MONITOR3) { - for (i = 0; i < (CmdLen - 1); i++) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("content[%d] = %d\n", i, CmdBuf[1 + i])); - } else if (para_idx == RADBG_DEBUG_MONITOR4) - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {%d.%d}\n", "RA Version =", CmdBuf[1], CmdBuf[2])); + for (i = 0; i < (cmd_len - 1); i++) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("content[%d] = %d\n", i, cmd_buf[1 + i])); + } else if (para_idx == RADBG_DEBUG_MONITOR4) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {%d.%d}\n", "RA version =", cmd_buf[1], cmd_buf[2])); else if (para_idx == RADBG_DEBUG_MONITOR5) { - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Current rate =", CmdBuf[1])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Retry ratio =", CmdBuf[2])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Rate down ratio =", CmdBuf[3])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest rate =", CmdBuf[4])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {0x%x 0x%x}\n", "Muti-try =", CmdBuf[5], CmdBuf[6])); - ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x%x%x%x%x\n", "RA mask =", CmdBuf[11], CmdBuf[10], CmdBuf[9], CmdBuf[8], CmdBuf[7])); - } + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Current rate =", cmd_buf[1])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Retry ratio =", cmd_buf[2])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "rate down ratio =", cmd_buf[3])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest rate =", cmd_buf[4])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {0x%x 0x%x}\n", "Muti-try =", cmd_buf[5], cmd_buf[6])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x%x%x%x%x\n", "RA mask =", cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8], cmd_buf[7])); + } } -VOID +void phydm_ra_dynamic_retry_count( - IN PVOID pDM_VOID + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - PSTA_INFO_T pEntry; - u1Byte i, retry_offset; - u4Byte ma_rx_tp; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_ARFR)) { + if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_ARFR)) return; - } - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("pDM_Odm->pre_b_noisy = %d\n", pDM_Odm->pre_b_noisy ));*/ - if (pDM_Odm->pre_b_noisy != pDM_Odm->NoisyDecision) { + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("p_dm_odm->pre_b_noisy = %d\n", p_dm_odm->pre_b_noisy ));*/ + if (p_dm_odm->pre_b_noisy != p_dm_odm->noisy_decision) { - if (pDM_Odm->NoisyDecision) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Noisy Env. RA fallback value\n")); - ODM_SetMACReg(pDM_Odm, 0x430, bMaskDWord, 0x0); - ODM_SetMACReg(pDM_Odm, 0x434, bMaskDWord, 0x04030201); + if (p_dm_odm->noisy_decision) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Noisy Env. RA fallback value\n")); + odm_set_mac_reg(p_dm_odm, 0x430, MASKDWORD, 0x0); + odm_set_mac_reg(p_dm_odm, 0x434, MASKDWORD, 0x04030201); } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Clean Env. RA fallback value\n")); - ODM_SetMACReg(pDM_Odm, 0x430, bMaskDWord, 0x01000000); - ODM_SetMACReg(pDM_Odm, 0x434, bMaskDWord, 0x06050402); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Clean Env. RA fallback value\n")); + odm_set_mac_reg(p_dm_odm, 0x430, MASKDWORD, 0x01000000); + odm_set_mac_reg(p_dm_odm, 0x434, MASKDWORD, 0x06050402); } - pDM_Odm->pre_b_noisy = pDM_Odm->NoisyDecision; + p_dm_odm->pre_b_noisy = p_dm_odm->noisy_decision; } } #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) -VOID +void phydm_retry_limit_table_bound( - IN PVOID pDM_VOID, - IN u1Byte *retry_limit, - IN u1Byte offset + void *p_dm_void, + u8 *retry_limit, + u8 offset ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; if (*retry_limit > offset) { - + *retry_limit -= offset; - - if (*retry_limit < pRA_Table->retrylimit_low) - *retry_limit = pRA_Table->retrylimit_low; - else if (*retry_limit > pRA_Table->retrylimit_high) - *retry_limit = pRA_Table->retrylimit_high; + + if (*retry_limit < p_ra_table->retrylimit_low) + *retry_limit = p_ra_table->retrylimit_low; + else if (*retry_limit > p_ra_table->retrylimit_high) + *retry_limit = p_ra_table->retrylimit_high; } else - *retry_limit = pRA_Table->retrylimit_low; + *retry_limit = p_ra_table->retrylimit_low; } -VOID +void phydm_reset_retry_limit_table( - IN PVOID pDM_VOID + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte i; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u8 i; - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*support all IC platform*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*support all IC platform*/ - #else - #if ((RTL8192E_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1)) - u1Byte per_rate_retrylimit_table_20M[ODM_RATEMCS15+1] = { - 1, 1, 2, 4, /*CCK*/ - 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ - 2, 4, 6, 8, 12, 18, 20, 22, /*20M HT-1SS*/ - 2, 4, 6, 8, 12, 18, 20, 22 /*20M HT-2SS*/ - }; - u1Byte per_rate_retrylimit_table_40M[ODM_RATEMCS15+1] = { - 1, 1, 2, 4, /*CCK*/ - 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ - 4, 8, 12, 16, 24, 32, 32, 32, /*40M HT-1SS*/ - 4, 8, 12, 16, 24, 32, 32, 32 /*40M HT-2SS*/ - }; - - #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) - - #elif (RTL8812A_SUPPORT == 1) - - #elif(RTL8814A_SUPPORT == 1) +#else +#if ((RTL8192E_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1)) + u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = { + 1, 1, 2, 4, /*CCK*/ + 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ + 2, 4, 6, 8, 12, 18, 20, 22, /*20M HT-1SS*/ + 2, 4, 6, 8, 12, 18, 20, 22 /*20M HT-2SS*/ + }; + u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = { + 1, 1, 2, 4, /*CCK*/ + 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ + 4, 8, 12, 16, 24, 32, 32, 32, /*40M HT-1SS*/ + 4, 8, 12, 16, 24, 32, 32, 32 /*40M HT-2SS*/ + }; + +#elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) + +#elif (RTL8812A_SUPPORT == 1) + +#elif (RTL8814A_SUPPORT == 1) - #else +#else - #endif - #endif +#endif +#endif - memcpy(&(pRA_Table->per_rate_retrylimit_20M[0]), &(per_rate_retrylimit_table_20M[0]), ODM_NUM_RATE_IDX); - memcpy(&(pRA_Table->per_rate_retrylimit_40M[0]), &(per_rate_retrylimit_table_40M[0]), ODM_NUM_RATE_IDX); + memcpy(&(p_ra_table->per_rate_retrylimit_20M[0]), &(per_rate_retrylimit_table_20M[0]), ODM_NUM_RATE_IDX); + memcpy(&(p_ra_table->per_rate_retrylimit_40M[0]), &(per_rate_retrylimit_table_40M[0]), ODM_NUM_RATE_IDX); for (i = 0; i < ODM_NUM_RATE_IDX; i++) { - phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_20M[i]), 0); - phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_40M[i]), 0); - } + phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_20M[i]), 0); + phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_40M[i]), 0); + } } -VOID +void phydm_ra_dynamic_retry_limit_init( - IN PVOID pDM_VOID + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + + p_ra_table->retry_descend_num = RA_RETRY_DESCEND_NUM; + p_ra_table->retrylimit_low = RA_RETRY_LIMIT_LOW; + p_ra_table->retrylimit_high = RA_RETRY_LIMIT_HIGH; + + phydm_reset_retry_limit_table(p_dm_odm); - pRA_Table->retry_descend_num = RA_RETRY_DESCEND_NUM; - pRA_Table->retrylimit_low = RA_RETRY_LIMIT_LOW; - pRA_Table->retrylimit_high = RA_RETRY_LIMIT_HIGH; - - phydm_reset_retry_limit_table(pDM_Odm); - } #endif -VOID +void phydm_ra_dynamic_retry_limit( - IN PVOID pDM_VOID + void *p_dm_void ) { #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - PSTA_INFO_T pEntry; - u1Byte i, retry_offset; - u4Byte ma_rx_tp; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u8 i, retry_offset; + u32 ma_rx_tp; + + if (p_dm_odm->pre_number_active_client == p_dm_odm->number_active_client) { - if (pDM_Odm->pre_number_active_client == pDM_Odm->number_active_client) { - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" pre_number_active_client == number_active_client\n")); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" pre_number_active_client == number_active_client\n")); return; - + } else { - if (pDM_Odm->number_active_client == 1) { - phydm_reset_retry_limit_table(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("one client only->reset to default value\n")); + if (p_dm_odm->number_active_client == 1) { + phydm_reset_retry_limit_table(p_dm_odm); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("one client only->reset to default value\n")); } else { - retry_offset = pDM_Odm->number_active_client * pRA_Table->retry_descend_num; - + retry_offset = p_dm_odm->number_active_client * p_ra_table->retry_descend_num; + for (i = 0; i < ODM_NUM_RATE_IDX; i++) { - phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_20M[i]), retry_offset); - phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_40M[i]), retry_offset); - } + phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_20M[i]), retry_offset); + phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_40M[i]), retry_offset); + } } } #endif } #if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) -VOID +void phydm_ra_dynamic_rate_id_on_assoc( - IN PVOID pDM_VOID, - IN u1Byte wireless_mode, - IN u1Byte init_rate_id + void *p_dm_void, + u8 wireless_mode, + u8 init_rate_id ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n", pDM_Odm->RFType, wireless_mode, init_rate_id)); - - if ((pDM_Odm->RFType == ODM_2T2R) | (pDM_Odm->RFType == ODM_2T2R_GREEN) | (pDM_Odm->RFType == ODM_2T3R) | (pDM_Odm->RFType == ODM_2T4R)) { - - if ((pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8192E)) && - (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) - ){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set N-2SS ARFR5 table\n")); - ODM_SetMACReg(pDM_Odm, 0x4a4, bMaskDWord, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ - ODM_SetMACReg(pDM_Odm, 0x4a8, bMaskDWord, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ - } else if ((pDM_Odm->SupportICType & (ODM_RTL8812)) && + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n", p_dm_odm->rf_type, wireless_mode, init_rate_id)); + + if ((p_dm_odm->rf_type == ODM_2T2R) | (p_dm_odm->rf_type == ODM_2T2R_GREEN) | (p_dm_odm->rf_type == ODM_2T3R) | (p_dm_odm->rf_type == ODM_2T4R)) { + + if ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) && + (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) + ) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set N-2SS ARFR5 table\n")); + odm_set_mac_reg(p_dm_odm, 0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ + odm_set_mac_reg(p_dm_odm, 0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ + } else if ((p_dm_odm->support_ic_type & (ODM_RTL8812)) && (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) - ){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set AC-2SS ARFR0 table\n")); - ODM_SetMACReg(pDM_Odm, 0x444, bMaskDWord, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ - ODM_SetMACReg(pDM_Odm, 0x448, bMaskDWord, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ + ) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set AC-2SS ARFR0 table\n")); + odm_set_mac_reg(p_dm_odm, 0x444, MASKDWORD, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ + odm_set_mac_reg(p_dm_odm, 0x448, MASKDWORD, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ } } } -VOID +void phydm_ra_dynamic_rate_id_init( - IN PVOID pDM_VOID + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8192E)) { - - ODM_SetMACReg(pDM_Odm, 0x4a4, bMaskDWord, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ - ODM_SetMACReg(pDM_Odm, 0x4a8, bMaskDWord, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ - - ODM_SetMACReg(pDM_Odm, 0x444, bMaskDWord, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ - ODM_SetMACReg(pDM_Odm, 0x448, bMaskDWord, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) { + + odm_set_mac_reg(p_dm_odm, 0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ + odm_set_mac_reg(p_dm_odm, 0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ + + odm_set_mac_reg(p_dm_odm, 0x444, MASKDWORD, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ + odm_set_mac_reg(p_dm_odm, 0x448, MASKDWORD, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ } } -VOID +void phydm_update_rate_id( - IN PVOID pDM_VOID, - IN u1Byte rate, - IN u1Byte platform_macid + void *p_dm_void, + u8 rate, + u8 platform_macid ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte current_tx_ss; - u1Byte rate_idx = rate & 0x7f; /*remove bit7 SGI*/ - u1Byte wireless_mode; - u1Byte phydm_macid; - PSTA_INFO_T pEntry; - - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u8 current_tx_ss; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 wireless_mode; + u8 phydm_macid; + struct sta_info *p_entry; + + #if 0 if (rate_idx >= ODM_RATEVHTSS2MCS0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( VHT2SS-MCS%d ))\n", platform_macid, (rate_idx-ODM_RATEVHTSS2MCS0))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( VHT2SS-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0))); /*dummy for SD4 check patch*/ } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( VHT1SS-MCS%d ))\n", platform_macid, (rate_idx-ODM_RATEVHTSS1MCS0))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( VHT1SS-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0))); /*dummy for SD4 check patch*/ } else if (rate_idx >= ODM_RATEMCS0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( HT-MCS%d ))\n", platform_macid, (rate_idx-ODM_RATEMCS0))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( HT-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEMCS0))); /*dummy for SD4 check patch*/ } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( HT-MCS%d ))\n", platform_macid, rate_idx)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( HT-MCS%d ))\n", platform_macid, rate_idx)); /*dummy for SD4 check patch*/ } #endif - - phydm_macid = pDM_Odm->platform2phydm_macid_table[platform_macid]; - pEntry = pDM_Odm->pODM_StaInfo[phydm_macid]; - - if (IS_STA_VALID(pEntry)) { - wireless_mode = pEntry->WirelessMode; - if ((pDM_Odm->RFType == ODM_2T2R) | (pDM_Odm->RFType == ODM_2T2R_GREEN) | (pDM_Odm->RFType == ODM_2T3R) | (pDM_Odm->RFType == ODM_2T4R)) { - - pEntry->ratr_idx = pEntry->ratr_idx_init; + phydm_macid = p_dm_odm->platform2phydm_macid_table[platform_macid]; + p_entry = p_dm_odm->p_odm_sta_info[phydm_macid]; + + if (IS_STA_VALID(p_entry)) { + wireless_mode = p_entry->wireless_mode; + + if ((p_dm_odm->rf_type == ODM_2T2R) | (p_dm_odm->rf_type == ODM_2T2R_GREEN) | (p_dm_odm->rf_type == ODM_2T3R) | (p_dm_odm->rf_type == ODM_2T4R)) { + + p_entry->ratr_idx = p_entry->ratr_idx_init; if (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) { /*N mode*/ if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*2SS mode*/ - - pEntry->ratr_idx = ARFR_5_RATE_ID; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_5\n")); + + p_entry->ratr_idx = ARFR_5_RATE_ID; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_5\n")); } } else if (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) {/*AC mode*/ if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*2SS mode*/ - - pEntry->ratr_idx = ARFR_0_RATE_ID; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_0\n")); + + p_entry->ratr_idx = ARFR_0_RATE_ID; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_0\n")); } } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("UPdate_RateID[%d]: (( 0x%x ))\n", platform_macid, pEntry->ratr_idx)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("UPdate_RateID[%d]: (( 0x%x ))\n", platform_macid, p_entry->ratr_idx)); } } } #endif -VOID +void phydm_print_rate( - IN PVOID pDM_VOID, - IN u1Byte rate, - IN u4Byte dbg_component + void *p_dm_void, + u8 rate, + u32 dbg_component ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; - u1Byte rate_idx = rate & 0x7f; /*remove bit7 SGI*/ - u1Byte vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0; - u1Byte b_sgi = (rate & 0x80)>>7; - - ODM_RT_TRACE_F(pDM_Odm, dbg_component, ODM_DBG_LOUD, ("( %s%s%s%s%d%s%s)\n", + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0; + u8 b_sgi = (rate & 0x80) >> 7; + + ODM_RT_TRACE_F(p_dm_odm, dbg_component, ODM_DBG_LOUD, ("( %s%s%s%s%d%s%s)\n", ((rate_idx >= ODM_RATEVHTSS1MCS0) && (rate_idx <= ODM_RATEVHTSS1MCS9)) ? "VHT 1ss " : "", ((rate_idx >= ODM_RATEVHTSS2MCS0) && (rate_idx <= ODM_RATEVHTSS2MCS9)) ? "VHT 2ss " : "", ((rate_idx >= ODM_RATEVHTSS3MCS0) && (rate_idx <= ODM_RATEVHTSS3MCS9)) ? "VHT 3ss " : "", - (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", - (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0)%10) : ((rate_idx >= ODM_RATEMCS0) ? (rate_idx - ODM_RATEMCS0) : ((rate_idx <= ODM_RATE54M)?legacy_table[rate_idx]:0)), - (b_sgi) ? "-S" : " ", - (rate_idx >= ODM_RATEMCS0) ? "" : "M")); + (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", + (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0) % 10) : ((rate_idx >= ODM_RATEMCS0) ? (rate_idx - ODM_RATEMCS0) : ((rate_idx <= ODM_RATE54M) ? legacy_table[rate_idx] : 0)), + (b_sgi) ? "-S" : " ", + (rate_idx >= ODM_RATEMCS0) ? "" : "M")); } -VOID +void phydm_c2h_ra_report_handler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte legacy_table[12] = {1,2,5,11,6,9,12,18,24,36,48,54}; - u1Byte macid = CmdBuf[1]; - u1Byte rate = CmdBuf[0]; - u1Byte rate_idx = rate & 0x7f; /*remove bit7 SGI*/ - u1Byte pre_rate = pRA_Table->link_tx_rate[macid]; - u1Byte rate_order; - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - - GET_HAL_DATA(Adapter)->CurrentRARate = HwRateToMRate(rate_idx); - #endif - - - if (CmdLen >= 4) { - if (CmdBuf[3] == 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("TX Init-Rate Update[%d]:", macid)); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u8 macid = cmd_buf[1]; + u8 rate = cmd_buf[0]; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 rate_order; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + + GET_HAL_DATA(adapter)->CurrentRARate = HwRateToMRate(rate_idx); +#endif + + + if (cmd_len >= 4) { + if (cmd_buf[3] == 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("TX Init-rate Update[%d]:", macid)); /**/ - } else if (CmdBuf[3] == 0xff) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("FW Level: Fix rate[%d]:", macid)); + } else if (cmd_buf[3] == 0xff) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("FW Level: Fix rate[%d]:", macid)); /**/ - } else if (CmdBuf[3] == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Success[%d]:", macid)); + } else if (cmd_buf[3] == 1) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Success[%d]:", macid)); /**/ - } else if (CmdBuf[3] == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Fail & Try Again[%d]:", macid)); + } else if (cmd_buf[3] == 2) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Fail & Try Again[%d]:", macid)); /**/ - } else if (CmdBuf[3] == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate Back[%d]:", macid)); + } else if (cmd_buf[3] == 3) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate Back[%d]:", macid)); /**/ - } else if (CmdBuf[3] == 4) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("start rate by RSSI[%d]:", macid)); + } else if (cmd_buf[3] == 4) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("start rate by RSSI[%d]:", macid)); /**/ - } else if (CmdBuf[3] == 5) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try rate[%d]:", macid)); + } else if (cmd_buf[3] == 5) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try rate[%d]:", macid)); /**/ } } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Tx Rate Update[%d]:", macid)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Tx rate Update[%d]:", macid)); /**/ } - - /*phydm_print_rate(pDM_Odm, pre_rate_idx, ODM_COMP_RATE_ADAPTIVE);*/ - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (">\n",macid );*/ - phydm_print_rate(pDM_Odm, rate, ODM_COMP_RATE_ADAPTIVE); - pRA_Table->link_tx_rate[macid] = rate; + /*phydm_print_rate(p_dm_odm, pre_rate_idx, ODM_COMP_RATE_ADAPTIVE);*/ + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (">\n",macid );*/ + phydm_print_rate(p_dm_odm, rate, ODM_COMP_RATE_ADAPTIVE); + + p_ra_table->link_tx_rate[macid] = rate; /*trigger power training*/ - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - rate_order = phydm_rate_order_compute(pDM_Odm, rate_idx); - - if ((pDM_Odm->bOneEntryOnly) || - ((rate_order > pRA_Table->highest_client_tx_order) && (pRA_Table->power_tracking_flag == 1)) - ) { - phydm_update_pwr_track(pDM_Odm, rate_idx); - pRA_Table->power_tracking_flag = 0; + rate_order = phydm_rate_order_compute(p_dm_odm, rate_idx); + + if ((p_dm_odm->is_one_entry_only) || + ((rate_order > p_ra_table->highest_client_tx_order) && (p_ra_table->power_tracking_flag == 1)) + ) { + phydm_update_pwr_track(p_dm_odm, rate_idx); + p_ra_table->power_tracking_flag = 0; } - - #endif - + +#endif + /*trigger dynamic rate ID*/ - #if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8192E)) - phydm_update_rate_id(pDM_Odm, rate, macid); - #endif +#if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) + if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) + phydm_update_rate_id(p_dm_odm, rate, macid); +#endif } -VOID -odm_RSSIMonitorInit( - IN PVOID pDM_VOID +void +odm_rssi_monitor_init( + void *p_dm_void ) { -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - pRA_Table->PT_collision_pre = TRUE; /*used in ODM_DynamicARFBSelect(WIN only)*/ - - pHalData->UndecoratedSmoothedPWDB = -1; - pHalData->ra_rpt_linked = FALSE; - #endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + + p_ra_table->PT_collision_pre = true; /*used in odm_dynamic_arfb_select(WIN only)*/ + + p_hal_data->UndecoratedSmoothedPWDB = -1; + p_hal_data->ra_rpt_linked = false; +#endif + + p_ra_table->firstconnect = false; - pRA_Table->firstconnect = FALSE; - #endif } -VOID -ODM_RAPostActionOnAssoc( - IN PVOID pDM_VOID +void +odm_ra_post_action_on_assoc( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -/* - pDM_Odm->H2C_RARpt_connect = 1; - odm_RSSIMonitorCheck(pDM_Odm); - pDM_Odm->H2C_RARpt_connect = 0; -*/ +#if 0 + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + p_dm_odm->h2c_rarpt_connect = 1; + odm_rssi_monitor_check(p_dm_odm); + p_dm_odm->h2c_rarpt_connect = 0; +#endif } -VOID -phydm_initRaInfo( - IN PVOID pDM_VOID +void +phydm_init_ra_info( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) { - u4Byte ret_value; + if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + u32 ret_value; - ret_value = ODM_GetBBReg(pDM_Odm, 0x4c8, bMaskByte2); - ODM_SetBBReg(pDM_Odm, 0x4cc, bMaskByte3, (ret_value - 1)); + ret_value = odm_get_bb_reg(p_dm_odm, 0x4c8, MASKBYTE2); + odm_set_bb_reg(p_dm_odm, 0x4cc, MASKBYTE3, (ret_value - 1)); } #endif } -VOID -odm_RSSIMonitorCheckMP( - IN PVOID pDM_VOID +void +phydm_modify_RA_PCR_threshold( + void *p_dm_void, + u8 RA_offset_direction, + u8 RA_threshold_offset + +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + + p_ra_table->RA_offset_direction = RA_offset_direction; + p_ra_table->RA_threshold_offset = RA_threshold_offset; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Set RA_threshold_offset = (( %s%d ))\n", ((RA_threshold_offset == 0) ? " " : ((RA_offset_direction) ? "+" : "-")), RA_threshold_offset)); +} + +void +odm_rssi_monitor_check_mp( + void *p_dm_void ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u1Byte H2C_Parameter[H2C_0X42_LENGTH] = {0}; - u4Byte i; - BOOLEAN bExtRAInfo = TRUE; - u1Byte cmdlen = H2C_0X42_LENGTH; - u1Byte TxBF_EN = 0, stbc_en = 0; - - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PSTA_INFO_T pEntry = NULL; - s4Byte tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - PMGNT_INFO pDefaultMgntInfo = &Adapter->MgntInfo; - u8Byte curTxOkCnt = 0, curRxOkCnt = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; + u32 i; + boolean is_ext_ra_info = true; + u8 cmdlen = H2C_0X42_LENGTH; + u8 tx_bf_en = 0, stbc_en = 0; + + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct sta_info *p_entry = NULL; + s32 tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff; + PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; + PMGNT_INFO p_default_mgnt_info = &adapter->MgntInfo; + u64 cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0; #if (BEAMFORMING_SUPPORT == 1) #ifndef BEAMFORMING_VERSION_1 - BEAMFORMING_CAP Beamform_cap = BEAMFORMING_CAP_NONE; + enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; #endif #endif - PADAPTER pLoopAdapter = GetDefaultAdapter(Adapter); + struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(adapter); - if (pDM_Odm->SupportICType == ODM_RTL8188E) { - bExtRAInfo = FALSE; + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + is_ext_ra_info = false; cmdlen = 3; } - while (pLoopAdapter) { + while (p_loop_adapter) { - if (pLoopAdapter != NULL) { - pMgntInfo = &pLoopAdapter->MgntInfo; - curTxOkCnt = pLoopAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt; - curRxOkCnt = pLoopAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt; - pMgntInfo->lastTxOkCnt = curTxOkCnt; - pMgntInfo->lastRxOkCnt = curRxOkCnt; + if (p_loop_adapter != NULL) { + p_mgnt_info = &p_loop_adapter->MgntInfo; + cur_tx_ok_cnt = p_loop_adapter->TxStats.NumTxBytesUnicast - p_mgnt_info->lastTxOkCnt; + cur_rx_ok_cnt = p_loop_adapter->RxStats.NumRxBytesUnicast - p_mgnt_info->lastRxOkCnt; + p_mgnt_info->lastTxOkCnt = cur_tx_ok_cnt; + p_mgnt_info->lastRxOkCnt = cur_rx_ok_cnt; } for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) { - if (IsAPModeExist(pLoopAdapter)) { - if (GetFirstExtAdapter(pLoopAdapter) != NULL && - GetFirstExtAdapter(pLoopAdapter) == pLoopAdapter) - pEntry = AsocEntry_EnumStation(pLoopAdapter, i); - else if (GetFirstGOPort(pLoopAdapter) != NULL && - IsFirstGoAdapter(pLoopAdapter)) - pEntry = AsocEntry_EnumStation(pLoopAdapter, i); + if (IsAPModeExist(p_loop_adapter)) { + if (GetFirstExtAdapter(p_loop_adapter) != NULL && + GetFirstExtAdapter(p_loop_adapter) == p_loop_adapter) + p_entry = AsocEntry_EnumStation(p_loop_adapter, i); + else if (GetFirstGOPort(p_loop_adapter) != NULL && + IsFirstGoAdapter(p_loop_adapter)) + p_entry = AsocEntry_EnumStation(p_loop_adapter, i); } else { - if (GetDefaultAdapter(pLoopAdapter) == pLoopAdapter) - pEntry = AsocEntry_EnumStation(pLoopAdapter, i); + if (GetDefaultAdapter(p_loop_adapter) == p_loop_adapter) + p_entry = AsocEntry_EnumStation(p_loop_adapter, i); } - if (pEntry != NULL) { - if (pEntry->bAssociated) { + if (p_entry != NULL) { + if (p_entry->bAssociated) { - RT_DISP_ADDR(FDM, DM_PWDB, ("pEntry->MacAddr ="), pEntry->MacAddr); - RT_DISP(FDM, DM_PWDB, ("pEntry->rssi = 0x%x(%d)\n", - pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); + RT_DISP_ADDR(FDM, DM_PWDB, ("p_entry->mac_addr ="), p_entry->MacAddr); + RT_DISP(FDM, DM_PWDB, ("p_entry->rssi = 0x%x(%d)\n", + p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_stat.undecorated_smoothed_pwdb)); - //2 BF_en + /* 2 BF_en */ #if (BEAMFORMING_SUPPORT == 1) #ifndef BEAMFORMING_VERSION_1 - Beamform_cap = phydm_Beamforming_GetEntryBeamCapByMacId(pDM_Odm, pEntry->AssociatedMacId); - if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) - TxBF_EN = 1; + beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(p_dm_odm, p_entry->AssociatedMacId); + if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + tx_bf_en = 1; #else - if(Beamform_GetSupportBeamformerCap(GetDefaultAdapter(Adapter), pEntry)) - TxBF_EN = 1; + if (Beamform_GetSupportBeamformerCap(GetDefaultAdapter(adapter), p_entry)) + tx_bf_en = 1; #endif #endif - //2 STBC_en - if ((IS_WIRELESS_MODE_AC(Adapter) && TEST_FLAG(pEntry->VHTInfo.STBC, STBC_VHT_ENABLE_TX)) || - TEST_FLAG(pEntry->HTInfo.STBC, STBC_HT_ENABLE_TX)) + /* 2 STBC_en */ + if ((IS_WIRELESS_MODE_AC(adapter) && TEST_FLAG(p_entry->VHTInfo.STBC, STBC_VHT_ENABLE_TX)) || + TEST_FLAG(p_entry->HTInfo.STBC, STBC_HT_ENABLE_TX)) stbc_en = 1; - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) - tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) - tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + if (p_entry->rssi_stat.undecorated_smoothed_pwdb < tmp_entry_min_pwdb) + tmp_entry_min_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; + if (p_entry->rssi_stat.undecorated_smoothed_pwdb > tmp_entry_max_pwdb) + tmp_entry_max_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - H2C_Parameter[4] = (pRA_Table->RA_threshold_offset & 0x7f) | (pRA_Table->RA_offset_direction<<8); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((pRA_Table->RA_threshold_offset == 0) ? " " : ((pRA_Table->RA_offset_direction) ? "+" : "-")),pRA_Table->RA_threshold_offset)); + h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); - if (bExtRAInfo) { - if (curRxOkCnt > (curTxOkCnt * 6)) - H2C_Parameter[3] |= RAINFO_BE_RX_STATE; + if (is_ext_ra_info) { + if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6)) + h2c_parameter[3] |= RAINFO_BE_RX_STATE; - if (TxBF_EN) - H2C_Parameter[3] |= RAINFO_BF_STATE; + if (tx_bf_en) + h2c_parameter[3] |= RAINFO_BF_STATE; else { if (stbc_en) - H2C_Parameter[3] |= RAINFO_STBC_STATE; + h2c_parameter[3] |= RAINFO_STBC_STATE; } - if (pDM_Odm->NoisyDecision) - H2C_Parameter[3] |= RAINFO_NOISY_STATE; + if (p_dm_odm->noisy_decision) + h2c_parameter[3] |= RAINFO_NOISY_STATE; else - H2C_Parameter[3] &= (~RAINFO_NOISY_STATE); - #if 1 - if (pDM_Odm->H2C_RARpt_connect) { - H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("H2C_RARpt_connect = (( %d ))\n", pDM_Odm->H2C_RARpt_connect)); + h2c_parameter[3] &= (~RAINFO_NOISY_STATE); +#if 1 + if (p_dm_odm->h2c_rarpt_connect) { + h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("h2c_rarpt_connect = (( %d ))\n", p_dm_odm->h2c_rarpt_connect)); } - #else - - if (pEntry->rssi_stat.ra_rpt_linked == FALSE) { - H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - pEntry->rssi_stat.ra_rpt_linked = TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("RA First Link, RSSI[%d] = ((%d))\n", - pEntry->AssociatedMacId, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); +#else + + if (p_entry->rssi_stat.ra_rpt_linked == false) { + h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + p_entry->rssi_stat.ra_rpt_linked = true; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("RA First Link, RSSI[%d] = ((%d))\n", + p_entry->associated_mac_id, p_entry->rssi_stat.undecorated_smoothed_pwdb)); } - #endif +#endif } - H2C_Parameter[2] = (u1Byte)(pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0xFF); - //H2C_Parameter[1] = 0x20; // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 - H2C_Parameter[0] = (pEntry->AssociatedMacId); + h2c_parameter[2] = (u8)(p_entry->rssi_stat.undecorated_smoothed_pwdb & 0xFF); + /* h2c_parameter[1] = 0x20; */ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 */ + h2c_parameter[0] = (p_entry->AssociatedMacId); - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); } } else break; } - pLoopAdapter = GetNextExtAdapter(pLoopAdapter); + p_loop_adapter = GetNextExtAdapter(p_loop_adapter); } /*Default port*/ - if (tmpEntryMaxPWDB != 0) { // If associated entry is found - pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; - RT_DISP(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n", tmpEntryMaxPWDB, tmpEntryMaxPWDB)); + if (tmp_entry_max_pwdb != 0) { /* If associated entry is found */ + p_hal_data->EntryMaxUndecoratedSmoothedPWDB = tmp_entry_max_pwdb; + RT_DISP(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n", tmp_entry_max_pwdb, tmp_entry_max_pwdb)); } else - pHalData->EntryMaxUndecoratedSmoothedPWDB = 0; + p_hal_data->EntryMaxUndecoratedSmoothedPWDB = 0; - if (tmpEntryMinPWDB != 0xff) { // If associated entry is found - pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; - RT_DISP(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", tmpEntryMinPWDB, tmpEntryMinPWDB)); + if (tmp_entry_min_pwdb != 0xff) { /* If associated entry is found */ + p_hal_data->EntryMinUndecoratedSmoothedPWDB = tmp_entry_min_pwdb; + RT_DISP(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", tmp_entry_min_pwdb, tmp_entry_min_pwdb)); } else - pHalData->EntryMinUndecoratedSmoothedPWDB = 0; + p_hal_data->EntryMinUndecoratedSmoothedPWDB = 0; /* Default porti sent RSSI to FW */ - if (pHalData->bUseRAMask) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("1 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", - WIN_DEFAULT_PORT_MACID, pHalData->UndecoratedSmoothedPWDB, pHalData->ra_rpt_linked)); - if (pHalData->UndecoratedSmoothedPWDB > 0) { - - PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pDefaultMgntInfo); - PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pDefaultMgntInfo); + if (p_hal_data->bUseRAMask) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("1 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", + WIN_DEFAULT_PORT_MACID, p_hal_data->UndecoratedSmoothedPWDB, p_hal_data->ra_rpt_linked)); + if (p_hal_data->UndecoratedSmoothedPWDB > 0) { + + PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_default_mgnt_info); + PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_default_mgnt_info); /* BF_en*/ - #if (BEAMFORMING_SUPPORT == 1) - #ifndef BEAMFORMING_VERSION_1 - Beamform_cap = phydm_Beamforming_GetEntryBeamCapByMacId(pDM_Odm, pDefaultMgntInfo->mMacId); - - if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) - TxBF_EN = 1; - #else - if(Beamform_GetSupportBeamformerCap(GetDefaultAdapter(Adapter), NULL)) - TxBF_EN = 1; - #endif - #endif +#if (BEAMFORMING_SUPPORT == 1) +#ifndef BEAMFORMING_VERSION_1 + beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(p_dm_odm, p_default_mgnt_info->m_mac_id); + + if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + tx_bf_en = 1; +#else + if (Beamform_GetSupportBeamformerCap(GetDefaultAdapter(adapter), NULL)) + tx_bf_en = 1; +#endif +#endif /* STBC_en*/ - if ((IS_WIRELESS_MODE_AC(Adapter) && TEST_FLAG(pVHTInfo->VhtCurStbc, STBC_VHT_ENABLE_TX)) || - TEST_FLAG(pHTInfo->HtCurStbc, STBC_HT_ENABLE_TX)) + if ((IS_WIRELESS_MODE_AC(adapter) && TEST_FLAG(p_vht_info->VhtCurStbc, STBC_VHT_ENABLE_TX)) || + TEST_FLAG(p_ht_info->HtCurStbc, STBC_HT_ENABLE_TX)) stbc_en = 1; - H2C_Parameter[4] = (pRA_Table->RA_threshold_offset & 0x7f) | (pRA_Table->RA_offset_direction<<8); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((pRA_Table->RA_threshold_offset == 0) ? " " : ((pRA_Table->RA_offset_direction) ? "+" : "-")), pRA_Table->RA_threshold_offset)); + h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); - if (bExtRAInfo) { - if (TxBF_EN) - H2C_Parameter[3] |= RAINFO_BF_STATE; + if (is_ext_ra_info) { + if (tx_bf_en) + h2c_parameter[3] |= RAINFO_BF_STATE; else { if (stbc_en) - H2C_Parameter[3] |= RAINFO_STBC_STATE; + h2c_parameter[3] |= RAINFO_STBC_STATE; } - #if 1 - if (pDM_Odm->H2C_RARpt_connect) { - H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("H2C_RARpt_connect = (( %d ))\n", pDM_Odm->H2C_RARpt_connect)); +#if 1 + if (p_dm_odm->h2c_rarpt_connect) { + h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("h2c_rarpt_connect = (( %d ))\n", p_dm_odm->h2c_rarpt_connect)); } - #else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("2 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", - WIN_DEFAULT_PORT_MACID, pHalData->UndecoratedSmoothedPWDB, pHalData->ra_rpt_linked)); - - if (pHalData->ra_rpt_linked == FALSE) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("3 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", - WIN_DEFAULT_PORT_MACID, pHalData->UndecoratedSmoothedPWDB, pHalData->ra_rpt_linked)); - - H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - pHalData->ra_rpt_linked = TRUE; +#else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("2 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", + WIN_DEFAULT_PORT_MACID, p_hal_data->undecorated_smoothed_pwdb, p_hal_data->ra_rpt_linked)); + + if (p_hal_data->ra_rpt_linked == false) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("3 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", + WIN_DEFAULT_PORT_MACID, p_hal_data->undecorated_smoothed_pwdb, p_hal_data->ra_rpt_linked)); + + h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + p_hal_data->ra_rpt_linked = true; } - #endif - - if (pDM_Odm->NoisyDecision == 1) { - H2C_Parameter[3] |= RAINFO_NOISY_STATE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] Send H2C to FW\n")); +#endif + + if (p_dm_odm->noisy_decision == 1) { + h2c_parameter[3] |= RAINFO_NOISY_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] Send H2C to FW\n")); } else - H2C_Parameter[3] &= (~RAINFO_NOISY_STATE); + h2c_parameter[3] &= (~RAINFO_NOISY_STATE); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] H2C_Parameter=%x\n", H2C_Parameter[3])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] h2c_parameter=%x\n", h2c_parameter[3])); } - H2C_Parameter[2] = (u1Byte)(pHalData->UndecoratedSmoothedPWDB & 0xFF); - /*H2C_Parameter[1] = 0x20;*/ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ - H2C_Parameter[0] = WIN_DEFAULT_PORT_MACID; /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ + h2c_parameter[2] = (u8)(p_hal_data->UndecoratedSmoothedPWDB & 0xFF); + /*h2c_parameter[1] = 0x20;*/ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ + h2c_parameter[0] = WIN_DEFAULT_PORT_MACID; /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); } - - // BT 3.0 HS mode Rssi - if (pDM_Odm->bBtHsOperation) { - H2C_Parameter[2] = pDM_Odm->btHsRssi; - //H2C_Parameter[1] = 0x0; - H2C_Parameter[0] = WIN_BT_PORT_MACID; - - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + + /* BT 3.0 HS mode rssi */ + if (p_dm_odm->is_bt_hs_operation) { + h2c_parameter[2] = p_dm_odm->bt_hs_rssi; + /* h2c_parameter[1] = 0x0; */ + h2c_parameter[0] = WIN_BT_PORT_MACID; + + odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); } } else - PlatformEFIOWrite1Byte(Adapter, 0x4fe, (u1Byte)pHalData->UndecoratedSmoothedPWDB); + PlatformEFIOWrite1Byte(adapter, 0x4fe, (u8)p_hal_data->UndecoratedSmoothedPWDB); - if ((pDM_Odm->SupportICType == ODM_RTL8812) || (pDM_Odm->SupportICType == ODM_RTL8192E)) - odm_RSSIDumpToRegister(pDM_Odm); + if ((p_dm_odm->support_ic_type == ODM_RTL8812) || (p_dm_odm->support_ic_type == ODM_RTL8192E)) + odm_rssi_dump_to_register(p_dm_odm); { - PADAPTER pLoopAdapter = GetDefaultAdapter(Adapter); - BOOLEAN default_pointer_value, *pbLink_temp = &default_pointer_value; - s4Byte GlobalRSSI_min = 0xFF, LocalRSSI_Min; - BOOLEAN bLink = FALSE; - - while (pLoopAdapter) { - LocalRSSI_Min = phydm_FindMinimumRSSI(pDM_Odm, pLoopAdapter, pbLink_temp); - //DbgPrint("pHalData->bLinked=%d, LocalRSSI_Min=%d\n", pHalData->bLinked, LocalRSSI_Min); - - if (*pbLink_temp) - bLink = TRUE; - - if ((LocalRSSI_Min < GlobalRSSI_min) && (*pbLink_temp)) - GlobalRSSI_min = LocalRSSI_Min; - - pLoopAdapter = GetNextExtAdapter(pLoopAdapter); + struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(adapter); + boolean default_pointer_value, *p_is_link_temp = &default_pointer_value; + s32 global_rssi_min = 0xFF, local_rssi_min; + boolean is_link = false; + + while (p_loop_adapter) { + local_rssi_min = phydm_find_minimum_rssi(p_dm_odm, p_loop_adapter, p_is_link_temp); + /* dbg_print("p_hal_data->is_linked=%d, local_rssi_min=%d\n", p_hal_data->is_linked, local_rssi_min); */ + + if (*p_is_link_temp) + is_link = true; + + if ((local_rssi_min < global_rssi_min) && (*p_is_link_temp)) + global_rssi_min = local_rssi_min; + + p_loop_adapter = GetNextExtAdapter(p_loop_adapter); } - pHalData->bLinked = bLink; - ODM_CmnInfoUpdate(&pHalData->DM_OutSrc , ODM_CMNINFO_LINK, (u8Byte)bLink); + p_hal_data->bLinked = is_link; + odm_cmn_info_update(&p_hal_data->DM_OutSrc, ODM_CMNINFO_LINK, (u64)is_link); - if (bLink) - ODM_CmnInfoUpdate(&pHalData->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, (u8Byte)GlobalRSSI_min); + if (is_link) + odm_cmn_info_update(&p_hal_data->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, (u64)global_rssi_min); else - ODM_CmnInfoUpdate(&pHalData->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, 0); + odm_cmn_info_update(&p_hal_data->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, 0); } -#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ } -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && !defined(DM_ODM_CE_MAC80211) /*H2C_RSSI_REPORT*/ -s8 phydm_rssi_report(PDM_ODM_T pDM_Odm, u8 mac_id) +s8 phydm_rssi_report(struct PHY_DM_STRUCT *p_dm_odm, u8 mac_id) { - PADAPTER Adapter = pDM_Odm->Adapter; - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 H2C_Parameter[4] = {0}; - u8 UL_DL_STATE = 0, STBC_TX = 0, TxBF_EN = 0; - u8 cmdlen = 4, first_connect = _FALSE; - u64 curTxOkCnt = 0, curRxOkCnt = 0; - PSTA_INFO_T pEntry = pDM_Odm->pODM_StaInfo[mac_id]; - - if (!IS_STA_VALID(pEntry)) + struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter); + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; + u8 UL_DL_STATE = 0, STBC_TX = 0, tx_bf_en = 0; + u8 cmdlen = H2C_0X42_LENGTH, first_connect = _FALSE; + u64 cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0; + struct sta_info *p_entry = p_dm_odm->p_odm_sta_info[mac_id]; + + if (!IS_STA_VALID(p_entry)) return _FAIL; - if (mac_id != pEntry->mac_id) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u:%u invalid\n", __func__, mac_id, pEntry->mac_id)); + if (mac_id != p_entry->mac_id) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u:%u invalid\n", __func__, mac_id, p_entry->mac_id)); rtw_warn_on(1); return _FAIL; - } - - if (IS_MCAST(pEntry->hwaddr)) /*if(psta->mac_id ==1)*/ + } + + if (IS_MCAST(p_entry->hwaddr)) /*if(psta->mac_id ==1)*/ + return _FAIL; + + if (p_dm_odm->is_in_lps_pg) return _FAIL; - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == (-1)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi == -1\n", __func__, pEntry->mac_id, MAC_ARG(pEntry->hwaddr))); + if (p_entry->rssi_stat.undecorated_smoothed_pwdb == (-1)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi == -1\n", __func__, p_entry->mac_id, MAC_ARG(p_entry->hwaddr))); return _FAIL; } - curTxOkCnt = pdvobjpriv->traffic_stat.cur_tx_bytes; - curRxOkCnt = pdvobjpriv->traffic_stat.cur_rx_bytes; - if (curRxOkCnt > (curTxOkCnt * 6)) + cur_tx_ok_cnt = pdvobjpriv->traffic_stat.cur_tx_bytes; + cur_rx_ok_cnt = pdvobjpriv->traffic_stat.cur_rx_bytes; + if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6)) UL_DL_STATE = 1; else UL_DL_STATE = 0; - - #ifdef CONFIG_BEAMFORMING + +#ifdef CONFIG_BEAMFORMING { - #if (BEAMFORMING_SUPPORT == 1) - BEAMFORMING_CAP Beamform_cap = phydm_Beamforming_GetEntryBeamCapByMacId(pDM_Odm, pEntry->mac_id); - #else/*for drv beamforming*/ - BEAMFORMING_CAP Beamform_cap = beamforming_get_entry_beam_cap_by_mac_id(&Adapter->mlmepriv, pEntry->mac_id); - #endif - - if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) - TxBF_EN = 1; +#if (BEAMFORMING_SUPPORT == 1) + enum beamforming_cap beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(p_dm_odm, p_entry->mac_id); +#else/*for drv beamforming*/ + enum beamforming_cap beamform_cap = beamforming_get_entry_beam_cap_by_mac_id(&adapter->mlmepriv, p_entry->mac_id); +#endif + + if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + tx_bf_en = 1; else - TxBF_EN = 0; + tx_bf_en = 0; } - #endif /*#ifdef CONFIG_BEAMFORMING*/ - - if (TxBF_EN) +#endif /*#ifdef CONFIG_BEAMFORMING*/ + + if (tx_bf_en) STBC_TX = 0; else { - #ifdef CONFIG_80211AC_VHT - if (IsSupportedVHT(pEntry->wireless_mode)) - STBC_TX = TEST_FLAG(pEntry->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX); +#ifdef CONFIG_80211AC_VHT + if (is_supported_vht(p_entry->wireless_mode)) + STBC_TX = TEST_FLAG(p_entry->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX); else - #endif - STBC_TX = TEST_FLAG(pEntry->htpriv.stbc_cap, STBC_HT_ENABLE_TX); +#endif +#ifdef CONFIG_80211N_HT + STBC_TX = TEST_FLAG(p_entry->htpriv.stbc_cap, STBC_HT_ENABLE_TX); +#endif } - - H2C_Parameter[0] = (u8)(pEntry->mac_id & 0xFF); - H2C_Parameter[2] = pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0x7F; - + + h2c_parameter[0] = (u8)(p_entry->mac_id & 0xFF); + h2c_parameter[2] = p_entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F; + if (UL_DL_STATE) - H2C_Parameter[3] |= RAINFO_BE_RX_STATE; - - if (TxBF_EN) - H2C_Parameter[3] |= RAINFO_BF_STATE; + h2c_parameter[3] |= RAINFO_BE_RX_STATE; + + if (tx_bf_en) + h2c_parameter[3] |= RAINFO_BF_STATE; if (STBC_TX) - H2C_Parameter[3] |= RAINFO_STBC_STATE; - if (pDM_Odm->NoisyDecision) - H2C_Parameter[3] |= RAINFO_NOISY_STATE; - - if ((pEntry->ra_rpt_linked == _FALSE) && (pEntry->rssi_stat.bsend_rssi == RA_RSSI_STATE_SEND)) { - H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - pEntry->ra_rpt_linked = _TRUE; - pEntry->rssi_stat.bsend_rssi = RA_RSSI_STATE_HOLD; + h2c_parameter[3] |= RAINFO_STBC_STATE; + if (p_dm_odm->noisy_decision) + h2c_parameter[3] |= RAINFO_NOISY_STATE; + + if ((p_entry->ra_rpt_linked == _FALSE) && (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_SEND)) { + h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + p_entry->ra_rpt_linked = _TRUE; + p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_HOLD; first_connect = _TRUE; } - - #if 1 + + h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); + +#if 1 if (first_connect) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__, - pEntry->mac_id, MAC_ARG(pEntry->hwaddr), pEntry->rssi_stat.UndecoratedSmoothedPWDB)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s RAINFO - TP:%s, TxBF:%s, STBC:%s, Noisy:%s, Firstcont:%s\n", __func__, - (UL_DL_STATE) ? "DL" : "UL", (TxBF_EN) ? "EN" : "DIS", (STBC_TX) ? "EN" : "DIS", - (pDM_Odm->NoisyDecision) ? "True" : "False", (first_connect) ? "True" : "False")); - } - #endif - - if (pHalData->fw_ractrl == _TRUE) { - #if (RTL8188E_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8188E) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__, + p_entry->mac_id, MAC_ARG(p_entry->hwaddr), p_entry->rssi_stat.undecorated_smoothed_pwdb)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s RAINFO - TP:%s, TxBF:%s, STBC:%s, Noisy:%s, Firstcont:%s\n", __func__, + (UL_DL_STATE) ? "DL" : "UL", (tx_bf_en) ? "EN" : "DIS", (STBC_TX) ? "EN" : "DIS", + (p_dm_odm->noisy_decision) ? "True" : "False", (first_connect) ? "True" : "False")); + } +#endif + + if (p_hal_data->fw_ractrl == _TRUE) { +#if (RTL8188E_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8188E) cmdlen = 3; - #endif - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); +#endif + odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); } else { - #if ((RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)) - if (pDM_Odm->SupportICType == ODM_RTL8188E) - ODM_RA_SetRSSI_8188E(pDM_Odm, (u8)(pEntry->mac_id & 0xFF), pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0x7F); - #endif +#if ((RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)) + if (p_dm_odm->support_ic_type == ODM_RTL8188E) + odm_ra_set_rssi_8188e(p_dm_odm, (u8)(p_entry->mac_id & 0xFF), p_entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F); +#endif } return _SUCCESS; } -void phydm_ra_rssi_rpt_wk_hdl(PVOID pContext) +void phydm_ra_rssi_rpt_wk_hdl(void *p_context) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pContext; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_context; int i; u8 mac_id = 0xFF; - PSTA_INFO_T pEntry = NULL; - + struct sta_info *p_entry = NULL; + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - pEntry = pDM_Odm->pODM_StaInfo[i]; - if (IS_STA_VALID(pEntry)) { - if (IS_MCAST(pEntry->hwaddr)) /*if(psta->mac_id ==1)*/ + p_entry = p_dm_odm->p_odm_sta_info[i]; + if (IS_STA_VALID(p_entry)) { + if (IS_MCAST(p_entry->hwaddr)) /*if(psta->mac_id ==1)*/ continue; - if (pEntry->ra_rpt_linked == _FALSE) { + if (p_entry->ra_rpt_linked == _FALSE) { mac_id = i; break; } } } if (mac_id != 0xFF) - phydm_rssi_report(pDM_Odm, mac_id); + phydm_rssi_report(p_dm_odm, mac_id); } -void phydm_ra_rssi_rpt_wk(PVOID pContext) +void phydm_ra_rssi_rpt_wk(void *p_context) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pContext; - - rtw_run_in_thread_cmd(pDM_Odm->Adapter, phydm_ra_rssi_rpt_wk_hdl, pDM_Odm); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_context; + + rtw_run_in_thread_cmd(p_dm_odm->adapter, phydm_ra_rssi_rpt_wk_hdl, p_dm_odm); } #endif -VOID -odm_RSSIMonitorCheckCE( - IN PVOID pDM_VOID +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +void +odm_rssi_monitor_check_ce( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_mac *mac = rtl_mac(rtlpriv); + struct rtl_sta_info *p_entry; + int i; + int tmp_entry_min_pwdb = 0xff; + unsigned long cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0; + u8 UL_DL_STATE = 0, STBC_TX = 0, tx_bf_en = 0; + u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; + u8 cmdlen = H2C_0X42_LENGTH; + u8 macid = 0; + + if (p_dm_odm->is_linked != _TRUE) + return; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + p_entry = (struct rtl_sta_info *)p_dm_odm->p_odm_sta_info[i]; + if (!IS_STA_VALID(p_entry)) + continue; + + if (is_multicast_ether_addr(p_entry->mac_addr) || + is_broadcast_ether_addr(p_entry->mac_addr)) + continue; + + if (p_entry->rssi_stat.undecorated_smoothed_pwdb == (-1)) + continue; + + /* calculate min_pwdb */ + if (p_entry->rssi_stat.undecorated_smoothed_pwdb < tmp_entry_min_pwdb) + tmp_entry_min_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; + + /* report RSSI */ + cur_tx_ok_cnt = rtlpriv->stats.txbytesunicast_inperiod; + cur_rx_ok_cnt = rtlpriv->stats.rxbytesunicast_inperiod; + + if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6)) + UL_DL_STATE = 1; + else + UL_DL_STATE = 0; + + if (mac->opmode == NL80211_IFTYPE_AP || + mac->opmode == NL80211_IFTYPE_ADHOC) { + struct ieee80211_sta *sta = + container_of((void *)p_entry, struct ieee80211_sta, drv_priv); + macid = sta->aid + 1; + } + + h2c_parameter[0] = macid; + h2c_parameter[2] = p_entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F; + + if (UL_DL_STATE) + h2c_parameter[3] |= RAINFO_BE_RX_STATE; + + if (tx_bf_en) + h2c_parameter[3] |= RAINFO_BF_STATE; + if (STBC_TX) + h2c_parameter[3] |= RAINFO_STBC_STATE; + if (p_dm_odm->noisy_decision) + h2c_parameter[3] |= RAINFO_NOISY_STATE; + + if (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_SEND) { + h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_HOLD; + } + + h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); + + odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); + } + + if (tmp_entry_min_pwdb != 0xff) + p_dm_odm->rssi_min = tmp_entry_min_pwdb; +} +#else +void +odm_rssi_monitor_check_ce( + void *p_dm_void ) { #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PSTA_INFO_T pEntry; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct sta_info *p_entry; int i; - int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; + int tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff; u8 sta_cnt = 0; - - if (pDM_Odm->bLinked != _TRUE) - return; + + if (p_dm_odm->is_linked != _TRUE) + return; for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - pEntry = pDM_Odm->pODM_StaInfo[i]; - if (IS_STA_VALID(pEntry)) { - if (IS_MCAST(pEntry->hwaddr)) /*if(psta->mac_id ==1)*/ + p_entry = p_dm_odm->p_odm_sta_info[i]; + if (IS_STA_VALID(p_entry)) { + if (IS_MCAST(p_entry->hwaddr)) /*if(psta->mac_id ==1)*/ continue; - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == (-1)) + if (p_entry->rssi_stat.undecorated_smoothed_pwdb == (-1)) continue; - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) - tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + if (p_entry->rssi_stat.undecorated_smoothed_pwdb < tmp_entry_min_pwdb) + tmp_entry_min_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) - tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + if (p_entry->rssi_stat.undecorated_smoothed_pwdb > tmp_entry_max_pwdb) + tmp_entry_max_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - if (phydm_rssi_report(pDM_Odm, i)) + if (phydm_rssi_report(p_dm_odm, i)) sta_cnt++; } } - if (tmpEntryMaxPWDB != 0) // If associated entry is found - pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; + if (tmp_entry_max_pwdb != 0) /* If associated entry is found */ + p_hal_data->entry_max_undecorated_smoothed_pwdb = tmp_entry_max_pwdb; else - pHalData->EntryMaxUndecoratedSmoothedPWDB = 0; + p_hal_data->entry_max_undecorated_smoothed_pwdb = 0; - if (tmpEntryMinPWDB != 0xff) // If associated entry is found - pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; + if (tmp_entry_min_pwdb != 0xff) /* If associated entry is found */ + p_hal_data->entry_min_undecorated_smoothed_pwdb = tmp_entry_min_pwdb; else - pHalData->EntryMinUndecoratedSmoothedPWDB = 0; + p_hal_data->entry_min_undecorated_smoothed_pwdb = 0; - FindMinimumRSSI(Adapter);//get pdmpriv->MinUndecoratedPWDBForDM + find_minimum_rssi(adapter);/* get pdmpriv->min_undecorated_pwdb_for_dm */ - pDM_Odm->RSSI_Min = pHalData->MinUndecoratedPWDBForDM; - //ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); -#endif//if (DM_ODM_SUPPORT_TYPE == ODM_CE) + p_dm_odm->rssi_min = p_hal_data->min_undecorated_pwdb_for_dm; + /* odm_cmn_info_update(&p_hal_data->odmpriv,ODM_CMNINFO_RSSI_MIN, pdmpriv->min_undecorated_pwdb_for_dm); */ +#endif/* if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ } +#endif -VOID -odm_RSSIMonitorCheckAP( - IN PVOID pDM_VOID +void +odm_rssi_monitor_check_ap( + void *p_dm_void ) { #if (DM_ODM_SUPPORT_TYPE == ODM_AP) #if (RTL8812A_SUPPORT || RTL8881A_SUPPORT || RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8197F_SUPPORT) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte H2C_Parameter[H2C_0X42_LENGTH] = {0}; - u4Byte i; - BOOLEAN bExtRAInfo = TRUE; - u1Byte cmdlen = H2C_0X42_LENGTH; - u1Byte TxBF_EN = 0, stbc_en = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; + u32 i; + boolean is_ext_ra_info = true; + u8 cmdlen = H2C_0X42_LENGTH; + u8 tx_bf_en = 0, stbc_en = 0; - prtl8192cd_priv priv = pDM_Odm->priv; - PSTA_INFO_T pstat; - BOOLEAN act_bfer = FALSE; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct sta_info *pstat; + boolean act_bfer = false; #if (BEAMFORMING_SUPPORT == 1) - u1Byte Idx=0xff; + u8 idx = 0xff; #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; - pDM_BdcTable->num_Txbfee_Client = 0; - pDM_BdcTable->num_Txbfer_Client = 0; + struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; + p_dm_bdc_table->num_txbfee_client = 0; + p_dm_bdc_table->num_txbfer_client = 0; #endif #endif - if (!pDM_Odm->H2C_RARpt_connect && (priv->up_time % 2)) + if (!p_dm_odm->h2c_rarpt_connect && (priv->up_time % 2)) return; - if (pDM_Odm->SupportICType == ODM_RTL8188E) { - bExtRAInfo = FALSE; + if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + is_ext_ra_info = false; cmdlen = 3; } for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - pstat = pDM_Odm->pODM_StaInfo[i]; + pstat = p_dm_odm->p_odm_sta_info[i]; if (IS_STA_VALID(pstat)) { if (pstat->sta_in_firmware != 1) continue; - //2 BF_en - #if (BEAMFORMING_SUPPORT == 1) - BEAMFORMING_CAP Beamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, pstat->aid); - PRT_BEAMFORMING_ENTRY pEntry = Beamforming_GetEntryByMacId(priv, pstat->aid, &Idx); + /* 2 BF_en */ +#if (BEAMFORMING_SUPPORT == 1) + BEAMFORMING_CAP beamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, pstat->aid); + PRT_BEAMFORMING_ENTRY p_entry = Beamforming_GetEntryByMacId(priv, pstat->aid, &idx); - if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { - - if (pEntry->Sounding_En) - TxBF_EN = 1; + if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { + + if (p_entry->Sounding_En) + tx_bf_en = 1; else - TxBF_EN = 0; - - act_bfer = TRUE; + tx_bf_en = 0; + + act_bfer = true; } - #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*BDC*/ - if (act_bfer == TRUE) { - pDM_BdcTable->w_BFee_Client[i] = 1; //AP act as BFer - pDM_BdcTable->num_Txbfee_Client++; +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*BDC*/ + if (act_bfer == true) { + p_dm_bdc_table->w_bfee_client[i] = 1; /* AP act as BFer */ + p_dm_bdc_table->num_txbfee_client++; } else { - pDM_BdcTable->w_BFee_Client[i] = 0; //AP act as BFer + p_dm_bdc_table->w_bfee_client[i] = 0; /* AP act as BFer */ } - if ((Beamform_cap & BEAMFORMEE_CAP_HT_EXPLICIT) || (Beamform_cap & BEAMFORMEE_CAP_VHT_SU)) { - pDM_BdcTable->w_BFer_Client[i] = 1; //AP act as BFee - pDM_BdcTable->num_Txbfer_Client++; + if ((beamform_cap & BEAMFORMEE_CAP_HT_EXPLICIT) || (beamform_cap & BEAMFORMEE_CAP_VHT_SU)) { + p_dm_bdc_table->w_bfer_client[i] = 1; /* AP act as BFee */ + p_dm_bdc_table->num_txbfer_client++; } else { - pDM_BdcTable->w_BFer_Client[i] = 0; //AP act as BFer + p_dm_bdc_table->w_bfer_client[i] = 0; /* AP act as BFer */ } - #endif - #endif +#endif +#endif - //2 STBC_en + /* 2 STBC_en */ if ((priv->pmib->dot11nConfigEntry.dot11nSTBC) && - ((pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_RX_STBC_CAP_)) - #ifdef RTK_AC_SUPPORT - || (pstat->vht_cap_buf.vht_cap_info & cpu_to_le32(_VHTCAP_RX_STBC_CAP_)) - #endif - )) + ((pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_RX_STBC_CAP_)) +#ifdef RTK_AC_SUPPORT + || (pstat->vht_cap_buf.vht_cap_info & cpu_to_le32(_VHTCAP_RX_STBC_CAP_)) +#endif + )) stbc_en = 1; - //2 RAINFO + /* 2 RAINFO */ + + h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); - if (bExtRAInfo) { + if (is_ext_ra_info) { if ((pstat->rx_avarage) > ((pstat->tx_avarage) * 6)) - H2C_Parameter[3] |= RAINFO_BE_RX_STATE; + h2c_parameter[3] |= RAINFO_BE_RX_STATE; - if (TxBF_EN) - H2C_Parameter[3] |= RAINFO_BF_STATE; + if (tx_bf_en) + h2c_parameter[3] |= RAINFO_BF_STATE; else { if (stbc_en) - H2C_Parameter[3] |= RAINFO_STBC_STATE; + h2c_parameter[3] |= RAINFO_STBC_STATE; } - if (pDM_Odm->NoisyDecision) - H2C_Parameter[3] |= RAINFO_NOISY_STATE; + if (p_dm_odm->noisy_decision) + h2c_parameter[3] |= RAINFO_NOISY_STATE; else - H2C_Parameter[3] &= (~RAINFO_NOISY_STATE); - + h2c_parameter[3] &= (~RAINFO_NOISY_STATE); + if (pstat->H2C_rssi_rpt) { - H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[RA Init] set Init rate by RSSI, STA %d\n", pstat->aid)); + h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[RA Init] set Init rate by RSSI, STA %d\n", pstat->aid)); } - /*ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RAINFO] H2C_Para[3] = %x\n",H2C_Parameter[3]));*/ + /*ODM_RT_TRACE(p_dm_odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RAINFO] H2C_Para[3] = %x\n",h2c_parameter[3]));*/ } - H2C_Parameter[2] = (u1Byte)(pstat->rssi & 0xFF); - H2C_Parameter[0] = REMAP_AID(pstat); + h2c_parameter[2] = (u8)(pstat->rssi & 0xFF); + h2c_parameter[0] = REMAP_AID(pstat); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("H2C_Parameter[3]=%d\n", H2C_Parameter[3])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("h2c_parameter[3]=%d\n", h2c_parameter[3])); - //ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RSSI] H2C_Para[2] = %x, \n",H2C_Parameter[2])); - //ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[MACID] H2C_Para[0] = %x, \n",H2C_Parameter[0])); + /* ODM_RT_TRACE(p_dm_odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RSSI] H2C_Para[2] = %x,\n",h2c_parameter[2])); */ + /* ODM_RT_TRACE(p_dm_odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[MACID] H2C_Para[0] = %x,\n",h2c_parameter[0])); */ - ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); } } @@ -1395,27 +1525,27 @@ odm_RSSIMonitorCheckAP( } -VOID -odm_RSSIMonitorCheck( - IN PVOID pDM_VOID +void +odm_rssi_monitor_check( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (!(p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR)) return; - switch (pDM_Odm->SupportPlatform) { + switch (p_dm_odm->support_platform) { case ODM_WIN: - odm_RSSIMonitorCheckMP(pDM_Odm); + odm_rssi_monitor_check_mp(p_dm_odm); break; case ODM_CE: - odm_RSSIMonitorCheckCE(pDM_Odm); + odm_rssi_monitor_check_ce(p_dm_odm); break; case ODM_AP: - odm_RSSIMonitorCheckAP(pDM_Odm); + odm_rssi_monitor_check_ap(p_dm_odm); break; default: @@ -1424,62 +1554,62 @@ odm_RSSIMonitorCheck( } -VOID -odm_RateAdaptiveMaskInit( - IN PVOID pDM_VOID +void +odm_rate_adaptive_mask_init( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RATE_ADAPTIVE pOdmRA = &pDM_Odm->RateAdaptive; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ODM_RATE_ADAPTIVE *p_odm_ra = &p_dm_odm->rate_adaptive; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMGNT_INFO pMgntInfo = &pDM_Odm->Adapter->MgntInfo; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); + PMGNT_INFO p_mgnt_info = &p_dm_odm->adapter->MgntInfo; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); - pMgntInfo->Ratr_State = DM_RATR_STA_INIT; + p_mgnt_info->Ratr_State = DM_RATR_STA_INIT; - if (pMgntInfo->DM_Type == DM_Type_ByDriver) - pHalData->bUseRAMask = TRUE; + if (p_mgnt_info->DM_Type == dm_type_by_driver) + p_hal_data->bUseRAMask = true; else - pHalData->bUseRAMask = FALSE; + p_hal_data->bUseRAMask = false; #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - pOdmRA->Type = DM_Type_ByDriver; - if (pOdmRA->Type == DM_Type_ByDriver) - pDM_Odm->bUseRAMask = _TRUE; + p_odm_ra->type = dm_type_by_driver; + if (p_odm_ra->type == dm_type_by_driver) + p_dm_odm->is_use_ra_mask = _TRUE; else - pDM_Odm->bUseRAMask = _FALSE; + p_dm_odm->is_use_ra_mask = _FALSE; #endif - pOdmRA->RATRState = DM_RATR_STA_INIT; + p_odm_ra->ratr_state = DM_RATR_STA_INIT; -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (pDM_Odm->SupportICType == ODM_RTL8812) - pOdmRA->LdpcThres = 50; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (p_dm_odm->support_ic_type == ODM_RTL8812) + p_odm_ra->ldpc_thres = 50; else - pOdmRA->LdpcThres = 35; + p_odm_ra->ldpc_thres = 35; - pOdmRA->RtsThres = 35; + p_odm_ra->rts_thres = 35; -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - pOdmRA->LdpcThres = 35; - pOdmRA->bUseLdpc = FALSE; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + p_odm_ra->ldpc_thres = 35; + p_odm_ra->is_use_ldpc = false; #else - pOdmRA->UltraLowRSSIThresh = 9; + p_odm_ra->ultra_low_rssi_thresh = 9; #endif - pOdmRA->HighRSSIThresh = 50; + p_odm_ra->high_rssi_thresh = 50; #if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - pOdmRA->LowRSSIThresh = 23; + p_odm_ra->low_rssi_thresh = 23; #else - pOdmRA->LowRSSIThresh = 20; + p_odm_ra->low_rssi_thresh = 20; #endif } /*----------------------------------------------------------------------------- - * Function: odm_RefreshRateAdaptiveMask() + * Function: odm_refresh_rate_adaptive_mask() * * Overview: Update rate table mask according to rssi * @@ -1491,931 +1621,1027 @@ odm_RateAdaptiveMaskInit( * * Revised History: * When Who Remark - * 05/27/2009 hpfan Create Version 0. + * 05/27/2009 hpfan Create version 0. * *---------------------------------------------------------------------------*/ -VOID -odm_RefreshRateAdaptiveMask( - IN PVOID pDM_VOID +void +odm_refresh_rate_adaptive_mask( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - if (!pDM_Odm->bLinked) + if (!p_dm_odm->is_linked) return; - - if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_RefreshRateAdaptiveMask(): Return cos not supported\n")); + + if (!(p_dm_odm->support_ability & ODM_BB_RA_MASK)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_refresh_rate_adaptive_mask(): Return cos not supported\n")); return; } - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // - switch (pDM_Odm->SupportPlatform) { + + p_ra_table->force_update_ra_mask_count++; + /* */ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ + /* */ + switch (p_dm_odm->support_platform) { case ODM_WIN: - odm_RefreshRateAdaptiveMaskMP(pDM_Odm); + odm_refresh_rate_adaptive_mask_mp(p_dm_odm); break; case ODM_CE: - odm_RefreshRateAdaptiveMaskCE(pDM_Odm); + odm_refresh_rate_adaptive_mask_ce(p_dm_odm); break; case ODM_AP: - odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm); + odm_refresh_rate_adaptive_mask_apadsl(p_dm_odm); break; } } -u1Byte +u8 phydm_trans_platform_bw( - IN PVOID pDM_VOID, - IN u1Byte BW + void *p_dm_void, + u8 BW ) { - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (BW == CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == CHANNEL_WIDTH_40) - BW = PHYDM_BW_40; - - else if (BW == CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - - else if (BW == CHANNEL_WIDTH_160) - BW = PHYDM_BW_160; - - else if (BW == CHANNEL_WIDTH_80_80) - BW = PHYDM_BW_80_80; - - #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - if (BW == HT_CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == HT_CHANNEL_WIDTH_20_40) - BW = PHYDM_BW_40; - - else if (BW == HT_CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - - else if (BW == HT_CHANNEL_WIDTH_160) - BW = PHYDM_BW_160; - - else if (BW == HT_CHANNEL_WIDTH_10) - BW = PHYDM_BW_10; - - else if (BW == HT_CHANNEL_WIDTH_5) - BW = PHYDM_BW_5; - - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - if (BW == CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == CHANNEL_WIDTH_40) - BW = PHYDM_BW_40; - - else if (BW == CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - - else if (BW == CHANNEL_WIDTH_160) - BW = PHYDM_BW_160; - - else if (BW == CHANNEL_WIDTH_80_80) - BW = PHYDM_BW_80_80; - #endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (BW == CHANNEL_WIDTH_20) + BW = PHYDM_BW_20; + + else if (BW == CHANNEL_WIDTH_40) + BW = PHYDM_BW_40; + + else if (BW == CHANNEL_WIDTH_80) + BW = PHYDM_BW_80; + + else if (BW == CHANNEL_WIDTH_160) + BW = PHYDM_BW_160; + + else if (BW == CHANNEL_WIDTH_80_80) + BW = PHYDM_BW_80_80; + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + if (BW == HT_CHANNEL_WIDTH_20) + BW = PHYDM_BW_20; + + else if (BW == HT_CHANNEL_WIDTH_20_40) + BW = PHYDM_BW_40; + + else if (BW == HT_CHANNEL_WIDTH_80) + BW = PHYDM_BW_80; + + else if (BW == HT_CHANNEL_WIDTH_160) + BW = PHYDM_BW_160; + + else if (BW == HT_CHANNEL_WIDTH_10) + BW = PHYDM_BW_10; + + else if (BW == HT_CHANNEL_WIDTH_5) + BW = PHYDM_BW_5; + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + + if (BW == HT_CHANNEL_WIDTH_20) + BW = PHYDM_BW_20; + + else if (BW == HT_CHANNEL_WIDTH_20_40) + BW = PHYDM_BW_40; + + else if (BW == HT_CHANNEL_WIDTH_80) + BW = PHYDM_BW_80; + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + if (BW == CHANNEL_WIDTH_20) + BW = PHYDM_BW_20; + + else if (BW == CHANNEL_WIDTH_40) + BW = PHYDM_BW_40; + + else if (BW == CHANNEL_WIDTH_80) + BW = PHYDM_BW_80; + + else if (BW == CHANNEL_WIDTH_160) + BW = PHYDM_BW_160; + + else if (BW == CHANNEL_WIDTH_80_80) + BW = PHYDM_BW_80_80; +#endif return BW; } -u1Byte +u8 phydm_trans_platform_rf_type( - IN PVOID pDM_VOID, - IN u1Byte RfType + void *p_dm_void, + u8 rf_type ) { - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (RfType == RF_1T2R) - RfType = PHYDM_RF_1T2R; - - else if (RfType == RF_2T4R) - RfType = PHYDM_RF_2T4R; - - else if (RfType == RF_2T2R) - RfType = PHYDM_RF_2T2R; - - else if (RfType == RF_1T1R) - RfType = PHYDM_RF_1T1R; - - else if (RfType == RF_2T2R_GREEN) - RfType = PHYDM_RF_2T2R_GREEN; - - else if (RfType == RF_3T3R) - RfType = PHYDM_RF_3T3R; - - else if (RfType == RF_4T4R) - RfType = PHYDM_RF_4T4R; - - else if (RfType == RF_2T3R) - RfType = PHYDM_RF_1T2R; - - else if (RfType == RF_3T4R) - RfType = PHYDM_RF_3T4R; - - #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - if (RfType == MIMO_1T2R) - RfType = PHYDM_RF_1T2R; - - else if (RfType == MIMO_2T4R) - RfType = PHYDM_RF_2T4R; - - else if (RfType == MIMO_2T2R) - RfType = PHYDM_RF_2T2R; - - else if (RfType == MIMO_1T1R) - RfType = PHYDM_RF_1T1R; - - else if (RfType == MIMO_3T3R) - RfType = PHYDM_RF_3T3R; - - else if (RfType == MIMO_4T4R) - RfType = PHYDM_RF_4T4R; - - else if (RfType == MIMO_2T3R) - RfType = PHYDM_RF_1T2R; - - else if (RfType == MIMO_3T4R) - RfType = PHYDM_RF_3T4R; - - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - if (RfType == RF_1T2R) - RfType = PHYDM_RF_1T2R; - - else if (RfType == RF_2T4R) - RfType = PHYDM_RF_2T4R; - - else if (RfType == RF_2T2R) - RfType = PHYDM_RF_2T2R; - - else if (RfType == RF_1T1R) - RfType = PHYDM_RF_1T1R; - - else if (RfType == RF_2T2R_GREEN) - RfType = PHYDM_RF_2T2R_GREEN; - - else if (RfType == RF_3T3R) - RfType = PHYDM_RF_3T3R; - - else if (RfType == RF_4T4R) - RfType = PHYDM_RF_4T4R; - - else if (RfType == RF_2T3R) - RfType = PHYDM_RF_1T2R; - - else if (RfType == RF_3T4R) - RfType = PHYDM_RF_3T4R; - - #endif - - return RfType; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (rf_type == RF_1T2R) + rf_type = PHYDM_RF_1T2R; + + else if (rf_type == RF_2T4R) + rf_type = PHYDM_RF_2T4R; + + else if (rf_type == RF_2T2R) + rf_type = PHYDM_RF_2T2R; + + else if (rf_type == RF_1T1R) + rf_type = PHYDM_RF_1T1R; + + else if (rf_type == RF_2T2R_GREEN) + rf_type = PHYDM_RF_2T2R_GREEN; + + else if (rf_type == RF_3T3R) + rf_type = PHYDM_RF_3T3R; + + else if (rf_type == RF_4T4R) + rf_type = PHYDM_RF_4T4R; + + else if (rf_type == RF_2T3R) + rf_type = PHYDM_RF_1T2R; + + else if (rf_type == RF_3T4R) + rf_type = PHYDM_RF_3T4R; + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + if (rf_type == MIMO_1T2R) + rf_type = PHYDM_RF_1T2R; + + else if (rf_type == MIMO_2T4R) + rf_type = PHYDM_RF_2T4R; + + else if (rf_type == MIMO_2T2R) + rf_type = PHYDM_RF_2T2R; + + else if (rf_type == MIMO_1T1R) + rf_type = PHYDM_RF_1T1R; + + else if (rf_type == MIMO_3T3R) + rf_type = PHYDM_RF_3T3R; + + else if (rf_type == MIMO_4T4R) + rf_type = PHYDM_RF_4T4R; + + else if (rf_type == MIMO_2T3R) + rf_type = PHYDM_RF_1T2R; + + else if (rf_type == MIMO_3T4R) + rf_type = PHYDM_RF_3T4R; + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + if (rf_type == RF_1T2R) + rf_type = PHYDM_RF_1T2R; + + else if (rf_type == RF_2T4R) + rf_type = PHYDM_RF_2T4R; + + else if (rf_type == RF_2T2R) + rf_type = PHYDM_RF_2T2R; + + else if (rf_type == RF_1T1R) + rf_type = PHYDM_RF_1T1R; + + else if (rf_type == RF_2T2R_GREEN) + rf_type = PHYDM_RF_2T2R_GREEN; + + else if (rf_type == RF_3T3R) + rf_type = PHYDM_RF_3T3R; + + else if (rf_type == RF_4T4R) + rf_type = PHYDM_RF_4T4R; + + else if (rf_type == RF_2T3R) + rf_type = PHYDM_RF_1T2R; + + else if (rf_type == RF_3T4R) + rf_type = PHYDM_RF_3T4R; + +#endif + + return rf_type; } -u4Byte +u32 phydm_trans_platform_wireless_mode( - IN PVOID pDM_VOID, - IN u4Byte wireless_mode + void *p_dm_void, + u32 wireless_mode ) { - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - - #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (wireless_mode == WIRELESS_11A) - wireless_mode = PHYDM_WIRELESS_MODE_A; - - else if (wireless_mode == WIRELESS_11B) - wireless_mode = PHYDM_WIRELESS_MODE_B; - - else if ((wireless_mode == WIRELESS_11G) || (wireless_mode == WIRELESS_11BG)) - wireless_mode = PHYDM_WIRELESS_MODE_G; - - else if (wireless_mode == WIRELESS_AUTO) - wireless_mode = PHYDM_WIRELESS_MODE_AUTO; - - else if ((wireless_mode == WIRELESS_11_24N) || (wireless_mode == WIRELESS_11G_24N) || (wireless_mode == WIRELESS_11B_24N) || - (wireless_mode == WIRELESS_11BG_24N) || (wireless_mode == WIRELESS_MODE_24G) || (wireless_mode == WIRELESS_11ABGN) || (wireless_mode == WIRELESS_11AGN)) - wireless_mode = PHYDM_WIRELESS_MODE_N_24G; - - else if ((wireless_mode == WIRELESS_11_5N) || (wireless_mode == WIRELESS_11A_5N)) - wireless_mode = PHYDM_WIRELESS_MODE_N_5G; - - else if ((wireless_mode == WIRELESS_11AC) || (wireless_mode == WIRELESS_11_5AC) || (wireless_mode == WIRELESS_MODE_5G)) - wireless_mode = PHYDM_WIRELESS_MODE_AC_5G; - - else if (wireless_mode == WIRELESS_11_24AC) - wireless_mode = PHYDM_WIRELESS_MODE_AC_24G; - - else if (wireless_mode == WIRELESS_11AC) - wireless_mode = PHYDM_WIRELESS_MODE_AC_ONLY; - - else if (wireless_mode == WIRELESS_MODE_MAX) - wireless_mode = PHYDM_WIRELESS_MODE_MAX; - else - wireless_mode = PHYDM_WIRELESS_MODE_UNKNOWN; - #endif + wireless_mode = PHYDM_WIRELESS_MODE_A; + + else if (wireless_mode == WIRELESS_11B) + wireless_mode = PHYDM_WIRELESS_MODE_B; + + else if ((wireless_mode == WIRELESS_11G) || (wireless_mode == WIRELESS_11BG)) + wireless_mode = PHYDM_WIRELESS_MODE_G; + + else if (wireless_mode == WIRELESS_AUTO) + wireless_mode = PHYDM_WIRELESS_MODE_AUTO; + + else if ((wireless_mode == WIRELESS_11_24N) || (wireless_mode == WIRELESS_11G_24N) || (wireless_mode == WIRELESS_11B_24N) || + (wireless_mode == WIRELESS_11BG_24N) || (wireless_mode == WIRELESS_MODE_24G) || (wireless_mode == WIRELESS_11ABGN) || (wireless_mode == WIRELESS_11AGN)) + wireless_mode = PHYDM_WIRELESS_MODE_N_24G; + + else if ((wireless_mode == WIRELESS_11_5N) || (wireless_mode == WIRELESS_11A_5N)) + wireless_mode = PHYDM_WIRELESS_MODE_N_5G; + + else if ((wireless_mode == WIRELESS_11AC) || (wireless_mode == WIRELESS_11_5AC) || (wireless_mode == WIRELESS_MODE_5G)) + wireless_mode = PHYDM_WIRELESS_MODE_AC_5G; + + else if (wireless_mode == WIRELESS_11_24AC) + wireless_mode = PHYDM_WIRELESS_MODE_AC_24G; + + else if (wireless_mode == WIRELESS_11AC) + wireless_mode = PHYDM_WIRELESS_MODE_AC_ONLY; + + else if (wireless_mode == WIRELESS_MODE_MAX) + wireless_mode = PHYDM_WIRELESS_MODE_MAX; + else + wireless_mode = PHYDM_WIRELESS_MODE_UNKNOWN; +#endif return wireless_mode; } -u1Byte +u8 phydm_vht_en_mapping( - IN PVOID pDM_VOID, - IN u4Byte WirelessMode + void *p_dm_void, + u32 wireless_mode ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte vht_en_out = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 vht_en_out = 0; - if ((WirelessMode == PHYDM_WIRELESS_MODE_AC_5G) || - (WirelessMode == PHYDM_WIRELESS_MODE_AC_24G) || - (WirelessMode == PHYDM_WIRELESS_MODE_AC_ONLY) - ) { + if ((wireless_mode == PHYDM_WIRELESS_MODE_AC_5G) || + (wireless_mode == PHYDM_WIRELESS_MODE_AC_24G) || + (wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY) + ) { vht_en_out = 1; /**/ } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("WirelessMode= (( 0x%x )), VHT_EN= (( %d ))\n", WirelessMode, vht_en_out)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n", wireless_mode, vht_en_out)); return vht_en_out; } -u1Byte +u8 phydm_rate_id_mapping( - IN PVOID pDM_VOID, - IN u4Byte WirelessMode, - IN u1Byte RfType, - IN u1Byte bw + void *p_dm_void, + u32 wireless_mode, + u8 rf_type, + u8 bw ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte rate_id_idx = 0; - u1Byte phydm_BW; - u1Byte phydm_RfType; - - phydm_BW = phydm_trans_platform_bw(pDM_Odm, bw); - phydm_RfType = phydm_trans_platform_rf_type(pDM_Odm, RfType); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - WirelessMode = phydm_trans_platform_wireless_mode(pDM_Odm, WirelessMode); - #endif + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 rate_id_idx = 0; + u8 phydm_BW; + u8 phydm_rf_type; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wirelessMode= (( 0x%x )), RfType = (( 0x%x )), BW = (( 0x%x ))\n", - WirelessMode, phydm_RfType, phydm_BW)); + phydm_BW = phydm_trans_platform_bw(p_dm_odm, bw); + phydm_rf_type = phydm_trans_platform_rf_type(p_dm_odm, rf_type); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + wireless_mode = phydm_trans_platform_wireless_mode(p_dm_odm, wireless_mode); +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n", + wireless_mode, phydm_rf_type, phydm_BW)); + + + switch (wireless_mode) { - - switch (WirelessMode) { - case PHYDM_WIRELESS_MODE_N_24G: - { - - if (phydm_BW == PHYDM_BW_40) { - - if (phydm_RfType == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_BGN_40M_1SS; - else - rate_id_idx = PHYDM_BGN_40M_2SS; - - } else { - - if (phydm_RfType == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_BGN_20M_1SS; - else - rate_id_idx = PHYDM_BGN_20M_2SS; - } - } - break; - - case PHYDM_WIRELESS_MODE_N_5G: - { - if (phydm_RfType == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_GN_N1SS; + { + + if (phydm_BW == PHYDM_BW_40) { + + if (phydm_rf_type == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_BGN_40M_1SS; + else if (phydm_rf_type == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_BGN_40M_2SS; else - rate_id_idx = PHYDM_GN_N2SS; + rate_id_idx = PHYDM_ARFR5_N_3SS; + + } else { + + if (phydm_rf_type == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_BGN_20M_1SS; + else if (phydm_rf_type == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_BGN_20M_2SS; + else + rate_id_idx = PHYDM_ARFR5_N_3SS; } - - break; - + } + break; + + case PHYDM_WIRELESS_MODE_N_5G: + { + if (phydm_rf_type == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_GN_N1SS; + else if (phydm_rf_type == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_GN_N2SS; + else + rate_id_idx = PHYDM_ARFR5_N_3SS; + } + + break; + case PHYDM_WIRELESS_MODE_G: rate_id_idx = PHYDM_BG; break; - + case PHYDM_WIRELESS_MODE_A: rate_id_idx = PHYDM_G; - break; - + break; + case PHYDM_WIRELESS_MODE_B: rate_id_idx = PHYDM_B_20M; break; - - + + case PHYDM_WIRELESS_MODE_AC_5G: case PHYDM_WIRELESS_MODE_AC_ONLY: - { - if (phydm_RfType == PHYDM_RF_1T1R) + { + if (phydm_rf_type == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (phydm_rf_type == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else + rate_id_idx = PHYDM_ARFR4_AC_3SS; + } + break; + + case PHYDM_WIRELESS_MODE_AC_24G: + { + /*Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/ + if (phydm_BW >= PHYDM_BW_80) { + if (phydm_rf_type == PHYDM_RF_1T1R) rate_id_idx = PHYDM_ARFR1_AC_1SS; - else if (phydm_RfType == PHYDM_RF_2T2R) + else if (phydm_rf_type == PHYDM_RF_2T2R) rate_id_idx = PHYDM_ARFR0_AC_2SS; else rate_id_idx = PHYDM_ARFR4_AC_3SS; + } else { + + if (phydm_rf_type == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; + else if (phydm_rf_type == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; + else + rate_id_idx = PHYDM_ARFR4_AC_3SS; } - break; - - case PHYDM_WIRELESS_MODE_AC_24G: - { - if (phydm_BW >= PHYDM_BW_80) { - if (phydm_RfType == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_ARFR1_AC_1SS; - else if (phydm_RfType == PHYDM_RF_2T2R) - rate_id_idx = PHYDM_ARFR0_AC_2SS; - else - rate_id_idx = PHYDM_ARFR5_N_3SS; - } else { - - if (phydm_RfType == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; - else - rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; - } - } - break; - + } + break; + default: rate_id_idx = 0; break; } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA Rate ID = (( 0x%d ))\n", rate_id_idx)); - + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA rate ID = (( 0x%x ))\n", rate_id_idx)); + return rate_id_idx; } -VOID -phydm_UpdateHalRAMask( - IN PVOID pDM_VOID, - IN u4Byte wirelessMode, - IN u1Byte RfType, - IN u1Byte BW, - IN u1Byte MimoPs_enable, - IN u1Byte disable_cck_rate, - IN u4Byte *ratr_bitmap_msb_in, - IN u4Byte *ratr_bitmap_lsb_in, - IN u1Byte tx_rate_level - ) +void +phydm_update_hal_ra_mask( + void *p_dm_void, + u32 wireless_mode, + u8 rf_type, + u8 BW, + u8 mimo_ps_enable, + u8 disable_cck_rate, + u32 *ratr_bitmap_msb_in, + u32 *ratr_bitmap_lsb_in, + u8 tx_rate_level +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte mask_rate_threshold; - u1Byte phydm_RfType; - u1Byte phydm_BW; - u4Byte ratr_bitmap = *ratr_bitmap_lsb_in, ratr_bitmap_msb = *ratr_bitmap_msb_in; - /*PODM_RATE_ADAPTIVE pRA = &(pDM_Odm->RateAdaptive);*/ - - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - wirelessMode = phydm_trans_platform_wireless_mode(pDM_Odm, wirelessMode); - #endif - - phydm_RfType = phydm_trans_platform_rf_type(pDM_Odm, RfType); - phydm_BW = phydm_trans_platform_bw(pDM_Odm, BW); - - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("phydm_RfType = (( %x )), RfType = (( %x ))\n", phydm_RfType, RfType));*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Platfoem original RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap)); - - switch (wirelessMode) { - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 phydm_rf_type; + u8 phydm_BW; + u32 ratr_bitmap = *ratr_bitmap_lsb_in, ratr_bitmap_msb = *ratr_bitmap_msb_in; + /*struct _ODM_RATE_ADAPTIVE* p_ra = &(p_dm_odm->rate_adaptive);*/ + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + wireless_mode = phydm_trans_platform_wireless_mode(p_dm_odm, wireless_mode); +#endif + + phydm_rf_type = phydm_trans_platform_rf_type(p_dm_odm, rf_type); + phydm_BW = phydm_trans_platform_bw(p_dm_odm, BW); + + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type));*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Platfoem original RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap)); + + switch (wireless_mode) { + case PHYDM_WIRELESS_MODE_B: - { - ratr_bitmap &= 0x0000000f; - } - break; + { + ratr_bitmap &= 0x0000000f; + } + break; case PHYDM_WIRELESS_MODE_G: - { - ratr_bitmap &= 0x00000ff5; - } - break; - + { + ratr_bitmap &= 0x00000ff5; + } + break; + case PHYDM_WIRELESS_MODE_A: - { - ratr_bitmap &= 0x00000ff0; - } - break; - + { + ratr_bitmap &= 0x00000ff0; + } + break; + case PHYDM_WIRELESS_MODE_N_24G: case PHYDM_WIRELESS_MODE_N_5G: - { - if (MimoPs_enable) - phydm_RfType = PHYDM_RF_1T1R; - - if (phydm_RfType == PHYDM_RF_1T1R) { - - if (phydm_BW == PHYDM_BW_40) - ratr_bitmap &= 0x000ff015; - else - ratr_bitmap &= 0x000ff005; - } else if (phydm_RfType == PHYDM_RF_2T2R || phydm_RfType == PHYDM_RF_2T4R || phydm_RfType == PHYDM_RF_2T3R) { - - if (phydm_BW == PHYDM_BW_40) - ratr_bitmap &= 0x0ffff015; - else - ratr_bitmap &= 0x0ffff005; - } else { /*3T*/ - - ratr_bitmap &= 0xfffff015; - ratr_bitmap_msb &= 0xf; - } + { + if (mimo_ps_enable) + phydm_rf_type = PHYDM_RF_1T1R; + + if (phydm_rf_type == PHYDM_RF_1T1R) { + + if (phydm_BW == PHYDM_BW_40) + ratr_bitmap &= 0x000ff015; + else + ratr_bitmap &= 0x000ff005; + } else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) { + + if (phydm_BW == PHYDM_BW_40) + ratr_bitmap &= 0x0ffff015; + else + ratr_bitmap &= 0x0ffff005; + } else { /*3T*/ + + ratr_bitmap &= 0xfffff015; + ratr_bitmap_msb &= 0xf; } - break; + } + break; case PHYDM_WIRELESS_MODE_AC_24G: - { - if (phydm_RfType == PHYDM_RF_1T1R) - ratr_bitmap &= 0x003ff015; - else if (phydm_RfType == PHYDM_RF_2T2R || phydm_RfType == PHYDM_RF_2T4R || phydm_RfType == PHYDM_RF_2T3R) - ratr_bitmap &= 0xfffff015; - else {/*3T*/ - - ratr_bitmap &= 0xfffff010; - ratr_bitmap_msb &= 0x3ff; - } + { + if (phydm_rf_type == PHYDM_RF_1T1R) + ratr_bitmap &= 0x003ff015; + else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) + ratr_bitmap &= 0xfffff015; + else {/*3T*/ + + ratr_bitmap &= 0xfffff010; + ratr_bitmap_msb &= 0x3ff; + } - if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ - ratr_bitmap &= 0x7fdfffff; - ratr_bitmap_msb &= 0x1ff; - } + if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ + ratr_bitmap &= 0x7fdfffff; + ratr_bitmap_msb &= 0x1ff; } - break; + } + break; case PHYDM_WIRELESS_MODE_AC_5G: - { - if (phydm_RfType == PHYDM_RF_1T1R) - ratr_bitmap &= 0x003ff010; - else if (phydm_RfType == PHYDM_RF_2T2R || phydm_RfType == PHYDM_RF_2T4R || phydm_RfType == PHYDM_RF_2T3R) - ratr_bitmap &= 0xfffff010; - else {/*3T*/ - - ratr_bitmap &= 0xfffff010; - ratr_bitmap_msb &= 0x3ff; - } + { + if (phydm_rf_type == PHYDM_RF_1T1R) + ratr_bitmap &= 0x003ff010; + else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) + ratr_bitmap &= 0xfffff010; + else {/*3T*/ + + ratr_bitmap &= 0xfffff010; + ratr_bitmap_msb &= 0x3ff; + } - if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ - ratr_bitmap &= 0x7fdfffff; - ratr_bitmap_msb &= 0x1ff; - } + if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ + ratr_bitmap &= 0x7fdfffff; + ratr_bitmap_msb &= 0x1ff; } - break; + } + break; default: break; } - if (wirelessMode != PHYDM_WIRELESS_MODE_B) { - - if (tx_rate_level == 0) + if (wireless_mode != PHYDM_WIRELESS_MODE_B) { + + if (tx_rate_level == 0) ratr_bitmap &= 0xffffffff; - else if (tx_rate_level == 1) + else if (tx_rate_level == 1) ratr_bitmap &= 0xfffffff0; - else if (tx_rate_level == 2) + else if (tx_rate_level == 2) ratr_bitmap &= 0xffffefe0; - else if (tx_rate_level == 3) + else if (tx_rate_level == 3) ratr_bitmap &= 0xffffcfc0; - else if (tx_rate_level == 4) + else if (tx_rate_level == 4) ratr_bitmap &= 0xffff8f80; - else if (tx_rate_level >= 5) + else if (tx_rate_level >= 5) ratr_bitmap &= 0xffff0f00; - + } - + if (disable_cck_rate) ratr_bitmap &= 0xfffffff0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wirelessMode= (( 0x%x )), RfType = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%d ))\n", - wirelessMode, phydm_RfType, phydm_BW, MimoPs_enable, tx_rate_level)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n", + wireless_mode, phydm_rf_type, phydm_BW, mimo_ps_enable, tx_rate_level)); - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap));*/ + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap));*/ *ratr_bitmap_lsb_in = ratr_bitmap; *ratr_bitmap_msb_in = ratr_bitmap_msb; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Phydm modified RA Mask = (( 0x %x | %x ))\n", *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Phydm modified RA Mask = (( 0x %x | %x ))\n", *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in)); } -u1Byte +u8 phydm_RA_level_decision( - IN PVOID pDM_VOID, - IN u4Byte rssi, - IN u1Byte Ratr_State - ) + void *p_dm_void, + u32 rssi, + u8 ratr_state +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte ra_lowest_rate; - u1Byte ra_rate_floor_table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/ - u1Byte new_Ratr_State = 0; - u1Byte i; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 ra_rate_floor_table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/ + u8 new_ratr_state = 0; + u8 i; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("curr RA level = ((%d)), Rate_floor_table ori [ %d , %d, %d , %d, %d, %d]\n", Ratr_State, + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("curr RA level = ((%d)), Rate_floor_table ori [ %d , %d, %d , %d, %d, %d]\n", ratr_state, ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5])); for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { - if (i >= (Ratr_State)) + if (i >= (ratr_state)) ra_rate_floor_table[i] += RA_FLOOR_UP_GAP; } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI = ((%d)), Rate_floor_table_mod [ %d , %d, %d , %d, %d, %d]\n", + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI = ((%d)), Rate_floor_table_mod [ %d , %d, %d , %d, %d, %d]\n", rssi, ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5])); - + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { if (rssi < ra_rate_floor_table[i]) { - new_Ratr_State = i; + new_ratr_state = i; break; } } - return new_Ratr_State; + return new_ratr_state; } -VOID -odm_RefreshRateAdaptiveMaskMP( - IN PVOID pDM_VOID +void +odm_refresh_rate_adaptive_mask_mp( + void *p_dm_void ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER pAdapter = pDM_Odm->Adapter; - PADAPTER pTargetAdapter = NULL; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(pAdapter); - u4Byte i; - PSTA_INFO_T pEntry; - u1Byte Ratr_State_new; - - if (pAdapter->bDriverStopped) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + struct _ADAPTER *p_target_adapter = NULL; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(p_adapter); + struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(p_adapter); + PMGNT_INFO p_loop_mgnt_info = &(p_loop_adapter->MgntInfo); + HAL_DATA_TYPE *p_loop_hal_data = GET_HAL_DATA(p_loop_adapter); + + u32 i; + struct sta_info *p_entry; + u8 ratr_state_new; + + if (p_adapter->bDriverStopped) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_refresh_rate_adaptive_mask(): driver is going to unload\n")); return; } - if (!pHalData->bUseRAMask) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); + if (!p_hal_data->bUseRAMask) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_refresh_rate_adaptive_mask(): driver does not control rate adaptive mask\n")); return; } - // if default port is connected, update RA table for default port (infrastructure mode only) - if (pMgntInfo->mAssoc && (!ACTING_AS_AP(pAdapter))) { - odm_RefreshLdpcRtsMP(pAdapter, pDM_Odm, pMgntInfo->mMacId, pMgntInfo->IOTPeer, pHalData->UndecoratedSmoothedPWDB); - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Infrasture Mode\n"));*/ + /* if default port is connected, update RA table for default port (infrastructure mode only) */ + /* Need to consider other ports for P2P cases*/ + + while(p_loop_adapter){ + + p_loop_mgnt_info = &(p_loop_adapter->MgntInfo); + p_loop_hal_data = GET_HAL_DATA(p_loop_adapter); + + if (p_loop_mgnt_info->mAssoc && (!ACTING_AS_AP(p_loop_adapter))) { + odm_refresh_ldpc_rts_mp(p_loop_adapter, p_dm_odm, p_loop_mgnt_info->mMacId, p_loop_mgnt_info->IOTPeer, p_loop_hal_data->UndecoratedSmoothedPWDB); + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Infrasture mode\n"));*/ + +#if RA_MASK_PHYDMLIZE_WIN + ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_loop_hal_data->UndecoratedSmoothedPWDB, p_loop_mgnt_info->Ratr_State); - #if RA_MASK_PHYDMLIZE_WIN - Ratr_State_new = phydm_RA_level_decision(pDM_Odm, pHalData->UndecoratedSmoothedPWDB, pMgntInfo->Ratr_State); + if ((p_loop_mgnt_info->Ratr_State != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { - if (pMgntInfo->Ratr_State != Ratr_State_new) { - - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pMgntInfo->Bssid); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n\n", - pMgntInfo->Ratr_State, Ratr_State_new, pHalData->UndecoratedSmoothedPWDB)); - - pMgntInfo->Ratr_State = Ratr_State_new; - pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, Ratr_State_new); + p_ra_table->force_update_ra_mask_count = 0; + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), p_loop_mgnt_info->Bssid); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n\n", + p_mgnt_info->Ratr_State, ratr_state_new, p_loop_hal_data->UndecoratedSmoothedPWDB)); + + p_loop_mgnt_info->Ratr_State = ratr_state_new; + p_adapter->HalFunc.UpdateHalRAMaskHandler(p_loop_adapter, p_loop_mgnt_info->mMacId, NULL, ratr_state_new); } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", Ratr_State_new)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); /**/ } - - #else - if (ODM_RAStateCheck(pDM_Odm, pHalData->UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pMgntInfo->Ratr_State)) { - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pHalData->UndecoratedSmoothedPWDB, pMgntInfo->Ratr_State)); - pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State); - } else if (pDM_Odm->bChangeState) { - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training State, bDisablePowerTraining = %d\n", pDM_Odm->bDisablePowerTraining)); - pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State); + +#else + if (odm_ra_state_check(p_dm_odm, p_hal_data->UndecoratedSmoothedPWDB, p_mgnt_info->bSetTXPowerTrainingByOid, &p_mgnt_info->Ratr_State)) { + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), p_mgnt_info->Bssid); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_hal_data->UndecoratedSmoothedPWDB, p_mgnt_info->Ratr_State)); + p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, p_mgnt_info->Ratr_State); + } else if (p_dm_odm->is_change_state) { + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), p_mgnt_info->Bssid); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training state, is_disable_power_training = %d\n", p_dm_odm->is_disable_power_training)); + p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, p_mgnt_info->Ratr_State); } - #endif +#endif + + } + + p_loop_adapter = GetNextExtAdapter(p_loop_adapter); } - // - // The following part configure AP/VWifi/IBSS rate adaptive mask. - // + /* */ + /* The following part configure AP/VWifi/IBSS rate adaptive mask. */ + /* */ - if (pMgntInfo->mIbss) // Target: AP/IBSS peer. - pTargetAdapter = GetDefaultAdapter(pAdapter); + if (p_mgnt_info->mIbss) /* Target: AP/IBSS peer. */ + p_target_adapter = GetDefaultAdapter(p_adapter); else - pTargetAdapter = GetFirstAPAdapter(pAdapter); + p_target_adapter = GetFirstAPAdapter(p_adapter); - // if extension port (softap) is started, updaet RA table for more than one clients associate - if (pTargetAdapter != NULL) { + /* if extension port (softap) is started, updaet RA table for more than one clients associate */ + if (p_target_adapter != NULL) { for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - - pEntry = AsocEntry_EnumStation(pTargetAdapter, i); - - if (IS_STA_VALID(pEntry)) { - - odm_RefreshLdpcRtsMP(pAdapter, pDM_Odm, pEntry->AssociatedMacId, pEntry->IOTPeer, pEntry->rssi_stat.UndecoratedSmoothedPWDB); - - #if RA_MASK_PHYDMLIZE_WIN - Ratr_State_new = phydm_RA_level_decision(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->Ratr_State); - - if (pEntry->Ratr_State != Ratr_State_new) { - - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pEntry->MacAddr); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", - pEntry->Ratr_State, Ratr_State_new, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); - - pEntry->Ratr_State = Ratr_State_new; - pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pEntry->AssociatedMacId, NULL, Ratr_State_new); + + p_entry = AsocEntry_EnumStation(p_target_adapter, i); + + if (IS_STA_VALID(p_entry)) { + + odm_refresh_ldpc_rts_mp(p_target_adapter, p_dm_odm, p_entry->AssociatedMacId, p_entry->IOTPeer, p_entry->rssi_stat.undecorated_smoothed_pwdb); + +#if RA_MASK_PHYDMLIZE_WIN + ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->Ratr_State); + + if ((p_entry->Ratr_State != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { + + p_ra_table->force_update_ra_mask_count = 0; + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), p_entry->MacAddr); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", + p_entry->Ratr_State, ratr_state_new, p_entry->rssi_stat.undecorated_smoothed_pwdb)); + + p_entry->Ratr_State = ratr_state_new; + p_adapter->HalFunc.UpdateHalRAMaskHandler(p_target_adapter, p_entry->AssociatedMacId, p_entry, ratr_state_new); } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", Ratr_State_new)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); /**/ } - - - #else - - if (ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntry->Ratr_State)) { - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->Ratr_State)); - pAdapter->HalFunc.UpdateHalRAMaskHandler(pTargetAdapter, pEntry->AssociatedMacId, pEntry, pEntry->Ratr_State); - } else if (pDM_Odm->bChangeState) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training State, bDisablePowerTraining = %d\n", pDM_Odm->bDisablePowerTraining)); - pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State); + + +#else + + if (odm_ra_state_check(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_mgnt_info->bSetTXPowerTrainingByOid, &p_entry->Ratr_State)) { + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), p_entry->mac_addr); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->Ratr_State)); + p_adapter->hal_func.update_hal_ra_mask_handler(p_target_adapter, p_entry->AssociatedMacId, p_entry, p_entry->Ratr_State); + } else if (p_dm_odm->is_change_state) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training state, is_disable_power_training = %d\n", p_dm_odm->is_disable_power_training)); + p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, p_mgnt_info->Ratr_State); } - #endif - +#endif + } } } - - #if RA_MASK_PHYDMLIZE_WIN - #else - if (pMgntInfo->bSetTXPowerTrainingByOid) - pMgntInfo->bSetTXPowerTrainingByOid = FALSE; - #endif -#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if RA_MASK_PHYDMLIZE_WIN + +#else + if (p_mgnt_info->bSetTXPowerTrainingByOid) + p_mgnt_info->bSetTXPowerTrainingByOid = false; +#endif +#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ } -VOID -odm_RefreshRateAdaptiveMaskCE( - IN PVOID pDM_VOID +void +odm_refresh_rate_adaptive_mask_ce( + void *p_dm_void ) { #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER pAdapter = pDM_Odm->Adapter; - PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; - u4Byte i; - PSTA_INFO_T pEntry; - u1Byte Ratr_State_new; - - if (RTW_CANNOT_RUN(pAdapter)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + struct _ODM_RATE_ADAPTIVE *p_ra = &p_dm_odm->rate_adaptive; +#endif + u32 i; + struct sta_info *p_entry; + u8 ratr_state_new; + +#ifndef DM_ODM_CE_MAC80211 + if (RTW_CANNOT_RUN(p_adapter)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_refresh_rate_adaptive_mask(): driver is going to unload\n")); return; } +#endif - if (!pDM_Odm->bUseRAMask) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); + if (!p_dm_odm->is_use_ra_mask) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_refresh_rate_adaptive_mask(): driver does not control rate adaptive mask\n")); return; } for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - - pEntry = pDM_Odm->pODM_StaInfo[i]; - - if (IS_STA_VALID(pEntry)) { - if (IS_MCAST(pEntry->hwaddr)) - continue; + p_entry = p_dm_odm->p_odm_sta_info[i]; - #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) - if ((pDM_Odm->SupportICType == ODM_RTL8812) || (pDM_Odm->SupportICType == ODM_RTL8821)) { - if (pEntry->rssi_stat.UndecoratedSmoothedPWDB < pRA->LdpcThres) { - pRA->bUseLdpc = TRUE; - pRA->bLowerRtsRate = TRUE; - if ((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A)) - Set_RA_LDPC_8812(pEntry, TRUE); - //DbgPrint("RSSI=%d, bUseLdpc = TRUE\n", pHalData->UndecoratedSmoothedPWDB); - } else if (pEntry->rssi_stat.UndecoratedSmoothedPWDB > (pRA->LdpcThres - 5)) { - pRA->bUseLdpc = FALSE; - pRA->bLowerRtsRate = FALSE; - if ((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A)) - Set_RA_LDPC_8812(pEntry, FALSE); - //DbgPrint("RSSI=%d, bUseLdpc = FALSE\n", pHalData->UndecoratedSmoothedPWDB); - } - } - #endif - - #if RA_MASK_PHYDMLIZE_CE - Ratr_State_new = phydm_RA_level_decision(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->rssi_level); - - if (pEntry->rssi_level != Ratr_State_new) { - - /*ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pstat->hwaddr);*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", - pEntry->rssi_level, Ratr_State_new, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); - - pEntry->rssi_level = Ratr_State_new; - rtw_hal_update_ra_mask(pEntry, pEntry->rssi_level); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", Ratr_State_new)); - /**/ - } - #else - if (TRUE == ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, FALSE , &pEntry->rssi_level)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->rssi_level)); - //printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level); - rtw_hal_update_ra_mask(pEntry, pEntry->rssi_level); - } else if (pDM_Odm->bChangeState) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training State, bDisablePowerTraining = %d\n", pDM_Odm->bDisablePowerTraining)); - rtw_hal_update_ra_mask(pEntry, pEntry->rssi_level); + if (!IS_STA_VALID(p_entry)) { + continue; + } + +#ifdef DM_ODM_CE_MAC80211 + if (is_multicast_ether_addr(p_entry->mac_addr)) + continue; + else if (is_broadcast_ether_addr(p_entry->mac_addr)) + continue; +#else + if (IS_MCAST(p_entry->hwaddr)) + continue; +#endif + +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + if ((p_dm_odm->support_ic_type == ODM_RTL8812) || (p_dm_odm->support_ic_type == ODM_RTL8821)) { + if (p_entry->rssi_stat.undecorated_smoothed_pwdb < p_ra->ldpc_thres) { + p_ra->is_use_ldpc = true; + p_ra->is_lower_rts_rate = true; + if ((p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->cut_version == ODM_CUT_A)) + set_ra_ldpc_8812(p_entry, true); + /* dbg_print("RSSI=%d, is_use_ldpc = true\n", p_hal_data->undecorated_smoothed_pwdb); */ + } else if (p_entry->rssi_stat.undecorated_smoothed_pwdb > (p_ra->ldpc_thres - 5)) { + p_ra->is_use_ldpc = false; + p_ra->is_lower_rts_rate = false; + if ((p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->cut_version == ODM_CUT_A)) + set_ra_ldpc_8812(p_entry, false); + /* dbg_print("RSSI=%d, is_use_ldpc = false\n", p_hal_data->undecorated_smoothed_pwdb); */ } - #endif + } +#endif + +#if RA_MASK_PHYDMLIZE_CE + ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_level); + + if ((p_entry->rssi_level != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { + p_ra_table->force_update_ra_mask_count = 0; + /*ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pstat->hwaddr);*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", + p_entry->rssi_level, ratr_state_new, p_entry->rssi_stat.undecorated_smoothed_pwdb)); + + p_entry->rssi_level = ratr_state_new; +#ifdef DM_ODM_CE_MAC80211 + rtl_hal_update_ra_mask(p_adapter, p_entry, p_entry->rssi_level); +#else + rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE); +#endif + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); + /**/ + } +#else + if (true == odm_ra_state_check(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, false, &p_entry->rssi_level)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_level)); + /* printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.undecorated_smoothed_pwdb, pstat->rssi_level); */ + rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE); + } else if (p_dm_odm->is_change_state) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training state, is_disable_power_training = %d\n", p_dm_odm->is_disable_power_training)); + rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE); } +#endif + + } #endif } -VOID -odm_RefreshRateAdaptiveMaskAPADSL( - IN PVOID pDM_VOID +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +void +phydm_gen_ramask_h2c_AP( + void *p_dm_void, + struct rtl8192cd_priv *priv, + struct sta_info *p_entry, + u8 rssi_level +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type == ODM_RTL8812) { + +#if (RTL8812A_SUPPORT == 1) + UpdateHalRAMask8812(priv, p_entry, rssi_level); + /**/ +#endif + } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + +#if (RTL8188E_SUPPORT == 1) +#ifdef TXREPORT + add_RATid(priv, p_entry); + /**/ +#endif +#endif + } else { + +#ifdef CONFIG_WLAN_HAL + GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, p_entry, rssi_level); +#endif + + } +} + +#endif + +void +odm_refresh_rate_adaptive_mask_apadsl( + void *p_dm_void ) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - struct rtl8192cd_priv *priv = pDM_Odm->priv; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct rtl8192cd_priv *priv = p_dm_odm->priv; struct aid_obj *aidarray; - u4Byte i; - PSTA_INFO_T pEntry; - u1Byte Ratr_State_new; - + u32 i; + struct sta_info *p_entry; + u8 ratr_state_new; + if (priv->up_time % 2) return; for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - pEntry = pDM_Odm->pODM_StaInfo[i]; + p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(pEntry)) { - - #if defined(UNIVERSAL_REPEATER) || defined(MBSSID) - aidarray = container_of(pEntry, struct aid_obj, station); + if (IS_STA_VALID(p_entry)) { + +#if defined(UNIVERSAL_REPEATER) || defined(MBSSID) + aidarray = container_of(p_entry, struct aid_obj, station); priv = aidarray->priv; - #endif +#endif if (!priv->pmib->dot11StationConfigEntry.autoRate) continue; #if RA_MASK_PHYDMLIZE_AP - Ratr_State_new = phydm_RA_level_decision(pDM_Odm, (u4Byte)pEntry->rssi, pEntry->rssi_level); - - if (pEntry->rssi_level != Ratr_State_new) { - - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pEntry->hwaddr); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", pEntry->rssi_level, Ratr_State_new, pEntry->rssi)); - - pEntry->rssi_level = Ratr_State_new; - phydm_gen_ramask_h2c_AP(pDM_Odm, priv, pEntry, pEntry->rssi_level); + ratr_state_new = phydm_RA_level_decision(p_dm_odm, (u32)p_entry->rssi, p_entry->rssi_level); + + if ((p_entry->rssi_level != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { + + p_ra_table->force_update_ra_mask_count = 0; + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), p_entry->hwaddr); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", p_entry->rssi_level, ratr_state_new, p_entry->rssi)); + + p_entry->rssi_level = ratr_state_new; + phydm_gen_ramask_h2c_AP(p_dm_odm, priv, p_entry, p_entry->rssi_level); } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", Ratr_State_new)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); /**/ } #else - if (ODM_RAStateCheck(pDM_Odm, (s4Byte)pEntry->rssi, FALSE, &pEntry->rssi_level)) { - ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->hwaddr); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi, pEntry->rssi_level)); + if (odm_ra_state_check(p_dm_odm, (s32)p_entry->rssi, false, &p_entry->rssi_level)) { + ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), p_entry->hwaddr); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_entry->rssi, p_entry->rssi_level)); - #ifdef CONFIG_WLAN_HAL +#ifdef CONFIG_WLAN_HAL if (IS_HAL_CHIP(priv)) { - #ifdef WDS - /*if(!(pstat->state & WIFI_WDS))*/ /*if WDS donot setting*/ - #endif - GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, pEntry, pEntry->rssi_level); +#ifdef WDS + /*if(!(pstat->state & WIFI_WDS))*/ /*if WDS donot setting*/ +#endif + GET_HAL_INTERFACE(priv)->update_hal_ra_mask_handler(priv, p_entry, p_entry->rssi_level); } else - #endif +#endif - #ifdef CONFIG_RTL_8812_SUPPORT +#ifdef CONFIG_RTL_8812_SUPPORT if (GET_CHIP_VER(priv) == VERSION_8812E) - UpdateHalRAMask8812(priv, pEntry, 3); + update_hal_ra_mask8812(priv, p_entry, 3); else - #endif +#endif { - #ifdef CONFIG_RTL_88E_SUPPORT +#ifdef CONFIG_RTL_88E_SUPPORT if (GET_CHIP_VER(priv) == VERSION_8188E) { - #ifdef TXREPORT - add_RATid(priv, pEntry); - #endif +#ifdef TXREPORT + add_ra_tid(priv, p_entry); +#endif } - #endif +#endif } - } + } #endif /*#ifdef RA_MASK_PHYDMLIZE*/ - + } } #endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_AP)*/ } -VOID -odm_RefreshBasicRateMask( - IN PVOID pDM_VOID +void +odm_refresh_basic_rate_mask( + void *p_dm_void ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - static u1Byte Stage = 0; - u1Byte CurStage = 0; - OCTET_STRING osRateSet; - PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter); - u1Byte RateSet[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M}; - - if (pDM_Odm->SupportICType != ODM_RTL8812 && pDM_Odm->SupportICType != ODM_RTL8821) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + static u8 stage = 0; + u8 cur_stage = 0; + OCTET_STRING os_rate_set; + PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(adapter); + u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M}; + + if (p_dm_odm->support_ic_type != ODM_RTL8812 && p_dm_odm->support_ic_type != ODM_RTL8821) return; - if (pDM_Odm->bLinked == FALSE) // unlink Default port information - CurStage = 0; - else if (pDM_Odm->RSSI_Min < 40) // link RSSI < 40% - CurStage = 1; - else if (pDM_Odm->RSSI_Min > 45) // link RSSI > 45% - CurStage = 3; + if (p_dm_odm->is_linked == false) /* unlink Default port information */ + cur_stage = 0; + else if (p_dm_odm->rssi_min < 40) /* link RSSI < 40% */ + cur_stage = 1; + else if (p_dm_odm->rssi_min > 45) /* link RSSI > 45% */ + cur_stage = 3; else - CurStage = 2; // link 25% <= RSSI <= 30% + cur_stage = 2; /* link 25% <= RSSI <= 30% */ - if (CurStage != Stage) { - if (CurStage == 1) { - FillOctetString(osRateSet, RateSet, 5); - FilterSupportRate(pMgntInfo->mBrates, &osRateSet, FALSE); - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_BASIC_RATE, (pu1Byte)&osRateSet); - } else if (CurStage == 3 && (Stage == 1 || Stage == 2)) - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates)); + if (cur_stage != stage) { + if (cur_stage == 1) { + FillOctetString(os_rate_set, rate_set, 5); + FilterSupportRate(p_mgnt_info->mBrates, &os_rate_set, false); + phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set); + } else if (cur_stage == 3 && (stage == 1 || stage == 2)) + phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_BASIC_RATE, (u8 *)(&p_mgnt_info->mBrates)); } - Stage = CurStage; + stage = cur_stage; #endif } -u1Byte +u8 phydm_rate_order_compute( - IN PVOID pDM_VOID, - IN u1Byte rate_idx - ) + void *p_dm_void, + u8 rate_idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte rate_order = 0; + u8 rate_order = 0; if (rate_idx >= ODM_RATEVHTSS4MCS0) { - + rate_idx -= ODM_RATEVHTSS4MCS0; /**/ } else if (rate_idx >= ODM_RATEVHTSS3MCS0) { - + rate_idx -= ODM_RATEVHTSS3MCS0; - /**/ + /**/ } else if (rate_idx >= ODM_RATEVHTSS2MCS0) { - + rate_idx -= ODM_RATEVHTSS2MCS0; - /**/ + /**/ } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { - + rate_idx -= ODM_RATEVHTSS1MCS0; /**/ } else if (rate_idx >= ODM_RATEMCS24) { - + rate_idx -= ODM_RATEMCS24; /**/ } else if (rate_idx >= ODM_RATEMCS16) { - + rate_idx -= ODM_RATEMCS16; /**/ } else if (rate_idx >= ODM_RATEMCS8) { - - rate_idx -= ODM_RATEMCS8; + + rate_idx -= ODM_RATEMCS8; /**/ } rate_order = rate_idx; @@ -2424,95 +2650,95 @@ phydm_rate_order_compute( } -VOID +void phydm_ra_common_info_update( - IN PVOID pDM_VOID - ) + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; - u2Byte macid; - u1Byte rate_order_tmp; - u1Byte cnt = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u16 macid; + u8 rate_order_tmp; + u8 cnt = 0; - pRA_Table->highest_client_tx_order = 0; - pRA_Table->power_tracking_flag = 1; + p_ra_table->highest_client_tx_order = 0; + p_ra_table->power_tracking_flag = 1; - if (pDM_Odm->number_linked_client != 0) { + if (p_dm_odm->number_linked_client != 0) { for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { - - rate_order_tmp = phydm_rate_order_compute(pDM_Odm, ((pRA_Table->link_tx_rate[macid]) & 0x7f)); - if (rate_order_tmp >= (pRA_Table->highest_client_tx_order)) { - pRA_Table->highest_client_tx_order = rate_order_tmp; - pRA_Table->highest_client_tx_rate_order = macid; + rate_order_tmp = phydm_rate_order_compute(p_dm_odm, ((p_ra_table->link_tx_rate[macid]) & 0x7f)); + + if (rate_order_tmp >= (p_ra_table->highest_client_tx_order)) { + p_ra_table->highest_client_tx_order = rate_order_tmp; + p_ra_table->highest_client_tx_rate_order = macid; } - + cnt++; - - if (cnt == pDM_Odm->number_linked_client) + + if (cnt == p_dm_odm->number_linked_client) break; } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("MACID[%d], Highest Tx order Update for power traking: %d\n", (pRA_Table->highest_client_tx_rate_order), (pRA_Table->highest_client_tx_order))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("MACID[%d], Highest Tx order Update for power traking: %d\n", (p_ra_table->highest_client_tx_rate_order), (p_ra_table->highest_client_tx_order))); } } -VOID +void phydm_ra_info_watchdog( - IN PVOID pDM_VOID - ) + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - phydm_ra_common_info_update(pDM_Odm); - phydm_ra_dynamic_retry_limit(pDM_Odm); - phydm_ra_dynamic_retry_count(pDM_Odm); - odm_RefreshRateAdaptiveMask(pDM_Odm); - odm_RefreshBasicRateMask(pDM_Odm); + phydm_ra_common_info_update(p_dm_odm); + phydm_ra_dynamic_retry_limit(p_dm_odm); + phydm_ra_dynamic_retry_count(p_dm_odm); + odm_refresh_rate_adaptive_mask(p_dm_odm); + odm_refresh_basic_rate_mask(p_dm_odm); } -VOID +void phydm_ra_info_init( - IN PVOID pDM_VOID - ) + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - pRA_Table->highest_client_tx_rate_order = 0; - pRA_Table->highest_client_tx_order = 0; - pRA_Table->RA_threshold_offset = 0; - pRA_Table->RA_offset_direction = 0; + p_ra_table->highest_client_tx_rate_order = 0; + p_ra_table->highest_client_tx_order = 0; + p_ra_table->RA_threshold_offset = 0; + p_ra_table->RA_offset_direction = 0; - #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - phydm_ra_dynamic_retry_limit_init(pDM_Odm); - #endif - - #if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) - phydm_ra_dynamic_rate_id_init(pDM_Odm); - #endif - #if (defined(CONFIG_RA_DBG_CMD)) - odm_RA_ParaAdjust_init(pDM_Odm); - #endif +#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) + phydm_ra_dynamic_retry_limit_init(p_dm_odm); +#endif + +#if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) + phydm_ra_dynamic_rate_id_init(p_dm_odm); +#endif +#if (defined(CONFIG_RA_DBG_CMD)) + odm_ra_para_adjust_init(p_dm_odm); +#endif } #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -u1Byte -odm_Find_RTS_Rate( - IN PVOID pDM_VOID, - IN u1Byte Tx_Rate, - IN BOOLEAN bErpProtect +u8 +odm_find_rts_rate( + void *p_dm_void, + u8 tx_rate, + boolean is_erp_protect ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte RTS_Ini_Rate = ODM_RATE6M; - - if (bErpProtect) /* use CCK rate as RTS*/ - RTS_Ini_Rate = ODM_RATE1M; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 rts_ini_rate = ODM_RATE6M; + + if (is_erp_protect) /* use CCK rate as RTS*/ + rts_ini_rate = ODM_RATE1M; else { - switch (Tx_Rate) { + switch (tx_rate) { case ODM_RATEVHTSS3MCS9: case ODM_RATEVHTSS3MCS8: case ODM_RATEVHTSS3MCS7: @@ -2547,8 +2773,8 @@ odm_Find_RTS_Rate( case ODM_RATE54M: case ODM_RATE48M: case ODM_RATE36M: - case ODM_RATE24M: - RTS_Ini_Rate = ODM_RATE24M; + case ODM_RATE24M: + rts_ini_rate = ODM_RATE24M; break; case ODM_RATEVHTSS3MCS2: case ODM_RATEVHTSS3MCS1: @@ -2562,7 +2788,7 @@ odm_Find_RTS_Rate( case ODM_RATEMCS1: case ODM_RATE18M: case ODM_RATE12M: - RTS_Ini_Rate = ODM_RATE12M; + rts_ini_rate = ODM_RATE12M; break; case ODM_RATEVHTSS3MCS0: case ODM_RATEVHTSS2MCS0: @@ -2571,426 +2797,432 @@ odm_Find_RTS_Rate( case ODM_RATEMCS0: case ODM_RATE9M: case ODM_RATE6M: - RTS_Ini_Rate = ODM_RATE6M; + rts_ini_rate = ODM_RATE6M; break; case ODM_RATE11M: case ODM_RATE5_5M: case ODM_RATE2M: case ODM_RATE1M: - RTS_Ini_Rate = ODM_RATE1M; + rts_ini_rate = ODM_RATE1M; break; default: - RTS_Ini_Rate = ODM_RATE6M; + rts_ini_rate = ODM_RATE6M; break; } } - if (*pDM_Odm->pBandType == 1) { - if (RTS_Ini_Rate < ODM_RATE6M) - RTS_Ini_Rate = ODM_RATE6M; + if (*p_dm_odm->p_band_type == 1) { + if (rts_ini_rate < ODM_RATE6M) + rts_ini_rate = ODM_RATE6M; } - return RTS_Ini_Rate; + return rts_ini_rate; } -VOID -odm_Set_RA_DM_ARFB_by_Noisy( - IN PDM_ODM_T pDM_Odm +void +odm_set_ra_dm_arfb_by_noisy( + struct PHY_DM_STRUCT *p_dm_odm ) { #if 0 - /*DbgPrint("DM_ARFB ====>\n");*/ - if (pDM_Odm->bNoisyState) { - ODM_Write4Byte(pDM_Odm, 0x430, 0x00000000); - ODM_Write4Byte(pDM_Odm, 0x434, 0x05040200); - /*DbgPrint("DM_ARFB ====> Noisy State\n");*/ + /*dbg_print("DM_ARFB ====>\n");*/ + if (p_dm_odm->is_noisy_state) { + odm_write_4byte(p_dm_odm, 0x430, 0x00000000); + odm_write_4byte(p_dm_odm, 0x434, 0x05040200); + /*dbg_print("DM_ARFB ====> Noisy state\n");*/ } else { - ODM_Write4Byte(pDM_Odm, 0x430, 0x02010000); - ODM_Write4Byte(pDM_Odm, 0x434, 0x07050403); - /*DbgPrint("DM_ARFB ====> Clean State\n");*/ + odm_write_4byte(p_dm_odm, 0x430, 0x02010000); + odm_write_4byte(p_dm_odm, 0x434, 0x07050403); + /*dbg_print("DM_ARFB ====> Clean state\n");*/ } #endif } -VOID -ODM_UpdateNoisyState( - IN PVOID pDM_VOID, - IN BOOLEAN bNoisyStateFromC2H +void +odm_update_noisy_state( + void *p_dm_void, + boolean is_noisy_state_from_c2h ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - /*DbgPrint("Get C2H Command! NoisyState=0x%x\n ", bNoisyStateFromC2H);*/ - if (pDM_Odm->SupportICType == ODM_RTL8821 || pDM_Odm->SupportICType == ODM_RTL8812 || - pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723D) - pDM_Odm->bNoisyState = bNoisyStateFromC2H; - odm_Set_RA_DM_ARFB_by_Noisy(pDM_Odm); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + +/* JJ ADD 20161014 */ + /*dbg_print("Get C2H Command! NoisyState=0x%x\n ", is_noisy_state_from_c2h);*/ + if (p_dm_odm->support_ic_type == ODM_RTL8821 || p_dm_odm->support_ic_type == ODM_RTL8812 || + p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B) + p_dm_odm->is_noisy_state = is_noisy_state_from_c2h; + odm_set_ra_dm_arfb_by_noisy(p_dm_odm); }; -VOID +void phydm_update_pwr_track( - IN PVOID pDM_VOID, - IN u1Byte Rate + void *p_dm_void, + u8 rate ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte pathIdx = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Pwr Track Get Rate=0x%x\n", Rate)); - - pDM_Odm->TxRate = Rate; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - #if USE_WORKITEM - PlatformScheduleWorkItem(&pDM_Odm->RaRptWorkitem); - #else - if (pDM_Odm->SupportICType == ODM_RTL8821) { - #if (RTL8821A_SUPPORT == 1) - ODM_TxPwrTrackSetPwr8821A(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); - #endif - } else if (pDM_Odm->SupportICType == ODM_RTL8812) { - for (pathIdx = ODM_RF_PATH_A; pathIdx < MAX_PATH_NUM_8812A; pathIdx++) { - #if (RTL8812A_SUPPORT == 1) - ODM_TxPwrTrackSetPwr8812A(pDM_Odm, MIX_MODE, pathIdx, 0); - #endif - } - } else if (pDM_Odm->SupportICType == ODM_RTL8723B) { - #if (RTL8723B_SUPPORT == 1) - ODM_TxPwrTrackSetPwr_8723B(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); - #endif - } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { - for (pathIdx = ODM_RF_PATH_A; pathIdx < MAX_PATH_NUM_8192E; pathIdx++) { - #if (RTL8192E_SUPPORT == 1) - ODM_TxPwrTrackSetPwr92E(pDM_Odm, MIX_MODE, pathIdx, 0); - #endif - } - } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { - #if (RTL8188E_SUPPORT == 1) - ODM_TxPwrTrackSetPwr88E(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); - #endif - } - #endif - #else - PlatformScheduleWorkItem(&pDM_Odm->RaRptWorkitem); - #endif - #endif + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + u8 path_idx = 0; +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Pwr Track Get rate=0x%x\n", rate)); + + p_dm_odm->tx_rate = rate; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +#if USE_WORKITEM + odm_schedule_work_item(&p_dm_odm->ra_rpt_workitem); +#else + if (p_dm_odm->support_ic_type == ODM_RTL8821) { +#if (RTL8821A_SUPPORT == 1) + odm_tx_pwr_track_set_pwr8821a(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); +#endif + } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { + for (path_idx = ODM_RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) { +#if (RTL8812A_SUPPORT == 1) + odm_tx_pwr_track_set_pwr8812a(p_dm_odm, MIX_MODE, path_idx, 0); +#endif + } + } else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { +#if (RTL8723B_SUPPORT == 1) + odm_tx_pwr_track_set_pwr_8723b(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); +#endif + } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + for (path_idx = ODM_RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) { +#if (RTL8192E_SUPPORT == 1) + odm_tx_pwr_track_set_pwr92_e(p_dm_odm, MIX_MODE, path_idx, 0); +#endif + } + } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + odm_tx_pwr_track_set_pwr88_e(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); +#endif + } +#endif +#else + odm_schedule_work_item(&p_dm_odm->ra_rpt_workitem); +#endif +#endif } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -s4Byte -phydm_FindMinimumRSSI( -IN PDM_ODM_T pDM_Odm, -IN PADAPTER pAdapter, -IN OUT BOOLEAN *pbLink_temp - - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); - BOOLEAN act_as_ap = ACTING_AS_AP(pAdapter); - +s32 +phydm_find_minimum_rssi( + struct PHY_DM_STRUCT *p_dm_odm, + struct _ADAPTER *p_adapter, + OUT boolean *p_is_link_temp + +) +{ + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + PMGNT_INFO p_mgnt_info = &(p_adapter->MgntInfo); + boolean act_as_ap = ACTING_AS_AP(p_adapter); + /* 1.Determine the minimum RSSI */ - if ((!pMgntInfo->bMediaConnect) || - (act_as_ap && (pHalData->EntryMinUndecoratedSmoothedPWDB == 0))) {/* We should check AP mode and Entry info.into consideration, revised by Roger, 2013.10.18*/ - - pHalData->MinUndecoratedPWDBForDM = 0; - *pbLink_temp = FALSE; + if ((!p_mgnt_info->bMediaConnect) || + (act_as_ap && (p_hal_data->EntryMinUndecoratedSmoothedPWDB == 0))) {/* We should check AP mode and Entry info.into consideration, revised by Roger, 2013.10.18*/ + + p_hal_data->MinUndecoratedPWDBForDM = 0; + *p_is_link_temp = false; } else - *pbLink_temp = TRUE; - + *p_is_link_temp = true; - if (pMgntInfo->bMediaConnect) { /* Default port*/ - - if (act_as_ap || pMgntInfo->mIbss) { - pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; + + if (p_mgnt_info->bMediaConnect) { /* Default port*/ + + if (act_as_ap || p_mgnt_info->mIbss) { + p_hal_data->MinUndecoratedPWDBForDM = p_hal_data->EntryMinUndecoratedSmoothedPWDB; /**/ } else { - pHalData->MinUndecoratedPWDBForDM = pHalData->UndecoratedSmoothedPWDB; + p_hal_data->MinUndecoratedPWDBForDM = p_hal_data->UndecoratedSmoothedPWDB; /**/ } } else { /* associated entry pwdb*/ - pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; + p_hal_data->MinUndecoratedPWDBForDM = p_hal_data->EntryMinUndecoratedSmoothedPWDB; /**/ } - return pHalData->MinUndecoratedPWDBForDM; + return p_hal_data->MinUndecoratedPWDBForDM; } -VOID -ODM_UpdateInitRateWorkItemCallback( - IN PVOID pContext +void +odm_update_init_rate_work_item_callback( + void *p_context ) { - PADAPTER Adapter = (PADAPTER)pContext; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - u1Byte p = 0; + struct _ADAPTER *adapter = (struct _ADAPTER *)p_context; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + u8 p = 0; - if (pDM_Odm->SupportICType == ODM_RTL8821) { - ODM_TxPwrTrackSetPwr8821A(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); + if (p_dm_odm->support_ic_type == ODM_RTL8821) { + odm_tx_pwr_track_set_pwr8821a(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); /**/ - } else if (pDM_Odm->SupportICType == ODM_RTL8812) { + } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) { /*DOn't know how to include &c*/ - - ODM_TxPwrTrackSetPwr8812A(pDM_Odm, MIX_MODE, p, 0); + + odm_tx_pwr_track_set_pwr8812a(p_dm_odm, MIX_MODE, p, 0); /**/ } - } else if (pDM_Odm->SupportICType == ODM_RTL8723B) { - ODM_TxPwrTrackSetPwr_8723B(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); - /**/ - } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { + } else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + odm_tx_pwr_track_set_pwr_8723b(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); + /**/ + } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) { /*DOn't know how to include &c*/ - ODM_TxPwrTrackSetPwr92E(pDM_Odm, MIX_MODE, p, 0); + odm_tx_pwr_track_set_pwr92_e(p_dm_odm, MIX_MODE, p, 0); /**/ } - } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { - ODM_TxPwrTrackSetPwr88E(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); + } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + odm_tx_pwr_track_set_pwr88_e(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); /**/ } } -VOID -odm_RSSIDumpToRegister( - IN PVOID pDM_VOID +void +odm_rssi_dump_to_register( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; - if (pDM_Odm->SupportICType == ODM_RTL8812) { - PlatformEFIOWrite1Byte(Adapter, rA_RSSIDump_Jaguar, Adapter->RxStats.RxRSSIPercentage[0]); - PlatformEFIOWrite1Byte(Adapter, rB_RSSIDump_Jaguar, Adapter->RxStats.RxRSSIPercentage[1]); + if (p_dm_odm->support_ic_type == ODM_RTL8812) { + PlatformEFIOWrite1Byte(adapter, REG_A_RSSI_DUMP_JAGUAR, adapter->RxStats.RxRSSIPercentage[0]); + PlatformEFIOWrite1Byte(adapter, REG_B_RSSI_DUMP_JAGUAR, adapter->RxStats.RxRSSIPercentage[1]); /* Rx EVM*/ - PlatformEFIOWrite1Byte(Adapter, rS1_RXevmDump_Jaguar, Adapter->RxStats.RxEVMdbm[0]); - PlatformEFIOWrite1Byte(Adapter, rS2_RXevmDump_Jaguar, Adapter->RxStats.RxEVMdbm[1]); + PlatformEFIOWrite1Byte(adapter, REG_S1_RXEVM_DUMP_JAGUAR, adapter->RxStats.RxEVMdbm[0]); + PlatformEFIOWrite1Byte(adapter, REG_S2_RXEVM_DUMP_JAGUAR, adapter->RxStats.RxEVMdbm[1]); /* Rx SNR*/ - PlatformEFIOWrite1Byte(Adapter, rA_RXsnrDump_Jaguar, (u1Byte)(Adapter->RxStats.RxSNRdB[0])); - PlatformEFIOWrite1Byte(Adapter, rB_RXsnrDump_Jaguar, (u1Byte)(Adapter->RxStats.RxSNRdB[1])); + PlatformEFIOWrite1Byte(adapter, REG_A_RX_SNR_DUMP_JAGUAR, (u8)(adapter->RxStats.RxSNRdB[0])); + PlatformEFIOWrite1Byte(adapter, REG_B_RX_SNR_DUMP_JAGUAR, (u8)(adapter->RxStats.RxSNRdB[1])); /* Rx Cfo_Short*/ - PlatformEFIOWrite2Byte(Adapter, rA_CfoShortDump_Jaguar, Adapter->RxStats.RxCfoShort[0]); - PlatformEFIOWrite2Byte(Adapter, rB_CfoShortDump_Jaguar, Adapter->RxStats.RxCfoShort[1]); + PlatformEFIOWrite2Byte(adapter, REG_A_CFO_SHORT_DUMP_JAGUAR, adapter->RxStats.RxCfoShort[0]); + PlatformEFIOWrite2Byte(adapter, REG_B_CFO_SHORT_DUMP_JAGUAR, adapter->RxStats.RxCfoShort[1]); /* Rx Cfo_Tail*/ - PlatformEFIOWrite2Byte(Adapter, rA_CfoLongDump_Jaguar, Adapter->RxStats.RxCfoTail[0]); - PlatformEFIOWrite2Byte(Adapter, rB_CfoLongDump_Jaguar, Adapter->RxStats.RxCfoTail[1]); - } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { - PlatformEFIOWrite1Byte(Adapter, rA_RSSIDump_92E, Adapter->RxStats.RxRSSIPercentage[0]); - PlatformEFIOWrite1Byte(Adapter, rB_RSSIDump_92E, Adapter->RxStats.RxRSSIPercentage[1]); + PlatformEFIOWrite2Byte(adapter, REG_A_CFO_LONG_DUMP_JAGUAR, adapter->RxStats.RxCfoTail[0]); + PlatformEFIOWrite2Byte(adapter, REG_B_CFO_LONG_DUMP_JAGUAR, adapter->RxStats.RxCfoTail[1]); + } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + PlatformEFIOWrite1Byte(adapter, REG_A_RSSI_DUMP_92E, adapter->RxStats.RxRSSIPercentage[0]); + PlatformEFIOWrite1Byte(adapter, REG_B_RSSI_DUMP_92E, adapter->RxStats.RxRSSIPercentage[1]); /* Rx EVM*/ - PlatformEFIOWrite1Byte(Adapter, rS1_RXevmDump_92E, Adapter->RxStats.RxEVMdbm[0]); - PlatformEFIOWrite1Byte(Adapter, rS2_RXevmDump_92E, Adapter->RxStats.RxEVMdbm[1]); + PlatformEFIOWrite1Byte(adapter, REG_S1_RXEVM_DUMP_92E, adapter->RxStats.RxEVMdbm[0]); + PlatformEFIOWrite1Byte(adapter, REG_S2_RXEVM_DUMP_92E, adapter->RxStats.RxEVMdbm[1]); /* Rx SNR*/ - PlatformEFIOWrite1Byte(Adapter, rA_RXsnrDump_92E, (u1Byte)(Adapter->RxStats.RxSNRdB[0])); - PlatformEFIOWrite1Byte(Adapter, rB_RXsnrDump_92E, (u1Byte)(Adapter->RxStats.RxSNRdB[1])); + PlatformEFIOWrite1Byte(adapter, REG_A_RX_SNR_DUMP_92E, (u8)(adapter->RxStats.RxSNRdB[0])); + PlatformEFIOWrite1Byte(adapter, REG_B_RX_SNR_DUMP_92E, (u8)(adapter->RxStats.RxSNRdB[1])); /* Rx Cfo_Short*/ - PlatformEFIOWrite2Byte(Adapter, rA_CfoShortDump_92E, Adapter->RxStats.RxCfoShort[0]); - PlatformEFIOWrite2Byte(Adapter, rB_CfoShortDump_92E, Adapter->RxStats.RxCfoShort[1]); + PlatformEFIOWrite2Byte(adapter, REG_A_CFO_SHORT_DUMP_92E, adapter->RxStats.RxCfoShort[0]); + PlatformEFIOWrite2Byte(adapter, REG_B_CFO_SHORT_DUMP_92E, adapter->RxStats.RxCfoShort[1]); /* Rx Cfo_Tail*/ - PlatformEFIOWrite2Byte(Adapter, rA_CfoLongDump_92E, Adapter->RxStats.RxCfoTail[0]); - PlatformEFIOWrite2Byte(Adapter, rB_CfoLongDump_92E, Adapter->RxStats.RxCfoTail[1]); + PlatformEFIOWrite2Byte(adapter, REG_A_CFO_LONG_DUMP_92E, adapter->RxStats.RxCfoTail[0]); + PlatformEFIOWrite2Byte(adapter, REG_B_CFO_LONG_DUMP_92E, adapter->RxStats.RxCfoTail[1]); } } -VOID -odm_RefreshLdpcRtsMP( - IN PADAPTER pAdapter, - IN PDM_ODM_T pDM_Odm, - IN u1Byte mMacId, - IN u1Byte IOTPeer, - IN s4Byte UndecoratedSmoothedPWDB +void +odm_refresh_ldpc_rts_mp( + struct _ADAPTER *p_adapter, + struct PHY_DM_STRUCT *p_dm_odm, + u8 m_mac_id, + u8 iot_peer, + s32 undecorated_smoothed_pwdb ) { - BOOLEAN bCtlLdpc = FALSE; - PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; + boolean is_ctl_ldpc = false; + struct _ODM_RATE_ADAPTIVE *p_ra = &p_dm_odm->rate_adaptive; - if (pDM_Odm->SupportICType != ODM_RTL8821 && pDM_Odm->SupportICType != ODM_RTL8812) + if (p_dm_odm->support_ic_type != ODM_RTL8821 && p_dm_odm->support_ic_type != ODM_RTL8812) return; - if ((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A)) - bCtlLdpc = TRUE; - else if (pDM_Odm->SupportICType == ODM_RTL8812 && - IOTPeer == HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP) - bCtlLdpc = TRUE; + if ((p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->cut_version == ODM_CUT_A)) + is_ctl_ldpc = true; + else if (p_dm_odm->support_ic_type == ODM_RTL8812 && + iot_peer == HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP) + is_ctl_ldpc = true; - if (bCtlLdpc) { - if (UndecoratedSmoothedPWDB < (pRA->LdpcThres - 5)) - MgntSet_TX_LDPC(pAdapter, mMacId, TRUE); - else if (UndecoratedSmoothedPWDB > pRA->LdpcThres) - MgntSet_TX_LDPC(pAdapter, mMacId, FALSE); + if (is_ctl_ldpc) { + if (undecorated_smoothed_pwdb < (p_ra->ldpc_thres - 5)) + MgntSet_TX_LDPC(p_adapter, m_mac_id, true); + else if (undecorated_smoothed_pwdb > p_ra->ldpc_thres) + MgntSet_TX_LDPC(p_adapter, m_mac_id, false); } - if (UndecoratedSmoothedPWDB < (pRA->RtsThres - 5)) - pRA->bLowerRtsRate = TRUE; - else if (UndecoratedSmoothedPWDB > pRA->RtsThres) - pRA->bLowerRtsRate = FALSE; + if (undecorated_smoothed_pwdb < (p_ra->rts_thres - 5)) + p_ra->is_lower_rts_rate = true; + else if (undecorated_smoothed_pwdb > p_ra->rts_thres) + p_ra->is_lower_rts_rate = false; } #if 0 -VOID -ODM_DynamicARFBSelect( - IN PVOID pDM_VOID, - IN u1Byte rate, - IN BOOLEAN Collision_State +void +odm_dynamic_arfb_select( + void *p_dm_void, + u8 rate, + boolean collision_state ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - if (pDM_Odm->SupportICType != ODM_RTL8192E) + if (p_dm_odm->support_ic_type != ODM_RTL8192E) return; - if (Collision_State == pRA_Table->PT_collision_pre) + if (collision_state == p_ra_table->PT_collision_pre) return; if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS12) { - if (Collision_State == 1) { + if (collision_state == 1) { if (rate == DESC_RATEMCS12) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060501); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07060501); } else if (rate == DESC_RATEMCS11) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07070605); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07070605); } else if (rate == DESC_RATEMCS10) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08080706); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08080706); } else if (rate == DESC_RATEMCS9) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08080707); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08080707); } else { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09090808); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09090808); } - } else { /* Collision_State == 0*/ + } else { /* collision_state == 0*/ if (rate == DESC_RATEMCS12) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x05010000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080706); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x05010000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09080706); } else if (rate == DESC_RATEMCS11) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x06050000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080807); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x06050000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09080807); } else if (rate == DESC_RATEMCS10) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x07060000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0a090908); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x07060000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x0a090908); } else if (rate == DESC_RATEMCS9) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x07070000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0a090808); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x07070000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x0a090808); } else { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x08080000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0b0a0909); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x08080000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x0b0a0909); } } } else { /* MCS13~MCS15, 1SS, G-mode*/ - if (Collision_State == 1) { + if (collision_state == 1) { if (rate == DESC_RATEMCS15) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x05040302); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x05040302); } else if (rate == DESC_RATEMCS14) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x06050302); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x06050302); } else if (rate == DESC_RATEMCS13) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060502); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07060502); } else { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x06050402); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x06050402); } - } else { // Collision_State == 0 + } else { /* collision_state == 0 */ if (rate == DESC_RATEMCS15) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x03020000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060504); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x03020000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07060504); } else if (rate == DESC_RATEMCS14) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x03020000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08070605); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x03020000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08070605); } else if (rate == DESC_RATEMCS13) { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x05020000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080706); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x05020000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09080706); } else { - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x04020000); - ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08070605); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x04020000); + odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08070605); } } } - pRA_Table->PT_collision_pre = Collision_State; + p_ra_table->PT_collision_pre = collision_state; } #endif -VOID -ODM_RateAdaptiveStateApInit( - IN PVOID PADAPTER_VOID, - IN PRT_WLAN_STA pEntry +void +odm_rate_adaptive_state_ap_init( + void *PADAPTER_VOID, + struct sta_info *p_entry ) { - PADAPTER Adapter = (PADAPTER)PADAPTER_VOID; - pEntry->Ratr_State = DM_RATR_STA_INIT; + struct _ADAPTER *adapter = (struct _ADAPTER *)PADAPTER_VOID; + p_entry->Ratr_State = DM_RATR_STA_INIT; } + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ static void -FindMinimumRSSI( - IN PADAPTER pAdapter +find_minimum_rssi( + struct _ADAPTER *p_adapter ) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct PHY_DM_STRUCT *p_dm_odm = &(p_hal_data->odmpriv); /*Determine the minimum RSSI*/ - if ((pDM_Odm->bLinked != _TRUE) && - (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) { - pHalData->MinUndecoratedPWDBForDM = 0; - /*ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any\n"));*/ + if ((p_dm_odm->is_linked != _TRUE) && + (p_hal_data->entry_min_undecorated_smoothed_pwdb == 0)) { + p_hal_data->min_undecorated_pwdb_for_dm = 0; + /*ODM_RT_TRACE(p_dm_odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any\n"));*/ } else - pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; + p_hal_data->min_undecorated_pwdb_for_dm = p_hal_data->entry_min_undecorated_smoothed_pwdb; - /*DBG_8192C("%s=>MinUndecoratedPWDBForDM(%d)\n",__FUNCTION__,pdmpriv->MinUndecoratedPWDBForDM);*/ - /*ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM));*/ + /*DBG_8192C("%s=>min_undecorated_pwdb_for_dm(%d)\n",__FUNCTION__,pdmpriv->min_undecorated_pwdb_for_dm);*/ + /*ODM_RT_TRACE(p_dm_odm,COMP_DIG, DBG_LOUD, ("min_undecorated_pwdb_for_dm =%d\n",p_hal_data->min_undecorated_pwdb_for_dm));*/ } -u8Byte -PhyDM_Get_Rate_Bitmap_Ex( - IN PVOID pDM_VOID, - IN u4Byte macid, - IN u8Byte ra_mask, - IN u1Byte rssi_level, - OUT u8Byte *dm_RA_Mask, - OUT u1Byte *dm_RteID +u64 +phydm_get_rate_bitmap_ex( + void *p_dm_void, + u32 macid, + u64 ra_mask, + u8 rssi_level, + u64 *dm_ra_mask, + u8 *dm_rte_id ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PSTA_INFO_T pEntry; - u8Byte rate_bitmap = 0; - u1Byte WirelessMode; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct sta_info *p_entry; + u64 rate_bitmap = 0; + u8 wireless_mode; - pEntry = pDM_Odm->pODM_StaInfo[macid]; - if (!IS_STA_VALID(pEntry)) + p_entry = p_dm_odm->p_odm_sta_info[macid]; + if (!IS_STA_VALID(p_entry)) return ra_mask; - WirelessMode = pEntry->wireless_mode; - switch (WirelessMode) { + wireless_mode = p_entry->wireless_mode; + switch (wireless_mode) { case ODM_WM_B: if (ra_mask & 0x000000000000000c) /* 11M or 5.5M enable */ rate_bitmap = 0x000000000000000d; @@ -3018,25 +3250,26 @@ PhyDM_Get_Rate_Bitmap_Ex( case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): case (ODM_WM_B|ODM_WM_N24G): case (ODM_WM_G|ODM_WM_N24G): - case (ODM_WM_A|ODM_WM_N5G): { - if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { + case (ODM_WM_A|ODM_WM_N5G): + { + if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) { if (rssi_level == DM_RATR_STA_HIGH) rate_bitmap = 0x00000000000f0000; else if (rssi_level == DM_RATR_STA_MIDDLE) rate_bitmap = 0x00000000000ff000; else { - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + if (*(p_dm_odm->p_band_width) == ODM_BW40M) rate_bitmap = 0x00000000000ff015; else rate_bitmap = 0x00000000000ff005; } - } else if (pDM_Odm->RFType == ODM_2T2R || pDM_Odm->RFType == ODM_2T3R || pDM_Odm->RFType == ODM_2T4R) { + } else if (p_dm_odm->rf_type == ODM_2T2R || p_dm_odm->rf_type == ODM_2T3R || p_dm_odm->rf_type == ODM_2T4R) { if (rssi_level == DM_RATR_STA_HIGH) rate_bitmap = 0x000000000f8f0000; else if (rssi_level == DM_RATR_STA_MIDDLE) rate_bitmap = 0x000000000f8ff000; else { - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + if (*(p_dm_odm->p_band_width) == ODM_BW40M) rate_bitmap = 0x000000000f8ff015; else rate_bitmap = 0x000000000f8ff005; @@ -3047,7 +3280,7 @@ PhyDM_Get_Rate_Bitmap_Ex( else if (rssi_level == DM_RATR_STA_MIDDLE) rate_bitmap = 0x0000000fcfcfe000; else { - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + if (*(p_dm_odm->p_band_width) == ODM_BW40M) rate_bitmap = 0x0000000ffffff015; else rate_bitmap = 0x0000000ffffff005; @@ -3067,14 +3300,14 @@ PhyDM_Get_Rate_Bitmap_Ex( case (ODM_WM_AC|ODM_WM_A): - if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { + if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) { if (rssi_level == 1) /* add by Gary for ac-series */ rate_bitmap = 0x00000000003f8000; else if (rssi_level == 2) rate_bitmap = 0x00000000003fe000; else rate_bitmap = 0x00000000003ff010; - } else if (pDM_Odm->RFType == ODM_2T2R || pDM_Odm->RFType == ODM_2T3R || pDM_Odm->RFType == ODM_2T4R) { + } else if (p_dm_odm->rf_type == ODM_2T2R || p_dm_odm->rf_type == ODM_2T3R || p_dm_odm->rf_type == ODM_2T4R) { if (rssi_level == 1) /* add by Gary for ac-series */ rate_bitmap = 0x00000000fe3f8000; /* VHT 2SS MCS3~9 */ else if (rssi_level == 2) @@ -3092,45 +3325,45 @@ PhyDM_Get_Rate_Bitmap_Ex( break; default: - if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) + if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) rate_bitmap = 0x00000000000fffff; - else if (pDM_Odm->RFType == ODM_2T2R || pDM_Odm->RFType == ODM_2T3R || pDM_Odm->RFType == ODM_2T4R) + else if (p_dm_odm->rf_type == ODM_2T2R || p_dm_odm->rf_type == ODM_2T3R || p_dm_odm->rf_type == ODM_2T4R) rate_bitmap = 0x000000000fffffff; else rate_bitmap = 0x0000003fffffffffULL; break; } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%016llx\n", rssi_level, WirelessMode, rate_bitmap)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%016llx\n", rssi_level, wireless_mode, rate_bitmap)); - return (ra_mask & rate_bitmap); + return ra_mask & rate_bitmap; } -u4Byte -ODM_Get_Rate_Bitmap( - IN PVOID pDM_VOID, - IN u4Byte macid, - IN u4Byte ra_mask, - IN u1Byte rssi_level +u32 +odm_get_rate_bitmap( + void *p_dm_void, + u32 macid, + u32 ra_mask, + u8 rssi_level ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PSTA_INFO_T pEntry; - u4Byte rate_bitmap = 0; - u1Byte WirelessMode; - //u1Byte WirelessMode =*(pDM_Odm->pWirelessMode); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct sta_info *p_entry; + u32 rate_bitmap = 0; + u8 wireless_mode; + /* u8 wireless_mode =*(p_dm_odm->p_wireless_mode); */ - pEntry = pDM_Odm->pODM_StaInfo[macid]; - if (!IS_STA_VALID(pEntry)) + p_entry = p_dm_odm->p_odm_sta_info[macid]; + if (!IS_STA_VALID(p_entry)) return ra_mask; - WirelessMode = pEntry->wireless_mode; + wireless_mode = p_entry->wireless_mode; - switch (WirelessMode) { + switch (wireless_mode) { case ODM_WM_B: - if (ra_mask & 0x0000000c) //11M or 5.5M enable + if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ rate_bitmap = 0x0000000d; else rate_bitmap = 0x0000000f; @@ -3153,17 +3386,18 @@ ODM_Get_Rate_Bitmap( rate_bitmap = 0x00000ff5; break; - case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G) : - case (ODM_WM_B|ODM_WM_N24G) : - case (ODM_WM_G|ODM_WM_N24G) : - case (ODM_WM_A|ODM_WM_N5G) : { - if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { + case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): + case (ODM_WM_B|ODM_WM_N24G): + case (ODM_WM_G|ODM_WM_N24G): + case (ODM_WM_A|ODM_WM_N5G): + { + if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) { if (rssi_level == DM_RATR_STA_HIGH) rate_bitmap = 0x000f0000; else if (rssi_level == DM_RATR_STA_MIDDLE) rate_bitmap = 0x000ff000; else { - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + if (*(p_dm_odm->p_band_width) == ODM_BW40M) rate_bitmap = 0x000ff015; else rate_bitmap = 0x000ff005; @@ -3174,7 +3408,7 @@ ODM_Get_Rate_Bitmap( else if (rssi_level == DM_RATR_STA_MIDDLE) rate_bitmap = 0x0f8ff000; else { - if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + if (*(p_dm_odm->p_band_width) == ODM_BW40M) rate_bitmap = 0x0f8ff015; else rate_bitmap = 0x0f8ff005; @@ -3194,25 +3428,25 @@ ODM_Get_Rate_Bitmap( case (ODM_WM_AC|ODM_WM_A): - if (pDM_Odm->RFType == RF_1T1R) { - if (rssi_level == 1) // add by Gary for ac-series + if (p_dm_odm->rf_type == RF_1T1R) { + if (rssi_level == 1) /* add by Gary for ac-series */ rate_bitmap = 0x003f8000; else if (rssi_level == 2) rate_bitmap = 0x003ff000; else rate_bitmap = 0x003ff010; } else { - if (rssi_level == 1) // add by Gary for ac-series - rate_bitmap = 0xfe3f8000; // VHT 2SS MCS3~9 + if (rssi_level == 1) /* add by Gary for ac-series */ + rate_bitmap = 0xfe3f8000; /* VHT 2SS MCS3~9 */ else if (rssi_level == 2) - rate_bitmap = 0xfffff000; // VHT 2SS MCS0~9 + rate_bitmap = 0xfffff000; /* VHT 2SS MCS0~9 */ else - rate_bitmap = 0xfffff010; // All + rate_bitmap = 0xfffff010; /* All */ } break; default: - if (pDM_Odm->RFType == RF_1T2R) + if (p_dm_odm->rf_type == RF_1T2R) rate_bitmap = 0x000fffff; else rate_bitmap = 0x0fffffff; @@ -3220,50 +3454,17 @@ ODM_Get_Rate_Bitmap( } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", __func__, rssi_level, WirelessMode, rate_bitmap)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", rssi_level, WirelessMode, rate_bitmap)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%08x\n", __func__, rssi_level, wireless_mode, rate_bitmap)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%08x\n", rssi_level, wireless_mode, rate_bitmap)); - return (ra_mask & rate_bitmap); + return ra_mask & rate_bitmap; } -#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -VOID -phydm_gen_ramask_h2c_AP( - IN PVOID pDM_VOID, - IN struct rtl8192cd_priv *priv, - IN PSTA_INFO_T *pEntry, - IN u1Byte rssi_level -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & (ODM_RTL8192E | ODM_RTL8881A)) { - - #ifdef CONFIG_WLAN_HAL - GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, pEntry, rssi_level); - #endif - - } else if (pDM_Odm->SupportICType == ODM_RTL8812) { - - #if (RTL8812A_SUPPORT == 1) - UpdateHalRAMask8812(priv, pEntry, rssi_level); - /**/ - #endif - } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { - - #if (RTL8188E_SUPPORT == 1) - #ifdef TXREPORT - add_RATid(priv, pEntry); - /**/ - #endif - #endif - } -} - #endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ @@ -3272,87 +3473,85 @@ phydm_gen_ramask_h2c_AP( #if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN) -BOOLEAN -ODM_RAStateCheck( - IN PVOID pDM_VOID, - IN s4Byte RSSI, - IN BOOLEAN bForceUpdate, - OUT pu1Byte pRATRState +boolean +odm_ra_state_check( + void *p_dm_void, + s32 RSSI, + boolean is_force_update, + u8 *p_ra_tr_state ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; - const u1Byte GoUpGap = 5; - u1Byte HighRSSIThreshForRA = pRA->HighRSSIThresh; - u1Byte LowRSSIThreshForRA = pRA->LowRSSIThresh; - u1Byte RATRState; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI= (( %d )), Current_RSSI_level = (( %d ))\n", RSSI, *pRATRState)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Ori RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", HighRSSIThreshForRA, LowRSSIThreshForRA)); - /* Threshold Adjustment:*/ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ODM_RATE_ADAPTIVE *p_ra = &p_dm_odm->rate_adaptive; + const u8 go_up_gap = 5; + u8 high_rssi_thresh_for_ra = p_ra->high_rssi_thresh; + u8 low_rssi_thresh_for_ra = p_ra->low_rssi_thresh; + u8 ratr_state; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI= (( %d )), Current_RSSI_level = (( %d ))\n", RSSI, *p_ra_tr_state)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Ori RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", high_rssi_thresh_for_ra, low_rssi_thresh_for_ra)); + /* threshold Adjustment:*/ /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough.*/ - /* Here GoUpGap is added to solve the boundary's level alternation issue.*/ + /* Here go_up_gap is added to solve the boundary's level alternation issue.*/ #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u1Byte UltraLowRSSIThreshForRA = pRA->UltraLowRSSIThresh; + u8 ultra_low_rssi_thresh_for_ra = p_ra->ultra_low_rssi_thresh; - if (pDM_Odm->SupportICType == ODM_RTL8881A) - LowRSSIThreshForRA = 30; /* for LDPC / BCC switch*/ + if (p_dm_odm->support_ic_type == ODM_RTL8881A) + low_rssi_thresh_for_ra = 30; /* for LDPC / BCC switch*/ #endif - switch (*pRATRState) { + switch (*p_ra_tr_state) { case DM_RATR_STA_INIT: case DM_RATR_STA_HIGH: break; case DM_RATR_STA_MIDDLE: - HighRSSIThreshForRA += GoUpGap; + high_rssi_thresh_for_ra += go_up_gap; break; case DM_RATR_STA_LOW: - HighRSSIThreshForRA += GoUpGap; - LowRSSIThreshForRA += GoUpGap; + high_rssi_thresh_for_ra += go_up_gap; + low_rssi_thresh_for_ra += go_up_gap; break; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) case DM_RATR_STA_ULTRA_LOW: - HighRSSIThreshForRA += GoUpGap; - LowRSSIThreshForRA += GoUpGap; - UltraLowRSSIThreshForRA += GoUpGap; + high_rssi_thresh_for_ra += go_up_gap; + low_rssi_thresh_for_ra += go_up_gap; + ultra_low_rssi_thresh_for_ra += go_up_gap; break; #endif default: - ODM_RT_ASSERT(pDM_Odm, FALSE, ("wrong rssi level setting %d !", *pRATRState)); + ODM_RT_ASSERT(p_dm_odm, false, ("wrong rssi level setting %d !", *p_ra_tr_state)); break; } - /* Decide RATRState by RSSI.*/ - if (RSSI > HighRSSIThreshForRA) - RATRState = DM_RATR_STA_HIGH; - else if (RSSI > LowRSSIThreshForRA) - RATRState = DM_RATR_STA_MIDDLE; + /* Decide ratr_state by RSSI.*/ + if (RSSI > high_rssi_thresh_for_ra) + ratr_state = DM_RATR_STA_HIGH; + else if (RSSI > low_rssi_thresh_for_ra) + ratr_state = DM_RATR_STA_MIDDLE; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - else if (RSSI > UltraLowRSSIThreshForRA) - RATRState = DM_RATR_STA_LOW; + else if (RSSI > ultra_low_rssi_thresh_for_ra) + ratr_state = DM_RATR_STA_LOW; else - RATRState = DM_RATR_STA_ULTRA_LOW; + ratr_state = DM_RATR_STA_ULTRA_LOW; #else else - RATRState = DM_RATR_STA_LOW; + ratr_state = DM_RATR_STA_LOW; #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Mod RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", HighRSSIThreshForRA, LowRSSIThreshForRA)); - /*printk("==>%s,RATRState:0x%02x ,RSSI:%d\n",__FUNCTION__,RATRState,RSSI);*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Mod RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", high_rssi_thresh_for_ra, low_rssi_thresh_for_ra)); + /*printk("==>%s,ratr_state:0x%02x,RSSI:%d\n",__FUNCTION__,ratr_state,RSSI);*/ - if (*pRATRState != RATRState || bForceUpdate) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[RSSI Level Update] %d -> %d\n", *pRATRState, RATRState)); - *pRATRState = RATRState; - return TRUE; + if (*p_ra_tr_state != ratr_state || is_force_update) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[RSSI Level Update] %d->%d\n", *p_ra_tr_state, ratr_state)); + *p_ra_tr_state = ratr_state; + return true; } - return FALSE; + return false; } #endif - - diff --git a/hal/phydm/phydm_rainfo.h b/hal/phydm/phydm_rainfo.h index 76ba36f..82d58cb 100644 --- a/hal/phydm/phydm_rainfo.h +++ b/hal/phydm/phydm_rainfo.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PHYDMRAINFO_H__ #define __PHYDMRAINFO_H__ @@ -27,27 +22,32 @@ /*#define RAINFO_VERSION "3.3" 2015.07.29 YuChen*/ /*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/ /*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */ -#define RAINFO_VERSION "4.1" /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */ +/*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */ +/*#define RAINFO_VERSION "4.2"*/ /*2016.05.17 Dino, Add H2C debug cmd */ +#define RAINFO_VERSION "4.3" /*2016.07.11 Dino, Fix RA hang in CCK 1M problem */ + +#define FORCED_UPDATE_RAMASK_PERIOD 5 #define H2C_0X42_LENGTH 5 +#define H2C_MAX_LENGTH 7 -#define RA_FLOOR_UP_GAP 3 +#define RA_FLOOR_UP_GAP 3 #define RA_FLOOR_TABLE_SIZE 7 -#define ACTIVE_TP_THRESHOLD 150 +#define ACTIVE_TP_THRESHOLD 1 #define RA_RETRY_DESCEND_NUM 2 #define RA_RETRY_LIMIT_LOW 4 #define RA_RETRY_LIMIT_HIGH 32 -#define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL -#define RAINFO_STBC_STATE BIT1 -//#define RAINFO_LDPC_STATE BIT2 -#define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection -#define RAINFO_SHURTCUT_STATE BIT3 -#define RAINFO_SHURTCUT_FLAG BIT4 -#define RAINFO_INIT_RSSI_RATE_STATE BIT5 -#define RAINFO_BF_STATE BIT6 -#define RAINFO_BE_TX_STATE BIT7 // 1:TX +#define RAINFO_BE_RX_STATE BIT(0) /* 1:RX */ /* ULDL */ +#define RAINFO_STBC_STATE BIT(1) +/* #define RAINFO_LDPC_STATE BIT2 */ +#define RAINFO_NOISY_STATE BIT(2) /* set by Noisy_Detection */ +#define RAINFO_SHURTCUT_STATE BIT(3) +#define RAINFO_SHURTCUT_FLAG BIT(4) +#define RAINFO_INIT_RSSI_RATE_STATE BIT(5) +#define RAINFO_BF_STATE BIT(6) +#define RAINFO_BE_TX_STATE BIT(7) /* 1:TX */ #define RA_MASK_CCK 0xf #define RA_MASK_OFDM 0xff0 @@ -58,46 +58,50 @@ #define RA_MASK_VHT1SS 0x3ff000 #define RA_MASK_VHT2SS 0xffc00000 -#if(DM_ODM_SUPPORT_TYPE == ODM_AP) -#define RA_FIRST_MACID 1 +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #define RA_FIRST_MACID 1 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#define RA_FIRST_MACID 0 -#define WIN_DEFAULT_PORT_MACID 0 -#define WIN_BT_PORT_MACID 2 + #define RA_FIRST_MACID 0 + #define WIN_DEFAULT_PORT_MACID 0 + #define WIN_BT_PORT_MACID 2 #else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ -#define RA_FIRST_MACID 0 + #define RA_FIRST_MACID 0 #endif -#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#define AP_InitRateAdaptiveState odm_rate_adaptive_state_ap_init +#else +#define ap_init_rate_adaptive_state odm_rate_adaptive_state_ap_init +#endif #if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN) -#define DM_RATR_STA_INIT 0 -#define DM_RATR_STA_HIGH 1 -#define DM_RATR_STA_MIDDLE 2 -#define DM_RATR_STA_LOW 3 -#define DM_RATR_STA_ULTRA_LOW 4 + #define DM_RATR_STA_INIT 0 + #define DM_RATR_STA_HIGH 1 + #define DM_RATR_STA_MIDDLE 2 + #define DM_RATR_STA_LOW 3 + #define DM_RATR_STA_ULTRA_LOW 4 #endif -typedef enum _phydm_arfr_num { +enum phydm_ra_arfr_num_e { ARFR_0_RATE_ID = 0x9, ARFR_1_RATE_ID = 0xa, ARFR_2_RATE_ID = 0xb, ARFR_3_RATE_ID = 0xc, ARFR_4_RATE_ID = 0xd, ARFR_5_RATE_ID = 0xe -} PHYDM_RA_ARFR_NUM_E; +}; -typedef enum _Phydm_ra_dbg_para { +enum phydm_ra_dbg_para_e { RADBG_PCR_TH_OFFSET = 0, RADBG_RTY_PENALTY = 1, - RADBG_N_HIGH = 2, + RADBG_N_HIGH = 2, RADBG_N_LOW = 3, RADBG_TRATE_UP_TABLE = 4, RADBG_TRATE_DOWN_TABLE = 5, RADBG_TRYING_NECESSARY = 6, RADBG_TDROPING_NECESSARY = 7, RADBG_RATE_UP_RTY_RATIO = 8, - RADBG_RATE_DOWN_RTY_RATIO = 9, //u8 + RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */ RADBG_DEBUG_MONITOR1 = 0xc, RADBG_DEBUG_MONITOR2 = 0xd, @@ -105,10 +109,10 @@ typedef enum _Phydm_ra_dbg_para { RADBG_DEBUG_MONITOR4 = 0xf, RADBG_DEBUG_MONITOR5 = 0x10, NUM_RA_PARA -} PHYDM_RA_DBG_PARA_E; +}; + +enum phydm_wireless_mode_e { -typedef enum PHYDM_WIRELESS_MODE { - PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, PHYDM_WIRELESS_MODE_A = 0x01, PHYDM_WIRELESS_MODE_B = 0x02, @@ -121,10 +125,10 @@ typedef enum PHYDM_WIRELESS_MODE { PHYDM_WIRELESS_MODE_AC_ONLY = 0x100, PHYDM_WIRELESS_MODE_MAX = 0x800, PHYDM_WIRELESS_MODE_ALL = 0xFFFF -} PHYDM_WIRELESS_MODE_E; +}; + +enum phydm_rateid_idx_e { -typedef enum PHYDM_RATEID_IDX_ { - PHYDM_BGN_40M_2SS = 0, PHYDM_BGN_40M_1SS = 1, PHYDM_BGN_20M_2SS = 2, @@ -140,11 +144,11 @@ typedef enum PHYDM_RATEID_IDX_ { PHYDM_ARFR3_AC_2G_2SS = 12, PHYDM_ARFR4_AC_3SS = 13, PHYDM_ARFR5_N_3SS = 14 -} PHYDM_RATEID_IDX_E; +}; -typedef enum _PHYDM_RF_TYPE_DEFINITION { +enum phydm_rf_type_def_e { PHYDM_RF_1T1R = 0, - PHYDM_RF_1T2R, + PHYDM_RF_1T2R, PHYDM_RF_2T2R, PHYDM_RF_2T2R_GREEN, PHYDM_RF_2T3R, @@ -153,413 +157,430 @@ typedef enum _PHYDM_RF_TYPE_DEFINITION { PHYDM_RF_3T4R, PHYDM_RF_4T4R, PHYDM_RF_MAX_TYPE -} PHYDM_RF_TYPE_DEF_E; +}; -typedef enum _PHYDM_BW { +enum phydm_bw_e { PHYDM_BW_20 = 0, PHYDM_BW_40, PHYDM_BW_80, - PHYDM_BW_80_80, + PHYDM_BW_80_80, PHYDM_BW_160, PHYDM_BW_10, PHYDM_BW_5 -} PHYDM_BW_E; - - -#if (RATE_ADAPTIVE_SUPPORT == 1)//88E RA -typedef struct _ODM_RA_Info_ { - u1Byte RateID; - u4Byte RateMask; - u4Byte RAUseRate; - u1Byte RateSGI; - u1Byte RssiStaRA; - u1Byte PreRssiStaRA; - u1Byte SGIEnable; - u1Byte DecisionRate; - u1Byte PreRate; - u1Byte HighestRate; - u1Byte LowestRate; - u4Byte NscUp; - u4Byte NscDown; - u2Byte RTY[5]; - u4Byte TOTAL; - u2Byte DROP; - u1Byte Active; - u2Byte RptTime; - u1Byte RAWaitingCounter; - u1Byte RAPendingCounter; - u1Byte RADropAfterDown; -#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~! - u1Byte PTActive; // on or off - u1Byte PTTryState; // 0 trying state, 1 for decision state - u1Byte PTStage; // 0~6 - u1Byte PTStopCount; //Stop PT counter - u1Byte PTPreRate; // if rate change do PT - u1Byte PTPreRssi; // if RSSI change 5% do PT - u1Byte PTModeSS; // decide whitch rate should do PT - u1Byte RAstage; // StageRA, decide how many times RA will be done between PT - u1Byte PTSmoothFactor; +}; + + +#if (RATE_ADAPTIVE_SUPPORT == 1)/* 88E RA */ +struct _odm_ra_info_ { + u8 rate_id; + u32 rate_mask; + u32 ra_use_rate; + u8 rate_sgi; + u8 rssi_sta_ra; + u8 pre_rssi_sta_ra; + u8 sgi_enable; + u8 decision_rate; + u8 pre_rate; + u8 highest_rate; + u8 lowest_rate; + u32 nsc_up; + u32 nsc_down; + u16 RTY[5]; + u32 TOTAL; + u16 DROP; + u8 active; + u16 rpt_time; + u8 ra_waiting_counter; + u8 ra_pending_counter; + u8 ra_drop_after_down; +#if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile pass only~! */ + u8 pt_active; /* on or off */ + u8 pt_try_state; /* 0 trying state, 1 for decision state */ + u8 pt_stage; /* 0~6 */ + u8 pt_stop_count; /* Stop PT counter */ + u8 pt_pre_rate; /* if rate change do PT */ + u8 pt_pre_rssi; /* if RSSI change 5% do PT */ + u8 pt_mode_ss; /* decide whitch rate should do PT */ + u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */ + u8 pt_smooth_factor; #endif -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - u1Byte RateDownCounter; - u1Byte RateUpCounter; - u1Byte RateDirection; - u1Byte BoundingType; - u1Byte BoundingCounter; - u1Byte BoundingLearningTime; - u1Byte RateDownStartTime; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + u8 rate_down_counter; + u8 rate_up_counter; + u8 rate_direction; + u8 bounding_type; + u8 bounding_counter; + u8 bounding_learning_time; + u8 rate_down_start_time; #endif -} ODM_RA_INFO_T, *PODM_RA_INFO_T; +}; #endif -typedef struct _Rate_Adaptive_Table_ { - u1Byte firstconnect; -#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) - BOOLEAN PT_collision_pre; +struct _rate_adaptive_table_ { + u8 firstconnect; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + boolean PT_collision_pre; #endif #if (defined(CONFIG_RA_DBG_CMD)) - BOOLEAN is_ra_dbg_init; + boolean is_ra_dbg_init; - u1Byte RTY_P[ODM_NUM_RATE_IDX]; - u1Byte RTY_P_default[ODM_NUM_RATE_IDX]; - BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX]; + u8 RTY_P[ODM_NUM_RATE_IDX]; + u8 RTY_P_default[ODM_NUM_RATE_IDX]; + boolean RTY_P_modify_note[ODM_NUM_RATE_IDX]; - u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX]; - u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX]; - BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; + u8 RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX]; + u8 RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX]; + boolean RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; - u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX]; - u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX]; - BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; + u8 RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX]; + u8 RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX]; + boolean RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; - BOOLEAN RA_Para_feedback_req; + boolean ra_para_feedback_req; - u1Byte para_idx; - u1Byte rate_idx; - u1Byte value; - u2Byte value_16; - u1Byte rate_length; + u8 para_idx; + u8 rate_idx; + u8 value; + u16 value_16; + u8 rate_length; +#endif + u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM]; + u8 highest_client_tx_order; + u16 highest_client_tx_rate_order; + u8 power_tracking_flag; + u8 RA_threshold_offset; + u8 RA_offset_direction; + u8 force_update_ra_mask_count; + +#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) + u8 per_rate_retrylimit_20M[ODM_NUM_RATE_IDX]; + u8 per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; + u8 retry_descend_num; + u8 retrylimit_low; + u8 retrylimit_high; #endif - u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM]; - u1Byte highest_client_tx_order; - u2Byte highest_client_tx_rate_order; - u1Byte power_tracking_flag; - u1Byte RA_threshold_offset; - u1Byte RA_offset_direction; - - #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX]; - u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; - u1Byte retry_descend_num; - u1Byte retrylimit_low; - u1Byte retrylimit_high; - #endif - - -} RA_T, *pRA_T; - -typedef struct _ODM_RATE_ADAPTIVE { - u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver - u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH - u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW - u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW - -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC - BOOLEAN bLowerRtsRate; + + +}; + +struct _ODM_RATE_ADAPTIVE { + u8 type; /* dm_type_by_fw/dm_type_by_driver */ + u8 high_rssi_thresh; /* if RSSI > high_rssi_thresh => ratr_state is DM_RATR_STA_HIGH */ + u8 low_rssi_thresh; /* if RSSI <= low_rssi_thresh => ratr_state is DM_RATR_STA_LOW */ + u8 ratr_state; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + u8 ldpc_thres; /* if RSSI > ldpc_thres => switch from LPDC to BCC */ + boolean is_lower_rts_rate; #endif -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - u1Byte RtsThres; -#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) - BOOLEAN bUseLdpc; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + u8 rts_thres; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + boolean is_use_ldpc; #else - u1Byte UltraLowRSSIThresh; - u4Byte LastRATR; // RATR Register Content + u8 ultra_low_rssi_thresh; + u32 last_ratr; /* RATR Register Content */ #endif -} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; +}; + +void +phydm_h2C_debug( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); #if (defined(CONFIG_RA_DBG_CMD)) -VOID +void odm_RA_debug( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value + void *p_dm_void, + u32 *const dm_value ); -VOID -odm_RA_ParaAdjust_init( - IN PVOID pDM_VOID +void +odm_ra_para_adjust_init( + void *p_dm_void ); #else -VOID +void phydm_RA_debug_PCR( - IN PVOID pDM_VOID, - IN u4Byte *const dm_value, - IN u4Byte *_used, - OUT char *output, - IN u4Byte *_out_len + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len ); #endif -VOID -ODM_C2HRaParaReportHandler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen +void +odm_c2h_ra_para_report_handler( + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len ); -VOID -odm_RA_ParaAdjust( - IN PVOID pDM_VOID +void +odm_ra_para_adjust( + void *p_dm_void ); -VOID +void phydm_ra_dynamic_retry_count( - IN PVOID pDM_VOID + void *p_dm_void ); -VOID +void phydm_ra_dynamic_retry_limit( - IN PVOID pDM_VOID + void *p_dm_void ); -VOID +void phydm_ra_dynamic_rate_id_on_assoc( - IN PVOID pDM_VOID, - IN u1Byte wireless_mode, - IN u1Byte init_rate_id + void *p_dm_void, + u8 wireless_mode, + u8 init_rate_id ); -VOID +void phydm_print_rate( - IN PVOID pDM_VOID, - IN u1Byte rate, - IN u4Byte dbg_component + void *p_dm_void, + u8 rate, + u32 dbg_component ); -VOID +void phydm_c2h_ra_report_handler( - IN PVOID pDM_VOID, - IN pu1Byte CmdBuf, - IN u1Byte CmdLen + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len ); -u1Byte +u8 phydm_rate_order_compute( - IN PVOID pDM_VOID, - IN u1Byte rate_idx - ); + void *p_dm_void, + u8 rate_idx +); -VOID +void phydm_ra_info_watchdog( - IN PVOID pDM_VOID + void *p_dm_void ); -VOID +void phydm_ra_info_init( - IN PVOID pDM_VOID + void *p_dm_void +); + +void +odm_rssi_monitor_init( + void *p_dm_void ); -VOID -odm_RSSIMonitorInit( - IN PVOID pDM_VOID +void +phydm_modify_RA_PCR_threshold( + void *p_dm_void, + u8 RA_offset_direction, + u8 RA_threshold_offset ); -VOID -odm_RSSIMonitorCheck( - IN PVOID pDM_VOID +void +odm_rssi_monitor_check( + void *p_dm_void ); -VOID -phydm_initRaInfo( - IN PVOID pDM_VOID +void +phydm_init_ra_info( + void *p_dm_void ); -u1Byte +u8 phydm_vht_en_mapping( - IN PVOID pDM_VOID, - IN u4Byte WirelessMode + void *p_dm_void, + u32 wireless_mode ); -u1Byte +u8 phydm_rate_id_mapping( - IN PVOID pDM_VOID, - IN u4Byte WirelessMode, - IN u1Byte RfType, - IN u1Byte bw + void *p_dm_void, + u32 wireless_mode, + u8 rf_type, + u8 bw ); -VOID -phydm_UpdateHalRAMask( - IN PVOID pDM_VOID, - IN u4Byte wirelessMode, - IN u1Byte RfType, - IN u1Byte BW, - IN u1Byte MimoPs_enable, - IN u1Byte disable_cck_rate, - IN u4Byte *ratr_bitmap_msb_in, - IN u4Byte *ratr_bitmap_in, - IN u1Byte tx_rate_level +void +phydm_update_hal_ra_mask( + void *p_dm_void, + u32 wireless_mode, + u8 rf_type, + u8 BW, + u8 mimo_ps_enable, + u8 disable_cck_rate, + u32 *ratr_bitmap_msb_in, + u32 *ratr_bitmap_in, + u8 tx_rate_level ); -VOID -odm_RateAdaptiveMaskInit( - IN PVOID pDM_VOID +void +odm_rate_adaptive_mask_init( + void *p_dm_void ); -VOID -odm_RefreshRateAdaptiveMask( - IN PVOID pDM_VOID +void +odm_refresh_rate_adaptive_mask( + void *p_dm_void ); -VOID -odm_RefreshRateAdaptiveMaskMP( - IN PVOID pDM_VOID +void +odm_refresh_rate_adaptive_mask_mp( + void *p_dm_void ); -VOID -odm_RefreshRateAdaptiveMaskCE( - IN PVOID pDM_VOID +void +odm_refresh_rate_adaptive_mask_ce( + void *p_dm_void ); -VOID -odm_RefreshRateAdaptiveMaskAPADSL( - IN PVOID pDM_VOID +void +odm_refresh_rate_adaptive_mask_apadsl( + void *p_dm_void ); -u1Byte +u8 phydm_RA_level_decision( - IN PVOID pDM_VOID, - IN u4Byte rssi, - IN u1Byte Ratr_State + void *p_dm_void, + u32 rssi, + u8 ratr_state ); -BOOLEAN -ODM_RAStateCheck( - IN PVOID pDM_VOID, - IN s4Byte RSSI, - IN BOOLEAN bForceUpdate, - OUT pu1Byte pRATRState +boolean +odm_ra_state_check( + void *p_dm_void, + s32 RSSI, + boolean is_force_update, + u8 *p_ra_tr_state ); -VOID -odm_RefreshBasicRateMask( - IN PVOID pDM_VOID +void +odm_refresh_basic_rate_mask( + void *p_dm_void ); -VOID -ODM_RAPostActionOnAssoc( - IN PVOID pDM_Odm +void +odm_ra_post_action_on_assoc( + void *p_dm_odm ); #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -u1Byte -odm_Find_RTS_Rate( - IN PVOID pDM_VOID, - IN u1Byte Tx_Rate, - IN BOOLEAN bErpProtect +u8 +odm_find_rts_rate( + void *p_dm_void, + u8 tx_rate, + boolean is_erp_protect ); -VOID -ODM_UpdateNoisyState( - IN PVOID pDM_VOID, - IN BOOLEAN bNoisyStateFromC2H +void +odm_update_noisy_state( + void *p_dm_void, + boolean is_noisy_state_from_c2h ); -VOID +void phydm_update_pwr_track( - IN PVOID pDM_VOID, - IN u1Byte Rate + void *p_dm_void, + u8 rate ); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -s4Byte -phydm_FindMinimumRSSI( -IN PDM_ODM_T pDM_Odm, -IN PADAPTER pAdapter, -IN OUT BOOLEAN *pbLink_temp +s32 +phydm_find_minimum_rssi( + struct PHY_DM_STRUCT *p_dm_odm, + struct _ADAPTER *p_adapter, + OUT boolean *p_is_link_temp ); -VOID -ODM_UpdateInitRateWorkItemCallback( - IN PVOID pContext +void +odm_update_init_rate_work_item_callback( + void *p_context ); -VOID -odm_RSSIDumpToRegister( - IN PVOID pDM_VOID +void +odm_rssi_dump_to_register( + void *p_dm_void ); -VOID -odm_RefreshLdpcRtsMP( - IN PADAPTER pAdapter, - IN PDM_ODM_T pDM_Odm, - IN u1Byte mMacId, - IN u1Byte IOTPeer, - IN s4Byte UndecoratedSmoothedPWDB +void +odm_refresh_ldpc_rts_mp( + struct _ADAPTER *p_adapter, + struct PHY_DM_STRUCT *p_dm_odm, + u8 m_mac_id, + u8 iot_peer, + s32 undecorated_smoothed_pwdb ); #if 0 -VOID -ODM_DynamicARFBSelect( - IN PVOID pDM_VOID, - IN u1Byte rate, - IN BOOLEAN Collision_State +void +odm_dynamic_arfb_select( + void *p_dm_void, + u8 rate, + boolean collision_state ); #endif -VOID -ODM_RateAdaptiveStateApInit( - IN PVOID PADAPTER_VOID, - IN PRT_WLAN_STA pEntry +void +odm_rate_adaptive_state_ap_init( + void *PADAPTER_VOID, + struct sta_info *p_entry ); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) static void -FindMinimumRSSI( - IN PADAPTER pAdapter +find_minimum_rssi( + struct _ADAPTER *p_adapter ); -u8Byte -PhyDM_Get_Rate_Bitmap_Ex( - IN PVOID pDM_VOID, - IN u4Byte macid, - IN u8Byte ra_mask, - IN u1Byte rssi_level, - OUT u8Byte *dm_RA_Mask, - OUT u1Byte *dm_RteID +u64 +phydm_get_rate_bitmap_ex( + void *p_dm_void, + u32 macid, + u64 ra_mask, + u8 rssi_level, + u64 *dm_ra_mask, + u8 *dm_rte_id ); -u4Byte -ODM_Get_Rate_Bitmap( - IN PVOID pDM_VOID, - IN u4Byte macid, - IN u4Byte ra_mask, - IN u1Byte rssi_level +u32 +odm_get_rate_bitmap( + void *p_dm_void, + u32 macid, + u32 ra_mask, + u8 rssi_level ); -void phydm_ra_rssi_rpt_wk(PVOID pContext); +void phydm_ra_rssi_rpt_wk(void *p_context); #endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -VOID +/* +void phydm_gen_ramask_h2c_AP( - IN PVOID pDM_VOID, - IN struct rtl8192cd_priv *priv, - IN PSTA_INFO_T *pEntry, - IN u1Byte rssi_level + void *p_dm_void, + struct rtl8192cd_priv *priv, + struct sta_info *p_entry, + u8 rssi_level ); - +*/ #endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ #endif /*#ifndef __ODMRAINFO_H__*/ - - diff --git a/hal/phydm/phydm_reg.h b/hal/phydm/phydm_reg.h index 542a1b7..9bb5dde 100644 --- a/hal/phydm/phydm_reg.h +++ b/hal/phydm/phydm_reg.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,29 +11,24 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + *****************************************************************************/ +/* ************************************************************ + * File Name: odm_reg.h + * + * Description: * + * This file is for general register definition. * - ******************************************************************************/ -//============================================================ -// File Name: odm_reg.h -// -// Description: -// -// This file is for general register definition. -// -// -//============================================================ + * + * ************************************************************ */ #ifndef __HAL_ODM_REG_H__ #define __HAL_ODM_REG_H__ -// -// Register Definition -// +/* + * Register Definition + * */ -//MAC REG +/* MAC REG */ #define ODM_BB_RESET 0x002 #define ODM_DUMMY 0x4fe #define RF_T_METER_OLD 0x24 @@ -51,7 +46,7 @@ #define REG_LTECOEX_READ_DATA 0x07C8 #define REG_LTECOEX_PATH_CONTROL 0x70 -//BB REG +/* BB REG */ #define ODM_FPGA_PHY0_PAGE8 0x800 #define ODM_PSD_SETTING 0x808 #define ODM_AFE_SETTING 0x818 @@ -102,7 +97,7 @@ #define ODM_TXAGC_A_MCS8_MCS11 0xe18 #define ODM_TXAGC_A_MCS12_MCS15 0xe1c -//RF REG +/* RF REG */ #define ODM_GAIN_SETTING 0x00 #define ODM_CHANNEL 0x18 #define ODM_RF_T_METER 0x24 @@ -110,106 +105,120 @@ #define ODM_RF_T_METER_88E 0x42 #define ODM_RF_T_METER_92E 0x42 #define ODM_RF_T_METER_8812 0x42 -#define rRF_TxGainOffset 0x55 +#define REG_RF_TX_GAIN_OFFSET 0x55 -//Ant Detect Reg +/* ant Detect Reg */ #define ODM_DPDT 0x300 -//PSD Init +/* PSD Init */ #define ODM_PSDREG 0x808 -//92D Path Div +/* 92D path Div */ #define PATHDIV_REG 0xB30 #define PATHDIV_TRI 0xBA0 -// -// Bitmap Definition -// -#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) -// TX AGC -#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 -#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 -#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 -#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c -#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 -#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 -#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 -#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c -#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 -#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 -#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 -#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c -#if defined(CONFIG_WLAN_HAL_8814AE) -#define rTxAGC_A_MCS19_MCS16_JAguar 0xcd8 -#define rTxAGC_A_MCS23_MCS20_JAguar 0xcdc -#define rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 0xce0 -#define rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 0xce4 -#define rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 0xce8 -#endif -#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 -#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 -#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 -#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c -#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 -#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 -#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 -#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c -#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 -#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 -#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 -#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c -#if defined(CONFIG_WLAN_HAL_8814AE) -#define rTxAGC_B_MCS19_MCS16_JAguar 0xed8 -#define rTxAGC_B_MCS23_MCS20_JAguar 0xedc -#define rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 0xee0 -#define rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 0xee4 -#define rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 0xee8 -#define rTxAGC_C_CCK11_CCK1_JAguar 0x1820 -#define rTxAGC_C_Ofdm18_Ofdm6_JAguar 0x1824 -#define rTxAGC_C_Ofdm54_Ofdm24_JAguar 0x1828 -#define rTxAGC_C_MCS3_MCS0_JAguar 0x182c -#define rTxAGC_C_MCS7_MCS4_JAguar 0x1830 -#define rTxAGC_C_MCS11_MCS8_JAguar 0x1834 -#define rTxAGC_C_MCS15_MCS12_JAguar 0x1838 -#define rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 0x183c -#define rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 0x1840 -#define rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 0x1844 -#define rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 0x1848 -#define rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 0x184c -#define rTxAGC_C_MCS19_MCS16_JAguar 0x18d8 -#define rTxAGC_C_MCS23_MCS20_JAguar 0x18dc -#define rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 0x18e0 -#define rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 0x18e4 -#define rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 0x18e8 -#define rTxAGC_D_CCK11_CCK1_JAguar 0x1a20 -#define rTxAGC_D_Ofdm18_Ofdm6_JAguar 0x1a24 -#define rTxAGC_D_Ofdm54_Ofdm24_JAguar 0x1a28 -#define rTxAGC_D_MCS3_MCS0_JAguar 0x1a2c -#define rTxAGC_D_MCS7_MCS4_JAguar 0x1a30 -#define rTxAGC_D_MCS11_MCS8_JAguar 0x1a34 -#define rTxAGC_D_MCS15_MCS12_JAguar 0x1a38 -#define rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 0x1a3c -#define rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 0x1a40 -#define rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 0x1a44 -#define rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 0x1a48 -#define rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 0x1a4c -#define rTxAGC_D_MCS19_MCS16_JAguar 0x1ad8 -#define rTxAGC_D_MCS23_MCS20_JAguar 0x1adc -#define rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 0x1ae0 -#define rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 0x1ae4 -#define rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 0x1ae8 +/* + * Bitmap Definition + * */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + /* TX AGC */ + #define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR 0xc20 + #define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR 0xc24 + #define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR 0xc28 + #define REG_TX_AGC_A_MCS3_MCS0_JAGUAR 0xc2c + #define REG_TX_AGC_A_MCS7_MCS4_JAGUAR 0xc30 + #define REG_TX_AGC_A_MCS11_MCS8_JAGUAR 0xc34 + #define REG_TX_AGC_A_MCS15_MCS12_JAGUAR 0xc38 + #define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xc3c + #define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xc40 + #define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xc44 + #define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xc48 + #define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xc4c + #if defined(CONFIG_WLAN_HAL_8814AE) + #define REG_TX_AGC_A_MCS19_MCS16_JAGUAR 0xcd8 + #define REG_TX_AGC_A_MCS23_MCS20_JAGUAR 0xcdc + #define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xce0 + #define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xce4 + #define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xce8 + #endif + #define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR 0xe20 + #define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR 0xe24 + #define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR 0xe28 + #define REG_TX_AGC_B_MCS3_MCS0_JAGUAR 0xe2c + #define REG_TX_AGC_B_MCS7_MCS4_JAGUAR 0xe30 + #define REG_TX_AGC_B_MCS11_MCS8_JAGUAR 0xe34 + #define REG_TX_AGC_B_MCS15_MCS12_JAGUAR 0xe38 + #define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xe3c + #define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xe40 + #define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xe44 + #define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xe48 + #define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xe4c + #if defined(CONFIG_WLAN_HAL_8814AE) + #define REG_TX_AGC_B_MCS19_MCS16_JAGUAR 0xed8 + #define REG_TX_AGC_B_MCS23_MCS20_JAGUAR 0xedc + #define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xee0 + #define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xee4 + #define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xee8 + #define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR 0x1820 + #define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR 0x1824 + #define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR 0x1828 + #define REG_TX_AGC_C_MCS3_MCS0_JAGUAR 0x182c + #define REG_TX_AGC_C_MCS7_MCS4_JAGUAR 0x1830 + #define REG_TX_AGC_C_MCS11_MCS8_JAGUAR 0x1834 + #define REG_TX_AGC_C_MCS15_MCS12_JAGUAR 0x1838 + #define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x183c + #define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1840 + #define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1844 + #define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1848 + #define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x184c + #define REG_TX_AGC_C_MCS19_MCS16_JAGUAR 0x18d8 + #define REG_TX_AGC_C_MCS23_MCS20_JAGUAR 0x18dc + #define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x18e0 + #define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x18e4 + #define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x18e8 + #define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR 0x1a20 + #define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR 0x1a24 + #define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR 0x1a28 + #define REG_TX_AGC_D_MCS3_MCS0_JAGUAR 0x1a2c + #define REG_TX_AGC_D_MCS7_MCS4_JAGUAR 0x1a30 + #define REG_TX_AGC_D_MCS11_MCS8_JAGUAR 0x1a34 + #define REG_TX_AGC_D_MCS15_MCS12_JAGUAR 0x1a38 + #define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x1a3c + #define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1a40 + #define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1a44 + #define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1a48 + #define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x1a4c + #define REG_TX_AGC_D_MCS19_MCS16_JAGUAR 0x1ad8 + #define REG_TX_AGC_D_MCS23_MCS20_JAGUAR 0x1adc + #define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x1ae0 + #define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x1ae4 + #define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x1ae8 + #endif + + #define is_tx_agc_byte0_jaguar 0xff + #define is_tx_agc_byte1_jaguar 0xff00 + #define is_tx_agc_byte2_jaguar 0xff0000 + #define is_tx_agc_byte3_jaguar 0xff000000 #endif -#define bTxAGC_byte0_Jaguar 0xff -#define bTxAGC_byte1_Jaguar 0xff00 -#define bTxAGC_byte2_Jaguar 0xff0000 -#define bTxAGC_byte3_Jaguar 0xff000000 -#endif - -#define BIT_FA_RESET BIT0 +#define BIT_FA_RESET BIT(0) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + #define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0xC80 + #define REG_OFDM_0_ECCA_THRESHOLD 0xC4C + #define REG_FPGA0_XB_LSSI_READ_BACK 0x8A4 + #define REG_FPGA0_TX_GAIN_STAGE 0x80C + #define REG_OFDM_0_XA_AGC_CORE1 0xC50 + #define REG_OFDM_0_XB_AGC_CORE1 0xC58 + #define REG_A_TX_SCALE_JAGUAR 0xC1C + #define REG_B_TX_SCALE_JAGUAR 0xE1C + #define REG_AFE_XTAL_CTRL 0x0024 + #define REG_AFE_PLL_CTRL 0x0028 + #define REG_MAC_PHY_CTRL 0x002C + #define RF_CHNLBW 0x18 #endif +#endif diff --git a/hal/phydm/phydm_regdefine11ac.h b/hal/phydm/phydm_regdefine11ac.h index 0e39bfb..7bcd4d8 100644 --- a/hal/phydm/phydm_regdefine11ac.h +++ b/hal/phydm/phydm_regdefine11ac.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,32 +11,27 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - + *****************************************************************************/ + #ifndef __ODM_REGDEFINE11AC_H__ #define __ODM_REGDEFINE11AC_H__ -//2 RF REG LIST +/* 2 RF REG LIST */ -//2 BB REG LIST -//PAGE 8 +/* 2 BB REG LIST + * PAGE 8 */ #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 #define ODM_REG_BB_RX_PATH_11AC 0x808 #define ODM_REG_BB_TX_PATH_11AC 0x80c #define ODM_REG_BB_ATC_11AC 0x860 #define ODM_REG_EDCCA_POWER_CAL 0x8dc #define ODM_REG_DBG_RPT_11AC 0x8fc -//PAGE 9 +/* PAGE 9 */ #define ODM_REG_EDCCA_DOWN_OPT 0x900 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944 -#define ODM_ADC_TRIGGER_Jaguar2 0x95C /*ADC sample mode*/ +#define odm_adc_trigger_jaguar2 0x95C /*ADC sample mode*/ #define ODM_REG_OFDM_FA_RST_11AC 0x9A4 #define ODM_REG_CCX_PERIOD_11AC 0x990 #define ODM_REG_NHM_TH9_TH10_11AC 0x994 @@ -46,19 +41,19 @@ #define ODM_REG_NHM_TH8_11AC 0x9a0 #define ODM_REG_NHM_9E8_11AC 0x9e8 #define ODM_REG_CSI_CONTENT_VALUE 0x9b4 -//PAGE A +/* PAGE A */ #define ODM_REG_CCK_CCA_11AC 0xA0A #define ODM_REG_CCK_FA_RST_11AC 0xA2C #define ODM_REG_CCK_FA_11AC 0xA5C -//PAGE B +/* PAGE B */ #define ODM_REG_RST_RPT_11AC 0xB58 -//PAGE C +/* PAGE C */ #define ODM_REG_TRMUX_11AC 0xC08 #define ODM_REG_IGI_A_11AC 0xC50 -//PAGE E +/* PAGE E */ #define ODM_REG_IGI_B_11AC 0xE50 #define ODM_REG_TRMUX_11AC_B 0xE08 -//PAGE F +/* PAGE F */ #define ODM_REG_CCK_CRC32_CNT_11AC 0xF04 #define ODM_REG_CCK_CCA_CNT_11AC 0xF08 #define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c @@ -73,22 +68,21 @@ #define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac #define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0 #define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 -//PAGE 18 +/* PAGE 18 */ #define ODM_REG_IGI_C_11AC 0x1850 -//PAGE 1A +/* PAGE 1A */ #define ODM_REG_IGI_D_11AC 0x1A50 -//2 MAC REG LIST +/* 2 MAC REG LIST */ #define ODM_REG_RESP_TX_11AC 0x6D8 -//DIG Related +/* DIG Related */ #define ODM_BIT_IGI_11AC 0xFFFFFFFF -#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16 +#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16) #define ODM_BIT_BB_RX_PATH_11AC 0xF #define ODM_BIT_BB_TX_PATH_11AC 0xF -#define ODM_BIT_BB_ATC_11AC BIT14 +#define ODM_BIT_BB_ATC_11AC BIT(14) #endif - diff --git a/hal/phydm/phydm_regdefine11n.h b/hal/phydm/phydm_regdefine11n.h index bc76e63..7d85b94 100644 --- a/hal/phydm/phydm_regdefine11n.h +++ b/hal/phydm/phydm_regdefine11n.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,18 +11,13 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - + *****************************************************************************/ + #ifndef __ODM_REGDEFINE11N_H__ #define __ODM_REGDEFINE11N_H__ -//2 RF REG LIST +/* 2 RF REG LIST */ #define ODM_REG_RF_MODE_11N 0x00 #define ODM_REG_RF_0B_11N 0x0B #define ODM_REG_CHNBW_11N 0x18 @@ -38,8 +33,8 @@ -//2 BB REG LIST -//PAGE 8 +/* 2 BB REG LIST + * PAGE 8 */ #define ODM_REG_BB_CTRL_11N 0x800 #define ODM_REG_RF_PIN_11N 0x804 #define ODM_REG_PSD_CTRL_11N 0x808 @@ -68,12 +63,12 @@ #define ODM_REG_CLM_RESULT_11N 0x8d0 #define ODM_REG_NHM_CNT_11N 0x8d8 -// For ACS, Jeffery, 2014-12-26 -#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc -#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0 -#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4 +/* For struct _ACS_, Jeffery, 2014-12-26 */ +#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc +#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0 +#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4 -//PAGE 9 +/* PAGE 9 */ #define ODM_REG_BB_CTRL_PAGE9_11N 0x900 #define ODM_REG_DBG_RPT_11N 0x908 #define ODM_REG_BB_TX_PATH_11N 0x90c @@ -82,7 +77,7 @@ #define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 #define ODM_REG_RX_DFIR_MOD_97F 0x948 -//PAGE A +/* PAGE A */ #define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 #define ODM_REG_CCK_ANT_SEL_11N 0xA04 #define ODM_REG_CCK_CCA_11N 0xA0A @@ -102,7 +97,7 @@ #define ODM_REG_CCK_FA_LSB_11N 0xA5C #define ODM_REG_CCK_CCA_CNT_11N 0xA60 #define ODM_REG_BB_PWR_SAV4_11N 0xA74 -//PAGE B +/* PAGE B */ #define ODM_REG_LNA_SWITCH_11N 0xB2C #define ODM_REG_PATH_SWITCH_11N 0xB30 #define ODM_REG_RSSI_CTRL_11N 0xB38 @@ -111,7 +106,7 @@ #define ODM_REG_RXCK_RFMOD 0xBB0 #define ODM_REG_EDCCA_DCNF_97F 0xBC0 -//PAGE C +/* PAGE C */ #define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 #define ODM_REG_BB_RX_PATH_11N 0xC04 #define ODM_REG_TRMUX_11N 0xC08 @@ -135,7 +130,7 @@ #define ODM_REG_ANTDIV_PARA1_11N 0xCA4 #define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4 #define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 -//PAGE D +/* PAGE D */ #define ODM_REG_OFDM_FA_RSTD_11N 0xD00 #define ODM_REG_BB_RX_ANT_11N 0xD04 #define ODM_REG_BB_ATC_11N 0xD2C @@ -143,7 +138,7 @@ #define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 #define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 #define ODM_REG_RPT_11N 0xDF4 -//PAGE E +/* PAGE E */ #define ODM_REG_TXAGC_A_6_18_11N 0xE00 #define ODM_REG_TXAGC_A_24_54_11N 0xE04 #define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 @@ -169,7 +164,7 @@ #define ODM_REG_TX_CCK_BBON_11N 0xE78 #define ODM_REG_OFDM_RFON_11N 0xE7C #define ODM_REG_OFDM_BBON_11N 0xE80 -#define ODM_REG_TX2RX_11N 0xE84 +#define ODM_REG_TX2RX_11N 0xE84 #define ODM_REG_TX2TX_11N 0xE88 #define ODM_REG_RX_CCK_11N 0xE8C #define ODM_REG_RX_OFDM_11N 0xED0 @@ -186,8 +181,9 @@ #define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88 #define ODM_REG_HT_CRC32_CNT_11N 0xF90 #define ODM_REG_OFDM_CRC32_CNT_11N 0xF94 +#define ODM_REG_HT_CRC32_CNT_11N_AGG 0xFB8 -//2 MAC REG LIST +/* 2 MAC REG LIST */ #define ODM_REG_BB_RST_11N 0x02 #define ODM_REG_ANTSEL_PIN_11N 0x4C #define ODM_REG_EARLY_MODE_11N 0x4D0 @@ -202,12 +198,11 @@ #define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 -//DIG Related +/* DIG Related */ #define ODM_BIT_IGI_11N 0x0000007F -#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9 +#define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9) #define ODM_BIT_BB_RX_PATH_11N 0xF #define ODM_BIT_BB_TX_PATH_11N 0xF -#define ODM_BIT_BB_ATC_11N BIT11 +#define ODM_BIT_BB_ATC_11N BIT(11) #endif - diff --git a/hal/phydm/phydm_types.h b/hal/phydm/phydm_types.h index dcc07f5..2d4417c 100644 --- a/hal/phydm/phydm_types.h +++ b/hal/phydm/phydm_types.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __ODM_TYPES_H__ #define __ODM_TYPES_H__ @@ -25,26 +20,31 @@ #define ODM_AP 0x01 /*BIT0*/ #define ODM_CE 0x04 /*BIT2*/ #define ODM_WIN 0x08 /*BIT3*/ -#define ODM_ADSL 0x10 /*BIT4*/ +#define ODM_ADSL 0x10 /*BIT4*/ /*already combine with ODM_AP, and is nouse now*/ #define ODM_IOT 0x20 /*BIT5*/ +/*For FW API*/ +#define __iram_odm_func__ + /*Deifne HW endian support*/ #define ODM_ENDIAN_BIG 0 #define ODM_ENDIAN_LITTLE 1 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->DM_OutSrc))) + #define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->DM_OutSrc))) #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->odmpriv))) + #define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->odmpriv))) +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&(__padapter->pshare->_dmODM))) #endif #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) -#define RT_PCI_INTERFACE 1 -#define RT_USB_INTERFACE 2 -#define RT_SDIO_INTERFACE 3 + #define RT_PCI_INTERFACE 1 + #define RT_USB_INTERFACE 2 + #define RT_SDIO_INTERFACE 3 #endif -typedef enum _HAL_STATUS{ +enum hal_status { HAL_STATUS_SUCCESS, HAL_STATUS_FAILURE, /*RT_STATUS_PENDING, @@ -53,46 +53,43 @@ typedef enum _HAL_STATUS{ RT_STATUS_INVALID_PARAMETER, RT_STATUS_NOT_SUPPORT, RT_STATUS_OS_API_FAILED,*/ -}HAL_STATUS,*PHAL_STATUS; +}; -#if( DM_ODM_SUPPORT_TYPE == ODM_AP) -#define MP_DRIVER 0 -#endif -#if(DM_ODM_SUPPORT_TYPE != ODM_WIN) +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) #define VISTA_USB_RX_REVISE 0 -// -// Declare for ODM spin lock defintion temporarily fro compile pass. -// -typedef enum _RT_SPINLOCK_TYPE{ +/* + * Declare for ODM spin lock defintion temporarily fro compile pass. + * */ +enum rt_spinlock_type { RT_TX_SPINLOCK = 1, RT_RX_SPINLOCK = 2, RT_RM_SPINLOCK = 3, RT_CAM_SPINLOCK = 4, RT_SCAN_SPINLOCK = 5, - RT_LOG_SPINLOCK = 7, + RT_LOG_SPINLOCK = 7, RT_BW_SPINLOCK = 8, RT_CHNLOP_SPINLOCK = 9, RT_RF_OPERATE_SPINLOCK = 10, RT_INITIAL_SPINLOCK = 11, - RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30. + RT_RF_STATE_SPINLOCK = 12, /* For RF state. Added by Bruce, 2007-10-30. */ #if VISTA_USB_RX_REVISE RT_USBRX_CONTEXT_SPINLOCK = 13, - RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR + RT_USBRX_POSTPROC_SPINLOCK = 14, /* protect data of adapter->IndicateW/ IndicateR */ #endif - //Shall we define Ndis 6.2 SpinLock Here ? - RT_PORT_SPINLOCK=16, - RT_VNIC_SPINLOCK=17, - RT_HVL_SPINLOCK=18, - RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09. + /* Shall we define Ndis 6.2 SpinLock Here ? */ + RT_PORT_SPINLOCK = 16, + RT_VNIC_SPINLOCK = 17, + RT_HVL_SPINLOCK = 18, + RT_H2C_SPINLOCK = 20, /* For H2C cmd. Added by tynli. 2009.11.09. */ - RT_BTData_SPINLOCK=25, + rt_bt_data_spinlock = 25, - RT_WAPI_OPTION_SPINLOCK=26, - RT_WAPI_RX_SPINLOCK=27, + RT_WAPI_OPTION_SPINLOCK = 26, + RT_WAPI_RX_SPINLOCK = 27, - // add for 92D CCK control issue + /* add for 92D CCK control issue */ RT_CCK_PAGEA_SPINLOCK = 28, RT_BUFFER_SPINLOCK = 29, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30, @@ -101,64 +98,49 @@ typedef enum _RT_SPINLOCK_TYPE{ RT_FW_PS_SPINLOCK = 33, RT_HW_TIMER_SPIN_LOCK = 34, RT_MPT_WI_SPINLOCK = 35, - RT_P2P_SPIN_LOCK = 36, // Protect P2P context + RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */ RT_DBG_SPIN_LOCK = 37, RT_IQK_SPINLOCK = 38, RT_PENDED_OID_SPINLOCK = 39, - RT_CHNLLIST_SPINLOCK = 40, - RT_INDIC_SPINLOCK = 41, //protect indication + RT_CHNLLIST_SPINLOCK = 40, + RT_INDIC_SPINLOCK = 41, /* protect indication */ RT_RFD_SPINLOCK = 42, RT_SYNC_IO_CNT_SPINLOCK = 43, RT_LAST_SPINLOCK, -}RT_SPINLOCK_TYPE; +}; #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define STA_INFO_T RT_WLAN_STA - #define PSTA_INFO_T PRT_WLAN_STA + #define sta_info _RT_WLAN_STA + #define cmn_sta_info _RT_WLAN_STA /*tmp add for compile*/ #define __func__ __FUNCTION__ #define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT - #define bMaskH3Bytes 0xffffff00 + #define MASKH3BYTES 0xffffff00 #define SUCCESS 0 #define FAIL (-1) -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #define u8 u1Byte + #define s8 s1Byte + + #define u16 u2Byte + #define s16 s2Byte + + #define u32 u4Byte + #define s32 s4Byte - // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. - #define ADSL_AP_BUILD_WORKAROUND - #define AP_BUILD_WORKAROUND + #define u64 u8Byte + #define s64 s8Byte + + #define timer_list _RT_TIMER - #ifdef AP_BUILD_WORKAROUND - #include "../typedef.h" - #else - typedef void VOID,*PVOID; - typedef unsigned char BOOLEAN,*PBOOLEAN; - typedef unsigned char u1Byte,*pu1Byte; - typedef unsigned short u2Byte,*pu2Byte; - typedef unsigned int u4Byte,*pu4Byte; - typedef unsigned long long u8Byte,*pu8Byte; -#if 1 -/* In ARM platform, system would use the type -- "char" as "unsigned char" - * And we only use s1Byte/ps1Byte as INT8 now, so changes the type of s1Byte.*/ - typedef signed char s1Byte,*ps1Byte; -#else - typedef char s1Byte,*ps1Byte; -#endif - typedef short s2Byte,*ps2Byte; - typedef long s4Byte,*ps4Byte; - typedef long long s8Byte,*ps8Byte; - #endif - typedef struct rtl8192cd_priv *prtl8192cd_priv; - typedef struct stat_info STA_INFO_T,*PSTA_INFO_T; - typedef struct timer_list RT_TIMER, *PRT_TIMER; - typedef void * RT_TIMER_CALL_BACK; +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "../typedef.h" -#ifdef CONFIG_PCI_HCI - #define DEV_BUS_TYPE RT_PCI_INTERFACE -#endif + #ifdef CONFIG_PCI_HCI + #define DEV_BUS_TYPE RT_PCI_INTERFACE + #endif #define _TRUE 1 #define _FALSE 0 @@ -168,77 +150,87 @@ typedef enum _RT_SPINLOCK_TYPE{ #else #define PHYDM_TESTCHIP_SUPPORT 0 #endif - + + #define sta_info stat_info + #define cmn_sta_info stat_info /*tmp add for compile*/ + #define boolean bool + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + + #include + + #define DEV_BUS_TYPE RT_PCI_INTERFACE + + #if defined(__LITTLE_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #elif defined(__BIG_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #else + #error + #endif + + /* define useless flag to avoid compile warning */ + #define USE_WORKITEM 0 + #define FOR_BRAZIL_PRETEST 0 + #define FPGA_TWO_MAC_VERIFICATION 0 + #define RTL8881A_SUPPORT 0 + #define PHYDM_TESTCHIP_SUPPORT 0 + + /* support list */ + #define RTL8188E_SUPPORT 0 + #define RTL8812A_SUPPORT 0 + #define RTL8821A_SUPPORT 0 + #define RTL8723B_SUPPORT 0 + #define RTL8723D_SUPPORT 0 + #define RTL8192E_SUPPORT 0 + #define RTL8814A_SUPPORT 0 + #define RTL8195A_SUPPORT 0 + #define RTL8197F_SUPPORT 0 + #define RTL8703B_SUPPORT 0 + #define RTL8188F_SUPPORT 0 + #define RTL8822B_SUPPORT 1 + #define RTL8821B_SUPPORT 0 + #define RTL8821C_SUPPORT 0 + + #define RATE_ADAPTIVE_SUPPORT 0 + #define POWER_TRAINING_ACTIVE 0 + + #define sta_info rtl_sta_info + #define cmn_sta_info rtl_sta_info /*tmp add for compile*/ + #define _FALSE false + #define boolean bool + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) #include -#if 0 - typedef u8 u1Byte, *pu1Byte; - typedef u16 u2Byte,*pu2Byte; - typedef u32 u4Byte,*pu4Byte; - typedef u64 u8Byte,*pu8Byte; - typedef s8 s1Byte,*ps1Byte; - typedef s16 s2Byte,*ps2Byte; - typedef s32 s4Byte,*ps4Byte; - typedef s64 s8Byte,*ps8Byte; -#else - #define u1Byte u8 - #define pu1Byte u8* - - #define u2Byte u16 - #define pu2Byte u16* - - #define u4Byte u32 - #define pu4Byte u32* - - #define u8Byte u64 - #define pu8Byte u64* - - #define s1Byte s8 - #define ps1Byte s8* - - #define s2Byte s16 - #define ps2Byte s16* - - #define s4Byte s32 - #define ps4Byte s32* - - #define s8Byte s64 - #define ps8Byte s64* - -#endif + #ifdef CONFIG_USB_HCI - #define DEV_BUS_TYPE RT_USB_INTERFACE + #define DEV_BUS_TYPE RT_USB_INTERFACE #elif defined(CONFIG_PCI_HCI) - #define DEV_BUS_TYPE RT_PCI_INTERFACE + #define DEV_BUS_TYPE RT_PCI_INTERFACE #elif defined(CONFIG_SDIO_HCI) - #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #define DEV_BUS_TYPE RT_SDIO_INTERFACE #elif defined(CONFIG_GSPI_HCI) - #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #define DEV_BUS_TYPE RT_SDIO_INTERFACE #endif - - #if defined(CONFIG_LITTLE_ENDIAN) + + #if defined(CONFIG_LITTLE_ENDIAN) #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE #elif defined (CONFIG_BIG_ENDIAN) #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG #endif - - typedef struct timer_list RT_TIMER, *PRT_TIMER; - typedef void * RT_TIMER_CALL_BACK; - #define STA_INFO_T struct sta_info - #define PSTA_INFO_T struct sta_info * - + #define boolean bool - #define TRUE _TRUE - #define FALSE _FALSE + #define true _TRUE + #define false _FALSE - #define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) - #define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) - #define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) + #define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+8, 24, 1, __value) + #define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+8, 25, 1, __value) + #define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+28, 29, 1, __value) - //define useless flag to avoid compile warning + /* define useless flag to avoid compile warning */ #define USE_WORKITEM 0 #define FOR_BRAZIL_PRETEST 0 #define FPGA_TWO_MAC_VERIFICATION 0 @@ -251,11 +243,29 @@ typedef enum _RT_SPINLOCK_TYPE{ #endif #endif -#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) +#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i+1]; } while (0) #define COND_ELSE 2 #define COND_ENDIF 3 -#include "phydm_features.h" - -#endif // __ODM_TYPES_H__ - +#define MASKBYTE0 0xff +#define MASKBYTE1 0xff00 +#define MASKBYTE2 0xff0000 +#define MASKBYTE3 0xff000000 +#define MASKHWORD 0xffff0000 +#define MASKLWORD 0x0000ffff +#define MASKDWORD 0xffffffff +#define MASK7BITS 0x7f +#define MASK12BITS 0xfff +#define MASKH4BITS 0xf0000000 +#define MASK20BITS 0xfffff +#define MASKOFDM_D 0xffc00000 +#define MASKCCK 0x3f3f3f3f +#define RFREGOFFSETMASK 0xfffff +#define MASKH3BYTES 0xffffff00 +#define MASKL3BYTES 0x00ffffff +#define MASKBYTE2HIGHNIBBLE 0x00f00000 +#define MASKBYTE3LOWNIBBLE 0x0f000000 +#define MASKL3BYTES 0x00ffffff +#define RFREGOFFSETMASK 0xfffff + +#endif /* __ODM_TYPES_H__ */ diff --git a/hal/phydm/rtl8822b/halhwimg8822b_bb.c b/hal/phydm/rtl8822b/halhwimg8822b_bb.c index afc3f13..a23b07e 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_bb.c +++ b/hal/phydm/rtl8822b/halhwimg8822b_bb.c @@ -1,126 +1,171 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* ******************************************************************************/ -/*Image2HeaderVersion: 2.22*/ +/*Image2HeaderVersion: R2 1.2.1*/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (RTL8822B_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 +static boolean +check_positive( + struct PHY_DM_STRUCT *p_dm_odm, + const u32 condition1, + const u32 condition2, + const u32 condition3, + const u32 condition4 ) { - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; + u8 cut_version_for_para = (p_dm_odm->cut_version == ODM_CUT_A) ? 15 : p_dm_odm->cut_version; + u8 pkg_type_for_para = (p_dm_odm->package_type == 0) ? 15 : p_dm_odm->package_type; - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; + u32 driver1 = cut_version_for_para << 24 | + (p_dm_odm->support_interface & 0xF0) << 16 | + p_dm_odm->support_platform << 16 | + pkg_type_for_para << 12 | + (p_dm_odm->support_interface & 0x0F) << 8 | + p_dm_odm->rfe_type; -u4Byte driver3 = 0; + u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 | + (p_dm_odm->type_gpa & 0xFF) << 8 | + (p_dm_odm->type_alna & 0xFF) << 16 | + (p_dm_odm->type_apa & 0xFF) << 24; - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; + u32 driver3 = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 | + (p_dm_odm->type_gpa & 0xFF00) | + (p_dm_odm->type_alna & 0xFF00) << 8 | + (p_dm_odm->type_apa & 0xFF00) << 16; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (RFE, Package) = (0x%X, 0x%X)\n", p_dm_odm->rfe_type, p_dm_odm->package_type)); - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ + /*============== value Defined Check ===============*/ + /*cut version [27:24] need to do value check*/ + + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return false; - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; + /*pkg type [15:12] need to do value check*/ - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return false; - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; + if (cond1 == driver1) + return true; + else + return false; } -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 +static boolean +check_negative( + struct PHY_DM_STRUCT *p_dm_odm, + const u32 condition1, + const u32 condition2 ) { - return TRUE; + return true; } /****************************************************************************** -* AGC_TAB.TXT +* agc_tab.TXT ******************************************************************************/ -u4Byte Array_MP_8822B_AGC_TAB[] = { - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, +u32 array_mp_8822b_agc_tab[] = { + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xEC240003, + 0x81C, 0xEB260003, + 0x81C, 0xEA280003, + 0x81C, 0xE92A0003, + 0x81C, 0xE82C0003, + 0x81C, 0xE72E0003, + 0x81C, 0xE6300003, + 0x81C, 0xE5320003, + 0x81C, 0xC8340003, + 0x81C, 0xC7360003, + 0x81C, 0xC6380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xC1420003, + 0x81C, 0xC0440003, + 0x81C, 0xA3460003, + 0x81C, 0xA2480003, + 0x81C, 0xA14A0003, + 0x81C, 0xA04C0003, + 0x81C, 0x824E0003, + 0x81C, 0x81500003, + 0x81C, 0x80520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x445A0003, + 0x81C, 0x435C0003, + 0x81C, 0x425E0003, + 0x81C, 0x41600003, + 0x81C, 0x40620003, + 0x81C, 0x05640003, + 0x81C, 0x04660003, + 0x81C, 0x03680003, + 0x81C, 0x026A0003, + 0x81C, 0x016C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xF5000003, 0x81C, 0xF4020003, @@ -186,7 +231,271 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFD000003, + 0x81C, 0xFC020003, + 0x81C, 0xFB040003, + 0x81C, 0xFA060003, + 0x81C, 0xF9080003, + 0x81C, 0xF80A0003, + 0x81C, 0xF70C0003, + 0x81C, 0xF60E0003, + 0x81C, 0xF5100003, + 0x81C, 0xF4120003, + 0x81C, 0xF3140003, + 0x81C, 0xF2160003, + 0x81C, 0xF1180003, + 0x81C, 0xF01A0003, + 0x81C, 0xEF1C0003, + 0x81C, 0xEE1E0003, + 0x81C, 0xED200003, + 0x81C, 0xEC220003, + 0x81C, 0xEB240003, + 0x81C, 0xEA260003, + 0x81C, 0xE9280003, + 0x81C, 0xE82A0003, + 0x81C, 0xE72C0003, + 0x81C, 0xE62E0003, + 0x81C, 0xE5300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xC43A0003, + 0x81C, 0xC33C0003, + 0x81C, 0xC23E0003, + 0x81C, 0xC1400003, + 0x81C, 0xC0420003, + 0x81C, 0xA5440003, + 0x81C, 0xA4460003, + 0x81C, 0xA3480003, + 0x81C, 0xA24A0003, + 0x81C, 0xA14C0003, + 0x81C, 0x834E0003, + 0x81C, 0x82500003, + 0x81C, 0x81520003, + 0x81C, 0x80540003, + 0x81C, 0x65560003, + 0x81C, 0x64580003, + 0x81C, 0x635A0003, + 0x81C, 0x625C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x40640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFD000003, + 0x81C, 0xFC020003, + 0x81C, 0xFB040003, + 0x81C, 0xFA060003, + 0x81C, 0xF9080003, + 0x81C, 0xF80A0003, + 0x81C, 0xF70C0003, + 0x81C, 0xF60E0003, + 0x81C, 0xF5100003, + 0x81C, 0xF4120003, + 0x81C, 0xF3140003, + 0x81C, 0xF2160003, + 0x81C, 0xF1180003, + 0x81C, 0xF01A0003, + 0x81C, 0xEF1C0003, + 0x81C, 0xEE1E0003, + 0x81C, 0xED200003, + 0x81C, 0xEC220003, + 0x81C, 0xEB240003, + 0x81C, 0xEA260003, + 0x81C, 0xE9280003, + 0x81C, 0xE82A0003, + 0x81C, 0xE72C0003, + 0x81C, 0xE62E0003, + 0x81C, 0xE5300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xC43A0003, + 0x81C, 0xC33C0003, + 0x81C, 0xC23E0003, + 0x81C, 0xC1400003, + 0x81C, 0xC0420003, + 0x81C, 0xA5440003, + 0x81C, 0xA4460003, + 0x81C, 0xA3480003, + 0x81C, 0xA24A0003, + 0x81C, 0xA14C0003, + 0x81C, 0x834E0003, + 0x81C, 0x82500003, + 0x81C, 0x81520003, + 0x81C, 0x80540003, + 0x81C, 0x65560003, + 0x81C, 0x64580003, + 0x81C, 0x635A0003, + 0x81C, 0x625C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x40640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xDC000003, + 0x81C, 0xDB020003, + 0x81C, 0xDA040003, + 0x81C, 0xD9060003, + 0x81C, 0xD8080003, + 0x81C, 0xD70A0003, + 0x81C, 0xD60C0003, + 0x81C, 0xD50E0003, + 0x81C, 0xD4100003, + 0x81C, 0xD3120003, + 0x81C, 0xD2140003, + 0x81C, 0xD1160003, + 0x81C, 0xD0180003, + 0x81C, 0xB41A0003, + 0x81C, 0xB31C0003, + 0x81C, 0xB21E0003, + 0x81C, 0xB1200003, + 0x81C, 0xB0220003, + 0x81C, 0xAF240003, + 0x81C, 0xAE260003, + 0x81C, 0xAD280003, + 0x81C, 0xAC2A0003, + 0x81C, 0xAB2C0003, + 0x81C, 0x8C2E0003, + 0x81C, 0x8B300003, + 0x81C, 0x8A320003, + 0x81C, 0x89340003, + 0x81C, 0x88360003, + 0x81C, 0x87380003, + 0x81C, 0x863A0003, + 0x81C, 0x853C0003, + 0x81C, 0x693E0003, + 0x81C, 0x68400003, + 0x81C, 0x67420003, + 0x81C, 0x66440003, + 0x81C, 0x65460003, + 0x81C, 0x48480003, + 0x81C, 0x474A0003, + 0x81C, 0x464C0003, + 0x81C, 0x454E0003, + 0x81C, 0x44500003, + 0x81C, 0x43520003, + 0x81C, 0x27540003, + 0x81C, 0x26560003, + 0x81C, 0x25580003, + 0x81C, 0x245A0003, + 0x81C, 0x235C0003, + 0x81C, 0x045E0003, + 0x81C, 0x03600003, + 0x81C, 0x02620003, + 0x81C, 0x01640003, + 0x81C, 0x00660003, + 0x81C, 0x00680003, + 0x81C, 0x006A0003, + 0x81C, 0x006C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFD000003, + 0x81C, 0xFC020003, + 0x81C, 0xFB040003, + 0x81C, 0xFA060003, + 0x81C, 0xF9080003, + 0x81C, 0xF80A0003, + 0x81C, 0xF70C0003, + 0x81C, 0xF60E0003, + 0x81C, 0xF5100003, + 0x81C, 0xF4120003, + 0x81C, 0xF3140003, + 0x81C, 0xF2160003, + 0x81C, 0xF1180003, + 0x81C, 0xF01A0003, + 0x81C, 0xEF1C0003, + 0x81C, 0xEE1E0003, + 0x81C, 0xED200003, + 0x81C, 0xEC220003, + 0x81C, 0xEB240003, + 0x81C, 0xEA260003, + 0x81C, 0xE9280003, + 0x81C, 0xE82A0003, + 0x81C, 0xE72C0003, + 0x81C, 0xE62E0003, + 0x81C, 0xE5300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xC43A0003, + 0x81C, 0xC33C0003, + 0x81C, 0xC23E0003, + 0x81C, 0xC1400003, + 0x81C, 0xC0420003, + 0x81C, 0xA5440003, + 0x81C, 0xA4460003, + 0x81C, 0xA3480003, + 0x81C, 0xA24A0003, + 0x81C, 0xA14C0003, + 0x81C, 0x834E0003, + 0x81C, 0x82500003, + 0x81C, 0x81520003, + 0x81C, 0x80540003, + 0x81C, 0x65560003, + 0x81C, 0x64580003, + 0x81C, 0x635A0003, + 0x81C, 0x625C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x40640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xF5000003, 0x81C, 0xF4020003, @@ -252,7 +561,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xF5000003, 0x81C, 0xF4020003, @@ -318,7 +627,73 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xEC240003, + 0x81C, 0xEB260003, + 0x81C, 0xEA280003, + 0x81C, 0xE92A0003, + 0x81C, 0xE82C0003, + 0x81C, 0xE72E0003, + 0x81C, 0xE6300003, + 0x81C, 0xE5320003, + 0x81C, 0xC8340003, + 0x81C, 0xC7360003, + 0x81C, 0xC6380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xC1420003, + 0x81C, 0xC0440003, + 0x81C, 0xA3460003, + 0x81C, 0xA2480003, + 0x81C, 0xA14A0003, + 0x81C, 0xA04C0003, + 0x81C, 0x824E0003, + 0x81C, 0x81500003, + 0x81C, 0x80520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x445A0003, + 0x81C, 0x435C0003, + 0x81C, 0x425E0003, + 0x81C, 0x41600003, + 0x81C, 0x40620003, + 0x81C, 0x05640003, + 0x81C, 0x04660003, + 0x81C, 0x03680003, + 0x81C, 0x026A0003, + 0x81C, 0x016C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xF5000003, 0x81C, 0xF4020003, @@ -384,7 +759,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x9000000a, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xFE000003, 0x81C, 0xFD020003, @@ -450,7 +825,73 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x9000000b, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xF5000003, + 0x81C, 0xF4020003, + 0x81C, 0xF3040003, + 0x81C, 0xF2060003, + 0x81C, 0xF1080003, + 0x81C, 0xF00A0003, + 0x81C, 0xEF0C0003, + 0x81C, 0xEE0E0003, + 0x81C, 0xED100003, + 0x81C, 0xEC120003, + 0x81C, 0xEB140003, + 0x81C, 0xEA160003, + 0x81C, 0xE9180003, + 0x81C, 0xE81A0003, + 0x81C, 0xE71C0003, + 0x81C, 0xE61E0003, + 0x81C, 0xE5200003, + 0x81C, 0xE4220003, + 0x81C, 0xE3240003, + 0x81C, 0xE2260003, + 0x81C, 0xE1280003, + 0x81C, 0xE02A0003, + 0x81C, 0xC32C0003, + 0x81C, 0xC22E0003, + 0x81C, 0xC1300003, + 0x81C, 0xC0320003, + 0x81C, 0xA4340003, + 0x81C, 0xA3360003, + 0x81C, 0xA2380003, + 0x81C, 0xA13A0003, + 0x81C, 0xA03C0003, + 0x81C, 0x823E0003, + 0x81C, 0x81400003, + 0x81C, 0x80420003, + 0x81C, 0x64440003, + 0x81C, 0x63460003, + 0x81C, 0x62480003, + 0x81C, 0x614A0003, + 0x81C, 0x604C0003, + 0x81C, 0x454E0003, + 0x81C, 0x44500003, + 0x81C, 0x43520003, + 0x81C, 0x42540003, + 0x81C, 0x41560003, + 0x81C, 0x40580003, + 0x81C, 0x055A0003, + 0x81C, 0x045C0003, + 0x81C, 0x035E0003, + 0x81C, 0x02600003, + 0x81C, 0x01620003, + 0x81C, 0x00640003, + 0x81C, 0x00660003, + 0x81C, 0x00680003, + 0x81C, 0x006A0003, + 0x81C, 0x006C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x9000000c, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xFE000003, 0x81C, 0xFD020003, @@ -516,7 +957,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xFE000003, 0x81C, 0xFD020003, @@ -582,7 +1023,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003, - 0xA0000000, 0x00000000, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xFE000003, 0x81C, 0xFD020003, @@ -648,191 +1089,127 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003, - 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, - 0x81C, 0xF9000103, - 0x81C, 0xF8020103, - 0x81C, 0xF7040103, - 0x81C, 0xF6060103, - 0x81C, 0xF5080103, - 0x81C, 0xF40A0103, - 0x81C, 0xF30C0103, - 0x81C, 0xF20E0103, - 0x81C, 0xF1100103, - 0x81C, 0xF0120103, - 0x81C, 0xEF140103, - 0x81C, 0xEE160103, - 0x81C, 0xED180103, - 0x81C, 0xEC1A0103, - 0x81C, 0xEB1C0103, - 0x81C, 0xEA1E0103, - 0x81C, 0xE9200103, - 0x81C, 0xE8220103, - 0x81C, 0xE7240103, - 0x81C, 0xE6260103, - 0x81C, 0xE5280103, - 0x81C, 0xE42A0103, - 0x81C, 0xE32C0103, - 0x81C, 0xC32E0103, - 0x81C, 0xC2300103, - 0x81C, 0xC1320103, - 0x81C, 0xC0340103, - 0x81C, 0xA3360103, - 0x81C, 0xA2380103, - 0x81C, 0xA13A0103, - 0x81C, 0xA03C0103, - 0x81C, 0x823E0103, - 0x81C, 0x81400103, - 0x81C, 0x80420103, - 0x81C, 0x63440103, - 0x81C, 0x62460103, - 0x81C, 0x61480103, - 0x81C, 0x604A0103, - 0x81C, 0x424C0103, - 0x81C, 0x414E0103, - 0x81C, 0x40500103, - 0x81C, 0x22520103, - 0x81C, 0x21540103, - 0x81C, 0x20560103, - 0x81C, 0x03580103, - 0x81C, 0x025A0103, - 0x81C, 0x015C0103, - 0x81C, 0x005E0103, - 0x81C, 0x00600103, - 0x81C, 0x00620103, - 0x81C, 0x00640103, - 0x81C, 0x00660103, - 0x81C, 0x00680103, - 0x81C, 0x006A0103, - 0x81C, 0x006C0103, - 0x81C, 0x006E0103, - 0x81C, 0x00700103, - 0x81C, 0x00720103, - 0x81C, 0x00740103, - 0x81C, 0x00760103, - 0x81C, 0x00780103, - 0x81C, 0x007A0103, - 0x81C, 0x007C0103, - 0x81C, 0x007E0103, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x81C, 0xFA000103, - 0x81C, 0xF9020103, - 0x81C, 0xF8040103, - 0x81C, 0xF7060103, - 0x81C, 0xF6080103, - 0x81C, 0xF50A0103, - 0x81C, 0xF40C0103, - 0x81C, 0xF30E0103, - 0x81C, 0xF2100103, - 0x81C, 0xF1120103, - 0x81C, 0xF0140103, - 0x81C, 0xEF160103, - 0x81C, 0xEE180103, - 0x81C, 0xED1A0103, - 0x81C, 0xEC1C0103, - 0x81C, 0xEB1E0103, - 0x81C, 0xEA200103, - 0x81C, 0xE9220103, - 0x81C, 0xE8240103, - 0x81C, 0xE7260103, - 0x81C, 0xE6280103, - 0x81C, 0xE52A0103, - 0x81C, 0xC42C0103, - 0x81C, 0xC32E0103, - 0x81C, 0xC2300103, - 0x81C, 0xC1320103, - 0x81C, 0xA3340103, - 0x81C, 0xA2360103, - 0x81C, 0xA1380103, - 0x81C, 0xA03A0103, - 0x81C, 0x823C0103, - 0x81C, 0x813E0103, - 0x81C, 0x80400103, - 0x81C, 0x63420103, - 0x81C, 0x62440103, - 0x81C, 0x61460103, - 0x81C, 0x60480103, - 0x81C, 0x424A0103, - 0x81C, 0x414C0103, - 0x81C, 0x404E0103, - 0x81C, 0x22500103, - 0x81C, 0x21520103, - 0x81C, 0x20540103, - 0x81C, 0x03560103, - 0x81C, 0x02580103, - 0x81C, 0x015A0103, - 0x81C, 0x005C0103, - 0x81C, 0x005E0103, - 0x81C, 0x00600103, - 0x81C, 0x00620103, - 0x81C, 0x00640103, - 0x81C, 0x00660103, - 0x81C, 0x00680103, - 0x81C, 0x006A0103, - 0x81C, 0x006C0103, - 0x81C, 0x006E0103, - 0x81C, 0x00700103, - 0x81C, 0x00720103, - 0x81C, 0x00740103, - 0x81C, 0x00760103, - 0x81C, 0x00780103, - 0x81C, 0x007A0103, - 0x81C, 0x007C0103, - 0x81C, 0x007E0103, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF8000103, - 0x81C, 0xF7020103, - 0x81C, 0xF6040103, - 0x81C, 0xF5060103, - 0x81C, 0xF4080103, - 0x81C, 0xF30A0103, - 0x81C, 0xF20C0103, - 0x81C, 0xF10E0103, - 0x81C, 0xF0100103, - 0x81C, 0xEF120103, - 0x81C, 0xEE140103, - 0x81C, 0xED160103, - 0x81C, 0xEC180103, - 0x81C, 0xEB1A0103, - 0x81C, 0xEA1C0103, - 0x81C, 0xE91E0103, - 0x81C, 0xE8200103, - 0x81C, 0xE7220103, - 0x81C, 0xE6240103, - 0x81C, 0xE5260103, - 0x81C, 0xE4280103, - 0x81C, 0xE32A0103, - 0x81C, 0xC32C0103, - 0x81C, 0xC22E0103, - 0x81C, 0xC1300103, - 0x81C, 0xC0320103, - 0x81C, 0xA3340103, - 0x81C, 0xA2360103, - 0x81C, 0xA1380103, - 0x81C, 0xA03A0103, - 0x81C, 0x823C0103, - 0x81C, 0x813E0103, - 0x81C, 0x80400103, - 0x81C, 0x63420103, - 0x81C, 0x62440103, - 0x81C, 0x61460103, - 0x81C, 0x60480103, - 0x81C, 0x424A0103, - 0x81C, 0x414C0103, - 0x81C, 0x404E0103, - 0x81C, 0x22500103, - 0x81C, 0x21520103, - 0x81C, 0x20540103, - 0x81C, 0x03560103, - 0x81C, 0x02580103, - 0x81C, 0x015A0103, - 0x81C, 0x005C0103, - 0x81C, 0x005E0103, - 0x81C, 0x00600103, - 0x81C, 0x00620103, - 0x81C, 0x00640103, - 0x81C, 0x00660103, - 0x81C, 0x00680103, + 0xA0000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFE000003, + 0x81C, 0xFD020003, + 0x81C, 0xFC040003, + 0x81C, 0xFB060003, + 0x81C, 0xFA080003, + 0x81C, 0xF90A0003, + 0x81C, 0xF80C0003, + 0x81C, 0xF70E0003, + 0x81C, 0xF6100003, + 0x81C, 0xF5120003, + 0x81C, 0xF4140003, + 0x81C, 0xF3160003, + 0x81C, 0xF2180003, + 0x81C, 0xF11A0003, + 0x81C, 0xF01C0003, + 0x81C, 0xEF1E0003, + 0x81C, 0xEE200003, + 0x81C, 0xED220003, + 0x81C, 0xEC240003, + 0x81C, 0xEB260003, + 0x81C, 0xEA280003, + 0x81C, 0xE92A0003, + 0x81C, 0xE82C0003, + 0x81C, 0xE72E0003, + 0x81C, 0xE6300003, + 0x81C, 0xE5320003, + 0x81C, 0xC8340003, + 0x81C, 0xC7360003, + 0x81C, 0xC6380003, + 0x81C, 0xC53A0003, + 0x81C, 0xC43C0003, + 0x81C, 0xC33E0003, + 0x81C, 0xC2400003, + 0x81C, 0xC1420003, + 0x81C, 0xC0440003, + 0x81C, 0xA3460003, + 0x81C, 0xA2480003, + 0x81C, 0xA14A0003, + 0x81C, 0xA04C0003, + 0x81C, 0x824E0003, + 0x81C, 0x81500003, + 0x81C, 0x80520003, + 0x81C, 0x64540003, + 0x81C, 0x63560003, + 0x81C, 0x62580003, + 0x81C, 0x445A0003, + 0x81C, 0x435C0003, + 0x81C, 0x425E0003, + 0x81C, 0x41600003, + 0x81C, 0x40620003, + 0x81C, 0x05640003, + 0x81C, 0x04660003, + 0x81C, 0x03680003, + 0x81C, 0x026A0003, + 0x81C, 0x016C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0xB0000000, 0x00000000, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEE1C0103, + 0x81C, 0xED1E0103, + 0x81C, 0xEC200103, + 0x81C, 0xEB220103, + 0x81C, 0xEA240103, + 0x81C, 0xE9260103, + 0x81C, 0xE8280103, + 0x81C, 0xE72A0103, + 0x81C, 0xE62C0103, + 0x81C, 0xE52E0103, + 0x81C, 0xE4300103, + 0x81C, 0xE3320103, + 0x81C, 0xE2340103, + 0x81C, 0xC5360103, + 0x81C, 0xC4380103, + 0x81C, 0xC33A0103, + 0x81C, 0xC23C0103, + 0x81C, 0xA53E0103, + 0x81C, 0xA4400103, + 0x81C, 0xA3420103, + 0x81C, 0xA2440103, + 0x81C, 0xA1460103, + 0x81C, 0x83480103, + 0x81C, 0x824A0103, + 0x81C, 0x814C0103, + 0x81C, 0x804E0103, + 0x81C, 0x63500103, + 0x81C, 0x62520103, + 0x81C, 0x61540103, + 0x81C, 0x43560103, + 0x81C, 0x42580103, + 0x81C, 0x415A0103, + 0x81C, 0x405C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103, @@ -844,7 +1221,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0103, 0x81C, 0x007C0103, 0x81C, 0x007E0103, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xF8000103, 0x81C, 0xF7020103, 0x81C, 0xF6040103, @@ -885,9 +1262,9 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x424A0103, 0x81C, 0x414C0103, 0x81C, 0x404E0103, - 0x81C, 0x22500103, - 0x81C, 0x21520103, - 0x81C, 0x20540103, + 0x81C, 0x06500103, + 0x81C, 0x05520103, + 0x81C, 0x04540103, 0x81C, 0x03560103, 0x81C, 0x02580103, 0x81C, 0x015A0103, @@ -909,7 +1286,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0103, 0x81C, 0x007C0103, 0x81C, 0x007E0103, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xF8000103, 0x81C, 0xF7020103, 0x81C, 0xF6040103, @@ -974,7 +1351,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0103, 0x81C, 0x007C0103, 0x81C, 0x007E0103, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFE000103, 0x81C, 0xFD020103, 0x81C, 0xFC040103, @@ -1039,56 +1416,706 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0103, 0x81C, 0x007C0103, 0x81C, 0x007E0103, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFE000103, - 0x81C, 0xFD020103, - 0x81C, 0xFC040103, - 0x81C, 0xFB060103, - 0x81C, 0xFA080103, - 0x81C, 0xF90A0103, - 0x81C, 0xF80C0103, - 0x81C, 0xF70E0103, - 0x81C, 0xF6100103, - 0x81C, 0xF5120103, - 0x81C, 0xF4140103, - 0x81C, 0xF3160103, - 0x81C, 0xF2180103, - 0x81C, 0xF11A0103, - 0x81C, 0xF01C0103, - 0x81C, 0xEF1E0103, - 0x81C, 0xEE200103, - 0x81C, 0xED220103, - 0x81C, 0xEC240103, - 0x81C, 0xEB260103, - 0x81C, 0xEA280103, - 0x81C, 0xE92A0103, - 0x81C, 0xE82C0103, - 0x81C, 0xE72E0103, - 0x81C, 0xE6300103, - 0x81C, 0xE5320103, - 0x81C, 0xE4340103, - 0x81C, 0xE3360103, - 0x81C, 0xC6380103, - 0x81C, 0xC53A0103, - 0x81C, 0xC43C0103, - 0x81C, 0xC33E0103, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000103, + 0x81C, 0xF7020103, + 0x81C, 0xF6040103, + 0x81C, 0xF5060103, + 0x81C, 0xF4080103, + 0x81C, 0xF30A0103, + 0x81C, 0xF20C0103, + 0x81C, 0xF10E0103, + 0x81C, 0xF0100103, + 0x81C, 0xEF120103, + 0x81C, 0xEE140103, + 0x81C, 0xED160103, + 0x81C, 0xEC180103, + 0x81C, 0xEB1A0103, + 0x81C, 0xEA1C0103, + 0x81C, 0xE91E0103, + 0x81C, 0xE8200103, + 0x81C, 0xE7220103, + 0x81C, 0xE6240103, + 0x81C, 0xE5260103, + 0x81C, 0xE4280103, + 0x81C, 0xE32A0103, + 0x81C, 0xC32C0103, + 0x81C, 0xC22E0103, + 0x81C, 0xC1300103, + 0x81C, 0xC0320103, + 0x81C, 0xA3340103, + 0x81C, 0xA2360103, + 0x81C, 0xA1380103, + 0x81C, 0xA03A0103, + 0x81C, 0x823C0103, + 0x81C, 0x813E0103, + 0x81C, 0x80400103, + 0x81C, 0x63420103, + 0x81C, 0x62440103, + 0x81C, 0x61460103, + 0x81C, 0x60480103, + 0x81C, 0x424A0103, + 0x81C, 0x414C0103, + 0x81C, 0x404E0103, + 0x81C, 0x22500103, + 0x81C, 0x21520103, + 0x81C, 0x20540103, + 0x81C, 0x03560103, + 0x81C, 0x02580103, + 0x81C, 0x015A0103, + 0x81C, 0x005C0103, + 0x81C, 0x005E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEF1C0103, + 0x81C, 0xEE1E0103, + 0x81C, 0xED200103, + 0x81C, 0xEC220103, + 0x81C, 0xEB240103, + 0x81C, 0xEA260103, + 0x81C, 0xE9280103, + 0x81C, 0xE82A0103, + 0x81C, 0xE72C0103, + 0x81C, 0xE62E0103, + 0x81C, 0xE5300103, + 0x81C, 0xE4320103, + 0x81C, 0xE3340103, + 0x81C, 0xE2360103, + 0x81C, 0xC5380103, + 0x81C, 0xC43A0103, + 0x81C, 0xC33C0103, + 0x81C, 0xC23E0103, 0x81C, 0xA5400103, 0x81C, 0xA4420103, 0x81C, 0xA3440103, 0x81C, 0xA2460103, 0x81C, 0xA1480103, - 0x81C, 0xA04A0103, + 0x81C, 0x834A0103, 0x81C, 0x824C0103, 0x81C, 0x814E0103, - 0x81C, 0x80500103, - 0x81C, 0x64520103, - 0x81C, 0x63540103, - 0x81C, 0x62560103, - 0x81C, 0x61580103, - 0x81C, 0x605A0103, + 0x81C, 0x64500103, + 0x81C, 0x63520103, + 0x81C, 0x62540103, + 0x81C, 0x61560103, + 0x81C, 0x42580103, + 0x81C, 0x415A0103, + 0x81C, 0x405C0103, + 0x81C, 0x065E0103, + 0x81C, 0x05600103, + 0x81C, 0x04620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFA000103, + 0x81C, 0xF9020103, + 0x81C, 0xF8040103, + 0x81C, 0xF7060103, + 0x81C, 0xF6080103, + 0x81C, 0xF50A0103, + 0x81C, 0xF40C0103, + 0x81C, 0xF30E0103, + 0x81C, 0xF2100103, + 0x81C, 0xF1120103, + 0x81C, 0xF0140103, + 0x81C, 0xEF160103, + 0x81C, 0xEE180103, + 0x81C, 0xED1A0103, + 0x81C, 0xEC1C0103, + 0x81C, 0xEB1E0103, + 0x81C, 0xEA200103, + 0x81C, 0xE9220103, + 0x81C, 0xE8240103, + 0x81C, 0xE7260103, + 0x81C, 0xE6280103, + 0x81C, 0xE52A0103, + 0x81C, 0xC42C0103, + 0x81C, 0xC32E0103, + 0x81C, 0xC2300103, + 0x81C, 0xC1320103, + 0x81C, 0xA4340103, + 0x81C, 0xA3360103, + 0x81C, 0xA2380103, + 0x81C, 0xA13A0103, + 0x81C, 0x833C0103, + 0x81C, 0x823E0103, + 0x81C, 0x81400103, + 0x81C, 0x63420103, + 0x81C, 0x62440103, + 0x81C, 0x61460103, + 0x81C, 0x60480103, + 0x81C, 0x424A0103, + 0x81C, 0x414C0103, + 0x81C, 0x404E0103, + 0x81C, 0x22500103, + 0x81C, 0x21520103, + 0x81C, 0x20540103, + 0x81C, 0x03560103, + 0x81C, 0x02580103, + 0x81C, 0x015A0103, + 0x81C, 0x005C0103, + 0x81C, 0x005E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000103, + 0x81C, 0xF7020103, + 0x81C, 0xF6040103, + 0x81C, 0xF5060103, + 0x81C, 0xF4080103, + 0x81C, 0xF30A0103, + 0x81C, 0xF20C0103, + 0x81C, 0xF10E0103, + 0x81C, 0xF0100103, + 0x81C, 0xEF120103, + 0x81C, 0xEE140103, + 0x81C, 0xED160103, + 0x81C, 0xEC180103, + 0x81C, 0xEB1A0103, + 0x81C, 0xEA1C0103, + 0x81C, 0xE91E0103, + 0x81C, 0xE8200103, + 0x81C, 0xE7220103, + 0x81C, 0xE6240103, + 0x81C, 0xE5260103, + 0x81C, 0xE4280103, + 0x81C, 0xE32A0103, + 0x81C, 0xE22C0103, + 0x81C, 0xC32E0103, + 0x81C, 0xC2300103, + 0x81C, 0xC1320103, + 0x81C, 0xA3340103, + 0x81C, 0xA2360103, + 0x81C, 0xA1380103, + 0x81C, 0xA03A0103, + 0x81C, 0x823C0103, + 0x81C, 0x813E0103, + 0x81C, 0x80400103, + 0x81C, 0x64420103, + 0x81C, 0x63440103, + 0x81C, 0x62460103, + 0x81C, 0x61480103, + 0x81C, 0x434A0103, + 0x81C, 0x424C0103, + 0x81C, 0x414E0103, + 0x81C, 0x40500103, + 0x81C, 0x22520103, + 0x81C, 0x21540103, + 0x81C, 0x20560103, + 0x81C, 0x04580103, + 0x81C, 0x035A0103, + 0x81C, 0x025C0103, + 0x81C, 0x015E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEF1C0103, + 0x81C, 0xEE1E0103, + 0x81C, 0xED200103, + 0x81C, 0xEC220103, + 0x81C, 0xEB240103, + 0x81C, 0xEA260103, + 0x81C, 0xE9280103, + 0x81C, 0xE82A0103, + 0x81C, 0xE72C0103, + 0x81C, 0xE62E0103, + 0x81C, 0xE5300103, + 0x81C, 0xE4320103, + 0x81C, 0xE3340103, + 0x81C, 0xC6360103, + 0x81C, 0xC5380103, + 0x81C, 0xC43A0103, + 0x81C, 0xC33C0103, + 0x81C, 0xC23E0103, + 0x81C, 0xA5400103, + 0x81C, 0xA4420103, + 0x81C, 0xA3440103, + 0x81C, 0xA2460103, + 0x81C, 0xA1480103, + 0x81C, 0x834A0103, + 0x81C, 0x824C0103, + 0x81C, 0x814E0103, + 0x81C, 0x63500103, + 0x81C, 0x62520103, + 0x81C, 0x61540103, + 0x81C, 0x43560103, + 0x81C, 0x42580103, + 0x81C, 0x245A0103, 0x81C, 0x235C0103, 0x81C, 0x225E0103, 0x81C, 0x21600103, + 0x81C, 0x04620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000103, + 0x81C, 0xF7020103, + 0x81C, 0xF6040103, + 0x81C, 0xF5060103, + 0x81C, 0xF4080103, + 0x81C, 0xF30A0103, + 0x81C, 0xF20C0103, + 0x81C, 0xF10E0103, + 0x81C, 0xF0100103, + 0x81C, 0xEF120103, + 0x81C, 0xEE140103, + 0x81C, 0xED160103, + 0x81C, 0xEC180103, + 0x81C, 0xEB1A0103, + 0x81C, 0xEA1C0103, + 0x81C, 0xE91E0103, + 0x81C, 0xE8200103, + 0x81C, 0xE7220103, + 0x81C, 0xE6240103, + 0x81C, 0xE5260103, + 0x81C, 0xE4280103, + 0x81C, 0xE32A0103, + 0x81C, 0xE22C0103, + 0x81C, 0xC32E0103, + 0x81C, 0xC2300103, + 0x81C, 0xC1320103, + 0x81C, 0xA3340103, + 0x81C, 0xA2360103, + 0x81C, 0xA1380103, + 0x81C, 0xA03A0103, + 0x81C, 0x823C0103, + 0x81C, 0x813E0103, + 0x81C, 0x80400103, + 0x81C, 0x64420103, + 0x81C, 0x63440103, + 0x81C, 0x62460103, + 0x81C, 0x61480103, + 0x81C, 0x434A0103, + 0x81C, 0x424C0103, + 0x81C, 0x414E0103, + 0x81C, 0x40500103, + 0x81C, 0x22520103, + 0x81C, 0x21540103, + 0x81C, 0x20560103, + 0x81C, 0x04580103, + 0x81C, 0x035A0103, + 0x81C, 0x025C0103, + 0x81C, 0x015E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x9000000a, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEE1C0103, + 0x81C, 0xED1E0103, + 0x81C, 0xEC200103, + 0x81C, 0xEB220103, + 0x81C, 0xEA240103, + 0x81C, 0xE9260103, + 0x81C, 0xE8280103, + 0x81C, 0xE72A0103, + 0x81C, 0xE62C0103, + 0x81C, 0xE52E0103, + 0x81C, 0xE4300103, + 0x81C, 0xE3320103, + 0x81C, 0xE2340103, + 0x81C, 0xC5360103, + 0x81C, 0xC4380103, + 0x81C, 0xC33A0103, + 0x81C, 0xC23C0103, + 0x81C, 0xA53E0103, + 0x81C, 0xA4400103, + 0x81C, 0xA3420103, + 0x81C, 0xA2440103, + 0x81C, 0xA1460103, + 0x81C, 0x83480103, + 0x81C, 0x824A0103, + 0x81C, 0x814C0103, + 0x81C, 0x804E0103, + 0x81C, 0x63500103, + 0x81C, 0x62520103, + 0x81C, 0x61540103, + 0x81C, 0x43560103, + 0x81C, 0x42580103, + 0x81C, 0x415A0103, + 0x81C, 0x405C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x9000000b, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF9000103, + 0x81C, 0xF8020103, + 0x81C, 0xF7040103, + 0x81C, 0xF6060103, + 0x81C, 0xF5080103, + 0x81C, 0xF40A0103, + 0x81C, 0xF30C0103, + 0x81C, 0xF20E0103, + 0x81C, 0xF1100103, + 0x81C, 0xF0120103, + 0x81C, 0xEF140103, + 0x81C, 0xEE160103, + 0x81C, 0xED180103, + 0x81C, 0xEC1A0103, + 0x81C, 0xEB1C0103, + 0x81C, 0xEA1E0103, + 0x81C, 0xE9200103, + 0x81C, 0xE8220103, + 0x81C, 0xE7240103, + 0x81C, 0xE6260103, + 0x81C, 0xE5280103, + 0x81C, 0xE42A0103, + 0x81C, 0xE32C0103, + 0x81C, 0xC32E0103, + 0x81C, 0xC2300103, + 0x81C, 0xC1320103, + 0x81C, 0xA4340103, + 0x81C, 0xA3360103, + 0x81C, 0xA2380103, + 0x81C, 0xA13A0103, + 0x81C, 0xA03C0103, + 0x81C, 0x823E0103, + 0x81C, 0x81400103, + 0x81C, 0x80420103, + 0x81C, 0x63440103, + 0x81C, 0x62460103, + 0x81C, 0x61480103, + 0x81C, 0x604A0103, + 0x81C, 0x244C0103, + 0x81C, 0x234E0103, + 0x81C, 0x22500103, + 0x81C, 0x21520103, + 0x81C, 0x20540103, + 0x81C, 0x05560103, + 0x81C, 0x04580103, + 0x81C, 0x035A0103, + 0x81C, 0x025C0103, + 0x81C, 0x015E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x9000000c, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEE1C0103, + 0x81C, 0xED1E0103, + 0x81C, 0xEC200103, + 0x81C, 0xEB220103, + 0x81C, 0xEA240103, + 0x81C, 0xE9260103, + 0x81C, 0xE8280103, + 0x81C, 0xE72A0103, + 0x81C, 0xE62C0103, + 0x81C, 0xE52E0103, + 0x81C, 0xE4300103, + 0x81C, 0xE3320103, + 0x81C, 0xE2340103, + 0x81C, 0xC5360103, + 0x81C, 0xC4380103, + 0x81C, 0xC33A0103, + 0x81C, 0xC23C0103, + 0x81C, 0xA53E0103, + 0x81C, 0xA4400103, + 0x81C, 0xA3420103, + 0x81C, 0xA2440103, + 0x81C, 0xA1460103, + 0x81C, 0x83480103, + 0x81C, 0x824A0103, + 0x81C, 0x814C0103, + 0x81C, 0x804E0103, + 0x81C, 0x63500103, + 0x81C, 0x62520103, + 0x81C, 0x61540103, + 0x81C, 0x43560103, + 0x81C, 0x42580103, + 0x81C, 0x415A0103, + 0x81C, 0x405C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEE1C0103, + 0x81C, 0xED1E0103, + 0x81C, 0xEC200103, + 0x81C, 0xEB220103, + 0x81C, 0xEA240103, + 0x81C, 0xE9260103, + 0x81C, 0xE8280103, + 0x81C, 0xE72A0103, + 0x81C, 0xE62C0103, + 0x81C, 0xE52E0103, + 0x81C, 0xE4300103, + 0x81C, 0xE3320103, + 0x81C, 0xE2340103, + 0x81C, 0xC5360103, + 0x81C, 0xC4380103, + 0x81C, 0xC33A0103, + 0x81C, 0xC23C0103, + 0x81C, 0xA53E0103, + 0x81C, 0xA4400103, + 0x81C, 0xA3420103, + 0x81C, 0xA2440103, + 0x81C, 0xA1460103, + 0x81C, 0x83480103, + 0x81C, 0x824A0103, + 0x81C, 0x814C0103, + 0x81C, 0x804E0103, + 0x81C, 0x63500103, + 0x81C, 0x62520103, + 0x81C, 0x61540103, + 0x81C, 0x43560103, + 0x81C, 0x42580103, + 0x81C, 0x415A0103, + 0x81C, 0x405C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEE1C0103, + 0x81C, 0xED1E0103, + 0x81C, 0xEC200103, + 0x81C, 0xEB220103, + 0x81C, 0xEA240103, + 0x81C, 0xE9260103, + 0x81C, 0xE8280103, + 0x81C, 0xE72A0103, + 0x81C, 0xE62C0103, + 0x81C, 0xE52E0103, + 0x81C, 0xE4300103, + 0x81C, 0xE3320103, + 0x81C, 0xE2340103, + 0x81C, 0xC5360103, + 0x81C, 0xC4380103, + 0x81C, 0xC33A0103, + 0x81C, 0xC23C0103, + 0x81C, 0xA53E0103, + 0x81C, 0xA4400103, + 0x81C, 0xA3420103, + 0x81C, 0xA2440103, + 0x81C, 0xA1460103, + 0x81C, 0x83480103, + 0x81C, 0x824A0103, + 0x81C, 0x814C0103, + 0x81C, 0x804E0103, + 0x81C, 0x63500103, + 0x81C, 0x62520103, + 0x81C, 0x61540103, + 0x81C, 0x43560103, + 0x81C, 0x42580103, + 0x81C, 0x415A0103, + 0x81C, 0x405C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, 0x81C, 0x20620103, 0x81C, 0x03640103, 0x81C, 0x02660103, @@ -1170,54 +2197,119 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, - 0x81C, 0xF8000203, - 0x81C, 0xF7020203, - 0x81C, 0xF6040203, - 0x81C, 0xF5060203, - 0x81C, 0xF4080203, - 0x81C, 0xF30A0203, - 0x81C, 0xF20C0203, - 0x81C, 0xF10E0203, - 0x81C, 0xF0100203, - 0x81C, 0xEF120203, - 0x81C, 0xEE140203, - 0x81C, 0xED160203, - 0x81C, 0xEC180203, - 0x81C, 0xEB1A0203, - 0x81C, 0xEA1C0203, - 0x81C, 0xE91E0203, - 0x81C, 0xE8200203, - 0x81C, 0xE7220203, - 0x81C, 0xE6240203, - 0x81C, 0xE5260203, - 0x81C, 0xE4280203, - 0x81C, 0xE32A0203, - 0x81C, 0xC42C0203, - 0x81C, 0xC32E0203, - 0x81C, 0xC2300203, - 0x81C, 0xC1320203, - 0x81C, 0xC0340203, - 0x81C, 0xA3360203, - 0x81C, 0xA2380203, - 0x81C, 0xA13A0203, - 0x81C, 0xA03C0203, - 0x81C, 0x823E0203, - 0x81C, 0x81400203, - 0x81C, 0x80420203, - 0x81C, 0x64440203, - 0x81C, 0x63460203, - 0x81C, 0x62480203, - 0x81C, 0x614A0203, - 0x81C, 0x604C0203, - 0x81C, 0x414E0203, - 0x81C, 0x40500203, - 0x81C, 0x22520203, - 0x81C, 0x21540203, - 0x81C, 0x20560203, - 0x81C, 0x03580203, - 0x81C, 0x025A0203, - 0x81C, 0x015C0203, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000203, + 0x81C, 0xFB020203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEE1A0203, + 0x81C, 0xED1C0203, + 0x81C, 0xEC1E0203, + 0x81C, 0xEB200203, + 0x81C, 0xEA220203, + 0x81C, 0xE9240203, + 0x81C, 0xE8260203, + 0x81C, 0xE7280203, + 0x81C, 0xE62A0203, + 0x81C, 0xE52C0203, + 0x81C, 0xE42E0203, + 0x81C, 0xE3300203, + 0x81C, 0xE2320203, + 0x81C, 0xC6340203, + 0x81C, 0xC5360203, + 0x81C, 0xC4380203, + 0x81C, 0xC33A0203, + 0x81C, 0xA63C0203, + 0x81C, 0xA53E0203, + 0x81C, 0xA4400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0x83480203, + 0x81C, 0x824A0203, + 0x81C, 0x814C0203, + 0x81C, 0x804E0203, + 0x81C, 0x63500203, + 0x81C, 0x62520203, + 0x81C, 0x61540203, + 0x81C, 0x42560203, + 0x81C, 0x41580203, + 0x81C, 0x405A0203, + 0x81C, 0x225C0203, + 0x81C, 0x215E0203, + 0x81C, 0x20600203, + 0x81C, 0x04620203, + 0x81C, 0x03640203, + 0x81C, 0x02660203, + 0x81C, 0x01680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF7000203, + 0x81C, 0xF6020203, + 0x81C, 0xF5040203, + 0x81C, 0xF4060203, + 0x81C, 0xF3080203, + 0x81C, 0xF20A0203, + 0x81C, 0xF10C0203, + 0x81C, 0xF00E0203, + 0x81C, 0xEF100203, + 0x81C, 0xEE120203, + 0x81C, 0xED140203, + 0x81C, 0xEC160203, + 0x81C, 0xEB180203, + 0x81C, 0xEA1A0203, + 0x81C, 0xE91C0203, + 0x81C, 0xE81E0203, + 0x81C, 0xE7200203, + 0x81C, 0xE6220203, + 0x81C, 0xE5240203, + 0x81C, 0xE4260203, + 0x81C, 0xE3280203, + 0x81C, 0xC42A0203, + 0x81C, 0xC32C0203, + 0x81C, 0xC22E0203, + 0x81C, 0xC1300203, + 0x81C, 0xC0320203, + 0x81C, 0xA3340203, + 0x81C, 0xA2360203, + 0x81C, 0xA1380203, + 0x81C, 0xA03A0203, + 0x81C, 0x823C0203, + 0x81C, 0x813E0203, + 0x81C, 0x80400203, + 0x81C, 0x63420203, + 0x81C, 0x62440203, + 0x81C, 0x61460203, + 0x81C, 0x60480203, + 0x81C, 0x424A0203, + 0x81C, 0x414C0203, + 0x81C, 0x404E0203, + 0x81C, 0x06500203, + 0x81C, 0x05520203, + 0x81C, 0x04540203, + 0x81C, 0x03560203, + 0x81C, 0x02580203, + 0x81C, 0x015A0203, + 0x81C, 0x005C0203, 0x81C, 0x005E0203, 0x81C, 0x00600203, 0x81C, 0x00620203, @@ -1231,32 +2323,32 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x00720203, 0x81C, 0x00740203, 0x81C, 0x00760203, - 0x81C, 0x00780203, - 0x81C, 0x007A0203, - 0x81C, 0x007C0203, - 0x81C, 0x007E0203, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x81C, 0xF9000203, - 0x81C, 0xF8020203, - 0x81C, 0xF7040203, - 0x81C, 0xF6060203, - 0x81C, 0xF5080203, - 0x81C, 0xF40A0203, - 0x81C, 0xF30C0203, - 0x81C, 0xF20E0203, - 0x81C, 0xF1100203, - 0x81C, 0xF0120203, - 0x81C, 0xEF140203, - 0x81C, 0xEE160203, - 0x81C, 0xED180203, - 0x81C, 0xEC1A0203, - 0x81C, 0xEB1C0203, - 0x81C, 0xEA1E0203, - 0x81C, 0xE9200203, - 0x81C, 0xE8220203, - 0x81C, 0xE7240203, - 0x81C, 0xE6260203, - 0x81C, 0xE5280203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF7000203, + 0x81C, 0xF6020203, + 0x81C, 0xF5040203, + 0x81C, 0xF4060203, + 0x81C, 0xF3080203, + 0x81C, 0xF20A0203, + 0x81C, 0xF10C0203, + 0x81C, 0xF00E0203, + 0x81C, 0xEF100203, + 0x81C, 0xEE120203, + 0x81C, 0xED140203, + 0x81C, 0xEC160203, + 0x81C, 0xEB180203, + 0x81C, 0xEA1A0203, + 0x81C, 0xE91C0203, + 0x81C, 0xE81E0203, + 0x81C, 0xE7200203, + 0x81C, 0xE6220203, + 0x81C, 0xE5240203, + 0x81C, 0xE4260203, + 0x81C, 0xE3280203, 0x81C, 0xC42A0203, 0x81C, 0xC32C0203, 0x81C, 0xC22E0203, @@ -1300,7 +2392,72 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0203, 0x81C, 0x007C0203, 0x81C, 0x007E0203, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000203, + 0x81C, 0xFB020203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEF1A0203, + 0x81C, 0xEE1C0203, + 0x81C, 0xED1E0203, + 0x81C, 0xEC200203, + 0x81C, 0xEB220203, + 0x81C, 0xEA240203, + 0x81C, 0xE9260203, + 0x81C, 0xE8280203, + 0x81C, 0xE72A0203, + 0x81C, 0xE62C0203, + 0x81C, 0xE52E0203, + 0x81C, 0xE4300203, + 0x81C, 0xE3320203, + 0x81C, 0xE2340203, + 0x81C, 0xC6360203, + 0x81C, 0xC5380203, + 0x81C, 0xC43A0203, + 0x81C, 0xC33C0203, + 0x81C, 0xA63E0203, + 0x81C, 0xA5400203, + 0x81C, 0xA4420203, + 0x81C, 0xA3440203, + 0x81C, 0xA2460203, + 0x81C, 0xA1480203, + 0x81C, 0x834A0203, + 0x81C, 0x824C0203, + 0x81C, 0x814E0203, + 0x81C, 0x64500203, + 0x81C, 0x63520203, + 0x81C, 0x62540203, + 0x81C, 0x61560203, + 0x81C, 0x60580203, + 0x81C, 0x405A0203, + 0x81C, 0x215C0203, + 0x81C, 0x205E0203, + 0x81C, 0x03600203, + 0x81C, 0x02620203, + 0x81C, 0x01640203, + 0x81C, 0x00660203, + 0x81C, 0x00680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xF7000203, 0x81C, 0xF6020203, 0x81C, 0xF5040203, @@ -1365,33 +2522,293 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0203, 0x81C, 0x007C0203, 0x81C, 0x007E0203, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000203, - 0x81C, 0xF6020203, - 0x81C, 0xF5040203, - 0x81C, 0xF4060203, - 0x81C, 0xF3080203, - 0x81C, 0xF20A0203, - 0x81C, 0xF10C0203, - 0x81C, 0xF00E0203, - 0x81C, 0xEF100203, - 0x81C, 0xEE120203, - 0x81C, 0xED140203, - 0x81C, 0xEC160203, - 0x81C, 0xEB180203, - 0x81C, 0xEA1A0203, - 0x81C, 0xE91C0203, - 0x81C, 0xE81E0203, - 0x81C, 0xE7200203, - 0x81C, 0xE6220203, - 0x81C, 0xE5240203, - 0x81C, 0xE4260203, - 0x81C, 0xE3280203, - 0x81C, 0xC42A0203, - 0x81C, 0xC32C0203, - 0x81C, 0xC22E0203, - 0x81C, 0xC1300203, - 0x81C, 0xC0320203, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000203, + 0x81C, 0xFB020203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEF1A0203, + 0x81C, 0xEE1C0203, + 0x81C, 0xED1E0203, + 0x81C, 0xEC200203, + 0x81C, 0xEB220203, + 0x81C, 0xEA240203, + 0x81C, 0xE9260203, + 0x81C, 0xE8280203, + 0x81C, 0xE72A0203, + 0x81C, 0xE62C0203, + 0x81C, 0xE52E0203, + 0x81C, 0xE4300203, + 0x81C, 0xE3320203, + 0x81C, 0xE2340203, + 0x81C, 0xE1360203, + 0x81C, 0xC5380203, + 0x81C, 0xC43A0203, + 0x81C, 0xC33C0203, + 0x81C, 0xC23E0203, + 0x81C, 0xC1400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0xA0480203, + 0x81C, 0x834A0203, + 0x81C, 0x824C0203, + 0x81C, 0x814E0203, + 0x81C, 0x64500203, + 0x81C, 0x63520203, + 0x81C, 0x62540203, + 0x81C, 0x61560203, + 0x81C, 0x25580203, + 0x81C, 0x245A0203, + 0x81C, 0x235C0203, + 0x81C, 0x225E0203, + 0x81C, 0x21600203, + 0x81C, 0x04620203, + 0x81C, 0x03640203, + 0x81C, 0x02660203, + 0x81C, 0x01680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF9000203, + 0x81C, 0xF8020203, + 0x81C, 0xF7040203, + 0x81C, 0xF6060203, + 0x81C, 0xF5080203, + 0x81C, 0xF40A0203, + 0x81C, 0xF30C0203, + 0x81C, 0xF20E0203, + 0x81C, 0xF1100203, + 0x81C, 0xF0120203, + 0x81C, 0xEF140203, + 0x81C, 0xEE160203, + 0x81C, 0xED180203, + 0x81C, 0xEC1A0203, + 0x81C, 0xEB1C0203, + 0x81C, 0xEA1E0203, + 0x81C, 0xE9200203, + 0x81C, 0xE8220203, + 0x81C, 0xE7240203, + 0x81C, 0xE6260203, + 0x81C, 0xE5280203, + 0x81C, 0xC42A0203, + 0x81C, 0xC32C0203, + 0x81C, 0xC22E0203, + 0x81C, 0xC1300203, + 0x81C, 0xC0320203, + 0x81C, 0xA3340203, + 0x81C, 0xA2360203, + 0x81C, 0xA1380203, + 0x81C, 0xA03A0203, + 0x81C, 0x823C0203, + 0x81C, 0x813E0203, + 0x81C, 0x80400203, + 0x81C, 0x64420203, + 0x81C, 0x63440203, + 0x81C, 0x62460203, + 0x81C, 0x61480203, + 0x81C, 0x604A0203, + 0x81C, 0x414C0203, + 0x81C, 0x404E0203, + 0x81C, 0x22500203, + 0x81C, 0x21520203, + 0x81C, 0x20540203, + 0x81C, 0x03560203, + 0x81C, 0x02580203, + 0x81C, 0x015A0203, + 0x81C, 0x005C0203, + 0x81C, 0x005E0203, + 0x81C, 0x00600203, + 0x81C, 0x00620203, + 0x81C, 0x00640203, + 0x81C, 0x00660203, + 0x81C, 0x00680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000203, + 0x81C, 0xF7020203, + 0x81C, 0xF6040203, + 0x81C, 0xF5060203, + 0x81C, 0xF4080203, + 0x81C, 0xF30A0203, + 0x81C, 0xF20C0203, + 0x81C, 0xF10E0203, + 0x81C, 0xF0100203, + 0x81C, 0xEF120203, + 0x81C, 0xEE140203, + 0x81C, 0xED160203, + 0x81C, 0xEC180203, + 0x81C, 0xEB1A0203, + 0x81C, 0xEA1C0203, + 0x81C, 0xE91E0203, + 0x81C, 0xE8200203, + 0x81C, 0xE7220203, + 0x81C, 0xE6240203, + 0x81C, 0xE5260203, + 0x81C, 0xE4280203, + 0x81C, 0xE32A0203, + 0x81C, 0xC42C0203, + 0x81C, 0xC32E0203, + 0x81C, 0xC2300203, + 0x81C, 0xC1320203, + 0x81C, 0xA3340203, + 0x81C, 0xA2360203, + 0x81C, 0xA1380203, + 0x81C, 0xA03A0203, + 0x81C, 0x823C0203, + 0x81C, 0x813E0203, + 0x81C, 0x80400203, + 0x81C, 0x65420203, + 0x81C, 0x64440203, + 0x81C, 0x63460203, + 0x81C, 0x62480203, + 0x81C, 0x614A0203, + 0x81C, 0x424C0203, + 0x81C, 0x414E0203, + 0x81C, 0x40500203, + 0x81C, 0x22520203, + 0x81C, 0x21540203, + 0x81C, 0x20560203, + 0x81C, 0x04580203, + 0x81C, 0x035A0203, + 0x81C, 0x025C0203, + 0x81C, 0x015E0203, + 0x81C, 0x00600203, + 0x81C, 0x00620203, + 0x81C, 0x00640203, + 0x81C, 0x00660203, + 0x81C, 0x00680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000203, + 0x81C, 0xFA020203, + 0x81C, 0xF9040203, + 0x81C, 0xF8060203, + 0x81C, 0xF7080203, + 0x81C, 0xF60A0203, + 0x81C, 0xF50C0203, + 0x81C, 0xF40E0203, + 0x81C, 0xF3100203, + 0x81C, 0xF2120203, + 0x81C, 0xF1140203, + 0x81C, 0xF0160203, + 0x81C, 0xEF180203, + 0x81C, 0xEE1A0203, + 0x81C, 0xED1C0203, + 0x81C, 0xEC1E0203, + 0x81C, 0xEB200203, + 0x81C, 0xEA220203, + 0x81C, 0xE9240203, + 0x81C, 0xE8260203, + 0x81C, 0xE7280203, + 0x81C, 0xE62A0203, + 0x81C, 0xE52C0203, + 0x81C, 0xE42E0203, + 0x81C, 0xE3300203, + 0x81C, 0xE2320203, + 0x81C, 0xC6340203, + 0x81C, 0xC5360203, + 0x81C, 0xC4380203, + 0x81C, 0xC33A0203, + 0x81C, 0xC23C0203, + 0x81C, 0xC13E0203, + 0x81C, 0xC0400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0xA0480203, + 0x81C, 0x824A0203, + 0x81C, 0x814C0203, + 0x81C, 0x804E0203, + 0x81C, 0x63500203, + 0x81C, 0x62520203, + 0x81C, 0x61540203, + 0x81C, 0x60560203, + 0x81C, 0x24580203, + 0x81C, 0x235A0203, + 0x81C, 0x225C0203, + 0x81C, 0x215E0203, + 0x81C, 0x20600203, + 0x81C, 0x03620203, + 0x81C, 0x02640203, + 0x81C, 0x01660203, + 0x81C, 0x00680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000203, + 0x81C, 0xF7020203, + 0x81C, 0xF6040203, + 0x81C, 0xF5060203, + 0x81C, 0xF4080203, + 0x81C, 0xF30A0203, + 0x81C, 0xF20C0203, + 0x81C, 0xF10E0203, + 0x81C, 0xF0100203, + 0x81C, 0xEF120203, + 0x81C, 0xEE140203, + 0x81C, 0xED160203, + 0x81C, 0xEC180203, + 0x81C, 0xEB1A0203, + 0x81C, 0xEA1C0203, + 0x81C, 0xE91E0203, + 0x81C, 0xE8200203, + 0x81C, 0xE7220203, + 0x81C, 0xE6240203, + 0x81C, 0xE5260203, + 0x81C, 0xE4280203, + 0x81C, 0xE32A0203, + 0x81C, 0xC42C0203, + 0x81C, 0xC32E0203, + 0x81C, 0xC2300203, + 0x81C, 0xC1320203, 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203, @@ -1399,21 +2816,21 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x823C0203, 0x81C, 0x813E0203, 0x81C, 0x80400203, - 0x81C, 0x64420203, - 0x81C, 0x63440203, - 0x81C, 0x62460203, - 0x81C, 0x61480203, - 0x81C, 0x604A0203, - 0x81C, 0x414C0203, - 0x81C, 0x404E0203, - 0x81C, 0x22500203, - 0x81C, 0x21520203, - 0x81C, 0x20540203, - 0x81C, 0x03560203, - 0x81C, 0x02580203, - 0x81C, 0x015A0203, - 0x81C, 0x005C0203, - 0x81C, 0x005E0203, + 0x81C, 0x65420203, + 0x81C, 0x64440203, + 0x81C, 0x63460203, + 0x81C, 0x62480203, + 0x81C, 0x614A0203, + 0x81C, 0x424C0203, + 0x81C, 0x414E0203, + 0x81C, 0x40500203, + 0x81C, 0x22520203, + 0x81C, 0x21540203, + 0x81C, 0x20560203, + 0x81C, 0x04580203, + 0x81C, 0x035A0203, + 0x81C, 0x025C0203, + 0x81C, 0x015E0203, 0x81C, 0x00600203, 0x81C, 0x00620203, 0x81C, 0x00640203, @@ -1430,33 +2847,98 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0203, 0x81C, 0x007C0203, 0x81C, 0x007E0203, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000203, - 0x81C, 0xF6020203, - 0x81C, 0xF5040203, - 0x81C, 0xF4060203, - 0x81C, 0xF3080203, - 0x81C, 0xF20A0203, - 0x81C, 0xF10C0203, - 0x81C, 0xF00E0203, - 0x81C, 0xEF100203, - 0x81C, 0xEE120203, - 0x81C, 0xED140203, - 0x81C, 0xEC160203, - 0x81C, 0xEB180203, - 0x81C, 0xEA1A0203, - 0x81C, 0xE91C0203, - 0x81C, 0xE81E0203, - 0x81C, 0xE7200203, - 0x81C, 0xE6220203, - 0x81C, 0xE5240203, - 0x81C, 0xE4260203, - 0x81C, 0xE3280203, - 0x81C, 0xC42A0203, - 0x81C, 0xC32C0203, - 0x81C, 0xC22E0203, - 0x81C, 0xC1300203, - 0x81C, 0xC0320203, + 0x9000000a, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000203, + 0x81C, 0xFB020203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEE1A0203, + 0x81C, 0xED1C0203, + 0x81C, 0xEC1E0203, + 0x81C, 0xEB200203, + 0x81C, 0xEA220203, + 0x81C, 0xE9240203, + 0x81C, 0xE8260203, + 0x81C, 0xE7280203, + 0x81C, 0xE62A0203, + 0x81C, 0xE52C0203, + 0x81C, 0xE42E0203, + 0x81C, 0xE3300203, + 0x81C, 0xE2320203, + 0x81C, 0xC6340203, + 0x81C, 0xC5360203, + 0x81C, 0xC4380203, + 0x81C, 0xC33A0203, + 0x81C, 0xA63C0203, + 0x81C, 0xA53E0203, + 0x81C, 0xA4400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0x83480203, + 0x81C, 0x824A0203, + 0x81C, 0x814C0203, + 0x81C, 0x804E0203, + 0x81C, 0x63500203, + 0x81C, 0x62520203, + 0x81C, 0x61540203, + 0x81C, 0x42560203, + 0x81C, 0x41580203, + 0x81C, 0x405A0203, + 0x81C, 0x225C0203, + 0x81C, 0x215E0203, + 0x81C, 0x20600203, + 0x81C, 0x04620203, + 0x81C, 0x03640203, + 0x81C, 0x02660203, + 0x81C, 0x01680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0x9000000b, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF9000203, + 0x81C, 0xF8020203, + 0x81C, 0xF7040203, + 0x81C, 0xF6060203, + 0x81C, 0xF5080203, + 0x81C, 0xF40A0203, + 0x81C, 0xF30C0203, + 0x81C, 0xF20E0203, + 0x81C, 0xF1100203, + 0x81C, 0xF0120203, + 0x81C, 0xEF140203, + 0x81C, 0xEE160203, + 0x81C, 0xED180203, + 0x81C, 0xEC1A0203, + 0x81C, 0xEB1C0203, + 0x81C, 0xEA1E0203, + 0x81C, 0xE9200203, + 0x81C, 0xE8220203, + 0x81C, 0xE7240203, + 0x81C, 0xE6260203, + 0x81C, 0xE5280203, + 0x81C, 0xE42A0203, + 0x81C, 0xC42C0203, + 0x81C, 0xC32E0203, + 0x81C, 0xC2300203, + 0x81C, 0xC1320203, 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203, @@ -1469,16 +2951,16 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x62460203, 0x81C, 0x61480203, 0x81C, 0x604A0203, - 0x81C, 0x414C0203, - 0x81C, 0x404E0203, + 0x81C, 0x244C0203, + 0x81C, 0x234E0203, 0x81C, 0x22500203, 0x81C, 0x21520203, 0x81C, 0x20540203, - 0x81C, 0x03560203, - 0x81C, 0x02580203, - 0x81C, 0x015A0203, - 0x81C, 0x005C0203, - 0x81C, 0x005E0203, + 0x81C, 0x05560203, + 0x81C, 0x04580203, + 0x81C, 0x035A0203, + 0x81C, 0x025C0203, + 0x81C, 0x015E0203, 0x81C, 0x00600203, 0x81C, 0x00620203, 0x81C, 0x00640203, @@ -1495,7 +2977,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0203, 0x81C, 0x007C0203, 0x81C, 0x007E0203, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x9000000c, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFC000203, 0x81C, 0xFB020203, 0x81C, 0xFA040203, @@ -1509,46 +2991,46 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0xF2140203, 0x81C, 0xF1160203, 0x81C, 0xF0180203, - 0x81C, 0xEF1A0203, - 0x81C, 0xEE1C0203, - 0x81C, 0xED1E0203, - 0x81C, 0xEC200203, - 0x81C, 0xEB220203, - 0x81C, 0xEA240203, - 0x81C, 0xE9260203, - 0x81C, 0xE8280203, - 0x81C, 0xE72A0203, - 0x81C, 0xE62C0203, - 0x81C, 0xE52E0203, - 0x81C, 0xE4300203, - 0x81C, 0xE3320203, - 0x81C, 0xE2340203, - 0x81C, 0xC6360203, - 0x81C, 0xC5380203, - 0x81C, 0xC43A0203, - 0x81C, 0xC33C0203, - 0x81C, 0xA63E0203, - 0x81C, 0xA5400203, - 0x81C, 0xA4420203, - 0x81C, 0xA3440203, - 0x81C, 0xA2460203, - 0x81C, 0xA1480203, - 0x81C, 0x834A0203, - 0x81C, 0x824C0203, - 0x81C, 0x814E0203, - 0x81C, 0x64500203, - 0x81C, 0x63520203, - 0x81C, 0x62540203, - 0x81C, 0x61560203, - 0x81C, 0x60580203, + 0x81C, 0xEE1A0203, + 0x81C, 0xED1C0203, + 0x81C, 0xEC1E0203, + 0x81C, 0xEB200203, + 0x81C, 0xEA220203, + 0x81C, 0xE9240203, + 0x81C, 0xE8260203, + 0x81C, 0xE7280203, + 0x81C, 0xE62A0203, + 0x81C, 0xE52C0203, + 0x81C, 0xE42E0203, + 0x81C, 0xE3300203, + 0x81C, 0xE2320203, + 0x81C, 0xC6340203, + 0x81C, 0xC5360203, + 0x81C, 0xC4380203, + 0x81C, 0xC33A0203, + 0x81C, 0xA63C0203, + 0x81C, 0xA53E0203, + 0x81C, 0xA4400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0x83480203, + 0x81C, 0x824A0203, + 0x81C, 0x814C0203, + 0x81C, 0x804E0203, + 0x81C, 0x63500203, + 0x81C, 0x62520203, + 0x81C, 0x61540203, + 0x81C, 0x42560203, + 0x81C, 0x41580203, 0x81C, 0x405A0203, - 0x81C, 0x215C0203, - 0x81C, 0x205E0203, - 0x81C, 0x03600203, - 0x81C, 0x02620203, - 0x81C, 0x01640203, - 0x81C, 0x00660203, - 0x81C, 0x00680203, + 0x81C, 0x225C0203, + 0x81C, 0x215E0203, + 0x81C, 0x20600203, + 0x81C, 0x04620203, + 0x81C, 0x03640203, + 0x81C, 0x02660203, + 0x81C, 0x01680203, 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203, @@ -1560,60 +3042,60 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0203, 0x81C, 0x007C0203, 0x81C, 0x007E0203, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFC000203, 0x81C, 0xFB020203, - 0x81C, 0xFA040203, - 0x81C, 0xF9060203, - 0x81C, 0xF8080203, - 0x81C, 0xF70A0203, - 0x81C, 0xF60C0203, - 0x81C, 0xF50E0203, - 0x81C, 0xF4100203, - 0x81C, 0xF3120203, - 0x81C, 0xF2140203, - 0x81C, 0xF1160203, - 0x81C, 0xF0180203, - 0x81C, 0xEF1A0203, - 0x81C, 0xEE1C0203, - 0x81C, 0xED1E0203, - 0x81C, 0xEC200203, - 0x81C, 0xEB220203, - 0x81C, 0xEA240203, - 0x81C, 0xE9260203, - 0x81C, 0xE8280203, - 0x81C, 0xE72A0203, - 0x81C, 0xE62C0203, - 0x81C, 0xE52E0203, - 0x81C, 0xE4300203, - 0x81C, 0xE3320203, - 0x81C, 0xE2340203, - 0x81C, 0xC6360203, - 0x81C, 0xC5380203, - 0x81C, 0xC43A0203, - 0x81C, 0xC33C0203, - 0x81C, 0xA63E0203, - 0x81C, 0xA5400203, - 0x81C, 0xA4420203, - 0x81C, 0xA3440203, - 0x81C, 0xA2460203, - 0x81C, 0xA1480203, - 0x81C, 0x834A0203, - 0x81C, 0x824C0203, - 0x81C, 0x814E0203, - 0x81C, 0x64500203, - 0x81C, 0x63520203, - 0x81C, 0x62540203, - 0x81C, 0x61560203, - 0x81C, 0x60580203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEE1A0203, + 0x81C, 0xED1C0203, + 0x81C, 0xEC1E0203, + 0x81C, 0xEB200203, + 0x81C, 0xEA220203, + 0x81C, 0xE9240203, + 0x81C, 0xE8260203, + 0x81C, 0xE7280203, + 0x81C, 0xE62A0203, + 0x81C, 0xE52C0203, + 0x81C, 0xE42E0203, + 0x81C, 0xE3300203, + 0x81C, 0xE2320203, + 0x81C, 0xC6340203, + 0x81C, 0xC5360203, + 0x81C, 0xC4380203, + 0x81C, 0xC33A0203, + 0x81C, 0xA63C0203, + 0x81C, 0xA53E0203, + 0x81C, 0xA4400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0x83480203, + 0x81C, 0x824A0203, + 0x81C, 0x814C0203, + 0x81C, 0x804E0203, + 0x81C, 0x63500203, + 0x81C, 0x62520203, + 0x81C, 0x61540203, + 0x81C, 0x42560203, + 0x81C, 0x41580203, 0x81C, 0x405A0203, - 0x81C, 0x215C0203, - 0x81C, 0x205E0203, - 0x81C, 0x03600203, - 0x81C, 0x02620203, - 0x81C, 0x01640203, - 0x81C, 0x00660203, - 0x81C, 0x00680203, + 0x81C, 0x225C0203, + 0x81C, 0x215E0203, + 0x81C, 0x20600203, + 0x81C, 0x04620203, + 0x81C, 0x03640203, + 0x81C, 0x02660203, + 0x81C, 0x01680203, 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203, @@ -1625,7 +3107,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0203, 0x81C, 0x007C0203, 0x81C, 0x007E0203, - 0xA0000000, 0x00000000, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFC000203, 0x81C, 0xFB020203, 0x81C, 0xFA040203, @@ -1639,20 +3121,85 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0xF2140203, 0x81C, 0xF1160203, 0x81C, 0xF0180203, - 0x81C, 0xEF1A0203, - 0x81C, 0xEE1C0203, - 0x81C, 0xED1E0203, - 0x81C, 0xEC200203, - 0x81C, 0xEB220203, - 0x81C, 0xEA240203, - 0x81C, 0xE9260203, - 0x81C, 0xE8280203, - 0x81C, 0xE72A0203, - 0x81C, 0xE62C0203, - 0x81C, 0xE52E0203, - 0x81C, 0xE4300203, - 0x81C, 0xE3320203, - 0x81C, 0xE2340203, + 0x81C, 0xEE1A0203, + 0x81C, 0xED1C0203, + 0x81C, 0xEC1E0203, + 0x81C, 0xEB200203, + 0x81C, 0xEA220203, + 0x81C, 0xE9240203, + 0x81C, 0xE8260203, + 0x81C, 0xE7280203, + 0x81C, 0xE62A0203, + 0x81C, 0xE52C0203, + 0x81C, 0xE42E0203, + 0x81C, 0xE3300203, + 0x81C, 0xE2320203, + 0x81C, 0xC6340203, + 0x81C, 0xC5360203, + 0x81C, 0xC4380203, + 0x81C, 0xC33A0203, + 0x81C, 0xA63C0203, + 0x81C, 0xA53E0203, + 0x81C, 0xA4400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0x83480203, + 0x81C, 0x824A0203, + 0x81C, 0x814C0203, + 0x81C, 0x804E0203, + 0x81C, 0x63500203, + 0x81C, 0x62520203, + 0x81C, 0x61540203, + 0x81C, 0x42560203, + 0x81C, 0x41580203, + 0x81C, 0x405A0203, + 0x81C, 0x225C0203, + 0x81C, 0x215E0203, + 0x81C, 0x20600203, + 0x81C, 0x04620203, + 0x81C, 0x03640203, + 0x81C, 0x02660203, + 0x81C, 0x01680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0xA0000000, 0x00000000, + 0x81C, 0xFD000203, + 0x81C, 0xFC020203, + 0x81C, 0xFB040203, + 0x81C, 0xFA060203, + 0x81C, 0xF9080203, + 0x81C, 0xF80A0203, + 0x81C, 0xF70C0203, + 0x81C, 0xF60E0203, + 0x81C, 0xF5100203, + 0x81C, 0xF4120203, + 0x81C, 0xF3140203, + 0x81C, 0xF2160203, + 0x81C, 0xF1180203, + 0x81C, 0xF01A0203, + 0x81C, 0xEF1C0203, + 0x81C, 0xEE1E0203, + 0x81C, 0xED200203, + 0x81C, 0xEC220203, + 0x81C, 0xEB240203, + 0x81C, 0xEA260203, + 0x81C, 0xE9280203, + 0x81C, 0xE82A0203, + 0x81C, 0xE72C0203, + 0x81C, 0xE62E0203, + 0x81C, 0xE5300203, + 0x81C, 0xE4320203, + 0x81C, 0xE3340203, 0x81C, 0xC6360203, 0x81C, 0xC5380203, 0x81C, 0xC43A0203, @@ -1671,13 +3218,13 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x62540203, 0x81C, 0x61560203, 0x81C, 0x60580203, - 0x81C, 0x405A0203, - 0x81C, 0x215C0203, - 0x81C, 0x205E0203, - 0x81C, 0x03600203, - 0x81C, 0x02620203, - 0x81C, 0x01640203, - 0x81C, 0x00660203, + 0x81C, 0x235A0203, + 0x81C, 0x225C0203, + 0x81C, 0x215E0203, + 0x81C, 0x20600203, + 0x81C, 0x03620203, + 0x81C, 0x02640203, + 0x81C, 0x01660203, 0x81C, 0x00680203, 0x81C, 0x006A0203, 0x81C, 0x006C0203, @@ -1691,54 +3238,119 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, - 0x81C, 0xF8000303, - 0x81C, 0xF7020303, - 0x81C, 0xF6040303, - 0x81C, 0xF5060303, - 0x81C, 0xF4080303, - 0x81C, 0xF30A0303, - 0x81C, 0xF20C0303, - 0x81C, 0xF10E0303, - 0x81C, 0xF0100303, - 0x81C, 0xEF120303, - 0x81C, 0xEE140303, - 0x81C, 0xED160303, - 0x81C, 0xEC180303, - 0x81C, 0xEB1A0303, - 0x81C, 0xEA1C0303, - 0x81C, 0xE91E0303, - 0x81C, 0xCA200303, - 0x81C, 0xC9220303, - 0x81C, 0xC8240303, - 0x81C, 0xC7260303, - 0x81C, 0xC6280303, - 0x81C, 0xC52A0303, - 0x81C, 0xC42C0303, - 0x81C, 0xC32E0303, - 0x81C, 0xC2300303, - 0x81C, 0xC1320303, - 0x81C, 0xA4340303, - 0x81C, 0xA3360303, - 0x81C, 0xA2380303, - 0x81C, 0xA13A0303, - 0x81C, 0xA03C0303, - 0x81C, 0x823E0303, - 0x81C, 0x81400303, - 0x81C, 0x80420303, - 0x81C, 0x64440303, - 0x81C, 0x63460303, - 0x81C, 0x62480303, - 0x81C, 0x614A0303, - 0x81C, 0x604C0303, - 0x81C, 0x414E0303, - 0x81C, 0x40500303, - 0x81C, 0x22520303, - 0x81C, 0x21540303, - 0x81C, 0x20560303, - 0x81C, 0x03580303, - 0x81C, 0x025A0303, - 0x81C, 0x015C0303, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000303, + 0x81C, 0xFB020303, + 0x81C, 0xFA040303, + 0x81C, 0xF9060303, + 0x81C, 0xF8080303, + 0x81C, 0xF70A0303, + 0x81C, 0xF60C0303, + 0x81C, 0xF50E0303, + 0x81C, 0xF4100303, + 0x81C, 0xF3120303, + 0x81C, 0xF2140303, + 0x81C, 0xF1160303, + 0x81C, 0xEF180303, + 0x81C, 0xEE1A0303, + 0x81C, 0xED1C0303, + 0x81C, 0xEC1E0303, + 0x81C, 0xEB200303, + 0x81C, 0xEA220303, + 0x81C, 0xE9240303, + 0x81C, 0xE8260303, + 0x81C, 0xE7280303, + 0x81C, 0xE62A0303, + 0x81C, 0xE52C0303, + 0x81C, 0xE42E0303, + 0x81C, 0xE3300303, + 0x81C, 0xE2320303, + 0x81C, 0xC6340303, + 0x81C, 0xC5360303, + 0x81C, 0xC4380303, + 0x81C, 0xC33A0303, + 0x81C, 0xA63C0303, + 0x81C, 0xA53E0303, + 0x81C, 0xA4400303, + 0x81C, 0xA3420303, + 0x81C, 0xA2440303, + 0x81C, 0xA1460303, + 0x81C, 0x83480303, + 0x81C, 0x824A0303, + 0x81C, 0x814C0303, + 0x81C, 0x804E0303, + 0x81C, 0x63500303, + 0x81C, 0x62520303, + 0x81C, 0x61540303, + 0x81C, 0x42560303, + 0x81C, 0x41580303, + 0x81C, 0x405A0303, + 0x81C, 0x225C0303, + 0x81C, 0x215E0303, + 0x81C, 0x20600303, + 0x81C, 0x04620303, + 0x81C, 0x03640303, + 0x81C, 0x02660303, + 0x81C, 0x01680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF7000303, + 0x81C, 0xF6020303, + 0x81C, 0xF5040303, + 0x81C, 0xF4060303, + 0x81C, 0xF3080303, + 0x81C, 0xF20A0303, + 0x81C, 0xF10C0303, + 0x81C, 0xF00E0303, + 0x81C, 0xEF100303, + 0x81C, 0xEE120303, + 0x81C, 0xED140303, + 0x81C, 0xEC160303, + 0x81C, 0xEB180303, + 0x81C, 0xEA1A0303, + 0x81C, 0xE91C0303, + 0x81C, 0xCA1E0303, + 0x81C, 0xC9200303, + 0x81C, 0xC8220303, + 0x81C, 0xC7240303, + 0x81C, 0xC6260303, + 0x81C, 0xC5280303, + 0x81C, 0xC42A0303, + 0x81C, 0xC32C0303, + 0x81C, 0xC22E0303, + 0x81C, 0xC1300303, + 0x81C, 0xA4320303, + 0x81C, 0xA3340303, + 0x81C, 0xA2360303, + 0x81C, 0xA1380303, + 0x81C, 0xA03A0303, + 0x81C, 0x823C0303, + 0x81C, 0x813E0303, + 0x81C, 0x80400303, + 0x81C, 0x64420303, + 0x81C, 0x63440303, + 0x81C, 0x62460303, + 0x81C, 0x61480303, + 0x81C, 0x604A0303, + 0x81C, 0x414C0303, + 0x81C, 0x404E0303, + 0x81C, 0x06500303, + 0x81C, 0x05520303, + 0x81C, 0x04540303, + 0x81C, 0x03560303, + 0x81C, 0x02580303, + 0x81C, 0x015A0303, + 0x81C, 0x005C0303, 0x81C, 0x005E0303, 0x81C, 0x00600303, 0x81C, 0x00620303, @@ -1756,32 +3368,32 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0303, 0x81C, 0x007C0303, 0x81C, 0x007E0303, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x81C, 0xF8000303, - 0x81C, 0xF7020303, - 0x81C, 0xF6040303, - 0x81C, 0xF5060303, - 0x81C, 0xF4080303, - 0x81C, 0xF30A0303, - 0x81C, 0xF20C0303, - 0x81C, 0xF10E0303, - 0x81C, 0xF0100303, - 0x81C, 0xEF120303, - 0x81C, 0xEE140303, - 0x81C, 0xED160303, - 0x81C, 0xEC180303, - 0x81C, 0xEB1A0303, - 0x81C, 0xEA1C0303, - 0x81C, 0xC91E0303, - 0x81C, 0xC8200303, - 0x81C, 0xC7220303, - 0x81C, 0xC6240303, - 0x81C, 0xC5260303, - 0x81C, 0xC4280303, - 0x81C, 0xC32A0303, - 0x81C, 0xC22C0303, - 0x81C, 0xC12E0303, - 0x81C, 0xC0300303, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF7000303, + 0x81C, 0xF6020303, + 0x81C, 0xF5040303, + 0x81C, 0xF4060303, + 0x81C, 0xF3080303, + 0x81C, 0xF20A0303, + 0x81C, 0xF10C0303, + 0x81C, 0xF00E0303, + 0x81C, 0xEF100303, + 0x81C, 0xEE120303, + 0x81C, 0xED140303, + 0x81C, 0xEC160303, + 0x81C, 0xEB180303, + 0x81C, 0xEA1A0303, + 0x81C, 0xE91C0303, + 0x81C, 0xCA1E0303, + 0x81C, 0xC9200303, + 0x81C, 0xC8220303, + 0x81C, 0xC7240303, + 0x81C, 0xC6260303, + 0x81C, 0xC5280303, + 0x81C, 0xC42A0303, + 0x81C, 0xC32C0303, + 0x81C, 0xC22E0303, + 0x81C, 0xC1300303, 0x81C, 0xA4320303, 0x81C, 0xA3340303, 0x81C, 0xA2360303, @@ -1790,20 +3402,20 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x823C0303, 0x81C, 0x813E0303, 0x81C, 0x80400303, - 0x81C, 0x65420303, - 0x81C, 0x64440303, - 0x81C, 0x63460303, - 0x81C, 0x62480303, - 0x81C, 0x614A0303, - 0x81C, 0x604C0303, - 0x81C, 0x414E0303, - 0x81C, 0x40500303, - 0x81C, 0x22520303, - 0x81C, 0x21540303, - 0x81C, 0x20560303, - 0x81C, 0x03580303, - 0x81C, 0x025A0303, - 0x81C, 0x015C0303, + 0x81C, 0x64420303, + 0x81C, 0x63440303, + 0x81C, 0x62460303, + 0x81C, 0x61480303, + 0x81C, 0x604A0303, + 0x81C, 0x414C0303, + 0x81C, 0x404E0303, + 0x81C, 0x22500303, + 0x81C, 0x21520303, + 0x81C, 0x20540303, + 0x81C, 0x03560303, + 0x81C, 0x02580303, + 0x81C, 0x015A0303, + 0x81C, 0x005C0303, 0x81C, 0x005E0303, 0x81C, 0x00600303, 0x81C, 0x00620303, @@ -1821,7 +3433,72 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0303, 0x81C, 0x007C0303, 0x81C, 0x007E0303, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000303, + 0x81C, 0xFB020303, + 0x81C, 0xFA040303, + 0x81C, 0xF9060303, + 0x81C, 0xF8080303, + 0x81C, 0xF70A0303, + 0x81C, 0xF60C0303, + 0x81C, 0xF50E0303, + 0x81C, 0xF4100303, + 0x81C, 0xF3120303, + 0x81C, 0xF2140303, + 0x81C, 0xF1160303, + 0x81C, 0xF0180303, + 0x81C, 0xEF1A0303, + 0x81C, 0xEE1C0303, + 0x81C, 0xED1E0303, + 0x81C, 0xEC200303, + 0x81C, 0xEB220303, + 0x81C, 0xEA240303, + 0x81C, 0xE9260303, + 0x81C, 0xE8280303, + 0x81C, 0xE72A0303, + 0x81C, 0xE62C0303, + 0x81C, 0xE52E0303, + 0x81C, 0xE4300303, + 0x81C, 0xE3320303, + 0x81C, 0xE2340303, + 0x81C, 0xC6360303, + 0x81C, 0xC5380303, + 0x81C, 0xC43A0303, + 0x81C, 0xC33C0303, + 0x81C, 0xA63E0303, + 0x81C, 0xA5400303, + 0x81C, 0xA4420303, + 0x81C, 0xA3440303, + 0x81C, 0xA2460303, + 0x81C, 0x84480303, + 0x81C, 0x834A0303, + 0x81C, 0x824C0303, + 0x81C, 0x814E0303, + 0x81C, 0x80500303, + 0x81C, 0x63520303, + 0x81C, 0x62540303, + 0x81C, 0x61560303, + 0x81C, 0x60580303, + 0x81C, 0x225A0303, + 0x81C, 0x055C0303, + 0x81C, 0x045E0303, + 0x81C, 0x03600303, + 0x81C, 0x02620303, + 0x81C, 0x01640303, + 0x81C, 0x00660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xF7000303, 0x81C, 0xF6020303, 0x81C, 0xF5040303, @@ -1886,23 +3563,88 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0303, 0x81C, 0x007C0303, 0x81C, 0x007E0303, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000303, - 0x81C, 0xF6020303, - 0x81C, 0xF5040303, - 0x81C, 0xF4060303, - 0x81C, 0xF3080303, - 0x81C, 0xF20A0303, - 0x81C, 0xF10C0303, - 0x81C, 0xF00E0303, - 0x81C, 0xEF100303, - 0x81C, 0xEE120303, - 0x81C, 0xED140303, - 0x81C, 0xEC160303, - 0x81C, 0xEB180303, - 0x81C, 0xEA1A0303, - 0x81C, 0xE91C0303, - 0x81C, 0xCA1E0303, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000303, + 0x81C, 0xFA020303, + 0x81C, 0xF9040303, + 0x81C, 0xF8060303, + 0x81C, 0xF7080303, + 0x81C, 0xF60A0303, + 0x81C, 0xF50C0303, + 0x81C, 0xF40E0303, + 0x81C, 0xF3100303, + 0x81C, 0xF2120303, + 0x81C, 0xF1140303, + 0x81C, 0xF0160303, + 0x81C, 0xEF180303, + 0x81C, 0xEE1A0303, + 0x81C, 0xED1C0303, + 0x81C, 0xEC1E0303, + 0x81C, 0xEB200303, + 0x81C, 0xEA220303, + 0x81C, 0xE9240303, + 0x81C, 0xE8260303, + 0x81C, 0xE7280303, + 0x81C, 0xE62A0303, + 0x81C, 0xE52C0303, + 0x81C, 0xE42E0303, + 0x81C, 0xE3300303, + 0x81C, 0xE2320303, + 0x81C, 0xE1340303, + 0x81C, 0xC5360303, + 0x81C, 0xC4380303, + 0x81C, 0xC33A0303, + 0x81C, 0xC23C0303, + 0x81C, 0xC13E0303, + 0x81C, 0xA4400303, + 0x81C, 0xA3420303, + 0x81C, 0xA2440303, + 0x81C, 0xA1460303, + 0x81C, 0x83480303, + 0x81C, 0x824A0303, + 0x81C, 0x814C0303, + 0x81C, 0x804E0303, + 0x81C, 0x64500303, + 0x81C, 0x63520303, + 0x81C, 0x62540303, + 0x81C, 0x61560303, + 0x81C, 0x60580303, + 0x81C, 0x235A0303, + 0x81C, 0x225C0303, + 0x81C, 0x215E0303, + 0x81C, 0x20600303, + 0x81C, 0x04620303, + 0x81C, 0x03640303, + 0x81C, 0x02660303, + 0x81C, 0x01680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF9000303, + 0x81C, 0xF8020303, + 0x81C, 0xF7040303, + 0x81C, 0xF6060303, + 0x81C, 0xF5080303, + 0x81C, 0xF40A0303, + 0x81C, 0xF30C0303, + 0x81C, 0xF20E0303, + 0x81C, 0xF1100303, + 0x81C, 0xF0120303, + 0x81C, 0xEF140303, + 0x81C, 0xEE160303, + 0x81C, 0xED180303, + 0x81C, 0xEC1A0303, + 0x81C, 0xEB1C0303, + 0x81C, 0xEA1E0303, 0x81C, 0xC9200303, 0x81C, 0xC8220303, 0x81C, 0xC7240303, @@ -1912,7 +3654,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0xC32C0303, 0x81C, 0xC22E0303, 0x81C, 0xC1300303, - 0x81C, 0xA4320303, + 0x81C, 0xC0320303, 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303, @@ -1951,33 +3693,293 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0303, 0x81C, 0x007C0303, 0x81C, 0x007E0303, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xF7000303, - 0x81C, 0xF6020303, - 0x81C, 0xF5040303, - 0x81C, 0xF4060303, - 0x81C, 0xF3080303, - 0x81C, 0xF20A0303, - 0x81C, 0xF10C0303, - 0x81C, 0xF00E0303, - 0x81C, 0xEF100303, - 0x81C, 0xEE120303, - 0x81C, 0xED140303, - 0x81C, 0xEC160303, - 0x81C, 0xEB180303, - 0x81C, 0xEA1A0303, - 0x81C, 0xE91C0303, - 0x81C, 0xCA1E0303, - 0x81C, 0xC9200303, - 0x81C, 0xC8220303, - 0x81C, 0xC7240303, - 0x81C, 0xC6260303, - 0x81C, 0xC5280303, - 0x81C, 0xC42A0303, - 0x81C, 0xC32C0303, - 0x81C, 0xC22E0303, - 0x81C, 0xC1300303, - 0x81C, 0xA4320303, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000303, + 0x81C, 0xF7020303, + 0x81C, 0xF6040303, + 0x81C, 0xF5060303, + 0x81C, 0xF4080303, + 0x81C, 0xF30A0303, + 0x81C, 0xF20C0303, + 0x81C, 0xF10E0303, + 0x81C, 0xF0100303, + 0x81C, 0xEF120303, + 0x81C, 0xEE140303, + 0x81C, 0xED160303, + 0x81C, 0xEC180303, + 0x81C, 0xEB1A0303, + 0x81C, 0xEA1C0303, + 0x81C, 0xE91E0303, + 0x81C, 0xCA200303, + 0x81C, 0xC9220303, + 0x81C, 0xC8240303, + 0x81C, 0xC7260303, + 0x81C, 0xC6280303, + 0x81C, 0xC52A0303, + 0x81C, 0xC42C0303, + 0x81C, 0xC32E0303, + 0x81C, 0xC2300303, + 0x81C, 0xC1320303, + 0x81C, 0xA3340303, + 0x81C, 0xA2360303, + 0x81C, 0xA1380303, + 0x81C, 0xA03A0303, + 0x81C, 0x823C0303, + 0x81C, 0x813E0303, + 0x81C, 0x80400303, + 0x81C, 0x65420303, + 0x81C, 0x64440303, + 0x81C, 0x63460303, + 0x81C, 0x62480303, + 0x81C, 0x614A0303, + 0x81C, 0x424C0303, + 0x81C, 0x414E0303, + 0x81C, 0x40500303, + 0x81C, 0x22520303, + 0x81C, 0x21540303, + 0x81C, 0x20560303, + 0x81C, 0x04580303, + 0x81C, 0x035A0303, + 0x81C, 0x025C0303, + 0x81C, 0x015E0303, + 0x81C, 0x00600303, + 0x81C, 0x00620303, + 0x81C, 0x00640303, + 0x81C, 0x00660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000303, + 0x81C, 0xFA020303, + 0x81C, 0xF9040303, + 0x81C, 0xF8060303, + 0x81C, 0xF7080303, + 0x81C, 0xF60A0303, + 0x81C, 0xF50C0303, + 0x81C, 0xF40E0303, + 0x81C, 0xF3100303, + 0x81C, 0xF2120303, + 0x81C, 0xF1140303, + 0x81C, 0xF0160303, + 0x81C, 0xEF180303, + 0x81C, 0xEE1A0303, + 0x81C, 0xED1C0303, + 0x81C, 0xEC1E0303, + 0x81C, 0xEB200303, + 0x81C, 0xEA220303, + 0x81C, 0xE9240303, + 0x81C, 0xE8260303, + 0x81C, 0xE7280303, + 0x81C, 0xE62A0303, + 0x81C, 0xE52C0303, + 0x81C, 0xE42E0303, + 0x81C, 0xE3300303, + 0x81C, 0xE2320303, + 0x81C, 0xC6340303, + 0x81C, 0xC5360303, + 0x81C, 0xC4380303, + 0x81C, 0xC33A0303, + 0x81C, 0xC23C0303, + 0x81C, 0xC13E0303, + 0x81C, 0xA4400303, + 0x81C, 0xA3420303, + 0x81C, 0xA2440303, + 0x81C, 0xA1460303, + 0x81C, 0x83480303, + 0x81C, 0x824A0303, + 0x81C, 0x814C0303, + 0x81C, 0x804E0303, + 0x81C, 0x63500303, + 0x81C, 0x62520303, + 0x81C, 0x43540303, + 0x81C, 0x42560303, + 0x81C, 0x41580303, + 0x81C, 0x235A0303, + 0x81C, 0x225C0303, + 0x81C, 0x215E0303, + 0x81C, 0x20600303, + 0x81C, 0x04620303, + 0x81C, 0x03640303, + 0x81C, 0x02660303, + 0x81C, 0x01680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000303, + 0x81C, 0xF7020303, + 0x81C, 0xF6040303, + 0x81C, 0xF5060303, + 0x81C, 0xF4080303, + 0x81C, 0xF30A0303, + 0x81C, 0xF20C0303, + 0x81C, 0xF10E0303, + 0x81C, 0xF0100303, + 0x81C, 0xEF120303, + 0x81C, 0xEE140303, + 0x81C, 0xED160303, + 0x81C, 0xEC180303, + 0x81C, 0xEB1A0303, + 0x81C, 0xEA1C0303, + 0x81C, 0xE91E0303, + 0x81C, 0xCA200303, + 0x81C, 0xC9220303, + 0x81C, 0xC8240303, + 0x81C, 0xC7260303, + 0x81C, 0xC6280303, + 0x81C, 0xC52A0303, + 0x81C, 0xC42C0303, + 0x81C, 0xC32E0303, + 0x81C, 0xC2300303, + 0x81C, 0xC1320303, + 0x81C, 0xA3340303, + 0x81C, 0xA2360303, + 0x81C, 0xA1380303, + 0x81C, 0xA03A0303, + 0x81C, 0x823C0303, + 0x81C, 0x813E0303, + 0x81C, 0x80400303, + 0x81C, 0x65420303, + 0x81C, 0x64440303, + 0x81C, 0x63460303, + 0x81C, 0x62480303, + 0x81C, 0x614A0303, + 0x81C, 0x424C0303, + 0x81C, 0x414E0303, + 0x81C, 0x40500303, + 0x81C, 0x22520303, + 0x81C, 0x21540303, + 0x81C, 0x20560303, + 0x81C, 0x04580303, + 0x81C, 0x035A0303, + 0x81C, 0x025C0303, + 0x81C, 0x015E0303, + 0x81C, 0x00600303, + 0x81C, 0x00620303, + 0x81C, 0x00640303, + 0x81C, 0x00660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x9000000a, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000303, + 0x81C, 0xFB020303, + 0x81C, 0xFA040303, + 0x81C, 0xF9060303, + 0x81C, 0xF8080303, + 0x81C, 0xF70A0303, + 0x81C, 0xF60C0303, + 0x81C, 0xF50E0303, + 0x81C, 0xF4100303, + 0x81C, 0xF3120303, + 0x81C, 0xF2140303, + 0x81C, 0xF1160303, + 0x81C, 0xEF180303, + 0x81C, 0xEE1A0303, + 0x81C, 0xED1C0303, + 0x81C, 0xEC1E0303, + 0x81C, 0xEB200303, + 0x81C, 0xEA220303, + 0x81C, 0xE9240303, + 0x81C, 0xE8260303, + 0x81C, 0xE7280303, + 0x81C, 0xE62A0303, + 0x81C, 0xE52C0303, + 0x81C, 0xE42E0303, + 0x81C, 0xE3300303, + 0x81C, 0xE2320303, + 0x81C, 0xC6340303, + 0x81C, 0xC5360303, + 0x81C, 0xC4380303, + 0x81C, 0xC33A0303, + 0x81C, 0xA63C0303, + 0x81C, 0xA53E0303, + 0x81C, 0xA4400303, + 0x81C, 0xA3420303, + 0x81C, 0xA2440303, + 0x81C, 0xA1460303, + 0x81C, 0x83480303, + 0x81C, 0x824A0303, + 0x81C, 0x814C0303, + 0x81C, 0x804E0303, + 0x81C, 0x63500303, + 0x81C, 0x62520303, + 0x81C, 0x61540303, + 0x81C, 0x42560303, + 0x81C, 0x41580303, + 0x81C, 0x405A0303, + 0x81C, 0x225C0303, + 0x81C, 0x215E0303, + 0x81C, 0x20600303, + 0x81C, 0x04620303, + 0x81C, 0x03640303, + 0x81C, 0x02660303, + 0x81C, 0x01680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x9000000b, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000303, + 0x81C, 0xF7020303, + 0x81C, 0xF6040303, + 0x81C, 0xF5060303, + 0x81C, 0xF4080303, + 0x81C, 0xF30A0303, + 0x81C, 0xF20C0303, + 0x81C, 0xF10E0303, + 0x81C, 0xF0100303, + 0x81C, 0xEF120303, + 0x81C, 0xEE140303, + 0x81C, 0xED160303, + 0x81C, 0xEC180303, + 0x81C, 0xEB1A0303, + 0x81C, 0xEA1C0303, + 0x81C, 0xE91E0303, + 0x81C, 0xCA200303, + 0x81C, 0xC9220303, + 0x81C, 0xC8240303, + 0x81C, 0xC7260303, + 0x81C, 0xC6280303, + 0x81C, 0xC52A0303, + 0x81C, 0xC42C0303, + 0x81C, 0xC32E0303, + 0x81C, 0xC2300303, + 0x81C, 0xC1320303, 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303, @@ -1990,16 +3992,16 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x62460303, 0x81C, 0x61480303, 0x81C, 0x604A0303, - 0x81C, 0x414C0303, - 0x81C, 0x404E0303, - 0x81C, 0x22500303, - 0x81C, 0x21520303, - 0x81C, 0x20540303, - 0x81C, 0x03560303, - 0x81C, 0x02580303, - 0x81C, 0x015A0303, - 0x81C, 0x005C0303, - 0x81C, 0x005E0303, + 0x81C, 0x234C0303, + 0x81C, 0x224E0303, + 0x81C, 0x21500303, + 0x81C, 0x20520303, + 0x81C, 0x06540303, + 0x81C, 0x05560303, + 0x81C, 0x04580303, + 0x81C, 0x035A0303, + 0x81C, 0x025C0303, + 0x81C, 0x015E0303, 0x81C, 0x00600303, 0x81C, 0x00620303, 0x81C, 0x00640303, @@ -2016,7 +4018,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0303, 0x81C, 0x007C0303, 0x81C, 0x007E0303, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x9000000c, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFC000303, 0x81C, 0xFB020303, 0x81C, 0xFA040303, @@ -2029,47 +4031,47 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0xF3120303, 0x81C, 0xF2140303, 0x81C, 0xF1160303, - 0x81C, 0xF0180303, - 0x81C, 0xEF1A0303, - 0x81C, 0xEE1C0303, - 0x81C, 0xED1E0303, - 0x81C, 0xEC200303, - 0x81C, 0xEB220303, - 0x81C, 0xEA240303, - 0x81C, 0xE9260303, - 0x81C, 0xE8280303, - 0x81C, 0xE72A0303, - 0x81C, 0xE62C0303, - 0x81C, 0xE52E0303, - 0x81C, 0xE4300303, - 0x81C, 0xE3320303, - 0x81C, 0xE2340303, - 0x81C, 0xC6360303, - 0x81C, 0xC5380303, - 0x81C, 0xC43A0303, - 0x81C, 0xC33C0303, - 0x81C, 0xA63E0303, - 0x81C, 0xA5400303, - 0x81C, 0xA4420303, - 0x81C, 0xA3440303, - 0x81C, 0xA2460303, - 0x81C, 0x84480303, - 0x81C, 0x834A0303, - 0x81C, 0x824C0303, - 0x81C, 0x814E0303, - 0x81C, 0x80500303, - 0x81C, 0x63520303, - 0x81C, 0x62540303, - 0x81C, 0x61560303, - 0x81C, 0x60580303, - 0x81C, 0x225A0303, - 0x81C, 0x055C0303, - 0x81C, 0x045E0303, - 0x81C, 0x03600303, - 0x81C, 0x02620303, - 0x81C, 0x01640303, - 0x81C, 0x00660303, - 0x81C, 0x00680303, + 0x81C, 0xEF180303, + 0x81C, 0xEE1A0303, + 0x81C, 0xED1C0303, + 0x81C, 0xEC1E0303, + 0x81C, 0xEB200303, + 0x81C, 0xEA220303, + 0x81C, 0xE9240303, + 0x81C, 0xE8260303, + 0x81C, 0xE7280303, + 0x81C, 0xE62A0303, + 0x81C, 0xE52C0303, + 0x81C, 0xE42E0303, + 0x81C, 0xE3300303, + 0x81C, 0xE2320303, + 0x81C, 0xC6340303, + 0x81C, 0xC5360303, + 0x81C, 0xC4380303, + 0x81C, 0xC33A0303, + 0x81C, 0xA63C0303, + 0x81C, 0xA53E0303, + 0x81C, 0xA4400303, + 0x81C, 0xA3420303, + 0x81C, 0xA2440303, + 0x81C, 0xA1460303, + 0x81C, 0x83480303, + 0x81C, 0x824A0303, + 0x81C, 0x814C0303, + 0x81C, 0x804E0303, + 0x81C, 0x63500303, + 0x81C, 0x62520303, + 0x81C, 0x61540303, + 0x81C, 0x42560303, + 0x81C, 0x41580303, + 0x81C, 0x405A0303, + 0x81C, 0x225C0303, + 0x81C, 0x215E0303, + 0x81C, 0x20600303, + 0x81C, 0x04620303, + 0x81C, 0x03640303, + 0x81C, 0x02660303, + 0x81C, 0x01680303, 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303, @@ -2081,60 +4083,125 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0303, 0x81C, 0x007C0303, 0x81C, 0x007E0303, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFC000303, - 0x81C, 0xFB020303, - 0x81C, 0xFA040303, - 0x81C, 0xF9060303, - 0x81C, 0xF8080303, - 0x81C, 0xF70A0303, - 0x81C, 0xF60C0303, - 0x81C, 0xF50E0303, - 0x81C, 0xF4100303, - 0x81C, 0xF3120303, - 0x81C, 0xF2140303, - 0x81C, 0xF1160303, - 0x81C, 0xF0180303, - 0x81C, 0xEF1A0303, - 0x81C, 0xEE1C0303, - 0x81C, 0xED1E0303, - 0x81C, 0xEC200303, - 0x81C, 0xEB220303, - 0x81C, 0xEA240303, - 0x81C, 0xE9260303, - 0x81C, 0xE8280303, - 0x81C, 0xE72A0303, - 0x81C, 0xE62C0303, - 0x81C, 0xE52E0303, - 0x81C, 0xE4300303, - 0x81C, 0xE3320303, - 0x81C, 0xE2340303, - 0x81C, 0xC6360303, - 0x81C, 0xC5380303, - 0x81C, 0xC43A0303, - 0x81C, 0xC33C0303, - 0x81C, 0xA63E0303, - 0x81C, 0xA5400303, - 0x81C, 0xA4420303, - 0x81C, 0xA3440303, - 0x81C, 0xA2460303, - 0x81C, 0x84480303, - 0x81C, 0x834A0303, - 0x81C, 0x824C0303, - 0x81C, 0x814E0303, - 0x81C, 0x80500303, - 0x81C, 0x63520303, - 0x81C, 0x62540303, - 0x81C, 0x61560303, - 0x81C, 0x60580303, - 0x81C, 0x225A0303, - 0x81C, 0x055C0303, - 0x81C, 0x045E0303, - 0x81C, 0x03600303, - 0x81C, 0x02620303, - 0x81C, 0x01640303, - 0x81C, 0x00660303, - 0x81C, 0x00680303, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000303, + 0x81C, 0xFA020303, + 0x81C, 0xF9040303, + 0x81C, 0xF8060303, + 0x81C, 0xF7080303, + 0x81C, 0xF60A0303, + 0x81C, 0xF50C0303, + 0x81C, 0xF40E0303, + 0x81C, 0xF3100303, + 0x81C, 0xF2120303, + 0x81C, 0xF1140303, + 0x81C, 0xEF160303, + 0x81C, 0xEE180303, + 0x81C, 0xED1A0303, + 0x81C, 0xEC1C0303, + 0x81C, 0xEB1E0303, + 0x81C, 0xEA200303, + 0x81C, 0xE9220303, + 0x81C, 0xE8240303, + 0x81C, 0xE7260303, + 0x81C, 0xE6280303, + 0x81C, 0xE52A0303, + 0x81C, 0xE42C0303, + 0x81C, 0xE32E0303, + 0x81C, 0xE2300303, + 0x81C, 0xE1320303, + 0x81C, 0xC6340303, + 0x81C, 0xC5360303, + 0x81C, 0xC4380303, + 0x81C, 0xC33A0303, + 0x81C, 0xA63C0303, + 0x81C, 0xA53E0303, + 0x81C, 0xA4400303, + 0x81C, 0xA3420303, + 0x81C, 0xA2440303, + 0x81C, 0xA1460303, + 0x81C, 0x83480303, + 0x81C, 0x824A0303, + 0x81C, 0x814C0303, + 0x81C, 0x804E0303, + 0x81C, 0x63500303, + 0x81C, 0x62520303, + 0x81C, 0x61540303, + 0x81C, 0x42560303, + 0x81C, 0x41580303, + 0x81C, 0x405A0303, + 0x81C, 0x225C0303, + 0x81C, 0x215E0303, + 0x81C, 0x20600303, + 0x81C, 0x04620303, + 0x81C, 0x03640303, + 0x81C, 0x02660303, + 0x81C, 0x01680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000303, + 0x81C, 0xFA020303, + 0x81C, 0xF9040303, + 0x81C, 0xF8060303, + 0x81C, 0xF7080303, + 0x81C, 0xF60A0303, + 0x81C, 0xF50C0303, + 0x81C, 0xF40E0303, + 0x81C, 0xF3100303, + 0x81C, 0xF2120303, + 0x81C, 0xF1140303, + 0x81C, 0xEF160303, + 0x81C, 0xEE180303, + 0x81C, 0xED1A0303, + 0x81C, 0xEC1C0303, + 0x81C, 0xEB1E0303, + 0x81C, 0xEA200303, + 0x81C, 0xE9220303, + 0x81C, 0xE8240303, + 0x81C, 0xE7260303, + 0x81C, 0xE6280303, + 0x81C, 0xE52A0303, + 0x81C, 0xE42C0303, + 0x81C, 0xE32E0303, + 0x81C, 0xE2300303, + 0x81C, 0xE1320303, + 0x81C, 0xC6340303, + 0x81C, 0xC5360303, + 0x81C, 0xC4380303, + 0x81C, 0xC33A0303, + 0x81C, 0xA63C0303, + 0x81C, 0xA53E0303, + 0x81C, 0xA4400303, + 0x81C, 0xA3420303, + 0x81C, 0xA2440303, + 0x81C, 0xA1460303, + 0x81C, 0x83480303, + 0x81C, 0x824A0303, + 0x81C, 0x814C0303, + 0x81C, 0x804E0303, + 0x81C, 0x63500303, + 0x81C, 0x62520303, + 0x81C, 0x61540303, + 0x81C, 0x42560303, + 0x81C, 0x41580303, + 0x81C, 0x405A0303, + 0x81C, 0x225C0303, + 0x81C, 0x215E0303, + 0x81C, 0x20600303, + 0x81C, 0x04620303, + 0x81C, 0x03640303, + 0x81C, 0x02660303, + 0x81C, 0x01680303, 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303, @@ -2192,13 +4259,13 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x62540303, 0x81C, 0x61560303, 0x81C, 0x60580303, - 0x81C, 0x225A0303, - 0x81C, 0x055C0303, - 0x81C, 0x045E0303, - 0x81C, 0x03600303, - 0x81C, 0x02620303, - 0x81C, 0x01640303, - 0x81C, 0x00660303, + 0x81C, 0x235A0303, + 0x81C, 0x225C0303, + 0x81C, 0x215E0303, + 0x81C, 0x20600303, + 0x81C, 0x03620303, + 0x81C, 0x02640303, + 0x81C, 0x01660303, 0x81C, 0x00680303, 0x81C, 0x006A0303, 0x81C, 0x006C0303, @@ -2212,7 +4279,403 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xF5000403, + 0x81C, 0xF4020403, + 0x81C, 0xF3040403, + 0x81C, 0xF2060403, + 0x81C, 0xF1080403, + 0x81C, 0xF00A0403, + 0x81C, 0xEF0C0403, + 0x81C, 0xEE0E0403, + 0x81C, 0xED100403, + 0x81C, 0xEC120403, + 0x81C, 0xEB140403, + 0x81C, 0xEA160403, + 0x81C, 0xE9180403, + 0x81C, 0xE81A0403, + 0x81C, 0xE71C0403, + 0x81C, 0xE61E0403, + 0x81C, 0xE5200403, + 0x81C, 0xE4220403, + 0x81C, 0xE3240403, + 0x81C, 0xE2260403, + 0x81C, 0xE1280403, + 0x81C, 0xE02A0403, + 0x81C, 0xC32C0403, + 0x81C, 0xC22E0403, + 0x81C, 0xC1300403, + 0x81C, 0xC0320403, + 0x81C, 0xA4340403, + 0x81C, 0xA3360403, + 0x81C, 0xA2380403, + 0x81C, 0xA13A0403, + 0x81C, 0xA03C0403, + 0x81C, 0x823E0403, + 0x81C, 0x81400403, + 0x81C, 0x80420403, + 0x81C, 0x64440403, + 0x81C, 0x63460403, + 0x81C, 0x62480403, + 0x81C, 0x614A0403, + 0x81C, 0x604C0403, + 0x81C, 0x454E0403, + 0x81C, 0x44500403, + 0x81C, 0x43520403, + 0x81C, 0x42540403, + 0x81C, 0x41560403, + 0x81C, 0x40580403, + 0x81C, 0x055A0403, + 0x81C, 0x045C0403, + 0x81C, 0x035E0403, + 0x81C, 0x02600403, + 0x81C, 0x01620403, + 0x81C, 0x00640403, + 0x81C, 0x00660403, + 0x81C, 0x00680403, + 0x81C, 0x006A0403, + 0x81C, 0x006C0403, + 0x81C, 0x006E0403, + 0x81C, 0x00700403, + 0x81C, 0x00720403, + 0x81C, 0x00740403, + 0x81C, 0x00760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xF6000403, + 0x81C, 0xF5020403, + 0x81C, 0xF4040403, + 0x81C, 0xF3060403, + 0x81C, 0xF2080403, + 0x81C, 0xF10A0403, + 0x81C, 0xF00C0403, + 0x81C, 0xEF0E0403, + 0x81C, 0xD6100403, + 0x81C, 0xD5120403, + 0x81C, 0xD4140403, + 0x81C, 0xD3160403, + 0x81C, 0xD2180403, + 0x81C, 0xD11A0403, + 0x81C, 0xD01C0403, + 0x81C, 0xCF1E0403, + 0x81C, 0x95200403, + 0x81C, 0x94220403, + 0x81C, 0x93240403, + 0x81C, 0x92260403, + 0x81C, 0x91280403, + 0x81C, 0x902A0403, + 0x81C, 0x8F2C0403, + 0x81C, 0x8E2E0403, + 0x81C, 0x8D300403, + 0x81C, 0x8C320403, + 0x81C, 0x8B340403, + 0x81C, 0x8A360403, + 0x81C, 0x89380403, + 0x81C, 0x883A0403, + 0x81C, 0x873C0403, + 0x81C, 0x863E0403, + 0x81C, 0x68400403, + 0x81C, 0x67420403, + 0x81C, 0x66440403, + 0x81C, 0x65460403, + 0x81C, 0x64480403, + 0x81C, 0x634A0403, + 0x81C, 0x484C0403, + 0x81C, 0x474E0403, + 0x81C, 0x46500403, + 0x81C, 0x45520403, + 0x81C, 0x44540403, + 0x81C, 0x27560403, + 0x81C, 0x26580403, + 0x81C, 0x255A0403, + 0x81C, 0x245C0403, + 0x81C, 0x235E0403, + 0x81C, 0x04600403, + 0x81C, 0x03620403, + 0x81C, 0x02640403, + 0x81C, 0x01660403, + 0x81C, 0x00680403, + 0x81C, 0x006A0403, + 0x81C, 0x006C0403, + 0x81C, 0x006E0403, + 0x81C, 0x00700403, + 0x81C, 0x00720403, + 0x81C, 0x00740403, + 0x81C, 0x00760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xF5000403, 0x81C, 0xF4020403, @@ -2278,7 +4741,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xF5000403, 0x81C, 0xF4020403, @@ -2344,7 +4807,73 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x90000008, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000009, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xF5000403, 0x81C, 0xF4020403, @@ -2410,7 +4939,73 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x9000000a, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x9000000b, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xF5000403, 0x81C, 0xF4020403, @@ -2476,7 +5071,7 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x9000000c, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xFF000403, 0x81C, 0xFF020403, @@ -2493,10 +5088,10 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0xF4180403, 0x81C, 0xF31A0403, 0x81C, 0xF21C0403, - 0x81C, 0xD91E0403, - 0x81C, 0xD8200403, - 0x81C, 0xD7220403, - 0x81C, 0xD6240403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, 0x81C, 0xB6260403, 0x81C, 0xB5280403, 0x81C, 0xB42A0403, @@ -2523,26 +5118,26 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x82540403, 0x81C, 0x81560403, 0x81C, 0x80580403, - 0x81C, 0x465A0403, - 0x81C, 0x455C0403, - 0x81C, 0x445E0403, - 0x81C, 0x43600403, - 0x81C, 0x42620403, - 0x81C, 0x07640403, - 0x81C, 0x06660403, - 0x81C, 0x05680403, - 0x81C, 0x046A0403, - 0x81C, 0x036C0403, - 0x81C, 0x026E0403, - 0x81C, 0x01700403, - 0x81C, 0x00720403, - 0x81C, 0x00740403, - 0x81C, 0x00760403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, 0x81C, 0x00780403, 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xFF000403, 0x81C, 0xFF020403, @@ -2559,10 +5154,10 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0xF4180403, 0x81C, 0xF31A0403, 0x81C, 0xF21C0403, - 0x81C, 0xD91E0403, - 0x81C, 0xD8200403, - 0x81C, 0xD7220403, - 0x81C, 0xD6240403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, 0x81C, 0xB6260403, 0x81C, 0xB5280403, 0x81C, 0xB42A0403, @@ -2589,26 +5184,26 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x82540403, 0x81C, 0x81560403, 0x81C, 0x80580403, - 0x81C, 0x465A0403, - 0x81C, 0x455C0403, - 0x81C, 0x445E0403, - 0x81C, 0x43600403, - 0x81C, 0x42620403, - 0x81C, 0x07640403, - 0x81C, 0x06660403, - 0x81C, 0x05680403, - 0x81C, 0x046A0403, - 0x81C, 0x036C0403, - 0x81C, 0x026E0403, - 0x81C, 0x01700403, - 0x81C, 0x00720403, - 0x81C, 0x00740403, - 0x81C, 0x00760403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, 0x81C, 0x00780403, 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xFF000403, 0x81C, 0xFF020403, @@ -2625,10 +5220,10 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0xF4180403, 0x81C, 0xF31A0403, 0x81C, 0xF21C0403, - 0x81C, 0xD91E0403, - 0x81C, 0xD8200403, - 0x81C, 0xD7220403, - 0x81C, 0xD6240403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, 0x81C, 0xB6260403, 0x81C, 0xB5280403, 0x81C, 0xB42A0403, @@ -2655,21 +5250,21 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x82540403, 0x81C, 0x81560403, 0x81C, 0x80580403, - 0x81C, 0x465A0403, - 0x81C, 0x455C0403, - 0x81C, 0x445E0403, - 0x81C, 0x43600403, - 0x81C, 0x42620403, - 0x81C, 0x07640403, - 0x81C, 0x06660403, - 0x81C, 0x05680403, - 0x81C, 0x046A0403, - 0x81C, 0x036C0403, - 0x81C, 0x026E0403, - 0x81C, 0x01700403, - 0x81C, 0x00720403, - 0x81C, 0x00740403, - 0x81C, 0x00760403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, 0x81C, 0x00780403, 0x81C, 0x007A0403, 0x81C, 0x007C0403, @@ -2691,10 +5286,10 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0xF4180403, 0x81C, 0xF31A0403, 0x81C, 0xF21C0403, - 0x81C, 0xD91E0403, - 0x81C, 0xD8200403, - 0x81C, 0xD7220403, - 0x81C, 0xD6240403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, 0x81C, 0xB6260403, 0x81C, 0xB5280403, 0x81C, 0xB42A0403, @@ -2721,103 +5316,120 @@ u4Byte Array_MP_8822B_AGC_TAB[] = { 0x81C, 0x82540403, 0x81C, 0x81560403, 0x81C, 0x80580403, - 0x81C, 0x465A0403, - 0x81C, 0x455C0403, - 0x81C, 0x445E0403, - 0x81C, 0x43600403, - 0x81C, 0x42620403, - 0x81C, 0x07640403, - 0x81C, 0x06660403, - 0x81C, 0x05680403, - 0x81C, 0x046A0403, - 0x81C, 0x036C0403, - 0x81C, 0x026E0403, - 0x81C, 0x01700403, - 0x81C, 0x00720403, - 0x81C, 0x00740403, - 0x81C, 0x00760403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, 0x81C, 0x00780403, 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403, 0xB0000000, 0x00000000, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + 0xA0000000, 0x00000000, 0xC50, 0x00000022, 0xC50, 0x00000020, 0xE50, 0x00000022, 0xE50, 0x00000020, + 0xB0000000, 0x00000000, }; void -ODM_ReadAndConfig_MP_8822B_AGC_TAB( - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_agc_tab( + struct PHY_DM_STRUCT *p_dm_odm ) { - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8822B_AGC_TAB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_AGC_TAB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8822b_agc_tab)/sizeof(u32); + u32 *array = array_mp_8822b_agc_tab; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_AGC_TAB\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_agc_tab\n")); - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped?false:true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; } else { - bMatched = FALSE; - bSkipped = FALSE; + is_matched = false; + is_skipped = false; } } else - bMatched = FALSE; + is_matched = false; } } else { - if (bMatched) - odm_ConfigBB_AGC_8822B(pDM_Odm, v1, bMaskDWord, v2); + if (is_matched) + odm_config_bb_agc_8822b(p_dm_odm, v1, MASKDWORD, v2); } i = i + 2; } } -u4Byte -ODM_GetVersion_MP_8822B_AGC_TAB(void) +u32 +odm_get_version_mp_8822b_agc_tab(void) { - return 50; + return 85; } /****************************************************************************** -* PHY_REG.TXT +* phy_reg.TXT ******************************************************************************/ -u4Byte Array_MP_8822B_PHY_REG[] = { +u32 array_mp_8822b_phy_reg[] = { 0x800, 0x9020D010, 0x804, 0x800181A0, 0x808, 0x0E028233, 0x80C, 0x10000013, - 0x810, 0x21101263, + 0x810, 0x21101243, 0x814, 0x020C3D10, 0x818, 0x84A10385, 0x81C, 0x1E1E081F, @@ -2828,20 +5440,20 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0x830, 0x79A0EA2A, 0x834, 0x072E6986, 0x838, 0x87766441, - 0x83C, 0x9194B2B6, - 0x840, 0x171740E0, - 0x844, 0x4D3D7CDB, + 0x83C, 0x9194B2B7, + 0x840, 0x171750E0, + 0x844, 0x4C3D7CDB, 0x848, 0x4AD0408B, 0x84C, 0x6AFBF7A5, 0x850, 0x28A74706, 0x854, 0x0001520C, 0x858, 0x4060C000, - 0x85C, 0x74010360, + 0x85C, 0x74010160, 0x860, 0x68A7C321, 0x864, 0x79F27432, 0x868, 0x8CA7A314, - 0x86C, 0xAA8C2878, - 0x870, 0xAAAAAAAA, + 0x86C, 0x778C2878, + 0x870, 0x77777777, 0x874, 0x27612C2E, 0x878, 0xC0003152, 0x87C, 0x5C8FC000, @@ -2864,13 +5476,13 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0x8C0, 0xFFE04020, 0x8C4, 0x47C00000, 0x8C8, 0x000251A5, - 0x8CC, 0x08108000, + 0x8CC, 0x08108492, 0x8D0, 0x0000B800, 0x8D4, 0x860308A0, - 0x8D8, 0x210B5612, + 0x8D8, 0x29095612, 0x8DC, 0x00000000, 0x8E0, 0x32D16777, - 0x8E4, 0x4909292D, + 0x8E4, 0x4C098935, 0x8E8, 0xFFFFC42C, 0x8EC, 0x99999999, 0x8F0, 0x00009999, @@ -2886,7 +5498,7 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0x918, 0x1C1028C0, 0x91C, 0x64B11A1C, 0x920, 0xE0767233, - 0x924, 0x055A2500, + 0x924, 0x855A2500, 0x928, 0x4AB0E4E4, 0x92C, 0xFFFEB200, 0x930, 0xFFFFFFFE, @@ -2912,7 +5524,7 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0x980, 0x00000000, 0x984, 0x00000000, 0x988, 0x00000000, - 0x98C, 0x23440000, + 0x98C, 0x43440000, 0x990, 0x27100000, 0x994, 0xFFFF0100, 0x998, 0xFFFFFF5C, @@ -2966,7 +5578,7 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0xA98, 0x030A0000, 0xA9C, 0x00060000, 0xAA0, 0x00000000, - 0xAA4, 0x00040018, + 0xAA4, 0x0004000F, 0xAA8, 0x00000200, 0xB00, 0xE1000440, 0xB04, 0x00800000, @@ -3005,7 +5617,7 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0xB88, 0x00000000, 0xB8C, 0x00000000, 0xC00, 0x00000007, - 0xC04, 0x00000020, + 0xC04, 0x00240020, 0xC08, 0x60403231, 0xC0C, 0x00012345, 0xC10, 0x00000100, @@ -3062,7 +5674,7 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0xCE8, 0x00000000, 0xCEC, 0x00000000, 0xE00, 0x00000007, - 0xE04, 0x00000020, + 0xE04, 0x00240020, 0xE08, 0x60403231, 0xE0C, 0x00012345, 0xE10, 0x00000100, @@ -3214,18 +5826,18 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0x1C74, 0x01000000, 0x1C78, 0x00000000, 0x1C7C, 0x00000010, - 0x1C80, 0x00000100, - 0x1C84, 0x01000000, - 0x1C88, 0x00000100, - 0x1C8C, 0x01000000, - 0x1C90, 0x00000100, - 0x1C94, 0x01000000, - 0x1C98, 0x00000100, - 0x1C9C, 0x01000000, + 0x1C80, 0x5FFF5FFF, + 0x1C84, 0x5FFF5FFF, + 0x1C88, 0x5FFF5FFF, + 0x1C8C, 0x5FFF5FFF, + 0x1C90, 0x5FFF5FFF, + 0x1C94, 0x5FFF5FFF, + 0x1C98, 0x5FFF5FFF, + 0x1C9C, 0x5FFF5FFF, 0x1CA0, 0x00000100, 0x1CA4, 0x01000000, 0x1CA8, 0x00000100, - 0x1CAC, 0x01000000, + 0x1CAC, 0x5FFF5FFF, 0x1CB0, 0x00000100, 0x1CB4, 0x01000000, 0x1CB8, 0x00000000, @@ -3305,7 +5917,7 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0x1B04, 0xE24629D2, 0x1B08, 0x00000080, 0x1B0C, 0x00000000, - 0x1B10, 0x00010C00, + 0x1B10, 0x00011C00, 0x1B14, 0x00000000, 0x1B18, 0x00292903, 0x1B1C, 0xA2193C32, @@ -3317,7 +5929,7 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0x1B34, 0x00000800, 0x1B3C, 0x20000000, 0x1BC0, 0x01000000, - 0x1BCC, 0x00000009, + 0x1BCC, 0x00000000, 0x1B00, 0xF800000A, 0x1B1C, 0xA2193C32, 0x1B20, 0x01840008, @@ -3328,8 +5940,8 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0x1B34, 0x00000800, 0x1B3C, 0x20000000, 0x1BC0, 0x01000000, - 0x1BCC, 0x00000009, - 0x1B00, 0xF8000008, + 0x1BCC, 0x00000000, + 0x1B00, 0xF8000000, 0x1B80, 0x00000007, 0x1B80, 0x090A0005, 0x1B80, 0x090A0007, @@ -3377,16 +5989,16 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0x1B80, 0x85030157, 0x1B80, 0x40090165, 0x1B80, 0x40090167, - 0x1B80, 0xE0210175, - 0x1B80, 0xE0210177, + 0x1B80, 0xE0280175, + 0x1B80, 0xE0280177, 0x1B80, 0x4B050185, 0x1B80, 0x4B050187, 0x1B80, 0x86030195, 0x1B80, 0x86030197, 0x1B80, 0x400B01A5, 0x1B80, 0x400B01A7, - 0x1B80, 0xE02101B5, - 0x1B80, 0xE02101B7, + 0x1B80, 0xE02801B5, + 0x1B80, 0xE02801B7, 0x1B80, 0x4B0001C5, 0x1B80, 0x4B0001C7, 0x1B80, 0x000701D5, @@ -3395,840 +6007,1066 @@ u4Byte Array_MP_8822B_PHY_REG[] = { 0x1B80, 0x4C0001E7, 0x1B80, 0x000401F5, 0x1B80, 0x000401F7, - 0x1B80, 0x30000205, - 0x1B80, 0x30000207, - 0x1B80, 0xFE160215, - 0x1B80, 0xFE160217, - 0x1B80, 0xFF160225, - 0x1B80, 0xFF160227, - 0x1B80, 0xE1670235, - 0x1B80, 0xE1670237, - 0x1B80, 0xF00A0245, - 0x1B80, 0xF00A0247, - 0x1B80, 0xF10A0255, - 0x1B80, 0xF10A0257, - 0x1B80, 0xF20A0265, - 0x1B80, 0xF20A0267, - 0x1B80, 0xF30A0275, - 0x1B80, 0xF30A0277, - 0x1B80, 0xF40A0285, - 0x1B80, 0xF40A0287, - 0x1B80, 0xF50A0295, - 0x1B80, 0xF50A0297, - 0x1B80, 0xF60A02A5, - 0x1B80, 0xF60A02A7, - 0x1B80, 0xF70A02B5, - 0x1B80, 0xF70A02B7, - 0x1B80, 0xF80A02C5, - 0x1B80, 0xF80A02C7, - 0x1B80, 0x000102D5, - 0x1B80, 0x000102D7, - 0x1B80, 0x303902E5, - 0x1B80, 0x303902E7, - 0x1B80, 0x305102F5, - 0x1B80, 0x305102F7, - 0x1B80, 0x309C0305, - 0x1B80, 0x309C0307, - 0x1B80, 0x30530315, - 0x1B80, 0x30530317, - 0x1B80, 0x305E0325, - 0x1B80, 0x305E0327, - 0x1B80, 0x30690335, - 0x1B80, 0x30690337, - 0x1B80, 0x30A00345, - 0x1B80, 0x30A00347, - 0x1B80, 0x30AF0355, - 0x1B80, 0x30AF0357, - 0x1B80, 0x30BA0365, - 0x1B80, 0x30BA0367, - 0x1B80, 0x30ED0375, - 0x1B80, 0x30ED0377, - 0x1B80, 0x30F00385, - 0x1B80, 0x30F00387, - 0x1B80, 0xE1060395, - 0x1B80, 0xE1060397, - 0x1B80, 0x4D0403A5, - 0x1B80, 0x4D0403A7, - 0x1B80, 0x208003B5, - 0x1B80, 0x208003B7, - 0x1B80, 0x000003C5, - 0x1B80, 0x000003C7, - 0x1B80, 0x4D0003D5, - 0x1B80, 0x4D0003D7, - 0x1B80, 0x550703E5, - 0x1B80, 0x550703E7, - 0x1B80, 0xE0FE03F5, - 0x1B80, 0xE0FE03F7, - 0x1B80, 0xE0FE0405, - 0x1B80, 0xE0FE0407, - 0x1B80, 0x4D040415, - 0x1B80, 0x4D040417, - 0x1B80, 0x20880425, - 0x1B80, 0x20880427, - 0x1B80, 0x02000435, - 0x1B80, 0x02000437, - 0x1B80, 0x4D000445, - 0x1B80, 0x4D000447, - 0x1B80, 0x550F0455, - 0x1B80, 0x550F0457, - 0x1B80, 0xE0FE0465, - 0x1B80, 0xE0FE0467, - 0x1B80, 0x4F020475, - 0x1B80, 0x4F020477, - 0x1B80, 0x4E000485, - 0x1B80, 0x4E000487, - 0x1B80, 0x53020495, - 0x1B80, 0x53020497, - 0x1B80, 0x520104A5, - 0x1B80, 0x520104A7, - 0x1B80, 0xE10204B5, - 0x1B80, 0xE10204B7, - 0x1B80, 0x4D0804C5, - 0x1B80, 0x4D0804C7, - 0x1B80, 0x571004D5, - 0x1B80, 0x571004D7, - 0x1B80, 0x570004E5, - 0x1B80, 0x570004E7, + 0x1B80, 0x4D040205, + 0x1B80, 0x4D040207, + 0x1B80, 0x2EF00215, + 0x1B80, 0x2EF00217, + 0x1B80, 0x00000225, + 0x1B80, 0x00000227, + 0x1B80, 0x20810235, + 0x1B80, 0x20810237, + 0x1B80, 0x23450245, + 0x1B80, 0x23450247, + 0x1B80, 0x4D000255, + 0x1B80, 0x4D000257, + 0x1B80, 0x00040265, + 0x1B80, 0x00040267, + 0x1B80, 0x30000275, + 0x1B80, 0x30000277, + 0x1B80, 0xE1D80285, + 0x1B80, 0xE1D80287, + 0x1B80, 0xF0110295, + 0x1B80, 0xF0110297, + 0x1B80, 0xF11102A5, + 0x1B80, 0xF11102A7, + 0x1B80, 0xF21102B5, + 0x1B80, 0xF21102B7, + 0x1B80, 0xF31102C5, + 0x1B80, 0xF31102C7, + 0x1B80, 0xF41102D5, + 0x1B80, 0xF41102D7, + 0x1B80, 0xF51102E5, + 0x1B80, 0xF51102E7, + 0x1B80, 0xF61102F5, + 0x1B80, 0xF61102F7, + 0x1B80, 0xF7110305, + 0x1B80, 0xF7110307, + 0x1B80, 0xF8110315, + 0x1B80, 0xF8110317, + 0x1B80, 0xF9110325, + 0x1B80, 0xF9110327, + 0x1B80, 0xFA110335, + 0x1B80, 0xFA110337, + 0x1B80, 0xFB110345, + 0x1B80, 0xFB110347, + 0x1B80, 0xFC110355, + 0x1B80, 0xFC110357, + 0x1B80, 0xFD110365, + 0x1B80, 0xFD110367, + 0x1B80, 0xFE110375, + 0x1B80, 0xFE110377, + 0x1B80, 0xFF110385, + 0x1B80, 0xFF110387, + 0x1B80, 0x00010395, + 0x1B80, 0x00010397, + 0x1B80, 0x305103A5, + 0x1B80, 0x305103A7, + 0x1B80, 0x306903B5, + 0x1B80, 0x306903B7, + 0x1B80, 0x30B403C5, + 0x1B80, 0x30B403C7, + 0x1B80, 0x30B703D5, + 0x1B80, 0x30B703D7, + 0x1B80, 0x306B03E5, + 0x1B80, 0x306B03E7, + 0x1B80, 0x307603F5, + 0x1B80, 0x307603F7, + 0x1B80, 0x30810405, + 0x1B80, 0x30810407, + 0x1B80, 0x30C10415, + 0x1B80, 0x30C10417, + 0x1B80, 0x30BB0425, + 0x1B80, 0x30BB0427, + 0x1B80, 0x30CF0435, + 0x1B80, 0x30CF0437, + 0x1B80, 0x30DA0445, + 0x1B80, 0x30DA0447, + 0x1B80, 0x30E50455, + 0x1B80, 0x30E50457, + 0x1B80, 0x304A0465, + 0x1B80, 0x304A0467, + 0x1B80, 0x31140475, + 0x1B80, 0x31140477, + 0x1B80, 0x31250485, + 0x1B80, 0x31250487, + 0x1B80, 0x313A0495, + 0x1B80, 0x313A0497, + 0x1B80, 0x4D0404A5, + 0x1B80, 0x4D0404A7, + 0x1B80, 0x2EF004B5, + 0x1B80, 0x2EF004B7, + 0x1B80, 0x000004C5, + 0x1B80, 0x000004C7, + 0x1B80, 0x208104D5, + 0x1B80, 0x208104D7, + 0x1B80, 0xA3B504E5, + 0x1B80, 0xA3B504E7, 0x1B80, 0x4D0004F5, 0x1B80, 0x4D0004F7, - 0x1B80, 0x00010505, - 0x1B80, 0x00010507, - 0x1B80, 0xE1060515, - 0x1B80, 0xE1060517, - 0x1B80, 0x00010525, - 0x1B80, 0x00010527, - 0x1B80, 0x30730535, - 0x1B80, 0x30730537, - 0x1B80, 0x00230545, - 0x1B80, 0x00230547, - 0x1B80, 0xE15A0555, - 0x1B80, 0xE15A0557, - 0x1B80, 0x00020565, - 0x1B80, 0x00020567, - 0x1B80, 0x54E90575, - 0x1B80, 0x54E90577, - 0x1B80, 0x0BA60585, - 0x1B80, 0x0BA60587, - 0x1B80, 0x00230595, - 0x1B80, 0x00230597, - 0x1B80, 0xE15A05A5, - 0x1B80, 0xE15A05A7, - 0x1B80, 0x000205B5, - 0x1B80, 0x000205B7, - 0x1B80, 0x4D3005C5, - 0x1B80, 0x4D3005C7, - 0x1B80, 0x308C05D5, - 0x1B80, 0x308C05D7, - 0x1B80, 0x306F05E5, - 0x1B80, 0x306F05E7, - 0x1B80, 0x002205F5, - 0x1B80, 0x002205F7, - 0x1B80, 0xE15A0605, - 0x1B80, 0xE15A0607, - 0x1B80, 0x00020615, - 0x1B80, 0x00020617, - 0x1B80, 0x54E80625, - 0x1B80, 0x54E80627, - 0x1B80, 0x0BA60635, - 0x1B80, 0x0BA60637, - 0x1B80, 0x00220645, - 0x1B80, 0x00220647, - 0x1B80, 0xE15A0655, - 0x1B80, 0xE15A0657, - 0x1B80, 0x00020665, - 0x1B80, 0x00020667, - 0x1B80, 0x4D300675, - 0x1B80, 0x4D300677, - 0x1B80, 0x308C0685, - 0x1B80, 0x308C0687, - 0x1B80, 0x63F10695, - 0x1B80, 0x63F10697, - 0x1B80, 0xE10606A5, - 0x1B80, 0xE10606A7, - 0x1B80, 0xE15A06B5, - 0x1B80, 0xE15A06B7, - 0x1B80, 0x63F406C5, - 0x1B80, 0x63F406C7, - 0x1B80, 0xE10606D5, - 0x1B80, 0xE10606D7, - 0x1B80, 0xE15A06E5, - 0x1B80, 0xE15A06E7, - 0x1B80, 0x0BA806F5, - 0x1B80, 0x0BA806F7, - 0x1B80, 0x63F80705, - 0x1B80, 0x63F80707, - 0x1B80, 0xE1060715, - 0x1B80, 0xE1060717, - 0x1B80, 0xE15A0725, - 0x1B80, 0xE15A0727, - 0x1B80, 0x0BA90735, - 0x1B80, 0x0BA90737, - 0x1B80, 0x63FC0745, - 0x1B80, 0x63FC0747, - 0x1B80, 0xE1060755, - 0x1B80, 0xE1060757, - 0x1B80, 0xE15A0765, - 0x1B80, 0xE15A0767, - 0x1B80, 0x63FF0775, - 0x1B80, 0x63FF0777, - 0x1B80, 0xE1060785, - 0x1B80, 0xE1060787, - 0x1B80, 0xE15A0795, - 0x1B80, 0xE15A0797, - 0x1B80, 0x630007A5, - 0x1B80, 0x630007A7, - 0x1B80, 0xE10607B5, - 0x1B80, 0xE10607B7, - 0x1B80, 0xE15A07C5, - 0x1B80, 0xE15A07C7, - 0x1B80, 0x630307D5, - 0x1B80, 0x630307D7, - 0x1B80, 0xE10607E5, - 0x1B80, 0xE10607E7, - 0x1B80, 0xE15A07F5, - 0x1B80, 0xE15A07F7, - 0x1B80, 0xF3D40805, - 0x1B80, 0xF3D40807, - 0x1B80, 0x63070815, - 0x1B80, 0x63070817, - 0x1B80, 0xE1060825, - 0x1B80, 0xE1060827, - 0x1B80, 0xE15A0835, - 0x1B80, 0xE15A0837, - 0x1B80, 0xF4DB0845, - 0x1B80, 0xF4DB0847, - 0x1B80, 0x630B0855, - 0x1B80, 0x630B0857, - 0x1B80, 0xE1060865, - 0x1B80, 0xE1060867, - 0x1B80, 0xE15A0875, - 0x1B80, 0xE15A0877, - 0x1B80, 0x630E0885, - 0x1B80, 0x630E0887, - 0x1B80, 0xE1060895, - 0x1B80, 0xE1060897, - 0x1B80, 0xE15A08A5, - 0x1B80, 0xE15A08A7, - 0x1B80, 0x4D3008B5, - 0x1B80, 0x4D3008B7, - 0x1B80, 0x550108C5, - 0x1B80, 0x550108C7, - 0x1B80, 0x570408D5, - 0x1B80, 0x570408D7, - 0x1B80, 0x570008E5, - 0x1B80, 0x570008E7, - 0x1B80, 0x960008F5, - 0x1B80, 0x960008F7, - 0x1B80, 0x57080905, - 0x1B80, 0x57080907, - 0x1B80, 0x57000915, - 0x1B80, 0x57000917, - 0x1B80, 0x95000925, - 0x1B80, 0x95000927, - 0x1B80, 0x4D000935, - 0x1B80, 0x4D000937, - 0x1B80, 0x6C070945, - 0x1B80, 0x6C070947, - 0x1B80, 0x7B200955, - 0x1B80, 0x7B200957, - 0x1B80, 0x7A000965, - 0x1B80, 0x7A000967, - 0x1B80, 0x79000975, - 0x1B80, 0x79000977, - 0x1B80, 0x7F200985, - 0x1B80, 0x7F200987, - 0x1B80, 0x7E000995, - 0x1B80, 0x7E000997, - 0x1B80, 0x7D0009A5, - 0x1B80, 0x7D0009A7, - 0x1B80, 0x000109B5, - 0x1B80, 0x000109B7, - 0x1B80, 0x628509C5, - 0x1B80, 0x628509C7, - 0x1B80, 0xE10609D5, - 0x1B80, 0xE10609D7, - 0x1B80, 0xE13409E5, - 0x1B80, 0xE13409E7, - 0x1B80, 0x000109F5, - 0x1B80, 0x000109F7, - 0x1B80, 0x5C320A05, - 0x1B80, 0x5C320A07, - 0x1B80, 0x63FC0A15, - 0x1B80, 0x63FC0A17, - 0x1B80, 0x62850A25, - 0x1B80, 0x62850A27, - 0x1B80, 0xE1060A35, - 0x1B80, 0xE1060A37, - 0x1B80, 0x30CC0A45, - 0x1B80, 0x30CC0A47, - 0x1B80, 0x00230A55, - 0x1B80, 0x00230A57, - 0x1B80, 0xE15F0A65, - 0x1B80, 0xE15F0A67, - 0x1B80, 0x00020A75, - 0x1B80, 0x00020A77, - 0x1B80, 0x54E90A85, - 0x1B80, 0x54E90A87, - 0x1B80, 0x0BA60A95, - 0x1B80, 0x0BA60A97, - 0x1B80, 0x00230AA5, - 0x1B80, 0x00230AA7, - 0x1B80, 0xE15F0AB5, - 0x1B80, 0xE15F0AB7, - 0x1B80, 0x00020AC5, - 0x1B80, 0x00020AC7, - 0x1B80, 0x4D100AD5, - 0x1B80, 0x4D100AD7, - 0x1B80, 0x308C0AE5, - 0x1B80, 0x308C0AE7, - 0x1B80, 0x30C40AF5, - 0x1B80, 0x30C40AF7, - 0x1B80, 0x00220B05, - 0x1B80, 0x00220B07, - 0x1B80, 0xE15F0B15, - 0x1B80, 0xE15F0B17, - 0x1B80, 0x00020B25, - 0x1B80, 0x00020B27, - 0x1B80, 0x54E80B35, - 0x1B80, 0x54E80B37, - 0x1B80, 0x0BA60B45, - 0x1B80, 0x0BA60B47, - 0x1B80, 0x00220B55, - 0x1B80, 0x00220B57, - 0x1B80, 0xE15F0B65, - 0x1B80, 0xE15F0B67, - 0x1B80, 0x00020B75, - 0x1B80, 0x00020B77, - 0x1B80, 0x4D100B85, - 0x1B80, 0x4D100B87, - 0x1B80, 0x308C0B95, - 0x1B80, 0x308C0B97, - 0x1B80, 0x5C320BA5, - 0x1B80, 0x5C320BA7, - 0x1B80, 0x63F40BB5, - 0x1B80, 0x63F40BB7, - 0x1B80, 0x62850BC5, - 0x1B80, 0x62850BC7, - 0x1B80, 0xE1060BD5, - 0x1B80, 0xE1060BD7, - 0x1B80, 0x67F10BE5, - 0x1B80, 0x67F10BE7, - 0x1B80, 0xE1340BF5, - 0x1B80, 0xE1340BF7, - 0x1B80, 0xE15F0C05, - 0x1B80, 0xE15F0C07, - 0x1B80, 0x67F40C15, - 0x1B80, 0x67F40C17, - 0x1B80, 0xE1340C25, - 0x1B80, 0xE1340C27, - 0x1B80, 0xE15F0C35, - 0x1B80, 0xE15F0C37, - 0x1B80, 0x5C320C45, - 0x1B80, 0x5C320C47, - 0x1B80, 0x63FC0C55, - 0x1B80, 0x63FC0C57, - 0x1B80, 0x62850C65, - 0x1B80, 0x62850C67, - 0x1B80, 0xE1060C75, - 0x1B80, 0xE1060C77, - 0x1B80, 0x0BA80C85, - 0x1B80, 0x0BA80C87, - 0x1B80, 0x67F80C95, - 0x1B80, 0x67F80C97, - 0x1B80, 0xE1340CA5, - 0x1B80, 0xE1340CA7, - 0x1B80, 0xE15F0CB5, - 0x1B80, 0xE15F0CB7, - 0x1B80, 0x0BA90CC5, - 0x1B80, 0x0BA90CC7, - 0x1B80, 0x67FC0CD5, - 0x1B80, 0x67FC0CD7, - 0x1B80, 0xE1340CE5, - 0x1B80, 0xE1340CE7, - 0x1B80, 0xE15F0CF5, - 0x1B80, 0xE15F0CF7, - 0x1B80, 0x67FF0D05, - 0x1B80, 0x67FF0D07, - 0x1B80, 0xE1340D15, - 0x1B80, 0xE1340D17, - 0x1B80, 0xE15F0D25, - 0x1B80, 0xE15F0D27, - 0x1B80, 0x5C320D35, - 0x1B80, 0x5C320D37, - 0x1B80, 0x63030D45, - 0x1B80, 0x63030D47, - 0x1B80, 0xE1060D55, - 0x1B80, 0xE1060D57, - 0x1B80, 0x67000D65, - 0x1B80, 0x67000D67, - 0x1B80, 0xE1340D75, - 0x1B80, 0xE1340D77, - 0x1B80, 0xE15F0D85, - 0x1B80, 0xE15F0D87, - 0x1B80, 0x67030D95, - 0x1B80, 0x67030D97, - 0x1B80, 0xE1340DA5, - 0x1B80, 0xE1340DA7, - 0x1B80, 0xE15F0DB5, - 0x1B80, 0xE15F0DB7, - 0x1B80, 0xF6C90DC5, - 0x1B80, 0xF6C90DC7, - 0x1B80, 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0x551517A5, + 0x1B80, 0x551517A7, + 0x1B80, 0xE16117B5, + 0x1B80, 0xE16117B7, + 0x1B80, 0xE1C717C5, + 0x1B80, 0xE1C717C7, + 0x1B80, 0x000117D5, + 0x1B80, 0x000117D7, + 0x1B80, 0x54BF17E5, + 0x1B80, 0x54BF17E7, + 0x1B80, 0x54C017F5, + 0x1B80, 0x54C017F7, + 0x1B80, 0x54A31805, + 0x1B80, 0x54A31807, + 0x1B80, 0x54C11815, + 0x1B80, 0x54C11817, + 0x1B80, 0x54A41825, + 0x1B80, 0x54A41827, + 0x1B80, 0x4C181835, + 0x1B80, 0x4C181837, + 0x1B80, 0xBF071845, + 0x1B80, 0xBF071847, + 0x1B80, 0x54C21855, + 0x1B80, 0x54C21857, + 0x1B80, 0x54A41865, + 0x1B80, 0x54A41867, + 0x1B80, 0xBF041875, + 0x1B80, 0xBF041877, + 0x1B80, 0x54C11885, + 0x1B80, 0x54C11887, + 0x1B80, 0x54A31895, + 0x1B80, 0x54A31897, + 0x1B80, 0xBF0118A5, + 0x1B80, 0xBF0118A7, + 0x1B80, 0xE1D518B5, + 0x1B80, 0xE1D518B7, + 0x1B80, 0x54DF18C5, + 0x1B80, 0x54DF18C7, + 0x1B80, 0x000118D5, + 0x1B80, 0x000118D7, + 0x1B80, 0x54BF18E5, + 0x1B80, 0x54BF18E7, + 0x1B80, 0x54E518F5, + 0x1B80, 0x54E518F7, + 0x1B80, 0x050A1905, + 0x1B80, 0x050A1907, + 0x1B80, 0x54DF1915, + 0x1B80, 0x54DF1917, + 0x1B80, 0x00011925, + 0x1B80, 0x00011927, + 0x1B80, 0x7F201935, + 0x1B80, 0x7F201937, + 0x1B80, 0x7E001945, + 0x1B80, 0x7E001947, + 0x1B80, 0x7D001955, + 0x1B80, 0x7D001957, + 0x1B80, 0x55011965, + 0x1B80, 0x55011967, + 0x1B80, 0x5C311975, + 0x1B80, 0x5C311977, + 0x1B80, 0xE15D1985, + 0x1B80, 0xE15D1987, + 0x1B80, 0xE1611995, + 0x1B80, 0xE1611997, + 0x1B80, 0x548019A5, + 0x1B80, 0x548019A7, + 0x1B80, 0x540019B5, + 0x1B80, 0x540019B7, + 0x1B80, 0xE15D19C5, + 0x1B80, 0xE15D19C7, + 0x1B80, 0xE16119D5, + 0x1B80, 0xE16119D7, + 0x1B80, 0x548119E5, + 0x1B80, 0x548119E7, + 0x1B80, 0x540019F5, + 0x1B80, 0x540019F7, + 0x1B80, 0xE15D1A05, + 0x1B80, 0xE15D1A07, + 0x1B80, 0xE1611A15, + 0x1B80, 0xE1611A17, + 0x1B80, 0x54821A25, + 0x1B80, 0x54821A27, + 0x1B80, 0x54001A35, + 0x1B80, 0x54001A37, + 0x1B80, 0xE17E1A45, + 0x1B80, 0xE17E1A47, + 0x1B80, 0xBFE91A55, + 0x1B80, 0xBFE91A57, + 0x1B80, 0x301D1A65, + 0x1B80, 0x301D1A67, + 0x1B80, 0x00231A75, + 0x1B80, 0x00231A77, + 0x1B80, 0x7B201A85, + 0x1B80, 0x7B201A87, + 0x1B80, 0x7A001A95, + 0x1B80, 0x7A001A97, + 0x1B80, 0x79001AA5, + 0x1B80, 0x79001AA7, + 0x1B80, 0xE1CB1AB5, + 0x1B80, 0xE1CB1AB7, + 0x1B80, 0x00021AC5, + 0x1B80, 0x00021AC7, + 0x1B80, 0x00011AD5, + 0x1B80, 0x00011AD7, + 0x1B80, 0x00221AE5, + 0x1B80, 0x00221AE7, + 0x1B80, 0x7B201AF5, + 0x1B80, 0x7B201AF7, + 0x1B80, 0x7A001B05, + 0x1B80, 0x7A001B07, + 0x1B80, 0x79001B15, + 0x1B80, 0x79001B17, + 0x1B80, 0xE1CB1B25, + 0x1B80, 0xE1CB1B27, + 0x1B80, 0x00021B35, + 0x1B80, 0x00021B37, + 0x1B80, 0x00011B45, + 0x1B80, 0x00011B47, + 0x1B80, 0x74021B55, + 0x1B80, 0x74021B57, + 0x1B80, 0x003F1B65, + 0x1B80, 0x003F1B67, + 0x1B80, 0x74001B75, + 0x1B80, 0x74001B77, + 0x1B80, 0x00021B85, + 0x1B80, 0x00021B87, + 0x1B80, 0x00011B95, + 0x1B80, 0x00011B97, + 0x1B80, 0x4D041BA5, + 0x1B80, 0x4D041BA7, + 0x1B80, 0x2EF81BB5, + 0x1B80, 0x2EF81BB7, + 0x1B80, 0x00001BC5, + 0x1B80, 0x00001BC7, + 0x1B80, 0x23301BD5, + 0x1B80, 0x23301BD7, + 0x1B80, 0x00241BE5, + 0x1B80, 0x00241BE7, + 0x1B80, 0x23E01BF5, + 0x1B80, 0x23E01BF7, + 0x1B80, 0x003F1C05, + 0x1B80, 0x003F1C07, + 0x1B80, 0x23FC1C15, + 0x1B80, 0x23FC1C17, + 0x1B80, 0xBFCE1C25, + 0x1B80, 0xBFCE1C27, + 0x1B80, 0x2EF01C35, + 0x1B80, 0x2EF01C37, + 0x1B80, 0x00001C45, + 0x1B80, 0x00001C47, + 0x1B80, 0x4D001C55, + 0x1B80, 0x4D001C57, + 0x1B80, 0x00011C65, + 0x1B80, 0x00011C67, + 0x1B80, 0x549F1C75, + 0x1B80, 0x549F1C77, + 0x1B80, 0x54FF1C85, + 0x1B80, 0x54FF1C87, + 0x1B80, 0x54001C95, + 0x1B80, 0x54001C97, + 0x1B80, 0x00011CA5, + 0x1B80, 0x00011CA7, + 0x1B80, 0x5C311CB5, + 0x1B80, 0x5C311CB7, + 0x1B80, 0x07141CC5, + 0x1B80, 0x07141CC7, + 0x1B80, 0x54001CD5, + 0x1B80, 0x54001CD7, + 0x1B80, 0x5C321CE5, + 0x1B80, 0x5C321CE7, + 0x1B80, 0x00011CF5, + 0x1B80, 0x00011CF7, + 0x1B80, 0x5C321D05, + 0x1B80, 0x5C321D07, + 0x1B80, 0x07141D15, + 0x1B80, 0x07141D17, + 0x1B80, 0x54001D25, + 0x1B80, 0x54001D27, + 0x1B80, 0x5C311D35, + 0x1B80, 0x5C311D37, + 0x1B80, 0x00011D45, + 0x1B80, 0x00011D47, + 0x1B80, 0x4C981D55, + 0x1B80, 0x4C981D57, + 0x1B80, 0x4C181D65, + 0x1B80, 0x4C181D67, + 0x1B80, 0x00011D75, + 0x1B80, 0x00011D77, + 0x1B80, 0x5C321D85, + 0x1B80, 0x5C321D87, + 0x1B80, 0x62841D95, + 0x1B80, 0x62841D97, + 0x1B80, 0x66861DA5, + 0x1B80, 0x66861DA7, + 0x1B80, 0x6C031DB5, + 0x1B80, 0x6C031DB7, + 0x1B80, 0x7B201DC5, + 0x1B80, 0x7B201DC7, + 0x1B80, 0x7A001DD5, + 0x1B80, 0x7A001DD7, + 0x1B80, 0x79001DE5, + 0x1B80, 0x79001DE7, + 0x1B80, 0x7F201DF5, + 0x1B80, 0x7F201DF7, + 0x1B80, 0x7E001E05, + 0x1B80, 0x7E001E07, + 0x1B80, 0x7D001E15, + 0x1B80, 0x7D001E17, + 0x1B80, 0x09011E25, + 0x1B80, 0x09011E27, + 0x1B80, 0x0C011E35, + 0x1B80, 0x0C011E37, + 0x1B80, 0x0BA61E45, + 0x1B80, 0x0BA61E47, + 0x1B80, 0x00011E55, + 0x1B80, 0x00011E57, 0x1B80, 0x00000006, 0x1B80, 0x00000002, }; void -ODM_ReadAndConfig_MP_8822B_PHY_REG( - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_phy_reg( + struct PHY_DM_STRUCT *p_dm_odm ) { - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_PHY_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8822b_phy_reg)/sizeof(u32); + u32 *array = array_mp_8822b_phy_reg; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_phy_reg\n")); - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped?false:true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; } else { - bMatched = FALSE; - bSkipped = FALSE; + is_matched = false; + is_skipped = false; } } else - bMatched = FALSE; + is_matched = false; } } else { - if (bMatched) - odm_ConfigBB_PHY_8822B(pDM_Odm, v1, bMaskDWord, v2); + if (is_matched) + odm_config_bb_phy_8822b(p_dm_odm, v1, MASKDWORD, v2); } i = i + 2; } } -u4Byte -ODM_GetVersion_MP_8822B_PHY_REG(void) +u32 +odm_get_version_mp_8822b_phy_reg(void) { - return 50; + return 85; } /****************************************************************************** -* PHY_REG_PG.TXT +* phy_reg_pg.TXT ******************************************************************************/ -u4Byte Array_MP_8822B_PHY_REG_PG[] = { - 0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840, - 0, 0, 0, 0x00000c24, 0xffffffff, 0x38404244, - 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323436, - 0, 0, 0, 0x00000c2c, 0xffffffff, 0x36384042, - 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, +u32 array_mp_8822b_phy_reg_pg[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 0, 0, 0, 0x00000c3c, 0xffffffff, 0x36384042, - 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402426, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 0, 1, 0, 0x00000e20, 0xffffffff, 0x34363840, - 0, 1, 0, 0x00000e24, 0xffffffff, 0x38404244, - 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323436, - 0, 1, 0, 0x00000e2c, 0xffffffff, 0x36384042, - 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 0, 1, 0, 0x00000e3c, 0xffffffff, 0x36384042, - 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402426, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x38404244, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323436, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x36384042, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303234, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x36384042, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303234, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x38402426, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x38404244, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323436, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x36384042, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303234, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x36384042, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303234, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x38402426, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628 + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 }; void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG( - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_phy_reg_pg( + struct PHY_DM_STRUCT *p_dm_odm ) { - u4Byte i = 0; - u4Byte ArrayLen = sizeof(Array_MP_8822B_PHY_REG_PG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_PHY_REG_PG; + u32 i = 0; + u32 array_len = sizeof(array_mp_8822b_phy_reg_pg)/sizeof(u32); + u32 *array = array_mp_8822b_phy_reg_pg; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesReadPwrByRate = ArrayLen/6; + PlatformZeroMemory(p_hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + p_hal_data->nLinesReadPwrByRate = array_len/6; #endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_PHY_REG_PG\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_phy_reg_pg\n")); - pDM_Odm->PhyRegPgVersion = 1; - pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + p_dm_odm->phy_reg_pg_version = 1; + p_dm_odm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; - for (i = 0; i < ArrayLen; i += 6) { - u4Byte v1 = Array[i]; - u4Byte v2 = Array[i+1]; - u4Byte v3 = Array[i+2]; - u4Byte v4 = Array[i+3]; - u4Byte v5 = Array[i+4]; - u4Byte v6 = Array[i+5]; + for (i = 0; i < array_len; i += 6) { + u32 v1 = array[i]; + u32 v2 = array[i+1]; + u32 v3 = array[i+2]; + u32 v4 = array[i+3]; + u32 v5 = array[i+4]; + u32 v6 = array[i+5]; - odm_ConfigBB_PHY_REG_PG_8822B(pDM_Odm, v1, v2, v3, v4, v5, v6); + odm_config_bb_phy_reg_pg_8822b(p_dm_odm, v1, v2, v3, v4, v5, v6); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + rsprintf((char *)p_hal_data->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); #endif } diff --git a/hal/phydm/rtl8822b/halhwimg8822b_bb.h b/hal/phydm/rtl8822b/halhwimg8822b_bb.h index b270a0d..cd0ba96 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_bb.h +++ b/hal/phydm/rtl8822b/halhwimg8822b_bb.h @@ -1,58 +1,53 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* ******************************************************************************/ -/*Image2HeaderVersion: 2.22*/ +/*Image2HeaderVersion: R2 1.2.1*/ #if (RTL8822B_SUPPORT == 1) #ifndef __INC_MP_BB_HW_IMG_8822B_H #define __INC_MP_BB_HW_IMG_8822B_H /****************************************************************************** -* AGC_TAB.TXT +* agc_tab.TXT ******************************************************************************/ void -ODM_ReadAndConfig_MP_8822B_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_agc_tab(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte ODM_GetVersion_MP_8822B_AGC_TAB(void); +u32 odm_get_version_mp_8822b_agc_tab(void); /****************************************************************************** -* PHY_REG.TXT +* phy_reg.TXT ******************************************************************************/ void -ODM_ReadAndConfig_MP_8822B_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_phy_reg(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte ODM_GetVersion_MP_8822B_PHY_REG(void); +u32 odm_get_version_mp_8822b_phy_reg(void); /****************************************************************************** -* PHY_REG_PG.TXT +* phy_reg_pg.TXT ******************************************************************************/ void -ODM_ReadAndConfig_MP_8822B_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_phy_reg_pg(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte ODM_GetVersion_MP_8822B_PHY_REG_PG(void); +u32 odm_get_version_mp_8822b_phy_reg_pg(void); #endif #endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8822b/halhwimg8822b_fw.c b/hal/phydm/rtl8822b/halhwimg8822b_fw.c index 16b7f23..6b5ed8e 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_fw.c +++ b/hal/phydm/rtl8822b/halhwimg8822b_fw.c @@ -1,21 +1,21 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* ******************************************************************************/ /*Image2HeaderVersion: 2.16*/ @@ -23,7 +23,7 @@ #include "../phydm_precomp.h" #ifdef LOAD_FW_HEADER_FROM_DRIVER -#include "../../rtl8822b/hal8822b_fw.h" + #include "../../rtl8822b/hal8822b_fw.h" #endif @@ -32,13398 +32,13398 @@ #ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8822B_FW_AP[] = { -0x22, 0x88, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, 0xC9, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x03, 0x1B, 0x10, 0x33, 0xE0, 0x07, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, -0x00, 0x00, 0x20, 0x80, 0x88, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0xB0, 0xDD, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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u8 *p_firmware, + u32 *p_firmware_size ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8822B_FW_AP; + *((SIZE_PTR *)p_firmware) = (SIZE_PTR)array_mp_8822b_fw_ap; #else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8822B_FW_AP, ArrayLength_MP_8822B_FW_AP); + odm_move_memory(p_dm_odm, p_firmware, array_mp_8822b_fw_ap, array_length_mp_8822b_fw_ap); #endif - *pFirmwareSize = ArrayLength_MP_8822B_FW_AP; + *p_firmware_size = array_length_mp_8822b_fw_ap; } -#endif /* #if (defined(CONFIG_AP_WOWLAN)||(DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ +#endif /* #if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) #ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8822B_FW_NIC[] = { -0x22, 0x88, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, 0xC9, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x03, 0x1B, 0x10, 0x32, 0xE0, 0x07, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, -0x00, 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-u4Byte ArrayLength_MP_8822B_FW_NIC = 88160; +u32 array_length_mp_8822b_fw_nic = 88160; #endif void -ODM_ReadFirmware_MP_8822B_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize +odm_read_firmware_mp_8822b_fw_nic( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_firmware, + u32 *p_firmware_size ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8822B_FW_NIC; + *((SIZE_PTR *)p_firmware) = (SIZE_PTR)array_mp_8822b_fw_nic; #else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8822B_FW_NIC, ArrayLength_MP_8822B_FW_NIC); + odm_move_memory(p_dm_odm, p_firmware, array_mp_8822b_fw_nic, array_length_mp_8822b_fw_nic); #endif - *pFirmwareSize = ArrayLength_MP_8822B_FW_NIC; + *p_firmware_size = array_length_mp_8822b_fw_nic; } -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u1Byte Array_MP_8822B_FW_WOWLAN[] = { -0x22, 0x88, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, 0xC9, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x03, 0x1B, 0x10, 0x33, 0xE0, 0x07, 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0x6D, 0x00, 0x6E, 0x00, 0x18, 0x64, 0x2A, 0x30, 0xF0, + 0x20, 0x6A, 0x80, 0xF6, 0xB8, 0x9A, 0x81, 0xF2, 0x00, 0x6C, 0x00, 0x6E, 0x00, 0x18, 0x64, 0x2A, + 0x01, 0xF0, 0x14, 0x6C, 0x1F, 0xF4, 0x00, 0x6D, 0x0F, 0x6E, 0x00, 0x18, 0x64, 0x2A, 0x30, 0xF0, + 0x20, 0x6A, 0xC1, 0xF0, 0x0C, 0x9A, 0x2C, 0xE8, 0x2C, 0x10, 0x06, 0x92, 0x24, 0x5A, 0x4F, 0x61, + 0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF6, 0xB8, 0x9A, 0x81, 0xF2, 0x00, 0x6C, 0x01, 0x6E, 0x00, 0x18, + 0x64, 0x2A, 0x40, 0xF4, 0x14, 0x6C, 0x80, 0x6D, 0x01, 0x6E, 0x00, 0x18, 0x64, 0x2A, 0x30, 0xF0, + 0x20, 0x6A, 0x40, 0xF6, 0xB8, 0x9A, 0x01, 0xF0, 0x08, 0x6C, 0x00, 0x6E, 0x00, 0x18, 0x64, 0x2A, + 0x01, 0xF0, 0x14, 0x6C, 0x1F, 0xF4, 0x00, 0x6D, 0x22, 0x6E, 0x00, 0x18, 0x64, 0x2A, 0x30, 0xF0, + 0x20, 0x6A, 0xC1, 0xF0, 0x0C, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF0, 0x50, 0x9A, 0x2C, 0xE8, + 0x4D, 0xE8, 0x30, 0xF0, 0x20, 0x6A, 0x0C, 0x94, 0x81, 0xF0, 0xF0, 0x9A, 0x00, 0x6D, 0x18, 0x6E, + 0x01, 0x49, 0x04, 0xD0, 0x00, 0x18, 0xCB, 0x33, 0x00, 0x6B, 0x01, 0x21, 0x01, 0x6B, 0xFF, 0x69, + 0x4C, 0xE9, 0x6C, 0xE9, 0x0C, 0x93, 0x4A, 0xA3, 0x0D, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0x81, 0xF0, + 0xF0, 0x9A, 0x83, 0x67, 0x01, 0x6D, 0x18, 0x6E, 0x04, 0xD0, 0x00, 0x18, 0xCB, 0x33, 0x4C, 0xE9, + 0xFF, 0x6A, 0x4C, 0xE9, 0x0C, 0x94, 0x06, 0x95, 0x00, 0x18, 0xDE, 0x32, 0x01, 0x2A, 0x00, 0x69, + 0x51, 0x67, 0x0B, 0x97, 0x0A, 0x91, 0x09, 0x90, 0x06, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62, + 0x08, 0xD1, 0x07, 0xD0, 0xFF, 0x68, 0x0C, 0xED, 0x24, 0x67, 0x0D, 0xD7, 0x04, 0xD5, 0xCC, 0xE8, + 0x00, 0x18, 0x7C, 0x36, 0x0F, 0x22, 0x04, 0x95, 0x91, 0x67, 0x00, 0x18, 0xCC, 0x35, 0x0A, 0x22, + 0x0D, 0x96, 0x91, 0x67, 0xB0, 0x67, 0x00, 0x18, 0xFB, 0x34, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7, + 0x62, 0x32, 0x01, 0x10, 0x00, 0x6A, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, + 0xE9, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -u4Byte ArrayLength_MP_8822B_FW_WOWLAN = 59032; +u32 array_length_mp_8822b_fw_wowlan = 59032; #endif void -ODM_ReadFirmware_MP_8822B_FW_WOWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize +odm_read_firmware_mp_8822b_fw_wowlan( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_firmware, + u32 *p_firmware_size ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8822B_FW_WOWLAN; + *((SIZE_PTR *)p_firmware) = (SIZE_PTR)array_mp_8822b_fw_wowlan; #else - ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8822B_FW_WOWLAN, ArrayLength_MP_8822B_FW_WOWLAN); + odm_move_memory(p_dm_odm, p_firmware, array_mp_8822b_fw_wowlan, array_length_mp_8822b_fw_wowlan); #endif - *pFirmwareSize = ArrayLength_MP_8822B_FW_WOWLAN; + *p_firmware_size = array_length_mp_8822b_fw_wowlan; } @@ -13431,4 +13431,3 @@ ODM_ReadFirmware_MP_8822B_FW_WOWLAN( #endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ #endif /* end of HWIMG_SUPPORT*/ - diff --git a/hal/phydm/rtl8822b/halhwimg8822b_fw.h b/hal/phydm/rtl8822b/halhwimg8822b_fw.h index f565516..9c52383 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_fw.h +++ b/hal/phydm/rtl8822b/halhwimg8822b_fw.h @@ -1,21 +1,21 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* ******************************************************************************/ /*Image2HeaderVersion: 2.16*/ @@ -24,39 +24,38 @@ #define __INC_MP_FW_HW_IMG_8822B_H -/****************************************************************************** -* FW_AP.TXT -******************************************************************************/ +/******************************************************************************/ +/* FW_AP.TXT*/ +/******************************************************************************/ void -ODM_ReadFirmware_MP_8822B_FW_AP( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize +odm_read_firmware_mp_8822b_fw_ap( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_firmware, + u32 *p_firmware_size ); -/****************************************************************************** -* FW_NIC.TXT -******************************************************************************/ +/******************************************************************************/ +/* FW_NIC.TXT*/ +/******************************************************************************/ void -ODM_ReadFirmware_MP_8822B_FW_NIC( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize +odm_read_firmware_mp_8822b_fw_nic( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_firmware, + u32 *p_firmware_size ); -/****************************************************************************** -* FW_WOWLAN.TXT -******************************************************************************/ +/******************************************************************************/ +/* FW_WoWLAN.TXT*/ +/******************************************************************************/ void -ODM_ReadFirmware_MP_8822B_FW_WOWLAN( - IN PDM_ODM_T pDM_Odm, - OUT u1Byte *pFirmware, - OUT u4Byte *pFirmwareSize +odm_read_firmware_mp_8822b_fw_wowlan( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_firmware, + u32 *p_firmware_size ); #endif #endif /* end of HWIMG_SUPPORT*/ - diff --git a/hal/phydm/rtl8822b/halhwimg8822b_mac.c b/hal/phydm/rtl8822b/halhwimg8822b_mac.c index 12aff4e..f3212bb 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_mac.c +++ b/hal/phydm/rtl8822b/halhwimg8822b_mac.c @@ -1,125 +1,104 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* ******************************************************************************/ -/*Image2HeaderVersion: 2.22*/ +/*Image2HeaderVersion: R2 1.2.1*/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (RTL8822B_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 +static boolean +check_positive( + struct PHY_DM_STRUCT *p_dm_odm, + const u32 condition1, + const u32 condition2, + const u32 condition3, + const u32 condition4 ) { - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; + u8 cut_version_for_para = (p_dm_odm->cut_version == ODM_CUT_A) ? 15 : p_dm_odm->cut_version; + u8 pkg_type_for_para = (p_dm_odm->package_type == 0) ? 15 : p_dm_odm->package_type; - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; + u32 driver1 = cut_version_for_para << 24 | + (p_dm_odm->support_interface & 0xF0) << 16 | + p_dm_odm->support_platform << 16 | + pkg_type_for_para << 12 | + (p_dm_odm->support_interface & 0x0F) << 8 | + p_dm_odm->rfe_type; -u4Byte driver3 = 0; + u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 | + (p_dm_odm->type_gpa & 0xFF) << 8 | + (p_dm_odm->type_alna & 0xFF) << 16 | + (p_dm_odm->type_apa & 0xFF) << 24; - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; + u32 driver3 = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 | + (p_dm_odm->type_gpa & 0xFF00) | + (p_dm_odm->type_alna & 0xFF00) << 8 | + (p_dm_odm->type_apa & 0xFF00) << 16; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (RFE, Package) = (0x%X, 0x%X)\n", p_dm_odm->rfe_type, p_dm_odm->package_type)); - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; - /*=============== Bit Defined Check ================*/ - /* We don't care [31:28] */ + /*============== value Defined Check ===============*/ + /*cut version [27:24] need to do value check*/ - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return false; - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; + /*pkg type [15:12] need to do value check*/ - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return false; - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return true; + else + return false; } -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 +static boolean +check_negative( + struct PHY_DM_STRUCT *p_dm_odm, + const u32 condition1, + const u32 condition2 ) { - return TRUE; + return true; } /****************************************************************************** -* MAC_REG.TXT +* mac_reg.TXT ******************************************************************************/ -u4Byte Array_MP_8822B_MAC_REG[] = { +u32 array_mp_8822b_mac_reg[] = { 0x029, 0x000000F9, 0x420, 0x00000080, 0x421, 0x0000000F, @@ -214,9 +193,7 @@ u4Byte Array_MP_8822B_MAC_REG[] = { 0x55D, 0x000000FF, 0x577, 0x0000000B, 0x5BE, 0x00000064, - 0x604, 0x00000001, 0x605, 0x00000030, - 0x607, 0x00000001, 0x608, 0x0000000E, 0x609, 0x00000022, 0x60C, 0x00000018, @@ -245,77 +222,69 @@ u4Byte Array_MP_8822B_MAC_REG[] = { 0x643, 0x00000000, 0x652, 0x000000C8, 0x66E, 0x00000005, - 0x700, 0x00000021, - 0x701, 0x00000043, - 0x702, 0x00000065, - 0x703, 0x00000087, - 0x708, 0x00000021, - 0x709, 0x00000043, - 0x70A, 0x00000065, - 0x70B, 0x00000087, 0x718, 0x00000040, - 0x7D4, 0x00000010, + 0x7D4, 0x00000098, }; void -ODM_ReadAndConfig_MP_8822B_MAC_REG( - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_mac_reg( + struct PHY_DM_STRUCT *p_dm_odm ) { - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8822B_MAC_REG)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_MAC_REG; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8822b_mac_reg)/sizeof(u32); + u32 *array = array_mp_8822b_mac_reg; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_MAC_REG\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_mac_reg\n")); - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped?false:true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; } else { - bMatched = FALSE; - bSkipped = FALSE; + is_matched = false; + is_skipped = false; } } else - bMatched = FALSE; + is_matched = false; } } else { - if (bMatched) - odm_ConfigMAC_8822B(pDM_Odm, v1, (u1Byte)v2); + if (is_matched) + odm_config_mac_8822b(p_dm_odm, v1, (u8)v2); } i = i + 2; } } -u4Byte -ODM_GetVersion_MP_8822B_MAC_REG(void) +u32 +odm_get_version_mp_8822b_mac_reg(void) { - return 50; + return 85; } #endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8822b/halhwimg8822b_mac.h b/hal/phydm/rtl8822b/halhwimg8822b_mac.h index e45c653..17c9c57 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_mac.h +++ b/hal/phydm/rtl8822b/halhwimg8822b_mac.h @@ -1,38 +1,33 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* ******************************************************************************/ -/*Image2HeaderVersion: 2.22*/ +/*Image2HeaderVersion: R2 1.2.1*/ #if (RTL8822B_SUPPORT == 1) #ifndef __INC_MP_MAC_HW_IMG_8822B_H #define __INC_MP_MAC_HW_IMG_8822B_H /****************************************************************************** -* MAC_REG.TXT +* mac_reg.TXT ******************************************************************************/ void -ODM_ReadAndConfig_MP_8822B_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_mac_reg(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte ODM_GetVersion_MP_8822B_MAC_REG(void); +u32 odm_get_version_mp_8822b_mac_reg(void); #endif #endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8822b/halhwimg8822b_rf.c b/hal/phydm/rtl8822b/halhwimg8822b_rf.c index 3e50d5b..0228bde 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_rf.c +++ b/hal/phydm/rtl8822b/halhwimg8822b_rf.c @@ -1,140 +1,143 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* ******************************************************************************/ -/*Image2HeaderVersion: 2.22*/ +/*Image2HeaderVersion: R2 1.2.1*/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (RTL8822B_SUPPORT == 1) -static BOOLEAN -CheckPositive( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2, - IN const u4Byte Condition3, - IN const u4Byte Condition4 +static boolean +check_positive( + struct PHY_DM_STRUCT *p_dm_odm, + const u32 condition1, + const u32 condition2, + const u32 condition3, + const u32 condition4 ) { - u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ - ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ - ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ - ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ - ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ - - u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; - u4Byte driver1 = pDM_Odm->CutVersion << 24 | - (pDM_Odm->SupportInterface & 0xF0) << 16 | - pDM_Odm->SupportPlatform << 16 | - pDM_Odm->PackageType << 12 | - (pDM_Odm->SupportInterface & 0x0F) << 8 | - _BoardType; - - u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | - (pDM_Odm->TypeGPA & 0xFF) << 8 | - (pDM_Odm->TypeALNA & 0xFF) << 16 | - (pDM_Odm->TypeAPA & 0xFF) << 24; - -u4Byte driver3 = 0; - - u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | - (pDM_Odm->TypeGPA & 0xFF00) | - (pDM_Odm->TypeALNA & 0xFF00) << 8 | - (pDM_Odm->TypeAPA & 0xFF00) << 16; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); - - - /*============== Value Defined Check ===============*/ - /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ - - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) - return FALSE; + u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; + + u8 cut_version_for_para = (p_dm_odm->cut_version == ODM_CUT_A) ? 15 : p_dm_odm->cut_version; + u8 pkg_type_for_para = (p_dm_odm->package_type == 0) ? 15 : p_dm_odm->package_type; + + u32 driver1 = cut_version_for_para << 24 | + (p_dm_odm->support_interface & 0xF0) << 16 | + p_dm_odm->support_platform << 16 | + pkg_type_for_para << 12 | + (p_dm_odm->support_interface & 0x0F) << 8 | + p_dm_odm->rfe_type; + + u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 | + (p_dm_odm->type_gpa & 0xFF) << 8 | + (p_dm_odm->type_alna & 0xFF) << 16 | + (p_dm_odm->type_apa & 0xFF) << 24; + + u32 driver3 = 0; + + u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 | + (p_dm_odm->type_gpa & 0xFF00) | + (p_dm_odm->type_alna & 0xFF00) << 8 | + (p_dm_odm->type_apa & 0xFF00) << 16; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (RFE, Package) = (0x%X, 0x%X)\n", p_dm_odm->rfe_type, p_dm_odm->package_type)); + + + /*============== value Defined Check ===============*/ + /*cut version [27:24] need to do value check*/ + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return FALSE; + return false; + + /*pkg type [15:12] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return false; /*=============== Bit Defined Check ================*/ /* We don't care [31:28] */ - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u4Byte bitMask = 0; - - if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ - return TRUE; - - if ((cond1 & BIT0) != 0) /*GLNA*/ - bitMask |= 0x000000FF; - if ((cond1 & BIT1) != 0) /*GPA*/ - bitMask |= 0x0000FF00; - if ((cond1 & BIT2) != 0) /*ALNA*/ - bitMask |= 0x00FF0000; - if ((cond1 & BIT3) != 0) /*APA*/ - bitMask |= 0xFF000000; - - if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ - return TRUE; - else - return FALSE; - } else - return FALSE; + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return true; + else + return false; } -static BOOLEAN -CheckNegative( - IN PDM_ODM_T pDM_Odm, - IN const u4Byte Condition1, - IN const u4Byte Condition2 +static boolean +check_negative( + struct PHY_DM_STRUCT *p_dm_odm, + const u32 condition1, + const u32 condition2 ) { - return TRUE; + return true; } /****************************************************************************** -* RadioA.TXT +* radioa.TXT ******************************************************************************/ -u4Byte Array_MP_8822B_RadioA[] = { +u32 array_mp_8822b_radioa[] = { 0x000, 0x00030000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x0004002D, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x0004002D, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x0004002D, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x0004002D, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x00040029, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x00040029, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x00040029, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, 0xA0000000, 0x00000000, 0x001, 0x00040029, 0xB0000000, 0x00000000, @@ -142,7 +145,11 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x0EF, 0x00080000, 0x033, 0x00000002, 0x03E, 0x0000003F, + 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000D0F4E, + 0xA0000000, 0x00000000, 0x03F, 0x000C0F4E, + 0xB0000000, 0x00000000, 0x033, 0x00000001, 0x03E, 0x00000034, 0x03F, 0x0004080E, @@ -155,28 +162,91 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x0EF, 0x00080000, 0x033, 0x00000025, 0x03E, 0x00000037, - 0x03F, 0x0006EFCE, + 0x03F, 0x0007EFCE, 0x0EF, 0x00000000, 0x0EF, 0x00080000, 0x033, 0x00000026, 0x03E, 0x00000037, - 0x03F, 0x0005EFCE, + 0x03F, 0x000DEFCE, 0x0EF, 0x00000000, - 0x8000200f, 0x00000000, 0x40000000, 0x00000000, + 0x07F, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, 0xA0000000, 0x00000000, 0x0B0, 0x000FF0F8, 0xB0000000, 0x00000000, 0x0B1, 0x0007DBE4, 0x0B2, 0x000225D1, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, 0x0B3, 0x000FC760, - 0x0B4, 0x00099DD4, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x0B3, 0x000FC760, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x0B3, 0x000FC760, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x0B3, 0x0007C330, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x0B3, 0x000FC760, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x0B3, 0x000FC760, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x0B3, 0x000FC760, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x0B3, 0x000FC760, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x0B3, 0x000FC760, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0B3, 0x000FC760, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x0B3, 0x000FC760, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x0B3, 0x000FC760, + 0xA0000000, 0x00000000, + 0x0B3, 0x000FC760, + 0xB0000000, 0x00000000, + 0x0B4, 0x00099DD0, 0x0B5, 0x000400FC, 0x0B6, 0x000187F0, 0x0B7, 0x00030018, @@ -184,7 +254,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x0B9, 0x00000000, 0x0BA, 0x00008000, 0x0BB, 0x00000000, - 0x0BC, 0x00040000, + 0x0BC, 0x00040030, 0x0BD, 0x00000000, 0x0BE, 0x00000000, 0x0BF, 0x00000000, @@ -197,7 +267,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x0C6, 0x00040299, 0x0C7, 0x00055555, 0x0C8, 0x0000C16C, - 0x0C9, 0x0001C140, + 0x0C9, 0x0001C146, 0x0CA, 0x00000000, 0x0CB, 0x00000000, 0x0CC, 0x00000000, @@ -207,111 +277,337 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x0DF, 0x00000009, 0x018, 0x00010524, 0x089, 0x00000207, - 0x8000100f, 0x05050505, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, 0x08A, 0x000FE186, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FE186, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FE186, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, 0xA0000000, 0x00000000, 0x08A, 0x000FF186, 0xB0000000, 0x00000000, 0x08B, 0x00061E3C, 0x08C, 0x000112C7, 0x08D, 0x000F4988, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0xA0000000, 0x00000000, 0x08E, 0x00064D40, - 0xB0000000, 0x00000000, 0x0EF, 0x00020000, 0x033, 0x00000007, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, 0xA0000000, 0x00000000, 0x03E, 0x00004000, 0xB0000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000DFF86, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000DFF86, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0xA0000000, 0x00000000, + 0x03F, 0x000C3186, + 0xB0000000, 0x00000000, 0x033, 0x00000006, - 0x8000100f, 0x05050505, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, 0xA0000000, 0x00000000, 0x03E, 0x00004080, 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000005, - 0x8000100f, 0x05050505, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000040C8, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000040C8, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000040C8, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000040C8, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000040C8, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004084, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000040C8, 0xA0000000, 0x00000000, 0x03E, 0x000040C8, 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000004, - 0x8000100f, 0x05050505, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004190, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004190, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004190, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004190, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004190, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004108, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004190, 0xA0000000, 0x00000000, 0x03E, 0x00004190, 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000003, - 0x8000100f, 0x05050505, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004998, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004998, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004998, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004998, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004998, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x0000490C, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004998, 0xA0000000, 0x00000000, 0x03E, 0x00004998, 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000002, - 0x8000100f, 0x05050505, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00005840, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00005840, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00005840, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00005840, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00005840, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00005E00, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00005840, 0xA0000000, 0x00000000, 0x03E, 0x00005840, 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000001, - 0x8000100f, 0x05050505, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000058C2, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000058C2, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000058C2, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000058C2, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000058C2, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00005862, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000058C2, 0xA0000000, 0x00000000, 0x03E, 0x000058C2, 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000000, - 0x8000100f, 0x05050505, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00005930, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00005930, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00005930, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00005930, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00005930, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00005948, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00005930, 0xA0000000, 0x00000000, 0x03E, 0x00005930, 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x0000000F, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004080, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, 0xA0000000, 0x00000000, 0x03E, 0x00004000, 0xB0000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000DFF86, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000DFF86, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0xA0000000, 0x00000000, + 0x03F, 0x000C3186, + 0xB0000000, 0x00000000, 0x033, 0x0000000E, 0x03E, 0x00004080, 0x03F, 0x000C3186, @@ -334,20 +630,88 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03E, 0x00005930, 0x03F, 0x000C3186, 0x033, 0x00000017, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004080, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, 0xA0000000, 0x00000000, 0x03E, 0x00004000, 0xB0000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0xA0000000, 0x00000000, + 0x03F, 0x000C3186, + 0xB0000000, 0x00000000, 0x033, 0x00000016, 0x03E, 0x00004080, 0x03F, 0x000C3186, @@ -372,26 +736,78 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x0EF, 0x00000000, 0x0EF, 0x00004000, 0x033, 0x00000000, - 0x8000100f, 0x05050505, 0x40000000, 0x00000000, - 0x03F, 0x0000000E, - 0xA0000000, 0x00000000, 0x03F, 0x0000000A, - 0xB0000000, 0x00000000, 0x033, 0x00000001, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00000000, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000006, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0xA0000000, 0x00000000, + 0x03F, 0x00000005, + 0xB0000000, 0x00000000, 0x033, 0x00000002, 0x03F, 0x00000000, 0x0EF, 0x00000000, 0x018, 0x00000401, 0x084, 0x00001209, 0x086, 0x000001A0, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x087, 0x00068080, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, 0x087, 0x00068080, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x087, 0x00068080, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x087, 0x00068080, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x087, 0x00068080, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x087, 0x00068080, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x087, 0x00068080, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x087, 0x00068080, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x087, 0x00068080, 0xA0000000, 0x00000000, 0x087, 0x000E8180, @@ -433,9 +849,15 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00000008, 0x0EF, 0x00000000, 0x0B8, 0x00080A00, + 0x0FE, 0x00000000, 0x0B0, 0x000FF0FA, + 0x0FE, 0x00000000, + 0x0FE, 0x00000000, 0x0CA, 0x00080000, + 0x0FE, 0x00000000, 0x0C9, 0x0001C141, + 0x0FE, 0x00000000, + 0x0FE, 0x00000000, 0x0B0, 0x000FF0F8, 0x018, 0x00018D24, 0xFFE, 0x00000000, @@ -443,7 +865,6 @@ u4Byte Array_MP_8822B_RadioA[] = { 0xFFE, 0x00000000, 0xFFE, 0x00000000, 0x018, 0x00010D24, - 0x80002100, 0x00000000, 0x40000000, 0x00000000, 0x01B, 0x00075A40, 0x0EE, 0x00000002, 0x033, 0x00000000, @@ -457,97 +878,331 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x033, 0x00000004, 0x03F, 0x00000004, 0x033, 0x00000005, - 0x03F, 0x00000004, + 0x03F, 0x00000006, 0x033, 0x00000006, - 0x03F, 0x00000000, + 0x03F, 0x00000004, 0x033, 0x00000007, - 0x03F, 0x00000022, + 0x03F, 0x00000000, 0x0EE, 0x00000000, - 0xA0000000, 0x00000000, - 0x01B, 0x00075A40, - 0x0EE, 0x00000002, - 0x033, 0x00000000, - 0x03F, 0x00000004, - 0x033, 0x00000001, - 0x03F, 0x00000004, - 0x033, 0x00000002, - 0x03F, 0x00000004, - 0x033, 0x00000003, - 0x03F, 0x00000004, - 0x033, 0x00000004, - 0x03F, 0x00000004, - 0x033, 0x00000005, - 0x03F, 0x00000004, - 0x033, 0x00000006, - 0x03F, 0x00000004, - 0x033, 0x00000007, - 0x03F, 0x00000004, - 0x0EE, 0x00000000, - 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D3D1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000062, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D301, + 0x062, 0x0000D303, + 0x063, 0x00000002, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000062, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D301, + 0x062, 0x0000D303, + 0x063, 0x00000002, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D301, + 0x062, 0x0000D303, + 0x063, 0x00000002, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D3D1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D3D1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D301, + 0x062, 0x0000D303, + 0x063, 0x00000002, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D3D1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D3D1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000062, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D301, 0x062, 0x0000D303, 0x063, 0x00000002, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000062, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D301, 0x062, 0x0000D303, 0x063, 0x00000002, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D4A0, + 0x062, 0x0000D203, + 0x063, 0x00000062, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D4A0, + 0x062, 0x0000D203, + 0x063, 0x00000062, 0xA0000000, 0x00000000, 0x061, 0x0005D3D0, 0x062, 0x0000D303, 0x063, 0x00000002, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200, - 0x030, 0x000004A0, - 0x030, 0x000014A0, - 0x030, 0x000024A0, - 0x030, 0x000034A0, - 0x030, 0x000044A0, - 0x030, 0x000054A0, - 0x030, 0x000064A0, - 0x030, 0x000074A0, - 0x030, 0x000084A0, - 0x030, 0x000094A0, - 0x030, 0x0000A4A0, - 0x030, 0x0000B4A0, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A3, + 0x030, 0x000093A3, + 0x030, 0x0000A3A3, + 0x030, 0x0000B3A3, 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200, - 0x030, 0x000004A0, - 0x030, 0x000014A0, - 0x030, 0x000024A0, - 0x030, 0x000034A0, - 0x030, 0x000044A0, - 0x030, 0x000054A0, - 0x030, 0x000064A0, - 0x030, 0x000074A0, - 0x030, 0x000084A0, - 0x030, 0x000094A0, - 0x030, 0x0000A4A0, - 0x030, 0x0000B4A0, + 0x030, 0x000004A3, + 0x030, 0x000014A3, + 0x030, 0x000024A3, + 0x030, 0x000034A3, + 0x030, 0x000044A3, + 0x030, 0x000054A3, + 0x030, 0x000064A3, + 0x030, 0x000074A3, + 0x030, 0x000084A3, + 0x030, 0x000094A3, + 0x030, 0x0000A4A3, + 0x030, 0x0000B4A3, + 0x0EF, 0x00000000, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000002A6, + 0x030, 0x000012A6, + 0x030, 0x000022A6, + 0x030, 0x000032A6, + 0x030, 0x000042A6, + 0x030, 0x000052A6, + 0x030, 0x000062A6, + 0x030, 0x000072A6, + 0x030, 0x000082A6, + 0x030, 0x000092A6, + 0x030, 0x0000A2A6, + 0x030, 0x0000B2A6, + 0x0EF, 0x00000000, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x00000303, + 0x030, 0x00001303, + 0x030, 0x00002303, + 0x030, 0x00003303, + 0x030, 0x000043A4, + 0x030, 0x000053A4, + 0x030, 0x000063A4, + 0x030, 0x000073A4, + 0x030, 0x00008365, + 0x030, 0x00009365, + 0x030, 0x0000A365, + 0x030, 0x0000B365, + 0x0EF, 0x00000000, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000002A6, + 0x030, 0x000012A6, + 0x030, 0x000022A6, + 0x030, 0x000032A6, + 0x030, 0x000042A6, + 0x030, 0x000052A6, + 0x030, 0x000062A6, + 0x030, 0x000072A6, + 0x030, 0x000082A6, + 0x030, 0x000092A6, + 0x030, 0x0000A2A6, + 0x030, 0x0000B2A6, + 0x0EF, 0x00000000, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000003A3, + 0x030, 0x000013A3, + 0x030, 0x000023A3, + 0x030, 0x000033A3, + 0x030, 0x00004355, + 0x030, 0x00005355, + 0x030, 0x00006355, + 0x030, 0x00007355, + 0x030, 0x00008314, + 0x030, 0x00009314, + 0x030, 0x0000A314, + 0x030, 0x0000B314, + 0x0EF, 0x00000000, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000004A3, + 0x030, 0x000014A3, + 0x030, 0x000024A3, + 0x030, 0x000034A3, + 0x030, 0x000044A3, + 0x030, 0x000054A3, + 0x030, 0x000064A3, + 0x030, 0x000074A3, + 0x030, 0x000084A3, + 0x030, 0x000094A3, + 0x030, 0x0000A4A3, + 0x030, 0x0000B4A3, 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000004A3, + 0x030, 0x000014A3, + 0x030, 0x000024A3, + 0x030, 0x000034A3, + 0x030, 0x000044A3, + 0x030, 0x000054A3, + 0x030, 0x000064A3, + 0x030, 0x000074A3, + 0x030, 0x000084A3, + 0x030, 0x000094A3, + 0x030, 0x0000A4A3, + 0x030, 0x0000B4A3, + 0x0EF, 0x00000000, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x00000384, + 0x030, 0x00001384, + 0x030, 0x00002384, + 0x030, 0x00003384, + 0x030, 0x00004425, + 0x030, 0x00005425, + 0x030, 0x00006425, + 0x030, 0x00007425, + 0x030, 0x000084A6, + 0x030, 0x000094A6, + 0x030, 0x0000A4A6, + 0x030, 0x0000B4A6, + 0x0EF, 0x00000000, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x00000463, + 0x030, 0x00001463, + 0x030, 0x00002463, + 0x030, 0x00003463, + 0x030, 0x00004545, + 0x030, 0x00005545, + 0x030, 0x00006545, + 0x030, 0x00007545, + 0x030, 0x00008565, + 0x030, 0x00009565, + 0x030, 0x0000A565, + 0x030, 0x0000B565, + 0x0EF, 0x00000000, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A3, + 0x030, 0x000093A3, + 0x030, 0x0000A3A3, + 0x030, 0x0000B3A3, + 0x0EF, 0x00000000, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000004A3, + 0x030, 0x000014A3, + 0x030, 0x000024A3, + 0x030, 0x000034A3, + 0x030, 0x000044A3, + 0x030, 0x000054A3, + 0x030, 0x000064A3, + 0x030, 0x000074A3, + 0x030, 0x000084A3, + 0x030, 0x000094A3, + 0x030, 0x0000A4A3, + 0x030, 0x0000B4A3, + 0x0EF, 0x00000000, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x00000443, + 0x030, 0x00001443, + 0x030, 0x00002443, + 0x030, 0x00003443, + 0x030, 0x000043A4, + 0x030, 0x000053A4, + 0x030, 0x000063A4, + 0x030, 0x000073A4, + 0x030, 0x00008365, + 0x030, 0x00009365, + 0x030, 0x0000A365, + 0x030, 0x0000B365, + 0x0EF, 0x00000000, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x00000443, + 0x030, 0x00001443, + 0x030, 0x00002443, + 0x030, 0x00003443, + 0x030, 0x00004383, + 0x030, 0x00005383, + 0x030, 0x00006383, + 0x030, 0x00007383, + 0x030, 0x000084A4, + 0x030, 0x000094A4, + 0x030, 0x0000A4A4, + 0x030, 0x0000B4A4, + 0x0EF, 0x00000000, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x00000363, + 0x030, 0x00001363, + 0x030, 0x00002363, + 0x030, 0x00003363, + 0x030, 0x000043A3, + 0x030, 0x000053A3, + 0x030, 0x000063A3, + 0x030, 0x000073A3, + 0x030, 0x000084A4, + 0x030, 0x000094A4, + 0x030, 0x0000A4A4, + 0x030, 0x0000B4A4, + 0x0EF, 0x00000000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000004A0, 0x030, 0x000014A0, @@ -562,7 +1217,67 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x030, 0x0000A4A0, 0x030, 0x0000B4A0, 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000002A1, + 0x030, 0x000012A1, + 0x030, 0x000022A1, + 0x030, 0x000032A1, + 0x030, 0x000042A1, + 0x030, 0x000052A1, + 0x030, 0x000062A1, + 0x030, 0x000072A1, + 0x030, 0x000082A1, + 0x030, 0x000092A1, + 0x030, 0x0000A2A1, + 0x030, 0x0000B2A1, + 0x0EF, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000003A0, + 0x030, 0x000013A0, + 0x030, 0x000023A0, + 0x030, 0x000033A0, + 0x030, 0x000043A1, + 0x030, 0x000053A1, + 0x030, 0x000063A1, + 0x030, 0x000073A1, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x0EF, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000002A1, + 0x030, 0x000012A1, + 0x030, 0x000022A1, + 0x030, 0x000032A1, + 0x030, 0x000042A1, + 0x030, 0x000052A1, + 0x030, 0x000062A1, + 0x030, 0x000072A1, + 0x030, 0x000082A1, + 0x030, 0x000092A1, + 0x030, 0x0000A2A1, + 0x030, 0x0000B2A1, + 0x0EF, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000003A0, + 0x030, 0x000013A0, + 0x030, 0x000023A0, + 0x030, 0x000033A0, + 0x030, 0x00004430, + 0x030, 0x00005430, + 0x030, 0x00006430, + 0x030, 0x00007430, + 0x030, 0x00008372, + 0x030, 0x00009372, + 0x030, 0x0000A372, + 0x030, 0x0000B372, + 0x0EF, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000004A0, 0x030, 0x000014A0, @@ -577,7 +1292,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x030, 0x0000A4A0, 0x030, 0x0000B4A0, 0x0EF, 0x00000000, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000004A0, 0x030, 0x000014A0, @@ -592,36 +1307,6 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x030, 0x0000A4A0, 0x030, 0x0000B4A0, 0x0EF, 0x00000000, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000200, - 0x030, 0x000003A0, - 0x030, 0x000013A0, - 0x030, 0x000023A0, - 0x030, 0x000033A0, - 0x030, 0x00004430, - 0x030, 0x00005430, - 0x030, 0x00006430, - 0x030, 0x00007430, - 0x030, 0x00008372, - 0x030, 0x00009372, - 0x030, 0x0000A372, - 0x030, 0x0000B372, - 0x0EF, 0x00000000, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000200, - 0x030, 0x000003A0, - 0x030, 0x000013A0, - 0x030, 0x000023A0, - 0x030, 0x000033A0, - 0x030, 0x000043A1, - 0x030, 0x000053A1, - 0x030, 0x000063A1, - 0x030, 0x000073A1, - 0x030, 0x000083A2, - 0x030, 0x000093A2, - 0x030, 0x0000A3A2, - 0x030, 0x0000B3A2, - 0x0EF, 0x00000000, 0xA0000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000003D0, @@ -638,67 +1323,21 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x030, 0x0000B3D0, 0x0EF, 0x00000000, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, - 0x0EF, 0x00000080, - 0x030, 0x00000203, - 0x030, 0x00001203, - 0x030, 0x00002203, - 0x030, 0x00003203, - 0x030, 0x00004203, - 0x030, 0x00005203, - 0x030, 0x00006203, - 0x030, 0x00007203, - 0x030, 0x00008203, - 0x030, 0x00009203, - 0x030, 0x0000A203, - 0x030, 0x0000B203, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x0EF, 0x00000080, - 0x030, 0x00000203, - 0x030, 0x00001203, - 0x030, 0x00002203, - 0x030, 0x00003203, - 0x030, 0x00004203, - 0x030, 0x00005203, - 0x030, 0x00006203, - 0x030, 0x00007203, - 0x030, 0x00008203, - 0x030, 0x00009203, - 0x030, 0x0000A203, - 0x030, 0x0000B203, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000080, - 0x030, 0x00000203, - 0x030, 0x00001203, - 0x030, 0x00002203, - 0x030, 0x00003203, - 0x030, 0x00004203, - 0x030, 0x00005203, - 0x030, 0x00006203, - 0x030, 0x00007203, - 0x030, 0x00008203, - 0x030, 0x00009203, - 0x030, 0x0000A203, - 0x030, 0x0000B203, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000080, - 0x030, 0x00000203, - 0x030, 0x00001203, - 0x030, 0x00002203, - 0x030, 0x00003203, - 0x030, 0x00004203, - 0x030, 0x00005203, - 0x030, 0x00006203, - 0x030, 0x00007203, - 0x030, 0x00008203, - 0x030, 0x00009203, - 0x030, 0x0000A203, - 0x030, 0x0000B203, - 0x0EF, 0x00000000, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203, @@ -712,8 +1351,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x030, 0x00009203, 0x030, 0x0000A203, 0x030, 0x0000B203, - 0x0EF, 0x00000000, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2, @@ -727,8 +1365,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, - 0x0EF, 0x00000000, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2, @@ -742,8 +1379,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2, @@ -757,18 +1393,269 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, - 0x0EF, 0x00000040, - 0x030, 0x00000645, - 0x030, 0x00001333, - 0x030, 0x00002011, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x00000203, + 0x030, 0x00001203, + 0x030, 0x00002203, + 0x030, 0x00003203, + 0x030, 0x00004203, + 0x030, 0x00005203, + 0x030, 0x00006203, + 0x030, 0x00007203, + 0x030, 0x00008203, + 0x030, 0x00009203, + 0x030, 0x0000A203, + 0x030, 0x0000B203, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x00000203, + 0x030, 0x00001203, + 0x030, 0x00002203, + 0x030, 0x00003203, + 0x030, 0x00004203, + 0x030, 0x00005203, + 0x030, 0x00006203, + 0x030, 0x00007203, + 0x030, 0x00008203, + 0x030, 0x00009203, + 0x030, 0x0000A203, + 0x030, 0x0000B203, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A3, + 0x030, 0x000013A3, + 0x030, 0x000023A3, + 0x030, 0x000033A3, + 0x030, 0x000043A3, + 0x030, 0x000053A3, + 0x030, 0x000063A3, + 0x030, 0x000073A3, + 0x030, 0x000083A3, + 0x030, 0x000093A3, + 0x030, 0x0000A3A3, + 0x030, 0x0000B3A3, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x00000203, + 0x030, 0x00001203, + 0x030, 0x00002203, + 0x030, 0x00003203, + 0x030, 0x00004203, + 0x030, 0x00005203, + 0x030, 0x00006203, + 0x030, 0x00007203, + 0x030, 0x00008203, + 0x030, 0x00009203, + 0x030, 0x0000A203, + 0x030, 0x0000B203, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x00000203, + 0x030, 0x00001203, + 0x030, 0x00002203, + 0x030, 0x00003203, + 0x030, 0x00004203, + 0x030, 0x00005203, + 0x030, 0x00006203, + 0x030, 0x00007203, + 0x030, 0x00008203, + 0x030, 0x00009203, + 0x030, 0x0000A203, + 0x030, 0x0000B203, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x00000203, + 0x030, 0x00001203, + 0x030, 0x00002203, + 0x030, 0x00003203, + 0x030, 0x00004203, + 0x030, 0x00005203, + 0x030, 0x00006203, + 0x030, 0x00007203, + 0x030, 0x00008203, + 0x030, 0x00009203, + 0x030, 0x0000A203, + 0x030, 0x0000B203, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x00000203, + 0x030, 0x00001203, + 0x030, 0x00002203, + 0x030, 0x00003203, + 0x030, 0x00004203, + 0x030, 0x00005203, + 0x030, 0x00006203, + 0x030, 0x00007203, + 0x030, 0x00008203, + 0x030, 0x00009203, + 0x030, 0x0000A203, + 0x030, 0x0000B203, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000764, + 0x030, 0x00001632, + 0x030, 0x00002421, 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645, 0x030, 0x00001333, @@ -776,17 +1663,39 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645, 0x030, 0x00001333, 0x030, 0x00002011, - 0x030, 0x00004000, - 0x030, 0x00005000, - 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000777, + 0x030, 0x00001442, + 0x030, 0x00002222, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000776, + 0x030, 0x00001455, + 0x030, 0x00002325, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645, 0x030, 0x00001333, @@ -794,8 +1703,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645, 0x030, 0x00001333, @@ -803,25 +1711,118 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000040, - 0x030, 0x00000775, - 0x030, 0x00001343, - 0x030, 0x00002210, + 0x030, 0x00000660, + 0x030, 0x00001443, + 0x030, 0x00002221, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000764, + 0x030, 0x00001632, + 0x030, 0x00002421, 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000040, - 0x030, 0x00000775, - 0x030, 0x00001422, - 0x030, 0x00002210, - 0x030, 0x00004000, + 0x030, 0x00000764, + 0x030, 0x00001632, + 0x030, 0x00002421, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000767, + 0x030, 0x00001442, + 0x030, 0x00002222, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000767, + 0x030, 0x00001632, + 0x030, 0x00002451, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000764, + 0x030, 0x00001632, + 0x030, 0x00002421, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000775, + 0x030, 0x00001422, + 0x030, 0x00002210, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000775, + 0x030, 0x00001343, + 0x030, 0x00002210, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, 0xA0000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000764, @@ -830,26 +1831,171 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0xA0000000, 0x00000000, + 0x0EF, 0x00000000, 0x0EF, 0x00000800, - 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000C09, + 0x033, 0x00000021, + 0x03F, 0x00000C0C, + 0x033, 0x00000022, + 0x03F, 0x00000C0F, + 0x033, 0x00000023, + 0x03F, 0x00000C2C, + 0x033, 0x00000024, + 0x03F, 0x00000C2F, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000C90, + 0x033, 0x00000028, + 0x03F, 0x00000CD0, + 0x033, 0x00000029, + 0x03F, 0x00000CF2, + 0x033, 0x0000002A, + 0x03F, 0x00000CF5, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000007, + 0x033, 0x00000021, + 0x03F, 0x0000000A, + 0x033, 0x00000022, + 0x03F, 0x0000000D, + 0x033, 0x00000023, + 0x03F, 0x0000002A, + 0x033, 0x00000024, + 0x03F, 0x0000002D, + 0x033, 0x00000025, + 0x03F, 0x00000030, + 0x033, 0x00000026, + 0x03F, 0x0000006D, + 0x033, 0x00000027, + 0x03F, 0x00000070, + 0x033, 0x00000028, + 0x03F, 0x000000ED, + 0x033, 0x00000029, + 0x03F, 0x000000F0, + 0x033, 0x0000002A, + 0x03F, 0x000000F3, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000005, + 0x033, 0x00000021, + 0x03F, 0x00000008, + 0x033, 0x00000022, + 0x03F, 0x0000000B, + 0x033, 0x00000023, + 0x03F, 0x0000000E, + 0x033, 0x00000024, + 0x03F, 0x0000002B, + 0x033, 0x00000025, + 0x03F, 0x00000068, + 0x033, 0x00000026, + 0x03F, 0x0000006B, + 0x033, 0x00000027, + 0x03F, 0x0000006E, + 0x033, 0x00000028, + 0x03F, 0x00000071, + 0x033, 0x00000029, + 0x03F, 0x00000074, + 0x033, 0x0000002A, + 0x03F, 0x00000077, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000429, + 0x033, 0x00000021, + 0x03F, 0x00000828, + 0x033, 0x00000022, + 0x03F, 0x00000847, + 0x033, 0x00000023, + 0x03F, 0x0000084A, + 0x033, 0x00000024, + 0x03F, 0x00000C4B, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000CEA, + 0x033, 0x00000027, + 0x03F, 0x00000CED, + 0x033, 0x00000028, + 0x03F, 0x00000CF0, + 0x033, 0x00000029, + 0x03F, 0x00000CF3, + 0x033, 0x0000002A, + 0x03F, 0x00000CF6, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000005, + 0x033, 0x00000021, + 0x03F, 0x00000008, + 0x033, 0x00000022, + 0x03F, 0x0000000B, + 0x033, 0x00000023, + 0x03F, 0x0000000E, + 0x033, 0x00000024, + 0x03F, 0x0000002B, + 0x033, 0x00000025, + 0x03F, 0x00000068, + 0x033, 0x00000026, + 0x03F, 0x0000006B, + 0x033, 0x00000027, + 0x03F, 0x0000006E, + 0x033, 0x00000028, + 0x03F, 0x00000071, + 0x033, 0x00000029, + 0x03F, 0x00000074, + 0x033, 0x0000002A, + 0x03F, 0x00000077, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x0000042B, + 0x033, 0x00000021, + 0x03F, 0x0000082A, + 0x033, 0x00000022, + 0x03F, 0x00000849, + 0x033, 0x00000023, + 0x03F, 0x0000084C, + 0x033, 0x00000024, + 0x03F, 0x00000C4C, + 0x033, 0x00000025, + 0x03F, 0x00000CA9, + 0x033, 0x00000026, + 0x03F, 0x00000CEA, + 0x033, 0x00000027, + 0x03F, 0x00000CED, + 0x033, 0x00000028, + 0x03F, 0x00000CF0, + 0x033, 0x00000029, + 0x03F, 0x00000CF3, + 0x033, 0x0000002A, + 0x03F, 0x00000CF6, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000007, + 0x033, 0x00000021, + 0x03F, 0x0000000A, + 0x033, 0x00000022, + 0x03F, 0x0000000D, + 0x033, 0x00000023, + 0x03F, 0x0000002A, + 0x033, 0x00000024, + 0x03F, 0x0000002D, + 0x033, 0x00000025, + 0x03F, 0x00000030, + 0x033, 0x00000026, + 0x03F, 0x0000006D, + 0x033, 0x00000027, + 0x03F, 0x00000070, + 0x033, 0x00000028, + 0x03F, 0x000000ED, + 0x033, 0x00000029, + 0x03F, 0x000000F0, + 0x033, 0x0000002A, + 0x03F, 0x000000F3, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021, @@ -872,378 +2018,1228 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000C0C, + 0x033, 0x00000021, + 0x03F, 0x00000C29, + 0x033, 0x00000022, + 0x03F, 0x00000C2C, + 0x033, 0x00000023, + 0x03F, 0x00000C69, + 0x033, 0x00000024, + 0x03F, 0x00000CA8, + 0x033, 0x00000025, + 0x03F, 0x00000CE8, + 0x033, 0x00000026, + 0x03F, 0x00000CEB, + 0x033, 0x00000027, + 0x03F, 0x00000CEE, + 0x033, 0x00000028, + 0x03F, 0x00000CF1, + 0x033, 0x00000029, + 0x03F, 0x00000CF4, + 0x033, 0x0000002A, + 0x03F, 0x00000CF7, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, + 0x03F, 0x00000C09, + 0x033, 0x00000021, + 0x03F, 0x00000C0C, + 0x033, 0x00000022, + 0x03F, 0x00000C0F, + 0x033, 0x00000023, + 0x03F, 0x00000C2C, + 0x033, 0x00000024, + 0x03F, 0x00000C2F, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000C90, + 0x033, 0x00000028, + 0x03F, 0x00000CD0, + 0x033, 0x00000029, + 0x03F, 0x00000CF2, + 0x033, 0x0000002A, + 0x03F, 0x00000CF5, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000C09, + 0x033, 0x00000021, + 0x03F, 0x00000C0C, + 0x033, 0x00000022, + 0x03F, 0x00000C0F, + 0x033, 0x00000023, + 0x03F, 0x00000C2C, + 0x033, 0x00000024, + 0x03F, 0x00000C2F, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000C90, + 0x033, 0x00000028, + 0x03F, 0x00000CD0, + 0x033, 0x00000029, + 0x03F, 0x00000CF2, + 0x033, 0x0000002A, + 0x03F, 0x00000CF5, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000007, + 0x033, 0x00000021, + 0x03F, 0x0000000A, + 0x033, 0x00000022, + 0x03F, 0x0000000D, + 0x033, 0x00000023, + 0x03F, 0x0000002A, + 0x033, 0x00000024, + 0x03F, 0x0000002D, + 0x033, 0x00000025, + 0x03F, 0x00000030, + 0x033, 0x00000026, + 0x03F, 0x0000006D, + 0x033, 0x00000027, + 0x03F, 0x00000070, + 0x033, 0x00000028, + 0x03F, 0x000000ED, + 0x033, 0x00000029, + 0x03F, 0x000000F0, + 0x033, 0x0000002A, + 0x03F, 0x000000F3, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000429, + 0x033, 0x00000021, + 0x03F, 0x00000828, + 0x033, 0x00000022, + 0x03F, 0x00000847, + 0x033, 0x00000023, + 0x03F, 0x0000084A, + 0x033, 0x00000024, + 0x03F, 0x00000C4B, + 0x033, 0x00000025, + 0x03F, 0x00000CE5, + 0x033, 0x00000026, + 0x03F, 0x00000CE8, + 0x033, 0x00000027, + 0x03F, 0x00000CEB, + 0x033, 0x00000028, + 0x03F, 0x00000CEE, + 0x033, 0x00000029, + 0x03F, 0x00000CF1, + 0x033, 0x0000002A, + 0x03F, 0x00000CF4, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000C0A, + 0x033, 0x00000021, + 0x03F, 0x00000C0D, + 0x033, 0x00000022, + 0x03F, 0x00000C2A, + 0x033, 0x00000023, + 0x03F, 0x00000C2D, + 0x033, 0x00000024, + 0x03F, 0x00000C6A, + 0x033, 0x00000025, + 0x03F, 0x00000CAA, + 0x033, 0x00000026, + 0x03F, 0x00000CAD, + 0x033, 0x00000027, + 0x03F, 0x00000CB0, + 0x033, 0x00000028, + 0x03F, 0x00000CF1, + 0x033, 0x00000029, + 0x03F, 0x00000CF4, + 0x033, 0x0000002A, + 0x03F, 0x00000CF7, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000C09, + 0x033, 0x00000021, + 0x03F, 0x00000C0C, + 0x033, 0x00000022, + 0x03F, 0x00000C0F, + 0x033, 0x00000023, + 0x03F, 0x00000C2C, + 0x033, 0x00000024, + 0x03F, 0x00000C2F, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000C90, + 0x033, 0x00000028, + 0x03F, 0x00000CD0, + 0x033, 0x00000029, + 0x03F, 0x00000CF2, + 0x033, 0x0000002A, + 0x03F, 0x00000CF5, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000007, + 0x033, 0x00000021, + 0x03F, 0x0000000A, + 0x033, 0x00000022, + 0x03F, 0x0000000D, + 0x033, 0x00000023, + 0x03F, 0x0000002A, + 0x033, 0x00000024, + 0x03F, 0x0000002D, + 0x033, 0x00000025, + 0x03F, 0x00000030, + 0x033, 0x00000026, + 0x03F, 0x0000006D, + 0x033, 0x00000027, + 0x03F, 0x00000070, + 0x033, 0x00000028, + 0x03F, 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0x000000A3, - 0x03F, 0x0000002A, + 0x03F, 0x00000C2C, 0x033, 0x000000A4, - 0x03F, 0x0000002D, + 0x03F, 0x00000C2F, 0x033, 0x000000A5, - 0x03F, 0x00000030, + 0x03F, 0x00000C8A, 0x033, 0x000000A6, - 0x03F, 0x0000006D, + 0x03F, 0x00000C8D, 0x033, 0x000000A7, - 0x03F, 0x00000070, + 0x03F, 0x00000C90, 0x033, 0x000000A8, - 0x03F, 0x000000ED, + 0x03F, 0x00000CEF, 0x033, 0x000000A9, - 0x03F, 0x000000F0, + 0x03F, 0x00000CF2, 0x033, 0x000000AA, - 0x03F, 0x000000F3, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x03F, 0x00000CF5, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x00000007, 0x033, 0x000000A1, @@ -1266,80 +3262,76 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x00000007, + 0x03F, 0x00000005, 0x033, 0x000000A1, - 0x03F, 0x0000000A, + 0x03F, 0x00000008, 0x033, 0x000000A2, - 0x03F, 0x0000000D, + 0x03F, 0x0000000B, 0x033, 0x000000A3, - 0x03F, 0x0000002A, + 0x03F, 0x0000000E, 0x033, 0x000000A4, - 0x03F, 0x0000002D, + 0x03F, 0x00000047, 0x033, 0x000000A5, - 0x03F, 0x00000030, + 0x03F, 0x0000004A, 0x033, 0x000000A6, - 0x03F, 0x0000006D, + 0x03F, 0x0000004D, 0x033, 0x000000A7, - 0x03F, 0x00000070, + 0x03F, 0x00000050, 0x033, 0x000000A8, - 0x03F, 0x000000ED, + 0x03F, 0x00000053, 0x033, 0x000000A9, - 0x03F, 0x000000F0, + 0x03F, 0x00000056, 0x033, 0x000000AA, - 0x03F, 0x000000F3, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000094, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x00000006, + 0x03F, 0x0000042A, 0x033, 0x000000A1, - 0x03F, 0x00000009, + 0x03F, 0x00000829, 0x033, 0x000000A2, - 0x03F, 0x0000000C, + 0x03F, 0x00000848, 0x033, 0x000000A3, - 0x03F, 0x00000029, + 0x03F, 0x0000084B, 0x033, 0x000000A4, - 0x03F, 0x0000002C, + 0x03F, 0x00000C4C, 0x033, 0x000000A5, - 0x03F, 0x0000004B, + 0x03F, 0x00000C8A, 0x033, 0x000000A6, - 0x03F, 0x00000448, + 0x03F, 0x00000C8D, 0x033, 0x000000A7, - 0x03F, 0x0000044B, + 0x03F, 0x00000CEB, 0x033, 0x000000A8, - 0x03F, 0x0000084B, + 0x03F, 0x00000CEE, 0x033, 0x000000A9, - 0x03F, 0x0000086B, + 0x03F, 0x00000CF1, 0x033, 0x000000AA, - 0x03F, 0x0000086E, - 0x0EF, 0x00000000, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000CF4, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x00000006, + 0x03F, 0x00000005, 0x033, 0x000000A1, - 0x03F, 0x00000009, + 0x03F, 0x00000008, 0x033, 0x000000A2, - 0x03F, 0x0000000C, + 0x03F, 0x0000000B, 0x033, 0x000000A3, - 0x03F, 0x00000029, + 0x03F, 0x0000000E, 0x033, 0x000000A4, - 0x03F, 0x0000002C, + 0x03F, 0x00000047, 0x033, 0x000000A5, - 0x03F, 0x0000004B, + 0x03F, 0x0000004A, 0x033, 0x000000A6, - 0x03F, 0x00000448, + 0x03F, 0x0000004D, 0x033, 0x000000A7, - 0x03F, 0x0000044B, + 0x03F, 0x00000050, 0x033, 0x000000A8, - 0x03F, 0x0000084B, + 0x03F, 0x00000053, 0x033, 0x000000A9, - 0x03F, 0x0000086B, + 0x03F, 0x00000056, 0x033, 0x000000AA, - 0x03F, 0x0000086E, - 0x0EF, 0x00000000, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000094, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x0000042A, 0x033, 0x000000A1, @@ -1362,31 +3354,52 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00000CF1, 0x033, 0x000000AA, 0x03F, 0x00000CF4, - 0x0EF, 0x00000000, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x0000042A, + 0x03F, 0x00000007, 0x033, 0x000000A1, - 0x03F, 0x00000829, + 0x03F, 0x0000000A, 0x033, 0x000000A2, - 0x03F, 0x00000848, + 0x03F, 0x0000000D, 0x033, 0x000000A3, - 0x03F, 0x0000084B, + 0x03F, 0x0000002A, 0x033, 0x000000A4, - 0x03F, 0x00000C4C, + 0x03F, 0x0000002D, 0x033, 0x000000A5, - 0x03F, 0x00000C8A, + 0x03F, 0x00000030, 0x033, 0x000000A6, - 0x03F, 0x00000C8D, + 0x03F, 0x0000006D, 0x033, 0x000000A7, - 0x03F, 0x00000CEB, + 0x03F, 0x00000070, 0x033, 0x000000A8, - 0x03F, 0x00000CEE, + 0x03F, 0x000000ED, 0x033, 0x000000A9, - 0x03F, 0x00000CF1, + 0x03F, 0x000000F0, 0x033, 0x000000AA, - 0x03F, 0x00000CF4, - 0x0EF, 0x00000000, + 0x03F, 0x000000F3, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000007, + 0x033, 0x000000A1, + 0x03F, 0x0000000A, + 0x033, 0x000000A2, + 0x03F, 0x0000000D, + 0x033, 0x000000A3, + 0x03F, 0x0000002A, + 0x033, 0x000000A4, + 0x03F, 0x0000002D, + 0x033, 0x000000A5, + 0x03F, 0x00000030, + 0x033, 0x000000A6, + 0x03F, 0x0000006D, + 0x033, 0x000000A7, + 0x03F, 0x00000070, + 0x033, 0x000000A8, + 0x03F, 0x000000ED, + 0x033, 0x000000A9, + 0x03F, 0x000000F0, + 0x033, 0x000000AA, + 0x03F, 0x000000F3, 0xA0000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x00000C09, @@ -1410,10 +3423,10 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5, - 0x0EF, 0x00000000, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x0EF, 0x00000000, 0x0EF, 0x00000400, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000047C, 0x033, 0x00000001, @@ -1422,9 +3435,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x0000047C, 0x033, 0x00000003, 0x03F, 0x0000047C, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x0EF, 0x00000400, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000047C, 0x033, 0x00000001, @@ -1433,9 +3444,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x0000047C, 0x033, 0x00000003, 0x03F, 0x0000047C, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000400, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000047C, 0x033, 0x00000001, @@ -1444,9 +3453,61 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x0000047C, 0x033, 0x00000003, 0x03F, 0x0000047C, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000400, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0000047C, + 0x033, 0x00000001, + 0x03F, 0x0000047C, + 0x033, 0x00000002, + 0x03F, 0x0000047C, + 0x033, 0x00000003, + 0x03F, 0x0000047C, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0000047C, + 0x033, 0x00000001, + 0x03F, 0x0000047C, + 0x033, 0x00000002, + 0x03F, 0x0000047C, + 0x033, 0x00000003, + 0x03F, 0x0000047C, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x000008BB, + 0x033, 0x00000001, + 0x03F, 0x000008BB, + 0x033, 0x00000002, + 0x03F, 0x000008BB, + 0x033, 0x00000003, + 0x03F, 0x000008BB, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0000047C, + 0x033, 0x00000001, + 0x03F, 0x0000047C, + 0x033, 0x00000002, + 0x03F, 0x0000047C, + 0x033, 0x00000003, + 0x03F, 0x0000047C, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0000047C, + 0x033, 0x00000001, + 0x03F, 0x0000047C, + 0x033, 0x00000002, + 0x03F, 0x0000047C, + 0x033, 0x00000003, + 0x03F, 0x0000047C, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0000047C, + 0x033, 0x00000001, + 0x03F, 0x0000047C, + 0x033, 0x00000002, + 0x03F, 0x0000047C, + 0x033, 0x00000003, + 0x03F, 0x0000047C, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000047C, 0x033, 0x00000001, @@ -1455,9 +3516,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x0000047C, 0x033, 0x00000003, 0x03F, 0x0000047C, - 0x0EF, 0x00000000, 0xA0000000, 0x00000000, - 0x0EF, 0x00000400, 0x033, 0x00000000, 0x03F, 0x000004BB, 0x033, 0x00000001, @@ -1466,10 +3525,10 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x000004BB, 0x033, 0x00000003, 0x03F, 0x000004BB, - 0x0EF, 0x00000000, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x0EF, 0x00000000, 0x0EF, 0x00000100, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00001726, 0x033, 0x00000001, @@ -1478,9 +3537,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00001726, 0x033, 0x00000003, 0x03F, 0x00001726, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00001726, 0x033, 0x00000001, @@ -1489,9 +3546,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00001726, 0x033, 0x00000003, 0x03F, 0x00001726, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00001726, 0x033, 0x00000001, @@ -1500,9 +3555,52 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00001726, 0x033, 0x00000003, 0x03F, 0x00001726, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00001726, + 0x033, 0x00000001, + 0x03F, 0x00001726, + 0x033, 0x00000002, + 0x03F, 0x00001726, + 0x033, 0x00000003, + 0x03F, 0x00001726, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00001726, + 0x033, 0x00000001, + 0x03F, 0x00001726, + 0x033, 0x00000002, + 0x03F, 0x00001726, + 0x033, 0x00000003, + 0x03F, 0x00001726, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00001726, + 0x033, 0x00000001, + 0x03F, 0x00001726, + 0x033, 0x00000002, + 0x03F, 0x00001726, + 0x033, 0x00000003, + 0x03F, 0x00001726, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00001726, + 0x033, 0x00000001, + 0x03F, 0x00001726, + 0x033, 0x00000002, + 0x03F, 0x00001726, + 0x033, 0x00000003, + 0x03F, 0x00001726, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00001726, + 0x033, 0x00000001, + 0x03F, 0x00001726, + 0x033, 0x00000002, + 0x03F, 0x00001726, + 0x033, 0x00000003, + 0x03F, 0x00001726, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00001726, 0x033, 0x00000001, @@ -1511,9 +3609,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00001726, 0x033, 0x00000003, 0x03F, 0x00001726, - 0x0EF, 0x00000000, 0xA0000000, 0x00000000, - 0x0EF, 0x00000100, 0x033, 0x00000000, 0x03F, 0x00000F34, 0x033, 0x00000001, @@ -1522,9 +3618,59 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00000F34, 0x033, 0x00000003, 0x03F, 0x00000F34, - 0x0EF, 0x00000000, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x0EF, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x081, 0x0000F400, + 0x087, 0x00016040, + 0x051, 0x00000808, + 0x052, 0x00098002, + 0x053, 0x0000FA47, + 0x054, 0x00058032, + 0x056, 0x00051000, + 0x057, 0x0000CE0A, + 0x058, 0x00082030, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x081, 0x0000F400, + 0x087, 0x00016040, + 0x051, 0x00000808, + 0x052, 0x00098002, + 0x053, 0x0000FA47, + 0x054, 0x00058032, + 0x056, 0x00051000, + 0x057, 0x0000CE0A, + 0x058, 0x00082030, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x081, 0x0000F400, + 0x087, 0x00016040, + 0x051, 0x00000808, + 0x052, 0x00098002, + 0x053, 0x0000FA47, + 0x054, 0x00058032, + 0x056, 0x00051000, + 0x057, 0x0000CE0A, + 0x058, 0x00082030, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x081, 0x0000F400, + 0x087, 0x00016040, + 0x051, 0x00000808, + 0x052, 0x00098002, + 0x053, 0x0000FA47, + 0x054, 0x00058032, + 0x056, 0x00051000, + 0x057, 0x0000CE0A, + 0x058, 0x00082030, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x081, 0x0000F400, + 0x087, 0x00016040, + 0x051, 0x00000808, + 0x052, 0x00098002, + 0x053, 0x0000FA47, + 0x054, 0x00058032, + 0x056, 0x00051000, + 0x057, 0x0000CE0A, + 0x058, 0x00082030, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808, @@ -1534,7 +3680,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808, @@ -1544,7 +3690,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808, @@ -1554,7 +3700,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808, @@ -1574,8 +3720,8 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x057, 0x0000CE0A, 0x058, 0x00058750, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x0EF, 0x00000800, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003, 0x033, 0x00000001, @@ -1598,9 +3744,30 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000002, + 0x033, 0x00000001, + 0x03F, 0x00000005, + 0x033, 0x00000002, + 0x03F, 0x00000008, + 0x033, 0x00000003, + 0x03F, 0x0000000B, + 0x033, 0x00000004, + 0x03F, 0x0000000E, + 0x033, 0x00000005, + 0x03F, 0x0000002B, + 0x033, 0x00000006, + 0x03F, 0x0000002E, + 0x033, 0x00000007, + 0x03F, 0x00000031, + 0x033, 0x00000008, + 0x03F, 0x0000006E, + 0x033, 0x00000009, + 0x03F, 0x00000071, + 0x033, 0x0000000A, + 0x03F, 0x00000074, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003, 0x033, 0x00000001, @@ -1623,9 +3790,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003, 0x033, 0x00000001, @@ -1648,9 +3813,99 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003, 0x033, 0x00000001, @@ -1673,9 +3928,7 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C, - 0x0EF, 0x00000000, 0xA0000000, 0x00000000, - 0x0EF, 0x00000800, 0x033, 0x00000000, 0x03F, 0x0005142C, 0x033, 0x00000001, @@ -1698,8 +3951,8 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x03F, 0x00051CF4, 0x033, 0x0000000A, 0x03F, 0x00051CF7, - 0x0EF, 0x00000000, 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, 0x0EF, 0x00000010, 0x033, 0x00000000, 0x008, 0x0009C060, @@ -1709,96 +3962,147 @@ u4Byte Array_MP_8822B_RadioA[] = { 0x033, 0x000000A2, 0x0EF, 0x00080000, 0x03E, 0x0000593F, + 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000D0F4F, + 0xA0000000, 0x00000000, 0x03F, 0x000C0F4F, + 0xB0000000, 0x00000000, 0x0EF, 0x00000000, 0x033, 0x000000A3, 0x0EF, 0x00080000, 0x03E, 0x00005934, 0x03F, 0x0005AFCF, 0x0EF, 0x00000000, + 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00064700, + 0xA0000000, 0x00000000, + 0x0CF, 0x00064700, + 0xB0000000, 0x00000000, + 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000096, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000096, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x0B0, 0x000FF0FC, + 0x0C4, 0x00081402, + 0x0CC, 0x00080000, }; void -ODM_ReadAndConfig_MP_8822B_RadioA( - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_radioa( + struct PHY_DM_STRUCT *p_dm_odm ) { - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8822B_RadioA)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_RadioA; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_RadioA\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8822b_radioa)/sizeof(u32); + u32 *array = array_mp_8822b_radioa; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_radioa\n")); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped?false:true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; } else { - bMatched = FALSE; - bSkipped = FALSE; + is_matched = false; + is_skipped = false; } } else - bMatched = FALSE; + is_matched = false; } } else { - if (bMatched) - odm_ConfigRF_RadioA_8822B(pDM_Odm, v1, v2); + if (is_matched) + odm_config_rf_radio_a_8822b(p_dm_odm, v1, v2); } i = i + 2; } } -u4Byte -ODM_GetVersion_MP_8822B_RadioA(void) +u32 +odm_get_version_mp_8822b_radioa(void) { - return 50; + return 85; } /****************************************************************************** -* RadioB.TXT +* radiob.TXT ******************************************************************************/ -u4Byte Array_MP_8822B_RadioB[] = { +u32 array_mp_8822b_radiob[] = { 0x000, 0x00030000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x0004002D, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x0004002D, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x0004002D, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x0004002D, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x00040029, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x00040029, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x00040029, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x0004002D, 0xA0000000, 0x00000000, 0x001, 0x00040029, 0xB0000000, 0x00000000, @@ -1806,7 +4110,11 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x0EF, 0x00080000, 0x033, 0x00000002, 0x03E, 0x0000003F, + 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000D0F4E, + 0xA0000000, 0x00000000, 0x03F, 0x000C0F4E, + 0xB0000000, 0x00000000, 0x033, 0x00000001, 0x03E, 0x00000034, 0x03F, 0x0004080E, @@ -1819,57 +4127,103 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x0EF, 0x00080000, 0x033, 0x00000025, 0x03E, 0x00000037, - 0x03F, 0x0006EFCE, + 0x03F, 0x0007EFCE, 0x0EF, 0x00000000, 0x0EF, 0x00080000, 0x033, 0x00000026, 0x03E, 0x00000037, - 0x03F, 0x0005EFCE, + 0x03F, 0x000DEFCE, 0x0EF, 0x00000000, 0x0DF, 0x00000009, 0x018, 0x00010524, 0x089, 0x00000207, - 0x8000100f, 0x05050505, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FE186, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x08A, 0x000FE186, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x08A, 0x000FF186, 0xA0000000, 0x00000000, 0x08A, 0x000FF186, 0xB0000000, 0x00000000, 0x08B, 0x00061E3C, 0x08C, 0x000112C7, 0x08D, 0x000F4988, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x08E, 0x00064D40, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x08E, 0x00064D40, - 0xA0000000, 0x00000000, - 0x08E, 0x00064D40, - 0xB0000000, 0x00000000, 0x0EF, 0x00020000, 0x033, 0x00000007, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004080, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000DFF86, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x03F, 0x000C3186, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, + 0x03F, 0x000C3186, 0xA0000000, 0x00000000, 0x03E, 0x00004000, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, + 0xB0000000, 0x00000000, 0x033, 0x00000006, 0x03E, 0x00004080, 0x03F, 0x000C3186, @@ -1892,20 +4246,70 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03E, 0x00005930, 0x03F, 0x000C3186, 0x033, 0x0000000F, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004080, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x03F, 0x000C3186, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, + 0x03F, 0x000C3186, 0xA0000000, 0x00000000, 0x03E, 0x00004000, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, + 0xB0000000, 0x00000000, 0x033, 0x0000000E, 0x03E, 0x00004080, 0x03F, 0x000C3186, @@ -1918,30 +4322,80 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x033, 0x0000000B, 0x03E, 0x00004998, 0x03F, 0x000C3186, - 0x033, 0x0000000A, - 0x03E, 0x00005840, + 0x033, 0x0000000A, + 0x03E, 0x00005840, + 0x03F, 0x000C3186, + 0x033, 0x00000009, + 0x03E, 0x000058C2, + 0x03F, 0x000C3186, + 0x033, 0x00000008, + 0x03E, 0x00005930, + 0x03F, 0x000C3186, + 0x033, 0x00000017, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000DFF86, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x03F, 0x000C3186, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, + 0x03F, 0x000C3186, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C3186, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004040, 0x03F, 0x000C3186, - 0x033, 0x00000009, - 0x03E, 0x000058C2, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, 0x03F, 0x000C3186, - 0x033, 0x00000008, - 0x03E, 0x00005930, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, 0x03F, 0x000C3186, - 0x033, 0x00000017, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x03E, 0x00004080, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004080, + 0x03F, 0x000C3186, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, + 0x03F, 0x000C3186, 0xA0000000, 0x00000000, 0x03E, 0x00004000, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, + 0xB0000000, 0x00000000, 0x033, 0x00000016, 0x03E, 0x00004080, 0x03F, 0x000C3186, @@ -1968,20 +4422,76 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x033, 0x00000000, 0x03F, 0x0000000A, 0x033, 0x00000001, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000002, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000005, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0xA0000000, 0x00000000, + 0x03F, 0x00000005, + 0xB0000000, 0x00000000, 0x033, 0x00000002, 0x03F, 0x00000000, 0x0EF, 0x00000000, 0x018, 0x00000401, 0x084, 0x00001209, 0x086, 0x000001A0, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x087, 0x00068080, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x087, 0x00068080, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x087, 0x00068080, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x087, 0x00068080, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, 0x087, 0x00068080, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x087, 0x00068080, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x087, 0x00068080, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x087, 0x00068080, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x087, 0x00068080, 0xA0000000, 0x00000000, 0x087, 0x000E8180, @@ -2028,27 +4538,6 @@ u4Byte Array_MP_8822B_RadioB[] = { 0xFFE, 0x00000000, 0xFFE, 0x00000000, 0x018, 0x00010D24, - 0x80002100, 0x00000000, 0x40000000, 0x00000000, - 0x01B, 0x00075A40, - 0x0EE, 0x00000002, - 0x033, 0x00000000, - 0x03F, 0x00000004, - 0x033, 0x00000001, - 0x03F, 0x00000004, - 0x033, 0x00000002, - 0x03F, 0x00000004, - 0x033, 0x00000003, - 0x03F, 0x00000004, - 0x033, 0x00000004, - 0x03F, 0x00000004, - 0x033, 0x00000005, - 0x03F, 0x00000004, - 0x033, 0x00000006, - 0x03F, 0x00000000, - 0x033, 0x00000007, - 0x03F, 0x00000022, - 0x0EE, 0x00000000, - 0xA0000000, 0x00000000, 0x01B, 0x00075A40, 0x0EE, 0x00000002, 0x033, 0x00000000, @@ -2062,63 +4551,302 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x033, 0x00000004, 0x03F, 0x00000004, 0x033, 0x00000005, - 0x03F, 0x00000004, + 0x03F, 0x00000006, 0x033, 0x00000006, 0x03F, 0x00000004, 0x033, 0x00000007, - 0x03F, 0x00000004, + 0x03F, 0x00000000, 0x0EE, 0x00000000, - 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D3D1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000062, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000062, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D3D1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D3D1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D3D1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D3D1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000062, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, 0x063, 0x00000002, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000062, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, 0x063, 0x00000002, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D4A0, + 0x062, 0x0000D203, + 0x063, 0x00000062, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D4A0, + 0x062, 0x0000D203, + 0x063, 0x00000062, 0xA0000000, 0x00000000, 0x061, 0x0005D3D0, 0x062, 0x0000D303, 0x063, 0x00000002, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, - 0x0EF, 0x00000200, - 0x030, 0x000004A0, - 0x030, 0x000014A0, - 0x030, 0x000024A0, - 0x030, 0x000034A0, - 0x030, 0x000044A0, - 0x030, 0x000054A0, - 0x030, 0x000064A0, - 0x030, 0x000074A0, - 0x030, 0x000084A0, - 0x030, 0x000094A0, - 0x030, 0x0000A4A0, - 0x030, 0x0000B4A0, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x0EF, 0x00000200, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A3, + 0x030, 0x000053A3, + 0x030, 0x000063A3, + 0x030, 0x000073A3, + 0x030, 0x000083A3, + 0x030, 0x000093A3, + 0x030, 0x0000A3A3, + 0x030, 0x0000B3A3, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000004A3, + 0x030, 0x000014A3, + 0x030, 0x000024A3, + 0x030, 0x000034A3, + 0x030, 0x000044A3, + 0x030, 0x000054A3, + 0x030, 0x000064A3, + 0x030, 0x000074A3, + 0x030, 0x000084A3, + 0x030, 0x000094A3, + 0x030, 0x0000A4A3, + 0x030, 0x0000B4A3, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000002A6, + 0x030, 0x000012A6, + 0x030, 0x000022A6, + 0x030, 0x000032A6, + 0x030, 0x000042A6, + 0x030, 0x000052A6, + 0x030, 0x000062A6, + 0x030, 0x000072A6, + 0x030, 0x000082A6, + 0x030, 0x000092A6, + 0x030, 0x0000A2A6, + 0x030, 0x0000B2A6, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000303, + 0x030, 0x00001303, + 0x030, 0x00002303, + 0x030, 0x00003303, + 0x030, 0x000043A4, + 0x030, 0x000053A4, + 0x030, 0x000063A4, + 0x030, 0x000073A4, + 0x030, 0x00008365, + 0x030, 0x00009365, + 0x030, 0x0000A365, + 0x030, 0x0000B365, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000002A6, + 0x030, 0x000012A6, + 0x030, 0x000022A6, + 0x030, 0x000032A6, + 0x030, 0x000042A6, + 0x030, 0x000052A6, + 0x030, 0x000062A6, + 0x030, 0x000072A6, + 0x030, 0x000082A6, + 0x030, 0x000092A6, + 0x030, 0x0000A2A6, + 0x030, 0x0000B2A6, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000004A4, + 0x030, 0x000014A4, + 0x030, 0x000024A4, + 0x030, 0x000034A4, + 0x030, 0x000043A4, + 0x030, 0x000053A4, + 0x030, 0x000063A4, + 0x030, 0x000073A4, + 0x030, 0x000083A5, + 0x030, 0x000093A5, + 0x030, 0x0000A3A5, + 0x030, 0x0000B3A5, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000004A3, + 0x030, 0x000014A3, + 0x030, 0x000024A3, + 0x030, 0x000034A3, + 0x030, 0x000044A3, + 0x030, 0x000054A3, + 0x030, 0x000064A3, + 0x030, 0x000074A3, + 0x030, 0x000084A3, + 0x030, 0x000094A3, + 0x030, 0x0000A4A3, + 0x030, 0x0000B4A3, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000004A3, + 0x030, 0x000014A3, + 0x030, 0x000024A3, + 0x030, 0x000034A3, + 0x030, 0x000044A3, + 0x030, 0x000054A3, + 0x030, 0x000064A3, + 0x030, 0x000074A3, + 0x030, 0x000084A3, + 0x030, 0x000094A3, + 0x030, 0x0000A4A3, + 0x030, 0x0000B4A3, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000002F4, + 0x030, 0x000012F4, + 0x030, 0x000022F4, + 0x030, 0x000032F4, + 0x030, 0x00004365, + 0x030, 0x00005365, + 0x030, 0x00006365, + 0x030, 0x00007365, + 0x030, 0x000082A4, + 0x030, 0x000092A4, + 0x030, 0x0000A2A4, + 0x030, 0x0000B2A4, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000382, + 0x030, 0x00001382, + 0x030, 0x00002382, + 0x030, 0x00003382, + 0x030, 0x00004445, + 0x030, 0x00005445, + 0x030, 0x00006445, + 0x030, 0x00007445, + 0x030, 0x00008425, + 0x030, 0x00009425, + 0x030, 0x0000A425, + 0x030, 0x0000B425, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A3, + 0x030, 0x000053A3, + 0x030, 0x000063A3, + 0x030, 0x000073A3, + 0x030, 0x000083A3, + 0x030, 0x000093A3, + 0x030, 0x0000A3A3, + 0x030, 0x0000B3A3, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000004A3, + 0x030, 0x000014A3, + 0x030, 0x000024A3, + 0x030, 0x000034A3, + 0x030, 0x000044A3, + 0x030, 0x000054A3, + 0x030, 0x000064A3, + 0x030, 0x000074A3, + 0x030, 0x000084A3, + 0x030, 0x000094A3, + 0x030, 0x0000A4A3, + 0x030, 0x0000B4A3, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000443, + 0x030, 0x00001443, + 0x030, 0x00002443, + 0x030, 0x00003443, + 0x030, 0x000043A4, + 0x030, 0x000053A4, + 0x030, 0x000063A4, + 0x030, 0x000073A4, + 0x030, 0x00008365, + 0x030, 0x00009365, + 0x030, 0x0000A365, + 0x030, 0x0000B365, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000443, + 0x030, 0x00001443, + 0x030, 0x00002443, + 0x030, 0x00003443, + 0x030, 0x00004383, + 0x030, 0x00005383, + 0x030, 0x00006383, + 0x030, 0x00007383, + 0x030, 0x000084A4, + 0x030, 0x000094A4, + 0x030, 0x0000A4A4, + 0x030, 0x0000B4A4, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000363, + 0x030, 0x00001363, + 0x030, 0x00002363, + 0x030, 0x00003363, + 0x030, 0x000043A3, + 0x030, 0x000053A3, + 0x030, 0x000063A3, + 0x030, 0x000073A3, + 0x030, 0x000083A4, + 0x030, 0x000093A4, + 0x030, 0x0000A3A4, + 0x030, 0x0000B3A4, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000004A0, 0x030, 0x000014A0, 0x030, 0x000024A0, @@ -2131,24 +4859,59 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x030, 0x000094A0, 0x030, 0x0000A4A0, 0x030, 0x0000B4A0, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000200, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000002A1, + 0x030, 0x000012A1, + 0x030, 0x000022A1, + 0x030, 0x000032A1, + 0x030, 0x000042A1, + 0x030, 0x000052A1, + 0x030, 0x000062A1, + 0x030, 0x000072A1, + 0x030, 0x000082A1, + 0x030, 0x000092A1, + 0x030, 0x0000A2A1, + 0x030, 0x0000B2A1, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000004A0, 0x030, 0x000014A0, 0x030, 0x000024A0, 0x030, 0x000034A0, - 0x030, 0x000044A0, - 0x030, 0x000054A0, - 0x030, 0x000064A0, - 0x030, 0x000074A0, - 0x030, 0x000084A0, - 0x030, 0x000094A0, - 0x030, 0x0000A4A0, - 0x030, 0x0000B4A0, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000200, + 0x030, 0x000043A1, + 0x030, 0x000053A1, + 0x030, 0x000063A1, + 0x030, 0x000073A1, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000002A1, + 0x030, 0x000012A1, + 0x030, 0x000022A1, + 0x030, 0x000032A1, + 0x030, 0x000042A1, + 0x030, 0x000052A1, + 0x030, 0x000062A1, + 0x030, 0x000072A1, + 0x030, 0x000082A1, + 0x030, 0x000092A1, + 0x030, 0x0000A2A1, + 0x030, 0x0000B2A1, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000004A1, + 0x030, 0x000014A1, + 0x030, 0x000024A1, + 0x030, 0x000034A1, + 0x030, 0x000043A1, + 0x030, 0x000053A1, + 0x030, 0x000063A1, + 0x030, 0x000073A1, + 0x030, 0x000083A1, + 0x030, 0x000093A1, + 0x030, 0x0000A3A1, + 0x030, 0x0000B3A1, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000004A0, 0x030, 0x000014A0, 0x030, 0x000024A0, @@ -2161,9 +4924,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x030, 0x000094A0, 0x030, 0x0000A4A0, 0x030, 0x0000B4A0, - 0x0EF, 0x00000000, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000200, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000004A0, 0x030, 0x000014A0, 0x030, 0x000024A0, @@ -2176,39 +4937,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x030, 0x000094A0, 0x030, 0x0000A4A0, 0x030, 0x0000B4A0, - 0x0EF, 0x00000000, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000200, - 0x030, 0x000004A1, - 0x030, 0x000014A1, - 0x030, 0x000024A1, - 0x030, 0x000034A1, - 0x030, 0x000043A1, - 0x030, 0x000053A1, - 0x030, 0x000063A1, - 0x030, 0x000073A1, - 0x030, 0x000083A1, - 0x030, 0x000093A1, - 0x030, 0x0000A3A1, - 0x030, 0x0000B3A1, - 0x0EF, 0x00000000, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000200, - 0x030, 0x000004A0, - 0x030, 0x000014A0, - 0x030, 0x000024A0, - 0x030, 0x000034A0, - 0x030, 0x000043A1, - 0x030, 0x000053A1, - 0x030, 0x000063A1, - 0x030, 0x000073A1, - 0x030, 0x000083A2, - 0x030, 0x000093A2, - 0x030, 0x0000A3A2, - 0x030, 0x0000B3A2, - 0x0EF, 0x00000000, 0xA0000000, 0x00000000, - 0x0EF, 0x00000200, 0x030, 0x000002D0, 0x030, 0x000012D0, 0x030, 0x000022D0, @@ -2221,10 +4950,23 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x030, 0x000092D0, 0x030, 0x0000A2D0, 0x030, 0x0000B2D0, - 0x0EF, 0x00000000, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x0EF, 0x00000000, 0x0EF, 0x00000080, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000203, 0x030, 0x00001203, 0x030, 0x00002203, @@ -2237,9 +4979,59 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x030, 0x00009203, 0x030, 0x0000A203, 0x030, 0x0000B203, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x0EF, 0x00000080, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000203, 0x030, 0x00001203, 0x030, 0x00002203, @@ -2252,9 +5044,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x030, 0x00009203, 0x030, 0x0000A203, 0x030, 0x0000B203, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000080, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000203, 0x030, 0x00001203, 0x030, 0x00002203, @@ -2267,9 +5057,46 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x030, 0x00009203, 0x030, 0x0000A203, 0x030, 0x0000B203, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000080, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A3, + 0x030, 0x000013A3, + 0x030, 0x000023A3, + 0x030, 0x000033A3, + 0x030, 0x000043A4, + 0x030, 0x000053A4, + 0x030, 0x000063A4, + 0x030, 0x000073A4, + 0x030, 0x000083A3, + 0x030, 0x000093A3, + 0x030, 0x0000A3A3, + 0x030, 0x0000B3A3, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000203, 0x030, 0x00001203, 0x030, 0x00002203, @@ -2282,9 +5109,46 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x030, 0x00009203, 0x030, 0x0000A203, 0x030, 0x0000B203, - 0x0EF, 0x00000000, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000080, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000203, 0x030, 0x00001203, 0x030, 0x00002203, @@ -2297,9 +5161,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x030, 0x00009203, 0x030, 0x0000A203, 0x030, 0x0000B203, - 0x0EF, 0x00000000, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000080, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2, @@ -2312,9 +5174,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, - 0x0EF, 0x00000000, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000080, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2, @@ -2327,9 +5187,59 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, - 0x0EF, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000203, + 0x030, 0x00001203, + 0x030, 0x00002203, + 0x030, 0x00003203, + 0x030, 0x00004203, + 0x030, 0x00005203, + 0x030, 0x00006203, + 0x030, 0x00007203, + 0x030, 0x00008203, + 0x030, 0x00009203, + 0x030, 0x0000A203, + 0x030, 0x0000B203, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000203, + 0x030, 0x00001203, + 0x030, 0x00002203, + 0x030, 0x00003203, + 0x030, 0x00004203, + 0x030, 0x00005203, + 0x030, 0x00006203, + 0x030, 0x00007203, + 0x030, 0x00008203, + 0x030, 0x00009203, + 0x030, 0x0000A203, + 0x030, 0x0000B203, 0xA0000000, 0x00000000, - 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2, @@ -2342,99 +5252,312 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, - 0x0EF, 0x00000000, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x0EF, 0x00000000, 0x0EF, 0x00000040, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000764, + 0x030, 0x00001632, + 0x030, 0x00002421, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x0EF, 0x00000040, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000777, + 0x030, 0x00001442, + 0x030, 0x00002222, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000764, + 0x030, 0x00001452, + 0x030, 0x00002220, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000040, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000040, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000660, + 0x030, 0x00001341, + 0x030, 0x00002220, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000764, + 0x030, 0x00001632, + 0x030, 0x00002421, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000764, + 0x030, 0x00001632, + 0x030, 0x00002421, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000040, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000767, + 0x030, 0x00001442, + 0x030, 0x00002222, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000767, + 0x030, 0x00001632, + 0x030, 0x00002451, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000764, + 0x030, 0x00001632, + 0x030, 0x00002421, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000040, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000775, - 0x030, 0x00001222, + 0x030, 0x00001422, 0x030, 0x00002210, 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000040, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000775, - 0x030, 0x00001422, + 0x030, 0x00001222, 0x030, 0x00002210, 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000645, + 0x030, 0x00001333, + 0x030, 0x00002011, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, 0xA0000000, 0x00000000, - 0x0EF, 0x00000040, 0x030, 0x00000764, 0x030, 0x00001632, 0x030, 0x00002421, 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, - 0x0EF, 0x00000000, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, - 0xA0000000, 0x00000000, + 0x0EF, 0x00000000, 0x0EF, 0x00000800, - 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000C09, + 0x033, 0x00000021, + 0x03F, 0x00000C0C, + 0x033, 0x00000022, + 0x03F, 0x00000C0F, + 0x033, 0x00000023, + 0x03F, 0x00000C2C, + 0x033, 0x00000024, + 0x03F, 0x00000C2F, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000C90, + 0x033, 0x00000028, + 0x03F, 0x00000CD0, + 0x033, 0x00000029, + 0x03F, 0x00000CF2, + 0x033, 0x0000002A, + 0x03F, 0x00000CF5, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000007, + 0x033, 0x00000021, + 0x03F, 0x0000000A, + 0x033, 0x00000022, + 0x03F, 0x0000000D, + 0x033, 0x00000023, + 0x03F, 0x0000002A, + 0x033, 0x00000024, + 0x03F, 0x0000002D, + 0x033, 0x00000025, + 0x03F, 0x00000030, + 0x033, 0x00000026, + 0x03F, 0x0000006D, + 0x033, 0x00000027, + 0x03F, 0x00000070, + 0x033, 0x00000028, + 0x03F, 0x000000ED, + 0x033, 0x00000029, + 0x03F, 0x000000F0, + 0x033, 0x0000002A, + 0x03F, 0x000000F3, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000005, + 0x033, 0x00000021, + 0x03F, 0x00000008, + 0x033, 0x00000022, + 0x03F, 0x0000000B, + 0x033, 0x00000023, + 0x03F, 0x0000000E, + 0x033, 0x00000024, + 0x03F, 0x0000002B, + 0x033, 0x00000025, + 0x03F, 0x00000068, + 0x033, 0x00000026, + 0x03F, 0x0000006B, + 0x033, 0x00000027, + 0x03F, 0x0000006E, + 0x033, 0x00000028, + 0x03F, 0x00000071, + 0x033, 0x00000029, + 0x03F, 0x00000074, + 0x033, 0x0000002A, + 0x03F, 0x00000077, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000429, + 0x033, 0x00000021, + 0x03F, 0x00000828, + 0x033, 0x00000022, + 0x03F, 0x00000847, + 0x033, 0x00000023, + 0x03F, 0x0000084A, + 0x033, 0x00000024, + 0x03F, 0x00000C4B, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000CEA, + 0x033, 0x00000027, + 0x03F, 0x00000CED, + 0x033, 0x00000028, + 0x03F, 0x00000CF0, + 0x033, 0x00000029, + 0x03F, 0x00000CF3, + 0x033, 0x0000002A, + 0x03F, 0x00000CF6, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000005, + 0x033, 0x00000021, + 0x03F, 0x00000008, + 0x033, 0x00000022, + 0x03F, 0x0000000B, + 0x033, 0x00000023, + 0x03F, 0x0000000E, + 0x033, 0x00000024, + 0x03F, 0x0000002B, + 0x033, 0x00000025, + 0x03F, 0x00000068, + 0x033, 0x00000026, + 0x03F, 0x0000006B, + 0x033, 0x00000027, + 0x03F, 0x0000006E, + 0x033, 0x00000028, + 0x03F, 0x00000071, + 0x033, 0x00000029, + 0x03F, 0x00000074, + 0x033, 0x0000002A, + 0x03F, 0x00000077, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x0000042A, + 0x033, 0x00000021, + 0x03F, 0x00000829, + 0x033, 0x00000022, + 0x03F, 0x00000848, + 0x033, 0x00000023, + 0x03F, 0x0000084B, + 0x033, 0x00000024, + 0x03F, 0x00000C4C, + 0x033, 0x00000025, + 0x03F, 0x00000C8B, + 0x033, 0x00000026, + 0x03F, 0x00000CEA, + 0x033, 0x00000027, + 0x03F, 0x00000CED, + 0x033, 0x00000028, + 0x03F, 0x00000CF0, + 0x033, 0x00000029, + 0x03F, 0x00000CF3, + 0x033, 0x0000002A, + 0x03F, 0x00000CF6, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021, @@ -2457,7 +5580,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021, @@ -2480,7 +5603,76 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000828, + 0x033, 0x00000021, + 0x03F, 0x0000082B, + 0x033, 0x00000022, + 0x03F, 0x00000868, + 0x033, 0x00000023, + 0x03F, 0x00000889, + 0x033, 0x00000024, + 0x03F, 0x000008AA, + 0x033, 0x00000025, + 0x03F, 0x00000CE8, + 0x033, 0x00000026, + 0x03F, 0x00000CEB, + 0x033, 0x00000027, + 0x03F, 0x00000CEE, + 0x033, 0x00000028, + 0x03F, 0x00000CF1, + 0x033, 0x00000029, + 0x03F, 0x00000CF4, + 0x033, 0x0000002A, + 0x03F, 0x00000CF7, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000C09, + 0x033, 0x00000021, + 0x03F, 0x00000C0C, + 0x033, 0x00000022, + 0x03F, 0x00000C0F, + 0x033, 0x00000023, + 0x03F, 0x00000C2C, + 0x033, 0x00000024, + 0x03F, 0x00000C2F, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000C90, + 0x033, 0x00000028, + 0x03F, 0x00000CD0, + 0x033, 0x00000029, + 0x03F, 0x00000CF2, + 0x033, 0x0000002A, + 0x03F, 0x00000CF5, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000C09, + 0x033, 0x00000021, + 0x03F, 0x00000C0C, + 0x033, 0x00000022, + 0x03F, 0x00000C0F, + 0x033, 0x00000023, + 0x03F, 0x00000C2C, + 0x033, 0x00000024, + 0x03F, 0x00000C2F, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000C90, + 0x033, 0x00000028, + 0x03F, 0x00000CD0, + 0x033, 0x00000029, + 0x03F, 0x00000CF2, + 0x033, 0x0000002A, + 0x03F, 0x00000CF5, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021, @@ -2503,53 +5695,168 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, - 0x03F, 0x00000006, + 0x03F, 0x00000429, 0x033, 0x00000021, - 0x03F, 0x00000009, + 0x03F, 0x00000828, 0x033, 0x00000022, - 0x03F, 0x0000000C, + 0x03F, 0x00000847, 0x033, 0x00000023, - 0x03F, 0x00000029, + 0x03F, 0x0000084A, 0x033, 0x00000024, - 0x03F, 0x0000002C, + 0x03F, 0x00000C4B, 0x033, 0x00000025, - 0x03F, 0x0000004B, + 0x03F, 0x00000CE5, 0x033, 0x00000026, - 0x03F, 0x00000448, + 0x03F, 0x00000CE8, 0x033, 0x00000027, - 0x03F, 0x0000044B, + 0x03F, 0x00000CEB, 0x033, 0x00000028, - 0x03F, 0x0000084B, + 0x03F, 0x00000CEE, 0x033, 0x00000029, - 0x03F, 0x0000086B, + 0x03F, 0x00000CF1, 0x033, 0x0000002A, - 0x03F, 0x0000086E, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000CF4, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, - 0x03F, 0x00000006, + 0x03F, 0x00000C0A, 0x033, 0x00000021, - 0x03F, 0x00000009, + 0x03F, 0x00000C0D, 0x033, 0x00000022, - 0x03F, 0x0000000C, + 0x03F, 0x00000C2A, 0x033, 0x00000023, - 0x03F, 0x00000029, + 0x03F, 0x00000C2D, 0x033, 0x00000024, - 0x03F, 0x0000002C, + 0x03F, 0x00000C6A, 0x033, 0x00000025, - 0x03F, 0x0000004B, + 0x03F, 0x00000CAA, 0x033, 0x00000026, - 0x03F, 0x00000448, + 0x03F, 0x00000CAD, 0x033, 0x00000027, - 0x03F, 0x0000044B, + 0x03F, 0x00000CB0, 0x033, 0x00000028, - 0x03F, 0x0000084B, + 0x03F, 0x00000CF1, + 0x033, 0x00000029, + 0x03F, 0x00000CF4, + 0x033, 0x0000002A, + 0x03F, 0x00000CF7, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000C09, + 0x033, 0x00000021, + 0x03F, 0x00000C0C, + 0x033, 0x00000022, + 0x03F, 0x00000C0F, + 0x033, 0x00000023, + 0x03F, 0x00000C2C, + 0x033, 0x00000024, + 0x03F, 0x00000C2F, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000C90, + 0x033, 0x00000028, + 0x03F, 0x00000CD0, + 0x033, 0x00000029, + 0x03F, 0x00000CF2, + 0x033, 0x0000002A, + 0x03F, 0x00000CF5, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000007, + 0x033, 0x00000021, + 0x03F, 0x0000000A, + 0x033, 0x00000022, + 0x03F, 0x0000000D, + 0x033, 0x00000023, + 0x03F, 0x0000002A, + 0x033, 0x00000024, + 0x03F, 0x0000002D, + 0x033, 0x00000025, + 0x03F, 0x00000030, + 0x033, 0x00000026, + 0x03F, 0x0000006D, + 0x033, 0x00000027, + 0x03F, 0x00000070, + 0x033, 0x00000028, + 0x03F, 0x000000ED, + 0x033, 0x00000029, + 0x03F, 0x000000F0, + 0x033, 0x0000002A, + 0x03F, 0x000000F3, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000005, + 0x033, 0x00000021, + 0x03F, 0x00000008, + 0x033, 0x00000022, + 0x03F, 0x0000000B, + 0x033, 0x00000023, + 0x03F, 0x0000000E, + 0x033, 0x00000024, + 0x03F, 0x0000002B, + 0x033, 0x00000025, + 0x03F, 0x00000068, + 0x033, 0x00000026, + 0x03F, 0x0000006B, + 0x033, 0x00000027, + 0x03F, 0x0000006E, + 0x033, 0x00000028, + 0x03F, 0x00000071, + 0x033, 0x00000029, + 0x03F, 0x00000074, + 0x033, 0x0000002A, + 0x03F, 0x00000077, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x0000042B, + 0x033, 0x00000021, + 0x03F, 0x0000082A, + 0x033, 0x00000022, + 0x03F, 0x00000849, + 0x033, 0x00000023, + 0x03F, 0x0000084C, + 0x033, 0x00000024, + 0x03F, 0x00000C4C, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000CEB, + 0x033, 0x00000028, + 0x03F, 0x00000CEE, + 0x033, 0x00000029, + 0x03F, 0x00000CF1, + 0x033, 0x0000002A, + 0x03F, 0x00000CF4, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000005, + 0x033, 0x00000021, + 0x03F, 0x00000008, + 0x033, 0x00000022, + 0x03F, 0x0000000B, + 0x033, 0x00000023, + 0x03F, 0x0000000E, + 0x033, 0x00000024, + 0x03F, 0x0000002B, + 0x033, 0x00000025, + 0x03F, 0x00000068, + 0x033, 0x00000026, + 0x03F, 0x0000006B, + 0x033, 0x00000027, + 0x03F, 0x0000006E, + 0x033, 0x00000028, + 0x03F, 0x00000071, 0x033, 0x00000029, - 0x03F, 0x0000086B, + 0x03F, 0x00000074, 0x033, 0x0000002A, - 0x03F, 0x0000086E, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000077, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, 0x03F, 0x0000042B, 0x033, 0x00000021, @@ -2557,44 +5864,67 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x033, 0x00000022, 0x03F, 0x00000849, 0x033, 0x00000023, - 0x03F, 0x0000084C, + 0x03F, 0x0000084C, + 0x033, 0x00000024, + 0x03F, 0x00000C4C, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000CEB, + 0x033, 0x00000028, + 0x03F, 0x00000CEE, + 0x033, 0x00000029, + 0x03F, 0x00000CF1, + 0x033, 0x0000002A, + 0x03F, 0x00000CF4, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000007, + 0x033, 0x00000021, + 0x03F, 0x0000000A, + 0x033, 0x00000022, + 0x03F, 0x0000000D, + 0x033, 0x00000023, + 0x03F, 0x0000002A, 0x033, 0x00000024, - 0x03F, 0x00000C4C, + 0x03F, 0x0000002D, 0x033, 0x00000025, - 0x03F, 0x00000C8A, + 0x03F, 0x00000030, 0x033, 0x00000026, - 0x03F, 0x00000C8D, + 0x03F, 0x0000006D, 0x033, 0x00000027, - 0x03F, 0x00000CEB, + 0x03F, 0x00000070, 0x033, 0x00000028, - 0x03F, 0x00000CEE, + 0x03F, 0x000000ED, 0x033, 0x00000029, - 0x03F, 0x00000CF1, + 0x03F, 0x000000F0, 0x033, 0x0000002A, - 0x03F, 0x00000CF4, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000000F3, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, - 0x03F, 0x0000042B, + 0x03F, 0x00000007, 0x033, 0x00000021, - 0x03F, 0x0000082A, + 0x03F, 0x0000000A, 0x033, 0x00000022, - 0x03F, 0x00000849, + 0x03F, 0x0000000D, 0x033, 0x00000023, - 0x03F, 0x0000084C, + 0x03F, 0x0000002A, 0x033, 0x00000024, - 0x03F, 0x00000C4C, + 0x03F, 0x0000002D, 0x033, 0x00000025, - 0x03F, 0x00000C8A, + 0x03F, 0x00000030, 0x033, 0x00000026, - 0x03F, 0x00000C8D, + 0x03F, 0x0000006D, 0x033, 0x00000027, - 0x03F, 0x00000CEB, + 0x03F, 0x00000070, 0x033, 0x00000028, - 0x03F, 0x00000CEE, + 0x03F, 0x000000ED, 0x033, 0x00000029, - 0x03F, 0x00000CF1, + 0x03F, 0x000000F0, 0x033, 0x0000002A, - 0x03F, 0x00000CF4, + 0x03F, 0x000000F3, 0xA0000000, 0x00000000, 0x033, 0x00000020, 0x03F, 0x00000C09, @@ -2619,7 +5949,30 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x033, 0x0000002A, 0x03F, 0x00000CF5, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000C0A, + 0x033, 0x00000061, + 0x03F, 0x00000C0D, + 0x033, 0x00000062, + 0x03F, 0x00000C2A, + 0x033, 0x00000063, + 0x03F, 0x00000C2D, + 0x033, 0x00000064, + 0x03F, 0x00000C6A, + 0x033, 0x00000065, + 0x03F, 0x00000CAA, + 0x033, 0x00000066, + 0x03F, 0x00000CAD, + 0x033, 0x00000067, + 0x03F, 0x00000CB0, + 0x033, 0x00000068, + 0x03F, 0x00000CF1, + 0x033, 0x00000069, + 0x03F, 0x00000CF4, + 0x033, 0x0000006A, + 0x03F, 0x00000CF7, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061, @@ -2642,7 +5995,99 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000005, + 0x033, 0x00000061, + 0x03F, 0x00000008, + 0x033, 0x00000062, + 0x03F, 0x0000000B, + 0x033, 0x00000063, + 0x03F, 0x0000000E, + 0x033, 0x00000064, + 0x03F, 0x0000002B, + 0x033, 0x00000065, + 0x03F, 0x00000068, + 0x033, 0x00000066, + 0x03F, 0x0000006B, + 0x033, 0x00000067, + 0x03F, 0x0000006E, + 0x033, 0x00000068, + 0x03F, 0x00000071, + 0x033, 0x00000069, + 0x03F, 0x00000074, + 0x033, 0x0000006A, + 0x03F, 0x00000077, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000429, + 0x033, 0x00000061, + 0x03F, 0x00000828, + 0x033, 0x00000062, + 0x03F, 0x00000847, + 0x033, 0x00000063, + 0x03F, 0x0000084A, + 0x033, 0x00000064, + 0x03F, 0x00000C4B, + 0x033, 0x00000065, + 0x03F, 0x00000C8A, + 0x033, 0x00000066, + 0x03F, 0x00000CEA, + 0x033, 0x00000067, + 0x03F, 0x00000CED, + 0x033, 0x00000068, + 0x03F, 0x00000CF0, + 0x033, 0x00000069, + 0x03F, 0x00000CF3, + 0x033, 0x0000006A, + 0x03F, 0x00000CF6, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000005, + 0x033, 0x00000061, + 0x03F, 0x00000008, + 0x033, 0x00000062, + 0x03F, 0x0000000B, + 0x033, 0x00000063, + 0x03F, 0x0000000E, + 0x033, 0x00000064, + 0x03F, 0x0000002B, + 0x033, 0x00000065, + 0x03F, 0x00000068, + 0x033, 0x00000066, + 0x03F, 0x0000006B, + 0x033, 0x00000067, + 0x03F, 0x0000006E, + 0x033, 0x00000068, + 0x03F, 0x00000071, + 0x033, 0x00000069, + 0x03F, 0x00000074, + 0x033, 0x0000006A, + 0x03F, 0x00000077, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x0000042A, + 0x033, 0x00000061, + 0x03F, 0x00000829, + 0x033, 0x00000062, + 0x03F, 0x00000848, + 0x033, 0x00000063, + 0x03F, 0x0000084B, + 0x033, 0x00000064, + 0x03F, 0x00000C69, + 0x033, 0x00000065, + 0x03F, 0x00000CA9, + 0x033, 0x00000066, + 0x03F, 0x00000CEA, + 0x033, 0x00000067, + 0x03F, 0x00000CED, + 0x033, 0x00000068, + 0x03F, 0x00000CF0, + 0x033, 0x00000069, + 0x03F, 0x00000CF3, + 0x033, 0x0000006A, + 0x03F, 0x00000CF6, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061, @@ -2665,7 +6110,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061, @@ -2688,53 +6133,214 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060, - 0x03F, 0x00000006, + 0x03F, 0x00000842, 0x033, 0x00000061, - 0x03F, 0x00000009, + 0x03F, 0x00000845, 0x033, 0x00000062, - 0x03F, 0x0000000C, + 0x03F, 0x00000866, 0x033, 0x00000063, - 0x03F, 0x00000029, + 0x03F, 0x000008A6, 0x033, 0x00000064, - 0x03F, 0x0000002C, + 0x03F, 0x000008C8, + 0x033, 0x00000065, + 0x03F, 0x00000CE8, + 0x033, 0x00000066, + 0x03F, 0x00000CEB, + 0x033, 0x00000067, + 0x03F, 0x00000CEE, + 0x033, 0x00000068, + 0x03F, 0x00000CF1, + 0x033, 0x00000069, + 0x03F, 0x00000CF4, + 0x033, 0x0000006A, + 0x03F, 0x00000CF7, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000C0A, + 0x033, 0x00000061, + 0x03F, 0x00000C0D, + 0x033, 0x00000062, + 0x03F, 0x00000C2A, + 0x033, 0x00000063, + 0x03F, 0x00000C2D, + 0x033, 0x00000064, + 0x03F, 0x00000C6A, + 0x033, 0x00000065, + 0x03F, 0x00000CAA, + 0x033, 0x00000066, + 0x03F, 0x00000CAD, + 0x033, 0x00000067, + 0x03F, 0x00000CB0, + 0x033, 0x00000068, + 0x03F, 0x00000CF1, + 0x033, 0x00000069, + 0x03F, 0x00000CF4, + 0x033, 0x0000006A, + 0x03F, 0x00000CF7, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000C0A, + 0x033, 0x00000061, + 0x03F, 0x00000C0D, + 0x033, 0x00000062, + 0x03F, 0x00000C2A, + 0x033, 0x00000063, + 0x03F, 0x00000C2D, + 0x033, 0x00000064, + 0x03F, 0x00000C6A, + 0x033, 0x00000065, + 0x03F, 0x00000CAA, + 0x033, 0x00000066, + 0x03F, 0x00000CAD, + 0x033, 0x00000067, + 0x03F, 0x00000CB0, + 0x033, 0x00000068, + 0x03F, 0x00000CF1, + 0x033, 0x00000069, + 0x03F, 0x00000CF4, + 0x033, 0x0000006A, + 0x03F, 0x00000CF7, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000005, + 0x033, 0x00000061, + 0x03F, 0x00000008, + 0x033, 0x00000062, + 0x03F, 0x0000000B, + 0x033, 0x00000063, + 0x03F, 0x0000000E, + 0x033, 0x00000064, + 0x03F, 0x0000002B, + 0x033, 0x00000065, + 0x03F, 0x00000068, + 0x033, 0x00000066, + 0x03F, 0x0000006B, + 0x033, 0x00000067, + 0x03F, 0x0000006E, + 0x033, 0x00000068, + 0x03F, 0x00000071, + 0x033, 0x00000069, + 0x03F, 0x00000074, + 0x033, 0x0000006A, + 0x03F, 0x00000077, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000429, + 0x033, 0x00000061, + 0x03F, 0x00000828, + 0x033, 0x00000062, + 0x03F, 0x00000847, + 0x033, 0x00000063, + 0x03F, 0x0000084A, + 0x033, 0x00000064, + 0x03F, 0x00000C4B, + 0x033, 0x00000065, + 0x03F, 0x00000CE5, + 0x033, 0x00000066, + 0x03F, 0x00000CE8, + 0x033, 0x00000067, + 0x03F, 0x00000CEB, + 0x033, 0x00000068, + 0x03F, 0x00000CEE, + 0x033, 0x00000069, + 0x03F, 0x00000CF1, + 0x033, 0x0000006A, + 0x03F, 0x00000CF4, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000C0A, + 0x033, 0x00000061, + 0x03F, 0x00000C0D, + 0x033, 0x00000062, + 0x03F, 0x00000C2A, + 0x033, 0x00000063, + 0x03F, 0x00000C2D, + 0x033, 0x00000064, + 0x03F, 0x00000C6A, + 0x033, 0x00000065, + 0x03F, 0x00000CAA, + 0x033, 0x00000066, + 0x03F, 0x00000CAD, + 0x033, 0x00000067, + 0x03F, 0x00000CB0, + 0x033, 0x00000068, + 0x03F, 0x00000CF1, + 0x033, 0x00000069, + 0x03F, 0x00000CF4, + 0x033, 0x0000006A, + 0x03F, 0x00000CF7, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000C0A, + 0x033, 0x00000061, + 0x03F, 0x00000C0D, + 0x033, 0x00000062, + 0x03F, 0x00000C2A, + 0x033, 0x00000063, + 0x03F, 0x00000C2D, + 0x033, 0x00000064, + 0x03F, 0x00000C6A, + 0x033, 0x00000065, + 0x03F, 0x00000CAA, + 0x033, 0x00000066, + 0x03F, 0x00000CAD, + 0x033, 0x00000067, + 0x03F, 0x00000CB0, + 0x033, 0x00000068, + 0x03F, 0x00000CF1, + 0x033, 0x00000069, + 0x03F, 0x00000CF4, + 0x033, 0x0000006A, + 0x03F, 0x00000CF7, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000007, + 0x033, 0x00000061, + 0x03F, 0x0000000A, + 0x033, 0x00000062, + 0x03F, 0x0000000D, + 0x033, 0x00000063, + 0x03F, 0x0000002A, + 0x033, 0x00000064, + 0x03F, 0x0000002D, 0x033, 0x00000065, - 0x03F, 0x0000004B, + 0x03F, 0x00000030, 0x033, 0x00000066, - 0x03F, 0x00000448, + 0x03F, 0x0000006D, 0x033, 0x00000067, - 0x03F, 0x0000044B, + 0x03F, 0x00000070, 0x033, 0x00000068, - 0x03F, 0x0000084B, + 0x03F, 0x000000ED, 0x033, 0x00000069, - 0x03F, 0x0000086B, + 0x03F, 0x000000F0, 0x033, 0x0000006A, - 0x03F, 0x0000086E, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000000F3, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060, - 0x03F, 0x00000006, + 0x03F, 0x00000005, 0x033, 0x00000061, - 0x03F, 0x00000009, + 0x03F, 0x00000008, 0x033, 0x00000062, - 0x03F, 0x0000000C, + 0x03F, 0x0000000B, 0x033, 0x00000063, - 0x03F, 0x00000029, + 0x03F, 0x0000000E, 0x033, 0x00000064, - 0x03F, 0x0000002C, + 0x03F, 0x0000002B, 0x033, 0x00000065, - 0x03F, 0x0000004B, + 0x03F, 0x00000068, 0x033, 0x00000066, - 0x03F, 0x00000448, + 0x03F, 0x0000006B, 0x033, 0x00000067, - 0x03F, 0x0000044B, + 0x03F, 0x0000006E, 0x033, 0x00000068, - 0x03F, 0x0000084B, + 0x03F, 0x00000071, 0x033, 0x00000069, - 0x03F, 0x0000086B, + 0x03F, 0x00000074, 0x033, 0x0000006A, - 0x03F, 0x0000086E, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000077, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060, 0x03F, 0x0000042C, 0x033, 0x00000061, @@ -2757,7 +6363,30 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000CF2, 0x033, 0x0000006A, 0x03F, 0x00000CF5, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000005, + 0x033, 0x00000061, + 0x03F, 0x00000008, + 0x033, 0x00000062, + 0x03F, 0x0000000B, + 0x033, 0x00000063, + 0x03F, 0x0000000E, + 0x033, 0x00000064, + 0x03F, 0x0000002B, + 0x033, 0x00000065, + 0x03F, 0x00000068, + 0x033, 0x00000066, + 0x03F, 0x0000006B, + 0x033, 0x00000067, + 0x03F, 0x0000006E, + 0x033, 0x00000068, + 0x03F, 0x00000071, + 0x033, 0x00000069, + 0x03F, 0x00000074, + 0x033, 0x0000006A, + 0x03F, 0x00000077, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060, 0x03F, 0x0000042C, 0x033, 0x00000061, @@ -2780,6 +6409,52 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000CF2, 0x033, 0x0000006A, 0x03F, 0x00000CF5, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000007, + 0x033, 0x00000061, + 0x03F, 0x0000000A, + 0x033, 0x00000062, + 0x03F, 0x0000000D, + 0x033, 0x00000063, + 0x03F, 0x0000002A, + 0x033, 0x00000064, + 0x03F, 0x0000002D, + 0x033, 0x00000065, + 0x03F, 0x00000030, + 0x033, 0x00000066, + 0x03F, 0x0000006D, + 0x033, 0x00000067, + 0x03F, 0x00000070, + 0x033, 0x00000068, + 0x03F, 0x000000ED, + 0x033, 0x00000069, + 0x03F, 0x000000F0, + 0x033, 0x0000006A, + 0x03F, 0x000000F3, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000007, + 0x033, 0x00000061, + 0x03F, 0x0000000A, + 0x033, 0x00000062, + 0x03F, 0x0000000D, + 0x033, 0x00000063, + 0x03F, 0x0000002A, + 0x033, 0x00000064, + 0x03F, 0x0000002D, + 0x033, 0x00000065, + 0x03F, 0x00000030, + 0x033, 0x00000066, + 0x03F, 0x0000006D, + 0x033, 0x00000067, + 0x03F, 0x00000070, + 0x033, 0x00000068, + 0x03F, 0x000000ED, + 0x033, 0x00000069, + 0x03F, 0x000000F0, + 0x033, 0x0000006A, + 0x03F, 0x000000F3, 0xA0000000, 0x00000000, 0x033, 0x00000060, 0x03F, 0x00000C0A, @@ -2804,7 +6479,260 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x033, 0x0000006A, 0x03F, 0x00000CF7, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x83000000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000C09, + 0x033, 0x000000A1, + 0x03F, 0x00000C0C, + 0x033, 0x000000A2, + 0x03F, 0x00000C0F, + 0x033, 0x000000A3, + 0x03F, 0x00000C2C, + 0x033, 0x000000A4, + 0x03F, 0x00000C2F, + 0x033, 0x000000A5, + 0x03F, 0x00000C8A, + 0x033, 0x000000A6, + 0x03F, 0x00000C8D, + 0x033, 0x000000A7, + 0x03F, 0x00000C90, + 0x033, 0x000000A8, + 0x03F, 0x00000CEF, + 0x033, 0x000000A9, + 0x03F, 0x00000CF2, + 0x033, 0x000000AA, + 0x03F, 0x00000CF5, + 0x93000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000007, + 0x033, 0x000000A1, + 0x03F, 0x0000000A, + 0x033, 0x000000A2, + 0x03F, 0x0000000D, + 0x033, 0x000000A3, + 0x03F, 0x0000002A, + 0x033, 0x000000A4, + 0x03F, 0x0000002D, + 0x033, 0x000000A5, + 0x03F, 0x00000030, + 0x033, 0x000000A6, + 0x03F, 0x0000006D, + 0x033, 0x000000A7, + 0x03F, 0x00000070, + 0x033, 0x000000A8, + 0x03F, 0x000000ED, + 0x033, 0x000000A9, + 0x03F, 0x000000F0, + 0x033, 0x000000AA, + 0x03F, 0x000000F3, + 0x93000002, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000005, + 0x033, 0x000000A1, + 0x03F, 0x00000008, + 0x033, 0x000000A2, + 0x03F, 0x0000000B, + 0x033, 0x000000A3, + 0x03F, 0x0000000E, + 0x033, 0x000000A4, + 0x03F, 0x00000047, + 0x033, 0x000000A5, + 0x03F, 0x0000004A, + 0x033, 0x000000A6, + 0x03F, 0x0000004D, + 0x033, 0x000000A7, + 0x03F, 0x00000050, + 0x033, 0x000000A8, + 0x03F, 0x00000053, + 0x033, 0x000000A9, + 0x03F, 0x00000056, + 0x033, 0x000000AA, + 0x03F, 0x00000094, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000429, + 0x033, 0x000000A1, + 0x03F, 0x00000828, + 0x033, 0x000000A2, + 0x03F, 0x00000847, + 0x033, 0x000000A3, + 0x03F, 0x0000084A, + 0x033, 0x000000A4, + 0x03F, 0x00000C4B, + 0x033, 0x000000A5, + 0x03F, 0x00000C8A, + 0x033, 0x000000A6, + 0x03F, 0x00000CEA, + 0x033, 0x000000A7, + 0x03F, 0x00000CED, + 0x033, 0x000000A8, + 0x03F, 0x00000CF0, + 0x033, 0x000000A9, + 0x03F, 0x00000CF3, + 0x033, 0x000000AA, + 0x03F, 0x00000CF6, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000005, + 0x033, 0x000000A1, + 0x03F, 0x00000008, + 0x033, 0x000000A2, + 0x03F, 0x0000000B, + 0x033, 0x000000A3, + 0x03F, 0x0000000E, + 0x033, 0x000000A4, + 0x03F, 0x00000047, + 0x033, 0x000000A5, + 0x03F, 0x0000004A, + 0x033, 0x000000A6, + 0x03F, 0x0000004D, + 0x033, 0x000000A7, + 0x03F, 0x00000050, + 0x033, 0x000000A8, + 0x03F, 0x00000053, + 0x033, 0x000000A9, + 0x03F, 0x00000056, + 0x033, 0x000000AA, + 0x03F, 0x00000094, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x0000042A, + 0x033, 0x000000A1, + 0x03F, 0x00000829, + 0x033, 0x000000A2, + 0x03F, 0x00000848, + 0x033, 0x000000A3, + 0x03F, 0x0000084B, + 0x033, 0x000000A4, + 0x03F, 0x00000C4C, + 0x033, 0x000000A5, + 0x03F, 0x00000CA9, + 0x033, 0x000000A6, + 0x03F, 0x00000CEA, + 0x033, 0x000000A7, + 0x03F, 0x00000CED, + 0x033, 0x000000A8, + 0x03F, 0x00000CF0, + 0x033, 0x000000A9, + 0x03F, 0x00000CF3, + 0x033, 0x000000AA, + 0x03F, 0x00000CF6, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000007, + 0x033, 0x000000A1, + 0x03F, 0x0000000A, + 0x033, 0x000000A2, + 0x03F, 0x0000000D, + 0x033, 0x000000A3, + 0x03F, 0x0000002A, + 0x033, 0x000000A4, + 0x03F, 0x0000002D, + 0x033, 0x000000A5, + 0x03F, 0x00000030, + 0x033, 0x000000A6, + 0x03F, 0x0000006D, + 0x033, 0x000000A7, + 0x03F, 0x00000070, + 0x033, 0x000000A8, + 0x03F, 0x000000ED, + 0x033, 0x000000A9, + 0x03F, 0x000000F0, + 0x033, 0x000000AA, + 0x03F, 0x000000F3, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000007, + 0x033, 0x000000A1, + 0x03F, 0x0000000A, + 0x033, 0x000000A2, + 0x03F, 0x0000000D, + 0x033, 0x000000A3, + 0x03F, 0x0000002A, + 0x033, 0x000000A4, + 0x03F, 0x0000002D, + 0x033, 0x000000A5, + 0x03F, 0x00000030, + 0x033, 0x000000A6, + 0x03F, 0x0000006D, + 0x033, 0x000000A7, + 0x03F, 0x00000070, + 0x033, 0x000000A8, + 0x03F, 0x000000ED, + 0x033, 0x000000A9, + 0x03F, 0x000000F0, + 0x033, 0x000000AA, + 0x03F, 0x000000F3, + 0x93000008, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000826, + 0x033, 0x000000A1, + 0x03F, 0x00000829, + 0x033, 0x000000A2, + 0x03F, 0x0000082C, + 0x033, 0x000000A3, + 0x03F, 0x0000082F, + 0x033, 0x000000A4, + 0x03F, 0x0000086C, + 0x033, 0x000000A5, + 0x03F, 0x00000CE8, + 0x033, 0x000000A6, + 0x03F, 0x00000CEB, + 0x033, 0x000000A7, + 0x03F, 0x00000CEE, + 0x033, 0x000000A8, + 0x03F, 0x00000CF1, + 0x033, 0x000000A9, + 0x03F, 0x00000CF4, + 0x033, 0x000000AA, + 0x03F, 0x00000CF7, + 0x93000009, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000C09, + 0x033, 0x000000A1, + 0x03F, 0x00000C0C, + 0x033, 0x000000A2, + 0x03F, 0x00000C0F, + 0x033, 0x000000A3, + 0x03F, 0x00000C2C, + 0x033, 0x000000A4, + 0x03F, 0x00000C2F, + 0x033, 0x000000A5, + 0x03F, 0x00000C8A, + 0x033, 0x000000A6, + 0x03F, 0x00000C8D, + 0x033, 0x000000A7, + 0x03F, 0x00000C90, + 0x033, 0x000000A8, + 0x03F, 0x00000CEF, + 0x033, 0x000000A9, + 0x03F, 0x00000CF2, + 0x033, 0x000000AA, + 0x03F, 0x00000CF5, + 0x9300000a, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000C09, + 0x033, 0x000000A1, + 0x03F, 0x00000C0C, + 0x033, 0x000000A2, + 0x03F, 0x00000C0F, + 0x033, 0x000000A3, + 0x03F, 0x00000C2C, + 0x033, 0x000000A4, + 0x03F, 0x00000C2F, + 0x033, 0x000000A5, + 0x03F, 0x00000C8A, + 0x033, 0x000000A6, + 0x03F, 0x00000C8D, + 0x033, 0x000000A7, + 0x03F, 0x00000C90, + 0x033, 0x000000A8, + 0x03F, 0x00000CEF, + 0x033, 0x000000A9, + 0x03F, 0x00000CF2, + 0x033, 0x000000AA, + 0x03F, 0x00000CF5, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x00000007, 0x033, 0x000000A1, @@ -2827,32 +6755,76 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x00000007, + 0x03F, 0x00000429, 0x033, 0x000000A1, - 0x03F, 0x0000000A, + 0x03F, 0x00000828, 0x033, 0x000000A2, - 0x03F, 0x0000000D, + 0x03F, 0x00000847, 0x033, 0x000000A3, - 0x03F, 0x0000002A, + 0x03F, 0x0000084A, 0x033, 0x000000A4, - 0x03F, 0x0000002D, + 0x03F, 0x00000C4B, 0x033, 0x000000A5, - 0x03F, 0x00000030, + 0x03F, 0x00000CE5, 0x033, 0x000000A6, - 0x03F, 0x0000006D, + 0x03F, 0x00000CE8, 0x033, 0x000000A7, - 0x03F, 0x00000070, + 0x03F, 0x00000CEB, 0x033, 0x000000A8, - 0x03F, 0x000000ED, + 0x03F, 0x00000CEE, 0x033, 0x000000A9, - 0x03F, 0x000000F0, + 0x03F, 0x00000CF1, 0x033, 0x000000AA, - 0x03F, 0x000000F3, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000CF4, + 0x9300000d, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000C09, + 0x033, 0x000000A1, + 0x03F, 0x00000C0C, + 0x033, 0x000000A2, + 0x03F, 0x00000C0F, + 0x033, 0x000000A3, + 0x03F, 0x00000C2C, + 0x033, 0x000000A4, + 0x03F, 0x00000C2F, + 0x033, 0x000000A5, + 0x03F, 0x00000C8A, + 0x033, 0x000000A6, + 0x03F, 0x00000C8D, + 0x033, 0x000000A7, + 0x03F, 0x00000C90, + 0x033, 0x000000A8, + 0x03F, 0x00000CEF, + 0x033, 0x000000A9, + 0x03F, 0x00000CF2, + 0x033, 0x000000AA, + 0x03F, 0x00000CF5, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000C09, + 0x033, 0x000000A1, + 0x03F, 0x00000C0C, + 0x033, 0x000000A2, + 0x03F, 0x00000C0F, + 0x033, 0x000000A3, + 0x03F, 0x00000C2C, + 0x033, 0x000000A4, + 0x03F, 0x00000C2F, + 0x033, 0x000000A5, + 0x03F, 0x00000C8A, + 0x033, 0x000000A6, + 0x03F, 0x00000C8D, + 0x033, 0x000000A7, + 0x03F, 0x00000C90, + 0x033, 0x000000A8, + 0x03F, 0x00000CEF, + 0x033, 0x000000A9, + 0x03F, 0x00000CF2, + 0x033, 0x000000AA, + 0x03F, 0x00000CF5, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x00000007, 0x033, 0x000000A1, @@ -2875,56 +6847,76 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x00000006, + 0x03F, 0x00000005, 0x033, 0x000000A1, - 0x03F, 0x00000009, + 0x03F, 0x00000008, 0x033, 0x000000A2, - 0x03F, 0x0000000C, + 0x03F, 0x0000000B, 0x033, 0x000000A3, - 0x03F, 0x00000029, + 0x03F, 0x0000000E, 0x033, 0x000000A4, - 0x03F, 0x0000002C, + 0x03F, 0x00000047, 0x033, 0x000000A5, - 0x03F, 0x0000004B, + 0x03F, 0x0000004A, 0x033, 0x000000A6, - 0x03F, 0x00000448, + 0x03F, 0x0000004D, 0x033, 0x000000A7, - 0x03F, 0x0000044B, + 0x03F, 0x00000050, 0x033, 0x000000A8, + 0x03F, 0x00000053, + 0x033, 0x000000A9, + 0x03F, 0x00000056, + 0x033, 0x000000AA, + 0x03F, 0x00000094, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x0000042A, + 0x033, 0x000000A1, + 0x03F, 0x00000829, + 0x033, 0x000000A2, + 0x03F, 0x00000848, + 0x033, 0x000000A3, 0x03F, 0x0000084B, + 0x033, 0x000000A4, + 0x03F, 0x00000C4C, + 0x033, 0x000000A5, + 0x03F, 0x00000C8A, + 0x033, 0x000000A6, + 0x03F, 0x00000C8D, + 0x033, 0x000000A7, + 0x03F, 0x00000CEC, + 0x033, 0x000000A8, + 0x03F, 0x00000CEF, 0x033, 0x000000A9, - 0x03F, 0x0000086B, + 0x03F, 0x00000CF2, 0x033, 0x000000AA, - 0x03F, 0x0000086E, - 0x0EF, 0x00000000, - 0x9000200c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000CF5, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x00000006, + 0x03F, 0x00000005, 0x033, 0x000000A1, - 0x03F, 0x00000009, + 0x03F, 0x00000008, 0x033, 0x000000A2, - 0x03F, 0x0000000C, + 0x03F, 0x0000000B, 0x033, 0x000000A3, - 0x03F, 0x00000029, + 0x03F, 0x0000000E, 0x033, 0x000000A4, - 0x03F, 0x0000002C, + 0x03F, 0x00000047, 0x033, 0x000000A5, - 0x03F, 0x0000004B, + 0x03F, 0x0000004A, 0x033, 0x000000A6, - 0x03F, 0x00000448, + 0x03F, 0x0000004D, 0x033, 0x000000A7, - 0x03F, 0x0000044B, + 0x03F, 0x00000050, 0x033, 0x000000A8, - 0x03F, 0x0000084B, + 0x03F, 0x00000053, 0x033, 0x000000A9, - 0x03F, 0x0000086B, + 0x03F, 0x00000056, 0x033, 0x000000AA, - 0x03F, 0x0000086E, - 0x0EF, 0x00000000, - 0x90002100, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000094, + 0x90000005, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x0000042A, 0x033, 0x000000A1, @@ -2947,31 +6939,52 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5, - 0x0EF, 0x00000000, - 0x90002000, 0x00000000, 0x40000000, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x0000042A, + 0x03F, 0x00000007, 0x033, 0x000000A1, - 0x03F, 0x00000829, + 0x03F, 0x0000000A, 0x033, 0x000000A2, - 0x03F, 0x00000848, + 0x03F, 0x0000000D, 0x033, 0x000000A3, - 0x03F, 0x0000084B, + 0x03F, 0x0000002A, 0x033, 0x000000A4, - 0x03F, 0x00000C4C, + 0x03F, 0x0000002D, 0x033, 0x000000A5, - 0x03F, 0x00000C8A, + 0x03F, 0x00000030, 0x033, 0x000000A6, - 0x03F, 0x00000C8D, + 0x03F, 0x0000006D, 0x033, 0x000000A7, - 0x03F, 0x00000CEC, + 0x03F, 0x00000070, 0x033, 0x000000A8, - 0x03F, 0x00000CEF, + 0x03F, 0x000000ED, 0x033, 0x000000A9, - 0x03F, 0x00000CF2, + 0x03F, 0x000000F0, 0x033, 0x000000AA, - 0x03F, 0x00000CF5, - 0x0EF, 0x00000000, + 0x03F, 0x000000F3, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000007, + 0x033, 0x000000A1, + 0x03F, 0x0000000A, + 0x033, 0x000000A2, + 0x03F, 0x0000000D, + 0x033, 0x000000A3, + 0x03F, 0x0000002A, + 0x033, 0x000000A4, + 0x03F, 0x0000002D, + 0x033, 0x000000A5, + 0x03F, 0x00000030, + 0x033, 0x000000A6, + 0x03F, 0x0000006D, + 0x033, 0x000000A7, + 0x03F, 0x00000070, + 0x033, 0x000000A8, + 0x03F, 0x000000ED, + 0x033, 0x000000A9, + 0x03F, 0x000000F0, + 0x033, 0x000000AA, + 0x03F, 0x000000F3, 0xA0000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x00000C09, @@ -2995,10 +7008,10 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5, - 0x0EF, 0x00000000, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x0EF, 0x00000000, 0x0EF, 0x00000400, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000265A, 0x033, 0x00000001, @@ -3007,9 +7020,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x0000265A, 0x033, 0x00000003, 0x03F, 0x0000265A, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x0EF, 0x00000400, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000265A, 0x033, 0x00000001, @@ -3018,9 +7029,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x0000265A, 0x033, 0x00000003, 0x03F, 0x0000265A, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000400, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000265A, 0x033, 0x00000001, @@ -3029,9 +7038,52 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x0000265A, 0x033, 0x00000003, 0x03F, 0x0000265A, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000400, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0000265A, + 0x033, 0x00000001, + 0x03F, 0x0000265A, + 0x033, 0x00000002, + 0x03F, 0x0000265A, + 0x033, 0x00000003, + 0x03F, 0x0000265A, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0000265A, + 0x033, 0x00000001, + 0x03F, 0x0000265A, + 0x033, 0x00000002, + 0x03F, 0x0000265A, + 0x033, 0x00000003, + 0x03F, 0x0000265A, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0000265A, + 0x033, 0x00000001, + 0x03F, 0x0000265A, + 0x033, 0x00000002, + 0x03F, 0x0000265A, + 0x033, 0x00000003, + 0x03F, 0x0000265A, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0000265A, + 0x033, 0x00000001, + 0x03F, 0x0000265A, + 0x033, 0x00000002, + 0x03F, 0x0000265A, + 0x033, 0x00000003, + 0x03F, 0x0000265A, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0000265A, + 0x033, 0x00000001, + 0x03F, 0x0000265A, + 0x033, 0x00000002, + 0x03F, 0x0000265A, + 0x033, 0x00000003, + 0x03F, 0x0000265A, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000265A, 0x033, 0x00000001, @@ -3039,22 +7091,65 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x033, 0x00000002, 0x03F, 0x0000265A, 0x033, 0x00000003, - 0x03F, 0x0000265A, - 0x0EF, 0x00000000, - 0xA0000000, 0x00000000, - 0x0EF, 0x00000400, + 0x03F, 0x0000265A, + 0xA0000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x000004BB, + 0x033, 0x00000001, + 0x03F, 0x000004BB, + 0x033, 0x00000002, + 0x03F, 0x000004BB, + 0x033, 0x00000003, + 0x03F, 0x000004BB, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00000100, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000745, + 0x033, 0x00000001, + 0x03F, 0x00000745, + 0x033, 0x00000002, + 0x03F, 0x00000745, + 0x033, 0x00000003, + 0x03F, 0x00000745, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000745, + 0x033, 0x00000001, + 0x03F, 0x00000745, + 0x033, 0x00000002, + 0x03F, 0x00000745, + 0x033, 0x00000003, + 0x03F, 0x00000745, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000745, + 0x033, 0x00000001, + 0x03F, 0x00000745, + 0x033, 0x00000002, + 0x03F, 0x00000745, + 0x033, 0x00000003, + 0x03F, 0x00000745, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000745, + 0x033, 0x00000001, + 0x03F, 0x00000745, + 0x033, 0x00000002, + 0x03F, 0x00000745, + 0x033, 0x00000003, + 0x03F, 0x00000745, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, - 0x03F, 0x000004BB, + 0x03F, 0x00000745, 0x033, 0x00000001, - 0x03F, 0x000004BB, + 0x03F, 0x00000745, 0x033, 0x00000002, - 0x03F, 0x000004BB, + 0x03F, 0x00000745, 0x033, 0x00000003, - 0x03F, 0x000004BB, - 0x0EF, 0x00000000, - 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, + 0x03F, 0x00000745, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000745, 0x033, 0x00000001, @@ -3063,9 +7158,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000745, 0x033, 0x00000003, 0x03F, 0x00000745, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000745, 0x033, 0x00000001, @@ -3074,9 +7167,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000745, 0x033, 0x00000003, 0x03F, 0x00000745, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000745, 0x033, 0x00000001, @@ -3085,9 +7176,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000745, 0x033, 0x00000003, 0x03F, 0x00000745, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000100, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000745, 0x033, 0x00000001, @@ -3096,9 +7185,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000745, 0x033, 0x00000003, 0x03F, 0x00000745, - 0x0EF, 0x00000000, 0xA0000000, 0x00000000, - 0x0EF, 0x00000100, 0x033, 0x00000000, 0x03F, 0x00000F34, 0x033, 0x00000001, @@ -3107,9 +7194,59 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000F34, 0x033, 0x00000003, 0x03F, 0x00000F34, - 0x0EF, 0x00000000, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, + 0x0EF, 0x00000000, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, + 0x081, 0x0000F400, + 0x087, 0x00016040, + 0x051, 0x00000808, + 0x052, 0x00098002, + 0x053, 0x0000FA47, + 0x054, 0x00058032, + 0x056, 0x00051000, + 0x057, 0x0000CE0A, + 0x058, 0x00082030, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x081, 0x0000F400, + 0x087, 0x00016040, + 0x051, 0x00000808, + 0x052, 0x00098002, + 0x053, 0x0000FA47, + 0x054, 0x00058032, + 0x056, 0x00051000, + 0x057, 0x0000CE0A, + 0x058, 0x00082030, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, + 0x081, 0x0000F400, + 0x087, 0x00016040, + 0x051, 0x00000808, + 0x052, 0x00098002, + 0x053, 0x0000FA47, + 0x054, 0x00058032, + 0x056, 0x00051000, + 0x057, 0x0000CE0A, + 0x058, 0x00082030, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, + 0x081, 0x0000F400, + 0x087, 0x00016040, + 0x051, 0x00000808, + 0x052, 0x00098002, + 0x053, 0x0000FA47, + 0x054, 0x00058032, + 0x056, 0x00051000, + 0x057, 0x0000CE0A, + 0x058, 0x00082030, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x081, 0x0000F400, + 0x087, 0x00016040, + 0x051, 0x00000808, + 0x052, 0x00098002, + 0x053, 0x0000FA47, + 0x054, 0x00058032, + 0x056, 0x00051000, + 0x057, 0x0000CE0A, + 0x058, 0x00082030, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808, @@ -3119,7 +7256,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808, @@ -3129,7 +7266,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808, @@ -3139,7 +7276,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808, @@ -3159,8 +7296,8 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x057, 0x0000CE0A, 0x058, 0x00058750, 0xB0000000, 0x00000000, - 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x0EF, 0x00000800, + 0x83000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003, 0x033, 0x00000001, @@ -3183,9 +7320,30 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C, - 0x0EF, 0x00000000, - 0x9000100f, 0x05050505, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000002, + 0x033, 0x00000001, + 0x03F, 0x00000005, + 0x033, 0x00000002, + 0x03F, 0x00000008, + 0x033, 0x00000003, + 0x03F, 0x0000000B, + 0x033, 0x00000004, + 0x03F, 0x0000000E, + 0x033, 0x00000005, + 0x03F, 0x0000002B, + 0x033, 0x00000006, + 0x03F, 0x0000002E, + 0x033, 0x00000007, + 0x03F, 0x00000031, + 0x033, 0x00000008, + 0x03F, 0x0000006E, + 0x033, 0x00000009, + 0x03F, 0x00000071, + 0x033, 0x0000000A, + 0x03F, 0x00000074, + 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003, 0x033, 0x00000001, @@ -3208,9 +7366,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C, - 0x0EF, 0x00000000, - 0x9000100f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, + 0x93000007, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003, 0x033, 0x00000001, @@ -3233,9 +7389,122 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C, - 0x0EF, 0x00000000, - 0x9000200f, 0x00000000, 0x40000000, 0x00000000, - 0x0EF, 0x00000800, + 0x9300000b, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0005142C, + 0x033, 0x00000001, + 0x03F, 0x0005142F, + 0x033, 0x00000002, + 0x03F, 0x00051432, + 0x033, 0x00000003, + 0x03F, 0x00051CA5, + 0x033, 0x00000004, + 0x03F, 0x00051CA8, + 0x033, 0x00000005, + 0x03F, 0x00051CAB, + 0x033, 0x00000006, + 0x03F, 0x00051CEB, + 0x033, 0x00000007, + 0x03F, 0x00051CEE, + 0x033, 0x00000008, + 0x03F, 0x00051CF1, + 0x033, 0x00000009, + 0x03F, 0x00051CF4, + 0x033, 0x0000000A, + 0x03F, 0x00051CF7, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000006, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x00000003, + 0x033, 0x00000001, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000009, + 0x033, 0x00000003, + 0x03F, 0x00000026, + 0x033, 0x00000004, + 0x03F, 0x00000029, + 0x033, 0x00000005, + 0x03F, 0x0000002C, + 0x033, 0x00000006, + 0x03F, 0x0000002F, + 0x033, 0x00000007, + 0x03F, 0x00000033, + 0x033, 0x00000008, + 0x03F, 0x00000036, + 0x033, 0x00000009, + 0x03F, 0x00000039, + 0x033, 0x0000000A, + 0x03F, 0x0000003C, + 0x90000007, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003, 0x033, 0x00000001, @@ -3258,9 +7527,7 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C, - 0x0EF, 0x00000000, 0xA0000000, 0x00000000, - 0x0EF, 0x00000800, 0x033, 0x00000000, 0x03F, 0x0005142C, 0x033, 0x00000001, @@ -3283,6 +7550,10 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x03F, 0x00051CF4, 0x033, 0x0000000A, 0x03F, 0x00051CF7, + 0xB0000000, 0x00000000, + 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, 0x0EF, 0x00000000, 0xB0000000, 0x00000000, 0x0EF, 0x00000010, @@ -3294,7 +7565,11 @@ u4Byte Array_MP_8822B_RadioB[] = { 0x033, 0x000000A2, 0x0EF, 0x00080000, 0x03E, 0x0000593F, + 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000D0F4F, + 0xA0000000, 0x00000000, 0x03F, 0x000C0F4F, + 0xB0000000, 0x00000000, 0x0EF, 0x00000000, 0x033, 0x000000A3, 0x0EF, 0x00080000, @@ -3305,417 +7580,2236 @@ u4Byte Array_MP_8822B_RadioB[] = { }; void -ODM_ReadAndConfig_MP_8822B_RadioB( - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_radiob( + struct PHY_DM_STRUCT *p_dm_odm ) { - u4Byte i = 0; - u1Byte cCond; - BOOLEAN bMatched = TRUE, bSkipped = FALSE; - u4Byte ArrayLen = sizeof(Array_MP_8822B_RadioB)/sizeof(u4Byte); - pu4Byte Array = Array_MP_8822B_RadioB; - - u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8822B_RadioB\n")); - - while ((i + 1) < ArrayLen) { - v1 = Array[i]; - v2 = Array[i + 1]; - - if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ - if (v1 & BIT31) {/* positive condition*/ - cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); - if (cCond == COND_ENDIF) {/*end*/ - bMatched = TRUE; - bSkipped = FALSE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (cCond == COND_ELSE) { /*else*/ - bMatched = bSkipped?FALSE:TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8822b_radiob)/sizeof(u32); + u32 *array = array_mp_8822b_radiob; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_radiob\n")); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped?false:true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); } - } else if (v1 & BIT30) { /*negative condition*/ - if (bSkipped == FALSE) { - if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { - bMatched = TRUE; - bSkipped = TRUE; + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; } else { - bMatched = FALSE; - bSkipped = FALSE; + is_matched = false; + is_skipped = false; } } else - bMatched = FALSE; + is_matched = false; } } else { - if (bMatched) - odm_ConfigRF_RadioB_8822B(pDM_Odm, v1, v2); + if (is_matched) + odm_config_rf_radio_b_8822b(p_dm_odm, v1, v2); } i = i + 2; } } -u4Byte -ODM_GetVersion_MP_8822B_RadioB(void) +u32 +odm_get_version_mp_8822b_radiob(void) +{ + return 85; +} + +/****************************************************************************** +* txpowertrack.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, + {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, + {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20}, + {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +odm_read_and_config_mp_8822b_txpowertrack( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_8822b, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpowertrack_type0.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type0_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type0_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type0_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type0_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type0_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type0_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type0_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type0_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type0_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type0_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type0_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type0_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +odm_read_and_config_mp_8822b_txpowertrack_type0( + struct PHY_DM_STRUCT *p_dm_odm +) { - return 50; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** -* TxPowerTrack.TXT +* txpowertrack_type1.TXT ******************************************************************************/ -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type1_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, }; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type1_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17}, }; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type1_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, }; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type1_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20}, {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18}, {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18}, }; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type1_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type1_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type1_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type1_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type1_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type1_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type1_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type1_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack( - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpowertrack_type1( + struct PHY_DM_STRUCT *p_dm_odm ) { - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_8822B, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** -* TxPowerTrack_type0.TXT +* txpowertrack_type10.TXT ******************************************************************************/ -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type0_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type10_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, }; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type0_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type10_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, }; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type0_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type10_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, }; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type0_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type10_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, }; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type0_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type0_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type0_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type0_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type10_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type10_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type10_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type10_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type10_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type10_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type10_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type10_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type0( - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpowertrack_type10( + struct PHY_DM_STRUCT *p_dm_odm ) { - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type0_8822B, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** -* TxPowerTrack_type1.TXT +* txpowertrack_type11.TXT ******************************************************************************/ -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type1_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, - {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type11_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, }; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type1_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, - {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17}, +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type11_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, }; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type1_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, - {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type11_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, }; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type1_8822B[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20}, - {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18}, - {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18}, +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type11_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type11_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type11_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type11_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type11_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type11_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type11_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type11_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type11_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +odm_read_and_config_mp_8822b_txpowertrack_type11( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpowertrack_type12.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type12_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type12_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type12_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type12_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type12_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type12_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type12_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type12_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type12_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type12_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type12_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type12_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; + +void +odm_read_and_config_mp_8822b_txpowertrack_type12( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpowertrack_type13.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type13_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type13_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type13_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type13_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type13_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type13_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type13_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type13_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type13_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type13_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type13_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type13_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +odm_read_and_config_mp_8822b_txpowertrack_type13( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpowertrack_type14.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type14_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type14_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type14_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type14_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type14_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type14_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type14_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type14_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type14_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type14_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type14_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type14_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +odm_read_and_config_mp_8822b_txpowertrack_type14( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpowertrack_type2.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type2_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type2_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type2_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type2_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, }; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type1_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type1_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type1_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type1_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type2_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type2_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type2_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type2_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type2_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type2_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type2_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type2_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type1( - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpowertrack_type2( + struct PHY_DM_STRUCT *p_dm_odm ) { - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type1_8822B, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** -* TxPowerTrack_Type3_Type5.TXT +* txpowertrack_type3_type5.TXT ******************************************************************************/ -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_Type5_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type3_type5_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, }; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_Type5_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type3_type5_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, }; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_Type5_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type3_type5_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, }; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_Type5_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type3_type5_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, }; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_Type5_8822B[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; + +void +odm_read_and_config_mp_8822b_txpowertrack_type3_type5( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpowertrack_type4.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type4_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type4_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type4_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type4_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type4_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type4_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type4_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type4_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type4_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type4_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type4_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type4_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_Type3_Type5( - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpowertrack_type4( + struct PHY_DM_STRUCT *p_dm_odm ) { - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_Type3_Type5_8822B, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** -* TxPowerTrack_type6.TXT +* txpowertrack_type6.TXT ******************************************************************************/ -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type6_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type6_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17}, }; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type6_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type6_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21}, {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21}, }; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type6_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type6_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15}, {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, }; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type6_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type6_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21}, {0, 1, 2, 2, 3, 4, 4, 5, 7, 7, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21}, {0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 20, 20, 20, 20}, }; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type6_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type6_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type6_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type6_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type6_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type6_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type6_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type6_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type6_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type6_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type6_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type6_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type6( - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpowertrack_type6( + struct PHY_DM_STRUCT *p_dm_odm ) { - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type6_8822B, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** -* TxPowerTrack_type7.TXT +* txpowertrack_type7.TXT ******************************************************************************/ -u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type7_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type7_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17}, }; -u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type7_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type7_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21}, {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21}, }; -u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type7_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type7_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15}, {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, }; -u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type7_8822B[][DELTA_SWINGIDX_SIZE] = { +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type7_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21}, {0, 1, 2, 2, 3, 4, 4, 5, 7, 7, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21}, {0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 20, 20, 20, 20}, }; -u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type7_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type7_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type7_8822B[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type7_8822B[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type7_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type7_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type7_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type7_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type7_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type7_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type7_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type7_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +odm_read_and_config_mp_8822b_txpowertrack_type7( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpowertrack_type8.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type8_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type8_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type8_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type8_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type8_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type8_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type8_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type8_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type8_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type8_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type8_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type8_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type7( - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpowertrack_type8( + struct PHY_DM_STRUCT *p_dm_odm ) { - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8822B\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpowertrack_type9.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type9_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type9_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type9_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type9_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type9_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type9_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type9_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type9_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type9_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type9_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type9_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type9_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; + +void +odm_read_and_config_mp_8822b_txpowertrack_type9( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpwr_lmt.TXT +******************************************************************************/ + +const char *array_mp_8822b_txpwr_lmt[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", 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"2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", 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"HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", 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"26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", 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"120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +odm_read_and_config_mp_8822b_txpwr_lmt( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt)/sizeof(u8); + u8 *array = (u8 *)array_mp_8822b_txpwr_lmt; +#else + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt)/sizeof(u8 *); + u8 **array = (u8 **)array_mp_8822b_txpwr_lmt; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + + PlatformZeroMemory(p_hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + p_hal_data->nLinesReadPwrLmt = array_len/7; +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_txpwr_lmt\n")); + + for (i = 0; i < array_len; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u8 regulation = array[i]; + u8 band = array[i+1]; + u8 bandwidth = array[i+2]; + u8 rate = array[i+3]; + u8 rf_path = array[i+4]; + u8 chnl = array[i+5]; + u8 val = array[i+6]; +#else + u8 *regulation = array[i]; + u8 *band = array[i+1]; + u8 *bandwidth = array[i+2]; + u8 *rate = array[i+3]; + u8 *rf_path = array[i+4]; + u8 *chnl = array[i+5]; + u8 *val = array[i+6]; +#endif + + odm_config_bb_txpwr_lmt_8822b(p_dm_odm, regulation, band, bandwidth, rate, rf_path, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)p_hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rf_path, chnl, val); +#endif + } + +} + +/****************************************************************************** +* txpwr_lmt_type5.TXT +******************************************************************************/ + +const char *array_mp_8822b_txpwr_lmt_type5[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type5( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type5)/sizeof(u8); + u8 *array = (u8 *)array_mp_8822b_txpwr_lmt_type5; +#else + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type5)/sizeof(u8 *); + u8 **array = (u8 **)array_mp_8822b_txpwr_lmt_type5; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + + PlatformZeroMemory(p_hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + p_hal_data->nLinesReadPwrLmt = array_len/7; +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_txpwr_lmt_type5\n")); + + for (i = 0; i < array_len; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u8 regulation = array[i]; + u8 band = array[i+1]; + u8 bandwidth = array[i+2]; + u8 rate = array[i+3]; + u8 rf_path = array[i+4]; + u8 chnl = array[i+5]; + u8 val = array[i+6]; +#else + u8 *regulation = array[i]; + u8 *band = array[i+1]; + u8 *bandwidth = array[i+2]; + u8 *rate = array[i+3]; + u8 *rf_path = array[i+4]; + u8 *chnl = array[i+5]; + u8 *val = array[i+6]; +#endif + + odm_config_bb_txpwr_lmt_8822b(p_dm_odm, regulation, band, bandwidth, rate, rf_path, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)p_hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rf_path, chnl, val); +#endif + } - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE*3); - ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_type7_8822B, DELTA_SWINGIDX_SIZE*3); } #endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8822b/halhwimg8822b_rf.h b/hal/phydm/rtl8822b/halhwimg8822b_rf.h index adebd0d..203aec1 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_rf.h +++ b/hal/phydm/rtl8822b/halhwimg8822b_rf.h @@ -1,108 +1,213 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.22*/ +/****************************************************************************** +* +* Copyright(c) 2007 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ + +/*Image2HeaderVersion: R2 1.2.1*/ #if (RTL8822B_SUPPORT == 1) #ifndef __INC_MP_RF_HW_IMG_8822B_H #define __INC_MP_RF_HW_IMG_8822B_H /****************************************************************************** -* RadioA.TXT +* radioa.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_radioa(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8822b_radioa(void); + +/****************************************************************************** +* radiob.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_radiob(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8822b_radiob(void); + +/****************************************************************************** +* txpowertrack.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpowertrack(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8822b_txpowertrack(void); + +/****************************************************************************** +* txpowertrack_type0.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpowertrack_type0(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8822b_txpowertrack_type0(void); + +/****************************************************************************** +* txpowertrack_type1.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpowertrack_type1(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8822b_txpowertrack_type1(void); + +/****************************************************************************** +* txpowertrack_type10.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpowertrack_type10(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8822b_txpowertrack_type10(void); + +/****************************************************************************** +* txpowertrack_type11.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpowertrack_type11(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8822b_txpowertrack_type11(void); + +/****************************************************************************** +* txpowertrack_type12.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpowertrack_type12(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8822b_txpowertrack_type12(void); + +/****************************************************************************** +* txpowertrack_type13.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpowertrack_type13(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8822b_txpowertrack_type13(void); + +/****************************************************************************** +* txpowertrack_type14.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpowertrack_type14(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8822b_txpowertrack_type14(void); + +/****************************************************************************** +* txpowertrack_type2.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpowertrack_type2(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8822b_txpowertrack_type2(void); + +/****************************************************************************** +* txpowertrack_type3_type5.TXT ******************************************************************************/ void -ODM_ReadAndConfig_MP_8822B_RadioA(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpowertrack_type3_type5(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte ODM_GetVersion_MP_8822B_RadioA(void); +u32 odm_get_version_mp_8822b_txpowertrack_type3_type5(void); /****************************************************************************** -* RadioB.TXT +* txpowertrack_type4.TXT ******************************************************************************/ void -ODM_ReadAndConfig_MP_8822B_RadioB(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpowertrack_type4(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte ODM_GetVersion_MP_8822B_RadioB(void); +u32 odm_get_version_mp_8822b_txpowertrack_type4(void); /****************************************************************************** -* TxPowerTrack.TXT +* txpowertrack_type6.TXT ******************************************************************************/ void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpowertrack_type6(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack(void); +u32 odm_get_version_mp_8822b_txpowertrack_type6(void); /****************************************************************************** -* TxPowerTrack_type0.TXT +* txpowertrack_type7.TXT ******************************************************************************/ void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type0(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpowertrack_type7(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type0(void); +u32 odm_get_version_mp_8822b_txpowertrack_type7(void); /****************************************************************************** -* TxPowerTrack_type1.TXT +* txpowertrack_type8.TXT ******************************************************************************/ void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type1(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpowertrack_type8(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type1(void); +u32 odm_get_version_mp_8822b_txpowertrack_type8(void); /****************************************************************************** -* TxPowerTrack_Type3_Type5.TXT +* txpowertrack_type9.TXT ******************************************************************************/ void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_Type3_Type5(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpowertrack_type9(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_Type3_Type5(void); +u32 odm_get_version_mp_8822b_txpowertrack_type9(void); /****************************************************************************** -* TxPowerTrack_type6.TXT +* txpwr_lmt.TXT ******************************************************************************/ void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type6(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpwr_lmt(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type6(void); +u32 odm_get_version_mp_8822b_txpwr_lmt(void); /****************************************************************************** -* TxPowerTrack_type7.TXT +* txpwr_lmt_type5.TXT ******************************************************************************/ void -ODM_ReadAndConfig_MP_8822B_TxPowerTrack_type7(/* TC: Test Chip, MP: MP Chip*/ - IN PDM_ODM_T pDM_Odm +odm_read_and_config_mp_8822b_txpwr_lmt_type5(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm ); -u4Byte ODM_GetVersion_MP_8822B_TxPowerTrack_type7(void); +u32 odm_get_version_mp_8822b_txpwr_lmt_type5(void); #endif #endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8822b/phydm_hal_api8822b.c b/hal/phydm/rtl8822b/phydm_hal_api8822b.c index 6f08a71..c0f33ad 100644 --- a/hal/phydm/rtl8822b/phydm_hal_api8822b.c +++ b/hal/phydm/rtl8822b/phydm_hal_api8822b.c @@ -1,7 +1,7 @@ /****************************************************************************** * * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -17,570 +17,642 @@ * * ******************************************************************************/ - #include "mp_precomp.h" #include "../phydm_precomp.h" -#if (RTL8822B_SUPPORT == 1) +#if (RTL8822B_SUPPORT == 1) +#if (PHYDM_FW_API_ENABLE_8822B == 1) /* ======================================================================== */ /* These following functions can be used for PHY DM only*/ -u4Byte reg82c_8822b; -u4Byte reg838_8822b; -u4Byte reg830_8822b; -u4Byte reg83c_8822b; -u4Byte rega20_8822b; -u4Byte rega24_8822b; -u4Byte rega28_8822b; -ODM_BW_E bw_8822b; -u1Byte central_ch_8822b; +enum odm_bw_e bw_8822b; +u8 central_ch_8822b; + +#if !(DM_ODM_SUPPORT_TYPE == ODM_CE) + u32 cca_ifem_bcut[3][4] = { + {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ + {0x79a0ea2a, 0x79a0ea2a, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ + {0x87766441, 0x87746341, 0x87765541, 0x87746341} /*Reg838*/ + }; + u32 cca_efem_bcut[3][4] = { + {0x75B76010, 0x75B76010, 0x75B76010, 0x75B75010}, /*Reg82C*/ + {0x79a0ea2a, 0x79a0ea2a, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ + {0x87766451, 0x87766431, 0x87766451, 0x87766431} /*Reg838*/ + }; +#endif + +u32 cca_ifem_ccut[3][4] = { + {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ + {0x79a0ea2a, 0x79A0EA2C, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ + {0x87765541, 0x87746341, 0x87765541, 0x87746341} /*Reg838*/ +}; +u32 cca_efem_ccut[3][4] = { + {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/ + {0x79A0EA28, 0x79A0EA2C, 0x79A0EA28, 0x79a0ea2a}, /*Reg830*/ + {0x87766451, 0x87766431, 0x87766451, 0x87766431} /*Reg838*/ +}; +u32 cca_ifem_ccut_rfetype[3][4] = { + {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/ + {0x79a0ea2a, 0x97A0EA2C, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ + {0x87765541, 0x86666341, 0x87765561, 0x86666361} /*Reg838*/ +}; + +__iram_odm_func__ +void +phydm_igi_toggle_8822b( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 igi = 0x20; + + igi = odm_get_bb_reg(p_dm_odm, 0xc50, 0x7f); + odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, (igi - 2)); + odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, igi); + odm_set_bb_reg(p_dm_odm, 0xe50, 0x7f, (igi - 2)); + odm_set_bb_reg(p_dm_odm, 0xe50, 0x7f, igi); +} + +__iram_odm_func__ +u32 +phydm_check_bit_mask(u32 bit_mask, u32 data_original, u32 data) +{ + u8 bit_shift; + if (bit_mask != 0xfffff) { + for (bit_shift = 0; bit_shift <= 19; bit_shift++) { + if (((bit_mask >> bit_shift) & 0x1) == 1) + break; + } + return ((data_original)&(~bit_mask)) | (data << bit_shift); + } + return data; +} -BOOLEAN +__iram_odm_func__ +boolean phydm_rfe_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte channel - ) + struct PHY_DM_STRUCT *p_dm_odm, + u8 channel +) { - if (pDM_Odm->RFEType == 4) { + + /* Distinguish the setting band */ + if (channel <= 14) + p_dm_odm->rfe_hwsetting_band = 1; + else + p_dm_odm->rfe_hwsetting_band = 2; + + /* HW Setting for each RFE type */ + if ((p_dm_odm->rfe_type == 4) || (p_dm_odm->rfe_type == 11)) { /*TRSW = trsw_forced_BT ? 0x804[0] : (0xCB8[2] ? 0xCB8[0] : trsw_lut); trsw_lut = TXON*/ /*TRSWB = trsw_forced_BT ? (~0x804[0]) : (0xCB8[2] ? 0xCB8[1] : trswb_lut); trswb_lut = TXON*/ /*trsw_forced_BT = 0x804[1] ? 0 : (~GNT_WL); */ - /*ODM_SetBBReg(pDM_Odm, 0x804, (BIT1|BIT0), 0x0);*/ + /*odm_set_bb_reg(p_dm_odm, 0x804, (BIT1|BIT0), 0x0);*/ /* Default setting is in PHY parameters */ - + if (channel <= 14) { /* signal source */ - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x745774); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x745774); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57); + odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x745774); + odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x745774); + odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x57); + odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x57); /* inverse or not */ - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x8); - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x2); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x8); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x2); + odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x8); + odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(11) | BIT(10)), 0x2); + odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x8); + odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(11) | BIT(10)), 0x2); /* antenna switch table */ - if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) { + if ((p_dm_odm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) || (p_dm_odm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) { /* 2TX or 2RX */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf050); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf050); - } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) { + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xf050); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xf050); + } else if (p_dm_odm->rx_ant_status == p_dm_odm->tx_ant_status) { /* TXA+RXA or TXB+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf055); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf055); + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xf055); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xf055); } else { /* TXB+RXA or TXA+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf550); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf550); + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xf550); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xf550); } - + } else if (channel > 35) { /* signal source */ - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x477547); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x477547); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75); + odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x477547); + odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x477547); + odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x75); + odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x75); /* inverse or not */ - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); + odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(11) | BIT(10)), 0x0); /* antenna switch table */ - if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) { + if ((p_dm_odm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) || (p_dm_odm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) { /* 2TX or 2RX */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa501); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa501); - } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) { + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa501); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa501); + } else if (p_dm_odm->rx_ant_status == p_dm_odm->tx_ant_status) { /* TXA+RXA or TXB+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa500); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa500); + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa500); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa500); } else { /* TXB+RXA or TXA+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa005); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa005); + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa005); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa005); } } else - return FALSE; + return false; - - } else { - if (((pDM_Odm->CutVersion == ODM_CUT_A) || (pDM_Odm->CutVersion == ODM_CUT_B)) && (pDM_Odm->RFEType < 2)) { + + } else if ((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 2) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7) || (p_dm_odm->rfe_type == 9)) { + /* eFem */ + if ((p_dm_odm->cut_version == ODM_CUT_B) && (p_dm_odm->rfe_type < 2)) { if (channel <= 14) { /* signal source */ - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x704570); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x704570); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45); + odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x704570); + odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x704570); + odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x45); + odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x45); } else if (channel > 35) { - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x174517); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x174517); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45); + odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x174517); + odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x174517); + odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x45); + odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x45); } else - return FALSE; + return false; /* delay 400ns for PAPE */ - ODM_SetBBReg(pDM_Odm, 0x810, bMaskByte3|BIT20|BIT21|BIT22|BIT23, 0x211); + odm_set_bb_reg(p_dm_odm, 0x810, MASKBYTE3 | BIT(20) | BIT(21) | BIT(22) | BIT(23), 0x211); /* antenna switch table */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa555); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa555); + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa555); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa555); /* inverse or not */ - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); + odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(11) | BIT(10)), 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Using old RFE control pin setting for A-cut and B-cut\n", __func__)); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Using old RFE control pin setting for A-cut and B-cut\n", __func__)); } else { if (channel <= 14) { /* signal source */ - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x745774); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x745774); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57); + odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x705770); + odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x705770); + odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x57); + odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x57); + odm_set_bb_reg(p_dm_odm, 0xcb8, BIT(4), 0); + odm_set_bb_reg(p_dm_odm, 0xeb8, BIT(4), 0); } else if (channel > 35) { /* signal source */ - ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x477547); - ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x477547); - ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75); - ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75); + odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x177517); + odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x177517); + odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x75); + odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x75); + odm_set_bb_reg(p_dm_odm, 0xcb8, BIT(5), 0); + odm_set_bb_reg(p_dm_odm, 0xeb8, BIT(5), 0); } else - return FALSE; + return false; /* inverse or not */ - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0); - ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0); + odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(11) | BIT(10)), 0x0); /* delay 400ns for PAPE */ - /* ODM_SetBBReg(pDM_Odm, 0x810, bMaskByte3|BIT20|BIT21|BIT22|BIT23, 0x211); */ + /* odm_set_bb_reg(p_dm_odm, 0x810, MASKBYTE3|BIT20|BIT21|BIT22|BIT23, 0x211); */ /* antenna switch table */ - if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) { + if ((p_dm_odm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) || (p_dm_odm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) { /* 2TX or 2RX */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa501); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa501); - } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) { + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa501); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa501); + } else if (p_dm_odm->rx_ant_status == p_dm_odm->tx_ant_status) { /* TXA+RXA or TXB+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa500); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa500); + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa500); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa500); } else { /* TXB+RXA or TXA+RXB */ - ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa005); - ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa005); + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa005); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa005); } } - } + } else if ((p_dm_odm->rfe_type == 0) || (p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5) || (p_dm_odm->rfe_type == 8) || (p_dm_odm->rfe_type == 10) || (p_dm_odm->rfe_type == 12)) { + /* iFEM */ + if (channel <= 14) { + /* signal source */ + odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x745774); + odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x745774); + odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x57); + odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x57); + } else if (channel > 35) { + /* signal source */ + odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x477547); + odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x477547); + odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x75); + odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x75); + + } else + return false; + + /* inverse or not */ + odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(11) | BIT(10)), 0x0); + + /* antenna switch table */ + if (channel <= 14) { + if ((p_dm_odm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) || (p_dm_odm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) { + /* 2TX or 2RX */ + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa501); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa501); + } else if (p_dm_odm->rx_ant_status == p_dm_odm->tx_ant_status) { + /* TXA+RXA or TXB+RXB */ + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa500); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa500); + } else { + /* TXB+RXA or TXA+RXB */ + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa005); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa005); + } + } else if (channel > 35) { + odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa5a5); + odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa5a5); + } + } + /* chip top mux */ - ODM_SetBBReg(pDM_Odm, 0x64, BIT29|BIT28, 0x3); - ODM_SetBBReg(pDM_Odm, 0x4c, BIT26|BIT25, 0x0); - ODM_SetBBReg(pDM_Odm, 0x40, BIT2, 0x1); + odm_set_bb_reg(p_dm_odm, 0x64, BIT(29) | BIT(28), 0x3); + odm_set_bb_reg(p_dm_odm, 0x4c, BIT(26) | BIT(25), 0x0); + odm_set_bb_reg(p_dm_odm, 0x40, BIT(2), 0x1); /* from s0 or s1 */ - ODM_SetBBReg(pDM_Odm, 0x1990, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x30); - ODM_SetBBReg(pDM_Odm, 0x1990, (BIT11|BIT10), 0x3); + odm_set_bb_reg(p_dm_odm, 0x1990, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x30); + odm_set_bb_reg(p_dm_odm, 0x1990, (BIT(11) | BIT(10)), 0x3); /* input or output */ - ODM_SetBBReg(pDM_Odm, 0x974, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x3f); - ODM_SetBBReg(pDM_Odm, 0x974, (BIT11|BIT10), 0x3); + odm_set_bb_reg(p_dm_odm, 0x974, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x3f); + odm_set_bb_reg(p_dm_odm, 0x974, (BIT(11) | BIT(10)), 0x3); + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update RFE control pin setting (ch%d, tx_path 0x%x, rx_path 0x%x)\n", __func__, channel, p_dm_odm->tx_ant_status, p_dm_odm->rx_ant_status)); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update RFE control pin setting (ch%d, TxPath 0x%x, RxPath 0x%x)\n", __func__, channel, pDM_Odm->TXAntStatus, pDM_Odm->RXAntStatus)); + return true; +} - return TRUE; +__iram_odm_func__ +u8 +phydm_is_dfs_channel(u8 channel_num) +{ + if(channel_num >= 52 && channel_num <= 140) + return 1; + else + return 0; } -VOID +__iram_odm_func__ +void phydm_ccapar_by_rfe_8822b( - IN PDM_ODM_T pDM_Odm - ) + struct PHY_DM_STRUCT *p_dm_odm +) { + u32 cca_ifem[3][4], cca_efem[3][4]; + u8 col; + u32 reg82c, reg830, reg838; + boolean is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false; + #if !(DM_ODM_SUPPORT_TYPE == ODM_CE) - u4Byte cca_ifem_bcut[12][4] = { - /*20M*/ - {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/ - /*40M*/ - {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ - {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/ - {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/ - /*80M*/ - {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x00000000, 0x87746641, 0x00000000, 0x87746641}, /*Reg838*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000} }; /*Reg83C*/ - u4Byte cca_efem_bcut[12][4] = { - /*20M*/ - {0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/ - /*40M*/ - {0x75A75010, 0x75A75010, 0x75A75010, 0x75A75010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/ - /*80M*/ - {0x75BA7010, 0x75BA7010, 0x75BA7010, 0x75BA7010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/ -#endif - u4Byte cca_ifem_ccut[12][4] = { - /*20M*/ - {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/ - /*40M*/ - {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/ - {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/ - {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/ - /*80M*/ - {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x00000000, 0x87746641, 0x00000000, 0x87746641}, /*Reg838*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/ - u4Byte cca_efem_ccut[12][4] = { - /*20M*/ - {0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/ - {0x9194b2b9, 0x9194b2b9, 0x9194b2b9, 0x9194b2b9}, /*Reg83C*/ - /*40M*/ - {0x75A85010, 0x75A75010, 0x75A85010, 0x75A75010}, /*Reg82C*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/ - {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/ - /*80M*/ - {0x76BA7010, 0x75BA7010, 0x76BA7010, 0x75BA7010}, /*Reg82C*/ - {0x79a0ea28, 0x00000000, 0x79a0ea28, 0x00000000}, /*Reg830*/ - {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/ - {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/ - u4Byte cca_ifem[12][4], cca_efem[12][4]; - u1Byte row, col; - u4Byte reg82c, reg830, reg838, reg83c; - - if (pDM_Odm->CutVersion == ODM_CUT_A) - return; -#if !(DM_ODM_SUPPORT_TYPE == ODM_CE) - if (pDM_Odm->CutVersion == ODM_CUT_B) { - ODM_MoveMemory(pDM_Odm, cca_efem, cca_efem_bcut, 48*4); - ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_bcut, 48*4); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Bcut\n", __func__)); + if (p_dm_odm->cut_version == ODM_CUT_B) { + odm_move_memory(p_dm_odm, cca_efem, cca_efem_bcut, 12 * 4); + odm_move_memory(p_dm_odm, cca_ifem, cca_ifem_bcut, 12 * 4); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Bcut\n", __func__)); } else #endif { - ODM_MoveMemory(pDM_Odm, cca_efem, cca_efem_ccut, 48*4); - ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_ccut, 48*4); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Ccut\n", __func__)); - } - - if (bw_8822b == ODM_BW20M) - row = 0; - else if (bw_8822b == ODM_BW40M) - row = 4; - else - row = 8; + odm_move_memory(p_dm_odm, cca_efem, cca_efem_ccut, 12 * 4); + if ((p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5)) { + odm_move_memory(p_dm_odm, cca_ifem, cca_ifem_ccut_rfetype, 12 * 4); + is_rfe_type = true; + } else + odm_move_memory(p_dm_odm, cca_ifem, cca_ifem_ccut, 12 * 4); + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Ccut\n", __func__)); + } if (central_ch_8822b <= 14) { - if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) - col = 0; + if ((p_dm_odm->rx_ant_status == ODM_RF_A) || (p_dm_odm->rx_ant_status == ODM_RF_B)) + col = 0; /*1R 2G*/ else - col = 1; + col = 1; /*2R 2G*/ } else { - if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) - col = 2; + if ((p_dm_odm->rx_ant_status == ODM_RF_A) || (p_dm_odm->rx_ant_status == ODM_RF_B)) + col = 2; /*1R 5G*/ else - col = 3; + col = 3; /*2R 5G*/ } - if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 4) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7)) { - /*eFEM => RFE type 1 & RFE type 4 & RFE type 6 & RFE type 7*/ - reg82c = (cca_efem[row][col] != 0)?cca_efem[row][col]:reg82c_8822b; - reg830 = (cca_efem[row + 1][col] != 0)?cca_efem[row + 1][col]:reg830_8822b; - reg838 = (cca_efem[row + 2][col] != 0)?cca_efem[row + 2][col]:reg838_8822b; - reg83c = (cca_efem[row + 3][col] != 0)?cca_efem[row + 3][col]:reg83c_8822b; - } else if (pDM_Odm->RFEType == 2) { - /*5G eFEM, 2G iFEM => RFE type 2*/ + if ((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 4) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7) || (p_dm_odm->rfe_type == 11)) { + /*eFEM => RFE type 1 & RFE type 4 & RFE type 6 & RFE type 7 & RFE type 11*/ + reg82c = cca_efem[0][col]; + reg830 = cca_efem[1][col]; + reg838 = cca_efem[2][col]; + is_efem_cca = true; + } else if ((p_dm_odm->rfe_type == 2) || (p_dm_odm->rfe_type == 9)) { + /*5G eFEM, 2G iFEM => RFE type 2, 5G eFEM => RFE type 9 */ if (central_ch_8822b <= 14) { - reg82c = (cca_ifem[row][col] != 0)?cca_ifem[row][col]:reg82c_8822b; - reg830 = (cca_ifem[row + 1][col] != 0)?cca_ifem[row + 1][col]:reg830_8822b; - reg838 = (cca_ifem[row + 2][col] != 0)?cca_ifem[row + 2][col]:reg838_8822b; - reg83c = (cca_ifem[row + 3][col] != 0)?cca_ifem[row + 3][col]:reg83c_8822b; + reg82c = cca_ifem[0][col]; + reg830 = cca_ifem[1][col]; + reg838 = cca_ifem[2][col]; + is_ifem_cca = true; } else { - reg82c = (cca_efem[row][col] != 0)?cca_efem[row][col]:reg82c_8822b; - reg830 = (cca_efem[row + 1][col] != 0)?cca_efem[row + 1][col]:reg830_8822b; - reg838 = (cca_efem[row + 2][col] != 0)?cca_efem[row + 2][col]:reg838_8822b; - reg83c = (cca_efem[row + 3][col] != 0)?cca_efem[row + 3][col]:reg83c_8822b; + reg82c = cca_efem[0][col]; + reg830 = cca_efem[1][col]; + reg838 = cca_efem[2][col]; + is_efem_cca = true; } } else { - /*iFEM =>RFEtype 3 & RFE type 5 & RFE type -0*/ - reg82c = (cca_ifem[row][col] != 0)?cca_ifem[row][col]:reg82c_8822b; - reg830 = (cca_ifem[row + 1][col] != 0)?cca_ifem[row + 1][col]:reg830_8822b; - reg838 = (cca_ifem[row + 2][col] != 0)?cca_ifem[row + 2][col]:reg838_8822b; - reg83c = (cca_ifem[row + 3][col] != 0)?cca_ifem[row + 3][col]:reg83c_8822b; + /* iFEM =>RFEtype 3 & RFE type 5 & RFE type 0 & RFE type 8 & RFE type 10 & RFE type 12*/ + reg82c = cca_ifem[0][col]; + reg830 = cca_ifem[1][col]; + reg838 = cca_ifem[2][col]; + is_ifem_cca = true; } - - ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c); - ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, reg830); - ODM_SetBBReg(pDM_Odm, 0x838, bMaskDWord, reg838); - ODM_SetBBReg(pDM_Odm, 0x83c, bMaskDWord, reg83c); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: (Pkt%d, Intf%d, RFE%d), row = %d, col = %d\n", - __func__, pDM_Odm->PackageType, pDM_Odm->SupportInterface, pDM_Odm->RFEType, row, col)); -} -VOID -phydm_ccapar_by_bw_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_BW_E bandwidth - ) -{ - u4Byte reg82c; + odm_set_bb_reg(p_dm_odm, 0x82c, MASKDWORD, reg82c); + if (is_ifem_cca == true) + if (((p_dm_odm->cut_version == ODM_CUT_B) && (col == 1 || col == 3) && (bw_8822b == ODM_BW40M)) || + ((is_rfe_type == false) && (col == 3) && (bw_8822b == ODM_BW40M)) || + ((p_dm_odm->rfe_type == 5) && (col == 3))) + odm_set_bb_reg(p_dm_odm, 0x830, MASKDWORD, 0x79a0ea28); + else + odm_set_bb_reg(p_dm_odm, 0x830, MASKDWORD, reg830); + else + odm_set_bb_reg(p_dm_odm, 0x830, MASKDWORD, reg830); - if (pDM_Odm->CutVersion != ODM_CUT_A) - return; + odm_set_bb_reg(p_dm_odm, 0x838, MASKDWORD, reg838); - /* A-cut */ - reg82c = ODM_GetBBReg(pDM_Odm, 0x82c, bMaskDWord); + if ((is_efem_cca == true) && !(p_dm_odm->cut_version == ODM_CUT_B)) + odm_set_bb_reg(p_dm_odm, 0x83c, MASKDWORD, 0x9194b2b9); - if (bandwidth == ODM_BW20M) { - /* 82c[15:12] = 4 */ - /* 82c[27:24] = 6 */ - - reg82c &= (~(0x0f00f000)); - reg82c |= ((0x4) << 12); - reg82c |= ((0x6) << 24); - } else if (bandwidth == ODM_BW40M) { - /* 82c[19:16] = 9 */ - /* 82c[27:24] = 6 */ + if (phydm_is_dfs_channel(central_ch_8822b) && (bw_8822b == ODM_BW80M)) + odm_set_bb_reg(p_dm_odm, 0x838, 0x1, 0); - reg82c &= (~(0x0f0f0000)); - reg82c |= ((0x9) << 16); - reg82c |= ((0x6) << 24); - } else if (bandwidth == ODM_BW80M) { - /* 82c[15:12] 7 */ - /* 82c[19:16] b */ - /* 82c[23:20] d */ - /* 82c[27:24] 3 */ - - reg82c &= (~(0x0ffff000)); - reg82c |= ((0xdb7) << 12); - reg82c |= ((0x3) << 24); - } - - ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_CcaParByBw_8822b(): Update CCA parameters for Acut\n")); - -} - -VOID -phydm_ccapar_by_rxpath_8822b( - IN PDM_ODM_T pDM_Odm - ) -{ - - if (pDM_Odm->CutVersion != ODM_CUT_A) - return; - - if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) { - /* 838[7:4] = 8 */ - /* 838[11:8] = 7 */ - /* 838[15:12] = 6 */ - /* 838[19:16] = 7 */ - /* 838[23:20] = 7 */ - /* 838[27:24] = 7 */ - ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x777678); - } else { - /* 838[7:4] = 3 */ - /* 838[11:8] = 3 */ - /* 838[15:12] = 6 */ - /* 838[19:16] = 6 */ - /* 838[23:20] = 7 */ - /* 838[27:24] = 7 */ - ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x776633); - } - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_CcaParByRxPath_8822b(): Update CCA parameters for Acut\n")); - + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: (Pkt%d, Intf%d, RFE%d), col = %d\n", + __func__, p_dm_odm->package_type, p_dm_odm->support_interface, p_dm_odm->rfe_type, col)); } -VOID +__iram_odm_func__ +void phydm_rxdfirpar_by_bw_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_BW_E bandwidth - ) + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_bw_e bandwidth +) { if (bandwidth == ODM_BW40M) { /* RX DFIR for BW40 */ - ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x0); - ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0); - ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x0); + odm_set_bb_reg(p_dm_odm, 0x948, BIT(29) | BIT(28), 0x1); + odm_set_bb_reg(p_dm_odm, 0x94c, BIT(29) | BIT(28), 0x0); + odm_set_bb_reg(p_dm_odm, 0xc20, BIT(31), 0x0); + odm_set_bb_reg(p_dm_odm, 0xe20, BIT(31), 0x0); } else if (bandwidth == ODM_BW80M) { /* RX DFIR for BW80 */ - ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2); - ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0); - ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x0); + odm_set_bb_reg(p_dm_odm, 0x948, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(p_dm_odm, 0x94c, BIT(29) | BIT(28), 0x1); + odm_set_bb_reg(p_dm_odm, 0xc20, BIT(31), 0x0); + odm_set_bb_reg(p_dm_odm, 0xe20, BIT(31), 0x0); } else { /* RX DFIR for BW20, BW10 and BW5*/ - ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2); - ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x2); - ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x1); - ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x1); + odm_set_bb_reg(p_dm_odm, 0x948, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(p_dm_odm, 0x94c, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(p_dm_odm, 0xc20, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xe20, BIT(31), 0x1); } } -BOOLEAN +__iram_odm_func__ +boolean phydm_write_txagc_1byte_8822b( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) + struct PHY_DM_STRUCT *p_dm_odm, + u32 power_index, + enum odm_rf_radio_path_e path, + u8 hw_rate +) { - u4Byte offset_txagc[2] = {0x1d00, 0x1d80}; - u1Byte rate_idx = (HwRate & 0xfc), i; - u1Byte rate_offset = (HwRate & 0x3); - u4Byte txagc_content = 0x0; +#if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1) + + u32 offset_txagc[2] = {0x1d00, 0x1d80}; + u8 rate_idx = (hw_rate & 0xfc), i; + u8 rate_offset = (hw_rate & 0x3); + u32 txagc_content = 0x0; /* For debug command only!!!! */ - /* Error handling */ - if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): unsupported path (%d)\n", Path)); - return FALSE; + /* Error handling */ + if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): unsupported path (%d)\n", path)); + return false; } /* For HW limitation, We can't write TXAGC once a byte. */ for (i = 0; i < 4; i++) { if (i != rate_offset) - txagc_content = txagc_content|(config_phydm_read_txagc_8822b(pDM_Odm, Path, rate_idx + i) << (i << 3)); + txagc_content = txagc_content | (config_phydm_read_txagc_8822b(p_dm_odm, path, rate_idx + i) << (i << 3)); else - txagc_content = txagc_content|((PowerIndex & 0x3f) << (i << 3)); + txagc_content = txagc_content | ((power_index & 0x3f) << (i << 3)); } - ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, txagc_content); + odm_set_bb_reg(p_dm_odm, (offset_txagc[path] + rate_idx), MASKDWORD, txagc_content); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): Path-%d Rate index 0x%x (0x%x) = 0x%x\n", - Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex)); - return TRUE; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): path-%d rate index 0x%x (0x%x) = 0x%x\n", + path, hw_rate, (offset_txagc[path] + hw_rate), power_index)); + return true; +#else + return false; +#endif } -VOID +__iram_odm_func__ +void phydm_init_hw_info_by_rfe_type_8822b( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ) { - u2Byte mask_path_a = 0x0303; - u2Byte mask_path_b = 0x0c0c; - /*u2Byte mask_path_c = 0x3030;*/ - /*u2Byte mask_path_d = 0xc0c0;*/ - - pDM_Odm->bInitHwInfoByRfe = FALSE; - - if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7)) { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA|ODM_BOARD_EXT_PA_5G)); - - if (pDM_Odm->RFEType == 6) { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a|mask_path_b))); - } else if (pDM_Odm->RFEType == 7) { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA2 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA2 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA2 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA2 & (mask_path_a|mask_path_b))); +#if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1) + u16 mask_path_a = 0x0303; + u16 mask_path_b = 0x0c0c; + /*u16 mask_path_c = 0x3030;*/ + /*u16 mask_path_d = 0xc0c0;*/ + + p_dm_odm->is_init_hw_info_by_rfe = false; + + if ((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7)) { + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G)); + + if (p_dm_odm->rfe_type == 6) { + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a | mask_path_b))); + } else if (p_dm_odm->rfe_type == 7) { + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GPA, (TYPE_GPA2 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_APA, (TYPE_APA2 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GLNA, (TYPE_GLNA2 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA2 & (mask_path_a | mask_path_b))); } else { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a | mask_path_b))); } - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE); - } else if (pDM_Odm->RFEType == 2) { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA_5G)); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b))); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE); - } else if ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5)) { + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, true); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, true); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, true); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, true); + } else if (p_dm_odm->rfe_type == 2) { + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA_5G)); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a | mask_path_b))); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, true); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, true); + } else if (p_dm_odm->rfe_type == 9) { + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G)); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a | mask_path_b))); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, true); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); + } else if (p_dm_odm->rfe_type == 3) { /* RFE type 3: 8822BS\8822BU TFBGA iFEM */ + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, 0); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); + } else if (p_dm_odm->rfe_type == 5) { /* RFE type 5: 8822BE TFBGA iFEM */ - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_SLIM); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); + } else if (p_dm_odm->rfe_type == 12) { + /* RFE type 12: QFN iFEM */ + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, 0); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); + } else if (p_dm_odm->rfe_type == 4) { + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G)); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a | mask_path_b))); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, true); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, true); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, true); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, true); + } else if (p_dm_odm->rfe_type == 11) { + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G)); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a | mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); - } else if (pDM_Odm->RFEType == 4) { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA|ODM_BOARD_EXT_PA_5G)); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a|mask_path_b))); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b))); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 2); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, true); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, true); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, true); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, true); + + } else if (p_dm_odm->rfe_type == 8) { + /* RFE type 8: TFBGA iFEM AP */ + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, 0); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); + } else if (p_dm_odm->rfe_type == 10) { + /* RFE type 10: QFN iFEM AP PCIE TRSW */ + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_TRSW); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); } else { - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1); - - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE); + /* RFE Type 0: QFN iFEM */ + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, 0); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); } - pDM_Odm->bInitHwInfoByRfe = TRUE; + p_dm_odm->is_init_hw_info_by_rfe = true; - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): RFE type (%d), Board type (0x%x), Package type (%d)\n", pDM_Odm->RFEType, pDM_Odm->BoardType, pDM_Odm->PackageType)); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n", pDM_Odm->ExtPA5G, pDM_Odm->ExtLNA5G, pDM_Odm->ExtPA, pDM_Odm->ExtLNA)); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n", pDM_Odm->TypeAPA, pDM_Odm->TypeALNA, pDM_Odm->TypeGPA, pDM_Odm->TypeGLNA)); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, + ("%s: RFE type (%d), Board type (0x%x), Package type (%d)\n", __func__, p_dm_odm->rfe_type, p_dm_odm->board_type, p_dm_odm->package_type)); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, + ("%s: 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n", __func__, p_dm_odm->ext_pa_5g, p_dm_odm->ext_lna_5g, p_dm_odm->ext_pa, p_dm_odm->ext_lna)); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, + ("%s: 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n", __func__, p_dm_odm->type_apa, p_dm_odm->type_alna, p_dm_odm->type_gpa, p_dm_odm->type_glna)); + +#endif /*PHYDM_FW_API_FUNC_ENABLE_8822B == 1*/ } -s4Byte +__iram_odm_func__ +s32 phydm_get_condition_number_8822B( - IN PDM_ODM_T pDM_Odm + struct PHY_DM_STRUCT *p_dm_odm ) { - s4Byte ret_val; + s32 ret_val; - ODM_SetBBReg( pDM_Odm, 0x1988, BIT22, 0x1); - ret_val = (s4Byte)ODM_GetBBReg(pDM_Odm, 0xf84, (BIT17|BIT16|bMaskLWord)); + odm_set_bb_reg(p_dm_odm, 0x1988, BIT(22), 0x1); + ret_val = (s32)odm_get_bb_reg(p_dm_odm, 0xf84, (BIT(17) | BIT(16) | MASKLWORD)); if (bw_8822b == 0) { ret_val = ret_val << (8 - 4); @@ -592,312 +664,651 @@ phydm_get_condition_number_8822B( ret_val = ret_val << (6 - 4); ret_val = ret_val / 52; } - + return ret_val; } - /* ======================================================================== */ /* ======================================================================== */ /* These following functions can be used by driver*/ -u4Byte +__iram_odm_func__ +u32 config_phydm_read_rf_reg_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ) + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e rf_path, + u32 reg_addr, + u32 bit_mask +) { - u4Byte Readback_Value, Direct_Addr; - u4Byte offset_readRF[2] = {0x2800, 0x2c00}; - u4Byte power_RF[2] = {0x1c, 0xec}; + u32 readback_value, direct_addr; + u32 offset_read_rf[2] = {0x2800, 0x2c00}; /* Error handling.*/ - if (RFPath > ODM_RF_PATH_B) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): unsupported path (%d)\n", RFPath)); - return INVALID_RF_DATA; - } - - /* Error handling. Check if RF power is enable or not */ - /* 0xffffffff means RF power is disable */ - if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): Read fail, RF is disabled\n")); + if (rf_path > ODM_RF_PATH_B) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): unsupported path (%d)\n", rf_path)); return INVALID_RF_DATA; } /* Calculate offset */ - RegAddr &= 0xff; - Direct_Addr = offset_readRF[RFPath] + (RegAddr << 2); + reg_addr &= 0xff; + direct_addr = offset_read_rf[rf_path] + (reg_addr << 2); /* RF register only has 20bits */ - BitMask &= bRFRegOffsetMask; + bit_mask &= RFREGOFFSETMASK; /* Read RF register directly */ - Readback_Value = ODM_GetBBReg(pDM_Odm, Direct_Addr, BitMask); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", - RFPath, RegAddr, Readback_Value, BitMask)); - return Readback_Value; + readback_value = odm_get_bb_reg(p_dm_odm, direct_addr, bit_mask); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", + rf_path, reg_addr, readback_value, bit_mask)); + return readback_value; } -BOOLEAN +__iram_odm_func__ +boolean config_phydm_write_rf_reg_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ) + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e rf_path, + u32 reg_addr, + u32 bit_mask, + u32 data +) { - u4Byte DataAndAddr = 0, Data_original = 0; - u4Byte offset_writeRF[2] = {0xc90, 0xe90}; - u4Byte power_RF[2] = {0x1c, 0xec}; - u1Byte BitShift; + u32 data_and_addr = 0, data_original = 0; + u32 offset_write_rf[2] = {0xc90, 0xe90}; /* Error handling.*/ - if (RFPath > ODM_RF_PATH_B) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): unsupported path (%d)\n", RFPath)); - return FALSE; + if (rf_path > ODM_RF_PATH_B) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): unsupported path (%d)\n", rf_path)); + return false; } /* Read RF register content first */ - RegAddr &= 0xff; - BitMask = BitMask & bRFRegOffsetMask; + reg_addr &= 0xff; + bit_mask = bit_mask & RFREGOFFSETMASK; - if (BitMask != bRFRegOffsetMask) { - Data_original = config_phydm_read_rf_reg_8822b(pDM_Odm, RFPath, RegAddr, bRFRegOffsetMask); + if (bit_mask != RFREGOFFSETMASK) { + data_original = config_phydm_read_rf_reg_8822b(p_dm_odm, rf_path, reg_addr, RFREGOFFSETMASK); /* Error handling. RF is disabled */ - if (config_phydm_read_rf_check_8822b(Data_original) == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): Write fail, RF is disable\n")); - return FALSE; + if (config_phydm_read_rf_check_8822b(data_original) == false) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): Write fail, RF is disable\n")); + return false; } /* check bit mask */ - if (BitMask != 0xfffff) { - for (BitShift = 0; BitShift <= 19; BitShift++) { - if (((BitMask >> BitShift) & 0x1) == 1) - break; - } - Data = ((Data_original) & (~BitMask)) | (Data << BitShift); - } - } else if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): Write fail, RF is disabled\n")); - return FALSE; + data = phydm_check_bit_mask(bit_mask, data_original, data); } /* Put write addr in [27:20] and write data in [19:00] */ - DataAndAddr = ((RegAddr<<20) | (Data&0x000fffff)) & 0x0fffffff; + data_and_addr = ((reg_addr << 20) | (data & 0x000fffff)) & 0x0fffffff; - /* Write Operation */ - ODM_SetBBReg(pDM_Odm, offset_writeRF[RFPath], bMaskDWord, DataAndAddr); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", - RFPath, RegAddr, Data, Data_original, BitMask)); - return TRUE; + /* Write operation */ + odm_set_bb_reg(p_dm_odm, offset_write_rf[rf_path], MASKDWORD, data_and_addr); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", + rf_path, reg_addr, data, data_original, bit_mask)); + return true; } -BOOLEAN +__iram_odm_func__ +boolean config_phydm_write_txagc_8822b( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) + struct PHY_DM_STRUCT *p_dm_odm, + u32 power_index, + enum odm_rf_radio_path_e path, + u8 hw_rate +) { - u4Byte offset_txagc[2] = {0x1d00, 0x1d80}; - u1Byte rate_idx = (HwRate & 0xfc); +#if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1) + + u32 offset_txagc[2] = {0x1d00, 0x1d80}; + u8 rate_idx = (hw_rate & 0xfc); /* Input need to be HW rate index, not driver rate index!!!! */ - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): disable PHY API for debug!!\n")); - return TRUE; + if (p_dm_odm->is_disable_phy_api) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): disable PHY API for debug!!\n")); + return true; } - /* Error handling */ - if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): unsupported path (%d)\n", Path)); - return FALSE; + /* Error handling */ + if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): unsupported path (%d)\n", path)); + return false; } /* driver need to construct a 4-byte power index */ - ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, PowerIndex); + odm_set_bb_reg(p_dm_odm, (offset_txagc[path] + rate_idx), MASKDWORD, power_index); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): Path-%d Rate index 0x%x (0x%x) = 0x%x\n", - Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex)); - return TRUE; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): path-%d rate index 0x%x (0x%x) = 0x%x\n", + path, hw_rate, (offset_txagc[path] + hw_rate), power_index)); + return true; + +#else + return false; +#endif } -u1Byte +__iram_odm_func__ +u8 config_phydm_read_txagc_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ) + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e path, + u8 hw_rate +) { - u1Byte readBack_data; +#if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1) + u8 read_back_data; /* Input need to be HW rate index, not driver rate index!!!! */ - /* Error handling */ - if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): unsupported path (%d)\n", Path)); + /* Error handling */ + if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): unsupported path (%d)\n", path)); return INVALID_TXAGC_DATA; } /* Disable TX AGC report */ - ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0); /* need to check */ + odm_set_bb_reg(p_dm_odm, 0x1998, BIT(16), 0x0); /* need to check */ /* Set data rate index (bit0~6) and path index (bit7) */ - ODM_SetBBReg(pDM_Odm, 0x1998, bMaskByte0, (HwRate|(Path << 7))); + odm_set_bb_reg(p_dm_odm, 0x1998, MASKBYTE0, (hw_rate | (path << 7))); /* Enable TXAGC report */ - ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x1); + odm_set_bb_reg(p_dm_odm, 0x1998, BIT(16), 0x1); /* Read TX AGC report */ - readBack_data = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xd30, 0x7f0000); + read_back_data = (u8)odm_get_bb_reg(p_dm_odm, 0xd30, 0x7f0000); /* Driver have to disable TXAGC report after reading TXAGC (ref. user guide v11) */ - ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0); - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): Path-%d rate index 0x%x = 0x%x\n", Path, HwRate, readBack_data)); - return readBack_data; + odm_set_bb_reg(p_dm_odm, 0x1998, BIT(16), 0x0); + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): path-%d rate index 0x%x = 0x%x\n", path, hw_rate, read_back_data)); + return read_back_data; +#else + return 0; +#endif } -BOOLEAN -config_phydm_switch_band_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ) +__iram_odm_func__ +void +phydm_dynamic_spur_det_elimitor( + struct PHY_DM_STRUCT *p_dm_odm +) { - u4Byte rf_reg18; - BOOLEAN rf_reg_status = TRUE; +#if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1) + + u32 freq_2g[number_of_2g_freq_pt] = {0xFC67, 0xFC27, 0xFFE6, 0xFFA6, 0xFC67, 0xFCE7, 0xFCA7, 0xFC67, 0xFC27, 0xFFE6, 0xFFA6, 0xFF66, 0xFF26, 0xFCE7}; + u32 freq_5g[number_of_5g_freq_pt] = {0xFFC0, 0xFFC0, 0xFC81, 0xFC81, 0xFC41, 0xFC40, 0xFF80, 0xFF80, 0xFF40, 0xFD42}; + u32 freq_2g_n1[number_of_2g_freq_pt] = {0}, freq_2g_p1[number_of_2g_freq_pt] = {0}; + u32 freq_5g_n1[number_of_5g_freq_pt] = {0}, freq_5g_p1[number_of_5g_freq_pt] = {0}; + u32 freq_pt_2g_final = 0, freq_pt_5g_final = 0, freq_pt_2g_b_final = 0, freq_pt_5g_b_final = 0; + u32 max_ret_psd_final = 0, max_ret_psd_b_final = 0; + u32 max_ret_psd_2nd[number_of_sample] = {0}, max_ret_psd_b_2nd[number_of_sample] = {0}; + u32 psd_set[number_of_psd_value] = {0}, psd_set_B[number_of_psd_value] = {0}; + u32 rank_psd_index_in[number_of_psd_value] = {0}, rank_sample_index_in[number_of_sample] = {0}; + u32 rank_psd_index_out[number_of_psd_value] = {0}; + u32 rank_sample_index_out[number_of_sample] = {0}; + u32 reg_910_15_12 = 0; + u8 j = 0, k = 0, threshold_nbi = 0x8D, threshold_csi = 0x8D; + u8 idx = 0, set_result_nbi = SET_NO_NEED, set_result_csi = SET_NO_NEED; + boolean s_dopsd = false, s_donbi_a = false, s_docsi = false, s_donbi_b = false; + + if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_PSDTOOL)) { + ODM_RT_TRACE(p_dm_odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[Return Init] Not Support Dynamic Spur Detection and Eliminator\n")); + return; + } - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b()======================>\n")); + ODM_RT_TRACE(p_dm_odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("Dynamic Spur Detection and Eliminator is ON\n")); - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): disable PHY API for debug!!\n")); - return TRUE; + /* 2G Channel Setting > 20M: 5, 6, 7, 8, 13; 40M: 3~11 */ + if ((*p_dm_odm->p_channel >= 1) && (*p_dm_odm->p_channel <= 14)) { + if (*p_dm_odm->p_band_width == ODM_BW20M) { + + if (*p_dm_odm->p_channel >= 5 && *p_dm_odm->p_channel <= 8) + idx = *p_dm_odm->p_channel - 5; + else if (*p_dm_odm->p_channel == 13) + idx = 4; + else + idx = 16; + } else { + + if (*p_dm_odm->p_channel >= 3 && *p_dm_odm->p_channel <= 11) + idx = *p_dm_odm->p_channel + 2; + else + idx = 16; + } + } else { /* 5G Channel Setting > 20M: 153, 161; 40M: 54, 118, 151, 159; 80M: 58, 122, 155, 155 */ + switch (*p_dm_odm->p_channel) { + case 153: + idx = 0; + break; + case 161: + idx = 1; + break; + case 54: + idx = 2; + break; + case 118: + idx = 3; + break; + case 151: + idx = 4; + break; + case 159: + idx = 5; + break; + case 58: + idx = 6; + break; + case 122: + idx = 7; + break; + case 155: + idx = 8; + break; + default: + idx = 16; + break; + } + } + + if (idx == 16) + s_dopsd = false; + else + s_dopsd = true; + + ODM_RT_TRACE(p_dm_odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[%s] idx = %d, BW = %d, Channel = %d\n", __func__, idx, *p_dm_odm->p_band_width, *p_dm_odm->p_channel)); + + for (k = 0; k < number_of_2g_freq_pt; k++) { + freq_2g_n1[k] = freq_2g[k] - 1; + freq_2g_p1[k] = freq_2g[k] + 1; + } + + for (k = 0; k < number_of_5g_freq_pt; k++) { + freq_5g_n1[k] = freq_5g[k] - 1; + freq_5g_p1[k] = freq_5g[k] + 1; + } + + if ((s_dopsd == TRUE) && (idx <= 13)) { + for (k = 0; k < number_of_sample; k++) { + if (k == 0) { + freq_pt_2g_final = freq_2g_n1[idx]; + freq_pt_5g_final = freq_5g_n1[idx]; + freq_pt_2g_b_final = freq_2g_n1[idx] | BIT(16); + freq_pt_5g_b_final = freq_5g_n1[idx] | BIT(16); + } else if (k == 1) { + freq_pt_2g_final = freq_2g[idx]; + freq_pt_5g_final = freq_5g[idx]; + freq_pt_2g_b_final = freq_2g[idx] | BIT(16); + freq_pt_5g_b_final = freq_5g[idx] | BIT(16); + } else if (k == 2) { + freq_pt_2g_final = freq_2g_p1[idx]; + freq_pt_5g_final = freq_5g_p1[idx]; + freq_pt_2g_b_final = freq_2g_p1[idx] | BIT(16); + freq_pt_5g_b_final = freq_5g_p1[idx] | BIT(16); + } + + for (j = 0; j < number_of_psd_value; j++) { + odm_set_bb_reg(p_dm_odm, 0xc00, MASKBYTE0, 0x4);/* disable 3-wire, path-A */ + odm_set_bb_reg(p_dm_odm, 0xe00, MASKBYTE0, 0x4);/* disable 3-wire, path-B */ + reg_910_15_12 = odm_get_bb_reg(p_dm_odm, 0x910, (BIT15 | BIT14 | BIT13 | BIT12)); + + if (p_dm_odm->rx_ant_status & ODM_RF_A) { + odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, (((ODM_RF_A)<<4) | ODM_RF_A));/*path-A*/ + + if ((*p_dm_odm->p_channel >= 1) && (*p_dm_odm->p_channel <= 14)) + odm_set_bb_reg(p_dm_odm, 0x910, MASKDWORD, BIT(22) | freq_pt_2g_final);/* Start PSD */ + else + odm_set_bb_reg(p_dm_odm, 0x910, MASKDWORD, BIT(22) | freq_pt_5g_final);/* Start PSD */ + + ODM_delay_us(500); + + psd_set[j] = odm_get_bb_reg(p_dm_odm, 0xf44, MASKLWORD); + + odm_set_bb_reg(p_dm_odm, 0x910, BIT22, 0x0);/* turn off PSD */ + } + + if (p_dm_odm->rx_ant_status & ODM_RF_B) { + odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, (((ODM_RF_B)<<4) | ODM_RF_B));/*path-B*/ + + if ((*p_dm_odm->p_channel > 0) && (*p_dm_odm->p_channel <= 14)) + odm_set_bb_reg(p_dm_odm, 0x910, MASKDWORD, BIT(22) | freq_pt_2g_b_final);/* Start PSD */ + else + odm_set_bb_reg(p_dm_odm, 0x910, MASKDWORD, BIT(22) | freq_pt_5g_b_final);/* Start PSD */ + + ODM_delay_us(500); + + psd_set_B[j] = odm_get_bb_reg(p_dm_odm, 0xf44, MASKLWORD); + + odm_set_bb_reg(p_dm_odm, 0x910, BIT22, 0x0);/* turn off PSD */ + } + + odm_set_bb_reg(p_dm_odm, 0xc00, MASKBYTE0, 0x7);/*eanble 3-wire*/ + odm_set_bb_reg(p_dm_odm, 0xe00, MASKBYTE0, 0x7); + odm_set_bb_reg(p_dm_odm, 0x910, (BIT15 | BIT14 | BIT13 | BIT12), reg_910_15_12); + + odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, (((p_dm_odm->rx_ant_status)<<4) | p_dm_odm->rx_ant_status)); + + /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */ + phydm_igi_toggle_8822b(p_dm_odm); + + } + if (p_dm_odm->rx_ant_status & ODM_RF_A) { + phydm_seq_sorting(p_dm_odm, psd_set, rank_psd_index_in, rank_psd_index_out, number_of_psd_value); + max_ret_psd_2nd[k] = psd_set[0]; + } + if (p_dm_odm->rx_ant_status & ODM_RF_B) { + phydm_seq_sorting(p_dm_odm, psd_set_B, rank_psd_index_in, rank_psd_index_out, number_of_psd_value); + max_ret_psd_b_2nd[k] = psd_set_B[0]; + } + } + + if (p_dm_odm->rx_ant_status & ODM_RF_A) { + phydm_seq_sorting(p_dm_odm, max_ret_psd_2nd, rank_sample_index_in, rank_sample_index_out, number_of_sample); + max_ret_psd_final = max_ret_psd_2nd[0]; + + if (max_ret_psd_final >= threshold_nbi) + s_donbi_a = true; + else + s_donbi_a = false; + } + if (p_dm_odm->rx_ant_status & ODM_RF_B) { + phydm_seq_sorting(p_dm_odm, max_ret_psd_b_2nd, rank_sample_index_in, rank_sample_index_out, number_of_sample); + max_ret_psd_b_final = max_ret_psd_b_2nd[0]; + + if (max_ret_psd_b_final >= threshold_nbi) + s_donbi_b = true; + else + s_donbi_b = false; + } + + ODM_RT_TRACE(p_dm_odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[%s] max_ret_psd_final = %d, max_ret_psd_b_final = %d\n", __func__, max_ret_psd_final, max_ret_psd_b_final)); + + if ((max_ret_psd_final >= threshold_csi) || (max_ret_psd_b_final >= threshold_csi)) + s_docsi = true; + else + s_docsi = false; + + } + + /* Reset NBI/CSI everytime after changing channel/BW/band */ + odm_set_bb_reg(p_dm_odm, 0x880, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x884, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x888, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x88c, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x890, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x894, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x898, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x89c, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x874, BIT(0), 0x0); + + odm_set_bb_reg(p_dm_odm, 0x87c, BIT(13), 0x0); + odm_set_bb_reg(p_dm_odm, 0xc20, BIT(28), 0x0); + odm_set_bb_reg(p_dm_odm, 0xe20, BIT(28), 0x0); + + if (s_donbi_a == true || s_donbi_b == true) { + if (*p_dm_odm->p_band_width == ODM_BW20M) { + if (*p_dm_odm->p_channel == 153) + set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 20, 5760, PHYDM_DONT_CARE); + else if (*p_dm_odm->p_channel == 161) + set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 20, 5800, PHYDM_DONT_CARE); + else if (*p_dm_odm->p_channel >= 5 && *p_dm_odm->p_channel <= 8) + set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 20, 2440, PHYDM_DONT_CARE); + else if (*p_dm_odm->p_channel == 13) + set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 20, 2480, PHYDM_DONT_CARE); + else + set_result_nbi = SET_NO_NEED; + } else if (*p_dm_odm->p_band_width == ODM_BW40M) { + if (*p_dm_odm->p_channel == 54) { + set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 40, 5280, PHYDM_DONT_CARE); + } else if (*p_dm_odm->p_channel == 118) { + set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 40, 5600, PHYDM_DONT_CARE); + } else if (*p_dm_odm->p_channel == 151) { + set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 40, 5760, PHYDM_DONT_CARE); + } else if (*p_dm_odm->p_channel == 159) { + set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 40, 5800, PHYDM_DONT_CARE); + /* 2.4G */ + } else if ((*p_dm_odm->p_channel >= 4) && (*p_dm_odm->p_channel <= 6)) { + set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 40, 2440, PHYDM_DONT_CARE); + } else if (*p_dm_odm->p_channel == 11) { + set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 40, 2480, PHYDM_DONT_CARE); + } else + set_result_nbi = SET_NO_NEED; + } else + set_result_nbi = SET_NO_NEED; + } + + if (s_docsi == true) { + if (*p_dm_odm->p_band_width == ODM_BW20M) { + if (*p_dm_odm->p_channel == 153) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 20, 5760, PHYDM_DONT_CARE); + else if (*p_dm_odm->p_channel == 161) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 20, 5800, PHYDM_DONT_CARE); + else if (*p_dm_odm->p_channel >= 5 && *p_dm_odm->p_channel <= 8) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 20, 2440, PHYDM_DONT_CARE); + else if (*p_dm_odm->p_channel == 13) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 20, 2480, PHYDM_DONT_CARE); + else + set_result_csi = SET_NO_NEED; + } else if (*p_dm_odm->p_band_width == ODM_BW40M) { + if (*p_dm_odm->p_channel == 54) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 40, 5280, PHYDM_DONT_CARE); + else if (*p_dm_odm->p_channel == 118) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 40, 5600, PHYDM_DONT_CARE); + else if (*p_dm_odm->p_channel == 151) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 40, 5760, PHYDM_DONT_CARE); + else if (*p_dm_odm->p_channel == 159) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 40, 5800, PHYDM_DONT_CARE); + else if ((*p_dm_odm->p_channel >= 3) && (*p_dm_odm->p_channel <= 10)) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 40, 2440, PHYDM_DONT_CARE); + else if (*p_dm_odm->p_channel == 11) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 40, 2480, PHYDM_DONT_CARE); + else + set_result_csi = SET_NO_NEED; + } else if (*p_dm_odm->p_band_width == ODM_BW80M) { + if (*p_dm_odm->p_channel == 58) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 80, 5280, PHYDM_DONT_CARE); + else if (*p_dm_odm->p_channel == 122) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 80, 5600, PHYDM_DONT_CARE); + else if (*p_dm_odm->p_channel == 155) + set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 80, 5760, PHYDM_DONT_CARE); + else + set_result_csi = SET_NO_NEED; + } else + set_result_csi = SET_NO_NEED; + } + +#endif /*PHYDM_SPUR_CANCELL_ENABLE_8822B == 1*/ +} + +__iram_odm_func__ +boolean +config_phydm_switch_band_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 central_ch +) +{ + u32 rf_reg18; + boolean rf_reg_status = true; + u32 reg_8; + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b()======================>\n")); + + if (p_dm_odm->is_disable_phy_api) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): disable PHY API for debug!!\n")); + return true; } - rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); + rf_reg18 = config_phydm_read_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); if (central_ch <= 14) { /* 2.4G */ /* Enable CCK block */ - ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x1); + odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0x1); /* Disable MAC CCK check */ - ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x0); + odm_set_bb_reg(p_dm_odm, 0x454, BIT(7), 0x0); /* Disable BB CCK check */ - ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x0); + odm_set_bb_reg(p_dm_odm, 0xa80, BIT(18), 0x0); /*CCA Mask*/ - ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 15); /*default value*/ + odm_set_bb_reg(p_dm_odm, 0x814, 0x0000FC00, 15); /*default value*/ /* RF band */ - rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8))); + rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8)))); + + /* RxHP dynamic control */ + /* QFN eFEM RxHP are always low at 2G */ + reg_8 = odm_get_bb_reg(p_dm_odm, 0x19a8, BIT(31)); + + if (!((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7) || (p_dm_odm->rfe_type == 9))) { + /* SoML on */ + if ((reg_8 == 0x1) && (!((p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5)))) { + odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08100000); + odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x0); + odm_set_bb_reg(p_dm_odm, 0xc04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xe04, (BIT(18)|BIT(21)), 0x0); + /* SoML off */ + } else { + odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08108492); + odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x1); + odm_set_bb_reg(p_dm_odm, 0xc04, BIT(18), 0x1); + odm_set_bb_reg(p_dm_odm, 0xe04, BIT(18), 0x1); + odm_set_bb_reg(p_dm_odm, 0xc04, BIT(21), 0x1); + odm_set_bb_reg(p_dm_odm, 0xe04, BIT(21), 0x1); + } + } + } else if (central_ch > 35) { /* 5G */ /* Enable BB CCK check */ - ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x1); - + odm_set_bb_reg(p_dm_odm, 0xa80, BIT(18), 0x1); + /* Enable CCK check */ - ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x1); + odm_set_bb_reg(p_dm_odm, 0x454, BIT(7), 0x1); /* Disable CCK block */ - ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x0); + odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0x0); /*CCA Mask*/ - ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 34); /*CCA mask = 13.6us*/ + if (!p_dm_odm->wifi_test) + odm_set_bb_reg(p_dm_odm, 0x814, 0x0000FC00, 34); /*CCA mask = 13.6us*/ + else + odm_set_bb_reg(p_dm_odm, 0x814, 0x0000FC00, 15); /*default value*/ /* RF band */ - rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8))); - rf_reg18 = (rf_reg18|BIT8|BIT16); + rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8)))); + rf_reg18 = (rf_reg18 | BIT(8) | BIT(16)); + + /* RxHP dynamic control */ + reg_8 = odm_get_bb_reg(p_dm_odm, 0x19a8, BIT(31)); + + if ((reg_8 == 0x1) && (!((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7) || (p_dm_odm->rfe_type == 9)))) { + odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08100000); + odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x0); + odm_set_bb_reg(p_dm_odm, 0xc04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xe04, (BIT(18)|BIT(21)), 0x0); + } else { + odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08108492); + odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x1); + odm_set_bb_reg(p_dm_odm, 0xc04, BIT(18), 0x1); + odm_set_bb_reg(p_dm_odm, 0xe04, BIT(18), 0x1); + odm_set_bb_reg(p_dm_odm, 0xc04, BIT(21), 0x1); + odm_set_bb_reg(p_dm_odm, 0xe04, BIT(21), 0x1); + } + } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d)\n", central_ch)); - return FALSE; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d)\n", central_ch)); + return false; } - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); - if (pDM_Odm->RFType > ODM_1T1R) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18); + if (p_dm_odm->rf_type > ODM_1T1R) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_B, 0x18, RFREGOFFSETMASK, rf_reg18); - if (phydm_rfe_8822b(pDM_Odm, central_ch) == FALSE) - return FALSE; + if (phydm_rfe_8822b(p_dm_odm, central_ch) == false) + return false; - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d), because writing RF register is fail\n", central_ch)); - return FALSE; + if (rf_reg_status == false) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d), because writing RF register is fail\n", central_ch)); + return false; } - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Success to switch band (ch: %d)\n", central_ch)); - return TRUE; + /* Dynamic spur detection by PSD and NBI/CSI mask */ + if (*(p_dm_odm->p_mp_mode)) + phydm_dynamic_spur_det_elimitor(p_dm_odm); + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Success to switch band (ch: %d)\n", central_ch)); + return true; } -BOOLEAN -config_phydm_switch_channel_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ) +__iram_odm_func__ +boolean +config_phydm_switch_channel_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 central_ch +) { - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u4Byte rf_reg18 = 0, rf_regB8 = 0, rf_regBE = 0xff; - BOOLEAN rf_reg_status = TRUE; - u1Byte low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6}; - u1Byte middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7}; - u1Byte high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 0x7, 0x7, 0x6, 0x5, 0x5, 0x0}; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b()====================>\n")); - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): disable PHY API for debug!!\n")); - return TRUE; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u32 rf_reg18 = 0, rf_reg_be = 0xff; + boolean rf_reg_status = true; + u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6}; + u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7}; + u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 0x7, 0x7, 0x6, 0x5, 0x5, 0x0}; + u8 band_index = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b()====================>\n")); + + if (p_dm_odm->is_disable_phy_api) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): disable PHY API for debug!!\n")); + return true; } central_ch_8822b = central_ch; - rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); - rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); - rf_reg18 = (rf_reg18 & (~(BIT18|BIT17|bMaskByte0))); - if (pDM_Odm->CutVersion == ODM_CUT_A) { - rf_regB8 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask); - rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_regB8); - } + /* Errir handling for wrong HW setting due to wrong channel setting */ + if (central_ch_8822b <= 14) + band_index = 1; + else + band_index = 2; + + if (p_dm_odm->rfe_hwsetting_band != band_index) + phydm_rfe_8822b(p_dm_odm, central_ch_8822b); + + /* RF register setting */ + rf_reg18 = config_phydm_read_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); + rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0))); /* Switch band and channel */ if (central_ch <= 14) { /* 2.4G */ /* 1. RF band and channel*/ - rf_reg18 = (rf_reg18|central_ch); + rf_reg18 = (rf_reg18 | central_ch); /* 2. AGC table selection */ - ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x0); - pDM_DigTable->agcTableIdx = 0x0; + odm_set_bb_reg(p_dm_odm, 0x958, 0x1f, 0x0); + p_dm_dig_table->agc_table_idx = 0x0; /* 3. Set central frequency for clock offset tracking */ - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x96a); - - /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ - if (pDM_Odm->CutVersion == ODM_CUT_A) - rf_regB8 = rf_regB8 | BIT19; + odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x96a); /* CCK TX filter parameters */ + if (central_ch == 14) { - ODM_SetBBReg(pDM_Odm, 0xa20, bMaskHWord, 0x8488); - ODM_SetBBReg(pDM_Odm, 0xa24, bMaskDWord, 0x00006577); - ODM_SetBBReg(pDM_Odm, 0xa28, bMaskLWord, 0x0000); + odm_set_bb_reg(p_dm_odm, 0xa24, MASKDWORD, 0x00006577); + odm_set_bb_reg(p_dm_odm, 0xa28, MASKLWORD, 0x0000); } else { - ODM_SetBBReg(pDM_Odm, 0xa20, bMaskHWord, (rega20_8822b>>16)); - ODM_SetBBReg(pDM_Odm, 0xa24, bMaskDWord, rega24_8822b); - ODM_SetBBReg(pDM_Odm, 0xa28, bMaskLWord, (rega28_8822b & bMaskLWord)); + odm_set_bb_reg(p_dm_odm, 0xa24, MASKDWORD, 0x384f6577); + odm_set_bb_reg(p_dm_odm, 0xa28, MASKLWORD, 0x1525); } } else if (central_ch > 35) { @@ -908,134 +1319,130 @@ config_phydm_switch_channel_8822b( /* 2. AGC table selection */ if ((central_ch >= 36) && (central_ch <= 64)) { - ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x1); - pDM_DigTable->agcTableIdx = 0x1; + odm_set_bb_reg(p_dm_odm, 0x958, 0x1f, 0x1); + p_dm_dig_table->agc_table_idx = 0x1; } else if ((central_ch >= 100) && (central_ch <= 144)) { - ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x2); - pDM_DigTable->agcTableIdx = 0x2; + odm_set_bb_reg(p_dm_odm, 0x958, 0x1f, 0x2); + p_dm_dig_table->agc_table_idx = 0x2; } else if (central_ch >= 149) { - ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x3); - pDM_DigTable->agcTableIdx = 0x3; + odm_set_bb_reg(p_dm_odm, 0x958, 0x1f, 0x3); + p_dm_dig_table->agc_table_idx = 0x3; } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (AGC) (ch: %d)\n", central_ch)); - return FALSE; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (AGC) (ch: %d)\n", central_ch)); + return false; } /* 3. Set central frequency for clock offset tracking */ if ((central_ch >= 36) && (central_ch <= 48)) - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x494); + odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x494); else if ((central_ch >= 52) && (central_ch <= 64)) - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x453); + odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x453); else if ((central_ch >= 100) && (central_ch <= 116)) - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x452); + odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x452); else if ((central_ch >= 118) && (central_ch <= 177)) - ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x412); + odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x412); else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (fc_area) (ch: %d)\n", central_ch)); - return FALSE; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (fc_area) (ch: %d)\n", central_ch)); + return false; } - /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ - if (pDM_Odm->CutVersion == ODM_CUT_A) { - if ((central_ch >= 57) && (central_ch <= 75)) - rf_regB8 = rf_regB8 & (~BIT19); - else - rf_regB8 = rf_regB8 | BIT19; - } } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d)\n", central_ch)); - return FALSE; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d)\n", central_ch)); + return false; } /* Modify IGI for MP driver to aviod PCIE interference */ - if ((pDM_Odm->mp_mode == TRUE) && ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5))) { + if ((*(p_dm_odm->p_mp_mode) == true) && ((p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5))) { if (central_ch == 14) - ODM_Write_DIG(pDM_Odm, 0x26); + odm_write_dig(p_dm_odm, 0x26); else - ODM_Write_DIG(pDM_Odm, 0x20); + odm_write_dig(p_dm_odm, 0x20); } /* Modify the setting of register 0xBE to reduce phase noise */ if (central_ch <= 14) - rf_regBE = 0x0; + rf_reg_be = 0x0; else if ((central_ch >= 36) && (central_ch <= 64)) - rf_regBE = low_band[(central_ch - 36)>>1]; + rf_reg_be = low_band[(central_ch - 36) >> 1]; else if ((central_ch >= 100) && (central_ch <= 144)) - rf_regBE = middle_band[(central_ch - 100)>>1]; + rf_reg_be = middle_band[(central_ch - 100) >> 1]; else if ((central_ch >= 149) && (central_ch <= 177)) - rf_regBE = high_band[(central_ch - 149)>>1]; + rf_reg_be = high_band[(central_ch - 149) >> 1]; else - rf_regBE = 0xff; + rf_reg_be = 0xff; - if (rf_regBE != 0xff) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xbe, (BIT17|BIT16|BIT15), rf_regBE); + if (rf_reg_be != 0xff) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xbe, (BIT(17) | BIT(16) | BIT(15)), rf_reg_be); else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d, Phase noise)\n", central_ch)); - return FALSE; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d, Phase noise)\n", central_ch)); + return false; } /* Fix channel 144 issue, ask by RFSI Alvin*/ /* 00 when freq < 5400; 01 when 5400<=freq<=5720; 10 when freq > 5720; 2G don't care*/ /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ if (central_ch == 144) { - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xdf, BIT18, 0x1); - rf_reg18 = (rf_reg18 | BIT17); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xdf, BIT(18), 0x1); + rf_reg18 = (rf_reg18 | BIT(17)); } else { - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xdf, BIT18, 0x0); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xdf, BIT(18), 0x0); if (central_ch > 144) - rf_reg18 = (rf_reg18 | BIT18); + rf_reg18 = (rf_reg18 | BIT(18)); else if (central_ch >= 80) - rf_reg18 = (rf_reg18 | BIT17); + rf_reg18 = (rf_reg18 | BIT(17)); } - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); - - if (pDM_Odm->CutVersion == ODM_CUT_A) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask, rf_regB8); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); - if (pDM_Odm->RFType > ODM_1T1R) { - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18); + if (p_dm_odm->rf_type > ODM_1T1R) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_B, 0x18, RFREGOFFSETMASK, rf_reg18); - if (pDM_Odm->CutVersion == ODM_CUT_A) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0xb8, bRFRegOffsetMask, rf_regB8); + if (rf_reg_status == false) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d), because writing RF register is fail\n", central_ch)); + return false; } - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d), because writing RF register is fail\n", central_ch)); - return FALSE; - } + /* Debug for RF resister reading error during synthesizer parameters parsing */ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xb8, BIT(19), 0); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xb8, BIT(19), 1); + + phydm_igi_toggle_8822b(p_dm_odm); + /* Dynamic spur detection by PSD and NBI/CSI mask */ + if (*(p_dm_odm->p_mp_mode)) + phydm_dynamic_spur_det_elimitor(p_dm_odm); - phydm_ccapar_by_rfe_8822b(pDM_Odm); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Success to switch channel (ch: %d)\n", central_ch)); - return TRUE; + phydm_ccapar_by_rfe_8822b(p_dm_odm); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Success to switch channel (ch: %d)\n", central_ch)); + return true; } -BOOLEAN -config_phydm_switch_bandwidth_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ) +__iram_odm_func__ +boolean +config_phydm_switch_bandwidth_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 primary_ch_idx, + enum odm_bw_e bandwidth +) { - u4Byte rf_reg18; - BOOLEAN rf_reg_status = TRUE; + u32 rf_reg18; + boolean rf_reg_status = true; - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b()===================>\n")); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b()===================>\n")); - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): disable PHY API for debug!!\n")); - return TRUE; + if (p_dm_odm->is_disable_phy_api) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): disable PHY API for debug!!\n")); + return true; } - /* Error handling */ + /* Error handling */ if ((bandwidth >= ODM_BW_MAX) || ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) || ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); - return FALSE; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); + return false; } bw_8822b = bandwidth; - rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask); + rf_reg18 = config_phydm_read_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); /* Switch bandwidth */ @@ -1043,366 +1450,403 @@ config_phydm_switch_bandwidth_8822b( case ODM_BW20M: { /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, ODM_BW20M); + odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, ODM_BW20M); /* ADC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x1); + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(9) | BIT(8)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(16), 0x1); /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x1); + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(21) | BIT(20)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(28), 0x1); /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); + odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x1); /* RF bandwidth */ - rf_reg18 = (rf_reg18 | BIT11 | BIT10); + rf_reg18 = (rf_reg18 | BIT(11) | BIT(10)); break; } case ODM_BW40M: { /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 40M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW40M)); + odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | ODM_BW40M)); /* CCK primary channel */ if (primary_ch_idx == 1) - ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, primary_ch_idx); + odm_set_bb_reg(p_dm_odm, 0xa00, BIT(4), primary_ch_idx); else - ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, 0); + odm_set_bb_reg(p_dm_odm, 0xa00, BIT(4), 0); /* ADC clock = 160M clock for BW40 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT11|BIT10), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT17, 0x1); + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(17), 0x1); /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT23|BIT22), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT29, 0x1); + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(23) | BIT(22)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(29), 0x1); /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); + odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x1); /* RF bandwidth */ - rf_reg18 = (rf_reg18 & (~(BIT11|BIT10))); - rf_reg18 = (rf_reg18|BIT11); + rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10)))); + rf_reg18 = (rf_reg18 | BIT(11)); break; } case ODM_BW80M: { /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW80M)); + odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | ODM_BW80M)); /* ADC clock = 160M clock for BW80 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT13|BIT12), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT18, 0x1); + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(13) | BIT(12)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(18), 0x1); /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT25|BIT24), 0x0); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT30, 0x1); + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(25) | BIT(24)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(30), 0x1); /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1); + odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x1); /* RF bandwidth */ - rf_reg18 = (rf_reg18 & (~(BIT11|BIT10))); - rf_reg18 = (rf_reg18|BIT10); + rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10)))); + rf_reg18 = (rf_reg18 | BIT(10)); break; } case ODM_BW5M: { /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT6|ODM_BW20M)); + odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (BIT(6) | ODM_BW20M)); /* ADC clock = 40M clock */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x2); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(9) | BIT(8)), 0x2); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(16), 0x0); /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x2); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(21) | BIT(20)), 0x2); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(28), 0x0); /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0); - ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1); + odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8c8, BIT(31), 0x1); /* RF bandwidth */ - rf_reg18 = (rf_reg18|BIT11|BIT10); + rf_reg18 = (rf_reg18 | BIT(11) | BIT(10)); break; } case ODM_BW10M: { /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT7|ODM_BW20M)); + odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (BIT(7) | ODM_BW20M)); /* ADC clock = 80M clock */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x3); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(9) | BIT(8)), 0x3); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(16), 0x0); /* DAC clock = 160M clock for BW20 */ - ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x3); - ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(21) | BIT(20)), 0x3); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(28), 0x0); /* ADC buffer clock */ - ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0); - ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1); + odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8c8, BIT(31), 0x1); /* RF bandwidth */ - rf_reg18 = (rf_reg18|BIT11|BIT10); + rf_reg18 = (rf_reg18 | BIT(11) | BIT(10)); break; } default: - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); } /* Write RF register */ - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); - if (pDM_Odm->RFType > ODM_1T1R) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18); + if (p_dm_odm->rf_type > ODM_1T1R) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_B, 0x18, RFREGOFFSETMASK, rf_reg18); - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", bandwidth, primary_ch_idx)); - return FALSE; + if (rf_reg_status == false) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", bandwidth, primary_ch_idx)); + return false; } /* Modify RX DFIR parameters */ - phydm_rxdfirpar_by_bw_8822b(pDM_Odm, bandwidth); + phydm_rxdfirpar_by_bw_8822b(p_dm_odm, bandwidth); + + /* Toggle IGI to let RF enter RX mode */ + phydm_igi_toggle_8822b(p_dm_odm); + + /* Dynamic spur detection by PSD and NBI/CSI mask */ + if (*(p_dm_odm->p_mp_mode)) + phydm_dynamic_spur_det_elimitor(p_dm_odm); /* Modify CCA parameters */ - phydm_ccapar_by_bw_8822b(pDM_Odm, bandwidth); - phydm_ccapar_by_rfe_8822b(pDM_Odm); + phydm_ccapar_by_rfe_8822b(p_dm_odm); /* Toggle RX path to avoid RX dead zone issue */ - ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, 0x0); - ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, (pDM_Odm->RXAntStatus|(pDM_Odm->RXAntStatus<<4))); + odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, 0x0); + odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, (p_dm_odm->rx_ant_status | (p_dm_odm->rx_ant_status << 4))); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Success to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); - return TRUE; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Success to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); + return true; } -BOOLEAN -config_phydm_switch_channel_bw_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ) +__iram_odm_func__ +boolean +config_phydm_switch_channel_bw_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 central_ch, + u8 primary_ch_idx, + enum odm_bw_e bandwidth +) { /* Switch band */ - if (config_phydm_switch_band_8822b(pDM_Odm, central_ch) == FALSE) - return FALSE; + if (config_phydm_switch_band_8822b(p_dm_odm, central_ch) == false) + return false; /* Switch channel */ - if (config_phydm_switch_channel_8822b(pDM_Odm, central_ch) == FALSE) - return FALSE; + if (config_phydm_switch_channel_8822b(p_dm_odm, central_ch) == false) + return false; /* Switch bandwidth */ - if (config_phydm_switch_bandwidth_8822b(pDM_Odm, primary_ch_idx, bandwidth) == FALSE) - return FALSE; + if (config_phydm_switch_bandwidth_8822b(p_dm_odm, primary_ch_idx, bandwidth) == false) + return false; - return TRUE; + return true; } -BOOLEAN +__iram_odm_func__ +boolean config_phydm_trx_mode_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_PATH_E TxPath, - IN ODM_RF_PATH_E RxPath, - IN BOOLEAN bTx2Path - ) + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_path_e tx_path, + enum odm_rf_path_e rx_path, + boolean is_tx2_path +) { - BOOLEAN rf_reg_status = TRUE; - u1Byte IGI; - - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b()=====================>\n")); - - if (pDM_Odm->bDisablePhyApi) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): disable PHY API for debug!!\n")); - return TRUE; + boolean rf_reg_status = true; + u32 rf_reg33 = 0; + u16 counter = 0; + /* struct PHY_DM_STRUCT* p_dm_odm = (struct PHY_DM_STRUCT*)p_dm_void; */ + /* struct _ADAPTER* p_adapter = p_dm_odm->adapter; */ + /* PMGNT_INFO p_mgnt_info = &(p_adapter->mgnt_info); */ + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b()=====================>\n")); + + if (p_dm_odm->is_disable_phy_api) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): disable PHY API for debug!!\n")); + return true; } - if ((TxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong TX setting (TX: 0x%x)\n", TxPath)); - return FALSE; + if ((tx_path & (~(ODM_RF_A | ODM_RF_B))) != 0) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong TX setting (TX: 0x%x)\n", tx_path)); + return false; } - if ((RxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong RX setting (RX: 0x%x)\n", RxPath)); - return FALSE; + if ((rx_path & (~(ODM_RF_A | ODM_RF_B))) != 0) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong RX setting (RX: 0x%x)\n", rx_path)); + return false; } /* RF mode of path-A and path-B */ /* Cannot shut down path-A, beacause synthesizer will be shut down when path-A is in shut down mode */ - if ((TxPath|RxPath) & ODM_RF_A) - ODM_SetBBReg(pDM_Odm, 0xc08, bMaskLWord, 0x3231); + if ((tx_path | rx_path) & ODM_RF_A) + odm_set_bb_reg(p_dm_odm, 0xc08, MASKLWORD, 0x3231); else - ODM_SetBBReg(pDM_Odm, 0xc08, bMaskLWord, 0x1111); + odm_set_bb_reg(p_dm_odm, 0xc08, MASKLWORD, 0x1111); - if ((TxPath|RxPath) & ODM_RF_B) - ODM_SetBBReg(pDM_Odm, 0xe08, bMaskLWord, 0x3231); + if ((tx_path | rx_path) & ODM_RF_B) + odm_set_bb_reg(p_dm_odm, 0xe08, MASKLWORD, 0x3231); else - ODM_SetBBReg(pDM_Odm, 0xe08, bMaskLWord, 0x1111); + odm_set_bb_reg(p_dm_odm, 0xe08, MASKLWORD, 0x1111); /* Set TX antenna by Nsts */ - ODM_SetBBReg(pDM_Odm, 0x93c, (BIT19|BIT18), 0x3); - ODM_SetBBReg(pDM_Odm, 0x80c, (BIT29|BIT28), 0x1); + odm_set_bb_reg(p_dm_odm, 0x93c, (BIT(19) | BIT(18)), 0x3); + odm_set_bb_reg(p_dm_odm, 0x80c, (BIT(29) | BIT(28)), 0x1); /* Control CCK TX path by 0xa07[7] */ - ODM_SetBBReg(pDM_Odm, 0x80c, BIT30, 0x1); - - /* TX logic map and TX path en for Nsts = 1, and CCK TX path*/ - if (TxPath & ODM_RF_A) { - ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x001); - ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x8); - } else if (TxPath & ODM_RF_B) { - ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x002); - ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x4); + odm_set_bb_reg(p_dm_odm, 0x80c, BIT(30), 0x1); + + /* TX logic map and TX path en for Nsts = 1, and CCK TX path*/ + if (tx_path & ODM_RF_A) { + odm_set_bb_reg(p_dm_odm, 0x93c, 0xfff00000, 0x001); + odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x8); + } else if (tx_path & ODM_RF_B) { + odm_set_bb_reg(p_dm_odm, 0x93c, 0xfff00000, 0x002); + odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x4); } - + /* TX logic map and TX path en for Nsts = 2*/ - if ((TxPath == ODM_RF_A) || (TxPath == ODM_RF_B)) - ODM_SetBBReg(pDM_Odm, 0x940, 0xfff0, 0x01); + if ((tx_path == ODM_RF_A) || (tx_path == ODM_RF_B)) + odm_set_bb_reg(p_dm_odm, 0x940, 0xfff0, 0x01); else - ODM_SetBBReg(pDM_Odm, 0x940, 0xfff0, 0x43); + odm_set_bb_reg(p_dm_odm, 0x940, 0xfff0, 0x43); /* TX path enable */ - ODM_SetBBReg(pDM_Odm, 0x80c, bMaskByte0, ((TxPath << 4)|TxPath)); + odm_set_bb_reg(p_dm_odm, 0x80c, MASKBYTE0, ((tx_path << 4) | tx_path)); /* Tx2path for 1ss */ - if (!((TxPath == ODM_RF_A) || (TxPath == ODM_RF_B))) { - if (bTx2Path || pDM_Odm->mp_mode) { + if (!((tx_path == ODM_RF_A) || (tx_path == ODM_RF_B))) { + if (is_tx2_path || *(p_dm_odm->p_mp_mode)) { /* 2Tx for OFDM */ - ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x043); + odm_set_bb_reg(p_dm_odm, 0x93c, 0xfff00000, 0x043); /* 2Tx for CCK */ - ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0xc); + odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0xc); } } /* Always disable MRC for CCK CCA */ - ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x0); + odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(22), 0x0); /* Always disable MRC for CCK barker */ - ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x0); + odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(18), 0x0); - /* CCK RX 1st and 2nd path setting*/ - if (RxPath & ODM_RF_A) - ODM_SetBBReg(pDM_Odm, 0xa04, 0x0f000000, 0x0); - else if (RxPath & ODM_RF_B) - ODM_SetBBReg(pDM_Odm, 0xa04, 0x0f000000, 0x5); + /* CCK RX 1st and 2nd path setting*/ + if (rx_path & ODM_RF_A) + odm_set_bb_reg(p_dm_odm, 0xa04, 0x0f000000, 0x0); + else if (rx_path & ODM_RF_B) + odm_set_bb_reg(p_dm_odm, 0xa04, 0x0f000000, 0x5); /* RX path enable */ - ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, ((RxPath << 4)|RxPath)); + odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, ((rx_path << 4) | rx_path)); - if ((RxPath == ODM_RF_A) || (RxPath == ODM_RF_B)) { + if ((rx_path == ODM_RF_A) || (rx_path == ODM_RF_B)) { /* 1R */ /* Disable MRC for CCA */ - /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x0); */ + /* odm_set_bb_reg(p_dm_odm, 0xa2c, BIT22, 0x0); */ /* Disable MRC for barker */ - /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x0); */ - + /* odm_set_bb_reg(p_dm_odm, 0xa2c, BIT18, 0x0); */ + /* Disable CCK antenna diversity */ - /* ODM_SetBBReg(pDM_Odm, 0xa00, BIT15, 0x0); */ + /* odm_set_bb_reg(p_dm_odm, 0xa00, BIT15, 0x0); */ /* Disable Antenna weighting */ - ODM_SetBBReg(pDM_Odm, 0x1904, BIT16, 0x0); - ODM_SetBBReg(pDM_Odm, 0x800, BIT28, 0x0); - ODM_SetBBReg(pDM_Odm, 0x850, BIT23, 0x0); + odm_set_bb_reg(p_dm_odm, 0x1904, BIT(16), 0x0); + odm_set_bb_reg(p_dm_odm, 0x800, BIT(28), 0x0); + odm_set_bb_reg(p_dm_odm, 0x850, BIT(23), 0x0); } else { /* 2R */ /* Enable MRC for CCA */ - /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x1); */ + /* odm_set_bb_reg(p_dm_odm, 0xa2c, BIT22, 0x1); */ /* Enable MRC for barker */ - /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x1); */ + /* odm_set_bb_reg(p_dm_odm, 0xa2c, BIT18, 0x1); */ /* Disable CCK antenna diversity */ - /* ODM_SetBBReg(pDM_Odm, 0xa00, BIT15, 0x0); */ + /* odm_set_bb_reg(p_dm_odm, 0xa00, BIT15, 0x0); */ /* Enable Antenna weighting */ - ODM_SetBBReg(pDM_Odm, 0x1904, BIT16, 0x1); - ODM_SetBBReg(pDM_Odm, 0x800, BIT28, 0x1); - ODM_SetBBReg(pDM_Odm, 0x850, BIT23, 0x1); + odm_set_bb_reg(p_dm_odm, 0x1904, BIT(16), 0x1); + odm_set_bb_reg(p_dm_odm, 0x800, BIT(28), 0x1); + odm_set_bb_reg(p_dm_odm, 0x850, BIT(23), 0x1); } /* Update TXRX antenna status for PHYDM */ - pDM_Odm->TXAntStatus = (TxPath & 0x3); - pDM_Odm->RXAntStatus = (RxPath & 0x3); + p_dm_odm->tx_ant_status = (tx_path & 0x3); + p_dm_odm->rx_ant_status = (rx_path & 0x3); /* MP driver need to support path-B TX\RX */ - if (pDM_Odm->mp_mode) { + + while (1) { + counter++; + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x80000); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK, 0x00001); + + ODM_delay_us(2); + rf_reg33 = config_phydm_read_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK); + + if ((rf_reg33 == 0x00001) && (config_phydm_read_rf_check_8822b(rf_reg33))) + break; + else if (counter == 100) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting, because writing RF mode table is fail\n")); + return false; + } + } + + if (*(p_dm_odm->p_mp_mode) || (*p_dm_odm->p_antenna_test) || (p_dm_odm->normal_rx_path)) { /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080e 0xef 0x00000 suggested by Lucas*/ - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x00034); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0x4080e); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): MP mode!! support path-B TX and RX\n")); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x80000); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK, 0x00001); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x3e, RFREGOFFSETMASK, 0x00034); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x3f, RFREGOFFSETMASK, 0x4080e); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x00000); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): MP mode or Antenna test mode!! support path-B TX and RX\n")); } else { /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080c 0xef 0x00000 */ - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x00034); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0x4080c); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Normal mode!! Do not support path-B TX and RX\n")); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x80000); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK, 0x00001); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x3e, RFREGOFFSETMASK, 0x00034); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x3f, RFREGOFFSETMASK, 0x4080c); + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x00000); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Normal mode!! Do not support path-B TX and RX\n")); } - if (rf_reg_status == FALSE) { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting (TX: 0x%x, RX: 0x%x), because writing RF register is fail\n", TxPath, RxPath)); - return FALSE; + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x00000); + + if (rf_reg_status == false) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting (TX: 0x%x, RX: 0x%x), because writing RF register is fail\n", tx_path, rx_path)); + return false; } - /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */ - IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); - ODM_Write_DIG(pDM_Odm, IGI - 2); - ODM_Write_DIG(pDM_Odm, IGI); + /* Toggle igi to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */ + phydm_igi_toggle_8822b(p_dm_odm); /* Modify CCA parameters */ - phydm_ccapar_by_rxpath_8822b(pDM_Odm); - phydm_ccapar_by_rfe_8822b(pDM_Odm); - phydm_rfe_8822b(pDM_Odm, central_ch_8822b); + phydm_ccapar_by_rfe_8822b(p_dm_odm); + phydm_rfe_8822b(p_dm_odm, central_ch_8822b); + + /* Dynamic spur detection by PSD and NBI/CSI mask */ + if (*(p_dm_odm->p_mp_mode)) + phydm_dynamic_spur_det_elimitor(p_dm_odm); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n", TxPath, RxPath)); - return TRUE; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n", tx_path, rx_path)); + return true; } -BOOLEAN -config_phydm_parameter_init( - IN PDM_ODM_T pDM_Odm, - IN ODM_PARAMETER_INIT_E type - ) +__iram_odm_func__ +boolean +config_phydm_parameter_init_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_parameter_init_e type +) { if (type == ODM_PRE_SETTING) { - ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x0); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Pre setting: disable OFDM and CCK block\n")); + odm_set_bb_reg(p_dm_odm, 0x808, (BIT(28) | BIT(29)), 0x0); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Pre setting: disable OFDM and CCK block\n", __func__)); } else if (type == ODM_POST_SETTING) { - ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x3); - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Post setting: enable OFDM and CCK block\n")); - reg82c_8822b = ODM_GetBBReg(pDM_Odm, 0x82c, bMaskDWord); - reg838_8822b = ODM_GetBBReg(pDM_Odm, 0x838, bMaskDWord); - reg830_8822b = ODM_GetBBReg(pDM_Odm, 0x830, bMaskDWord); - reg83c_8822b = ODM_GetBBReg(pDM_Odm, 0x83c, bMaskDWord); - rega20_8822b = ODM_GetBBReg(pDM_Odm, 0xa20, bMaskDWord); - rega24_8822b = ODM_GetBBReg(pDM_Odm, 0xa24, bMaskDWord); - rega28_8822b = ODM_GetBBReg(pDM_Odm, 0xa28, bMaskDWord); + odm_set_bb_reg(p_dm_odm, 0x808, (BIT(28) | BIT(29)), 0x3); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Post setting: enable OFDM and CCK block\n", __func__)); +#if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1) + } else if (type == ODM_INIT_FW_SETTING) { + u8 h2c_content[4] = {0}; + + h2c_content[0] = p_dm_odm->rfe_type; + h2c_content[1] = p_dm_odm->rf_type; + h2c_content[2] = p_dm_odm->cut_version; + h2c_content[3] = (p_dm_odm->tx_ant_status << 4) | p_dm_odm->rx_ant_status; + + odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_FW_GENERAL_INIT, 4, h2c_content); +#endif } else { - ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Wrong type!!\n")); - return FALSE; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Wrong type!!\n", __func__)); + return false; } - return TRUE; + return true; } /* ======================================================================== */ +#endif /*PHYDM_FW_API_ENABLE_8822B == 1*/ #endif /* RTL8822B_SUPPORT == 1 */ - diff --git a/hal/phydm/rtl8822b/phydm_hal_api8822b.h b/hal/phydm/rtl8822b/phydm_hal_api8822b.h index 14bce47..1f74a1c 100644 --- a/hal/phydm/rtl8822b/phydm_hal_api8822b.h +++ b/hal/phydm/rtl8822b/phydm_hal_api8822b.h @@ -1,7 +1,7 @@ /****************************************************************************** * * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -22,112 +22,120 @@ #if (RTL8822B_SUPPORT == 1) -#define PHY_CONFIG_VERSION_8822B "26.5.27" /*2016.05.19 (HW user guide version: R26, SW user guide version: R05, Modification: R27)*/ +#define PHY_CONFIG_VERSION_8822B "28.5.34" /*2017.01.18 (HW user guide version: R28, SW user guide version: R05, Modification: R34), remove A cut setting, refine CCK txfilter and OFDM CCA setting by YuChen*/ #define INVALID_RF_DATA 0xffffffff #define INVALID_TXAGC_DATA 0xff +#define number_of_psd_value 5 +#define number_of_sample 3 +#define number_of_2g_freq_pt 14 +#define number_of_5g_freq_pt 10 + #define config_phydm_read_rf_check_8822b(data) (data != INVALID_RF_DATA) #define config_phydm_read_txagc_check_8822b(data) (data != INVALID_TXAGC_DATA) -u4Byte +u32 config_phydm_read_rf_reg_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ); + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e rf_path, + u32 reg_addr, + u32 bit_mask +); -BOOLEAN +boolean config_phydm_write_rf_reg_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E RFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ); - -BOOLEAN + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e rf_path, + u32 reg_addr, + u32 bit_mask, + u32 data +); + +boolean config_phydm_write_txagc_8822b( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ); + struct PHY_DM_STRUCT *p_dm_odm, + u32 power_index, + enum odm_rf_radio_path_e path, + u8 hw_rate +); -u1Byte +u8 config_phydm_read_txagc_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ); - -BOOLEAN -config_phydm_switch_band_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ); - -BOOLEAN -config_phydm_switch_channel_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch - ); - -BOOLEAN -config_phydm_switch_bandwidth_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ); - -BOOLEAN -config_phydm_switch_channel_bw_8822b( - IN PDM_ODM_T pDM_Odm, - IN u1Byte central_ch, - IN u1Byte primary_ch_idx, - IN ODM_BW_E bandwidth - ); - -BOOLEAN + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e path, + u8 hw_rate +); + +void +phydm_dynamic_spur_det_elimitor( + struct PHY_DM_STRUCT *p_dm_odm +); + +boolean +config_phydm_switch_band_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 central_ch +); + +boolean +config_phydm_switch_channel_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 central_ch +); + +boolean +config_phydm_switch_bandwidth_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 primary_ch_idx, + enum odm_bw_e bandwidth +); + +boolean +config_phydm_switch_channel_bw_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 central_ch, + u8 primary_ch_idx, + enum odm_bw_e bandwidth +); + +boolean config_phydm_trx_mode_8822b( - IN PDM_ODM_T pDM_Odm, - IN ODM_RF_PATH_E TxPath, - IN ODM_RF_PATH_E RxPath, - IN BOOLEAN bTx2Path - ); + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_path_e tx_path, + enum odm_rf_path_e rx_path, + boolean is_tx2_path +); -BOOLEAN -config_phydm_parameter_init( - IN PDM_ODM_T pDM_Odm, - IN ODM_PARAMETER_INIT_E type - ); +boolean +config_phydm_parameter_init_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_parameter_init_e type +); /* ======================================================================== */ /* These following functions can be used for PHY DM only*/ -BOOLEAN +boolean phydm_write_txagc_1byte_8822b( - IN PDM_ODM_T pDM_Odm, - IN u4Byte PowerIndex, - IN ODM_RF_RADIO_PATH_E Path, - IN u1Byte HwRate - ); + struct PHY_DM_STRUCT *p_dm_odm, + u32 power_index, + enum odm_rf_radio_path_e path, + u8 hw_rate +); -VOID +void phydm_init_hw_info_by_rfe_type_8822b( - IN PDM_ODM_T pDM_Odm - ); + struct PHY_DM_STRUCT *p_dm_odm +); -s4Byte +s32 phydm_get_condition_number_8822B( - IN PDM_ODM_T pDM_Odm - ); + struct PHY_DM_STRUCT *p_dm_odm +); /* ======================================================================== */ #endif /* RTL8822B_SUPPORT == 1 */ #endif /* __INC_PHYDM_API_H_8822B__ */ - - diff --git a/hal/phydm/rtl8822b/phydm_regconfig8822b.c b/hal/phydm/rtl8822b/phydm_regconfig8822b.c index de6f7e6..7a06ebf 100644 --- a/hal/phydm/rtl8822b/phydm_regconfig8822b.c +++ b/hal/phydm/rtl8822b/phydm_regconfig8822b.c @@ -1,7 +1,7 @@ /****************************************************************************** * * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -21,197 +21,292 @@ #include "mp_precomp.h" #include "../phydm_precomp.h" -#if (RTL8822B_SUPPORT == 1) +#if (RTL8822B_SUPPORT == 1) void -odm_ConfigRFReg_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ) +odm_config_rf_reg_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data, + enum odm_rf_radio_path_e RF_PATH, + u32 reg_addr +) { - if ((Addr == 0xfe) || (Addr == 0xffe)) { - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif + if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + if (addr == 0xffe) + phydm_set_reg_by_fw(p_dm_odm, + PHYDM_HALMAC_CMD_DELAY_MS, + reg_addr, + data, + RFREGOFFSETMASK, + RF_PATH, + 50); + else if (addr == 0xfe) + phydm_set_reg_by_fw(p_dm_odm, + PHYDM_HALMAC_CMD_DELAY_US, + reg_addr, + data, + RFREGOFFSETMASK, + RF_PATH, + 100); + else { + phydm_set_reg_by_fw(p_dm_odm, + PHYDM_HALMAC_CMD_RF_W, + reg_addr, + data, + RFREGOFFSETMASK, + RF_PATH, + 0); + phydm_set_reg_by_fw(p_dm_odm, + PHYDM_HALMAC_CMD_DELAY_US, + reg_addr, + data, + RFREGOFFSETMASK, + RF_PATH, + 1); + } } else { - ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + if (addr == 0xffe) { +#ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); +#else + ODM_delay_ms(50); +#endif + } else if (addr == 0xfe) { +#ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_us(100); +#else + ODM_delay_us(100); +#endif + } else { + odm_set_rf_reg(p_dm_odm, RF_PATH, reg_addr, RFREGOFFSETMASK, data); - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); - } + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + } + } } -void -odm_ConfigRF_RadioA_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) +void +odm_config_rf_radio_a_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data +) { - u4Byte content = 0x1000; /* RF_Content: radioa_txt */ - u4Byte maskforPhySet = (u4Byte)(content&0xE000); + u32 content = 0x1000; /* RF_Content: radioa_txt */ + u32 maskfor_phy_set = (u32)(content & 0xE000); - odm_ConfigRFReg_8822B(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + odm_config_rf_reg_8822b(p_dm_odm, addr, data, ODM_RF_PATH_A, addr | maskfor_phy_set); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", addr, data)); } -void -odm_ConfigRF_RadioB_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ) +void +odm_config_rf_radio_b_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data +) { - u4Byte content = 0x1001; /* RF_Content: radiob_txt */ - u4Byte maskforPhySet = (u4Byte)(content&0xE000); + u32 content = 0x1001; /* RF_Content: radiob_txt */ + u32 maskfor_phy_set = (u32)(content & 0xE000); - odm_ConfigRFReg_8822B(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); + odm_config_rf_reg_8822b(p_dm_odm, addr, data, ODM_RF_PATH_B, addr | maskfor_phy_set); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n", addr, data)); } -void -odm_ConfigMAC_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ) +void +odm_config_mac_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u8 data +) { - ODM_Write1Byte(pDM_Odm, Addr, Data); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); + if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) + phydm_set_reg_by_fw(p_dm_odm, + PHYDM_HALMAC_CMD_MAC_W8, + addr, + data, + 0, + 0, + 0); + else + odm_write_1byte(p_dm_odm, addr, data); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> config_mac: [MAC_REG] %08X %08X\n", addr, data)); } void -odm_UpdateAgcBigJumpLmt_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data +odm_update_agc_big_jump_lmt_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data ) { - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - u1Byte rfGainIdx = (u1Byte)((Data & 0xFF000000) >> 24); - u1Byte bbGainIdx = (u1Byte)((Data & 0x00ff0000) >> 16); - u1Byte agcTableIdx = (u1Byte)((Data & 0x00000f00) >> 8); - static BOOLEAN isLimit; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24); + u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16); + u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8); + static boolean is_limit; - if (Addr != 0x81c) + if (addr != 0x81c) return; - /*DbgPrint("Data = 0x%x, rfGainIdx = 0x%x, bbGainIdx = 0x%x, agcTableIdx = 0x%d\n", Data, rfGainIdx, bbGainIdx, agcTableIdx);*/ - /*DbgPrint("rfGainIdx = 0x%x, pDM_DigTable->rfGainIdx = 0x%x\n", rfGainIdx, pDM_DigTable->rfGainIdx);*/ + /*dbg_print("data = 0x%x, rf_gain_idx = 0x%x, bb_gain_idx = 0x%x, agc_table_idx = 0x%x\n", data, rf_gain_idx, bb_gain_idx, agc_table_idx);*/ + /*dbg_print("rf_gain_idx = 0x%x, p_dm_dig_table->rf_gain_idx = 0x%x\n", rf_gain_idx, p_dm_dig_table->rf_gain_idx);*/ - if (bbGainIdx > 0x3c) { - if ((rfGainIdx == pDM_DigTable->rfGainIdx) && (isLimit == FALSE)) { - isLimit = TRUE; - pDM_DigTable->bigJumpLmt[agcTableIdx] = bbGainIdx - 2; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("===> [AGC_TAB] bigJumpLmt [%d] = 0x%x\n", agcTableIdx, pDM_DigTable->bigJumpLmt[agcTableIdx])); - } + if (bb_gain_idx > 0x3c) { + if ((rf_gain_idx == p_dm_dig_table->rf_gain_idx) && (is_limit == false)) { + is_limit = true; + p_dm_dig_table->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n", agc_table_idx, p_dm_dig_table->big_jump_lmt[agc_table_idx])); + } } else - isLimit = FALSE; - - pDM_DigTable->rfGainIdx = rfGainIdx; - + is_limit = false; + + p_dm_dig_table->rf_gain_idx = rf_gain_idx; + } -void -odm_ConfigBB_AGC_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) +void +odm_config_bb_agc_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 bitmask, + u32 data +) { - odm_UpdateAgcBigJumpLmt_8822B(pDM_Odm, Addr, Data); - - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + odm_update_agc_big_jump_lmt_8822b(p_dm_odm, addr, data); - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); + if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) + phydm_set_reg_by_fw(p_dm_odm, + PHYDM_HALMAC_CMD_BB_W32, + addr, + data, + bitmask, + 0, + 0); + else + odm_set_bb_reg(p_dm_odm, addr, bitmask, data); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data)); } void -odm_ConfigBB_PHY_REG_PG_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe || Addr == 0xffe) { - #ifdef CONFIG_LONG_DELAY_ISSUE +odm_config_bb_phy_reg_pg_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 band, + u32 rf_path, + u32 tx_num, + u32 addr, + u32 bitmask, + u32 data +) +{ + if (addr == 0xfe || addr == 0xffe) { +#ifdef CONFIG_LONG_DELAY_ISSUE ODM_sleep_ms(50); - #else +#else ODM_delay_ms(50); - #endif +#endif } else { -#if (!(DM_ODM_SUPPORT_TYPE&ODM_AP)) - PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + phy_store_tx_power_by_rate(p_dm_odm->adapter, band, rf_path, tx_num, addr, bitmask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PHY_StoreTxPowerByRate(p_dm_odm->adapter, band, rf_path, tx_num, addr, bitmask, data); #endif } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data)); } -void -odm_ConfigBB_PHY_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ) -{ - if (Addr == 0xfe) - #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); - #else - ODM_delay_ms(50); - #endif - else if (Addr == 0xfd) - ODM_delay_ms(5); - else if (Addr == 0xfc) - ODM_delay_ms(1); - else if (Addr == 0xfb) - ODM_delay_us(50); - else if (Addr == 0xfa) - ODM_delay_us(5); - else if (Addr == 0xf9) - ODM_delay_us(1); - else - ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); +void +odm_config_bb_phy_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 bitmask, + u32 data +) +{ + if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + u32 delay_time = 0; + + if (addr >= 0xf9 && addr <= 0xfe) { + if (addr == 0xfe || addr == 0xfb) + delay_time = 50; + else if (addr == 0xfd || addr == 0xfa) + delay_time = 5; + else + delay_time = 1; + + if (addr >= 0xfc && addr <=0xfe) + phydm_set_reg_by_fw(p_dm_odm, + PHYDM_HALMAC_CMD_DELAY_MS, + addr, + data, + bitmask, + 0, + delay_time); + else + phydm_set_reg_by_fw(p_dm_odm, + PHYDM_HALMAC_CMD_DELAY_US, + addr, + data, + bitmask, + 0, + delay_time); + } else + phydm_set_reg_by_fw(p_dm_odm, + PHYDM_HALMAC_CMD_BB_W32, + addr, + data, + bitmask, + 0, + 0); + } else { + if (addr == 0xfe) +#ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); +#else + ODM_delay_ms(50); +#endif + else if (addr == 0xfd) + ODM_delay_ms(5); + else if (addr == 0xfc) + ODM_delay_ms(1); + else if (addr == 0xfb) + ODM_delay_us(50); + else if (addr == 0xfa) + ODM_delay_us(5); + else if (addr == 0xf9) + ODM_delay_us(1); + else + odm_set_bb_reg(p_dm_odm, addr, bitmask, data); + } - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> config_bb: [PHY_REG] %08X %08X\n", addr, data)); } void -odm_ConfigBB_TXPWR_LMT_8822B( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ) +odm_config_bb_txpwr_lmt_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *regulation, + u8 *band, + u8 *bandwidth, + u8 *rate_section, + u8 *rf_path, + u8 *channel, + u8 *power_limit +) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, - Bandwidth, RateSection, RfPath, Channel, PowerLimit); +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + phy_set_tx_power_limit(p_dm_odm, regulation, band, + bandwidth, rate_section, rf_path, channel, power_limit); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PHY_SetTxPowerLimit(p_dm_odm, regulation, band, + bandwidth, rate_section, rf_path, channel, power_limit); #endif } #endif - diff --git a/hal/phydm/rtl8822b/phydm_regconfig8822b.h b/hal/phydm/rtl8822b/phydm_regconfig8822b.h index 894ddf8..0b9ef68 100644 --- a/hal/phydm/rtl8822b/phydm_regconfig8822b.h +++ b/hal/phydm/rtl8822b/phydm_regconfig8822b.h @@ -1,7 +1,7 @@ /****************************************************************************** * * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -23,81 +23,80 @@ #if (RTL8822B_SUPPORT == 1) void -odm_ConfigRFReg_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data, - IN ODM_RF_RADIO_PATH_E RF_PATH, - IN u4Byte RegAddr - ); +odm_config_rf_reg_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data, + enum odm_rf_radio_path_e RF_PATH, + u32 reg_addr +); -void -odm_ConfigRF_RadioA_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); +void +odm_config_rf_radio_a_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data +); -void -odm_ConfigRF_RadioB_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data - ); +void +odm_config_rf_radio_b_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data +); -void -odm_ConfigMAC_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u1Byte Data - ); +void +odm_config_mac_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u8 data +); void -odm_UpdateAgcBigJumpLmt_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Data +odm_update_agc_big_jump_lmt_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data ); -void -odm_ConfigBB_AGC_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); +void +odm_config_bb_agc_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 bitmask, + u32 data +); void -odm_ConfigBB_PHY_REG_PG_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Band, - IN u4Byte RfPath, - IN u4Byte TxNum, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); +odm_config_bb_phy_reg_pg_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 band, + u32 rf_path, + u32 tx_num, + u32 addr, + u32 bitmask, + u32 data +); -void -odm_ConfigBB_PHY_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte Addr, - IN u4Byte Bitmask, - IN u4Byte Data - ); +void +odm_config_bb_phy_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 bitmask, + u32 data +); void -odm_ConfigBB_TXPWR_LMT_8822B( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte Regulation, - IN pu1Byte Band, - IN pu1Byte Bandwidth, - IN pu1Byte RateSection, - IN pu1Byte RfPath, - IN pu1Byte Channel, - IN pu1Byte PowerLimit - ); +odm_config_bb_txpwr_lmt_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *regulation, + u8 *band, + u8 *bandwidth, + u8 *rate_section, + u8 *rf_path, + u8 *channel, + u8 *power_limit +); #endif #endif /* RTL8822B_SUPPORT == 1*/ - diff --git a/hal/phydm/rtl8822b/phydm_rtl8822b.c b/hal/phydm/rtl8822b/phydm_rtl8822b.c index c94bf13..85c3c25 100644 --- a/hal/phydm/rtl8822b/phydm_rtl8822b.c +++ b/hal/phydm/rtl8822b/phydm_rtl8822b.c @@ -1,7 +1,7 @@ /****************************************************************************** * * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -18,9 +18,11 @@ * ******************************************************************************/ -/*============================================================ -// include files -============================================================*/ +#if 0 + /* ============================================================ + * include files + * ============================================================ */ +#endif #include "mp_precomp.h" #include "../phydm_precomp.h" @@ -28,6 +30,393 @@ #if (RTL8822B_SUPPORT == 1) +void +phydm_dynamic_switch_htstf_mumimo_8822b( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + s32 sig_power; + u32 value32; + u8 pwdb; -#endif /* RTL8822B_SUPPORT == 1 */ + value32 = odm_get_bb_reg(p_dm_odm, 0xF90, MASKDWORD); + pwdb = (u8)((value32 & MASKBYTE1) >> 8); + pwdb = pwdb >> 1; + sig_power = -110 + pwdb; + + /*if Pin > -60dBm, enable HT-STF gain controller, otherwise, if rssi < -65dBm, disable the controller*/ + + if (sig_power >= -60) + odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(17), 0x1); + else if (sig_power < -65) + odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(17), 0x0); + +} + +void +phydm_dynamic_parameters_ota( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + s32 sig_power; + u32 value32, bktreg, bktreg1, bktreg2, bktreg3; + u8 pwdb; + + value32 = odm_get_bb_reg(p_dm_odm, 0xF90, MASKDWORD); + pwdb = (u8)((value32 & MASKBYTE1) >> 8); + pwdb = pwdb >> 1; + sig_power = -110 + pwdb; + + bktreg = odm_get_bb_reg(p_dm_odm, 0x98c, MASKDWORD); + bktreg1 = odm_get_bb_reg(p_dm_odm, 0x818, MASKDWORD); + bktreg2 = odm_get_bb_reg(p_dm_odm, 0x98c, MASKDWORD); + bktreg3 = odm_get_bb_reg(p_dm_odm, 0x818, MASKDWORD); + + if ((*p_dm_odm->p_channel <= 14) && (*p_dm_odm->p_band_width == ODM_BW20M)) { + if (sig_power >= -60) { + odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(17), 0x1); + odm_set_bb_reg(p_dm_odm, 0x98c, 0x7fc0000, 0x0); + odm_set_bb_reg(p_dm_odm, 0x818, 0x7000000, 0x1); + odm_set_bb_reg(p_dm_odm, 0xc04, BIT(18), 0x1); + odm_set_bb_reg(p_dm_odm, 0xe04, BIT(18), 0x1); + if (p_dm_odm->p_advance_ota & BIT(1)) { + odm_set_bb_reg(p_dm_odm, 0x19d8, MASKDWORD, 0x444); + odm_set_bb_reg(p_dm_odm, 0x19d4, MASKDWORD, 0x4444aaaa); + } else if (p_dm_odm->p_advance_ota & BIT(2)) { + odm_set_bb_reg(p_dm_odm, 0x19d8, MASKDWORD, 0x444); + odm_set_bb_reg(p_dm_odm, 0x19d4, MASKDWORD, 0x444444aa); + } + } else if (sig_power < -65) { + odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(17), 0x0); + odm_set_bb_reg(p_dm_odm, 0x98c, MASKDWORD, 0x43440000); + odm_set_bb_reg(p_dm_odm, 0x818, 0x7000000, 0x4); + odm_set_bb_reg(p_dm_odm, 0xc04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xe04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x19d8, MASKDWORD, 0xaaa); + odm_set_bb_reg(p_dm_odm, 0x19d4, MASKDWORD, 0xaaaaaaaa); + } + } else { + //odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(17), 0x0); + odm_set_bb_reg(p_dm_odm, 0x98c, MASKDWORD, 0x43440000); + odm_set_bb_reg(p_dm_odm, 0x818, 0x7000000, 0x4); + odm_set_bb_reg(p_dm_odm, 0xc04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xe04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x19d8, MASKDWORD, 0xaaa); + odm_set_bb_reg(p_dm_odm, 0x19d4, MASKDWORD, 0xaaaaaaaa); + } +} + + +static +void +_setTxACaliValue( + struct PHY_DM_STRUCT *p_dm_odm, + u8 eRFPath, + u8 offset, + u8 TxABiaOffset + ) +{ + u32 modiTxAValue = 0; + u8 tmp1Byte = 0; + boolean bMinus = false; + u8 compValue = 0; + + + switch (offset) { + case 0x0: + odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X10124); + break; + case 0x1: + odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X10524); + break; + case 0x2: + odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X10924); + break; + case 0x3: + odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X10D24); + break; + case 0x4: + odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X30164); + break; + case 0x5: + odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X30564); + break; + case 0x6: + odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X30964); + break; + case 0x7: + odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X30D64); + break; + case 0x8: + odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X50195); + break; + case 0x9: + odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X50595); + break; + case 0xa: + odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X50995); + break; + case 0xb: + odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X50D95); + break; + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Invalid TxA band offset...\n")); + return; + break; + } + + /* Get TxA value */ + modiTxAValue = odm_get_rf_reg(p_dm_odm, eRFPath, 0x61, 0xFFFFF); + tmp1Byte = (u8)modiTxAValue&(BIT(3)|BIT(2)|BIT(1)|BIT(0)); + + /* check how much need to calibration */ + switch (TxABiaOffset) { + case 0xF6: + bMinus = true; + compValue = 3; + break; + + case 0xF4: + bMinus = true; + compValue = 2; + break; + + case 0xF2: + bMinus = true; + compValue = 1; + break; + + case 0xF3: + bMinus = false; + compValue = 1; + break; + + case 0xF5: + bMinus = false; + compValue = 2; + break; + + case 0xF7: + bMinus = false; + compValue = 3; + break; + + case 0xF9: + bMinus = false; + compValue = 4; + break; + + /* do nothing case */ + case 0xF0: + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("No need to do TxA bias current calibration\n")); + return; + break; + } + + /* calc correct value to calibrate */ + if (bMinus) { + if (tmp1Byte >= compValue) { + tmp1Byte -= compValue; + //modiTxAValue += tmp1Byte; + } else { + tmp1Byte = 0; + } + } else { + tmp1Byte += compValue; + if (tmp1Byte >= 7) { + tmp1Byte = 7; + } + } + + /* Write back to RF reg */ + odm_set_rf_reg(p_dm_odm, eRFPath, 0x30, 0xFFFF, (offset<<12|(modiTxAValue&0xFF0)|tmp1Byte)); +} + +static +void +_txaBiasCali4eachPath( + struct PHY_DM_STRUCT *p_dm_odm, + u8 eRFPath, + u8 efuseValue + ) +{ + /* switch on set TxA bias */ + odm_set_rf_reg(p_dm_odm, eRFPath, 0xEF, 0xFFFFF, 0x200); + + /* Set 12 sets of TxA value */ + _setTxACaliValue(p_dm_odm, eRFPath, 0x0, efuseValue); + _setTxACaliValue(p_dm_odm, eRFPath, 0x1, efuseValue); + _setTxACaliValue(p_dm_odm, eRFPath, 0x2, efuseValue); + _setTxACaliValue(p_dm_odm, eRFPath, 0x3, efuseValue); + _setTxACaliValue(p_dm_odm, eRFPath, 0x4, efuseValue); + _setTxACaliValue(p_dm_odm, eRFPath, 0x5, efuseValue); + _setTxACaliValue(p_dm_odm, eRFPath, 0x6, efuseValue); + _setTxACaliValue(p_dm_odm, eRFPath, 0x7, efuseValue); + _setTxACaliValue(p_dm_odm, eRFPath, 0x8, efuseValue); + _setTxACaliValue(p_dm_odm, eRFPath, 0x9, efuseValue); + _setTxACaliValue(p_dm_odm, eRFPath, 0xa, efuseValue); + _setTxACaliValue(p_dm_odm, eRFPath, 0xb, efuseValue); + + // switch off set TxA bias + odm_set_rf_reg(p_dm_odm, eRFPath, 0xEF, 0xFFFFF, 0x0); +} + +/* for 8822B PCIE D-cut patch only */ +/* Normal driver and MP driver need this patch */ + +void +phydm_txcurrentcalibration( + struct PHY_DM_STRUCT *p_dm_odm + ) +{ + u8 efuse0x3D8, efuse0x3D7; + u32 origRF0x18PathA = 0, origRF0x18PathB = 0; + if (!(p_dm_odm->support_ic_type & ODM_RTL8822B)) + return; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("8822b 5g tx current calibration 0x3d7=0x%X 0x3d8=0x%X\n", p_dm_odm->efuse0x3d7, p_dm_odm->efuse0x3d8)); + + /* save original 0x18 value */ + origRF0x18PathA = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xFFFFF); + origRF0x18PathB = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x18, 0xFFFFF); + + /* define efuse content */ + efuse0x3D8 = p_dm_odm->efuse0x3d8; + efuse0x3D7 = p_dm_odm->efuse0x3d7; + + /* check efuse content to judge whether need to calibration or not */ + if (0xFF == efuse0x3D7) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("efuse content 0x3D7 == 0xFF, No need to do TxA cali\n")); + return; + } + + /* write RF register for calibration */ + _txaBiasCali4eachPath(p_dm_odm, ODM_RF_PATH_A, efuse0x3D7); + _txaBiasCali4eachPath(p_dm_odm, ODM_RF_PATH_B, efuse0x3D8); + + /* restore original 0x18 value */ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xFFFFF, origRF0x18PathA); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x18, 0xFFFFF, origRF0x18PathB); +} + +void +phydm_dynamic_select_cck_path_8822b( + struct PHY_DM_STRUCT *p_dm +) +{ + struct _FALSE_ALARM_STATISTICS *p_fa_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm, PHYDM_FALSEALMCNT); + struct phydm_rtl8822b_struct *p_8822b = &p_dm->phydm_rtl8822b; + + if (p_dm->ap_total_num > 10) { + if (p_8822b->path_judge & BIT(2)) + odm_set_bb_reg(p_dm, 0xa04, 0x0f000000, 0x0); /*fix CCK Path A if AP nums > 10*/ + return; + } + + if (p_8822b->path_judge & BIT(2)) + return; + + ODM_RT_TRACE(p_dm, ODM_PHY_CONFIG, ODM_DBG_LOUD, + ("phydm 8822b cck rx path selection start\n")); + + if (p_8822b->path_judge & ODM_RF_A) { + p_8822b->path_a_cck_fa = (u16)p_fa_cnt->cnt_cck_fail; + p_8822b->path_judge &= ~ODM_RF_A; + odm_set_bb_reg(p_dm, 0xa04, 0x0f000000, 0x5); /*change to path B collect CCKFA*/ + } else if (p_8822b->path_judge & ODM_RF_B) { + p_8822b->path_b_cck_fa = (u16)p_fa_cnt->cnt_cck_fail; + p_8822b->path_judge &= ~ODM_RF_B; + + if (p_8822b->path_a_cck_fa <= p_8822b->path_b_cck_fa) + odm_set_bb_reg(p_dm, 0xa04, 0x0f000000, 0x0); /*FA A<=B choose A*/ + else + odm_set_bb_reg(p_dm, 0xa04, 0x0f000000, 0x5); /*FA B>A choose B*/ + + p_8822b->path_judge |= BIT(2); /*it means we have already choosed cck rx path*/ + } + + ODM_RT_TRACE(p_dm, ODM_PHY_CONFIG, ODM_DBG_LOUD, + ("path_a_fa = %d, path_b_fa = %d\n", p_8822b->path_a_cck_fa, p_8822b->path_b_cck_fa)); + +} + +void +phydm_somlrxhp_setting( + struct PHY_DM_STRUCT *p_dm_odm, + boolean switch_soml +) +{ + if (switch_soml == true) + odm_set_bb_reg(p_dm_odm, 0x19a8, MASKDWORD, 0xd10a0000); + else + odm_set_bb_reg(p_dm_odm, 0x19a8, MASKDWORD, 0x010a0000); + + /* Dynamic RxHP setting with SoML on/off apply on all RFE type, except of QFN eFEM (1,6,7,9) */ + /* SoML on -> 2.4G: high-to-low; 5G: always low */ + /* SoML off-> 2.4G, 5G: high-to-low */ + if (!((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7) || (p_dm_odm->rfe_type == 9))) { + if (*p_dm_odm->p_channel <= 14) { + /* TFBGA iFEM SoML on/off with RxHP always high-to-low */ + if (!((p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5))) { + if (switch_soml == true) { + odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08100000); + odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x0); + odm_set_bb_reg(p_dm_odm, 0xc04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xe04, (BIT(18)|BIT(21)), 0x0); + } else { + odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08108492); + odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x1); + } + } + } else if (*p_dm_odm->p_channel > 35) { + if ((switch_soml == true) && (!((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7) || (p_dm_odm->rfe_type == 9)))) { + odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08100000); + odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x0); + odm_set_bb_reg(p_dm_odm, 0xc04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(p_dm_odm, 0xe04, (BIT(18)|BIT(21)), 0x0); + } else { + odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08108492); + odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x1); + } + } + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Dynamic RxHP control with SoML is enable !!\n")); */ + } +} + + +void +phydm_hwsetting_8822b( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct phydm_rtl8822b_struct *p_8822b = &p_dm_odm->phydm_rtl8822b; + + if((p_dm_odm->p_advance_ota & PHYDM_HP_OTA_SETTING_A) || (p_dm_odm->p_advance_ota & PHYDM_HP_OTA_SETTING_B)) { + phydm_dynamic_parameters_ota(p_dm_odm); + } else { + if (p_dm_odm->bhtstfenabled == TRUE) + phydm_dynamic_switch_htstf_mumimo_8822b(p_dm_odm); + else + /* odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(17), 0x1);*/ + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_LOUD, ("Default HT-STF gain control setting\n")); + } + + if (p_dm_odm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) { + if (p_dm_odm->rssi_min <= 20) + phydm_somlrxhp_setting(p_dm_odm, false); + else if (p_dm_odm->rssi_min >= 25) + phydm_somlrxhp_setting(p_dm_odm, true); + } + + if (p_dm_odm->p_advance_ota & PHYDM_ASUS_OTA_SETTING_CCK_PATH) { + if (p_dm_odm->is_linked) + phydm_dynamic_select_cck_path_8822b(p_dm_odm); + else + p_8822b->path_judge |= ((~ BIT(2)) | ODM_RF_A | ODM_RF_B); + } + +} + +#endif /* RTL8822B_SUPPORT == 1 */ diff --git a/hal/phydm/rtl8822b/phydm_rtl8822b.h b/hal/phydm/rtl8822b/phydm_rtl8822b.h index 7d8e398..3b23b13 100644 --- a/hal/phydm/rtl8822b/phydm_rtl8822b.h +++ b/hal/phydm/rtl8822b/phydm_rtl8822b.h @@ -1,7 +1,7 @@ /****************************************************************************** * * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -21,7 +21,16 @@ #ifndef __ODM_RTL8822B_H__ #define __ODM_RTL8822B_H__ +void +phydm_somlrxhp_setting( + struct PHY_DM_STRUCT *p_dm_odm, + boolean switch_soml +); + +void +phydm_hwsetting_8822b( + struct PHY_DM_STRUCT *p_dm_odm +); #endif /* #define __ODM_RTL8822B_H__ */ #endif - diff --git a/hal/phydm/rtl8822b/version_rtl8822b.h b/hal/phydm/rtl8822b/version_rtl8822b.h index b4c8769..85de71d 100644 --- a/hal/phydm/rtl8822b/version_rtl8822b.h +++ b/hal/phydm/rtl8822b/version_rtl8822b.h @@ -4,6 +4,6 @@ Since 01/Aug/2015, the commit rules will be simplified. You do not need to fill up the version.h anymore, only the maintenance supervisor fills it before formal release. */ -#define RELEASE_DATE_8822B 20160526 +#define RELEASE_DATE_8822B 20170526 #define COMMIT_BY_8822B "BB_JOE" -#define RELEASE_VERSION_8822B 50 +#define RELEASE_VERSION_8822B 85 diff --git a/hal/phydm/txbf/halcomtxbf.c b/hal/phydm/txbf/halcomtxbf.c index 926a0bc..090b239 100644 --- a/hal/phydm/txbf/halcomtxbf.c +++ b/hal/phydm/txbf/halcomtxbf.c @@ -1,536 +1,552 @@ -//============================================================ -// Description: -// -// This file is for TXBF mechanism -// -//============================================================ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for TXBF mechanism + * + * ************************************************************ */ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (BEAMFORMING_SUPPORT == 1) /*Beamforming halcomtxbf API create by YuChen 2015/05*/ -VOID -halComTxbf_beamformInit( - IN PVOID pDM_VOID - ) +void +hal_com_txbf_beamform_init( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + boolean is_iqgen_setting_ok = false; - if (pDM_Odm->SupportICType & ODM_RTL8822B) - HalTxbf8822B_Init(pDM_Odm); + if (p_dm_odm->support_ic_type & ODM_RTL8814A) { + is_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(p_dm_odm); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] is_iqgen_setting_ok = %d\n", __func__, is_iqgen_setting_ok)); + } } /*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ -VOID -halComTxbf_ConfigGtab( - IN PVOID pDM_VOID +void +hal_com_txbf_config_gtab( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (pDM_Odm->SupportICType & ODM_RTL8822B) - HalTxbf8822B_ConfigGtab(pDM_Odm); + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_config_gtab(p_dm_odm); } -VOID -phydm_beamformSetSoundingEnter( - IN PVOID pDM_VOID - ) +void +phydm_beamform_set_sounding_enter( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_EnterWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_EnterWorkItem)); + if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_enter_work_item)) == false) + odm_schedule_work_item(&(p_txbf_info->txbf_enter_work_item)); #else - halComTxbf_EnterWorkItemCallback(pDM_Odm); + hal_com_txbf_enter_work_item_callback(p_dm_odm); #endif } -VOID -phydm_beamformSetSoundingLeave( - IN PVOID pDM_VOID - ) +void +phydm_beamform_set_sounding_leave( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_LeaveWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_LeaveWorkItem)); + if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_leave_work_item)) == false) + odm_schedule_work_item(&(p_txbf_info->txbf_leave_work_item)); #else - halComTxbf_LeaveWorkItemCallback(pDM_Odm); + hal_com_txbf_leave_work_item_callback(p_dm_odm); #endif } -VOID -phydm_beamformSetSoundingRate( - IN PVOID pDM_VOID - ) +void +phydm_beamform_set_sounding_rate( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_RateWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_RateWorkItem)); + if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_rate_work_item)) == false) + odm_schedule_work_item(&(p_txbf_info->txbf_rate_work_item)); #else - halComTxbf_RateWorkItemCallback(pDM_Odm); + hal_com_txbf_rate_work_item_callback(p_dm_odm); #endif } -VOID -phydm_beamformSetSoundingStatus( - IN PVOID pDM_VOID - ) +void +phydm_beamform_set_sounding_status( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_StatusWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_StatusWorkItem)); + if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_status_work_item)) == false) + odm_schedule_work_item(&(p_txbf_info->txbf_status_work_item)); #else - halComTxbf_StatusWorkItemCallback(pDM_Odm); + hal_com_txbf_status_work_item_callback(p_dm_odm); #endif } -VOID -phydm_beamformSetSoundingFwNdpa( - IN PVOID pDM_VOID - ) +void +phydm_beamform_set_sounding_fw_ndpa( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - if (*pDM_Odm->pbFwDwRsvdPageInProgress) - ODM_SetTimer(pDM_Odm, &(pTxbfInfo->Txbf_FwNdpaTimer), 5); + if (*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress) + odm_set_timer(p_dm_odm, &(p_txbf_info->txbf_fw_ndpa_timer), 5); else - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_FwNdpaWorkItem)); + odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item)); #else - halComTxbf_FwNdpaWorkItemCallback(pDM_Odm); + hal_com_txbf_fw_ndpa_work_item_callback(p_dm_odm); #endif } -VOID -phydm_beamformSetSoundingClk( - IN PVOID pDM_VOID - ) +void +phydm_beamform_set_sounding_clk( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_ClkWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_ClkWorkItem)); -#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER padapter = pDM_Odm->Adapter; + if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_clk_work_item)) == false) + odm_schedule_work_item(&(p_txbf_info->txbf_clk_work_item)); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct _ADAPTER *padapter = p_dm_odm->adapter; - rtw_run_in_thread_cmd(padapter, halComTxbf_ClkWorkItemCallback, padapter); + rtw_run_in_thread_cmd(padapter, hal_com_txbf_clk_work_item_callback, padapter); #else - halComTxbf_ClkWorkItemCallback(pDM_Odm); + hal_com_txbf_clk_work_item_callback(p_dm_odm); #endif } -VOID -phydm_beamformSetResetTxPath( - IN PVOID pDM_VOID - ) +void +phydm_beamform_set_reset_tx_path( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_ResetTxPathWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_ResetTxPathWorkItem)); + if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_reset_tx_path_work_item)) == false) + odm_schedule_work_item(&(p_txbf_info->txbf_reset_tx_path_work_item)); #else - halComTxbf_ResetTxPathWorkItemCallback(pDM_Odm); + hal_com_txbf_reset_tx_path_work_item_callback(p_dm_odm); #endif } -VOID -phydm_beamformSetGetTxRate( - IN PVOID pDM_VOID - ) +void +phydm_beamform_set_get_tx_rate( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_GetTxRateWorkItem)) == FALSE) - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_GetTxRateWorkItem)); + if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_get_tx_rate_work_item)) == false) + odm_schedule_work_item(&(p_txbf_info->txbf_get_tx_rate_work_item)); #else - halComTxbf_GetTxRateWorkItemCallback(pDM_Odm); + hal_com_txbf_get_tx_rate_work_item_callback(p_dm_odm); #endif } -VOID -halComTxbf_EnterWorkItemCallback( +void +hal_com_txbf_enter_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ) +) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; #else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #endif - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - u1Byte Idx = pTxbfInfo->TXBFIdx; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) - HalTxbfJaguar_Enter(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8192E) - HalTxbf8192E_Enter(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_Enter(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8822B) - HalTxbf8822B_Enter(pDM_Odm, Idx); + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + u8 idx = p_txbf_info->txbf_idx; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_enter(p_dm_odm, idx); + else if (p_dm_odm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_enter(p_dm_odm, idx); + else if (p_dm_odm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_enter(p_dm_odm, idx); + else if (p_dm_odm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_enter(p_dm_odm, idx); } -VOID -halComTxbf_LeaveWorkItemCallback( +void +hal_com_txbf_leave_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ) +) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; #else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #endif - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - u1Byte Idx = pTxbfInfo->TXBFIdx; + u8 idx = p_txbf_info->txbf_idx; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) - HalTxbfJaguar_Leave(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8192E) - HalTxbf8192E_Leave(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_Leave(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8822B) - HalTxbf8822B_Leave(pDM_Odm, Idx); + if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_leave(p_dm_odm, idx); + else if (p_dm_odm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_leave(p_dm_odm, idx); + else if (p_dm_odm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_leave(p_dm_odm, idx); + else if (p_dm_odm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_leave(p_dm_odm, idx); } -VOID -halComTxbf_FwNdpaWorkItemCallback( +void +hal_com_txbf_fw_ndpa_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ) +) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; #else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #endif - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - u1Byte Idx = pTxbfInfo->NdpaIdx; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) - HalTxbfJaguar_FwTxBF(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8192E) - HalTxbf8192E_FwTxBF(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_FwTxBF(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8822B) - HalTxbf8822B_FwTxBF(pDM_Odm, Idx); + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + u8 idx = p_txbf_info->ndpa_idx; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_fw_txbf(p_dm_odm, idx); + else if (p_dm_odm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_fw_tx_bf(p_dm_odm, idx); + else if (p_dm_odm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_fw_txbf(p_dm_odm, idx); + else if (p_dm_odm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_fw_txbf(p_dm_odm, idx); } -VOID -halComTxbf_ClkWorkItemCallback( +void +hal_com_txbf_clk_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ) +) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; #else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #endif - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - if (pDM_Odm->SupportICType & ODM_RTL8812) - HalTxbfJaguar_Clk_8812A(pDM_Odm); + if (p_dm_odm->support_ic_type & ODM_RTL8812) + hal_txbf_jaguar_clk_8812a(p_dm_odm); } -VOID -halComTxbf_RateWorkItemCallback( +void +hal_com_txbf_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ) +) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; #else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #endif - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - u1Byte BW = pTxbfInfo->BW; - u1Byte Rate = pTxbfInfo->Rate; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pDM_Odm->SupportICType & ODM_RTL8812) - HalTxbf8812A_setNDPArate(pDM_Odm, BW, Rate); - else if (pDM_Odm->SupportICType & ODM_RTL8192E) - HalTxbf8192E_setNDPArate(pDM_Odm, BW, Rate); - else if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_setNDPArate(pDM_Odm, BW, Rate); - + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + u8 BW = p_txbf_info->BW; + u8 rate = p_txbf_info->rate; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (p_dm_odm->support_ic_type & ODM_RTL8812) + hal_txbf_8812a_set_ndpa_rate(p_dm_odm, BW, rate); + else if (p_dm_odm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_set_ndpa_rate(p_dm_odm, BW, rate); + else if (p_dm_odm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_set_ndpa_rate(p_dm_odm, BW, rate); + } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -halComTxbf_FwNdpaTimerCallback( - IN PRT_TIMER pTimer - ) +void +hal_com_txbf_fw_ndpa_timer_callback( + struct timer_list *p_timer +) { - PADAPTER Adapter = (PADAPTER)pTimer->Adapter; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - if (*pDM_Odm->pbFwDwRsvdPageInProgress) - ODM_SetTimer(pDM_Odm, &(pTxbfInfo->Txbf_FwNdpaTimer), 5); + if (*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress) + odm_set_timer(p_dm_odm, &(p_txbf_info->txbf_fw_ndpa_timer), 5); else - PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_FwNdpaWorkItem)); + odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item)); } #endif -VOID -halComTxbf_StatusWorkItemCallback( +void +hal_com_txbf_status_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ) +) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; #else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #endif - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - u1Byte Idx = pTxbfInfo->TXBFIdx; + u8 idx = p_txbf_info->txbf_idx; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) - HalTxbfJaguar_Status(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8192E) - HalTxbf8192E_Status(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_Status(pDM_Odm, Idx); - else if (pDM_Odm->SupportICType & ODM_RTL8822B) - HalTxbf8822B_Status(pDM_Odm, Idx); + if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_status(p_dm_odm, idx); + else if (p_dm_odm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_status(p_dm_odm, idx); + else if (p_dm_odm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_status(p_dm_odm, idx); + else if (p_dm_odm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_status(p_dm_odm, idx); } -VOID -halComTxbf_ResetTxPathWorkItemCallback( +void +hal_com_txbf_reset_tx_path_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ) +) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; #else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #endif - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - u1Byte Idx = pTxbfInfo->TXBFIdx; + u8 idx = p_txbf_info->txbf_idx; + + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_reset_tx_path(p_dm_odm, idx); - if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_ResetTxPath(pDM_Odm, Idx); - } -VOID -halComTxbf_GetTxRateWorkItemCallback( +void +hal_com_txbf_get_tx_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ) +) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; #else - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #endif - - if (pDM_Odm->SupportICType & ODM_RTL8814A) - HalTxbf8814A_GetTxRate(pDM_Odm); + + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_get_tx_rate(p_dm_odm); } -BOOLEAN -HalComTxbf_Set( - IN PVOID pDM_VOID, - IN u1Byte setType, - IN PVOID pInBuf - ) +boolean +hal_com_txbf_set( + void *p_dm_void, + u8 set_type, + void *p_in_buf +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - pu1Byte pU1Tmp=(pu1Byte)pInBuf; - PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 *p_u1_tmp = (u8 *)p_in_buf; + struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] setType = 0x%X\n", __func__, setType)); - - switch(setType){ + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set_type = 0x%X\n", __func__, set_type)); + + switch (set_type) { case TXBF_SET_SOUNDING_ENTER: - pTxbfInfo->TXBFIdx = *pU1Tmp; - phydm_beamformSetSoundingEnter(pDM_Odm); - break; + p_txbf_info->txbf_idx = *p_u1_tmp; + phydm_beamform_set_sounding_enter(p_dm_odm); + break; case TXBF_SET_SOUNDING_LEAVE: - pTxbfInfo->TXBFIdx = *pU1Tmp; - phydm_beamformSetSoundingLeave(pDM_Odm); - break; + p_txbf_info->txbf_idx = *p_u1_tmp; + phydm_beamform_set_sounding_leave(p_dm_odm); + break; case TXBF_SET_SOUNDING_RATE: - pTxbfInfo->BW = pU1Tmp[0]; - pTxbfInfo->Rate = pU1Tmp[1]; - phydm_beamformSetSoundingRate(pDM_Odm); - break; + p_txbf_info->BW = p_u1_tmp[0]; + p_txbf_info->rate = p_u1_tmp[1]; + phydm_beamform_set_sounding_rate(p_dm_odm); + break; case TXBF_SET_SOUNDING_STATUS: - pTxbfInfo->TXBFIdx = *pU1Tmp; - phydm_beamformSetSoundingStatus(pDM_Odm); - break; + p_txbf_info->txbf_idx = *p_u1_tmp; + phydm_beamform_set_sounding_status(p_dm_odm); + break; case TXBF_SET_SOUNDING_FW_NDPA: - pTxbfInfo->NdpaIdx = *pU1Tmp; - phydm_beamformSetSoundingFwNdpa(pDM_Odm); - break; + p_txbf_info->ndpa_idx = *p_u1_tmp; + phydm_beamform_set_sounding_fw_ndpa(p_dm_odm); + break; case TXBF_SET_SOUNDING_CLK: - phydm_beamformSetSoundingClk(pDM_Odm); - break; - + phydm_beamform_set_sounding_clk(p_dm_odm); + break; + case TXBF_SET_TX_PATH_RESET: - pTxbfInfo->TXBFIdx = *pU1Tmp; - phydm_beamformSetResetTxPath(pDM_Odm); - break; + p_txbf_info->txbf_idx = *p_u1_tmp; + phydm_beamform_set_reset_tx_path(p_dm_odm); + break; case TXBF_SET_GET_TX_RATE: - phydm_beamformSetGetTxRate(pDM_Odm); - break; - + phydm_beamform_set_get_tx_rate(p_dm_odm); + break; + } - return TRUE; + return true; } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -BOOLEAN -HalComTxbf_Get( - IN PADAPTER Adapter, - IN u1Byte getType, - OUT PVOID pOutBuf - ) +boolean +hal_com_txbf_get( + struct _ADAPTER *adapter, + u8 get_type, + void *p_out_buf +) { - PHAL_DATA_TYPE pHalData=GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - PBOOLEAN pBoolean=(PBOOLEAN)pOutBuf; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (getType == TXBF_GET_EXPLICIT_BEAMFORMEE) { - if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(Adapter)) - *pBoolean = FALSE; - else if (/*IS_HARDWARE_TYPE_8822B(Adapter) ||*/ - IS_HARDWARE_TYPE_8821B(Adapter) || - IS_HARDWARE_TYPE_8192E(Adapter) || - IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) - *pBoolean = TRUE; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + boolean *p_boolean = (boolean *)p_out_buf; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (get_type == TXBF_GET_EXPLICIT_BEAMFORMEE) { + if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter)) + *p_boolean = false; + else if (/*IS_HARDWARE_TYPE_8822B(adapter) ||*/ + IS_HARDWARE_TYPE_8821B(adapter) || + IS_HARDWARE_TYPE_8192E(adapter) || + IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + *p_boolean = true; else - *pBoolean = FALSE; - } else if (getType == TXBF_GET_EXPLICIT_BEAMFORMER) { - if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(Adapter)) - *pBoolean = FALSE; - else if (/*IS_HARDWARE_TYPE_8822B(Adapter) ||*/ - IS_HARDWARE_TYPE_8821B(Adapter) || - IS_HARDWARE_TYPE_8192E(Adapter) || - IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) { - if(pHalData->RF_Type == RF_2T2R || pHalData->RF_Type == RF_3T3R) - *pBoolean = TRUE; + *p_boolean = false; + } else if (get_type == TXBF_GET_EXPLICIT_BEAMFORMER) { + if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter)) + *p_boolean = false; + else if (/*IS_HARDWARE_TYPE_8822B(adapter) ||*/ + IS_HARDWARE_TYPE_8821B(adapter) || + IS_HARDWARE_TYPE_8192E(adapter) || + IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) { + if (p_hal_data->RF_Type == RF_2T2R || p_hal_data->RF_Type == RF_3T3R) + *p_boolean = true; else - *pBoolean = FALSE; + *p_boolean = false; } else - *pBoolean = FALSE; - } else if (getType == TXBF_GET_MU_MIMO_STA) { + *p_boolean = false; + } else if (get_type == TXBF_GET_MU_MIMO_STA) { #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - if (IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter)) - *pBoolean = TRUE; + if (IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8821C(adapter)) + *p_boolean = true; else #endif - *pBoolean = FALSE; + *p_boolean = false; - } else if (getType == TXBF_GET_MU_MIMO_AP) { -#if (RTL8822B_SUPPORT == 1) - if (IS_HARDWARE_TYPE_8822B(Adapter)) - *pBoolean = TRUE; + } else if (get_type == TXBF_GET_MU_MIMO_AP) { +#if (RTL8822B_SUPPORT == 1) + if (IS_HARDWARE_TYPE_8822B(adapter)) + *p_boolean = true; else #endif - *pBoolean = FALSE; + *p_boolean = false; } - - return TRUE; -} -#endif + return true; +} +#endif -#endif +#endif diff --git a/hal/phydm/txbf/halcomtxbf.h b/hal/phydm/txbf/halcomtxbf.h index 7be4efd..0d95b69 100644 --- a/hal/phydm/txbf/halcomtxbf.h +++ b/hal/phydm/txbf/halcomtxbf.h @@ -1,24 +1,37 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __HAL_COM_TXBF_H__ #define __HAL_COM_TXBF_H__ /* -typedef BOOLEAN +typedef bool (*TXBF_GET)( - IN PVOID pAdapter, - IN u1Byte getType, - OUT PVOID pOutBuf + void* p_adapter, + u8 get_type, + void* p_out_buf ); -typedef BOOLEAN +typedef bool (*TXBF_SET)( - IN PVOID pAdapter, - IN u1Byte setType, - OUT PVOID pInBuf + void* p_adapter, + u8 set_type, + void* p_in_buf ); */ -#define TxBF_Nr(a, b) ((a > b) ? (b) : (a)) -typedef enum _TXBF_SET_TYPE{ +enum txbf_set_type { TXBF_SET_SOUNDING_ENTER, TXBF_SET_SOUNDING_LEAVE, TXBF_SET_SOUNDING_RATE, @@ -27,155 +40,154 @@ typedef enum _TXBF_SET_TYPE{ TXBF_SET_SOUNDING_CLK, TXBF_SET_TX_PATH_RESET, TXBF_SET_GET_TX_RATE -}TXBF_SET_TYPE,*PTXBF_SET_TYPE; +}; -typedef enum _TXBF_GET_TYPE{ +enum txbf_get_type { TXBF_GET_EXPLICIT_BEAMFORMEE, TXBF_GET_EXPLICIT_BEAMFORMER, TXBF_GET_MU_MIMO_STA, TXBF_GET_MU_MIMO_AP -}TXBF_GET_TYPE,*PTXBF_GET_TYPE; - - - -//2 HAL TXBF related -typedef struct _HAL_TXBF_INFO { - u1Byte TXBFIdx; - u1Byte NdpaIdx; - u1Byte BW; - u1Byte Rate; - - RT_TIMER Txbf_FwNdpaTimer; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_WORK_ITEM Txbf_EnterWorkItem; - RT_WORK_ITEM Txbf_LeaveWorkItem; - RT_WORK_ITEM Txbf_FwNdpaWorkItem; - RT_WORK_ITEM Txbf_ClkWorkItem; - RT_WORK_ITEM Txbf_StatusWorkItem; - RT_WORK_ITEM Txbf_RateWorkItem; - RT_WORK_ITEM Txbf_ResetTxPathWorkItem; - RT_WORK_ITEM Txbf_GetTxRateWorkItem; +}; + + + +/* 2 HAL TXBF related */ +struct _HAL_TXBF_INFO { + u8 txbf_idx; + u8 ndpa_idx; + u8 BW; + u8 rate; + + struct timer_list txbf_fw_ndpa_timer; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_WORK_ITEM txbf_enter_work_item; + RT_WORK_ITEM txbf_leave_work_item; + RT_WORK_ITEM txbf_fw_ndpa_work_item; + RT_WORK_ITEM txbf_clk_work_item; + RT_WORK_ITEM txbf_status_work_item; + RT_WORK_ITEM txbf_rate_work_item; + RT_WORK_ITEM txbf_reset_tx_path_work_item; + RT_WORK_ITEM txbf_get_tx_rate_work_item; #endif -} HAL_TXBF_INFO, *PHAL_TXBF_INFO; +}; #if (BEAMFORMING_SUPPORT == 1) -VOID -halComTxbf_beamformInit( - IN PVOID pDM_VOID - ); +void +hal_com_txbf_beamform_init( + void *p_dm_void +); -VOID -halComTxbf_ConfigGtab( - IN PVOID pDM_VOID - ); +void +hal_com_txbf_config_gtab( + void *p_dm_void +); -VOID -halComTxbf_EnterWorkItemCallback( +void +hal_com_txbf_enter_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ); +); -VOID -halComTxbf_LeaveWorkItemCallback( +void +hal_com_txbf_leave_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ); +); -VOID -halComTxbf_FwNdpaWorkItemCallback( +void +hal_com_txbf_fw_ndpa_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ); +); -VOID -halComTxbf_ClkWorkItemCallback( +void +hal_com_txbf_clk_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ); +); -VOID -halComTxbf_ResetTxPathWorkItemCallback( +void +hal_com_txbf_reset_tx_path_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ); +); -VOID -halComTxbf_GetTxRateWorkItemCallback( +void +hal_com_txbf_get_tx_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ); +); -VOID -halComTxbf_RateWorkItemCallback( +void +hal_com_txbf_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ); +); -VOID -halComTxbf_FwNdpaTimerCallback( - IN PRT_TIMER pTimer - ); +void +hal_com_txbf_fw_ndpa_timer_callback( + struct timer_list *p_timer +); -VOID -halComTxbf_StatusWorkItemCallback( +void +hal_com_txbf_status_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN PADAPTER Adapter + struct _ADAPTER *adapter #else - IN PVOID pDM_VOID + void *p_dm_void #endif - ); - -BOOLEAN -HalComTxbf_Set( - IN PVOID pDM_VOID, - IN u1Byte setType, - IN PVOID pInBuf - ); - -BOOLEAN -HalComTxbf_Get( - IN PADAPTER Adapter, - IN u1Byte getType, - OUT PVOID pOutBuf - ); +); + +boolean +hal_com_txbf_set( + void *p_dm_void, + u8 set_type, + void *p_in_buf +); + +boolean +hal_com_txbf_get( + struct _ADAPTER *adapter, + u8 get_type, + void *p_out_buf +); #else -#define halComTxbf_beamformInit(pDM_VOID) NULL -#define halComTxbf_ConfigGtab(pDM_VOID) NULL -#define halComTxbf_EnterWorkItemCallback(_Adapter) NULL -#define halComTxbf_LeaveWorkItemCallback(_Adapter) NULL -#define halComTxbf_FwNdpaWorkItemCallback(_Adapter) NULL -#define halComTxbf_ClkWorkItemCallback(_Adapter) NULL -#define halComTxbf_RateWorkItemCallback(_Adapter) NULL -#define halComTxbf_FwNdpaTimerCallback(_Adapter) NULL -#define halComTxbf_StatusWorkItemCallback(_Adapter) NULL -#define HalComTxbf_Get(_Adapter, _getType, _pOutBuf) +#define hal_com_txbf_beamform_init(p_dm_void) NULL +#define hal_com_txbf_config_gtab(p_dm_void) NULL +#define hal_com_txbf_enter_work_item_callback(_adapter) NULL +#define hal_com_txbf_leave_work_item_callback(_adapter) NULL +#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL +#define hal_com_txbf_clk_work_item_callback(_adapter) NULL +#define hal_com_txbf_rate_work_item_callback(_adapter) NULL +#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL +#define hal_com_txbf_status_work_item_callback(_adapter) NULL +#define hal_com_txbf_get(_adapter, _get_type, _pout_buf) #endif - -#endif // #ifndef __HAL_COM_TXBF_H__ +#endif /* #ifndef __HAL_COM_TXBF_H__ */ diff --git a/hal/phydm/txbf/haltxbf8192e.c b/hal/phydm/txbf/haltxbf8192e.c index 073dfdc..8b1df1e 100644 --- a/hal/phydm/txbf/haltxbf8192e.c +++ b/hal/phydm/txbf/haltxbf8192e.c @@ -1,392 +1,405 @@ -//============================================================ -// Description: -// -// This file is for 8192E TXBF mechanism -// -//============================================================ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for 8192E TXBF mechanism + * + * ************************************************************ */ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (BEAMFORMING_SUPPORT == 1) #if (RTL8192E_SUPPORT == 1) -VOID -HalTxbf8192E_setNDPArate( - IN PVOID pDM_VOID, - IN u1Byte BW, - IN u1Byte Rate +void +hal_txbf_8192e_set_ndpa_rate( + void *p_dm_void, + u8 BW, + u8 rate ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8192E, (Rate << 2 | BW)); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW)); } -VOID -halTxbf8192E_RfMode( - IN PVOID pDM_VOID, - IN PRT_BEAMFORMING_INFO pBeamInfo +void +hal_txbf_8192e_rf_mode( + void *p_dm_void, + struct _RT_BEAMFORMING_INFO *p_beam_info ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN bSelfBeamformer = FALSE; - BOOLEAN bSelfBeamformee = FALSE; - BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + boolean is_self_beamformer = false; + boolean is_self_beamformee = false; + enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - if (pDM_Odm->RFType == ODM_1T1R) + if (p_dm_odm->rf_type == ODM_1T1R) return; - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/ - - if (pBeamInfo->beamformee_su_cnt > 0) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ + + if (p_beam_info->beamformee_su_cnt > 0) { /*Path_A*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ /*Path_B*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*Select RX mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ } else { /*Path_A*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*Select RX mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ /*Path_B*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*Select RX mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ } - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ - if (pBeamInfo->beamformee_su_cnt > 0) { - ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x83321333); - ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, bMaskByte3, 0xc1); + if (p_beam_info->beamformee_su_cnt > 0) { + odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x83321333); + odm_set_bb_reg(p_dm_odm, 0xa04, MASKBYTE3, 0xc1); } else - ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x81121313); + odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x81121313); } -VOID -halTxbf8192E_FwTxBFCmd( - IN PVOID pDM_VOID +void +hal_txbf_8192e_fw_txbf_cmd( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx, Period0 = 0, Period1 = 0; - u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; - u1Byte u1TxBFParm[3] = {0}; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - if (pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (Idx == 0) { - if (pBeamInfo->BeamformeeEntry[Idx].bSound) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 idx, period0 = 0, period1 = 0; + u8 PageNum0 = 0xFF, PageNum1 = 0xFF; + u8 u1_tx_bf_parm[3] = {0}; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + if (p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (idx == 0) { + if (p_beam_info->beamformee_entry[idx].is_sound) PageNum0 = 0xFE; else - PageNum0 = 0xFF; //stop sounding - Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); - } else if (Idx == 1) { - if (pBeamInfo->BeamformeeEntry[Idx].bSound) + PageNum0 = 0xFF; /* stop sounding */ + period0 = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + } else if (idx == 1) { + if (p_beam_info->beamformee_entry[idx].is_sound) PageNum1 = 0xFE; else - PageNum1 = 0xFF; //stop sounding - Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + PageNum1 = 0xFF; /* stop sounding */ + period1 = (u8)(p_beam_info->beamformee_entry[idx].sound_period); } } } - u1TxBFParm[0] = PageNum0; - u1TxBFParm[1] = PageNum1; - u1TxBFParm[2] = (Period1 << 4) | Period0; - ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm); + u1_tx_bf_parm[0] = PageNum0; + u1_tx_bf_parm[1] = PageNum1; + u1_tx_bf_parm[2] = (period1 << 4) | period0; + odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, - ("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, + ("[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", __func__, PageNum0, period0, PageNum1, period1)); } -VOID -halTxbf8192E_DownloadNDPA( - IN PVOID pDM_VOID, - IN u1Byte Idx +void +hal_txbf_8192e_download_ndpa( + void *p_dm_void, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page; - u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; - BOOLEAN bSendBeacon = FALSE; - PADAPTER Adapter = pDM_Odm->Adapter; - u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 u1b_tmp = 0, tmp_reg422 = 0, head_page; + u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; + boolean is_send_beacon = false; + struct _ADAPTER *adapter = p_dm_odm->adapter; + u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/ - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE; + *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true; #endif - if (Idx == 0) - Head_Page = 0xFE; + if (idx == 0) + head_page = 0xFE; else - Head_Page = 0xFE; + head_page = 0xFE; - Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy); + phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy); /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1); - ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp | BIT0)); + u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8192E+1); + odm_write_1byte(p_dm_odm, REG_CR_8192E+1, (u1b_tmp | BIT(0))); /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2); - ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422 & (~BIT6)); + tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2); + odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422 & (~BIT(6))); - if (tmpReg422 & BIT6) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an Adapter is sending beacon.\n", __func__)); - bSendBeacon = TRUE; + if (tmp_reg422 & BIT(6)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an adapter is sending beacon.\n", __func__)); + is_send_beacon = true; } /*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/ - ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, Head_Page); + odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+1, head_page); do { /*Clear beacon valid check bit.*/ - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2); - ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2, (BcnValidReg | BIT0)); + bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2); + odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2, (bcn_valid_reg | BIT(0))); - // download NDPA rsvd page. - Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); + /* download NDPA rsvd page. */ + beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); -#if(DEV_BUS_TYPE == RT_PCI_INTERFACE) - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3); +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + u1b_tmp = odm_read_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3); count = 0; - while ((count < 20) && (u1bTmp & BIT4)) { + while ((count < 20) && (u1b_tmp & BIT(4))) { count++; ODM_delay_us(10); - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3); + u1b_tmp = odm_read_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3); } - ODM_Write1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3, u1bTmp | BIT4); + odm_write_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3, u1b_tmp | BIT(4)); #endif /*check rsvd page download OK.*/ - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2); + bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2); count = 0; - while (!(BcnValidReg & BIT0) && count < 20) { + while (!(bcn_valid_reg & BIT(0)) && count < 20) { count++; ODM_delay_us(10); - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2); + bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2); } - DLBcnCount++; - } while (!(BcnValidReg & BIT0) && DLBcnCount < 5); + dl_bcn_count++; + } while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5); - if (!(BcnValidReg & BIT0)) - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__)); + if (!(bcn_valid_reg & BIT(0))) + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__)); /*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/ - ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, TxPageBndy); + odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+1, tx_page_bndy); /*To make sure that if there exists an adapter which would like to send beacon.*/ /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ /*the beacon cannot be sent by HW.*/ /*2010.06.23. Added by tynli.*/ - if (bSendBeacon) - ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422); + if (is_send_beacon) + odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422); /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1); - ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp & (~BIT0))); + u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8192E+1); + odm_write_1byte(p_dm_odm, REG_CR_8192E+1, (u1b_tmp & (~BIT(0)))); - pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; + p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE; + *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false; #endif } -VOID -HalTxbf8192E_Enter( - IN PVOID pDM_VOID, - IN u1Byte BFerBFeeIdx +void +hal_txbf_8192e_enter( + void *p_dm_void, + u8 bfer_bfee_idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; - u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); - u4Byte CSI_Param; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - RT_BEAMFORMER_ENTRY BeamformerEntry; - u2Byte STAid = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0; + u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; + u8 bfee_idx = (bfer_bfee_idx & 0xF); + u32 csi_param; + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + u16 sta_id = 0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - halTxbf8192E_RfMode(pDM_Odm, pBeamformingInfo); + hal_txbf_8192e_rf_mode(p_dm_odm, p_beamforming_info); - if (pDM_Odm->RFType == ODM_2T2R) - ODM_Write4Byte(pDM_Odm, 0xd80, 0x00000000); /*Nc =2*/ + if (p_dm_odm->rf_type == ODM_2T2R) + odm_write_4byte(p_dm_odm, 0xd80, 0x00000000); /*nc =2*/ - if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { - BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; + if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { + beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx]; /*Sounding protocol control*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xCB); + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E, 0xCB); /*MAC address/Partial AID of Beamformer*/ - if (BFerIdx == 0) { + if (bfer_idx == 0) { for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), BeamformerEntry.MacAddr[i]); + odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), beamformer_entry.mac_addr[i]); } else { for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), BeamformerEntry.MacAddr[i]); + odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), beamformer_entry.mac_addr[i]); } - /*CSI report parameters of Beamformer Default use Nc = 2*/ - CSI_Param = 0x03090309; + /*CSI report parameters of Beamformer Default use nc = 2*/ + csi_param = 0x03090309; - ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8192E, CSI_Param); - ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8192E, CSI_Param); - ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8192E, CSI_Param); + odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param); + odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param); + odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param); /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E+3, 0x50); + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E+3, 0x50); } - if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { + beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx]; - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - STAid = BeamformeeEntry.MacId; + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + sta_id = beamformee_entry.mac_id; else - STAid = BeamformeeEntry.P_AID; + sta_id = beamformee_entry.p_aid; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], STAid=0x%X\n", __func__, STAid)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], sta_id=0x%X\n", __func__, sta_id)); /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ - if (BFeeIdx == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, STAid); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3) | BIT4 | BIT6 | BIT7); + if (bfee_idx == 0) { + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E, sta_id); + odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+3) | BIT(4) | BIT(6) | BIT(7)); } else - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, STAid | BIT12 | BIT14 | BIT15); + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E+2, sta_id | BIT(12) | BIT(14) | BIT(15)); /*CSI report parameters of Beamformee*/ - if (BFeeIdx == 0) { + if (bfee_idx == 0) { /*Get BIT24 & BIT25*/ - u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3; - - ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, STAid | BIT9); + u8 tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3; + + odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9)); } else { /*Set BIT25*/ - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, STAid | 0xE200); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, sta_id | 0xE200); } - phydm_Beamforming_Notify(pDM_Odm); + phydm_beamforming_notify(p_dm_odm); } } -VOID -HalTxbf8192E_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx +void +hal_txbf_8192e_leave( + void *p_dm_void, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - halTxbf8192E_RfMode(pDM_Odm, pBeamInfo); + hal_txbf_8192e_rf_mode(p_dm_odm, p_beam_info); /* Clear P_AID of Beamformee - * Clear MAC addresss of Beamformer + * Clear MAC addresss of Beamformer * Clear Associated Bfmee Sel */ - if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE) - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xC8); - - if (Idx == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, 0); - ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0); + if (p_beam_info->beamform_cap == BEAMFORMING_CAP_NONE) + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E, 0xC8); + + if (idx == 0) { + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E, 0); + odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0); } else { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2) & 0xF000); - ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60); + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E+2, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+2) & 0xF000); + odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60); } - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d\n", __func__, Idx)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx %d\n", __func__, idx)); } -VOID -HalTxbf8192E_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx +void +hal_txbf_8192e_status( + void *p_dm_void, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte BeamCtrlVal; - u4Byte BeamCtrlReg; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx]; - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - BeamCtrlVal = BeamformEntry.MacId; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u16 beam_ctrl_val; + u32 beam_ctrl_reg; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamform_entry = p_beam_info->beamformee_entry[idx]; + + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + beam_ctrl_val = beamform_entry.mac_id; else - BeamCtrlVal = BeamformEntry.P_AID; + beam_ctrl_val = beamform_entry.p_aid; - if (Idx == 0) - BeamCtrlReg = REG_TXBF_CTRL_8192E; + if (idx == 0) + beam_ctrl_reg = REG_TXBF_CTRL_8192E; else { - BeamCtrlReg = REG_TXBF_CTRL_8192E+2; - BeamCtrlVal |= BIT12 | BIT14 | BIT15; + beam_ctrl_reg = REG_TXBF_CTRL_8192E+2; + beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); } - if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamInfo->applyVmatrix == TRUE)) { - if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) - BeamCtrlVal |= BIT9; - else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) - BeamCtrlVal |= BIT10; + if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beam_info->apply_v_matrix == true)) { + if (beamform_entry.sound_bw == CHANNEL_WIDTH_20) + beam_ctrl_val |= BIT(9); + else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40) + beam_ctrl_val |= BIT(10); } else - BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); + beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); - ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); + odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d BeamCtrlReg %x BeamCtrlVal %x\n", __func__, Idx, BeamCtrlReg, BeamCtrlVal)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__, idx, beam_ctrl_reg, beam_ctrl_val)); } -VOID -HalTxbf8192E_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx +void +hal_txbf_8192e_fw_tx_bf( + void *p_dm_void, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) - halTxbf8192E_DownloadNDPA(pDM_Odm, Idx); + if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) + hal_txbf_8192e_download_ndpa(p_dm_odm, idx); - halTxbf8192E_FwTxBFCmd(pDM_Odm); + hal_txbf_8192e_fw_txbf_cmd(p_dm_odm); } #endif /* #if (RTL8192E_SUPPORT == 1)*/ #endif - diff --git a/hal/phydm/txbf/haltxbf8192e.h b/hal/phydm/txbf/haltxbf8192e.h index be70cc6..636e0d5 100644 --- a/hal/phydm/txbf/haltxbf8192e.h +++ b/hal/phydm/txbf/haltxbf8192e.h @@ -1,52 +1,74 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __HAL_TXBF_8192E_H__ #define __HAL_TXBF_8192E_H__ -#if (BEAMFORMING_SUPPORT == 1) #if (RTL8192E_SUPPORT == 1) -VOID -HalTxbf8192E_setNDPArate( - IN PVOID pDM_VOID, - IN u1Byte BW, - IN u1Byte Rate +#if (BEAMFORMING_SUPPORT == 1) + +void +hal_txbf_8192e_set_ndpa_rate( + void *p_dm_void, + u8 BW, + u8 rate ); -VOID -HalTxbf8192E_Enter( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_8192e_enter( + void *p_dm_void, + u8 idx +); -VOID -HalTxbf8192E_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_8192e_leave( + void *p_dm_void, + u8 idx +); -VOID -HalTxbf8192E_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_8192e_status( + void *p_dm_void, + u8 idx +); -VOID -HalTxbf8192E_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_8192e_fw_tx_bf( + void *p_dm_void, + u8 idx +); #else -#define HalTxbf8192E_setNDPArate(pDM_VOID, BW, Rate) -#define HalTxbf8192E_Enter(pDM_VOID, Idx) -#define HalTxbf8192E_Leave(pDM_VOID, Idx) -#define HalTxbf8192E_Status(pDM_VOID, Idx) -#define HalTxbf8192E_FwTxBF(pDM_VOID, Idx) +#define hal_txbf_8192e_set_ndpa_rate(p_dm_void, BW, rate) +#define hal_txbf_8192e_enter(p_dm_void, idx) +#define hal_txbf_8192e_leave(p_dm_void, idx) +#define hal_txbf_8192e_status(p_dm_void, idx) +#define hal_txbf_8192e_fw_tx_bf(p_dm_void, idx) #endif -#endif +#else + +#define hal_txbf_8192e_set_ndpa_rate(p_dm_void, BW, rate) +#define hal_txbf_8192e_enter(p_dm_void, idx) +#define hal_txbf_8192e_leave(p_dm_void, idx) +#define hal_txbf_8192e_status(p_dm_void, idx) +#define hal_txbf_8192e_fw_tx_bf(p_dm_void, idx) #endif +#endif diff --git a/hal/phydm/txbf/haltxbf8814a.c b/hal/phydm/txbf/haltxbf8814a.c index 532a970..0c700c3 100644 --- a/hal/phydm/txbf/haltxbf8814a.c +++ b/hal/phydm/txbf/haltxbf8814a.c @@ -1,9 +1,23 @@ -//============================================================ -// Description: -// -// This file is for 8814A TXBF mechanism -// -//============================================================ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for 8814A TXBF mechanism + * + * ************************************************************ */ #include "mp_precomp.h" #include "../phydm_precomp.h" @@ -11,437 +25,462 @@ #if (BEAMFORMING_SUPPORT == 1) #if (RTL8814A_SUPPORT == 1) -VOID -HalTxbf8814A_setNDPArate( - IN PVOID pDM_VOID, - IN u1Byte BW, - IN u1Byte Rate +boolean +phydm_beamforming_set_iqgen_8814A( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8814A, BW); - ODM_Write1Byte(pDM_Odm, REG_NDPA_RATE_8814A, (u1Byte) Rate); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0; + u16 counter = 0; + u32 rf_mode[4]; + + for (i = ODM_RF_PATH_A ; i < MAX_RF_PATH ; i++) + odm_set_rf_reg(p_dm_odm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ + + while (1) { + counter++; + for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) + odm_set_rf_reg(p_dm_odm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/ + + ODM_delay_us(2); + + for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) + rf_mode[i] = odm_get_rf_reg(p_dm_odm, i, RF_RCK_OS, 0xfffff); + + if ((rf_mode[0] == 0x18000) && (rf_mode[1] == 0x18000) && (rf_mode[2] == 0x18000) && (rf_mode[3] == 0x18000)) + break; + else if (counter == 100) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("iqgen setting fail:8814A\n")); + return false; + } + } + + for (i = ODM_RF_PATH_A ; i < MAX_RF_PATH ; i++) { + odm_set_rf_reg(p_dm_odm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/ + odm_set_rf_reg(p_dm_odm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*Enable TXIQGEN in Rx mode*/ + } + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*Enable TXIQGEN in Rx mode*/ + + for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) + odm_set_rf_reg(p_dm_odm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ + + return true; } + + +void +hal_txbf_8814a_set_ndpa_rate( + void *p_dm_void, + u8 BW, + u8 rate +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8814A, BW); + odm_write_1byte(p_dm_odm, REG_NDPA_RATE_8814A, (u8) rate); + +} +#if 0 #define PHYDM_MEMORY_MAP_BUF_READ 0x8000 #define PHYDM_CTRL_INFO_PAGE 0x660 -VOID -phydm_DataRate_8814A( - IN PDM_ODM_T pDM_Odm, - IN u1Byte macId, - OUT pu4Byte data, - IN u1Byte dataLen - ) +void +phydm_data_rate_8814a( + struct PHY_DM_STRUCT *p_dm_odm, + u8 mac_id, + u32 *data, + u8 data_len +) { - u1Byte i = 0; - u2Byte XReadDataAddr = 0; - - ODM_Write2Byte(pDM_Odm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE); - XReadDataAddr = PHYDM_MEMORY_MAP_BUF_READ + macId*32; /*Ctrl Info: 32Bytes for each macid(n)*/ - - if ((XReadDataAddr < PHYDM_MEMORY_MAP_BUF_READ) || (XReadDataAddr > 0x8FFF)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("XReadDataAddr(0x%x) is not correct!\n", XReadDataAddr)); - return; + u8 i = 0; + u16 x_read_data_addr = 0; + + odm_write_2byte(p_dm_odm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE); + x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*Ctrl Info: 32Bytes for each macid(n)*/ + + if ((x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ) || (x_read_data_addr > 0x8FFF)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("x_read_data_addr(0x%x) is not correct!\n", x_read_data_addr)); + return; } - + /* Read data */ - for (i = 0; i < dataLen; i++) - *(data+i) = ODM_Read2Byte(pDM_Odm, XReadDataAddr+i); - + for (i = 0; i < data_len; i++) + *(data + i) = odm_read_2byte(p_dm_odm, x_read_data_addr + i); + } +#endif -VOID -HalTxbf8814A_GetTxRate( - IN PVOID pDM_VOID +void +hal_txbf_8814a_get_tx_rate( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pEntry; - u4Byte TxRptData = 0; - u1Byte DataRate = 0xFF; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_entry; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u32 tx_rpt_data = 0; + u8 data_rate = 0xFF; - pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); - - phydm_DataRate_8814A(pDM_Odm, (u1Byte)pEntry->MacId, &TxRptData, 1); - DataRate = (u1Byte)TxRptData; - DataRate &= bMask7bits; /*Bit7 indicates SGI*/ + p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); - pDM_Odm->TxBfDataRate = DataRate; + data_rate = p_ra_table->link_tx_rate[(u8)p_entry->mac_id]; + data_rate &= 0x7f; /*Bit7 indicates SGI*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] pDM_Odm->TxBfDataRate = 0x%x\n", __func__, pDM_Odm->TxBfDataRate)); + p_beam_info->tx_bf_data_rate = data_rate; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] p_dm_odm->tx_bf_data_rate = 0x%x\n", __func__, p_beam_info->tx_bf_data_rate)); } -VOID -HalTxbf8814A_ResetTxPath( - IN PVOID pDM_VOID, - IN u1Byte idx +void +hal_txbf_8814a_reset_tx_path( + void *p_dm_void, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; #if DEV_BUS_TYPE == RT_USB_INTERFACE - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - u1Byte Nr_index = 0, txSS = 0; + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + u8 nr_index = 0, tx_ss = 0; if (idx < BEAMFORMEE_ENTRY_NUM) - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; + beamformee_entry = p_beamforming_info->beamformee_entry[idx]; else return; - if ((pDM_Odm->LastUSBHub) != (*pDM_Odm->HubUsbMode)) { - Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), BeamformeeEntry.CompSteeringNumofBFer); + if ((p_beamforming_info->last_usb_hub) != (*p_dm_odm->hub_usb_mode)) { + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), beamformee_entry.comp_steering_num_of_bfer); - if (*pDM_Odm->HubUsbMode == 2) { - if (pDM_Odm->RFType == ODM_4T4R) - txSS = 0xf; - else if (pDM_Odm->RFType == ODM_3T3R) - txSS = 0xe; + if (*p_dm_odm->hub_usb_mode == 2) { + if (p_dm_odm->rf_type == ODM_4T4R) + tx_ss = 0xf; + else if (p_dm_odm->rf_type == ODM_3T3R) + tx_ss = 0xe; else - txSS = 0x6; - } else if (*pDM_Odm->HubUsbMode == 1) /*USB 2.0 always 2Tx*/ - txSS = 0x6; + tx_ss = 0x6; + } else if (*p_dm_odm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/ + tx_ss = 0x6; else - txSS = 0x6; - - if (txSS == 0xf) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93f); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskDWord, 0x93f93f0); - } else if (txSS == 0xe) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93e); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e93e0); - } else if (txSS == 0x6) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x936); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskLWord, 0x9360); + tx_ss = 0x6; + + if (tx_ss == 0xf) { + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f); + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0); + } else if (tx_ss == 0xe) { + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e); + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0); + } else if (tx_ss == 0x6) { + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936); + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360); } if (idx == 0) { - switch (Nr_index) { + switch (nr_index) { case 0: - break; + break; case 1: /*Nsts = 2 BC*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ - break; + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + break; case 2: /*Nsts = 3 BCD*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ - break; + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + break; - default: /*Nr>3, same as Case 3*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ - break; + default: /*nr>3, same as Case 3*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + break; } } else { - switch (Nr_index) { + switch (nr_index) { case 0: break; case 1: /*Nsts = 2 BC*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ - break; + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + break; case 2: /*Nsts = 3 BCD*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ - break; + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + break; - default: /*Nr>3, same as Case 3*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ - break; + default: /*nr>3, same as Case 3*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + break; } } - pDM_Odm->LastUSBHub = *pDM_Odm->HubUsbMode; + p_beamforming_info->last_usb_hub = *p_dm_odm->hub_usb_mode; } else return; #endif } -u1Byte -halTxbf8814A_GetNtx( - IN PVOID pDM_VOID +u8 +hal_txbf_8814a_get_ntx( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Ntx = 0, txSS = 3; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 ntx = 0, tx_ss = 3; #if DEV_BUS_TYPE == RT_USB_INTERFACE - txSS = *pDM_Odm->HubUsbMode; + tx_ss = *p_dm_odm->hub_usb_mode; #endif - if (txSS == 3 || txSS == 2) { - if (pDM_Odm->RFType == ODM_4T4R) - Ntx = 3; - else if (pDM_Odm->RFType == ODM_3T3R) - Ntx = 2; + if (tx_ss == 3 || tx_ss == 2) { + if (p_dm_odm->rf_type == ODM_4T4R) + ntx = 3; + else if (p_dm_odm->rf_type == ODM_3T3R) + ntx = 2; else - Ntx = 1; - } else if (txSS == 1) /*USB 2.0 always 2Tx*/ - Ntx = 1; + ntx = 1; + } else if (tx_ss == 1) /*USB 2.0 always 2Tx*/ + ntx = 1; else - Ntx = 1; + ntx = 1; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Ntx = %d\n", __func__, Ntx)); - return Ntx; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ntx = %d\n", __func__, ntx)); + return ntx; } -u1Byte -halTxbf8814A_GetNrx( - IN PVOID pDM_VOID +u8 +hal_txbf_8814a_get_nrx( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Nrx = 0; - - if (pDM_Odm->RFType == ODM_4T4R) - Nrx = 3; - else if (pDM_Odm->RFType == ODM_3T3R) - Nrx = 2; - else if (pDM_Odm->RFType == ODM_2T2R) - Nrx = 1; - else if (pDM_Odm->RFType == ODM_2T3R) - Nrx = 2; - else if (pDM_Odm->RFType == ODM_2T4R) - Nrx = 3; - else if (pDM_Odm->RFType == ODM_1T1R) - Nrx = 0; - else if (pDM_Odm->RFType == ODM_1T2R) - Nrx = 1; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 nrx = 0; + + if (p_dm_odm->rf_type == ODM_4T4R) + nrx = 3; + else if (p_dm_odm->rf_type == ODM_3T3R) + nrx = 2; + else if (p_dm_odm->rf_type == ODM_2T2R) + nrx = 1; + else if (p_dm_odm->rf_type == ODM_2T3R) + nrx = 2; + else if (p_dm_odm->rf_type == ODM_2T4R) + nrx = 3; + else if (p_dm_odm->rf_type == ODM_1T1R) + nrx = 0; + else if (p_dm_odm->rf_type == ODM_1T2R) + nrx = 1; else - Nrx = 0; + nrx = 0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Nrx = %d\n", __func__, Nrx)); - return Nrx; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] nrx = %d\n", __func__, nrx)); + return nrx; } -VOID -halTxbf8814A_RfMode( - IN PVOID pDM_VOID, - IN PRT_BEAMFORMING_INFO pBeamformingInfo, - IN u1Byte idx +void +hal_txbf_8814a_rf_mode( + void *p_dm_void, + struct _RT_BEAMFORMING_INFO *p_beamforming_info, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i, Nr_index = 0; - u1Byte txSS = 3; /*default use 3 Tx*/ - RT_BEAMFORMEE_ENTRY BeamformeeEntry; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i, nr_index = 0; + u8 tx_ss = 3; /*default use 3 Tx*/ + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; if (idx < BEAMFORMEE_ENTRY_NUM) - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; + beamformee_entry = p_beamforming_info->beamformee_entry[idx]; else return; - Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), BeamformeeEntry.CompSteeringNumofBFer); + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), beamformee_entry.comp_steering_num_of_bfer); - if (pDM_Odm->RFType == ODM_1T1R) + if (p_dm_odm->rf_type == ODM_1T1R) return; - for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x1); - /*RF Mode table write enable*/ - } - - if (pBeamformingInfo->beamformee_su_cnt > 0) { - for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableAddr, 0xfffff, 0x18000); - /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData0, 0xfffff, 0xBE77F); - /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData1, 0xfffff, 0x226BF); - /*Enable TXIQGEN in RX mode*/ - } - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); - /*Enable TXIQGEN in RX mode*/ - } - - for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x0); - /*RF Mode table write disable*/ - } - - if (pBeamformingInfo->beamformee_su_cnt > 0) { + if (p_beamforming_info->beamformee_su_cnt > 0) { #if DEV_BUS_TYPE == RT_USB_INTERFACE - pDM_Odm->LastUSBHub = *pDM_Odm->HubUsbMode; - txSS = *pDM_Odm->HubUsbMode; + p_beamforming_info->last_usb_hub = *p_dm_odm->hub_usb_mode; + tx_ss = *p_dm_odm->hub_usb_mode; #endif - if (txSS == 3 || txSS == 2) { - if (pDM_Odm->RFType == ODM_4T4R) - txSS = 0xf; - else if (pDM_Odm->RFType == ODM_3T3R) - txSS = 0xe; + if (tx_ss == 3 || tx_ss == 2) { + if (p_dm_odm->rf_type == ODM_4T4R) + tx_ss = 0xf; + else if (p_dm_odm->rf_type == ODM_3T3R) + tx_ss = 0xe; else - txSS = 0x6; - } else if (txSS == 1) /*USB 2.0 always 2Tx*/ - txSS = 0x6; + tx_ss = 0x6; + } else if (tx_ss == 1) /*USB 2.0 always 2Tx*/ + tx_ss = 0x6; else - txSS = 0x6; - - if (txSS == 0xf) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93f); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskDWord, 0x93f93f0); - } else if (txSS == 0xe) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x93e); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e93e0); - } else if (txSS == 0x6) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x936); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskLWord, 0x9360); + tx_ss = 0x6; + + if (tx_ss == 0xf) { + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f); + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0); + } else if (tx_ss == 0xe) { + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e); + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0); + } else if (tx_ss == 0x6) { + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936); + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360); } /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT28 | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ - + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*if Nsts > Nc don't apply V matrix*/ + if (idx == 0) { - switch (Nr_index) { + switch (nr_index) { case 0: - break; + break; case 1: /*Nsts = 2 BC*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ - break; + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + break; case 2: /*Nsts = 3 BCD*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ - break; + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + break; - default: /*Nr>3, same as Case 3*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ - - break; + default: /*nr>3, same as Case 3*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + + break; } } else { - switch (Nr_index) { + switch (nr_index) { case 0: - break; + break; case 1: /*Nsts = 2 BC*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ - break; + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + break; case 2: /*Nsts = 3 BCD*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ - break; + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + break; - default: /*Nr>3, same as Case 3*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8814A, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ - break; + default: /*nr>3, same as Case 3*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + break; } } } - if ((pBeamformingInfo->beamformee_su_cnt == 0) && (pBeamformingInfo->beamformer_su_cnt == 0)) { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8814A, bMaskByte3 | bMaskByte2HighNibble, 0x932); /*set TxPath selection for 8814a BFer bug refine*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8814A, bMaskDWord, 0x93e9360); + if ((p_beamforming_info->beamformee_su_cnt == 0) && (p_beamforming_info->beamformer_su_cnt == 0)) { + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360); } } #if 0 -VOID -halTxbf8814A_DownloadNDPA( - IN PVOID pDM_VOID, - IN u1Byte Idx +void +hal_txbf_8814a_download_ndpa( + void *p_dm_void, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte u1bTmp = 0, tmpReg422 = 0; - u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; - u2Byte Head_Page = 0x7FE; - BOOLEAN bSendBeacon = FALSE; - u2Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; - PADAPTER Adapter = pDM_Odm->Adapter; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 u1b_tmp = 0, tmp_reg422 = 0; + u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; + u16 head_page = 0x7FE; + boolean is_send_beacon = false; + u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + struct _ADAPTER *adapter = p_dm_odm->adapter; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE; + *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true; #endif - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu2Byte)&TxPageBndy); + phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy); /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8814A + 1); - ODM_Write1Byte(pDM_Odm, REG_CR_8814A + 1, (u1bTmp | BIT0)); + u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8814A + 1); + odm_write_1byte(p_dm_odm, REG_CR_8814A + 1, (u1b_tmp | BIT(0))); /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2); - ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422 & (~BIT6)); + tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2); + odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422 & (~BIT(6))); - if (tmpReg422 & BIT6) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: There is an Adapter is sending beacon.\n", __func__)); - bSendBeacon = TRUE; + if (tmp_reg422 & BIT(6)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: There is an adapter is sending beacon.\n", __func__)); + is_send_beacon = true; } /*0x204[11:0] Beacon Head for TXDMA*/ - ODM_Write2Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A, Head_Page); + odm_write_2byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A, head_page); do { /*Clear beacon valid check bit.*/ - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1); - ODM_Write1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1, (BcnValidReg | BIT7)); + bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1); + odm_write_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7))); /*download NDPA rsvd page.*/ - if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) - Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); + if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) + beamforming_send_vht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE); else - Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); + beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); /*check rsvd page download OK.*/ - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 1); + bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1); count = 0; - while (!(BcnValidReg & BIT7) && count < 20) { + while (!(bcn_valid_reg & BIT(7)) && count < 20) { count++; ODM_delay_ms(10); - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A + 2); + bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 2); } - DLBcnCount++; - } while (!(BcnValidReg & BIT7) && DLBcnCount < 5); + dl_bcn_count++; + } while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5); - if (!(BcnValidReg & BIT7)) - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); + if (!(bcn_valid_reg & BIT(7))) + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); /*0x204[11:0] Beacon Head for TXDMA*/ - ODM_Write2Byte(pDM_Odm, REG_FIFOPAGE_CTRL_2_8814A, TxPageBndy); + odm_write_2byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy); /*To make sure that if there exists an adapter which would like to send beacon.*/ /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ /*the beacon cannot be sent by HW.*/ /*2010.06.23. Added by tynli.*/ - if (bSendBeacon) - ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422); + if (is_send_beacon) + odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422); /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8814A + 1); - ODM_Write1Byte(pDM_Odm, REG_CR_8814A + 1, (u1bTmp & (~BIT0))); + u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8814A + 1); + odm_write_1byte(p_dm_odm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0)))); - pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; + p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE; + *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false; #endif } -VOID -halTxbf8814A_FwTxBFCmd( - IN PVOID pDM_VOID +void +hal_txbf_8814a_fw_txbf_cmd( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx, Period = 0; - u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; - u1Byte u1TxBFParm[3] = {0}; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (pBeamInfo->BeamformeeEntry[Idx].bSound) { + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 idx, period = 0; + u8 PageNum0 = 0xFF, PageNum1 = 0xFF; + u8 u1_tx_bf_parm[3] = {0}; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (p_beam_info->beamformee_entry[idx].is_sound) { PageNum0 = 0xFE; PageNum1 = 0x07; - Period = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + period = (u8)(p_beam_info->beamformee_entry[idx].sound_period); } else if (PageNum0 == 0xFF) { PageNum0 = 0xFF; /*stop sounding*/ PageNum1 = 0x0F; @@ -449,120 +488,120 @@ halTxbf8814A_FwTxBFCmd( } } - u1TxBFParm[0] = PageNum0; - u1TxBFParm[1] = PageNum1; - u1TxBFParm[2] = Period; - ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm); + u1_tx_bf_parm[0] = PageNum0; + u1_tx_bf_parm[1] = PageNum1; + u1_tx_bf_parm[2] = period; + odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, - ("[%s] PageNum0 = %d, PageNum1 = %d Period = %d\n", __func__, PageNum0, PageNum1, Period)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, + ("[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__, PageNum0, PageNum1, period)); } #endif -VOID -HalTxbf8814A_Enter( - IN PVOID pDM_VOID, - IN u1Byte BFerBFeeIdx +void +hal_txbf_8814a_enter( + void *p_dm_void, + u8 bfer_bfee_idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; - u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - RT_BEAMFORMER_ENTRY BeamformerEntry; - u2Byte STAid = 0, CSI_Param = 0; - u1Byte Nc_index = 0, Nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFerIdx=%d, BFeeIdx=%d\n", __func__, BFerIdx, BFeeIdx)); - ODM_SetMACReg(pDM_Odm, REG_SND_PTCL_CTRL_8814A, bMaskByte1 | bMaskByte2, 0x0202); - - if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { - BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0; + u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; + u8 bfee_idx = (bfer_bfee_idx & 0xF); + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + u16 sta_id = 0, csi_param = 0; + u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_idx, bfee_idx)); + odm_set_mac_reg(p_dm_odm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202); + + if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { + beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx]; /*Sounding protocol control*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xDB); + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A, 0xDB); /*MAC address/Partial AID of Beamformer*/ - if (BFerIdx == 0) { + if (bfer_idx == 0) { for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), BeamformerEntry.MacAddr[i]); + odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]); } else { for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), BeamformerEntry.MacAddr[i]); + odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]); } /*CSI report parameters of Beamformer*/ - Nc_index = halTxbf8814A_GetNrx(pDM_Odm); /*for 8814A Nrx = 3(4 Ant), min=0(1 Ant)*/ - Nr_index = BeamformerEntry.NumofSoundingDim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/ + nc_index = hal_txbf_8814a_get_nrx(p_dm_odm); /*for 8814A nrx = 3(4 ant), min=0(1 ant)*/ + nr_index = beamformer_entry.num_of_sounding_dim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ grouping = 0; /*for ac = 1, for n = 3*/ - if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) + if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) codebookinfo = 1; - else if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_HT_EXPLICIT) + else if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT) codebookinfo = 3; coefficientsize = 3; - CSI_Param = (u2Byte)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (Nr_index << 3) | (Nc_index)); + csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index)); - if (BFerIdx == 0) - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, CSI_Param); + if (bfer_idx == 0) + odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param); else - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, CSI_Param); + odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param); /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A + 3, 0x40); + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A + 3, 0x40); } - if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { + beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx]; - halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx); + hal_txbf_8814a_rf_mode(p_dm_odm, p_beamforming_info, bfee_idx); - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - STAid = BeamformeeEntry.MacId; + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + sta_id = beamformee_entry.mac_id; else - STAid = BeamformeeEntry.P_AID; + sta_id = beamformee_entry.p_aid; /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ - if (BFeeIdx == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, STAid); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7); + if (bfee_idx == 0) { + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, sta_id); + odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7)); } else - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, STAid | BIT14 | BIT15 | BIT12); + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12)); /*CSI report parameters of Beamformee*/ - if (BFeeIdx == 0) { + if (bfee_idx == 0) { /*Get BIT24 & BIT25*/ - u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3; + u8 tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3; - ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, STAid | BIT9); + odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9)); } else - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, STAid | 0xE200); /*Set BIT25*/ + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/ - phydm_Beamforming_Notify(pDM_Odm); + phydm_beamforming_notify(p_dm_odm); } } -VOID -HalTxbf8814A_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx +void +hal_txbf_8814a_leave( + void *p_dm_void, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMER_ENTRY BeamformerEntry; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - - if (Idx < BEAMFORMER_ENTRY_NUM) { - BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx]; - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx]; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + + if (idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = p_beamforming_info->beamformer_entry[idx]; + beamformee_entry = p_beamforming_info->beamformee_entry[idx]; } else return; @@ -570,80 +609,80 @@ HalTxbf8814A_Leave( /*Clear MAC address of Beamformer*/ /*Clear Associated Bfmee Sel*/ - if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xD8); - if (Idx == 0) { - ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, 0); + if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A, 0xD8); + if (idx == 0) { + odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0); + odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A, 0); } else { - ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0); + odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0); + odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0); } } - if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { - halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, Idx); - if (Idx == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, 0x0); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0); + if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { + hal_txbf_8814a_rf_mode(p_dm_odm, p_beamforming_info, idx); + if (idx == 0) { + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, 0x0); + odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0); } else { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT14 | BIT15 | BIT12); + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12)); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60); } } } -VOID -HalTxbf8814A_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx +void +hal_txbf_8814a_status( + void *p_dm_void, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte BeamCtrlVal, tmpVal; - u4Byte BeamCtrlReg; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformEntry; - - if (Idx < BEAMFORMEE_ENTRY_NUM) - BeamformEntry = pBeamformingInfo->BeamformeeEntry[Idx]; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u16 beam_ctrl_val, tmp_val; + u32 beam_ctrl_reg; + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamform_entry; + + if (idx < BEAMFORMEE_ENTRY_NUM) + beamform_entry = p_beamforming_info->beamformee_entry[idx]; else return; - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - BeamCtrlVal = BeamformEntry.MacId; + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + beam_ctrl_val = beamform_entry.mac_id; else - BeamCtrlVal = BeamformEntry.P_AID; + beam_ctrl_val = beamform_entry.p_aid; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BeamformEntry.BeamformEntryState = %d", __func__, BeamformEntry.BeamformEntryState)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, beamform_entry.beamform_entry_state = %d", __func__, beamform_entry.beamform_entry_state)); - if (Idx == 0) - BeamCtrlReg = REG_TXBF_CTRL_8814A; + if (idx == 0) + beam_ctrl_reg = REG_TXBF_CTRL_8814A; else { - BeamCtrlReg = REG_TXBF_CTRL_8814A + 2; - BeamCtrlVal |= BIT12 | BIT14 | BIT15; + beam_ctrl_reg = REG_TXBF_CTRL_8814A + 2; + beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); } - if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamformingInfo->applyVmatrix == TRUE)) { - if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) - BeamCtrlVal |= BIT9; - else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) - BeamCtrlVal |= (BIT9 | BIT10); - else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80) - BeamCtrlVal |= (BIT9 | BIT10 | BIT11); + if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beamforming_info->apply_v_matrix == true)) { + if (beamform_entry.sound_bw == CHANNEL_WIDTH_20) + beam_ctrl_val |= BIT(9); + else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40) + beam_ctrl_val |= (BIT(9) | BIT(10)); + else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80) + beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11)); } else { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); - BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); + beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); } - ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); + odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val); /*disable NDP packet use beamforming */ - tmpVal = ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8814A); - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, tmpVal | BIT15); + tmp_val = odm_read_2byte(p_dm_odm, REG_TXBF_CTRL_8814A); + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15)); } @@ -651,27 +690,26 @@ HalTxbf8814A_Status( -VOID -HalTxbf8814A_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx +void +hal_txbf_8814a_fw_txbf( + void *p_dm_void, + u8 idx ) { #if 0 - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) - halTxbf8814A_DownloadNDPA(pDM_Odm, Idx); + if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) + hal_txbf_8814a_download_ndpa(p_dm_odm, idx); - halTxbf8814A_FwTxBFCmd(pDM_Odm); + hal_txbf_8814a_fw_txbf_cmd(p_dm_odm); #endif } #endif /* (RTL8814A_SUPPORT == 1)*/ #endif - diff --git a/hal/phydm/txbf/haltxbf8814a.h b/hal/phydm/txbf/haltxbf8814a.h index aac2b93..b070564 100644 --- a/hal/phydm/txbf/haltxbf8814a.h +++ b/hal/phydm/txbf/haltxbf8814a.h @@ -1,70 +1,103 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __HAL_TXBF_8814A_H__ #define __HAL_TXBF_8814A_H__ -#if (BEAMFORMING_SUPPORT == 1) #if (RTL8814A_SUPPORT == 1) -VOID -HalTxbf8814A_setNDPArate( - IN PVOID pDM_VOID, - IN u1Byte BW, - IN u1Byte Rate +#if (BEAMFORMING_SUPPORT == 1) + +boolean +phydm_beamforming_set_iqgen_8814A( + void *p_dm_void ); -u1Byte -halTxbf8814A_GetNtx( - IN PVOID pDM_VOID - ); +void +hal_txbf_8814a_set_ndpa_rate( + void *p_dm_void, + u8 BW, + u8 rate +); -VOID -HalTxbf8814A_Enter( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +u8 +hal_txbf_8814a_get_ntx( + void *p_dm_void +); +void +hal_txbf_8814a_enter( + void *p_dm_void, + u8 idx +); -VOID -HalTxbf8814A_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_8814a_leave( + void *p_dm_void, + u8 idx +); -VOID -HalTxbf8814A_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); -VOID -HalTxbf8814A_ResetTxPath( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_8814a_status( + void *p_dm_void, + u8 idx +); +void +hal_txbf_8814a_reset_tx_path( + void *p_dm_void, + u8 idx +); -VOID -HalTxbf8814A_GetTxRate( - IN PVOID pDM_VOID - ); -VOID -HalTxbf8814A_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_8814a_get_tx_rate( + void *p_dm_void +); + +void +hal_txbf_8814a_fw_txbf( + void *p_dm_void, + u8 idx +); + #else -#define HalTxbf8814A_setNDPArate(pDM_VOID, BW, Rate) -#define halTxbf8814A_GetNtx(pDM_VOID) 0 -#define HalTxbf8814A_Enter(pDM_VOID, Idx) -#define HalTxbf8814A_Leave(pDM_VOID, Idx) -#define HalTxbf8814A_Status(pDM_VOID, Idx) -#define HalTxbf8814A_ResetTxPath(pDM_VOID, Idx) -#define HalTxbf8814A_GetTxRate(pDM_VOID) -#define HalTxbf8814A_FwTxBF(pDM_VOID, Idx) -#endif +#define hal_txbf_8814a_set_ndpa_rate(p_dm_void, BW, rate) +#define hal_txbf_8814a_get_ntx(p_dm_void) 0 +#define hal_txbf_8814a_enter(p_dm_void, idx) +#define hal_txbf_8814a_leave(p_dm_void, idx) +#define hal_txbf_8814a_status(p_dm_void, idx) +#define hal_txbf_8814a_reset_tx_path(p_dm_void, idx) +#define hal_txbf_8814a_get_tx_rate(p_dm_void) +#define hal_txbf_8814a_fw_txbf(p_dm_void, idx) +#define phydm_beamforming_set_iqgen_8814A(p_dm_void) 0 #endif +#else + +#define hal_txbf_8814a_set_ndpa_rate(p_dm_void, BW, rate) +#define hal_txbf_8814a_get_ntx(p_dm_void) 0 +#define hal_txbf_8814a_enter(p_dm_void, idx) +#define hal_txbf_8814a_leave(p_dm_void, idx) +#define hal_txbf_8814a_status(p_dm_void, idx) +#define hal_txbf_8814a_reset_tx_path(p_dm_void, idx) +#define hal_txbf_8814a_get_tx_rate(p_dm_void) +#define hal_txbf_8814a_fw_txbf(p_dm_void, idx) +#define phydm_beamforming_set_iqgen_8814A(p_dm_void) 0 #endif +#endif diff --git a/hal/phydm/txbf/haltxbf8822b.c b/hal/phydm/txbf/haltxbf8822b.c index 03c4451..56ad3e7 100644 --- a/hal/phydm/txbf/haltxbf8822b.c +++ b/hal/phydm/txbf/haltxbf8822b.c @@ -1,254 +1,270 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ /*============================================================*/ -/* Description: */ -/* */ -/* This file is for 8814A TXBF mechanism */ -/* */ +/* Description: */ +/* */ +/* This file is for 8814A TXBF mechanism */ +/* */ /*============================================================*/ #include "mp_precomp.h" +#include "phydm_precomp.h" -#if (BEAMFORMING_SUPPORT == 1) #if (RTL8822B_SUPPORT == 1) +#if (BEAMFORMING_SUPPORT == 1) -u1Byte -halTxbf8822B_GetNtx( - IN PVOID pDM_VOID - ) +u8 +hal_txbf_8822b_get_ntx( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Ntx = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 ntx = 0; #if DEV_BUS_TYPE == RT_USB_INTERFACE - if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { - if (*pDM_Odm->HubUsbMode == 2) {/*USB3.0*/ - if (pDM_Odm->RFType == ODM_4T4R) - Ntx = 3; - else if (pDM_Odm->RFType == ODM_3T3R) - Ntx = 2; + if (p_dm_odm->support_interface == ODM_ITRF_USB) { + if (*p_dm_odm->hub_usb_mode == 2) {/*USB3.0*/ + if (p_dm_odm->rf_type == ODM_4T4R) + ntx = 3; + else if (p_dm_odm->rf_type == ODM_3T3R) + ntx = 2; else - Ntx = 1; - } else if (*pDM_Odm->HubUsbMode == 1) /*USB 2.0 always 2Tx*/ - Ntx = 1; + ntx = 1; + } else if (*p_dm_odm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/ + ntx = 1; else - Ntx = 1; + ntx = 1; } else #endif { - if (pDM_Odm->RFType == ODM_4T4R) - Ntx = 3; - else if (pDM_Odm->RFType == ODM_3T3R) - Ntx = 2; + if (p_dm_odm->rf_type == ODM_4T4R) + ntx = 3; + else if (p_dm_odm->rf_type == ODM_3T3R) + ntx = 2; else - Ntx = 1; + ntx = 1; } - return Ntx; + return ntx; } -u1Byte -halTxbf8822B_GetNrx( - IN PVOID pDM_VOID - ) +u8 +hal_txbf_8822b_get_nrx( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Nrx = 0; - - if (pDM_Odm->RFType == ODM_4T4R) - Nrx = 3; - else if (pDM_Odm->RFType == ODM_3T3R) - Nrx = 2; - else if (pDM_Odm->RFType == ODM_2T2R) - Nrx = 1; - else if (pDM_Odm->RFType == ODM_2T3R) - Nrx = 2; - else if (pDM_Odm->RFType == ODM_2T4R) - Nrx = 3; - else if (pDM_Odm->RFType == ODM_1T1R) - Nrx = 0; - else if (pDM_Odm->RFType == ODM_1T2R) - Nrx = 1; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 nrx = 0; + + if (p_dm_odm->rf_type == ODM_4T4R) + nrx = 3; + else if (p_dm_odm->rf_type == ODM_3T3R) + nrx = 2; + else if (p_dm_odm->rf_type == ODM_2T2R) + nrx = 1; + else if (p_dm_odm->rf_type == ODM_2T3R) + nrx = 2; + else if (p_dm_odm->rf_type == ODM_2T4R) + nrx = 3; + else if (p_dm_odm->rf_type == ODM_1T1R) + nrx = 0; + else if (p_dm_odm->rf_type == ODM_1T2R) + nrx = 1; else - Nrx = 0; + nrx = 0; + + return nrx; - return Nrx; - } /***************SU & MU BFee Entry********************/ -VOID -halTxbf8822B_RfMode( - IN PVOID pDM_VOID, - IN PRT_BEAMFORMING_INFO pBeamformingInfo, - IN u1Byte idx - ) +void +hal_txbf_8822b_rf_mode( + void *p_dm_void, + struct _RT_BEAMFORMING_INFO *p_beamforming_info, + u8 idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i, Nr_index = 0; - BOOLEAN bSelfBeamformer = FALSE; - BOOLEAN bSelfBeamformee = FALSE; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; +#if 0 + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i, nr_index = 0; + boolean is_self_beamformer = false; + boolean is_self_beamformee = false; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; if (idx < BEAMFORMEE_ENTRY_NUM) - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; + beamformee_entry = p_beamforming_info->beamformee_entry[idx]; else return; - if (pDM_Odm->RFType == ODM_1T1R) + if (p_dm_odm->rf_type == ODM_1T1R) return; for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x1); - /*RF Mode table write enable*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_welut_jaguar, 0x80000, 0x1); + /*RF mode table write enable*/ } - if ((pBeamformingInfo->beamformee_su_cnt > 0) || (pBeamformingInfo->beamformee_mu_cnt > 0)) { + if ((p_beamforming_info->beamformee_su_cnt > 0) || (p_beamforming_info->beamformee_mu_cnt > 0)) { for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableAddr, 0xfffff, 0x18000); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_mode_table_addr, 0xfffff, 0x18000); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData0, 0xfffff, 0xBE77F); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_mode_table_data0, 0xfffff, 0xBE77F); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_ModeTableData1, 0xfffff, 0x226BF); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_mode_table_data1, 0xfffff, 0x226BF); /*Enable TXIQGEN in RX mode*/ } - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, rf_mode_table_data1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ } for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { - ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)i, RF_WeLut_Jaguar, 0x80000, 0x0); - /*RF Mode table write disable*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_welut_jaguar, 0x80000, 0x0); + /*RF mode table write disable*/ } - if (pBeamformingInfo->beamformee_su_cnt > 0) { + if (p_beamforming_info->beamformee_su_cnt > 0) { /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT28|BIT29, 0x2); /*enable BB TxBF ant mapping register*/ - + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ + if (idx == 0) { /*Nsts = 2 AB*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); - /*ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x430);*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433); + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + /*odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430);*/ } else {/*IDX =1*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); - /*ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x430;*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + /*odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430;*/ } } else { - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8822B, bMaskLWord, 0x430); /*2SS by path-A,B*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*2SS by path-A,B*/ } - - if (pBeamformingInfo->beamformee_mu_cnt > 0) { + + if (p_beamforming_info->beamformee_mu_cnt > 0) { /*MU STAs share the common setting*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT31, 1); - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); } - +#endif } #if 0 -VOID -halTxbf8822B_DownloadNDPA( - IN PADAPTER Adapter, - IN u1Byte Idx - ) +void +hal_txbf_8822b_download_ndpa( + struct _ADAPTER *adapter, + u8 idx +) { - u1Byte u1bTmp = 0, tmpReg422 = 0; - u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; - u2Byte Head_Page = 0x7FE; - BOOLEAN bSendBeacon = FALSE; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u2Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ - PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry+Idx; - - pHalData->bFwDwRsvdPageInProgress = TRUE; - Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu2Byte)&TxPageBndy); - + u8 u1b_tmp = 0, tmp_reg422 = 0; + u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; + u16 head_page = 0x7FE; + boolean is_send_beacon = false; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ + struct _RT_BEAMFORMING_INFO *p_beam_info = GET_BEAMFORM_INFO(adapter); + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + + p_hal_data->is_fw_dw_rsvd_page_in_progress = true; + phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy); + /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8814A+1); - PlatformEFIOWrite1Byte(Adapter, REG_CR_8814A+1, (u1bTmp|BIT0)); + u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1); + platform_efio_write_1byte(adapter, REG_CR_8814A + 1, (u1b_tmp | BIT(0))); /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmpReg422 = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2); - PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2, tmpReg422&(~BIT6)); + tmp_reg422 = platform_efio_read_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2); + platform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422 & (~BIT(6))); - if (tmpReg422 & BIT6) { - RT_TRACE(COMP_INIT, DBG_LOUD, ("SetBeamformDownloadNDPA_8814A(): There is an Adapter is sending beacon.\n")); - bSendBeacon = TRUE; + if (tmp_reg422 & BIT(6)) { + RT_TRACE(COMP_INIT, DBG_LOUD, ("SetBeamformDownloadNDPA_8814A(): There is an adapter is sending beacon.\n")); + is_send_beacon = true; } /*0x204[11:0] Beacon Head for TXDMA*/ - PlatformEFIOWrite2Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A, Head_Page); - - do { + platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, head_page); + + do { /*Clear beacon valid check bit.*/ - BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+1); - PlatformEFIOWrite1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+1, (BcnValidReg|BIT7)); - + bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); + platform_efio_write_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7))); + /*download NDPA rsvd page.*/ - if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) - Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); - else - Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); - + if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) + beamforming_send_vht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE); + else + beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + /*check rsvd page download OK.*/ - BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); + bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); count = 0; - while (!(BcnValidReg & BIT7) && count < 20) { + while (!(bcn_valid_reg & BIT(7)) && count < 20) { count++; delay_us(10); - BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+2); + bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 2); } - DLBcnCount++; - } while (!(BcnValidReg & BIT7) && DLBcnCount < 5); - - if (!(BcnValidReg & BIT0)) + dl_bcn_count++; + } while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5); + + if (!(bcn_valid_reg & BIT(0))) RT_DISP(FBEAM, FBEAM_ERROR, ("%s Download RSVD page failed!\n", __func__)); /*0x204[11:0] Beacon Head for TXDMA*/ - PlatformEFIOWrite2Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A, TxPageBndy); + platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy); /*To make sure that if there exists an adapter which would like to send beacon.*/ /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ /*the beacon cannot be sent by HW.*/ /*2010.06.23. Added by tynli.*/ - if (bSendBeacon) - PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2, tmpReg422); + if (is_send_beacon) + platform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422); /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8814A+1); - PlatformEFIOWrite1Byte(Adapter, REG_CR_8814A+1, (u1bTmp&(~BIT0))); + u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1); + platform_efio_write_1byte(adapter, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0)))); - pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; + p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; - pHalData->bFwDwRsvdPageInProgress = FALSE; + p_hal_data->is_fw_dw_rsvd_page_in_progress = false; } -VOID -halTxbf8822B_FwTxBFCmd( - IN PADAPTER Adapter - ) +void +hal_txbf_8822b_fw_txbf_cmd( + struct _ADAPTER *adapter +) { - u1Byte Idx, Period = 0; - u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; - u1Byte u1TxBFParm[3] = {0}; + u8 idx, period = 0; + u8 PageNum0 = 0xFF, PageNum1 = 0xFF; + u8 u1_tx_bf_parm[3] = {0}; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); + PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); + struct _RT_BEAMFORMING_INFO *p_beam_info = GET_BEAMFORM_INFO(adapter); - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { - if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (pBeamInfo->BeamformeeEntry[Idx].bSound) { + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (p_beam_info->beamformee_entry[idx].is_sound) { PageNum0 = 0xFE; PageNum1 = 0x07; - Period = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + period = (u8)(p_beam_info->beamformee_entry[idx].sound_period); } else if (PageNum0 == 0xFF) { PageNum0 = 0xFF; /*stop sounding*/ PageNum1 = 0x0F; @@ -256,245 +272,246 @@ halTxbf8822B_FwTxBFCmd( } } - u1TxBFParm[0] = PageNum0; - u1TxBFParm[1] = PageNum1; - u1TxBFParm[2] = Period; - FillH2CCmd(Adapter, PHYDM_H2C_TXBF, 3, u1TxBFParm); - - RT_DISP(FBEAM, FBEAM_FUN, ("@%s End, PageNum0 = 0x%x, PageNum1 = 0x%x Period = %d", __func__, PageNum0, PageNum1, Period)); + u1_tx_bf_parm[0] = PageNum0; + u1_tx_bf_parm[1] = PageNum1; + u1_tx_bf_parm[2] = period; + fill_h2c_cmd(adapter, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); + + RT_DISP(FBEAM, FBEAM_FUN, ("@%s End, PageNum0 = 0x%x, PageNum1 = 0x%x period = %d", __func__, PageNum0, PageNum1, period)); } #endif -VOID -HalTxbf8822B_Init( - IN PVOID pDM_VOID - ) +#if 0 +void +hal_txbf_8822b_init( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte u1bTmp; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT16, 1); /*Enable P1 aggr new packet according to P0 transfer time*/ - ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT15|BIT14|BIT13|BIT12, 10); /*MU Retry Limit*/ - ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT7, 0); /*Disable Tx MU-MIMO until sounding done*/ - ODM_SetBBReg(pDM_Odm, 0x14c0 , 0x3F, 0); /* Clear validity of MU STAs */ - ODM_Write1Byte(pDM_Odm, 0x167c , 0x70); /*MU-MIMO Option as default value*/ - ODM_Write2Byte(pDM_Odm, 0x1680 , 0); /*MU-MIMO Control as default value*/ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 u1b_tmp; + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _ADAPTER *adapter = p_dm_odm->adapter; + + odm_set_bb_reg(p_dm_odm, 0x14c0, BIT(16), 1); /*Enable P1 aggr new packet according to P0 transfer time*/ + odm_set_bb_reg(p_dm_odm, 0x14c0, BIT(15) | BIT14 | BIT13 | BIT12, 10); /*MU Retry Limit*/ + odm_set_bb_reg(p_dm_odm, 0x14c0, BIT(7), 0); /*Disable Tx MU-MIMO until sounding done*/ + odm_set_bb_reg(p_dm_odm, 0x14c0, 0x3F, 0); /* Clear validity of MU STAs */ + odm_write_1byte(p_dm_odm, 0x167c, 0x70); /*MU-MIMO Option as default value*/ + odm_write_2byte(p_dm_odm, 0x1680, 0); /*MU-MIMO Control as default value*/ /* Set MU NDPA rate & BW source */ /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ - u1bTmp = ODM_Read1Byte(pDM_Odm, 0x42C); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B, (u1bTmp|BIT6)); - /* 0x45F[7:0] = 0x10 (Rate=OFDM_6M, BW20) */ - ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B, 0x10); + u1b_tmp = odm_read_1byte(p_dm_odm, 0x42C); + odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8822B, (u1b_tmp | BIT(6))); + /* 0x45F[7:0] = 0x10 (rate=OFDM_6M, BW20) */ + odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8822B, 0x10); /*Temp Settings*/ - ODM_SetBBReg(pDM_Odm, 0x6DC , 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/ - ODM_SetBBReg(pDM_Odm, 0x1C94 , bMaskDWord, 0xAFFFAFFF); /*Grouping bitmap parameters*/ + odm_set_bb_reg(p_dm_odm, 0x6DC, 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/ + odm_set_bb_reg(p_dm_odm, 0x1C94, MASKDWORD, 0xAFFFAFFF); /*Grouping bitmap parameters*/ /* Init HW variable */ - pBeamformingInfo->RegMUTxCtrl = ODM_Read4Byte(pDM_Odm, 0x14c0); + p_beamforming_info->reg_mu_tx_ctrl = odm_read_4byte(p_dm_odm, 0x14c0); - if (pDM_Odm->RFType == ODM_2T2R) { /*2T2R*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: RFType is 2T2R\n", __func__)); - config_phydm_trx_mode_8822b(pDM_Odm, (ODM_RF_PATH_E)3, (ODM_RF_PATH_E)3, TRUE);/*Tx2path*/ + if (p_dm_odm->rf_type == ODM_2T2R) { /*2T2R*/ + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: rf_type is 2T2R\n", __func__)); + config_phydm_trx_mode_8822b(p_dm_odm, (enum odm_rf_path_e)3, (enum odm_rf_path_e)3, true);/*Tx2path*/ } #if (OMNIPEEK_SNIFFER_ENABLED == 1) /* Config HW to receive packet on the user position from registry for sniffer mode. */ - /* ODM_SetBBReg(pDM_Odm, 0xB00 , BIT9, 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */ - ODM_SetBBReg(pDM_Odm, 0xB54 , BIT30, 1); /* RegB54[30] = 1 (force user position) */ - ODM_SetBBReg(pDM_Odm, 0xB54 , (BIT29|BIT28), Adapter->MgntInfo.SniffUserPosition); /* RegB54[29:28] = user position (0~3) */ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Set Adapter->MgntInfo.SniffUserPosition=%#X\n", Adapter->MgntInfo.SniffUserPosition)); + /* odm_set_bb_reg(p_dm_odm, 0xB00, BIT(9), 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */ + odm_set_bb_reg(p_dm_odm, 0xB54, BIT(30), 1); /* RegB54[30] = 1 (force user position) */ + odm_set_bb_reg(p_dm_odm, 0xB54, (BIT(29) | BIT28), adapter->MgntInfo.sniff_user_position); /* RegB54[29:28] = user position (0~3) */ + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Set adapter->MgntInfo.sniff_user_position=%#X\n", adapter->MgntInfo.sniff_user_position)); #endif } +#endif -VOID -HalTxbf8822B_Enter( - IN PVOID pDM_VOID, - IN u1Byte BFerBFeeIdx - ) +void +hal_txbf_8822b_enter( + void *p_dm_void, + u8 bfer_bfee_idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - u1Byte BFerIdx = (BFerBFeeIdx & 0xF0)>>4; - u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); - u2Byte CSI_Param = 0; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamformeeEntry; - PRT_BEAMFORMER_ENTRY pBeamformerEntry; - u2Byte value16, STAid = 0; - u1Byte Nc_index = 0, Nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; - u4Byte gid_valid, user_position_l, user_position_h; - u4Byte mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; - u1Byte u1bTmp; - u4Byte u4bTmp; - - RT_DISP(FBEAM, FBEAM_FUN, ("%s: BFerBFeeIdx=%d, BFerIdx=%d, BFeeIdx=%d\n", __func__, BFerBFeeIdx, BFerIdx, BFeeIdx)); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0; + u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; + u8 bfee_idx = (bfer_bfee_idx & 0xF); + u16 csi_param = 0; + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry; + struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry; + u16 value16, sta_id = 0; + u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; + u32 gid_valid, user_position_l, user_position_h; + u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; + u8 u1b_tmp; + u32 u4b_tmp; + + RT_DISP(FBEAM, FBEAM_FUN, ("%s: bfer_bfee_idx=%d, bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_bfee_idx, bfer_idx, bfee_idx)); /*************SU BFer Entry Init*************/ - if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { - pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[BFerIdx]; - pBeamformerEntry->is_mu_ap = FALSE; + if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { + p_beamformer_entry = &p_beamforming_info->beamformer_entry[bfer_idx]; + p_beamformer_entry->is_mu_ap = false; /*Sounding protocol control*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); - - + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + + for (i = 0; i < MAX_BEAMFORMER_SU; i++) { - if ((pBeamformingInfo->beamformer_su_reg_maping & BIT(i)) == 0) { - pBeamformingInfo->beamformer_su_reg_maping |= BIT(i); - pBeamformerEntry->su_reg_index = i; + if ((p_beamforming_info->beamformer_su_reg_maping & BIT(i)) == 0) { + p_beamforming_info->beamformer_su_reg_maping |= BIT(i); + p_beamformer_entry->su_reg_index = i; break; } } - + /*MAC address/Partial AID of Beamformer*/ - if (pBeamformerEntry->su_reg_index == 0) { + if (p_beamformer_entry->su_reg_index == 0) { for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+i), pBeamformerEntry->MacAddr[i]); + odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), p_beamformer_entry->mac_addr[i]); } else { for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8822B+i), pBeamformerEntry->MacAddr[i]); + odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8822B + i), p_beamformer_entry->mac_addr[i]); } /*CSI report parameters of Beamformer*/ - Nc_index = halTxbf8822B_GetNrx(pDM_Odm); /*for 8814A Nrx = 3(4 Ant), min=0(1 Ant)*/ - Nr_index = pBeamformerEntry->NumofSoundingDim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/ - + nc_index = hal_txbf_8822b_get_nrx(p_dm_odm); /*for 8814A nrx = 3(4 ant), min=0(1 ant)*/ + nr_index = p_beamformer_entry->num_of_sounding_dim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ + grouping = 0; /*for ac = 1, for n = 3*/ - if (pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) - codebookinfo = 1; - else if (pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_HT_EXPLICIT) - codebookinfo = 3; + if (p_beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) + codebookinfo = 1; + else if (p_beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT) + codebookinfo = 3; coefficientsize = 3; - CSI_Param = (u2Byte)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(Nr_index<<3)|(Nc_index)); + csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index)); - if (BFerIdx == 0) - ODM_Write2Byte(pDM_Odm, REG_TX_CSI_RPT_PARAM_BW20_8822B, CSI_Param); + if (bfer_idx == 0) + odm_write_2byte(p_dm_odm, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param); else - ODM_Write2Byte(pDM_Odm, REG_TX_CSI_RPT_PARAM_BW20_8822B+2, CSI_Param); + odm_write_2byte(p_dm_odm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, csi_param); /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B+3, 0x70); - + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B + 3, 0x70); + } /*************SU BFee Entry Init*************/ - if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { - pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[BFeeIdx]; - pBeamformeeEntry->is_mu_sta = FALSE; - halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx); - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - STAid = pBeamformeeEntry->MacId; - else - STAid = pBeamformeeEntry->P_AID; + if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { + p_beamformee_entry = &p_beamforming_info->beamformee_entry[bfee_idx]; + p_beamformee_entry->is_mu_sta = false; + hal_txbf_8822b_rf_mode(p_dm_odm, p_beamforming_info, bfee_idx); + + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + sta_id = p_beamformee_entry->mac_id; + else + sta_id = p_beamformee_entry->p_aid; for (i = 0; i < MAX_BEAMFORMEE_SU; i++) { - if ((pBeamformingInfo->beamformee_su_reg_maping & BIT(i)) == 0) { - pBeamformingInfo->beamformee_su_reg_maping |= BIT(i); - pBeamformeeEntry->su_reg_index = i; + if ((p_beamforming_info->beamformee_su_reg_maping & BIT(i)) == 0) { + p_beamforming_info->beamformee_su_reg_maping |= BIT(i); + p_beamformee_entry->su_reg_index = i; break; } } - + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ - if (pBeamformeeEntry->su_reg_index == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, STAid); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3)|BIT4|BIT6|BIT7); - } else { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B+2, STAid | BIT14 | BIT15 | BIT12); - } + if (p_beamformee_entry->su_reg_index == 0) { + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B, sta_id); + odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7)); + } else + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B + 2, sta_id | BIT(14) | BIT(15) | BIT(12)); /*CSI report parameters of Beamformee*/ - if (pBeamformeeEntry->su_reg_index == 0) { + if (p_beamformee_entry->su_reg_index == 0) { /*Get BIT24 & BIT25*/ - u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+3) & 0x3; - - ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B, STAid | BIT9); - } else - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2, STAid | 0xE200); /*Set BIT25*/ - - phydm_Beamforming_Notify(pDM_Odm); + u8 tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3) & 0x3; + + odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B, sta_id | BIT(9)); + } else + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, sta_id | 0xE200); /*Set BIT25*/ + + phydm_beamforming_notify(p_dm_odm); } /*************MU BFer Entry Init*************/ - if ((pBeamformingInfo->beamformer_mu_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { - pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[BFerIdx]; - pBeamformingInfo->mu_ap_index = BFerIdx; - pBeamformerEntry->is_mu_ap = TRUE; + if ((p_beamforming_info->beamformer_mu_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { + p_beamformer_entry = &p_beamforming_info->beamformer_entry[bfer_idx]; + p_beamforming_info->mu_ap_index = bfer_idx; + p_beamformer_entry->is_mu_ap = true; for (i = 0; i < 8; i++) - pBeamformerEntry->gid_valid[i] = 0; + p_beamformer_entry->gid_valid[i] = 0; for (i = 0; i < 16; i++) - pBeamformerEntry->user_position[i] = 0; - + p_beamformer_entry->user_position[i] = 0; + /*Sounding protocol control*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, 0xDB); /* MAC address */ for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+i), pBeamformerEntry->MacAddr[i]); + odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), p_beamformer_entry->mac_addr[i]); /* Set partial AID */ - ODM_Write2Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+6), pBeamformerEntry->P_AID); + odm_write_2byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8822B + 6), p_beamformer_entry->p_aid); /* Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, 0x1680); - u1bTmp = (pBeamformerEntry->AID)&0xFFF; - ODM_Write1Byte(pDM_Odm, 0x1680, u1bTmp); + u1b_tmp = odm_read_1byte(p_dm_odm, 0x1680); + u1b_tmp = (p_beamformer_entry->p_aid) & 0xFFF; + odm_write_1byte(p_dm_odm, 0x1680, u1b_tmp); /* Set 80us for leaving ndp_rx_standby_state */ - ODM_Write1Byte(pDM_Odm, 0x71B, 0x50); - + odm_write_1byte(p_dm_odm, 0x71B, 0x50); + /* Set 0x6A0[14] = 1 to accept action_no_ack */ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1); - u1bTmp |= 0x40; - ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1, u1bTmp); + u1b_tmp = odm_read_1byte(p_dm_odm, REG_RXFLTMAP0_8822B + 1); + u1b_tmp |= 0x40; + odm_write_1byte(p_dm_odm, REG_RXFLTMAP0_8822B + 1, u1b_tmp); /* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP1_8822B); - u1bTmp |= 0x30; - ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP1_8822B, u1bTmp); - + u1b_tmp = odm_read_1byte(p_dm_odm, REG_RXFLTMAP1_8822B); + u1b_tmp |= 0x30; + odm_write_1byte(p_dm_odm, REG_RXFLTMAP1_8822B, u1b_tmp); + /*CSI report parameters of Beamformer*/ - Nc_index = halTxbf8822B_GetNrx(pDM_Odm); /* Depend on RF type */ - Nr_index = 1; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/ + nc_index = hal_txbf_8822b_get_nrx(p_dm_odm); /* Depend on RF type */ + nr_index = 1; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ grouping = 0; /*no grouping*/ codebookinfo = 1; /*7 bit for psi, 9 bit for phi*/ - coefficientsize = 0; /*This is nothing really matter*/ - CSI_Param = (u2Byte)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(Nr_index<<3)|(Nc_index)); - ODM_Write2Byte(pDM_Odm, 0x6F4, CSI_Param); + coefficientsize = 0; /*This is nothing really matter*/ + csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index)); + odm_write_2byte(p_dm_odm, 0x6F4, csi_param); - /*for B-Cut*/ - ODM_SetBBReg(pDM_Odm, 0x6A0 , BIT20, 0); - ODM_SetBBReg(pDM_Odm, 0x688 , BIT20, 0); + /*for B-cut*/ + odm_set_bb_reg(p_dm_odm, 0x6A0, BIT(20), 0); + odm_set_bb_reg(p_dm_odm, 0x688, BIT(20), 0); } - + /*************MU BFee Entry Init*************/ - if ((pBeamformingInfo->beamformee_mu_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { - pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[BFeeIdx]; - pBeamformeeEntry->is_mu_sta = TRUE; + if ((p_beamforming_info->beamformee_mu_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { + p_beamformee_entry = &p_beamforming_info->beamformee_entry[bfee_idx]; + p_beamformee_entry->is_mu_sta = true; for (i = 0; i < MAX_BEAMFORMEE_MU; i++) { - if ((pBeamformingInfo->beamformee_mu_reg_maping & BIT(i)) == 0) { - pBeamformingInfo->beamformee_mu_reg_maping |= BIT(i); - pBeamformeeEntry->mu_reg_index = i; + if ((p_beamforming_info->beamformee_mu_reg_maping & BIT(i)) == 0) { + p_beamforming_info->beamformee_mu_reg_maping |= BIT(i); + p_beamformee_entry->mu_reg_index = i; break; } } - if (pBeamformeeEntry->mu_reg_index == 0xFF) { + if (p_beamformee_entry->mu_reg_index == 0xFF) { /* There is no valid bit in beamformee_mu_reg_maping */ RT_DISP(FBEAM, FBEAM_FUN, ("%s: ERROR! There is no valid bit in beamformee_mu_reg_maping!\n", __func__)); return; } - + /*User position table*/ - switch (pBeamformeeEntry->mu_reg_index) { + switch (p_beamformee_entry->mu_reg_index) { case 0: gid_valid = 0x7fe; user_position_l = 0x111110; @@ -529,90 +546,90 @@ HalTxbf8822B_Enter( for (i = 0; i < 8; i++) { if (i < 4) { - pBeamformeeEntry->gid_valid[i] = (u1Byte)(gid_valid & 0xFF); + p_beamformee_entry->gid_valid[i] = (u8)(gid_valid & 0xFF); gid_valid = (gid_valid >> 8); } else - pBeamformeeEntry->gid_valid[i] = 0; + p_beamformee_entry->gid_valid[i] = 0; } for (i = 0; i < 16; i++) { if (i < 4) - pBeamformeeEntry->user_position[i] = (u1Byte)((user_position_l >>(i*8)) & 0xFF); + p_beamformee_entry->user_position[i] = (u8)((user_position_l >> (i * 8)) & 0xFF); else if (i < 8) - pBeamformeeEntry->user_position[i] = (u1Byte)((user_position_h >>((i-4)*8)) & 0xFF); + p_beamformee_entry->user_position[i] = (u8)((user_position_h >> ((i - 4) * 8)) & 0xFF); else - pBeamformeeEntry->user_position[i] = 0; + p_beamformee_entry->user_position[i] = 0; } /*Sounding protocol control*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, 0xDB); /*select MU STA table*/ - pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); - pBeamformingInfo->RegMUTxCtrl |= (pBeamformeeEntry->mu_reg_index << 8)&(BIT8|BIT9|BIT10); - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - - ODM_SetBBReg(pDM_Odm, 0x14c4 , bMaskDWord, 0); /*Reset gid_valid table*/ - ODM_SetBBReg(pDM_Odm, 0x14c8 , bMaskDWord, user_position_l); - ODM_SetBBReg(pDM_Odm, 0x14cc , bMaskDWord, user_position_h); + p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + p_beamforming_info->reg_mu_tx_ctrl |= (p_beamformee_entry->mu_reg_index << 8) & (BIT(8) | BIT(9) | BIT(10)); + odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + + odm_set_bb_reg(p_dm_odm, 0x14c4, MASKDWORD, 0); /*Reset gid_valid table*/ + odm_set_bb_reg(p_dm_odm, 0x14c8, MASKDWORD, user_position_l); + odm_set_bb_reg(p_dm_odm, 0x14cc, MASKDWORD, user_position_h); - /*set validity of MU STAs*/ - pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0; - pBeamformingInfo->RegMUTxCtrl |= pBeamformingInfo->beamformee_mu_reg_maping&0x3F; - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + /*set validity of MU STAs*/ + p_beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; + p_beamforming_info->reg_mu_tx_ctrl |= p_beamforming_info->beamformee_mu_reg_maping & 0x3F; + odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, RegMUTxCtrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", - __func__, pBeamformingInfo->RegMUTxCtrl, user_position_l, user_position_h)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, reg_mu_tx_ctrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, p_beamforming_info->reg_mu_tx_ctrl, user_position_l, user_position_h)); - value16 = ODM_Read2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index]); + value16 = odm_read_2byte(p_dm_odm, mu_reg[p_beamformee_entry->mu_reg_index]); value16 &= 0xFE00; /*Clear PAID*/ - value16 |= BIT9; /*Enable MU BFee*/ - value16 |= pBeamformeeEntry->P_AID; - ODM_Write2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index] , value16); - + value16 |= BIT(9); /*Enable MU BFee*/ + value16 |= p_beamformee_entry->p_aid; + odm_write_2byte(p_dm_odm, mu_reg[p_beamformee_entry->mu_reg_index], value16); + /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3); - u1bTmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/ - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, u1bTmp); + u1b_tmp = odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3); + u1b_tmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/ + odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3, u1b_tmp); /* Set NDPA to 6M*/ - ODM_Write1Byte(pDM_Odm, REG_NDPA_RATE_8822B, 0x4); + odm_write_1byte(p_dm_odm, REG_NDPA_RATE_8822B, 0x4); - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B); - u1bTmp &= 0xFC; /* Clear bit 0, 1*/ - ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B, u1bTmp); + u1b_tmp = odm_read_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8822B); + u1b_tmp &= 0xFC; /* Clear bit 0, 1*/ + odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8822B, u1b_tmp); - u4bTmp = ODM_Read4Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B); - u4bTmp = ((u4bTmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202*/ - ODM_Write4Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, u4bTmp); + u4b_tmp = odm_read_4byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B); + u4b_tmp = ((u4b_tmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202*/ + odm_write_4byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, u4b_tmp); /* Set 0x6A0[14] = 1 to accept action_no_ack */ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1); - u1bTmp |= 0x40; - ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1, u1bTmp); + u1b_tmp = odm_read_1byte(p_dm_odm, REG_RXFLTMAP0_8822B + 1); + u1b_tmp |= 0x40; + odm_write_1byte(p_dm_odm, REG_RXFLTMAP0_8822B + 1, u1b_tmp); /* End of MAC registers setting */ - - halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx); + + hal_txbf_8822b_rf_mode(p_dm_odm, p_beamforming_info, bfee_idx); #if (SUPPORT_MU_BF == 1) /*Special for plugfest*/ delay_ms(50); /* wait for 4-way handshake ending*/ - SendSWVHTGIDMgntFrame(pDM_Odm, pBeamformeeEntry->MacAddr, BFeeIdx); -#endif + send_sw_vht_gid_mgnt_frame(p_dm_odm, p_beamformee_entry->mac_addr, bfee_idx); +#endif - phydm_Beamforming_Notify(pDM_Odm); + phydm_beamforming_notify(p_dm_odm); #if 1 { - u4Byte ctrl_info_offset, index; + u32 ctrl_info_offset, index; /*Set Ctrl Info*/ - ODM_Write2Byte(pDM_Odm, 0x140, 0x660); - ctrl_info_offset = 0x8000 + 32 * pBeamformeeEntry->MacId; + odm_write_2byte(p_dm_odm, 0x140, 0x660); + ctrl_info_offset = 0x8000 + 32 * p_beamformee_entry->mac_id; /*Reset Ctrl Info*/ for (index = 0; index < 8; index++) - ODM_Write4Byte(pDM_Odm, ctrl_info_offset + index*4, 0); - - ODM_Write4Byte(pDM_Odm, ctrl_info_offset, (pBeamformeeEntry->mu_reg_index + 1) << 16); - ODM_Write1Byte(pDM_Odm, 0x81, 0x80); /*RPTBUF ready*/ + odm_write_4byte(p_dm_odm, ctrl_info_offset + index * 4, 0); + + odm_write_4byte(p_dm_odm, ctrl_info_offset, (p_beamformee_entry->mu_reg_index + 1) << 16); + odm_write_1byte(p_dm_odm, 0x81, 0x80); /*RPTBUF ready*/ - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, MacId = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n", - __func__, pBeamformeeEntry->MacId, ctrl_info_offset, pBeamformeeEntry->mu_reg_index)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, mac_id = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n", + __func__, p_beamformee_entry->mac_id, ctrl_info_offset, p_beamformee_entry->mu_reg_index)); } #endif } @@ -620,21 +637,21 @@ HalTxbf8822B_Enter( } -VOID -HalTxbf8822B_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx - ) +void +hal_txbf_8822b_leave( + void *p_dm_void, + u8 idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMER_ENTRY pBeamformerEntry; - PRT_BEAMFORMEE_ENTRY pBeamformeeEntry; - u4Byte mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; - - if (Idx < BEAMFORMER_ENTRY_NUM) { - pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[Idx]; - pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[Idx]; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry; + struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry; + u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; + + if (idx < BEAMFORMER_ENTRY_NUM) { + p_beamformer_entry = &p_beamforming_info->beamformer_entry[idx]; + p_beamformee_entry = &p_beamforming_info->beamformee_entry[idx]; } else return; @@ -642,75 +659,75 @@ HalTxbf8822B_Leave( /*Clear MAC address of Beamformer*/ /*Clear Associated Bfmee Sel*/ - if (pBeamformerEntry->BeamformEntryCap == BEAMFORMING_CAP_NONE) { - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xD8); - if (pBeamformerEntry->is_mu_ap == 0) { /*SU BFer */ - if (pBeamformerEntry->su_reg_index == 0) { - ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8822B+4, 0); - ODM_Write2Byte(pDM_Odm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0); + if (p_beamformer_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) { + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, 0xD8); + if (p_beamformer_entry->is_mu_ap == 0) { /*SU BFer */ + if (p_beamformer_entry->su_reg_index == 0) { + odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8822B + 4, 0); + odm_write_2byte(p_dm_odm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0); } else { - ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8822B+4, 0); - ODM_Write2Byte(pDM_Odm, REG_TX_CSI_RPT_PARAM_BW20_8822B+2, 0); + odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8822B + 4, 0); + odm_write_2byte(p_dm_odm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, 0); } - pBeamformingInfo->beamformer_su_reg_maping &= ~(BIT(pBeamformerEntry->su_reg_index)); - pBeamformerEntry->su_reg_index = 0xFF; + p_beamforming_info->beamformer_su_reg_maping &= ~(BIT(p_beamformer_entry->su_reg_index)); + p_beamformer_entry->su_reg_index = 0xFF; } else { /*MU BFer */ /*set validity of MU STA0 and MU STA1*/ - pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0; - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + p_beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; + odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); - ODM_Memory_Set(pDM_Odm, pBeamformerEntry->gid_valid, 0, 8); - ODM_Memory_Set(pDM_Odm, pBeamformerEntry->user_position, 0, 16); - pBeamformerEntry->is_mu_ap = FALSE; + odm_memory_set(p_dm_odm, p_beamformer_entry->gid_valid, 0, 8); + odm_memory_set(p_dm_odm, p_beamformer_entry->user_position, 0, 16); + p_beamformer_entry->is_mu_ap = false; } } - if (pBeamformeeEntry->BeamformEntryCap == BEAMFORMING_CAP_NONE) { - halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, Idx); - if (pBeamformeeEntry->is_mu_sta == 0) { /*SU BFee*/ - if (pBeamformeeEntry->su_reg_index == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, 0x0); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3)|BIT4|BIT6|BIT7); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0); + if (p_beamformee_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) { + hal_txbf_8822b_rf_mode(p_dm_odm, p_beamforming_info, idx); + if (p_beamformee_entry->is_mu_sta == 0) { /*SU BFee*/ + if (p_beamformee_entry->su_reg_index == 0) { + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B, 0x0); + odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0); } else { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B+2, 0x0 | BIT14 | BIT15 | BIT12); + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B + 2, 0x0 | BIT(14) | BIT(15) | BIT(12)); - ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2, - ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2) & 0x60); + odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, + odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2) & 0x60); } - pBeamformingInfo->beamformee_su_reg_maping &= ~(BIT(pBeamformeeEntry->su_reg_index)); - pBeamformeeEntry->su_reg_index = 0xFF; + p_beamforming_info->beamformee_su_reg_maping &= ~(BIT(p_beamformee_entry->su_reg_index)); + p_beamformee_entry->su_reg_index = 0xFF; } else { /*MU BFee */ /*Disable sending NDPA & BF-rpt-poll to this BFee*/ - ODM_Write2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index] , 0); + odm_write_2byte(p_dm_odm, mu_reg[p_beamformee_entry->mu_reg_index], 0); /*set validity of MU STA*/ - pBeamformingInfo->RegMUTxCtrl &= ~(BIT(pBeamformeeEntry->mu_reg_index)); - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(p_beamformee_entry->mu_reg_index)); + odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); - - pBeamformeeEntry->is_mu_sta = FALSE; - pBeamformingInfo->beamformee_mu_reg_maping &= ~(BIT(pBeamformeeEntry->mu_reg_index)); - pBeamformeeEntry->mu_reg_index = 0xFF; + + p_beamformee_entry->is_mu_sta = false; + p_beamforming_info->beamformee_mu_reg_maping &= ~(BIT(p_beamformee_entry->mu_reg_index)); + p_beamformee_entry->mu_reg_index = 0xFF; } } } /***********SU & MU BFee Entry Only when souding done****************/ -VOID -HalTxbf8822B_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx - ) +void +hal_txbf_8822b_status( + void *p_dm_void, + u8 beamform_idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte BeamCtrlVal, tmpVal; - u4Byte BeamCtrlReg; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamformEntry; - BOOLEAN is_mu_sounding = pBeamformingInfo->is_mu_sounding, is_bitmap_ready = FALSE; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u16 beam_ctrl_val, tmp_val; + u32 beam_ctrl_reg; + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry; + boolean is_mu_sounding = p_beamforming_info->is_mu_sounding, is_bitmap_ready = false; u16 bitmap; u8 idx, gid, i; u8 id1, id0; @@ -718,71 +735,71 @@ HalTxbf8822B_Status( u32 user_position_lsb[6] = {0}; u32 user_position_msb[6] = {0}; u32 value32; - BOOLEAN is_sounding_success[6] = {FALSE}; + boolean is_sounding_success[6] = {false}; - if (Idx < BEAMFORMEE_ENTRY_NUM) - pBeamformEntry = &pBeamformingInfo->BeamformeeEntry[Idx]; + if (beamform_idx < BEAMFORMEE_ENTRY_NUM) + p_beamform_entry = &p_beamforming_info->beamformee_entry[beamform_idx]; else return; - + /*SU sounding done */ - if (is_mu_sounding == FALSE) { + if (is_mu_sounding == false) { - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - BeamCtrlVal = pBeamformEntry->MacId; - else - BeamCtrlVal = pBeamformEntry->P_AID; + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + beam_ctrl_val = p_beamform_entry->mac_id; + else + beam_ctrl_val = p_beamform_entry->p_aid; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BeamformEntry.BeamformEntryState = %d", __func__, pBeamformEntry->BeamformEntryState)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, beamform_entry.beamform_entry_state = %d", __func__, p_beamform_entry->beamform_entry_state)); - if (pBeamformEntry->su_reg_index == 0) { - BeamCtrlReg = REG_TXBF_CTRL_8822B; - } else { - BeamCtrlReg = REG_TXBF_CTRL_8822B+2; - BeamCtrlVal |= BIT12|BIT14|BIT15; + if (p_beamform_entry->su_reg_index == 0) + beam_ctrl_reg = REG_TXBF_CTRL_8822B; + else { + beam_ctrl_reg = REG_TXBF_CTRL_8822B + 2; + beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); } - if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_20) - BeamCtrlVal |= BIT9; - else if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_40) - BeamCtrlVal |= (BIT9|BIT10); - else if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_80) - BeamCtrlVal |= (BIT9|BIT10|BIT11); + if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (p_beamform_entry->sound_bw == CHANNEL_WIDTH_20) + beam_ctrl_val |= BIT(9); + else if (p_beamform_entry->sound_bw == CHANNEL_WIDTH_40) + beam_ctrl_val |= (BIT(9) | BIT(10)); + else if (p_beamform_entry->sound_bw == CHANNEL_WIDTH_80) + beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11)); } else { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); - BeamCtrlVal &= ~(BIT9|BIT10|BIT11); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); + beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); } - ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); + odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val); /*disable NDP packet use beamforming */ - tmpVal = ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8822B); - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, tmpVal|BIT15); + tmp_val = odm_read_2byte(p_dm_odm, REG_TXBF_CTRL_8822B); + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B, tmp_val | BIT(15)); } else { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, MU Sounding Done\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, MU Sounding Done\n", __func__)); /*MU sounding done */ - if (1){//(pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n", __func__)); - - value32 = ODM_GetBBReg(pDM_Odm, 0x1684, bMaskDWord); - is_sounding_success[0] = (value32 & BIT10)?1:0; - is_sounding_success[1] = (value32 & BIT26)?1:0; - value32 = ODM_GetBBReg(pDM_Odm, 0x1688, bMaskDWord); - is_sounding_success[2] = (value32 & BIT10)?1:0; - is_sounding_success[3] = (value32 & BIT26)?1:0; - value32 = ODM_GetBBReg(pDM_Odm, 0x168C, bMaskDWord); - is_sounding_success[4] = (value32 & BIT10)?1:0; - is_sounding_success[5] = (value32 & BIT26)?1:0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n", - __func__, is_sounding_success[0], is_sounding_success[1] , is_sounding_success[2] , is_sounding_success[3] , is_sounding_success[4] , is_sounding_success[5] )); - - value32 = ODM_GetBBReg(pDM_Odm, 0xF4C, 0xFFFF0000); - //ODM_SetBBReg(pDM_Odm, 0x19E0, bMaskHWord, 0xFFFF);/*Let MAC ignore bitmap*/ - - is_bitmap_ready = (BOOLEAN)((value32 & BIT15) >> 15); + if (1) { /* (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { */ + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n", __func__)); + + value32 = odm_get_bb_reg(p_dm_odm, 0x1684, MASKDWORD); + is_sounding_success[0] = (value32 & BIT(10)) ? 1 : 0; + is_sounding_success[1] = (value32 & BIT(26)) ? 1 : 0; + value32 = odm_get_bb_reg(p_dm_odm, 0x1688, MASKDWORD); + is_sounding_success[2] = (value32 & BIT(10)) ? 1 : 0; + is_sounding_success[3] = (value32 & BIT(26)) ? 1 : 0; + value32 = odm_get_bb_reg(p_dm_odm, 0x168C, MASKDWORD); + is_sounding_success[4] = (value32 & BIT(10)) ? 1 : 0; + is_sounding_success[5] = (value32 & BIT(26)) ? 1 : 0; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n", + __func__, is_sounding_success[0], is_sounding_success[1], is_sounding_success[2], is_sounding_success[3], is_sounding_success[4], is_sounding_success[5])); + + value32 = odm_get_bb_reg(p_dm_odm, 0xF4C, 0xFFFF0000); + /* odm_set_bb_reg(p_dm_odm, 0x19E0, MASKHWORD, 0xFFFF);Let MAC ignore bitmap */ + + is_bitmap_ready = (boolean)((value32 & BIT(15)) >> 15); bitmap = (u16)(value32 & 0x3FFF); - + for (idx = 0; idx < 15; idx++) { if (idx < 5) {/*bit0~4*/ id0 = 0; @@ -793,7 +810,7 @@ HalTxbf8822B_Status( } else if (idx < 12) { /*bit9~11*/ id0 = 2; id1 = (u8)(idx - 6); - } else if (idx < 14) { /*bit12~13*/ + } else if (idx < 14) { /*bit12~13*/ id0 = 3; id1 = (u8)(idx - 8); } else { /*bit14*/ @@ -822,69 +839,69 @@ HalTxbf8822B_Status( } for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - pBeamformEntry = &pBeamformingInfo->BeamformeeEntry[i]; - if ((pBeamformEntry->is_mu_sta) && (pBeamformEntry->mu_reg_index < 6)) { - value32 = gid_valid[pBeamformEntry->mu_reg_index]; + p_beamform_entry = &p_beamforming_info->beamformee_entry[i]; + if ((p_beamform_entry->is_mu_sta) && (p_beamform_entry->mu_reg_index < 6)) { + value32 = gid_valid[p_beamform_entry->mu_reg_index]; for (idx = 0; idx < 4; idx++) { - pBeamformEntry->gid_valid[idx] = (u8)(value32 & 0xFF); + p_beamform_entry->gid_valid[idx] = (u8)(value32 & 0xFF); value32 = (value32 >> 8); } } } for (idx = 0; idx < 6; idx++) { - pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); - pBeamformingInfo->RegMUTxCtrl |= ((idx<<8)&(BIT8|BIT9|BIT10)); - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - ODM_SetMACReg(pDM_Odm, 0x14C4, bMaskDWord, gid_valid[idx]); /*set MU STA gid valid table*/ + p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + p_beamforming_info->reg_mu_tx_ctrl |= ((idx << 8) & (BIT(8) | BIT(9) | BIT(10))); + odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + odm_set_mac_reg(p_dm_odm, 0x14C4, MASKDWORD, gid_valid[idx]); /*set MU STA gid valid table*/ } /*Enable TxMU PPDU*/ - if (pBeamformingInfo->dbg_disable_mu_tx == FALSE) - pBeamformingInfo->RegMUTxCtrl |= BIT7; + if (p_beamforming_info->dbg_disable_mu_tx == false) + p_beamforming_info->reg_mu_tx_ctrl |= BIT(7); else - pBeamformingInfo->RegMUTxCtrl &= ~BIT7; - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + p_beamforming_info->reg_mu_tx_ctrl &= ~BIT(7); + odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); } } } /*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ -VOID -HalTxbf8822B_ConfigGtab( - IN PVOID pDM_VOID - ) +void +hal_txbf_8822b_config_gtab( + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL; - u4Byte gid_valid = 0, user_position_l = 0, user_position_h = 0, i; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry = NULL; + u32 gid_valid = 0, user_position_l = 0, user_position_h = 0, i; - if (pBeamformingInfo->mu_ap_index < BEAMFORMER_ENTRY_NUM) - pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[pBeamformingInfo->mu_ap_index]; + if (p_beamforming_info->mu_ap_index < BEAMFORMER_ENTRY_NUM) + p_beamformer_entry = &p_beamforming_info->beamformer_entry[p_beamforming_info->mu_ap_index]; else return; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s==>\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s==>\n", __func__)); /*For GID 0~31*/ for (i = 0; i < 4; i++) - gid_valid |= (pBeamformerEntry->gid_valid[i] << (i<<3)); + gid_valid |= (p_beamformer_entry->gid_valid[i] << (i << 3)); for (i = 0; i < 8; i++) { if (i < 4) - user_position_l |= (pBeamformerEntry->user_position[i] << (i << 3)); + user_position_l |= (p_beamformer_entry->user_position[i] << (i << 3)); else - user_position_h |= (pBeamformerEntry->user_position[i] << ((i - 4)<<3)); + user_position_h |= (p_beamformer_entry->user_position[i] << ((i - 4) << 3)); } /*select MU STA0 table*/ - pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - ODM_SetBBReg(pDM_Odm, 0x14c4, bMaskDWord, gid_valid); - ODM_SetBBReg(pDM_Odm, 0x14c8, bMaskDWord, user_position_l); - ODM_SetBBReg(pDM_Odm, 0x14cc, bMaskDWord, user_position_h); + p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + odm_set_bb_reg(p_dm_odm, 0x14c4, MASKDWORD, gid_valid); + odm_set_bb_reg(p_dm_odm, 0x14c8, MASKDWORD, user_position_l); + odm_set_bb_reg(p_dm_odm, 0x14cc, MASKDWORD, user_position_h); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", - __func__, gid_valid, user_position_l, user_position_h)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, gid_valid, user_position_l, user_position_h)); gid_valid = 0; user_position_l = 0; @@ -892,46 +909,46 @@ HalTxbf8822B_ConfigGtab( /*For GID 32~64*/ for (i = 4; i < 8; i++) - gid_valid |= (pBeamformerEntry->gid_valid[i] << ((i - 4)<<3)); + gid_valid |= (p_beamformer_entry->gid_valid[i] << ((i - 4) << 3)); for (i = 8; i < 16; i++) { if (i < 4) - user_position_l |= (pBeamformerEntry->user_position[i] << ((i - 8) << 3)); + user_position_l |= (p_beamformer_entry->user_position[i] << ((i - 8) << 3)); else - user_position_h |= (pBeamformerEntry->user_position[i] << ((i - 12) << 3)); + user_position_h |= (p_beamformer_entry->user_position[i] << ((i - 12) << 3)); } /*select MU STA1 table*/ - pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); - pBeamformingInfo->RegMUTxCtrl |= BIT8; - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - ODM_SetBBReg(pDM_Odm, 0x14c4, bMaskDWord, gid_valid); - ODM_SetBBReg(pDM_Odm, 0x14c8, bMaskDWord, user_position_l); - ODM_SetBBReg(pDM_Odm, 0x14cc, bMaskDWord, user_position_h); + p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + p_beamforming_info->reg_mu_tx_ctrl |= BIT(8); + odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + odm_set_bb_reg(p_dm_odm, 0x14c4, MASKDWORD, gid_valid); + odm_set_bb_reg(p_dm_odm, 0x14c8, MASKDWORD, user_position_l); + odm_set_bb_reg(p_dm_odm, 0x14cc, MASKDWORD, user_position_h); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", - __func__, gid_valid, user_position_l, user_position_h)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, gid_valid, user_position_l, user_position_h)); /* Set validity of MU STA0 and MU STA1*/ - pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0; - pBeamformingInfo->RegMUTxCtrl |= 0x3; /* STA0, STA1*/ - ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); - + p_beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; + p_beamforming_info->reg_mu_tx_ctrl |= 0x3; /* STA0, STA1*/ + odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + } #if 0 /*This function translate the bitmap to GTAB*/ -VOID +void haltxbf8822b_gtab_translation( - IN PDM_ODM_T pDM_Odm -) + struct PHY_DM_STRUCT *p_dm_odm +) { u8 idx, gid; u8 id1, id0; u32 gid_valid[6] = {0}; u32 user_position_lsb[6] = {0}; u32 user_position_msb[6] = {0}; - + for (idx = 0; idx < 15; idx++) { if (idx < 5) {/*bit0~4*/ id0 = 0; @@ -942,7 +959,7 @@ haltxbf8822b_gtab_translation( } else if (idx < 12) { /*bit9~11*/ id0 = 2; id1 = (u8)(idx - 6); - } else if (idx < 14) { /*bit12~13*/ + } else if (idx < 14) { /*bit12~13*/ id0 = 3; id1 = (u8)(idx - 8); } else { /*bit14*/ @@ -961,7 +978,7 @@ haltxbf8822b_gtab_translation( /*user_position_msb[id0] |= (0 << ((gid - 16) << 1));*/ user_position_msb[id1] |= (1 << ((gid - 16) << 1)); } - + /*Pair 2*/ gid += 1; gid_valid[id0] |= (1 << gid); @@ -978,124 +995,120 @@ haltxbf8822b_gtab_translation( for (idx = 0; idx < 6; idx++) { - /*DbgPrint("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]); - DbgPrint("user_position[%d] = 0x%x %x\n", idx, user_position_msb[idx], user_position_lsb[idx]);*/ + /*dbg_print("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]); + dbg_print("user_position[%d] = 0x%x %x\n", idx, user_position_msb[idx], user_position_lsb[idx]);*/ } } #endif -VOID -HalTxbf8822B_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx - ) +void +hal_txbf_8822b_fw_txbf( + void *p_dm_void, + u8 idx +) { #if 0 - PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry+Idx; + struct _RT_BEAMFORMING_INFO *p_beam_info = GET_BEAMFORM_INFO(adapter); + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; - if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) - halTxbf8822B_DownloadNDPA(Adapter, Idx); + if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) + hal_txbf_8822b_download_ndpa(adapter, idx); - halTxbf8822B_FwTxBFCmd(Adapter); + hal_txbf_8822b_fw_txbf_cmd(adapter); #endif } +#endif +#if (defined(CONFIG_BB_TXBF_API)) /*this function is only used for BFer*/ -VOID +void phydm_8822btxbf_rfmode( - IN PVOID pDM_VOID, - IN u1Byte SUBFeeCnt, - IN u1Byte MUBFeeCnt - ) + void *p_dm_void, + u8 su_bfee_cnt, + u8 mu_bfee_cnt +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i, Nr_index = 0; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i, nr_index = 0; - if (pDM_Odm->RFType == ODM_1T1R) + if (p_dm_odm->rf_type == ODM_1T1R) return; - if ((SUBFeeCnt > 0) || (MUBFeeCnt > 0)) { + if ((su_bfee_cnt > 0) || (mu_bfee_cnt > 0)) { for (i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++) { - ODM_SetRFReg(pDM_Odm, i, 0xEF, BIT19, 0x1); /*RF Mode table write enable*/ - ODM_SetRFReg(pDM_Odm, i, 0x33, 0xF, 3); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, i, 0x3E, 0xfffff, 0x00036); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, i, 0x3F, 0xfffff, 0x5AFCE); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, i, 0xEF, BIT19, 0x0); /*RF Mode table write disable*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0xEF, BIT(19), 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0x33, 0xF, 3); /*Select RX mode*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0x3E, 0xfffff, 0x00036); /*Set Table data*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0x3F, 0xfffff, 0x5AFCE); /*Set Table data*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0xEF, BIT(19), 0x0); /*RF mode table write disable*/ } } - if (SUBFeeCnt > 0 || MUBFeeCnt > 0) { + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(30), 1); /*if Nsts > Nc, don't apply V matrix*/ + + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT28|BIT29, 0x2); /*enable BB TxBF ant mapping register*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT31, 1); /*ignore user since 8822B only 2Tx*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); /*ignore user since 8822B only 2Tx*/ + /*Nsts = 2 AB*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); } else { - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT28|BIT29, 0x0); /*enable BB TxBF ant mapping register*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT31, 0); /*ignore user since 8822B only 2Tx*/ - - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ - ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2_8822B, bMaskLWord, 0x430); /*2SS by path-A,B*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x0); /*enable BB TxBF ant mapping register*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 0); /*ignore user since 8822B only 2Tx*/ + + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ + odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*2SS by path-A,B*/ } } /*this function is for BFer bug workaround*/ -VOID +void phydm_8822b_sutxbfer_workaroud( - IN PVOID pDM_VOID, - IN BOOLEAN EnableSUBfer, - IN u1Byte Nc, - IN u1Byte Nr, - IN u1Byte Ng, - IN u1Byte CB, - IN u1Byte BW, - IN BOOLEAN isVHT - ) + void *p_dm_void, + boolean enable_su_bfer, + u8 nc, + u8 nr, + u8 ng, + u8 CB, + u8 BW, + boolean is_vht +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (EnableSUBfer) { - ODM_SetBBReg(pDM_Odm, 0x19f8, BIT22|BIT21|BIT20, 0x1); - ODM_SetBBReg(pDM_Odm, 0x19f8, BIT25|BIT24|BIT23, 0x0); - ODM_SetBBReg(pDM_Odm, 0x19f8, BIT16, 0x1); + if (enable_su_bfer) { + odm_set_bb_reg(p_dm_odm, 0x19f8, BIT(22) | BIT(21) | BIT(20), 0x1); + odm_set_bb_reg(p_dm_odm, 0x19f8, BIT(25) | BIT(24) | BIT(23), 0x0); + odm_set_bb_reg(p_dm_odm, 0x19f8, BIT(16), 0x1); - if (isVHT) - ODM_SetBBReg(pDM_Odm, 0x19f0, BIT5|BIT4|BIT3|BIT2|BIT1|BIT0, 0x1f); + if (is_vht) + odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x1f); else - ODM_SetBBReg(pDM_Odm, 0x19f0, BIT5|BIT4|BIT3|BIT2|BIT1|BIT0, 0x22); - - ODM_SetBBReg(pDM_Odm, 0x19f0, BIT7|BIT6, Nc); - ODM_SetBBReg(pDM_Odm, 0x19f0, BIT9|BIT8, Nr); - ODM_SetBBReg(pDM_Odm, 0x19f0, BIT11|BIT10, Ng); - ODM_SetBBReg(pDM_Odm, 0x19f0, BIT13|BIT12, CB); - - ODM_SetBBReg(pDM_Odm, 0xb58, BIT3|BIT2, BW); - ODM_SetBBReg(pDM_Odm, 0xb58, BIT7|BIT6|BIT5|BIT4, 0x0); - ODM_SetBBReg(pDM_Odm, 0xb58, BIT9|BIT8, BW); - ODM_SetBBReg(pDM_Odm, 0xb58, BIT13|BIT12|BIT11|BIT10, 0x0); - } else - ODM_SetBBReg(pDM_Odm, 0x19f8, BIT16, 0x0); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] EnableSUBfer = %d, isVHT = %d\n", __func__, EnableSUBfer, isVHT)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] Nc = %d, Nr = %d, Ng = %d, CB = %d, BW = %d\n", __func__, Nc, Nr, Ng, CB, BW)); - - -} + odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x22); + odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(7) | BIT(6), nc); + odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(9) | BIT(8), nr); + odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(11) | BIT(10), ng); + odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(13) | BIT(12), CB); + odm_set_bb_reg(p_dm_odm, 0xb58, BIT(3) | BIT(2), BW); + odm_set_bb_reg(p_dm_odm, 0xb58, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x0); + odm_set_bb_reg(p_dm_odm, 0xb58, BIT(9) | BIT(8), BW); + odm_set_bb_reg(p_dm_odm, 0xb58, BIT(13) | BIT(12) | BIT(11) | BIT(10), 0x0); + } else + odm_set_bb_reg(p_dm_odm, 0x19f8, BIT(16), 0x0); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] enable_su_bfer = %d, is_vht = %d\n", __func__, enable_su_bfer, is_vht)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] nc = %d, nr = %d, ng = %d, CB = %d, BW = %d\n", __func__, nc, nr, ng, CB, BW)); -#else /* (RTL8822B_SUPPORT == 1)*/ +} +#endif #endif /* (RTL8822B_SUPPORT == 1)*/ - -#endif - - diff --git a/hal/phydm/txbf/haltxbf8822b.h b/hal/phydm/txbf/haltxbf8822b.h index d35675a..2ff19bd 100644 --- a/hal/phydm/txbf/haltxbf8822b.h +++ b/hal/phydm/txbf/haltxbf8822b.h @@ -1,73 +1,93 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __HAL_TXBF_8822B_H__ #define __HAL_TXBF_8822B_H__ -#if (BEAMFORMING_SUPPORT == 1) + #if (RTL8822B_SUPPORT == 1) +#if (BEAMFORMING_SUPPORT == 1) -VOID -HalTxbf8822B_Init( - IN PVOID pDM_VOID - ); +void +hal_txbf_8822b_enter( + void *p_dm_void, + u8 idx +); -VOID -HalTxbf8822B_Enter( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_8822b_leave( + void *p_dm_void, + u8 idx +); -VOID -HalTxbf8822B_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_8822b_status( + void *p_dm_void, + u8 beamform_idx +); -VOID -HalTxbf8822B_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_8822b_config_gtab( + void *p_dm_void +); -VOID -HalTxbf8822B_ConfigGtab( - IN PVOID pDM_VOID - ); +void +hal_txbf_8822b_fw_txbf( + void *p_dm_void, + u8 idx +); +#else +#define hal_txbf_8822b_enter(p_dm_void, idx) +#define hal_txbf_8822b_leave(p_dm_void, idx) +#define hal_txbf_8822b_status(p_dm_void, idx) +#define hal_txbf_8822b_fw_txbf(p_dm_void, idx) +#define hal_txbf_8822b_config_gtab(p_dm_void) -VOID -HalTxbf8822B_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +#endif -VOID +#if (defined(CONFIG_BB_TXBF_API)) +void phydm_8822btxbf_rfmode( - IN PVOID pDM_VOID, - IN u1Byte SUBFeeCnt, - IN u1Byte MUBFeeCnt - ); + void *p_dm_void, + u8 su_bfee_cnt, + u8 mu_bfee_cnt +); -VOID +void phydm_8822b_sutxbfer_workaroud( - IN PVOID pDM_VOID, - IN BOOLEAN EnableSUBfer, - IN u1Byte Nc, - IN u1Byte Nr, - IN u1Byte Ng, - IN u1Byte CB, - IN u1Byte BW, - IN BOOLEAN isVHT - ); + void *p_dm_void, + boolean enable_su_bfer, + u8 nc, + u8 nr, + u8 ng, + u8 CB, + u8 BW, + boolean is_vht +); #else -#define HalTxbf8822B_Init(pDM_VOID) -#define HalTxbf8822B_Enter(pDM_VOID, Idx) -#define HalTxbf8822B_Leave(pDM_VOID, Idx) -#define HalTxbf8822B_Status(pDM_VOID, Idx) -#define HalTxbf8822B_FwTxBF(pDM_VOID, Idx) -#define HalTxbf8822B_ConfigGtab(pDM_VOID) +#define phydm_8822btxbf_rfmode(p_dm_void, su_bfee_cnt, mu_bfee_cnt) +#define phydm_8822b_sutxbfer_workaroud(p_dm_void, enable_su_bfer, nc, nr, ng, CB, BW, is_vht) #endif +#else +#define hal_txbf_8822b_enter(p_dm_void, idx) +#define hal_txbf_8822b_leave(p_dm_void, idx) +#define hal_txbf_8822b_status(p_dm_void, idx) +#define hal_txbf_8822b_fw_txbf(p_dm_void, idx) +#define hal_txbf_8822b_config_gtab(p_dm_void) #endif #endif - diff --git a/hal/phydm/txbf/haltxbfinterface.c b/hal/phydm/txbf/haltxbfinterface.c index 3ac0b16..5be3016 100644 --- a/hal/phydm/txbf/haltxbfinterface.c +++ b/hal/phydm/txbf/haltxbfinterface.c @@ -1,469 +1,483 @@ -//============================================================ -// Description: -// -// This file is for TXBF interface mechanism -// -//============================================================ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for TXBF interface mechanism + * + * ************************************************************ */ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -Beamforming_GidPAid( - PADAPTER Adapter, - PRT_TCB pTcb +void +beamforming_gid_paid( + struct _ADAPTER *adapter, + PRT_TCB p_tcb ) { - u1Byte Idx = 0; - u1Byte RA[6] ={0}; - pu1Byte pHeader = GET_FRAME_OF_FIRST_FRAG(Adapter, pTcb); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - - if (Adapter->HardwareType < HARDWARE_TYPE_RTL8192EE) + u8 idx = 0; + u8 RA[6] = {0}; + u8 *p_header = GET_FRAME_OF_FIRST_FRAG(adapter, p_tcb); + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + + if (adapter->HardwareType < HARDWARE_TYPE_RTL8192EE) return; - else if (IS_WIRELESS_MODE_N(Adapter) == FALSE) + else if (IS_WIRELESS_MODE_N(adapter) == false) return; #if (SUPPORT_MU_BF == 1) - if (pTcb->TxBFPktType == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* MU NDPA */ + if (p_tcb->tx_bf_pkt_type == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* MU NDPA */ #else if (0) { #endif /* Fill G_ID and P_AID */ - pTcb->G_ID = 63; - if (pBeamInfo->FirstMUBFeeIndex < BEAMFORMEE_ENTRY_NUM) { - pTcb->P_AID = pBeamInfo->BeamformeeEntry[pBeamInfo->FirstMUBFeeIndex].P_AID; - RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, pTcb->G_ID, pTcb->P_AID)); + p_tcb->G_ID = 63; + if (p_beam_info->first_mu_bfee_index < BEAMFORMEE_ENTRY_NUM) { + p_tcb->P_AID = p_beam_info->beamformee_entry[p_beam_info->first_mu_bfee_index].p_aid; + RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, p_tcb->G_ID, p_tcb->P_AID)); } } else { - GET_80211_HDR_ADDRESS1(pHeader, &RA); - - // VHT SU PPDU carrying one or more group addressed MPDUs or - // Transmitting a VHT NDP intended for multiple recipients - if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || pTcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) { - pTcb->G_ID = 63; - pTcb->P_AID = 0; - } else if (ACTING_AS_AP(Adapter)) { - u2Byte AID = (u2Byte) (MacIdGetOwnerAssociatedClientAID(Adapter, pTcb->macId) & 0x1ff); /*AID[0:8]*/ - - /*RT_DISP(FBEAM, FBEAM_FUN, ("@%s pTcb->macId=0x%X, AID=0x%X\n", __func__, pTcb->macId, AID));*/ - pTcb->G_ID = 63; + GET_80211_HDR_ADDRESS1(p_header, &RA); + + /* VHT SU PPDU carrying one or more group addressed MPDUs or */ + /* Transmitting a VHT NDP intended for multiple recipients */ + if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || p_tcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) { + p_tcb->G_ID = 63; + p_tcb->P_AID = 0; + } else if (ACTING_AS_AP(adapter)) { + u16 AID = (u16)(MacIdGetOwnerAssociatedClientAID(adapter, p_tcb->macId) & 0x1ff); /*AID[0:8]*/ + + /*RT_DISP(FBEAM, FBEAM_FUN, ("@%s p_tcb->mac_id=0x%X, AID=0x%X\n", __func__, p_tcb->mac_id, AID));*/ + p_tcb->G_ID = 63; if (AID == 0) /*A PPDU sent by an AP to a non associated STA*/ - pTcb->P_AID = 0; + p_tcb->P_AID = 0; else { /*Sent by an AP and addressed to a STA associated with that AP*/ - u2Byte BSSID = 0; - GET_80211_HDR_ADDRESS2(pHeader, &RA); + u16 BSSID = 0; + GET_80211_HDR_ADDRESS2(p_header, &RA); BSSID = ((RA[5] & 0xf0) >> 4) ^ (RA[5] & 0xf); /*BSSID[44:47] xor BSSID[40:43]*/ - pTcb->P_AID = (AID + BSSID *32) & 0x1ff; /*(dec(A) + dec(B)*32) mod 512*/ + p_tcb->P_AID = (AID + BSSID * 32) & 0x1ff; /*(dec(A) + dec(B)*32) mod 512*/ } - } else if (ACTING_AS_IBSS(Adapter)) { - pTcb->G_ID = 63; + } else if (ACTING_AS_IBSS(adapter)) { + p_tcb->G_ID = 63; /*P_AID for infrasturcture mode; MACID for ad-hoc mode. */ - pTcb->P_AID = pTcb->macId; - } else if (MgntLinkStatusQuery(Adapter)) { /*Addressed to AP*/ - pTcb->G_ID = 0; - GET_80211_HDR_ADDRESS1(pHeader, &RA); - pTcb->P_AID = RA[5]; /*RA[39:47]*/ - pTcb->P_AID = (pTcb->P_AID << 1) | (RA[4] >> 7 ); + p_tcb->P_AID = p_tcb->macId; + } else if (MgntLinkStatusQuery(adapter)) { /*Addressed to AP*/ + p_tcb->G_ID = 0; + GET_80211_HDR_ADDRESS1(p_header, &RA); + p_tcb->P_AID = RA[5]; /*RA[39:47]*/ + p_tcb->P_AID = (p_tcb->P_AID << 1) | (RA[4] >> 7); } else { - pTcb->G_ID = 63; - pTcb->P_AID = 0; + p_tcb->G_ID = 63; + p_tcb->P_AID = 0; } - /*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, pTcb->G_ID, pTcb->P_AID));*/ + /*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, p_tcb->G_ID, p_tcb->P_AID));*/ } } -RT_STATUS -Beamforming_GetReportFrame( - IN PADAPTER Adapter, - IN PRT_RFD pRfd, - IN POCTET_STRING pPduOS - ) +enum rt_status +beamforming_get_report_frame( + struct _ADAPTER *adapter, + PRT_RFD p_rfd, + POCTET_STRING p_pdu_os +) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; - pu1Byte pMIMOCtrlField, pCSIReport, pCSIMatrix; - u1Byte Idx, Nc, Nr, CH_W; - u2Byte CSIMatrixLen = 0; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; + u8 *p_mimo_ctrl_field, p_csi_report, p_csi_matrix; + u8 idx, nc, nr, CH_W; + u16 csi_matrix_len = 0; - ACT_PKT_TYPE pktType = ACT_PKT_TYPE_UNKNOWN; + ACT_PKT_TYPE pkt_type = ACT_PKT_TYPE_UNKNOWN; - //Memory comparison to see if CSI report is the same with previous one - pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, Frame_Addr2(*pPduOS), &Idx); + /* Memory comparison to see if CSI report is the same with previous one */ + p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, Frame_Addr2(*p_pdu_os), &idx); - if (pBeamformEntry == NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Beamforming_GetReportFrame: Cannot find entry by addr\n")); + if (p_beamform_entry == NULL) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("beamforming_get_report_frame: Cannot find entry by addr\n")); return RT_STATUS_FAILURE; } - pktType = PacketGetActionFrameType(pPduOS); - - //-@ Modified by David - if (pktType == ACT_PKT_VHT_COMPRESSED_BEAMFORMING) { - pMIMOCtrlField = pPduOS->Octet + 26; - Nc = ((*pMIMOCtrlField) & 0x7) + 1; - Nr = (((*pMIMOCtrlField) & 0x38) >> 3) + 1; - CH_W = (((*pMIMOCtrlField) & 0xC0) >> 6); - pCSIMatrix = pMIMOCtrlField + 3 + Nc; //24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(Nc=2) - CSIMatrixLen = pPduOS->Length - 26 -3 -Nc; - } else if (pktType == ACT_PKT_HT_COMPRESSED_BEAMFORMING) { - pMIMOCtrlField = pPduOS->Octet + 26; - Nc = ((*pMIMOCtrlField) & 0x3) + 1; - Nr = (((*pMIMOCtrlField) & 0xC) >> 2) + 1; - CH_W = (((*pMIMOCtrlField) & 0x10) >> 4); - pCSIMatrix = pMIMOCtrlField + 6 + Nr; //24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(Nc=2) - CSIMatrixLen = pPduOS->Length - 26 -6 -Nr; + pkt_type = PacketGetActionFrameType(p_pdu_os); + + /* -@ Modified by David */ + if (pkt_type == ACT_PKT_VHT_COMPRESSED_BEAMFORMING) { + p_mimo_ctrl_field = p_pdu_os->Octet + 26; + nc = ((*p_mimo_ctrl_field) & 0x7) + 1; + nr = (((*p_mimo_ctrl_field) & 0x38) >> 3) + 1; + CH_W = (((*p_mimo_ctrl_field) & 0xC0) >> 6); + /*p_csi_matrix = p_mimo_ctrl_field + 3 + nc;*/ /* 24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */ + csi_matrix_len = p_pdu_os->Length - 26 - 3 - nc; + } else if (pkt_type == ACT_PKT_HT_COMPRESSED_BEAMFORMING) { + p_mimo_ctrl_field = p_pdu_os->Octet + 26; + nc = ((*p_mimo_ctrl_field) & 0x3) + 1; + nr = (((*p_mimo_ctrl_field) & 0xC) >> 2) + 1; + CH_W = (((*p_mimo_ctrl_field) & 0x10) >> 4); + /*p_csi_matrix = p_mimo_ctrl_field + 6 + nr;*/ /* 24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */ + csi_matrix_len = p_pdu_os->Length - 26 - 6 - nr; } else - return RT_STATUS_SUCCESS; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d, pkt type=%d, Nc=%d, Nr=%d, CH_W=%d\n", __func__, Idx, pktType, Nc, Nr, CH_W)); + return RT_STATUS_SUCCESS; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d, pkt type=%d, nc=%d, nr=%d, CH_W=%d\n", __func__, idx, pkt_type, nc, nr, CH_W)); return RT_STATUS_SUCCESS; } -VOID -ConstructHTNDPAPacket( - PADAPTER Adapter, - pu1Byte RA, - pu1Byte Buffer, - pu4Byte pLength, +void +construct_ht_ndpa_packet( + struct _ADAPTER *adapter, + u8 *RA, + u8 *buffer, + u32 *p_length, CHANNEL_WIDTH BW - ) +) { - u2Byte Duration= 0; - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - OCTET_STRING pNDPAFrame,ActionContent; - u1Byte ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + u16 duration = 0; + PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); + OCTET_STRING p_ndpa_frame, action_content; + u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + + PlatformZeroMemory(buffer, 32); - PlatformZeroMemory(Buffer, 32); + SET_80211_HDR_FRAME_CONTROL(buffer, 0); - SET_80211_HDR_FRAME_CONTROL(Buffer,0); + SET_80211_HDR_ORDER(buffer, 1); + SET_80211_HDR_TYPE_AND_SUBTYPE(buffer, Type_Action_No_Ack); - SET_80211_HDR_ORDER(Buffer, 1); - SET_80211_HDR_TYPE_AND_SUBTYPE(Buffer,Type_Action_No_Ack); + SET_80211_HDR_ADDRESS1(buffer, RA); + SET_80211_HDR_ADDRESS2(buffer, adapter->CurrentAddress); + SET_80211_HDR_ADDRESS3(buffer, p_mgnt_info->Bssid); - SET_80211_HDR_ADDRESS1(Buffer, RA); - SET_80211_HDR_ADDRESS2(Buffer, Adapter->CurrentAddress); - SET_80211_HDR_ADDRESS3(Buffer, pMgntInfo->Bssid); + duration = 2 * a_SifsTime + 40; - Duration = 2*aSifsTime + 40; - if (BW == CHANNEL_WIDTH_40) - Duration+= 87; - else - Duration+= 180; + duration += 87; + else + duration += 180; + + SET_80211_HDR_DURATION(buffer, duration); - SET_80211_HDR_DURATION(Buffer, Duration); + /* HT control field */ + SET_HT_CTRL_CSI_STEERING(buffer + sMacHdrLng, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(buffer + sMacHdrLng, 1); - //HT control field - SET_HT_CTRL_CSI_STEERING(Buffer+sMacHdrLng, 3); - SET_HT_CTRL_NDP_ANNOUNCEMENT(Buffer+sMacHdrLng, 1); - - FillOctetString(pNDPAFrame, Buffer, sMacHdrLng+sHTCLng); + FillOctetString(p_ndpa_frame, buffer, sMacHdrLng + sHTCLng); - FillOctetString(ActionContent, ActionHdr, 4); - PacketAppendData(&pNDPAFrame, ActionContent); + FillOctetString(action_content, action_hdr, 4); + PacketAppendData(&p_ndpa_frame, action_content); - *pLength = 32; + *p_length = 32; } -BOOLEAN -SendFWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ) +boolean +send_fw_ht_ndpa_packet( + void *p_dm_void, + u8 *RA, + CHANNEL_WIDTH BW +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u4Byte BufLen; - pu1Byte BufAddr; - u1Byte DescLen = 0, Idx = 0, NDPTxRate; - PADAPTER pDefAdapter = GetDefaultAdapter(Adapter); - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pBeamformEntry == NULL) - return FALSE; - - NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetFWBuffer(pDefAdapter, &pTcb, &pBuf)) { -#if(DEV_BUS_TYPE != RT_PCI_INTERFACE) - DescLen = Adapter->HWDescHeadLength - pHalData->USBALLDummyLength; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + PRT_TCB p_tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u32 buf_len; + u8 *buf_addr; + u8 desc_len = 0, idx = 0, ndp_tx_rate; + struct _ADAPTER *p_def_adapter = GetDefaultAdapter(adapter); + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (p_beamform_entry == NULL) + return false; + + ndp_tx_rate = beamforming_get_htndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetFWBuffer(p_def_adapter, &p_tcb, &p_buf)) { +#if (DEV_BUS_TYPE != RT_PCI_INTERFACE) + desc_len = adapter->HWDescHeadLength - p_hal_data->USBALLDummyLength; #endif - BufAddr = pBuf->Buffer.VirtualAddress + DescLen; + buf_addr = p_buf->Buffer.VirtualAddress + desc_len; - ConstructHTNDPAPacket( - Adapter, - RA, - BufAddr, - &BufLen, - BW - ); + construct_ht_ndpa_packet( + adapter, + RA, + buf_addr, + &buf_len, + BW + ); - pTcb->PacketLength = BufLen + DescLen; + p_tcb->PacketLength = buf_len + desc_len; - pTcb->bTxEnableSwCalcDur = TRUE; - - pTcb->BWOfPacket = BW; + p_tcb->bTxEnableSwCalcDur = true; - if(ACTING_AS_IBSS(Adapter) || ACTING_AS_AP(Adapter)) - pTcb->G_ID = 63; + p_tcb->BWOfPacket = BW; - pTcb->P_AID = pBeamformEntry->P_AID; - pTcb->DataRate = NDPTxRate; /*rate of NDP decide by Nr*/ + if (ACTING_AS_IBSS(adapter) || ACTING_AS_AP(adapter)) + p_tcb->G_ID = 63; - Adapter->HalFunc.CmdSendPacketHandler(Adapter, pTcb, pBuf, pTcb->PacketLength, DESC_PACKET_TYPE_NORMAL, FALSE); + p_tcb->P_AID = p_beamform_entry->p_aid; + p_tcb->DataRate = ndp_tx_rate; /*rate of NDP decide by nr*/ + + adapter->HalFunc.CmdSendPacketHandler(adapter, p_tcb, p_buf, p_tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false); } else - ret = FALSE; + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); - if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); return ret; } -BOOLEAN -SendSWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ) +boolean +send_sw_ht_ndpa_packet( + void *p_dm_void, + u8 *RA, + CHANNEL_WIDTH BW +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u1Byte Idx = 0, NDPTxRate = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { - ConstructHTNDPAPacket( - Adapter, - RA, - pBuf->Buffer.VirtualAddress, - &pTcb->PacketLength, - BW - ); - - pTcb->bTxEnableSwCalcDur = TRUE; - - pTcb->BWOfPacket = BW; - - MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + PRT_TCB p_tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 idx = 0, ndp_tx_rate = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + ndp_tx_rate = beamforming_get_htndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + construct_ht_ndpa_packet( + adapter, + RA, + p_buf->Buffer.VirtualAddress, + &p_tcb->PacketLength, + BW + ); + + p_tcb->bTxEnableSwCalcDur = true; + + p_tcb->BWOfPacket = BW; + + MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); return ret; } -VOID -ConstructVHTNDPAPacket( - IN PDM_ODM_T pDM_Odm, - pu1Byte RA, - u2Byte AID, - pu1Byte Buffer, - pu4Byte pLength, +void +construct_vht_ndpa_packet( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *RA, + u16 AID, + u8 *buffer, + u32 *p_length, CHANNEL_WIDTH BW - ) +) { - u2Byte Duration= 0; - u1Byte Sequence = 0; - pu1Byte pNDPAFrame = Buffer; - RT_NDPA_STA_INFO STAInfo; - PADAPTER Adapter = pDM_Odm->Adapter; - u1Byte Idx = 0; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - // Frame control. - SET_80211_HDR_FRAME_CONTROL(pNDPAFrame, 0); - SET_80211_HDR_TYPE_AND_SUBTYPE(pNDPAFrame, Type_NDPA); - - SET_80211_HDR_ADDRESS1(pNDPAFrame, RA); - SET_80211_HDR_ADDRESS2(pNDPAFrame, pBeamformEntry->MyMacAddr); - - Duration = 2*aSifsTime + 44; - + u16 duration = 0; + u8 sequence = 0; + u8 *p_ndpa_frame = buffer; + struct _RT_NDPA_STA_INFO sta_info; + struct _ADAPTER *adapter = p_dm_odm->adapter; + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + /* Frame control. */ + SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA); + + SET_80211_HDR_ADDRESS1(p_ndpa_frame, RA); + SET_80211_HDR_ADDRESS2(p_ndpa_frame, p_beamform_entry->my_mac_addr); + + duration = 2 * a_SifsTime + 44; + if (BW == CHANNEL_WIDTH_80) - Duration += 40; - else if(BW == CHANNEL_WIDTH_40) - Duration+= 87; - else - Duration+= 180; + duration += 40; + else if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; - SET_80211_HDR_DURATION(pNDPAFrame, Duration); + SET_80211_HDR_DURATION(p_ndpa_frame, duration); - Sequence = *(pDM_Odm->pSoundingSeq) << 2; - ODM_MoveMemory(pDM_Odm, pNDPAFrame+16, &Sequence, 1); + sequence = *(p_dm_odm->p_sounding_seq) << 2; + odm_move_memory(p_dm_odm, p_ndpa_frame + 16, &sequence, 1); - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS) || phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP) == FALSE) + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss) || phydm_acting_determine(p_dm_odm, phydm_acting_as_ap) == false) AID = 0; - STAInfo.AID = AID; - STAInfo.FeedbackType = 0; - STAInfo.NcIndex = 0; - - ODM_MoveMemory(pDM_Odm, pNDPAFrame+17, (pu1Byte)&STAInfo, 2); + sta_info.aid = AID; + sta_info.feedback_type = 0; + sta_info.nc_index = 0; + + odm_move_memory(p_dm_odm, p_ndpa_frame + 17, (u8 *)&sta_info, 2); - *pLength = 19; + *p_length = 19; } -BOOLEAN -SendFWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ) +boolean +send_fw_vht_ndpa_packet( + void *p_dm_void, + u8 *RA, + u16 AID, + CHANNEL_WIDTH BW +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u4Byte BufLen; - pu1Byte BufAddr; - u1Byte DescLen = 0, Idx = 0, NDPTxRate = 0; - PADAPTER pDefAdapter = GetDefaultAdapter(Adapter); - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PRT_BEAMFORMEE_ENTRY pBeamformEntry =phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (pBeamformEntry == NULL) - return FALSE; - - NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetFWBuffer(pDefAdapter, &pTcb, &pBuf)) { -#if(DEV_BUS_TYPE != RT_PCI_INTERFACE) - DescLen = Adapter->HWDescHeadLength - pHalData->USBALLDummyLength; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + PRT_TCB p_tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u32 buf_len; + u8 *buf_addr; + u8 desc_len = 0, idx = 0, ndp_tx_rate = 0; + struct _ADAPTER *p_def_adapter = GetDefaultAdapter(adapter); + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (p_beamform_entry == NULL) + return false; + + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetFWBuffer(p_def_adapter, &p_tcb, &p_buf)) { +#if (DEV_BUS_TYPE != RT_PCI_INTERFACE) + desc_len = adapter->HWDescHeadLength - p_hal_data->USBALLDummyLength; #endif - BufAddr = pBuf->Buffer.VirtualAddress + DescLen; - - ConstructVHTNDPAPacket( - pDM_Odm, - RA, - AID, - BufAddr, - &BufLen, - BW - ); - - pTcb->PacketLength = BufLen + DescLen; - - pTcb->bTxEnableSwCalcDur = TRUE; - - pTcb->BWOfPacket = BW; - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS) || phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) - pTcb->G_ID = 63; - - pTcb->P_AID = pBeamformEntry->P_AID; - pTcb->DataRate = NDPTxRate; /*decide by Nr*/ - - Adapter->HalFunc.CmdSendPacketHandler(Adapter, pTcb, pBuf, pTcb->PacketLength, DESC_PACKET_TYPE_NORMAL, FALSE); + buf_addr = p_buf->Buffer.VirtualAddress + desc_len; + + construct_vht_ndpa_packet( + p_dm_odm, + RA, + AID, + buf_addr, + &buf_len, + BW + ); + + p_tcb->PacketLength = buf_len + desc_len; + + p_tcb->bTxEnableSwCalcDur = true; + + p_tcb->BWOfPacket = BW; + + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss) || phydm_acting_determine(p_dm_odm, phydm_acting_as_ap)) + p_tcb->G_ID = 63; + + p_tcb->P_AID = p_beamform_entry->p_aid; + p_tcb->DataRate = ndp_tx_rate; /*decide by nr*/ + + adapter->HalFunc.CmdSendPacketHandler(adapter, p_tcb, p_buf, p_tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false); } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, ret=%d\n", __func__, ret)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, ret=%d\n", __func__, ret)); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); return ret; } -BOOLEAN -SendSWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ) +boolean +send_sw_vht_ndpa_packet( + void *p_dm_void, + u8 *RA, + u16 AID, + CHANNEL_WIDTH BW +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u1Byte Idx = 0, NDPTxRate = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { - ConstructVHTNDPAPacket( - pDM_Odm, - RA, - AID, - pBuf->Buffer.VirtualAddress, - &pTcb->PacketLength, - BW - ); - - pTcb->bTxEnableSwCalcDur = TRUE; - pTcb->BWOfPacket = BW; - - /*rate of NDP decide by Nr*/ - MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + PRT_TCB p_tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 idx = 0, ndp_tx_rate = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + construct_vht_ndpa_packet( + p_dm_odm, + RA, + AID, + p_buf->Buffer.VirtualAddress, + &p_tcb->PacketLength, + BW + ); + + p_tcb->bTxEnableSwCalcDur = true; + p_tcb->BWOfPacket = BW; + + /*rate of NDP decide by nr*/ + MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); return ret; } @@ -471,75 +485,75 @@ SendSWVHTNDPAPacket( #ifdef SUPPORT_MU_BF #if (SUPPORT_MU_BF == 1) /* -// Description: On VHT GID management frame by an MU beamformee. -// -// 2015.05.20. Created by tynli. -*/ -RT_STATUS -Beamforming_GetVHTGIDMgntFrame( - IN PADAPTER Adapter, - IN PRT_RFD pRfd, - IN POCTET_STRING pPduOS - ) + * Description: On VHT GID management frame by an MU beamformee. + * + * 2015.05.20. Created by tynli. + */ +enum rt_status +beamforming_get_vht_gid_mgnt_frame( + struct _ADAPTER *adapter, + PRT_RFD p_rfd, + POCTET_STRING p_pdu_os +) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - RT_STATUS rtStatus = RT_STATUS_SUCCESS; - pu1Byte pBuffer = NULL; - pu1Byte pRaddr = NULL; - u1Byte MemStatus[8] = {0}, UserPos[16] = {0}; - u1Byte idx; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMER_ENTRY pBeamformEntry = &pBeamInfo->BeamformerEntry[pBeamInfo->mu_ap_index]; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] On VHT GID mgnt frame!\n", __func__)); + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + enum rt_status rt_status = RT_STATUS_SUCCESS; + u8 *p_buffer = NULL; + u8 *p_raddr = NULL; + u8 mem_status[8] = {0}, user_pos[16] = {0}; + u8 idx; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_BEAMFORMER_ENTRY *p_beamform_entry = &p_beam_info->beamformer_entry[p_beam_info->mu_ap_index]; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] On VHT GID mgnt frame!\n", __func__)); /* Check length*/ - if (pPduOS->Length < (FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY+16)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Beamforming_GetVHTGIDMgntFrame(): Invalid length (%d)\n", pPduOS->Length)); + if (p_pdu_os->length < (FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY + 16)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("beamforming_get_vht_gid_mgnt_frame(): Invalid length (%d)\n", p_pdu_os->length)); return RT_STATUS_INVALID_LENGTH; } /* Check RA*/ - pRaddr = (pu1Byte)(pPduOS->Octet)+4; - if (!eqMacAddr(pRaddr, Adapter->CurrentAddress)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Beamforming_GetVHTGIDMgntFrame(): Drop because of RA error.\n")); + p_raddr = (u8 *)(p_pdu_os->Octet) + 4; + if (!eq_mac_addr(p_raddr, adapter->CurrentAddress)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("beamforming_get_vht_gid_mgnt_frame(): Drop because of RA error.\n")); return RT_STATUS_PKT_DROP; } - RT_DISP_DATA(FBEAM, FBEAM_DATA, "On VHT GID Mgnt Frame ==>:\n", pPduOS->Octet, pPduOS->Length); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "On VHT GID Mgnt Frame ==>:\n", p_pdu_os->Octet, p_pdu_os->length); - /*Parsing Membership Status Array*/ - pBuffer = pPduOS->Octet + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY; + /*Parsing Membership status array*/ + p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY; for (idx = 0; idx < 8; idx++) { - MemStatus[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(pBuffer+idx); - pBeamformEntry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(pBuffer+idx); + mem_status[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx); + p_beamform_entry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx); } - RT_DISP_DATA(FBEAM, FBEAM_DATA, "MemStatus: ", MemStatus, 8); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "mem_status: ", mem_status, 8); - /* Parsing User Position Array*/ - pBuffer = pPduOS->Octet + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY; + /* Parsing User Position array*/ + p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY; for (idx = 0; idx < 16; idx++) { - UserPos[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(pBuffer+idx); - pBeamformEntry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(pBuffer+idx); + user_pos[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx); + p_beamform_entry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx); } - RT_DISP_DATA(FBEAM, FBEAM_DATA, "UserPos: ", UserPos, 16); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "user_pos: ", user_pos, 16); /* Group ID detail printed*/ { - u1Byte i, j; - u1Byte tmpVal; - u2Byte tmpVal2; + u8 i, j; + u8 tmp_val; + u16 tmp_val2; for (i = 0; i < 8; i++) { - tmpVal = MemStatus[i]; - tmpVal2 = ((UserPos[i*2 + 1] << 8) & 0xFF00) + (UserPos[i * 2] & 0xFF); + tmp_val = mem_status[i]; + tmp_val2 = ((user_pos[i * 2 + 1] << 8) & 0xFF00) + (user_pos[i * 2] & 0xFF); for (j = 0; j < 8; j++) { - if ((tmpVal >> j) & BIT0) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Use Group ID (%d), User Position (%d)\n", - (i*8+j), (tmpVal2 >> 2 * j)&0x3)); + if ((tmp_val >> j) & BIT(0)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Use Group ID (%d), User Position (%d)\n", + (i * 8 + j), (tmp_val2 >> 2 * j) & 0x3)); } } } @@ -547,198 +561,198 @@ Beamforming_GetVHTGIDMgntFrame( /* Indicate GID frame to IHV service. */ { - u1Byte Indibuffer[24] = {0}; - u1Byte Indioffset = 0; - - PlatformMoveMemory(Indibuffer + Indioffset, pBeamformEntry->gid_valid, 8); - Indioffset += 8; - PlatformMoveMemory(Indibuffer + Indioffset, pBeamformEntry->user_position, 16); - Indioffset += 16; + u8 indibuffer[24] = {0}; + u8 indioffset = 0; + + PlatformMoveMemory(indibuffer + indioffset, p_beamform_entry->gid_valid, 8); + indioffset += 8; + PlatformMoveMemory(indibuffer + indioffset, p_beamform_entry->user_position, 16); + indioffset += 16; PlatformIndicateCustomStatus( - Adapter, + adapter, RT_CUSTOM_EVENT_VHT_RECV_GID_MGNT_FRAME, RT_CUSTOM_INDI_TARGET_IHV, - Indibuffer, - Indioffset); + indibuffer, + indioffset); } /* Config HW GID table */ - halComTxbf_ConfigGtab(pDM_Odm); + hal_com_txbf_config_gtab(p_dm_odm); - return rtStatus; + return rt_status; } /* -// Description: Construct VHT Group ID (GID) management frame. -// -// 2015.05.20. Created by tynli. -*/ -VOID -ConstructVHTGIDMgntFrame( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte RA, - IN PRT_BEAMFORMEE_ENTRY pBeamformEntry, - OUT pu1Byte Buffer, - OUT pu4Byte pLength - + * Description: Construct VHT Group ID (GID) management frame. + * + * 2015.05.20. Created by tynli. + */ +void +construct_vht_gid_mgnt_frame( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *RA, + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry, + u8 *buffer, + u32 *p_length + ) { - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - OCTET_STRING osFTMFrame, tmp; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _ADAPTER *adapter = p_beam_info->source_adapter; + OCTET_STRING os_ftm_frame, tmp; - FillOctetString(osFTMFrame, Buffer, 0); - *pLength = 0; + FillOctetString(os_ftm_frame, buffer, 0); + *p_length = 0; ConstructMaFrameHdr( - Adapter, - RA, - ACT_CAT_VHT, - ACT_VHT_GROUPID_MANAGEMENT, - &osFTMFrame); + adapter, + RA, + ACT_CAT_VHT, + ACT_VHT_GROUPID_MANAGEMENT, + &os_ftm_frame); - /* Membership Status Array*/ - FillOctetString(tmp, pBeamformEntry->gid_valid, 8); - PacketAppendData(&osFTMFrame, tmp); + /* Membership status array*/ + FillOctetString(tmp, p_beamform_entry->gid_valid, 8); + PacketAppendData(&os_ftm_frame, tmp); - /* User Position Array*/ - FillOctetString(tmp, pBeamformEntry->user_position, 16); - PacketAppendData(&osFTMFrame, tmp); + /* User Position array*/ + FillOctetString(tmp, p_beamform_entry->user_position, 16); + PacketAppendData(&os_ftm_frame, tmp); - *pLength = osFTMFrame.Length; + *p_length = os_ftm_frame.length; - RT_DISP_DATA(FBEAM, FBEAM_DATA, "ConstructVHTGIDMgntFrame():\n", Buffer, *pLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "construct_vht_gid_mgnt_frame():\n", buffer, *p_length); } -BOOLEAN -SendSWVHTGIDMgntFrame( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u1Byte Idx - ) +boolean +send_sw_vht_gid_mgnt_frame( + void *p_dm_void, + u8 *RA, + u8 idx +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u1Byte DataRate = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = &pBeamInfo->BeamformeeEntry[Idx]; - PADAPTER Adapter = pBeamInfo->SourceAdapter; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { - ConstructVHTGIDMgntFrame( - pDM_Odm, - RA, - pBeamformEntry, - pBuf->Buffer.VirtualAddress, - &pTcb->PacketLength - ); - - pTcb->BWOfPacket = CHANNEL_WIDTH_20; - DataRate = MGN_6M; - MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, DataRate); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + PRT_TCB p_tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 data_rate = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = &p_beam_info->beamformee_entry[idx]; + struct _ADAPTER *adapter = p_beam_info->source_adapter; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + construct_vht_gid_mgnt_frame( + p_dm_odm, + RA, + p_beamform_entry, + p_buf->Buffer.VirtualAddress, + &p_tcb->PacketLength + ); + + p_tcb->bw_of_packet = CHANNEL_WIDTH_20; + data_rate = MGN_6M; + MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, data_rate); } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); return ret; } /* -// Description: Construct VHT beamforming report poll. -// -// 2015.05.20. Created by tynli. -*/ -VOID -ConstructVHTBFReportPoll( - IN PDM_ODM_T pDM_Odm, - IN pu1Byte RA, - OUT pu1Byte Buffer, - OUT pu4Byte pLength + * Description: Construct VHT beamforming report poll. + * + * 2015.05.20. Created by tynli. + */ +void +construct_vht_bf_report_poll( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *RA, + u8 *buffer, + u32 *p_length ) { - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - pu1Byte pBFRptPoll = Buffer; - + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _ADAPTER *adapter = p_beam_info->source_adapter; + u8 *p_bf_rpt_poll = buffer; + /* Frame control*/ - SET_80211_HDR_FRAME_CONTROL(pBFRptPoll, 0); - SET_80211_HDR_TYPE_AND_SUBTYPE(pBFRptPoll, Type_Beamforming_Report_Poll); + SET_80211_HDR_FRAME_CONTROL(p_bf_rpt_poll, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(p_bf_rpt_poll, Type_Beamforming_Report_Poll); - /* Duration*/ - SET_80211_HDR_DURATION(pBFRptPoll, 100); + /* duration*/ + SET_80211_HDR_DURATION(p_bf_rpt_poll, 100); /* RA*/ - SET_VHT_BF_REPORT_POLL_RA(pBFRptPoll, RA); + SET_VHT_BF_REPORT_POLL_RA(p_bf_rpt_poll, RA); /* TA*/ - SET_VHT_BF_REPORT_POLL_TA(pBFRptPoll, Adapter->CurrentAddress); + SET_VHT_BF_REPORT_POLL_TA(p_bf_rpt_poll, adapter->CurrentAddress); /* Feedback Segment Retransmission Bitmap*/ - SET_VHT_BF_REPORT_POLL_FEEDBACK_SEG_RETRAN_BITMAP(pBFRptPoll, 0xFF); + SET_VHT_BF_REPORT_POLL_FEEDBACK_SEG_RETRAN_BITMAP(p_bf_rpt_poll, 0xFF); - *pLength = 17; + *p_length = 17; - RT_DISP_DATA(FBEAM, FBEAM_DATA, "ConstructVHTBFReportPoll():\n", Buffer, *pLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "construct_vht_bf_report_poll():\n", buffer, *p_length); } -BOOLEAN -SendSWVHTBFReportPoll( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN BOOLEAN bFinalPoll - ) +boolean +send_sw_vht_bf_report_poll( + void *p_dm_void, + u8 *RA, + boolean is_final_poll +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u1Byte Idx = 0, DataRate = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { - ConstructVHTBFReportPoll( - pDM_Odm, - RA, - pBuf->Buffer.VirtualAddress, - &pTcb->PacketLength - ); - - pTcb->bTxEnableSwCalcDur = TRUE; /* need?*/ - pTcb->BWOfPacket = CHANNEL_WIDTH_20; - - if (bFinalPoll) - pTcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + PRT_TCB p_tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 idx = 0, data_rate = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct _ADAPTER *adapter = p_beam_info->source_adapter; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + construct_vht_bf_report_poll( + p_dm_odm, + RA, + p_buf->Buffer.VirtualAddress, + &p_tcb->PacketLength + ); + + p_tcb->bTxEnableSwCalcDur = true; /* need?*/ + p_tcb->BWOfPacket = CHANNEL_WIDTH_20; + + if (is_final_poll) + p_tcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL; else - pTcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL; - - DataRate = MGN_6M; /* Legacy OFDM rate*/ - MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, DataRate); + p_tcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL; + + data_rate = MGN_6M; /* Legacy OFDM rate*/ + MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, data_rate); } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "SendSWVHTBFReportPoll():\n", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "send_sw_vht_bf_report_poll():\n", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); return ret; @@ -746,243 +760,243 @@ SendSWVHTBFReportPoll( /* -// Description: Construct VHT MU NDPA packet. -// We should combine this function with ConstructVHTNDPAPacket() in the future. -// -// 2015.05.21. Created by tynli. -*/ -VOID -ConstructVHTMUNDPAPacket( - IN PDM_ODM_T pDM_Odm, - IN CHANNEL_WIDTH BW, - OUT pu1Byte Buffer, - OUT pu4Byte pLength - ) -{ - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - u2Byte Duration = 0; - u1Byte Sequence = 0; - pu1Byte pNDPAFrame = Buffer; - RT_NDPA_STA_INFO STAInfo; - u1Byte idx; - u1Byte DestAddr[6] = {0}; - PRT_BEAMFORMEE_ENTRY pEntry = NULL; + * Description: Construct VHT MU NDPA packet. + * We should combine this function with construct_vht_ndpa_packet() in the future. + * + * 2015.05.21. Created by tynli. + */ +void +construct_vht_mu_ndpa_packet( + struct PHY_DM_STRUCT *p_dm_odm, + CHANNEL_WIDTH BW, + u8 *buffer, + u32 *p_length +) +{ + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _ADAPTER *adapter = p_beam_info->source_adapter; + u16 duration = 0; + u8 sequence = 0; + u8 *p_ndpa_frame = buffer; + struct _RT_NDPA_STA_INFO sta_info; + u8 idx; + u8 dest_addr[6] = {0}; + struct _RT_BEAMFORMEE_ENTRY *p_entry = NULL; /* Fill the first MU BFee entry (STA1) MAC addr to destination address then HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - pEntry = &(pBeamInfo->BeamformeeEntry[idx]); - if (pEntry->is_mu_sta) { - cpMacAddr(DestAddr, pEntry->MacAddr); + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + p_entry = &(p_beam_info->beamformee_entry[idx]); + if (p_entry->is_mu_sta) { + cp_mac_addr(dest_addr, p_entry->mac_addr); break; } } - if (pEntry == NULL) + if (p_entry == NULL) return; - + /* Frame control.*/ - SET_80211_HDR_FRAME_CONTROL(pNDPAFrame, 0); - SET_80211_HDR_TYPE_AND_SUBTYPE(pNDPAFrame, Type_NDPA); + SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA); - SET_80211_HDR_ADDRESS1(pNDPAFrame, DestAddr); - SET_80211_HDR_ADDRESS2(pNDPAFrame, pEntry->MyMacAddr); + SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr); + SET_80211_HDR_ADDRESS2(p_ndpa_frame, p_entry->my_mac_addr); /*--------------------------------------------*/ - /* Need to modify "Duration" to MU consideration. */ - Duration = 2*aSifsTime + 44; - + /* Need to modify "duration" to MU consideration. */ + duration = 2 * a_SifsTime + 44; + if (BW == CHANNEL_WIDTH_80) - Duration += 40; - else if(BW == CHANNEL_WIDTH_40) - Duration+= 87; - else - Duration+= 180; + duration += 40; + else if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; /*--------------------------------------------*/ - SET_80211_HDR_DURATION(pNDPAFrame, Duration); + SET_80211_HDR_DURATION(p_ndpa_frame, duration); - Sequence = *(pDM_Odm->pSoundingSeq) << 2; - ODM_MoveMemory(pDM_Odm, pNDPAFrame + 16, &Sequence, 1); + sequence = *(p_dm_odm->p_sounding_seq) << 2; + odm_move_memory(p_dm_odm, p_ndpa_frame + 16, &sequence, 1); - *pLength = 17; + *p_length = 17; /* Construct STA info. for multiple STAs*/ - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - pEntry = &(pBeamInfo->BeamformeeEntry[idx]); - if (pEntry->is_mu_sta) { - STAInfo.AID = pEntry->AID; - STAInfo.FeedbackType = 1; /* 1'b1: MU*/ - STAInfo.NcIndex = 0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BeamformeeEntry idx(%d), AID =%d\n", __func__, idx, pEntry->AID)); - - ODM_MoveMemory(pDM_Odm, pNDPAFrame+(*pLength), (pu1Byte)&STAInfo, 2); - *pLength += 2; + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + p_entry = &(p_beam_info->beamformee_entry[idx]); + if (p_entry->is_mu_sta) { + sta_info.aid = p_entry->AID; + sta_info.feedback_type = 1; /* 1'b1: MU*/ + sta_info.nc_index = 0; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get beamformee_entry idx(%d), AID =%d\n", __func__, idx, p_entry->AID)); + + odm_move_memory(p_dm_odm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2); + *p_length += 2; } } } -BOOLEAN -SendSWVHTMUNDPAPacket( - IN PVOID pDM_VOID, - IN CHANNEL_WIDTH BW - ) +boolean +send_sw_vht_mu_ndpa_packet( + void *p_dm_void, + CHANNEL_WIDTH BW +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u1Byte NDPTxRate = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - - NDPTxRate = MGN_VHT2SS_MCS0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { - ConstructVHTMUNDPAPacket( - pDM_Odm, - BW, - pBuf->Buffer.VirtualAddress, - &pTcb->PacketLength - ); - - pTcb->bTxEnableSwCalcDur = TRUE; - pTcb->BWOfPacket = BW; - pTcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA; - - /*rate of NDP decide by Nr*/ - MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + PRT_TCB p_tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 ndp_tx_rate = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _ADAPTER *adapter = p_beam_info->source_adapter; + + ndp_tx_rate = MGN_VHT2SS_MCS0; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + construct_vht_mu_ndpa_packet( + p_dm_odm, + BW, + p_buf->Buffer.VirtualAddress, + &p_tcb->PacketLength + ); + + p_tcb->bTxEnableSwCalcDur = true; + p_tcb->BWOfPacket = BW; + p_tcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA; + + /*rate of NDP decide by nr*/ + MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); return ret; } -VOID -DBG_ConstructVHTMUNDPAPacket( - IN PDM_ODM_T pDM_Odm, - IN CHANNEL_WIDTH BW, - OUT pu1Byte Buffer, - OUT pu4Byte pLength - ) -{ - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - u2Byte Duration = 0; - u1Byte Sequence = 0; - pu1Byte pNDPAFrame = Buffer; - RT_NDPA_STA_INFO STAInfo; - u1Byte idx; - u1Byte DestAddr[6] = {0}; - PRT_BEAMFORMEE_ENTRY pEntry = NULL; +void +dbg_construct_vht_mundpa_packet( + struct PHY_DM_STRUCT *p_dm_odm, + CHANNEL_WIDTH BW, + u8 *buffer, + u32 *p_length +) +{ + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _ADAPTER *adapter = p_beam_info->source_adapter; + u16 duration = 0; + u8 sequence = 0; + u8 *p_ndpa_frame = buffer; + struct _RT_NDPA_STA_INFO sta_info; + u8 idx; + u8 dest_addr[6] = {0}; + struct _RT_BEAMFORMEE_ENTRY *p_entry = NULL; - BOOLEAN is_STA1 = FALSE; + boolean is_STA1 = false; /* Fill the first MU BFee entry (STA1) MAC addr to destination address then HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - pEntry = &(pBeamInfo->BeamformeeEntry[idx]); - if (pEntry->is_mu_sta) { - if (is_STA1 == FALSE) { - is_STA1 = TRUE; + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + p_entry = &(p_beam_info->beamformee_entry[idx]); + if (p_entry->is_mu_sta) { + if (is_STA1 == false) { + is_STA1 = true; continue; } else { - cpMacAddr(DestAddr, pEntry->MacAddr); + cp_mac_addr(dest_addr, p_entry->mac_addr); break; } } } /* Frame control.*/ - SET_80211_HDR_FRAME_CONTROL(pNDPAFrame, 0); - SET_80211_HDR_TYPE_AND_SUBTYPE(pNDPAFrame, Type_NDPA); + SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA); - SET_80211_HDR_ADDRESS1(pNDPAFrame, DestAddr); - SET_80211_HDR_ADDRESS2(pNDPAFrame, pDM_Odm->CurrentAddress); + SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr); + SET_80211_HDR_ADDRESS2(p_ndpa_frame, p_dm_odm->CurrentAddress); /*--------------------------------------------*/ - /* Need to modify "Duration" to MU consideration. */ - Duration = 2*aSifsTime + 44; - + /* Need to modify "duration" to MU consideration. */ + duration = 2 * a_SifsTime + 44; + if (BW == CHANNEL_WIDTH_80) - Duration += 40; + duration += 40; else if (BW == CHANNEL_WIDTH_40) - Duration += 87; - else - Duration += 180; + duration += 87; + else + duration += 180; /*--------------------------------------------*/ - SET_80211_HDR_DURATION(pNDPAFrame, Duration); + SET_80211_HDR_DURATION(p_ndpa_frame, duration); - Sequence = *(pDM_Odm->pSoundingSeq) << 2; - ODM_MoveMemory(pDM_Odm, pNDPAFrame + 16, &Sequence, 1); + sequence = *(p_dm_odm->p_sounding_seq) << 2; + odm_move_memory(p_dm_odm, p_ndpa_frame + 16, &sequence, 1); - *pLength = 17; + *p_length = 17; /*STA2's STA Info*/ - STAInfo.AID = pEntry->AID; - STAInfo.FeedbackType = 1; /* 1'b1: MU */ - STAInfo.NcIndex = 0; + sta_info.aid = p_entry->aid; + sta_info.feedback_type = 1; /* 1'b1: MU */ + sta_info.nc_index = 0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BeamformeeEntry idx(%d), AID =%d\n", __func__, idx, pEntry->AID)); - - ODM_MoveMemory(pDM_Odm, pNDPAFrame+(*pLength), (pu1Byte)&STAInfo, 2); - *pLength += 2; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get beamformee_entry idx(%d), AID =%d\n", __func__, idx, p_entry->aid)); + + odm_move_memory(p_dm_odm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2); + *p_length += 2; } -BOOLEAN -DBG_SendSWVHTMUNDPAPacket( - IN PVOID pDM_VOID, - IN CHANNEL_WIDTH BW - ) +boolean +dbg_send_sw_vht_mundpa_packet( + void *p_dm_void, + CHANNEL_WIDTH BW +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN ret = TRUE; - u1Byte NDPTxRate = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PADAPTER Adapter = pBeamInfo->SourceAdapter; - - NDPTxRate = MGN_VHT2SS_MCS0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { - DBG_ConstructVHTMUNDPAPacket( - pDM_Odm, - BW, - pBuf->Buffer.VirtualAddress, - &pTcb->PacketLength - ); - - pTcb->bTxEnableSwCalcDur = TRUE; - pTcb->BWOfPacket = BW; - pTcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA; - - /*rate of NDP decide by Nr*/ - MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + PRT_TCB p_tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 ndp_tx_rate = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _ADAPTER *adapter = p_beam_info->source_adapter; + + ndp_tx_rate = MGN_VHT2SS_MCS0; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + dbg_construct_vht_mundpa_packet( + p_dm_odm, + BW, + p_buf->Buffer.VirtualAddress, + &p_tcb->PacketLength + ); + + p_tcb->bTxEnableSwCalcDur = true; + p_tcb->BWOfPacket = BW; + p_tcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA; + + /*rate of NDP decide by nr*/ + MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); } else - ret = FALSE; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); return ret; } @@ -994,74 +1008,74 @@ DBG_SendSWVHTMUNDPAPacket( #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -u4Byte -Beamforming_GetReportFrame( - IN PVOID pDM_VOID, +u32 +beamforming_get_report_frame( + void *p_dm_void, union recv_frame *precv_frame - ) +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u4Byte ret = _SUCCESS; - PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; - pu1Byte pframe = precv_frame->u.hdr.rx_data; - u4Byte frame_len = precv_frame->u.hdr.len; - pu1Byte TA; - u1Byte Idx, offset; - + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 ret = _SUCCESS; + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; + u8 *pframe = precv_frame->u.hdr.rx_data; + u32 frame_len = precv_frame->u.hdr.len; + u8 *TA; + u8 idx, offset; + /*Memory comparison to see if CSI report is the same with previous one*/ - TA = GetAddr2Ptr(pframe); - pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, TA, &Idx); - if(pBeamformEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) - offset = 31; /*24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/ - else if(pBeamformEntry->BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT) - offset = 34; /*24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/ + TA = get_addr2_ptr(pframe); + p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, TA, &idx); + if (p_beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) + offset = 31; /*24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/ + else if (p_beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) + offset = 34; /*24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/ else return ret; - + return ret; } -BOOLEAN -SendFWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ) +boolean +send_fw_ht_ndpa_packet( + void *p_dm_void, + u8 *RA, + CHANNEL_WIDTH BW +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u1Byte ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; - u1Byte *pframe; - u2Byte *fctrl; - u2Byte duration = 0; - u1Byte aSifsTime = 0, NDPTxRate = 0, Idx = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); pmgntframe = alloc_mgtxmitframe(pxmitpriv); - + if (pmgntframe == NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); return _FALSE; } - //update attribute + /* update attribute */ pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(Adapter, pattrib); + update_mgntframe_attrib(adapter, pattrib); pattrib->qsel = QSLT_BEACON; - NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - pattrib->rate = NDPTxRate; + ndp_tx_rate = beamforming_get_htndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + pattrib->rate = ndp_tx_rate; pattrib->bwmode = BW; pattrib->order = 1; pattrib->subtype = WIFI_ACTION_NOACK; @@ -1070,85 +1084,85 @@ SendFWHTNDPAPacket( pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; fctrl = &pwlanhdr->frame_ctl; *(fctrl) = 0; - SetOrderBit(pframe); - SetFrameSubType(pframe, WIFI_ACTION_NOACK); + set_order_bit(pframe); + set_frame_sub_type(pframe, WIFI_ACTION_NOACK); _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, p_beamform_entry->my_mac_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - if( pmlmeext->cur_wireless_mode == WIRELESS_11B) - aSifsTime = 10; + if (pmlmeext->cur_wireless_mode == WIRELESS_11B) + a_sifs_time = 10; else - aSifsTime = 16; + a_sifs_time = 16; - duration = 2*aSifsTime + 40; - - if(BW == CHANNEL_WIDTH_40) - duration+= 87; - else - duration+= 180; + duration = 2 * a_sifs_time + 40; - SetDuration(pframe, duration); + if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; - //HT control field - SET_HT_CTRL_CSI_STEERING(pframe+24, 3); - SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe+24, 1); + set_duration(pframe, duration); - _rtw_memcpy(pframe+28, ActionHdr, 4); + /* HT control field */ + SET_HT_CTRL_CSI_STEERING(pframe + 24, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1); + + _rtw_memcpy(pframe + 28, action_hdr, 4); pattrib->pktlen = 32; pattrib->last_txcmdsz = pattrib->pktlen; - dump_mgntframe(Adapter, pmgntframe); + dump_mgntframe(adapter, pmgntframe); return _TRUE; } -BOOLEAN -SendSWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ) +boolean +send_sw_ht_ndpa_packet( + void *p_dm_void, + u8 *RA, + CHANNEL_WIDTH BW +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u1Byte ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; - pu1Byte pframe; - pu2Byte fctrl; - u2Byte duration = 0; - u1Byte aSifsTime = 0, NDPTxRate = 0, Idx = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - + u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + + ndp_tx_rate = beamforming_get_htndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); + pmgntframe = alloc_mgtxmitframe(pxmitpriv); - + if (pmgntframe == NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); return _FALSE; } /*update attribute*/ pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(Adapter, pattrib); + update_mgntframe_attrib(adapter, pattrib); pattrib->qsel = QSLT_MGNT; - pattrib->rate = NDPTxRate; + pattrib->rate = ndp_tx_rate; pattrib->bwmode = BW; pattrib->order = 1; pattrib->subtype = WIFI_ACTION_NOACK; @@ -1162,84 +1176,84 @@ SendSWHTNDPAPacket( fctrl = &pwlanhdr->frame_ctl; *(fctrl) = 0; - SetOrderBit(pframe); - SetFrameSubType(pframe, WIFI_ACTION_NOACK); + set_order_bit(pframe); + set_frame_sub_type(pframe, WIFI_ACTION_NOACK); _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, p_beamform_entry->my_mac_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); if (pmlmeext->cur_wireless_mode == WIRELESS_11B) - aSifsTime = 10; + a_sifs_time = 10; else - aSifsTime = 16; + a_sifs_time = 16; + + duration = 2 * a_sifs_time + 40; - duration = 2*aSifsTime + 40; - if (BW == CHANNEL_WIDTH_40) duration += 87; - else + else duration += 180; - SetDuration(pframe, duration); + set_duration(pframe, duration); /*HT control field*/ - SET_HT_CTRL_CSI_STEERING(pframe+24, 3); - SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe+24, 1); + SET_HT_CTRL_CSI_STEERING(pframe + 24, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1); - _rtw_memcpy(pframe+28, ActionHdr, 4); + _rtw_memcpy(pframe + 28, action_hdr, 4); pattrib->pktlen = 32; pattrib->last_txcmdsz = pattrib->pktlen; - dump_mgntframe(Adapter, pmgntframe); + dump_mgntframe(adapter, pmgntframe); return _TRUE; } -BOOLEAN -SendFWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ) +boolean +send_fw_vht_ndpa_packet( + void *p_dm_void, + u8 *RA, + u16 AID, + CHANNEL_WIDTH BW +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); - pu1Byte pframe; - pu2Byte fctrl; - u2Byte duration = 0; - u1Byte sequence = 0, aSifsTime = 0, NDPTxRate= 0, Idx = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - RT_NDPA_STA_INFO sta_info; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 sequence = 0, a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct _RT_NDPA_STA_INFO sta_info; pmgntframe = alloc_mgtxmitframe(pxmitpriv); - + if (pmgntframe == NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); return _FALSE; } - //update attribute + /* update attribute */ pattrib = &pmgntframe->attrib; _rtw_memcpy(pattrib->ra, RA, ETH_ALEN); - update_mgntframe_attrib(Adapter, pattrib); + update_mgntframe_attrib(adapter, pattrib); pattrib->qsel = QSLT_BEACON; - NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); - pattrib->rate = NDPTxRate; + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + pattrib->rate = ndp_tx_rate; pattrib->bwmode = BW; pattrib->subtype = WIFI_NDPA; @@ -1247,101 +1261,101 @@ SendFWVHTNDPAPacket( pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; fctrl = &pwlanhdr->frame_ctl; *(fctrl) = 0; - SetFrameSubType(pframe, WIFI_NDPA); + set_frame_sub_type(pframe, WIFI_NDPA); _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, p_beamform_entry->my_mac_addr, ETH_ALEN); - if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode)) - aSifsTime = 16; + if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) + a_sifs_time = 16; else - aSifsTime = 10; + a_sifs_time = 10; + + duration = 2 * a_sifs_time + 44; - duration = 2*aSifsTime + 44; - - if(BW == CHANNEL_WIDTH_80) + if (BW == CHANNEL_WIDTH_80) duration += 40; - else if(BW == CHANNEL_WIDTH_40) - duration+= 87; - else - duration+= 180; + else if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; - SetDuration(pframe, duration); + set_duration(pframe, duration); - sequence = pBeamInfo->SoundingSequence<< 2; - if (pBeamInfo->SoundingSequence >= 0x3f) - pBeamInfo->SoundingSequence = 0; + sequence = p_beam_info->sounding_sequence << 2; + if (p_beam_info->sounding_sequence >= 0x3f) + p_beam_info->sounding_sequence = 0; else - pBeamInfo->SoundingSequence++; + p_beam_info->sounding_sequence++; - _rtw_memcpy(pframe+16, &sequence,1); + _rtw_memcpy(pframe + 16, &sequence, 1); - if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) - AID = 0; + if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) + AID = 0; - sta_info.AID = AID; - sta_info.FeedbackType = 0; - sta_info.NcIndex= 0; - - _rtw_memcpy(pframe+17, (u8 *)&sta_info, 2); + sta_info.aid = AID; + sta_info.feedback_type = 0; + sta_info.nc_index = 0; + + _rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2); pattrib->pktlen = 19; pattrib->last_txcmdsz = pattrib->pktlen; - dump_mgntframe(Adapter, pmgntframe); + dump_mgntframe(adapter, pmgntframe); return _TRUE; } -BOOLEAN -SendSWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ) +boolean +send_sw_vht_ndpa_packet( + void *p_dm_void, + u8 *RA, + u16 AID, + CHANNEL_WIDTH BW +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); - RT_NDPA_STA_INFO ndpa_sta_info; - u1Byte NDPTxRate = 0, sequence = 0, aSifsTime = 0, Idx = 0; - pu1Byte pframe; - pu2Byte fctrl; - u2Byte duration = 0; - PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); - PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); - - NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct _RT_NDPA_STA_INFO ndpa_sta_info; + u8 ndp_tx_rate = 0, sequence = 0, a_sifs_time = 0, idx = 0; + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); pmgntframe = alloc_mgtxmitframe(pxmitpriv); - + if (pmgntframe == NULL) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); return _FALSE; } - + /*update attribute*/ pattrib = &pmgntframe->attrib; _rtw_memcpy(pattrib->ra, RA, ETH_ALEN); - update_mgntframe_attrib(Adapter, pattrib); + update_mgntframe_attrib(adapter, pattrib); pattrib->qsel = QSLT_MGNT; - pattrib->rate = NDPTxRate; + pattrib->rate = ndp_tx_rate; pattrib->bwmode = BW; pattrib->subtype = WIFI_NDPA; @@ -1354,50 +1368,50 @@ SendSWVHTNDPAPacket( fctrl = &pwlanhdr->frame_ctl; *(fctrl) = 0; - SetFrameSubType(pframe, WIFI_NDPA); + set_frame_sub_type(pframe, WIFI_NDPA); _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, p_beamform_entry->my_mac_addr, ETH_ALEN); - if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode)) - aSifsTime = 16; + if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) + a_sifs_time = 16; else - aSifsTime = 10; + a_sifs_time = 10; + + duration = 2 * a_sifs_time + 44; - duration = 2*aSifsTime + 44; - if (BW == CHANNEL_WIDTH_80) duration += 40; else if (BW == CHANNEL_WIDTH_40) duration += 87; - else + else duration += 180; - SetDuration(pframe, duration); - - sequence = pBeamInfo->SoundingSequence << 2; - if (pBeamInfo->SoundingSequence >= 0x3f) - pBeamInfo->SoundingSequence = 0; + set_duration(pframe, duration); + + sequence = p_beam_info->sounding_sequence << 2; + if (p_beam_info->sounding_sequence >= 0x3f) + p_beam_info->sounding_sequence = 0; else - pBeamInfo->SoundingSequence++; + p_beam_info->sounding_sequence++; - _rtw_memcpy(pframe+16, &sequence, 1); - if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) - AID = 0; + _rtw_memcpy(pframe + 16, &sequence, 1); + if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) + AID = 0; + + ndpa_sta_info.aid = AID; + ndpa_sta_info.feedback_type = 0; + ndpa_sta_info.nc_index = 0; - ndpa_sta_info.AID = AID; - ndpa_sta_info.FeedbackType = 0; - ndpa_sta_info.NcIndex = 0; - - _rtw_memcpy(pframe+17, (u8 *)&ndpa_sta_info, 2); + _rtw_memcpy(pframe + 17, (u8 *)&ndpa_sta_info, 2); pattrib->pktlen = 19; pattrib->last_txcmdsz = pattrib->pktlen; - dump_mgntframe(Adapter, pmgntframe); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] [%d]\n", __func__, __LINE__)); - + dump_mgntframe(adapter, pmgntframe); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] [%d]\n", __func__, __LINE__)); + return _TRUE; } @@ -1405,96 +1419,96 @@ SendSWVHTNDPAPacket( #endif -VOID -Beamforming_GetNDPAFrame( - IN PVOID pDM_VOID, +void +beamforming_get_ndpa_frame( + void *p_dm_void, #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN OCTET_STRING pduOS + OCTET_STRING pdu_os #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) union recv_frame *precv_frame #endif ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - pu1Byte TA ; - u1Byte Idx, Sequence; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + u8 *TA ; + u8 idx, sequence; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - pu1Byte pNDPAFrame = pduOS.Octet; + u8 *p_ndpa_frame = pdu_os.Octet; #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - pu1Byte pNDPAFrame = precv_frame->u.hdr.rx_data; + u8 *p_ndpa_frame = precv_frame->u.hdr.rx_data; #endif - PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL; /*Modified By Jeffery @2014-10-29*/ - + struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry = NULL; /*Modified By Jeffery @2014-10-29*/ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "Beamforming_GetNDPAFrame\n", pduOS.Octet, pduOS.Length); - if (IsCtrlNDPA(pNDPAFrame) == FALSE) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "beamforming_get_ndpa_frame\n", pdu_os.Octet, pdu_os.Length); + if (IsCtrlNDPA(p_ndpa_frame) == false) #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (GetFrameSubType(pNDPAFrame) != WIFI_NDPA) + if (get_frame_sub_type(p_ndpa_frame) != WIFI_NDPA) #endif return; - else if (!(pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821))) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] not 8812 or 8821A, return\n", __func__)); + else if (!(p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] not 8812 or 8821A, return\n", __func__)); return; } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - TA = Frame_Addr2(pduOS); + TA = Frame_Addr2(pdu_os); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - TA = GetAddr2Ptr(pNDPAFrame); + TA = get_addr2_ptr(p_ndpa_frame); #endif /*Remove signaling TA. */ TA[0] = TA[0] & 0xFE; - - pBeamformerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, TA, &Idx); // Modified By Jeffery @2014-10-29 - /*Break options for Clock Reset*/ - if (pBeamformerEntry == NULL) + p_beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(p_dm_odm, TA, &idx); /* Modified By Jeffery @2014-10-29 */ + + /*Break options for Clock Reset*/ + if (p_beamformer_entry == NULL) return; - else if (!(pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU)) + else if (!(p_beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)) return; - /*LogSuccess: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/ - /*ClockResetTimes: While BFer entry always doesn't receive our CSI, clock will reset again and again.So ClockResetTimes is limited to 5 times.2015-04-13, Jeffery*/ - else if ((pBeamformerEntry->LogSuccess == 1) || (pBeamformerEntry->ClockResetTimes == 5)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] LogSeq=%d, PreLogSeq=%d, LogRetryCnt=%d, LogSuccess=%d, ClockResetTimes=%d, clock reset is no longer needed.\n", - __func__, pBeamformerEntry->LogSeq, pBeamformerEntry->PreLogSeq, pBeamformerEntry->LogRetryCnt, pBeamformerEntry->LogSuccess, pBeamformerEntry->ClockResetTimes)); + /*log_success: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/ + /*clock_reset_times: While BFer entry always doesn't receive our CSI, clock will reset again and again.So clock_reset_times is limited to 5 times.2015-04-13, Jeffery*/ + else if ((p_beamformer_entry->log_success == 1) || (p_beamformer_entry->clock_reset_times == 5)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, log_success=%d, clock_reset_times=%d, clock reset is no longer needed.\n", + __func__, p_beamformer_entry->log_seq, p_beamformer_entry->pre_log_seq, p_beamformer_entry->log_retry_cnt, p_beamformer_entry->log_success, p_beamformer_entry->clock_reset_times)); - return; + return; } - Sequence = (pNDPAFrame[16]) >> 2; + sequence = (p_ndpa_frame[16]) >> 2; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start, Sequence=%d, LogSeq=%d, PreLogSeq=%d, LogRetryCnt=%d, ClockResetTimes=%d, LogSuccess=%d\n", - __func__, Sequence, pBeamformerEntry->LogSeq, pBeamformerEntry->PreLogSeq, pBeamformerEntry->LogRetryCnt, pBeamformerEntry->ClockResetTimes, pBeamformerEntry->LogSuccess)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start, sequence=%d, log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, clock_reset_times=%d, log_success=%d\n", + __func__, sequence, p_beamformer_entry->log_seq, p_beamformer_entry->pre_log_seq, p_beamformer_entry->log_retry_cnt, p_beamformer_entry->clock_reset_times, p_beamformer_entry->log_success)); - if ((pBeamformerEntry->LogSeq != 0) && (pBeamformerEntry->PreLogSeq != 0)) { + if ((p_beamformer_entry->log_seq != 0) && (p_beamformer_entry->pre_log_seq != 0)) { /*Success condition*/ - if ((pBeamformerEntry->LogSeq != Sequence) && (pBeamformerEntry->PreLogSeq != pBeamformerEntry->LogSeq)) { + if ((p_beamformer_entry->log_seq != sequence) && (p_beamformer_entry->pre_log_seq != p_beamformer_entry->log_seq)) { /* break option for clcok reset, 2015-03-30, Jeffery */ - pBeamformerEntry->LogRetryCnt = 0; + p_beamformer_entry->log_retry_cnt = 0; /*As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/ - /*That is, LogSuccess is NOT needed to be reset to zero, 2015-04-13, Jeffery*/ - pBeamformerEntry->LogSuccess = 1; + /*That is, log_success is NOT needed to be reset to zero, 2015-04-13, Jeffery*/ + p_beamformer_entry->log_success = 1; } else {/*Fail condition*/ - if (pBeamformerEntry->LogRetryCnt == 5) { - pBeamformerEntry->ClockResetTimes++; - pBeamformerEntry->LogRetryCnt = 0; + if (p_beamformer_entry->log_retry_cnt == 5) { + p_beamformer_entry->clock_reset_times++; + p_beamformer_entry->log_retry_cnt = 0; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Clock Reset!!! ClockResetTimes=%d\n", - __func__, pBeamformerEntry->ClockResetTimes)); - HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_CLK, NULL); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Clock Reset!!! clock_reset_times=%d\n", + __func__, p_beamformer_entry->clock_reset_times)); + hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_CLK, NULL); } else - pBeamformerEntry->LogRetryCnt++; + p_beamformer_entry->log_retry_cnt++; } } - /*Update LogSeq & PreLogSeq*/ - pBeamformerEntry->PreLogSeq = pBeamformerEntry->LogSeq; - pBeamformerEntry->LogSeq = Sequence; - + /*Update log_seq & pre_log_seq*/ + p_beamformer_entry->pre_log_seq = p_beamformer_entry->log_seq; + p_beamformer_entry->log_seq = sequence; + } diff --git a/hal/phydm/txbf/haltxbfinterface.h b/hal/phydm/txbf/haltxbfinterface.h index 6f0b427..fcaae54 100644 --- a/hal/phydm/txbf/haltxbfinterface.h +++ b/hal/phydm/txbf/haltxbfinterface.h @@ -1,162 +1,179 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __HAL_TXBF_INTERFACE_H__ #define __HAL_TXBF_INTERFACE_H__ #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -Beamforming_GidPAid( - PADAPTER Adapter, - PRT_TCB pTcb - ); - -RT_STATUS -Beamforming_GetReportFrame( - IN PADAPTER Adapter, - IN PRT_RFD pRfd, - IN POCTET_STRING pPduOS - ); - -VOID -Beamforming_GetNDPAFrame( - IN PVOID pDM_VOID, - IN OCTET_STRING pduOS - ); - -BOOLEAN -SendFWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ); - -BOOLEAN -SendFWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ); - -BOOLEAN -SendSWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ); - -BOOLEAN -SendSWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ); + +#define a_SifsTime ((IS_WIRELESS_MODE_5G(adapter)|| IS_WIRELESS_MODE_N_24G(adapter))? 16 : 10) + +void +beamforming_gid_paid( + struct _ADAPTER *adapter, + PRT_TCB p_tcb +); + +enum rt_status +beamforming_get_report_frame( + struct _ADAPTER *adapter, + PRT_RFD p_rfd, + POCTET_STRING p_pdu_os +); + +void +beamforming_get_ndpa_frame( + void *p_dm_void, + OCTET_STRING pdu_os +); + +boolean +send_fw_ht_ndpa_packet( + void *p_dm_void, + u8 *RA, + CHANNEL_WIDTH BW +); + +boolean +send_fw_vht_ndpa_packet( + void *p_dm_void, + u8 *RA, + u16 AID, + CHANNEL_WIDTH BW +); + +boolean +send_sw_vht_ndpa_packet( + void *p_dm_void, + u8 *RA, + u16 AID, + CHANNEL_WIDTH BW +); + +boolean +send_sw_ht_ndpa_packet( + void *p_dm_void, + u8 *RA, + CHANNEL_WIDTH BW +); #if (SUPPORT_MU_BF == 1) -RT_STATUS -Beamforming_GetVHTGIDMgntFrame( - IN PADAPTER Adapter, - IN PRT_RFD pRfd, - IN POCTET_STRING pPduOS - ); - -BOOLEAN -SendSWVHTGIDMgntFrame( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u1Byte Idx - ); - -BOOLEAN -SendSWVHTBFReportPoll( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN BOOLEAN bFinalPoll - ); - -BOOLEAN -SendSWVHTMUNDPAPacket( - IN PVOID pDM_VOID, - IN CHANNEL_WIDTH BW - ); +enum rt_status +beamforming_get_vht_gid_mgnt_frame( + struct _ADAPTER *adapter, + PRT_RFD p_rfd, + POCTET_STRING p_pdu_os +); + +boolean +send_sw_vht_gid_mgnt_frame( + void *p_dm_void, + u8 *RA, + u8 idx +); + +boolean +send_sw_vht_bf_report_poll( + void *p_dm_void, + u8 *RA, + boolean is_final_poll +); + +boolean +send_sw_vht_mu_ndpa_packet( + void *p_dm_void, + CHANNEL_WIDTH BW +); #else -#define Beamforming_GetVHTGIDMgntFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE -#define SendSWVHTGIDMgntFrame(pDM_VOID, RA) -#define SendSWVHTBFReportPoll(pDM_VOID, RA, bFinalPoll) -#define SendSWVHTMUNDPAPacket(pDM_VOID, BW) +#define beamforming_get_vht_gid_mgnt_frame(adapter, p_rfd, p_pdu_os) RT_STATUS_FAILURE +#define send_sw_vht_gid_mgnt_frame(p_dm_void, RA) +#define send_sw_vht_bf_report_poll(p_dm_void, RA, is_final_poll) +#define send_sw_vht_mu_ndpa_packet(p_dm_void, BW) #endif #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -u4Byte -Beamforming_GetReportFrame( - IN PVOID pDM_VOID, +u32 +beamforming_get_report_frame( + void *p_dm_void, union recv_frame *precv_frame - ); - -BOOLEAN -SendFWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ); - -BOOLEAN -SendSWHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN CHANNEL_WIDTH BW - ); - -BOOLEAN -SendFWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ); - -BOOLEAN -SendSWVHTNDPAPacket( - IN PVOID pDM_VOID, - IN pu1Byte RA, - IN u2Byte AID, - IN CHANNEL_WIDTH BW - ); +); + +boolean +send_fw_ht_ndpa_packet( + void *p_dm_void, + u8 *RA, + CHANNEL_WIDTH BW +); + +boolean +send_sw_ht_ndpa_packet( + void *p_dm_void, + u8 *RA, + CHANNEL_WIDTH BW +); + +boolean +send_fw_vht_ndpa_packet( + void *p_dm_void, + u8 *RA, + u16 AID, + CHANNEL_WIDTH BW +); + +boolean +send_sw_vht_ndpa_packet( + void *p_dm_void, + u8 *RA, + u16 AID, + CHANNEL_WIDTH BW +); #endif -VOID -Beamforming_GetNDPAFrame( - IN PVOID pDM_VOID, +void +beamforming_get_ndpa_frame( + void *p_dm_void, #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - IN OCTET_STRING pduOS + OCTET_STRING pdu_os #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) union recv_frame *precv_frame #endif ); -BOOLEAN -DBG_SendSWVHTMUNDPAPacket( - IN PVOID pDM_VOID, - IN CHANNEL_WIDTH BW - ); +boolean +dbg_send_sw_vht_mundpa_packet( + void *p_dm_void, + CHANNEL_WIDTH BW +); #else -#define Beamforming_GetNDPAFrame(pDM_Odm, _PduOS) +#define beamforming_get_ndpa_frame(p_dm_odm, _pdu_os) #if (DM_ODM_SUPPORT_TYPE == ODM_CE) -#define Beamforming_GetReportFrame(Adapter, precv_frame) RT_STATUS_FAILURE + #define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#define Beamforming_GetReportFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE -#define Beamforming_GetVHTGIDMgntFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE + #define beamforming_get_report_frame(adapter, p_rfd, p_pdu_os) RT_STATUS_FAILURE + #define beamforming_get_vht_gid_mgnt_frame(adapter, p_rfd, p_pdu_os) RT_STATUS_FAILURE #endif -#define SendFWHTNDPAPacket(pDM_VOID, RA, BW) -#define SendSWHTNDPAPacket(pDM_VOID, RA, BW) -#define SendFWVHTNDPAPacket(pDM_VOID, RA, AID, BW) -#define SendSWVHTNDPAPacket(pDM_VOID, RA, AID, BW) -#define SendSWVHTGIDMgntFrame(pDM_VOID, RA, idx) -#define SendSWVHTBFReportPoll(pDM_VOID, RA, bFinalPoll) -#define SendSWVHTMUNDPAPacket(pDM_VOID, BW) +#define send_fw_ht_ndpa_packet(p_dm_void, RA, BW) +#define send_sw_ht_ndpa_packet(p_dm_void, RA, BW) +#define send_fw_vht_ndpa_packet(p_dm_void, RA, AID, BW) +#define send_sw_vht_ndpa_packet(p_dm_void, RA, AID, BW) +#define send_sw_vht_gid_mgnt_frame(p_dm_void, RA, idx) +#define send_sw_vht_bf_report_poll(p_dm_void, RA, is_final_poll) +#define send_sw_vht_mu_ndpa_packet(p_dm_void, BW) #endif #endif diff --git a/hal/phydm/txbf/haltxbfjaguar.c b/hal/phydm/txbf/haltxbfjaguar.c index e1651f6..4525771 100644 --- a/hal/phydm/txbf/haltxbfjaguar.c +++ b/hal/phydm/txbf/haltxbfjaguar.c @@ -1,468 +1,482 @@ -//============================================================ -// Description: -// -// This file is for 8812/8821/8811 TXBF mechanism -// -//============================================================ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for 8812/8821/8811 TXBF mechanism + * + * ************************************************************ */ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (BEAMFORMING_SUPPORT == 1) #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) -VOID -HalTxbf8812A_setNDPArate( - IN PVOID pDM_VOID, - IN u1Byte BW, - IN u1Byte Rate +void +hal_txbf_8812a_set_ndpa_rate( + void *p_dm_void, + u8 BW, + u8 rate ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8812A, (Rate << 2 | BW)); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8812A, (rate << 2 | BW)); } -VOID -halTxbfJaguar_RfMode( - IN PVOID pDM_VOID, - IN PRT_BEAMFORMING_INFO pBeamInfo +void +hal_txbf_jaguar_rf_mode( + void *p_dm_void, + struct _RT_BEAMFORMING_INFO *p_beam_info ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->RFType == ODM_1T1R) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->rf_type == ODM_1T1R) return; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set TxIQGen\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set TxIQGen\n", __func__)); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); /*RF mode table write enable*/ - if (pBeamInfo->beamformee_su_cnt > 0) { - // Paath_A - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ - // Path_B - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ + if (p_beam_info->beamformee_su_cnt > 0) { + /* Paath_A */ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ + /* Path_B */ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ } else { - // Paath_A - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ - // Path_B - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ + /* Paath_A */ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ + /* Path_B */ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ } - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); /*RF mode table write disable*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); /*RF mode table write disable*/ - if (pBeamInfo->beamformee_su_cnt > 0) - ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x33); + if (p_beam_info->beamformee_su_cnt > 0) + odm_set_bb_reg(p_dm_odm, 0x80c, MASKBYTE1, 0x33); else - ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x11); + odm_set_bb_reg(p_dm_odm, 0x80c, MASKBYTE1, 0x11); } -VOID -halTxbfJaguar_DownloadNDPA( - IN PVOID pDM_VOID, - IN u1Byte Idx +void +hal_txbf_jaguar_download_ndpa( + void *p_dm_void, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page; - u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; - BOOLEAN bSendBeacon = FALSE; - u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/ - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; - PADAPTER Adapter = pDM_Odm->Adapter; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 u1b_tmp = 0, tmp_reg422 = 0, head_page; + u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; + boolean is_send_beacon = false; + u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/ + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + struct _ADAPTER *adapter = p_dm_odm->adapter; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE; + *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true; #endif - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - if (Idx == 0) - Head_Page = 0xFE; + if (idx == 0) + head_page = 0xFE; else - Head_Page = 0xFE; + head_page = 0xFE; - Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy); + phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy); /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1); - ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp | BIT0)); + u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8812A + 1); + odm_write_1byte(p_dm_odm, REG_CR_8812A + 1, (u1b_tmp | BIT(0))); /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2); - ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422 & (~BIT6)); + tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8812A + 2); + odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6))); - if (tmpReg422 & BIT6) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("SetBeamformDownloadNDPA_8812(): There is an Adapter is sending beacon.\n")); - bSendBeacon = TRUE; + if (tmp_reg422 & BIT(6)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\n")); + is_send_beacon = true; } /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ - ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, Head_Page); + odm_write_1byte(p_dm_odm, REG_TDECTRL_8812A + 1, head_page); do { /*Clear beacon valid check bit.*/ - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); - ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 2, (BcnValidReg | BIT0)); + bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_TDECTRL_8812A + 2); + odm_write_1byte(p_dm_odm, REG_TDECTRL_8812A + 2, (bcn_valid_reg | BIT(0))); /*download NDPA rsvd page.*/ - if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) - Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); + if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) + beamforming_send_vht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->aid, p_beam_entry->sound_bw, BEACON_QUEUE); else - Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); + beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); /*check rsvd page download OK.*/ - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); + bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_TDECTRL_8812A + 2); count = 0; - while (!(BcnValidReg & BIT0) && count < 20) { + while (!(bcn_valid_reg & BIT(0)) && count < 20) { count++; ODM_delay_ms(10); - BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); + bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_TDECTRL_8812A + 2); } - DLBcnCount++; - } while (!(BcnValidReg & BIT0) && DLBcnCount < 5); + dl_bcn_count++; + } while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5); - if (!(BcnValidReg & BIT0)) - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); + if (!(bcn_valid_reg & BIT(0))) + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ - ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, TxPageBndy); + odm_write_1byte(p_dm_odm, REG_TDECTRL_8812A + 1, tx_page_bndy); /*To make sure that if there exists an adapter which would like to send beacon.*/ /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ /*the beacon cannot be sent by HW.*/ /*2010.06.23. Added by tynli.*/ - if (bSendBeacon) - ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422); + if (is_send_beacon) + odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422); /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1); - ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp & (~BIT0))); + u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8812A + 1); + odm_write_1byte(p_dm_odm, REG_CR_8812A + 1, (u1b_tmp & (~BIT(0)))); - pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; + p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE; + *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false; #endif } -VOID -halTxbfJaguar_FwTxBFCmd( - IN PVOID pDM_VOID +void +hal_txbf_jaguar_fw_txbf_cmd( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte Idx, Period0 = 0, Period1 = 0; - u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; - u1Byte u1TxBFParm[3] = {0}; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 idx, period0 = 0, period1 = 0; + u8 PageNum0 = 0xFF, PageNum1 = 0xFF; + u8 u1_tx_bf_parm[3] = {0}; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { /*Modified by David*/ - if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (Idx == 0) { - if (pBeamInfo->BeamformeeEntry[Idx].bSound) + if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (idx == 0) { + if (p_beam_info->beamformee_entry[idx].is_sound) PageNum0 = 0xFE; else PageNum0 = 0xFF; /*stop sounding*/ - Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); - } else if (Idx == 1) { - if (pBeamInfo->BeamformeeEntry[Idx].bSound) + period0 = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + } else if (idx == 1) { + if (p_beam_info->beamformee_entry[idx].is_sound) PageNum1 = 0xFE; else PageNum1 = 0xFF; /*stop sounding*/ - Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + period1 = (u8)(p_beam_info->beamformee_entry[idx].sound_period); } } } - u1TxBFParm[0] = PageNum0; - u1TxBFParm[1] = PageNum1; - u1TxBFParm[2] = (Period1 << 4) | Period0; - ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm); + u1_tx_bf_parm[0] = PageNum0; + u1_tx_bf_parm[1] = PageNum1; + u1_tx_bf_parm[2] = (period1 << 4) | period0; + odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, - ("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, + ("[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", __func__, PageNum0, period0, PageNum1, period1)); } -VOID -HalTxbfJaguar_Enter( - IN PVOID pDM_VOID, - IN u1Byte BFerBFeeIdx +void +hal_txbf_jaguar_enter( + void *p_dm_void, + u8 bfer_bfee_idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0; - u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; - u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); - u4Byte CSI_Param; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - RT_BEAMFORMER_ENTRY BeamformerEntry; - u2Byte STAid = 0; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!\n", __func__)); - - halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo); - - if (pDM_Odm->RFType == ODM_2T2R) - ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x00000000); /*Nc =2*/ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0; + u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; + u8 bfee_idx = (bfer_bfee_idx & 0xF); + u32 csi_param; + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + u16 sta_id = 0; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!\n", __func__)); + + hal_txbf_jaguar_rf_mode(p_dm_odm, p_beamforming_info); + + if (p_dm_odm->rf_type == ODM_2T2R) + odm_set_bb_reg(p_dm_odm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/ else - ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x01081008); /*Nc =1*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/ - if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { - BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; + if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { + beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx]; /*Sounding protocol control*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB); + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A, 0xCB); /*MAC address/Partial AID of Beamformer*/ - if (BFerIdx == 0) { + if (bfer_idx == 0) { for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_BFMER0_INFO_8812A + i), BeamformerEntry.MacAddr[i]); + odm_write_1byte(p_dm_odm, (REG_BFMER0_INFO_8812A + i), beamformer_entry.mac_addr[i]); /*CSI report use legacy ofdm so don't need to fill P_AID. */ - /*PlatformEFIOWrite2Byte(Adapter, REG_BFMER0_INFO_8812A+6, BeamformEntry.P_AID); */ + /*platform_efio_write_2byte(adapter, REG_BFMER0_INFO_8812A+6, beamform_entry.P_AID); */ } else { for (i = 0; i < 6 ; i++) - ODM_Write1Byte(pDM_Odm, (REG_BFMER1_INFO_8812A + i), BeamformerEntry.MacAddr[i]); + odm_write_1byte(p_dm_odm, (REG_BFMER1_INFO_8812A + i), beamformer_entry.mac_addr[i]); /*CSI report use legacy ofdm so don't need to fill P_AID.*/ - /*PlatformEFIOWrite2Byte(Adapter, REG_BFMER1_INFO_8812A+6, BeamformEntry.P_AID);*/ + /*platform_efio_write_2byte(adapter, REG_BFMER1_INFO_8812A+6, beamform_entry.P_AID);*/ } /*CSI report parameters of Beamformee*/ - if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) { - if (pDM_Odm->RFType == ODM_2T2R) - CSI_Param = 0x01090109; + if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) { + if (p_dm_odm->rf_type == ODM_2T2R) + csi_param = 0x01090109; else - CSI_Param = 0x01080108; + csi_param = 0x01080108; } else { - if (pDM_Odm->RFType == ODM_2T2R) - CSI_Param = 0x03090309; + if (p_dm_odm->rf_type == ODM_2T2R) + csi_param = 0x03090309; else - CSI_Param = 0x03080308; + csi_param = 0x03080308; } - ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, CSI_Param); - ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, CSI_Param); - ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, CSI_Param); + odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8812A, csi_param); + odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8812A, csi_param); + odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8812A, csi_param); /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A + 3, 0x50); + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A + 3, 0x50); } - if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { + beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx]; - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - STAid = BeamformeeEntry.MacId; + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + sta_id = beamformee_entry.mac_id; else - STAid = BeamformeeEntry.P_AID; + sta_id = beamformee_entry.p_aid; /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ - if (BFeeIdx == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, STAid); - ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3) | BIT4 | BIT6 | BIT7); + if (bfee_idx == 0) { + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8812A, sta_id); + odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8812A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8812A + 3) | BIT(4) | BIT(6) | BIT(7)); } else - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, STAid | BIT12 | BIT14 | BIT15); + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8812A + 2, sta_id | BIT(12) | BIT(14) | BIT(15)); /*CSI report parameters of Beamformee*/ - if (BFeeIdx == 0) { + if (bfee_idx == 0) { /*Get BIT24 & BIT25*/ - u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3) & 0x3; + u8 tmp = odm_read_1byte(p_dm_odm, REG_BFMEE_SEL_8812A + 3) & 0x3; - ODM_Write1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60); - ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, STAid | BIT9); + odm_write_1byte(p_dm_odm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60); + odm_write_2byte(p_dm_odm, REG_BFMEE_SEL_8812A, sta_id | BIT(9)); } else { /*Set BIT25*/ - ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, STAid | 0xE200); + odm_write_2byte(p_dm_odm, REG_BFMEE_SEL_8812A + 2, sta_id | 0xE200); } - phydm_Beamforming_Notify(pDM_Odm); + phydm_beamforming_notify(p_dm_odm); } } -VOID -HalTxbfJaguar_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx +void +hal_txbf_jaguar_leave( + void *p_dm_void, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMER_ENTRY BeamformerEntry; - RT_BEAMFORMEE_ENTRY BeamformeeEntry; - - if (Idx < BEAMFORMER_ENTRY_NUM) { - BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx]; - BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx]; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + + if (idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = p_beamforming_info->beamformer_entry[idx]; + beamformee_entry = p_beamforming_info->beamformee_entry[idx]; } else return; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!, IDx = %d\n", __func__, Idx)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!, IDx = %d\n", __func__, idx)); /*Clear P_AID of Beamformee*/ /*Clear MAC address of Beamformer*/ /*Clear Associated Bfmee Sel*/ - - if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8); - if (Idx == 0) { - ODM_Write4Byte(pDM_Odm, REG_BFMER0_INFO_8812A, 0); - ODM_Write2Byte(pDM_Odm, REG_BFMER0_INFO_8812A + 4, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); + + if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A, 0xC8); + if (idx == 0) { + odm_write_4byte(p_dm_odm, REG_BFMER0_INFO_8812A, 0); + odm_write_2byte(p_dm_odm, REG_BFMER0_INFO_8812A + 4, 0); + odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); + odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); + odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); } else { - ODM_Write4Byte(pDM_Odm, REG_BFMER1_INFO_8812A, 0); - ODM_Write2Byte(pDM_Odm, REG_BFMER1_INFO_8812A + 4, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); - ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); + odm_write_4byte(p_dm_odm, REG_BFMER1_INFO_8812A, 0); + odm_write_2byte(p_dm_odm, REG_BFMER1_INFO_8812A + 4, 0); + odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); + odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); + odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); } } - if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { - halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo); - if (Idx == 0) { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, 0x0); - ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, 0); + if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { + hal_txbf_jaguar_rf_mode(p_dm_odm, p_beamforming_info); + if (idx == 0) { + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8812A, 0x0); + odm_write_2byte(p_dm_odm, REG_BFMEE_SEL_8812A, 0); } else { - ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2) & 0xF000); - ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2) & 0x60); + odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8812A + 2, odm_read_2byte(p_dm_odm, REG_TXBF_CTRL_8812A + 2) & 0xF000); + odm_write_2byte(p_dm_odm, REG_BFMEE_SEL_8812A + 2, odm_read_2byte(p_dm_odm, REG_BFMEE_SEL_8812A + 2) & 0x60); } } - + } -VOID -HalTxbfJaguar_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx +void +hal_txbf_jaguar_status( + void *p_dm_void, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte BeamCtrlVal; - u4Byte BeamCtrlReg; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx]; - - if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) - BeamCtrlVal = BeamformEntry.MacId; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u16 beam_ctrl_val; + u32 beam_ctrl_reg; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamform_entry = p_beam_info->beamformee_entry[idx]; + + if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + beam_ctrl_val = beamform_entry.mac_id; else - BeamCtrlVal = BeamformEntry.P_AID; + beam_ctrl_val = beamform_entry.p_aid; - if (Idx == 0) - BeamCtrlReg = REG_TXBF_CTRL_8812A; + if (idx == 0) + beam_ctrl_reg = REG_TXBF_CTRL_8812A; else { - BeamCtrlReg = REG_TXBF_CTRL_8812A + 2; - BeamCtrlVal |= BIT12 | BIT14 | BIT15; + beam_ctrl_reg = REG_TXBF_CTRL_8812A + 2; + beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); } - if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamInfo->applyVmatrix == TRUE)) { - if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) - BeamCtrlVal |= BIT9; - else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) - BeamCtrlVal |= (BIT9 | BIT10); - else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80) - BeamCtrlVal |= (BIT9 | BIT10 | BIT11); + if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beam_info->apply_v_matrix == true)) { + if (beamform_entry.sound_bw == CHANNEL_WIDTH_20) + beam_ctrl_val |= BIT(9); + else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40) + beam_ctrl_val |= (BIT(9) | BIT(10)); + else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80) + beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11)); } else - BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); + beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamCtrlVal = 0x%x!\n", __func__, BeamCtrlVal)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] beam_ctrl_val = 0x%x!\n", __func__, beam_ctrl_val)); - ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); + odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val); } -VOID -HalTxbfJaguar_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx +void +hal_txbf_jaguar_fw_txbf( + void *p_dm_void, + u8 idx ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; - PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) - halTxbfJaguar_DownloadNDPA(pDM_Odm, Idx); + if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) + hal_txbf_jaguar_download_ndpa(p_dm_odm, idx); - halTxbfJaguar_FwTxBFCmd(pDM_Odm); + hal_txbf_jaguar_fw_txbf_cmd(p_dm_odm); } -VOID -HalTxbfJaguar_Patch( - IN PVOID pDM_VOID, - IN u1Byte Operation +void +hal_txbf_jaguar_patch( + void *p_dm_void, + u8 operation ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE) + if (p_beam_info->beamform_cap == BEAMFORMING_CAP_NONE) return; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (Operation == SCAN_OPT_BACKUP_BAND0) - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8); - else if (Operation == SCAN_OPT_RESTORE) - ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB); + if (operation == SCAN_OPT_BACKUP_BAND0) + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A, 0xC8); + else if (operation == SCAN_OPT_RESTORE) + odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A, 0xCB); #endif } -VOID -HalTxbfJaguar_Clk_8812A( - IN PVOID pDM_VOID +void +hal_txbf_jaguar_clk_8812a( + void *p_dm_void ) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u2Byte u2btmp; - u1Byte Count = 0, u1btmp; - PADAPTER Adapter = pDM_Odm->Adapter; - - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (*(pDM_Odm->pbScanInProcess)) { - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] return by Scan\n", __func__)); + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u16 u2btmp; + u8 count = 0, u1btmp; + struct _ADAPTER *adapter = p_dm_odm->adapter; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (*(p_dm_odm->p_is_scan_in_process)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] return by Scan\n", __func__)); return; } -#if DEV_BUS_TYPE == RT_PCI_INTERFACE +#if DEV_BUS_TYPE == RT_PCI_INTERFACE /*Stop PCIe TxDMA*/ - ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE); + odm_write_1byte(p_dm_odm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE); #endif /*Stop Usb TxDMA*/ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_DISABLE_FUNC(Adapter, DF_TX_BIT); - PlatformReturnAllPendingTxPackets(Adapter); + RT_DISABLE_FUNC(adapter, DF_TX_BIT); + PlatformReturnAllPendingTxPackets(adapter); #else - rtw_write_port_cancel(Adapter); + rtw_write_port_cancel(adapter); #endif /*Wait TXFF empty*/ - for (Count = 0; Count < 100; Count++) { - u2btmp = ODM_Read2Byte(pDM_Odm, REG_TXPKT_EMPTY_8812A); + for (count = 0; count < 100; count++) { + u2btmp = odm_read_2byte(p_dm_odm, REG_TXPKT_EMPTY_8812A); u2btmp = u2btmp & 0xfff; if (u2btmp != 0xfff) { ODM_delay_ms(10); @@ -472,11 +486,11 @@ HalTxbfJaguar_Clk_8812A( } /*TX pause*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF); + odm_write_1byte(p_dm_odm, REG_TXPAUSE_8812A, 0xFF); - /*Wait TX State Machine OK*/ - for (Count = 0; Count < 100; Count++) { - if (ODM_Read4Byte(pDM_Odm, REG_SCH_TXCMD_8812A) != 0) + /*Wait TX state Machine OK*/ + for (count = 0; count < 100; count++) { + if (odm_read_4byte(p_dm_odm, REG_SCH_TXCMD_8812A) != 0) continue; else break; @@ -484,39 +498,39 @@ HalTxbfJaguar_Clk_8812A( /*Stop RX DMA path*/ - u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A); - ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT2); + u1btmp = odm_read_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A); + odm_write_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT(2)); - for (Count = 0; Count < 100; Count++) { - u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A); - if (u1btmp & BIT1) + for (count = 0; count < 100; count++) { + u1btmp = odm_read_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A); + if (u1btmp & BIT(1)) break; else ODM_delay_ms(10); } /*Disable clock*/ - ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xf0); + odm_write_1byte(p_dm_odm, REG_SYS_CLKR_8812A + 1, 0xf0); /*Disable 320M*/ - ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0x8); + odm_write_1byte(p_dm_odm, REG_AFE_PLL_CTRL_8812A + 3, 0x8); /*Enable 320M*/ - ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0xa); + odm_write_1byte(p_dm_odm, REG_AFE_PLL_CTRL_8812A + 3, 0xa); /*Enable clock*/ - ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xfc); + odm_write_1byte(p_dm_odm, REG_SYS_CLKR_8812A + 1, 0xfc); /*Release Tx pause*/ - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0); + odm_write_1byte(p_dm_odm, REG_TXPAUSE_8812A, 0); /*Enable RX DMA path*/ - u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A); - ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT2)); + u1btmp = odm_read_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A); + odm_write_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT(2))); #if DEV_BUS_TYPE == RT_PCI_INTERFACE /*Enable PCIe TxDMA*/ - ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0); + odm_write_1byte(p_dm_odm, REG_PCIE_CTRL_REG_8812A + 1, 0); #endif /*Start Usb TxDMA*/ - RT_ENABLE_FUNC(Adapter, DF_TX_BIT); + RT_ENABLE_FUNC(adapter, DF_TX_BIT); } #endif @@ -524,4 +538,3 @@ HalTxbfJaguar_Clk_8812A( #endif - diff --git a/hal/phydm/txbf/haltxbfjaguar.h b/hal/phydm/txbf/haltxbfjaguar.h index ba16b7f..4b1b320 100644 --- a/hal/phydm/txbf/haltxbfjaguar.h +++ b/hal/phydm/txbf/haltxbfjaguar.h @@ -1,67 +1,88 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __HAL_TXBF_JAGUAR_H__ #define __HAL_TXBF_JAGUAR_H__ - -#if (BEAMFORMING_SUPPORT == 1) #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) -VOID -HalTxbf8812A_setNDPArate( - IN PVOID pDM_VOID, - IN u1Byte BW, - IN u1Byte Rate -); +#if (BEAMFORMING_SUPPORT == 1) +void +hal_txbf_8812a_set_ndpa_rate( + void *p_dm_void, + u8 BW, + u8 rate +); -VOID -HalTxbfJaguar_Enter( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_jaguar_enter( + void *p_dm_void, + u8 idx +); -VOID -HalTxbfJaguar_Leave( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_jaguar_leave( + void *p_dm_void, + u8 idx +); -VOID -HalTxbfJaguar_Status( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_jaguar_status( + void *p_dm_void, + u8 idx +); -VOID -HalTxbfJaguar_FwTxBF( - IN PVOID pDM_VOID, - IN u1Byte Idx - ); +void +hal_txbf_jaguar_fw_txbf( + void *p_dm_void, + u8 idx +); -VOID -HalTxbfJaguar_Patch( - IN PVOID pDM_VOID, - IN u1Byte Operation - ); +void +hal_txbf_jaguar_patch( + void *p_dm_void, + u8 operation +); -VOID -HalTxbfJaguar_Clk_8812A( - IN PVOID pDM_VOID - ); +void +hal_txbf_jaguar_clk_8812a( + void *p_dm_void +); #else -#define HalTxbf8812A_setNDPArate(pDM_VOID, BW, Rate) -#define HalTxbfJaguar_Enter(pDM_VOID, Idx) -#define HalTxbfJaguar_Leave(pDM_VOID, Idx) -#define HalTxbfJaguar_Status(pDM_VOID, Idx) -#define HalTxbfJaguar_FwTxBF(pDM_VOID, Idx) -#define HalTxbfJaguar_Patch(pDM_VOID, Operation) -#define HalTxbfJaguar_Clk_8812A(pDM_VOID) +#define hal_txbf_8812a_set_ndpa_rate(p_dm_void, BW, rate) +#define hal_txbf_jaguar_enter(p_dm_void, idx) +#define hal_txbf_jaguar_leave(p_dm_void, idx) +#define hal_txbf_jaguar_status(p_dm_void, idx) +#define hal_txbf_jaguar_fw_txbf(p_dm_void, idx) +#define hal_txbf_jaguar_patch(p_dm_void, operation) +#define hal_txbf_jaguar_clk_8812a(p_dm_void) #endif +#else -#endif -#endif // #ifndef __HAL_TXBF_JAGUAR_H__ +#define hal_txbf_8812a_set_ndpa_rate(p_dm_void, BW, rate) +#define hal_txbf_jaguar_enter(p_dm_void, idx) +#define hal_txbf_jaguar_leave(p_dm_void, idx) +#define hal_txbf_jaguar_status(p_dm_void, idx) +#define hal_txbf_jaguar_fw_txbf(p_dm_void, idx) +#define hal_txbf_jaguar_patch(p_dm_void, operation) +#define hal_txbf_jaguar_clk_8812a(p_dm_void) +#endif +#endif /* #ifndef __HAL_TXBF_JAGUAR_H__ */ diff --git a/hal/phydm/txbf/phydm_hal_txbf_api.c b/hal/phydm/txbf/phydm_hal_txbf_api.c index e3d5e2b..eed3487 100644 --- a/hal/phydm/txbf/phydm_hal_txbf_api.c +++ b/hal/phydm/txbf/phydm_hal_txbf_api.c @@ -1,60 +1,193 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" -#if (BEAMFORMING_SUPPORT == 1) - +#if (defined(CONFIG_BB_TXBF_API)) +#if (RTL8822B_SUPPORT == 1) /*Add by YuChen for 8822B MU-MIMO API*/ /*this function is only used for BFer*/ -u1Byte +u8 phydm_get_ndpa_rate( - IN PVOID pDM_VOID - ) + void *p_dm_void +) { - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte NDPARate = ODM_RATE6M; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 ndpa_rate = ODM_RATE6M; - if (pDM_Odm->RSSI_Min >= 30) /*link RSSI > 30%*/ - NDPARate = ODM_RATE24M; - else if (pDM_Odm->RSSI_Min <= 25) - NDPARate = ODM_RATE6M; + if (p_dm_odm->rssi_min >= 30) /*link RSSI > 30%*/ + ndpa_rate = ODM_RATE24M; + else if (p_dm_odm->rssi_min <= 25) + ndpa_rate = ODM_RATE6M; - ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] NDPARate = 0x%x\n", __func__, NDPARate)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] ndpa_rate = 0x%x\n", __func__, ndpa_rate)); - return NDPARate; + return ndpa_rate; } /*this function is only used for BFer*/ -u1Byte +u8 phydm_get_beamforming_sounding_info( - IN PVOID pDM_VOID, - IN pu2Byte Troughput, - IN u1Byte Total_BFee_Num, - IN pu1Byte TxRate - ) + void *p_dm_void, + u16 *troughput, + u8 total_bfee_num, + u8 *tx_rate +) { - u1Byte idx = 0; - u1Byte soundingdecision = 0xff; - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u8 idx = 0; + u8 soundingdecision = 0xff; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - for (idx = 0; idx < Total_BFee_Num; idx++) { - if (((TxRate[idx] >= ODM_RATEVHTSS3MCS7) && (TxRate[idx] <= ODM_RATEVHTSS3MCS9))) - soundingdecision = soundingdecision & ~(1<= ODM_RATEVHTSS3MCS7) && (tx_rate[idx] <= ODM_RATEVHTSS3MCS9))) + soundingdecision = soundingdecision & ~(1 << idx); } - for (idx = 0; idx < Total_BFee_Num; idx++) { - if (Troughput[idx] <= 10) - soundingdecision = soundingdecision & ~(1<= 500) + snding_score = 100; + else if (throughput >= 450) + snding_score = 90; + else if (throughput >= 400) + snding_score = 80; + else if (throughput >= 350) + snding_score = 70; + else if (throughput >= 300) + snding_score = 60; + else if (throughput >= 250) + snding_score = 50; + else if (throughput >= 200) + snding_score = 40; + else if (throughput >= 150) + snding_score = 30; + else if (throughput >= 100) + snding_score = 20; + else if (throughput >= 50) + snding_score = 10; + else + snding_score = 0; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] snding_score = 0x%x\n", __func__, snding_score)); + + return snding_score; + +} + + +#endif +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +u8 +beamforming_get_htndp_tx_rate( + void *p_dm_void, + u8 comp_steering_num_of_bfer +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 nr_index = 0; + u8 ndp_tx_rate; + /*Find nr*/ +#if (RTL8814A_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), comp_steering_num_of_bfer); + else +#endif + nr_index = tx_bf_nr(1, comp_steering_num_of_bfer); + + switch (nr_index) { + case 1: + ndp_tx_rate = ODM_MGN_MCS8; + break; + + case 2: + ndp_tx_rate = ODM_MGN_MCS16; + break; + + case 3: + ndp_tx_rate = ODM_MGN_MCS24; + break; + + default: + ndp_tx_rate = ODM_MGN_MCS8; + break; + } + + return ndp_tx_rate; + +} + +u8 +beamforming_get_vht_ndp_tx_rate( + void *p_dm_void, + u8 comp_steering_num_of_bfer +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 nr_index = 0; + u8 ndp_tx_rate; + /*Find nr*/ +#if (RTL8814A_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), comp_steering_num_of_bfer); + else +#endif + nr_index = tx_bf_nr(1, comp_steering_num_of_bfer); + + switch (nr_index) { + case 1: + ndp_tx_rate = ODM_MGN_VHT2SS_MCS0; + break; + + case 2: + ndp_tx_rate = ODM_MGN_VHT3SS_MCS0; + break; + case 3: + ndp_tx_rate = ODM_MGN_VHT4SS_MCS0; + break; + + default: + ndp_tx_rate = ODM_MGN_VHT2SS_MCS0; + break; + } + return ndp_tx_rate; + +} #endif +#endif diff --git a/hal/phydm/txbf/phydm_hal_txbf_api.h b/hal/phydm/txbf/phydm_hal_txbf_api.h index 47fb30b..3dd0bb3 100644 --- a/hal/phydm/txbf/phydm_hal_txbf_api.h +++ b/hal/phydm/txbf/phydm_hal_txbf_api.h @@ -1,36 +1,66 @@ -/********************************************************************************/ -/**/ -/*Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.*/ -/**/ -/*This program is free software; you can redistribute it and/or modify it*/ -/*under the terms of version 2 of the GNU General Public License as*/ -/*published by the Free Software Foundation.*/ -/**/ -/*This program is distributed in the hope that it will be useful, but WITHOUT*/ -/*ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or*/ -/*FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for*/ -/*more details.*/ -/*You should have received a copy of the GNU General Public License along with*/ -/*this program; if not, write to the Free Software Foundation, Inc.,*/ -/*51 Franklin Street, Fifth Floor, Boston, MA 02110, USA*/ -/**/ -/**/ -/********************************************************************************/ +/****************************************************************************** + * + * Copyright(c) 2011 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + #ifndef __PHYDM_HAL_TXBF_API_H__ #define __PHYDM_HAL_TXBF_API_H__ -u1Byte -phydm_get_beamforming_sounding_info( - IN PVOID pDM_VOID, - IN pu2Byte Troughput, - IN u1Byte Total_BFee_Num, - IN pu1Byte TxRate - ); +#if (defined(CONFIG_BB_TXBF_API)) + +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#define tx_bf_nr(a, b) ((a > b) ? (b) : (a)) + +u8 +beamforming_get_htndp_tx_rate( + void *p_dm_void, + u8 comp_steering_num_of_bfer +); +u8 +beamforming_get_vht_ndp_tx_rate( + void *p_dm_void, + u8 comp_steering_num_of_bfer +); -u1Byte +#endif + +#if (RTL8822B_SUPPORT == 1) +u8 +phydm_get_beamforming_sounding_info( + void *p_dm_void, + u16 *troughput, + u8 total_bfee_num, + u8 *tx_rate +); + +u8 phydm_get_ndpa_rate( - IN PVOID pDM_VOID - ); + void *p_dm_void +); + +u8 +phydm_get_mu_bfee_snding_decision( + void *p_dm_void, + u16 throughput +); + +#else +#define phydm_get_beamforming_sounding_info(p_dm_void, troughput, total_bfee_num, tx_rate) +#define phydm_get_ndpa_rate(p_dm_void) +#define phydm_get_mu_bfee_snding_decision(p_dm_void, troughput) #endif + +#endif +#endif diff --git a/hal/rtl8822b/rtl8822b.h b/hal/rtl8822b/rtl8822b.h index 40cc8d5..978be7f 100644 --- a/hal/rtl8822b/rtl8822b.h +++ b/hal/rtl8822b/rtl8822b.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8822B_H_ #define _RTL8822B_H_ @@ -25,10 +20,27 @@ #include /* struct pkt_attrib, struct xmit_frame */ #include /* struct recv_frame */ #include /* HAL_DEF_VARIABLE */ +#include "hal8822b_fw.h" /* FW array */ #define DRIVER_EARLY_INT_TIME_8822B 0x05 #define BCN_DMA_ATIME_INT_TIME_8822B 0x02 +/* rtl8822b_ops.c */ +struct hw_port_reg { + u32 net_type; /*reg_offset*/ + u8 net_type_shift; + u32 macaddr; /*reg_offset*/ + u32 bssid; /*reg_offset*/ + u32 bcn_ctl; /*reg_offset*/ + u32 tsf_rst; /*reg_offset*/ + u8 tsf_rst_bit; + u32 bcn_space; /*reg_offset*/ + u8 bcn_space_shift; + u16 bcn_space_mask; + u32 ps_aid; /*reg_offset*/ +}; + + /* rtl8822b_halinit.c */ void rtl8822b_init_hal_spec(PADAPTER); u32 rtl8822b_power_on(PADAPTER); @@ -53,17 +65,14 @@ u8 rtl8822b_rx_tsf_addr_filter_config(PADAPTER, u8 config); s32 rtl8822b_fw_dl(PADAPTER, u8 wowlan); /* rtl8822b_ops.c */ -void rtl8822b_read_efuse(PADAPTER); +u8 rtl8822b_read_efuse(PADAPTER); void rtl8822b_run_thread(PADAPTER); void rtl8822b_cancel_thread(PADAPTER); void rtl8822b_sethwreg(PADAPTER, u8 variable, u8 *pval); void rtl8822b_gethwreg(PADAPTER, u8 variable, u8 *pval); -void rtl8822b_sethwregwithbuf(PADAPTER, u8 variable, u8 *pbuf, int len); u8 rtl8822b_sethaldefvar(PADAPTER, HAL_DEF_VARIABLE, void *pval); u8 rtl8822b_gethaldefvar(PADAPTER, HAL_DEF_VARIABLE, void *pval); void rtl8822b_set_hal_ops(PADAPTER); -void rtl8822b_resume_tx_beacon(PADAPTER); -void rtl8822b_stop_tx_beacon(PADAPTER); /* tx */ void rtl8822b_fill_txdesc_sectype(struct pkt_attrib *, u8 *ptxdesc); @@ -72,6 +81,8 @@ void rtl8822b_fill_txdesc_phy(PADAPTER, struct pkt_attrib *, u8 *ptxdesc); void rtl8822b_fill_txdesc_force_bmc_camid(struct pkt_attrib *, u8 *ptxdesc); u8 rtl8822b_bw_mapping(PADAPTER, struct pkt_attrib *); u8 rtl8822b_sc_mapping(PADAPTER, struct pkt_attrib *); +void rtl8822b_fill_txdesc_bf(struct xmit_frame *, u8 *desc); +void rtl8822b_fill_txdesc_mgnt_bf(struct xmit_frame *, u8 *desc); void rtl8822b_cal_txdesc_chksum(PADAPTER, u8 *ptxdesc); void rtl8822b_update_txdesc(struct xmit_frame *, u8 *pbuf); void rtl8822b_dbg_dump_tx_desc(PADAPTER, int frame_tag, u8 *ptxdesc); @@ -83,12 +94,11 @@ void rtl8822b_query_rx_desc(union recv_frame *, u8 *pdesc); /* rtl8822b_cmd.c */ s32 rtl8822b_fillh2ccmd(PADAPTER, u8 id, u32 buf_len, u8 *pbuf); void rtl8822b_set_FwMediaStatusRpt_cmd(PADAPTER, u8 mstatus, u8 macid); -void rtl8822b_set_FwMacIdConfig_cmd(PADAPTER , u64 bitmap, u8 *arg); +void rtl8822b_set_FwMacIdConfig_cmd(PADAPTER , u64 bitmap, u8 *arg, u8 bw); void rtl8822b_set_FwRssiSetting_cmd(PADAPTER, u8 *param); void rtl8822b_set_FwPwrMode_cmd(PADAPTER, u8 psmode); -#ifdef CONFIG_P2P -void rtl8822b_set_p2p_ps_offload_cmd(PADAPTER, u8 p2p_ps_state); -#endif +void rtl8822b_set_FwPwrModeInIPS_cmd(PADAPTER adapter, u8 cmd_param); +void rtl8822b_req_txrpt_cmd(PADAPTER, u8 macid); void rtl8822b_fw_update_beacon_cmd(PADAPTER); void rtl8822b_c2h_handler(PADAPTER, u8 *pbuf, u16 length); void rtl8822b_c2h_handler_no_io(PADAPTER, u8 *pbuf, u16 length); @@ -111,18 +121,18 @@ void rtl8822b_write_bb_reg(PADAPTER, u32 addr, u32 mask, u32 val); u32 rtl8822b_read_rf_reg(PADAPTER, u8 path, u32 addr, u32 mask); void rtl8822b_write_rf_reg(PADAPTER, u8 path, u32 addr, u32 mask, u32 val); void rtl8822b_set_channel_bw(PADAPTER, u8 center_ch, CHANNEL_WIDTH, u8 offset40, u8 offset80); -void rtl8822b_set_channel(PADAPTER, u8 center_ch); -void rtl8822b_set_bw_mode(PADAPTER, CHANNEL_WIDTH, u8 offset); void rtl8822b_set_tx_power_level(PADAPTER, u8 channel); void rtl8822b_get_tx_power_level(PADAPTER, s32 *power); void rtl8822b_set_tx_power_index(PADAPTER, u32 powerindex, u8 rfpath, u8 rate); -u8 rtl8822b_get_tx_power_index(PADAPTER, u8 rfpath, u8 rate, u8 bandwidth, u8 channel); +u8 rtl8822b_get_tx_power_index(PADAPTER, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); void rtl8822b_notch_filter_switch(PADAPTER, bool enable); #ifdef CONFIG_BEAMFORMING -void rtl8822b_phy_init_beamforming(PADAPTER); -void rtl8822b_phy_sounding_enter(PADAPTER, struct sta_info*); -void rtl8822b_phy_sounding_leave(PADAPTER, u8 *addr); -void rtl8822b_phy_sounding_set_gid_table(PADAPTER, struct beamformer_entry*); +void rtl8822b_phy_bf_init(PADAPTER); +void rtl8822b_phy_bf_enter(PADAPTER, struct sta_info*); +void rtl8822b_phy_bf_leave(PADAPTER, u8 *addr); +void rtl8822b_phy_bf_set_gid_table(PADAPTER, struct beamformer_entry*); +void rtl8822b_phy_bf_set_csi_report(PADAPTER, struct _RT_CSI_INFO*); +void rtl8822b_phy_bf_sounding_status(PADAPTER, u8 status); #endif /* CONFIG_BEAMFORMING */ #endif /* _RTL8822B_H_ */ diff --git a/hal/rtl8822b/rtl8822b_cmd.c b/hal/rtl8822b/rtl8822b_cmd.c index 8268d74..4f59767 100644 --- a/hal/rtl8822b/rtl8822b_cmd.c +++ b/hal/rtl8822b/rtl8822b_cmd.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8822B_CMD_C_ #include /* HAL_DATA_TYPE */ @@ -134,7 +129,7 @@ static void rtl8822b_set_FwAoacRsvdPage_cmd(PADAPTER adapter, PRSVDPAGE_LOC rsvd rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); } else { #ifdef CONFIG_PNO_SUPPORT - if (!pwrpriv->pno_in_resume) { + if (!pwrpriv->wowlan_in_resume) { RTW_INFO("%s: NLO_INFO=%d\n", __FUNCTION__, rsvdpageloc->LocPNOInfo); AOAC_RSVD_PAGE3_SET_CMD_ID(h2c, CMD_ID_AOAC_RSVD_PAGE3); AOAC_RSVD_PAGE3_SET_CLASS(h2c, CLASS_AOAC_RSVD_PAGE3); @@ -235,12 +230,12 @@ static u8 get_ra_ldpc(struct sta_info *psta) en_ldpc = 0; else { #ifdef CONFIG_80211AC_VHT - if (IsSupportedVHT(psta->wireless_mode)) { + if (is_supported_vht(psta->wireless_mode)) { if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_CAP_TX)) en_ldpc = 1; else en_ldpc = 0; - } else if (IsSupportedHT(psta->wireless_mode)) { + } else if (is_supported_ht(psta->wireless_mode)) { if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_CAP_TX)) en_ldpc = 1; else @@ -261,12 +256,13 @@ static u8 get_ra_ldpc(struct sta_info *psta) * arg[2] = shortGIrate * arg[3] = init_rate */ -void rtl8822b_set_FwMacIdConfig_cmd(PADAPTER adapter, u64 mask, u8 *arg) +void rtl8822b_set_FwMacIdConfig_cmd(PADAPTER adapter, u64 mask, u8 *arg, u8 bw) { HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; struct sta_info *psta = NULL; - u8 mac_id, init_rate, raid, bw, sgi = _FALSE; + u8 mac_id, init_rate, raid, sgi = _FALSE; + u8 ignore_bw = _FALSE; u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; @@ -278,7 +274,8 @@ void rtl8822b_set_FwMacIdConfig_cmd(PADAPTER adapter, u64 mask, u8 *arg) mac_id = arg[0]; raid = arg[1]; - sgi = arg[2]; + sgi = arg[2] & 0x0F; + ignore_bw = arg[2] >> 4; init_rate = arg[3]; if (mac_id < macid_ctl->num) @@ -290,8 +287,6 @@ void rtl8822b_set_FwMacIdConfig_cmd(PADAPTER adapter, u64 mask, u8 *arg) return; } - bw = psta->bw_mode; - RTW_INFO(FUNC_ADPT_FMT ": mac_id=%d raid=0x%x bw=%d mask=0x%016llx\n", FUNC_ADPT_ARG(adapter), mac_id, raid, bw, mask); @@ -303,6 +298,7 @@ void rtl8822b_set_FwMacIdConfig_cmd(PADAPTER adapter, u64 mask, u8 *arg) MACID_CFG_SET_MAC_ID(h2c, mac_id); MACID_CFG_SET_RATE_ID(h2c, raid); MACID_CFG_SET_SGI(h2c, (sgi) ? 1 : 0); + MACID_CFG_SET_NO_UPDATE(h2c, (ignore_bw) ? 1 : 0); MACID_CFG_SET_BW(h2c, bw); MACID_CFG_SET_LDPC_CAP(h2c, get_ra_ldpc(psta)); MACID_CFG_SET_WHT_EN(h2c, get_ra_vht_en(psta->wireless_mode, mask)); @@ -313,9 +309,9 @@ void rtl8822b_set_FwMacIdConfig_cmd(PADAPTER adapter, u64 mask, u8 *arg) MACID_CFG_SET_DISPT(h2c, 1); RTW_INFO("%s: Disable PWT by driver\n", __FUNCTION__); } else { - PDM_ODM_T pDM_OutSrc = &hal->odmpriv; + struct PHY_DM_STRUCT *p_dm_out_src = &hal->odmpriv; - if (pDM_OutSrc->bDisablePowerTraining) { + if (p_dm_out_src->is_disable_power_training) { MACID_CFG_SET_DISPT(h2c, 1); RTW_INFO("%s: Disable PWT by DM\n", __FUNCTION__); } @@ -379,10 +375,27 @@ void rtl8822b_set_FwAPReqRPT_cmd(PADAPTER adapter, u32 need_ack) rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); } +void rtl8822b_req_txrpt_cmd(PADAPTER adapter, u8 macid) +{ + u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; + + AP_REQ_TXRPT_SET_CMD_ID(h2c, CMD_ID_AP_REQ_TXRPT); + AP_REQ_TXRPT_SET_CLASS(h2c, CLASS_AP_REQ_TXRPT); + + AP_REQ_TXRPT_SET_STA1_MACID(h2c, macid); + AP_REQ_TXRPT_SET_STA2_MACID(h2c, 0xff); + AP_REQ_TXRPT_SET_RTY_OK_TOTAL(h2c, 0x00); + AP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c, 0x00); + rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); + + AP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c, 0x01); + rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); +} + void rtl8822b_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) { int i; - u8 smart_ps = 0; + u8 smart_ps = 0, mode = 0; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; @@ -393,21 +406,26 @@ void rtl8822b_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) if (pwrpriv->dtim > 0) - RTW_INFO(FUNC_ADPT_FMT ": FW LPS mode = %d, SmartPS=%d, dtim=%d\n", - FUNC_ADPT_ARG(adapter), psmode, pwrpriv->smart_ps, pwrpriv->dtim); + RTW_INFO(FUNC_ADPT_FMT ": FW LPS mode = %d, SmartPS=%d, dtim=%d, HW port id=%d\n", + FUNC_ADPT_ARG(adapter), psmode, pwrpriv->smart_ps, pwrpriv->dtim, + psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id:get_hw_port(adapter)); else - RTW_INFO(FUNC_ADPT_FMT ": FW LPS mode = %d, SmartPS=%d\n", - FUNC_ADPT_ARG(adapter), psmode, pwrpriv->smart_ps); + RTW_INFO(FUNC_ADPT_FMT ": FW LPS mode = %d, SmartPS=%d, HW port id=%d\n", + FUNC_ADPT_ARG(adapter), psmode, pwrpriv->smart_ps, + psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id:get_hw_port(adapter)); if (psmode == PS_MODE_MIN) { + mode = 1; rlbm = 0; awake_intvl = 2; smart_ps = pwrpriv->smart_ps; } else if (psmode == PS_MODE_MAX) { + mode = 1; rlbm = 1; awake_intvl = 2; smart_ps = pwrpriv->smart_ps; } else if (psmode == PS_MODE_DTIM) { + mode = 1; /* For WOWLAN LPS, DTIM = (awake_intvl - 1) */ if (pwrpriv->dtim > 0 && pwrpriv->dtim < 16) /* DTIM = (awake_intvl - 1) */ @@ -418,6 +436,13 @@ void rtl8822b_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) rlbm = 2; smart_ps = pwrpriv->smart_ps; + } else if (psmode == PS_MODE_UAPSD_WMM) { + mode = 2; + rlbm = 0; /*1*/ + /*(WMM)smart_ps: 0:PS_Poll, 1:NullData*/ + smart_ps = (pwrpriv->smart_ps) ? 1 : 0; + } else if (psmode == PS_MODE_ACTIVE) { + mode = 0; } else { rlbm = 2; awake_intvl = 4; @@ -463,13 +488,20 @@ void rtl8822b_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) SET_PWR_MODE_SET_CMD_ID(h2c, CMD_ID_SET_PWR_MODE); SET_PWR_MODE_SET_CLASS(h2c, CLASS_SET_PWR_MODE); - SET_PWR_MODE_SET_MODE(h2c, (psmode > 0) ? 1 : 0); + SET_PWR_MODE_SET_MODE(h2c, mode); SET_PWR_MODE_SET_SMART_PS(h2c, smart_ps); SET_PWR_MODE_SET_RLBM(h2c, rlbm); SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c, awake_intvl); SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c, adapter->registrypriv.uapsd_enable); SET_PWR_MODE_SET_PWR_STATE(h2c, PowerState); - SET_PWR_MODE_SET_PORT_ID(h2c, get_hw_port(adapter)); + if (psmode == PS_MODE_ACTIVE) { + /* Leave LPS, set the same HW port ID */ + SET_PWR_MODE_SET_PORT_ID(h2c, pwrpriv->current_lps_hw_port_id); + } else { + /* Enter LPS, record HW port ID */ + SET_PWR_MODE_SET_PORT_ID(h2c, get_hw_port(adapter)); + pwrpriv->current_lps_hw_port_id = get_hw_port(adapter); + } if (byte5 & BIT(0)) SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c, 1); @@ -535,6 +567,20 @@ void rtl8822b_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) void rtl8822b_set_FwPwrModeInIPS_cmd(PADAPTER adapter, u8 cmd_param) { + + u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; + + INACTIVE_PS_SET_CMD_ID(h2c, CMD_ID_INACTIVE_PS); + INACTIVE_PS_SET_CLASS(h2c, CLASS_INACTIVE_PS); + + if (cmd_param & BIT0) + INACTIVE_PS_SET_ENABLE(h2c, 1); + + if (cmd_param & BIT1) + INACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c, 1); + + RTW_DBG_DUMP("H2C-FwPwrModeInIPS Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); + rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); } static s32 rtl8822b_set_FwLowPwrLps_cmd(PADAPTER adapter, u8 enable) @@ -564,7 +610,7 @@ static void ConstructBeacon(PADAPTER adapter, u8 *pframe, u32 *pLength) _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); SetSeqNum(pwlanhdr, 0); - SetFrameSubType(pframe, WIFI_BEACON); + set_frame_sub_type(pframe, WIFI_BEACON); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -645,10 +691,10 @@ static void ConstructPSPoll(PADAPTER adapter, u8 *pframe, u32 *pLength) fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; SetPwrMgt(fctrl); - SetFrameSubType(pframe, WIFI_PSPOLL); + set_frame_sub_type(pframe, WIFI_PSPOLL); /* AID. */ - SetDuration(pframe, (pmlmeinfo->aid | 0xc000)); + set_duration(pframe, (pmlmeinfo->aid | 0xc000)); /* BSSID. */ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); @@ -711,7 +757,7 @@ static void ConstructNullFunctionData( if (bQoS == _TRUE) { struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; - SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); + set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe; SetPriority(&pwlanqoshdr->qc, AC); @@ -719,7 +765,7 @@ static void ConstructNullFunctionData( pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); } else { - SetFrameSubType(pframe, WIFI_DATA_NULL); + set_frame_sub_type(pframe, WIFI_DATA_NULL); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); } @@ -763,7 +809,7 @@ static void ConstructProbeRsp(PADAPTER adapter, u8 *pframe, u32 *pLength, u8 *St RTW_INFO("%s FW IP Addr" IP_FMT "\n", __FUNCTION__, IP_ARG(StaAddr)); SetSeqNum(pwlanhdr, 0); - SetFrameSubType(fctrl, WIFI_PROBERSP); + set_frame_sub_type(fctrl, WIFI_PROBERSP); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); pframe += pktlen; @@ -922,13 +968,13 @@ static void ConstructBtNullFunctionData( _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN); - SetDuration(pwlanhdr, 0); + set_duration(pwlanhdr, 0); SetSeqNum(pwlanhdr, 0); if (bQoS == _TRUE) { struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; - SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); + set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe; SetPriority(&pwlanqoshdr->qc, AC); @@ -936,7 +982,7 @@ static void ConstructBtNullFunctionData( pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); } else { - SetFrameSubType(pframe, WIFI_DATA_NULL); + set_frame_sub_type(pframe, WIFI_DATA_NULL); pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); } @@ -1057,7 +1103,8 @@ void rtl8822b_download_BTCoex_AP_mode_rsvd_page(PADAPTER adapter) u8 bcn_valid = _FALSE; u8 DLBcnCount = 0; u32 poll = 0; - u8 val8; + u8 val8, RegFwHwTxQCtrl; + u8 restore[2]; RTW_INFO("+" FUNC_ADPT_FMT ": hw_port=%d fw_state=0x%08X\n", @@ -1075,29 +1122,32 @@ void rtl8822b_download_BTCoex_AP_mode_rsvd_page(PADAPTER adapter) pmlmeinfo = &pmlmeext->mlmext_info; /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */ - rtw_write16(adapter, REG_BCN_PSR_RPT, (0xC000 | pmlmeinfo->aid)); + rtw_write16(adapter, REG_BCN_PSR_RPT_8822B, (0xC000 | pmlmeinfo->aid)); /* set REG_CR bit 8 */ - val8 = rtw_read8(adapter, REG_CR + 1); + val8 = rtw_read8(adapter, REG_CR_8822B + 1); + restore[0] = val8; val8 |= BIT(0); /* ENSWBCN */ - rtw_write8(adapter, REG_CR + 1, val8); + rtw_write8(adapter, REG_CR_8822B + 1, val8); /* * Disable Hw protection for a time which revserd for Hw sending beacon. * Fix download reserved page packet fail that access collision with the protection time. */ - val8 = rtw_read8(adapter, REG_BCN_CTRL); - val8 &= ~EN_BCN_FUNCTION; - val8 |= DIS_TSF_UDT; - rtw_write8(adapter, REG_BCN_CTRL, val8); + val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B); + restore[1] = val8; + val8 &= ~BIT_EN_BCN_FUNCTION_8822B; + val8 |= BIT_DIS_TSF_UDT_8822B; + rtw_write8(adapter, REG_BCN_CTRL_8822B, val8); /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */ - if (hal->RegFwHwTxQCtrl & BIT(6)) + RegFwHwTxQCtrl = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2); + if (RegFwHwTxQCtrl & BIT(6)) bRecover = _TRUE; /* To tell Hw the packet is not a real beacon frame. */ - hal->RegFwHwTxQCtrl &= ~BIT(6); - rtw_write8(adapter, REG_FWHW_TXQ_CTRL + 2, hal->RegFwHwTxQCtrl); + RegFwHwTxQCtrl &= ~BIT(6); + rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2, RegFwHwTxQCtrl); /* Clear beacon valid check bit. */ rtw_hal_set_hwreg(adapter, HW_VAR_BCN_VALID, NULL); @@ -1132,11 +1182,6 @@ void rtl8822b_download_BTCoex_AP_mode_rsvd_page(PADAPTER adapter) ADPT_ARG(adapter), rtw_is_drv_stopped(adapter) ? "True" : "False"); } - val8 = rtw_read8(adapter, REG_BCN_CTRL); - val8 |= EN_BCN_FUNCTION; - val8 &= ~DIS_TSF_UDT; - rtw_write8(adapter, REG_BCN_CTRL, val8); - /* * To make sure that if there exists an adapter which would like to send beacon. * If exists, the origianl value of 0x422[6] will be 1, we should check this to @@ -1144,105 +1189,22 @@ void rtl8822b_download_BTCoex_AP_mode_rsvd_page(PADAPTER adapter) * the beacon cannot be sent by HW. */ if (bRecover) { - hal->RegFwHwTxQCtrl |= BIT(6); - rtw_write8(adapter, REG_FWHW_TXQ_CTRL + 2, hal->RegFwHwTxQCtrl); + RegFwHwTxQCtrl |= BIT(6); + rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2, RegFwHwTxQCtrl); } + rtw_write8(adapter, REG_BCN_CTRL_8822B, restore[1]); + rtw_write8(adapter, REG_CR_8822B + 1, restore[0]); + /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */ #ifndef CONFIG_PCI_HCI - val8 = rtw_read8(adapter, REG_CR + 1); + val8 = rtw_read8(adapter, REG_CR_8822B + 1); val8 &= ~BIT(0); /* ~ENSWBCN */ - rtw_write8(adapter, REG_CR + 1, val8); + rtw_write8(adapter, REG_CR_8822B + 1, val8); #endif /* !CONFIG_PCI_HCI */ } #endif /* CONFIG_BT_COEXIST */ -#ifdef CONFIG_P2P -void rtl8822b_set_p2p_ps_offload_cmd(PADAPTER adapter, u8 p2p_ps_state) -{ - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); - struct wifidirect_info *pwdinfo = &adapter->wdinfo; - u8 i; - u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; - - - _rtw_memcpy(&h2c[1], &hal->p2p_ps_offload, sizeof(hal->p2p_ps_offload)); - - P2P_PS_OFFLOAD_SET_CMD_ID(h2c, CMD_ID_P2P_PS_OFFLOAD); - P2P_PS_OFFLOAD_SET_CLASS(h2c, CLASS_P2P_PS_OFFLOAD); - - switch (p2p_ps_state) { - case P2P_PS_DISABLE: - RTW_INFO("P2P_PS_DISABLE\n"); - _rtw_memset(&h2c[1], 0, sizeof(hal->p2p_ps_offload)); - break; - - case P2P_PS_ENABLE: - RTW_INFO("P2P_PS_ENABLE\n"); - /* update CTWindow value. */ - if (pwdinfo->ctwindow > 0) { - P2P_PS_OFFLOAD_SET_CTWINDOW_EN(h2c, 1); - rtw_write8(adapter, REG_CTWND_8822B, pwdinfo->ctwindow); - } - - /* hw only support 2 set of NoA */ - for (i = 0; i < pwdinfo->noa_num; i++) { - /* To control the register setting for which NOA */ - rtw_write8(adapter, REG_TXCMD_NOA_SEL_8822B, (i << 4)); - if (i == 0) - P2P_PS_OFFLOAD_SET_NOA0_EN(h2c, 1); - else - P2P_PS_OFFLOAD_SET_NOA1_EN(h2c, 1); - - /* config P2P NoA Descriptor Register */ - /* config NOA duration */ - rtw_write32(adapter, REG_NOA_PARAM_8822B, pwdinfo->noa_duration[i]); - /* config NOA interval */ - rtw_write32(adapter, (REG_NOA_PARAM_8822B + 4), pwdinfo->noa_interval[i]); - /* config NOA start time */ - rtw_write32(adapter, (REG_NOA_PARAM_8822B + 8), pwdinfo->noa_start_time[i]); - /* config NOA count */ - rtw_write8(adapter, (REG_NOA_PARAM_8822B + 12), pwdinfo->noa_count[i]); - } - - if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) { - /* rst p2p circuit */ - rtw_write8(adapter, REG_P2P_RST_8822B, BIT(0)); - - P2P_PS_OFFLOAD_SET_OFFLOAD_EN(h2c, 1); - - if (pwdinfo->role == P2P_ROLE_GO) { - P2P_PS_OFFLOAD_SET_ROLE(h2c, 1); - P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(h2c, 0); - } else - P2P_PS_OFFLOAD_SET_ROLE(h2c, 0); - - ((struct P2P_PS_Offload_t *)&h2c[1])->discovery = 0; - } - break; - - case P2P_PS_SCAN: - RTW_INFO("P2P_PS_SCAN\n"); - ((struct P2P_PS_Offload_t *)&h2c[1])->discovery = 1; - break; - - case P2P_PS_SCAN_DONE: - RTW_INFO("P2P_PS_SCAN_DONE\n"); - ((struct P2P_PS_Offload_t *)&h2c[1])->discovery = 0; - pwdinfo->p2p_ps_state = P2P_PS_ENABLE; - break; - - default: - break; - } - - RTW_DBG_DUMP("H2C-P2PPSOffload Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); - rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); - - _rtw_memcpy(&hal->p2p_ps_offload, &h2c[1], sizeof(hal->p2p_ps_offload)); -} -#endif /* CONFIG_P2P */ #ifdef CONFIG_TSF_RESET_OFFLOAD /* @@ -1279,20 +1241,78 @@ void rtl8822b_fw_update_beacon_cmd(PADAPTER adapter) static void c2h_ccx_rpt(PADAPTER adapter, u8 *pdata) { #ifdef CONFIG_XMIT_ACK - u8 seq_no, retry_over, life_time_over; +#define C2H_CCX_RPT_GET_TX_STATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 30, 2) + u8 tx_state = _FALSE; + tx_state = C2H_CCX_RPT_GET_TX_STATE(pdata); - seq_no = C2H_CCX_RPT_GET_SEQ(pdata); - retry_over = C2H_CCX_RPT_GET_RETRY_OVER(pdata); - life_time_over = C2H_CCX_RPT_GET_LIFE_TIME_OVER(pdata); - - if (retry_over || life_time_over) - rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); - else + /* 0 means success, 1 means retry drop */ + if (tx_state == 0) rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_SUCCESS); + else + rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); #endif /* CONFIG_XMIT_ACK */ } +static VOID +C2HTxRPTHandler_8822b( + IN PADAPTER Adapter, + IN u8 *CmdBuf, + IN u8 CmdLen +) +{ + _irqL irqL; + u8 macid = 0, IniRate = 0; + u16 TxOK = 0, TxFail = 0; + u8 TxOK0 = 0, TxOK1 = 0; + u8 TxFail0 = 0, TxFail1 = 0; + struct sta_priv *pstapriv = &(Adapter->stapriv); + struct sta_info *psta = NULL; + struct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(Adapter); + + if (!pstapriv->c2h_sta) { + RTW_WARN("%s: No corresponding sta_info!\n", __FUNCTION__); + return; + } + psta = pstapriv->c2h_sta; + macid = C2H_AP_REQ_TXRPT_GET_STA1_MACID(CmdBuf); + TxOK0 = C2H_AP_REQ_TXRPT_GET_TX_OK1_0(CmdBuf); + TxOK1 = C2H_AP_REQ_TXRPT_GET_TX_OK1_1(CmdBuf); + TxOK = (TxOK1 << 8) | TxOK0; + TxFail0 = C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(CmdBuf); + TxFail1 = C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(CmdBuf); + TxFail = (TxFail1 << 8) | TxFail0; + IniRate = C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(CmdBuf); + + psta->sta_stats.tx_ok_cnt = TxOK; + psta->sta_stats.tx_fail_cnt = TxFail; + +} + +static VOID +C2HSPC_STAT_8822b( + IN PADAPTER Adapter, + IN u8 *CmdBuf, + IN u8 CmdLen +) +{ + _irqL irqL; + struct sta_priv *pstapriv = &(Adapter->stapriv); + struct sta_info *psta = NULL; + struct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(Adapter); + _list *plist, *phead; + u8 idx = C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(CmdBuf); + + if (!pstapriv->c2h_sta) { + RTW_WARN("%s: No corresponding sta_info!\n", __FUNCTION__); + return; + } + psta = pstapriv->c2h_sta; + psta->sta_stats.tx_retry_cnt = (C2H_SPECIAL_STATISTICS_GET_DATA3(CmdBuf) << 8) | C2H_SPECIAL_STATISTICS_GET_DATA2(CmdBuf); + pstapriv->c2h_sta = NULL; + rtw_sctx_done(&pstapriv->gotc2h); +} + /** * c2h = RXDESC + c2h packet * size = RXDESC_SIZE + c2h packet size @@ -1303,7 +1323,7 @@ static void process_c2h_event(PADAPTER adapter, u8 *c2h, u32 size) PHAL_DATA_TYPE hal; struct mlme_ext_priv *pmlmeext; struct mlme_ext_info *pmlmeinfo; - PDM_ODM_T pDM_Odm; + struct PHY_DM_STRUCT *p_dm_odm; u8 id, seq; u8 c2h_len, c2h_payload_len; u8 *pc2h_data, *pc2h_payload; @@ -1321,7 +1341,7 @@ static void process_c2h_event(PADAPTER adapter, u8 *c2h, u32 size) } hal = GET_HAL_DATA(adapter); - pDM_Odm = &hal->odmpriv; + p_dm_odm = &hal->odmpriv; pmlmeext = &adapter->mlmeextpriv; pmlmeinfo = &pmlmeext->mlmext_info; @@ -1337,29 +1357,41 @@ static void process_c2h_event(PADAPTER adapter, u8 *c2h, u32 size) c2h_payload_len = c2h_len - 2; switch (id) { +#ifdef CONFIG_BEAMFORMING + case CMD_ID_C2H_SND_TXBF: + RTW_INFO("%s: [CMD_ID_C2H_SND_TXBF] len=%d\n", __FUNCTION__, c2h_payload_len); + rtw_bf_c2h_handler(adapter, id, pc2h_data, c2h_len); + break; +#endif /* CONFIG_BEAMFORMING */ + case CMD_ID_C2H_CCX_RPT: c2h_ccx_rpt(adapter, pc2h_data); break; -#ifdef CONFIG_BT_COEXIST - case C2H_BT_INFO: - rtw_btcoex_BtInfoNotify(adapter, c2h_payload_len, pc2h_payload); - break; - case C2H_BT_MP_INFO: - rtw_btcoex_BtMpRptNotify(adapter, c2h_payload_len, pc2h_payload); - break; - case C2H_BT_SCOREBOARD_STATUS: - rtw_btcoex_ScoreBoardStatusNotify(adapter, c2h_payload_len, pc2h_payload); - break; -#endif - /* FW offload C2H is 0xFF cmd according to halmac function - halmac_parse_c2h_packet */ - case 0xFF: + + case CMD_ID_C2H_AP_REQ_TXRPT: + /*RTW_INFO("[C2H], C2H_AP_REQ_TXRPT!!\n");*/ + C2HTxRPTHandler_8822b(adapter, pc2h_data, c2h_len); + break; + + case CMD_ID_C2H_SPECIAL_STATISTICS: + /*RTW_INFO("[C2H], C2H_SPC_STAT!!\n");*/ + C2HSPC_STAT_8822b(adapter, pc2h_data, c2h_len); + break; + + case C2H_EXTEND: + if (C2H_HDR_GET_C2H_SUB_CMD_ID(pc2h_data) == C2H_SUB_CMD_ID_CCX_RPT) { + /* Shift C2H HDR 4 bytes */ + c2h_ccx_rpt(adapter, pc2h_data + 4); + break; + } + /* indicate c2h pkt + rx desc to halmac */ rtw_halmac_c2h_handle(adapter_to_dvobj(adapter), c2h, size); break; - /* others for phydm */ + + /* others for c2h common code */ default: - if (!(phydm_c2H_content_parsing(pDM_Odm, id, c2h_payload_len, pc2h_payload))) - RTW_INFO("%s: [WARNING] unknown C2H(0x%02x)\n", __FUNCTION__, id); + c2h_handler(adapter, id, seq, c2h_payload_len, pc2h_payload); break; } } @@ -1385,8 +1417,9 @@ void rtl8822b_c2h_handler(PADAPTER adapter, u8 *pbuf, u16 length) */ void rtl8822b_c2h_handler_no_io(PADAPTER adapter, u8 *pbuf, u16 length) { - u8 id, seq, c2h_size; + u8 id, seq; u8 *pc2h_content; + u8 res; if ((length == 0) || (!pbuf)) @@ -1401,14 +1434,22 @@ void rtl8822b_c2h_handler_no_io(PADAPTER adapter, u8 *pbuf, u16 length) __FUNCTION__, id, seq, length); switch (id) { - /* no I/O, process directly */ + case CMD_ID_C2H_SND_TXBF: case CMD_ID_C2H_CCX_RPT: + case C2H_BT_MP_INFO: + case C2H_FW_CHNL_SWITCH_COMPLETE: + case C2H_IQK_FINISH: + case C2H_MCC: + case C2H_BCN_EARLY_RPT: + case C2H_EXTEND: + /* no I/O, process directly */ process_c2h_event(adapter, pbuf, length); break; - /* need I/O, run in command thread */ default: - if (rtw_c2h_packet_wk_cmd(adapter, pbuf, length) == _FAIL) + /* Others may need I/O, run in command thread */ + res = rtw_c2h_packet_wk_cmd(adapter, pbuf, length); + if (res == _FAIL) RTW_ERR("%s: C2H(%d) enqueue FAIL!\n", __FUNCTION__, id); break; } diff --git a/hal/rtl8822b/rtl8822b_halinit.c b/hal/rtl8822b/rtl8822b_halinit.c index 972e3cc..a58bf55 100644 --- a/hal/rtl8822b/rtl8822b_halinit.c +++ b/hal/rtl8822b/rtl8822b_halinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,17 +11,12 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8822B_HALINIT_C_ #include /* PADAPTER, basic_types.h and etc. */ #include /* GET_HAL_SPEC(), HAL_DATA_TYPE */ -#include "../hal_halmac.h" /* HALMAC_SECURITY_CAM_ENTRY_NUM_8822B */ +#include "../hal_halmac.h" /* HALMAC API */ #include "rtl8822b.h" @@ -31,13 +26,20 @@ void rtl8822b_init_hal_spec(PADAPTER adapter) hal_spec = GET_HAL_SPEC(adapter); + rtw_halmac_fill_hal_spec(adapter_to_dvobj(adapter), hal_spec); + hal_spec->ic_name = "rtl8822b"; hal_spec->macid_num = 128; - hal_spec->sec_cam_ent_num = HALMAC_SECURITY_CAM_ENTRY_NUM_8822B; - hal_spec->sec_cap = 0; - hal_spec->nss_num = 2; + /* hal_spec->sec_cam_ent_num follow halmac setting */ + hal_spec->sec_cap = SEC_CAP_CHK_BMC; + hal_spec->rfpath_num_2g = 2; + hal_spec->rfpath_num_5g = 2; + hal_spec->max_tx_cnt = 2; + hal_spec->tx_nss_num = 2; + hal_spec->rx_nss_num = 2; hal_spec->band_cap = BAND_CAP_2G | BAND_CAP_5G; hal_spec->bw_cap = BW_CAP_20M | BW_CAP_40M | BW_CAP_80M; + hal_spec->port_num = 5; hal_spec->proto_cap = PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | PROTO_CAP_11AC; hal_spec->wl_func = 0 @@ -45,6 +47,8 @@ void rtl8822b_init_hal_spec(PADAPTER adapter) | WL_FUNC_MIRACAST | WL_FUNC_TDLS ; + + hal_spec->hci_type = 0; } u32 rtl8822b_power_on(PADAPTER adapter) @@ -53,7 +57,7 @@ u32 rtl8822b_power_on(PADAPTER adapter) PHAL_DATA_TYPE hal; u8 bMacPwrCtrlOn; int err = 0; - u8 ret = _TRUE; + u8 ret = _SUCCESS; d = adapter_to_dvobj(adapter); @@ -65,19 +69,14 @@ u32 rtl8822b_power_on(PADAPTER adapter) err = rtw_halmac_poweron(d); if (err) { - RTW_INFO("%s: Power ON Fail!!\n", __FUNCTION__); - ret = _FALSE; + RTW_ERR("%s: Power ON Fail!!\n", __FUNCTION__); + ret = _FAIL; goto out; } bMacPwrCtrlOn = _TRUE; rtw_hal_set_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); -#ifdef CONFIG_BT_COEXIST - hal = GET_HAL_DATA(adapter); - if (hal->EEPROMBluetoothCoexist) - rtw_btcoex_PowerOnSetting(adapter); -#endif /* CONFIG_BT_COEXIST */ out: return ret; } @@ -98,58 +97,65 @@ void rtl8822b_power_off(PADAPTER adapter) err = rtw_halmac_poweroff(d); if (err) { - RTW_INFO("%s: Power OFF Fail!!\n", __FUNCTION__); + RTW_ERR("%s: Power OFF Fail!!\n", __FUNCTION__); goto out; } bMacPwrCtrlOn = _FALSE; rtw_hal_set_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); - adapter->bFWReady = _FALSE; + GET_HAL_DATA(adapter)->bFWReady = _FALSE; out: return; } -#ifdef CONFIG_EMBEDDED_FWIMG -/* New FW array is TBD. So use phydm FW. - * TODO remove extern reference after FW array is defined - */ -extern u8 Array_MP_8822B_FW_NIC[]; -extern u32 ArrayLength_MP_8822B_FW_NIC; -#endif - u8 rtl8822b_hal_init(PADAPTER adapter) { struct dvobj_priv *d; PHAL_DATA_TYPE hal; int err; - + u8 fw_bin = _TRUE; d = adapter_to_dvobj(adapter); hal = GET_HAL_DATA(adapter); - adapter->bFWReady = _FALSE; + hal->bFWReady = _FALSE; hal->fw_ractrl = _FALSE; -#ifdef CONFIG_EMBEDDED_FWIMG - RTW_INFO("%s: Load embedded fw img\n", __FUNCTION__); - err = rtw_halmac_init_hal_fw(d, Array_MP_8822B_FW_NIC, ArrayLength_MP_8822B_FW_NIC); -#else - RTW_INFO("%s: Load fw file\n", __FUNCTION__); - err = rtw_halmac_init_hal_fw_file(d, REALTEK_CONFIG_PATH "RTL8822Bfw_NIC.bin"); -#endif +#ifdef CONFIG_FILE_FWIMG + rtw_get_phy_file_path(adapter, MAC_FILE_FW_NIC); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { + RTW_INFO("%s acquire FW from file:%s\n", __FUNCTION__, rtw_phy_para_file_path); + fw_bin = _TRUE; + } else +#endif /* CONFIG_FILE_FWIMG */ + { + RTW_INFO("%s fw source from array\n", __FUNCTION__); + fw_bin = _FALSE; + } + +#ifdef CONFIG_FILE_FWIMG + if (_TRUE == fw_bin) + err = rtw_halmac_init_hal_fw_file(d, rtw_phy_para_file_path); + else +#endif /* CONFIG_FILE_FWIMG */ + err = rtw_halmac_init_hal_fw(d, array_mp_8822b_fw_nic, array_length_mp_8822b_fw_nic); + if (err) { - RTW_INFO("%s: fail\n", __FUNCTION__); + RTW_ERR("%s Download Firmware from %s failed\n", __FUNCTION__, (fw_bin) ? "file" : "array"); return _FALSE; } - RTW_INFO("%s: successful, fw_ver=%d fw_subver=%d\n", __FUNCTION__, hal->FirmwareVersion, hal->FirmwareSubVersion); + + RTW_INFO("%s Download Firmware from %s success\n", __FUNCTION__, (fw_bin) ? "file" : "array"); + RTW_INFO("%s FW Version:%d SubVersion:%d FW size:%d\n", "NIC", + hal->firmware_version, hal->firmware_sub_version, hal->firmware_size); /* Sync driver status with hardware setting */ rtl8822b_rcr_get(adapter, NULL); - adapter->bFWReady = _TRUE; + hal->bFWReady = _TRUE; hal->fw_ractrl = _TRUE; return _TRUE; @@ -188,7 +194,7 @@ void rtl8822b_init_misc(PADAPTER adapter) */ /* initial channel setting */ - if (IS_A_CUT(hal->VersionID) || IS_B_CUT(hal->VersionID)) { + if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) { /* for A/B cut use under only 5G */ u8 i = 0; struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); @@ -208,8 +214,10 @@ void rtl8822b_init_misc(PADAPTER adapter) } } - hal->CurrentBandType = BAND_MAX; - set_channel_bwmode(adapter, adapter->registrypriv.channel, 0, 0); + /* Modify to make sure first time change channel(band) would be done properly */ + hal->current_channel = 0; + hal->current_channel_bw = CHANNEL_WIDTH_MAX; + hal->current_band_type = BAND_MAX; /* initial security setting */ invalidate_cam_all(adapter); @@ -219,6 +227,16 @@ void rtl8822b_init_misc(PADAPTER adapter) /* clear rx ctrl frame */ rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0); + + /*Enable MAC security engine*/ + rtw_write16(adapter, REG_CR, (rtw_read16(adapter, REG_CR) | BIT_MAC_SEC_EN)); + +#ifdef CONFIG_XMIT_ACK + /* ack for xmit mgmt frames. */ + rtw_write32(adapter, REG_FWHW_TXQ_CTRL_8822B, + rtw_read32(adapter, REG_FWHW_TXQ_CTRL_8822B) | BIT_EN_QUEUE_RPT_8822B(BIT(4))); +#endif /* CONFIG_XMIT_ACK */ + } u32 rtl8822b_init(PADAPTER adapter) @@ -234,13 +252,17 @@ u32 rtl8822b_init(PADAPTER adapter) rtl8822b_phy_init_haldm(adapter); #ifdef CONFIG_BEAMFORMING - rtl8822b_phy_init_beamforming(adapter); + rtl8822b_phy_bf_init(adapter); #endif #ifdef CONFIG_BT_COEXIST /* Init BT hw config. */ if (_TRUE == hal->EEPROMBluetoothCoexist) rtw_btcoex_HAL_Initialize(adapter, _FALSE); + else + rtw_btcoex_wifionly_hw_config(adapter); +#else /* CONFIG_BT_COEXIST */ + rtw_btcoex_wifionly_hw_config(adapter); #endif /* CONFIG_BT_COEXIST */ rtl8822b_init_misc(adapter); @@ -258,7 +280,7 @@ u32 rtl8822b_deinit(PADAPTER adapter) d = adapter_to_dvobj(adapter); hal = GET_HAL_DATA(adapter); - adapter->bFWReady = _FALSE; + hal->bFWReady = _FALSE; hal->fw_ractrl = _FALSE; err = rtw_halmac_deinit_hal(d); @@ -276,7 +298,8 @@ void rtl8822b_init_default_value(PADAPTER adapter) hal = GET_HAL_DATA(adapter); - adapter->registrypriv.wireless_mode = WIRELESS_MODE_24G | WIRELESS_MODE_5G; + if (adapter->registrypriv.wireless_mode == WIRELESS_MODE_MAX) + adapter->registrypriv.wireless_mode = WIRELESS_MODE_24G | WIRELESS_MODE_5G; /* init default value */ hal->fw_ractrl = _FALSE; @@ -286,15 +309,15 @@ void rtl8822b_init_default_value(PADAPTER adapter) /* init phydm default value */ hal->bIQKInitialized = _FALSE; - hal->odmpriv.RFCalibrateInfo.TM_Trigger = 0; /* for IQK */ - hal->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0; + hal->odmpriv.rf_calibrate_info.tm_trigger = 0; /* for IQK */ + hal->odmpriv.rf_calibrate_info.thermal_value_hp_index = 0; for (i = 0; i < HP_THERMAL_NUM; i++) - hal->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0; + hal->odmpriv.rf_calibrate_info.thermal_value_hp[i] = 0; /* init Efuse variables */ hal->EfuseUsedBytes = 0; hal->EfuseUsedPercentage = 0; -#ifdef HAL_EFUSE_MEMORY + hal->EfuseHal.fakeEfuseBank = 0; hal->EfuseHal.fakeEfuseUsedBytes = 0; _rtw_memset(hal->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE); @@ -309,5 +332,5 @@ void rtl8822b_init_default_value(PADAPTER adapter) _rtw_memset(hal->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE); _rtw_memset(hal->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); _rtw_memset(hal->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); -#endif + } diff --git a/hal/rtl8822b/rtl8822b_mac.c b/hal/rtl8822b/rtl8822b_mac.c index 3b0fe69..4ceac65 100644 --- a/hal/rtl8822b/rtl8822b_mac.c +++ b/hal/rtl8822b/rtl8822b_mac.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,17 +11,13 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8822B_MAC_C_ #include /* PADAPTER, basic_types.h and etc. */ #include /* HAL_DATA_TYPE */ #include "../hal_halmac.h" /* Register Definition and etc. */ +#include "rtl8822b.h" /* FW array */ inline u8 rtl8822b_rcr_config(PADAPTER p, u32 rcr) @@ -165,22 +161,55 @@ inline u8 rtl8822b_rx_tsf_addr_filter_config(PADAPTER p, u8 config) */ s32 rtl8822b_fw_dl(PADAPTER adapter, u8 wowlan) { - struct dvobj_priv *d; + struct dvobj_priv *d = adapter_to_dvobj(adapter); + HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); int err; + u8 fw_bin = _TRUE; - - if (_TRUE == wowlan) { - RTW_INFO("%s: NOT support WOWLan firmware yet!\n", __FUNCTION__); - return _FAIL; +#ifdef CONFIG_FILE_FWIMG +#ifdef CONFIG_WOWLAN + if (wowlan) + rtw_get_phy_file_path(adapter, MAC_FILE_FW_WW_IMG); + else +#endif /* CONFIG_WOWLAN */ + rtw_get_phy_file_path(adapter, MAC_FILE_FW_NIC); + + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { + RTW_INFO("%s acquire FW from file:%s\n", __FUNCTION__, rtw_phy_para_file_path); + fw_bin = _TRUE; + } else +#endif /* CONFIG_FILE_FWIMG */ + { + RTW_INFO("%s fw source from array\n", __FUNCTION__); + fw_bin = _FALSE; } - d = adapter_to_dvobj(adapter); - - err = rtw_halmac_dlfw_from_file(d, REALTEK_CONFIG_PATH "RTL8822Bfw_NIC.bin"); - if (err) { - RTW_INFO("%s: Download Firmware fail\n", __FUNCTION__); - return _FALSE; +#ifdef CONFIG_FILE_FWIMG + if (_TRUE == fw_bin) { + err = rtw_halmac_dlfw_from_file(d, rtw_phy_para_file_path); + } else +#endif /* CONFIG_FILE_FWIMG */ + { + #ifdef CONFIG_WOWLAN + if (_TRUE == wowlan) + err = rtw_halmac_dlfw(d, array_mp_8822b_fw_wowlan, array_length_mp_8822b_fw_wowlan); + else + #endif /* CONFIG_WOWLAN */ + err = rtw_halmac_dlfw(d, array_mp_8822b_fw_nic, array_length_mp_8822b_fw_nic); } - return _SUCCESS; + if (!err) { + hal->bFWReady = _TRUE; + hal->fw_ractrl = _TRUE; + RTW_INFO("%s Download Firmware from %s success\n", __FUNCTION__, (fw_bin) ? "file" : "array"); + RTW_INFO("%s FW Version:%d SubVersion:%d FW size:%d\n", (wowlan) ? "WOW" : "NIC", + hal->firmware_version, hal->firmware_sub_version, hal->firmware_size); + return _SUCCESS; + } else { + hal->bFWReady = _FALSE; + hal->fw_ractrl = _FALSE; + RTW_ERR("%s Download Firmware from %s failed\n", __FUNCTION__, (fw_bin) ? "file" : "array"); + return _FAIL; + } } diff --git a/hal/rtl8822b/rtl8822b_ops.c b/hal/rtl8822b/rtl8822b_ops.c index a3ce948..96b1183 100644 --- a/hal/rtl8822b/rtl8822b_ops.c +++ b/hal/rtl8822b/rtl8822b_ops.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8822B_OPS_C_ #include /* basic_types.h, rtw_io.h and etc. */ @@ -31,6 +26,114 @@ #include "rtl8822b_hal.h" +static const struct hw_port_reg port_cfg[] = { + /*port 0*/ + { + .net_type = (REG_CR_8822B + 2), + .net_type_shift = 0, + .macaddr = REG_MACID_8822B, + .bssid = REG_BSSID_8822B, + .bcn_ctl = REG_BCN_CTRL_8822B, + .tsf_rst = REG_DUAL_TSF_RST, + .tsf_rst_bit = BIT_TSFTR_RST_8822B, + .bcn_space = REG_MBSSID_BCN_SPACE_8822B, + .bcn_space_shift = 0, + .bcn_space_mask = 0xffff, + .ps_aid = REG_BCN_PSR_RPT_8822B, + }, + /*port 1*/ + { + .net_type = (REG_CR_8822B + 2), + .net_type_shift = 2, + .macaddr = REG_MACID1_8822B, + .bssid = REG_BSSID1_8822B, + .bcn_ctl = REG_BCN_CTRL_CLINT0_8822B, + .tsf_rst = REG_DUAL_TSF_RST, + .tsf_rst_bit = BIT_TSFTR_CLI0_RST_8822B, + .bcn_space = REG_MBSSID_BCN_SPACE_8822B, + .bcn_space_shift = 16, + .bcn_space_mask = 0xfff, + .ps_aid = REG_BCN_PSR_RPT1_8822B, + }, + /*port 2*/ + { + .net_type = REG_CR_EXT_8822B, + .net_type_shift = 0, + .macaddr = REG_MACID2_8822B, + .bssid = REG_BSSID2_8822B, + .bcn_ctl = REG_BCN_CTRL_CLINT1_8822B, + .tsf_rst = REG_DUAL_TSF_RST, + .tsf_rst_bit = BIT_TSFTR_CLI1_RST_8822B, + .bcn_space = REG_MBSSID_BCN_SPACE2_8822B, + .bcn_space_shift = 0, + .bcn_space_mask = 0xfff, + .ps_aid = REG_BCN_PSR_RPT2_8822B, + }, + /*port 3*/ + { + .net_type = REG_CR_EXT_8822B, + .net_type_shift = 2, + .macaddr = REG_MACID3_8822B, + .bssid = REG_BSSID3_8822B, + .bcn_ctl = REG_BCN_CTRL_CLINT2_8822B, + .tsf_rst = REG_DUAL_TSF_RST, + .tsf_rst_bit = BIT_TSFTR_CLI2_RST_8822B, + .bcn_space = REG_MBSSID_BCN_SPACE2_8822B, + .bcn_space_shift = 16, + .bcn_space_mask = 0xfff, + .ps_aid = REG_BCN_PSR_RPT3_8822B, + }, + /*port 4*/ + { + .net_type = REG_CR_EXT_8822B, + .net_type_shift = 4, + .macaddr = REG_MACID4_8822B, + .bssid = REG_BSSID4_8822B, + .bcn_ctl = REG_BCN_CTRL_CLINT3_8822B, + .tsf_rst = REG_DUAL_TSF_RST, + .tsf_rst_bit = BIT_TSFTR_CLI3_RST_8822B, + .bcn_space = REG_MBSSID_BCN_SPACE3_8822B, + .bcn_space_shift = 0, + .bcn_space_mask = 0xfff, + .ps_aid = REG_BCN_PSR_RPT4_8822B, + }, +}; + +static void hw_bcn_ctrl_add(_adapter *adapter, u8 bcn_ctl_val) +{ + u8 hw_port = get_hw_port(adapter); + u32 bcn_ctl_addr = 0; + u8 val8 = 0; + + if (hw_port >= MAX_HW_PORT) { + RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port); + rtw_warn_on(1); + return; + } + + bcn_ctl_addr = port_cfg[hw_port].bcn_ctl; + val8 = rtw_read8(adapter, bcn_ctl_addr) | bcn_ctl_val; + rtw_write8(adapter, bcn_ctl_addr, val8); +} + +static void hw_bcn_ctrl_clr(_adapter *adapter, u8 bcn_ctl_val) +{ + u8 hw_port = get_hw_port(adapter); + u32 bcn_ctl_addr = 0; + u8 val8 = 0; + + if (hw_port >= MAX_HW_PORT) { + RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port); + rtw_warn_on(1); + return; + } + + bcn_ctl_addr = port_cfg[hw_port].bcn_ctl; + val8 = rtw_read8(adapter, bcn_ctl_addr); + val8 &= ~bcn_ctl_val; + rtw_write8(adapter, bcn_ctl_addr, val8); +} + static void read_chip_version(PADAPTER adapter) { PHAL_DATA_TYPE hal; @@ -40,31 +143,31 @@ static void read_chip_version(PADAPTER adapter) hal = GET_HAL_DATA(adapter); value32 = rtw_read32(adapter, REG_SYS_CFG1_8822B); - hal->VersionID.ICType = CHIP_8822B; - hal->VersionID.ChipType = ((value32 & BIT_RTL_ID_8822B) ? TEST_CHIP : NORMAL_CHIP); - hal->VersionID.CUTVersion = BIT_GET_CHIP_VER_8822B(value32); - hal->VersionID.VendorType = BIT_GET_VENDOR_ID_8822B(value32); - hal->VersionID.VendorType >>= 2; - switch (hal->VersionID.VendorType) { + hal->version_id.ICType = CHIP_8822B; + hal->version_id.ChipType = ((value32 & BIT_RTL_ID_8822B) ? TEST_CHIP : NORMAL_CHIP); + hal->version_id.CUTVersion = BIT_GET_CHIP_VER_8822B(value32); + hal->version_id.VendorType = BIT_GET_VENDOR_ID_8822B(value32); + hal->version_id.VendorType >>= 2; + switch (hal->version_id.VendorType) { case 0: - hal->VersionID.VendorType = CHIP_VENDOR_TSMC; + hal->version_id.VendorType = CHIP_VENDOR_TSMC; break; case 1: - hal->VersionID.VendorType = CHIP_VENDOR_SMIC; + hal->version_id.VendorType = CHIP_VENDOR_SMIC; break; case 2: - hal->VersionID.VendorType = CHIP_VENDOR_UMC; + hal->version_id.VendorType = CHIP_VENDOR_UMC; break; } - hal->VersionID.RFType = ((value32 & BIT_RF_TYPE_ID_8822B) ? RF_TYPE_2T2R : RF_TYPE_1T1R); + hal->version_id.RFType = ((value32 & BIT_RF_TYPE_ID_8822B) ? RF_TYPE_2T2R : RF_TYPE_1T1R); if (adapter->registrypriv.special_rf_path == 1) - hal->VersionID.RFType = RF_TYPE_1T1R; /* RF_1T1R; */ + hal->version_id.RFType = RF_TYPE_1T1R; /* RF_1T1R; */ hal->RegulatorMode = ((value32 & BIT_SPSLDO_SEL_8822B) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR); value32 = rtw_read32(adapter, REG_SYS_STATUS1_8822B); - hal->VersionID.ROMVer = BIT_GET_RF_RL_ID_8822B(value32); + hal->version_id.ROMVer = BIT_GET_RF_RL_ID_8822B(value32); /* For multi-function consideration. */ hal->MultiFunc = RT_MULTI_FUNC_NONE; @@ -75,7 +178,7 @@ static void read_chip_version(PADAPTER adapter) rtw_hal_config_rftype(adapter); - dump_chip_info(hal->VersionID); + dump_chip_info(hal->version_id); } /* @@ -111,320 +214,13 @@ static void Hal_EfuseParseEEPROMVer(PADAPTER adapter, u8 *map, u8 mapvalid) RTW_INFO("EEPROM Version = %d\n", hal->EEPROMVersion); } -static u8 Hal_GetChnlGroup(u8 chnl, u8 *pGroup) -{ - u8 bIn24G = _TRUE; - - - if (chnl <= 14) { - bIn24G = _TRUE; - - if (1 <= chnl && chnl <= 2) - *pGroup = 0; - else if (3 <= chnl && chnl <= 5) - *pGroup = 1; - else if (6 <= chnl && chnl <= 8) - *pGroup = 2; - else if (9 <= chnl && chnl <= 11) - *pGroup = 3; - else if (12 <= chnl && chnl <= 14) - *pGroup = 4; - else - RTW_INFO("%s: in 2.4 G, but Channel %d in Group not found\n", __FUNCTION__, chnl); - } else { - bIn24G = _FALSE; - - if (36 <= chnl && chnl <= 42) - *pGroup = 0; - else if (44 <= chnl && chnl <= 48) - *pGroup = 1; - else if (50 <= chnl && chnl <= 58) - *pGroup = 2; - else if (60 <= chnl && chnl <= 64) - *pGroup = 3; - else if (100 <= chnl && chnl <= 106) - *pGroup = 4; - else if (108 <= chnl && chnl <= 114) - *pGroup = 5; - else if (116 <= chnl && chnl <= 122) - *pGroup = 6; - else if (124 <= chnl && chnl <= 130) - *pGroup = 7; - else if (132 <= chnl && chnl <= 138) - *pGroup = 8; - else if (140 <= chnl && chnl <= 144) - *pGroup = 9; - else if (149 <= chnl && chnl <= 155) - *pGroup = 10; - else if (157 <= chnl && chnl <= 161) - *pGroup = 11; - else if (165 <= chnl && chnl <= 171) - *pGroup = 12; - else if (173 <= chnl && chnl <= 177) - *pGroup = 13; - else - RTW_INFO("%s: in 5G, but Channel %d in Group not found\n", __FUNCTION__, chnl); - } - - return bIn24G; -} - -static void load_default_txpower(PADAPTER adapter, PTxPowerInfo24G tbl2g4, PTxPowerInfo5G tbl5g) -{ - u32 rfpath, group, txcount; - - - for (rfpath = 0; rfpath < MAX_RF_PATH; rfpath++) { - /* 2.4G default value */ - for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { - tbl2g4->IndexCCK_Base[rfpath][group] = EEPROM_DEFAULT_24G_INDEX; - tbl2g4->IndexBW40_Base[rfpath][group] = EEPROM_DEFAULT_24G_INDEX; - } - for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { - if (txcount == 0) { - tbl2g4->BW20_Diff[rfpath][0] = EEPROM_DEFAULT_24G_HT20_DIFF; - tbl2g4->OFDM_Diff[rfpath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF; - } else { - tbl2g4->BW20_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF; - tbl2g4->BW40_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF; - tbl2g4->CCK_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF; - tbl2g4->OFDM_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF; - } - } - - /* 5G default value */ - for (group = 0; group < MAX_CHNL_GROUP_5G; group++) - tbl5g->IndexBW40_Base[rfpath][group] = EEPROM_DEFAULT_5G_INDEX; - for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { - if (txcount == 0) { - tbl5g->OFDM_Diff[rfpath][0] = EEPROM_DEFAULT_5G_OFDM_DIFF; - tbl5g->BW20_Diff[rfpath][0] = EEPROM_DEFAULT_5G_HT20_DIFF; - tbl5g->BW80_Diff[rfpath][0] = EEPROM_DEFAULT_DIFF; - tbl5g->BW160_Diff[rfpath][0] = EEPROM_DEFAULT_DIFF; - } else { - tbl5g->OFDM_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF; - tbl5g->BW20_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF; - tbl5g->BW40_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF; - tbl5g->BW80_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF; - tbl5g->BW160_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF; - } - } - } -} - -static inline u8 power_valid(u8 power) -{ - if (power <= 63) - return _TRUE; - - return _FALSE; -} - -static inline s8 power_diff(s8 diff) -{ - /* bit sign number to 8 bit sign number */ - if (diff & BIT(3)) - diff |= 0xF0; - - return diff; -} - -static void load_txpower_from_map( - PADAPTER adapter, PTxPowerInfo24G tbl2g4, PTxPowerInfo5G tbl5g, - u8 *map, u8 mapvalid) -{ - PHAL_DATA_TYPE hal; - u32 rfpath, eeAddr, group, txcount = 0; - u8 power; - s8 diff; - - - hal = GET_HAL_DATA(adapter); - - hal->bTXPowerDataReadFromEEPORM = _FALSE; - _rtw_memset(tbl2g4, 0, sizeof(TxPowerInfo24G)); - _rtw_memset(tbl5g, 0, sizeof(TxPowerInfo5G)); - load_default_txpower(adapter, tbl2g4, tbl5g); - - if (_FALSE == mapvalid) - return; - - eeAddr = EEPROM_TX_PWR_INX_8822B; - if (0xFF == map[eeAddr]) - return; - - hal->bTXPowerDataReadFromEEPORM = _TRUE; - - for (rfpath = 0; rfpath < hal->NumTotalRFPath; rfpath++) { - /* 2.4G */ - for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { - power = map[eeAddr++]; - if (power_valid(power) == _TRUE) - tbl2g4->IndexCCK_Base[rfpath][group] = power; - } - - for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) { - power = map[eeAddr++]; - if (power_valid(power) == _TRUE) - tbl2g4->IndexBW40_Base[rfpath][group] = power; - } - - for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { - if (txcount == 0) { - tbl2g4->BW40_Diff[rfpath][0] = 0; - - diff = (map[eeAddr] & 0xF0) >> 4; - tbl2g4->BW20_Diff[rfpath][0] = power_diff(diff); - - diff = map[eeAddr] & 0x0F; - tbl2g4->OFDM_Diff[rfpath][0] = power_diff(diff); - - tbl2g4->CCK_Diff[rfpath][0] = 0; - - eeAddr++; - } else { - diff = (map[eeAddr] & 0xF0) >> 4; - tbl2g4->BW40_Diff[rfpath][txcount] = power_diff(diff); - - diff = map[eeAddr] & 0x0F; - tbl2g4->BW20_Diff[rfpath][txcount] = power_diff(diff); - - eeAddr++; - - diff = (map[eeAddr] & 0xF0) >> 4; - tbl2g4->OFDM_Diff[rfpath][txcount] = power_diff(diff); - - diff = map[eeAddr] & 0x0F; - tbl2g4->CCK_Diff[rfpath][txcount] = power_diff(diff); - - eeAddr++; - } - } - - /* 5G */ - for (group = 0; group < MAX_CHNL_GROUP_5G; group++) { - power = map[eeAddr++]; - if (power_valid(power) == _TRUE) - tbl5g->IndexBW40_Base[rfpath][group] = power; - } - - for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { - if (txcount == 0) { - tbl5g->BW40_Diff[rfpath][0] = 0; - - diff = (map[eeAddr] & 0xF0) >> 4; - tbl5g->BW20_Diff[rfpath][0] = power_diff(diff); - - diff = map[eeAddr] & 0x0F; - tbl5g->OFDM_Diff[rfpath][0] = power_diff(diff); - - eeAddr++; - } else { - diff = (map[eeAddr] & 0xF0) >> 4; - tbl5g->BW40_Diff[rfpath][txcount] = power_diff(diff); - - diff = map[eeAddr] & 0x0F; - tbl5g->BW20_Diff[rfpath][txcount] = power_diff(diff); - - eeAddr++; - } - } - - diff = (map[eeAddr] & 0xF0) >> 4; - tbl5g->OFDM_Diff[rfpath][1] = power_diff(diff); - - diff = map[eeAddr] & 0x0F; - tbl5g->OFDM_Diff[rfpath][2] = power_diff(diff); - - eeAddr++; - - diff = map[eeAddr] & 0x0F; - tbl5g->OFDM_Diff[rfpath][3] = power_diff(diff); - - eeAddr++; - - for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) { - diff = (map[eeAddr] & 0xF0) >> 4; - tbl5g->BW80_Diff[rfpath][txcount] = power_diff(diff); - - diff = map[eeAddr] & 0x0F; - tbl5g->BW160_Diff[rfpath][txcount] = power_diff(diff); - - eeAddr++; - } - } -} - static void Hal_EfuseParseTxPowerInfo(PADAPTER adapter, u8 *map, u8 mapvalid) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); TxPowerInfo24G tbl2G4; TxPowerInfo5G tbl5g; - u8 rfpath, ch, group = 0, txcount = 1; - - - load_txpower_from_map(adapter, &tbl2G4, &tbl5g, map, mapvalid); - - for (rfpath = 0; rfpath < hal->NumTotalRFPath; rfpath++) { - for (ch = 0; ch < CENTER_CH_2G_NUM; ch++) { - Hal_GetChnlGroup(ch + 1, &group); - - if (ch == 14 - 1) { - hal->Index24G_CCK_Base[rfpath][ch] = tbl2G4.IndexCCK_Base[rfpath][5]; - hal->Index24G_BW40_Base[rfpath][ch] = tbl2G4.IndexBW40_Base[rfpath][group]; - } else { - hal->Index24G_CCK_Base[rfpath][ch] = tbl2G4.IndexCCK_Base[rfpath][group]; - hal->Index24G_BW40_Base[rfpath][ch] = tbl2G4.IndexBW40_Base[rfpath][group]; - } - RTW_INFO("======= Path %d, Channel %d, Group %d =======\n", rfpath, ch + 1, group); - RTW_INFO("Index24G_CCK_Base[%d][%d]=0x%x\n", rfpath, ch, hal->Index24G_CCK_Base[rfpath][ch]); - RTW_INFO("Index24G_BW40_Base[%d][%d]=0x%x\n", rfpath, ch, hal->Index24G_BW40_Base[rfpath][ch]); - } - - for (ch = 0; ch < CENTER_CH_5G_ALL_NUM; ch++) { - Hal_GetChnlGroup(center_ch_5g_all[ch], &group); - hal->Index5G_BW40_Base[rfpath][ch] = tbl5g.IndexBW40_Base[rfpath][group]; - - RTW_INFO("======= Path %d, Channel %d, Group %d =======\n", rfpath, center_ch_5g_all[ch], group); - RTW_INFO("Index5G_BW40_Base[%d][%d]=0x%x\n", rfpath, ch, hal->Index5G_BW40_Base[rfpath][ch]); - } - - for (ch = 0; ch < CENTER_CH_5G_80M_NUM; ch++) { - u8 upper = 0, lower = 0; - - Hal_GetChnlGroup(center_ch_5g_80m[ch], &group); - upper = tbl5g.IndexBW40_Base[rfpath][group]; - lower = tbl5g.IndexBW40_Base[rfpath][group + 1]; - hal->Index5G_BW80_Base[rfpath][ch] = (upper + lower) / 2; - - RTW_INFO("======= Path %d, Channel %d, Group %d =======\n", rfpath, center_ch_5g_80m[ch], group); - RTW_INFO("Index5G_BW80_Base[%d][%d]=0x%x\n", rfpath, ch, hal->Index5G_BW80_Base[rfpath][ch]); - } - - for (txcount = 0; txcount < hal->NumTotalRFPath; txcount++) { - hal->CCK_24G_Diff[rfpath][txcount] = tbl2G4.CCK_Diff[rfpath][txcount]; - hal->OFDM_24G_Diff[rfpath][txcount] = tbl2G4.OFDM_Diff[rfpath][txcount]; - hal->BW20_24G_Diff[rfpath][txcount] = tbl2G4.BW20_Diff[rfpath][txcount]; - hal->BW40_24G_Diff[rfpath][txcount] = tbl2G4.BW40_Diff[rfpath][txcount]; - - hal->OFDM_5G_Diff[rfpath][txcount] = tbl5g.OFDM_Diff[rfpath][txcount]; - hal->BW20_5G_Diff[rfpath][txcount] = tbl5g.BW20_Diff[rfpath][txcount]; - hal->BW40_5G_Diff[rfpath][txcount] = tbl5g.BW40_Diff[rfpath][txcount]; - hal->BW80_5G_Diff[rfpath][txcount] = tbl5g.BW80_Diff[rfpath][txcount]; - - RTW_INFO("----------------------------------- 2.4G %dSS ----------------------------------\n", txcount + 1); - RTW_INFO("CCK_24G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->CCK_24G_Diff[rfpath][txcount]); - RTW_INFO("OFDM_24G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->OFDM_24G_Diff[rfpath][txcount]); - RTW_INFO("BW20_24G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->BW20_24G_Diff[rfpath][txcount]); - RTW_INFO("BW40_24G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->BW40_24G_Diff[rfpath][txcount]); - RTW_INFO("------------------------------------ 5G %dSS -----------------------------------\n", txcount + 1); - RTW_INFO("OFDM_5G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->OFDM_5G_Diff[rfpath][txcount]); - RTW_INFO("BW20_5G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->BW20_5G_Diff[rfpath][txcount]); - RTW_INFO("BW40_5G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->BW40_5G_Diff[rfpath][txcount]); - RTW_INFO("BW80_5G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->BW80_5G_Diff[rfpath][txcount]); - } - } + hal_load_txpwr_info(adapter, &tbl2G4, &tbl5g, map); if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8822B] != 0xFF)) hal->EEPROMRegulatory = map[EEPROM_RF_BOARD_OPTION_8822B] & 0x7; /* bit0~2 */ @@ -449,9 +245,16 @@ static void Hal_EfuseParseBoardType(PADAPTER adapter, u8 *map, u8 mapvalid) static void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); u8 setting; u32 tmpu4; +#ifdef CONFIG_RTW_MAC_HIDDEN_RPT + if (hal_spec->hci_type <= 3 && hal_spec->hci_type >= 1) { + hal->EEPROMBluetoothCoexist = _FALSE; + goto exit; + } +#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */ if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8822B] != 0xFF)) { /* 0xc1[7:5] = 0x01 */ @@ -477,6 +280,7 @@ static void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid) hal->ant_path = ODM_RF_PATH_A; } +exit: RTW_INFO("EEPROM %s BT-coex, ant_num=%d\n", hal->EEPROMBluetoothCoexist == _TRUE ? "Enable" : "Disable", hal->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1); @@ -484,7 +288,7 @@ static void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid) static void Hal_EfuseParseChnlPlan(PADAPTER adapter, u8 *map, u8 autoloadfail) { - adapter->mlmepriv.ChannelPlan = hal_com_config_channel_plan( + hal_com_config_channel_plan( adapter, map ? &map[EEPROM_COUNTRY_CODE_8822B] : NULL, map ? map[EEPROM_ChannelPlan_8822B] : 0xFF, @@ -493,8 +297,6 @@ static void Hal_EfuseParseChnlPlan(PADAPTER adapter, u8 *map, u8 autoloadfail) RTW_CHPLAN_REALTEK_DEFINE, autoloadfail ); - - RTW_INFO("EEPROM ChannelPlan=0x%02x\n", adapter->mlmepriv.ChannelPlan); } static void Hal_EfuseParseXtal(PADAPTER adapter, u8 *map, u8 mapvalid) @@ -503,11 +305,11 @@ static void Hal_EfuseParseXtal(PADAPTER adapter, u8 *map, u8 mapvalid) if ((_TRUE == mapvalid) && map[EEPROM_XTAL_8822B] != 0xFF) - hal->CrystalCap = map[EEPROM_XTAL_8822B]; + hal->crystal_cap = map[EEPROM_XTAL_8822B]; else - hal->CrystalCap = EEPROM_Default_CrystalCap; + hal->crystal_cap = EEPROM_Default_CrystalCap; - RTW_INFO("EEPROM CrystalCap=0x%02x\n", hal->CrystalCap); + RTW_INFO("EEPROM crystal_cap=0x%02x\n", hal->crystal_cap); } static void Hal_EfuseParseThermalMeter(PADAPTER adapter, u8 *map, u8 mapvalid) @@ -517,13 +319,13 @@ static void Hal_EfuseParseThermalMeter(PADAPTER adapter, u8 *map, u8 mapvalid) /* ThermalMeter from EEPROM */ if ((_TRUE == mapvalid) && (map[EEPROM_THERMAL_METER_8822B] != 0xFF)) - hal->EEPROMThermalMeter = map[EEPROM_THERMAL_METER_8822B]; + hal->eeprom_thermal_meter = map[EEPROM_THERMAL_METER_8822B]; else { - hal->EEPROMThermalMeter = EEPROM_Default_ThermalMeter; - hal->odmpriv.RFCalibrateInfo.bAPKThermalMeterIgnore = _TRUE; + hal->eeprom_thermal_meter = EEPROM_Default_ThermalMeter; + hal->odmpriv.rf_calibrate_info.is_apk_thermal_meter_ignore = _TRUE; } - RTW_INFO("EEPROM ThermalMeter=0x%02x\n", hal->EEPROMThermalMeter); + RTW_INFO("EEPROM ThermalMeter=0x%02x\n", hal->eeprom_thermal_meter); } static void Hal_EfuseParseAntennaDiversity(PADAPTER adapter, u8 *map, u8 mapvalid) @@ -553,12 +355,12 @@ static void Hal_EfuseParseAntennaDiversity(PADAPTER adapter, u8 *map, u8 mapvali hal->TRxAntDivType = S0S1_SW_ANTDIV; /* internal switch S0S1 */ else RTW_INFO("EEPROM efuse[0x%x]=0x%02x is unknown type\n", - __FUNCTION__, EEPROM_RFE_OPTION_8723B, hal->TRxAntDivType); + EEPROM_RFE_OPTION_8723B, hal->TRxAntDivType); } else hal->TRxAntDivType = registry_par->antdiv_type; RTW_INFO("EEPROM AntDivCfg=%d, AntDivType=%d\n", - __FUNCTION__, hal->AntDivCfg, hal->TRxAntDivType); + hal->AntDivCfg, hal->TRxAntDivType); #endif /* CONFIG_ANTENNA_DIVERSITY */ } @@ -617,17 +419,17 @@ static void hal_ReadPAType(PADAPTER adapter, u8 *map, u8 mapvalid) if (hal->LNAType_5G == 0xFF) hal->LNAType_5G = 0; - hal->ExternalPA_5G = (hal->PAType_5G & BIT0) ? 1 : 0; - hal->ExternalLNA_5G = (hal->LNAType_5G & BIT3) ? 1 : 0; + hal->external_pa_5g = (hal->PAType_5G & BIT0) ? 1 : 0; + hal->external_lna_5g = (hal->LNAType_5G & BIT3) ? 1 : 0; } else { - hal->ExternalPA_5G = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G) ? 1 : 0; - hal->ExternalLNA_5G = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0; + hal->external_pa_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G) ? 1 : 0; + hal->external_lna_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0; } } else { hal->ExternalPA_2G = EEPROM_Default_PAType; - hal->ExternalPA_5G = 0xFF; + hal->external_pa_5g = 0xFF; hal->ExternalLNA_2G = EEPROM_Default_LNAType; - hal->ExternalLNA_5G = 0xFF; + hal->external_lna_5g = 0xFF; /* AUTO */ if (GetRegAmplifierType2G(adapter) == 0) { @@ -640,18 +442,18 @@ static void hal_ReadPAType(PADAPTER adapter, u8 *map, u8 mapvalid) /* AUTO */ if (GetRegAmplifierType5G(adapter) == 0) { - hal->ExternalPA_5G = 0; - hal->ExternalLNA_5G = 0; + hal->external_pa_5g = 0; + hal->external_lna_5g = 0; } else { - hal->ExternalPA_5G = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G) ? 1 : 0; - hal->ExternalLNA_5G = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0; + hal->external_pa_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G) ? 1 : 0; + hal->external_lna_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0; } } RTW_INFO("EEPROM PAType_2G is 0x%x, ExternalPA_2G = %d\n", hal->PAType_2G, hal->ExternalPA_2G); - RTW_INFO("EEPROM PAType_5G is 0x%x, ExternalPA_5G = %d\n", hal->PAType_5G, hal->ExternalPA_5G); + RTW_INFO("EEPROM PAType_5G is 0x%x, external_pa_5g = %d\n", hal->PAType_5G, hal->external_pa_5g); RTW_INFO("EEPROM LNAType_2G is 0x%x, ExternalLNA_2G = %d\n", hal->LNAType_2G, hal->ExternalLNA_2G); - RTW_INFO("EEPROM LNAType_5G is 0x%x, ExternalLNA_5G = %d\n", hal->LNAType_5G, hal->ExternalLNA_5G); + RTW_INFO("EEPROM LNAType_5G is 0x%x, external_lna_5g = %d\n", hal->LNAType_5G, hal->external_lna_5g); } static void Hal_ReadAmplifierType(PADAPTER adapter, u8 *map, u8 mapvalid) @@ -690,60 +492,65 @@ static void Hal_ReadAmplifierType(PADAPTER adapter, u8 *map, u8 mapvalid) RTW_INFO("EEPROM TypeALNA = 0x%X\n", hal->TypeALNA); } -static void Hal_ReadRFEType(PADAPTER adapter, u8 *map, u8 mapvalid) +static u8 Hal_ReadRFEType(PADAPTER adapter, u8 *map, u8 mapvalid) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - /* check registry valye */ + /* check registry value */ if (GetRegRFEType(adapter) != CONFIG_RTW_RFE_TYPE) { - hal->RFEType = GetRegRFEType(adapter); + hal->rfe_type = GetRegRFEType(adapter); goto exit; } if (mapvalid) { /* check efuse map */ - hal->RFEType = ReadLE1Byte(&map[EEPROM_RFE_OPTION_8822B]); - if (0xFF != hal->RFEType) + hal->rfe_type = ReadLE1Byte(&map[EEPROM_RFE_OPTION_8822B]); + if (0xFF != hal->rfe_type) goto exit; } /* error handle */ - hal->RFEType = 0; - RTW_ERR("please pg efuse or change RFE_Type of registrypriv!!\n"); + hal->rfe_type = 0; + + /* If ignore incorrect rfe_type may cause card drop. */ + /* it's DIFFICULT do debug especially on COB project */ + RTW_ERR("\n\nEmpty EFUSE with unknown REF type!!\n\n"); + RTW_ERR("please program efuse or specify correct RFE type.\n"); + RTW_ERR("cmd: insmod rtl8822bx.ko rtw_RFE_type=\n\n"); + + return _FAIL; exit: - RTW_INFO("EEPROM RFEType=0x%x\n", hal->RFEType); + RTW_INFO("EEPROM rfe_type=0x%x\n", hal->rfe_type); + return _SUCCESS; } static void Hal_EfuseParsePackageType(PADAPTER adapter, u8 *map, u8 mapvalid) { } -#ifdef CONFIG_RF_POWER_TRIM -static void Hal_ReadRFGainOffset(PADAPTER adapter, u8 *map, u8 mapvalid) +static void Hal_EfuseParsePABias(PADAPTER adapter) { - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct hal_com_data *hal; + u8 data[2] = {0xFF, 0xFF}; + u8 ret; - /* - * BB_RF Gain Offset from EEPROM - */ - if ((_TRUE == mapvalid) || (adapter->registrypriv.RegPwrTrimEnable == 1)) { -#if 0 - hal->EEPROMRFGainOffset = map[EEPROM_RF_GAIN_OFFSET]; - hal->EEPROMRFGainVal = EFUSE_Read1Byte(adapter, EEPROM_RF_GAIN_VAL); -#else - hal->EEPROMRFGainOffset = 0; - hal->EEPROMRFGainVal = 0xFF; -#endif - } else { - hal->EEPROMRFGainOffset = 0; - hal->EEPROMRFGainVal = 0xFF; + + ret = rtw_efuse_access(adapter, 0, 0x3D7, 2, data); + if (_FAIL == ret) { + RTW_ERR("%s: Fail to read PA Bias from eFuse!\n", __FUNCTION__); + return; } - RTW_INFO("EEPROM RFGainOffset=0x%02x\n", hal->EEPROMRFGainOffset); - RTW_INFO("EEPROM RFGainVal=0x%02x\n", hal->EEPROMRFGainVal); + + hal = GET_HAL_DATA(adapter); + hal->efuse0x3d7 = data[0]; /* efuse[0x3D7] */ + hal->efuse0x3d8 = data[1]; /* efuse[0x3D8] */ + + RTW_INFO("EEPROM efuse[0x3D7]=0x%x\n", hal->efuse0x3d7); + RTW_INFO("EEPROM efuse[0x3D8]=0x%x\n", hal->efuse0x3d8); } -#endif /* CONFIG_RF_POWER_TRIM */ + #ifdef CONFIG_USB_HCI static void Hal_ReadUsbModeSwitch(PADAPTER adapter, u8 *map, u8 mapvalid) @@ -769,54 +576,34 @@ static void Hal_ReadUsbModeSwitch(PADAPTER adapter, u8 *map, u8 mapvalid) * 3. Read file if necessary * 4. Parsing Efuse data */ -void rtl8822b_read_efuse(PADAPTER adapter) +u8 rtl8822b_read_efuse(PADAPTER adapter) { - struct dvobj_priv *d; PHAL_DATA_TYPE hal; u8 val8; - u32 efuse_size; u8 *efuse_map = NULL; u8 valid; - int err; - HALMAC_EFUSE_READ_CFG cfg; + u8 ret = _FAIL; - d = adapter_to_dvobj(adapter); hal = GET_HAL_DATA(adapter); - efuse_size = EEPROM_MAX_SIZE; efuse_map = hal->efuse_eeprom_data; - err = rtw_halmac_get_logical_efuse_size(d, &efuse_size); - if (err || !efuse_size) { - RTW_INFO("%s: fail to get efuse size!\n", __FUNCTION__); - efuse_size = EEPROM_MAX_SIZE; - } - if (efuse_size > EEPROM_MAX_SIZE) { - RTW_INFO("%s: size of efuse data(%d) is large than expected(%d)!\n", - __FUNCTION__, efuse_size, EEPROM_MAX_SIZE); - efuse_size = EEPROM_MAX_SIZE; - } +#ifdef CONFIG_RTW_MAC_HIDDEN_RPT + if (hal_read_mac_hidden_rpt(adapter) != _SUCCESS) + goto exit; +#endif /* 1. Read registers to check hardware eFuse available or not */ val8 = rtw_read8(adapter, REG_SYS_EEPROM_CTRL_8822B); hal->EepromOrEfuse = (val8 & BIT_EERPOMSEL_8822B) ? _TRUE : _FALSE; hal->bautoload_fail_flag = (val8 & BIT_AUTOLOAD_SUS_8822B) ? _FALSE : _TRUE; - if (hal->bautoload_fail_flag == _TRUE) - goto load_efuse_file; - /* * In 8822B, bautoload_fail_flag is used to present eFuse map is valid * or not, no matter the map comes from hardware or files. */ /* 2. Read eFuse */ - err = rtw_halmac_read_logical_efuse_map(d, efuse_map, efuse_size); - if (err) { - RTW_INFO("%s: fail to get efuse map!\n", __FUNCTION__); - goto load_efuse_file; - } - goto parse_efuse; + EFUSE_ShadowMapUpdate(adapter, EFUSE_WIFI, 0); -load_efuse_file: /* 3. Read Efuse file if necessary */ #ifdef CONFIG_EFUSE_CONFIG_FILE if (check_phy_efuse_tx_power_info_valid(adapter) == _FALSE) { @@ -825,9 +612,6 @@ void rtl8822b_read_efuse(PADAPTER adapter) } #endif /* CONFIG_EFUSE_CONFIG_FILE */ -parse_efuse: - rtw_dump_cur_efuse(adapter); - /* 4. Parse Efuse data */ valid = Hal_EfuseParseIDCode(adapter, efuse_map); if (_TRUE == valid) @@ -847,17 +631,21 @@ void rtl8822b_read_efuse(PADAPTER adapter) Hal_EfuseParseCustomerID(adapter, efuse_map, valid); Hal_DetectWoWMode(adapter); Hal_ReadAmplifierType(adapter, efuse_map, valid); - Hal_ReadRFEType(adapter, efuse_map, valid); + if (Hal_ReadRFEType(adapter, efuse_map, valid) != _SUCCESS) + goto exit; /* Data out of Efuse Map */ Hal_EfuseParsePackageType(adapter, efuse_map, valid); -#ifdef CONFIG_RF_POWER_TRIM - Hal_ReadRFGainOffset(adapter, efuse_map, valid); -#endif /* CONFIG_RF_POWER_TRIM */ + Hal_EfuseParsePABias(adapter); #ifdef CONFIG_USB_HCI Hal_ReadUsbModeSwitch(adapter, efuse_map, valid); #endif /* CONFIG_USB_HCI */ + + ret = _SUCCESS; + +exit: + return ret; } void rtl8822b_run_thread(PADAPTER adapter) @@ -888,53 +676,17 @@ static u8 check_ips_status(PADAPTER adapter) return _FALSE; } -static void update_ra_mask(PADAPTER adapter, u32 mac_id, u8 rssi_level) +static void update_ra_mask_8822b(_adapter *adapter, struct sta_info *psta, struct macid_cfg *h2c_macid_cfg) { - u64 mask, rate_bitmap, *dm_RA_Mask = NULL; - u8 shortGIrate = _FALSE, *dm_RteID = NULL; u8 arg[4] = {0}; - struct sta_info *psta; - PHAL_DATA_TYPE hal; - struct macid_ctl_t *macid_ctl; - - RTW_INFO(FUNC_ADPT_FMT ": mac_id=%d rssi_level=%d\n", - FUNC_ADPT_ARG(adapter), mac_id, rssi_level); - - macid_ctl = &adapter->dvobj->macid_ctl; - psta = NULL; - if (mac_id < macid_ctl->num) - psta = macid_ctl->sta[mac_id]; - if (psta == NULL) { - RTW_PRINT(FUNC_ADPT_FMT " macid:%u, sta is NULL\n", - FUNC_ADPT_ARG(adapter), mac_id); - return; - } - - hal = GET_HAL_DATA(adapter); - shortGIrate = query_ra_short_GI(psta); - mask = psta->ra_mask; - - rate_bitmap = 0xffffffff; - rate_bitmap = PhyDM_Get_Rate_Bitmap_Ex(&hal->odmpriv, mac_id, mask, rssi_level, dm_RA_Mask, dm_RteID); - RTW_INFO("%s => mac_id:%d, networkType:0x%02x, mask:0x%016llx\n\t ==> rssi_level:%d, rate_bitmap:0x%016llx, shortGIrate=%d\n", - __FUNCTION__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap, shortGIrate); - - mask &= rate_bitmap; - -#ifdef CONFIG_BT_COEXIST - if (hal->EEPROMBluetoothCoexist) { - rate_bitmap = rtw_btcoex_GetRaMask(adapter); - mask &= ~rate_bitmap; - } -#endif /* CONFIG_BT_COEXIST */ - - arg[0] = mac_id; - arg[1] = psta->raid; - arg[2] = shortGIrate; + arg[0] = h2c_macid_cfg->mac_id; + arg[1] = h2c_macid_cfg->rate_id; + arg[2] = (h2c_macid_cfg->ignore_bw << 4) | h2c_macid_cfg->short_gi; arg[3] = psta->init_rate; - rtl8822b_set_FwMacIdConfig_cmd(adapter, mask, arg); + rtl8822b_set_FwMacIdConfig_cmd(adapter, h2c_macid_cfg->ra_mask, arg, h2c_macid_cfg->bandwidth); + } static void InitBeaconParameters(PADAPTER adapter) @@ -953,7 +705,14 @@ static void InitBeaconParameters(PADAPTER adapter) #endif rtw_write16(adapter, REG_BCN_CTRL_8822B, val16); - rtw_write16(adapter, REG_TBTT_PROHIBIT_8822B, 0x6404); /* ms */ + /* setup time:128 us */ + rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B, 0x04); + + /*TBTT hold time :4ms 0x540[19:8]*/ + rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 1, + TBTT_PROBIHIT_HOLD_TIME & 0xFF); + rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 2, + (rtw_read8(adapter, REG_TBTT_PROHIBIT_8822B + 2) & 0xF0) | (TBTT_PROBIHIT_HOLD_TIME >> 8)); rtw_write8(adapter, REG_DRVERLYINT_8822B, DRIVER_EARLY_INT_TIME_8822B); /* 5ms */ rtw_write8(adapter, REG_BCNDMATIM_8822B, BCN_DMA_ATIME_INT_TIME_8822B); /* 2ms */ @@ -963,38 +722,6 @@ static void InitBeaconParameters(PADAPTER adapter) * beacause test chip does not contension before sending beacon. */ rtw_write16(adapter, REG_BCNTCFG_8822B, 0x660F); - - hal->RegBcnCtrlVal = rtw_read8(adapter, REG_BCN_CTRL_8822B); - hal->RegTxPause = rtw_read8(adapter, REG_TXPAUSE_8822B); - hal->RegFwHwTxQCtrl = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2); - hal->RegReg542 = rtw_read8(adapter, REG_TBTT_PROHIBIT_8822B + 2); - hal->RegCR_1 = rtw_read8(adapter, REG_CR_8822B + 1); -} - -void rtl8822b_resume_tx_beacon(PADAPTER adapter) -{ - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - - - hal->RegFwHwTxQCtrl |= (BIT_EN_BCNQ_DL_8822B >> 16); - rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2, hal->RegFwHwTxQCtrl); - - rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 1, 0xff); - hal->RegReg542 |= BIT(0); - rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 2, hal->RegReg542); -} - -void rtl8822b_stop_tx_beacon(PADAPTER adapter) -{ - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - - - hal->RegFwHwTxQCtrl &= ~(BIT_EN_BCNQ_DL_8822B >> 16); - rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2, hal->RegFwHwTxQCtrl); - - rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 1, 0x64); - hal->RegReg542 &= ~BIT(0); - rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 2, hal->RegReg542); } static void beacon_function_enable(PADAPTER adapter, u8 Enable, u8 Linked) @@ -1086,28 +813,7 @@ static void set_beacon_related_registers(PADAPTER adapter) beacon_function_enable(adapter, _TRUE, _TRUE); - rtl8822b_resume_tx_beacon(adapter); -} - -/* - * arg[0] = macid - * arg[1] = raid - * arg[2] = shortGIrate - * arg[3] = init_rate - */ -void add_rateatid(PADAPTER adapter, u64 rate_bitmap, u8 *arg, u8 rssi_level) -{ - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - u64 *dm_RA_Mask = NULL; - u8 *dm_RteID = NULL; - u8 macid; - - macid = arg[0]; - - if (rssi_level != DM_RATR_STA_INIT) - rate_bitmap = PhyDM_Get_Rate_Bitmap_Ex(&hal->odmpriv, macid, rate_bitmap, rssi_level, dm_RA_Mask, dm_RteID); - - rtl8822b_set_FwMacIdConfig_cmd(adapter, rate_bitmap, arg); + ResumeTxBeacon(adapter); } static void xmit_status_check(PADAPTER p) @@ -1175,29 +881,6 @@ static void linked_status_check(PADAPTER p) } } -#ifdef CONFIG_TSF_RESET_OFFLOAD -static int reset_tsf(PADAPTER adapter, u8 reset_port) -{ - u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0; - u32 reg_reset_tsf_cnt = (HW_PORT0 == reset_port) ? - REG_FW_RESET_TSF_CNT_0 : REG_FW_RESET_TSF_CNT_1; - - - /* site survey will cause reset_tsf fail */ - rtw_mi_buddy_scan_abort(adapter, _FALSE); - reset_cnt_after = reset_cnt_before = rtw_read8(adapter, reg_reset_tsf_cnt); - rtl8822b_reset_tsf(adapter, reset_port); - - while ((reset_cnt_after == reset_cnt_before) && (loop_cnt < 10)) { - rtw_msleep_os(100); - loop_cnt++; - reset_cnt_after = rtw_read8(adapter, reg_reset_tsf_cnt); - } - - return (loop_cnt >= 10) ? _FAIL : _TRUE; -} -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - static void set_opmode_monitor(PADAPTER adapter) { u32 rcr_bits; @@ -1205,10 +888,6 @@ static void set_opmode_monitor(PADAPTER adapter) struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - /* Leave IPS */ - rtw_pm_set_ips(adapter, IPS_NONE); - LeaveAllPowerSaveMode(adapter); - /* Receive all type */ rcr_bits = BIT_AAP_8822B | BIT_APM_8822B | BIT_AM_8822B | BIT_AB_8822B | BIT_APWRMGT_8822B @@ -1225,6 +904,66 @@ static void set_opmode_monitor(PADAPTER adapter) rtw_write16(adapter, REG_RXFLTMAP_8822B, value_rxfltmap2); } +static void hw_port0_tsf_sync_sel(_adapter *adapter, u8 hw_port, u8 benable, u16 tr_offset) +{ + u8 val8, client_port_num = 0; + + /* check if port0 is already synced */ + if (adapter->tsf.sync_port != MAX_HW_PORT) + return; + + if (benable && hw_port == HW_PORT0) { + RTW_ERR(FUNC_ADPT_FMT ": hw_port is port0 under enable\n", FUNC_ADPT_ARG(adapter)); + rtw_warn_on(1); + return; + } + + /* translate hw_port number to client port numer */ + switch (hw_port) { + case HW_PORT1: + client_port_num = 0; + break; + case HW_PORT2: + client_port_num = 1; + break; + case HW_PORT3: + client_port_num = 2; + break; + case HW_PORT4: + client_port_num = 3; + break; + } + + /* stop port0 bcn funtion */ + hw_bcn_ctrl_clr(adapter, BIT_EN_BCN_FUNCTION); + + + /*Reg 0x518[15:0]: TSFTR_SYN_OFFSET*/ + if (tr_offset) + rtw_write16(adapter, REG_TSFTR_SYN_OFFSET_8822B, tr_offset); + + + /* auto sycn for every TBTT */ + val8 = rtw_read8(adapter, REG_MISC_CTRL_8822B); + val8 |= BIT6; + rtw_write8(adapter, REG_MISC_CTRL_8822B, val8); + + /*0x5B4 [6:4] :SYNC_CLI_SEL - The selector for the CLINT port of sync tsft source for port 0*/ + /* Bit[5:4] : 0 for CLINT 0, 1 for clint1, 2 for clint2, 3 for clint3. + Bit6 : 1= enable sync to port 0. 0=disable sync to port 0.*/ + val8 = rtw_read8(adapter, REG_TIMER0_SRC_SEL_8822B); + if (benable) { + val8 &= 0x8F; + val8 |= (BIT(6) | (client_port_num << 4)); + } else + val8 &= ~BIT(6); + + rtw_write8(adapter, REG_TIMER0_SRC_SEL_8822B, val8); + + /* restart port0 bcn funtion */ + hw_bcn_ctrl_add(adapter, BIT_EN_BCN_FUNCTION); +} + static void set_opmode_port0(PADAPTER adapter, u8 mode) { u8 is_ap_exist; @@ -1252,7 +991,7 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) case _HW_STATE_NOLINK_: case _HW_STATE_STATION_: if (_FALSE == is_ap_exist) { - rtl8822b_stop_tx_beacon(adapter); + StopTxBeacon(adapter); #ifdef CONFIG_PCI_HCI UpdateInterruptMask8822BE(adapter, 0, 0, RT_BCN_INT_MASKS, 0); #endif /* CONFIG_PCI_HCI */ @@ -1272,7 +1011,7 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) break; case _HW_STATE_ADHOC_: - rtl8822b_resume_tx_beacon(adapter); + ResumeTxBeacon(adapter); val8 = BIT_DIS_TSF_UDT_8822B | BIT_EN_BCN_FUNCTION_8822B; rtw_write8(adapter, REG_BCN_CTRL_8822B, val8); @@ -1285,7 +1024,7 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) UpdateInterruptMask8822BE(adapter, RT_BCN_INT_MASKS, 0, 0, 0); #endif /* CONFIG_PCI_HCI */ - rtl8822b_resume_tx_beacon(adapter); + ResumeTxBeacon(adapter); /* * enable BCN0 Function for if1 @@ -1294,8 +1033,10 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) * Reg REG_FWHW_TXQ_CTRL_8822B [2] = 1 * Reg REG_BCN_CTRL_8822B[3][5] = 1 * Enable ATIM + * Enable HW seq for BCN */ /* enable TX BCN report */ + /* disable RX BCN report */ val8 = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822B); val8 |= BIT_EN_BCN_TRXRPT_V1_8822B; rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B, val8); @@ -1303,6 +1044,7 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) /* enable BCN0 Function */ val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B); val8 |= BIT_EN_BCN_FUNCTION_8822B | BIT_DIS_TSF_UDT_8822B | BIT_P0_EN_TXBCN_RPT_8822B; + val8 &= (~BIT_P0_EN_RXBCN_RPT_8822B); rtw_write8(adapter, REG_BCN_CTRL_8822B, val8); /* Enable ATIM */ @@ -1310,10 +1052,20 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) val8 &= ~BIT_DIS_ATIM_ROOT_8822B; rtw_write8(adapter, REG_DIS_ATIM_8822B, val8); + /* Enable HW seq for BCN + 0x4FC[0]: EN_HWSEQ += 0x4FC[1]: EN_HWSEQEXT + According TX desc + */ + rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01); /* Set RCR */ /* CBSSID_DATA must set to 0, reject ICV_ERR packet */ - rtl8822b_rcr_clear(adapter, BIT_CBSSID_DATA_8822B); + if (adapter->registrypriv.wifi_spec) + /* for 11n Logo 4.2.31/4.2.32, disable BSSID BCN check for AP mode */ + rtl8822b_rcr_clear(adapter, BIT_CBSSID_DATA_8822B | BIT_CBSSID_BCN_8822B); + else + rtl8822b_rcr_clear(adapter, BIT_CBSSID_DATA_8822B); /* enable to rx data frame */ rtw_write16(adapter, REG_RXFLTMAP_8822B, 0xFFFF); @@ -1323,9 +1075,19 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) /* Beacon Control related register for first time */ rtw_write8(adapter, REG_BCNDMATIM_8822B, 0x02); /* 2ms */ - rtw_write8(adapter, REG_ATIMWND_8822B, 0x0a); /* 10ms */ + rtw_write8(adapter, REG_ATIMWND_8822B, 0x0c); /* 12ms */ + rtw_write16(adapter, REG_BCNTCFG_8822B, 0x00); - rtw_write16(adapter, REG_TBTT_PROHIBIT_8822B, 0xff04); + + /* setup time:128 us */ + rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B, 0x04); + + /*TBTT hold time :4ms 0x540[19:8]*/ + rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 1, + TBTT_PROBIHIT_HOLD_TIME & 0xFF); + rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 2, + (rtw_read8(adapter, REG_TBTT_PROHIBIT_8822B + 2) & 0xF0) | (TBTT_PROBIHIT_HOLD_TIME >> 8)); + rtw_write16(adapter, REG_TSFTR_SYN_OFFSET_8822B, 0x7fff); /* +32767 (~32ms) */ /* reset TSF */ @@ -1340,22 +1102,27 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) rtw_write8(adapter, REG_CCK_CHECK_8822B, val8); #ifdef CONFIG_CONCURRENT_MODE - if (!rtw_mi_buddy_check_fwstate(adapter, WIFI_FW_ASSOC_SUCCESS)) { - val8 = rtw_read8(adapter, REG_BCN_CTRL_CLINT0_8822B); - val8 &= ~BIT_EN_BCN_FUNCTION_8822B; - rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822B, val8); + { + /* Sync TSF from AP of STA interface to avoid tx bcn fail */ + _adapter *iface; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 i = 0; + u8 connect = _FALSE; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + if (iface == adapter) + continue; + if (check_fwstate(&iface->mlmepriv, (WIFI_STATION_STATE | WIFI_ASOC_STATE))) { + hw_port0_tsf_sync_sel(adapter, iface->hw_port, _TRUE, 50);/*the offset = 50ms.*/ + break; + } + } } #endif /* CONFIG_CONCURRENT_MODE */ -#ifdef CONFIG_TSF_RESET_OFFLOAD - /* Reset TSF for STA+AP concurrent mode */ - if (rtw_mi_buddy_check_fwstate(adapter, (WIFI_STATION_STATE | WIFI_ASOC_STATE))) { - if (reset_tsf(adapter, HW_PORT0) == _FALSE) - RTW_INFO(FUNC_ADPT_FMT ": ERROR! Reset port0 TSF fail\n", - FUNC_ADPT_ARG(adapter)); - } -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - break; } } @@ -1383,7 +1150,7 @@ static void set_opmode_port1(PADAPTER adapter, u8 mode) case _HW_STATE_NOLINK_: case _HW_STATE_STATION_: if (_FALSE == is_ap_exist) { - rtl8822b_stop_tx_beacon(adapter); + StopTxBeacon(adapter); #ifdef CONFIG_PCI_HCI UpdateInterruptMask8822BE(adapter, 0, 0, RT_BCN_INT_MASKS, 0); #endif /* CONFIG_PCI_HCI */ @@ -1398,7 +1165,7 @@ static void set_opmode_port1(PADAPTER adapter, u8 mode) break; case _HW_STATE_ADHOC_: - rtl8822b_resume_tx_beacon(adapter); + ResumeTxBeacon(adapter); val8 = BIT_CLI0_DIS_TSF_UDT_8822B | BIT_CLI0_EN_BCN_FUNCTION_8822B; rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822B, val8); @@ -1478,18 +1245,11 @@ static void hw_var_set_macaddr(PADAPTER adapter, u8 *val) static void hw_var_set_bssid(PADAPTER adapter, u8 *val) { - u8 idx = 0; - u32 reg_bssid; + u8 port; -#ifdef CONFIG_CONCURRENT_MODE - if (adapter->hw_port == HW_PORT1) - reg_bssid = REG_BSSID1_8822B; - else -#endif - reg_bssid = REG_BSSID_8822B; - for (idx = 0; idx < 6; idx++) - rtw_write8(adapter, (reg_bssid + idx), val[idx]); + port = adapter->hw_port; + rtw_halmac_set_bssid(adapter_to_dvobj(adapter), port, val); } static void hw_var_set_basic_rate(PADAPTER adapter, u8 *ratetbl) @@ -1531,7 +1291,7 @@ static void hw_var_set_basic_rate(PADAPTER adapter, u8 *ratetbl) input_b = BrateCfg; /* apply force and allow mask */ - if (hal->CurrentBandType == BAND_ON_2_4G) { + if (hal->current_band_type == BAND_ON_2_4G) { BrateCfg |= rrsr_2g_force_mask; BrateCfg &= rrsr_2g_allow_mask; } else { @@ -1563,15 +1323,7 @@ static void hw_var_set_basic_rate(PADAPTER adapter, u8 *ratetbl) static void hw_var_set_bcn_func(PADAPTER adapter, u8 enable) { - u32 bcn_ctrl_reg; - u8 val8; - -#ifdef CONFIG_CONCURRENT_MODE - if (adapter->hw_port == HW_PORT1) - bcn_ctrl_reg = REG_BCN_CTRL_CLINT0_8822B; - else -#endif - bcn_ctrl_reg = REG_BCN_CTRL_8822B; + u8 val8 = 0; if (enable) { /* enable TX BCN report @@ -1582,31 +1334,69 @@ static void hw_var_set_bcn_func(PADAPTER adapter, u8 enable) val8 |= BIT_EN_BCN_TRXRPT_V1_8822B; rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B, val8); - if (bcn_ctrl_reg == REG_BCN_CTRL_CLINT0_8822B) { - /* setting port 1 */ - val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B); - val8 |= BIT_EN_BCN_FUNCTION_8822B | BIT_P0_EN_TXBCN_RPT_8822B; - rtw_write8(adapter, REG_BCN_CTRL_8822B, val8); + + switch (adapter->hw_port) { + case HW_PORT0: + val8 = BIT_EN_BCN_FUNCTION_8822B | BIT_P0_EN_TXBCN_RPT_8822B; + hw_bcn_ctrl_clr(adapter, BIT_P0_EN_RXBCN_RPT_8822B); + break; +#ifdef CONFIG_CONCURRENT_MODE + case HW_PORT1: + val8 = BIT_CLI0_EN_BCN_FUNCTION_8822B; + hw_bcn_ctrl_clr(adapter, BIT_CLI0_EN_RXBCN_RPT_8822B); + break; + case HW_PORT2: + val8 = BIT_CLI1_EN_BCN_FUNCTION_8822B; + hw_bcn_ctrl_clr(adapter, BIT_CLI1_EN_RXBCN_RPT_8822B); + break; + case HW_PORT3: + val8 = BIT_CLI2_EN_BCN_FUNCTION_8822B; + hw_bcn_ctrl_clr(adapter, BIT_CLI2_EN_RXBCN_RPT_8822B); + break; + case HW_PORT4: + val8 = BIT_CLI3_EN_BCN_FUNCTION_8822B; + hw_bcn_ctrl_clr(adapter, BIT_CLI3_EN_RXBCN_RPT_8822B); + break; +#endif /* CONFIG_CONCURRENT_MODE */ + default: + RTW_ERR(FUNC_ADPT_FMT" Unknow hw port(%d) \n", FUNC_ADPT_ARG(adapter), adapter->hw_port); + rtw_warn_on(1); + break; - val8 = rtw_read8(adapter, REG_BCN_CTRL_CLINT0_8822B); - val8 |= BIT_CLI0_EN_BCN_FUNCTION_8822B; - rtw_write8(adapter, bcn_ctrl_reg, val8); - } else { - /* setting port 0 */ - val8 = BIT_EN_BCN_FUNCTION_8822B | BIT_P0_EN_TXBCN_RPT_8822B; - rtw_write8(adapter, bcn_ctrl_reg, val8); } + hw_bcn_ctrl_add(adapter, val8); } else { - val8 = rtw_read8(adapter, bcn_ctrl_reg); - val8 &= ~(BIT_EN_BCN_FUNCTION_8822B | BIT_P0_EN_TXBCN_RPT_8822B); + + switch (adapter->hw_port) { + case HW_PORT0: + val8 = BIT_EN_BCN_FUNCTION_8822B | BIT_P0_EN_TXBCN_RPT_8822B; #ifdef CONFIG_BT_COEXIST - /* Always enable port0 beacon function for PSTDMA */ - if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist) { - if (REG_BCN_CTRL_8822B == bcn_ctrl_reg) - val8 |= BIT_EN_BCN_FUNCTION_8822B; - } + /* Always enable port0 beacon function for PSTDMA */ + if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist) + val8 = BIT_P0_EN_TXBCN_RPT_8822B; #endif /* CONFIG_BT_COEXIST */ - rtw_write8(adapter, bcn_ctrl_reg, val8); + break; +#ifdef CONFIG_CONCURRENT_MODE + case HW_PORT1: + val8 = BIT_CLI0_EN_BCN_FUNCTION_8822B; + break; + case HW_PORT2: + val8 = BIT_CLI1_EN_BCN_FUNCTION_8822B; + break; + case HW_PORT3: + val8 = BIT_CLI2_EN_BCN_FUNCTION_8822B; + break; + case HW_PORT4: + val8 = BIT_CLI3_EN_BCN_FUNCTION_8822B; + break; +#endif /* CONFIG_CONCURRENT_MODE */ + default: + RTW_ERR(FUNC_ADPT_FMT" Unknow hw port(%d) \n", FUNC_ADPT_ARG(adapter), adapter->hw_port); + rtw_warn_on(1); + break; + } + + hw_bcn_ctrl_clr(adapter, val8); } } @@ -1627,7 +1417,7 @@ static void hw_var_set_correct_tsf(PADAPTER adapter) if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) - rtl8822b_stop_tx_beacon(adapter); + StopTxBeacon(adapter); rtw_hal_correct_tsf(adapter, adapter->hw_port, tsf); @@ -1647,21 +1437,18 @@ static void hw_var_set_correct_tsf(PADAPTER adapter) continue; if ((check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE) - && (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE)) { - rtw_hal_correct_tsf(iface, iface->hw_port, tsf); -#ifdef CONFIG_TSF_RESET_OFFLOAD - if (reset_tsf(iface, iface->hw_port) == _FALSE) - RTW_INFO(FUNC_ADPT_FMT": [ERROR] Reset port%d TSF fail!\n", - FUNC_ADPT_ARG(iface), iface->hw_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - } + && (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE)) + hw_port0_tsf_sync_sel(iface, adapter->hw_port, _TRUE, 50);/* the offset = 50ms.*/ } - } -#endif /* CONFIG_CONCURRENT_MODE */ + } else if (((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) + && (adapter->hw_port == HW_PORT0)) + #endif /*CONFIG_CONCURRENT_MODE*/ + /* disable func of port0 TSF sync from another port*/ + hw_port0_tsf_sync_sel(adapter, adapter->hw_port, _FALSE, 0); if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) - rtl8822b_resume_tx_beacon(adapter); + ResumeTxBeacon(adapter); #endif /* !CONFIG_MI_WITH_MBSSID_CAM */ } @@ -1682,7 +1469,7 @@ static void hw_var_set_check_bssid(PADAPTER adapter, u8 enable) static void hw_var_set_mlme_disconnect(PADAPTER adapter) { u8 val8; - u8 ld_sta_num = 0, lg_sta_num = 0; + struct mi_state mstate; #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE) @@ -1716,10 +1503,10 @@ static void hw_var_set_mlme_disconnect(PADAPTER adapter) rtw_write8(adapter, REG_BCN_CTRL_8822B, val8); } - rtw_mi_status_no_self(adapter, NULL, &ld_sta_num, &lg_sta_num, NULL, NULL, NULL); + rtw_mi_status_no_self(adapter, &mstate); /* clear update TSF only BSSID match for no linked station */ - if (ld_sta_num == 0 && lg_sta_num == 0) + if (MSTATE_STA_LD_NUM(&mstate) == 0 && MSTATE_STA_LG_NUM(&mstate) == 0) rtl8822b_rx_tsf_addr_filter_config(adapter, 0); } @@ -1772,7 +1559,7 @@ static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable) hal->RegRRSR = rtw_read16(adapter, REG_RRSR_8822B); if (rtw_mi_check_status(adapter, MI_AP_MODE)) - rtl8822b_stop_tx_beacon(adapter); + StopTxBeacon(adapter); } else { /* sitesurvey done * 1. enable rx data frame @@ -1786,6 +1573,11 @@ static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable) #ifdef CONFIG_MI_WITH_MBSSID_CAM rtl8822b_rcr_clear(adapter, BIT_CBSSID_BCN_8822B | BIT_CBSSID_DATA_8822B); #else /* CONFIG_MI_WITH_MBSSID_CAM */ + + /* for 11n Logo 4.2.31/4.2.32, disable BSSID BCN check for AP mode */ + if (adapter->registrypriv.wifi_spec && MLME_IS_AP(adapter)) + rcr_bit &= ~(BIT_CBSSID_BCN_8822B); + rtl8822b_rcr_add(adapter, rcr_bit); #endif /* CONFIG_MI_WITH_MBSSID_CAM */ @@ -1817,7 +1609,7 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) if (type == 0) { /* prepare to join */ if (rtw_mi_check_status(adapter, MI_AP_MODE)) - rtl8822b_stop_tx_beacon(adapter); + StopTxBeacon(adapter); /* enable to rx data frame.Accept all data frame */ rtw_write16(adapter, REG_RXFLTMAP_8822B, 0xFFFF); @@ -1851,7 +1643,7 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) rtw_write16(adapter, REG_RXFLTMAP_8822B, 0x00); if (rtw_mi_check_status(adapter, MI_AP_MODE)) { - rtl8822b_resume_tx_beacon(adapter); + ResumeTxBeacon(adapter); /* reset TSF 1/2 after resume_tx_beacon */ val8 = BIT_TSFTR_RST_8822B | BIT_TSFTR_CLI0_RST_8822B; @@ -1880,7 +1672,7 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) } if (rtw_mi_check_status(adapter, MI_AP_MODE)) { - rtl8822b_resume_tx_beacon(adapter); + ResumeTxBeacon(adapter); /* reset TSF 1/2 after resume_tx_beacon */ rtw_write8(adapter, REG_DUAL_TSF_RST_8822B, BIT_TSFTR_RST_8822B | BIT_TSFTR_CLI0_RST_8822B); @@ -1893,13 +1685,13 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) if (type == 0) { /* prepare to join */ - /* enable to rx data frame.Accept all data frame */ + /* enable to rx data frame. Accept all data frame */ rtw_write16(adapter, REG_RXFLTMAP_8822B, 0xFFFF); hw_var_set_check_bssid(adapter, !adapter->in_cta_test); /* - * for 8822B, must enable BCN function if BIT_CBSSID_BCN_8822B(bit 7) of REG_RCR(0x608) is enable to recv BSSID bcn + * for 8822B, must enable BCN function if BIT_CBSSID_BCN_8822B(bit 7) of REG_RCR(0x608) is enabled to recv BSSID bcn */ hw_var_set_bcn_func(adapter, _TRUE); @@ -1979,48 +1771,20 @@ static void hw_var_set_bcn_interval(PADAPTER adapter, u16 bcn_interval) if (adapter->hw_port == HW_PORT1) { /* Port 1(clint 0) */ val16 = rtw_read16(adapter, (REG_MBSSID_BCN_SPACE_8822B + 2)); + val16 &= (~BIT_MASK_BCN_SPACE_CLINT0_8822B); val16 |= (bcn_interval & BIT_MASK_BCN_SPACE_CLINT0_8822B); rtw_write16(adapter, REG_MBSSID_BCN_SPACE_8822B + 2, val16); } else #endif { /* Port 0 */ - val16 = rtw_read16(adapter, (REG_MBSSID_BCN_SPACE_8822B)); - val16 |= (bcn_interval & BIT_MASK_BCN_SPACE0_8822B); - rtw_write16(adapter, REG_MBSSID_BCN_SPACE_8822B, val16); + rtw_write16(adapter, REG_MBSSID_BCN_SPACE_8822B, bcn_interval); } RTW_INFO("%s: [HW_VAR_BEACON_INTERVAL] 0x%x=0x%x\n", __FUNCTION__, REG_MBSSID_BCN_SPACE_8822B, rtw_read32(adapter, REG_MBSSID_BCN_SPACE_8822B)); } -static void hw_var_set_sec_cfg(PADAPTER adapter, u8 cfg) -{ -#if defined(CONFIG_CONCURRENT_MODE) && !defined(DYNAMIC_CAMID_ALLOC) - /* enable tx enc and rx dec engine, and no key search for MC/BC */ - rtw_write8(adapter, REG_SECCFG_8822B, BIT_NOSKMC_8822B | BIT_RXDEC_8822B | BIT_TXENC_8822B); -#elif defined(DYNAMIC_CAMID_ALLOC) - u16 reg_scr_ori; - u16 reg_scr; - - reg_scr = reg_scr_ori = rtw_read16(adapter, REG_SECCFG_8822B); - reg_scr |= (BIT_CHK_KEYID_8822B | BIT_RXDEC_8822B | BIT_TXENC_8822B); - - if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC)) - reg_scr |= BIT_CHK_BMC_8822B; - - if (_rtw_camctl_chk_flags(adapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH)) - reg_scr |= BIT_NOSKMC_8822B; - - if (reg_scr != reg_scr_ori) - rtw_write16(adapter, REG_SECCFG_8822B, reg_scr); -#else - rtw_write8(adapter, REG_SECCFG_8822B, cfg); -#endif - RTW_INFO("%s: [HW_VAR_SEC_CFG] 0x%x=0x%x\n", __FUNCTION__, - REG_SECCFG_8822B, rtw_read32(adapter, REG_SECCFG_8822B)); -} - static void hw_var_set_sec_dk_cfg(PADAPTER adapter, u8 enable) { struct security_priv *sec = &adapter->securitypriv; @@ -2101,6 +1865,7 @@ void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus) u8 DLBcnCount = 0; u32 poll = 0; u8 val8; + u8 restore[2]; RTW_INFO(FUNC_ADPT_FMT ":+ hw_port=%d mstatus(%x)\n", @@ -2112,11 +1877,12 @@ void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus) #endif u8 v8; - /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */ - rtw_write16(adapter, REG_BCN_PSR_RPT_8822B, (0xC000 | pmlmeinfo->aid)); + /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 8822B. */ + rtw_write16(adapter, port_cfg[get_hw_port(adapter)].ps_aid, (0xF800 | pmlmeinfo->aid)); /* Enable SW TX beacon */ v8 = rtw_read8(adapter, REG_CR_8822B + 1); + restore[0] = v8; v8 |= (BIT_ENSWBCN_8822B >> 8); rtw_write8(adapter, REG_CR_8822B + 1, v8); @@ -2125,19 +1891,21 @@ void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus) * Fix download reserved page packet fail that access collision with the protection time. */ val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B); + restore[1] = val8; val8 &= ~BIT_EN_BCN_FUNCTION_8822B; val8 |= BIT_DIS_TSF_UDT_8822B; rtw_write8(adapter, REG_BCN_CTRL_8822B, val8); #if 0 /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */ - if (hal->RegFwHwTxQCtrl & BIT(6)) + RegFwHwTxQCtrl = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2); + + if (RegFwHwTxQCtrl & BIT(6)) bRecover = _TRUE; /* To tell Hw the packet is not a real beacon frame. */ - val8 = hal->RegFwHwTxQCtrl & ~BIT(6); - rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2, val8); - hal->RegFwHwTxQCtrl &= ~BIT(6); + RegFwHwTxQCtrl &= ~BIT(6); + rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2, RegFwHwTxQCtrl); #endif /* Clear beacon valid check bit. */ @@ -2173,10 +1941,8 @@ void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus) ADPT_ARG(adapter), DLBcnCount, poll); } - val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B); - val8 |= BIT_EN_BCN_FUNCTION_8822B; - val8 &= ~BIT_DIS_TSF_UDT_8822B; - rtw_write8(adapter, REG_BCN_CTRL_8822B, val8); + rtw_write8(adapter, REG_BCN_CTRL, restore[1]); + rtw_write8(adapter, REG_CR + 1, restore[0]); #if 0 /* * To make sure that if there exists an adapter which would like to send beacon. @@ -2185,8 +1951,8 @@ void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus) * the beacon cannot be sent by HW. */ if (bRecover) { - rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2, hal->RegFwHwTxQCtrl | BIT(6)); - hal->RegFwHwTxQCtrl |= BIT(6); + RegFwHwTxQCtrl |= BIT(6); + rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2, RegFwHwTxQCtrl); } #endif #ifndef CONFIG_PCI_HCI @@ -2232,6 +1998,114 @@ static u8 rx_agg_switch(PADAPTER adapter, u8 enable) return _SUCCESS; } + +#ifdef CONFIG_AP_PORT_SWAP +/* + * Parameters: + * if_ap ap interface + * if_port0 port0 interface + */ + +static void hw_port_reconfig(_adapter * if_ap, _adapter *if_port0) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(if_port0); + struct mlme_ext_priv *pmlmeext = &if_port0->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u32 bssid_offset = 0; + u8 bssid[6] = {0}; + u8 vnet_type = 0; + u8 vbcn_ctrl = 0; + u8 i; + u8 port = if_ap->hw_port; + + if (port > (hal_spec->port_num - 1)) { + RTW_INFO("[WARN] "ADPT_FMT"- hw_port : %d,will switch to invalid port-%d\n", + ADPT_ARG(if_port0), if_port0->hw_port, port); + rtw_warn_on(1); + } + + RTW_PRINT(ADPT_FMT" - hw_port : %d,will switch to port-%d\n", + ADPT_ARG(if_port0), if_port0->hw_port, port); + + /*backup*/ + GetHwReg(if_port0, HW_VAR_MEDIA_STATUS, &vnet_type); + vbcn_ctrl = rtw_read8(if_port0, port_cfg[if_port0->hw_port].bcn_ctl); + + if (is_client_associated_to_ap(if_port0)) { + RTW_INFO("port0-iface("ADPT_FMT") is STA mode and linked\n", ADPT_ARG(if_port0)); + bssid_offset = port_cfg[if_port0->hw_port].bssid; + for (i = 0; i < 6; i++) + bssid[i] = rtw_read8(if_port0, bssid_offset + i); + } + + /*reconfigure*/ + if_port0->hw_port = port; + /* adapter mac addr switch to port mac addr */ + hw_var_set_macaddr(if_port0, adapter_mac_addr(if_port0)); + Set_MSR(if_port0, vnet_type); + rtw_write8(if_port0, port_cfg[if_port0->hw_port].bcn_ctl, vbcn_ctrl); + + if (is_client_associated_to_ap(if_port0)) + hw_var_set_bssid(if_port0, bssid); + + if_ap->hw_port =HW_PORT0; + /* port mac addr switch to adapter mac addr */ + hw_var_set_macaddr(if_ap, adapter_mac_addr(if_ap)); + +} + +static void hw_var_ap_port_switch(_adapter *adapter, u8 mode) +{ + u8 hw_port = get_hw_port(adapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 ap_nums = 0; + _adapter *if_port0 = NULL; + int i; + + RTW_INFO(ADPT_FMT ": hw_port(%d) will set mode to %d\n", ADPT_ARG(adapter), hw_port, mode); +#if 0 + #ifdef CONFIG_P2P + if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) { + RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, + rtw_p2p_role(&adapter->wdinfo), rtw_p2p_state(&adapter->wdinfo), rtw_p2p_pre_state(&adapter->wdinfo)); + } + #endif +#endif + + if (mode != _HW_STATE_AP_) + return; + + if (hw_port == HW_PORT0) + return; + + /*check and prepare switch port to port0 for AP mode's BCN function*/ + ap_nums = rtw_mi_get_ap_num(adapter); + if (ap_nums > 0) { + RTW_ERR("SortAP mode numbers:%d, must move setting to MBSSID CAM, not support yet\n", ap_nums); + rtw_warn_on(1); + return; + } + + /*Get iface of port-0*/ + for (i = 0; i < dvobj->iface_nums; i++) { + if (get_hw_port(dvobj->padapters[i]) == HW_PORT0) { + if_port0 = dvobj->padapters[i]; + break; + } + } + + if (if_port0 == NULL) { + RTW_ERR("%s if_port0 == NULL\n", __func__); + rtw_warn_on(1); + return; + } + /* if_port0 switch to hw_port */ + hw_port_reconfig(adapter, if_port0); + RTW_INFO(ADPT_FMT ": Cfg SoftAP mode to hw_port(%d) done\n", ADPT_ARG(adapter), adapter->hw_port); + +} +#endif + void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); @@ -2289,7 +2163,11 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) #ifdef CONFIG_BT_COEXIST if (hal->EEPROMBluetoothCoexist) rtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE); -#endif + else + rtw_btcoex_wifionly_scan_notify(adapter); +#else /* !CONFIG_BT_COEXIST */ + rtw_btcoex_wifionly_scan_notify(adapter); +#endif /* CONFIG_BT_COEXIST */ break; case HW_VAR_MLME_JOIN: @@ -2341,9 +2219,11 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) hw_var_set_ack_preamble(adapter, *val); break; +/* case HW_VAR_SEC_CFG: - hw_var_set_sec_cfg(adapter, *val); + follow hal_com.c break; +*/ case HW_VAR_SEC_DK_CFG: if (val) @@ -2377,7 +2257,7 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) break; case HW_VAR_AC_PARAM_BE: - hal->AcParam_BE = *(u32 *)val; + hal->ac_param_be = *(u32 *)val; rtw_write32(adapter, REG_EDCA_BE_PARAM_8822B, *(u32 *)val); break; @@ -2431,11 +2311,11 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_FWLPS_RF_ON: break; */ -#ifdef CONFIG_P2P +#ifdef CONFIG_P2P_PS case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: - rtl8822b_set_p2p_ps_offload_cmd(adapter, *val); + rtw_set_p2p_ps_offload_cmd(adapter, *val); break; -#endif +#endif /* CONFIG_P2P_PS */ /* case HW_VAR_TRIGGER_GPIO_0: case HW_VAR_BT_SET_COEXIST: @@ -2576,10 +2456,7 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_PCIE_STOP_TX_DMA: break; */ - case HW_VAR_APFM_ON_MAC: - hal->bMacPwrCtrlOn = *val; - RTW_INFO("[HW_VAR_APFM_ON_MAC] bMacPwrCtrlOn=%d\n", hal->bMacPwrCtrlOn); - break; + /* case HW_VAR_HCI_SUS_STATE: #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) @@ -2592,29 +2469,21 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) #ifdef CONFIG_GPIO_WAKEUP case HW_SET_GPIO_WL_CTRL: { u8 enable = *val; - u8 shift = 2; - u32 addr; - u8 bit_en; + u8 value = 0; + u8 addr = REG_PAD_CTRL1_8822B + 3; - addr = REG_LED_CFG_8822B + shift; - bit_en = BIT_GPIO13_14_WL_CTRL_EN_8822B >> (shift * 8); + if (WAKEUP_GPIO_IDX == 6) { + value = rtw_read8(adapter, addr); - val8 = rtw_read8(adapter, addr); - - if (enable == _TRUE) { - if (val8 & bit_en) { - val8 &= ~bit_en; - rtw_write8(adapter, addr, val8); - } - } else { - if (!(val8 & bit_en)) { - val8 |= bit_en; - rtw_write8(adapter, addr, val8); - } + if (enable == _TRUE && (value & BIT(1))) + /* set 0x64[25] = 0 to control GPIO 6 */ + rtw_write8(adapter, addr, value & (~BIT(1))); + else if (enable == _FALSE) + rtw_write8(adapter, addr, value | BIT(1)); + RTW_INFO("[HW_SET_GPIO_WL_CTRL] 0x%02X=0x%02X\n", + addr, rtw_read8(adapter, addr)); } - RTW_INFO("[HW_SET_GPIO_WL_CTRL] 0x%02X=0x%02X\n", - addr, rtw_read8(adapter, addr)); } break; #endif @@ -2638,7 +2507,6 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) break; /* - case HW_VAR_C2H_HANDLE: case HW_VAR_RPT_TIMER_SETTING: case HW_VAR_TX_RPT_MAX_MACID: case HW_VAR_CHK_HI_QUEUE_EMPTY: @@ -2660,9 +2528,16 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_AMPDU_MAX_TIME: case HW_VAR_WIRELESS_MODE: case HW_VAR_USB_MODE: +*/ +#ifdef CONFIG_AP_PORT_SWAP case HW_VAR_PORT_SWITCH: + { + u8 mode = *((u8 *)val); + + hw_var_ap_port_switch(adapter, mode); + } break; -*/ +#endif case HW_VAR_DO_IQK: if (*val) hal->bNeedIQK = _TRUE; @@ -2680,21 +2555,30 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) */ #ifdef CONFIG_BEAMFORMING case HW_VAR_SOUNDING_ENTER: - rtl8822b_phy_sounding_enter(adapter, (struct sta_info*)val); + rtl8822b_phy_bf_enter(adapter, (struct sta_info*)val); break; case HW_VAR_SOUNDING_LEAVE: - rtl8822b_phy_sounding_leave(adapter, val); + rtl8822b_phy_bf_leave(adapter, val); break; /* case HW_VAR_SOUNDING_RATE: + break; +*/ case HW_VAR_SOUNDING_STATUS: + rtl8822b_phy_bf_sounding_status(adapter, *val); + break; +/* case HW_VAR_SOUNDING_FW_NDPA: case HW_VAR_SOUNDING_CLK: break; */ case HW_VAR_SOUNDING_SET_GID_TABLE: - rtl8822b_phy_sounding_set_gid_table(adapter, (struct beamformer_entry*)val); + rtl8822b_phy_bf_set_gid_table(adapter, (struct beamformer_entry*)val); + break; + + case HW_VAR_SOUNDING_CSI_REPORT: + rtl8822b_phy_bf_set_csi_report(adapter, (struct _RT_CSI_INFO*)val); break; #endif /* CONFIG_BEAMFORMING */ /* @@ -2991,9 +2875,7 @@ void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_PCIE_STOP_TX_DMA: break; */ - case HW_VAR_APFM_ON_MAC: - *val = hal->bMacPwrCtrlOn; - break; + /* case HW_VAR_HCI_SUS_STATE: break; @@ -3002,11 +2884,11 @@ void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) /* case HW_VAR_WOWLAN: break; -*/ + case HW_VAR_WAKEUP_REASON: rtw_halmac_get_wow_reason(adapter_to_dvobj(adapter), val); break; -/* + case HW_VAR_RPWM_TOG: break; */ @@ -3022,7 +2904,6 @@ void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) break; /* case HW_VAR_NAV_UPPER: - case HW_VAR_C2H_HANDLE: case HW_VAR_RPT_TIMER_SETTING: case HW_VAR_TX_RPT_MAX_MACID: break; @@ -3087,23 +2968,6 @@ void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) } } -void rtl8822b_sethwregwithbuf(PADAPTER adapter, u8 variable, u8 *pbuf, int len) -{ - PHAL_DATA_TYPE hal; - - - hal = GET_HAL_DATA(adapter); - - switch (variable) { - case HW_VAR_C2H_HANDLE: - rtl8822b_c2h_handler(adapter, pbuf, len); - break; - - default: - break; - } -} - /* * Description: * Change default setting of specified variable. @@ -3196,7 +3060,7 @@ u8 rtl8822b_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval break; case HAL_DEF_MAX_RECVBUF_SZ: - *((u32 *)pval) = HALMAC_RX_FIFO_SIZE_8822B; + *((u32 *)pval) = MAX_RECVBUF_SZ; break; case HAL_DEF_RX_PACKET_OFFSET: @@ -3354,36 +3218,6 @@ u8 rtl8822b_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval return bResult; } -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -/* - * Description: Prepare some information to Fw for WoWLAN. - * (1) Download wowlan Fw. - * (2) Download RSVD page packets. - * (3) Enable AP offload if needed. - */ -static void SetFwRelatedForWoWLAN(PADAPTER adapter, u8 bHostIsGoingtoSleep) -{ - u8 status = _FAIL; - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - u8 bRecover = _FALSE; - - /* - * 1. Before WoWLAN we need to re-download WoWLAN Fw. - */ - status = rtl8723b_FirmwareDownload(adapter, bHostIsGoingtoSleep); - if (status != _SUCCESS) { - RTW_INFO("%s: Re-Download Firmware failed!!\n", __FUNCTION__); - return; - } - RTW_INFO("%s: Re-Download Firmware Success !!\n", , __FUNCTION__); - - /* - * 2. Re-Init the variables about Fw related setting. - */ - rtl8723b_InitializeFirmwareVars(adapter); -} -#endif /* CONFIG_WOWLAN || CONFIG_AP_WOWLAN */ - void rtl8822b_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc) { if ((pattrib->encrypt > 0) && !pattrib->bswenc) { @@ -3452,14 +3286,14 @@ u8 rtl8822b_bw_mapping(PADAPTER adapter, struct pkt_attrib *pattrib) PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - if (hal->CurrentChannelBW == CHANNEL_WIDTH_80) { + if (hal->current_channel_bw == CHANNEL_WIDTH_80) { if (pattrib->bwmode == CHANNEL_WIDTH_80) BWSettingOfDesc = 2; else if (pattrib->bwmode == CHANNEL_WIDTH_40) BWSettingOfDesc = 1; else BWSettingOfDesc = 0; - } else if (hal->CurrentChannelBW == CHANNEL_WIDTH_40) { + } else if (hal->current_channel_bw == CHANNEL_WIDTH_40) { if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80)) BWSettingOfDesc = 1; else @@ -3476,7 +3310,7 @@ u8 rtl8822b_sc_mapping(PADAPTER adapter, struct pkt_attrib *pattrib) PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - if (hal->CurrentChannelBW == CHANNEL_WIDTH_80) { + if (hal->current_channel_bw == CHANNEL_WIDTH_80) { if (pattrib->bwmode == CHANNEL_WIDTH_80) SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; else if (pattrib->bwmode == CHANNEL_WIDTH_40) { @@ -3498,7 +3332,7 @@ u8 rtl8822b_sc_mapping(PADAPTER adapter, struct pkt_attrib *pattrib) else RTW_INFO("SCMapping: DONOT CARE Mode Setting\n"); } - } else if (hal->CurrentChannelBW == CHANNEL_WIDTH_40) { + } else if (hal->current_channel_bw == CHANNEL_WIDTH_40) { if (pattrib->bwmode == CHANNEL_WIDTH_40) SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; else if (pattrib->bwmode == CHANNEL_WIDTH_20) { @@ -3535,6 +3369,97 @@ void rtl8822b_fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdes } #endif +/* + * Description: + * Fill tx description for beamforming packets + */ +void rtl8822b_fill_txdesc_bf(struct xmit_frame *frame, u8 *desc) +{ +#ifndef CONFIG_BEAMFORMING + return; +#else /* CONFIG_BEAMFORMING */ + struct pkt_attrib *attrib; + + + attrib = &frame->attrib; + + SET_TX_DESC_G_ID_8822B(desc, attrib->txbf_g_id); + SET_TX_DESC_P_AID_8822B(desc, attrib->txbf_p_aid); + + SET_TX_DESC_MU_DATARATE_8822B(desc, MRateToHwRate(attrib->rate)); + /*SET_TX_DESC_MU_RC_8822B(desc, 0);*/ + + /* Force to disable STBC when txbf is enabled */ + if (attrib->txbf_p_aid && attrib->stbc) + SET_TX_DESC_DATA_STBC_8822B(desc, 0); +#endif /* CONFIG_BEAMFORMING */ +} + +/* + * Description: + * Fill tx description for beamformer, + * include following management packets: + * 1. VHT NDPA + * 2. HT NDPA + * 3. Beamforming Report Poll + */ +void rtl8822b_fill_txdesc_mgnt_bf(struct xmit_frame *frame, u8 *desc) +{ +#ifndef CONFIG_BEAMFORMING + return; +#else /* CONFIG_BEAMFORMING */ + PADAPTER adapter; + struct pkt_attrib *attrib; + u8 ndpa = 0; + u8 ht_ndpa = 0; + u8 report_poll = 0; + + + adapter = frame->padapter; + attrib = &frame->attrib; + + if (attrib->subtype == WIFI_NDPA) + ndpa = 1; + if ((attrib->subtype == WIFI_ACTION_NOACK) && (attrib->order == 1)) + ht_ndpa = 1; + if (attrib->subtype == WIFI_BF_REPORT_POLL) + report_poll = 1; + + if ((!ndpa) && (!ht_ndpa) && (!report_poll)) + return; + + /*SET_TX_DESC_TXPKTSIZE_8822B(desc, pattrib->last_txcmdsz);*/ + /*SET_TX_DESC_OFFSET_8822B(desc, HALMAC_TX_DESC_SIZE_8822B);*/ + SET_TX_DESC_DISRTSFB_8822B(desc, 1); + SET_TX_DESC_DISDATAFB(desc, 1); + /*SET_TX_DESC_SW_SEQ_8822B(desc, pattrib->seqnum);*/ + SET_TX_DESC_DATA_BW_8822B(desc, rtl8822b_bw_mapping(adapter, attrib)); + SET_TX_DESC_RTS_SC_8822B(desc, rtl8822b_sc_mapping(adapter, attrib)); + /*SET_TX_DESC_RTY_LMT_EN_8822B(ptxdesc, 1);*/ + SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(desc, 5); + SET_TX_DESC_NDPA_8822B(desc, 1); + SET_TX_DESC_NAVUSEHDR_8822B(desc, 1); + /*SET_TX_DESC_QSEL_8822B(desc, QSLT_MGNT);*/ + /* + * NSS2MCS0 for VHT + * MCS8 for HT + */ + SET_TX_DESC_DATARATE_8822B(desc, MRateToHwRate(attrib->rate)); + /*SET_TX_DESC_USE_RATE_8822B(desc, 1);*/ + /*SET_TX_DESC_MACID_8822B(desc, pattrib->mac_id);*/ /* ad-hoc mode */ + /*SET_TX_DESC_G_ID_8822B(desc, 63);*/ + /* + * partial AID of 1st STA, at infrastructure mode, either SU or MU; + * MACID, at ad-hoc mode + * + * For WMAC to restore the received CSI report of STA1. + * WMAC would set p_aid field to 0 in PLCP header for MU. + */ + /*SET_TX_DESC_P_AID_8822B(desc, pattrib->txbf_p_aid);*/ + SET_TX_DESC_SND_PKT_SEL_8822B(desc, attrib->bf_pkt_type); +#endif /* CONFIG_BEAMFORMING */ +} + void rtl8822b_cal_txdesc_chksum(PADAPTER adapter, u8 *ptxdesc) { PHALMAC_ADAPTER halmac; @@ -3743,16 +3668,9 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) SET_TX_DESC_MBSSID_8822B(pbuf, pattrib->mbssid & 0xF); -#ifdef CONFIG_INTEL_PROXIM - if ((adapter->proximity.proxim_on == _TRUE) - && (pattrib->intel_proxim == _TRUE)) { - RTW_INFO("%s: pattrib->rate=%d\n", __FUNCTION__, pattrib->rate); - SET_TX_DESC_DATARATE_8822B(pbuf, pattrib->rate); - } else -#endif - { - SET_TX_DESC_DATARATE_8822B(pbuf, MRateToHwRate(pmlmeext->tx_rate)); - } + SET_TX_DESC_DATARATE_8822B(pbuf, MRateToHwRate(pattrib->rate)); + + rtl8822b_fill_txdesc_mgnt_bf(pxmitframe, pbuf); #ifdef CONFIG_XMIT_ACK /* CCX-TXRPT ack for xmit mgmt frames. */ @@ -3822,10 +3740,10 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) if (!pattrib->qos_en) SET_TX_DESC_EN_HWSEQ_8822B(pbuf, 1); -#ifdef CONFIG_BEAMFORMING - SET_TX_DESC_G_ID_8822B(pbuf, pattrib->txbf_g_id); - SET_TX_DESC_P_AID_8822B(pbuf, pattrib->txbf_p_aid); -#endif /* CONFIG_BEAMFORMING */ + SET_TX_DESC_PORT_ID_8822B(pbuf, get_hw_port(adapter)); + SET_TX_DESC_MULTIPLE_PORT_8822B(pbuf, get_hw_port(adapter)); + + rtl8822b_fill_txdesc_bf(pxmitframe, pbuf); } /* @@ -3840,7 +3758,7 @@ void rtl8822b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) fill_default_txdesc(pxmitframe, pbuf); #ifdef CONFIG_ANTENNA_DIVERSITY - ODM_SetTxAntByTxInfo(&GET_HAL_DATA(pxmitframe->adapter)->odmpriv, pbuf, pxmitframe->attrib.mac_id); + odm_set_tx_ant_by_tx_info(&GET_HAL_DATA(pxmitframe->padapter)->odmpriv, pbuf, pxmitframe->attrib.mac_id); #endif /* CONFIG_ANTENNA_DIVERSITY */ rtl8822b_cal_txdesc_chksum(pxmitframe->padapter, pbuf); @@ -3857,6 +3775,8 @@ static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame) { /* Clear all status */ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + _rtw_memset(pDesc, 0, HALMAC_TX_DESC_SIZE_8822B); SET_TX_DESC_LS_8822B(pDesc, 1); @@ -3866,19 +3786,26 @@ static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen, SET_TX_DESC_TXPKTSIZE_8822B(pDesc, BufferLen); SET_TX_DESC_QSEL_8822B(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */ + if (pmlmeext->cur_wireless_mode & WIRELESS_11B) + SET_TX_DESC_RATE_ID_8822B(pDesc, RATEID_IDX_B); + else + SET_TX_DESC_RATE_ID_8822B(pDesc, RATEID_IDX_G); + /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by HW */ if (_TRUE == IsPsPoll) SET_TX_DESC_NAVUSEHDR_8822B(pDesc, 1); else { + SET_TX_DESC_DISQSELSEQ_8822B(pDesc, 1); SET_TX_DESC_EN_HWSEQ_8822B(pDesc, 1); - SET_TX_DESC_HW_SSN_SEL_8822B(pDesc, 0); + SET_TX_DESC_HW_SSN_SEL_8822B(pDesc, 0);/*pattrib->hw_ssn_sel*/ + SET_TX_DESC_EN_HWEXSEQ_8822B(pDesc, 0); } if (_TRUE == IsBTQosNull) SET_TX_DESC_BT_NULL_8822B(pDesc, 1); SET_TX_DESC_USE_RATE_8822B(pDesc, 1); - SET_TX_DESC_DATARATE_8822B(pDesc, DESC_RATE1M); + SET_TX_DESC_DATARATE_8822B(pDesc, MRateToHwRate(pmlmeext->tx_rate)); /* * Encrypt the data frame if under security mode excepct null data. @@ -3908,6 +3835,8 @@ static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen, } } + SET_TX_DESC_PORT_ID_8822B(pDesc, get_hw_port(adapter)); + SET_TX_DESC_MULTIPLE_PORT_8822B(pDesc, get_hw_port(adapter)); #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) /* * USB interface drop packet if the checksum of descriptor isn't correct. @@ -3991,11 +3920,22 @@ void rtl8822b_query_rx_desc(union recv_frame *precvframe, u8 *pdesc) void rtl8822b_set_hal_ops(PADAPTER adapter) { + struct hal_com_data *hal; struct hal_ops *ops; - ops = &adapter->HalFunc; + hal = GET_HAL_DATA(adapter); + ops = &adapter->hal_func; + + /* + * Initialize hal_com_data variables + */ + hal->efuse0x3d7 = 0xFF; + hal->efuse0x3d8 = 0xFF; + /* + * Initialize operation callback functions + */ /*** initialize section ***/ ops->read_chip_version = read_chip_version; /* @@ -4056,8 +3996,6 @@ void rtl8822b_set_hal_ops(PADAPTER adapter) ops->InitSwLeds = NULL; ops->DeInitSwLeds = NULL; */ - ops->set_bwmode_handler = rtl8822b_set_bw_mode; - ops->set_channel_handler = rtl8822b_set_channel; ops->set_chnl_bw_handler = rtl8822b_set_channel_bw; ops->set_tx_power_level_handler = rtl8822b_set_tx_power_level; @@ -4071,19 +4009,17 @@ void rtl8822b_set_hal_ops(PADAPTER adapter) ops->hal_dm_watchdog_in_lps = rtl8822b_phy_haldm_watchdog_in_lps; #endif - ops->SetHwRegHandler = rtl8822b_sethwreg; + ops->set_hw_reg_handler = rtl8822b_sethwreg; ops->GetHwRegHandler = rtl8822b_gethwreg; - ops->SetHwRegHandlerWithBuf = rtl8822b_sethwregwithbuf; - ops->GetHalDefVarHandler = rtl8822b_gethaldefvar; + ops->get_hal_def_var_handler = rtl8822b_gethaldefvar; ops->SetHalDefVarHandler = rtl8822b_sethaldefvar; ops->GetHalODMVarHandler = GetHalODMVar; ops->SetHalODMVarHandler = SetHalODMVar; - ops->UpdateRAMaskHandler = update_ra_mask; + ops->update_ra_mask_handler = update_ra_mask_8822b; ops->SetBeaconRelatedRegistersHandler = set_beacon_related_registers; - ops->Add_RateATid = add_rateatid; /* ops->interface_ps_func = NULL; */ @@ -4125,10 +4061,7 @@ void rtl8822b_set_hal_ops(PADAPTER adapter) #endif ops->hal_notch_filter = rtl8822b_notch_filter_switch; -/* - ops->c2h_handler = NULL; - ops->c2h_id_filter_ccx = NULL; -*/ + ops->hal_mac_c2h_handler = rtl8822b_c2h_handler; ops->fill_h2c_cmd = rtl8822b_fillh2ccmd; ops->fill_fake_txdesc = fill_fake_txdesc; ops->fw_dl = rtl8822b_fw_dl; @@ -4152,4 +4085,5 @@ void rtl8822b_set_hal_ops(PADAPTER adapter) /* HALMAC related functions */ ops->init_mac_register = rtl8822b_phy_init_mac_register; ops->init_phy = rtl8822b_phy_init; + ops->reqtxrpt = rtl8822b_req_txrpt_cmd; } diff --git a/hal/rtl8822b/rtl8822b_phy.c b/hal/rtl8822b/rtl8822b_phy.c index 6030eea..e606317 100644 --- a/hal/rtl8822b/rtl8822b_phy.c +++ b/hal/rtl8822b/rtl8822b_phy.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8822B_PHY_C_ #include /* HAL_DATA_TYPE */ @@ -70,22 +65,21 @@ static void bb_rf_register_definition(PADAPTER adapter) u8 rtl8822b_phy_init_mac_register(PADAPTER adapter) { PHAL_DATA_TYPE hal; - u8 regfile[] = RTL8822B_PHY_MACREG; u8 ret = _TRUE; int res; - HAL_STATUS status; + enum hal_status status; hal = GET_HAL_DATA(adapter); ret = _FALSE; #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE - res = phy_ConfigMACWithParaFile(adapter, regfile); + res = phy_ConfigMACWithParaFile(adapter, PHY_FILE_MAC_REG); if (_SUCCESS == res) ret = _TRUE; #endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */ if (_FALSE == ret) { - status = ODM_ConfigMACWithHeaderFile(&hal->odmpriv); + status = odm_config_mac_with_header_file(&hal->odmpriv); if (HAL_STATUS_SUCCESS == status) ret = _TRUE; } @@ -98,25 +92,21 @@ u8 rtl8822b_phy_init_mac_register(PADAPTER adapter) static u8 _init_bb_reg(PADAPTER Adapter) { PHAL_DATA_TYPE hal = GET_HAL_DATA(Adapter); - u8 regfile[] = RTL8822B_PHY_REG; - u8 agcfile[] = RTL8822B_AGC_TAB; - u8 regfile_mp[] = RTL8822B_PHY_REG_MP; u8 ret = _TRUE; int res; - HAL_STATUS status; - + enum hal_status status; /* * 1. Read PHY_REG.TXT BB INIT!! */ ret = _FALSE; #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE - res = phy_ConfigBBWithParaFile(Adapter, regfile, CONFIG_BB_PHY_REG); + res = phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG); if (_SUCCESS == res) ret = _TRUE; #endif if (_FALSE == ret) { - status = ODM_ConfigBBWithHeaderFile(&hal->odmpriv, CONFIG_BB_PHY_REG); + status = odm_config_bb_with_header_file(&hal->odmpriv, CONFIG_BB_PHY_REG); if (HAL_STATUS_SUCCESS == status) ret = _TRUE; } @@ -133,12 +123,12 @@ static u8 _init_bb_reg(PADAPTER Adapter) */ ret = _FALSE; #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE - res = phy_ConfigBBWithMpParaFile(Adapter, regfile_mp); + res = phy_ConfigBBWithMpParaFile(Adapter, PHY_FILE_PHY_REG_MP); if (_SUCCESS == res) ret = _TRUE; #endif if (_FALSE == ret) { - status = ODM_ConfigBBWithHeaderFile(&hal->odmpriv, CONFIG_BB_PHY_REG_MP); + status = odm_config_bb_with_header_file(&hal->odmpriv, CONFIG_BB_PHY_REG_MP); if (HAL_STATUS_SUCCESS == status) ret = _TRUE; } @@ -154,12 +144,12 @@ static u8 _init_bb_reg(PADAPTER Adapter) */ ret = _FALSE; #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE - res = phy_ConfigBBWithParaFile(Adapter, agcfile, CONFIG_BB_AGC_TAB); + res = phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB); if (_SUCCESS == res) ret = _TRUE; #endif if (_FALSE == ret) { - status = ODM_ConfigBBWithHeaderFile(&hal->odmpriv, CONFIG_BB_AGC_TAB); + status = odm_config_bb_with_header_file(&hal->odmpriv, CONFIG_BB_AGC_TAB); if (HAL_STATUS_SUCCESS == status) ret = _TRUE; } @@ -183,7 +173,7 @@ static u8 init_bb_reg(PADAPTER adapter) */ ret = _init_bb_reg(adapter); - hal_set_crystal_cap(adapter, hal->CrystalCap); + hal_set_crystal_cap(adapter, hal->crystal_cap); return ret; } @@ -192,11 +182,10 @@ static u8 _init_rf_reg(PADAPTER adapter) { u8 path, phydm_path; PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - u8 regfile_a[] = RTL8822B_PHY_RADIO_A; - u8 regfile_b[] = RTL8822B_PHY_RADIO_B; +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE u8 *regfile; - u8 txpwrtrackfile[] = RTL8822B_TXPWR_TRACK; - HAL_STATUS status; +#endif + enum hal_status status; int res; u8 ret = _TRUE; @@ -209,12 +198,16 @@ static u8 _init_rf_reg(PADAPTER adapter) switch (path) { case RF_PATH_A: phydm_path = ODM_RF_PATH_A; - regfile = regfile_a; + #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + regfile = PHY_FILE_RADIO_A; + #endif break; case RF_PATH_B: phydm_path = ODM_RF_PATH_B; - regfile = regfile_b; + #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + regfile = PHY_FILE_RADIO_B; + #endif break; default: @@ -229,7 +222,7 @@ static u8 _init_rf_reg(PADAPTER adapter) ret = _TRUE; #endif if (_FALSE == ret) { - status = ODM_ConfigRFWithHeaderFile(&hal->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)phydm_path); + status = odm_config_rf_with_header_file(&hal->odmpriv, CONFIG_RF_RADIO, (enum odm_rf_radio_path_e)phydm_path); if (HAL_STATUS_SUCCESS != status) goto exit; ret = _TRUE; @@ -241,12 +234,12 @@ static u8 _init_rf_reg(PADAPTER adapter) */ ret = _FALSE; #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE - res = PHY_ConfigRFWithTxPwrTrackParaFile(adapter, txpwrtrackfile); + res = PHY_ConfigRFWithTxPwrTrackParaFile(adapter, PHY_FILE_TXPWR_TRACK); if (_SUCCESS == res) ret = _TRUE; #endif if (_FALSE == ret) { - status = ODM_ConfigRFWithTxPwrTrackHeaderFile(&hal->odmpriv); + status = odm_config_rf_with_tx_pwr_track_header_file(&hal->odmpriv); if (HAL_STATUS_SUCCESS != status) { RTW_INFO("%s: Write PwrTrack Table Fail!\n", __FUNCTION__); goto exit; @@ -279,9 +272,9 @@ static u8 init_rf_reg(PADAPTER adapter) u8 rtl8822b_phy_init(PADAPTER adapter) { PHAL_DATA_TYPE hal; - PDM_ODM_T phydm; + struct PHY_DM_STRUCT *phydm; u8 rf_type; - ODM_RF_PATH_E txpath, rxpath; + enum odm_rf_path_e txpath, rxpath; BOOLEAN tx2path; u8 ok = _TRUE; BOOLEAN ret; @@ -294,7 +287,7 @@ u8 rtl8822b_phy_init(PADAPTER adapter) rtw_halmac_phy_power_switch(adapter_to_dvobj(adapter), _TRUE); - ret = config_phydm_parameter_init(phydm, ODM_PRE_SETTING); + ret = config_phydm_parameter_init_8822b(phydm, ODM_PRE_SETTING); if (FALSE == ret) return _FALSE; @@ -305,7 +298,7 @@ u8 rtl8822b_phy_init(PADAPTER adapter) if (_FALSE == ok) return _FALSE; - ret = config_phydm_parameter_init(phydm, ODM_POST_SETTING); + ret = config_phydm_parameter_init_8822b(phydm, ODM_POST_SETTING); if (FALSE == ret) return _FALSE; @@ -446,6 +439,38 @@ void dm_InterruptMigration(PADAPTER adapter) } #endif /* CONFIG_PCI_HCI */ +#ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 +void dm_HalBeamformingConfigCSIRate(PADAPTER adapter) +{ + struct PHY_DM_STRUCT *p_dm_odm; + struct beamforming_info *bf_info; + u8 fix_rate_enable = 0; + u8 new_csi_rate_idx; + + /* Acting as BFee */ + if (IS_BEAMFORMEE(adapter)) { + #if 0 + /* Do not enable now because it will affect MU performance and CTS/BA rate. 2016.07.19. by tynli. [PCIE-1660] */ + if (IS_HARDWARE_TYPE_8821C(Adapter)) + FixRateEnable = 1; /* Support after 8821C */ + #endif + + p_dm_odm = GET_ODM(adapter); + bf_info = GET_BEAMFORM_INFO(adapter); + + rtw_halmac_bf_cfg_csi_rate(adapter_to_dvobj(adapter), + p_dm_odm->rssi_min, + bf_info->cur_csi_rpt_rate, + fix_rate_enable, &new_csi_rate_idx); + + if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) + bf_info->cur_csi_rpt_rate = new_csi_rate_idx; + } +} +#endif /* RTW_BEAMFORMING_VERSION_2 */ +#endif /* CONFIG_BEAMFORMING */ + /* * ============================================================ * functions @@ -454,152 +479,89 @@ void dm_InterruptMigration(PADAPTER adapter) static void init_phydm_cominfo(PADAPTER adapter) { PHAL_DATA_TYPE hal; - PDM_ODM_T pDM_Odm; - u32 SupportAbility = 0; + struct PHY_DM_STRUCT *p_dm_odm; + u32 support_ability = 0; u8 cut_ver = ODM_CUT_A, fab_ver = ODM_TSMC; hal = GET_HAL_DATA(adapter); - pDM_Odm = &hal->odmpriv; + p_dm_odm = &hal->odmpriv; Init_ODM_ComInfo(adapter); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, hal->PackageType); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_IC_TYPE, ODM_RTL8822B); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, hal->PackageType); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_IC_TYPE, ODM_RTL8822B); - if (IS_CHIP_VENDOR_TSMC(hal->VersionID)) + if (IS_CHIP_VENDOR_TSMC(hal->version_id)) fab_ver = ODM_TSMC; - else if (IS_CHIP_VENDOR_UMC(hal->VersionID)) + else if (IS_CHIP_VENDOR_UMC(hal->version_id)) fab_ver = ODM_UMC; - else if (IS_CHIP_VENDOR_SMIC(hal->VersionID)) + else if (IS_CHIP_VENDOR_SMIC(hal->version_id)) fab_ver = ODM_UMC + 1; else RTW_INFO("%s: unknown fab_ver=%d !!\n", - __FUNCTION__, GET_CVID_MANUFACTUER(hal->VersionID)); + __FUNCTION__, GET_CVID_MANUFACTUER(hal->version_id)); - if (IS_A_CUT(hal->VersionID)) + if (IS_A_CUT(hal->version_id)) cut_ver = ODM_CUT_A; - else if (IS_B_CUT(hal->VersionID)) + else if (IS_B_CUT(hal->version_id)) cut_ver = ODM_CUT_B; - else if (IS_C_CUT(hal->VersionID)) + else if (IS_C_CUT(hal->version_id)) cut_ver = ODM_CUT_C; - else if (IS_D_CUT(hal->VersionID)) + else if (IS_D_CUT(hal->version_id)) cut_ver = ODM_CUT_D; - else if (IS_E_CUT(hal->VersionID)) + else if (IS_E_CUT(hal->version_id)) cut_ver = ODM_CUT_E; - else if (IS_F_CUT(hal->VersionID)) + else if (IS_F_CUT(hal->version_id)) cut_ver = ODM_CUT_F; - else if (IS_I_CUT(hal->VersionID)) + else if (IS_I_CUT(hal->version_id)) cut_ver = ODM_CUT_I; - else if (IS_J_CUT(hal->VersionID)) + else if (IS_J_CUT(hal->version_id)) cut_ver = ODM_CUT_J; - else if (IS_K_CUT(hal->VersionID)) + else if (IS_K_CUT(hal->version_id)) cut_ver = ODM_CUT_K; else RTW_INFO("%s: unknown cut_ver=%d !!\n", - __FUNCTION__, GET_CVID_CUT_VERSION(hal->VersionID)); + __FUNCTION__, GET_CVID_CUT_VERSION(hal->version_id)); RTW_INFO("%s: fab_ver=%d cut_ver=%d\n", __FUNCTION__, fab_ver, cut_ver); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_FAB_VER, fab_ver); - ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_CUT_VER, cut_ver); - -#ifdef CONFIG_DISABLE_ODM - SupportAbility = 0; -#else /* !CONFIG_DISABLE_ODM */ - SupportAbility = ODM_RF_CALIBRATION | ODM_RF_TX_PWR_TRACK; -#endif /* !CONFIG_DISABLE_ODM */ - ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, SupportAbility); -} + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_FAB_VER, fab_ver); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_CUT_VER, cut_ver); -static void update_phydm_cominfo(PADAPTER adapter) -{ - PHAL_DATA_TYPE hal; - PDM_ODM_T pDM_Odm; - u32 SupportAbility = 0; - - - hal = GET_HAL_DATA(adapter); - pDM_Odm = &hal->odmpriv; - - SupportAbility = 0 - | ODM_BB_DIG - | ODM_BB_RA_MASK - | ODM_BB_DYNAMIC_TXPWR - | ODM_BB_FA_CNT - | ODM_BB_RSSI_MONITOR - | ODM_BB_CCK_PD -/* | ODM_BB_PWR_SAVE*/ - | ODM_BB_CFO_TRACKING - | ODM_MAC_EDCA_TURBO - | ODM_RF_TX_PWR_TRACK - | ODM_RF_CALIBRATION - | ODM_BB_NHM_CNT -/* | ODM_BB_PWR_TRAIN*/ - ; - - if (rtw_odm_adaptivity_needed(adapter) == _TRUE) - SupportAbility |= ODM_BB_ADAPTIVITY; - -#ifdef CONFIG_ANTENNA_DIVERSITY - if (hal->AntDivCfg) - SupportAbility |= ODM_BB_ANT_DIV; -#endif /* CONFIG_ANTENNA_DIVERSITY */ - -#ifdef CONFIG_MP_INCLUDED - if (adapter->registrypriv.mp_mode == 1) { - SupportAbility = 0 - | ODM_RF_CALIBRATION - | ODM_RF_TX_PWR_TRACK - ; - } -#endif /* CONFIG_MP_INCLUDED */ - -#ifdef CONFIG_DISABLE_ODM - SupportAbility = 0; -#endif /* CONFIG_DISABLE_ODM */ - - ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, SupportAbility); } void rtl8822b_phy_init_dm_priv(PADAPTER adapter) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - PDM_ODM_T podmpriv = &hal->odmpriv; - - - /* - * Call this before other phydm functions - * to guarantee debug messages of phydm would be printed. - */ - PHYDM_InitDebugSetting(podmpriv); + struct PHY_DM_STRUCT *podmpriv = &hal->odmpriv; init_phydm_cominfo(adapter); - ODM_InitAllTimers(podmpriv); + odm_init_all_timers(podmpriv); + /*PHYDM API - thermal trim*/ + phydm_get_thermal_trim_offset(podmpriv); + /*PHYDM API - power trim*/ + phydm_get_power_trim_offset(podmpriv); + } void rtl8822b_phy_deinit_dm_priv(PADAPTER adapter) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - PDM_ODM_T podmpriv = &hal->odmpriv; + struct PHY_DM_STRUCT *podmpriv = &hal->odmpriv; - - ODM_CancelAllTimers(podmpriv); + odm_cancel_all_timers(podmpriv); } void rtl8822b_phy_init_haldm(PADAPTER adapter) { PHAL_DATA_TYPE hal; - PDM_ODM_T pDM_Odm; + struct PHY_DM_STRUCT *p_dm_odm; hal = GET_HAL_DATA(adapter); - pDM_Odm = &hal->odmpriv; - - hal->DM_Type = DM_Type_ByDriver; + p_dm_odm = &hal->odmpriv; - update_phydm_cominfo(adapter); - - ODM_DMInit(pDM_Odm); + odm_dm_init(p_dm_odm); } static void check_rxfifo_full(PADAPTER adapter) @@ -607,16 +569,19 @@ static void check_rxfifo_full(PADAPTER adapter) struct dvobj_priv *psdpriv = adapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); + struct registry_priv *regsty = &adapter->registrypriv; u8 val8 = 0; - /* switch counter to RX fifo */ - val8 = rtw_read8(adapter, REG_RXERR_RPT_8822B + 3); - rtw_write8(adapter, REG_RXERR_RPT_8822B + 3, (val8 | 0xa0)); + if (regsty->check_hw_status == 1) { + /* switch counter to RX fifo */ + val8 = rtw_read8(adapter, REG_RXERR_RPT_8822B + 3); + rtw_write8(adapter, REG_RXERR_RPT_8822B + 3, (val8 | 0xa0)); - pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow; - pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT_8822B); - pdbgpriv->dbg_rx_fifo_diff_overflow = - pdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow; + pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow; + pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT_8822B); + pdbgpriv->dbg_rx_fifo_diff_overflow = + pdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow; + } } void rtl8822b_phy_haldm_watchdog(PADAPTER adapter) @@ -641,13 +606,13 @@ void rtl8822b_phy_haldm_watchdog(PADAPTER adapter) rtw_hal_get_hwreg(adapter, HW_VAR_FWLPS_RF_ON, (u8 *)&bFwPSAwake); #endif /* CONFIG_LPS */ -#ifdef CONFIG_P2P +#ifdef CONFIG_P2P_PS /* * Fw is under p2p powersaving mode, driver should stop dynamic mechanism. */ if (adapter->wdinfo.p2p_ps_mode) bFwPSAwake = _FALSE; -#endif /* CONFIG_P2P */ +#endif /* CONFIG_P2P_PS */ if ((rtw_is_hw_init_completed(adapter)) && ((!bFwCurrentInPSMode) && bFwPSAwake)) { @@ -662,27 +627,35 @@ void rtl8822b_phy_haldm_watchdog(PADAPTER adapter) /* PHYDM */ if (rtw_is_hw_init_completed(adapter)) { - u8 bLinked = _FALSE; + u8 is_linked = _FALSE; u8 bsta_state = _FALSE; u8 bBtDisabled = _TRUE; if (rtw_mi_check_status(adapter, MI_ASSOC)) { - bLinked = _TRUE; + is_linked = _TRUE; if (rtw_mi_check_status(adapter, MI_STA_LINKED)) bsta_state = _TRUE; } - ODM_CmnInfoUpdate(&hal->odmpriv, ODM_CMNINFO_LINK, bLinked); - ODM_CmnInfoUpdate(&hal->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state); + odm_cmn_info_update(&hal->odmpriv, ODM_CMNINFO_LINK, is_linked); + odm_cmn_info_update(&hal->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state); #ifdef CONFIG_BT_COEXIST bBtDisabled = rtw_btcoex_IsBtDisabled(adapter); #endif /* CONFIG_BT_COEXIST */ - ODM_CmnInfoUpdate(&hal->odmpriv, ODM_CMNINFO_BT_ENABLED, ((bBtDisabled == _TRUE) ? _FALSE : _TRUE)); + odm_cmn_info_update(&hal->odmpriv, ODM_CMNINFO_BT_ENABLED, ((bBtDisabled == _TRUE) ? _FALSE : _TRUE)); - ODM_DMWatchdog(&hal->odmpriv); + odm_dm_watchdog(&hal->odmpriv); } +#ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 + if (check_fwstate(&adapter->mlmepriv, WIFI_STATION_STATE) && + check_fwstate(&adapter->mlmepriv, _FW_LINKED)) + dm_HalBeamformingConfigCSIRate(adapter); +#endif +#endif + skip_dm: /* * Check GPIO to determine current RF on/off and Pbc status. @@ -700,32 +673,32 @@ void rtl8822b_phy_haldm_in_lps(PADAPTER adapter) u32 PWDB_rssi = 0; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - PDM_ODM_T pDM_Odm = &hal->odmpriv; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + struct PHY_DM_STRUCT *p_dm_odm = &hal->odmpriv; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; struct sta_priv *pstapriv = &adapter->stapriv; struct sta_info *psta = NULL; - RTW_INFO("%s: RSSI_Min=%d\n", __FUNCTION__, pDM_Odm->RSSI_Min); + RTW_INFO("%s: rssi_min=%d\n", __FUNCTION__, p_dm_odm->rssi_min); /* update IGI */ - ODM_Write_DIG(pDM_Odm, pDM_Odm->RSSI_Min); + odm_write_dig(p_dm_odm, p_dm_odm->rssi_min); /* set rssi to fw */ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); - if (psta && (psta->rssi_stat.UndecoratedSmoothedPWDB > 0)) { - PWDB_rssi = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB << 16)); + if (psta && (psta->rssi_stat.undecorated_smoothed_pwdb > 0)) { + PWDB_rssi = (psta->mac_id | (psta->rssi_stat.undecorated_smoothed_pwdb << 16)); rtl8822b_set_FwRssiSetting_cmd(adapter, (u8 *)&PWDB_rssi); } } void rtl8822b_phy_haldm_watchdog_in_lps(PADAPTER adapter) { - u8 bLinked = _FALSE; + u8 is_linked = _FALSE; PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - PDM_ODM_T pDM_Odm = &hal->odmpriv; - pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + struct PHY_DM_STRUCT *p_dm_odm = &hal->odmpriv; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; struct sta_priv *pstapriv = &adapter->stapriv; struct sta_info *psta = NULL; @@ -733,14 +706,14 @@ void rtl8822b_phy_haldm_watchdog_in_lps(PADAPTER adapter) goto skip_lps_dm; if (rtw_mi_check_status(adapter, MI_ASSOC)) - bLinked = _TRUE; + is_linked = _TRUE; - ODM_CmnInfoUpdate(&hal->odmpriv, ODM_CMNINFO_LINK, bLinked); + odm_cmn_info_update(&hal->odmpriv, ODM_CMNINFO_LINK, is_linked); - if (bLinked == _FALSE) + if (is_linked == _FALSE) goto skip_lps_dm; - if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) + if (!(p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR)) goto skip_lps_dm; /* Do DIG by RSSI In LPS-32K */ @@ -750,21 +723,21 @@ void rtl8822b_phy_haldm_watchdog_in_lps(PADAPTER adapter) if (psta == NULL) goto skip_lps_dm; - hal->EntryMinUndecoratedSmoothedPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; + hal->entry_min_undecorated_smoothed_pwdb = psta->rssi_stat.undecorated_smoothed_pwdb; - RTW_INFO("CurIGValue=%d, EntryMinUndecoratedSmoothedPWDB=%d\n", - pDM_DigTable->CurIGValue, hal->EntryMinUndecoratedSmoothedPWDB); + RTW_INFO("CurIGValue=%d, entry_min_undecorated_smoothed_pwdb=%d\n", + p_dm_dig_table->cur_ig_value, hal->entry_min_undecorated_smoothed_pwdb); - if (hal->EntryMinUndecoratedSmoothedPWDB <= 0) + if (hal->entry_min_undecorated_smoothed_pwdb <= 0) goto skip_lps_dm; - hal->MinUndecoratedPWDBForDM = hal->EntryMinUndecoratedSmoothedPWDB; + hal->min_undecorated_pwdb_for_dm = hal->entry_min_undecorated_smoothed_pwdb; - pDM_Odm->RSSI_Min = hal->MinUndecoratedPWDBForDM; + p_dm_odm->rssi_min = hal->min_undecorated_pwdb_for_dm; #ifdef CONFIG_LPS - if ((pDM_DigTable->CurIGValue > pDM_Odm->RSSI_Min + 5) - || (pDM_DigTable->CurIGValue < pDM_Odm->RSSI_Min - 5)) + if ((p_dm_dig_table->cur_ig_value > p_dm_odm->rssi_min + 5) + || (p_dm_dig_table->cur_ig_value < p_dm_odm->rssi_min - 5)) rtw_dm_in_lps_wk_cmd(adapter); #endif @@ -822,7 +795,7 @@ void rtl8822b_write_bb_reg(PADAPTER adapter, u32 addr, u32 mask, u32 val) u32 rtl8822b_read_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask) { PHAL_DATA_TYPE hal; - PDM_ODM_T phydm; + struct PHY_DM_STRUCT *phydm; u32 val; @@ -840,7 +813,7 @@ u32 rtl8822b_read_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask) void rtl8822b_write_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask, u32 val) { PHAL_DATA_TYPE hal; - PDM_ODM_T phydm; + struct PHY_DM_STRUCT *phydm; u8 ret; @@ -855,29 +828,29 @@ void rtl8822b_write_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask, u32 va static void set_tx_power_level_by_path(PADAPTER adapter, u8 channel, u8 path) { - PHY_SetTxPowerIndexByRateSection(adapter, path, channel, CCK); - PHY_SetTxPowerIndexByRateSection(adapter, path, channel, OFDM); - PHY_SetTxPowerIndexByRateSection(adapter, path, channel, HT_MCS0_MCS7); - PHY_SetTxPowerIndexByRateSection(adapter, path, channel, HT_MCS8_MCS15); - PHY_SetTxPowerIndexByRateSection(adapter, path, channel, VHT_1SSMCS0_1SSMCS9); - PHY_SetTxPowerIndexByRateSection(adapter, path, channel, VHT_2SSMCS0_2SSMCS9); + phy_set_tx_power_index_by_rate_section(adapter, path, channel, CCK); + phy_set_tx_power_index_by_rate_section(adapter, path, channel, OFDM); + phy_set_tx_power_index_by_rate_section(adapter, path, channel, HT_MCS0_MCS7); + phy_set_tx_power_index_by_rate_section(adapter, path, channel, HT_MCS8_MCS15); + phy_set_tx_power_index_by_rate_section(adapter, path, channel, VHT_1SSMCS0_1SSMCS9); + phy_set_tx_power_index_by_rate_section(adapter, path, channel, VHT_2SSMCS0_2SSMCS9); } void rtl8822b_set_tx_power_level(PADAPTER adapter, u8 channel) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - PDM_ODM_T phydm; - pFAT_T pDM_FatTable; + struct PHY_DM_STRUCT *phydm; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table; u8 path = ODM_RF_PATH_A; hal = GET_HAL_DATA(adapter); phydm = &hal->odmpriv; - pDM_FatTable = &phydm->DM_FatTable; + p_dm_fat_table = &phydm->dm_fat_table; if (hal->AntDivCfg) { /* antenna diversity Enable */ - path = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B; + path = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B; set_tx_power_level_by_path(adapter, channel, path); } else { /* antenna diversity disable */ @@ -894,13 +867,13 @@ void rtl8822b_get_tx_power_level(PADAPTER adapter, s32 *power) * Parameters: * padatper * powerindex power index for rate - * rfpath Antenna(RF) path, type "enum _ODM_RF_RADIO_PATH" + * rfpath Antenna(RF) path, type "enum odm_rf_radio_path_e" * rate data rate, type "enum MGN_RATE" */ void rtl8822b_set_tx_power_index(PADAPTER adapter, u32 powerindex, u8 rfpath, u8 rate) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - PDM_ODM_T phydm = &hal->odmpriv; + struct PHY_DM_STRUCT *phydm = &hal->odmpriv; u8 shift = 0; static u32 index = 0; @@ -919,7 +892,7 @@ void rtl8822b_set_tx_power_index(PADAPTER adapter, u32 powerindex, u8 rfpath, u8 if (!config_phydm_write_txagc_8822b(phydm, index, rfpath, rate)) { RTW_INFO("%s(index:%d, rfpath:%d, rate:0x%02x, disable api:%d) fail\n", - __FUNCTION__, index, rfpath, rate, phydm->bDisablePhyApi); + __FUNCTION__, index, rfpath, rate, phydm->is_disable_phy_api); rtw_warn_on(1); } @@ -943,7 +916,7 @@ static u8 rtl8822b_phy_get_current_tx_num(PADAPTER adapter, u8 rate) /* * Parameters: * padatper - * rfpath Antenna(RF) path, type "enum _ODM_RF_RADIO_PATH" + * rfpath Antenna(RF) path, type "enum odm_rf_radio_path_e" * rate data rate, type "enum MGN_RATE" * bandwidth Bandwidth, type "enum _CHANNEL_WIDTH" * channel Channel number @@ -951,36 +924,44 @@ static u8 rtl8822b_phy_get_current_tx_num(PADAPTER adapter, u8 rate) * Rteurn: * tx_power power index for rate */ -u8 rtl8822b_get_tx_power_index(PADAPTER adapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel) +u8 rtl8822b_get_tx_power_index(PADAPTER adapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - s8 power_diff_by_rate = 0; - s8 tx_power = 0, limit = 0; - u8 tx_num = rtl8822b_phy_get_current_tx_num(adapter, rate); + u8 base_idx = 0, power_idx = 0; + s8 by_rate_diff = 0, limit = 0, tpt_offset = 0, extra_bias = 0; + u8 ntx_idx = rtl8822b_phy_get_current_tx_num(adapter, rate); u8 bIn24G = _FALSE; + base_idx = PHY_GetTxPowerIndexBase(adapter, rfpath, rate, ntx_idx, bandwidth, channel, &bIn24G); - tx_power = (s8) PHY_GetTxPowerIndexBase(adapter, rfpath, rate, bandwidth, channel, &bIn24G); + by_rate_diff = PHY_GetTxPowerByRate(adapter, (u8)(!bIn24G), rfpath, rate); + limit = PHY_GetTxPowerLimit(adapter, NULL, (BAND_TYPE)(!bIn24G), + hal->current_channel_bw, rfpath, rate, ntx_idx, hal->current_channel); - power_diff_by_rate = PHY_GetTxPowerByRate(adapter, (u8)(!bIn24G), rfpath, tx_num, rate); + /* tpt_offset += PHY_GetTxPowerTrackingOffset(adapter, rfpath, rate); */ - limit = PHY_GetTxPowerLimit(adapter, adapter->registrypriv.RegPwrTblSel, (BAND_TYPE)(!bIn24G), - hal->CurrentChannelBW, rfpath, rate, hal->CurrentChannel); - - power_diff_by_rate = power_diff_by_rate > limit ? limit : power_diff_by_rate; + if (tic) { + tic->ntx_idx = ntx_idx; + tic->base = base_idx; + tic->by_rate = by_rate_diff; + tic->limit = limit; + tic->tpt = tpt_offset; + tic->ebias = extra_bias; + } - tx_power += power_diff_by_rate; + by_rate_diff = by_rate_diff > limit ? limit : by_rate_diff; + power_idx = base_idx + by_rate_diff + tpt_offset + extra_bias; #if 0 #if CCX_SUPPORT - CCX_CellPowerLimit(pAdapter, Channel, Rate, (u8 *)&txPower); + CCX_CellPowerLimit(adapter, channel, rate, (pu1Byte)&power_idx); #endif #endif - if (tx_power > MAX_POWER_INDEX) - tx_power = MAX_POWER_INDEX; + if (power_idx > MAX_POWER_INDEX) + power_idx = MAX_POWER_INDEX; - return tx_power; + return power_idx; } /* @@ -999,7 +980,7 @@ static u8 need_switch_band(PADAPTER adapter, u8 channelToSW) u8 Band = BAND_ON_5G, BandToSW = BAND_ON_5G; PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - Band = hal->CurrentBandType; + Band = hal->current_band_type; /* Use current swich channel to judge Band Type and switch Band if need */ if (channelToSW > 14) @@ -1009,7 +990,7 @@ static u8 need_switch_band(PADAPTER adapter, u8 channelToSW) if (BandToSW != Band) { /* record current band type for other hal use */ - hal->CurrentBandType = (BAND_TYPE)BandToSW; + hal->current_band_type = (BAND_TYPE)BandToSW; ret_value = _TRUE; } else ret_value = _FALSE; @@ -1022,7 +1003,7 @@ static u8 get_pri_ch_id(PADAPTER adapter) u8 pri_ch_idx = 0; PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - if (hal->CurrentChannelBW == CHANNEL_WIDTH_80) { + if (hal->current_channel_bw == CHANNEL_WIDTH_80) { /* primary channel is at lower subband of 80MHz & 40MHz */ if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ; @@ -1043,7 +1024,7 @@ static u8 get_pri_ch_id(PADAPTER adapter) else RTW_INFO("SCMapping: DONOT CARE Mode Setting\n"); } - } else if (hal->CurrentChannelBW == CHANNEL_WIDTH_40) { + } else if (hal->current_channel_bw == CHANNEL_WIDTH_40) { /* primary channel is at upper subband of 40MHz */ if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ; @@ -1063,8 +1044,8 @@ static void mac_switch_bandwidth(PADAPTER adapter, u8 pri_ch_idx) PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); int err; - channel = hal->CurrentChannel; - bw = hal->CurrentChannelBW; + channel = hal->current_channel; + bw = hal->current_channel_bw; err = rtw_halmac_set_bandwidth(adapter_to_dvobj(adapter), channel, pri_ch_idx, bw); if (err) { RTW_INFO(FUNC_ADPT_FMT ": (channel=%d, pri_ch_idx=%d, bw=%d) fail\n", @@ -1079,16 +1060,16 @@ static void mac_switch_bandwidth(PADAPTER adapter, u8 pri_ch_idx) void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - PDM_ODM_T pDM_Odm = &hal->odmpriv; + struct PHY_DM_STRUCT *p_dm_odm = &hal->odmpriv; u8 center_ch = 0, ret = 0; if (adapter->bNotifyChannelChange) { RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n", __FUNCTION__, hal->bSwChnl, - hal->CurrentChannel, + hal->current_channel, hal->bSetChnlBW, - hal->CurrentChannelBW); + hal->current_channel_bw); } if (RTW_CANNOT_RUN(adapter)) { @@ -1098,7 +1079,7 @@ void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) /* set channel & Bandwidth register */ /* 1. set switch band register if need to switch band */ - if (need_switch_band(adapter, hal->CurrentChannel) == _TRUE) { + if (need_switch_band(adapter, hal->current_channel) == _TRUE) { #ifdef CONFIG_BT_COEXIST if (hal->EEPROMBluetoothCoexist) { struct mlme_ext_priv *mlmeext; @@ -1106,14 +1087,17 @@ void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) /* switch band under site survey or not, must notify to BT COEX */ mlmeext = &adapter->mlmeextpriv; if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE) - rtw_btcoex_switchband_notify(_TRUE, hal->CurrentBandType); + rtw_btcoex_switchband_notify(_TRUE, hal->current_band_type); else - rtw_btcoex_switchband_notify(_FALSE, hal->CurrentBandType); - } + rtw_btcoex_switchband_notify(_FALSE, hal->current_band_type); + } else + rtw_btcoex_wifionly_switchband_notify(adapter); +#else /* !CONFIG_BT_COEXIST */ + rtw_btcoex_wifionly_switchband_notify(adapter); #endif /* CONFIG_BT_COEXIST */ - /* hal->CurrentChannel is center channel of pmlmeext->cur_channel(primary channel) */ - ret = config_phydm_switch_band_8822b(pDM_Odm, hal->CurrentChannel); + /* hal->current_channel is center channel of pmlmeext->cur_channel(primary channel) */ + ret = config_phydm_switch_band_8822b(p_dm_odm, hal->current_channel); if (!ret) { RTW_INFO("%s: config_phydm_switch_band_8822b fail\n", __FUNCTION__); @@ -1126,10 +1110,10 @@ void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) if (adapter->registrypriv.mp_mode == _TRUE) { /* <2016/02/25, VincentL> Add for 8822B Antenna Binding between "2.4G-WiFi" And between "5G-BT", Suggested by RF SzuyiTsai*/ - if (hal->CurrentChannel <= 14) /* 2.4G*/ - PHY_SetRFPathSwitch_8822B(adapter, 1); /*To WiFi-2.4G*/ + if (hal->current_channel <= 14) /* 2.4G*/ + phy_set_rf_path_switch_8822b(adapter, 1); /*To WiFi-2.4G*/ else /* 5G */ - PHY_SetRFPathSwitch_8822B(adapter, 0); /*To BT-5G*/ + phy_set_rf_path_switch_8822b(adapter, 0); /*To BT-5G*/ } #endif @@ -1137,7 +1121,7 @@ void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) /* 2. set channel register */ if (hal->bSwChnl) { - ret = config_phydm_switch_channel_8822b(pDM_Odm, hal->CurrentChannel); + ret = config_phydm_switch_channel_8822b(p_dm_odm, hal->current_channel); hal->bSwChnl = _FALSE; if (!ret) { @@ -1146,7 +1130,7 @@ void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) return; } } - + phydm_config_kfree(p_dm_odm, hal->current_channel); /* 3. set Bandwidth register */ if (hal->bSetChnlBW) { /* get primary channel index */ @@ -1156,7 +1140,7 @@ void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) mac_switch_bandwidth(adapter, pri_ch_idx); /* 3.2 set BB/RF registet */ - ret = config_phydm_switch_bandwidth_8822b(pDM_Odm, pri_ch_idx, hal->CurrentChannelBW); + ret = config_phydm_switch_bandwidth_8822b(p_dm_odm, pri_ch_idx, hal->current_channel_bw); hal->bSetChnlBW = _FALSE; if (!ret) { @@ -1167,13 +1151,13 @@ void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) } /* TX Power Setting */ - ODM_ClearTxPowerTrackingState(pDM_Odm); - rtw_hal_set_tx_power_level(adapter, hal->CurrentChannel); + odm_clear_txpowertracking_state(p_dm_odm); + rtw_hal_set_tx_power_level(adapter, hal->current_channel); /* IQK */ if ((hal->bNeedIQK == _TRUE) || (adapter->registrypriv.mp_mode == 1)) { - PHY_IQCalibrate_8822B(pDM_Odm, _FALSE); + phy_iq_calibrate_8822b(p_dm_odm, _FALSE); hal->bNeedIQK = _FALSE; } } @@ -1198,8 +1182,8 @@ void rtl8822b_handle_sw_chnl_and_set_bw( { PADAPTER pDefAdapter = GetDefaultAdapter(Adapter); PHAL_DATA_TYPE hal = GET_HAL_DATA(pDefAdapter); - u8 tmpChannel = hal->CurrentChannel; - CHANNEL_WIDTH tmpBW = hal->CurrentChannelBW; + u8 tmpChannel = hal->current_channel; + CHANNEL_WIDTH tmpBW = hal->current_channel_bw; u8 tmpnCur40MhzPrimeSC = hal->nCur40MhzPrimeSC; u8 tmpnCur80MhzPrimeSC = hal->nCur80MhzPrimeSC; u8 tmpCenterFrequencyIndex1 = hal->CurrentCenterFrequencyIndex1; @@ -1214,7 +1198,7 @@ void rtl8822b_handle_sw_chnl_and_set_bw( /* skip switch channel operation for current channel & ChannelNum(will be switch) are the same */ if (bSwitchChannel) { - if (hal->CurrentChannel != ChannelNum) { + if (hal->current_channel != ChannelNum) { if (HAL_IsLegalChannel(Adapter, ChannelNum)) hal->bSwChnl = _TRUE; else @@ -1228,7 +1212,7 @@ void rtl8822b_handle_sw_chnl_and_set_bw( if (hal->bChnlBWInitialized == _FALSE) { hal->bChnlBWInitialized = _TRUE; hal->bSetChnlBW = _TRUE; - } else if ((hal->CurrentChannelBW != ChnlWidth) || /* check whether need set band or not */ + } else if ((hal->current_channel_bw != ChnlWidth) || /* check whether need set band or not */ (hal->nCur40MhzPrimeSC != ChnlOffsetOf40MHz) || (hal->nCur80MhzPrimeSC != ChnlOffsetOf80MHz) || (hal->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1)) @@ -1236,18 +1220,18 @@ void rtl8822b_handle_sw_chnl_and_set_bw( } /* return if not need set bandwidth nor channel after check*/ - if (!hal->bSetChnlBW && !hal->bSwChnl) + if (!hal->bSetChnlBW && !hal->bSwChnl && hal->bNeedIQK != _TRUE) return; /* set channel number to hal data */ if (hal->bSwChnl) { - hal->CurrentChannel = ChannelNum; + hal->current_channel = ChannelNum; hal->CurrentCenterFrequencyIndex1 = ChannelNum; } /* set bandwidth info to hal data */ if (hal->bSetChnlBW) { - hal->CurrentChannelBW = ChnlWidth; + hal->current_channel_bw = ChnlWidth; hal->nCur40MhzPrimeSC = ChnlOffsetOf40MHz; hal->nCur80MhzPrimeSC = ChnlOffsetOf80MHz; hal->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1; @@ -1258,12 +1242,12 @@ void rtl8822b_handle_sw_chnl_and_set_bw( rtl8822b_switch_chnl_and_set_bw(Adapter); else { if (hal->bSwChnl) { - hal->CurrentChannel = tmpChannel; + hal->current_channel = tmpChannel; hal->CurrentCenterFrequencyIndex1 = tmpChannel; } if (hal->bSetChnlBW) { - hal->CurrentChannelBW = tmpBW; + hal->current_channel_bw = tmpBW; hal->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC; hal->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC; hal->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1; @@ -1271,33 +1255,6 @@ void rtl8822b_handle_sw_chnl_and_set_bw( } } -/* - * Description: - * Change bandwidth, current channel is the same - * Parameters: - * bw bandwidth - * offset channel offset for 40MHz or 80MHz Bandwidth according to bw - */ -void rtl8822b_set_bw_mode(PADAPTER adapter, CHANNEL_WIDTH bw, u8 offset) -{ - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - - rtl8822b_handle_sw_chnl_and_set_bw(adapter, _FALSE, _TRUE, hal->CurrentChannel, bw, offset, offset, hal->CurrentChannel); -} - -/* - * Description: - * Change channel, and bandwidth & offset are not changed - * Parameters: - * center_ch center channel - */ -void rtl8822b_set_channel(PADAPTER adapter, u8 center_ch) -{ - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - - rtl8822b_handle_sw_chnl_and_set_bw(adapter, _TRUE, _FALSE, center_ch, 0, 0, 0, center_ch); -} - /* * Description: * Change channel, bandwidth & offset @@ -1333,25 +1290,26 @@ void rtl8822b_mp_config_rfpath(PADAPTER adapter) PHAL_DATA_TYPE hal; PMPT_CONTEXT mpt; ANTENNA_PATH anttx, antrx; - ODM_RF_PATH_E rxant; + enum odm_rf_path_e rxant; hal = GET_HAL_DATA(adapter); - mpt = &adapter->mppriv.MptCtx; - anttx = hal->AntennaTxPath; + mpt = &adapter->mppriv.mpt_ctx; + anttx = hal->antenna_tx_path; antrx = hal->AntennaRxPath; + hal->antenna_test = _TRUE; RTW_INFO("+Config RF Path, tx=0x%x rx=0x%x\n", anttx, antrx); switch (anttx) { case ANTENNA_A: - mpt->MptRfPath = ODM_RF_A; + mpt->mpt_rf_path = ODM_RF_A; break; case ANTENNA_B: - mpt->MptRfPath = ODM_RF_B; + mpt->mpt_rf_path = ODM_RF_B; break; case ANTENNA_AB: default: - mpt->MptRfPath = ODM_RF_A | ODM_RF_B; + mpt->mpt_rf_path = ODM_RF_A | ODM_RF_B; break; } @@ -1368,832 +1326,1118 @@ void rtl8822b_mp_config_rfpath(PADAPTER adapter) break; } - config_phydm_trx_mode_8822b(GET_PDM_ODM(adapter), mpt->MptRfPath, rxant, FALSE); + config_phydm_trx_mode_8822b(GET_PDM_ODM(adapter), mpt->mpt_rf_path, rxant, FALSE); RTW_INFO("-Config RF Path Finish\n"); } #endif /* CONFIG_MP_INCLUDED */ #ifdef CONFIG_BEAMFORMING -void rtl8822b_phy_init_beamforming(PADAPTER adapter) -{ - u8 v8; - u32 v32; +/* REG_TXBF_CTRL (Offset 0x42C) */ +#define BITS_R_TXBF1_AID_8822B (BIT_MASK_R_TXBF1_AID_8822B << BIT_SHIFT_R_TXBF1_AID_8822B) +#define BIT_CLEAR_R_TXBF1_AID_8822B(x) ((x) & (~BITS_R_TXBF1_AID_8822B)) +#define BIT_SET_R_TXBF1_AID_8822B(x, v) (BIT_CLEAR_R_TXBF1_AID_8822B(x) | BIT_R_TXBF1_AID_8822B(v)) + +#define BITS_R_TXBF0_AID_8822B (BIT_MASK_R_TXBF0_AID_8822B << BIT_SHIFT_R_TXBF0_AID_8822B) +#define BIT_CLEAR_R_TXBF0_AID_8822B(x) ((x) & (~BITS_R_TXBF0_AID_8822B)) +#define BIT_SET_R_TXBF0_AID_8822B(x, v) (BIT_CLEAR_R_TXBF0_AID_8822B(x) | BIT_R_TXBF0_AID_8822B(v)) + +/* REG_NDPA_OPT_CTRL (Offset 0x45F) */ +#define BITS_R_NDPA_BW_8822B (BIT_MASK_R_NDPA_BW_8822B << BIT_SHIFT_R_NDPA_BW_8822B) +#define BIT_CLEAR_R_NDPA_BW_8822B(x) ((x) & (~BITS_R_NDPA_BW_8822B)) +#define BIT_SET_R_NDPA_BW_8822B(x, v) (BIT_CLEAR_R_NDPA_BW_8822B(x) | BIT_R_NDPA_BW_8822B(v)) + +/* REG_ASSOCIATED_BFMEE_SEL (Offset 0x714) */ +#define BITS_AID1_8822B (BIT_MASK_AID1_8822B << BIT_SHIFT_AID1_8822B) +#define BIT_CLEAR_AID1_8822B(x) ((x) & (~BITS_AID1_8822B)) +#define BIT_SET_AID1_8822B(x, v) (BIT_CLEAR_AID1_8822B(x) | BIT_AID1_8822B(v)) + +#define BITS_AID0_8822B (BIT_MASK_AID0_8822B << BIT_SHIFT_AID0_8822B) +#define BIT_CLEAR_AID0_8822B(x) ((x) & (~BITS_AID0_8822B)) +#define BIT_SET_AID0_8822B(x, v) (BIT_CLEAR_AID0_8822B(x) | BIT_AID0_8822B(v)) + +/* REG_SND_PTCL_CTRL (Offset 0x718) */ +#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8822B BIT(15) + +/* REG_MU_TX_CTL (Offset 0x14C0) */ +#define BIT_R_MU_P1_WAIT_STATE_EN_8822B BIT(16) + +#define BIT_SHIFT_R_MU_RL_8822B 12 +#define BIT_MASK_R_MU_RL_8822B 0xF +#define BITS_R_MU_RL_8822B (BIT_MASK_R_MU_RL_8822B << BIT_SHIFT_R_MU_RL_8822B) +#define BIT_R_MU_RL_8822B(x) (((x) & BIT_MASK_R_MU_RL_8822B) << BIT_SHIFT_R_MU_RL_8822B) +#define BIT_CLEAR_R_MU_RL_8822B(x) ((x) & (~BITS_R_MU_RL_8822B)) +#define BIT_SET_R_MU_RL_8822B(x, v) (BIT_CLEAR_R_MU_RL_8822B(x) | BIT_R_MU_RL_8822B(v)) + +#define BIT_SHIFT_R_MU_TAB_SEL_8822B 8 +#define BIT_MASK_R_MU_TAB_SEL_8822B 0x7 +#define BITS_R_MU_TAB_SEL_8822B (BIT_MASK_R_MU_TAB_SEL_8822B << BIT_SHIFT_R_MU_TAB_SEL_8822B) +#define BIT_R_MU_TAB_SEL_8822B(x) (((x) & BIT_MASK_R_MU_TAB_SEL_8822B) << BIT_SHIFT_R_MU_TAB_SEL_8822B) +#define BIT_CLEAR_R_MU_TAB_SEL_8822B(x) ((x) & (~BITS_R_MU_TAB_SEL_8822B)) +#define BIT_SET_R_MU_TAB_SEL_8822B(x, v) (BIT_CLEAR_R_MU_TAB_SEL_8822B(x) | BIT_R_MU_TAB_SEL_8822B(v)) + +#define BIT_R_EN_MU_MIMO_8822B BIT(7) + +#define BITS_R_MU_TABLE_VALID_8822B (BIT_MASK_R_MU_TABLE_VALID_8822B << BIT_SHIFT_R_MU_TABLE_VALID_8822B) +#define BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) ((x) & (~BITS_R_MU_TABLE_VALID_8822B)) +#define BIT_SET_R_MU_TABLE_VALID_8822B(x, v) (BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) | BIT_R_MU_TABLE_VALID_8822B(v)) + +/* REG_WMAC_MU_BF_CTL (Offset 0x1680) */ +#define BITS_WMAC_MU_BFRPTSEG_SEL_8822B (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822B(x) ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8822B)) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8822B(x, v) (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822B(x) | BIT_WMAC_MU_BFRPTSEG_SEL_8822B(v)) + +#define BITS_WMAC_MU_BF_MYAID_8822B (BIT_MASK_WMAC_MU_BF_MYAID_8822B << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8822B(x) ((x) & (~BITS_WMAC_MU_BF_MYAID_8822B)) +#define BIT_SET_WMAC_MU_BF_MYAID_8822B(x, v) (BIT_CLEAR_WMAC_MU_BF_MYAID_8822B(x) | BIT_WMAC_MU_BF_MYAID_8822B(v)) + +/* REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ +#define BIT_STATUS_BFEE7_8822B BIT(10) + +enum _HW_CFG_SOUNDING_TYPE { + HW_CFG_SOUNDING_TYPE_SOUNDDOWN, + HW_CFG_SOUNDING_TYPE_LEAVE, + HW_CFG_SOUNDING_TYPE_RESET, + HW_CFG_SOUNDING_TYPE_MAX +}; - v32 = rtw_read32(adapter, 0x14c0); - /* Enable P1 aggr new packet according to P0 transfer time */ - v32 |= BIT(16); - /* MU Retry Limit */ - v32 = (v32 & 0xFFFF0FFF) | 0xA000; - /*Disable Tx MU-MIMO until sounding done*/ - v32 &= ~BIT(7); - /* Clear validity of MU STAs */ - v32 &= 0xFFFFFFC0; - rtw_write32(adapter, 0x14C0, v32); +static u8 _bf_get_nrx(PADAPTER adapter) +{ + u8 rf; + u8 nrx = 0; - /* MU-MIMO Option as default value */ - rtw_write8(adapter, 0x167C, 0x70); - /*MU-MIMO Control as default value*/ - rtw_write16(adapter, 0x1680, 0); - /* Set MU NDPA rate & BW source */ - /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ - v8 = rtw_read8(adapter, REG_TXBF_CTRL_8822B); - v8 |= BIT(6); - rtw_write8(adapter, REG_TXBF_CTRL_8822B, v8); - /* 0x45F[7:0] = 0x10 (Rate=OFDM_6M, BW20) */ - rtw_write8(adapter, REG_NDPA_OPT_CTRL_8822B, 0x10); + rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &rf); + switch (rf) { + case RF_1T1R: + nrx = 0; + break; + default: + case RF_1T2R: + case RF_2T2R: + nrx = 1; + break; + } - /* Temp Settings */ - /* STA2's CSI rate is fixed at 6M */ - v8 = rtw_read8(adapter, 0x6DF); - v8 = (v8 & 0xC0) | 0x4; - rtw_write8(adapter, 0x6DF, v8); - /* Grouping bitmap parameters */ - rtw_write32(adapter, 0x1C94, 0xAFFFAFFF); + return nrx; } -static void _setbeamformrfmode(PADAPTER adapter, u8 cnt_bfee_su, u8 cnt_bfee_mu, u8 idx) +static void _sounding_reset_all(PADAPTER adapter) { - BEAMFORMING_CAP bf_cap = BEAMFORMING_CAP_NONE; - - - if (GET_RF_TYPE(adapter) == RF_1T1R) - return; - - /* RF Mode table write enable */ - PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x1); - PHY_SetRFReg(adapter, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x1); - - if (cnt_bfee_su || cnt_bfee_mu) { - /* Path_A */ - /* Select RX mode */ - PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); - /* Set Table data */ - PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0xBE77F); - /* Enable TXIQGEN in RX mode */ - PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x226BF); - /* Path_B */ - /* Select RX mode */ - PHY_SetRFReg(adapter, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); - /* Set Table data */ - PHY_SetRFReg(adapter, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0xBE77F); - /* Enable TXIQGEN in RX mode */ - PHY_SetRFReg(adapter, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x226BF); - - /* Enable TXIQGEN in RX mode */ - PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); - } + struct beamforming_info *info; + struct beamformee_entry *bfee; + u8 i; + u32 mu_tx_ctl; - /* RF Mode table write disable */ - PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x0); - PHY_SetRFReg(adapter, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x0); - if (cnt_bfee_su) { - /* enable BB TxBF ant mapping register */ - PHY_SetBBReg(adapter, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28)|BIT(29), 0x2); + info = GET_BEAMFORM_INFO(adapter); - if (idx == 0) { - /* Nsts = 2, AB */ - PHY_SetBBReg(adapter, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433); - PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); - /*PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_2_8822B, bMaskLWord, 0x430);*/ + rtw_write8(adapter, REG_TXBF_CTRL_8822B+3, 0); - } else { /* idx = 1 */ - PHY_SetBBReg(adapter, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); - /*PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_2_8822B, bMaskLWord, 0x430;*/ - } - } else { - PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /* 1SS by path-A */ - PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_2_8822B, bMaskLWord, 0x430); /* 2SS by path-A,B */ + /* Clear all MU entry table */ + for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { + bfee = &info->bfee_entry[i]; + for (i = 0; i < 8; i++) + bfee->gid_valid[i] = 0; } - if (cnt_bfee_mu) { - /* MU STAs share the common setting */ - PHY_SetBBReg(adapter, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); - PHY_SetBBReg(adapter, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + mu_tx_ctl = rtw_read32(adapter, REG_MU_TX_CTL_8822B); + for (i = 0; i < 6; i++) { + mu_tx_ctl = BIT_SET_R_MU_TAB_SEL_8822B(mu_tx_ctl, i); + rtw_write32(adapter, REG_MU_TX_CTL_8822B, mu_tx_ctl); + /* set MU STA gid valid table */ + rtw_write32(adapter, REG_MU_STA_GID_VLD_8822B, 0); } + + /* Disable TxMU PPDU */ + mu_tx_ctl &= ~BIT_R_EN_MU_MIMO_8822B; + rtw_write32(adapter, REG_MU_TX_CTL_8822B, mu_tx_ctl); } -static u8 _get_txbf_nrx(PADAPTER adapter) +static void _sounding_config_su(PADAPTER adapter, struct beamformee_entry *bfee, enum _HW_CFG_SOUNDING_TYPE cfg_type) { - u8 rf; - u8 nrx = 0; + u32 txbf_ctrl, new_ctrl; - rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &rf); - switch (rf) { - case RF_1T1R: - nrx = 0; + txbf_ctrl = rtw_read32(adapter, REG_TXBF_CTRL_8822B); + new_ctrl = txbf_ctrl; + + /* Clear TxBF status at 20M/40/80M first */ + switch (bfee->su_reg_index) { + case 0: + new_ctrl &= ~(BIT_R_TXBF0_20M_8822B|BIT_R_TXBF0_40M_8822B|BIT_R_TXBF0_80M_8822B); + break; + case 1: + new_ctrl &= ~(BIT_R_TXBF1_20M_8822B|BIT_R_TXBF1_40M_8822B|BIT_R_TXBF1_80M_8822B); + break; + } + + switch (cfg_type) { + case HW_CFG_SOUNDING_TYPE_SOUNDDOWN: + switch (bfee->sound_bw) { + default: + case CHANNEL_WIDTH_80: + if (0 == bfee->su_reg_index) + new_ctrl |= BIT_R_TXBF0_80M_8822B; + else if (1 == bfee->su_reg_index) + new_ctrl |= BIT_R_TXBF1_80M_8822B; + /* fall through */ + case CHANNEL_WIDTH_40: + if (0 == bfee->su_reg_index) + new_ctrl |= BIT_R_TXBF0_40M_8822B; + else if (1 == bfee->su_reg_index) + new_ctrl |= BIT_R_TXBF1_40M_8822B; + /* fall through */ + case CHANNEL_WIDTH_20: + if (0 == bfee->su_reg_index) + new_ctrl |= BIT_R_TXBF0_20M_8822B; + else if (1 == bfee->su_reg_index) + new_ctrl |= BIT_R_TXBF1_20M_8822B; + break; + } break; + default: - case RF_1T2R: - case RF_2T2R: - nrx = 1; + RTW_INFO("%s: SU cfg_type=%d, don't apply Vmatrix!\n", __FUNCTION__, cfg_type); break; } - return nrx; + if (new_ctrl != txbf_ctrl) + rtw_write32(adapter, REG_TXBF_CTRL_8822B, new_ctrl); } -typedef enum _HW_CFG_SOUNDING_TYPE { - HW_CFG_SOUNDING_TYPE_SOUNDDOWN, - HW_CFG_SOUNDING_TYPE_LEAVE, - HW_CFG_SOUNDING_TYPE_RESET, - HW_CFG_SOUNDING_TYPE_MAX -} HW_CFG_SOUNDING_TYPE, *PHW_CFG_SOUNDING_TYPE; - -static void _config_sounding(PADAPTER adapter, struct beamformee_entry *entry, u8 mu_sounding, HW_CFG_SOUNDING_TYPE cfg_type) +static void _sounding_config_mu(PADAPTER adapter, struct beamformee_entry *bfee, enum _HW_CFG_SOUNDING_TYPE cfg_type) { - struct mlme_priv *mlme; - struct beamforming_info *bf_info; - u8 su_cnt, mu_cnt; - u16 BeamCtrlVal; - u32 BeamCtrlReg; + struct beamforming_info *info; u8 is_bitmap_ready = _FALSE; + u32 mu_tx_ctl; u16 bitmap; - u8 gid, i, j, count = 0; - u8 id1, id0; + u8 id1, id0, gid; u32 gid_valid[6] = {0}; + u8 i, j; u32 val32; - mlme = &adapter->mlmepriv; - bf_info = GET_BEAMFORM_INFO(adapter); - - if (cfg_type == HW_CFG_SOUNDING_TYPE_RESET) { - RTW_INFO("%s: HW_CFG_SOUNDING_TYPE_RESET\n", __FUNCTION__); + info = GET_BEAMFORM_INFO(adapter); - rtw_write8(adapter, REG_TXBF_CTRL_8822B+3, 0); + switch (cfg_type) { + case HW_CFG_SOUNDING_TYPE_LEAVE: + RTW_INFO("%s: MU HW_CFG_SOUNDING_TYPE_LEAVE\n", __FUNCTION__); - /* Clear all MU entry table */ - for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { - entry = &bf_info->bfee_entry[i]; + /* Clear the entry table */ + mu_tx_ctl = rtw_read32(adapter, REG_MU_TX_CTL_8822B); + if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU)) { for (i = 0; i < 8; i++) - entry->gid_valid[i] = 0; + bfee->gid_valid[i] = 0; + + mu_tx_ctl = BIT_SET_R_MU_TAB_SEL_8822B(mu_tx_ctl, bfee->mu_reg_index); + rtw_write32(adapter, REG_MU_TX_CTL_8822B, mu_tx_ctl); + /* Set MU STA gid valid table */ + rtw_write32(adapter, REG_MU_STA_GID_VLD_8822B, 0); + } else { + RTW_ERR("%s: ERROR! It is not an MU BFee entry!!\n", __FUNCTION__); } - val32 = rtw_read32(adapter, 0x14C0); - for (i = 0; i < 6; i++) { - val32 &= ~(BIT(8)|BIT(9)|BIT(10)); - val32 |= ((i<<8) & (BIT(8)|BIT(9)|BIT(10))); - rtw_write32(adapter, 0x14C0, val32); - /* set MU STA gid valid table */ - rtw_write32(adapter, 0x14C4, 0); + if (info->beamformee_su_cnt == 0) { + /* Disable TxMU PPDU */ + mu_tx_ctl &= ~BIT_R_EN_MU_MIMO_8822B; + rtw_write32(adapter, REG_MU_TX_CTL_8822B, mu_tx_ctl); } - /* Disable TxMU PPDU */ - val32 &= ~BIT(7); - rtw_write32(adapter, 0x14C0, val32); - } else { - if (_FALSE == mu_sounding) { - /* SU sounding */ - if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE) - || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE)) - BeamCtrlVal = entry->mac_id; - else - BeamCtrlVal = entry->p_aid; + break; - if (entry->su_reg_index == 0) { - BeamCtrlReg = REG_TXBF_CTRL_8822B; + case HW_CFG_SOUNDING_TYPE_SOUNDDOWN: + RTW_INFO("%s: MU HW_CFG_SOUNDING_TYPE_SOUNDDOWN\n", __FUNCTION__); + + /* Update all MU entry table */ + i = 0; + do { + /* Check BB GID bitmap ready */ + val32 = phy_query_bb_reg(adapter, 0xF4C, 0xFFFF0000); + + is_bitmap_ready = (val32 & BIT(15)) ? _TRUE : _FALSE; + i++; + rtw_udelay_os(5); + } while ((_FALSE == is_bitmap_ready) && (i < 100)); + + bitmap = (u16)(val32 & 0x3FFF); + + for (i = 0; i < 15; i++) { + if (i < 5) { + /* bit0~4 */ + id0 = 0; + id1 = i + 1; + } else if (i < 9) { + /* bit5~8 */ + id0 = 1; + id1 = i - 3; + } else if (i < 12) { + /* bit9~11 */ + id0 = 2; + id1 = i - 6; + } else if (i < 14) { + /* bit12~13 */ + id0 = 3; + id1 = i - 8; } else { - BeamCtrlReg = REG_TXBF_CTRL_8822B+2; - BeamCtrlVal |= ((BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B) >> 16); + /* bit14 */ + id0 = 4; + id1 = i - 9; } - - /* Current BFee sound down */ - if (entry->bDeleteSounding - || (cfg_type == HW_CFG_SOUNDING_TYPE_LEAVE)) { - RTW_INFO("%s: SU HW_CFG_SOUNDING_TYPE_LEAVE\n", __FUNCTION__); - RTW_INFO("%s: Don't apply Vmatrix\n", __FUNCTION__); - BeamCtrlVal &= ~(BIT(9)|BIT(10)|BIT(11)); + if (bitmap & BIT(i)) { + /* Pair 1 */ + gid = (i << 1) + 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + /* Pair 2 */ + gid += 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); } else { - if (entry->sound_bw == CHANNEL_WIDTH_20) - BeamCtrlVal |= BIT(9); - else if (entry->sound_bw == CHANNEL_WIDTH_40) - BeamCtrlVal |= (BIT(9)|BIT(10)); - else if (entry->sound_bw == CHANNEL_WIDTH_80) - BeamCtrlVal |= (BIT(9)|BIT(10)|BIT(11)); + /* Pair 1 */ + gid = (i << 1) + 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + /* Pair 2 */ + gid += 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); } + } - rtw_write16(adapter, BeamCtrlReg, BeamCtrlVal); - } else { - /* MU sounding */ - if (cfg_type == HW_CFG_SOUNDING_TYPE_LEAVE) { - RTW_INFO("%s: MU HW_CFG_SOUNDING_TYPE_LEAVE\n", __FUNCTION__); - - /* Clear the entry table */ - val32 = rtw_read32(adapter, 0x14C0); - if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_MU)) { - for (i = 0; i < 8; i++) - entry->gid_valid[i] = 0; - - val32 &= ~(BIT(8)|BIT(9)|BIT(10)); - val32 |= ((i<<8) & (BIT(8)|BIT(9)|BIT(10))); - rtw_write32(adapter, 0x14C0, val32); - /* Set MU STA gid valid table */ - rtw_write32(adapter, 0x14C4, 0); - } else { - RTW_ERR("%s: ERROR! It is not an MU BFee entry!!\n", __FUNCTION__); + for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { + bfee = &info->bfee_entry[i]; + if (_FALSE == bfee->used) + continue; + if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU) + && (bfee->mu_reg_index < 6)) { + val32 = gid_valid[bfee->mu_reg_index]; + for (j = 0; j < 4; j++) { + bfee->gid_valid[j] = (u8)(val32 & 0xFF); + val32 >>= 8; } + } + } - if (bf_info->beamformee_su_cnt == 0) { - /* Disable TxMU PPDU */ - val32 &= ~BIT(7); - rtw_write32(adapter, 0x14C0, val32); - } - } else if (cfg_type == HW_CFG_SOUNDING_TYPE_SOUNDDOWN) { - RTW_INFO("%s: MU HW_CFG_SOUNDING_TYPE_SOUNDDOWN\n", __FUNCTION__); - - /* Update all MU entry table */ - do { - /* Check BB GID bitmap ready */ - val32 = PHY_QueryBBReg(adapter, 0xF4C, 0xFFFF0000); - - is_bitmap_ready = (val32 & BIT(15)) ? _TRUE : _FALSE; - count++; - rtw_udelay_os(5); - } while ((_FALSE == is_bitmap_ready) && (count < 100)); - - bitmap = (u16)(val32 & 0x3FFF); - - for (i = 0; i < 15; i++) { - if (i < 5) {/*bit0~4*/ - id0 = 0; - id1 = (u8)(i + 1); - } else if (i < 9) { /*bit5~8*/ - id0 = 1; - id1 = (u8)(i - 3); - } else if (i < 12) { /*bit9~11*/ - id0 = 2; - id1 = (u8)(i - 6); - } else if (i < 14) { /*bit12~13*/ - id0 = 3; - id1 = (u8)(i - 8); - } else { /*bit14*/ - id0 = 4; - id1 = (u8)(i - 9); - } - if (bitmap & BIT(i)) { - /*Pair 1*/ - gid = (i << 1) + 1; - gid_valid[id0] |= (BIT(gid)); - gid_valid[id1] |= (BIT(gid)); - /*Pair 2*/ - gid += 1; - gid_valid[id0] |= (BIT(gid)); - gid_valid[id1] |= (BIT(gid)); - } else { - /*Pair 1*/ - gid = (i << 1) + 1; - gid_valid[id0] &= ~(BIT(gid)); - gid_valid[id1] &= ~(BIT(gid)); - /*Pair 2*/ - gid += 1; - gid_valid[id0] &= ~(BIT(gid)); - gid_valid[id1] &= ~(BIT(gid)); - } - } + mu_tx_ctl = rtw_read32(adapter, REG_MU_TX_CTL_8822B); + for (i = 0; i < 6; i++) { + mu_tx_ctl = BIT_SET_R_MU_TAB_SEL_8822B(mu_tx_ctl, i); + rtw_write32(adapter, REG_MU_TX_CTL_8822B, mu_tx_ctl); + /* Set MU STA gid valid table */ + rtw_write32(adapter, REG_MU_STA_GID_VLD_8822B, gid_valid[i]); + } - for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) { - entry = &bf_info->bfee_entry[i]; - if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_MU) - && (entry->mu_reg_index < 6)) { - val32 = gid_valid[entry->mu_reg_index]; - for (j = 0; j < 4; j++) { - entry->gid_valid[j] = (u8)(val32 & 0xFF); - val32 >>= 8; - } - } - } + /* Enable TxMU PPDU */ + mu_tx_ctl |= BIT_R_EN_MU_MIMO_8822B; + rtw_write32(adapter, REG_MU_TX_CTL_8822B, mu_tx_ctl); - val32 = rtw_read32(adapter, 0x14C0); - for (i = 0; i < 6; i++) { - val32 &= ~(BIT8|BIT9|BIT10); - val32 |= ((i<<8) & (BIT8|BIT9|BIT10)); - rtw_write32(adapter, 0x14C0, val32); - /* Set MU STA gid valid table */ - rtw_write32(adapter, 0x14C4, gid_valid[i]); - } + break; - /* Enable TxMU PPDU */ - val32 |= BIT(7); - rtw_write32(adapter, 0x14C0, val32); - } - } + default: + break; + } +} + +static void _config_sounding(PADAPTER adapter, struct beamformee_entry *bfee, u8 mu_sounding, enum _HW_CFG_SOUNDING_TYPE cfg_type) +{ + if (cfg_type == HW_CFG_SOUNDING_TYPE_RESET) { + RTW_INFO("%s: HW_CFG_SOUNDING_TYPE_RESET\n", __FUNCTION__); + _sounding_reset_all(adapter); + return; + } + + if (_FALSE == mu_sounding) + _sounding_config_su(adapter, bfee, cfg_type); + else + _sounding_config_mu(adapter, bfee, cfg_type); +} + +static void _config_beamformer_su(PADAPTER adapter, struct beamformer_entry *bfer) +{ + /* Beamforming */ + u8 nc_index = 0, nr_index = 0; + u8 grouping = 0, codebookinfo = 0, coefficientsize = 0; + u32 addr_bfer_info, addr_csi_rpt; + u32 csi_param; + /* Misc */ + u8 i; + + + RTW_INFO("%s: Config SU BFer entry HW setting\n", __FUNCTION__); + + if (bfer->su_reg_index == 0) { + addr_bfer_info = REG_ASSOCIATED_BFMER0_INFO_8822B; + addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20_8822B; + } else { + addr_bfer_info = REG_ASSOCIATED_BFMER1_INFO_8822B; + addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20_8822B + 2; } + + /* Sounding protocol control */ + rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B, 0xDB); + + /* MAC address/Partial AID of Beamformer */ + for (i = 0; i < 6; i++) + rtw_write8(adapter, addr_bfer_info+i, bfer->mac_addr[i]); + + /* CSI report parameters of Beamformer */ + nc_index = _bf_get_nrx(adapter); + /* + * 0x718[7] = 1 use Nsts + * 0x718[7] = 0 use reg setting + * As Bfee, we use Nsts, so nr_index don't care + */ + nr_index = bfer->NumofSoundingDim; + grouping = 0; + /* for ac = 1, for n = 3 */ + if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU)) + codebookinfo = 1; + else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_HT_EXPLICIT)) + codebookinfo = 3; + coefficientsize = 3; + csi_param = (u16)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(nr_index<<3)|(nc_index)); + rtw_write16(adapter, addr_csi_rpt, csi_param); + RTW_INFO("%s: nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n", + __FUNCTION__, nc_index, nr_index, grouping, codebookinfo, coefficientsize); + RTW_INFO("%s: csi=0x%04x\n", __FUNCTION__, csi_param); + + /* ndp_rx_standby_timer */ + rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B+3, 0x70); } -void rtl8822b_phy_sounding_enter(PADAPTER adapter, struct sta_info *sta) +static void _config_beamformer_mu(PADAPTER adapter, struct beamformer_entry *bfer) { + /* General */ PHAL_DATA_TYPE hal; - struct mlme_priv *mlme; + /* Beamforming */ struct beamforming_info *bf_info; - struct beamformer_entry *bfer; - struct beamformee_entry *bfee; - u8 cnt_bfee_su = 0, cnt_bfee_mu = 0; - u8 i = 0, idx; + u8 nc_index = 0, nr_index = 0; + u8 grouping = 0, codebookinfo = 0, coefficientsize = 0; u32 csi_param; - u16 p_aid = 0; - /* MU */ - u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; - u32 gid_valid = 0, user_position_l = 0, user_position_h = 0; - u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168A, 0x168C, 0x168E}; + /* Misc */ + u8 i, val8; + u16 val16; + + RTW_INFO("%s: Config MU BFer entry HW setting\n", __FUNCTION__); + + hal = GET_HAL_DATA(adapter); + bf_info = GET_BEAMFORM_INFO(adapter); + + /* Reset GID table */ + for (i = 0; i < 8; i++) + bfer->gid_valid[i] = 0; + for (i = 0; i < 16; i++) + bfer->user_position[i] = 0; + + /* CSI report parameters of Beamformer */ + nc_index = _bf_get_nrx(adapter); + nr_index = 1; /* 0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care */ + grouping = 0; /* no grouping */ + codebookinfo = 1; /* 7 bit for psi, 9 bit for phi */ + coefficientsize = 0; /* This is nothing really matter */ + csi_param = (u16)((coefficientsize<<10)|(codebookinfo<<8)| + (grouping<<6)|(nr_index<<3)|(nc_index)); + + RTW_INFO("%s: nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n", + __func__, nc_index, nr_index, grouping, codebookinfo, + coefficientsize); + RTW_INFO("%s: csi=0x%04x\n", __func__, csi_param); + + rtw_halmac_bf_add_mu_bfer(adapter_to_dvobj(adapter), bfer->p_aid, + csi_param, bfer->aid & 0xfff, HAL_CSI_SEG_4K, + bfer->mac_addr); + + bf_info->cur_csi_rpt_rate = HALMAC_OFDM54; + rtw_halmac_bf_cfg_sounding(adapter_to_dvobj(adapter), HAL_BFEE, + bf_info->cur_csi_rpt_rate); + + /* Set 0x6A0[14] = 1 to accept action_no_ack */ + val8 = rtw_read8(adapter, REG_RXFLTMAP0_8822B+1); + val8 |= (BIT_MGTFLT14EN_8822B >> 8); + rtw_write8(adapter, REG_RXFLTMAP0_8822B+1, val8); + + /* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */ + val8 = rtw_read8(adapter, REG_RXFLTMAP1_8822B); + val8 |= BIT_CTRLFLT4EN_8822B | BIT_CTRLFLT5EN_8822B; + rtw_write8(adapter, REG_RXFLTMAP1_8822B, val8); + + /* for B-Cut */ + if (IS_B_CUT(hal->version_id)) { + phy_set_bb_reg(adapter, REG_RXFLTMAP0_8822B, BIT(20), 0); + phy_set_bb_reg(adapter, REG_RXFLTMAP3_8822B, BIT(20), 0); + } +} + +static void _config_beamformee_su(PADAPTER adapter, struct beamformee_entry *bfee) +{ /* General */ + struct mlme_priv *mlme; + /* Beamforming */ + struct beamforming_info *info; + u8 idx; + u16 p_aid = 0; + /* Misc */ u8 val8; u16 val16; u32 val32; - RTW_INFO("+%s\n", __FUNCTION__); + RTW_INFO("%s: Config SU BFee entry HW setting\n", __FUNCTION__); - hal = GET_HAL_DATA(adapter); mlme = &adapter->mlmepriv; - bf_info = GET_BEAMFORM_INFO(adapter); + info = GET_BEAMFORM_INFO(adapter); + idx = bfee->su_reg_index; - bfee = beamforming_get_bfee_entry_by_addr(adapter, sta->hwaddr); - bfer = beamforming_get_bfer_entry_by_addr(adapter, sta->hwaddr); + if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE) + || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE)) + p_aid = bfee->mac_id; + else + p_aid = bfee->p_aid; - if (bfer) { - bfer->state = BEAMFORM_ENTRY_HW_STATE_ADDING; + phydm_8822btxbf_rfmode(GET_PDM_ODM(adapter), info->beamformee_su_cnt, info->beamformee_mu_cnt); - if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_MU)) { - /* Config MU BFer entry */ - RTW_INFO("%s: Config MU BFer entry HW setting\n", __FUNCTION__); + /* P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt */ + val32 = rtw_read32(adapter, REG_TXBF_CTRL_8822B); + if (idx == 0) { + val32 = BIT_SET_R_TXBF0_AID_8822B(val32, p_aid); + val32 &= ~(BIT_R_TXBF0_20M_8822B | BIT_R_TXBF0_40M_8822B | BIT_R_TXBF0_80M_8822B); + } else { + val32 = BIT_SET_R_TXBF1_AID_8822B(val32, p_aid); + val32 &= ~(BIT_R_TXBF1_20M_8822B | BIT_R_TXBF1_40M_8822B | BIT_R_TXBF1_80M_8822B); + } + val32 |= BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B; + rtw_write32(adapter, REG_TXBF_CTRL_8822B, val32); + + /* CSI report parameters of Beamformee */ + val32 = rtw_read32(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B); + if (idx == 0) { + val32 = BIT_SET_AID0_8822B(val32, p_aid); + val32 |= BIT_TXUSER_ID0_8822B; + + /* unknown? */ + val32 &= 0x03FFFFFF; + val32 |= 0x60000000; + } else { + val32 = BIT_SET_AID1_8822B(val32, p_aid); + val32 |= BIT_TXUSER_ID1_8822B; - /* Reset GID table */ - for (i = 0; i < 8; i++) - bfer->gid_valid[i] = 0; - for (i = 0; i < 16; i++) - bfer->user_position[i] = 0; + /* unknown? */ + val32 &= 0x03FFFFFF; + val32 |= 0xE0000000; + } + rtw_write32(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B, val32); +} - /* Sounding protocol control */ - rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B, 0xDB); +static void _config_beamformee_mu(PADAPTER adapter, struct beamformee_entry *bfee) +{ + /* General */ + PHAL_DATA_TYPE hal; + /* Beamforming */ + struct beamforming_info *info; + u8 idx; + u32 gid_valid = 0, user_position_l = 0, user_position_h = 0; + u32 mu_reg[6] = {REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B, + REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B, + REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B, + REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B, + REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B, + REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B}; + /* Misc */ + u8 i, val8; + u16 val16; + u32 val32; - /* MAC address */ - for (i = 0; i < ETH_ALEN; i++) - rtw_write8(adapter, REG_ASSOCIATED_BFMER0_INFO_8822B+i, bfer->mac_addr[i]); - /* Set partial AID */ - rtw_write16(adapter, REG_ASSOCIATED_BFMER0_INFO_8822B+6, bfer->p_aid); + RTW_INFO("%s: Config MU BFee entry HW setting\n", __FUNCTION__); - /* - * Fill our AID to 0x1680[11:0] and - * [13:12] = 2b'00, BF report segement select to 3895 bytes - */ - val16 = rtw_read16(adapter, 0x1680); - val16 &= ~0x3FFF; - val16 |= (bfer->aid & 0xFFF); - rtw_write16(adapter, 0x1680, val16); - - /* Set 80us for leaving ndp_rx_standby_state */ - rtw_write8(adapter, 0x71B, 0x50); - - /* Set 0x6A0[14] = 1 to accept action_no_ack */ - val8 = rtw_read8(adapter, REG_RXFLTMAP0_8822B+1); - val8 |= 0x40; - rtw_write8(adapter, REG_RXFLTMAP0_8822B+1, val8); - - /* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */ - val8 = rtw_read8(adapter, REG_RXFLTMAP1_8822B); - val8 |= 0x30; - rtw_write8(adapter, REG_RXFLTMAP1_8822B, val8); - - /* CSI report parameters of Beamformer */ - nc_index = _get_txbf_nrx(adapter); - /* - * 0x718[7] = 1 use Nsts - * 0x718[7] = 0 use reg setting - * As Bfee, we use Nsts, so nr_index don't care - */ - nr_index = 1; - grouping = 0; /* no grouping */ - codebookinfo = 1; /* 7 bit for psi, 9 bit for phi */ - coefficientsize = 0; /* This is nothing really matter */ - csi_param = (u16)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(nr_index<<3)|(nc_index)); - rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param); - RTW_INFO("%s: nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n", - __FUNCTION__, nc_index, nr_index, grouping, codebookinfo, coefficientsize); - RTW_INFO("%s: csi=0x%04x\n", __FUNCTION__, csi_param); - - /*for B-Cut*/ - PHY_SetBBReg(adapter, REG_RXFLTMAP0_8822B, BIT(20), 0); - PHY_SetBBReg(adapter, REG_RXFLTMAP3_8822B, BIT(20), 0); - } else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) { - /* Config SU BFer entry */ - RTW_INFO("%s: Config SU BFer entry HW setting.\n", __FUNCTION__); - - /* Sounding protocol control */ - rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B, 0xDB); - - /* MAC address/Partial AID of Beamformer */ - if (bfer->su_reg_index == 0) - for (i = 0; i < 6; i++) - rtw_write8(adapter, (REG_ASSOCIATED_BFMER0_INFO_8822B+i), bfer->mac_addr[i]); - else - for (i = 0; i < 6; i++) - rtw_write8(adapter, (REG_ASSOCIATED_BFMER1_INFO_8822B+i), bfer->mac_addr[i]); + hal = GET_HAL_DATA(adapter); + info = GET_BEAMFORM_INFO(adapter); + idx = bfee->mu_reg_index; + + /* User position table */ + switch (idx) { + case 0: + gid_valid = 0x7fe; + user_position_l = 0x111110; + user_position_h = 0x0; + break; + case 1: + gid_valid = 0x7f806; + user_position_l = 0x11000004; + user_position_h = 0x11; + break; + case 2: + gid_valid = 0x1f81818; + user_position_l = 0x400040; + user_position_h = 0x11100; + break; + case 3: + gid_valid = 0x1e186060; + user_position_l = 0x4000400; + user_position_h = 0x1100040; + break; + case 4: + gid_valid = 0x66618180; + user_position_l = 0x40004000; + user_position_h = 0x10040400; + break; + case 5: + gid_valid = 0x79860600; + user_position_l = 0x40000; + user_position_h = 0x4404004; + break; + } - /* CSI report parameters of Beamformer */ - nc_index = _get_txbf_nrx(adapter); - /* - * 0x718[7] = 1 use Nsts - * 0x718[7] = 0 use reg setting - * As Bfee, we use Nsts, so nr_index don't care - */ - nr_index = bfer->NumofSoundingDim; + for (i = 0; i < 8; i++) { + if (i < 4) { + bfee->gid_valid[i] = (u8)(gid_valid & 0xFF); + gid_valid >>= 8; + } else { + bfee->gid_valid[i] = 0; + } + } + for (i = 0; i < 16; i++) { + if (i < 4) + bfee->user_position[i] = (u8)((user_position_l >> (i*8)) & 0xFF); + else if (i < 8) + bfee->user_position[i] = (u8)((user_position_h >> ((i-4)*8)) & 0xFF); + else + bfee->user_position[i] = 0; + } - grouping = 0; + /* Sounding protocol control */ + rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B, 0xDB); - /* for ac = 1, for n = 3 */ - if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU)) - codebookinfo = 1; - else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_HT_EXPLICIT)) - codebookinfo = 3; + /* select MU STA table */ + val32 = rtw_read32(adapter, REG_MU_TX_CTL_8822B); + val32 = BIT_SET_R_MU_TAB_SEL_8822B(val32, idx); + rtw_write32(adapter, REG_MU_TX_CTL_8822B, val32); - coefficientsize = 3; + /* Reset gid_valid table */ + rtw_write32(adapter, REG_MU_STA_GID_VLD_8822B, 0); + rtw_write32(adapter, REG_MU_STA_USER_POS_INFO_8822B , user_position_l); + rtw_write32(adapter, REG_MU_STA_USER_POS_INFO_8822B+4 , user_position_h); - csi_param = (u16)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(nr_index<<3)|(nc_index)); + /* set validity of MU STAs */ + val32 = BIT_SET_R_MU_TABLE_VALID_8822B(val32, info->beamformee_mu_reg_maping); + rtw_write32(adapter, REG_MU_TX_CTL_8822B, val32); - if (bfer->su_reg_index == 0) - rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param); - else - rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B+2, csi_param); - /* ndp_rx_standby_timer */ - rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B+3, 0x70); - } + RTW_INFO("%s: RegMUTxCtrl=0x%x, user_position_l=0x%x, user_position_h=0x%x\n", + __FUNCTION__, val32, user_position_l, user_position_h); - bfer->state = BEAMFORM_ENTRY_HW_STATE_ADDED; + val16 = rtw_read16(adapter, mu_reg[idx]); + val16 &= 0xFE00; /* Clear PAID */ + val16 |= BIT(9); /* Enable MU BFee */ + val16 |= bfee->p_aid; + rtw_write16(adapter, mu_reg[idx], val16); + RTW_INFO("%s: Write mu_reg 0x%x = 0x%x\n", + __FUNCTION__, mu_reg[idx], val16); + + /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ + val8 = rtw_read8(adapter, REG_TXBF_CTRL_8822B+3); + val8 |= 0xD0; /* Set bit 28, 30, 31 to 3b'111 */ + rtw_write8(adapter, REG_TXBF_CTRL_8822B+3, val8); + + /* Set NDPA rate*/ + val8 = phydm_get_ndpa_rate(GET_PDM_ODM(adapter)); + rtw_write8(adapter, REG_NDPA_RATE_8822B, val8); + + val8 = rtw_read8(adapter, REG_NDPA_OPT_CTRL_8822B); + val8 = BIT_SET_R_NDPA_BW_8822B(val8, 0); /* Clear bit 0, 1 */ + rtw_write8(adapter, REG_NDPA_OPT_CTRL_8822B, val8); + + val32 = rtw_read32(adapter, REG_SND_PTCL_CTRL_8822B); + val32 = (val32 & 0xFF0000FF) | 0x020200; /* Set [23:8] to 0x0202 */ + rtw_write32(adapter, REG_SND_PTCL_CTRL_8822B, val32); + + /* Set 0x6A0[14] = 1 to accept action_no_ack */ + val8 = rtw_read8(adapter, REG_RXFLTMAP0_8822B+1); + val8 |= (BIT_MGTFLT14EN_8822B >> 8); + rtw_write8(adapter, REG_RXFLTMAP0_8822B+1, val8); + + /* 0x718[15] = 1. Patch for STA2 CSI report start offset error issue for C-cut and later version */ + if (!IS_A_CUT(hal->version_id) || !IS_B_CUT(hal->version_id)) { + val8 = rtw_read8(adapter, REG_SND_PTCL_CTRL_8822B+1); + val8 |= (BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8822B >> 8); + rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B+1, val8); } - if (bfee) { - bfee->state = BEAMFORM_ENTRY_HW_STATE_ADDING; + /* End of MAC registers setting */ - if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU)) { - idx = bfee->mu_reg_index; - /* User position table */ - switch (idx) { - case 0: - gid_valid = 0x7fe; - user_position_l = 0x111110; - user_position_h = 0x0; - break; - case 1: - gid_valid = 0x7f806; - user_position_l = 0x11000004; - user_position_h = 0x11; - break; - case 2: - gid_valid = 0x1f81818; - user_position_l = 0x400040; - user_position_h = 0x11100; - break; - case 3: - gid_valid = 0x1e186060; - user_position_l = 0x4000400; - user_position_h = 0x1100040; - break; - case 4: - gid_valid = 0x66618180; - user_position_l = 0x40004000; - user_position_h = 0x10040400; - break; - case 5: - gid_valid = 0x79860600; - user_position_l = 0x40000; - user_position_h = 0x4404004; - break; - } + phydm_8822btxbf_rfmode(GET_PDM_ODM(adapter), info->beamformee_su_cnt, info->beamformee_mu_cnt); - for (i = 0; i < 8; i++) { - if (i < 4) { - bfee->gid_valid[i] = (u8)(gid_valid & 0xFF); - gid_valid = (gid_valid >> 8); - } else - bfee->gid_valid[i] = 0; - } - for (i = 0; i < 16; i++) { - if (i < 4) - bfee->user_position[i] = (u8)((user_position_l >> (i*8)) & 0xFF); - else if (i < 8) - bfee->user_position[i] = (u8)((user_position_h >> ((i-4)*8)) & 0xFF); - else - bfee->user_position[i] = 0; - } + /* Need to set timer 2015.12.23 */ + /* Special for plugfest */ + rtw_mdelay_os(50); /* wait for 4-way handshake ending */ + rtw_bf_send_vht_gid_mgnt_packet(adapter, bfee->mac_addr, bfee->gid_valid, bfee->user_position); +} - /* Sounding protocol control */ - rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B, 0xDB); - - /* select MU STA table */ - val32 = rtw_read32(adapter, 0x14C0); - val32 &= ~(BIT(8)|BIT(9)|BIT(10)); - val32 |= (idx << 8) & (BIT(8)|BIT(9)|BIT(10)); - rtw_write32(adapter, 0x14C0, val32); - - /* Reset gid_valid table */ - rtw_write32(adapter, 0x14C4, 0); - rtw_write32(adapter, 0x14C8 , user_position_l); - rtw_write32(adapter, 0x14CC , user_position_h); - - /* set validity of MU STAs */ - val32 &= 0xFFFFFFC0; - val32 |= bf_info->beamformee_mu_reg_maping & 0x3F; - rtw_write32(adapter, 0x14C0, val32); - - RTW_INFO("%s: RegMUTxCtrl=0x%x, user_position_l=0x%x, user_position_h=0x%x\n", - __FUNCTION__, val32, user_position_l, user_position_h); - - val16 = rtw_read16(adapter, mu_reg[idx]); - val16 &= 0xFE00; /* Clear PAID */ - val16 |= BIT(9); /* Enable MU BFee */ - val16 |= bfee->p_aid; - rtw_write16(adapter, mu_reg[idx], val16); - RTW_INFO("%s: Write mu_reg 0x%x = 0x%x\n", - __FUNCTION__, mu_reg[idx], val16); - - /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ - val8 = rtw_read8(adapter, REG_TXBF_CTRL_8822B+3); - val8 |= 0xD0; /* Set bit 28, 30, 31 to 3b'111 */ - rtw_write8(adapter, REG_TXBF_CTRL_8822B+3, val8); - /* Set NDPA to 6M*/ - rtw_write8(adapter, REG_NDPA_RATE_8822B, 0x4); /* 6M */ - - val8 = rtw_read8(adapter, REG_NDPA_OPT_CTRL_8822B); - val8 &= 0xFC; /* Clear bit 0, 1 */ - rtw_write8(adapter, REG_NDPA_OPT_CTRL_8822B, val8); - - val32 = rtw_read32(adapter, REG_SND_PTCL_CTRL_8822B); - val32 = ((val32 & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202 */ - rtw_write32(adapter, REG_SND_PTCL_CTRL_8822B, val32); - - /* Set 0x6A0[14] = 1 to accept action_no_ack */ - val8 = rtw_read8(adapter, REG_RXFLTMAP0_8822B+1); - val8 |= 0x40; - rtw_write8(adapter, REG_RXFLTMAP0_8822B+1, val8); - /* End of MAC registers setting */ - - _setbeamformrfmode(adapter, bf_info->beamformee_su_cnt, bf_info->beamformee_mu_cnt, 0); - - /* Need to set timer 2015.12.23 */ - /* Special for plugfest */ - rtw_mdelay_os(50); /* wait for 4-way handshake ending */ - beamforming_send_vht_gid_mgnt_packet(adapter, bfee); - -#if 1 /* Fix rate. Do we need to keep this action? */ - /* Set Ctrl Info */ - rtw_write16(adapter, 0x140, 0x660); - - /* Reset Ctrl Info */ - val32 = 0x8000 + 32 * bfee->mac_id; - for (i = 0; i < 8; i++) - rtw_write32(adapter, val32 + i*4, 0); +static void _reset_beamformer_su(PADAPTER adapter, struct beamformer_entry *bfer) +{ + /* Beamforming */ + struct beamforming_info *info; + u8 idx; - rtw_write32(adapter, val32, (idx + 1) << 16); - rtw_write8(adapter, 0x81, 0x80); /* RPTBUF ready */ - RTW_INFO("%s: mac_id=%d, ctrl_info_offset=0x%x, mu_reg_index=%x\n", - __FUNCTION__, bfee->mac_id, val32, idx); -#endif - } else if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) { - RTW_INFO("%s: Config SU BFee entry HW setting\n", __FUNCTION__); + info = GET_BEAMFORM_INFO(adapter); + /* SU BFer */ + idx = bfer->su_reg_index; - idx = bfee->su_reg_index; + if (idx == 0) { + rtw_write32(adapter, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); + rtw_write16(adapter, REG_ASSOCIATED_BFMER0_INFO_8822B+4, 0); + rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0); + } else { + rtw_write32(adapter, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); + rtw_write16(adapter, REG_ASSOCIATED_BFMER1_INFO_8822B+4, 0); + rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B+2, 0); + } - if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE) - || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE)) - p_aid = bfee->mac_id; - else - p_aid = bfee->p_aid; + info->beamformer_su_reg_maping &= ~BIT(idx); + bfer->su_reg_index = 0xFF; - _setbeamformrfmode(adapter, bf_info->beamformee_su_cnt, bf_info->beamformee_mu_cnt, idx); + RTW_INFO("%s: Clear SU BFer entry(%d) HW setting\n", __FUNCTION__, idx); +} - /* P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt */ - if (idx == 0) { - rtw_write16(adapter, REG_TXBF_CTRL_8822B, p_aid); - val8 = rtw_read8(adapter, REG_TXBF_CTRL_8822B+3); - val8 |= ((BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B) >> 24); - rtw_write8(adapter, REG_TXBF_CTRL_8822B+3, val8); - } else { - val16 = p_aid; - val16 |= ((BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B) >> 16); - rtw_write16(adapter, REG_TXBF_CTRL_8822B+2, val16); - } +static void _reset_beamformer_mu(PADAPTER adapter, struct beamformer_entry *bfer) +{ + struct beamforming_info *bf_info; - /* CSI report parameters of Beamformee */ - if (idx == 0) { - /* Get BIT24 & BIT(25)=BIT_TXUSER_ID1_8822B */ - val8 = rtw_read8(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B+3) & 0x3; - val8 |= 0x60; - rtw_write8(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B+3, val8); + bf_info = GET_BEAMFORM_INFO(adapter); - val16 = p_aid | BIT_TXUSER_ID0_8822B; - rtw_write16(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B, val16); - } else { - /* Set BIT(25)=BIT_TXUSER_ID1_8822B */ - val16 = p_aid | 0xE200; - rtw_write16(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B+2, val16); - } - } + rtw_halmac_bf_del_mu_bfer(adapter_to_dvobj(adapter)); - bfee->state = BEAMFORM_ENTRY_HW_STATE_ADDED; + if (bf_info->beamformer_su_cnt == 0 && + bf_info->beamformer_mu_cnt == 0) + rtw_halmac_bf_del_sounding(adapter_to_dvobj(adapter), HAL_BFEE); + + RTW_INFO("%s: Clear MU BFer entry HW setting\n", __FUNCTION__); +} + +static void _reset_beamformee_su(PADAPTER adapter, struct beamformee_entry *bfee) +{ + /* Beamforming */ + struct beamforming_info *info; + u8 idx; + /* Misc */ + u32 txbf_ctrl, bfmee_sel; + + + info = GET_BEAMFORM_INFO(adapter); + /* SU BFee */ + idx = bfee->su_reg_index; + + /* Force disable sounding config */ + _config_sounding(adapter, bfee, _FALSE, HW_CFG_SOUNDING_TYPE_LEAVE); + + /* clear P_AID */ + txbf_ctrl = rtw_read32(adapter, REG_TXBF_CTRL_8822B); + bfmee_sel = rtw_read32(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B); + if (idx == 0) { + txbf_ctrl = BIT_SET_R_TXBF0_AID_8822B(txbf_ctrl, 0); + txbf_ctrl &= ~(BIT_R_TXBF0_20M_8822B | BIT_R_TXBF0_40M_8822B | BIT_R_TXBF0_80M_8822B); + + bfmee_sel = BIT_SET_AID0_8822B(bfmee_sel, 0); + bfmee_sel &= ~BIT_TXUSER_ID0_8822B; + } else { + txbf_ctrl = BIT_SET_R_TXBF1_AID_8822B(txbf_ctrl, 0); + txbf_ctrl &= ~(BIT_R_TXBF1_20M_8822B | BIT_R_TXBF1_40M_8822B | BIT_R_TXBF1_80M_8822B); + + bfmee_sel = BIT_SET_AID1_8822B(bfmee_sel, 0); + bfmee_sel &= ~BIT_TXUSER_ID1_8822B; } + txbf_ctrl |= BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B; + rtw_write32(adapter, REG_TXBF_CTRL_8822B, txbf_ctrl); + rtw_write32(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B, bfmee_sel); - RTW_INFO("-%s\n", __FUNCTION__); + info->beamformee_su_reg_maping &= ~BIT(idx); + bfee->su_reg_index = 0xFF; + + RTW_INFO("%s: Clear SU BFee entry(%d) HW setting\n", __FUNCTION__, idx); } -void rtl8822b_phy_sounding_leave(PADAPTER adapter, u8 *addr) +static void _reset_beamformee_mu(PADAPTER adapter, struct beamformee_entry *bfee) { - PHAL_DATA_TYPE hal; - struct beamforming_info *bf_info; - struct beamformer_entry *bfer_entry; - struct beamformee_entry *bfee_entry; - u8 cnt_bfee_su = 0, cnt_bfee_mu = 0; - u8 i = 0, idx; - u16 p_aid = 0; - /* MU */ - u32 gid_valid, user_position_l, user_position_h; - u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; - /* General */ - u8 val8; - u16 val16; + /* Beamforming */ + struct beamforming_info *info; + u8 idx; + u32 mu_reg[6] = {REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B, + REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B, + REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B, + REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B, + REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B, + REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B}; + /* Misc */ + u32 val32; + + + info = GET_BEAMFORM_INFO(adapter); + /* MU BFee */ + idx = bfee->mu_reg_index; + + /* Disable sending NDPA & BF-rpt-poll to this BFee */ + rtw_write16(adapter, mu_reg[idx] , 0); + /* Set validity of MU STA */ + val32 = rtw_read32(adapter, REG_MU_TX_CTL_8822B); + val32 &= ~BIT(idx); + rtw_write32(adapter, REG_MU_TX_CTL_8822B, val32); + + /* Force disable sounding config */ + _config_sounding(adapter, bfee, _TRUE, HW_CFG_SOUNDING_TYPE_LEAVE); + + info->beamformee_mu_reg_maping &= ~BIT(idx); + bfee->mu_reg_index = 0xFF; + + RTW_INFO("%s: Clear MU BFee entry(%d) HW setting\n", __FUNCTION__, idx); +} + +void rtl8822b_phy_bf_reset_all(PADAPTER adapter) +{ + struct beamforming_info *info; + u8 i, val8; u32 val32; RTW_INFO("+%s\n", __FUNCTION__); + info = GET_BEAMFORM_INFO(adapter); - hal = GET_HAL_DATA(adapter); - bf_info = GET_BEAMFORM_INFO(adapter); + info->bSetBFHwConfigInProgess = _TRUE; - bfee_entry = beamforming_get_bfee_entry_by_addr(adapter, addr); - bfer_entry = beamforming_get_bfer_entry_by_addr(adapter, addr); + /* Reset MU BFer entry setting */ + /* Clear validity of MU STA0 and MU STA1 */ + val32 = rtw_read32(adapter, REG_MU_TX_CTL_8822B); + val32 = BIT_SET_R_MU_TABLE_VALID_8822B(val32, 0); + rtw_write32(adapter, REG_MU_TX_CTL_8822B, val32); - /* Clear P_AID of Beamformee */ - /* Clear MAC address of Beamformer */ - /* Clear Associated Bfmee Sel */ - if (bfer_entry) { - bfer_entry->state = BEAMFORM_ENTRY_HW_STATE_DELETING; + /* Reset SU BFer entry setting */ + rtw_write32(adapter, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); + rtw_write16(adapter, REG_ASSOCIATED_BFMER0_INFO_8822B+4, 0); + rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0); - rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B, 0xD8); + rtw_write32(adapter, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); + rtw_write16(adapter, REG_ASSOCIATED_BFMER1_INFO_8822B+4, 0); + rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B+2, 0); - if (TEST_FLAG(bfer_entry->cap, BEAMFORMER_CAP_VHT_MU)) { - /* MU BFer entry */ - /* Clear validity of MU STA0 and MU STA1*/ - val32 = rtw_read32(adapter, 0x14C0); - val32 &= 0xFFFFFFC0; - rtw_write32(adapter, 0x14C0, val32); - - RTW_INFO("%s: Clear MU BFer entry HW setting\n", __FUNCTION__); - } else if (TEST_FLAG(bfer_entry->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) { - /* SU BFer entry */ - idx = bfer_entry->su_reg_index; - if (idx == 0) { - rtw_write32(adapter, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); - rtw_write16(adapter, REG_ASSOCIATED_BFMER0_INFO_8822B+4, 0); - rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0); - } else { - rtw_write32(adapter, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); - rtw_write16(adapter, REG_ASSOCIATED_BFMER1_INFO_8822B+4, 0); - rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B+2, 0); - } + /* Force disable sounding */ + _config_sounding(adapter, NULL, _FALSE, HW_CFG_SOUNDING_TYPE_RESET); - bf_info->beamformer_su_reg_maping &= ~BIT(idx); - bfer_entry->su_reg_index = 0xFF; + /* Config RF mode */ + phydm_8822btxbf_rfmode(GET_PDM_ODM(adapter), info->beamformee_su_cnt, info->beamformee_mu_cnt); - RTW_INFO("%s: Clear SU BFer entry HW setting\n", __FUNCTION__); - } + /* Reset MU BFee entry setting */ + + /* Disable sending NDPA & BF-rpt-poll to all BFee */ + for (i=0; i < MAX_NUM_BEAMFORMEE_MU; i++) + rtw_write16(adapter, REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B+(i*2), 0); + + /* set validity of MU STA */ + rtw_write32(adapter, REG_MU_TX_CTL_8822B, 0); + + /* Reset SU BFee entry setting */ + /* SU BF0 and BF1 */ + val32 = BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B; + rtw_write32(adapter, REG_TXBF_CTRL_8822B, val32); + rtw_write32(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B, 0); - bfer_entry->used = _FALSE; - bfer_entry->state = BEAMFORM_ENTRY_HW_STATE_NONE; - bfer_entry->cap = BEAMFORMING_CAP_NONE; + info->bSetBFHwConfigInProgess = _FALSE; + + /* Clear SU TxBF workaround BB registers */ + if (_TRUE == info->bEnableSUTxBFWorkAround) + rtl8822b_phy_bf_set_csi_report(adapter, &info->TargetCSIInfo); + + RTW_INFO("-%s\n", __FUNCTION__); +} + +void rtl8822b_phy_bf_init(PADAPTER adapter) +{ + u8 v8; + u32 v32; + + v32 = rtw_read32(adapter, REG_MU_TX_CTL_8822B); + /* Enable P1 aggr new packet according to P0 transfer time */ + v32 |= BIT_R_MU_P1_WAIT_STATE_EN_8822B; + /* MU Retry Limit */ + v32 = BIT_SET_R_MU_RL_8822B(v32, 0xA); + /* Disable Tx MU-MIMO until sounding done */ + v32 &= ~BIT_R_EN_MU_MIMO_8822B; + /* Clear validity of MU STAs */ + v32 = BIT_SET_R_MU_TABLE_VALID_8822B(v32, 0); + rtw_write32(adapter, REG_MU_TX_CTL_8822B, v32); + + /* MU-MIMO Option as default value */ + v8 = BIT_WMAC_TXMU_ACKPOLICY_8822B(3); + v8 |= BIT_BIT_WMAC_TXMU_ACKPOLICY_EN_8822B; + rtw_write8(adapter, REG_WMAC_MU_BF_OPTION_8822B, v8); + /* MU-MIMO Control as default value */ + rtw_write16(adapter, REG_WMAC_MU_BF_CTL_8822B, 0); + + /* Set MU NDPA rate & BW source */ + /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ + v8 = rtw_read8(adapter, REG_TXBF_CTRL_8822B+3); + v8 |= (BIT_USE_NDPA_PARAMETER_8822B >> 24); + rtw_write8(adapter, REG_TXBF_CTRL_8822B+3, v8); + /* 0x45F[7:0] = 0x10 (Rate=OFDM_6M, BW20) */ + rtw_write8(adapter, REG_NDPA_OPT_CTRL_8822B, 0x10); + + /* Temp Settings */ + /* STA2's CSI rate is fixed at 6M */ + v8 = rtw_read8(adapter, 0x6DF); + v8 = (v8 & 0xC0) | 0x4; + rtw_write8(adapter, 0x6DF, v8); + /* Grouping bitmap parameters */ + rtw_write32(adapter, 0x1C94, 0xAFFFAFFF); +} + +void rtl8822b_phy_bf_enter(PADAPTER adapter, struct sta_info *sta) +{ + struct beamforming_info *info; + struct beamformer_entry *bfer; + struct beamformee_entry *bfee; + + + RTW_INFO("+%s: " MAC_FMT "\n", __FUNCTION__, MAC_ARG(sta->hwaddr)); + + info = GET_BEAMFORM_INFO(adapter); + bfer = rtw_bf_bfer_get_entry_by_addr(adapter, sta->hwaddr); + bfee = rtw_bf_bfee_get_entry_by_addr(adapter, sta->hwaddr); + + info->bSetBFHwConfigInProgess = _TRUE; + + if (bfer) { + bfer->state = BEAMFORM_ENTRY_HW_STATE_ADDING; + + if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_MU)) + _config_beamformer_mu(adapter, bfer); + else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) + _config_beamformer_su(adapter, bfer); + + bfer->state = BEAMFORM_ENTRY_HW_STATE_ADDED; } - if (bfee_entry) { - bfee_entry->state = BEAMFORM_ENTRY_HW_STATE_DELETING; + if (bfee) { + bfee->state = BEAMFORM_ENTRY_HW_STATE_ADDING; - _setbeamformrfmode(adapter, bf_info->beamformee_su_cnt, bf_info->beamformee_mu_cnt, bfee_entry->su_reg_index); + if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU)) + _config_beamformee_mu(adapter, bfee); + else if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) + _config_beamformee_su(adapter, bfee); - if (TEST_FLAG(bfee_entry->cap, BEAMFORMER_CAP_VHT_MU)) { - /*MU BFee */ - idx = bfee_entry->mu_reg_index; + bfee->state = BEAMFORM_ENTRY_HW_STATE_ADDED; + } - /* Disable sending NDPA & BF-rpt-poll to this BFee */ - rtw_write16(adapter, mu_reg[idx] , 0); - /* Set validity of MU STA */ - val32 = rtw_read32(adapter, 0x14C0); - val32 &= ~(BIT(idx)); - rtw_write32(adapter, 0x14C0, val32); + info->bSetBFHwConfigInProgess = _FALSE; - /* Force disable sounding config */ - _config_sounding(adapter, bfee_entry, _TRUE, HW_CFG_SOUNDING_TYPE_LEAVE); + RTW_INFO("-%s\n", __FUNCTION__); +} - bf_info->beamformee_mu_reg_maping &= ~BIT(idx); - bfee_entry->mu_reg_index = 0xFF; +void rtl8822b_phy_bf_leave(PADAPTER adapter, u8 *addr) +{ + struct beamforming_info *info; + struct beamformer_entry *bfer; + struct beamformee_entry *bfee; - RTW_INFO("%s: Clear MU BFee entry HW setting\n", __FUNCTION__); - } else if (TEST_FLAG(bfee_entry->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) { - /* SU BFee */ - idx = bfee_entry->su_reg_index; - if (idx == 0) { - rtw_write16(adapter, REG_TXBF_CTRL_8822B, 0x0); - val8 = rtw_read8(adapter, REG_TXBF_CTRL_8822B+3); - val8 |= ((BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B) >> 24); - rtw_write8(adapter, REG_TXBF_CTRL_8822B+3, val8); - rtw_write16(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B, 0); - } else { - val16 = 0x0; - val16 |= ((BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B) >> 16); - rtw_write16(adapter, REG_TXBF_CTRL_8822B+2, val16); + RTW_INFO("+%s: " MAC_FMT "\n", __FUNCTION__, MAC_ARG(addr)); - val16 = rtw_read16(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B+2); - val16 &= 0x60; - rtw_write16(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B+2, val16); - } + info = GET_BEAMFORM_INFO(adapter); - /* Force disable sounding config */ - _config_sounding(adapter, bfee_entry, _FALSE, HW_CFG_SOUNDING_TYPE_LEAVE); + bfer = rtw_bf_bfer_get_entry_by_addr(adapter, addr); + bfee = rtw_bf_bfee_get_entry_by_addr(adapter, addr); - bf_info->beamformee_su_reg_maping &= ~BIT(idx); - bfee_entry->su_reg_index = 0xFF; + /* Clear P_AID of Beamformee */ + /* Clear MAC address of Beamformer */ + /* Clear Associated Bfmee Sel */ + if (bfer) { + bfer->state = BEAMFORM_ENTRY_HW_STATE_DELETING; - RTW_INFO("%s: Clear SU BFee entry HW setting\n", __FUNCTION__); - } + rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B, 0xD8); + + if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_MU)) + _reset_beamformer_mu(adapter, bfer); + else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) + _reset_beamformer_su(adapter, bfer); + + bfer->state = BEAMFORM_ENTRY_HW_STATE_NONE; + bfer->cap = BEAMFORMING_CAP_NONE; + bfer->used = _FALSE; + } + + if (bfee) { + bfee->state = BEAMFORM_ENTRY_HW_STATE_DELETING; + + phydm_8822btxbf_rfmode(GET_PDM_ODM(adapter), info->beamformee_su_cnt, info->beamformee_mu_cnt); + + if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU)) + _reset_beamformee_mu(adapter, bfee); + else if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) + _reset_beamformee_su(adapter, bfee); + + bfee->state = BEAMFORM_ENTRY_HW_STATE_NONE; + bfee->cap = BEAMFORMING_CAP_NONE; + bfee->used = _FALSE; } RTW_INFO("-%s\n", __FUNCTION__); } -void rtl8822b_phy_sounding_set_gid_table(PADAPTER adapter, struct beamformer_entry *bfer) +void rtl8822b_phy_bf_set_gid_table(PADAPTER adapter, + struct beamformer_entry *bfer_info) { - struct beamforming_info *bf_info; - u32 beamctrlreg; - u16 beamctrlval; - /* MU */ - u32 gid_valid, user_position_l, user_position_h; - u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; - /* General */ - u8 val8; - u16 val16; - u32 val32; + struct beamformer_entry *bfer; + struct beamforming_info *info; + u32 gid_valid[2] = {0}; + u32 user_position[4] = {0}; int i; + /* update bfer info */ + bfer = rtw_bf_bfer_get_entry_by_addr(adapter, bfer_info->mac_addr); + if (!bfer) { + RTW_INFO("%s: Cannot find BFer entry!!\n", __func__); + return; + } + _rtw_memcpy(bfer->gid_valid, bfer_info->gid_valid, 8); + _rtw_memcpy(bfer->user_position, bfer_info->user_position, 16); - bf_info = GET_BEAMFORM_INFO(adapter); + info = GET_BEAMFORM_INFO(adapter); + info->bSetBFHwConfigInProgess = _TRUE; /* For GID 0~31 */ - gid_valid = 0; - user_position_l = 0; - user_position_h = 0; for (i = 0; i < 4; i++) - gid_valid |= (bfer->gid_valid[i] << (i << 3)); + gid_valid[0] |= (bfer->gid_valid[i] << (i << 3)); + for (i = 0; i < 8; i++) { if (i < 4) - user_position_l |= (bfer->user_position[i] << (i << 3)); + user_position[0] |= (bfer->user_position[i] << (i << 3)); else - user_position_h |= (bfer->user_position[i] << ((i - 4) << 3)); + user_position[1] |= (bfer->user_position[i] << ((i - 4) << 3)); } - /* select MU STA0 table */ - val32 = rtw_read32(adapter, 0x14C0); - val32 &= ~(BIT(8)|BIT(9)|BIT(10)); - rtw_write32(adapter, 0x14C0, val32); - rtw_write32(adapter, 0x14C4, gid_valid); - rtw_write32(adapter, 0x14C8, user_position_l); - rtw_write32(adapter, 0x14CC, user_position_h); RTW_INFO("%s: STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n", - __FUNCTION__, gid_valid, user_position_l, user_position_h); + __func__, gid_valid[0], user_position[0], user_position[1]); /* For GID 32~64 */ - gid_valid = 0; - user_position_l = 0; - user_position_h = 0; for (i = 4; i < 8; i++) - gid_valid |= (bfer->gid_valid[i] << ((i - 4)<<3)); + gid_valid[1] |= (bfer->gid_valid[i] << ((i - 4) << 3)); + for (i = 8; i < 16; i++) { if (i < 12) - user_position_l |= (bfer->user_position[i] << ((i - 8) << 3)); + user_position[2] |= (bfer->user_position[i] << ((i - 8) << 3)); else - user_position_h |= (bfer->user_position[i] << ((i - 12) << 3)); + user_position[3] |= (bfer->user_position[i] << ((i - 12) << 3)); } - /* select MU STA1 table */ - val32 = rtw_read32(adapter, 0x14C0); - val32 &= ~(BIT(8)|BIT(9)|BIT(10)); - val32 |= BIT(8); - rtw_write32(adapter, 0x14C0, val32); - rtw_write32(adapter, 0x14C4, gid_valid); - rtw_write32(adapter, 0x14C8, user_position_l); - rtw_write32(adapter, 0x14CC, user_position_h); - + RTW_INFO("%s: STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n", - __FUNCTION__, gid_valid, user_position_l, user_position_h); + __func__, gid_valid[1], user_position[2], user_position[3]); + + rtw_halmac_bf_cfg_mu_bfee(adapter_to_dvobj(adapter), gid_valid, user_position); + + info->bSetBFHwConfigInProgess = _FALSE; +} + +void rtl8822b_phy_bf_set_csi_report(PADAPTER adapter, struct _RT_CSI_INFO *csi) +{ + PHAL_DATA_TYPE hal; + struct beamforming_info *info; + BOOLEAN enable_su = FALSE; - /* Set validity of MU STA0 and MU STA1 */ - val32 = rtw_read32(adapter, 0x14C0); - val32 &= 0xFFFFFFC0; - val32 |= 0x3; /* STA0, STA1 */ - rtw_write32(adapter, 0x14C0, val32); + + hal = GET_HAL_DATA(adapter); + info = GET_BEAMFORM_INFO(adapter); + + info->bSetBFHwConfigInProgess = _TRUE; + + if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id) || IS_C_CUT(hal->version_id)) { + /* If there is an MU BFee added then discard the SU BFee supported capability */ + if ((info->beamformee_su_cnt > 0) && (info->beamformee_mu_cnt == 0)) + enable_su = TRUE; + + phydm_8822b_sutxbfer_workaroud( + GET_PDM_ODM(adapter), + enable_su, + csi->Nc, + csi->Nr, + csi->Ng, + csi->CodeBook, + csi->ChnlWidth, + csi->bVHT); + + RTW_INFO("%s: bEnable=%d, Nc=%d, Nr=%d, CH_W=%d, Ng=%d, CodeBook=%d\n", + __FUNCTION__, bEnable, + csi->Nc, csi->Nr, csi->ChnlWidth, csi->Ng, csi->CodeBook); + } + + info->bSetBFHwConfigInProgess = _FALSE; +} + +void rtl8822b_phy_bf_sounding_status(PADAPTER adapter, u8 status) +{ + struct beamforming_info *info; + struct sounding_info *sounding; + struct beamformee_entry *bfee; + enum _HW_CFG_SOUNDING_TYPE sounding_type; + u16 val16; + u32 val32; + u8 is_sounding_success[6] = {0}; + + + RTW_INFO("+%s\n", __FUNCTION__); + + info = GET_BEAMFORM_INFO(adapter); + sounding = &info->sounding_info; + + info->bSetBFHwConfigInProgess = _TRUE; + + if (sounding->state == SOUNDING_STATE_SU_SOUNDDOWN) { + /* SU sounding done */ + RTW_INFO("%s: SUBFeeCurIdx=%d\n", __FUNCTION__, sounding->su_bfee_curidx); + + bfee = &info->bfee_entry[sounding->su_bfee_curidx]; + if (bfee->bSoundingTimeout) { + RTW_INFO("%s: Return because SUBFeeCurIdx(%d) is sounding timeout!!!\n", __FUNCTION__, sounding->su_bfee_curidx); + info->bSetBFHwConfigInProgess = _FALSE; + return; + } + + RTW_INFO("%s: Config SU sound down HW settings\n", __FUNCTION__); + /* Config SU sounding */ + if (_TRUE == status) + sounding_type = HW_CFG_SOUNDING_TYPE_SOUNDDOWN; + else + sounding_type = HW_CFG_SOUNDING_TYPE_LEAVE; + _config_sounding(adapter, bfee, _FALSE, sounding_type); + + /* Why set here? */ + /* disable NDP packet use beamforming */ + val16 = rtw_read16(adapter, REG_TXBF_CTRL_8822B); + val16 |= BIT_DIS_NDP_BFEN_8822B; + rtw_write16(adapter, REG_TXBF_CTRL_8822B, val16); + } else if (sounding->state == SOUNDING_STATE_MU_SOUNDDOWN) { + /* MU sounding done */ + RTW_INFO("%s: Config MU sound down HW settings\n", __FUNCTION__); + + val32 = rtw_read32(adapter, REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B); + is_sounding_success[0] = (val32 & BIT_STATUS_BFEE2_8822B) ? 1:0; + is_sounding_success[1] = ((val32 >> 16) & BIT_STATUS_BFEE3_8822B) ? 1:0; + val32 = rtw_read32(adapter, REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B); + is_sounding_success[2] = (val32 & BIT_STATUS_BFEE4_8822B) ? 1:0; + is_sounding_success[3] = ((val32 >> 16) & BIT_STATUS_BFEE5_8822B) ? 1:0; + val32 = rtw_read32(adapter, REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B); + is_sounding_success[4] = (val32 & BIT_STATUS_BFEE6_8822B) ? 1:0; + is_sounding_success[5] = ((val32 >> 16) & BIT_STATUS_BFEE7_8822B) ? 1:0; + + RTW_INFO("%s: is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n", + __FUNCTION__, is_sounding_success[0], is_sounding_success[1] , is_sounding_success[2], + is_sounding_success[3], is_sounding_success[4], is_sounding_success[5]); + + /* Config MU sounding */ + _config_sounding(adapter, NULL, _TRUE, HW_CFG_SOUNDING_TYPE_SOUNDDOWN); + } else { + RTW_INFO("%s: Invalid sounding state(%d). Do nothing!\n", __FUNCTION__, sounding->state); + } + + info->bSetBFHwConfigInProgess = _FALSE; + + RTW_INFO("-%s\n", __FUNCTION__); } #endif /* CONFIG_BEAMFORMING */ diff --git a/hal/rtl8822b/usb/rtl8822bu.h b/hal/rtl8822b/usb/rtl8822bu.h index 493bf4a..f8d0858 100644 --- a/hal/rtl8822b/usb/rtl8822bu.h +++ b/hal/rtl8822b/usb/rtl8822bu.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8822BU_H_ #define _RTL8822BU_H_ @@ -24,6 +19,12 @@ #define USB_AGG_EN_8822B BIT(7) +#ifdef CONFIG_LPS_LCLK +/* for CONFIG_LPS_LCLK setting in rtl8822bu_ops.c */ +#define REG_USB_HRPWM_8822B 0xFE58 +#define REG_USB_HCPWM_8822B 0xFE57 +#endif /* CONFIG_LPS_LCLK */ + /* rtl8822bu_halinit.c */ u32 rtl8822bu_init(PADAPTER); u32 rtl8822bu_deinit(PADAPTER); @@ -50,6 +51,9 @@ s32 rtl8822bu_mgnt_xmit(PADAPTER, struct xmit_frame *); s32 rtl8822bu_hal_xmit(PADAPTER, struct xmit_frame *); s32 rtl8822bu_hal_xmitframe_enqueue(PADAPTER, struct xmit_frame *); s32 rtl8822bu_hostap_mgnt_xmit_entry(PADAPTER, _pkt *); +#ifdef CONFIG_XMIT_THREAD_MODE +s32 rtl8822bu_xmit_buf_handler(PADAPTER); +#endif /* CONFIG_XMIT_THREAD_MODE */ /* rtl8822bu_recv.c */ int rtl8822bu_init_recv_priv(PADAPTER); diff --git a/hal/rtl8822b/usb/rtl8822bu_halinit.c b/hal/rtl8822b/usb/rtl8822bu_halinit.c index edab64d..5711127 100644 --- a/hal/rtl8822b/usb/rtl8822bu_halinit.c +++ b/hal/rtl8822b/usb/rtl8822bu_halinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8822BU_HALINIT_C_ #include /* HAL DATA */ @@ -44,11 +39,164 @@ static void _dbg_dump_macreg(PADAPTER padapter) } } +#ifdef CONFIG_FWLPS_IN_IPS +u8 rtl8822bu_fw_ips_init(_adapter *padapter) +{ + struct sreset_priv *psrtpriv = &GET_HAL_DATA(padapter)->srestpriv; + struct debug_priv *pdbgpriv = &adapter_to_dvobj(padapter)->drv_dbg; + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + + if (pwrctl->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE + && GET_HAL_DATA(padapter)->bFWReady == _TRUE && pwrctl->pre_ips_type == 0) { + u32 start_time; + u8 cpwm_orig, cpwm_now, rpwm; + u8 bMacPwrCtrlOn = _TRUE; + + RTW_INFO("%s: Leaving FW_IPS\n", __func__); +#ifdef CONFIG_LPS_LCLK + /* for polling cpwm */ + cpwm_orig = 0; + rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig); + + /* set rpwm */ + rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &rpwm); + rpwm += 0x80; + rpwm |= PS_ACK; + rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm)); + + + RTW_INFO("%s: write rpwm=%02x\n", __func__, rpwm); + + pwrctl->tog = (rpwm + 0x80) & 0x80; + + /* do polling cpwm */ + start_time = rtw_get_current_time(); + do { + + rtw_mdelay_os(1); + + rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now); + if ((cpwm_orig ^ cpwm_now) & 0x80) { + #ifdef DBG_CHECK_FW_PS_STATE + RTW_INFO("%s: polling cpwm ok when leaving IPS in FWLPS state, cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x\n" + , __func__, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR)); + #endif /* DBG_CHECK_FW_PS_STATE */ + break; + } + + if (rtw_get_passing_time_ms(start_time) > 100) { + RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state, cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x\n", + __func__, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR)); + break; + } + } while (1); +#endif /* CONFIG_LPS_LCLK */ + rtl8822b_set_FwPwrModeInIPS_cmd(padapter, 0); + + rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); +#ifdef CONFIG_LPS_LCLK + #ifdef DBG_CHECK_FW_PS_STATE + if (rtw_fw_ps_state(padapter) == _FAIL) { + RTW_INFO("after hal init, fw ps state in 32k\n"); + pdbgpriv->dbg_ips_drvopen_fail_cnt++; + } + #endif /* DBG_CHECK_FW_PS_STATE */ +#endif /* CONFIG_LPS_LCLK */ + return _SUCCESS; + } + return _FAIL; +} + +u8 rtl8822bu_fw_ips_deinit(_adapter *padapter) +{ + struct sreset_priv *psrtpriv = &GET_HAL_DATA(padapter)->srestpriv; + struct debug_priv *pdbgpriv = &adapter_to_dvobj(padapter)->drv_dbg; + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + + if (pwrctl->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE + && GET_HAL_DATA(padapter)->bFWReady == _TRUE && padapter->netif_up == _TRUE) { + int cnt = 0; + u8 val8 = 0, rpwm; + + RTW_INFO("%s: issue H2C to FW when entering IPS\n", __func__); + + rtl8822b_set_FwPwrModeInIPS_cmd(padapter, 0x1); +#ifdef CONFIG_LPS_LCLK + /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */ + do { + val8 = rtw_read8(padapter, REG_HMETFR); + cnt++; + RTW_INFO("%s polling REG_HMETFR=0x%x, cnt=%d\n", __func__, val8, cnt); + rtw_mdelay_os(10); + } while (cnt < 100 && (val8 != 0)); + + /* H2C done, enter 32k */ + if (val8 == 0) { + /* set rpwm to enter 32k */ + rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &rpwm); + rpwm += 0x80; + rpwm |= BIT_SYS_CLK_8822B; + rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm)); + RTW_INFO("%s: write rpwm=%02x\n", __func__, rpwm); + pwrctl->tog = (val8 + 0x80) & 0x80; + + cnt = val8 = 0; + do { + val8 = rtw_read8(padapter, REG_CR); + cnt++; + RTW_INFO("%s polling 0x100=0x%x, cnt=%d\n", __func__, val8, cnt); + rtw_mdelay_os(10); + } while (cnt < 100 && (val8 != 0xEA)); + + #ifdef DBG_CHECK_FW_PS_STATE + if (val8 != 0xEA) + RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n" + , rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4) + , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, REG_HMETFR)); + #endif /* DBG_CHECK_FW_PS_STATE */ + } else { + RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n" + , rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4) + , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, REG_HMETFR)); + } + + RTW_INFO("polling done when entering IPS, check result : 0x100=0x%x, cnt=%d, MAC_1cc=0x%02x\n" + , rtw_read8(padapter, REG_CR), cnt, rtw_read8(padapter, REG_HMETFR)); + + pwrctl->pre_ips_type = 0; +#endif /* CONFIG_LPS_LCLK */ + return _SUCCESS; + } + + pdbgpriv->dbg_carddisable_cnt++; + pwrctl->pre_ips_type = 1; + + return _FAIL; + +} + +#endif + +static void hal_init_misc(PADAPTER padapter) +{ + if (padapter->registrypriv.wifi_spec) { + padapter->registrypriv.adaptivity_en = 1; + padapter->registrypriv.adaptivity_mode = 0; + } +} + u32 rtl8822bu_init(PADAPTER padapter) { u8 status = _SUCCESS; u32 init_start_time = rtw_get_current_time(); +#ifdef CONFIG_FWLPS_IN_IPS + if (_SUCCESS == rtl8822bu_fw_ips_init(padapter)) + goto exit; +#endif + + hal_init_misc(padapter); + rtl8822b_init(padapter); exit: @@ -71,6 +219,10 @@ u32 rtl8822bu_deinit(PADAPTER padapter) RTW_INFO("==> %s\n", __func__); +#ifdef CONFIG_FWLPS_IN_IPS + if (_SUCCESS == rtl8822bu_fw_ips_deinit(padapter)) + goto exit; +#endif hal_deinit_misc(padapter); status = rtl8822b_deinit(padapter); @@ -79,6 +231,7 @@ u32 rtl8822bu_deinit(PADAPTER padapter) return _FAIL; } +exit: RTW_INFO("%s <==\n", __func__); return _SUCCESS; } @@ -97,13 +250,20 @@ u32 rtl8822bu_inirp_init(PADAPTER padapter) u32(*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr); #endif - _func_enter_; +#ifdef CONFIG_FWLPS_IN_IPS + /* Do not sumbit urb repeat */ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + + if (pwrctl->bips_processing == _TRUE) { + status = _SUCCESS; + goto exit; + } +#endif /* CONFIG_FWLPS_IN_IPS */ _read_port = pintfhdl->io_ops._read_port; status = _SUCCESS; - RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("===> usb_inirp_init\n")); precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR; @@ -111,7 +271,6 @@ u32 rtl8822bu_inirp_init(PADAPTER padapter) precvbuf = (struct recv_buf *)precvpriv->precv_buf; for (i = 0; i < NR_RECVBUFF; i++) { if (_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (u8 *)precvbuf) == _FALSE) { - RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("usb_rx_init: usb_read_port error\n")); status = _FAIL; goto exit; } @@ -128,16 +287,13 @@ u32 rtl8822bu_inirp_init(PADAPTER padapter) } _read_interrupt = pintfhdl->io_ops._read_interrupt; if (_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE) { - RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("usb_rx_init: usb_read_interrupt error\n")); status = _FAIL; } #endif exit: - RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<=== usb_inirp_init\n")); - _func_exit_; return status; @@ -145,11 +301,9 @@ u32 rtl8822bu_inirp_init(PADAPTER padapter) u32 rtl8822bu_inirp_deinit(PADAPTER padapter) { - RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n ===> usb_rx_deinit\n")); rtw_read_port_cancel(padapter); - RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n <=== usb_rx_deinit\n")); return _SUCCESS; } @@ -254,12 +408,14 @@ void rtl8822bu_interface_configure(PADAPTER padapter) #ifdef CONFIG_USB_RX_AGGREGATION /* according to value defined by halmac */ pHalData->rxagg_mode = RX_AGG_USB; -#if 0 - pHalData->rxagg_usb_size = 8; - pHalData->rxagg_usb_timeout = 0x6; - pHalData->rxagg_dma_size = 16; - pHalData->rxagg_dma_timeout = 0x6; -#endif +#ifdef CONFIG_PLATFORM_NOVATEK_NT72668 + pHalData->rxagg_usb_size = 0x03; + pHalData->rxagg_usb_timeout = 0x20; +#elif defined(CONFIG_PLATFORM_HISILICON) + /* use 16k to workaround for HISILICON platform */ + pHalData->rxagg_usb_size = 3; + pHalData->rxagg_usb_timeout = 8; +#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */ #endif /* CONFIG_USB_RX_AGGREGATION */ usb_set_queue_pipe_mapping(padapter, diff --git a/hal/rtl8822b/usb/rtl8822bu_halmac.c b/hal/rtl8822b/usb/rtl8822bu_halmac.c index fa98a37..2941487 100644 --- a/hal/rtl8822b/usb/rtl8822bu_halmac.c +++ b/hal/rtl8822b/usb/rtl8822bu_halmac.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,21 +11,183 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8822BU_HALMAC_C_ #include /* struct dvobj_priv and etc. */ #include "../../hal_halmac.h" +#include "../rtl8822b.h" /* rtl8822b_cal_txdesc_chksum() */ -static u8 usb_write_data_rsvd_page(void *d, u8 *pBuf, u32 size) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) +#define usb_write_port_complete_not_xmitframe(purb, regs) usb_write_port_complete_not_xmitframe(purb) +#endif +static void usb_write_port_complete_not_xmitframe(struct urb *purb, struct pt_regs *regs) +{ + + if (purb->status == 0) { + ; + } else { + RTW_INFO("###=> urb_write_port_complete status(%d)\n", purb->status); + if ((purb->status == -EPIPE) || (purb->status == -EPROTO)) { + ; + } else if (purb->status == -EINPROGRESS) { + goto check_completion; + + } else if (purb->status == -ENOENT) { + RTW_INFO("%s: -ENOENT\n", __func__); + goto check_completion; + + } else if (purb->status == -ECONNRESET) { + RTW_INFO("%s: -ECONNRESET\n", __func__); + goto check_completion; + + } else if (purb->status == -ESHUTDOWN) { + RTW_INFO("%s: -ESHUTDOWN\n", __func__); + goto check_completion; + } else { + goto check_completion; + } + } + +check_completion: + rtw_mfree(purb->transfer_buffer, purb->transfer_buffer_length); + usb_free_urb(purb); +} + +static u32 usb_write_port_not_xmitframe(struct dvobj_priv *d, u8 addr, u32 cnt, u8 *wmem) { struct dvobj_priv *pobj = (struct dvobj_priv *)d; - PADAPTER padapter = pobj->padapters[IFACE_ID0]; + PADAPTER padapter = dvobj_get_primary_adapter(pobj); + unsigned int pipe; + int status; + u32 ret = _FAIL, bwritezero = _FALSE; + PURB purb = NULL; + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + struct usb_device *pusbd = pdvobj->pusbdev; + + + purb = usb_alloc_urb(0, GFP_KERNEL); + if (purb == NULL) { + RTW_ERR("purb == NULL\n"); + return _FAIL; + } + + /* translate DMA FIFO addr to pipehandle */ + pipe = ffaddr2pipehdl(pdvobj, addr); + + + usb_fill_bulk_urb(purb, pusbd, pipe, + wmem, + cnt, + usb_write_port_complete_not_xmitframe, + padapter); + + +#ifdef USB_PACKET_OFFSET_SZ +#if (USB_PACKET_OFFSET_SZ == 0) + purb->transfer_flags |= URB_ZERO_PACKET; +#endif +#endif + +#if 0 + if (bwritezero) + purb->transfer_flags |= URB_ZERO_PACKET; +#endif + + status = usb_submit_urb(purb, GFP_ATOMIC); + if (!status) { + #ifdef DBG_CONFIG_ERROR_DETECT + { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + pHalData->srestpriv.last_tx_time = rtw_get_current_time(); + } + #endif + } else { + RTW_INFO("usb_write_port, status=%d\n", status); + + switch (status) { + case -ENODEV: + break; + default: + break; + } + goto exit; + } + + ret = _SUCCESS; + +exit: + if (ret != _SUCCESS) + usb_free_urb(purb); + + return ret; +} + +static u8 usb_write_data_not_xmitframe(void *d, u8 *pBuf, u32 size, u8 qsel) +{ + struct dvobj_priv *pobj = (struct dvobj_priv *)d; + PADAPTER padapter = dvobj_get_primary_adapter(pobj); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + u32 desclen, len; + u8 *buf; + u8 ret; + u8 addr; + u8 add_pkt_offset = 0; + + + + halmac = dvobj_to_halmac((struct dvobj_priv *)d); + api = HALMAC_GET_API(halmac); + + desclen = HALMAC_TX_DESC_SIZE_8822B; + len = desclen + size; + + if (len % pHalData->UsbBulkOutSize == 0) + add_pkt_offset = 1; + + if (add_pkt_offset == 1) + len = len + PACKET_OFFSET_SZ; + + buf = rtw_zmalloc(len); + if (!buf) + return _FALSE; + + if (add_pkt_offset == 1) + _rtw_memcpy(buf + desclen + PACKET_OFFSET_SZ , pBuf, size); + else + _rtw_memcpy(buf + desclen, pBuf, size); + + SET_TX_DESC_TXPKTSIZE_8822B(buf, size); + if (add_pkt_offset == 1) { + SET_TX_DESC_OFFSET_8822B(buf, desclen + PACKET_OFFSET_SZ); + SET_TX_DESC_PKT_OFFSET_8822B(buf, 1); + } else + SET_TX_DESC_OFFSET_8822B(buf, desclen); + + SET_TX_DESC_QSEL_8822B(buf, qsel); + rtl8822b_cal_txdesc_chksum(padapter, buf); + + addr = rtw_halmac_usb_get_bulkout_id(d, buf, len); + ret = usb_write_port_not_xmitframe(d, addr, len , buf); + if (_SUCCESS == ret) { + ret = _TRUE; + } else { + RTW_ERR("%s , rtl8822bu_simple_write_port fail\n", __func__); + rtw_mfree(buf , len); + ret = _FALSE; + } + + return ret; + +} + +static u8 usb_write_data_rsvd_page_normal(void *d, u8 *pBuf, u32 size) +{ + struct dvobj_priv *pobj = (struct dvobj_priv *)d; + PADAPTER padapter = dvobj_get_primary_adapter(pobj); PHALMAC_ADAPTER halmac = dvobj_to_halmac((struct dvobj_priv *)d); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct xmit_frame *pcmdframe = NULL; @@ -54,7 +216,7 @@ static u8 usb_write_data_rsvd_page(void *d, u8 *pBuf, u32 size) /* update attribute */ pattrib = &pcmdframe->attrib; update_mgntframe_attrib(padapter, pattrib); - pattrib->qsel = QSLT_BEACON; + pattrib->qsel = HALMAC_TXDESC_QSEL_BEACON; pattrib->pktlen = size; pattrib->last_txcmdsz = size; @@ -64,10 +226,10 @@ static u8 usb_write_data_rsvd_page(void *d, u8 *pBuf, u32 size) return _TRUE; } -static u8 usb_write_data_h2c(void *d, u8 *pBuf, u32 size) +static u8 usb_write_data_h2c_normal(void *d, u8 *pBuf, u32 size) { struct dvobj_priv *pobj = (struct dvobj_priv *)d; - PADAPTER padapter = pobj->padapters[IFACE_ID0]; + PADAPTER padapter = dvobj_get_primary_adapter(pobj); PHALMAC_ADAPTER halmac = dvobj_to_halmac((struct dvobj_priv *)d); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct xmit_frame *pcmdframe = NULL; @@ -107,6 +269,31 @@ static u8 usb_write_data_h2c(void *d, u8 *pBuf, u32 size) } + +static u8 usb_write_data_rsvd_page(void *d, u8 *pBuf, u32 size) +{ + struct dvobj_priv *pobj = (struct dvobj_priv *)d; + PADAPTER padapter = dvobj_get_primary_adapter(pobj); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (pHalData->not_xmitframe_fw_dl) + return usb_write_data_not_xmitframe(d , pBuf , size, HALMAC_TXDESC_QSEL_BEACON); + else + return usb_write_data_rsvd_page_normal(d , pBuf , size); +} + +static u8 usb_write_data_h2c(void *d, u8 *pBuf, u32 size) +{ + struct dvobj_priv *pobj = (struct dvobj_priv *)d; + PADAPTER padapter = dvobj_get_primary_adapter(pobj); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (pHalData->not_xmitframe_fw_dl) + return usb_write_data_not_xmitframe(d , pBuf , size, HALMAC_TXDESC_QSEL_H2C_CMD); + else + return usb_write_data_h2c_normal(d , pBuf , size); +} + int rtl8822bu_halmac_init_adapter(PADAPTER padapter) { struct dvobj_priv *d; diff --git a/hal/rtl8822b/usb/rtl8822bu_io.c b/hal/rtl8822b/usb/rtl8822bu_io.c index cdc872d..63584f8 100644 --- a/hal/rtl8822b/usb/rtl8822bu_io.c +++ b/hal/rtl8822b/usb/rtl8822bu_io.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,19 +11,13 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8822BU_IO_C_ #include /* PADAPTER and etc. */ void rtl8822bu_set_intf_ops(struct _io_ops *pops) { - _func_enter_; _rtw_memset((u8 *)pops, 0, sizeof(struct _io_ops)); @@ -53,6 +47,5 @@ void rtl8822bu_set_intf_ops(struct _io_ops *pops) pops->_read_interrupt = &usb_read_interrupt; #endif - _func_exit_; } diff --git a/hal/rtl8822b/usb/rtl8822bu_led.c b/hal/rtl8822b/usb/rtl8822bu_led.c index 94fb77f..188f1d0 100644 --- a/hal/rtl8822b/usb/rtl8822bu_led.c +++ b/hal/rtl8822b/usb/rtl8822bu_led.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8822BU_LED_C_ #include /* PADAPTER */ diff --git a/hal/rtl8822b/usb/rtl8822bu_ops.c b/hal/rtl8822b/usb/rtl8822bu_ops.c index 97e19be..8310ac4 100644 --- a/hal/rtl8822b/usb/rtl8822bu_ops.c +++ b/hal/rtl8822b/usb/rtl8822bu_ops.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8822BU_OPS_C_ #include /* PADAPTER, basic_types.h and etc. */ @@ -28,8 +23,8 @@ #ifdef CONFIG_SUPPORT_USB_INT static void rtl8822bu_interrupt_handler(PADAPTER padapter, u16 pkt_len, u8 *pbuf) -{ -} +{ + } #endif /* CONFIG_SUPPORT_USB_INT */ void rtl8822bu_set_hw_type(struct dvobj_priv *pdvobj) @@ -41,6 +36,7 @@ void rtl8822bu_set_hw_type(struct dvobj_priv *pdvobj) static void sethwreg(PADAPTER padapter, u8 variable, u8 *val) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); struct registry_priv *registry_par = &padapter->registrypriv; int status = 0; @@ -48,11 +44,55 @@ static void sethwreg(PADAPTER padapter, u8 variable, u8 *val) switch (variable) { case HW_VAR_RXDMA_AGG_PG_TH: #ifdef CONFIG_USB_RX_AGGREGATION - + if (pdvobjpriv->traffic_stat.cur_tx_tp < 1 && pdvobjpriv->traffic_stat.cur_rx_tp < 1) { + /* for low traffic, do not usb AGGREGATION */ + pHalData->rxagg_usb_timeout = 0x01; + pHalData->rxagg_usb_size = 0; + + } else { +#ifdef CONFIG_PLATFORM_NOVATEK_NT72668 + pHalData->rxagg_usb_timeout = 0x20; + pHalData->rxagg_usb_size = 0x03; +#elif defined(CONFIG_PLATFORM_HISILICON) + /* use 16k to workaround for HISILICON platform */ + pHalData->rxagg_usb_timeout = 8; + pHalData->rxagg_usb_size = 3; +#else + /* default setting */ + pHalData->rxagg_usb_timeout = 0x20; + pHalData->rxagg_usb_size = 0x05; +#endif + } + rtw_halmac_rx_agg_switch(pdvobjpriv, _TRUE); +#if 0 + RTW_INFO("\n==========RAFFIC_STATISTIC==============\n"); + RTW_INFO("cur_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_tx_bytes); + RTW_INFO("cur_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_rx_bytes); + + RTW_INFO("last_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_tx_bytes); + RTW_INFO("last_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_rx_bytes); + + RTW_INFO("cur_tx_tp:%d\n", pdvobjpriv->traffic_stat.cur_tx_tp); + RTW_INFO("cur_rx_tp:%d\n", pdvobjpriv->traffic_stat.cur_rx_tp); + RTW_INFO("\n========================\n"); +#endif #endif break; case HW_VAR_SET_RPWM: - +#ifdef CONFIG_LPS_LCLK + { + u8 ps_state = *((u8 *)val); + + /*rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e. + BIT0 value - 1: 32k, 0:40MHz. + BIT6 value - 1: report cpwm value after success set, 0:do not report. + BIT7 value - Toggle bit change. + modify by Thomas. 2012/4/2.*/ + ps_state = ps_state & 0xC1; + /* RTW_INFO("##### Change RPWM value to = %x for switch clk #####\n", ps_state); */ + rtw_write8(padapter, REG_USB_HRPWM_8822B, ps_state); + } +#endif break; case HW_VAR_AMPDU_MAX_TIME: rtw_write8(padapter, REG_AMPDU_MAX_TIME_V1_8822B, 0x70); @@ -74,6 +114,19 @@ static void sethwreg(PADAPTER padapter, u8 variable, u8 *val) } } break; + case HW_VAR_SET_REQ_FW_PS: + { + /* + * 1. driver write 0x8f[4]=1 + * request fw ps state (only can write bit4) + */ + u8 req_fw_ps = 0; + + req_fw_ps = rtw_read8(padapter, 0x8f); + req_fw_ps |= 0x10; + rtw_write8(padapter, 0x8f, req_fw_ps); + } + break; default: rtl8822b_sethwreg(padapter, variable, val); break; @@ -83,15 +136,30 @@ static void sethwreg(PADAPTER padapter, u8 variable, u8 *val) static void gethwreg(PADAPTER padapter, u8 variable, u8 *val) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - _func_enter_; switch (variable) { + case HW_VAR_CPWM: +#ifdef CONFIG_LPS_LCLK + *val = rtw_read8(padapter, REG_USB_HCPWM_8822B); + /* RTW_INFO("##### REG_USB_HCPWM(0x%02x) = 0x%02x #####\n", REG_USB_HCPWM_8822B, *val); */ +#endif /* CONFIG_LPS_LCLK */ + break; + case HW_VAR_RPWM_TOG: +#ifdef CONFIG_LPS_LCLK + *val = rtw_read8(padapter, REG_USB_HRPWM_8822B); + *val &= BIT_TOGGLING_8822B; +#endif /* CONFIG_LPS_LCLK */ + break; + + case HW_VAR_FW_PS_STATE: + /* driver read dword 0x88 to get fw ps state */ + *((u16 *)val) = rtw_read16(padapter, 0x88); + break; default: rtl8822b_gethwreg(padapter, variable, val); break; } - _func_exit_; } /* @@ -164,12 +232,15 @@ static u8 rtl8822bu_ps_func(PADAPTER padapter, HAL_INTF_PS_FUNC efunc_id, u8 *va * 2. Read registers to initialize * 3. Other vaiables initialization */ -static void read_adapter_info(PADAPTER padapter) +static u8 read_adapter_info(PADAPTER padapter) { + u8 ret = _FAIL; + /* * 1. Read Efuse/EEPROM to initialize */ - rtl8822b_read_efuse(padapter); + if (rtl8822b_read_efuse(padapter) != _SUCCESS) + goto exit; /* * 2. Read registers to initialize @@ -178,6 +249,11 @@ static void read_adapter_info(PADAPTER padapter) /* * 3. Other Initialization */ + + ret = _SUCCESS; + +exit: + return ret; } @@ -186,7 +262,6 @@ void rtl8822bu_set_hal_ops(PADAPTER padapter) struct hal_ops *ops; int err; - _func_enter_; err = rtl8822bu_halmac_init_adapter(padapter); if (err) { @@ -196,7 +271,7 @@ void rtl8822bu_set_hal_ops(PADAPTER padapter) rtl8822b_set_hal_ops(padapter); - ops = &padapter->HalFunc; + ops = &padapter->hal_func; ops->hal_init = rtl8822bu_init; ops->hal_deinit = rtl8822bu_deinit; @@ -221,9 +296,9 @@ void rtl8822bu_set_hal_ops(PADAPTER padapter) ops->intf_chip_configure = rtl8822bu_interface_configure; ops->read_adapter_info = read_adapter_info; - ops->SetHwRegHandler = sethwreg; + ops->set_hw_reg_handler = sethwreg; ops->GetHwRegHandler = gethwreg; - ops->GetHalDefVarHandler = gethaldefvar; + ops->get_hal_def_var_handler = gethaldefvar; ops->SetHalDefVarHandler = sethaldefvar; @@ -242,6 +317,5 @@ void rtl8822bu_set_hal_ops(PADAPTER padapter) ops->interrupt_handler = rtl8822bu_interrupt_handler; #endif - _func_exit_; } diff --git a/hal/rtl8822b/usb/rtl8822bu_recv.c b/hal/rtl8822b/usb/rtl8822bu_recv.c index 9e75ffb..983ff99 100644 --- a/hal/rtl8822b/usb/rtl8822bu_recv.c +++ b/hal/rtl8822b/usb/rtl8822bu_recv.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8822BU_RECV_C_ #include /* PADAPTER, rtw_xmit.h and etc. */ @@ -77,10 +72,7 @@ static u8 recvbuf2recvframe_proccess_normal_rx if (pattrib->physt && pphy_status) rx_query_phy_status(precvframe, pphy_status); - if (rtw_recv_entry(precvframe) != _SUCCESS) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, - ("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n")); - } + rtw_recv_entry(precvframe); exit: return ret; @@ -118,7 +110,6 @@ int recvbuf2recvframe(PADAPTER padapter, void *ptr) do { precvframe = rtw_alloc_recvframe(pfree_recv_queue); if (precvframe == NULL) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("recvbuf2recvframe: precvframe==NULL\n")); RTW_INFO("%s()-%d: rtw_alloc_recvframe() failed! RX Drop!\n", __func__, __LINE__); goto _exit_recvbuf2recvframe; } @@ -141,7 +132,6 @@ int recvbuf2recvframe(PADAPTER padapter, void *ptr) pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz + pattrib->pkt_len; if ((pattrib->pkt_len <= 0) || (pkt_offset > transfer_len)) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("recvbuf2recvframe: pkt_len<=0\n")); RTW_INFO("%s()-%d: RX Warning!,pkt_len<=0(%d) or pkt_offset(%d)> transfer_len(%d)\n" , __func__, __LINE__, pattrib->pkt_len, pkt_offset, transfer_len); if (pkt_offset > transfer_len) diff --git a/hal/rtl8822b/usb/rtl8822bu_xmit.c b/hal/rtl8822b/usb/rtl8822bu_xmit.c index 3ecd94c..5e13abb 100644 --- a/hal/rtl8822b/usb/rtl8822bu_xmit.c +++ b/hal/rtl8822b/usb/rtl8822bu_xmit.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8822BU_XMIT_C_ #include /* PADAPTER, rtw_xmit.h and etc. */ @@ -127,6 +122,11 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bag rtl8822b_fill_txdesc_vcs(padapter, pattrib, ptxdesc); +#ifdef CONFIG_CONCURRENT_MODE + if (bmcst) + rtl8822b_fill_txdesc_force_bmc_camid(pattrib, ptxdesc); +#endif + if ((pattrib->ether_type != 0x888e) && (pattrib->ether_type != 0x0806) && (pattrib->ether_type != 0x88b4) && @@ -208,34 +208,16 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bag SET_TX_DESC_USE_RATE_8822B(ptxdesc, 1); DriverFixedRate = 0x01; -#ifdef CONFIG_INTEL_PROXIM - if ((padapter->proximity.proxim_on == _TRUE) && (pattrib->intel_proxim == _TRUE)) { - RTW_INFO("\n %s pattrib->rate=%d\n", __func__, pattrib->rate); - SET_TX_DESC_DATARATE_8822B(ptxdesc, pattrib->rate); - } else -#endif - SET_TX_DESC_DATARATE_8822B(ptxdesc, MRateToHwRate(pattrib->rate)); - - /* VHT NDPA or HT NDPA Packet for Beamformer. */ - if ((pattrib->subtype == WIFI_NDPA) || - ((pattrib->subtype == WIFI_ACTION_NOACK) && (pattrib->order == 1))) { + SET_TX_DESC_DATARATE_8822B(ptxdesc, MRateToHwRate(pattrib->rate)); - SET_TX_DESC_NAVUSEHDR_8822B(ptxdesc, 1); + SET_TX_DESC_RTY_LMT_EN_8822B(ptxdesc, 1); + if (pattrib->retry_ctrl == _TRUE) + SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(ptxdesc, 6); + else + SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(ptxdesc, 12); - SET_TX_DESC_DATA_BW_8822B(ptxdesc, rtl8822b_bw_mapping(padapter, pattrib)); - SET_TX_DESC_RTS_SC_8822B(ptxdesc, rtl8822b_sc_mapping(padapter, pattrib)); - - SET_TX_DESC_RTY_LMT_EN_8822B(ptxdesc, 1); - SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(ptxdesc, 5); - SET_TX_DESC_DISRTSFB_8822B(ptxdesc, 1); - SET_TX_DESC_NDPA_8822B(ptxdesc, 1); - } else { - SET_TX_DESC_RTY_LMT_EN_8822B(ptxdesc, 1); - if (pattrib->retry_ctrl == _TRUE) - SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(ptxdesc, 6); - else - SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(ptxdesc, 12); - } + /* VHT NDPA or HT NDPA Packet for Beamformer. */ + rtl8822b_fill_txdesc_mgnt_bf(pxmitframe, ptxdesc); #ifdef CONFIG_XMIT_ACK /* CCX-TXRPT ack for xmit mgmt frames */ @@ -248,10 +230,14 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bag #endif /* CONFIG_XMIT_ACK */ } else if ((pxmitframe->frame_tag & 0x0f) == TXAGG_FRAMETAG) RTW_INFO("pxmitframe->frame_tag == TXAGG_FRAMETAG\n"); + +#ifdef CONFIG_MP_INCLUDED else if (((pxmitframe->frame_tag & 0x0f) == MP_FRAMETAG) && (padapter->registrypriv.mp_mode == 1)) fill_txdesc_for_mp(padapter, ptxdesc); +#endif + else { RTW_INFO("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag); @@ -260,11 +246,16 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bag SET_TX_DESC_DATARATE_8822B(ptxdesc, MRateToHwRate(pmlmeext->tx_rate)); } + rtl8822b_fill_txdesc_bf(pxmitframe, ptxdesc); + if (DriverFixedRate) SWDefineContent |= 0x01; SET_TX_DESC_SW_DEFINE_8822B(ptxdesc, SWDefineContent); + SET_TX_DESC_PORT_ID_8822B(ptxdesc, get_hw_port(padapter)); + SET_TX_DESC_MULTIPLE_PORT_8822B(ptxdesc, get_hw_port(padapter)); + rtl8822b_cal_txdesc_chksum(padapter, ptxdesc); rtl8822b_dbg_dump_tx_desc(padapter, pxmitframe->frame_tag, ptxdesc); return pull; @@ -293,19 +284,15 @@ s32 rtl8822bu_xmit_buf_handler(PADAPTER padapter) pxmitpriv = &padapter->xmitpriv; ret = _rtw_down_sema(&pxmitpriv->xmit_sema); - if (_FAIL == ret) { - RT_TRACE(_module_hal_xmit_c_, _drv_emerg_, - ("%s: down SdioXmitBufSema fail!\n", __FUNCTION__)); + if (_FAIL == ret) return _FAIL; - } if (RTW_CANNOT_RUN(padapter)) { - RT_TRACE(_module_hal_xmit_c_, _drv_notice_ - , ("%s: bDriverStopped(%s) bSurpriseRemoved(%s)!\n" - , __func__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); - return _FAIL; + RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n", + FUNC_ADPT_ARG(padapter), + rtw_is_drv_stopped(padapter) ? "True" : "False", + rtw_is_surprise_removed(padapter) ? "True" : "False"); + return _FAIL; } if (check_pending_xmitbuf(pxmitpriv) == _FALSE) @@ -314,8 +301,6 @@ s32 rtl8822bu_xmit_buf_handler(PADAPTER padapter) #ifdef CONFIG_LPS_LCLK ret = rtw_register_tx_alive(padapter); if (ret != _SUCCESS) { - RT_TRACE(_module_hal_xmit_c_, _drv_notice_, - ("%s: wait to leave LPS_LCLK\n", __FUNCTION__)); return _SUCCESS; } #endif /* CONFIG_LPS_LCLK */ @@ -325,7 +310,8 @@ s32 rtl8822bu_xmit_buf_handler(PADAPTER padapter) if (pxmitbuf == NULL) break; - rtw_write_port(padapter, pxmitbuf->ff_hwaddr, pxmitbuf->len, (unsigned char *)pxmitbuf); + /* only XMITBUF_DATA & XMITBUF_MGNT */ + rtw_write_port_and_wait(padapter, pxmitbuf->ff_hwaddr, pxmitbuf->len, (unsigned char *)pxmitbuf, 500); } while (1); #ifdef CONFIG_LPS_LCLK @@ -368,7 +354,6 @@ static s32 rtw_dump_xframe(PADAPTER padapter, struct xmit_frame *pxmitframe) ret = _FAIL; if (t != (pattrib->nr_frags - 1)) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("pattrib->nr_frags=%d\n", pattrib->nr_frags)); sz = pxmitpriv->frag_len; sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len); @@ -401,7 +386,12 @@ static s32 rtw_dump_xframe(PADAPTER padapter, struct xmit_frame *pxmitframe) #ifdef CONFIG_XMIT_THREAD_MODE pxmitbuf->len = w_sz; pxmitbuf->ff_hwaddr = ff_hwaddr; - enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf); + + if (pxmitbuf->buf_tag == XMITBUF_CMD) + /* download rsvd page or fw */ + inner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz, (unsigned char *)pxmitbuf); + else + enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf); #else inner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz, (unsigned char *)pxmitbuf); #endif @@ -476,7 +466,6 @@ static s32 rtl8822bu_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxm int res = _SUCCESS; #endif - RT_TRACE(_module_rtl8192c_xmit_c_, _drv_info_, ("+xmitframe_complete\n")); /* check xmitbuffer is ok */ @@ -500,17 +489,12 @@ static s32 rtl8822bu_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxm #ifndef IDEA_CONDITION if (pxmitframe->frame_tag != DATA_FRAMETAG) { - RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, - ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n", - pxmitframe->frame_tag, DATA_FRAMETAG)); continue; } /* TID 0~15 */ if ((pxmitframe->attrib.priority < 0) || (pxmitframe->attrib.priority > 15)) { - RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, - ("xmitframe_complete: TID(%d) should be 0~15!\n", pxmitframe->attrib.priority)); continue; } #endif @@ -629,9 +613,6 @@ static s32 rtl8822bu_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxm #ifndef IDEA_CONDITION /* suppose only data frames would be in queue */ if (pxmitframe->frame_tag != DATA_FRAMETAG) { - RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, - ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n", - pxmitframe->frame_tag, DATA_FRAMETAG)); rtw_free_xmitframe(pxmitpriv, pxmitframe); continue; } @@ -639,9 +620,6 @@ static s32 rtl8822bu_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxm /* TID 0~15 */ if ((pxmitframe->attrib.priority < 0) || (pxmitframe->attrib.priority > 15)) { - RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, - ("xmitframe_complete: TID(%d) should be 0~15!\n", - pxmitframe->attrib.priority)); rtw_free_xmitframe(pxmitpriv, pxmitframe); continue; } @@ -729,7 +707,18 @@ static s32 rtl8822bu_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxm #endif ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe); +#ifdef CONFIG_XMIT_THREAD_MODE + pxmitbuf->len = pbuf_tail; + pxmitbuf->ff_hwaddr = ff_hwaddr; + + if (pxmitbuf->buf_tag == XMITBUF_CMD) + /* download rsvd page or fw */ + rtw_write_port(padapter, ff_hwaddr, pbuf_tail, (u8 *)pxmitbuf); + else + enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf); +#else rtw_write_port(padapter, ff_hwaddr, pbuf_tail, (u8 *)pxmitbuf); +#endif /* 5. update statisitc */ @@ -757,7 +746,6 @@ static s32 rtl8822bu_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxm phwxmits = pxmitpriv->hwxmits; hwentry = pxmitpriv->hwxmit_entry; - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("xmitframe_complete()\n")); if (pxmitbuf == NULL) { pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); @@ -785,7 +773,6 @@ static s32 rtl8822bu_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxm } - RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("xmitframe_complete(): rtw_dump_xframe\n")); if (res == _SUCCESS) @@ -891,7 +878,7 @@ static s32 pre_xmitframe(PADAPTER padapter, struct xmit_frame *pxmitframe) if (rtw_xmit_ac_blocked(padapter) == _TRUE) goto enqueue; - if (padapter->dvobj->iface_state.lg_sta_num) + if (DEV_STA_LG_NUM(padapter->dvobj)) goto enqueue; pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); @@ -916,7 +903,6 @@ static s32 pre_xmitframe(PADAPTER padapter, struct xmit_frame *pxmitframe) _exit_critical_bh(&pxmitpriv->lock, &irqL); if (res != _SUCCESS) { - RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("pre_xmitframe: enqueue xmitframe fail\n")); rtw_free_xmitframe(pxmitpriv, pxmitframe); pxmitpriv->tx_drop++; diff --git a/ifcfg-wlan0 b/ifcfg-wlan0 index 7ecb7ae..20dcbec 100644 --- a/ifcfg-wlan0 +++ b/ifcfg-wlan0 @@ -1,4 +1,4 @@ -#DHCP client -DEVICE=wlan0 -BOOTPROTO=dhcp +#DHCP client +DEVICE=wlan0 +BOOTPROTO=dhcp ONBOOT=yes \ No newline at end of file diff --git a/include/Hal8188EPhyCfg.h b/include/Hal8188EPhyCfg.h index b0d3f4f..917831d 100644 --- a/include/Hal8188EPhyCfg.h +++ b/include/Hal8188EPhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8188EPHYCFG_H__ #define __INC_HAL8188EPHYCFG_H__ @@ -117,8 +112,9 @@ PHY_GetTxPowerIndex_8188E( IN PADAPTER pAdapter, IN u8 RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, - IN u8 Channel + IN u8 BandWidth, + IN u8 Channel, + struct txpwr_idx_comp *tic ); /* @@ -166,7 +162,7 @@ PHY_SetRFEReg_8188E( /* * BB/MAC/RF other monitor API * */ -VOID PHY_SetRFPathSwitch_8188E(IN PADAPTER pAdapter, IN BOOLEAN bMain); +VOID phy_set_rf_path_switch_8188e(IN PADAPTER pAdapter, IN bool bMain); extern VOID PHY_SwitchEphyParameter( @@ -184,13 +180,6 @@ SetAntennaConfig92C( IN u8 DefaultAnt ); -VOID -storePwrIndexDiffRateOffset( - IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data -); /*--------------------------Exported Function prototype---------------------*/ /* diff --git a/include/Hal8188EPhyReg.h b/include/Hal8188EPhyReg.h index 783ea64..2eab831 100644 --- a/include/Hal8188EPhyReg.h +++ b/include/Hal8188EPhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8188EPHYREG_H__ #define __INC_HAL8188EPHYREG_H__ /*--------------------------Define Parameters-------------------------------*/ diff --git a/include/Hal8188EPwrSeq.h b/include/Hal8188EPwrSeq.h index 385722a..46c61ab 100644 --- a/include/Hal8188EPwrSeq.h +++ b/include/Hal8188EPwrSeq.h @@ -1,7 +1,6 @@ - /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,12 +11,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ + #ifndef __HAL8188EPWRSEQ_H__ #define __HAL8188EPWRSEQ_H__ diff --git a/include/Hal8188FPhyCfg.h b/include/Hal8188FPhyCfg.h index 7920650..d513a07 100644 --- a/include/Hal8188FPhyCfg.h +++ b/include/Hal8188FPhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8188FPHYCFG_H__ #define __INC_HAL8188FPHYCFG_H__ @@ -101,8 +96,9 @@ PHY_GetTxPowerIndex_8188F( IN PADAPTER pAdapter, IN u8 RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, - IN u8 Channel + IN u8 BandWidth, + IN u8 Channel, + struct txpwr_idx_comp *tic ); VOID @@ -117,19 +113,6 @@ PHY_SetTxPowerLevel8188F( IN u8 channel ); -VOID -PHY_SetBWMode8188F( - IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth, /* 20M or 40M */ - IN unsigned char Offset /* Upper, Lower, or Don't care */ -); - -VOID -PHY_SwChnl8188F(/* Call after initialization */ - IN PADAPTER Adapter, - IN u8 channel -); - VOID PHY_SetSwChnlBWMode8188F( IN PADAPTER Adapter, @@ -139,10 +122,13 @@ PHY_SetSwChnlBWMode8188F( IN u8 Offset80 ); -VOID PHY_SetRFPathSwitch_8188F( +VOID phy_set_rf_path_switch_8188f( IN PADAPTER pAdapter, - IN BOOLEAN bMain + IN bool bMain ); + +void BBTurnOnBlock_8188F(_adapter *adapter); + /*--------------------------Exported Function prototype End---------------------*/ #endif diff --git a/include/Hal8188FPhyReg.h b/include/Hal8188FPhyReg.h index 8d38c0f..a831faa 100644 --- a/include/Hal8188FPhyReg.h +++ b/include/Hal8188FPhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8188FPHYREG_H__ #define __INC_HAL8188FPHYREG_H__ diff --git a/include/Hal8188FPwrSeq.h b/include/Hal8188FPwrSeq.h index 81e6132..5cad428 100644 --- a/include/Hal8188FPwrSeq.h +++ b/include/Hal8188FPwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef REALTEK_POWER_SEQUENCE_8188F #define REALTEK_POWER_SEQUENCE_8188F diff --git a/include/Hal8192EPhyCfg.h b/include/Hal8192EPhyCfg.h index 02489be..f64b92b 100644 --- a/include/Hal8192EPhyCfg.h +++ b/include/Hal8192EPhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8192EPHYCFG_H__ #define __INC_HAL8192EPHYCFG_H__ @@ -104,30 +99,14 @@ PHY_GetTxPowerIndex_8192E( IN PADAPTER pAdapter, IN u8 RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, - IN u8 Channel -); - -/* - * Switch bandwidth for 8192S - * */ -VOID -PHY_SetBWMode8192E( - IN PADAPTER pAdapter, - IN CHANNEL_WIDTH Bandwidth, - IN u8 Offset + IN u8 BandWidth, + IN u8 Channel, + struct txpwr_idx_comp *tic ); /* * channel switch related funciton * */ -VOID -PHY_SwChnl8192E( - IN PADAPTER Adapter, - IN u8 channel -); - - VOID PHY_SetSwChnlBWMode8192E( IN PADAPTER Adapter, @@ -145,7 +124,7 @@ PHY_SetRFEReg_8192E( void phy_SpurCalibration_8192E( IN PADAPTER Adapter, - IN SPUR_CAL_METHOD Method + IN enum spur_cal_method method ); void PHY_SpurCalibration_8192E(IN PADAPTER Adapter); @@ -160,17 +139,9 @@ phy_SpurCalibration_8192E_NBI( * */ VOID -PHY_SetRFPathSwitch_8192E( +phy_set_rf_path_switch_8192e( IN PADAPTER pAdapter, - IN BOOLEAN bMain -); - -VOID -storePwrIndexDiffRateOffset( - IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data + IN bool bMain ); /*--------------------------Exported Function prototype---------------------*/ diff --git a/include/Hal8192EPhyReg.h b/include/Hal8192EPhyReg.h index cd13c22..a3277b1 100644 --- a/include/Hal8192EPhyReg.h +++ b/include/Hal8192EPhyReg.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ /***************************************************************************** * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. * diff --git a/include/Hal8192EPwrSeq.h b/include/Hal8192EPwrSeq.h index 12bb2fb..bec2d5c 100644 --- a/include/Hal8192EPwrSeq.h +++ b/include/Hal8192EPwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef REALTEK_POWER_SEQUENCE_8192E #define REALTEK_POWER_SEQUENCE_8192E diff --git a/include/Hal8703BPhyCfg.h b/include/Hal8703BPhyCfg.h index e8701f6..da9a7dc 100644 --- a/include/Hal8703BPhyCfg.h +++ b/include/Hal8703BPhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8703BPHYCFG_H__ #define __INC_HAL8703BPHYCFG_H__ @@ -101,8 +96,9 @@ PHY_GetTxPowerIndex_8703B( IN PADAPTER pAdapter, IN u8 RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, - IN u8 Channel + IN u8 BandWidth, + IN u8 Channel, + struct txpwr_idx_comp *tic ); VOID @@ -117,19 +113,6 @@ PHY_SetTxPowerLevel8703B( IN u8 channel ); -VOID -PHY_SetBWMode8703B( - IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth, /* 20M or 40M */ - IN unsigned char Offset /* Upper, Lower, or Don't care */ -); - -VOID -PHY_SwChnl8703B(/* Call after initialization */ - IN PADAPTER Adapter, - IN u8 channel -); - VOID PHY_SetSwChnlBWMode8703B( IN PADAPTER Adapter, @@ -139,9 +122,9 @@ PHY_SetSwChnlBWMode8703B( IN u8 Offset80 ); -VOID PHY_SetRFPathSwitch_8703B( +VOID phy_set_rf_path_switch_8703b( IN PADAPTER pAdapter, - IN BOOLEAN bMain + IN bool bMain ); /*--------------------------Exported Function prototype End---------------------*/ diff --git a/include/Hal8703BPhyReg.h b/include/Hal8703BPhyReg.h index e8eb664..881a13c 100644 --- a/include/Hal8703BPhyReg.h +++ b/include/Hal8703BPhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8703BPHYREG_H__ #define __INC_HAL8703BPHYREG_H__ diff --git a/include/Hal8703BPwrSeq.h b/include/Hal8703BPwrSeq.h index a53ca9a..0dac13e 100644 --- a/include/Hal8703BPwrSeq.h +++ b/include/Hal8703BPwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef REALTEK_POWER_SEQUENCE_8703B #define REALTEK_POWER_SEQUENCE_8703B diff --git a/include/Hal8723BPhyCfg.h b/include/Hal8723BPhyCfg.h index 6a7046d..9d941b4 100644 --- a/include/Hal8723BPhyCfg.h +++ b/include/Hal8723BPhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8723BPHYCFG_H__ #define __INC_HAL8723BPHYCFG_H__ @@ -101,8 +96,9 @@ PHY_GetTxPowerIndex_8723B( IN PADAPTER pAdapter, IN u8 RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, - IN u8 Channel + IN u8 BandWidth, + IN u8 Channel, + struct txpwr_idx_comp *tic ); VOID @@ -117,19 +113,6 @@ PHY_SetTxPowerLevel8723B( IN u8 channel ); -VOID -PHY_SetBWMode8723B( - IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth, /* 20M or 40M */ - IN unsigned char Offset /* Upper, Lower, or Don't care */ -); - -VOID -PHY_SwChnl8723B(/* Call after initialization */ - IN PADAPTER Adapter, - IN u8 channel -); - VOID PHY_SetSwChnlBWMode8723B( IN PADAPTER Adapter, @@ -139,10 +122,11 @@ PHY_SetSwChnlBWMode8723B( IN u8 Offset80 ); -VOID PHY_SetRFPathSwitch_8723B( +VOID phy_set_rf_path_switch_8723b( IN PADAPTER pAdapter, - IN BOOLEAN bMain + IN bool bMain ); + /*--------------------------Exported Function prototype End---------------------*/ #endif diff --git a/include/Hal8723BPhyReg.h b/include/Hal8723BPhyReg.h index 551c0a5..ce485c2 100644 --- a/include/Hal8723BPhyReg.h +++ b/include/Hal8723BPhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8723BPHYREG_H__ #define __INC_HAL8723BPHYREG_H__ diff --git a/include/Hal8723BPwrSeq.h b/include/Hal8723BPwrSeq.h index 6b89562..1aec885 100644 --- a/include/Hal8723BPwrSeq.h +++ b/include/Hal8723BPwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef REALTEK_POWER_SEQUENCE_8723B #define REALTEK_POWER_SEQUENCE_8723B diff --git a/include/Hal8723DPhyCfg.h b/include/Hal8723DPhyCfg.h index c02c5a2..080edd0 100644 --- a/include/Hal8723DPhyCfg.h +++ b/include/Hal8723DPhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8723DPHYCFG_H__ #define __INC_HAL8723DPHYCFG_H__ @@ -101,8 +96,9 @@ PHY_GetTxPowerIndex_8723D( IN PADAPTER pAdapter, IN u8 RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, - IN u8 Channel + IN u8 BandWidth, + IN u8 Channel, + struct txpwr_idx_comp *tic ); VOID @@ -117,19 +113,6 @@ PHY_SetTxPowerLevel8723D( IN u8 channel ); -VOID -PHY_SetBWMode8723D( - IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth, /* 20M or 40M */ - IN unsigned char Offset /* Upper, Lower, or Don't care */ -); - -VOID -PHY_SwChnl8723D(/* Call after initialization */ - IN PADAPTER Adapter, - IN u8 channel -); - VOID PHY_SetSwChnlBWMode8723D( IN PADAPTER Adapter, @@ -139,9 +122,9 @@ PHY_SetSwChnlBWMode8723D( IN u8 Offset80 ); -VOID PHY_SetRFPathSwitch_8723D( +VOID phy_set_rf_path_switch_8723d( IN PADAPTER pAdapter, - IN BOOLEAN bMain + IN bool bMain ); /*--------------------------Exported Function prototype End---------------------*/ diff --git a/include/Hal8723DPhyReg.h b/include/Hal8723DPhyReg.h index c4a52f5..036144a 100644 --- a/include/Hal8723DPhyReg.h +++ b/include/Hal8723DPhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8723DPHYREG_H__ #define __INC_HAL8723DPHYREG_H__ @@ -536,7 +531,7 @@ #define bOFDMTxStatus 0x2 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) -#define RF_TX_GAIN_OFFSET_8723D(_val) (abs((_val)) | (((_val) > 0) ? BIT(5) : 0)) +#define RF_TX_GAIN_OFFSET_8723D(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0)) /* 2. Page8(0x800) */ #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ diff --git a/include/Hal8723DPwrSeq.h b/include/Hal8723DPwrSeq.h index e7a6013..70afbdb 100644 --- a/include/Hal8723DPwrSeq.h +++ b/include/Hal8723DPwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef REALTEK_POWER_SEQUENCE_8723D #define REALTEK_POWER_SEQUENCE_8723D @@ -63,7 +77,6 @@ {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable HSISR GPIO9 interrupt*/\ {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)},/*For GPIO9 internal pull high setting by test chip*/\ {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/*For GPIO9 internal pull high setting*/\ - {0x0073, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)},/*GNT Controlled by Wifi*/\ {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\ {0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\ {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\ diff --git a/include/Hal8723PwrSeq.h b/include/Hal8723PwrSeq.h index 6669641..22de833 100644 --- a/include/Hal8723PwrSeq.h +++ b/include/Hal8723PwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __HAL8723PWRSEQ_H__ #define __HAL8723PWRSEQ_H__ /* diff --git a/include/Hal8812PhyCfg.h b/include/Hal8812PhyCfg.h index fabd2d3..fb0705e 100644 --- a/include/Hal8812PhyCfg.h +++ b/include/Hal8812PhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8812PHYCFG_H__ #define __INC_HAL8812PHYCFG_H__ @@ -103,11 +98,12 @@ u8 PHY_GetTxPowerIndex_8812A( IN PADAPTER pAdapter, IN u8 RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, - IN u8 Channel + IN u8 BandWidth, + IN u8 Channel, + struct txpwr_idx_comp *tic ); -u32 PHY_GetTxBBSwing_8812A( +u32 phy_get_tx_bb_swing_8812a( IN PADAPTER Adapter, IN BAND_TYPE Band, IN u8 RFPath @@ -121,26 +117,9 @@ PHY_SetTxPowerIndex_8812A( IN u1Byte Rate ); -/* - * Switch bandwidth for 8192S - * */ -VOID -PHY_SetBWMode8812( - IN PADAPTER pAdapter, - IN CHANNEL_WIDTH Bandwidth, - IN u8 Offset -); - /* * channel switch related funciton * */ -VOID -PHY_SwChnl8812( - IN PADAPTER Adapter, - IN u8 channel -); - - VOID PHY_SetSwChnlBWMode8812( IN PADAPTER Adapter, @@ -155,9 +134,9 @@ PHY_SetSwChnlBWMode8812( * */ VOID -PHY_SetRFPathSwitch_8812A( +phy_set_rf_path_switch_8812a( IN PADAPTER pAdapter, - IN BOOLEAN bMain + IN bool bMain ); /*--------------------------Exported Function prototype---------------------*/ diff --git a/include/Hal8812PhyReg.h b/include/Hal8812PhyReg.h index 5009750..ef4abb2 100644 --- a/include/Hal8812PhyReg.h +++ b/include/Hal8812PhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8812PHYREG_H__ #define __INC_HAL8812PHYREG_H__ /*--------------------------Define Parameters-------------------------------*/ diff --git a/include/Hal8812PwrSeq.h b/include/Hal8812PwrSeq.h index e089c1a..9ef8c44 100644 --- a/include/Hal8812PwrSeq.h +++ b/include/Hal8812PwrSeq.h @@ -1,7 +1,6 @@ - /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,12 +11,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ + #ifndef __HAL8812PWRSEQ_H__ #define __HAL8812PWRSEQ_H__ diff --git a/include/Hal8814PhyCfg.h b/include/Hal8814PhyCfg.h index aed00c7..2dc3a7f 100644 --- a/include/Hal8814PhyCfg.h +++ b/include/Hal8814PhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8814PHYCFG_H__ #define __INC_HAL8814PHYCFG_H__ @@ -92,12 +87,6 @@ phy_BB8814A_Config_ParaFile( IN PADAPTER Adapter ); - -RT_STATUS -PHY_BBConfigMP_8814A( - IN PADAPTER Adapter -); - VOID PHY_ConfigBB_8814A( IN PADAPTER Adapter @@ -134,7 +123,7 @@ PHY_SetTxPowerLevel8814( ); u8 -PHY_GetTxPowerIndex_8814A( +phy_get_tx_power_index_8814a( IN PADAPTER Adapter, IN u8 RFPath, IN u8 Rate, @@ -142,6 +131,16 @@ PHY_GetTxPowerIndex_8814A( IN u8 Channel ); +u8 +PHY_GetTxPowerIndex8814A( + IN PADAPTER Adapter, + IN u8 RFPath, + IN u8 Rate, + IN u8 BandWidth, + IN u8 Channel, + struct txpwr_idx_comp *tic +); + VOID PHY_SetTxPowerIndex_8814A( IN PADAPTER Adapter, @@ -171,7 +170,7 @@ PHY_GetTxBBSwing_8814A( VOID PHY_SwChnlTimerCallback8814A( - IN PRT_TIMER pTimer + IN struct timer_list *p_timer ); VOID @@ -244,19 +243,6 @@ PHY_SetIO_8814A( PADAPTER pAdapter ); -VOID -PHY_SetBWMode8814( - IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth, /* 20M or 40M */ - IN u8 Offset /* Upper, Lower, or Don't care */ -); - -VOID -PHY_SwChnl8814( - IN PADAPTER Adapter, - IN u8 channel -); - VOID PHY_SetSwChnlBWMode8814( IN PADAPTER Adapter, diff --git a/include/Hal8814PhyReg.h b/include/Hal8814PhyReg.h index 0aec994..2fa46dd 100644 --- a/include/Hal8814PhyReg.h +++ b/include/Hal8814PhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8814PHYREG_H__ #define __INC_HAL8814PHYREG_H__ /*--------------------------Define Parameters-------------------------------*/ diff --git a/include/Hal8814PwrSeq.h b/include/Hal8814PwrSeq.h index 696959b..5f4097d 100644 --- a/include/Hal8814PwrSeq.h +++ b/include/Hal8814PwrSeq.h @@ -1,7 +1,6 @@ - /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,12 +11,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ + #ifndef __HAL8814PWRSEQ_H__ #define __HAL8814PWRSEQ_H__ diff --git a/include/Hal8821APwrSeq.h b/include/Hal8821APwrSeq.h index 393068b..568b8e5 100644 --- a/include/Hal8821APwrSeq.h +++ b/include/Hal8821APwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef REALTEK_POWER_SEQUENCE_8821 #define REALTEK_POWER_SEQUENCE_8821 diff --git a/include/HalPwrSeqCmd.h b/include/HalPwrSeqCmd.h index b511436..f67ed22 100644 --- a/include/HalPwrSeqCmd.h +++ b/include/HalPwrSeqCmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HALPWRSEQCMD_H__ #define __HALPWRSEQCMD_H__ diff --git a/include/HalVerDef.h b/include/HalVerDef.h index 3d81880..f50861d 100644 --- a/include/HalVerDef.h +++ b/include/HalVerDef.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_VERSION_DEF_H__ #define __HAL_VERSION_DEF_H__ @@ -178,24 +173,26 @@ typedef struct tag_HAL_VERSION { #define IS_8723A_A_CUT(version) ((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE) #define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE) #endif +#ifdef CONFIG_USB_HCI +#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) (FALSE) +#else +#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE) +#endif +#define IS_VENDOR_8812A_TEST_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8812A_MP_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8812A_C_CUT(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE) -#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE) - -#define IS_VENDOR_8812A_TEST_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) -#define IS_VENDOR_8812A_MP_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) -#define IS_VENDOR_8812A_C_CUT(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE) - -#define IS_VENDOR_8821A_TEST_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) -#define IS_VENDOR_8821A_MP_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8821A_TEST_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8821A_MP_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE) -#define IS_VENDOR_8192E_B_CUT(_Adapter) ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) == B_CUT_VERSION) ? TRUE : FALSE) +#define IS_VENDOR_8192E_B_CUT(_Adapter) ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == B_CUT_VERSION) ? TRUE : FALSE) -#define IS_VENDOR_8723B_TEST_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) -#define IS_VENDOR_8723B_MP_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8723B_TEST_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8723B_MP_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE) -#define IS_VENDOR_8703B_TEST_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) -#define IS_VENDOR_8703B_MP_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) -#define IS_VENDOR_8814A_TEST_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) -#define IS_VENDOR_8814A_MP_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8703B_TEST_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8703B_MP_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8814A_TEST_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8814A_MP_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE) #endif diff --git a/include/autoconf.h b/include/autoconf.h index a5a4a92..f0f42df 100644 --- a/include/autoconf.h +++ b/include/autoconf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define CONFIG_SINGLE_IMG /* #define CONFIG_DISABLE_ODM */ @@ -24,8 +19,8 @@ * Public General Config */ #define AUTOCONF_INCLUDED -#define RTL871X_MODULE_NAME "8822BU" -#define DRV_NAME "rtl8822bu" +#define RTL871X_MODULE_NAME "88x2BU" +#define DRV_NAME "rtl88x2bu" /* Set CONFIG_RTL8822B from Makefile */ #ifndef CONFIG_RTL8822B @@ -38,51 +33,45 @@ * Wi-Fi Functions Config */ -#define CONFIG_NL80211_BAND_5GHZ 1 +#define CONFIG_IEEE80211_BAND_5GHZ 1 #define CONFIG_80211N_HT 1 #ifdef CONFIG_80211N_HT -#define CONFIG_80211AC_VHT 1 -/* #define CONFIG_BEAMFORMING */ - -#ifdef CONFIG_BEAMFORMING -#define CONFIG_PHYDM_BEAMFORMING -#ifdef CONFIG_PHYDM_BEAMFORMING -#define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/ -#define SUPPORT_MU_BF 0 -#else -#define BEAMFORMING_SUPPORT 0 /*for driver beamforming*/ -#endif -#endif + #define CONFIG_80211AC_VHT 1 + + /* #define CONFIG_BEAMFORMING */ #endif /* set CONFIG_IOCTL_CFG80211 from Makefile */ #ifdef CONFIG_IOCTL_CFG80211 -/* - * Indecate new sta asoc through cfg80211_new_sta - * If kernel version >= 3.2 or - * version < 3.2 but already apply cfg80211 patch, - * RTW_USE_CFG80211_STA_EVENT must be defiend! - */ -/* Set RTW_USE_CFG80211_STA_EVENT from Makefile */ -/* #define RTW_USE_CFG80211_STA_EVENT */ /* Indecate new sta asoc through cfg80211_new_sta */ -#define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER -/* #define CONFIG_DEBUG_CFG80211 */ -/* #define CONFIG_DRV_ISSUE_PROV_REQ */ /* IOT FOR S2 */ -#define CONFIG_SET_SCAN_DENY_TIMER + /* + * Indecate new sta asoc through cfg80211_new_sta + * If kernel version >= 3.2 or + * version < 3.2 but already apply cfg80211 patch, + * RTW_USE_CFG80211_STA_EVENT must be defiend! + */ + /* Set RTW_USE_CFG80211_STA_EVENT from Makefile */ + /* #define RTW_USE_CFG80211_STA_EVENT */ /* Indecate new sta asoc through cfg80211_new_sta */ + #define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER + /* #define CONFIG_DEBUG_CFG80211 */ + /* #define CONFIG_DRV_ISSUE_PROV_REQ */ /* IOT FOR S2 */ + #define CONFIG_SET_SCAN_DENY_TIMER #endif /* * Internal General Config */ /* #define CONFIG_H2CLBK */ -#define CONFIG_C2H_PACKET_EN /* necessary for 8822B */ + #define RTW_HALMAC /* Use HALMAC architecture, necessary for 8822B */ #define CONFIG_EMBEDDED_FWIMG 1 +#if (CONFIG_EMBEDDED_FWIMG==1) + #define LOAD_FW_HEADER_FROM_DRIVER +#endif /* #define CONFIG_FILE_FWIMG */ -/* #define CONFIG_XMIT_ACK */ +#define CONFIG_XMIT_ACK #ifdef CONFIG_XMIT_ACK -#define CONFIG_ACTIVE_KEEP_ALIVE_CHECK + #define CONFIG_ACTIVE_KEEP_ALIVE_CHECK #endif #define CONFIG_RECV_REORDERING_CTRL 1 @@ -91,53 +80,58 @@ /* #define CONFIG_DRVEXT_MODULE 1 */ -#define CONFIG_RF_POWER_TRIM - -#define CONFIG_DFS 1 /* #define CONFIG_SUPPORT_USB_INT */ #ifdef CONFIG_SUPPORT_USB_INT -/* #define CONFIG_USB_INTERRUPT_IN_PIPE 1 */ -#endif + /* #define CONFIG_USB_INTERRUPT_IN_PIPE 1 */ +#endif /* CONFIG_SUPPORT_USB_INT */ /* #ifndef CONFIG_MP_INCLUDED */ -/* #define CONFIG_IPS 1 */ -#ifdef CONFIG_IPS -/* #define CONFIG_IPS_LEVEL_2 1*/ /*enable this to set default IPS mode to IPS_LEVEL_2*/ -#define CONFIG_IPS_CHECK_IN_WD /* Do IPS Check in WatchDog. */ -#endif -/* #define SUPPORT_HW_RFOFF_DETECTED 1 */ - -#define CONFIG_LPS 1 -#if defined(CONFIG_LPS) && defined(CONFIG_SUPPORT_USB_INT) -/* #define CONFIG_LPS_LCLK 1 */ -#endif - -#ifdef CONFIG_LPS_LCLK -#define CONFIG_XMIT_THREAD_MODE -#endif + /* #define CONFIG_IPS 1 */ + #ifdef CONFIG_IPS + /* #define CONFIG_IPS_LEVEL_2 1*/ /*enable this to set default IPS mode to IPS_LEVEL_2*/ + #define CONFIG_IPS_CHECK_IN_WD /* Do IPS Check in WatchDog. */ + /* #define CONFIG_FWLPS_IN_IPS */ + #endif + /* #define SUPPORT_HW_RFOFF_DETECTED 1 */ -/* before link */ -/* #define CONFIG_ANTENNA_DIVERSITY */ + #define CONFIG_LPS 1 + #if defined(CONFIG_LPS) + /* #define CONFIG_LPS_LCLK 1 */ + #endif -/* after link */ -#ifdef CONFIG_ANTENNA_DIVERSITY -#define CONFIG_HW_ANTENNA_DIVERSITY -#endif + #ifdef CONFIG_LPS_LCLK + #ifdef CONFIG_POWER_SAVING + #define CONFIG_XMIT_THREAD_MODE + #endif /* CONFIG_POWER_SAVING */ + #ifndef CONFIG_SUPPORT_USB_INT + #define LPS_RPWM_WAIT_MS 300 + #define CONFIG_DETECT_CPWM_BY_POLLING + #endif /* !CONFIG_SUPPORT_USB_INT */ + /* #define DBG_CHECK_FW_PS_STATE */ + #endif /* CONFIG_LPS_LCLK */ + + /* before link */ + /* #define CONFIG_ANTENNA_DIVERSITY */ + + /* after link */ + #ifdef CONFIG_ANTENNA_DIVERSITY + #define CONFIG_HW_ANTENNA_DIVERSITY + #endif -/*#define CONFIG_CONCURRENT_MODE 1 */ -#ifdef CONFIG_CONCURRENT_MODE -#define CONFIG_HWPORT_SWAP /* Port0->Sec , Port1->Pri */ -/*#define CONFIG_RUNTIME_PORT_SWITCH*/ -/* #define DBG_RUNTIME_PORT_SWITCH */ -#define CONFIG_SCAN_BACKOP -#if 0 -#ifdef CONFIG_RTL8812A -#define CONFIG_TSF_RESET_OFFLOAD 1 /* For 2 PORT TSF SYNC. */ -#endif -#endif -#endif + /*#define CONFIG_CONCURRENT_MODE 1 */ + #ifdef CONFIG_CONCURRENT_MODE + /* #define CONFIG_HWPORT_SWAP */ /* Port0->Sec , Port1->Pri */ + /*#define CONFIG_RUNTIME_PORT_SWITCH*/ + /* #define DBG_RUNTIME_PORT_SWITCH */ + #define CONFIG_SCAN_BACKOP + #if 0 + #ifdef CONFIG_RTL8812A + #define CONFIG_TSF_RESET_OFFLOAD 1 /* For 2 PORT TSF SYNC. */ + #endif + #endif + #endif /*#else*/ /* CONFIG_MP_INCLUDED */ @@ -145,49 +139,49 @@ #define CONFIG_AP_MODE 1 #ifdef CONFIG_AP_MODE -/* #define CONFIG_INTERRUPT_BASED_TXBCN */ /* Tx Beacon when driver BCN_OK ,BCN_ERR interrupt occurs */ -#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_INTERRUPT_BASED_TXBCN) -#undef CONFIG_INTERRUPT_BASED_TXBCN -#endif -#ifdef CONFIG_INTERRUPT_BASED_TXBCN -/* #define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ -#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR -#endif + /* #define CONFIG_INTERRUPT_BASED_TXBCN */ /* Tx Beacon when driver BCN_OK ,BCN_ERR interrupt occurs */ + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_INTERRUPT_BASED_TXBCN) + #undef CONFIG_INTERRUPT_BASED_TXBCN + #endif + #ifdef CONFIG_INTERRUPT_BASED_TXBCN + /* #define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ + #define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + #endif -#define CONFIG_NATIVEAP_MLME -#ifndef CONFIG_NATIVEAP_MLME -#define CONFIG_HOSTAPD_MLME 1 -#endif -#define CONFIG_FIND_BEST_CHANNEL 1 + #define CONFIG_NATIVEAP_MLME + #ifndef CONFIG_NATIVEAP_MLME + #define CONFIG_HOSTAPD_MLME 1 + #endif + #define CONFIG_FIND_BEST_CHANNEL 1 #endif #define CONFIG_P2P 1 #ifdef CONFIG_P2P -/* The CONFIG_WFD is for supporting the Wi-Fi display */ -#define CONFIG_WFD + /* The CONFIG_WFD is for supporting the Wi-Fi display */ + #define CONFIG_WFD -#define CONFIG_P2P_REMOVE_GROUP_INFO + #define CONFIG_P2P_REMOVE_GROUP_INFO -/* #define CONFIG_DBG_P2P */ + /* #define CONFIG_DBG_P2P */ -#define CONFIG_P2P_PS -/* #define CONFIG_P2P_IPS */ -#define CONFIG_P2P_OP_CHK_SOCIAL_CH -#define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT /* replace CONFIG_P2P_CHK_INVITE_CH_LIST flag */ -#define CONFIG_P2P_INVITE_IOT + #define CONFIG_P2P_PS + /* #define CONFIG_P2P_IPS */ + #define CONFIG_P2P_OP_CHK_SOCIAL_CH + #define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT /* replace CONFIG_P2P_CHK_INVITE_CH_LIST flag */ + #define CONFIG_P2P_INVITE_IOT #endif /* Added by Kurt 20110511 */ #ifdef CONFIG_TDLS -#define CONFIG_TDLS_DRIVER_SETUP + #define CONFIG_TDLS_DRIVER_SETUP /* #ifndef CONFIG_WFD #define CONFIG_WFD #endif */ -/* #define CONFIG_TDLS_AUTOSETUP */ -#define CONFIG_TDLS_AUTOCHECKALIVE -#define CONFIG_TDLS_CH_SW /* Enable "CONFIG_TDLS_CH_SW" by default, however limit it to only work in wifi logo test mode but not in normal mode currently */ + /* #define CONFIG_TDLS_AUTOSETUP */ + #define CONFIG_TDLS_AUTOCHECKALIVE + #define CONFIG_TDLS_CH_SW /* Enable "CONFIG_TDLS_CH_SW" by default, however limit it to only work in wifi logo test mode but not in normal mode currently */ #endif @@ -195,10 +189,10 @@ #define CONFIG_LED #ifdef CONFIG_LED -#define CONFIG_SW_LED -#ifdef CONFIG_SW_LED -/* #define CONFIG_LED_HANDLED_BY_CMD_THREAD */ -#endif + #define CONFIG_SW_LED + #ifdef CONFIG_SW_LED + /* #define CONFIG_LED_HANDLED_BY_CMD_THREAD */ + #endif #endif /* CONFIG_LED */ #define USB_INTERFERENCE_ISSUE /* this should be checked in all usb interface */ @@ -226,8 +220,8 @@ */ #ifndef CONFIG_MINIMAL_MEMORY_USAGE -#define CONFIG_USB_TX_AGGREGATION 1 -#define CONFIG_USB_RX_AGGREGATION 1 + #define CONFIG_USB_TX_AGGREGATION 1 + #define CONFIG_USB_RX_AGGREGATION 1 #endif /* #define CONFIG_REDUCE_USB_TX_INT 1 */ /* Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms. */ @@ -241,10 +235,10 @@ #ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX #else -#define CONFIG_PREALLOC_RECV_SKB -#ifdef CONFIG_PREALLOC_RECV_SKB -/* #define CONFIG_FIX_NR_BULKIN_BUFFER */ /* only use PREALLOC_RECV_SKB buffer, don't alloc skb at runtime */ -#endif + #define CONFIG_PREALLOC_RECV_SKB + #ifdef CONFIG_PREALLOC_RECV_SKB + /* #define CONFIG_FIX_NR_BULKIN_BUFFER */ /* only use PREALLOC_RECV_SKB buffer, don't alloc skb at runtime */ + #endif #endif /* @@ -259,17 +253,6 @@ /* #define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ 1 */ -#ifdef CONFIG_WOWLAN -/* #define CONFIG_GTK_OL */ -#define CONFIG_ARP_KEEP_ALIVE -#endif /* CONFIG_WOWLAN */ - -#ifdef CONFIG_GPIO_WAKEUP -#ifndef WAKEUP_GPIO_IDX -#define WAKEUP_GPIO_IDX 1 /* WIFI Chip Side */ -#endif /* WAKEUP_GPIO_IDX */ -#endif /* CONFIG_GPIO_WAKEUP */ - /* * HAL Related Config */ @@ -290,52 +273,52 @@ #define DISABLE_BB_RF 0 #ifdef CONFIG_MP_INCLUDED -#define MP_DRIVER 1 -#define CONFIG_MP_IWPRIV_SUPPORT 1 -/* - #undef CONFIG_USB_TX_AGGREGATION - #undef CONFIG_USB_RX_AGGREGATION -*/ + #define MP_DRIVER 1 + #define CONFIG_MP_IWPRIV_SUPPORT 1 + /* + #undef CONFIG_USB_TX_AGGREGATION + #undef CONFIG_USB_RX_AGGREGATION + */ #else -#define MP_DRIVER 0 + #define MP_DRIVER 0 #endif /* * Platform Related Config */ #ifdef CONFIG_PLATFORM_MN10300 -#define CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV -#define CONFIG_USE_USB_BUFFER_ALLOC_RX + #define CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + #define CONFIG_USE_USB_BUFFER_ALLOC_RX -#if defined(CONFIG_SW_ANTENNA_DIVERSITY) -#undef CONFIG_SW_ANTENNA_DIVERSITY -#define CONFIG_HW_ANTENNA_DIVERSITY -#endif + #if defined(CONFIG_SW_ANTENNA_DIVERSITY) + #undef CONFIG_SW_ANTENNA_DIVERSITY + #define CONFIG_HW_ANTENNA_DIVERSITY + #endif -#if defined(CONFIG_POWER_SAVING) -#undef CONFIG_POWER_SAVING -#endif + #if defined(CONFIG_POWER_SAVING) + #undef CONFIG_POWER_SAVING + #endif #endif /* CONFIG_PLATFORM_MN10300 */ #if defined(CONFIG_PLATFORM_ACTIONS_ATM702X) -#ifdef CONFIG_USB_TX_AGGREGATION -#undef CONFIG_USB_TX_AGGREGATION -#endif -#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX -#define CONFIG_USE_USB_BUFFER_ALLOC_TX -#endif -#ifndef CONFIG_USE_USB_BUFFER_ALLOC_RX -#define CONFIG_USE_USB_BUFFER_ALLOC_RX -#endif + #ifdef CONFIG_USB_TX_AGGREGATION + #undef CONFIG_USB_TX_AGGREGATION + #endif + #ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX + #define CONFIG_USE_USB_BUFFER_ALLOC_TX + #endif + #ifndef CONFIG_USE_USB_BUFFER_ALLOC_RX + #define CONFIG_USE_USB_BUFFER_ALLOC_RX + #endif #endif #ifdef CONFIG_BT_COEXIST -/* for ODM and outsrc BT-Coex */ -#ifndef CONFIG_LPS -#define CONFIG_LPS /* download reserved page to FW */ -#endif + /* for ODM and outsrc BT-Coex */ + #ifndef CONFIG_LPS + #define CONFIG_LPS /* download reserved page to FW */ + #endif #endif /* !CONFIG_BT_COEXIST */ @@ -350,21 +333,15 @@ #define CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR -/*#define CONFIG_BEAMFORMING*/ -#ifdef CONFIG_BEAMFORMING -#define BEAMFORMING_SUPPORT 0 /* Use driver self mechanism, not phydm */ -#define RTW_BEAMFORMING_VERSION_2 -#endif /* CONFIG_BEAMFORMING */ - /* * Debug Related Config */ #define DBG 1 -/* #define CONFIG_DEBUG_RTL871X */ /* RT_TRACE, RT_PRINT_DATA, _func_enter_, _func_exit_ */ #define CONFIG_PROC_DEBUG #define DBG_CONFIG_ERROR_DETECT + /* #define DBG_CONFIG_ERROR_DETECT_INT #define DBG_CONFIG_ERROR_RESET diff --git a/include/basic_types.h b/include/basic_types.h index 60634f9..1c65aa7 100644 --- a/include/basic_types.h +++ b/include/basic_types.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __BASIC_TYPES_H__ #define __BASIC_TYPES_H__ @@ -296,9 +291,9 @@ else { \ WriteLE4Byte(__pStart, \ LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - | \ + | \ ((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \ - ); \ + ); \ } \ } while (0) @@ -309,9 +304,9 @@ else { \ WriteLE2Byte(__pStart, \ LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ - | \ + | \ ((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \ - ); \ + ); \ } \ } while (0) @@ -322,9 +317,9 @@ else { \ WriteLE1Byte(__pStart, \ LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ - | \ + | \ ((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \ - ); \ + ); \ } \ } while (0) @@ -338,9 +333,9 @@ else { \ WriteBE4Byte(__pStart, \ BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - | \ + | \ ((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \ - ); \ + ); \ } \ } while (0) @@ -351,9 +346,9 @@ else { \ WriteBE2Byte(__pStart, \ BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ - | \ + | \ ((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \ - ); \ + ); \ } \ } while (0) @@ -364,9 +359,9 @@ else { \ WriteBE1Byte(__pStart, \ BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ - | \ + | \ ((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \ - ); \ + ); \ } \ } while (0) diff --git a/include/byteorder/big_endian.h b/include/byteorder/big_endian.h index 345e9d8..6b1dc44 100644 --- a/include/byteorder/big_endian.h +++ b/include/byteorder/big_endian.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H #define _LINUX_BYTEORDER_BIG_ENDIAN_H diff --git a/include/byteorder/generic.h b/include/byteorder/generic.h index 02cf675..f85114b 100644 --- a/include/byteorder/generic.h +++ b/include/byteorder/generic.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_BYTEORDER_GENERIC_H #define _LINUX_BYTEORDER_GENERIC_H diff --git a/include/byteorder/little_endian.h b/include/byteorder/little_endian.h index 0b77336..c4b6451 100644 --- a/include/byteorder/little_endian.h +++ b/include/byteorder/little_endian.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H #define _LINUX_BYTEORDER_LITTLE_ENDIAN_H diff --git a/include/byteorder/swab.h b/include/byteorder/swab.h index d6d81b5..a8dd46b 100644 --- a/include/byteorder/swab.h +++ b/include/byteorder/swab.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_BYTEORDER_SWAB_H #define _LINUX_BYTEORDER_SWAB_H diff --git a/include/byteorder/swabb.h b/include/byteorder/swabb.h index ce33424..634519a 100644 --- a/include/byteorder/swabb.h +++ b/include/byteorder/swabb.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_BYTEORDER_SWABB_H #define _LINUX_BYTEORDER_SWABB_H diff --git a/include/circ_buf.h b/include/circ_buf.h index 2352316..7a5b8ef 100644 --- a/include/circ_buf.h +++ b/include/circ_buf.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __CIRC_BUF_H_ #define __CIRC_BUF_H_ 1 diff --git a/include/cmd_osdep.h b/include/cmd_osdep.h index 9c63a1c..e4ba2b6 100644 --- a/include/cmd_osdep.h +++ b/include/cmd_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __CMD_OSDEP_H_ #define __CMD_OSDEP_H_ diff --git a/include/custom_gpio.h b/include/custom_gpio.h index 5691d9a..49411b6 100644 --- a/include/custom_gpio.h +++ b/include/custom_gpio.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __CUSTOM_GPIO_H__ #define __CUSTOM_GPIO_H___ diff --git a/include/drv_conf.h b/include/drv_conf.h index 3246e4e..cf43fab 100644 --- a/include/drv_conf.h +++ b/include/drv_conf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_CONF_H__ #define __DRV_CONF_H__ #include "autoconf.h" @@ -24,45 +19,51 @@ #if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) -#error "Shall be Linux or Windows, but not both!\n" + #error "Shall be Linux or Windows, but not both!\n" #endif #if defined(CONFIG_MCC_MODE) && (!defined(CONFIG_CONCURRENT_MODE)) -#error "Enable CONCURRENT_MODE before enable MCC MODE\n" + #error "Enable CONCURRENT_MODE before enable MCC MODE\n" #endif #if defined(CONFIG_MCC_MODE) && defined(CONFIG_BT_COEXIST) -#error "Disable BT COEXIST before enable MCC MODE\n" + #error "Disable BT COEXIST before enable MCC MODE\n" #endif #if defined(CONFIG_MCC_MODE) && defined(CONFIG_TDLS) -#error "Disable TDLS before enable MCC MODE\n" + #error "Disable TDLS before enable MCC MODE\n" + +#endif + +#if defined(CONFIG_RTW_80211R) && !defined(CONFIG_LAYER2_ROAMING) + + #error "Enable CONFIG_LAYER2_ROAMING before enable CONFIG_RTW_80211R\n" #endif /* Older Android kernel doesn't has CONFIG_ANDROID defined, * add this to force CONFIG_ANDROID defined */ #ifdef CONFIG_PLATFORM_ANDROID -#ifndef CONFIG_ANDROID -#define CONFIG_ANDROID -#endif + #ifndef CONFIG_ANDROID + #define CONFIG_ANDROID + #endif #endif #ifdef CONFIG_ANDROID -/* Some Android build will restart the UI while non-printable ascii is passed -* between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID -* for Android here. If you are sure there is no risk on your system about this, -* mask this macro define to support non-printable ascii ssid. -* #define CONFIG_VALIDATE_SSID */ + /* Some Android build will restart the UI while non-printable ascii is passed + * between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID + * for Android here. If you are sure there is no risk on your system about this, + * mask this macro define to support non-printable ascii ssid. + * #define CONFIG_VALIDATE_SSID */ -/* Android expect dbm as the rx signal strength unit */ -#define CONFIG_SIGNAL_DISPLAY_DBM + /* Android expect dbm as the rx signal strength unit */ + #define CONFIG_SIGNAL_DISPLAY_DBM #endif /* @@ -78,180 +79,223 @@ */ #ifdef CONFIG_RESUME_IN_WORKQUEUE /* this can be removed, because there is no case for this... */ -#if !defined(CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER) -#error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..." -#error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..." -#endif + #if !defined(CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER) + #error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..." + #error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..." + #endif #endif /* About USB VENDOR REQ */ #if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX) -#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically" -#define CONFIG_USB_VENDOR_REQ_MUTEX + #warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically" + #define CONFIG_USB_VENDOR_REQ_MUTEX #endif #if defined(CONFIG_VENDOR_REQ_RETRY) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX) -#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically" -#define CONFIG_USB_VENDOR_REQ_MUTEX + #warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically" + #define CONFIG_USB_VENDOR_REQ_MUTEX #endif #if !defined(CONFIG_AP_MODE) && defined(CONFIG_DFS_MASTER) -#warning "undef CONFIG_DFS_MASTER because CONFIG_AP_MODE is not defined" -#undef CONFIG_DFS_MASTER + #warning "undef CONFIG_DFS_MASTER because CONFIG_AP_MODE is not defined" + #undef CONFIG_DFS_MASTER #endif #define RTW_SCAN_SPARSE_MIRACAST 1 #define RTW_SCAN_SPARSE_BG 0 +#define RTW_SCAN_SPARSE_ROAMING_ACTIVE 1 #ifndef CONFIG_RTW_HIQ_FILTER -#define CONFIG_RTW_HIQ_FILTER 1 + #define CONFIG_RTW_HIQ_FILTER 1 #endif #ifndef CONFIG_RTW_FORCE_IGI_LB -#define CONFIG_RTW_FORCE_IGI_LB 0 + #define CONFIG_RTW_FORCE_IGI_LB 0 #endif #ifndef CONFIG_RTW_ADAPTIVITY_EN -#define CONFIG_RTW_ADAPTIVITY_EN 0 + #define CONFIG_RTW_ADAPTIVITY_EN 0 #endif #ifndef CONFIG_RTW_ADAPTIVITY_MODE -#define CONFIG_RTW_ADAPTIVITY_MODE 0 + #define CONFIG_RTW_ADAPTIVITY_MODE 0 #endif #ifndef CONFIG_RTW_ADAPTIVITY_DML -#define CONFIG_RTW_ADAPTIVITY_DML 0 + #define CONFIG_RTW_ADAPTIVITY_DML 0 #endif #ifndef CONFIG_RTW_ADAPTIVITY_DC_BACKOFF -#define CONFIG_RTW_ADAPTIVITY_DC_BACKOFF 2 + #define CONFIG_RTW_ADAPTIVITY_DC_BACKOFF 2 #endif #ifndef CONFIG_RTW_ADAPTIVITY_TH_L2H_INI -#define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0 + #define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0 #endif #ifndef CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF -#define CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF 0 + #define CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF 0 #endif #ifndef CONFIG_RTW_EXCL_CHS -#define CONFIG_RTW_EXCL_CHS {0} + #define CONFIG_RTW_EXCL_CHS {0} #endif #ifndef CONFIG_RTW_DFS_REGION_DOMAIN -#define CONFIG_RTW_DFS_REGION_DOMAIN 0 + #define CONFIG_RTW_DFS_REGION_DOMAIN 0 +#endif + +#ifndef CONFIG_TXPWR_BY_RATE_EN +#define CONFIG_TXPWR_BY_RATE_EN 2 /* by efuse */ +#endif +#ifndef CONFIG_TXPWR_LIMIT_EN +#define CONFIG_TXPWR_LIMIT_EN 2 /* by efuse */ +#endif + +/* compatible with old fashion configuration */ +#if defined(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY) + #undef CONFIG_TXPWR_BY_RATE_EN + #undef CONFIG_TXPWR_LIMIT_EN + #define CONFIG_TXPWR_BY_RATE_EN 1 + #define CONFIG_TXPWR_LIMIT_EN 1 +#elif defined(CONFIG_CALIBRATE_TX_POWER_TO_MAX) + #undef CONFIG_TXPWR_BY_RATE_EN + #undef CONFIG_TXPWR_LIMIT_EN + #define CONFIG_TXPWR_BY_RATE_EN 1 + #define CONFIG_TXPWR_LIMIT_EN 0 +#endif + +#ifndef RTW_DEF_MODULE_REGULATORY_CERT + #define RTW_DEF_MODULE_REGULATORY_CERT 0 +#endif + +#if RTW_DEF_MODULE_REGULATORY_CERT + /* force enable TX power by rate and TX power limit */ + #undef CONFIG_TXPWR_BY_RATE_EN + #undef CONFIG_TXPWR_LIMIT_EN + #define CONFIG_TXPWR_BY_RATE_EN 1 + #define CONFIG_TXPWR_LIMIT_EN 1 +#endif + +#if !defined(CONFIG_TXPWR_LIMIT) && CONFIG_TXPWR_LIMIT_EN + #define CONFIG_TXPWR_LIMIT +#endif + +#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS + #define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS {0xFF, 0xFF, 0xFF, 0xFF} +#endif +#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS + #define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS {0xFF, 0xFF, 0xFF, 0xFF} +#endif +#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS + #define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS {0xFF, 0xFF, 0xFF, 0xFF} +#endif +#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS + #define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS {0xFF, 0xFF, 0xFF, 0xFF} #endif #ifndef CONFIG_RTW_TARGET_TX_PWR_2G_A -#define CONFIG_RTW_TARGET_TX_PWR_2G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} + #define CONFIG_RTW_TARGET_TX_PWR_2G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} #endif #ifndef CONFIG_RTW_TARGET_TX_PWR_2G_B -#define CONFIG_RTW_TARGET_TX_PWR_2G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} + #define CONFIG_RTW_TARGET_TX_PWR_2G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} #endif #ifndef CONFIG_RTW_TARGET_TX_PWR_2G_C -#define CONFIG_RTW_TARGET_TX_PWR_2G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} + #define CONFIG_RTW_TARGET_TX_PWR_2G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} #endif #ifndef CONFIG_RTW_TARGET_TX_PWR_2G_D -#define CONFIG_RTW_TARGET_TX_PWR_2G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} + #define CONFIG_RTW_TARGET_TX_PWR_2G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} #endif #ifndef CONFIG_RTW_TARGET_TX_PWR_5G_A -#define CONFIG_RTW_TARGET_TX_PWR_5G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1} + #define CONFIG_RTW_TARGET_TX_PWR_5G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1} #endif #ifndef CONFIG_RTW_TARGET_TX_PWR_5G_B -#define CONFIG_RTW_TARGET_TX_PWR_5G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1} + #define CONFIG_RTW_TARGET_TX_PWR_5G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1} #endif #ifndef CONFIG_RTW_TARGET_TX_PWR_5G_C -#define CONFIG_RTW_TARGET_TX_PWR_5G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1} + #define CONFIG_RTW_TARGET_TX_PWR_5G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1} #endif #ifndef CONFIG_RTW_TARGET_TX_PWR_5G_D -#define CONFIG_RTW_TARGET_TX_PWR_5G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1} + #define CONFIG_RTW_TARGET_TX_PWR_5G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1} #endif #ifndef CONFIG_RTW_AMPLIFIER_TYPE_2G -#define CONFIG_RTW_AMPLIFIER_TYPE_2G 0 + #define CONFIG_RTW_AMPLIFIER_TYPE_2G 0 #endif #ifndef CONFIG_RTW_AMPLIFIER_TYPE_5G -#define CONFIG_RTW_AMPLIFIER_TYPE_5G 0 + #define CONFIG_RTW_AMPLIFIER_TYPE_5G 0 #endif #ifndef CONFIG_RTW_RFE_TYPE -#define CONFIG_RTW_RFE_TYPE 64 + #define CONFIG_RTW_RFE_TYPE 64 #endif #ifndef CONFIG_RTW_GLNA_TYPE -#define CONFIG_RTW_GLNA_TYPE 0 + #define CONFIG_RTW_GLNA_TYPE 0 #endif #ifndef CONFIG_RTW_PLL_REF_CLK_SEL -#define CONFIG_RTW_PLL_REF_CLK_SEL 0x0F + #define CONFIG_RTW_PLL_REF_CLK_SEL 0x0F #endif #ifndef CONFIG_IFACE_NUMBER -#ifdef CONFIG_CONCURRENT_MODE -#define CONFIG_IFACE_NUMBER 2 -#else -#define CONFIG_IFACE_NUMBER 1 -#endif + #ifdef CONFIG_CONCURRENT_MODE + #define CONFIG_IFACE_NUMBER 2 + #else + #define CONFIG_IFACE_NUMBER 1 + #endif #endif #ifndef CONFIG_CONCURRENT_MODE -#if (CONFIG_IFACE_NUMBER > 1) -#error "CONFIG_IFACE_NUMBER over 1,but CONFIG_CONCURRENT_MODE not defined" -#endif + #if (CONFIG_IFACE_NUMBER > 1) + #error "CONFIG_IFACE_NUMBER over 1,but CONFIG_CONCURRENT_MODE not defined" + #endif #endif #if (CONFIG_IFACE_NUMBER == 0) -#error "CONFIG_IFACE_NUMBER cound not equel to 0 !!" + #error "CONFIG_IFACE_NUMBER cound not equel to 0 !!" #endif #if (CONFIG_IFACE_NUMBER > 3) -#error "Not support over 3 interfaces yet !!" + #error "Not support over 3 interfaces yet !!" #endif #if (CONFIG_IFACE_NUMBER > 8) /*IFACE_ID_MAX*/ -#error "HW count not support over 8 interfaces !!" + #error "HW count not support over 8 interfaces !!" #endif #if (CONFIG_IFACE_NUMBER > 2) -#define CONFIG_MI_WITH_MBSSID_CAM + #define CONFIG_MI_WITH_MBSSID_CAM -#ifdef CONFIG_MI_WITH_MBSSID_CAM -#define CONFIG_MBSSID_CAM -#if defined(CONFIG_RUNTIME_PORT_SWITCH) -#undef CONFIG_RUNTIME_PORT_SWITCH -#endif -#endif + #ifdef CONFIG_MI_WITH_MBSSID_CAM + #define CONFIG_MBSSID_CAM + #if defined(CONFIG_RUNTIME_PORT_SWITCH) + #undef CONFIG_RUNTIME_PORT_SWITCH + #endif + #endif -#ifdef CONFIG_AP_MODE -#define CONFIG_SWTIMER_BASED_TXBCN -/*#define CONFIG_FW_BASED_BCN*/ -#endif + #ifdef CONFIG_AP_MODE + #define CONFIG_SWTIMER_BASED_TXBCN + /*#define CONFIG_FW_BASED_BCN*/ + #endif #endif #define MACID_NUM_SW_LIMIT 32 #define SEC_CAM_ENT_NUM_SW_LIMIT 32 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) -#define CONFIG_NL80211_BAND_5GHZ + #define CONFIG_IEEE80211_BAND_5GHZ #endif -#ifndef RTW_DEF_MODULE_REGULATORY_CERT -#define RTW_DEF_MODULE_REGULATORY_CERT 0 -#endif - -#if RTW_DEF_MODULE_REGULATORY_CERT -/* force enable TX power by rate and TX power limit */ -#ifndef CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY -#define CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY -#endif +#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)) + #define CONFIG_WOW_PATTERN_HW_CAM #endif /* @@ -267,12 +311,15 @@ /*#define CONFIG_DOSCAN_IN_BUSYTRAFFIC */ +/*Don't release SDIO irq in suspend/resume procedure*/ +#define CONFIG_RTW_SDIO_KEEP_IRQ 0 + /* * Add by Lucas@2016/02/15 * For RX Aggregation */ #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_RX_AGGREGATION) -#define RTW_RX_AGGREGATION + #define RTW_RX_AGGREGATION #endif /* CONFIG_SDIO_HCI || CONFIG_USB_RX_AGGREGATION */ #endif /* __DRV_CONF_H__ */ diff --git a/include/drv_types.h b/include/drv_types.h index eabd01b..b6d71e3 100644 --- a/include/drv_types.h +++ b/include/drv_types.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /*------------------------------------------------------------------------------- For type defines and data structure defines @@ -35,20 +30,20 @@ #include #include #ifdef CONFIG_ARP_KEEP_ALIVE -#include -#include + #include + #include #endif #ifdef PLATFORM_OS_XP -#include + #include #endif #ifdef PLATFORM_OS_CE -#include + #include #endif #ifdef PLATFORM_LINUX -#include + #include #endif enum _NIC_VERSION { @@ -66,15 +61,15 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include #ifdef CONFIG_80211N_HT -#include + #include #endif #ifdef CONFIG_80211AC_VHT -#include + #include #endif #ifdef CONFIG_INTEL_WIDI -#include + #include #endif #include @@ -85,7 +80,7 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include #ifdef CONFIG_BEAMFORMING -#include + #include #endif #include @@ -117,33 +112,33 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER -#include + #include #endif #include #ifdef CONFIG_TDLS -#include + #include #endif /* CONFIG_TDLS */ #ifdef CONFIG_WAPI_SUPPORT -#include + #include #endif /* CONFIG_WAPI_SUPPORT */ #ifdef CONFIG_DRVEXT_MODULE -#include + #include #endif /* CONFIG_DRVEXT_MODULE */ #ifdef CONFIG_MP_INCLUDED -#include + #include #endif /* CONFIG_MP_INCLUDED */ #ifdef CONFIG_BR_EXT -#include + #include #endif /* CONFIG_BR_EXT */ #ifdef CONFIG_IOL -#include + #include #endif /* CONFIG_IOL */ #include @@ -153,12 +148,13 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include +#include #ifdef CONFIG_BT_COEXIST -#include + #include #endif /* CONFIG_BT_COEXIST */ #ifdef CONFIG_MCC_MODE -#include + #include #endif /*CONFIG_MCC_MODE */ #define SPEC_DEV_ID_NONE BIT(0) @@ -197,13 +193,18 @@ struct registry_priv { u8 soft_ap; u8 power_mgnt; u8 ips_mode; + u8 lps_level; u8 smart_ps; u8 usb_rxagg_mode; + u8 dynamic_agg_enable; u8 long_retry_lmt; u8 short_retry_lmt; u16 busy_thresh; u8 ack_policy; u8 mp_mode; +#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR) + u8 mp_customer_str; +#endif u8 mp_dm; u8 software_encrypt; u8 software_decrypt; @@ -222,6 +223,8 @@ struct registry_priv { WLAN_BSSID_EX dev_network; + u8 tx_bw_mode; + #ifdef CONFIG_80211N_HT u8 ht_enable; /* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz */ @@ -231,6 +234,7 @@ struct registry_priv { u8 ampdu_enable;/* for tx */ u8 rx_stbc; u8 ampdu_amsdu;/* A-MPDU Supports A-MSDU is permitted */ + u8 rx_ampdu_sz_limit_by_nss_bw[4][4]; /* 1~4SS, BW20~BW160 */ /* Short GI support Bit Map */ /* BIT0 - 20MHz, 1: support, 0: non-support */ /* BIT1 - 40MHz, 1: support, 0: non-support */ @@ -257,7 +261,7 @@ struct registry_priv { #ifdef CONFIG_80211AC_VHT u8 vht_enable; /* 0:disable, 1:enable, 2:auto */ u8 ampdu_factor; - u8 vht_rate_sel; + u8 vht_rx_mcs_map[2]; #endif /* CONFIG_80211AC_VHT */ u8 lowrate_two_xmit; @@ -325,14 +329,14 @@ struct registry_priv { u8 pll_ref_clk_sel; /* define for tx power adjust */ +#ifdef CONFIG_TXPWR_LIMIT u8 RegEnableTxPowerLimit; +#endif u8 RegEnableTxPowerByRate; - u8 RegPowerBase; - u8 RegPwrTblSel; u8 target_tx_pwr_valid; s8 target_tx_pwr_2g[RF_PATH_MAX][RATE_SECTION_NUM]; -#ifdef CONFIG_NL80211_BAND_5GHZ +#ifdef CONFIG_IEEE80211_BAND_5GHZ s8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1]; #endif @@ -379,11 +383,6 @@ struct registry_priv { u8 dfs_region_domain; #endif -#ifdef CONFIG_NAPI - u8 napi_debug; - u16 napi_weight; -#endif - #ifdef CONFIG_MCC_MODE u8 en_mcc; u32 rtw_mcc_single_tx_cri; @@ -393,9 +392,31 @@ struct registry_priv { u32 rtw_mcc_sta_bw20_target_tx_tp; u32 rtw_mcc_sta_bw40_target_tx_tp; u32 rtw_mcc_sta_bw80_target_tx_tp; + s8 rtw_mcc_policy_table_idx; + u8 rtw_mcc_duration; + u8 rtw_mcc_tsf_sync_offset; + u8 rtw_mcc_start_time_offset; + u8 rtw_mcc_interval; + s8 rtw_mcc_guard_offset0; + s8 rtw_mcc_guard_offset1; #endif /* CONFIG_MCC_MODE */ +#ifdef CONFIG_RTW_NAPI + u8 en_napi; +#ifdef CONFIG_RTW_GRO + u8 en_gro; +#endif /* CONFIG_RTW_GRO */ +#endif /* CONFIG_RTW_NAPI */ + bool default_patterns_en; +#ifdef CONFIG_SUPPORT_TRX_SHARED + u8 trx_share_mode; +#endif + u8 check_hw_status; + + u32 pci_aspm_config; + + u8 iqk_fw_offload; }; /* For registry parameters */ @@ -416,8 +437,10 @@ struct registry_priv { #define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(WLAN_BSSID_EX, field)) #define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field) -#define REGSTY_BW_2G(regsty) ((regsty)->bw_mode & 0x0F) -#define REGSTY_BW_5G(regsty) (((regsty)->bw_mode) >> 4) +#define BW_MODE_2G(bw_mode) ((bw_mode) & 0x0F) +#define BW_MODE_5G(bw_mode) ((bw_mode) >> 4) +#define REGSTY_BW_2G(regsty) BW_MODE_2G((regsty)->bw_mode) +#define REGSTY_BW_5G(regsty) BW_MODE_5G((regsty)->bw_mode) #define REGSTY_IS_BW_2G_SUPPORT(regsty, bw) (REGSTY_BW_2G((regsty)) >= (bw)) #define REGSTY_IS_BW_5G_SUPPORT(regsty, bw) (REGSTY_BW_5G((regsty)) >= (bw)) @@ -425,31 +448,31 @@ struct registry_priv { #define REGSTY_IS_11AC_AUTO(regsty) ((regsty)->vht_enable == 2) typedef struct rtw_if_operations { - int __must_check(*read)(struct dvobj_priv *d, int addr, void *buf, - size_t len, bool fixed); - int __must_check(*write)(struct dvobj_priv *d, int addr, void *buf, - size_t len, bool fixed); + int __must_check (*read)(struct dvobj_priv *d, unsigned int addr, void *buf, + size_t len, bool fixed); + int __must_check (*write)(struct dvobj_priv *d, unsigned int addr, void *buf, + size_t len, bool fixed); } RTW_IF_OPS, *PRTW_IF_OPS; #ifdef CONFIG_SDIO_HCI -#include -#define INTF_DATA SDIO_DATA -#define INTF_OPS PRTW_IF_OPS + #include + #define INTF_DATA SDIO_DATA + #define INTF_OPS PRTW_IF_OPS #elif defined(CONFIG_GSPI_HCI) -#include -#define INTF_DATA GSPI_DATA + #include + #define INTF_DATA GSPI_DATA #elif defined(CONFIG_PCI_HCI) -#include + #include #endif #ifdef CONFIG_CONCURRENT_MODE -#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER) -#define is_vir_adapter(adapter) (adapter->adapter_type == MAX_ADAPTER) -#define get_hw_port(adapter) (adapter->hw_port) + #define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER) + #define is_vir_adapter(adapter) (adapter->adapter_type == VIRTUAL_ADAPTER) + #define get_hw_port(adapter) (adapter->hw_port) #else -#define is_primary_adapter(adapter) (1) -#define is_vir_adapter(adapter) (0) -#define get_hw_port(adapter) (HW_PORT0) + #define is_primary_adapter(adapter) (1) + #define is_vir_adapter(adapter) (0) + #define get_hw_port(adapter) (HW_PORT0) #endif #define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->padapters[IFACE_ID0]) #define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums) @@ -717,10 +740,89 @@ struct macid_ctl_t { u8 iface_bmc[CONFIG_IFACE_NUMBER];/*for bc-sta of AP or Adhoc mode*/ struct macid_bmp ch_g[2]; /* 2 ch concurrency */ u8 h2c_msr[MACID_NUM_SW_LIMIT]; + u8 bw[MACID_NUM_SW_LIMIT]; + u8 vht_en[MACID_NUM_SW_LIMIT]; + u32 rate_bmp0[MACID_NUM_SW_LIMIT]; + u32 rate_bmp1[MACID_NUM_SW_LIMIT]; struct sta_info *sta[MACID_NUM_SW_LIMIT]; }; +/* used for rf_ctl_t.rate_bmp_cck_ofdm */ +#define RATE_BMP_CCK 0x000F +#define RATE_BMP_OFDM 0xFFF0 +#define RATE_BMP_HAS_CCK(_bmp_cck_ofdm) (_bmp_cck_ofdm & RATE_BMP_CCK) +#define RATE_BMP_HAS_OFDM(_bmp_cck_ofdm) (_bmp_cck_ofdm & RATE_BMP_OFDM) +#define RATE_BMP_GET_CCK(_bmp_cck_ofdm) (_bmp_cck_ofdm & RATE_BMP_CCK) +#define RATE_BMP_GET_OFDM(_bmp_cck_ofdm) ((_bmp_cck_ofdm & RATE_BMP_OFDM) >> 4) + +/* used for rf_ctl_t.rate_bmp_ht_by_bw */ +#define RATE_BMP_HT_1SS 0x000000FF +#define RATE_BMP_HT_2SS 0x0000FF00 +#define RATE_BMP_HT_3SS 0x00FF0000 +#define RATE_BMP_HT_4SS 0xFF000000 +#define RATE_BMP_HAS_HT_1SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_1SS) +#define RATE_BMP_HAS_HT_2SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_2SS) +#define RATE_BMP_HAS_HT_3SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_3SS) +#define RATE_BMP_HAS_HT_4SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_4SS) +#define RATE_BMP_GET_HT_1SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_1SS) +#define RATE_BMP_GET_HT_2SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_2SS) >> 8) +#define RATE_BMP_GET_HT_3SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_3SS) >> 16) +#define RATE_BMP_GET_HT_4SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_4SS) >> 24) + +/* used for rf_ctl_t.rate_bmp_vht_by_bw */ +#define RATE_BMP_VHT_1SS 0x000003FF +#define RATE_BMP_VHT_2SS 0x000FFC00 +#define RATE_BMP_VHT_3SS 0x3FF00000 +#define RATE_BMP_HAS_VHT_1SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_1SS) +#define RATE_BMP_HAS_VHT_2SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_2SS) +#define RATE_BMP_HAS_VHT_3SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_3SS) +#define RATE_BMP_GET_VHT_1SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_1SS) +#define RATE_BMP_GET_VHT_2SS(_bmp_vht) ((_bmp_vht & RATE_BMP_VHT_2SS) >> 10) +#define RATE_BMP_GET_VHT_3SS(_bmp_vht) ((_bmp_vht & RATE_BMP_VHT_3SS) >> 20) + +#define TXPWR_LMT_REF_VHT_FROM_HT BIT0 +#define TXPWR_LMT_REF_HT_FROM_VHT BIT1 + +#define TXPWR_LMT_HAS_CCK_1T BIT0 +#define TXPWR_LMT_HAS_CCK_2T BIT1 +#define TXPWR_LMT_HAS_CCK_3T BIT2 +#define TXPWR_LMT_HAS_CCK_4T BIT3 +#define TXPWR_LMT_HAS_OFDM_1T BIT4 +#define TXPWR_LMT_HAS_OFDM_2T BIT5 +#define TXPWR_LMT_HAS_OFDM_3T BIT6 +#define TXPWR_LMT_HAS_OFDM_4T BIT7 + struct rf_ctl_t { + const struct country_chplan *country_ent; + u8 ChannelPlan; + u8 max_chan_nums; + RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM]; + struct p2p_channels channel_list; + + /* used for debug or by tx power limit */ + u16 rate_bmp_cck_ofdm; /* 20MHz */ + u32 rate_bmp_ht_by_bw[2]; /* 20MHz, 40MHz. 4SS supported */ + u32 rate_bmp_vht_by_bw[4]; /* 20MHz, 40MHz, 80MHz, 160MHz. up to 3SS supported */ + + /* used by tx power limit */ + u8 highest_ht_rate_bw_bmp; + u8 highest_vht_rate_bw_bmp; + +#ifdef CONFIG_TXPWR_LIMIT + _mutex txpwr_lmt_mutex; + _list reg_exc_list; + u8 regd_exc_num; + _list txpwr_lmt_list; + u8 txpwr_regd_num; + const char *regd_name; + + u8 txpwr_lmt_2g_cck_ofdm_state; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + u8 txpwr_lmt_5g_cck_ofdm_state; + u8 txpwr_lmt_5g_20_40_ref; + #endif +#endif + #ifdef CONFIG_DFS_MASTER bool radar_detect_by_others; u8 dfs_master_enabled; @@ -746,20 +848,6 @@ struct rf_ctl_t { #define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && time_after((unsigned long)(rfctl)->cac_end_time, (unsigned long)rtw_get_current_time())) #define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && time_after((unsigned long)rtw_get_current_time(), (unsigned long)(rfctl)->cac_start_time)) -struct mi_state { - u8 sta_num; /*WIFI_FW_STATION_STATE*/ - u8 ld_sta_num; /*WIFI_FW_STATION_STATE |_FW_LINKED*/ - u8 lg_sta_num; /*WIFI_FW_STATION_STATE |_FW_UNDER_LINKING*/ - u8 ap_num; /*WIFI_FW_AP_STATE|_FW_LINKED*/ - u8 ld_ap_num; /*WIFI_FW_AP_STATE|_FW_LINKED && asoc_sta_count > 2*/ - u8 adhoc_num; /* WIFI_FW_ADHOC_STATE */ - u8 ld_adhoc_num; /* WIFI_FW_ADHOC_STATE && asoc_sta_count > 2 */ - u8 uwps_num; /*WIFI_UNDER_WPS*/ - u8 union_ch; - u8 union_bw; - u8 union_offset; -}; - #ifdef CONFIG_MBSSID_CAM #define TOTAL_MBID_CAM_NUM 8 #define INVALID_CAM_ID 0xFF @@ -786,16 +874,11 @@ struct halmac_indicator { struct halmacpriv { /* flags */ - /* - * send_general_info - * 0: no need to call halmac_send_general_info() - * 1: need to call halmac_send_general_info() - */ - u8 send_general_info; /* For asynchronous functions */ struct halmac_indicator *indicator; + /* Hardware parameters */ #ifdef CONFIG_SDIO_HCI /* Store hardware tx queue page number setting */ u16 txpage[HW_QUEUE_ENTRY]; @@ -818,6 +901,13 @@ struct dvobj_priv { _mutex hw_init_mutex; _mutex h2c_fwcmd_mutex; + +#ifdef CONFIG_RTW_CUSTOMER_STR + _mutex customer_str_mutex; + struct submit_ctx *customer_str_sctx; + u8 customer_str[RTW_CUSTOMER_STR_LEN]; +#endif + _mutex setch_mutex; _mutex setbw_mutex; _mutex rf_read_reg_mutex; @@ -866,23 +956,34 @@ struct dvobj_priv { ATOMIC_T disable_func; + u8 xmit_block; + _lock xmit_block_lock; + struct pwrctrl_priv pwrctl_priv; struct rtw_traffic_statistics traffic_stat; -#if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY) +#ifdef PLATFORM_LINUX + _thread_hdl_ rtnl_lock_holder; + + #if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY) struct wiphy *wiphy; -#endif + #endif +#endif /* PLATFORM_LINUX */ #ifdef CONFIG_SWTIMER_BASED_TXBCN _timer txbcn_timer; #endif + _timer dynamic_chk_timer; /* dynamic/periodic check timer */ #ifdef RTW_HALMAC void *halmac; struct halmacpriv hmpriv; #endif /* RTW_HALMAC */ +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT + u8 default_port_id; +#endif /*-------- below is for SDIO INTERFACE --------*/ #ifdef INTF_DATA @@ -1007,6 +1108,20 @@ struct dvobj_priv { #endif /*CONFIG_MCC_MODE */ }; +#define DEV_STA_NUM(_dvobj) MSTATE_STA_NUM(&((_dvobj)->iface_state)) +#define DEV_STA_LD_NUM(_dvobj) MSTATE_STA_LD_NUM(&((_dvobj)->iface_state)) +#define DEV_STA_LG_NUM(_dvobj) MSTATE_STA_LG_NUM(&((_dvobj)->iface_state)) +#define DEV_AP_NUM(_dvobj) MSTATE_AP_NUM(&((_dvobj)->iface_state)) +#define DEV_AP_LD_NUM(_dvobj) MSTATE_AP_LD_NUM(&((_dvobj)->iface_state)) +#define DEV_ADHOC_NUM(_dvobj) MSTATE_ADHOC_NUM(&((_dvobj)->iface_state)) +#define DEV_ADHOC_LD_NUM(_dvobj) MSTATE_ADHOC_LD_NUM(&((_dvobj)->iface_state)) +#define DEV_WPS_NUM(_dvobj) MSTATE_WPS_NUM(&((_dvobj)->iface_state)) +#define DEV_ROCH_NUM(_dvobj) MSTATE_ROCH_NUM(&((_dvobj)->iface_state)) +#define DEV_MGMT_TX_NUM(_dvobj) MSTATE_MGMT_TX_NUM(&((_dvobj)->iface_state)) +#define DEV_U_CH(_dvobj) MSTATE_U_CH(&((_dvobj)->iface_state)) +#define DEV_U_BW(_dvobj) MSTATE_U_BW(&((_dvobj)->iface_state)) +#define DEV_U_OFFSET(_dvobj) MSTATE_U_OFFSET(&((_dvobj)->iface_state)) + #define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv)) #define pwrctl_to_dvobj(pwrctl) container_of(pwrctl, struct dvobj_priv, pwrctl_priv) #define dvobj_to_macidctl(dvobj) (&(dvobj->macid_ctl)) @@ -1018,8 +1133,28 @@ struct dvobj_priv { #define dvobj_to_rfctl(dvobj) (&(dvobj->rf_ctl)) #define rfctl_to_dvobj(rfctl) container_of((rfctl), struct dvobj_priv, rf_ctl) +static inline void dev_set_surprise_removed(struct dvobj_priv *dvobj) +{ + ATOMIC_SET(&dvobj->bSurpriseRemoved, _TRUE); +} +static inline void dev_clr_surprise_removed(struct dvobj_priv *dvobj) +{ + ATOMIC_SET(&dvobj->bSurpriseRemoved, _FALSE); +} +static inline void dev_set_drv_stopped(struct dvobj_priv *dvobj) +{ + ATOMIC_SET(&dvobj->bDriverStopped, _TRUE); +} +static inline void dev_clr_drv_stopped(struct dvobj_priv *dvobj) +{ + ATOMIC_SET(&dvobj->bDriverStopped, _FALSE); +} +#define dev_is_surprise_removed(dvobj) (ATOMIC_READ(&dvobj->bSurpriseRemoved) == _TRUE) +#define dev_is_drv_stopped(dvobj) (ATOMIC_READ(&dvobj->bDriverStopped) == _TRUE) + #ifdef PLATFORM_LINUX -static struct device *dvobj_to_dev(struct dvobj_priv *dvobj) { +static struct device *dvobj_to_dev(struct dvobj_priv *dvobj) +{ /* todo: get interface type from dvobj and the return the dev accordingly */ #ifdef RTW_DVOBJ_CHIP_HW_TYPE #endif @@ -1040,6 +1175,8 @@ static struct device *dvobj_to_dev(struct dvobj_priv *dvobj) { #endif _adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj); +_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj); +_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr); #define dvobj_get_primary_adapter(dvobj) ((dvobj)->padapters[IFACE_ID0]) enum _hw_port { @@ -1063,6 +1200,13 @@ typedef enum _DRIVER_STATE { DRIVER_REPLACE_DONGLE = 2, } DRIVER_STATE; +#ifdef CONFIG_RTW_NAPI +enum _NAPI_STATE { + NAPI_DISABLE = 0, + NAPI_ENABLE = 1, +}; +#endif + #ifdef CONFIG_INTEL_PROXIM struct proxim { bool proxim_support; @@ -1070,7 +1214,7 @@ struct proxim { void *proximity_priv; int (*proxim_rx)(_adapter *padapter, - union recv_frame *precv_frame); + union recv_frame *precv_frame); u8(*proxim_get_var)(_adapter *padapter, u8 type); }; #endif /* CONFIG_INTEL_PROXIM */ @@ -1091,6 +1235,14 @@ typedef struct loopbackdata { } LOOPBACKDATA, *PLOOPBACKDATA; #endif +struct tsf_info { + u8 sync_port;/*tsf sync from portx*/ + u8 offset; /*tsf timer offset*/ +}; + +#define ADAPTER_TX_BW_2G(adapter) BW_MODE_2G((adapter)->driver_tx_bw_mode) +#define ADAPTER_TX_BW_5G(adapter) BW_MODE_5G((adapter)->driver_tx_bw_mode) + struct _ADAPTER { int DriverState;/* for disable driver using module, use dongle to replace module. */ int pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */ @@ -1113,6 +1265,14 @@ struct _ADAPTER { struct registry_priv registrypriv; struct led_priv ledpriv; +#ifdef CONFIG_CHNL_LOAD_MAGT + BOOLEAN clm_flag; +#endif + +#ifdef CONFIG_RTW_NAPI + struct napi_struct napi; + u8 napi_state; +#endif #ifdef CONFIG_MP_INCLUDED struct mp_priv mppriv; @@ -1160,7 +1320,7 @@ struct _ADAPTER { PVOID HalData; u32 hal_data_sz; - struct hal_ops HalFunc; + struct hal_ops hal_func; u32 IsrContent; u32 ImrContent; @@ -1182,6 +1342,7 @@ struct _ADAPTER { _thread_hdl_ xmitThread; _thread_hdl_ recvThread; + u8 registered; #ifndef PLATFORM_LINUX NDIS_STATUS(*dvobj_init)(struct dvobj_priv *dvobj); void (*dvobj_deinit)(struct dvobj_priv *dvobj); @@ -1240,10 +1401,6 @@ struct _ADAPTER { #endif /* CONFIG_IOCTL_CFG80211 */ -#ifdef CONFIG_NAPI - struct napi_struct napi; -#endif /* CONFIG_NAPI */ - #endif /* PLATFORM_LINUX */ #ifdef PLATFORM_FREEBSD @@ -1256,7 +1413,6 @@ struct _ADAPTER { u8 netif_up; - u8 bFWReady; u8 bBTFWReady; u8 bLinkInfoDump; u8 bRxRSSIDisplay; @@ -1279,6 +1435,7 @@ struct _ADAPTER { ** refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.*/ u8 adapter_type;/*be used in Multi-interface to recognize whether is PRIMARY_ADAPTER or not(PRIMARY_ADAPTER/VIRTUAL_ADAPTER) .*/ u8 hw_port; /*interface port type, it depends on HW port */ + struct tsf_info tsf; /*extend to support multi interface*/ @@ -1316,6 +1473,17 @@ struct _ADAPTER { u8 fix_rate; u8 fix_bw; u8 data_fb; /* data rate fallback, valid only when fix_rate is not 0xff */ + u8 power_offset; + u8 driver_tx_bw_mode; + u8 rsvd_page_offset; + u8 rsvd_page_num; + +#ifdef CONFIG_SUPPORT_FIFO_DUMP + u8 fifo_sel; + u32 fifo_addr; + u32 fifo_size; +#endif + u8 driver_vcs_en; /* Enable=1, Disable=0 driver control vrtl_carrier_sense for tx */ u8 driver_vcs_type;/* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */ u8 driver_ampdu_spacing;/* driver control AMPDU Density for peer sta's rx */ @@ -1323,8 +1491,11 @@ struct _ADAPTER { u8 driver_rx_ampdu_spacing; /* driver control Rx AMPDU Density */ u8 fix_rx_ampdu_accept; u8 fix_rx_ampdu_size; /* 0~127, TODO:consider each sta and each TID */ +#ifdef CONFIG_TX_AMSDU u8 tx_amsdu; u16 tx_amsdu_rate; +#endif + u8 driver_tx_max_agg_num; /*fix tx desc max agg num , 0xff: disable drv ctrl*/ unsigned char in_cta_test; #ifdef DBG_RX_COUNTER_DUMP u8 dump_rx_cnt_mode;/*BIT0:drv,BIT1:mac,BIT2:phy*/ @@ -1357,6 +1528,7 @@ struct _ADAPTER { #define adapter_to_rfctl(adapter) dvobj_to_rfctl(adapter_to_dvobj((adapter))) #define adapter_mac_addr(adapter) (adapter->mac_addr) +#define adapter_to_chset(adapter) (adapter_to_rfctl((adapter))->channel_set) #define mlme_to_adapter(mlme) container_of((mlme), struct _ADAPTER, mlmepriv) #define tdls_info_to_adapter(tdls) container_of((tdls), struct _ADAPTER, tdlsinfo) @@ -1367,20 +1539,24 @@ struct _ADAPTER { #define rtw_get_mi_nums(adapter) (((PADAPTER)adapter)->dvobj->iface_nums) -static inline void rtw_set_surprise_removed(_adapter *padapter) { - ATOMIC_SET(&adapter_to_dvobj(padapter)->bSurpriseRemoved, _TRUE); +static inline void rtw_set_surprise_removed(_adapter *padapter) +{ + dev_set_surprise_removed(adapter_to_dvobj(padapter)); } -static inline void rtw_clr_surprise_removed(_adapter *padapter) { - ATOMIC_SET(&adapter_to_dvobj(padapter)->bSurpriseRemoved, _FALSE); +static inline void rtw_clr_surprise_removed(_adapter *padapter) +{ + dev_clr_surprise_removed(adapter_to_dvobj(padapter)); } -static inline void rtw_set_drv_stopped(_adapter *padapter) { - ATOMIC_SET(&adapter_to_dvobj(padapter)->bDriverStopped, _TRUE); +static inline void rtw_set_drv_stopped(_adapter *padapter) +{ + dev_set_drv_stopped(adapter_to_dvobj(padapter)); } -static inline void rtw_clr_drv_stopped(_adapter *padapter) { - ATOMIC_SET(&adapter_to_dvobj(padapter)->bDriverStopped, _FALSE); +static inline void rtw_clr_drv_stopped(_adapter *padapter) +{ + dev_clr_drv_stopped(adapter_to_dvobj(padapter)); } -#define rtw_is_surprise_removed(padapter) (ATOMIC_READ(&adapter_to_dvobj(padapter)->bSurpriseRemoved) == _TRUE) -#define rtw_is_drv_stopped(padapter) (ATOMIC_READ(&adapter_to_dvobj(padapter)->bDriverStopped) == _TRUE) +#define rtw_is_surprise_removed(padapter) (dev_is_surprise_removed(adapter_to_dvobj(padapter))) +#define rtw_is_drv_stopped(padapter) (dev_is_drv_stopped(adapter_to_dvobj(padapter))) /* * Function disabled. @@ -1391,13 +1567,15 @@ static inline void rtw_clr_drv_stopped(_adapter *padapter) { /* #define RTW_DISABLE_FUNC(padapter, func) (ATOMIC_ADD(&adapter_to_dvobj(padapter)->disable_func, (func))) */ /* #define RTW_ENABLE_FUNC(padapter, func) (ATOMIC_SUB(&adapter_to_dvobj(padapter)->disable_func, (func))) */ -__inline static void RTW_DISABLE_FUNC(_adapter *padapter, int func_bit) { +__inline static void RTW_DISABLE_FUNC(_adapter *padapter, int func_bit) +{ int df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func); df |= func_bit; ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df); } -__inline static void RTW_ENABLE_FUNC(_adapter *padapter, int func_bit) { +__inline static void RTW_ENABLE_FUNC(_adapter *padapter, int func_bit) +{ int df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func); df &= ~(func_bit); ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df); @@ -1424,41 +1602,41 @@ __inline static void RTW_ENABLE_FUNC(_adapter *padapter, int func_bit) { #ifdef CONFIG_PNO_SUPPORT int rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid, int max, int *bytes_left); int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num, - int pno_time, int pno_repeat, int pno_freq_expo_max); + int pno_time, int pno_repeat, int pno_freq_expo_max); #ifdef CONFIG_PNO_SET_DEBUG -void rtw_dev_pno_debug(struct net_device *net); + void rtw_dev_pno_debug(struct net_device *net); #endif /* CONFIG_PNO_SET_DEBUG */ #endif /* CONFIG_PNO_SUPPORT */ int rtw_suspend_free_assoc_resource(_adapter *padapter); #ifdef CONFIG_WOWLAN -int rtw_suspend_wow(_adapter *padapter); -int rtw_resume_process_wow(_adapter *padapter); + int rtw_suspend_wow(_adapter *padapter); + int rtw_resume_process_wow(_adapter *padapter); #endif /* HCI Related header file */ #ifdef CONFIG_USB_HCI -#include -#include -#include + #include + #include + #include #endif #ifdef CONFIG_SDIO_HCI -#include -#include -#include + #include + #include + #include #endif #ifdef CONFIG_GSPI_HCI -#include -#include -#include + #include + #include + #include #endif #ifdef CONFIG_PCI_HCI -#include -#include -#include + #include + #include + #include #endif #endif /* __DRV_TYPES_H__ */ diff --git a/include/drv_types_ce.h b/include/drv_types_ce.h index fc26389..c00dea8 100644 --- a/include/drv_types_ce.h +++ b/include/drv_types_ce.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_TYPES_CE_H__ #define __DRV_TYPES_CE_H__ diff --git a/include/drv_types_gspi.h b/include/drv_types_gspi.h index f0efc8c..c22c497 100644 --- a/include/drv_types_gspi.h +++ b/include/drv_types_gspi.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_TYPES_GSPI_H__ #define __DRV_TYPES_GSPI_H__ diff --git a/include/drv_types_linux.h b/include/drv_types_linux.h index 812b744..91ca68b 100644 --- a/include/drv_types_linux.h +++ b/include/drv_types_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_TYPES_LINUX_H__ #define __DRV_TYPES_LINUX_H__ diff --git a/include/drv_types_pci.h b/include/drv_types_pci.h index c03657f..682688d 100644 --- a/include/drv_types_pci.h +++ b/include/drv_types_pci.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_TYPES_PCI_H__ #define __DRV_TYPES_PCI_H__ @@ -29,8 +24,10 @@ #define INTEL_VENDOR_ID 0x8086 #define SIS_VENDOR_ID 0x1039 #define ATI_VENDOR_ID 0x1002 -#define ATI_DEVICE_ID 0x7914 #define AMD_VENDOR_ID 0x1022 +#define NVI_VENDOR_ID 0x10de + +#define ATI_DEVICE_ID 0x7914 #define PCI_MAX_BRIDGE_NUMBER 255 #define PCI_MAX_DEVICES 32 @@ -86,9 +83,10 @@ enum pci_bridge_vendor { PCI_BRIDGE_VENDOR_INTEL = 0x0,/* 0b'0000,0001 */ PCI_BRIDGE_VENDOR_ATI, /* = 0x02, */ /* 0b'0000,0010 */ PCI_BRIDGE_VENDOR_AMD, /* = 0x04, */ /* 0b'0000,0100 */ - PCI_BRIDGE_VENDOR_SIS ,/* = 0x08, */ /* 0b'0000,1000 */ + PCI_BRIDGE_VENDOR_SIS, /* = 0x08, */ /* 0b'0000,1000 */ + PCI_BRIDGE_VENDOR_NVI, /* = 0x10, */ /* 0b'0001,0000 */ PCI_BRIDGE_VENDOR_UNKNOWN, /* = 0x40, */ /* 0b'0100,0000 */ - PCI_BRIDGE_VENDOR_MAX ,/* = 0x80 */ + PCI_BRIDGE_VENDOR_MAX, /* = 0x80 */ } ; /* copy this data structor defination from MSDN SDK */ diff --git a/include/drv_types_sdio.h b/include/drv_types_sdio.h index 736ae06..9feca12 100644 --- a/include/drv_types_sdio.h +++ b/include/drv_types_sdio.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_TYPES_SDIO_H__ #define __DRV_TYPES_SDIO_H__ @@ -24,11 +19,8 @@ #ifdef PLATFORM_LINUX #include #include - - #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_PLATFORM_SPRD) - #include - #include - #endif + #include + #include #ifdef CONFIG_PLATFORM_SPRD #include @@ -45,6 +37,10 @@ #include #endif +#define RTW_SDIO_CLK_33M 33000000 +#define RTW_SDIO_CLK_40M 40000000 +#define RTW_SDIO_CLK_80M 80000000 +#define RTW_SDIO_CLK_160M 160000000 typedef struct sdio_data { u8 func_number; @@ -56,6 +52,9 @@ typedef struct sdio_data { #ifdef PLATFORM_LINUX struct sdio_func *func; _thread_hdl_ sys_sdio_irq_thd; + unsigned int clock; + unsigned int timing; + u8 sd3_bus_mode; #endif #ifdef PLATFORM_OS_XP diff --git a/include/drv_types_xp.h b/include/drv_types_xp.h index 93766be..81c4504 100644 --- a/include/drv_types_xp.h +++ b/include/drv_types_xp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_TYPES_XP_H__ #define __DRV_TYPES_XP_H__ diff --git a/include/ethernet.h b/include/ethernet.h index e127605..2bafa4d 100644 --- a/include/ethernet.h +++ b/include/ethernet.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /*! \file */ #ifndef __INC_ETHERNET_H #define __INC_ETHERNET_H diff --git a/include/gspi_hal.h b/include/gspi_hal.h index 98fec09..6da0f07 100644 --- a/include/gspi_hal.h +++ b/include/gspi_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __GSPI_HAL_H__ #define __GSPI_HAL_H__ diff --git a/include/gspi_ops.h b/include/gspi_ops.h index 6812915..bcfaad2 100644 --- a/include/gspi_ops.h +++ b/include/gspi_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __GSPI_OPS_H__ #define __GSPI_OPS_H__ @@ -179,7 +174,7 @@ extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter); extern u8 CheckIPSStatus(PADAPTER padapter); #endif /* CONFIG_RTL8188E */ #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - extern u8 RecvOnePkt(PADAPTER padapter, u32 size); + extern u8 RecvOnePkt(PADAPTER padapter); #endif /* CONFIG_WOWLAN */ #endif /* __GSPI_OPS_H__ */ diff --git a/include/gspi_ops_linux.h b/include/gspi_ops_linux.h index 9bd18da..0ba263d 100644 --- a/include/gspi_ops_linux.h +++ b/include/gspi_ops_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __SDIO_OPS_LINUX_H__ #define __SDIO_OPS_LINUX_H__ diff --git a/include/gspi_osintf.h b/include/gspi_osintf.h index e51d2e4..6393f77 100644 --- a/include/gspi_osintf.h +++ b/include/gspi_osintf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __SDIO_OSINTF_H__ #define __SDIO_OSINTF_H__ diff --git a/include/h2clbk.h b/include/h2clbk.h index e7f0df5..4e22afc 100644 --- a/include/h2clbk.h +++ b/include/h2clbk.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _H2CLBK_H_ diff --git a/include/hal_btcoex.h b/include/hal_btcoex.h index 9241bc2..0e01607 100644 --- a/include/hal_btcoex.h +++ b/include/hal_btcoex.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_BTCOEX_H__ #define __HAL_BTCOEX_H__ @@ -42,6 +37,7 @@ void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum); u8 hal_btcoex_Initialize(PADAPTER padapter); void hal_btcoex_PowerOnSetting(PADAPTER padapter); +void hal_btcoex_PowerOffSetting(PADAPTER padapter); void hal_btcoex_PreLoadFirmware(PADAPTER padapter); void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly); @@ -55,8 +51,7 @@ void hal_btcoex_IQKNotify(PADAPTER padapter, u8 state); void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf); void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf); void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state); -void hal_btcoex_HaltNotify(PADAPTER padapter); -void hal_btcoex_ScoreBoardStatusNotify(PADAPTER padapter, u8 length, u8 *tmpBuf); +void hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt); void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter); void hal_btcoex_Hanlder(PADAPTER padapter); @@ -81,7 +76,7 @@ void hal_btcoex_SetBtPatchVersion(PADAPTER, u16 btHciVer, u16 btPatchVer); void hal_btcoex_SetHciVersion(PADAPTER, u16 hciVersion); void hal_btcoex_SendScanNotify(PADAPTER, u8 type); void hal_btcoex_StackUpdateProfileInfo(void); -void hal_btcoex_BTOffOnNotify(PADAPTER padapter, u8 bBTON); +void hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON); void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype); #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE int hal_btcoex_AntIsolationConfig_ParaFile(IN PADAPTER Adapter, IN char *pFileName); @@ -91,4 +86,9 @@ u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data); u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val); void hal_btcoex_set_rfe_type(u8 type); void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type); + +#ifdef CONFIG_RF4CE_COEXIST +void hal_btcoex_set_rf4ce_link_state(u8 state); +u8 hal_btcoex_get_rf4ce_link_state(void); +#endif #endif /* !__HAL_BTCOEX_H__ */ diff --git a/include/hal_com.h b/include/hal_com.h index f8c9d76..5a10a27 100644 --- a/include/hal_com.h +++ b/include/hal_com.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_COMMON_H__ #define __HAL_COMMON_H__ @@ -192,12 +187,6 @@ (rate == DESC_RATEVHTSS3MCS8) ? "VHTSS3MCS8" :\ (rate == DESC_RATEVHTSS3MCS9) ? "VHTSS3MCS9" : "UNKNOWN" -#define HDATA_BW(bw)\ - (bw == CHANNEL_WIDTH_20) ? "20M" :\ - (bw == CHANNEL_WIDTH_40) ? "40M" :\ - (bw == CHANNEL_WIDTH_80) ? "80M" :\ - (bw == CHANNEL_WIDTH_160) ? "160M" : "UNKNOWN" - enum { UP_LINK, DOWN_LINK, @@ -218,6 +207,30 @@ typedef enum _CH_SW_USE_CASE { CH_SW_USE_CASE_MCC = 1 } CH_SW_USE_CASE; +typedef enum _WAKEUP_REASON{ + RX_PAIRWISEKEY = 0x01, + RX_GTK = 0x02, + RX_FOURWAY_HANDSHAKE = 0x03, + RX_DISASSOC = 0x04, + RX_DEAUTH = 0x08, + RX_ARP_REQUEST = 0x09, + FW_DECISION_DISCONNECT = 0x10, + RX_MAGIC_PKT = 0x21, + RX_UNICAST_PKT = 0x22, + RX_PATTERN_PKT = 0x23, + RTD3_SSID_MATCH = 0x24, + RX_REALWOW_V2_WAKEUP_PKT = 0x30, + RX_REALWOW_V2_ACK_LOST = 0x31, + ENABLE_FAIL_DMA_IDLE = 0x40, + ENABLE_FAIL_DMA_PAUSE = 0x41, + RTIME_FAIL_DMA_IDLE = 0x42, + RTIME_FAIL_DMA_PAUSE = 0x43, + RX_PNO = 0x55, + AP_OFFLOAD_WAKEUP = 0x66, + CLK_32K_UNLOCK = 0xFD, + CLK_32K_LOCK = 0xFE +}WAKEUP_REASON; + /* * Queue Select Value in TxDesc * */ @@ -314,6 +327,8 @@ void rtw_hal_config_rftype(PADAPTER padapter); #define WL_FUNC_FTM BIT3 #define WL_FUNC_BIT_NUM 4 +#define TBTT_PROBIHIT_HOLD_TIME 0x80 + int hal_spec_init(_adapter *adapter); void dump_hal_spec(void *sel, _adapter *adapter); @@ -327,7 +342,7 @@ u8 hal_largest_bw(_adapter *adapter, u8 in_bw); bool hal_chk_wl_func(_adapter *adapter, u8 func); -u8 hal_com_config_channel_plan( +void hal_com_config_channel_plan( IN PADAPTER padapter, IN char *hw_alpha2, IN u8 hw_chplan, @@ -347,7 +362,7 @@ HAL_IsLegalChannel( u8 MRateToHwRate(u8 rate); -u8 HwRateToMRate(u8 rate); +u8 hw_rate_to_m_rate(u8 rate); void HalSetBrateCfg( IN PADAPTER Adapter, @@ -360,15 +375,21 @@ Hal_MappingOutPipe( IN u8 NumOutPipe ); - +void rtw_dump_fw_info(void *sel, _adapter *adapter); void rtw_restore_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/ void rtw_hal_dump_macaddr(void *sel, _adapter *adapter); void rtw_init_hal_com_default_value(PADAPTER Adapter); +#ifdef CONFIG_FW_C2H_REG void c2h_evt_clear(_adapter *adapter); -s32 c2h_evt_read(_adapter *adapter, u8 *buf); s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf); +#endif + +#ifdef CONFIG_FW_C2H_PKT +void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len); +void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len); +#endif u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta); u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type); @@ -379,6 +400,7 @@ u32 rtw_sec_read_cam(_adapter *adapter, u8 addr); void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata); void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key); void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key); +void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id); bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id); void rtw_hal_set_msr(_adapter *adapter, u8 net_type); @@ -392,6 +414,7 @@ void hw_var_port_switch(_adapter *adapter); void SetHwReg(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg(PADAPTER padapter, u8 variable, u8 *val); void rtw_hal_check_rxfifo_full(_adapter *adapter); +void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid); u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value); u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value); @@ -509,6 +532,9 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished); s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode); #endif #endif +#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) +s32 rtw_hal_set_wifi_port_id_cmd(_adapter *adapter); +#endif #ifdef CONFIG_GPIO_API u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num); @@ -527,61 +553,12 @@ void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case); void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval); #endif -typedef enum _HAL_PHYDM_OPS { - HAL_PHYDM_DIS_ALL_FUNC, - HAL_PHYDM_FUNC_SET, - HAL_PHYDM_FUNC_CLR, - HAL_PHYDM_ABILITY_BK, - HAL_PHYDM_ABILITY_RESTORE, - HAL_PHYDM_ABILITY_SET, - HAL_PHYDM_ABILITY_GET, -} HAL_PHYDM_OPS; - - -#define DYNAMIC_FUNC_DISABLE (0x0) -u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability); - -#define rtw_phydm_func_disable_all(adapter) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0) - -#define rtw_phydm_func_for_offchannel(adapter) \ - do { \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \ - if (rtw_odm_adaptivity_needed(adapter)) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \ - } while (0) - -#define rtw_phydm_func_set(adapter, ability) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ability) - -#define rtw_phydm_func_clr(adapter, ability) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability) - -#define rtw_phydm_ability_backup(adapter) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0) - -#define rtw_phydm_ability_restore(adapter) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0) - -#define rtw_phydm_ability_set(adapter, ability) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_SET, ability) - -static inline u32 rtw_phydm_ability_get(_adapter *adapter) -{ - return rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0); -} - #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE extern char *rtw_phy_file_path; extern char rtw_phy_para_file_path[PATH_LENGTH_MAX]; #define GetLineFromBuffer(buffer) strsep(&buffer, "\r\n") #endif -#ifdef CONFIG_FW_C2H_DEBUG - void Debug_FwC2H(PADAPTER padapter, u8 *pdata, u8 len); -#endif -/*CONFIG_FW_C2H_DEBUG*/ - void update_IOT_info(_adapter *padapter); #ifdef CONFIG_AUTO_CHNL_SEL_NHM @@ -609,7 +586,72 @@ void StopTxBeacon(_adapter *padapter); #endif #ifdef CONFIG_LPS_PG +#define LPSPG_RSVD_PAGE_SET_MACID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 0, 8, _value)/*used macid*/ +#define LPSPG_RSVD_PAGE_SET_MBSSCAMID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 8, 8, _value)/*used BSSID CAM entry*/ +#define LPSPG_RSVD_PAGE_SET_PMC_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 16, 8, _value)/*Max used Pattern Match CAM entry*/ +#define LPSPG_RSVD_PAGE_SET_MU_RAID_GID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 24, 8, _value)/*Max MU rate table Group ID*/ +#define LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 0, 8, _value)/*used Security CAM entry number*/ +#define LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 8, 8, _value)/*Txbuf used page number for fw offload*/ +#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID1(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 0, 8, _value)/*used Security CAM entry -1*/ +#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID2(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 8, 8, _value)/*used Security CAM entry -2*/ +#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID3(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 16, 8, _value)/*used Security CAM entry -3*/ +#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID4(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 24, 8, _value)/*used Security CAM entry -4*/ +#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID5(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 0, 8, _value)/*used Security CAM entry -5*/ +#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID6(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 8, 8, _value)/*used Security CAM entry -6*/ +#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID7(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 16, 8, _value)/*used Security CAM entry -7*/ +#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID8(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 24, 8, _value)/*used Security CAM entry -8*/ +enum lps_pg_hdl_id { + LPS_PG_INFO_CFG = 0, + LPS_PG_REDLEMEM, + LPS_PG_RESEND_H2C, +}; + u8 rtw_hal_set_lps_pg_info(_adapter *adapter); #endif +int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size); + +#ifdef CONFIG_WOWLAN +struct rtl_wow_pattern { + u16 crc; + u8 type; + u32 mask[4]; +}; +void rtw_wow_pattern_cam_dump(_adapter *adapter); + +#ifdef CONFIG_WOW_PATTERN_HW_CAM +void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct rtl_wow_pattern *context); +void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx); +#endif + +struct rtw_ndp_info { + u8 enable:1; + u8 check_remote_ip:1; /* Need to Check Sender IP or not */ + u8 rsvd:6; + u8 num_of_target_ip; /* Number of Check IP which NA query IP */ + u8 target_link_addr[6]; /* DUT's MAC address */ + u8 remote_ipv6_addr[16]; /* Just respond IP */ + u8 target_ipv6_addr[16]; /* target IP */ +}; +#endif +void rtw_dump_phy_cap(void *sel, _adapter *adapter); +void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num); +#ifdef CONFIG_SUPPORT_FIFO_DUMP +void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size); +#endif + +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT +s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id); +s32 rtw_set_default_port_id(_adapter *adapter); +s32 rtw_set_ps_rsvd_page(_adapter *adapter); +#endif + +#ifdef CONFIG_P2P_PS +#ifdef RTW_HALMAC +void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state); +#endif +#endif + +void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter); + #endif /* __HAL_COMMON_H__ */ diff --git a/include/hal_com_h2c.h b/include/hal_com_h2c.h index 62f6cc6..9e63909 100644 --- a/include/hal_com_h2c.h +++ b/include/hal_com_h2c.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __COMMON_H2C_H__ #define __COMMON_H2C_H__ @@ -32,6 +27,7 @@ enum h2c_cmd { H2C_KEEP_ALIVE = 0x03, H2C_DISCON_DECISION = 0x04, H2C_PSD_OFFLOAD = 0x05, + H2C_CUSTOMER_STR_REQ = 0x06, H2C_AP_OFFLOAD = 0x08, H2C_BCN_RSVDPAGE = 0x09, H2C_PROBERSP_RSVDPAGE = 0x0A, @@ -42,7 +38,7 @@ enum h2c_cmd { H2C_MCC_UPDATE_PARAM = 0x15, H2C_MCC_MACID_BITMAP = 0x16, H2C_MCC_LOCATION = 0x10, - H2C_MCC_INFO = 0x18, + H2C_MCC_CTRL = 0x18, H2C_MCC_NOA_PARAM = 0x19, H2C_MCC_IQK_PARAM = 0x1A, #endif /* CONFIG_MCC_MODE */ @@ -65,6 +61,10 @@ enum h2c_cmd { #ifdef CONFIG_LPS_PG H2C_LPS_PG_INFO = 0x2B, #endif + +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT + H2C_DEFAULT_PORT_ID = 0x2C, +#endif /* Dynamic Mechanism Class: 010 */ H2C_MACID_CFG = 0x40, H2C_TXBF = 0x41, @@ -91,7 +91,9 @@ enum h2c_cmd { H2C_BT_CONTROL = 0x68, H2C_BT_WIFI_CTRL = 0x69, H2C_BT_FW_PATCH = 0x6A, - +#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) + H2C_BTC_WL_PORT_ID = 0x71, +#endif /* WOWLAN Class: 100 */ H2C_WOWLAN = 0x80, H2C_REMOTE_WAKE_CTRL = 0x81, @@ -107,12 +109,20 @@ enum h2c_cmd { H2C_RESET_TSF = 0xC0, H2C_BCNHWSEQ = 0xC5, + H2C_CUSTOMER_STR_W1 = 0xC6, + H2C_CUSTOMER_STR_W2 = 0xC7, + H2C_CUSTOMER_STR_W3 = 0xC8, H2C_MAXID, }; #define H2C_INACTIVE_PS_LEN 3 #define H2C_RSVDPAGE_LOC_LEN 5 +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT +#define H2C_DEFAULT_PORT_ID_LEN 2 +#define H2C_MEDIA_STATUS_RPT_LEN 4 +#else #define H2C_MEDIA_STATUS_RPT_LEN 3 +#endif #define H2C_KEEP_ALIVE_CTRL_LEN 2 #define H2C_DISCON_DECISION_LEN 3 #define H2C_AP_OFFLOAD_LEN 3 @@ -129,14 +139,14 @@ enum h2c_cmd { #define H2C_SCAN_OFFLOAD_CTRL_LEN 4 #define H2C_BT_FW_PATCH_LEN 6 #define H2C_RSSI_SETTING_LEN 4 -#define H2C_AP_REQ_TXRPT_LEN 2 +#define H2C_AP_REQ_TXRPT_LEN 3 #define H2C_FORCE_BT_TXPWR_LEN 3 #define H2C_BCN_RSVDPAGE_LEN 5 #define H2C_PROBERSP_RSVDPAGE_LEN 5 #define H2C_P2PRSVDPAGE_LOC_LEN 5 #define H2C_P2P_OFFLOAD_LEN 3 #ifdef CONFIG_MCC_MODE - #define H2C_MCC_INFO_LEN 7 + #define H2C_MCC_CTRL_LEN 7 #define H2C_MCC_LOCATION_LEN 3 #define H2C_MCC_MACID_BITMAP_LEN 6 #define H2C_MCC_UPDATE_INFO_LEN 4 @@ -151,56 +161,62 @@ enum h2c_cmd { #define H2C_LPS_POFF_CTRL_LEN 1 #define H2C_LPS_POFF_PARAM_LEN 5 #endif -#define eqMacAddr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0) -#define cpMacAddr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5]) + +#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) +#define H2C_BTC_WL_PORT_ID_LEN 1 +#endif +#define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0) +#define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5]) #define cpIpAddr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3]) + + #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - /* - * ARP packet - * - * LLC Header */ - #define GET_ARP_PKT_LLC_TYPE(__pHeader) ReadLE2Byte(((u8 *)(__pHeader)) + 6) - - /* ARP element */ - #define GET_ARP_PKT_OPERATION(__pHeader) ReadLE2Byte(((u8 *)(__pHeader)) + 6) - #define GET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr((u8 *)(_val), ((u8 *)(__pHeader))+8) - #define GET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr((u8 *)(_val), ((u8 *)(__pHeader))+14) - #define GET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr((u8 *)(_val), ((u8 *)(__pHeader))+18) - #define GET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr((u8 *)(_val), ((u8 *)(__pHeader))+24) - - #define SET_ARP_PKT_HW(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 0, __Value) - #define SET_ARP_PKT_PROTOCOL(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 2, __Value) - #define SET_ARP_PKT_HW_ADDR_LEN(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 4, __Value) - #define SET_ARP_PKT_PROTOCOL_ADDR_LEN(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 5, __Value) - #define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 6, __Value) - #define SET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8 *)(__pHeader))+8, (u8 *)(_val)) - #define SET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr(((u8 *)(__pHeader))+14, (u8 *)(_val)) - #define SET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8 *)(__pHeader))+18, (u8 *)(_val)) - #define SET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr(((u8 *)(__pHeader))+24, (u8 *)(_val)) - - #define FW_WOWLAN_FUN_EN BIT(0) - #define FW_WOWLAN_PATTERN_MATCH BIT(1) - #define FW_WOWLAN_MAGIC_PKT BIT(2) - #define FW_WOWLAN_UNICAST BIT(3) - #define FW_WOWLAN_ALL_PKT_DROP BIT(4) - #define FW_WOWLAN_GPIO_ACTIVE BIT(5) - #define FW_WOWLAN_REKEY_WAKEUP BIT(6) - #define FW_WOWLAN_DEAUTH_WAKEUP BIT(7) - - #define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0) - #define FW_FW_PARSE_MAGIC_PKT BIT(1) - - #define FW_REMOTE_WAKE_CTRL_EN BIT(0) - #define FW_REALWOWLAN_EN BIT(5) - - #define FW_WOWLAN_KEEP_ALIVE_EN BIT(0) - #define FW_ADOPT_USER BIT(1) - #define FW_WOWLAN_KEEP_ALIVE_PKT_TYPE BIT(2) - - #define FW_REMOTE_WAKE_CTRL_EN BIT(0) - #define FW_ARP_EN BIT(1) - #define FW_REALWOWLAN_EN BIT(5) - #define FW_WOW_FW_UNICAST_EN BIT(7) +/* +* ARP packet +* +* LLC Header */ +#define GET_ARP_PKT_LLC_TYPE(__pHeader) ReadLE2Byte(((u8 *)(__pHeader)) + 6) + +/* ARP element */ +#define GET_ARP_PKT_OPERATION(__pHeader) ReadLE2Byte(((u8 *)(__pHeader)) + 6) +#define GET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cp_mac_addr((u8 *)(_val), ((u8 *)(__pHeader))+8) +#define GET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr((u8 *)(_val), ((u8 *)(__pHeader))+14) +#define GET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cp_mac_addr((u8 *)(_val), ((u8 *)(__pHeader))+18) +#define GET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr((u8 *)(_val), ((u8 *)(__pHeader))+24) + +#define SET_ARP_PKT_HW(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 0, __Value) +#define SET_ARP_PKT_PROTOCOL(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 2, __Value) +#define SET_ARP_PKT_HW_ADDR_LEN(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 4, __Value) +#define SET_ARP_PKT_PROTOCOL_ADDR_LEN(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 5, __Value) +#define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 6, __Value) +#define SET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cp_mac_addr(((u8 *)(__pHeader))+8, (u8 *)(_val)) +#define SET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr(((u8 *)(__pHeader))+14, (u8 *)(_val)) +#define SET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cp_mac_addr(((u8 *)(__pHeader))+18, (u8 *)(_val)) +#define SET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr(((u8 *)(__pHeader))+24, (u8 *)(_val)) + +#define FW_WOWLAN_FUN_EN BIT(0) +#define FW_WOWLAN_PATTERN_MATCH BIT(1) +#define FW_WOWLAN_MAGIC_PKT BIT(2) +#define FW_WOWLAN_UNICAST BIT(3) +#define FW_WOWLAN_ALL_PKT_DROP BIT(4) +#define FW_WOWLAN_GPIO_ACTIVE BIT(5) +#define FW_WOWLAN_REKEY_WAKEUP BIT(6) +#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7) + +#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0) +#define FW_FW_PARSE_MAGIC_PKT BIT(1) + +#define FW_REMOTE_WAKE_CTRL_EN BIT(0) +#define FW_REALWOWLAN_EN BIT(5) + +#define FW_WOWLAN_KEEP_ALIVE_EN BIT(0) +#define FW_ADOPT_USER BIT(1) +#define FW_WOWLAN_KEEP_ALIVE_PKT_TYPE BIT(2) + +#define FW_REMOTE_WAKE_CTRL_EN BIT(0) +#define FW_ARP_EN BIT(1) +#define FW_REALWOWLAN_EN BIT(5) +#define FW_WOW_FW_UNICAST_EN BIT(7) #endif /* CONFIG_WOWLAN */ @@ -219,6 +235,7 @@ enum h2c_cmd { #define SET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 4, 4, (__Value)) #define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value)) #define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 2, 0, 8, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_PORT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 3, 0, 3, (__Value)) #define GET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 0, 1) #define GET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 2, 1) @@ -251,14 +268,47 @@ s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool #define SET_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) #define SET_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) #define SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 3, __Value) #define SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) /* _DISCONNECT_DECISION_CMD_0x04 */ #define SET_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) #define SET_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_DISCONDECISION_PORT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 3, __Value) #define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) #define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) +#ifdef CONFIG_RTW_CUSTOMER_STR +#define RTW_CUSTOMER_STR_LEN 16 +#define RTW_CUSTOMER_STR_FMT "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x" +#define RTW_CUSTOMER_STR_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \ + ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \ + ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] + +/* H2C_CUSTOMER_STR_REQ 0x06 */ +#define H2C_CUSTOMER_STR_REQ_LEN 1 +#define SET_H2CCMD_CUSTOMER_STR_REQ_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value)) +s32 rtw_hal_h2c_customer_str_req(_adapter *adapter); +s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs); + +/* H2C_CUSTOMER_STR_W1 0xC6 */ +#define H2C_CUSTOMER_STR_W1_LEN 7 +#define SET_H2CCMD_CUSTOMER_STR_W1_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value)) +#define H2CCMD_CUSTOMER_STR_W1_BYTE0(__pH2CCmd) (((u8 *)(__pH2CCmd)) + 1) + +/* H2C_CUSTOMER_STR_W2 0xC7 */ +#define H2C_CUSTOMER_STR_W2_LEN 7 +#define SET_H2CCMD_CUSTOMER_STR_W2_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value)) +#define H2CCMD_CUSTOMER_STR_W2_BYTE6(__pH2CCmd) (((u8 *)(__pH2CCmd)) + 1) + +/* H2C_CUSTOMER_STR_W3 0xC8 */ +#define H2C_CUSTOMER_STR_W3_LEN 5 +#define SET_H2CCMD_CUSTOMER_STR_W3_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value)) +#define H2CCMD_CUSTOMER_STR_W3_BYTE12(__pH2CCmd) (((u8 *)(__pH2CCmd)) + 1) +s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs); +s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); +#endif /* CONFIG_RTW_CUSTOMER_STR */ + /* _AP_Offload 0x08 */ #define SET_H2CCMD_AP_WOWLAN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) /* _BCN_RsvdPage 0x09 */ @@ -298,49 +348,56 @@ s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) #endif +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT +/* DEFAULT PORT ID 0x2C*/ +#define SET_H2CCMD_DFTPID_PORT_ID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 8, (__Value)) +#define SET_H2CCMD_DFTPID_MAC_ID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value)) +#endif + #ifdef CONFIG_MCC_MODE - /* MCC LOC CMD 0x10 */ - #define SET_H2CCMD_MCC_RSVDPAGE_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) - - /* MCC MAC ID CMD 0x16 */ - #define SET_H2CCMD_MCC_MACID_BITMAP_L(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) - #define SET_H2CCMD_MCC_MACID_BITMAP_H(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) - - /* MCC INFO CMD 0x18 */ - #define SET_H2CCMD_MCC_INFO_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) - #define SET_H2CCMD_MCC_INFO_TOTALNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) - #define SET_H2CCMD_MCC_INFO_CHIDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) - #define SET_H2CCMD_MCC_INFO_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value) - #define SET_H2CCMD_MCC_INFO_BW40SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 3, __Value) - #define SET_H2CCMD_MCC_INFO_BW80SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 5, 3, __Value) - #define SET_H2CCMD_MCC_INFO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) - #define SET_H2CCMD_MCC_INFO_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value) - #define SET_H2CCMD_MCC_INFO_INCURCH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value) - #define SET_H2CCMD_MCC_INFO_RSVD0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value) - #define SET_H2CCMD_MCC_INFO_RSVD1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) - #define SET_H2CCMD_MCC_INFO_RFETYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 4, __Value) - #define SET_H2CCMD_MCC_INFO_DISTXNULL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 4, 1, __Value) - #define SET_H2CCMD_MCC_INFO_C2HRPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 5, 2, __Value) - #define SET_H2CCMD_MCC_INFO_CHSCAN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value) - - /* MCC NoA CMD 0x19 */ - #define SET_H2CCMD_MCC_NOA_FW_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) - #define SET_H2CCMD_MCC_NOA_TSF_SYNC_OFFSET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value) - #define SET_H2CCMD_MCC_NOA_START_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) - #define SET_H2CCMD_MCC_NOA_INTERVAL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) - #define SET_H2CCMD_MCC_EARLY_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) - - /* MCC IQK CMD 0x1A */ - #define SET_H2CCMD_MCC_IQK_READY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) - #define SET_H2CCMD_MCC_IQK_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 2, __Value) - #define SET_H2CCMD_MCC_IQK_RX_L(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) - #define SET_H2CCMD_MCC_IQK_RX_M1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value) - #define SET_H2CCMD_MCC_IQK_RX_M2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 6, __Value) - #define SET_H2CCMD_MCC_IQK_RX_H(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 4, __Value) - #define SET_H2CCMD_MCC_IQK_TX_L(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) - #define SET_H2CCMD_MCC_IQK_TX_M1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 3, __Value) - #define SET_H2CCMD_MCC_IQK_TX_M2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 3, 5, __Value) - #define SET_H2CCMD_MCC_IQK_TX_H(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 6, __Value) +/* MCC LOC CMD 0x10 */ +#define SET_H2CCMD_MCC_RSVDPAGE_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) + +/* MCC MAC ID CMD 0x16 */ +#define SET_H2CCMD_MCC_MACID_BITMAP_L(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_MCC_MACID_BITMAP_H(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) + +/* MCC INFO CMD 0x18 */ +#define SET_H2CCMD_MCC_CTRL_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_TOTALNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_CHIDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_MCC_CTRL_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value) +#define SET_H2CCMD_MCC_CTRL_BW40SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 3, __Value) +#define SET_H2CCMD_MCC_CTRL_BW80SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 5, 3, __Value) +#define SET_H2CCMD_MCC_CTRL_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_MCC_CTRL_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value) +#define SET_H2CCMD_MCC_CTRL_INCURCH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value) +#define SET_H2CCMD_MCC_CTRL_RSVD0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_RSVD1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) +#define SET_H2CCMD_MCC_CTRL_RFETYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_DISTXNULL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 4, 1, __Value) +#define SET_H2CCMD_MCC_CTRL_C2HRPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 5, 2, __Value) +#define SET_H2CCMD_MCC_CTRL_CHSCAN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value) + +/* MCC NoA CMD 0x19 */ +#define SET_H2CCMD_MCC_NOA_FW_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_MCC_NOA_TSF_SYNC_OFFSET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value) +#define SET_H2CCMD_MCC_NOA_START_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_MCC_NOA_INTERVAL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_MCC_EARLY_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) + +/* MCC IQK CMD 0x1A */ +#define SET_H2CCMD_MCC_IQK_READY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_MCC_IQK_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 4, __Value) +#define SET_H2CCMD_MCC_IQK_PATH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 2, __Value) +#define SET_H2CCMD_MCC_IQK_RX_L(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_MCC_IQK_RX_M1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value) +#define SET_H2CCMD_MCC_IQK_RX_M2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 6, __Value) +#define SET_H2CCMD_MCC_IQK_RX_H(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 4, __Value) +#define SET_H2CCMD_MCC_IQK_TX_L(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_H2CCMD_MCC_IQK_TX_M1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 3, __Value) +#define SET_H2CCMD_MCC_IQK_TX_M2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 3, 5, __Value) +#define SET_H2CCMD_MCC_IQK_TX_H(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 6, __Value) #endif /* CONFIG_MCC_MODE */ /* CHNL SWITCH OPER OFFLOAD 0x1C */ @@ -350,6 +407,10 @@ s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool #define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 5, 3, __Value) #define SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 0, 4, __Value) +#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) +#define SET_H2CCMD_BTC_WL_PORT_ID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#endif + /* _WoWLAN PARAM_CMD_0x80 */ #define SET_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) #define SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) @@ -375,6 +436,9 @@ s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool #define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) #define SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 1, __Value) #define SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 2, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(__pH2CCmd, __Value) \ + SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 3, 1, __Value) + #define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value) #define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 1, __Value) @@ -389,38 +453,46 @@ s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) #ifdef CONFIG_GTK_OL - #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) #endif /* CONFIG_GTK_OL */ +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(__pH2CCmd, __Value) \ + SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value) + +/* AOAC_RSVDPAGE_2_0x84 */ + +/* AOAC_RSVDPAGE_3_0x88 */ #ifdef CONFIG_PNO_SUPPORT - #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) #endif +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(__pH2CCmd, __Value) \ + SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 8, __Value) #ifdef CONFIG_PNO_SUPPORT - /* D0_Scan_Offload_Info_0x86 */ - #define SET_H2CCMD_AOAC_NLO_FUN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 3, 1, __Value) - #define SET_H2CCMD_AOAC_NLO_IPS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 4, 1, __Value) - #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) - #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) - #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +/* D0_Scan_Offload_Info_0x86 */ +#define SET_H2CCMD_AOAC_NLO_FUN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 3, 1, __Value) +#define SET_H2CCMD_AOAC_NLO_IPS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 4, 1, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) #endif /* CONFIG_PNO_SUPPORT */ #ifdef CONFIG_P2P_WOWLAN - /* P2P_RsvdPage_0x8a */ - #define SET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) - #define SET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) - #define SET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) - #define SET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) - #define SET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +/* P2P_RsvdPage_0x8a */ +#define SET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) #endif /* CONFIG_P2P_WOWLAN */ #ifdef CONFIG_LPS_PG - #define SET_H2CCMD_LPSPG_SEC_CAM_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*SecurityCAM_En*/ - #define SET_H2CCMD_LPSPG_MBID_CAM_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)/*BSSIDCAM_En*/ - #define SET_H2CCMD_LPSPG_PMC_CAM_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)/*PatternMatchCAM_En*/ - #define SET_H2CCMD_LPSPG_MACID_SEARCH_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)/*MACIDSearch_En*/ - #define SET_H2CCMD_LPSPG_TXSC_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)/*TXSC_En*/ - #define SET_H2CCMD_LPSPG_MU_RATE_TB_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)/*MURateTable_En*/ - #define SET_H2CCMD_LPSPG_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)/*Loc_LPS_PG*/ +#define SET_H2CCMD_LPSPG_SEC_CAM_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*SecurityCAM_En*/ +#define SET_H2CCMD_LPSPG_MBID_CAM_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)/*BSSIDCAM_En*/ +#define SET_H2CCMD_LPSPG_PMC_CAM_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)/*PatternMatchCAM_En*/ +#define SET_H2CCMD_LPSPG_MACID_SEARCH_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)/*MACIDSearch_En*/ +#define SET_H2CCMD_LPSPG_TXSC_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)/*TXSC_En*/ +#define SET_H2CCMD_LPSPG_MU_RATE_TB_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)/*MURateTable_En*/ +#define SET_H2CCMD_LPSPG_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)/*Loc_LPS_PG*/ #endif /* --------------------------------------------------------------------------------------------------------- @@ -443,6 +515,8 @@ typedef struct _RSVDPAGE_LOC { #ifdef CONFIG_GTK_OL u8 LocGTKEXTMEM; #endif /* CONFIG_GTK_OL */ + u8 LocNDPInfo; + u8 LocAOACReport; #ifdef CONFIG_PNO_SUPPORT u8 LocPNOInfo; u8 LocScanInfo; diff --git a/include/hal_com_led.h b/include/hal_com_led.h index 01dbb9c..38ac683 100644 --- a/include/hal_com_led.h +++ b/include/hal_com_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_COMMON_LED_H_ #define __HAL_COMMON_LED_H_ diff --git a/include/hal_com_phycfg.h b/include/hal_com_phycfg.h index 4bb6646..67eec83 100644 --- a/include/hal_com_phycfg.h +++ b/include/hal_com_phycfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_COM_PHYCFG_H__ #define __HAL_COM_PHYCFG_H__ @@ -36,18 +31,6 @@ typedef enum _RF_TX_NUM { #define MAX_POWER_INDEX 0x3F -typedef enum _REGULATION_TXPWR_LMT { - TXPWR_LMT_FCC = 0, - TXPWR_LMT_MKK = 1, - TXPWR_LMT_ETSI = 2, - TXPWR_LMT_WW = 3, - - TXPWR_LMT_MAX_REGULATION_NUM = 4 -} REGULATION_TXPWR_LMT; - -#define TX_PWR_LMT_REF_VHT_FROM_HT BIT0 -#define TX_PWR_LMT_REF_HT_FROM_VHT BIT1 - /*------------------------------Define structure----------------------------*/ typedef struct _BB_REGISTER_DEFINITION { u32 rfintfs; /* set software control: */ @@ -79,19 +62,9 @@ PHY_GetTxPowerByRateBase( IN PADAPTER Adapter, IN u8 Band, IN u8 RfPath, - IN u8 TxNum, IN RATE_SECTION RateSection ); -#ifdef TX_POWER_BY_RATE_OLD -u8 -PHY_GetRateSectionIndexOfTxPowerByRate( - IN PADAPTER pAdapter, - IN u32 RegAddr, - IN u32 BitMask -); -#endif /* TX_POWER_BY_RATE_OLD */ - VOID PHY_GetRateValuesOfTxPowerByRate( IN PADAPTER pAdapter, @@ -109,7 +82,7 @@ PHY_GetRateIndexOfTxPowerByRate( ); VOID -PHY_SetTxPowerIndexByRateSection( +phy_set_tx_power_index_by_rate_section( IN PADAPTER pAdapter, IN u8 RFPath, IN u8 Channel, @@ -121,7 +94,6 @@ _PHY_GetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, IN u8 RFPath, - IN u8 TxNum, IN u8 RateIndex ); @@ -130,33 +102,20 @@ PHY_GetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, IN u8 RFPath, - IN u8 TxNum, IN u8 RateIndex ); -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI -s8 -PHY_GetTxPowerByRateOriginal( - IN PADAPTER pAdapter, - IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, - IN u8 Rate -); -#endif - VOID PHY_SetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, IN u8 RFPath, - IN u8 TxNum, IN u8 Rate, IN s8 Value ); VOID -PHY_SetTxPowerLevelByPath( +phy_set_tx_power_level_by_path( IN PADAPTER Adapter, IN u8 channel, IN u8 path @@ -178,7 +137,7 @@ PHY_InitTxPowerByRate( ); VOID -PHY_StoreTxPowerByRate( +phy_store_tx_power_by_rate( IN PADAPTER pAdapter, IN u32 Band, IN u32 RfPath, @@ -198,54 +157,54 @@ PHY_GetTxPowerIndexBase( IN PADAPTER pAdapter, IN u8 RFPath, IN u8 Rate, + u8 ntx_idx, IN CHANNEL_WIDTH BandWidth, IN u8 Channel, OUT PBOOLEAN bIn24G ); -s8 -PHY_GetTxPowerLimit( - IN PADAPTER Adapter, - IN u32 RegPwrTblSel, - IN BAND_TYPE Band, - IN CHANNEL_WIDTH Bandwidth, - IN u8 RfPath, - IN u8 DataRate, - IN u8 Channel +#ifdef CONFIG_TXPWR_LIMIT +s8 phy_get_txpwr_lmt_abs(_adapter *adapter + , const char *regd_name + , BAND_TYPE band, CHANNEL_WIDTH bw + , u8 tlrs, u8 ntx_idx, u8 cch, u8 lock ); -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI -s8 -PHY_GetTxPowerLimitOriginal( - IN PADAPTER Adapter, - IN u32 RegPwrTblSel, - IN BAND_TYPE Band, - IN CHANNEL_WIDTH Bandwidth, - IN u8 RfPath, - IN u8 DataRate, - IN u8 Channel -); -#endif - -VOID -PHY_ConvertTxPowerLimitToPowerIndex( - IN PADAPTER Adapter +s8 phy_get_txpwr_lmt(_adapter *adapter + , const char *regd_name + , BAND_TYPE band, CHANNEL_WIDTH bw + , u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock ); -VOID -PHY_InitTxPowerLimit( - IN PADAPTER Adapter +s8 PHY_GetTxPowerLimit(_adapter *adapter + , const char *regd_name + , BAND_TYPE band, CHANNEL_WIDTH bw + , u8 rfpath, u8 rate, u8 ntx_idx, u8 cch ); +#else +#define phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock) MAX_POWER_INDEX +#define phy_get_txpwr_lmt(adapter, regd_name, band, bw, rfpath, rs, ntx_idx, cch, lock) MAX_POWER_INDEX +#define PHY_GetTxPowerLimit(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch) MAX_POWER_INDEX +#endif /* CONFIG_TXPWR_LIMIT */ s8 PHY_GetTxPowerTrackingOffset( PADAPTER pAdapter, - u8 Rate, - u8 RFPath + u8 RFPath, + u8 Rate ); +struct txpwr_idx_comp { + u8 ntx_idx; + u8 base; + s8 by_rate; + s8 limit; + s8 tpt; + s8 ebias; +}; + u8 -PHY_GetTxPowerIndex( +phy_get_tx_power_index( IN PADAPTER pAdapter, IN u8 RFPath, IN u8 Rate, @@ -261,48 +220,78 @@ PHY_SetTxPowerIndex( IN u8 Rate ); +void dump_tx_power_idx_title(void *sel, _adapter *adapter); +void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs); +void dump_tx_power_idx(void *sel, _adapter *adapter); + bool phy_is_tx_power_limit_needed(_adapter *adapter); bool phy_is_tx_power_by_rate_needed(_adapter *adapter); -int phy_load_tx_power_by_rate(_adapter *adapter, const char *hal_file_name, u8 force); -int phy_load_tx_power_limit(_adapter *adapter, const char *hal_file_name, u8 force); -void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file, u8 force); +int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file); +#ifdef CONFIG_TXPWR_LIMIT +int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file); +#endif +void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file); void phy_reload_tx_power_ext_info(_adapter *adapter); void phy_reload_default_tx_power_ext_info(_adapter *adapter); +const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter); + +void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt); +void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt); + +void hal_load_txpwr_info( + _adapter *adapter, + TxPowerInfo24G *pwr_info_2g, + TxPowerInfo5G *pwr_info_5g, + u8 *pg_data +); + void dump_tx_power_ext_info(void *sel, _adapter *adapter); void dump_target_tx_power(void *sel, _adapter *adapter); void dump_tx_power_by_rate(void *sel, _adapter *adapter); -void dump_tx_power_limit(void *sel, _adapter *adapter); -int rtw_is_phy_file_readable(const char *hal_file_name); +int rtw_get_phy_file_path(_adapter *adapter, const char *file_name); #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE - #define MAX_PARA_FILE_BUF_LEN 25600 - - #define LOAD_MAC_PARA_FILE BIT0 - #define LOAD_BB_PARA_FILE BIT1 - #define LOAD_BB_PG_PARA_FILE BIT2 - #define LOAD_BB_MP_PARA_FILE BIT3 - #define LOAD_RF_PARA_FILE BIT4 - #define LOAD_RF_TXPWR_TRACK_PARA_FILE BIT5 - #define LOAD_RF_TXPWR_LMT_PARA_FILE BIT6 - - int phy_ConfigMACWithParaFile(IN PADAPTER Adapter, IN char *pFileName); - - int phy_ConfigBBWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN u32 ConfigType); - - int phy_ConfigBBWithPgParaFile(IN PADAPTER Adapter, IN const char *pFileName); - - int phy_ConfigBBWithMpParaFile(IN PADAPTER Adapter, IN char *pFileName); - - int PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN u8 eRFPath); - - int PHY_ConfigRFWithTxPwrTrackParaFile(IN PADAPTER Adapter, IN char *pFileName); - - int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER Adapter, IN const char *pFileName); - - void phy_free_filebuf_mask(_adapter *padapter, u8 mask); - void phy_free_filebuf(_adapter *padapter); +#define MAC_FILE_FW_NIC "FW_NIC.bin" +#define MAC_FILE_FW_WW_IMG "FW_WoWLAN.bin" +#define PHY_FILE_MAC_REG "MAC_REG.txt" + +#define PHY_FILE_AGC_TAB "AGC_TAB.txt" +#define PHY_FILE_PHY_REG "PHY_REG.txt" +#define PHY_FILE_PHY_REG_MP "PHY_REG_MP.txt" +#define PHY_FILE_PHY_REG_PG "PHY_REG_PG.txt" + +#define PHY_FILE_RADIO_A "RadioA.txt" +#define PHY_FILE_RADIO_B "RadioB.txt" +#define PHY_FILE_RADIO_C "RadioC.txt" +#define PHY_FILE_RADIO_D "RadioD.txt" +#define PHY_FILE_TXPWR_TRACK "TxPowerTrack.txt" +#define PHY_FILE_TXPWR_LMT "TXPWR_LMT.txt" + +#define PHY_FILE_WIFI_ANT_ISOLATION "wifi_ant_isolation.txt" + +#define MAX_PARA_FILE_BUF_LEN 25600 + +#define LOAD_MAC_PARA_FILE BIT0 +#define LOAD_BB_PARA_FILE BIT1 +#define LOAD_BB_PG_PARA_FILE BIT2 +#define LOAD_BB_MP_PARA_FILE BIT3 +#define LOAD_RF_PARA_FILE BIT4 +#define LOAD_RF_TXPWR_TRACK_PARA_FILE BIT5 +#define LOAD_RF_TXPWR_LMT_PARA_FILE BIT6 + +int phy_ConfigMACWithParaFile(IN PADAPTER Adapter, IN char *pFileName); +int phy_ConfigBBWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN u32 ConfigType); +int phy_ConfigBBWithPgParaFile(IN PADAPTER Adapter, IN const char *pFileName); +int phy_ConfigBBWithMpParaFile(IN PADAPTER Adapter, IN char *pFileName); +int PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN u8 eRFPath); +int PHY_ConfigRFWithTxPwrTrackParaFile(IN PADAPTER Adapter, IN char *pFileName); +#ifdef CONFIG_TXPWR_LIMIT +int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER Adapter, IN const char *pFileName); +#endif +void phy_free_filebuf_mask(_adapter *padapter, u8 mask); +void phy_free_filebuf(_adapter *padapter); #endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */ #endif /* __HAL_COMMON_H__ */ diff --git a/include/hal_com_reg.h b/include/hal_com_reg.h index eba2e9e..71990e7 100644 --- a/include/hal_com_reg.h +++ b/include/hal_com_reg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_COMMON_REG_H__ #define __HAL_COMMON_REG_H__ @@ -31,691 +26,693 @@ #define DISABLE_TRXPKT_BUF_ACCESS 0x0 #ifndef RTW_HALMAC - /* ************************************************************ - * - * ************************************************************ */ - - /* ----------------------------------------------------- - * - * 0x0000h ~ 0x00FFh System Configuration - * - * ----------------------------------------------------- */ - #define REG_SYS_ISO_CTRL 0x0000 - #define REG_SYS_FUNC_EN 0x0002 - #define REG_APS_FSMCO 0x0004 - #define REG_SYS_CLKR 0x0008 - #define REG_SYS_CLK_CTRL REG_SYS_CLKR - #define REG_9346CR 0x000A - #define REG_SYS_EEPROM_CTRL 0x000A - #define REG_EE_VPD 0x000C - #define REG_AFE_MISC 0x0010 - #define REG_SPS0_CTRL 0x0011 - #define REG_SPS0_CTRL_6 0x0016 - #define REG_POWER_OFF_IN_PROCESS 0x0017 - #define REG_SPS_OCP_CFG 0x0018 - #define REG_RSV_CTRL 0x001C - #define REG_RF_CTRL 0x001F - #define REG_LDOA15_CTRL 0x0020 - #define REG_LDOV12D_CTRL 0x0021 - #define REG_LDOHCI12_CTRL 0x0022 - #define REG_LPLDO_CTRL 0x0023 - #define REG_AFE_XTAL_CTRL 0x0024 - #define REG_AFE_LDO_CTRL 0x0027 /* 1.5v for 8188EE test chip, 1.4v for MP chip */ - #define REG_AFE_PLL_CTRL 0x0028 - #define REG_MAC_PHY_CTRL 0x002c /* for 92d, DMDP, SMSP, DMSP contrl */ - #define REG_APE_PLL_CTRL_EXT 0x002c - #define REG_EFUSE_CTRL 0x0030 - #define REG_EFUSE_TEST 0x0034 - #define REG_PWR_DATA 0x0038 - #define REG_CAL_TIMER 0x003C - #define REG_ACLK_MON 0x003E - #define REG_GPIO_MUXCFG 0x0040 - #define REG_GPIO_IO_SEL 0x0042 - #define REG_MAC_PINMUX_CFG 0x0043 - #define REG_GPIO_PIN_CTRL 0x0044 - #define REG_GPIO_INTM 0x0048 - #define REG_LEDCFG0 0x004C - #define REG_LEDCFG1 0x004D - #define REG_LEDCFG2 0x004E - #define REG_LEDCFG3 0x004F - #define REG_FSIMR 0x0050 - #define REG_FSISR 0x0054 - #define REG_HSIMR 0x0058 - #define REG_HSISR 0x005c - #define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ - #define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ - #define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */ - #define REG_GSSR 0x006c - #define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */ - #define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */ - #define REG_MCUFWDL 0x0080 - #define REG_WOL_EVENT 0x0081 /* RTL8188E */ - #define REG_MCUTSTCFG 0x0084 - #define REG_FDHM0 0x0088 - #define REG_HOST_SUSP_CNT 0x00BC /* RTL8192C Host suspend counter on FPGA platform */ - #define REG_SYSTEM_ON_CTRL 0x00CC /* For 8723AE Reset after S3 */ - #define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection for RTL8723 */ - #define REG_BIST_SCAN 0x00D0 - #define REG_BIST_RPT 0x00D4 - #define REG_BIST_ROM_RPT 0x00D8 - #define REG_USB_SIE_INTF 0x00E0 - #define REG_PCIE_MIO_INTF 0x00E4 - #define REG_PCIE_MIO_INTD 0x00E8 - #define REG_HPON_FSM 0x00EC - #define REG_SYS_CFG 0x00F0 - #define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ - #define REG_TYPE_ID 0x00FC - - /* - * 2010/12/29 MH Add for 92D - * */ - #define REG_MAC_PHY_CTRL_NORMAL 0x00f8 - - - /* ----------------------------------------------------- - * - * 0x0100h ~ 0x01FFh MACTOP General Configuration - * - * ----------------------------------------------------- */ - #define REG_CR 0x0100 - #define REG_PBP 0x0104 - #define REG_PKT_BUFF_ACCESS_CTRL 0x0106 - #define REG_TRXDMA_CTRL 0x010C - #define REG_TRXFF_BNDY 0x0114 - #define REG_TRXFF_STATUS 0x0118 - #define REG_RXFF_PTR 0x011C - #define REG_HIMR 0x0120 - #define REG_HISR 0x0124 - #define REG_HIMRE 0x0128 - #define REG_HISRE 0x012C - #define REG_CPWM 0x012F - #define REG_FWIMR 0x0130 - #define REG_FWISR 0x0134 - #define REG_FTIMR 0x0138 - #define REG_FTISR 0x013C /* RTL8192C */ - #define REG_PKTBUF_DBG_CTRL 0x0140 - #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) - #define REG_PKTBUF_DBG_DATA_L 0x0144 - #define REG_PKTBUF_DBG_DATA_H 0x0148 - - #define REG_TC0_CTRL 0x0150 - #define REG_TC1_CTRL 0x0154 - #define REG_TC2_CTRL 0x0158 - #define REG_TC3_CTRL 0x015C - #define REG_TC4_CTRL 0x0160 - #define REG_TCUNIT_BASE 0x0164 - #define REG_MBIST_START 0x0174 - #define REG_MBIST_DONE 0x0178 - #define REG_MBIST_FAIL 0x017C - #define REG_32K_CTRL 0x0194 /* RTL8188E */ - #define REG_C2HEVT_MSG_NORMAL 0x01A0 - #define REG_C2HEVT_CLEAR 0x01AF - #define REG_MCUTST_1 0x01c0 - #define REG_MCUTST_WOWLAN 0x01C7 /* Defined after 8188E series. */ - #define REG_FMETHR 0x01C8 - #define REG_HMETFR 0x01CC - #define REG_HMEBOX_0 0x01D0 - #define REG_HMEBOX_1 0x01D4 - #define REG_HMEBOX_2 0x01D8 - #define REG_HMEBOX_3 0x01DC - #define REG_LLT_INIT 0x01E0 - #define REG_HMEBOX_EXT_0 0x01F0 - #define REG_HMEBOX_EXT_1 0x01F4 - #define REG_HMEBOX_EXT_2 0x01F8 - #define REG_HMEBOX_EXT_3 0x01FC - - - /* ----------------------------------------------------- - * - * 0x0200h ~ 0x027Fh TXDMA Configuration - * - * ----------------------------------------------------- */ - #define REG_RQPN 0x0200 - #define REG_FIFOPAGE 0x0204 - #define REG_TDECTRL 0x0208 - #define REG_TXDMA_OFFSET_CHK 0x020C - #define REG_TXDMA_STATUS 0x0210 - #define REG_RQPN_NPQ 0x0214 - #define REG_AUTO_LLT 0x0224 - - - /* ----------------------------------------------------- - * - * 0x0280h ~ 0x02FFh RXDMA Configuration - * - * ----------------------------------------------------- */ - #define REG_RXDMA_AGG_PG_TH 0x0280 - #define REG_RXPKT_NUM 0x0284 - #define REG_RXDMA_STATUS 0x0288 - - /* ----------------------------------------------------- - * - * 0x0300h ~ 0x03FFh PCIe - * - * ----------------------------------------------------- */ - #ifndef CONFIG_TRX_BD_ARCH /* prevent CONFIG_TRX_BD_ARCH to use old registers */ - - #define REG_PCIE_CTRL_REG 0x0300 - #define REG_INT_MIG 0x0304 /* Interrupt Migration */ - #define REG_BCNQ_DESA 0x0308 /* TX Beacon Descriptor Address */ - #define REG_HQ_DESA 0x0310 /* TX High Queue Descriptor Address */ - #define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descriptor Address */ - #define REG_VOQ_DESA 0x0320 /* TX VO Queue Descriptor Address */ - #define REG_VIQ_DESA 0x0328 /* TX VI Queue Descriptor Address */ - #define REG_BEQ_DESA 0x0330 /* TX BE Queue Descriptor Address */ - #define REG_BKQ_DESA 0x0338 /* TX BK Queue Descriptor Address */ - #define REG_RX_DESA 0x0340 /* RX Queue Descriptor Address */ - /* sherry added for DBI Read/Write 20091126 */ - #define REG_DBI_WDATA 0x0348 /* Backdoor REG for Access Configuration */ - #define REG_DBI_RDATA 0x034C /* Backdoor REG for Access Configuration */ - #define REG_DBI_CTRL 0x0350 /* Backdoor REG for Access Configuration */ - #define REG_DBI_FLAG 0x0352 /* Backdoor REG for Access Configuration */ - #define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ - #define REG_DBG_SEL 0x0360 /* Debug Selection Register */ - #define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ - #define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ - #define REG_WATCH_DOG 0x0368 - #define REG_RX_RXBD_NUM 0x0382 - - /* RTL8723 series ------------------------------- */ - #define REG_PCIE_HISR_EN 0x0394 /* PCIE Local Interrupt Enable Register */ - #define REG_PCIE_HISR 0x03A0 - #define REG_PCIE_HISRE 0x03A4 - #define REG_PCIE_HIMR 0x03A8 - #define REG_PCIE_HIMRE 0x03AC - - #endif /* !CONFIG_TRX_BD_ARCH */ - - #define REG_USB_HIMR 0xFE38 - #define REG_USB_HIMRE 0xFE3C - #define REG_USB_HISR 0xFE78 - #define REG_USB_HISRE 0xFE7C - - - /* ----------------------------------------------------- - * - * 0x0400h ~ 0x047Fh Protocol Configuration - * - * ----------------------------------------------------- */ - - /* 92C, 92D */ - #define REG_VOQ_INFO 0x0400 - #define REG_VIQ_INFO 0x0404 - #define REG_BEQ_INFO 0x0408 - #define REG_BKQ_INFO 0x040C - - /* 88E, 8723A, 8812A, 8821A, 92E, 8723B */ - #define REG_Q0_INFO 0x400 - #define REG_Q1_INFO 0x404 - #define REG_Q2_INFO 0x408 - #define REG_Q3_INFO 0x40C - - #define REG_MGQ_INFO 0x0410 - #define REG_HGQ_INFO 0x0414 - #define REG_BCNQ_INFO 0x0418 - #define REG_TXPKT_EMPTY 0x041A - #define REG_CPU_MGQ_INFORMATION 0x041C - #define REG_FWHW_TXQ_CTRL 0x0420 - #define REG_HWSEQ_CTRL 0x0423 - #define REG_BCNQ_BDNY 0x0424 - #define REG_MGQ_BDNY 0x0425 - #define REG_LIFETIME_CTRL 0x0426 - #define REG_MULTI_BCNQ_OFFSET 0x0427 - #define REG_SPEC_SIFS 0x0428 - #define REG_RL 0x042A - #define REG_DARFRC 0x0430 - #define REG_RARFRC 0x0438 - #define REG_RRSR 0x0440 - #define REG_ARFR0 0x0444 - #define REG_ARFR1 0x0448 - #define REG_ARFR2 0x044C - #define REG_ARFR3 0x0450 - #define REG_CCK_CHECK 0x0454 - #define REG_BCNQ1_BDNY 0x0457 - - #define REG_AGGLEN_LMT 0x0458 - #define REG_AMPDU_MIN_SPACE 0x045C - #define REG_WMAC_LBK_BF_HD 0x045D - #define REG_FAST_EDCA_CTRL 0x0460 - #define REG_RD_RESP_PKT_TH 0x0463 - - /* 8723A, 8812A, 8821A, 92E, 8723B */ - #define REG_Q4_INFO 0x468 - #define REG_Q5_INFO 0x46C - #define REG_Q6_INFO 0x470 - #define REG_Q7_INFO 0x474 - - #define REG_INIRTS_RATE_SEL 0x0480 - #define REG_INIDATA_RATE_SEL 0x0484 - - /* 8723B, 92E, 8812A, 8821A*/ - #define REG_MACID_SLEEP_3 0x0484 - #define REG_MACID_SLEEP_1 0x0488 - - #define REG_POWER_STAGE1 0x04B4 - #define REG_POWER_STAGE2 0x04B8 - #define REG_PKT_VO_VI_LIFE_TIME 0x04C0 - #define REG_PKT_BE_BK_LIFE_TIME 0x04C2 - #define REG_STBC_SETTING 0x04C4 - #define REG_QUEUE_CTRL 0x04C6 - #define REG_SINGLE_AMPDU_CTRL 0x04c7 - #define REG_PROT_MODE_CTRL 0x04C8 - #define REG_MAX_AGGR_NUM 0x04CA - #define REG_RTS_MAX_AGGR_NUM 0x04CB - #define REG_BAR_MODE_CTRL 0x04CC - #define REG_RA_TRY_RATE_AGG_LMT 0x04CF - - /* 8723A */ - #define REG_MACID_DROP 0x04D0 - - /* 88E */ - #define REG_EARLY_MODE_CONTROL 0x04D0 - - /* 8723B, 92E, 8812A, 8821A */ - #define REG_MACID_SLEEP_2 0x04D0 - - /* 8723A, 8723B, 92E, 8812A, 8821A */ - #define REG_MACID_SLEEP 0x04D4 - - #define REG_NQOS_SEQ 0x04DC - #define REG_QOS_SEQ 0x04DE - #define REG_NEED_CPU_HANDLE 0x04E0 - #define REG_PKT_LOSE_RPT 0x04E1 - #define REG_PTCL_ERR_STATUS 0x04E2 - #define REG_TX_RPT_CTRL 0x04EC - #define REG_TX_RPT_TIME 0x04F0 /* 2 byte */ - #define REG_DUMMY 0x04FC - - /* ----------------------------------------------------- - * - * 0x0500h ~ 0x05FFh EDCA Configuration - * - * ----------------------------------------------------- */ - #define REG_EDCA_VO_PARAM 0x0500 - #define REG_EDCA_VI_PARAM 0x0504 - #define REG_EDCA_BE_PARAM 0x0508 - #define REG_EDCA_BK_PARAM 0x050C - #define REG_BCNTCFG 0x0510 - #define REG_PIFS 0x0512 - #define REG_RDG_PIFS 0x0513 - #define REG_SIFS_CTX 0x0514 - #define REG_SIFS_TRX 0x0516 - #define REG_TSFTR_SYN_OFFSET 0x0518 - #define REG_AGGR_BREAK_TIME 0x051A - #define REG_SLOT 0x051B - #define REG_TX_PTCL_CTRL 0x0520 - #define REG_TXPAUSE 0x0522 - #define REG_DIS_TXREQ_CLR 0x0523 - #define REG_RD_CTRL 0x0524 - /* - * Format for offset 540h-542h: - * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. - * [7:4]: Reserved. - * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. - * [23:20]: Reserved - * Description: - * | - * |<--Setup--|--Hold------------>| - * --------------|---------------------- - * | - * TBTT - * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. - * Described by Designer Tim and Bruce, 2011-01-14. - * */ - #define REG_TBTT_PROHIBIT 0x0540 - #define REG_RD_NAV_NXT 0x0544 - #define REG_NAV_PROT_LEN 0x0546 - #define REG_BCN_CTRL 0x0550 - #define REG_BCN_CTRL_1 0x0551 - #define REG_MBID_NUM 0x0552 - #define REG_DUAL_TSF_RST 0x0553 - #define REG_BCN_INTERVAL 0x0554 /* The same as REG_MBSSID_BCN_SPACE */ - #define REG_DRVERLYINT 0x0558 - #define REG_BCNDMATIM 0x0559 - #define REG_ATIMWND 0x055A - #define REG_USTIME_TSF 0x055C - #define REG_BCN_MAX_ERR 0x055D - #define REG_RXTSF_OFFSET_CCK 0x055E - #define REG_RXTSF_OFFSET_OFDM 0x055F - #define REG_TSFTR 0x0560 - #define REG_TSFTR1 0x0568 /* HW Port 1 TSF Register */ - #define REG_ATIMWND_1 0x0570 - #define REG_P2P_CTWIN 0x0572 /* 1 Byte long (in unit of TU) */ - #define REG_PSTIMER 0x0580 - #define REG_TIMER0 0x0584 - #define REG_TIMER1 0x0588 - #define REG_ACMHWCTRL 0x05C0 - #define REG_NOA_DESC_SEL 0x05CF - #define REG_NOA_DESC_DURATION 0x05E0 - #define REG_NOA_DESC_INTERVAL 0x05E4 - #define REG_NOA_DESC_START 0x05E8 - #define REG_NOA_DESC_COUNT 0x05EC - - #define REG_DMC 0x05F0 /* Dual MAC Co-Existence Register */ - #define REG_SCH_TX_CMD 0x05F8 - - #define REG_FW_RESET_TSF_CNT_1 0x05FC - #define REG_FW_RESET_TSF_CNT_0 0x05FD - #define REG_FW_BCN_DIS_CNT 0x05FE - - /* ----------------------------------------------------- - * - * 0x0600h ~ 0x07FFh WMAC Configuration - * - * ----------------------------------------------------- */ - #define REG_APSD_CTRL 0x0600 - #define REG_BWOPMODE 0x0603 - #define REG_TCR 0x0604 - #define REG_RCR 0x0608 - #define REG_RX_PKT_LIMIT 0x060C - #define REG_RX_DLK_TIME 0x060D - #define REG_RX_DRVINFO_SZ 0x060F - - #define REG_MACID 0x0610 - #define REG_BSSID 0x0618 - #define REG_MAR 0x0620 - #define REG_MBIDCAMCFG_1 0x0628 - #define REG_MBIDCAMCFG_2 0x062C - - #define REG_PNO_STATUS 0x0631 - #define REG_USTIME_EDCA 0x0638 - #define REG_MAC_SPEC_SIFS 0x063A - /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ - #define REG_RESP_SIFS_CCK 0x063C /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ - #define REG_RESP_SIFS_OFDM 0x063E /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ - - #define REG_ACKTO 0x0640 - #define REG_CTS2TO 0x0641 - #define REG_EIFS 0x0642 - - - /* RXERR_RPT */ - #define RXERR_TYPE_OFDM_PPDU 0 - #define RXERR_TYPE_OFDM_FALSE_ALARM 1 - #define RXERR_TYPE_OFDM_MPDU_OK 2 - #define RXERR_TYPE_OFDM_MPDU_FAIL 3 - #define RXERR_TYPE_CCK_PPDU 4 - #define RXERR_TYPE_CCK_FALSE_ALARM 5 - #define RXERR_TYPE_CCK_MPDU_OK 6 - #define RXERR_TYPE_CCK_MPDU_FAIL 7 - #define RXERR_TYPE_HT_PPDU 8 - #define RXERR_TYPE_HT_FALSE_ALARM 9 - #define RXERR_TYPE_HT_MPDU_TOTAL 10 - #define RXERR_TYPE_HT_MPDU_OK 11 - #define RXERR_TYPE_HT_MPDU_FAIL 12 - #define RXERR_TYPE_RX_FULL_DROP 15 - - #define RXERR_COUNTER_MASK 0xFFFFF - #define RXERR_RPT_RST BIT(27) - #define _RXERR_RPT_SEL(type) ((type) << 28) - - /* - * Note: - * The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is - * always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending - * CTS in the air. We must update this value greater than 25,000 microseconds to pass the item. - * The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented - * by SD1 Scott. - * By Bruce, 2011-07-18. - * */ - #define REG_NAV_UPPER 0x0652 /* unit of 128 */ - - /* WMA, BA, CCX */ - #define REG_NAV_CTRL 0x0650 - #define REG_BACAMCMD 0x0654 - #define REG_BACAMCONTENT 0x0658 - #define REG_LBDLY 0x0660 - #define REG_FWDLY 0x0661 - #define REG_RXERR_RPT 0x0664 - #define REG_WMAC_TRXPTCL_CTL 0x0668 - - /* Security */ - #define REG_CAMCMD 0x0670 - #define REG_CAMWRITE 0x0674 - #define REG_CAMREAD 0x0678 - #define REG_CAMDBG 0x067C - #define REG_SECCFG 0x0680 - - /* Power */ - #define REG_WOW_CTRL 0x0690 - #define REG_PS_RX_INFO 0x0692 - #define REG_UAPSD_TID 0x0693 - #define REG_WKFMCAM_CMD 0x0698 - #define REG_WKFMCAM_NUM REG_WKFMCAM_CMD - #define REG_WKFMCAM_RWD 0x069C - #define REG_RXFLTMAP0 0x06A0 - #define REG_RXFLTMAP1 0x06A2 - #define REG_RXFLTMAP2 0x06A4 - #define REG_BCN_PSR_RPT 0x06A8 - #define REG_BT_COEX_TABLE 0x06C0 - - /* Hardware Port 1 */ - #define REG_MACID1 0x0700 - #define REG_BSSID1 0x0708 - /* Hardware Port 2 */ - #define REG_MACID2 0x1620 - #define REG_BSSID2 0x1628 - /* Hardware Port 3*/ - #define REG_MACID3 0x1630 - #define REG_BSSID3 0x1638 - /* Hardware Port 4 */ - #define REG_MACID4 0x1640 - #define REG_BSSID4 0x1648 - - - #define REG_CR_EXT 0x1100 - - /* ----------------------------------------------------- - * - * 0xFE00h ~ 0xFE55h USB Configuration - * - * ----------------------------------------------------- */ - #define REG_USB_INFO 0xFE17 - #define REG_USB_SPECIAL_OPTION 0xFE55 - #define REG_USB_DMA_AGG_TO 0xFE5B - #define REG_USB_AGG_TO 0xFE5C - #define REG_USB_AGG_TH 0xFE5D - - #define REG_USB_HRPWM 0xFE58 - #define REG_USB_HCPWM 0xFE57 - - /* for 92DU high_Queue low_Queue Normal_Queue select */ - #define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44 - /* #define REG_USB_LOW_Queue_Select_MAC0 0xFE45 */ - #define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47 - /* #define REG_USB_LOW_Queue_Select_MAC1 0xFE48 */ - - /* For test chip */ - #define REG_TEST_USB_TXQS 0xFE48 - #define REG_TEST_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ - #define REG_TEST_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ - #define REG_TEST_SIE_OPTIONAL 0xFE64 - #define REG_TEST_SIE_CHIRP_K 0xFE65 - #define REG_TEST_SIE_PHY 0xFE66 /* 0xFE66~0xFE6B */ - #define REG_TEST_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ - #define REG_TEST_SIE_STRING 0xFE80 /* 0xFE80~0xFEB9 */ - - - /* For normal chip */ - #define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ - #define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ - #define REG_NORMAL_SIE_OPTIONAL 0xFE64 - #define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ - #define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ - #define REG_NORMAL_SIE_OPTIONAL2 0xFE6C - #define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */ - #define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ - #define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ - - - /* ----------------------------------------------------- - * - * Redifine 8192C register definition for compatibility - * - * ----------------------------------------------------- */ - - /* TODO: use these definition when using REG_xxx naming rule. - * NOTE: DO NOT Remove these definition. Use later. */ - - #define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ - #define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */ - #define MSR (REG_CR + 2) /* Media Status register - * #define ISR REG_HISR */ - #define MSR1 REG_CR_EXT - - #define TSFR REG_TSFTR /* Timing Sync Function Timer Register. */ - #define TSFR1 REG_TSFTR1 /* HW Port 1 TSF Register */ - - #define PBP REG_PBP - - /* Redifine MACID register, to compatible prior ICs. */ - #define IDR0 REG_MACID /* MAC ID Register, Offset 0x0050-0x0053 */ - #define IDR4 (REG_MACID + 4) /* MAC ID Register, Offset 0x0054-0x0055 */ - - - /* - * 9. Security Control Registers (Offset: ) - * */ - #define RWCAM REG_CAMCMD /* IN 8190 Data Sheet is called CAMcmd */ - #define WCAMI REG_CAMWRITE /* Software write CAM input content */ - #define RCAMO REG_CAMREAD /* Software read/write CAM config */ - #define CAMDBG REG_CAMDBG - #define SECR REG_SECCFG /* Security Configuration Register */ - - /* Unused register */ - #define UnusedRegister 0x1BF - #define DCAM UnusedRegister - #define PSR UnusedRegister - #define BBAddr UnusedRegister - #define PhyDataR UnusedRegister - - /* Min Spacing related settings. */ - #define MAX_MSS_DENSITY_2T 0x13 - #define MAX_MSS_DENSITY_1T 0x0A - - /* ---------------------------------------------------------------------------- - * 8192C Cmd9346CR bits (Offset 0xA, 16bit) - * ---------------------------------------------------------------------------- */ - #define CmdEEPROM_En BIT5 /* EEPROM enable when set 1 */ - #define CmdEERPOMSEL BIT4 /* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */ - #define Cmd9346CR_9356SEL BIT4 - - /* ---------------------------------------------------------------------------- - * 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) - * ---------------------------------------------------------------------------- */ - #define GPIOSEL_GPIO 0 - #define GPIOSEL_ENBT BIT5 - - /* ---------------------------------------------------------------------------- - * 8192C GPIO PIN Control Register (offset 0x44, 4 byte) - * ---------------------------------------------------------------------------- */ - #define GPIO_IN REG_GPIO_PIN_CTRL /* GPIO pins input value */ - #define GPIO_OUT (REG_GPIO_PIN_CTRL+1) /* GPIO pins output value */ - #define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) /* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */ - #define GPIO_MOD (REG_GPIO_PIN_CTRL+3) - - /* ---------------------------------------------------------------------------- - * 8811A GPIO PIN Control Register (offset 0x60, 4 byte) - * ---------------------------------------------------------------------------- */ - #define GPIO_IN_8811A REG_GPIO_PIN_CTRL_2 /* GPIO pins input value */ - #define GPIO_OUT_8811A (REG_GPIO_PIN_CTRL_2+1) /* GPIO pins output value */ - #define GPIO_IO_SEL_8811A (REG_GPIO_PIN_CTRL_2+2) /* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */ - #define GPIO_MOD_8811A (REG_GPIO_PIN_CTRL_2+3) - - /* ---------------------------------------------------------------------------- - * 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) - * ---------------------------------------------------------------------------- */ - #define HSIMR_GPIO12_0_INT_EN BIT0 - #define HSIMR_SPS_OCP_INT_EN BIT5 - #define HSIMR_RON_INT_EN BIT6 - #define HSIMR_PDN_INT_EN BIT7 - #define HSIMR_GPIO9_INT_EN BIT25 - - /* ---------------------------------------------------------------------------- - * 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) - * ---------------------------------------------------------------------------- */ - #define HSISR_GPIO12_0_INT BIT0 - #define HSISR_SPS_OCP_INT BIT5 - #define HSISR_RON_INT BIT6 - #define HSISR_PDNINT BIT7 - #define HSISR_GPIO9_INT BIT25 - - /* ---------------------------------------------------------------------------- - * 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) - * ---------------------------------------------------------------------------- - * - Network Type - 00: No link - 01: Link in ad hoc network - 10: Link in infrastructure network - 11: AP mode - Default: 00b. - */ - #define MSR_NOLINK 0x00 - #define MSR_ADHOC 0x01 - #define MSR_INFRA 0x02 - #define MSR_AP 0x03 - - /* ---------------------------------------------------------------------------- - * USB INTR CONTENT - * ---------------------------------------------------------------------------- */ - #define USB_C2H_CMDID_OFFSET 0 - #define USB_C2H_SEQ_OFFSET 1 - #define USB_C2H_EVENT_OFFSET 2 - #define USB_INTR_CPWM_OFFSET 16 - #define USB_INTR_CONTENT_C2H_OFFSET 0 - #define USB_INTR_CONTENT_CPWM1_OFFSET 16 - #define USB_INTR_CONTENT_CPWM2_OFFSET 20 - #define USB_INTR_CONTENT_HISR_OFFSET 48 - #define USB_INTR_CONTENT_HISRE_OFFSET 52 - #define USB_INTR_CONTENT_LENGTH 56 - - /* ---------------------------------------------------------------------------- - * Response Rate Set Register (offset 0x440, 24bits) - * ---------------------------------------------------------------------------- */ - #define RRSR_1M BIT0 - #define RRSR_2M BIT1 - #define RRSR_5_5M BIT2 - #define RRSR_11M BIT3 - #define RRSR_6M BIT4 - #define RRSR_9M BIT5 - #define RRSR_12M BIT6 - #define RRSR_18M BIT7 - #define RRSR_24M BIT8 - #define RRSR_36M BIT9 - #define RRSR_48M BIT10 - #define RRSR_54M BIT11 - #define RRSR_MCS0 BIT12 - #define RRSR_MCS1 BIT13 - #define RRSR_MCS2 BIT14 - #define RRSR_MCS3 BIT15 - #define RRSR_MCS4 BIT16 - #define RRSR_MCS5 BIT17 - #define RRSR_MCS6 BIT18 - #define RRSR_MCS7 BIT19 - - #define RRSR_CCK_RATES (RRSR_11M | RRSR_5_5M | RRSR_2M | RRSR_1M) - #define RRSR_OFDM_RATES (RRSR_54M | RRSR_48M | RRSR_36M | RRSR_24M | RRSR_18M | RRSR_12M | RRSR_9M | RRSR_6M) - - /* WOL bit information */ - #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 - #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 - #define HAL92C_WOL_DISASSOC_EVENT BIT2 - #define HAL92C_WOL_DEAUTH_EVENT BIT3 - #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT4 - - - /*---------------------------------------------------------------------------- - ** REG_CCK_CHECK (offset 0x454) - ------------------------------------------------------------------------------*/ - #define BIT_BCN_PORT_SEL BIT5 +/* ************************************************************ +* +* ************************************************************ */ + +/* ----------------------------------------------------- +* +* 0x0000h ~ 0x00FFh System Configuration +* +* ----------------------------------------------------- */ +#define REG_SYS_ISO_CTRL 0x0000 +#define REG_SYS_FUNC_EN 0x0002 +#define REG_APS_FSMCO 0x0004 +#define REG_SYS_CLKR 0x0008 +#define REG_SYS_CLK_CTRL REG_SYS_CLKR +#define REG_9346CR 0x000A +#define REG_SYS_EEPROM_CTRL 0x000A +#define REG_EE_VPD 0x000C +#define REG_AFE_MISC 0x0010 +#define REG_SPS0_CTRL 0x0011 +#define REG_SPS0_CTRL_6 0x0016 +#define REG_POWER_OFF_IN_PROCESS 0x0017 +#define REG_SPS_OCP_CFG 0x0018 +#define REG_RSV_CTRL 0x001C +#define REG_RF_CTRL 0x001F +#define REG_LDOA15_CTRL 0x0020 +#define REG_LDOV12D_CTRL 0x0021 +#define REG_LDOHCI12_CTRL 0x0022 +#define REG_LPLDO_CTRL 0x0023 +#define REG_AFE_XTAL_CTRL 0x0024 +#define REG_AFE_LDO_CTRL 0x0027 /* 1.5v for 8188EE test chip, 1.4v for MP chip */ +#define REG_AFE_PLL_CTRL 0x0028 +#define REG_MAC_PHY_CTRL 0x002c /* for 92d, DMDP, SMSP, DMSP contrl */ +#define REG_APE_PLL_CTRL_EXT 0x002c +#define REG_EFUSE_CTRL 0x0030 +#define REG_EFUSE_TEST 0x0034 +#define REG_PWR_DATA 0x0038 +#define REG_CAL_TIMER 0x003C +#define REG_ACLK_MON 0x003E +#define REG_GPIO_MUXCFG 0x0040 +#define REG_GPIO_IO_SEL 0x0042 +#define REG_MAC_PINMUX_CFG 0x0043 +#define REG_GPIO_PIN_CTRL 0x0044 +#define REG_GPIO_INTM 0x0048 +#define REG_LEDCFG0 0x004C +#define REG_LEDCFG1 0x004D +#define REG_LEDCFG2 0x004E +#define REG_LEDCFG3 0x004F +#define REG_FSIMR 0x0050 +#define REG_FSISR 0x0054 +#define REG_HSIMR 0x0058 +#define REG_HSISR 0x005c +#define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ +#define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ +#define REG_PAD_CTRL_1 0x0064 +#define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */ +#define REG_GSSR 0x006c +#define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */ +#define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */ +#define REG_MCUFWDL 0x0080 +#define REG_WOL_EVENT 0x0081 /* RTL8188E */ +#define REG_MCUTSTCFG 0x0084 +#define REG_FDHM0 0x0088 +#define REG_HOST_SUSP_CNT 0x00BC /* RTL8192C Host suspend counter on FPGA platform */ +#define REG_SYSTEM_ON_CTRL 0x00CC /* For 8723AE Reset after S3 */ +#define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection for RTL8723 */ +#define REG_BIST_SCAN 0x00D0 +#define REG_BIST_RPT 0x00D4 +#define REG_BIST_ROM_RPT 0x00D8 +#define REG_USB_SIE_INTF 0x00E0 +#define REG_PCIE_MIO_INTF 0x00E4 +#define REG_PCIE_MIO_INTD 0x00E8 +#define REG_HPON_FSM 0x00EC +#define REG_SYS_CFG 0x00F0 +#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ +#define REG_TYPE_ID 0x00FC + +/* +* 2010/12/29 MH Add for 92D +* */ +#define REG_MAC_PHY_CTRL_NORMAL 0x00f8 + + +/* ----------------------------------------------------- +* +* 0x0100h ~ 0x01FFh MACTOP General Configuration +* +* ----------------------------------------------------- */ +#define REG_CR 0x0100 +#define REG_PBP 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 +#define REG_TRXDMA_CTRL 0x010C +#define REG_TRXFF_BNDY 0x0114 +#define REG_TRXFF_STATUS 0x0118 +#define REG_RXFF_PTR 0x011C +#define REG_HIMR 0x0120 +#define REG_FE1IMR 0x0120 +#define REG_HISR 0x0124 +#define REG_HIMRE 0x0128 +#define REG_HISRE 0x012C +#define REG_CPWM 0x012F +#define REG_FWIMR 0x0130 +#define REG_FWISR 0x0134 +#define REG_FTIMR 0x0138 +#define REG_FTISR 0x013C /* RTL8192C */ +#define REG_PKTBUF_DBG_CTRL 0x0140 +#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) +#define REG_PKTBUF_DBG_DATA_L 0x0144 +#define REG_PKTBUF_DBG_DATA_H 0x0148 + +#define REG_TC0_CTRL 0x0150 +#define REG_TC1_CTRL 0x0154 +#define REG_TC2_CTRL 0x0158 +#define REG_TC3_CTRL 0x015C +#define REG_TC4_CTRL 0x0160 +#define REG_TCUNIT_BASE 0x0164 +#define REG_MBIST_START 0x0174 +#define REG_MBIST_DONE 0x0178 +#define REG_MBIST_FAIL 0x017C +#define REG_32K_CTRL 0x0194 /* RTL8188E */ +#define REG_C2HEVT_MSG_NORMAL 0x01A0 +#define REG_C2HEVT_CLEAR 0x01AF +#define REG_MCUTST_1 0x01c0 +#define REG_MCUTST_WOWLAN 0x01C7 /* Defined after 8188E series. */ +#define REG_FMETHR 0x01C8 +#define REG_HMETFR 0x01CC +#define REG_HMEBOX_0 0x01D0 +#define REG_HMEBOX_1 0x01D4 +#define REG_HMEBOX_2 0x01D8 +#define REG_HMEBOX_3 0x01DC +#define REG_LLT_INIT 0x01E0 +#define REG_HMEBOX_EXT_0 0x01F0 +#define REG_HMEBOX_EXT_1 0x01F4 +#define REG_HMEBOX_EXT_2 0x01F8 +#define REG_HMEBOX_EXT_3 0x01FC + + +/* ----------------------------------------------------- +* +* 0x0200h ~ 0x027Fh TXDMA Configuration +* +* ----------------------------------------------------- */ +#define REG_RQPN 0x0200 +#define REG_FIFOPAGE 0x0204 +#define REG_TDECTRL 0x0208 +#define REG_TXDMA_OFFSET_CHK 0x020C +#define REG_TXDMA_STATUS 0x0210 +#define REG_RQPN_NPQ 0x0214 +#define REG_AUTO_LLT 0x0224 + + +/* ----------------------------------------------------- +* +* 0x0280h ~ 0x02FFh RXDMA Configuration +* +* ----------------------------------------------------- */ +#define REG_RXDMA_AGG_PG_TH 0x0280 +#define REG_RXPKT_NUM 0x0284 +#define REG_RXDMA_STATUS 0x0288 + +/* ----------------------------------------------------- +* +* 0x0300h ~ 0x03FFh PCIe +* +* ----------------------------------------------------- */ +#ifndef CONFIG_TRX_BD_ARCH /* prevent CONFIG_TRX_BD_ARCH to use old registers */ + +#define REG_PCIE_CTRL_REG 0x0300 +#define REG_INT_MIG 0x0304 /* Interrupt Migration */ +#define REG_BCNQ_DESA 0x0308 /* TX Beacon Descriptor Address */ +#define REG_HQ_DESA 0x0310 /* TX High Queue Descriptor Address */ +#define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descriptor Address */ +#define REG_VOQ_DESA 0x0320 /* TX VO Queue Descriptor Address */ +#define REG_VIQ_DESA 0x0328 /* TX VI Queue Descriptor Address */ +#define REG_BEQ_DESA 0x0330 /* TX BE Queue Descriptor Address */ +#define REG_BKQ_DESA 0x0338 /* TX BK Queue Descriptor Address */ +#define REG_RX_DESA 0x0340 /* RX Queue Descriptor Address */ +/* sherry added for DBI Read/Write 20091126 */ +#define REG_DBI_WDATA 0x0348 /* Backdoor REG for Access Configuration */ +#define REG_DBI_RDATA 0x034C /* Backdoor REG for Access Configuration */ +#define REG_DBI_CTRL 0x0350 /* Backdoor REG for Access Configuration */ +#define REG_DBI_FLAG 0x0352 /* Backdoor REG for Access Configuration */ +#define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ +#define REG_DBG_SEL 0x0360 /* Debug Selection Register */ +#define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ +#define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ +#define REG_WATCH_DOG 0x0368 +#define REG_RX_RXBD_NUM 0x0382 + +/* RTL8723 series ------------------------------- */ +#define REG_PCIE_HISR_EN 0x0394 /* PCIE Local Interrupt Enable Register */ +#define REG_PCIE_HISR 0x03A0 +#define REG_PCIE_HISRE 0x03A4 +#define REG_PCIE_HIMR 0x03A8 +#define REG_PCIE_HIMRE 0x03AC + +#endif /* !CONFIG_TRX_BD_ARCH */ + +#define REG_USB_HIMR 0xFE38 +#define REG_USB_HIMRE 0xFE3C +#define REG_USB_HISR 0xFE78 +#define REG_USB_HISRE 0xFE7C + + +/* ----------------------------------------------------- +* +* 0x0400h ~ 0x047Fh Protocol Configuration +* +* ----------------------------------------------------- */ + +/* 92C, 92D */ +#define REG_VOQ_INFO 0x0400 +#define REG_VIQ_INFO 0x0404 +#define REG_BEQ_INFO 0x0408 +#define REG_BKQ_INFO 0x040C + +/* 88E, 8723A, 8812A, 8821A, 92E, 8723B */ +#define REG_Q0_INFO 0x400 +#define REG_Q1_INFO 0x404 +#define REG_Q2_INFO 0x408 +#define REG_Q3_INFO 0x40C + +#define REG_MGQ_INFO 0x0410 +#define REG_HGQ_INFO 0x0414 +#define REG_BCNQ_INFO 0x0418 +#define REG_TXPKT_EMPTY 0x041A +#define REG_CPU_MGQ_INFORMATION 0x041C +#define REG_FWHW_TXQ_CTRL 0x0420 +#define REG_HWSEQ_CTRL 0x0423 +#define REG_BCNQ_BDNY 0x0424 +#define REG_MGQ_BDNY 0x0425 +#define REG_LIFETIME_CTRL 0x0426 +#define REG_MULTI_BCNQ_OFFSET 0x0427 +#define REG_SPEC_SIFS 0x0428 +#define REG_RL 0x042A +#define REG_DARFRC 0x0430 +#define REG_RARFRC 0x0438 +#define REG_RRSR 0x0440 +#define REG_ARFR0 0x0444 +#define REG_ARFR1 0x0448 +#define REG_ARFR2 0x044C +#define REG_ARFR3 0x0450 +#define REG_CCK_CHECK 0x0454 +#define REG_BCNQ1_BDNY 0x0457 + +#define REG_AGGLEN_LMT 0x0458 +#define REG_AMPDU_MIN_SPACE 0x045C +#define REG_WMAC_LBK_BF_HD 0x045D +#define REG_FAST_EDCA_CTRL 0x0460 +#define REG_RD_RESP_PKT_TH 0x0463 + +/* 8723A, 8812A, 8821A, 92E, 8723B */ +#define REG_Q4_INFO 0x468 +#define REG_Q5_INFO 0x46C +#define REG_Q6_INFO 0x470 +#define REG_Q7_INFO 0x474 + +#define REG_INIRTS_RATE_SEL 0x0480 +#define REG_INIDATA_RATE_SEL 0x0484 + +/* 8723B, 92E, 8812A, 8821A*/ +#define REG_MACID_SLEEP_3 0x0484 +#define REG_MACID_SLEEP_1 0x0488 + +#define REG_POWER_STAGE1 0x04B4 +#define REG_POWER_STAGE2 0x04B8 +#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 +#define REG_STBC_SETTING 0x04C4 +#define REG_QUEUE_CTRL 0x04C6 +#define REG_SINGLE_AMPDU_CTRL 0x04c7 +#define REG_PROT_MODE_CTRL 0x04C8 +#define REG_MAX_AGGR_NUM 0x04CA +#define REG_RTS_MAX_AGGR_NUM 0x04CB +#define REG_BAR_MODE_CTRL 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT 0x04CF + +/* 8723A */ +#define REG_MACID_DROP 0x04D0 + +/* 88E */ +#define REG_EARLY_MODE_CONTROL 0x04D0 + +/* 8723B, 92E, 8812A, 8821A */ +#define REG_MACID_SLEEP_2 0x04D0 + +/* 8723A, 8723B, 92E, 8812A, 8821A */ +#define REG_MACID_SLEEP 0x04D4 + +#define REG_NQOS_SEQ 0x04DC +#define REG_QOS_SEQ 0x04DE +#define REG_NEED_CPU_HANDLE 0x04E0 +#define REG_PKT_LOSE_RPT 0x04E1 +#define REG_PTCL_ERR_STATUS 0x04E2 +#define REG_TX_RPT_CTRL 0x04EC +#define REG_TX_RPT_TIME 0x04F0 /* 2 byte */ +#define REG_DUMMY 0x04FC + +/* ----------------------------------------------------- +* +* 0x0500h ~ 0x05FFh EDCA Configuration +* +* ----------------------------------------------------- */ +#define REG_EDCA_VO_PARAM 0x0500 +#define REG_EDCA_VI_PARAM 0x0504 +#define REG_EDCA_BE_PARAM 0x0508 +#define REG_EDCA_BK_PARAM 0x050C +#define REG_BCNTCFG 0x0510 +#define REG_PIFS 0x0512 +#define REG_RDG_PIFS 0x0513 +#define REG_SIFS_CTX 0x0514 +#define REG_SIFS_TRX 0x0516 +#define REG_TSFTR_SYN_OFFSET 0x0518 +#define REG_AGGR_BREAK_TIME 0x051A +#define REG_SLOT 0x051B +#define REG_TX_PTCL_CTRL 0x0520 +#define REG_TXPAUSE 0x0522 +#define REG_DIS_TXREQ_CLR 0x0523 +#define REG_RD_CTRL 0x0524 +/* +* Format for offset 540h-542h: +* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. +* [7:4]: Reserved. +* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. +* [23:20]: Reserved +* Description: +* | +* |<--Setup--|--Hold------------>| +* --------------|---------------------- +* | +* TBTT +* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. +* Described by Designer Tim and Bruce, 2011-01-14. +* */ +#define REG_TBTT_PROHIBIT 0x0540 +#define REG_RD_NAV_NXT 0x0544 +#define REG_NAV_PROT_LEN 0x0546 +#define REG_BCN_CTRL 0x0550 +#define REG_BCN_CTRL_1 0x0551 +#define REG_MBID_NUM 0x0552 +#define REG_DUAL_TSF_RST 0x0553 +#define REG_BCN_INTERVAL 0x0554 /* The same as REG_MBSSID_BCN_SPACE */ +#define REG_DRVERLYINT 0x0558 +#define REG_BCNDMATIM 0x0559 +#define REG_ATIMWND 0x055A +#define REG_USTIME_TSF 0x055C +#define REG_BCN_MAX_ERR 0x055D +#define REG_RXTSF_OFFSET_CCK 0x055E +#define REG_RXTSF_OFFSET_OFDM 0x055F +#define REG_TSFTR 0x0560 +#define REG_TSFTR1 0x0568 /* HW Port 1 TSF Register */ +#define REG_ATIMWND_1 0x0570 +#define REG_P2P_CTWIN 0x0572 /* 1 Byte long (in unit of TU) */ +#define REG_PSTIMER 0x0580 +#define REG_TIMER0 0x0584 +#define REG_TIMER1 0x0588 +#define REG_ACMHWCTRL 0x05C0 +#define REG_NOA_DESC_SEL 0x05CF +#define REG_NOA_DESC_DURATION 0x05E0 +#define REG_NOA_DESC_INTERVAL 0x05E4 +#define REG_NOA_DESC_START 0x05E8 +#define REG_NOA_DESC_COUNT 0x05EC + +#define REG_DMC 0x05F0 /* Dual MAC Co-Existence Register */ +#define REG_SCH_TX_CMD 0x05F8 + +#define REG_FW_RESET_TSF_CNT_1 0x05FC +#define REG_FW_RESET_TSF_CNT_0 0x05FD +#define REG_FW_BCN_DIS_CNT 0x05FE + +/* ----------------------------------------------------- +* +* 0x0600h ~ 0x07FFh WMAC Configuration +* +* ----------------------------------------------------- */ +#define REG_APSD_CTRL 0x0600 +#define REG_BWOPMODE 0x0603 +#define REG_TCR 0x0604 +#define REG_RCR 0x0608 +#define REG_RX_PKT_LIMIT 0x060C +#define REG_RX_DLK_TIME 0x060D +#define REG_RX_DRVINFO_SZ 0x060F + +#define REG_MACID 0x0610 +#define REG_BSSID 0x0618 +#define REG_MAR 0x0620 +#define REG_MBIDCAMCFG_1 0x0628 +#define REG_MBIDCAMCFG_2 0x062C + +#define REG_PNO_STATUS 0x0631 +#define REG_USTIME_EDCA 0x0638 +#define REG_MAC_SPEC_SIFS 0x063A +/* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ +#define REG_RESP_SIFS_CCK 0x063C /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ +#define REG_RESP_SIFS_OFDM 0x063E /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ + +#define REG_ACKTO 0x0640 +#define REG_CTS2TO 0x0641 +#define REG_EIFS 0x0642 + + +/* RXERR_RPT */ +#define RXERR_TYPE_OFDM_PPDU 0 +#define RXERR_TYPE_OFDM_FALSE_ALARM 1 +#define RXERR_TYPE_OFDM_MPDU_OK 2 +#define RXERR_TYPE_OFDM_MPDU_FAIL 3 +#define RXERR_TYPE_CCK_PPDU 4 +#define RXERR_TYPE_CCK_FALSE_ALARM 5 +#define RXERR_TYPE_CCK_MPDU_OK 6 +#define RXERR_TYPE_CCK_MPDU_FAIL 7 +#define RXERR_TYPE_HT_PPDU 8 +#define RXERR_TYPE_HT_FALSE_ALARM 9 +#define RXERR_TYPE_HT_MPDU_TOTAL 10 +#define RXERR_TYPE_HT_MPDU_OK 11 +#define RXERR_TYPE_HT_MPDU_FAIL 12 +#define RXERR_TYPE_RX_FULL_DROP 15 + +#define RXERR_COUNTER_MASK 0xFFFFF +#define RXERR_RPT_RST BIT(27) +#define _RXERR_RPT_SEL(type) ((type) << 28) + +/* +* Note: +* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is +* always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending +* CTS in the air. We must update this value greater than 25,000 microseconds to pass the item. +* The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented +* by SD1 Scott. +* By Bruce, 2011-07-18. +* */ +#define REG_NAV_UPPER 0x0652 /* unit of 128 */ + +/* WMA, BA, CCX */ +#define REG_NAV_CTRL 0x0650 +#define REG_BACAMCMD 0x0654 +#define REG_BACAMCONTENT 0x0658 +#define REG_LBDLY 0x0660 +#define REG_FWDLY 0x0661 +#define REG_RXERR_RPT 0x0664 +#define REG_WMAC_TRXPTCL_CTL 0x0668 + +/* Security */ +#define REG_CAMCMD 0x0670 +#define REG_CAMWRITE 0x0674 +#define REG_CAMREAD 0x0678 +#define REG_CAMDBG 0x067C +#define REG_SECCFG 0x0680 + +/* Power */ +#define REG_WOW_CTRL 0x0690 +#define REG_PS_RX_INFO 0x0692 +#define REG_WMMPS_UAPSD_TID 0x0693 +#define REG_WKFMCAM_CMD 0x0698 +#define REG_WKFMCAM_NUM REG_WKFMCAM_CMD +#define REG_WKFMCAM_RWD 0x069C +#define REG_RXFLTMAP0 0x06A0 +#define REG_RXFLTMAP1 0x06A2 +#define REG_RXFLTMAP2 0x06A4 +#define REG_BCN_PSR_RPT 0x06A8 +#define REG_BT_COEX_TABLE 0x06C0 + +/* Hardware Port 1 */ +#define REG_MACID1 0x0700 +#define REG_BSSID1 0x0708 +/* Hardware Port 2 */ +#define REG_MACID2 0x1620 +#define REG_BSSID2 0x1628 +/* Hardware Port 3*/ +#define REG_MACID3 0x1630 +#define REG_BSSID3 0x1638 +/* Hardware Port 4 */ +#define REG_MACID4 0x1640 +#define REG_BSSID4 0x1648 + + +#define REG_CR_EXT 0x1100 + +/* ----------------------------------------------------- +* +* 0xFE00h ~ 0xFE55h USB Configuration +* +* ----------------------------------------------------- */ +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +#define REG_USB_HRPWM 0xFE58 +#define REG_USB_HCPWM 0xFE57 + +/* for 92DU high_Queue low_Queue Normal_Queue select */ +#define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44 +/* #define REG_USB_LOW_Queue_Select_MAC0 0xFE45 */ +#define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47 +/* #define REG_USB_LOW_Queue_Select_MAC1 0xFE48 */ + +/* For test chip */ +#define REG_TEST_USB_TXQS 0xFE48 +#define REG_TEST_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ +#define REG_TEST_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ +#define REG_TEST_SIE_OPTIONAL 0xFE64 +#define REG_TEST_SIE_CHIRP_K 0xFE65 +#define REG_TEST_SIE_PHY 0xFE66 /* 0xFE66~0xFE6B */ +#define REG_TEST_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ +#define REG_TEST_SIE_STRING 0xFE80 /* 0xFE80~0xFEB9 */ + + +/* For normal chip */ +#define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ +#define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ +#define REG_NORMAL_SIE_OPTIONAL 0xFE64 +#define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ +#define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ +#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C +#define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */ +#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ +#define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ + + +/* ----------------------------------------------------- +* +* Redifine 8192C register definition for compatibility +* +* ----------------------------------------------------- */ + +/* TODO: use these definition when using REG_xxx naming rule. +* NOTE: DO NOT Remove these definition. Use later. */ + +#define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ +#define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */ +#define MSR (REG_CR + 2) /* Media Status register */ +/* #define ISR REG_HISR */ +#define MSR1 REG_CR_EXT + +#define TSFR REG_TSFTR /* Timing Sync Function Timer Register. */ +#define TSFR1 REG_TSFTR1 /* HW Port 1 TSF Register */ + +#define PBP REG_PBP + +/* Redifine MACID register, to compatible prior ICs. */ +#define IDR0 REG_MACID /* MAC ID Register, Offset 0x0050-0x0053 */ +#define IDR4 (REG_MACID + 4) /* MAC ID Register, Offset 0x0054-0x0055 */ + + +/* +* 9. Security Control Registers (Offset: ) +* */ +#define RWCAM REG_CAMCMD /* IN 8190 Data Sheet is called CAMcmd */ +#define WCAMI REG_CAMWRITE /* Software write CAM input content */ +#define RCAMO REG_CAMREAD /* Software read/write CAM config */ +#define CAMDBG REG_CAMDBG +#define SECR REG_SECCFG /* Security Configuration Register */ + +/* Unused register */ +#define UnusedRegister 0x1BF +#define DCAM UnusedRegister +#define PSR UnusedRegister +#define BBAddr UnusedRegister +#define PhyDataR UnusedRegister + +/* Min Spacing related settings. */ +#define MAX_MSS_DENSITY_2T 0x13 +#define MAX_MSS_DENSITY_1T 0x0A + +/* ---------------------------------------------------------------------------- +* 8192C Cmd9346CR bits (Offset 0xA, 16bit) +* ---------------------------------------------------------------------------- */ +#define CmdEEPROM_En BIT(5) /* EEPROM enable when set 1 */ +#define CmdEERPOMSEL BIT(4) /* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */ +#define Cmd9346CR_9356SEL BIT(4) + +/* ---------------------------------------------------------------------------- +* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) +* ---------------------------------------------------------------------------- */ +#define GPIOSEL_GPIO 0 +#define GPIOSEL_ENBT BIT(5) + +/* ---------------------------------------------------------------------------- +* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) +* ---------------------------------------------------------------------------- */ +#define GPIO_IN REG_GPIO_PIN_CTRL /* GPIO pins input value */ +#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) /* GPIO pins output value */ +#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) /* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */ +#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) + +/* ---------------------------------------------------------------------------- +* 8811A GPIO PIN Control Register (offset 0x60, 4 byte) +* ---------------------------------------------------------------------------- */ +#define GPIO_IN_8811A REG_GPIO_PIN_CTRL_2 /* GPIO pins input value */ +#define GPIO_OUT_8811A (REG_GPIO_PIN_CTRL_2+1) /* GPIO pins output value */ +#define GPIO_IO_SEL_8811A (REG_GPIO_PIN_CTRL_2+2) /* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */ +#define GPIO_MOD_8811A (REG_GPIO_PIN_CTRL_2+3) + +/* ---------------------------------------------------------------------------- +* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) +* ---------------------------------------------------------------------------- */ +#define HSIMR_GPIO12_0_INT_EN BIT(0) +#define HSIMR_SPS_OCP_INT_EN BIT(5) +#define HSIMR_RON_INT_EN BIT(6) +#define HSIMR_PDN_INT_EN BIT(7) +#define HSIMR_GPIO9_INT_EN BIT(25) + +/* ---------------------------------------------------------------------------- +* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) +* ---------------------------------------------------------------------------- */ +#define HSISR_GPIO12_0_INT BIT(0) +#define HSISR_SPS_OCP_INT BIT(5) +#define HSISR_RON_INT BIT(6) +#define HSISR_PDNINT BIT(7) +#define HSISR_GPIO9_INT BIT(25) + +/* ---------------------------------------------------------------------------- +* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) +* ---------------------------------------------------------------------------- */ +/* +Network Type +00: No link +01: Link in ad hoc network +10: Link in infrastructure network +11: AP mode +Default: 00b. +*/ +#define MSR_NOLINK 0x00 +#define MSR_ADHOC 0x01 +#define MSR_INFRA 0x02 +#define MSR_AP 0x03 + +/* ---------------------------------------------------------------------------- +* USB INTR CONTENT +* ---------------------------------------------------------------------------- */ +#define USB_C2H_CMDID_OFFSET 0 +#define USB_C2H_SEQ_OFFSET 1 +#define USB_C2H_EVENT_OFFSET 2 +#define USB_INTR_CPWM_OFFSET 16 +#define USB_INTR_CONTENT_C2H_OFFSET 0 +#define USB_INTR_CONTENT_CPWM1_OFFSET 16 +#define USB_INTR_CONTENT_CPWM2_OFFSET 20 +#define USB_INTR_CONTENT_HISR_OFFSET 48 +#define USB_INTR_CONTENT_HISRE_OFFSET 52 +#define USB_INTR_CONTENT_LENGTH 56 + +/* ---------------------------------------------------------------------------- +* Response Rate Set Register (offset 0x440, 24bits) +* ---------------------------------------------------------------------------- */ +#define RRSR_1M BIT(0) +#define RRSR_2M BIT(1) +#define RRSR_5_5M BIT(2) +#define RRSR_11M BIT(3) +#define RRSR_6M BIT(4) +#define RRSR_9M BIT(5) +#define RRSR_12M BIT(6) +#define RRSR_18M BIT(7) +#define RRSR_24M BIT(8) +#define RRSR_36M BIT(9) +#define RRSR_48M BIT(10) +#define RRSR_54M BIT(11) +#define RRSR_MCS0 BIT(12) +#define RRSR_MCS1 BIT(13) +#define RRSR_MCS2 BIT(14) +#define RRSR_MCS3 BIT(15) +#define RRSR_MCS4 BIT(16) +#define RRSR_MCS5 BIT(17) +#define RRSR_MCS6 BIT(18) +#define RRSR_MCS7 BIT(19) + +#define RRSR_CCK_RATES (RRSR_11M | RRSR_5_5M | RRSR_2M | RRSR_1M) +#define RRSR_OFDM_RATES (RRSR_54M | RRSR_48M | RRSR_36M | RRSR_24M | RRSR_18M | RRSR_12M | RRSR_9M | RRSR_6M) + +/* WOL bit information */ +#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) +#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) +#define HAL92C_WOL_DISASSOC_EVENT BIT(2) +#define HAL92C_WOL_DEAUTH_EVENT BIT(3) +#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4) + + +/*---------------------------------------------------------------------------- +** REG_CCK_CHECK (offset 0x454) +------------------------------------------------------------------------------*/ +#define BIT_BCN_PORT_SEL BIT(5) #endif /* RTW_HALMAC */ /* ---------------------------------------------------------------------------- * Rate Definition - * ---------------------------------------------------------------------------- - * CCK */ + * ---------------------------------------------------------------------------- */ +/* CCK */ #define RATR_1M 0x00000001 #define RATR_2M 0x00000002 #define RATR_55M 0x00000004 @@ -800,15 +797,15 @@ /* ---------------------------------------------------------------------------- * BW_OPMODE bits (Offset 0x603, 8bit) * ---------------------------------------------------------------------------- */ -#define BW_OPMODE_20MHZ BIT2 -#define BW_OPMODE_5G BIT1 +#define BW_OPMODE_20MHZ BIT(2) +#define BW_OPMODE_5G BIT(1) /* ---------------------------------------------------------------------------- * CAM Config Setting (offset 0x680, 1 byte) * ---------------------------------------------------------------------------- */ -#define CAM_VALID BIT15 +#define CAM_VALID BIT(15) #define CAM_NOTVALID 0x0000 -#define CAM_USEDK BIT5 +#define CAM_USEDK BIT(5) #define CAM_CONTENT_COUNT 8 @@ -825,17 +822,17 @@ #define CAM_CONFIG_USEDK _TRUE #define CAM_CONFIG_NO_USEDK _FALSE -#define CAM_WRITE BIT16 +#define CAM_WRITE BIT(16) #define CAM_READ 0x00000000 -#define CAM_POLLINIG BIT31 +#define CAM_POLLINIG BIT(31) /* * 10. Power Save Control Registers * */ -#define WOW_PMEN BIT0 /* Power management Enable. */ -#define WOW_WOMEN BIT1 /* WoW function on or off. */ -#define WOW_MAGIC BIT2 /* Magic packet */ -#define WOW_UWF BIT3 /* Unicast Wakeup frame. */ +#define WOW_PMEN BIT(0) /* Power management Enable. */ +#define WOW_WOMEN BIT(1) /* WoW function on or off. */ +#define WOW_MAGIC BIT(2) /* Magic packet */ +#define WOW_UWF BIT(3) /* Unicast Wakeup frame. */ /* * 12. Host Interrupt Status Registers @@ -846,156 +843,156 @@ #define IMR8190_DISABLED 0x0 #define IMR_DISABLED 0x0 /* IMR DW0 Bit 0-31 */ -#define IMR_BCNDMAINT6 BIT31 /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5 BIT30 /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4 BIT29 /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3 BIT28 /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2 BIT27 /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1 BIT26 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK8 BIT25 /* Beacon Queue DMA OK Interrup 8 */ -#define IMR_BCNDOK7 BIT24 /* Beacon Queue DMA OK Interrup 7 */ -#define IMR_BCNDOK6 BIT23 /* Beacon Queue DMA OK Interrup 6 */ -#define IMR_BCNDOK5 BIT22 /* Beacon Queue DMA OK Interrup 5 */ -#define IMR_BCNDOK4 BIT21 /* Beacon Queue DMA OK Interrup 4 */ -#define IMR_BCNDOK3 BIT20 /* Beacon Queue DMA OK Interrup 3 */ -#define IMR_BCNDOK2 BIT19 /* Beacon Queue DMA OK Interrup 2 */ -#define IMR_BCNDOK1 BIT18 /* Beacon Queue DMA OK Interrup 1 */ -#define IMR_TIMEOUT2 BIT17 /* Timeout interrupt 2 */ -#define IMR_TIMEOUT1 BIT16 /* Timeout interrupt 1 */ -#define IMR_TXFOVW BIT15 /* Transmit FIFO Overflow */ -#define IMR_PSTIMEOUT BIT14 /* Power save time out interrupt */ -#define IMR_BcnInt BIT13 /* Beacon DMA Interrupt 0 */ -#define IMR_RXFOVW BIT12 /* Receive FIFO Overflow */ -#define IMR_RDU BIT11 /* Receive Descriptor Unavailable */ -#define IMR_ATIMEND BIT10 /* For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */ -#define IMR_BDOK BIT9 /* Beacon Queue DMA OK Interrup */ -#define IMR_HIGHDOK BIT8 /* High Queue DMA OK Interrupt */ -#define IMR_TBDOK BIT7 /* Transmit Beacon OK interrup */ -#define IMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */ -#define IMR_TBDER BIT5 /* For 92C, Transmit Beacon Error Interrupt */ -#define IMR_BKDOK BIT4 /* AC_BK DMA OK Interrupt */ -#define IMR_BEDOK BIT3 /* AC_BE DMA OK Interrupt */ -#define IMR_VIDOK BIT2 /* AC_VI DMA OK Interrupt */ -#define IMR_VODOK BIT1 /* AC_VO DMA Interrupt */ -#define IMR_ROK BIT0 /* Receive DMA OK Interrupt */ +#define IMR_BCNDMAINT6 BIT(31) /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5 BIT(30) /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4 BIT(29) /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3 BIT(28) /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2 BIT(27) /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1 BIT(26) /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDOK8 BIT(25) /* Beacon Queue DMA OK Interrupt 8 */ +#define IMR_BCNDOK7 BIT(24) /* Beacon Queue DMA OK Interrupt 7 */ +#define IMR_BCNDOK6 BIT(23) /* Beacon Queue DMA OK Interrupt 6 */ +#define IMR_BCNDOK5 BIT(22) /* Beacon Queue DMA OK Interrupt 5 */ +#define IMR_BCNDOK4 BIT(21) /* Beacon Queue DMA OK Interrupt 4 */ +#define IMR_BCNDOK3 BIT(20) /* Beacon Queue DMA OK Interrupt 3 */ +#define IMR_BCNDOK2 BIT(19) /* Beacon Queue DMA OK Interrupt 2 */ +#define IMR_BCNDOK1 BIT(18) /* Beacon Queue DMA OK Interrupt 1 */ +#define IMR_TIMEOUT2 BIT(17) /* Timeout interrupt 2 */ +#define IMR_TIMEOUT1 BIT(16) /* Timeout interrupt 1 */ +#define IMR_TXFOVW BIT(15) /* Transmit FIFO Overflow */ +#define IMR_PSTIMEOUT BIT(14) /* Power save time out interrupt */ +#define IMR_BcnInt BIT(13) /* Beacon DMA Interrupt 0 */ +#define IMR_RXFOVW BIT(12) /* Receive FIFO Overflow */ +#define IMR_RDU BIT(11) /* Receive Descriptor Unavailable */ +#define IMR_ATIMEND BIT(10) /* For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */ +#define IMR_BDOK BIT(9) /* Beacon Queue DMA OK Interrupt */ +#define IMR_HIGHDOK BIT(8) /* High Queue DMA OK Interrupt */ +#define IMR_TBDOK BIT(7) /* Transmit Beacon OK interrupt */ +#define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK Interrupt */ +#define IMR_TBDER BIT(5) /* For 92C, Transmit Beacon Error Interrupt */ +#define IMR_BKDOK BIT(4) /* AC_BK DMA OK Interrupt */ +#define IMR_BEDOK BIT(3) /* AC_BE DMA OK Interrupt */ +#define IMR_VIDOK BIT(2) /* AC_VI DMA OK Interrupt */ +#define IMR_VODOK BIT(1) /* AC_VO DMA Interrupt */ +#define IMR_ROK BIT(0) /* Receive DMA OK Interrupt */ /* 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) */ -#define IMR_TSF_BIT32_TOGGLE BIT15 -#define IMR_BcnInt_E BIT12 -#define IMR_TXERR BIT11 -#define IMR_RXERR BIT10 -#define IMR_C2HCMD BIT9 -#define IMR_CPWM BIT8 +#define IMR_TSF_BIT32_TOGGLE BIT(15) +#define IMR_BcnInt_E BIT(12) +#define IMR_TXERR BIT(11) +#define IMR_RXERR BIT(10) +#define IMR_C2HCMD BIT(9) +#define IMR_CPWM BIT(8) /* RSVD [2-7] */ -#define IMR_OCPINT BIT1 -#define IMR_WLANOFF BIT0 +#define IMR_OCPINT BIT(1) +#define IMR_WLANOFF BIT(0) /* ---------------------------------------------------------------------------- * 8723E series PCIE Host IMR/ISR bit - * ---------------------------------------------------------------------------- - * IMR DW0 Bit 0-31 */ -#define PHIMR_TIMEOUT2 BIT31 -#define PHIMR_TIMEOUT1 BIT30 -#define PHIMR_PSTIMEOUT BIT29 -#define PHIMR_GTINT4 BIT28 -#define PHIMR_GTINT3 BIT27 -#define PHIMR_TXBCNERR BIT26 -#define PHIMR_TXBCNOK BIT25 -#define PHIMR_TSF_BIT32_TOGGLE BIT24 -#define PHIMR_BCNDMAINT3 BIT23 -#define PHIMR_BCNDMAINT2 BIT22 -#define PHIMR_BCNDMAINT1 BIT21 -#define PHIMR_BCNDMAINT0 BIT20 -#define PHIMR_BCNDOK3 BIT19 -#define PHIMR_BCNDOK2 BIT18 -#define PHIMR_BCNDOK1 BIT17 -#define PHIMR_BCNDOK0 BIT16 -#define PHIMR_HSISR_IND_ON BIT15 -#define PHIMR_BCNDMAINT_E BIT14 -#define PHIMR_ATIMEND_E BIT13 -#define PHIMR_ATIM_CTW_END BIT12 -#define PHIMR_HISRE_IND BIT11 /* RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) */ -#define PHIMR_C2HCMD BIT10 -#define PHIMR_CPWM2 BIT9 -#define PHIMR_CPWM BIT8 -#define PHIMR_HIGHDOK BIT7 /* High Queue DMA OK Interrupt */ -#define PHIMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */ -#define PHIMR_BKDOK BIT5 /* AC_BK DMA OK Interrupt */ -#define PHIMR_BEDOK BIT4 /* AC_BE DMA OK Interrupt */ -#define PHIMR_VIDOK BIT3 /* AC_VI DMA OK Interrupt */ -#define PHIMR_VODOK BIT2 /* AC_VO DMA Interrupt */ -#define PHIMR_RDU BIT1 /* Receive Descriptor Unavailable */ -#define PHIMR_ROK BIT0 /* Receive DMA OK Interrupt */ + * ---------------------------------------------------------------------------- */ +/* IMR DW0 Bit 0-31 */ +#define PHIMR_TIMEOUT2 BIT(31) +#define PHIMR_TIMEOUT1 BIT(30) +#define PHIMR_PSTIMEOUT BIT(29) +#define PHIMR_GTINT4 BIT(28) +#define PHIMR_GTINT3 BIT(27) +#define PHIMR_TXBCNERR BIT(26) +#define PHIMR_TXBCNOK BIT(25) +#define PHIMR_TSF_BIT32_TOGGLE BIT(24) +#define PHIMR_BCNDMAINT3 BIT(23) +#define PHIMR_BCNDMAINT2 BIT(22) +#define PHIMR_BCNDMAINT1 BIT(21) +#define PHIMR_BCNDMAINT0 BIT(20) +#define PHIMR_BCNDOK3 BIT(19) +#define PHIMR_BCNDOK2 BIT(18) +#define PHIMR_BCNDOK1 BIT(17) +#define PHIMR_BCNDOK0 BIT(16) +#define PHIMR_HSISR_IND_ON BIT(15) +#define PHIMR_BCNDMAINT_E BIT(14) +#define PHIMR_ATIMEND_E BIT(13) +#define PHIMR_ATIM_CTW_END BIT(12) +#define PHIMR_HISRE_IND BIT(11) /* RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) */ +#define PHIMR_C2HCMD BIT(10) +#define PHIMR_CPWM2 BIT(9) +#define PHIMR_CPWM BIT(8) +#define PHIMR_HIGHDOK BIT(7) /* High Queue DMA OK Interrupt */ +#define PHIMR_MGNTDOK BIT(6) /* Management Queue DMA OK Interrupt */ +#define PHIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ +#define PHIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ +#define PHIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ +#define PHIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ +#define PHIMR_RDU BIT(1) /* Receive Descriptor Unavailable */ +#define PHIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ /* PCIE Host Interrupt Status Extension bit */ -#define PHIMR_BCNDMAINT7 BIT23 -#define PHIMR_BCNDMAINT6 BIT22 -#define PHIMR_BCNDMAINT5 BIT21 -#define PHIMR_BCNDMAINT4 BIT20 -#define PHIMR_BCNDOK7 BIT19 -#define PHIMR_BCNDOK6 BIT18 -#define PHIMR_BCNDOK5 BIT17 -#define PHIMR_BCNDOK4 BIT16 +#define PHIMR_BCNDMAINT7 BIT(23) +#define PHIMR_BCNDMAINT6 BIT(22) +#define PHIMR_BCNDMAINT5 BIT(21) +#define PHIMR_BCNDMAINT4 BIT(20) +#define PHIMR_BCNDOK7 BIT(19) +#define PHIMR_BCNDOK6 BIT(18) +#define PHIMR_BCNDOK5 BIT(17) +#define PHIMR_BCNDOK4 BIT(16) /* bit12 15: RSVD */ -#define PHIMR_TXERR BIT11 -#define PHIMR_RXERR BIT10 -#define PHIMR_TXFOVW BIT9 -#define PHIMR_RXFOVW BIT8 +#define PHIMR_TXERR BIT(11) +#define PHIMR_RXERR BIT(10) +#define PHIMR_TXFOVW BIT(9) +#define PHIMR_RXFOVW BIT(8) /* bit2-7: RSVD */ -#define PHIMR_OCPINT BIT1 +#define PHIMR_OCPINT BIT(1) /* bit0: RSVD */ -#define UHIMR_TIMEOUT2 BIT31 -#define UHIMR_TIMEOUT1 BIT30 -#define UHIMR_PSTIMEOUT BIT29 -#define UHIMR_GTINT4 BIT28 -#define UHIMR_GTINT3 BIT27 -#define UHIMR_TXBCNERR BIT26 -#define UHIMR_TXBCNOK BIT25 -#define UHIMR_TSF_BIT32_TOGGLE BIT24 -#define UHIMR_BCNDMAINT3 BIT23 -#define UHIMR_BCNDMAINT2 BIT22 -#define UHIMR_BCNDMAINT1 BIT21 -#define UHIMR_BCNDMAINT0 BIT20 -#define UHIMR_BCNDOK3 BIT19 -#define UHIMR_BCNDOK2 BIT18 -#define UHIMR_BCNDOK1 BIT17 -#define UHIMR_BCNDOK0 BIT16 -#define UHIMR_HSISR_IND BIT15 -#define UHIMR_BCNDMAINT_E BIT14 -/* RSVD BIT13 */ -#define UHIMR_CTW_END BIT12 -/* RSVD BIT11 */ -#define UHIMR_C2HCMD BIT10 -#define UHIMR_CPWM2 BIT9 -#define UHIMR_CPWM BIT8 -#define UHIMR_HIGHDOK BIT7 /* High Queue DMA OK Interrupt */ -#define UHIMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */ -#define UHIMR_BKDOK BIT5 /* AC_BK DMA OK Interrupt */ -#define UHIMR_BEDOK BIT4 /* AC_BE DMA OK Interrupt */ -#define UHIMR_VIDOK BIT3 /* AC_VI DMA OK Interrupt */ -#define UHIMR_VODOK BIT2 /* AC_VO DMA Interrupt */ -#define UHIMR_RDU BIT1 /* Receive Descriptor Unavailable */ -#define UHIMR_ROK BIT0 /* Receive DMA OK Interrupt */ +#define UHIMR_TIMEOUT2 BIT(31) +#define UHIMR_TIMEOUT1 BIT(30) +#define UHIMR_PSTIMEOUT BIT(29) +#define UHIMR_GTINT4 BIT(28) +#define UHIMR_GTINT3 BIT(27) +#define UHIMR_TXBCNERR BIT(26) +#define UHIMR_TXBCNOK BIT(25) +#define UHIMR_TSF_BIT32_TOGGLE BIT(24) +#define UHIMR_BCNDMAINT3 BIT(23) +#define UHIMR_BCNDMAINT2 BIT(22) +#define UHIMR_BCNDMAINT1 BIT(21) +#define UHIMR_BCNDMAINT0 BIT(20) +#define UHIMR_BCNDOK3 BIT(19) +#define UHIMR_BCNDOK2 BIT(18) +#define UHIMR_BCNDOK1 BIT(17) +#define UHIMR_BCNDOK0 BIT(16) +#define UHIMR_HSISR_IND BIT(15) +#define UHIMR_BCNDMAINT_E BIT(14) +/* RSVD BIT(13) */ +#define UHIMR_CTW_END BIT(12) +/* RSVD BIT(11) */ +#define UHIMR_C2HCMD BIT(10) +#define UHIMR_CPWM2 BIT(9) +#define UHIMR_CPWM BIT(8) +#define UHIMR_HIGHDOK BIT(7) /* High Queue DMA OK Interrupt */ +#define UHIMR_MGNTDOK BIT(6) /* Management Queue DMA OK Interrupt */ +#define UHIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ +#define UHIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ +#define UHIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ +#define UHIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ +#define UHIMR_RDU BIT(1) /* Receive Descriptor Unavailable */ +#define UHIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ /* USB Host Interrupt Status Extension bit */ -#define UHIMR_BCNDMAINT7 BIT23 -#define UHIMR_BCNDMAINT6 BIT22 -#define UHIMR_BCNDMAINT5 BIT21 -#define UHIMR_BCNDMAINT4 BIT20 -#define UHIMR_BCNDOK7 BIT19 -#define UHIMR_BCNDOK6 BIT18 -#define UHIMR_BCNDOK5 BIT17 -#define UHIMR_BCNDOK4 BIT16 +#define UHIMR_BCNDMAINT7 BIT(23) +#define UHIMR_BCNDMAINT6 BIT(22) +#define UHIMR_BCNDMAINT5 BIT(21) +#define UHIMR_BCNDMAINT4 BIT(20) +#define UHIMR_BCNDOK7 BIT(19) +#define UHIMR_BCNDOK6 BIT(18) +#define UHIMR_BCNDOK5 BIT(17) +#define UHIMR_BCNDOK4 BIT(16) /* bit14-15: RSVD */ -#define UHIMR_ATIMEND_E BIT13 -#define UHIMR_ATIMEND BIT12 -#define UHIMR_TXERR BIT11 -#define UHIMR_RXERR BIT10 -#define UHIMR_TXFOVW BIT9 -#define UHIMR_RXFOVW BIT8 +#define UHIMR_ATIMEND_E BIT(13) +#define UHIMR_ATIMEND BIT(12) +#define UHIMR_TXERR BIT(11) +#define UHIMR_RXERR BIT(10) +#define UHIMR_TXFOVW BIT(9) +#define UHIMR_RXFOVW BIT(8) /* bit2-7: RSVD */ -#define UHIMR_OCPINT BIT1 +#define UHIMR_OCPINT BIT(1) /* bit0: RSVD */ @@ -1007,51 +1004,51 @@ * ---------------------------------------------------------------------------- */ #define IMR_DISABLED_88E 0x0 /* IMR DW0(0x0060-0063) Bit 0-31 */ -#define IMR_TXCCK_88E BIT30 /* TXRPT interrupt when CCX bit of the packet is set */ -#define IMR_PSTIMEOUT_88E BIT29 /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_88E BIT28 /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_88E BIT27 /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TBDER_88E BIT26 /* Transmit Beacon0 Error */ -#define IMR_TBDOK_88E BIT25 /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_88E BIT24 /* TSF Timer BIT32 toggle indication interrupt */ -#define IMR_BCNDMAINT0_88E BIT20 /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_88E BIT16 /* Beacon Queue DMA Error 0 */ -#define IMR_HSISR_IND_ON_INT_88E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_88E BIT14 /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_88E BIT12 /* CTWidnow End or ATIM Window End */ -#define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ -#define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */ -#define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */ -#define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */ -#define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */ -#define IMR_VIDOK_88E BIT3 /* AC_VI DMA OK */ -#define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */ -#define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */ -#define IMR_ROK_88E BIT0 /* Receive DMA OK */ +#define IMR_TXCCK_88E BIT(30) /* TXRPT interrupt when CCX bit of the packet is set */ +#define IMR_PSTIMEOUT_88E BIT(29) /* Power Save Time Out Interrupt */ +#define IMR_GTINT4_88E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ +#define IMR_GTINT3_88E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ +#define IMR_TBDER_88E BIT(26) /* Transmit Beacon0 Error */ +#define IMR_TBDOK_88E BIT(25) /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_88E BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ +#define IMR_BCNDMAINT0_88E BIT(20) /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_88E BIT(16) /* Beacon Queue DMA Error 0 */ +#define IMR_HSISR_IND_ON_INT_88E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ +#define IMR_BCNDMAINT_E_88E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ +#define IMR_ATIMEND_88E BIT(12) /* CTWidnow End or ATIM Window End */ +#define IMR_HISR1_IND_INT_88E BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ +#define IMR_C2HCMD_88E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ +#define IMR_CPWM2_88E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_CPWM_88E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_HIGHDOK_88E BIT(7) /* High Queue DMA OK */ +#define IMR_MGNTDOK_88E BIT(6) /* Management Queue DMA OK */ +#define IMR_BKDOK_88E BIT(5) /* AC_BK DMA OK */ +#define IMR_BEDOK_88E BIT(4) /* AC_BE DMA OK */ +#define IMR_VIDOK_88E BIT(3) /* AC_VI DMA OK */ +#define IMR_VODOK_88E BIT(2) /* AC_VO DMA OK */ +#define IMR_RDU_88E BIT(1) /* Rx Descriptor Unavailable */ +#define IMR_ROK_88E BIT(0) /* Receive DMA OK */ /* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_88E BIT27 /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_88E BIT26 /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_88E BIT25 /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_88E BIT24 /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_88E BIT23 /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_88E BIT22 /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_88E BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_88E BIT20 /* Beacon Queue DMA OK Interrup 7 */ -#define IMR_BCNDOK6_88E BIT19 /* Beacon Queue DMA OK Interrup 6 */ -#define IMR_BCNDOK5_88E BIT18 /* Beacon Queue DMA OK Interrup 5 */ -#define IMR_BCNDOK4_88E BIT17 /* Beacon Queue DMA OK Interrup 4 */ -#define IMR_BCNDOK3_88E BIT16 /* Beacon Queue DMA OK Interrup 3 */ -#define IMR_BCNDOK2_88E BIT15 /* Beacon Queue DMA OK Interrup 2 */ -#define IMR_BCNDOK1_88E BIT14 /* Beacon Queue DMA OK Interrup 1 */ -#define IMR_ATIMEND_E_88E BIT13 /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_88E BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_88E BIT10 /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */ +#define IMR_BCNDMAINT7_88E BIT(27) /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_88E BIT(26) /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_88E BIT(25) /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_88E BIT(24) /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_88E BIT(23) /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_88E BIT(22) /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_88E BIT(21) /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDOK7_88E BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ +#define IMR_BCNDOK6_88E BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ +#define IMR_BCNDOK5_88E BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ +#define IMR_BCNDOK4_88E BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ +#define IMR_BCNDOK3_88E BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ +#define IMR_BCNDOK2_88E BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ +#define IMR_BCNDOK1_88E BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ +#define IMR_ATIMEND_E_88E BIT(13) /* ATIM Window End Extension for Win7 */ +#define IMR_TXERR_88E BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ +#define IMR_RXERR_88E BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ +#define IMR_TXFOVW_88E BIT(9) /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_88E BIT(8) /* Receive FIFO Overflow */ /*=================================================================== ===================================================================== @@ -1076,55 +1073,55 @@ Current IOREG MAP */ /* ---------------------------------------------------------------------------- */ /* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */ -/* ---------------------------------------------------------------------------- -* Note: +/* ---------------------------------------------------------------------------- */ +/* Note: * The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong, * the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3. * 8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim. * By Bruce, 2011-09-22. */ -#define StopBecon BIT6 -#define StopHigh BIT5 -#define StopMgt BIT4 -#define StopBK BIT3 -#define StopBE BIT2 -#define StopVI BIT1 -#define StopVO BIT0 +#define StopBecon BIT(6) +#define StopHigh BIT(5) +#define StopMgt BIT(4) +#define StopBK BIT(3) +#define StopBE BIT(2) +#define StopVI BIT(1) +#define StopVO BIT(0) /* ---------------------------------------------------------------------------- * 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) * ---------------------------------------------------------------------------- */ -#define RCR_APPFCS BIT31 /* WMAC append FCS after pauload */ -#define RCR_APP_MIC BIT30 /* MACRX will retain the MIC at the bottom of the packet. */ -#define RCR_APP_ICV BIT29 /* MACRX will retain the ICV at the bottom of the packet. */ -#define RCR_APP_PHYST_RXFF BIT28 /* PHY Status is appended before RX packet in RXFF */ -#define RCR_APP_BA_SSN BIT27 /* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */ -#define RCR_VHT_DACK BIT26 /* This bit to control response type for vht single mpdu data packet. 1. ACK as response 0. BA as response */ -#define RCR_TCPOFLD_EN BIT25 /* Enable TCP checksum offload */ -#define RCR_ENMBID BIT24 /* Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */ -#define RCR_LSIGEN BIT23 /* Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */ -#define RCR_MFBEN BIT22 /* Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */ -#define RCR_DISCHKPPDLLEN BIT21 /* Do not check PPDU while the PPDU length is smaller than 14 byte. */ -#define RCR_PKTCTL_DLEN BIT20 /* While rx path dead lock occurs, reset rx path */ -#define RCR_DISGCLK BIT19 /* Disable macrx clock gating control (no used) */ -#define RCR_TIM_PARSER_EN BIT18 /* RX Beacon TIM Parser. */ -#define RCR_BC_MD_EN BIT17 /* Broadcast data packet more data bit check interrupt enable.*/ -#define RCR_UC_MD_EN BIT16 /* Unicast data packet more data bit check interrupt enable. */ -#define RCR_RXSK_PERPKT BIT15 /* Executing key search per MPDU */ -#define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC = 1 MFC-->HTC = 0 */ -#define RCR_AMF BIT13 /* Accept management type frame */ -#define RCR_ACF BIT12 /* Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */ -#define RCR_ADF BIT11 /* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */ -#define RCR_DISDECMYPKT BIT10 /* This bit determines whether hw need to do decryption.1: If A1 match, do decryption.0: Do decryption. */ -#define RCR_AICV BIT9 /* Accept ICV error packet */ -#define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */ -#define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet (Rx beacon, probe rsp) */ -#define RCR_CBSSID_DATA BIT6 /* Accept BSSID match packet (Data) */ -#define RCR_APWRMGT BIT5 /* Accept power management packet */ -#define RCR_ADD3 BIT4 /* Accept address 3 match packet */ -#define RCR_AB BIT3 /* Accept broadcast packet */ -#define RCR_AM BIT2 /* Accept multicast packet */ -#define RCR_APM BIT1 /* Accept physical match packet */ -#define RCR_AAP BIT0 /* Accept all unicast packet */ +#define RCR_APPFCS BIT(31) /* WMAC append FCS after pauload */ +#define RCR_APP_MIC BIT(30) /* MACRX will retain the MIC at the bottom of the packet. */ +#define RCR_APP_ICV BIT(29) /* MACRX will retain the ICV at the bottom of the packet. */ +#define RCR_APP_PHYST_RXFF BIT(28) /* PHY Status is appended before RX packet in RXFF */ +#define RCR_APP_BA_SSN BIT(27) /* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */ +#define RCR_VHT_DACK BIT(26) /* This bit to control response type for vht single mpdu data packet. 1. ACK as response 0. BA as response */ +#define RCR_TCPOFLD_EN BIT(25) /* Enable TCP checksum offload */ +#define RCR_ENMBID BIT(24) /* Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */ +#define RCR_LSIGEN BIT(23) /* Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */ +#define RCR_MFBEN BIT(22) /* Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */ +#define RCR_DISCHKPPDLLEN BIT(21) /* Do not check PPDU while the PPDU length is smaller than 14 byte. */ +#define RCR_PKTCTL_DLEN BIT(20) /* While rx path dead lock occurs, reset rx path */ +#define RCR_DISGCLK BIT(19) /* Disable macrx clock gating control (no used) */ +#define RCR_TIM_PARSER_EN BIT(18) /* RX Beacon TIM Parser. */ +#define RCR_BC_MD_EN BIT(17) /* Broadcast data packet more data bit check interrupt enable.*/ +#define RCR_UC_MD_EN BIT(16) /* Unicast data packet more data bit check interrupt enable. */ +#define RCR_RXSK_PERPKT BIT(15) /* Executing key search per MPDU */ +#define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC = 1 MFC-->HTC = 0 */ +#define RCR_AMF BIT(13) /* Accept management type frame */ +#define RCR_ACF BIT(12) /* Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */ +#define RCR_ADF BIT(11) /* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */ +#define RCR_DISDECMYPKT BIT(10) /* This bit determines whether hw need to do decryption.1: If A1 match, do decryption.0: Do decryption. */ +#define RCR_AICV BIT(9) /* Accept ICV error packet */ +#define RCR_ACRC32 BIT(8) /* Accept CRC32 error packet */ +#define RCR_CBSSID_BCN BIT(7) /* Accept BSSID match packet (Rx beacon, probe rsp) */ +#define RCR_CBSSID_DATA BIT(6) /* Accept BSSID match packet (Data) */ +#define RCR_APWRMGT BIT(5) /* Accept power management packet */ +#define RCR_ADD3 BIT(4) /* Accept address 3 match packet */ +#define RCR_AB BIT(3) /* Accept broadcast packet */ +#define RCR_AM BIT(2) /* Accept multicast packet */ +#define RCR_APM BIT(1) /* Accept physical match packet */ +#define RCR_AAP BIT(0) /* Accept all unicast packet */ /* ----------------------------------------------------- @@ -1397,8 +1394,8 @@ Current IOREG MAP * * 0x0200h ~ 0x027Fh TXDMA Configuration * - * ----------------------------------------------------- - * 2 RQPN */ + * ----------------------------------------------------- */ +/* 2 RQPN */ #define _HPQ(x) ((x) & 0xFF) #define _LPQ(x) (((x) & 0xFF) << 8) #define _PUBQ(x) (((x) & 0xFF) << 16) @@ -1432,6 +1429,17 @@ Current IOREG MAP #define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space) +/* ----------------------------------------------------- + * + * 0x0120h ~ 0x0123h RX DMA Configuration + * + * ----------------------------------------------------- */ +#define BIT_FS_RXDONE_INT_EN BIT(16) + + +/* REG_RXPKT_NUM (Offset 0x0284) */ +#define BIT_RW_RELEASE_EN BIT(18) + /* ----------------------------------------------------- * * 0x0280h ~ 0x028Bh RX DMA Configuration @@ -1458,8 +1466,8 @@ Current IOREG MAP * * 0x0400h ~ 0x047Fh Protocol Configuration * - * ----------------------------------------------------- - * 2 FWHW_TXQ_CTRL */ + * ----------------------------------------------------- */ +/* 2 FWHW_TXQ_CTRL */ #define EN_AMPDU_RTY_NEW BIT(7) @@ -1652,56 +1660,56 @@ Current IOREG MAP #define SDIO_HIMR_DISABLED 0 /* RTL8723/RTL8188E SDIO Host Interrupt Mask Register */ -#define SDIO_HIMR_RX_REQUEST_MSK BIT0 -#define SDIO_HIMR_AVAL_MSK BIT1 -#define SDIO_HIMR_TXERR_MSK BIT2 -#define SDIO_HIMR_RXERR_MSK BIT3 -#define SDIO_HIMR_TXFOVW_MSK BIT4 -#define SDIO_HIMR_RXFOVW_MSK BIT5 -#define SDIO_HIMR_TXBCNOK_MSK BIT6 -#define SDIO_HIMR_TXBCNERR_MSK BIT7 -#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 -#define SDIO_HIMR_C2HCMD_MSK BIT17 -#define SDIO_HIMR_CPWM1_MSK BIT18 -#define SDIO_HIMR_CPWM2_MSK BIT19 -#define SDIO_HIMR_HSISR_IND_MSK BIT20 -#define SDIO_HIMR_GTINT3_IND_MSK BIT21 -#define SDIO_HIMR_GTINT4_IND_MSK BIT22 -#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 -#define SDIO_HIMR_OCPINT_MSK BIT24 -#define SDIO_HIMR_ATIMEND_MSK BIT25 -#define SDIO_HIMR_ATIMEND_E_MSK BIT26 -#define SDIO_HIMR_CTWEND_MSK BIT27 +#define SDIO_HIMR_RX_REQUEST_MSK BIT(0) +#define SDIO_HIMR_AVAL_MSK BIT(1) +#define SDIO_HIMR_TXERR_MSK BIT(2) +#define SDIO_HIMR_RXERR_MSK BIT(3) +#define SDIO_HIMR_TXFOVW_MSK BIT(4) +#define SDIO_HIMR_RXFOVW_MSK BIT(5) +#define SDIO_HIMR_TXBCNOK_MSK BIT(6) +#define SDIO_HIMR_TXBCNERR_MSK BIT(7) +#define SDIO_HIMR_BCNERLY_INT_MSK BIT(16) +#define SDIO_HIMR_C2HCMD_MSK BIT(17) +#define SDIO_HIMR_CPWM1_MSK BIT(18) +#define SDIO_HIMR_CPWM2_MSK BIT(19) +#define SDIO_HIMR_HSISR_IND_MSK BIT(20) +#define SDIO_HIMR_GTINT3_IND_MSK BIT(21) +#define SDIO_HIMR_GTINT4_IND_MSK BIT(22) +#define SDIO_HIMR_PSTIMEOUT_MSK BIT(23) +#define SDIO_HIMR_OCPINT_MSK BIT(24) +#define SDIO_HIMR_ATIMEND_MSK BIT(25) +#define SDIO_HIMR_ATIMEND_E_MSK BIT(26) +#define SDIO_HIMR_CTWEND_MSK BIT(27) /* RTL8188E SDIO Specific */ -#define SDIO_HIMR_MCU_ERR_MSK BIT28 -#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 +#define SDIO_HIMR_MCU_ERR_MSK BIT(28) +#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT(29) /* SDIO Host Interrupt Service Routine */ -#define SDIO_HISR_RX_REQUEST BIT0 -#define SDIO_HISR_AVAL BIT1 -#define SDIO_HISR_TXERR BIT2 -#define SDIO_HISR_RXERR BIT3 -#define SDIO_HISR_TXFOVW BIT4 -#define SDIO_HISR_RXFOVW BIT5 -#define SDIO_HISR_TXBCNOK BIT6 -#define SDIO_HISR_TXBCNERR BIT7 -#define SDIO_HISR_BCNERLY_INT BIT16 -#define SDIO_HISR_C2HCMD BIT17 -#define SDIO_HISR_CPWM1 BIT18 -#define SDIO_HISR_CPWM2 BIT19 -#define SDIO_HISR_HSISR_IND BIT20 -#define SDIO_HISR_GTINT3_IND BIT21 -#define SDIO_HISR_GTINT4_IND BIT22 -#define SDIO_HISR_PSTIMEOUT BIT23 -#define SDIO_HISR_OCPINT BIT24 -#define SDIO_HISR_ATIMEND BIT25 -#define SDIO_HISR_ATIMEND_E BIT26 -#define SDIO_HISR_CTWEND BIT27 +#define SDIO_HISR_RX_REQUEST BIT(0) +#define SDIO_HISR_AVAL BIT(1) +#define SDIO_HISR_TXERR BIT(2) +#define SDIO_HISR_RXERR BIT(3) +#define SDIO_HISR_TXFOVW BIT(4) +#define SDIO_HISR_RXFOVW BIT(5) +#define SDIO_HISR_TXBCNOK BIT(6) +#define SDIO_HISR_TXBCNERR BIT(7) +#define SDIO_HISR_BCNERLY_INT BIT(16) +#define SDIO_HISR_C2HCMD BIT(17) +#define SDIO_HISR_CPWM1 BIT(18) +#define SDIO_HISR_CPWM2 BIT(19) +#define SDIO_HISR_HSISR_IND BIT(20) +#define SDIO_HISR_GTINT3_IND BIT(21) +#define SDIO_HISR_GTINT4_IND BIT(22) +#define SDIO_HISR_PSTIMEOUT BIT(23) +#define SDIO_HISR_OCPINT BIT(24) +#define SDIO_HISR_ATIMEND BIT(25) +#define SDIO_HISR_ATIMEND_E BIT(26) +#define SDIO_HISR_CTWEND BIT(27) /* RTL8188E SDIO Specific */ -#define SDIO_HISR_MCU_ERR BIT28 -#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 +#define SDIO_HISR_MCU_ERR BIT(28) +#define SDIO_HISR_TSF_BIT32_TOGGLE BIT(29) #define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\ SDIO_HISR_RXERR |\ @@ -1719,8 +1727,8 @@ Current IOREG MAP SDIO_HISR_OCPINT) /* SDIO HCI Suspend Control Register */ -#define HCI_RESUME_PWR_RDY BIT1 -#define HCI_SUS_CTRL BIT0 +#define HCI_RESUME_PWR_RDY BIT(1) +#define HCI_SUS_CTRL BIT(0) /* SDIO Tx FIFO related */ #define SDIO_TX_FREE_PG_QUEUE 4 /* The number of Tx FIFO free page */ @@ -1760,31 +1768,31 @@ Current IOREG MAP /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ -#define WL_HWPDN_EN BIT0 /* Enable GPIO[9] as WiFi HW PDn source */ -#define WL_HWPDN_SL BIT1 /* WiFi HW PDn polarity control */ -#define WL_FUNC_EN BIT2 /* WiFi function enable */ -#define WL_HWROF_EN BIT3 /* Enable GPIO[9] as WiFi RF HW PDn source */ -#define BT_HWPDN_EN BIT16 /* Enable GPIO[11] as BT HW PDn source */ -#define BT_HWPDN_SL BIT17 /* BT HW PDn polarity control */ -#define BT_FUNC_EN BIT18 /* BT function enable */ -#define BT_HWROF_EN BIT19 /* Enable GPIO[11] as BT/GPS RF HW PDn source */ -#define GPS_HWPDN_EN BIT20 /* Enable GPIO[10] as GPS HW PDn source */ -#define GPS_HWPDN_SL BIT21 /* GPS HW PDn polarity control */ -#define GPS_FUNC_EN BIT22 /* GPS function enable */ +#define WL_HWPDN_EN BIT(0) /* Enable GPIO[9] as WiFi HW PDn source */ +#define WL_HWPDN_SL BIT(1) /* WiFi HW PDn polarity control */ +#define WL_FUNC_EN BIT(2) /* WiFi function enable */ +#define WL_HWROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW PDn source */ +#define BT_HWPDN_EN BIT(16) /* Enable GPIO[11] as BT HW PDn source */ +#define BT_HWPDN_SL BIT(17) /* BT HW PDn polarity control */ +#define BT_FUNC_EN BIT(18) /* BT function enable */ +#define BT_HWROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS RF HW PDn source */ +#define GPS_HWPDN_EN BIT(20) /* Enable GPIO[10] as GPS HW PDn source */ +#define GPS_HWPDN_SL BIT(21) /* GPS HW PDn polarity control */ +#define GPS_FUNC_EN BIT(22) /* GPS function enable */ /* 3 REG_LIFECTRL_CTRL */ -#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 -#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 -#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 -#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3) +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2) +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1) +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0) #define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us, said by Tim. */ /* 2 8192D PartNo. */ #define PARTNO_92D_NIC (BIT7 | BIT6) #define PARTNO_92D_NIC_REMARK (BIT5 | BIT4) -#define PARTNO_SINGLE_BAND_VS BIT3 -#define PARTNO_SINGLE_BAND_VS_REMARK BIT1 +#define PARTNO_SINGLE_BAND_VS BIT(3) +#define PARTNO_SINGLE_BAND_VS_REMARK BIT(1) #define PARTNO_CONCURRENT_BAND_VC (BIT3 | BIT2) #define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1 | BIT0) @@ -1810,9 +1818,9 @@ Current IOREG MAP /* GPIO BIT */ -#define HAL_8812A_HW_GPIO_WPS_BIT BIT2 -#define HAL_8192C_HW_GPIO_WPS_BIT BIT2 -#define HAL_8192EU_HW_GPIO_WPS_BIT BIT7 -#define HAL_8188E_HW_GPIO_WPS_BIT BIT7 +#define HAL_8812A_HW_GPIO_WPS_BIT BIT(2) +#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) +#define HAL_8192EU_HW_GPIO_WPS_BIT BIT(7) +#define HAL_8188E_HW_GPIO_WPS_BIT BIT(7) #endif /* __HAL_COMMON_H__ */ diff --git a/include/hal_data.h b/include/hal_data.h index d36516a..a036ec8 100644 --- a/include/hal_data.h +++ b/include/hal_data.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_DATA_H__ #define __HAL_DATA_H__ @@ -24,14 +19,14 @@ #include "../hal/phydm/phydm_precomp.h" #ifdef CONFIG_BT_COEXIST -#include + #include #endif #ifdef CONFIG_SDIO_HCI -#include + #include #endif #ifdef CONFIG_GSPI_HCI -#include + #include #endif /* * For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. @@ -86,12 +81,6 @@ typedef enum _RT_AMPDU_BRUST_MODE { RT_AMPDU_BRUST_8723B = 7, } RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE; -#if 0 -#define CHANNEL_MAX_NUMBER 14+24+21 /* 14 is the max channel number */ -#endif -#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, ch4~9, ch10~14 total three groups */ -#define MAX_PG_GROUP 13 - /* Tx Power Limit Table Size */ #define MAX_REGULATION_NUM 4 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 @@ -129,6 +118,65 @@ typedef enum _RX_AGG_MODE { #endif /* RTW_RX_AGGREGATION */ +/* E-Fuse */ +#ifdef CONFIG_RTL8188E + #define EFUSE_MAP_SIZE 512 +#endif +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) + #define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8192E + #define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8723B + #define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8814A + #define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8703B + #define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8723D + #define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8188F + #define EFUSE_MAP_SIZE 512 +#endif + +#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) + #define EFUSE_MAX_SIZE 1024 +#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8703B) + #define EFUSE_MAX_SIZE 256 +#else + #define EFUSE_MAX_SIZE 512 +#endif +/* end of E-Fuse */ + +#define Mac_OFDM_OK 0x00000000 +#define Mac_OFDM_Fail 0x10000000 +#define Mac_OFDM_FasleAlarm 0x20000000 +#define Mac_CCK_OK 0x30000000 +#define Mac_CCK_Fail 0x40000000 +#define Mac_CCK_FasleAlarm 0x50000000 +#define Mac_HT_OK 0x60000000 +#define Mac_HT_Fail 0x70000000 +#define Mac_HT_FasleAlarm 0x90000000 +#define Mac_DropPacket 0xA0000000 + +#ifdef CONFIG_RF_POWER_TRIM +#if defined(CONFIG_RTL8723B) + #define REG_RF_BB_GAIN_OFFSET 0x7f + #define RF_GAIN_OFFSET_MASK 0xfffff +#elif defined(CONFIG_RTL8188E) + #define REG_RF_BB_GAIN_OFFSET 0x55 + #define RF_GAIN_OFFSET_MASK 0xfffff +#else + #define REG_RF_BB_GAIN_OFFSET 0x55 + #define RF_GAIN_OFFSET_MASK 0xfffff +#endif /* CONFIG_RTL8723B */ +#endif /*CONFIG_RF_POWER_TRIM*/ + /* For store initial value of BB register */ typedef struct _BB_INIT_REGISTER { u16 offset; @@ -172,8 +220,8 @@ struct auto_chan_sel { #define MACADDR_FILE_FAILED 1 #define MACADDR_FILE_LOADED 2 -#define KFREE_FLAG_ON BIT0 -#define KFREE_FLAG_THERMAL_K_ON BIT1 +#define KFREE_FLAG_ON BIT(0) +#define KFREE_FLAG_THERMAL_K_ON BIT(1) #define MAX_IQK_INFO_BACKUP_CHNL_NUM 5 #define MAX_IQK_INFO_BACKUP_REG_NUM 10 @@ -182,7 +230,7 @@ struct kfree_data_t { u8 flag; s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX]; -#ifdef CONFIG_NL80211_BAND_5GHZ +#ifdef CONFIG_IEEE80211_BAND_5GHZ s8 pa_bias_5g[RF_PATH_MAX]; s8 pad_bias_5g[RF_PATH_MAX]; #endif @@ -192,47 +240,142 @@ struct kfree_data_t { bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data); struct hal_spec_t { + char *ic_name; u8 macid_num; u8 sec_cam_ent_num; u8 sec_cap; - u8 nss_num; + u8 rfpath_num_2g:4; /* used for tx power index path */ + u8 rfpath_num_5g:4; /* used for tx power index path */ + + u8 max_tx_cnt; + u8 tx_nss_num:4; + u8 rx_nss_num:4; u8 band_cap; /* value of BAND_CAP_XXX */ u8 bw_cap; /* value of BW_CAP_XXX */ u8 port_num; u8 proto_cap; /* value of PROTO_CAP_XXX */ u8 wl_func; /* value of WL_FUNC_XXX */ + u8 hci_type; /* value of HCI Type */ }; +#define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path)) +#define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path)) +#define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \ + _band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \ + _band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0) + +#define HAL_SPEC_CHK_TX_CNT(_spec, _cnt_idx) ((_spec)->max_tx_cnt > (_cnt_idx)) + +#ifdef CONFIG_PHY_CAPABILITY_QUERY +struct phy_spec_t { + u32 trx_cap; + u32 stbc_cap; + u32 ldpc_cap; + u32 txbf_param; + u32 txbf_cap; +}; +#endif struct hal_iqk_reg_backup { u8 central_chnl; u8 bw_mode; u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM]; }; + +typedef struct hal_p2p_ps_para { + /*DW0*/ + u8 offload_en:1; + u8 role:1; + u8 ctwindow_en:1; + u8 noa_en:1; + u8 noa_sel:1; + u8 all_sta_sleep:1; + u8 discovery:1; + u8 rsvd2:1; + u8 p2p_port_id; + u8 p2p_group; + u8 p2p_macid; + + /*DW1*/ + u8 ctwindow_length; + u8 rsvd3; + u8 rsvd4; + u8 rsvd5; + + /*DW2*/ + u32 noa_duration_para; + + /*DW3*/ + u32 noa_interval_para; + + /*DW4*/ + u32 noa_start_time_para; + + /*DW5*/ + u32 noa_count_para; +} HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA; + +#define TXPWR_LMT_RS_CCK 0 +#define TXPWR_LMT_RS_OFDM 1 +#define TXPWR_LMT_RS_HT 2 +#define TXPWR_LMT_RS_VHT 3 +#define TXPWR_LMT_RS_NUM 4 + +#define TXPWR_LMT_RS_NUM_2G 4 /* CCK, OFDM, HT, VHT */ +#define TXPWR_LMT_RS_NUM_5G 3 /* OFDM, HT, VHT */ + +#ifdef CONFIG_TXPWR_LIMIT +extern const char *const _txpwr_lmt_rs_str[]; +#define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)]) + +struct txpwr_lmt_ent { + _list list; + + s8 lmt_2g[MAX_2_4G_BANDWIDTH_NUM] + [TXPWR_LMT_RS_NUM_2G] + [CENTER_CH_2G_NUM] + [MAX_TX_COUNT]; + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + s8 lmt_5g[MAX_5G_BANDWIDTH_NUM] + [TXPWR_LMT_RS_NUM_5G] + [CENTER_CH_5G_ALL_NUM] + [MAX_TX_COUNT]; +#endif + + char regd_name[0]; +}; +#endif /* CONFIG_TXPWR_LIMIT */ + typedef struct hal_com_data { - HAL_VERSION VersionID; + HAL_VERSION version_id; RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */ RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */ RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */ u8 hw_init_completed; /****** FW related ******/ - u16 FirmwareVersion; + u32 firmware_size; + u16 firmware_version; u16 FirmwareVersionRev; - u16 FirmwareSubVersion; + u16 firmware_sub_version; u16 FirmwareSignature; u8 RegFWOffload; + u8 bFWReady; u8 fw_ractrl; u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/ u8 LastHMEBoxNum; /* H2C - for host message to fw */ /****** current WIFI_PHY values ******/ WIRELESS_MODE CurrentWirelessMode; - CHANNEL_WIDTH CurrentChannelBW; - BAND_TYPE CurrentBandType; /* 0:2.4G, 1:5G */ + CHANNEL_WIDTH current_channel_bw; + BAND_TYPE current_band_type; /* 0:2.4G, 1:5G */ BAND_TYPE BandSet; - u8 CurrentChannel; + u8 current_channel; + u8 cch_20; + u8 cch_40; + u8 cch_80; u8 CurrentCenterFrequencyIndex1; u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */ u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ @@ -247,6 +390,11 @@ typedef struct hal_com_data { BOOLEAN bSWToBW80M; BOOLEAN bChnlBWInitialized; u32 BackUp_BB_REG_4_2nd_CCA[3]; + +#ifdef CONFIG_CHNL_LOAD_MAGT + u16 clm_result[MAX_CHANNEL_NUM]; + u16 clm_period; +#endif #ifdef CONFIG_AUTO_CHNL_SEL_NHM struct auto_chan_sel acs; #endif @@ -255,6 +403,7 @@ typedef struct hal_com_data { u8 rf_type; u8 PackageType; u8 NumTotalRFPath; + u8 antenna_test; /****** Debug ******/ u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ @@ -262,6 +411,7 @@ typedef struct hal_com_data { u8 bDumpRxPkt; u8 bDumpTxPkt; u8 bDisableTXPowerTraining; + u8 dis_turboedca; /****** EEPROM setting.******/ @@ -289,14 +439,17 @@ typedef struct hal_com_data { u8 EEPROMSubCustomerID; u8 EEPROMVersion; u8 EEPROMRegulatory; - u8 EEPROMThermalMeter; + u8 eeprom_thermal_meter; u8 EEPROMBluetoothCoexist; u8 EEPROMBluetoothType; u8 EEPROMBluetoothAntNum; u8 EEPROMBluetoothAntIsolation; u8 EEPROMBluetoothRadioShared; - u8 bTXPowerDataReadFromEEPORM; u8 EEPROMMACAddr[ETH_ALEN]; + u8 tx_bbswing_24G; + u8 tx_bbswing_5G; + u8 efuse0x3d7; /* efuse[0x3D7] */ + u8 efuse0x3d8; /* efuse[0x3D8] */ #ifdef CONFIG_RF_POWER_TRIM u8 EEPROMRFGainOffset; @@ -315,126 +468,45 @@ typedef struct hal_com_data { EFUSE_HAL EfuseHal; /*---------------------------------------------------------------------------------*/ - /* 3 [2.4G] */ + /* 2.4G TX power info for target TX power*/ u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; - /* If only one tx, only BW20 and OFDM are used. */ s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; - /* 3 [5G] */ + + /* 5G TX power info for target TX power*/ +#ifdef CONFIG_IEEE80211_BAND_5GHZ u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM]; u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM]; s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; - - u8 Regulation2_4G; - u8 Regulation5G; - - u8 TxPwrInPercentage; - - /******************************** - * TX power by rate table at most 4RF path. - * The register is - * - * VHT TX power by rate off setArray = - * Band:-2G&5G = 0 / 1 - * RF: at most 4*4 = ABCD=0/1/2/3 - * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 - **********************************/ - u8 TxPwrByRateTable; - u8 TxPwrByRateBand; - s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] - [TX_PWR_BY_RATE_NUM_RF] - [TX_PWR_BY_RATE_NUM_RF] - [TX_PWR_BY_RATE_NUM_RATE]; - -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI - s8 TxPwrByRate[TX_PWR_BY_RATE_NUM_BAND] - [TX_PWR_BY_RATE_NUM_RF] - [TX_PWR_BY_RATE_NUM_RF] - [TX_PWR_BY_RATE_NUM_RATE]; -#endif - /* --------------------------------------------------------------------------------- */ - -#if 0 - /* 2 Power Limit Table */ - u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; - u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */ - u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */ - s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* HT 20<->40 Pwr diff */ - u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* For HT<->legacy pwr diff */ #endif - u8 tx_pwr_lmt_5g_20_40_ref; - - /* Power Limit Table for 2.4G */ - s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM] - [MAX_2_4G_BANDWIDTH_NUM] - [MAX_RATE_SECTION_NUM] - [CENTER_CH_2G_NUM] - [MAX_RF_PATH]; + u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND] + [TX_PWR_BY_RATE_NUM_RF]; - /* Power Limit Table for 5G */ - s8 TxPwrLimit_5G[MAX_REGULATION_NUM] - [MAX_5G_BANDWIDTH_NUM] - [MAX_RATE_SECTION_NUM] - [CENTER_CH_5G_ALL_NUM] - [MAX_RF_PATH]; - - -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI - s8 TxPwrLimit_2_4G_Original[MAX_REGULATION_NUM] - [MAX_2_4G_BANDWIDTH_NUM] - [MAX_RATE_SECTION_NUM] - [CENTER_CH_2G_NUM] - [MAX_RF_PATH]; - - - s8 TxPwrLimit_5G_Original[MAX_REGULATION_NUM] - [MAX_5G_BANDWIDTH_NUM] - [MAX_RATE_SECTION_NUM] - [CENTER_CH_5G_ALL_NUM] - [MAX_RF_PATH]; - -#endif + s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] + [TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RATE]; - /* Store the original power by rate value of the base of each rate section of rf path A & B */ + /* Store the original power by rate value of the base rate for each rate section and rf path */ u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] - [TX_PWR_BY_RATE_NUM_RF] - [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; + [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF] - [TX_PWR_BY_RATE_NUM_RF] - [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; + [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; - u8 txpwr_by_rate_loaded: 1; - u8 txpwr_by_rate_from_file: 1; - u8 txpwr_limit_loaded: 1; - u8 txpwr_limit_from_file: 1; - u8 RfPowerTrackingType; - - /* For power group */ - /* - u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; - u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; - */ - u8 PGMaxGroup; - - /* The current Tx Power Level */ - u8 CurrentCckTxPwrIdx; - u8 CurrentOfdm24GTxPwrIdx; - u8 CurrentBW2024GTxPwrIdx; - u8 CurrentBW4024GTxPwrIdx; + u8 txpwr_by_rate_loaded:1; + u8 txpwr_by_rate_from_file:1; + u8 txpwr_limit_loaded:1; + u8 txpwr_limit_from_file:1; + u8 rf_power_tracking_type; /* Read/write are allow for following hardware information variables */ - u8 pwrGroupCnt; - u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; - u32 CCKTxPowerLevelOriginalOffset; - - u8 CrystalCap; + u8 crystal_cap; u8 PAType_2G; u8 PAType_5G; @@ -442,17 +514,18 @@ typedef struct hal_com_data { u8 LNAType_5G; u8 ExternalPA_2G; u8 ExternalLNA_2G; - u8 ExternalPA_5G; - u8 ExternalLNA_5G; + u8 external_pa_5g; + u8 external_lna_5g; u16 TypeGLNA; u16 TypeGPA; u16 TypeALNA; u16 TypeAPA; - u16 RFEType; + u16 rfe_type; u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ - u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */ - + u32 ac_param_be; /* Original parameter for BE, use for EDCA turbo. */ + u8 is_turbo_edca; + u8 prv_traffic_idx; BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; /* Radio A/B/C/D */ u32 RfRegChnlVal[MAX_RF_PATH]; @@ -460,33 +533,27 @@ typedef struct hal_com_data { /* RDG enable */ BOOLEAN bRDGEnable; - u8 RegTxPause; - /* Beacon function related global variable. */ - u8 RegBcnCtrlVal; - u8 RegFwHwTxQCtrl; - u8 RegReg542; - u8 RegCR_1; - u8 Reg837; - u16 RegRRSR; - + u16 RegRRSR; /****** antenna diversity ******/ u8 AntDivCfg; + u8 with_extenal_ant_switch; + u8 b_fix_tx_ant; u8 AntDetection; u8 TRxAntDivType; u8 ant_path; /* for 8723B s0/s1 selection */ - u32 AntennaTxPath; /* Antenna path Tx */ + u32 antenna_tx_path; /* Antenna path Tx */ u32 AntennaRxPath; /* Antenna path Rx */ u8 sw_antdiv_bl_state; /******** PHY DM & DM Section **********/ - u8 DM_Type; _lock IQKSpinLock; u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; /* Upper and Lower Signal threshold for Rate Adaptive*/ - int EntryMinUndecoratedSmoothedPWDB; - int EntryMaxUndecoratedSmoothedPWDB; - int MinUndecoratedPWDBForDM; - DM_ODM_T odmpriv; + int entry_min_undecorated_smoothed_pwdb; + int entry_max_undecorated_smoothed_pwdb; + int min_undecorated_pwdb_for_dm; + struct PHY_DM_STRUCT odmpriv; + u64 bk_rf_ability; u8 bIQKInitialized; u8 bNeedIQK; u8 IQK_MP_Switch; @@ -553,7 +620,7 @@ typedef struct hal_com_data { /* SDIO Rx FIFO related. */ /* */ u8 SdioRxFIFOCnt; - u16 SdioRxFIFOSize; + u32 SdioRxFIFOSize; #ifndef RTW_HALMAC u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */ @@ -565,9 +632,17 @@ typedef struct hal_com_data { u16 tx_extra_page; u16 tx_pub_page; u16 max_oqt_page; + #ifdef XMIT_BUF_SIZE u32 max_xmit_size_vovi; u32 max_xmit_size_bebk; -#endif + #endif /*XMIT_BUF_SIZE*/ + u16 max_xmit_page; + u16 max_xmit_page_vo; + u16 max_xmit_page_vi; + u16 max_xmit_page_be; + u16 max_xmit_page_bk; + +#endif /*#ifdef CONFIG_RTL8821C*/ #endif /* !RTW_HALMAC */ #endif /* CONFIG_SDIO_HCI */ @@ -578,11 +653,11 @@ typedef struct hal_com_data { BOOLEAN UsbTxVeryHighSpeedMode; u32 UsbBulkOutSize; BOOLEAN bSupportUSB3; + u8 usb_intf_start; /* Interrupt relatd register information. */ u32 IntArray[3];/* HISR0,HISR1,HSISR */ u32 IntrMask[3]; - u8 C2hArray[16]; #ifdef CONFIG_USB_TX_AGGREGATION u8 UsbTxAggMode; u8 UsbTxAggDescNum; @@ -613,6 +688,7 @@ typedef struct hal_com_data { BOOLEAN bL1OffSupport; BOOLEAN bSupportBackDoor; + u32 pci_backdoor_ctrl; u8 bDefaultAntenna; @@ -668,7 +744,9 @@ typedef struct hal_com_data { #endif struct hal_spec_t hal_spec; - +#ifdef CONFIG_PHY_CAPABILITY_QUERY + struct phy_spec_t phy_spec; +#endif u8 RfKFreeEnable; u8 RfKFree_ch_group; BOOLEAN bCCKinCH14; @@ -682,11 +760,18 @@ typedef struct hal_com_data { struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM]; +#ifdef RTW_HALMAC + u8 drv_rsvd_page_number; +#endif + #ifdef CONFIG_BEAMFORMING + u8 backup_snd_ptcl_ctrl; #ifdef RTW_BEAMFORMING_VERSION_2 struct beamforming_info beamforming_info; #endif /* RTW_BEAMFORMING_VERSION_2 */ #endif /* CONFIG_BEAMFORMING */ + + u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/ } HAL_DATA_COMMON, *PHAL_DATA_COMMON; @@ -722,4 +807,260 @@ typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; int rtw_halmac_deinit_adapter(struct dvobj_priv *); #endif /* RTW_HALMAC */ +/* alias for phydm coding style */ +#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance +#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold +#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack +#define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage +#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 +#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 +#define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar +#define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar + +#define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW +#define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter +#define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1 +#define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter +#define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE +#define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1 +#define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter +#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack +#define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE +#define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW +#define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl +#define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock +#define REG_FPGA1_TX_INFO rFPGA1_TxInfo +#define REG_IQK_AGC_CONT rIQK_AGC_Cont +#define REG_IQK_AGC_PTS rIQK_AGC_Pts +#define REG_IQK_AGC_RSP rIQK_AGC_Rsp +#define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable +#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold +#define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta +#define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar +#define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable +#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 +#define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance +#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance +#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 +#define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance +#define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance +#define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE +#define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE + +/*#define REG_A_CFO_LONG_DUMP_92E rA_CfoLongDump_92E*/ +#define REG_A_CFO_LONG_DUMP_JAGUAR rA_CfoLongDump_Jaguar +/*#define REG_A_CFO_SHORT_DUMP_92E rA_CfoShortDump_92E*/ +#define REG_A_CFO_SHORT_DUMP_JAGUAR rA_CfoShortDump_Jaguar +#define REG_A_RFE_PINMUX_JAGUAR rA_RFE_Pinmux_Jaguar +/*#define REG_A_RSSI_DUMP_92E rA_RSSIDump_92E*/ +#define REG_A_RSSI_DUMP_JAGUAR rA_RSSIDump_Jaguar +/*#define REG_A_RX_SNR_DUMP_92E rA_RXsnrDump_92E*/ +#define REG_A_RX_SNR_DUMP_JAGUAR rA_RXsnrDump_Jaguar +/*#define REG_A_TX_AGC rA_TXAGC*/ +#define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar +#define REG_BW_INDICATION_JAGUAR rBWIndication_Jaguar +/*#define REG_B_BBSWING rB_BBSWING*/ +/*#define REG_B_CFO_LONG_DUMP_92E rB_CfoLongDump_92E*/ +#define REG_B_CFO_LONG_DUMP_JAGUAR rB_CfoLongDump_Jaguar +/*#define REG_B_CFO_SHORT_DUMP_92E rB_CfoShortDump_92E*/ +#define REG_B_CFO_SHORT_DUMP_JAGUAR rB_CfoShortDump_Jaguar +/*#define REG_B_RSSI_DUMP_92E rB_RSSIDump_92E*/ +#define REG_B_RSSI_DUMP_JAGUAR rB_RSSIDump_Jaguar +/*#define REG_B_RX_SNR_DUMP_92E rB_RXsnrDump_92E*/ +#define REG_B_RX_SNR_DUMP_JAGUAR rB_RXsnrDump_Jaguar +/*#define REG_B_TX_AGC rB_TXAGC*/ +#define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar +#define REG_BLUE_TOOTH rBlue_Tooth +#define REG_CCK_0_AFE_SETTING rCCK0_AFESetting +/*#define REG_C_BBSWING rC_BBSWING*/ +/*#define REG_C_TX_AGC rC_TXAGC*/ +#define REG_C_TX_SCALE_JAGUAR2 rC_TxScale_Jaguar2 +#define REG_CONFIG_ANT_A rConfig_AntA +#define REG_CONFIG_ANT_B rConfig_AntB +#define REG_CONFIG_PMPD_ANT_A rConfig_Pmpd_AntA +#define REG_CONFIG_PMPD_ANT_B rConfig_Pmpd_AntB +#define REG_DPDT_CONTROL rDPDT_control +/*#define REG_D_BBSWING rD_BBSWING*/ +/*#define REG_D_TX_AGC rD_TXAGC*/ +#define REG_D_TX_SCALE_JAGUAR2 rD_TxScale_Jaguar2 +#define REG_FPGA0_ANALOG_PARAMETER4 rFPGA0_AnalogParameter4 +#define REG_FPGA0_IQK rFPGA0_IQK +#define REG_FPGA0_PSD_FUNCTION rFPGA0_PSDFunction +#define REG_FPGA0_PSD_REPORT rFPGA0_PSDReport +#define REG_FPGA0_RFMOD rFPGA0_RFMOD +#define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage +#define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW +#define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter +#define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1 +#define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter +#define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE +#define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1 +#define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter +#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack +#define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE +#define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW +#define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl +#define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock +#define REG_FPGA1_TX_INFO rFPGA1_TxInfo +#define REG_IQK_AGC_CONT rIQK_AGC_Cont +#define REG_IQK_AGC_PTS rIQK_AGC_Pts +#define REG_IQK_AGC_RSP rIQK_AGC_Rsp +#define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable +#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold +#define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta +#define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar +#define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable +#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 +#define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance +#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance +#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 +#define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance +#define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance +#define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE +#define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE +#define REG_PMPD_ANAEN rPMPD_ANAEN +#define REG_PDP_ANT_A rPdp_AntA +#define REG_PDP_ANT_A_4 rPdp_AntA_4 +#define REG_PDP_ANT_B rPdp_AntB +#define REG_PDP_ANT_B_4 rPdp_AntB_4 +#define REG_PWED_TH_JAGUAR rPwed_TH_Jaguar +#define REG_RX_CCK rRx_CCK +#define REG_RX_IQK rRx_IQK +#define REG_RX_IQK_PI_A rRx_IQK_PI_A +#define REG_RX_IQK_PI_B rRx_IQK_PI_B +#define REG_RX_IQK_TONE_A rRx_IQK_Tone_A +#define REG_RX_IQK_TONE_B rRx_IQK_Tone_B +#define REG_RX_OFDM rRx_OFDM +#define REG_RX_POWER_AFTER_IQK_A_2 rRx_Power_After_IQK_A_2 +#define REG_RX_POWER_AFTER_IQK_B_2 rRx_Power_After_IQK_B_2 +#define REG_RX_POWER_BEFORE_IQK_A_2 rRx_Power_Before_IQK_A_2 +#define REG_RX_POWER_BEFORE_IQK_B_2 rRx_Power_Before_IQK_B_2 +#define REG_RX_TO_RX rRx_TO_Rx +#define REG_RX_WAIT_CCA rRx_Wait_CCA +#define REG_RX_WAIT_RIFS rRx_Wait_RIFS +#define REG_S0_S1_PATH_SWITCH rS0S1_PathSwitch +/*#define REG_S1_RXEVM_DUMP_92E rS1_RXevmDump_92E*/ +#define REG_S1_RXEVM_DUMP_JAGUAR rS1_RXevmDump_Jaguar +/*#define REG_S2_RXEVM_DUMP_92E rS2_RXevmDump_92E*/ +#define REG_S2_RXEVM_DUMP_JAGUAR rS2_RXevmDump_Jaguar +#define REG_SYM_WLBT_PAPE_SEL rSYM_WLBT_PAPE_SEL +#define REG_SINGLE_TONE_CONT_TX_JAGUAR rSingleTone_ContTx_Jaguar +#define REG_SLEEP rSleep +#define REG_STANDBY rStandby +#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR rTxAGC_A_CCK11_CCK1_JAguar +#define REG_TX_AGC_A_CCK_1_MCS32 rTxAGC_A_CCK1_Mcs32 +#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR rTxAGC_A_MCS11_MCS8_JAguar +#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR rTxAGC_A_MCS15_MCS12_JAguar +#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR rTxAGC_A_MCS19_MCS16_JAguar +#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR rTxAGC_A_MCS23_MCS20_JAguar +#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR rTxAGC_A_MCS3_MCS0_JAguar +#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR rTxAGC_A_MCS7_MCS4_JAguar +#define REG_TX_AGC_A_MCS03_MCS00 rTxAGC_A_Mcs03_Mcs00 +#define REG_TX_AGC_A_MCS07_MCS04 rTxAGC_A_Mcs07_Mcs04 +#define REG_TX_AGC_A_MCS11_MCS08 rTxAGC_A_Mcs11_Mcs08 +#define REG_TX_AGC_A_MCS15_MCS12 rTxAGC_A_Mcs15_Mcs12 +#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_A_Nss1Index3_Nss1Index0_JAguar +#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_A_Nss1Index7_Nss1Index4_JAguar +#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_A_Nss2Index1_Nss1Index8_JAguar +#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_A_Nss2Index5_Nss2Index2_JAguar +#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_A_Nss2Index9_Nss2Index6_JAguar +#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_A_Nss3Index3_Nss3Index0_JAguar +#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_A_Nss3Index7_Nss3Index4_JAguar +#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_A_Nss3Index9_Nss3Index8_JAguar +#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR rTxAGC_A_Ofdm18_Ofdm6_JAguar +#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR rTxAGC_A_Ofdm54_Ofdm24_JAguar +#define REG_TX_AGC_A_RATE18_06 rTxAGC_A_Rate18_06 +#define REG_TX_AGC_A_RATE54_24 rTxAGC_A_Rate54_24 +#define REG_TX_AGC_B_CCK_11_A_CCK_2_11 rTxAGC_B_CCK11_A_CCK2_11 +#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR rTxAGC_B_CCK11_CCK1_JAguar +#define REG_TX_AGC_B_CCK_1_55_MCS32 rTxAGC_B_CCK1_55_Mcs32 +#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR rTxAGC_B_MCS11_MCS8_JAguar +#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR rTxAGC_B_MCS15_MCS12_JAguar +#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR rTxAGC_B_MCS19_MCS16_JAguar +#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR rTxAGC_B_MCS23_MCS20_JAguar +#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR rTxAGC_B_MCS3_MCS0_JAguar +#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR rTxAGC_B_MCS7_MCS4_JAguar +#define REG_TX_AGC_B_MCS03_MCS00 rTxAGC_B_Mcs03_Mcs00 +#define REG_TX_AGC_B_MCS07_MCS04 rTxAGC_B_Mcs07_Mcs04 +#define REG_TX_AGC_B_MCS11_MCS08 rTxAGC_B_Mcs11_Mcs08 +#define REG_TX_AGC_B_MCS15_MCS12 rTxAGC_B_Mcs15_Mcs12 +#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_B_Nss1Index3_Nss1Index0_JAguar +#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_B_Nss1Index7_Nss1Index4_JAguar +#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_B_Nss2Index1_Nss1Index8_JAguar +#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_B_Nss2Index5_Nss2Index2_JAguar +#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_B_Nss2Index9_Nss2Index6_JAguar +#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_B_Nss3Index3_Nss3Index0_JAguar +#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_B_Nss3Index7_Nss3Index4_JAguar +#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_B_Nss3Index9_Nss3Index8_JAguar +#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR rTxAGC_B_Ofdm18_Ofdm6_JAguar +#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR rTxAGC_B_Ofdm54_Ofdm24_JAguar +#define REG_TX_AGC_B_RATE18_06 rTxAGC_B_Rate18_06 +#define REG_TX_AGC_B_RATE54_24 rTxAGC_B_Rate54_24 +#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR rTxAGC_C_CCK11_CCK1_JAguar +#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR rTxAGC_C_MCS11_MCS8_JAguar +#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR rTxAGC_C_MCS15_MCS12_JAguar +#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR rTxAGC_C_MCS19_MCS16_JAguar +#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR rTxAGC_C_MCS23_MCS20_JAguar +#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR rTxAGC_C_MCS3_MCS0_JAguar +#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR rTxAGC_C_MCS7_MCS4_JAguar +#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_C_Nss1Index3_Nss1Index0_JAguar +#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_C_Nss1Index7_Nss1Index4_JAguar +#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_C_Nss2Index1_Nss1Index8_JAguar +#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_C_Nss2Index5_Nss2Index2_JAguar +#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_C_Nss2Index9_Nss2Index6_JAguar +#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_C_Nss3Index3_Nss3Index0_JAguar +#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_C_Nss3Index7_Nss3Index4_JAguar +#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_C_Nss3Index9_Nss3Index8_JAguar +#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR rTxAGC_C_Ofdm18_Ofdm6_JAguar +#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR rTxAGC_C_Ofdm54_Ofdm24_JAguar +#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR rTxAGC_D_CCK11_CCK1_JAguar +#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR rTxAGC_D_MCS11_MCS8_JAguar +#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR rTxAGC_D_MCS15_MCS12_JAguar +#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR rTxAGC_D_MCS19_MCS16_JAguar +#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR rTxAGC_D_MCS23_MCS20_JAguar +#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR rTxAGC_D_MCS3_MCS0_JAguar +#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR rTxAGC_D_MCS7_MCS4_JAguar +#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_D_Nss1Index3_Nss1Index0_JAguar +#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_D_Nss1Index7_Nss1Index4_JAguar +#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_D_Nss2Index1_Nss1Index8_JAguar +#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_D_Nss2Index5_Nss2Index2_JAguar +#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_D_Nss2Index9_Nss2Index6_JAguar +#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_D_Nss3Index3_Nss3Index0_JAguar +#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_D_Nss3Index7_Nss3Index4_JAguar +#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_D_Nss3Index9_Nss3Index8_JAguar +#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR rTxAGC_D_Ofdm18_Ofdm6_JAguar +#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR rTxAGC_D_Ofdm54_Ofdm24_JAguar +#define REG_TX_PATH_JAGUAR rTxPath_Jaguar +#define REG_TX_CCK_BBON rTx_CCK_BBON +#define REG_TX_CCK_RFON rTx_CCK_RFON +#define REG_TX_IQK rTx_IQK +#define REG_TX_IQK_PI_A rTx_IQK_PI_A +#define REG_TX_IQK_PI_B rTx_IQK_PI_B +#define REG_TX_IQK_TONE_A rTx_IQK_Tone_A +#define REG_TX_IQK_TONE_B rTx_IQK_Tone_B +#define REG_TX_OFDM_BBON rTx_OFDM_BBON +#define REG_TX_OFDM_RFON rTx_OFDM_RFON +#define REG_TX_POWER_AFTER_IQK_A rTx_Power_After_IQK_A +#define REG_TX_POWER_AFTER_IQK_B rTx_Power_After_IQK_B +#define REG_TX_POWER_BEFORE_IQK_A rTx_Power_Before_IQK_A +#define REG_TX_POWER_BEFORE_IQK_B rTx_Power_Before_IQK_B +#define REG_TX_TO_RX rTx_To_Rx +#define REG_TX_TO_TX rTx_To_Tx +#define REG_APK rAPK +#define REG_ANTSEL_SW_JAGUAR r_ANTSEL_SW_Jaguar + + + +#define rf_welut_jaguar RF_WeLut_Jaguar +#define rf_mode_table_addr RF_ModeTableAddr +#define rf_mode_table_data0 RF_ModeTableData0 +#define rf_mode_table_data1 RF_ModeTableData1 + + + + + + +#define RX_SMOOTH_FACTOR Rx_Smooth_Factor + #endif /* __HAL_DATA_H__ */ diff --git a/include/hal_gspi.h b/include/hal_gspi.h index 68119c5..51d491c 100644 --- a/include/hal_gspi.h +++ b/include/hal_gspi.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_GSPI_H_ #define __HAL_GSPI_H_ diff --git a/include/hal_ic_cfg.h b/include/hal_ic_cfg.h index eb5eae2..5432b16 100644 --- a/include/hal_ic_cfg.h +++ b/include/hal_ic_cfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_IC_CFG_H__ #define __HAL_IC_CFG_H__ @@ -34,6 +29,8 @@ #define RTL8822B_SUPPORT 0 #define RTL8821B_SUPPORT 0 #define RTL8821C_SUPPORT 0 +#define RTL8710B_SUPPORT 0 +#define RTL8814B_SUPPORT 0 /*#if (RTL8188E_SUPPORT==1)*/ #define RATE_ADAPTIVE_SUPPORT 0 @@ -50,56 +47,162 @@ #define RTL8188E_SUPPORT 1 #define RATE_ADAPTIVE_SUPPORT 1 #define POWER_TRAINING_ACTIVE 1 + #define CONFIG_GET_RAID_BY_DRV #endif #ifdef CONFIG_RTL8812A #undef RTL8812A_SUPPORT #define RTL8812A_SUPPORT 1 + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif #endif #ifdef CONFIG_RTL8821A #undef RTL8821A_SUPPORT #define RTL8821A_SUPPORT 1 + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif #endif #ifdef CONFIG_RTL8192E #undef RTL8192E_SUPPORT #define RTL8192E_SUPPORT 1 + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif #endif #ifdef CONFIG_RTL8723B #undef RTL8723B_SUPPORT #define RTL8723B_SUPPORT 1 + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif #endif #ifdef CONFIG_RTL8723D #undef RTL8723D_SUPPORT #define RTL8723D_SUPPORT 1 + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif + #ifndef CONFIG_RTW_MAC_HIDDEN_RPT + #define CONFIG_RTW_MAC_HIDDEN_RPT + #endif + #ifndef CONFIG_RTW_CUSTOMER_STR + #define CONFIG_RTW_CUSTOMER_STR + #endif #endif #ifdef CONFIG_RTL8814A #undef RTL8814A_SUPPORT #define RTL8814A_SUPPORT 1 + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif #endif #ifdef CONFIG_RTL8703B #undef RTL8703B_SUPPORT #define RTL8703B_SUPPORT 1 + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif + #ifndef CONFIG_RTW_MAC_HIDDEN_RPT + #define CONFIG_RTW_MAC_HIDDEN_RPT + #endif #endif #ifdef CONFIG_RTL8188F #undef RTL8188F_SUPPORT #define RTL8188F_SUPPORT 1 + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif + #ifndef CONFIG_RTW_MAC_HIDDEN_RPT + #define CONFIG_RTW_MAC_HIDDEN_RPT + #endif + #ifndef CONFIG_RTW_CUSTOMER_STR + #define CONFIG_RTW_CUSTOMER_STR + #endif #endif #ifdef CONFIG_RTL8822B #undef RTL8822B_SUPPORT #define RTL8822B_SUPPORT 1 -#endif + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif /* CONFIG_FW_C2H_PKT */ + #define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */ + #define CONFIG_DFS /* Enable 5G band 2&3 channel */ + + #ifdef CONFIG_WOWLAN + #define CONFIG_GTK_OL + #define CONFIG_ARP_KEEP_ALIVE + #ifndef CONFIG_DEFAULT_PATTERNS_EN + #warning "Force to enable CONFIG_DEFAULT_PATTERNS_EN under WOW" + #define CONFIG_DEFAULT_PATTERNS_EN + #endif /* !CONFIG_DEFAULT_PATTERNS_EN */ + + #ifdef CONFIG_GPIO_WAKEUP + #ifndef WAKEUP_GPIO_IDX + #define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */ + #endif /* !WAKEUP_GPIO_IDX */ + #endif /* CONFIG_GPIO_WAKEUP */ + + #endif /* CONFIG_WOWLAN */ + #ifdef CONFIG_CONCURRENT_MODE + #define CONFIG_AP_PORT_SWAP + #define CONFIG_FW_MULTI_PORT_SUPPORT + #endif /* CONFIG_CONCURRENT_MODE */ + + /* + * Beamforming related definition + */ + /* Beamforming mechanism is on driver not phydm, always disable it */ + #define BEAMFORMING_SUPPORT 0 + /* Only support new beamforming mechanism */ + #ifdef CONFIG_BEAMFORMING + #define RTW_BEAMFORMING_VERSION_2 + #endif /* CONFIG_BEAMFORMING */ + + #ifndef CONFIG_RTW_MAC_HIDDEN_RPT + #define CONFIG_RTW_MAC_HIDDEN_RPT + #endif /* CONFIG_RTW_MAC_HIDDEN_RPT */ + + #ifndef DBG_RX_DFRAME_RAW_DATA + #define DBG_RX_DFRAME_RAW_DATA + #endif /* DBG_RX_DFRAME_RAW_DATA */ + + #ifndef RTW_IQK_FW_OFFLOAD + #define RTW_IQK_FW_OFFLOAD + #endif /* RTW_IQK_FW_OFFLOAD */ +#endif /* CONFIG_RTL8822B */ #ifdef CONFIG_RTL8821C #undef RTL8821C_SUPPORT #define RTL8821C_SUPPORT 1 + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif + #ifdef CONFIG_NO_FW + #ifdef CONFIG_RTW_MAC_HIDDEN_RPT + #undef CONFIG_RTW_MAC_HIDDEN_RPT + #endif + #else + #ifndef CONFIG_RTW_MAC_HIDDEN_RPT + #define CONFIG_RTW_MAC_HIDDEN_RPT + #endif + #endif + #define LOAD_FW_HEADER_FROM_DRIVER + #define CONFIG_PHY_CAPABILITY_QUERY + #ifdef CONFIG_CONCURRENT_MODE + #define CONFIG_AP_PORT_SWAP + #define CONFIG_FW_MULTI_PORT_SUPPORT + #endif + #define CONFIG_SUPPORT_FIFO_DUMP #endif #endif /*__HAL_IC_CFG_H__*/ diff --git a/include/hal_intf.h b/include/hal_intf.h index 61c6d9e..2ca849d 100644 --- a/include/hal_intf.h +++ b/include/hal_intf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_INTF_H__ #define __HAL_INTF_H__ @@ -45,6 +40,14 @@ enum _CHIP_TYPE { MAX_CHIP_TYPE }; +#ifdef RTW_HALMAC +enum fw_mem { + FW_EMEM, + FW_IMEM, + FW_DMEM, +}; +#endif + extern const u32 _chip_type_to_odm_ic_type[]; #define chip_type_to_odm_ic_type(chip_type) (((chip_type) >= MAX_CHIP_TYPE) ? _chip_type_to_odm_ic_type[MAX_CHIP_TYPE] : _chip_type_to_odm_ic_type[(chip_type)]) @@ -87,6 +90,9 @@ typedef enum _HW_VARIABLES { HW_VAR_AC_PARAM_BE, HW_VAR_AC_PARAM_BK, HW_VAR_ACM_CTRL, +#ifdef CONFIG_WMMPS + HW_VAR_UAPSD_TID, +#endif HW_VAR_AMPDU_MIN_SPACE, HW_VAR_AMPDU_FACTOR, HW_VAR_RXDMA_AGG_PG_TH, @@ -102,6 +108,9 @@ typedef enum _HW_VARIABLES { HW_VAR_LPS_POFF_DEINIT, HW_VAR_LPS_POFF_SET_MODE, HW_VAR_LPS_POFF_WOW_EN, +#endif +#ifdef CONFIG_LPS_PG + HW_VAR_LPS_PG_HANDLE, #endif HW_VAR_TRIGGER_GPIO_0, HW_VAR_BT_SET_COEXIST, @@ -122,14 +131,13 @@ typedef enum _HW_VARIABLES { #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) HW_VAR_WOWLAN, HW_VAR_WAKEUP_REASON, - HW_VAR_RPWM_TOG, #endif + HW_VAR_RPWM_TOG, #ifdef CONFIG_GPIO_WAKEUP HW_SET_GPIO_WL_CTRL, #endif HW_VAR_SYS_CLKR, HW_VAR_NAV_UPPER, - HW_VAR_C2H_HANDLE, HW_VAR_RPT_TIMER_SETTING, HW_VAR_TX_RPT_MAX_MACID, HW_VAR_CHK_HI_QUEUE_EMPTY, @@ -149,6 +157,7 @@ typedef enum _HW_VARIABLES { HW_VAR_SOUNDING_FW_NDPA, HW_VAR_SOUNDING_CLK, HW_VAR_SOUNDING_SET_GID_TABLE, + HW_VAR_SOUNDING_CSI_REPORT, /*Add by YuChen for TXBF HW timer*/ HW_VAR_HW_REG_TIMER_INIT, HW_VAR_HW_REG_TIMER_RESTART, @@ -171,6 +180,11 @@ typedef enum _HW_VARIABLES { HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, HW_VAR_CH_SW_IQK_INFO_BACKUP, HW_VAR_CH_SW_IQK_INFO_RESTORE, + + HW_VAR_DBI, + HW_VAR_MDIO, + HW_VAR_L1OFF_CAPABILITY, + HW_VAR_L1OFF_NIC_SUPPORT, #ifdef CONFIG_TDLS HW_VAR_TDLS_WRCR, HW_VAR_TDLS_RS_RCR, @@ -246,14 +260,27 @@ typedef enum _HAL_INTF_PS_FUNC { HAL_MAX_ID, } HAL_INTF_PS_FUNC; -typedef s32(*c2h_id_filter)(u8 *c2h_evt); +typedef s32(*c2h_id_filter)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); + +struct txpwr_idx_comp; + +struct macid_cfg { + u8 mac_id; + u8 rate_id; + u8 bandwidth; + u8 short_gi; + u8 ignore_bw; + u8 rsvd; + u16 rsvd1; + u64 ra_mask; +}; struct hal_ops { /*** initialize section ***/ void (*read_chip_version)(_adapter *padapter); void (*init_default_value)(_adapter *padapter); void (*intf_chip_configure)(_adapter *padapter); - void (*read_adapter_info)(_adapter *padapter); + u8 (*read_adapter_info)(_adapter *padapter); u32(*hal_power_on)(_adapter *padapter); void (*hal_power_off)(_adapter *padapter); u32(*hal_init)(_adapter *padapter); @@ -279,6 +306,9 @@ struct hal_ops { /*** recv section ***/ s32(*init_recv_priv)(_adapter *padapter); void (*free_recv_priv)(_adapter *padapter); +#ifdef CONFIG_RECV_THREAD_MODE + s32 (*recv_hdl)(_adapter *adapter); +#endif #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) u32(*inirp_init)(_adapter *padapter); u32(*inirp_deinit)(_adapter *padapter); @@ -304,39 +334,36 @@ struct hal_ops { void (*InitSwLeds)(_adapter *padapter); void (*DeInitSwLeds)(_adapter *padapter); - - void (*set_bwmode_handler)(_adapter *padapter, CHANNEL_WIDTH Bandwidth, u8 Offset); - void (*set_channel_handler)(_adapter *padapter, u8 channel); void (*set_chnl_bw_handler)(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); void (*set_tx_power_level_handler)(_adapter *padapter, u8 channel); void (*get_tx_power_level_handler)(_adapter *padapter, s32 *powerlevel); void (*set_tx_power_index_handler)(_adapter *padapter, u32 powerindex, u8 rfpath, u8 rate); - u8(*get_tx_power_index_handler)(_adapter *padapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel); + u8(*get_tx_power_index_handler)(_adapter *padapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); void (*hal_dm_watchdog)(_adapter *padapter); #ifdef CONFIG_LPS_LCLK_WD_TIMER void (*hal_dm_watchdog_in_lps)(_adapter *padapter); #endif - void (*SetHwRegHandler)(_adapter *padapter, u8 variable, u8 *val); + + void (*set_hw_reg_handler)(_adapter *padapter, u8 variable, u8 *val); + void (*GetHwRegHandler)(_adapter *padapter, u8 variable, u8 *val); -#ifdef CONFIG_C2H_PACKET_EN - void (*SetHwRegHandlerWithBuf)(_adapter *padapter, u8 variable, u8 *pbuf, int len); -#endif - u8(*GetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); + + u8 (*get_hal_def_var_handler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); + u8(*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); void (*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2); void (*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet); - void (*UpdateRAMaskHandler)(_adapter *padapter, u32 mac_id, u8 rssi_level); + void (*update_ra_mask_handler)(_adapter *padapter, struct sta_info *psta, struct macid_cfg *h2c_macid_cfg); void (*SetBeaconRelatedRegistersHandler)(_adapter *padapter); - void (*Add_RateATid)(_adapter *padapter, u64 bitmap, u8 *arg, u8 rssi_level); u8(*interface_ps_func)(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val); u32(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask); @@ -373,12 +400,19 @@ struct hal_ops { #endif void (*hal_notch_filter)(_adapter *adapter, bool enable); - s32(*c2h_handler)(_adapter *padapter, u8 *c2h_evt); - c2h_id_filter c2h_id_filter_ccx; +#ifdef RTW_HALMAC + void (*hal_mac_c2h_handler)(_adapter *adapter, u8 *pbuf, u16 length); +#else + s32(*c2h_handler)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); +#endif + void (*reqtxrpt)(_adapter *padapter, u8 macid); s32(*fill_h2c_cmd)(PADAPTER, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); void (*fill_fake_txdesc)(PADAPTER, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); s32(*fw_dl)(_adapter *adapter, u8 wowlan); +#ifdef RTW_HALMAC + s32 (*fw_mem_dl)(_adapter *adapter, enum fw_mem mem); +#endif #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_PCI_HCI) void (*clear_interrupt)(_adapter *padapter); @@ -396,11 +430,10 @@ struct hal_ops { u8(*init_phy)(PADAPTER); #endif /* RTW_HALMAC */ -#ifdef CONFIG_NAPI - void (*napi_irq_disable)(PADAPTER Adapter); - void (*napi_irq_enable)(PADAPTER Adapter); - int (*napi_poll)(PADAPTER padapter, int budget); +#ifdef CONFIG_PCI_HCI + void (*hal_set_l1ssbackdoor_handler)(_adapter *padapter, u8 enable); #endif + }; typedef enum _RT_EEPROM_TYPE { @@ -576,18 +609,6 @@ struct wowlan_ioctl_param { unsigned int wakeup_reason; }; -#define Rx_Pairwisekey 0x01 -#define Rx_GTK 0x02 -#define Rx_DisAssoc 0x04 -#define Rx_DeAuth 0x08 -#define Rx_ARPReq 0x09 -#define FWDecisionDisconnect 0x10 -#define Rx_MagicPkt 0x21 -#define Rx_UnicastPkt 0x22 -#define Rx_PatternPkt 0x23 -#define RX_PNOWakeUp 0x55 -#define AP_WakeUp 0x66 - u8 rtw_hal_data_init(_adapter *padapter); void rtw_hal_data_deinit(_adapter *padapter); @@ -609,12 +630,8 @@ void rtw_hal_stop(_adapter *padapter); void rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val); void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val); -#ifdef CONFIG_C2H_PACKET_EN - void rtw_hal_set_hwreg_with_buf(_adapter *padapter, u8 variable, u8 *pbuf, int len); -#endif - void rtw_hal_chip_configure(_adapter *padapter); -void rtw_hal_read_chip_info(_adapter *padapter); +u8 rtw_hal_read_chip_info(_adapter *padapter); void rtw_hal_read_chip_version(_adapter *padapter); u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); @@ -635,6 +652,12 @@ u8 rtw_hal_check_ips_status(_adapter *padapter); #if defined(CONFIG_PCI_HCI) void rtw_hal_irp_reset(_adapter *padapter); +void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data); +u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr); +void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data); +u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr); +u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter); +u8 rtw_hal_pci_l1off_capability(_adapter *padapter); #endif u8 rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val); @@ -649,8 +672,8 @@ void rtw_hal_free_xmit_priv(_adapter *padapter); s32 rtw_hal_init_recv_priv(_adapter *padapter); void rtw_hal_free_recv_priv(_adapter *padapter); -void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level); -void rtw_hal_add_ra_tid(_adapter *padapter, u64 bitmap, u8 *arg, u8 rssi_level); +void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level, u8 is_update_bw); +void rtw_update_ramask(_adapter *padapter, struct sta_info *psta, u32 mac_id, u8 rssi_level, u8 is_update_bw); void rtw_hal_start_thread(_adapter *padapter); void rtw_hal_stop_thread(_adapter *padapter); @@ -662,13 +685,15 @@ void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data) u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask); void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); -#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask)) -#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data)) -#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask)) -#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) -#define PHY_SetMacReg PHY_SetBBReg -#define PHY_QueryMacReg PHY_QueryBBReg +#define phy_query_bb_reg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask)) +#define phy_set_bb_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data)) +#define phy_query_rf_reg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask)) +#define phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) + +#define phy_set_mac_reg phy_set_bb_reg +#define phy_query_mac_reg phy_query_bb_reg + #if defined(CONFIG_PCI_HCI) s32 rtw_hal_interrupt_handler(_adapter *padapter); @@ -677,8 +702,6 @@ void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMa void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf); #endif -void rtw_hal_set_bwmode(_adapter *padapter, CHANNEL_WIDTH Bandwidth, u8 Offset); -void rtw_hal_set_chan(_adapter *padapter, u8 channel); void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); void rtw_hal_dm_watchdog(_adapter *padapter); void rtw_hal_dm_watchdog_in_lps(_adapter *padapter); @@ -691,29 +714,44 @@ void rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel); #endif #ifdef DBG_CONFIG_ERROR_DETECT - void rtw_hal_sreset_init(_adapter *padapter); - void rtw_hal_sreset_reset(_adapter *padapter); - void rtw_hal_sreset_reset_value(_adapter *padapter); - void rtw_hal_sreset_xmit_status_check(_adapter *padapter); - void rtw_hal_sreset_linked_status_check(_adapter *padapter); - u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter); - bool rtw_hal_sreset_inprogress(_adapter *padapter); +void rtw_hal_sreset_init(_adapter *padapter); +void rtw_hal_sreset_reset(_adapter *padapter); +void rtw_hal_sreset_reset_value(_adapter *padapter); +void rtw_hal_sreset_xmit_status_check(_adapter *padapter); +void rtw_hal_sreset_linked_status_check(_adapter *padapter); +u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter); +bool rtw_hal_sreset_inprogress(_adapter *padapter); #endif #ifdef CONFIG_IOL - int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); +int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); #endif #ifdef CONFIG_XMIT_THREAD_MODE - s32 rtw_hal_xmit_thread_handler(_adapter *padapter); +s32 rtw_hal_xmit_thread_handler(_adapter *padapter); +#endif + +#ifdef CONFIG_RECV_THREAD_MODE +s32 rtw_hal_recv_hdl(_adapter *adapter); #endif void rtw_hal_notch_filter(_adapter *adapter, bool enable); +#ifdef CONFIG_FW_C2H_REG +bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload); bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf); s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf); -s32 rtw_hal_c2h_handler(_adapter *adapter, u8 *c2h_evt); -c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter); +#endif + +#ifdef CONFIG_FW_C2H_PKT +bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload); +#endif + +s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); +#ifndef RTW_HALMAC +s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); +s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); +#endif s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter); @@ -726,7 +764,7 @@ void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen, u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan); #ifdef CONFIG_GPIO_API - void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag); +void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag); int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num); void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num); #endif @@ -739,13 +777,14 @@ s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan); #endif void rtw_hal_set_tx_power_index(PADAPTER, u32 powerindex, u8 rfpath, u8 rate); -u8 rtw_hal_get_tx_power_index(PADAPTER, u8 rfpath, u8 rate, u8 bandwidth, u8 channel); +u8 rtw_hal_get_tx_power_index(PADAPTER, u8 rfpath, u8 rate, u8 bandwidth, u8 channel,struct txpwr_idx_comp *tic); u8 rtw_hal_ops_check(_adapter *padapter); #ifdef RTW_HALMAC u8 rtw_hal_init_mac_register(PADAPTER); u8 rtw_hal_init_phy(PADAPTER); +s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem); #endif /* RTW_HALMAC */ #endif /* __HAL_INTF_H__ */ diff --git a/include/hal_pg.h b/include/hal_pg.h index 06d8a08..c60f7fc 100644 --- a/include/hal_pg.h +++ b/include/hal_pg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_PG_H__ #define __HAL_PG_H__ @@ -27,6 +22,7 @@ #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F #define PPG_THERMAL_OFFSET_MASK 0x1F #define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) +#define KFREE_BB_GAIN_2G_TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg_v) >> 5) : (-((_ppg_v) >> 5)))) #define KFREE_BB_GAIN_5G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) @@ -428,12 +424,6 @@ * EEPROM/Efuse PG Offset for 8822B * ==================================================== */ -#define GET_PG_KFREE_ON_8822B(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) -#define GET_PG_KFREE_THERMAL_K_ON_8822B(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) - -#define PPG_BB_GAIN_2G_TXA_OFFSET_8822B 0xEE -#define PPG_THERMAL_OFFSET_8822B 0xEF - #define EEPROM_TX_PWR_INX_8822B 0x10 #define EEPROM_ChannelPlan_8822B 0xB8 @@ -478,15 +468,9 @@ * EEPROM/Efuse PG Offset for 8821C * ==================================================== */ -#define GET_PG_KFREE_ON_8821C(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) -#define GET_PG_KFREE_THERMAL_K_ON_8821C(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) - -#define PPG_BB_GAIN_2G_TXA_OFFSET_8821C 0xEE -#define PPG_THERMAL_OFFSET_8821C 0xEF - #define EEPROM_TX_PWR_INX_8821C 0x10 -#define EEPROM_ChannelPlan_8821C 0xB8 +#define EEPROM_CHANNEL_PLAN_8821C 0xB8 #define EEPROM_XTAL_8821C 0xB9 #define EEPROM_THERMAL_METER_8821C 0xBA #define EEPROM_IQK_LCK_8821C 0xBB @@ -504,8 +488,9 @@ #define EEPROM_FEATURE_OPTION_8821C 0xC2 #define EEPROM_RF_BT_SETTING_8821C 0xC3 #define EEPROM_VERSION_8821C 0xC4 -#define EEPROM_CustomID_8821C 0xC5 +#define EEPROM_CUSTOMER_ID_8821C 0xC5 #define EEPROM_TX_BBSWING_2G_8821C 0xC6 +#define EEPROM_TX_BBSWING_5G_8821C 0xC7 #define EEPROM_TX_PWR_CALIBRATE_RATE_8821C 0xC8 #define EEPROM_RF_ANTENNA_OPT_8821C 0xC9 #define EEPROM_RFE_OPTION_8821C 0xCA @@ -531,7 +516,11 @@ #define GET_PG_KFREE_THERMAL_K_ON_8723D(_pg_m) \ LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) +#define PPG_8723D_S1 0 +#define PPG_8723D_S0 1 + #define PPG_BB_GAIN_2G_TXA_OFFSET_8723D 0xEE +#define PPG_BB_GAIN_2G_TX_OFFSET_8723D 0x1EE #define PPG_THERMAL_OFFSET_8723D 0xEF #define EEPROM_TX_PWR_INX_8723D 0x10 @@ -555,18 +544,6 @@ #define EEPROM_RFE_OPTION_8723D 0xCA #define EEPROM_COUNTRY_CODE_8723D 0xCB -/* MAC Hidden */ -#define PPG_MAC_HIDDEN_START_8723D 0xF0 -#define PPG_MAC_HIDDEN_END_8723D 0xFF -#define EEPROM_HCI_AND_PACKAGE_TYPE_8723D 0xF8 -#define EEPROM_WL_FUNC_CAP_8723D 0xF9 -#define EEPROM_BW_AND_ANT_NUM_CAP_8723D 0xFB -#define GET_PMH_HCI_TYPE_8723D(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_HCI_AND_PACKAGE_TYPE_8723D - PPG_MAC_HIDDEN_START_8723D, 0, 4) -#define GET_PMH_PACKAGE_TYPE_8723D(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_HCI_AND_PACKAGE_TYPE_8723D - PPG_MAC_HIDDEN_START_8723D, 4, 4) -#define GET_PMH_WL_FUNC_CAP_8723D(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_WL_FUNC_CAP_8723D - PPG_MAC_HIDDEN_START_8723D, 0, 4) -#define GET_PMH_BW_CAP_8723D(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_BW_AND_ANT_NUM_CAP_8723D - PPG_MAC_HIDDEN_START_8723D, 0, 3) -#define GET_PMH_ANT_NUM_CAP_8723D(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_BW_AND_ANT_NUM_CAP_8723D - PPG_MAC_HIDDEN_START_8723D, 5, 3) - /* RTL8723DE */ #define EEPROM_MAC_ADDR_8723DE 0xD0 #define EEPROM_VID_8723DE 0xD6 @@ -682,15 +659,6 @@ #define EEPROM_Default_LNAType 0 /* New EFUSE default value */ -#define EEPROM_DEFAULT_24G_INDEX 0x2D -#define EEPROM_DEFAULT_24G_HT20_DIFF 0X02 -#define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 - -#define EEPROM_DEFAULT_5G_INDEX 0X2A -#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 -#define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 - -#define EEPROM_DEFAULT_DIFF 0XFE #define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F #define EEPROM_DEFAULT_BOARD_OPTION 0x00 #define EEPROM_DEFAULT_RFE_OPTION_8192E 0xFF diff --git a/include/hal_phy.h b/include/hal_phy.h index 9c16380..2c3c321 100644 --- a/include/hal_phy.h +++ b/include/hal_phy.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_PHY_H__ #define __HAL_PHY_H__ @@ -66,14 +61,6 @@ typedef enum _RF_TYPE { RF_TYPE_MAX } RF_TYPE_E, *PRF_TYPE_E; -#define TX_1S 0 -#define TX_2S 1 -#define TX_3S 2 -#define TX_4S 3 - -#define RF_PATH_MAX_92C_88E 2 -#define RF_PATH_MAX_90_8812 4 /* Max RF number 90 support */ - typedef enum _ANTENNA_PATH { ANTENNA_NONE = 0, ANTENNA_D = 1, diff --git a/include/hal_phy_reg.h b/include/hal_phy_reg.h index 9a92e40..6e6a99e 100644 --- a/include/hal_phy_reg.h +++ b/include/hal_phy_reg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_PHY_REG_H__ #define __HAL_PHY_REG_H__ diff --git a/include/hal_sdio.h b/include/hal_sdio.h index 5e7c5db..3c22eb9 100644 --- a/include/hal_sdio.h +++ b/include/hal_sdio.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_SDIO_H_ #define __HAL_SDIO_H_ @@ -27,5 +22,10 @@ u8 rtw_hal_sdio_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPag void rtw_hal_sdio_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum); void rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ); u32 rtw_hal_get_sdio_tx_max_length(PADAPTER padapter, u8 queue_idx); +bool sdio_power_on_check(PADAPTER padapter); + +#ifdef CONFIG_FW_C2H_REG +void sd_c2h_hisr_hdl(_adapter *adapter); +#endif -#endif /* __RTW_LED_H_ */ +#endif /* __HAL_SDIO_H_ */ diff --git a/include/ieee80211.h b/include/ieee80211.h index 2773d1f..05a4c51 100644 --- a/include/ieee80211.h +++ b/include/ieee80211.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,21 +11,16 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __IEEE80211_H #define __IEEE80211_H #ifndef CONFIG_RTL8711FW -#if defined PLATFORM_OS_XP -#include -#endif + #if defined PLATFORM_OS_XP + #include + #endif #else #endif @@ -224,7 +219,7 @@ enum NETWORK_TYPE { #define IsLegacyOnly(NetType) ((NetType) == ((NetType) & (WIRELESS_11BG | WIRELESS_11A))) #define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE) -#define IsSupported5G(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE) +#define is_supported_5g(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE) #define IsEnableHWCCK(NetType) IsSupported24G(NetType) #define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11_24N | SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE) @@ -235,9 +230,12 @@ enum NETWORK_TYPE { #define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE) #define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11A) ? _TRUE : _FALSE) -#define IsSupportedHT(NetType) ((NetType) & (WIRELESS_11_24N | WIRELESS_11_5N) ? _TRUE : _FALSE) +#define is_supported_ht(NetType) ((NetType) & (WIRELESS_11_24N | WIRELESS_11_5N) ? _TRUE : _FALSE) + +#define is_supported_vht(NetType) ((NetType) & (WIRELESS_11AC) ? _TRUE : _FALSE) + + -#define IsSupportedVHT(NetType) ((NetType) & (WIRELESS_11AC) ? _TRUE : _FALSE) typedef struct ieee_param { @@ -309,12 +307,12 @@ struct sta_data { #if WIRELESS_EXT < 17 -#define IW_QUAL_QUAL_INVALID 0x10 -#define IW_QUAL_LEVEL_INVALID 0x20 -#define IW_QUAL_NOISE_INVALID 0x40 -#define IW_QUAL_QUAL_UPDATED 0x1 -#define IW_QUAL_LEVEL_UPDATED 0x2 -#define IW_QUAL_NOISE_UPDATED 0x4 + #define IW_QUAL_QUAL_INVALID 0x10 + #define IW_QUAL_LEVEL_INVALID 0x20 + #define IW_QUAL_NOISE_INVALID 0x40 + #define IW_QUAL_QUAL_UPDATED 0x1 + #define IW_QUAL_LEVEL_UPDATED 0x2 + #define IW_QUAL_NOISE_UPDATED 0x4 #endif #define IEEE80211_DATA_LEN 2304 @@ -536,7 +534,7 @@ enum eap_type { #define BLOCK_ACK 3 #ifndef ETH_P_PAE -#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ + #define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ #endif /* ETH_P_PAE */ #define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */ @@ -544,7 +542,7 @@ enum eap_type { #define ETH_P_ECONET 0x0018 #ifndef ETH_P_80211_RAW -#define ETH_P_80211_RAW (ETH_P_ECONET + 1) + #define ETH_P_80211_RAW (ETH_P_ECONET + 1) #endif /* IEEE 802.11 defines */ @@ -862,6 +860,93 @@ enum MGN_RATE { #define IS_3T_RATE(_rate) (IS_HT3SS_RATE((_rate)) || IS_VHT3SS_RATE((_rate))) #define IS_4T_RATE(_rate) (IS_HT4SS_RATE((_rate)) || IS_VHT4SS_RATE((_rate))) +#define MGN_RATE_STR(_rate) \ + (_rate == MGN_1M) ? "CCK_1M" : \ + (_rate == MGN_2M) ? "CCK_2M" : \ + (_rate == MGN_5_5M) ? "CCK_5.5M" : \ + (_rate == MGN_11M) ? "CCK_11M" : \ + (_rate == MGN_6M) ? "OFDM_6M" : \ + (_rate == MGN_9M) ? "OFDM_9M" : \ + (_rate == MGN_12M) ? "OFDM_12M" : \ + (_rate == MGN_18M) ? "OFDM_18M" : \ + (_rate == MGN_24M) ? "OFDM_24M" : \ + (_rate == MGN_36M) ? "OFDM_36M" : \ + (_rate == MGN_48M) ? "OFDM_48M" : \ + (_rate == MGN_54M) ? "OFDM_54M" : \ + (_rate == MGN_MCS32) ? "MCS32" : \ + (_rate == MGN_MCS0) ? "MCS0" : \ + (_rate == MGN_MCS1) ? "MCS1" : \ + (_rate == MGN_MCS2) ? "MCS2" : \ + (_rate == MGN_MCS3) ? "MCS3" : \ + (_rate == MGN_MCS4) ? "MCS4" : \ + (_rate == MGN_MCS5) ? "MCS5" : \ + (_rate == MGN_MCS6) ? "MCS6" : \ + (_rate == MGN_MCS7) ? "MCS7" : \ + (_rate == MGN_MCS8) ? "MCS8" : \ + (_rate == MGN_MCS9) ? "MCS9" : \ + (_rate == MGN_MCS10) ? "MCS10" : \ + (_rate == MGN_MCS11) ? "MCS11" : \ + (_rate == MGN_MCS12) ? "MCS12" : \ + (_rate == MGN_MCS13) ? "MCS13" : \ + (_rate == MGN_MCS14) ? "MCS14" : \ + (_rate == MGN_MCS15) ? "MCS15" : \ + (_rate == MGN_MCS16) ? "MCS16" : \ + (_rate == MGN_MCS17) ? "MCS17" : \ + (_rate == MGN_MCS18) ? "MCS18" : \ + (_rate == MGN_MCS19) ? "MCS19" : \ + (_rate == MGN_MCS20) ? "MCS20" : \ + (_rate == MGN_MCS21) ? "MCS21" : \ + (_rate == MGN_MCS22) ? "MCS22" : \ + (_rate == MGN_MCS23) ? "MCS23" : \ + (_rate == MGN_MCS24) ? "MCS24" : \ + (_rate == MGN_MCS25) ? "MCS25" : \ + (_rate == MGN_MCS26) ? "MCS26" : \ + (_rate == MGN_MCS27) ? "MCS27" : \ + (_rate == MGN_MCS28) ? "MCS28" : \ + (_rate == MGN_MCS29) ? "MCS29" : \ + (_rate == MGN_MCS30) ? "MCS30" : \ + (_rate == MGN_MCS31) ? "MCS31" : \ + (_rate == MGN_VHT1SS_MCS0) ? "VHT1SMCS0" : \ + (_rate == MGN_VHT1SS_MCS1) ? "VHT1SMCS1" : \ + (_rate == MGN_VHT1SS_MCS2) ? "VHT1SMCS2" : \ + (_rate == MGN_VHT1SS_MCS3) ? "VHT1SMCS3" : \ + (_rate == MGN_VHT1SS_MCS4) ? "VHT1SMCS4" : \ + (_rate == MGN_VHT1SS_MCS5) ? "VHT1SMCS5" : \ + (_rate == MGN_VHT1SS_MCS6) ? "VHT1SMCS6" : \ + (_rate == MGN_VHT1SS_MCS7) ? "VHT1SMCS7" : \ + (_rate == MGN_VHT1SS_MCS8) ? "VHT1SMCS8" : \ + (_rate == MGN_VHT1SS_MCS9) ? "VHT1SMCS9" : \ + (_rate == MGN_VHT2SS_MCS0) ? "VHT2SMCS0" : \ + (_rate == MGN_VHT2SS_MCS1) ? "VHT2SMCS1" : \ + (_rate == MGN_VHT2SS_MCS2) ? "VHT2SMCS2" : \ + (_rate == MGN_VHT2SS_MCS3) ? "VHT2SMCS3" : \ + (_rate == MGN_VHT2SS_MCS4) ? "VHT2SMCS4" : \ + (_rate == MGN_VHT2SS_MCS5) ? "VHT2SMCS5" : \ + (_rate == MGN_VHT2SS_MCS6) ? "VHT2SMCS6" : \ + (_rate == MGN_VHT2SS_MCS7) ? "VHT2SMCS7" : \ + (_rate == MGN_VHT2SS_MCS8) ? "VHT2SMCS8" : \ + (_rate == MGN_VHT2SS_MCS9) ? "VHT2SMCS9" : \ + (_rate == MGN_VHT3SS_MCS0) ? "VHT3SMCS0" : \ + (_rate == MGN_VHT3SS_MCS1) ? "VHT3SMCS1" : \ + (_rate == MGN_VHT3SS_MCS2) ? "VHT3SMCS2" : \ + (_rate == MGN_VHT3SS_MCS3) ? "VHT3SMCS3" : \ + (_rate == MGN_VHT3SS_MCS4) ? "VHT3SMCS4" : \ + (_rate == MGN_VHT3SS_MCS5) ? "VHT3SMCS5" : \ + (_rate == MGN_VHT3SS_MCS6) ? "VHT3SMCS6" : \ + (_rate == MGN_VHT3SS_MCS7) ? "VHT3SMCS7" : \ + (_rate == MGN_VHT3SS_MCS8) ? "VHT3SMCS8" : \ + (_rate == MGN_VHT3SS_MCS9) ? "VHT3SMCS9" : \ + (_rate == MGN_VHT4SS_MCS0) ? "VHT4SMCS0" : \ + (_rate == MGN_VHT4SS_MCS1) ? "VHT4SMCS1" : \ + (_rate == MGN_VHT4SS_MCS2) ? "VHT4SMCS2" : \ + (_rate == MGN_VHT4SS_MCS3) ? "VHT4SMCS3" : \ + (_rate == MGN_VHT4SS_MCS4) ? "VHT4SMCS4" : \ + (_rate == MGN_VHT4SS_MCS5) ? "VHT4SMCS5" : \ + (_rate == MGN_VHT4SS_MCS6) ? "VHT4SMCS6" : \ + (_rate == MGN_VHT4SS_MCS7) ? "VHT4SMCS7" : \ + (_rate == MGN_VHT4SS_MCS8) ? "VHT4SMCS8" : \ + (_rate == MGN_VHT4SS_MCS9) ? "VHT4SMCS9" : "UNKNOWN" + typedef enum _RATE_SECTION { CCK = 0, OFDM = 1, @@ -1016,18 +1101,18 @@ struct ieee80211_softmac_stats { #define WEP_KEY_LEN 13 #ifdef CONFIG_IEEE80211W -#define BIP_MAX_KEYID 5 -#define BIP_AAD_SIZE 20 + #define BIP_MAX_KEYID 5 + #define BIP_AAD_SIZE 20 #endif /* CONFIG_IEEE80211W */ #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) struct ieee80211_security { - u16 active_key: 2, - enabled: 1, - auth_mode: 2, - auth_algo: 4, - unicast_uses_group: 1; + u16 active_key:2, + enabled:1, + auth_mode:2, + auth_algo:4, + unicast_uses_group:1; u8 key_sizes[WEP_KEYS]; u8 keys[WEP_KEYS][WEP_KEY_LEN]; u8 level; @@ -1040,11 +1125,11 @@ struct ieee80211_security { #pragma pack(1) struct ieee80211_security { - u16 active_key: 2, - enabled: 1, - auth_mode: 2, - auth_algo: 4, - unicast_uses_group: 1; + u16 active_key:2, + enabled:1, + auth_mode:2, + auth_algo:4, + unicast_uses_group:1; u8 key_sizes[WEP_KEYS]; u8 keys[WEP_KEYS][WEP_KEY_LEN]; u8 level; @@ -1260,7 +1345,6 @@ struct ieee80211_txb { #define MAX_RATES_LENGTH ((u8)12) #define MAX_RATES_EX_LENGTH ((u8)16) #define MAX_NETWORK_COUNT 128 -#define MAX_CHANNEL_NUMBER 161 #define IEEE80211_SOFTMAC_SCAN_TIME 400 /* (HZ / 2) */ #define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) @@ -1381,6 +1465,8 @@ enum ieee80211_state { #define DEFAULT_FTS 2346 #define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" #define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5] +#define MAC_SFMT "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx" +#define MAC_SARG(x) ((u8*)(x)),((u8*)(x)) + 1,((u8*)(x)) + 2,((u8*)(x)) + 3,((u8*)(x)) + 4,((u8*)(x)) + 5 #define IP_FMT "%d.%d.%d.%d" #define IP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3] #define PORT_FMT "%u" @@ -1392,18 +1478,21 @@ enum ieee80211_state { (((Addr[2]) & 0xff) == 0xff) && (((Addr[3]) & 0xff) == 0xff) && (((Addr[4]) & 0xff) == 0xff) && \ (((Addr[5]) & 0xff) == 0xff)) #else -extern __inline int is_multicast_mac_addr(const u8 *addr) { +extern __inline int is_multicast_mac_addr(const u8 *addr) +{ return (addr[0] != 0xff) && (0x01 & addr[0]); } -extern __inline int is_broadcast_mac_addr(const u8 *addr) { +extern __inline int is_broadcast_mac_addr(const u8 *addr) +{ return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \ - (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); + (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); } -extern __inline int is_zero_mac_addr(const u8 *addr) { +extern __inline int is_zero_mac_addr(const u8 *addr) +{ return ((addr[0] == 0x00) && (addr[1] == 0x00) && (addr[2] == 0x00) && \ - (addr[3] == 0x00) && (addr[4] == 0x00) && (addr[5] == 0x00)); + (addr[3] == 0x00) && (addr[4] == 0x00) && (addr[5] == 0x00)); } #endif /* PLATFORM_FREEBSD */ @@ -1429,15 +1518,15 @@ int ieee80211_is_empty_essid(const char *essid, int essid_len); int ieee80211_get_hdrlen(u16 fc); #if 0 -/* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */ -#define WLAN_ACTION_SPECTRUM_MGMT 0 -#define WLAN_ACTION_QOS 1 -#define WLAN_ACTION_DLS 2 -#define WLAN_ACTION_BLOCK_ACK 3 -#define WLAN_ACTION_RADIO_MEASUREMENT 5 -#define WLAN_ACTION_FT 6 -#define WLAN_ACTION_SA_QUERY 8 -#define WLAN_ACTION_WMM 17 + /* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */ + #define WLAN_ACTION_SPECTRUM_MGMT 0 + #define WLAN_ACTION_QOS 1 + #define WLAN_ACTION_DLS 2 + #define WLAN_ACTION_BLOCK_ACK 3 + #define WLAN_ACTION_RADIO_MEASUREMENT 5 + #define WLAN_ACTION_FT 6 + #define WLAN_ACTION_SA_QUERY 8 + #define WLAN_ACTION_WMM 17 #endif @@ -1452,6 +1541,7 @@ enum rtw_ieee80211_category { RTW_WLAN_CATEGORY_FT = 6, RTW_WLAN_CATEGORY_HT = 7, RTW_WLAN_CATEGORY_SA_QUERY = 8, + RTW_WLAN_CATEGORY_WNM = 10, RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, /* add for CONFIG_IEEE80211W, none 11w also can use */ RTW_WLAN_CATEGORY_TDLS = 12, RTW_WLAN_CATEGORY_SELF_PROTECTED = 15, /* add for CONFIG_IEEE80211W, none 11w also can use */ @@ -1550,11 +1640,22 @@ enum rtw_ieee80211_vht_actioncode { RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION = 2, }; +/*IEEE 802.11r action code*/ +#ifdef CONFIG_RTW_80211R +enum rtw_ieee80211_ft_actioncode { + RTW_WLAN_ACTION_FT_RESV, + RTW_WLAN_ACTION_FT_REQUEST, + RTW_WLAN_ACTION_FT_RESPONSE, + RTW_WLAN_ACTION_FT_CONFIRM, + RTW_WLAN_ACTION_FT_ACK, + RTW_WLAN_ACTION_FT_MAX, +}; +#endif #define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs) * 00:50:F2 */ #ifndef PLATFORM_FREEBSD /* Baron BSD has defined */ -#define WME_OUI_TYPE 2 + #define WME_OUI_TYPE 2 #endif /* PLATFORM_FREEBSD */ #define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0 #define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1 @@ -1607,7 +1708,7 @@ enum rtw_ieee80211_channel_flags { /* Represent channel details, subset of ieee80211_channel */ struct rtw_ieee80211_channel { - /* enum nl80211_band band; */ + /* enum ieee80211_band band; */ /* u16 center_freq; */ u16 hw_value; u32 flags; @@ -1705,8 +1806,8 @@ struct rtw_ieee802_11_elems { typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes; ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, - struct rtw_ieee802_11_elems *elems, - int show_errors); + struct rtw_ieee802_11_elems *elems, + int show_errors); u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen); u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen); @@ -1766,16 +1867,16 @@ void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset); void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset); bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a - , u8 ch_b, u8 bw_b, u8 offset_b); + , u8 ch_b, u8 bw_b, u8 offset_b); void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset - , u8 *g_ch, u8 *g_bw, u8 *g_offset); + , u8 *g_ch, u8 *g_bw, u8 *g_offset); u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len); int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie); void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len); u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen); -u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id , u8 *buf_attr, u32 *len_attr); -u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id , u8 *buf_content, uint *len_content); +u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr); +u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content); u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr); uint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg); uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id); @@ -1813,6 +1914,7 @@ void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr); u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate); u8 rtw_ht_mcsset_to_nss(u8 *supp_mcs_set); +u32 rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss); int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action); const char *action_public_str(u8 action); @@ -1823,4 +1925,5 @@ void macstr2num(u8 *dst, u8 *src); u8 convert_ip_addr(u8 hch, u8 mch, u8 lch); int wifirate2_ratetbl_inx(unsigned char rate); + #endif /* IEEE80211_H */ diff --git a/include/ieee80211_ext.h b/include/ieee80211_ext.h index 2121a6d..94a8e58 100644 --- a/include/ieee80211_ext.h +++ b/include/ieee80211_ext.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __IEEE80211_EXT_H #define __IEEE80211_EXT_H @@ -408,21 +403,21 @@ struct ieee80211_mgmt { u8 status_code; u8 variable[0]; } wme_action; - /* - struct{ - u8 action_code; - u8 element_id; - u8 length; - struct ieee80211_channel_sw_ie sw_elem; - } chan_switch; - struct{ - u8 action_code; - u8 dialog_token; - u8 element_id; - u8 length; - struct ieee80211_msrment_ie msr_elem; - } measurement; - */ + #if 0 + struct{ + u8 action_code; + u8 element_id; + u8 length; + struct ieee80211_channel_sw_ie sw_elem; + } chan_switch; + struct{ + u8 action_code; + u8 dialog_token; + u8 element_id; + u8 length; + struct ieee80211_msrment_ie msr_elem; + } measurement; + #endif struct { u8 action_code; u8 dialog_token; diff --git a/include/if_ether.h b/include/if_ether.h index 9d08f56..a3007c4 100644 --- a/include/if_ether.h +++ b/include/if_ether.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_IF_ETHER_H #define _LINUX_IF_ETHER_H diff --git a/include/ip.h b/include/ip.h index c78034d..4feb98f 100644 --- a/include/ip.h +++ b/include/ip.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_IP_H #define _LINUX_IP_H diff --git a/include/linux/wireless.h b/include/linux/wireless.h index b4bb716..c7f4a6c 100644 --- a/include/linux/wireless.h +++ b/include/linux/wireless.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_WIRELESS_H #define _LINUX_WIRELESS_H diff --git a/include/mlme_osdep.h b/include/mlme_osdep.h index 8dcc589..291ecd2 100644 --- a/include/mlme_osdep.h +++ b/include/mlme_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __MLME_OSDEP_H_ #define __MLME_OSDEP_H_ @@ -25,7 +20,6 @@ extern int time_after(u32 now, u32 old); #endif -extern void rtw_init_mlme_timer(_adapter *padapter); extern void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated); extern void rtw_os_indicate_connect(_adapter *adapter); void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted); diff --git a/include/mp_custom_oid.h b/include/mp_custom_oid.h index 7ca76ad..8ed1441 100644 --- a/include/mp_custom_oid.h +++ b/include/mp_custom_oid.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __CUSTOM_OID_H #define __CUSTOM_OID_H diff --git a/include/nic_spec.h b/include/nic_spec.h index c0a952f..913ef9b 100644 --- a/include/nic_spec.h +++ b/include/nic_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __NIC_SPEC_H__ diff --git a/include/osdep_intf.h b/include/osdep_intf.h index 5a02432..7be0880 100644 --- a/include/osdep_intf.h +++ b/include/osdep_intf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __OSDEP_INTF_H_ #define __OSDEP_INTF_H_ @@ -101,64 +96,69 @@ void rtw_dev_unload(PADAPTER padapter); u32 rtw_start_drv_threads(_adapter *padapter); void rtw_stop_drv_threads(_adapter *padapter); #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - void rtw_cancel_dynamic_chk_timer(_adapter *padapter); +void rtw_cancel_dynamic_chk_timer(_adapter *padapter); #endif void rtw_cancel_all_timer(_adapter *padapter); uint loadparam(_adapter *adapter); #ifdef PLATFORM_LINUX - int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); +int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); - int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname); - struct net_device *rtw_init_netdev(_adapter *padapter); +int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname); +struct net_device *rtw_init_netdev(_adapter *padapter); - void rtw_os_ndev_free(_adapter *adapter); - int rtw_os_ndev_init(_adapter *adapter, char *name); - void rtw_os_ndev_deinit(_adapter *adapter); - void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj); - int rtw_os_ndevs_init(struct dvobj_priv *dvobj); - void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj); +void rtw_os_ndev_free(_adapter *adapter); +int rtw_os_ndev_init(_adapter *adapter, const char *name); +void rtw_os_ndev_deinit(_adapter *adapter); +void rtw_os_ndev_unregister(_adapter *adapter); +void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj); +int rtw_os_ndevs_init(struct dvobj_priv *dvobj); +void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj); - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) - u16 rtw_recv_select_queue(struct sk_buff *skb); - #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) +u16 rtw_recv_select_queue(struct sk_buff *skb); +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) */ - int rtw_ndev_notifier_register(void); - void rtw_ndev_notifier_unregister(void); +int rtw_ndev_notifier_register(void); +void rtw_ndev_notifier_unregister(void); +void rtw_inetaddr_notifier_register(void); +void rtw_inetaddr_notifier_unregister(void); - #include "../os_dep/linux/rtw_proc.h" +#include "../os_dep/linux/rtw_proc.h" - #ifdef CONFIG_IOCTL_CFG80211 - #include "../os_dep/linux/ioctl_cfg80211.h" - #endif /* CONFIG_IOCTL_CFG80211 */ +#ifdef CONFIG_IOCTL_CFG80211 + #include "../os_dep/linux/ioctl_cfg80211.h" +#endif /* CONFIG_IOCTL_CFG80211 */ + +u8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj); +void rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl); #endif /* PLATFORM_LINUX */ #ifdef PLATFORM_FREEBSD - extern int rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); +extern int rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); #endif void rtw_ips_dev_unload(_adapter *padapter); #ifdef CONFIG_IPS - int rtw_ips_pwr_up(_adapter *padapter); - void rtw_ips_pwr_down(_adapter *padapter); +int rtw_ips_pwr_up(_adapter *padapter); +void rtw_ips_pwr_down(_adapter *padapter); #endif #ifdef CONFIG_CONCURRENT_MODE - struct _io_ops; - struct dvobj_priv; - _adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops)); - void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj); - void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj); +struct _io_ops; +struct dvobj_priv; +_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops)); +void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj); +void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj); #endif void rtw_ndev_destructor(_nic_hdl ndev); - #ifdef CONFIG_ARP_KEEP_ALIVE - int rtw_gw_addr_query(_adapter *padapter); +int rtw_gw_addr_query(_adapter *padapter); #endif int rtw_suspend_common(_adapter *padapter); diff --git a/include/osdep_service.h b/include/osdep_service.h index 59b01e3..7756685 100644 --- a/include/osdep_service.h +++ b/include/osdep_service.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,19 +11,25 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __OSDEP_SERVICE_H_ #define __OSDEP_SERVICE_H_ +//EDX_S +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) +#include +#endif +//EDX_E + +#define _FAIL 0 +#define _SUCCESS 1 +#define RTW_RX_HANDLED 2 +#define RTW_RFRAME_UNAVAIL 3 +#define RTW_RFRAME_PKT_UNAVAIL 4 +#define RTW_RBUF_UNAVAIL 5 +#define RTW_RBUF_PKT_UNAVAIL 6 +#define RTW_SDIO_READ_PORT_FAIL 7 -#define _FAIL 0 -#define _SUCCESS 1 -#define RTW_RX_HANDLED 2 /* #define RTW_STATUS_TIMEDOUT -110 */ #undef _TRUE @@ -49,9 +55,6 @@ #include #endif -#define RTW_TIMER_HDL_NAME(name) rtw_##name##_timer_hdl -#define RTW_DECLARE_TIMER_HDL(name) void RTW_TIMER_HDL_NAME(name)(RTW_TIMER_HDL_ARGS) - /* #include */ #ifndef BIT @@ -132,125 +135,149 @@ typedef enum mstat_status { } MSTAT_STATUS; #ifdef DBG_MEM_ALLOC - void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz); - void rtw_mstat_dump(void *sel); - u8 *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); - u8 *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); - void dbg_rtw_vmfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); - u8 *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line); - u8 *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); - void dbg_rtw_mfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); - - struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line); - void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); - struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); - struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); - int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line); - void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line); - #ifdef CONFIG_USB_HCI - void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, const int line); - void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, const int line); - #endif /* CONFIG_USB_HCI */ - - #ifdef CONFIG_USE_VMALLOC - #define rtw_vmalloc(sz) dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) - #define rtw_zvmalloc(sz) dbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) - #define rtw_vmfree(pbuf, sz) dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) - #define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_vmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) - #define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zvmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) - #define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_vmfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) - #else /* CONFIG_USE_VMALLOC */ - #define rtw_vmalloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) - #define rtw_zvmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) - #define rtw_vmfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) - #define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) - #define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) - #define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) - #endif /* CONFIG_USE_VMALLOC */ - #define rtw_malloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) - #define rtw_zmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) - #define rtw_mfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) - #define rtw_malloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) - #define rtw_zmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) - #define rtw_mfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) - - #define rtw_skb_alloc(size) dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) - #define rtw_skb_free(skb) dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) - #define rtw_skb_alloc_f(size, mstat_f) dbg_rtw_skb_alloc((size), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) - #define rtw_skb_free_f(skb, mstat_f) dbg_rtw_skb_free((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) - #define rtw_skb_copy(skb) dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) - #define rtw_skb_clone(skb) dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) - #define rtw_skb_copy_f(skb, mstat_f) dbg_rtw_skb_copy((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) - #define rtw_skb_clone_f(skb, mstat_f) dbg_rtw_skb_clone((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) - #define rtw_netif_rx(ndev, skb) dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) - #define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) - #ifdef CONFIG_USB_HCI - #define rtw_usb_buffer_alloc(dev, size, dma) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__) - #define rtw_usb_buffer_free(dev, size, addr, dma) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__) - #define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__) - #define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__) - #endif /* CONFIG_USB_HCI */ +void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz); +void rtw_mstat_dump(void *sel); +u8 *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +u8 *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_vmfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); +u8 *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +u8 *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_mfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); + +struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); +struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); +struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); +int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line); +#ifdef CONFIG_RTW_NAPI +int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line); +#ifdef CONFIG_RTW_GRO +gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line); +#endif +#endif /* CONFIG_RTW_NAPI */ +void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line); +#ifdef CONFIG_USB_HCI +void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, const int line); +#endif /* CONFIG_USB_HCI */ + +#ifdef CONFIG_USE_VMALLOC +#define rtw_vmalloc(sz) dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_zvmalloc(sz) dbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_vmfree(pbuf, sz) dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_vmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zvmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_vmfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#else /* CONFIG_USE_VMALLOC */ +#define rtw_vmalloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_zvmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_vmfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#endif /* CONFIG_USE_VMALLOC */ +#define rtw_malloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_zmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_mfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_malloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_zmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_mfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) + +#define rtw_skb_alloc(size) dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_free(skb) dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_alloc_f(size, mstat_f) dbg_rtw_skb_alloc((size), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_free_f(skb, mstat_f) dbg_rtw_skb_free((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_copy(skb) dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_clone(skb) dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_copy_f(skb, mstat_f) dbg_rtw_skb_copy((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_clone_f(skb, mstat_f) dbg_rtw_skb_clone((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_netif_rx(ndev, skb) dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#ifdef CONFIG_RTW_NAPI +#define rtw_netif_receive_skb(ndev, skb) dbg_rtw_netif_receive_skb(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#ifdef CONFIG_RTW_GRO +#define rtw_napi_gro_receive(napi, skb) dbg_rtw_napi_gro_receive(napi, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#endif +#endif /* CONFIG_RTW_NAPI */ +#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#ifdef CONFIG_USB_HCI +#define rtw_usb_buffer_alloc(dev, size, dma) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__) +#define rtw_usb_buffer_free(dev, size, addr, dma) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__) +#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__) +#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__) +#endif /* CONFIG_USB_HCI */ #else /* DBG_MEM_ALLOC */ - #define rtw_mstat_update(flag, status, sz) do {} while (0) - #define rtw_mstat_dump(sel) do {} while (0) - u8 *_rtw_vmalloc(u32 sz); - u8 *_rtw_zvmalloc(u32 sz); - void _rtw_vmfree(u8 *pbuf, u32 sz); - u8 *_rtw_zmalloc(u32 sz); - u8 *_rtw_malloc(u32 sz); - void _rtw_mfree(u8 *pbuf, u32 sz); - - struct sk_buff *_rtw_skb_alloc(u32 sz); - void _rtw_skb_free(struct sk_buff *skb); - struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb); - struct sk_buff *_rtw_skb_clone(struct sk_buff *skb); - int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb); - void _rtw_skb_queue_purge(struct sk_buff_head *list); - - #ifdef CONFIG_USB_HCI - void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma); - void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma); - #endif /* CONFIG_USB_HCI */ - - #ifdef CONFIG_USE_VMALLOC - #define rtw_vmalloc(sz) _rtw_vmalloc((sz)) - #define rtw_zvmalloc(sz) _rtw_zvmalloc((sz)) - #define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz)) - #define rtw_vmalloc_f(sz, mstat_f) _rtw_vmalloc((sz)) - #define rtw_zvmalloc_f(sz, mstat_f) _rtw_zvmalloc((sz)) - #define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_vmfree((pbuf), (sz)) - #else /* CONFIG_USE_VMALLOC */ - #define rtw_vmalloc(sz) _rtw_malloc((sz)) - #define rtw_zvmalloc(sz) _rtw_zmalloc((sz)) - #define rtw_vmfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) - #define rtw_vmalloc_f(sz, mstat_f) _rtw_malloc((sz)) - #define rtw_zvmalloc_f(sz, mstat_f) _rtw_zmalloc((sz)) - #define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz)) - #endif /* CONFIG_USE_VMALLOC */ - #define rtw_malloc(sz) _rtw_malloc((sz)) - #define rtw_zmalloc(sz) _rtw_zmalloc((sz)) - #define rtw_mfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) - #define rtw_malloc_f(sz, mstat_f) _rtw_malloc((sz)) - #define rtw_zmalloc_f(sz, mstat_f) _rtw_zmalloc((sz)) - #define rtw_mfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz)) - - #define rtw_skb_alloc(size) _rtw_skb_alloc((size)) - #define rtw_skb_free(skb) _rtw_skb_free((skb)) - #define rtw_skb_alloc_f(size, mstat_f) _rtw_skb_alloc((size)) - #define rtw_skb_free_f(skb, mstat_f) _rtw_skb_free((skb)) - #define rtw_skb_copy(skb) _rtw_skb_copy((skb)) - #define rtw_skb_clone(skb) _rtw_skb_clone((skb)) - #define rtw_skb_copy_f(skb, mstat_f) _rtw_skb_copy((skb)) - #define rtw_skb_clone_f(skb, mstat_f) _rtw_skb_clone((skb)) - #define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb) - #define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head) - #ifdef CONFIG_USB_HCI - #define rtw_usb_buffer_alloc(dev, size, dma) _rtw_usb_buffer_alloc((dev), (size), (dma)) - #define rtw_usb_buffer_free(dev, size, addr, dma) _rtw_usb_buffer_free((dev), (size), (addr), (dma)) - #define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) _rtw_usb_buffer_alloc((dev), (size), (dma)) - #define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) _rtw_usb_buffer_free((dev), (size), (addr), (dma)) - #endif /* CONFIG_USB_HCI */ +#define rtw_mstat_update(flag, status, sz) do {} while (0) +#define rtw_mstat_dump(sel) do {} while (0) +u8 *_rtw_vmalloc(u32 sz); +u8 *_rtw_zvmalloc(u32 sz); +void _rtw_vmfree(u8 *pbuf, u32 sz); +u8 *_rtw_zmalloc(u32 sz); +u8 *_rtw_malloc(u32 sz); +void _rtw_mfree(u8 *pbuf, u32 sz); + +struct sk_buff *_rtw_skb_alloc(u32 sz); +void _rtw_skb_free(struct sk_buff *skb); +struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb); +struct sk_buff *_rtw_skb_clone(struct sk_buff *skb); +int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb); +#ifdef CONFIG_RTW_NAPI +int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb); +#ifdef CONFIG_RTW_GRO +gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb); +#endif +#endif /* CONFIG_RTW_NAPI */ +void _rtw_skb_queue_purge(struct sk_buff_head *list); + +#ifdef CONFIG_USB_HCI +void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma); +void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma); +#endif /* CONFIG_USB_HCI */ + +#ifdef CONFIG_USE_VMALLOC +#define rtw_vmalloc(sz) _rtw_vmalloc((sz)) +#define rtw_zvmalloc(sz) _rtw_zvmalloc((sz)) +#define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz)) +#define rtw_vmalloc_f(sz, mstat_f) _rtw_vmalloc((sz)) +#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zvmalloc((sz)) +#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_vmfree((pbuf), (sz)) +#else /* CONFIG_USE_VMALLOC */ +#define rtw_vmalloc(sz) _rtw_malloc((sz)) +#define rtw_zvmalloc(sz) _rtw_zmalloc((sz)) +#define rtw_vmfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) +#define rtw_vmalloc_f(sz, mstat_f) _rtw_malloc((sz)) +#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zmalloc((sz)) +#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz)) +#endif /* CONFIG_USE_VMALLOC */ +#define rtw_malloc(sz) _rtw_malloc((sz)) +#define rtw_zmalloc(sz) _rtw_zmalloc((sz)) +#define rtw_mfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) +#define rtw_malloc_f(sz, mstat_f) _rtw_malloc((sz)) +#define rtw_zmalloc_f(sz, mstat_f) _rtw_zmalloc((sz)) +#define rtw_mfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz)) + +#define rtw_skb_alloc(size) _rtw_skb_alloc((size)) +#define rtw_skb_free(skb) _rtw_skb_free((skb)) +#define rtw_skb_alloc_f(size, mstat_f) _rtw_skb_alloc((size)) +#define rtw_skb_free_f(skb, mstat_f) _rtw_skb_free((skb)) +#define rtw_skb_copy(skb) _rtw_skb_copy((skb)) +#define rtw_skb_clone(skb) _rtw_skb_clone((skb)) +#define rtw_skb_copy_f(skb, mstat_f) _rtw_skb_copy((skb)) +#define rtw_skb_clone_f(skb, mstat_f) _rtw_skb_clone((skb)) +#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb) +#ifdef CONFIG_RTW_NAPI +#define rtw_netif_receive_skb(ndev, skb) _rtw_netif_receive_skb(ndev, skb) +#ifdef CONFIG_RTW_GRO +#define rtw_napi_gro_receive(napi, skb) _rtw_napi_gro_receive(napi, skb) +#endif +#endif /* CONFIG_RTW_NAPI */ +#define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head) +#ifdef CONFIG_USB_HCI +#define rtw_usb_buffer_alloc(dev, size, dma) _rtw_usb_buffer_alloc((dev), (size), (dma)) +#define rtw_usb_buffer_free(dev, size, addr, dma) _rtw_usb_buffer_free((dev), (size), (addr), (dma)) +#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) _rtw_usb_buffer_alloc((dev), (size), (dma)) +#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) _rtw_usb_buffer_free((dev), (size), (addr), (dma)) +#endif /* CONFIG_USB_HCI */ #endif /* DBG_MEM_ALLOC */ extern void *rtw_malloc2d(int h, int w, size_t size); @@ -266,7 +293,7 @@ extern u32 rtw_is_list_empty(_list *phead); extern void rtw_list_insert_head(_list *plist, _list *phead); extern void rtw_list_insert_tail(_list *plist, _list *phead); #ifndef PLATFORM_FREEBSD - extern void rtw_list_delete(_list *plist); +extern void rtw_list_delete(_list *plist); #endif /* PLATFORM_FREEBSD */ extern void _rtw_init_sema(_sema *sema, int init_val); @@ -276,7 +303,7 @@ extern u32 _rtw_down_sema(_sema *sema); extern void _rtw_mutex_init(_mutex *pmutex); extern void _rtw_mutex_free(_mutex *pmutex); #ifndef PLATFORM_FREEBSD - extern void _rtw_spinlock_init(_lock *plock); +extern void _rtw_spinlock_init(_lock *plock); #endif /* PLATFORM_FREEBSD */ extern void _rtw_spinlock_free(_lock *plock); extern void _rtw_spinlock(_lock *plock); @@ -303,51 +330,66 @@ extern void rtw_usleep_os(int us); extern u32 rtw_atoi(u8 *s); #ifdef DBG_DELAY_OS - #define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__) - #define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__) - extern void _rtw_mdelay_os(int ms, const char *func, const int line); - extern void _rtw_udelay_os(int us, const char *func, const int line); +#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__) +#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__) +extern void _rtw_mdelay_os(int ms, const char *func, const int line); +extern void _rtw_udelay_os(int us, const char *func, const int line); #else - extern void rtw_mdelay_os(int ms); - extern void rtw_udelay_os(int us); +extern void rtw_mdelay_os(int ms); +extern void rtw_udelay_os(int us); #endif extern void rtw_yield_os(void); -extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc); +extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx); __inline static unsigned char _cancel_timer_ex(_timer *ptimer) { -#ifdef PLATFORM_LINUX - return del_timer_sync(ptimer); -#endif -#ifdef PLATFORM_FREEBSD - _cancel_timer(ptimer, 0); - return 0; -#endif -#ifdef PLATFORM_WINDOWS u8 bcancelled; _cancel_timer(ptimer, &bcancelled); return bcancelled; -#endif } static __inline void thread_enter(char *name) { #ifdef PLATFORM_LINUX -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) - daemonize("%s", name); -#endif allow_signal(SIGTERM); #endif #ifdef PLATFORM_FREEBSD printf("%s", "RTKTHREAD_enter"); #endif } +void thread_exit(_completion *comp); +void _rtw_init_completion(_completion *comp); +void _rtw_wait_for_comp_timeout(_completion *comp); +void _rtw_wait_for_comp(_completion *comp); + +static inline bool rtw_thread_stop(_thread_hdl_ th) +{ +#ifdef PLATFORM_LINUX + return kthread_stop(th); +#endif +} +static inline void rtw_thread_wait_stop(void) +{ +#ifdef PLATFORM_LINUX + #if 0 + while (!kthread_should_stop()) + rtw_msleep_os(10); + #else + set_current_state(TASK_INTERRUPTIBLE); + while (!kthread_should_stop()) { + schedule(); + set_current_state(TASK_INTERRUPTIBLE); + } + __set_current_state(TASK_RUNNING); + #endif +#endif +} __inline static void flush_signals_thread(void) { @@ -383,9 +425,9 @@ __inline static void rtw_dump_stack(void) } #ifdef PLATFORM_LINUX - #define rtw_warn_on(condition) WARN_ON(condition) +#define rtw_warn_on(condition) WARN_ON(condition) #else - #define rtw_warn_on(condition) do {} while (0) +#define rtw_warn_on(condition) do {} while (0) #endif __inline static int rtw_bug_check(void *parg1, void *parg2, void *parg3, void *parg4) @@ -405,6 +447,11 @@ __inline static int rtw_bug_check(void *parg1, void *parg2, void *parg3, void *p return ret; } +#ifdef PLATFORM_LINUX +#define RTW_DIV_ROUND_UP(n, d) DIV_ROUND_UP(n, d) +#else /* !PLATFORM_LINUX */ +#define RTW_DIV_ROUND_UP(n, d) (((n) + (d - 1)) / d) +#endif /* !PLATFORM_LINUX */ #define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r)) #define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0 : 1)) << 2) @@ -475,15 +522,26 @@ __inline static u32 bitshift(u32 bitmask) return i; } +static inline int largest_bit(u32 bitmask) +{ + int i; + + for (i = 31; i >= 0; i--) + if (bitmask & BIT(i)) + break; + + return i; +} + #define rtw_min(a, b) ((a > b) ? b : a) #define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b))) #define rtw_is_range_overlap(hi_a, lo_a, hi_b, lo_b) (((hi_a) > (lo_b)) && ((lo_a) < (hi_b))) #ifndef MAC_FMT - #define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" +#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" #endif #ifndef MAC_ARG - #define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5] +#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5] #endif @@ -499,8 +557,8 @@ extern void rtw_lock_resume_scan_timeout(u32 timeout_ms); extern void rtw_resume_lock_suspend(void); extern void rtw_resume_unlock_suspend(void); #ifdef CONFIG_AP_WOWLAN - extern void rtw_softap_lock_suspend(void); - extern void rtw_softap_unlock_suspend(void); +extern void rtw_softap_lock_suspend(void); +extern void rtw_softap_unlock_suspend(void); #endif extern void ATOMIC_SET(ATOMIC_T *v, int i); @@ -515,13 +573,14 @@ extern int ATOMIC_INC_RETURN(ATOMIC_T *v); extern int ATOMIC_DEC_RETURN(ATOMIC_T *v); /* File operation APIs, just for linux now */ -extern int rtw_is_file_readable(char *path); -extern int rtw_retrieve_from_file(char *path, u8 *buf, u32 sz); -extern int rtw_store_to_file(char *path, u8 *buf, u32 sz); +extern int rtw_is_file_readable(const char *path); +extern int rtw_is_file_readable_with_size(const char *path, u32 *sz); +extern int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz); +extern int rtw_store_to_file(const char *path, u8 *buf, u32 sz); #ifndef PLATFORM_FREEBSD - extern void rtw_free_netdev(struct net_device *netdev); +extern void rtw_free_netdev(struct net_device *netdev); #endif /* PLATFORM_FREEBSD */ @@ -612,8 +671,37 @@ void *rtw_cbuf_pop(struct rtw_cbuf *cbuf); struct rtw_cbuf *rtw_cbuf_alloc(u32 size); void rtw_cbuf_free(struct rtw_cbuf *cbuf); +struct map_seg_t { + u16 sa; + u16 len; + u8 *c; +}; + +struct map_t { + u16 len; + u16 seg_num; + u8 init_value; + struct map_seg_t *segs; +}; + +#define MAPSEG_ARRAY_ENT(_sa, _len, _c, arg...) \ + { .sa = _sa, .len = _len, .c = (u8[_len]){ _c, ##arg}, } + +#define MAPSEG_PTR_ENT(_sa, _len, _p) \ + { .sa = _sa, .len = _len, .c = _p, } + +#define MAP_ENT(_len, _seg_num, _init_v, _seg, arg...) \ + { .len = _len, .seg_num = _seg_num, .init_value = _init_v, .segs = (struct map_seg_t[_seg_num]){ _seg, ##arg}, } + +int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf); +u8 map_read8(const struct map_t *map, u16 offset); + /* String handler */ +BOOLEAN is_null(char c); +BOOLEAN is_all_null(char *c, int len); +BOOLEAN is_eol(char c); +BOOLEAN is_space(char c); BOOLEAN IsHexDigit(char chTmp); BOOLEAN is_alpha(char chTmp); char alpha_to_upper(char c); @@ -622,9 +710,9 @@ char alpha_to_upper(char c); * Write formatted output to sized buffer */ #ifdef PLATFORM_LINUX - #define rtw_sprintf(buf, size, format, arg...) snprintf(buf, size, format, ##arg) +#define rtw_sprintf(buf, size, format, arg...) snprintf(buf, size, format, ##arg) #else /* !PLATFORM_LINUX */ - #error "NOT DEFINE \"rtw_sprintf\"!!" +#error "NOT DEFINE \"rtw_sprintf\"!!" #endif /* !PLATFORM_LINUX */ #endif diff --git a/include/osdep_service_bsd.h b/include/osdep_service_bsd.h index 040225c..f4ce7f8 100644 --- a/include/osdep_service_bsd.h +++ b/include/osdep_service_bsd.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,739 +11,747 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __OSDEP_BSD_SERVICE_H_ -#define __OSDEP_BSD_SERVICE_H_ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include "usbdevs.h" - -#define USB_DEBUG_VAR rum_debug -#include - -#if 1 //Baron porting from linux, it's all temp solution, needs to check again -#include -#include /* XXX for PCPU_GET */ -// typedef struct semaphore _sema; - typedef struct sema _sema; -// typedef spinlock_t _lock; - typedef struct mtx _lock; - typedef struct mtx _mutex; - typedef struct timer_list _timer; - struct list_head { - struct list_head *next, *prev; - }; - struct __queue { - struct list_head queue; - _lock lock; - }; - - //typedef struct sk_buff _pkt; - typedef struct mbuf _pkt; - typedef struct mbuf _buffer; - - typedef struct __queue _queue; - typedef struct list_head _list; - typedef int _OS_STATUS; - //typedef u32 _irqL; - typedef unsigned long _irqL; - typedef struct ifnet * _nic_hdl; - - typedef pid_t _thread_hdl_; -// typedef struct thread _thread_hdl_; - typedef void thread_return; - typedef void* thread_context; - - //#define thread_exit() complete_and_exit(NULL, 0) - - #define thread_exit() do{printf("%s", "RTKTHREAD_exit");}while(0) - - typedef void timer_hdl_return; - typedef void* timer_hdl_context; - typedef struct work_struct _workitem; - -#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) -/* emulate a modern version */ -#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35) - -#define WIRELESS_EXT -1 -#define HZ hz -#define spin_lock_irqsave mtx_lock_irqsave -#define spin_lock_bh mtx_lock_irqsave -#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));} -//#define IFT_RTW 0xf9 //ifnet allocate type for RTW -#define free_netdev if_free -#define LIST_CONTAINOR(ptr, type, member) \ - ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) -#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n)) -/* - * Linux timers are emulated using FreeBSD callout functions - * (and taskqueue functionality). - * - * Currently no timer stats functionality. - * - * See (linux_compat) processes.c - * - */ -struct timer_list { - - /* FreeBSD callout related fields */ - struct callout callout; - - //timeout function - void (*function)(void*); - //argument - void *arg; - -}; -struct workqueue_struct; -struct work_struct; -typedef void (*work_func_t)(struct work_struct *work); -/* Values for the state of an item of work (work_struct) */ -typedef enum work_state { - WORK_STATE_UNSET = 0, - WORK_STATE_CALLOUT_PENDING = 1, - WORK_STATE_TASK_PENDING = 2, - WORK_STATE_WORK_CANCELLED = 3 -} work_state_t; - -struct work_struct { - struct task task; /* FreeBSD task */ - work_state_t state; /* the pending or otherwise state of work. */ - work_func_t func; -}; -#define spin_unlock_irqrestore mtx_unlock_irqrestore -#define spin_unlock_bh mtx_unlock_irqrestore -#define mtx_unlock_irqrestore(lock,x) mtx_unlock(lock); -extern void _rtw_spinlock_init(_lock *plock); - -//modify private structure to match freebsd -#define BITS_PER_LONG 32 -union ktime { - s64 tv64; -#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR) - struct { -#ifdef __BIG_ENDIAN - s32 sec, nsec; -#else - s32 nsec, sec; -#endif - } tv; -#endif -}; -#define kmemcheck_bitfield_begin(name) -#define kmemcheck_bitfield_end(name) -#define CHECKSUM_NONE 0 -typedef unsigned char *sk_buff_data_t; -typedef union ktime ktime_t; /* Kill this */ - -void rtw_mtx_lock(_lock *plock); - -void rtw_mtx_unlock(_lock *plock); - -/** - * struct sk_buff - socket buffer - * @next: Next buffer in list - * @prev: Previous buffer in list - * @sk: Socket we are owned by - * @tstamp: Time we arrived - * @dev: Device we arrived on/are leaving by - * @transport_header: Transport layer header - * @network_header: Network layer header - * @mac_header: Link layer header - * @_skb_refdst: destination entry (with norefcount bit) - * @sp: the security path, used for xfrm - * @cb: Control buffer. Free for use by every layer. Put private vars here - * @len: Length of actual data - * @data_len: Data length - * @mac_len: Length of link layer header - * @hdr_len: writable header length of cloned skb - * @csum: Checksum (must include start/offset pair) - * @csum_start: Offset from skb->head where checksumming should start - * @csum_offset: Offset from csum_start where checksum should be stored - * @local_df: allow local fragmentation - * @cloned: Head may be cloned (check refcnt to be sure) - * @nohdr: Payload reference only, must not modify header - * @pkt_type: Packet class - * @fclone: skbuff clone status - * @ip_summed: Driver fed us an IP checksum - * @priority: Packet queueing priority - * @users: User count - see {datagram,tcp}.c - * @protocol: Packet protocol from driver - * @truesize: Buffer size - * @head: Head of buffer - * @data: Data head pointer - * @tail: Tail pointer - * @end: End pointer - * @destructor: Destruct function - * @mark: Generic packet mark - * @nfct: Associated connection, if any - * @ipvs_property: skbuff is owned by ipvs - * @peeked: this packet has been seen already, so stats have been - * done for it, don't do them again - * @nf_trace: netfilter packet trace flag - * @nfctinfo: Relationship of this skb to the connection - * @nfct_reasm: netfilter conntrack re-assembly pointer - * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c - * @skb_iif: ifindex of device we arrived on - * @rxhash: the packet hash computed on receive - * @queue_mapping: Queue mapping for multiqueue devices - * @tc_index: Traffic control index - * @tc_verd: traffic control verdict - * @ndisc_nodetype: router type (from link layer) - * @dma_cookie: a cookie to one of several possible DMA operations - * done by skb DMA functions - * @secmark: security marking - * @vlan_tci: vlan tag control information - */ - -struct sk_buff { - /* These two members must be first. */ - struct sk_buff *next; - struct sk_buff *prev; - - ktime_t tstamp; - - struct sock *sk; - //struct net_device *dev; - struct ifnet *dev; - - /* - * This is the control buffer. It is free to use for every - * layer. Please put your private variables there. If you - * want to keep them across layers you have to do a skb_clone() - * first. This is owned by whoever has the skb queued ATM. - */ - char cb[48] __aligned(8); - - unsigned long _skb_refdst; -#ifdef CONFIG_XFRM - struct sec_path *sp; -#endif - unsigned int len, - data_len; - u16 mac_len, - hdr_len; - union { - u32 csum; - struct { - u16 csum_start; - u16 csum_offset; - }smbol2; - }smbol1; - u32 priority; - kmemcheck_bitfield_begin(flags1); - u8 local_df:1, - cloned:1, - ip_summed:2, - nohdr:1, - nfctinfo:3; - u8 pkt_type:3, - fclone:2, - ipvs_property:1, - peeked:1, - nf_trace:1; - kmemcheck_bitfield_end(flags1); - u16 protocol; - - void (*destructor)(struct sk_buff *skb); -#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) - struct nf_conntrack *nfct; - struct sk_buff *nfct_reasm; -#endif -#ifdef CONFIG_BRIDGE_NETFILTER - struct nf_bridge_info *nf_bridge; -#endif - - int skb_iif; -#ifdef CONFIG_NET_SCHED - u16 tc_index; /* traffic control index */ -#ifdef CONFIG_NET_CLS_ACT - u16 tc_verd; /* traffic control verdict */ -#endif -#endif - - u32 rxhash; - - kmemcheck_bitfield_begin(flags2); - u16 queue_mapping:16; -#ifdef CONFIG_IPV6_NDISC_NODETYPE - u8 ndisc_nodetype:2, - deliver_no_wcard:1; -#else - u8 deliver_no_wcard:1; -#endif - kmemcheck_bitfield_end(flags2); - - /* 0/14 bit hole */ - -#ifdef CONFIG_NET_DMA - dma_cookie_t dma_cookie; -#endif -#ifdef CONFIG_NETWORK_SECMARK - u32 secmark; -#endif - union { - u32 mark; - u32 dropcount; - }symbol3; - - u16 vlan_tci; - - sk_buff_data_t transport_header; - sk_buff_data_t network_header; - sk_buff_data_t mac_header; - /* These elements must be at the end, see alloc_skb() for details. */ - sk_buff_data_t tail; - sk_buff_data_t end; - unsigned char *head, - *data; - unsigned int truesize; - atomic_t users; + *****************************************************************************/ +#ifndef __OSDEP_BSD_SERVICE_H_ +#define __OSDEP_BSD_SERVICE_H_ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include "usbdevs.h" + +#define USB_DEBUG_VAR rum_debug +#include + +#if 1 //Baron porting from linux, it's all temp solution, needs to check again +#include +#include /* XXX for PCPU_GET */ +// typedef struct semaphore _sema; + typedef struct sema _sema; +// typedef spinlock_t _lock; + typedef struct mtx _lock; + typedef struct mtx _mutex; + typedef struct timer_list _timer; + struct list_head { + struct list_head *next, *prev; + }; + struct __queue { + struct list_head queue; + _lock lock; + }; + + //typedef struct sk_buff _pkt; + typedef struct mbuf _pkt; + typedef struct mbuf _buffer; + + typedef struct __queue _queue; + typedef struct list_head _list; + typedef int _OS_STATUS; + //typedef u32 _irqL; + typedef unsigned long _irqL; + typedef struct ifnet * _nic_hdl; + + typedef pid_t _thread_hdl_; +// typedef struct thread _thread_hdl_; + typedef void thread_return; + typedef void* thread_context; + + typedef void timer_hdl_return; + typedef void* timer_hdl_context; + typedef struct work_struct _workitem; + +#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) +/* emulate a modern version */ +#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35) + +#define WIRELESS_EXT -1 +#define HZ hz +#define spin_lock_irqsave mtx_lock_irqsave +#define spin_lock_bh mtx_lock_irqsave +#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));} +//#define IFT_RTW 0xf9 //ifnet allocate type for RTW +#define free_netdev if_free +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) +#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n)) +/* + * Linux timers are emulated using FreeBSD callout functions + * (and taskqueue functionality). + * + * Currently no timer stats functionality. + * + * See (linux_compat) processes.c + * + */ +struct timer_list { + struct callout callout; + void (*function)(void *); + void *arg; }; -struct sk_buff_head { - /* These two members must be first. */ - struct sk_buff *next; - struct sk_buff *prev; + +struct workqueue_struct; +struct work_struct; +typedef void (*work_func_t)(struct work_struct *work); +/* Values for the state of an item of work (work_struct) */ +typedef enum work_state { + WORK_STATE_UNSET = 0, + WORK_STATE_CALLOUT_PENDING = 1, + WORK_STATE_TASK_PENDING = 2, + WORK_STATE_WORK_CANCELLED = 3 +} work_state_t; + +struct work_struct { + struct task task; /* FreeBSD task */ + work_state_t state; /* the pending or otherwise state of work. */ + work_func_t func; +}; +#define spin_unlock_irqrestore mtx_unlock_irqrestore +#define spin_unlock_bh mtx_unlock_irqrestore +#define mtx_unlock_irqrestore(lock,x) mtx_unlock(lock); +extern void _rtw_spinlock_init(_lock *plock); + +//modify private structure to match freebsd +#define BITS_PER_LONG 32 +union ktime { + s64 tv64; +#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR) + struct { +#ifdef __BIG_ENDIAN + s32 sec, nsec; +#else + s32 nsec, sec; +#endif + } tv; +#endif +}; +#define kmemcheck_bitfield_begin(name) +#define kmemcheck_bitfield_end(name) +#define CHECKSUM_NONE 0 +typedef unsigned char *sk_buff_data_t; +typedef union ktime ktime_t; /* Kill this */ + +void rtw_mtx_lock(_lock *plock); + +void rtw_mtx_unlock(_lock *plock); + +/** + * struct sk_buff - socket buffer + * @next: Next buffer in list + * @prev: Previous buffer in list + * @sk: Socket we are owned by + * @tstamp: Time we arrived + * @dev: Device we arrived on/are leaving by + * @transport_header: Transport layer header + * @network_header: Network layer header + * @mac_header: Link layer header + * @_skb_refdst: destination entry (with norefcount bit) + * @sp: the security path, used for xfrm + * @cb: Control buffer. Free for use by every layer. Put private vars here + * @len: Length of actual data + * @data_len: Data length + * @mac_len: Length of link layer header + * @hdr_len: writable header length of cloned skb + * @csum: Checksum (must include start/offset pair) + * @csum_start: Offset from skb->head where checksumming should start + * @csum_offset: Offset from csum_start where checksum should be stored + * @local_df: allow local fragmentation + * @cloned: Head may be cloned (check refcnt to be sure) + * @nohdr: Payload reference only, must not modify header + * @pkt_type: Packet class + * @fclone: skbuff clone status + * @ip_summed: Driver fed us an IP checksum + * @priority: Packet queueing priority + * @users: User count - see {datagram,tcp}.c + * @protocol: Packet protocol from driver + * @truesize: Buffer size + * @head: Head of buffer + * @data: Data head pointer + * @tail: Tail pointer + * @end: End pointer + * @destructor: Destruct function + * @mark: Generic packet mark + * @nfct: Associated connection, if any + * @ipvs_property: skbuff is owned by ipvs + * @peeked: this packet has been seen already, so stats have been + * done for it, don't do them again + * @nf_trace: netfilter packet trace flag + * @nfctinfo: Relationship of this skb to the connection + * @nfct_reasm: netfilter conntrack re-assembly pointer + * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c + * @skb_iif: ifindex of device we arrived on + * @rxhash: the packet hash computed on receive + * @queue_mapping: Queue mapping for multiqueue devices + * @tc_index: Traffic control index + * @tc_verd: traffic control verdict + * @ndisc_nodetype: router type (from link layer) + * @dma_cookie: a cookie to one of several possible DMA operations + * done by skb DMA functions + * @secmark: security marking + * @vlan_tci: vlan tag control information + */ + +struct sk_buff { + /* These two members must be first. */ + struct sk_buff *next; + struct sk_buff *prev; + + ktime_t tstamp; + + struct sock *sk; + //struct net_device *dev; + struct ifnet *dev; + + /* + * This is the control buffer. It is free to use for every + * layer. Please put your private variables there. If you + * want to keep them across layers you have to do a skb_clone() + * first. This is owned by whoever has the skb queued ATM. + */ + char cb[48] __aligned(8); + + unsigned long _skb_refdst; +#ifdef CONFIG_XFRM + struct sec_path *sp; +#endif + unsigned int len, + data_len; + u16 mac_len, + hdr_len; + union { + u32 csum; + struct { + u16 csum_start; + u16 csum_offset; + }smbol2; + }smbol1; + u32 priority; + kmemcheck_bitfield_begin(flags1); + u8 local_df:1, + cloned:1, + ip_summed:2, + nohdr:1, + nfctinfo:3; + u8 pkt_type:3, + fclone:2, + ipvs_property:1, + peeked:1, + nf_trace:1; + kmemcheck_bitfield_end(flags1); + u16 protocol; + + void (*destructor)(struct sk_buff *skb); +#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) + struct nf_conntrack *nfct; + struct sk_buff *nfct_reasm; +#endif +#ifdef CONFIG_BRIDGE_NETFILTER + struct nf_bridge_info *nf_bridge; +#endif + + int skb_iif; +#ifdef CONFIG_NET_SCHED + u16 tc_index; /* traffic control index */ +#ifdef CONFIG_NET_CLS_ACT + u16 tc_verd; /* traffic control verdict */ +#endif +#endif + + u32 rxhash; + + kmemcheck_bitfield_begin(flags2); + u16 queue_mapping:16; +#ifdef CONFIG_IPV6_NDISC_NODETYPE + u8 ndisc_nodetype:2, + deliver_no_wcard:1; +#else + u8 deliver_no_wcard:1; +#endif + kmemcheck_bitfield_end(flags2); + + /* 0/14 bit hole */ + +#ifdef CONFIG_NET_DMA + dma_cookie_t dma_cookie; +#endif +#ifdef CONFIG_NETWORK_SECMARK + u32 secmark; +#endif + union { + u32 mark; + u32 dropcount; + }symbol3; + + u16 vlan_tci; + + sk_buff_data_t transport_header; + sk_buff_data_t network_header; + sk_buff_data_t mac_header; + /* These elements must be at the end, see alloc_skb() for details. */ + sk_buff_data_t tail; + sk_buff_data_t end; + unsigned char *head, + *data; + unsigned int truesize; + atomic_t users; +}; +struct sk_buff_head { + /* These two members must be first. */ + struct sk_buff *next; + struct sk_buff *prev; + + u32 qlen; + _lock lock; +}; +#define skb_tail_pointer(skb) skb->tail +static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len) +{ + unsigned char *tmp = skb_tail_pointer(skb); + //SKB_LINEAR_ASSERT(skb); + skb->tail += len; + skb->len += len; + return tmp; +} + +static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len) +{ + skb->len -= len; + if(skb->len < skb->data_len) + printf("%s(),%d,error!\n",__FUNCTION__,__LINE__); + return skb->data += len; +} +static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len) +{ + #ifdef PLATFORM_FREEBSD + return __skb_pull(skb, len); + #else + return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len); + #endif //PLATFORM_FREEBSD +} +static inline u32 skb_queue_len(const struct sk_buff_head *list_) +{ + return list_->qlen; +} +static inline void __skb_insert(struct sk_buff *newsk, + struct sk_buff *prev, struct sk_buff *next, + struct sk_buff_head *list) +{ + newsk->next = next; + newsk->prev = prev; + next->prev = prev->next = newsk; + list->qlen++; +} +static inline void __skb_queue_before(struct sk_buff_head *list, + struct sk_buff *next, + struct sk_buff *newsk) +{ + __skb_insert(newsk, next->prev, next, list); +} +static inline void skb_queue_tail(struct sk_buff_head *list, + struct sk_buff *newsk) +{ + mtx_lock(&list->lock); + __skb_queue_before(list, (struct sk_buff *)list, newsk); + mtx_unlock(&list->lock); +} +static inline struct sk_buff *skb_peek(struct sk_buff_head *list_) +{ + struct sk_buff *list = ((struct sk_buff *)list_)->next; + if (list == (struct sk_buff *)list_) + list = NULL; + return list; +} +static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list) +{ + struct sk_buff *next, *prev; + + list->qlen--; + next = skb->next; + prev = skb->prev; + skb->next = skb->prev = NULL; + next->prev = prev; + prev->next = next; +} + +static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list) +{ + mtx_lock(&list->lock); + + struct sk_buff *skb = skb_peek(list); + if (skb) + __skb_unlink(skb, list); + + mtx_unlock(&list->lock); + + return skb; +} +static inline void skb_reserve(struct sk_buff *skb, int len) +{ + skb->data += len; + skb->tail += len; +} +static inline void __skb_queue_head_init(struct sk_buff_head *list) +{ + list->prev = list->next = (struct sk_buff *)list; + list->qlen = 0; +} +/* + * This function creates a split out lock class for each invocation; + * this is needed for now since a whole lot of users of the skb-queue + * infrastructure in drivers have different locking usage (in hardirq) + * than the networking core (in softirq only). In the long run either the + * network layer or drivers should need annotation to consolidate the + * main types of usage into 3 classes. + */ +static inline void skb_queue_head_init(struct sk_buff_head *list) +{ + _rtw_spinlock_init(&list->lock); + __skb_queue_head_init(list); +} +unsigned long copy_from_user(void *to, const void *from, unsigned long n); +unsigned long copy_to_user(void *to, const void *from, unsigned long n); +struct sk_buff * dev_alloc_skb(unsigned int size); +struct sk_buff *skb_clone(const struct sk_buff *skb); +void dev_kfree_skb_any(struct sk_buff *skb); +#endif //Baron porting from linux, it's all temp solution, needs to check again + + +#if 1 // kenny add Linux compatibility code for Linux USB driver +#include + +#define __init // __attribute ((constructor)) +#define __exit // __attribute ((destructor)) + +/* + * Definitions for module_init and module_exit macros. + * + * These macros will use the SYSINIT framework to call a specified + * function (with no arguments) on module loading or unloading. + * + */ + +void module_init_exit_wrapper(void *arg); + +#define module_init(initfn) \ + SYSINIT(mod_init_ ## initfn, \ + SI_SUB_KLD, SI_ORDER_FIRST, \ + module_init_exit_wrapper, initfn) + +#define module_exit(exitfn) \ + SYSUNINIT(mod_exit_ ## exitfn, \ + SI_SUB_KLD, SI_ORDER_ANY, \ + module_init_exit_wrapper, exitfn) + +/* + * The usb_register and usb_deregister functions are used to register + * usb drivers with the usb subsystem. + */ +int usb_register(struct usb_driver *driver); +int usb_deregister(struct usb_driver *driver); + +/* + * usb_get_dev and usb_put_dev - increment/decrement the reference count + * of the usb device structure. + * + * Original body of usb_get_dev: + * + * if (dev) + * get_device(&dev->dev); + * return dev; + * + * Reference counts are not currently used in this compatibility + * layer. So these functions will do nothing. + */ +static inline struct usb_device * +usb_get_dev(struct usb_device *dev) +{ + return dev; +} + +static inline void +usb_put_dev(struct usb_device *dev) +{ + return; +} + + +// rtw_usb_compat_linux +int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags); +int rtw_usb_unlink_urb(struct urb *urb); +int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe); +int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe, + uint8_t request, uint8_t requesttype, + uint16_t value, uint16_t index, void *data, + uint16_t size, usb_timeout_t timeout); +int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index); +int rtw_usb_setup_endpoint(struct usb_device *dev, + struct usb_host_endpoint *uhe, usb_size_t bufsize); +struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags); +struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep); +struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index); +struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no); +void *rtw_usbd_get_intfdata(struct usb_interface *intf); +void rtw_usb_linux_register(void *arg); +void rtw_usb_linux_deregister(void *arg); +void rtw_usb_linux_free_device(struct usb_device *dev); +void rtw_usb_free_urb(struct urb *urb); +void rtw_usb_init_urb(struct urb *urb); +void rtw_usb_kill_urb(struct urb *urb); +void rtw_usb_set_intfdata(struct usb_interface *intf, void *data); +void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev, + struct usb_host_endpoint *uhe, void *buf, + int length, usb_complete_t callback, void *arg); +int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe, + void *data, int len, uint16_t *pactlen, usb_timeout_t timeout); +void *usb_get_intfdata(struct usb_interface *intf); +int usb_linux_init_endpoints(struct usb_device *udev); + + + +typedef struct urb * PURB; + +typedef unsigned gfp_t; +#define __GFP_WAIT ((gfp_t)0x10u) /* Can wait and reschedule? */ +#define __GFP_HIGH ((gfp_t)0x20u) /* Should access emergency pools? */ +#define __GFP_IO ((gfp_t)0x40u) /* Can start physical IO? */ +#define __GFP_FS ((gfp_t)0x80u) /* Can call down to low-level FS? */ +#define __GFP_COLD ((gfp_t)0x100u) /* Cache-cold page required */ +#define __GFP_NOWARN ((gfp_t)0x200u) /* Suppress page allocation failure warning */ +#define __GFP_REPEAT ((gfp_t)0x400u) /* Retry the allocation. Might fail */ +#define __GFP_NOFAIL ((gfp_t)0x800u) /* Retry for ever. Cannot fail */ +#define __GFP_NORETRY ((gfp_t)0x1000u)/* Do not retry. Might fail */ +#define __GFP_NO_GROW ((gfp_t)0x2000u)/* Slab internal usage */ +#define __GFP_COMP ((gfp_t)0x4000u)/* Add compound page metadata */ +#define __GFP_ZERO ((gfp_t)0x8000u)/* Return zeroed page on success */ +#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */ +#define __GFP_HARDWALL ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */ + +/* This equals 0, but use constants in case they ever change */ +#define GFP_NOWAIT (GFP_ATOMIC & ~__GFP_HIGH) +/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */ +#define GFP_ATOMIC (__GFP_HIGH) +#define GFP_NOIO (__GFP_WAIT) +#define GFP_NOFS (__GFP_WAIT | __GFP_IO) +#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS) +#define GFP_USER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL) +#define GFP_HIGHUSER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \ + __GFP_HIGHMEM) + + +#endif // kenny add Linux compatibility code for Linux USB + +__inline static _list *get_next(_list *list) +{ + return list->next; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + + +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) + + +__inline static void _enter_critical(_lock *plock, _irqL *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +__inline static void _exit_critical(_lock *plock, _irqL *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +{ + spin_lock_bh(plock, *pirqL); +} + +__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +{ + spin_unlock_bh(plock, *pirqL); +} + +__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + + mtx_lock(pmutex); + +} + + +__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + + mtx_unlock(pmutex); + +} +static inline void __list_del(struct list_head * prev, struct list_head * next) +{ + next->prev = prev; + prev->next = next; +} +static inline void INIT_LIST_HEAD(struct list_head *list) +{ + list->next = list; + list->prev = list; +} +__inline static void rtw_list_delete(_list *plist) +{ + __list_del(plist->prev, plist->next); + INIT_LIST_HEAD(plist); +} + +static inline void timer_hdl(void *ctx) +{ + _timer *timer = (_timer *)ctx; - u32 qlen; - _lock lock; -}; -#define skb_tail_pointer(skb) skb->tail -static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len) -{ - unsigned char *tmp = skb_tail_pointer(skb); - //SKB_LINEAR_ASSERT(skb); - skb->tail += len; - skb->len += len; - return tmp; -} - -static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len) -{ - skb->len -= len; - if(skb->len < skb->data_len) - printf("%s(),%d,error!\n",__FUNCTION__,__LINE__); - return skb->data += len; -} -static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len) -{ - #ifdef PLATFORM_FREEBSD - return __skb_pull(skb, len); - #else - return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len); - #endif //PLATFORM_FREEBSD -} -static inline u32 skb_queue_len(const struct sk_buff_head *list_) -{ - return list_->qlen; -} -static inline void __skb_insert(struct sk_buff *newsk, - struct sk_buff *prev, struct sk_buff *next, - struct sk_buff_head *list) -{ - newsk->next = next; - newsk->prev = prev; - next->prev = prev->next = newsk; - list->qlen++; -} -static inline void __skb_queue_before(struct sk_buff_head *list, - struct sk_buff *next, - struct sk_buff *newsk) -{ - __skb_insert(newsk, next->prev, next, list); -} -static inline void skb_queue_tail(struct sk_buff_head *list, - struct sk_buff *newsk) -{ - mtx_lock(&list->lock); - __skb_queue_before(list, (struct sk_buff *)list, newsk); - mtx_unlock(&list->lock); -} -static inline struct sk_buff *skb_peek(struct sk_buff_head *list_) -{ - struct sk_buff *list = ((struct sk_buff *)list_)->next; - if (list == (struct sk_buff *)list_) - list = NULL; - return list; -} -static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list) -{ - struct sk_buff *next, *prev; - - list->qlen--; - next = skb->next; - prev = skb->prev; - skb->next = skb->prev = NULL; - next->prev = prev; - prev->next = next; -} - -static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list) -{ - mtx_lock(&list->lock); - - struct sk_buff *skb = skb_peek(list); - if (skb) - __skb_unlink(skb, list); - - mtx_unlock(&list->lock); - - return skb; -} -static inline void skb_reserve(struct sk_buff *skb, int len) -{ - skb->data += len; - skb->tail += len; -} -static inline void __skb_queue_head_init(struct sk_buff_head *list) -{ - list->prev = list->next = (struct sk_buff *)list; - list->qlen = 0; -} -/* - * This function creates a split out lock class for each invocation; - * this is needed for now since a whole lot of users of the skb-queue - * infrastructure in drivers have different locking usage (in hardirq) - * than the networking core (in softirq only). In the long run either the - * network layer or drivers should need annotation to consolidate the - * main types of usage into 3 classes. - */ -static inline void skb_queue_head_init(struct sk_buff_head *list) -{ - _rtw_spinlock_init(&list->lock); - __skb_queue_head_init(list); -} -unsigned long copy_from_user(void *to, const void *from, unsigned long n); -unsigned long copy_to_user(void *to, const void *from, unsigned long n); -struct sk_buff * dev_alloc_skb(unsigned int size); -struct sk_buff *skb_clone(const struct sk_buff *skb); -void dev_kfree_skb_any(struct sk_buff *skb); -#endif //Baron porting from linux, it's all temp solution, needs to check again - - -#if 1 // kenny add Linux compatibility code for Linux USB driver -#include - -#define __init // __attribute ((constructor)) -#define __exit // __attribute ((destructor)) - -/* - * Definitions for module_init and module_exit macros. - * - * These macros will use the SYSINIT framework to call a specified - * function (with no arguments) on module loading or unloading. - * - */ - -void module_init_exit_wrapper(void *arg); - -#define module_init(initfn) \ - SYSINIT(mod_init_ ## initfn, \ - SI_SUB_KLD, SI_ORDER_FIRST, \ - module_init_exit_wrapper, initfn) - -#define module_exit(exitfn) \ - SYSUNINIT(mod_exit_ ## exitfn, \ - SI_SUB_KLD, SI_ORDER_ANY, \ - module_init_exit_wrapper, exitfn) - -/* - * The usb_register and usb_deregister functions are used to register - * usb drivers with the usb subsystem. - */ -int usb_register(struct usb_driver *driver); -int usb_deregister(struct usb_driver *driver); - -/* - * usb_get_dev and usb_put_dev - increment/decrement the reference count - * of the usb device structure. - * - * Original body of usb_get_dev: - * - * if (dev) - * get_device(&dev->dev); - * return dev; - * - * Reference counts are not currently used in this compatibility - * layer. So these functions will do nothing. - */ -static inline struct usb_device * -usb_get_dev(struct usb_device *dev) -{ - return dev; -} - -static inline void -usb_put_dev(struct usb_device *dev) -{ - return; -} - - -// rtw_usb_compat_linux -int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags); -int rtw_usb_unlink_urb(struct urb *urb); -int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe); -int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe, - uint8_t request, uint8_t requesttype, - uint16_t value, uint16_t index, void *data, - uint16_t size, usb_timeout_t timeout); -int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index); -int rtw_usb_setup_endpoint(struct usb_device *dev, - struct usb_host_endpoint *uhe, usb_size_t bufsize); -struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags); -struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep); -struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index); -struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no); -void *rtw_usbd_get_intfdata(struct usb_interface *intf); -void rtw_usb_linux_register(void *arg); -void rtw_usb_linux_deregister(void *arg); -void rtw_usb_linux_free_device(struct usb_device *dev); -void rtw_usb_free_urb(struct urb *urb); -void rtw_usb_init_urb(struct urb *urb); -void rtw_usb_kill_urb(struct urb *urb); -void rtw_usb_set_intfdata(struct usb_interface *intf, void *data); -void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev, - struct usb_host_endpoint *uhe, void *buf, - int length, usb_complete_t callback, void *arg); -int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe, - void *data, int len, uint16_t *pactlen, usb_timeout_t timeout); -void *usb_get_intfdata(struct usb_interface *intf); -int usb_linux_init_endpoints(struct usb_device *udev); - - - -typedef struct urb * PURB; - -typedef unsigned gfp_t; -#define __GFP_WAIT ((gfp_t)0x10u) /* Can wait and reschedule? */ -#define __GFP_HIGH ((gfp_t)0x20u) /* Should access emergency pools? */ -#define __GFP_IO ((gfp_t)0x40u) /* Can start physical IO? */ -#define __GFP_FS ((gfp_t)0x80u) /* Can call down to low-level FS? */ -#define __GFP_COLD ((gfp_t)0x100u) /* Cache-cold page required */ -#define __GFP_NOWARN ((gfp_t)0x200u) /* Suppress page allocation failure warning */ -#define __GFP_REPEAT ((gfp_t)0x400u) /* Retry the allocation. Might fail */ -#define __GFP_NOFAIL ((gfp_t)0x800u) /* Retry for ever. Cannot fail */ -#define __GFP_NORETRY ((gfp_t)0x1000u)/* Do not retry. Might fail */ -#define __GFP_NO_GROW ((gfp_t)0x2000u)/* Slab internal usage */ -#define __GFP_COMP ((gfp_t)0x4000u)/* Add compound page metadata */ -#define __GFP_ZERO ((gfp_t)0x8000u)/* Return zeroed page on success */ -#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */ -#define __GFP_HARDWALL ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */ - -/* This equals 0, but use constants in case they ever change */ -#define GFP_NOWAIT (GFP_ATOMIC & ~__GFP_HIGH) -/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */ -#define GFP_ATOMIC (__GFP_HIGH) -#define GFP_NOIO (__GFP_WAIT) -#define GFP_NOFS (__GFP_WAIT | __GFP_IO) -#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS) -#define GFP_USER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL) -#define GFP_HIGHUSER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \ - __GFP_HIGHMEM) - - -#endif // kenny add Linux compatibility code for Linux USB - -__inline static _list *get_next(_list *list) -{ - return list->next; -} - -__inline static _list *get_list_head(_queue *queue) -{ - return (&(queue->queue)); -} - - -#define LIST_CONTAINOR(ptr, type, member) \ - ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) - - -__inline static void _enter_critical(_lock *plock, _irqL *pirqL) -{ - spin_lock_irqsave(plock, *pirqL); -} - -__inline static void _exit_critical(_lock *plock, _irqL *pirqL) -{ - spin_unlock_irqrestore(plock, *pirqL); -} - -__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) -{ - spin_lock_irqsave(plock, *pirqL); -} - -__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) -{ - spin_unlock_irqrestore(plock, *pirqL); -} - -__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) -{ - spin_lock_bh(plock, *pirqL); -} - -__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) -{ - spin_unlock_bh(plock, *pirqL); -} - -__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - - mtx_lock(pmutex); - -} + rtw_mtx_lock(NULL); + if (callout_pending(&timer->callout)) { + /* callout was reset */ + rtw_mtx_unlock(NULL); + return; + } + if (!callout_active(&timer->callout)) { + /* callout was stopped */ + rtw_mtx_unlock(NULL); + return; + } -__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ + callout_deactivate(&timer->callout); - mtx_unlock(pmutex); + timer->function(timer->arg); -} -static inline void __list_del(struct list_head * prev, struct list_head * next) -{ - next->prev = prev; - prev->next = next; -} -static inline void INIT_LIST_HEAD(struct list_head *list) -{ - list->next = list; - list->prev = list; -} -__inline static void rtw_list_delete(_list *plist) -{ - __list_del(plist->prev, plist->next); - INIT_LIST_HEAD(plist); + rtw_mtx_unlock(NULL); } -__inline static void _init_timer(_timer *ptimer,_nic_hdl padapter,void *pfunc,void* cntx) +static inline void _init_timer(_timer *ptimer, _nic_hdl padapter, void *pfunc, void *cntx) { ptimer->function = pfunc; ptimer->arg = cntx; callout_init(&ptimer->callout, CALLOUT_MPSAFE); } -__inline static void _set_timer(_timer *ptimer,u32 delay_time) -{ - // mod_timer(ptimer , (jiffies+(delay_time*HZ/1000))); - if(ptimer->function && ptimer->arg){ - rtw_mtx_lock(NULL); - callout_reset(&ptimer->callout, delay_time,ptimer->function, ptimer->arg); - rtw_mtx_unlock(NULL); - } -} - -__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) -{ - // del_timer_sync(ptimer); - // *bcancelled= _TRUE;//TRUE ==1; FALSE==0 - rtw_mtx_lock(NULL); - callout_drain(&ptimer->callout); - rtw_mtx_unlock(NULL); -} - -__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) -{ - printf("%s Not implement yet! \n",__FUNCTION__); -} - -__inline static void _set_workitem(_workitem *pwork) -{ - printf("%s Not implement yet! \n",__FUNCTION__); -// schedule_work(pwork); -} - -// -// Global Mutex: can only be used at PASSIVE level. -// - -#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ -} - -#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ -} - -#define ATOMIC_INIT(i) { (i) } - -static __inline void thread_enter(char *name); - -//Atomic integer operations -typedef uint32_t ATOMIC_T ; - -#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc) - -#define rtw_free_netdev(netdev) if_free((netdev)) - -#define NDEV_FMT "%s" -#define NDEV_ARG(ndev) "" -#define ADPT_FMT "%s" -#define ADPT_ARG(adapter) "" -#define FUNC_NDEV_FMT "%s" -#define FUNC_NDEV_ARG(ndev) __func__ -#define FUNC_ADPT_FMT "%s" -#define FUNC_ADPT_ARG(adapter) __func__ - -#define STRUCT_PACKED - -#endif - +__inline static void _set_timer(_timer *ptimer,u32 delay_time) +{ + if (ptimer->function && ptimer->arg) { + rtw_mtx_lock(NULL); + callout_reset(&ptimer->callout, delay_time, timer_hdl, ptimer); + rtw_mtx_unlock(NULL); + } +} + +__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) +{ + rtw_mtx_lock(NULL); + callout_drain(&ptimer->callout); + rtw_mtx_unlock(NULL); + *bcancelled = 1; /* assume an pending timer to be canceled */ +} + +__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +{ + printf("%s Not implement yet! \n",__FUNCTION__); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + printf("%s Not implement yet! \n",__FUNCTION__); +// schedule_work(pwork); +} + +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ +} + +#define ATOMIC_INIT(i) { (i) } + +static __inline void thread_enter(char *name); + +//Atomic integer operations +typedef uint32_t ATOMIC_T ; + +#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc) + +#define rtw_free_netdev(netdev) if_free((netdev)) + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) "" +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) "" +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s" +#define FUNC_ADPT_ARG(adapter) __func__ + +#define STRUCT_PACKED + +#endif + diff --git a/include/osdep_service_ce.h b/include/osdep_service_ce.h index 5f2a78a..bc920c0 100644 --- a/include/osdep_service_ce.h +++ b/include/osdep_service_ce.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,182 +11,190 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __OSDEP_CE_SERVICE_H_ -#define __OSDEP_CE_SERVICE_H_ - - -#include -#include - -#ifdef CONFIG_SDIO_HCI -#include "SDCardDDK.h" -#endif - -#ifdef CONFIG_USB_HCI -#include -#endif - -typedef HANDLE _sema; -typedef LIST_ENTRY _list; -typedef NDIS_STATUS _OS_STATUS; - -typedef NDIS_SPIN_LOCK _lock; - -typedef HANDLE _rwlock; //Mutex - -typedef u32 _irqL; - -typedef NDIS_HANDLE _nic_hdl; - - -typedef NDIS_MINIPORT_TIMER _timer; - -struct __queue { - LIST_ENTRY queue; - _lock lock; + *****************************************************************************/ + +#ifndef __OSDEP_CE_SERVICE_H_ +#define __OSDEP_CE_SERVICE_H_ + + +#include +#include + +#ifdef CONFIG_SDIO_HCI +#include "SDCardDDK.h" +#endif + +#ifdef CONFIG_USB_HCI +#include +#endif + +typedef HANDLE _sema; +typedef LIST_ENTRY _list; +typedef NDIS_STATUS _OS_STATUS; + +typedef NDIS_SPIN_LOCK _lock; + +typedef HANDLE _rwlock; //Mutex + +typedef u32 _irqL; + +typedef NDIS_HANDLE _nic_hdl; + +struct timer_list { + NDIS_MINIPORT_TIMER ndis_timer; + void (*function)(void *); + void *arg; }; - -typedef NDIS_PACKET _pkt; -typedef NDIS_BUFFER _buffer; -typedef struct __queue _queue; - -typedef HANDLE _thread_hdl_; -typedef DWORD thread_return; -typedef void* thread_context; -typedef NDIS_WORK_ITEM _workitem; - -#define thread_exit() ExitThread(STATUS_SUCCESS); return 0; - - -#define SEMA_UPBND (0x7FFFFFFF) //8192 - -__inline static _list *get_prev(_list *list) -{ - return list->Blink; -} - -__inline static _list *get_next(_list *list) -{ - return list->Flink; -} - -__inline static _list *get_list_head(_queue *queue) -{ - return (&(queue->queue)); -} - -#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) - -__inline static void _enter_critical(_lock *plock, _irqL *pirqL) -{ - NdisAcquireSpinLock(plock); -} - -__inline static void _exit_critical(_lock *plock, _irqL *pirqL) -{ - NdisReleaseSpinLock(plock); -} - -__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) -{ - NdisDprAcquireSpinLock(plock); -} - -__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) -{ - NdisDprReleaseSpinLock(plock); -} - - -__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL) -{ - WaitForSingleObject(*prwlock, INFINITE ); - -} - -__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL) -{ - ReleaseMutex(*prwlock); -} - -__inline static void rtw_list_delete(_list *plist) -{ - RemoveEntryList(plist); - InitializeListHead(plist); -} - -#define RTW_TIMER_HDL_ARGS IN PVOID SystemSpecific1, IN PVOID FunctionContext, IN PVOID SystemSpecific2, IN PVOID SystemSpecific3 - -__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx) + +struct __queue { + LIST_ENTRY queue; + _lock lock; +}; + +typedef NDIS_PACKET _pkt; +typedef NDIS_BUFFER _buffer; +typedef struct __queue _queue; + +typedef HANDLE _thread_hdl_; +typedef DWORD thread_return; +typedef void* thread_context; +typedef NDIS_WORK_ITEM _workitem; + + + +#define SEMA_UPBND (0x7FFFFFFF) //8192 + +__inline static _list *get_prev(_list *list) +{ + return list->Blink; +} + +__inline static _list *get_next(_list *list) +{ + return list->Flink; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + +#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) + +__inline static void _enter_critical(_lock *plock, _irqL *pirqL) +{ + NdisAcquireSpinLock(plock); +} + +__inline static void _exit_critical(_lock *plock, _irqL *pirqL) +{ + NdisReleaseSpinLock(plock); +} + +__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprAcquireSpinLock(plock); +} + +__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprReleaseSpinLock(plock); +} + + +__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL) +{ + WaitForSingleObject(*prwlock, INFINITE ); + +} + +__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL) +{ + ReleaseMutex(*prwlock); +} + +__inline static void rtw_list_delete(_list *plist) +{ + RemoveEntryList(plist); + InitializeListHead(plist); +} + +static inline void timer_hdl( + IN PVOID SystemSpecific1, + IN PVOID FunctionContext, + IN PVOID SystemSpecific2, + IN PVOID SystemSpecific3) { - NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx); -} + _timer *timer = (_timer *)FunctionContext; -__inline static void _set_timer(_timer *ptimer,u32 delay_time) -{ - NdisMSetTimer(ptimer,delay_time); + timer->function(timer->arg); } -__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) +static inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx) { - NdisMCancelTimer(ptimer,bcancelled); + ptimer->function = pfunc; + ptimer->arg = cntx; + NdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer); } -__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +static inline void _set_timer(_timer *ptimer, u32 delay_time) { - - NdisInitializeWorkItem(pwork, pfunc, cntx); + NdisMSetTimer(ptimer, delay_time); } -__inline static void _set_workitem(_workitem *pwork) +static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled) { - NdisScheduleWorkItem(pwork); -} - -#define ATOMIC_INIT(i) { (i) } - -// -// Global Mutex: can only be used at PASSIVE level. -// - -#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ - { \ - NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ - NdisMSleep(10000); \ - } \ -} - -#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ -} - -// limitation of path length -#define PATH_LENGTH_MAX MAX_PATH - -//Atomic integer operations -#define ATOMIC_T LONG - -#define NDEV_FMT "%s" -#define NDEV_ARG(ndev) "" -#define ADPT_FMT "%s" -#define ADPT_ARG(adapter) "" -#define FUNC_NDEV_FMT "%s" -#define FUNC_NDEV_ARG(ndev) __func__ -#define FUNC_ADPT_FMT "%s" -#define FUNC_ADPT_ARG(adapter) __func__ - -#define STRUCT_PACKED - - -#endif - + NdisMCancelTimer(ptimer, bcancelled); +} + +__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +{ + + NdisInitializeWorkItem(pwork, pfunc, cntx); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + NdisScheduleWorkItem(pwork); +} + +#define ATOMIC_INIT(i) { (i) } + +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ + { \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ + NdisMSleep(10000); \ + } \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ +} + +// limitation of path length +#define PATH_LENGTH_MAX MAX_PATH + +//Atomic integer operations +#define ATOMIC_T LONG + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) "" +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) "" +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s" +#define FUNC_ADPT_ARG(adapter) __func__ + +#define STRUCT_PACKED + + +#endif + diff --git a/include/osdep_service_linux.h b/include/osdep_service_linux.h index e3f7a6c..3b79bfb 100644 --- a/include/osdep_service_linux.h +++ b/include/osdep_service_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __OSDEP_LINUX_SERVICE_H_ #define __OSDEP_LINUX_SERVICE_H_ @@ -29,10 +24,11 @@ #include #include #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 5)) -#include + #include #endif /* #include */ #include +#include #include #include #include @@ -40,9 +36,9 @@ #include #include #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)) -#include + #include #else -#include + #include #endif #include #include @@ -52,6 +48,7 @@ #include #include #include +#include #include #include #include @@ -62,81 +59,105 @@ #include #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 5, 41)) -#include + #include #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0)) -#include + #include #else -#include + #include #endif #ifdef RTK_DMP_PLATFORM -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12)) -#include -#endif -#include + #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12)) + #include + #endif + #include #endif #ifdef CONFIG_NET_RADIO -#define CONFIG_WIRELESS_EXT + #define CONFIG_WIRELESS_EXT #endif /* Monitor mode */ #include -#include + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) + #include +#endif + #ifdef CONFIG_IOCTL_CFG80211 -/* #include */ -#include + /* #include */ + #include #endif /* CONFIG_IOCTL_CFG80211 */ #ifdef CONFIG_TCP_CSUM_OFFLOAD_TX -#include -#include + #include + #include #endif #ifdef CONFIG_HAS_EARLYSUSPEND -#include + #include #endif /* CONFIG_HAS_EARLYSUSPEND */ #ifdef CONFIG_EFUSE_CONFIG_FILE -#include + #include #endif #ifdef CONFIG_USB_HCI -#include -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21)) -#include -#else -#include -#endif + #include + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21)) + #include + #else + #include + #endif #endif #ifdef CONFIG_BT_COEXIST_SOCKET_TRX -#include -#include -#include -#include -#include + #include + #include + #include + #include + #include #endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ #ifdef CONFIG_USB_HCI -typedef struct urb *PURB; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)) -#ifdef CONFIG_USB_SUSPEND -#define CONFIG_AUTOSUSPEND 1 -#endif + typedef struct urb *PURB; + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)) + #ifdef CONFIG_USB_SUSPEND + #define CONFIG_AUTOSUSPEND 1 + #endif + #endif #endif + +#if defined(CONFIG_RTW_GRO) && (!defined(CONFIG_RTW_NAPI)) + + #error "Enable NAPI before enable GRO\n" + +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) && defined(CONFIG_RTW_NAPI)) + + #error "Linux Kernel version too old (should newer than 2.6.29)\n" + #endif + typedef struct semaphore _sema; typedef spinlock_t _lock; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) -typedef struct mutex _mutex; + typedef struct mutex _mutex; #else -typedef struct semaphore _mutex; + typedef struct semaphore _mutex; #endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) +typedef struct legacy_timer_emu { + struct timer_list t; + void (*function)(unsigned long); + unsigned long data; +} _timer; +#else typedef struct timer_list _timer; +#endif +typedef struct completion _completion; struct __queue { struct list_head queue; @@ -157,45 +178,49 @@ typedef void *_thread_hdl_; typedef int thread_return; typedef void *thread_context; -#define thread_exit() complete_and_exit(NULL, 0) - typedef void timer_hdl_return; typedef void *timer_hdl_context; #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41)) -typedef struct work_struct _workitem; + typedef struct work_struct _workitem; #else -typedef struct tq_struct _workitem; + typedef struct tq_struct _workitem; #endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) -#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) + #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) #endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22)) /* Porting from linux kernel, for compatible with old kernel. */ -static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb) { +static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb) +{ return skb->tail; } -static inline void skb_reset_tail_pointer(struct sk_buff *skb) { +static inline void skb_reset_tail_pointer(struct sk_buff *skb) +{ skb->tail = skb->data; } -static inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset) { +static inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset) +{ skb->tail = skb->data + offset; } -static inline unsigned char *skb_end_pointer(const struct sk_buff *skb) { +static inline unsigned char *skb_end_pointer(const struct sk_buff *skb) +{ return skb->end; } #endif -__inline static _list *get_next(_list *list) { +__inline static _list *get_next(_list *list) +{ return list->next; } -__inline static _list *get_list_head(_queue *queue) { +__inline static _list *get_list_head(_queue *queue) +{ return &(queue->queue); } @@ -204,31 +229,38 @@ __inline static _list *get_list_head(_queue *queue) { ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) -__inline static void _enter_critical(_lock *plock, _irqL *pirqL) { +__inline static void _enter_critical(_lock *plock, _irqL *pirqL) +{ spin_lock_irqsave(plock, *pirqL); } -__inline static void _exit_critical(_lock *plock, _irqL *pirqL) { +__inline static void _exit_critical(_lock *plock, _irqL *pirqL) +{ spin_unlock_irqrestore(plock, *pirqL); } -__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) { +__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ spin_lock_irqsave(plock, *pirqL); } -__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) { +__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ spin_unlock_irqrestore(plock, *pirqL); } -__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) { +__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +{ spin_lock_bh(plock); } -__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) { +__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +{ spin_unlock_bh(plock); } -__inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) { +__inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ int ret = 0; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) /* mutex_lock(pmutex); */ @@ -240,7 +272,8 @@ __inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) { } -__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) { +__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) mutex_unlock(pmutex); #else @@ -248,30 +281,51 @@ __inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) { #endif } -__inline static void rtw_list_delete(_list *plist) { +__inline static void rtw_list_delete(_list *plist) +{ list_del_init(plist); } -#define RTW_TIMER_HDL_ARGS void *FunctionContext +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) +static void legacy_timer_emu_func(struct timer_list *t) +{ + struct legacy_timer_emu *lt = from_timer(lt, t, t); + lt->function(lt->data); +} +#endif -__inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx) { +__inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx) +{ /* setup_timer(ptimer, pfunc,(u32)cntx); */ ptimer->function = pfunc; ptimer->data = (unsigned long)cntx; - init_timer(ptimer); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + timer_setup(&ptimer->t, legacy_timer_emu_func, 0); + #else + init_timer(ptimer); + #endif } -__inline static void _set_timer(_timer *ptimer, u32 delay_time) { - mod_timer(ptimer , (jiffies + (delay_time * HZ / 1000))); +__inline static void _set_timer(_timer *ptimer, u32 delay_time) +{ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + mod_timer(&ptimer->t, (jiffies + (delay_time * HZ / 1000))); + #else + mod_timer(ptimer , (jiffies + (delay_time * HZ / 1000))); + #endif } -__inline static void _cancel_timer(_timer *ptimer, u8 *bcancelled) { - del_timer_sync(ptimer); - *bcancelled = 1; +__inline static void _cancel_timer(_timer *ptimer, u8 *bcancelled) +{ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + *bcancelled = del_timer_sync(&ptimer->t) == 1 ? 1 : 0; + #else + *bcancelled = del_timer_sync(ptimer) == 1 ? 1 : 0; + #endif } - -static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx) { +static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)) INIT_WORK(pwork, pfunc); #elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41)) @@ -281,7 +335,8 @@ static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx) { #endif } -__inline static void _set_workitem(_workitem *pwork) { +__inline static void _set_workitem(_workitem *pwork) +{ #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41)) schedule_work(pwork); #else @@ -289,7 +344,8 @@ __inline static void _set_workitem(_workitem *pwork) { #endif } -__inline static void _cancel_workitem_sync(_workitem *pwork) { +__inline static void _cancel_workitem_sync(_workitem *pwork) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)) cancel_work_sync(pwork); #elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41)) @@ -315,18 +371,20 @@ __inline static void _cancel_workitem_sync(_workitem *pwork) { atomic_dec((atomic_t *)&(_MutexCounter)); \ } -static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) { +static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) return (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) && - netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) && - netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) && - netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3))); + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3))); #else return netif_queue_stopped(pnetdev); #endif } -static inline void rtw_netif_wake_queue(struct net_device *pnetdev) { +static inline void rtw_netif_wake_queue(struct net_device *pnetdev) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) netif_tx_wake_all_queues(pnetdev); #else @@ -334,7 +392,8 @@ static inline void rtw_netif_wake_queue(struct net_device *pnetdev) { #endif } -static inline void rtw_netif_start_queue(struct net_device *pnetdev) { +static inline void rtw_netif_start_queue(struct net_device *pnetdev) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) netif_tx_start_all_queues(pnetdev); #else @@ -342,35 +401,40 @@ static inline void rtw_netif_start_queue(struct net_device *pnetdev) { #endif } -static inline void rtw_netif_stop_queue(struct net_device *pnetdev) { +static inline void rtw_netif_stop_queue(struct net_device *pnetdev) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) netif_tx_stop_all_queues(pnetdev); #else netif_stop_queue(pnetdev); #endif } -static inline void rtw_netif_carrier_on(struct net_device *pnetdev) { +static inline void rtw_netif_carrier_on(struct net_device *pnetdev) +{ netif_device_attach(pnetdev); netif_carrier_on(pnetdev); } -static inline void rtw_merge_string(char *dst, int dst_len, const char *src1, const char *src2) { +static inline int rtw_merge_string(char *dst, int dst_len, const char *src1, const char *src2) +{ int len = 0; len += snprintf(dst + len, dst_len - len, "%s", src1); len += snprintf(dst + len, dst_len - len, "%s", src2); + + return len; } #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) -#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)), (sig), 1) + #define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)), (sig), 1) #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */ -#define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1) + #define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1) #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */ /* Suspend lock prevent system from going suspend */ #ifdef CONFIG_WAKELOCK -#include + #include #elif defined(CONFIG_ANDROID_POWER) -#include + #include #endif /* limitation of path length */ @@ -384,11 +448,11 @@ static inline void rtw_merge_string(char *dst, int dst_len, const char *src1, co #define NDEV_FMT "%s" #define NDEV_ARG(ndev) ndev->name #define ADPT_FMT "%s" -#define ADPT_ARG(adapter) adapter->pnetdev->name +#define ADPT_ARG(adapter) (adapter->pnetdev ? adapter->pnetdev->name : NULL) #define FUNC_NDEV_FMT "%s(%s)" #define FUNC_NDEV_ARG(ndev) __func__, ndev->name #define FUNC_ADPT_FMT "%s(%s)" -#define FUNC_ADPT_ARG(adapter) __func__, adapter->pnetdev->name +#define FUNC_ADPT_ARG(adapter) __func__, (adapter->pnetdev ? adapter->pnetdev->name : NULL) struct rtw_netdev_priv_indicator { void *priv; diff --git a/include/osdep_service_xp.h b/include/osdep_service_xp.h index 61b1a00..fdbdb50 100644 --- a/include/osdep_service_xp.h +++ b/include/osdep_service_xp.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,192 +11,200 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __OSDEP_LINUX_SERVICE_H_ -#define __OSDEP_LINUX_SERVICE_H_ - - #include - #include - #include - #include - -#ifdef CONFIG_USB_HCI - #include - #include - #include -#endif - - typedef KSEMAPHORE _sema; - typedef LIST_ENTRY _list; - typedef NDIS_STATUS _OS_STATUS; - - - typedef NDIS_SPIN_LOCK _lock; - - typedef KMUTEX _mutex; - - typedef KIRQL _irqL; - - // USB_PIPE for WINCE , but handle can be use just integer under windows - typedef NDIS_HANDLE _nic_hdl; - - - typedef NDIS_MINIPORT_TIMER _timer; - - struct __queue { - LIST_ENTRY queue; - _lock lock; + *****************************************************************************/ +#ifndef __OSDEP_LINUX_SERVICE_H_ +#define __OSDEP_LINUX_SERVICE_H_ + + #include + #include + #include + #include + +#ifdef CONFIG_USB_HCI + #include + #include + #include +#endif + + typedef KSEMAPHORE _sema; + typedef LIST_ENTRY _list; + typedef NDIS_STATUS _OS_STATUS; + + + typedef NDIS_SPIN_LOCK _lock; + + typedef KMUTEX _mutex; + + typedef KIRQL _irqL; + + // USB_PIPE for WINCE , but handle can be use just integer under windows + typedef NDIS_HANDLE _nic_hdl; + + struct timer_list { + NDIS_MINIPORT_TIMER ndis_timer; + void (*function)(void *); + void *arg; }; - - typedef NDIS_PACKET _pkt; - typedef NDIS_BUFFER _buffer; - typedef struct __queue _queue; - - typedef PKTHREAD _thread_hdl_; - typedef void thread_return; - typedef void* thread_context; - - typedef NDIS_WORK_ITEM _workitem; - - #define thread_exit() PsTerminateSystemThread(STATUS_SUCCESS); - - #define HZ 10000000 - #define SEMA_UPBND (0x7FFFFFFF) //8192 - -__inline static _list *get_next(_list *list) -{ - return list->Flink; -} - -__inline static _list *get_list_head(_queue *queue) -{ - return (&(queue->queue)); -} - - -#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) - - -__inline static _enter_critical(_lock *plock, _irqL *pirqL) -{ - NdisAcquireSpinLock(plock); -} - -__inline static _exit_critical(_lock *plock, _irqL *pirqL) -{ - NdisReleaseSpinLock(plock); -} - - -__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) + + struct __queue { + LIST_ENTRY queue; + _lock lock; + }; + + typedef NDIS_PACKET _pkt; + typedef NDIS_BUFFER _buffer; + typedef struct __queue _queue; + + typedef PKTHREAD _thread_hdl_; + typedef void thread_return; + typedef void* thread_context; + + typedef NDIS_WORK_ITEM _workitem; + + + #define HZ 10000000 + #define SEMA_UPBND (0x7FFFFFFF) //8192 + +__inline static _list *get_next(_list *list) +{ + return list->Flink; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + + +#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) + + +__inline static _enter_critical(_lock *plock, _irqL *pirqL) +{ + NdisAcquireSpinLock(plock); +} + +__inline static _exit_critical(_lock *plock, _irqL *pirqL) +{ + NdisReleaseSpinLock(plock); +} + + +__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprAcquireSpinLock(plock); +} + +__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprReleaseSpinLock(plock); +} + +__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +{ + NdisDprAcquireSpinLock(plock); +} + +__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +{ + NdisDprReleaseSpinLock(plock); +} + +__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL); +} + + +__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + KeReleaseMutex(pmutex, FALSE); +} + + +__inline static void rtw_list_delete(_list *plist) +{ + RemoveEntryList(plist); + InitializeListHead(plist); +} + +static inline void timer_hdl( + IN PVOID SystemSpecific1, + IN PVOID FunctionContext, + IN PVOID SystemSpecific2, + IN PVOID SystemSpecific3) { - NdisDprAcquireSpinLock(plock); -} + _timer *timer = (_timer *)FunctionContext; -__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) -{ - NdisDprReleaseSpinLock(plock); + timer->function(timer->arg); } -__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +static inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx) { - NdisDprAcquireSpinLock(plock); + ptimer->function = pfunc; + ptimer->arg = cntx; + NdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer); } -__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +static inline void _set_timer(_timer *ptimer, u32 delay_time) { - NdisDprReleaseSpinLock(plock); + NdisMSetTimer(ptimer, delay_time); } -__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL); -} - - -__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled) { - KeReleaseMutex(pmutex, FALSE); -} - - -__inline static void rtw_list_delete(_list *plist) -{ - RemoveEntryList(plist); - InitializeListHead(plist); -} - -#define RTW_TIMER_HDL_ARGS IN PVOID SystemSpecific1, IN PVOID FunctionContext, IN PVOID SystemSpecific2, IN PVOID SystemSpecific3 - -__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx) -{ - NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx); -} - -__inline static void _set_timer(_timer *ptimer,u32 delay_time) -{ - NdisMSetTimer(ptimer,delay_time); -} - -__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) -{ - NdisMCancelTimer(ptimer,bcancelled); -} - -__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) -{ - - NdisInitializeWorkItem(pwork, pfunc, cntx); -} - -__inline static void _set_workitem(_workitem *pwork) -{ - NdisScheduleWorkItem(pwork); -} - - -#define ATOMIC_INIT(i) { (i) } - -// -// Global Mutex: can only be used at PASSIVE level. -// - -#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ - { \ - NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ - NdisMSleep(10000); \ - } \ -} - -#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ -} - -// limitation of path length -#define PATH_LENGTH_MAX MAX_PATH - -//Atomic integer operations -#define ATOMIC_T LONG - - -#define NDEV_FMT "%s" -#define NDEV_ARG(ndev) "" -#define ADPT_FMT "%s" -#define ADPT_ARG(adapter) "" -#define FUNC_NDEV_FMT "%s" -#define FUNC_NDEV_ARG(ndev) __func__ -#define FUNC_ADPT_FMT "%s" -#define FUNC_ADPT_ARG(adapter) __func__ - -#define STRUCT_PACKED - -#endif - + NdisMCancelTimer(ptimer, bcancelled); +} + +__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +{ + + NdisInitializeWorkItem(pwork, pfunc, cntx); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + NdisScheduleWorkItem(pwork); +} + + +#define ATOMIC_INIT(i) { (i) } + +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ + { \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ + NdisMSleep(10000); \ + } \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ +} + +// limitation of path length +#define PATH_LENGTH_MAX MAX_PATH + +//Atomic integer operations +#define ATOMIC_T LONG + + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) "" +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) "" +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s" +#define FUNC_ADPT_ARG(adapter) __func__ + +#define STRUCT_PACKED + +#endif + diff --git a/include/pci_hal.h b/include/pci_hal.h index 8aa1a56..16eac21 100644 --- a/include/pci_hal.h +++ b/include/pci_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PCI_HAL_H__ #define __PCI_HAL_H__ diff --git a/include/pci_ops.h b/include/pci_ops.h index bef8237..f195f5b 100644 --- a/include/pci_ops.h +++ b/include/pci_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PCI_OPS_H_ #define __PCI_OPS_H_ @@ -89,4 +84,8 @@ void rtl8822be_set_intf_ops(struct _io_ops *pops); #endif +#ifdef CONFIG_RTL8821C + void rtl8821ce_set_intf_ops(struct _io_ops *pops); +#endif + #endif diff --git a/include/pci_osintf.h b/include/pci_osintf.h index 3339352..29143ca 100644 --- a/include/pci_osintf.h +++ b/include/pci_osintf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PCI_OSINTF_H #define __PCI_OSINTF_H @@ -33,9 +28,18 @@ #define PCIE_TRANSLATE_OFFSET 0x104 /* translate offset from CTRL_START */ #endif +#define PCI_BC_CLK_REQ BIT0 +#define PCI_BC_ASPM_L0s BIT1 +#define PCI_BC_ASPM_L1 BIT2 +#define PCI_BC_ASPM_L1Off BIT3 +//#define PCI_BC_ASPM_LTR BIT4 +//#define PCI_BC_ASPM_OBFF BIT5 + void rtw_pci_disable_aspm(_adapter *padapter); void rtw_pci_enable_aspm(_adapter *padapter); void PlatformClearPciPMEStatus(PADAPTER Adapter); +void rtw_pci_aspm_config(_adapter *padapter); +void rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 eanble); #ifdef CONFIG_64BIT_DMA u8 PlatformEnableDMA64(PADAPTER Adapter); #endif diff --git a/include/recv_osdep.h b/include/recv_osdep.h index 604875d..7715442 100644 --- a/include/recv_osdep.h +++ b/include/recv_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RECV_OSDEP_H_ #define __RECV_OSDEP_H_ @@ -55,7 +50,12 @@ void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attri void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf); -void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl); +#ifdef PLATFORM_LINUX +#ifdef CONFIG_RTW_NAPI +#include /* struct napi_struct */ +int rtw_recv_napi_poll(struct napi_struct *, int budget); +#endif /* CONFIG_RTW_NAPI */ +#endif /* PLATFORM_LINUX */ #endif /* */ diff --git a/include/rtl8188e_cmd.h b/include/rtl8188e_cmd.h index 6aff8c6..e9f252b 100644 --- a/include/rtl8188e_cmd.h +++ b/include/rtl8188e_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_CMD_H__ #define __RTL8188E_CMD_H__ @@ -141,8 +136,7 @@ typedef struct _RSVDPAGE_LOC_88E { void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); u8 rtl8188e_set_rssi_cmd(PADAPTER padapter, u8 *param); -u8 rtl8188e_set_raid_cmd(_adapter *padapter, u32 bitmap, u8 *arg); -void rtl8188e_Add_RateATid(PADAPTER padapter, u64 rate_bitmap, u8 *arg, u8 rssi_level); +u8 rtl8188e_set_raid_cmd(_adapter *padapter, u32 bitmap, u8 *arg, u8 bw); s32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); /* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */ u8 GetTxBufferRsvdPageNum8188E(_adapter *padapter, bool wowlan); diff --git a/include/rtl8188e_dm.h b/include/rtl8188e_dm.h index a4c2527..501d3a9 100644 --- a/include/rtl8188e_dm.h +++ b/include/rtl8188e_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_DM_H__ #define __RTL8188E_DM_H__ diff --git a/include/rtl8188e_hal.h b/include/rtl8188e_hal.h index 3d2aa1a..4c8ef93 100644 --- a/include/rtl8188e_hal.h +++ b/include/rtl8188e_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_HAL_H__ #define __RTL8188E_HAL_H__ @@ -38,29 +33,6 @@ #include "rtl8188e_sreset.h" #endif -#if 0 - /* Fw Array */ - #define Rtl8188E_FwImageArray Rtl8188EFwImgArray - #define Rtl8188E_FWImgArrayLength Rtl8188EFWImgArrayLength - #ifdef CONFIG_WOWLAN - #define Rtl8188E_FwWoWImageArray Array_MP_8188E_FW_WoWLAN - #define Rtl8188E_FwWoWImgArrayLength ArrayLength_MP_8188E_FW_WoWLAN - #endif /* CONFIG_WOWLAN */ -#endif - - -#define RTL8188E_FW_IMG "rtl8188e/FW_NIC.bin" -#define RTL8188E_FW_WW_IMG "rtl8188e/FW_WoWLAN.bin" -#define RTL8188E_PHY_REG "rtl8188e/PHY_REG.txt" -#define RTL8188E_PHY_RADIO_A "rtl8188e/RadioA.txt" -#define RTL8188E_PHY_RADIO_B "rtl8188e/RadioB.txt" -#define RTL8188E_TXPWR_TRACK "rtl8188e/TxPowerTrack.txt" -#define RTL8188E_AGC_TAB "rtl8188e/AGC_TAB.txt" -#define RTL8188E_PHY_MACREG "rtl8188e/MAC_REG.txt" -#define RTL8188E_PHY_REG_PG "rtl8188e/PHY_REG_PG.txt" -#define RTL8188E_PHY_REG_MP "rtl8188e/PHY_REG_MP.txt" -#define RTL8188E_TXPWR_LMT "rtl8188e/TXPWR_LMT.txt" - /* --------------------------------------------------------------------- */ /* RTL8188E Power Configuration CMDs for USB/SDIO/PCIE interfaces */ /* --------------------------------------------------------------------- */ @@ -138,14 +110,10 @@ typedef struct _RT_8188E_FIRMWARE_HDR { /* #define MAX_RX_DMA_BUFFER_SIZE_88E 0x2400 */ /* 9k for 88E nornal chip , */ /* MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */ -#ifdef CONFIG_USB_HCI - #define RX_DMA_SIZE_88E(__Adapter) 0x2800 /* no cut difference */ -#else - #define RX_DMA_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter)) ? 0x2800 : 0x4000) -#endif +#define RX_DMA_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter))?0x2800:0x4000) #ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_NUM) /* 16 entries, for each is 24 bytes*/ + #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ #else #define RESV_FMWF 0 #endif @@ -161,7 +129,7 @@ typedef struct _RT_8188E_FIRMWARE_HDR { * must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) * 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS null-data */ -#define BCNQ_PAGE_NUM_88E 0x08 +#define BCNQ_PAGE_NUM_88E 0x09 /* For WoWLan , more reserved page */ #ifdef CONFIG_WOWLAN @@ -175,11 +143,7 @@ Tx FIFO Size : previous CUT:22K /I_CUT after:32KB Tx page Size : 128B Total page numbers : 176(0xB0) / 256(0x100) */ -#ifdef CONFIG_USB_HCI - #define TOTAL_PAGE_NUMBER_88E(_Adapter) (0xB0 - 1) /* no cut difference */ -#else - #define TOTAL_PAGE_NUMBER_88E(_Adapter) ((IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ? 0x100 : 0xB0) - 1)/* must reserved 1 page for dma issue */ -#endif +#define TOTAL_PAGE_NUMBER_88E(_Adapter) ((IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)?0x100:0xB0) - 1)/* must reserved 1 page for dma issue */ #define TX_TOTAL_PAGE_NUMBER_88E(_Adapter) (TOTAL_PAGE_NUMBER_88E(_Adapter) - BCNQ_PAGE_NUM_88E - WOWLAN_PAGE_NUM_88E) #define TX_PAGE_BOUNDARY_88E(_Adapter) (TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1) /* beacon header start address */ diff --git a/include/rtl8188e_led.h b/include/rtl8188e_led.h index 8d0feee..d3e7f0b 100644 --- a/include/rtl8188e_led.h +++ b/include/rtl8188e_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_LED_H__ #define __RTL8188E_LED_H__ diff --git a/include/rtl8188e_recv.h b/include/rtl8188e_recv.h index 2f574a8..dc79cbc 100644 --- a/include/rtl8188e_recv.h +++ b/include/rtl8188e_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_RECV_H__ #define __RTL8188E_RECV_H__ diff --git a/include/rtl8188e_rf.h b/include/rtl8188e_rf.h index 6588126..e7f9750 100644 --- a/include/rtl8188e_rf.h +++ b/include/rtl8188e_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_RF_H__ #define __RTL8188E_RF_H__ diff --git a/include/rtl8188e_spec.h b/include/rtl8188e_spec.h index c7698a6..9691f51 100644 --- a/include/rtl8188e_spec.h +++ b/include/rtl8188e_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_SPEC_H__ #define __RTL8188E_SPEC_H__ @@ -47,6 +43,15 @@ #define REG_HISR_88E 0x00B4 /* RTL8188E */ #define REG_HIMRE_88E 0x00B8 /* RTL8188E */ #define REG_HISRE_88E 0x00BC /* RTL8188E */ + +#define REG_DBI_WDATA_8188E 0x0348 /* DBI Write data */ +#define REG_DBI_RDATA_8188E 0x034C /* DBI Read data */ +#define REG_DBI_ADDR_8188E 0x0350 /* DBI Address */ +#define REG_DBI_FLAG_8188E 0x0352 /* DBI Read/Write Flag */ +#define REG_MDIO_WDATA_8188E 0x0354 /* MDIO for Write PCIE PHY */ +#define REG_MDIO_RDATA_8188E 0x0356 /* MDIO for Reads PCIE PHY */ +#define REG_MDIO_CTL_8188E 0x0358 /* MDIO for Control */ + #define REG_MACID_NO_LINK_0 0x0484 #define REG_MACID_NO_LINK_1 0x0488 #define REG_MACID_PAUSE_0 0x048c @@ -142,19 +147,6 @@ #define RT_AC_INT_MASKS (IMR_VIDOK_88E | IMR_VODOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E) #endif - -/* ******************************************************** - * General definitions - * ******************************************************** */ - -#define MACID_NUM_88E 64 -#define SEC_CAM_ENT_NUM_88E 32 -#define HW_PORT_NUM_88E 2 -#define NSS_NUM_88E 1 -#define BAND_CAP_88E (BAND_CAP_2G) -#define BW_CAP_88E (BW_CAP_20M | BW_CAP_40M) -#define PROTO_CAP_88E (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N) - /* ---------------------------------------------------------------------------- * 8192C EEPROM/EFUSE share register definition. * ---------------------------------------------------------------------------- */ diff --git a/include/rtl8188e_sreset.h b/include/rtl8188e_sreset.h index d0214ac..f4ec2d8 100644 --- a/include/rtl8188e_sreset.h +++ b/include/rtl8188e_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8188E_SRESET_H_ #define _RTL8188E_SRESET_H_ diff --git a/include/rtl8188e_xmit.h b/include/rtl8188e_xmit.h index c04a66c..f625576 100644 --- a/include/rtl8188e_xmit.h +++ b/include/rtl8188e_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_XMIT_H__ #define __RTL8188E_XMIT_H__ diff --git a/include/rtl8188f_cmd.h b/include/rtl8188f_cmd.h index 5231234..16e0a96 100644 --- a/include/rtl8188f_cmd.h +++ b/include/rtl8188f_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_CMD_H__ #define __RTL8188F_CMD_H__ @@ -184,36 +179,35 @@ enum h2c_cmd_8188F { void rtl8188f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8188f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); void rtl8188f_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8188f_Add_RateATid(PADAPTER pAdapter, u64 bitmap, u8 *arg, u8 rssi_level); void rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); /* s32 rtl8188f_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ void rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8188f_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask); +void rtl8188f_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); void rtl8188f_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus); #ifdef CONFIG_BT_COEXIST void rtl8188f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); #endif /* CONFIG_BT_COEXIST */ #ifdef CONFIG_P2P - void rtl8188f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); +void rtl8188f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ void CheckFwRsvdPageContent(PADAPTER padapter); #ifdef CONFIG_TDLS - #ifdef CONFIG_TDLS_CH_SW - void rtl8188f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); - #endif +#ifdef CONFIG_TDLS_CH_SW +void rtl8188f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); +#endif #endif #ifdef CONFIG_P2P_WOWLAN - void rtl8188f_set_p2p_wowlan_offload_cmd(PADAPTER padapter); +void rtl8188f_set_p2p_wowlan_offload_cmd(PADAPTER padapter); #endif void rtl8188f_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); #ifdef CONFIG_TSF_RESET_OFFLOAD - u8 rtl8188f_reset_tsf(_adapter *padapter, u8 reset_port); +u8 rtl8188f_reset_tsf(_adapter *padapter, u8 reset_port); #endif /* CONFIG_TSF_RESET_OFFLOAD */ s32 FillH2CCmd8188F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8188F(_adapter *padapter, bool wowlan); diff --git a/include/rtl8188f_dm.h b/include/rtl8188f_dm.h index 78aeab0..4af0338 100644 --- a/include/rtl8188f_dm.h +++ b/include/rtl8188f_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_DM_H__ #define __RTL8188F_DM_H__ /* ************************************************************ diff --git a/include/rtl8188f_hal.h b/include/rtl8188f_hal.h index 105ded4..9f36709 100644 --- a/include/rtl8188f_hal.h +++ b/include/rtl8188f_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_HAL_H__ #define __RTL8188F_HAL_H__ @@ -33,41 +28,9 @@ #include "Hal8188FPhyReg.h" #include "Hal8188FPhyCfg.h" #ifdef DBG_CONFIG_ERROR_DETECT - #include "rtl8188f_sreset.h" -#endif - - -/* --------------------------------------------------------------------- - * RTL8188F From file - * --------------------------------------------------------------------- */ -#define RTL8188F_FW_IMG "rtl8188f/FW_NIC.bin" -#define RTL8188F_FW_WW_IMG "rtl8188f/FW_WoWLAN.bin" -#define RTL8188F_PHY_REG "rtl8188f/PHY_REG.txt" -#define RTL8188F_PHY_RADIO_A "rtl8188f/RadioA.txt" -#define RTL8188F_PHY_RADIO_B "rtl8188f/RadioB.txt" -#define RTL8188F_TXPWR_TRACK "rtl8188f/TxPowerTrack.txt" -#define RTL8188F_AGC_TAB "rtl8188f/AGC_TAB.txt" -#define RTL8188F_PHY_MACREG "rtl8188f/MAC_REG.txt" -#define RTL8188F_PHY_REG_PG "rtl8188f/PHY_REG_PG.txt" -#define RTL8188F_PHY_REG_MP "rtl8188f/PHY_REG_MP.txt" -#define RTL8188F_TXPWR_LMT "rtl8188f/TXPWR_LMT.txt" - -/* --------------------------------------------------------------------- - * RTL8188F From header - * --------------------------------------------------------------------- */ - -#if MP_DRIVER == 1 - #define Rtl8188F_FwBTImgArray Rtl8188FFwBTImgArray - #define Rtl8188F_FwBTImgArrayLength Rtl8188FFwBTImgArrayLength - - #define Rtl8188F_FwMPImageArray Rtl8188FFwMPImgArray - #define Rtl8188F_FwMPImgArrayLength Rtl8188FMPImgArrayLength - - #define Rtl8188F_PHY_REG_Array_MP Rtl8188F_PHYREG_Array_MP - #define Rtl8188F_PHY_REG_Array_MPLength Rtl8188F_PHYREG_Array_MPLength +#include "rtl8188f_sreset.h" #endif - #define FW_8188F_SIZE 0x8000 #define FW_8188F_START_ADDRESS 0x1000 #define FW_8188F_END_ADDRESS 0x1FFF /* 0x5FFF */ @@ -131,7 +94,7 @@ typedef struct _RT_8188F_FIRMWARE_HDR { #endif #ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_NUM) /* 16 entries, for each is 24 bytes*/ + #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ #else #define RESV_FMWF 0 #endif @@ -150,25 +113,27 @@ typedef struct _RT_8188F_FIRMWARE_HDR { #endif #ifdef CONFIG_PNO_SUPPORT - #undef BCNQ1_PAGE_NUM_8188F - #define BCNQ1_PAGE_NUM_8188F 0x00 /* 0x04 */ +#undef BCNQ1_PAGE_NUM_8188F +#define BCNQ1_PAGE_NUM_8188F 0x00 /* 0x04 */ #endif /* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, PNO: 6 */ + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt:1 ,PNO: 6 + * NS offload:2 NDP info: 1 + */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8188F 0x07 + #define WOWLAN_PAGE_NUM_8188F 0x0b #else #define WOWLAN_PAGE_NUM_8188F 0x00 #endif #ifdef CONFIG_PNO_SUPPORT - #undef WOWLAN_PAGE_NUM_8188F - #define WOWLAN_PAGE_NUM_8188F 0x15 +#undef WOWLAN_PAGE_NUM_8188F +#define WOWLAN_PAGE_NUM_8188F 0x15 #endif #ifdef CONFIG_AP_WOWLAN - #define AP_WOWLAN_PAGE_NUM_8188F 0x02 +#define AP_WOWLAN_PAGE_NUM_8188F 0x02 #endif #define TX_TOTAL_PAGE_NUMBER_8188F (0xFF - BCNQ_PAGE_NUM_8188F - BCNQ1_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F) @@ -192,14 +157,14 @@ typedef struct _RT_8188F_FIRMWARE_HDR { #include "HalVerDef.h" #include "hal_com.h" -#define EFUSE_OOB_PROTECT_BYTES 15 +#define EFUSE_OOB_PROTECT_BYTES (34 + 1) #define HAL_EFUSE_MEMORY #define HWSET_MAX_SIZE_8188F 512 -#define EFUSE_REAL_CONTENT_LEN_8188F 512 +#define EFUSE_REAL_CONTENT_LEN_8188F 256 #define EFUSE_MAP_LEN_8188F 512 -#define EFUSE_MAX_SECTION_8188F 64 +#define EFUSE_MAX_SECTION_8188F (EFUSE_MAP_LEN_8188F / 8) #define EFUSE_IC_ID_OFFSET 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */ #define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8188F) @@ -217,12 +182,6 @@ typedef struct _RT_8188F_FIRMWARE_HDR { #define EFUSE_PROTECT_BYTES_BANK 16 -typedef struct _C2H_EVT_HDR { - u8 CmdID; - u8 CmdLen; - u8 CmdSeq; -} __attribute__((__packed__)) C2H_EVT_HDR, *PC2H_EVT_HDR; - #define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) #define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) @@ -257,11 +216,7 @@ void Hal_EfuseParseThermalMeter_8188F(PADAPTER padapter, u8 *hwinfo, u8 AutoLoad void Hal_EfuseParseKFreeData_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); #if 0 /* Do not need for rtl8188f */ - VOID Hal_EfuseParseVoltage_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -#endif - -#ifdef CONFIG_C2H_PACKET_EN - void rtl8188f_c2h_packet_handler(PADAPTER padapter, u8 *pbuf, u16 length); +VOID Hal_EfuseParseVoltage_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); #endif void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel); @@ -270,9 +225,6 @@ void rtl8188f_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8188f(_adapter *adapter); void SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val); -#ifdef CONFIG_C2H_PACKET_EN - void SetHwRegWithBuf8188F(PADAPTER padapter, u8 variable, u8 *pbuf, int len); -#endif /* CONFIG_C2H_PACKET_EN */ u8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); @@ -282,7 +234,7 @@ void rtl8188f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); void _InitBurstPktLen_8188FS(PADAPTER Adapter); void _8051Reset8188(PADAPTER padapter); #ifdef CONFIG_WOWLAN - void Hal_DetectWoWMode(PADAPTER pAdapter); +void Hal_DetectWoWMode(PADAPTER pAdapter); #endif /* CONFIG_WOWLAN */ void rtl8188f_start_thread(_adapter *padapter); @@ -296,23 +248,21 @@ void rtl8188f_stop_thread(_adapter *padapter); #endif #ifdef CONFIG_GPIO_WAKEUP - void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); +void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); #endif +#ifdef CONFIG_MP_INCLUDED int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); +#endif void CCX_FwC2HTxRpt_8188f(PADAPTER padapter, u8 *pdata, u8 len); -#ifdef CONFIG_FW_C2H_DEBUG - void Debug_FwC2H_8188f(PADAPTER padapter, u8 *pdata, u8 len); -#endif /* CONFIG_FW_C2H_DEBUG */ -s32 c2h_id_filter_ccx_8188f(u8 *buf); -s32 c2h_handler_8188f(PADAPTER padapter, u8 *pC2hEvent); + u8 MRateToHwRate8188F(u8 rate); u8 HwRateToMRate8188F(u8 rate); #ifdef CONFIG_PCI_HCI - BOOLEAN InterruptRecognized8188FE(PADAPTER Adapter); - VOID UpdateInterruptMask8188FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); +BOOLEAN InterruptRecognized8188FE(PADAPTER Adapter); +VOID UpdateInterruptMask8188FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); #endif #endif diff --git a/include/rtl8188f_led.h b/include/rtl8188f_led.h index ffe76c4..ffd1971 100644 --- a/include/rtl8188f_led.h +++ b/include/rtl8188f_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_LED_H__ #define __RTL8188F_LED_H__ @@ -29,20 +24,20 @@ * Interface to manipulate LED objects. * ******************************************************************************** */ #ifdef CONFIG_USB_HCI - void rtl8188fu_InitSwLeds(PADAPTER padapter); - void rtl8188fu_DeInitSwLeds(PADAPTER padapter); +void rtl8188fu_InitSwLeds(PADAPTER padapter); +void rtl8188fu_DeInitSwLeds(PADAPTER padapter); #endif #ifdef CONFIG_SDIO_HCI - void rtl8188fs_InitSwLeds(PADAPTER padapter); - void rtl8188fs_DeInitSwLeds(PADAPTER padapter); +void rtl8188fs_InitSwLeds(PADAPTER padapter); +void rtl8188fs_DeInitSwLeds(PADAPTER padapter); #endif #ifdef CONFIG_GSPI_HCI - void rtl8188fs_InitSwLeds(PADAPTER padapter); - void rtl8188fs_DeInitSwLeds(PADAPTER padapter); +void rtl8188fs_InitSwLeds(PADAPTER padapter); +void rtl8188fs_DeInitSwLeds(PADAPTER padapter); #endif #ifdef CONFIG_PCI_HCI - void rtl8188fe_InitSwLeds(PADAPTER padapter); - void rtl8188fe_DeInitSwLeds(PADAPTER padapter); +void rtl8188fe_InitSwLeds(PADAPTER padapter); +void rtl8188fe_DeInitSwLeds(PADAPTER padapter); #endif #endif diff --git a/include/rtl8188f_recv.h b/include/rtl8188f_recv.h index 2e1b664..6366b81 100644 --- a/include/rtl8188f_recv.h +++ b/include/rtl8188f_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_RECV_H__ #define __RTL8188F_RECV_H__ @@ -52,19 +47,20 @@ #define Rx_Smooth_Factor (20) #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - s32 rtl8188fs_init_recv_priv(PADAPTER padapter); - void rtl8188fs_free_recv_priv(PADAPTER padapter); +s32 rtl8188fs_init_recv_priv(PADAPTER padapter); +void rtl8188fs_free_recv_priv(PADAPTER padapter); +s32 rtl8188fs_recv_hdl(_adapter *padapter); #endif #ifdef CONFIG_USB_HCI - int rtl8188fu_init_recv_priv(_adapter *padapter); - void rtl8188fu_free_recv_priv(_adapter *padapter); - void rtl8188fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); +int rtl8188fu_init_recv_priv(_adapter *padapter); +void rtl8188fu_free_recv_priv(_adapter *padapter); +void rtl8188fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); #endif #ifdef CONFIG_PCI_HCI - s32 rtl8188fe_init_recv_priv(PADAPTER padapter); - void rtl8188fe_free_recv_priv(PADAPTER padapter); +s32 rtl8188fe_init_recv_priv(PADAPTER padapter); +void rtl8188fe_free_recv_priv(PADAPTER padapter); #endif void rtl8188f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); diff --git a/include/rtl8188f_rf.h b/include/rtl8188f_rf.h index 185d2d0..eef9337 100644 --- a/include/rtl8188f_rf.h +++ b/include/rtl8188f_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_RF_H__ #define __RTL8188F_RF_H__ diff --git a/include/rtl8188f_spec.h b/include/rtl8188f_spec.h index 193bc6f..6e99acf 100644 --- a/include/rtl8188f_spec.h +++ b/include/rtl8188f_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_SPEC_H__ #define __RTL8188F_SPEC_H__ @@ -110,8 +106,8 @@ #define REG_TXPKTBUF_MGQ_BDNY_8188F 0x0425 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F 0x045D #ifdef CONFIG_WOWLAN - #define REG_TXPKTBUF_IV_LOW 0x0484 - #define REG_TXPKTBUF_IV_HIGH 0x0488 +#define REG_TXPKTBUF_IV_LOW 0x0484 +#define REG_TXPKTBUF_IV_HIGH 0x0488 #endif #define REG_AMPDU_BURST_MODE_8188F 0x04BC @@ -200,9 +196,9 @@ #define RXDMA_AGG_MODE_EN BIT(1) #ifdef CONFIG_WOWLAN - #define RXPKT_RELEASE_POLL BIT(16) - #define RXDMA_IDLE BIT(17) - #define RW_RELEASE_EN BIT(18) +#define RXPKT_RELEASE_POLL BIT(16) +#define RXDMA_IDLE BIT(17) +#define RW_RELEASE_EN BIT(18) #endif /* ----------------------------------------------------- @@ -214,7 +210,7 @@ /* ---------------------------------------------------------------------------- * 8188F REG_CCK_CHECK (offset 0x454) * ---------------------------------------------------------------------------- */ -#define BIT_BCN_PORT_SEL BIT5 +#define BIT_BCN_PORT_SEL BIT(5) /* ----------------------------------------------------- * @@ -233,71 +229,59 @@ * ---------------------------------------------------------------------------- */ #define IMR_DISABLED_8188F 0 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ -#define IMR_TIMER2_8188F BIT31 /* Timeout interrupt 2 */ -#define IMR_TIMER1_8188F BIT30 /* Timeout interrupt 1 */ -#define IMR_PSTIMEOUT_8188F BIT29 /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_8188F BIT28 /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_8188F BIT27 /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TXBCN0ERR_8188F BIT26 /* Transmit Beacon0 Error */ -#define IMR_TXBCN0OK_8188F BIT25 /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_8188F BIT24 /* TSF Timer BIT32 toggle indication interrupt */ -#define IMR_BCNDMAINT0_8188F BIT20 /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_8188F BIT16 /* Beacon Queue DMA OK0 */ -#define IMR_HSISR_IND_ON_INT_8188F BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_8188F BIT14 /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_8188F BIT12 /* CTWidnow End or ATIM Window End */ -#define IMR_C2HCMD_8188F BIT10 /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_8188F BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_8188F BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_8188F BIT7 /* High Queue DMA OK */ -#define IMR_MGNTDOK_8188F BIT6 /* Management Queue DMA OK */ -#define IMR_BKDOK_8188F BIT5 /* AC_BK DMA OK */ -#define IMR_BEDOK_8188F BIT4 /* AC_BE DMA OK */ -#define IMR_VIDOK_8188F BIT3 /* AC_VI DMA OK */ -#define IMR_VODOK_8188F BIT2 /* AC_VO DMA OK */ -#define IMR_RDU_8188F BIT1 /* Rx Descriptor Unavailable */ -#define IMR_ROK_8188F BIT0 /* Receive DMA OK */ +#define IMR_TIMER2_8188F BIT(31) /* Timeout interrupt 2 */ +#define IMR_TIMER1_8188F BIT(30) /* Timeout interrupt 1 */ +#define IMR_PSTIMEOUT_8188F BIT(29) /* Power Save Time Out Interrupt */ +#define IMR_GTINT4_8188F BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ +#define IMR_GTINT3_8188F BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ +#define IMR_TXBCN0ERR_8188F BIT(26) /* Transmit Beacon0 Error */ +#define IMR_TXBCN0OK_8188F BIT(25) /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_8188F BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */ +#define IMR_BCNDMAINT0_8188F BIT(20) /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_8188F BIT(16) /* Beacon Queue DMA OK0 */ +#define IMR_HSISR_IND_ON_INT_8188F BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ +#define IMR_BCNDMAINT_E_8188F BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ +#define IMR_ATIMEND_8188F BIT(12) /* CTWidnow End or ATIM Window End */ +#define IMR_C2HCMD_8188F BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ +#define IMR_CPWM2_8188F BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_CPWM_8188F BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_HIGHDOK_8188F BIT(7) /* High Queue DMA OK */ +#define IMR_MGNTDOK_8188F BIT(6) /* Management Queue DMA OK */ +#define IMR_BKDOK_8188F BIT(5) /* AC_BK DMA OK */ +#define IMR_BEDOK_8188F BIT(4) /* AC_BE DMA OK */ +#define IMR_VIDOK_8188F BIT(3) /* AC_VI DMA OK */ +#define IMR_VODOK_8188F BIT(2) /* AC_VO DMA OK */ +#define IMR_RDU_8188F BIT(1) /* Rx Descriptor Unavailable */ +#define IMR_ROK_8188F BIT(0) /* Receive DMA OK */ /* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_8188F BIT27 /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_8188F BIT26 /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_8188F BIT25 /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_8188F BIT24 /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_8188F BIT23 /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_8188F BIT22 /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_8188F BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8188F BIT20 /* Beacon Queue DMA OK Interrup 7 */ -#define IMR_BCNDOK6_8188F BIT19 /* Beacon Queue DMA OK Interrup 6 */ -#define IMR_BCNDOK5_8188F BIT18 /* Beacon Queue DMA OK Interrup 5 */ -#define IMR_BCNDOK4_8188F BIT17 /* Beacon Queue DMA OK Interrup 4 */ -#define IMR_BCNDOK3_8188F BIT16 /* Beacon Queue DMA OK Interrup 3 */ -#define IMR_BCNDOK2_8188F BIT15 /* Beacon Queue DMA OK Interrup 2 */ -#define IMR_BCNDOK1_8188F BIT14 /* Beacon Queue DMA OK Interrup 1 */ -#define IMR_ATIMEND_E_8188F BIT13 /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_8188F BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_8188F BIT10 /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_8188F BIT9 /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_8188F BIT8 /* Receive FIFO Overflow */ +#define IMR_BCNDMAINT7_8188F BIT(27) /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_8188F BIT(26) /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_8188F BIT(25) /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_8188F BIT(24) /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_8188F BIT(23) /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_8188F BIT(22) /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_8188F BIT(21) /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDOK7_8188F BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ +#define IMR_BCNDOK6_8188F BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ +#define IMR_BCNDOK5_8188F BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ +#define IMR_BCNDOK4_8188F BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ +#define IMR_BCNDOK3_8188F BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ +#define IMR_BCNDOK2_8188F BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ +#define IMR_BCNDOK1_8188F BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ +#define IMR_ATIMEND_E_8188F BIT(13) /* ATIM Window End Extension for Win7 */ +#define IMR_TXERR_8188F BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ +#define IMR_RXERR_8188F BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ +#define IMR_TXFOVW_8188F BIT(9) /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_8188F BIT(8) /* Receive FIFO Overflow */ #ifdef CONFIG_PCI_HCI - /* #define IMR_RX_MASK (IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F) */ - #define IMR_TX_MASK (IMR_VODOK_8188F | IMR_VIDOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F | IMR_MGNTDOK_8188F | IMR_HIGHDOK_8188F) +/* #define IMR_RX_MASK (IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F) */ +#define IMR_TX_MASK (IMR_VODOK_8188F | IMR_VIDOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F | IMR_MGNTDOK_8188F | IMR_HIGHDOK_8188F) - #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F) +#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F) - #define RT_AC_INT_MASKS (IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F) +#define RT_AC_INT_MASKS (IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F) #endif -/* ******************************************************** - * General definitions - * ******************************************************** */ - -#define MACID_NUM_8188F 16 -#define SEC_CAM_ENT_NUM_8188F 16 -#define HW_PORT_NUM_8188F 2 -#define NSS_NUM_8188F 1 -#define BAND_CAP_8188F (BAND_CAP_2G) -#define BW_CAP_8188F (BW_CAP_20M | BW_CAP_40M) -#define PROTO_CAP_8188F (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N) - #endif /* __RTL8188F_SPEC_H__ */ diff --git a/include/rtl8188f_sreset.h b/include/rtl8188f_sreset.h index 3aa513d..fe56567 100644 --- a/include/rtl8188f_sreset.h +++ b/include/rtl8188f_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,19 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8188F_SRESET_H_ #define _RTL8188F_SRESET_H_ #include #ifdef DBG_CONFIG_ERROR_DETECT - extern void rtl8188f_sreset_xmit_status_check(_adapter *padapter); - extern void rtl8188f_sreset_linked_status_check(_adapter *padapter); +extern void rtl8188f_sreset_xmit_status_check(_adapter *padapter); +extern void rtl8188f_sreset_linked_status_check(_adapter *padapter); #endif #endif diff --git a/include/rtl8188f_xmit.h b/include/rtl8188f_xmit.h index 7810692..069183d 100644 --- a/include/rtl8188f_xmit.h +++ b/include/rtl8188f_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_XMIT_H__ #define __RTL8188F_XMIT_H__ @@ -25,200 +20,200 @@ #ifndef __INC_HAL8188FDESC_H - #define __INC_HAL8188FDESC_H - - #define RX_STATUS_DESC_SIZE_8188F 24 - #define RX_DRV_INFO_SIZE_UNIT_8188F 8 - - - /* DWORD 0 */ - #define SET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) - #define SET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) - #define SET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) - - #define GET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) - #define GET_RX_STATUS_DESC_CRC32_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) - #define GET_RX_STATUS_DESC_ICV_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) - #define GET_RX_STATUS_DESC_DRVINFO_SIZE_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) - #define GET_RX_STATUS_DESC_SECURITY_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) - #define GET_RX_STATUS_DESC_QOS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) - #define GET_RX_STATUS_DESC_SHIFT_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) - #define GET_RX_STATUS_DESC_PHY_STATUS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) - #define GET_RX_STATUS_DESC_SWDEC_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) - #define GET_RX_STATUS_DESC_LAST_SEG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1) - #define GET_RX_STATUS_DESC_FIRST_SEG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1) - #define GET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) - #define GET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) - - /* DWORD 1 */ - #define GET_RX_STATUS_DESC_MACID_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) - #define GET_RX_STATUS_DESC_TID_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) - #define GET_RX_STATUS_DESC_AMSDU_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) - #define GET_RX_STATUS_DESC_RXID_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) - #define GET_RX_STATUS_DESC_PAGGR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1) - #define GET_RX_STATUS_DESC_A1_FIT_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4) - #define GET_RX_STATUS_DESC_CHKERR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1) - #define GET_RX_STATUS_DESC_IPVER_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) - #define GET_RX_STATUS_DESC_IS_TCPUDP__8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) - #define GET_RX_STATUS_DESC_CHK_VLD_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) - #define GET_RX_STATUS_DESC_PAM_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1) - #define GET_RX_STATUS_DESC_PWR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1) - #define GET_RX_STATUS_DESC_MORE_DATA_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1) - #define GET_RX_STATUS_DESC_MORE_FRAG_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1) - #define GET_RX_STATUS_DESC_TYPE_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2) - #define GET_RX_STATUS_DESC_MC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1) - #define GET_RX_STATUS_DESC_BC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1) - - /* DWORD 2 */ - #define GET_RX_STATUS_DESC_SEQ_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) - #define GET_RX_STATUS_DESC_FRAG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) - #define GET_RX_STATUS_DESC_RX_IS_QOS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) - #define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) - #define GET_RX_STATUS_DESC_RPT_SEL_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) - - /* DWORD 3 */ - #define GET_RX_STATUS_DESC_RX_RATE_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) - #define GET_RX_STATUS_DESC_HTC_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) - #define GET_RX_STATUS_DESC_EOSP_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) - #define GET_RX_STATUS_DESC_BSSID_FIT_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) - #ifdef CONFIG_USB_RX_AGGREGATION - #define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) - #endif - #define GET_RX_STATUS_DESC_PATTERN_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) - #define GET_RX_STATUS_DESC_UNICAST_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) - #define GET_RX_STATUS_DESC_MAGIC_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) - - /* DWORD 6 */ - #define GET_RX_STATUS_DESC_SPLCP_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1) - #define GET_RX_STATUS_DESC_LDPC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1) - #define GET_RX_STATUS_DESC_STBC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1) - #define GET_RX_STATUS_DESC_BW_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2) - - /* DWORD 5 */ - #define GET_RX_STATUS_DESC_TSFL_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) - - #define GET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) - #define GET_RX_STATUS_DESC_BUFF_ADDR64_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) - - #define SET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) - - - /* Dword 0 */ - #define GET_TX_DESC_OWN_8188F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) - - #define SET_TX_DESC_PKT_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) - #define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) - #define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) - #define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) - #define SET_TX_DESC_LAST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) - #define SET_TX_DESC_FIRST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) - #define SET_TX_DESC_LINIP_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) - #define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) - #define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) - #define SET_TX_DESC_OWN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) - - /* Dword 1 */ - #define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) - #define SET_TX_DESC_QUEUE_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) - #define SET_TX_DESC_RDG_NAV_EXT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) - #define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) - #define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) - #define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) - #define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) - #define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) - #define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) - - - /* Dword 2 */ - #define SET_TX_DESC_PAID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) - #define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) - #define SET_TX_DESC_AGG_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) - #define SET_TX_DESC_RDG_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) - #define SET_TX_DESC_AGG_BREAK_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) - #define SET_TX_DESC_MORE_FRAG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) - #define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) - #define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) - #define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) - #define SET_TX_DESC_BT_INT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) - #define SET_TX_DESC_GID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) - - - /* Dword 3 */ - #define SET_TX_DESC_WHEADER_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value) - #define SET_TX_DESC_CHK_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value) - #define SET_TX_DESC_EARLY_MODE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) - #define SET_TX_DESC_HWSEQ_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) - #define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) - #define SET_TX_DESC_DISABLE_RTS_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) - #define SET_TX_DESC_DISABLE_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) - #define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) - #define SET_TX_DESC_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) - #define SET_TX_DESC_HW_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) - #define SET_TX_DESC_NAV_USE_HDR_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) - #define SET_TX_DESC_USE_MAX_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) - #define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) - #define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) - #define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) - - /* Dword 4 */ - #define SET_TX_DESC_TX_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) - #define SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) - #define SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) - #define SET_TX_DESC_RETRY_LIMIT_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) - #define SET_TX_DESC_DATA_RETRY_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) - #define SET_TX_DESC_RTS_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) - - - /* Dword 5 */ - #define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) - #define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) - #define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) - #define SET_TX_DESC_DATA_LDPC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) - #define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) - #define SET_TX_DESC_CTROL_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) - #define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) - #define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) - - - /* Dword 6 */ - #define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) - #define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) - #define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) - #define SET_TX_DESC_ANTSEL_B_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) - #define SET_TX_DESC_ANTSEL_C_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value) - #define SET_TX_DESC_ANTSEL_D_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) - - /* Dword 7 */ - #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - #define SET_TX_DESC_TX_BUFFER_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) - #else - #define SET_TX_DESC_TX_DESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) - #endif - #define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) - #if (DEV_BUS_TYPE == RT_SDIO_INTERFACE) - #define SET_TX_DESC_SDIO_TXSEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) - #endif - - /* Dword 8 */ - #define SET_TX_DESC_HWSEQ_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) - - /* Dword 9 */ - #define SET_TX_DESC_SEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) - - /* Dword 10 */ - #define SET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value) - #define GET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32) - - /* Dword 11 */ - #define SET_TX_DESC_NEXT_DESC_ADDRESS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value) - - - #define SET_EARLYMODE_PKTNUM_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) - #define SET_EARLYMODE_LEN0_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) - #define SET_EARLYMODE_LEN1_1_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) - #define SET_EARLYMODE_LEN1_2_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) - #define SET_EARLYMODE_LEN2_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) - #define SET_EARLYMODE_LEN3_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) +#define __INC_HAL8188FDESC_H + +#define RX_STATUS_DESC_SIZE_8188F 24 +#define RX_DRV_INFO_SIZE_UNIT_8188F 8 + + +/* DWORD 0 */ +#define SET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) +#define SET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) +#define SET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) + +#define GET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) +#define GET_RX_STATUS_DESC_CRC32_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) +#define GET_RX_STATUS_DESC_ICV_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) +#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) +#define GET_RX_STATUS_DESC_SECURITY_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) +#define GET_RX_STATUS_DESC_QOS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) +#define GET_RX_STATUS_DESC_SHIFT_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) +#define GET_RX_STATUS_DESC_PHY_STATUS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) +#define GET_RX_STATUS_DESC_SWDEC_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) +#define GET_RX_STATUS_DESC_LAST_SEG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1) +#define GET_RX_STATUS_DESC_FIRST_SEG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1) +#define GET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) +#define GET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) + +/* DWORD 1 */ +#define GET_RX_STATUS_DESC_MACID_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) +#define GET_RX_STATUS_DESC_TID_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) +#define GET_RX_STATUS_DESC_AMSDU_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) +#define GET_RX_STATUS_DESC_RXID_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) +#define GET_RX_STATUS_DESC_PAGGR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1) +#define GET_RX_STATUS_DESC_A1_FIT_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4) +#define GET_RX_STATUS_DESC_CHKERR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1) +#define GET_RX_STATUS_DESC_IPVER_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) +#define GET_RX_STATUS_DESC_IS_TCPUDP__8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) +#define GET_RX_STATUS_DESC_CHK_VLD_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) +#define GET_RX_STATUS_DESC_PAM_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1) +#define GET_RX_STATUS_DESC_PWR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1) +#define GET_RX_STATUS_DESC_MORE_DATA_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1) +#define GET_RX_STATUS_DESC_MORE_FRAG_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1) +#define GET_RX_STATUS_DESC_TYPE_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2) +#define GET_RX_STATUS_DESC_MC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1) +#define GET_RX_STATUS_DESC_BC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1) + +/* DWORD 2 */ +#define GET_RX_STATUS_DESC_SEQ_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) +#define GET_RX_STATUS_DESC_FRAG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) +#define GET_RX_STATUS_DESC_RX_IS_QOS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) +#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) +#define GET_RX_STATUS_DESC_RPT_SEL_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) + +/* DWORD 3 */ +#define GET_RX_STATUS_DESC_RX_RATE_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) +#define GET_RX_STATUS_DESC_HTC_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) +#define GET_RX_STATUS_DESC_EOSP_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) +#define GET_RX_STATUS_DESC_BSSID_FIT_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) +#ifdef CONFIG_USB_RX_AGGREGATION +#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) +#endif +#define GET_RX_STATUS_DESC_PATTERN_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) +#define GET_RX_STATUS_DESC_UNICAST_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) +#define GET_RX_STATUS_DESC_MAGIC_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) + +/* DWORD 6 */ +#define GET_RX_STATUS_DESC_SPLCP_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1) +#define GET_RX_STATUS_DESC_LDPC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1) +#define GET_RX_STATUS_DESC_STBC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1) +#define GET_RX_STATUS_DESC_BW_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2) + +/* DWORD 5 */ +#define GET_RX_STATUS_DESC_TSFL_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) + +#define GET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) +#define GET_RX_STATUS_DESC_BUFF_ADDR64_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) + +#define SET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) + + +/* Dword 0 */ +#define GET_TX_DESC_OWN_8188F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) + +#define SET_TX_DESC_PKT_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) +#define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) +#define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) +#define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) +#define SET_TX_DESC_LAST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) +#define SET_TX_DESC_FIRST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) +#define SET_TX_DESC_LINIP_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) +#define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) +#define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) +#define SET_TX_DESC_OWN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) + +/* Dword 1 */ +#define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) +#define SET_TX_DESC_QUEUE_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) +#define SET_TX_DESC_RDG_NAV_EXT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) +#define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) +#define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) +#define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) +#define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) +#define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) +#define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) + + +/* Dword 2 */ +#define SET_TX_DESC_PAID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) +#define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) +#define SET_TX_DESC_AGG_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) +#define SET_TX_DESC_RDG_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) +#define SET_TX_DESC_AGG_BREAK_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) +#define SET_TX_DESC_MORE_FRAG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) +#define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) +#define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) +#define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) +#define SET_TX_DESC_BT_INT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) +#define SET_TX_DESC_GID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) + + +/* Dword 3 */ +#define SET_TX_DESC_WHEADER_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value) +#define SET_TX_DESC_CHK_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value) +#define SET_TX_DESC_EARLY_MODE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) +#define SET_TX_DESC_HWSEQ_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) +#define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) +#define SET_TX_DESC_DISABLE_RTS_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) +#define SET_TX_DESC_DISABLE_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) +#define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) +#define SET_TX_DESC_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) +#define SET_TX_DESC_HW_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) +#define SET_TX_DESC_NAV_USE_HDR_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) +#define SET_TX_DESC_USE_MAX_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) +#define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) +#define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) +#define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) + +/* Dword 4 */ +#define SET_TX_DESC_TX_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) +#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) +#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) +#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) +#define SET_TX_DESC_DATA_RETRY_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) +#define SET_TX_DESC_RTS_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) + + +/* Dword 5 */ +#define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) +#define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) +#define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) +#define SET_TX_DESC_DATA_LDPC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) +#define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) +#define SET_TX_DESC_CTROL_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) +#define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) +#define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) + + +/* Dword 6 */ +#define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) +#define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) +#define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) +#define SET_TX_DESC_ANTSEL_B_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) +#define SET_TX_DESC_ANTSEL_C_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value) +#define SET_TX_DESC_ANTSEL_D_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) + +/* Dword 7 */ +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#define SET_TX_DESC_TX_BUFFER_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) +#else +#define SET_TX_DESC_TX_DESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) +#endif +#define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) +#if (DEV_BUS_TYPE == RT_SDIO_INTERFACE) +#define SET_TX_DESC_SDIO_TXSEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) +#endif + +/* Dword 8 */ +#define SET_TX_DESC_HWSEQ_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) + +/* Dword 9 */ +#define SET_TX_DESC_SEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) + +/* Dword 10 */ +#define SET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value) +#define GET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32) + +/* Dword 11 */ +#define SET_TX_DESC_NEXT_DESC_ADDRESS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value) + + +#define SET_EARLYMODE_PKTNUM_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) +#define SET_EARLYMODE_LEN0_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) +#define SET_EARLYMODE_LEN1_1_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) +#define SET_EARLYMODE_LEN1_2_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) +#define SET_EARLYMODE_LEN2_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) +#define SET_EARLYMODE_LEN3_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) #endif /* ----------------------------------------------------------- @@ -291,45 +286,45 @@ void rtl8188f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); void rtl8188f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); #if defined(CONFIG_CONCURRENT_MODE) - void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); +void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - s32 rtl8188fs_init_xmit_priv(PADAPTER padapter); - void rtl8188fs_free_xmit_priv(PADAPTER padapter); - s32 rtl8188fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8188fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8188fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - s32 rtl8188fs_xmit_buf_handler(PADAPTER padapter); - thread_return rtl8188fs_xmit_thread(thread_context context); - #define hal_xmit_handler rtl8188fs_xmit_buf_handler +s32 rtl8188fs_init_xmit_priv(PADAPTER padapter); +void rtl8188fs_free_xmit_priv(PADAPTER padapter); +s32 rtl8188fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); +s32 rtl8188fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); +s32 rtl8188fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +s32 rtl8188fs_xmit_buf_handler(PADAPTER padapter); +thread_return rtl8188fs_xmit_thread(thread_context context); +#define hal_xmit_handler rtl8188fs_xmit_buf_handler #endif #ifdef CONFIG_USB_HCI - s32 rtl8188fu_xmit_buf_handler(PADAPTER padapter); - #define hal_xmit_handler rtl8188fu_xmit_buf_handler - - - s32 rtl8188fu_init_xmit_priv(PADAPTER padapter); - void rtl8188fu_free_xmit_priv(PADAPTER padapter); - s32 rtl8188fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8188fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8188fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - /* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */ - void rtl8188fu_xmit_tasklet(void *priv); - s32 rtl8188fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); - void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc); +s32 rtl8188fu_xmit_buf_handler(PADAPTER padapter); +#define hal_xmit_handler rtl8188fu_xmit_buf_handler + + +s32 rtl8188fu_init_xmit_priv(PADAPTER padapter); +void rtl8188fu_free_xmit_priv(PADAPTER padapter); +s32 rtl8188fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); +s32 rtl8188fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); +s32 rtl8188fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */ +void rtl8188fu_xmit_tasklet(void *priv); +s32 rtl8188fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); +void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc); #endif #ifdef CONFIG_PCI_HCI - s32 rtl8188fe_init_xmit_priv(PADAPTER padapter); - void rtl8188fe_free_xmit_priv(PADAPTER padapter); - struct xmit_buf *rtl8188fe_dequeue_xmitbuf(struct rtw_tx_ring *ring); - void rtl8188fe_xmitframe_resume(_adapter *padapter); - s32 rtl8188fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8188fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8188fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - void rtl8188fe_xmit_tasklet(void *priv); +s32 rtl8188fe_init_xmit_priv(PADAPTER padapter); +void rtl8188fe_free_xmit_priv(PADAPTER padapter); +struct xmit_buf *rtl8188fe_dequeue_xmitbuf(struct rtw_tx_ring *ring); +void rtl8188fe_xmitframe_resume(_adapter *padapter); +s32 rtl8188fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); +s32 rtl8188fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); +s32 rtl8188fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +void rtl8188fe_xmit_tasklet(void *priv); #endif u8 BWMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib); diff --git a/include/rtl8192e_cmd.h b/include/rtl8192e_cmd.h index 9cdafe5..976bc29 100644 --- a/include/rtl8192e_cmd.h +++ b/include/rtl8192e_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_CMD_H__ #define __RTL8192E_CMD_H__ @@ -122,12 +117,11 @@ typedef struct _RSVDPAGE_LOC_92E { void rtl8192e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8192e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); u8 rtl8192e_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8192e_set_raid_cmd(PADAPTER padapter, u32 bitmap, u8 *arg); -void rtl8192e_Add_RateATid(PADAPTER padapter, u64 rate_bitmap, u8 *arg, u8 rssi_level); +void rtl8192e_set_raid_cmd(PADAPTER padapter, u32 bitmap, u8 *arg, u8 bw); s32 FillH2CCmd_8192E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8192E(_adapter *padapter, bool wowlan); /* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */ -s32 c2h_handler_8192e(PADAPTER padapter, u8 *buf); +s32 c2h_handler_8192e(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); #ifdef CONFIG_BT_COEXIST void rtl8192e_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); #endif /* CONFIG_BT_COEXIST */ @@ -159,19 +153,4 @@ void CheckFwRsvdPageContent(PADAPTER padapter); #define GET_8192E_C2H_TX_RPT_QUEUE_TIME(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) /* In unit of 256 microseconds. */ #define GET_8192E_C2H_TX_RPT_FINAL_DATA_RATE(_Header) LE_BITS_TO_1BYTE((_Header + 5), 0, 8) - - -void C2HContentParsing8192E( - IN PADAPTER Adapter, - IN u1Byte c2hCmdId, - IN u1Byte c2hCmdLen, - IN pu1Byte tmpBuf -); -VOID -C2HPacketHandler_8192E( - IN PADAPTER Adapter, - IN pu1Byte Buffer, - IN u1Byte Length -); - #endif /* __RTL8192E_CMD_H__ */ diff --git a/include/rtl8192e_dm.h b/include/rtl8192e_dm.h index ff1b341..0f3d96d 100644 --- a/include/rtl8192e_dm.h +++ b/include/rtl8192e_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_DM_H__ #define __RTL8192E_DM_H__ diff --git a/include/rtl8192e_hal.h b/include/rtl8192e_hal.h index d64c75d..6799210 100644 --- a/include/rtl8192e_hal.h +++ b/include/rtl8192e_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_HAL_H__ #define __RTL8192E_HAL_H__ @@ -41,23 +36,6 @@ #include "rtl8192e_sreset.h" #endif - -/* --------------------------------------------------------------------- - * RTL8192E From header - * --------------------------------------------------------------------- */ -#define RTL8192E_FW_IMG "rtl8192e/FW_NIC.bin" -#define RTL8192E_FW_WW_IMG "rtl8192e/FW_WoWLAN.bin" -#define RTL8192E_PHY_REG "rtl8192e/PHY_REG.txt" -#define RTL8192E_PHY_RADIO_A "rtl8192e/RadioA.txt" -#define RTL8192E_PHY_RADIO_B "rtl8192e/RadioB.txt" -#define RTL8192E_TXPWR_TRACK "rtl8192e/TxPowerTrack.txt" -#define RTL8192E_AGC_TAB "rtl8192e/AGC_TAB.txt" -#define RTL8192E_PHY_MACREG "rtl8192e/MAC_REG.txt" -#define RTL8192E_PHY_REG_PG "rtl8192e/PHY_REG_PG.txt" -#define RTL8192E_PHY_REG_MP "rtl8192e/PHY_REG_MP.txt" -#define RTL8192E_TXPWR_LMT "rtl8192e/TXPWR_LMT.txt" -#define RTL8192E_WIFI_ANT_ISOLATION "rtl8192e/wifi_ant_isolation.txt" - /* --------------------------------------------------------------------- * RTL8192E Power Configuration CMDs for PCIe interface * --------------------------------------------------------------------- */ @@ -131,7 +109,7 @@ typedef struct _RT_FIRMWARE_8192E { #define RX_DMA_SIZE_8192E 0x4000 /* 16K*/ #ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_NUM) /* 16 entries, for each is 24 bytes*/ + #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ #else #define RESV_FMWF 0 #endif @@ -148,9 +126,11 @@ typedef struct _RT_FIRMWARE_8192E { * Beacon:2, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1 */ #define RSVD_PAGE_NUM_8192E 0x08 /* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, PNO: 6 */ + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6 + * NS offload: 2 NDP info: 1 + */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8192E 0x07 + #define WOWLAN_PAGE_NUM_8192E 0x0b #else #define WOWLAN_PAGE_NUM_8192E 0x00 #endif diff --git a/include/rtl8192e_led.h b/include/rtl8192e_led.h index d79bd91..ad8fd4d 100644 --- a/include/rtl8192e_led.h +++ b/include/rtl8192e_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_LED_H__ #define __RTL8192E_LED_H__ diff --git a/include/rtl8192e_recv.h b/include/rtl8192e_recv.h index 34f081c..7d17b86 100644 --- a/include/rtl8192e_recv.h +++ b/include/rtl8192e_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_RECV_H__ #define __RTL8192E_RECV_H__ diff --git a/include/rtl8192e_rf.h b/include/rtl8192e_rf.h index cd344a4..6a4b9f6 100644 --- a/include/rtl8192e_rf.h +++ b/include/rtl8192e_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_RF_H__ #define __RTL8192E_RF_H__ diff --git a/include/rtl8192e_spec.h b/include/rtl8192e_spec.h index 7b3c83a..8af37a7 100644 --- a/include/rtl8192e_spec.h +++ b/include/rtl8192e_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_SPEC_H__ #define __RTL8192E_SPEC_H__ @@ -232,51 +228,51 @@ * ---------------------------------------------------------------------------- */ #define IMR_DISABLED_8192E 0 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ -#define IMR_TIMER2_8192E BIT31 /* Timeout interrupt 2 */ -#define IMR_TIMER1_8192E BIT30 /* Timeout interrupt 1 */ -#define IMR_PSTIMEOUT_8192E BIT29 /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_8192E BIT28 /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_8192E BIT27 /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TXBCN0ERR_8192E BIT26 /* Transmit Beacon0 Error */ -#define IMR_TXBCN0OK_8192E BIT25 /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_8192E BIT24 /* TSF Timer BIT32 toggle indication interrupt */ -#define IMR_BCNDMAINT0_8192E BIT20 /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_8192E BIT16 /* Beacon Queue DMA OK0 */ -#define IMR_HSISR_IND_ON_INT_8192E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_8192E BIT14 /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_8192E BIT12 /* CTWidnow End or ATIM Window End */ -#define IMR_C2HCMD_8192E BIT10 /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_8192E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_8192E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_8192E BIT7 /* High Queue DMA OK */ -#define IMR_MGNTDOK_8192E BIT6 /* Management Queue DMA OK */ -#define IMR_BKDOK_8192E BIT5 /* AC_BK DMA OK */ -#define IMR_BEDOK_8192E BIT4 /* AC_BE DMA OK */ -#define IMR_VIDOK_8192E BIT3 /* AC_VI DMA OK */ -#define IMR_VODOK_8192E BIT2 /* AC_VO DMA OK */ -#define IMR_RDU_8192E BIT1 /* Rx Descriptor Unavailable */ -#define IMR_ROK_8192E BIT0 /* Receive DMA OK */ +#define IMR_TIMER2_8192E BIT(31) /* Timeout interrupt 2 */ +#define IMR_TIMER1_8192E BIT(30) /* Timeout interrupt 1 */ +#define IMR_PSTIMEOUT_8192E BIT(29) /* Power Save Time Out Interrupt */ +#define IMR_GTINT4_8192E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ +#define IMR_GTINT3_8192E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ +#define IMR_TXBCN0ERR_8192E BIT(26) /* Transmit Beacon0 Error */ +#define IMR_TXBCN0OK_8192E BIT(25) /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_8192E BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */ +#define IMR_BCNDMAINT0_8192E BIT(20) /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_8192E BIT(16) /* Beacon Queue DMA OK0 */ +#define IMR_HSISR_IND_ON_INT_8192E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ +#define IMR_BCNDMAINT_E_8192E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ +#define IMR_ATIMEND_8192E BIT(12) /* CTWidnow End or ATIM Window End */ +#define IMR_C2HCMD_8192E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ +#define IMR_CPWM2_8192E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_CPWM_8192E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_HIGHDOK_8192E BIT(7) /* High Queue DMA OK */ +#define IMR_MGNTDOK_8192E BIT(6) /* Management Queue DMA OK */ +#define IMR_BKDOK_8192E BIT(5) /* AC_BK DMA OK */ +#define IMR_BEDOK_8192E BIT(4) /* AC_BE DMA OK */ +#define IMR_VIDOK_8192E BIT(3) /* AC_VI DMA OK */ +#define IMR_VODOK_8192E BIT(2) /* AC_VO DMA OK */ +#define IMR_RDU_8192E BIT(1) /* Rx Descriptor Unavailable */ +#define IMR_ROK_8192E BIT(0) /* Receive DMA OK */ /* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_8192E BIT27 /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_8192E BIT26 /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_8192E BIT25 /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_8192E BIT24 /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_8192E BIT23 /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_8192E BIT22 /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_8192E BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8192E BIT20 /* Beacon Queue DMA OK Interrup 7 */ -#define IMR_BCNDOK6_8192E BIT19 /* Beacon Queue DMA OK Interrup 6 */ -#define IMR_BCNDOK5_8192E BIT18 /* Beacon Queue DMA OK Interrup 5 */ -#define IMR_BCNDOK4_8192E BIT17 /* Beacon Queue DMA OK Interrup 4 */ -#define IMR_BCNDOK3_8192E BIT16 /* Beacon Queue DMA OK Interrup 3 */ -#define IMR_BCNDOK2_8192E BIT15 /* Beacon Queue DMA OK Interrup 2 */ -#define IMR_BCNDOK1_8192E BIT14 /* Beacon Queue DMA OK Interrup 1 */ -#define IMR_ATIMEND_E_8192E BIT13 /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_8192E BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_8192E BIT10 /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_8192E BIT9 /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_8192E BIT8 /* Receive FIFO Overflow */ +#define IMR_BCNDMAINT7_8192E BIT(27) /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_8192E BIT(26) /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_8192E BIT(25) /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_8192E BIT(24) /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_8192E BIT(23) /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_8192E BIT(22) /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_8192E BIT(21) /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDOK7_8192E BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ +#define IMR_BCNDOK6_8192E BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ +#define IMR_BCNDOK5_8192E BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ +#define IMR_BCNDOK4_8192E BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ +#define IMR_BCNDOK3_8192E BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ +#define IMR_BCNDOK2_8192E BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ +#define IMR_BCNDOK1_8192E BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ +#define IMR_ATIMEND_E_8192E BIT(13) /* ATIM Window End Extension for Win7 */ +#define IMR_TXERR_8192E BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ +#define IMR_RXERR_8192E BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ +#define IMR_TXFOVW_8192E BIT(9) /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_8192E BIT(8) /* Receive FIFO Overflow */ /* ---------------------------------------------------------------------------- * 8192E Auto LLT bits (offset 0x224, 8bits) @@ -287,19 +283,19 @@ /* ---------------------------------------------------------------------------- * 8192E Auto LLT bits (offset 0x290, 32bits) * ---------------------------------------------------------------------------- */ -#define BIT_DMA_MODE BIT1 -#define BIT_USB_RXDMA_AGG_EN BIT31 +#define BIT_DMA_MODE BIT(1) +#define BIT_USB_RXDMA_AGG_EN BIT(31) /* ---------------------------------------------------------------------------- * 8192E REG_SYS_CFG1 (offset 0xF0, 32bits) * ---------------------------------------------------------------------------- */ -#define BIT_SPSLDO_SEL BIT24 +#define BIT_SPSLDO_SEL BIT(24) /* ---------------------------------------------------------------------------- * 8192E REG_CCK_CHECK (offset 0x454, 8bits) * ---------------------------------------------------------------------------- */ -#define BIT_BCN_PORT_SEL BIT5 +#define BIT_BCN_PORT_SEL BIT(5) /* **************************************************************************** * Regsiter Bit and Content definition @@ -314,16 +310,4 @@ #define AcmHw_ViqStatus_8192E BIT(6) #define AcmHw_BeqStatus_8192E BIT(7) -/* ******************************************************** - * General definitions - * ******************************************************** */ - -#define MACID_NUM_8192E 128 -#define SEC_CAM_ENT_NUM_8192E 64 -#define HW_PORT_NUM_8192E 2 -#define NSS_NUM_8192E 2 -#define BAND_CAP_8192E (BAND_CAP_2G) -#define BW_CAP_8192E (BW_CAP_20M | BW_CAP_40M) -#define PROTO_CAP_8192E (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N) - #endif /* __RTL8192E_SPEC_H__ */ diff --git a/include/rtl8192e_sreset.h b/include/rtl8192e_sreset.h index 7430d9a..4273824 100644 --- a/include/rtl8192e_sreset.h +++ b/include/rtl8192e_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL88812A_SRESET_H_ #define _RTL8812A_SRESET_H_ diff --git a/include/rtl8192e_xmit.h b/include/rtl8192e_xmit.h index 23deb8d..a621fd9 100644 --- a/include/rtl8192e_xmit.h +++ b/include/rtl8192e_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_XMIT_H__ #define __RTL8192E_XMIT_H__ diff --git a/include/rtl8703b_cmd.h b/include/rtl8703b_cmd.h index e7a32fe..8e97ec8 100644 --- a/include/rtl8703b_cmd.h +++ b/include/rtl8703b_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_CMD_H__ #define __RTL8703B_CMD_H__ @@ -183,11 +178,10 @@ enum h2c_cmd_8703B { void rtl8703b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8703b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); void rtl8703b_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8703b_Add_RateATid(PADAPTER pAdapter, u64 rate_bitmap, u8 *arg, u8 rssi_level); void rtl8703b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); /* s32 rtl8703b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ void rtl8703b_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8703b_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask); +void rtl8703b_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); void rtl8703b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); void rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus); #ifdef CONFIG_BT_COEXIST diff --git a/include/rtl8703b_dm.h b/include/rtl8703b_dm.h index 4ee834d..7ca7995 100644 --- a/include/rtl8703b_dm.h +++ b/include/rtl8703b_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_DM_H__ #define __RTL8703B_DM_H__ /* ************************************************************ diff --git a/include/rtl8703b_hal.h b/include/rtl8703b_hal.h index 4083242..149320e 100644 --- a/include/rtl8703b_hal.h +++ b/include/rtl8703b_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_HAL_H__ #define __RTL8703B_HAL_H__ @@ -36,35 +31,6 @@ #include "rtl8703b_sreset.h" #endif - -/* --------------------------------------------------------------------- - * RTL8703B From file - * --------------------------------------------------------------------- */ -#define RTL8703B_FW_IMG "rtl8703b/FW_NIC.bin" -#define RTL8703B_FW_WW_IMG "rtl8703b/FW_WoWLAN.bin" -#define RTL8703B_PHY_REG "rtl8703b/PHY_REG.txt" -#define RTL8703B_PHY_RADIO_A "rtl8703b/RadioA.txt" -#define RTL8703B_PHY_RADIO_B "rtl8703b/RadioB.txt" -#define RTL8703B_TXPWR_TRACK "rtl8703b/TxPowerTrack.txt" -#define RTL8703B_AGC_TAB "rtl8703b/AGC_TAB.txt" -#define RTL8703B_PHY_MACREG "rtl8703b/MAC_REG.txt" -#define RTL8703B_PHY_REG_PG "rtl8703b/PHY_REG_PG.txt" -#define RTL8703B_PHY_REG_MP "rtl8703b/PHY_REG_MP.txt" -#define RTL8703B_TXPWR_LMT "rtl8703b/TXPWR_LMT.txt" - -/* --------------------------------------------------------------------- - * RTL8703B From header - * --------------------------------------------------------------------- */ - -#if MP_DRIVER == 1 - #define Rtl8703B_FwBTImgArray Rtl8703BFwBTImgArray - #define Rtl8703B_FwBTImgArrayLength Rtl8703BFwBTImgArrayLength - - #define Rtl8703B_PHY_REG_Array_MP Rtl8703B_PHYREG_Array_MP - #define Rtl8703B_PHY_REG_Array_MPLength Rtl8703B_PHYREG_Array_MPLength -#endif - - #define FW_8703B_SIZE 0x8000 #define FW_8703B_START_ADDRESS 0x1000 #define FW_8703B_END_ADDRESS 0x1FFF /* 0x5FFF */ @@ -124,7 +90,7 @@ typedef struct _RT_8703B_FIRMWARE_HDR { #define RX_DMA_SIZE_8703B 0x4000 /* 16K(RX) */ #ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_NUM) /* 16 entries, for each is 24 bytes*/ + #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ #else #define RESV_FMWF 0 #endif @@ -154,9 +120,11 @@ typedef struct _RT_8703B_FIRMWARE_HDR { #endif /* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, PNO: 6 */ + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1 PNO: 6 + * NS offload: 2NDP info: 1 + */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8703B 0x07 + #define WOWLAN_PAGE_NUM_8703B 0x0b #else #define WOWLAN_PAGE_NUM_8703B 0x00 #endif @@ -216,12 +184,6 @@ typedef struct _RT_8703B_FIRMWARE_HDR { #define EFUSE_BT_MAX_SECTION (EFUSE_BT_MAP_LEN / 8) #define EFUSE_PROTECT_BYTES_BANK 16 -typedef struct _C2H_EVT_HDR { - u8 CmdID; - u8 CmdLen; - u8 CmdSeq; -} __attribute__((__packed__)) C2H_EVT_HDR, *PC2H_EVT_HDR; - typedef enum tag_Package_Definition { PACKAGE_DEFAULT, PACKAGE_QFN68, @@ -263,18 +225,10 @@ void Hal_EfuseParseThermalMeter_8703B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoad VOID Hal_EfuseParseVoltage_8703B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); VOID Hal_EfuseParseBoardType_8703B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -#ifdef CONFIG_C2H_PACKET_EN - void rtl8703b_c2h_packet_handler(PADAPTER padapter, u8 *pbuf, u16 length); -#endif - - void rtl8703b_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8703b(_adapter *adapter); void SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val); -#ifdef CONFIG_C2H_PACKET_EN - void SetHwRegWithBuf8703B(PADAPTER padapter, u8 variable, u8 *pbuf, int len); -#endif /* CONFIG_C2H_PACKET_EN */ u8 SetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); @@ -302,12 +256,11 @@ void rtl8703b_stop_thread(_adapter *padapter); #ifdef CONFIG_GPIO_WAKEUP void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); #endif - +#ifdef CONFIG_MP_INCLUDED int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); - +#endif void CCX_FwC2HTxRpt_8703b(PADAPTER padapter, u8 *pdata, u8 len); -s32 c2h_id_filter_ccx_8703b(u8 *buf); -s32 c2h_handler_8703b(PADAPTER padapter, u8 *pC2hEvent); + u8 MRateToHwRate8703B(u8 rate); u8 HwRateToMRate8703B(u8 rate); diff --git a/include/rtl8703b_led.h b/include/rtl8703b_led.h index fb11fdd..2baaa96 100644 --- a/include/rtl8703b_led.h +++ b/include/rtl8703b_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_LED_H__ #define __RTL8703B_LED_H__ diff --git a/include/rtl8703b_recv.h b/include/rtl8703b_recv.h index 4c82652..e796e6e 100644 --- a/include/rtl8703b_recv.h +++ b/include/rtl8703b_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_RECV_H__ #define __RTL8703B_RECV_H__ diff --git a/include/rtl8703b_rf.h b/include/rtl8703b_rf.h index 0d3d0aa..14dde98 100644 --- a/include/rtl8703b_rf.h +++ b/include/rtl8703b_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_RF_H__ #define __RTL8703B_RF_H__ diff --git a/include/rtl8703b_spec.h b/include/rtl8703b_spec.h index 9f9491e..633b23b 100644 --- a/include/rtl8703b_spec.h +++ b/include/rtl8703b_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_SPEC_H__ #define __RTL8703B_SPEC_H__ @@ -393,7 +389,7 @@ /* ---------------------------------------------------------------------------- * 8703B REG_CCK_CHECK (offset 0x454) * ---------------------------------------------------------------------------- */ -#define BIT_BCN_PORT_SEL BIT5 +#define BIT_BCN_PORT_SEL BIT(5) #ifdef CONFIG_RF_POWER_TRIM @@ -410,51 +406,51 @@ * ---------------------------------------------------------------------------- */ #define IMR_DISABLED_8703B 0 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ -#define IMR_TIMER2_8703B BIT31 /* Timeout interrupt 2 */ -#define IMR_TIMER1_8703B BIT30 /* Timeout interrupt 1 */ -#define IMR_PSTIMEOUT_8703B BIT29 /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_8703B BIT28 /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_8703B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TXBCN0ERR_8703B BIT26 /* Transmit Beacon0 Error */ -#define IMR_TXBCN0OK_8703B BIT25 /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_8703B BIT24 /* TSF Timer BIT32 toggle indication interrupt */ -#define IMR_BCNDMAINT0_8703B BIT20 /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_8703B BIT16 /* Beacon Queue DMA OK0 */ -#define IMR_HSISR_IND_ON_INT_8703B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_8703B BIT14 /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_8703B BIT12 /* CTWidnow End or ATIM Window End */ -#define IMR_C2HCMD_8703B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_8703B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_8703B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_8703B BIT7 /* High Queue DMA OK */ -#define IMR_MGNTDOK_8703B BIT6 /* Management Queue DMA OK */ -#define IMR_BKDOK_8703B BIT5 /* AC_BK DMA OK */ -#define IMR_BEDOK_8703B BIT4 /* AC_BE DMA OK */ -#define IMR_VIDOK_8703B BIT3 /* AC_VI DMA OK */ -#define IMR_VODOK_8703B BIT2 /* AC_VO DMA OK */ -#define IMR_RDU_8703B BIT1 /* Rx Descriptor Unavailable */ -#define IMR_ROK_8703B BIT0 /* Receive DMA OK */ +#define IMR_TIMER2_8703B BIT(31) /* Timeout interrupt 2 */ +#define IMR_TIMER1_8703B BIT(30) /* Timeout interrupt 1 */ +#define IMR_PSTIMEOUT_8703B BIT(29) /* Power Save Time Out Interrupt */ +#define IMR_GTINT4_8703B BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ +#define IMR_GTINT3_8703B BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ +#define IMR_TXBCN0ERR_8703B BIT(26) /* Transmit Beacon0 Error */ +#define IMR_TXBCN0OK_8703B BIT(25) /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_8703B BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ +#define IMR_BCNDMAINT0_8703B BIT(20) /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_8703B BIT(16) /* Beacon Queue DMA OK0 */ +#define IMR_HSISR_IND_ON_INT_8703B BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ +#define IMR_BCNDMAINT_E_8703B BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ +#define IMR_ATIMEND_8703B BIT(12) /* CTWidnow End or ATIM Window End */ +#define IMR_C2HCMD_8703B BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ +#define IMR_CPWM2_8703B BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_CPWM_8703B BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_HIGHDOK_8703B BIT(7) /* High Queue DMA OK */ +#define IMR_MGNTDOK_8703B BIT(6) /* Management Queue DMA OK */ +#define IMR_BKDOK_8703B BIT(5) /* AC_BK DMA OK */ +#define IMR_BEDOK_8703B BIT(4) /* AC_BE DMA OK */ +#define IMR_VIDOK_8703B BIT(3) /* AC_VI DMA OK */ +#define IMR_VODOK_8703B BIT(2) /* AC_VO DMA OK */ +#define IMR_RDU_8703B BIT(1) /* Rx Descriptor Unavailable */ +#define IMR_ROK_8703B BIT(0) /* Receive DMA OK */ /* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_8703B BIT27 /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_8703B BIT26 /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_8703B BIT25 /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_8703B BIT24 /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_8703B BIT23 /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_8703B BIT22 /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_8703B BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8703B BIT20 /* Beacon Queue DMA OK Interrup 7 */ -#define IMR_BCNDOK6_8703B BIT19 /* Beacon Queue DMA OK Interrup 6 */ -#define IMR_BCNDOK5_8703B BIT18 /* Beacon Queue DMA OK Interrup 5 */ -#define IMR_BCNDOK4_8703B BIT17 /* Beacon Queue DMA OK Interrup 4 */ -#define IMR_BCNDOK3_8703B BIT16 /* Beacon Queue DMA OK Interrup 3 */ -#define IMR_BCNDOK2_8703B BIT15 /* Beacon Queue DMA OK Interrup 2 */ -#define IMR_BCNDOK1_8703B BIT14 /* Beacon Queue DMA OK Interrup 1 */ -#define IMR_ATIMEND_E_8703B BIT13 /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_8703B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_8703B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_8703B BIT9 /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_8703B BIT8 /* Receive FIFO Overflow */ +#define IMR_BCNDMAINT7_8703B BIT(27) /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_8703B BIT(26) /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_8703B BIT(25) /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_8703B BIT(24) /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_8703B BIT(23) /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_8703B BIT(22) /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_8703B BIT(21) /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDOK7_8703B BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ +#define IMR_BCNDOK6_8703B BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ +#define IMR_BCNDOK5_8703B BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ +#define IMR_BCNDOK4_8703B BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ +#define IMR_BCNDOK3_8703B BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ +#define IMR_BCNDOK2_8703B BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ +#define IMR_BCNDOK1_8703B BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ +#define IMR_ATIMEND_E_8703B BIT(13) /* ATIM Window End Extension for Win7 */ +#define IMR_TXERR_8703B BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ +#define IMR_RXERR_8703B BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ +#define IMR_TXFOVW_8703B BIT(9) /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_8703B BIT(8) /* Receive FIFO Overflow */ #ifdef CONFIG_PCI_HCI /* #define IMR_RX_MASK (IMR_ROK_8703B|IMR_RDU_8703B|IMR_RXFOVW_8703B) */ @@ -465,16 +461,4 @@ #define RT_AC_INT_MASKS (IMR_VIDOK_8703B | IMR_VODOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B) #endif -/* ******************************************************** - * General definitions - * ******************************************************** */ - -#define MACID_NUM_8703B 16 -#define SEC_CAM_ENT_NUM_8703B 16 -#define HW_PORT_NUM_8703B 2 -#define NSS_NUM_8703B 1 -#define BAND_CAP_8703B (BAND_CAP_2G) -#define BW_CAP_8703B (BW_CAP_20M | BW_CAP_40M) -#define PROTO_CAP_8703B (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N) - #endif /* __RTL8703B_SPEC_H__ */ diff --git a/include/rtl8703b_sreset.h b/include/rtl8703b_sreset.h index fbed1fb..5fe53cf 100644 --- a/include/rtl8703b_sreset.h +++ b/include/rtl8703b_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8703B_SRESET_H_ #define _RTL8703B_SRESET_H_ diff --git a/include/rtl8703b_xmit.h b/include/rtl8703b_xmit.h index c44609c..4aad2cb 100644 --- a/include/rtl8703b_xmit.h +++ b/include/rtl8703b_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_XMIT_H__ #define __RTL8703B_XMIT_H__ diff --git a/include/rtl8723b_cmd.h b/include/rtl8723b_cmd.h index 59dc564..995d016 100644 --- a/include/rtl8723b_cmd.h +++ b/include/rtl8723b_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_CMD_H__ #define __RTL8723B_CMD_H__ @@ -183,11 +178,10 @@ enum h2c_cmd_8723B { void rtl8723b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8723b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); void rtl8723b_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8723b_Add_RateATid(PADAPTER pAdapter, u64 rate_bitmap, u8 *arg, u8 rssi_level); void rtl8723b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); /* s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ void rtl8723b_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8723b_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask); +void rtl8723b_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); void rtl8723b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); void rtl8723b_download_rsvd_page(PADAPTER padapter, u8 mstatus); #ifdef CONFIG_BT_COEXIST diff --git a/include/rtl8723b_dm.h b/include/rtl8723b_dm.h index a3bb7df..a7ab603 100644 --- a/include/rtl8723b_dm.h +++ b/include/rtl8723b_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_DM_H__ #define __RTL8723B_DM_H__ /* ************************************************************ diff --git a/include/rtl8723b_hal.h b/include/rtl8723b_hal.h index e262129..ecb6f25 100644 --- a/include/rtl8723b_hal.h +++ b/include/rtl8723b_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_HAL_H__ #define __RTL8723B_HAL_H__ @@ -36,35 +31,6 @@ #include "rtl8723b_sreset.h" #endif - -/* --------------------------------------------------------------------- - * RTL8723B From file - * --------------------------------------------------------------------- */ -#define RTL8723B_FW_IMG "rtl8723b/FW_NIC.bin" -#define RTL8723B_FW_WW_IMG "rtl8723b/FW_WoWLAN.bin" -#define RTL8723B_PHY_REG "rtl8723b/PHY_REG.txt" -#define RTL8723B_PHY_RADIO_A "rtl8723b/RadioA.txt" -#define RTL8723B_PHY_RADIO_B "rtl8723b/RadioB.txt" -#define RTL8723B_TXPWR_TRACK "rtl8723b/TxPowerTrack.txt" -#define RTL8723B_AGC_TAB "rtl8723b/AGC_TAB.txt" -#define RTL8723B_PHY_MACREG "rtl8723b/MAC_REG.txt" -#define RTL8723B_PHY_REG_PG "rtl8723b/PHY_REG_PG.txt" -#define RTL8723B_PHY_REG_MP "rtl8723b/PHY_REG_MP.txt" -#define RTL8723B_TXPWR_LMT "rtl8723b/TXPWR_LMT.txt" - -/* --------------------------------------------------------------------- - * RTL8723B From header - * --------------------------------------------------------------------- */ - -#if MP_DRIVER == 1 - #define Rtl8723B_FwBTImgArray Rtl8723BFwBTImgArray - #define Rtl8723B_FwBTImgArrayLength Rtl8723BFwBTImgArrayLength - - #define Rtl8723B_PHY_REG_Array_MP Rtl8723B_PHYREG_Array_MP - #define Rtl8723B_PHY_REG_Array_MPLength Rtl8723B_PHYREG_Array_MPLength -#endif - - #define FW_8723B_SIZE 0x8000 #define FW_8723B_START_ADDRESS 0x1000 #define FW_8723B_END_ADDRESS 0x1FFF /* 0x5FFF */ @@ -124,7 +90,7 @@ typedef struct _RT_8723B_FIRMWARE_HDR { #define RX_DMA_SIZE_8723B 0x4000 /* 16K(RX) */ #ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_NUM) /* 16 entries, for each is 24 bytes*/ + #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ #else #define RESV_FMWF 0 #endif @@ -154,9 +120,11 @@ typedef struct _RT_8723B_FIRMWARE_HDR { #endif /* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, PNO: 6 */ + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6 + * NS offload: 2 NDP info: 1 + */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8723B 0x07 + #define WOWLAN_PAGE_NUM_8723B 0x0b #else #define WOWLAN_PAGE_NUM_8723B 0x00 #endif @@ -216,12 +184,6 @@ typedef struct _RT_8723B_FIRMWARE_HDR { #define EFUSE_PROTECT_BYTES_BANK 16 -typedef struct _C2H_EVT_HDR { - u8 CmdID; - u8 CmdLen; - u8 CmdSeq; -} __attribute__((__packed__)) C2H_EVT_HDR, *PC2H_EVT_HDR; - typedef enum tag_Package_Definition { PACKAGE_DEFAULT, PACKAGE_QFN68, @@ -264,18 +226,10 @@ VOID Hal_EfuseParsePackageType_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN Auto VOID Hal_EfuseParseVoltage_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); VOID Hal_EfuseParseBoardType_8723B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -#ifdef CONFIG_C2H_PACKET_EN - void rtl8723b_c2h_packet_handler(PADAPTER padapter, u8 *pbuf, u16 length); -#endif - - void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8723b(_adapter *adapter); void SetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val); -#ifdef CONFIG_C2H_PACKET_EN - void SetHwRegWithBuf8723B(PADAPTER padapter, u8 variable, u8 *pbuf, int len); -#endif /* CONFIG_C2H_PACKET_EN */ u8 SetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); @@ -301,12 +255,11 @@ void rtl8723b_stop_thread(_adapter *padapter); #ifdef CONFIG_GPIO_WAKEUP void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); #endif - +#ifdef CONFIG_MP_INCLUDED int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); - +#endif void CCX_FwC2HTxRpt_8723b(PADAPTER padapter, u8 *pdata, u8 len); -s32 c2h_id_filter_ccx_8723b(u8 *buf); -s32 c2h_handler_8723b(PADAPTER padapter, u8 *pC2hEvent); + u8 MRateToHwRate8723B(u8 rate); u8 HwRateToMRate8723B(u8 rate); diff --git a/include/rtl8723b_led.h b/include/rtl8723b_led.h index 0a7b2c9..24c5124 100644 --- a/include/rtl8723b_led.h +++ b/include/rtl8723b_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_LED_H__ #define __RTL8723B_LED_H__ diff --git a/include/rtl8723b_recv.h b/include/rtl8723b_recv.h index fd9faef..cf5e18b 100644 --- a/include/rtl8723b_recv.h +++ b/include/rtl8723b_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_RECV_H__ #define __RTL8723B_RECV_H__ diff --git a/include/rtl8723b_rf.h b/include/rtl8723b_rf.h index bf56dde..3494e8c 100644 --- a/include/rtl8723b_rf.h +++ b/include/rtl8723b_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_RF_H__ #define __RTL8723B_RF_H__ diff --git a/include/rtl8723b_spec.h b/include/rtl8723b_spec.h index 85b9d1e..b0fb4aa 100644 --- a/include/rtl8723b_spec.h +++ b/include/rtl8723b_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_SPEC_H__ #define __RTL8723B_SPEC_H__ @@ -198,7 +194,7 @@ /* ---------------------------------------------------------------------------- * 8723B REG_CCK_CHECK (offset 0x454) * ---------------------------------------------------------------------------- */ -#define BIT_BCN_PORT_SEL BIT5 +#define BIT_BCN_PORT_SEL BIT(5) /* ----------------------------------------------------- * @@ -226,51 +222,51 @@ * ---------------------------------------------------------------------------- */ #define IMR_DISABLED_8723B 0 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ -#define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */ -#define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */ -#define IMR_PSTIMEOUT_8723B BIT29 /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TXBCN0ERR_8723B BIT26 /* Transmit Beacon0 Error */ -#define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_8723B BIT24 /* TSF Timer BIT32 toggle indication interrupt */ -#define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_8723B BIT16 /* Beacon Queue DMA OK0 */ -#define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_8723B BIT14 /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */ -#define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */ -#define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */ -#define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */ -#define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */ -#define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */ -#define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */ -#define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */ -#define IMR_ROK_8723B BIT0 /* Receive DMA OK */ +#define IMR_TIMER2_8723B BIT(31) /* Timeout interrupt 2 */ +#define IMR_TIMER1_8723B BIT(30) /* Timeout interrupt 1 */ +#define IMR_PSTIMEOUT_8723B BIT(29) /* Power Save Time Out Interrupt */ +#define IMR_GTINT4_8723B BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ +#define IMR_GTINT3_8723B BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ +#define IMR_TXBCN0ERR_8723B BIT(26) /* Transmit Beacon0 Error */ +#define IMR_TXBCN0OK_8723B BIT(25) /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_8723B BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */ +#define IMR_BCNDMAINT0_8723B BIT(20) /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_8723B BIT(16) /* Beacon Queue DMA OK0 */ +#define IMR_HSISR_IND_ON_INT_8723B BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ +#define IMR_BCNDMAINT_E_8723B BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ +#define IMR_ATIMEND_8723B BIT(12) /* CTWidnow End or ATIM Window End */ +#define IMR_C2HCMD_8723B BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ +#define IMR_CPWM2_8723B BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_CPWM_8723B BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_HIGHDOK_8723B BIT(7) /* High Queue DMA OK */ +#define IMR_MGNTDOK_8723B BIT(6) /* Management Queue DMA OK */ +#define IMR_BKDOK_8723B BIT(5) /* AC_BK DMA OK */ +#define IMR_BEDOK_8723B BIT(4) /* AC_BE DMA OK */ +#define IMR_VIDOK_8723B BIT(3) /* AC_VI DMA OK */ +#define IMR_VODOK_8723B BIT(2) /* AC_VO DMA OK */ +#define IMR_RDU_8723B BIT(1) /* Rx Descriptor Unavailable */ +#define IMR_ROK_8723B BIT(0) /* Receive DMA OK */ /* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_8723B BIT26 /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_8723B BIT24 /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_8723B BIT23 /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_8723B BIT22 /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_8723B BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrup 7 */ -#define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrup 6 */ -#define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrup 5 */ -#define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrup 4 */ -#define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrup 3 */ -#define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrup 2 */ -#define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrup 1 */ -#define IMR_ATIMEND_E_8723B BIT13 /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */ +#define IMR_BCNDMAINT7_8723B BIT(27) /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_8723B BIT(26) /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_8723B BIT(25) /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_8723B BIT(24) /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_8723B BIT(23) /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_8723B BIT(22) /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_8723B BIT(21) /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDOK7_8723B BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ +#define IMR_BCNDOK6_8723B BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ +#define IMR_BCNDOK5_8723B BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ +#define IMR_BCNDOK4_8723B BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ +#define IMR_BCNDOK3_8723B BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ +#define IMR_BCNDOK2_8723B BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ +#define IMR_BCNDOK1_8723B BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ +#define IMR_ATIMEND_E_8723B BIT(13) /* ATIM Window End Extension for Win7 */ +#define IMR_TXERR_8723B BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ +#define IMR_RXERR_8723B BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ +#define IMR_TXFOVW_8723B BIT(9) /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_8723B BIT(8) /* Receive FIFO Overflow */ #ifdef CONFIG_PCI_HCI /* #define IMR_RX_MASK (IMR_ROK_8723B|IMR_RDU_8723B|IMR_RXFOVW_8723B) */ @@ -281,16 +277,4 @@ #define RT_AC_INT_MASKS (IMR_VIDOK_8723B | IMR_VODOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B) #endif -/* ******************************************************** - * General definitions - * ******************************************************** */ - -#define MACID_NUM_8723B 128 -#define SEC_CAM_ENT_NUM_8723B 64 -#define HW_PORT_NUM_8723B 2 -#define NSS_NUM_8723B 1 -#define BAND_CAP_8723B (BAND_CAP_2G) -#define BW_CAP_8723B (BW_CAP_20M | BW_CAP_40M) -#define PROTO_CAP_8723B (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N) - #endif /* __RTL8723B_SPEC_H__ */ diff --git a/include/rtl8723b_sreset.h b/include/rtl8723b_sreset.h index 8067359..c97f264 100644 --- a/include/rtl8723b_sreset.h +++ b/include/rtl8723b_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8723B_SRESET_H_ #define _RTL8723B_SRESET_H_ diff --git a/include/rtl8723b_xmit.h b/include/rtl8723b_xmit.h index 7cc33e1..199e7ef 100644 --- a/include/rtl8723b_xmit.h +++ b/include/rtl8723b_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_XMIT_H__ #define __RTL8723B_XMIT_H__ diff --git a/include/rtl8723d_cmd.h b/include/rtl8723d_cmd.h index 50afb72..5cabd19 100644 --- a/include/rtl8723d_cmd.h +++ b/include/rtl8723d_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_CMD_H__ #define __RTL8723D_CMD_H__ @@ -182,11 +177,10 @@ enum h2c_cmd_8723D { void rtl8723d_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8723d_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); void rtl8723d_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8723d_Add_RateATid(PADAPTER pAdapter, u64 rate_bitmap, u8 *arg, u8 rssi_level); void rtl8723d_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); /* s32 rtl8723d_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ void rtl8723d_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8723d_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask); +void rtl8723d_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); void rtl8723d_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); void rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus); #ifdef CONFIG_BT_COEXIST diff --git a/include/rtl8723d_dm.h b/include/rtl8723d_dm.h index bae086d..c2bdac3 100644 --- a/include/rtl8723d_dm.h +++ b/include/rtl8723d_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_DM_H__ #define __RTL8723D_DM_H__ /* ************************************************************ diff --git a/include/rtl8723d_hal.h b/include/rtl8723d_hal.h index e9d8097..139c60c 100644 --- a/include/rtl8723d_hal.h +++ b/include/rtl8723d_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_HAL_H__ #define __RTL8723D_HAL_H__ @@ -39,35 +34,6 @@ #include "rtl8723d_lps_poff.h" #endif - -/* --------------------------------------------------------------------- - * RTL8723D From file - * --------------------------------------------------------------------- */ -#define RTL8723D_FW_IMG "rtl8723d/FW_NIC.bin" -#define RTL8723D_FW_WW_IMG "rtl8723d/FW_WoWLAN.bin" -#define RTL8723D_PHY_REG "rtl8723d/PHY_REG.txt" -#define RTL8723D_PHY_RADIO_A "rtl8723d/RadioA.txt" -#define RTL8723D_PHY_RADIO_B "rtl8723d/RadioB.txt" -#define RTL8723D_TXPWR_TRACK "rtl8723d/TxPowerTrack.txt" -#define RTL8723D_AGC_TAB "rtl8723d/AGC_TAB.txt" -#define RTL8723D_PHY_MACREG "rtl8723d/MAC_REG.txt" -#define RTL8723D_PHY_REG_PG "rtl8723d/PHY_REG_PG.txt" -#define RTL8723D_PHY_REG_MP "rtl8723d/PHY_REG_MP.txt" -#define RTL8723D_TXPWR_LMT "rtl8723d/TXPWR_LMT.txt" - -/* --------------------------------------------------------------------- - * RTL8723D From header - * --------------------------------------------------------------------- */ - -#if MP_DRIVER == 1 - #define Rtl8723D_FwBTImgArray Rtl8723DFwBTImgArray - #define Rtl8723D_FwBTImgArrayLength Rtl8723DFwBTImgArrayLength - - #define Rtl8723D_PHY_REG_Array_MP Rtl8723D_PHYREG_Array_MP - #define Rtl8723D_PHY_REG_Array_MPLength Rtl8723D_PHYREG_Array_MPLength -#endif - - #define FW_8723D_SIZE 0x8000 #define FW_8723D_START_ADDRESS 0x1000 #define FW_8723D_END_ADDRESS 0x1FFF /* 0x5FFF */ @@ -128,7 +94,7 @@ typedef struct _RT_8723D_FIRMWARE_HDR { #define RX_DMA_SIZE_8723D 0x4000 /* 16K(RX) */ #ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_NUM) /* 16 entries, for each is 24 bytes*/ + #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ #else #define RESV_FMWF 0 #endif @@ -159,9 +125,11 @@ typedef struct _RT_8723D_FIRMWARE_HDR { #endif /* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, PNO: 6 */ + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6 + * NS offload: 2 NDP info: 1 + */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8723D 0x07 + #define WOWLAN_PAGE_NUM_8723D 0x0b #else #define WOWLAN_PAGE_NUM_8723D 0x00 #endif @@ -198,11 +166,11 @@ typedef struct _RT_8723D_FIRMWARE_HDR { #include "HalVerDef.h" #include "hal_com.h" -#define EFUSE_OOB_PROTECT_BYTES 15 +#define EFUSE_OOB_PROTECT_BYTES (96 + 1) #define HAL_EFUSE_MEMORY #define HWSET_MAX_SIZE_8723D 512 -#define EFUSE_REAL_CONTENT_LEN_8723D 256 +#define EFUSE_REAL_CONTENT_LEN_8723D 512 #define EFUSE_MAP_LEN_8723D 512 #define EFUSE_MAX_SECTION_8723D 64 @@ -224,12 +192,6 @@ typedef struct _RT_8723D_FIRMWARE_HDR { #define EFUSE_BT_MAX_SECTION (EFUSE_BT_MAP_LEN / 8) #define EFUSE_PROTECT_BYTES_BANK 16 -typedef struct _C2H_EVT_HDR { - u8 CmdID; - u8 CmdLen; - u8 CmdSeq; -} __attribute__((__packed__)) C2H_EVT_HDR, *PC2H_EVT_HDR; - typedef enum tag_Package_Definition { PACKAGE_DEFAULT, PACKAGE_QFN68, @@ -288,25 +250,15 @@ void Hal_EfuseParseXtal_8723D(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail); void Hal_EfuseParseThermalMeter_8723D(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail); -VOID Hal_EfuseParseMacHidden_8723D(PADAPTER pAdapter, - u8 *hwinfo, BOOLEAN AutoLoadFail); VOID Hal_EfuseParseVoltage_8723D(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); VOID Hal_EfuseParseBoardType_8723D(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -#ifdef CONFIG_C2H_PACKET_EN - void rtl8723d_c2h_packet_handler(PADAPTER padapter, u8 *pbuf, u16 length); -#endif - - void rtl8723d_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8723d(_adapter *adapter); void SetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val); -#ifdef CONFIG_C2H_PACKET_EN - void SetHwRegWithBuf8723D(PADAPTER padapter, u8 variable, u8 *pbuf, int len); -#endif /* CONFIG_C2H_PACKET_EN */ u8 SetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); @@ -334,12 +286,11 @@ void rtl8723d_stop_thread(_adapter *padapter); #ifdef CONFIG_GPIO_WAKEUP void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); #endif - +#ifdef CONFIG_MP_INCLUDED int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); - +#endif void CCX_FwC2HTxRpt_8723d(PADAPTER padapter, u8 *pdata, u8 len); -s32 c2h_id_filter_ccx_8723d(u8 *buf); -s32 c2h_handler_8723d(PADAPTER padapter, u8 *pC2hEvent); + u8 MRateToHwRate8723D(u8 rate); u8 HwRateToMRate8723D(u8 rate); diff --git a/include/rtl8723d_led.h b/include/rtl8723d_led.h index 439ee82..7111dfc 100644 --- a/include/rtl8723d_led.h +++ b/include/rtl8723d_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_LED_H__ #define __RTL8723D_LED_H__ diff --git a/include/rtl8723d_lps_poff.h b/include/rtl8723d_lps_poff.h index c466d40..138a0ca 100644 --- a/include/rtl8723d_lps_poff.h +++ b/include/rtl8723d_lps_poff.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /******************************************** CONST ************************/ #define NUM_OF_REGISTER_BANK 13 diff --git a/include/rtl8723d_recv.h b/include/rtl8723d_recv.h index 84c9b89..0be4309 100644 --- a/include/rtl8723d_recv.h +++ b/include/rtl8723d_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_RECV_H__ #define __RTL8723D_RECV_H__ @@ -56,7 +51,7 @@ #elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - #define MAX_RECVBUF_SZ (10240) + #define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8723D + 1) #endif diff --git a/include/rtl8723d_rf.h b/include/rtl8723d_rf.h index 0aa5813..5101eaf 100644 --- a/include/rtl8723d_rf.h +++ b/include/rtl8723d_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_RF_H__ #define __RTL8723D_RF_H__ diff --git a/include/rtl8723d_spec.h b/include/rtl8723d_spec.h index 1d41056..950242e 100644 --- a/include/rtl8723d_spec.h +++ b/include/rtl8723d_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_SPEC_H__ #define __RTL8723D_SPEC_H__ @@ -442,16 +438,4 @@ #define RT_AC_INT_MASKS (IMR_VIDOK_8723D | IMR_VODOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D) #endif -/* ******************************************************** - * General definitions - * ******************************************************** */ - -#define MACID_NUM_8723D 16 -#define SEC_CAM_ENT_NUM_8723D 32 -#define HW_PORT_NUM_8723D 3 /*port0, port1, port2*/ -#define NSS_NUM_8723D 1 -#define BAND_CAP_8723D (BAND_CAP_2G) -#define BW_CAP_8723D (BW_CAP_20M | BW_CAP_40M) -#define PROTO_CAP_8723D (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N) - #endif /* __RTL8723D_SPEC_H__ */ diff --git a/include/rtl8723d_sreset.h b/include/rtl8723d_sreset.h index aafe7c8..db75dba 100644 --- a/include/rtl8723d_sreset.h +++ b/include/rtl8723d_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8723D_SRESET_H_ #define _RTL8723D_SRESET_H_ diff --git a/include/rtl8723d_xmit.h b/include/rtl8723d_xmit.h index 20f98b0..054bf32 100644 --- a/include/rtl8723d_xmit.h +++ b/include/rtl8723d_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_XMIT_H__ #define __RTL8723D_XMIT_H__ diff --git a/include/rtl8812a_cmd.h b/include/rtl8812a_cmd.h index b784fad..8979470 100644 --- a/include/rtl8812a_cmd.h +++ b/include/rtl8812a_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_CMD_H__ #define __RTL8812A_CMD_H__ @@ -103,40 +98,38 @@ struct H2C_SS_RFOFF_PARAM { #define SET_8812_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) -void Set_RA_LDPC_8812(struct sta_info *psta, BOOLEAN bLDPC); +void set_ra_ldpc_8812(struct sta_info *psta, BOOLEAN bLDPC); /* host message to firmware cmd */ -s32 FillH2CCmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); +s32 fill_h2c_cmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); void rtl8812_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode); void rtl8812_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); u8 rtl8812_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8812_set_raid_cmd(PADAPTER padapter, u32 bitmap, u8 *arg); -void rtl8812_Add_RateATid(PADAPTER padapter, u64 rate_bitmap, u8 *arg, u8 rssi_level); +void rtl8812_set_raid_cmd(PADAPTER padapter, u32 bitmap, u8 *arg, u8 bw); void rtl8812_set_wowlan_cmd(_adapter *padapter, u8 enable); -s32 FillH2CCmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8812(_adapter *padapter, bool wowlan); #ifdef CONFIG_BT_COEXIST - void rtl8812a_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); +void rtl8812a_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); #endif /* CONFIG_BT_COEXIST */ #ifdef CONFIG_P2P_PS - void rtl8812_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); +void rtl8812_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ #ifdef CONFIG_FWLPS_IN_IPS - void rtl8812_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); +void rtl8812_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); #endif void CheckFwRsvdPageContent(PADAPTER padapter); #ifdef CONFIG_TDLS - #ifdef CONFIG_TDLS_CH_SW - void rtl8812_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); - #endif +#ifdef CONFIG_TDLS_CH_SW +void rtl8812_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); +#endif #endif #ifdef CONFIG_TSF_RESET_OFFLOAD - int reset_tsf(PADAPTER Adapter, u8 reset_port); +int reset_tsf(PADAPTER Adapter, u8 reset_port); #endif /* CONFIG_TSF_RESET_OFFLOAD */ /* ------------------------------------ @@ -168,16 +161,6 @@ void CheckFwRsvdPageContent(PADAPTER padapter); #define SET_8812_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+4, 0, 8, __Value) #define SET_8812_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+5, 0, 8, __Value) -int rtl8812_iqk_wait(_adapter *padapter, u32 timeout_ms); -void rtl8812_iqk_done(_adapter *padapter); - -s32 -_C2HContentParsing8812( - IN PADAPTER Adapter, - IN u8 c2hCmdId, - IN u8 c2hCmdLen, - IN u8 *tmpBuf -); -void C2HPacketHandler_8812(PADAPTER Adapter, u8 *Buffer, u8 Length); +s32 c2h_handler_8812a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); #endif/* __RTL8812A_CMD_H__ */ diff --git a/include/rtl8812a_dm.h b/include/rtl8812a_dm.h index fef5824..584f6d3 100644 --- a/include/rtl8812a_dm.h +++ b/include/rtl8812a_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_DM_H__ #define __RTL8812A_DM_H__ diff --git a/include/rtl8812a_hal.h b/include/rtl8812a_hal.h index f52453d..e79a866 100644 --- a/include/rtl8812a_hal.h +++ b/include/rtl8812a_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_HAL_H__ #define __RTL8812A_HAL_H__ @@ -36,41 +31,9 @@ #include "Hal8812PhyReg.h" #include "Hal8812PhyCfg.h" #ifdef DBG_CONFIG_ERROR_DETECT - #include "rtl8812a_sreset.h" +#include "rtl8812a_sreset.h" #endif - -/* --------------------------------------------------------------------- - * RTL8812AU From header - * --------------------------------------------------------------------- */ -#define RTL8812_FW_IMG "rtl8812a/FW_NIC.bin" -#define RTL8812_FW_WW_IMG "rtl8812a/FW_WoWLAN.bin" -#define RTL8812_PHY_REG "rtl8812a/PHY_REG.txt" -#define RTL8812_PHY_RADIO_A "rtl8812a/RadioA.txt" -#define RTL8812_PHY_RADIO_B "rtl8812a/RadioB.txt" -#define RTL8812_TXPWR_TRACK "rtl8812a/TxPowerTrack.txt" -#define RTL8812_AGC_TAB "rtl8812a/AGC_TAB.txt" -#define RTL8812_PHY_MACREG "rtl8812a/MAC_REG.txt" -#define RTL8812_PHY_REG_PG "rtl8812a/PHY_REG_PG.txt" -#define RTL8812_PHY_REG_MP "rtl8812a/PHY_REG_MP.txt" -#define RTL8812_TXPWR_LMT "rtl8812a/TXPWR_LMT.txt" -#define RTL8812_WIFI_ANT_ISOLATION "rtl8812a/wifi_ant_isolation.txt" - -/* --------------------------------------------------------------------- - * RTL8821U From file - * --------------------------------------------------------------------- */ -#define RTL8821_FW_IMG "rtl8821a/FW_NIC.bin" -#define RTL8821_FW_WW_IMG "rtl8821a/FW_WoWLAN.bin" -#define RTL8821_PHY_REG "rtl8821a/PHY_REG.txt" -#define RTL8821_PHY_RADIO_A "rtl8821a/RadioA.txt" -#define RTL8821_PHY_RADIO_B "rtl8821a/RadioB.txt" -#define RTL8821_TXPWR_TRACK "rtl8821a/TxPowerTrack.txt" -#define RTL8821_AGC_TAB "rtl8821a/AGC_TAB.txt" -#define RTL8821_PHY_MACREG "rtl8821a/MAC_REG.txt" -#define RTL8821_PHY_REG_PG "rtl8821a/PHY_REG_PG.txt" -#define RTL8821_PHY_REG_MP "rtl8821a/PHY_REG_MP.txt" -#define RTL8821_TXPWR_LMT "rtl8821a/TXPWR_LMT.txt" - /* --------------------------------------------------------------------- * RTL8812 Power Configuration CMDs for PCIe interface * --------------------------------------------------------------------- */ @@ -160,7 +123,7 @@ typedef struct _RT_FIRMWARE_8812 { #define MAX_RX_DMA_BUFFER_SIZE_8812 0x3E80 /* RX 16K */ #ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_NUM) /* 16 entries, for each is 24 bytes*/ + #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ #else #define RESV_FMWF 0 #endif @@ -175,9 +138,11 @@ typedef struct _RT_FIRMWARE_8812 { #define BCNQ_PAGE_NUM_8812 0x07 /* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, PNO: 6 */ + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, AOAC rpt: 1,PNO: 6 + * NS offload: 1 NDP info: 1 + */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8812 0x05 + #define WOWLAN_PAGE_NUM_8812 0x08 #else #define WOWLAN_PAGE_NUM_8812 0x00 #endif @@ -264,11 +229,11 @@ typedef struct _RT_FIRMWARE_8812 { #define EFUSE_HIDDEN_812AU_VN 3 #if 0 - #define EFUSE_REAL_CONTENT_LEN_JAGUAR 1024 - #define HWSET_MAX_SIZE_JAGUAR 1024 +#define EFUSE_REAL_CONTENT_LEN_JAGUAR 1024 +#define HWSET_MAX_SIZE_JAGUAR 1024 #else - #define EFUSE_REAL_CONTENT_LEN_JAGUAR 512 - #define HWSET_MAX_SIZE_JAGUAR 512 +#define EFUSE_REAL_CONTENT_LEN_JAGUAR 512 +#define HWSET_MAX_SIZE_JAGUAR 512 #endif #define EFUSE_MAX_BANK_8812A 2 @@ -283,13 +248,6 @@ typedef struct _RT_FIRMWARE_8812 { * | 2byte|----8bytes----|1byte|--7bytes--| */ /* 92D */ #define EFUSE_OOB_PROTECT_BYTES_JAGUAR 18 /* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */ #define EFUSE_PROTECT_BYTES_BANK_JAGUAR 16 -/* Added for different registry settings to adjust TxPwr index. added by Roger, 2010.03.09. */ -typedef enum _TX_PWR_PERCENTAGE { - TX_PWR_PERCENTAGE_0 = 0x01, /* 12.5% */ - TX_PWR_PERCENTAGE_1 = 0x02, /* 25% */ - TX_PWR_PERCENTAGE_2 = 0x04, /* 50% */ - TX_PWR_PERCENTAGE_3 = 0x08, /* 100%, default target output power. */ -} TX_PWR_PERCENTAGE; #define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) #define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) @@ -297,16 +255,29 @@ typedef enum _TX_PWR_PERCENTAGE { /* #define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */ /* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */ +#define HAL_EFUSE_MEMORY +/* ******************************************************** + * EFUSE for BT definition + * ******************************************************** */ +#define BANK_NUM 2 +#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512 +#define EFUSE_BT_REAL_CONTENT_LEN \ + (EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM) +#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ +#define EFUSE_BT_MAX_SECTION (EFUSE_BT_MAP_LEN / 8) +#define EFUSE_PROTECT_BYTES_BANK 16 + +#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_BT_REAL_CONTENT_LEN) #ifdef CONFIG_FILE_FWIMG - extern char *rtw_fw_file_path; - #ifdef CONFIG_WOWLAN - extern char *rtw_fw_wow_file_path; - #endif - #ifdef CONFIG_MP_INCLUDED - extern char *rtw_fw_mp_bt_file_path; - #endif +extern char *rtw_fw_file_path; +#ifdef CONFIG_WOWLAN +extern char *rtw_fw_wow_file_path; +#endif +#ifdef CONFIG_MP_INCLUDED +extern char *rtw_fw_mp_bt_file_path; +#endif #endif @@ -337,14 +308,16 @@ void Hal_ReadPAType_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFai void Hal_ReadRFEType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); void Hal_EfuseParseBTCoexistInfo8812A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail); void hal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); +#ifdef CONFIG_MP_INCLUDED int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); +#endif void Hal_ReadRemoteWakeup_8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter); void Hal_EfuseParseKFreeData_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); #ifdef CONFIG_WOWLAN - void Hal_DetectWoWMode(PADAPTER pAdapter); +void Hal_DetectWoWMode(PADAPTER pAdapter); #endif /* CONFIG_WOWLAN */ void _InitBeaconParameters_8812A(PADAPTER padapter); @@ -357,7 +330,6 @@ void SetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval); void GetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval); u8 SetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); -s32 c2h_id_filter_ccx_8812a(u8 *buf); void rtl8812_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8812a(_adapter *adapter); void init_hal_spec_8821a(_adapter *adapter); @@ -369,12 +341,13 @@ void rtl8812_start_thread(PADAPTER padapter); void rtl8812_stop_thread(PADAPTER padapter); #ifdef CONFIG_PCI_HCI - BOOLEAN InterruptRecognized8812AE(PADAPTER Adapter); - VOID UpdateInterruptMask8812AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); +BOOLEAN InterruptRecognized8812AE(PADAPTER Adapter); +VOID UpdateInterruptMask8812AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); +VOID InitTRXDescHwAddress8812AE(PADAPTER Adapter); #endif #ifdef CONFIG_BT_COEXIST - void rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter); +void rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter); #endif VOID diff --git a/include/rtl8812a_led.h b/include/rtl8812a_led.h index 47016c6..c28b391 100644 --- a/include/rtl8812a_led.h +++ b/include/rtl8812a_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_LED_H__ #define __RTL8812A_LED_H__ @@ -25,17 +20,17 @@ * Interface to manipulate LED objects. * ******************************************************************************** */ #ifdef CONFIG_USB_HCI - void rtl8812au_InitSwLeds(PADAPTER padapter); - void rtl8812au_DeInitSwLeds(PADAPTER padapter); +void rtl8812au_InitSwLeds(PADAPTER padapter); +void rtl8812au_DeInitSwLeds(PADAPTER padapter); #endif #ifdef CONFIG_PCI_HCI - void rtl8812ae_InitSwLeds(PADAPTER padapter); - void rtl8812ae_DeInitSwLeds(PADAPTER padapter); +void rtl8812ae_InitSwLeds(PADAPTER padapter); +void rtl8812ae_DeInitSwLeds(PADAPTER padapter); #endif #ifdef CONFIG_SDIO_HCI - void rtl8821as_hw_led_config(PADAPTER adapter); - void rtl8821as_InitSwLeds(PADAPTER padapter); - void rtl8821as_DeInitSwLeds(PADAPTER padapter); +void rtl8821as_hw_led_config(PADAPTER adapter); +void rtl8821as_InitSwLeds(PADAPTER padapter); +void rtl8821as_DeInitSwLeds(PADAPTER padapter); #endif #endif diff --git a/include/rtl8812a_recv.h b/include/rtl8812a_recv.h index 8f9f7ef..bf1d4b6 100644 --- a/include/rtl8812a_recv.h +++ b/include/rtl8812a_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_RECV_H__ #define __RTL8812A_RECV_H__ @@ -116,7 +111,7 @@ #define GET_RX_STATUS_DESC_EOSP_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) #define GET_RX_STATUS_DESC_BSSID_FIT_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) #ifdef CONFIG_USB_RX_AGGREGATION - #define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) +#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) #endif #define GET_RX_STATUS_DESC_PATTERN_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) #define GET_RX_STATUS_DESC_UNICAST_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) @@ -138,19 +133,19 @@ #ifdef CONFIG_SDIO_HCI - s32 InitRecvPriv8821AS(PADAPTER padapter); - void FreeRecvPriv8821AS(PADAPTER padapter); +s32 InitRecvPriv8821AS(PADAPTER padapter); +void FreeRecvPriv8821AS(PADAPTER padapter); #endif /* CONFIG_SDIO_HCI */ #ifdef CONFIG_USB_HCI - void rtl8812au_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); - s32 rtl8812au_init_recv_priv(PADAPTER padapter); - void rtl8812au_free_recv_priv(PADAPTER padapter); +void rtl8812au_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); +s32 rtl8812au_init_recv_priv(PADAPTER padapter); +void rtl8812au_free_recv_priv(PADAPTER padapter); #endif #ifdef CONFIG_PCI_HCI - s32 rtl8812ae_init_recv_priv(PADAPTER padapter); - void rtl8812ae_free_recv_priv(PADAPTER padapter); +s32 rtl8812ae_init_recv_priv(PADAPTER padapter); +void rtl8812ae_free_recv_priv(PADAPTER padapter); #endif void rtl8812_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); diff --git a/include/rtl8812a_rf.h b/include/rtl8812a_rf.h index 9a7175d..1e2c1a0 100644 --- a/include/rtl8812a_rf.h +++ b/include/rtl8812a_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_RF_H__ #define __RTL8812A_RF_H__ diff --git a/include/rtl8812a_spec.h b/include/rtl8812a_spec.h index 4334fa3..3e3927b 100644 --- a/include/rtl8812a_spec.h +++ b/include/rtl8812a_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,266 +11,250 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_SPEC_H__ - #define __RTL8812A_SPEC_H__ - - #include - - - /* ************************************************************ - * 8812 Regsiter offset definition - * ************************************************************ */ - - /* ************************************************************ - * - * ************************************************************ */ - - /* ----------------------------------------------------- - * - * 0x0000h ~ 0x00FFh System Configuration - * - * ----------------------------------------------------- */ - #define REG_SYS_CLKR_8812A 0x0008 - #define REG_AFE_PLL_CTRL_8812A 0x0028 - #define REG_HSIMR_8812 0x0058 - #define REG_HSISR_8812 0x005c - #define REG_GPIO_EXT_CTRL 0x0060 - #define REG_GPIO_STATUS_8812 0x006C - #define REG_SDIO_CTRL_8812 0x0070 - #define REG_OPT_CTRL_8812 0x0074 - #define REG_RF_B_CTRL_8812 0x0076 - #define REG_FW_DRV_MSG_8812 0x0088 - #define REG_HMEBOX_E2_E3_8812 0x008C - #define REG_HIMR0_8812 0x00B0 - #define REG_HISR0_8812 0x00B4 - #define REG_HIMR1_8812 0x00B8 - #define REG_HISR1_8812 0x00BC - #define REG_EFUSE_BURN_GNT_8812 0x00CF - #define REG_SYS_CFG1_8812 0x00FC - - /* ----------------------------------------------------- - * - * 0x0100h ~ 0x01FFh MACTOP General Configuration - * - * ----------------------------------------------------- */ - #define REG_CR_8812A 0x100 - #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) - #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) - #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) - #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN - - #define REG_RSVD3_8812 0x0168 - #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 - #define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 - #define REG_C2HEVT_CMD_LEN_88XX 0x01AE - - #define REG_HMEBOX_EXT0_8812 0x01F0 - #define REG_HMEBOX_EXT1_8812 0x01F4 - #define REG_HMEBOX_EXT2_8812 0x01F8 - #define REG_HMEBOX_EXT3_8812 0x01FC - - /* ----------------------------------------------------- - * - * 0x0200h ~ 0x027Fh TXDMA Configuration - * - * ----------------------------------------------------- */ - #define REG_DWBCN0_CTRL_8812 REG_TDECTRL - #define REG_DWBCN1_CTRL_8812 0x0228 - - /* ----------------------------------------------------- - * - * 0x0280h ~ 0x02FFh RXDMA Configuration - * - * ----------------------------------------------------- */ - #define REG_TDECTRL_8812A 0x0208 - #define REG_RXDMA_CONTROL_8812A 0x0286 /*Control the RX DMA.*/ - #define REG_RXDMA_PRO_8812 0x0290 - #define REG_EARLY_MODE_CONTROL_8812 0x02BC - #define REG_RSVD5_8812 0x02F0 - #define REG_RSVD6_8812 0x02F4 - #define REG_RSVD7_8812 0x02F8 - #define REG_RSVD8_8812 0x02FC - - - /* ----------------------------------------------------- - * - * 0x0300h ~ 0x03FFh PCIe - * - * ----------------------------------------------------- */ - #define REG_PCIE_CTRL_REG_8812A 0x0300 - #define REG_DBI_WDATA_8812 0x0348 /* DBI Write Data */ - #define REG_DBI_RDATA_8812 0x034C /* DBI Read Data */ - #define REG_DBI_ADDR_8812 0x0350 /* DBI Address */ - #define REG_DBI_FLAG_8812 0x0352 /* DBI Read/Write Flag */ - #define REG_MDIO_WDATA_8812 0x0354 /* MDIO for Write PCIE PHY */ - #define REG_MDIO_RDATA_8812 0x0356 /* MDIO for Reads PCIE PHY */ - #define REG_MDIO_CTL_8812 0x0358 /* MDIO for Control */ - #define REG_PCIE_MULTIFET_CTRL_8812 0x036A /* PCIE Multi-Fethc Control */ - - /* ----------------------------------------------------- - * - * 0x0400h ~ 0x047Fh Protocol Configuration - * - * ----------------------------------------------------- */ - #define REG_TXPKT_EMPTY_8812A 0x041A - #define REG_FWHW_TXQ_CTRL_8812A 0x0420 - #define REG_TXBF_CTRL_8812A 0x042C - #define REG_ARFR0_8812 0x0444 - #define REG_ARFR1_8812 0x044C - #define REG_CCK_CHECK_8812 0x0454 - #define REG_AMPDU_MAX_TIME_8812 0x0456 - #define REG_TXPKTBUF_BCNQ_BDNY1_8812 0x0457 - - #define REG_AMPDU_MAX_LENGTH_8812 0x0458 - #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812 0x045D - #define REG_NDPA_OPT_CTRL_8812A 0x045F - #define REG_DATA_SC_8812 0x0483 - #ifdef CONFIG_WOWLAN - #define REG_TXPKTBUF_IV_LOW 0x0484 - #define REG_TXPKTBUF_IV_HIGH 0x0488 - #endif - #define REG_ARFR2_8812 0x048C - #define REG_ARFR3_8812 0x0494 - #define REG_TXRPT_START_OFFSET 0x04AC - #define REG_AMPDU_BURST_MODE_8812 0x04BC - #define REG_HT_SINGLE_AMPDU_8812 0x04C7 - #define REG_MACID_PKT_DROP0_8812 0x04D0 - - /* ----------------------------------------------------- - * - * 0x0500h ~ 0x05FFh EDCA Configuration - * - * ----------------------------------------------------- */ - #define REG_TXPAUSE_8812A 0x0522 - #define REG_CTWND_8812 0x0572 - #define REG_SECONDARY_CCA_CTRL_8812 0x0577 - #define REG_SCH_TXCMD_8812A 0x05F8 - - /* ----------------------------------------------------- - * - * 0x0600h ~ 0x07FFh WMAC Configuration - * - * ----------------------------------------------------- */ - #define REG_MAC_CR_8812 0x0600 - - #define REG_MAC_TX_SM_STATE_8812 0x06B4 - - /* Power */ - #define REG_BFMER0_INFO_8812A 0x06E4 - #define REG_BFMER1_INFO_8812A 0x06EC - #define REG_CSI_RPT_PARAM_BW20_8812A 0x06F4 - #define REG_CSI_RPT_PARAM_BW40_8812A 0x06F8 - #define REG_CSI_RPT_PARAM_BW80_8812A 0x06FC - - /* Hardware Port 2 */ - #define REG_BFMEE_SEL_8812A 0x0714 - #define REG_SND_PTCL_CTRL_8812A 0x0718 - - - /* ----------------------------------------------------- - * - * Redifine register definition for compatibility - * - * ----------------------------------------------------- */ - - /* TODO: use these definition when using REG_xxx naming rule. - * NOTE: DO NOT Remove these definition. Use later. */ - #define ISR_8812 REG_HISR0_8812 - - /* ---------------------------------------------------------------------------- - * 8195 IMR/ISR bits (offset 0xB0, 8bits) - * ---------------------------------------------------------------------------- */ - #define IMR_DISABLED_8812 0 - /* IMR DW0(0x00B0-00B3) Bit 0-31 */ - #define IMR_TIMER2_8812 BIT31 /* Timeout interrupt 2 */ - #define IMR_TIMER1_8812 BIT30 /* Timeout interrupt 1 */ - #define IMR_PSTIMEOUT_8812 BIT29 /* Power Save Time Out Interrupt */ - #define IMR_GTINT4_8812 BIT28 /* When GTIMER4 expires, this bit is set to 1 */ - #define IMR_GTINT3_8812 BIT27 /* When GTIMER3 expires, this bit is set to 1 */ - #define IMR_TXBCN0ERR_8812 BIT26 /* Transmit Beacon0 Error */ - #define IMR_TXBCN0OK_8812 BIT25 /* Transmit Beacon0 OK */ - #define IMR_TSF_BIT32_TOGGLE_8812 BIT24 /* TSF Timer BIT32 toggle indication interrupt */ - #define IMR_BCNDMAINT0_8812 BIT20 /* Beacon DMA Interrupt 0 */ - #define IMR_BCNDERR0_8812 BIT16 /* Beacon Queue DMA OK0 */ - #define IMR_HSISR_IND_ON_INT_8812 BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ - #define IMR_BCNDMAINT_E_8812 BIT14 /* Beacon DMA Interrupt Extension for Win7 */ - #define IMR_ATIMEND_8812 BIT12 /* CTWidnow End or ATIM Window End */ - #define IMR_C2HCMD_8812 BIT10 /* CPU to Host Command INT Status, Write 1 clear */ - #define IMR_CPWM2_8812 BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ - #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ - #define IMR_HIGHDOK_8812 BIT7 /* High Queue DMA OK */ - #define IMR_MGNTDOK_8812 BIT6 /* Management Queue DMA OK */ - #define IMR_BKDOK_8812 BIT5 /* AC_BK DMA OK */ - #define IMR_BEDOK_8812 BIT4 /* AC_BE DMA OK */ - #define IMR_VIDOK_8812 BIT3 /* AC_VI DMA OK */ - #define IMR_VODOK_8812 BIT2 /* AC_VO DMA OK */ - #define IMR_RDU_8812 BIT1 /* Rx Descriptor Unavailable */ - #define IMR_ROK_8812 BIT0 /* Receive DMA OK */ - - /* IMR DW1(0x00B4-00B7) Bit 0-31 */ - #define IMR_BCNDMAINT7_8812 BIT27 /* Beacon DMA Interrupt 7 */ - #define IMR_BCNDMAINT6_8812 BIT26 /* Beacon DMA Interrupt 6 */ - #define IMR_BCNDMAINT5_8812 BIT25 /* Beacon DMA Interrupt 5 */ - #define IMR_BCNDMAINT4_8812 BIT24 /* Beacon DMA Interrupt 4 */ - #define IMR_BCNDMAINT3_8812 BIT23 /* Beacon DMA Interrupt 3 */ - #define IMR_BCNDMAINT2_8812 BIT22 /* Beacon DMA Interrupt 2 */ - #define IMR_BCNDMAINT1_8812 BIT21 /* Beacon DMA Interrupt 1 */ - #define IMR_BCNDOK7_8812 BIT20 /* Beacon Queue DMA OK Interrup 7 */ - #define IMR_BCNDOK6_8812 BIT19 /* Beacon Queue DMA OK Interrup 6 */ - #define IMR_BCNDOK5_8812 BIT18 /* Beacon Queue DMA OK Interrup 5 */ - #define IMR_BCNDOK4_8812 BIT17 /* Beacon Queue DMA OK Interrup 4 */ - #define IMR_BCNDOK3_8812 BIT16 /* Beacon Queue DMA OK Interrup 3 */ - #define IMR_BCNDOK2_8812 BIT15 /* Beacon Queue DMA OK Interrup 2 */ - #define IMR_BCNDOK1_8812 BIT14 /* Beacon Queue DMA OK Interrup 1 */ - #define IMR_ATIMEND_E_8812 BIT13 /* ATIM Window End Extension for Win7 */ - #define IMR_TXERR_8812 BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ - #define IMR_RXERR_8812 BIT10 /* Rx Error Flag INT Status, Write 1 clear */ - #define IMR_TXFOVW_8812 BIT9 /* Transmit FIFO Overflow */ - #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */ - - - #ifdef CONFIG_PCI_HCI - /* #define IMR_RX_MASK (IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812) */ - #define IMR_TX_MASK (IMR_VODOK_8812 | IMR_VIDOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812 | IMR_MGNTDOK_8812 | IMR_HIGHDOK_8812) - - #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812) - - #define RT_AC_INT_MASKS (IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812) - #endif - - - /* **************************************************************************** - * Regsiter Bit and Content definition - * **************************************************************************** */ - - /* 2 ACMHWCTRL 0x05C0 */ - #define AcmHw_HwEn_8812 BIT(0) - #define AcmHw_VoqEn_8812 BIT(1) - #define AcmHw_ViqEn_8812 BIT(2) - #define AcmHw_BeqEn_8812 BIT(3) - #define AcmHw_VoqStatus_8812 BIT(5) - #define AcmHw_ViqStatus_8812 BIT(6) - #define AcmHw_BeqStatus_8812 BIT(7) - - /* ******************************************************** - * General definitions - * ******************************************************** */ - - #define MACID_NUM_8812A 128 - #define SEC_CAM_ENT_NUM_8812A 64 - #define HW_PORT_NUM_8812A 2 - #define NSS_NUM_8812A 2 - #define BAND_CAP_8812A (BAND_CAP_2G | BAND_CAP_5G) - #define BW_CAP_8812A (BW_CAP_20M | BW_CAP_40M | BW_CAP_80M) - #define PROTO_CAP_8812A (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | PROTO_CAP_11AC) +#define __RTL8812A_SPEC_H__ + +#include + + +/* ************************************************************ +* 8812 Regsiter offset definition +* ************************************************************ */ + +/* ************************************************************ +* +* ************************************************************ */ + +/* ----------------------------------------------------- +* +* 0x0000h ~ 0x00FFh System Configuration +* +* ----------------------------------------------------- */ +#define REG_SYS_CLKR_8812A 0x0008 +#define REG_AFE_PLL_CTRL_8812A 0x0028 +#define REG_HSIMR_8812 0x0058 +#define REG_HSISR_8812 0x005c +#define REG_GPIO_EXT_CTRL 0x0060 +#define REG_GPIO_STATUS_8812 0x006C +#define REG_SDIO_CTRL_8812 0x0070 +#define REG_OPT_CTRL_8812 0x0074 +#define REG_RF_B_CTRL_8812 0x0076 +#define REG_FW_DRV_MSG_8812 0x0088 +#define REG_HMEBOX_E2_E3_8812 0x008C +#define REG_HIMR0_8812 0x00B0 +#define REG_HISR0_8812 0x00B4 +#define REG_HIMR1_8812 0x00B8 +#define REG_HISR1_8812 0x00BC +#define REG_EFUSE_BURN_GNT_8812 0x00CF +#define REG_SYS_CFG1_8812 0x00FC + +/* ----------------------------------------------------- +* +* 0x0100h ~ 0x01FFh MACTOP General Configuration +* +* ----------------------------------------------------- */ +#define REG_CR_8812A 0x100 +#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) +#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) +#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) +#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN + +#define REG_RSVD3_8812 0x0168 +#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 +#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 +#define REG_C2HEVT_CMD_LEN_88XX 0x01AE + +#define REG_HMEBOX_EXT0_8812 0x01F0 +#define REG_HMEBOX_EXT1_8812 0x01F4 +#define REG_HMEBOX_EXT2_8812 0x01F8 +#define REG_HMEBOX_EXT3_8812 0x01FC + +/* ----------------------------------------------------- +* +* 0x0200h ~ 0x027Fh TXDMA Configuration +* +* ----------------------------------------------------- */ +#define REG_DWBCN0_CTRL_8812 REG_TDECTRL +#define REG_DWBCN1_CTRL_8812 0x0228 + +/* ----------------------------------------------------- +* +* 0x0280h ~ 0x02FFh RXDMA Configuration +* +* ----------------------------------------------------- */ +#define REG_TDECTRL_8812A 0x0208 +#define REG_RXDMA_CONTROL_8812A 0x0286 /*Control the RX DMA.*/ +#define REG_RXDMA_PRO_8812 0x0290 +#define REG_EARLY_MODE_CONTROL_8812 0x02BC +#define REG_RSVD5_8812 0x02F0 +#define REG_RSVD6_8812 0x02F4 +#define REG_RSVD7_8812 0x02F8 +#define REG_RSVD8_8812 0x02FC + + +/* ----------------------------------------------------- +* +* 0x0300h ~ 0x03FFh PCIe +* +* ----------------------------------------------------- */ +#define REG_PCIE_CTRL_REG_8812A 0x0300 +#define REG_DBI_WDATA_8812 0x0348 /* DBI Write Data */ +#define REG_DBI_RDATA_8812 0x034C /* DBI Read Data */ +#define REG_DBI_ADDR_8812 0x0350 /* DBI Address */ +#define REG_DBI_FLAG_8812 0x0352 /* DBI Read/Write Flag */ +#define REG_MDIO_WDATA_8812 0x0354 /* MDIO for Write PCIE PHY */ +#define REG_MDIO_RDATA_8812 0x0356 /* MDIO for Reads PCIE PHY */ +#define REG_MDIO_CTL_8812 0x0358 /* MDIO for Control */ +#define REG_PCIE_MULTIFET_CTRL_8812 0x036A /* PCIE Multi-Fethc Control */ + +/* ----------------------------------------------------- +* +* 0x0400h ~ 0x047Fh Protocol Configuration +* +* ----------------------------------------------------- */ +#define REG_TXPKT_EMPTY_8812A 0x041A +#define REG_FWHW_TXQ_CTRL_8812A 0x0420 +#define REG_TXBF_CTRL_8812A 0x042C +#define REG_ARFR0_8812 0x0444 +#define REG_ARFR1_8812 0x044C +#define REG_CCK_CHECK_8812 0x0454 +#define REG_AMPDU_MAX_TIME_8812 0x0456 +#define REG_TXPKTBUF_BCNQ_BDNY1_8812 0x0457 + +#define REG_AMPDU_MAX_LENGTH_8812 0x0458 +#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812 0x045D +#define REG_NDPA_OPT_CTRL_8812A 0x045F +#define REG_DATA_SC_8812 0x0483 +#ifdef CONFIG_WOWLAN +#define REG_TXPKTBUF_IV_LOW 0x0484 +#define REG_TXPKTBUF_IV_HIGH 0x0488 +#endif +#define REG_ARFR2_8812 0x048C +#define REG_ARFR3_8812 0x0494 +#define REG_TXRPT_START_OFFSET 0x04AC +#define REG_AMPDU_BURST_MODE_8812 0x04BC +#define REG_HT_SINGLE_AMPDU_8812 0x04C7 +#define REG_MACID_PKT_DROP0_8812 0x04D0 + +/* ----------------------------------------------------- +* +* 0x0500h ~ 0x05FFh EDCA Configuration +* +* ----------------------------------------------------- */ +#define REG_TXPAUSE_8812A 0x0522 +#define REG_CTWND_8812 0x0572 +#define REG_SECONDARY_CCA_CTRL_8812 0x0577 +#define REG_SCH_TXCMD_8812A 0x05F8 + +/* ----------------------------------------------------- +* +* 0x0600h ~ 0x07FFh WMAC Configuration +* +* ----------------------------------------------------- */ +#define REG_MAC_CR_8812 0x0600 + +#define REG_MAC_TX_SM_STATE_8812 0x06B4 + +/* Power */ +#define REG_BFMER0_INFO_8812A 0x06E4 +#define REG_BFMER1_INFO_8812A 0x06EC +#define REG_CSI_RPT_PARAM_BW20_8812A 0x06F4 +#define REG_CSI_RPT_PARAM_BW40_8812A 0x06F8 +#define REG_CSI_RPT_PARAM_BW80_8812A 0x06FC + +/* Hardware Port 2 */ +#define REG_BFMEE_SEL_8812A 0x0714 +#define REG_SND_PTCL_CTRL_8812A 0x0718 + + +/* ----------------------------------------------------- +* +* Redifine register definition for compatibility +* +* ----------------------------------------------------- */ + +/* TODO: use these definition when using REG_xxx naming rule. +* NOTE: DO NOT Remove these definition. Use later. */ +#define ISR_8812 REG_HISR0_8812 + +/* ---------------------------------------------------------------------------- +* 8195 IMR/ISR bits (offset 0xB0, 8bits) +* ---------------------------------------------------------------------------- */ +#define IMR_DISABLED_8812 0 +/* IMR DW0(0x00B0-00B3) Bit 0-31 */ +#define IMR_TIMER2_8812 BIT31 /* Timeout interrupt 2 */ +#define IMR_TIMER1_8812 BIT30 /* Timeout interrupt 1 */ +#define IMR_PSTIMEOUT_8812 BIT29 /* Power Save Time Out Interrupt */ +#define IMR_GTINT4_8812 BIT28 /* When GTIMER4 expires, this bit is set to 1 */ +#define IMR_GTINT3_8812 BIT27 /* When GTIMER3 expires, this bit is set to 1 */ +#define IMR_TXBCN0ERR_8812 BIT26 /* Transmit Beacon0 Error */ +#define IMR_TXBCN0OK_8812 BIT25 /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_8812 BIT24 /* TSF Timer BIT32 toggle indication interrupt */ +#define IMR_BCNDMAINT0_8812 BIT20 /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_8812 BIT16 /* Beacon Queue DMA OK0 */ +#define IMR_HSISR_IND_ON_INT_8812 BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ +#define IMR_BCNDMAINT_E_8812 BIT14 /* Beacon DMA Interrupt Extension for Win7 */ +#define IMR_ATIMEND_8812 BIT12 /* CTWidnow End or ATIM Window End */ +#define IMR_C2HCMD_8812 BIT10 /* CPU to Host Command INT Status, Write 1 clear */ +#define IMR_CPWM2_8812 BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_HIGHDOK_8812 BIT7 /* High Queue DMA OK */ +#define IMR_MGNTDOK_8812 BIT6 /* Management Queue DMA OK */ +#define IMR_BKDOK_8812 BIT5 /* AC_BK DMA OK */ +#define IMR_BEDOK_8812 BIT4 /* AC_BE DMA OK */ +#define IMR_VIDOK_8812 BIT3 /* AC_VI DMA OK */ +#define IMR_VODOK_8812 BIT2 /* AC_VO DMA OK */ +#define IMR_RDU_8812 BIT1 /* Rx Descriptor Unavailable */ +#define IMR_ROK_8812 BIT0 /* Receive DMA OK */ + +/* IMR DW1(0x00B4-00B7) Bit 0-31 */ +#define IMR_BCNDMAINT7_8812 BIT27 /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_8812 BIT26 /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_8812 BIT25 /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_8812 BIT24 /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_8812 BIT23 /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_8812 BIT22 /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_8812 BIT21 /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDOK7_8812 BIT20 /* Beacon Queue DMA OK Interrup 7 */ +#define IMR_BCNDOK6_8812 BIT19 /* Beacon Queue DMA OK Interrup 6 */ +#define IMR_BCNDOK5_8812 BIT18 /* Beacon Queue DMA OK Interrup 5 */ +#define IMR_BCNDOK4_8812 BIT17 /* Beacon Queue DMA OK Interrup 4 */ +#define IMR_BCNDOK3_8812 BIT16 /* Beacon Queue DMA OK Interrup 3 */ +#define IMR_BCNDOK2_8812 BIT15 /* Beacon Queue DMA OK Interrup 2 */ +#define IMR_BCNDOK1_8812 BIT14 /* Beacon Queue DMA OK Interrup 1 */ +#define IMR_ATIMEND_E_8812 BIT13 /* ATIM Window End Extension for Win7 */ +#define IMR_TXERR_8812 BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ +#define IMR_RXERR_8812 BIT10 /* Rx Error Flag INT Status, Write 1 clear */ +#define IMR_TXFOVW_8812 BIT9 /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */ + + +#ifdef CONFIG_PCI_HCI +/* #define IMR_RX_MASK (IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812) */ +#define IMR_TX_MASK (IMR_VODOK_8812 | IMR_VIDOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812 | IMR_MGNTDOK_8812 | IMR_HIGHDOK_8812) + +#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812) + +#define RT_AC_INT_MASKS (IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812) +#endif + + +/* **************************************************************************** +* Regsiter Bit and Content definition +* **************************************************************************** */ + +/* 2 ACMHWCTRL 0x05C0 */ +#define AcmHw_HwEn_8812 BIT(0) +#define AcmHw_VoqEn_8812 BIT(1) +#define AcmHw_ViqEn_8812 BIT(2) +#define AcmHw_BeqEn_8812 BIT(3) +#define AcmHw_VoqStatus_8812 BIT(5) +#define AcmHw_ViqStatus_8812 BIT(6) +#define AcmHw_BeqStatus_8812 BIT(7) #endif /* __RTL8812A_SPEC_H__ */ #ifdef CONFIG_RTL8821A - #include "rtl8821a_spec.h" +#include "rtl8821a_spec.h" #endif /* CONFIG_RTL8821A */ diff --git a/include/rtl8812a_sreset.h b/include/rtl8812a_sreset.h index 07f6903..d4bbd58 100644 --- a/include/rtl8812a_sreset.h +++ b/include/rtl8812a_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,19 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL88812A_SRESET_H_ #define _RTL8812A_SRESET_H_ #include #ifdef DBG_CONFIG_ERROR_DETECT - extern void rtl8812_sreset_xmit_status_check(_adapter *padapter); - extern void rtl8812_sreset_linked_status_check(_adapter *padapter); +extern void rtl8812_sreset_xmit_status_check(_adapter *padapter); +extern void rtl8812_sreset_linked_status_check(_adapter *padapter); #endif #endif diff --git a/include/rtl8812a_xmit.h b/include/rtl8812a_xmit.h index fbf6eda..0daa43e 100644 --- a/include/rtl8812a_xmit.h +++ b/include/rtl8812a_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_XMIT_H__ #define __RTL8812A_XMIT_H__ @@ -286,7 +281,7 @@ typedef struct txdescriptor_8812 { #define SET_TX_DESC_TX_DESC_CHECKSUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) #define SET_TX_DESC_USB_TXAGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) #ifdef CONFIG_SDIO_HCI - #define SET_TX_DESC_SDIO_TXSEQ_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) +#define SET_TX_DESC_SDIO_TXSEQ_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) #endif /* Dword 8 */ @@ -324,33 +319,38 @@ void rtl8812a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc); void rtl8812a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc); void rtl8812a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc); #if defined(CONFIG_CONCURRENT_MODE) - void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); +void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif #ifdef CONFIG_USB_HCI - s32 rtl8812au_init_xmit_priv(PADAPTER padapter); - void rtl8812au_free_xmit_priv(PADAPTER padapter); - s32 rtl8812au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8812au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8812au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); - void rtl8812au_xmit_tasklet(void *priv); - s32 rtl8812au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); +s32 rtl8812au_init_xmit_priv(PADAPTER padapter); +void rtl8812au_free_xmit_priv(PADAPTER padapter); +s32 rtl8812au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); +s32 rtl8812au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); +s32 rtl8812au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); +void rtl8812au_xmit_tasklet(void *priv); +s32 rtl8812au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); #endif #ifdef CONFIG_PCI_HCI - s32 rtl8812ae_init_xmit_priv(PADAPTER padapter); - void rtl8812ae_free_xmit_priv(PADAPTER padapter); - struct xmit_buf *rtl8812ae_dequeue_xmitbuf(struct rtw_tx_ring *ring); - void rtl8812ae_xmitframe_resume(_adapter *padapter); - s32 rtl8812ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8812ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8812ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - void rtl8812ae_xmit_tasklet(void *priv); +s32 rtl8812ae_init_xmit_priv(PADAPTER padapter); +void rtl8812ae_free_xmit_priv(PADAPTER padapter); +struct xmit_buf *rtl8812ae_dequeue_xmitbuf(struct rtw_tx_ring *ring); +void rtl8812ae_xmitframe_resume(_adapter *padapter); +s32 rtl8812ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); +s32 rtl8812ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); +s32 rtl8812ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +void rtl8812ae_xmit_tasklet(void *priv); + +#ifdef CONFIG_XMIT_THREAD_MODE +s32 rtl8812ae_xmit_buf_handler(_adapter *padapter); +#endif + #endif #ifdef CONFIG_TX_EARLY_MODE - void UpdateEarlyModeInfo8812(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); +void UpdateEarlyModeInfo8812(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); #endif void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, u8 *ptxdesc); @@ -362,5 +362,5 @@ u8 SCMapping_8812(PADAPTER Adapter, struct pkt_attrib *pattrib); #endif /* __RTL8812_XMIT_H__ */ #ifdef CONFIG_RTL8821A - #include "rtl8821a_xmit.h" +#include "rtl8821a_xmit.h" #endif /* CONFIG_RTL8821A */ diff --git a/include/rtl8814a_cmd.h b/include/rtl8814a_cmd.h index 38ce2c2..d17951b 100644 --- a/include/rtl8814a_cmd.h +++ b/include/rtl8814a_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_CMD_H__ #define __RTL8814A_CMD_H__ #include "hal_com_h2c.h" @@ -80,6 +75,30 @@ #define SET_88E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) #define SET_88E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +/* AP_REQ_TXREP_CMD 0x43 */ +#define SET_8814A_H2CCMD_TXREP_PARM_STA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8814A_H2CCMD_TXREP_PARM_STA2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8814A_H2CCMD_TXREP_PARM_RTY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value) + +/* C2H_AP_REQ_TXRPT */ +#define GET_8814A_C2H_TC2H_APREQ_TXRPT_MACID1(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 8) +#define GET_8814A_C2H_TC2H_APREQ_TXRPT_TXOK1(_Header) LE_BITS_TO_2BYTE((_Header + 1), 0, 16) +#define GET_8814A_C2H_TC2H_APREQ_TXRPT_TXFAIL1(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) +#define GET_8814A_C2H_TC2H_APREQ_TXRPT_INIRATE1(_Header) LE_BITS_TO_1BYTE((_Header + 5), 0, 8) +#define GET_8814A_C2H_TC2H_APREQ_TXRPT_MACID2(_Header) LE_BITS_TO_1BYTE((_Header + 6), 0, 8) +#define GET_8814A_C2H_TC2H_APREQ_TXRPT_TXOK2(_Header) LE_BITS_TO_2BYTE((_Header + 7), 0, 16) +#define GET_8814A_C2H_TC2H_APREQ_TXRPT_TXFAIL2(_Header) LE_BITS_TO_2BYTE((_Header + 9), 0, 16) +#define GET_8814A_C2H_TC2H_APREQ_TXRPT_INIRATE2(_Header) LE_BITS_TO_1BYTE((_Header + 11), 0, 8) + +/* C2H_SPC_STAT */ +#define GET_8814A_C2H_SPC_STAT_IDX(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 8) + /* Tip :TYPE_A data3 is msb and data0 is lsb */ +#define GET_8814A_C2H_SPC_STAT_TYPEA_RETRY(_Header) LE_BITS_TO_4BYTE((_Header + 1), 0, 32) +#define GET_8814A_C2H_SPC_STAT_TYPEB_PKT1(_Header) LE_BITS_TO_2BYTE((_Header + 1), 0, 16) +#define GET_8814A_C2H_SPC_STAT_TYPEB_RETRY1(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) +#define GET_8814A_C2H_SPC_STAT_TYPEB_PKT2(_Header) LE_BITS_TO_2BYTE((_Header + 5), 0, 16) +#define GET_8814A_C2H_SPC_STAT_TYPEB_RETRY2(_Header) LE_BITS_TO_2BYTE((_Header + 7), 0, 16) + /*BCNHWSEQ*/ #define SET_8814A_H2CCMD_BCNHWSEQ_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value) #define SET_8814A_H2CCMD_BCNHWSEQ_BCN_NUMBER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 1, 3, __Value) @@ -117,13 +136,13 @@ void rtl8814_fw_update_beacon_cmd(_adapter *padapter); #define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) s32 FillH2CCmd_8814(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); -void rtl8814_set_raid_cmd(PADAPTER padapter, u64 bitmap, u8 *arg); -void rtl8814_Add_RateATid(PADAPTER padapter, u64 rate_bitmap, u8 *arg, u8 rssi_level); +void rtl8814_set_raid_cmd(PADAPTER padapter, u64 bitmap, u8 *arg, u8 bw); void rtl8814_set_wowlan_cmd(_adapter *padapter, u8 enable); void rtl8814_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); void rtl8814_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode); u8 GetTxBufferRsvdPageNum8814(_adapter *padapter, bool wowlan); u8 rtl8814_set_rssi_cmd(_adapter *padapter, u8 *param); +void rtl8814_req_txrpt_cmd(PADAPTER padapter, u8 macid); #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW @@ -136,24 +155,11 @@ Set_RA_LDPC_8814( struct sta_info *psta, BOOLEAN bLDPC ); -int rtl8814_iqk_wait(_adapter *padapter, u32 timeout_ms); -void rtl8814_iqk_done(_adapter *padapter); -VOID -C2HPacketHandler_8814( - IN PADAPTER Adapter, - IN u8 *Buffer, - IN u8 Length -); + +s32 c2h_handler_8814a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); + #ifdef CONFIG_P2P_PS void rtl8814_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -s32 -_C2HContentParsing8814( - IN PADAPTER Adapter, - IN u8 c2hCmdId, - IN u8 c2hCmdLen, - IN u8 *tmpBuf -); - #endif/* __RTL8814A_CMD_H__ */ diff --git a/include/rtl8814a_dm.h b/include/rtl8814a_dm.h index bb925e4..f615117 100644 --- a/include/rtl8814a_dm.h +++ b/include/rtl8814a_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_DM_H__ #define __RTL8814A_DM_H__ diff --git a/include/rtl8814a_hal.h b/include/rtl8814a_hal.h index 50a1ffc..319ad21 100644 --- a/include/rtl8814a_hal.h +++ b/include/rtl8814a_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_HAL_H__ #define __RTL8814A_HAL_H__ @@ -38,15 +33,6 @@ #include "rtl8814a_sreset.h" #endif /* DBG_CONFIG_ERROR_DETECT */ - -typedef enum _TX_PWR_PERCENTAGE { - TX_PWR_PERCENTAGE_0 = 0x01, /* 12.5% */ - TX_PWR_PERCENTAGE_1 = 0x02, /* 25% */ - TX_PWR_PERCENTAGE_2 = 0x04, /* 50% */ - TX_PWR_PERCENTAGE_3 = 0x08, /* 100%, default target output power. */ -} TX_PWR_PERCENTAGE; - - enum { VOLTAGE_V25 = 0x03, LDOE25_SHIFT = 28 , @@ -67,24 +53,6 @@ typedef struct _RT_FIRMWARE_8814 { #define PAGE_SIZE_TX_8814 PAGE_SIZE_128 #define BCNQ_PAGE_NUM_8814 0x08 -/* --------------------------------------------------------------------- - * RTL8814AU From header - * --------------------------------------------------------------------- */ -#define RTL8814A_FW_IMG "rtl8814a/FW_NIC.bin" -#define RTL8814A_FW_WW_IMG "rtl8814a/FW_WoWLAN.bin" -#define RTL8814A_PHY_REG "rtl8814a/PHY_REG.txt" -#define RTL8814A_PHY_RADIO_A "rtl8814a/RadioA.txt" -#define RTL8814A_PHY_RADIO_B "rtl8814a/RadioB.txt" -#define RTL8814A_PHY_RADIO_C "rtl8814a/RadioC.txt" -#define RTL8814A_PHY_RADIO_D "rtl8814a/RadioD.txt" -#define RTL8814A_TXPWR_TRACK "rtl8814a/TxPowerTrack.txt" -#define RTL8814A_AGC_TAB "rtl8814a/AGC_TAB.txt" -#define RTL8814A_PHY_MACREG "rtl8814a/MAC_REG.txt" -#define RTL8814A_PHY_REG_PG "rtl8814a/PHY_REG_PG.txt" -#define RTL8814A_PHY_REG_MP "rtl8814a/PHY_REG_MP.txt" -#define RTL8814A_TXPWR_LMT "rtl8814a/TXPWR_LMT.txt" -#define RTL8814A_WIFI_ANT_ISOLATION "rtl8814a/wifi_ant_isolation.txt" - #define Rtl8814A_NIC_PWR_ON_FLOW rtl8814A_power_on_flow #define Rtl8814A_NIC_RF_OFF_FLOW rtl8814A_radio_off_flow #define Rtl8814A_NIC_DISABLE_FLOW rtl8814A_card_disable_flow @@ -328,7 +296,6 @@ void SetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval); void GetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval); u8 SetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); -s32 c2h_id_filter_ccx_8814a(u8 *buf); void rtl8814_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8814a(_adapter *adapter); diff --git a/include/rtl8814a_led.h b/include/rtl8814a_led.h index 1137a9b..799ae87 100644 --- a/include/rtl8814a_led.h +++ b/include/rtl8814a_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_LED_H__ #define __RTL8814A_LED_H__ diff --git a/include/rtl8814a_recv.h b/include/rtl8814a_recv.h index e9626f3..0963ea8 100644 --- a/include/rtl8814a_recv.h +++ b/include/rtl8814a_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_RECV_H__ #define __RTL8814A_RECV_H__ diff --git a/include/rtl8814a_rf.h b/include/rtl8814a_rf.h index 7b11d99..17fe1c0 100644 --- a/include/rtl8814a_rf.h +++ b/include/rtl8814a_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_RF_H__ #define __RTL8814A_RF_H__ diff --git a/include/rtl8814a_spec.h b/include/rtl8814a_spec.h index 43a6381..3d94e8e 100644 --- a/include/rtl8814a_spec.h +++ b/include/rtl8814a_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_SPEC_H__ #define __RTL8814A_SPEC_H__ @@ -640,12 +636,4 @@ So the following defines for 92C is not entire!!!!!! #define LAST_ENTRY_OF_TX_PKT_BUFFER_8814A (2048-1) /* 20130415 KaiYuan add for 8814 */ -#define MACID_NUM_8814A 128 -#define SEC_CAM_ENT_NUM_8814A 64 -#define HW_PORT_NUM_8814A 5 -#define NSS_NUM_8814A 3 -#define BAND_CAP_8814A (BAND_CAP_2G | BAND_CAP_5G) -#define BW_CAP_8814A (BW_CAP_20M | BW_CAP_40M | BW_CAP_80M) -#define PROTO_CAP_8814A (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | PROTO_CAP_11AC) - #endif /* __RTL8814A_SPEC_H__ */ diff --git a/include/rtl8814a_sreset.h b/include/rtl8814a_sreset.h index 5d95e1f..939b151 100644 --- a/include/rtl8814a_sreset.h +++ b/include/rtl8814a_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL88814A_SRESET_H_ #define _RTL8814A_SRESET_H_ diff --git a/include/rtl8814a_xmit.h b/include/rtl8814a_xmit.h index 099760d..bc9310b 100644 --- a/include/rtl8814a_xmit.h +++ b/include/rtl8814a_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_XMIT_H__ #define __RTL8814A_XMIT_H__ diff --git a/include/rtl8821a_spec.h b/include/rtl8821a_spec.h index b4dfe3f..44afdff 100644 --- a/include/rtl8821a_spec.h +++ b/include/rtl8821a_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8821A_SPEC_H__ #define __RTL8821A_SPEC_H__ @@ -93,16 +89,4 @@ * Regsiter Bit and Content definition * ************************************************************ */ -/* ******************************************************** - * General definitions - * ******************************************************** */ - -#define MACID_NUM_8821A 128 -#define SEC_CAM_ENT_NUM_8821A 64 -#define HW_PORT_NUM_8821A 2 -#define NSS_NUM_8821A 1 -#define BAND_CAP_8821A (BAND_CAP_2G | BAND_CAP_5G) -#define BW_CAP_8821A (BW_CAP_20M | BW_CAP_40M | BW_CAP_80M) -#define PROTO_CAP_8821A (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | PROTO_CAP_11AC) - #endif /* __RTL8821A_SPEC_H__ */ diff --git a/include/rtl8821a_xmit.h b/include/rtl8821a_xmit.h index e604099..5d973cd 100644 --- a/include/rtl8821a_xmit.h +++ b/include/rtl8821a_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8821A_XMIT_H__ #define __RTL8821A_XMIT_H__ @@ -141,38 +136,38 @@ typedef struct txdescriptor_8821a { } TXDESC_8821A, *PTXDESC_8821A; #ifdef CONFIG_SDIO_HCI - s32 InitXmitPriv8821AS(PADAPTER padapter); - void FreeXmitPriv8821AS(PADAPTER padapter); - s32 XmitBufHandler8821AS(PADAPTER padapter); - s32 MgntXmit8821AS(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 HalXmitNoLock8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 HalXmit8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe); - #ifndef CONFIG_SDIO_TX_TASKLET - thread_return XmitThread8821AS(thread_context context); - #endif /* !CONFIG_SDIO_TX_TASKLET */ +s32 InitXmitPriv8821AS(PADAPTER padapter); +void FreeXmitPriv8821AS(PADAPTER padapter); +s32 XmitBufHandler8821AS(PADAPTER padapter); +s32 MgntXmit8821AS(PADAPTER padapter, struct xmit_frame *pmgntframe); +s32 HalXmitNoLock8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe); +s32 HalXmit8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe); +#ifndef CONFIG_SDIO_TX_TASKLET +thread_return XmitThread8821AS(thread_context context); +#endif /* !CONFIG_SDIO_TX_TASKLET */ #endif /* CONFIG_SDIO_HCI */ #if 0 - #ifdef CONFIG_USB_HCI - s32 rtl8821au_init_xmit_priv(PADAPTER padapter); - void rtl8821au_free_xmit_priv(PADAPTER padapter); - s32 rtl8821au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8821au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8821au_hal_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8821au_xmit_buf_handler(PADAPTER padapter); - void rtl8821au_xmit_tasklet(void *priv); - s32 rtl8821au_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); - #endif /* CONFIG_USB_HCI */ +#ifdef CONFIG_USB_HCI +s32 rtl8821au_init_xmit_priv(PADAPTER padapter); +void rtl8821au_free_xmit_priv(PADAPTER padapter); +s32 rtl8821au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); +s32 rtl8821au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); +s32 rtl8821au_hal_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe); +s32 rtl8821au_xmit_buf_handler(PADAPTER padapter); +void rtl8821au_xmit_tasklet(void *priv); +s32 rtl8821au_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); +#endif /* CONFIG_USB_HCI */ - #ifdef CONFIG_PCI_HCI - s32 rtl8821e_init_xmit_priv(PADAPTER padapter); - void rtl8821e_free_xmit_priv(PADAPTER padapter); - struct xmit_buf *rtl8821e_dequeue_xmitbuf(struct rtw_tx_ring *ring); - void rtl8821e_xmitframe_resume(PADAPTER padapter); - s32 rtl8821e_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8821e_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - void rtl8821e_xmit_tasklet(void *priv); - #endif /* CONFIG_PCI_HCI */ +#ifdef CONFIG_PCI_HCI +s32 rtl8821e_init_xmit_priv(PADAPTER padapter); +void rtl8821e_free_xmit_priv(PADAPTER padapter); +struct xmit_buf *rtl8821e_dequeue_xmitbuf(struct rtw_tx_ring *ring); +void rtl8821e_xmitframe_resume(PADAPTER padapter); +s32 rtl8821e_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); +s32 rtl8821e_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); +void rtl8821e_xmit_tasklet(void *priv); +#endif /* CONFIG_PCI_HCI */ #endif #endif /* __RTL8821_XMIT_H__ */ diff --git a/include/rtl8821c_hal.h b/include/rtl8821c_hal.h index 3e2ea84..083af0c 100644 --- a/include/rtl8821c_hal.h +++ b/include/rtl8821c_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,28 +11,43 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8821C_HAL_H_ #define _RTL8821C_HAL_H_ #include /* BIT(x) */ #include "../hal/halmac/halmac_api.h" /* MAC REG definition */ #include "hal_data.h" +#include "rtl8821c_spec.h" +#include "../hal/rtl8821c/hal8821c_fw.h" + +#ifdef CONFIG_USB_HCI +#include +#endif +#ifdef CONFIG_SDIO_HCI +#include +#endif +#ifdef CONFIG_PCI_HCI +#include +#endif + +#ifdef CONFIG_SUPPORT_TRX_SHARED +#define FIFO_BLOCK_SIZE 32768 /*@Block size = 32K*/ +#define RX_FIFO_EXPANDING (1 * FIFO_BLOCK_SIZE) +#else +#define RX_FIFO_EXPANDING 0 +#endif + #if defined(CONFIG_USB_HCI) #ifndef MAX_RECVBUF_SZ #ifndef CONFIG_MINIMAL_MEMORY_USAGE #ifdef CONFIG_PLATFORM_MSTAR - #define MAX_RECVBUF_SZ (8192) /* 8K */ + #define MAX_RECVBUF_SZ (8192 + RX_FIFO_EXPANDING) /* 8K */ #else /* 8821C - RX FIFO :16K ,for RX agg DMA mode = 16K, Rx agg USB mode could large than 16k*/ - #define MAX_RECVBUF_SZ HALMAC_RX_FIFO_SIZE_8821C + #define MAX_RECVBUF_SZ (HALMAC_RX_FIFO_SIZE_8821C + RX_FIFO_EXPANDING) #endif /*#define MAX_RECVBUF_SZ_8821C (24576)*/ /* 24k*/ /*#define MAX_RECVBUF_SZ_8821C (20480)*/ /*20K*/ @@ -40,7 +55,7 @@ /*#define MAX_RECVBUF_SZ_8821C (15360)*/ /*15k < 16k*/ /*#define MAX_RECVBUF_SZ_8821C (8192+1024)*/ /* 8K+1k*/ #else - #define MAX_RECVBUF_SZ (4096) /* about 4K */ + #define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */ #endif #endif/* !MAX_RECVBUF_SZ*/ @@ -48,196 +63,19 @@ /*#ifndef CONFIG_MINIMAL_MEMORY_USAGE #define MAX_RECVBUF_SZ (9100) #else*/ - #define MAX_RECVBUF_SZ (4096) /* about 4K */ + #define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */ /*#endif*/ #elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - - #define MAX_RECVBUF_SZ HALMAC_RX_FIFO_SIZE_8821C - + #define MAX_RECVBUF_SZ (HALMAC_RX_FIFO_SIZE_8821C + RX_FIFO_EXPANDING) #endif -#define EFUSE_MAP_SIZE HALMAC_EFUSE_SIZE_8821C - -#define MACID_NUM_8821C 128 -#define NSS_NUM_8821C 1 -#define HW_PORT_NUM_8821C 5 - -/* - * MAC Register definition - */ -#define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8821C /* hal_com.c & phydm */ -#define REG_AFE_PLL_CTRL REG_AFE_CTRL2_8821C /* hal_com.c & phydm */ -#define REG_MAC_PHY_CTRL REG_AFE_CTRL3_8821C /* phydm only */ -#define REG_LEDCFG0 REG_LED_CFG_8821C /* rtw_mp.c */ -#define MSR (REG_CR_8821C + 2) /* rtw_mp.c */ -#define MSR1 REG_CR_EXT_8821C /* rtw_mp.c & hal_com.c */ -#define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ -#define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ -#define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */ -#define REG_TSFTR1 REG_FREERUN_CNT_8821C /* hal_com.c */ -#define REG_RXFLTMAP2 REG_RXFLTMAP_8821C /* rtw_mp.c */ - -/* RXERR_RPT, for rtw_mp.c */ -#define RXERR_TYPE_OFDM_PPDU 0 -#define RXERR_TYPE_OFDM_FALSE_ALARM 2 -#define RXERR_TYPE_OFDM_MPDU_OK 0 -#define RXERR_TYPE_OFDM_MPDU_FAIL 1 -#define RXERR_TYPE_CCK_PPDU 3 -#define RXERR_TYPE_CCK_FALSE_ALARM 5 -#define RXERR_TYPE_CCK_MPDU_OK 3 -#define RXERR_TYPE_CCK_MPDU_FAIL 4 -#define RXERR_TYPE_HT_PPDU 8 -#define RXERR_TYPE_HT_FALSE_ALARM 9 -#define RXERR_TYPE_HT_MPDU_TOTAL 6 -#define RXERR_TYPE_HT_MPDU_OK 6 -#define RXERR_TYPE_HT_MPDU_FAIL 7 -#define RXERR_TYPE_RX_FULL_DROP 10 - -#define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8821C -#define RXERR_RPT_RST BIT_RXERR_RPT_RST_8821C -#define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8821C(type) \ - | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8821C : 0)) - -/* - * BB Register definition - */ -#define rPMAC_Reset 0x100 /* hal_mp.c */ - -#define rFPGA0_RFMOD 0x800 -#define rFPGA0_TxInfo 0x804 -#define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */ -#define rFPGA0_TxGainStage 0x80C /* phydm only */ -#define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */ -#define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */ -#define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */ -#define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */ -#define rTxAGC_B_Rate18_06 0x830 -#define rTxAGC_B_Rate54_24 0x834 -#define rTxAGC_B_CCK1_55_Mcs32 0x838 -#define rCCAonSec_Jaguar 0x838 /* hal_mp.c */ -#define rTxAGC_B_Mcs03_Mcs00 0x83C -#define rTxAGC_B_Mcs07_Mcs04 0x848 -#define rTxAGC_B_Mcs11_Mcs08 0x84C -#define rFPGA0_XA_RFInterfaceOE 0x860 -#define rFPGA0_XB_RFInterfaceOE 0x864 -#define rTxAGC_B_Mcs15_Mcs12 0x868 -#define rTxAGC_B_CCK11_A_CCK2_11 0x86C -#define rFPGA0_XAB_RFInterfaceSW 0x870 -#define rFPGA0_XAB_RFParameter 0x878 -#define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */ -#define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */ -#define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8821c_phy.c) */ - -#define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */ -#define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */ - -#define rFPGA1_TxInfo 0x90C /* hal_mp.c */ -#define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */ - -#define rCCK0_System 0xA00 -#define rCCK0_AFESetting 0xA04 - -#define rCCK0_DSPParameter2 0xA1C -#define rCCK0_TxFilter1 0xA20 -#define rCCK0_TxFilter2 0xA24 -#define rCCK0_DebugPort 0xA28 -#define rCCK0_FalseAlarmReport 0xA2C - -#define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */ -#define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */ - -#define rOFDM0_TRxPathEnable 0xC04 -#define rOFDM0_TRMuxPar 0xC08 -#define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */ -#define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */ -#define rOFDM0_ECCAThreshold 0xC4C /* phydm only */ -#define rOFDM0_XAAGCCore1 0xC50 /* phydm only */ -#define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */ -#define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ -#define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ -#define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ -#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ - -#define rOFDM1_LSTF 0xD00 -#define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ -#define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8821c_phy.c) */ -#define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8821c_phy.c) */ -#define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8821c_phy.c) */ -#define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8821c_phy.c) */ - -#define rTxAGC_A_Rate18_06 0xE00 -#define rTxAGC_A_Rate54_24 0xE04 -#define rTxAGC_A_CCK1_Mcs32 0xE08 -#define rTxAGC_A_Mcs03_Mcs00 0xE10 -#define rTxAGC_A_Mcs07_Mcs04 0xE14 -#define rTxAGC_A_Mcs11_Mcs08 0xE18 -#define rTxAGC_A_Mcs15_Mcs12 0xE1C -#define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ -#define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ -#define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ -#define rB_RFE_Pinmux_Jaguar 0xEB0 /* hal_mp.c */ - -/* Page1(0x100) */ -#define bBBResetB 0x100 - -/* Page8(0x800) */ -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 -/* Reg 0x80C rFPGA0_TxGainStage */ -#define bXBTxAGC 0xF00 -#define bXCTxAGC 0xF000 -#define bXDTxAGC 0xF0000 - -/* PageA(0xA00) */ -#define bCCKBBMode 0x3 - -#define bCCKScramble 0x8 -#define bCCKTxRate 0x3000 - -/* General */ -#define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */ -#define bMaskByte1 0xFF00 /* hal_mp.c & phydm */ -#define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */ -#define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */ -#define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */ -#define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */ -#define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */ - -#define bEnable 0x1 /* hal_mp.c, rtw_mp.c */ -#define bDisable 0x0 /* rtw_mp.c */ - -#define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */ - -#define Rx_Smooth_Factor 20 /* phydm only */ - -/* - * RF Register definition - */ -#define RF_AC 0x00 -#define RF_AC_Jaguar 0x00 /* hal_mp.c */ -#define RF_CHNLBW 0x18 /* rtl8821c_phy.c */ -#define RF_0x52 0x52 - -/* - * 8821C files path - */ -#define RTL8821C_FW_IMG "rtl8821c/FW_NIC.bin" -#define RTL8821C_FW_WW_IMG "rtl8821c/FW_WoWLAN.bin" -#define RTL8821C_PHY_REG "rtl8821c/PHY_REG.txt" -#define RTL8821C_PHY_RADIO_A "rtl8821c/RadioA.txt" -#define RTL8821C_PHY_RADIO_B "rtl8821c/RadioB.txt" -#define RTL8821C_TXPWR_TRACK "rtl8821c/TxPowerTrack.txt" -#define RTL8821C_AGC_TAB "rtl8821c/AGC_TAB.txt" -#define RTL8821C_PHY_MACREG "rtl8821c/MAC_REG.txt" -#define RTL8821C_PHY_REG_PG "rtl8821c/PHY_REG_PG.txt" -#define RTL8821C_PHY_REG_MP "rtl8821c/PHY_REG_MP.txt" -#define RTL8821C_TXPWR_LMT "rtl8821c/TXPWR_LMT.txt" - void init_hal_spec_rtl8821c(PADAPTER); /* MP Functions */ +#ifdef CONFIG_MP_INCLUDED void rtl8821c_phy_init_haldm(PADAPTER); /* rtw_mp.c */ void rtl8821c_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ void rtl8821c_mp_config_rfpath(PADAPTER); /* hal_mp.c */ +#endif #endif /* _RTL8821C_HAL_H_ */ diff --git a/include/rtl8821cs_hal.h b/include/rtl8821cs_hal.h index 97df6e9..ceecc15 100644 --- a/include/rtl8821cs_hal.h +++ b/include/rtl8821cs_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8821CS_HAL_H_ #define _RTL8821CS_HAL_H_ diff --git a/include/rtl8821cu_hal.h b/include/rtl8821cu_hal.h index 63c25a8..aec4372 100644 --- a/include/rtl8821cu_hal.h +++ b/include/rtl8821cu_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8821CU_HAL_H_ #define _RTL8821CU_HAL_H_ diff --git a/include/rtl8822b_hal.h b/include/rtl8822b_hal.h index 5d49b58..307dd61 100644 --- a/include/rtl8822b_hal.h +++ b/include/rtl8822b_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8822B_HAL_H_ #define _RTL8822B_HAL_H_ @@ -25,7 +20,11 @@ #include "../hal/halmac/halmac_api.h" /* MAC REG definition */ +#ifdef CONFIG_SUPPORT_TRX_SHARED +#define MAX_RECVBUF_SZ HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B +#else /* !CONFIG_SUPPORT_TRX_SHARED */ #define MAX_RECVBUF_SZ HALMAC_RX_FIFO_SIZE_8822B +#endif /* !CONFIG_SUPPORT_TRX_SHARED */ /* * MAC Register definition @@ -41,6 +40,8 @@ #define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8822B /* hal_com.c */ #define REG_TSFTR1 REG_FREERUN_CNT_8822B /* hal_com.c */ #define REG_RXFLTMAP2 REG_RXFLTMAP_8822B /* rtw_mp.c */ +#define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c */ +#define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8822B /* hal_com.c */ /* RXERR_RPT, for rtw_mp.c */ #define RXERR_TYPE_OFDM_PPDU 0 @@ -194,30 +195,16 @@ #define RF_0x52 0x52 #define RF_WeLut_Jaguar 0xEF /* rtl8822b_phy.c */ -/* - * 8822B files path - */ -#define RTL8822B_FW_IMG "rtl8822b/FW_NIC.bin" -#define RTL8822B_FW_WW_IMG "rtl8822b/FW_WoWLAN.bin" -#define RTL8822B_PHY_REG "rtl8822b/PHY_REG.txt" -#define RTL8822B_PHY_RADIO_A "rtl8822b/RadioA.txt" -#define RTL8822B_PHY_RADIO_B "rtl8822b/RadioB.txt" -#define RTL8822B_TXPWR_TRACK "rtl8822b/TxPowerTrack.txt" -#define RTL8822B_AGC_TAB "rtl8822b/AGC_TAB.txt" -#define RTL8822B_PHY_MACREG "rtl8822b/MAC_REG.txt" -#define RTL8822B_PHY_REG_PG "rtl8822b/PHY_REG_PG.txt" -#define RTL8822B_PHY_REG_MP "rtl8822b/PHY_REG_MP.txt" -#define RTL8822B_TXPWR_LMT "rtl8822b/TXPWR_LMT.txt" - - /* General Functions */ void rtl8822b_init_hal_spec(PADAPTER); /* hal/hal_com.c */ +#ifdef CONFIG_MP_INCLUDED /* MP Functions */ #include /* struct mp_priv */ void rtl8822b_phy_init_haldm(PADAPTER); /* rtw_mp.c */ void rtl8822b_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ void rtl8822b_mp_config_rfpath(PADAPTER); /* hal_mp.c */ +#endif #ifdef CONFIG_USB_HCI #include diff --git a/include/rtl8822be_hal.h b/include/rtl8822be_hal.h index 8379fab..1755869 100644 --- a/include/rtl8822be_hal.h +++ b/include/rtl8822be_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8822BE_HAL_H_ #define _RTL8822BE_HAL_H_ diff --git a/include/rtl8822bs_hal.h b/include/rtl8822bs_hal.h index 313036d..ffaddee 100644 --- a/include/rtl8822bs_hal.h +++ b/include/rtl8822bs_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8822BS_HAL_H_ #define _RTL8822BS_HAL_H_ @@ -25,6 +20,10 @@ /* rtl8822bs_ops.c */ void rtl8822bs_set_hal_ops(PADAPTER); +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) +void rtl8822bs_disable_interrupt_but_cpwm2(PADAPTER adapter); +#endif + /* rtl8822bs_xmit.c */ s32 rtl8822bs_dequeue_writeport(PADAPTER); #define _dequeue_writeport(a) rtl8822bs_dequeue_writeport(a) diff --git a/include/rtl8822bu_hal.h b/include/rtl8822bu_hal.h index df16056..39618c9 100644 --- a/include/rtl8822bu_hal.h +++ b/include/rtl8822bu_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8822BU_HAL_H_ #define _RTL8822BU_HAL_H_ @@ -43,7 +38,14 @@ #define MAX_RECVBUF_SZ (8192+1024) #else /* !PLATFORM_OS_CE */ #ifndef CONFIG_MINIMAL_MEMORY_USAGE + #ifdef CONFIG_PLATFORM_NOVATEK_NT72668 + #define MAX_RECVBUF_SZ (15360) /* 15k */ + #elif defined(CONFIG_PLATFORM_HISILICON) + /* use 16k to workaround for HISILICON platform */ + #define MAX_RECVBUF_SZ (16384) + #else #define MAX_RECVBUF_SZ (32768) + #endif #else #define MAX_RECVBUF_SZ (4000) #endif diff --git a/include/rtw_android.h b/include/rtw_android.h index 09d638d..424a64e 100644 --- a/include/rtw_android.h +++ b/include/rtw_android.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_ANDROID_H__ #define __RTW_ANDROID_H__ @@ -105,10 +100,10 @@ static void rtw_android_wifictrl_func_del(void) {} #endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */ #ifdef CONFIG_GPIO_WAKEUP - #ifdef CONFIG_PLATFORM_INTEL_BYT - int wifi_configure_gpio(void); - #endif /* CONFIG_PLATFORM_INTEL_BYT */ - void wifi_free_gpio(unsigned int gpio); +#ifdef CONFIG_PLATFORM_INTEL_BYT +int wifi_configure_gpio(void); +#endif /* CONFIG_PLATFORM_INTEL_BYT */ +void wifi_free_gpio(unsigned int gpio); #endif /* CONFIG_GPIO_WAKEUP */ diff --git a/include/rtw_ap.h b/include/rtw_ap.h index fce1cd5..44e2239 100644 --- a/include/rtw_ap.h +++ b/include/rtw_ap.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,77 +11,73 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_AP_H_ - #define __RTW_AP_H_ +#define __RTW_AP_H_ - #ifdef CONFIG_AP_MODE +#ifdef CONFIG_AP_MODE - /* external function */ - extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta); - extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta); +/* external function */ +extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta); +extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta); - void init_mlme_ap_info(_adapter *padapter); - void free_mlme_ap_info(_adapter *padapter); - /* void update_BCNTIM(_adapter *padapter); */ - void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len); - void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index); - void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *tag); - #define update_beacon(adapter, ie_id, oui, tx) _update_beacon((adapter), (ie_id), (oui), (tx), __func__) - void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level); - void expire_timeout_chk(_adapter *padapter); - void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta); - void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter); - void start_bss_network(_adapter *padapter, struct createbss_parm *parm); - int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len); - void rtw_ap_restore_network(_adapter *padapter); +void init_mlme_ap_info(_adapter *padapter); +void free_mlme_ap_info(_adapter *padapter); +/* void update_BCNTIM(_adapter *padapter); */ +void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len); +void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index); +void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *tag); +#define update_beacon(adapter, ie_id, oui, tx) _update_beacon((adapter), (ie_id), (oui), (tx), __func__) +void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level, u8 is_update_bw); +void expire_timeout_chk(_adapter *padapter); +void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta); +void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter); +void start_bss_network(_adapter *padapter, struct createbss_parm *parm); +int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len); +void rtw_ap_restore_network(_adapter *padapter); - #if CONFIG_RTW_MACADDR_ACL - void rtw_set_macaddr_acl(_adapter *adapter, int mode); - int rtw_acl_add_sta(_adapter *adapter, const u8 *addr); - int rtw_acl_remove_sta(_adapter *adapter, const u8 *addr); - #endif /* CONFIG_RTW_MACADDR_ACL */ +#if CONFIG_RTW_MACADDR_ACL +void rtw_set_macaddr_acl(_adapter *adapter, int mode); +int rtw_acl_add_sta(_adapter *adapter, const u8 *addr); +int rtw_acl_remove_sta(_adapter *adapter, const u8 *addr); +#endif /* CONFIG_RTW_MACADDR_ACL */ - u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta); - int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid); - int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx); +u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta); +int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid); +int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx); - #ifdef CONFIG_NATIVEAP_MLME - void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type); - void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta); - u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta); - void sta_info_update(_adapter *padapter, struct sta_info *psta); - void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta); - u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue); - int rtw_sta_flush(_adapter *padapter, bool enqueue); - int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset); - void start_ap_mode(_adapter *padapter); - void stop_ap_mode(_adapter *padapter); - #endif - - void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset); - bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow); +#ifdef CONFIG_NATIVEAP_MLME +void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type); +void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta); +u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta); +void sta_info_update(_adapter *padapter, struct sta_info *psta); +void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta); +u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue); +int rtw_sta_flush(_adapter *padapter, bool enqueue); +int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset); +void start_ap_mode(_adapter *padapter); +void stop_ap_mode(_adapter *padapter); +#endif - #ifdef CONFIG_AUTO_AP_MODE - extern void rtw_start_auto_ap(_adapter *adapter); - #endif /* CONFIG_AUTO_AP_MODE */ +void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset); +bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow); - #endif /* end of CONFIG_AP_MODE */ +#ifdef CONFIG_AUTO_AP_MODE +extern void rtw_start_auto_ap(_adapter *adapter); +#endif /* CONFIG_AUTO_AP_MODE */ +void rtw_ap_acdata_control(_adapter *padapter, u8 power_mode); +#endif /* end of CONFIG_AP_MODE */ #endif void update_bmc_sta(_adapter *padapter); void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field); void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len); +int rtw_ht_operation_update(_adapter *padapter); #ifdef CONFIG_SWTIMER_BASED_TXBCN - void tx_beacon_handlder(struct dvobj_priv *pdvobj); - void tx_beacon_timer_handlder(struct dvobj_priv *pdvobj); +void tx_beacon_handlder(struct dvobj_priv *pdvobj); +void tx_beacon_timer_handlder(void *ctx); #endif diff --git a/include/rtw_beamforming.h b/include/rtw_beamforming.h index 1d46f4b..f589c74 100644 --- a/include/rtw_beamforming.h +++ b/include/rtw_beamforming.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,18 +11,12 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_BEAMFORMING_H_ #define __RTW_BEAMFORMING_H_ #ifdef CONFIG_BEAMFORMING -#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/ #ifdef RTW_BEAMFORMING_VERSION_2 #define MAX_NUM_BEAMFORMEE_SU 2 #define MAX_NUM_BEAMFORMER_SU 2 @@ -32,31 +26,34 @@ #define MAX_BEAMFORMEE_ENTRY_NUM (MAX_NUM_BEAMFORMEE_SU + MAX_NUM_BEAMFORMEE_MU) #define MAX_BEAMFORMER_ENTRY_NUM (MAX_NUM_BEAMFORMER_SU + MAX_NUM_BEAMFORMER_MU) -#define GetInitSoundCnt(_SoundPeriod, _MinSoundPeriod) ((_SoundPeriod)/(_MinSoundPeriod)) +/* Need to be defined by IC */ +#define SU_SOUNDING_TIMEOUT 5 /* unit: ms */ +#define MU_SOUNDING_TIMEOUT 8 /* unit: ms */ #define GET_BEAMFORM_INFO(adapter) (&GET_HAL_DATA(adapter)->beamforming_info) -#else /* !RTW_BEAMFORMING_VERSION_2 */ -#define BEAMFORMING_ENTRY_NUM 2 -#define GET_BEAMFORM_INFO(_pmlmepriv) ((struct beamforming_info *)(&(_pmlmepriv)->beamforming_info)) -#endif /* !RTW_BEAMFORMING_VERSION_2 */ - -typedef enum _BEAMFORMING_ENTRY_STATE { - BEAMFORMING_ENTRY_STATE_UNINITIALIZE, - BEAMFORMING_ENTRY_STATE_INITIALIZEING, - BEAMFORMING_ENTRY_STATE_INITIALIZED, - BEAMFORMING_ENTRY_STATE_PROGRESSING, - BEAMFORMING_ENTRY_STATE_PROGRESSED, -} BEAMFORMING_ENTRY_STATE, *PBEAMFORMING_ENTRY_STATE; +#define GetInitSoundCnt(_SoundPeriod, _MinSoundPeriod) ((_SoundPeriod)/(_MinSoundPeriod)) +enum BEAMFORMING_CTRL_TYPE { + BEAMFORMING_CTRL_ENTER = 0, + BEAMFORMING_CTRL_LEAVE = 1, + BEAMFORMING_CTRL_START_PERIOD = 2, + BEAMFORMING_CTRL_END_PERIOD = 3, + BEAMFORMING_CTRL_SOUNDING_FAIL = 4, + BEAMFORMING_CTRL_SOUNDING_CLK = 5, + BEAMFORMING_CTRL_SET_GID_TABLE = 6, + BEAMFORMING_CTRL_SET_CSI_REPORT = 7, +}; -typedef enum _BEAMFORMING_STATE { +enum _BEAMFORMING_STATE { BEAMFORMING_STATE_IDLE, BEAMFORMING_STATE_START, BEAMFORMING_STATE_END, -} BEAMFORMING_STATE, *PBEAMFORMING_STATE; - +}; -typedef enum _BEAMFORMING_CAP { +/* + * typedef BEAMFORMING_CAP for phydm + */ +typedef enum beamforming_cap { BEAMFORMING_CAP_NONE = 0x0, BEAMFORMER_CAP_HT_EXPLICIT = 0x1, BEAMFORMEE_CAP_HT_EXPLICIT = 0x2, @@ -66,23 +63,8 @@ typedef enum _BEAMFORMING_CAP { BEAMFORMEE_CAP_VHT_MU = 0x20, /* Self has ee Cap, because Reg ee & peer er */ BEAMFORMER_CAP = 0x40, BEAMFORMEE_CAP = 0x80, -} BEAMFORMING_CAP, *PBEAMFORMING_CAP; - +} BEAMFORMING_CAP; -typedef enum _SOUNDING_MODE { - SOUNDING_SW_VHT_TIMER = 0x0, - SOUNDING_SW_HT_TIMER = 0x1, - SOUNDING_STOP_All_TIMER = 0x2, - SOUNDING_HW_VHT_TIMER = 0x3, - SOUNDING_HW_HT_TIMER = 0x4, - SOUNDING_STOP_OID_TIMER = 0x5, - SOUNDING_AUTO_VHT_TIMER = 0x6, - SOUNDING_AUTO_HT_TIMER = 0x7, - SOUNDING_FW_VHT_TIMER = 0x8, - SOUNDING_FW_HT_TIMER = 0x9, -} SOUNDING_MODE, *PSOUNDING_MODE; - -#ifdef RTW_BEAMFORMING_VERSION_2 enum _BEAMFORM_ENTRY_HW_STATE { BEAMFORM_ENTRY_HW_STATE_NONE, BEAMFORM_ENTRY_HW_STATE_ADD_INIT, @@ -93,6 +75,18 @@ enum _BEAMFORM_ENTRY_HW_STATE { BEAMFORM_ENTRY_HW_STATE_MAX }; +/* The sounding state is recorded by BFer. */ +enum _SOUNDING_STATE { + SOUNDING_STATE_NONE = 0, + SOUNDING_STATE_INIT = 1, + SOUNDING_STATE_SU_START = 2, + SOUNDING_STATE_SU_SOUNDDOWN = 3, + SOUNDING_STATE_MU_START = 4, + SOUNDING_STATE_MU_SOUNDDOWN = 5, + SOUNDING_STATE_SOUNDING_TIMEOUT = 6, + SOUNDING_STATE_MAX +}; + struct beamformee_entry { u8 used; /* _TRUE/_FALSE */ u8 txbf; @@ -103,14 +97,14 @@ struct beamformee_entry { u16 mac_id; /* Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC */ u16 p_aid; - u16 g_id; + u8 g_id; /* Used to fill Reg6E4 to fill Mac address of CSI report frame */ u8 mac_addr[ETH_ALEN]; /* Sounding BandWidth */ CHANNEL_WIDTH sound_bw; u16 sound_period; - BEAMFORMING_CAP cap; + enum beamforming_cap cap; enum _BEAMFORM_ENTRY_HW_STATE state; /* The BFee need to be sounded when count to zero */ @@ -118,6 +112,12 @@ struct beamformee_entry { u8 bCandidateSoundingPeer; u8 bSoundingTimeout; u8 bDeleteSounding; + /* Get the result through throughput and Tx rate from BB API */ + u8 bApplySounding; + + /* information for sounding judgement */ + u32 tx_timestamp; + u64 tx_bytes; u16 LogStatusFailCnt:5; /* 0~21 */ u16 DefaultCSICnt:5; /* 0~21 */ @@ -125,14 +125,21 @@ struct beamformee_entry { u16 CSIMatrixLen; u8 NumofSoundingDim; - u8 CompSteeringNumofBFer; + u8 comp_steering_num_of_bfer; + + + /* SU-MIMO */ u8 su_reg_index; /* MU-MIMO */ u8 mu_reg_index; u8 gid_valid[8]; u8 user_position[16]; + + /* For 8822B C-cut workaround */ + /* If the flag set to _TRUE, do not sound this STA */ + u8 bSuspendSUCap; }; struct beamformer_entry { @@ -140,82 +147,179 @@ struct beamformer_entry { /* p_aid of BFer entry is probably not used */ /* Used to fill Reg42C & Reg714 to compare with p_aid of Tx DESC */ u16 p_aid; - u16 g_id; + u8 g_id; u8 mac_addr[ETH_ALEN]; - BEAMFORMING_CAP cap; + enum beamforming_cap cap; enum _BEAMFORM_ENTRY_HW_STATE state; u8 NumofSoundingDim; + + /* SU-MIMO */ u8 su_reg_index; - /* MU-MIMO */ + /* MU-MIMO */ u8 gid_valid[8]; u8 user_position[16]; u16 aid; }; -/* The sounding state is recorded by BFer. */ -enum _SOUNDING_STATE { - SOUNDING_STATE_NONE = 0, - SOUNDING_STATE_INIT = 1, - SOUNDING_STATE_SU_START = 2, - SOUNDING_STATE_SU_SOUNDDOWN = 3, - SOUNDING_STATE_MU_START = 4, - SOUNDING_STATE_MU_SOUNDDOWN = 5, - SOUNDING_STATE_SOUNDING_TIMEOUT = 6, - SOUNDING_STATE_MAX -}; - struct sounding_info { - u8 su_sounding_list[MAX_NUM_BEAMFORMEE_SU]; - u8 mu_sounding_list[MAX_NUM_BEAMFORMEE_MU]; + u8 su_sounding_list[MAX_NUM_BEAMFORMEE_SU]; + u8 mu_sounding_list[MAX_NUM_BEAMFORMEE_MU]; - enum _SOUNDING_STATE state; - u8 su_bfee_curidx; - u8 candidate_mu_bfee_cnt; + enum _SOUNDING_STATE state; + /* + * su_bfee_curidx is index for beamforming_info.bfee_entry[] + * range: 0~MAX_BEAMFORMEE_ENTRY_NUM + */ + u8 su_bfee_curidx; + u8 candidate_mu_bfee_cnt; /* For sounding schedule maintenance */ - u16 min_sounding_period; + u16 min_sounding_period; /* Get from sounding list */ /* Ex: SU STA1, SU STA2, MU STA(1~n) => the value will be 2+1=3 */ - u8 sound_remain_cnt_per_period; - /* Real number of SU sound per period */ - u8 su_sound_num_per_period; - /* Real number of MU sound per period */ - u8 mu_sound_num_per_period; + u8 sound_remain_cnt_per_period; +}; + +struct _RT_CSI_INFO{ + u8 Nc; + u8 Nr; + u8 Ng; + u8 CodeBook; + u8 ChnlWidth; + u8 bVHT; }; struct beamforming_info { - BEAMFORMING_CAP beamforming_cap; - BEAMFORMING_STATE beamforming_state; - struct beamformee_entry bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM]; - struct beamformer_entry bfer_entry[MAX_BEAMFORMER_ENTRY_NUM]; - u8 sounding_sequence; - u8 beamformee_su_cnt; - u8 beamformer_su_cnt; - u32 beamformee_su_reg_maping; - u32 beamformer_su_reg_maping; + enum beamforming_cap beamforming_cap; + enum _BEAMFORMING_STATE beamforming_state; + struct beamformee_entry bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM]; + struct beamformer_entry bfer_entry[MAX_BEAMFORMER_ENTRY_NUM]; + u8 sounding_sequence; + u8 beamformee_su_cnt; + u8 beamformer_su_cnt; + u32 beamformee_su_reg_maping; + u32 beamformer_su_reg_maping; /* For MU-MINO */ - u8 beamformee_mu_cnt; - u8 beamformer_mu_cnt; - u32 beamformee_mu_reg_maping; - u8 first_mu_bfee_index; - u8 mu_bfer_curidx; - - struct sounding_info sounding_info; + u8 beamformee_mu_cnt; + u8 beamformer_mu_cnt; + u32 beamformee_mu_reg_maping; + u8 first_mu_bfee_index; + u8 mu_bfer_curidx; + u8 cur_csi_rpt_rate; + + struct sounding_info sounding_info; + /* schedule regular timer for sounding */ + _timer sounding_timer; + /* moniter if soudning too long */ + _timer sounding_timeout_timer; /* For HW configuration */ - u8 SetHalBFEnterOnDemandCnt; - u8 SetHalBFLeaveOnDemandCnt; - u8 SetHalSoundownOnDemandCnt; + u8 SetHalBFEnterOnDemandCnt; + u8 SetHalBFLeaveOnDemandCnt; + u8 SetHalSoundownOnDemandCnt; + u8 bSetBFHwConfigInProgess; + + /* + * Target CSI report info. + * Keep the first SU CSI report info for 8822B HW bug workaround. + */ + u8 bEnableSUTxBFWorkAround; + struct _RT_CSI_INFO TargetCSIInfo; + /* Only peform sounding to the first SU BFee */ + struct beamformee_entry *TargetSUBFee; + + /* For debug */ + s8 sounding_running; }; -struct beamformee_entry *beamforming_get_bfee_entry_by_addr(PADAPTER, u8 *ra); -struct beamformer_entry *beamforming_get_bfer_entry_by_addr(PADAPTER, u8 *ra); -u8 beamforming_send_vht_gid_mgnt_packet(PADAPTER, struct beamformee_entry*); +enum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlmepriv, u8 mac_id); +struct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER, u8 *ra); +struct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER, u8 *ra); +void rtw_bf_get_ndpa_packet(PADAPTER, union recv_frame *); +u32 rtw_bf_get_report_packet(PADAPTER, union recv_frame *); +u8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER, u8 *ra, u8 *gid, u8 *position); +void rtw_bf_get_vht_gid_mgnt_packet(PADAPTER, union recv_frame *); +void rtw_bf_init(PADAPTER); +void rtw_bf_cmd_hdl(PADAPTER, u8 type, u8 *pbuf); +u8 rtw_bf_cmd(PADAPTER, s32 type, u8 *pbuf, s32 size, u8 enqueue); +void rtw_bf_update_attrib(PADAPTER, struct pkt_attrib *, struct sta_info *); +void rtw_bf_c2h_handler(PADAPTER, u8 id, u8 *buf, u8 buf_len); +void rtw_bf_update_traffic(PADAPTER); + +/* Compatible with old function name, only for using outside rtw_beamforming.c */ +#define beamforming_get_entry_beam_cap_by_mac_id rtw_bf_bfee_get_entry_cap_by_macid +#define rtw_beamforming_get_ndpa_frame rtw_bf_get_ndpa_packet +#define rtw_beamforming_get_report_frame rtw_bf_get_report_packet +#define rtw_beamforming_get_vht_gid_mgnt_frame rtw_bf_get_vht_gid_mgnt_packet +#define beamforming_wk_hdl rtw_bf_cmd_hdl +#define beamforming_wk_cmd rtw_bf_cmd +#define update_attrib_txbf_info rtw_bf_update_attrib + +#define HT_BF_CAP(adapter) ((adapter)->mlmepriv.htpriv.beamform_cap) +#define VHT_BF_CAP(adapter) ((adapter)->mlmepriv.vhtpriv.beamform_cap) + +#define IS_HT_BEAMFORMEE(adapter) \ + (HT_BF_CAP(adapter) & \ + (BEAMFORMING_HT_BEAMFORMEE_ENABLE)) + +#define IS_VHT_BEAMFORMEE(adapter) \ + (VHT_BF_CAP(adapter) & \ + (BEAMFORMING_VHT_BEAMFORMEE_ENABLE | \ + BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) + +#define IS_BEAMFORMEE(adapter) (IS_HT_BEAMFORMEE(adapter) | \ + IS_VHT_BEAMFORMEE(adapter)) #else /* !RTW_BEAMFORMING_VERSION_2 */ + +#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/ +#define BEAMFORMING_ENTRY_NUM 2 +#define GET_BEAMFORM_INFO(_pmlmepriv) ((struct beamforming_info *)(&(_pmlmepriv)->beamforming_info)) + + +typedef enum _BEAMFORMING_ENTRY_STATE { + BEAMFORMING_ENTRY_STATE_UNINITIALIZE, + BEAMFORMING_ENTRY_STATE_INITIALIZEING, + BEAMFORMING_ENTRY_STATE_INITIALIZED, + BEAMFORMING_ENTRY_STATE_PROGRESSING, + BEAMFORMING_ENTRY_STATE_PROGRESSED, +} BEAMFORMING_ENTRY_STATE, *PBEAMFORMING_ENTRY_STATE; + + +typedef enum _BEAMFORMING_STATE { + BEAMFORMING_STATE_IDLE, + BEAMFORMING_STATE_START, + BEAMFORMING_STATE_END, +} BEAMFORMING_STATE, *PBEAMFORMING_STATE; + + +typedef enum _BEAMFORMING_CAP { + BEAMFORMING_CAP_NONE = 0x0, + BEAMFORMER_CAP_HT_EXPLICIT = 0x1, + BEAMFORMEE_CAP_HT_EXPLICIT = 0x2, + BEAMFORMER_CAP_VHT_SU = 0x4, /* Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_SU = 0x8, /* Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP = 0x10, + BEAMFORMEE_CAP = 0x20, +} BEAMFORMING_CAP, *PBEAMFORMING_CAP; + + +typedef enum _SOUNDING_MODE { + SOUNDING_SW_VHT_TIMER = 0x0, + SOUNDING_SW_HT_TIMER = 0x1, + SOUNDING_STOP_All_TIMER = 0x2, + SOUNDING_HW_VHT_TIMER = 0x3, + SOUNDING_HW_HT_TIMER = 0x4, + SOUNDING_STOP_OID_TIMER = 0x5, + SOUNDING_AUTO_VHT_TIMER = 0x6, + SOUNDING_AUTO_HT_TIMER = 0x7, + SOUNDING_FW_VHT_TIMER = 0x8, + SOUNDING_FW_HT_TIMER = 0x9, +} SOUNDING_MODE, *PSOUNDING_MODE; + struct beamforming_entry { BOOLEAN bUsed; BOOLEAN bSound; @@ -263,11 +367,9 @@ struct rtw_ndpa_sta_info { u16 nc_index:3; }; +BEAMFORMING_CAP beamforming_get_entry_beam_cap_by_mac_id(PVOID pmlmepriv , u8 mac_id); void beamforming_notify(PADAPTER adapter); BEAMFORMING_CAP beamforming_get_beamform_cap(struct beamforming_info *pBeamInfo); -#endif /* !RTW_BEAMFORMING_VERSION_2 */ - -BEAMFORMING_CAP beamforming_get_entry_beam_cap_by_mac_id(void *mlmepriv, u8 mac_id); BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx); BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx); @@ -284,16 +386,16 @@ enum BEAMFORMING_CTRL_TYPE { BEAMFORMING_CTRL_END_PERIOD = 3, BEAMFORMING_CTRL_SOUNDING_FAIL = 4, BEAMFORMING_CTRL_SOUNDING_CLK = 5, - BEAMFORMING_CTRL_SET_GID_TABLE = 6, }; -u32 beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_frame); -void beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame); -u32 beamforming_get_vht_gid_mgnt_frame(PADAPTER, union recv_frame *); +u32 rtw_beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_frame); +void rtw_beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame); void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf); u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue); void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta); +#endif /* !RTW_BEAMFORMING_VERSION_2 */ + #endif /*#ifdef CONFIG_BEAMFORMING */ #endif /*__RTW_BEAMFORMING_H_*/ diff --git a/include/rtw_br_ext.h b/include/rtw_br_ext.h index cc1510b..54ba75e 100644 --- a/include/rtw_br_ext.h +++ b/include/rtw_br_ext.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,25 +11,20 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_BR_EXT_H_ #define _RTW_BR_EXT_H_ #if 1 /* rtw_wifi_driver */ - #define CL_IPV6_PASS 1 - #define MACADDRLEN 6 - #define _DEBUG_ERR RTW_INFO - #define _DEBUG_INFO /* RTW_INFO */ - #define DEBUG_WARN RTW_INFO - #define DEBUG_INFO /* RTW_INFO */ - #define DEBUG_ERR RTW_INFO - /* #define GET_MY_HWADDR ((GET_MIB(priv))->dot11OperationEntry.hwaddr) */ - #define GET_MY_HWADDR(padapter) (adapter_mac_addr(padapter)) +#define CL_IPV6_PASS 1 +#define MACADDRLEN 6 +#define _DEBUG_ERR RTW_INFO +#define _DEBUG_INFO /* RTW_INFO */ +#define DEBUG_WARN RTW_INFO +#define DEBUG_INFO /* RTW_INFO */ +#define DEBUG_ERR RTW_INFO +/* #define GET_MY_HWADDR ((GET_MIB(priv))->dot11OperationEntry.hwaddr) */ +#define GET_MY_HWADDR(padapter) (adapter_mac_addr(padapter)) #endif /* rtw_wifi_driver */ #define NAT25_HASH_BITS 4 diff --git a/include/rtw_bt_mp.h b/include/rtw_bt_mp.h index cd6ed0a..a152d18 100644 --- a/include/rtw_bt_mp.h +++ b/include/rtw_bt_mp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_BT_MP_H #define __RTW_BT_MP_H diff --git a/include/rtw_btcoex.h b/include/rtw_btcoex.h index b114d60..847c426 100644 --- a/include/rtw_btcoex.h +++ b/include/rtw_btcoex.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_BTCOEX_H__ #define __RTW_BTCOEX_H__ @@ -53,6 +48,13 @@ typedef enum _BT_CTRL_STATUS { BT_STATUS_MAX } BT_CTRL_STATUS, *PBT_CTRL_STATUS; +typedef enum _BTCOEX_SUSPEND_STATE { + BTCOEX_SUSPEND_STATE_RESUME = 0x0, + BTCOEX_SUSPEND_STATE_SUSPEND = 0x1, + BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT = 0x2, + BTCOEX_SUSPEND_STATE_MAX +} BTCOEX_SUSPEND_STATE, *PBTCOEX_SUSPEND_STATE; + #define SET_BT_MP_OPER_RET(OpCode, StatusCode) ((OpCode << 8) | StatusCode) #define GET_OP_CODE_FROM_BT_MP_OPER_RET(RetCode) ((RetCode & 0xF0) >> 8) #define GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode) (RetCode & 0x0F) @@ -362,6 +364,7 @@ struct bt_coex_info { void rtw_btcoex_Initialize(PADAPTER); void rtw_btcoex_PowerOnSetting(PADAPTER padapter); +void rtw_btcoex_PowerOffSetting(PADAPTER padapter); void rtw_btcoex_PreLoadFirmware(PADAPTER padapter); void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly); void rtw_btcoex_IpsNotify(PADAPTER, u8 type); @@ -375,7 +378,6 @@ void rtw_btcoex_BtInfoNotify(PADAPTER, u8 length, u8 *tmpBuf); void rtw_btcoex_BtMpRptNotify(PADAPTER, u8 length, u8 *tmpBuf); void rtw_btcoex_SuspendNotify(PADAPTER, u8 state); void rtw_btcoex_HaltNotify(PADAPTER); -void rtw_btcoex_ScoreBoardStatusNotify(PADAPTER, u8 length, u8 *tmpBuf); void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type); void rtw_btcoex_SwitchBtTRxMask(PADAPTER); void rtw_btcoex_Switch(PADAPTER, u8 enable); @@ -397,26 +399,32 @@ void rtw_btcoex_SetDBG(PADAPTER, u32 *pDbgModule); u32 rtw_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize); u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER); u8 rtw_btcoex_IsBtLinkExist(PADAPTER); -void rtw_btcoex_BTOffOnNotify(PADAPTER padapter, u8 bBTON); +void rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON); + +#ifdef CONFIG_RF4CE_COEXIST +void rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state); +u8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter); +#endif + #ifdef CONFIG_BT_COEXIST_SOCKET_TRX - void rtw_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer); - void rtw_btcoex_SetHciVersion(PADAPTER padapter, u16 hciVersion); - void rtw_btcoex_StackUpdateProfileInfo(void); - void rtw_btcoex_init_socket(_adapter *padapter); - void rtw_btcoex_close_socket(_adapter *padapter); - void rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name); - u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force); - u8 rtw_btcoex_create_kernel_socket(_adapter *padapter); - void rtw_btcoex_close_kernel_socket(_adapter *padapter); - void rtw_btcoex_recvmsgbysocket(void *data); - u16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size); - u8 rtw_btcoex_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length); - void rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *cmd, u16 len); - void rtw_btcoex_SendEventExtBtCoexControl(PADAPTER Adapter, u8 bNeedDbgRsp, u8 dataLen, void *pData); - void rtw_btcoex_SendEventExtBtInfoControl(PADAPTER Adapter, u8 dataLen, void *pData); - void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType); - #define BT_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData) rtw_btcoex_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData) - #define BT_SendEventExtBtInfoControl(Adapter, dataLen, pData) rtw_btcoex_SendEventExtBtInfoControl(Adapter, dataLen, pData) +void rtw_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer); +void rtw_btcoex_SetHciVersion(PADAPTER padapter, u16 hciVersion); +void rtw_btcoex_StackUpdateProfileInfo(void); +void rtw_btcoex_init_socket(_adapter *padapter); +void rtw_btcoex_close_socket(_adapter *padapter); +void rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name); +u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force); +u8 rtw_btcoex_create_kernel_socket(_adapter *padapter); +void rtw_btcoex_close_kernel_socket(_adapter *padapter); +void rtw_btcoex_recvmsgbysocket(void *data); +u16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size); +u8 rtw_btcoex_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length); +void rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *cmd, u16 len); +void rtw_btcoex_SendEventExtBtCoexControl(PADAPTER Adapter, u8 bNeedDbgRsp, u8 dataLen, void *pData); +void rtw_btcoex_SendEventExtBtInfoControl(PADAPTER Adapter, u8 dataLen, void *pData); +void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType); +#define BT_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData) rtw_btcoex_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData) +#define BT_SendEventExtBtInfoControl(Adapter, dataLen, pData) rtw_btcoex_SendEventExtBtInfoControl(Adapter, dataLen, pData) #endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data); u16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val); @@ -431,8 +439,8 @@ u8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter); /* ================================================== * Below Functions are called by BT-Coex * ================================================== */ -void rtw_btcoex_rx_ampdu_apply(PADAPTER); -void rtw_btcoex_LPS_Enter(PADAPTER); -void rtw_btcoex_LPS_Leave(PADAPTER); +void rtw_btcoex_rx_ampdu_apply(PADAPTER padapter); +void rtw_btcoex_LPS_Enter(PADAPTER padapter); +u8 rtw_btcoex_LPS_Leave(PADAPTER padapter); #endif /* __RTW_BTCOEX_H__ */ diff --git a/include/rtw_byteorder.h b/include/rtw_byteorder.h index 70482d2..8e6bb7a 100644 --- a/include/rtw_byteorder.h +++ b/include/rtw_byteorder.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL871X_BYTEORDER_H_ #define _RTL871X_BYTEORDER_H_ diff --git a/include/rtw_cmd.h b/include/rtw_cmd.h index 6455dff..8ae7c9a 100644 --- a/include/rtw_cmd.h +++ b/include/rtw_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_CMD_H_ #define __RTW_CMD_H_ @@ -60,7 +55,8 @@ enum { struct cmd_priv { _sema cmd_queue_sema; /* _sema cmd_done_sema; */ - _sema terminate_cmdthread_sema; + _sema start_cmdthread_sema; + _queue cmd_queue; u8 cmd_seq; u8 *cmd_buf; /* shall be non-paged, and 4 bytes aligned */ @@ -72,7 +68,7 @@ struct cmd_priv { u32 rsp_cnt; ATOMIC_T cmdthd_running; /* u8 cmdthd_running; */ - u8 stop_req; + _adapter *padapter; _mutex sctx_mutex; }; @@ -90,16 +86,19 @@ struct evt_obj { struct evt_priv { #ifdef CONFIG_EVENT_THREAD_MODE _sema evt_notify; - _sema terminate_evtthread_sema; + _queue evt_queue; #endif -#define CONFIG_C2H_WK +#ifdef CONFIG_FW_C2H_REG + #define CONFIG_C2H_WK +#endif + #ifdef CONFIG_C2H_WK _workitem c2h_wk; bool c2h_wk_alive; struct rtw_cbuf *c2h_queue; -#define C2H_QUEUE_MAX_LEN 10 + #define C2H_QUEUE_MAX_LEN 10 #endif #ifdef CONFIG_H2CLBK @@ -142,23 +141,6 @@ struct evt_priv { pcmd->rspsz = 0;\ } while (0) -struct c2h_evt_hdr { - u8 id:4; - u8 plen:4; - u8 seq; - u8 payload[0]; -}; - -struct c2h_evt_hdr_88xx { - u8 id; - u8 seq; - u8 payload[12]; - u8 plen; - u8 trigger; -}; - -#define c2h_evt_valid(c2h_evt) ((c2h_evt)->id || (c2h_evt)->plen) - struct P2P_PS_Offload_t { u8 Offload_En:1; u8 role:1; /* 1: Owner, 0: Client */ @@ -189,9 +171,9 @@ extern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv); extern void rtw_free_cmd_obj(struct cmd_obj *pcmd); #ifdef CONFIG_EVENT_THREAD_MODE - extern u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj); - extern struct evt_obj *rtw_dequeue_evt(_queue *queue); - extern void rtw_free_evt_obj(struct evt_obj *pcmd); +extern u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj); +extern struct evt_obj *rtw_dequeue_evt(_queue *queue); +extern void rtw_free_evt_obj(struct evt_obj *pcmd); #endif void rtw_stop_cmd_thread(_adapter *adapter); @@ -205,7 +187,25 @@ extern void rtw_free_evt_priv(struct evt_priv *pevtpriv); extern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv); extern void rtw_evt_notify_isr(struct evt_priv *pevtpriv); #ifdef CONFIG_P2P - u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType); +u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType); + +#ifdef CONFIG_IOCTL_CFG80211 +struct p2p_roch_parm { + u64 cookie; + struct wireless_dev *wdev; + struct ieee80211_channel ch; + enum nl80211_channel_type ch_type; + unsigned int duration; +}; + +u8 p2p_roch_cmd(_adapter *adapter + , u64 cookie, struct wireless_dev *wdev + , struct ieee80211_channel *ch, enum nl80211_channel_type ch_type + , unsigned int duration + , u8 flags +); +u8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags); +#endif /* CONFIG_IOCTL_CFG80211 */ #endif /* CONFIG_P2P */ #else @@ -238,6 +238,8 @@ enum rtw_drvextra_cmd_id { SESSION_TRACKER_WK_CID, EN_HW_UPDATE_TSF_WK_CID, TEST_H2C_CID, + MP_CMD_WK_CID, + CUSTOMER_STR_WK_CID, MAX_WK_CID }; @@ -329,23 +331,20 @@ struct createbss_parm { }; #if 0 - /* Caller Mode: AP, Ad-HoC, Infra */ - - /* Notes: To set the NIC mode of RTL8711 */ - - /* Command Mode */ - - /* The definition of mode: */ - - #define IW_MODE_AUTO 0 /* Let the driver decides which AP to join */ - #define IW_MODE_ADHOC 1 /* Single cell network (Ad-Hoc Clients) */ - #define IW_MODE_INFRA 2 /* Multi cell network, roaming, .. */ - #define IW_MODE_MASTER 3 /* Synchronisation master or Access Point */ - #define IW_MODE_REPEAT 4 /* Wireless Repeater (forwarder) */ - #define IW_MODE_SECOND 5 /* Secondary master/repeater (backup) */ - #define IW_MODE_MONITOR 6 /* Passive monitor (listen only) */ - +/* Caller Mode: AP, Ad-HoC, Infra */ +/* Notes: To set the NIC mode of RTL8711 */ +/* Command Mode */ +/* The definition of mode: */ + +#define IW_MODE_AUTO 0 /* Let the driver decides which AP to join */ +#define IW_MODE_ADHOC 1 /* Single cell network (Ad-Hoc Clients) */ +#define IW_MODE_INFRA 2 /* Multi cell network, roaming, .. */ +#define IW_MODE_MASTER 3 /* Synchronisation master or Access Point */ +#define IW_MODE_REPEAT 4 /* Wireless Repeater (forwarder) */ +#define IW_MODE_SECOND 5 /* Secondary master/repeater (backup) */ +#define IW_MODE_MONITOR 6 /* Passive monitor (listen only) */ #endif + struct setopmode_parm { u8 mode; u8 rsvd[3]; @@ -448,13 +447,9 @@ struct set_assocsta_rsp { /* Caller Ad-Hoc/AP - Command mode - This is to force fw to del an sta_data entry per driver's request - FW will invalidate the cam entry associated with it. - */ struct del_assocsta_parm { u8 addr[ETH_ALEN]; @@ -535,35 +530,6 @@ struct getdatarate_rsp { u8 datarates[NumRates]; }; - -/* -Caller Mode: Any -AP: AP can use the info for the contents of beacon frame -Infra: STA can use the info when sitesurveying -Ad-HoC(M): Like AP -Ad-HoC(C): Like STA - - -Notes: To set the phy capability of the NIC - -Command Mode - -*/ - -struct setphyinfo_parm { - struct regulatory_class class_sets[NUM_REGULATORYS]; - u8 status; -}; - -struct getphyinfo_parm { - u32 rsvd; -}; - -struct getphyinfo_rsp { - struct regulatory_class class_sets[NUM_REGULATORYS]; - u8 status; -}; - /* Caller Mode: Any @@ -1030,7 +996,7 @@ extern u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_ty extern u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue); extern u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork); -u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, bool enqueue); +u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags); extern u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, bool enqueue); extern u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset); extern u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset); @@ -1060,11 +1026,11 @@ u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter); u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim); #if (RATE_ADAPTIVE_SUPPORT == 1) - u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime); +u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime); #endif #ifdef CONFIG_ANTENNA_DIVERSITY - extern u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue); +extern u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue); #endif u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta); @@ -1075,7 +1041,7 @@ extern u8 rtw_ps_cmd(_adapter *padapter); u8 rtw_chk_hi_queue_cmd(_adapter *padapter); #ifdef CONFIG_DFS_MASTER u8 rtw_dfs_master_cmd(_adapter *adapter, bool enqueue); -void rtw_dfs_master_timer_hdl(RTW_TIMER_HDL_ARGS); +void rtw_dfs_master_timer_hdl(void *ctx); void rtw_dfs_master_enable(_adapter *adapter, u8 ch, u8 bw, u8 offset); void rtw_dfs_master_disable(_adapter *adapter, u8 ch, u8 bw, u8 offset, bool by_others); enum { @@ -1090,7 +1056,7 @@ void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action); #endif /* CONFIG_AP_MODE */ #ifdef CONFIG_BT_COEXIST - u8 rtw_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length); +u8 rtw_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length); #endif u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len); @@ -1106,11 +1072,19 @@ extern u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed); extern u8 rtw_set_csa_cmd(_adapter *padapter, u8 new_ch_no); extern u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option); -/* #ifdef CONFIG_C2H_PACKET_EN */ -extern u8 rtw_c2h_packet_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length); -/* #else */ -extern u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *c2h_evt); -/* #endif */ +u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags); + +#ifdef CONFIG_RTW_CUSTOMER_STR +u8 rtw_customer_str_req_cmd(_adapter *adapter); +u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr); +#endif + +#ifdef CONFIG_FW_C2H_REG +u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt); +#endif +#ifdef CONFIG_FW_C2H_PKT +u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length); +#endif u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context); diff --git a/include/rtw_debug.h b/include/rtw_debug.h index 9db67e2..74a26de 100644 --- a/include/rtw_debug.h +++ b/include/rtw_debug.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_DEBUG_H__ #define __RTW_DEBUG_H__ @@ -34,7 +29,7 @@ enum { #define DRIVER_PREFIX "RTW: " #ifdef PLATFORM_OS_CE - extern void rtl871x_cedbg(const char *fmt, ...); +extern void rtl871x_cedbg(const char *fmt, ...); #endif #ifdef PLATFORM_WINDOWS @@ -67,6 +62,7 @@ enum { #define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) #define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) +#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) #define _RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) #define _RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) @@ -76,8 +72,6 @@ enum { /* don't use these 3 APIs anymore, will be removed later */ #define RT_TRACE(_Comp, _Level, Fmt) do {} while (0) -#define _func_enter_ do {} while (0) -#define _func_exit_ do {} while (0) #undef _dbgdump @@ -100,7 +94,7 @@ enum { #ifdef CONFIG_RTW_DEBUG #ifndef _OS_INTFS_C_ - extern uint rtw_drv_log_level; +extern uint rtw_drv_log_level; #endif #if defined(_dbgdump) @@ -151,35 +145,55 @@ enum { #undef RTW_INFO_DUMP #define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) \ - if (_DRV_INFO_ <= rtw_drv_log_level) { \ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - _dbgdump("%s", DRIVER_PREFIX); \ - _dbgdump(_TitleString); \ - for (__i = 0; __i<(int)_HexDataLen; __i++) \ - { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } + do {\ + if (_DRV_INFO_ <= rtw_drv_log_level) { \ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + _dbgdump("%s", DRIVER_PREFIX); \ + _dbgdump(_TitleString); \ + for (__i = 0; __i < (int)_HexDataLen; __i++) { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) \ + _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } \ + } while (0) #undef RTW_DBG_DUMP #define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) \ - if (_DRV_DEBUG_ <= rtw_drv_log_level) { \ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - _dbgdump("%s", DRIVER_PREFIX); \ - _dbgdump(_TitleString); \ - for (__i = 0; __i<(int)_HexDataLen; __i++) \ - { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } + do {\ + if (_DRV_DEBUG_ <= rtw_drv_log_level) { \ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + _dbgdump("%s", DRIVER_PREFIX); \ + _dbgdump(_TitleString); \ + for (__i = 0; __i < (int)_HexDataLen; __i++) { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) \ + _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } \ + } while (0) +#undef RTW_PRINT_DUMP +#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) \ + do {\ + if (_DRV_ALWAYS_ <= rtw_drv_log_level) { \ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + _dbgdump("%s", DRIVER_PREFIX); \ + _dbgdump(_TitleString); \ + for (__i = 0; __i < (int)_HexDataLen; __i++) { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) \ + _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } \ + } while (0) /* without driver-defined prefix */ #undef _RTW_PRINT @@ -283,6 +297,32 @@ enum { } \ } while (0) +/* dump message to selected 'stream' */ +#undef _RTW_DUMP_SEL +#define _RTW_DUMP_SEL(sel, _HexData, _HexDataLen) \ + do {\ + if (sel == RTW_DBGDUMP) {\ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + for (__i = 0; __i < (int)_HexDataLen; __i++) { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) \ + _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } \ + else {\ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + for (__i = 0; __i < (int)_HexDataLen; __i++) { \ + _seqdump(sel, "%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) \ + _seqdump(sel, "\n"); \ + } \ + _seqdump(sel, "\n"); \ + } \ + } while (0) + #endif /* defined(_seqdump) */ @@ -297,32 +337,29 @@ void dump_log_level(void *sel); void dump_drv_cfg(void *sel); #ifdef CONFIG_SDIO_HCI - void sd_f0_reg_dump(void *sel, _adapter *adapter); - void sdio_local_reg_dump(void *sel, _adapter *adapter); +void sd_f0_reg_dump(void *sel, _adapter *adapter); +void sdio_local_reg_dump(void *sel, _adapter *adapter); #endif /* CONFIG_SDIO_HCI */ void mac_reg_dump(void *sel, _adapter *adapter); void bb_reg_dump(void *sel, _adapter *adapter); +void bb_reg_dump_ex(void *sel, _adapter *adapter); void rf_reg_dump(void *sel, _adapter *adapter); -bool rtw_fwdl_test_trigger_chksum_fail(void); -bool rtw_fwdl_test_trigger_wintint_rdy_fail(void); -bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void); - -u32 rtw_get_wait_hiq_empty_ms(void); void rtw_sink_rtp_seq_dbg(_adapter *adapter, _pkt *pkt); struct sta_info; void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta); struct dvobj_priv; +void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj); void dump_adapters_status(void *sel, struct dvobj_priv *dvobj); -void dump_adapters_info(void *sel, struct dvobj_priv *dvobj); struct sec_cam_ent; void dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id); void dump_sec_cam_ent_title(void *sel, u8 has_id); void dump_sec_cam(void *sel, _adapter *adapter); +void dump_sec_cam_cache(void *sel, _adapter *adapter); #ifdef CONFIG_PROC_DEBUG ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); @@ -333,12 +370,16 @@ int proc_get_fwstate(struct seq_file *m, void *v); int proc_get_sec_info(struct seq_file *m, void *v); int proc_get_mlmext_state(struct seq_file *m, void *v); #ifdef CONFIG_LAYER2_ROAMING - int proc_get_roam_flags(struct seq_file *m, void *v); - ssize_t proc_set_roam_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - int proc_get_roam_param(struct seq_file *m, void *v); - ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_roam_flags(struct seq_file *m, void *v); +ssize_t proc_set_roam_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_roam_param(struct seq_file *m, void *v); +ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif /* CONFIG_LAYER2_ROAMING */ +#ifdef CONFIG_RTW_80211R +int proc_get_ft_flags(struct seq_file *m, void *v); +ssize_t proc_set_ft_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif int proc_get_qos_option(struct seq_file *m, void *v); int proc_get_ht_option(struct seq_file *m, void *v); int proc_get_rf_info(struct seq_file *m, void *v); @@ -346,49 +387,61 @@ int proc_get_scan_param(struct seq_file *m, void *v); ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_scan_abort(struct seq_file *m, void *v); #ifdef CONFIG_SCAN_BACKOP - int proc_get_backop_flags_sta(struct seq_file *m, void *v); - ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - int proc_get_backop_flags_ap(struct seq_file *m, void *v); - ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_backop_flags_sta(struct seq_file *m, void *v); +ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_backop_flags_ap(struct seq_file *m, void *v); +ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif /* CONFIG_SCAN_BACKOP */ int proc_get_survey_info(struct seq_file *m, void *v); ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_ap_info(struct seq_file *m, void *v); ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_trx_info(struct seq_file *m, void *v); +ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_tx_power_offset(struct seq_file *m, void *v); int proc_get_rate_ctl(struct seq_file *m, void *v); int proc_get_wifi_spec(struct seq_file *m, void *v); ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_bw_ctl(struct seq_file *m, void *v); ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #ifdef DBG_RX_COUNTER_DUMP - int proc_get_rx_cnt_dump(struct seq_file *m, void *v); - ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_rx_cnt_dump(struct seq_file *m, void *v); +ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif int proc_get_dis_pwt(struct seq_file *m, void *v); ssize_t proc_set_dis_pwt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_suspend_resume_info(struct seq_file *m, void *v); +bool rtw_fwdl_test_trigger_chksum_fail(void); +bool rtw_fwdl_test_trigger_wintint_rdy_fail(void); ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void); ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #ifdef CONFIG_DFS_MASTER - int proc_get_dfs_master_test_case(struct seq_file *m, void *v); - ssize_t proc_set_dfs_master_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_dfs_master_test_case(struct seq_file *m, void *v); +ssize_t proc_set_dfs_master_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif /* CONFIG_DFS_MASTER */ +u32 rtw_get_wait_hiq_empty_ms(void); ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +void rtw_sta_linking_test_set_start(void); +bool rtw_sta_linking_test_wait_done(void); +bool rtw_sta_linking_test_force_fail(void); +ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_rx_stat(struct seq_file *m, void *v); +int proc_get_tx_stat(struct seq_file *m, void *v); #ifdef CONFIG_AP_MODE - int proc_get_all_sta_info(struct seq_file *m, void *v); +int proc_get_all_sta_info(struct seq_file *m, void *v); #endif /* CONFIG_AP_MODE */ #ifdef DBG_MEMORY_LEAK - int proc_get_malloc_cnt(struct seq_file *m, void *v); +int proc_get_malloc_cnt(struct seq_file *m, void *v); #endif /* DBG_MEMORY_LEAK */ #ifdef CONFIG_FIND_BEST_CHANNEL - int proc_get_best_channel(struct seq_file *m, void *v); - ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_best_channel(struct seq_file *m, void *v); +ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif /* CONFIG_FIND_BEST_CHANNEL */ int proc_get_trx_info_debug(struct seq_file *m, void *v); @@ -396,124 +449,144 @@ int proc_get_trx_info_debug(struct seq_file *m, void *v); int proc_get_rx_signal(struct seq_file *m, void *v); ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_hw_status(struct seq_file *m, void *v); +ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #ifdef CONFIG_80211N_HT - int proc_get_ht_enable(struct seq_file *m, void *v); - ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - - int proc_get_bw_mode(struct seq_file *m, void *v); - ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - - int proc_get_ampdu_enable(struct seq_file *m, void *v); - ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - - int proc_get_mac_rptbuf(struct seq_file *m, void *v); - - int proc_get_rx_ampdu(struct seq_file *m, void *v); - ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - - int proc_get_rx_stbc(struct seq_file *m, void *v); - ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - - - int proc_get_rx_ampdu_factor(struct seq_file *m, void *v); - ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - - int proc_get_rx_ampdu_density(struct seq_file *m, void *v); - ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - - int proc_get_tx_ampdu_density(struct seq_file *m, void *v); - ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_ht_enable(struct seq_file *m, void *v); +ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_bw_mode(struct seq_file *m, void *v); +ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_ampdu_enable(struct seq_file *m, void *v); +ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_mac_rptbuf(struct seq_file *m, void *v); + +void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter); +int proc_get_rx_ampdu(struct seq_file *m, void *v); +ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +void rtw_dump_dft_phy_cap(void *sel, _adapter *adapter); +void rtw_get_dft_phy_cap(void *sel, _adapter *adapter); +void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter); + +int proc_get_rx_stbc(struct seq_file *m, void *v); +ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_stbc_cap(struct seq_file *m, void *v); +ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_ldpc_cap(struct seq_file *m, void *v); +ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#ifdef CONFIG_BEAMFORMING +int proc_get_txbf_cap(struct seq_file *m, void *v); +ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif +int proc_get_rx_ampdu_factor(struct seq_file *m, void *v); +ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - int proc_get_tx_amsdu(struct seq_file *m, void *v); - ssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_tx_max_agg_num(struct seq_file *m, void *v); +ssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - int proc_get_tx_amsdu_rate(struct seq_file *m, void *v); - ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_rx_ampdu_density(struct seq_file *m, void *v); +ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_tx_ampdu_density(struct seq_file *m, void *v); +ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#ifdef CONFIG_TX_AMSDU +int proc_get_tx_amsdu(struct seq_file *m, void *v); +ssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_tx_amsdu_rate(struct seq_file *m, void *v); +ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif #endif /* CONFIG_80211N_HT */ - int proc_get_en_fwps(struct seq_file *m, void *v); ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -/* int proc_get_two_path_rssi(struct seq_file *m, void *v); - * int proc_get_rssi_disp(struct seq_file *m, void *v); - * ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); */ +#if 0 +int proc_get_two_path_rssi(struct seq_file *m, void *v); +int proc_get_rssi_disp(struct seq_file *m, void *v); +ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif #ifdef CONFIG_BT_COEXIST - int proc_get_btcoex_dbg(struct seq_file *m, void *v); - ssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - int proc_get_btcoex_info(struct seq_file *m, void *v); +int proc_get_btcoex_dbg(struct seq_file *m, void *v); +ssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_btcoex_info(struct seq_file *m, void *v); +#ifdef CONFIG_RF4CE_COEXIST +int proc_get_rf4ce_state(struct seq_file *m, void *v); +ssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif #endif /* CONFIG_BT_COEXIST */ #if defined(DBG_CONFIG_ERROR_DETECT) - int proc_get_sreset(struct seq_file *m, void *v); - ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_sreset(struct seq_file *m, void *v); +ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif /* DBG_CONFIG_ERROR_DETECT */ -int proc_get_odm_dbg_comp(struct seq_file *m, void *v); -ssize_t proc_set_odm_dbg_comp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_odm_dbg_level(struct seq_file *m, void *v); -ssize_t proc_set_odm_dbg_level(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - int proc_get_odm_adaptivity(struct seq_file *m, void *v); ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #ifdef CONFIG_DBG_COUNTER - int proc_get_rx_logs(struct seq_file *m, void *v); - int proc_get_tx_logs(struct seq_file *m, void *v); - int proc_get_int_logs(struct seq_file *m, void *v); +int proc_get_rx_logs(struct seq_file *m, void *v); +int proc_get_tx_logs(struct seq_file *m, void *v); +int proc_get_int_logs(struct seq_file *m, void *v); #endif #ifdef CONFIG_PCI_HCI - int proc_get_rx_ring(struct seq_file *m, void *v); - int proc_get_tx_ring(struct seq_file *m, void *v); +int proc_get_rx_ring(struct seq_file *m, void *v); +int proc_get_tx_ring(struct seq_file *m, void *v); +int proc_get_pci_aspm(struct seq_file *m, void *v); #endif #ifdef CONFIG_WOWLAN int proc_get_pattern_info(struct seq_file *m, void *v); ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer, - size_t count, loff_t *pos, void *data); + size_t count, loff_t *pos, void *data); +int proc_get_wakeup_reason(struct seq_file *m, void *v); #endif #ifdef CONFIG_GPIO_WAKEUP int proc_get_wowlan_gpio_info(struct seq_file *m, void *v); ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer, - size_t count, loff_t *pos, void *data); + size_t count, loff_t *pos, void *data); #endif /*CONFIG_GPIO_WAKEUP*/ #ifdef CONFIG_P2P_WOWLAN - int proc_get_p2p_wowlan_info(struct seq_file *m, void *v); +int proc_get_p2p_wowlan_info(struct seq_file *m, void *v); #endif /* CONFIG_P2P_WOWLAN */ int proc_get_new_bcn_max(struct seq_file *m, void *v); ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #ifdef CONFIG_POWER_SAVING - int proc_get_ps_info(struct seq_file *m, void *v); +int proc_get_ps_info(struct seq_file *m, void *v); #endif /* CONFIG_POWER_SAVING */ #ifdef CONFIG_TDLS - int proc_get_tdls_info(struct seq_file *m, void *v); +int proc_get_tdls_info(struct seq_file *m, void *v); #endif int proc_get_monitor(struct seq_file *m, void *v); ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#ifdef DBG_XMIT_BLOCK +int proc_get_xmit_block(struct seq_file *m, void *v); +ssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER - int proc_get_rtkm_info(struct seq_file *m, void *v); +int proc_get_rtkm_info(struct seq_file *m, void *v); #endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ #ifdef CONFIG_IEEE80211W - ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - int proc_get_tx_sa_query(struct seq_file *m, void *v); - ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - int proc_get_tx_deauth(struct seq_file *m, void *v); - ssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - int proc_get_tx_auth(struct seq_file *m, void *v); +ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_tx_sa_query(struct seq_file *m, void *v); +ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_tx_deauth(struct seq_file *m, void *v); +ssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_tx_auth(struct seq_file *m, void *v); #endif /* CONFIG_IEEE80211W */ #endif /* CONFIG_PROC_DEBUG */ @@ -522,22 +595,24 @@ int proc_get_efuse_map(struct seq_file *m, void *v); ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #ifdef CONFIG_MCC_MODE - int proc_get_mcc_info(struct seq_file *m, void *v); - ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - ssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - ssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - ssize_t proc_set_mcc_ap_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - ssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - ssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); - ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_mcc_info(struct seq_file *m, void *v); +ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_mcc_ap_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_mcc_policy_table(struct seq_file *m, void *v); +ssize_t proc_set_mcc_policy_table(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif /* CONFIG_MCC_MODE */ -#ifdef CONFIG_NAPI -int proc_get_napi(struct seq_file *m, void *v); -ssize_t proc_set_napi(struct file *file, const char __user *buffer, - size_t count, loff_t *pos, void *data); -#endif +int proc_get_ack_timeout(struct seq_file *m, void *v); +ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_iqk_fw_offload(struct seq_file *m, void *v); +ssize_t proc_set_iqk_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #define _drv_always_ 1 #define _drv_emerg_ 2 diff --git a/include/rtw_eeprom.h b/include/rtw_eeprom.h index 55b22f6..62304d5 100644 --- a/include/rtw_eeprom.h +++ b/include/rtw_eeprom.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_EEPROM_H__ #define __RTW_EEPROM_H__ @@ -73,13 +68,13 @@ typedef enum _RT_CUSTOMER_ID { RT_CID_819x_ALPHA = 16, RT_CID_819x_Sitecom = 17, RT_CID_CCX = 18, /* It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. */ - RT_CID_819x_Lenovo = 19, + RT_CID_819X_LENOVO = 19, RT_CID_819x_QMI = 20, RT_CID_819x_Edimax_Belkin = 21, RT_CID_819x_Sercomm_Belkin = 22, RT_CID_819x_CAMEO1 = 23, RT_CID_819x_MSI = 24, - RT_CID_819x_Acer = 25, + RT_CID_819X_ACER = 25, RT_CID_819x_AzWave_ASUS = 26, RT_CID_819x_AzWave = 27, /* For AzWave in PCIe, The ID is AzWave use and not only Asus */ RT_CID_819x_HP = 28, @@ -111,11 +106,11 @@ extern void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz); extern void read_eeprom_content_by_attrib(_adapter *padapter); #ifdef PLATFORM_LINUX - #ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE - extern int isAdaptorInfoFileValid(void); - extern int storeAdaptorInfoFile(char *path, u8 *efuse_data); - extern int retriveAdaptorInfoFile(char *path, u8 *efuse_data); - #endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */ +#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE +extern int isAdaptorInfoFileValid(void); +extern int storeAdaptorInfoFile(char *path, u8 *efuse_data); +extern int retriveAdaptorInfoFile(char *path, u8 *efuse_data); +#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */ #endif /* PLATFORM_LINUX */ #endif /* __RTL871X_EEPROM_H__ */ diff --git a/include/rtw_efuse.h b/include/rtw_efuse.h index 35f2251..2e73342 100644 --- a/include/rtw_efuse.h +++ b/include/rtw_efuse.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_EFUSE_H__ #define __RTW_EFUSE_H__ @@ -52,6 +47,8 @@ enum _EFUSE_DEF_TYPE { #define EFUSE_MAX_HW_SIZE 1024 #define EFUSE_MAX_SECTION_BASE 16 +#define EFUSE_MAX_SECTION_NUM 128 +#define EFUSE_MAX_BANK_SIZE 512 /*RTL8822B 8821C BT EFUSE Define 1 BANK 128 size logical map 1024*/ #ifdef RTW_HALMAC @@ -159,7 +156,7 @@ typedef struct _EFUSE_HAL { } EFUSE_HAL, *PEFUSE_HAL; -extern u8 maskfileBuffer[32]; +extern u8 maskfileBuffer[64]; /*------------------------Export global variable----------------------------*/ extern u8 fakeEfuseBank; @@ -178,8 +175,22 @@ extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; extern u8 fakeBTEfuseInitMap[]; extern u8 fakeBTEfuseModifiedMap[]; /*------------------------Export global variable----------------------------*/ +#define MAX_SEGMENT_SIZE 200 +#define MAX_SEGMENT_NUM 200 +#define MAX_BUF_SIZE (MAX_SEGMENT_SIZE*MAX_SEGMENT_NUM) +#define TMP_BUF_SIZE 100 + +static u8 dcmd_Return_Buffer[MAX_BUF_SIZE] = {0}; +static u32 dcmd_Buf_Idx = 0; +static u32 dcmd_Finifh_Flag = 0; + +static char dcmd_Buf[TMP_BUF_SIZE]; + +#define rtprintf dcmd_Store_Return_Buf + u8 efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size); u16 efuse_bt_GetMaxSize(PADAPTER padapter); +u16 efuse_GetavailableSize(PADAPTER adapter); u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size); u16 efuse_GetMaxSize(PADAPTER padapter); @@ -197,6 +208,8 @@ u8 Efuse_CalculateWordCnts(u8 word_en); void ReadEFuseByte(PADAPTER Adapter, u16 _offset, u8 *pbuf, BOOLEAN bPseudoTest) ; void EFUSE_GetEfuseDefinition(PADAPTER pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest); u8 efuse_OneByteRead(PADAPTER pAdapter, u16 addr, u8 *data, BOOLEAN bPseudoTest); +#define efuse_onebyte_read(adapter, addr, data, pseudo_test) efuse_OneByteRead((adapter), (addr), (data), (pseudo_test)) + u8 efuse_OneByteWrite(PADAPTER pAdapter, u16 addr, u8 data, BOOLEAN bPseudoTest); void BTEfuse_PowerSwitch(PADAPTER pAdapter, u8 bWrite, u8 PwrState); @@ -205,10 +218,9 @@ int Efuse_PgPacketRead(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTe int Efuse_PgPacketWrite(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata); u8 Efuse_WordEnableDataWrite(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); - -u8 EFUSE_Read1Byte(PADAPTER pAdapter, u16 Address); void EFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); void EFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value); +#define efuse_logical_map_read(adapter, type, offset, value) EFUSE_ShadowRead((adapter), (type), (offset), (value)) VOID hal_ReadEFuse_BT_logic_map( PADAPTER padapter, @@ -222,6 +234,9 @@ u8 EfusePgPacketWrite_BT( u8 word_en, u8 *pData, u8 bPseudoTest); +u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter); +void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray); +void rtw_efuse_analyze(PADAPTER padapter, u8 Type, u8 Fake); #define MAC_HIDDEN_MAX_BW_NUM 8 extern const u8 _mac_hidden_max_bw_to_hal_bw_cap[]; @@ -234,11 +249,11 @@ extern const u8 _mac_hidden_proto_to_hal_proto_cap[]; u8 mac_hidden_wl_func_to_hal_wl_func(u8 func); #ifdef PLATFORM_LINUX - u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len); - #ifdef CONFIG_EFUSE_CONFIG_FILE - u32 rtw_read_efuse_from_file(const char *path, u8 *buf); - u32 rtw_read_macaddr_from_file(const char *path, u8 *buf); - #endif /* CONFIG_EFUSE_CONFIG_FILE */ +u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len); +#ifdef CONFIG_EFUSE_CONFIG_FILE +u32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size); +u32 rtw_read_macaddr_from_file(const char *path, u8 *buf); +#endif /* CONFIG_EFUSE_CONFIG_FILE */ #endif /* PLATFORM_LINUX */ #endif diff --git a/include/rtw_event.h b/include/rtw_event.h index 4516e5c..8e4d5d6 100644 --- a/include/rtw_event.h +++ b/include/rtw_event.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_EVENT_H_ #define _RTW_EVENT_H_ diff --git a/include/rtw_ht.h b/include/rtw_ht.h index 8ae15ed..028f2c8 100644 --- a/include/rtw_ht.h +++ b/include/rtw_ht.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_HT_H_ #define _RTW_HT_H_ diff --git a/include/rtw_io.h b/include/rtw_io.h index fa2956c..28430d8 100644 --- a/include/rtw_io.h +++ b/include/rtw_io.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_IO_H_ #define _RTW_IO_H_ @@ -307,21 +302,21 @@ struct reg_protocol_wt { }; #ifdef CONFIG_PCI_HCI - #define MAX_CONTINUAL_IO_ERR 4 +#define MAX_CONTINUAL_IO_ERR 4 #endif #ifdef CONFIG_USB_HCI - #define MAX_CONTINUAL_IO_ERR 4 +#define MAX_CONTINUAL_IO_ERR 4 #endif #ifdef CONFIG_SDIO_HCI - #define SD_IO_TRY_CNT (8) - #define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT +#define SD_IO_TRY_CNT (8) +#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT #endif #ifdef CONFIG_GSPI_HCI - #define SD_IO_TRY_CNT (8) - #define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT +#define SD_IO_TRY_CNT (8) +#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT #endif @@ -379,15 +374,15 @@ extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val); extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata); #ifdef CONFIG_SDIO_HCI - u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr); - #ifdef CONFIG_SDIO_INDIRECT_ACCESS - u8 _rtw_sd_iread8(_adapter *adapter, u32 addr); - u16 _rtw_sd_iread16(_adapter *adapter, u32 addr); - u32 _rtw_sd_iread32(_adapter *adapter, u32 addr); - int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val); - int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val); - int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val); - #endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr); +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 _rtw_sd_iread8(_adapter *adapter, u32 addr); +u16 _rtw_sd_iread16(_adapter *adapter, u32 addr); +u32 _rtw_sd_iread32(_adapter *adapter, u32 addr); +int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val); +int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val); +int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val); +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ #endif /* CONFIG_SDIO_HCI */ extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val); @@ -400,102 +395,102 @@ u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int extern void _rtw_write_port_cancel(_adapter *adapter); #ifdef DBG_IO - bool match_read_sniff_ranges(u32 addr, u16 len); - bool match_write_sniff_ranges(u32 addr, u16 len); - bool match_rf_read_sniff_ranges(u8 path, u32 addr, u32 mask); - bool match_rf_write_sniff_ranges(u8 path, u32 addr, u32 mask); - - extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line); - extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line); - extern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line); - - extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line); - extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line); - extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line); - extern int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line); - - #ifdef CONFIG_SDIO_HCI - u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line); - #ifdef CONFIG_SDIO_INDIRECT_ACCESS - u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line); - u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line); - u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line); - int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line); - int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line); - int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line); - #endif /* CONFIG_SDIO_INDIRECT_ACCESS */ - #endif /* CONFIG_SDIO_HCI */ - - #define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__) - #define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__) - #define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__) - #define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) - #define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) - #define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) - - #define rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__) - #define rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__) - #define rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__) - #define rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__) - - #define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) - #define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) - #define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) - - #define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem) - #define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem) - #define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) - #define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter) - - #ifdef CONFIG_SDIO_HCI - #define rtw_sd_f0_read8(adapter, addr) dbg_rtw_sd_f0_read8((adapter), (addr), __func__, __LINE__) - #ifdef CONFIG_SDIO_INDIRECT_ACCESS - #define rtw_sd_iread8(adapter, addr) dbg_rtw_sd_iread8((adapter), (addr), __func__, __LINE__) - #define rtw_sd_iread16(adapter, addr) dbg_rtw_sd_iread16((adapter), (addr), __func__, __LINE__) - #define rtw_sd_iread32(adapter, addr) dbg_rtw_sd_iread32((adapter), (addr), __func__, __LINE__) - #define rtw_sd_iwrite8(adapter, addr, val) dbg_rtw_sd_iwrite8((adapter), (addr), (val), __func__, __LINE__) - #define rtw_sd_iwrite16(adapter, addr, val) dbg_rtw_sd_iwrite16((adapter), (addr), (val), __func__, __LINE__) - #define rtw_sd_iwrite32(adapter, addr, val) dbg_rtw_sd_iwrite32((adapter), (addr), (val), __func__, __LINE__) - #endif /* CONFIG_SDIO_INDIRECT_ACCESS */ - #endif /* CONFIG_SDIO_HCI */ +bool match_read_sniff_ranges(u32 addr, u16 len); +bool match_write_sniff_ranges(u32 addr, u16 len); +bool match_rf_read_sniff_ranges(u8 path, u32 addr, u32 mask); +bool match_rf_write_sniff_ranges(u8 path, u32 addr, u32 mask); + +extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line); +extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line); +extern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line); + +extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line); +extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line); +extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line); +extern int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line); + +#ifdef CONFIG_SDIO_HCI +u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line); +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line); +u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line); +u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line); +int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line); +int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line); +int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line); +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ + +#define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__) +#define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__) +#define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__) +#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) +#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) +#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) + +#define rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__) +#define rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__) +#define rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__) +#define rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__) + +#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) +#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) +#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) + +#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem) +#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem) +#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) +#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter) + +#ifdef CONFIG_SDIO_HCI +#define rtw_sd_f0_read8(adapter, addr) dbg_rtw_sd_f0_read8((adapter), (addr), __func__, __LINE__) +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +#define rtw_sd_iread8(adapter, addr) dbg_rtw_sd_iread8((adapter), (addr), __func__, __LINE__) +#define rtw_sd_iread16(adapter, addr) dbg_rtw_sd_iread16((adapter), (addr), __func__, __LINE__) +#define rtw_sd_iread32(adapter, addr) dbg_rtw_sd_iread32((adapter), (addr), __func__, __LINE__) +#define rtw_sd_iwrite8(adapter, addr, val) dbg_rtw_sd_iwrite8((adapter), (addr), (val), __func__, __LINE__) +#define rtw_sd_iwrite16(adapter, addr, val) dbg_rtw_sd_iwrite16((adapter), (addr), (val), __func__, __LINE__) +#define rtw_sd_iwrite32(adapter, addr, val) dbg_rtw_sd_iwrite32((adapter), (addr), (val), __func__, __LINE__) +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ #else /* DBG_IO */ - #define match_read_sniff_ranges(addr, len) _FALSE - #define match_write_sniff_ranges(addr, len) _FALSE - #define match_rf_read_sniff_ranges(path, addr, mask) _FALSE - #define match_rf_write_sniff_ranges(path, addr, mask) _FALSE - #define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr)) - #define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr)) - #define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr)) - #define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) - #define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) - #define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) - - #define rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val)) - #define rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val)) - #define rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val)) - #define rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data)) - - #define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) - #define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) - #define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) - - #define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem)) - #define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem)) - #define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) - #define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter)) - - #ifdef CONFIG_SDIO_HCI - #define rtw_sd_f0_read8(adapter, addr) _rtw_sd_f0_read8((adapter), (addr)) - #ifdef CONFIG_SDIO_INDIRECT_ACCESS - #define rtw_sd_iread8(adapter, addr) _rtw_sd_iread8((adapter), (addr)) - #define rtw_sd_iread16(adapter, addr) _rtw_sd_iread16((adapter), (addr)) - #define rtw_sd_iread32(adapter, addr) _rtw_sd_iread32((adapter), (addr)) - #define rtw_sd_iwrite8(adapter, addr, val) _rtw_sd_iwrite8((adapter), (addr), (val)) - #define rtw_sd_iwrite16(adapter, addr, val) _rtw_sd_iwrite16((adapter), (addr), (val)) - #define rtw_sd_iwrite32(adapter, addr, val) _rtw_sd_iwrite32((adapter), (addr), (val)) - #endif /* CONFIG_SDIO_INDIRECT_ACCESS */ - #endif /* CONFIG_SDIO_HCI */ +#define match_read_sniff_ranges(addr, len) _FALSE +#define match_write_sniff_ranges(addr, len) _FALSE +#define match_rf_read_sniff_ranges(path, addr, mask) _FALSE +#define match_rf_write_sniff_ranges(path, addr, mask) _FALSE +#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr)) +#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr)) +#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr)) +#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) +#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) +#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) + +#define rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val)) +#define rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val)) +#define rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val)) +#define rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data)) + +#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) +#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) +#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) + +#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem)) +#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem)) +#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) +#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter)) + +#ifdef CONFIG_SDIO_HCI +#define rtw_sd_f0_read8(adapter, addr) _rtw_sd_f0_read8((adapter), (addr)) +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +#define rtw_sd_iread8(adapter, addr) _rtw_sd_iread8((adapter), (addr)) +#define rtw_sd_iread16(adapter, addr) _rtw_sd_iread16((adapter), (addr)) +#define rtw_sd_iread32(adapter, addr) _rtw_sd_iread32((adapter), (addr)) +#define rtw_sd_iwrite8(adapter, addr, val) _rtw_sd_iwrite8((adapter), (addr), (val)) +#define rtw_sd_iwrite16(adapter, addr, val) _rtw_sd_iwrite16((adapter), (addr), (val)) +#define rtw_sd_iwrite32(adapter, addr, val) _rtw_sd_iwrite32((adapter), (addr), (val)) +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ #endif /* DBG_IO */ diff --git a/include/rtw_ioctl.h b/include/rtw_ioctl.h index 7537425..4924751 100644 --- a/include/rtw_ioctl.h +++ b/include/rtw_ioctl.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,75 +11,70 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_IOCTL_H_ #define _RTW_IOCTL_H_ #ifndef PLATFORM_WINDOWS - /* 00 - Success - * 11 - Error */ - #define STATUS_SUCCESS (0x00000000L) - #define STATUS_PENDING (0x00000103L) - - #define STATUS_UNSUCCESSFUL (0xC0000001L) - #define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL) - #define STATUS_NOT_SUPPORTED (0xC00000BBL) - - #define NDIS_STATUS_SUCCESS ((NDIS_STATUS)STATUS_SUCCESS) - #define NDIS_STATUS_PENDING ((NDIS_STATUS)STATUS_PENDING) - #define NDIS_STATUS_NOT_RECOGNIZED ((NDIS_STATUS)0x00010001L) - #define NDIS_STATUS_NOT_COPIED ((NDIS_STATUS)0x00010002L) - #define NDIS_STATUS_NOT_ACCEPTED ((NDIS_STATUS)0x00010003L) - #define NDIS_STATUS_CALL_ACTIVE ((NDIS_STATUS)0x00010007L) - - #define NDIS_STATUS_FAILURE ((NDIS_STATUS)STATUS_UNSUCCESSFUL) - #define NDIS_STATUS_RESOURCES ((NDIS_STATUS)STATUS_INSUFFICIENT_RESOURCES) - #define NDIS_STATUS_CLOSING ((NDIS_STATUS)0xC0010002L) - #define NDIS_STATUS_BAD_VERSION ((NDIS_STATUS)0xC0010004L) - #define NDIS_STATUS_BAD_CHARACTERISTICS ((NDIS_STATUS)0xC0010005L) - #define NDIS_STATUS_ADAPTER_NOT_FOUND ((NDIS_STATUS)0xC0010006L) - #define NDIS_STATUS_OPEN_FAILED ((NDIS_STATUS)0xC0010007L) - #define NDIS_STATUS_DEVICE_FAILED ((NDIS_STATUS)0xC0010008L) - #define NDIS_STATUS_MULTICAST_FULL ((NDIS_STATUS)0xC0010009L) - #define NDIS_STATUS_MULTICAST_EXISTS ((NDIS_STATUS)0xC001000AL) - #define NDIS_STATUS_MULTICAST_NOT_FOUND ((NDIS_STATUS)0xC001000BL) - #define NDIS_STATUS_REQUEST_ABORTED ((NDIS_STATUS)0xC001000CL) - #define NDIS_STATUS_RESET_IN_PROGRESS ((NDIS_STATUS)0xC001000DL) - #define NDIS_STATUS_CLOSING_INDICATING ((NDIS_STATUS)0xC001000EL) - #define NDIS_STATUS_NOT_SUPPORTED ((NDIS_STATUS)STATUS_NOT_SUPPORTED) - #define NDIS_STATUS_INVALID_PACKET ((NDIS_STATUS)0xC001000FL) - #define NDIS_STATUS_OPEN_LIST_FULL ((NDIS_STATUS)0xC0010010L) - #define NDIS_STATUS_ADAPTER_NOT_READY ((NDIS_STATUS)0xC0010011L) - #define NDIS_STATUS_ADAPTER_NOT_OPEN ((NDIS_STATUS)0xC0010012L) - #define NDIS_STATUS_NOT_INDICATING ((NDIS_STATUS)0xC0010013L) - #define NDIS_STATUS_INVALID_LENGTH ((NDIS_STATUS)0xC0010014L) - #define NDIS_STATUS_INVALID_DATA ((NDIS_STATUS)0xC0010015L) - #define NDIS_STATUS_BUFFER_TOO_SHORT ((NDIS_STATUS)0xC0010016L) - #define NDIS_STATUS_INVALID_OID ((NDIS_STATUS)0xC0010017L) - #define NDIS_STATUS_ADAPTER_REMOVED ((NDIS_STATUS)0xC0010018L) - #define NDIS_STATUS_UNSUPPORTED_MEDIA ((NDIS_STATUS)0xC0010019L) - #define NDIS_STATUS_GROUP_ADDRESS_IN_USE ((NDIS_STATUS)0xC001001AL) - #define NDIS_STATUS_FILE_NOT_FOUND ((NDIS_STATUS)0xC001001BL) - #define NDIS_STATUS_ERROR_READING_FILE ((NDIS_STATUS)0xC001001CL) - #define NDIS_STATUS_ALREADY_MAPPED ((NDIS_STATUS)0xC001001DL) - #define NDIS_STATUS_RESOURCE_CONFLICT ((NDIS_STATUS)0xC001001EL) - #define NDIS_STATUS_NO_CABLE ((NDIS_STATUS)0xC001001FL) - - #define NDIS_STATUS_INVALID_SAP ((NDIS_STATUS)0xC0010020L) - #define NDIS_STATUS_SAP_IN_USE ((NDIS_STATUS)0xC0010021L) - #define NDIS_STATUS_INVALID_ADDRESS ((NDIS_STATUS)0xC0010022L) - #define NDIS_STATUS_VC_NOT_ACTIVATED ((NDIS_STATUS)0xC0010023L) - #define NDIS_STATUS_DEST_OUT_OF_ORDER ((NDIS_STATUS)0xC0010024L) /* cause 27 */ - #define NDIS_STATUS_VC_NOT_AVAILABLE ((NDIS_STATUS)0xC0010025L) /* cause 35, 45 */ - #define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((NDIS_STATUS)0xC0010026L) /* cause 37 */ - #define NDIS_STATUS_INCOMPATABLE_QOS ((NDIS_STATUS)0xC0010027L) /* cause 49 */ - #define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((NDIS_STATUS)0xC0010028L) /* cause 93 */ - #define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((NDIS_STATUS)0xC0010029L) /* cause 3 */ +/* 00 - Success +* 11 - Error */ +#define STATUS_SUCCESS (0x00000000L) +#define STATUS_PENDING (0x00000103L) + +#define STATUS_UNSUCCESSFUL (0xC0000001L) +#define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL) +#define STATUS_NOT_SUPPORTED (0xC00000BBL) + +#define NDIS_STATUS_SUCCESS ((NDIS_STATUS)STATUS_SUCCESS) +#define NDIS_STATUS_PENDING ((NDIS_STATUS)STATUS_PENDING) +#define NDIS_STATUS_NOT_RECOGNIZED ((NDIS_STATUS)0x00010001L) +#define NDIS_STATUS_NOT_COPIED ((NDIS_STATUS)0x00010002L) +#define NDIS_STATUS_NOT_ACCEPTED ((NDIS_STATUS)0x00010003L) +#define NDIS_STATUS_CALL_ACTIVE ((NDIS_STATUS)0x00010007L) + +#define NDIS_STATUS_FAILURE ((NDIS_STATUS)STATUS_UNSUCCESSFUL) +#define NDIS_STATUS_RESOURCES ((NDIS_STATUS)STATUS_INSUFFICIENT_RESOURCES) +#define NDIS_STATUS_CLOSING ((NDIS_STATUS)0xC0010002L) +#define NDIS_STATUS_BAD_VERSION ((NDIS_STATUS)0xC0010004L) +#define NDIS_STATUS_BAD_CHARACTERISTICS ((NDIS_STATUS)0xC0010005L) +#define NDIS_STATUS_ADAPTER_NOT_FOUND ((NDIS_STATUS)0xC0010006L) +#define NDIS_STATUS_OPEN_FAILED ((NDIS_STATUS)0xC0010007L) +#define NDIS_STATUS_DEVICE_FAILED ((NDIS_STATUS)0xC0010008L) +#define NDIS_STATUS_MULTICAST_FULL ((NDIS_STATUS)0xC0010009L) +#define NDIS_STATUS_MULTICAST_EXISTS ((NDIS_STATUS)0xC001000AL) +#define NDIS_STATUS_MULTICAST_NOT_FOUND ((NDIS_STATUS)0xC001000BL) +#define NDIS_STATUS_REQUEST_ABORTED ((NDIS_STATUS)0xC001000CL) +#define NDIS_STATUS_RESET_IN_PROGRESS ((NDIS_STATUS)0xC001000DL) +#define NDIS_STATUS_CLOSING_INDICATING ((NDIS_STATUS)0xC001000EL) +#define NDIS_STATUS_NOT_SUPPORTED ((NDIS_STATUS)STATUS_NOT_SUPPORTED) +#define NDIS_STATUS_INVALID_PACKET ((NDIS_STATUS)0xC001000FL) +#define NDIS_STATUS_OPEN_LIST_FULL ((NDIS_STATUS)0xC0010010L) +#define NDIS_STATUS_ADAPTER_NOT_READY ((NDIS_STATUS)0xC0010011L) +#define NDIS_STATUS_ADAPTER_NOT_OPEN ((NDIS_STATUS)0xC0010012L) +#define NDIS_STATUS_NOT_INDICATING ((NDIS_STATUS)0xC0010013L) +#define NDIS_STATUS_INVALID_LENGTH ((NDIS_STATUS)0xC0010014L) +#define NDIS_STATUS_INVALID_DATA ((NDIS_STATUS)0xC0010015L) +#define NDIS_STATUS_BUFFER_TOO_SHORT ((NDIS_STATUS)0xC0010016L) +#define NDIS_STATUS_INVALID_OID ((NDIS_STATUS)0xC0010017L) +#define NDIS_STATUS_ADAPTER_REMOVED ((NDIS_STATUS)0xC0010018L) +#define NDIS_STATUS_UNSUPPORTED_MEDIA ((NDIS_STATUS)0xC0010019L) +#define NDIS_STATUS_GROUP_ADDRESS_IN_USE ((NDIS_STATUS)0xC001001AL) +#define NDIS_STATUS_FILE_NOT_FOUND ((NDIS_STATUS)0xC001001BL) +#define NDIS_STATUS_ERROR_READING_FILE ((NDIS_STATUS)0xC001001CL) +#define NDIS_STATUS_ALREADY_MAPPED ((NDIS_STATUS)0xC001001DL) +#define NDIS_STATUS_RESOURCE_CONFLICT ((NDIS_STATUS)0xC001001EL) +#define NDIS_STATUS_NO_CABLE ((NDIS_STATUS)0xC001001FL) + +#define NDIS_STATUS_INVALID_SAP ((NDIS_STATUS)0xC0010020L) +#define NDIS_STATUS_SAP_IN_USE ((NDIS_STATUS)0xC0010021L) +#define NDIS_STATUS_INVALID_ADDRESS ((NDIS_STATUS)0xC0010022L) +#define NDIS_STATUS_VC_NOT_ACTIVATED ((NDIS_STATUS)0xC0010023L) +#define NDIS_STATUS_DEST_OUT_OF_ORDER ((NDIS_STATUS)0xC0010024L) /* cause 27 */ +#define NDIS_STATUS_VC_NOT_AVAILABLE ((NDIS_STATUS)0xC0010025L) /* cause 35, 45 */ +#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((NDIS_STATUS)0xC0010026L) /* cause 37 */ +#define NDIS_STATUS_INCOMPATABLE_QOS ((NDIS_STATUS)0xC0010027L) /* cause 49 */ +#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((NDIS_STATUS)0xC0010028L) /* cause 93 */ +#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((NDIS_STATUS)0xC0010029L) /* cause 3 */ #endif /* #ifndef PLATFORM_WINDOWS */ @@ -122,13 +117,6 @@ #define OID_MP_SEG3 0xFF818700 #define OID_MP_SEG4 0xFF011100 -#define DEBUG_OID(dbg, str) \ - if ((!dbg)) \ - { \ - RT_TRACE(_module_rtl871x_ioctl_c_, _drv_info_,("%s(%d): %s", __FUNCTION__, __LINE__, str)); \ - } - - enum oid_type { QUERY_OID, SET_OID @@ -163,144 +151,142 @@ struct oid_obj_priv { (defined(PLATFORM_WINDOWS) && defined(_RTW_IOCTL_RTL_C_)) static NDIS_STATUS oid_null_function(struct oid_par_priv *poid_par_priv) { - _func_enter_; - _func_exit_; return NDIS_STATUS_SUCCESS; } #endif #ifdef PLATFORM_WINDOWS - int TranslateNdisPsToRtPs(IN NDIS_802_11_POWER_MODE ndisPsMode); - - /* OID Handler for Segment 1 */ - NDIS_STATUS oid_gen_supported_list_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_hardware_status_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_media_supported_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_media_in_use_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_maximum_lookahead_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_maximum_frame_size_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_link_speed_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_transmit_buffer_space_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_receive_buffer_space_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_transmit_block_size_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_receive_block_size_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_vendor_id_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_vendor_description_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_current_packet_filter_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_current_lookahead_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_driver_version_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_maximum_total_size_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_protocol_options_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_mac_options_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_media_connect_status_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_maximum_send_packets_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_vendor_driver_version_hdl(struct oid_par_priv *poid_par_priv); - - - /* OID Handler for Segment 2 */ - NDIS_STATUS oid_gen_physical_medium_hdl(struct oid_par_priv *poid_par_priv); - - /* OID Handler for Segment 3 */ - NDIS_STATUS oid_gen_xmit_ok_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_rcv_ok_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_xmit_error_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_rcv_error_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_gen_rcv_no_buffer_hdl(struct oid_par_priv *poid_par_priv); - - - /* OID Handler for Segment 4 */ - NDIS_STATUS oid_802_3_permanent_address_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_3_current_address_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_3_multicast_list_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_3_maximum_list_size_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_3_mac_options_hdl(struct oid_par_priv *poid_par_priv); - - - - /* OID Handler for Segment 5 */ - NDIS_STATUS oid_802_3_rcv_error_alignment_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_3_xmit_one_collision_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_3_xmit_more_collisions_hdl(struct oid_par_priv *poid_par_priv); - - - /* OID Handler for Segment 6 */ - NDIS_STATUS oid_802_3_xmit_deferred_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_3_xmit_max_collisions_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_3_rcv_overrun_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_3_xmit_underrun_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_3_xmit_heartbeat_failure_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_3_xmit_times_crs_lost_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_3_xmit_late_collisions_hdl(struct oid_par_priv *poid_par_priv); - - - - /* OID Handler for Segment 7 */ - NDIS_STATUS oid_pnp_capabilities_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_pnp_set_power_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_pnp_query_power_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_pnp_add_wake_up_pattern_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_pnp_remove_wake_up_pattern_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_pnp_wake_up_pattern_list_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_pnp_enable_wake_up_hdl(struct oid_par_priv *poid_par_priv); - - - - /* OID Handler for Segment 8 */ - NDIS_STATUS oid_802_11_bssid_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_ssid_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_infrastructure_mode_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_add_wep_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_remove_wep_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_disassociate_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_authentication_mode_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_privacy_filter_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_bssid_list_scan_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_encryption_status_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_reload_defaults_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_add_key_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_remove_key_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_association_information_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_test_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_media_stream_mode_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_capability_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_pmkid_hdl(struct oid_par_priv *poid_par_priv); - - - - - - /* OID Handler for Segment 9 */ - NDIS_STATUS oid_802_11_network_types_supported_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_network_type_in_use_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_tx_power_level_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_rssi_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_rssi_trigger_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_fragmentation_threshold_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_rts_threshold_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_number_of_antennas_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_rx_antenna_selected_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_tx_antenna_selected_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_supported_rates_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_desired_rates_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_configuration_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_power_mode_hdl(struct oid_par_priv *poid_par_priv); - NDIS_STATUS oid_802_11_bssid_list_hdl(struct oid_par_priv *poid_par_priv); +int TranslateNdisPsToRtPs(IN NDIS_802_11_POWER_MODE ndisPsMode); + +/* OID Handler for Segment 1 */ +NDIS_STATUS oid_gen_supported_list_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_hardware_status_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_media_supported_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_media_in_use_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_maximum_lookahead_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_maximum_frame_size_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_link_speed_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_transmit_buffer_space_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_receive_buffer_space_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_transmit_block_size_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_receive_block_size_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_vendor_id_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_vendor_description_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_current_packet_filter_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_current_lookahead_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_driver_version_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_maximum_total_size_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_protocol_options_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_mac_options_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_media_connect_status_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_maximum_send_packets_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_vendor_driver_version_hdl(struct oid_par_priv *poid_par_priv); + + +/* OID Handler for Segment 2 */ +NDIS_STATUS oid_gen_physical_medium_hdl(struct oid_par_priv *poid_par_priv); + +/* OID Handler for Segment 3 */ +NDIS_STATUS oid_gen_xmit_ok_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_rcv_ok_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_xmit_error_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_rcv_error_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_gen_rcv_no_buffer_hdl(struct oid_par_priv *poid_par_priv); + + +/* OID Handler for Segment 4 */ +NDIS_STATUS oid_802_3_permanent_address_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_3_current_address_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_3_multicast_list_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_3_maximum_list_size_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_3_mac_options_hdl(struct oid_par_priv *poid_par_priv); + + + +/* OID Handler for Segment 5 */ +NDIS_STATUS oid_802_3_rcv_error_alignment_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_3_xmit_one_collision_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_3_xmit_more_collisions_hdl(struct oid_par_priv *poid_par_priv); + + +/* OID Handler for Segment 6 */ +NDIS_STATUS oid_802_3_xmit_deferred_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_3_xmit_max_collisions_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_3_rcv_overrun_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_3_xmit_underrun_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_3_xmit_heartbeat_failure_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_3_xmit_times_crs_lost_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_3_xmit_late_collisions_hdl(struct oid_par_priv *poid_par_priv); + + + +/* OID Handler for Segment 7 */ +NDIS_STATUS oid_pnp_capabilities_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_pnp_set_power_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_pnp_query_power_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_pnp_add_wake_up_pattern_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_pnp_remove_wake_up_pattern_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_pnp_wake_up_pattern_list_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_pnp_enable_wake_up_hdl(struct oid_par_priv *poid_par_priv); + + + +/* OID Handler for Segment 8 */ +NDIS_STATUS oid_802_11_bssid_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_ssid_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_infrastructure_mode_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_add_wep_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_remove_wep_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_disassociate_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_authentication_mode_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_privacy_filter_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_bssid_list_scan_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_encryption_status_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_reload_defaults_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_add_key_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_remove_key_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_association_information_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_test_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_media_stream_mode_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_capability_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_pmkid_hdl(struct oid_par_priv *poid_par_priv); + + + + + +/* OID Handler for Segment 9 */ +NDIS_STATUS oid_802_11_network_types_supported_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_network_type_in_use_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_tx_power_level_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_rssi_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_rssi_trigger_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_fragmentation_threshold_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_rts_threshold_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_number_of_antennas_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_rx_antenna_selected_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_tx_antenna_selected_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_supported_rates_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_desired_rates_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_configuration_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_power_mode_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_802_11_bssid_list_hdl(struct oid_par_priv *poid_par_priv); - /* OID Handler for Segment 10 */ - NDIS_STATUS oid_802_11_statistics_hdl(struct oid_par_priv *poid_par_priv); +/* OID Handler for Segment 10 */ +NDIS_STATUS oid_802_11_statistics_hdl(struct oid_par_priv *poid_par_priv); - /* OID Handler for Segment ED */ - NDIS_STATUS oid_rt_mh_vender_id_hdl(struct oid_par_priv *poid_par_priv); +/* OID Handler for Segment ED */ +NDIS_STATUS oid_rt_mh_vender_id_hdl(struct oid_par_priv *poid_par_priv); - void Set_802_3_MULTICAST_LIST(ADAPTER *pAdapter, UCHAR *MCListbuf, ULONG MCListlen, BOOLEAN bAcceptAllMulticast); +void Set_802_3_MULTICAST_LIST(ADAPTER *pAdapter, UCHAR *MCListbuf, ULONG MCListlen, BOOLEAN bAcceptAllMulticast); #endif/* end of PLATFORM_WINDOWS */ #if defined(PLATFORM_LINUX) && defined(CONFIG_WIRELESS_EXT) - extern struct iw_handler_def rtw_handlers_def; +extern struct iw_handler_def rtw_handlers_def; #endif extern void rtw_request_wps_pbc_event(_adapter *padapter); @@ -323,4 +309,11 @@ extern NDIS_STATUS drv_set_info( OUT u32 *BytesNeeded ); +#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE +extern int rtw_vendor_ie_get_raw_data(struct net_device *, u32, char *, u32); +extern int rtw_vendor_ie_get_data(struct net_device*, int , char*); +extern int rtw_vendor_ie_get(struct net_device *, struct iw_request_info *, union iwreq_data *, char *); +extern int rtw_vendor_ie_set(struct net_device*, struct iw_request_info*, union iwreq_data*, char*); +#endif + #endif /* #ifndef __INC_CEINFO_ */ diff --git a/include/rtw_ioctl_query.h b/include/rtw_ioctl_query.h index 1ccf0df..cc7b557 100644 --- a/include/rtw_ioctl_query.h +++ b/include/rtw_ioctl_query.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,21 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_IOCTL_QUERY_H_ #define _RTW_IOCTL_QUERY_H_ #ifdef PLATFORM_WINDOWS - - u8 query_802_11_capability(_adapter *padapter, u8 *pucBuf, u32 *pulOutLen); - u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIATION_INFORMATION pAssocInfo); - +u8 query_802_11_capability(_adapter *padapter, u8 *pucBuf, u32 *pulOutLen); +u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIATION_INFORMATION pAssocInfo); #endif diff --git a/include/rtw_ioctl_rtl.h b/include/rtw_ioctl_rtl.h index ddf798f..2df8713 100644 --- a/include/rtw_ioctl_rtl.h +++ b/include/rtw_ioctl_rtl.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_IOCTL_RTL_H_ #define _RTW_IOCTL_RTL_H_ diff --git a/include/rtw_ioctl_set.h b/include/rtw_ioctl_set.h index 93a8abc..1d252ca 100644 --- a/include/rtw_ioctl_set.h +++ b/include/rtw_ioctl_set.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_IOCTL_SET_H_ #define __RTW_IOCTL_SET_H_ @@ -39,15 +34,15 @@ typedef struct _NDIS_802_11_PMKID { #ifdef PLATFORM_WINDOWS - u8 rtw_set_802_11_reload_defaults(_adapter *padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults); - u8 rtw_set_802_11_test(_adapter *padapter, NDIS_802_11_TEST *test); - u8 rtw_set_802_11_pmkid(_adapter *pdapter, NDIS_802_11_PMKID *pmkid); +u8 rtw_set_802_11_reload_defaults(_adapter *padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults); +u8 rtw_set_802_11_test(_adapter *padapter, NDIS_802_11_TEST *test); +u8 rtw_set_802_11_pmkid(_adapter *pdapter, NDIS_802_11_PMKID *pmkid); - u8 rtw_pnp_set_power_sleep(_adapter *padapter); - u8 rtw_pnp_set_power_wakeup(_adapter *padapter); +u8 rtw_pnp_set_power_sleep(_adapter *padapter); +u8 rtw_pnp_set_power_wakeup(_adapter *padapter); - void rtw_pnp_resume_wk(void *context); - void rtw_pnp_sleep_wk(void *context); +void rtw_pnp_resume_wk(void *context); +void rtw_pnp_sleep_wk(void *context); #endif diff --git a/include/rtw_iol.h b/include/rtw_iol.h index b32e06a..fa35a59 100644 --- a/include/rtw_iol.h +++ b/include/rtw_iol.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_IOL_H_ #define __RTW_IOL_H_ @@ -94,23 +89,21 @@ typedef struct _io_offload_cmd { /* #define IOL_CMD_DELAY_S 0x82 */ #define IOL_CMD_END 0x83 -#if 0 - /* **************************************************** - * CMD Address Value - * (B1) (B2/B3:H/L addr) (B4:B7 : MSB:LSB) - * ****************************************************** - * IOL_CMD_LLT - B7: PGBNDY - * IOL_CMD_R_EFUSE - - */ - IOL_CMD_WB_REG 0x0~0xFFFF B7 - IOL_CMD_WW_REG 0x0~0xFFFF B6~B7 - IOL_CMD_WD_REG 0x0~0xFFFF B4~B7 - /* IOL_CMD_W_RF RF Reg B5~B7 */ - IOL_CMD_DELAY_US - B6~B7 - IOL_CMD_DELAY_MS - B6~B7 - /* IOL_CMD_DELAY_S - B6~B7 */ - IOL_CMD_END - - - /* ***************************************************** */ -#endif +/***************************************************** +CMD Address Value +(B1) (B2/B3:H/L addr) (B4:B7 : MSB:LSB) +****************************************************** +IOL_CMD_LLT - B7: PGBNDY +IOL_CMD_R_EFUSE - - +IOL_CMD_WB_REG 0x0~0xFFFF B7 +IOL_CMD_WW_REG 0x0~0xFFFF B6~B7 +IOL_CMD_WD_REG 0x0~0xFFFF B4~B7 +IOL_CMD_W_RF RF Reg B5~B7 +IOL_CMD_DELAY_US - B6~B7 +IOL_CMD_DELAY_MS - B6~B7 +IOL_CMD_DELAY_S - B6~B7 +IOL_CMD_END - - +******************************************************/ int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value); int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value); int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value); @@ -120,16 +113,16 @@ int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms); #ifdef DBG_IO - int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line); - int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line); - int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line); - #define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) - #define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) - #define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) +int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line); +int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line); +int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line); +#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) +#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) +#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) #else - #define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value)) - #define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value)) - #define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value)) +#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value)) +#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value)) +#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value)) #endif /* DBG_IO */ #endif /* CONFIG_IOL_NEW_GENERATION */ diff --git a/include/rtw_mcc.h b/include/rtw_mcc.h index 177dae3..e73e9cf 100644 --- a/include/rtw_mcc.h +++ b/include/rtw_mcc.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - ******************************************************************************/ + *****************************************************************************/ #ifdef CONFIG_MCC_MODE #ifndef _RTW_MCC_H_ @@ -29,7 +25,6 @@ #define MCC_STATUS_DOING_MCC BIT3 -#define MCC_DURATION 35 /* ms */ #define MCC_SWCH_FW_EARLY_TIME 10 /* ms */ #define MCC_EXPIRE_TIME 50 /* ms */ #define MCC_TOLERANCE_TIME 2 /* 2*2 = 4s */ @@ -88,6 +83,7 @@ enum mcc_status_rpt { MCC_RPT_STOPMCC = 2, MCC_RPT_READY = 3, MCC_RPT_SWICH_CHANNEL_NOTIFY = 7, + MCC_RPT_UPDATE_NOA_START_TIME = 8, MCC_RPT_MAX, }; @@ -115,7 +111,7 @@ struct mcc_adapter_priv { /* flow control */ u8 mcc_tx_stop; /* check if tp stop or not */ u8 mcc_tp_limit; /* check if tp limit or not */ - u32 mcc_target_tx_bytes_to_port; /* customer require */ + u32 mcc_target_tx_bytes_to_port; /* customer require */ u32 mcc_tx_bytes_to_port; /* already tx to tx fifo (write port) */ /* data from kernel to check if enqueue data or netif stop queue */ @@ -132,6 +128,12 @@ struct mcc_adapter_priv { /* set macid bitmap to let fw know which macid should be tx pause */ /* all interface share total 16 macid */ u16 mcc_macid_bitmap; + + /* use for NoA start time (unit: mircoseconds) */ + u32 noa_start_time; + + u8 p2p_go_noa_ie[MAX_P2P_IE_LEN]; + u32 p2p_go_noa_ie_len; }; struct mcc_obj_priv { @@ -142,6 +144,7 @@ struct mcc_obj_priv { u8 mcc_tolerance_time; /* used for detect mcc switch channel success */ u8 mcc_loc_rsvd_paga[MAX_MCC_NUM]; /* mcc rsvd page */ u8 mcc_status; /* mcc status stop or start .... */ + u8 policy_index; u32 mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */ _mutex mcc_mutex; _lock mcc_lock; @@ -150,7 +153,7 @@ struct mcc_obj_priv { }; /* backup IQK val */ -void rtw_hal_mcc_backup_IQK_val(PADAPTER padapter); +void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter); /* check mcc status */ u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status); @@ -174,13 +177,13 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter); /* change some scan flags under site survey */ u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset); -/* record data kernel TX to driver to check MCC concurrent TX */ +/* record data kernel TX to driver to check MCC concurrent TX */ void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len); -/* record data to port to let driver do flow ctrl */ +/* record data to port to let driver do flow ctrl */ void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len); -/* check stop write port or not */ +/* check stop write port or not */ u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter); u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter); @@ -203,5 +206,11 @@ u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg); void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode); +u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len); + +void rtw_hal_mcc_update_switch_channel_policy_table(PADAPTER padapter); + +void rtw_hal_dump_mcc_policy_table(void *sel); + #endif /* _RTW_MCC_H_ */ #endif /* CONFIG_MCC_MODE */ diff --git a/include/rtw_mem.h b/include/rtw_mem.h index ae6049f..229028c 100644 --- a/include/rtw_mem.h +++ b/include/rtw_mem.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_MEM_H__ #define __RTW_MEM_H__ diff --git a/include/rtw_mi.h b/include/rtw_mi.h index ba96805..153aa39 100644 --- a/include/rtw_mi.h +++ b/include/rtw_mi.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_MI_H_ #define __RTW_MI_H_ @@ -24,25 +19,66 @@ void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw); int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset); int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset); -void rtw_mi_status(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num - , u8 *ap_num, u8 *ld_ap_num, u8 *uw_num); -void rtw_mi_status_no_self(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num - , u8 *ap_num, u8 *ld_ap_num, u8 *uw_num); - -void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state); +struct mi_state { + u8 sta_num; /*WIFI_FW_STATION_STATE*/ + u8 ld_sta_num; /*WIFI_FW_STATION_STATE |_FW_LINKED*/ + u8 lg_sta_num; /*WIFI_FW_STATION_STATE |_FW_UNDER_LINKING*/ + u8 ap_num; /*WIFI_FW_AP_STATE|_FW_LINKED*/ + u8 ld_ap_num; /*WIFI_FW_AP_STATE|_FW_LINKED && asoc_sta_count > 2*/ + u8 adhoc_num; /* WIFI_FW_ADHOC_STATE */ + u8 ld_adhoc_num; /* WIFI_FW_ADHOC_STATE && asoc_sta_count > 2 */ + u8 uwps_num; /*WIFI_UNDER_WPS*/ + +#ifdef CONFIG_IOCTL_CFG80211 + #ifdef CONFIG_P2P + u8 roch_num; + #endif + u8 mgmt_tx_num; +#endif + u8 union_ch; + u8 union_bw; + u8 union_offset; +}; -#ifdef CONFIG_MP_INCLUDED - u8 rtw_mi_mp_mode_check(_adapter *padapter); +#define MSTATE_STA_NUM(_mstate) ((_mstate)->sta_num) +#define MSTATE_STA_LD_NUM(_mstate) ((_mstate)->ld_sta_num) +#define MSTATE_STA_LG_NUM(_mstate) ((_mstate)->lg_sta_num) +#define MSTATE_AP_NUM(_mstate) ((_mstate)->ap_num) +#define MSTATE_AP_LD_NUM(_mstate) ((_mstate)->ld_ap_num) +#define MSTATE_ADHOC_NUM(_mstate) ((_mstate)->adhoc_num) +#define MSTATE_ADHOC_LD_NUM(_mstate) ((_mstate)->ld_adhoc_num) +#define MSTATE_WPS_NUM(_mstate) ((_mstate)->uwps_num) + +#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P) +#define MSTATE_ROCH_NUM(_mstate) ((_mstate)->roch_num) +#else +#define MSTATE_ROCH_NUM(_mstate) 0 #endif -#ifdef CONFIG_CONCURRENT_MODE - #define UNDER_SURVEY_T1 1 /*buddy under suvey*/ - #define UNDER_SURVEY_T2 2 /*buddy under suvey by scan_request*/ - u8 rtw_mi_buddy_under_survey(_adapter *padapter); - void rtw_mi_buddy_indicate_scan_done(_adapter *padapter, bool bscan_aborted); +#if defined(CONFIG_IOCTL_CFG80211) +#define MSTATE_MGMT_TX_NUM(_mstate) ((_mstate)->mgmt_tx_num) +#else +#define MSTATE_MGMT_TX_NUM(_mstate) 0 #endif +#define MSTATE_U_CH(_mstate) ((_mstate)->union_ch) +#define MSTATE_U_BW(_mstate) ((_mstate)->union_bw) +#define MSTATE_U_OFFSET(_mstate) ((_mstate)->union_offset) + +#define rtw_mi_get_union_chan(adapter) adapter_to_dvobj(adapter)->iface_state.union_ch +#define rtw_mi_get_union_bw(adapter) adapter_to_dvobj(adapter)->iface_state.union_bw +#define rtw_mi_get_union_offset(adapter) adapter_to_dvobj(adapter)->iface_state.union_offset + +#define rtw_mi_get_assoced_sta_num(adapter) DEV_STA_LD_NUM(adapter_to_dvobj(adapter)) +#define rtw_mi_get_ap_num(adapter) DEV_AP_NUM(adapter_to_dvobj(adapter)) + +/* For now, not return union_ch/bw/offset */ +void rtw_mi_status(_adapter *adapter, struct mi_state *mstate); +void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate); + +void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state); + u8 rtw_mi_netif_stop_queue(_adapter *padapter, bool carrier_off); u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter, bool carrier_off); @@ -74,11 +110,11 @@ void rtw_mi_suspend_free_assoc_resource(_adapter *adapter); void rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter); #ifdef CONFIG_SET_SCAN_DENY_TIMER - void rtw_mi_set_scan_deny(_adapter *adapter, u32 ms); - void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms); +void rtw_mi_set_scan_deny(_adapter *adapter, u32 ms); +void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms); #else - #define rtw_mi_set_scan_deny(adapter, ms) do {} while (0) - #define rtw_mi_buddy_set_scan_deny(adapter, ms) do {} while (0) +#define rtw_mi_set_scan_deny(adapter, ms) do {} while (0) +#define rtw_mi_buddy_set_scan_deny(adapter, ms) do {} while (0) #endif u8 rtw_mi_is_scan_deny(_adapter *adapter); @@ -94,8 +130,8 @@ void rtw_mi_hal_dump_macaddr(_adapter *padapter); void rtw_mi_buddy_hal_dump_macaddr(_adapter *padapter); #ifdef CONFIG_PCI_HCI - void rtw_mi_xmit_tasklet_schedule(_adapter *padapter); - void rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter); +void rtw_mi_xmit_tasklet_schedule(_adapter *padapter); +void rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter); #endif u8 rtw_mi_busy_traffic_check(_adapter *padapter, bool check_sc_interval); @@ -119,17 +155,10 @@ enum { MI_STA_LINKING, }; u8 rtw_mi_check_status(_adapter *adapter, u8 type); -#define rtw_mi_get_union_chan(adapter) adapter_to_dvobj(adapter)->iface_state.union_ch -#define rtw_mi_get_union_bw(adapter) adapter_to_dvobj(adapter)->iface_state.union_bw -#define rtw_mi_get_union_offset(adapter) adapter_to_dvobj(adapter)->iface_state.union_offset - -#define rtw_mi_get_assoced_sta_num(adapter) adapter_to_dvobj(adapter)->iface_state.ld_sta_num -#define rtw_mi_get_ap_num(adapter) adapter_to_dvobj(adapter)->iface_state.ap_num -#define rtw_mi_get_sta_num(adapter) adapter_to_dvobj(adapter)->iface_state.sta_num void dump_dvobj_mi_status(void *sel, const char *fun_name, _adapter *adapter); #ifdef DBG_IFACE_STATUS - #define DBG_IFACE_STATUS_DUMP(adapter) dump_dvobj_mi_status(RTW_DBGDUMP, __func__, adapter) +#define DBG_IFACE_STATUS_DUMP(adapter) dump_dvobj_mi_status(RTW_DBGDUMP, __func__, adapter) #endif void dump_mi_status(void *sel, struct dvobj_priv *dvobj); @@ -137,18 +166,18 @@ u8 rtw_mi_traffic_statistics(_adapter *padapter); u8 rtw_mi_check_miracast_enabled(_adapter *padapter); #ifdef CONFIG_XMIT_THREAD_MODE - u8 rtw_mi_check_pending_xmitbuf(_adapter *padapter); - u8 rtw_mi_buddy_check_pending_xmitbuf(_adapter *padapter); +u8 rtw_mi_check_pending_xmitbuf(_adapter *padapter); +u8 rtw_mi_buddy_check_pending_xmitbuf(_adapter *padapter); #endif #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - #ifdef CONFIG_RTL8822B - #include - #else - extern s32 _dequeue_writeport(PADAPTER padapter); - #endif - u8 rtw_mi_dequeue_writeport(_adapter *padapter); - u8 rtw_mi_buddy_dequeue_writeport(_adapter *padapter); +#ifdef CONFIG_RTL8822B + #include +#else + extern s32 _dequeue_writeport(PADAPTER padapter); +#endif +u8 rtw_mi_dequeue_writeport(_adapter *padapter); +u8 rtw_mi_buddy_dequeue_writeport(_adapter *padapter); #endif void rtw_mi_adapter_reset(_adapter *padapter); @@ -160,7 +189,7 @@ u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter); u8 rtw_mi_dev_unload(_adapter *padapter); u8 rtw_mi_buddy_dev_unload(_adapter *padapter); -extern void dynamic_chk_wk_hdl(_adapter *padapter); +extern void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter); u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter); u8 rtw_mi_buddy_dynamic_chk_wk_hdl(_adapter *padapter); @@ -182,10 +211,10 @@ u8 rtw_mi_set_tx_beacon_cmd(_adapter *padapter); u8 rtw_mi_buddy_set_tx_beacon_cmd(_adapter *padapter); #ifdef CONFIG_P2P - u8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state); - u8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state); - u8 rtw_mi_stay_in_p2p_mode(_adapter *padapter); - u8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter); +u8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state); +u8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state); +u8 rtw_mi_stay_in_p2p_mode(_adapter *padapter); +u8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter); #endif _adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id); @@ -195,10 +224,15 @@ _adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port); void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status); #ifdef CONFIG_PCI_HCI - /*API be create temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/ - _adapter *rtw_mi_get_ap_adapter(_adapter *padapter); +/*API be create temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/ +_adapter *rtw_mi_get_ap_adapter(_adapter *padapter); #endif void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b); +#ifdef CONFIG_AP_MODE +void rtw_mi_ap_acdata_control(_adapter *padapter, u8 power_mode); +void rtw_mi_buddy_ap_acdata_control(_adapter *padapter, u8 power_mode); +#endif /*CONFIG_AP_MODE*/ + #endif /*__RTW_MI_H_*/ diff --git a/include/rtw_mlme.h b/include/rtw_mlme.h index 8f41e09..9880aaf 100644 --- a/include/rtw_mlme.h +++ b/include/rtw_mlme.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_MLME_H_ #define __RTW_MLME_H_ @@ -30,15 +25,18 @@ * Increase the scanning timeout because of increasing the SURVEY_TO value. */ #define SCANNING_TIMEOUT 8000 +#ifdef CONFIG_CHNL_LOAD_MAGT +#define CLM_SCANNING_TIMEOUT 9000 +#endif #ifdef CONFIG_SCAN_BACKOP - #define CONC_SCANNING_TIMEOUT_SINGLE_BAND 10000 - #define CONC_SCANNING_TIMEOUT_DUAL_BAND 15000 +#define CONC_SCANNING_TIMEOUT_SINGLE_BAND 10000 +#define CONC_SCANNING_TIMEOUT_DUAL_BAND 15000 #endif #ifdef PALTFORM_OS_WINCE - #define SCANQUEUE_LIFETIME 12000000 /* unit:us */ +#define SCANQUEUE_LIFETIME 12000000 /* unit:us */ #else - #define SCANQUEUE_LIFETIME 20000 /* 20sec, unit:msec */ +#define SCANQUEUE_LIFETIME 20000 /* 20sec, unit:msec */ #endif #define WIFI_NULL_STATE 0x00000000 @@ -96,23 +94,39 @@ void rtw_wfd_st_switch(struct sta_info *sta, bool on); #define MLME_IS_MONITOR(adapter) (MLME_STATE((adapter)) & WIFI_MONITOR_STATE) #define MLME_IS_MP(adapter) (MLME_STATE((adapter)) & WIFI_MP_STATE) #ifdef CONFIG_P2P + #define MLME_IS_PD(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_DEVICE) #define MLME_IS_GC(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_CLIENT) #define MLME_IS_GO(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_GO) #else /* !CONFIG_P2P */ + #define MLME_IS_PD(adapter) 0 #define MLME_IS_GC(adapter) 0 #define MLME_IS_GO(adapter) 0 #endif /* !CONFIG_P2P */ + +#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P) +#define MLME_IS_ROCH(adapter) (rtw_cfg80211_get_is_roch(adapter) == _TRUE) +#else +#define MLME_IS_ROCH(adapter) 0 +#endif + #define MLME_IS_MSRC(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SOURCE) #define MLME_IS_MSINK(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SINK) -#define MLME_STATE_FMT "%s%s%s%s%s%s%s%s%s%s%s%s%s%s" +#ifdef CONFIG_IOCTL_CFG80211 +#define MLME_IS_MGMT_TX(adapter) rtw_cfg80211_get_is_mgmt_tx(adapter) +#else +#define MLME_IS_MGMT_TX(adapter) 0 +#endif + +#define MLME_STATE_FMT "%s%s%s%s%s%s%s%s%s%s%s%s" #define MLME_STATE_ARG(adapter) \ - MLME_IS_STA((adapter)) ? (MLME_IS_GC((adapter)) ? " GC" : " STA") : "", \ - MLME_IS_AP((adapter)) ? (MLME_IS_GO((adapter)) ? " GO" : " AP") : "", \ - MLME_IS_ADHOC((adapter)) ? " ADHOC" : "", \ - MLME_IS_ADHOC_MASTER((adapter)) ? " ADHOC_M" : "", \ - MLME_IS_MONITOR((adapter)) ? " MONITOR" : "", \ + MLME_IS_STA((adapter)) ? (MLME_IS_GC((adapter)) ? " GC" : " STA") : \ + MLME_IS_AP((adapter)) ? (MLME_IS_GO((adapter)) ? " GO" : " AP") : \ + MLME_IS_ADHOC((adapter)) ? " ADHOC" : \ + MLME_IS_ADHOC_MASTER((adapter)) ? " ADHOC_M" : \ + MLME_IS_MONITOR((adapter)) ? " MONITOR" : \ MLME_IS_MP((adapter)) ? " MP" : "", \ + MLME_IS_PD((adapter)) ? " PD" : "", \ MLME_IS_MSRC((adapter)) ? " MSRC" : "", \ MLME_IS_MSINK((adapter)) ? " MSINK" : "", \ (MLME_STATE((adapter)) & WIFI_SITE_MONITOR) ? " SCAN" : "", \ @@ -120,6 +134,8 @@ void rtw_wfd_st_switch(struct sta_info *sta, bool on); (MLME_STATE((adapter)) & WIFI_ASOC_STATE) ? " ASOC" : "", \ (MLME_STATE((adapter)) & WIFI_OP_CH_SWITCHING) ? " OP_CH_SW" : "", \ (MLME_STATE((adapter)) & WIFI_UNDER_WPS) ? " WPS" : "", \ + MLME_IS_ROCH((adapter)) ? " ROCH" : "", \ + MLME_IS_MGMT_TX((adapter)) ? " MGMT_TX" : "", \ (MLME_STATE((adapter)) & WIFI_SLEEP_STATE) ? " SLEEP" : "" #define _FW_UNDER_LINKING WIFI_UNDER_LINKING @@ -158,7 +174,7 @@ enum SCAN_RESULT_TYPE { SCAN_RESULT_P2P_ONLY = 0, /* Will return all the P2P devices. */ SCAN_RESULT_ALL = 1, /* Will return all the scanned device, include AP. */ SCAN_RESULT_WFD_TYPE = 2 /* Will just return the correct WFD device. */ - /* If this device is Miracast sink device, it will just return all the Miracast source devices. */ + /* If this device is Miracast sink device, it will just return all the Miracast source devices. */ }; /* @@ -180,13 +196,6 @@ SHALL not lock up more than one locks at a time! #define traffic_threshold 10 #define traffic_scan_period 500 -struct sitesurvey_ctrl { - u64 last_tx_pkts; - uint last_rx_pkts; - sint traffic_busy; - _timer sitesurvey_ctrl_timer; -}; - typedef struct _RT_LINK_DETECT_T { u32 NumTxOkInPeriod; u32 NumRxOkInPeriod; @@ -232,20 +241,20 @@ struct wifi_display_info { u16 rtsp_ctrlport; /* TCP port number at which the this WFD device listens for RTSP messages, 0 when WFD disable */ u16 tdls_rtsp_ctrlport; /* rtsp_ctrlport used by tdls, will sync when rtsp_ctrlport is changed by user */ u16 peer_rtsp_ctrlport; /* TCP port number at which the peer WFD device listens for RTSP messages */ - /* This filed should be filled when receiving the gropu negotiation request */ + /* This filed should be filled when receiving the gropu negotiation request */ u8 peer_session_avail; /* WFD session is available or not for the peer wfd device. */ - /* This variable will be set when sending the provisioning discovery request to peer WFD device. */ - /* And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. */ + /* This variable will be set when sending the provisioning discovery request to peer WFD device. */ + /* And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. */ u8 ip_address[4]; u8 peer_ip_address[4]; u8 wfd_pc; /* WFD preferred connection */ - /* 0->Prefer to use the P2P for WFD connection on peer side. */ - /* 1->Prefer to use the TDLS for WFD connection on peer side. */ + /* 0 -> Prefer to use the P2P for WFD connection on peer side. */ + /* 1 -> Prefer to use the TDLS for WFD connection on peer side. */ u8 wfd_device_type; /* WFD Device Type */ - /* 0->WFD Source Device */ - /* 1->WFD Primary Sink Device */ + /* 0 -> WFD Source Device */ + /* 1 -> WFD Primary Sink Device */ enum SCAN_RESULT_TYPE scan_result_type; /* Used when P2P is enable. This parameter will impact the scan result. */ u8 op_wfd_mode; u8 stack_wfd_mode; @@ -264,19 +273,19 @@ struct tx_provdisc_req_info { struct rx_provdisc_req_info { /* When peer device issue prov_disc_req first, we should store the following informations */ u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ u8 strconfig_method_desc_of_prov_disc_req[4]; /* description for the config method located in the provisioning discovery request frame. */ - /* The UI must know this information to know which config method the remote p2p device is requiring. */ + /* The UI must know this information to know which config method the remote p2p device is requiring. */ }; struct tx_nego_req_info { u16 peer_channel_num[2]; /* The channel number which the receiver stands. */ u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ u8 benable; /* This negoitation request frame is trigger to send or not */ - u8 peer_ch; /* The listen channel for peer P2P device */ + u8 peer_ch; /* The listen channel for peer P2P device */ }; struct group_id_info { u8 go_device_addr[ETH_ALEN]; /* The GO's device address of this P2P group */ - u8 ssid[WLAN_SSID_MAXLEN]; /* The SSID of this P2P group */ + u8 ssid[WLAN_SSID_MAXLEN]; /* The SSID of this P2P group */ }; struct scan_limit_info { @@ -297,6 +306,7 @@ struct cfg80211_wifidirect_info { ATOMIC_T ro_ch_cookie_gen; u64 remain_on_ch_cookie; bool is_ro_ch; + struct wireless_dev *ro_ch_wdev; u32 last_ro_ch_time; /* this will be updated at the beginning and end of ro_ch */ }; #endif /* CONFIG_IOCTL_CFG80211 */ @@ -378,32 +388,32 @@ struct wifidirect_info { u8 p2p_group_ssid[WLAN_SSID_MAXLEN]; u8 p2p_group_ssid_len; u8 persistent_supported; /* Flag to know the persistent function should be supported or not. */ - /* In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. */ - /* 0: disable */ - /* 1: enable */ + /* In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. */ + /* 0: disable */ + /* 1: enable */ u8 session_available; /* Flag to set the WFD session available to enable or disable "by Sigma" */ - /* In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. */ - /* 0: disable */ - /* 1: enable */ + /* In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. */ + /* 0: disable */ + /* 1: enable */ u8 wfd_tdls_enable; /* Flag to enable or disable the TDLS by WFD Sigma */ - /* 0: disable */ - /* 1: enable */ + /* 0: disable */ + /* 1: enable */ u8 wfd_tdls_weaksec; /* Flag to enable or disable the weak security function for TDLS by WFD Sigma */ - /* 0: disable */ - /* In this case, the driver can't issue the tdsl setup request frame. */ - /* 1: enable */ - /* In this case, the driver can issue the tdls setup request frame */ - /* even the current security is weak security. */ + /* 0: disable */ + /* In this case, the driver can't issue the tdsl setup request frame. */ + /* 1: enable */ + /* In this case, the driver can issue the tdls setup request frame */ + /* even the current security is weak security. */ enum P2P_WPSINFO ui_got_wps_info; /* This field will store the WPS value (PIN value or PBC) that UI had got from the user. */ u16 supported_wps_cm; /* This field describes the WPS config method which this driver supported. */ - /* The value should be the combination of config method defined in page104 of WPS v2.0 spec. */ + /* The value should be the combination of config method defined in page104 of WPS v2.0 spec. */ u8 external_uuid; /* UUID flag */ u8 uuid[16]; /* UUID */ - uint channel_list_attr_len; /* This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. */ + uint channel_list_attr_len; /* This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. */ u8 channel_list_attr[100]; /* This field will contain the body of P2P Channel List attribute of group negotitation response frame. */ - /* We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. */ + /* We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. */ u8 driver_interface; /* Indicate DRIVER_WEXT or DRIVER_CFG80211 */ #ifdef CONFIG_CONCURRENT_MODE @@ -503,6 +513,65 @@ struct beacon_keys { int group_cipher; int is_8021x; }; +#ifdef CONFIG_RTW_80211R +#define FT_ACTION_REQ_LIMIT 4 + +typedef enum _RTW_WIFI_FT_STA_STATUS { + RTW_FT_UNASSOCIATED_STA = 0, + RTW_FT_AUTHENTICATING_STA, + RTW_FT_AUTHENTICATED_STA, + RTW_FT_ASSOCIATING_STA, + RTW_FT_ASSOCIATED_STA, + RTW_FT_REQUESTING_STA, + RTW_FT_REQUESTED_STA, + RTW_FT_CONFIRMED_STA, + RTW_FT_UNSPECIFIED_STA +} RTW_WIFI_FT_STA_STATUS; + +#define rtw_chk_ft_status(adapter, status) ((adapter)->mlmepriv.ftpriv.ft_status == status) +#define rtw_set_ft_status(adapter, status) \ + do { \ + ((adapter)->mlmepriv.ftpriv.ft_status = status); \ + } while (0) + +#define rtw_reset_ft_status(adapter) \ + do { \ + ((adapter)->mlmepriv.ftpriv.ft_status = RTW_FT_UNASSOCIATED_STA); \ + } while (0) + +typedef enum _RTW_WIFI_FT_CAPABILITY { + RTW_FT_STA_SUPPORTED = BIT0, + RTW_FT_STA_OVER_DS_SUPPORTED = BIT1, + RTW_FT_SUPPORTED = BIT2, + RTW_FT_OVER_DS_SUPPORTED = BIT3, +} RTW_WIFI_FT_CAPABILITY; + +#define rtw_chk_ft_flags(adapter, flags) ((adapter)->mlmepriv.ftpriv.ft_flags & (flags)) +#define rtw_set_ft_flags(adapter, flags) \ + do { \ + ((adapter)->mlmepriv.ftpriv.ft_flags |= (flags)); \ + } while (0) + +#define rtw_clr_ft_flags(adapter, flags) \ + do { \ + ((adapter)->mlmepriv.ftpriv.ft_flags &= ~(flags)); \ + } while (0) + +#define RTW_MAX_FTIE_SZ 256 +typedef struct _ft_priv { + u16 mdid; + u8 ft_cap; /*b0: FT over DS, b1: Resource Req Protocol Cap, b2~b7: Reserved*/ + u8 updated_ft_ies[RTW_MAX_FTIE_SZ]; + u16 updated_ft_ies_len; + u8 ft_action[RTW_MAX_FTIE_SZ]; + u16 ft_action_len; + struct cfg80211_ft_event_params ft_event; + u8 ft_roam_on_expired; + u8 ft_flags; + u32 ft_status; + u32 ft_req_retry_cnt; +} ft_priv; +#endif struct mlme_priv { @@ -518,13 +587,12 @@ struct mlme_priv { u32 roam_scan_int_ms; /* scan interval for active roam */ u32 roam_scanr_exp_ms; /* scan result expire time in ms for roam */ u8 roam_tgt_addr[ETH_ALEN]; /* request to roam to speicific target without other consideration */ + u8 roam_rssi_threshold; + bool need_to_roam; #endif u8 *nic_hdl; -#ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 - u8 not_indic_disco; -#endif _list *pscanned; _queue free_bss_pool; _queue scanned_queue; @@ -545,6 +613,7 @@ struct mlme_priv { #ifdef CONFIG_ARP_KEEP_ALIVE /* for arp offload keep alive */ u8 bGetGateway; + u8 GetGatewayTryCnt; u8 gw_mac_addr[6]; u8 gw_ip[4]; #endif @@ -587,11 +656,11 @@ struct mlme_priv { struct vht_priv vhtpriv; #endif #ifdef CONFIG_BEAMFORMING -#if (BEAMFORMING_SUPPORT == 0)/*for driver beamforming*/ #ifndef RTW_BEAMFORMING_VERSION_2 +#if (BEAMFORMING_SUPPORT == 0)/*for driver beamforming*/ struct beamforming_info beamforming_info; -#endif /* !RTW_BEAMFORMING_VERSION_2 */ #endif +#endif /* !RTW_BEAMFORMING_VERSION_2 */ #endif #ifdef CONFIG_DFS @@ -601,13 +670,13 @@ struct mlme_priv { /* TODO: move to rfctl */ _timer dfs_master_timer; #endif +#ifdef CONFIG_RTW_80211R + ft_priv ftpriv; +#endif RT_LINK_DETECT_T LinkDetectInfo; - _timer dynamic_chk_timer; /* dynamic/periodic check timer */ u8 acm_mask; /* for wmm acm mask */ - const struct country_chplan *country_ent; - u8 ChannelPlan; RT_SCAN_TYPE scan_mode; /* active: 1, passive: 0 */ u8 *wps_probe_req_ie; @@ -627,7 +696,7 @@ struct mlme_priv { /* Number of associated stations that do not support Short Preamble */ int num_sta_no_short_preamble; - int olbc; /* Overlapping Legacy BSS Condition (Legacy b/g)*/ + ATOMIC_T olbc; /* Overlapping Legacy BSS Condition (Legacy b/g)*/ /* Number of HT associated stations that do not support greenfield */ int num_sta_ht_no_gf; @@ -642,7 +711,7 @@ struct mlme_priv { int num_sta_40mhz_intolerant; /* Overlapping BSS information */ - int olbc_ht; + ATOMIC_T olbc_ht; #ifdef CONFIG_80211N_HT int ht_20mhz_width_req; @@ -651,33 +720,44 @@ struct mlme_priv { u8 sw_to_20mhz; /*switch to 20Mhz BW*/ #endif /* CONFIG_80211N_HT */ +#ifdef CONFIG_RTW_80211R + u8 *auth_rsp; + u32 auth_rsp_len; +#endif u8 *assoc_req; u32 assoc_req_len; + u8 *assoc_rsp; u32 assoc_rsp_len; - u8 *wps_beacon_ie; /* u8 *wps_probe_req_ie; */ - u8 *wps_probe_resp_ie; - u8 *wps_assoc_resp_ie; /* for CONFIG_IOCTL_CFG80211, this IE could include p2p ie / wfd ie */ + /* u32 wps_probe_req_ie_len; */ + u8 *wps_beacon_ie; u32 wps_beacon_ie_len; - /* u32 wps_probe_req_ie_len; */ + + u8 *wps_probe_resp_ie; u32 wps_probe_resp_ie_len; - u32 wps_assoc_resp_ie_len; /* for CONFIG_IOCTL_CFG80211, this IE len could include p2p ie / wfd ie */ - u8 *p2p_beacon_ie; - u8 *p2p_probe_req_ie; - u8 *p2p_probe_resp_ie; - u8 *p2p_go_probe_resp_ie; /* for GO */ - u8 *p2p_assoc_req_ie; - u8 *p2p_assoc_resp_ie; + u8 *wps_assoc_resp_ie; + u32 wps_assoc_resp_ie_len; + u8 *p2p_beacon_ie; u32 p2p_beacon_ie_len; + + u8 *p2p_probe_req_ie; u32 p2p_probe_req_ie_len; + + u8 *p2p_probe_resp_ie; u32 p2p_probe_resp_ie_len; - u32 p2p_go_probe_resp_ie_len; /* for GO */ + + u8 *p2p_go_probe_resp_ie; /* for GO */ + u32 p2p_go_probe_resp_ie_len; /* for GO */ + + u8 *p2p_assoc_req_ie; u32 p2p_assoc_req_ie_len; + + u8 *p2p_assoc_resp_ie; u32 p2p_assoc_resp_ie_len; _lock bcn_update_lock; @@ -689,21 +769,23 @@ struct mlme_priv { #endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ #if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) - u8 *wfd_beacon_ie; - u8 *wfd_probe_req_ie; - u8 *wfd_probe_resp_ie; - u8 *wfd_go_probe_resp_ie; /* for GO */ - u8 *wfd_assoc_req_ie; - u8 *wfd_assoc_resp_ie; - u32 wfd_beacon_ie_len; + + u8 *wfd_probe_req_ie; u32 wfd_probe_req_ie_len; + + u8 *wfd_probe_resp_ie; u32 wfd_probe_resp_ie_len; - u32 wfd_go_probe_resp_ie_len; /* for GO */ + + u8 *wfd_go_probe_resp_ie; /* for GO */ + u32 wfd_go_probe_resp_ie_len; /* for GO */ + + u8 *wfd_assoc_req_ie; u32 wfd_assoc_req_ie_len; - u32 wfd_assoc_resp_ie_len; + u8 *wfd_assoc_resp_ie; + u32 wfd_assoc_resp_ie_len; #endif #ifdef RTK_DMP_PLATFORM @@ -736,15 +818,17 @@ struct mlme_priv { u16 p2p_sdt_cid[MAX_NUM_P2P_SDT]; u16 p2p_sdt_scid[MAX_NUM_P2P_SDT]; u8 p2p_reject_disable; /* When starting NL80211 wpa_supplicant/hostapd, it will call netdev_close */ - /* such that it will cause p2p disabled. Use this flag to reject. */ + /* such that it will cause p2p disabled. Use this flag to reject. */ #endif /* CONFIG_INTEL_WIDI */ u32 lastscantime; #ifdef CONFIG_CONCURRENT_MODE u8 scanning_via_buddy_intf; #endif - /* u8 NumOfBcnInfoChkFail; - * u32 timeBcnInfoChkStart; */ +#if 0 + u8 NumOfBcnInfoChkFail; + u32 timeBcnInfoChkStart; +#endif #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE u32 vendor_ie_mask[WLAN_MAX_VENDOR_IE_NUM]; @@ -799,10 +883,12 @@ extern void rtw_atimdone_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf); #ifdef CONFIG_IEEE80211W - void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf); +void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf); #endif /* CONFIG_IEEE80211W */ -extern void rtw_join_timeout_handler(RTW_TIMER_HDL_ARGS); -extern void _rtw_scan_timeout_handler(RTW_TIMER_HDL_ARGS); +#ifdef CONFIG_RTW_80211R +void rtw_update_ft_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork); +void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf); +#endif thread_return event_thread(thread_context context); @@ -826,7 +912,7 @@ __inline static u8 *get_bssid(struct mlme_priv *pmlmepriv) __inline static sint check_fwstate(struct mlme_priv *pmlmepriv, sint state) { if ((state == WIFI_NULL_STATE) && - (pmlmepriv->fw_state == WIFI_NULL_STATE)) + (pmlmepriv->fw_state == WIFI_NULL_STATE)) return _TRUE; if (pmlmepriv->fw_state & state) @@ -950,20 +1036,21 @@ extern void rtw_update_registrypriv_dev_network(_adapter *adapter); extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter); -extern void _rtw_join_timeout_handler(_adapter *adapter); -extern void rtw_scan_timeout_handler(_adapter *adapter); +extern void rtw_join_timeout_handler(void *ctx); +extern void rtw_scan_timeout_handler(void *ctx); + +extern void rtw_dynamic_check_timer_handlder(void *ctx); +extern void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter); -extern void rtw_dynamic_check_timer_handlder(_adapter *adapter); #ifdef CONFIG_SET_SCAN_DENY_TIMER - bool rtw_is_scan_deny(_adapter *adapter); - void rtw_clear_scan_deny(_adapter *adapter); - void rtw_set_scan_deny_timer_hdl(_adapter *adapter); - void rtw_set_scan_deny(_adapter *adapter, u32 ms); +bool rtw_is_scan_deny(_adapter *adapter); +void rtw_clear_scan_deny(_adapter *adapter); +void rtw_set_scan_deny_timer_hdl(void *ctx); +void rtw_set_scan_deny(_adapter *adapter, u32 ms); #else - #define rtw_is_scan_deny(adapter) _FALSE - #define rtw_clear_scan_deny(adapter) do {} while (0) - #define rtw_set_scan_deny_timer_hdl(adapter) do {} while (0) - #define rtw_set_scan_deny(adapter, ms) do {} while (0) +#define rtw_is_scan_deny(adapter) _FALSE +#define rtw_clear_scan_deny(adapter) do {} while (0) +#define rtw_set_scan_deny(adapter, ms) do {} while (0) #endif void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv); @@ -976,7 +1063,7 @@ void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv); #define MLME_ASSOC_RESP_IE 5 #if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) - int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_len); +int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_len); #endif @@ -1005,12 +1092,12 @@ u8 *rtw_get_beacon_interval_from_ie(u8 *ie); void rtw_joinbss_reset(_adapter *padapter); #ifdef CONFIG_80211N_HT - void rtw_ht_use_default_setting(_adapter *padapter); - void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len); - unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel); - void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel); - void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe); - void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len); +void rtw_ht_use_default_setting(_adapter *padapter); +void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len); +unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel); +void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel); +void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe); +void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len); #endif int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork); @@ -1066,9 +1153,9 @@ u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool co void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm); #ifdef CONFIG_INTEL_PROXIM - void rtw_proxim_enable(_adapter *padapter); - void rtw_proxim_disable(_adapter *padapter); - void rtw_proxim_send_packet(_adapter *padapter, u8 *pbuf, u16 len, u8 hw_rate); +void rtw_proxim_enable(_adapter *padapter); +void rtw_proxim_disable(_adapter *padapter); +void rtw_proxim_send_packet(_adapter *padapter, u8 *pbuf, u16 len, u8 m_rate); #endif /* CONFIG_INTEL_PROXIM */ #define IPV4_SRC(_iphdr) (((u8 *)(_iphdr)) + 12) diff --git a/include/rtw_mlme_ext.h b/include/rtw_mlme_ext.h index 58a7129..2871f97 100644 --- a/include/rtw_mlme_ext.h +++ b/include/rtw_mlme_ext.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_MLME_EXT_H_ #define __RTW_MLME_EXT_H_ @@ -26,11 +21,14 @@ * The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. * So, this driver tried to extend the dwell time for each scanning channel. * This will increase the chance to receive the probe response from SoftAP. */ - -#define SURVEY_TO (150) +#ifdef CONFIG_CHNL_LOAD_MAGT + #define SURVEY_TO (200) +#else + #define SURVEY_TO (100) +#endif #define REAUTH_TO (300) /* (50) */ -#define REASSOC_TO (300) /* (50) - * #define DISCONNECT_TO (3000) */ +#define REASSOC_TO (300) /* (50) */ +/* #define DISCONNECT_TO (3000) */ #define ADDBA_TO (2000) #define LINKED_TO (1) /* unit:2 sec, 1x2 = 2 sec */ @@ -129,6 +127,7 @@ typedef enum _RT_CHANNEL_DOMAIN { RTW_CHPLAN_WORLD_KCC1 = 0x28, RTW_CHPLAN_WORLD_FCC2 = 0x29, RTW_CHPLAN_FCC2_NULL = 0x2A, + RTW_CHPLAN_IC1_IC2 = 0x2B, RTW_CHPLAN_WORLD_FCC3 = 0x30, RTW_CHPLAN_WORLD_FCC4 = 0x31, RTW_CHPLAN_WORLD_FCC5 = 0x32, @@ -160,6 +159,30 @@ typedef enum _RT_CHANNEL_DOMAIN { RTW_CHPLAN_MKK2_MKK4 = 0x58, RTW_CHPLAN_WORLD_ETSI14 = 0x59, RTW_CHPLAN_FCC1_FCC5 = 0x60, + RTW_CHPLAN_FCC2_FCC7 = 0x61, + RTW_CHPLAN_FCC2_FCC1 = 0x62, + RTW_CHPLAN_WORLD_ETSI15 = 0x63, + RTW_CHPLAN_MKK2_MKK5 = 0x64, + RTW_CHPLAN_ETSI1_ETSI16 = 0x65, + RTW_CHPLAN_FCC1_FCC14 = 0x66, + RTW_CHPLAN_FCC1_FCC12 = 0x67, + RTW_CHPLAN_FCC2_FCC14 = 0x68, + RTW_CHPLAN_FCC2_FCC12 = 0x69, + RTW_CHPLAN_ETSI1_ETSI17 = 0x6A, + RTW_CHPLAN_WORLD_FCC16 = 0x6B, + RTW_CHPLAN_WORLD_FCC13 = 0x6C, + RTW_CHPLAN_FCC2_FCC15 = 0x6D, + RTW_CHPLAN_WORLD_FCC12 = 0x6E, + RTW_CHPLAN_NULL_ETSI8 = 0x6F, + RTW_CHPLAN_NULL_ETSI18 = 0x70, + RTW_CHPLAN_NULL_ETSI17 = 0x71, + RTW_CHPLAN_NULL_ETSI19 = 0x72, + RTW_CHPLAN_WORLD_FCC7 = 0x73, + RTW_CHPLAN_FCC2_FCC17 = 0x74, + RTW_CHPLAN_WORLD_ETSI20 = 0x75, + RTW_CHPLAN_FCC2_FCC11 = 0x76, + RTW_CHPLAN_WORLD_ETSI21 = 0x77, + RTW_CHPLAN_FCC1_FCC18 = 0x78, RTW_CHPLAN_MAX, RTW_CHPLAN_REALTEK_DEFINE = 0x7F, @@ -175,6 +198,7 @@ typedef enum _RT_CHANNEL_DOMAIN_2G { RTW_RD_2G_GLOBAL = 6, /* Global domain */ RTW_RD_2G_MKK2 = 7, /* Japan */ RTW_RD_2G_FCC2 = 8, /* US */ + RTW_RD_2G_IC1 = 9, /* Canada */ RTW_RD_2G_MAX, } RT_CHANNEL_DOMAIN_2G, *PRT_CHANNEL_DOMAIN_2G; @@ -190,30 +214,49 @@ typedef enum _RT_CHANNEL_DOMAIN_5G { RTW_RD_5G_FCC4 = 7, /* Venezuela */ RTW_RD_5G_FCC5 = 8, /* China */ RTW_RD_5G_FCC6 = 9, /* */ - RTW_RD_5G_FCC7 = 10, /* US Canada(w/o Weather radar) */ - RTW_RD_5G_KCC1 = 11, /* Korea */ - RTW_RD_5G_MKK1 = 12, /* Japan */ - RTW_RD_5G_MKK2 = 13, /* Japan (W52, W53) */ - RTW_RD_5G_MKK3 = 14, /* Japan (W56) */ - RTW_RD_5G_NCC1 = 15, /* Taiwan, (w/o Weather radar) */ - RTW_RD_5G_NCC2 = 16, /* Taiwan, Band2, Band4 */ - RTW_RD_5G_NCC3 = 17, /* Taiwan w/o DFS, Band4 only */ - RTW_RD_5G_ETSI4 = 18, /* Europe w/o DFS, Band1 only */ - RTW_RD_5G_ETSI5 = 19, /* Australia, New Zealand(w/o Weather radar) */ - RTW_RD_5G_FCC8 = 20, /* Latin America */ - RTW_RD_5G_ETSI6 = 21, /* Israel, Bahrain, Egypt, India, China, Malaysia */ - RTW_RD_5G_ETSI7 = 22, /* China */ - RTW_RD_5G_ETSI8 = 23, /* Jordan */ - RTW_RD_5G_ETSI9 = 24, /* Lebanon */ - RTW_RD_5G_ETSI10 = 25, /* Qatar */ - RTW_RD_5G_ETSI11 = 26, /* Russia */ - RTW_RD_5G_NCC4 = 27, /* Taiwan, (w/o Weather radar) */ - RTW_RD_5G_ETSI12 = 28, /* Indonesia */ - RTW_RD_5G_FCC9 = 29, /* (w/o Weather radar) */ - RTW_RD_5G_ETSI13 = 30, /* (w/o Weather radar) */ - RTW_RD_5G_FCC10 = 31, /* Argentina(w/o Weather radar) */ - RTW_RD_5G_MKK4 = 32, /* Japan (W52) */ - RTW_RD_5G_ETSI14 = 33, /* Russia */ + RTW_RD_5G_FCC7 = 10, /* US(w/o Weather radar) */ + RTW_RD_5G_IC1 = 11, /* Canada(w/o Weather radar) */ + RTW_RD_5G_KCC1 = 12, /* Korea */ + RTW_RD_5G_MKK1 = 13, /* Japan */ + RTW_RD_5G_MKK2 = 14, /* Japan (W52, W53) */ + RTW_RD_5G_MKK3 = 15, /* Japan (W56) */ + RTW_RD_5G_NCC1 = 16, /* Taiwan, (w/o Weather radar) */ + RTW_RD_5G_NCC2 = 17, /* Taiwan, Band2, Band4 */ + RTW_RD_5G_NCC3 = 18, /* Taiwan w/o DFS, Band4 only */ + RTW_RD_5G_ETSI4 = 19, /* Europe w/o DFS, Band1 only */ + RTW_RD_5G_ETSI5 = 20, /* Australia, New Zealand(w/o Weather radar) */ + RTW_RD_5G_FCC8 = 21, /* Latin America */ + RTW_RD_5G_ETSI6 = 22, /* Israel, Bahrain, Egypt, India, China, Malaysia */ + RTW_RD_5G_ETSI7 = 23, /* China */ + RTW_RD_5G_ETSI8 = 24, /* Jordan */ + RTW_RD_5G_ETSI9 = 25, /* Lebanon */ + RTW_RD_5G_ETSI10 = 26, /* Qatar */ + RTW_RD_5G_ETSI11 = 27, /* Russia */ + RTW_RD_5G_NCC4 = 28, /* Taiwan, (w/o Weather radar) */ + RTW_RD_5G_ETSI12 = 29, /* Indonesia */ + RTW_RD_5G_FCC9 = 30, /* (w/o Weather radar) */ + RTW_RD_5G_ETSI13 = 31, /* (w/o Weather radar) */ + RTW_RD_5G_FCC10 = 32, /* Argentina(w/o Weather radar) */ + RTW_RD_5G_MKK4 = 33, /* Japan (W52) */ + RTW_RD_5G_ETSI14 = 34, /* Russia */ + RTW_RD_5G_FCC11 = 35, /* US(include CH144) */ + RTW_RD_5G_ETSI15 = 36, /* Malaysia */ + RTW_RD_5G_MKK5 = 37, /* Japan */ + RTW_RD_5G_ETSI16 = 38, /* Europe */ + RTW_RD_5G_ETSI17 = 39, /* Europe */ + RTW_RD_5G_FCC12 = 40, /* FCC */ + RTW_RD_5G_FCC13 = 41, /* FCC */ + RTW_RD_5G_FCC14 = 42, /* FCC w/o Weather radar(w/o 5600~5650MHz) */ + RTW_RD_5G_FCC15 = 43, /* FCC w/o Band3 */ + RTW_RD_5G_FCC16 = 44, /* FCC w/o Band3 */ + RTW_RD_5G_ETSI18 = 45, /* ETSI w/o DFS Band2&3 */ + RTW_RD_5G_ETSI19 = 46, /* Europe */ + RTW_RD_5G_FCC17 = 47, /* FCC w/o Weather radar(w/o 5600~5650MHz) */ + RTW_RD_5G_ETSI20 = 48, /* Europe */ + RTW_RD_5G_IC2 = 49, /* Canada(w/o Weather radar), include ch144 */ + RTW_RD_5G_ETSI21 = 50, /* Australia, New Zealand(w/o Weather radar) */ + RTW_RD_5G_FCC18 = 51, /* */ + RTW_RD_5G_WORLD = 52, /* Worldwide */ /* === Below are driver defined for legacy channel plan compatible, DON'T assign index ==== */ RTW_RD_5G_OLD_FCC1, @@ -232,22 +275,30 @@ typedef struct _RT_CHANNEL_PLAN { unsigned char Len; } RT_CHANNEL_PLAN, *PRT_CHANNEL_PLAN; -typedef struct _RT_CHANNEL_PLAN_2G { - unsigned char Channel[MAX_CHANNEL_NUM_2G]; - unsigned char Len; -} RT_CHANNEL_PLAN_2G, *PRT_CHANNEL_PLAN_2G; +struct ch_list_t { + u8 *len_ch; +}; -typedef struct _RT_CHANNEL_PLAN_5G { - unsigned char Channel[MAX_CHANNEL_NUM_5G]; - unsigned char Len; -} RT_CHANNEL_PLAN_5G, *PRT_CHANNEL_PLAN_5G; +#define CH_LIST_ENT(_len, arg...) \ + {.len_ch = (u8[_len + 1]) {_len, ##arg}, } + +#define CH_LIST_LEN(_ch_list) (_ch_list.len_ch[0]) +#define CH_LIST_CH(_ch_list, _i) (_ch_list.len_ch[_i + 1]) typedef struct _RT_CHANNEL_PLAN_MAP { u8 Index2G; +#ifdef CONFIG_IEEE80211_BAND_5GHZ u8 Index5G; +#endif u8 regd; /* value of REGULATION_TXPWR_LMT */ } RT_CHANNEL_PLAN_MAP, *PRT_CHANNEL_PLAN_MAP; +#ifdef CONFIG_IEEE80211_BAND_5GHZ +#define CHPLAN_ENT(i2g, i5g, regd) {i2g, i5g, regd} +#else +#define CHPLAN_ENT(i2g, i5g, regd) {i2g, regd} +#endif + enum Associated_AP { atherosAP = 0, broadcomAP = 1, @@ -333,10 +384,15 @@ struct ss_res { u8 next_state; /* will set to state on next cmd hdl */ int bss_cnt; int channel_idx; +#ifdef CONFIG_DFS + u8 dfs_ch_ssid_scan; +#endif int scan_mode; u16 scan_ch_ms; u8 rx_ampdu_accept; u8 rx_ampdu_size; + u8 igi_scan; + u8 igi_before_scan; /* used for restoring IGI value without enable DIG & FA_CNT */ #ifdef CONFIG_SCAN_BACKOP u8 backop_flags_sta; /* policy for station mode*/ u8 backop_flags_ap; /* policy for ap mode */ @@ -365,6 +421,7 @@ struct ss_res { #define WIFI_FW_AP_STATE _HW_STATE_AP_ #define WIFI_FW_ADHOC_STATE _HW_STATE_ADHOC_ +#define WIFI_FW_PRE_LINK 0x00000800 #define WIFI_FW_AUTH_NULL 0x00000100 #define WIFI_FW_AUTH_STATE 0x00000200 #define WIFI_FW_AUTH_SUCCESS 0x00000400 @@ -420,6 +477,9 @@ enum TDLS_option { #define RTW_BACK_OP_CH_MS 400 #endif +#define RTW_IP_ADDR_LEN 4 +#define RTW_IPv6_ADDR_LEN 16 + struct mlme_ext_info { u32 state; #ifdef CONFIG_MI_WITH_MBSSID_CAM @@ -461,6 +521,9 @@ struct mlme_ext_info { u8 hidden_ssid_mode; u8 VHT_enable; + u8 ip_addr[RTW_IP_ADDR_LEN]; + u8 ip6_addr[RTW_IPv6_ADDR_LEN]; + struct ADDBA_request ADDBA_req; struct WMM_para_element WMM_param; struct HT_caps_element HT_caps; @@ -478,8 +541,11 @@ typedef struct _RT_CHANNEL_INFO { #ifdef CONFIG_FIND_BEST_CHANNEL u32 rx_count; #endif -#ifdef CONFIG_DFS_MASTER +#ifdef CONFIG_DFS + #ifdef CONFIG_DFS_MASTER u32 non_ocp_end_time; + #endif + u8 hidden_bss_cnt; /* per scan count */ #endif } RT_CHANNEL_INFO, *PRT_CHANNEL_INFO; @@ -488,25 +554,28 @@ typedef struct _RT_CHANNEL_INFO { #define CAC_TIME_CE_MS (10*60*1000) #define NON_OCP_TIME_MS (30*60*1000) +#ifdef CONFIG_TXPWR_LIMIT +void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl); +#endif void rtw_rfctl_init(_adapter *adapter); +void rtw_rfctl_deinit(_adapter *adapter); #ifdef CONFIG_DFS_MASTER - struct rf_ctl_t; - #define CH_IS_NON_OCP(rt_ch_info) (time_after((unsigned long)(rt_ch_info)->non_ocp_end_time, (unsigned long)rtw_get_current_time())) - bool rtw_is_cac_reset_needed(_adapter *adapter, u8 ch, u8 bw, u8 offset); - bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset); - bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl); - bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl); - bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); - void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); - void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms); - u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms); - void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset); - bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset, u8 d_flags); +struct rf_ctl_t; +#define CH_IS_NON_OCP(rt_ch_info) (time_after((unsigned long)(rt_ch_info)->non_ocp_end_time, (unsigned long)rtw_get_current_time())) +bool rtw_is_cac_reset_needed(_adapter *adapter, u8 ch, u8 bw, u8 offset); +bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset); +bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl); +bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl); +bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); +void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); +void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms); +u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms); +void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset); #else - #define CH_IS_NON_OCP(rt_ch_info) 0 - #define rtw_chset_is_ch_non_ocp(ch_set, ch, bw, offset) _FALSE - #define rtw_rfctl_is_tx_blocked_by_ch_waiting(rfctl) _FALSE +#define CH_IS_NON_OCP(rt_ch_info) 0 +#define rtw_chset_is_ch_non_ocp(ch_set, ch, bw, offset) _FALSE +#define rtw_rfctl_is_tx_blocked_by_ch_waiting(rfctl) _FALSE #endif enum { @@ -518,6 +587,9 @@ enum { RTW_CHF_NON_LONG_CAC = BIT5, RTW_CHF_NON_OCP = BIT6, }; + +bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset, u8 d_flags); + void dump_country_chplan(void *sel, const struct country_chplan *ent); void dump_country_chplan_map(void *sel); void dump_chplan_id_list(void *sel); @@ -525,7 +597,7 @@ void dump_chplan_test(void *sel); void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set); void dump_cur_chset(void *sel, _adapter *adapter); -int rtw_ch_set_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch); +int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch); u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); bool rtw_mlme_band_check(_adapter *adapter, const u32 ch); @@ -591,9 +663,6 @@ struct mlme_ext_priv { unsigned char cur_ch_offset;/* PRIME_CHNL_OFFSET */ unsigned char cur_wireless_mode; /* NETWORK_TYPE */ - unsigned char max_chan_nums; - RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM]; - struct p2p_channels channel_list; unsigned char basicrate[NumRates]; unsigned char datarate[NumRates]; #ifdef CONFIG_80211N_HT @@ -605,8 +674,11 @@ struct mlme_ext_priv { * for ap mode, network includes ap's cap_info */ _timer survey_timer; _timer link_timer; +#ifdef CONFIG_RTW_80211R + _timer ft_link_timer; + _timer ft_roam_timer; +#endif - /* _timer ADDBA_timer; */ u32 last_scan_time; u8 scan_abort; u8 tx_rate; /* TXRATE when USERATE is set. */ @@ -710,16 +782,14 @@ void init_mlme_default_rate_set(_adapter *padapter); int init_mlme_ext_priv(_adapter *padapter); int init_hw_mlme_ext(_adapter *padapter); void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext); -extern void init_mlme_ext_timer(_adapter *padapter); -extern void init_addba_retry_timer(_adapter *padapter, struct sta_info *psta); extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv); struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv); /* void fill_fwpriv(_adapter * padapter, struct fw_priv *pfwpriv); */ - +#ifdef CONFIG_GET_RAID_BY_DRV unsigned char networktype_to_raid(_adapter *adapter, struct sta_info *psta); unsigned char networktype_to_raid_ex(_adapter *adapter, struct sta_info *psta); - +#endif u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen); void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len); void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask); @@ -743,8 +813,6 @@ u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset); u8 rtw_get_offset_by_ch(u8 channel); void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode); -void SelectChannel(_adapter *padapter, unsigned char channel); -void SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset); unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval); @@ -752,6 +820,7 @@ void _clear_cam_entry(_adapter *padapter, u8 entry); void write_cam_from_cache(_adapter *adapter, u8 id); void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b); void rtw_clean_dk_section(_adapter *adapter); +void rtw_clean_hw_dk_cam(_adapter *adapter); /* modify both HW and cache */ void write_cam(_adapter *padapter, u8 id, u16 ctrl, u8 *mac, u8 *key); @@ -784,8 +853,8 @@ unsigned char check_assoc_AP(u8 *pframe, uint len); int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); #ifdef CONFIG_WFD - void rtw_process_wfd_ie(_adapter *adapter, u8 *ie, u8 ie_len, const char *tag); - void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag); +void rtw_process_wfd_ie(_adapter *adapter, u8 *ie, u8 ie_len, const char *tag); +void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag); #endif void WMMOnAssocRsp(_adapter *padapter); @@ -798,12 +867,13 @@ void VCS_update(_adapter *padapter, struct sta_info *psta); void update_ldpc_stbc_cap(struct sta_info *psta); int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len, - struct beacon_keys *recv_beacon); + struct beacon_keys *recv_beacon); +int validate_beacon_len(u8 *pframe, uint len); void rtw_dump_bcn_keys(struct beacon_keys *recv_beacon); int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len); void update_beacon_info(_adapter *padapter, u8 *pframe, uint len, struct sta_info *psta); #ifdef CONFIG_DFS - void process_csa_ie(_adapter *padapter, u8 *pframe, uint len); +void process_csa_ie(_adapter *padapter, u8 *pframe, uint len); #endif /* CONFIG_DFS */ void update_capinfo(PADAPTER Adapter, u16 updateCap); void update_wireless_mode(_adapter *padapter); @@ -815,7 +885,6 @@ int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num void update_sta_info(_adapter *padapter, struct sta_info *psta); unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz); unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz); -unsigned int update_MCS_rate(struct HT_caps_element *pHT_caps); void Update_RA_Entry(_adapter *padapter, struct sta_info *psta); void set_sta_rate(_adapter *padapter, struct sta_info *psta); @@ -857,6 +926,10 @@ void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta); void rtw_release_macid(_adapter *padapter, struct sta_info *psta); u8 rtw_search_max_mac_id(_adapter *padapter); void rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr); +void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw); +void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en); +void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp); +void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp); void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl); void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl); u8 rtw_iface_bcmc_id_get(_adapter *padapter); @@ -883,17 +956,20 @@ s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntfram s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms); #ifdef CONFIG_P2P - void issue_probersp_p2p(_adapter *padapter, unsigned char *da); - void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr); - void issue_p2p_GO_request(_adapter *padapter, u8 *raddr); - void issue_probereq_p2p(_adapter *padapter, u8 *da); - int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms); - void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 success); - void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr); +int get_reg_classes_full_count(struct p2p_channels *channel_list); +void issue_probersp_p2p(_adapter *padapter, unsigned char *da); +void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr); +void issue_p2p_GO_request(_adapter *padapter, u8 *raddr); +void issue_probereq_p2p(_adapter *padapter, u8 *da); +int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms); +void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 success); +void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr); #endif /* CONFIG_P2P */ void issue_beacon(_adapter *padapter, int timeout_ms); void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq); +void _issue_assocreq(_adapter *padapter, u8 is_assoc); void issue_assocreq(_adapter *padapter); +void issue_reassocreq(_adapter *padapter); void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type); void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status); void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da); @@ -911,9 +987,8 @@ void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 i int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator, int try_cnt, int wait_ms); #ifdef CONFIG_IEEE80211W - void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type); - int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type); - extern void init_dot11w_expire_timer(_adapter *padapter, struct sta_info *psta); +void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type); +int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type); #endif /* CONFIG_IEEE80211W */ int issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoPsMode); int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms); @@ -945,6 +1020,9 @@ unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame); unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame); +#ifdef CONFIG_RTW_WNM +unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe); +#endif #define RX_AMPDU_ACCEPT_INVALID 0xFF #define RX_AMPDU_SIZE_INVALID 0xFF @@ -959,20 +1037,29 @@ bool rtw_rx_ampdu_is_accept(_adapter *adapter); bool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason); bool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason); u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size); +u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta); u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size); u16 rtw_rx_ampdu_apply(_adapter *adapter); unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame); unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame); #ifdef CONFIG_IEEE80211W - unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame); #endif /* CONFIG_IEEE80211W */ unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame); - +#ifdef CONFIG_RTW_80211R +void start_clnt_ft_action(_adapter *padapter, u8 *pTargetAddr); +void issue_action_ft_request(_adapter *padapter, u8 *pTargetAddr); +void report_ft_event(_adapter *padapter); +void report_ft_reassoc_event(_adapter *padapter, u8 *pMacAddr); +void ft_link_timer_hdl(void *ctx); +void ft_roam_timer_hdl(void *ctx); +#endif void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res); void mlmeext_sta_del_event_callback(_adapter *padapter); void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta); @@ -981,14 +1068,16 @@ void linked_status_chk(_adapter *padapter, u8 from_timer); void _linked_info_dump(_adapter *padapter); -void survey_timer_hdl(_adapter *padapter); -void link_timer_hdl(_adapter *padapter); -void addba_timer_hdl(struct sta_info *psta); +void survey_timer_hdl(void *ctx); +void link_timer_hdl(void *ctx); +void addba_timer_hdl(void *ctx); #ifdef CONFIG_IEEE80211W - void sa_query_timer_hdl(struct sta_info *psta); -#endif /* CONFIG_IEEE80211W -* void reauth_timer_hdl(_adapter *padapter); -* void reassoc_timer_hdl(_adapter *padapter); */ +void sa_query_timer_hdl(void *ctx); +#endif /* CONFIG_IEEE80211W */ +#if 0 +void reauth_timer_hdl(_adapter *padapter); +void reassoc_timer_hdl(_adapter *padapter); +#endif #define set_survey_timer(mlmeext, ms) \ do { \ @@ -1100,8 +1189,8 @@ struct cmd_hdl wlancmds[] = { GEN_MLME_EXT_HANDLER(sizeof(struct getbasicrate_parm), NULL) GEN_MLME_EXT_HANDLER(sizeof(struct setdatarate_parm), NULL) GEN_MLME_EXT_HANDLER(sizeof(struct getdatarate_parm), NULL) - GEN_MLME_EXT_HANDLER(sizeof(struct setphyinfo_parm), NULL) - GEN_MLME_EXT_HANDLER(sizeof(struct getphyinfo_parm), NULL) /*30*/ + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) /*30*/ GEN_MLME_EXT_HANDLER(sizeof(struct setphy_parm), NULL) GEN_MLME_EXT_HANDLER(sizeof(struct getphy_parm), NULL) GEN_MLME_EXT_HANDLER(0, NULL) @@ -1202,6 +1291,9 @@ enum rtw_c2h_event { #ifdef CONFIG_IEEE80211W GEN_EVT_CODE(_TimeoutSTA), #endif /* CONFIG_IEEE80211W */ +#ifdef CONFIG_RTW_80211R + GEN_EVT_CODE(_FT_REASSOC), +#endif MAX_C2HEVT }; @@ -1239,7 +1331,9 @@ static struct fwevent wlanevents[] = { #ifdef CONFIG_IEEE80211W {sizeof(struct stadel_event), &rtw_sta_timeout_event_callback}, #endif /* CONFIG_IEEE80211W */ - +#ifdef CONFIG_RTW_80211R + {sizeof(struct stassoc_event), &rtw_ft_reassoc_event_callback}, +#endif }; #endif/* _RTW_MLME_EXT_C_ */ diff --git a/include/rtw_mp.h b/include/rtw_mp.h index d9c213a..c645f37 100644 --- a/include/rtw_mp.h +++ b/include/rtw_mp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_MP_H_ #define _RTW_MP_H_ @@ -217,14 +212,18 @@ typedef struct _MPT_CONTEXT { /* The Value of IO operation is depend of MptActType. */ ULONG MptIoValue; /* The RfPath of IO operation is depend of MptActType. */ - ULONG MptRfPath; + + ULONG mpt_rf_path; + WIRELESS_MODE MptWirelessModeToSw; /* Wireless mode to switch. */ u8 MptChannelToSw; /* Channel to switch. */ u8 MptInitGainToSet; /* Initial gain to set. */ /* ULONG bMptAntennaA; */ /* TRUE if we want to use antenna A. */ ULONG MptBandWidth; /* bandwidth to switch. */ - ULONG MptRateIndex; /* rate index. */ + + ULONG mpt_rate_index;/* rate index. */ + /* Register value kept for Single Carrier Tx test. */ u8 btMpCckTxPower; /* Register value kept for Single Carrier Tx test. */ @@ -243,13 +242,19 @@ typedef struct _MPT_CONTEXT { BOOLEAN bCckContTx; /* TRUE if we are in CCK Continuous Tx test. */ BOOLEAN bOfdmContTx; /* TRUE if we are in OFDM Continuous Tx test. */ - BOOLEAN bStartContTx; /* TRUE if we have start Continuous Tx test. */ + /* TRUE if we have start Continuous Tx test. */ + BOOLEAN is_start_cont_tx; + /* TRUE if we are in Single Carrier Tx test. */ BOOLEAN bSingleCarrier; /* TRUE if we are in Carrier Suppression Tx Test. */ - BOOLEAN bCarrierSuppression; + + BOOLEAN is_carrier_suppression; + /* TRUE if we are in Single Tone Tx test. */ - BOOLEAN bSingleTone; + + BOOLEAN is_single_tone; + /* ACK counter asked by K.Y.. */ BOOLEAN bMptEnableAckCounter; @@ -287,41 +292,6 @@ typedef struct _MPT_CONTEXT { } MPT_CONTEXT, *PMPT_CONTEXT; /* #endif */ -/* E-Fuse */ -#ifdef CONFIG_RTL8188E - #define EFUSE_MAP_SIZE 512 -#endif -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) - #define EFUSE_MAP_SIZE 512 -#endif -#ifdef CONFIG_RTL8192E - #define EFUSE_MAP_SIZE 512 -#endif -#ifdef CONFIG_RTL8723B - #define EFUSE_MAP_SIZE 512 -#endif -#ifdef CONFIG_RTL8814A - #define EFUSE_MAP_SIZE 512 -#endif -#ifdef CONFIG_RTL8703B - #define EFUSE_MAP_SIZE 512 -#endif -#ifdef CONFIG_RTL8723D - #define EFUSE_MAP_SIZE 512 -#endif -#ifdef CONFIG_RTL8188F - #define EFUSE_MAP_SIZE 512 -#endif - -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) - #define EFUSE_MAX_SIZE 1024 -#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) ||\ - defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D) - #define EFUSE_MAX_SIZE 256 -#else - #define EFUSE_MAX_SIZE 512 -#endif -/* end of E-Fuse */ /* #define RTPRIV_IOCTL_MP ( SIOCIWFIRSTPRIV + 0x17) */ enum { @@ -360,8 +330,13 @@ enum { EFUSE_FILE, MP_TX, MP_RX, + MP_IQK, + MP_LCK, MP_HW_TX_MODE, MP_GET_TXPOWER_INX, + MP_CUSTOMER_STR, + MP_PWRLMT, + MP_PWRBYRATE, MP_NULL, MP_SetBT, #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE @@ -466,7 +441,10 @@ struct mp_priv { BOOLEAN bTxBufCkFail; BOOLEAN bRTWSmbCfg; BOOLEAN bloopback; - MPT_CONTEXT MptCtx; + BOOLEAN bloadefusemap; + + MPT_CONTEXT mpt_ctx; + u8 *TXradomBuffer; }; @@ -508,28 +486,28 @@ typedef struct _MP_FIRMWARE { /* Hardware Registers */ #if 0 - #if 0 - #define IOCMD_CTRL_REG 0x102502C0 - #define IOCMD_DATA_REG 0x102502C4 - #else - #define IOCMD_CTRL_REG 0x10250370 - #define IOCMD_DATA_REG 0x10250374 - #endif - - #define IOCMD_GET_THERMAL_METER 0xFD000028 - - #define IOCMD_CLASS_BB_RF 0xF0 - #define IOCMD_BB_READ_IDX 0x00 - #define IOCMD_BB_WRITE_IDX 0x01 - #define IOCMD_RF_READ_IDX 0x02 - #define IOCMD_RF_WRIT_IDX 0x03 +#if 0 +#define IOCMD_CTRL_REG 0x102502C0 +#define IOCMD_DATA_REG 0x102502C4 +#else +#define IOCMD_CTRL_REG 0x10250370 +#define IOCMD_DATA_REG 0x10250374 +#endif + +#define IOCMD_GET_THERMAL_METER 0xFD000028 + +#define IOCMD_CLASS_BB_RF 0xF0 +#define IOCMD_BB_READ_IDX 0x00 +#define IOCMD_BB_WRITE_IDX 0x01 +#define IOCMD_RF_READ_IDX 0x02 +#define IOCMD_RF_WRIT_IDX 0x03 #endif #define BB_REG_BASE_ADDR 0x800 /* MP variables */ #if 0 - #define _2MAC_MODE_ 0 - #define _LOOPBOOK_MODE_ 1 +#define _2MAC_MODE_ 0 +#define _LOOPBOOK_MODE_ 1 #endif typedef enum _MP_MODE_ { MP_OFF, @@ -709,17 +687,6 @@ typedef enum _OFDM_TX_MODE { #define RX_PKT_DEST_ADDR 2 #define RX_PKT_PHY_MATCH 3 -#define Mac_OFDM_OK 0x00000000 -#define Mac_OFDM_Fail 0x10000000 -#define Mac_OFDM_FasleAlarm 0x20000000 -#define Mac_CCK_OK 0x30000000 -#define Mac_CCK_Fail 0x40000000 -#define Mac_CCK_FasleAlarm 0x50000000 -#define Mac_HT_OK 0x60000000 -#define Mac_HT_Fail 0x70000000 -#define Mac_HT_FasleAlarm 0x90000000 -#define Mac_DropPacket 0xA0000000 - typedef enum _ENCRY_CTRL_STATE_ { HW_CONTROL, /* hw encryption& decryption */ SW_CONTROL, /* sw encryption& decryption */ @@ -735,28 +702,16 @@ typedef enum _MPT_TXPWR_DEF { MPT_VHT } MPT_TXPWR_DEF; -#ifdef CONFIG_RF_POWER_TRIM - - #if defined(CONFIG_RTL8723B) - #define REG_RF_BB_GAIN_OFFSET 0x7f - #define RF_GAIN_OFFSET_MASK 0xfffff - #elif defined(CONFIG_RTL8188E) - #define REG_RF_BB_GAIN_OFFSET 0x55 - #define RF_GAIN_OFFSET_MASK 0xfffff - #else - #define REG_RF_BB_GAIN_OFFSET 0x55 - #define RF_GAIN_OFFSET_MASK 0xfffff - #endif /* CONFIG_RTL8723B */ - -#endif /*CONFIG_RF_POWER_TRIM*/ #define IS_MPT_HT_RATE(_rate) (_rate >= MPT_RATE_MCS0 && _rate <= MPT_RATE_MCS31) #define IS_MPT_VHT_RATE(_rate) (_rate >= MPT_RATE_VHT1SS_MCS0 && _rate <= MPT_RATE_VHT4SS_MCS9) #define IS_MPT_CCK_RATE(_rate) (_rate >= MPT_RATE_1M && _rate <= MPT_RATE_11M) #define IS_MPT_OFDM_RATE(_rate) (_rate >= MPT_RATE_6M && _rate <= MPT_RATE_54M) -/* *********************************************************************** - * extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv); - * extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe); */ +/*************************************************************************/ +#if 0 +extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv); +extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe); +#endif extern s32 init_mp_priv(PADAPTER padapter); extern void free_mp_priv(struct mp_priv *pmp_priv); @@ -797,7 +752,9 @@ u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter); s32 SetPowerTracking(PADAPTER padapter, u8 enable); void GetPowerTracking(PADAPTER padapter, u8 *enable); u32 mp_query_psd(PADAPTER pAdapter, u8 *data); - +void rtw_mp_trigger_iqk(PADAPTER padapter); +void rtw_mp_trigger_lck(PADAPTER padapter); +u8 rtw_mp_mode_check(PADAPTER padapter); void hal_mpt_SwitchRfSetting(PADAPTER pAdapter); @@ -813,19 +770,16 @@ s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther); void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter); u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter); void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value); -void hal_mpt_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven); void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart); void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart); void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart); void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); -void hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart); -void hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart); void mpt_ProSetPMacTx(PADAPTER Adapter); - void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain); +u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter); ULONG mpt_ProQueryCalTxPower(PADAPTER pAdapter, u8 RfPath); void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart); -u8 MptToMgntRate(u32 MptRateIdx); +u8 mpt_to_mgnt_rate(u32 MptRateIdx); u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr); u32 mp_join(PADAPTER padapter, u8 mode); u32 hal_mpt_query_phytxok(PADAPTER pAdapter); @@ -868,20 +822,20 @@ void VHT_Delimiter_generator( int rtw_mp_write_reg(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_read_reg(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_write_rf(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_read_rf(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_start(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_stop(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); @@ -889,96 +843,107 @@ int rtw_mp_rate(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); int rtw_mp_channel(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_bandwidth(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_txpower_index(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_txpower(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_txpower(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_ant_tx(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_ant_rx(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_set_ctx_destAddr(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_ctx(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_disable_bt_coexist(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_mp_disable_bt_coexist(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_mp_arx(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_trx_query(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_pwrtrk(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_psd(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_thermal(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_reset_stats(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_dump(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); int rtw_mp_phypara(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_SetRFPath(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_QueryDrv(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_mp_PwrCtlDM(struct net_device *dev, - struct iw_request_info *info, - struct iw_point *wrqu, char *extra); + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_getver(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_mp_mon(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_pwrlmt(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_pwrbyrate(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_efuse_mask_file(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_efuse_file_map(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_mp_SetBT(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra); int rtw_mp_tx(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_mp_rx(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_mp_hwtx(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); u8 HwRateToMPTRate(u8 rate); - +int rtw_mp_iqk(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_lck(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); #endif /* _RTW_MP_H_ */ diff --git a/include/rtw_mp_ioctl.h b/include/rtw_mp_ioctl.h index 95c3a6d..a9dabfc 100644 --- a/include/rtw_mp_ioctl.h +++ b/include/rtw_mp_ioctl.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_MP_IOCTL_H_ #define _RTW_MP_IOCTL_H_ @@ -24,11 +19,11 @@ #include #if 0 - #define TESTFWCMDNUMBER 1000000 - #define TEST_H2CINT_WAIT_TIME 500 - #define TEST_C2HINT_WAIT_TIME 500 - #define HCI_TEST_SYSCFG_HWMASK 1 - #define _BUSCLK_40M (4 << 2) +#define TESTFWCMDNUMBER 1000000 +#define TEST_H2CINT_WAIT_TIME 500 +#define TEST_C2HINT_WAIT_TIME 500 +#define HCI_TEST_SYSCFG_HWMASK 1 +#define _BUSCLK_40M (4 << 2) #endif /* ------------------------------------------------------------------------------ */ typedef struct CFG_DBG_MSG_STRUCT { diff --git a/include/rtw_mp_phy_regdef.h b/include/rtw_mp_phy_regdef.h index 11a80d0..be62780 100644 --- a/include/rtw_mp_phy_regdef.h +++ b/include/rtw_mp_phy_regdef.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /***************************************************************************** * * Module: __RTW_MP_PHY_REGDEF_H_ @@ -1025,13 +1020,13 @@ /* for PutRFRegsetting & GetRFRegSetting BitMask */ #if (RTL92SE_FPGA_VERIFY == 1) - /* #define bMask12Bits 0xfff */ /* RF Reg mask bits - * #define bMask20Bits 0xfff */ /* RF Reg mask bits T65 RF */ - #define bRFRegOffsetMask 0xfff +/* #define bMask12Bits 0xfff */ /* RF Reg mask bits */ +/* #define bMask20Bits 0xfff */ /* RF Reg mask bits T65 RF */ +#define bRFRegOffsetMask 0xfff #else - /* #define bMask12Bits 0xfffff */ /* RF Reg mask bits - * #define bMask20Bits 0xfffff */ /* RF Reg mask bits T65 RF */ - #define bRFRegOffsetMask 0xfffff +/* #define bMask12Bits 0xfffff */ /* RF Reg mask bits */ +/* #define bMask20Bits 0xfffff */ /* RF Reg mask bits T65 RF */ +#define bRFRegOffsetMask 0xfffff #endif #define bEnable 0x1 /* Useless */ #define bDisable 0x0 @@ -1066,12 +1061,12 @@ #define bWNICControl 0x2 #if 0 - #define ANTENNA_A 0x1 /* Useless */ - #define ANTENNA_B 0x2 - #define ANTENNA_AB 0x3 /* ANTENNA_A | ANTENNA_B */ +#define ANTENNA_A 0x1 /* Useless */ +#define ANTENNA_B 0x2 +#define ANTENNA_AB 0x3 /* ANTENNA_A | ANTENNA_B */ - #define ANTENNA_C 0x4 - #define ANTENNA_D 0x8 +#define ANTENNA_C 0x4 +#define ANTENNA_D 0x8 #endif #define RCR_AAP BIT(0) /* accept all physical address */ diff --git a/include/rtw_odm.h b/include/rtw_odm.h index a6a5e77..bcb4ea9 100644 --- a/include/rtw_odm.h +++ b/include/rtw_odm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_ODM_H__ #define __RTW_ODM_H__ @@ -25,14 +20,45 @@ /* * This file provides utilities/wrappers for rtw driver to use ODM */ +typedef enum _HAL_PHYDM_OPS { + HAL_PHYDM_DIS_ALL_FUNC, + HAL_PHYDM_FUNC_SET, + HAL_PHYDM_FUNC_CLR, + HAL_PHYDM_ABILITY_BK, + HAL_PHYDM_ABILITY_RESTORE, + HAL_PHYDM_ABILITY_SET, + HAL_PHYDM_ABILITY_GET, +} HAL_PHYDM_OPS; + + +#define DYNAMIC_FUNC_DISABLE (0x0) + u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability); + +#define rtw_phydm_func_disable_all(adapter) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0) + +#define rtw_phydm_func_for_offchannel(adapter) \ + do { \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \ + if (rtw_odm_adaptivity_needed(adapter)) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \ + } while (0) -void rtw_odm_dbg_comp_msg(void *sel, _adapter *adapter); -void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps); -void rtw_odm_dbg_level_msg(void *sel, _adapter *adapter); -void rtw_odm_dbg_level_set(_adapter *adapter, u32 level); +#define rtw_phydm_func_clr(adapter, ability) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability) + +#define rtw_phydm_ability_backup(adapter) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0) + +#define rtw_phydm_ability_restore(adapter) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0) + + +static inline u32 rtw_phydm_ability_get(_adapter *adapter) +{ + return rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0); +} -void rtw_odm_ability_msg(void *sel, _adapter *adapter); -void rtw_odm_ability_set(_adapter *adapter, u32 ability); void rtw_odm_init_ic_type(_adapter *adapter); @@ -43,16 +69,20 @@ void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter); bool rtw_odm_adaptivity_needed(_adapter *adapter); void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter); -void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff, s8 TH_L2H_ini_mode2, s8 TH_EDCCA_HL_diff_mode2, u8 EDCCA_enable); +void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff, s8 th_l2h_ini_mode2, s8 th_edcca_hl_diff_mode2, u8 edcca_enable); void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter); -void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type); -void rtw_odm_releasespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type); +void rtw_odm_acquirespinlock(_adapter *adapter, enum rt_spinlock_type type); +void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type); +u8 rtw_odm_get_dfs_domain(_adapter *adapter); +u8 rtw_odm_dfs_domain_unknown(_adapter *adapter); #ifdef CONFIG_DFS_MASTER - u8 rtw_odm_get_dfs_domain(_adapter *adapter); - VOID rtw_odm_radar_detect_reset(_adapter *adapter); - VOID rtw_odm_radar_detect_disable(_adapter *adapter); - VOID rtw_odm_radar_detect_enable(_adapter *adapter); - BOOLEAN rtw_odm_radar_detect(_adapter *adapter); +VOID rtw_odm_radar_detect_reset(_adapter *adapter); +VOID rtw_odm_radar_detect_disable(_adapter *adapter); +VOID rtw_odm_radar_detect_enable(_adapter *adapter); +BOOLEAN rtw_odm_radar_detect(_adapter *adapter); #endif /* CONFIG_DFS_MASTER */ + +void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys); + #endif /* __RTW_ODM_H__ */ diff --git a/include/rtw_p2p.h b/include/rtw_p2p.h index eeb32ef..f5fe3c1 100644 --- a/include/rtw_p2p.h +++ b/include/rtw_p2p.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_P2P_H_ #define __RTW_P2P_H_ @@ -27,29 +22,29 @@ u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code); u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); #ifdef CONFIG_WFD - int rtw_init_wifi_display_info(_adapter *padapter); - void rtw_wfd_enable(_adapter *adapter, bool on); - void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port); - void rtw_tdls_wfd_enable(_adapter *adapter, bool on); - - u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); - u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled); - u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); - u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); - u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); - u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); - u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); - u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); - u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); - u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); - u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); - u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); - - u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf); - u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf); - u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf); - u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf); - u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf); +int rtw_init_wifi_display_info(_adapter *padapter); +void rtw_wfd_enable(_adapter *adapter, bool on); +void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port); +void rtw_tdls_wfd_enable(_adapter *adapter, bool on); + +u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled); +u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); + +u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf); +u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf); +u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf); +u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf); +u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf); #endif /*CONFIG_WFD */ void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe); @@ -66,17 +61,17 @@ u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pfr u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength); -void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType); +s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf); #ifdef CONFIG_P2P_PS - void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength); - void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state); - u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue); +void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength); +void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state); +u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue); #endif /* CONFIG_P2P_PS */ #ifdef CONFIG_IOCTL_CFG80211 - void rtw_init_cfg80211_wifidirect_info(_adapter *padapter); - int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx); +void rtw_init_cfg80211_wifidirect_info(_adapter *padapter); +int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx); #endif /* CONFIG_IOCTL_CFG80211 */ void reset_global_wifidirect_info(_adapter *padapter); @@ -133,19 +128,19 @@ static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_RO } #ifdef CONFIG_DBG_P2P - void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); - void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); - /* void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line); */ - void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line); - #define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__) - #define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__) - #define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__) - /* #define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__) */ +void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); +void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); +/* void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line); */ +void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line); +#define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__) +#define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__) +#define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__) +/* #define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__) */ #else /* CONFIG_DBG_P2P */ - #define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state) - #define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state) - #define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role) - /* #define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) */ +#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state) +#define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state) +#define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role) +/* #define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) */ #endif /* CONFIG_DBG_P2P */ #define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo) diff --git a/include/rtw_pwrctrl.h b/include/rtw_pwrctrl.h index 849e839..1d5dfe9 100644 --- a/include/rtw_pwrctrl.h +++ b/include/rtw_pwrctrl.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_PWRCTRL_H_ #define __RTW_PWRCTRL_H_ @@ -41,23 +36,28 @@ #define CMD_ALIVE BIT(2) #define EVT_ALIVE BIT(3) #ifdef CONFIG_BT_COEXIST - #define BTCOEX_ALIVE BIT(4) +#define BTCOEX_ALIVE BIT(4) #endif /* CONFIG_BT_COEXIST */ #ifdef CONFIG_WOWLAN #ifdef CONFIG_DEFAULT_PATTERNS_EN #ifdef CONFIG_PLATFORM_ANDROID_INTEL_X86 /* TCP/ICMP/UDP multicast with specific IP addr */ - #define DEFAULT_PATTERN_NUM 3 + #define DEFAULT_PATTERN_NUM 4 #else /* TCP/ICMP */ - #define DEFAULT_PATTERN_NUM 2 + #define DEFAULT_PATTERN_NUM 3 #endif #else #define DEFAULT_PATTERN_NUM 0 #endif /*CONFIG_DEFAULT_PATTERNS_EN*/ -#define MAX_WKFM_NUM 16 /* Frame Mask Cam number for pattern match */ +#ifdef CONFIG_WOW_PATTERN_HW_CAM /* Frame Mask Cam number for pattern match */ +#define MAX_WKFM_CAM_NUM 12 +#else +#define MAX_WKFM_CAM_NUM 16 +#endif + #define MAX_WKFM_SIZE 16 /* (16 bytes for WKFM bit mask, 16*8 = 128 bits) */ #define MAX_WKFM_PATTERN_SIZE 128 #define WKFMCAM_ADDR_NUM 6 @@ -76,11 +76,6 @@ typedef struct rtl_priv_pattern { char mask[MAX_WKFM_SIZE]; } rtl_priv_pattern_t; -struct rtl_wow_pattern { - u16 crc; - u8 type; - u32 mask[4]; -}; #endif /* CONFIG_WOWLAN */ enum Power_Mgnt { @@ -98,10 +93,17 @@ enum Power_Mgnt { PS_MODE_NUM, }; +enum lps_level { + LPS_NORMAL = 0, + LPS_LCLK, + LPS_PG, + LPS_LEVEL_MAX, +}; + #ifdef CONFIG_PNO_SUPPORT - #define MAX_PNO_LIST_COUNT 16 - #define MAX_SCAN_LIST_COUNT 14 /* 2.4G only */ - #define MAX_HIDDEN_AP 8 /* 8 hidden AP */ +#define MAX_PNO_LIST_COUNT 16 +#define MAX_SCAN_LIST_COUNT 14 /* 2.4G only */ +#define MAX_HIDDEN_AP 8 /* 8 hidden AP */ #endif /* @@ -233,6 +235,8 @@ typedef enum _PS_DENY_REASON { PS_DENY_SUSPEND, PS_DENY_IOCTL, PS_DENY_MGNT_TX, + PS_DENY_MONITOR_MODE, + PS_DENY_BEAMFORMING, /* Beamforming */ PS_DENY_DRV_REMOVE = 30, PS_DENY_OTHERS = 31 } PS_DENY_REASON; @@ -297,6 +301,14 @@ typedef struct lps_poff_info { } lps_poff_info_t; #endif /*CONFIG_LPS_POFF*/ +struct aoac_report { + u8 iv[8]; + u8 replay_counter_eapol_key[8]; + u8 group_key[32]; + u8 key_index; + u8 security_type; +}; + struct pwrctrl_priv { _pwrlock lock; _pwrlock check_32k_lock; @@ -312,6 +324,7 @@ struct pwrctrl_priv { u32 alives; _workitem cpwm_event; + _workitem dma_event; /*for handle un-synchronized tx dma*/ #ifdef CONFIG_LPS_RPWM_TIMER u8 brpwmtimeout; _workitem rpwmtimeoutwi; @@ -367,25 +380,33 @@ struct pwrctrl_priv { #endif u8 bSupportRemoteWakeup; u8 wowlan_wake_reason; + u8 wowlan_last_wake_reason; u8 wowlan_ap_mode; u8 wowlan_mode; u8 wowlan_p2p_mode; u8 wowlan_pno_enable; + u8 wowlan_in_resume; #ifdef CONFIG_GPIO_WAKEUP u8 is_high_active; #endif /* CONFIG_GPIO_WAKEUP */ #ifdef CONFIG_WOWLAN + u8 wowlan_ns_offload_en; u8 wowlan_txpause_status; u8 wowlan_pattern_idx; u64 wowlan_fw_iv; - struct rtl_priv_pattern patterns[MAX_WKFM_NUM]; + struct rtl_priv_pattern patterns[MAX_WKFM_CAM_NUM]; #ifdef CONFIG_PNO_SUPPORT - u8 pno_in_resume; u8 pno_inited; pno_nlo_info_t *pnlo_info; pno_scan_info_t *pscan_info; pno_ssid_list_t *pno_ssid_list; #endif /* CONFIG_PNO_SUPPORT */ +#ifdef CONFIG_WOW_PATTERN_HW_CAM + _mutex wowlan_pattern_cam_mutex; +#endif + u8 wowlan_aoac_rpt_loc; + struct aoac_report wowlan_aoac_rpt; + u8 wowlan_dis_lps;/*for debug purpose*/ #endif /* CONFIG_WOWLAN */ _timer pwr_state_check_timer; int pwr_state_check_interval; @@ -425,10 +446,13 @@ struct pwrctrl_priv { #ifdef CONFIG_LPS_POFF lps_poff_info_t *plps_poff_info; #endif - + u8 lps_level_bk; + u8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/ #ifdef CONFIG_LPS_PG u8 lpspg_rsvd_page_locate; + u8 blpspg_info_up; #endif + u8 current_lps_hw_port_id; }; #define rtw_get_ips_mode_req(pwrctl) \ @@ -452,67 +476,68 @@ extern void rtw_init_pwrctrl_priv(_adapter *adapter); extern void rtw_free_pwrctrl_priv(_adapter *adapter); #ifdef CONFIG_LPS_LCLK - s32 rtw_register_task_alive(PADAPTER, u32 task); - void rtw_unregister_task_alive(PADAPTER, u32 task); - extern s32 rtw_register_tx_alive(PADAPTER padapter); - extern void rtw_unregister_tx_alive(PADAPTER padapter); - extern s32 rtw_register_rx_alive(PADAPTER padapter); - extern void rtw_unregister_rx_alive(PADAPTER padapter); - extern s32 rtw_register_cmd_alive(PADAPTER padapter); - extern void rtw_unregister_cmd_alive(PADAPTER padapter); - extern s32 rtw_register_evt_alive(PADAPTER padapter); - extern void rtw_unregister_evt_alive(PADAPTER padapter); - extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate); - extern void LPS_Leave_check(PADAPTER padapter); +s32 rtw_register_task_alive(PADAPTER, u32 task); +void rtw_unregister_task_alive(PADAPTER, u32 task); +extern s32 rtw_register_tx_alive(PADAPTER padapter); +extern void rtw_unregister_tx_alive(PADAPTER padapter); +extern s32 rtw_register_rx_alive(PADAPTER padapter); +extern void rtw_unregister_rx_alive(PADAPTER padapter); +extern s32 rtw_register_cmd_alive(PADAPTER padapter); +extern void rtw_unregister_cmd_alive(PADAPTER padapter); +extern s32 rtw_register_evt_alive(PADAPTER padapter); +extern void rtw_unregister_evt_alive(PADAPTER padapter); +extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate); +extern void LPS_Leave_check(PADAPTER padapter); #endif extern void LeaveAllPowerSaveMode(PADAPTER Adapter); extern void LeaveAllPowerSaveModeDirect(PADAPTER Adapter); #ifdef CONFIG_IPS - void _ips_enter(_adapter *padapter); - void ips_enter(_adapter *padapter); - int _ips_leave(_adapter *padapter); - int ips_leave(_adapter *padapter); +void _ips_enter(_adapter *padapter); +void ips_enter(_adapter *padapter); +int _ips_leave(_adapter *padapter); +int ips_leave(_adapter *padapter); #endif void rtw_ps_processor(_adapter *padapter); #ifdef CONFIG_AUTOSUSPEND - int autoresume_enter(_adapter *padapter); +int autoresume_enter(_adapter *padapter); #endif #ifdef SUPPORT_HW_RFOFF_DETECTED - rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter); +rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter); #endif int rtw_fw_ps_state(PADAPTER padapter); #ifdef CONFIG_LPS - s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms); - void LPS_Enter(PADAPTER padapter, const char *msg); - void LPS_Leave(PADAPTER padapter, const char *msg); - void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets); - void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg); - void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable); - void rtw_set_rpwm(_adapter *padapter, u8 val8); +s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms); +void LPS_Enter(PADAPTER padapter, const char *msg); +void LPS_Leave(PADAPTER padapter, const char *msg); +void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets); +void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg); +void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable); +void rtw_set_rpwm(_adapter *padapter, u8 val8); +void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en); #endif #ifdef CONFIG_RESUME_IN_WORKQUEUE - void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv); +void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv); #endif /* CONFIG_RESUME_IN_WORKQUEUE */ #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) - bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv); - bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv); - void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable); - void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv); - void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv); +bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv); +bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv); +void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable); +void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv); +void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv); #else - #define rtw_is_earlysuspend_registered(pwrpriv) _FALSE - #define rtw_is_do_late_resume(pwrpriv) _FALSE - #define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0) - #define rtw_register_early_suspend(pwrpriv) do {} while (0) - #define rtw_unregister_early_suspend(pwrpriv) do {} while (0) +#define rtw_is_earlysuspend_registered(pwrpriv) _FALSE +#define rtw_is_do_late_resume(pwrpriv) _FALSE +#define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0) +#define rtw_register_early_suspend(pwrpriv) do {} while (0) +#define rtw_unregister_early_suspend(pwrpriv) do {} while (0) #endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */ u8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val); @@ -522,6 +547,7 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller); #define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__) int rtw_pm_set_ips(_adapter *padapter, u8 mode); int rtw_pm_set_lps(_adapter *padapter, u8 mode); +int rtw_pm_set_lps_level(_adapter *padapter, u8 level); void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason); void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason); @@ -530,16 +556,11 @@ u32 rtw_ps_deny_get(PADAPTER padapter); #if defined(CONFIG_WOWLAN) void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip); void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr); -void rtw_set_sec_pn(_adapter *padapter); bool rtw_check_pattern_valid(u8 *input, u8 len); -bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx, - struct rtl_wow_pattern *content); - -bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx); bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern, - int *pattern_len, char *bit_mask); + int *pattern_len, char *bit_mask); +void rtw_wow_pattern_sw_reset(_adapter *adapter); u8 rtw_set_default_pattern(_adapter *adapter); -void rtw_dump_priv_pattern(_adapter *adapter, u8 idx); -void rtw_clean_pattern(_adapter *adapter); +void rtw_wow_pattern_sw_dump(_adapter *adapter); #endif /* CONFIG_WOWLAN */ #endif /* __RTL871X_PWRCTRL_H_ */ diff --git a/include/rtw_qos.h b/include/rtw_qos.h index 57555e1..380120f 100644 --- a/include/rtw_qos.h +++ b/include/rtw_qos.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_QOS_H_ diff --git a/include/rtw_recv.h b/include/rtw_recv.h index e5637e5..750dff1 100644 --- a/include/rtw_recv.h +++ b/include/rtw_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_RECV_H_ #define _RTW_RECV_H_ @@ -51,6 +46,9 @@ #define NR_PREALLOC_RECV_SKB 8 #endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ + #ifdef CONFIG_RTW_NAPI + #define RTL_NAPI_WEIGHT (32) + #endif #endif #define NR_RECVFRAME 256 @@ -63,7 +61,7 @@ #define MAX_RXFRAME_CNT 512 #define MAX_RX_NUMBLKS (32) #define RECVFRAME_HDR_ALIGN 128 -#define MAX_CONTINUAL_NORXPACKET_COUNT 1 /* In MAX_CONTINUAL_NORXPACKET_COUNT*2 sec , no rx traffict would issue DELBA*/ +#define MAX_CONTINUAL_NORXPACKET_COUNT 4 /* In MAX_CONTINUAL_NORXPACKET_COUNT*2 sec , no rx traffict would issue DELBA*/ #define PHY_RSSI_SLID_WIN_MAX 100 #define PHY_LINKQUALITY_SLID_WIN_MAX 20 @@ -105,24 +103,24 @@ struct recv_reorder_ctrl { struct stainfo_rxcache { u16 tid_rxseq[16]; - /* - unsigned short tid0_rxseq; - unsigned short tid1_rxseq; - unsigned short tid2_rxseq; - unsigned short tid3_rxseq; - unsigned short tid4_rxseq; - unsigned short tid5_rxseq; - unsigned short tid6_rxseq; - unsigned short tid7_rxseq; - unsigned short tid8_rxseq; - unsigned short tid9_rxseq; - unsigned short tid10_rxseq; - unsigned short tid11_rxseq; - unsigned short tid12_rxseq; - unsigned short tid13_rxseq; - unsigned short tid14_rxseq; - unsigned short tid15_rxseq; - */ +#if 0 + unsigned short tid0_rxseq; + unsigned short tid1_rxseq; + unsigned short tid2_rxseq; + unsigned short tid3_rxseq; + unsigned short tid4_rxseq; + unsigned short tid5_rxseq; + unsigned short tid6_rxseq; + unsigned short tid7_rxseq; + unsigned short tid8_rxseq; + unsigned short tid9_rxseq; + unsigned short tid10_rxseq; + unsigned short tid11_rxseq; + unsigned short tid12_rxseq; + unsigned short tid13_rxseq; + unsigned short tid14_rxseq; + unsigned short tid15_rxseq; +#endif }; @@ -250,14 +248,15 @@ struct rx_pkt_attrib { u8 ack_policy; - /* #ifdef CONFIG_TCP_CSUM_OFFLOAD_RX */ +/* #ifdef CONFIG_TCP_CSUM_OFFLOAD_RX */ u8 tcpchk_valid; /* 0: invalid, 1: valid */ u8 ip_chkrpt; /* 0: incorrect, 1: correct */ - u8 tcp_chkrpt; /* 0: incorrect, 1: correct - * #endif */ + u8 tcp_chkrpt; /* 0: incorrect, 1: correct */ +/* #endif */ u8 key_index; u8 data_rate; + u8 ch; /* RX channel */ u8 bw; u8 stbc; u8 ldpc; @@ -266,13 +265,13 @@ struct rx_pkt_attrib { u32 tsfl; u32 MacIDValidEntry[2]; /* 64 bits present 64 entry. */ - /* - u8 signal_qual; - s8 rx_mimo_signal_qual[2]; - u8 signal_strength; - u32 RxPWDBAll; - s32 RecvSignalPower; - */ +#if 0 + u8 signal_qual; + s8 rx_mimo_signal_qual[2]; + u8 signal_strength; + u32 RxPWDBAll; + s32 RecvSignalPower; +#endif struct phy_info phy_info; }; @@ -338,9 +337,9 @@ struct recv_stat { #ifdef CONFIG_PCI_HCI #define PCI_MAX_RX_QUEUE 1/* MSDU packet queue, Rx Command Queue */ -#define PCI_MAX_RX_COUNT 512 +#define PCI_MAX_RX_COUNT 128 #ifdef CONFIG_TRX_BD_ARCH - #define RX_BD_NUM PCI_MAX_RX_COUNT /* alias */ +#define RX_BD_NUM PCI_MAX_RX_COUNT /* alias */ #endif struct rtw_rx_ring { @@ -368,7 +367,7 @@ struct recv_priv { #ifdef CONFIG_RECV_THREAD_MODE _sema recv_sema; - _sema terminate_recvthread_sema; + #endif /* _queue blk_strms[MAX_RX_NUMBLKS]; */ /* keeping the block ack frame until return ack */ @@ -395,7 +394,9 @@ struct recv_priv { NDIS_EVENT recv_resource_evt ; #endif - u32 bIsAnyNonBEPkts; + + u32 is_any_non_be_pkts; + u64 rx_bytes; u64 rx_pkts; u64 rx_drop; @@ -426,12 +427,13 @@ struct recv_priv { struct task recv_tasklet; #else /* PLATFORM_FREEBSD */ struct tasklet_struct irq_prepare_beacon_tasklet; -#ifndef CONFIG_NAPI struct tasklet_struct recv_tasklet; -#endif #endif /* PLATFORM_FREEBSD */ struct sk_buff_head free_recv_skb_queue; struct sk_buff_head rx_skb_queue; +#ifdef CONFIG_RTW_NAPI + struct sk_buff_head rx_napi_skb_queue; +#endif #ifdef CONFIG_RX_INDICATE_QUEUE struct task rx_indicate_tasklet; struct ifqueue rx_indicate_queue; @@ -486,7 +488,7 @@ struct recv_priv { }; #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - #define rtw_set_signal_stat_timer(recvpriv) _set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval) +#define rtw_set_signal_stat_timer(recvpriv) _set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval) #endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ struct sta_recv_priv { @@ -657,6 +659,10 @@ void rx_query_phy_status(union recv_frame *rframe, u8 *phy_stat); int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index); void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index); +#ifdef CONFIG_RECV_THREAD_MODE +thread_return rtw_recv_thread(thread_context context); +#endif + __inline static u8 *get_rxmem(union recv_frame *precvframe) { /* always return rx_head... */ diff --git a/include/rtw_rf.h b/include/rtw_rf.h index 1fb17c2..113adf3 100644 --- a/include/rtw_rf.h +++ b/include/rtw_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,39 +11,16 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_RF_H_ #define __RTW_RF_H_ - -#define OFDM_PHY 1 -#define MIXED_PHY 2 -#define CCK_PHY 3 - #define NumRates (13) /* slot time for 11g */ #define SHORT_SLOT_TIME 9 #define NON_SHORT_SLOT_TIME 20 -#define RTL8711_RF_MAX_SENS 6 -#define RTL8711_RF_DEF_SENS 4 - -/* - * We now define the following channels as the max channels in each channel plan. - * 2G, total 14 chnls - * {1,2,3,4,5,6,7,8,9,10,11,12,13,14} - * 5G, total 24 chnls - * {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165} */ -#define MAX_CHANNEL_NUM_2G 14 -#define MAX_CHANNEL_NUM_5G 24 -#define MAX_CHANNEL_NUM 38/* 14+24 */ - #define CENTER_CH_2G_40M_NUM 9 #define CENTER_CH_2G_NUM 14 #define CENTER_CH_5G_20M_NUM 28 /* 20M center channels */ @@ -52,33 +29,30 @@ #define CENTER_CH_5G_160M_NUM 3 /* 160M center channels */ #define CENTER_CH_5G_ALL_NUM (CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM + CENTER_CH_5G_80M_NUM) +#define MAX_CHANNEL_NUM_2G CENTER_CH_2G_NUM +#define MAX_CHANNEL_NUM_5G CENTER_CH_5G_20M_NUM +#define MAX_CHANNEL_NUM (MAX_CHANNEL_NUM_2G + MAX_CHANNEL_NUM_5G) + +extern u8 center_ch_2g[CENTER_CH_2G_NUM]; +extern u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM]; + +u8 center_chs_2g_num(u8 bw); +u8 center_chs_2g(u8 bw, u8 id); + extern u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM]; extern u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM]; +extern u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM]; extern u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM]; extern u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM]; u8 center_chs_5g_num(u8 bw); u8 center_chs_5g(u8 bw, u8 id); +u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset); + u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num); -/* #define NUM_REGULATORYS 21 */ -#define NUM_REGULATORYS 1 - -/* Country codes */ -#define USA 0x555320 -#define EUROPE 0x1 /* temp, should be provided later */ -#define JAPAN 0x2 /* temp, should be provided later */ - -struct regulatory_class { - u32 starting_freq; /* MHz, */ - u8 channel_set[MAX_CHANNEL_NUM]; - u8 channel_cck_power[MAX_CHANNEL_NUM];/* dbm */ - u8 channel_ofdm_power[MAX_CHANNEL_NUM];/* dbm */ - u8 txpower_limit; /* dbm */ - u8 channel_spacing; /* MHz */ - u8 modem; -}; +u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group); typedef enum _CAPABILITY { cESS = 0x0001, @@ -105,18 +79,6 @@ enum _REG_PREAMBLE_MODE { PREAMBLE_SHORT = 3, }; - -enum _RTL8712_RF_MIMO_CONFIG_ { - RTL8712_RFCONFIG_1T = 0x10, - RTL8712_RFCONFIG_2T = 0x20, - RTL8712_RFCONFIG_1R = 0x01, - RTL8712_RFCONFIG_2R = 0x02, - RTL8712_RFCONFIG_1T1R = 0x11, - RTL8712_RFCONFIG_1T2R = 0x12, - RTL8712_RFCONFIG_TURBO = 0x92, - RTL8712_RFCONFIG_2T2R = 0x22 -}; - typedef enum _RF_PATH { RF_PATH_A = 0, RF_PATH_B = 1, @@ -203,9 +165,17 @@ typedef enum _RT_RF_TYPE_DEFINITION { RF_3T4R = 7, RF_4T4R = 8, - RF_MAX_TYPE = 0xF, /* u1Byte */ + RF_TYPE_AUTO, } RT_RF_TYPE_DEF_E; +#define RF_TYPE_VALID(rf_type) (rf_type < RF_TYPE_AUTO) + +extern const u8 _rf_type_to_rf_tx_cnt[]; +#define rf_type_to_rf_tx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_tx_cnt[rf_type] : 0) + +extern const u8 _rf_type_to_rf_rx_cnt[]; +#define rf_type_to_rf_rx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_rx_cnt[rf_type] : 0) + int rtw_ch2freq(int chan); int rtw_freq2ch(int freq); bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo); @@ -218,6 +188,8 @@ bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo); #define RTW_MODULE_RTL8723BE_HMC_M2 BIT5 /* RTL8723BE(HMC + M.2) */ #define RTW_MODULE_RTL8723BS_NGFF1216 BIT6 /* RTL8723BS(NGFF1216) */ #define RTW_MODULE_RTL8192EEBT_HMC_M2 BIT7 /* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */ +#define RTW_MODULE_RTL8723DE_NGFF1630 BIT8 /* RTL8723DE(NGFF1630) */ +#define RTW_MODULE_RTL8822BE BIT9 /* RTL8822BE */ #define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF) @@ -228,7 +200,7 @@ struct country_chplan { u8 en_11ac; #endif #if RTW_DEF_MODULE_REGULATORY_CERT - u8 def_module_flags; /* RTW_MODULE_RTLXXX */ + u16 def_module_flags; /* RTW_MODULE_RTLXXX */ #endif }; @@ -246,8 +218,48 @@ struct country_chplan { const struct country_chplan *rtw_get_chplan_from_country(const char *country_code); +struct rf_ctl_t; + +typedef enum _REGULATION_TXPWR_LMT { + TXPWR_LMT_NONE = 0, /* no limit */ + TXPWR_LMT_FCC = 1, + TXPWR_LMT_MKK = 2, + TXPWR_LMT_ETSI = 3, + TXPWR_LMT_IC = 4, + TXPWR_LMT_KCC = 5, + TXPWR_LMT_WW = 6, /* smallest of all available limit, keep last */ +} REGULATION_TXPWR_LMT; + +extern const char *const _regd_str[]; +#define regd_str(regd) (((regd) > TXPWR_LMT_WW) ? _regd_str[TXPWR_LMT_WW] : _regd_str[(regd)]) + +#ifdef CONFIG_TXPWR_LIMIT +struct regd_exc_ent { + _list list; + char country[2]; + u8 domain; + char regd_name[0]; +}; + +void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl); +void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen); +void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name); +struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain); +struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain); +void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl); + +void dump_txpwr_lmt(void *sel, _adapter *adapter); +void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen + , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt); +void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name + , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt); +struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name); +struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name); +void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl); +#endif /* CONFIG_TXPWR_LIMIT */ + #define BB_GAIN_2G 0 -#ifdef CONFIG_NL80211_BAND_5GHZ +#ifdef CONFIG_IEEE80211_BAND_5GHZ #define BB_GAIN_5GLB1 1 #define BB_GAIN_5GLB2 2 #define BB_GAIN_5GMB1 3 @@ -255,7 +267,7 @@ const struct country_chplan *rtw_get_chplan_from_country(const char *country_cod #define BB_GAIN_5GHB 5 #endif -#ifdef CONFIG_NL80211_BAND_5GHZ +#ifdef CONFIG_IEEE80211_BAND_5GHZ #define BB_GAIN_NUM 6 #else #define BB_GAIN_NUM 1 @@ -265,8 +277,14 @@ int rtw_ch_to_bb_gain_sel(int ch); void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset); void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch); -bool rtw_is_dfs_range(u32 hi, u32 lo); -bool rtw_is_dfs_ch(u8 ch, u8 bw, u8 offset); +u8 rtw_is_5g_band1(u8 ch); +u8 rtw_is_5g_band2(u8 ch); +u8 rtw_is_5g_band3(u8 ch); +u8 rtw_is_5g_band4(u8 ch); + +u8 rtw_is_dfs_range(u32 hi, u32 lo); +u8 rtw_is_dfs_ch(u8 ch); +u8 rtw_is_dfs_chbw(u8 ch, u8 bw, u8 offset); bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region); bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region); diff --git a/include/rtw_sdio.h b/include/rtw_sdio.h index da86a3a..7490b54 100644 --- a/include/rtw_sdio.h +++ b/include/rtw_sdio.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_SDIO_H_ #define _RTW_SDIO_H_ diff --git a/include/rtw_security.h b/include/rtw_security.h index f7b1718..ca7c526 100644 --- a/include/rtw_security.h +++ b/include/rtw_security.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_SECURITY_H_ #define __RTW_SECURITY_H_ @@ -30,9 +25,9 @@ #define _WEP_WPA_MIXED_ 0x07 /* WEP + WPA */ #define _SMS4_ 0x06 #ifdef CONFIG_IEEE80211W - #define _BIP_ 0x8 -#endif /* CONFIG_IEEE80211W -* 802.11W use wrong key */ +#define _BIP_ 0x8 +#endif /* CONFIG_IEEE80211W */ +/* 802.11W use wrong key */ #define IEEE80211W_RIGHT_KEY 0x0 #define IEEE80211W_WRONG_KEY 0x1 #define IEEE80211W_NO_KEY 0x2 @@ -50,6 +45,7 @@ const char *security_type_str(u8 value); #define RTW_KEK_LEN 16 #define RTW_KCK_LEN 16 +#define RTW_TKIP_MIC_LEN 8 #define RTW_REPLAY_CTR_LEN 8 #define INVALID_SEC_MAC_CAM_ID 0xFF @@ -65,11 +61,11 @@ typedef enum { #ifndef Ndis802_11AuthModeWPA2 - #define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1) +#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1) #endif #ifndef Ndis802_11AuthModeWPA2PSK - #define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2) +#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2) #endif union pn48 { @@ -78,29 +74,29 @@ union pn48 { #ifdef CONFIG_LITTLE_ENDIAN - struct { - u8 TSC0; - u8 TSC1; - u8 TSC2; - u8 TSC3; - u8 TSC4; - u8 TSC5; - u8 TSC6; - u8 TSC7; - } _byte_; +struct { + u8 TSC0; + u8 TSC1; + u8 TSC2; + u8 TSC3; + u8 TSC4; + u8 TSC5; + u8 TSC6; + u8 TSC7; +} _byte_; #elif defined(CONFIG_BIG_ENDIAN) - struct { - u8 TSC7; - u8 TSC6; - u8 TSC5; - u8 TSC4; - u8 TSC3; - u8 TSC2; - u8 TSC1; - u8 TSC0; - } _byte_; +struct { + u8 TSC7; + u8 TSC6; + u8 TSC5; + u8 TSC4; + u8 TSC3; + u8 TSC2; + u8 TSC1; + u8 TSC0; +} _byte_; #endif @@ -158,6 +154,8 @@ struct security_priv { #ifdef CONFIG_CONCURRENT_MODE u8 dot118021x_bmc_cam_id; #endif + /*IEEE802.11-2012 Std. Table 8-101 AKM Suite Selectors*/ + u32 rsn_akm_suite_type; u8 wps_ie[MAX_WPS_IE_LEN];/* added in assoc req */ int wps_ie_len; @@ -171,7 +169,6 @@ struct security_priv { u8 binstallBIPkey; #endif /* CONFIG_IEEE80211W */ u8 busetkipkey; - /* _timer tkip_timer; */ u8 bcheck_grpkey; u8 bgrpkey_handshake; @@ -368,7 +365,7 @@ static inline u32 rotr(u32 val, int bits) #define TD3_(i) rotr(Td0[(i) & 0xff], 24) #define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \ - ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3])) + ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3])) #define PUTU32(ct, st) { \ (ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \ @@ -439,10 +436,10 @@ static const unsigned long K[64] = { #define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3)) #define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10)) #ifndef MIN - #define MIN(x, y) (((x) < (y)) ? (x) : (y)) +#define MIN(x, y) (((x) < (y)) ? (x) : (y)) #endif #ifdef CONFIG_IEEE80211W - int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac); +int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac); #endif /* CONFIG_IEEE80211W */ void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key); void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b); @@ -465,26 +462,24 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe); u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe); void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe); #ifdef CONFIG_IEEE80211W - u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe); +u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe); #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_TDLS void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta); int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq, - u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie, - u8 *mic); + u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie, + u8 *mic); int wpa_tdls_teardown_ftie_mic(u8 *kck, u8 *lnkid, u16 reason, - u8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic); + u8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic); int tdls_verify_mic(u8 *kck, u8 trans_seq, - u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie); + u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie); #endif /* CONFIG_TDLS */ -void rtw_use_tkipkey_handler(RTW_TIMER_HDL_ARGS); - void rtw_sec_restore_wep_key(_adapter *adapter); u8 rtw_handle_tkip_countermeasure(_adapter *adapter, const char *caller); #ifdef CONFIG_WOWLAN - u16 rtw_calc_crc(u8 *pdata, int length); +u16 rtw_calc_crc(u8 *pdata, int length); #endif /*CONFIG_WOWLAN*/ #endif /* __RTL871X_SECURITY_H_ */ diff --git a/include/rtw_sreset.h b/include/rtw_sreset.h index 0ecdfc7..edf3763 100644 --- a/include/rtw_sreset.h +++ b/include/rtw_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_SRESET_H_ #define _RTW_SRESET_H_ diff --git a/include/rtw_tdls.h b/include/rtw_tdls.h index 86ce65c..841fd58 100644 --- a/include/rtw_tdls.h +++ b/include/rtw_tdls.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_TDLS_H_ #define __RTW_TDLS_H_ @@ -105,7 +100,7 @@ int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len); u8 rtw_tdls_is_setup_allowed(_adapter *padapter); #ifdef CONFIG_TDLS_CH_SW - u8 rtw_tdls_is_chsw_allowed(_adapter *padapter); +u8 rtw_tdls_is_chsw_allowed(_adapter *padapter); #endif void rtw_reset_tdls_info(_adapter *padapter); @@ -117,15 +112,15 @@ void rtw_free_tdls_timer(struct sta_info *psta); void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta); #ifdef CONFIG_TDLS_CH_SW - void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable); - void rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter); - s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time); - void rtw_tdls_chsw_oper_done(_adapter *padapter); +void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable); +void rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter); +s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time); +void rtw_tdls_chsw_oper_done(_adapter *padapter); #endif #ifdef CONFIG_WFD - int issue_tunneled_probe_req(_adapter *padapter); - int issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame); +int issue_tunneled_probe_req(_adapter *padapter); +int issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame); #endif /* CONFIG_WFD */ int issue_tdls_dis_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt); int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack); @@ -136,8 +131,8 @@ int issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *psta, struct tdls_txmgmt *ptxmgmt); int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *psta); #ifdef CONFIG_TDLS_CH_SW - int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta); - int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack); +int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta); +int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack); #endif sint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame); sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame); @@ -148,10 +143,10 @@ int On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame); int On_TDLS_Peer_Traffic_Indication(_adapter *adapter, union recv_frame *precv_frame); int On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame); #ifdef CONFIG_TDLS_CH_SW - sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame); - sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame); - void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); - void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame); +sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame); +void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); #endif void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); @@ -164,7 +159,6 @@ void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_ void rtw_build_tunneled_probe_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe); void rtw_build_tunneled_probe_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe); -u8 update_sgi_tdls(_adapter *padapter, struct sta_info *psta); u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta); int rtw_tdls_is_driver_setup(_adapter *padapter); void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta); diff --git a/include/rtw_version.h b/include/rtw_version.h index 9181079..ab5dcbd 100644 --- a/include/rtw_version.h +++ b/include/rtw_version.h @@ -1,2 +1,2 @@ -#define DRIVERVERSION "v5.1.0-5_17968.20160601_BTCOEX20160411-1400_beta" -#define BTCOEXVERSION "BTCOEX20160411-1400" +#define DRIVERVERSION "v5.2.4_22552.20170531_COEX20170518-4444" +#define BTCOEXVERSION "COEX20170518-4444" diff --git a/include/rtw_vht.h b/include/rtw_vht.h index 1d886bb..f316c85 100644 --- a/include/rtw_vht.h +++ b/include/rtw_vht.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_VHT_H_ #define _RTW_VHT_H_ @@ -126,7 +121,7 @@ struct vht_priv { u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map); u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate); -u64 rtw_vht_rate_to_bitmap(u8 *pVHTRate); +u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss); void rtw_vht_use_default_setting(_adapter *padapter); u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel); u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw); @@ -139,5 +134,6 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta); u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len); void VHTOnAssocRsp(_adapter *padapter); u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map); +void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map); #endif /* _RTW_VHT_H_ */ diff --git a/include/rtw_wapi.h b/include/rtw_wapi.h index 635aec0..92d68d6 100644 --- a/include/rtw_wapi.h +++ b/include/rtw_wapi.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __INC_WAPI_H #define __INC_WAPI_H diff --git a/include/rtw_wifi_regd.h b/include/rtw_wifi_regd.h index 2182712..f56008c 100644 --- a/include/rtw_wifi_regd.h +++ b/include/rtw_wifi_regd.h @@ -1,6 +1,15 @@ /****************************************************************************** * - * Copyright(c) 2009-2010 Realtek Corporation. + * Copyright(c) 2009-2010 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. * *****************************************************************************/ diff --git a/include/rtw_xmit.h b/include/rtw_xmit.h index 68c0266..b89d5aa 100644 --- a/include/rtw_xmit.h +++ b/include/rtw_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_XMIT_H_ #define _RTW_XMIT_H_ @@ -57,12 +52,12 @@ #define NR_XMITBUFF (4) #endif /* CONFIG_SINGLE_XMIT_BUF */ #elif defined (CONFIG_PCI_HCI) -#ifdef TX_AMSDU +#ifdef CONFIG_TX_AMSDU #define MAX_XMITBUF_SZ (3500) #else #define MAX_XMITBUF_SZ (1664) #endif - #define NR_XMITBUFF (512) + #define NR_XMITBUFF (128) #endif #ifdef PLATFORM_OS_CE @@ -89,7 +84,7 @@ #endif #ifdef CONFIG_RTL8812A - #define MAX_CMDBUF_SZ (512*14) + #define MAX_CMDBUF_SZ (512 * 17) #elif defined(CONFIG_RTL8723D) && defined(CONFIG_LPS_POFF) #define MAX_CMDBUF_SZ (128*70) /*(8960)*/ #else @@ -118,7 +113,7 @@ #ifdef CONFIG_TRX_BD_ARCH #define TX_BD_NUM (128+1) /* +1 result from ring buffer */ #else - #define TXDESC_NUM 64 + #define TXDESC_NUM 128 #endif #endif @@ -158,6 +153,18 @@ dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\ } while (0) +/* Check if AMPDU Tx is supported or not. If it is supported, +* it need to check "amsdu in ampdu" is supported or not. +* (ampdu_en, amsdu_ampdu_en) = +* (0, x) : AMPDU is not enable, but AMSDU is valid to send. +* (1, 0) : AMPDU is enable, AMSDU in AMPDU is not enable. So, AMSDU is not valid to send. +* (1, 1) : AMPDU and AMSDU in AMPDU are enable. So, AMSDU is valid to send. +*/ +#define IS_AMSDU_AMPDU_NOT_VALID(pattrib)\ + ((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE)) + +#define IS_AMSDU_AMPDU_VALID(pattrib)\ + !((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE)) #define HWXMIT_ENTRY 4 @@ -413,6 +420,7 @@ struct pkt_attrib { u8 ampdu_en;/* tx ampdu enable */ u8 ampdu_spacing; /* ampdu_min_spacing for peer sta's rx */ u8 amsdu; + u8 amsdu_ampdu_en;/* tx amsdu in ampdu enable */ u8 mdata;/* more data bit */ u8 pctrl;/* per packet txdesc control enable */ u8 triggered;/* for ap mode handling Power Saving sta */ @@ -447,11 +455,27 @@ struct pkt_attrib { #ifdef CONFIG_BEAMFORMING u16 txbf_p_aid;/*beamforming Partial_AID*/ u16 txbf_g_id;/*beamforming Group ID*/ + + /* + * 2'b00: Unicast NDPA + * 2'b01: Broadcast NDPA + * 2'b10: Beamforming Report Poll + * 2'b11: Final Beamforming Report Poll + */ + u8 bf_pkt_type; #endif }; #endif +#ifdef CONFIG_TX_AMSDU +enum { + RTW_AMSDU_TIMER_UNSET = 0, + RTW_AMSDU_TIMER_SETTING, + RTW_AMSDU_TIMER_TIMEOUT, +}; +#endif + #define WLANHDR_OFFSET 64 #define NULL_FRAMETAG (0x0) @@ -498,12 +522,8 @@ enum { RTW_SCTX_DONE_DRV_STOP, RTW_SCTX_DONE_DEV_REMOVE, RTW_SCTX_DONE_CMD_ERROR, -}; - -enum { - RTW_AMSDU_TIMER_UNSET = 0, - RTW_AMSDU_TIMER_SETTING, - RTW_AMSDU_TIMER_TIMEOUT, + RTW_SCTX_DONE_CMD_DROP, + RTX_SCTX_CSTR_WAIT_RPT2, }; @@ -684,7 +704,6 @@ struct xmit_priv { _lock lock; _sema xmit_sema; - _sema terminate_xmitthread_sema; /* _queue blk_strms[MAX_NUMBLKS]; */ _queue be_pending; @@ -774,7 +793,6 @@ struct xmit_priv { #else _thread_hdl_ SdioXmitThread; _sema SdioXmitSema; - _sema SdioXmitTerminateSema; #endif /* CONFIG_SDIO_TX_TASKLET */ #endif /* CONFIG_SDIO_HCI */ @@ -810,7 +828,7 @@ struct xmit_priv { u8 seq_no; #endif -#ifdef TX_AMSDU +#ifdef CONFIG_TX_AMSDU _timer amsdu_vo_timer; u8 amsdu_vo_timeout; @@ -829,8 +847,8 @@ struct xmit_priv { u32 amsdu_debug_coalesce_two; #endif - _lock lock_sctx; + }; extern struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, @@ -874,19 +892,17 @@ struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); extern struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry); - - extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe); extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib); #define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib) extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); #ifdef CONFIG_IEEE80211W - extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); +extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_TDLS - extern struct tdls_txmgmt *ptxmgmt; - s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt); - s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib); +extern struct tdls_txmgmt *ptxmgmt; +s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt); +s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib); #endif s32 _rtw_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag); void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv); @@ -903,55 +919,81 @@ void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv); void rtw_alloc_hwxmits(_adapter *padapter); void rtw_free_hwxmits(_adapter *padapter); - +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev); - +#endif s32 rtw_xmit(_adapter *padapter, _pkt **pkt); bool xmitframe_hiq_filter(struct xmit_frame *xmitframe); #if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) - sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); - void stop_sta_xmit(_adapter *padapter, struct sta_info *psta); - void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta); - void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta); +sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); +void stop_sta_xmit(_adapter *padapter, struct sta_info *psta); +void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta); +void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta); #endif -u8 query_ra_short_GI(struct sta_info *psta); +u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta); + +void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht); +void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj); +u16 rtw_get_tx_rate_bmp_cck_ofdm(struct dvobj_priv *dvobj); +u32 rtw_get_tx_rate_bmp_ht_by_bw(struct dvobj_priv *dvobj, u8 bw); +u32 rtw_get_tx_rate_bmp_vht_by_bw(struct dvobj_priv *dvobj, u8 bw); +u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw); +u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw); + +u8 query_ra_short_GI(struct sta_info *psta, u8 bw); u8 qos_acm(u8 acm_mask, u8 priority); #ifdef CONFIG_XMIT_THREAD_MODE - void enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); - void enqueue_pending_xmitbuf_to_head(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); - struct xmit_buf *dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv); - struct xmit_buf *dequeue_pending_xmitbuf_under_survey(struct xmit_priv *pxmitpriv); - sint check_pending_xmitbuf(struct xmit_priv *pxmitpriv); - thread_return rtw_xmit_thread(thread_context context); +void enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); +void enqueue_pending_xmitbuf_to_head(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); +struct xmit_buf *dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv); +struct xmit_buf *select_and_dequeue_pending_xmitbuf(_adapter *padapter); +sint check_pending_xmitbuf(struct xmit_priv *pxmitpriv); +thread_return rtw_xmit_thread(thread_context context); #endif -#ifdef TX_AMSDU - extern void rtw_amsdu_vo_timeout_handler(void *FunctionContext); - extern void rtw_amsdu_vi_timeout_handler(void *FunctionContext); - extern void rtw_amsdu_be_timeout_handler(void *FunctionContext); - extern void rtw_amsdu_bk_timeout_handler(void *FunctionContext); +#ifdef CONFIG_TX_AMSDU +extern void rtw_amsdu_vo_timeout_handler(void *FunctionContext); +extern void rtw_amsdu_vi_timeout_handler(void *FunctionContext); +extern void rtw_amsdu_be_timeout_handler(void *FunctionContext); +extern void rtw_amsdu_bk_timeout_handler(void *FunctionContext); - extern u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority); - extern void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status); - extern void rtw_amsdu_set_timer(_adapter *padapter, u8 priority); - extern void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority); +extern u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority); +extern void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status); +extern void rtw_amsdu_set_timer(_adapter *padapter, u8 priority); +extern void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority); - extern s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue); - extern int check_amsdu(struct xmit_frame *pxmitframe); - extern struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame); +extern s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue); +extern s32 check_amsdu(struct xmit_frame *pxmitframe); +extern s32 check_amsdu_tx_support(_adapter *padapter); +extern struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame); #endif static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib); u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe); #ifdef CONFIG_XMIT_ACK - int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms); - void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status); +int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms); +void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status); #endif /* CONFIG_XMIT_ACK */ +enum XMIT_BLOCK_REASON { + XMIT_BLOCK_NONE = 0, + XMIT_BLOCK_REDLMEM = BIT0, /*LPS-PG*/ + XMIT_BLOCK_SUSPEND = BIT1, /*WOW*/ + XMIT_BLOCK_MAX = 0xFF, +}; +void rtw_init_xmit_block(_adapter *padapter); +void rtw_deinit_xmit_block(_adapter *padapter); + +#ifdef DBG_XMIT_BLOCK +void dump_xmit_block(void *sel, _adapter *padapter); +#endif +void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason); +void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason); +bool rtw_is_xmit_blocked(_adapter *padapter); /* include after declaring struct xmit_buf, in order to avoid warning */ #include diff --git a/include/sdio_hal.h b/include/sdio_hal.h index 6680ce1..62e7f79 100644 --- a/include/sdio_hal.h +++ b/include/sdio_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __SDIO_HAL_H__ #define __SDIO_HAL_H__ @@ -24,31 +19,31 @@ void sd_int_dpc(PADAPTER padapter); u8 rtw_set_hal_ops(_adapter *padapter); #ifdef CONFIG_RTL8188E - void rtl8188es_set_hal_ops(PADAPTER padapter); +void rtl8188es_set_hal_ops(PADAPTER padapter); #endif #ifdef CONFIG_RTL8723B - void rtl8723bs_set_hal_ops(PADAPTER padapter); +void rtl8723bs_set_hal_ops(PADAPTER padapter); #endif #ifdef CONFIG_RTL8821A - void rtl8821as_set_hal_ops(PADAPTER padapter); +void rtl8821as_set_hal_ops(PADAPTER padapter); #endif #ifdef CONFIG_RTL8192E - void rtl8192es_set_hal_ops(PADAPTER padapter); +void rtl8192es_set_hal_ops(PADAPTER padapter); #endif #ifdef CONFIG_RTL8703B - void rtl8703bs_set_hal_ops(PADAPTER padapter); +void rtl8703bs_set_hal_ops(PADAPTER padapter); #endif #ifdef CONFIG_RTL8723D - void rtl8723ds_set_hal_ops(PADAPTER padapter); +void rtl8723ds_set_hal_ops(PADAPTER padapter); #endif #ifdef CONFIG_RTL8188F - void rtl8188fs_set_hal_ops(PADAPTER padapter); +void rtl8188fs_set_hal_ops(PADAPTER padapter); #endif #endif /* __SDIO_HAL_H__ */ diff --git a/include/sdio_ops.h b/include/sdio_ops.h index 38862d2..73eeae4 100644 --- a/include/sdio_ops.h +++ b/include/sdio_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __SDIO_OPS_H__ #define __SDIO_OPS_H__ @@ -27,7 +22,7 @@ #define SDIO_ERR_VAL32 0xFFFFFFFF #ifdef PLATFORM_LINUX - #include +#include #endif #ifdef PLATFORM_WINDOWS @@ -43,16 +38,19 @@ struct async_context { #endif #ifdef PLATFORM_OS_CE - #include +#include #endif #endif /* PLATFORM_WINDOWS */ extern void sdio_set_intf_ops(_adapter *padapter, struct _io_ops *pops); +void dump_sdio_card_info(void *sel, struct dvobj_priv *dvobj); -/* extern void sdio_func1cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); - * extern void sdio_func1cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); */ +#if 0 +extern void sdio_func1cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); +extern void sdio_func1cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); +#endif extern u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr); extern void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v); extern s32 _sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf); @@ -67,90 +65,93 @@ extern void sd_int_hdl(PADAPTER padapter); extern u8 CheckIPSStatus(PADAPTER padapter); #ifdef CONFIG_RTL8188E - extern void InitInterrupt8188ESdio(PADAPTER padapter); - extern void EnableInterrupt8188ESdio(PADAPTER padapter); - extern void DisableInterrupt8188ESdio(PADAPTER padapter); - extern void UpdateInterruptMask8188ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR); - extern u8 HalQueryTxBufferStatus8189ESdio(PADAPTER padapter); - extern u8 HalQueryTxOQTBufferStatus8189ESdio(PADAPTER padapter); - extern void ClearInterrupt8188ESdio(PADAPTER padapter); +extern void InitInterrupt8188ESdio(PADAPTER padapter); +extern void EnableInterrupt8188ESdio(PADAPTER padapter); +extern void DisableInterrupt8188ESdio(PADAPTER padapter); +extern void UpdateInterruptMask8188ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR); +extern u8 HalQueryTxBufferStatus8189ESdio(PADAPTER padapter); +extern u8 HalQueryTxOQTBufferStatus8189ESdio(PADAPTER padapter); +extern void ClearInterrupt8188ESdio(PADAPTER padapter); #endif /* CONFIG_RTL8188E */ #ifdef CONFIG_RTL8821A - extern void InitInterrupt8821AS(PADAPTER padapter); - extern void EnableInterrupt8821AS(PADAPTER padapter); - extern void DisableInterrupt8821AS(PADAPTER padapter); - extern u8 HalQueryTxBufferStatus8821AS(PADAPTER padapter); - extern u8 HalQueryTxOQTBufferStatus8821ASdio(PADAPTER padapter); - #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - void ClearInterrupt8821AS(PADAPTER padapter); - #endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */ +extern void InitInterrupt8821AS(PADAPTER padapter); +extern void EnableInterrupt8821AS(PADAPTER padapter); +extern void DisableInterrupt8821AS(PADAPTER padapter); +extern u8 HalQueryTxBufferStatus8821AS(PADAPTER padapter); +extern u8 HalQueryTxOQTBufferStatus8821ASdio(PADAPTER padapter); +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) +void ClearInterrupt8821AS(PADAPTER padapter); +#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */ #endif /* CONFIG_RTL8821A */ #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - extern u8 RecvOnePkt(PADAPTER padapter, u32 size); +#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) +u8 rtw_hal_enable_cpwm2(_adapter *adapter); +#endif +extern u8 RecvOnePkt(PADAPTER padapter); #endif /* CONFIG_WOWLAN */ #ifdef CONFIG_RTL8723B - extern void InitInterrupt8723BSdio(PADAPTER padapter); - extern void InitSysInterrupt8723BSdio(PADAPTER padapter); - extern void EnableInterrupt8723BSdio(PADAPTER padapter); - extern void DisableInterrupt8723BSdio(PADAPTER padapter); - extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter); - extern u8 HalQueryTxOQTBufferStatus8723BSdio(PADAPTER padapter); - #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - extern void DisableInterruptButCpwm28723BSdio(PADAPTER padapter); - extern void ClearInterrupt8723BSdio(PADAPTER padapter); - #endif /* CONFIG_WOWLAN */ +extern void InitInterrupt8723BSdio(PADAPTER padapter); +extern void InitSysInterrupt8723BSdio(PADAPTER padapter); +extern void EnableInterrupt8723BSdio(PADAPTER padapter); +extern void DisableInterrupt8723BSdio(PADAPTER padapter); +extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter); +extern u8 HalQueryTxOQTBufferStatus8723BSdio(PADAPTER padapter); +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) +extern void DisableInterruptButCpwm28723BSdio(PADAPTER padapter); +extern void ClearInterrupt8723BSdio(PADAPTER padapter); +#endif /* CONFIG_WOWLAN */ #endif #ifdef CONFIG_RTL8192E - extern void InitInterrupt8192ESdio(PADAPTER padapter); - extern void EnableInterrupt8192ESdio(PADAPTER padapter); - extern void DisableInterrupt8192ESdio(PADAPTER padapter); - extern void UpdateInterruptMask8192ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR); - extern u8 HalQueryTxBufferStatus8192ESdio(PADAPTER padapter); - extern u8 HalQueryTxOQTBufferStatus8192ESdio(PADAPTER padapter); - extern void ClearInterrupt8192ESdio(PADAPTER padapter); +extern void InitInterrupt8192ESdio(PADAPTER padapter); +extern void EnableInterrupt8192ESdio(PADAPTER padapter); +extern void DisableInterrupt8192ESdio(PADAPTER padapter); +extern void UpdateInterruptMask8192ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR); +extern u8 HalQueryTxBufferStatus8192ESdio(PADAPTER padapter); +extern u8 HalQueryTxOQTBufferStatus8192ESdio(PADAPTER padapter); +extern void ClearInterrupt8192ESdio(PADAPTER padapter); #endif /* CONFIG_RTL8192E */ #ifdef CONFIG_RTL8703B - extern void InitInterrupt8703BSdio(PADAPTER padapter); - extern void InitSysInterrupt8703BSdio(PADAPTER padapter); - extern void EnableInterrupt8703BSdio(PADAPTER padapter); - extern void DisableInterrupt8703BSdio(PADAPTER padapter); - extern u8 HalQueryTxBufferStatus8703BSdio(PADAPTER padapter); - extern u8 HalQueryTxOQTBufferStatus8703BSdio(PADAPTER padapter); - #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - extern void DisableInterruptButCpwm28703BSdio(PADAPTER padapter); - extern void ClearInterrupt8703BSdio(PADAPTER padapter); - #endif /* CONFIG_WOWLAN */ +extern void InitInterrupt8703BSdio(PADAPTER padapter); +extern void InitSysInterrupt8703BSdio(PADAPTER padapter); +extern void EnableInterrupt8703BSdio(PADAPTER padapter); +extern void DisableInterrupt8703BSdio(PADAPTER padapter); +extern u8 HalQueryTxBufferStatus8703BSdio(PADAPTER padapter); +extern u8 HalQueryTxOQTBufferStatus8703BSdio(PADAPTER padapter); +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) +extern void DisableInterruptButCpwm28703BSdio(PADAPTER padapter); +extern void ClearInterrupt8703BSdio(PADAPTER padapter); +#endif /* CONFIG_WOWLAN */ #endif #ifdef CONFIG_RTL8723D - extern void InitInterrupt8723DSdio(PADAPTER padapter); - extern void InitSysInterrupt8723DSdio(PADAPTER padapter); - extern void EnableInterrupt8723DSdio(PADAPTER padapter); - extern void DisableInterrupt8723DSdio(PADAPTER padapter); - extern u8 HalQueryTxBufferStatus8723DSdio(PADAPTER padapter); - extern u8 HalQueryTxOQTBufferStatus8723DSdio(PADAPTER padapter); - #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - extern void DisableInterruptButCpwm28723dSdio(PADAPTER padapter); - extern void ClearInterrupt8723DSdio(PADAPTER padapter); - #endif /* CONFIG_WOWLAN */ +extern void InitInterrupt8723DSdio(PADAPTER padapter); +extern void InitSysInterrupt8723DSdio(PADAPTER padapter); +extern void EnableInterrupt8723DSdio(PADAPTER padapter); +extern void DisableInterrupt8723DSdio(PADAPTER padapter); +extern u8 HalQueryTxBufferStatus8723DSdio(PADAPTER padapter); +extern u8 HalQueryTxOQTBufferStatus8723DSdio(PADAPTER padapter); +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) +extern void DisableInterruptButCpwm28723dSdio(PADAPTER padapter); +extern void ClearInterrupt8723DSdio(PADAPTER padapter); +#endif /* CONFIG_WOWLAN */ #endif #ifdef CONFIG_RTL8188F - extern void InitInterrupt8188FSdio(PADAPTER padapter); - extern void InitSysInterrupt8188FSdio(PADAPTER padapter); - extern void EnableInterrupt8188FSdio(PADAPTER padapter); - extern void DisableInterrupt8188FSdio(PADAPTER padapter); - extern u8 HalQueryTxBufferStatus8188FSdio(PADAPTER padapter); - extern u8 HalQueryTxOQTBufferStatus8188FSdio(PADAPTER padapter); - #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - extern void DisableInterruptButCpwm28188FSdio(PADAPTER padapter); - extern void ClearInterrupt8188FSdio(PADAPTER padapter); - #endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */ +extern void InitInterrupt8188FSdio(PADAPTER padapter); +extern void InitSysInterrupt8188FSdio(PADAPTER padapter); +extern void EnableInterrupt8188FSdio(PADAPTER padapter); +extern void DisableInterrupt8188FSdio(PADAPTER padapter); +extern u8 HalQueryTxBufferStatus8188FSdio(PADAPTER padapter); +extern u8 HalQueryTxOQTBufferStatus8188FSdio(PADAPTER padapter); +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) +extern void DisableInterruptButCpwm28188FSdio(PADAPTER padapter); +extern void ClearInterrupt8188FSdio(PADAPTER padapter); +#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */ #endif #endif /* !__SDIO_OPS_H__ */ diff --git a/include/sdio_ops_ce.h b/include/sdio_ops_ce.h index e821bfe..d542cb7 100644 --- a/include/sdio_ops_ce.h +++ b/include/sdio_ops_ce.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _SDIO_OPS_WINCE_H_ #define _SDIO_OPS_WINCE_H_ @@ -29,25 +24,25 @@ #ifdef PLATFORM_OS_CE - extern u8 sdbus_cmd52r_ce(struct intf_priv *pintfpriv, u32 addr); +extern u8 sdbus_cmd52r_ce(struct intf_priv *pintfpriv, u32 addr); - extern void sdbus_cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8); +extern void sdbus_cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8); - uint sdbus_read_blocks_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); +uint sdbus_read_blocks_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); - extern uint sdbus_read_bytes_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); +extern uint sdbus_read_bytes_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); - extern uint sdbus_write_blocks_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf, u8 async); +extern uint sdbus_write_blocks_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf, u8 async); - extern uint sdbus_write_bytes_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); - extern u8 sdbus_func1cmd52r_ce(struct intf_priv *pintfpriv, u32 addr); - extern void sdbus_func1cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8); - extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata); - extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata); - extern void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata); +extern uint sdbus_write_bytes_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); +extern u8 sdbus_func1cmd52r_ce(struct intf_priv *pintfpriv, u32 addr); +extern void sdbus_func1cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8); +extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata); +extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata); +extern void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata); #endif diff --git a/include/sdio_ops_linux.h b/include/sdio_ops_linux.h index 3f08a27..a4c948a 100644 --- a/include/sdio_ops_linux.h +++ b/include/sdio_ops_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,44 +11,48 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __SDIO_OPS_LINUX_H__ #define __SDIO_OPS_LINUX_H__ #ifndef RTW_HALMAC - u8 sd_f0_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err); - void sd_f0_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err); - - s32 _sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata); - s32 _sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata); - s32 sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata); - s32 sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata); - - u8 _sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err); - u8 sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err); - u16 sd_read16(struct intf_hdl *pintfhdl, u32 addr, s32 *err); - u32 _sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err); - u32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err); - void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err); - void sd_write16(struct intf_hdl *pintfhdl, u32 addr, u16 v, s32 *err); - void _sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err); - void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err); +u8 sd_f0_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err); +void sd_f0_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err); + +s32 _sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata); +s32 _sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata); +s32 sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata); +s32 sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata); + +u8 _sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err); +u8 sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err); +u16 sd_read16(struct intf_hdl *pintfhdl, u32 addr, s32 *err); +u32 _sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err); +u32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err); +void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err); +void sd_write16(struct intf_hdl *pintfhdl, u32 addr, u16 v, s32 *err); +void _sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err); +void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err); #endif /* RTW_HALMAC */ + +/* The unit of return value is Hz */ +static inline u32 rtw_sdio_get_clock(struct dvobj_priv *d) +{ + return d->intf_data.clock; +} + +bool rtw_is_sdio30(_adapter *adapter); s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); s32 sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); s32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); s32 sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); void rtw_sdio_set_irq_thd(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl); -int __must_check rtw_sdio_raw_read(struct dvobj_priv *d, int addr, - void *buf, size_t len, bool fixed); -int __must_check rtw_sdio_raw_write(struct dvobj_priv *d, int addr, - void *buf, size_t len, bool fixed); +int __must_check rtw_sdio_raw_read(struct dvobj_priv *d, unsigned int addr, + void *buf, size_t len, bool fixed); +int __must_check rtw_sdio_raw_write(struct dvobj_priv *d, unsigned int addr, + void *buf, size_t len, bool fixed); + +#endif /* __SDIO_OPS_LINUX_H__ */ -#endif diff --git a/include/sdio_ops_xp.h b/include/sdio_ops_xp.h index f464c97..d3d8764 100644 --- a/include/sdio_ops_xp.h +++ b/include/sdio_ops_xp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _SDIO_OPS_XP_H_ #define _SDIO_OPS_XP_H_ @@ -29,25 +24,25 @@ #ifdef PLATFORM_OS_XP - extern u8 sdbus_cmd52r_xp(struct intf_priv *pintfpriv, u32 addr); +extern u8 sdbus_cmd52r_xp(struct intf_priv *pintfpriv, u32 addr); - extern void sdbus_cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8); +extern void sdbus_cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8); - uint sdbus_read_blocks_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); +uint sdbus_read_blocks_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); - extern uint sdbus_read_bytes_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); +extern uint sdbus_read_bytes_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); - extern uint sdbus_write_blocks_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf, u8 async); +extern uint sdbus_write_blocks_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf, u8 async); - extern uint sdbus_write_bytes_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); - extern u8 sdbus_func1cmd52r_xp(struct intf_priv *pintfpriv, u32 addr); - extern void sdbus_func1cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8); - extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata); - extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata); - extern void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata); +extern uint sdbus_write_bytes_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); +extern u8 sdbus_func1cmd52r_xp(struct intf_priv *pintfpriv, u32 addr); +extern void sdbus_func1cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8); +extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata); +extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata); +extern void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata); #endif diff --git a/include/sdio_osintf.h b/include/sdio_osintf.h index e51d2e4..7c2abd1 100644 --- a/include/sdio_osintf.h +++ b/include/sdio_osintf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,20 +11,15 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __SDIO_OSINTF_H__ #define __SDIO_OSINTF_H__ #ifdef PLATFORM_OS_CE - extern NDIS_STATUS ce_sd_get_dev_hdl(PADAPTER padapter); - SD_API_STATUS ce_sd_int_callback(SD_DEVICE_HANDLE hDevice, PADAPTER padapter); - extern void sd_setup_irs(PADAPTER padapter); +extern NDIS_STATUS ce_sd_get_dev_hdl(PADAPTER padapter); +SD_API_STATUS ce_sd_int_callback(SD_DEVICE_HANDLE hDevice, PADAPTER padapter); +extern void sd_setup_irs(PADAPTER padapter); #endif #endif diff --git a/include/sta_info.h b/include/sta_info.h index 4689e53..b7fb7ee 100644 --- a/include/sta_info.h +++ b/include/sta_info.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __STA_INFO_H_ #define __STA_INFO_H_ @@ -27,13 +22,39 @@ #ifndef CONFIG_RTW_MACADDR_ACL #define CONFIG_RTW_MACADDR_ACL 1 #endif + +#ifndef CONFIG_RTW_PRE_LINK_STA + #define CONFIG_RTW_PRE_LINK_STA 0 +#endif + #define NUM_ACL 16 #define RTW_ACL_MODE_DISABLED 0 #define RTW_ACL_MODE_ACCEPT_UNLESS_LISTED 1 #define RTW_ACL_MODE_DENY_UNLESS_LISTED 2 +#define RTW_ACL_MODE_MAX 3 + +#if CONFIG_RTW_MACADDR_ACL +extern const char *const _acl_mode_str[]; +#define acl_mode_str(mode) (((mode) >= RTW_ACL_MODE_MAX) ? _acl_mode_str[RTW_ACL_MODE_DISABLED] : _acl_mode_str[(mode)]) +#endif + +#ifndef RTW_PRE_LINK_STA_NUM + #define RTW_PRE_LINK_STA_NUM 8 +#endif + +struct pre_link_sta_node_t { + u8 valid; + u8 addr[ETH_ALEN]; +}; + +struct pre_link_sta_ctl_t { + _lock lock; + u8 num; + struct pre_link_sta_node_t node[RTW_PRE_LINK_STA_NUM]; +}; #ifdef CONFIG_TDLS - #define MAX_ALLOWED_TDLS_STA_NUM 4 +#define MAX_ALLOWED_TDLS_STA_NUM 4 #endif enum sta_info_update_type { @@ -67,34 +88,36 @@ struct wlan_acl_pool { }; typedef struct _RSSI_STA { - s32 UndecoratedSmoothedPWDB; - s32 UndecoratedSmoothedCCK; - s32 UndecoratedSmoothedOFDM; - u8 OFDM_pkt; - u8 CCK_pkt; - u16 CCK_sum_power; - u8 bsend_rssi; - u64 PacketMap; - u8 ValidBit; + + s32 undecorated_smoothed_pwdb; + s32 undecorated_smoothed_cck; + s32 undecorated_smoothed_ofdm; + u8 ofdm_pkt; + u8 cck_pkt; + u16 cck_sum_power; + u8 is_send_rssi; + u64 packet_map; + u8 valid_bit; } RSSI_STA, *PRSSI_STA; struct stainfo_stats { u64 rx_mgnt_pkts; - u64 rx_beacon_pkts; - u64 rx_probereq_pkts; - u64 rx_probersp_pkts; - u64 rx_probersp_bm_pkts; - u64 rx_probersp_uo_pkts; + u64 rx_beacon_pkts; + u64 rx_probereq_pkts; + u64 rx_probersp_pkts; + u64 rx_probersp_bm_pkts; + u64 rx_probersp_uo_pkts; u64 rx_ctrl_pkts; u64 rx_data_pkts; + u64 rx_data_last_pkts; /* For Read & Clear requirement in proc_get_rx_stat() */ u64 rx_data_qos_pkts[TID_NUM]; u64 last_rx_mgnt_pkts; - u64 last_rx_beacon_pkts; - u64 last_rx_probereq_pkts; - u64 last_rx_probersp_pkts; - u64 last_rx_probersp_bm_pkts; - u64 last_rx_probersp_uo_pkts; + u64 last_rx_beacon_pkts; + u64 last_rx_probereq_pkts; + u64 last_rx_probersp_pkts; + u64 last_rx_probersp_bm_pkts; + u64 last_rx_probersp_uo_pkts; u64 last_rx_ctrl_pkts; u64 last_rx_data_pkts; u64 last_rx_data_qos_pkts[TID_NUM]; @@ -108,10 +131,16 @@ struct stainfo_stats { u64 tx_pkts; u64 tx_bytes; u64 tx_drops; + + u32 duplicate_cnt; /* Read & Clear, in proc_get_rx_stat() */ + u32 rxratecnt[128]; /* Read & Clear, in proc_get_rx_stat() */ + u32 tx_ok_cnt; /* Read & Clear, in proc_get_tx_stat() */ + u32 tx_fail_cnt; /* Read & Clear, in proc_get_tx_stat() */ + u32 tx_retry_cnt; /* Read & Clear, in proc_get_tx_stat() */ }; #ifndef DBG_SESSION_TRACKER - #define DBG_SESSION_TRACKER 0 +#define DBG_SESSION_TRACKER 0 #endif /* session tracker status */ @@ -330,6 +359,9 @@ struct sta_info { int wpa2_pairwise_cipher; u8 bpairwise_key_installed; +#ifdef CONFIG_RTW_80211R + u8 ft_pairwise_key_installed; +#endif #ifdef CONFIG_NATIVEAP_MLME u8 wpa_ie[32]; @@ -430,6 +462,7 @@ struct sta_info { u16 RxMgmtFrameSeqNum; struct st_ctl_t st_ctl; + u8 max_agg_num_minimal_record; /*keep minimal tx desc max_agg_num setting*/ }; #define sta_rx_pkts(sta) \ @@ -520,11 +553,11 @@ struct sta_info { #define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)" #ifdef CONFIG_WFD - #define STA_OP_WFD_MODE(sta) (sta)->op_wfd_mode - #define STA_SET_OP_WFD_MODE(sta, mode) (sta)->op_wfd_mode = (mode) +#define STA_OP_WFD_MODE(sta) (sta)->op_wfd_mode +#define STA_SET_OP_WFD_MODE(sta, mode) (sta)->op_wfd_mode = (mode) #else - #define STA_OP_WFD_MODE(sta) 0 - #define STA_SET_OP_WFD_MODE(sta, mode) do {} while (0) +#define STA_OP_WFD_MODE(sta) 0 +#define STA_SET_OP_WFD_MODE(sta, mode) do {} while (0) #endif struct sta_priv { @@ -570,12 +603,17 @@ struct sta_priv { struct wlan_acl_pool acl_list; #endif -#endif + #if CONFIG_RTW_PRE_LINK_STA + struct pre_link_sta_ctl_t pre_link_sta_ctl; + #endif + +#endif /* CONFIG_AP_MODE */ #ifdef CONFIG_ATMEL_RC_PATCH u8 atmel_rc_pattern[6]; #endif - + struct sta_info *c2h_sta; + struct submit_ctx *gotc2h; }; @@ -612,7 +650,18 @@ extern u32 rtw_init_bcmc_stainfo(_adapter *padapter); extern struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter); #if CONFIG_RTW_MACADDR_ACL - extern u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr); +extern u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr); +void dump_macaddr_acl(void *sel, _adapter *adapter); #endif +bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr); +#if CONFIG_RTW_PRE_LINK_STA +struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr); +void rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr); +void rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv); +void rtw_pre_link_sta_ctl_init(struct sta_priv *stapriv); +void rtw_pre_link_sta_ctl_deinit(struct sta_priv *stapriv); +void dump_pre_link_sta_ctl(void *sel, struct sta_priv *stapriv); +#endif /* CONFIG_RTW_PRE_LINK_STA */ + #endif /* _STA_INFO_H_ */ diff --git a/include/usb_hal.h b/include/usb_hal.h index ad472a4..a5af048 100644 --- a/include/usb_hal.h +++ b/include/usb_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,54 +11,52 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __USB_HAL_H__ #define __USB_HAL_H__ int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz); void usb_free_recv_priv(_adapter *padapter, u16 ini_in_buf_sz); +#ifdef CONFIG_FW_C2H_REG +void usb_c2h_hisr_hdl(_adapter *adapter, u8 *buf); +#endif u8 rtw_set_hal_ops(_adapter *padapter); #ifdef CONFIG_RTL8188E - void rtl8188eu_set_hal_ops(_adapter *padapter); +void rtl8188eu_set_hal_ops(_adapter *padapter); #endif #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - void rtl8812au_set_hal_ops(_adapter *padapter); +void rtl8812au_set_hal_ops(_adapter *padapter); #endif #ifdef CONFIG_RTL8192E - void rtl8192eu_set_hal_ops(_adapter *padapter); +void rtl8192eu_set_hal_ops(_adapter *padapter); #endif #ifdef CONFIG_RTL8723B - void rtl8723bu_set_hal_ops(_adapter *padapter); +void rtl8723bu_set_hal_ops(_adapter *padapter); #endif #ifdef CONFIG_RTL8814A - void rtl8814au_set_hal_ops(_adapter *padapter); +void rtl8814au_set_hal_ops(_adapter *padapter); #endif /* CONFIG_RTL8814A */ #ifdef CONFIG_RTL8188F - void rtl8188fu_set_hal_ops(_adapter *padapter); +void rtl8188fu_set_hal_ops(_adapter *padapter); #endif #ifdef CONFIG_RTL8703B - void rtl8703bu_set_hal_ops(_adapter *padapter); +void rtl8703bu_set_hal_ops(_adapter *padapter); #endif #ifdef CONFIG_RTL8723D - void rtl8723du_set_hal_ops(_adapter *padapter); +void rtl8723du_set_hal_ops(_adapter *padapter); #endif #ifdef CONFIG_INTEL_PROXIM - extern _adapter *rtw_usb_get_sw_pointer(void); +extern _adapter *rtw_usb_get_sw_pointer(void); #endif /* CONFIG_INTEL_PROXIM */ #endif /* __USB_HAL_H__ */ diff --git a/include/usb_ops.h b/include/usb_ops.h index 2ad6b34..06b0f42 100644 --- a/include/usb_ops.h +++ b/include/usb_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __USB_OPS_H_ #define __USB_OPS_H_ @@ -36,69 +31,69 @@ enum { #define MAX_USB_IO_CTL_SIZE (MAX_VENDOR_REQ_CMD_SIZE + ALIGNMENT_UNIT) #ifdef PLATFORM_LINUX - #include +#include #endif /* PLATFORM_LINUX */ #ifdef CONFIG_RTL8188E - void rtl8188eu_set_hw_type(struct dvobj_priv *pdvobj); - #ifdef CONFIG_SUPPORT_USB_INT - void interrupt_handler_8188eu(_adapter *padapter, u16 pkt_len, u8 *pbuf); - #endif +void rtl8188eu_set_hw_type(struct dvobj_priv *pdvobj); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8188eu(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif #endif #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - void rtl8812au_set_hw_type(struct dvobj_priv *pdvobj); - #ifdef CONFIG_SUPPORT_USB_INT - void interrupt_handler_8812au(_adapter *padapter, u16 pkt_len, u8 *pbuf); - #endif +void rtl8812au_set_hw_type(struct dvobj_priv *pdvobj); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8812au(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif #endif #ifdef CONFIG_RTL8814A - void rtl8814au_set_hw_type(struct dvobj_priv *pdvobj); - #ifdef CONFIG_SUPPORT_USB_INT - void interrupt_handler_8814au(_adapter *padapter, u16 pkt_len, u8 *pbuf); - #endif +void rtl8814au_set_hw_type(struct dvobj_priv *pdvobj); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8814au(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif #endif /* CONFIG_RTL8814 */ #ifdef CONFIG_RTL8192E - void rtl8192eu_set_hw_type(struct dvobj_priv *pdvobj); - #ifdef CONFIG_SUPPORT_USB_INT - void interrupt_handler_8192eu(_adapter *padapter, u16 pkt_len, u8 *pbuf); - #endif +void rtl8192eu_set_hw_type(struct dvobj_priv *pdvobj); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8192eu(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif #endif #ifdef CONFIG_RTL8188F - void rtl8188fu_set_hw_type(struct dvobj_priv *pdvobj); - #ifdef CONFIG_SUPPORT_USB_INT - void interrupt_handler_8188fu(_adapter *padapter, u16 pkt_len, u8 *pbuf); - #endif +void rtl8188fu_set_hw_type(struct dvobj_priv *pdvobj); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8188fu(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif #endif #ifdef CONFIG_RTL8723B - void rtl8723bu_set_hw_type(struct dvobj_priv *pdvobj); - #ifdef CONFIG_SUPPORT_USB_INT - void interrupt_handler_8723bu(_adapter *padapter, u16 pkt_len, u8 *pbuf); - #endif +void rtl8723bu_set_hw_type(struct dvobj_priv *pdvobj); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8723bu(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif #endif #ifdef CONFIG_RTL8703B - void rtl8703bu_set_hw_type(struct dvobj_priv *pdvobj); - #ifdef CONFIG_SUPPORT_USB_INT - void interrupt_handler_8703bu(_adapter *padapter, u16 pkt_len, u8 *pbuf); - #endif /* CONFIG_SUPPORT_USB_INT */ +void rtl8703bu_set_hw_type(struct dvobj_priv *pdvobj); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8703bu(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif /* CONFIG_SUPPORT_USB_INT */ #endif /* CONFIG_RTL8703B */ void usb_set_intf_ops(_adapter *padapter, struct _io_ops *pops); #ifdef CONFIG_RTL8723D - void rtl8723du_set_hw_type(struct dvobj_priv *pdvobj); - void rtl8723du_set_intf_ops(struct _io_ops *pops); - void rtl8723du_recv_tasklet(void *priv); - void rtl8723du_xmit_tasklet(void *priv); - #ifdef CONFIG_SUPPORT_USB_INT - void interrupt_handler_8723du(_adapter *padapter, u16 pkt_len, u8 *pbuf); - #endif /* CONFIG_SUPPORT_USB_INT */ +void rtl8723du_set_hw_type(struct dvobj_priv *pdvobj); +void rtl8723du_set_intf_ops(struct _io_ops *pops); +void rtl8723du_recv_tasklet(void *priv); +void rtl8723du_xmit_tasklet(void *priv); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8723du(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif /* CONFIG_SUPPORT_USB_INT */ #endif /* CONFIG_RTL8723D */ enum RTW_USB_SPEED { diff --git a/include/usb_ops_linux.h b/include/usb_ops_linux.h index 039852e..bf59ca0 100644 --- a/include/usb_ops_linux.h +++ b/include/usb_ops_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __USB_OPS_LINUX_H__ #define __USB_OPS_LINUX_H__ @@ -41,12 +36,12 @@ #define RTW_USB_BULKOUT_TIMEOUT 5000/* ms */ #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) - #define _usbctrl_vendorreq_async_callback(urb, regs) _usbctrl_vendorreq_async_callback(urb) - #define usb_bulkout_zero_complete(purb, regs) usb_bulkout_zero_complete(purb) - #define usb_write_mem_complete(purb, regs) usb_write_mem_complete(purb) - #define usb_write_port_complete(purb, regs) usb_write_port_complete(purb) - #define usb_read_port_complete(purb, regs) usb_read_port_complete(purb) - #define usb_read_interrupt_complete(purb, regs) usb_read_interrupt_complete(purb) +#define _usbctrl_vendorreq_async_callback(urb, regs) _usbctrl_vendorreq_async_callback(urb) +#define usb_bulkout_zero_complete(purb, regs) usb_bulkout_zero_complete(purb) +#define usb_write_mem_complete(purb, regs) usb_write_mem_complete(purb) +#define usb_write_port_complete(purb, regs) usb_write_port_complete(purb) +#define usb_read_port_complete(purb, regs) usb_read_port_complete(purb) +#define usb_read_interrupt_complete(purb, regs) usb_read_interrupt_complete(purb) #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 12)) @@ -65,9 +60,9 @@ #ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ - int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val); - int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val); - int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val); +int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val); +int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val); +int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val); #endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */ unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr); @@ -83,7 +78,7 @@ void usb_write_port_cancel(struct intf_hdl *pintfhdl); int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype); #ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request, - u16 value, u16 index, void *pdata, u16 len, u8 requesttype); + u16 value, u16 index, void *pdata, u16 len, u8 requesttype); #endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */ u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr); @@ -97,7 +92,7 @@ u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); void usb_recv_tasklet(void *priv); #ifdef CONFIG_USB_INTERRUPT_IN_PIPE - void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs); - u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr); +void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs); +u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr); #endif #endif diff --git a/include/usb_osintf.h b/include/usb_osintf.h index 9c39520..7e5feed 100644 --- a/include/usb_osintf.h +++ b/include/usb_osintf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __USB_OSINTF_H #define __USB_OSINTF_H diff --git a/include/usb_vendor_req.h b/include/usb_vendor_req.h index d71550e..a003bfb 100644 --- a/include/usb_vendor_req.h +++ b/include/usb_vendor_req.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _USB_VENDOR_REQUEST_H_ #define _USB_VENDOR_REQUEST_H_ @@ -51,9 +46,11 @@ typedef enum _RT_USB_WVALUE { } RT_USB_WVALUE; -/* BOOLEAN usbvendorrequest(PCE_USB_DEVICE CEdevice, RT_USB_BREQUEST bRequest, RT_USB_WVALUE wValue, UCHAR wIndex, PVOID Data, UCHAR DataLength, BOOLEAN isDirectionIn); - * BOOLEAN CEusbGetStatusRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT Index, PVOID Data); - * BOOLEAN CEusbFeatureRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT FeatureSelector, IN USHORT Index); - * BOOLEAN CEusbGetDescriptorRequest(PCE_USB_DEVICE CEdevice, IN short urbLength, IN UCHAR DescriptorType, IN UCHAR Index, IN USHORT LanguageId, IN PVOID TransferBuffer, IN ULONG TransferBufferLength); */ +#if 0 +BOOLEAN usbvendorrequest(PCE_USB_DEVICE CEdevice, RT_USB_BREQUEST bRequest, RT_USB_WVALUE wValue, UCHAR wIndex, PVOID Data, UCHAR DataLength, BOOLEAN isDirectionIn); +BOOLEAN CEusbGetStatusRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT Index, PVOID Data); +BOOLEAN CEusbFeatureRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT FeatureSelector, IN USHORT Index); +BOOLEAN CEusbGetDescriptorRequest(PCE_USB_DEVICE CEdevice, IN short urbLength, IN UCHAR DescriptorType, IN UCHAR Index, IN USHORT LanguageId, IN PVOID TransferBuffer, IN ULONG TransferBufferLength); +#endif #endif diff --git a/include/wifi.h b/include/wifi.h index f432457..8540bf5 100644 --- a/include/wifi.h +++ b/include/wifi.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,19 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _WIFI_H_ #define _WIFI_H_ #ifdef BIT - /* #error "BIT define occurred earlier elsewhere!\n" */ - #undef BIT +/* #error "BIT define occurred earlier elsewhere!\n" */ +#undef BIT #endif #define BIT(x) (1 << (x)) @@ -51,13 +46,13 @@ #define WLAN_WMM_LEN 24 #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE - #define WLAN_MAX_VENDOR_IE_LEN 255 - #define WLAN_MAX_VENDOR_IE_NUM 5 - #define WIFI_BEACON_VENDOR_IE_BIT BIT(0) - #define WIFI_PROBEREQ_VENDOR_IE_BIT BIT(1) - #define WIFI_PROBERESP_VENDOR_IE_BIT BIT(2) - #define WIFI_ASSOCREQ_VENDOR_IE_BIT BIT(3) - #define WIFI_ASSOCRESP_VENDOR_IE_BIT BIT(4) +#define WLAN_MAX_VENDOR_IE_LEN 255 +#define WLAN_MAX_VENDOR_IE_NUM 5 +#define WIFI_BEACON_VENDOR_IE_BIT BIT(0) +#define WIFI_PROBEREQ_VENDOR_IE_BIT BIT(1) +#define WIFI_PROBERESP_VENDOR_IE_BIT BIT(2) +#define WIFI_ASSOCREQ_VENDOR_IE_BIT BIT(3) +#define WIFI_ASSOCRESP_VENDOR_IE_BIT BIT(4) #endif #define P80211CAPTURE_VERSION 0x80211001 @@ -67,7 +62,7 @@ #define WiFiNavUpperUs 30000 /* 30 ms */ #ifdef GREEN_HILL - #pragma pack(1) +#pragma pack(1) #endif enum WIFI_FRAME_TYPE { @@ -95,6 +90,7 @@ enum WIFI_FRAME_SUBTYPE { WIFI_ACTION_NOACK = (BIT(7) | BIT(6) | BIT(5) | WIFI_MGT_TYPE), /* below is for control frame */ + WIFI_BF_REPORT_POLL = (BIT(6) | WIFI_CTRL_TYPE), WIFI_NDPA = (BIT(6) | BIT(4) | WIFI_CTRL_TYPE), WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), @@ -148,33 +144,33 @@ enum WIFI_REASON_CODE { /* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22) */ #if 0 - #define WLAN_REASON_UNSPECIFIED 1 - #define WLAN_REASON_PREV_AUTH_NOT_VALID 2 - #define WLAN_REASON_DEAUTH_LEAVING 3 - #define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 - #define WLAN_REASON_DISASSOC_AP_BUSY 5 - #define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 - #define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 - #define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 - #define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 +#define WLAN_REASON_UNSPECIFIED 1 +#define WLAN_REASON_PREV_AUTH_NOT_VALID 2 +#define WLAN_REASON_DEAUTH_LEAVING 3 +#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 +#define WLAN_REASON_DISASSOC_AP_BUSY 5 +#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 +#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 +#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 +#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 #endif /* IEEE 802.11h */ #define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10 #define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11 #if 0 - /* IEEE 802.11i */ - #define WLAN_REASON_INVALID_IE 13 - #define WLAN_REASON_MICHAEL_MIC_FAILURE 14 - #define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15 - #define WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT 16 - #define WLAN_REASON_IE_IN_4WAY_DIFFERS 17 - #define WLAN_REASON_GROUP_CIPHER_NOT_VALID 18 - #define WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID 19 - #define WLAN_REASON_AKMP_NOT_VALID 20 - #define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21 - #define WLAN_REASON_INVALID_RSN_IE_CAPAB 22 - #define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23 - #define WLAN_REASON_CIPHER_SUITE_REJECTED 24 +/* IEEE 802.11i */ +#define WLAN_REASON_INVALID_IE 13 +#define WLAN_REASON_MICHAEL_MIC_FAILURE 14 +#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15 +#define WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT 16 +#define WLAN_REASON_IE_IN_4WAY_DIFFERS 17 +#define WLAN_REASON_GROUP_CIPHER_NOT_VALID 18 +#define WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID 19 +#define WLAN_REASON_AKMP_NOT_VALID 20 +#define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21 +#define WLAN_REASON_INVALID_RSN_IE_CAPAB 22 +#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23 +#define WLAN_REASON_CIPHER_SUITE_REJECTED 24 #endif enum WIFI_STATUS_CODE { @@ -199,20 +195,20 @@ enum WIFI_STATUS_CODE { /* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23) */ #if 0 - #define WLAN_STATUS_SUCCESS 0 - #define WLAN_STATUS_UNSPECIFIED_FAILURE 1 - #define WLAN_STATUS_CAPS_UNSUPPORTED 10 - #define WLAN_STATUS_REASSOC_NO_ASSOC 11 - #define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 - #define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 - #define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 - #define WLAN_STATUS_CHALLENGE_FAIL 15 - #define WLAN_STATUS_AUTH_TIMEOUT 16 - #define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 - #define WLAN_STATUS_ASSOC_DENIED_RATES 18 +#define WLAN_STATUS_SUCCESS 0 +#define WLAN_STATUS_UNSPECIFIED_FAILURE 1 +#define WLAN_STATUS_CAPS_UNSUPPORTED 10 +#define WLAN_STATUS_REASSOC_NO_ASSOC 11 +#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 +#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 +#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 +#define WLAN_STATUS_CHALLENGE_FAIL 15 +#define WLAN_STATUS_AUTH_TIMEOUT 16 +#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 +#define WLAN_STATUS_ASSOC_DENIED_RATES 18 #endif -/* entended - * IEEE 802.11b */ +/* entended */ +/* IEEE 802.11b */ #define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 #define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 #define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 @@ -368,14 +364,16 @@ enum WIFI_REG_DOMAIN { *(unsigned short *)(pbuf) |= __constant_cpu_to_le16(type); \ } while (0) -#define GetFrameSubType(pbuf) (cpu_to_le16(*(unsigned short *)(pbuf)) & (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))) +#define get_frame_sub_type(pbuf) (cpu_to_le16(*(unsigned short *)(pbuf)) & (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))) + -#define SetFrameSubType(pbuf, type) \ +#define set_frame_sub_type(pbuf, type) \ do { \ *(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); \ *(unsigned short *)(pbuf) |= cpu_to_le16(type); \ } while (0) + #define GetSequence(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) >> 4) #define GetFragNum(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & 0x0f) @@ -396,7 +394,7 @@ enum WIFI_REG_DOMAIN { le16_to_cpu((unsigned short)(0xfff0 & (num << 4))); \ } while (0) -#define SetDuration(pbuf, dur) \ +#define set_duration(pbuf, dur) \ do { \ *(unsigned short *)((SIZE_PTR)(pbuf) + 2) = cpu_to_le16(0xffff & (dur)); \ } while (0) @@ -434,12 +432,13 @@ enum WIFI_REG_DOMAIN { #define GetAddr1Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 4)) -#define GetAddr2Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 10)) +#define get_addr2_ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 10)) #define GetAddr3Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 16)) #define GetAddr4Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 24)) + #define MacAddr_isBcst(addr) \ (\ ((addr[0] == 0xff) && (addr[1] == 0xff) && \ @@ -464,7 +463,7 @@ __inline static unsigned char *get_ra(unsigned char *pframe) __inline static unsigned char *get_ta(unsigned char *pframe) { unsigned char *ta; - ta = GetAddr2Ptr(pframe); + ta = get_addr2_ptr(pframe); return ta; } @@ -499,13 +498,13 @@ __inline static unsigned char *get_sa(unsigned char *pframe) switch (to_fr_ds) { case 0x00: /* ToDs=0, FromDs=0 */ - sa = GetAddr2Ptr(pframe); + sa = get_addr2_ptr(pframe); break; case 0x01: /* ToDs=0, FromDs=1 */ sa = GetAddr3Ptr(pframe); break; case 0x02: /* ToDs=1, FromDs=0 */ - sa = GetAddr2Ptr(pframe); + sa = get_addr2_ptr(pframe); break; default: /* ToDs=1, FromDs=1 */ sa = GetAddr4Ptr(pframe); @@ -525,7 +524,7 @@ __inline static unsigned char *get_hdr_bssid(unsigned char *pframe) sa = GetAddr3Ptr(pframe); break; case 0x01: /* ToDs=0, FromDs=1 */ - sa = GetAddr2Ptr(pframe); + sa = get_addr2_ptr(pframe); break; case 0x02: /* ToDs=1, FromDs=0 */ sa = GetAddr1Ptr(pframe); @@ -589,6 +588,7 @@ __inline static int IsFrameTypeCtrl(unsigned char *pframe) #define _EXT_SUPPORTEDRATES_IE_ 50 #define _HT_CAPABILITY_IE_ 45 +#define _MDIE_ 54 #define _FTIE_ 55 #define _TIMEOUT_ITVL_IE_ 56 #define _SRC_IE_ 59 @@ -601,7 +601,7 @@ __inline static int IsFrameTypeCtrl(unsigned char *pframe) * #define EID_BSSIntolerantChlReport 73 */ #define _RIC_Descriptor_IE_ 75 #ifdef CONFIG_IEEE80211W - #define _MME_IE_ 76 /* 802.11w Management MIC element */ +#define _MME_IE_ 76 /* 802.11w Management MIC element */ #endif /* CONFIG_IEEE80211W */ #define _LINK_ID_IE_ 101 #define _CH_SWITCH_TIMING_ 104 @@ -728,20 +728,20 @@ typedef enum _ELEMENT_ID { #define _IEEE8021X_PSK_ 2 /* WPA with pre-shared key */ #if 0 - #define _NO_PRIVACY_ 0 - #define _WEP_40_PRIVACY_ 1 - #define _TKIP_PRIVACY_ 2 - #define _WRAP_PRIVACY_ 3 - #define _CCMP_PRIVACY_ 4 - #define _WEP_104_PRIVACY_ 5 - #define _WEP_WPA_MIXED_PRIVACY_ 6 /* WEP + WPA */ +#define _NO_PRIVACY_ 0 +#define _WEP_40_PRIVACY_ 1 +#define _TKIP_PRIVACY_ 2 +#define _WRAP_PRIVACY_ 3 +#define _CCMP_PRIVACY_ 4 +#define _WEP_104_PRIVACY_ 5 +#define _WEP_WPA_MIXED_PRIVACY_ 6 /* WEP + WPA */ #endif #ifdef CONFIG_IEEE80211W - #define _MME_IE_LENGTH_ 18 -#endif /* CONFIG_IEEE80211W -*----------------------------------------------------------------------------- -Below is the definition for WMM +#define _MME_IE_LENGTH_ 18 +#endif /* CONFIG_IEEE80211W */ +/*----------------------------------------------------------------------------- + Below is the definition for WMM ------------------------------------------------------------------------------*/ #define _WMM_IE_Length_ 7 /* for WMM STA */ #define _WMM_Para_Element_Length_ 24 @@ -753,11 +753,13 @@ Below is the definition for WMM /* #ifdef CONFIG_80211N_HT */ -#define SetOrderBit(pbuf) \ +#define set_order_bit(pbuf) \ do { \ *(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \ } while (0) + + #define GetOrderBit(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0) #define ACT_CAT_VENDOR 0x7F/* 127 */ @@ -773,10 +775,10 @@ struct rtw_ieee80211_bar { unsigned short frame_control; unsigned short duration; unsigned char ra[6]; - unsigned char ta[6]; - unsigned short control; - unsigned short start_seq_num; - } __attribute__((packed)); + unsigned char ta[6]; + unsigned short control; + unsigned short start_seq_num; +} __attribute__((packed)); #endif /* 802.11 BAR control masks */ @@ -936,6 +938,13 @@ typedef enum _HT_CAP_AMPDU_FACTOR { MAX_AMPDU_FACTOR_64K = 3, } HT_CAP_AMPDU_FACTOR; +typedef enum _VHT_CAP_AMPDU_FACTOR { + MAX_AMPDU_FACTOR_128K = 4, + MAX_AMPDU_FACTOR_256K = 5, + MAX_AMPDU_FACTOR_512K = 6, + MAX_AMPDU_FACTOR_1M = 7, +} VHT_CAP_AMPDU_FACTOR; + typedef enum _HT_CAP_AMPDU_DENSITY { AMPDU_DENSITY_VALUE_0 = 0 , /* For no restriction */ @@ -1043,8 +1052,8 @@ typedef enum _HT_CAP_AMPDU_DENSITY { /* #endif */ -/* ===============WPS Section=============== - * For WPSv1.0 */ +/* ===============WPS Section=============== */ +/* For WPSv1.0 */ #define WPSOUI 0x0050f204 /* WPS attribute ID */ #define WPS_ATTR_VER1 0x104A @@ -1132,8 +1141,8 @@ typedef enum _HT_CAP_AMPDU_DENSITY { #define WPS_ASSOC_STATE_ASSOCIATION_FAILURE 0x03 #define WPS_ASSOC_STATE_IP_FAILURE 0x04 -/* =====================P2P Section===================== - * For P2P */ +/* =====================P2P Section===================== */ +/* For P2P */ #define P2POUI 0x506F9A09 /* P2P Attribute ID */ @@ -1146,7 +1155,7 @@ typedef enum _HT_CAP_AMPDU_DENSITY { #define P2P_ATTR_LISTEN_CH 0x06 #define P2P_ATTR_GROUP_BSSID 0x07 #define P2P_ATTR_EX_LISTEN_TIMING 0x08 -#define P2P_ATTR_INTENTED_IF_ADDR 0x09 +#define P2P_ATTR_INTENDED_IF_ADDR 0x09 #define P2P_ATTR_MANAGEABILITY 0x0A #define P2P_ATTR_CH_LIST 0x0B #define P2P_ATTR_NOA 0x0C @@ -1307,6 +1316,7 @@ enum P2P_PROTO_WK_ID { P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4, P2P_AP_P2P_CH_SWITCH_PROCESS_WK = 5, P2P_RO_CH_WK = 6, + P2P_CANCEL_RO_CH_WK = 7, }; #ifdef CONFIG_P2P_PS @@ -1347,8 +1357,8 @@ enum P2P_PS_MODE { #define WFD_DEVINFO_HDCP_SUPPORT 0x0100 #ifdef CONFIG_TX_MCAST2UNI - #define IP_MCAST_MAC(mac) ((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e)) - #define ICMPV6_MCAST_MAC(mac) ((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff)) +#define IP_MCAST_MAC(mac) ((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e)) +#define ICMPV6_MCAST_MAC(mac) ((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff)) #endif /* CONFIG_TX_MCAST2UNI */ #ifdef CONFIG_IOCTL_CFG80211 @@ -1372,18 +1382,18 @@ struct rtw_regulatory { #endif #ifdef CONFIG_WAPI_SUPPORT - #ifndef IW_AUTH_WAPI_VERSION_1 - #define IW_AUTH_WAPI_VERSION_1 0x00000008 - #endif - #ifndef IW_AUTH_KEY_MGMT_WAPI_PSK - #define IW_AUTH_KEY_MGMT_WAPI_PSK 0x04 - #endif - #ifndef IW_AUTH_WAPI_ENABLED - #define IW_AUTH_WAPI_ENABLED 0x20 - #endif - #ifndef IW_ENCODE_ALG_SM4 - #define IW_ENCODE_ALG_SM4 0x20 - #endif +#ifndef IW_AUTH_WAPI_VERSION_1 +#define IW_AUTH_WAPI_VERSION_1 0x00000008 +#endif +#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK +#define IW_AUTH_KEY_MGMT_WAPI_PSK 0x04 +#endif +#ifndef IW_AUTH_WAPI_ENABLED +#define IW_AUTH_WAPI_ENABLED 0x20 +#endif +#ifndef IW_ENCODE_ALG_SM4 +#define IW_ENCODE_ALG_SM4 0x20 +#endif #endif #endif /* _WIFI_H_ */ diff --git a/include/wlan_bssdef.h b/include/wlan_bssdef.h index 9e446d7..84cb2d4 100644 --- a/include/wlan_bssdef.h +++ b/include/wlan_bssdef.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __WLAN_BSSDEF_H__ #define __WLAN_BSSDEF_H__ @@ -519,7 +514,7 @@ typedef struct _NDIS_802_11_TEST { #endif /* PLATFORM_FREEBSD */ #ifndef Ndis802_11APMode - #define Ndis802_11APMode (Ndis802_11InfrastructureMax+1) +#define Ndis802_11APMode (Ndis802_11InfrastructureMax+1) #endif typedef struct _WLAN_PHY_INFO { @@ -546,8 +541,8 @@ typedef struct _WLAN_BCN_INFO { * WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz() */ #ifdef PLATFORM_WINDOWS - #pragma pack(push) - #pragma pack(1) +#pragma pack(push) +#pragma pack(1) #endif typedef struct _WLAN_BSSID_EX { ULONG Length; @@ -565,11 +560,11 @@ typedef struct _WLAN_BSSID_EX { UCHAR IEs[MAX_IE_SZ]; /* (timestamp, beacon interval, and capability information) */ } #ifndef PLATFORM_WINDOWS - __attribute__((packed)) +__attribute__((packed)) #endif WLAN_BSSID_EX, *PWLAN_BSSID_EX; #ifdef PLATFORM_WINDOWS - #pragma pack(pop) +#pragma pack(pop) #endif #define BSS_EX_IES(bss_ex) ((bss_ex)->IEs) diff --git a/include/xmit_osdep.h b/include/xmit_osdep.h index d2c86e9..70070a8 100644 --- a/include/xmit_osdep.h +++ b/include/xmit_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __XMIT_OSDEP_H_ #define __XMIT_OSDEP_H_ @@ -33,11 +28,11 @@ struct pkt_file { #ifdef PLATFORM_WINDOWS #ifdef PLATFORM_OS_XP - #ifdef CONFIG_USB_HCI - #include - #include - #include - #endif +#ifdef CONFIG_USB_HCI +#include +#include +#include +#endif #endif #ifdef CONFIG_GSPI_HCI @@ -54,28 +49,28 @@ extern NDIS_STATUS rtw_xmit_entry( IN UINT flags ); -#endif +#endif /* PLATFORM_WINDOWS */ #ifdef PLATFORM_FREEBSD - #define NR_XMITFRAME 256 - extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); - extern void rtw_xmit_entry_wrap(struct ifnet *pifp); +#define NR_XMITFRAME 256 +extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); +extern void rtw_xmit_entry_wrap(struct ifnet *pifp); #endif /* PLATFORM_FREEBSD */ #ifdef PLATFORM_LINUX - #define NR_XMITFRAME 256 +#define NR_XMITFRAME 256 - struct xmit_priv; - struct pkt_attrib; - struct sta_xmit_priv; - struct xmit_frame; - struct xmit_buf; +struct xmit_priv; +struct pkt_attrib; +struct sta_xmit_priv; +struct xmit_frame; +struct xmit_buf; - extern int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); - extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); +extern int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); +extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); -#endif +#endif /* PLATFORM_LINUX */ void rtw_os_xmit_schedule(_adapter *padapter); diff --git a/os_dep/linux/custom_gpio_linux.c b/os_dep/linux/custom_gpio_linux.c index 7f9a67f..23401b7 100644 --- a/os_dep/linux/custom_gpio_linux.c +++ b/os_dep/linux/custom_gpio_linux.c @@ -1,7 +1,6 @@ /****************************************************************************** - * Customer code to add GPIO control during WLAN start/stop * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include "drv_types.h" #ifdef CONFIG_PLATFORM_SPRD @@ -29,27 +23,27 @@ #if !(defined ANDROID_2X) #ifdef CONFIG_RTL8188E - #include - #include +#include +#include #endif /* CONFIG_RTL8188E */ #ifndef GPIO_WIFI_POWER - #define GPIO_WIFI_POWER -1 +#define GPIO_WIFI_POWER -1 #endif /* !GPIO_WIFI_POWER */ #ifndef GPIO_WIFI_RESET - #define GPIO_WIFI_RESET -1 +#define GPIO_WIFI_RESET -1 #endif /* !GPIO_WIFI_RESET */ #ifndef GPIO_WIFI_PWDN - #define GPIO_WIFI_PWDN -1 +#define GPIO_WIFI_PWDN -1 #endif /* !GPIO_WIFI_RESET */ #ifdef CONFIG_GSPI_HCI - extern unsigned int oob_irq; +extern unsigned int oob_irq; #endif /* CONFIG_GSPI_HCI */ #ifdef CONFIG_SDIO_HCI - extern int rtw_mp_mode; +extern int rtw_mp_mode; #else /* !CONFIG_SDIO_HCI */ #endif /* !CONFIG_SDIO_HCI */ @@ -162,11 +156,11 @@ void rtw_wifi_gpio_wlan_ctrl(int onoff) #include #ifdef CONFIG_RTL8188E - extern int sprd_3rdparty_gpio_wifi_power; +extern int sprd_3rdparty_gpio_wifi_power; #endif extern int sprd_3rdparty_gpio_wifi_pwd; #if defined(CONFIG_RTL8723B) - extern int sprd_3rdparty_gpio_bt_reset; +extern int sprd_3rdparty_gpio_bt_reset; #endif int rtw_wifi_gpio_init(void) diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index 2dd125e..7a18ad0 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,15 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _IOCTL_CFG80211_C_ #include +#include #ifdef CONFIG_IOCTL_CFG80211 @@ -29,13 +25,22 @@ #endif #endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) -#define STATION_INFO_SIGNAL BIT(NL80211_STA_INFO_SIGNAL) -#define STATION_INFO_TX_BITRATE BIT(NL80211_STA_INFO_TX_BITRATE) -#define STATION_INFO_RX_PACKETS BIT(NL80211_STA_INFO_RX_PACKETS) -#define STATION_INFO_TX_PACKETS BIT(NL80211_STA_INFO_TX_PACKETS) -#define STATION_INFO_ASSOC_REQ_IES 0 -#endif /* Linux kernel >= 4.0.0 */ + +#ifdef CONFIG_CENTOS_7 + #define STATION_INFO_SIGNAL BIT(NL80211_STA_INFO_SIGNAL) + #define STATION_INFO_TX_BITRATE BIT(NL80211_STA_INFO_TX_BITRATE) + #define STATION_INFO_RX_PACKETS BIT(NL80211_STA_INFO_RX_PACKETS) + #define STATION_INFO_TX_PACKETS BIT(NL80211_STA_INFO_TX_PACKETS) + #define STATION_INFO_ASSOC_REQ_IES 0 +#else + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) + #define STATION_INFO_SIGNAL BIT(NL80211_STA_INFO_SIGNAL) + #define STATION_INFO_TX_BITRATE BIT(NL80211_STA_INFO_TX_BITRATE) + #define STATION_INFO_RX_PACKETS BIT(NL80211_STA_INFO_RX_PACKETS) + #define STATION_INFO_TX_PACKETS BIT(NL80211_STA_INFO_TX_PACKETS) + #define STATION_INFO_ASSOC_REQ_IES 0 + #endif /* Linux kernel >= 4.0.0 */ +#endif #include @@ -66,8 +71,12 @@ #define NL80211_WAPI_VERSION_1 (1 << 2) #endif -#endif +#endif /* CONFIG_WAPI_SUPPORT */ +#ifdef CONFIG_RTW_80211R +#define WLAN_AKM_SUITE_FT_8021X 0x000FAC03 +#define WLAN_AKM_SUITE_FT_PSK 0x000FAC04 +#endif static const u32 rtw_cipher_suites[] = { WLAN_CIPHER_SUITE_WEP40, @@ -85,26 +94,26 @@ static const u32 rtw_cipher_suites[] = { #define RATETAB_ENT(_rate, _rateid, _flags) \ { \ .bitrate = (_rate), \ - .hw_value = (_rateid), \ - .flags = (_flags), \ + .hw_value = (_rateid), \ + .flags = (_flags), \ } #define CHAN2G(_channel, _freq, _flags) { \ .band = NL80211_BAND_2GHZ, \ - .center_freq = (_freq), \ - .hw_value = (_channel), \ - .flags = (_flags), \ - .max_antenna_gain = 0, \ - .max_power = 30, \ + .center_freq = (_freq), \ + .hw_value = (_channel), \ + .flags = (_flags), \ + .max_antenna_gain = 0, \ + .max_power = 30, \ } #define CHAN5G(_channel, _flags) { \ - .band = NL80211_BAND_5GHZ, \ - .center_freq = 5000 + (5 * (_channel)), \ - .hw_value = (_channel), \ - .flags = (_flags), \ - .max_antenna_gain = 0, \ - .max_power = 30, \ + .band = NL80211_BAND_5GHZ, \ + .center_freq = 5000 + (5 * (_channel)), \ + .hw_value = (_channel), \ + .flags = (_flags), \ + .max_antenna_gain = 0, \ + .max_power = 30, \ } #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) @@ -120,6 +129,9 @@ static const struct wiphy_wowlan_support wowlan_stub = { .pattern_min_len = 0, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) .max_pkt_offset = 0, + #ifdef CONFIG_CENTOS_7 + .max_nd_match_sets = 0, + #endif #endif }; #endif @@ -144,10 +156,8 @@ static struct ieee80211_rate rtw_rates[] = { #define rtw_g_rates (rtw_rates + 0) #define RTW_G_RATES_NUM 12 -#define RTW_2G_CHANNELS_NUM 14 -#define RTW_5G_CHANNELS_NUM 37 - -static struct ieee80211_channel rtw_2ghz_channels[] = { +/* from center_ch_2g */ +static struct ieee80211_channel rtw_2ghz_channels[MAX_CHANNEL_NUM_2G] = { CHAN2G(1, 2412, 0), CHAN2G(2, 2417, 0), CHAN2G(3, 2422, 0), @@ -164,72 +174,65 @@ static struct ieee80211_channel rtw_2ghz_channels[] = { CHAN2G(14, 2484, 0), }; -static struct ieee80211_channel rtw_5ghz_a_channels[] = { - CHAN5G(34, 0), CHAN5G(36, 0), - CHAN5G(38, 0), CHAN5G(40, 0), - CHAN5G(42, 0), CHAN5G(44, 0), - CHAN5G(46, 0), CHAN5G(48, 0), - CHAN5G(52, 0), CHAN5G(56, 0), - CHAN5G(60, 0), CHAN5G(64, 0), - CHAN5G(100, 0), CHAN5G(104, 0), - CHAN5G(108, 0), CHAN5G(112, 0), - CHAN5G(116, 0), CHAN5G(120, 0), - CHAN5G(124, 0), CHAN5G(128, 0), - CHAN5G(132, 0), CHAN5G(136, 0), - CHAN5G(140, 0), CHAN5G(149, 0), - CHAN5G(153, 0), CHAN5G(157, 0), - CHAN5G(161, 0), CHAN5G(165, 0), - CHAN5G(184, 0), CHAN5G(188, 0), - CHAN5G(192, 0), CHAN5G(196, 0), - CHAN5G(200, 0), CHAN5G(204, 0), - CHAN5G(208, 0), CHAN5G(212, 0), - CHAN5G(216, 0), +/* from center_ch_5g_20m */ +static struct ieee80211_channel rtw_5ghz_a_channels[MAX_CHANNEL_NUM_5G] = { + CHAN5G(36, 0), CHAN5G(40, 0), CHAN5G(44, 0), CHAN5G(48, 0), + + CHAN5G(52, 0), CHAN5G(56, 0), CHAN5G(60, 0), CHAN5G(64, 0), + + CHAN5G(100, 0), CHAN5G(104, 0), CHAN5G(108, 0), CHAN5G(112, 0), + CHAN5G(116, 0), CHAN5G(120, 0), CHAN5G(124, 0), CHAN5G(128, 0), + CHAN5G(132, 0), CHAN5G(136, 0), CHAN5G(140, 0), CHAN5G(144, 0), + + CHAN5G(149, 0), CHAN5G(153, 0), CHAN5G(157, 0), CHAN5G(161, 0), + CHAN5G(165, 0), CHAN5G(169, 0), CHAN5G(173, 0), CHAN5G(177, 0), }; -void rtw_2g_channels_init(struct ieee80211_channel *channels) { - _rtw_memcpy((void *)channels, (void *)rtw_2ghz_channels, - sizeof(struct ieee80211_channel) * RTW_2G_CHANNELS_NUM - ); +void rtw_2g_channels_init(struct ieee80211_channel *channels) +{ + _rtw_memcpy((void *)channels, (void *)rtw_2ghz_channels, sizeof(rtw_2ghz_channels)); } -void rtw_5g_channels_init(struct ieee80211_channel *channels) { - _rtw_memcpy((void *)channels, (void *)rtw_5ghz_a_channels, - sizeof(struct ieee80211_channel) * RTW_5G_CHANNELS_NUM - ); +void rtw_5g_channels_init(struct ieee80211_channel *channels) +{ + _rtw_memcpy((void *)channels, (void *)rtw_5ghz_a_channels, sizeof(rtw_5ghz_a_channels)); } -void rtw_2g_rates_init(struct ieee80211_rate *rates) { +void rtw_2g_rates_init(struct ieee80211_rate *rates) +{ _rtw_memcpy(rates, rtw_g_rates, - sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM - ); + sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM + ); } -void rtw_5g_rates_init(struct ieee80211_rate *rates) { +void rtw_5g_rates_init(struct ieee80211_rate *rates) +{ _rtw_memcpy(rates, rtw_a_rates, - sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM - ); + sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM + ); } struct ieee80211_supported_band *rtw_spt_band_alloc( - enum nl80211_band band -) { + enum nl80211_band band +) +{ struct ieee80211_supported_band *spt_band = NULL; int n_channels, n_bitrates; if (band == NL80211_BAND_2GHZ) { - n_channels = RTW_2G_CHANNELS_NUM; + n_channels = MAX_CHANNEL_NUM_2G; n_bitrates = RTW_G_RATES_NUM; } else if (band == NL80211_BAND_5GHZ) { - n_channels = RTW_5G_CHANNELS_NUM; + n_channels = MAX_CHANNEL_NUM_5G; n_bitrates = RTW_A_RATES_NUM; } else goto exit; spt_band = (struct ieee80211_supported_band *)rtw_zmalloc( - sizeof(struct ieee80211_supported_band) - + sizeof(struct ieee80211_channel) * n_channels - + sizeof(struct ieee80211_rate) * n_bitrates + sizeof(struct ieee80211_supported_band) + + sizeof(struct ieee80211_channel) * n_channels + + sizeof(struct ieee80211_rate) * n_bitrates ); if (!spt_band) goto exit; @@ -255,20 +258,37 @@ struct ieee80211_supported_band *rtw_spt_band_alloc( return spt_band; } -void rtw_spt_band_free(struct ieee80211_supported_band *spt_band) { +void rtw_spt_band_free(struct ieee80211_supported_band *spt_band) +{ u32 size = 0; if (!spt_band) return; +#ifdef CONFIG_CENTOS_7 if (spt_band->band == NL80211_BAND_2GHZ) { +#else + #if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE) + if (spt_band->band == NL80211_BAND_2GHZ) { + #else + if (spt_band->band == IEEE80211_BAND_2GHZ) { + #endif +#endif size = sizeof(struct ieee80211_supported_band) - + sizeof(struct ieee80211_channel) * RTW_2G_CHANNELS_NUM - + sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM; + + sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_2G + + sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM; +#ifdef CONFIG_CENTOS_7 } else if (spt_band->band == NL80211_BAND_5GHZ) { +#else + #if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE) + } else if (spt_band->band == NL80211_BAND_5GHZ) { + #else + } else if (spt_band->band == IEEE80211_BAND_5GHZ) { + #endif +#endif size = sizeof(struct ieee80211_supported_band) - + sizeof(struct ieee80211_channel) * RTW_5G_CHANNELS_NUM - + sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM; + + sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_5G + + sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM; } else { } @@ -323,10 +343,18 @@ static const struct ieee80211_txrx_stypes BIT(IEEE80211_STYPE_DEAUTH >> 4) | BIT(IEEE80211_STYPE_ACTION >> 4) }, +#if defined(RTW_DEDICATED_P2P_DEVICE) + [NL80211_IFTYPE_P2P_DEVICE] = { + .tx = 0xffff, + .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | + BIT(IEEE80211_STYPE_PROBE_REQ >> 4) + }, +#endif }; #endif -static u64 rtw_get_systime_us(void) { +static u64 rtw_get_systime_us(void) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) struct timespec ts; get_monotonic_boottime(&ts); @@ -338,8 +366,40 @@ static u64 rtw_get_systime_us(void) { #endif } +/* Try to remove non target BSS's SR to reduce PBC overlap rate */ +static int rtw_cfg80211_clear_wps_sr_of_non_target_bss(_adapter *padapter, struct wlan_network *pnetwork, struct cfg80211_ssid *req_ssid) +{ + struct rtw_wdev_priv *wdev_data = adapter_wdev_data(padapter); + int ret = 0; + u8 *psr = NULL, sr = 0; + NDIS_802_11_SSID *pssid = &pnetwork->network.Ssid; + u32 wpsielen = 0; + u8 *wpsie = NULL; + + if (pssid->SsidLength == req_ssid->ssid_len + && _rtw_memcmp(pssid->Ssid, req_ssid->ssid, req_ssid->ssid_len) == _TRUE) + goto exit; + + wpsie = rtw_get_wps_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_ + , pnetwork->network.IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen); + if (wpsie && wpsielen > 0) + psr = rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_SELECTED_REGISTRAR, &sr, NULL); + + if (psr && sr) { + if (0) + RTW_INFO("clear sr of non target bss:%s("MAC_FMT")\n" + , pssid->Ssid, MAC_ARG(pnetwork->network.MacAddress)); + *psr = 0; /* clear sr */ + ret = 1; + } + +exit: + return ret; +} + #define MAX_BSSINFO_LEN 1000 -struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork) { +struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork) +{ struct ieee80211_channel *notify_channel; struct cfg80211_bss *bss = NULL; /* struct ieee80211_supported_band *band; */ @@ -391,69 +451,6 @@ struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_net } #endif /* !CONFIG_WAPI_SUPPORT */ - /* To reduce PBC Overlap rate */ - /* _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); */ - if (adapter_wdev_data(padapter)->scan_request != NULL) { - u8 *psr = NULL, sr = 0; - NDIS_802_11_SSID *pssid = &pnetwork->network.Ssid; - struct cfg80211_scan_request *request = adapter_wdev_data(padapter)->scan_request; - struct cfg80211_ssid *ssids = request->ssids; - u32 wpsielen = 0; - u8 *wpsie = NULL; - - wpsie = rtw_get_wps_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, pnetwork->network.IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen); - - if (wpsie && wpsielen > 0) - psr = rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL); - - if (sr != 0) { - if (request->n_ssids == 1 && request->n_channels == 1) { /* it means under processing WPS */ - RTW_INFO("ssid=%s, len=%d\n", pssid->Ssid, pssid->SsidLength); - - if (ssids[0].ssid_len == 0) { - } else if (pssid->SsidLength == ssids[0].ssid_len && - _rtw_memcmp(pssid->Ssid, ssids[0].ssid, ssids[0].ssid_len)) - RTW_INFO("%s, got sr and ssid match!\n", __func__); - else { - if (psr != NULL) - *psr = 0; /* clear sr */ - -#if 0 - WLAN_BSSID_EX *pselect_network = &pnetwork->network; - struct cfg80211_bss *pselect_bss = NULL; - struct ieee80211_channel *notify_channel = NULL; - u32 freq; - - RTW_INFO("%s, got sr, but ssid mismatch, to remove this bss\n", __func__); - - freq = rtw_ch2freq(pselect_network->Configuration.DSConfig); - notify_channel = ieee80211_get_channel(wiphy, freq); - pselect_bss = cfg80211_get_bss(wiphy, NULL/*notify_channel*/, - pselect_network->MacAddress, pselect_network->Ssid.Ssid, - pselect_network->Ssid.SsidLength, 0/*WLAN_CAPABILITY_ESS*/, - 0/*WLAN_CAPABILITY_ESS*/); - - if (pselect_bss) { - RTW_INFO("%s, got bss for cfg80211 for unlinking bss\n", __func__); - - cfg80211_unlink_bss(wiphy, pselect_bss); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) - cfg80211_put_bss(wiphy, pselect_bss); -#else - cfg80211_put_bss(pselect_bss); -#endif - - } - - goto exit; -#endif - } - } - } - } - /* _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); */ - - channel = pnetwork->network.Configuration.DSConfig; freq = rtw_ch2freq(channel); notify_channel = ieee80211_get_channel(wiphy, freq); @@ -471,7 +468,7 @@ struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_net /* We've set wiphy's signal_type as CFG80211_SIGNAL_TYPE_MBM: signal strength in mBm (100*dBm) */ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && - is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { + is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { notify_signal = 100 * translate_percentage_to_dbm(padapter->recvpriv.signal_strength); /* dbm */ } else { notify_signal = 100 * translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength); /* dbm */ @@ -497,10 +494,10 @@ struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_net if (pnetwork->network.Reserved[0] == 1) { /* WIFI_BEACON */ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); - SetFrameSubType(pbuf, WIFI_BEACON); + set_frame_sub_type(pbuf, WIFI_BEACON); } else { _rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN); - SetFrameSubType(pbuf, WIFI_PROBERSP); + set_frame_sub_type(pbuf, WIFI_PROBERSP); } _rtw_memcpy(pwlanhdr->addr2, pnetwork->network.MacAddress, ETH_ALEN); @@ -514,21 +511,19 @@ struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_net len += pnetwork->network.IELength; - /* #ifdef CONFIG_P2P */ - /* if(rtw_get_p2p_ie(pnetwork->network.IEs+12, pnetwork->network.IELength-12, NULL, NULL)) */ - /* { */ - /* RTW_INFO("%s, got p2p_ie\n", __func__); */ - /* } */ - /* #endif */ + #if defined(CONFIG_P2P) && 0 + if(rtw_get_p2p_ie(pnetwork->network.IEs+12, pnetwork->network.IELength-12, NULL, NULL)) + RTW_INFO("%s, got p2p_ie\n", __func__); + #endif #if 1 bss = cfg80211_inform_bss_frame(wiphy, notify_channel, (struct ieee80211_mgmt *)pbuf, - len, notify_signal, GFP_ATOMIC); + len, notify_signal, GFP_ATOMIC); #else bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)pnetwork->network.MacAddress, - notify_timestamp, notify_capability, notify_interval, notify_ie, - notify_ielen, notify_signal, GFP_ATOMIC/*GFP_KERNEL*/); + notify_timestamp, notify_capability, notify_interval, notify_ie, + notify_ielen, notify_signal, GFP_ATOMIC/*GFP_KERNEL*/); #endif if (unlikely(!bss)) { @@ -549,23 +544,17 @@ struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_net #endif /* COMPAT_KERNEL_RELEASE */ #endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 38) */ - /* - { - if( bss->information_elements == bss->proberesp_ies) - { - if( bss->len_information_elements != bss->len_proberesp_ies) - { - RTW_INFO("error!, len_information_elements != bss->len_proberesp_ies\n"); - } - - } - else if(bss->len_information_elements < bss->len_beacon_ies) - { - bss->information_elements = bss->beacon_ies; - bss->len_information_elements = bss->len_beacon_ies; - } +#if 0 + { + if (bss->information_elements == bss->proberesp_ies) { + if (bss->len_information_elements != bss->len_proberesp_ies) + RTW_INFO("error!, len_information_elements != bss->len_proberesp_ies\n"); + } else if (bss->len_information_elements < bss->len_beacon_ies) { + bss->information_elements = bss->beacon_ies; + bss->len_information_elements = bss->len_beacon_ies; } - */ + } +#endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) cfg80211_put_bss(wiphy, bss); #else @@ -585,7 +574,8 @@ struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_net return _TRUE if bss is valid, _FALSE for not found. */ -int rtw_cfg80211_check_bss(_adapter *padapter) { +int rtw_cfg80211_check_bss(_adapter *padapter) +{ WLAN_BSSID_EX *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network); struct cfg80211_bss *bss = NULL; struct ieee80211_channel *notify_channel = NULL; @@ -597,9 +587,14 @@ int rtw_cfg80211_check_bss(_adapter *padapter) { freq = rtw_ch2freq(pnetwork->Configuration.DSConfig); notify_channel = ieee80211_get_channel(padapter->rtw_wdev->wiphy, freq); bss = cfg80211_get_bss(padapter->rtw_wdev->wiphy, notify_channel, - pnetwork->MacAddress, pnetwork->Ssid.Ssid, - pnetwork->Ssid.SsidLength, - WLAN_CAPABILITY_ESS, WLAN_CAPABILITY_ESS); + pnetwork->MacAddress, pnetwork->Ssid.Ssid, + pnetwork->Ssid.SsidLength, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) + pnetwork->InfrastructureMode == Ndis802_11Infrastructure?IEEE80211_BSS_TYPE_ESS:IEEE80211_BSS_TYPE_IBSS, + IEEE80211_PRIVACY(pnetwork->Privacy)); +#else + pnetwork->InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS, pnetwork->InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS); +#endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) cfg80211_put_bss(padapter->rtw_wdev->wiphy, bss); @@ -610,15 +605,22 @@ int rtw_cfg80211_check_bss(_adapter *padapter) { return bss != NULL; } -void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter) { +void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter) +{ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_network *cur_network = &(pmlmepriv->cur_network); struct wireless_dev *pwdev = padapter->rtw_wdev; struct cfg80211_bss *bss = NULL; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) +#ifdef CONFIG_CENTOS_7 struct wiphy *wiphy = pwdev->wiphy; int freq = 2412; struct ieee80211_channel *notify_channel; +#else + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) + struct wiphy *wiphy = pwdev->wiphy; + int freq = 2412; + struct ieee80211_channel *notify_channel; + #endif #endif RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); @@ -654,8 +656,8 @@ void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter) { rtw_warn_on(1); if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE - && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE - ) { + && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE + ) { if (!rtw_cfg80211_inform_bss(padapter, scanned)) RTW_INFO(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter)); else { @@ -671,18 +673,26 @@ void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter) { RTW_PRINT(FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter)); } /* notify cfg80211 that device joined an IBSS */ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) +#ifdef CONFIG_CENTOS_7 notify_channel = ieee80211_get_channel(wiphy, freq); cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, notify_channel, GFP_ATOMIC); #else - cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, GFP_ATOMIC); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) + notify_channel = ieee80211_get_channel(wiphy, freq); + cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, notify_channel, GFP_ATOMIC); + #else + cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, GFP_ATOMIC); + #endif #endif } -void rtw_cfg80211_indicate_connect(_adapter *padapter) { +void rtw_cfg80211_indicate_connect(_adapter *padapter) +{ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_network *cur_network = &(pmlmepriv->cur_network); struct wireless_dev *pwdev = padapter->rtw_wdev; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + _irqL irqL; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif @@ -690,10 +700,10 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) { RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); if (pwdev->iftype != NL80211_IFTYPE_STATION -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - && pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT -#endif - ) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + && pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT + #endif + ) return; if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) @@ -701,12 +711,14 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) { #ifdef CONFIG_P2P if (pwdinfo->driver_interface == DRIVER_CFG80211) { + #if !RTW_P2P_GROUP_INTERFACE if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); } + #endif } #endif /* CONFIG_P2P */ @@ -722,8 +734,8 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) { } if (_rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE - && _rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE - ) { + && _rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE + ) { if (!rtw_cfg80211_inform_bss(padapter, scanned)) RTW_INFO(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter)); else { @@ -731,9 +743,9 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) { } } else { RTW_INFO("scanned: %s("MAC_FMT"), cur: %s("MAC_FMT")\n", - scanned->network.Ssid.Ssid, MAC_ARG(scanned->network.MacAddress), - pnetwork->Ssid.Ssid, MAC_ARG(pnetwork->MacAddress) - ); + scanned->network.Ssid.Ssid, MAC_ARG(scanned->network.MacAddress), + pnetwork->Ssid.Ssid, MAC_ARG(pnetwork->MacAddress) + ); rtw_warn_on(1); } } @@ -742,8 +754,10 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) { if (!rtw_cfg80211_check_bss(padapter)) RTW_PRINT(FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter)); + _enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + if (rtw_to_roam(padapter) > 0) { -#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) + #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) struct wiphy *wiphy = pwdev->wiphy; struct ieee80211_channel *notify_channel; u32 freq; @@ -751,50 +765,67 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) { freq = rtw_ch2freq(channel); notify_channel = ieee80211_get_channel(wiphy, freq); -#endif + #endif RTW_INFO(FUNC_ADPT_FMT" call cfg80211_roamed\n", FUNC_ADPT_ARG(padapter)); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) - struct cfg80211_roam_info roam_info = { - .channel = notify_channel, - .bssid = cur_network->network.MacAddress, - .req_ie = pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2, - .req_ie_len = pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2, - .resp_ie = pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6, - .resp_ie_len = pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 - }; - cfg80211_roamed(padapter->pnetdev,&roam_info, GFP_ATOMIC); -#else - cfg80211_roamed(padapter->pnetdev -#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) - , notify_channel -#endif - , cur_network->network.MacAddress - , pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2 - , pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2 - , pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 - , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 - , GFP_ATOMIC); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) + struct cfg80211_roam_info roam_info = { + .channel = notify_channel, + .bssid = cur_network->network.MacAddress, + .req_ie = pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2, + .req_ie_len = pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2, + .resp_ie = pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6, + .resp_ie_len = pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 + }; + cfg80211_roamed(padapter->pnetdev,&roam_info, GFP_ATOMIC); + #else + cfg80211_roamed(padapter->pnetdev + #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) + , notify_channel + #endif + , cur_network->network.MacAddress + , pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2 + , pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2 + , pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 + , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 + , GFP_ATOMIC); + #endif +#ifdef CONFIG_RTW_80211R + if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) + rtw_set_ft_status(padapter, RTW_FT_ASSOCIATED_STA); #endif } else { -#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) - RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state); -#endif - cfg80211_connect_result(padapter->pnetdev, cur_network->network.MacAddress - , pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2 - , pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2 - , pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 - , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 - , WLAN_STATUS_SUCCESS, GFP_ATOMIC); -#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) - RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state); -#endif - } + #ifdef CONFIG_CENTOS_7 + #else + #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) + RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state); + #endif + #endif + rtw_cfg80211_connect_result(pwdev, cur_network->network.MacAddress + , pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2 + , pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2 + , pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 + , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 + , WLAN_STATUS_SUCCESS, GFP_ATOMIC); + #ifdef CONFIG_CENTOS_7 + #else + #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) + RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state); + #endif + #endif + } + + rtw_wdev_free_connect_req(pwdev_priv); + + _exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL); } -void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated) { +void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated) +{ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wireless_dev *pwdev = padapter->rtw_wdev; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + _irqL irqL; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif @@ -806,10 +837,10 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally reason = 0; if (pwdev->iftype != NL80211_IFTYPE_STATION -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - && pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT -#endif - ) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + && pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT + #endif + ) return; if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) @@ -820,9 +851,11 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + #if RTW_P2P_GROUP_INTERFACE + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) if (pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT) -#endif + #endif + #endif rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); @@ -830,50 +863,46 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally } #endif /* CONFIG_P2P */ -#ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 - if (!padapter->mlmepriv.not_indic_disco || padapter->ndev_unregistering) { -#else - { -#endif -#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) - RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state); + _enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + + if (padapter->ndev_unregistering || !rtw_wdev_not_indic_disco(pwdev_priv)) { + #ifdef CONFIG_CENTOS_7 + #else + #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) + RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state); + + if (pwdev->sme_state == CFG80211_SME_CONNECTING) { + RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result\n", FUNC_ADPT_ARG(padapter)); + rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0, + WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC); + } else if (pwdev->sme_state == CFG80211_SME_CONNECTED) { + RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter)); + rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC); + } - if (pwdev->sme_state == CFG80211_SME_CONNECTING) - cfg80211_connect_result(padapter->pnetdev, NULL, NULL, 0, NULL, 0, - WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC/*GFP_KERNEL*/); - else if (pwdev->sme_state == CFG80211_SME_CONNECTED) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) - cfg80211_disconnected(padapter->pnetdev, reason, NULL, 0, locally_generated, GFP_ATOMIC); -#else - cfg80211_disconnected(padapter->pnetdev, 0, NULL, 0, GFP_ATOMIC); -#endif - } - /* else */ - /* RTW_INFO("pwdev->sme_state=%d\n", pwdev->sme_state); */ + RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state); + #else + if (pwdev_priv->connect_req) { + RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result\n", FUNC_ADPT_ARG(padapter)); + rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0, + WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC); + } else { + RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter)); + rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC); + } + #endif + #endif + } - RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state); -#else + rtw_wdev_free_connect_req(pwdev_priv); - if (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) - RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter)); - cfg80211_disconnected(padapter->pnetdev, reason, NULL, 0, locally_generated, GFP_ATOMIC); -#else - RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter)); - cfg80211_disconnected(padapter->pnetdev, 0, NULL, 0, GFP_ATOMIC); -#endif - } else { - RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result\n", FUNC_ADPT_ARG(padapter)); - cfg80211_connect_result(padapter->pnetdev, NULL, NULL, 0, NULL, 0, - WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC); - } -#endif - } + _exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL); } #ifdef CONFIG_AP_MODE -static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) { +static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +{ int ret = 0; u32 wep_key_idx, wep_key_len, wep_total_len; struct sta_info *psta = NULL, *pbcmc_sta = NULL; @@ -895,13 +924,13 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { if (param->u.crypt.idx >= WEP_KEYS #ifdef CONFIG_IEEE80211W - && param->u.crypt.idx > BIP_MAX_KEYID + && param->u.crypt.idx > BIP_MAX_KEYID #endif /* CONFIG_IEEE80211W */ - ) { + ) { ret = -EINVAL; goto exit; } @@ -966,8 +995,7 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } - if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) { /* */ - /* group key */ + if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) { /* group key */ if (param->u.crypt.set_tx == 0) { /* group key */ if (strcmp(param->u.crypt.alg, "WEP") == 0) { RTW_INFO("%s, set group_key, WEP\n", __FUNCTION__); @@ -1135,7 +1163,8 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } #endif -static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) { +static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +{ int ret = 0; u32 wep_key_idx, wep_key_len, wep_total_len; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -1145,7 +1174,6 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param struct wifidirect_info *pwdinfo = &padapter->wdinfo; #endif /* CONFIG_P2P */ - _func_enter_; RTW_INFO("%s\n", __func__); @@ -1158,13 +1186,13 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param } if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { if (param->u.crypt.idx >= WEP_KEYS #ifdef CONFIG_IEEE80211W - && param->u.crypt.idx > BIP_MAX_KEYID + && param->u.crypt.idx > BIP_MAX_KEYID #endif /* CONFIG_IEEE80211W */ - ) { + ) { ret = -EINVAL; goto exit; } @@ -1179,7 +1207,6 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param } if (strcmp(param->u.crypt.alg, "WEP") == 0) { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("wpa_set_encryption, crypt.alg = WEP\n")); RTW_INFO("wpa_set_encryption, crypt.alg = WEP\n"); wep_key_idx = param->u.crypt.idx; @@ -1223,7 +1250,12 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param /* RTW_INFO("%s, : dot11AuthAlgrthm == dot11AuthAlgrthm_8021X\n", __func__); */ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */ - psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); +#ifdef CONFIG_RTW_80211R + if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) + psta = rtw_get_stainfo(pstapriv, pmlmepriv->assoc_bssid); + else +#endif + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); if (psta == NULL) { /* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */ RTW_INFO("%s, : Obtain Sta_info fail\n", __func__); @@ -1234,7 +1266,7 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) || - (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) + (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; if (param->u.crypt.set_tx == 1) { /* pairwise key */ @@ -1249,9 +1281,11 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); padapter->securitypriv.busetkipkey = _FALSE; - /* _set_timer(&padapter->securitypriv.tkip_timer, 50); */ } psta->bpairwise_key_installed = _TRUE; +#ifdef CONFIG_RTW_80211R + psta->ft_pairwise_key_installed = _TRUE; +#endif /* DEBUG_ERR((" param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); */ RTW_INFO(" ~~~~set sta key:unicastkey\n"); @@ -1259,7 +1293,7 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param } else { /* group key */ if (strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) { _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, - (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); padapter->securitypriv.binstallGrpkey = _TRUE; @@ -1275,7 +1309,7 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param /* RTW_INFO("BIP key_len=%d , index=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.key_len, param->u.crypt.idx); */ /* save the IGTK key, length 16 bytes */ _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, - (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); /*RTW_INFO("IGTK key below:\n"); for(no=0;no<16;no++) printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); @@ -1305,7 +1339,7 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param pbcmc_sta->ieee8021x_blocked = _FALSE; if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) || - (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) + (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; } } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { /* adhoc mode */ @@ -1375,18 +1409,18 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param RTW_INFO("%s, ret=%d\n", __func__, ret); - _func_exit_; return ret; } static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - u8 key_index, bool pairwise, const u8 *mac_addr, + u8 key_index, bool pairwise, const u8 *mac_addr, #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - u8 key_index, const u8 *mac_addr, + u8 key_index, const u8 *mac_addr, #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - struct key_params *params) { + struct key_params *params) +{ char *alg_name; u32 param_len; struct ieee_param *param = NULL; @@ -1500,7 +1534,8 @@ static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, ret = rtw_cfg80211_ap_set_encryption(ndev, param, param_len); #endif } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE - || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { + || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE + ) { /* RTW_INFO("@@@@@@@@@@ fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype); */ ret = rtw_cfg80211_set_encryption(ndev, param, param_len); } else @@ -1517,13 +1552,13 @@ static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - u8 key_index, bool pairwise, const u8 *mac_addr, + u8 key_index, bool pairwise, const u8 *mac_addr, #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - u8 key_index, const u8 *mac_addr, + u8 key_index, const u8 *mac_addr, #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - void *cookie, - void (*callback)(void *cookie, - struct key_params *)) { + void *cookie, + void (*callback)(void *cookie, struct key_params *)) +{ #if 0 struct iwm_priv *iwm = ndev_to_iwm(ndev); struct iwm_key *key = &iwm->keys[key_index]; @@ -1549,9 +1584,9 @@ static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev, static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - u8 key_index, bool pairwise, const u8 *mac_addr) + u8 key_index, bool pairwise, const u8 *mac_addr) #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - u8 key_index, const u8 *mac_addr) + u8 key_index, const u8 *mac_addr) #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ { _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); @@ -1568,31 +1603,32 @@ static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev, } static int cfg80211_rtw_set_default_key(struct wiphy *wiphy, - struct net_device *ndev, u8 key_index -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) - , bool unicast, bool multicast -#endif - ) { + struct net_device *ndev, u8 key_index + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) + , bool unicast, bool multicast + #endif +) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct security_priv *psecuritypriv = &padapter->securitypriv; #define SET_DEF_KEY_PARAM_FMT " key_index=%d" #define SET_DEF_KEY_PARAM_ARG , key_index #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) -#define SET_DEF_KEY_PARAM_FMT_2_6_38 ", unicast=%d, multicast=%d" -#define SET_DEF_KEY_PARAM_ARG_2_6_38 , unicast, multicast + #define SET_DEF_KEY_PARAM_FMT_2_6_38 ", unicast=%d, multicast=%d" + #define SET_DEF_KEY_PARAM_ARG_2_6_38 , unicast, multicast #else -#define SET_DEF_KEY_PARAM_FMT_2_6_38 "" -#define SET_DEF_KEY_PARAM_ARG_2_6_38 + #define SET_DEF_KEY_PARAM_FMT_2_6_38 "" + #define SET_DEF_KEY_PARAM_ARG_2_6_38 #endif RTW_INFO(FUNC_NDEV_FMT - SET_DEF_KEY_PARAM_FMT - SET_DEF_KEY_PARAM_FMT_2_6_38 - "\n", FUNC_NDEV_ARG(ndev) - SET_DEF_KEY_PARAM_ARG - SET_DEF_KEY_PARAM_ARG_2_6_38 - ); + SET_DEF_KEY_PARAM_FMT + SET_DEF_KEY_PARAM_FMT_2_6_38 + "\n", FUNC_NDEV_ARG(ndev) + SET_DEF_KEY_PARAM_ARG + SET_DEF_KEY_PARAM_ARG_2_6_38 + ); if ((key_index < WEP_KEYS) && ((psecuritypriv->dot11PrivacyAlgrthm == _WEP40_) || (psecuritypriv->dot11PrivacyAlgrthm == _WEP104_))) { /* set wep default key */ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; @@ -1614,8 +1650,9 @@ static int cfg80211_rtw_set_default_key(struct wiphy *wiphy, } #if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) static int cfg80211_rtw_set_rekey_data(struct wiphy *wiphy, - struct net_device *ndev, - struct cfg80211_gtk_rekey_data *data) { + struct net_device *ndev, + struct cfg80211_gtk_rekey_data *data) +{ /*int i;*/ struct sta_info *psta; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); @@ -1647,13 +1684,14 @@ static int cfg80211_rtw_set_rekey_data(struct wiphy *wiphy, } #endif /*CONFIG_GTK_OL*/ static int cfg80211_rtw_get_station(struct wiphy *wiphy, - struct net_device *ndev, + struct net_device *ndev, #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)) - u8 *mac, + u8 *mac, #else - const u8 *mac, + const u8 *mac, #endif - struct station_info *sinfo) { + struct station_info *sinfo) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -1681,8 +1719,8 @@ static int cfg80211_rtw_get_station(struct wiphy *wiphy, /* for infra./P2PClient mode */ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) - && check_fwstate(pmlmepriv, _FW_LINKED) - ) { + && check_fwstate(pmlmepriv, _FW_LINKED) + ) { struct wlan_network *cur_network = &(pmlmepriv->cur_network); if (_rtw_memcmp((u8 *)mac, cur_network->network.MacAddress, ETH_ALEN) == _FALSE) { @@ -1707,10 +1745,10 @@ static int cfg80211_rtw_get_station(struct wiphy *wiphy, /* for Ad-Hoc/AP mode */ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) - || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) - || check_fwstate(pmlmepriv, WIFI_AP_STATE)) - && check_fwstate(pmlmepriv, _FW_LINKED) - ) { + || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) + || check_fwstate(pmlmepriv, WIFI_AP_STATE)) + && check_fwstate(pmlmepriv, _FW_LINKED) + ) { /* TODO: should acquire station info... */ } @@ -1738,13 +1776,14 @@ enum nl80211_iftype { }; #endif static int cfg80211_rtw_change_iface(struct wiphy *wiphy, - struct net_device *ndev, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)) + struct net_device *ndev, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)) enum nl80211_iftype type, -#else - enum nl80211_iftype type, u32 *flags, -#endif - struct vif_params *params) { + #else + enum nl80211_iftype type, u32 *flags, + #endif + struct vif_params *params) +{ enum nl80211_iftype old_type; NDIS_802_11_NETWORK_INFRASTRUCTURE networkType; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); @@ -1752,11 +1791,12 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 is_p2p = _FALSE; #endif int ret = 0; u8 change = _FALSE; - RTW_INFO(FUNC_NDEV_FMT" type=%d\n", FUNC_NDEV_ARG(ndev), type); + RTW_INFO(FUNC_NDEV_FMT" type=%d, hw_port:%d\n", FUNC_NDEV_ARG(ndev), type, padapter->hw_port); if (adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) { ret = -EPERM; @@ -1780,7 +1820,7 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, old_type = rtw_wdev->iftype; RTW_INFO(FUNC_NDEV_FMT" old_iftype=%d, new_iftype=%d\n", - FUNC_NDEV_ARG(ndev), old_type, type); + FUNC_NDEV_ARG(ndev), old_type, type); if (old_type != type) { change = _TRUE; @@ -1791,50 +1831,69 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, /* initial default type */ ndev->type = ARPHRD_ETHER; + /* + * Disable Power Save in moniter mode, + * and enable it after leaving moniter mode. + */ + if (type == NL80211_IFTYPE_MONITOR) { + rtw_ps_deny(padapter, PS_DENY_MONITOR_MODE); + LeaveAllPowerSaveMode(padapter); + } else if (old_type == NL80211_IFTYPE_MONITOR) { + /* driver in moniter mode in last time */ + rtw_ps_deny_cancel(padapter, PS_DENY_MONITOR_MODE); + } + switch (type) { case NL80211_IFTYPE_ADHOC: networkType = Ndis802_11IBSS; break; -#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_CLIENT: -#endif + is_p2p = _TRUE; + #endif case NL80211_IFTYPE_STATION: networkType = Ndis802_11Infrastructure; -#ifdef CONFIG_P2P - if (pwdinfo->driver_interface == DRIVER_CFG80211) { - if (change && rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - /* it means remove GO and change mode from AP(GO) to station(P2P DEVICE) */ - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); - rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); - RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); - } -#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) - if (type == NL80211_IFTYPE_P2P_CLIENT) - rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); - else { - /* NL80211_IFTYPE_STATION */ - if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) - rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + #ifdef CONFIG_P2P + if (change && pwdinfo->driver_interface == DRIVER_CFG80211) { + if (is_p2p == _TRUE) + rtw_p2p_enable(padapter, P2P_ROLE_CLIENT); + #if !RTW_P2P_GROUP_INTERFACE + else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) + || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) + ) { + /* it means remove GC/GO and change mode from GC/GO to station(P2P DEVICE) */ + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); } -#endif + #endif } -#endif /* CONFIG_P2P */ + #endif /* CONFIG_P2P */ + break; -#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_GO: -#endif + is_p2p = _TRUE; + #endif case NL80211_IFTYPE_AP: networkType = Ndis802_11APMode; -#ifdef CONFIG_P2P - if (pwdinfo->driver_interface == DRIVER_CFG80211) { - if (change && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + + #ifdef CONFIG_P2P + if (change && pwdinfo->driver_interface == DRIVER_CFG80211) { + if (is_p2p == _TRUE) + rtw_p2p_enable(padapter, P2P_ROLE_GO); + #if !RTW_P2P_GROUP_INTERFACE + else if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { /* it means P2P Group created, we will be GO and change mode from P2P DEVICE to AP(GO) */ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); } + #endif } -#endif /* CONFIG_P2P */ + #endif /* CONFIG_P2P */ + break; + case NL80211_IFTYPE_MONITOR: networkType = Ndis802_11Monitor; #if 0 @@ -1863,43 +1922,45 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, return ret; } -void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted) { - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)) - struct cfg80211_scan_info info = { - .aborted = aborted - }; -#endif +void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted) +{ struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); _irqL irqL; +#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE) + struct cfg80211_scan_info info; + + memset(&info, 0, sizeof(info)); + info.aborted = aborted; +#endif + _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); if (pwdev_priv->scan_request != NULL) { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s with scan req\n", __FUNCTION__); -#endif + #endif /* avoid WARN_ON(request != wiphy_to_dev(request->wiphy)->scan_req); */ if (pwdev_priv->scan_request->wiphy != pwdev_priv->rtw_wdev->wiphy) RTW_INFO("error wiphy compare\n"); - else { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)) + else +#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE) cfg80211_scan_done(pwdev_priv->scan_request, &info); #else cfg80211_scan_done(pwdev_priv->scan_request, aborted); #endif - } pwdev_priv->scan_request = NULL; } else { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s without scan req\n", __FUNCTION__); -#endif + #endif } _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); } -u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms) { +u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms) +{ struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter); u8 empty = _FALSE; u32 start; @@ -1924,25 +1985,32 @@ u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms) { if (empty == _FALSE && pass_ms > timeout_ms) RTW_PRINT(FUNC_ADPT_FMT" pass_ms:%u, timeout\n" - , FUNC_ADPT_ARG(adapter), pass_ms); + , FUNC_ADPT_ARG(adapter), pass_ms); return pass_ms; } -void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork) { +void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork) +{ struct wireless_dev *pwdev = padapter->rtw_wdev; struct wiphy *wiphy = pwdev->wiphy; struct cfg80211_bss *bss = NULL; WLAN_BSSID_EX select_network = pnetwork->network; bss = cfg80211_get_bss(wiphy, NULL/*notify_channel*/, - select_network.MacAddress, select_network.Ssid.Ssid, - select_network.Ssid.SsidLength, 0/*WLAN_CAPABILITY_ESS*/, - 0/*WLAN_CAPABILITY_ESS*/); + select_network.MacAddress, select_network.Ssid.Ssid, + select_network.Ssid.SsidLength, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) + select_network.InfrastructureMode == Ndis802_11Infrastructure?IEEE80211_BSS_TYPE_ESS:IEEE80211_BSS_TYPE_IBSS, + IEEE80211_PRIVACY(select_network.Privacy)); +#else + select_network.InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS, + select_network.InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS); +#endif if (bss) { cfg80211_unlink_bss(wiphy, bss); - RTW_INFO("%s(): cfg80211_unlink %s!! () ", __func__, select_network.Ssid.Ssid); + RTW_INFO("%s(): cfg80211_unlink %s!!\n", __func__, select_network.Ssid.Ssid); #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) cfg80211_put_bss(padapter->rtw_wdev->wiphy, bss); #else @@ -1952,7 +2020,27 @@ void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork) return; } -void rtw_cfg80211_surveydone_event_callback(_adapter *padapter) { +/* if target wps scan ongoing, target_ssid is filled */ +int rtw_cfg80211_is_target_wps_scan(struct cfg80211_scan_request *scan_req, struct cfg80211_ssid *target_ssid) +{ + int ret = 0; + + if (scan_req->n_ssids != 1 + || scan_req->ssids[0].ssid_len == 0 + || scan_req->n_channels != 1 + ) + goto exit; + + /* under target WPS scan */ + _rtw_memcpy(target_ssid, scan_req->ssids, sizeof(struct cfg80211_ssid)); + ret = 1; + +exit: + return ret; +} + +static void _rtw_cfg80211_surveydone_event_callback(_adapter *padapter, struct cfg80211_scan_request *scan_req) +{ _irqL irqL; _list *plist, *phead; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -1961,15 +2049,23 @@ void rtw_cfg80211_surveydone_event_callback(_adapter *padapter) { u32 cnt = 0; u32 wait_for_surveydone; sint wait_status; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &padapter->wdinfo; -#endif /* CONFIG_P2P */ struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + struct cfg80211_ssid target_ssid; + u8 target_wps_scan = 0; #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s\n", __func__); #endif + if (scan_req) + target_wps_scan = rtw_cfg80211_is_target_wps_scan(scan_req, &target_ssid); + else { + _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + if (pwdev_priv->scan_request != NULL) + target_wps_scan = rtw_cfg80211_is_target_wps_scan(pwdev_priv->scan_request, &target_ssid); + _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + } + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); phead = get_list_head(queue); @@ -1982,11 +2078,12 @@ void rtw_cfg80211_surveydone_event_callback(_adapter *padapter) { pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); /* report network only if the current channel set contains the channel to which this network belongs */ - if (rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 - && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE - && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) - ) { - /* ev=translate_scan(padapter, a, pnetwork, ev, stop); */ + if (rtw_chset_search_ch(adapter_to_chset(padapter), pnetwork->network.Configuration.DSConfig) >= 0 + && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE + && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) + ) { + if (target_wps_scan) + rtw_cfg80211_clear_wps_sr_of_non_target_bss(padapter, pnetwork, &target_ssid); rtw_cfg80211_inform_bss(padapter, pnetwork); } #if 0 @@ -2007,7 +2104,13 @@ void rtw_cfg80211_surveydone_event_callback(_adapter *padapter) { _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); } -static int rtw_cfg80211_set_probe_req_wpsp2pie(_adapter *padapter, char *buf, int len) { +inline void rtw_cfg80211_surveydone_event_callback(_adapter *padapter) +{ + _rtw_cfg80211_surveydone_event_callback(padapter, NULL); +} + +static int rtw_cfg80211_set_probe_req_wpsp2pie(_adapter *padapter, char *buf, int len) +{ int ret = 0; uint wps_ielen = 0; u8 *wps_ie; @@ -2024,9 +2127,9 @@ static int rtw_cfg80211_set_probe_req_wpsp2pie(_adapter *padapter, char *buf, in if (len > 0) { wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen); if (wps_ie) { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("probe_req_wps_ielen=%d\n", wps_ielen); -#endif + #endif if (pmlmepriv->wps_probe_req_ie) { u32 free_len = pmlmepriv->wps_probe_req_ie_len; @@ -2048,16 +2151,16 @@ static int rtw_cfg80211_set_probe_req_wpsp2pie(_adapter *padapter, char *buf, in /* buf += wps_ielen; */ /* len -= wps_ielen; */ -#ifdef CONFIG_P2P + #ifdef CONFIG_P2P p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen); if (p2p_ie) { struct wifidirect_info *wdinfo = &padapter->wdinfo; u32 attr_contentlen = 0; u8 listen_ch_attr[5]; -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("probe_req_p2p_ielen=%d\n", p2p_ielen); -#endif + #endif if (pmlmepriv->p2p_probe_req_ie) { u32 free_len = pmlmepriv->p2p_probe_req_ie_len; @@ -2076,42 +2179,131 @@ static int rtw_cfg80211_set_probe_req_wpsp2pie(_adapter *padapter, char *buf, in pmlmepriv->p2p_probe_req_ie_len = p2p_ielen; if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8 *)listen_ch_attr, (uint *) &attr_contentlen) - && attr_contentlen == 5) { + && attr_contentlen == 5) { if (wdinfo->listen_channel != listen_ch_attr[4]) { RTW_INFO(FUNC_ADPT_FMT" listen channel - country:%c%c%c, class:%u, ch:%u\n", - FUNC_ADPT_ARG(padapter), listen_ch_attr[0], listen_ch_attr[1], listen_ch_attr[2], - listen_ch_attr[3], listen_ch_attr[4]); + FUNC_ADPT_ARG(padapter), listen_ch_attr[0], listen_ch_attr[1], listen_ch_attr[2], + listen_ch_attr[3], listen_ch_attr[4]); wdinfo->listen_channel = listen_ch_attr[4]; } } } -#endif /* CONFIG_P2P */ + #endif /* CONFIG_P2P */ -#ifdef CONFIG_WFD + #ifdef CONFIG_WFD wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen); if (wfd_ie) { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("probe_req_wfd_ielen=%d\n", wfd_ielen); -#endif + #endif if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_REQ_IE, wfd_ie, wfd_ielen) != _SUCCESS) return -EINVAL; } -#endif /* CONFIG_WFD */ + #endif /* CONFIG_WFD */ + } + + return ret; + +} + +#ifdef CONFIG_CONCURRENT_MODE +u8 rtw_cfg80211_scan_via_buddy(_adapter *padapter, struct cfg80211_scan_request *request) +{ + int i; + u8 ret = _FALSE; + _adapter *iface = NULL; + _irqL irqL; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + for (i = 0; i < dvobj->iface_nums; i++) { + struct mlme_priv *buddy_mlmepriv; + struct rtw_wdev_priv *buddy_wdev_priv; + + iface = dvobj->padapters[i]; + if (iface == NULL) + continue; + + if (iface == padapter) + continue; + + if (rtw_is_adapter_up(iface) == _FALSE) + continue; + + buddy_mlmepriv = &iface->mlmepriv; + if (!check_fwstate(buddy_mlmepriv, _FW_UNDER_SURVEY)) + continue; + + buddy_wdev_priv = adapter_wdev_data(iface); + _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + _enter_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL); + if (buddy_wdev_priv->scan_request) { + pmlmepriv->scanning_via_buddy_intf = _TRUE; + _enter_critical_bh(&pmlmepriv->lock, &irqL); + set_fwstate(pmlmepriv, _FW_UNDER_SURVEY); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + pwdev_priv->scan_request = request; + ret = _TRUE; + } + _exit_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL); + _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + + if (ret == _TRUE) + goto exit; } +exit: return ret; +} + +void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_aborted) +{ + int i; + u8 ret = 0; + _adapter *iface = NULL; + _irqL irqL; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mlme_priv *mlmepriv; + struct rtw_wdev_priv *wdev_priv; + bool indicate_buddy_scan; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if ((iface) && rtw_is_adapter_up(iface)) { + + if (iface == padapter) + continue; + + mlmepriv = &(iface->mlmepriv); + wdev_priv = adapter_wdev_data(iface); + indicate_buddy_scan = _FALSE; + _enter_critical_bh(&wdev_priv->scan_req_lock, &irqL); + if (wdev_priv->scan_request && mlmepriv->scanning_via_buddy_intf == _TRUE) { + mlmepriv->scanning_via_buddy_intf = _FALSE; + clr_fwstate(mlmepriv, _FW_UNDER_SURVEY); + indicate_buddy_scan = _TRUE; + } + _exit_critical_bh(&wdev_priv->scan_req_lock, &irqL); + + if (indicate_buddy_scan == _TRUE) { + rtw_cfg80211_surveydone_event_callback(iface); + rtw_indicate_scan_done(iface, bscan_aborted); + } + + } + } } +#endif /* CONFIG_CONCURRENT_MODE */ static int cfg80211_rtw_scan(struct wiphy *wiphy -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) - , struct net_device *ndev -#endif - , struct cfg80211_scan_request *request) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - struct net_device *ndev = wdev_to_ndev(request->wdev); -#endif + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) + , struct net_device *ndev + #endif + , struct cfg80211_scan_request *request) +{ int i, chan_num = 0; u8 _status = _FALSE; int ret = 0; @@ -2131,38 +2323,52 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy bool ps_denied = _FALSE; _adapter *padapter; + struct wireless_dev *wdev; struct rtw_wdev_priv *pwdev_priv; struct mlme_priv *pmlmepriv; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo; #endif /* CONFIG_P2P */ - if (ndev == NULL) { - ret = -EINVAL; - goto exit; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + wdev = request->wdev; + #if defined(RTW_DEDICATED_P2P_DEVICE) + if (wdev == wiphy_to_pd_wdev(wiphy)) + padapter = wiphy_to_adapter(wiphy); + else + #endif + if (wdev_to_ndev(wdev)) + padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev)); + else { + ret = -EINVAL; + goto exit; + } +#else + if (ndev == NULL) { + ret = -EINVAL; + goto exit; } - padapter = (_adapter *)rtw_netdev_priv(ndev); + wdev = ndev_to_wdev(ndev); +#endif + pwdev_priv = adapter_wdev_data(padapter); pmlmepriv = &padapter->mlmepriv; #ifdef CONFIG_P2P pwdinfo = &(padapter->wdinfo); #endif /* CONFIG_P2P */ - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + RTW_INFO(FUNC_ADPT_FMT"%s\n", FUNC_ADPT_ARG(padapter) + , wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : ""); #ifdef CONFIG_MP_INCLUDED - if (rtw_mi_mp_mode_check(padapter)) { + if (rtw_mp_mode_check(padapter)) { RTW_INFO("MP mode block Scan request\n"); ret = -EPERM; goto exit; } #endif - _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); - pwdev_priv->scan_request = request; - _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); - if (adapter_wdev_data(padapter)->block_scan == _TRUE) { RTW_INFO(FUNC_ADPT_FMT" wdev_priv.block_scan is set\n", FUNC_ADPT_ARG(padapter)); need_indicate_scan_done = _TRUE; @@ -2179,25 +2385,24 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy #ifdef CONFIG_P2P if (pwdinfo->driver_interface == DRIVER_CFG80211) { if (ssids->ssid != NULL - && _rtw_memcmp(ssids->ssid, "DIRECT-", 7) - && rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL) - ) { - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + && _rtw_memcmp(ssids->ssid, "DIRECT-", 7) + && rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL) + ) { + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); - adapter_wdev_data(padapter)->p2p_enabled = _TRUE; - } else { + else { rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); -#endif + #endif } rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); if (request->n_channels == 3 && - request->channels[0]->hw_value == 1 && - request->channels[1]->hw_value == 6 && - request->channels[2]->hw_value == 11 - ) + request->channels[0]->hw_value == 1 && + request->channels[1]->hw_value == 6 && + request->channels[2]->hw_value == 11 + ) social_channel = 1; } } @@ -2246,19 +2451,14 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy need_indicate_scan_done = _TRUE; goto check_need_indicate_scan_done; - } else { - bool scan_via_buddy = _FALSE; - u8 bunder_survey = rtw_mi_buddy_under_survey(padapter); + } else if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_SURVEY)) { + bool scan_via_buddy = rtw_cfg80211_scan_via_buddy(padapter, request); - if (bunder_survey) { - scan_via_buddy = (UNDER_SURVEY_T2 == bunder_survey) ? _TRUE : _FALSE; - if (scan_via_buddy == _FALSE) - need_indicate_scan_done = _TRUE; + if (scan_via_buddy == _FALSE) + need_indicate_scan_done = _TRUE; - goto check_need_indicate_scan_done; - } + goto check_need_indicate_scan_done; } - #endif /* CONFIG_CONCURRENT_MODE */ /* busy traffic check*/ @@ -2283,9 +2483,9 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID) * RTW_SSID_SCAN_AMOUNT); /* parsing request ssids, n_ssids */ for (i = 0; i < request->n_ssids && i < RTW_SSID_SCAN_AMOUNT; i++) { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("ssid=%s, len=%d\n", ssids[i].ssid, ssids[i].ssid_len); -#endif + #endif _rtw_memcpy(ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len); ssid[i].SsidLength = ssids[i].ssid_len; } @@ -2293,15 +2493,13 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy /* parsing channels, n_channels */ _rtw_memset(ch, 0, sizeof(struct rtw_ieee80211_channel) * RTW_CHANNEL_SCAN_AMOUNT); for (i = 0; i < request->n_channels && i < RTW_CHANNEL_SCAN_AMOUNT; i++) { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO(FUNC_ADPT_FMT CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(request->channels[i])); -#endif + #endif ch[i].hw_value = request->channels[i]->hw_value; ch[i].flags = request->channels[i]->flags; } - - if (request->n_channels == 1) { for (i = 1; i < survey_times_for_one_ch; i++) _rtw_memcpy(&ch[i], &ch[0], sizeof(struct rtw_ieee80211_channel)); @@ -2318,18 +2516,31 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy chan_num = request->n_channels; } + _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); _enter_critical_bh(&pmlmepriv->lock, &irqL); _status = rtw_sitesurvey_cmd(padapter, ssid, RTW_SSID_SCAN_AMOUNT, pch, chan_num); - _exit_critical_bh(&pmlmepriv->lock, &irqL); - - - if (_status == _FALSE) + if (_status == _SUCCESS) + pwdev_priv->scan_request = request; + else ret = -1; + _exit_critical_bh(&pmlmepriv->lock, &irqL); + _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); check_need_indicate_scan_done: if (_TRUE == need_indicate_scan_done) { - rtw_cfg80211_surveydone_event_callback(padapter); - rtw_cfg80211_indicate_scan_done(padapter, _FALSE); +#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE) + struct cfg80211_scan_info info; + + memset(&info, 0, sizeof(info)); + info.aborted = 0; +#endif + + _rtw_cfg80211_surveydone_event_callback(padapter, request); +#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE) + cfg80211_scan_done(request, &info); +#else + cfg80211_scan_done(request, 0); +#endif } cancel_ps_deny: @@ -2341,32 +2552,33 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy } -static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed) { +static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed) +{ #if 0 struct iwm_priv *iwm = wiphy_to_iwm(wiphy); if (changed & WIPHY_PARAM_RTS_THRESHOLD && - (iwm->conf.rts_threshold != wiphy->rts_threshold)) { + (iwm->conf.rts_threshold != wiphy->rts_threshold)) { int ret; iwm->conf.rts_threshold = wiphy->rts_threshold; ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX, - CFG_RTS_THRESHOLD, - iwm->conf.rts_threshold); + CFG_RTS_THRESHOLD, + iwm->conf.rts_threshold); if (ret < 0) return ret; } if (changed & WIPHY_PARAM_FRAG_THRESHOLD && - (iwm->conf.frag_threshold != wiphy->frag_threshold)) { + (iwm->conf.frag_threshold != wiphy->frag_threshold)) { int ret; iwm->conf.frag_threshold = wiphy->frag_threshold; ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_FA_CFG_FIX, - CFG_FRAG_THRESHOLD, - iwm->conf.frag_threshold); + CFG_FRAG_THRESHOLD, + iwm->conf.frag_threshold); if (ret < 0) return ret; } @@ -2377,7 +2589,8 @@ static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed) { -static int rtw_cfg80211_set_wpa_version(struct security_priv *psecuritypriv, u32 wpa_version) { +static int rtw_cfg80211_set_wpa_version(struct security_priv *psecuritypriv, u32 wpa_version) +{ RTW_INFO("%s, wpa_version=%d\n", __func__, wpa_version); if (!wpa_version) { @@ -2389,24 +2602,23 @@ static int rtw_cfg80211_set_wpa_version(struct security_priv *psecuritypriv, u32 if (wpa_version & (NL80211_WPA_VERSION_1 | NL80211_WPA_VERSION_2)) psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK; - /* - if (wpa_version & NL80211_WPA_VERSION_2) - { - psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; - } - */ +#if 0 + if (wpa_version & NL80211_WPA_VERSION_2) + psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; +#endif -#ifdef CONFIG_WAPI_SUPPORT + #ifdef CONFIG_WAPI_SUPPORT if (wpa_version & NL80211_WAPI_VERSION_1) psecuritypriv->ndisauthtype = Ndis802_11AuthModeWAPI; -#endif + #endif return 0; } static int rtw_cfg80211_set_auth_type(struct security_priv *psecuritypriv, - enum nl80211_auth_type sme_auth_type) { + enum nl80211_auth_type sme_auth_type) +{ RTW_INFO("%s, nl80211_auth_type=%d\n", __func__, sme_auth_type); @@ -2446,11 +2658,12 @@ static int rtw_cfg80211_set_auth_type(struct security_priv *psecuritypriv, } -static int rtw_cfg80211_set_cipher(struct security_priv *psecuritypriv, u32 cipher, bool ucast) { +static int rtw_cfg80211_set_cipher(struct security_priv *psecuritypriv, u32 cipher, bool ucast) +{ u32 ndisencryptstatus = Ndis802_11EncryptionDisabled; u32 *profile_cipher = ucast ? &psecuritypriv->dot11PrivacyAlgrthm : - &psecuritypriv->dot118021XGrpPrivacy; + &psecuritypriv->dot118021XGrpPrivacy; RTW_INFO("%s, ucast=%d, cipher=0x%x\n", __func__, ucast, cipher); @@ -2507,22 +2720,33 @@ static int rtw_cfg80211_set_cipher(struct security_priv *psecuritypriv, u32 ciph return 0; } -static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key_mgt) { +static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key_mgt) +{ RTW_INFO("%s, key_mgt=0x%x\n", __func__, key_mgt); - if (key_mgt == WLAN_AKM_SUITE_8021X) + if (key_mgt == WLAN_AKM_SUITE_8021X) { /* *auth_type = UMAC_AUTH_TYPE_8021X; */ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; - else if (key_mgt == WLAN_AKM_SUITE_PSK) + psecuritypriv->rsn_akm_suite_type = 1; + } else if (key_mgt == WLAN_AKM_SUITE_PSK) { psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; + psecuritypriv->rsn_akm_suite_type = 2; + } #ifdef CONFIG_WAPI_SUPPORT else if (key_mgt == WLAN_AKM_SUITE_WAPI_PSK) psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI; else if (key_mgt == WLAN_AKM_SUITE_WAPI_CERT) psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI; #endif - - +#ifdef CONFIG_RTW_80211R + else if (key_mgt == WLAN_AKM_SUITE_FT_8021X) { + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; + psecuritypriv->rsn_akm_suite_type = 3; + } else if (key_mgt == WLAN_AKM_SUITE_FT_PSK) { + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; + psecuritypriv->rsn_akm_suite_type = 4; + } +#endif else { RTW_INFO("Invalid key mgt: 0x%x\n", key_mgt); /* return -EINVAL; */ @@ -2531,7 +2755,8 @@ static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key return 0; } -static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) { +static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) +{ u8 *buf = NULL, *pos = NULL; u32 left; int group_cipher = 0, pairwise_cipher = 0; @@ -2570,7 +2795,6 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) { pos = buf; if (ielen < RSN_HEADER_LEN) { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("Ie len too short %d\n", ielen)); ret = -1; goto exit; } @@ -2648,8 +2872,7 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) { break; } - { - /* handle wps_ie */ + {/* handle wps_ie */ uint wps_ielen; u8 *wps_ie; @@ -2663,18 +2886,17 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) { _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); } -#ifdef CONFIG_P2P - { - /* check p2p_ie for assoc req; */ + #ifdef CONFIG_P2P + {/* check p2p_ie for assoc req; */ uint p2p_ielen = 0; u8 *p2p_ie; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); p2p_ie = rtw_get_p2p_ie(buf, ielen, NULL, &p2p_ielen); if (p2p_ie) { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s p2p_assoc_req_ielen=%d\n", __FUNCTION__, p2p_ielen); -#endif + #endif if (pmlmepriv->p2p_assoc_req_ie) { u32 free_len = pmlmepriv->p2p_assoc_req_ie_len; @@ -2692,9 +2914,9 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) { pmlmepriv->p2p_assoc_req_ie_len = p2p_ielen; } } -#endif /* CONFIG_P2P */ + #endif /* CONFIG_P2P */ -#ifdef CONFIG_WFD + #ifdef CONFIG_WFD { uint wfd_ielen = 0; u8 *wfd_ie; @@ -2702,27 +2924,24 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) { wfd_ie = rtw_get_wfd_ie(buf, ielen, NULL, &wfd_ielen); if (wfd_ie) { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s wfd_assoc_req_ielen=%d\n", __FUNCTION__, wfd_ielen); -#endif + #endif if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_REQ_IE, wfd_ie, wfd_ielen) != _SUCCESS) goto exit; } } -#endif /* CONFIG_WFD */ + #endif /* CONFIG_WFD */ /* TKIP and AES disallow multicast packets until installing group key */ if (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_ - || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_ - || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) + || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_ + || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) /* WPS open need to enable multicast */ /* || check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) */ rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr); - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, - ("rtw_set_wpa_ie: pairwise_cipher=0x%08x padapter->securitypriv.ndisencryptstatus=%d padapter->securitypriv.ndisauthtype=%d\n", - pairwise_cipher, padapter->securitypriv.ndisencryptstatus, padapter->securitypriv.ndisauthtype)); exit: if (buf) @@ -2734,7 +2953,8 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) { } static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev, - struct cfg80211_ibss_params *params) { + struct cfg80211_ibss_params *params) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); NDIS_802_11_SSID ndis_ssid; struct security_priv *psecuritypriv = &padapter->securitypriv; @@ -2765,22 +2985,22 @@ static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev, goto exit; } - rtw_ps_deny(padapter, PS_DENY_JOIN); - if (_FAIL == rtw_pwr_wakeup(padapter)) { + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { ret = -EPERM; goto exit; } - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + rtw_ps_deny(padapter, PS_DENY_JOIN); + if (_FAIL == rtw_pwr_wakeup(padapter)) { ret = -EPERM; - goto exit; + goto cancel_ps_deny; } #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING)) { RTW_INFO("%s, but buddy_intf is under linking\n", __FUNCTION__); ret = -EINVAL; - goto exit; + goto cancel_ps_deny; } rtw_mi_buddy_scan_abort(padapter, _TRUE); /* OR rtw_mi_scan_abort(padapter, _TRUE);*/ #endif /*CONFIG_CONCURRENT_MODE*/ @@ -2806,25 +3026,26 @@ static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev, if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) { ret = -1; - goto exit; + goto cancel_ps_deny; } -exit: +cancel_ps_deny: rtw_ps_deny_cancel(padapter, PS_DENY_JOIN); +exit: return ret; } -static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev) { +static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct wireless_dev *rtw_wdev = padapter->rtw_wdev; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); enum nl80211_iftype old_type; int ret = 0; RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); -#ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 - padapter->mlmepriv.not_indic_disco = _TRUE; -#endif + rtw_wdev_set_not_indic_disco(pwdev_priv, 1); old_type = rtw_wdev->iftype; @@ -2845,18 +3066,15 @@ static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev) } leave_ibss: -#ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 - padapter->mlmepriv.not_indic_disco = _FALSE; -#endif + rtw_wdev_set_not_indic_disco(pwdev_priv, 0); return 0; } static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, - struct cfg80211_connect_params *sme) { + struct cfg80211_connect_params *sme) +{ int ret = 0; - _irqL irqL; - _list *phead; struct wlan_network *pnetwork = NULL; NDIS_802_11_AUTHENTICATION_MODE authmode; NDIS_802_11_SSID ndis_ssid; @@ -2869,17 +3087,18 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct security_priv *psecuritypriv = &padapter->securitypriv; _queue *queue = &pmlmepriv->scanned_queue; + struct wireless_dev *pwdev = padapter->rtw_wdev; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + _irqL irqL; -#ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 - padapter->mlmepriv.not_indic_disco = _TRUE; -#endif + rtw_wdev_set_not_indic_disco(pwdev_priv, 1); RTW_INFO("=>"FUNC_NDEV_FMT" - Start to Connection\n", FUNC_NDEV_ARG(ndev)); RTW_INFO("privacy=%d, key=%p, key_len=%d, key_idx=%d, auth_type=%d\n", - sme->privacy, sme->key, sme->key_len, sme->key_idx, sme->auth_type); + sme->privacy, sme->key, sme->key_len, sme->key_idx, sme->auth_type); - if (adapter_wdev_data(padapter)->block == _TRUE) { + if (pwdev_priv->block == _TRUE) { ret = -EBUSY; RTW_INFO("%s wdev_priv.block is set\n", __FUNCTION__); goto exit; @@ -2887,7 +3106,7 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, #ifdef CONFIG_PLATFORM_MSTAR_SCAN_BEFORE_CONNECT printk("MStar Android!\n"); - if (adapter_wdev_data(padapter)->bandroid_scan == _FALSE) { + if (pwdev_priv->bandroid_scan == _FALSE) { #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) @@ -2910,28 +3129,27 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, goto exit; } - rtw_ps_deny(padapter, PS_DENY_JOIN); if (_FAIL == rtw_pwr_wakeup(padapter)) { ret = -EPERM; - goto exit; + goto cancel_ps_deny; } if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { ret = -EPERM; - goto exit; + goto cancel_ps_deny; } if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { ret = -EBUSY; RTW_INFO("%s, fw_state=0x%x, goto exit\n", __func__, pmlmepriv->fw_state); - goto exit; + goto cancel_ps_deny; } #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING)) { ret = -EINVAL; - goto exit; + goto cancel_ps_deny; } #endif @@ -2960,7 +3178,7 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, ret = rtw_cfg80211_set_wpa_version(psecuritypriv, sme->crypto.wpa_versions); if (ret < 0) - goto exit; + goto cancel_ps_deny; #ifdef CONFIG_WAPI_SUPPORT if (sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) { @@ -2979,18 +3197,18 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, if (ret < 0) - goto exit; + goto cancel_ps_deny; RTW_INFO("%s, ie_len=%zu\n", __func__, sme->ie_len); ret = rtw_cfg80211_set_wpa_ie(padapter, (u8 *)sme->ie, sme->ie_len); if (ret < 0) - goto exit; + goto cancel_ps_deny; if (sme->crypto.n_ciphers_pairwise) { ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.ciphers_pairwise[0], _TRUE); if (ret < 0) - goto exit; + goto cancel_ps_deny; } /* For WEP Shared auth */ @@ -3004,7 +3222,7 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, if (sme->key_idx > WEP_KEYS) { ret = -EINVAL; - goto exit; + goto cancel_ps_deny; } if (wep_key_len > 0) { @@ -3014,7 +3232,7 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, if (pwep == NULL) { RTW_INFO(" wpa_set_encryption: pwep allocate fail !!!\n"); ret = -ENOMEM; - goto exit; + goto cancel_ps_deny; } _rtw_memset(pwep, 0, wep_total_len); @@ -3028,7 +3246,7 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, } } else { ret = -EINVAL; - goto exit; + goto cancel_ps_deny; } pwep->KeyIndex = wep_key_idx; @@ -3043,7 +3261,7 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, rtw_mfree((u8 *)pwep, wep_total_len); if (ret < 0) - goto exit; + goto cancel_ps_deny; } ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.cipher_group, _FALSE); @@ -3053,8 +3271,14 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, if (sme->crypto.n_akm_suites) { ret = rtw_cfg80211_set_key_mgt(psecuritypriv, sme->crypto.akm_suites[0]); if (ret < 0) - goto exit; + goto cancel_ps_deny; + } +#ifdef CONFIG_8011R + else { + /*It could be a connection without RSN IEs*/ + psecuritypriv->rsn_akm_suite_type = 0; } +#endif #ifdef CONFIG_WAPI_SUPPORT if (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_PSK) @@ -3070,34 +3294,51 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, if (rtw_set_802_11_connect(padapter, (u8 *)sme->bssid, &ndis_ssid) == _FALSE) { ret = -1; - goto exit; + goto cancel_ps_deny; } - RTW_INFO("set ssid:dot11AuthAlgrthm=%d, dot11PrivacyAlgrthm=%d, dot118021XGrpPrivacy=%d\n", psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, - psecuritypriv->dot118021XGrpPrivacy); -exit: + _enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + + if (pwdev_priv->connect_req) { + rtw_wdev_free_connect_req(pwdev_priv); + RTW_INFO(FUNC_NDEV_FMT" free existing connect_req\n", FUNC_NDEV_ARG(ndev)); + } + + pwdev_priv->connect_req = (struct cfg80211_connect_params *)rtw_malloc(sizeof(*pwdev_priv->connect_req)); + if (pwdev_priv->connect_req) + _rtw_memcpy(pwdev_priv->connect_req, sme, sizeof(*pwdev_priv->connect_req)); + else + RTW_WARN(FUNC_NDEV_FMT" alloc connect_req fail\n", FUNC_NDEV_ARG(ndev)); + + _exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + + RTW_INFO("set ssid:dot11AuthAlgrthm=%d, dot11PrivacyAlgrthm=%d, dot118021XGrpPrivacy=%d\n", psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, + psecuritypriv->dot118021XGrpPrivacy); +cancel_ps_deny: rtw_ps_deny_cancel(padapter, PS_DENY_JOIN); +exit: RTW_INFO("<=%s, ret %d\n", __FUNCTION__, ret); -#ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 - padapter->mlmepriv.not_indic_disco = _FALSE; -#endif + rtw_wdev_set_not_indic_disco(pwdev_priv, 0); return ret; } static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev, - u16 reason_code) { + u16 reason_code) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); RTW_INFO(FUNC_NDEV_FMT" - Start to Disconnect\n", FUNC_NDEV_ARG(ndev)); -#ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 - padapter->mlmepriv.not_indic_disco = _TRUE; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + if (!wiphy->dev.power.is_prepared) #endif + rtw_wdev_set_not_indic_disco(pwdev_priv, 1); rtw_set_to_roam(padapter, 0); @@ -3105,20 +3346,17 @@ static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev, { rtw_scan_abort(padapter); LeaveAllPowerSaveMode(padapter); - rtw_disassoc_cmd(padapter, 500, _FALSE); - rtw_sta_mstatus_report(padapter); + rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK); RTW_INFO("%s...call rtw_indicate_disconnect\n", __func__); rtw_free_assoc_resources(padapter, 1); - rtw_indicate_disconnect(padapter, 0, _TRUE); + rtw_indicate_disconnect(padapter, 0, wiphy->dev.power.is_prepared ? _FALSE : _TRUE); rtw_pwr_wakeup(padapter); } -#ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 - padapter->mlmepriv.not_indic_disco = _FALSE; -#endif + rtw_wdev_set_not_indic_disco(pwdev_priv, 0); RTW_INFO(FUNC_NDEV_FMT" return 0\n", FUNC_NDEV_ARG(ndev)); return 0; @@ -3126,12 +3364,12 @@ static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev, static int cfg80211_rtw_set_txpower(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - struct wireless_dev *wdev, + struct wireless_dev *wdev, #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) || defined(COMPAT_KERNEL_RELEASE) - enum nl80211_tx_power_setting type, int mbm) + enum nl80211_tx_power_setting type, int mbm) #else - enum tx_power_setting type, int dbm) + enum tx_power_setting type, int dbm) #endif { #if 0 @@ -3149,8 +3387,8 @@ static int cfg80211_rtw_set_txpower(struct wiphy *wiphy, return 0; ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX, - CFG_TX_PWR_LIMIT_USR, - MBM_TO_DBM(mbm) * 2); + CFG_TX_PWR_LIMIT_USR, + MBM_TO_DBM(mbm) * 2); if (ret < 0) return ret; @@ -3166,9 +3404,10 @@ static int cfg80211_rtw_set_txpower(struct wiphy *wiphy, static int cfg80211_rtw_get_txpower(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - struct wireless_dev *wdev, + struct wireless_dev *wdev, #endif - int *dbm) { + int *dbm) +{ RTW_INFO("%s\n", __func__); *dbm = (12); @@ -3176,19 +3415,21 @@ static int cfg80211_rtw_get_txpower(struct wiphy *wiphy, return 0; } -inline bool rtw_cfg80211_pwr_mgmt(_adapter *adapter) { +inline bool rtw_cfg80211_pwr_mgmt(_adapter *adapter) +{ struct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(adapter); return rtw_wdev_priv->power_mgmt; } static int cfg80211_rtw_set_power_mgmt(struct wiphy *wiphy, - struct net_device *ndev, - bool enabled, int timeout) { + struct net_device *ndev, + bool enabled, int timeout) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(padapter); RTW_INFO(FUNC_NDEV_FMT" enabled:%u, timeout:%d\n", FUNC_NDEV_ARG(ndev), - enabled, timeout); + enabled, timeout); rtw_wdev_priv->power_mgmt = enabled; @@ -3201,8 +3442,9 @@ static int cfg80211_rtw_set_power_mgmt(struct wiphy *wiphy, } static int cfg80211_rtw_set_pmksa(struct wiphy *wiphy, - struct net_device *ndev, - struct cfg80211_pmksa *pmksa) { + struct net_device *ndev, + struct cfg80211_pmksa *pmksa) +{ u8 index, blInserted = _FALSE; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct mlme_priv *mlme = &padapter->mlmepriv; @@ -3210,7 +3452,7 @@ static int cfg80211_rtw_set_pmksa(struct wiphy *wiphy, u8 strZeroMacAddress[ETH_ALEN] = { 0x00 }; RTW_INFO(FUNC_NDEV_FMT" "MAC_FMT" "KEY_FMT"\n", FUNC_NDEV_ARG(ndev) - , MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid)); + , MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid)); if (_rtw_memcmp((u8 *)pmksa->bssid, strZeroMacAddress, ETH_ALEN) == _TRUE) return -EINVAL; @@ -3239,7 +3481,7 @@ static int cfg80211_rtw_set_pmksa(struct wiphy *wiphy, if (!blInserted) { /* Find a new entry */ RTW_INFO(FUNC_NDEV_FMT" Use the new entry index = %d for this PMKID.\n", - FUNC_NDEV_ARG(ndev), psecuritypriv->PMKIDIndex); + FUNC_NDEV_ARG(ndev), psecuritypriv->PMKIDIndex); _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, (u8 *)pmksa->bssid, ETH_ALEN); _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, (u8 *)pmksa->pmkid, WLAN_PMKID_LEN); @@ -3254,14 +3496,15 @@ static int cfg80211_rtw_set_pmksa(struct wiphy *wiphy, } static int cfg80211_rtw_del_pmksa(struct wiphy *wiphy, - struct net_device *ndev, - struct cfg80211_pmksa *pmksa) { + struct net_device *ndev, + struct cfg80211_pmksa *pmksa) +{ u8 index, bMatched = _FALSE; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct security_priv *psecuritypriv = &padapter->securitypriv; RTW_INFO(FUNC_NDEV_FMT" "MAC_FMT" "KEY_FMT"\n", FUNC_NDEV_ARG(ndev) - , MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid)); + , MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid)); for (index = 0 ; index < NUM_PMKID_CACHE; index++) { if (_rtw_memcmp(psecuritypriv->PMKIDList[index].Bssid, (u8 *)pmksa->bssid, ETH_ALEN) == _TRUE) { @@ -3277,7 +3520,7 @@ static int cfg80211_rtw_del_pmksa(struct wiphy *wiphy, if (_FALSE == bMatched) { RTW_INFO(FUNC_NDEV_FMT" do not have matched BSSID\n" - , FUNC_NDEV_ARG(ndev)); + , FUNC_NDEV_ARG(ndev)); return -EINVAL; } @@ -3285,7 +3528,8 @@ static int cfg80211_rtw_del_pmksa(struct wiphy *wiphy, } static int cfg80211_rtw_flush_pmksa(struct wiphy *wiphy, - struct net_device *ndev) { + struct net_device *ndev) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct security_priv *psecuritypriv = &padapter->securitypriv; @@ -3298,7 +3542,8 @@ static int cfg80211_rtw_flush_pmksa(struct wiphy *wiphy, } #ifdef CONFIG_AP_MODE -void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) { +void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) +{ s32 freq; int channel; struct wireless_dev *pwdev = padapter->rtw_wdev; @@ -3311,7 +3556,7 @@ void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint f { struct station_info sinfo; u8 ie_offset; - if (GetFrameSubType(pmgmt_frame) == WIFI_ASSOCREQ) + if (get_frame_sub_type(pmgmt_frame) == WIFI_ASSOCREQ) ie_offset = _ASOCREQ_IE_OFFSET_; else /* WIFI_REASSOCREQ */ ie_offset = _REASOCREQ_IE_OFFSET_; @@ -3320,34 +3565,35 @@ void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint f sinfo.filled = STATION_INFO_ASSOC_REQ_IES; sinfo.assoc_req_ies = pmgmt_frame + WLAN_HDR_A3_LEN + ie_offset; sinfo.assoc_req_ies_len = frame_len - WLAN_HDR_A3_LEN - ie_offset; - cfg80211_new_sta(ndev, GetAddr2Ptr(pmgmt_frame), &sinfo, GFP_ATOMIC); + cfg80211_new_sta(ndev, get_addr2_ptr(pmgmt_frame), &sinfo, GFP_ATOMIC); } #else /* defined(RTW_USE_CFG80211_STA_EVENT) */ channel = pmlmeext->cur_channel; freq = rtw_ch2freq(channel); -#ifdef COMPAT_KERNEL_RELEASE - rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) - rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); -#else /* COMPAT_KERNEL_RELEASE */ + #ifdef COMPAT_KERNEL_RELEASE + rtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) + rtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); + #else /* COMPAT_KERNEL_RELEASE */ { /* to avoid WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION) when calling cfg80211_send_rx_assoc() */ -#ifndef CONFIG_PLATFORM_MSTAR + #ifndef CONFIG_PLATFORM_MSTAR pwdev->iftype = NL80211_IFTYPE_STATION; -#endif /* CONFIG_PLATFORM_MSTAR */ + #endif /* CONFIG_PLATFORM_MSTAR */ RTW_INFO("iftype=%d before call cfg80211_send_rx_assoc()\n", pwdev->iftype); rtw_cfg80211_send_rx_assoc(padapter, NULL, pmgmt_frame, frame_len); RTW_INFO("iftype=%d after call cfg80211_send_rx_assoc()\n", pwdev->iftype); pwdev->iftype = NL80211_IFTYPE_AP; /* cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); */ } -#endif /* COMPAT_KERNEL_RELEASE */ + #endif /* COMPAT_KERNEL_RELEASE */ #endif /* defined(RTW_USE_CFG80211_STA_EVENT) */ } -void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason) { +void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason) +{ s32 freq; int channel; u8 *pmgmt_frame; @@ -3357,6 +3603,7 @@ void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, u u8 mgmt_buf[128] = {0}; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wireless_dev *wdev = padapter->rtw_wdev; struct net_device *ndev = padapter->pnetdev; RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); @@ -3379,7 +3626,7 @@ void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, u SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pmgmt_frame, WIFI_DEAUTH); + set_frame_sub_type(pmgmt_frame, WIFI_DEAUTH); pmgmt_frame += sizeof(struct rtw_ieee80211_hdr_3addr); frame_len = sizeof(struct rtw_ieee80211_hdr_3addr); @@ -3387,18 +3634,19 @@ void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, u reason = cpu_to_le16(reason); pmgmt_frame = rtw_set_fixed_ie(pmgmt_frame, _RSON_CODE_ , (unsigned char *)&reason, &frame_len); -#ifdef COMPAT_KERNEL_RELEASE - rtw_cfg80211_rx_mgmt(padapter, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) - rtw_cfg80211_rx_mgmt(padapter, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC); -#else /* COMPAT_KERNEL_RELEASE */ + #ifdef COMPAT_KERNEL_RELEASE + rtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC); + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) + rtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC); + #else /* COMPAT_KERNEL_RELEASE */ cfg80211_send_disassoc(padapter->pnetdev, mgmt_buf, frame_len); /* cfg80211_rx_action(padapter->pnetdev, freq, mgmt_buf, frame_len, GFP_ATOMIC); */ -#endif /* COMPAT_KERNEL_RELEASE */ + #endif /* COMPAT_KERNEL_RELEASE */ #endif /* defined(RTW_USE_CFG80211_STA_EVENT) */ } -static int rtw_cfg80211_monitor_if_open(struct net_device *ndev) { +static int rtw_cfg80211_monitor_if_open(struct net_device *ndev) +{ int ret = 0; RTW_INFO("%s\n", __func__); @@ -3406,7 +3654,8 @@ static int rtw_cfg80211_monitor_if_open(struct net_device *ndev) { return ret; } -static int rtw_cfg80211_monitor_if_close(struct net_device *ndev) { +static int rtw_cfg80211_monitor_if_close(struct net_device *ndev) +{ int ret = 0; RTW_INFO("%s\n", __func__); @@ -3414,7 +3663,8 @@ static int rtw_cfg80211_monitor_if_close(struct net_device *ndev) { return ret; } -static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_device *ndev) { +static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_device *ndev) +{ int ret = 0; int rtap_len; int qos_len = 0; @@ -3483,8 +3733,8 @@ static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_de return ret; } else if ((frame_ctl & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE)) - == (RTW_IEEE80211_FTYPE_MGMT | RTW_IEEE80211_STYPE_ACTION) - ) { + == (RTW_IEEE80211_FTYPE_MGMT | RTW_IEEE80211_STYPE_ACTION) + ) { /* only for action frames */ struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; @@ -3501,17 +3751,17 @@ static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_de if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) { RTW_INFO(FUNC_NDEV_FMT" frame_control:0x%x\n", FUNC_NDEV_ARG(ndev), - le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl)); + le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl)); goto fail; } RTW_INFO("RTW_Tx:da="MAC_FMT" via "FUNC_NDEV_FMT"\n", - MAC_ARG(GetAddr1Ptr(buf)), FUNC_NDEV_ARG(ndev)); -#ifdef CONFIG_P2P + MAC_ARG(GetAddr1Ptr(buf)), FUNC_NDEV_ARG(ndev)); + #ifdef CONFIG_P2P type = rtw_p2p_check_frames(padapter, buf, len, _TRUE); if (type >= 0) goto dump; -#endif + #endif if (category == RTW_WLAN_CATEGORY_PUBLIC) RTW_INFO("RTW_Tx:%s\n", action_public_str(action)); else @@ -3563,11 +3813,13 @@ static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_de } -static void rtw_cfg80211_monitor_if_set_multicast_list(struct net_device *ndev) { +static void rtw_cfg80211_monitor_if_set_multicast_list(struct net_device *ndev) +{ RTW_INFO("%s\n", __func__); } -static int rtw_cfg80211_monitor_if_set_mac_address(struct net_device *ndev, void *addr) { +static int rtw_cfg80211_monitor_if_set_mac_address(struct net_device *ndev, void *addr) +{ int ret = 0; RTW_INFO("%s\n", __func__); @@ -3580,14 +3832,15 @@ static const struct net_device_ops rtw_cfg80211_monitor_if_ops = { .ndo_open = rtw_cfg80211_monitor_if_open, .ndo_stop = rtw_cfg80211_monitor_if_close, .ndo_start_xmit = rtw_cfg80211_monitor_if_xmit_entry, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) .ndo_set_multicast_list = rtw_cfg80211_monitor_if_set_multicast_list, -#endif + #endif .ndo_set_mac_address = rtw_cfg80211_monitor_if_set_mac_address, }; #endif -static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct net_device **ndev) { +static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct net_device **ndev) +{ int ret = 0; struct net_device *mon_ndev = NULL; struct wireless_dev *mon_wdev = NULL; @@ -3602,7 +3855,7 @@ static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct ne if (pwdev_priv->pmon_ndev) { RTW_INFO(FUNC_ADPT_FMT" monitor interface exist: "NDEV_FMT"\n", - FUNC_ADPT_ARG(padapter), NDEV_ARG(pwdev_priv->pmon_ndev)); + FUNC_ADPT_ARG(padapter), NDEV_ARG(pwdev_priv->pmon_ndev)); ret = -EBUSY; goto out; } @@ -3617,12 +3870,12 @@ static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct ne mon_ndev->type = ARPHRD_IEEE80211_RADIOTAP; strncpy(mon_ndev->name, name, IFNAMSIZ); mon_ndev->name[IFNAMSIZ - 1] = 0; -#if (LINUX_VERSION_CODE>=KERNEL_VERSION(4,11,9)) - mon_ndev->needs_free_netdev = true; - mon_ndev->priv_destructor = rtw_ndev_destructor; -#else - mon_ndev->destructor = rtw_ndev_destructor; -#endif + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(4,11,9)) + mon_ndev->needs_free_netdev = true; + mon_ndev->priv_destructor = rtw_ndev_destructor; + #else + mon_ndev->destructor = rtw_ndev_destructor; + #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) mon_ndev->netdev_ops = &rtw_cfg80211_monitor_if_ops; @@ -3678,63 +3931,90 @@ static struct net_device * #else static int #endif -cfg80211_rtw_add_virtual_intf( - struct wiphy *wiphy, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0)) - const char *name, -#else - char *name, -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) - unsigned char name_assign_type, -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)) - enum nl80211_iftype type, struct vif_params *params) -#else - enum nl80211_iftype type, u32 *flags, struct vif_params *params) -#endif - { + cfg80211_rtw_add_virtual_intf( + struct wiphy *wiphy, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0)) + const char *name, + #else + char *name, + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + unsigned char name_assign_type, + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)) + enum nl80211_iftype type, struct vif_params *params) + #else + enum nl80211_iftype type, u32 *flags, struct vif_params *params) + #endif +{ int ret = 0; + struct wireless_dev *wdev = NULL; struct net_device *ndev = NULL; - _adapter *padapter = wiphy_to_adapter(wiphy); + _adapter *padapter; + struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); - RTW_INFO("%s wiphy:%s, name:%s, type:%d\n", - __func__, wiphy_name(wiphy), name, type); + rtw_set_rtnl_lock_holder(dvobj, current); + + RTW_INFO(FUNC_WIPHY_FMT" name:%s, type:%d\n", FUNC_WIPHY_ARG(wiphy), name, type); switch (type) { - case NL80211_IFTYPE_ADHOC: - case NL80211_IFTYPE_AP_VLAN: - case NL80211_IFTYPE_WDS: - case NL80211_IFTYPE_MESH_POINT: - ret = -ENODEV; - break; case NL80211_IFTYPE_MONITOR: + padapter = wiphy_to_adapter(wiphy); /* TODO: get ap iface ? */ ret = rtw_cfg80211_add_monitor_if(padapter, (char *)name, &ndev); + if (ret == 0) + wdev = ndev->ieee80211_ptr; break; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) +#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_CLIENT: + case NL80211_IFTYPE_P2P_GO: #endif case NL80211_IFTYPE_STATION: - ret = -ENODEV; + case NL80211_IFTYPE_AP: + padapter = dvobj_get_unregisterd_adapter(dvobj); + if (!padapter) { + RTW_WARN("adapter pool empty!\n"); + ret = -ENODEV; + break; + } + if (rtw_os_ndev_init(padapter, name) != _SUCCESS) { + RTW_WARN("ndev init fail!\n"); + ret = -ENODEV; + break; + } + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + if (type == NL80211_IFTYPE_P2P_CLIENT || type == NL80211_IFTYPE_P2P_GO) + rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); + #endif + ndev = padapter->pnetdev; + wdev = ndev->ieee80211_ptr; break; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - case NL80211_IFTYPE_P2P_GO: -#endif - case NL80211_IFTYPE_AP: - ret = -ENODEV; +#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE) + case NL80211_IFTYPE_P2P_DEVICE: + ret = rtw_pd_iface_alloc(wiphy, name, &wdev); break; +#endif + + case NL80211_IFTYPE_ADHOC: + case NL80211_IFTYPE_AP_VLAN: + case NL80211_IFTYPE_WDS: + case NL80211_IFTYPE_MESH_POINT: default: ret = -ENODEV; RTW_INFO("Unsupported interface type\n"); break; } - RTW_INFO("%s ndev:%p, ret:%d\n", __func__, ndev, ret); + if (ndev) + RTW_INFO(FUNC_WIPHY_FMT" ndev:%p, ret:%d\n", FUNC_WIPHY_ARG(wiphy), ndev, ret); + else + RTW_INFO(FUNC_WIPHY_FMT" wdev:%p, ret:%d\n", FUNC_WIPHY_ARG(wiphy), wdev, ret); + + rtw_set_rtnl_lock_holder(dvobj, NULL); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - return ndev ? ndev->ieee80211_ptr : ERR_PTR(ret); + return wdev ? wdev : ERR_PTR(ret); #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) return ndev ? ndev : ERR_PTR(ret); #else @@ -3744,39 +4024,58 @@ cfg80211_rtw_add_virtual_intf( static int cfg80211_rtw_del_virtual_intf(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - struct wireless_dev *wdev + struct wireless_dev *wdev #else - struct net_device *ndev + struct net_device *ndev #endif - ) { +) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) struct net_device *ndev = wdev_to_ndev(wdev); #endif int ret = 0; + struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); _adapter *adapter; struct rtw_wdev_priv *pwdev_priv; - if (!ndev) { - ret = -EINVAL; - goto exit; - } - - adapter = (_adapter *)rtw_netdev_priv(ndev); - pwdev_priv = adapter_wdev_data(adapter); + rtw_set_rtnl_lock_holder(dvobj, current); - unregister_netdevice(ndev); + if (ndev) { + adapter = (_adapter *)rtw_netdev_priv(ndev); + pwdev_priv = adapter_wdev_data(adapter); - if (ndev == pwdev_priv->pmon_ndev) { - pwdev_priv->pmon_ndev = NULL; - pwdev_priv->ifname_mon[0] = '\0'; - RTW_INFO(FUNC_NDEV_FMT" remove monitor interface\n", FUNC_NDEV_ARG(ndev)); + if (ndev == pwdev_priv->pmon_ndev) { + unregister_netdevice(ndev); + pwdev_priv->pmon_ndev = NULL; + pwdev_priv->ifname_mon[0] = '\0'; + RTW_INFO(FUNC_NDEV_FMT" remove monitor ndev\n", FUNC_NDEV_ARG(ndev)); + } else { + RTW_INFO(FUNC_NDEV_FMT" unregister ndev\n", FUNC_NDEV_ARG(ndev)); + rtw_os_ndev_unregister(adapter); + } + } else +#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE) + if (wdev->iftype == NL80211_IFTYPE_P2P_DEVICE) { + if (wdev == wiphy_to_pd_wdev(wiphy)) + rtw_pd_iface_free(wiphy); + else { + RTW_ERR(FUNC_WIPHY_FMT" unknown P2P Device wdev:%p\n", FUNC_WIPHY_ARG(wiphy), wdev); + rtw_warn_on(1); + } + } else +#endif + { + ret = -EINVAL; + goto exit; } exit: + rtw_set_rtnl_lock_holder(dvobj, NULL); return ret; } -static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, const u8 *tail, size_t tail_len) { +static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, const u8 *tail, size_t tail_len) +{ int ret = 0; u8 *pbuf = NULL; uint len, wps_ielen = 0; @@ -3831,7 +4130,6 @@ static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, co if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { RTW_INFO("Enable P2P function for the first time\n"); rtw_p2p_enable(adapter, P2P_ROLE_GO); - adapter_wdev_data(adapter)->p2p_enabled = _TRUE; adapter->stapriv.expire_to = 3; /* 3x2 = 6 sec in p2p mode */ } else { @@ -3870,7 +4168,8 @@ static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, co #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE) static int cfg80211_rtw_add_beacon(struct wiphy *wiphy, struct net_device *ndev, - struct beacon_parameters *info) { + struct beacon_parameters *info) +{ int ret = 0; _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); @@ -3881,7 +4180,8 @@ static int cfg80211_rtw_add_beacon(struct wiphy *wiphy, struct net_device *ndev, } static int cfg80211_rtw_set_beacon(struct wiphy *wiphy, struct net_device *ndev, - struct beacon_parameters *info) { + struct beacon_parameters *info) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); @@ -3894,22 +4194,24 @@ static int cfg80211_rtw_set_beacon(struct wiphy *wiphy, struct net_device *ndev, return 0; } -static int cfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *ndev) { +static int cfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *ndev) +{ RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); return 0; } #else static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, - struct cfg80211_ap_settings *settings) { + struct cfg80211_ap_settings *settings) +{ int ret = 0; _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); RTW_INFO(FUNC_NDEV_FMT" hidden_ssid:%d, auth_type:%d\n", FUNC_NDEV_ARG(ndev), - settings->hidden_ssid, settings->auth_type); + settings->hidden_ssid, settings->auth_type); ret = rtw_add_beacon(adapter, settings->beacon.head, settings->beacon.head_len, - settings->beacon.tail, settings->beacon.tail_len); + settings->beacon.tail, settings->beacon.tail_len); adapter->mlmeextpriv.mlmext_info.hidden_ssid_mode = settings->hidden_ssid; @@ -3919,8 +4221,8 @@ static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, if (0) RTW_INFO(FUNC_ADPT_FMT" ssid:(%s,%zu), from ie:(%s,%d)\n", FUNC_ADPT_ARG(adapter), - settings->ssid, settings->ssid_len, - pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength); + settings->ssid, settings->ssid_len, + pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength); _rtw_memcpy(pbss_network->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len); pbss_network->Ssid.SsidLength = settings->ssid_len; @@ -3929,15 +4231,16 @@ static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, if (0) RTW_INFO(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), - pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, - pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); + pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, + pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); } return ret; } static int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *ndev, - struct cfg80211_beacon_data *info) { + struct cfg80211_beacon_data *info) +{ int ret = 0; _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); @@ -3948,7 +4251,8 @@ static int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *nd return ret; } -static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev) { +static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev) +{ RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); return 0; } @@ -3957,7 +4261,8 @@ static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev) { #if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) static int cfg80211_rtw_set_mac_acl(struct wiphy *wiphy, struct net_device *ndev, - const struct cfg80211_acl_data *params) { + const struct cfg80211_acl_data *params) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); u8 acl_mode = RTW_ACL_MODE_DISABLED; int ret = -1; @@ -3969,7 +4274,7 @@ static int cfg80211_rtw_set_mac_acl(struct wiphy *wiphy, struct net_device *ndev } RTW_INFO(FUNC_ADPT_FMT" acl_policy:%d, entry_num:%d\n" - , FUNC_ADPT_ARG(adapter), params->acl_policy, params->n_acl_entries); + , FUNC_ADPT_ARG(adapter), params->acl_policy, params->n_acl_entries); if (params->acl_policy == NL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED) acl_mode = RTW_ACL_MODE_ACCEPT_UNLESS_LISTED; @@ -3979,7 +4284,7 @@ static int cfg80211_rtw_set_mac_acl(struct wiphy *wiphy, struct net_device *ndev if (!params->n_acl_entries) { if (acl_mode != RTW_ACL_MODE_DISABLED) RTW_WARN(FUNC_ADPT_FMT" acl_policy:%d with no entry\n" - , FUNC_ADPT_ARG(adapter), params->acl_policy); + , FUNC_ADPT_ARG(adapter), params->acl_policy); acl_mode = RTW_ACL_MODE_DISABLED; goto exit; } @@ -3997,11 +4302,12 @@ static int cfg80211_rtw_set_mac_acl(struct wiphy *wiphy, struct net_device *ndev static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev, #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)) - u8 *mac, + u8 *mac, #else - const u8 *mac, + const u8 *mac, #endif - struct station_parameters *params) { + struct station_parameters *params) +{ int ret = 0; #ifdef CONFIG_TDLS _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); @@ -4028,13 +4334,14 @@ static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev, #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)) - u8 *mac + u8 *mac #elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)) - const u8 *mac + const u8 *mac #else - struct station_del_parameters *params + struct station_del_parameters *params #endif - ) { +) +{ int ret = 0; _irqL irqL; _list *phead, *plist; @@ -4074,8 +4381,8 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev RTW_INFO("free sta macaddr =" MAC_FMT "\n", MAC_ARG(target_mac)); if (target_mac[0] == 0xff && target_mac[1] == 0xff && - target_mac[2] == 0xff && target_mac[3] == 0xff && - target_mac[4] == 0xff && target_mac[5] == 0xff) + target_mac[2] == 0xff && target_mac[3] == 0xff && + target_mac[4] == 0xff && target_mac[5] == 0xff) return -EINVAL; @@ -4127,11 +4434,12 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev static int cfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *ndev, #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)) - u8 *mac, + u8 *mac, #else - const u8 *mac, + const u8 *mac, #endif - struct station_parameters *params) { + struct station_parameters *params) +{ RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); return 0; @@ -4159,7 +4467,8 @@ struct sta_info *rtw_sta_info_get_by_idx(const int idx, struct sta_priv *pstapri } static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *ndev, - int idx, u8 *mac, struct station_info *sinfo) { + int idx, u8 *mac, struct station_info *sinfo) +{ int ret = 0; _irqL irqL; @@ -4186,36 +4495,39 @@ static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *nde } static int cfg80211_rtw_change_bss(struct wiphy *wiphy, struct net_device *ndev, - struct bss_parameters *params) { + struct bss_parameters *params) +{ u8 i; RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); - /* - RTW_INFO("use_cts_prot=%d\n", params->use_cts_prot); - RTW_INFO("use_short_preamble=%d\n", params->use_short_preamble); - RTW_INFO("use_short_slot_time=%d\n", params->use_short_slot_time); - RTW_INFO("ap_isolate=%d\n", params->ap_isolate); - - RTW_INFO("basic_rates_len=%d\n", params->basic_rates_len); - for(i=0; ibasic_rates_len; i++) - { - RTW_INFO("basic_rates=%d\n", params->basic_rates[i]); - - } - */ +/* + RTW_INFO("use_cts_prot=%d\n", params->use_cts_prot); + RTW_INFO("use_short_preamble=%d\n", params->use_short_preamble); + RTW_INFO("use_short_slot_time=%d\n", params->use_short_slot_time); + RTW_INFO("ap_isolate=%d\n", params->ap_isolate); + + RTW_INFO("basic_rates_len=%d\n", params->basic_rates_len); + for(i = 0; i < params->basic_rates_len; i++) + RTW_INFO("basic_rates=%d\n", params->basic_rates[i]); +*/ return 0; } static int cfg80211_rtw_set_channel(struct wiphy *wiphy + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) + , struct net_device *ndev + #endif + , struct ieee80211_channel *chan, enum nl80211_channel_type channel_type) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) - , struct net_device *ndev + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); +#else + _adapter *padapter = wiphy_to_adapter(wiphy); #endif - , struct ieee80211_channel *chan, enum nl80211_channel_type channel_type) { int chan_target = (u8) ieee80211_frequency_to_channel(chan->center_freq); int chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; int chan_width = CHANNEL_WIDTH_20; - _adapter *padapter = wiphy_to_adapter(wiphy); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); @@ -4248,12 +4560,13 @@ static int cfg80211_rtw_set_channel(struct wiphy *wiphy static int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) - , struct cfg80211_chan_def *chandef + , struct cfg80211_chan_def *chandef #else - , struct ieee80211_channel *chan - , enum nl80211_channel_type channel_type + , struct ieee80211_channel *chan + , enum nl80211_channel_type channel_type #endif - ) { +) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) struct ieee80211_channel *chan = chandef->chan; #endif @@ -4266,11 +4579,11 @@ static int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("center_freq %u Mhz ch %u width %u freq1 %u freq2 %u\n" - , chan->center_freq - , chan->hw_value - , chandef->width - , chandef->center_freq1 - , chandef->center_freq2); + , chan->center_freq + , chan->hw_value + , chandef->width + , chandef->center_freq1 + , chandef->center_freq2); #endif /* CONFIG_DEBUG_CFG80211 */ switch (chandef->width) { @@ -4311,9 +4624,9 @@ static int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy #else #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("center_freq %u Mhz ch %u channel_type %u\n" - , chan->center_freq - , chan->hw_value - , channel_type); + , chan->center_freq + , chan->hw_value + , channel_type); #endif /* CONFIG_DEBUG_CFG80211 */ switch (channel_type) { @@ -4343,109 +4656,156 @@ static int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy } static int cfg80211_rtw_auth(struct wiphy *wiphy, struct net_device *ndev, - struct cfg80211_auth_request *req) { + struct cfg80211_auth_request *req) +{ RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); return 0; } static int cfg80211_rtw_assoc(struct wiphy *wiphy, struct net_device *ndev, - struct cfg80211_assoc_request *req) { + struct cfg80211_assoc_request *req) +{ RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); return 0; } #endif /* CONFIG_AP_MODE */ -void rtw_cfg80211_rx_probe_request(_adapter *adapter, u8 *frame, uint frame_len) { - s32 freq; - int channel; - struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); +void rtw_cfg80211_rx_probe_request(_adapter *adapter, union recv_frame *rframe) +{ + struct wireless_dev *wdev = adapter->rtw_wdev; struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); - u8 category, action; + u8 *frame = get_recvframe_data(rframe); + uint frame_len = rframe->u.hdr.len; + s32 freq; + u8 ch, sch = rtw_get_oper_ch(adapter); - channel = rtw_get_oper_ch(adapter); - freq = rtw_ch2freq(channel); + ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; + freq = rtw_ch2freq(ch); #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("RTW_Rx: probe request, cur_ch=%d\n", channel); -#endif /* CONFIG_DEBUG_CFG80211 */ - rtw_cfg80211_rx_mgmt(adapter, freq, 0, frame, frame_len, GFP_ATOMIC); + RTW_INFO("RTW_Rx: probe request, ch=%d(%d)\n", ch, sch); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); +#else + cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); +#endif } -void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) { - int type; +void rtw_cfg80211_rx_action_p2p(_adapter *adapter, union recv_frame *rframe) +{ + struct wireless_dev *wdev = adapter->rtw_wdev; + u8 *frame = get_recvframe_data(rframe); + uint frame_len = rframe->u.hdr.len; s32 freq; - int channel; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + u8 ch, sch = rtw_get_oper_ch(adapter); u8 category, action; + int type; - channel = rtw_get_oper_ch(padapter); + ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; + freq = rtw_ch2freq(ch); - RTW_INFO("RTW_Rx:cur_ch=%d\n", channel); + RTW_INFO("RTW_Rx:ch=%d(%d)\n", ch, sch); #ifdef CONFIG_P2P - type = rtw_p2p_check_frames(padapter, pmgmt_frame, frame_len, _FALSE); + type = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE); if (type >= 0) goto indicate; #endif - rtw_action_frame_parse(pmgmt_frame, frame_len, &category, &action); + rtw_action_frame_parse(frame, frame_len, &category, &action); RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action); indicate: - freq = rtw_ch2freq(channel); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); + rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); #else - cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); + cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); #endif } -void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) { - int type; +void rtw_cfg80211_rx_p2p_action_public(_adapter *adapter, union recv_frame *rframe) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct wireless_dev *wdev = adapter->rtw_wdev; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); + u8 *frame = get_recvframe_data(rframe); + uint frame_len = rframe->u.hdr.len; s32 freq; - int channel; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + u8 ch, sch = rtw_get_oper_ch(adapter); u8 category, action; + int type; - channel = rtw_get_oper_ch(padapter); + ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; + freq = rtw_ch2freq(ch); - RTW_INFO("RTW_Rx:cur_ch=%d\n", channel); -#ifdef CONFIG_P2P - type = rtw_p2p_check_frames(padapter, pmgmt_frame, frame_len, _FALSE); + RTW_INFO("RTW_Rx:ch=%d(%d)\n", ch, sch); + #ifdef CONFIG_P2P + type = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE); if (type >= 0) { switch (type) { case P2P_GO_NEGO_CONF: + if (0) { + RTW_INFO(FUNC_ADPT_FMT" Nego confirm. state=%u, status=%u, iaddr="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status + , MAC_ARG(pwdev_priv->nego_info.iface_addr)); + } + if (pwdev_priv->nego_info.state == 2 + && pwdev_priv->nego_info.status == 0 + && rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE + ) { + _adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr); + + if (intended_iface) { + RTW_INFO(FUNC_ADPT_FMT" Nego confirm. Allow only "ADPT_FMT" to scan for 2000 ms\n" + , FUNC_ADPT_ARG(adapter), ADPT_ARG(intended_iface)); + /* allow only intended_iface to do scan for 2000 ms */ + rtw_mi_set_scan_deny(adapter, 2000); + rtw_clear_scan_deny(intended_iface); + } + } + break; case P2P_PROVISION_DISC_RESP: case P2P_INVIT_RESP: - /*rtw_mi_set_scan_deny(padapter, 2000); - rtw_clear_scan_deny(padapter);*/ - rtw_mi_buddy_set_scan_deny(padapter, 2000); + #if !RTW_P2P_GROUP_INTERFACE + rtw_mi_buddy_set_scan_deny(adapter, 2000); + #endif + break; } goto indicate; } -#endif - rtw_action_frame_parse(pmgmt_frame, frame_len, &category, &action); + #endif + rtw_action_frame_parse(frame, frame_len, &category, &action); RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action); indicate: - freq = rtw_ch2freq(channel); + #if defined(RTW_DEDICATED_P2P_DEVICE) + if (rtw_cfg80211_redirect_pd_wdev(dvobj_to_wiphy(dvobj), get_ra(frame), &wdev)) + if (0) + RTW_INFO("redirect to pd_wdev:%p\n", wdev); + #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); + rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); #else - cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); + cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); #endif } -void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const char *msg) { - s32 freq; - int channel; - struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); +void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg) +{ + struct wireless_dev *wdev = adapter->rtw_wdev; struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); + u8 *frame = get_recvframe_data(rframe); + uint frame_len = rframe->u.hdr.len; + s32 freq; + u8 ch, sch = rtw_get_oper_ch(adapter); u8 category, action; - channel = rtw_get_oper_ch(adapter); + ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; + freq = rtw_ch2freq(ch); rtw_action_frame_parse(frame, frame_len, &category, &action); @@ -4454,15 +4814,13 @@ void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const rtw_mi_scan_abort(adapter, _FALSE); /*rtw_scan_abort_no_wait*/ } - freq = rtw_ch2freq(channel); - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - rtw_cfg80211_rx_mgmt(adapter, freq, 0, frame, frame_len, GFP_ATOMIC); + rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); #else cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); #endif - RTW_INFO("RTW_Rx:cur_ch=%d\n", channel); + RTW_INFO("RTW_Rx:ch=%d(%d)\n", ch, sch); if (msg) RTW_INFO("RTW_Rx:%s\n", msg); else @@ -4470,7 +4828,8 @@ void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const } #ifdef CONFIG_P2P -void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len) { +void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len) +{ u16 wps_devicepassword_id = 0x0000; uint wps_devicepassword_id_len = 0; u8 wpsie[255] = { 0x00 }, p2p_ie[255] = { 0x00 }; @@ -4575,14 +4934,14 @@ void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_ACTION); + set_frame_sub_type(pframe, WIFI_ACTION); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); - pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) & (p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); @@ -4683,34 +5042,87 @@ void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS) RTW_INFO("%s, ack to\n", __func__); - /* if(wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) */ - /* { */ - /* RTW_INFO("waiting for p2p peer key-in PIN CODE\n"); */ - /* rtw_msleep_os(15000); */ /* 15 sec for key in PIN CODE, workaround for GS2 before issuing Nego Req. */ - /* } */ + #if 0 + if(wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) { + RTW_INFO("waiting for p2p peer key-in PIN CODE\n"); + rtw_msleep_os(15000); /* 15 sec for key in PIN CODE, workaround for GS2 before issuing Nego Req. */ + } + #endif } +#ifdef CONFIG_RTW_80211R +static s32 cfg80211_rtw_update_ft_ies(struct wiphy *wiphy, + struct net_device *ndev, + struct cfg80211_update_ft_ies_params *ftie) +{ + _adapter *padapter = NULL; + struct mlme_priv *pmlmepriv = NULL; + ft_priv *pftpriv = NULL; + _irqL irqL; + u8 *p; + u8 *pie = NULL; + u32 ie_len = 0; + + if (ndev == NULL) + return -EINVAL; + + padapter = (_adapter *)rtw_netdev_priv(ndev); + pmlmepriv = &(padapter->mlmepriv); + pftpriv = &pmlmepriv->ftpriv; + + p = (u8 *)ftie->ie; + if (ftie->ie_len <= sizeof(pftpriv->updated_ft_ies)) { + _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_memcpy(pftpriv->updated_ft_ies, ftie->ie, ftie->ie_len); + pftpriv->updated_ft_ies_len = ftie->ie_len; + _exit_critical_bh(&pmlmepriv->lock, &irqL); + } else { + RTW_ERR("FTIEs parsing fail!\n"); + return -EINVAL; + } + + if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_status(padapter, RTW_FT_AUTHENTICATED_STA)) { + RTW_PRINT("auth success, start reassoc\n"); + _enter_critical_bh(&pmlmepriv->lock, &irqL); + rtw_set_ft_status(padapter, RTW_FT_ASSOCIATING_STA); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + start_clnt_assoc(padapter); + } + + return 0; +} +#endif + +inline void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val) +{ + adapter->cfg80211_wdinfo.is_ro_ch = val; + rtw_mi_update_iface_status(&(adapter->mlmepriv), 0); +} + +inline bool rtw_cfg80211_get_is_roch(_adapter *adapter) +{ + return adapter->cfg80211_wdinfo.is_ro_ch; +} + static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - struct wireless_dev *wdev, + struct wireless_dev *wdev, #else - struct net_device *ndev, + struct net_device *ndev, #endif - struct ieee80211_channel *channel, + struct ieee80211_channel *channel, #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) - enum nl80211_channel_type channel_type, -#endif - unsigned int duration, u64 *cookie) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - struct net_device *ndev = wdev_to_ndev(wdev); + enum nl80211_channel_type channel_type, #endif + unsigned int duration, u64 *cookie) +{ s32 err = 0; u8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq); u8 union_ch = 0, union_bw = 0, union_offset = 0; u8 i; u8 ready_on_channel = _FALSE; - _adapter *padapter; + _adapter *padapter = NULL; _adapter *iface; struct dvobj_priv *dvobj; struct rtw_wdev_priv *pwdev_priv; @@ -4719,15 +5131,34 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, struct cfg80211_wifidirect_info *pcfg80211_wdinfo; u8 is_p2p_find = _FALSE; -#ifndef CONFIG_RADIO_WORK /*define for Android L*/ +#ifndef CONFIG_RADIO_WORK #define RTW_ROCH_DURATION_ENLARGE #define RTW_ROCH_BACK_OP #endif - if (ndev == NULL) - return -EINVAL; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + #if defined(RTW_DEDICATED_P2P_DEVICE) + if (wdev == wiphy_to_pd_wdev(wiphy)) + padapter = wiphy_to_adapter(wiphy); + else + #endif + if (wdev_to_ndev(wdev)) + padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev)); + else { + err = -EINVAL; + goto exit; + } +#else + struct wireless_dev *wdev; + if (ndev == NULL) { + err = -EINVAL; + goto exit; + } padapter = (_adapter *)rtw_netdev_priv(ndev); + wdev = ndev_to_wdev(ndev); +#endif + dvobj = adapter_to_dvobj(padapter); pwdev_priv = adapter_wdev_data(padapter); pmlmeext = &padapter->mlmeextpriv; @@ -4739,39 +5170,29 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, *cookie = ATOMIC_INC_RETURN(&pcfg80211_wdinfo->ro_ch_cookie_gen); - RTW_INFO(FUNC_ADPT_FMT" ch:%u duration:%d, cookie:0x%llx\n", FUNC_ADPT_ARG(padapter), remain_ch, duration, *cookie); + RTW_INFO(FUNC_ADPT_FMT"%s ch:%u duration:%d, cookie:0x%llx\n" + , FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : "" + , remain_ch, duration, *cookie); + + if (rtw_chset_search_ch(adapter_to_chset(padapter), remain_ch) < 0) { + RTW_WARN(FUNC_ADPT_FMT" invalid ch:%u\n", FUNC_ADPT_ARG(padapter), remain_ch); + err = -EFAULT; + goto exit; + } #ifdef CONFIG_MP_INCLUDED - if (rtw_mi_mp_mode_check(padapter)) { + if (rtw_mp_mode_check(padapter)) { RTW_INFO("MP mode block remain_on_channel request\n"); err = -EFAULT; goto exit; } #endif - if (pcfg80211_wdinfo->is_ro_ch == _TRUE) { - RTW_INFO("%s, cancel ro ch timer\n", __func__); - _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); -#ifdef CONFIG_CONCURRENT_MODE - ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); -#endif /* CONFIG_CONCURRENT_MODE */ - p2p_protocol_wk_hdl(padapter, P2P_RO_CH_WK); - } - - pcfg80211_wdinfo->is_ro_ch = _TRUE; - pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); - if (_FAIL == rtw_pwr_wakeup(padapter)) { err = -EFAULT; goto exit; } - _rtw_memcpy(&pcfg80211_wdinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel)); -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) - pcfg80211_wdinfo->remain_on_ch_type = channel_type; -#endif - pcfg80211_wdinfo->remain_on_ch_cookie = *cookie; - rtw_scan_abort(padapter); #ifdef CONFIG_CONCURRENT_MODE /*don't scan_abort during p2p_listen.*/ @@ -4779,34 +5200,47 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, rtw_mi_buddy_scan_abort(padapter, _TRUE); #endif /*CONFIG_CONCURRENT_MODE*/ - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS) == _TRUE) { - RTW_INFO(ADPT_FMT"- _FW_UNDER_LINKING |WIFI_UNDER_WPS (mlme state:0x%x)\n", ADPT_ARG(iface), get_fwstate(&iface->mlmepriv)); - remain_ch = iface->mlmeextpriv.cur_channel; - } + if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) { + _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); + p2p_cancel_roch_cmd(padapter, 0, NULL, RTW_CMDF_WAIT_ACK); } /* if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) */ if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); - adapter_wdev_data(padapter)->p2p_enabled = _TRUE; - padapter->wdinfo.listen_channel = remain_ch; - } else if (rtw_p2p_chk_state(pwdinfo , P2P_STATE_LISTEN)) padapter->wdinfo.listen_channel = remain_ch; - else { + RTW_INFO(FUNC_ADPT_FMT" init listen_channel %u\n" + , FUNC_ADPT_ARG(padapter), padapter->wdinfo.listen_channel); + } else if (rtw_p2p_chk_state(pwdinfo , P2P_STATE_LISTEN) + && (time_after_eq((unsigned long)rtw_get_current_time(), (unsigned long)pwdev_priv->probe_resp_ie_update_time) + && rtw_get_passing_time_ms(pwdev_priv->probe_resp_ie_update_time) < 50) + ) { + if (padapter->wdinfo.listen_channel != remain_ch) { + padapter->wdinfo.listen_channel = remain_ch; + RTW_INFO(FUNC_ADPT_FMT" update listen_channel %u\n" + , FUNC_ADPT_ARG(padapter), padapter->wdinfo.listen_channel); + } + } else { rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); -#endif + #endif + } + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS) == _TRUE) { + RTW_INFO(ADPT_FMT"- _FW_UNDER_LINKING |WIFI_UNDER_WPS (mlme state:0x%x)\n", ADPT_ARG(iface), get_fwstate(&iface->mlmepriv)); + remain_ch = iface->mlmeextpriv.cur_channel; + } } rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); -#ifdef RTW_ROCH_DURATION_ENLARGE + #ifdef RTW_ROCH_DURATION_ENLARGE if (duration < 400) duration = duration * 3; /* extend from exper */ -#endif + #endif #if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) if (rtw_mi_check_status(padapter, MI_LINKED)) { @@ -4817,144 +5251,321 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, } #endif /*defined (RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) */ + rtw_cfg80211_set_is_roch(padapter, _TRUE); + pcfg80211_wdinfo->ro_ch_wdev = wdev; + pcfg80211_wdinfo->remain_on_ch_cookie = *cookie; + pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); + _rtw_memcpy(&pcfg80211_wdinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel)); + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) + pcfg80211_wdinfo->remain_on_ch_type = channel_type; + #endif pcfg80211_wdinfo->restore_channel = rtw_get_oper_ch(padapter); - if (rtw_ch_set_search_ch(pmlmeext->channel_set, remain_ch) >= 0) { - #ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) && (0 != rtw_mi_get_union_chan(padapter))) { - if ((remain_ch != rtw_mi_get_union_chan(padapter)) && !check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { - if (ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1 || - (remain_ch != pmlmeext->cur_channel)) { - - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); - ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); - + if (rtw_mi_check_status(padapter, MI_LINKED) && (0 != rtw_mi_get_union_chan(padapter))) { + if ((remain_ch != rtw_mi_get_union_chan(padapter)) && !check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { + if ( #ifdef RTW_ROCH_BACK_OP - RTW_INFO("%s, set switch ch timer, duration=%d\n", __func__, duration - pwdinfo->ext_listen_interval); - _set_timer(&pwdinfo->ap_p2p_switch_timer, duration - pwdinfo->ext_listen_interval); + ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1 || #endif - } - } - - ready_on_channel = _TRUE; - /* pmlmeext->cur_channel = remain_ch; */ - /* set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); */ - } else -#endif /* CONFIG_CONCURRENT_MODE */ - if (remain_ch != rtw_get_oper_ch(padapter)) { - ready_on_channel = _TRUE; - /* pmlmeext->cur_channel = remain_ch; */ - /* set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); */ + (remain_ch != pmlmeext->cur_channel)) { + #ifdef CONFIG_AP_MODE + /*mac-id sleep or wake-up for AP mode*/ + rtw_mi_buddy_ap_acdata_control(padapter, 1); + #endif/*CONFIG_AP_MODE*/ + rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); + #ifdef RTW_ROCH_BACK_OP + RTW_INFO("%s, set switch ch timer, duration=%d\n", __func__, duration - pwdinfo->ext_listen_interval); + ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); + _set_timer(&pwdinfo->ap_p2p_switch_timer, duration - pwdinfo->ext_listen_interval); + #endif } + } + ready_on_channel = _TRUE; } else - RTW_INFO("%s remain_ch:%u not in channel plan!!!!\n", __FUNCTION__, remain_ch); - - - /* call this after other things have been done */ -#ifdef CONFIG_CONCURRENT_MODE - if (ATOMIC_READ(&pwdev_priv->ro_ch_to) == 1 || - (remain_ch != rtw_get_oper_ch(padapter))) { - u8 co_channel = 0xff; - ATOMIC_SET(&pwdev_priv->ro_ch_to, 0); -#endif - - if (ready_on_channel == _TRUE) { - if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { - pmlmeext->cur_channel = remain_ch; - -#ifdef CONFIG_CONCURRENT_MODE - co_channel = rtw_get_oper_ch(padapter); +#endif /* CONFIG_CONCURRENT_MODE */ + { + if (remain_ch != rtw_get_oper_ch(padapter)) + ready_on_channel = _TRUE; + } - if (co_channel != remain_ch) -#endif - { - /* if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic) */ - set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - } + if (ready_on_channel == _TRUE) { + #ifndef RTW_SINGLE_WIPHY + if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) + #endif + { + #ifdef CONFIG_CONCURRENT_MODE + if (rtw_get_oper_ch(padapter) != remain_ch) + #endif + { + /* if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic) */ + set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); } } - RTW_INFO("%s, set ro ch timer, duration=%d\n", __func__, duration); - _set_timer(&pcfg80211_wdinfo->remain_on_ch_timer, duration); - -#ifdef CONFIG_CONCURRENT_MODE } + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_ScanNotify(padapter, _TRUE); #endif - rtw_cfg80211_ready_on_channel(padapter, *cookie, channel, channel_type, duration, GFP_KERNEL); + RTW_INFO("%s, set ro ch timer, duration=%d\n", __func__, duration); + _set_timer(&pcfg80211_wdinfo->remain_on_ch_timer, duration); -exit: - if (err) { - pcfg80211_wdinfo->is_ro_ch = _FALSE; - pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); - } + rtw_cfg80211_ready_on_channel(wdev, *cookie, channel, channel_type, duration, GFP_KERNEL); +exit: return err; } static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - struct wireless_dev *wdev, + struct wireless_dev *wdev, #else - struct net_device *ndev, -#endif - u64 cookie) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - struct net_device *ndev = wdev_to_ndev(wdev); + struct net_device *ndev, #endif + u64 cookie) +{ s32 err = 0; _adapter *padapter; struct rtw_wdev_priv *pwdev_priv; struct wifidirect_info *pwdinfo; struct cfg80211_wifidirect_info *pcfg80211_wdinfo; - if (ndev == NULL) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + #if defined(RTW_DEDICATED_P2P_DEVICE) + if (wdev == wiphy_to_pd_wdev(wiphy)) + padapter = wiphy_to_adapter(wiphy); + else + #endif + if (wdev_to_ndev(wdev)) + padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev)); + else { err = -EINVAL; goto exit; } +#else + struct wireless_dev *wdev; + if (ndev == NULL) { + err = -EINVAL; + goto exit; + } padapter = (_adapter *)rtw_netdev_priv(ndev); + wdev = ndev_to_wdev(ndev); +#endif + pwdev_priv = adapter_wdev_data(padapter); pwdinfo = &padapter->wdinfo; pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; - RTW_INFO(FUNC_ADPT_FMT" cookie:0x%llx\n", FUNC_ADPT_ARG(padapter), cookie); + RTW_INFO(FUNC_ADPT_FMT"%s cookie:0x%llx\n" + , FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : "" + , cookie); - if (pcfg80211_wdinfo->is_ro_ch == _TRUE) { - RTW_INFO("%s, cancel ro ch timer\n", __func__); + if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) { _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); -#ifdef CONFIG_CONCURRENT_MODE - ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); -#endif - p2p_protocol_wk_hdl(padapter, P2P_RO_CH_WK); + p2p_cancel_roch_cmd(padapter, cookie, wdev, RTW_CMDF_WAIT_ACK); } -#if 0 - /* Disable P2P Listen State */ - if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { - rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); - _rtw_memset(pwdinfo, 0x00, sizeof(struct wifidirect_info)); - } - } else +exit: + return err; +} + +inline int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter) +{ + struct wiphy *wiphy = adapter_to_wiphy(adapter); + struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter); + +#if RTW_P2P_GROUP_INTERFACE + if (is_primary_adapter(adapter)) + return 0; +#endif + return 1; +} + +inline int rtw_cfg80211_is_p2p_scan(_adapter *adapter) +{ +#if RTW_P2P_GROUP_INTERFACE + if (rtw_cfg80211_iface_has_p2p_group_cap(adapter)) #endif { - rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); -#ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); + struct wifidirect_info *wdinfo = &adapter->wdinfo; + + return rtw_p2p_chk_state(wdinfo, P2P_STATE_SCAN) + || rtw_p2p_chk_state(wdinfo, P2P_STATE_FIND_PHASE_SEARCH); + } + +#if RTW_P2P_GROUP_INTERFACE + #if defined(RTW_DEDICATED_P2P_DEVICE) + if (wiphy_to_pd_wdev(adapter_to_wiphy(adapter))) /* pd_wdev exist */ + return rtw_cfg80211_is_scan_by_pd_wdev(adapter); + #endif + { + /* + * For 2 RTW_P2P_GROUP_INTERFACE cases: + * 1. RTW_DEDICATED_P2P_DEVICE defined but upper layer don't use pd_wdev or + * 2. RTW_DEDICATED_P2P_DEVICE not defined + */ + struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter); + _irqL irqL; + int is_p2p_scan = 0; + + _enter_critical_bh(&wdev_data->scan_req_lock, &irqL); + if (wdev_data->scan_request + && wdev_data->scan_request->ssids + && wdev_data->scan_request->ie + ) { + if (_rtw_memcmp(wdev_data->scan_request->ssids->ssid, "DIRECT-", 7) + && rtw_get_p2p_ie((u8 *)wdev_data->scan_request->ie, wdev_data->scan_request->ie_len, NULL, NULL)) + is_p2p_scan = 1; + } + _exit_critical_bh(&wdev_data->scan_req_lock, &irqL); + + return is_p2p_scan; + } #endif +} + +#if defined(RTW_DEDICATED_P2P_DEVICE) +int rtw_pd_iface_alloc(struct wiphy *wiphy, const char *name, struct wireless_dev **pd_wdev) +{ + struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy); + struct wireless_dev *wdev = NULL; + struct rtw_netdev_priv_indicator *npi; + _adapter *primary_adpt = wiphy_to_adapter(wiphy); + int ret = 0; + + if (wiphy_data->pd_wdev) { + RTW_WARN(FUNC_WIPHY_FMT" pd_wdev already exists\n", FUNC_WIPHY_ARG(wiphy)); + ret = -EBUSY; + goto exit; } - pcfg80211_wdinfo->is_ro_ch = _FALSE; - pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); + wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev)); + if (!wdev) { + RTW_WARN(FUNC_WIPHY_FMT" allocate wdev fail\n", FUNC_WIPHY_ARG(wiphy)); + ret = -ENOMEM; + goto exit; + } + + wdev->wiphy = wiphy; + wdev->iftype = NL80211_IFTYPE_P2P_DEVICE; + _rtw_memcpy(wdev->address, adapter_mac_addr(primary_adpt), ETH_ALEN); + + wiphy_data->pd_wdev = wdev; + *pd_wdev = wdev; + + RTW_INFO(FUNC_WIPHY_FMT" pd_wdev:%p, addr="MAC_FMT" added\n" + , FUNC_WIPHY_ARG(wiphy), wdev, MAC_ARG(wdev_address(wdev))); exit: - return err; + if (ret && wdev) { + rtw_mfree((u8 *)wdev, sizeof(struct wireless_dev)); + wdev = NULL; + } + + return ret; } +void rtw_pd_iface_free(struct wiphy *wiphy) +{ + struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); + struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy); + u8 rtnl_lock_needed; + + if (!wiphy_data->pd_wdev) + goto exit; + + RTW_INFO(FUNC_WIPHY_FMT" pd_wdev:%p, addr="MAC_FMT"\n" + , FUNC_WIPHY_ARG(wiphy), wiphy_data->pd_wdev + , MAC_ARG(wdev_address(wiphy_data->pd_wdev))); + + rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj); + if (rtnl_lock_needed) + rtnl_lock(); + cfg80211_unregister_wdev(wiphy_data->pd_wdev); + if (rtnl_lock_needed) + rtnl_unlock(); + + rtw_mfree((u8 *)wiphy_data->pd_wdev, sizeof(struct wireless_dev)); + wiphy_data->pd_wdev = NULL; + +exit: + return; +} + +static int cfg80211_rtw_start_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev) +{ + _adapter *adapter = wiphy_to_adapter(wiphy); + + RTW_INFO(FUNC_WIPHY_FMT" wdev=%p\n", FUNC_WIPHY_ARG(wiphy), wdev); + + rtw_p2p_enable(adapter, P2P_ROLE_DEVICE); + return 0; +} + +static void cfg80211_rtw_stop_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev) +{ + _adapter *adapter = wiphy_to_adapter(wiphy); + + RTW_INFO(FUNC_WIPHY_FMT" wdev=%p\n", FUNC_WIPHY_ARG(wiphy), wdev); + + if (rtw_cfg80211_is_p2p_scan(adapter)) + rtw_scan_abort(adapter); + + rtw_p2p_enable(adapter, P2P_ROLE_DISABLE); +} + +inline int rtw_cfg80211_redirect_pd_wdev(struct wiphy *wiphy, u8 *ra, struct wireless_dev **wdev) +{ + struct wireless_dev *pd_wdev = wiphy_to_pd_wdev(wiphy); + + if (pd_wdev && pd_wdev != *wdev + && _rtw_memcmp(wdev_address(pd_wdev), ra, ETH_ALEN) == _TRUE + ) { + *wdev = pd_wdev; + return 1; + } + return 0; +} + +inline int rtw_cfg80211_is_scan_by_pd_wdev(_adapter *adapter) +{ + struct wiphy *wiphy = adapter_to_wiphy(adapter); + struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter); + struct wireless_dev *wdev = NULL; + _irqL irqL; + + _enter_critical_bh(&wdev_data->scan_req_lock, &irqL); + if (wdev_data->scan_request) + wdev = wdev_data->scan_request->wdev; + _exit_critical_bh(&wdev_data->scan_req_lock, &irqL); + + if (wdev && wdev == wiphy_to_pd_wdev(wiphy)) + return 1; + + return 0; +} +#endif /* RTW_DEDICATED_P2P_DEVICE */ #endif /* CONFIG_P2P */ -static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, const u8 *buf, size_t len, int wait_ack) { +inline void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val) +{ + struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter); + + wdev_priv->is_mgmt_tx = val; + rtw_mi_update_iface_status(&(adapter->mlmepriv), 0); +} + +inline u8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter) +{ + struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter); + + return wdev_priv->is_mgmt_tx; +} + +static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack) +{ struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; unsigned char *pframe; @@ -4974,19 +5585,31 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, const u8 *buf, si rtw_mi_set_scan_deny(padapter, 1000); rtw_mi_scan_abort(padapter, _TRUE); + rtw_cfg80211_set_is_mgmt_tx(padapter, 1); + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_ScanNotify(padapter, _TRUE); +#endif + #ifdef CONFIG_P2P - if (padapter->cfg80211_wdinfo.is_ro_ch == _TRUE) { - /* RTW_INFO("%s, cancel ro ch timer\n", __func__); */ - /* _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); */ - /* padapter->cfg80211_wdinfo.is_ro_ch = _FALSE; */ -#ifdef CONFIG_CONCURRENT_MODE + if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) { + #ifdef CONFIG_CONCURRENT_MODE if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { RTW_INFO("%s, extend ro ch time\n", __func__); _set_timer(&padapter->cfg80211_wdinfo.remain_on_ch_timer, pwdinfo->ext_listen_period); } -#endif /* CONFIG_CONCURRENT_MODE */ + #endif /* CONFIG_CONCURRENT_MODE */ } #endif /* CONFIG_P2P */ + +#ifdef CONFIG_MCC_MODE + if (MCC_EN(padapter)) { + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + /* don't set channel, issue frame directly */ + goto issue_mgmt_frame; + } +#endif /* CONFIG_MCC_MODE */ + #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED)) { u8 union_ch = rtw_mi_get_union_chan(padapter); @@ -4997,6 +5620,10 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, const u8 *buf, si u16 ext_listen_period; if (ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1) { + #ifdef CONFIG_AP_MODE + /*mac-id sleep or wake-up for AP mode*/ + rtw_mi_buddy_ap_acdata_control(padapter, 1); + #endif/*CONFIG_AP_MODE*/ rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); /* RTW_INFO("%s, set switch ch timer, period=%d\n", __func__, pwdinfo->ext_listen_period); */ @@ -5005,13 +5632,13 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, const u8 *buf, si if (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) ext_listen_period = 500;/*500ms*/ +#ifdef CONFIG_P2P else ext_listen_period = pwdinfo->ext_listen_period; - - RTW_INFO("%s, set switch ch timer, period=%d\n", __func__, ext_listen_period); _set_timer(&pwdinfo->ap_p2p_switch_timer, ext_listen_period); - +#endif + RTW_INFO("%s, set switch ch timer, period=%d\n", __func__, ext_listen_period); } if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) @@ -5021,13 +5648,14 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, const u8 *buf, si set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); } else #endif /* CONFIG_CONCURRENT_MODE */ - /* if (tx_ch != pmlmeext->cur_channel) { */ - if (tx_ch != rtw_get_oper_ch(padapter)) { - if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) - pmlmeext->cur_channel = tx_ch; - set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - } + /* if (tx_ch != pmlmeext->cur_channel) { */ + if (tx_ch != rtw_get_oper_ch(padapter)) { + if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) + pmlmeext->cur_channel = tx_ch; + set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } +issue_mgmt_frame: /* starting alloc mgmt frame to dump it */ pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) { @@ -5039,6 +5667,13 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, const u8 *buf, si /* update attribute */ pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); + + if (no_cck && IS_CCK_RATE(pattrib->rate)) { + /* force OFDM 6M rate*/ + pattrib->rate = MGN_6M; + pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G); + } + pattrib->retry_ctrl = _FALSE; _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); @@ -5083,6 +5718,11 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, const u8 *buf, si ret = _SUCCESS; } exit: + rtw_cfg80211_set_is_mgmt_tx(padapter, 0); + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_ScanNotify(padapter, _FALSE); +#endif #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s, ret=%d\n", __func__, ret); @@ -5094,38 +5734,36 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, const u8 *buf, si static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - struct wireless_dev *wdev, + struct wireless_dev *wdev, #else - struct net_device *ndev, + struct net_device *ndev, #endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) || defined(COMPAT_KERNEL_RELEASE) - struct ieee80211_channel *chan, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) - bool offchan, -#endif -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) - enum nl80211_channel_type channel_type, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - bool channel_type_valid, -#endif -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) - unsigned int wait, -#endif - const u8 *buf, size_t len, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) - bool no_cck, -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) - bool dont_wait_for_ack, -#endif + struct ieee80211_channel *chan, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) + bool offchan, + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) + enum nl80211_channel_type channel_type, + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) + bool channel_type_valid, + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) + unsigned int wait, + #endif + const u8 *buf, size_t len, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + bool no_cck, + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + bool dont_wait_for_ack, + #endif #else - struct cfg80211_mgmt_tx_params *params, -#endif - u64 *cookie) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - struct net_device *ndev = wdev_to_ndev(wdev); + struct cfg80211_mgmt_tx_params *params, #endif + u64 *cookie) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(COMPAT_KERNEL_RELEASE) struct ieee80211_channel *chan = params->chan; bool offchan = params->offchan; @@ -5134,6 +5772,9 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, size_t len = params->len; bool no_cck = params->no_cck; bool dont_wait_for_ack = params->dont_wait_for_ack; +#endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) + bool no_cck = 0; #endif int ret = 0; int tx_ret; @@ -5147,51 +5788,75 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, int type = (-1); u32 start = rtw_get_current_time(); _adapter *padapter; + struct dvobj_priv *dvobj; struct rtw_wdev_priv *pwdev_priv; - if ((ndev == NULL) || (chan == NULL)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + #if defined(RTW_DEDICATED_P2P_DEVICE) + if (wdev == wiphy_to_pd_wdev(wiphy)) + padapter = wiphy_to_adapter(wiphy); + else + #endif + if (wdev_to_ndev(wdev)) + padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev)); + else { + ret = -EINVAL; + goto exit; + } +#else + struct wireless_dev *wdev; + + if (ndev == NULL) { + ret = -EINVAL; + goto exit; + } + padapter = (_adapter *)rtw_netdev_priv(ndev); + wdev = ndev_to_wdev(ndev); +#endif + + if (chan == NULL) { ret = -EINVAL; goto exit; } tx_ch = (u8)ieee80211_frequency_to_channel(chan->center_freq); - padapter = (_adapter *)rtw_netdev_priv(ndev); + dvobj = adapter_to_dvobj(padapter); pwdev_priv = adapter_wdev_data(padapter); /* cookie generation */ *cookie = (unsigned long) buf; #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO(FUNC_ADPT_FMT" len=%zu, ch=%d" -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) - ", ch_type=%d" -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - ", channel_type_valid=%d" -#endif -#endif - "\n", FUNC_ADPT_ARG(padapter), - len, tx_ch -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) - , channel_type -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - , channel_type_valid -#endif -#endif - ); + RTW_INFO(FUNC_ADPT_FMT"%s len=%zu, ch=%d" + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) + ", ch_type=%d" + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) + ", channel_type_valid=%d" + #endif + "\n", FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : "" + , len, tx_ch + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) + , channel_type + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) + , channel_type_valid + #endif + ); #endif /* CONFIG_DEBUG_CFG80211 */ /* indicate ack before issue frame to avoid racing with rsp frame */ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - rtw_cfg80211_mgmt_tx_status(padapter, *cookie, buf, len, ack, GFP_KERNEL); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + rtw_cfg80211_mgmt_tx_status(wdev, *cookie, buf, len, ack, GFP_KERNEL); +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 36)) cfg80211_action_tx_status(ndev, *cookie, buf, len, ack, GFP_KERNEL); #endif frame_styp = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl) & IEEE80211_FCTL_STYPE; if (IEEE80211_STYPE_PROBE_RESP == frame_styp) { #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("RTW_Tx: probe_resp tx_ch=%d, da="MAC_FMT"\n", tx_ch, MAC_ARG(GetAddr1Ptr(buf))); + RTW_INFO("RTW_Tx: probe_resp tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf))); #endif /* CONFIG_DEBUG_CFG80211 */ wait_ack = 0; goto dump; @@ -5199,15 +5864,17 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) { RTW_INFO(FUNC_ADPT_FMT" frame_control:0x%x\n", FUNC_ADPT_ARG(padapter), - le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl)); + le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl)); goto exit; } - RTW_INFO("RTW_Tx:tx_ch=%d, da="MAC_FMT"\n", tx_ch, MAC_ARG(GetAddr1Ptr(buf))); + RTW_INFO("RTW_Tx:tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf))); #ifdef CONFIG_P2P type = rtw_p2p_check_frames(padapter, buf, len, _TRUE); - if (type >= 0) + if (type >= 0) { + no_cck = 1; /* force no CCK for P2P frames */ goto dump; + } #endif if (category == RTW_WLAN_CATEGORY_PUBLIC) RTW_INFO("RTW_Tx:%s\n", action_public_str(action)); @@ -5227,7 +5894,7 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, u32 retry_guarantee_ms = 0; dump_cnt++; - tx_ret = _cfg80211_rtw_mgmt_tx(padapter, tx_ch, buf, len, wait_ack); + tx_ret = _cfg80211_rtw_mgmt_tx(padapter, tx_ch, no_cck, buf, len, wait_ack); switch (action) { case ACT_PUBLIC_GAS_INITIAL_REQ: @@ -5237,7 +5904,7 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, } if (tx_ret == _SUCCESS - || (dump_cnt >= dump_limit && rtw_get_passing_time_ms(start) >= retry_guarantee_ms)) + || (dump_cnt >= dump_limit && rtw_get_passing_time_ms(start) >= retry_guarantee_ms)) break; if (sleep_ms > 0) @@ -5246,21 +5913,40 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, if (tx_ret != _SUCCESS || dump_cnt > 1) { RTW_INFO(FUNC_ADPT_FMT" %s (%d/%d) in %d ms\n", FUNC_ADPT_ARG(padapter), - tx_ret == _SUCCESS ? "OK" : "FAIL", dump_cnt, dump_limit, rtw_get_passing_time_ms(start)); + tx_ret == _SUCCESS ? "OK" : "FAIL", dump_cnt, dump_limit, rtw_get_passing_time_ms(start)); } switch (type) { case P2P_GO_NEGO_CONF: - rtw_clear_scan_deny(padapter); + if (0) { + RTW_INFO(FUNC_ADPT_FMT" Nego confirm. state=%u, status=%u, iaddr="MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status + , MAC_ARG(pwdev_priv->nego_info.iface_addr)); + } + if (pwdev_priv->nego_info.state == 2 + && pwdev_priv->nego_info.status == 0 + && rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE + ) { + _adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr); + + if (intended_iface) { + RTW_INFO(FUNC_ADPT_FMT" Nego confirm. Allow only "ADPT_FMT" to scan for 2000 ms\n" + , FUNC_ADPT_ARG(padapter), ADPT_ARG(intended_iface)); + /* allow only intended_iface to do scan for 2000 ms */ + rtw_mi_set_scan_deny(padapter, 2000); + rtw_clear_scan_deny(intended_iface); + } + } break; case P2P_INVIT_RESP: if (pwdev_priv->invit_info.flags & BIT(0) - && pwdev_priv->invit_info.status == 0) { + && pwdev_priv->invit_info.status == 0 + ) { RTW_INFO(FUNC_ADPT_FMT" agree with invitation of persistent group\n", - FUNC_ADPT_ARG(padapter)); - /*rtw_set_scan_deny(padapter, 5000); - rtw_clear_scan_deny(padapter);*/ + FUNC_ADPT_ARG(padapter)); + #if !RTW_P2P_GROUP_INTERFACE rtw_mi_buddy_set_scan_deny(padapter, 5000); + #endif rtw_pwr_wakeup_ex(padapter, 5000); } break; @@ -5274,11 +5960,12 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) - struct wireless_dev *wdev, + struct wireless_dev *wdev, #else - struct net_device *ndev, + struct net_device *ndev, #endif - u16 frame_type, bool reg) { + u16 frame_type, bool reg) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) struct net_device *ndev = wdev_to_ndev(wdev); #endif @@ -5294,7 +5981,7 @@ static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy, #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO(FUNC_ADPT_FMT" frame_type:%x, reg:%d\n", FUNC_ADPT_ARG(adapter), - frame_type, reg); + frame_type, reg); #endif /* Wait QC Verify */ @@ -5317,23 +6004,24 @@ static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy, #if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy, - struct net_device *ndev, + struct net_device *ndev, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) - const u8 *peer, + const u8 *peer, #else - u8 *peer, + u8 *peer, #endif - u8 action_code, - u8 dialog_token, - u16 status_code, + u8 action_code, + u8 dialog_token, + u16 status_code, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) - u32 peer_capability, + u32 peer_capability, #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0)) - bool initiator, + bool initiator, #endif - const u8 *buf, - size_t len) { + const u8 *buf, + size_t len) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; @@ -5367,8 +6055,8 @@ static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy, #if 1 RTW_INFO("%s %d\n", __FUNCTION__, __LINE__); RTW_INFO("peer:"MAC_FMT", action code:%d, dialog:%d, status code:%d\n", - MAC_ARG(txmgmt.peer), txmgmt.action_code, - txmgmt.dialog_token, txmgmt.status_code); + MAC_ARG(txmgmt.peer), txmgmt.action_code, + txmgmt.dialog_token, txmgmt.status_code); if (txmgmt.len > 0) { int i = 0; for (; i < len; i++) @@ -5407,13 +6095,14 @@ static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy, } static int cfg80211_rtw_tdls_oper(struct wiphy *wiphy, - struct net_device *ndev, + struct net_device *ndev, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) - const u8 *peer, + const u8 *peer, #else - u8 *peer, + u8 *peer, #endif - enum nl80211_tdls_operation oper) { + enum nl80211_tdls_operation oper) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; struct tdls_txmgmt txmgmt; @@ -5488,8 +6177,9 @@ static int cfg80211_rtw_tdls_oper(struct wiphy *wiphy, #if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, - struct net_device *dev, - struct cfg80211_sched_scan_request *request) { + struct net_device *dev, + struct cfg80211_sched_scan_request *request) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -5501,8 +6191,8 @@ static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, } if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE || - check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE || - check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { + check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE || + check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { RTW_INFO("%s: device is busy.\n", __func__); rtw_scan_abort(padapter); } @@ -5513,7 +6203,7 @@ static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, } ret = rtw_android_cfg80211_pno_setup(dev, request->ssids, - request->n_ssids, request->interval); + request->n_ssids, request->interval); if (ret < 0) { RTW_INFO("%s ret: %d\n", __func__, ret); @@ -5530,12 +6220,14 @@ static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, } static int cfg80211_rtw_sched_scan_stop(struct wiphy *wiphy, - struct net_device *dev) { + struct net_device *dev) +{ return rtw_android_pno_enable(dev, _FALSE); } #endif /* CONFIG_PNO_SUPPORT */ -static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len) { +static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len) +{ int ret = 0; uint wps_ielen = 0; u8 *wps_ie; @@ -5553,9 +6245,9 @@ static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, if (len > 0) { wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen); if (wps_ie) { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("bcn_wps_ielen=%d\n", wps_ielen); -#endif + #endif if (pmlmepriv->wps_beacon_ie) { u32 free_len = pmlmepriv->wps_beacon_ie_len; @@ -5581,12 +6273,12 @@ static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, /* buf += wps_ielen; */ /* len -= wps_ielen; */ -#ifdef CONFIG_P2P + #ifdef CONFIG_P2P p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen); if (p2p_ie) { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("bcn_p2p_ielen=%d\n", p2p_ielen); -#endif + #endif if (pmlmepriv->p2p_beacon_ie) { u32 free_len = pmlmepriv->p2p_beacon_ie_len; @@ -5606,20 +6298,20 @@ static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, pmlmepriv->p2p_beacon_ie_len = p2p_ielen; } -#endif /* CONFIG_P2P */ + #endif /* CONFIG_P2P */ -#ifdef CONFIG_WFD + #ifdef CONFIG_WFD wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen); if (wfd_ie) { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("bcn_wfd_ielen=%d\n", wfd_ielen); -#endif + #endif if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_BEACON_IE, wfd_ie, wfd_ielen) != _SUCCESS) return -EINVAL; } -#endif /* CONFIG_WFD */ + #endif /* CONFIG_WFD */ pmlmeext->bstart_bss = _TRUE; @@ -5629,7 +6321,8 @@ static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, } -static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *buf, int len) { +static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *buf, int len) +{ int ret = 0; uint wps_ielen = 0; u8 *wps_ie; @@ -5650,9 +6343,9 @@ static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *bu uint attr_contentlen = 0; u16 uconfig_method, *puconfig_method = NULL; -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("probe_resp_wps_ielen=%d\n", wps_ielen); -#endif + #endif if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { u8 sr = 0; @@ -5686,11 +6379,11 @@ static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *bu /* struct registry_priv *pregistrypriv = &padapter->registrypriv; */ struct wireless_dev *wdev = padapter->rtw_wdev; -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 /* printk("config_method in wpsie of probe_resp = 0x%x\n", be16_to_cpu(*puconfig_method)); */ -#endif + #endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) /* for WIFI-DIRECT LOGO 4.2.2, AUTO GO can't set PUSH_BUTTON flags */ if (wdev->iftype == NL80211_IFTYPE_P2P_GO) { uconfig_method = WPS_CM_PUSH_BUTTON; @@ -5698,7 +6391,7 @@ static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *bu *puconfig_method &= ~uconfig_method; } -#endif + #endif } _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, wps_ie, wps_ielen); @@ -5709,16 +6402,16 @@ static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *bu /* buf += wps_ielen; */ /* len -= wps_ielen; */ -#ifdef CONFIG_P2P + #ifdef CONFIG_P2P p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen); if (p2p_ie) { u8 is_GO = _FALSE; u32 attr_contentlen = 0; u16 cap_attr = 0; -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("probe_resp_p2p_ielen=%d\n", p2p_ielen); -#endif + #endif /* Check P2P Capability ATTR */ if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) { @@ -5769,20 +6462,20 @@ static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *bu } } -#endif /* CONFIG_P2P */ + #endif /* CONFIG_P2P */ -#ifdef CONFIG_WFD + #ifdef CONFIG_WFD wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen); if (wfd_ie) { -#ifdef CONFIG_DEBUG_CFG80211 + #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("probe_resp_wfd_ielen=%d\n", wfd_ielen); -#endif + #endif if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_RESP_IE, wfd_ie, wfd_ielen) != _SUCCESS) return -EINVAL; } -#endif /* CONFIG_WFD */ + #endif /* CONFIG_WFD */ } @@ -5790,7 +6483,8 @@ static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *bu } -static int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *buf, int len) { +static int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *buf, int len) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(net); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -5851,7 +6545,8 @@ static int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *bu } int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, - int type) { + int type) +{ int ret = 0; uint wps_ielen = 0; u32 p2p_ielen = 0; @@ -5861,10 +6556,10 @@ int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, #endif if ((rtw_get_wps_ie(buf, len, NULL, &wps_ielen) && (wps_ielen > 0)) -#ifdef CONFIG_P2P - || (rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen) && (p2p_ielen > 0)) -#endif - ) { + #ifdef CONFIG_P2P + || (rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen) && (p2p_ielen > 0)) + #endif + ) { if (net != NULL) { switch (type) { case 0x1: /* BEACON */ @@ -5872,6 +6567,10 @@ int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, break; case 0x2: /* PROBE_RESP */ ret = rtw_cfg80211_set_probe_resp_wpsp2pie(net, buf, len); + #ifdef CONFIG_P2P + if (ret == 0) + adapter_wdev_data((_adapter *)rtw_netdev_priv(net))->probe_resp_ie_update_time = rtw_get_current_time(); + #endif break; case 0x4: /* ASSOC_RESP */ ret = rtw_cfg80211_set_assoc_resp_wpsp2pie(net, buf, len); @@ -5884,7 +6583,8 @@ int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, } -static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter, struct ieee80211_sta_ht_cap *ht_cap, enum nl80211_band band, u8 rf_type) { +static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter, struct ieee80211_sta_ht_cap *ht_cap, enum nl80211_band band, u8 rf_type) +{ struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct ht_priv *phtpriv = &pmlmepriv->htpriv; @@ -5903,9 +6603,9 @@ static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter, struct ieee80211_s /* RX STBC */ if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) { /*rtw_rx_stbc 0: disable, bit(0):enable 2.4g, bit(1):enable 5g*/ - if (NL80211_BAND_2GHZ == band) + if (band == NL80211_BAND_2GHZ) stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(0)) ? _TRUE : _FALSE; - if (NL80211_BAND_5GHZ == band) + if (band == NL80211_BAND_5GHZ) stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(1)) ? _TRUE : _FALSE; if (stbc_rx_enable) { @@ -5931,16 +6631,16 @@ static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter, struct ieee80211_s } } -static void rtw_cfg80211_init_ht_capab(_adapter *padapter, struct ieee80211_sta_ht_cap *ht_cap, enum nl80211_band band, u8 rf_type) { -#define MAX_BIT_RATE_40MHZ_MCS23 450 /* Mbps */ -#define MAX_BIT_RATE_40MHZ_MCS15 300 /* Mbps */ -#define MAX_BIT_RATE_40MHZ_MCS7 150 /* Mbps */ +static void rtw_cfg80211_init_ht_capab(_adapter *padapter, struct ieee80211_sta_ht_cap *ht_cap, enum nl80211_band band, u8 rf_type) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + u8 rx_nss = 0; ht_cap->ht_supported = _TRUE; ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | - IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20 | - IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU; + IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20 | + IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU; rtw_cfg80211_init_ht_capab_ex(padapter, ht_cap, band, rf_type); /* @@ -5954,47 +6654,48 @@ static void rtw_cfg80211_init_ht_capab(_adapter *padapter, struct ieee80211_sta_ ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; - /* - *hw->wiphy->bands[NL80211_BAND_2GHZ] - *base on ant_num - *rx_mask: RX mask - *if rx_ant =1 rx_mask[0]=0xff;==>MCS0-MCS7 - *if rx_ant =2 rx_mask[1]=0xff;==>MCS8-MCS15 - *if rx_ant >=3 rx_mask[2]=0xff; - *if BW_40 rx_mask[4]=0x01; - *highest supported RX rate - */ - if (rf_type == RF_1T1R) { + rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num); + switch (rx_nss) { + case 1: ht_cap->mcs.rx_mask[0] = 0xFF; - - ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS7; - } else if ((rf_type == RF_1T2R) || (rf_type == RF_2T2R) || (rf_type == RF_2T2R_GREEN)) { + break; + case 2: ht_cap->mcs.rx_mask[0] = 0xFF; ht_cap->mcs.rx_mask[1] = 0xFF; - - ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS15; - } else if ((rf_type == RF_2T3R) || (rf_type == RF_3T3R)) { + break; + case 3: ht_cap->mcs.rx_mask[0] = 0xFF; ht_cap->mcs.rx_mask[1] = 0xFF; ht_cap->mcs.rx_mask[2] = 0xFF; - - ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS23; - } else { + break; + case 4: + ht_cap->mcs.rx_mask[0] = 0xFF; + ht_cap->mcs.rx_mask[1] = 0xFF; + ht_cap->mcs.rx_mask[2] = 0xFF; + ht_cap->mcs.rx_mask[3] = 0xFF; + break; + default: rtw_warn_on(1); RTW_INFO("%s, error rf_type=%d\n", __func__, rf_type); - } + }; + ht_cap->mcs.rx_highest = rtw_mcs_rate(rf_type + , hal_is_bw_support(padapter, CHANNEL_WIDTH_40) + , hal_is_bw_support(padapter, CHANNEL_WIDTH_40) ? ht_cap->cap & IEEE80211_HT_CAP_SGI_40 : ht_cap->cap & IEEE80211_HT_CAP_SGI_20 + , ht_cap->mcs.rx_mask + ); } -void rtw_cfg80211_init_wdev_data(_adapter *padapter) { +void rtw_cfg80211_init_wdev_data(_adapter *padapter) +{ #ifdef CONFIG_CONCURRENT_MODE struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); ATOMIC_SET(&pwdev_priv->switch_ch_to, 1); - ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); #endif } -void rtw_cfg80211_init_wiphy(_adapter *padapter) { +void rtw_cfg80211_init_wiphy(_adapter *padapter) +{ u8 rf_type; struct ieee80211_supported_band *bands; struct wireless_dev *pwdev = padapter->rtw_wdev; @@ -6009,8 +6710,8 @@ void rtw_cfg80211_init_wiphy(_adapter *padapter) { if (bands) rtw_cfg80211_init_ht_capab(padapter, &bands->ht_cap, NL80211_BAND_2GHZ, rf_type); } -#ifdef CONFIG_NL80211_BAND_5GHZ - if (IsSupported5G(padapter->registrypriv.wireless_mode)) { +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (is_supported_5g(padapter->registrypriv.wireless_mode)) { bands = wiphy->bands[NL80211_BAND_5GHZ]; if (bands) rtw_cfg80211_init_ht_capab(padapter, &bands->ht_cap, NL80211_BAND_5GHZ, rf_type); @@ -6029,32 +6730,43 @@ struct ieee80211_iface_limit rtw_limits[] = { { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) -#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) - | BIT(NL80211_IFTYPE_P2P_CLIENT) -#endif + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + | BIT(NL80211_IFTYPE_P2P_CLIENT) + #endif }, -#ifdef CONFIG_AP_MODE + #ifdef CONFIG_AP_MODE { .max = 1, .types = BIT(NL80211_IFTYPE_AP) -#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) - | BIT(NL80211_IFTYPE_P2P_GO) -#endif + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + | BIT(NL80211_IFTYPE_P2P_GO) + #endif }, -#endif + #endif + #if defined(RTW_DEDICATED_P2P_DEVICE) + { + .max = 1, + .types = BIT(NL80211_IFTYPE_P2P_DEVICE) + } + #endif }; struct ieee80211_iface_combination rtw_combinations[] = { { .limits = rtw_limits, .n_limits = ARRAY_SIZE(rtw_limits), + #if defined(RTW_DEDICATED_P2P_DEVICE) + .max_interfaces = 3, + #else .max_interfaces = 2, + #endif .num_different_channels = 1, }, }; #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) */ -static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) { +static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) +{ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct registry_priv *regsty = dvobj_to_regsty(dvobj); @@ -6073,29 +6785,32 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) { #endif wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) - | BIT(NL80211_IFTYPE_ADHOC) + | BIT(NL80211_IFTYPE_ADHOC) #ifdef CONFIG_AP_MODE - | BIT(NL80211_IFTYPE_AP) -#ifdef CONFIG_WIFI_MONITOR - | BIT(NL80211_IFTYPE_MONITOR) -#endif + | BIT(NL80211_IFTYPE_AP) + #ifdef CONFIG_WIFI_MONITOR + | BIT(NL80211_IFTYPE_MONITOR) + #endif #endif #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) - | BIT(NL80211_IFTYPE_P2P_CLIENT) - | BIT(NL80211_IFTYPE_P2P_GO) + | BIT(NL80211_IFTYPE_P2P_CLIENT) + | BIT(NL80211_IFTYPE_P2P_GO) + #if defined(RTW_DEDICATED_P2P_DEVICE) + | BIT(NL80211_IFTYPE_P2P_DEVICE) + #endif #endif - ; + ; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) #ifdef CONFIG_AP_MODE wiphy->mgmt_stypes = rtw_cfg80211_default_mgmt_stypes; -#endif /* CONFIG_AP_MODE */ +#endif /* CONFIG_AP_MODE */ #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) -#ifdef CONFIG_WIFI_MONITOR + #ifdef CONFIG_WIFI_MONITOR wiphy->software_iftypes |= BIT(NL80211_IFTYPE_MONITOR); -#endif + #endif #endif #if defined(RTW_SINGLE_WIPHY) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) @@ -6109,8 +6824,8 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) { if (IsSupported24G(adapter->registrypriv.wireless_mode)) wiphy->bands[NL80211_BAND_2GHZ] = rtw_spt_band_alloc(NL80211_BAND_2GHZ); -#ifdef CONFIG_NL80211_BAND_5GHZ - if (IsSupported5G(adapter->registrypriv.wireless_mode)) +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (is_supported_5g(adapter->registrypriv.wireless_mode)) wiphy->bands[NL80211_BAND_5GHZ] = rtw_spt_band_alloc(NL80211_BAND_5GHZ); #endif @@ -6132,12 +6847,16 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) { #endif #endif -#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)) - wiphy->wowlan = wowlan_stub; -#else +#ifdef CONFIG_CENTOS_7 wiphy->wowlan = &wowlan_stub; -#endif +#else + #if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)) + wiphy->wowlan = wowlan_stub; + #else + wiphy->wowlan = &wowlan_stub; + #endif + #endif #endif #if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) @@ -6218,6 +6937,14 @@ static struct cfg80211_ops rtw_cfg80211_ops = { #ifdef CONFIG_P2P .remain_on_channel = cfg80211_rtw_remain_on_channel, .cancel_remain_on_channel = cfg80211_rtw_cancel_remain_on_channel, + #if defined(RTW_DEDICATED_P2P_DEVICE) + .start_p2p_device = cfg80211_rtw_start_p2p_device, + .stop_p2p_device = cfg80211_rtw_stop_p2p_device, + #endif +#endif /* CONFIG_P2P */ + +#ifdef CONFIG_RTW_80211R + .update_ft_ies = cfg80211_rtw_update_ft_ies, #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) @@ -6238,18 +6965,25 @@ static struct cfg80211_ops rtw_cfg80211_ops = { #endif /* CONFIG_PNO_SUPPORT */ }; -struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev) { +struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev) +{ struct wiphy *wiphy; struct rtw_wiphy_data *wiphy_data; /* wiphy */ - wiphy = wiphy_new(&rtw_cfg80211_ops, sizeof(_adapter *)); + wiphy = wiphy_new(&rtw_cfg80211_ops, sizeof(struct rtw_wiphy_data)); if (!wiphy) { RTW_INFO("Couldn't allocate wiphy device\n"); goto exit; } set_wiphy_dev(wiphy, dev); - *((_adapter **)wiphy_priv(wiphy)) = padapter; + + /* wiphy_data */ + wiphy_data = rtw_wiphy_priv(wiphy); + wiphy_data->dvobj = adapter_to_dvobj(padapter); +#ifndef RTW_SINGLE_WIPHY + wiphy_data->adapter = padapter; +#endif rtw_cfg80211_preinit_wiphy(padapter, wiphy); @@ -6259,7 +6993,8 @@ struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev) { return wiphy; } -void rtw_wiphy_free(struct wiphy *wiphy) { +void rtw_wiphy_free(struct wiphy *wiphy) +{ if (!wiphy) return; @@ -6277,7 +7012,8 @@ void rtw_wiphy_free(struct wiphy *wiphy) { wiphy_free(wiphy); } -int rtw_wiphy_register(struct wiphy *wiphy) { +int rtw_wiphy_register(struct wiphy *wiphy) +{ RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy)); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) @@ -6287,17 +7023,23 @@ int rtw_wiphy_register(struct wiphy *wiphy) { return wiphy_register(wiphy); } -void rtw_wiphy_unregister(struct wiphy *wiphy) { +void rtw_wiphy_unregister(struct wiphy *wiphy) +{ RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy)); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) rtw_cfgvendor_detach(wiphy); #endif + #if defined(RTW_DEDICATED_P2P_DEVICE) + rtw_pd_iface_free(wiphy); + #endif + return wiphy_unregister(wiphy); } -int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy) { +int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy) +{ int ret = 0; struct net_device *pnetdev = padapter->pnetdev; struct wireless_dev *wdev; @@ -6315,9 +7057,9 @@ int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy) { wdev->wiphy = wiphy; wdev->netdev = pnetdev; - wdev->iftype = NL80211_IFTYPE_STATION; /* will be init in rtw_hal_init() */ - /* Must sync with _rtw_init_mlme_priv() */ - /* pmlmepriv->fw_state = WIFI_STATION_STATE */ + wdev->iftype = NL80211_IFTYPE_STATION; /* will be init in rtw_hal_init() */ + /* Must sync with _rtw_init_mlme_priv() */ + /* pmlmepriv->fw_state = WIFI_STATION_STATE */ /* wdev->iftype = NL80211_IFTYPE_MONITOR; */ /* for rtw_setopmode_cmd() in cfg80211_rtw_change_iface() */ padapter->rtw_wdev = wdev; pnetdev->ieee80211_ptr = wdev; @@ -6330,8 +7072,11 @@ int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy) { pwdev_priv->padapter = padapter; pwdev_priv->scan_request = NULL; _rtw_spinlock_init(&pwdev_priv->scan_req_lock); + pwdev_priv->connect_req = NULL; + _rtw_spinlock_init(&pwdev_priv->connect_req_lock); pwdev_priv->p2p_enabled = _FALSE; + pwdev_priv->probe_resp_ie_update_time = rtw_get_current_time(); pwdev_priv->provdisc_req_issued = _FALSE; rtw_wdev_invit_info_init(&pwdev_priv->invit_info); rtw_wdev_nego_info_init(&pwdev_priv->nego_info); @@ -6343,34 +7088,52 @@ int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy) { else pwdev_priv->power_mgmt = _FALSE; + _rtw_mutex_init(&pwdev_priv->roch_mutex); + #ifdef CONFIG_CONCURRENT_MODE ATOMIC_SET(&pwdev_priv->switch_ch_to, 1); - ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); #endif exit: return ret; } -void rtw_wdev_free(struct wireless_dev *wdev) { - RTW_INFO("%s(wdev=%p)\n", __func__, wdev); - +void rtw_wdev_free(struct wireless_dev *wdev) +{ if (!wdev) return; + RTW_INFO("%s(wdev=%p)\n", __func__, wdev); + + if (wdev_to_ndev(wdev)) { + _adapter *adapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev)); + struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter); + _irqL irqL; + + _rtw_spinlock_free(&wdev_priv->scan_req_lock); + + _enter_critical_bh(&wdev_priv->connect_req_lock, &irqL); + rtw_wdev_free_connect_req(wdev_priv); + _exit_critical_bh(&wdev_priv->connect_req_lock, &irqL); + _rtw_spinlock_free(&wdev_priv->connect_req_lock); + + _rtw_mutex_free(&wdev_priv->roch_mutex); + } + rtw_mfree((u8 *)wdev, sizeof(struct wireless_dev)); } -void rtw_wdev_unregister(struct wireless_dev *wdev) { +void rtw_wdev_unregister(struct wireless_dev *wdev) +{ struct net_device *ndev; _adapter *adapter; struct rtw_wdev_priv *pwdev_priv; - RTW_INFO("%s(wdev=%p)\n", __func__, wdev); - if (!wdev) return; + RTW_INFO("%s(wdev=%p)\n", __func__, wdev); + ndev = wdev_to_ndev(wdev); if (!ndev) return; @@ -6380,18 +7143,12 @@ void rtw_wdev_unregister(struct wireless_dev *wdev) { rtw_cfg80211_indicate_scan_done(adapter, _TRUE); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) || defined(COMPAT_KERNEL_RELEASE) if (wdev->current_bss) { - u8 locally_generated = 1; RTW_INFO(FUNC_ADPT_FMT" clear current_bss by cfg80211_disconnected\n", FUNC_ADPT_ARG(adapter)); - cfg80211_disconnected(adapter->pnetdev, 0, NULL, 0, locally_generated, GFP_ATOMIC); + rtw_cfg80211_indicate_disconnect(adapter, 0, 1); } -#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0))) || defined(COMPAT_KERNEL_RELEASE) - if (wdev->current_bss) { - RTW_INFO(FUNC_ADPT_FMT" clear current_bss by cfg80211_disconnected\n", FUNC_ADPT_ARG(adapter)); - cfg80211_disconnected(adapter->pnetdev, 0, NULL, 0, GFP_ATOMIC); - } -#endif + #endif if (pwdev_priv->pmon_ndev) { RTW_INFO("%s, unregister monitor interface\n", __func__); @@ -6399,7 +7156,8 @@ void rtw_wdev_unregister(struct wireless_dev *wdev) { } } -int rtw_cfg80211_ndev_res_alloc(_adapter *adapter) { +int rtw_cfg80211_ndev_res_alloc(_adapter *adapter) +{ int ret = _FAIL; #if !defined(RTW_SINGLE_WIPHY) @@ -6427,15 +7185,18 @@ int rtw_cfg80211_ndev_res_alloc(_adapter *adapter) { return ret; } -void rtw_cfg80211_ndev_res_free(_adapter *adapter) { +void rtw_cfg80211_ndev_res_free(_adapter *adapter) +{ rtw_wdev_free(adapter->rtw_wdev); + adapter->rtw_wdev = NULL; #if !defined(RTW_SINGLE_WIPHY) rtw_wiphy_free(adapter_to_wiphy(adapter)); adapter->wiphy = NULL; #endif } -int rtw_cfg80211_ndev_res_register(_adapter *adapter) { +int rtw_cfg80211_ndev_res_register(_adapter *adapter) +{ int ret = _FAIL; #if !defined(RTW_SINGLE_WIPHY) @@ -6451,18 +7212,20 @@ int rtw_cfg80211_ndev_res_register(_adapter *adapter) { return ret; } -void rtw_cfg80211_ndev_res_unregister(_adapter *adapter) { +void rtw_cfg80211_ndev_res_unregister(_adapter *adapter) +{ rtw_wdev_unregister(adapter->rtw_wdev); } -int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj) { +int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj) +{ int ret = _FAIL; #if defined(RTW_SINGLE_WIPHY) struct wiphy *wiphy; struct device *dev = dvobj_to_dev(dvobj); - wiphy = rtw_wiphy_alloc(dvobj->padapters[IFACE_ID0], dev); + wiphy = rtw_wiphy_alloc(dvobj_get_primary_adapter(dvobj), dev); if (wiphy == NULL) goto exit; @@ -6475,14 +7238,16 @@ int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj) { return ret; } -void rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj) { +void rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj) +{ #if defined(RTW_SINGLE_WIPHY) rtw_wiphy_free(dvobj_to_wiphy(dvobj)); dvobj->wiphy = NULL; #endif } -int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj) { +int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj) +{ int ret = _FAIL; #if defined(RTW_SINGLE_WIPHY) @@ -6496,7 +7261,8 @@ int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj) { return ret; } -void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj) { +void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj) +{ #if defined(RTW_SINGLE_WIPHY) rtw_wiphy_unregister(dvobj_to_wiphy(dvobj)); #endif diff --git a/os_dep/linux/ioctl_cfg80211.h b/os_dep/linux/ioctl_cfg80211.h index c7f49de..2e5e06f 100644 --- a/os_dep/linux/ioctl_cfg80211.h +++ b/os_dep/linux/ioctl_cfg80211.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,23 +11,61 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __IOCTL_CFG80211_H__ #define __IOCTL_CFG80211_H__ +#ifndef RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT + #define RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT 0 +#endif + #if defined(RTW_USE_CFG80211_STA_EVENT) -#undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER + #undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER +#endif + +#ifndef RTW_P2P_GROUP_INTERFACE + #define RTW_P2P_GROUP_INTERFACE 0 +#endif + +/* +* (RTW_P2P_GROUP_INTERFACE, RTW_DEDICATED_P2P_DEVICE) +* (0, 0): wlan0 + p2p0(PD+PG) +* (1, 0): wlan0(with PD) + dynamic PGs +* (1, 1): wlan0 (with dynamic PD wdev) + dynamic PGs +*/ + +#if RTW_P2P_GROUP_INTERFACE + #ifndef CONFIG_RTW_DYNAMIC_NDEV + #define CONFIG_RTW_DYNAMIC_NDEV + #endif + #ifndef RTW_SINGLE_WIPHY + #define RTW_SINGLE_WIPHY + #endif + #ifndef CONFIG_RADIO_WORK + #define CONFIG_RADIO_WORK + #endif + #ifndef RTW_DEDICATED_P2P_DEVICE + #define RTW_DEDICATED_P2P_DEVICE + #endif +#endif + +#if !defined(CONFIG_P2P) && RTW_P2P_GROUP_INTERFACE + #error "RTW_P2P_GROUP_INTERFACE can't be enabled when CONFIG_P2P is disabled\n" +#endif + +#if !RTW_P2P_GROUP_INTERFACE && defined(RTW_DEDICATED_P2P_DEVICE) + #error "RTW_DEDICATED_P2P_DEVICE can't be enabled when RTW_P2P_GROUP_INTERFACE is disabled\n" +#endif + +#if defined(RTW_DEDICATED_P2P_DEVICE) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0)) + #error "RTW_DEDICATED_P2P_DEVICE can't be enabled when kernel < 3.7.0\n" #endif struct rtw_wdev_invit_info { u8 state; /* 0: req, 1:rep */ u8 peer_mac[ETH_ALEN]; + u8 group_bssid[ETH_ALEN]; u8 active; u8 token; u8 flags; @@ -40,6 +78,7 @@ struct rtw_wdev_invit_info { do { \ (invit_info)->state = 0xff; \ _rtw_memset((invit_info)->peer_mac, 0, ETH_ALEN); \ + _rtw_memset((invit_info)->group_bssid, 0, ETH_ALEN); \ (invit_info)->active = 0xff; \ (invit_info)->token = 0; \ (invit_info)->flags = 0x00; \ @@ -50,7 +89,9 @@ struct rtw_wdev_invit_info { struct rtw_wdev_nego_info { u8 state; /* 0: req, 1:rep, 2:conf */ + u8 iface_addr[ETH_ALEN]; u8 peer_mac[ETH_ALEN]; + u8 peer_iface_addr[ETH_ALEN]; u8 active; u8 token; u8 status; @@ -65,7 +106,9 @@ struct rtw_wdev_nego_info { #define rtw_wdev_nego_info_init(nego_info) \ do { \ (nego_info)->state = 0xff; \ + _rtw_memset((nego_info)->iface_addr, 0, ETH_ALEN); \ _rtw_memset((nego_info)->peer_mac, 0, ETH_ALEN); \ + _rtw_memset((nego_info)->peer_iface_addr, 0, ETH_ALEN); \ (nego_info)->active = 0xff; \ (nego_info)->token = 0; \ (nego_info)->status = 0xff; \ @@ -82,13 +125,21 @@ struct rtw_wdev_priv { _adapter *padapter; + #if !RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT + u8 not_indic_disco; + #endif + struct cfg80211_scan_request *scan_request; _lock scan_req_lock; + struct cfg80211_connect_params *connect_req; + _lock connect_req_lock; + struct net_device *pmon_ndev;/* for monitor interface */ char ifname_mon[IFNAMSIZ + 1]; /* interface name for monitor interface */ u8 p2p_enabled; + u32 probe_resp_ie_update_time; u8 provdisc_req_issued; @@ -103,19 +154,62 @@ struct rtw_wdev_priv { /* report mgmt_frame registered */ u16 report_mgmt; + u8 is_mgmt_tx; + + _mutex roch_mutex; + #ifdef CONFIG_CONCURRENT_MODE - ATOMIC_T ro_ch_to; ATOMIC_T switch_ch_to; #endif }; -#define wiphy_to_adapter(x) (*((_adapter **)wiphy_priv(x))) +#if RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT +#define rtw_wdev_not_indic_disco(rtw_wdev_data) 0 +#define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do {} while (0) +#else +#define rtw_wdev_not_indic_disco(rtw_wdev_data) ((rtw_wdev_data)->not_indic_disco) +#define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do { (rtw_wdev_data)->not_indic_disco = (val); } while (0) +#endif + +#define rtw_wdev_free_connect_req(rtw_wdev_data) \ + do { \ + if ((rtw_wdev_data)->connect_req) { \ + rtw_mfree((u8 *)(rtw_wdev_data)->connect_req, sizeof(*(rtw_wdev_data)->connect_req)); \ + (rtw_wdev_data)->connect_req = NULL; \ + } \ + } while (0) #define wdev_to_ndev(w) ((w)->netdev) #define wdev_to_wiphy(w) ((w)->wiphy) #define ndev_to_wdev(n) ((n)->ieee80211_ptr) +struct rtw_wiphy_data { + struct dvobj_priv *dvobj; + +#ifndef RTW_SINGLE_WIPHY + _adapter *adapter; +#endif + +#if defined(RTW_DEDICATED_P2P_DEVICE) + struct wireless_dev *pd_wdev; /* P2P device wdev */ +#endif +}; + +#define rtw_wiphy_priv(wiphy) ((struct rtw_wiphy_data *)wiphy_priv(wiphy)) +#define wiphy_to_dvobj(wiphy) (((struct rtw_wiphy_data *)wiphy_priv(wiphy))->dvobj) +#ifdef RTW_SINGLE_WIPHY +#define wiphy_to_adapter(wiphy) (dvobj_get_primary_adapter(wiphy_to_dvobj(wiphy))) +#else +#define wiphy_to_adapter(wiphy) (((struct rtw_wiphy_data *)wiphy_priv(wiphy))->adapter) +#endif + +#if defined(RTW_DEDICATED_P2P_DEVICE) +#define wiphy_to_pd_wdev(wiphy) (rtw_wiphy_priv(wiphy)->pd_wdev) +#else +#define wiphy_to_pd_wdev(wiphy) NULL +#endif + #define WIPHY_FMT "%s" #define WIPHY_ARG(wiphy) wiphy_name(wiphy) #define FUNC_WIPHY_FMT "%s("WIPHY_FMT")" @@ -156,31 +250,54 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted); u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms); +#ifdef CONFIG_CONCURRENT_MODE +u8 rtw_cfg80211_scan_via_buddy(_adapter *padapter, struct cfg80211_scan_request *request); +void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_aborted); +#endif + #ifdef CONFIG_AP_MODE void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason); #endif /* CONFIG_AP_MODE */ +#ifdef CONFIG_P2P +void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val); +bool rtw_cfg80211_get_is_roch(_adapter *adapter); + +int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter); +int rtw_cfg80211_is_p2p_scan(_adapter *adapter); +#if defined(RTW_DEDICATED_P2P_DEVICE) +int rtw_cfg80211_redirect_pd_wdev(struct wiphy *wiphy, u8 *ra, struct wireless_dev **wdev); +int rtw_cfg80211_is_scan_by_pd_wdev(_adapter *adapter); +int rtw_pd_iface_alloc(struct wiphy *wiphy, const char *name, struct wireless_dev **pd_wdev); +void rtw_pd_iface_free(struct wiphy *wiphy); +#endif +#endif /* CONFIG_P2P */ + +void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val); +u8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter); + void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len); -void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); -void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); -void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const char *msg); -void rtw_cfg80211_rx_probe_request(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); + +void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, union recv_frame *rframe); +void rtw_cfg80211_rx_action_p2p(_adapter *padapter, union recv_frame *rframe); +void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg); +void rtw_cfg80211_rx_probe_request(_adapter *padapter, union recv_frame *rframe); int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type); bool rtw_cfg80211_pwr_mgmt(_adapter *adapter); #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE) -#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, buf, len, gfp) +#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, buf, len, gfp) #elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) -#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, sig_dbm, buf, len, gfp) +#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, sig_dbm, buf, len, gfp) #elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 12, 0)) -#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, gfp) +#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) #elif (LINUX_VERSION_CODE < KERNEL_VERSION(3 , 18 , 0)) -#define rtw_cfg80211_rx_mgmt(adapter , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev , freq , sig_dbm , buf , len , 0 , gfp) +#define rtw_cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , 0 , gfp) #else -#define rtw_cfg80211_rx_mgmt(adapter , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev , freq , sig_dbm , buf , len , 0) +#define rtw_cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , 0) #endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE) @@ -190,20 +307,47 @@ bool rtw_cfg80211_pwr_mgmt(_adapter *adapter); #endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) -#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->pnetdev, cookie, buf, len, ack, gfp) +#define rtw_cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status(wdev_to_ndev(wdev), cookie, buf, len, ack, gfp) #else -#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->rtw_wdev, cookie, buf, len, ack, gfp) +#define rtw_cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp) #endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) -#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->pnetdev, cookie, chan, channel_type, duration, gfp) -#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->pnetdev, cookie, chan, chan_type, gfp) +#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel(wdev_to_ndev(wdev), cookie, chan, channel_type, duration, gfp) +#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev_to_ndev(wdev), cookie, chan, chan_type, gfp) #elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) -#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, channel_type, duration, gfp) -#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, chan_type, gfp) +#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp) +#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) #else -#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, duration, gfp) -#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, gfp) +#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel(wdev, cookie, chan, duration, gfp) +#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev, cookie, chan, gfp) +#endif + +#define rtw_cfg80211_connect_result(wdev, bssid, req_ie, req_ie_len, resp_ie, resp_ie_len, status, gfp) cfg80211_connect_result(wdev_to_ndev(wdev), bssid, req_ie, req_ie_len, resp_ie, resp_ie_len, status, gfp) + +#ifdef CONFIG_CENTOS_7 +#define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, locally_generated, gfp) +#else +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0)) +#define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, gfp) +#else +#define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, locally_generated, gfp) +#endif +#endif + +#ifdef CONFIG_RTW_80211R +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) +#define rtw_cfg80211_ft_event(adapter, parm) cfg80211_ft_event((adapter)->pnetdev, parm) +#else + #error "Cannot support FT for KERNEL_VERSION < 3.10\n" +#endif +#endif + +#ifdef CONFIG_CENTOS_7 +#else +#if (KERNEL_VERSION(4, 7, 0) >= LINUX_VERSION_CODE) +#define NUM_NL80211_BANDS IEEE80211_NUM_BANDS +#endif #endif #include "rtw_cfgvendor.h" diff --git a/os_dep/linux/ioctl_linux.c b/os_dep/linux/ioctl_linux.c index c23f6dc..3609a77 100644 --- a/os_dep/linux/ioctl_linux.c +++ b/os_dep/linux/ioctl_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,18 +11,16 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _IOCTL_LINUX_C_ #include #include #include #include "../../hal/phydm/phydm_precomp.h" +#ifdef RTW_HALMAC +#include "../../hal/hal_halmac.h" +#endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)) #define iwe_stream_add_event(a, b, c, d, e) iwe_stream_add_event(b, c, d, e) @@ -64,14 +62,14 @@ extern void macstr2num(u8 *dst, u8 *src); extern u8 convert_ip_addr(u8 hch, u8 mch, u8 lch); u32 rtw_rates[] = {1000000, 2000000, 5500000, 11000000, - 6000000, 9000000, 12000000, 18000000, 24000000, 36000000, 48000000, 54000000 - }; + 6000000, 9000000, 12000000, 18000000, 24000000, 36000000, 48000000, 54000000}; static const char *const iw_operation_mode[] = { "Auto", "Ad-Hoc", "Managed", "Master", "Repeater", "Secondary", "Monitor" }; -static int hex2num_i(char c) { +static int hex2num_i(char c) +{ if (c >= '0' && c <= '9') return c - '0'; if (c >= 'a' && c <= 'f') @@ -81,7 +79,8 @@ static int hex2num_i(char c) { return -1; } -static int hex2byte_i(const char *hex) { +static int hex2byte_i(const char *hex) +{ int a, b; a = hex2num_i(*hex++); if (a < 0) @@ -98,7 +97,8 @@ static int hex2byte_i(const char *hex) { * @addr: Buffer for the MAC address (ETH_ALEN = 6 bytes) * Returns: 0 on success, -1 on failure (e.g., string not a MAC address) */ -static int hwaddr_aton_i(const char *txt, u8 *addr) { +static int hwaddr_aton_i(const char *txt, u8 *addr) +{ int i; for (i = 0; i < 6; i++) { @@ -118,7 +118,8 @@ static int hwaddr_aton_i(const char *txt, u8 *addr) { return 0; } -static void indicate_wx_custom_event(_adapter *padapter, char *msg) { +static void indicate_wx_custom_event(_adapter *padapter, char *msg) +{ u8 *buff, *p; union iwreq_data wrqu; @@ -146,7 +147,8 @@ static void indicate_wx_custom_event(_adapter *padapter, char *msg) { } -static void request_wps_pbc_event(_adapter *padapter) { +static void request_wps_pbc_event(_adapter *padapter) +{ u8 *buff, *p; union iwreq_data wrqu; @@ -179,7 +181,8 @@ static void request_wps_pbc_event(_adapter *padapter) { } #ifdef CONFIG_SUPPORT_HW_WPS_PBC -void rtw_request_wps_pbc_event(_adapter *padapter) { +void rtw_request_wps_pbc_event(_adapter *padapter) +{ #ifdef RTK_DMP_PLATFORM #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12)) kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC); @@ -201,7 +204,8 @@ void rtw_request_wps_pbc_event(_adapter *padapter) { } #endif/* #ifdef CONFIG_SUPPORT_HW_WPS_PBC */ -void indicate_wx_scan_complete_event(_adapter *padapter) { +void indicate_wx_scan_complete_event(_adapter *padapter) +{ union iwreq_data wrqu; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -214,7 +218,8 @@ void indicate_wx_scan_complete_event(_adapter *padapter) { } -void rtw_indicate_wx_assoc_event(_adapter *padapter) { +void rtw_indicate_wx_assoc_event(_adapter *padapter) +{ union iwreq_data wrqu; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; @@ -236,7 +241,8 @@ void rtw_indicate_wx_assoc_event(_adapter *padapter) { #endif } -void rtw_indicate_wx_disassoc_event(_adapter *padapter) { +void rtw_indicate_wx_disassoc_event(_adapter *padapter) +{ union iwreq_data wrqu; _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); @@ -283,15 +289,16 @@ uint rtw_is_cckratesonly_included(u8 *rate) */ static int search_p2p_wfd_ie(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop) +{ #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &padapter->wdinfo; #ifdef CONFIG_WFD if (SCAN_RESULT_ALL == pwdinfo->wfd_info->scan_result_type) { } else if ((SCAN_RESULT_P2P_ONLY == pwdinfo->wfd_info->scan_result_type) || - (SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type)) + (SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type)) #endif /* CONFIG_WFD */ { if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { @@ -355,8 +362,9 @@ static int search_p2p_wfd_ie(_adapter *padapter, return _TRUE; } static inline char *iwe_stream_mac_addr_proess(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop, struct iw_event *iwe) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ /* AP MAC address */ iwe->cmd = SIOCGIWAP; iwe->u.ap_addr.sa_family = ARPHRD_ETHER; @@ -366,8 +374,9 @@ static inline char *iwe_stream_mac_addr_proess(_adapter *padapter, return start; } static inline char *iwe_stream_essid_proess(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop, struct iw_event *iwe) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ /* Add the ESSID */ iwe->cmd = SIOCGIWESSID; @@ -378,8 +387,9 @@ static inline char *iwe_stream_essid_proess(_adapter *padapter, } static inline char *iwe_stream_chan_process(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop, struct iw_event *iwe) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ if (pnetwork->network.Configuration.DSConfig < 1 /*|| pnetwork->network.Configuration.DSConfig>14*/) pnetwork->network.Configuration.DSConfig = 1; @@ -392,8 +402,9 @@ static inline char *iwe_stream_chan_process(_adapter *padapter, return start; } static inline char *iwe_stream_mode_process(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop, struct iw_event *iwe, u16 cap) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe, u16 cap) +{ /* Add mode */ if (cap & (WLAN_CAPABILITY_IBSS | WLAN_CAPABILITY_BSS)) { iwe->cmd = SIOCGIWMODE; @@ -407,8 +418,9 @@ static inline char *iwe_stream_mode_process(_adapter *padapter, return start; } static inline char *iwe_stream_encryption_process(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop, struct iw_event *iwe, u16 cap) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe, u16 cap) +{ /* Add encryption capability */ iwe->cmd = SIOCGIWENCODE; @@ -423,8 +435,9 @@ static inline char *iwe_stream_encryption_process(_adapter *padapter, } static inline char *iwe_stream_protocol_process(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop, struct iw_event *iwe) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ u16 ht_cap = _FALSE, vht_cap = _FALSE; u32 ht_ielen = 0, vht_ielen = 0; char *p; @@ -455,11 +468,11 @@ static inline char *iwe_stream_protocol_process(_adapter *padapter, snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bg"); } else { if (pnetwork->network.Configuration.DSConfig > 14) { -#ifdef CONFIG_80211AC_VHT + #ifdef CONFIG_80211AC_VHT if (vht_cap == _TRUE) snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11AC"); else -#endif + #endif { if (ht_cap == _TRUE) snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11an"); @@ -478,8 +491,9 @@ static inline char *iwe_stream_protocol_process(_adapter *padapter, } static inline char *iwe_stream_rate_process(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop, struct iw_event *iwe) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ u32 ht_ielen = 0, vht_ielen = 0; char *p; u16 max_rate = 0, rate, ht_cap = _FALSE, vht_cap = _FALSE; @@ -528,7 +542,7 @@ static inline char *iwe_stream_rate_process(_adapter *padapter, if (rate > max_rate) max_rate = rate; p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), - "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); + "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); i++; } #ifdef CONFIG_80211AC_VHT @@ -558,8 +572,9 @@ static inline char *iwe_stream_rate_process(_adapter *padapter, } static inline char *iwe_stream_wpa_wpa2_process(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop, struct iw_event *iwe) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ int buf_size = MAX_WPA_IE_LEN * 2; /* u8 pbuf[buf_size]={0}; */ u8 *pbuf = rtw_zmalloc(buf_size); @@ -576,8 +591,6 @@ static inline char *iwe_stream_wpa_wpa2_process(_adapter *padapter, /* parsing WPA/WPA2 IE */ if (pnetwork->network.Reserved[0] != 2) { /* Probe Request */ out_len = rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, rsn_ie, &rsn_len, wpa_ie, &wpa_len); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_scan: ssid=%s\n", pnetwork->network.Ssid.Ssid)); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_scan: wpa_len=%d rsn_len=%d\n", wpa_len, rsn_len)); if (wpa_len > 0) { @@ -628,8 +641,9 @@ static inline char *iwe_stream_wpa_wpa2_process(_adapter *padapter, } static inline char *iwe_stream_wps_process(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop, struct iw_event *iwe) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ /* parsing WPS IE */ uint cnt = 0, total_ielen; u8 *wpsie_ptr = NULL; @@ -659,8 +673,9 @@ static inline char *iwe_stream_wps_process(_adapter *padapter, } static inline char *iwe_stream_wapi_process(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop, struct iw_event *iwe) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ #ifdef CONFIG_WAPI_SUPPORT char *p; @@ -673,8 +688,6 @@ static inline char *iwe_stream_wapi_process(_adapter *padapter, u16 i; out_len_wapi = rtw_get_wapi_ie(pnetwork->network.IEs , pnetwork->network.IELength, wapi_ie, &wapi_len); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_scan: ssid=%s\n", pnetwork->network.Ssid.Ssid)); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_scan: wapi_len=%d\n", wapi_len)); RTW_INFO("rtw_wx_get_scan: %s ", pnetwork->network.Ssid.Ssid); RTW_INFO("rtw_wx_get_scan: ssid = %d ", wapi_len); @@ -703,8 +716,9 @@ static inline char *iwe_stream_wapi_process(_adapter *padapter, } static inline char *iwe_stream_rssi_process(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop, struct iw_event *iwe) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ u8 ss, sq; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -712,17 +726,17 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, iwe->cmd = IWEVQUAL; iwe->u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - | IW_QUAL_NOISE_UPDATED + | IW_QUAL_NOISE_UPDATED #else - | IW_QUAL_NOISE_INVALID + | IW_QUAL_NOISE_INVALID #endif #ifdef CONFIG_SIGNAL_DISPLAY_DBM - | IW_QUAL_DBM + | IW_QUAL_DBM #endif - ; + ; if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && - is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { + is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { ss = padapter->recvpriv.signal_strength; sq = padapter->recvpriv.signal_qual; } else { @@ -742,7 +756,7 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); - iwe->u.qual.level = (u8)odm_SignalScaleMapping(&pHal->odmpriv, ss); + iwe->u.qual.level = (u8)odm_signal_scale_mapping(&pHal->odmpriv, ss); } #endif #endif @@ -770,8 +784,9 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, } static inline char *iwe_stream_net_rsv_process(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop, struct iw_event *iwe) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ u8 buf[32] = {0}; u8 *p, *pos; int len; @@ -788,8 +803,9 @@ static inline char *iwe_stream_net_rsv_process(_adapter *padapter, #if 1 static char *translate_scan(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop) +{ struct iw_event iwe; u16 cap = 0; _rtw_memset(&iwe, 0, sizeof(iwe)); @@ -821,8 +837,9 @@ static char *translate_scan(_adapter *padapter, } #else static char *translate_scan(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop) { + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop) +{ struct iw_event iwe; u16 cap; u32 ht_ielen = 0, vht_ielen = 0; @@ -963,7 +980,7 @@ static char *translate_scan(_adapter *padapter, if (rate > max_rate) max_rate = rate; p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), - "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); + "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); i++; } @@ -996,8 +1013,6 @@ static char *translate_scan(_adapter *padapter, u8 *p; sint out_len = 0; out_len = rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, rsn_ie, &rsn_len, wpa_ie, &wpa_len); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_scan: ssid=%s\n", pnetwork->network.Ssid.Ssid)); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_scan: wpa_len=%d rsn_len=%d\n", wpa_len, rsn_len)); if (wpa_len > 0) { p = buf; @@ -1042,8 +1057,7 @@ static char *translate_scan(_adapter *padapter, } } - { - /* parsing WPS IE */ + { /* parsing WPS IE */ uint cnt = 0, total_ielen; u8 *wpsie_ptr = NULL; uint wps_ielen = 0; @@ -1083,8 +1097,6 @@ static char *translate_scan(_adapter *padapter, _rtw_memset(wapi_ie, 0, MAX_WAPI_IE_LEN); out_len_wapi = rtw_get_wapi_ie(pnetwork->network.IEs , pnetwork->network.IELength, wapi_ie, &wapi_len); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_scan: ssid=%s\n", pnetwork->network.Ssid.Ssid)); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_scan: wapi_len=%d\n", wapi_len)); RTW_INFO("rtw_wx_get_scan: %s ", pnetwork->network.Ssid.Ssid); RTW_INFO("rtw_wx_get_scan: ssid = %d ", wapi_len); @@ -1118,17 +1130,17 @@ static char *translate_scan(_adapter *padapter, iwe.cmd = IWEVQUAL; iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - | IW_QUAL_NOISE_UPDATED + | IW_QUAL_NOISE_UPDATED #else - | IW_QUAL_NOISE_INVALID + | IW_QUAL_NOISE_INVALID #endif #ifdef CONFIG_SIGNAL_DISPLAY_DBM - | IW_QUAL_DBM + | IW_QUAL_DBM #endif - ; + ; if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && - is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { + is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { ss = padapter->recvpriv.signal_strength; sq = padapter->recvpriv.signal_qual; } else { @@ -1148,7 +1160,7 @@ static char *translate_scan(_adapter *padapter, HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); - iwe.u.qual.level = (u8)odm_SignalScaleMapping(&pHal->odmpriv, ss); + iwe.u.qual.level = (u8)odm_signal_scale_mapping(&pHal->odmpriv, ss); } #endif #endif @@ -1192,7 +1204,8 @@ static char *translate_scan(_adapter *padapter, } #endif -static int wpa_set_auth_algs(struct net_device *dev, u32 value) { +static int wpa_set_auth_algs(struct net_device *dev, u32 value) +{ _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); int ret = 0; @@ -1236,7 +1249,8 @@ static int wpa_set_auth_algs(struct net_device *dev, u32 value) { } -static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) { +static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +{ int ret = 0; u32 wep_key_idx, wep_key_len, wep_total_len; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -1246,7 +1260,6 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, struct wifidirect_info *pwdinfo = &padapter->wdinfo; #endif /* CONFIG_P2P */ - _func_enter_; param->u.crypt.err = 0; param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; @@ -1257,12 +1270,12 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, } if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { if (param->u.crypt.idx >= WEP_KEYS #ifdef CONFIG_IEEE80211W - && param->u.crypt.idx > BIP_MAX_KEYID + && param->u.crypt.idx > BIP_MAX_KEYID #endif /* CONFIG_IEEE80211W */ ) { ret = -EINVAL; @@ -1279,7 +1292,6 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, } if (strcmp(param->u.crypt.alg, "WEP") == 0) { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("wpa_set_encryption, crypt.alg = WEP\n")); RTW_INFO("wpa_set_encryption, crypt.alg = WEP\n"); wep_key_idx = param->u.crypt.idx; @@ -1330,7 +1342,7 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, psta->ieee8021x_blocked = _FALSE; if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) || - (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) + (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; if (param->u.crypt.set_tx == 1) { /* pairwise key */ @@ -1342,7 +1354,6 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); padapter->securitypriv.busetkipkey = _FALSE; - /* _set_timer(&padapter->securitypriv.tkip_timer, 50); */ } /* DEBUG_ERR((" param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); */ @@ -1355,7 +1366,7 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, } else { /* group key */ if (strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) { _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, - (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); /* only TKIP group key need to install this */ if (param->u.crypt.key_len > 16) { _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); @@ -1375,7 +1386,7 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, /* printk("BIP key_len=%d , index=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.key_len, param->u.crypt.idx); */ /* save the IGTK key, length 16 bytes */ _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, - (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); /*printk("IGTK key below:\n"); for(no=0;no<16;no++) printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); @@ -1403,7 +1414,7 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, pbcmc_sta->ieee8021x_blocked = _FALSE; if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) || - (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) + (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; } } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { /* adhoc mode */ @@ -1470,12 +1481,12 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, exit: - _func_exit_; return ret; } -static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) { +static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) +{ u8 *buf = NULL, *pos = NULL; u32 left; int group_cipher = 0, pairwise_cipher = 0; @@ -1512,7 +1523,6 @@ static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) { pos = buf; if (ielen < RSN_HEADER_LEN) { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("Ie len too short %d\n", ielen)); ret = -1; goto exit; } @@ -1525,7 +1535,6 @@ static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) { pos += RSN_SELECTOR_LEN; left -= RSN_SELECTOR_LEN; } else if (left > 0) { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("Ie length mismatch, %u too much\n", left)); ret = -1; goto exit; } @@ -1595,8 +1604,7 @@ static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) { } _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); - { - /* set wps_ie */ + {/* set wps_ie */ u16 cnt = 0; u8 eid, wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; @@ -1628,15 +1636,12 @@ static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) { /* TKIP and AES disallow multicast packets until installing group key */ if (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_ - || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_ - || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) + || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_ + || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) /* WPS open need to enable multicast * || check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) */ rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr); - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, - ("rtw_set_wpa_ie: pairwise_cipher=0x%08x padapter->securitypriv.ndisencryptstatus=%d padapter->securitypriv.ndisauthtype=%d\n", - pairwise_cipher, padapter->securitypriv.ndisencryptstatus, padapter->securitypriv.ndisauthtype)); exit: @@ -1647,8 +1652,9 @@ static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) { } static int rtw_wx_get_name(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); u16 cap; u32 ht_ielen = 0; @@ -1658,9 +1664,7 @@ static int rtw_wx_get_name(struct net_device *dev, WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; NDIS_802_11_RATES_EX *prates = NULL; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("cmd_code=%x\n", info->cmd)); - _func_enter_; if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) { /* parsing HT_CAP_IE */ @@ -1711,14 +1715,14 @@ static int rtw_wx_get_name(struct net_device *dev, snprintf(wrqu->name, IFNAMSIZ, "unassociated"); } - _func_exit_; return 0; } static int rtw_wx_set_freq(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); @@ -1726,13 +1730,11 @@ static int rtw_wx_set_freq(struct net_device *dev, struct wlan_network *cur_network = &(pmlmepriv->cur_network); int exp = 1, freq = 0, div = 0; - _func_enter_; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+rtw_wx_set_freq\n")); if (wrqu->freq.m <= 1000) { if (wrqu->freq.flags == IW_FREQ_AUTO) { - if (rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, wrqu->freq.m) > 0) { + if (rtw_chset_search_ch(adapter_to_chset(padapter), wrqu->freq.m) > 0) { padapter->mlmeextpriv.cur_channel = wrqu->freq.m; RTW_INFO("%s: channel is auto, set to channel %d\n", __func__, wrqu->freq.m); } else { @@ -1770,17 +1772,18 @@ static int rtw_wx_set_freq(struct net_device *dev, padapter->mlmeextpriv.cur_channel = rtw_freq2ch(freq); RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel); } - + rtw_ps_deny(padapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */ set_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - - _func_exit_; + rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); return 0; } static int rtw_wx_get_freq(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; @@ -1801,13 +1804,13 @@ static int rtw_wx_get_freq(struct net_device *dev, } static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, - union iwreq_data *wrqu, char *b) { + union iwreq_data *wrqu, char *b) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); NDIS_802_11_NETWORK_INFRASTRUCTURE networkType ; int ret = 0; - _func_enter_; if (_FAIL == rtw_pwr_wakeup(padapter)) { ret = -EPERM; @@ -1822,14 +1825,26 @@ static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, /* initial default type */ dev->type = ARPHRD_ETHER; + if (wrqu->mode == IW_MODE_MONITOR) { + rtw_ps_deny(padapter, PS_DENY_MONITOR_MODE); + LeaveAllPowerSaveMode(padapter); + } else { + rtw_ps_deny_cancel(padapter, PS_DENY_MONITOR_MODE); + } + switch (wrqu->mode) { case IW_MODE_MONITOR: networkType = Ndis802_11Monitor; #if 0 dev->type = ARPHRD_IEEE80211; /* IEEE 802.11 : 801 */ #endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) dev->type = ARPHRD_IEEE80211_RADIOTAP; /* IEEE 802.11 + radiotap header : 803 */ RTW_INFO("set_mode = IW_MODE_MONITOR\n"); +#else + RTW_INFO("kernel version < 2.6.24 not support IW_MODE_MONITOR\n"); +#endif break; case IW_MODE_AUTO: @@ -1852,7 +1867,6 @@ static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, default: ret = -EINVAL;; - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("\n Mode: %s is not supported\n", iw_operation_mode[wrqu->mode])); goto exit; } @@ -1881,25 +1895,23 @@ static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, exit: - _func_exit_; return ret; } static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a, - union iwreq_data *wrqu, char *b) { + union iwreq_data *wrqu, char *b) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, (" rtw_wx_get_mode\n")); - _func_enter_; if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) wrqu->mode = IW_MODE_INFRA; else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || - (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) wrqu->mode = IW_MODE_ADHOC; else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) @@ -1909,7 +1921,6 @@ static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a, else wrqu->mode = IW_MODE_AUTO; - _func_exit_; return 0; @@ -1917,8 +1928,9 @@ static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a, static int rtw_wx_set_pmkid(struct net_device *dev, - struct iw_request_info *a, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); u8 j, blInserted = _FALSE; int intReturn = _FALSE; @@ -1967,7 +1979,7 @@ static int rtw_wx_set_pmkid(struct net_device *dev, if (!blInserted) { /* Find a new entry */ RTW_INFO("[rtw_wx_set_pmkid] Use the new entry index = %d for this PMKID.\n", - psecuritypriv->PMKIDIndex); + psecuritypriv->PMKIDIndex); _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, strIssueBssid, ETH_ALEN); _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pPMK->pmkid, IW_PMKID_LEN); @@ -1998,8 +2010,9 @@ static int rtw_wx_set_pmkid(struct net_device *dev, } static int rtw_wx_get_sens(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ #ifdef CONFIG_PLATFORM_ROCKCHIPS _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -2024,18 +2037,18 @@ static int rtw_wx_get_sens(struct net_device *dev, } static int rtw_wx_get_range(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ struct iw_range *range = (struct iw_range *)extra; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; u16 val; int i; - _func_enter_; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_range. cmd_code=%x\n", info->cmd)); wrqu->data.length = sizeof(*range); _rtw_memset(range, 0, sizeof(*range)); @@ -2076,8 +2089,8 @@ static int rtw_wx_get_range(struct net_device *dev, */ range->max_qual.qual = 100; #ifdef CONFIG_SIGNAL_DISPLAY_DBM - range->max_qual.level = (u8) - 100; - range->max_qual.noise = (u8) - 100; + range->max_qual.level = (u8)-100; + range->max_qual.noise = (u8)-100; range->max_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */ range->max_qual.updated |= IW_QUAL_DBM; #else /* !CONFIG_SIGNAL_DISPLAY_DBM */ @@ -2099,7 +2112,7 @@ static int rtw_wx_get_range(struct net_device *dev, range->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */ #ifdef CONFIG_SIGNAL_DISPLAY_DBM /* TODO: Find real 'good' to 'bad' threshold value for RSSI */ - range->avg_qual.level = (u8) - 70; + range->avg_qual.level = (u8)-70; range->avg_qual.noise = 0; range->avg_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */ range->avg_qual.updated |= IW_QUAL_DBM; @@ -2131,12 +2144,12 @@ static int rtw_wx_get_range(struct net_device *dev, * range->min_r_time; Minimal retry lifetime * range->max_r_time; Maximal retry lifetime */ - for (i = 0, val = 0; i < MAX_CHANNEL_NUM; i++) { + for (i = 0, val = 0; i < rfctl->max_chan_nums; i++) { /* Include only legal frequencies for some countries */ - if (pmlmeext->channel_set[i].ChannelNum != 0) { - range->freq[val].i = pmlmeext->channel_set[i].ChannelNum; - range->freq[val].m = rtw_ch2freq(pmlmeext->channel_set[i].ChannelNum) * 100000; + if (rfctl->channel_set[i].ChannelNum != 0) { + range->freq[val].i = rfctl->channel_set[i].ChannelNum; + range->freq[val].m = rtw_ch2freq(rfctl->channel_set[i].ChannelNum) * 100000; range->freq[val].e = 1; val++; } @@ -2166,16 +2179,15 @@ static int rtw_wx_get_range(struct net_device *dev, #if WIRELESS_EXT > 17 range->enc_capa = IW_ENC_CAPA_WPA | IW_ENC_CAPA_WPA2 | - IW_ENC_CAPA_CIPHER_TKIP | IW_ENC_CAPA_CIPHER_CCMP; + IW_ENC_CAPA_CIPHER_TKIP | IW_ENC_CAPA_CIPHER_CCMP; #endif #ifdef IW_SCAN_CAPA_ESSID /* WIRELESS_EXT > 21 */ range->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE | IW_SCAN_CAPA_BSSID | - IW_SCAN_CAPA_CHANNEL | IW_SCAN_CAPA_MODE | IW_SCAN_CAPA_RATE; + IW_SCAN_CAPA_CHANNEL | IW_SCAN_CAPA_MODE | IW_SCAN_CAPA_RATE; #endif - _func_exit_; return 0; @@ -2187,9 +2199,10 @@ static int rtw_wx_get_range(struct net_device *dev, * s3. set_802_11_encryption_mode() * s4. rtw_set_802_11_bssid() */ static int rtw_wx_set_wap(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *awrq, - char *extra) { + struct iw_request_info *info, + union iwreq_data *awrq, + char *extra) +{ _irqL irqL; uint ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -2201,7 +2214,6 @@ static int rtw_wx_set_wap(struct net_device *dev, struct wlan_network *pnetwork = NULL; NDIS_802_11_AUTHENTICATION_MODE authmode; - _func_enter_; /* #ifdef CONFIG_CONCURRENT_MODE if(padapter->adapter_type > PRIMARY_IFACE) @@ -2225,18 +2237,18 @@ static int rtw_wx_set_wap(struct net_device *dev, rtw_ps_deny(padapter, PS_DENY_JOIN); if (_FAIL == rtw_pwr_wakeup(padapter)) { ret = -1; - goto exit; + goto cancel_ps_deny; } if (!padapter->bup) { ret = -1; - goto exit; + goto cancel_ps_deny; } if (temp->sa_family != ARPHRD_ETHER) { ret = -EINVAL; - goto exit; + goto cancel_ps_deny; } authmode = padapter->securitypriv.ndisauthtype; @@ -2249,14 +2261,14 @@ static int rtw_wx_set_wap(struct net_device *dev, if ((rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) == _TRUE) { #if 0 ret = -EINVAL; - goto exit; + goto cancel_ps_deny; if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) { rtw_set_802_11_bssid(padapter, temp->sa_data); - goto exit; + goto cancel_ps_deny; } else { ret = -EINVAL; - goto exit; + goto cancel_ps_deny; } #endif @@ -2275,7 +2287,7 @@ static int rtw_wx_set_wap(struct net_device *dev, if (!rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode)) { ret = -1; _exit_critical_bh(&queue->lock, &irqL); - goto exit; + goto cancel_ps_deny; } break; @@ -2288,21 +2300,20 @@ static int rtw_wx_set_wap(struct net_device *dev, /* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */ if (rtw_set_802_11_bssid(padapter, temp->sa_data) == _FALSE) { ret = -1; - goto exit; + goto cancel_ps_deny; } -exit: - +cancel_ps_deny: rtw_ps_deny_cancel(padapter, PS_DENY_JOIN); - _func_exit_; - +exit: return ret; } static int rtw_wx_get_wap(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -2312,27 +2323,25 @@ static int rtw_wx_get_wap(struct net_device *dev, _rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_wap\n")); - _func_enter_; if (((check_fwstate(pmlmepriv, _FW_LINKED)) == _TRUE) || - ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) || - ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) == _TRUE)) + ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) || + ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) == _TRUE)) _rtw_memcpy(wrqu->ap_addr.sa_data, pcur_bss->MacAddress, ETH_ALEN); else _rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN); - _func_exit_; return 0; } static int rtw_wx_set_mlme(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ #if 0 /* SIOCSIWMLME data */ struct iw_mlme { @@ -2379,7 +2388,8 @@ static int rtw_wx_set_mlme(struct net_device *dev, } static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, - union iwreq_data *wrqu, char *extra) { + union iwreq_data *wrqu, char *extra) +{ u8 _status = _FALSE; int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -2389,16 +2399,14 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif /* CONFIG_P2P */ - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_set_scan\n")); - _func_enter_; #ifdef DBG_IOCTL RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__); #endif #ifdef CONFIG_MP_INCLUDED - if (rtw_mi_mp_mode_check(padapter)) { + if (rtw_mp_mode_check(padapter)) { RTW_INFO("MP mode block Scan request\n"); ret = -EPERM; goto exit; @@ -2412,12 +2420,12 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, rtw_ps_deny(padapter, PS_DENY_SCAN); if (_FAIL == rtw_pwr_wakeup(padapter)) { ret = -1; - goto exit; + goto cancel_ps_deny; } if (!rtw_is_adapter_up(padapter)) { ret = -1; - goto exit; + goto cancel_ps_deny; } #ifndef CONFIG_DOSCAN_IN_BUSYTRAFFIC @@ -2426,27 +2434,27 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, /* modify by thomas 2011-02-22. */ if (rtw_mi_busy_traffic_check(padapter, _FALSE)) { indicate_wx_scan_complete_event(padapter); - goto exit; + goto cancel_ps_deny; } #endif if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { RTW_INFO("AP mode process WPS\n"); indicate_wx_scan_complete_event(padapter); - goto exit; + goto cancel_ps_deny; } if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) { indicate_wx_scan_complete_event(padapter); - goto exit; + goto cancel_ps_deny; } #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_buddy_check_fwstate(padapter, - _FW_UNDER_SURVEY | _FW_UNDER_LINKING | WIFI_UNDER_WPS)) { + _FW_UNDER_SURVEY | _FW_UNDER_LINKING | WIFI_UNDER_WPS)) { indicate_wx_scan_complete_event(padapter); - goto exit; + goto cancel_ps_deny; } #endif @@ -2482,7 +2490,7 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, #endif if (wrqu->data.length >= WEXT_CSCAN_HEADER_SIZE - && _rtw_memcmp(extra, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE + && _rtw_memcmp(extra, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE ) { int len = wrqu->data.length - WEXT_CSCAN_HEADER_SIZE; char *pos = extra + WEXT_CSCAN_HEADER_SIZE; @@ -2569,21 +2577,20 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, if (_status == _FALSE) ret = -1; -exit: - +cancel_ps_deny: rtw_ps_deny_cancel(padapter, PS_DENY_SCAN); +exit: #ifdef DBG_IOCTL RTW_INFO("DBG_IOCTL %s:%d return %d\n", __FUNCTION__, __LINE__, ret); #endif - _func_exit_; - return ret; } static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, - union iwreq_data *wrqu, char *extra) { + union iwreq_data *wrqu, char *extra) +{ _irqL irqL; _list *plist, *phead; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -2600,10 +2607,7 @@ static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &padapter->wdinfo; #endif /* CONFIG_P2P */ - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_scan\n")); - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, (" Start of Query SIOCGIWSCAN .\n")); - _func_enter_; #ifdef DBG_IOCTL RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__); @@ -2630,18 +2634,18 @@ static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, #if 1 /* Wireless Extension use EAGAIN to try */ wait_status = _FW_UNDER_SURVEY #ifndef CONFIG_ANDROID - | _FW_UNDER_LINKING + | _FW_UNDER_LINKING #endif - ; + ; while (check_fwstate(pmlmepriv, wait_status) == _TRUE) return -EAGAIN; #else wait_status = _FW_UNDER_SURVEY #ifndef CONFIG_ANDROID - | _FW_UNDER_LINKING + | _FW_UNDER_LINKING #endif - ; + ; while (check_fwstate(pmlmepriv, wait_status) == _TRUE) { rtw_msleep_os(30); @@ -2667,9 +2671,9 @@ static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); /* report network only if the current channel set contains the channel to which this network belongs */ - if (rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 - && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE - && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) + if (rtw_chset_search_ch(adapter_to_chset(padapter), pnetwork->network.Configuration.DSConfig) >= 0 + && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE + && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) ) ev = translate_scan(padapter, a, pnetwork, ev, stop); @@ -2684,7 +2688,6 @@ static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, exit: - _func_exit_; #ifdef DBG_IOCTL RTW_INFO("DBG_IOCTL %s:%d return %d\n", __FUNCTION__, __LINE__, ret); @@ -2700,8 +2703,9 @@ static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, * s3. set_802_11_encryption_mode() * s4. rtw_set_802_11_ssid() */ static int rtw_wx_set_essid(struct net_device *dev, - struct iw_request_info *a, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ _irqL irqL; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -2715,7 +2719,6 @@ static int rtw_wx_set_essid(struct net_device *dev, uint ret = 0, len; - _func_enter_; #ifdef DBG_IOCTL RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__); @@ -2735,30 +2738,28 @@ static int rtw_wx_set_essid(struct net_device *dev, } - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, - ("+rtw_wx_set_essid: fw_state=0x%08x\n", get_fwstate(pmlmepriv))); rtw_ps_deny(padapter, PS_DENY_JOIN); if (_FAIL == rtw_pwr_wakeup(padapter)) { ret = -1; - goto exit; + goto cancel_ps_deny; } if (!padapter->bup) { ret = -1; - goto exit; + goto cancel_ps_deny; } if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { ret = -1; - goto exit; + goto cancel_ps_deny; } #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_SURVEY | _FW_UNDER_LINKING)) { RTW_INFO("set ssid, but buddy_intf is under scanning or linking\n"); ret = -EINVAL; - goto exit; + goto cancel_ps_deny; } #endif authmode = padapter->securitypriv.ndisauthtype; @@ -2786,7 +2787,6 @@ static int rtw_wx_set_essid(struct net_device *dev, _rtw_memcpy(ndis_ssid.Ssid, extra, len); src_ssid = ndis_ssid.Ssid; - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ("rtw_wx_set_essid: ssid=[%s]\n", src_ssid)); _enter_critical_bh(&queue->lock, &irqL); phead = get_list_head(queue); pmlmepriv->pscanned = get_next(phead); @@ -2797,15 +2797,12 @@ static int rtw_wx_set_essid(struct net_device *dev, if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) { rtw_set_802_11_ssid(padapter, &ndis_ssid); - goto exit; + goto cancel_ps_deny; } else { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ("rtw_wx_set_ssid(): scanned_queue is empty\n")); ret = -EINVAL; - goto exit; + goto cancel_ps_deny; } #endif - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_warning_, - ("rtw_wx_set_essid: scan_q is empty, set ssid to check if scanning again!\n")); break; } @@ -2816,14 +2813,9 @@ static int rtw_wx_set_essid(struct net_device *dev, dst_ssid = pnetwork->network.Ssid.Ssid; - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, - ("rtw_wx_set_essid: dst_ssid=%s\n", - pnetwork->network.Ssid.Ssid)); if ((_rtw_memcmp(dst_ssid, src_ssid, ndis_ssid.SsidLength) == _TRUE) && - (pnetwork->network.Ssid.SsidLength == ndis_ssid.SsidLength)) { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, - ("rtw_wx_set_essid: find match, set infra mode\n")); + (pnetwork->network.Ssid.SsidLength == ndis_ssid.SsidLength)) { if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) { if (pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode) @@ -2833,52 +2825,48 @@ static int rtw_wx_set_essid(struct net_device *dev, if (rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode) == _FALSE) { ret = -1; _exit_critical_bh(&queue->lock, &irqL); - goto exit; + goto cancel_ps_deny; } break; } } _exit_critical_bh(&queue->lock, &irqL); - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, - ("set ssid: set_802_11_auth. mode=%d\n", authmode)); rtw_set_802_11_authentication_mode(padapter, authmode); /* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */ if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) { ret = -1; - goto exit; + goto cancel_ps_deny; } } -exit: - +cancel_ps_deny: rtw_ps_deny_cancel(padapter, PS_DENY_JOIN); +exit: RTW_INFO("<=%s, ret %d\n", __FUNCTION__, ret); #ifdef DBG_IOCTL RTW_INFO("DBG_IOCTL %s:%d return %d\n", __FUNCTION__, __LINE__, ret); #endif - _func_exit_; return ret; } static int rtw_wx_get_essid(struct net_device *dev, - struct iw_request_info *a, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ u32 len, ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_wx_get_essid\n")); - _func_enter_; if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || - (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { len = pcur_bss->Ssid.SsidLength; wrqu->essid.length = len; @@ -2893,15 +2881,15 @@ static int rtw_wx_get_essid(struct net_device *dev, exit: - _func_exit_; return ret; } static int rtw_wx_set_rate(struct net_device *dev, - struct iw_request_info *a, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ int i, ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); u8 datarates[NumRates]; @@ -2910,10 +2898,7 @@ static int rtw_wx_set_rate(struct net_device *dev, u32 ratevalue = 0; u8 mpdatarate[NumRates] = {11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0xff}; - _func_enter_; - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, (" rtw_wx_set_rate\n")); - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ("target_rate = %d, fixed = %d\n", target_rate, fixed)); if (target_rate == -1) { ratevalue = 11; @@ -2973,22 +2958,20 @@ static int rtw_wx_set_rate(struct net_device *dev, } else datarates[i] = 0xff; - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ("datarate_inx=%d\n", datarates[i])); } if (rtw_setdatarate_cmd(padapter, datarates) != _SUCCESS) { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("rtw_wx_set_rate Fail!!!\n")); ret = -1; } - _func_exit_; return ret; } static int rtw_wx_get_rate(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ u16 max_rate = 0; max_rate = rtw_get_cur_max_rate((_adapter *)rtw_netdev_priv(dev)); @@ -3003,17 +2986,17 @@ static int rtw_wx_get_rate(struct net_device *dev, } static int rtw_wx_set_rts(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - _func_enter_; if (wrqu->rts.disabled) padapter->registrypriv.rts_thresh = 2347; else { if (wrqu->rts.value < 0 || - wrqu->rts.value > 2347) + wrqu->rts.value > 2347) return -EINVAL; padapter->registrypriv.rts_thresh = wrqu->rts.value; @@ -3021,18 +3004,17 @@ static int rtw_wx_set_rts(struct net_device *dev, RTW_INFO("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh); - _func_exit_; return 0; } static int rtw_wx_get_rts(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - _func_enter_; RTW_INFO("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh); @@ -3040,23 +3022,22 @@ static int rtw_wx_get_rts(struct net_device *dev, wrqu->rts.fixed = 0; /* no auto select */ /* wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD); */ - _func_exit_; return 0; } static int rtw_wx_set_frag(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - _func_enter_; if (wrqu->frag.disabled) padapter->xmitpriv.frag_len = MAX_FRAG_THRESHOLD; else { if (wrqu->frag.value < MIN_FRAG_THRESHOLD || - wrqu->frag.value > MAX_FRAG_THRESHOLD) + wrqu->frag.value > MAX_FRAG_THRESHOLD) return -EINVAL; padapter->xmitpriv.frag_len = wrqu->frag.value & ~0x1; @@ -3064,18 +3045,17 @@ static int rtw_wx_set_frag(struct net_device *dev, RTW_INFO("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len); - _func_exit_; return 0; } static int rtw_wx_get_frag(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - _func_enter_; RTW_INFO("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len); @@ -3083,14 +3063,14 @@ static int rtw_wx_get_frag(struct net_device *dev, wrqu->frag.fixed = 0; /* no auto select */ /* wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD); */ - _func_exit_; return 0; } static int rtw_wx_get_retry(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ /* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */ @@ -3103,31 +3083,32 @@ static int rtw_wx_get_retry(struct net_device *dev, } #if 0 -#define IW_ENCODE_INDEX 0x00FF /* Token index (if needed) */ -#define IW_ENCODE_FLAGS 0xFF00 /* Flags defined below */ -#define IW_ENCODE_MODE 0xF000 /* Modes defined below */ -#define IW_ENCODE_DISABLED 0x8000 /* Encoding disabled */ -#define IW_ENCODE_ENABLED 0x0000 /* Encoding enabled */ -#define IW_ENCODE_RESTRICTED 0x4000 /* Refuse non-encoded packets */ -#define IW_ENCODE_OPEN 0x2000 /* Accept non-encoded packets */ -#define IW_ENCODE_NOKEY 0x0800 /* Key is write only, so not present */ -#define IW_ENCODE_TEMP 0x0400 /* Temporary key */ -/* -iwconfig wlan0 key on->flags = 0x6001->maybe it means auto -iwconfig wlan0 key off->flags = 0x8800 -iwconfig wlan0 key open->flags = 0x2800 -iwconfig wlan0 key open 1234567890->flags = 0x2000 -iwconfig wlan0 key restricted->flags = 0x4800 -iwconfig wlan0 key open [3] 1234567890->flags = 0x2003 -iwconfig wlan0 key restricted [2] 1234567890->flags = 0x4002 -iwconfig wlan0 key open [3] -> flags = 0x2803 -iwconfig wlan0 key restricted [2] -> flags = 0x4802 -*/ + #define IW_ENCODE_INDEX 0x00FF /* Token index (if needed) */ + #define IW_ENCODE_FLAGS 0xFF00 /* Flags defined below */ + #define IW_ENCODE_MODE 0xF000 /* Modes defined below */ + #define IW_ENCODE_DISABLED 0x8000 /* Encoding disabled */ + #define IW_ENCODE_ENABLED 0x0000 /* Encoding enabled */ + #define IW_ENCODE_RESTRICTED 0x4000 /* Refuse non-encoded packets */ + #define IW_ENCODE_OPEN 0x2000 /* Accept non-encoded packets */ + #define IW_ENCODE_NOKEY 0x0800 /* Key is write only, so not present */ + #define IW_ENCODE_TEMP 0x0400 /* Temporary key */ + /* + iwconfig wlan0 key on->flags = 0x6001->maybe it means auto + iwconfig wlan0 key off->flags = 0x8800 + iwconfig wlan0 key open->flags = 0x2800 + iwconfig wlan0 key open 1234567890->flags = 0x2000 + iwconfig wlan0 key restricted->flags = 0x4800 + iwconfig wlan0 key open [3] 1234567890->flags = 0x2003 + iwconfig wlan0 key restricted [2] 1234567890->flags = 0x4002 + iwconfig wlan0 key open [3] -> flags = 0x2803 + iwconfig wlan0 key restricted [2] -> flags = 0x4802 + */ #endif static int rtw_wx_set_enc(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *keybuf) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *keybuf) +{ u32 key, ret = 0; u32 keyindex_provided; NDIS_802_11_WEP wep; @@ -3142,7 +3123,6 @@ static int rtw_wx_set_enc(struct net_device *dev, key = erq->flags & IW_ENCODE_INDEX; - _func_enter_; if (erq->flags & IW_ENCODE_DISABLED) { RTW_INFO("EncryptionDisabled\n"); @@ -3250,21 +3230,20 @@ static int rtw_wx_set_enc(struct net_device *dev, exit: - _func_exit_; return ret; } static int rtw_wx_get_enc(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *keybuf) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *keybuf) +{ uint key, ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct iw_point *erq = &(wrqu->encoding); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - _func_enter_; if (check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) { if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE) { @@ -3336,15 +3315,15 @@ static int rtw_wx_get_enc(struct net_device *dev, } - _func_exit_; return ret; } static int rtw_wx_get_power(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ /* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */ wrqu->power.value = 0; @@ -3356,8 +3335,9 @@ static int rtw_wx_get_power(struct net_device *dev, } static int rtw_wx_set_gen_ie(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -3367,10 +3347,11 @@ static int rtw_wx_set_gen_ie(struct net_device *dev, } static int rtw_wx_set_auth(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_param *param = (struct iw_param *) & (wrqu->param); + struct iw_param *param = (struct iw_param *)&(wrqu->param); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct security_priv *psecuritypriv = &padapter->securitypriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; @@ -3465,7 +3446,7 @@ static int rtw_wx_set_auth(struct net_device *dev, */ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { LeaveAllPowerSaveMode(padapter); - rtw_disassoc_cmd(padapter, 500, _FALSE); + rtw_disassoc_cmd(padapter, 500, RTW_CMDF_DIRECTLY); RTW_INFO("%s...call rtw_indicate_disconnect\n ", __FUNCTION__); rtw_indicate_disconnect(padapter, 0, _FALSE); rtw_free_assoc_resources(padapter, 1); @@ -3513,8 +3494,9 @@ static int rtw_wx_set_auth(struct net_device *dev, } static int rtw_wx_set_enc_ext(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ char *alg_name; u32 param_len; struct ieee_param *param = NULL; @@ -3576,11 +3558,11 @@ static int rtw_wx_set_enc_ext(struct net_device *dev, * just not checking GROUP key setting */ if ((pext->alg != IW_ENCODE_ALG_WEP) && - ((pext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) + ((pext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) #ifdef CONFIG_IEEE80211W - || (pext->ext_flags & IW_ENCODE_ALG_AES_CMAC) + || (pext->ext_flags & IW_ENCODE_ALG_AES_CMAC) #endif /* CONFIG_IEEE80211W */ - )) + )) param->u.crypt.set_tx = 0; param->u.crypt.idx = (pencoding->flags & 0x00FF) - 1 ; @@ -3618,8 +3600,9 @@ static int rtw_wx_set_enc_ext(struct net_device *dev, static int rtw_wx_get_nick(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ /* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */ /* struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); */ /* struct security_priv *psecuritypriv = &padapter->securitypriv; */ @@ -3627,7 +3610,7 @@ static int rtw_wx_get_nick(struct net_device *dev, if (extra) { wrqu->data.length = 14; wrqu->data.flags = 1; - _rtw_memcpy(extra, "rtl8822bu", 14); + _rtw_memcpy(extra, "", 14); } /* rtw_signal_process(pid, SIGUSR1); */ /* for test */ @@ -3682,8 +3665,9 @@ static int rtw_wx_get_nick(struct net_device *dev, } static int rtw_wx_read32(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ PADAPTER padapter; struct iw_point *p; u16 len; @@ -3727,6 +3711,21 @@ static int rtw_wx_read32(struct net_device *dev, data32 = rtw_read32(padapter, addr); sprintf(extra, "0x%08X", data32); break; + + #if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS) + case 11: + data32 = rtw_sd_iread8(padapter, addr); + sprintf(extra, "0x%02X", data32); + break; + case 12: + data32 = rtw_sd_iread16(padapter, addr); + sprintf(extra, "0x%04X", data32); + break; + case 14: + data32 = rtw_sd_iread32(padapter, addr); + sprintf(extra, "0x%08X", data32); + break; + #endif default: RTW_INFO("%s: usage> read [bytes],[address(hex)]\n", __func__); ret = -EINVAL; @@ -3741,8 +3740,9 @@ static int rtw_wx_read32(struct net_device *dev, } static int rtw_wx_write32(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); u32 addr; @@ -3777,8 +3777,9 @@ static int rtw_wx_write32(struct net_device *dev, } static int rtw_wx_read_rf(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); u32 path, addr, data32; @@ -3798,8 +3799,9 @@ static int rtw_wx_read_rf(struct net_device *dev, } static int rtw_wx_write_rf(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); u32 path, addr, data32; @@ -3814,12 +3816,14 @@ static int rtw_wx_write_rf(struct net_device *dev, } static int rtw_wx_priv_null(struct net_device *dev, struct iw_request_info *a, - union iwreq_data *wrqu, char *b) { + union iwreq_data *wrqu, char *b) +{ return -1; } static int dummy(struct net_device *dev, struct iw_request_info *a, - union iwreq_data *wrqu, char *b) { + union iwreq_data *wrqu, char *b) +{ /* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */ /* struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); */ @@ -3830,8 +3834,9 @@ static int dummy(struct net_device *dev, struct iw_request_info *a, } static int rtw_wx_set_channel_plan(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; u8 channel_plan_req = (u8)(*((int *)wrqu)); @@ -3843,22 +3848,21 @@ static int rtw_wx_set_channel_plan(struct net_device *dev, } static int rtw_wx_set_mtk_wps_probe_ie(struct net_device *dev, - struct iw_request_info *a, - union iwreq_data *wrqu, char *b) { + struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ #ifdef CONFIG_PLATFORM_MT53XX _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, - ("WLAN IOCTL: cmd_code=%x, fwstate=0x%x\n", - a->cmd, get_fwstate(pmlmepriv))); #endif return 0; } static int rtw_wx_get_sensitivity(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *buf) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *buf) +{ #ifdef CONFIG_PLATFORM_MT53XX _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -3871,8 +3875,9 @@ static int rtw_wx_get_sensitivity(struct net_device *dev, } static int rtw_wx_set_mtk_wps_ie(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ #ifdef CONFIG_PLATFORM_MT53XX _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -3891,7 +3896,8 @@ typedef int (*iw_handler)(struct net_device *dev, struct iw_request_info *info, * pointer to memory allocated in user space. */ static int rtw_drvext_hdl(struct net_device *dev, struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + union iwreq_data *wrqu, char *extra) +{ #if 0 struct iw_point { @@ -3939,20 +3945,16 @@ static int rtw_drvext_hdl(struct net_device *dev, struct iw_request_info *info, /* */ poidparam = (struct drvext_oidparam *)pparmbuf; - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ("drvext set oid subcode [%d], len[%d], InformationBufferLength[%d]\r\n", - poidparam->subcode, poidparam->len, len)); /* check subcode */ if (poidparam->subcode >= MAX_DRVEXT_HANDLERS) { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("no matching drvext handlers\r\n")); ret = -EINVAL; goto _rtw_drvext_hdl_exit; } if (poidparam->subcode >= MAX_DRVEXT_OID_SUBCODES) { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("no matching drvext subcodes\r\n")); ret = -EINVAL; goto _rtw_drvext_hdl_exit; } @@ -3961,8 +3963,6 @@ static int rtw_drvext_hdl(struct net_device *dev, struct iw_request_info *info, phandler = drvextoidhandlers + poidparam->subcode; if (poidparam->len != phandler->parmsize) { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("no matching drvext param size %d vs %d\r\n", - poidparam->len , phandler->parmsize)); ret = -EINVAL; goto _rtw_drvext_hdl_exit; } @@ -3992,7 +3992,8 @@ static int rtw_drvext_hdl(struct net_device *dev, struct iw_request_info *info, } -static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len) { +static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len) +{ pRW_Reg RegRWStruct; struct rf_reg_param *prfreg; u8 path; @@ -4087,9 +4088,10 @@ static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len) { } } - +#ifdef MP_IOCTL_HDL static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + union iwreq_data *wrqu, char *extra) +{ int ret = 0; u32 BytesRead, BytesWritten, BytesNeeded; struct oid_par_priv oid_par; @@ -4125,12 +4127,8 @@ static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info } poidparam = (struct mp_ioctl_param *)pparmbuf; - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, - ("rtw_mp_ioctl_hdl: subcode [%d], len[%d], buffer_len[%d]\r\n", - poidparam->subcode, poidparam->len, len)); if (poidparam->subcode >= MAX_MP_IOCTL_SUBCODE) { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("no matching drvext subcodes\r\n")); ret = -EINVAL; goto _rtw_mp_ioctl_hdl_exit; } @@ -4141,9 +4139,6 @@ static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info phandler = mp_ioctl_hdl + poidparam->subcode; if ((phandler->paramsize != 0) && (poidparam->len < phandler->paramsize)) { - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, - ("no matching drvext param size %d vs %d\r\n", - poidparam->len, phandler->paramsize)); ret = -EINVAL; goto _rtw_mp_ioctl_hdl_exit; } @@ -4173,7 +4168,7 @@ static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info /* todo:check status, BytesNeeded, etc. */ } else { RTW_INFO("rtw_mp_ioctl_hdl(): err!, subcode=%d, oid=%d, handler=%p\n", - poidparam->subcode, phandler->oid, phandler->handler); + poidparam->subcode, phandler->oid, phandler->handler); ret = -EFAULT; goto _rtw_mp_ioctl_hdl_exit; } @@ -4202,10 +4197,11 @@ static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info return ret; } - +#endif static int rtw_get_ap_info(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int bssid_match, ret = 0; u32 cnt = 0, wpa_ielen; _irqL irqL; @@ -4303,8 +4299,9 @@ static int rtw_get_ap_info(struct net_device *dev, } static int rtw_set_pid(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = rtw_netdev_priv(dev); @@ -4333,8 +4330,9 @@ static int rtw_set_pid(struct net_device *dev, } static int rtw_wps_start(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4372,8 +4370,9 @@ static int rtw_wps_start(struct net_device *dev, #ifdef CONFIG_P2P static int rtw_wext_p2p_enable(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4438,8 +4437,9 @@ static int rtw_wext_p2p_enable(struct net_device *dev, } static int rtw_p2p_set_go_nego_ssid(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4457,8 +4457,9 @@ static int rtw_p2p_set_go_nego_ssid(struct net_device *dev, static int rtw_p2p_set_intent(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct wifidirect_info *pwdinfo = &(padapter->wdinfo); @@ -4480,8 +4481,9 @@ static int rtw_p2p_set_intent(struct net_device *dev, } static int rtw_p2p_set_listen_ch(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4504,8 +4506,9 @@ static int rtw_p2p_set_listen_ch(struct net_device *dev, } static int rtw_p2p_set_op_ch(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ /* Commented by Albert 20110524 * This function is used to set the operating channel if the driver will become the group owner */ @@ -4530,8 +4533,9 @@ static int rtw_p2p_set_op_ch(struct net_device *dev, static int rtw_p2p_profilefound(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4579,8 +4583,9 @@ static int rtw_p2p_profilefound(struct net_device *dev, } static int rtw_p2p_setDN(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4598,8 +4603,9 @@ static int rtw_p2p_setDN(struct net_device *dev, static int rtw_p2p_get_status(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4608,8 +4614,8 @@ static int rtw_p2p_get_status(struct net_device *dev, if (padapter->bShowGetP2PState) { RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), - pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], - pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); + pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], + pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); } /* Commented by Albert 2010/10/12 */ @@ -4628,8 +4634,9 @@ static int rtw_p2p_get_status(struct net_device *dev, * by sending the provisioning discovery request frame. */ static int rtw_p2p_get_req_cm(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4644,8 +4651,9 @@ static int rtw_p2p_get_req_cm(struct net_device *dev, static int rtw_p2p_get_role(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4654,8 +4662,8 @@ static int rtw_p2p_get_role(struct net_device *dev, RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), - pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], - pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); + pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], + pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); sprintf(extra, "\n\nRole=%.2d\n", rtw_p2p_role(pwdinfo)); wrqu->data.length = strlen(extra); @@ -4665,8 +4673,9 @@ static int rtw_p2p_get_role(struct net_device *dev, static int rtw_p2p_get_peer_ifaddr(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4675,20 +4684,20 @@ static int rtw_p2p_get_peer_ifaddr(struct net_device *dev, RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), - pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], - pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); + pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], + pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); sprintf(extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X", - pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], - pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); + pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], + pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); wrqu->data.length = strlen(extra); return ret; } static int rtw_p2p_get_peer_devaddr(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { @@ -4698,21 +4707,21 @@ static int rtw_p2p_get_peer_devaddr(struct net_device *dev, struct wifidirect_info *pwdinfo = &(padapter->wdinfo); RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), - pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1], - pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3], - pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]); + pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1], + pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3], + pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]); sprintf(extra, "\n%.2X%.2X%.2X%.2X%.2X%.2X", - pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1], - pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3], - pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]); + pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1], + pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3], + pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]); wrqu->data.length = strlen(extra); return ret; } static int rtw_p2p_get_peer_devaddr_by_invitation(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { @@ -4722,21 +4731,21 @@ static int rtw_p2p_get_peer_devaddr_by_invitation(struct net_device *dev, struct wifidirect_info *pwdinfo = &(padapter->wdinfo); RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), - pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1], - pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3], - pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]); + pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1], + pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3], + pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]); sprintf(extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X", - pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1], - pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3], - pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]); + pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1], + pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3], + pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]); wrqu->data.length = strlen(extra); return ret; } static int rtw_p2p_get_groupid(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { @@ -4746,18 +4755,18 @@ static int rtw_p2p_get_groupid(struct net_device *dev, struct wifidirect_info *pwdinfo = &(padapter->wdinfo); sprintf(extra, "\n%.2X:%.2X:%.2X:%.2X:%.2X:%.2X %s", - pwdinfo->groupid_info.go_device_addr[0], pwdinfo->groupid_info.go_device_addr[1], - pwdinfo->groupid_info.go_device_addr[2], pwdinfo->groupid_info.go_device_addr[3], - pwdinfo->groupid_info.go_device_addr[4], pwdinfo->groupid_info.go_device_addr[5], - pwdinfo->groupid_info.ssid); + pwdinfo->groupid_info.go_device_addr[0], pwdinfo->groupid_info.go_device_addr[1], + pwdinfo->groupid_info.go_device_addr[2], pwdinfo->groupid_info.go_device_addr[3], + pwdinfo->groupid_info.go_device_addr[4], pwdinfo->groupid_info.go_device_addr[5], + pwdinfo->groupid_info.ssid); wrqu->data.length = strlen(extra); return ret; } static int rtw_p2p_get_op_ch(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) { @@ -4776,8 +4785,9 @@ static int rtw_p2p_get_op_ch(struct net_device *dev, } static int rtw_p2p_get_wps_configmethod(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra, char *subcmd) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4848,8 +4858,9 @@ static int rtw_p2p_get_wps_configmethod(struct net_device *dev, #ifdef CONFIG_WFD static int rtw_p2p_get_peer_wfd_port(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4867,8 +4878,9 @@ static int rtw_p2p_get_peer_wfd_port(struct net_device *dev, } static int rtw_p2p_get_peer_wfd_preferred_connection(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4885,8 +4897,9 @@ static int rtw_p2p_get_peer_wfd_preferred_connection(struct net_device *dev, } static int rtw_p2p_get_peer_wfd_session_available(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4904,8 +4917,9 @@ static int rtw_p2p_get_peer_wfd_session_available(struct net_device *dev, #endif /* CONFIG_WFD */ static int rtw_p2p_get_go_device_address(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra, char *subcmd) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -4978,7 +4992,7 @@ static int rtw_p2p_get_go_device_address(struct net_device *dev, sprintf(go_devadd_str, "\n\ndev_add=NULL"); else { sprintf(go_devadd_str, "\n\ndev_add=%.2X:%.2X:%.2X:%.2X:%.2X:%.2X", - attr_content[0], attr_content[1], attr_content[2], attr_content[3], attr_content[4], attr_content[5]); + attr_content[0], attr_content[1], attr_content[2], attr_content[3], attr_content[4], attr_content[5]); } wrqu->data.length = strlen(go_devadd_str); @@ -4989,8 +5003,9 @@ static int rtw_p2p_get_go_device_address(struct net_device *dev, } static int rtw_p2p_get_device_type(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra, char *subcmd) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -5062,8 +5077,9 @@ static int rtw_p2p_get_device_type(struct net_device *dev, } static int rtw_p2p_get_device_name(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra, char *subcmd) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -5131,8 +5147,9 @@ static int rtw_p2p_get_device_name(struct net_device *dev, } static int rtw_p2p_get_invitation_procedure(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra, char *subcmd) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -5211,8 +5228,9 @@ static int rtw_p2p_get_invitation_procedure(struct net_device *dev, } static int rtw_p2p_connect(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -5312,7 +5330,10 @@ static int rtw_p2p_connect(struct net_device *dev, u8 union_offset = rtw_mi_get_union_offset(padapter); /* Have to enter the power saving with the AP */ set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - + #ifdef CONFIG_AP_MODE + /*mac-id sleep or wake-up for AP mode*/ + rtw_mi_buddy_ap_acdata_control(padapter, 1); + #endif rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); } #endif /* CONFIG_CONCURRENT_MODE */ @@ -5350,8 +5371,9 @@ static int rtw_p2p_connect(struct net_device *dev, } static int rtw_p2p_invite_req(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -5503,13 +5525,16 @@ static int rtw_p2p_invite_req(struct net_device *dev, u8 union_offset = rtw_mi_get_union_offset(padapter); /* Have to enter the power saving with the AP */ set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - + #ifdef CONFIG_AP_MODE + /*mac-id sleep or wake-up for AP mode*/ + rtw_mi_buddy_ap_acdata_control(padapter, 1); + #endif/*CONFIG_AP_MODE*/ rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); } else set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); #else set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); -#endif +#endif/*CONFIG_CONCURRENT_MODE*/ _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); @@ -5532,8 +5557,9 @@ static int rtw_p2p_invite_req(struct net_device *dev, } static int rtw_p2p_set_persistent(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -5578,7 +5604,8 @@ static int rtw_p2p_set_persistent(struct net_device *dev, } -static int hexstr2bin(const char *hex, u8 *buf, size_t len) { +static int hexstr2bin(const char *hex, u8 *buf, size_t len) +{ size_t i; int a; const char *ipos = hex; @@ -5594,7 +5621,8 @@ static int hexstr2bin(const char *hex, u8 *buf, size_t len) { return 0; } -static int uuid_str2bin(const char *str, u8 *bin) { +static int uuid_str2bin(const char *str, u8 *bin) +{ const char *pos; u8 *opos; @@ -5628,8 +5656,9 @@ static int uuid_str2bin(const char *str, u8 *bin) { } static int rtw_p2p_set_wps_uuid(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -5649,8 +5678,9 @@ static int rtw_p2p_set_wps_uuid(struct net_device *dev, } #ifdef CONFIG_WFD static int rtw_p2p_set_pc(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -5764,8 +5794,9 @@ static int rtw_p2p_set_pc(struct net_device *dev, } static int rtw_p2p_set_wfd_device_type(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -5792,8 +5823,9 @@ static int rtw_p2p_set_wfd_device_type(struct net_device *dev, } static int rtw_p2p_set_wfd_enable(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ /* Commented by Kurt 20121206 * This function is used to set wfd enabled */ @@ -5813,8 +5845,9 @@ static int rtw_p2p_set_wfd_enable(struct net_device *dev, } static int rtw_p2p_set_driver_iface(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ /* Commented by Kurt 20121206 * This function is used to set driver iface is WEXT or CFG80211 */ int ret = 0; @@ -5835,8 +5868,9 @@ static int rtw_p2p_set_driver_iface(struct net_device *dev, /* To set the WFD session available to enable or disable */ static int rtw_p2p_set_sa(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -5867,8 +5901,9 @@ static int rtw_p2p_set_sa(struct net_device *dev, #endif /* CONFIG_WFD */ static int rtw_p2p_prov_disc(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct wifidirect_info *pwdinfo = &(padapter->wdinfo); @@ -5980,7 +6015,7 @@ static int rtw_p2p_prov_disc(struct net_device *dev, /* Some Intel WiDi source may not provide P2P IE, */ /* so we could only compare mac addr by 802.11 Source Address */ if (pmlmepriv->widi_state == INTEL_WIDI_STATE_WFD_CONNECTION - && uintPeerChannel == 0) { + && uintPeerChannel == 0) { if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { uintPeerChannel = pnetwork->network.Configuration.DSConfig; break; @@ -6056,7 +6091,10 @@ static int rtw_p2p_prov_disc(struct net_device *dev, /* Have to enter the power saving with the AP */ set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - + #ifdef CONFIG_AP_MODE + /*mac-id sleep or wake-up for AP mode*/ + rtw_mi_buddy_ap_acdata_control(padapter, 1); + #endif/*CONFIG_AP_MODE*/ rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); } else set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); @@ -6098,8 +6136,9 @@ static int rtw_p2p_prov_disc(struct net_device *dev, * to application. */ static int rtw_p2p_got_wpsinfo(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -6131,8 +6170,9 @@ static int rtw_p2p_got_wpsinfo(struct net_device *dev, #endif /* CONFIG_P2P */ static int rtw_p2p_set(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_P2P @@ -6224,8 +6264,9 @@ static int rtw_p2p_set(struct net_device *dev, } static int rtw_p2p_get(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; @@ -6277,8 +6318,9 @@ static int rtw_p2p_get(struct net_device *dev, } static int rtw_p2p_get2(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; @@ -6325,8 +6367,9 @@ static int rtw_p2p_get2(struct net_device *dev, } static int rtw_cta_test_start(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); RTW_INFO("%s %s\n", __func__, extra); @@ -6352,10 +6395,12 @@ static int rtw_cta_test_start(struct net_device *dev, extern int rtw_change_ifname(_adapter *padapter, const char *ifname); static int rtw_rereg_nd_name(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct rereg_nd_name_data *rereg_priv = &padapter->rereg_nd_name_priv; char new_ifname[IFNAMSIZ]; @@ -6383,7 +6428,9 @@ static int rtw_rereg_nd_name(struct net_device *dev, return ret; RTW_INFO("%s new_ifname:%s\n", __FUNCTION__, new_ifname); + rtw_set_rtnl_lock_holder(dvobj, current); ret = rtw_change_ifname(padapter, new_ifname); + rtw_set_rtnl_lock_holder(dvobj, NULL); if (0 != ret) goto exit; @@ -6424,9 +6471,15 @@ static int rtw_rereg_nd_name(struct net_device *dev, #ifdef DBG_CMD_QUEUE u8 dump_cmd_id = 0; #endif +/* +#ifdef DBG_DUMP_TSF_BY_PORT +extern void get_tsf_by_port(_adapter *adapter, u8 *tsftr, u8 hw_port); +#endif +*/ static int rtw_dbg_port(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _irqL irqL; int ret = 0; u8 major_cmd, minor_cmd; @@ -6510,7 +6563,7 @@ static int rtw_dbg_port(struct net_device *dev, break; case 0x78: /* IOL test */ switch (minor_cmd) { -#ifdef CONFIG_IOL + #ifdef CONFIG_IOL case 0x04: { /* LLT table initialization test */ u8 page_boundary = 0xf9; { @@ -6529,7 +6582,7 @@ static int rtw_dbg_port(struct net_device *dev, ret = -EPERM; } } - break; + break; case 0x05: { /* blink LED test */ u16 reg = 0x4c; u32 blink_num = 50; @@ -6546,23 +6599,23 @@ static int rtw_dbg_port(struct net_device *dev, } for (i = 0; i < blink_num; i++) { -#ifdef CONFIG_IOL_NEW_GENERATION + #ifdef CONFIG_IOL_NEW_GENERATION rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00, 0xff); rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms); rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08, 0xff); rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms); -#else + #else rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00); rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms); rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08); rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms); -#endif + #endif } if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, (blink_delay_ms * blink_num * 2) + 200, 0)) ret = -EPERM; } } - break; + break; case 0x06: { /* continuous wirte byte test */ u16 reg = arg; @@ -6581,11 +6634,11 @@ static int rtw_dbg_port(struct net_device *dev, } for (i = 0; i < write_num; i++) { -#ifdef CONFIG_IOL_NEW_GENERATION + #ifdef CONFIG_IOL_NEW_GENERATION rtw_IOL_append_WB_cmd(xmit_frame, reg, i + start_value, 0xFF); -#else + #else rtw_IOL_append_WB_cmd(xmit_frame, reg, i + start_value); -#endif + #endif } if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0)) ret = -EPERM; @@ -6597,7 +6650,7 @@ static int rtw_dbg_port(struct net_device *dev, else RTW_INFO("continuous IOL_CMD_WB_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final); } - break; + break; case 0x07: { /* continuous wirte word test */ u16 reg = arg; @@ -6617,11 +6670,11 @@ static int rtw_dbg_port(struct net_device *dev, } for (i = 0; i < write_num; i++) { -#ifdef CONFIG_IOL_NEW_GENERATION + #ifdef CONFIG_IOL_NEW_GENERATION rtw_IOL_append_WW_cmd(xmit_frame, reg, i + start_value, 0xFFFF); -#else + #else rtw_IOL_append_WW_cmd(xmit_frame, reg, i + start_value); -#endif + #endif } if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0)) ret = -EPERM; @@ -6633,7 +6686,7 @@ static int rtw_dbg_port(struct net_device *dev, else RTW_INFO("continuous IOL_CMD_WW_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final); } - break; + break; case 0x08: { /* continuous wirte dword test */ u16 reg = arg; @@ -6653,11 +6706,11 @@ static int rtw_dbg_port(struct net_device *dev, } for (i = 0; i < write_num; i++) { -#ifdef CONFIG_IOL_NEW_GENERATION + #ifdef CONFIG_IOL_NEW_GENERATION rtw_IOL_append_WD_cmd(xmit_frame, reg, i + start_value, 0xFFFFFFFF); -#else + #else rtw_IOL_append_WD_cmd(xmit_frame, reg, i + start_value); -#endif + #endif } if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0)) ret = -EPERM; @@ -6670,8 +6723,8 @@ static int rtw_dbg_port(struct net_device *dev, else RTW_INFO("continuous IOL_CMD_WD_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final); } - break; -#endif /* CONFIG_IOL */ + break; + #endif /* CONFIG_IOL */ } break; case 0x79: { @@ -6691,10 +6744,10 @@ static int rtw_dbg_port(struct net_device *dev, write_value = value | (value << 5); rtw_write16(padapter, 0x6d9, write_value); } - break; + break; case 0x7a: receive_disconnect(padapter, pmlmeinfo->network.MacAddress - , WLAN_REASON_EXPIRATION_CHK, _FALSE); + , WLAN_REASON_EXPIRATION_CHK, _FALSE); break; case 0x7F: switch (minor_cmd) { @@ -6703,8 +6756,8 @@ static int rtw_dbg_port(struct net_device *dev, break; case 0x01: RTW_INFO("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", - psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, - psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); + psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, + psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); break; case 0x02: RTW_INFO("pmlmeinfo->state=0x%x\n", pmlmeinfo->state); @@ -6747,28 +6800,34 @@ static int rtw_dbg_port(struct net_device *dev, RTW_INFO("can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); break; case 0x06: { + #ifdef DBG_DUMP_TSF_BY_PORT + u64 tsf = 0; + + get_tsf_by_port(padapter, (u8 *)&tsf, extra_arg); + RTW_INFO(" PORT-%d TSF :%lld\n", extra_arg, tsf); + #endif } - break; + break; case 0x07: RTW_INFO("bSurpriseRemoved=%s, bDriverStopped=%s\n" - , rtw_is_surprise_removed(padapter) ? "True" : "False" - , rtw_is_drv_stopped(padapter) ? "True" : "False"); + , rtw_is_surprise_removed(padapter) ? "True" : "False" + , rtw_is_drv_stopped(padapter) ? "True" : "False"); break; case 0x08: { struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct recv_priv *precvpriv = &padapter->recvpriv; RTW_INFO("free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d" - ", free_xmit_extbuf_cnt=%d, free_xframe_ext_cnt=%d" - ", free_recvframe_cnt=%d\n", - pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt, - pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt, - precvpriv->free_recvframe_cnt); + ", free_xmit_extbuf_cnt=%d, free_xframe_ext_cnt=%d" + ", free_recvframe_cnt=%d\n", + pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt, + pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt, + precvpriv->free_recvframe_cnt); #ifdef CONFIG_USB_HCI RTW_INFO("rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt))); #endif } - break; + break; case 0x09: { int i; _list *plist, *phead; @@ -6794,7 +6853,7 @@ static int rtw_dbg_port(struct net_device *dev, #ifdef CONFIG_80211N_HT RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, - psta->htpriv.sgi_40m); + psta->htpriv.sgi_40m); RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); #endif /* CONFIG_80211N_HT */ @@ -6818,7 +6877,7 @@ static int rtw_dbg_port(struct net_device *dev, _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); } - break; + break; case 0x0b: { /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */ /* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */ @@ -6837,7 +6896,7 @@ static int rtw_dbg_port(struct net_device *dev, padapter->driver_vcs_type = extra_arg; } } - break; + break; case 0x0c: { /* dump rx/tx packet */ if (arg == 0) { RTW_INFO("dump rx packet (%d)\n", extra_arg); @@ -6848,7 +6907,7 @@ static int rtw_dbg_port(struct net_device *dev, rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(extra_arg)); } } - break; + break; case 0x0e: { if (arg == 0) { RTW_INFO("disable driver ctrl rx_ampdu_factor\n"); @@ -6863,8 +6922,8 @@ static int rtw_dbg_port(struct net_device *dev, padapter->driver_rx_ampdu_factor = extra_arg; } } - break; -#ifdef DBG_CONFIG_ERROR_DETECT + break; + #ifdef DBG_CONFIG_ERROR_DETECT case 0x0f: { if (extra_arg == 0) { RTW_INFO("###### silent reset test.......#####\n"); @@ -6876,14 +6935,14 @@ static int rtw_dbg_port(struct net_device *dev, } } - break; + break; case 0x15: { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); RTW_INFO("==>silent resete cnts:%d\n", pwrpriv->ips_enter_cnts); } - break; + break; -#endif + #endif case 0x10: /* driver version display */ dump_drv_version(RTW_DBGDUMP); @@ -6903,7 +6962,7 @@ static int rtw_dbg_port(struct net_device *dev, } - break; + break; #ifdef CONFIG_80211N_HT case 0x12: { /* set rx_stbc */ struct registry_priv *pregpriv = &padapter->registrypriv; @@ -6916,34 +6975,26 @@ static int rtw_dbg_port(struct net_device *dev, RTW_INFO("get rx_stbc=%d\n", pregpriv->rx_stbc); } - break; + break; case 0x13: { /* set ampdu_enable */ struct registry_priv *pregpriv = &padapter->registrypriv; - /* 0: disable, 0x1:enable (but wifi_spec should be 0), 0x2: force enable (don't care wifi_spec) */ - if (pregpriv && extra_arg < 3) { + /* 0: disable, 0x1:enable */ + if (pregpriv && extra_arg < 2) { pregpriv->ampdu_enable = extra_arg; RTW_INFO("set ampdu_enable=%d\n", pregpriv->ampdu_enable); } else RTW_INFO("get ampdu_enable=%d\n", pregpriv->ampdu_enable); } - break; + break; #endif case 0x14: { /* get wifi_spec */ struct registry_priv *pregpriv = &padapter->registrypriv; RTW_INFO("get wifi_spec=%d\n", pregpriv->wifi_spec); } - break; - case 0x16: { - if (arg == 0xff) - rtw_odm_dbg_comp_msg(RTW_DBGDUMP, padapter); - else { - u64 dbg_comp = (u64)extra_arg; - rtw_odm_dbg_comp_set(padapter, dbg_comp); - } - } - break; + break; + #ifdef DBG_FIXED_CHAN case 0x17: { struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); @@ -6951,7 +7002,7 @@ static int rtw_dbg_port(struct net_device *dev, pmlmeext->fixed_chan = extra_arg; } - break; + break; #endif #ifdef CONFIG_80211N_HT case 0x19: { @@ -6967,7 +7018,7 @@ static int rtw_dbg_port(struct net_device *dev, pregistrypriv->ldpc_cap = (u8)(extra_arg & 0x33); } } - break; + break; case 0x1a: { struct registry_priv *pregistrypriv = &padapter->registrypriv; /* extra_arg : */ @@ -6981,7 +7032,7 @@ static int rtw_dbg_port(struct net_device *dev, pregistrypriv->stbc_cap = (u8)(extra_arg & 0x33); } } - break; + break; #endif /* CONFIG_80211N_HT */ case 0x1b: { struct registry_priv *pregistrypriv = &padapter->registrypriv; @@ -7023,7 +7074,7 @@ static int rtw_dbg_port(struct net_device *dev, #endif /* CONFIG_80211N_HT */ } } - break; + break; case 0x1c: { /* enable/disable driver control AMPDU Density for peer sta's rx */ if (arg == 0) { RTW_INFO("disable driver ctrl ampdu density\n"); @@ -7038,33 +7089,116 @@ static int rtw_dbg_port(struct net_device *dev, padapter->driver_ampdu_spacing = extra_arg; } } - break; + break; #ifdef CONFIG_BACKGROUND_NOISE_MONITOR case 0x1e: { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; u8 chan = rtw_get_oper_ch(padapter); RTW_INFO("===========================================\n"); - ODM_InbandNoise_Monitor(pDM_Odm, _TRUE, 0x1e, 100); + odm_inband_noise_monitor(pDM_Odm, _TRUE, 0x1e, 100); RTW_INFO("channel(%d),noise_a = %d, noise_b = %d , noise_all:%d\n", - chan, pDM_Odm->noise_level.noise[ODM_RF_PATH_A], - pDM_Odm->noise_level.noise[ODM_RF_PATH_B], - pDM_Odm->noise_level.noise_all); + chan, pDM_Odm->noise_level.noise[ODM_RF_PATH_A], + pDM_Odm->noise_level.noise[ODM_RF_PATH_B], + pDM_Odm->noise_level.noise_all); RTW_INFO("===========================================\n"); } - break; -#endif - case 0x23: { - RTW_INFO("turn %s the bNotifyChannelChange Variable\n", (extra_arg == 1) ? "on" : "off"); - padapter->bNotifyChannelChange = extra_arg; break; - } - case 0x24: { -#ifdef CONFIG_P2P - RTW_INFO("turn %s the bShowGetP2PState Variable\n", (extra_arg == 1) ? "on" : "off"); - padapter->bShowGetP2PState = extra_arg; -#endif /* CONFIG_P2P */ +#endif + + +#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS) + case 0x1f: + { + int i, j = 0, test_cnts = 0; + static u8 test_code = 0x5A; + static u32 data_misatch_cnt = 0, d_acc_err_cnt = 0; + + u32 d_data, i_data; + u32 imr; + + test_cnts = extra_arg; + for (i = 0; i < test_cnts; i++) { + if (RTW_CANNOT_IO(padapter)) + break; + + rtw_write8(padapter, 0x07, test_code); + + d_data = rtw_read32(padapter, 0x04); + imr = rtw_read32(padapter, 0x10250014); + rtw_write32(padapter, 0x10250014, 0); + rtw_msleep_os(50); + + i_data = rtw_sd_iread32(padapter, 0x04); + + rtw_write32(padapter, 0x10250014, imr); + + if (d_data != i_data) { + data_misatch_cnt++; + RTW_ERR("d_data :0x%08x, i_data : 0x%08x\n", d_data, i_data); + } + + if (test_code != (i_data >> 24)) { + d_acc_err_cnt++; + rtw_write8(padapter, 0x07, 0xAA); + RTW_ERR("test_code :0x%02x, i_data : 0x%08x\n", test_code, i_data); + } + if ((j++) == 100) { + rtw_msleep_os(2000); + RTW_INFO(" Indirect access testing..........%d/%d\n", i, test_cnts); + j = 0; + } + + test_code = ~test_code; + rtw_msleep_os(50); + } + RTW_INFO("========Indirect access test=========\n"); + RTW_INFO(" test_cnts = %d\n", test_cnts); + RTW_INFO(" direct & indirect read32 data missatch cnts = %d\n", data_misatch_cnt); + RTW_INFO(" indirect rdata is not equal to wdata cnts = %d\n", d_acc_err_cnt); + RTW_INFO("========Indirect access test=========\n\n"); + data_misatch_cnt = d_acc_err_cnt = 0; + + } + break; +#endif + case 0x20: + { + if (arg == 0xAA) { + u8 page_offset, page_num; + u32 page_size = 0; + u8 *buffer = NULL; + u32 buf_size = 0; + + page_offset = (u8)(extra_arg >> 16); + page_num = (u8)(extra_arg & 0xFF); + rtw_dump_rsvd_page(RTW_DBGDUMP, padapter, page_offset, page_num); + } +#ifdef CONFIG_SUPPORT_FIFO_DUMP + else { + u8 fifo_sel; + u32 addr, size; + + fifo_sel = (u8)(arg & 0x0F); + addr = (extra_arg >> 16) & 0xFFFF; + size = extra_arg & 0xFFFF; + rtw_dump_fifo(RTW_DBGDUMP, padapter, fifo_sel, addr, size); + } +#endif + } + break; + + case 0x23: { + RTW_INFO("turn %s the bNotifyChannelChange Variable\n", (extra_arg == 1) ? "on" : "off"); + padapter->bNotifyChannelChange = extra_arg; + break; + } + case 0x24: { +#ifdef CONFIG_P2P + RTW_INFO("turn %s the bShowGetP2PState Variable\n", (extra_arg == 1) ? "on" : "off"); + padapter->bShowGetP2PState = extra_arg; +#endif /* CONFIG_P2P */ break; } #ifdef CONFIG_GPIO_API @@ -7109,7 +7243,7 @@ static int rtw_dbg_port(struct net_device *dev, dump_cmd_id = extra_arg; RTW_INFO("dump_cmd_id:%d\n", dump_cmd_id); } - break; + break; #endif /* DBG_CMD_QUEUE */ case 0xaa: { if ((extra_arg & 0x7F) > 0x3F) @@ -7117,7 +7251,7 @@ static int rtw_dbg_port(struct net_device *dev, RTW_INFO("chang data rate to :0x%02x\n", extra_arg); padapter->fix_rate = extra_arg; } - break; + break; case 0xdd: { /* registers dump , 0 for mac reg,1 for bb reg, 2 for rf reg */ if (extra_arg == 0) mac_reg_dump(RTW_DBGDUMP, padapter); @@ -7125,13 +7259,15 @@ static int rtw_dbg_port(struct net_device *dev, bb_reg_dump(RTW_DBGDUMP, padapter); else if (extra_arg == 2) rf_reg_dump(RTW_DBGDUMP, padapter); + else if (extra_arg == 11) + bb_reg_dump_ex(RTW_DBGDUMP, padapter); } - break; + break; case 0xee: { RTW_INFO(" === please control /proc to trun on/off PHYDM func ===\n"); } - break; + break; case 0xfd: rtw_write8(padapter, 0xc50, arg); @@ -7170,7 +7306,7 @@ static int rtw_dbg_port(struct net_device *dev, RTW_INFO("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c)); RTW_INFO("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450)); } - break; + break; } break; default: @@ -7183,7 +7319,8 @@ static int rtw_dbg_port(struct net_device *dev, } -static int wpa_set_param(struct net_device *dev, u8 name, u32 value) { +static int wpa_set_param(struct net_device *dev, u8 name, u32 value) +{ uint ret = 0; u32 flags; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -7206,7 +7343,6 @@ static int wpa_set_param(struct net_device *dev, u8 name, u32 value) { break; } - RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ("wpa_set_param:padapter->securitypriv.ndisauthtype=%d\n", padapter->securitypriv.ndisauthtype)); break; @@ -7295,7 +7431,8 @@ static int wpa_set_param(struct net_device *dev, u8 name, u32 value) { } -static int wpa_mlme(struct net_device *dev, u32 command, u32 reason) { +static int wpa_mlme(struct net_device *dev, u32 command, u32 reason) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -7323,7 +7460,8 @@ static int wpa_mlme(struct net_device *dev, u32 command, u32 reason) { } -static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p) { +static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p) +{ struct ieee_param *param; uint ret = 0; @@ -7386,7 +7524,8 @@ static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p) { } #ifdef CONFIG_AP_MODE -static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) { +static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +{ int ret = 0; u32 wep_key_idx, wep_key_len, wep_total_len; NDIS_802_11_WEP *pwep = NULL; @@ -7409,11 +7548,11 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, } if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { if (param->u.crypt.idx >= WEP_KEYS #ifdef CONFIG_IEEE80211W - && param->u.crypt.idx > BIP_MAX_KEYID + && param->u.crypt.idx > BIP_MAX_KEYID #endif /* CONFIG_IEEE80211W */ ) { ret = -EINVAL; @@ -7515,8 +7654,7 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, } - if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) { /* */ - /* group key */ + if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) /* */ { /* group key */ if (param->u.crypt.set_tx == 1) { if (strcmp(param->u.crypt.alg, "WEP") == 0) { RTW_INFO("%s, set group_key, WEP\n", __FUNCTION__); @@ -7686,7 +7824,8 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, } -static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len) { +static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -7715,7 +7854,8 @@ static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int } -static int rtw_hostapd_sta_flush(struct net_device *dev) { +static int rtw_hostapd_sta_flush(struct net_device *dev) +{ /* _irqL irqL; */ /* _list *phead, *plist; */ int ret = 0; @@ -7733,7 +7873,8 @@ static int rtw_hostapd_sta_flush(struct net_device *dev) { } -static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) { +static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) +{ _irqL irqL; int ret = 0; struct sta_info *psta = NULL; @@ -7747,8 +7888,8 @@ static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) { return -EINVAL; if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) return -EINVAL; #if 0 @@ -7808,7 +7949,8 @@ static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) { } -static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) { +static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) +{ _irqL irqL; int ret = 0; struct sta_info *psta = NULL; @@ -7822,8 +7964,8 @@ static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) { return -EINVAL; if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) return -EINVAL; psta = rtw_get_stainfo(pstapriv, param->sta_addr); @@ -7856,7 +7998,8 @@ static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) { } -static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *param, int len) { +static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *param, int len) +{ int ret = 0; struct sta_info *psta = NULL; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -7871,8 +8014,8 @@ static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *par return -EINVAL; if (param_ex->sta_addr[0] == 0xff && param_ex->sta_addr[1] == 0xff && - param_ex->sta_addr[2] == 0xff && param_ex->sta_addr[3] == 0xff && - param_ex->sta_addr[4] == 0xff && param_ex->sta_addr[5] == 0xff) + param_ex->sta_addr[2] == 0xff && param_ex->sta_addr[3] == 0xff && + param_ex->sta_addr[4] == 0xff && param_ex->sta_addr[5] == 0xff) return -EINVAL; psta = rtw_get_stainfo(pstapriv, param_ex->sta_addr); @@ -7908,11 +8051,11 @@ static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *par */ psta_data->sta_set = ((psta->nonerp_set) | - (psta->no_short_slot_time_set << 1) | - (psta->no_short_preamble_set << 2) | - (psta->no_ht_gf_set << 3) | - (psta->no_ht_set << 4) | - (psta->ht_20mhz_set << 5)); + (psta->no_short_slot_time_set << 1) | + (psta->no_short_preamble_set << 2) | + (psta->no_ht_gf_set << 3) | + (psta->no_ht_set << 4) | + (psta->ht_20mhz_set << 5)); psta_data->tx_supp_rates_len = psta->bssratelen; _rtw_memcpy(psta_data->tx_supp_rates, psta->bssrateset, psta->bssratelen); @@ -7935,7 +8078,8 @@ static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *par } -static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param) { +static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param) +{ int ret = 0; struct sta_info *psta = NULL; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -7948,8 +8092,8 @@ static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param) { return -EINVAL; if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) return -EINVAL; psta = rtw_get_stainfo(pstapriv, param->sta_addr); @@ -7976,7 +8120,8 @@ static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param) { } -static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len) { +static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len) +{ int ret = 0; unsigned char wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -8019,7 +8164,8 @@ static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, } -static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len) { +static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -8053,7 +8199,8 @@ static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *par } -static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len) { +static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -8088,7 +8235,8 @@ static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *par } -static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len) { +static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len) +{ int ret = 0; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *mlmepriv = &(adapter->mlmepriv); @@ -8120,9 +8268,9 @@ static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, if (0) RTW_INFO(FUNC_ADPT_FMT" ssid:(%s,%d), from ie:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), - ssid, ssid_len, - pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, - pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); + ssid, ssid_len, + pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, + pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); _rtw_memcpy(pbss_network->Ssid.Ssid, (void *)ssid, ssid_len); pbss_network->Ssid.SsidLength = ssid_len; @@ -8131,18 +8279,19 @@ static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, if (0) RTW_INFO(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), - pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, - pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); + pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, + pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); } RTW_INFO(FUNC_ADPT_FMT" ignore_broadcast_ssid:%d, %s,%d\n", FUNC_ADPT_ARG(adapter), - ignore_broadcast_ssid, ssid, ssid_len); + ignore_broadcast_ssid, ssid, ssid_len); return ret; } #if CONFIG_RTW_MACADDR_ACL -static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len) { +static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -8151,8 +8300,8 @@ static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *p return -EINVAL; if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) return -EINVAL; ret = rtw_acl_remove_sta(padapter, param->sta_addr); @@ -8161,7 +8310,8 @@ static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *p } -static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len) { +static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -8170,8 +8320,8 @@ static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *para return -EINVAL; if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) return -EINVAL; ret = rtw_acl_add_sta(padapter, param->sta_addr); @@ -8180,7 +8330,8 @@ static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *para } -static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len) { +static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -8194,7 +8345,8 @@ static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param * } #endif /* CONFIG_RTW_MACADDR_ACL */ -static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p) { +static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p) +{ struct ieee_param *param; int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -8332,9 +8484,10 @@ static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p) { #endif static int rtw_wx_set_priv(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *awrq, - char *extra) { + struct iw_request_info *info, + union iwreq_data *awrq, + char *extra) +{ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV char *ext_dbg; @@ -8348,7 +8501,6 @@ static int rtw_wx_set_priv(struct net_device *dev, _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct iw_point *dwrq = (struct iw_point *)awrq; - /* RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, ("+rtw_wx_set_priv\n")); */ if (dwrq->length == 0) return -EFAULT; @@ -8363,9 +8515,6 @@ static int rtw_wx_set_priv(struct net_device *dev, } - /* RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, */ - /* ("rtw_wx_set_priv: %s req=%s\n", */ - /* dev->name, ext)); */ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV ext_dbg = rtw_vmalloc(len); @@ -8386,7 +8535,7 @@ static int rtw_wx_set_priv(struct net_device *dev, u8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; if ((_VENDOR_SPECIFIC_IE_ == probereq_wpsie[0]) && - (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) == _TRUE)) { + (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) == _TRUE)) { cp_sz = probereq_wpsie_len > MAX_WPS_IE_LEN ? MAX_WPS_IE_LEN : probereq_wpsie_len; if (pmlmepriv->wps_probe_req_ie) { @@ -8414,8 +8563,8 @@ static int rtw_wx_set_priv(struct net_device *dev, } if (len >= WEXT_CSCAN_HEADER_SIZE - && _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE - ) { + && _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE + ) { ret = rtw_wx_set_scan(dev, info, awrq, ext); goto FREE_EXT; } @@ -8441,12 +8590,12 @@ static int rtw_wx_set_priv(struct net_device *dev, else sprintf(ext, "OK"); } - break; + break; case ANDROID_WIFI_CMD_LINKSPEED: { u16 mbps = rtw_get_cur_max_rate(padapter) / 10; sprintf(ext, "LINKSPEED %d", mbps); } - break; + break; case ANDROID_WIFI_CMD_MACADDR: sprintf(ext, "MACADDR = " MAC_FMT, MAC_ARG(dev->dev_addr)); break; @@ -8454,12 +8603,12 @@ static int rtw_wx_set_priv(struct net_device *dev, /* rtw_set_scan_mode(padapter, SCAN_ACTIVE); */ sprintf(ext, "OK"); } - break; + break; case ANDROID_WIFI_CMD_SCAN_PASSIVE: { /* rtw_set_scan_mode(padapter, SCAN_PASSIVE); */ sprintf(ext, "OK"); } - break; + break; case ANDROID_WIFI_CMD_COUNTRY: { char country_code[10]; @@ -8467,12 +8616,12 @@ static int rtw_wx_set_priv(struct net_device *dev, rtw_set_country(padapter, country_code); sprintf(ext, "OK"); } - break; + break; default: -#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV RTW_INFO("%s: %s unknowned req=%s\n", __FUNCTION__, - dev->name, ext_dbg); -#endif + dev->name, ext_dbg); + #endif sprintf(ext, "OK"); @@ -8483,7 +8632,7 @@ static int rtw_wx_set_priv(struct net_device *dev, #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV RTW_INFO("%s: %s req=%s rep=%s dwrq->length=%d, strlen(ext)+1=%d\n", __FUNCTION__, - dev->name, ext_dbg , ext, dwrq->length, (u16)(strlen(ext) + 1)); + dev->name, ext_dbg , ext, dwrq->length, (u16)(strlen(ext) + 1)); #endif #endif /* end of CONFIG_ANDROID */ @@ -8491,9 +8640,9 @@ static int rtw_wx_set_priv(struct net_device *dev, FREE_EXT: rtw_vmfree(ext, len); -#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV rtw_vmfree(ext_dbg, len); -#endif + #endif /* RTW_INFO("rtw_wx_set_priv: (SIOCSIWPRIV) %s ret=%d\n", */ /* dev->name, ret); */ @@ -8503,8 +8652,9 @@ static int rtw_wx_set_priv(struct net_device *dev, } #ifdef CONFIG_WOWLAN static int rtw_wowlan_ctrl(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct wowlan_ioctl_param poidparam; struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); @@ -8517,7 +8667,7 @@ static int rtw_wowlan_ctrl(struct net_device *dev, RTW_INFO("+rtw_wowlan_ctrl: %s\n", extra); if (!check_fwstate(pmlmepriv, _FW_LINKED) && - check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { #ifdef CONFIG_PNO_SUPPORT pwrctrlpriv->wowlan_pno_enable = _TRUE; #else @@ -8553,7 +8703,7 @@ static int rtw_wowlan_ctrl(struct net_device *dev, _rtw_wowlan_ctrl_exit_free: RTW_INFO("-rtw_wowlan_ctrl( subcode = %d)\n", poidparam.subcode); RTW_PRINT("%s in %d ms\n", __func__, - rtw_get_passing_time_ms(start_time)); + rtw_get_passing_time_ms(start_time)); _rtw_wowlan_ctrl_exit: return ret; } @@ -8574,8 +8724,9 @@ static int rtw_wowlan_ctrl(struct net_device *dev, */ static int rtw_wowlan_set_pattern(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -8588,7 +8739,7 @@ static int rtw_wowlan_set_pattern(struct net_device *dev, poidparam.subcode = 0; if (!check_fwstate(pmlmepriv, _FW_LINKED) && - check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { ret = -EFAULT; RTW_INFO("Please Connect With AP First!!\n"); goto _rtw_wowlan_set_pattern_exit; @@ -8601,24 +8752,24 @@ static int rtw_wowlan_set_pattern(struct net_device *dev, } else { /* set pattern */ if (copy_from_user(input, - wrqu->data.pointer, wrqu->data.length)) + wrqu->data.pointer, wrqu->data.length)) return -EFAULT; /* leave PS first */ rtw_ps_deny(padapter, PS_DENY_IOCTL); LeaveAllPowerSaveModeDirect(padapter); if (strncmp(input, "pattern=", 8) == 0) { - if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_NUM) { + if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) { RTW_INFO("WARNING: priv-pattern is full(idx: %d)\n", - pwrpriv->wowlan_pattern_idx); + pwrpriv->wowlan_pattern_idx); RTW_INFO("WARNING: please clean priv-pattern first\n"); ret = -EINVAL; goto _rtw_wowlan_set_pattern_exit; } else { index = pwrpriv->wowlan_pattern_idx; ret = rtw_wowlan_parser_pattern_cmd(input, - pwrpriv->patterns[index].content, - &pwrpriv->patterns[index].len, - pwrpriv->patterns[index].mask); + pwrpriv->patterns[index].content, + &pwrpriv->patterns[index].len, + pwrpriv->patterns[index].mask); if (ret == _TRUE) pwrpriv->wowlan_pattern_idx++; @@ -8626,16 +8777,10 @@ static int rtw_wowlan_set_pattern(struct net_device *dev, } else if (strncmp(input, "clean", 5) == 0) { poidparam.subcode = WOWLAN_PATTERN_CLEAN; rtw_hal_set_hwreg(padapter, - HW_VAR_WOWLAN, (u8 *)&poidparam); + HW_VAR_WOWLAN, (u8 *)&poidparam); } else if (strncmp(input, "show", 4) == 0) { - for (i = 0 ; i < MAX_WKFM_NUM ; i++) { - RTW_INFO("=======[%d]=======\n", i); - rtw_read_from_frame_mask(padapter, i); - } - - RTW_INFO("********[RTK priv-patterns]*********\n"); - for (i = 0 ; i < MAX_WKFM_NUM ; i++) - rtw_dump_priv_pattern(padapter, i); + rtw_wow_pattern_cam_dump(padapter); + rtw_wow_pattern_sw_dump(padapter); } else { RTW_INFO("ERROR: incorrect parameter!\n"); ret = -EINVAL; @@ -8649,8 +8794,9 @@ static int rtw_wowlan_set_pattern(struct net_device *dev, #ifdef CONFIG_AP_WOWLAN static int rtw_ap_wowlan_ctrl(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct wowlan_ioctl_param poidparam; struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); @@ -8686,15 +8832,16 @@ static int rtw_ap_wowlan_ctrl(struct net_device *dev, _rtw_ap_wowlan_ctrl_exit_free: RTW_INFO("-rtw_ap_wowlan_ctrl( subcode = %d)\n", poidparam.subcode); RTW_PRINT("%s in %d ms\n", __func__, - rtw_get_passing_time_ms(start_time)); + rtw_get_passing_time_ms(start_time)); _rtw_ap_wowlan_ctrl_exit: return ret; } #endif /* CONFIG_AP_WOWLAN */ static int rtw_pm_set(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; unsigned mode = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -8707,6 +8854,9 @@ static int rtw_pm_set(struct net_device *dev, } else if (_rtw_memcmp(extra, "ips=", 4)) { sscanf(extra + 4, "%u", &mode); ret = rtw_pm_set_ips(padapter, mode); + } else if (_rtw_memcmp(extra, "lps_level=", 10)) { + if (sscanf(extra + 10, "%u", &mode) > 0) + ret = rtw_pm_set_lps_level(padapter, mode); } else ret = -EINVAL; @@ -8714,33 +8864,54 @@ static int rtw_pm_set(struct net_device *dev, } #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE -int rtw_vendor_ie_get(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - int ret = 0, vendor_ie_num = 0 , j , len = 0 , cmdlen; - char *pstring; +int rtw_vendor_ie_get_raw_data(struct net_device *dev, u32 vendor_ie_num, + char *extra, u32 length) +{ + int j; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct iw_point *p; - u8 *ptmp; u32 vendor_ie_mask = 0; + char *pstring; - p = &wrqu->data; - cmdlen = p->length; - if (0 == cmdlen) - return -EINVAL; - - ptmp = (u8 *)rtw_malloc(cmdlen); - if (NULL == ptmp) - return -ENOMEM; + if (vendor_ie_num >= WLAN_MAX_VENDOR_IE_NUM) { + RTW_INFO("[%s] only support %d vendor ie\n", __func__ , + WLAN_MAX_VENDOR_IE_NUM); + return -EFAULT; + } - if (copy_from_user(ptmp, p->pointer, cmdlen)) { - ret = -EFAULT; - goto exit; + if (pmlmepriv->vendor_ielen[vendor_ie_num] == 0) { + RTW_INFO("[%s] Fail, vendor_ie_num: %d is not set\n", __func__, + vendor_ie_num); + return -EFAULT; } - ret = sscanf(ptmp , "%d", &vendor_ie_num); - if (vendor_ie_num > WLAN_MAX_VENDOR_IE_NUM - 1) { - ret = -EFAULT; - goto exit; + + if (length < 2 * pmlmepriv->vendor_ielen[vendor_ie_num] + 5) { + RTW_INFO("[%s] Fail, buffer size is too small\n", __func__); + return -EFAULT; } + + vendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num]; + _rtw_memset(extra, 0, length); + + pstring = extra; + pstring += sprintf(pstring, "%d,%x,", vendor_ie_num, vendor_ie_mask); + + for (j = 0; j < pmlmepriv->vendor_ielen[vendor_ie_num]; j++) + pstring += sprintf(pstring, "%02x", pmlmepriv->vendor_ie[vendor_ie_num][j]); + + length = pstring - extra; + return length; +} + +int rtw_vendor_ie_get_data(struct net_device *dev, int vendor_ie_num, char *extra) +{ + int j; + char *pstring; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u32 vendor_ie_mask = 0; + __u16 length = 0; + vendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num]; pstring = extra; pstring += sprintf(pstring , "\nVendor IE num %d , Mask:%x " , vendor_ie_num , vendor_ie_mask); @@ -8760,7 +8931,37 @@ int rtw_vendor_ie_get(struct net_device *dev, struct iw_request_info *info, unio for (j = 0 ; j < pmlmepriv->vendor_ielen[vendor_ie_num] ; j++) pstring += sprintf(pstring , "%02x" , pmlmepriv->vendor_ie[vendor_ie_num][j]); - wrqu->data.length = pstring - extra; + length = pstring - extra; + return length; + +} + +int rtw_vendor_ie_get(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ + int ret = 0, vendor_ie_num = 0, cmdlen; + struct iw_point *p; + u8 *ptmp; + + p = &wrqu->data; + cmdlen = p->length; + if (0 == cmdlen) + return -EINVAL; + + ptmp = (u8 *)rtw_malloc(cmdlen); + if (NULL == ptmp) + return -ENOMEM; + + if (copy_from_user(ptmp, p->pointer, cmdlen)) { + ret = -EFAULT; + goto exit; + } + ret = sscanf(ptmp , "%d", &vendor_ie_num); + if (vendor_ie_num > WLAN_MAX_VENDOR_IE_NUM - 1) { + ret = -EFAULT; + goto exit; + } + + wrqu->data.length = rtw_vendor_ie_get_data(dev, vendor_ie_num, extra); exit: rtw_mfree(ptmp, cmdlen); @@ -8768,7 +8969,8 @@ int rtw_vendor_ie_get(struct net_device *dev, struct iw_request_info *info, unio return 0; } -int rtw_vendor_ie_set(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { +int rtw_vendor_ie_set(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) +{ int ret = 0, i , len = 0 , totoal_ie_len = 0 , total_ie_len_byte = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -8818,7 +9020,7 @@ int rtw_vendor_ie_set(struct net_device *dev, struct iw_request_info *info, unio elen = pmlmepriv->vendor_ie[vendor_ie_num][len]; if (elen != total_ie_len_byte) { RTW_INFO("[%s] Fail , Input IE length = \"%d\"(hex:%x) bytes , not match input total IE context length \"%d\" bytes\n", __func__ , elen , elen , - total_ie_len_byte); + total_ie_len_byte); goto _clear_path; } } @@ -8854,8 +9056,9 @@ int rtw_vendor_ie_set(struct net_device *dev, struct iw_request_info *info, unio #endif static int rtw_mp_efuse_get(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wdata, char *extra) { + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); @@ -8871,7 +9074,10 @@ static int rtw_mp_efuse_get(struct net_device *dev, char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00}; u16 i = 0, j = 0, mapLen = 0, addr = 0, cnts = 0; u16 max_available_len = 0, raw_cursize = 0, raw_maxsize = 0; + u16 mask_len; + u8 mask_buf[64] = ""; int err; + char *pextra = NULL; #ifdef CONFIG_IOL u8 org_fw_iol = padapter->registrypriv.fw_iol;/* 0:Disable, 1:enable, 2:by usb speed */ #endif @@ -8923,31 +9129,43 @@ static int rtw_mp_efuse_get(struct net_device *dev, if (strcmp(tmp[0], "status") == 0) { sprintf(extra, "Load File efuse=%s,Load File MAC=%s" - , pHalData->efuse_file_status == EFUSE_FILE_FAILED ? "FAIL" : "OK" - , pHalData->macaddr_file_status == MACADDR_FILE_FAILED ? "FAIL" : "OK" + , pHalData->efuse_file_status == EFUSE_FILE_FAILED ? "FAIL" : "OK" + , pHalData->macaddr_file_status == MACADDR_FILE_FAILED ? "FAIL" : "OK" ); goto exit; } else if (strcmp(tmp[0], "drvmap") == 0) { + static u8 drvmaporder = 0; + u8 *efuse; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE); + efuse = pHalData->efuse_eeprom_data; + + shift = blksz * drvmaporder; + efuse += shift; + cnt = mapLen - shift; + + if (cnt > blksz) { + cnt = blksz; + drvmaporder++; + } else + drvmaporder = 0; + sprintf(extra, "\n"); - for (i = 0; i < mapLen; i += 16) { - /*RTW_INFO("0x%02x\t", i);*/ - sprintf(extra, "%s0x%02x\t", extra, i); - for (j = 0; j < 8; j++) { - /* RTW_INFO("%02X ", data[i+j]); */ - sprintf(extra, "%s%02X ", extra, PROMContent[i + j]); - } - /* RTW_INFO("\t"); */ - sprintf(extra, "%s\t", extra); - for (; j < 16; j++) { - /* RTW_INFO("%02X ", data[i+j]); */ - sprintf(extra, "%s%02X ", extra, PROMContent[i + j]); - } - /* RTW_INFO("\n"); */ - sprintf(extra, "%s\n", extra); + for (i = 0; i < cnt; i += 16) { + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); + for (j = 0; j < 8; j++) + pextra += sprintf(pextra, "%02X ", efuse[i + j]); + pextra += sprintf(pextra, "\t"); + for (; j < 16; j++) + pextra += sprintf(pextra, "%02X ", efuse[i + j]); + pextra += sprintf(pextra, "\n"); } - /* RTW_INFO("\n"); */ + if ((shift + cnt) < mapLen) + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); + } else if (strcmp(tmp[0], "realmap") == 0) { static u8 order = 0; u8 *efuse; @@ -8987,16 +9205,17 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 0; i < cnt; i += 16) { - sprintf(extra, "%s0x%02x\t", extra, shift + i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); for (j = 0; j < 8; j++) - sprintf(extra, "%s%02X ", extra, efuse[i + j]); - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "%02X ", efuse[i + j]); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) - sprintf(extra, "%s%02X ", extra, efuse[i + j]); - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "%02X ", efuse[i + j]); + pextra += sprintf(pextra, "\n"); } if ((shift + cnt) < mapLen) - sprintf(extra, "%s\t...more\n", extra); + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); } else if (strcmp(tmp[0], "rmap") == 0) { if ((tmp[1] == NULL) || (tmp[2] == NULL)) { RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); @@ -9031,15 +9250,20 @@ static int rtw_mp_efuse_get(struct net_device *dev, /* RTW_INFO("%s: data={", __FUNCTION__); */ *extra = 0; + pextra = extra; for (i = 0; i < cnts; i++) { /* RTW_INFO("0x%02x ", data[i]); */ - sprintf(extra, "%s0x%02X ", extra, data[i]); + pextra += sprintf(pextra, "0x%02X ", data[i]); } /* RTW_INFO("}\n"); */ } else if (strcmp(tmp[0], "realraw") == 0) { + static u8 raw_order = 0; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + addr = 0; - mapLen = EFUSE_MAX_SIZE; - RTW_INFO("EFUSE_MAX_SIZE = %d\n", EFUSE_MAX_SIZE); + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN , (PVOID)&mapLen, _FALSE); + RTW_INFO("Real content len = %d\n",mapLen ); if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) { RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__); @@ -9047,52 +9271,79 @@ static int rtw_mp_efuse_get(struct net_device *dev, goto exit; } - if (mapLen >= 512) - mapLen = 512; - _rtw_memset(extra, '\0', strlen(extra)); - sprintf(extra, "\n0x00\t"); + shift = blksz * raw_order; + rawdata += shift; + cnt = mapLen - shift; + if (cnt > blksz) { + cnt = blksz; + raw_order++; + } else + raw_order = 0; - for (i = 0; i < mapLen ; i++) { - sprintf(extra, "%s%02X", extra, rawdata[i]); - if ((i & 0xF) == 0xF) { - sprintf(extra, "%s\n", extra); - sprintf(extra, "%s0x%02x\t", extra, i + 1); - } else if ((i & 0x7) == 0x7) - sprintf(extra, "%s \t", extra); - else - sprintf(extra, "%s ", extra); + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); + for (j = 0; j < 8; j++) + pextra += sprintf(pextra, "%02X ", rawdata[i + j]); + pextra += sprintf(pextra, "\t"); + for (; j < 16; j++) + pextra += sprintf(pextra, "%02X ", rawdata[i + j]); + pextra += sprintf(pextra, "\n"); } + if ((shift + cnt) < mapLen) + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); + + } else if (strcmp(tmp[0], "btrealraw") == 0) { + static u8 bt_raw_order = 0; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ - } else if (strcmp(tmp[0], "realrawb") == 0) { addr = 0; - mapLen = EFUSE_MAX_SIZE; - RTW_INFO("EFUSE_MAX_SIZE =%d\n", EFUSE_MAX_SIZE); + EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&mapLen, _FALSE); + RTW_INFO("Real content len = %d\n", mapLen); +#ifdef RTW_HALMAC + if (rtw_efuse_bt_access(padapter, _FALSE, 0, mapLen, rawdata) == _FAIL) { + RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__); + err = -EFAULT; + goto exit; + } +#else + rtw_write8(padapter, 0x35, 0x1); + if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) { - RTW_INFO("%s: rtw_efuse_access Fail!!\n", __FUNCTION__); + RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__); err = -EFAULT; goto exit; } +#endif _rtw_memset(extra, '\0', strlen(extra)); - /* RTW_INFO("%s: realraw={\n", __FUNCTION__); */ - sprintf(extra, "\n0x00\t"); - for (i = 512; i < mapLen; i++) { - /* RTW_INFO("%02X", rawdata[i]); */ - sprintf(extra, "%s%02X", extra, rawdata[i]); - if ((i & 0xF) == 0xF) { - /* RTW_INFO("\n"); */ - sprintf(extra, "%s\n", extra); - sprintf(extra, "%s0x%02x\t", extra, i + 1); - } else if ((i & 0x7) == 0x7) { - /* RTW_INFO("\t"); */ - sprintf(extra, "%s \t", extra); - } else { - /* RTW_INFO(" "); */ - sprintf(extra, "%s ", extra); - } + + shift = blksz * bt_raw_order; + rawdata += shift; + cnt = mapLen - shift; + if (cnt > blksz) { + cnt = blksz; + bt_raw_order++; + } else + bt_raw_order = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); + for (j = 0; j < 8; j++) + pextra += sprintf(pextra, "%02X ", rawdata[i + j]); + pextra += sprintf(pextra, "\t"); + for (; j < 16; j++) + pextra += sprintf(pextra, "%02X ", rawdata[i + j]); + pextra += sprintf(pextra, "\n"); } - /* RTW_INFO("}\n"); */ + if ((shift + cnt) < mapLen) + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); + } else if (strcmp(tmp[0], "mac") == 0) { if (hal_efuse_macaddr_offset(padapter) == -1) { err = -EFAULT; @@ -9117,12 +9368,13 @@ static int rtw_mp_efuse_get(struct net_device *dev, /* RTW_INFO("%s: MAC address={", __FUNCTION__); */ *extra = 0; + pextra = extra; for (i = 0; i < cnts; i++) { /* RTW_INFO("%02X", data[i]); */ - sprintf(extra, "%s%02X", extra, data[i]); + pextra += sprintf(pextra, "%02X", data[i]); if (i != (cnts - 1)) { /* RTW_INFO(":"); */ - sprintf(extra, "%s:", extra); + pextra += sprintf(pextra, ":"); } } /* RTW_INFO("}\n"); */ @@ -9180,18 +9432,23 @@ static int rtw_mp_efuse_get(struct net_device *dev, /* RTW_INFO("%s: {VID,PID}={", __FUNCTION__); */ *extra = 0; + pextra = extra; for (i = 0; i < cnts; i++) { /* RTW_INFO("0x%02x", data[i]); */ - sprintf(extra, "%s0x%02X", extra, data[i]); + pextra += sprintf(pextra, "0x%02X", data[i]); if (i != (cnts - 1)) { /* RTW_INFO(","); */ - sprintf(extra, "%s,", extra); + pextra += sprintf(pextra, ","); } } /* RTW_INFO("}\n"); */ } else if (strcmp(tmp[0], "ableraw") == 0) { +#ifdef RTW_HALMAC + raw_maxsize = efuse_GetavailableSize(padapter); +#else efuse_GetCurrentSize(padapter, &raw_cursize); raw_maxsize = efuse_GetMaxSize(padapter); +#endif sprintf(extra, "[available raw size]= %d bytes\n", raw_maxsize - raw_cursize); } else if (strcmp(tmp[0], "btableraw") == 0) { efuse_bt_GetCurrentSize(padapter, &raw_cursize); @@ -9212,19 +9469,20 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 0; i < 512; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */ /* RTW_INFO("0x%03x\t", i); */ - sprintf(extra, "%s0x%03x\t", extra, i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%03x\t", i); for (j = 0; j < 8; j++) { /* RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]); } /* RTW_INFO("\t"); */ - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) { /* RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]); } /* RTW_INFO("\n"); */ - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "\n"); } /* RTW_INFO("\n"); */ } else if (strcmp(tmp[0], "btbmap") == 0) { @@ -9241,22 +9499,34 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 512; i < 1024 ; i += 16) { /* RTW_INFO("0x%03x\t", i); */ - sprintf(extra, "%s0x%03x\t", extra, i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%03x\t", i); for (j = 0; j < 8; j++) { /* RTW_INFO("%02X ", data[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]); } /* RTW_INFO("\t"); */ - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) { /* RTW_INFO("%02X ", data[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]); } /* RTW_INFO("\n"); */ - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "\n"); } /* RTW_INFO("\n"); */ } else if (strcmp(tmp[0], "btrmap") == 0) { + u8 BTStatus; + + rtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */ + BTStatus = rtw_read8(padapter, 0xa0); + + RTW_INFO("%s: Check 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus); + if (BTStatus != 0x04) { + sprintf(extra, "BT Status not Active ,can't to read BT eFuse\n"); + goto exit; + } + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { err = -EINVAL; goto exit; @@ -9275,14 +9545,14 @@ static int rtw_mp_efuse_get(struct net_device *dev, goto exit; } RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); - +#ifndef RTW_HALMAC EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE); if ((addr + cnts) > max_available_len) { RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); err = -EFAULT; goto exit; } - +#endif if (rtw_BT_efuse_map_read(padapter, addr, cnts, data) == _FAIL) { RTW_INFO("%s: rtw_BT_efuse_map_read error!!\n", __FUNCTION__); err = -EFAULT; @@ -9290,10 +9560,11 @@ static int rtw_mp_efuse_get(struct net_device *dev, } *extra = 0; + pextra = extra; /* RTW_INFO("%s: bt efuse data={", __FUNCTION__); */ for (i = 0; i < cnts; i++) { /* RTW_INFO("0x%02x ", data[i]); */ - sprintf(extra, "%s 0x%02X ", extra, data[i]); + pextra += sprintf(pextra, " 0x%02X ", data[i]); } /* RTW_INFO("}\n"); */ RTW_INFO(FUNC_ADPT_FMT ": BT MAC=[%s]\n", FUNC_ADPT_ARG(padapter), extra); @@ -9302,19 +9573,20 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 0; i < 512; i += 16) { /* RTW_INFO("0x%03x\t", i); */ - sprintf(extra, "%s0x%03x\t", extra, i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%03x\t", i); for (j = 0; j < 8; j++) { /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); } /* RTW_INFO("\t"); */ - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) { /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); } /* RTW_INFO("\n"); */ - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "\n"); } /* RTW_INFO("\n"); */ } else if (strcmp(tmp[0], "btbfake") == 0) { @@ -9322,19 +9594,20 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 512; i < 1024; i += 16) { /* RTW_INFO("0x%03x\t", i); */ - sprintf(extra, "%s0x%03x\t", extra, i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%03x\t", i); for (j = 0; j < 8; j++) { /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); } /* RTW_INFO("\t"); */ - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) { /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); } /* RTW_INFO("\n"); */ - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "\n"); } /* RTW_INFO("\n"); */ } else if (strcmp(tmp[0], "wlrfkmap") == 0) { @@ -9357,16 +9630,17 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 0; i < cnt; i += 16) { - sprintf(extra, "%s0x%02x\t", extra, shift + i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); for (j = 0; j < 8; j++) - sprintf(extra, "%s%02X ", extra, efuse[i + j]); - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "%02X ", efuse[i + j]); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) - sprintf(extra, "%s%02X ", extra, efuse[i + j]); - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "%02X ", efuse[i + j]); + pextra += sprintf(pextra, "\n"); } if ((shift + cnt) < mapLen) - sprintf(extra, "%s\t...more\n", extra); + pextra += sprintf(pextra, "\t...more\n"); } else if (strcmp(tmp[0], "wlrfkrmap") == 0) { if ((tmp[1] == NULL) || (tmp[2] == NULL)) { @@ -9388,9 +9662,10 @@ static int rtw_mp_efuse_get(struct net_device *dev, /* RTW_INFO("%s: data={", __FUNCTION__); */ *extra = 0; + pextra = extra; for (i = 0; i < cnts; i++) { RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeEfuseModifiedMap[addr + i]); - sprintf(extra, "%s0x%02X ", extra, pEfuseHal->fakeEfuseModifiedMap[addr + i]); + pextra += sprintf(pextra, "0x%02X ", pEfuseHal->fakeEfuseModifiedMap[addr+i]); } } else if (strcmp(tmp[0], "btrfkrmap") == 0) { if ((tmp[1] == NULL) || (tmp[2] == NULL)) { @@ -9412,10 +9687,24 @@ static int rtw_mp_efuse_get(struct net_device *dev, /* RTW_INFO("%s: data={", __FUNCTION__); */ *extra = 0; + pextra = extra; for (i = 0; i < cnts; i++) { RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeBTEfuseModifiedMap[addr + i]); - sprintf(extra, "%s0x%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[addr + i]); + pextra += sprintf(pextra, "0x%02X ", pEfuseHal->fakeBTEfuseModifiedMap[addr+i]); } + } else if (strcmp(tmp[0], "mask") == 0) { + *extra = 0; + mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(padapter); + rtw_efuse_mask_array(padapter, mask_buf); + + if (padapter->registrypriv.bFileMaskEfuse == _TRUE) + _rtw_memcpy(mask_buf, maskfileBuffer, mask_len); + + sprintf(extra, "\n"); + pextra = extra + strlen(extra); + for (i = 0; i < mask_len; i++) + pextra += sprintf(pextra, "0x%02X\n", mask_buf[i]); + } else sprintf(extra, "Command not found!"); @@ -9444,13 +9733,16 @@ static int rtw_mp_efuse_get(struct net_device *dev, } static int rtw_mp_efuse_set(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wdata, char *extra) { + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ struct iw_point *wrqu; PADAPTER padapter; struct pwrctrl_priv *pwrctrlpriv ; PHAL_DATA_TYPE pHalData; PEFUSE_HAL pEfuseHal; + struct hal_ops *pHalFunc; + struct mp_priv *pmp_priv; u8 ips_mode = IPS_NUM; /* init invalid value */ u8 lps_mode = PS_MODE_NUM; /* init invalid value */ @@ -9469,6 +9761,9 @@ static int rtw_mp_efuse_set(struct net_device *dev, pwrctrlpriv = adapter_to_pwrctl(padapter); pHalData = GET_HAL_DATA(padapter); pEfuseHal = &pHalData->EfuseHal; + pHalFunc = &padapter->hal_func; + pmp_priv = &padapter->mppriv; + err = 0; if (copy_from_user(extra, wrqu->pointer, wrqu->length)) @@ -9995,6 +10290,15 @@ static int rtw_mp_efuse_set(struct net_device *dev, #endif } else if (strcmp(tmp[0], "wlfk2map") == 0) { + *extra = 0; + + if (padapter->registrypriv.bFileMaskEfuse != _TRUE && pmp_priv->bloadefusemap == _TRUE) { + RTW_INFO("%s: File eFuse mask file not to be loaded\n", __FUNCTION__); + sprintf(extra, "Not load eFuse mask file yet, Please use the efuse_mask CMD.\n"); + err = 0; + goto exit; + } + if (wifimaplen > EFUSE_MAX_MAP_LEN) cnts = EFUSE_MAX_MAP_LEN; else @@ -10004,7 +10308,7 @@ static int rtw_mp_efuse_set(struct net_device *dev, err = -EFAULT; goto exit; } - *extra = 0; + if (rtw_efuse_mask_map_read(padapter, 0x00, wifimaplen, ShadowMapWiFi) == _SUCCESS) { if (_rtw_memcmp((void *)ShadowMapWiFi , (void *)pEfuseHal->fakeEfuseModifiedMap, cnts)) { RTW_INFO("%s: WiFi write map afterf compare OK\n", __FUNCTION__); @@ -10047,7 +10351,8 @@ static int rtw_mp_efuse_set(struct net_device *dev, _rtw_memset(extra, '\0', strlen(extra)); sprintf(extra, "wlwfake OK\n"); - } else if (strcmp(tmp[0], "wfakemac") == 0) { + } + else if (strcmp(tmp[0], "wfakemac") == 0) { if (tmp[1] == NULL) { err = -EINVAL; goto exit; @@ -10084,8 +10389,35 @@ static int rtw_mp_efuse_set(struct net_device *dev, _rtw_memset(extra, '\0', strlen(extra)); sprintf(extra, "write mac addr to fake map OK\n"); - } + } else if(strcmp(tmp[0], "update") == 0) { + RTW_INFO("To Use new eFuse map\n"); + /*step read efuse/eeprom data and get mac_addr*/ + rtw_hal_read_chip_info(padapter); + /* set mac addr*/ + rtw_macaddr_cfg(adapter_mac_addr(padapter), get_hal_mac_addr(padapter)); + _rtw_memcpy(padapter->pnetdev->dev_addr, get_hal_mac_addr(padapter), ETH_ALEN); /* set mac addr to net_device */ +#ifdef CONFIG_P2P + rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); +#endif +#ifdef CONFIG_MI_WITH_MBSSID_CAM + rtw_hal_change_macaddr_mbid(padapter, adapter_mac_addr(padapter)); +#else + rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */ +#endif + /*pHalFunc->hal_deinit(padapter);*/ + if (pHalFunc->hal_init(padapter) == _FAIL) { + err = -EINVAL; + goto exit; + } + _rtw_memset(extra, '\0', strlen(extra)); + sprintf(extra, "eFuse Update OK\n"); + } else if (strcmp(tmp[0], "analyze") == 0) { + + rtw_efuse_analyze(padapter, EFUSE_WIFI, 0); + _rtw_memset(extra, '\0', strlen(extra)); + sprintf(extra, "eFuse Analyze OK,please to check kernel log\n"); + } exit: if (setdata) rtw_mfree(setdata, 1024); @@ -10111,36 +10443,122 @@ static int rtw_mp_efuse_set(struct net_device *dev, return err; } - #ifdef CONFIG_MP_INCLUDED + +#ifdef CONFIG_RTW_CUSTOMER_STR +static int rtw_mp_customer_str( + struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *adapter = rtw_netdev_priv(dev); + u32 len; + u8 *pbuf = NULL, *pch; + char *ptmp; + u8 param[RTW_CUSTOMER_STR_LEN]; + u8 count = 0; + u8 tmp; + u8 i; + u32 pos; + u8 ret; + u8 read = 0; + + if (adapter->registrypriv.mp_mode != 1 + || !adapter->registrypriv.mp_customer_str) + return -EFAULT; + + len = wrqu->data.length; + + pbuf = (u8 *)rtw_zmalloc(len); + if (pbuf == NULL) { + RTW_WARN("%s: no memory!\n", __func__); + return -ENOMEM; + } + + if (copy_from_user(pbuf, wrqu->data.pointer, len)) { + rtw_mfree(pbuf, len); + RTW_WARN("%s: copy from user fail!\n", __func__); + return -EFAULT; + } + RTW_INFO("%s: string=\"%s\"\n", __func__, pbuf); + + ptmp = (char *)pbuf; + pch = strsep(&ptmp, ","); + if ((pch == NULL) || (strlen(pch) == 0)) { + rtw_mfree(pbuf, len); + RTW_INFO("%s: parameter error(no cmd)!\n", __func__); + return -EFAULT; + } + + _rtw_memset(param, 0xFF, RTW_CUSTOMER_STR_LEN); + + if (strcmp(pch, "read") == 0) { + read = 1; + ret = rtw_hal_customer_str_read(adapter, param); + + } else if (strcmp(pch, "write") == 0) { + do { + pch = strsep(&ptmp, ":"); + if ((pch == NULL) || (strlen(pch) == 0)) + break; + if (strlen(pch) != 2 + || IsHexDigit(*pch) == _FALSE + || IsHexDigit(*(pch + 1)) == _FALSE + || sscanf(pch, "%hhx", &tmp) != 1 + ) { + RTW_WARN("%s: invalid 8-bit hex!\n", __func__); + rtw_mfree(pbuf, len); + return -EFAULT; + } + + param[count++] = tmp; + + } while (count < RTW_CUSTOMER_STR_LEN); + + if (count == 0) { + rtw_mfree(pbuf, len); + RTW_WARN("%s: no input!\n", __func__); + return -EFAULT; + } + ret = rtw_hal_customer_str_write(adapter, param); + } else { + rtw_mfree(pbuf, len); + RTW_INFO("%s: parameter error(unknown cmd)!\n", __func__); + return -EFAULT; + } + + pos = sprintf(extra, "%s: ", read ? "read" : "write"); + if (read == 0 || ret == _SUCCESS) { + for (i = 0; i < RTW_CUSTOMER_STR_LEN; i++) + pos += sprintf(extra + pos, "%02x:", param[i]); + extra[pos] = 0; + pos--; + } + pos += sprintf(extra + pos, " %s", ret == _SUCCESS ? "OK" : "FAIL"); + + wrqu->data.length = strlen(extra) + 1; + +free_buf: + rtw_mfree(pbuf, len); + return 0; +} +#endif /* CONFIG_RTW_CUSTOMER_STR */ + static int rtw_priv_mp_set(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wdata, char *extra) { + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ struct iw_point *wrqu = (struct iw_point *)wdata; u32 subcmd = wrqu->flags; + PADAPTER padapter = rtw_netdev_priv(dev); + + if (!is_primary_adapter(padapter)) { + RTW_INFO("MP mode only primary Adapter support\n"); + return -EIO; + } switch (subcmd) { - case MP_START: - RTW_INFO("set case mp_start\n"); - rtw_mp_start(dev, info, wrqu, extra); - break; - case MP_STOP: - RTW_INFO("set case mp_stop\n"); - rtw_mp_stop(dev, info, wrqu, extra); - break; - case MP_BANDWIDTH: - RTW_INFO("set case mp_bandwidth\n"); - rtw_mp_bandwidth(dev, info, wrqu, extra); - break; - case MP_RESET_STATS: - RTW_INFO("set case MP_RESET_STATS\n"); - rtw_mp_reset_stats(dev, info, wrqu, extra); - break; - case MP_SetRFPathSwh: - RTW_INFO("set MP_SetRFPathSwitch\n"); - rtw_mp_SetRFPath(dev, info, wdata, extra); - break; case CTA_TEST: RTW_INFO("set CTA_TEST\n"); rtw_cta_test_start(dev, info, wdata, extra); @@ -10149,6 +10567,15 @@ static int rtw_priv_mp_set(struct net_device *dev, RTW_INFO("set case MP_DISABLE_BT_COEXIST\n"); rtw_mp_disable_bt_coexist(dev, info, wdata, extra); break; + case MP_IQK: + RTW_INFO("set MP_IQK\n"); + rtw_mp_iqk(dev, info, wrqu, extra); + break; + case MP_LCK: + RTW_INFO("set MP_LCK\n"); + rtw_mp_lck(dev, info, wrqu, extra); + break; + default: return -EIO; } @@ -10157,13 +10584,40 @@ static int rtw_priv_mp_set(struct net_device *dev, } static int rtw_priv_mp_get(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wdata, char *extra) { + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ struct iw_point *wrqu = (struct iw_point *)wdata; u32 subcmd = wrqu->flags; + PADAPTER padapter = rtw_netdev_priv(dev); + + if (!is_primary_adapter(padapter)) { + RTW_INFO("MP mode only primary Adapter support\n"); + return -EIO; + } switch (subcmd) { + case MP_START: + RTW_INFO("set case mp_start\n"); + rtw_mp_start(dev, info, wrqu, extra); + break; + case MP_STOP: + RTW_INFO("set case mp_stop\n"); + rtw_mp_stop(dev, info, wrqu, extra); + break; + case MP_BANDWIDTH: + RTW_INFO("set case mp_bandwidth\n"); + rtw_mp_bandwidth(dev, info, wrqu, extra); + break; + case MP_RESET_STATS: + RTW_INFO("set case MP_RESET_STATS\n"); + rtw_mp_reset_stats(dev, info, wrqu, extra); + break; + case MP_SetRFPathSwh: + RTW_INFO("set MP_SetRFPathSwitch\n"); + rtw_mp_SetRFPath(dev, info, wrqu, extra); + break; case WRITE_REG: rtw_mp_write_reg(dev, info, wrqu, extra); break; @@ -10277,6 +10731,20 @@ static int rtw_priv_mp_get(struct net_device *dev, RTW_INFO("mp_get MP_HW_TX_MODE\n"); rtw_mp_hwtx(dev, info, wdata, extra); break; +#ifdef CONFIG_RTW_CUSTOMER_STR + case MP_CUSTOMER_STR: + RTW_INFO("customer str\n"); + rtw_mp_customer_str(dev, info, wdata, extra); + break; +#endif + case MP_PWRLMT: + RTW_INFO("mp_get MP_SETPWRLMT\n"); + rtw_mp_pwrlmt(dev, info, wdata, extra); + break; + case MP_PWRBYRATE: + RTW_INFO("mp_get MP_SETPWRBYRATE\n"); + rtw_mp_pwrbyrate(dev, info, wdata, extra); + break; default: return -EIO; } @@ -10289,9 +10757,10 @@ static int rtw_priv_mp_get(struct net_device *dev, #ifdef CONFIG_SDIO_INDIRECT_ACCESS #define DBG_MP_SDIO_INDIRECT_ACCESS 1 static int rtw_mp_sd_iread(struct net_device *dev - , struct iw_request_info *info - , struct iw_point *wrqu - , char *extra) { + , struct iw_request_info *info + , struct iw_point *wrqu + , char *extra) +{ char input[16]; u8 width; unsigned long addr; @@ -10351,9 +10820,10 @@ static int rtw_mp_sd_iread(struct net_device *dev } static int rtw_mp_sd_iwrite(struct net_device *dev - , struct iw_request_info *info - , struct iw_point *wrqu - , char *extra) { + , struct iw_request_info *info + , struct iw_point *wrqu + , char *extra) +{ char width; unsigned long addr, data; int ret = 0; @@ -10419,8 +10889,9 @@ static int rtw_mp_sd_iwrite(struct net_device *dev #endif /* CONFIG_SDIO_INDIRECT_ACCESS */ static int rtw_priv_set(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wdata, char *extra) { + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ struct iw_point *wrqu = (struct iw_point *)wdata; u32 subcmd = wrqu->flags; PADAPTER padapter = rtw_netdev_priv(dev); @@ -10444,7 +10915,9 @@ static int rtw_priv_set(struct net_device *dev, } if (subcmd < MP_NULL) { +#ifdef CONFIG_MP_INCLUDED rtw_priv_mp_set(dev, info, wdata, extra); +#endif return 0; } @@ -10481,8 +10954,9 @@ static int rtw_priv_set(struct net_device *dev, static int rtw_priv_get(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wdata, char *extra) { + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ struct iw_point *wrqu = (struct iw_point *)wdata; u32 subcmd = wrqu->flags; PADAPTER padapter = rtw_netdev_priv(dev); @@ -10507,7 +10981,9 @@ static int rtw_priv_get(struct net_device *dev, } if (subcmd < MP_NULL) { +#ifdef CONFIG_MP_INCLUDED rtw_priv_mp_get(dev, info, wdata, extra); +#endif return 0; } @@ -10543,8 +11019,9 @@ static int rtw_priv_get(struct net_device *dev, static int rtw_wx_tdls_wfd_enable(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -10566,8 +11043,9 @@ static int rtw_wx_tdls_wfd_enable(struct net_device *dev, } static int rtw_tdls_weaksec(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -10589,8 +11067,9 @@ static int rtw_tdls_weaksec(struct net_device *dev, static int rtw_tdls_enable(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -10651,8 +11130,9 @@ static int rtw_tdls_enable(struct net_device *dev, } static int rtw_tdls_setup(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS u8 i, j; @@ -10679,7 +11159,7 @@ static int rtw_tdls_setup(struct net_device *dev, if (0 == pwdinfo->wfd_tdls_weaksec) { /* Can't send the tdls setup request out!! */ RTW_INFO("[%s] Current link is not AES, " - "SKIP sending the tdls setup request!!\n", __FUNCTION__); + "SKIP sending the tdls setup request!!\n", __FUNCTION__); } else issue_tdls_setup_req(padapter, &txmgmt, _TRUE); } else @@ -10693,8 +11173,9 @@ static int rtw_tdls_setup(struct net_device *dev, } static int rtw_tdls_teardown(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -10708,7 +11189,7 @@ static int rtw_tdls_teardown(struct net_device *dev, if (wrqu->data.length - 1 != 17 && wrqu->data.length - 1 != 19) { RTW_INFO("[%s] length:%d != 17 or 19\n", - __FUNCTION__, (wrqu->data.length - 1)); + __FUNCTION__, (wrqu->data.length - 1)); return ret; } @@ -10732,8 +11213,9 @@ static int rtw_tdls_teardown(struct net_device *dev, } static int rtw_tdls_discovery(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -10756,8 +11238,9 @@ static int rtw_tdls_discovery(struct net_device *dev, } static int rtw_tdls_ch_switch(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -10816,8 +11299,9 @@ static int rtw_tdls_ch_switch(struct net_device *dev, } static int rtw_tdls_ch_switch_off(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -10850,8 +11334,8 @@ static int rtw_tdls_ch_switch_off(struct net_device *dev, rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL); pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE | - TDLS_CH_SWITCH_ON_STATE | - TDLS_PEER_AT_OFF_STATE); + TDLS_CH_SWITCH_ON_STATE | + TDLS_PEER_AT_OFF_STATE); _rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN); ptdls_sta->ch_switch_time = 0; @@ -10869,8 +11353,9 @@ static int rtw_tdls_ch_switch_off(struct net_device *dev, } static int rtw_tdls_dump_ch(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -10892,8 +11377,9 @@ static int rtw_tdls_dump_ch(struct net_device *dev, } static int rtw_tdls_off_ch_num(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -10915,8 +11401,9 @@ static int rtw_tdls_off_ch_num(struct net_device *dev, } static int rtw_tdls_ch_offset(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -10950,8 +11437,9 @@ static int rtw_tdls_ch_offset(struct net_device *dev, } static int rtw_tdls_pson(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -10975,8 +11463,9 @@ static int rtw_tdls_pson(struct net_device *dev, } static int rtw_tdls_psoff(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -11001,8 +11490,9 @@ static int rtw_tdls_psoff(struct net_device *dev, } static int rtw_tdls_setip(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -11033,10 +11523,10 @@ static int rtw_tdls_setip(struct net_device *dev, } RTW_INFO("[%s] Set IP = %u.%u.%u.%u\n", __FUNCTION__, - ptdlsinfo->wfd_info->ip_address[0], - ptdlsinfo->wfd_info->ip_address[1], - ptdlsinfo->wfd_info->ip_address[2], - ptdlsinfo->wfd_info->ip_address[3]); + ptdlsinfo->wfd_info->ip_address[0], + ptdlsinfo->wfd_info->ip_address[1], + ptdlsinfo->wfd_info->ip_address[2], + ptdlsinfo->wfd_info->ip_address[3]); #endif /* CONFIG_WFD */ #endif /* CONFIG_TDLS */ @@ -11045,8 +11535,9 @@ static int rtw_tdls_setip(struct net_device *dev, } static int rtw_tdls_getip(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -11059,12 +11550,12 @@ static int rtw_tdls_getip(struct net_device *dev, RTW_INFO("[%s]\n", __FUNCTION__); sprintf(extra, "\n\n%u.%u.%u.%u\n", - pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1], - pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]); + pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1], + pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]); RTW_INFO("[%s] IP=%u.%u.%u.%u\n", __FUNCTION__, - pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1], - pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]); + pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1], + pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]); wrqu->data.length = strlen(extra); @@ -11075,8 +11566,9 @@ static int rtw_tdls_getip(struct net_device *dev, } static int rtw_tdls_getport(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; @@ -11091,7 +11583,7 @@ static int rtw_tdls_getport(struct net_device *dev, sprintf(extra, "\n\n%d\n", pwfd_info->peer_rtsp_ctrlport); RTW_INFO("[%s] remote port = %d\n", - __FUNCTION__, pwfd_info->peer_rtsp_ctrlport); + __FUNCTION__, pwfd_info->peer_rtsp_ctrlport); wrqu->data.length = strlen(extra); @@ -11104,8 +11596,9 @@ static int rtw_tdls_getport(struct net_device *dev, /* WFDTDLS, for sigma test */ static int rtw_tdls_dis_result(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; @@ -11133,8 +11626,9 @@ static int rtw_tdls_dis_result(struct net_device *dev, /* WFDTDLS, for sigma test */ static int rtw_wfd_tdls_status(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; @@ -11146,30 +11640,30 @@ static int rtw_wfd_tdls_status(struct net_device *dev, RTW_INFO("[%s]\n", __FUNCTION__); sprintf(extra, "\nlink_established:%d\n" - "sta_cnt:%d\n" - "sta_maximum:%d\n" - "cur_channel:%d\n" - "tdls_enable:%d" + "sta_cnt:%d\n" + "sta_maximum:%d\n" + "cur_channel:%d\n" + "tdls_enable:%d" #ifdef CONFIG_TDLS_CH_SW - "ch_sw_state:%08x\n" - "chsw_on:%d\n" - "off_ch_num:%d\n" - "cur_time:%d\n" - "ch_offset:%d\n" - "delay_swtich_back:%d" -#endif - , - ptdlsinfo->link_established, ptdlsinfo->sta_cnt, - ptdlsinfo->sta_maximum, ptdlsinfo->cur_channel, - ptdlsinfo->tdls_enable + "ch_sw_state:%08x\n" + "chsw_on:%d\n" + "off_ch_num:%d\n" + "cur_time:%d\n" + "ch_offset:%d\n" + "delay_swtich_back:%d" +#endif + , + ptdlsinfo->link_established, ptdlsinfo->sta_cnt, + ptdlsinfo->sta_maximum, ptdlsinfo->cur_channel, + ptdlsinfo->tdls_enable #ifdef CONFIG_TDLS_CH_SW - , - ptdlsinfo->chsw_info.ch_sw_state, - ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on), - ptdlsinfo->chsw_info.off_ch_num, - ptdlsinfo->chsw_info.cur_time, - ptdlsinfo->chsw_info.ch_offset, - ptdlsinfo->chsw_info.delay_switch_back + , + ptdlsinfo->chsw_info.ch_sw_state, + ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on), + ptdlsinfo->chsw_info.off_ch_num, + ptdlsinfo->chsw_info.cur_time, + ptdlsinfo->chsw_info.ch_offset, + ptdlsinfo->chsw_info.delay_switch_back #endif ); @@ -11182,8 +11676,9 @@ static int rtw_wfd_tdls_status(struct net_device *dev, } static int rtw_tdls_getsta(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -11194,7 +11689,7 @@ static int rtw_tdls_getsta(struct net_device *dev, struct sta_info *ptdls_sta = NULL; RTW_INFO("[%s] %s %d\n", __FUNCTION__, - (char *)wrqu->data.pointer, wrqu->data.length - 1); + (char *)wrqu->data.pointer, wrqu->data.length - 1); if (copy_from_user(charmac, wrqu->data.pointer + 9, 17)) { ret = -EFAULT; @@ -11206,7 +11701,7 @@ static int rtw_tdls_getsta(struct net_device *dev, addr[i] = key_2char2num(*(charmac + j), *(charmac + j + 1)); RTW_INFO("[%s] %d, charmac:%s, addr:"MAC_FMT"\n", - __FUNCTION__, __LINE__, charmac, MAC_ARG(addr)); + __FUNCTION__, __LINE__, charmac, MAC_ARG(addr)); ptdls_sta = rtw_get_stainfo(&padapter->stapriv, addr); if (ptdls_sta) { sprintf(extra, "\n\ntdls_sta_state=0x%08x\n", ptdls_sta->tdls_sta_state); @@ -11224,53 +11719,55 @@ static int rtw_tdls_getsta(struct net_device *dev, } static int rtw_tdls_get_best_ch(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ #ifdef CONFIG_FIND_BEST_CHANNEL _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0; - for (i = 0; pmlmeext->channel_set[i].ChannelNum != 0; i++) { - if (pmlmeext->channel_set[i].ChannelNum == 1) + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) { + if (rfctl->channel_set[i].ChannelNum == 1) index_24G = i; - if (pmlmeext->channel_set[i].ChannelNum == 36) + if (rfctl->channel_set[i].ChannelNum == 36) index_5G = i; } - for (i = 0; pmlmeext->channel_set[i].ChannelNum != 0; i++) { + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) { /* 2.4G */ - if (pmlmeext->channel_set[i].ChannelNum == 6 || pmlmeext->channel_set[i].ChannelNum == 11) { - if (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_24G].rx_count) { + if (rfctl->channel_set[i].ChannelNum == 6 || rfctl->channel_set[i].ChannelNum == 11) { + if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) { index_24G = i; - best_channel_24G = pmlmeext->channel_set[i].ChannelNum; + best_channel_24G = rfctl->channel_set[i].ChannelNum; } } /* 5G */ - if (pmlmeext->channel_set[i].ChannelNum >= 36 - && pmlmeext->channel_set[i].ChannelNum < 140) { + if (rfctl->channel_set[i].ChannelNum >= 36 + && rfctl->channel_set[i].ChannelNum < 140) { /* Find primary channel */ - if (((pmlmeext->channel_set[i].ChannelNum - 36) % 8 == 0) - && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count)) { + if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0) + && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) { index_5G = i; - best_channel_5G = pmlmeext->channel_set[i].ChannelNum; + best_channel_5G = rfctl->channel_set[i].ChannelNum; } } - if (pmlmeext->channel_set[i].ChannelNum >= 149 - && pmlmeext->channel_set[i].ChannelNum < 165) { + if (rfctl->channel_set[i].ChannelNum >= 149 + && rfctl->channel_set[i].ChannelNum < 165) { /* Find primary channel */ - if (((pmlmeext->channel_set[i].ChannelNum - 149) % 8 == 0) - && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count)) { + if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0) + && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) { index_5G = i; - best_channel_5G = pmlmeext->channel_set[i].ChannelNum; + best_channel_5G = rfctl->channel_set[i].ChannelNum; } } #if 1 /* debug */ RTW_INFO("The rx cnt of channel %3d = %d\n", - pmlmeext->channel_set[i].ChannelNum, - pmlmeext->channel_set[i].rx_count); + rfctl->channel_set[i].ChannelNum, + rfctl->channel_set[i].rx_count); #endif } @@ -11291,8 +11788,9 @@ static int rtw_tdls_get_best_ch(struct net_device *dev, } static int rtw_tdls(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -11380,8 +11878,9 @@ static int rtw_tdls(struct net_device *dev, static int rtw_tdls_get(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; #ifdef CONFIG_TDLS @@ -11412,8 +11911,9 @@ static int rtw_tdls_get(struct net_device *dev, #ifdef CONFIG_INTEL_WIDI static int rtw_widi_set(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -11423,8 +11923,9 @@ static int rtw_widi_set(struct net_device *dev, } static int rtw_widi_set_probe_request(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ int ret = 0; u8 *pbuf = NULL; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -11485,7 +11986,8 @@ extern void rtl8192es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbu #endif /* CONFIG_SDIO_HCI */ #endif /* CONFIG_RTL8192E */ -static s32 initLoopback(PADAPTER padapter) { +static s32 initLoopback(PADAPTER padapter) +{ PLOOPBACKDATA ploopback; @@ -11506,7 +12008,8 @@ static s32 initLoopback(PADAPTER padapter) { return 0; } -static void freeLoopback(PADAPTER padapter) { +static void freeLoopback(PADAPTER padapter) +{ PLOOPBACKDATA ploopback; @@ -11517,7 +12020,8 @@ static void freeLoopback(PADAPTER padapter) { } } -static s32 initpseudoadhoc(PADAPTER padapter) { +static s32 initpseudoadhoc(PADAPTER padapter) +{ NDIS_802_11_NETWORK_INFRASTRUCTURE networkType; s32 err; @@ -11533,7 +12037,8 @@ static s32 initpseudoadhoc(PADAPTER padapter) { return _SUCCESS; } -static s32 createpseudoadhoc(PADAPTER padapter) { +static s32 createpseudoadhoc(PADAPTER padapter) +{ NDIS_802_11_AUTHENTICATION_MODE authmode; struct mlme_priv *pmlmepriv; NDIS_802_11_SSID *passoc_ssid; @@ -11605,7 +12110,8 @@ static s32 createpseudoadhoc(PADAPTER padapter) { return _SUCCESS; } -static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size) { +static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size) +{ struct xmit_priv *pxmitpriv; struct xmit_frame *pframe; struct xmit_buf *pxmitbuf; @@ -11720,7 +12226,7 @@ static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size) { /* 3 5.1. make wlan header, make_wlanhdr() */ hdr = (struct rtw_ieee80211_hdr *)pkt_start; - SetFrameSubType(&hdr->frame_ctl, pattrib->subtype); + set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype); _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */ _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */ _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */ @@ -11735,7 +12241,8 @@ static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size) { return pframe; } -static void freeloopbackpkt(PADAPTER padapter, struct xmit_frame *pframe) { +static void freeloopbackpkt(PADAPTER padapter, struct xmit_frame *pframe) +{ struct xmit_priv *pxmitpriv; struct xmit_buf *pxmitbuf; @@ -11747,7 +12254,8 @@ static void freeloopbackpkt(PADAPTER padapter, struct xmit_frame *pframe) { rtw_free_xmitbuf(pxmitpriv, pxmitbuf); } -static void printdata(u8 *pbuf, u32 len) { +static void printdata(u8 *pbuf, u32 len) +{ u32 i, val; @@ -11783,7 +12291,8 @@ static void printdata(u8 *pbuf, u32 len) { printk("\n"); } -static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) { +static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) +{ PHAL_DATA_TYPE phal; struct recv_stat *prxstat; struct recv_stat report; @@ -11813,26 +12322,26 @@ static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) { if ((txsz - TXDESC_SIZE) != (rxpktsize - fcssize)) { RTW_INFO("%s: ERROR! size not match tx/rx=%d/%d !\n", - __func__, txsz - TXDESC_SIZE, rxpktsize - fcssize); + __func__, txsz - TXDESC_SIZE, rxpktsize - fcssize); ret = _FALSE; } else { ret = _rtw_memcmp(txbuf + TXDESC_SIZE, \ - rxbuf + RXDESC_SIZE + drvinfosize, \ - txsz - TXDESC_SIZE); + rxbuf + RXDESC_SIZE + drvinfosize, \ + txsz - TXDESC_SIZE); if (ret == _FALSE) RTW_INFO("%s: ERROR! pkt content mismatch!\n", __func__); } if (ret == _FALSE) { RTW_INFO("\n%s: TX PKT total=%d, desc=%d, content=%d\n", - __func__, txsz, TXDESC_SIZE, txsz - TXDESC_SIZE); + __func__, txsz, TXDESC_SIZE, txsz - TXDESC_SIZE); RTW_INFO("%s: TX DESC size=%d\n", __func__, TXDESC_SIZE); printdata(txbuf, TXDESC_SIZE); RTW_INFO("%s: TX content size=%d\n", __func__, txsz - TXDESC_SIZE); printdata(txbuf + TXDESC_SIZE, txsz - TXDESC_SIZE); RTW_INFO("\n%s: RX PKT read=%d offset=%d(%d,%d) content=%d\n", - __func__, rxsz, RXDESC_SIZE + drvinfosize, RXDESC_SIZE, drvinfosize, rxpktsize); + __func__, rxsz, RXDESC_SIZE + drvinfosize, RXDESC_SIZE, drvinfosize, rxpktsize); if (rxpktsize != 0) { RTW_INFO("%s: RX DESC size=%d\n", __func__, RXDESC_SIZE); printdata(rxbuf, RXDESC_SIZE); @@ -11849,7 +12358,8 @@ static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) { return ret; } -thread_return lbk_thread(thread_context context) { +thread_return lbk_thread(thread_context context) +{ s32 err; PADAPTER padapter; PLOOPBACKDATA ploopback; @@ -11908,28 +12418,29 @@ thread_return lbk_thread(thread_context context) { freeloopbackpkt(padapter, pxmitframe); pxmitframe = NULL; - if (signal_pending(current)) - flush_signals(current); + flush_signals_thread(); if ((ploopback->bstop == _TRUE) || - ((ploopback->cnt != 0) && (ploopback->cnt == cnt))) { + ((ploopback->cnt != 0) && (ploopback->cnt == cnt))) { u32 ok_rate, fail_rate, all; all = cnt; ok_rate = (ok * 100) / all; fail_rate = (fail * 100) / all; sprintf(ploopback->msg, \ - "loopback result: ok=%d%%(%d/%d),error=%d%%(%d/%d)", \ - ok_rate, ok, all, fail_rate, fail, all); + "loopback result: ok=%d%%(%d/%d),error=%d%%(%d/%d)", \ + ok_rate, ok, all, fail_rate, fail, all); break; } } while (1); ploopback->bstop = _TRUE; - thread_exit(); + thread_exit(NULL); + return 0; } -static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg) { +static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg) +{ PLOOPBACKDATA ploopback; u32 len; s32 err; @@ -11986,6 +12497,7 @@ static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg) { ploopback->lbkthread = kthread_run(lbk_thread, padapter, "RTW_LBK_THREAD"); if (IS_ERR(padapter->lbkthread)) { freeLoopback(padapter); + ploopback->lbkthread = NULL; sprintf(pmsg, "loopback start FAIL! cnt=%d", cnt); return; } @@ -11995,9 +12507,10 @@ static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg) { #endif /* CONFIG_MAC_LOOPBACK_DRIVER */ static int rtw_test( - struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) { + struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ u32 len; u8 *pbuf, *pch; char *ptmp; @@ -12320,13 +12833,13 @@ static const struct iw_priv_args rtw_private_args[] = { static const struct iw_priv_args rtw_mp_private_args[] = { /* --- sub-ioctls definitions --- */ #ifdef CONFIG_MP_INCLUDED - { MP_START , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_start" }, + { MP_START , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_start" }, { MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" }, - { MP_STOP , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_stop" }, + { MP_STOP , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_stop" }, { MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" }, - { MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_bandwidth"}, + { MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_bandwidth"}, { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, - { MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_reset_stats"}, + { MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_reset_stats"}, { MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"}, { READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" }, { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, @@ -12343,10 +12856,10 @@ static const struct iw_priv_args rtw_mp_private_args[] = { { MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"}, { EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_set" }, { EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" }, - { MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_pwrtrk"}, + { MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrtrk"}, { MP_QueryDrvStats, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_drvquery" }, { MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ioctl"}, - { MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_setrfpath" }, + { MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setrfpath" }, { MP_PwrCtlDM, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrctldm" }, { MP_GET_TXPOWER_INX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_txpower" }, { MP_GETVER, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_priv_ver" }, @@ -12356,7 +12869,15 @@ static const struct iw_priv_args rtw_mp_private_args[] = { { MP_TX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_tx" }, { MP_RX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rx" }, { MP_HW_TX_MODE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_hxtx" }, + { MP_PWRLMT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrlmt" }, + { MP_PWRBYRATE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrbyrate" }, { CTA_TEST, IW_PRIV_TYPE_CHAR | 1024, 0, "cta_test"}, + { MP_IQK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_iqk"}, + { MP_LCK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_lck"}, +#ifdef CONFIG_RTW_CUSTOMER_STR + { MP_CUSTOMER_STR, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "customer_str" }, +#endif + #endif /* CONFIG_MP_INCLUDED */ }; @@ -12419,7 +12940,8 @@ static iw_handler rtw_private_handler[] = { }; #if WIRELESS_EXT >= 17 -static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev) { +static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct iw_statistics *piwstats = &padapter->iwstats; int tmp_level = 0; @@ -12443,7 +12965,7 @@ static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev) { HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); - tmp_level = (u8)odm_SignalScaleMapping(&pHal->odmpriv, padapter->recvpriv.signal_strength); + tmp_level = (u8)odm_signal_scale_mapping(&pHal->odmpriv, padapter->recvpriv.signal_strength); } #endif #endif @@ -12509,7 +13031,8 @@ static const char iw_priv_type_size[] = { 0, /* Not defined */ }; -static int get_priv_size(__u16 args) { +static int get_priv_size(__u16 args) +{ int num = args & IW_PRIV_SIZE_MASK; int type = (args & IW_PRIV_TYPE_MASK) >> 12; @@ -12518,7 +13041,8 @@ static int get_priv_size(__u16 args) { /* copy from net/wireless/wext.c end */ -static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq_data) { +static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq_data) +{ int err = 0; u8 *input = NULL; u32 input_len = 0; @@ -12554,8 +13078,10 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq _rtw_memcpy(&wdata, wrq_data, sizeof(wdata)); input_len = wdata.data.length; + if (!input_len) + return -EINVAL; input = rtw_zmalloc(input_len); - if (NULL == input || input_len == 0) + if (NULL == input) return -ENOMEM; if (copy_from_user(input, wdata.data.pointer, input_len)) { err = -EFAULT; @@ -12622,8 +13148,8 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq /* Find the matching *real* ioctl */ while ((++j < num_priv_args) && ((priv_args[j].name[0] != '\0') || - (priv_args[j].set_args != sel_priv_args[k].set_args) || - (priv_args[j].get_args != sel_priv_args[k].get_args))) + (priv_args[j].set_args != sel_priv_args[k].set_args) || + (priv_args[j].get_args != sel_priv_args[k].get_args))) ; /* If not found... */ @@ -12648,7 +13174,7 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq /* If we have to set some data */ if ((priv_args[k].set_args & IW_PRIV_TYPE_MASK) && - (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) { + (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) { u8 *str; switch (priv_args[k].set_args & IW_PRIV_TYPE_MASK) { @@ -12713,9 +13239,9 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq } if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && - (wdata.data.length != (priv_args[k].set_args & IW_PRIV_SIZE_MASK))) { + (wdata.data.length != (priv_args[k].set_args & IW_PRIV_SIZE_MASK))) { RTW_INFO("%s: The command %s needs exactly %d argument(s)...\n", - __func__, cmdname, priv_args[k].set_args & IW_PRIV_SIZE_MASK); + __func__, cmdname, priv_args[k].set_args & IW_PRIV_SIZE_MASK); err = -EINVAL; goto exit; } @@ -12726,15 +13252,15 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq /* Those two tests are important. They define how the driver * will have to handle the data */ if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && - ((get_priv_size(priv_args[k].set_args) + offset) <= IFNAMSIZ)) { + ((get_priv_size(priv_args[k].set_args) + offset) <= IFNAMSIZ)) { /* First case : all SET args fit within wrq */ if (offset) wdata.mode = subcmd; _rtw_memcpy(wdata.name + offset, buffer, IFNAMSIZ - offset); } else { if ((priv_args[k].set_args == 0) && - (priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && - (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) { + (priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && + (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) { /* Second case : no SET args, GET args fit within wrq */ if (offset) wdata.mode = subcmd; @@ -12758,7 +13284,7 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq /* Does it fits in iwr ? */ if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && - ((extra_size + offset) <= IFNAMSIZ)) + ((extra_size + offset) <= IFNAMSIZ)) extra_size = 0; } else { /* Size of get arguments */ @@ -12766,7 +13292,7 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq /* Does it fits in iwr ? */ if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && - (extra_size <= IFNAMSIZ)) + (extra_size <= IFNAMSIZ)) extra_size = 0; } @@ -12782,14 +13308,14 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq /* If we have to get some data */ if ((priv_args[k].get_args & IW_PRIV_TYPE_MASK) && - (priv_args[k].get_args & IW_PRIV_SIZE_MASK)) { + (priv_args[k].get_args & IW_PRIV_SIZE_MASK)) { int j; int n = 0; /* number of args */ u8 str[20] = {0}; /* Check where is the returned data */ if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && - (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) + (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) n = priv_args[k].get_args & IW_PRIV_SIZE_MASK; else n = wdata.data.length; @@ -12862,7 +13388,8 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq } #ifdef CONFIG_COMPAT -static int rtw_ioctl_compat_wext_private(struct net_device *dev, struct ifreq *rq) { +static int rtw_ioctl_compat_wext_private(struct net_device *dev, struct ifreq *rq) +{ struct compat_iw_point iwp_compat; union iwreq_data wrq_data; int err = 0; @@ -12886,7 +13413,8 @@ static int rtw_ioctl_compat_wext_private(struct net_device *dev, struct ifreq *r } #endif /* CONFIG_COMPAT */ -static int rtw_ioctl_standard_wext_private(struct net_device *dev, struct ifreq *rq) { +static int rtw_ioctl_standard_wext_private(struct net_device *dev, struct ifreq *rq) +{ struct iw_point *iwp; struct ifreq ifrq; union iwreq_data wrq_data; @@ -12904,15 +13432,22 @@ static int rtw_ioctl_standard_wext_private(struct net_device *dev, struct ifreq return err; } -static int rtw_ioctl_wext_private(struct net_device *dev, struct ifreq *rq) { - +static int rtw_ioctl_wext_private(struct net_device *dev, struct ifreq *rq) +{ #ifdef CONFIG_COMPAT - return rtw_ioctl_compat_wext_private(dev, rq); +#if (KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE) + if (is_compat_task()) +#else + if (in_compat_syscall()) +#endif + return rtw_ioctl_compat_wext_private(dev, rq); + else #endif /* CONFIG_COMPAT */ - return rtw_ioctl_standard_wext_private(dev, rq); + return rtw_ioctl_standard_wext_private(dev, rq); } -int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { +int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ struct iwreq *wrq = (struct iwreq *)rq; int ret = 0; diff --git a/os_dep/linux/ioctl_mp.c b/os_dep/linux/ioctl_mp.c index ce3484d..f2a9418 100644 --- a/os_dep/linux/ioctl_mp.c +++ b/os_dep/linux/ioctl_mp.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #if defined(CONFIG_MP_INCLUDED) #include @@ -130,7 +125,7 @@ int rtw_mp_read_reg(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - char input[wrqu->length]; + char input[wrqu->length + 1]; char *pch, *pnext, *ptmp; char *width_str; char width; @@ -138,14 +133,16 @@ int rtw_mp_read_reg(struct net_device *dev, u32 addr = 0, strtout = 0; u32 i = 0, j = 0, ret = 0, data32 = 0; PADAPTER padapter = rtw_netdev_priv(dev); - + char *pextra = extra; if (wrqu->length > 128) return -EFAULT; + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; _rtw_memset(extra, 0, wrqu->length); _rtw_memset(data, '\0', sizeof(data)); _rtw_memset(tmp, '\0', sizeof(tmp)); @@ -198,7 +195,7 @@ int rtw_mp_read_reg(struct net_device *dev, if (*pnext != '\0') { /*strtout = simple_strtoul(pnext , &ptmp, 16);*/ ret = sscanf(pnext, "%x", &strtout); - sprintf(extra, "%s %d" , extra , strtout); + pextra += sprintf(pextra, " %d", strtout); } else break; pch = pnext; @@ -230,7 +227,7 @@ int rtw_mp_read_reg(struct net_device *dev, pnext++; if (*pnext != '\0') { ret = sscanf(pnext, "%x", &strtout); - sprintf(extra, "%s %d" , extra , strtout); + pextra += sprintf(pextra, " %d", strtout); } else break; pch = pnext; @@ -310,6 +307,7 @@ int rtw_mp_read_rf(struct net_device *dev, u32 path, addr, strtou; u32 ret, i = 0 , j = 0; PADAPTER padapter = rtw_netdev_priv(dev); + char *pextra = extra; if (wrqu->length > 128) return -EFAULT; @@ -349,7 +347,7 @@ int rtw_mp_read_rf(struct net_device *dev, if (*pnext != '\0') { /*strtou =simple_strtoul(pnext , &ptmp, 16);*/ ret = sscanf(pnext, "%x", &strtou); - sprintf(extra, "%s %d" , extra , strtou); + pextra += sprintf(pextra, " %d", strtou); } else break; pch = pnext; @@ -364,57 +362,26 @@ int rtw_mp_start(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { + int ret = 0; u8 val8; PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct hal_ops *pHalFunc = &padapter->HalFunc; + struct hal_ops *pHalFunc = &padapter->hal_func; rtw_pm_set_ips(padapter, IPS_NONE); LeaveAllPowerSaveMode(padapter); - if (padapter->registrypriv.mp_mode == 0) { - rtw_hal_deinit(padapter); - padapter->registrypriv.mp_mode = 1; -#ifdef CONFIG_RF_POWER_TRIM - if (!IS_HARDWARE_TYPE_8814A(padapter) && !IS_HARDWARE_TYPE_8822B(padapter)) { - padapter->registrypriv.RegPwrTrimEnable = 1; - rtw_hal_read_chip_info(padapter); - } -#endif /*CONFIG_RF_POWER_TRIM*/ - rtw_hal_init(padapter); -#ifdef RTW_HALMAC /*for New IC*/ - MPT_InitializeAdapter(padapter, 1); -#endif /* CONFIG_MP_INCLUDED */ - } + if (rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY)) + rtw_mi_scan_abort(padapter, _FALSE); - if (padapter->registrypriv.mp_mode == 0) - return -EPERM; + if (rtw_mp_cmd(padapter, MP_START, RTW_CMDF_WAIT_ACK) != _SUCCESS) + ret = -EPERM; - if (padapter->mppriv.mode == MP_OFF) { - if (mp_start_test(padapter) == _FAIL) - return -EPERM; - padapter->mppriv.mode = MP_ON; - MPT_PwrCtlDM(padapter, 0); - } - padapter->mppriv.bmac_filter = _FALSE; -#ifdef CONFIG_RTL8723B -#ifdef CONFIG_USB_HCI - rtw_write32(padapter, 0x765, 0x0000); - rtw_write32(padapter, 0x948, 0x0280); -#else - rtw_write32(padapter, 0x765, 0x0000); - rtw_write32(padapter, 0x948, 0x0000); -#endif -#ifdef CONFIG_FOR_RTL8723BS_VQ0 - rtw_write32(padapter, 0x765, 0x0000); - rtw_write32(padapter, 0x948, 0x0280); -#endif - rtw_write8(padapter, 0x66, 0x27); /*Open BT uart Log*/ - rtw_write8(padapter, 0xc50, 0x20); /*for RX init Gain*/ -#endif - ODM_Write_DIG(&pHalData->odmpriv, 0x20); + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "mp_start %s\n", ret == 0 ? "ok" : "fail"); + wrqu->length = strlen(extra); - return 0; + return ret; } @@ -423,23 +390,18 @@ int rtw_mp_stop(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { + int ret = 0; PADAPTER padapter = rtw_netdev_priv(dev); - struct hal_ops *pHalFunc = &padapter->HalFunc; - - if (padapter->registrypriv.mp_mode == 1) { + struct hal_ops *pHalFunc = &padapter->hal_func; - MPT_DeInitAdapter(padapter); - pHalFunc->hal_deinit(padapter); - padapter->registrypriv.mp_mode = 0; - pHalFunc->hal_init(padapter); - } + if (rtw_mp_cmd(padapter, MP_STOP, RTW_CMDF_WAIT_ACK) != _SUCCESS) + ret = -EPERM; - if (padapter->mppriv.mode != MP_OFF) { - mp_stop_test(padapter); - padapter->mppriv.mode = MP_OFF; - } + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "mp_stop %s\n", ret == 0 ? "ok" : "fail"); + wrqu->length = strlen(extra); - return 0; + return ret; } @@ -448,13 +410,15 @@ int rtw_mp_rate(struct net_device *dev, struct iw_point *wrqu, char *extra) { u32 rate = MPT_RATE_1M; - u8 input[wrqu->length]; + u8 input[wrqu->length + 1]; PADAPTER padapter = rtw_netdev_priv(dev); - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; rate = rtw_mpRateParseFunc(padapter, input); padapter->mppriv.rateidx = rate; @@ -481,7 +445,7 @@ int rtw_mp_rate(struct net_device *dev, if (padapter->mppriv.rateidx >= DESC_RATEVHTSS4MCS9) return -EINVAL; - pMptCtx->MptRateIndex = HwRateToMPTRate(padapter->mppriv.rateidx); + pMptCtx->mpt_rate_index = HwRateToMPTRate(padapter->mppriv.rateidx); SetDataRate(padapter); wrqu->length = strlen(extra); @@ -496,20 +460,22 @@ int rtw_mp_channel(struct net_device *dev, PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - u8 input[wrqu->length]; + u8 input[wrqu->length + 1]; u32 channel = 1; int cur_ch_offset; + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; channel = rtw_atoi(input); /*RTW_INFO("%s: channel=%d\n", __func__, channel);*/ _rtw_memset(extra, 0, wrqu->length); sprintf(extra, "Change channel %d to channel %d", padapter->mppriv.channel , channel); padapter->mppriv.channel = channel; SetChannel(padapter); - pHalData->CurrentChannel = channel; + pHalData->current_channel = channel; wrqu->length = strlen(extra); return 0; @@ -524,8 +490,12 @@ int rtw_mp_bandwidth(struct net_device *dev, int cur_ch_offset; PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 input[wrqu->length]; - if (sscanf(extra, "40M=%d,shortGI=%d", &bandwidth, &sg) > 0) + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + if (sscanf(input, "40M=%d,shortGI=%d", &bandwidth, &sg) > 0) RTW_INFO("%s: bw=%d sg=%d\n", __func__, bandwidth , sg); if (bandwidth == 1) @@ -535,11 +505,14 @@ int rtw_mp_bandwidth(struct net_device *dev, padapter->mppriv.bandwidth = (u8)bandwidth; padapter->mppriv.preamble = sg; + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "Change BW %d to BW %d\n", pHalData->current_channel_bw , bandwidth); SetBandwidth(padapter); - pHalData->CurrentChannelBW = bandwidth; + pHalData->current_channel_bw = bandwidth; /*cur_ch_offset = rtw_get_offset_by_ch(padapter->mppriv.channel);*/ /*set_channel_bwmode(padapter, padapter->mppriv.channel, cur_ch_offset, bandwidth);*/ + wrqu->length = strlen(extra); return 0; } @@ -578,7 +551,7 @@ int rtw_mp_txpower(struct net_device *dev, u8 input[wrqu->length]; PADAPTER padapter = rtw_netdev_priv(dev); - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; @@ -613,14 +586,16 @@ int rtw_mp_ant_tx(struct net_device *dev, struct iw_point *wrqu, char *extra) { u8 i; - u8 input[wrqu->length]; + u8 input[wrqu->length + 1]; u16 antenna = 0; PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; sprintf(extra, "switch Tx antenna to %s", input); for (i = 0; i < strlen(input); i++) { @@ -644,7 +619,7 @@ int rtw_mp_ant_tx(struct net_device *dev, padapter->mppriv.antenna_tx = antenna; padapter->mppriv.antenna_rx = antenna; /*RTW_INFO("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_tx);*/ - pHalData->AntennaTxPath = antenna; + pHalData->antenna_tx_path = antenna; SetAntenna(padapter); @@ -659,12 +634,15 @@ int rtw_mp_ant_rx(struct net_device *dev, { u8 i; u16 antenna = 0; - u8 input[wrqu->length]; + u8 input[wrqu->length + 1]; PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + + input[wrqu->length] = '\0'; /*RTW_INFO("%s: input=%s\n", __func__, input);*/ _rtw_memset(extra, 0, wrqu->length); @@ -745,6 +723,7 @@ int rtw_mp_ctx(struct net_device *dev, if (copy_from_user(extra, wrqu->pointer, wrqu->length)) return -EFAULT; + *(extra + wrqu->length) = '\0'; RTW_INFO("%s: in=%s\n", __func__, extra); #ifdef CONFIG_CONCURRENT_MODE if (!is_primary_adapter(padapter)) { @@ -794,10 +773,10 @@ int rtw_mp_ctx(struct net_device *dev, bStartTest = 0; /* To set Stop*/ pmp_priv->tx.stop = 1; sprintf(extra, "Stop continuous Tx"); - ODM_Write_DIG(&pHalData->odmpriv, 0x20); + odm_write_dig(&pHalData->odmpriv, 0x20); } else { bStartTest = 1; - ODM_Write_DIG(&pHalData->odmpriv, 0x7f); + odm_write_dig(&pHalData->odmpriv, 0x7f); if (pmp_priv->mode != MP_ON) { if (pmp_priv->tx.stop != 1) { RTW_INFO("%s: MP_MODE != ON %d\n", __func__, pmp_priv->mode); @@ -833,7 +812,7 @@ int rtw_mp_disable_bt_coexist(struct net_device *dev, { PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct hal_ops *pHalFunc = &padapter->HalFunc; + struct hal_ops *pHalFunc = &padapter->hal_func; u8 input[wrqu->data.length]; u32 bt_coexist; @@ -844,8 +823,6 @@ int rtw_mp_disable_bt_coexist(struct net_device *dev, bt_coexist = rtw_atoi(input); if (bt_coexist == 0) { - RT_TRACE(_module_mp_, _drv_info_, - ("Set OID_RT_SET_DISABLE_BT_COEXIST: disable BT_COEXIST\n")); RTW_INFO("Set OID_RT_SET_DISABLE_BT_COEXIST: disable BT_COEXIST\n"); #ifdef CONFIG_BT_COEXIST rtw_btcoex_HaltNotify(padapter); @@ -856,8 +833,6 @@ int rtw_mp_disable_bt_coexist(struct net_device *dev, #endif /* CONFIG_BT_COEXIST */ } else { - RT_TRACE(_module_mp_, _drv_info_, - ("Set OID_RT_SET_DISABLE_BT_COEXIST: enable BT_COEXIST\n")); #ifdef CONFIG_BT_COEXIST rtw_btcoex_SetManualControl(padapter, _FALSE); #endif @@ -956,6 +931,7 @@ int rtw_mp_arx(struct net_device *dev, } else if (bStopRx) { SetPacketRx(padapter, bStartRx, _FALSE); pmppriv->bmac_filter = _FALSE; + pmppriv->bSetRxBssid = _FALSE; sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out); } else if (bQueryPhy) { _rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter)); @@ -1019,7 +995,7 @@ int rtw_mp_trx_query(struct net_device *dev, { u32 txok, txfail, rxok, rxfail, rxfilterout; PADAPTER padapter = rtw_netdev_priv(dev); - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo; if (PMacTxInfo.bEnPMacTx == TRUE) @@ -1089,11 +1065,13 @@ int rtw_mp_psd(struct net_device *dev, struct iw_point *wrqu, char *extra) { PADAPTER padapter = rtw_netdev_priv(dev); - u8 input[wrqu->length]; + u8 input[wrqu->length + 1]; + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; strcpy(extra, input); wrqu->length = mp_query_psd(padapter, extra); @@ -1187,6 +1165,10 @@ int rtw_mp_reset_stats(struct net_device *dev, rtw_reset_phy_rx_counters(padapter); rtw_reset_mac_rx_counters(padapter); + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "mp_reset_stats ok\n"); + wrqu->length = strlen(extra); + return 0; } @@ -1234,7 +1216,7 @@ int rtw_mp_phypara(struct net_device *dev, ret = sscanf(input, "xcap=%d", &valxcap); - pHalData->CrystalCap = (u8)valxcap; + pHalData->crystal_cap = (u8)valxcap; hal_set_crystal_cap(padapter , valxcap); sprintf(extra, "Set xcap=%d", valxcap); @@ -1247,27 +1229,39 @@ int rtw_mp_phypara(struct net_device *dev, int rtw_mp_SetRFPath(struct net_device *dev, struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) + struct iw_point *wrqu, char *extra) { PADAPTER padapter = rtw_netdev_priv(dev); - char input[wrqu->data.length]; + char input[wrqu->length]; int bMain = 1, bTurnoff = 1; - if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) - return -EFAULT; RTW_INFO("%s:iwpriv in=%s\n", __func__, input); + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + bMain = strncmp(input, "1", 2); /* strncmp TRUE is 0*/ bTurnoff = strncmp(input, "0", 3); /* strncmp TRUE is 0*/ + _rtw_memset(extra, 0, wrqu->length); + if (bMain == 0) { MP_PHY_SetRFPathSwitch(padapter, _TRUE); RTW_INFO("%s:PHY_SetRFPathSwitch=TRUE\n", __func__); + sprintf(extra, "mp_setrfpath Main\n"); + } else if (bTurnoff == 0) { MP_PHY_SetRFPathSwitch(padapter, _FALSE); RTW_INFO("%s:PHY_SetRFPathSwitch=FALSE\n", __func__); + sprintf(extra, "mp_setrfpath Aux\n"); + } else { + bMain = MP_PHY_QueryRFPathSwitch(padapter); + RTW_INFO("%s:PHY_SetRFPathSwitch = %s\n", __func__, (bMain ? "Main":"Aux")); + sprintf(extra, "mp_setrfpath %s\n" , (bMain ? "Main":"Aux")); } + wrqu->length = strlen(extra); + return 0; } @@ -1325,6 +1319,27 @@ int rtw_mp_PwrCtlDM(struct net_device *dev, return 0; } +int rtw_mp_iqk(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + + rtw_mp_trigger_iqk(padapter); + + return 0; +} + +int rtw_mp_lck(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + + rtw_mp_trigger_lck(padapter); + + return 0; +} int rtw_mp_getver(struct net_device *dev, struct iw_request_info *info, @@ -1351,7 +1366,7 @@ int rtw_mp_mon(struct net_device *dev, PADAPTER padapter = rtw_netdev_priv(dev); struct mp_priv *pmp_priv = &padapter->mppriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct hal_ops *pHalFunc = &padapter->HalFunc; + struct hal_ops *pHalFunc = &padapter->hal_func; NDIS_802_11_NETWORK_INFRASTRUCTURE networkType; int bstart = 1, bstop = 1; @@ -1359,6 +1374,7 @@ int rtw_mp_mon(struct net_device *dev, if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; + *(extra + wrqu->data.length) = '\0'; rtw_pm_set_ips(padapter, IPS_NONE); LeaveAllPowerSaveMode(padapter); @@ -1384,9 +1400,9 @@ int rtw_mp_mon(struct net_device *dev, pHalFunc->hal_deinit(padapter); padapter->registrypriv.mp_mode = 0; pHalFunc->hal_init(padapter); - /*rtw_disassoc_cmd(padapter, 0, _TRUE);*/ + /*rtw_disassoc_cmd(padapter, 0, 0);*/ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { - rtw_disassoc_cmd(padapter, 500, _TRUE); + rtw_disassoc_cmd(padapter, 500, 0); rtw_indicate_disconnect(padapter, 0, _FALSE); /*rtw_free_assoc_resources(padapter, 1);*/ } @@ -1402,7 +1418,8 @@ int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct mp_priv *pmp_priv = &padapter->mppriv; - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); + char *pextra = extra; switch (pmp_priv->mode) { @@ -1412,7 +1429,8 @@ int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) pmp_priv->mode = MP_ON; sprintf(extra, "Stop continuous Tx"); } else if (pmp_priv->tx.stop == 1) { - sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500 count=%u\n", extra, pmp_priv->tx.count); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "\nStart continuous DA=ffffffffffff len=1500 count=%u\n", pmp_priv->tx.count); pmp_priv->tx.stop = 0; SetPacketTx(padapter); } else @@ -1420,26 +1438,26 @@ int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) return 0; case MP_SINGLE_TONE_TX: if (bStartTest != 0) - sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes."); SetSingleToneTx(padapter, (u8)bStartTest); break; case MP_CONTINUOUS_TX: if (bStartTest != 0) - sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes."); SetContinuousTx(padapter, (u8)bStartTest); break; case MP_CARRIER_SUPPRISSION_TX: if (bStartTest != 0) { if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_11M) - sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes."); else - sprintf(extra, "%s\nSpecify carrier suppression but not CCK rate", extra); + strcat(extra, "\nSpecify carrier suppression but not CCK rate"); } SetCarrierSuppressionTx(padapter, (u8)bStartTest); break; case MP_SINGLE_CARRIER_TX: if (bStartTest != 0) - sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes."); SetSingleCarrierTx(padapter, (u8)bStartTest); break; @@ -1468,9 +1486,9 @@ int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) if (IS_HARDWARE_TYPE_8812AU(padapter)) { /* <20130425, Kordan> Turn off OFDM Rx to prevent from CCA causing Tx hang.*/ if (pmp_priv->mode == MP_PACKET_TX) - PHY_SetBBReg(padapter, rCCAonSec_Jaguar, BIT3, 1); + phy_set_bb_reg(padapter, rCCAonSec_Jaguar, BIT3, 1); else - PHY_SetBBReg(padapter, rCCAonSec_Jaguar, BIT3, 0); + phy_set_bb_reg(padapter, rCCAonSec_Jaguar, BIT3, 0); } #endif @@ -1485,9 +1503,9 @@ int rtw_mp_tx(struct net_device *dev, PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct mp_priv *pmp_priv = &padapter->mppriv; - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); struct registry_priv *pregistrypriv = &padapter->registrypriv; - + char *pextra = extra; u32 bandwidth = 0, sg = 0, channel = 6, txpower = 40, rate = 108, ant = 0, txmode = 1, count = 0; u8 i = 0, j = 0, bStartTest = 1, status = 0, Idx = 0, tmpU1B = 0; u16 antenna = 0; @@ -1517,13 +1535,13 @@ int rtw_mp_tx(struct net_device *dev, return 0; } else if (strncmp(extra, "setting", 7) == 0) { _rtw_memset(extra, 0, wrqu->data.length); - sprintf(extra, "Current Setting :\n Channel:%d", pmp_priv->channel); - sprintf(extra, "%s\n Bandwidth:%d", extra, pmp_priv->bandwidth); - sprintf(extra, "%s\n Rate index:%d", extra, pmp_priv->rateidx); - sprintf(extra, "%s\n TxPower index:%d", extra, pmp_priv->txpoweridx); - sprintf(extra, "%s\n Antenna TxPath:%d", extra, pmp_priv->antenna_tx); - sprintf(extra, "%s\n Antenna RxPath:%d", extra, pmp_priv->antenna_rx); - sprintf(extra, "%s\n MP Mode:%d", extra, pmp_priv->mode); + pextra += sprintf(pextra, "Current Setting :\n Channel:%d", pmp_priv->channel); + pextra += sprintf(pextra, "\n Bandwidth:%d", pmp_priv->bandwidth); + pextra += sprintf(pextra, "\n Rate index:%d", pmp_priv->rateidx); + pextra += sprintf(pextra, "\n TxPower index:%d", pmp_priv->txpoweridx); + pextra += sprintf(pextra, "\n Antenna TxPath:%d", pmp_priv->antenna_tx); + pextra += sprintf(pextra, "\n Antenna RxPath:%d", pmp_priv->antenna_rx); + pextra += sprintf(pextra, "\n MP Mode:%d", pmp_priv->mode); wrqu->data.length = strlen(extra); return 0; #ifdef CONFIG_MP_VHT_HW_TX_MODE @@ -1661,45 +1679,48 @@ int rtw_mp_tx(struct net_device *dev, if (sscanf(extra, "ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d", &channel, &bandwidth, &rate, &txpower, &ant, &txmode) < 6) { RTW_INFO("Invalid format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode); _rtw_memset(extra, 0, wrqu->data.length); - sprintf(extra, "\n Please input correct format as bleow:\n"); - sprintf(extra, "%s\t ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d\n", extra, channel, bandwidth, rate, txpower, ant, txmode); - sprintf(extra, "%s\n [ ch : BGN = <1~14> , A or AC = <36~165> ]", extra); - sprintf(extra, "%s\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]", extra); - sprintf(extra, "%s\n [ rate : CCK: 1 2 5.5 11M X 2 = < 2 4 11 22 >]", extra); - sprintf(extra, "%s\n [ OFDM: 6 9 12 18 24 36 48 54M X 2 = < 12 18 24 36 48 72 96 108>", extra); - sprintf(extra, "%s\n [ HT 1S2SS MCS0 ~ MCS15 : < [MCS0]=128 ~ [MCS7]=135 ~ [MCS15]=143 >", extra); - sprintf(extra, "%s\n [ HT 3SS MCS16 ~ MCS32 : < [MCS16]=144 ~ [MCS23]=151 ~ [MCS32]=159 >", extra); - sprintf(extra, "%s\n [ VHT 1SS MCS0 ~ MCS9 : < [MCS0]=160 ~ [MCS9]=169 >", extra); - sprintf(extra, "%s\n [ txpower : 1~63 power index", extra); - sprintf(extra, "%s\n [ ant : ,2T ex: AB=3 BC=6 CD=12", extra); - sprintf(extra, "%s\n [ txmode : < 0 = CONTINUOUS_TX, 1 = PACKET_TX, 2 = SINGLE_TONE_TX, 3 = CARRIER_SUPPRISSION_TX, 4 = SINGLE_CARRIER_TX>\n", extra); + pextra += sprintf(pextra, "\n Please input correct format as bleow:\n"); + pextra += sprintf(pextra, "\t ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d\n", channel, bandwidth, rate, txpower, ant, txmode); + pextra += sprintf(pextra, "\n [ ch : BGN = <1~14> , A or AC = <36~165> ]"); + pextra += sprintf(pextra, "\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]"); + pextra += sprintf(pextra, "\n [ rate : CCK: 1 2 5.5 11M X 2 = < 2 4 11 22 >]"); + pextra += sprintf(pextra, "\n [ OFDM: 6 9 12 18 24 36 48 54M X 2 = < 12 18 24 36 48 72 96 108>"); + pextra += sprintf(pextra, "\n [ HT 1S2SS MCS0 ~ MCS15 : < [MCS0]=128 ~ [MCS7]=135 ~ [MCS15]=143 >"); + pextra += sprintf(pextra, "\n [ HT 3SS MCS16 ~ MCS32 : < [MCS16]=144 ~ [MCS23]=151 ~ [MCS32]=159 >"); + pextra += sprintf(pextra, "\n [ VHT 1SS MCS0 ~ MCS9 : < [MCS0]=160 ~ [MCS9]=169 >"); + pextra += sprintf(pextra, "\n [ txpower : 1~63 power index"); + pextra += sprintf(pextra, "\n [ ant : ,2T ex: AB=3 BC=6 CD=12"); + pextra += sprintf(pextra, "\n [ txmode : < 0 = CONTINUOUS_TX, 1 = PACKET_TX, 2 = SINGLE_TONE_TX, 3 = CARRIER_SUPPRISSION_TX, 4 = SINGLE_CARRIER_TX>\n"); wrqu->data.length = strlen(extra); return status; } else { + char *pextra = extra; RTW_INFO("Got format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode); _rtw_memset(extra, 0, wrqu->data.length); sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel); padapter->mppriv.channel = channel; SetChannel(padapter); - pHalData->CurrentChannel = channel; + pHalData->current_channel = channel; if (bandwidth == 1) bandwidth = CHANNEL_WIDTH_40; else if (bandwidth == 2) bandwidth = CHANNEL_WIDTH_80; - sprintf(extra, "%s\nChange Current Bandwidth %d to Bandwidth %d", extra, padapter->mppriv.bandwidth , bandwidth); + pextra = extra + strlen(pextra); + pextra += sprintf(pextra, "\nChange Current Bandwidth %d to Bandwidth %d", padapter->mppriv.bandwidth, bandwidth); padapter->mppriv.bandwidth = (u8)bandwidth; padapter->mppriv.preamble = sg; SetBandwidth(padapter); - pHalData->CurrentChannelBW = bandwidth; + pHalData->current_channel_bw = bandwidth; - sprintf(extra, "%s\nSet power level :%d", extra, txpower); + pextra += sprintf(pextra, "\nSet power level :%d", txpower); padapter->mppriv.txpoweridx = (u8)txpower; pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)txpower; pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)txpower; pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)txpower; pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)txpower; + SetTxPower(padapter); RTW_INFO("%s: bw=%d sg=%d\n", __func__, bandwidth, sg); @@ -1717,13 +1738,13 @@ int rtw_mp_tx(struct net_device *dev, RTW_INFO("%s: rate index=%d\n", __func__, rate); if (rate >= MPT_RATE_LAST) return -EINVAL; - sprintf(extra, "%s\nSet data rate to %d index %d", extra, padapter->mppriv.rateidx, rate); + pextra += sprintf(pextra, "\nSet data rate to %d index %d", padapter->mppriv.rateidx, rate); padapter->mppriv.rateidx = rate; - pMptCtx->MptRateIndex = rate; + pMptCtx->mpt_rate_index = rate; SetDataRate(padapter); - sprintf(extra, "%s\nSet Antenna Path :%d", extra, ant); + pextra += sprintf(pextra, "\nSet Antenna Path :%d", ant); switch (ant) { case 1: antenna = ANTENNA_A; @@ -1771,7 +1792,7 @@ int rtw_mp_tx(struct net_device *dev, RTW_INFO("%s: antenna=0x%x\n", __func__, antenna); padapter->mppriv.antenna_tx = antenna; padapter->mppriv.antenna_rx = antenna; - pHalData->AntennaTxPath = antenna; + pHalData->antenna_tx_path = antenna; SetAntenna(padapter); if (txmode == 0) @@ -1803,8 +1824,8 @@ int rtw_mp_rx(struct net_device *dev, PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct mp_priv *pmp_priv = &padapter->mppriv; - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); - + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); + char *pextra = extra; u32 bandwidth = 0, sg = 0, channel = 6, ant = 0; u16 antenna = 0; u8 bStartRx = 0; @@ -1831,34 +1852,36 @@ int rtw_mp_rx(struct net_device *dev, } else if (sscanf(extra, "ch=%d,bw=%d,ant=%d", &channel, &bandwidth, &ant) < 3) { RTW_INFO("Invalid format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant); _rtw_memset(extra, 0, wrqu->data.length); - sprintf(extra, "\n Please input correct format as bleow:\n"); - sprintf(extra, "%s\t ch=%d,bw=%d,ant=%d\n", extra, channel, bandwidth, ant); - sprintf(extra, "%s\n [ ch : BGN = <1~14> , A or AC = <36~165> ]", extra); - sprintf(extra, "%s\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]", extra); - sprintf(extra, "%s\n [ ant : ,2T ex: AB=3 BC=6 CD=12", extra); + pextra += sprintf(pextra, "\n Please input correct format as bleow:\n"); + pextra += sprintf(pextra, "\t ch=%d,bw=%d,ant=%d\n", channel, bandwidth, ant); + pextra += sprintf(pextra, "\n [ ch : BGN = <1~14> , A or AC = <36~165> ]"); + pextra += sprintf(pextra, "\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]"); + pextra += sprintf(pextra, "\n [ ant : ,2T ex: AB=3 BC=6 CD=12"); wrqu->data.length = strlen(extra); return 0; } else { + char *pextra = extra; bStartRx = 1; RTW_INFO("Got format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant); _rtw_memset(extra, 0, wrqu->data.length); sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel); padapter->mppriv.channel = channel; SetChannel(padapter); - pHalData->CurrentChannel = channel; + pHalData->current_channel = channel; if (bandwidth == 1) bandwidth = CHANNEL_WIDTH_40; else if (bandwidth == 2) bandwidth = CHANNEL_WIDTH_80; - sprintf(extra, "%s\nChange Current Bandwidth %d to Bandwidth %d", extra, padapter->mppriv.bandwidth , bandwidth); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "\nChange Current Bandwidth %d to Bandwidth %d", padapter->mppriv.bandwidth, bandwidth); padapter->mppriv.bandwidth = (u8)bandwidth; padapter->mppriv.preamble = sg; SetBandwidth(padapter); - pHalData->CurrentChannelBW = bandwidth; + pHalData->current_channel_bw = bandwidth; - sprintf(extra, "%s\nSet Antenna Path :%d", extra, ant); + pextra += sprintf(pextra, "\nSet Antenna Path :%d", ant); switch (ant) { case 1: antenna = ANTENNA_A; @@ -1906,10 +1929,10 @@ int rtw_mp_rx(struct net_device *dev, RTW_INFO("%s: antenna=0x%x\n", __func__, antenna); padapter->mppriv.antenna_tx = antenna; padapter->mppriv.antenna_rx = antenna; - pHalData->AntennaTxPath = antenna; + pHalData->antenna_tx_path = antenna; SetAntenna(padapter); - sprintf(extra, "%s\nstart Rx", extra); + strcat(extra, "\nstart Rx"); SetPacketRx(padapter, bStartRx, _FALSE); } wrqu->data.length = strlen(extra); @@ -1924,7 +1947,7 @@ int rtw_mp_hwtx(struct net_device *dev, PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct mp_priv *pmp_priv = &padapter->mppriv; - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) u8 input[wrqu->data.length]; @@ -1944,6 +1967,60 @@ int rtw_mp_hwtx(struct net_device *dev, } +int rtw_mp_pwrlmt(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + struct registry_priv *registry_par = &padapter->registrypriv; + u8 pwrlimtstat = 0; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; +#ifdef CONFIG_TXPWR_LIMIT + pwrlimtstat = registry_par->RegEnableTxPowerLimit; + if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { + padapter->registrypriv.RegEnableTxPowerLimit = 0; + sprintf(extra, "Turn off Power Limit\n"); + + } else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) { + padapter->registrypriv.RegEnableTxPowerLimit = 1; + sprintf(extra, "Turn on Power Limit\n"); + + } else +#endif + sprintf(extra, "Get Power Limit Status:%s\n", (pwrlimtstat == 1) ? "ON" : "OFF"); + + + wrqu->data.length = strlen(extra); + return 0; +} + +int rtw_mp_pwrbyrate(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { + padapter->registrypriv.RegEnableTxPowerByRate = 0; + sprintf(extra, "Turn off Tx Power by Rate\n"); + + } else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) { + padapter->registrypriv.RegEnableTxPowerByRate = 1; + sprintf(extra, "Turn On Tx Power by Rate\n"); + + } else { + sprintf(extra, "Get Power by Rate Status:%s\n", (padapter->registrypriv.RegEnableTxPowerByRate == 1) ? "ON" : "OFF"); + } + + wrqu->data.length = strlen(extra); + return 0; +} + int rtw_efuse_mask_file(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) @@ -1957,6 +2034,7 @@ int rtw_efuse_mask_file(struct net_device *dev, if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; + *(extra + wrqu->data.length) = '\0'; if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { padapter->registrypriv.boffefusemask = 1; sprintf(extra, "Turn off Efuse Mask\n"); @@ -1969,6 +2047,46 @@ int rtw_efuse_mask_file(struct net_device *dev, wrqu->data.length = strlen(extra); return 0; } + if (strncmp(extra, "data,", 5) == 0) { + u8 *pch, *pdata; + char *ptmp, tmp; + u8 count = 0; + u8 i = 0; + u32 datalen = 0; + + ptmp = extra; + pch = strsep(&ptmp, ","); + + if ((pch == NULL) || (strlen(pch) == 0)) { + RTW_INFO("%s: parameter error(no cmd)!\n", __func__); + return -EFAULT; + } + + do { + pch = strsep(&ptmp, ":"); + if ((pch == NULL) || (strlen(pch) == 0)) + break; + if (strlen(pch) != 2 + || IsHexDigit(*pch) == _FALSE + || IsHexDigit(*(pch + 1)) == _FALSE + || sscanf(pch, "%hhx", &tmp) != 1 + ) { + RTW_INFO("%s: invalid 8-bit hex! input format: data,01:23:45:67:89:ab:cd:ef...\n", __func__); + return -EFAULT; + } + maskfileBuffer[count++] = tmp; + + } while (count < 64); + + for (i = 0; i < count; i++) + sprintf(extra, "%s:%02x", extra, maskfileBuffer[i]); + + padapter->registrypriv.bFileMaskEfuse = _TRUE; + + sprintf(extra, "%s\nLoad Efuse Mask data %d hex ok\n", extra, count); + wrqu->data.length = strlen(extra); + return 0; + } rtw_efuse_mask_file_path = extra; if (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) { @@ -1996,6 +2114,7 @@ int rtw_efuse_file_map(struct net_device *dev, PEFUSE_HAL pEfuseHal; PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mp_priv *pmp_priv = &padapter->mppriv; pEfuseHal = &pHalData->EfuseHal; if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) @@ -2008,10 +2127,13 @@ int rtw_efuse_file_map(struct net_device *dev, if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) { RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path); Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeEfuseModifiedMap, sizeof(pEfuseHal->fakeEfuseModifiedMap)); - if (Status == _TRUE) + if (Status == _TRUE) { + pmp_priv->bloadefusemap = _TRUE; sprintf(extra, "efuse file file_read OK\n"); - else + } else { + pmp_priv->bloadefusemap = _FALSE; sprintf(extra, "efuse file file_read FAIL\n"); + } } else { sprintf(extra, "efuse file readable FAIL\n"); RTW_INFO("%s rtw_is_file_readable fail!\n", __func__); @@ -2026,11 +2148,11 @@ int rtw_mp_SetBT(struct net_device *dev, union iwreq_data *wrqu, char *extra) { PADAPTER padapter = rtw_netdev_priv(dev); - struct hal_ops *pHalFunc = &padapter->HalFunc; + struct hal_ops *pHalFunc = &padapter->hal_func; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); BT_REQ_CMD BtReq; - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); PBT_RSP_CMD pBtRsp = (PBT_RSP_CMD)&pMptCtx->mptOutBuf[0]; char input[128]; char *pch, *ptmp, *token, *tmp[2] = {0x00, 0x00}; @@ -2236,7 +2358,7 @@ int rtw_mp_SetBT(struct net_device *dev, } if (strncmp(extra, "2ant", 4) == 0) { RTW_INFO("Set BT 2ant use!\n"); - PHY_SetMacReg(padapter, 0x67, BIT5, 0x1); + phy_set_mac_reg(padapter, 0x67, BIT5, 0x1); rtw_write32(padapter, 0x948, 0000); goto exit; diff --git a/os_dep/linux/mlme_linux.c b/os_dep/linux/mlme_linux.c index 7548d05..4da606e 100644 --- a/os_dep/linux/mlme_linux.c +++ b/os_dep/linux/mlme_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _MLME_OSDEP_C_ @@ -30,9 +25,7 @@ void Linkup_workitem_callback(struct work_struct *work) struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkup_workitem); _adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv); - _func_enter_; - RT_TRACE(_module_mlme_osdep_c_, _drv_info_, ("+ Linkup_workitem_callback\n")); #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12)) kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKUP); @@ -40,7 +33,6 @@ void Linkup_workitem_callback(struct work_struct *work) kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKUP); #endif - _func_exit_; } void Linkdown_workitem_callback(struct work_struct *work) @@ -48,9 +40,7 @@ void Linkdown_workitem_callback(struct work_struct *work) struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkdown_workitem); _adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv); - _func_enter_; - RT_TRACE(_module_mlme_osdep_c_, _drv_info_, ("+ Linkdown_workitem_callback\n")); #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12)) kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKDOWN); @@ -58,94 +48,15 @@ void Linkdown_workitem_callback(struct work_struct *work) kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKDOWN); #endif - _func_exit_; } #endif - -/* -void sitesurvey_ctrl_handler(void *FunctionContext) -{ - _adapter *adapter = (_adapter *)FunctionContext; - - _sitesurvey_ctrl_handler(adapter); - - _set_timer(&adapter->mlmepriv.sitesurveyctrl.sitesurvey_ctrl_timer, 3000); -} -*/ - -void rtw_join_timeout_handler(void *FunctionContext) -{ - _adapter *adapter = (_adapter *)FunctionContext; - _rtw_join_timeout_handler(adapter); -} - - -void _rtw_scan_timeout_handler(void *FunctionContext) -{ - _adapter *adapter = (_adapter *)FunctionContext; - rtw_scan_timeout_handler(adapter); -} - - -void _dynamic_check_timer_handlder(void *FunctionContext) -{ - _adapter *adapter = (_adapter *)FunctionContext; - -#if (MP_DRIVER == 1) - if (adapter->registrypriv.mp_mode == 1 && adapter->mppriv.mp_dm == 0) { /* for MP ODM dynamic Tx power tracking */ - /* RTW_INFO("_dynamic_check_timer_handlder mp_dm =0 return\n"); */ - _set_timer(&adapter->mlmepriv.dynamic_chk_timer, 2000); - return; - } -#endif - - rtw_mi_dynamic_check_timer_handlder(adapter); - - _set_timer(&adapter->mlmepriv.dynamic_chk_timer, 2000); -} - -#ifdef CONFIG_SET_SCAN_DENY_TIMER -void _rtw_set_scan_deny_timer_hdl(void *FunctionContext) -{ - _adapter *adapter = (_adapter *)FunctionContext; - rtw_set_scan_deny_timer_hdl(adapter); -} -#endif - - -void rtw_init_mlme_timer(_adapter *padapter) -{ - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - - _init_timer(&(pmlmepriv->assoc_timer), padapter->pnetdev, rtw_join_timeout_handler, padapter); - /* _init_timer(&(pmlmepriv->sitesurveyctrl.sitesurvey_ctrl_timer), padapter->pnetdev, sitesurvey_ctrl_handler, padapter); */ - _init_timer(&(pmlmepriv->scan_to_timer), padapter->pnetdev, _rtw_scan_timeout_handler, padapter); - -#ifdef CONFIG_DFS_MASTER - _init_timer(&(pmlmepriv->dfs_master_timer), padapter->pnetdev, rtw_dfs_master_timer_hdl, padapter); -#endif - - _init_timer(&(pmlmepriv->dynamic_chk_timer), padapter->pnetdev, _dynamic_check_timer_handlder, padapter); - -#ifdef CONFIG_SET_SCAN_DENY_TIMER - _init_timer(&(pmlmepriv->set_scan_deny_timer), padapter->pnetdev, _rtw_set_scan_deny_timer_hdl, padapter); -#endif - -#ifdef RTK_DMP_PLATFORM - _init_workitem(&(pmlmepriv->Linkup_workitem), Linkup_workitem_callback, padapter); - _init_workitem(&(pmlmepriv->Linkdown_workitem), Linkdown_workitem_callback, padapter); -#endif - -} - extern void rtw_indicate_wx_assoc_event(_adapter *padapter); extern void rtw_indicate_wx_disassoc_event(_adapter *padapter); void rtw_os_indicate_connect(_adapter *adapter) { struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - _func_enter_; #ifdef CONFIG_IOCTL_CFG80211 if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || @@ -165,7 +76,6 @@ void rtw_os_indicate_connect(_adapter *adapter) _set_workitem(&adapter->mlmepriv.Linkup_workitem); #endif - _func_exit_; } @@ -208,7 +118,6 @@ void rtw_reset_securitypriv(_adapter *adapter) pmlmeext->mgnt_80211w_IPN_rx = 0; #endif /* CONFIG_IEEE80211W */ _rtw_memset((unsigned char *)&adapter->securitypriv, 0, sizeof(struct security_priv)); - /* _init_timer(&(adapter->securitypriv.tkip_timer),adapter->pnetdev, rtw_use_tkipkey_handler, adapter); */ /* Added by Albert 2009/02/18 */ /* Restore the PMK information to securitypriv structure for the following connection. */ @@ -246,7 +155,6 @@ void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_gener { /* RT_PMKID_LIST backupPMKIDList[NUM_PMKID_CACHE]; */ - _func_enter_; netif_carrier_off(adapter->pnetdev); /* Do it first for tx broadcast pkt after disconnection issue! */ @@ -262,7 +170,6 @@ void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_gener /* modify for CONFIG_IEEE80211W, none 11w also can use the same command */ rtw_reset_securitypriv_cmd(adapter); - _func_exit_; } @@ -272,13 +179,10 @@ void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie) u8 *buff, *p, i; union iwreq_data wrqu; - _func_enter_; - RT_TRACE(_module_mlme_osdep_c_, _drv_info_, ("+rtw_report_sec_ie, authmode=%d\n", authmode)); buff = NULL; if (authmode == _WPA_IE_ID_) { - RT_TRACE(_module_mlme_osdep_c_, _drv_info_, ("rtw_report_sec_ie, authmode=%d\n", authmode)); buff = rtw_zmalloc(IW_CUSTOM_MAX); if (NULL == buff) { @@ -311,78 +215,7 @@ void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie) rtw_mfree(buff, IW_CUSTOM_MAX); } -exit: - - _func_exit_; - -} - -void _survey_timer_hdl(void *FunctionContext) -{ - _adapter *padapter = (_adapter *)FunctionContext; - - survey_timer_hdl(padapter); -} - -void _link_timer_hdl(void *FunctionContext) -{ - _adapter *padapter = (_adapter *)FunctionContext; - link_timer_hdl(padapter); -} - -void _addba_timer_hdl(void *FunctionContext) -{ - struct sta_info *psta = (struct sta_info *)FunctionContext; - addba_timer_hdl(psta); -} - -#ifdef CONFIG_IEEE80211W - -void _sa_query_timer_hdl(void *FunctionContext) -{ - struct sta_info *psta = (struct sta_info *)FunctionContext; - - sa_query_timer_hdl(psta); -} - -void init_dot11w_expire_timer(_adapter *padapter, struct sta_info *psta) -{ - _init_timer(&psta->dot11w_expire_timer, padapter->pnetdev, _sa_query_timer_hdl, psta); -} - -#endif /* CONFIG_IEEE80211W */ - -void init_addba_retry_timer(_adapter *padapter, struct sta_info *psta) -{ - - _init_timer(&psta->addba_retry_timer, padapter->pnetdev, _addba_timer_hdl, psta); -} - -/* -void _reauth_timer_hdl(void *FunctionContext) -{ - _adapter *padapter = (_adapter *)FunctionContext; - reauth_timer_hdl(padapter); -} - -void _reassoc_timer_hdl(void *FunctionContext) -{ - _adapter *padapter = (_adapter *)FunctionContext; - reassoc_timer_hdl(padapter); -} -*/ - -void init_mlme_ext_timer(_adapter *padapter) -{ - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - - _init_timer(&pmlmeext->survey_timer, padapter->pnetdev, _survey_timer_hdl, padapter); - _init_timer(&pmlmeext->link_timer, padapter->pnetdev, _link_timer_hdl, padapter); - - /* _init_timer(&pmlmeext->ADDBA_timer, padapter->pnetdev, _addba_timer_hdl, padapter); */ - /* _init_timer(&pmlmeext->reauth_timer, padapter->pnetdev, _reauth_timer_hdl, padapter); */ - /* _init_timer(&pmlmeext->reassoc_timer, padapter->pnetdev, _reassoc_timer_hdl, padapter); */ } #ifdef CONFIG_AP_MODE @@ -493,9 +326,11 @@ static const struct net_device_ops rtl871x_mgnt_netdev_ops = { .ndo_open = mgnt_netdev_open, .ndo_stop = mgnt_netdev_close, .ndo_start_xmit = mgnt_xmit_entry, - /* .ndo_set_mac_address = r871x_net_set_mac_address, - * .ndo_get_stats = r871x_net_get_stats, - * .ndo_do_ioctl = r871x_mp_ioctl, */ + #if 0 + .ndo_set_mac_address = r871x_net_set_mac_address, + .ndo_get_stats = r871x_net_get_stats, + .ndo_do_ioctl = r871x_mp_ioctl, + #endif }; #endif diff --git a/os_dep/linux/os_intfs.c b/os_dep/linux/os_intfs.c index aff7a80..d58b71e 100644 --- a/os_dep/linux/os_intfs.c +++ b/os_dep/linux/os_intfs.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _OS_INTFS_C_ #include @@ -24,14 +19,14 @@ #if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) -#error "Shall be Linux or Windows, but not both!\n" + #error "Shall be Linux or Windows, but not both!\n" #endif MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Realtek Wireless Lan Driver"); -MODULE_AUTHOR("Brandon Bailey "); +MODULE_AUTHOR("Realtek Semiconductor Corp."); MODULE_VERSION(DRIVERVERSION); /* module param defaults */ @@ -45,28 +40,47 @@ int rtw_network_mode = Ndis802_11IBSS;/* Ndis802_11Infrastructure; */ /* infra, int rtw_channel = 1;/* ad-hoc support requirement */ int rtw_wireless_mode = WIRELESS_MODE_MAX; int rtw_vrtl_carrier_sense = AUTO_VCS; -int rtw_vcs_type = RTS_CTS;/* * */ -int rtw_rts_thresh = 2347;/* * */ -int rtw_frag_thresh = 2346;/* * */ +int rtw_vcs_type = RTS_CTS; +int rtw_rts_thresh = 2347; +int rtw_frag_thresh = 2346; int rtw_preamble = PREAMBLE_LONG;/* long, short, auto */ int rtw_scan_mode = 1;/* active, passive */ int rtw_adhoc_tx_pwr = 1; int rtw_soft_ap = 0; /* int smart_ps = 1; */ #ifdef CONFIG_POWER_SAVING -int rtw_power_mgnt = PS_MODE_MAX; -#ifdef CONFIG_IPS_LEVEL_2 -int rtw_ips_mode = IPS_LEVEL_2; -#else -int rtw_ips_mode = IPS_NORMAL; -#endif -#else -int rtw_power_mgnt = PS_MODE_ACTIVE; -int rtw_ips_mode = IPS_NONE; -#endif + int rtw_power_mgnt = PS_MODE_MAX; + #ifdef CONFIG_IPS_LEVEL_2 + int rtw_ips_mode = IPS_LEVEL_2; + #else + int rtw_ips_mode = IPS_NORMAL; + #endif /*CONFIG_IPS_LEVEL_2*/ + + #ifdef CONFIG_USB_HCI + int rtw_lps_level = LPS_NORMAL; /*USB default LPS level*/ + #else /*SDIO,PCIE*/ + #if defined(CONFIG_LPS_PG) + /*int rtw_lps_level = LPS_PG;*//*FW not support yet*/ + int rtw_lps_level = LPS_LCLK; + #elif defined(CONFIG_LPS_LCLK) + int rtw_lps_level = LPS_LCLK; + #else + int rtw_lps_level = LPS_NORMAL; + #endif + #endif/*CONFIG_USB_HCI*/ +#else /* !CONFIG_POWER_SAVING */ + int rtw_power_mgnt = PS_MODE_ACTIVE; + int rtw_ips_mode = IPS_NONE; + int rtw_lps_level = LPS_NORMAL; +#endif /* CONFIG_POWER_SAVING */ + + module_param(rtw_ips_mode, int, 0644); MODULE_PARM_DESC(rtw_ips_mode, "The default IPS mode"); +module_param(rtw_lps_level, int, 0644); +MODULE_PARM_DESC(rtw_lps_level, "The default LPS level"); + int rtw_smart_ps = 2; int rtw_check_fw_ps = 1; @@ -78,13 +92,16 @@ int rtw_early_mode = 1; int rtw_usb_rxagg_mode = 2;/* RX_AGG_DMA=1, RX_AGG_USB=2 */ module_param(rtw_usb_rxagg_mode, int, 0644); +int rtw_dynamic_agg_enable = 1; +module_param(rtw_dynamic_agg_enable, int, 0644); + /* set log level when inserting driver module, default log level is _DRV_INFO_ = 4, * please refer to "How_to_set_driver_debug_log_level.doc" to set the available level. */ #ifdef RTW_LOG_LEVEL -uint rtw_drv_log_level = (uint)RTW_LOG_LEVEL; /* from Makefile */ + uint rtw_drv_log_level = (uint)RTW_LOG_LEVEL; /* from Makefile */ #else -uint rtw_drv_log_level = _DRV_INFO_; + uint rtw_drv_log_level = _DRV_INFO_; #endif module_param(rtw_drv_log_level, uint, 0644); MODULE_PARM_DESC(rtw_drv_log_level, "set log level when insert driver module, default log level is _DRV_INFO_ = 4"); @@ -98,6 +115,12 @@ int rtw_ack_policy = NORMAL_ACK; int rtw_mp_mode = 0; +#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR) +uint rtw_mp_customer_str = 0; +module_param(rtw_mp_customer_str, uint, 0644); +MODULE_PARM_DESC(rtw_mp_customer_str, "Whether or not to enable customer str support on MP mode"); +#endif + int rtw_software_encrypt = 0; int rtw_software_decrypt = 0; @@ -110,24 +133,53 @@ int rtw_uapsd_acbk_en = 0; int rtw_uapsd_acbe_en = 0; int rtw_uapsd_acvi_en = 0; int rtw_uapsd_acvo_en = 0; -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) -int rtw_pwrtrim_enable = 2; /* disable kfree , rename to power trim disable */ +#if defined(CONFIG_RTL8814A) + int rtw_pwrtrim_enable = 2; /* disable kfree , rename to power trim disable */ +#elif defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) + /*PHYDM API, must enable by default*/ + int rtw_pwrtrim_enable = 1; #else -int rtw_pwrtrim_enable = 0; /* Default Enalbe power trim by efuse config */ + int rtw_pwrtrim_enable = 0; /* Default Enalbe power trim by efuse config */ #endif + +uint rtw_tx_bw_mode = 0x21; +module_param(rtw_tx_bw_mode, uint, 0644); +MODULE_PARM_DESC(rtw_tx_bw_mode, "The max tx bw for 2.4G and 5G. format is the same as rtw_bw_mode"); + #ifdef CONFIG_80211N_HT int rtw_ht_enable = 1; /* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz, 4: 80+80MHz * 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 * 0x21 means enable 2.4G 40MHz & 5G 80MHz */ int rtw_bw_mode = 0x21; -int rtw_ampdu_enable = 1;/* for enable tx_ampdu , */ /* 0: disable, 0x1:enable (but wifi_spec should be 0), 0x2: force enable (don't care wifi_spec) */ +int rtw_ampdu_enable = 1;/* for enable tx_ampdu , */ /* 0: disable, 0x1:enable */ int rtw_rx_stbc = 1;/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */ -#if defined(CONFIG_RTL8822B) && defined(CONFIG_PCI_HCI) +#if (defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)) && defined(CONFIG_PCI_HCI) int rtw_ampdu_amsdu = 2;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */ #else int rtw_ampdu_amsdu = 0;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */ #endif + +static uint rtw_rx_ampdu_sz_limit_1ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS; +static uint rtw_rx_ampdu_sz_limit_1ss_num = 0; +module_param_array(rtw_rx_ampdu_sz_limit_1ss, uint, &rtw_rx_ampdu_sz_limit_1ss_num, 0644); +MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_1ss, "RX AMPDU size limit for 1SS link of each BW, 0xFF: no limitation"); + +static uint rtw_rx_ampdu_sz_limit_2ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS; +static uint rtw_rx_ampdu_sz_limit_2ss_num = 0; +module_param_array(rtw_rx_ampdu_sz_limit_2ss, uint, &rtw_rx_ampdu_sz_limit_2ss_num, 0644); +MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_2ss, "RX AMPDU size limit for 2SS link of each BW, 0xFF: no limitation"); + +static uint rtw_rx_ampdu_sz_limit_3ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS; +static uint rtw_rx_ampdu_sz_limit_3ss_num = 0; +module_param_array(rtw_rx_ampdu_sz_limit_3ss, uint, &rtw_rx_ampdu_sz_limit_3ss_num, 0644); +MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_3ss, "RX AMPDU size limit for 3SS link of each BW, 0xFF: no limitation"); + +static uint rtw_rx_ampdu_sz_limit_4ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS; +static uint rtw_rx_ampdu_sz_limit_4ss_num = 0; +module_param_array(rtw_rx_ampdu_sz_limit_4ss, uint, &rtw_rx_ampdu_sz_limit_4ss_num, 0644); +MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_4ss, "RX AMPDU size limit for 4SS link of each BW, 0xFF: no limitation"); + /* Short GI support Bit Map * BIT0 - 20MHz, 0: non-support, 1: support * BIT1 - 40MHz, 0: non-support, 1: support @@ -139,13 +191,13 @@ int rtw_ldpc_cap = 0x33; /* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */ int rtw_stbc_cap = 0x13; /* - * BIT0: Enable VHT SU Beamformer - * BIT1: Enable VHT SU Beamformee - * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer - * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee - * BIT4: Enable HT Beamformer - * BIT5: Enable HT Beamformee - */ +* BIT0: Enable VHT SU Beamformer +* BIT1: Enable VHT SU Beamformee +* BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer +* BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee +* BIT4: Enable HT Beamformer +* BIT5: Enable HT Beamformee +*/ int rtw_beamform_cap = BIT(1) | BIT(3); int rtw_bfer_rf_number = 0; /*BeamformerCapRfNum Rf path number, 0 for auto, others for manual*/ int rtw_bfee_rf_number = 0; /*BeamformeeCapRfNum Rf path number, 0 for auto, others for manual*/ @@ -154,26 +206,34 @@ int rtw_bfee_rf_number = 0; /*BeamformeeCapRfNum Rf path number, 0 for auto, ot #ifdef CONFIG_80211AC_VHT int rtw_vht_enable = 1; /* 0:disable, 1:enable, 2:force auto enable */ +module_param(rtw_vht_enable, int, 0644); + int rtw_ampdu_factor = 7; -int rtw_vht_rate_sel = 0; + +uint rtw_vht_rx_mcs_map = 0xaaaa; +module_param(rtw_vht_rx_mcs_map, uint, 0644); +MODULE_PARM_DESC(rtw_vht_rx_mcs_map, "VHT RX MCS map"); #endif /* CONFIG_80211AC_VHT */ int rtw_lowrate_two_xmit = 1;/* Use 2 path Tx to transmit MCS0~7 and legacy mode */ -/* int rf_config = RF_1T2R; */ /* 1T2R */ -int rtw_rf_config = RF_MAX_TYPE; /* auto */ +int rtw_rf_config = RF_TYPE_AUTO; +module_param(rtw_rf_config, int, 0644); + +/* 0: not check in watch dog, 1: check in watch dog */ +int rtw_check_hw_status = 0; int rtw_low_power = 0; #ifdef CONFIG_WIFI_TEST -int rtw_wifi_spec = 1;/* for wifi test */ + int rtw_wifi_spec = 1;/* for wifi test */ #else -int rtw_wifi_spec = 0; + int rtw_wifi_spec = 0; #endif #ifdef CONFIG_DEFAULT_PATTERNS_EN -bool rtw_support_default_patterns = _TRUE; + bool rtw_support_default_patterns = _TRUE; #else -bool rtw_support_default_patterns = _FALSE; + bool rtw_support_default_patterns = _FALSE; #endif int rtw_special_rf_path = 0; /* 0: 2T2R ,1: only turn on path A 1T1R */ @@ -195,9 +255,9 @@ MODULE_PARM_DESC(rtw_excl_chs, "exclusive channel array"); /*if concurrent softap + p2p(GO) is needed, this param lets p2p response full channel list. But Softap must be SHUT DOWN once P2P decide to set up connection and become a GO.*/ #ifdef CONFIG_FULL_CH_IN_P2P_HANDSHAKE -int rtw_full_ch_in_p2p_handshake = 1; /* reply full channel list*/ + int rtw_full_ch_in_p2p_handshake = 1; /* reply full channel list*/ #else -int rtw_full_ch_in_p2p_handshake = 0; /* reply only softap channel*/ + int rtw_full_ch_in_p2p_handshake = 0; /* reply only softap channel*/ #endif #ifdef CONFIG_BT_COEXIST @@ -218,7 +278,7 @@ int rtw_AcceptAddbaReq = _TRUE;/* 0:Reject AP's Add BA req, 1:Accept AP's Add BA int rtw_antdiv_cfg = 2; /* 0:OFF , 1:ON, 2:decide by Efuse config */ int rtw_antdiv_type = 0 - ; /* 0:decide by efuse 1: for 88EE, 1Tx and 1RxCG are diversity.(2 Ant with SPDT), 2: for 88EE, 1Tx and 2Rx are diversity.( 2 Ant, Tx and RxCG are both on aux port, RxCS is on main port ), 3: for 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */ + ; /* 0:decide by efuse 1: for 88EE, 1Tx and 1RxCG are diversity.(2 Ant with SPDT), 2: for 88EE, 1Tx and 2Rx are diversity.( 2 Ant, Tx and RxCG are both on aux port, RxCS is on main port ), 3: for 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */ int rtw_drv_ant_band_switch = 1; /* 0:OFF , 1:ON, Driver control antenna band switch*/ @@ -253,6 +313,13 @@ int rtw_mc2u_disable = 0; int rtw_80211d = 0; #endif +#ifdef CONFIG_PCI_ASPM +/* CLK_REQ:BIT0 L0s:BIT1 ASPM_L1:BIT2 L1Off:BIT3*/ +int rtw_pci_aspm_enable = 0xF; +#else +int rtw_pci_aspm_enable; +#endif + #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV int rtw_force_ant = 2;/* 0 :normal, 1:Main ant, 2:Aux ant */ int rtw_force_igi = 0; /* 0 :normal */ @@ -285,9 +352,9 @@ module_param(ifname, charp, 0644); MODULE_PARM_DESC(ifname, "The default name to allocate for first interface"); #ifdef CONFIG_PLATFORM_ANDROID -char *if2name = "p2p%d"; + char *if2name = "p2p%d"; #else /* CONFIG_PLATFORM_ANDROID */ -char *if2name = "wlan%d"; + char *if2name = "wlan%d"; #endif /* CONFIG_PLATFORM_ANDROID */ module_param(if2name, charp, 0644); MODULE_PARM_DESC(if2name, "The default name to allocate for second interface"); @@ -296,12 +363,12 @@ char *rtw_initmac = 0; /* temp mac address if users want to use instead of the #ifdef CONFIG_CONCURRENT_MODE -#if (CONFIG_IFACE_NUMBER > 2) -int rtw_virtual_iface_num = CONFIG_IFACE_NUMBER - 1; -module_param(rtw_virtual_iface_num, int, 0644); -#else -int rtw_virtual_iface_num = 1; -#endif + #if (CONFIG_IFACE_NUMBER > 2) + int rtw_virtual_iface_num = CONFIG_IFACE_NUMBER - 1; + module_param(rtw_virtual_iface_num, int, 0644); + #else + int rtw_virtual_iface_num = 1; + #endif #endif @@ -326,15 +393,12 @@ module_param(rtw_ampdu_enable, int, 0644); module_param(rtw_rx_stbc, int, 0644); module_param(rtw_ampdu_amsdu, int, 0644); #endif /* CONFIG_80211N_HT */ -#ifdef CONFIG_80211AC_VHT -module_param(rtw_vht_enable, int, 0644); -#endif /* CONFIG_80211AC_VHT */ + #ifdef CONFIG_BEAMFORMING module_param(rtw_beamform_cap, int, 0644); #endif module_param(rtw_lowrate_two_xmit, int, 0644); -module_param(rtw_rf_config, int, 0644); module_param(rtw_power_mgnt, int, 0644); module_param(rtw_smart_ps, int, 0644); module_param(rtw_low_power, int, 0644); @@ -353,6 +417,11 @@ module_param(rtw_hwpdn_mode, int, 0644); module_param(rtw_hwpwrp_detect, int, 0644); module_param(rtw_hw_wps_pbc, int, 0644); +module_param(rtw_check_hw_status, int, 0644); + +#ifdef CONFIG_PCI_HCI +module_param(rtw_pci_aspm_enable, int, 0644); +#endif #ifdef CONFIG_TX_EARLY_MODE module_param(rtw_early_mode, int, 0644); @@ -426,16 +495,16 @@ MODULE_PARM_DESC(rtw_adaptivity_dc_backoff, "DC backoff for Adaptivity"); int rtw_adaptivity_th_l2h_ini = CONFIG_RTW_ADAPTIVITY_TH_L2H_INI; module_param(rtw_adaptivity_th_l2h_ini, int, 0644); -MODULE_PARM_DESC(rtw_adaptivity_th_l2h_ini, "TH_L2H_ini for Adaptivity"); +MODULE_PARM_DESC(rtw_adaptivity_th_l2h_ini, "th_l2h_ini for Adaptivity"); int rtw_adaptivity_th_edcca_hl_diff = CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF; module_param(rtw_adaptivity_th_edcca_hl_diff, int, 0644); -MODULE_PARM_DESC(rtw_adaptivity_th_edcca_hl_diff, "TH_EDCCA_HL_diff for Adaptivity"); +MODULE_PARM_DESC(rtw_adaptivity_th_edcca_hl_diff, "th_edcca_hl_diff for Adaptivity"); #ifdef CONFIG_DFS_MASTER uint rtw_dfs_region_domain = CONFIG_RTW_DFS_REGION_DOMAIN; module_param(rtw_dfs_region_domain, uint, 0644); -MODULE_PARM_DESC(rtw_dfs_region_domain, "1:FCC, 2:MKK, 3:ETSI"); +MODULE_PARM_DESC(rtw_dfs_region_domain, "0:UNKNOWN, 1:FCC, 2:MKK, 3:ETSI"); #endif uint rtw_amplifier_type_2g = CONFIG_RTW_AMPLIFIER_TYPE_2G; @@ -490,32 +559,19 @@ uint rtw_rxgain_offset_5gh = 0; module_param(rtw_rxgain_offset_5gh, uint, 0644); MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GL Offset value:0"); - uint rtw_pll_ref_clk_sel = CONFIG_RTW_PLL_REF_CLK_SEL; module_param(rtw_pll_ref_clk_sel, uint, 0644); MODULE_PARM_DESC(rtw_pll_ref_clk_sel, "force pll_ref_clk_sel, 0xF:use autoload value"); -#if defined(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY) /* eFuse: Regulatory selection=1 */ -int rtw_tx_pwr_lmt_enable = 1; -int rtw_tx_pwr_by_rate = 1; -#elif defined(CONFIG_CALIBRATE_TX_POWER_TO_MAX)/* eFuse: Regulatory selection=0 */ -int rtw_tx_pwr_lmt_enable = 0; -int rtw_tx_pwr_by_rate = 1; -#else /* eFuse: Regulatory selection=2 */ -#ifdef CONFIG_PCI_HCI -int rtw_tx_pwr_lmt_enable = 2; /* 2- Depend on efuse */ -int rtw_tx_pwr_by_rate = 2;/* 2- Depend on efuse */ -#else /* USB & SDIO */ -int rtw_tx_pwr_lmt_enable = 0; -int rtw_tx_pwr_by_rate = 0; -#endif -#endif +int rtw_tx_pwr_by_rate = CONFIG_TXPWR_BY_RATE_EN; +module_param(rtw_tx_pwr_by_rate, int, 0644); +MODULE_PARM_DESC(rtw_tx_pwr_by_rate, "0:Disable, 1:Enable, 2: Depend on efuse"); +#ifdef CONFIG_TXPWR_LIMIT +int rtw_tx_pwr_lmt_enable = CONFIG_TXPWR_LIMIT_EN; module_param(rtw_tx_pwr_lmt_enable, int, 0644); MODULE_PARM_DESC(rtw_tx_pwr_lmt_enable, "0:Disable, 1:Enable, 2: Depend on efuse"); - -module_param(rtw_tx_pwr_by_rate, int, 0644); -MODULE_PARM_DESC(rtw_tx_pwr_by_rate, "0:Disable, 1:Enable, 2: Depend on efuse"); +#endif static int rtw_target_tx_pwr_2g_a[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_A; static int rtw_target_tx_pwr_2g_a_num = 0; @@ -537,7 +593,7 @@ static int rtw_target_tx_pwr_2g_d_num = 0; module_param_array(rtw_target_tx_pwr_2g_d, int, &rtw_target_tx_pwr_2g_d_num, 0644); MODULE_PARM_DESC(rtw_target_tx_pwr_2g_d, "2.4G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined"); -#ifdef CONFIG_NL80211_BAND_5GHZ +#ifdef CONFIG_IEEE80211_BAND_5GHZ static int rtw_target_tx_pwr_5g_a[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_A; static int rtw_target_tx_pwr_5g_a_num = 0; module_param_array(rtw_target_tx_pwr_5g_a, int, &rtw_target_tx_pwr_5g_a_num, 0644); @@ -557,7 +613,7 @@ static int rtw_target_tx_pwr_5g_d[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_P static int rtw_target_tx_pwr_5g_d_num = 0; module_param_array(rtw_target_tx_pwr_5g_d, int, &rtw_target_tx_pwr_5g_d_num, 0644); MODULE_PARM_DESC(rtw_target_tx_pwr_5g_d, "5G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined"); -#endif /* CONFIG_NL80211_BAND_5GHZ */ +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE char *rtw_phy_file_path = REALTEK_CONFIG_PATH; @@ -579,13 +635,14 @@ module_param(rtw_decrypt_phy_file, int, 0644); MODULE_PARM_DESC(rtw_decrypt_phy_file, "Enable Decrypt PHY File"); #endif -#ifdef CONFIG_NAPI -static uint rtw_napi_debug = 0; -module_param(rtw_napi_debug, uint, 0644); -MODULE_PARM_DESC(rtw_napi_debug, "default rtw_napi_debug:0"); -static uint rtw_napi_weight = 64; -module_param(rtw_napi_weight, uint, 0644); -MODULE_PARM_DESC(rtw_napi_weight, "default rtw_napi_weight:64"); +#ifdef CONFIG_SUPPORT_TRX_SHARED +#ifdef DFT_TRX_SHARE_MODE +int rtw_trx_share_mode = DFT_TRX_SHARE_MODE; +#else +int rtw_trx_share_mode = 0; +#endif +module_param(rtw_trx_share_mode, int, 0644); +MODULE_PARM_DESC(rtw_trx_share_mode, "TRx FIFO Shared"); #endif int _netdev_open(struct net_device *pnetdev); @@ -606,6 +663,13 @@ int rtw_mcc_sta_bw20_target_tx_tp = MCC_STA_BW20_TARGET_TX_TP; int rtw_mcc_sta_bw40_target_tx_tp = MCC_STA_BW40_TARGET_TX_TP; int rtw_mcc_sta_bw80_target_tx_tp = MCC_STA_BW80_TARGET_TX_TP; int rtw_mcc_single_tx_cri = MCC_SINGLE_TX_CRITERIA; +int rtw_mcc_policy_table_idx = 0; +int rtw_mcc_duration = 0; +int rtw_mcc_tsf_sync_offset = 0; +int rtw_mcc_start_time_offset = 0; +int rtw_mcc_interval = 0; +int rtw_mcc_guard_offset0 = -1; +int rtw_mcc_guard_offset1 = -1; module_param(rtw_en_mcc, int, 0644); module_param(rtw_mcc_single_tx_cri, int, 0644); module_param(rtw_mcc_ap_bw20_target_tx_tp, int, 0644); @@ -614,9 +678,37 @@ module_param(rtw_mcc_ap_bw80_target_tx_tp, int, 0644); module_param(rtw_mcc_sta_bw20_target_tx_tp, int, 0644); module_param(rtw_mcc_sta_bw40_target_tx_tp, int, 0644); module_param(rtw_mcc_sta_bw80_target_tx_tp, int, 0644); +module_param(rtw_mcc_policy_table_idx, int, 0644); +module_param(rtw_mcc_duration, int, 0644); +module_param(rtw_mcc_tsf_sync_offset, int, 0644); +module_param(rtw_mcc_start_time_offset, int, 0644); +module_param(rtw_mcc_interval, int, 0644); +module_param(rtw_mcc_guard_offset0, int, 0644); +module_param(rtw_mcc_guard_offset1, int, 0644); #endif /*CONFIG_MCC_MODE */ -void rtw_regsty_load_target_tx_power(struct registry_priv *regsty) { +#ifdef CONFIG_RTW_NAPI +/*following setting should define NAPI in Makefile +enable napi only = 1, disable napi = 0*/ +int rtw_en_napi = 1; +module_param(rtw_en_napi, int, 0644); +#ifdef CONFIG_RTW_GRO +/*following setting should define GRO in Makefile +enable gro = 1, disable gro = 0*/ +int rtw_en_gro = 1; +module_param(rtw_en_gro, int, 0644); +#endif /* CONFIG_RTW_GRO */ +#endif /* CONFIG_RTW_NAPI */ + +#ifdef RTW_IQK_FW_OFFLOAD +int rtw_iqk_fw_offload = 1; +#else +int rtw_iqk_fw_offload; +#endif /* RTW_IQK_FW_OFFLOAD */ +module_param(rtw_iqk_fw_offload, int, 0644); + +void rtw_regsty_load_target_tx_power(struct registry_priv *regsty) +{ int path, rs; int *target_tx_pwr; @@ -634,7 +726,7 @@ void rtw_regsty_load_target_tx_power(struct registry_priv *regsty) { regsty->target_tx_pwr_2g[path][rs] = target_tx_pwr[rs]; } -#ifdef CONFIG_NL80211_BAND_5GHZ +#ifdef CONFIG_IEEE80211_BAND_5GHZ for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { if (path == RF_PATH_A) target_tx_pwr = rtw_target_tx_pwr_5g_a; @@ -648,10 +740,11 @@ void rtw_regsty_load_target_tx_power(struct registry_priv *regsty) { for (rs = OFDM; rs < RATE_SECTION_NUM; rs++) regsty->target_tx_pwr_5g[path][rs - 1] = target_tx_pwr[rs - 1]; } -#endif /* CONFIG_NL80211_BAND_5GHZ */ +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ } -inline void rtw_regsty_load_excl_chs(struct registry_priv *regsty) { +inline void rtw_regsty_load_excl_chs(struct registry_priv *regsty) +{ int i; int ch_num = 0; @@ -663,11 +756,33 @@ inline void rtw_regsty_load_excl_chs(struct registry_priv *regsty) { regsty->excl_chs[ch_num] = 0; } -uint loadparam(_adapter *padapter) { +#ifdef CONFIG_80211N_HT +inline void rtw_regsty_init_rx_ampdu_sz_limit(struct registry_priv *regsty) +{ + int i, j; + uint *sz_limit; + + for (i = 0; i < 4; i++) { + if (i == 0) + sz_limit = rtw_rx_ampdu_sz_limit_1ss; + else if (i == 1) + sz_limit = rtw_rx_ampdu_sz_limit_2ss; + else if (i == 2) + sz_limit = rtw_rx_ampdu_sz_limit_3ss; + else if (i == 3) + sz_limit = rtw_rx_ampdu_sz_limit_4ss; + + for (j = 0; j < 4; j++) + regsty->rx_ampdu_sz_limit_by_nss_bw[i][j] = sz_limit[j]; + } +} +#endif /* CONFIG_80211N_HT */ + +uint loadparam(_adapter *padapter) +{ uint status = _SUCCESS; struct registry_priv *registry_par = &padapter->registrypriv; - _func_enter_; #ifdef CONFIG_RTW_DEBUG if (rtw_drv_log_level >= _DRV_MAX_) @@ -686,11 +801,11 @@ uint loadparam(_adapter *padapter) { registry_par->channel = (u8)rtw_channel; registry_par->wireless_mode = (u8)rtw_wireless_mode; - if (IsSupported24G(registry_par->wireless_mode) && (!IsSupported5G(registry_par->wireless_mode)) - && (registry_par->channel > 14)) + if (IsSupported24G(registry_par->wireless_mode) && (!is_supported_5g(registry_par->wireless_mode)) + && (registry_par->channel > 14)) registry_par->channel = 1; - else if (IsSupported5G(registry_par->wireless_mode) && (!IsSupported24G(registry_par->wireless_mode)) - && (registry_par->channel <= 14)) + else if (is_supported_5g(registry_par->wireless_mode) && (!IsSupported24G(registry_par->wireless_mode)) + && (registry_par->channel <= 14)) registry_par->channel = 36; registry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense ; @@ -705,6 +820,7 @@ uint loadparam(_adapter *padapter) { registry_par->check_fw_ps = (u8)rtw_check_fw_ps; registry_par->power_mgnt = (u8)rtw_power_mgnt; registry_par->ips_mode = (u8)rtw_ips_mode; + registry_par->lps_level = (u8)rtw_lps_level; registry_par->radio_enable = (u8)rtw_radio_enable; registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt; registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt; @@ -712,11 +828,15 @@ uint loadparam(_adapter *padapter) { /* registry_par->qos_enable = (u8)rtw_qos_enable; */ registry_par->ack_policy = (u8)rtw_ack_policy; registry_par->mp_mode = (u8)rtw_mp_mode; +#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR) + registry_par->mp_customer_str = (u8)rtw_mp_customer_str; +#endif registry_par->software_encrypt = (u8)rtw_software_encrypt; registry_par->software_decrypt = (u8)rtw_software_decrypt; registry_par->acm_method = (u8)rtw_acm_method; registry_par->usb_rxagg_mode = (u8)rtw_usb_rxagg_mode; + registry_par->dynamic_agg_enable = (u8)rtw_dynamic_agg_enable; /* UAPSD */ registry_par->wmm_enable = (u8)rtw_wmm_enable; @@ -729,6 +849,8 @@ uint loadparam(_adapter *padapter) { registry_par->RegPwrTrimEnable = (u8)rtw_pwrtrim_enable; + registry_par->tx_bw_mode = (u8)rtw_tx_bw_mode; + #ifdef CONFIG_80211N_HT registry_par->ht_enable = (u8)rtw_ht_enable; registry_par->bw_mode = (u8)rtw_bw_mode; @@ -741,12 +863,14 @@ uint loadparam(_adapter *padapter) { registry_par->beamform_cap = (u8)rtw_beamform_cap; registry_par->beamformer_rf_num = (u8)rtw_bfer_rf_number; registry_par->beamformee_rf_num = (u8)rtw_bfee_rf_number; + rtw_regsty_init_rx_ampdu_sz_limit(registry_par); #endif #ifdef CONFIG_80211AC_VHT registry_par->vht_enable = (u8)rtw_vht_enable; registry_par->ampdu_factor = (u8)rtw_ampdu_factor; - registry_par->vht_rate_sel = (u8)rtw_vht_rate_sel; + registry_par->vht_rx_mcs_map[0] = (u8)(rtw_vht_rx_mcs_map & 0xFF); + registry_par->vht_rx_mcs_map[1] = (u8)((rtw_vht_rx_mcs_map & 0xFF00) >> 8); #endif #ifdef CONFIG_TX_EARLY_MODE @@ -756,13 +880,14 @@ uint loadparam(_adapter *padapter) { registry_par->rf_config = (u8)rtw_rf_config; registry_par->low_power = (u8)rtw_low_power; + registry_par->check_hw_status = (u8)rtw_check_hw_status; registry_par->wifi_spec = (u8)rtw_wifi_spec; if (strlen(rtw_country_code) != 2 - || is_alpha(rtw_country_code[0]) == _FALSE - || is_alpha(rtw_country_code[1]) == _FALSE - ) { + || is_alpha(rtw_country_code[0]) == _FALSE + || is_alpha(rtw_country_code[1]) == _FALSE + ) { if (rtw_country_code != rtw_country_unspecified) RTW_ERR("%s discard rtw_country_code not in alpha2\n", __func__); _rtw_memset(registry_par->alpha2, 0xFF, 2); @@ -840,12 +965,13 @@ uint loadparam(_adapter *padapter) { registry_par->pll_ref_clk_sel = (u8)rtw_pll_ref_clk_sel; +#ifdef CONFIG_TXPWR_LIMIT registry_par->RegEnableTxPowerLimit = (u8)rtw_tx_pwr_lmt_enable; +#endif registry_par->RegEnableTxPowerByRate = (u8)rtw_tx_pwr_by_rate; rtw_regsty_load_target_tx_power(registry_par); - registry_par->RegPowerBase = 14; registry_par->TxBBSwing_2G = (s8)rtw_TxBBSwing_2G; registry_par->TxBBSwing_5G = (s8)rtw_TxBBSwing_5G; registry_par->bEn_RFE = 1; @@ -884,11 +1010,6 @@ uint loadparam(_adapter *padapter) { registry_par->dfs_region_domain = (u8)rtw_dfs_region_domain; #endif -#ifdef CONFIG_NAPI - registry_par->napi_debug = (u8) rtw_napi_debug; - registry_par->napi_weight = (u16) rtw_napi_weight; -#endif - #ifdef CONFIG_MCC_MODE registry_par->en_mcc = (u8)rtw_en_mcc; registry_par->rtw_mcc_ap_bw20_target_tx_tp = (u32)rtw_mcc_ap_bw20_target_tx_tp; @@ -898,12 +1019,38 @@ uint loadparam(_adapter *padapter) { registry_par->rtw_mcc_sta_bw40_target_tx_tp = (u32)rtw_mcc_sta_bw40_target_tx_tp; registry_par->rtw_mcc_sta_bw80_target_tx_tp = (u32)rtw_mcc_sta_bw80_target_tx_tp; registry_par->rtw_mcc_single_tx_cri = (u32)rtw_mcc_single_tx_cri; + registry_par->rtw_mcc_policy_table_idx = rtw_mcc_policy_table_idx; + registry_par->rtw_mcc_duration = (u8)rtw_mcc_duration; + registry_par->rtw_mcc_tsf_sync_offset = (u8)rtw_mcc_tsf_sync_offset; + registry_par->rtw_mcc_start_time_offset = (u8)rtw_mcc_start_time_offset; + registry_par->rtw_mcc_interval = (u8)rtw_mcc_interval; + registry_par->rtw_mcc_guard_offset0 = rtw_mcc_guard_offset0; + registry_par->rtw_mcc_guard_offset1 = rtw_mcc_guard_offset1; #endif /*CONFIG_MCC_MODE */ #ifdef CONFIG_DEFAULT_PATTERNS_EN registry_par->default_patterns_en = rtw_support_default_patterns; #endif - _func_exit_; +#ifdef CONFIG_SUPPORT_TRX_SHARED + registry_par->trx_share_mode = rtw_trx_share_mode; +#endif + +#ifdef CONFIG_PCI_HCI + registry_par->pci_aspm_config = rtw_pci_aspm_enable; +#endif + +#ifdef CONFIG_RTW_NAPI + registry_par->en_napi = (u8)rtw_en_napi; +#ifdef CONFIG_RTW_GRO + registry_par->en_gro = (u8)rtw_en_gro; + if (!registry_par->en_napi && registry_par->en_gro) { + registry_par->en_gro = 0; + RTW_WARN("Disable GRO because NAPI is not enabled\n"); + } +#endif /* CONFIG_RTW_GRO */ +#endif /* CONFIG_RTW_NAPI */ + + registry_par->iqk_fw_offload = (u8)rtw_iqk_fw_offload; return status; } @@ -924,7 +1071,8 @@ uint loadparam(_adapter *padapter) { * Auther: Arvin Liu * Date: 2015/05/29 */ -static int rtw_net_set_mac_address(struct net_device *pnetdev, void *addr) { +static int rtw_net_set_mac_address(struct net_device *pnetdev, void *addr) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct sockaddr *sa = (struct sockaddr *)addr; @@ -933,17 +1081,17 @@ static int rtw_net_set_mac_address(struct net_device *pnetdev, void *addr) { /* only the net_device is in down state to permit modifying mac addr */ if ((pnetdev->flags & IFF_UP) == _TRUE) { RTW_INFO(FUNC_ADPT_FMT": The net_device's is not in down state\n" - , FUNC_ADPT_ARG(padapter)); + , FUNC_ADPT_ARG(padapter)); return ret; } /* if the net_device is linked, it's not permit to modify mac addr */ if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) || - check_fwstate(pmlmepriv, _FW_LINKED) || - check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) { + check_fwstate(pmlmepriv, _FW_LINKED) || + check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) { RTW_INFO(FUNC_ADPT_FMT": The net_device's is not idle currently\n" - , FUNC_ADPT_ARG(padapter)); + , FUNC_ADPT_ARG(padapter)); return ret; } @@ -951,7 +1099,7 @@ static int rtw_net_set_mac_address(struct net_device *pnetdev, void *addr) { /* check whether the input mac address is valid to permit modifying mac addr */ if (rtw_check_invalid_mac_address(sa->sa_data, _FALSE) == _TRUE) { RTW_INFO(FUNC_ADPT_FMT": Invalid Mac Addr for "MAC_FMT"\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data)); + , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data)); return ret; } @@ -984,14 +1132,15 @@ static int rtw_net_set_mac_address(struct net_device *pnetdev, void *addr) { #endif RTW_INFO(FUNC_ADPT_FMT": Set Mac Addr to "MAC_FMT" Successfully\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data)); + , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data)); ret = 0; return ret; } -static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev) { +static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct recv_priv *precvpriv = &(padapter->recvpriv); @@ -1018,7 +1167,8 @@ static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev) { static const u16 rtw_1d_to_queue[8] = { 2, 3, 3, 2, 1, 1, 0, 0 }; /* Given a data frame determine the 802.1p/1d tag to use. */ -unsigned int rtw_classify8021d(struct sk_buff *skb) { +unsigned int rtw_classify8021d(struct sk_buff *skb) +{ unsigned int dscp; /* skb->priority values from 256->263 are magic values to @@ -1043,13 +1193,13 @@ unsigned int rtw_classify8021d(struct sk_buff *skb) { static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) - , void *accel_priv -#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) - , select_queue_fallback_t fallback -#endif - + , void *accel_priv + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) + , select_queue_fallback_t fallback + #endif #endif - ) { +) +{ _adapter *padapter = rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -1061,7 +1211,8 @@ static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb return rtw_1d_to_queue[skb->priority]; } -u16 rtw_recv_select_queue(struct sk_buff *skb) { +u16 rtw_recv_select_queue(struct sk_buff *skb) +{ struct iphdr *piphdr; unsigned int dscp; u16 eth_type; @@ -1089,37 +1240,43 @@ u16 rtw_recv_select_queue(struct sk_buff *skb) { } #endif -static int rtw_ndev_notifier_call(struct notifier_block *nb, unsigned long state, void *ptr) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) - struct net_device *dev = netdev_notifier_info_to_dev(ptr); + +static u8 is_rtw_ndev(struct net_device *ndev) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) + return ndev->netdev_ops + && ndev->netdev_ops->ndo_do_ioctl + && ndev->netdev_ops->ndo_do_ioctl == rtw_ioctl; #else - struct net_device *dev = ptr; + return ndev->do_ioctl + && ndev->do_ioctl == rtw_ioctl; #endif +} - if (dev == NULL) - return NOTIFY_DONE; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) - if (dev->netdev_ops == NULL) - return NOTIFY_DONE; +static int rtw_ndev_notifier_call(struct notifier_block *nb, unsigned long state, void *ptr) +{ + struct net_device *ndev; - if (dev->netdev_ops->ndo_do_ioctl == NULL) + if (ptr == NULL) return NOTIFY_DONE; - if (dev->netdev_ops->ndo_do_ioctl != rtw_ioctl) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + ndev = netdev_notifier_info_to_dev(ptr); #else - if (dev->do_ioctl == NULL) + ndev = ptr; +#endif + + if (ndev == NULL) return NOTIFY_DONE; - if (dev->do_ioctl != rtw_ioctl) -#endif + if (!is_rtw_ndev(ndev)) return NOTIFY_DONE; - RTW_INFO(FUNC_NDEV_FMT" state:%lu\n", FUNC_NDEV_ARG(dev), state); + RTW_INFO(FUNC_NDEV_FMT" state:%lu\n", FUNC_NDEV_ARG(ndev), state); switch (state) { case NETDEV_CHANGENAME: - rtw_adapter_proc_replace(dev); + rtw_adapter_proc_replace(ndev); break; } @@ -1130,20 +1287,22 @@ static struct notifier_block rtw_ndev_notifier = { .notifier_call = rtw_ndev_notifier_call, }; -int rtw_ndev_notifier_register(void) { +int rtw_ndev_notifier_register(void) +{ return register_netdevice_notifier(&rtw_ndev_notifier); } -void rtw_ndev_notifier_unregister(void) { +void rtw_ndev_notifier_unregister(void) +{ unregister_netdevice_notifier(&rtw_ndev_notifier); } - -int rtw_ndev_init(struct net_device *dev) { +int rtw_ndev_init(struct net_device *dev) +{ _adapter *adapter = rtw_netdev_priv(dev); RTW_PRINT(FUNC_ADPT_FMT" if%d mac_addr="MAC_FMT"\n" - , FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1), MAC_ARG(dev->dev_addr)); + , FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1), MAC_ARG(dev->dev_addr)); strncpy(adapter->old_ifname, dev->name, IFNAMSIZ); adapter->old_ifname[IFNAMSIZ - 1] = '\0'; rtw_adapter_proc_init(dev); @@ -1151,11 +1310,12 @@ int rtw_ndev_init(struct net_device *dev) { return 0; } -void rtw_ndev_uninit(struct net_device *dev) { +void rtw_ndev_uninit(struct net_device *dev) +{ _adapter *adapter = rtw_netdev_priv(dev); RTW_PRINT(FUNC_ADPT_FMT" if%d\n" - , FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1)); + , FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1)); rtw_adapter_proc_deinit(dev); } @@ -1175,7 +1335,8 @@ static const struct net_device_ops rtw_netdev_ops = { }; #endif -int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname) { +int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname) +{ _adapter *padapter = rtw_netdev_priv(pnetdev); #ifdef CONFIG_EASY_REPLACEMENT @@ -1212,7 +1373,7 @@ int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname) { #endif /* CONFIG_EASY_REPLACEMENT */ if (dev_alloc_name(pnetdev, ifname) < 0) - RT_TRACE(_module_os_intfs_c_, _drv_err_, ("dev_alloc_name, fail!\n")); + RTW_ERR("dev_alloc_name, fail!\n"); netif_carrier_off(pnetdev); /* rtw_netif_stop_queue(pnetdev); */ @@ -1220,7 +1381,8 @@ int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname) { return 0; } -void rtw_hook_if_ops(struct net_device *ndev) { +void rtw_hook_if_ops(struct net_device *ndev) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ndev->netdev_ops = &rtw_netdev_ops; #else @@ -1235,15 +1397,18 @@ void rtw_hook_if_ops(struct net_device *ndev) { #endif } -struct net_device *rtw_init_netdev(_adapter *old_padapter) { +#ifdef CONFIG_CONCURRENT_MODE +static void rtw_hook_vir_if_ops(struct net_device *ndev); +#endif +struct net_device *rtw_init_netdev(_adapter *old_padapter) +{ _adapter *padapter; struct net_device *pnetdev; - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("+init_net_dev\n")); - - if (old_padapter != NULL) + if (old_padapter != NULL) { + rtw_os_ndev_free(old_padapter); pnetdev = rtw_alloc_etherdev_with_old_priv(sizeof(_adapter), (void *)old_padapter); - else + } else pnetdev = rtw_alloc_etherdev(sizeof(_adapter)); if (!pnetdev) @@ -1257,6 +1422,10 @@ struct net_device *rtw_init_netdev(_adapter *old_padapter) { #endif rtw_hook_if_ops(pnetdev); +#ifdef CONFIG_CONCURRENT_MODE + if (!is_primary_adapter(padapter)) + rtw_hook_vir_if_ops(pnetdev); +#endif /* CONFIG_CONCURRENT_MODE */ #ifdef CONFIG_TCP_CSUM_OFFLOAD_TX pnetdev->features |= NETIF_F_IP_CSUM; @@ -1277,7 +1446,8 @@ struct net_device *rtw_init_netdev(_adapter *old_padapter) { return pnetdev; } -int rtw_os_ndev_alloc(_adapter *adapter) { +int rtw_os_ndev_alloc(_adapter *adapter) +{ int ret = _FAIL; struct net_device *ndev = NULL; @@ -1312,7 +1482,8 @@ int rtw_os_ndev_alloc(_adapter *adapter) { return ret; } -void rtw_os_ndev_free(_adapter *adapter) { +void rtw_os_ndev_free(_adapter *adapter) +{ #if defined(CONFIG_IOCTL_CFG80211) rtw_cfg80211_ndev_res_free(adapter); #endif @@ -1323,9 +1494,16 @@ void rtw_os_ndev_free(_adapter *adapter) { } } -int rtw_os_ndev_register(_adapter *adapter, char *name) { +int rtw_os_ndev_register(_adapter *adapter, const char *name) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); int ret = _SUCCESS; struct net_device *ndev = adapter->pnetdev; + u8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj); + +#ifdef CONFIG_RTW_NAPI + netif_napi_add(ndev, &adapter->napi, rtw_recv_napi_poll, RTL_NAPI_WEIGHT); +#endif /* CONFIG_RTW_NAPI */ #if defined(CONFIG_IOCTL_CFG80211) if (rtw_cfg80211_ndev_res_register(adapter) != _SUCCESS) { @@ -1335,34 +1513,50 @@ int rtw_os_ndev_register(_adapter *adapter, char *name) { } #endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) + ndev->gro_flush_timeout = 100000; +#endif + /* alloc netdev name */ rtw_init_netdev_name(ndev, name); _rtw_memcpy(ndev->dev_addr, adapter_mac_addr(adapter), ETH_ALEN); /* Tell the network stack we exist */ - if (register_netdev(ndev) != 0) { + + if (rtnl_lock_needed) + ret = (register_netdev(ndev) == 0) ? _SUCCESS : _FAIL; + else + ret = (register_netdevice(ndev) == 0) ? _SUCCESS : _FAIL; + + if (ret == _SUCCESS) + adapter->registered = 1; + else RTW_INFO(FUNC_NDEV_FMT" if%d Failed!\n", FUNC_NDEV_ARG(ndev), (adapter->iface_id + 1)); - ret = _FAIL; - } #if defined(CONFIG_IOCTL_CFG80211) if (ret != _SUCCESS) { rtw_cfg80211_ndev_res_unregister(adapter); -#if !defined(RTW_SINGLE_WIPHY) + #if !defined(RTW_SINGLE_WIPHY) rtw_wiphy_unregister(adapter_to_wiphy(adapter)); -#endif + #endif } #endif exit: +#ifdef CONFIG_RTW_NAPI + if (ret != _SUCCESS) + netif_napi_del(&adapter->napi); +#endif /* CONFIG_RTW_NAPI */ + return ret; } -void rtw_os_ndev_unregister(_adapter *adapter) { +void rtw_os_ndev_unregister(_adapter *adapter) +{ struct net_device *netdev = NULL; - if (adapter == NULL) + if (adapter == NULL || adapter->registered == 0) return; adapter->ndev_unregistering = 1; @@ -1373,13 +1567,29 @@ void rtw_os_ndev_unregister(_adapter *adapter) { rtw_cfg80211_ndev_res_unregister(adapter); #endif - if ((adapter->DriverState != DRIVER_DISAPPEAR) && netdev) - unregister_netdev(netdev); /* will call netdev_close() */ + if ((adapter->DriverState != DRIVER_DISAPPEAR) && netdev) { + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj); + + if (rtnl_lock_needed) + unregister_netdev(netdev); + else + unregister_netdevice(netdev); + } #if defined(CONFIG_IOCTL_CFG80211) && !defined(RTW_SINGLE_WIPHY) rtw_wiphy_unregister(adapter_to_wiphy(adapter)); #endif +#ifdef CONFIG_RTW_NAPI + if (adapter->napi_state == NAPI_ENABLE) { + napi_disable(&adapter->napi); + adapter->napi_state = NAPI_DISABLE; + } + netif_napi_del(&adapter->napi); +#endif /* CONFIG_RTW_NAPI */ + + adapter->registered = 0; adapter->ndev_unregistering = 0; } @@ -1391,7 +1601,8 @@ void rtw_os_ndev_unregister(_adapter *adapter) { * Returns: * _SUCCESS or _FAIL */ -int rtw_os_ndev_init(_adapter *adapter, char *name) { +int rtw_os_ndev_init(_adapter *adapter, const char *name) +{ int ret = _FAIL; if (rtw_os_ndev_alloc(adapter) != _SUCCESS) @@ -1413,12 +1624,14 @@ int rtw_os_ndev_init(_adapter *adapter, char *name) { * rtw_os_ndev_deinit - Unregister and free OS layer net device and relating structures for @adapter * @adapter: the adapter on which this function applies */ -void rtw_os_ndev_deinit(_adapter *adapter) { +void rtw_os_ndev_deinit(_adapter *adapter) +{ rtw_os_ndev_unregister(adapter); rtw_os_ndev_free(adapter); } -int rtw_os_ndevs_alloc(struct dvobj_priv *dvobj) { +int rtw_os_ndevs_alloc(struct dvobj_priv *dvobj) +{ int i, status = _SUCCESS; _adapter *adapter; @@ -1440,6 +1653,12 @@ int rtw_os_ndevs_alloc(struct dvobj_priv *dvobj) { adapter = dvobj->padapters[i]; if (adapter && !adapter->pnetdev) { + + #ifdef CONFIG_RTW_DYNAMIC_NDEV + if (!is_primary_adapter(adapter)) + continue; + #endif + status = rtw_os_ndev_alloc(adapter); if (status != _SUCCESS) { rtw_warn_on(1); @@ -1464,7 +1683,8 @@ int rtw_os_ndevs_alloc(struct dvobj_priv *dvobj) { return status; } -void rtw_os_ndevs_free(struct dvobj_priv *dvobj) { +void rtw_os_ndevs_free(struct dvobj_priv *dvobj) +{ int i; _adapter *adapter = NULL; @@ -1489,10 +1709,10 @@ void rtw_os_ndevs_free(struct dvobj_priv *dvobj) { #endif } -u32 rtw_start_drv_threads(_adapter *padapter) { +u32 rtw_start_drv_threads(_adapter *padapter) +{ u32 _status = _SUCCESS; - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("+rtw_start_drv_threads\n")); #ifdef CONFIG_XMIT_THREAD_MODE #if defined(CONFIG_SDIO_HCI) @@ -1500,30 +1720,40 @@ u32 rtw_start_drv_threads(_adapter *padapter) { #endif { padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD"); - if (IS_ERR(padapter->xmitThread)) + if (IS_ERR(padapter->xmitThread)) { + padapter->xmitThread = NULL; _status = _FAIL; + } } #endif /* #ifdef CONFIG_XMIT_THREAD_MODE */ #ifdef CONFIG_RECV_THREAD_MODE - padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD"); - if (IS_ERR(padapter->recvThread)) - _status = _FAIL; + if (is_primary_adapter(padapter)) { + padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD"); + if (IS_ERR(padapter->recvThread)) { + padapter->recvThread = NULL; + _status = _FAIL; + } + } #endif if (is_primary_adapter(padapter)) { padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD"); - if (IS_ERR(padapter->cmdThread)) + if (IS_ERR(padapter->cmdThread)) { + padapter->cmdThread = NULL; _status = _FAIL; + } else - _rtw_down_sema(&padapter->cmdpriv.terminate_cmdthread_sema); /* wait for cmd_thread to run */ + _rtw_down_sema(&padapter->cmdpriv.start_cmdthread_sema); /* wait for cmd_thread to run */ } #ifdef CONFIG_EVENT_THREAD_MODE padapter->evtThread = kthread_run(event_thread, padapter, "RTW_EVENT_THREAD"); - if (IS_ERR(padapter->evtThread)) + if (IS_ERR(padapter->evtThread)) { + padapter->evtThread = NULL; _status = _FAIL; + } #endif rtw_hal_start_thread(padapter); @@ -1531,16 +1761,18 @@ u32 rtw_start_drv_threads(_adapter *padapter) { } -void rtw_stop_drv_threads(_adapter *padapter) { - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("+rtw_stop_drv_threads\n")); +void rtw_stop_drv_threads(_adapter *padapter) +{ if (is_primary_adapter(padapter)) rtw_stop_cmd_thread(padapter); #ifdef CONFIG_EVENT_THREAD_MODE - _rtw_up_sema(&padapter->evtpriv.evt_notify); - if (padapter->evtThread) - _rtw_down_sema(&padapter->evtpriv.terminate_evtthread_sema); + if (padapter->evtThread) { + _rtw_up_sema(&padapter->evtpriv.evt_notify); + rtw_thread_stop(padapter->evtThread); + padapter->evtThread = NULL; + } #endif #ifdef CONFIG_XMIT_THREAD_MODE @@ -1550,24 +1782,29 @@ void rtw_stop_drv_threads(_adapter *padapter) { if (is_primary_adapter(padapter)) #endif /*SDIO_HCI */ { - _rtw_up_sema(&padapter->xmitpriv.xmit_sema); - _rtw_down_sema(&padapter->xmitpriv.terminate_xmitthread_sema); + if (padapter->xmitThread) { + _rtw_up_sema(&padapter->xmitpriv.xmit_sema); + rtw_thread_stop(padapter->xmitThread); + padapter->xmitThread = NULL; + } } - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("\n drv_halt: rtw_xmit_thread can be terminated !\n")); #endif #ifdef CONFIG_RECV_THREAD_MODE - /* Below is to termindate rx_thread... */ - _rtw_up_sema(&padapter->recvpriv.recv_sema); - _rtw_down_sema(&padapter->recvpriv.terminate_recvthread_sema); - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("\n drv_halt:recv_thread can be terminated!\n")); + if (is_primary_adapter(padapter) && padapter->recvThread) { + /* Below is to termindate rx_thread... */ + _rtw_up_sema(&padapter->recvpriv.recv_sema); + rtw_thread_stop(padapter->recvThread); + padapter->recvThread = NULL; + } #endif rtw_hal_stop_thread(padapter); } u8 rtw_init_default_value(_adapter *padapter); -u8 rtw_init_default_value(_adapter *padapter) { +u8 rtw_init_default_value(_adapter *padapter) +{ u8 ret = _SUCCESS; struct registry_priv *pregistrypriv = &padapter->registrypriv; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; @@ -1629,31 +1866,43 @@ u8 rtw_init_default_value(_adapter *padapter) { padapter->fix_rate = 0xFF; padapter->data_fb = 0; padapter->fix_bw = 0xFF; + padapter->power_offset = 0; + padapter->rsvd_page_offset = 0; + padapter->rsvd_page_num = 0; + + padapter->driver_tx_bw_mode = pregistrypriv->tx_bw_mode; + padapter->driver_ampdu_spacing = 0xFF; padapter->driver_rx_ampdu_factor = 0xFF; padapter->driver_rx_ampdu_spacing = 0xFF; padapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID; padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID; +#ifdef CONFIG_TX_AMSDU padapter->tx_amsdu = 2; padapter->tx_amsdu_rate = 400; +#endif + padapter->driver_tx_max_agg_num = 0xFF; #ifdef DBG_RX_COUNTER_DUMP padapter->dump_rx_cnt_mode = 0; padapter->drv_rx_cnt_ok = 0; padapter->drv_rx_cnt_crcerror = 0; padapter->drv_rx_cnt_drop = 0; #endif - return ret; -} +#ifdef CONFIG_RTW_NAPI + padapter->napi_state = NAPI_DISABLE; +#endif + padapter->tsf.sync_port = MAX_HW_PORT; + padapter->tsf.offset = 0; -#ifdef CONFIG_SWTIMER_BASED_TXBCN -void _tx_beacon_timer_handlder(void *FunctionContext) { - struct dvobj_priv *pdvobj = (struct dvobj_priv *)FunctionContext; +#ifdef CONFIG_CHNL_LOAD_MAGT + padapter->clm_flag = FALSE; +#endif - tx_beacon_timer_handlder(pdvobj); + return ret; } -#endif -struct dvobj_priv *devobj_init(void) { +struct dvobj_priv *devobj_init(void) +{ struct dvobj_priv *pdvobj = NULL; pdvobj = (struct dvobj_priv *)rtw_zmalloc(sizeof(*pdvobj)); @@ -1669,6 +1918,11 @@ struct dvobj_priv *devobj_init(void) { _rtw_mutex_init(&pdvobj->sd_indirect_access_mutex); #endif +#ifdef CONFIG_RTW_CUSTOMER_STR + _rtw_mutex_init(&pdvobj->customer_str_mutex); + _rtw_memset(pdvobj->customer_str, 0xFF, RTW_CUSTOMER_STR_LEN); +#endif + pdvobj->processing_dev_remove = _FALSE; ATOMIC_SET(&pdvobj->disable_func, 0); @@ -1676,7 +1930,7 @@ struct dvobj_priv *devobj_init(void) { rtw_macid_ctl_init(&pdvobj->macid_ctl); _rtw_spinlock_init(&pdvobj->cam_ctl.lock); _rtw_mutex_init(&pdvobj->cam_ctl.sec_cam_access_mutex); -#ifdef RTK_129X_PLATFORM +#if defined(RTK_129X_PLATFORM) && defined(CONFIG_PCI_HCI) _rtw_spinlock_init(&pdvobj->io_reg_lock); #endif #ifdef CONFIG_MBSSID_CAM @@ -1688,10 +1942,12 @@ struct dvobj_priv *devobj_init(void) { pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL; /* default value is equal to the default beacon_interval (100ms) */ _rtw_init_queue(&pdvobj->ap_if_q); #ifdef CONFIG_SWTIMER_BASED_TXBCN - _init_timer(&(pdvobj->txbcn_timer), NULL, _tx_beacon_timer_handlder, pdvobj); + rtw_init_timer(&(pdvobj->txbcn_timer), NULL, tx_beacon_timer_handlder, pdvobj); #endif #endif + rtw_init_timer(&(pdvobj->dynamic_chk_timer), NULL, rtw_dynamic_check_timer_handlder, pdvobj); + #ifdef CONFIG_MCC_MODE _rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_mutex)); _rtw_spinlock_init(&pdvobj->mcc_objpriv.mcc_lock); @@ -1701,7 +1957,8 @@ struct dvobj_priv *devobj_init(void) { } -void devobj_deinit(struct dvobj_priv *pdvobj) { +void devobj_deinit(struct dvobj_priv *pdvobj) +{ if (!pdvobj) return; @@ -1717,6 +1974,11 @@ void devobj_deinit(struct dvobj_priv *pdvobj) { _rtw_mutex_free(&pdvobj->hw_init_mutex); _rtw_mutex_free(&pdvobj->h2c_fwcmd_mutex); + +#ifdef CONFIG_RTW_CUSTOMER_STR + _rtw_mutex_free(&pdvobj->customer_str_mutex); +#endif + _rtw_mutex_free(&pdvobj->setch_mutex); _rtw_mutex_free(&pdvobj->setbw_mutex); _rtw_mutex_free(&pdvobj->rf_read_reg_mutex); @@ -1728,7 +1990,7 @@ void devobj_deinit(struct dvobj_priv *pdvobj) { _rtw_spinlock_free(&pdvobj->cam_ctl.lock); _rtw_mutex_free(&pdvobj->cam_ctl.sec_cam_access_mutex); -#ifdef RTK_129X_PLATFORM +#if defined(RTK_129X_PLATFORM) && defined(CONFIG_PCI_HCI) _rtw_spinlock_free(&pdvobj->io_reg_lock); #endif #ifdef CONFIG_MBSSID_CAM @@ -1740,7 +2002,42 @@ void devobj_deinit(struct dvobj_priv *pdvobj) { rtw_mfree((u8 *)pdvobj, sizeof(*pdvobj)); } -u8 rtw_reset_drv_sw(_adapter *padapter) { +inline u8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj) +{ + if (dvobj->rtnl_lock_holder && dvobj->rtnl_lock_holder == current) + return 0; + return 1; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)) +static inline int rtnl_is_locked(void) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 17)) + if (unlikely(rtnl_trylock())) { + rtnl_unlock(); +#else + if (unlikely(down_trylock(&rtnl_sem) == 0)) { + up(&rtnl_sem); +#endif + return 0; + } + return 1; +} +#endif + +inline void rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl) +{ + rtw_warn_on(!rtnl_is_locked()); + + if (!thd_hdl || rtnl_is_locked()) + dvobj->rtnl_lock_holder = thd_hdl; + + if (dvobj->rtnl_lock_holder && 0) + RTW_INFO("rtnl_lock_holder: %s:%d\n", current->comm, current->pid); +} + +u8 rtw_reset_drv_sw(_adapter *padapter) +{ u8 ret8 = _SUCCESS; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); @@ -1751,6 +2048,10 @@ u8 rtw_reset_drv_sw(_adapter *padapter) { RTW_ENABLE_FUNC(padapter, DF_RX_BIT); RTW_ENABLE_FUNC(padapter, DF_TX_BIT); + + padapter->tsf.sync_port = MAX_HW_PORT; + padapter->tsf.offset = 0; + padapter->bLinkInfoDump = 0; padapter->xmitpriv.tx_pkts = 0; @@ -1787,20 +2088,18 @@ u8 rtw_reset_drv_sw(_adapter *padapter) { } -u8 rtw_init_drv_sw(_adapter *padapter) { +u8 rtw_init_drv_sw(_adapter *padapter) +{ u8 ret8 = _SUCCESS; - _func_enter_; - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("+rtw_init_drv_sw\n")); _rtw_init_listhead(&padapter->list); ret8 = rtw_init_default_value(padapter); if ((rtw_init_cmd_priv(&padapter->cmdpriv)) == _FAIL) { - RT_TRACE(_module_os_intfs_c_, _drv_err_, ("\n Can't init cmd_priv\n")); ret8 = _FAIL; goto exit; } @@ -1808,15 +2107,14 @@ u8 rtw_init_drv_sw(_adapter *padapter) { padapter->cmdpriv.padapter = padapter; if ((rtw_init_evt_priv(&padapter->evtpriv)) == _FAIL) { - RT_TRACE(_module_os_intfs_c_, _drv_err_, ("\n Can't init evt_priv\n")); ret8 = _FAIL; goto exit; } - rtw_rfctl_init(padapter); + if (is_primary_adapter(padapter)) + rtw_rfctl_init(padapter); if (rtw_init_mlme_priv(padapter) == _FAIL) { - RT_TRACE(_module_os_intfs_c_, _drv_err_, ("\n Can't init mlme_priv\n")); ret8 = _FAIL; goto exit; } @@ -1825,17 +2123,16 @@ u8 rtw_init_drv_sw(_adapter *padapter) { rtw_init_wifidirect_timers(padapter); init_wifidirect_info(padapter, P2P_ROLE_DISABLE); reset_global_wifidirect_info(padapter); -#ifdef CONFIG_IOCTL_CFG80211 + #ifdef CONFIG_IOCTL_CFG80211 rtw_init_cfg80211_wifidirect_info(padapter); -#endif + #endif #ifdef CONFIG_WFD if (rtw_init_wifi_display_info(padapter) == _FAIL) - RT_TRACE(_module_os_intfs_c_, _drv_err_, ("\n Can't init init_wifi_display_info\n")); + RTW_ERR("Can't init init_wifi_display_info\n"); #endif #endif /* CONFIG_P2P */ if (init_mlme_ext_priv(padapter) == _FAIL) { - RT_TRACE(_module_os_intfs_c_, _drv_err_, ("\n Can't init mlme_ext_priv\n")); ret8 = _FAIL; goto exit; } @@ -1865,8 +2162,6 @@ u8 rtw_init_drv_sw(_adapter *padapter) { /* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */ /* _rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv)); */ - /* _init_timer(&(padapter->securitypriv.tkip_timer), padapter->pifp, rtw_use_tkipkey_handler, padapter); */ - if (_rtw_init_sta_priv(&padapter->stapriv) == _FAIL) { RTW_INFO("Can't _rtw_init_sta_priv\n"); ret8 = _FAIL; @@ -1876,6 +2171,10 @@ u8 rtw_init_drv_sw(_adapter *padapter) { padapter->stapriv.padapter = padapter; padapter->setband = WIFI_FREQUENCY_BAND_AUTO; padapter->fix_rate = 0xFF; + padapter->power_offset = 0; + padapter->rsvd_page_offset = 0; + padapter->rsvd_page_num = 0; + padapter->data_fb = 0; padapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID; padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID; @@ -1921,59 +2220,52 @@ u8 rtw_init_drv_sw(_adapter *padapter) { _rtw_spinlock_init(&padapter->br_ext_lock); #endif /* CONFIG_BR_EXT */ +#ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 + rtw_bf_init(padapter); +#endif /* RTW_BEAMFORMING_VERSION_2 */ +#endif /* CONFIG_BEAMFORMING */ + exit: - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("-rtw_init_drv_sw\n")); - _func_exit_; return ret8; } #ifdef CONFIG_WOWLAN -void rtw_cancel_dynamic_chk_timer(_adapter *padapter) { - _cancel_timer_ex(&padapter->mlmepriv.dynamic_chk_timer); - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("rtw_cancel_all_timer:cancel dynamic_chk_timer!\n")); +void rtw_cancel_dynamic_chk_timer(_adapter *padapter) +{ + _cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer); } #endif -void rtw_cancel_all_timer(_adapter *padapter) { - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("+rtw_cancel_all_timer\n")); +void rtw_cancel_all_timer(_adapter *padapter) +{ _cancel_timer_ex(&padapter->mlmepriv.assoc_timer); - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("rtw_cancel_all_timer:cancel association timer complete!\n")); - -#if 0 - _cancel_timer_ex(&padapter->securitypriv.tkip_timer); - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("rtw_cancel_all_timer:cancel tkip_timer!\n")); -#endif _cancel_timer_ex(&padapter->mlmepriv.scan_to_timer); - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("rtw_cancel_all_timer:cancel scan_to_timer!\n")); #ifdef CONFIG_DFS_MASTER _cancel_timer_ex(&padapter->mlmepriv.dfs_master_timer); #endif - _cancel_timer_ex(&padapter->mlmepriv.dynamic_chk_timer); - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("rtw_cancel_all_timer:cancel dynamic_chk_timer!\n")); + _cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer); /* cancel sw led timer */ rtw_hal_sw_led_deinit(padapter); - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("rtw_cancel_all_timer:cancel DeInitSwLeds!\n")); _cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_state_check_timer)); -#ifdef TX_AMSDU +#ifdef CONFIG_TX_AMSDU _cancel_timer_ex(&padapter->xmitpriv.amsdu_bk_timer); _cancel_timer_ex(&padapter->xmitpriv.amsdu_be_timer); _cancel_timer_ex(&padapter->xmitpriv.amsdu_vo_timer); _cancel_timer_ex(&padapter->xmitpriv.amsdu_vi_timer); #endif - - #ifdef CONFIG_IOCTL_CFG80211 #ifdef CONFIG_P2P _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); @@ -1983,12 +2275,16 @@ void rtw_cancel_all_timer(_adapter *padapter) { #ifdef CONFIG_SET_SCAN_DENY_TIMER _cancel_timer_ex(&padapter->mlmepriv.set_scan_deny_timer); rtw_clear_scan_deny(padapter); - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("rtw_cancel_all_timer:cancel set_scan_deny_timer!\n")); #endif #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS _cancel_timer_ex(&padapter->recvpriv.signal_stat_timer); #endif + +#ifdef CONFIG_LPS_RPWM_TIMER + _cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_rpwm_timer)); +#endif /* CONFIG_LPS_RPWM_TIMER */ + /* cancel dm timer */ rtw_hal_dm_deinit(padapter); @@ -1997,8 +2293,8 @@ void rtw_cancel_all_timer(_adapter *padapter) { #endif } -u8 rtw_free_drv_sw(_adapter *padapter) { - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("==>rtw_free_drv_sw")); +u8 rtw_free_drv_sw(_adapter *padapter) +{ #ifdef CONFIG_WAPI_SUPPORT rtw_wapi_free(padapter); @@ -2007,20 +2303,20 @@ u8 rtw_free_drv_sw(_adapter *padapter) { /* we can call rtw_p2p_enable here, but: */ /* 1. rtw_p2p_enable may have IO operation */ /* 2. rtw_p2p_enable is bundled with wext interface */ -#ifdef CONFIG_P2P + #ifdef CONFIG_P2P { struct wifidirect_info *pwdinfo = &padapter->wdinfo; if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { _cancel_timer_ex(&pwdinfo->find_phase_timer); _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); _cancel_timer_ex(&pwdinfo->pre_tx_scan_timer); -#ifdef CONFIG_CONCURRENT_MODE + #ifdef CONFIG_CONCURRENT_MODE _cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer); -#endif /* CONFIG_CONCURRENT_MODE */ + #endif /* CONFIG_CONCURRENT_MODE */ rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); } } -#endif + #endif /* add for CONFIG_IEEE80211W, none 11w also can use */ _rtw_spinlock_free(&padapter->security_key_mutex); @@ -2044,6 +2340,9 @@ u8 rtw_free_drv_sw(_adapter *padapter) { rtw_free_mlme_priv(&padapter->mlmepriv); + if (is_primary_adapter(padapter)) + rtw_rfctl_deinit(padapter); + /* free_io_queue(padapter); */ _rtw_free_xmit_priv(&padapter->xmitpriv); @@ -2062,29 +2361,30 @@ u8 rtw_free_drv_sw(_adapter *padapter) { rtw_hal_free_data(padapter); - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("<==rtw_free_drv_sw\n")); /* free the old_pnetdev */ if (padapter->rereg_nd_name_priv.old_pnetdev) { free_netdev(padapter->rereg_nd_name_priv.old_pnetdev); padapter->rereg_nd_name_priv.old_pnetdev = NULL; } - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("-rtw_free_drv_sw\n")); return _SUCCESS; } -void rtw_intf_start(_adapter *adapter) { +void rtw_intf_start(_adapter *adapter) +{ if (adapter->intf_start) adapter->intf_start(adapter); } -void rtw_intf_stop(_adapter *adapter) { +void rtw_intf_stop(_adapter *adapter) +{ if (adapter->intf_stop) adapter->intf_stop(adapter); } #ifdef CONFIG_CONCURRENT_MODE -int _netdev_vir_if_open(struct net_device *pnetdev) { +int _netdev_vir_if_open(struct net_device *pnetdev) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); _adapter *primary_padapter = GET_PRIMARY_ADAPTER(padapter); @@ -2123,34 +2423,34 @@ int _netdev_vir_if_open(struct net_device *pnetdev) { _netdev_open(primary_padapter->pnetdev); if (padapter->bup == _FALSE && primary_padapter->bup == _TRUE && - rtw_is_hw_init_completed(primary_padapter)) { - padapter->bFWReady = primary_padapter->bFWReady; + rtw_is_hw_init_completed(primary_padapter)) { #if 0 /*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/ rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */ #endif -#ifdef CONFIG_NAPI - napi_enable(&padapter->napi); -#endif + } + if (padapter->bup == _FALSE) { if (rtw_start_drv_threads(padapter) == _FAIL) goto _netdev_virtual_iface_open_error; + } + +#ifdef CONFIG_RTW_NAPI + if (padapter->napi_state == NAPI_DISABLE) { + napi_enable(&padapter->napi); + padapter->napi_state = NAPI_ENABLE; + } +#endif #ifdef CONFIG_IOCTL_CFG80211 - rtw_cfg80211_init_wiphy(padapter); - rtw_cfg80211_init_wdev_data(padapter); + rtw_cfg80211_init_wiphy(padapter); + rtw_cfg80211_init_wdev_data(padapter); #endif - padapter->bup = _TRUE; - - } + padapter->bup = _TRUE; padapter->net_closed = _FALSE; - /*execute dynamic_chk_timer only on primary interface - all of virtual interface shares the timer with primary interface.*/ - /*_set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);*/ - rtw_netif_wake_queue(pnetdev); RTW_INFO(FUNC_NDEV_FMT" (bup=%d) exit\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); @@ -2161,9 +2461,13 @@ int _netdev_vir_if_open(struct net_device *pnetdev) { padapter->bup = _FALSE; -#ifdef CONFIG_NAPI - napi_disable(&padapter->napi); +#ifdef CONFIG_RTW_NAPI + if(padapter->napi_state == NAPI_ENABLE) { + napi_disable(&padapter->napi); + padapter->napi_state = NAPI_DISABLE; + } #endif + netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); @@ -2171,7 +2475,8 @@ int _netdev_vir_if_open(struct net_device *pnetdev) { } -int netdev_vir_if_open(struct net_device *pnetdev) { +int netdev_vir_if_open(struct net_device *pnetdev) +{ int ret; _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); @@ -2187,7 +2492,8 @@ int netdev_vir_if_open(struct net_device *pnetdev) { return ret; } -static int netdev_vir_if_close(struct net_device *pnetdev) { +static int netdev_vir_if_close(struct net_device *pnetdev) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -2228,7 +2534,8 @@ static const struct net_device_ops rtw_netdev_vir_if_ops = { }; #endif -void rtw_hook_vir_if_ops(struct net_device *ndev) { +static void rtw_hook_vir_if_ops(struct net_device *ndev) +{ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) ndev->netdev_ops = &rtw_netdev_vir_if_ops; #else @@ -2240,7 +2547,8 @@ void rtw_hook_vir_if_ops(struct net_device *ndev) { #endif } _adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, - void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops)) { + void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops)) +{ int res = _FAIL; _adapter *padapter = NULL; struct dvobj_priv *pdvobjpriv; @@ -2269,11 +2577,7 @@ _adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, #ifdef CONFIG_MI_WITH_MBSSID_CAM padapter->hw_port = HW_PORT0; #else -#ifndef CONFIG_HWPORT_SWAP padapter->hw_port = HW_PORT1; -#else /* CONFIG_HWPORT_SWAP */ - padapter->hw_port = HW_PORT0; -#endif /* !CONFIG_HWPORT_SWAP */ #endif @@ -2287,7 +2591,6 @@ _adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, /* step init_io_priv */ if ((rtw_init_io_priv(padapter, set_intf_ops)) == _FAIL) { - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("\n Can't init io_reqs\n")); goto free_adapter; } @@ -2330,7 +2633,8 @@ _adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, return padapter; } -void rtw_drv_stop_vir_if(_adapter *padapter) { +void rtw_drv_stop_vir_if(_adapter *padapter) +{ struct net_device *pnetdev = NULL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -2340,22 +2644,22 @@ void rtw_drv_stop_vir_if(_adapter *padapter) { pnetdev = padapter->pnetdev; if (check_fwstate(pmlmepriv, _FW_LINKED)) - rtw_disassoc_cmd(padapter, 0, _FALSE); + rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); #ifdef CONFIG_AP_MODE if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { free_mlme_ap_info(padapter); -#ifdef CONFIG_HOSTAPD_MLME + #ifdef CONFIG_HOSTAPD_MLME hostapd_mode_unload(padapter); -#endif + #endif } #endif if (padapter->bup == _TRUE) { -#ifdef CONFIG_XMIT_ACK + #ifdef CONFIG_XMIT_ACK if (padapter->xmitpriv.ack_tx) rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); -#endif + #endif rtw_intf_stop(padapter); @@ -2367,7 +2671,8 @@ void rtw_drv_stop_vir_if(_adapter *padapter) { rtw_cancel_all_timer(padapter); } -void rtw_drv_free_vir_if(_adapter *padapter) { +void rtw_drv_free_vir_if(_adapter *padapter) +{ if (padapter == NULL) return; @@ -2381,26 +2686,30 @@ void rtw_drv_free_vir_if(_adapter *padapter) { } -void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj) { +void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj) +{ int i; for (i = VIF_START_ID; i < dvobj->iface_nums; i++) rtw_drv_stop_vir_if(dvobj->padapters[i]); } -void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj) { +void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj) +{ int i; for (i = VIF_START_ID; i < dvobj->iface_nums; i++) rtw_drv_free_vir_if(dvobj->padapters[i]); } -void rtw_drv_del_vir_if(_adapter *padapter) { +void rtw_drv_del_vir_if(_adapter *padapter) +{ rtw_drv_stop_vir_if(padapter); rtw_drv_free_vir_if(padapter); } -void rtw_drv_del_vir_ifaces(_adapter *primary_padapter) { +void rtw_drv_del_vir_ifaces(_adapter *primary_padapter) +{ int i; struct dvobj_priv *dvobj = primary_padapter->dvobj; @@ -2411,53 +2720,131 @@ void rtw_drv_del_vir_ifaces(_adapter *primary_padapter) { #endif /*end of CONFIG_CONCURRENT_MODE*/ -#ifdef CONFIG_NAPI -static int rtw_os_napi_poll(struct napi_struct *napi, int budget) { - _adapter *adapter; - int done; - static int cnt_done[10] = {0}; - struct dvobj_priv *pdvobjpriv; - struct registry_priv *reg; - _irqL irqL; - - adapter = container_of(napi, _adapter, napi); - pdvobjpriv = adapter_to_dvobj(adapter); - reg = dvobj_to_regsty(pdvobjpriv); - - done = adapter->HalFunc.napi_poll(adapter, budget); - if (done < budget) { - napi_complete(napi); - _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); - adapter->HalFunc.napi_irq_enable(adapter); - _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); - if (reg->napi_debug) { - if (printk_ratelimit()) - RTW_INFO("NAPI poll complete\n"); - if (done < 7) - cnt_done[done]++; - else - cnt_done[7]++; - } +/* IPv4, IPv6 IP addr notifier */ +static int rtw_inetaddr_notifier_call(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct in_ifaddr *ifa = (struct in_ifaddr *)data; + struct net_device *ndev; + struct mlme_ext_priv *pmlmeext = NULL; + struct mlme_ext_info *pmlmeinfo = NULL; + _adapter *adapter = NULL; + + if (!ifa || !ifa->ifa_dev || !ifa->ifa_dev->dev) + return NOTIFY_DONE; + + ndev = ifa->ifa_dev->dev; + + if (!is_rtw_ndev(ndev)) + return NOTIFY_DONE; + + adapter = (_adapter *)rtw_netdev_priv(ifa->ifa_dev->dev); + + if (adapter == NULL) + return NOTIFY_DONE; + + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + switch (action) { + case NETDEV_UP: + _rtw_memcpy(pmlmeinfo->ip_addr, &ifa->ifa_address, + RTW_IP_ADDR_LEN); + RTW_DBG("%s[%s]: up IP: %pI4\n", __func__, + ifa->ifa_label, pmlmeinfo->ip_addr); + break; + case NETDEV_DOWN: + _rtw_memset(pmlmeinfo->ip_addr, 0, RTW_IP_ADDR_LEN); + RTW_DBG("%s[%s]: down IP: %pI4\n", __func__, + ifa->ifa_label, pmlmeinfo->ip_addr); + break; + default: + RTW_DBG("%s: default action\n", __func__); + break; } + return NOTIFY_DONE; +} + +static int rtw_inet6addr_notifier_call(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct inet6_ifaddr *inet6_ifa = data; + struct net_device *ndev; + struct ipv6_addr *_ipv6_addr = NULL; + struct pwrctrl_priv *pwrctl = NULL; + struct mlme_ext_priv *pmlmeext = NULL; + struct mlme_ext_info *pmlmeinfo = NULL; + _adapter *adapter = NULL; + + if (!inet6_ifa || !inet6_ifa->idev || !inet6_ifa->idev->dev) + return NOTIFY_DONE; + + ndev = inet6_ifa->idev->dev; + + if (!is_rtw_ndev(ndev)) + return NOTIFY_DONE; + + adapter = (_adapter *)rtw_netdev_priv(inet6_ifa->idev->dev); + + if (adapter == NULL) + return NOTIFY_DONE; + + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + pwrctl = adapter_to_pwrctl(adapter); - if (reg->napi_debug && printk_ratelimit()) { - RTW_INFO("NAPI poll(%d) done %d\n", budget, done); - RTW_INFO("0:%d, 1:%d, 2:%d, 3:%d, 4:%d, 5:%d, 6:%d, O: %d\n", - cnt_done[0], - cnt_done[1], - cnt_done[2], - cnt_done[3], - cnt_done[4], - cnt_done[5], - cnt_done[6], - cnt_done[7]); + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + switch (action) { + case NETDEV_UP: +#ifdef CONFIG_WOWLAN + pwrctl->wowlan_ns_offload_en = _TRUE; +#endif + _rtw_memcpy(pmlmeinfo->ip6_addr, &inet6_ifa->addr, + RTW_IPv6_ADDR_LEN); + RTW_DBG("%s: up IPv6 addrs: %pI6\n", __func__, + pmlmeinfo->ip6_addr); + break; + case NETDEV_DOWN: +#ifdef CONFIG_WOWLAN + pwrctl->wowlan_ns_offload_en = _FALSE; +#endif + _rtw_memset(pmlmeinfo->ip6_addr, 0, RTW_IPv6_ADDR_LEN); + RTW_DBG("%s: down IPv6 addrs: %pI6\n", __func__, + pmlmeinfo->ip6_addr); + break; + default: + RTW_DBG("%s: default action\n", __func__); + break; } + return NOTIFY_DONE; +} + +static struct notifier_block rtw_inetaddr_notifier = { + .notifier_call = rtw_inetaddr_notifier_call +}; + +static struct notifier_block rtw_inet6addr_notifier = { + .notifier_call = rtw_inet6addr_notifier_call +}; - return done; +void rtw_inetaddr_notifier_register(void) +{ + RTW_INFO("%s\n", __func__); + register_inetaddr_notifier(&rtw_inetaddr_notifier); + register_inet6addr_notifier(&rtw_inet6addr_notifier); +} + +void rtw_inetaddr_notifier_unregister(void) +{ + RTW_INFO("%s\n", __func__); + unregister_inetaddr_notifier(&rtw_inetaddr_notifier); + unregister_inet6addr_notifier(&rtw_inet6addr_notifier); } -#endif -int rtw_os_ndevs_register(struct dvobj_priv *dvobj) { +int rtw_os_ndevs_register(struct dvobj_priv *dvobj) +{ int i, status = _SUCCESS; struct registry_priv *regsty = dvobj_to_regsty(dvobj); _adapter *adapter; @@ -2482,6 +2869,11 @@ int rtw_os_ndevs_register(struct dvobj_priv *dvobj) { if (adapter) { char *name; + #ifdef CONFIG_RTW_DYNAMIC_NDEV + if (!is_primary_adapter(adapter)) + continue; + #endif + if (adapter->iface_id == IFACE_ID0) name = regsty->ifname; else if (adapter->iface_id == IFACE_ID1) @@ -2489,16 +2881,6 @@ int rtw_os_ndevs_register(struct dvobj_priv *dvobj) { else name = "wlan%d"; -#ifdef CONFIG_CONCURRENT_MODE - if (!is_primary_adapter(adapter)) - rtw_hook_vir_if_ops(adapter->pnetdev); -#endif /* CONFIG_CONCURRENT_MODE */ - -#ifdef CONFIG_NAPI - netif_napi_add(adapter->pnetdev, &adapter->napi, - rtw_os_napi_poll, regsty->napi_weight); -#endif - status = rtw_os_ndev_register(adapter, name); if (status != _SUCCESS) { @@ -2511,12 +2893,8 @@ int rtw_os_ndevs_register(struct dvobj_priv *dvobj) { if (status != _SUCCESS) { for (; i >= 0; i--) { adapter = dvobj->padapters[i]; - if (adapter) { + if (adapter) rtw_os_ndev_unregister(adapter); -#ifdef CONFIG_NAPI - netif_napi_del(&adapter->napi); -#endif - } } } @@ -2528,7 +2906,8 @@ int rtw_os_ndevs_register(struct dvobj_priv *dvobj) { return status; } -void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj) { +void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj) +{ int i; _adapter *adapter = NULL; @@ -2539,9 +2918,6 @@ void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj) { continue; rtw_os_ndev_unregister(adapter); -#ifdef CONFIG_NAPI - netif_napi_del(&adapter->napi); -#endif } #if defined(CONFIG_IOCTL_CFG80211) @@ -2556,7 +2932,8 @@ void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj) { * Returns: * _SUCCESS or _FAIL */ -int rtw_os_ndevs_init(struct dvobj_priv *dvobj) { +int rtw_os_ndevs_init(struct dvobj_priv *dvobj) +{ int ret = _FAIL; if (rtw_os_ndevs_alloc(dvobj) != _SUCCESS) @@ -2578,13 +2955,15 @@ int rtw_os_ndevs_init(struct dvobj_priv *dvobj) { * rtw_os_ndevs_deinit - Unregister and free OS layer net devices and relating structures for @dvobj * @dvobj: the dvobj on which this function applies */ -void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj) { +void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj) +{ rtw_os_ndevs_unregister(dvobj); rtw_os_ndevs_free(dvobj); } #ifdef CONFIG_BR_EXT -void netdev_br_init(struct net_device *netdev) { +void netdev_br_init(struct net_device *netdev) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) @@ -2631,7 +3010,8 @@ void netdev_br_init(struct net_device *netdev) { } #endif /* CONFIG_BR_EXT */ -int _netdev_open(struct net_device *pnetdev) { +int _netdev_open(struct net_device *pnetdev) +{ uint status; _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); @@ -2639,7 +3019,6 @@ int _netdev_open(struct net_device *pnetdev) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); #endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("+871x_drv - dev_open\n")); RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); @@ -2667,13 +3046,8 @@ int _netdev_open(struct net_device *pnetdev) { rtw_clr_surprise_removed(padapter); rtw_clr_drv_stopped(padapter); -#ifdef CONFIG_NAPI - napi_enable(&padapter->napi); -#endif - status = rtw_hal_init(padapter); if (status == _FAIL) { - RT_TRACE(_module_os_intfs_c_, _drv_err_, ("rtl871x_hal_init(): Can't init h/w!\n")); goto netdev_open_error; } #if 0/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/ @@ -2688,6 +3062,13 @@ int _netdev_open(struct net_device *pnetdev) { goto netdev_open_error; } +#ifdef CONFIG_RTW_NAPI + if(padapter->napi_state == NAPI_DISABLE) { + napi_enable(&padapter->napi); + padapter->napi_state = NAPI_ENABLE; + } +#endif + #ifdef CONFIG_DRVEXT_MODULE init_drvext(padapter); #endif @@ -2711,7 +3092,7 @@ int _netdev_open(struct net_device *pnetdev) { } padapter->net_closed = _FALSE; - _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); + _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); #ifndef CONFIG_IPS_CHECK_IN_WD rtw_set_pwr_state_check_timer(pwrctrlpriv); @@ -2740,12 +3121,13 @@ int _netdev_open(struct net_device *pnetdev) { { _adapter *sec_adapter = adapter_to_dvobj(padapter)->padapters[IFACE_ID1]; + #ifndef CONFIG_RTW_DYNAMIC_NDEV if (sec_adapter && (sec_adapter->bup == _FALSE)) _netdev_vir_if_open(sec_adapter->pnetdev); + #endif } #endif - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("-871x_drv - dev_open\n")); RTW_INFO("-871x_drv - drv_open, bup=%d\n", padapter->bup); return 0; @@ -2754,20 +3136,24 @@ int _netdev_open(struct net_device *pnetdev) { padapter->bup = _FALSE; -#ifdef CONFIG_NAPI - napi_disable(&padapter->napi); +#ifdef CONFIG_RTW_NAPI + if(padapter->napi_state == NAPI_ENABLE) { + napi_disable(&padapter->napi); + padapter->napi_state = NAPI_DISABLE; + } #endif + netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); - RT_TRACE(_module_os_intfs_c_, _drv_err_, ("-871x_drv - dev_open, fail!\n")); RTW_INFO("-871x_drv - drv_open fail, bup=%d\n", padapter->bup); return -1; } -int netdev_open(struct net_device *pnetdev) { +int netdev_open(struct net_device *pnetdev) +{ int ret = _FALSE; _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); @@ -2796,7 +3182,8 @@ int netdev_open(struct net_device *pnetdev) { } #ifdef CONFIG_IPS -int ips_netdrv_open(_adapter *padapter) { +int ips_netdrv_open(_adapter *padapter) +{ int status = _SUCCESS; /* struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); */ @@ -2810,7 +3197,6 @@ int ips_netdrv_open(_adapter *padapter) { status = rtw_hal_init(padapter); if (status == _FAIL) { - RT_TRACE(_module_os_intfs_c_, _drv_err_, ("ips_netdrv_open(): Can't init h/w!\n")); goto netdev_open_error; } #if 0 @@ -2821,7 +3207,7 @@ int ips_netdrv_open(_adapter *padapter) { #ifndef CONFIG_IPS_CHECK_IN_WD rtw_set_pwr_state_check_timer(adapter_to_pwrctl(padapter)); #endif - _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); + _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); return _SUCCESS; @@ -2832,8 +3218,8 @@ int ips_netdrv_open(_adapter *padapter) { return _FAIL; } - -int rtw_ips_pwr_up(_adapter *padapter) { +int rtw_ips_pwr_up(_adapter *padapter) +{ int result; PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); #ifdef DBG_CONFIG_ERROR_DETECT @@ -2858,7 +3244,8 @@ int rtw_ips_pwr_up(_adapter *padapter) { } -void rtw_ips_pwr_down(_adapter *padapter) { +void rtw_ips_pwr_down(_adapter *padapter) +{ u32 start_time = rtw_get_current_time(); RTW_INFO("===> rtw_ips_pwr_down...................\n"); @@ -2868,7 +3255,8 @@ void rtw_ips_pwr_down(_adapter *padapter) { RTW_INFO("<=== rtw_ips_pwr_down..................... in %dms\n", rtw_get_passing_time_ms(start_time)); } #endif -void rtw_ips_dev_unload(_adapter *padapter) { +void rtw_ips_dev_unload(_adapter *padapter) +{ struct net_device *pnetdev = (struct net_device *)padapter->pnetdev; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); @@ -2893,8 +3281,8 @@ void rtw_ips_dev_unload(_adapter *padapter) { } - -int pm_netdev_open(struct net_device *pnetdev, u8 bnormal) { +int pm_netdev_open(struct net_device *pnetdev, u8 bnormal) +{ int status = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); @@ -2915,7 +3303,8 @@ int pm_netdev_open(struct net_device *pnetdev, u8 bnormal) { return status; } -static int netdev_close(struct net_device *pnetdev) { +static int netdev_close(struct net_device *pnetdev) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -2923,7 +3312,6 @@ static int netdev_close(struct net_device *pnetdev) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); #endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("+871x_drv - drv_close\n")); RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); #ifndef CONFIG_PLATFORM_INTEL_BYT if (pwrctl->bInternalAutoSuspend == _TRUE) { @@ -2953,7 +3341,7 @@ static int netdev_close(struct net_device *pnetdev) { #ifndef CONFIG_ANDROID /* s2. */ LeaveAllPowerSaveMode(padapter); - rtw_disassoc_cmd(padapter, 500, _FALSE); + rtw_disassoc_cmd(padapter, 500, RTW_CMDF_DIRECTLY); /* s2-2. indicate disconnect to os */ rtw_indicate_disconnect(padapter, 0, _FALSE); /* s2-3. */ @@ -3015,14 +3403,14 @@ static int netdev_close(struct net_device *pnetdev) { #endif /* !CONFIG_PLATFORM_INTEL_BYT */ - RT_TRACE(_module_os_intfs_c_, _drv_info_, ("-871x_drv - drv_close\n")); RTW_INFO("-871x_drv - drv_close, bup=%d\n", padapter->bup); return 0; } -int pm_netdev_close(struct net_device *pnetdev, u8 bnormal) { +int pm_netdev_close(struct net_device *pnetdev, u8 bnormal) +{ int status = 0; status = netdev_close(pnetdev); @@ -3030,7 +3418,8 @@ int pm_netdev_close(struct net_device *pnetdev, u8 bnormal) { return status; } -void rtw_ndev_destructor(struct net_device *ndev) { +void rtw_ndev_destructor(struct net_device *ndev) +{ RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); #ifdef CONFIG_IOCTL_CFG80211 @@ -3048,7 +3437,8 @@ struct route_info { unsigned int dev_index; }; -static void parse_routes(struct nlmsghdr *nl_hdr, struct route_info *rt_info) { +static void parse_routes(struct nlmsghdr *nl_hdr, struct route_info *rt_info) +{ struct rtmsg *rt_msg; struct rtattr *rt_attr; int rt_len; @@ -3078,7 +3468,8 @@ static void parse_routes(struct nlmsghdr *nl_hdr, struct route_info *rt_info) { } } -static int route_dump(u32 *gw_addr , int *gw_index) { +static int route_dump(u32 *gw_addr , int *gw_index) +{ int err = 0; struct socket *sock; struct { @@ -3256,7 +3647,8 @@ static int route_dump(u32 *gw_addr , int *gw_index) { } static int arp_query(unsigned char *haddr, u32 paddr, - struct net_device *dev) { + struct net_device *dev) +{ struct neighbour *neighbor_entry; int ret = 0; @@ -3273,7 +3665,8 @@ static int arp_query(unsigned char *haddr, u32 paddr, return ret; } -static int get_defaultgw(u32 *ip_addr , char mac[]) { +static int get_defaultgw(u32 *ip_addr , char mac[]) +{ int gw_index = 0; /* oif device index */ struct net_device *gw_dev = NULL; /* oif device */ @@ -3302,7 +3695,8 @@ static int get_defaultgw(u32 *ip_addr , char mac[]) { return 0; } -int rtw_gw_addr_query(_adapter *padapter) { +int rtw_gw_addr_query(_adapter *padapter) +{ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); u32 gw_addr = 0; /* default gw address */ @@ -3326,7 +3720,8 @@ int rtw_gw_addr_query(_adapter *padapter) { } #endif -void rtw_dev_unload(PADAPTER padapter) { +void rtw_dev_unload(PADAPTER padapter) +{ struct net_device *pnetdev = (struct net_device *)padapter->pnetdev; struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); struct dvobj_priv *pobjpriv = padapter->dvobj; @@ -3334,10 +3729,17 @@ void rtw_dev_unload(PADAPTER padapter) { struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 cnt = 0; - RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("+%s\n", __FUNCTION__)); if (padapter->bup == _TRUE) { - RTW_INFO("===> %s\n", __FUNCTION__); + RTW_INFO("==> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + +#ifdef CONFIG_WOWLAN +#ifdef CONFIG_GPIO_WAKEUP + /*default wake up pin change to BT*/ + RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__); + rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _FALSE); +#endif /* CONFIG_GPIO_WAKEUP */ +#endif /* CONFIG_WOWLAN */ rtw_set_drv_stopped(padapter); #ifdef CONFIG_XMIT_ACK @@ -3346,28 +3748,16 @@ void rtw_dev_unload(PADAPTER padapter) { #endif rtw_intf_stop(padapter); -#ifdef CONFIG_NAPI - napi_disable(&padapter->napi); -#endif - RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("@ rtw_dev_unload: stop intf complete!\n")); - if (!pwrctl->bInternalAutoSuspend) + if (!pwrctl->bInternalAutoSuspend) { rtw_stop_drv_threads(padapter); - while (ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE) { - if (cnt > 5) { - RTW_INFO("stop cmdthd timeout\n"); - break; - } else { - cnt++; - RTW_INFO("cmdthd is running(%d)\n", cnt); - rtw_msleep_os(10); + if (ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE) { + RTW_ERR("cmd_thread not stop !!\n"); + rtw_warn_on(1); } } - - RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("@ %s: stop thread complete!\n", __FUNCTION__)); - /* check the status of IPS */ if (rtw_hal_check_ips_status(padapter) == _TRUE || pwrctl->rf_pwrstate == rf_off) { /* check HW status and SW state */ RTW_PRINT("%s: driver in IPS-FWLPS\n", __func__); @@ -3381,7 +3771,7 @@ void rtw_dev_unload(PADAPTER padapter) { #endif #ifdef CONFIG_WOWLAN if (pwrctl->bSupportRemoteWakeup == _TRUE && - pwrctl->wowlan_mode == _TRUE) + pwrctl->wowlan_mode == _TRUE) RTW_PRINT("%s bSupportRemoteWakeup==_TRUE do not run rtw_hal_deinit()\n", __FUNCTION__); else #endif @@ -3391,20 +3781,18 @@ void rtw_dev_unload(PADAPTER padapter) { } rtw_set_surprise_removed(padapter); } - RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("@ %s: deinit hal complelt!\n", __FUNCTION__)); padapter->bup = _FALSE; - RTW_INFO("<=== %s\n", __FUNCTION__); + RTW_INFO("<== "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); } else { - RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("%s: bup==_FALSE\n", __FUNCTION__)); RTW_INFO("%s: bup==_FALSE\n", __FUNCTION__); } rtw_cancel_all_timer(padapter); - RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("-%s\n", __FUNCTION__)); } -int rtw_suspend_free_assoc_resource(_adapter *padapter) { +int rtw_suspend_free_assoc_resource(_adapter *padapter) +{ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct net_device *pnetdev = padapter->pnetdev; #ifdef CONFIG_P2P @@ -3415,22 +3803,26 @@ int rtw_suspend_free_assoc_resource(_adapter *padapter) { if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) { if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) - && check_fwstate(pmlmepriv, _FW_LINKED) -#ifdef CONFIG_P2P - && rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) -#endif /* CONFIG_P2P */ - ) { + && check_fwstate(pmlmepriv, _FW_LINKED) + #ifdef CONFIG_P2P + && (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) + #if defined(CONFIG_IOCTL_CFG80211) && RTW_P2P_GROUP_INTERFACE + || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) + #endif + ) + #endif /* CONFIG_P2P */ + ) { RTW_INFO("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n", __FUNCTION__, - pmlmepriv->cur_network.network.Ssid.Ssid, - MAC_ARG(pmlmepriv->cur_network.network.MacAddress), - pmlmepriv->cur_network.network.Ssid.SsidLength, - pmlmepriv->assoc_ssid.SsidLength); + pmlmepriv->cur_network.network.Ssid.Ssid, + MAC_ARG(pmlmepriv->cur_network.network.MacAddress), + pmlmepriv->cur_network.network.Ssid.SsidLength, + pmlmepriv->assoc_ssid.SsidLength); rtw_set_to_roam(padapter, 1); } } if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED)) { - rtw_disassoc_cmd(padapter, 0, _FALSE); + rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); /* s2-2. indicate disconnect to os */ rtw_indicate_disconnect(padapter, 0, _FALSE); } @@ -3464,7 +3856,8 @@ int rtw_suspend_free_assoc_resource(_adapter *padapter) { } #ifdef CONFIG_WOWLAN -int rtw_suspend_wow(_adapter *padapter) { +int rtw_suspend_wow(_adapter *padapter) +{ u8 ch, bw, offset; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct net_device *pnetdev = padapter->pnetdev; @@ -3488,13 +3881,21 @@ int rtw_suspend_wow(_adapter *padapter) { #endif if (pwrpriv->wowlan_mode == _TRUE) { - if (pnetdev) rtw_netif_stop_queue(pnetdev); rtw_mi_buddy_netif_stop_queue(padapter, _TRUE); /* 0. Power off LED */ rtw_led_control(padapter, LED_CTL_POWER_OFF); + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + /* 2.only for SDIO disable interrupt */ + rtw_intf_stop(padapter); + + /* 2.1 clean interrupt */ + rtw_hal_clear_interrupt(padapter); +#endif /* CONFIG_SDIO_HCI */ + /* 1. stop thread */ rtw_set_drv_stopped(padapter); /*for stop thread*/ for (i = 0; i < dvobj->iface_nums; i++) { @@ -3508,18 +3909,12 @@ int rtw_suspend_wow(_adapter *padapter) { /* rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN"); */ /* #endif */ -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - /* 2. disable interrupt */ - rtw_mi_intf_stop(padapter); - - /* 2.1 clean interupt */ - rtw_hal_clear_interrupt(padapter); -#endif /* CONFIG_SDIO_HCI */ - /* 2.2 free irq */ /* sdio_free_irq(adapter_to_dvobj(padapter)); */ +#if !(CONFIG_RTW_SDIO_KEEP_IRQ) if (padapter->intf_free_irq) padapter->intf_free_irq(adapter_to_dvobj(padapter)); +#endif #ifdef CONFIG_RUNTIME_PORT_SWITCH if (rtw_port_switch_chk(padapter)) { @@ -3532,12 +3927,12 @@ int rtw_suspend_wow(_adapter *padapter) { rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam); if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) { if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) - && check_fwstate(pmlmepriv, _FW_LINKED)) { + && check_fwstate(pmlmepriv, _FW_LINKED)) { RTW_INFO("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n", __FUNCTION__, - pmlmepriv->cur_network.network.Ssid.Ssid, - MAC_ARG(pmlmepriv->cur_network.network.MacAddress), - pmlmepriv->cur_network.network.Ssid.SsidLength, - pmlmepriv->assoc_ssid.SsidLength); + pmlmepriv->cur_network.network.Ssid.Ssid, + MAC_ARG(pmlmepriv->cur_network.network.MacAddress), + pmlmepriv->cur_network.network.Ssid.SsidLength, + pmlmepriv->assoc_ssid.SsidLength); rtw_set_to_roam(padapter, 0); } @@ -3557,32 +3952,40 @@ int rtw_suspend_wow(_adapter *padapter) { bw = rtw_mi_get_union_bw(padapter); offset = rtw_mi_get_union_offset(padapter); RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", - FUNC_ADPT_ARG(padapter), ch, bw, offset); + FUNC_ADPT_ARG(padapter), ch, bw, offset); set_channel_bwmode(padapter, ch, offset, bw); } #else if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) { RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", - FUNC_ADPT_ARG(padapter), ch, bw, offset); + FUNC_ADPT_ARG(padapter), ch, bw, offset); set_channel_bwmode(padapter, ch, offset, bw); rtw_mi_update_union_chan_inf(padapter, ch, offset, bw); } #endif +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT); +#endif + #ifdef CONFIG_CONCURRENT_MODE rtw_mi_buddy_suspend_free_assoc_resource(padapter); #endif if (pwrpriv->wowlan_pno_enable) { RTW_PRINT("%s: pno: %d\n", __func__, - pwrpriv->wowlan_pno_enable); + pwrpriv->wowlan_pno_enable); #ifdef CONFIG_FWLPS_IN_IPS rtw_set_fw_in_ips_mode(padapter, _TRUE); #endif } #ifdef CONFIG_LPS - else - rtw_set_ps_mode(padapter, PS_MODE_MAX, 0, 0, "WOWLAN"); + else { + if (!(pwrpriv->wowlan_dis_lps)) { + rtw_wow_lps_level_decide(padapter, _TRUE); + rtw_set_ps_mode(padapter, PS_MODE_MAX, 0, 0, "WOWLAN"); + } + } #endif /* #ifdef CONFIG_LPS */ } else @@ -3593,7 +3996,8 @@ int rtw_suspend_wow(_adapter *padapter) { #endif /* #ifdef CONFIG_WOWLAN */ #ifdef CONFIG_AP_WOWLAN -int rtw_suspend_ap_wow(_adapter *padapter) { +int rtw_suspend_ap_wow(_adapter *padapter) +{ u8 ch, bw, offset; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct dvobj_priv *psdpriv = padapter->dvobj; @@ -3616,6 +4020,14 @@ int rtw_suspend_ap_wow(_adapter *padapter) { /* 0. Power off LED */ rtw_led_control(padapter, LED_CTL_POWER_OFF); +#ifdef CONFIG_SDIO_HCI + /* 2.only for SDIO disable interrupt*/ + rtw_intf_stop(padapter); + + /* 2.1 clean interrupt */ + rtw_hal_clear_interrupt(padapter); +#endif /* CONFIG_SDIO_HCI */ + /* 1. stop thread */ rtw_set_drv_stopped(padapter); /*for stop thread*/ for (i = 0; i < dvobj->iface_nums; i++) { @@ -3625,14 +4037,6 @@ int rtw_suspend_ap_wow(_adapter *padapter) { } rtw_clr_drv_stopped(padapter); /*for 32k command*/ -#ifdef CONFIG_SDIO_HCI - /* 2. disable interrupt*/ - rtw_mi_intf_stop(padapter); - - /* 2.1 clean interupt */ - rtw_hal_clear_interrupt(padapter); -#endif /* CONFIG_SDIO_HCI */ - /* 2.2 free irq */ if (padapter->intf_free_irq) padapter->intf_free_irq(adapter_to_dvobj(padapter)); @@ -3664,6 +4068,10 @@ int rtw_suspend_ap_wow(_adapter *padapter) { } #endif +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT); +#endif + /*FOR ONE AP - TODO :Multi-AP*/ { int i; @@ -3681,7 +4089,10 @@ int rtw_suspend_ap_wow(_adapter *padapter) { } #ifdef CONFIG_LPS - rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, 0, "AP-WOWLAN"); + if (!(pwrpriv->wowlan_dis_lps)) { + rtw_wow_lps_level_decide(padapter, _TRUE); + rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, 0, "AP-WOWLAN"); + } #endif RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); @@ -3690,13 +4101,18 @@ int rtw_suspend_ap_wow(_adapter *padapter) { #endif /* #ifdef CONFIG_AP_WOWLAN */ -int rtw_suspend_normal(_adapter *padapter) { +int rtw_suspend_normal(_adapter *padapter) +{ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); int ret = _SUCCESS; RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND); +#endif + rtw_mi_netif_stop_queue(padapter, _TRUE); rtw_mi_suspend_free_assoc_resource(padapter); @@ -3704,12 +4120,14 @@ int rtw_suspend_normal(_adapter *padapter) { rtw_led_control(padapter, LED_CTL_POWER_OFF); if ((rtw_hal_check_ips_status(padapter) == _TRUE) - || (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)) + || (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)) RTW_PRINT("%s: ### ERROR #### driver in IPS ####ERROR###!!!\n", __FUNCTION__); #ifdef CONFIG_CONCURRENT_MODE - rtw_mi_buddy_dev_unload(padapter); + rtw_set_drv_stopped(padapter); /*for stop thread*/ + rtw_stop_cmd_thread(padapter); + rtw_drv_stop_vir_ifaces(adapter_to_dvobj(padapter)); #endif rtw_dev_unload(padapter); @@ -3717,11 +4135,17 @@ int rtw_suspend_normal(_adapter *padapter) { if (padapter->intf_deinit) padapter->intf_deinit(adapter_to_dvobj(padapter)); +#if !(CONFIG_RTW_SDIO_KEEP_IRQ) + if(padapter->intf_free_irq) + padapter->intf_free_irq(adapter_to_dvobj(padapter)); +#endif + RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); return ret; } -int rtw_suspend_common(_adapter *padapter) { +int rtw_suspend_common(_adapter *padapter) +{ struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(psdpriv); @@ -3751,9 +4175,9 @@ int rtw_suspend_common(_adapter *padapter) { if ((!padapter->bup) || RTW_CANNOT_RUN(padapter)) { RTW_INFO("%s bup=%d bDriverStopped=%s bSurpriseRemoved = %s\n", __func__ - , padapter->bup - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); + , padapter->bup + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False"); pdbgpriv->dbg_suspend_error_cnt++; goto exit; } @@ -3761,18 +4185,6 @@ int rtw_suspend_common(_adapter *padapter) { rtw_mi_cancel_all_timer(padapter); LeaveAllPowerSaveModeDirect(padapter); - rtw_stop_cmd_thread(padapter); - -#ifdef CONFIG_BT_COEXIST - /* wait for the latest FW to remove this condition. */ - if (rtw_mi_check_status(padapter, MI_AP_MODE)) { - rtw_btcoex_SuspendNotify(padapter, 0); - RTW_INFO("btcoex_SuspendNotify for WIFI_AP_STATE\n"); - } else { - rtw_btcoex_SuspendNotify(padapter, 1); - RTW_INFO("btcoex_SuspendNotify for STATION\n"); - } -#endif /* CONFIG_BT_COEXIST */ rtw_ps_deny_cancel(padapter, PS_DENY_SUSPEND); @@ -3793,33 +4205,30 @@ int rtw_suspend_common(_adapter *padapter) { if (pwrpriv->wowlan_mode == _TRUE) rtw_suspend_wow(padapter); else - rtw_suspend_normal(padapter); - -#else /* CONFIG_WOWLAN */ - rtw_suspend_normal(padapter); #endif /* CONFIG_WOWLAN */ + rtw_suspend_normal(padapter); } else if (rtw_mi_check_status(padapter, MI_AP_MODE)) { #ifdef CONFIG_AP_WOWLAN rtw_suspend_ap_wow(padapter); #else rtw_suspend_normal(padapter); #endif /*CONFIG_AP_WOWLAN*/ - } else - rtw_suspend_normal(padapter); + } RTW_PRINT("rtw suspend success in %d ms\n", - rtw_get_passing_time_ms(start_time)); + rtw_get_passing_time_ms(start_time)); exit: RTW_INFO("<=== %s return %d.............. in %dms\n", __FUNCTION__ - , ret, rtw_get_passing_time_ms(start_time)); + , ret, rtw_get_passing_time_ms(start_time)); return ret; } #ifdef CONFIG_WOWLAN -int rtw_resume_process_wow(_adapter *padapter) { +int rtw_resume_process_wow(_adapter *padapter) +{ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -3830,7 +4239,6 @@ int rtw_resume_process_wow(_adapter *padapter) { struct wowlan_ioctl_param poidparam; struct sta_info *psta = NULL; int ret = _SUCCESS; - _func_enter_; RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); @@ -3845,14 +4253,14 @@ int rtw_resume_process_wow(_adapter *padapter) { if (RTW_CANNOT_RUN(padapter)) { RTW_INFO("%s pdapter %p bDriverStopped %s bSurpriseRemoved %s\n" - , __func__, padapter - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); + , __func__, padapter + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False"); goto exit; } + pwrpriv->wowlan_in_resume = _TRUE; #ifdef CONFIG_PNO_SUPPORT - pwrpriv->pno_in_resume = _TRUE; #ifdef CONFIG_FWLPS_IN_IPS if (pwrpriv->wowlan_pno_enable) rtw_set_fw_in_ips_mode(padapter, _FALSE); @@ -3861,22 +4269,26 @@ int rtw_resume_process_wow(_adapter *padapter) { if (pwrpriv->wowlan_mode == _TRUE) { #ifdef CONFIG_LPS - rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN"); + if (!(pwrpriv->wowlan_dis_lps)) { + rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN"); + rtw_wow_lps_level_decide(padapter, _FALSE); + } #endif /* CONFIG_LPS */ pwrpriv->bFwCurrentInPSMode = _FALSE; -#ifdef CONFIG_SDIO_HCI +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI) rtw_mi_intf_stop(padapter); rtw_hal_clear_interrupt(padapter); -#endif /* CONFIG_SDIO_HCI */ +#endif +#if !(CONFIG_RTW_SDIO_KEEP_IRQ) /* if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { */ if ((padapter->intf_alloc_irq) && (padapter->intf_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS)) { ret = -1; - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: sdio_alloc_irq Failed!!\n", __FUNCTION__)); goto exit; } +#endif /* Disable WOW, set H2C command */ poidparam.subcode = WOWLAN_DISABLE; @@ -3915,17 +4327,17 @@ int rtw_resume_process_wow(_adapter *padapter) { } if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) { - if (pwrpriv->wowlan_wake_reason == FWDecisionDisconnect || - pwrpriv->wowlan_wake_reason == Rx_DisAssoc || - pwrpriv->wowlan_wake_reason == Rx_DeAuth) { + if (pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT || + pwrpriv->wowlan_wake_reason == RX_DISASSOC|| + pwrpriv->wowlan_wake_reason == RX_DEAUTH) { RTW_INFO("%s: disconnect reason: %02x\n", __func__, - pwrpriv->wowlan_wake_reason); + pwrpriv->wowlan_wake_reason); rtw_indicate_disconnect(padapter, 0, _FALSE); rtw_sta_media_status_rpt(padapter, - rtw_get_stainfo(&padapter->stapriv, - get_bssid(&padapter->mlmepriv)), 0); + rtw_get_stainfo(&padapter->stapriv, + get_bssid(&padapter->mlmepriv)), 0); rtw_free_assoc_resources(padapter, 1); pmlmeinfo->state = WIFI_FW_NULL_STATE; @@ -3936,30 +4348,24 @@ int rtw_resume_process_wow(_adapter *padapter) { } } - if (pwrpriv->wowlan_wake_reason == FWDecisionDisconnect) + if (pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT) rtw_lock_ext_suspend_timeout(2000); - if (pwrpriv->wowlan_wake_reason == Rx_GTK || - pwrpriv->wowlan_wake_reason == Rx_DisAssoc || - pwrpriv->wowlan_wake_reason == Rx_DeAuth) + if (pwrpriv->wowlan_wake_reason == RX_GTK || + pwrpriv->wowlan_wake_reason == RX_DISASSOC|| + pwrpriv->wowlan_wake_reason == RX_DEAUTH) rtw_lock_ext_suspend_timeout(8000); - if (pwrpriv->wowlan_wake_reason == RX_PNOWakeUp) { -#ifdef CONFIG_IOCTL_CFG80211 -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) - u8 locally_generated = 1; - - cfg80211_disconnected(padapter->pnetdev, 0, NULL, 0, locally_generated, GFP_ATOMIC); -#else - cfg80211_disconnected(padapter->pnetdev, 0, NULL, 0, GFP_ATOMIC); -#endif -#endif /* CONFIG_IOCTL_CFG80211 */ + if (pwrpriv->wowlan_wake_reason == RX_PNO) { + #ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_disconnected(padapter->rtw_wdev, 0, NULL, 0, 1, GFP_ATOMIC); + #endif rtw_lock_ext_suspend_timeout(10000); } if (pwrpriv->wowlan_mode == _TRUE) { pwrpriv->bips_processing = _FALSE; - _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); + _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); #ifndef CONFIG_IPS_CHECK_IN_WD rtw_set_pwr_state_check_timer(pwrpriv); #endif @@ -3971,25 +4377,30 @@ int rtw_resume_process_wow(_adapter *padapter) { /* Power On LED */ #ifdef CONFIG_SW_LED - if (pwrpriv->wowlan_wake_reason == Rx_DisAssoc || - pwrpriv->wowlan_wake_reason == Rx_DeAuth || - pwrpriv->wowlan_wake_reason == FWDecisionDisconnect) + if (pwrpriv->wowlan_wake_reason == RX_DISASSOC|| + pwrpriv->wowlan_wake_reason == RX_DEAUTH|| + pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT) rtw_led_control(padapter, LED_CTL_NO_LINK); else rtw_led_control(padapter, LED_CTL_LINK); #endif /* clean driver side wake up reason. */ + pwrpriv->wowlan_last_wake_reason = pwrpriv->wowlan_wake_reason; pwrpriv->wowlan_wake_reason = 0; +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME); +#endif /* CONFIG_BT_COEXIST */ + exit: RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); - _func_exit_; return ret; } #endif /* #ifdef CONFIG_WOWLAN */ #ifdef CONFIG_AP_WOWLAN -int rtw_resume_process_ap_wow(_adapter *padapter) { +int rtw_resume_process_ap_wow(_adapter *padapter) +{ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct net_device *pnetdev = padapter->pnetdev; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); @@ -3999,7 +4410,6 @@ int rtw_resume_process_ap_wow(_adapter *padapter) { struct sta_info *psta = NULL; int ret = _SUCCESS; u8 ch, bw, offset; - _func_enter_; RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); @@ -4014,7 +4424,10 @@ int rtw_resume_process_ap_wow(_adapter *padapter) { #ifdef CONFIG_LPS - rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "AP-WOWLAN"); + if (!(pwrpriv->wowlan_dis_lps)) { + rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "AP-WOWLAN"); + rtw_wow_lps_level_decide(padapter, _FALSE); + } #endif /* CONFIG_LPS */ pwrpriv->bFwCurrentInPSMode = _FALSE; @@ -4026,7 +4439,6 @@ int rtw_resume_process_ap_wow(_adapter *padapter) { /* if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { */ if ((padapter->intf_alloc_irq) && (padapter->intf_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS)) { ret = -1; - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: sdio_alloc_irq Failed!!\n", __FUNCTION__)); goto exit; } @@ -4066,7 +4478,7 @@ int rtw_resume_process_ap_wow(_adapter *padapter) { iface = dvobj->padapters[i]; if ((iface) && rtw_is_adapter_up(iface)) { if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | _FW_LINKED)) - rtw_mi_buddy_reset_drv_sw(iface); + rtw_reset_drv_sw(iface); } } @@ -4083,17 +4495,21 @@ int rtw_resume_process_ap_wow(_adapter *padapter) { /* rtw_unlock_suspend(); */ #endif /* CONFIG_RESUME_IN_WORKQUEUE */ - if (pwrpriv->wowlan_wake_reason == AP_WakeUp) + if (pwrpriv->wowlan_wake_reason == AP_OFFLOAD_WAKEUP) rtw_lock_ext_suspend_timeout(8000); pwrpriv->bips_processing = _FALSE; - _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); + _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); #ifndef CONFIG_IPS_CHECK_IN_WD rtw_set_pwr_state_check_timer(pwrpriv); #endif /* clean driver side wake up reason. */ pwrpriv->wowlan_wake_reason = 0; +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME); +#endif /* CONFIG_BT_COEXIST */ + /* Power On LED */ #ifdef CONFIG_SW_LED @@ -4101,12 +4517,12 @@ int rtw_resume_process_ap_wow(_adapter *padapter) { #endif exit: RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); - _func_exit_; return ret; } #endif /* #ifdef CONFIG_APWOWLAN */ -void rtw_mi_resume_process_normal(_adapter *padapter) { +void rtw_mi_resume_process_normal(_adapter *padapter) +{ int i; _adapter *iface; struct mlme_priv *pmlmepriv; @@ -4134,14 +4550,14 @@ void rtw_mi_resume_process_normal(_adapter *padapter) { } } -int rtw_resume_process_normal(_adapter *padapter) { +int rtw_resume_process_normal(_adapter *padapter) +{ struct net_device *pnetdev; struct pwrctrl_priv *pwrpriv; struct dvobj_priv *psdpriv; struct debug_priv *pdbgpriv; int ret = _SUCCESS; - _func_enter_; if (!padapter) { ret = -1; @@ -4158,16 +4574,17 @@ int rtw_resume_process_normal(_adapter *padapter) { /* if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) */ if ((padapter->intf_init) && (padapter->intf_init(adapter_to_dvobj(padapter)) != _SUCCESS)) { ret = -1; - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: initialize SDIO Failed!!\n", __FUNCTION__)); goto exit; } + rtw_clr_surprise_removed(padapter); rtw_hal_disable_interrupt(padapter); +#if !(CONFIG_RTW_SDIO_KEEP_IRQ) /* if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) */ if ((padapter->intf_alloc_irq) && (padapter->intf_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS)) { ret = -1; - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: sdio_alloc_irq Failed!!\n", __FUNCTION__)); goto exit; } +#endif rtw_mi_reset_drv_sw(padapter); @@ -4186,6 +4603,11 @@ int rtw_resume_process_normal(_adapter *padapter) { RTW_INFO("pid[1]:%d\n", padapter->pid[1]); rtw_signal_process(padapter->pid[1], SIGUSR2); } + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME); +#endif /* CONFIG_BT_COEXIST */ + rtw_mi_resume_process_normal(padapter); #ifdef CONFIG_RESUME_IN_WORKQUEUE @@ -4194,17 +4616,16 @@ int rtw_resume_process_normal(_adapter *padapter) { RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); exit: - _func_exit_; return ret; } -int rtw_resume_common(_adapter *padapter) { +int rtw_resume_common(_adapter *padapter) +{ int ret = 0; u32 start_time = rtw_get_current_time(); struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _func_enter_; if (pwrpriv->bInSuspend == _FALSE) return 0; @@ -4217,10 +4638,8 @@ int rtw_resume_common(_adapter *padapter) { if (pwrpriv->wowlan_mode == _TRUE) rtw_resume_process_wow(padapter); else - rtw_resume_process_normal(padapter); -#else - rtw_resume_process_normal(padapter); #endif + rtw_resume_process_normal(padapter); } else if (rtw_mi_check_status(padapter, WIFI_AP_STATE)) { #ifdef CONFIG_AP_WOWLAN @@ -4228,35 +4647,29 @@ int rtw_resume_common(_adapter *padapter) { #else rtw_resume_process_normal(padapter); #endif /* CONFIG_AP_WOWLAN */ - } else - rtw_resume_process_normal(padapter); - -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SuspendNotify(padapter, 0); -#endif /* CONFIG_BT_COEXIST */ + } if (pwrpriv) { pwrpriv->bInSuspend = _FALSE; -#ifdef CONFIG_PNO_SUPPORT - pwrpriv->pno_in_resume = _FALSE; -#endif + pwrpriv->wowlan_in_resume = _FALSE; } RTW_PRINT("%s:%d in %d ms\n", __FUNCTION__ , ret, - rtw_get_passing_time_ms(start_time)); + rtw_get_passing_time_ms(start_time)); - _func_exit_; return ret; } #ifdef CONFIG_GPIO_API -u8 rtw_get_gpio(struct net_device *netdev, u8 gpio_num) { +u8 rtw_get_gpio(struct net_device *netdev, u8 gpio_num) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); return rtw_hal_get_gpio(adapter, gpio_num); } EXPORT_SYMBOL(rtw_get_gpio); -int rtw_set_gpio_output_value(struct net_device *netdev, u8 gpio_num, bool isHigh) { +int rtw_set_gpio_output_value(struct net_device *netdev, u8 gpio_num, bool isHigh) +{ u8 direction = 0; u8 res = -1; _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); @@ -4264,21 +4677,44 @@ int rtw_set_gpio_output_value(struct net_device *netdev, u8 gpio_num, bool isHi } EXPORT_SYMBOL(rtw_set_gpio_output_value); -int rtw_config_gpio(struct net_device *netdev, u8 gpio_num, bool isOutput) { +int rtw_config_gpio(struct net_device *netdev, u8 gpio_num, bool isOutput) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); return rtw_hal_config_gpio(adapter, gpio_num, isOutput); } EXPORT_SYMBOL(rtw_config_gpio); -int rtw_register_gpio_interrupt(struct net_device *netdev, int gpio_num, void(*callback)(u8 level)) { +int rtw_register_gpio_interrupt(struct net_device *netdev, int gpio_num, void(*callback)(u8 level)) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); return rtw_hal_register_gpio_interrupt(adapter, gpio_num, callback); } EXPORT_SYMBOL(rtw_register_gpio_interrupt); -int rtw_disable_gpio_interrupt(struct net_device *netdev, int gpio_num) { +int rtw_disable_gpio_interrupt(struct net_device *netdev, int gpio_num) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); return rtw_hal_disable_gpio_interrupt(adapter, gpio_num); } EXPORT_SYMBOL(rtw_disable_gpio_interrupt); #endif /* #ifdef CONFIG_GPIO_API */ + +#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE + +int rtw_vendor_ie_get_api(struct net_device *dev, int ie_num, char *extra, + u16 extra_len) +{ + int ret = 0; + + ret = rtw_vendor_ie_get_raw_data(dev, ie_num, extra, extra_len); + return ret; +} +EXPORT_SYMBOL(rtw_vendor_ie_get_api); + +int rtw_vendor_ie_set_api(struct net_device *dev, char *extra) +{ + return rtw_vendor_ie_set(dev, NULL, NULL, extra); +} +EXPORT_SYMBOL(rtw_vendor_ie_set_api); + +#endif diff --git a/os_dep/linux/recv_linux.c b/os_dep/linux/recv_linux.c index b996e00..2541885 100644 --- a/os_dep/linux/recv_linux.c +++ b/os_dep/linux/recv_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RECV_OSDEP_C_ #include @@ -107,7 +102,6 @@ int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 } else { #if 0 { - RT_TRACE(_module_rtl871x_recv_c_, _drv_crit_, ("%s: no enough memory to allocate SKB!\n", __func__)); rtw_free_recvframe(precvframe_if2, &precvpriv->free_recv_queue); rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue); @@ -178,6 +172,11 @@ int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter) { int res = _SUCCESS; + +#ifdef CONFIG_RTW_NAPI + skb_queue_head_init(&precvpriv->rx_napi_skb_queue); +#endif /* CONFIG_RTW_NAPI */ + return res; } @@ -198,6 +197,13 @@ void rtw_os_recv_resource_free(struct recv_priv *precvpriv) union recv_frame *precvframe; precvframe = (union recv_frame *) precvpriv->precv_frame_buf; + +#ifdef CONFIG_RTW_NAPI + if (skb_queue_len(&precvpriv->rx_napi_skb_queue)) + RTW_WARN("rx_napi_skb_queue not empty\n"); + rtw_skb_queue_purge(&precvpriv->rx_napi_skb_queue); +#endif /* CONFIG_RTW_NAPI */ + for (i = 0; i < NR_RECVFRAME; i++) { if (precvframe->u.hdr.pkt) { rtw_skb_free(precvframe->u.hdr.pkt);/* free skb by driver */ @@ -316,8 +322,8 @@ _pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 _rtw_memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE))) { /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ skb_pull(sub_skb, SNAP_SIZE); - _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN); - _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pdata+6, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pdata, ETH_ALEN); } else { u16 len; /* Leave Ethernet header part of hdr and full payload */ @@ -330,6 +336,69 @@ _pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 return sub_skb; } +#ifdef CONFIG_RTW_NAPI +static int napi_recv(_adapter *padapter, int budget) +{ + _pkt *pskb; + struct recv_priv *precvpriv = &padapter->recvpriv; + int work_done = 0; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + u8 rx_ok; + + + while ((work_done < budget) && + (!skb_queue_empty(&precvpriv->rx_napi_skb_queue))) { + pskb = skb_dequeue(&precvpriv->rx_napi_skb_queue); + if (!pskb) + break; + + rx_ok = _FALSE; + +#ifdef CONFIG_RTW_GRO + if (pregistrypriv->en_gro) { + if (rtw_napi_gro_receive(&padapter->napi, pskb) != GRO_DROP) + rx_ok = _TRUE; + goto next; + } +#endif /* CONFIG_RTW_GRO */ + + if (rtw_netif_receive_skb(padapter->pnetdev, pskb) == NET_RX_SUCCESS) + rx_ok = _TRUE; + +next: + if (rx_ok == _TRUE) { + work_done++; + DBG_COUNTER(padapter->rx_logs.os_netif_ok); + } else { + DBG_COUNTER(padapter->rx_logs.os_netif_err); + } + } + + return work_done; +} + +int rtw_recv_napi_poll(struct napi_struct *napi, int budget) +{ + _adapter *padapter = container_of(napi, _adapter, napi); + int work_done = 0; + struct recv_priv *precvpriv = &padapter->recvpriv; + + + work_done = napi_recv(padapter, budget); + if (work_done < budget) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) + napi_complete_done(napi, work_done); +#else + napi_complete(napi); +#endif + if (!skb_queue_empty(&precvpriv->rx_napi_skb_queue)) + napi_schedule(napi); + } + + return work_done; +} +#endif /* CONFIG_RTW_NAPI */ + #ifdef DBG_UDP_PKT_LOSE_11AC #define PAYLOAD_LEN_LOC_OF_IP_HDR 0x10 /*ethernet payload length location of ip header (DA + SA+eth_type+(version&hdr_len)) */ #endif @@ -338,6 +407,7 @@ void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attri { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct recv_priv *precvpriv = &(padapter->recvpriv); + struct registry_priv *pregistrypriv = &padapter->registrypriv; #ifdef CONFIG_BR_EXT void *br_port = NULL; #endif @@ -447,6 +517,16 @@ void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attri pkt->ip_summed = CHECKSUM_NONE; #endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */ +#ifdef CONFIG_RTW_NAPI + if (pregistrypriv->en_napi) { + skb_queue_tail(&precvpriv->rx_napi_skb_queue, pkt); +#ifndef CONFIG_RTW_NAPI_V2 + napi_schedule(&padapter->napi); +#endif /* !CONFIG_RTW_NAPI_V2 */ + return; + } +#endif /* CONFIG_RTW_NAPI */ + ret = rtw_netif_rx(padapter->pnetdev, pkt); if (ret == NET_RX_SUCCESS) DBG_COUNTER(padapter->rx_logs.os_netif_ok); @@ -512,7 +592,6 @@ void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame) struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; struct net_device *pmgnt_netdev = phostapdpriv->pmgnt_netdev; - RT_TRACE(_module_recv_osdep_c_, _drv_info_, ("+rtw_hostapd_mlme_rx\n")); skb = precv_frame->u.hdr.pkt; @@ -666,14 +745,9 @@ int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame) skb = precv_frame->u.hdr.pkt; if (skb == NULL) { - RT_TRACE(_module_recv_osdep_c_, _drv_err_, ("rtw_recv_indicatepkt():skb==NULL something wrong!!!!\n")); goto _recv_indicatepkt_drop; } - RT_TRACE(_module_recv_osdep_c_, _drv_info_, ("rtw_recv_indicatepkt():skb != NULL !!!\n")); - RT_TRACE(_module_recv_osdep_c_, _drv_info_, ("rtw_recv_indicatepkt():precv_frame->u.hdr.rx_head=%p precv_frame->hdr.rx_data=%p\n", precv_frame->u.hdr.rx_head, precv_frame->u.hdr.rx_data)); - RT_TRACE(_module_recv_osdep_c_, _drv_info_, ("precv_frame->hdr.rx_tail=%p precv_frame->u.hdr.rx_end=%p precv_frame->hdr.len=%d\n", precv_frame->u.hdr.rx_tail, precv_frame->u.hdr.rx_end, - precv_frame->u.hdr.len)); skb->data = precv_frame->u.hdr.rx_data; @@ -681,8 +755,6 @@ int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame) skb->len = precv_frame->u.hdr.len; - RT_TRACE(_module_recv_osdep_c_, _drv_info_, ("\n skb->head=%p skb->data=%p skb->tail=%p skb->end=%p skb->len=%d\n", skb->head, skb->data, skb_tail_pointer(skb), skb_end_pointer(skb), - skb->len)); if (pattrib->eth_type == 0x888e) RTW_PRINT("recv eapol packet\n"); @@ -759,7 +831,6 @@ int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame) rtw_free_recvframe(precv_frame, pfree_recv_queue); - RT_TRACE(_module_recv_osdep_c_, _drv_info_, ("\n rtw_recv_indicatepkt :after rtw_os_recv_indicate_pkt!!!!\n")); return _SUCCESS; @@ -799,17 +870,4 @@ void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf) #endif } -void _rtw_reordering_ctrl_timeout_handler(void *FunctionContext); -void _rtw_reordering_ctrl_timeout_handler(void *FunctionContext) -{ - struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)FunctionContext; - rtw_reordering_ctrl_timeout_handler(preorder_ctrl); -} - -void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl) -{ - _adapter *padapter = preorder_ctrl->padapter; - _init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter->pnetdev, _rtw_reordering_ctrl_timeout_handler, preorder_ctrl); - -} diff --git a/os_dep/linux/rtw_android.c b/os_dep/linux/rtw_android.c index f574a53..c8eeca3 100644 --- a/os_dep/linux/rtw_android.c +++ b/os_dep/linux/rtw_android.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifdef CONFIG_GPIO_WAKEUP #include @@ -27,9 +22,9 @@ #if defined(RTW_ENABLE_WIFI_CONTROL_FUNC) #include #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) -#include + #include #else -#include + #include #endif #endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */ @@ -96,7 +91,7 @@ const char *android_wifi_cmd_str[ANDROID_WIFI_CMD_MAX] = { #if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0)) "GTK_REKEY_OFFLOAD", #endif /* CONFIG_GTK_OL */ - /* Private command for P2P disable*/ +/* Private command for P2P disable*/ "P2P_DISABLE", "DRIVER_VERSION" }; @@ -184,7 +179,8 @@ unsigned int oob_gpio = 0; * total_len: the length of the command. * * */ -static int rtw_android_pno_setup(struct net_device *net, char *command, int total_len) { +static int rtw_android_pno_setup(struct net_device *net, char *command, int total_len) +{ pno_ssid_t pno_ssids_local[MAX_PNO_LIST_COUNT]; int res = -1; int nssid = 0; @@ -218,21 +214,21 @@ static int rtw_android_pno_setup(struct net_device *net, char *command, int tota memset(pno_ssids_local, 0, sizeof(pno_ssids_local)); if ((cmd_tlv_temp->prefix == PNO_TLV_PREFIX) && - (cmd_tlv_temp->version == PNO_TLV_VERSION) && - (cmd_tlv_temp->subver == PNO_TLV_SUBVERSION)) { + (cmd_tlv_temp->version == PNO_TLV_VERSION) && + (cmd_tlv_temp->subver == PNO_TLV_SUBVERSION)) { str_ptr += sizeof(cmd_tlv_t); tlv_size_left -= sizeof(cmd_tlv_t); nssid = rtw_parse_ssid_list_tlv(&str_ptr, pno_ssids_local, - MAX_PNO_LIST_COUNT, &tlv_size_left); + MAX_PNO_LIST_COUNT, &tlv_size_left); if (nssid <= 0) { RTW_INFO("SSID is not presented or corrupted ret=%d\n", nssid); goto exit_proc; } else { if ((str_ptr[0] != PNO_TLV_TYPE_TIME) || (tlv_size_left <= 1)) { RTW_INFO("%s scan duration corrupted field size %d\n", - __func__, tlv_size_left); + __func__, tlv_size_left); goto exit_proc; } str_ptr++; @@ -242,7 +238,7 @@ static int rtw_android_pno_setup(struct net_device *net, char *command, int tota if (str_ptr[0] != 0) { if ((str_ptr[0] != PNO_TLV_FREQ_REPEAT)) { RTW_INFO("%s pno repeat : corrupted field\n", - __func__); + __func__); goto exit_proc; } str_ptr++; @@ -250,13 +246,13 @@ static int rtw_android_pno_setup(struct net_device *net, char *command, int tota RTW_INFO("%s :got pno_repeat=%d\n", __FUNCTION__, pno_repeat); if (str_ptr[0] != PNO_TLV_FREQ_EXPO_MAX) { RTW_INFO("%s FREQ_EXPO_MAX corrupted field size\n", - __func__); + __func__); goto exit_proc; } str_ptr++; pno_freq_expo_max = simple_strtoul(str_ptr, &str_ptr, 16); RTW_INFO("%s: pno_freq_expo_max=%d\n", - __func__, pno_freq_expo_max); + __func__, pno_freq_expo_max); } } } else { @@ -285,7 +281,8 @@ static int rtw_android_pno_setup(struct net_device *net, char *command, int tota * */ int rtw_android_cfg80211_pno_setup(struct net_device *net, - struct cfg80211_ssid *ssids, int n_ssids, int interval) { + struct cfg80211_ssid *ssids, int n_ssids, int interval) +{ int res = -1; int nssid = 0; int pno_time = 0; @@ -314,7 +311,7 @@ int rtw_android_cfg80211_pno_setup(struct net_device *net, RTW_INFO("%s: nssids: %d, pno_time=%d\n", __func__, nssid, pno_time); res = rtw_dev_pno_set(net, pno_ssids_local, nssid, pno_time, - pno_repeat, pno_freq_expo_max); + pno_repeat, pno_freq_expo_max); #ifdef CONFIG_PNO_SET_DEBUG rtw_dev_pno_debug(net); @@ -323,7 +320,8 @@ int rtw_android_cfg80211_pno_setup(struct net_device *net, return res; } -int rtw_android_pno_enable(struct net_device *net, int pno_enable) { +int rtw_android_pno_enable(struct net_device *net, int pno_enable) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(net); struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); @@ -350,7 +348,8 @@ int rtw_android_pno_enable(struct net_device *net, int pno_enable) { } #endif /* CONFIG_PNO_SUPPORT */ -int rtw_android_cmdstr_to_num(char *cmdstr) { +int rtw_android_cmdstr_to_num(char *cmdstr) +{ int cmd_num; for (cmd_num = 0 ; cmd_num < ANDROID_WIFI_CMD_MAX; cmd_num++) if (0 == strnicmp(cmdstr , android_wifi_cmd_str[cmd_num], strlen(android_wifi_cmd_str[cmd_num]))) @@ -359,7 +358,8 @@ int rtw_android_cmdstr_to_num(char *cmdstr) { return cmd_num; } -int rtw_android_get_rssi(struct net_device *net, char *command, int total_len) { +int rtw_android_get_rssi(struct net_device *net, char *command, int total_len) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(net); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct wlan_network *pcur_network = &pmlmepriv->cur_network; @@ -367,13 +367,14 @@ int rtw_android_get_rssi(struct net_device *net, char *command, int total_len) { if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { bytes_written += snprintf(&command[bytes_written], total_len, "%s rssi %d", - pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi); + pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi); } return bytes_written; } -int rtw_android_get_link_speed(struct net_device *net, char *command, int total_len) { +int rtw_android_get_link_speed(struct net_device *net, char *command, int total_len) +{ _adapter *padapter = (_adapter *)rtw_netdev_priv(net); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct wlan_network *pcur_network = &pmlmepriv->cur_network; @@ -386,7 +387,8 @@ int rtw_android_get_link_speed(struct net_device *net, char *command, int total_ return bytes_written; } -int rtw_android_get_macaddr(struct net_device *net, char *command, int total_len) { +int rtw_android_get_macaddr(struct net_device *net, char *command, int total_len) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); int bytes_written = 0; @@ -394,7 +396,8 @@ int rtw_android_get_macaddr(struct net_device *net, char *command, int total_len return bytes_written; } -int rtw_android_set_country(struct net_device *net, char *command, int total_len) { +int rtw_android_set_country(struct net_device *net, char *command, int total_len) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); char *country_code = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_COUNTRY]) + 1; int ret = _FAIL; @@ -404,7 +407,8 @@ int rtw_android_set_country(struct net_device *net, char *command, int total_len return (ret == _SUCCESS) ? 0 : -1; } -int rtw_android_get_p2p_dev_addr(struct net_device *net, char *command, int total_len) { +int rtw_android_get_p2p_dev_addr(struct net_device *net, char *command, int total_len) +{ int bytes_written = 0; /* We use the same address as our HW MAC address */ @@ -414,7 +418,8 @@ int rtw_android_get_p2p_dev_addr(struct net_device *net, char *command, int tota return bytes_written; } -int rtw_android_set_block_scan(struct net_device *net, char *command, int total_len) { +int rtw_android_set_block_scan(struct net_device *net, char *command, int total_len) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK_SCAN]) + 1; @@ -425,7 +430,8 @@ int rtw_android_set_block_scan(struct net_device *net, char *command, int total_ return 0; } -int rtw_android_set_block(struct net_device *net, char *command, int total_len) { +int rtw_android_set_block(struct net_device *net, char *command, int total_len) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK]) + 1; @@ -436,7 +442,8 @@ int rtw_android_set_block(struct net_device *net, char *command, int total_len) return 0; } -int rtw_android_setband(struct net_device *net, char *command, int total_len) { +int rtw_android_setband(struct net_device *net, char *command, int total_len) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); char *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SETBAND]) + 1; u32 band = WIFI_FREQUENCY_BAND_AUTO; @@ -448,7 +455,8 @@ int rtw_android_setband(struct net_device *net, char *command, int total_len) { return (ret == _SUCCESS) ? 0 : -1; } -int rtw_android_getband(struct net_device *net, char *command, int total_len) { +int rtw_android_getband(struct net_device *net, char *command, int total_len) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); int bytes_written = 0; @@ -458,7 +466,8 @@ int rtw_android_getband(struct net_device *net, char *command, int total_len) { } #ifdef CONFIG_WFD -int rtw_android_set_miracast_mode(struct net_device *net, char *command, int total_len) { +int rtw_android_set_miracast_mode(struct net_device *net, char *command, int total_len) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); struct wifi_display_info *wfd_info = &adapter->wfd_info; char *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_MIRACAST]) + 1; @@ -493,7 +502,8 @@ int rtw_android_set_miracast_mode(struct net_device *net, char *command, int tot } #endif /* CONFIG_WFD */ -int get_int_from_command(char *pcmd) { +int get_int_from_command(char *pcmd) +{ int i = 0; for (i = 0; i < strlen(pcmd); i++) { @@ -507,7 +517,8 @@ int get_int_from_command(char *pcmd) { } #if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0)) -int rtw_gtk_offload(struct net_device *net, u8 *cmd_ptr) { +int rtw_gtk_offload(struct net_device *net, u8 *cmd_ptr) +{ int i; /* u8 *cmd_ptr = priv_cmd.buf; */ struct sta_info *psta; @@ -550,7 +561,8 @@ int rtw_gtk_offload(struct net_device *net, u8 *cmd_ptr) { } #endif /* CONFIG_GTK_OL */ -int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) { +int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) +{ int ret = 0; char *command = NULL; int cmd_num; @@ -576,22 +588,27 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) { goto exit; } #ifdef CONFIG_COMPAT - /* User space is 32-bit, use compat ioctl */ - compat_android_wifi_priv_cmd compat_priv_cmd; - - if (copy_from_user(&compat_priv_cmd, ifr->ifr_data, sizeof(compat_android_wifi_priv_cmd))) { - ret = -EFAULT; - goto exit; - } - priv_cmd.buf = compat_ptr(compat_priv_cmd.buf); - priv_cmd.used_len = compat_priv_cmd.used_len; - priv_cmd.total_len = compat_priv_cmd.total_len; +#if (KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE) + if (is_compat_task()) { +#else + if (in_compat_syscall()) { +#endif + /* User space is 32-bit, use compat ioctl */ + compat_android_wifi_priv_cmd compat_priv_cmd; + if (copy_from_user(&compat_priv_cmd, ifr->ifr_data, sizeof(compat_android_wifi_priv_cmd))) { + ret = -EFAULT; + goto exit; + } + priv_cmd.buf = compat_ptr(compat_priv_cmd.buf); + priv_cmd.used_len = compat_priv_cmd.used_len; + priv_cmd.total_len = compat_priv_cmd.total_len; + } else #endif /* CONFIG_COMPAT */ - if (copy_from_user(&priv_cmd, ifr->ifr_data, sizeof(android_wifi_priv_cmd))) { - ret = -EFAULT; - goto exit; - } + if (copy_from_user(&priv_cmd, ifr->ifr_data, sizeof(android_wifi_priv_cmd))) { + ret = -EFAULT; + goto exit; + } if (padapter->registrypriv.mp_mode == 1) { ret = -EFAULT; goto exit; @@ -615,7 +632,7 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) { } RTW_INFO("%s: Android private cmd \"%s\" on %s\n" - , __FUNCTION__, command, ifr->ifr_name); + , __FUNCTION__, command, ifr->ifr_name); cmd_num = rtw_android_cmdstr_to_num(command); @@ -629,7 +646,7 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) { if (!g_wifi_on) { RTW_INFO("%s: Ignore private cmd \"%s\" - iface %s is down\n" - , __FUNCTION__, command, ifr->ifr_name); + , __FUNCTION__, command, ifr->ifr_name); ret = 0; goto exit; } @@ -917,7 +934,8 @@ static struct resource *wifi_irqres = NULL; static int wifi_add_dev(void); static void wifi_del_dev(void); -int rtw_android_wifictrl_func_add(void) { +int rtw_android_wifictrl_func_add(void) +{ int ret = 0; sema_init(&wifi_control_sem, 0); @@ -937,14 +955,16 @@ int rtw_android_wifictrl_func_add(void) { return ret; } -void rtw_android_wifictrl_func_del(void) { +void rtw_android_wifictrl_func_del(void) +{ if (g_wifidev_registered) { wifi_del_dev(); g_wifidev_registered = 0; } } -void *wl_android_prealloc(int section, unsigned long size) { +void *wl_android_prealloc(int section, unsigned long size) +{ void *alloc_ptr = NULL; if (wifi_control_data && wifi_control_data->mem_prealloc) { alloc_ptr = wifi_control_data->mem_prealloc(section, size); @@ -960,7 +980,8 @@ void *wl_android_prealloc(int section, unsigned long size) { return NULL; } -int wifi_get_irq_number(unsigned long *irq_flags_ptr) { +int wifi_get_irq_number(unsigned long *irq_flags_ptr) +{ if (wifi_irqres) { *irq_flags_ptr = wifi_irqres->flags & IRQF_TRIGGER_MASK; return (int)wifi_irqres->start; @@ -972,7 +993,8 @@ int wifi_get_irq_number(unsigned long *irq_flags_ptr) { #endif } -int wifi_set_power(int on, unsigned long msec) { +int wifi_set_power(int on, unsigned long msec) +{ RTW_INFO("%s = %d\n", __FUNCTION__, on); if (wifi_control_data && wifi_control_data->set_power) wifi_control_data->set_power(on); @@ -982,7 +1004,8 @@ int wifi_set_power(int on, unsigned long msec) { } #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) -int wifi_get_mac_addr(unsigned char *buf) { +int wifi_get_mac_addr(unsigned char *buf) +{ RTW_INFO("%s\n", __FUNCTION__); if (!buf) return -EINVAL; @@ -993,7 +1016,8 @@ int wifi_get_mac_addr(unsigned char *buf) { #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) */ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) || defined(COMPAT_KERNEL_RELEASE) -void *wifi_get_country_code(char *ccode) { +void *wifi_get_country_code(char *ccode) +{ RTW_INFO("%s\n", __FUNCTION__); if (!ccode) return NULL; @@ -1003,16 +1027,18 @@ void *wifi_get_country_code(char *ccode) { } #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) */ -static int wifi_set_carddetect(int on) { +static int wifi_set_carddetect(int on) +{ RTW_INFO("%s = %d\n", __FUNCTION__, on); if (wifi_control_data && wifi_control_data->set_carddetect) wifi_control_data->set_carddetect(on); return 0; } -static int wifi_probe(struct platform_device *pdev) { +static int wifi_probe(struct platform_device *pdev) +{ struct wifi_platform_data *wifi_ctrl = - (struct wifi_platform_data *)(pdev->dev.platform_data); + (struct wifi_platform_data *)(pdev->dev.platform_data); int wifi_wake_gpio = 0; RTW_INFO("## %s\n", __FUNCTION__); @@ -1020,13 +1046,13 @@ static int wifi_probe(struct platform_device *pdev) { if (wifi_irqres == NULL) wifi_irqres = platform_get_resource_byname(pdev, - IORESOURCE_IRQ, "bcm4329_wlan_irq"); + IORESOURCE_IRQ, "bcm4329_wlan_irq"); else wifi_wake_gpio = wifi_irqres->start; #ifdef CONFIG_GPIO_WAKEUP - printk("%s: gpio:%d wifi_wake_gpio:%d\n", __func__, - wifi_irqres->start, wifi_wake_gpio); + RTW_INFO("%s: gpio:%d wifi_wake_gpio:%d\n", __func__, + (int)wifi_irqres->start, wifi_wake_gpio); if (wifi_wake_gpio > 0) { #ifdef CONFIG_PLATFORM_INTEL_BYT @@ -1036,10 +1062,10 @@ static int wifi_probe(struct platform_device *pdev) { gpio_direction_input(wifi_wake_gpio); oob_irq = gpio_to_irq(wifi_wake_gpio); #endif /* CONFIG_PLATFORM_INTEL_BYT */ - printk("%s oob_irq:%d\n", __func__, oob_irq); + RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq); } else if (wifi_irqres) { oob_irq = wifi_irqres->start; - printk("%s oob_irq:%d\n", __func__, oob_irq); + RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq); } #endif wifi_control_data = wifi_ctrl; @@ -1054,7 +1080,8 @@ static int wifi_probe(struct platform_device *pdev) { #ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN extern PADAPTER g_test_adapter; -static void shutdown_card(void) { +static void shutdown_card(void) +{ u32 addr; u8 tmp8, cnt = 0; @@ -1067,6 +1094,14 @@ static void shutdown_card(void) { LeaveAllPowerSaveMode(g_test_adapter); #endif /* CONFIG_FWLPS_IN_IPS */ +#ifdef CONFIG_WOWLAN +#ifdef CONFIG_GPIO_WAKEUP + /*default wake up pin change to BT*/ + RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__); + rtw_hal_switch_gpio_wl_ctrl(g_test_adapter, WAKEUP_GPIO_IDX, _FALSE); +#endif /* CONFIG_GPIO_WAKEUP */ +#endif /* CONFIG_WOWLAN */ + /* Leave SDIO HCI Suspend */ addr = 0x10250086; rtw_write8(g_test_adapter, addr, 0); @@ -1074,14 +1109,14 @@ static void shutdown_card(void) { tmp8 = rtw_read8(g_test_adapter, addr); cnt++; RTW_INFO(FUNC_ADPT_FMT ": polling SDIO_HSUS_CTRL(0x%x)=0x%x, cnt=%d\n", - FUNC_ADPT_ARG(g_test_adapter), addr, tmp8, cnt); + FUNC_ADPT_ARG(g_test_adapter), addr, tmp8, cnt); if (tmp8 & BIT(1)) break; if (cnt >= 100) { RTW_INFO(FUNC_ADPT_FMT ": polling 0x%x[1]==1 FAIL!!\n", - FUNC_ADPT_ARG(g_test_adapter), addr); + FUNC_ADPT_ARG(g_test_adapter), addr); break; } @@ -1099,27 +1134,28 @@ static void shutdown_card(void) { tmp8 |= BIT(4); rtw_write8(g_test_adapter, addr, tmp8); RTW_INFO(FUNC_ADPT_FMT ": read after write 0x%x=0x%x\n", - FUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr)); + FUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr)); addr = 0x05; tmp8 = rtw_read8(g_test_adapter, addr); tmp8 |= BIT(7); rtw_write8(g_test_adapter, addr, tmp8); RTW_INFO(FUNC_ADPT_FMT ": read after write 0x%x=0x%x\n", - FUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr)); + FUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr)); /* lock register page0 0x0~0xB read/write */ rtw_write8(g_test_adapter, 0x1C, 0x0E); rtw_set_surprise_removed(g_test_adapter); RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s\n", - FUNC_ADPT_ARG(g_test_adapter), rtw_is_surprise_removed(g_test_adapter) ? "True" : "False"); + FUNC_ADPT_ARG(g_test_adapter), rtw_is_surprise_removed(g_test_adapter) ? "True" : "False"); } #endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */ -static int wifi_remove(struct platform_device *pdev) { +static int wifi_remove(struct platform_device *pdev) +{ struct wifi_platform_data *wifi_ctrl = - (struct wifi_platform_data *)(pdev->dev.platform_data); + (struct wifi_platform_data *)(pdev->dev.platform_data); RTW_INFO("## %s\n", __FUNCTION__); wifi_control_data = wifi_ctrl; @@ -1132,9 +1168,10 @@ static int wifi_remove(struct platform_device *pdev) { } #ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN -static void wifi_shutdown(struct platform_device *pdev) { +static void wifi_shutdown(struct platform_device *pdev) +{ struct wifi_platform_data *wifi_ctrl = - (struct wifi_platform_data *)(pdev->dev.platform_data); + (struct wifi_platform_data *)(pdev->dev.platform_data); RTW_INFO("## %s\n", __FUNCTION__); @@ -1147,7 +1184,8 @@ static void wifi_shutdown(struct platform_device *pdev) { } #endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */ -static int wifi_suspend(struct platform_device *pdev, pm_message_t state) { +static int wifi_suspend(struct platform_device *pdev, pm_message_t state) +{ RTW_INFO("##> %s\n", __FUNCTION__); #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY) bcmsdh_oob_intr_set(0); @@ -1155,7 +1193,8 @@ static int wifi_suspend(struct platform_device *pdev, pm_message_t state) { return 0; } -static int wifi_resume(struct platform_device *pdev) { +static int wifi_resume(struct platform_device *pdev) +{ RTW_INFO("##> %s\n", __FUNCTION__); #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY) if (dhd_os_check_if_up(bcmsdh_get_drvdata())) @@ -1188,14 +1227,16 @@ static struct platform_driver wifi_device_legacy = { } }; -static int wifi_add_dev(void) { +static int wifi_add_dev(void) +{ RTW_INFO("## Calling platform_driver_register\n"); platform_driver_register(&wifi_device); platform_driver_register(&wifi_device_legacy); return 0; } -static void wifi_del_dev(void) { +static void wifi_del_dev(void) +{ RTW_INFO("## Unregister platform_driver_register\n"); platform_driver_unregister(&wifi_device); platform_driver_unregister(&wifi_device_legacy); @@ -1204,7 +1245,8 @@ static void wifi_del_dev(void) { #ifdef CONFIG_GPIO_WAKEUP #ifdef CONFIG_PLATFORM_INTEL_BYT -int wifi_configure_gpio(void) { +int wifi_configure_gpio(void) +{ if (gpio_request(oob_gpio, "oob_irq")) { RTW_INFO("## %s Cannot request GPIO\n", __FUNCTION__); return -1; @@ -1225,7 +1267,8 @@ int wifi_configure_gpio(void) { return 0; } #endif /* CONFIG_PLATFORM_INTEL_BYT */ -void wifi_free_gpio(unsigned int gpio) { +void wifi_free_gpio(unsigned int gpio) +{ #ifdef CONFIG_PLATFORM_INTEL_BYT if (gpio) gpio_free(gpio); diff --git a/os_dep/linux/rtw_cfgvendor.c b/os_dep/linux/rtw_cfgvendor.c index 990d780..79e3f98 100644 --- a/os_dep/linux/rtw_cfgvendor.c +++ b/os_dep/linux/rtw_cfgvendor.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include @@ -37,18 +32,16 @@ #include #include #include - +#include */ #include #ifdef DBG_MEM_ALLOC extern bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size); -struct sk_buff *dbg_rtw_cfg80211_vendor_event_alloc(struct wiphy *wiphy, int len, int event_id, gfp_t gfp - , const enum mstat_f flags, const char *func, const int line) { - _adapter *padapter = wiphy_to_adapter(wiphy); - struct wireless_dev *wdev = padapter->rtw_wdev; - +struct sk_buff *dbg_rtw_cfg80211_vendor_event_alloc(struct wiphy *wiphy, struct wireless_dev *wdev, int len, int event_id, gfp_t gfp + , const enum mstat_f flags, const char *func, const int line) +{ struct sk_buff *skb; unsigned int truesize = 0; @@ -65,16 +58,17 @@ struct sk_buff *dbg_rtw_cfg80211_vendor_event_alloc(struct wiphy *wiphy, int len RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, len, skb, truesize); rtw_mstat_update( - flags - , skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL - , truesize + flags + , skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , truesize ); return skb; } void dbg_rtw_cfg80211_vendor_event(struct sk_buff *skb, gfp_t gfp - , const enum mstat_f flags, const char *func, const int line) { + , const enum mstat_f flags, const char *func, const int line) +{ unsigned int truesize = skb->truesize; if (match_mstat_sniff_rules(flags, truesize)) @@ -83,14 +77,15 @@ void dbg_rtw_cfg80211_vendor_event(struct sk_buff *skb, gfp_t gfp cfg80211_vendor_event(skb, gfp); rtw_mstat_update( - flags - , MSTAT_FREE - , truesize + flags + , MSTAT_FREE + , truesize ); } struct sk_buff *dbg_rtw_cfg80211_vendor_cmd_alloc_reply_skb(struct wiphy *wiphy, int len - , const enum mstat_f flags, const char *func, const int line) { + , const enum mstat_f flags, const char *func, const int line) +{ struct sk_buff *skb; unsigned int truesize = 0; @@ -103,16 +98,17 @@ struct sk_buff *dbg_rtw_cfg80211_vendor_cmd_alloc_reply_skb(struct wiphy *wiphy, RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, len, skb, truesize); rtw_mstat_update( - flags - , skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL - , truesize + flags + , skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , truesize ); return skb; } int dbg_rtw_cfg80211_vendor_cmd_reply(struct sk_buff *skb - , const enum mstat_f flags, const char *func, const int line) { + , const enum mstat_f flags, const char *func, const int line) +{ unsigned int truesize = skb->truesize; int ret; @@ -122,16 +118,16 @@ int dbg_rtw_cfg80211_vendor_cmd_reply(struct sk_buff *skb ret = cfg80211_vendor_cmd_reply(skb); rtw_mstat_update( - flags - , MSTAT_FREE - , truesize + flags + , MSTAT_FREE + , truesize ); return ret; } -#define rtw_cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp) \ - dbg_rtw_cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp) \ + dbg_rtw_cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) #define rtw_cfg80211_vendor_event(skb, gfp) \ dbg_rtw_cfg80211_vendor_event(skb, gfp, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) @@ -144,9 +140,8 @@ int dbg_rtw_cfg80211_vendor_cmd_reply(struct sk_buff *skb #else struct sk_buff *rtw_cfg80211_vendor_event_alloc( - struct wiphy *wiphy, int len, int event_id, gfp_t gfp) { - _adapter *padapter = wiphy_to_adapter(wiphy); - struct wireless_dev *wdev = padapter->rtw_wdev; + struct wiphy *wiphy, struct wireless_dev *wdev, int len, int event_id, gfp_t gfp) +{ struct sk_buff *skb; #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0)) @@ -174,14 +169,15 @@ struct sk_buff *rtw_cfg80211_vendor_event_alloc( * be used). */ int rtw_cfgvendor_send_async_event(struct wiphy *wiphy, - struct net_device *dev, int event_id, const void *data, int len) { + struct net_device *dev, int event_id, const void *data, int len) +{ u16 kflags; struct sk_buff *skb; kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL; /* Alloc the SKB for vendor_event */ - skb = rtw_cfg80211_vendor_event_alloc(wiphy, len, event_id, kflags); + skb = rtw_cfg80211_vendor_event_alloc(wiphy, ndev_to_wdev(dev), len, event_id, kflags); if (!skb) { RTW_ERR(FUNC_NDEV_FMT" skb alloc failed", FUNC_NDEV_ARG(dev)); return -ENOMEM; @@ -196,7 +192,8 @@ int rtw_cfgvendor_send_async_event(struct wiphy *wiphy, } static int rtw_cfgvendor_send_cmd_reply(struct wiphy *wiphy, - struct net_device *dev, const void *data, int len) { + struct net_device *dev, const void *data, int len) +{ struct sk_buff *skb; /* Alloc the SKB for vendor_event */ @@ -232,17 +229,18 @@ static int rtw_cfgvendor_send_cmd_reply(struct wiphy *wiphy, #define MAX_FEATURE_SET_CONCURRRENT_GROUPS 3 #include -int rtw_dev_get_feature_set(struct net_device *dev) { +int rtw_dev_get_feature_set(struct net_device *dev) +{ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter); - HAL_VERSION *hal_ver = &HalData->VersionID; + HAL_VERSION *hal_ver = &HalData->version_id; int feature_set = 0; feature_set |= WIFI_FEATURE_INFRA; if (IS_8814A_SERIES(*hal_ver) || IS_8812_SERIES(*hal_ver) || - IS_8821_SERIES(*hal_ver)) + IS_8821_SERIES(*hal_ver)) feature_set |= WIFI_FEATURE_INFRA_5G; feature_set |= WIFI_FEATURE_P2P; @@ -253,7 +251,8 @@ int rtw_dev_get_feature_set(struct net_device *dev) { return feature_set; } -int *rtw_dev_get_feature_set_matrix(struct net_device *dev, int *num) { +int *rtw_dev_get_feature_set_matrix(struct net_device *dev, int *num) +{ int feature_set_full, mem_needed; int *ret; @@ -263,48 +262,49 @@ int *rtw_dev_get_feature_set_matrix(struct net_device *dev, int *num) { if (!ret) { RTW_ERR(FUNC_NDEV_FMT" failed to allocate %d bytes\n" - , FUNC_NDEV_ARG(dev), mem_needed); + , FUNC_NDEV_ARG(dev), mem_needed); return ret; } feature_set_full = rtw_dev_get_feature_set(dev); ret[0] = (feature_set_full & WIFI_FEATURE_INFRA) | - (feature_set_full & WIFI_FEATURE_INFRA_5G) | - (feature_set_full & WIFI_FEATURE_NAN) | - (feature_set_full & WIFI_FEATURE_D2D_RTT) | - (feature_set_full & WIFI_FEATURE_D2AP_RTT) | - (feature_set_full & WIFI_FEATURE_PNO) | - (feature_set_full & WIFI_FEATURE_BATCH_SCAN) | - (feature_set_full & WIFI_FEATURE_GSCAN) | - (feature_set_full & WIFI_FEATURE_HOTSPOT) | - (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) | - (feature_set_full & WIFI_FEATURE_EPR); + (feature_set_full & WIFI_FEATURE_INFRA_5G) | + (feature_set_full & WIFI_FEATURE_NAN) | + (feature_set_full & WIFI_FEATURE_D2D_RTT) | + (feature_set_full & WIFI_FEATURE_D2AP_RTT) | + (feature_set_full & WIFI_FEATURE_PNO) | + (feature_set_full & WIFI_FEATURE_BATCH_SCAN) | + (feature_set_full & WIFI_FEATURE_GSCAN) | + (feature_set_full & WIFI_FEATURE_HOTSPOT) | + (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) | + (feature_set_full & WIFI_FEATURE_EPR); ret[1] = (feature_set_full & WIFI_FEATURE_INFRA) | - (feature_set_full & WIFI_FEATURE_INFRA_5G) | - /* Not yet verified NAN with P2P */ - /* (feature_set_full & WIFI_FEATURE_NAN) | */ - (feature_set_full & WIFI_FEATURE_P2P) | - (feature_set_full & WIFI_FEATURE_D2AP_RTT) | - (feature_set_full & WIFI_FEATURE_D2D_RTT) | - (feature_set_full & WIFI_FEATURE_EPR); + (feature_set_full & WIFI_FEATURE_INFRA_5G) | + /* Not yet verified NAN with P2P */ + /* (feature_set_full & WIFI_FEATURE_NAN) | */ + (feature_set_full & WIFI_FEATURE_P2P) | + (feature_set_full & WIFI_FEATURE_D2AP_RTT) | + (feature_set_full & WIFI_FEATURE_D2D_RTT) | + (feature_set_full & WIFI_FEATURE_EPR); ret[2] = (feature_set_full & WIFI_FEATURE_INFRA) | - (feature_set_full & WIFI_FEATURE_INFRA_5G) | - (feature_set_full & WIFI_FEATURE_NAN) | - (feature_set_full & WIFI_FEATURE_D2D_RTT) | - (feature_set_full & WIFI_FEATURE_D2AP_RTT) | - (feature_set_full & WIFI_FEATURE_TDLS) | - (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) | - (feature_set_full & WIFI_FEATURE_EPR); + (feature_set_full & WIFI_FEATURE_INFRA_5G) | + (feature_set_full & WIFI_FEATURE_NAN) | + (feature_set_full & WIFI_FEATURE_D2D_RTT) | + (feature_set_full & WIFI_FEATURE_D2AP_RTT) | + (feature_set_full & WIFI_FEATURE_TDLS) | + (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) | + (feature_set_full & WIFI_FEATURE_EPR); *num = MAX_FEATURE_SET_CONCURRRENT_GROUPS; return ret; } static int rtw_cfgvendor_get_feature_set(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) { + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0; int reply; @@ -314,13 +314,14 @@ static int rtw_cfgvendor_get_feature_set(struct wiphy *wiphy, if (unlikely(err)) RTW_ERR(FUNC_NDEV_FMT" Vendor Command reply failed ret:%d\n" - , FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err); + , FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err); return err; } static int rtw_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) { + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0; struct sk_buff *skb; int *reply; @@ -330,13 +331,13 @@ static int rtw_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy, if (!reply) { RTW_ERR(FUNC_NDEV_FMT" Could not get feature list matrix\n" - , FUNC_NDEV_ARG(wdev_to_ndev(wdev))); + , FUNC_NDEV_ARG(wdev_to_ndev(wdev))); err = -EINVAL; return err; } mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) + - ATTRIBUTE_U32_LEN; + ATTRIBUTE_U32_LEN; /* Alloc the SKB for vendor_event */ skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed); @@ -354,7 +355,7 @@ static int rtw_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy, if (unlikely(err)) RTW_ERR(FUNC_NDEV_FMT" Vendor Command reply failed ret:%d\n" - , FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err); + , FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err); exit: rtw_mfree((u8 *)reply, sizeof(int) * num); return err; @@ -362,7 +363,8 @@ static int rtw_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy, #if defined(GSCAN_SUPPORT) && 0 int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy, - struct net_device *dev, void *data, int len, wl_vendor_event_t event) { + struct net_device *dev, void *data, int len, wl_vendor_event_t event) +{ u16 kflags; const void *ptr; struct sk_buff *skb; @@ -375,13 +377,13 @@ int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy, if (malloc_len > NLMSG_DEFAULT_SIZE) malloc_len = NLMSG_DEFAULT_SIZE; iter_cnt_to_send = - (malloc_len - VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t); + (malloc_len - VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t); total = total - iter_cnt_to_send; kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL; /* Alloc the SKB for vendor_event */ - skb = rtw_cfg80211_vendor_event_alloc(wiphy, malloc_len, event, kflags); + skb = rtw_cfg80211_vendor_event_alloc(wiphy, ndev_to_wdev(dev), malloc_len, event, kflags); if (!skb) { WL_ERR(("skb alloc failed")); return -ENOMEM; @@ -412,7 +414,8 @@ int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy, static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) { + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0; struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); dhd_pno_gscan_capabilities_t *reply = NULL; @@ -420,7 +423,7 @@ static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy, reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg), - DHD_PNO_GET_CAPABILITIES, NULL, &reply_len); + DHD_PNO_GET_CAPABILITIES, NULL, &reply_len); if (!reply) { WL_ERR(("Could not get capabilities\n")); err = -EINVAL; @@ -428,7 +431,7 @@ static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy, } err = rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg), - reply, reply_len); + reply, reply_len); if (unlikely(err)) WL_ERR(("Vendor Command reply failed ret:%d\n", err)); @@ -438,7 +441,8 @@ static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy, } static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) { + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0, type, band; struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); uint16 *reply = NULL; @@ -453,7 +457,7 @@ static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy, return -1; reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg), - DHD_PNO_GET_CHANNEL_LIST, &band, &reply_len); + DHD_PNO_GET_CHANNEL_LIST, &band, &reply_len); if (!reply) { WL_ERR(("Could not get channel list\n")); @@ -484,7 +488,8 @@ static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy, } static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) { + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0; struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); gscan_results_cache_t *results, *iter; @@ -498,12 +503,12 @@ static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg)); dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg)); results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg), - DHD_PNO_GET_BATCH_RESULTS, NULL, &reply_len); + DHD_PNO_GET_BATCH_RESULTS, NULL, &reply_len); if (!results) { WL_ERR(("No results to send %d\n", err)); err = rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg), - results, 0); + results, 0); if (unlikely(err)) WL_ERR(("Vendor Command reply failed ret:%d\n", err)); @@ -513,8 +518,8 @@ static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, num_scan_ids = reply_len & 0xFFFF; num_results = (reply_len & 0xFFFF0000) >> 16; mem_needed = (num_results * sizeof(wifi_gscan_result_t)) + - (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) + - VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN; + (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) + + VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN; if (mem_needed > (int32)NLMSG_DEFAULT_SIZE) { mem_needed = (int32)NLMSG_DEFAULT_SIZE; @@ -523,7 +528,7 @@ static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, complete = 1; WL_TRACE(("complete %d mem_needed %d max_mem %d\n", complete, mem_needed, - (int)NLMSG_DEFAULT_SIZE)); + (int)NLMSG_DEFAULT_SIZE)); /* Alloc the SKB for vendor_event */ skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed); if (unlikely(!skb)) { @@ -542,7 +547,7 @@ static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id); nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag); num_results_iter = - (mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t); + (mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t); if ((iter->tot_count - iter->tot_consumed) < num_results_iter) num_results_iter = iter->tot_count - iter->tot_consumed; @@ -552,11 +557,11 @@ static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, ptr = &iter->results[iter->tot_consumed]; iter->tot_consumed += num_results_iter; nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS, - num_results_iter * sizeof(wifi_gscan_result_t), ptr); + num_results_iter * sizeof(wifi_gscan_result_t), ptr); } nla_nest_end(skb, scan_hdr); mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN + - (num_results_iter * sizeof(wifi_gscan_result_t)); + (num_results_iter * sizeof(wifi_gscan_result_t)); iter = iter->next; } @@ -567,7 +572,8 @@ static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, } static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) { + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0; struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); int type, tmp = len; @@ -596,7 +602,8 @@ static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy, } static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) { + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0; struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); int type; @@ -619,7 +626,8 @@ static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy, } static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) { + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0; struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); gscan_scan_params_t *scan_param; @@ -660,36 +668,36 @@ static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy, nla_for_each_nested(iter1, iter, tmp1) { type = nla_type(iter1); ch_bucket = - scan_param->channel_bucket; + scan_param->channel_bucket; switch (type) { case GSCAN_ATTRIBUTE_BUCKET_ID: break; case GSCAN_ATTRIBUTE_BUCKET_PERIOD: ch_bucket[j].bucket_freq_multiple = - nla_get_u32(iter1) / 1000; + nla_get_u32(iter1) / 1000; break; case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS: ch_bucket[j].num_channels = - nla_get_u32(iter1); + nla_get_u32(iter1); break; case GSCAN_ATTRIBUTE_BUCKET_CHANNELS: nla_for_each_nested(iter2, iter1, tmp2) { if (k >= PFN_SWC_RSSI_WINDOW_MAX) break; ch_bucket[j].chan_list[k] = - nla_get_u32(iter2); + nla_get_u32(iter2); k++; } k = 0; break; case GSCAN_ATTRIBUTE_BUCKETS_BAND: ch_bucket[j].band = (uint16) - nla_get_u32(iter1); + nla_get_u32(iter1); break; case GSCAN_ATTRIBUTE_REPORT_EVENTS: ch_bucket[j].report_flag = (uint8) - nla_get_u32(iter1); + nla_get_u32(iter1); break; } } @@ -699,7 +707,7 @@ static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy, } if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg), - DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) { + DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) { WL_ERR(("Could not set GSCAN scan cfg\n")); err = -EINVAL; } @@ -710,7 +718,8 @@ static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy, } static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) { + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0; struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); gscan_hotlist_scan_params_t *hotlist_params; @@ -743,7 +752,7 @@ static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy, break; case GSCAN_ATTRIBUTE_RSSI_LOW: pbssid[j].rssi_reporting_threshold = - (int8) nla_get_u8(inner); + (int8) nla_get_u8(inner); break; case GSCAN_ATTRIBUTE_RSSI_HIGH: dummy = (int8) nla_get_u8(inner); @@ -765,7 +774,7 @@ static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy, } if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg), - DHD_PNO_GEOFENCE_SCAN_CFG_ID, hotlist_params, flush) < 0) { + DHD_PNO_GEOFENCE_SCAN_CFG_ID, hotlist_params, flush) < 0) { WL_ERR(("Could not set GSCAN HOTLIST cfg\n")); err = -EINVAL; goto exit; @@ -775,7 +784,8 @@ static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy, return err; } static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) { + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0, tmp, type; struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); gscan_batch_params_t batch_param; @@ -801,7 +811,7 @@ static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy, } if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg), - DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param, 0) < 0) { + DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param, 0) < 0) { WL_ERR(("Could not set batch cfg\n")); err = -EINVAL; return err; @@ -811,7 +821,8 @@ static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy, } static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) { + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0; struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); gscan_swc_params_t *significant_params; @@ -855,11 +866,11 @@ static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy, break; case GSCAN_ATTRIBUTE_RSSI_HIGH: pbssid[j].rssi_high_threshold = - (int8) nla_get_u8(inner); + (int8) nla_get_u8(inner); break; case GSCAN_ATTRIBUTE_RSSI_LOW: pbssid[j].rssi_low_threshold = - (int8) nla_get_u8(inner); + (int8) nla_get_u8(inner); break; } } @@ -871,7 +882,7 @@ static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy, significant_params->nbssid = j; if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg), - DHD_PNO_SIGNIFICANT_SCAN_CFG_ID, significant_params, flush) < 0) { + DHD_PNO_SIGNIFICANT_SCAN_CFG_ID, significant_params, flush) < 0) { WL_ERR(("Could not set GSCAN significant cfg\n")); err = -EINVAL; goto exit; @@ -883,7 +894,8 @@ static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy, #endif /* GSCAN_SUPPORT */ #if defined(RTT_SUPPORT) && 0 -void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data) { +void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data) +{ struct wireless_dev *wdev = (struct wireless_dev *)ctx; struct wiphy *wiphy; struct sk_buff *skb; @@ -903,7 +915,7 @@ void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data) { rtt_list = (struct list_head *)rtt_data; kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL; /* Alloc the SKB for vendor_event */ - skb = rtw_cfg80211_vendor_event_alloc(wiphy, tot_len, GOOGLE_RTT_COMPLETE_EVENT, kflags); + skb = rtw_cfg80211_vendor_event_alloc(wiphy, wdev, tot_len, GOOGLE_RTT_COMPLETE_EVENT, kflags); if (!skb) { WL_ERR(("skb alloc failed")); goto exit; @@ -947,7 +959,8 @@ void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data) { } static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev *wdev, - const void *data, int len) { + const void *data, int len) +{ int err = 0, rem, rem1, rem2, type; rtt_config_params_t rtt_param; rtt_target_info_t *rtt_target = NULL; @@ -970,7 +983,7 @@ static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev rtt_param.rtt_target_cnt = nla_get_u8(iter); if (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) { WL_ERR(("exceed max target count : %d\n", - rtt_param.rtt_target_cnt)); + rtt_param.rtt_target_cnt)); err = BCME_RANGE; } break; @@ -1016,8 +1029,8 @@ static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev goto exit; } WL_INFORM(("Target addr %s, Channel : %s for RTT\n", - bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf), - wf_chspec_ntoa(rtt_target->chanspec, chanbuf))); + bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf), + wf_chspec_ntoa(rtt_target->chanspec, chanbuf))); rtt_target++; } break; @@ -1033,7 +1046,8 @@ static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev } static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_dev *wdev, - const void *data, int len) { + const void *data, int len) +{ int err = 0, rem, type, target_cnt = 0; const struct nlattr *iter; struct ether_addr *mac_list = NULL, *mac_addr = NULL; @@ -1072,7 +1086,8 @@ static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_d return err; } static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_dev *wdev, - const void *data, int len) { + const void *data, int len) +{ int err = 0; struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); rtt_capabilities_t capability; @@ -1083,7 +1098,7 @@ static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_ goto exit; } err = rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg), - &capability, sizeof(capability)); + &capability, sizeof(capability)); if (unlikely(err)) WL_ERR(("Vendor Command reply failed ret:%d\n", err)); @@ -1093,7 +1108,8 @@ static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_ #endif /* RTT_SUPPORT */ static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) { + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0; u8 resp[1] = {'\0'}; @@ -1101,7 +1117,7 @@ static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy, err = rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), resp, 1); if (unlikely(err)) RTW_ERR(FUNC_NDEV_FMT"Vendor Command reply failed ret:%d\n" - , FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err); + , FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err); return err; #if 0 @@ -1113,7 +1129,7 @@ static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy, if (strncmp((char *)data, BRCM_VENDOR_SCMD_CAPA, strlen(BRCM_VENDOR_SCMD_CAPA)) == 0) { err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "cap", NULL, 0, - cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync); + cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync); if (unlikely(err)) { WL_ERR(("error (%d)\n", err)); return err; @@ -1123,7 +1139,7 @@ static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy, } err = rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg), - cfg->ioctl_buf, data_len + 1); + cfg->ioctl_buf, data_len + 1); if (unlikely(err)) WL_ERR(("Vendor Command reply failed ret:%d\n", err)); else @@ -1278,7 +1294,8 @@ static const struct nl80211_vendor_cmd_info rtw_vendor_events[] = { #endif /* GSCAN_SUPPORT */ }; -int rtw_cfgvendor_attach(struct wiphy *wiphy) { +int rtw_cfgvendor_attach(struct wiphy *wiphy) +{ RTW_INFO("Register RTW cfg80211 vendor cmd(0x%x) interface\n", NL80211_CMD_VENDOR); @@ -1290,7 +1307,8 @@ int rtw_cfgvendor_attach(struct wiphy *wiphy) { return 0; } -int rtw_cfgvendor_detach(struct wiphy *wiphy) { +int rtw_cfgvendor_detach(struct wiphy *wiphy) +{ RTW_INFO("Vendor: Unregister RTW cfg80211 vendor interface\n"); wiphy->vendor_commands = NULL; diff --git a/os_dep/linux/rtw_cfgvendor.h b/os_dep/linux/rtw_cfgvendor.h index 76763c9..9f36e9f 100644 --- a/os_dep/linux/rtw_cfgvendor.h +++ b/os_dep/linux/rtw_cfgvendor.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_CFGVENDOR_H_ #define _RTW_CFGVENDOR_H_ @@ -235,10 +230,10 @@ typedef enum gscan_complete_event { extern int rtw_cfgvendor_attach(struct wiphy *wiphy); extern int rtw_cfgvendor_detach(struct wiphy *wiphy); extern int rtw_cfgvendor_send_async_event(struct wiphy *wiphy, - struct net_device *dev, int event_id, const void *data, int len); + struct net_device *dev, int event_id, const void *data, int len); #if defined(GSCAN_SUPPORT) && 0 extern int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy, - struct net_device *dev, void *data, int len, wl_vendor_event_t event); + struct net_device *dev, void *data, int len, wl_vendor_event_t event); #endif #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */ diff --git a/os_dep/linux/rtw_proc.c b/os_dep/linux/rtw_proc.c index da108f8..38ae3b2 100644 --- a/os_dep/linux/rtw_proc.c +++ b/os_dep/linux/rtw_proc.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include /* tolower() */ #include @@ -30,7 +25,8 @@ static struct proc_dir_entry *rtw_proc = NULL; -inline struct proc_dir_entry *get_rtw_drv_proc(void) { +inline struct proc_dir_entry *get_rtw_drv_proc(void) +{ return rtw_proc; } @@ -51,7 +47,8 @@ inline struct proc_dir_entry *get_rtw_drv_proc(void) { #define get_proc_net init_net.proc_net #endif -inline struct proc_dir_entry *rtw_proc_create_dir(const char *name, struct proc_dir_entry *parent, void *data) { +inline struct proc_dir_entry *rtw_proc_create_dir(const char *name, struct proc_dir_entry *parent, void *data) +{ struct proc_dir_entry *entry; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) @@ -67,7 +64,8 @@ inline struct proc_dir_entry *rtw_proc_create_dir(const char *name, struct proc_ } inline struct proc_dir_entry *rtw_proc_create_entry(const char *name, struct proc_dir_entry *parent, - const struct file_operations *fops, void *data) { + const struct file_operations *fops, void * data) +{ struct proc_dir_entry *entry; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) @@ -83,26 +81,31 @@ inline struct proc_dir_entry *rtw_proc_create_entry(const char *name, struct pro return entry; } -static int proc_get_dummy(struct seq_file *m, void *v) { +static int proc_get_dummy(struct seq_file *m, void *v) +{ return 0; } -static int proc_get_drv_version(struct seq_file *m, void *v) { +static int proc_get_drv_version(struct seq_file *m, void *v) +{ dump_drv_version(m); return 0; } -static int proc_get_log_level(struct seq_file *m, void *v) { +static int proc_get_log_level(struct seq_file *m, void *v) +{ dump_log_level(m); return 0; } -static int proc_get_drv_cfg(struct seq_file *m, void *v) { +static int proc_get_drv_cfg(struct seq_file *m, void *v) +{ dump_drv_cfg(m); return 0; } -static ssize_t proc_set_log_level(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_log_level(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ char tmp[32]; int log_level; @@ -133,23 +136,27 @@ static ssize_t proc_set_log_level(struct file *file, const char __user *buffer, } #ifdef DBG_MEM_ALLOC -static int proc_get_mstat(struct seq_file *m, void *v) { +static int proc_get_mstat(struct seq_file *m, void *v) +{ rtw_mstat_dump(m); return 0; } #endif /* DBG_MEM_ALLOC */ -static int proc_get_country_chplan_map(struct seq_file *m, void *v) { +static int proc_get_country_chplan_map(struct seq_file *m, void *v) +{ dump_country_chplan_map(m); return 0; } -static int proc_get_chplan_id_list(struct seq_file *m, void *v) { +static int proc_get_chplan_id_list(struct seq_file *m, void *v) +{ dump_chplan_id_list(m); return 0; } -static int proc_get_chplan_test(struct seq_file *m, void *v) { +static int proc_get_chplan_test(struct seq_file *m, void *v) +{ dump_chplan_test(m); return 0; } @@ -159,27 +166,44 @@ static int proc_get_chplan_test(struct seq_file *m, void *v) { * init/deinit when register/unregister driver */ const struct rtw_proc_hdl drv_proc_hdls[] = { - {"ver_info", proc_get_drv_version, NULL}, - {"log_level", proc_get_log_level, proc_set_log_level}, - {"drv_cfg", proc_get_drv_cfg, NULL}, + RTW_PROC_HDL_SSEQ("ver_info", proc_get_drv_version, NULL), + RTW_PROC_HDL_SSEQ("log_level", proc_get_log_level, proc_set_log_level), + RTW_PROC_HDL_SSEQ("drv_cfg", proc_get_drv_cfg, NULL), #ifdef DBG_MEM_ALLOC - {"mstat", proc_get_mstat, NULL}, + RTW_PROC_HDL_SSEQ("mstat", proc_get_mstat, NULL), #endif /* DBG_MEM_ALLOC */ - {"country_chplan_map", proc_get_country_chplan_map, NULL}, - {"chplan_id_list", proc_get_chplan_id_list, NULL}, - {"chplan_test", proc_get_chplan_test, NULL}, + RTW_PROC_HDL_SSEQ("country_chplan_map", proc_get_country_chplan_map, NULL), + RTW_PROC_HDL_SSEQ("chplan_id_list", proc_get_chplan_id_list, NULL), + RTW_PROC_HDL_SSEQ("chplan_test", proc_get_chplan_test, NULL), }; const int drv_proc_hdls_num = sizeof(drv_proc_hdls) / sizeof(struct rtw_proc_hdl); -static int rtw_drv_proc_open(struct inode *inode, struct file *file) { +static int rtw_drv_proc_open(struct inode *inode, struct file *file) +{ /* struct net_device *dev = proc_get_parent_data(inode); */ ssize_t index = (ssize_t)PDE_DATA(inode); const struct rtw_proc_hdl *hdl = drv_proc_hdls + index; - return single_open(file, hdl->show, NULL); + void *private = NULL; + + if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) { + int res = seq_open(file, hdl->u.seq_op); + + if (res == 0) + ((struct seq_file *)file->private_data)->private = private; + + return res; + } else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) { + int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy; + + return single_open(file, show, private); + } else { + return -EROFS; + } } -static ssize_t rtw_drv_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) { +static ssize_t rtw_drv_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) +{ ssize_t index = (ssize_t)PDE_DATA(file_inode(file)); const struct rtw_proc_hdl *hdl = drv_proc_hdls + index; ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write; @@ -190,7 +214,16 @@ static ssize_t rtw_drv_proc_write(struct file *file, const char __user *buffer, return -EROFS; } -static const struct file_operations rtw_drv_proc_fops = { +static const struct file_operations rtw_drv_proc_seq_fops = { + .owner = THIS_MODULE, + .open = rtw_drv_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, + .write = rtw_drv_proc_write, +}; + +static const struct file_operations rtw_drv_proc_sseq_fops = { .owner = THIS_MODULE, .open = rtw_drv_proc_open, .read = seq_read, @@ -199,7 +232,8 @@ static const struct file_operations rtw_drv_proc_fops = { .write = rtw_drv_proc_write, }; -int rtw_drv_proc_init(void) { +int rtw_drv_proc_init(void) +{ int ret = _FAIL; ssize_t i; struct proc_dir_entry *entry = NULL; @@ -217,7 +251,13 @@ int rtw_drv_proc_init(void) { } for (i = 0; i < drv_proc_hdls_num; i++) { - entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_fops, (void *)i); + if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ) + entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_seq_fops, (void *)i); + else if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ) + entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_sseq_fops, (void *)i); + else + entry = NULL; + if (!entry) { rtw_warn_on(1); goto exit; @@ -230,7 +270,8 @@ int rtw_drv_proc_init(void) { return ret; } -void rtw_drv_proc_deinit(void) { +void rtw_drv_proc_deinit(void) +{ int i; if (rtw_proc == NULL) @@ -243,8 +284,71 @@ void rtw_drv_proc_deinit(void) { rtw_proc = NULL; } +#ifndef RTW_SEQ_FILE_TEST +#define RTW_SEQ_FILE_TEST 0 +#endif + +#if RTW_SEQ_FILE_TEST +#define RTW_SEQ_FILE_TEST_SHOW_LIMIT 300 +static void *proc_start_seq_file_test(struct seq_file *m, loff_t *pos) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_PRINT(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + if (*pos >= RTW_SEQ_FILE_TEST_SHOW_LIMIT) { + RTW_PRINT(FUNC_ADPT_FMT" pos:%llu, out of range return\n", FUNC_ADPT_ARG(adapter), *pos); + return NULL; + } + + RTW_PRINT(FUNC_ADPT_FMT" return pos:%lld\n", FUNC_ADPT_ARG(adapter), *pos); + return pos; +} +void proc_stop_seq_file_test(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_PRINT(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); +} + +void *proc_next_seq_file_test(struct seq_file *m, void *v, loff_t *pos) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + (*pos)++; + if (*pos >= RTW_SEQ_FILE_TEST_SHOW_LIMIT) { + RTW_PRINT(FUNC_ADPT_FMT" pos:%lld, out of range return\n", FUNC_ADPT_ARG(adapter), *pos); + return NULL; + } + + RTW_PRINT(FUNC_ADPT_FMT" return pos:%lld\n", FUNC_ADPT_ARG(adapter), *pos); + return pos; +} + +static int proc_get_seq_file_test(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + u32 pos = *((loff_t *)(v)); + RTW_PRINT(FUNC_ADPT_FMT" pos:%d\n", FUNC_ADPT_ARG(adapter), pos); + RTW_PRINT_SEL(m, FUNC_ADPT_FMT" pos:%d\n", FUNC_ADPT_ARG(adapter), pos); + return 0; +} + +struct seq_operations seq_file_test = { + .start = proc_start_seq_file_test, + .stop = proc_stop_seq_file_test, + .next = proc_next_seq_file_test, + .show = proc_get_seq_file_test, +}; +#endif /* RTW_SEQ_FILE_TEST */ + #ifdef CONFIG_SDIO_HCI -static int proc_get_sd_f0_reg_dump(struct seq_file *m, void *v) { +static int proc_get_sd_f0_reg_dump(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -253,7 +357,8 @@ static int proc_get_sd_f0_reg_dump(struct seq_file *m, void *v) { return 0; } -static int proc_get_sdio_local_reg_dump(struct seq_file *m, void *v) { +static int proc_get_sdio_local_reg_dump(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -261,9 +366,38 @@ static int proc_get_sdio_local_reg_dump(struct seq_file *m, void *v) { return 0; } +static int proc_get_sdio_card_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_sdio_card_info(m, adapter_to_dvobj(adapter)); + + return 0; +} #endif /* CONFIG_SDIO_HCI */ -static int proc_get_mac_reg_dump(struct seq_file *m, void *v) { +#ifdef RTW_HALMAC +#include "../../hal/hal_halmac.h" +static int proc_get_halmac_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_dump_halmac_info(m); + return 0; +} +#endif +static int proc_get_fw_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_dump_fw_info(m, adapter); + return 0; +} +static int proc_get_mac_reg_dump(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -272,7 +406,8 @@ static int proc_get_mac_reg_dump(struct seq_file *m, void *v) { return 0; } -static int proc_get_bb_reg_dump(struct seq_file *m, void *v) { +static int proc_get_bb_reg_dump(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -281,7 +416,18 @@ static int proc_get_bb_reg_dump(struct seq_file *m, void *v) { return 0; } -static int proc_get_rf_reg_dump(struct seq_file *m, void *v) { +static int proc_get_bb_reg_dump_ex(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + bb_reg_dump_ex(m, adapter); + + return 0; +} + +static int proc_get_rf_reg_dump(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -290,7 +436,18 @@ static int proc_get_rf_reg_dump(struct seq_file *m, void *v) { return 0; } -static int proc_get_dump_adapters_status(struct seq_file *m, void *v) { +static int proc_get_dump_tx_rate_bmp(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_tx_rate_bmp(m, adapter_to_dvobj(adapter)); + + return 0; +} + +static int proc_get_dump_adapters_status(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -298,18 +455,28 @@ static int proc_get_dump_adapters_status(struct seq_file *m, void *v) { return 0; } -static int proc_get_dump_adapters_info(struct seq_file *m, void *v) { + +#ifdef CONFIG_RTW_CUSTOMER_STR +static int proc_get_customer_str(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u8 cstr[RTW_CUSTOMER_STR_LEN]; - dump_adapters_info(m, adapter_to_dvobj(adapter)); + if (rtw_hal_customer_str_read(adapter, cstr) != _SUCCESS) + goto exit; + + RTW_PRINT_SEL(m, RTW_CUSTOMER_STR_FMT"\n", RTW_CUSTOMER_STR_ARG(cstr)); +exit: return 0; } +#endif /* CONFIG_RTW_CUSTOMER_STR */ /* gpio setting */ #ifdef CONFIG_GPIO_API -static ssize_t proc_set_config_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_config_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32] = {0}; @@ -334,7 +501,8 @@ static ssize_t proc_set_config_gpio(struct file *file, const char __user *buffer return count; } -static ssize_t proc_set_gpio_output_value(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_gpio_output_value(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32] = {0}; @@ -358,7 +526,8 @@ static ssize_t proc_set_gpio_output_value(struct file *file, const char __user * } return count; } -static int proc_get_gpio(struct seq_file *m, void *v) { +static int proc_get_gpio(struct seq_file *m, void *v) +{ u8 gpioreturnvalue = 0; struct net_device *dev = m->private; @@ -366,12 +535,13 @@ static int proc_get_gpio(struct seq_file *m, void *v) { if (!padapter) return -EFAULT; gpioreturnvalue = rtw_hal_get_gpio(padapter, padapter->pre_gpio_pin); - RTW_PRINT_SEL(m, "get_gpio %d:%d\n", padapter->pre_gpio_pin , gpioreturnvalue); + RTW_PRINT_SEL(m, "get_gpio %d:%d\n", padapter->pre_gpio_pin, gpioreturnvalue); return 0; } -static ssize_t proc_set_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32] = {0}; @@ -394,7 +564,80 @@ static ssize_t proc_set_gpio(struct file *file, const char __user *buffer, size_ return count; } #endif -static ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { + +#ifdef CONFIG_CHNL_LOAD_MAGT +static ssize_t proc_set_clm_result(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + char tmp[32] = {0}; + int clm_flag = 0; + int clm_scan_ms = SURVEY_TO; + u16 *clm_period = &pHalData->clm_period; + + RTW_INFO("DBG_RX_SEQ %s\n", __FUNCTION__); + + if (count < 1) { + RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); + return -EFAULT; + } + if (count > sizeof(tmp)) { + RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%d %d", &clm_flag, &clm_scan_ms); + + if (num < 2) { + RTW_INFO("argument size is less than 2\n"); + goto exit; + } + RTW_INFO(" clm_flag = %d clm_scan_ms =%d\n", clm_flag, clm_scan_ms); + + padapter->clm_flag = (BOOLEAN)clm_flag; + RTW_INFO("clm feature on or off = %d\n", (int)padapter->clm_flag); + if (clm_flag == TRUE) { + if (clm_scan_ms > 200 || clm_scan_ms < 6) { + RTW_INFO("clm scan time need between 6 ~ 200ms\n"); + goto exit; + } + if (clm_scan_ms > 5 && clm_scan_ms <= 200) + *clm_period = (u16)((clm_scan_ms - 5)*1000/4); + pmlmeext->sitesurvey_res.scan_ch_ms = (u16)clm_scan_ms; + + RTW_INFO("clm_period = %u\n", pHalData->clm_period); + + } + } +exit: + return count; +} +static int proc_get_clm_result(struct seq_file *m, void *v) +{ + + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + u32 i; + + for (i = 0; i < rfctl->max_chan_nums ; i++) { + if (hal_data->clm_period != 0) + RTW_PRINT_SEL(m, "clm_period = %6u;clm_result =%6d ;channel %3d = %3d %%\n", hal_data->clm_period, hal_data->clm_result[i], rfctl->channel_set[i].ChannelNum, (hal_data->clm_result[i]*100/hal_data->clm_period)); + /* "x*100" to show by percentage*/ + } + return 0; +} +#endif + +static ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -424,14 +667,16 @@ static ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer } return count; } -static int proc_get_rx_info_msg(struct seq_file *m, void *v) { +static int proc_get_rx_info_msg(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); rtw_hal_set_odm_var(padapter, HAL_ODM_RX_Dframe_INFO, m, _FALSE); return 0; } -static int proc_get_tx_info_msg(struct seq_file *m, void *v) { +static int proc_get_tx_info_msg(struct seq_file *m, void *v) +{ _irqL irqL; struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -468,8 +713,8 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) { plist = get_next(plist); if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), 6) != _TRUE)) { + && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), 6) != _TRUE)) { switch (psta->bw_mode) { @@ -512,7 +757,8 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) { } -static int proc_get_linked_info_dump(struct seq_file *m, void *v) { +static int proc_get_linked_info_dump(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); if (padapter) @@ -522,7 +768,8 @@ static int proc_get_linked_info_dump(struct seq_file *m, void *v) { } -static ssize_t proc_set_linked_info_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_linked_info_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -562,7 +809,90 @@ static ssize_t proc_set_linked_info_dump(struct file *file, const char __user *b return count; } -static int proc_get_mac_qinfo(struct seq_file *m, void *v) { +static int proc_get_turboedca_ctrl(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + + if (hal_data) + RTW_PRINT_SEL(m, "Turbo-EDCA :%s\n", (hal_data->dis_turboedca) ? "Disable" : "Enable"); + + return 0; +} + +static ssize_t proc_set_turboedca_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + + char tmp[32] = {0}; + int mode = 0, num = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) + return -EFAULT; + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + num = sscanf(tmp, "%d ", &mode); + + if (num != 1) { + RTW_INFO("argument number is wrong\n"); + return -EFAULT; + } + hal_data->dis_turboedca = mode; + } + return count; +} +#ifdef CONFIG_WOWLAN +static int proc_get_wow_lps_ctrl(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + + if (pwrctl) + RTW_PRINT_SEL(m, "WOW lps :%s\n", (pwrctl->wowlan_dis_lps) ? "Disable" : "Enable"); + + return 0; +} + +static ssize_t proc_set_wow_lps_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + + char tmp[32] = {0}; + int mode = 0, num = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) + return -EFAULT; + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + num = sscanf(tmp, "%d ", &mode); + + if (num != 1) { + RTW_INFO("argument number is wrong\n"); + return -EFAULT; + } + pwrctl->wowlan_dis_lps = mode; + RTW_INFO("WOW lps :%s\n", (pwrctl->wowlan_dis_lps) ? "Disable" : "Enable"); + } + return count; +} +#endif + +static int proc_get_mac_qinfo(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -571,7 +901,8 @@ static int proc_get_mac_qinfo(struct seq_file *m, void *v) { return 0; } -int proc_get_wifi_spec(struct seq_file *m, void *v) { +int proc_get_wifi_spec(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct registry_priv *pregpriv = &padapter->registrypriv; @@ -580,7 +911,8 @@ int proc_get_wifi_spec(struct seq_file *m, void *v) { return 0; } -static int proc_get_chan_plan(struct seq_file *m, void *v) { +static int proc_get_chan_plan(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -589,7 +921,8 @@ static int proc_get_chan_plan(struct seq_file *m, void *v) { return 0; } -static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; @@ -619,19 +952,22 @@ static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, return count; } -static int proc_get_country_code(struct seq_file *m, void *v) { +static int proc_get_country_code(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - if (adapter->mlmepriv.country_ent) - dump_country_chplan(m, adapter->mlmepriv.country_ent); + if (rfctl->country_ent) + dump_country_chplan(m, rfctl->country_ent); else RTW_PRINT_SEL(m, "unspecified\n"); return 0; } -static ssize_t proc_set_country_code(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_country_code(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; @@ -659,15 +995,25 @@ static ssize_t proc_set_country_code(struct file *file, const char __user *buffe return count; } -#ifdef CONFIG_DFS_MASTER -ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +#if CONFIG_RTW_MACADDR_ACL +static int proc_get_macaddr_acl(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_macaddr_acl(m, adapter); + return 0; +} + +ssize_t proc_set_macaddr_acl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *mlme = &adapter->mlmepriv; struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - char tmp[32]; - u8 ch, bw = CHANNEL_WIDTH_20, offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - int ms = -1; + char tmp[17 * NUM_ACL + 32] = {0}; + u8 mode; + u8 addr[ETH_ALEN]; if (count < 1) return -EFAULT; @@ -678,30 +1024,74 @@ ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, si } if (buffer && !copy_from_user(tmp, buffer, count)) { + /* mode [] */ + char *c, *next; - int num = sscanf(tmp, "%hhu %hhu %hhu %d", &ch, &bw, &offset, &ms); + next = tmp; + c = strsep(&next, " \t"); - if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3)) - goto exit; + if (sscanf(c, "%hhu", &mode) != 1) + return count; + + if (mode >= RTW_ACL_MODE_MAX) + mode = RTW_ACL_MODE_DISABLED; + + rtw_set_macaddr_acl(adapter, RTW_ACL_MODE_DISABLED); /* deinit first */ + if (mode == RTW_ACL_MODE_DISABLED) + return count; + + rtw_set_macaddr_acl(adapter, mode); + + /* macaddr list */ + c = strsep(&next, " \t"); + while (c != NULL) { + if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6) + break; + + if (rtw_check_invalid_mac_address(addr, 0) == _FALSE) + rtw_acl_add_sta(adapter, addr); + + c = strsep(&next, " \t"); + } - if (bw == CHANNEL_WIDTH_20) - rtw_chset_update_non_ocp_ms(mlmeext->channel_set - , ch, bw, HAL_PRIME_CHNL_OFFSET_DONT_CARE, ms); - else - rtw_chset_update_non_ocp_ms(mlmeext->channel_set - , ch, bw, offset, ms); } exit: return count; } +#endif /* CONFIG_RTW_MACADDR_ACL */ + +#if CONFIG_RTW_PRE_LINK_STA +static int proc_get_pre_link_sta(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_pre_link_sta_ctl(m, &adapter->stapriv); + return 0; +} -ssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +ssize_t proc_set_pre_link_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - char tmp[32]; - u8 fake_radar_detect_cnt = 0; + struct mlme_priv *mlme = &adapter->mlmepriv; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + char tmp[17 * RTW_PRE_LINK_STA_NUM + 32] = {0}; + char arg0[16] = {0}; + u8 addr[ETH_ALEN]; + +#define PRE_LINK_STA_CMD_RESET 0 +#define PRE_LINK_STA_CMD_ADD 1 +#define PRE_LINK_STA_CMD_DEL 2 +#define PRE_LINK_STA_CMD_NUM 3 + + static const char * const pre_link_sta_cmd_str[] = { + "reset", + "add", + "del" + }; + u8 cmd_id = PRE_LINK_STA_CMD_NUM; if (count < 1) return -EFAULT; @@ -712,36 +1102,62 @@ ssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size } if (buffer && !copy_from_user(tmp, buffer, count)) { + /* cmd [] */ + char *c, *next; + int i; - int num = sscanf(tmp, "%hhu", &fake_radar_detect_cnt); + next = tmp; + c = strsep(&next, " \t"); - if (num < 1) + if (sscanf(c, "%s", arg0) != 1) goto exit; - rfctl->dbg_dfs_master_fake_radar_detect_cnt = fake_radar_detect_cnt; - } + for (i = 0; i < PRE_LINK_STA_CMD_NUM; i++) + if (strcmp(pre_link_sta_cmd_str[i], arg0) == 0) + cmd_id = i; -exit: - return count; -} + switch (cmd_id) { + case PRE_LINK_STA_CMD_RESET: + rtw_pre_link_sta_ctl_reset(&adapter->stapriv); + goto exit; + case PRE_LINK_STA_CMD_ADD: + case PRE_LINK_STA_CMD_DEL: + break; + default: + goto exit; + } -static int proc_get_dfs_ch_sel_d_flags(struct seq_file *m, void *v) { - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + /* macaddr list */ + c = strsep(&next, " \t"); + while (c != NULL) { + if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6) + break; - RTW_PRINT_SEL(m, "0x%02x\n", rfctl->dfs_ch_sel_d_flags); + if (rtw_check_invalid_mac_address(addr, 0) == _FALSE) { + if (cmd_id == PRE_LINK_STA_CMD_ADD) + rtw_pre_link_sta_add(&adapter->stapriv, addr); + else + rtw_pre_link_sta_del(&adapter->stapriv, addr); + } - return 0; + c = strsep(&next, " \t"); + } + } + +exit: + return count; } +#endif /* CONFIG_RTW_PRE_LINK_STA */ -static ssize_t proc_set_dfs_ch_sel_d_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +#ifdef CONFIG_DFS_MASTER +ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); char tmp[32]; - u8 d_flags; - int num; + u8 ch, bw = CHANNEL_WIDTH_20, offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + int ms = -1; if (count < 1) return -EFAULT; @@ -751,7 +1167,84 @@ static ssize_t proc_set_dfs_ch_sel_d_flags(struct file *file, const char __user return -EFAULT; } - if (!buffer || copy_from_user(tmp, buffer, count)) + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hhu %hhu %d", &ch, &bw, &offset, &ms); + + if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3)) + goto exit; + + if (bw == CHANNEL_WIDTH_20) + rtw_chset_update_non_ocp_ms(rfctl->channel_set + , ch, bw, HAL_PRIME_CHNL_OFFSET_DONT_CARE, ms); + else + rtw_chset_update_non_ocp_ms(rfctl->channel_set + , ch, bw, offset, ms); + } + +exit: + return count; +} + +ssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + char tmp[32]; + u8 fake_radar_detect_cnt = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu", &fake_radar_detect_cnt); + + if (num < 1) + goto exit; + + rfctl->dbg_dfs_master_fake_radar_detect_cnt = fake_radar_detect_cnt; + } + +exit: + return count; +} + +static int proc_get_dfs_ch_sel_d_flags(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + RTW_PRINT_SEL(m, "0x%02x\n", rfctl->dfs_ch_sel_d_flags); + + return 0; +} + +static ssize_t proc_set_dfs_ch_sel_d_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + char tmp[32]; + u8 d_flags; + int num; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (!buffer || copy_from_user(tmp, buffer, count)) goto exit; num = sscanf(tmp, "%hhx", &d_flags); @@ -765,7 +1258,57 @@ static ssize_t proc_set_dfs_ch_sel_d_flags(struct file *file, const char __user } #endif /* CONFIG_DFS_MASTER */ -static int proc_get_udpport(struct seq_file *m, void *v) { +#ifdef CONFIG_80211N_HT +int proc_get_rx_ampdu_size_limit(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_regsty_rx_ampdu_size_limit(m, adapter); + + return 0; +} + +ssize_t proc_set_rx_ampdu_size_limit(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *regsty = adapter_to_regsty(adapter); + char tmp[32]; + u8 nss; + u8 limit_by_bw[4] = {0xFF}; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int i; + int num = sscanf(tmp, "%hhu %hhu %hhu %hhu %hhu" + , &nss, &limit_by_bw[0], &limit_by_bw[1], &limit_by_bw[2], &limit_by_bw[3]); + + if (num < 2) + goto exit; + if (nss == 0 || nss > 4) + goto exit; + + for (i = 0; i < num - 1; i++) + regsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][i] = limit_by_bw[i]; + + rtw_rx_ampdu_apply(adapter); + } + +exit: + return count; +} +#endif /* CONFIG_80211N_HT */ + +static int proc_get_udpport(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct recv_priv *precvpriv = &(padapter->recvpriv); @@ -773,7 +1316,8 @@ static int proc_get_udpport(struct seq_file *m, void *v) { RTW_PRINT_SEL(m, "%d\n", precvpriv->sink_udpport); return 0; } -static ssize_t proc_set_udpport(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_udpport(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct recv_priv *precvpriv = &(padapter->recvpriv); @@ -810,7 +1354,8 @@ static ssize_t proc_set_udpport(struct file *file, const char __user *buffer, si } -static int proc_get_mi_ap_bc_info(struct seq_file *m, void *v) { +static int proc_get_mi_ap_bc_info(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); @@ -822,11 +1367,13 @@ static int proc_get_mi_ap_bc_info(struct seq_file *m, void *v) { return 0; } -static int proc_get_macid_info(struct seq_file *m, void *v) { +static int proc_get_macid_info(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u8 chip_type = rtw_get_chip_type(adapter); u8 i; u8 null_addr[ETH_ALEN] = {0}; u8 *macaddr; @@ -838,37 +1385,49 @@ static int proc_get_macid_info(struct seq_file *m, void *v) { dump_macid_map(m, &macid_ctl->used, macid_ctl->num); RTW_PRINT_SEL(m, "\n"); - RTW_PRINT_SEL(m, "%-3s %-3s %-4s %-4s %-17s %s" - "\n" - , "id", "bmc", "if_g", "ch_g", "macaddr", "status" - ); + RTW_PRINT_SEL(m, "%-3s %-3s %-4s %-4s %-17s %-6s %-3s" + , "id", "bmc", "if_g", "ch_g", "macaddr", "bw", "vht"); + + if (chip_type == RTL8814A) + _RTW_PRINT_SEL(m, " %-10s", "rate_bmp1"); + + _RTW_PRINT_SEL(m, " %-10s %s\n", "rate_bmp0", "status"); for (i = 0; i < macid_ctl->num; i++) { if (rtw_macid_is_used(macid_ctl, i) - || macid_ctl->h2c_msr[i] - ) { + || macid_ctl->h2c_msr[i] + ) { if (macid_ctl->sta[i]) macaddr = macid_ctl->sta[i]->hwaddr; else macaddr = null_addr; - RTW_PRINT_SEL(m, "%3u %3u %4d %4d "MAC_FMT" "H2C_MSR_FMT" %s" - "\n" - , i - , rtw_macid_is_bmc(macid_ctl, i) - , rtw_macid_get_if_g(macid_ctl, i) - , rtw_macid_get_ch_g(macid_ctl, i) - , MAC_ARG(macaddr) - , H2C_MSR_ARG(&macid_ctl->h2c_msr[i]) - , rtw_macid_is_used(macid_ctl, i) ? "" : "[unused]" - ); + RTW_PRINT_SEL(m, "%3u %3u %4d %4d "MAC_FMT" %6s %3u" + , i + , rtw_macid_is_bmc(macid_ctl, i) + , rtw_macid_get_if_g(macid_ctl, i) + , rtw_macid_get_ch_g(macid_ctl, i) + , MAC_ARG(macaddr) + , ch_width_str(macid_ctl->bw[i]) + , macid_ctl->vht_en[i] + ); + + if (chip_type == RTL8814A) + _RTW_PRINT_SEL(m, " 0x%08X", macid_ctl->rate_bmp1[i]); + + _RTW_PRINT_SEL(m, " 0x%08X "H2C_MSR_FMT" %s\n" + , macid_ctl->rate_bmp0[i] + , H2C_MSR_ARG(&macid_ctl->h2c_msr[i]) + , rtw_macid_is_used(macid_ctl, i) ? "" : "[unused]" + ); } } return 0; } -static int proc_get_sec_cam(struct seq_file *m, void *v) { +static int proc_get_sec_cam(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); @@ -891,7 +1450,8 @@ static int proc_get_sec_cam(struct seq_file *m, void *v) { return 0; } -static ssize_t proc_set_sec_cam(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_sec_cam(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); @@ -941,24 +1501,17 @@ static ssize_t proc_set_sec_cam(struct file *file, const char __user *buffer, si return count; } -static int proc_get_sec_cam_cache(struct seq_file *m, void *v) { +static int proc_get_sec_cam_cache(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - u8 i; - - RTW_PRINT_SEL(m, "SW sec cam cache:\n"); - dump_sec_cam_ent_title(m, 1); - for (i = 0; i < cam_ctl->num; i++) { - if (dvobj->cam_cache[i].ctrl != 0) - dump_sec_cam_ent(m, &dvobj->cam_cache[i], i); - } + dump_sec_cam_cache(m, adapter); return 0; } -static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *mlme = &(adapter->mlmepriv); @@ -990,7 +1543,88 @@ static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *bu return count; } -static int proc_get_target_tx_power(struct seq_file *m, void *v) { +static int proc_get_tx_bw_mode(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_PRINT_SEL(m, "0x%02x\n", adapter->driver_tx_bw_mode); + RTW_PRINT_SEL(m, "2.4G:%s\n", ch_width_str(ADAPTER_TX_BW_2G(adapter))); + RTW_PRINT_SEL(m, "5G:%s\n", ch_width_str(ADAPTER_TX_BW_5G(adapter))); + + return 0; +} + +static ssize_t proc_set_tx_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + struct mlme_priv *mlme = &(adapter->mlmepriv); + struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + char tmp[32]; + u8 bw_mode; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + u8 update = _FALSE; + int num = sscanf(tmp, "%hhx", &bw_mode); + + if (num < 1 || bw_mode == adapter->driver_tx_bw_mode) + goto exit; + + if ((MLME_STATE(adapter) & WIFI_ASOC_STATE) + && ((mlmeext->cur_channel <= 14 && BW_MODE_2G(bw_mode) != ADAPTER_TX_BW_2G(adapter)) + || (mlmeext->cur_channel >= 36 && BW_MODE_5G(bw_mode) != ADAPTER_TX_BW_5G(adapter))) + ) { + /* RA mask update needed */ + update = _TRUE; + } + adapter->driver_tx_bw_mode = bw_mode; + + if (update == _TRUE) { + struct sta_info *sta; + int i; + + for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { + sta = macid_ctl->sta[i]; + if (sta && !is_broadcast_mac_addr(sta->hwaddr)) + rtw_dm_ra_mask_wk_cmd(adapter, (u8 *)sta); + } + } + } + +exit: + return count; +} + +static int proc_get_hal_txpwr_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + + if (hal_is_band_support(adapter, BAND_ON_2_4G)) + dump_hal_txpwr_info_2g(m, adapter, hal_spec->rfpath_num_2g, hal_spec->max_tx_cnt); + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (hal_is_band_support(adapter, BAND_ON_5G)) + dump_hal_txpwr_info_5g(m, adapter, hal_spec->rfpath_num_5g, hal_spec->max_tx_cnt); +#endif + + return 0; +} + +static int proc_get_target_tx_power(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -999,7 +1633,8 @@ static int proc_get_target_tx_power(struct seq_file *m, void *v) { return 0; } -static int proc_get_tx_power_by_rate(struct seq_file *m, void *v) { +static int proc_get_tx_power_by_rate(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -1008,16 +1643,20 @@ static int proc_get_tx_power_by_rate(struct seq_file *m, void *v) { return 0; } -static int proc_get_tx_power_limit(struct seq_file *m, void *v) { +#ifdef CONFIG_TXPWR_LIMIT +static int proc_get_tx_power_limit(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - dump_tx_power_limit(m, adapter); + dump_txpwr_lmt(m, adapter); return 0; } +#endif /* CONFIG_TXPWR_LIMIT */ -static int proc_get_tx_power_ext_info(struct seq_file *m, void *v) { +static int proc_get_tx_power_ext_info(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -1026,7 +1665,8 @@ static int proc_get_tx_power_ext_info(struct seq_file *m, void *v) { return 0; } -static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -1045,9 +1685,9 @@ static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user * if (num < 1) return count; -#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE phy_free_filebuf_mask(adapter, LOAD_BB_PG_PARA_FILE | LOAD_RF_TXPWR_LMT_PARA_FILE); -#endif + #endif rtw_ps_deny(adapter, PS_DENY_IOCTL); LeaveAllPowerSaveModeDirect(adapter); @@ -1063,8 +1703,73 @@ static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user * return count; } +static void *proc_start_tx_power_idx(struct seq_file *m, loff_t *pos) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u8 path = ((*pos) & 0xFF00) >> 8; + u8 rs = *pos & 0xFF; + + if (path >= RF_PATH_MAX) + return NULL; + + return pos; +} +static void proc_stop_tx_power_idx(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); +} + +static void *proc_next_tx_power_idx(struct seq_file *m, void *v, loff_t *pos) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u8 path = ((*pos) & 0xFF00) >> 8; + u8 rs = *pos & 0xFF; + + rs++; + if (rs >= RATE_SECTION_NUM) { + rs = 0; + path++; + } + + if (path >= RF_PATH_MAX) + return NULL; + + *pos = (path << 8) | rs; + + return pos; +} + +static int proc_get_tx_power_idx(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u32 pos = *((loff_t *)(v)); + u8 path = (pos & 0xFF00) >> 8; + u8 rs = pos & 0xFF; + + if (0) + RTW_INFO("%s path=%u, rs=%u\n", __func__, path, rs); + + if (path == RF_PATH_A && rs == CCK) + dump_tx_power_idx_title(m, adapter); + dump_tx_power_idx_by_path_rs(m, adapter, path, rs); + + return 0; +} + +static struct seq_operations seq_ops_tx_power_idx = { + .start = proc_start_tx_power_idx, + .stop = proc_stop_tx_power_idx, + .next = proc_next_tx_power_idx, + .show = proc_get_tx_power_idx, +}; + #ifdef CONFIG_RF_POWER_TRIM -static int proc_get_kfree_flag(struct seq_file *m, void *v) { +static int proc_get_kfree_flag(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); @@ -1074,7 +1779,8 @@ static int proc_get_kfree_flag(struct seq_file *m, void *v) { return 0; } -static ssize_t proc_set_kfree_flag(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_kfree_flag(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); @@ -1099,7 +1805,8 @@ static ssize_t proc_set_kfree_flag(struct file *file, const char __user *buffer, return count; } -static int proc_get_kfree_bb_gain(struct seq_file *m, void *v) { +static int proc_get_kfree_bb_gain(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); @@ -1128,7 +1835,8 @@ static int proc_get_kfree_bb_gain(struct seq_file *m, void *v) { return 0; } -static ssize_t proc_set_kfree_bb_gain(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_kfree_bb_gain(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); @@ -1156,7 +1864,7 @@ static ssize_t proc_set_kfree_bb_gain(struct file *file, const char __user *buff } if (strcmp("2G", ch_band_Group) == 0) chidx = BB_GAIN_2G; -#ifdef CONFIG_NL80211_BAND_5GHZ +#ifdef CONFIG_IEEE80211_BAND_5GHZ else if (strcmp("5GLB1", ch_band_Group) == 0) chidx = BB_GAIN_5GLB1; else if (strcmp("5GLB2", ch_band_Group) == 0) @@ -1167,7 +1875,7 @@ static ssize_t proc_set_kfree_bb_gain(struct file *file, const char __user *buff chidx = BB_GAIN_5GMB2; else if (strcmp("5GHB", ch_band_Group) == 0) chidx = BB_GAIN_5GHB; -#endif /*CONFIG_NL80211_BAND_5GHZ*/ +#endif /*CONFIG_IEEE80211_BAND_5GHZ*/ else { RTW_INFO("Error Head Format, channel Group select\n,Please input:\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\n"); return count; @@ -1191,7 +1899,8 @@ static ssize_t proc_set_kfree_bb_gain(struct file *file, const char __user *buff } -static int proc_get_kfree_thermal(struct seq_file *m, void *v) { +static int proc_get_kfree_thermal(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); @@ -1201,7 +1910,8 @@ static int proc_get_kfree_thermal(struct seq_file *m, void *v) { return 0; } -static ssize_t proc_set_kfree_thermal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_kfree_thermal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); @@ -1226,7 +1936,8 @@ static ssize_t proc_set_kfree_thermal(struct file *file, const char __user *buff return count; } -static ssize_t proc_set_tx_gain_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_tx_gain_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *adapter; char tmp[32] = {0}; @@ -1258,7 +1969,8 @@ static ssize_t proc_set_tx_gain_offset(struct file *file, const char __user *buf #endif /* CONFIG_RF_POWER_TRIM */ #ifdef CONFIG_BT_COEXIST -ssize_t proc_set_btinfo_evt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +ssize_t proc_set_btinfo_evt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; @@ -1278,8 +1990,8 @@ ssize_t proc_set_btinfo_evt(struct file *file, const char __user *buffer, size_t _rtw_memset(btinfo, 0, 8); num = sscanf(tmp, "%hhx %hhx %hhx %hhx %hhx %hhx %hhx %hhx" - , &btinfo[0], &btinfo[1], &btinfo[2], &btinfo[3] - , &btinfo[4], &btinfo[5], &btinfo[6], &btinfo[7]); + , &btinfo[0], &btinfo[1], &btinfo[2], &btinfo[3] + , &btinfo[4], &btinfo[5], &btinfo[6], &btinfo[7]); if (num < 6) return -EINVAL; @@ -1307,7 +2019,8 @@ static u8 *btreg_type[] = { "le" }; -static int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val) { +static int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val) +{ u32 num; u8 str[80] = {0}; u8 t = 0; @@ -1347,7 +2060,7 @@ static int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val) { /* RF */ if (a & 0xFFFFFF80) { RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n", - __FUNCTION__, a, btreg_type[t], t); + __FUNCTION__, a, btreg_type[t], t); return -EINVAL; } break; @@ -1355,7 +2068,7 @@ static int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val) { /* Modem */ if (a & 0xFFFFFE00) { RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n", - __FUNCTION__, a, btreg_type[t], t); + __FUNCTION__, a, btreg_type[t], t); return -EINVAL; } break; @@ -1363,7 +2076,7 @@ static int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val) { /* Others(Bluewize, Vendor, LE) */ if (a & 0xFFFFF000) { RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n", - __FUNCTION__, a, btreg_type[t], t); + __FUNCTION__, a, btreg_type[t], t); return -EINVAL; } break; @@ -1383,7 +2096,8 @@ static int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val) { return 0; } -int proc_get_btreg_read(struct seq_file *m, void *v) { +int proc_get_btreg_read(struct seq_file *m, void *v) +{ struct net_device *dev; PADAPTER padapter; u16 ret; @@ -1405,7 +2119,8 @@ int proc_get_btreg_read(struct seq_file *m, void *v) { return 0; } -ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; PADAPTER padapter; u8 tmp[80] = {0}; @@ -1417,14 +2132,14 @@ ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t if (NULL == buffer) { RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", - FUNC_ADPT_ARG(padapter)); + FUNC_ADPT_ARG(padapter)); err = -EFAULT; goto exit; } if (count < 1) { RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", - FUNC_ADPT_ARG(padapter)); + FUNC_ADPT_ARG(padapter)); err = -EFAULT; goto exit; } @@ -1435,7 +2150,7 @@ ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t if (copy_from_user(tmp, buffer, num)) { RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n", - FUNC_ADPT_ARG(padapter)); + FUNC_ADPT_ARG(padapter)); err = -EFAULT; goto exit; } @@ -1447,7 +2162,7 @@ ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t goto exit; RTW_INFO(FUNC_ADPT_FMT ": addr=(%s)0x%X\n", - FUNC_ADPT_ARG(padapter), btreg_type[btreg_read_type], btreg_read_addr); + FUNC_ADPT_ARG(padapter), btreg_type[btreg_read_type], btreg_read_addr); exit: btreg_read_error = err; @@ -1455,7 +2170,8 @@ ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t return count; } -int proc_get_btreg_write(struct seq_file *m, void *v) { +int proc_get_btreg_write(struct seq_file *m, void *v) +{ struct net_device *dev; PADAPTER padapter; u16 ret; @@ -1481,7 +2197,8 @@ int proc_get_btreg_write(struct seq_file *m, void *v) { return 0; } -ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; PADAPTER padapter; u8 tmp[80] = {0}; @@ -1495,14 +2212,14 @@ ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_ if (NULL == buffer) { RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", - FUNC_ADPT_ARG(padapter)); + FUNC_ADPT_ARG(padapter)); err = -EFAULT; goto exit; } if (count < 1) { RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", - FUNC_ADPT_ARG(padapter)); + FUNC_ADPT_ARG(padapter)); err = -EFAULT; goto exit; } @@ -1513,7 +2230,7 @@ ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_ if (copy_from_user(tmp, buffer, num)) { RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n", - FUNC_ADPT_ARG(padapter)); + FUNC_ADPT_ARG(padapter)); err = -EFAULT; goto exit; } @@ -1523,7 +2240,7 @@ ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_ goto exit; RTW_INFO(FUNC_ADPT_FMT ": Set (%s)0x%X = 0x%x\n", - FUNC_ADPT_ARG(padapter), btreg_type[btreg_write_type], btreg_write_addr, val); + FUNC_ADPT_ARG(padapter), btreg_type[btreg_write_type], btreg_write_addr, val); ret = rtw_btcoex_btreg_write(padapter, btreg_write_type, btreg_write_addr, val); if (!CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS)) @@ -1537,7 +2254,8 @@ ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_ #endif /* CONFIG_BT_COEXIST */ #ifdef CONFIG_MBSSID_CAM -int proc_get_mbid_cam_cache(struct seq_file *m, void *v) { +int proc_get_mbid_cam_cache(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -1547,7 +2265,8 @@ int proc_get_mbid_cam_cache(struct seq_file *m, void *v) { } #endif /* CONFIG_MBSSID_CAM */ -int proc_get_mac_addr(struct seq_file *m, void *v) { +int proc_get_mac_addr(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -1555,7 +2274,8 @@ int proc_get_mac_addr(struct seq_file *m, void *v) { return 0; } -static int proc_get_skip_band(struct seq_file *m, void *v) { +static int proc_get_skip_band(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); int bandskip; @@ -1565,7 +2285,8 @@ static int proc_get_skip_band(struct seq_file *m, void *v) { return 0; } -static ssize_t proc_set_skip_band(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_skip_band(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[6]; @@ -1599,7 +2320,8 @@ static ssize_t proc_set_skip_band(struct file *file, const char __user *buffer, } #ifdef CONFIG_AUTO_CHNL_SEL_NHM -static int proc_get_best_chan(struct seq_file *m, void *v) { +static int proc_get_best_chan(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); u8 best_24g_ch = 0, best_5g_ch = 0; @@ -1611,7 +2333,8 @@ static int proc_get_best_chan(struct seq_file *m, void *v) { return 0; } -static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; @@ -1641,7 +2364,8 @@ static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_ } #endif -static int proc_get_hal_spec(struct seq_file *m, void *v) { +static int proc_get_hal_spec(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -1649,206 +2373,485 @@ static int proc_get_hal_spec(struct seq_file *m, void *v) { return 0; } +static int proc_get_phy_cap(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_dump_phy_cap(m, adapter); + rtw_dump_drv_phy_cap(m, adapter); + rtw_get_dft_phy_cap(m, adapter); + return 0; +} + +#ifdef CONFIG_SUPPORT_TRX_SHARED +#include "../../hal/hal_halmac.h" +static int proc_get_trx_share_mode(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_trx_share_mode(m, adapter); + return 0; +} +#endif + +static int proc_dump_rsvd_page(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_dump_rsvd_page(m, adapter, adapter->rsvd_page_offset, adapter->rsvd_page_num); + return 0; +} +static ssize_t proc_set_rsvd_page_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 page_offset, page_num; + + if (count < 2) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hhu", &page_offset, &page_num); + + if (num < 2) + return -EINVAL; + padapter->rsvd_page_offset = page_offset; + padapter->rsvd_page_num = page_num; + } + return count; +} + +#ifdef CONFIG_SUPPORT_FIFO_DUMP +static int proc_dump_fifo(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_dump_fifo(m, adapter, adapter->fifo_sel, adapter->fifo_addr, adapter->fifo_size); + return 0; +} +static ssize_t proc_set_fifo_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 fifo_sel = 0; + u32 fifo_addr = 0; + u32 fifo_size = 0; + + if (count < 3) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %x %d", &fifo_sel, &fifo_addr, &fifo_size); + + if (num < 3) + return -EINVAL; + + padapter->fifo_sel = fifo_sel; + padapter->fifo_addr = fifo_addr; + padapter->fifo_size = fifo_size; + } + return count; +} +#endif + +#ifdef CONFIG_WOW_PATTERN_HW_CAM +int proc_dump_pattern_cam(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + int i; + struct rtl_wow_pattern context; + + for (i = 0 ; i < pwrpriv->wowlan_pattern_idx; i++) { + rtw_wow_pattern_read_cam_ent(padapter, i, &context); + rtw_dump_wow_pattern(m, &context, i); + } + + return 0; +} +#endif + +static int proc_get_napi_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregistrypriv = &adapter->registrypriv; + u8 napi = 0, gro = 0; + u32 weight = 0; + + +#ifdef CONFIG_RTW_NAPI + if (pregistrypriv->en_napi) { + napi = 1; + weight = RTL_NAPI_WEIGHT; + } + +#ifdef CONFIG_RTW_GRO + if (pregistrypriv->en_gro) + gro = 1; +#endif /* CONFIG_RTW_GRO */ +#endif /* CONFIG_RTW_NAPI */ + + if (napi) + RTW_PRINT_SEL(m, "NAPI enable, weight=%d\n", weight); + else + RTW_PRINT_SEL(m, "NAPI disable\n"); + RTW_PRINT_SEL(m, "GRO %s\n", gro?"enable":"disable"); + + return 0; +} + +ssize_t proc_set_dynamic_agg_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + int enable = 0, i = 0; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + PADAPTER iface = NULL; + int num = sscanf(tmp, "%d", &enable); + + if (num != 1) { + RTW_INFO("invalid parameter!\n"); + return count; + } + + RTW_INFO("dynamic_agg_enable:%d\n", enable); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) + iface->registrypriv.dynamic_agg_enable = enable; + } + + } + + return count; + +} + +static int proc_get_dynamic_agg_enable(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregistrypriv = &adapter->registrypriv; + + RTW_PRINT_SEL(m, "dynamic_agg_enable:%d\n", pregistrypriv->dynamic_agg_enable); + + return 0; +} + /* * rtw_adapter_proc: * init/deinit when register/unregister net_device */ const struct rtw_proc_hdl adapter_proc_hdls[] = { - {"write_reg", proc_get_dummy, proc_set_write_reg}, - {"read_reg", proc_get_read_reg, proc_set_read_reg}, - {"adapters_status", proc_get_dump_adapters_status, NULL}, - {"adapters_info", proc_get_dump_adapters_info, NULL}, - {"fwstate", proc_get_fwstate, NULL}, - {"sec_info", proc_get_sec_info, NULL}, - {"mlmext_state", proc_get_mlmext_state, NULL}, - {"qos_option", proc_get_qos_option, NULL}, - {"ht_option", proc_get_ht_option, NULL}, - {"rf_info", proc_get_rf_info, NULL}, - {"scan_param", proc_get_scan_param, proc_set_scan_param}, - {"scan_abort", proc_get_scan_abort, NULL}, +#if RTW_SEQ_FILE_TEST + RTW_PROC_HDL_SEQ("seq_file_test", &seq_file_test, NULL), +#endif + RTW_PROC_HDL_SSEQ("write_reg", NULL, proc_set_write_reg), + RTW_PROC_HDL_SSEQ("read_reg", proc_get_read_reg, proc_set_read_reg), + RTW_PROC_HDL_SSEQ("tx_rate_bmp", proc_get_dump_tx_rate_bmp, NULL), + RTW_PROC_HDL_SSEQ("adapters_status", proc_get_dump_adapters_status, NULL), +#ifdef CONFIG_RTW_CUSTOMER_STR + RTW_PROC_HDL_SSEQ("customer_str", proc_get_customer_str, NULL), +#endif + RTW_PROC_HDL_SSEQ("fwstate", proc_get_fwstate, NULL), + RTW_PROC_HDL_SSEQ("sec_info", proc_get_sec_info, NULL), + RTW_PROC_HDL_SSEQ("mlmext_state", proc_get_mlmext_state, NULL), + RTW_PROC_HDL_SSEQ("qos_option", proc_get_qos_option, NULL), + RTW_PROC_HDL_SSEQ("ht_option", proc_get_ht_option, NULL), + RTW_PROC_HDL_SSEQ("rf_info", proc_get_rf_info, NULL), + RTW_PROC_HDL_SSEQ("scan_param", proc_get_scan_param, proc_set_scan_param), + RTW_PROC_HDL_SSEQ("scan_abort", proc_get_scan_abort, NULL), #ifdef CONFIG_SCAN_BACKOP - {"backop_flags_sta", proc_get_backop_flags_sta, proc_set_backop_flags_sta}, - {"backop_flags_ap", proc_get_backop_flags_ap, proc_set_backop_flags_ap}, + RTW_PROC_HDL_SSEQ("backop_flags_sta", proc_get_backop_flags_sta, proc_set_backop_flags_sta), + RTW_PROC_HDL_SSEQ("backop_flags_ap", proc_get_backop_flags_ap, proc_set_backop_flags_ap), #endif - {"survey_info", proc_get_survey_info, proc_set_survey_info}, - {"ap_info", proc_get_ap_info, NULL}, - {"trx_info", proc_get_trx_info, proc_reset_trx_info}, - {"rate_ctl", proc_get_rate_ctl, proc_set_rate_ctl}, - {"bw_ctl", proc_get_bw_ctl, proc_set_bw_ctl}, - {"dis_pwt_ctl", proc_get_dis_pwt, proc_set_dis_pwt}, - {"mac_qinfo", proc_get_mac_qinfo, NULL}, - {"macid_info", proc_get_macid_info, NULL}, - {"bcmc_info", proc_get_mi_ap_bc_info, NULL}, - {"sec_cam", proc_get_sec_cam, proc_set_sec_cam}, - {"sec_cam_cache", proc_get_sec_cam_cache, NULL}, - {"suspend_info", proc_get_suspend_resume_info, NULL}, - {"wifi_spec", proc_get_wifi_spec, NULL}, + RTW_PROC_HDL_SSEQ("survey_info", proc_get_survey_info, proc_set_survey_info), + RTW_PROC_HDL_SSEQ("ap_info", proc_get_ap_info, NULL), + RTW_PROC_HDL_SSEQ("trx_info", proc_get_trx_info, proc_reset_trx_info), + RTW_PROC_HDL_SSEQ("tx_power_offset", proc_get_tx_power_offset, proc_set_tx_power_offset), + RTW_PROC_HDL_SSEQ("rate_ctl", proc_get_rate_ctl, proc_set_rate_ctl), + RTW_PROC_HDL_SSEQ("bw_ctl", proc_get_bw_ctl, proc_set_bw_ctl), + RTW_PROC_HDL_SSEQ("dis_pwt_ctl", proc_get_dis_pwt, proc_set_dis_pwt), + RTW_PROC_HDL_SSEQ("mac_qinfo", proc_get_mac_qinfo, NULL), + RTW_PROC_HDL_SSEQ("macid_info", proc_get_macid_info, NULL), + RTW_PROC_HDL_SSEQ("bcmc_info", proc_get_mi_ap_bc_info, NULL), + RTW_PROC_HDL_SSEQ("sec_cam", proc_get_sec_cam, proc_set_sec_cam), + RTW_PROC_HDL_SSEQ("sec_cam_cache", proc_get_sec_cam_cache, NULL), + RTW_PROC_HDL_SSEQ("suspend_info", proc_get_suspend_resume_info, NULL), + RTW_PROC_HDL_SSEQ("wifi_spec", proc_get_wifi_spec, NULL), #ifdef CONFIG_LAYER2_ROAMING - {"roam_flags", proc_get_roam_flags, proc_set_roam_flags}, - {"roam_param", proc_get_roam_param, proc_set_roam_param}, - {"roam_tgt_addr", proc_get_dummy, proc_set_roam_tgt_addr}, + RTW_PROC_HDL_SSEQ("roam_flags", proc_get_roam_flags, proc_set_roam_flags), + RTW_PROC_HDL_SSEQ("roam_param", proc_get_roam_param, proc_set_roam_param), + RTW_PROC_HDL_SSEQ("roam_tgt_addr", NULL, proc_set_roam_tgt_addr), #endif /* CONFIG_LAYER2_ROAMING */ +#ifdef CONFIG_RTW_80211R + RTW_PROC_HDL_SSEQ("ft_flags", proc_get_ft_flags, proc_set_ft_flags), +#endif + #ifdef CONFIG_SDIO_HCI - {"sd_f0_reg_dump", proc_get_sd_f0_reg_dump, NULL}, - {"sdio_local_reg_dump", proc_get_sdio_local_reg_dump, NULL}, + RTW_PROC_HDL_SSEQ("sd_f0_reg_dump", proc_get_sd_f0_reg_dump, NULL), + RTW_PROC_HDL_SSEQ("sdio_local_reg_dump", proc_get_sdio_local_reg_dump, NULL), + RTW_PROC_HDL_SSEQ("sdio_card_info", proc_get_sdio_card_info, NULL), #endif /* CONFIG_SDIO_HCI */ - {"fwdl_test_case", proc_get_dummy, proc_set_fwdl_test_case}, - {"del_rx_ampdu_test_case", proc_get_dummy, proc_set_del_rx_ampdu_test_case}, - {"wait_hiq_empty", proc_get_dummy, proc_set_wait_hiq_empty}, + RTW_PROC_HDL_SSEQ("fwdl_test_case", NULL, proc_set_fwdl_test_case), + RTW_PROC_HDL_SSEQ("del_rx_ampdu_test_case", NULL, proc_set_del_rx_ampdu_test_case), + RTW_PROC_HDL_SSEQ("wait_hiq_empty", NULL, proc_set_wait_hiq_empty), + RTW_PROC_HDL_SSEQ("sta_linking_test", NULL, proc_set_sta_linking_test), - {"mac_reg_dump", proc_get_mac_reg_dump, NULL}, - {"bb_reg_dump", proc_get_bb_reg_dump, NULL}, - {"rf_reg_dump", proc_get_rf_reg_dump, NULL}, + RTW_PROC_HDL_SSEQ("mac_reg_dump", proc_get_mac_reg_dump, NULL), + RTW_PROC_HDL_SSEQ("bb_reg_dump", proc_get_bb_reg_dump, NULL), + RTW_PROC_HDL_SSEQ("bb_reg_dump_ex", proc_get_bb_reg_dump_ex, NULL), + RTW_PROC_HDL_SSEQ("rf_reg_dump", proc_get_rf_reg_dump, NULL), #ifdef CONFIG_AP_MODE - {"all_sta_info", proc_get_all_sta_info, NULL}, + RTW_PROC_HDL_SSEQ("all_sta_info", proc_get_all_sta_info, NULL), #endif /* CONFIG_AP_MODE */ #ifdef DBG_MEMORY_LEAK - {"_malloc_cnt", proc_get_malloc_cnt, NULL}, + RTW_PROC_HDL_SSEQ("_malloc_cnt", proc_get_malloc_cnt, NULL), #endif /* DBG_MEMORY_LEAK */ #ifdef CONFIG_FIND_BEST_CHANNEL - {"best_channel", proc_get_best_channel, proc_set_best_channel}, + RTW_PROC_HDL_SSEQ("best_channel", proc_get_best_channel, proc_set_best_channel), #endif - {"rx_signal", proc_get_rx_signal, proc_set_rx_signal}, - {"hw_info", proc_get_hw_status, NULL}, + RTW_PROC_HDL_SSEQ("rx_signal", proc_get_rx_signal, proc_set_rx_signal), + RTW_PROC_HDL_SSEQ("hw_info", proc_get_hw_status, proc_set_hw_status), #ifdef CONFIG_80211N_HT - {"ht_enable", proc_get_ht_enable, proc_set_ht_enable}, - {"bw_mode", proc_get_bw_mode, proc_set_bw_mode}, - {"ampdu_enable", proc_get_ampdu_enable, proc_set_ampdu_enable}, - {"rx_stbc", proc_get_rx_stbc, proc_set_rx_stbc}, - {"rx_ampdu", proc_get_rx_ampdu, proc_set_rx_ampdu}, - {"rx_ampdu_factor", proc_get_rx_ampdu_factor, proc_set_rx_ampdu_factor}, - {"rx_ampdu_density", proc_get_rx_ampdu_density, proc_set_rx_ampdu_density}, - {"tx_ampdu_density", proc_get_tx_ampdu_density, proc_set_tx_ampdu_density}, -#ifdef TX_AMSDU - {"tx_amsdu", proc_get_tx_amsdu, proc_set_tx_amsdu}, - {"tx_amsdu_rate", proc_get_tx_amsdu_rate, proc_set_tx_amsdu_rate}, + RTW_PROC_HDL_SSEQ("ht_enable", proc_get_ht_enable, proc_set_ht_enable), + RTW_PROC_HDL_SSEQ("bw_mode", proc_get_bw_mode, proc_set_bw_mode), + RTW_PROC_HDL_SSEQ("ampdu_enable", proc_get_ampdu_enable, proc_set_ampdu_enable), + RTW_PROC_HDL_SSEQ("rx_ampdu", proc_get_rx_ampdu, proc_set_rx_ampdu), + RTW_PROC_HDL_SSEQ("rx_ampdu_size_limit", proc_get_rx_ampdu_size_limit, proc_set_rx_ampdu_size_limit), + RTW_PROC_HDL_SSEQ("rx_ampdu_factor", proc_get_rx_ampdu_factor, proc_set_rx_ampdu_factor), + RTW_PROC_HDL_SSEQ("rx_ampdu_density", proc_get_rx_ampdu_density, proc_set_rx_ampdu_density), + RTW_PROC_HDL_SSEQ("tx_ampdu_density", proc_get_tx_ampdu_density, proc_set_tx_ampdu_density), +#ifdef CONFIG_TX_AMSDU + RTW_PROC_HDL_SSEQ("tx_amsdu", proc_get_tx_amsdu, proc_set_tx_amsdu), + RTW_PROC_HDL_SSEQ("tx_amsdu_rate", proc_get_tx_amsdu_rate, proc_set_tx_amsdu_rate), #endif #endif /* CONFIG_80211N_HT */ + RTW_PROC_HDL_SSEQ("tx_max_agg_num", proc_get_tx_max_agg_num, proc_set_tx_max_agg_num), - {"en_fwps", proc_get_en_fwps, proc_set_en_fwps}, - {"mac_rptbuf", proc_get_mac_rptbuf, NULL}, + RTW_PROC_HDL_SSEQ("en_fwps", proc_get_en_fwps, proc_set_en_fwps), + RTW_PROC_HDL_SSEQ("mac_rptbuf", proc_get_mac_rptbuf, NULL), - /* {"path_rssi", proc_get_two_path_rssi, NULL}, - * {"rssi_disp",proc_get_rssi_disp, proc_set_rssi_disp}, */ + /* RTW_PROC_HDL_SSEQ("path_rssi", proc_get_two_path_rssi, NULL), + * RTW_PROC_HDL_SSEQ("rssi_disp",proc_get_rssi_disp, proc_set_rssi_disp), */ #ifdef CONFIG_BT_COEXIST - {"btcoex_dbg", proc_get_btcoex_dbg, proc_set_btcoex_dbg}, - {"btcoex", proc_get_btcoex_info, NULL}, - {"btinfo_evt", proc_get_dummy, proc_set_btinfo_evt}, - {"btreg_read", proc_get_btreg_read, proc_set_btreg_read}, - {"btreg_write", proc_get_btreg_write, proc_set_btreg_write}, + RTW_PROC_HDL_SSEQ("btcoex_dbg", proc_get_btcoex_dbg, proc_set_btcoex_dbg), + RTW_PROC_HDL_SSEQ("btcoex", proc_get_btcoex_info, NULL), + RTW_PROC_HDL_SSEQ("btinfo_evt", NULL, proc_set_btinfo_evt), + RTW_PROC_HDL_SSEQ("btreg_read", proc_get_btreg_read, proc_set_btreg_read), + RTW_PROC_HDL_SSEQ("btreg_write", proc_get_btreg_write, proc_set_btreg_write), +#ifdef CONFIG_RF4CE_COEXIST + RTW_PROC_HDL_SSEQ("rf4ce_state", proc_get_rf4ce_state, proc_set_rf4ce_state), +#endif #endif /* CONFIG_BT_COEXIST */ #if defined(DBG_CONFIG_ERROR_DETECT) - {"sreset", proc_get_sreset, proc_set_sreset}, + RTW_PROC_HDL_SSEQ("sreset", proc_get_sreset, proc_set_sreset), #endif /* DBG_CONFIG_ERROR_DETECT */ - {"trx_info_debug", proc_get_trx_info_debug, NULL}, - {"linked_info_dump", proc_get_linked_info_dump, proc_set_linked_info_dump}, - {"tx_info_msg", proc_get_tx_info_msg, NULL}, - {"rx_info_msg", proc_get_rx_info_msg, proc_set_rx_info_msg}, + RTW_PROC_HDL_SSEQ("trx_info_debug", proc_get_trx_info_debug, NULL), + RTW_PROC_HDL_SSEQ("linked_info_dump", proc_get_linked_info_dump, proc_set_linked_info_dump), + RTW_PROC_HDL_SSEQ("dis_turboedca", proc_get_turboedca_ctrl, proc_set_turboedca_ctrl), + RTW_PROC_HDL_SSEQ("tx_info_msg", proc_get_tx_info_msg, NULL), + RTW_PROC_HDL_SSEQ("rx_info_msg", proc_get_rx_info_msg, proc_set_rx_info_msg), +#ifdef CONFIG_CHNL_LOAD_MAGT + RTW_PROC_HDL_SSEQ("clm_result", proc_get_clm_result, proc_set_clm_result), +#endif #ifdef CONFIG_GPIO_API - {"gpio_info", proc_get_gpio, proc_set_gpio}, - {"gpio_set_output_value", proc_get_dummy, proc_set_gpio_output_value}, - {"gpio_set_direction", proc_get_dummy, proc_set_config_gpio}, + RTW_PROC_HDL_SSEQ("gpio_info", proc_get_gpio, proc_set_gpio), + RTW_PROC_HDL_SSEQ("gpio_set_output_value", NULL, proc_set_gpio_output_value), + RTW_PROC_HDL_SSEQ("gpio_set_direction", NULL, proc_set_config_gpio), #endif #ifdef CONFIG_DBG_COUNTER - {"rx_logs", proc_get_rx_logs, NULL}, - {"tx_logs", proc_get_tx_logs, NULL}, - {"int_logs", proc_get_int_logs, NULL}, + RTW_PROC_HDL_SSEQ("rx_logs", proc_get_rx_logs, NULL), + RTW_PROC_HDL_SSEQ("tx_logs", proc_get_tx_logs, NULL), + RTW_PROC_HDL_SSEQ("int_logs", proc_get_int_logs, NULL), #endif #ifdef CONFIG_PCI_HCI - {"rx_ring", proc_get_rx_ring, NULL}, - {"tx_ring", proc_get_tx_ring, NULL}, + RTW_PROC_HDL_SSEQ("rx_ring", proc_get_rx_ring, NULL), + RTW_PROC_HDL_SSEQ("tx_ring", proc_get_tx_ring, NULL), + RTW_PROC_HDL_SSEQ("pci_aspm", proc_get_pci_aspm, NULL), #endif #ifdef CONFIG_WOWLAN - {"wow_pattern_info", proc_get_pattern_info, proc_set_pattern_info}, + RTW_PROC_HDL_SSEQ("wow_pattern_info", proc_get_pattern_info, proc_set_pattern_info), + RTW_PROC_HDL_SSEQ("wowlan_last_wake_reason", proc_get_wakeup_reason, NULL), +#ifdef CONFIG_WOW_PATTERN_HW_CAM + RTW_PROC_HDL_SSEQ("wow_pattern_cam", proc_dump_pattern_cam, NULL), +#endif + RTW_PROC_HDL_SSEQ("dis_wow_lps", proc_get_wow_lps_ctrl, proc_set_wow_lps_ctrl), #endif #ifdef CONFIG_GPIO_WAKEUP - { - "wowlan_gpio_info", proc_get_wowlan_gpio_info, - proc_set_wowlan_gpio_info - }, + RTW_PROC_HDL_SSEQ("wowlan_gpio_info", proc_get_wowlan_gpio_info, proc_set_wowlan_gpio_info), #endif #ifdef CONFIG_P2P_WOWLAN - {"p2p_wowlan_info", proc_get_p2p_wowlan_info, NULL}, + RTW_PROC_HDL_SSEQ("p2p_wowlan_info", proc_get_p2p_wowlan_info, NULL), +#endif + RTW_PROC_HDL_SSEQ("country_code", proc_get_country_code, proc_set_country_code), + RTW_PROC_HDL_SSEQ("chan_plan", proc_get_chan_plan, proc_set_chan_plan), +#if CONFIG_RTW_MACADDR_ACL + RTW_PROC_HDL_SSEQ("macaddr_acl", proc_get_macaddr_acl, proc_set_macaddr_acl), +#endif +#if CONFIG_RTW_PRE_LINK_STA + RTW_PROC_HDL_SSEQ("pre_link_sta", proc_get_pre_link_sta, proc_set_pre_link_sta), #endif - {"country_code", proc_get_country_code, proc_set_country_code}, - {"chan_plan", proc_get_chan_plan, proc_set_chan_plan}, #ifdef CONFIG_DFS_MASTER - {"dfs_master_test_case", proc_get_dfs_master_test_case, proc_set_dfs_master_test_case}, - {"update_non_ocp", proc_get_dummy, proc_set_update_non_ocp}, - {"radar_detect", proc_get_dummy, proc_set_radar_detect}, - {"dfs_ch_sel_d_flags", proc_get_dfs_ch_sel_d_flags, proc_set_dfs_ch_sel_d_flags}, + RTW_PROC_HDL_SSEQ("dfs_master_test_case", proc_get_dfs_master_test_case, proc_set_dfs_master_test_case), + RTW_PROC_HDL_SSEQ("update_non_ocp", NULL, proc_set_update_non_ocp), + RTW_PROC_HDL_SSEQ("radar_detect", NULL, proc_set_radar_detect), + RTW_PROC_HDL_SSEQ("dfs_ch_sel_d_flags", proc_get_dfs_ch_sel_d_flags, proc_set_dfs_ch_sel_d_flags), #endif - {"new_bcn_max", proc_get_new_bcn_max, proc_set_new_bcn_max}, - {"sink_udpport", proc_get_udpport, proc_set_udpport}, + RTW_PROC_HDL_SSEQ("new_bcn_max", proc_get_new_bcn_max, proc_set_new_bcn_max), + RTW_PROC_HDL_SSEQ("sink_udpport", proc_get_udpport, proc_set_udpport), #ifdef DBG_RX_COUNTER_DUMP - {"dump_rx_cnt_mode", proc_get_rx_cnt_dump, proc_set_rx_cnt_dump}, + RTW_PROC_HDL_SSEQ("dump_rx_cnt_mode", proc_get_rx_cnt_dump, proc_set_rx_cnt_dump), #endif - {"change_bss_chbw", NULL, proc_set_change_bss_chbw}, - {"target_tx_power", proc_get_target_tx_power, NULL}, - {"tx_power_by_rate", proc_get_tx_power_by_rate, NULL}, - {"tx_power_limit", proc_get_tx_power_limit, NULL}, - {"tx_power_ext_info", proc_get_tx_power_ext_info, proc_set_tx_power_ext_info}, + RTW_PROC_HDL_SSEQ("change_bss_chbw", NULL, proc_set_change_bss_chbw), + RTW_PROC_HDL_SSEQ("tx_bw_mode", proc_get_tx_bw_mode, proc_set_tx_bw_mode), + RTW_PROC_HDL_SSEQ("hal_txpwr_info", proc_get_hal_txpwr_info, NULL), + RTW_PROC_HDL_SSEQ("target_tx_power", proc_get_target_tx_power, NULL), + RTW_PROC_HDL_SSEQ("tx_power_by_rate", proc_get_tx_power_by_rate, NULL), +#ifdef CONFIG_TXPWR_LIMIT + RTW_PROC_HDL_SSEQ("tx_power_limit", proc_get_tx_power_limit, NULL), +#endif + RTW_PROC_HDL_SSEQ("tx_power_ext_info", proc_get_tx_power_ext_info, proc_set_tx_power_ext_info), + RTW_PROC_HDL_SEQ("tx_power_idx", &seq_ops_tx_power_idx, NULL), #ifdef CONFIG_RF_POWER_TRIM - {"tx_gain_offset", proc_get_dummy, proc_set_tx_gain_offset}, - {"kfree_flag", proc_get_kfree_flag, proc_set_kfree_flag}, - {"kfree_bb_gain", proc_get_kfree_bb_gain, proc_set_kfree_bb_gain}, - {"kfree_thermal", proc_get_kfree_thermal, proc_set_kfree_thermal}, + RTW_PROC_HDL_SSEQ("tx_gain_offset", NULL, proc_set_tx_gain_offset), + RTW_PROC_HDL_SSEQ("kfree_flag", proc_get_kfree_flag, proc_set_kfree_flag), + RTW_PROC_HDL_SSEQ("kfree_bb_gain", proc_get_kfree_bb_gain, proc_set_kfree_bb_gain), + RTW_PROC_HDL_SSEQ("kfree_thermal", proc_get_kfree_thermal, proc_set_kfree_thermal), #endif #ifdef CONFIG_POWER_SAVING - {"ps_info", proc_get_ps_info, NULL}, + RTW_PROC_HDL_SSEQ("ps_info", proc_get_ps_info, NULL), #endif #ifdef CONFIG_TDLS - {"tdls_info", proc_get_tdls_info, NULL}, + RTW_PROC_HDL_SSEQ("tdls_info", proc_get_tdls_info, NULL), #endif - {"monitor", proc_get_monitor, proc_set_monitor}, + RTW_PROC_HDL_SSEQ("monitor", proc_get_monitor, proc_set_monitor), #ifdef CONFIG_AUTO_CHNL_SEL_NHM - {"acs", proc_get_best_chan, proc_set_acs}, + RTW_PROC_HDL_SSEQ("acs", proc_get_best_chan, proc_set_acs), #endif #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER - {"rtkm_info", proc_get_rtkm_info, NULL}, + RTW_PROC_HDL_SSEQ("rtkm_info", proc_get_rtkm_info, NULL), #endif - {"efuse_map", proc_get_efuse_map, NULL}, + RTW_PROC_HDL_SSEQ("efuse_map", proc_get_efuse_map, NULL), #ifdef CONFIG_IEEE80211W - {"11w_tx_sa_query", proc_get_tx_sa_query, proc_set_tx_sa_query}, - {"11w_tx_deauth", proc_get_tx_deauth, proc_set_tx_deauth}, - {"11w_tx_auth", proc_get_tx_auth, proc_set_tx_auth}, + RTW_PROC_HDL_SSEQ("11w_tx_sa_query", proc_get_tx_sa_query, proc_set_tx_sa_query), + RTW_PROC_HDL_SSEQ("11w_tx_deauth", proc_get_tx_deauth, proc_set_tx_deauth), + RTW_PROC_HDL_SSEQ("11w_tx_auth", proc_get_tx_auth, proc_set_tx_auth), #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_MBSSID_CAM - {"mbid_cam", proc_get_mbid_cam_cache, NULL}, + RTW_PROC_HDL_SSEQ("mbid_cam", proc_get_mbid_cam_cache, NULL), +#endif + RTW_PROC_HDL_SSEQ("mac_addr", proc_get_mac_addr, NULL), + RTW_PROC_HDL_SSEQ("skip_band", proc_get_skip_band, proc_set_skip_band), + RTW_PROC_HDL_SSEQ("hal_spec", proc_get_hal_spec, NULL), + + RTW_PROC_HDL_SSEQ("rx_stat", proc_get_rx_stat, NULL), + + RTW_PROC_HDL_SSEQ("tx_stat", proc_get_tx_stat, NULL), + /**** PHY Capability ****/ + RTW_PROC_HDL_SSEQ("phy_cap", proc_get_phy_cap, NULL), + + RTW_PROC_HDL_SSEQ("rx_stbc", proc_get_rx_stbc, proc_set_rx_stbc), + RTW_PROC_HDL_SSEQ("stbc_cap", proc_get_stbc_cap, proc_set_stbc_cap), + RTW_PROC_HDL_SSEQ("ldpc_cap", proc_get_ldpc_cap, proc_set_ldpc_cap), +#ifdef CONFIG_BEAMFORMING + RTW_PROC_HDL_SSEQ("txbf_cap", proc_get_txbf_cap, proc_set_txbf_cap), #endif - {"mac_addr", proc_get_mac_addr, NULL}, - {"skip_band", proc_get_skip_band, proc_set_skip_band}, - {"hal_spec", proc_get_hal_spec, NULL}, -#ifdef CONFIG_NAPI - {"napi", proc_get_napi, proc_set_napi}, + +#ifdef CONFIG_SUPPORT_TRX_SHARED + RTW_PROC_HDL_SSEQ("trx_share_mode", proc_get_trx_share_mode, NULL), +#endif + RTW_PROC_HDL_SSEQ("napi_info", proc_get_napi_info, NULL), + RTW_PROC_HDL_SSEQ("rsvd_page", proc_dump_rsvd_page, proc_set_rsvd_page_info), + +#ifdef CONFIG_SUPPORT_FIFO_DUMP + RTW_PROC_HDL_SSEQ("fifo_dump", proc_dump_fifo, proc_set_fifo_info), +#endif + RTW_PROC_HDL_SSEQ("fw_info", proc_get_fw_info, NULL), +#ifdef RTW_HALMAC + RTW_PROC_HDL_SSEQ("halmac_info", proc_get_halmac_info, NULL), #endif + +#ifdef DBG_XMIT_BLOCK + RTW_PROC_HDL_SSEQ("xmit_block", proc_get_xmit_block, proc_set_xmit_block), +#endif + + RTW_PROC_HDL_SSEQ("ack_timeout", proc_get_ack_timeout, proc_set_ack_timeout), + + RTW_PROC_HDL_SSEQ("dynamic_agg_enable", proc_get_dynamic_agg_enable, proc_set_dynamic_agg_enable), + RTW_PROC_HDL_SSEQ("iqk_fw_offload", proc_get_iqk_fw_offload, proc_set_iqk_fw_offload), + }; const int adapter_proc_hdls_num = sizeof(adapter_proc_hdls) / sizeof(struct rtw_proc_hdl); -static int rtw_adapter_proc_open(struct inode *inode, struct file *file) { +static int rtw_adapter_proc_open(struct inode *inode, struct file *file) +{ ssize_t index = (ssize_t)PDE_DATA(inode); const struct rtw_proc_hdl *hdl = adapter_proc_hdls + index; + void *private = proc_get_parent_data(inode); + + if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) { + int res = seq_open(file, hdl->u.seq_op); + + if (res == 0) + ((struct seq_file *)file->private_data)->private = private; + + return res; + } else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) { + int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy; - return single_open(file, hdl->show, proc_get_parent_data(inode)); + return single_open(file, show, private); + } else { + return -EROFS; + } } -static ssize_t rtw_adapter_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) { +static ssize_t rtw_adapter_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) +{ ssize_t index = (ssize_t)PDE_DATA(file_inode(file)); const struct rtw_proc_hdl *hdl = adapter_proc_hdls + index; ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write; @@ -1859,127 +2862,27 @@ static ssize_t rtw_adapter_proc_write(struct file *file, const char __user *buff return -EROFS; } -static const struct file_operations rtw_adapter_proc_fops = { +static const struct file_operations rtw_adapter_proc_seq_fops = { .owner = THIS_MODULE, .open = rtw_adapter_proc_open, .read = seq_read, .llseek = seq_lseek, - .release = single_release, + .release = seq_release, .write = rtw_adapter_proc_write, }; -int proc_get_odm_dbg_comp(struct seq_file *m, void *v) { - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - rtw_odm_dbg_comp_msg(m, adapter); - - return 0; -} - -ssize_t proc_set_odm_dbg_comp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - - u64 dbg_comp; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%llx", &dbg_comp); - - if (num != 1) - return count; - - rtw_odm_dbg_comp_set(adapter, dbg_comp); - } - - return count; -} - -int proc_get_odm_dbg_level(struct seq_file *m, void *v) { - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - rtw_odm_dbg_level_msg(m, adapter); - - return 0; -} - -ssize_t proc_set_odm_dbg_level(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - - u32 dbg_level; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%u", &dbg_level); - - if (num != 1) - return count; - - rtw_odm_dbg_level_set(adapter, dbg_level); - } - - return count; -} - -int proc_get_odm_ability(struct seq_file *m, void *v) { - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - rtw_odm_ability_msg(m, adapter); - - return 0; -} - -ssize_t proc_set_odm_ability(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - - u32 ability; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%x", &ability); - - if (num != 1) - return count; - - rtw_odm_ability_set(adapter, ability); - } +static const struct file_operations rtw_adapter_proc_sseq_fops = { + .owner = THIS_MODULE, + .open = rtw_adapter_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = rtw_adapter_proc_write, +}; - return count; -} -int proc_get_odm_force_igi_lb(struct seq_file *m, void *v) { +int proc_get_odm_force_igi_lb(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -1988,7 +2891,8 @@ int proc_get_odm_force_igi_lb(struct seq_file *m, void *v) { return 0; } -ssize_t proc_set_odm_force_igi_lb(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +ssize_t proc_set_odm_force_igi_lb(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; @@ -2015,7 +2919,8 @@ ssize_t proc_set_odm_force_igi_lb(struct file *file, const char __user *buffer, return count; } -int proc_get_odm_adaptivity(struct seq_file *m, void *v) { +int proc_get_odm_adaptivity(struct seq_file *m, void *v) +{ struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -2024,15 +2929,16 @@ int proc_get_odm_adaptivity(struct seq_file *m, void *v) { return 0; } -ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; - u32 TH_L2H_ini; - u32 TH_L2H_ini_mode2; - s8 TH_EDCCA_HL_diff; - s8 TH_EDCCA_HL_diff_mode2; - u8 EDCCA_enable; + u32 th_l2h_ini; + u32 th_l2h_ini_mode2; + s8 th_edcca_hl_diff; + s8 th_edcca_hl_diff_mode2; + u8 edcca_enable; if (count < 1) return -EFAULT; @@ -2044,12 +2950,12 @@ ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, si if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%x %hhd %x %hhd %hhu", &TH_L2H_ini, &TH_EDCCA_HL_diff, &TH_L2H_ini_mode2, &TH_EDCCA_HL_diff_mode2, &EDCCA_enable); + int num = sscanf(tmp, "%x %hhd %x %hhd %hhu", &th_l2h_ini, &th_edcca_hl_diff, &th_l2h_ini_mode2, &th_edcca_hl_diff_mode2, &edcca_enable); if (num != 5) return count; - rtw_odm_adaptivity_parm_set(padapter, (s8)TH_L2H_ini, TH_EDCCA_HL_diff, (s8)TH_L2H_ini_mode2, TH_EDCCA_HL_diff_mode2, EDCCA_enable); + rtw_odm_adaptivity_parm_set(padapter, (s8)th_l2h_ini, th_edcca_hl_diff, (s8)th_l2h_ini_mode2, th_edcca_hl_diff_mode2, edcca_enable); } return count; @@ -2058,11 +2964,12 @@ ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, si static char *phydm_msg = NULL; #define PHYDM_MSG_LEN 80*24 -int proc_get_phydm_cmd(struct seq_file *m, void *v) { +int proc_get_phydm_cmd(struct seq_file *m, void *v) +{ struct net_device *netdev; PADAPTER padapter; PHAL_DATA_TYPE pHalData; - PDM_ODM_T phydm; + struct PHY_DM_STRUCT *phydm; netdev = m->private; @@ -2086,11 +2993,12 @@ int proc_get_phydm_cmd(struct seq_file *m, void *v) { return 0; } -ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ struct net_device *netdev; PADAPTER padapter; PHAL_DATA_TYPE pHalData; - PDM_ODM_T phydm; + struct PHY_DM_STRUCT *phydm; char tmp[64] = {0}; @@ -2124,29 +3032,125 @@ ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t return count; } +#ifdef CONFIG_LAMODE +static void *proc_start_lamode_dump(struct seq_file *m, loff_t *pos) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(m->private); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); + static unsigned long index; + static unsigned long max; + + + if (*pos == 0) { + rtw_pm_set_ips(adapter, IPS_NONE); + rtw_pm_set_lps(adapter, PS_MODE_ACTIVE); + ADCSmp_Start(pDM_Odm, AdcSmp); + index = 0; + *pos = max = ADCSmp_Get_SampleCounts(pDM_Odm); + if (max == 0) + return NULL; + } else if (index >= max) { + return NULL; + } + + return &index; +} + +static void proc_stop_lamode_dump(struct seq_file *m, void *v) +{ + /* v is a NULL in kernel 3.19.0-25 */ +} + +static void *proc_next_lamode_dump(struct seq_file *m, void *v, loff_t *pos) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(m->private); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + unsigned long *index = v; + + + *index += 2; + if (*index >= *pos) { + ADCSmp_DeInit(pDM_Odm); + if (phydm_msg) { + _RTW_PRINT_SEL(m, "%s", phydm_msg); + rtw_mfree(phydm_msg, PHYDM_MSG_LEN); + phydm_msg = NULL; + } + return NULL; + } + return index; +} + +static int proc_show_lamode_data(struct seq_file *m, void *v) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(m->private); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + unsigned long *index = v; + char line[32]; + int rtn; + + + memset(line, 0, sizeof(line)); + rtn = ADCSmp_Query_SingleData(pDM_Odm, line, sizeof(line), *index); + _RTW_PRINT_SEL(m, "%s", line); + + if (rtn<0) + return -1; + + return 0; +} + +static struct seq_operations seq_ops_lamode = { + .start = proc_start_lamode_dump, + .stop = proc_stop_lamode_dump, + .next = proc_next_lamode_dump, + .show = proc_show_lamode_data, +}; +#endif /* CONFIG_LAMODE */ + /* * rtw_odm_proc: * init/deinit when register/unregister net_device, along with rtw_adapter_proc */ const struct rtw_proc_hdl odm_proc_hdls[] = { - {"dbg_comp", proc_get_odm_dbg_comp, proc_set_odm_dbg_comp}, - {"dbg_level", proc_get_odm_dbg_level, proc_set_odm_dbg_level}, - {"ability", proc_get_odm_ability, proc_set_odm_ability}, - {"adaptivity", proc_get_odm_adaptivity, proc_set_odm_adaptivity}, - {"force_igi_lb", proc_get_odm_force_igi_lb, proc_set_odm_force_igi_lb}, - {"cmd", proc_get_phydm_cmd, proc_set_phydm_cmd}, + RTW_PROC_HDL_SSEQ("adaptivity", proc_get_odm_adaptivity, proc_set_odm_adaptivity), + RTW_PROC_HDL_SSEQ("force_igi_lb", proc_get_odm_force_igi_lb, proc_set_odm_force_igi_lb), + RTW_PROC_HDL_SSEQ("cmd", proc_get_phydm_cmd, proc_set_phydm_cmd), +#ifdef CONFIG_LAMODE + RTW_PROC_HDL_SEQ("lamode", &seq_ops_lamode, proc_set_phydm_cmd) +#endif /* CONFIG_LAMODE */ }; const int odm_proc_hdls_num = sizeof(odm_proc_hdls) / sizeof(struct rtw_proc_hdl); -static int rtw_odm_proc_open(struct inode *inode, struct file *file) { +static int rtw_odm_proc_open(struct inode *inode, struct file *file) +{ ssize_t index = (ssize_t)PDE_DATA(inode); const struct rtw_proc_hdl *hdl = odm_proc_hdls + index; + void *private = proc_get_parent_data(inode); + + if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) { + int res = seq_open(file, hdl->u.seq_op); + + if (res == 0) + ((struct seq_file *)file->private_data)->private = private; - return single_open(file, hdl->show, proc_get_parent_data(inode)); + return res; + } else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) { + int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy; + + return single_open(file, show, private); + } else { + return -EROFS; + } } -static ssize_t rtw_odm_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) { +static ssize_t rtw_odm_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) +{ ssize_t index = (ssize_t)PDE_DATA(file_inode(file)); const struct rtw_proc_hdl *hdl = odm_proc_hdls + index; ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write; @@ -2157,7 +3161,16 @@ static ssize_t rtw_odm_proc_write(struct file *file, const char __user *buffer, return -EROFS; } -static const struct file_operations rtw_odm_proc_fops = { +static const struct file_operations rtw_odm_proc_seq_fops = { + .owner = THIS_MODULE, + .open = rtw_odm_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, + .write = rtw_odm_proc_write, +}; + +static const struct file_operations rtw_odm_proc_sseq_fops = { .owner = THIS_MODULE, .open = rtw_odm_proc_open, .read = seq_read, @@ -2166,7 +3179,8 @@ static const struct file_operations rtw_odm_proc_fops = { .write = rtw_odm_proc_write, }; -struct proc_dir_entry *rtw_odm_proc_init(struct net_device *dev) { +struct proc_dir_entry *rtw_odm_proc_init(struct net_device *dev) +{ struct proc_dir_entry *dir_odm = NULL; struct proc_dir_entry *entry = NULL; _adapter *adapter = rtw_netdev_priv(dev); @@ -2191,7 +3205,13 @@ struct proc_dir_entry *rtw_odm_proc_init(struct net_device *dev) { adapter->dir_odm = dir_odm; for (i = 0; i < odm_proc_hdls_num; i++) { - entry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_fops, (void *)i); + if (odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ) + entry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_seq_fops, (void *)i); + else if (odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ) + entry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_sseq_fops, (void *)i); + else + entry = NULL; + if (!entry) { rtw_warn_on(1); goto exit; @@ -2202,7 +3222,8 @@ struct proc_dir_entry *rtw_odm_proc_init(struct net_device *dev) { return dir_odm; } -void rtw_odm_proc_deinit(_adapter *adapter) { +void rtw_odm_proc_deinit(_adapter *adapter) +{ struct proc_dir_entry *dir_odm = NULL; int i; @@ -2232,27 +3253,44 @@ void rtw_odm_proc_deinit(_adapter *adapter) { * init/deinit when register/unregister net_device, along with rtw_adapter_proc */ const struct rtw_proc_hdl mcc_proc_hdls[] = { - {"mcc_info", proc_get_mcc_info, NULL}, - {"mcc_enable", proc_get_mcc_info, proc_set_mcc_enable}, - {"mcc_single_tx_criteria", proc_get_mcc_info, proc_set_mcc_single_tx_criteria}, - {"mcc_ap_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw20_target_tp}, - {"mcc_ap_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw40_target_tp}, - {"mcc_ap_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw80_target_tp}, - {"mcc_sta_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw20_target_tp}, - {"mcc_sta_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw40_target_tp}, - {"mcc_sta_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw80_target_tp}, + RTW_PROC_HDL_SSEQ("mcc_info", proc_get_mcc_info, NULL), + RTW_PROC_HDL_SSEQ("mcc_enable", proc_get_mcc_info, proc_set_mcc_enable), + RTW_PROC_HDL_SSEQ("mcc_single_tx_criteria", proc_get_mcc_info, proc_set_mcc_single_tx_criteria), + RTW_PROC_HDL_SSEQ("mcc_ap_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw20_target_tp), + RTW_PROC_HDL_SSEQ("mcc_ap_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw40_target_tp), + RTW_PROC_HDL_SSEQ("mcc_ap_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw80_target_tp), + RTW_PROC_HDL_SSEQ("mcc_sta_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw20_target_tp), + RTW_PROC_HDL_SSEQ("mcc_sta_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw40_target_tp), + RTW_PROC_HDL_SSEQ("mcc_sta_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw80_target_tp), + RTW_PROC_HDL_SSEQ("mcc_policy_table", proc_get_mcc_policy_table, proc_set_mcc_policy_table), }; const int mcc_proc_hdls_num = sizeof(mcc_proc_hdls) / sizeof(struct rtw_proc_hdl); -static int rtw_mcc_proc_open(struct inode *inode, struct file *file) { +static int rtw_mcc_proc_open(struct inode *inode, struct file *file) +{ ssize_t index = (ssize_t)PDE_DATA(inode); const struct rtw_proc_hdl *hdl = mcc_proc_hdls + index; + void *private = proc_get_parent_data(inode); - return single_open(file, hdl->show, proc_get_parent_data(inode)); + if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) { + int res = seq_open(file, hdl->u.seq_op); + + if (res == 0) + ((struct seq_file *)file->private_data)->private = private; + + return res; + } else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) { + int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy; + + return single_open(file, show, private); + } else { + return -EROFS; + } } -static ssize_t rtw_mcc_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) { +static ssize_t rtw_mcc_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) +{ ssize_t index = (ssize_t)PDE_DATA(file_inode(file)); const struct rtw_proc_hdl *hdl = mcc_proc_hdls + index; ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write; @@ -2263,7 +3301,16 @@ static ssize_t rtw_mcc_proc_write(struct file *file, const char __user *buffer, return -EROFS; } -static const struct file_operations rtw_mcc_proc_fops = { +static const struct file_operations rtw_mcc_proc_seq_fops = { + .owner = THIS_MODULE, + .open = rtw_mcc_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, + .write = rtw_mcc_proc_write, +}; + +static const struct file_operations rtw_mcc_proc_sseq_fops = { .owner = THIS_MODULE, .open = rtw_mcc_proc_open, .read = seq_read, @@ -2272,7 +3319,8 @@ static const struct file_operations rtw_mcc_proc_fops = { .write = rtw_mcc_proc_write, }; -struct proc_dir_entry *rtw_mcc_proc_init(struct net_device *dev) { +struct proc_dir_entry *rtw_mcc_proc_init(struct net_device *dev) +{ struct proc_dir_entry *dir_mcc = NULL; struct proc_dir_entry *entry = NULL; _adapter *adapter = rtw_netdev_priv(dev); @@ -2297,7 +3345,13 @@ struct proc_dir_entry *rtw_mcc_proc_init(struct net_device *dev) { adapter->dir_mcc = dir_mcc; for (i = 0; i < mcc_proc_hdls_num; i++) { - entry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_fops, (void *)i); + if (mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ) + entry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_seq_fops, (void *)i); + else if (mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ) + entry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_sseq_fops, (void *)i); + else + entry = NULL; + if (!entry) { rtw_warn_on(1); goto exit; @@ -2308,7 +3362,8 @@ struct proc_dir_entry *rtw_mcc_proc_init(struct net_device *dev) { return dir_mcc; } -void rtw_mcc_proc_deinit(_adapter *adapter) { +void rtw_mcc_proc_deinit(_adapter *adapter) +{ struct proc_dir_entry *dir_mcc = NULL; int i; @@ -2328,7 +3383,8 @@ void rtw_mcc_proc_deinit(_adapter *adapter) { } #endif /* CONFIG_MCC_MODE */ -struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev) { +struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev) +{ struct proc_dir_entry *drv_proc = get_rtw_drv_proc(); struct proc_dir_entry *dir_dev = NULL; struct proc_dir_entry *entry = NULL; @@ -2355,7 +3411,13 @@ struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev) { adapter->dir_dev = dir_dev; for (i = 0; i < adapter_proc_hdls_num; i++) { - entry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_fops, (void *)i); + if (adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ) + entry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_seq_fops, (void *)i); + else if (adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ) + entry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_sseq_fops, (void *)i); + else + entry = NULL; + if (!entry) { rtw_warn_on(1); goto exit; @@ -2372,7 +3434,8 @@ struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev) { return dir_dev; } -void rtw_adapter_proc_deinit(struct net_device *dev) { +void rtw_adapter_proc_deinit(struct net_device *dev) +{ struct proc_dir_entry *drv_proc = get_rtw_drv_proc(); struct proc_dir_entry *dir_dev = NULL; _adapter *adapter = rtw_netdev_priv(dev); @@ -2399,7 +3462,8 @@ void rtw_adapter_proc_deinit(struct net_device *dev) { adapter->dir_dev = NULL; } -void rtw_adapter_proc_replace(struct net_device *dev) { +void rtw_adapter_proc_replace(struct net_device *dev) +{ struct proc_dir_entry *drv_proc = get_rtw_drv_proc(); struct proc_dir_entry *dir_dev = NULL; _adapter *adapter = rtw_netdev_priv(dev); diff --git a/os_dep/linux/rtw_proc.h b/os_dep/linux/rtw_proc.h index 8d7c758..c2c7c8e 100644 --- a/os_dep/linux/rtw_proc.h +++ b/os_dep/linux/rtw_proc.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,41 +11,49 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_PROC_H__ #define __RTW_PROC_H__ #include #include +#define RTW_PROC_HDL_TYPE_SEQ 0 +#define RTW_PROC_HDL_TYPE_SSEQ 1 + struct rtw_proc_hdl { char *name; - int (*show)(struct seq_file *, void *); + u8 type; + union { + int (*show)(struct seq_file *, void *); + struct seq_operations *seq_op; + } u; ssize_t (*write)(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); }; +#define RTW_PROC_HDL_SEQ(_name, _seq_op, _write) \ + { .name = _name, .type = RTW_PROC_HDL_TYPE_SEQ, .u.seq_op = _seq_op, .write = _write} + +#define RTW_PROC_HDL_SSEQ(_name, _show, _write) \ + { .name = _name, .type = RTW_PROC_HDL_TYPE_SSEQ, .u.show = _show, .write = _write} + #ifdef CONFIG_PROC_DEBUG - struct proc_dir_entry *get_rtw_drv_proc(void); - int rtw_drv_proc_init(void); - void rtw_drv_proc_deinit(void); - struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev); - void rtw_adapter_proc_deinit(struct net_device *dev); - void rtw_adapter_proc_replace(struct net_device *dev); +struct proc_dir_entry *get_rtw_drv_proc(void); +int rtw_drv_proc_init(void); +void rtw_drv_proc_deinit(void); +struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev); +void rtw_adapter_proc_deinit(struct net_device *dev); +void rtw_adapter_proc_replace(struct net_device *dev); #else /* !CONFIG_PROC_DEBUG */ - #define get_rtw_drv_proc() NULL - #define rtw_drv_proc_init() 0 - #define rtw_drv_proc_deinit() do {} while (0) - #define rtw_adapter_proc_init(dev) NULL - #define rtw_adapter_proc_deinit(dev) do {} while (0) - #define rtw_adapter_proc_replace(dev) do {} while (0) +#define get_rtw_drv_proc() NULL +#define rtw_drv_proc_init() 0 +#define rtw_drv_proc_deinit() do {} while (0) +#define rtw_adapter_proc_init(dev) NULL +#define rtw_adapter_proc_deinit(dev) do {} while (0) +#define rtw_adapter_proc_replace(dev) do {} while (0) #endif /* !CONFIG_PROC_DEBUG */ diff --git a/os_dep/linux/usb_intf.c b/os_dep/linux/usb_intf.c index 5f66e34..e8166a3 100644 --- a/os_dep/linux/usb_intf.c +++ b/os_dep/linux/usb_intf.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HCI_INTF_C_ #include @@ -24,10 +19,6 @@ #include -#ifdef CONFIG_RTL8821C -#include /* rtl8821cu_set_hal_ops() */ -#endif /* CONFIG_RTL8821C */ - #ifndef CONFIG_USB_HCI #error "CONFIG_USB_HCI shall be on!\n" #endif @@ -55,7 +46,8 @@ static int rtw_resume(struct usb_interface *intf); static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device_id *pdid); static void rtw_dev_remove(struct usb_interface *pusb_intf); -static void rtw_dev_shutdown(struct device *dev) { +static void rtw_dev_shutdown(struct device *dev) +{ struct usb_interface *usb_intf = container_of(dev, struct usb_interface, dev); struct dvobj_priv *dvobj = NULL; _adapter *adapter = NULL; @@ -66,7 +58,27 @@ static void rtw_dev_shutdown(struct device *dev) { if (usb_intf) { dvobj = usb_get_intfdata(usb_intf); if (dvobj) { - rtw_set_surprise_removed(dvobj->padapters[IFACE_ID0]); + adapter = dvobj_get_primary_adapter(dvobj); + if (adapter) { + if (!rtw_is_surprise_removed(adapter)) { + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + #ifdef CONFIG_WOWLAN + #ifdef CONFIG_GPIO_WAKEUP + /*default wake up pin change to BT*/ + RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__); + rtw_hal_switch_gpio_wl_ctrl(adapter, WAKEUP_GPIO_IDX, _FALSE); + #endif /* CONFIG_GPIO_WAKEUP */ + + if (pwrctl->wowlan_mode == _TRUE) + RTW_PRINT("%s wowlan_mode ==_TRUE do not run rtw_hal_deinit()\n", __FUNCTION__); + else + #endif + { + rtw_hal_deinit(adapter); + rtw_set_surprise_removed(adapter); + } + } + } ATOMIC_SET(&dvobj->continual_io_error, MAX_CONTINUAL_IO_ERR + 1); } } @@ -127,6 +139,7 @@ static void rtw_dev_shutdown(struct device *dev) { #endif +#define USB_VENDER_ID_EDIMAX 0x7392 //EDX #define USB_VENDER_ID_REALTEK 0x0BDA @@ -220,10 +233,12 @@ static struct usb_device_id rtw_usb_id_tbl[] = { #ifdef CONFIG_RTL8822B /*=== Realtek demoboard ===*/ + /*=== Realtek demoboard ===*/ {USB_DEVICE(0x0BDA, 0xB812), .driver_info = RTL8822B}, {USB_DEVICE(0x0B05, 0x1812), .driver_info = RTL8812}, /* ASUS - Edimax */ {USB_DEVICE(0x7392, 0xB822), .driver_info = RTL8822B}, /* Edimax - EW-7822ULC */ {USB_DEVICE(0x0b05, 0x184c), .driver_info = RTL8822B}, /* ASUS USB AC53 */ + {USB_DEVICE(0x7392, 0xC822), .driver_info = RTL8822B}, /* Edimax - EW-7822UTC */ {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB82C, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Default ID */ #endif /* CONFIG_RTL8822B */ @@ -236,6 +251,10 @@ static struct usb_device_id rtw_usb_id_tbl[] = { /*=== Realtek demoboard ===*/ {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xb82b, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xb820, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC821, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC820, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC82A, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC82B, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ /*=== Customer ID ===*/ #endif @@ -286,39 +305,48 @@ struct rtw_usb_drv usb_drv = { #endif }; -static inline int RT_usb_endpoint_dir_in(const struct usb_endpoint_descriptor *epd) { +static inline int RT_usb_endpoint_dir_in(const struct usb_endpoint_descriptor *epd) +{ return (epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN; } -static inline int RT_usb_endpoint_dir_out(const struct usb_endpoint_descriptor *epd) { +static inline int RT_usb_endpoint_dir_out(const struct usb_endpoint_descriptor *epd) +{ return (epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT; } -static inline int RT_usb_endpoint_xfer_int(const struct usb_endpoint_descriptor *epd) { +static inline int RT_usb_endpoint_xfer_int(const struct usb_endpoint_descriptor *epd) +{ return (epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT; } -static inline int RT_usb_endpoint_xfer_bulk(const struct usb_endpoint_descriptor *epd) { +static inline int RT_usb_endpoint_xfer_bulk(const struct usb_endpoint_descriptor *epd) +{ return (epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK; } -static inline int RT_usb_endpoint_is_bulk_in(const struct usb_endpoint_descriptor *epd) { +static inline int RT_usb_endpoint_is_bulk_in(const struct usb_endpoint_descriptor *epd) +{ return RT_usb_endpoint_xfer_bulk(epd) && RT_usb_endpoint_dir_in(epd); } -static inline int RT_usb_endpoint_is_bulk_out(const struct usb_endpoint_descriptor *epd) { +static inline int RT_usb_endpoint_is_bulk_out(const struct usb_endpoint_descriptor *epd) +{ return RT_usb_endpoint_xfer_bulk(epd) && RT_usb_endpoint_dir_out(epd); } -static inline int RT_usb_endpoint_is_int_in(const struct usb_endpoint_descriptor *epd) { +static inline int RT_usb_endpoint_is_int_in(const struct usb_endpoint_descriptor *epd) +{ return RT_usb_endpoint_xfer_int(epd) && RT_usb_endpoint_dir_in(epd); } -static inline int RT_usb_endpoint_num(const struct usb_endpoint_descriptor *epd) { +static inline int RT_usb_endpoint_num(const struct usb_endpoint_descriptor *epd) +{ return epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; } -static u8 rtw_init_intf_priv(struct dvobj_priv *dvobj) { +static u8 rtw_init_intf_priv(struct dvobj_priv *dvobj) +{ u8 rst = _SUCCESS; #ifdef CONFIG_USB_VENDOR_REQ_MUTEX @@ -334,7 +362,7 @@ static u8 rtw_init_intf_priv(struct dvobj_priv *dvobj) { goto exit; } dvobj->usb_vendor_req_buf = - (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(dvobj->usb_alloc_vendor_req_buf), ALIGNMENT_UNIT); + (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(dvobj->usb_alloc_vendor_req_buf), ALIGNMENT_UNIT); exit: #endif @@ -342,7 +370,8 @@ static u8 rtw_init_intf_priv(struct dvobj_priv *dvobj) { } -static u8 rtw_deinit_intf_priv(struct dvobj_priv *dvobj) { +static u8 rtw_deinit_intf_priv(struct dvobj_priv *dvobj) +{ u8 rst = _SUCCESS; #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC @@ -356,7 +385,8 @@ static u8 rtw_deinit_intf_priv(struct dvobj_priv *dvobj) { return rst; } -static void rtw_decide_chip_type_by_usb_info(struct dvobj_priv *pdvobjpriv, const struct usb_device_id *pdid) { +static void rtw_decide_chip_type_by_usb_info(struct dvobj_priv *pdvobjpriv, const struct usb_device_id *pdid) +{ pdvobjpriv->chip_type = pdid->driver_info; #ifdef CONFIG_RTL8188E @@ -410,7 +440,8 @@ static void rtw_decide_chip_type_by_usb_info(struct dvobj_priv *pdvobjpriv, cons #endif /* CONFIG_RTL8821C */ } -static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf, const struct usb_device_id *pdid) { +static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf, const struct usb_device_id *pdid) +{ int i; u8 val8; int status = _FAIL; @@ -424,7 +455,6 @@ static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf, const s struct usb_endpoint_descriptor *pendp_desc; struct usb_device *pusbd; - _func_enter_; pdvobjpriv = devobj_init(); @@ -566,7 +596,6 @@ static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf, const s } if (rtw_init_intf_priv(pdvobjpriv) == _FAIL) { - RT_TRACE(_module_os_intfs_c_, _drv_err_, ("\n Can't INIT rtw_init_intf_priv\n")); goto free_dvobj; } @@ -591,20 +620,19 @@ static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf, const s pdvobjpriv = NULL; } exit: - _func_exit_; return pdvobjpriv; } -static void usb_dvobj_deinit(struct usb_interface *usb_intf) { +static void usb_dvobj_deinit(struct usb_interface *usb_intf) +{ struct dvobj_priv *dvobj = usb_get_intfdata(usb_intf); - _func_enter_; usb_set_intfdata(usb_intf, NULL); if (dvobj) { /* Modify condition for 92DU DMDP 2010.11.18, by Thomas */ if ((dvobj->NumInterfaces != 2 && dvobj->NumInterfaces != 3) - || (dvobj->InterfaceNumber == 1)) { + || (dvobj->InterfaceNumber == 1)) { if (interface_to_usbdev(usb_intf)->state != USB_STATE_NOTATTACHED) { /* If we didn't unplug usb dongle and remove/insert modlue, driver fails on sitesurvey for the first time when device is up . */ /* Reset usb port for sitesurvey fail issue. 2009.8.13, by Thomas */ @@ -621,10 +649,10 @@ static void usb_dvobj_deinit(struct usb_interface *usb_intf) { /* RTW_INFO("%s %d\n", __func__, ATOMIC_READ(&usb_intf->dev.kobj.kref.refcount)); */ usb_put_dev(interface_to_usbdev(usb_intf)); - _func_exit_; } -static int usb_reprobe_switch_usb_mode(PADAPTER Adapter) { +static int usb_reprobe_switch_usb_mode(PADAPTER Adapter) +{ struct registry_priv *registry_par = &Adapter->registrypriv; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); u8 ret = _FALSE; @@ -643,7 +671,8 @@ static int usb_reprobe_switch_usb_mode(PADAPTER Adapter) { return ret; } -u8 rtw_set_hal_ops(_adapter *padapter) { +u8 rtw_set_hal_ops(_adapter *padapter) +{ /* alloc memory for HAL DATA */ if (rtw_hal_data_init(padapter) == _FAIL) return _FAIL; @@ -693,8 +722,10 @@ u8 rtw_set_hal_ops(_adapter *padapter) { #ifdef CONFIG_RTL8821C - if (rtw_get_chip_type(padapter) == RTL8821C) - rtl8821cu_set_hal_ops(padapter); + if (rtw_get_chip_type(padapter) == RTL8821C) { + if (rtl8821cu_set_hal_ops(padapter) == _FAIL) + return _FAIL; + } #endif if (_FAIL == rtw_hal_ops_check(padapter)) @@ -706,25 +737,24 @@ u8 rtw_set_hal_ops(_adapter *padapter) { return _SUCCESS; } -static void usb_intf_start(_adapter *padapter) { - - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+usb_intf_start\n")); +static void usb_intf_start(_adapter *padapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); rtw_hal_inirp_init(padapter); + hal->usb_intf_start = _TRUE; - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("-usb_intf_start\n")); } -static void usb_intf_stop(_adapter *padapter) { - - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+usb_intf_stop\n")); +static void usb_intf_stop(_adapter *padapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); /* disabel_hw_interrupt */ if (!rtw_is_surprise_removed(padapter)) { /* device still exists, so driver can do i/o operation */ /* TODO: */ - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("SurpriseRemoved==_FALSE\n")); } /* cancel in irp */ @@ -735,11 +765,12 @@ static void usb_intf_stop(_adapter *padapter) { /* todo:cancel other irps */ - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("-usb_intf_stop\n")); + hal->usb_intf_start = _FALSE; } -static void process_spec_devid(const struct usb_device_id *pdid) { +static void process_spec_devid(const struct usb_device_id *pdid) +{ u16 vid, pid; u32 flags; int i; @@ -772,20 +803,20 @@ static void process_spec_devid(const struct usb_device_id *pdid) { } #ifdef SUPPORT_HW_RFOFF_DETECTED -int rtw_hw_suspend(_adapter *padapter) { +int rtw_hw_suspend(_adapter *padapter) +{ struct pwrctrl_priv *pwrpriv; struct usb_interface *pusb_intf; struct net_device *pnetdev; - _func_enter_; if (NULL == padapter) goto error_exit; if ((_FALSE == padapter->bup) || RTW_CANNOT_RUN(padapter)) { RTW_INFO("padapter->bup=%d bDriverStopped=%s bSurpriseRemoved = %s\n" - , padapter->bup - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); + , padapter->bup + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False"); goto error_exit; } @@ -806,7 +837,7 @@ int rtw_hw_suspend(_adapter *padapter) { } /* s2. */ - rtw_disassoc_cmd(padapter, 500, _FALSE); + rtw_disassoc_cmd(padapter, 500, RTW_CMDF_DIRECTLY); /* s2-2. indicate disconnect to os */ /* rtw_indicate_disconnect(padapter); */ @@ -836,7 +867,6 @@ int rtw_hw_suspend(_adapter *padapter) { pwrpriv->bips_processing = _FALSE; _exit_pwrlock(&pwrpriv->lock); - _func_exit_; return 0; error_exit: @@ -845,12 +875,12 @@ int rtw_hw_suspend(_adapter *padapter) { } -int rtw_hw_resume(_adapter *padapter) { +int rtw_hw_resume(_adapter *padapter) +{ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct usb_interface *pusb_intf = adapter_to_dvobj(padapter)->pusbintf; struct net_device *pnetdev = padapter->pnetdev; - _func_enter_; RTW_INFO("==> rtw_hw_resume\n"); _enter_pwrlock(&pwrpriv->lock); pwrpriv->bips_processing = _TRUE; @@ -872,7 +902,6 @@ int rtw_hw_resume(_adapter *padapter) { pwrpriv->bips_processing = _FALSE; _exit_pwrlock(&pwrpriv->lock); - _func_exit_; return 0; error_exit: @@ -881,7 +910,8 @@ int rtw_hw_resume(_adapter *padapter) { } #endif -static int rtw_suspend(struct usb_interface *pusb_intf, pm_message_t message) { +static int rtw_suspend(struct usb_interface *pusb_intf, pm_message_t message) +{ struct dvobj_priv *dvobj; struct pwrctrl_priv *pwrpriv; struct debug_priv *pdbgpriv; @@ -892,7 +922,7 @@ static int rtw_suspend(struct usb_interface *pusb_intf, pm_message_t message) { dvobj = usb_get_intfdata(pusb_intf); pwrpriv = dvobj_to_pwrctl(dvobj); pdbgpriv = &dvobj->drv_dbg; - padapter = dvobj->padapters[IFACE_ID0]; + padapter = dvobj_get_primary_adapter(dvobj); if (pwrpriv->bInSuspend == _TRUE) { RTW_INFO("%s bInSuspend = %d\n", __FUNCTION__, pwrpriv->bInSuspend); @@ -906,7 +936,7 @@ static int rtw_suspend(struct usb_interface *pusb_intf, pm_message_t message) { #ifdef SUPPORT_HW_RFOFF_DETECTED /* The FW command register update must after MAC and FW init ready. */ - if ((padapter->bFWReady) && (pwrpriv->bHWPwrPindetect) && (padapter->registrypriv.usbss_enable)) { + if ((GET_HAL_DATA(padapter)->bFWReady) && (pwrpriv->bHWPwrPindetect) && (padapter->registrypriv.usbss_enable)) { u8 bOpen = _TRUE; rtw_interface_ps_func(padapter, HAL_USB_SELECT_SUSPEND, &bOpen); } @@ -921,7 +951,8 @@ static int rtw_suspend(struct usb_interface *pusb_intf, pm_message_t message) { return ret; } -int rtw_resume_process(_adapter *padapter) { +int rtw_resume_process(_adapter *padapter) +{ int ret, pm_cnt = 0; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct dvobj_priv *pdvobj = padapter->dvobj; @@ -952,7 +983,6 @@ int rtw_resume_process(_adapter *padapter) { } #endif /* #ifdef CONFIG_BT_COEXIST &CONFIG_AUTOSUSPEND& */ -#if defined(CONFIG_WOWLAN) || defined (CONFIG_AP_WOWLAN) /* * Due to usb wow suspend flow will cancel read/write port via intf_stop and * bReadPortCancel and bWritePortCancel are set _TRUE in intf_stop. @@ -961,7 +991,6 @@ int rtw_resume_process(_adapter *padapter) { */ RTW_ENABLE_FUNC(padapter, DF_RX_BIT); RTW_ENABLE_FUNC(padapter, DF_TX_BIT); -#endif ret = rtw_resume_common(padapter); @@ -969,7 +998,7 @@ int rtw_resume_process(_adapter *padapter) { if (pwrpriv->bInternalAutoSuspend) { #ifdef SUPPORT_HW_RFOFF_DETECTED /* The FW command register update must after MAC and FW init ready. */ - if ((padapter->bFWReady) && (pwrpriv->bHWPwrPindetect) && (padapter->registrypriv.usbss_enable)) { + if ((GET_HAL_DATA(padapter)->bFWReady) && (pwrpriv->bHWPwrPindetect) && (padapter->registrypriv.usbss_enable)) { u8 bOpen = _FALSE; rtw_interface_ps_func(padapter, HAL_USB_SELECT_SUSPEND, &bOpen); } @@ -993,7 +1022,8 @@ int rtw_resume_process(_adapter *padapter) { return ret; } -static int rtw_resume(struct usb_interface *pusb_intf) { +static int rtw_resume(struct usb_interface *pusb_intf) +{ struct dvobj_priv *dvobj; struct pwrctrl_priv *pwrpriv; struct debug_priv *pdbgpriv; @@ -1005,7 +1035,7 @@ static int rtw_resume(struct usb_interface *pusb_intf) { dvobj = usb_get_intfdata(pusb_intf); pwrpriv = dvobj_to_pwrctl(dvobj); pdbgpriv = &dvobj->drv_dbg; - padapter = dvobj->padapters[IFACE_ID0]; + padapter = dvobj_get_primary_adapter(dvobj); pmlmeext = &padapter->mlmeextpriv; RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid); @@ -1043,7 +1073,8 @@ static int rtw_resume(struct usb_interface *pusb_intf) { #ifdef CONFIG_AUTOSUSPEND -void autosuspend_enter(_adapter *padapter) { +void autosuspend_enter(_adapter *padapter) +{ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); @@ -1096,7 +1127,8 @@ void autosuspend_enter(_adapter *padapter) { } -int autoresume_enter(_adapter *padapter) { +int autoresume_enter(_adapter *padapter) +{ int result = _SUCCESS; struct security_priv *psecuritypriv = &(padapter->securitypriv); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; @@ -1171,7 +1203,8 @@ extern void rtd2885_wlan_netlink_sendMsg(char *action_string, char *name); _adapter *rtw_sw_export = NULL; _adapter *rtw_usb_primary_adapter_init(struct dvobj_priv *dvobj, - struct usb_interface *pusb_intf) { + struct usb_interface *pusb_intf) +{ _adapter *padapter = NULL; int status = _FAIL; @@ -1193,16 +1226,10 @@ _adapter *rtw_usb_primary_adapter_init(struct dvobj_priv *dvobj, /* set adapter_type/iface type for primary padapter */ padapter->isprimary = _TRUE; padapter->adapter_type = PRIMARY_ADAPTER; -#ifdef CONFIG_MI_WITH_MBSSID_CAM #ifdef CONFIG_MI_WITH_MBSSID_CAM/*Configure all IFACE to PORT0-MBSSID*/ padapter->hw_port = HW_PORT0; -#endif #else -#ifndef CONFIG_HWPORT_SWAP padapter->hw_port = HW_PORT0; -#else /* CONFIG_HWPORT_SWAP */ - padapter->hw_port = HW_PORT1; -#endif /* !CONFIG_HWPORT_SWAP */ #endif /* step init_io_priv */ @@ -1224,18 +1251,23 @@ _adapter *rtw_usb_primary_adapter_init(struct dvobj_priv *dvobj, rtw_hal_chip_configure(padapter); /* step read efuse/eeprom data and get mac_addr */ - rtw_hal_read_chip_info(padapter); - -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_Initialize(padapter); -#endif /* CONFIG_BT_COEXIST */ + if (rtw_hal_read_chip_info(padapter) == _FAIL) + goto free_hal_data; /* step 5. */ if (rtw_init_drv_sw(padapter) == _FAIL) { - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("Initialize driver software resource Failed!\n")); goto free_hal_data; } +#ifdef CONFIG_BT_COEXIST + if (GET_HAL_DATA(padapter)->EEPROMBluetoothCoexist) + rtw_btcoex_Initialize(padapter); + else + rtw_btcoex_wifionly_initialize(padapter); +#else /* !CONFIG_BT_COEXIST */ + rtw_btcoex_wifionly_initialize(padapter); +#endif /* CONFIG_BT_COEXIST */ + #ifdef CONFIG_PM #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) if (dvobj_to_pwrctl(dvobj)->bSupportRemoteWakeup) { @@ -1293,11 +1325,11 @@ _adapter *rtw_usb_primary_adapter_init(struct dvobj_priv *dvobj, rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); #endif /* CONFIG_P2P */ RTW_INFO("bDriverStopped:%s, bSurpriseRemoved:%s, bup:%d, hw_init_completed:%d\n" - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False" - , padapter->bup - , rtw_get_hw_init_completed(padapter) - ); + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False" + , padapter->bup + , rtw_get_hw_init_completed(padapter) + ); status = _SUCCESS; @@ -1313,21 +1345,22 @@ _adapter *rtw_usb_primary_adapter_init(struct dvobj_priv *dvobj, return padapter; } -static void rtw_usb_primary_adapter_deinit(_adapter *padapter) { +static void rtw_usb_primary_adapter_deinit(_adapter *padapter) +{ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); if (check_fwstate(pmlmepriv, _FW_LINKED)) - rtw_disassoc_cmd(padapter, 0, _FALSE); + rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); #ifdef CONFIG_AP_MODE if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { free_mlme_ap_info(padapter); -#ifdef CONFIG_HOSTAPD_MLME + #ifdef CONFIG_HOSTAPD_MLME hostapd_mode_unload(padapter); -#endif + #endif } #endif @@ -1372,7 +1405,8 @@ static void rtw_usb_primary_adapter_deinit(_adapter *padapter) { } -static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device_id *pdid) { +static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device_id *pdid) +{ _adapter *padapter = NULL; int status = _FAIL; struct dvobj_priv *dvobj; @@ -1380,7 +1414,6 @@ static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device int i; #endif - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+rtw_drv_init\n")); /* RTW_INFO("+rtw_drv_init\n"); */ /* step 0. */ @@ -1389,7 +1422,6 @@ static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device /* Initialize dvobj_priv */ dvobj = usb_dvobj_init(pusb_intf, pdid); if (dvobj == NULL) { - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("initialize device object priv Failed!\n")); goto exit; } @@ -1438,7 +1470,6 @@ static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device rtd2885_wlan_netlink_sendMsg("linkup", "8712"); #endif - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("-871x_drv - drv_init, success!\n")); status = _SUCCESS; @@ -1449,10 +1480,10 @@ static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device #endif free_if_vir: if (status != _SUCCESS) { -#ifdef CONFIG_CONCURRENT_MODE + #ifdef CONFIG_CONCURRENT_MODE rtw_drv_stop_vir_ifaces(dvobj); rtw_drv_free_vir_ifaces(dvobj); -#endif + #endif } free_if_prim: @@ -1470,17 +1501,16 @@ static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device * dev_remove() - our device is being removed */ /* rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both */ -static void rtw_dev_remove(struct usb_interface *pusb_intf) { +static void rtw_dev_remove(struct usb_interface *pusb_intf) +{ struct dvobj_priv *dvobj = usb_get_intfdata(pusb_intf); struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(dvobj); - _adapter *padapter = dvobj->padapters[IFACE_ID0]; + _adapter *padapter = dvobj_get_primary_adapter(dvobj); struct net_device *pnetdev = padapter->pnetdev; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _func_enter_; RTW_INFO("+rtw_dev_remove\n"); - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+dev_remove()\n")); dvobj->processing_dev_remove = _TRUE; @@ -1502,7 +1532,7 @@ static void rtw_dev_remove(struct usb_interface *pusb_intf) { rtw_unregister_early_suspend(pwrctl); #endif - if (padapter->bFWReady == _TRUE) { + if (GET_HAL_DATA(padapter)->bFWReady == _TRUE) { rtw_pm_set_ips(padapter, IPS_NONE); rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); @@ -1530,7 +1560,6 @@ static void rtw_dev_remove(struct usb_interface *pusb_intf) { usb_dvobj_deinit(pusb_intf); - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("-dev_remove()\n")); RTW_INFO("-r871xu_dev_remove, done\n"); @@ -1538,7 +1567,6 @@ static void rtw_dev_remove(struct usb_interface *pusb_intf) { rtw_sw_export = NULL; #endif - _func_exit_; return; @@ -1547,7 +1575,8 @@ static void rtw_dev_remove(struct usb_interface *pusb_intf) { extern int console_suspend_enabled; #endif -static int __init rtw_drv_entry(void) { +static int __init rtw_drv_entry(void) +{ int ret = 0; RTW_PRINT("module init start\n"); @@ -1570,6 +1599,7 @@ static int __init rtw_drv_entry(void) { rtw_suspend_lock_init(); rtw_drv_proc_init(); rtw_ndev_notifier_register(); + rtw_inetaddr_notifier_register(); ret = usb_register(&usb_drv.usbdrv); @@ -1578,6 +1608,7 @@ static int __init rtw_drv_entry(void) { rtw_suspend_lock_uninit(); rtw_drv_proc_deinit(); rtw_ndev_notifier_unregister(); + rtw_inetaddr_notifier_unregister(); goto exit; } @@ -1586,7 +1617,8 @@ static int __init rtw_drv_entry(void) { return ret; } -static void __exit rtw_drv_halt(void) { +static void __exit rtw_drv_halt(void) +{ RTW_PRINT("module exit start\n"); usb_drv.drv_registered = _FALSE; @@ -1598,6 +1630,7 @@ static void __exit rtw_drv_halt(void) { rtw_suspend_lock_uninit(); rtw_drv_proc_deinit(); rtw_ndev_notifier_unregister(); + rtw_inetaddr_notifier_unregister(); RTW_PRINT("module exit success\n"); @@ -1609,7 +1642,8 @@ module_init(rtw_drv_entry); module_exit(rtw_drv_halt); #ifdef CONFIG_INTEL_PROXIM -_adapter *rtw_usb_get_sw_pointer(void) { +_adapter *rtw_usb_get_sw_pointer(void) +{ return rtw_sw_export; } EXPORT_SYMBOL(rtw_usb_get_sw_pointer); diff --git a/os_dep/linux/usb_ops_linux.c b/os_dep/linux/usb_ops_linux.c index d7b996e..f3d64e5 100644 --- a/os_dep/linux/usb_ops_linux.c +++ b/os_dep/linux/usb_ops_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #define _USB_OPS_LINUX_C_ #include @@ -50,7 +46,6 @@ int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 inde /* RTW_INFO("%s %s:%d\n",__FUNCTION__, current->comm, current->pid); */ if (RTW_CANNOT_IO(padapter)) { - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usbctrl_vendorreq:(RTW_CANNOT_IO)!!!\n")); status = -EPERM; goto exit; } @@ -70,12 +65,12 @@ int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 inde #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC pIo_buf = pdvobjpriv->usb_vendor_req_buf; #else -#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE + #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE tmp_buf = rtw_malloc((u32) len + ALIGNMENT_UNIT); tmp_buflen = (u32)len + ALIGNMENT_UNIT; -#else /* use stack memory */ + #else /* use stack memory */ tmp_buflen = MAX_USB_IO_CTL_SIZE; -#endif + #endif /* Added by Albert 2010/02/09 */ /* For mstar platform, mstar suggests the address for USB IO should be 16 bytes alignment. */ @@ -117,12 +112,12 @@ int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 inde if (status == (-ESHUTDOWN) || status == -ENODEV) rtw_set_surprise_removed(padapter); else { -#ifdef DBG_CONFIG_ERROR_DETECT + #ifdef DBG_CONFIG_ERROR_DETECT { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); pHalData->srestpriv.Wifi_Error_Status = USB_VEN_REQ_CMD_FAIL; } -#endif + #endif } } else { /* status != len && status >= 0 */ if (status > 0) { @@ -171,7 +166,7 @@ static void _usbctrl_vendorreq_async_callback(struct urb *urb, struct pt_regs *r } int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request, - u16 value, u16 index, void *pdata, u16 len, u8 requesttype) + u16 value, u16 index, void *pdata, u16 len, u8 requesttype) { int rc; unsigned int pipe; @@ -213,7 +208,7 @@ int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request, _rtw_memcpy(buf, pdata, len); usb_fill_control_urb(urb, udev, pipe, (unsigned char *)dr, buf, len, - _usbctrl_vendorreq_async_callback, buf); + _usbctrl_vendorreq_async_callback, buf); rc = usb_submit_urb(urb, GFP_ATOMIC); if (rc < 0) { @@ -381,7 +376,6 @@ static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs) struct xmit_priv *pxmitpriv = &padapter->xmitpriv; /* struct pkt_attrib *pattrib = &pxmitframe->attrib; */ - _func_enter_; switch (pxmitbuf->flags) { case VO_QUEUE_INX: @@ -437,7 +431,6 @@ static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs) if(pxmitpriv->txirp_cnt==0) { - RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: txirp_cnt== 0, set allrxreturnevt!\n")); _rtw_up_sema(&(pxmitpriv->tx_retevt)); } */ @@ -457,14 +450,12 @@ static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs) if (purb->status == 0) { } else { - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_write_port_complete : purb->status(%d) != 0\n", purb->status)); RTW_INFO("###=> urb_write_port_complete status(%d)\n", purb->status); if ((purb->status == -EPIPE) || (purb->status == -EPROTO)) { /* usb_clear_halt(pusbdev, purb->pipe); */ /* msleep(10); */ sreset_set_wifi_error_status(padapter, USB_WRITE_PORT_FAIL); } else if (purb->status == -EINPROGRESS) { - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_write_port_complete: EINPROGESS\n")); goto check_completion; } else if (purb->status == -ENOENT) { @@ -476,26 +467,23 @@ static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs) goto check_completion; } else if (purb->status == -ESHUTDOWN) { - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_write_port_complete: ESHUTDOWN\n")); rtw_set_drv_stopped(padapter); - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_write_port_complete:bDriverStopped=TRUE\n")); goto check_completion; } else { rtw_set_surprise_removed(padapter); RTW_INFO("bSurpriseRemoved=TRUE\n"); - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_write_port_complete:bSurpriseRemoved=TRUE\n")); goto check_completion; } } -#ifdef DBG_CONFIG_ERROR_DETECT + #ifdef DBG_CONFIG_ERROR_DETECT { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); pHalData->srestpriv.last_tx_complete_time = rtw_get_current_time(); } -#endif + #endif check_completion: _enter_critical(&pxmitpriv->lock_sctx, &irqL); @@ -510,7 +498,6 @@ static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs) tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); } - _func_exit_; } @@ -530,9 +517,7 @@ u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) struct usb_device *pusbd = pdvobj->pusbdev; struct pkt_attrib *pattrib = &pxmitframe->attrib; - _func_enter_; - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("+usb_write_port\n")); if (RTW_CANNOT_TX(padapter)) { #ifdef DBG_TX @@ -540,7 +525,6 @@ u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) , rtw_is_drv_stopped(padapter) ? "True" : "False" , rtw_is_surprise_removed(padapter) ? "True" : "False"); #endif - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_write_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved )!!!\n")); rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_TX_DENY); goto exit; } @@ -619,16 +603,15 @@ u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) status = usb_submit_urb(purb, GFP_ATOMIC); if (!status) { -#ifdef DBG_CONFIG_ERROR_DETECT + #ifdef DBG_CONFIG_ERROR_DETECT { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); pHalData->srestpriv.last_tx_time = rtw_get_current_time(); } -#endif + #endif } else { rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_WRITE_PORT_ERR); RTW_INFO("usb_write_port, status=%d\n", status); - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_write_port(): usb_submit_urb, status=%x\n", status)); switch (status) { case -ENODEV: @@ -643,20 +626,18 @@ u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) ret = _SUCCESS; /* Commented by Albert 2009/10/13 - * We add the URB_ZERO_PACKET flag to urb so that the host will send the zero packet automatically. - * + * We add the URB_ZERO_PACKET flag to urb so that the host will send the zero packet automatically. */ + /* if(bwritezero == _TRUE) { usb_bulkout_zero(pintfhdl, addr); } */ - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("-usb_write_port\n")); exit: if (ret != _SUCCESS) rtw_free_xmitbuf(pxmitpriv, pxmitbuf); - _func_exit_; return ret; } @@ -714,16 +695,16 @@ void usb_recv_tasklet(void *priv) while (NULL != (precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue))) { if (RTW_CANNOT_RUN(padapter)) { - RTW_INFO("recv_tasklet => bDriverStopped or bSurpriseRemoved\n"); + RTW_INFO("recv_tasklet => bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" + , rtw_is_drv_stopped(padapter)? "True" : "False" + , rtw_is_surprise_removed(padapter)? "True" : "False"); break; } - recvbuf2recvframe(padapter, precvbuf); rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); } - } void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) @@ -732,8 +713,6 @@ void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) _adapter *padapter = (_adapter *)precvbuf->adapter; struct recv_priv *precvpriv = &padapter->recvpriv; - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete!!!\n")); - ATOMIC_DEC(&(precvpriv->rx_pending_cnt)); if (RTW_CANNOT_RX(padapter)) { @@ -741,28 +720,27 @@ void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) , __func__ , rtw_is_drv_stopped(padapter) ? "True" : "False" , rtw_is_surprise_removed(padapter) ? "True" : "False"); - goto exit; + return; } - if (purb->status == 0) { /* SUCCESS */ - if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) { - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete: (purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)\n")); + if (purb->status == 0) { + if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) { + RTW_INFO("%s()-%d: urb->actual_length:%u, MAX_RECVBUF_SZ:%u, RXDESC_SIZE:%u\n" + , __FUNCTION__, __LINE__, purb->actual_length, MAX_RECVBUF_SZ, RXDESC_SIZE); rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); } else { rtw_reset_continual_io_error(adapter_to_dvobj(padapter)); precvbuf->transfer_len = purb->actual_length; - /* rtw_enqueue_rx_transfer_buffer(precvpriv, rx_transfer_buf); */ rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue); tasklet_schedule(&precvpriv->recv_tasklet); } } else { - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete : purb->status(%d) != 0\n", purb->status)); - RTW_INFO("###=> usb_read_port_complete => urb status(%d)\n", purb->status); + RTW_INFO("###=> usb_read_port_complete => urb.status(%d)\n", purb->status); if (rtw_inc_and_chk_continual_io_error(adapter_to_dvobj(padapter)) == _TRUE) rtw_set_surprise_removed(padapter); @@ -772,23 +750,20 @@ void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) case -EPIPE: case -ENODEV: case -ESHUTDOWN: - /*rtw_set_surprise_removed(padapter);*/ - /* RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); */ case -ENOENT: rtw_set_drv_stopped(padapter); - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete:bDriverStopped=TRUE\n")); break; case -EPROTO: case -EILSEQ: case -ETIME: case -ECOMM: case -EOVERFLOW: -#ifdef DBG_CONFIG_ERROR_DETECT + #ifdef DBG_CONFIG_ERROR_DETECT { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL; } -#endif + #endif rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); break; case -EINPROGRESS: @@ -797,12 +772,8 @@ void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) default: break; } - } -exit: - - _func_exit_; } u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) @@ -818,10 +789,8 @@ u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) struct recv_priv *precvpriv = &adapter->recvpriv; struct usb_device *pusbd = pdvobj->pusbdev; - _func_enter_; if (RTW_CANNOT_RX(adapter) || (precvbuf == NULL)) { - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port:( RTW_CANNOT_RX ) || precvbuf == NULL!!!\n")); return _FAIL; } @@ -835,24 +804,22 @@ u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) pipe = ffaddr2pipehdl(pdvobj, addr); usb_fill_bulk_urb(purb, pusbd, pipe, - precvbuf->pbuf, - MAX_RECVBUF_SZ, - usb_read_port_complete, - precvbuf);/* context is precvbuf */ + precvbuf->pbuf, + MAX_RECVBUF_SZ, + usb_read_port_complete, + precvbuf);/* context is precvbuf */ purb->transfer_dma = precvbuf->dma_transfer_addr; purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; err = usb_submit_urb(purb, GFP_ATOMIC); if ((err) && (err != (-EPERM))) { - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("cannot submit rx in-token(err=0x%.8x), URB_STATUS =0x%.8x", err, purb->status)); RTW_INFO("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n", err, purb->status); ret = _FAIL; } } - _func_exit_; return ret; } @@ -868,10 +835,12 @@ void usb_recv_tasklet(void *priv) while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue))) { if (RTW_CANNOT_RUN(padapter)) { - RTW_INFO("recv_tasklet => bDriverStopped or bSurpriseRemoved\n"); -#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER + RTW_INFO("recv_tasklet => bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False"); + #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER if (rtw_free_skb_premem(pskb) != 0) -#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ + #endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ rtw_skb_free(pskb); break; } @@ -897,23 +866,22 @@ void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) _adapter *padapter = (_adapter *)precvbuf->adapter; struct recv_priv *precvpriv = &padapter->recvpriv; - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete!!!\n")); - ATOMIC_DEC(&(precvpriv->rx_pending_cnt)); if (RTW_CANNOT_RX(padapter)) { RTW_INFO("%s() RX Warning! bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" - , __func__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" + , __func__ + , rtw_is_drv_stopped(padapter) ? "True" : "False" , rtw_is_surprise_removed(padapter) ? "True" : "False"); goto exit; } - if (purb->status == 0) { /* SUCCESS */ + if (purb->status == 0) { + if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) { - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete: (purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)\n")); + RTW_INFO("%s()-%d: urb->actual_length:%u, MAX_RECVBUF_SZ:%u, RXDESC_SIZE:%u\n" + , __FUNCTION__, __LINE__, purb->actual_length, MAX_RECVBUF_SZ, RXDESC_SIZE); rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); - RTW_INFO("%s()-%d: RX Warning!\n", __FUNCTION__, __LINE__); } else { rtw_reset_continual_io_error(adapter_to_dvobj(padapter)); @@ -921,45 +889,40 @@ void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) skb_put(precvbuf->pskb, purb->actual_length); skb_queue_tail(&precvpriv->rx_skb_queue, precvbuf->pskb); -#ifndef CONFIG_FIX_NR_BULKIN_BUFFER + #ifndef CONFIG_FIX_NR_BULKIN_BUFFER if (skb_queue_len(&precvpriv->rx_skb_queue) <= 1) -#endif + #endif tasklet_schedule(&precvpriv->recv_tasklet); precvbuf->pskb = NULL; rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); } } else { - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete : purb->status(%d) != 0\n", purb->status)); - RTW_INFO("###=> usb_read_port_complete => urb status(%d)\n", purb->status); + RTW_INFO("###=> usb_read_port_complete => urb.status(%d)\n", purb->status); if (rtw_inc_and_chk_continual_io_error(adapter_to_dvobj(padapter)) == _TRUE) rtw_set_surprise_removed(padapter); - switch (purb->status) { case -EINVAL: case -EPIPE: case -ENODEV: case -ESHUTDOWN: - /*rtw_set_surprise_removed(padapter);*/ - /* RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); */ case -ENOENT: rtw_set_drv_stopped(padapter); - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete:bDriverStopped=TRUE\n")); break; case -EPROTO: case -EILSEQ: case -ETIME: case -ECOMM: case -EOVERFLOW: -#ifdef DBG_CONFIG_ERROR_DETECT + #ifdef DBG_CONFIG_ERROR_DETECT { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL; } -#endif + #endif rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); break; case -EINPROGRESS: @@ -968,13 +931,10 @@ void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) default: break; } - } exit: - - _func_exit_; - + return; } u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) @@ -990,10 +950,8 @@ u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) struct recv_priv *precvpriv = &adapter->recvpriv; struct usb_device *pusbd = pdvobj->pusbdev; - _func_enter_; if (RTW_CANNOT_RX(adapter) || (precvbuf == NULL)) { - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port:( RTW_CANNOT_RX ) || precvbuf == NULL!!!\n")); goto exit; } @@ -1007,9 +965,9 @@ u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) if (NULL != precvbuf->pskb) goto recv_buf_hook; -#ifndef CONFIG_FIX_NR_BULKIN_BUFFER + #ifndef CONFIG_FIX_NR_BULKIN_BUFFER precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); -#endif + #endif if (precvbuf->pskb == NULL) { if (0) @@ -1037,15 +995,15 @@ u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) pipe = ffaddr2pipehdl(pdvobj, addr); usb_fill_bulk_urb(purb, pusbd, pipe, - precvbuf->pbuf, - MAX_RECVBUF_SZ, - usb_read_port_complete, - precvbuf); + precvbuf->pbuf, + MAX_RECVBUF_SZ, + usb_read_port_complete, + precvbuf); err = usb_submit_urb(purb, GFP_ATOMIC); if (err && err != (-EPERM)) { RTW_INFO("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n" - , err, purb->status); + , err, purb->status); goto exit; } @@ -1054,7 +1012,6 @@ u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) exit: - _func_exit_; return ret; } @@ -1068,8 +1025,8 @@ void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs) if (RTW_CANNOT_RX(padapter)) { RTW_INFO("%s() RX Warning! bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" - , __func__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" + , __func__ + , rtw_is_drv_stopped(padapter) ? "True" : "False" , rtw_is_surprise_removed(padapter) ? "True" : "False"); return; @@ -1092,11 +1049,8 @@ void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs) case -EPIPE: case -ENODEV: case -ESHUTDOWN: - /*rtw_set_surprise_removed(padapter);*/ - /*RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete:bSurpriseRemoved=TRUE\n"));*/ case -ENOENT: rtw_set_drv_stopped(padapter); - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete:bDriverStopped=TRUE\n")); break; case -EPROTO: break; @@ -1119,10 +1073,8 @@ u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr) struct recv_priv *precvpriv = &adapter->recvpriv; struct usb_device *pusbd = pdvobj->pusbdev; - _func_enter_; if (RTW_CANNOT_RX(adapter)) { - RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_interrupt:( RTW_CANNOT_RX )!!!\n")); return _FAIL; } @@ -1130,11 +1082,11 @@ u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr) pipe = ffaddr2pipehdl(pdvobj, addr); usb_fill_int_urb(precvpriv->int_in_urb, pusbd, pipe, - precvpriv->int_in_buf, - INTERRUPT_MSG_FORMAT_LEN, - usb_read_interrupt_complete, - adapter, - 1); + precvpriv->int_in_buf, + INTERRUPT_MSG_FORMAT_LEN, + usb_read_interrupt_complete, + adapter, + 1); err = usb_submit_urb(precvpriv->int_in_urb, GFP_ATOMIC); if ((err) && (err != (-EPERM))) { @@ -1142,7 +1094,6 @@ u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr) ret = _FAIL; } - _func_exit_; return ret; } #endif /* CONFIG_USB_INTERRUPT_IN_PIPE */ diff --git a/os_dep/linux/wifi_regd.c b/os_dep/linux/wifi_regd.c index 30fb38a..745a9fe 100644 --- a/os_dep/linux/wifi_regd.c +++ b/os_dep/linux/wifi_regd.c @@ -1,6 +1,15 @@ /****************************************************************************** * - * Copyright(c) 2009-2010 Realtek Corporation. + * Copyright(c) 2009-2010 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. * *****************************************************************************/ @@ -134,13 +143,10 @@ static const struct ieee80211_regdomain rtw_regdom_14 = { static struct rtw_regulatory *rtw_regd; #endif -static bool _rtw_is_radar_freq(u16 center_freq) { - return center_freq >= 5260 && center_freq <= 5700; -} - #if 0 /* not_yet */ static void _rtw_reg_apply_beaconing_flags(struct wiphy *wiphy, - enum nl80211_reg_initiator initiator) { + enum nl80211_reg_initiator initiator) +{ enum nl80211_band band; struct ieee80211_supported_band *sband; const struct ieee80211_reg_rule *reg_rule; @@ -149,7 +155,7 @@ static void _rtw_reg_apply_beaconing_flags(struct wiphy *wiphy, u32 bandwidth = 0; int r; - for (band = 0; band < NUM_NL80211_BANDS; band++) { + for (band = 0; band < IEEE80211_NUM_BANDS; band++) { if (!wiphy->bands[band]) continue; @@ -158,12 +164,12 @@ static void _rtw_reg_apply_beaconing_flags(struct wiphy *wiphy, for (i = 0; i < sband->n_channels; i++) { ch = &sband->channels[i]; - if (_rtw_is_radar_freq(ch->center_freq) || - (ch->flags & IEEE80211_CHAN_RADAR)) + if (rtw_is_dfs_ch(ch->hw_value) || + (ch->flags & IEEE80211_CHAN_RADAR)) continue; if (initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) { r = freq_reg_info(wiphy, ch->center_freq, - bandwidth, ®_rule); + bandwidth, ®_rule); if (r) continue; @@ -179,14 +185,14 @@ static void _rtw_reg_apply_beaconing_flags(struct wiphy *wiphy, if (!(reg_rule->flags & NL80211_RRF_NO_IBSS)) ch->flags &= ~IEEE80211_CHAN_NO_IBSS; if (! - (reg_rule->flags & - NL80211_RRF_PASSIVE_SCAN)) + (reg_rule->flags & + NL80211_RRF_PASSIVE_SCAN)) ch->flags &= - ~IEEE80211_CHAN_PASSIVE_SCAN; + ~IEEE80211_CHAN_PASSIVE_SCAN; } else { if (ch->beacon_found) ch->flags &= ~(IEEE80211_CHAN_NO_IBSS | - IEEE80211_CHAN_PASSIVE_SCAN); + IEEE80211_CHAN_PASSIVE_SCAN); } } } @@ -194,8 +200,9 @@ static void _rtw_reg_apply_beaconing_flags(struct wiphy *wiphy, /* Allows active scan scan on Ch 12 and 13 */ static void _rtw_reg_apply_active_scan_flags(struct wiphy *wiphy, - enum nl80211_reg_initiator - initiator) { + enum nl80211_reg_initiator + initiator) +{ struct ieee80211_supported_band *sband; struct ieee80211_channel *ch; const struct ieee80211_reg_rule *reg_rule; @@ -249,7 +256,8 @@ static void _rtw_reg_apply_active_scan_flags(struct wiphy *wiphy, * Always apply Radar/DFS rules on * freq range 5260 MHz - 5700 MHz */ -static void _rtw_reg_apply_radar_flags(struct wiphy *wiphy) { +static void _rtw_reg_apply_radar_flags(struct wiphy *wiphy) +{ struct ieee80211_supported_band *sband; struct ieee80211_channel *ch; unsigned int i; @@ -261,19 +269,25 @@ static void _rtw_reg_apply_radar_flags(struct wiphy *wiphy) { for (i = 0; i < sband->n_channels; i++) { ch = &sband->channels[i]; - if (!_rtw_is_radar_freq(ch->center_freq)) + if (!rtw_is_dfs_ch(ch->hw_value)) continue; #ifdef CONFIG_DFS -#if defined(CONFIG_DFS_MASTER) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) - if (!(ch->flags & IEEE80211_CHAN_DISABLED)) { + if (!(ch->flags & IEEE80211_CHAN_DISABLED) + #if defined(CONFIG_DFS_MASTER) + && rtw_odm_dfs_domain_unknown(wiphy_to_adapter(wiphy)) + #endif + ) { ch->flags |= IEEE80211_CHAN_RADAR; -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) - ch->flags |= (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN); -#else - ch->flags |= IEEE80211_CHAN_NO_IR; -#endif + #ifdef CONFIG_CENTOS_7 + ch->flags |= IEEE80211_CHAN_NO_IR; + #else + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + ch->flags |= (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN); + #else + ch->flags |= IEEE80211_CHAN_NO_IR; + #endif + #endif } -#endif #endif /* CONFIG_DFS */ #if 0 @@ -290,19 +304,20 @@ static void _rtw_reg_apply_radar_flags(struct wiphy *wiphy) { */ if (!(ch->flags & IEEE80211_CHAN_DISABLED)) ch->flags |= IEEE80211_CHAN_RADAR | - IEEE80211_CHAN_NO_IBSS | - IEEE80211_CHAN_PASSIVE_SCAN; + IEEE80211_CHAN_NO_IBSS | + IEEE80211_CHAN_PASSIVE_SCAN; #endif } } -static void _rtw_reg_apply_flags(struct wiphy *wiphy) { +static void _rtw_reg_apply_flags(struct wiphy *wiphy) +{ #if 1 /* by channel plan */ _adapter *padapter = wiphy_to_adapter(wiphy); - u8 channel_plan = padapter->mlmepriv.ChannelPlan; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - RT_CHANNEL_INFO *channel_set = pmlmeext->channel_set; - u8 max_chan_nums = pmlmeext->max_chan_nums; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + u8 channel_plan = rfctl->ChannelPlan; + RT_CHANNEL_INFO *channel_set = rfctl->channel_set; + u8 max_chan_nums = rfctl->max_chan_nums; struct ieee80211_supported_band *sband; struct ieee80211_channel *ch; @@ -311,7 +326,6 @@ static void _rtw_reg_apply_flags(struct wiphy *wiphy) { u32 freq; /* all channels disable */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0) for (i = 0; i < NUM_NL80211_BANDS; i++) { sband = wiphy->bands[i]; @@ -324,22 +338,6 @@ static void _rtw_reg_apply_flags(struct wiphy *wiphy) { } } } -#else - for (i = 0; i < IEEE80211_NUM_BANDS; i++) { - sband = wiphy->bands[i]; - - if (sband) { - for (j = 0; j < sband->n_channels; j++) { - ch = &sband->channels[j]; - - if (ch) - ch->flags = IEEE80211_CHAN_DISABLED; - } - } - } -#endif - - /* channels apply by channel plans. */ for (i = 0; i < max_chan_nums; i++) { @@ -348,14 +346,20 @@ static void _rtw_reg_apply_flags(struct wiphy *wiphy) { ch = ieee80211_get_channel(wiphy, freq); if (ch) { - if (channel_set[i].ScanType == SCAN_PASSIVE) { -#if defined(CONFIG_DFS_MASTER) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) - ch->flags = 0; -#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) - ch->flags = (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN); -#else - ch->flags = IEEE80211_CHAN_NO_IR; -#endif + if (channel_set[i].ScanType == SCAN_PASSIVE + #if defined(CONFIG_DFS_MASTER) + && rtw_odm_dfs_domain_unknown(wiphy_to_adapter(wiphy)) + #endif + ) { + #ifdef CONFIG_CENTOS_7 + ch->flags = IEEE80211_CHAN_NO_IR; + #else + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + ch->flags = (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN); + #else + ch->flags = IEEE80211_CHAN_NO_IR; + #endif + #endif } else ch->flags = 0; } @@ -374,7 +378,7 @@ static void _rtw_reg_apply_flags(struct wiphy *wiphy) { u16 channel; u32 freq; - for (i = 0; i < IEEE80211_NUM_BANDS; i++) { + for (i = 0; i < NUM_NL80211_BANDS; i++) { sband = wiphy->bands[i]; if (sband) @@ -403,16 +407,18 @@ static void _rtw_reg_apply_flags(struct wiphy *wiphy) { } static void _rtw_reg_apply_world_flags(struct wiphy *wiphy, - enum nl80211_reg_initiator initiator, - struct rtw_regulatory *reg) { + enum nl80211_reg_initiator initiator, + struct rtw_regulatory *reg) +{ /* _rtw_reg_apply_beaconing_flags(wiphy, initiator); */ /* _rtw_reg_apply_active_scan_flags(wiphy, initiator); */ return; } static int _rtw_reg_notifier_apply(struct wiphy *wiphy, - struct regulatory_request *request, - struct rtw_regulatory *reg) { + struct regulatory_request *request, + struct rtw_regulatory *reg) +{ /* Hard code flags */ _rtw_reg_apply_flags(wiphy); @@ -424,23 +430,23 @@ static int _rtw_reg_notifier_apply(struct wiphy *wiphy, case NL80211_REGDOM_SET_BY_DRIVER: RTW_INFO("%s: %s\n", __func__, "NL80211_REGDOM_SET_BY_DRIVER"); _rtw_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, - reg); + reg); break; case NL80211_REGDOM_SET_BY_CORE: RTW_INFO("%s: %s\n", __func__, - "NL80211_REGDOM_SET_BY_CORE to DRV"); + "NL80211_REGDOM_SET_BY_CORE to DRV"); _rtw_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, - reg); + reg); break; case NL80211_REGDOM_SET_BY_USER: RTW_INFO("%s: %s\n", __func__, - "NL80211_REGDOM_SET_BY_USER to DRV"); + "NL80211_REGDOM_SET_BY_USER to DRV"); _rtw_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, - reg); + reg); break; case NL80211_REGDOM_SET_BY_COUNTRY_IE: RTW_INFO("%s: %s\n", __func__, - "NL80211_REGDOM_SET_BY_COUNTRY_IE"); + "NL80211_REGDOM_SET_BY_COUNTRY_IE"); _rtw_reg_apply_world_flags(wiphy, request->initiator, reg); break; } @@ -449,8 +455,9 @@ static int _rtw_reg_notifier_apply(struct wiphy *wiphy, } static const struct ieee80211_regdomain *_rtw_regdomain_select(struct - rtw_regulatory - *reg) { + rtw_regulatory + *reg) +{ #if 0 switch (reg->country_code) { case COUNTRY_CODE_USER: @@ -462,7 +469,8 @@ static const struct ieee80211_regdomain *_rtw_regdomain_select(struct #endif } -void _rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) { +void _rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) +{ struct rtw_regulatory *reg = NULL; RTW_INFO("%s\n", __func__); @@ -482,7 +490,8 @@ void rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) #endif } -void rtw_reg_notify_by_driver(_adapter *adapter) { +void rtw_reg_notify_by_driver(_adapter *adapter) +{ if ((adapter->rtw_wdev != NULL) && (adapter->rtw_wdev->wiphy)) { struct regulatory_request request; request.initiator = NL80211_REGDOM_SET_BY_DRIVER; @@ -490,19 +499,26 @@ void rtw_reg_notify_by_driver(_adapter *adapter) { } } -static void _rtw_regd_init_wiphy(struct rtw_regulatory *reg, struct wiphy *wiphy) { +static void _rtw_regd_init_wiphy(struct rtw_regulatory *reg, struct wiphy *wiphy) +{ const struct ieee80211_regdomain *regd; wiphy->reg_notifier = rtw_reg_notifier; -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) - wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY; - wiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY; - wiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS; -#else +#ifdef CONFIG_CENTOS_7 wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG; wiphy->regulatory_flags &= ~REGULATORY_STRICT_REG; wiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS; +#else + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY; + wiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY; + wiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS; + #else + wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG; + wiphy->regulatory_flags &= ~REGULATORY_STRICT_REG; + wiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS; + #endif #endif regd = _rtw_regdomain_select(reg); @@ -514,7 +530,8 @@ static void _rtw_regd_init_wiphy(struct rtw_regulatory *reg, struct wiphy *wiphy _rtw_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, reg); } -static struct country_code_to_enum_rd *_rtw_regd_find_country(u16 countrycode) { +static struct country_code_to_enum_rd *_rtw_regd_find_country(u16 countrycode) +{ int i; for (i = 0; i < ARRAY_SIZE(allCountries); i++) { @@ -524,13 +541,14 @@ static struct country_code_to_enum_rd *_rtw_regd_find_country(u16 countrycode) { return NULL; } -int rtw_regd_init(_adapter *padapter) { +int rtw_regd_init(_adapter *padapter) +{ struct wiphy *wiphy = padapter->rtw_wdev->wiphy; #if 0 if (rtw_regd == NULL) { rtw_regd = (struct rtw_regulatory *) - rtw_malloc(sizeof(struct rtw_regulatory)); + rtw_malloc(sizeof(struct rtw_regulatory)); rtw_regd->alpha2[0] = '9'; rtw_regd->alpha2[1] = '9'; @@ -539,7 +557,7 @@ int rtw_regd_init(_adapter *padapter) { } RTW_INFO("%s: Country alpha2 being used: %c%c\n", - __func__, rtw_regd->alpha2[0], rtw_regd->alpha2[1]); + __func__, rtw_regd->alpha2[0], rtw_regd->alpha2[1]); #endif _rtw_regd_init_wiphy(NULL, wiphy); diff --git a/os_dep/linux/xmit_linux.c b/os_dep/linux/xmit_linux.c index 8952a5b..aeef418 100644 --- a/os_dep/linux/xmit_linux.c +++ b/os_dep/linux/xmit_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _XMIT_OSDEP_C_ #include @@ -30,7 +25,6 @@ uint rtw_remainder_len(struct pkt_file *pfile) void _rtw_open_pktfile(_pkt *pktptr, struct pkt_file *pfile) { - _func_enter_; pfile->pkt = pktptr; pfile->cur_addr = pfile->buf_start = pktptr->data; @@ -38,14 +32,12 @@ void _rtw_open_pktfile(_pkt *pktptr, struct pkt_file *pfile) pfile->cur_buffer = pfile->buf_start ; - _func_exit_; } uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen) { uint len = 0; - _func_enter_; len = rtw_remainder_len(pfile); len = (rlen > len) ? len : rlen; @@ -56,21 +48,17 @@ uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen) pfile->cur_addr += len; pfile->pkt_len -= len; - _func_exit_; return len; } sint rtw_endofpktfile(struct pkt_file *pfile) { - _func_enter_; if (pfile->pkt_len == 0) { - _func_exit_; return _TRUE; } - _func_exit_; return _FALSE; } @@ -306,6 +294,13 @@ void rtw_os_xmit_schedule(_adapter *padapter) tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); _exit_critical_bh(&pxmitpriv->lock, &irqL); + +#if defined(CONFIG_PCI_HCI) && defined(CONFIG_XMIT_THREAD_MODE) + if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE) + _rtw_up_sema(&padapter->xmitpriv.xmit_sema); +#endif + + #endif } @@ -404,9 +399,9 @@ int rtw_mlcst2unicst(_adapter *padapter, struct sk_buff *skb) /* avoid come from STA1 and send back STA1 */ if (_rtw_memcmp(psta->hwaddr, &skb->data[6], 6) == _TRUE - || _rtw_memcmp(psta->hwaddr, null_addr, 6) == _TRUE - || _rtw_memcmp(psta->hwaddr, bc_addr, 6) == _TRUE - ) { + || _rtw_memcmp(psta->hwaddr, null_addr, 6) == _TRUE + || _rtw_memcmp(psta->hwaddr, bc_addr, 6) == _TRUE + ) { DBG_COUNTER(padapter->tx_logs.os_tx_m2u_ignore_self); continue; } @@ -452,21 +447,18 @@ int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) u16 queue; #endif - _func_enter_; if (padapter->registrypriv.mp_mode) { RTW_INFO("MP_TX_DROP_OS_FRAME\n"); goto drop_packet; } DBG_COUNTER(padapter->tx_logs.os_tx); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("+xmit_enry\n")); if (rtw_if_up(padapter) == _FALSE) { DBG_COUNTER(padapter->tx_logs.os_tx_err_up); - RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit_entry: rtw_if_up fail\n")); -#ifdef DBG_TX_DROP_FRAME + #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s if_up fail\n", __FUNCTION__); -#endif + #endif goto drop_packet; } @@ -474,15 +466,15 @@ int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) #ifdef CONFIG_TX_MCAST2UNI if (!rtw_mc2u_disable - && check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE - && (IP_MCAST_MAC(pkt->data) - || ICMPV6_MCAST_MAC(pkt->data) -#ifdef CONFIG_TX_BCAST2UNI - || is_broadcast_mac_addr(pkt->data) -#endif - ) - && (padapter->registrypriv.wifi_spec == 0) - ) { + && check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE + && (IP_MCAST_MAC(pkt->data) + || ICMPV6_MCAST_MAC(pkt->data) + #ifdef CONFIG_TX_BCAST2UNI + || is_broadcast_mac_addr(pkt->data) + #endif + ) + && (padapter->registrypriv.wifi_spec == 0) + ) { if (pxmitpriv->free_xmitframe_cnt > (NR_XMITFRAME / 4)) { res = rtw_mlcst2unicst(padapter, pkt); if (res == _TRUE) @@ -497,23 +489,20 @@ int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) res = rtw_xmit(padapter, &pkt); if (res < 0) { -#ifdef DBG_TX_DROP_FRAME + #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__); -#endif + #endif goto drop_packet; } - RT_TRACE(_module_xmit_osdep_c_, _drv_info_, ("rtw_xmit_entry: tx_pkts=%d\n", (u32)pxmitpriv->tx_pkts)); goto exit; drop_packet: pxmitpriv->tx_drop++; rtw_os_pkt_complete(padapter, pkt); - RT_TRACE(_module_xmit_osdep_c_, _drv_notice_, ("rtw_xmit_entry: drop, tx_drop=%d\n", (u32)pxmitpriv->tx_drop)); exit: - _func_exit_; return 0; } @@ -525,8 +514,11 @@ int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) int ret = 0; if (pkt) { - if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) + if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) rtw_monitor_xmit_entry((struct sk_buff *)pkt, pnetdev); +#endif + } else { rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, pkt->truesize); ret = _rtw_xmit_entry(pkt, pnetdev); diff --git a/os_dep/osdep_service.c b/os_dep/osdep_service.c index 9df4be6..86c38ee 100644 --- a/os_dep/osdep_service.c +++ b/os_dep/osdep_service.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _OSDEP_SERVICE_C_ @@ -26,10 +21,10 @@ #define RT_TAG '1178' #ifdef DBG_MEMORY_LEAK - #ifdef PLATFORM_LINUX - atomic_t _malloc_cnt = ATOMIC_INIT(0); - atomic_t _malloc_size = ATOMIC_INIT(0); - #endif +#ifdef PLATFORM_LINUX +atomic_t _malloc_cnt = ATOMIC_INIT(0); +atomic_t _malloc_size = ATOMIC_INIT(0); +#endif #endif /* DBG_MEMORY_LEAK */ @@ -335,56 +330,41 @@ inline struct sk_buff *_rtw_pskb_copy(struct sk_buff *skb) inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb) { -#ifdef CONFIG_NAPI -#ifdef CONFIG_GRO - _adapter *adapter = (_adapter *) rtw_netdev_priv(ndev); - struct registry_priv *reg = &adapter->registrypriv; - static int cnt_done[10] = {0}; - int ret; -#endif -#endif -#ifdef PLATFORM_LINUX +#if defined(PLATFORM_LINUX) skb->dev = ndev; -#ifdef CONFIG_NAPI -#ifdef CONFIG_GRO - /* - * enum gro_result { - * GRO_MERGED, - * GRO_MERGED_FREE, - * GRO_HELD, - * GRO_NORMAL, - * GRO_DROP, - * } - */ - ret = napi_gro_receive(&adapter->napi, skb); - if (reg->napi_debug) { - if (ret < 10) - cnt_done[ret]++; - - if (printk_ratelimit()) { - RTW_INFO("napi_gro_receive: %d\n", ret); - RTW_INFO("0:%d, 1:%d, 2:%d, 3:%d, 4:%d, 5:%d\n", - cnt_done[0], - cnt_done[1], - cnt_done[2], - cnt_done[3], - cnt_done[4], - cnt_done[5]); - } - } - return ret == GRO_DROP ? NET_RX_DROP : NET_RX_SUCCESS; + return netif_rx(skb); +#elif defined(PLATFORM_FREEBSD) + return (*ndev->if_input)(ndev, skb); #else + rtw_warn_on(1); + return -1; +#endif +} + +#ifdef CONFIG_RTW_NAPI +inline int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb) +{ +#if defined(PLATFORM_LINUX) + skb->dev = ndev; return netif_receive_skb(skb); -#endif /* CONFIG_GRO */ #else - return netif_rx(skb); -#endif /* CONFIG_NAPI */ -#endif /* PLATFORM_LINUX */ + rtw_warn_on(1); + return -1; +#endif +} -#ifdef PLATFORM_FREEBSD - return (*ndev->if_input)(ndev, skb); -#endif /* PLATFORM_FREEBSD */ +#ifdef CONFIG_RTW_GRO +inline gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb) +{ +#if defined(PLATFORM_LINUX) + return napi_gro_receive(napi, skb); +#else + rtw_warn_on(1); + return -1; +#endif } +#endif /* CONFIG_RTW_GRO */ +#endif /* CONFIG_RTW_NAPI */ void _rtw_skb_queue_purge(struct sk_buff_head *list) { @@ -436,7 +416,7 @@ struct rtw_mem_stat { struct rtw_mem_stat rtw_mem_type_stat[mstat_tf_idx(MSTAT_TYPE_MAX)]; #ifdef RTW_MEM_FUNC_STAT - struct rtw_mem_stat rtw_mem_func_stat[mstat_ff_idx(MSTAT_FUNC_MAX)]; +struct rtw_mem_stat rtw_mem_func_stat[mstat_ff_idx(MSTAT_FUNC_MAX)]; #endif char *MSTAT_TYPE_str[] = { @@ -510,14 +490,14 @@ void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 s ATOMIC_SET(&(rtw_mem_type_stat[i].alloc_cnt), 0); ATOMIC_SET(&(rtw_mem_type_stat[i].alloc_err_cnt), 0); } -#ifdef RTW_MEM_FUNC_STAT + #ifdef RTW_MEM_FUNC_STAT for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++) { ATOMIC_SET(&(rtw_mem_func_stat[i].alloc), 0); ATOMIC_SET(&(rtw_mem_func_stat[i].peak), 0); ATOMIC_SET(&(rtw_mem_func_stat[i].alloc_cnt), 0); ATOMIC_SET(&(rtw_mem_func_stat[i].alloc_err_cnt), 0); } -#endif + #endif } switch (status) { @@ -528,29 +508,29 @@ void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 s if (peak < alloc) ATOMIC_SET(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak), alloc); -#ifdef RTW_MEM_FUNC_STAT + #ifdef RTW_MEM_FUNC_STAT ATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt)); alloc = ATOMIC_ADD_RETURN(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz); peak = ATOMIC_READ(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak)); if (peak < alloc) ATOMIC_SET(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak), alloc); -#endif + #endif break; case MSTAT_ALLOC_FAIL: ATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_err_cnt)); -#ifdef RTW_MEM_FUNC_STAT + #ifdef RTW_MEM_FUNC_STAT ATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_err_cnt)); -#endif + #endif break; case MSTAT_FREE: ATOMIC_DEC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt)); ATOMIC_SUB(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz); -#ifdef RTW_MEM_FUNC_STAT + #ifdef RTW_MEM_FUNC_STAT ATOMIC_DEC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt)); ATOMIC_SUB(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz); -#endif + #endif break; }; @@ -581,8 +561,8 @@ bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size) int i; for (i = 0; i < mstat_sniff_rule_num; i++) { if (mstat_sniff_rules[i].flags == flags - && mstat_sniff_rules[i].lb <= size - && mstat_sniff_rules[i].hb >= size) + && mstat_sniff_rules[i].lb <= size + && mstat_sniff_rules[i].hb >= size) return _TRUE; } @@ -791,6 +771,48 @@ inline int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat return ret; } +#ifdef CONFIG_RTW_NAPI +inline int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) +{ + int ret; + unsigned int truesize = skb->truesize; + + if (match_mstat_sniff_rules(flags, truesize)) + RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize); + + ret = _rtw_netif_receive_skb(ndev, skb); + + rtw_mstat_update( + flags + , MSTAT_FREE + , truesize + ); + + return ret; +} + +#ifdef CONFIG_RTW_GRO +inline gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) +{ + int ret; + unsigned int truesize = skb->truesize; + + if (match_mstat_sniff_rules(flags, truesize)) + RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize); + + ret = _rtw_napi_gro_receive(napi, skb); + + rtw_mstat_update( + flags + , MSTAT_FREE + , truesize + ); + + return ret; +} +#endif /* CONFIG_RTW_GRO */ +#endif /* CONFIG_RTW_NAPI */ + inline void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line) { struct sk_buff *skb; @@ -879,7 +901,7 @@ inline void _rtw_memmove(void *dst, const void *src, u32 sz) #if defined(PLATFORM_LINUX) memmove(dst, src, sz); #else -#warning "no implementation\n" + #warning "no implementation\n" #endif } @@ -1039,18 +1061,18 @@ void rtw_list_insert_tail(_list *plist, _list *phead) } -void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc) +void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx) { _adapter *adapter = (_adapter *)padapter; #ifdef PLATFORM_LINUX - _init_timer(ptimer, adapter->pnetdev, pfunc, adapter); + _init_timer(ptimer, adapter->pnetdev, pfunc, ctx); #endif #ifdef PLATFORM_FREEBSD - _init_timer(ptimer, adapter->pifp, pfunc, adapter->mlmepriv.nic_hdl); + _init_timer(ptimer, adapter->pifp, pfunc, ctx); #endif #ifdef PLATFORM_WINDOWS - _init_timer(ptimer, adapter->hndis_adapter, pfunc, adapter->mlmepriv.nic_hdl); + _init_timer(ptimer, adapter->hndis_adapter, pfunc, ctx); #endif } @@ -1149,7 +1171,43 @@ u32 _rtw_down_sema(_sema *sema) #endif } +inline void thread_exit(_completion *comp) +{ +#ifdef PLATFORM_LINUX + complete_and_exit(comp, 0); +#endif +#ifdef PLATFORM_FREEBSD + printf("%s", "RTKTHREAD_exit"); +#endif + +#ifdef PLATFORM_OS_CE + ExitThread(STATUS_SUCCESS); +#endif + +#ifdef PLATFORM_OS_XP + PsTerminateSystemThread(STATUS_SUCCESS); +#endif +} + +inline void _rtw_init_completion(_completion *comp) +{ +#ifdef PLATFORM_LINUX + init_completion(comp); +#endif +} +inline void _rtw_wait_for_comp_timeout(_completion *comp) +{ +#ifdef PLATFORM_LINUX + wait_for_completion_timeout(comp, msecs_to_jiffies(3000)); +#endif +} +inline void _rtw_wait_for_comp(_completion *comp) +{ +#ifdef PLATFORM_LINUX + wait_for_completion(comp); +#endif +} void _rtw_mutex_init(_mutex *pmutex) { @@ -1923,7 +1981,7 @@ inline int ATOMIC_DEC_RETURN(ATOMIC_T *v) * @param mode please refer to linux document * @return Linux specific error code */ -static int openFile(struct file **fpp, char *path, int flag, int mode) +static int openFile(struct file **fpp, const char *path, int flag, int mode) { struct file *fp; @@ -1961,10 +2019,10 @@ static int readFile(struct file *fp, char *buf, int len) while (sum < len) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) && LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)) + rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos); +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) rlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos); -#else - rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos); #endif #else rlen = fp->f_op->read(fp, buf + sum, len - sum, &fp->f_pos); @@ -2004,10 +2062,11 @@ static int writeFile(struct file *fp, char *buf, int len) /* * Test if the specifi @param path is a file and readable +* If readable, @param sz is got * @param path the path of the file to test * @return Linux specific error code */ -static int isFileReadable(char *path) +static int isFileReadable(const char *path, u32 *sz) { struct file *fp; int ret = 0; @@ -2024,6 +2083,14 @@ static int isFileReadable(char *path) if (1 != readFile(fp, &buf, 1)) ret = PTR_ERR(fp); + if (ret == 0 && sz) { + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) + *sz = i_size_read(fp->f_path.dentry->d_inode); + #else + *sz = i_size_read(fp->f_dentry->d_inode); + #endif + } + set_fs(oldfs); filp_close(fp, NULL); } @@ -2037,7 +2104,7 @@ static int isFileReadable(char *path) * @param sz how many bytes to read at most * @return the byte we've read, or Linux specific error code */ -static int retriveFromFile(char *path, u8 *buf, u32 sz) +static int retriveFromFile(const char *path, u8 *buf, u32 sz) { int ret = -1; mm_segment_t oldfs; @@ -2072,7 +2139,7 @@ static int retriveFromFile(char *path, u8 *buf, u32 sz) * @param sz how many bytes to write at most * @return the byte we've written, or Linux specific error code */ -static int storeToFile(char *path, u8 *buf, u32 sz) +static int storeToFile(const char *path, u8 *buf, u32 sz) { int ret = 0; mm_segment_t oldfs; @@ -2106,10 +2173,29 @@ static int storeToFile(char *path, u8 *buf, u32 sz) * @param path the path of the file to test * @return _TRUE or _FALSE */ -int rtw_is_file_readable(char *path) +int rtw_is_file_readable(const char *path) { #ifdef PLATFORM_LINUX - if (isFileReadable(path) == 0) + if (isFileReadable(path, NULL) == 0) + return _TRUE; + else + return _FALSE; +#else + /* Todo... */ + return _FALSE; +#endif +} + +/* +* Test if the specifi @param path is a file and readable. +* If readable, @param sz is got +* @param path the path of the file to test +* @return _TRUE or _FALSE +*/ +int rtw_is_file_readable_with_size(const char *path, u32 *sz) +{ +#ifdef PLATFORM_LINUX + if (isFileReadable(path, sz) == 0) return _TRUE; else return _FALSE; @@ -2126,7 +2212,7 @@ int rtw_is_file_readable(char *path) * @param sz how many bytes to read at most * @return the byte we've read */ -int rtw_retrieve_from_file(char *path, u8 *buf, u32 sz) +int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz) { #ifdef PLATFORM_LINUX int ret = retriveFromFile(path, buf, sz); @@ -2144,7 +2230,7 @@ int rtw_retrieve_from_file(char *path, u8 *buf, u32 sz) * @param sz how many bytes to write at most * @return the byte we've written */ -int rtw_store_to_file(char *path, u8 *buf, u32 sz) +int rtw_store_to_file(const char *path, u8 *buf, u32 sz) { #ifdef PLATFORM_LINUX int ret = storeToFile(path, buf, sz); @@ -2222,20 +2308,19 @@ void rtw_free_netdev(struct net_device *netdev) return; } -/* -* Jeff: this function should be called under ioctl (rtnl_lock is accquired) while -* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26) -*/ int rtw_change_ifname(_adapter *padapter, const char *ifname) { + struct dvobj_priv *dvobj; struct net_device *pnetdev; struct net_device *cur_pnetdev; struct rereg_nd_name_data *rereg_priv; int ret; + u8 rtnl_lock_needed; if (!padapter) goto error; + dvobj = adapter_to_dvobj(padapter); cur_pnetdev = padapter->pnetdev; rereg_priv = &padapter->rereg_nd_name_priv; @@ -2245,11 +2330,11 @@ int rtw_change_ifname(_adapter *padapter, const char *ifname) rereg_priv->old_pnetdev = NULL; } -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) - if (!rtnl_is_locked()) + rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj); + + if (rtnl_lock_needed) unregister_netdev(cur_pnetdev); else -#endif unregister_netdevice(cur_pnetdev); rereg_priv->old_pnetdev = cur_pnetdev; @@ -2266,15 +2351,12 @@ int rtw_change_ifname(_adapter *padapter, const char *ifname) _rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) - if (!rtnl_is_locked()) + if (rtnl_lock_needed) ret = register_netdev(pnetdev); else -#endif ret = register_netdevice(pnetdev); if (ret != 0) { - RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("register_netdev() failed\n")); goto error; } @@ -2550,6 +2632,146 @@ void rtw_cbuf_free(struct rtw_cbuf *cbuf) rtw_mfree((u8 *)cbuf, sizeof(*cbuf) + sizeof(void *) * cbuf->size); } +/** + * map_readN - read a range of map data + * @map: map to read + * @offset: start address to read + * @len: length to read + * @buf: pointer of buffer to store data read + * + * Returns: _SUCCESS or _FAIL + */ +int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf) +{ + const struct map_seg_t *seg; + int ret = _FAIL; + int i; + + if (len == 0) { + rtw_warn_on(1); + goto exit; + } + + if (offset + len > map->len) { + rtw_warn_on(1); + goto exit; + } + + _rtw_memset(buf, map->init_value, len); + + for (i = 0; i < map->seg_num; i++) { + u8 *c_dst, *c_src; + u16 c_len; + + seg = map->segs + i; + if (seg->sa + seg->len <= offset || seg->sa >= offset + len) + continue; + + if (seg->sa >= offset) { + c_dst = buf + (seg->sa - offset); + c_src = seg->c; + if (seg->sa + seg->len <= offset + len) + c_len = seg->len; + else + c_len = offset + len - seg->sa; + } else { + c_dst = buf; + c_src = seg->c + (offset - seg->sa); + if (seg->sa + seg->len >= offset + len) + c_len = len; + else + c_len = seg->sa + seg->len - offset; + } + + _rtw_memcpy(c_dst, c_src, c_len); + } + +exit: + return ret; +} + +/** + * map_read8 - read 1 byte of map data + * @map: map to read + * @offset: address to read + * + * Returns: value of data of specified offset. map.init_value if offset is out of range + */ +u8 map_read8(const struct map_t *map, u16 offset) +{ + const struct map_seg_t *seg; + u8 val = map->init_value; + int i; + + if (offset + 1 > map->len) { + rtw_warn_on(1); + goto exit; + } + + for (i = 0; i < map->seg_num; i++) { + seg = map->segs + i; + if (seg->sa + seg->len <= offset || seg->sa >= offset + 1) + continue; + + val = *(seg->c + offset - seg->sa); + break; + } + +exit: + return val; +} + +/** +* is_null - +* +* Return TRUE if c is null character +* FALSE otherwise. +*/ +inline BOOLEAN is_null(char c) +{ + if (c == '\0') + return _TRUE; + else + return _FALSE; +} + +inline BOOLEAN is_all_null(char *c, int len) +{ + for (; len > 0; len--) + if (c[len - 1] != '\0') + return _FALSE; + + return _TRUE; +} + +/** +* is_eol - +* +* Return TRUE if c is represent for EOL (end of line) +* FALSE otherwise. +*/ +inline BOOLEAN is_eol(char c) +{ + if (c == '\r' || c == '\n') + return _TRUE; + else + return _FALSE; +} + +/** +* is_space - +* +* Return TRUE if c is represent for space +* FALSE otherwise. +*/ +inline BOOLEAN is_space(char c) +{ + if (c == ' ' || c == '\t') + return _TRUE; + else + return _FALSE; +} + /** * IsHexDigit - * @@ -2559,8 +2781,8 @@ void rtw_cbuf_free(struct rtw_cbuf *cbuf) inline BOOLEAN IsHexDigit(char chTmp) { if ((chTmp >= '0' && chTmp <= '9') || - (chTmp >= 'a' && chTmp <= 'f') || - (chTmp >= 'A' && chTmp <= 'F')) + (chTmp >= 'a' && chTmp <= 'f') || + (chTmp >= 'A' && chTmp <= 'F')) return _TRUE; else return _FALSE; @@ -2575,7 +2797,7 @@ inline BOOLEAN IsHexDigit(char chTmp) inline BOOLEAN is_alpha(char chTmp) { if ((chTmp >= 'a' && chTmp <= 'z') || - (chTmp >= 'A' && chTmp <= 'Z')) + (chTmp >= 'A' && chTmp <= 'Z')) return _TRUE; else return _FALSE; diff --git a/platform/custom_country_chplan.h b/platform/custom_country_chplan.h index 9d26bf4..f8cc13b 100644 --- a/platform/custom_country_chplan.h +++ b/platform/custom_country_chplan.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,18 +11,12 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #error "You have defined CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP to use a customized map of your own instead of the default one" #error "Before removing these error notifications, please make sure regulatory certification requirements of your target markets" static const struct country_chplan CUSTOMIZED_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0xFF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("TW", 0x76, 1, 0x3FF), /* Taiwan */ }; -static const u16 CUSTOMIZED_country_chplan_map_sz = sizeof(CUSTOMIZED_country_chplan_map) / sizeof(struct country_chplan); diff --git a/platform/platform_ARM_SUN50IW1P1_sdio.c b/platform/platform_ARM_SUN50IW1P1_sdio.c index 327ceec..2586455 100644 --- a/platform/platform_ARM_SUN50IW1P1_sdio.c +++ b/platform/platform_ARM_SUN50IW1P1_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* * Description: * This file can be applied to following platforms: @@ -24,20 +19,20 @@ */ #include #ifdef CONFIG_GPIO_WAKEUP - #include +#include #endif #ifdef CONFIG_MMC - #if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1) - extern void sunxi_mmc_rescan_card(unsigned ids); - extern void sunxi_wlan_set_power(int on); - extern int sunxi_wlan_get_bus_index(void); - extern int sunxi_wlan_get_oob_irq(void); - extern int sunxi_wlan_get_oob_irq_flags(void); - #endif - #ifdef CONFIG_GPIO_WAKEUP - extern unsigned int oob_irq; - #endif +#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1) +extern void sunxi_mmc_rescan_card(unsigned ids); +extern void sunxi_wlan_set_power(int on); +extern int sunxi_wlan_get_bus_index(void); +extern int sunxi_wlan_get_oob_irq(void); +extern int sunxi_wlan_get_oob_irq_flags(void); +#endif +#ifdef CONFIG_GPIO_WAKEUP +extern unsigned int oob_irq; +#endif #endif /* CONFIG_MMC */ /* diff --git a/platform/platform_ARM_SUNnI_sdio.c b/platform/platform_ARM_SUNnI_sdio.c index a21c3db..8a52aa9 100644 --- a/platform/platform_ARM_SUNnI_sdio.c +++ b/platform/platform_ARM_SUNnI_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* * Description: * This file can be applied to following platforms: @@ -27,30 +22,30 @@ #include #include #ifdef CONFIG_GPIO_WAKEUP - #include +#include #endif #ifdef CONFIG_MMC - static int sdc_id = -1; - static signed int gpio_eint_wlan = -1; - static u32 eint_wlan_handle = 0; +static int sdc_id = -1; +static signed int gpio_eint_wlan = -1; +static u32 eint_wlan_handle = 0; - #if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) - extern void sw_mci_rescan_card(unsigned id, unsigned insert); - #elif defined(CONFIG_PLATFORM_ARM_SUN8I) - extern void sunxi_mci_rescan_card(unsigned id, unsigned insert); - #endif +#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) +extern void sw_mci_rescan_card(unsigned id, unsigned insert); +#elif defined(CONFIG_PLATFORM_ARM_SUN8I) +extern void sunxi_mci_rescan_card(unsigned id, unsigned insert); +#endif - #ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1 - extern int get_rf_mod_type(void); - #else - extern int wifi_pm_get_mod_type(void); - #endif +#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1 +extern int get_rf_mod_type(void); +#else +extern int wifi_pm_get_mod_type(void); +#endif - extern void wifi_pm_power(int on); - #ifdef CONFIG_GPIO_WAKEUP - extern unsigned int oob_irq; - #endif +extern void wifi_pm_power(int on); +#ifdef CONFIG_GPIO_WAKEUP +extern unsigned int oob_irq; +#endif #endif /* CONFIG_MMC */ /* diff --git a/platform/platform_ARM_SUNxI_sdio.c b/platform/platform_ARM_SUNxI_sdio.c index 6eed7b1..795b7e7 100644 --- a/platform/platform_ARM_SUNxI_sdio.c +++ b/platform/platform_ARM_SUNxI_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #ifdef CONFIG_MMC_SUNXI_POWER_CONTROL diff --git a/platform/platform_ARM_SUNxI_usb.c b/platform/platform_ARM_SUNxI_usb.c index 76bce9b..9c2abc4 100644 --- a/platform/platform_ARM_SUNxI_usb.c +++ b/platform/platform_ARM_SUNxI_usb.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* * Description: * This file can be applied to following platforms: @@ -28,23 +23,23 @@ #include #ifdef CONFIG_PLATFORM_ARM_SUNxI - extern int sw_usb_disable_hcd(__u32 usbc_no); - extern int sw_usb_enable_hcd(__u32 usbc_no); - static int usb_wifi_host = 2; +extern int sw_usb_disable_hcd(__u32 usbc_no); +extern int sw_usb_enable_hcd(__u32 usbc_no); +static int usb_wifi_host = 2; #endif #if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) - extern int sw_usb_disable_hcd(__u32 usbc_no); - extern int sw_usb_enable_hcd(__u32 usbc_no); - extern void wifi_pm_power(int on); - static script_item_u item; +extern int sw_usb_disable_hcd(__u32 usbc_no); +extern int sw_usb_enable_hcd(__u32 usbc_no); +extern void wifi_pm_power(int on); +static script_item_u item; #endif #ifdef CONFIG_PLATFORM_ARM_SUN8I - extern int sunxi_usb_disable_hcd(__u32 usbc_no); - extern int sunxi_usb_enable_hcd(__u32 usbc_no); - extern void wifi_pm_power(int on); - static script_item_u item; +extern int sunxi_usb_disable_hcd(__u32 usbc_no); +extern int sunxi_usb_enable_hcd(__u32 usbc_no); +extern void wifi_pm_power(int on); +static script_item_u item; #endif @@ -125,16 +120,16 @@ void platform_wifi_power_off(void) #endif /* CONFIG_PLATFORM_ARM_SUNxI */ #if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) -#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B)) + #if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B)) sw_usb_disable_hcd(item.val); -#endif + #endif wifi_pm_power(0); #endif /* defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) */ #if defined(CONFIG_PLATFORM_ARM_SUN8I) -#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B)) + #if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B)) sunxi_usb_disable_hcd(item.val); -#endif + #endif wifi_pm_power(0); #endif /* defined(CONFIG_PLATFORM_ARM_SUN8I) */ diff --git a/platform/platform_ARM_WMT_sdio.c b/platform/platform_ARM_WMT_sdio.c index 159a5ac..d85002c 100644 --- a/platform/platform_ARM_WMT_sdio.c +++ b/platform/platform_ARM_WMT_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #include #include diff --git a/platform/platform_RTK_DMP_usb.c b/platform/platform_RTK_DMP_usb.c index af845f7..cb740b2 100644 --- a/platform/platform_RTK_DMP_usb.c +++ b/platform/platform_RTK_DMP_usb.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include int platform_wifi_power_on(void) diff --git a/platform/platform_arm_act_sdio.c b/platform/platform_arm_act_sdio.c index 031de54..ad7b6cf 100644 --- a/platform/platform_arm_act_sdio.c +++ b/platform/platform_arm_act_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* * Description: * This file can be applied to following platforms: @@ -25,8 +20,8 @@ #include #ifdef CONFIG_PLATFORM_ACTIONS_ATM705X - extern int acts_wifi_init(void); - extern void acts_wifi_cleanup(void); +extern int acts_wifi_init(void); +extern void acts_wifi_cleanup(void); #endif /* diff --git a/platform/platform_ops.c b/platform/platform_ops.c index 95da669..10766aa 100644 --- a/platform/platform_ops.c +++ b/platform/platform_ops.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef CONFIG_PLATFORM_OPS /* * Return: diff --git a/platform/platform_ops.h b/platform/platform_ops.h index b8314bb..12caf3c 100644 --- a/platform/platform_ops.h +++ b/platform/platform_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PLATFORM_OPS_H__ #define __PLATFORM_OPS_H__ diff --git a/platform/platform_sprd_sdio.c b/platform/platform_sprd_sdio.c index 05fd123..34061d0 100644 --- a/platform/platform_sprd_sdio.c +++ b/platform/platform_sprd_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,17 +11,12 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include extern void sdhci_bus_scan(void); #ifndef ANDROID_2X - extern int sdhci_device_attached(void); +extern int sdhci_device_attached(void); #endif /* diff --git a/rtl8822b.mk b/rtl8822b.mk index 5742f1c..f935b6c 100644 --- a/rtl8822b.mk +++ b/rtl8822b.mk @@ -2,13 +2,17 @@ RTL871X := rtl8822b EXTRA_CFLAGS += -DCONFIG_RTL8822B ifeq ($(CONFIG_USB_HCI), y) -MODULE_NAME = 8822bu +ifeq ($(CONFIG_BT_COEXIST), n) +MODULE_NAME = 8812bu +else +MODULE_NAME = 88x2bu +endif endif ifeq ($(CONFIG_PCI_HCI), y) -MODULE_NAME = 8822be +MODULE_NAME = 88x2be endif ifeq ($(CONFIG_SDIO_HCI), y) -MODULE_NAME = 8822bs +MODULE_NAME = 88x2bs endif ifeq ($(CONFIG_MP_INCLUDED), y) @@ -20,17 +24,20 @@ endif _HAL_HALMAC_FILES += hal/halmac/halmac_api.o _HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_api_88xx.o \ - hal/halmac/halmac_88xx/halmac_func_88xx.o \ hal/halmac/halmac_88xx/halmac_api_88xx_usb.o \ hal/halmac/halmac_88xx/halmac_api_88xx_sdio.o \ - hal/halmac/halmac_88xx/halmac_api_88xx_pcie.o + hal/halmac/halmac_88xx/halmac_api_88xx_pcie.o \ + hal/halmac/halmac_88xx/halmac_func_88xx.o \ + hal/halmac/halmac_88xx/halmac_gpio_88xx.o -_HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.o \ +_HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.o \ + hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.o \ hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.o \ + hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.o \ hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.o + hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.o \ + hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.o \ + hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.o _HAL_INTFS_FILES += hal/hal_halmac.o @@ -38,34 +45,41 @@ _HAL_INTFS_FILES += hal/rtl8822b/rtl8822b_halinit.o \ hal/rtl8822b/rtl8822b_mac.o \ hal/rtl8822b/rtl8822b_cmd.o \ hal/rtl8822b/rtl8822b_phy.o \ - hal/rtl8822b/rtl8822b_ops.o - -_HAL_INTFS_FILES += hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_halinit.o \ - hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_halmac.o \ - hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_io.o \ - hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \ - hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o \ - hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \ - hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_ops.o + hal/rtl8822b/rtl8822b_ops.o \ + hal/rtl8822b/hal8822b_fw.o ifeq ($(CONFIG_USB_HCI), y) -_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8822B_USB.o +_HAL_INTFS_FILES += hal/rtl8822b/$(HCI_NAME)/rtl8822bu_halinit.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822bu_halmac.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822bu_io.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822bu_xmit.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822bu_recv.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822bu_led.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822bu_ops.o + +_HAL_INTFS_FILES +=hal/efuse/rtl8822b/HalEfuseMask8822B_USB.o endif ifeq ($(CONFIG_PCI_HCI), y) -_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8822B_PCIE.o +_HAL_INTFS_FILES += hal/rtl8822b/$(HCI_NAME)/rtl8822be_halinit.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822be_halmac.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822be_io.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822be_xmit.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822be_recv.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822be_led.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822be_ops.o + +_HAL_INTFS_FILES +=hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.o endif ifeq ($(CONFIG_SDIO_HCI), y) -#_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8822B_SDIO.o -endif +_HAL_INTFS_FILES += hal/rtl8822b/$(HCI_NAME)/rtl8822bs_halinit.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822bs_halmac.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822bs_io.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822bs_xmit.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822bs_recv.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822bs_led.o \ + hal/rtl8822b/$(HCI_NAME)/rtl8822bs_ops.o -_OUTSRC_FILES += hal/phydm/rtl8822b/halhwimg8822b_bb.o \ - hal/phydm/rtl8822b/halhwimg8822b_fw.o \ - hal/phydm/rtl8822b/halhwimg8822b_mac.o \ - hal/phydm/rtl8822b/halhwimg8822b_rf.o \ - hal/phydm/rtl8822b/halphyrf_8822b.o \ - hal/phydm/rtl8822b/phydm_hal_api8822b.o \ - hal/phydm/rtl8822b/phydm_iqk_8822b.o \ - hal/phydm/rtl8822b/phydm_regconfig8822b.o \ - hal/phydm/rtl8822b/phydm_rtl8822b.o +_HAL_INTFS_FILES +=hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.o +endif -_HAL_INTFS_FILES += $(_HAL_HALMAC_FILES) +_HAL_INTFS_FILES += $(_HAL_HALMAC_FILES) \ No newline at end of file From 92223543489bf9cc41152a5b012b75f6af472a01 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Thu, 8 Feb 2018 20:22:19 +0200 Subject: [PATCH 07/48] new files for latest driver --- core/rtw_btcoex_wifionly.c | 37 + hal/btc/halbtc8192e1ant.c | 3431 ++ hal/btc/halbtc8192e1ant.h | 240 + hal/btc/halbtc8192e2ant.c | 4391 ++ hal/btc/halbtc8192e2ant.h | 225 + hal/btc/halbtc8703b1ant.c | 4307 ++ hal/btc/halbtc8703b1ant.h | 418 + hal/btc/halbtc8723b1ant.c | 5127 +++ hal/btc/halbtc8723b1ant.h | 307 + hal/btc/halbtc8723b2ant.c | 4972 +++ hal/btc/halbtc8723b2ant.h | 231 + hal/btc/halbtc8723bwifionly.c | 82 + hal/btc/halbtc8723bwifionly.h | 22 + hal/btc/halbtc8812a1ant.c | 3475 ++ hal/btc/halbtc8812a1ant.h | 244 + hal/btc/halbtc8812a2ant.c | 5638 +++ hal/btc/halbtc8812a2ant.h | 241 + hal/btc/halbtc8821a1ant.c | 3303 ++ hal/btc/halbtc8821a1ant.h | 228 + hal/btc/halbtc8821a2ant.c | 4651 ++ hal/btc/halbtc8821a2ant.h | 225 + hal/btc/halbtc8821c1ant.c | 5357 +++ hal/btc/halbtc8821c1ant.h | 497 + hal/btc/halbtc8821c2ant.c | 5965 +++ hal/btc/halbtc8821c2ant.h | 504 + hal/btc/halbtc8821cwifionly.c | 200 + hal/btc/halbtc8821cwifionly.h | 84 + hal/btc/halbtc8822b1ant.c | 7130 ++++ hal/btc/halbtc8822b1ant.h | 480 + hal/btc/halbtc8822b2ant.c | 6112 +++ hal/btc/halbtc8822b2ant.h | 526 + hal/btc/halbtc8822bwifionly.c | 68 + hal/btc/halbtc8822bwifionly.h | 36 + hal/btc/halbtcoutsrc.h | 1030 + hal/btc/mp_precomp.h | 85 + hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.c | 100 + hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.h | 27 + hal/hal_btcoex_wifionly.c | 170 + .../halmac_8822b/halmac_8822b_phy.c | 73 + .../halmac_8822b/halmac_gpio_8822b.c | 559 + .../halmac_8822b/halmac_gpio_8822b.h | 168 + hal/halmac/halmac_88xx/halmac_gpio_88xx.c | 453 + hal/halmac/halmac_88xx/halmac_gpio_88xx.h | 86 + hal/halmac/halmac_bit_8197f.h | 13080 ++++++ hal/halmac/halmac_bit_8814b.h | 11725 +++++ hal/halmac/halmac_gpio_cmd.h | 84 + hal/halmac/halmac_intf_phy_cmd.h | 45 + hal/halmac/halmac_reg_8197f.h | 697 + hal/halmac/halmac_reg_8814b.h | 751 + hal/phydm/ap_makefile.mk | 109 + hal/phydm/halrf/halphyrf_ap.c | 1369 + hal/phydm/halrf/halphyrf_ap.h | 127 + hal/phydm/halrf/halphyrf_ce.c | 914 + hal/phydm/halrf/halphyrf_ce.h | 119 + hal/phydm/halrf/halphyrf_win.c | 827 + hal/phydm/halrf/halphyrf_win.h | 118 + hal/phydm/halrf/halrf.c | 291 + hal/phydm/halrf/halrf.h | 125 + hal/phydm/halrf/halrf_features.h | 38 + hal/phydm/halrf/halrf_iqk.h | 65 + hal/phydm/halrf/halrf_kfree.c | 716 + hal/phydm/halrf/halrf_kfree.h | 123 + hal/phydm/halrf/halrf_powertracking_ap.c | 1166 + hal/phydm/halrf/halrf_powertracking_ap.h | 355 + hal/phydm/halrf/halrf_powertracking_ce.c | 762 + hal/phydm/halrf/halrf_powertracking_ce.h | 347 + hal/phydm/halrf/halrf_powertracking_win.c | 811 + hal/phydm/halrf/halrf_powertracking_win.h | 310 + hal/phydm/halrf/rtl8822b/halrf_8822b.c | 590 + hal/phydm/halrf/rtl8822b/halrf_8822b.h | 80 + hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c | 1483 + hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h | 68 + hal/phydm/phydm.mk | 157 + hal/phydm/phydm_dynamic_rx_path.c | 352 + hal/phydm/phydm_dynamic_rx_path.h | 141 + hal/phydm/phydm_psd.c | 439 + hal/phydm/phydm_psd.h | 96 + hal/phydm/rtl8822b/mp_precomp.h | 19 + hal/phydm/rtl8822b/phydm_rtl8822b_ram.c | 7 + hal/phydm/rtl8822b/phydm_rtl8822b_ram.h | 34 + hal/rtl8822b/hal8822b_fw.c | 35364 ++++++++++++++++ hal/rtl8822b/hal8822b_fw.h | 38 + include/.osdep_service_linux.h.swp | Bin 0 -> 16384 bytes include/hal_btcoex_wifionly.h | 61 + include/rtl8821c_dm.h | 25 + include/rtl8821c_spec.h | 192 + include/rtl8821ce_hal.h | 23 + include/rtw_btcoex_wifionly.h | 22 + 88 files changed, 145770 insertions(+) create mode 100644 core/rtw_btcoex_wifionly.c create mode 100644 hal/btc/halbtc8192e1ant.c create mode 100644 hal/btc/halbtc8192e1ant.h create mode 100644 hal/btc/halbtc8192e2ant.c create mode 100644 hal/btc/halbtc8192e2ant.h create mode 100644 hal/btc/halbtc8703b1ant.c create mode 100644 hal/btc/halbtc8703b1ant.h create mode 100644 hal/btc/halbtc8723b1ant.c create mode 100644 hal/btc/halbtc8723b1ant.h create mode 100644 hal/btc/halbtc8723b2ant.c create mode 100644 hal/btc/halbtc8723b2ant.h create mode 100644 hal/btc/halbtc8723bwifionly.c create mode 100644 hal/btc/halbtc8723bwifionly.h create mode 100644 hal/btc/halbtc8812a1ant.c create mode 100644 hal/btc/halbtc8812a1ant.h create mode 100644 hal/btc/halbtc8812a2ant.c create mode 100644 hal/btc/halbtc8812a2ant.h create mode 100644 hal/btc/halbtc8821a1ant.c create mode 100644 hal/btc/halbtc8821a1ant.h create mode 100644 hal/btc/halbtc8821a2ant.c create mode 100644 hal/btc/halbtc8821a2ant.h create mode 100644 hal/btc/halbtc8821c1ant.c create mode 100644 hal/btc/halbtc8821c1ant.h create mode 100644 hal/btc/halbtc8821c2ant.c create mode 100644 hal/btc/halbtc8821c2ant.h create mode 100644 hal/btc/halbtc8821cwifionly.c create mode 100644 hal/btc/halbtc8821cwifionly.h create mode 100644 hal/btc/halbtc8822b1ant.c create mode 100644 hal/btc/halbtc8822b1ant.h create mode 100644 hal/btc/halbtc8822b2ant.c create mode 100644 hal/btc/halbtc8822b2ant.h create mode 100644 hal/btc/halbtc8822bwifionly.c create mode 100644 hal/btc/halbtc8822bwifionly.h create mode 100644 hal/btc/halbtcoutsrc.h create mode 100644 hal/btc/mp_precomp.h create mode 100644 hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.c create mode 100644 hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.h create mode 100644 hal/hal_btcoex_wifionly.c create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.c create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h create mode 100644 hal/halmac/halmac_88xx/halmac_gpio_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_gpio_88xx.h create mode 100644 hal/halmac/halmac_bit_8197f.h create mode 100644 hal/halmac/halmac_bit_8814b.h create mode 100644 hal/halmac/halmac_gpio_cmd.h create mode 100644 hal/halmac/halmac_intf_phy_cmd.h create mode 100644 hal/halmac/halmac_reg_8197f.h create mode 100644 hal/halmac/halmac_reg_8814b.h create mode 100644 hal/phydm/ap_makefile.mk create mode 100644 hal/phydm/halrf/halphyrf_ap.c create mode 100644 hal/phydm/halrf/halphyrf_ap.h create mode 100644 hal/phydm/halrf/halphyrf_ce.c create mode 100644 hal/phydm/halrf/halphyrf_ce.h create mode 100644 hal/phydm/halrf/halphyrf_win.c create mode 100644 hal/phydm/halrf/halphyrf_win.h create mode 100644 hal/phydm/halrf/halrf.c create mode 100644 hal/phydm/halrf/halrf.h create mode 100644 hal/phydm/halrf/halrf_features.h create mode 100644 hal/phydm/halrf/halrf_iqk.h create mode 100644 hal/phydm/halrf/halrf_kfree.c create mode 100644 hal/phydm/halrf/halrf_kfree.h create mode 100644 hal/phydm/halrf/halrf_powertracking_ap.c create mode 100644 hal/phydm/halrf/halrf_powertracking_ap.h create mode 100644 hal/phydm/halrf/halrf_powertracking_ce.c create mode 100644 hal/phydm/halrf/halrf_powertracking_ce.h create mode 100644 hal/phydm/halrf/halrf_powertracking_win.c create mode 100644 hal/phydm/halrf/halrf_powertracking_win.h create mode 100644 hal/phydm/halrf/rtl8822b/halrf_8822b.c create mode 100644 hal/phydm/halrf/rtl8822b/halrf_8822b.h create mode 100644 hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c create mode 100644 hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h create mode 100644 hal/phydm/phydm.mk create mode 100644 hal/phydm/phydm_dynamic_rx_path.c create mode 100644 hal/phydm/phydm_dynamic_rx_path.h create mode 100644 hal/phydm/phydm_psd.c create mode 100644 hal/phydm/phydm_psd.h create mode 100644 hal/phydm/rtl8822b/mp_precomp.h create mode 100644 hal/phydm/rtl8822b/phydm_rtl8822b_ram.c create mode 100644 hal/phydm/rtl8822b/phydm_rtl8822b_ram.h create mode 100644 hal/rtl8822b/hal8822b_fw.c create mode 100644 hal/rtl8822b/hal8822b_fw.h create mode 100644 include/.osdep_service_linux.h.swp create mode 100644 include/hal_btcoex_wifionly.h create mode 100644 include/rtl8821c_dm.h create mode 100644 include/rtl8821c_spec.h create mode 100644 include/rtl8821ce_hal.h create mode 100644 include/rtw_btcoex_wifionly.h diff --git a/core/rtw_btcoex_wifionly.c b/core/rtw_btcoex_wifionly.c new file mode 100644 index 0000000..f7d70aa --- /dev/null +++ b/core/rtw_btcoex_wifionly.c @@ -0,0 +1,37 @@ +/****************************************************************************** + * + * Copyright(c) 2013 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include +#include +#include + +void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter) +{ + hal_btcoex_wifionly_switchband_notify(padapter); +} + +void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter) +{ + hal_btcoex_wifionly_scan_notify(padapter); +} + +void rtw_btcoex_wifionly_hw_config(PADAPTER padapter) +{ + hal_btcoex_wifionly_hw_config(padapter); +} + +void rtw_btcoex_wifionly_initialize(PADAPTER padapter) +{ + hal_btcoex_wifionly_initlizevariables(padapter); +} diff --git a/hal/btc/halbtc8192e1ant.c b/hal/btc/halbtc8192e1ant.c new file mode 100644 index 0000000..1c60239 --- /dev/null +++ b/hal/btc/halbtc8192e1ant.c @@ -0,0 +1,3431 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for RTL8192E Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8192E_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8192e_1ant glcoex_dm_8192e_1ant; +static struct coex_dm_8192e_1ant *coex_dm = &glcoex_dm_8192e_1ant; +static struct coex_sta_8192e_1ant glcoex_sta_8192e_1ant; +static struct coex_sta_8192e_1ant *coex_sta = &glcoex_sta_8192e_1ant; + +const char *const glbt_info_src_8192e_1ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u32 glcoex_ver_date_8192e_1ant = 20140527; +u32 glcoex_ver_8192e_1ant = 0x4f; + +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8192e1ant_ + * ************************************************************ */ +u8 halbtc8192e1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_bt_rssi_state; + } + + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + +u8 halbtc8192e1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_wifi_rssi_state[index]; + } + + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; + + return wifi_rssi_state; +} + +void halbtc8192e1ant_update_ra_mask(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 dis_rate_mask) +{ + coex_dm->cur_ra_mask = dis_rate_mask; + + if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) + btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, + &coex_dm->cur_ra_mask); + coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; +} + +void halbtc8192e1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + boolean wifi_under_b_mode = false; + + coex_dm->cur_arfr_type = type; + + if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { + switch (coex_dm->cur_arfr_type) { + case 0: /* normal mode */ + btcoexist->btc_write_4byte(btcoexist, 0x430, + coex_dm->backup_arfr_cnt1); + btcoexist->btc_write_4byte(btcoexist, 0x434, + coex_dm->backup_arfr_cnt2); + break; + case 1: + btcoexist->btc_get(btcoexist, + BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + if (wifi_under_b_mode) { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x01010101); + } else { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x04030201); + } + break; + default: + break; + } + } + + coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; +} + +void halbtc8192e1ant_retry_limit(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_retry_limit_type = type; + + if (force_exec || + (coex_dm->pre_retry_limit_type != + coex_dm->cur_retry_limit_type)) { + switch (coex_dm->cur_retry_limit_type) { + case 0: /* normal mode */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + coex_dm->backup_retry_limit); + break; + case 1: /* retry limit=8 */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + 0x0808); + break; + default: + break; + } + } + + coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; +} + +void halbtc8192e1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_ampdu_time_type = type; + + if (force_exec || + (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { + switch (coex_dm->cur_ampdu_time_type) { + case 0: /* normal mode */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + coex_dm->backup_ampdu_max_time); + break; + case 1: /* AMPDU timw = 0x38 * 32us */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + 0x38); + break; + default: + break; + } + } + + coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; +} + +void halbtc8192e1ant_limited_tx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, + IN u8 retry_limit_type, IN u8 ampdu_time_type) +{ + switch (ra_mask_type) { + case 0: /* normal mode */ + halbtc8192e1ant_update_ra_mask(btcoexist, force_exec, + 0x0); + break; + case 1: /* disable cck 1/2 */ + halbtc8192e1ant_update_ra_mask(btcoexist, force_exec, + 0x00000003); + break; + case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ + halbtc8192e1ant_update_ra_mask(btcoexist, force_exec, + 0x0001f1f7); + break; + default: + break; + } + + halbtc8192e1ant_auto_rate_fallback_retry(btcoexist, force_exec, + arfr_type); + halbtc8192e1ant_retry_limit(btcoexist, force_exec, retry_limit_type); + halbtc8192e1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); +} + +void halbtc8192e1ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +void halbtc8192e1ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + coex_sta->c2h_bt_info_req_sent = true; + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); +} + +void halbtc8192e1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u8 num_of_bt_counter_chk = 0; + + /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ + /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ + + if (coex_sta->under_ips) { + coex_sta->high_priority_tx = 65535; + coex_sta->high_priority_rx = 65535; + coex_sta->low_priority_tx = 65535; + coex_sta->low_priority_rx = 65535; + return; + } + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + if ((coex_sta->low_priority_tx >= 1050) && + (!coex_sta->c2h_bt_inquiry_page)) + coex_sta->pop_event_cnt++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); + BTC_TRACE(trace_buf); + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + + if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) && + (reg_lp_rx == 0)) { + num_of_bt_counter_chk++; + if (num_of_bt_counter_chk >= 3) { + halbtc8192e1ant_query_bt_info(btcoexist); + num_of_bt_counter_chk = 0; + } + } +} + + +void halbtc8192e1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ + s32 wifi_rssi = 0; + boolean wifi_busy = false, wifi_under_b_mode = false; + static u8 cck_lock_counter = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + if (coex_sta->under_ips) { + coex_sta->crc_ok_cck = 0; + coex_sta->crc_ok_11g = 0; + coex_sta->crc_ok_11n = 0; + coex_sta->crc_ok_11n_agg = 0; + + coex_sta->crc_err_cck = 0; + coex_sta->crc_err_11g = 0; + coex_sta->crc_err_11n = 0; + coex_sta->crc_err_11n_agg = 0; + } else { + coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist, + 0xf88); + coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, + 0xf94); + coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, + 0xf90); + coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, + 0xfb8); + + coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist, + 0xf84); + coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, + 0xf96); + coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, + 0xf92); + coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, + 0xfba); + } + + + /* reset counter */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0); + + if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { + if ((coex_dm->bt_status == BT_8192E_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == + BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (coex_dm->bt_status == + BT_8192E_1ANT_BT_STATUS_SCO_BUSY)) { + if (coex_sta->crc_ok_cck > (coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + + coex_sta->crc_ok_11n_agg)) { + if (cck_lock_counter < 5) + cck_lock_counter++; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + if (!coex_sta->pre_ccklock) { + + if (cck_lock_counter >= 5) + coex_sta->cck_lock = true; + else + coex_sta->cck_lock = false; + } else { + if (cck_lock_counter == 0) + coex_sta->cck_lock = false; + else + coex_sta->cck_lock = true; + } + + coex_sta->pre_ccklock = coex_sta->cck_lock; + + +} + +boolean halbtc8192e1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) +{ + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + } + + return false; +} + +void halbtc8192e1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = true; + bt_link_info->bt_link_exist = true; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = true; + else + bt_link_info->sco_only = false; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = true; + else + bt_link_info->a2dp_only = false; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = true; + else + bt_link_info->pan_only = false; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = true; + else + bt_link_info->hid_only = false; +} + +u8 halbtc8192e1ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + u8 algorithm = BT_8192E_1ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_1ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +void halbtc8192e1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean enable_auto_report) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = 0; + + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); + + btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); +} + +void halbtc8192e1ant_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable_auto_report) +{ + coex_dm->cur_bt_auto_report = enable_auto_report; + + if (!force_exec) { + if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) + return; + } + halbtc8192e1ant_set_bt_auto_report(btcoexist, + coex_dm->cur_bt_auto_report); + + coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; +} + +void halbtc8192e1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist + *btcoexist, IN boolean low_penalty_ra) +{ + u8 h2c_parameter[6] = {0}; + + h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ + + if (low_penalty_ra) { + h2c_parameter[1] |= BIT(0); + h2c_parameter[2] = + 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ + h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ + h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ + h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ + } + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); +} + +void halbtc8192e1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) + return; + } + halbtc8192e1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, + coex_dm->cur_low_penalty_ra); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; +} + +void halbtc8192e1ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8192e1ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8192e1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8192e1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** CoexTable(%d) **********\n", type); + BTC_TRACE(trace_buf); + + coex_sta->coex_table_type = type; + + switch (type) { + case 0: + halbtc8192e1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8192e1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 2: + halbtc8192e1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 3: + halbtc8192e1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 4: + halbtc8192e1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); + break; + case 5: + halbtc8192e1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0xaa5a5a5a, 0xffffff, 0x3); + break; + case 6: + halbtc8192e1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 7: + halbtc8192e1ant_coex_table(btcoexist, force_exec, + 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + default: + break; + } +} + +void halbtc8192e1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 h2c_parameter[1] = {0}; + + if (enable) + h2c_parameter[0] |= BIT(0); /* function enable */ + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + +void halbtc8192e1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8192e1ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8192e1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8192e1ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8192e1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8192e1ant_sw_mechanism(IN struct btc_coexist *btcoexist, + IN boolean low_penalty_ra) +{ + halbtc8192e1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); +} + +void halbtc8192e1ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) +{ + u32 u32tmp = 0; + + if (init_hwcfg) { + btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24); + btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700); + if (btcoexist->chip_interface == BTC_INTF_USB) + btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); + else + btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); + + /* 0x4c[27][24]='00', Set Antenna to BB */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp &= ~BIT(24); + u32tmp &= ~BIT(27); + btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); + } else if (wifi_off) { + if (btcoexist->chip_interface == BTC_INTF_USB) + btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); + else + btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); + + /* 0x4c[27][24]='11', Set Antenna to BT, 0x64[8:7]=0, 0x64[2]=1 */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp |= BIT(24); + u32tmp |= BIT(27); + btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); + } + + /* ext switch setting */ + switch (ant_pos_type) { + case BTC_ANT_PATH_WIFI: + btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); + break; + case BTC_ANT_PATH_BT: + btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20); + break; + default: + case BTC_ANT_PATH_PTA: + btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); + break; + } +} + +void halbtc8192e1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if (ap_enable) { + if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], FW for 1Ant AP mode\n"); + BTC_TRACE(trace_buf); + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + } + } + + h2c_parameter[0] = real_byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = real_byte5; + + coex_dm->ps_tdma_para[0] = real_byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = real_byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); +} + + +void halbtc8192e1ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = false; + u8 rssi_adjust_val = 0; + u8 ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51, + ps_tdma_byte3_val = 0x10; + s8 wifi_duration_adjust = 0x0; + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (coex_dm->cur_ps_tdma_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(on, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) + return; + } + + if (coex_sta->scan_ap_num <= 5) + wifi_duration_adjust = 5; + else if (coex_sta->scan_ap_num >= 40) + wifi_duration_adjust = -15; + else if (coex_sta->scan_ap_num >= 20) + wifi_duration_adjust = -10; + + if (!coex_sta->force_lps_on) { /* only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */ + ps_tdma_byte0_val = 0x61; /* no null-pkt */ + ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */ + ps_tdma_byte4_val = 0x10; /* 0x778 = d/1 toggle */ + } + + if ((type == 3) || (type == 13) || (type == 14)) + ps_tdma_byte4_val = ps_tdma_byte4_val & + 0xbf; /* no dynamic slot for multi-profile */ + + if (bt_link_info->slave_role == true) + ps_tdma_byte4_val = ps_tdma_byte4_val | + 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ + + if (turn_on) { + switch (type) { + default: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, + 0x1a, 0x1a, 0x0, ps_tdma_byte4_val); + break; + case 1: + halbtc8192e1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x3a + + wifi_duration_adjust, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 2: + halbtc8192e1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x2d + + wifi_duration_adjust, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 3: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, + 0x1d, 0x1d, 0x0, ps_tdma_byte4_val); + break; + case 4: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93, + 0x15, 0x3, 0x14, 0x0); + break; + case 5: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, + 0x15, 0x3, 0x11, 0x11); + break; + case 6: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, + 0x20, 0x3, 0x11, 0x11); + break; + case 7: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13, + 0xc, 0x5, 0x0, 0x0); + break; + case 8: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93, + 0x25, 0x3, 0x10, 0x0); + break; + case 9: + halbtc8192e1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x21, 0x3, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 10: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13, + 0xa, 0xa, 0x0, 0x40); + break; + case 11: + halbtc8192e1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x21, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 12: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, + 0x0a, 0x0a, 0x0, 0x50); + break; + case 13: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, + 0x12, 0x12, 0x0, ps_tdma_byte4_val); + break; + case 14: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, + 0x21, 0x3, 0x10, ps_tdma_byte4_val); + break; + case 15: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13, + 0xa, 0x3, 0x8, 0x0); + break; + case 16: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93, + 0x15, 0x3, 0x10, 0x0); + break; + case 18: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93, + 0x25, 0x3, 0x10, 0x0); + break; + case 20: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, + 0x3f, 0x03, 0x11, 0x10); + break; + case 21: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, 0x11); + break; + case 22: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, 0x10); + break; + case 23: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x3, 0x31, 0x18); + break; + case 24: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, + 0x15, 0x3, 0x31, 0x18); + break; + case 25: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, + 0xa, 0x3, 0x31, 0x18); + break; + case 26: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, + 0xa, 0x3, 0x31, 0x18); + break; + case 27: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x3, 0x31, 0x98); + break; + case 28: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x69, + 0x25, 0x3, 0x31, 0x0); + break; + case 29: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xab, + 0x1a, 0x1a, 0x1, 0x10); + break; + case 30: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, 0x10); + break; + case 31: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xd3, + 0x1a, 0x1a, 0, 0x58); + break; + case 32: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x3, 0x11, 0x11); + break; + case 33: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xa3, + 0x25, 0x3, 0x30, 0x90); + break; + case 34: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x53, + 0x1a, 0x1a, 0x0, 0x10); + break; + case 35: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x63, + 0x1a, 0x1a, 0x0, 0x10); + break; + case 36: + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xd3, + 0x12, 0x3, 0x14, 0x50); + break; + case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */ + /* here softap mode screen off will cost 70-80mA for phone */ + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x23, + 0x18, 0x00, 0x10, 0x24); + break; + } + } else { + + /* disable PS tdma */ + switch (type) { + case 8: /* PTA Control */ + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x8, + 0x0, 0x0, 0x0, 0x0); + halbtc8192e1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_PTA, false, false); + break; + case 0: + default: /* Software control, Antenna at BT side */ + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x0, 0x0); + halbtc8192e1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_BT, false, false); + break; + case 9: /* Software control, Antenna at WiFi side */ + halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x0, 0x0); + halbtc8192e1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_WIFI, false, false); + break; + } + } + rssi_adjust_val = 0; + btcoexist->btc_set(btcoexist, + BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val); + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", + btcoexist->btc_read_4byte(btcoexist, 0x948), + btcoexist->btc_read_1byte(btcoexist, 0x765), + btcoexist->btc_read_1byte(btcoexist, 0x67)); + BTC_TRACE(trace_buf); + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; +} + +void halbtc8192e1ant_coex_all_off(IN struct btc_coexist *btcoexist) +{ + /* sw all off */ + halbtc8192e1ant_sw_mechanism(btcoexist, false); + + /* hw all off */ + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +boolean halbtc8192e1ant_is_common_action(IN struct btc_coexist *btcoexist) +{ + boolean common = false, wifi_connected = false, wifi_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_connected && + BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ + + common = true; + } else if (wifi_connected && + (BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ + + common = true; + } else if (!wifi_connected && + (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ + + common = true; + } else if (wifi_connected && + (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ + + common = true; + } else if (!wifi_connected && + (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ + + common = true; + } else { + if (wifi_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } + + common = false; + } + + return common; +} + + +void halbtc8192e1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist + *btcoexist, IN u8 wifi_status) +{ + static s32 up, dn, m, n, wait_count; + s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ + u8 retry_count = 0, bt_info_ext; + boolean wifi_busy = false; + /*static boolean pre_wifi_busy = false;*/ + + if (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status) + wifi_busy = true; + else + wifi_busy = false; + + if ((BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == + wifi_status) || + (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) || + (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT == + wifi_status)) { + if (coex_dm->cur_ps_tdma != 1 && + coex_dm->cur_ps_tdma != 2 && + coex_dm->cur_ps_tdma != 3 && + coex_dm->cur_ps_tdma != 9) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 9); + coex_dm->ps_tdma_du_adj_type = 9; + + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } + return; + } + + if (!coex_dm->auto_tdma_adjust) { + coex_dm->auto_tdma_adjust = true; + + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + /* ============ */ + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } else { + /* acquire the BT TRx retry count from BT_Info byte2 */ + retry_count = coex_sta->bt_retry_cnt; + bt_info_ext = coex_sta->bt_info_ext; + + if ((coex_sta->low_priority_tx) > 1050 || + (coex_sta->low_priority_rx) > 1250) + retry_count++; + + result = 0; + wait_count++; + + if (retry_count == + 0) { /* no retry in the last 2-second duration */ + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ + wait_count = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + } + } else if (retry_count <= + 3) { /* <=3 retry in the last 2-second duration */ + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ + if (wait_count <= 2) + m++; /* to avoid loop between the two levels */ + else + m = 1; + + if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ + if (wait_count == 1) + m++; /* to avoid loop between the two levels */ + else + m = 1; + + if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + + if (result == -1) { + if ((BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && + ((coex_dm->cur_ps_tdma == 1) || + (coex_dm->cur_ps_tdma == 2))) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 1) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } + } else if (result == 1) { + if ((BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && + ((coex_dm->cur_ps_tdma == 1) || + (coex_dm->cur_ps_tdma == 2))) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = 1; + } + } else { /* no change */ + /* Bryant Modify + if(wifi_busy != pre_wifi_busy) + { + pre_wifi_busy = wifi_busy; + halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma); + } + */ + } + + if (coex_dm->cur_ps_tdma != 1 && + coex_dm->cur_ps_tdma != 2 && + coex_dm->cur_ps_tdma != 9 && + coex_dm->cur_ps_tdma != 11) { + /* recover to previous adjust type */ + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + coex_dm->ps_tdma_du_adj_type); + } + } +} + +void halbtc8192e1ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + +void halbtc8192e1ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = false; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + /* recover to original 32k low power setting */ + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + case BTC_PS_LPS_ON: + halbtc8192e1ant_ps_tdma_check_for_power_save_state( + btcoexist, true); + halbtc8192e1ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + coex_sta->force_lps_on = true; + break; + case BTC_PS_LPS_OFF: + halbtc8192e1ant_ps_tdma_check_for_power_save_state( + btcoexist, false); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + default: + break; + } +} + +void halbtc8192e1ant_action_wifi_only(IN struct btc_coexist *btcoexist) +{ + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 9); +} + +void halbtc8192e1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = true, bt_disabled = false; + + /* This function check if bt is disabled */ + + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = false; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = false; + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + BTC_TRACE(trace_buf); + } else { + bt_disable_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt all counters=0, %d times!!\n", + bt_disable_cnt); + BTC_TRACE(trace_buf); + if (bt_disable_cnt >= 2) { + bt_disabled = true; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + BTC_TRACE(trace_buf); + halbtc8192e1ant_action_wifi_only(btcoexist); + } + } + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + if (!bt_disabled) { + } else { + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + } + } +} + +/* ********************************************* + * + * Software Coex Mechanism start + * + * ********************************************* */ + +/* SCO only or SCO+PAN(HS) */ + +/* +void halbtc8192e1ant_action_sco(IN struct btc_coexist* btcoexist) +{ + halbtc8192e1ant_sw_mechanism(btcoexist, true); +} + + +void halbtc8192e1ant_action_hid(IN struct btc_coexist* btcoexist) +{ + halbtc8192e1ant_sw_mechanism(btcoexist, true); +} + + +void halbtc8192e1ant_action_a2dp(IN struct btc_coexist* btcoexist) +{ + halbtc8192e1ant_sw_mechanism(btcoexist, false); +} + +void halbtc8192e1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist) +{ + halbtc8192e1ant_sw_mechanism(btcoexist, false); +} + +void halbtc8192e1ant_action_pan_edr(IN struct btc_coexist* btcoexist) +{ + halbtc8192e1ant_sw_mechanism(btcoexist, false); +} + + +void halbtc8192e1ant_action_pan_hs(IN struct btc_coexist* btcoexist) +{ + halbtc8192e1ant_sw_mechanism(btcoexist, false); +} + + +void halbtc8192e1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist) +{ + halbtc8192e1ant_sw_mechanism(btcoexist, false); +} + +void halbtc8192e1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist) +{ + halbtc8192e1ant_sw_mechanism(btcoexist, true); +} + + +void halbtc8192e1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist) +{ + halbtc8192e1ant_sw_mechanism(btcoexist, true); +} + +void halbtc8192e1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist) +{ + halbtc8192e1ant_sw_mechanism(btcoexist, true); +} + +*/ + +/* ********************************************* + * + * Non-Software Coex Mechanism start + * + * ********************************************* */ +void halbtc8192e1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8192e1ant_action_hs(IN struct btc_coexist *btcoexist) +{ + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8192e1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, ap_enable = false, wifi_busy = false, + bt_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) { + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || + (bt_link_info->a2dp_exist)) { + /* SCO/HID/A2DP busy */ + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if ((bt_link_info->pan_exist) || (wifi_busy)) { + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + } +} + +void halbtc8192e1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist + *btcoexist, IN u8 wifi_status) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* tdma and coex table */ + + if (bt_link_info->sco_exist) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + } else { /* HID */ + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + } +} + +void halbtc8192e1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist + *btcoexist, IN u8 wifi_status) +{ + u8 bt_rssi_state; + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + bt_rssi_state = halbtc8192e1ant_bt_rssi_state(2, 28, 0); + + if ((coex_sta->low_priority_rx >= 1000) && + (coex_sta->low_priority_rx != 65535)) + bt_link_info->slave_role = true; + else + bt_link_info->slave_role = false; + + if (bt_link_info->hid_only) { /* HID */ + halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, + wifi_status); + coex_dm->auto_tdma_adjust = false; + return; + } else if (bt_link_info->a2dp_only) { /* A2DP */ + if (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = false; + } else { + halbtc8192e1ant_tdma_duration_adjust_for_acl(btcoexist, + wifi_status); +#if 0 + if (coex_sta->cck_lock) + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + else +#endif + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = true; + } + } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || + (bt_link_info->hid_exist && bt_link_info->a2dp_exist && + bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = false; + } else if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { /* HID+A2DP */ + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); + coex_dm->auto_tdma_adjust = false; + + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && + bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = false; + } else { + /* BT no-profile busy (0x9) */ + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = false; + } +} + +void halbtc8192e1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +{ + /* power save state */ + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8192e1ant_action_wifi_not_connected_scan(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + if (bt_link_info->a2dp_exist) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else if (bt_link_info->a2dp_exist && + bt_link_info->pan_exist) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 22); + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 20); + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } else { + /* Bryant Add */ + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8192e1ant_action_wifi_not_connected_asso_auth( + IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || + (bt_link_info->a2dp_exist)) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if (bt_link_info->pan_exist) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8192e1ant_action_wifi_connected_scan(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + if (bt_link_info->a2dp_exist) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else if (bt_link_info->a2dp_exist && + bt_link_info->pan_exist) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 22); + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 20); + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } else { + /* Bryant Add */ + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8192e1ant_action_wifi_connected_specific_packet( + IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || + (bt_link_info->a2dp_exist)) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if (bt_link_info->pan_exist) { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8192e1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +{ + boolean wifi_busy = false; + boolean scan = false, link = false, roam = false; + boolean under_4way = false, ap_enable = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect()===>\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + if (under_4way) { + halbtc8192e1ant_action_wifi_connected_specific_packet(btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + if (scan || link || roam) { + if (scan) + halbtc8192e1ant_action_wifi_connected_scan(btcoexist); + else + halbtc8192e1ant_action_wifi_connected_specific_packet( + btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + /* power save state */ + if (!ap_enable && + BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status && + !btcoexist->bt_link_info.hid_only) { + if (btcoexist->bt_link_info.a2dp_only) { /* A2DP */ + if (!wifi_busy) + halbtc8192e1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else { /* busy */ + if (coex_sta->scan_ap_num >= + BT_8192E_1ANT_WIFI_NOISY_THRESH) /* no force LPS, no PS-TDMA, use pure TDMA */ + halbtc8192e1ant_power_save_state( + btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8192e1ant_power_save_state( + btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + } + } else if ((coex_sta->pan_exist == false) && + (coex_sta->a2dp_exist == false) && + (coex_sta->hid_exist == false)) + halbtc8192e1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8192e1ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + } else + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + + /* tdma and coex table */ + if (!wifi_busy) { + if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + halbtc8192e1ant_action_wifi_connected_bt_acl_busy( + btcoexist, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } else { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); + + if ((coex_sta->high_priority_tx) + + (coex_sta->high_priority_rx) <= 60) + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 2); + else + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } + } else { + if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + halbtc8192e1ant_action_wifi_connected_bt_acl_busy( + btcoexist, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } else { + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); + + if ((coex_sta->high_priority_tx) + + (coex_sta->high_priority_rx) <= 60) + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 2); + else + halbtc8192e1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } + } +} + +void halbtc8192e1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + u8 algorithm = 0; + + algorithm = halbtc8192e1ant_action_algorithm(btcoexist); + coex_dm->cur_algorithm = algorithm; + + if (halbtc8192e1ant_is_common_action(btcoexist)) { + + } else { + switch (coex_dm->cur_algorithm) { + case BT_8192E_1ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_action_sco(btcoexist); */ + break; + case BT_8192E_1ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID.\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_action_hid(btcoexist); */ + break; + case BT_8192E_1ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_action_a2dp(btcoexist); */ + break; + case BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_action_a2dp_pan_hs(btcoexist); */ + break; + case BT_8192E_1ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_action_pan_edr(btcoexist); */ + break; + case BT_8192E_1ANT_COEX_ALGO_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HS mode.\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_action_pan_hs(btcoexist); */ + break; + case BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_action_pan_edr_a2dp(btcoexist); */ + break; + case BT_8192E_1ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_action_pan_edr_hid(btcoexist); */ + break; + case BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_action_hid_a2dp_pan_edr(btcoexist); */ + break; + case BT_8192E_1ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_action_hid_a2dp(btcoexist); */ + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + /* halbtc8192e1ant_coex_all_off(btcoexist); */ + break; + } + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + } +} + +void halbtc8192e1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, bt_hs_on = false; + boolean increase_scan_dev_num = false; + boolean bt_ctrl_agg_buf_size = false; + boolean miracast_plus_bt = false; + u8 agg_buf_size = 5; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if ((BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + increase_scan_dev_num = true; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, + &increase_scan_dev_num); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", + num_of_wifi_link, wifi_link_status); + BTC_TRACE(trace_buf); + + if (bt_link_info->bt_link_exist) { + halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, + 0, 1); + miracast_plus_bt = true; + } else { + halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, + 0, 0); + miracast_plus_bt = false; + } + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + + if ((bt_link_info->a2dp_exist) && + (coex_sta->c2h_bt_inquiry_page)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is Inquirying\n"); + BTC_TRACE(trace_buf); + halbtc8192e1ant_action_bt_inquiry(btcoexist); + } else + halbtc8192e1ant_action_wifi_multi_port(btcoexist); + + return; + } + + miracast_plus_bt = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + if ((bt_link_info->bt_link_exist) && (wifi_connected)) { + halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); + + if (bt_link_info->sco_exist) + halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, + false, true, 0x5); + else + halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, + false, true, 0x8); + + halbtc8192e1ant_sw_mechanism(btcoexist, true); + halbtc8192e1ant_run_sw_coexist_mechanism( + btcoexist); /* just print debug message */ + } else { + halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + + halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x5); + + halbtc8192e1ant_sw_mechanism(btcoexist, false); + halbtc8192e1ant_run_sw_coexist_mechanism( + btcoexist); /* just print debug message */ + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is Inquirying\n"); + BTC_TRACE(trace_buf); + halbtc8192e1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8192e1ant_action_hs(btcoexist); + return; + } + + + if (!wifi_connected) { + boolean scan = false, link = false, roam = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is non connected-idle !!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + if (scan || link || roam) { + if (scan) + halbtc8192e1ant_action_wifi_not_connected_scan( + btcoexist); + else + halbtc8192e1ant_action_wifi_not_connected_asso_auth( + btcoexist); + } else + halbtc8192e1ant_action_wifi_not_connected(btcoexist); + } else /* wifi LPS/Busy */ + halbtc8192e1ant_action_wifi_connected(btcoexist); +} + +void halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + /* force to reset coex mechanism */ + + /* sw all off */ + halbtc8192e1ant_sw_mechanism(btcoexist, false); + + /* halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ + halbtc8192e1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + coex_sta->pop_event_cnt = 0; +} + +void halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + u16 u16tmp = 0; + u8 u8tmp = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 1Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + /* antenna sw ctrl to bt */ + halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, false); + + halbtc8192e1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + /* antenna switch control parameter */ + btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555); + + /* coex parameters */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + /* 0x790[5:0]=0x5 */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); + u8tmp &= 0xc0; + u8tmp |= 0x5; + btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); + + /* enable counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); + + /* enable PTA */ + btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); + /* enable mailbox interface */ + u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40); + u16tmp |= BIT(9); + btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp); + + /* enable PTA I2C mailbox */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101); + u8tmp |= BIT(4); + btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp); + + /* enable bt clock when wifi is disabled. */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93); + u8tmp |= BIT(0); + btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp); + /* enable bt clock when suspend. */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); + u8tmp |= BIT(0); + btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); +} + + +/* +void halbtc8192e1ant_wifi_off_hw_cfg(IN struct btc_coexist* btcoexist) +{ + + +} +*/ + +/* ************************************************************ + * work around function start with wa_halbtc8192e1ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8192e1ant_ + * ************************************************************ */ +void ex_halbtc8192e1ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ +#if 0 + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x0; + u16 u16tmp = 0x0; + + btcoexist->stop_coex_dm = true; + + btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20); + + /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ + u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); + btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); + + /* set GRAN_BT = 1 */ + btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); + /* set WLAN_ACT = 0 */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); + + /* */ + /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + if (btcoexist->chip_interface == BTC_INTF_USB) { + /* fixed at S0 for USB interface */ + btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); + + u8tmp |= 0x1; /* antenna inverse */ + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + + board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; + } else { + /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ + if (board_info->single_ant_path == 0) { + /* set to S1 */ + btcoexist->btc_write_4byte(btcoexist, 0x948, 0x280); + board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; + } else if (board_info->single_ant_path == 1) { + /* set to S0 */ + btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); + u8tmp |= 0x1; /* antenna inverse */ + board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; + } + + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384, + u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, + u8tmp); + } +#endif +} + +void ex_halbtc8192e1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{ +} + +void ex_halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8192e1ant_init_hw_config(btcoexist, wifi_only); + btcoexist->stop_coex_dm = false; +} + +void ex_halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = false; + + halbtc8192e1ant_init_coex_dm(btcoexist); + + halbtc8192e1ant_query_bt_info(btcoexist); +} + +void ex_halbtc8192e1ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u32 u32tmp[4]; + u32 fw_ver = 0, bt_patch_ver = 0; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + if (btcoexist->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", + "Ant PG number/ Ant mechanism:", + board_info->pg_ant_num, board_info->btdm_ant_num); + CL_PRINTF(cli_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", + "CoexVer/ FwVer/ PatchVer", + glcoex_ver_date_8192e_1ant, glcoex_ver_8192e_1ant, fw_ver, + bt_patch_ver, bt_patch_ver); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "Wifi channel informed to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", + "BT [status/ rssi/ retryCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") + : ((BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi, coex_sta->bt_retry_cnt); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", + "SCO/HID/PAN/A2DP", + bt_link_info->sco_exist, bt_link_info->hid_exist, + bt_link_info->pan_exist, bt_link_info->a2dp_exist); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); + + bt_info_ext = coex_sta->bt_info_ext; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "BT Info A2DP rate", + (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); + CL_PRINTF(cli_buf); + + for (i = 0; i < BT_INFO_SRC_8192E_1ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8192e_1ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + if (!btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanisms]============"); + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", + "PS TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + coex_dm->auto_tdma_adjust); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", + "Latest error condition(should be 0)", + coex_dm->error_condition); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", + "IgnWlanAct", + coex_dm->cur_ignore_wlan_act); + CL_PRINTF(cli_buf); + } + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0xc04/ 0xd04/ 0x90c", + u32tmp[0], u32tmp[1], u32tmp[2]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", + u8tmp[0]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x92c/ 0x930", + (u8tmp[0]), u32tmp[0]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x40/ 0x4f", + u8tmp[0], u8tmp[1]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x550(bcn ctrl)/0x522", + u32tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", + u32tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", + u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(hp rx[31:16]/tx[15:0])", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x774(lp rx[31:16]/tx[15:0])", + coex_sta->low_priority_rx, coex_sta->low_priority_tx); + CL_PRINTF(cli_buf); +#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 1) + halbtc8192e1ant_monitor_bt_ctr(btcoexist); +#endif + + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + +void ex_halbtc8192e1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = true; + + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, + true); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = false; + + halbtc8192e1ant_init_hw_config(btcoexist, false); + halbtc8192e1ant_init_coex_dm(btcoexist); + halbtc8192e1ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8192e1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = true; + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = false; + } +} + +void ex_halbtc8192e1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false, bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + + u8 u8tmpa, u8tmpb; + u32 u32tmp; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + if (BTC_SCAN_START == type) { + coex_sta->wifi_is_high_pri_task = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify\n"); + BTC_TRACE(trace_buf); + + halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 8); /* Force antenna setup for no scan result issue */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); + u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); + u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", + u32tmp, u8tmpa, u8tmpb); + BTC_TRACE(trace_buf); + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + } + + if (coex_sta->bt_disabled) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + halbtc8192e1ant_query_bt_info(btcoexist); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8192e1ant_action_wifi_multi_port(btcoexist); + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8192e1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8192e1ant_action_hs(btcoexist); + return; + } + + if (BTC_SCAN_START == type) { + if (!wifi_connected) /* non-connected scan */ + halbtc8192e1ant_action_wifi_not_connected_scan( + btcoexist); + else /* wifi is connected */ + halbtc8192e1ant_action_wifi_connected_scan(btcoexist); + } else if (BTC_SCAN_FINISH == type) { + if (!wifi_connected) /* non-connected scan */ + halbtc8192e1ant_action_wifi_not_connected(btcoexist); + else + halbtc8192e1ant_action_wifi_connected(btcoexist); + } +} + +void ex_halbtc8192e1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false, bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm || + coex_sta->bt_disabled) + return; + + if (BTC_ASSOCIATE_START == type) { + coex_sta->wifi_is_high_pri_task = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify\n"); + BTC_TRACE(trace_buf); + coex_dm->arp_cnt = 0; + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify\n"); + BTC_TRACE(trace_buf); + /* coex_dm->arp_cnt = 0; */ + } + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8192e1ant_action_wifi_multi_port(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8192e1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8192e1ant_action_hs(btcoexist); + return; + } + + if (BTC_ASSOCIATE_START == type) + halbtc8192e1ant_action_wifi_not_connected_asso_auth(btcoexist); + else if (BTC_ASSOCIATE_FINISH == type) { + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + if (!wifi_connected) /* non-connected scan */ + halbtc8192e1ant_action_wifi_not_connected(btcoexist); + else + halbtc8192e1ant_action_wifi_connected(btcoexist); + } +} + +void ex_halbtc8192e1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + boolean wifi_under_b_mode = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm || + coex_sta->bt_disabled) + return; + + if (BTC_MEDIA_CONNECT == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x00); /* CCK Rx */ + } else { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x10); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x10); /* CCK Rx */ + } + + coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, + 0x430); + coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, + 0x434); + coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( + btcoexist, 0x42a); + coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( + btcoexist, 0x456); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + coex_dm->arp_cnt = 0; + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + } + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + /* h2c_parameter[0] = 0x1; */ + h2c_parameter[0] = 0x0; + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); +} + +void ex_halbtc8192e1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm || + coex_sta->bt_disabled) + return; + + if (BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + BTC_PACKET_ARP == type) { + if (BTC_PACKET_ARP == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ARP notify\n"); + BTC_TRACE(trace_buf); + + coex_dm->arp_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ARP Packet Count = %d\n", + coex_dm->arp_cnt); + BTC_TRACE(trace_buf); + + if (coex_dm->arp_cnt >= + 10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */ + coex_sta->wifi_is_high_pri_task = false; + else + coex_sta->wifi_is_high_pri_task = true; + } else { + coex_sta->wifi_is_high_pri_task = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet DHCP or EAPOL notify\n"); + BTC_TRACE(trace_buf); + } + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet [Type = %d] notify\n", type); + BTC_TRACE(trace_buf); + } + + coex_sta->specific_pkt_period_cnt = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8192e1ant_action_wifi_multi_port(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8192e1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8192e1ant_action_hs(btcoexist); + return; + } + + if (BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task))) + halbtc8192e1ant_action_wifi_connected_specific_packet(btcoexist); +} + +void ex_halbtc8192e1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 bt_info = 0; + u8 i, rsp_source = 0; + boolean wifi_connected = false; + boolean bt_busy = false; + + coex_sta->c2h_bt_info_req_sent = false; + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8192E_1ANT_MAX) + rsp_source = BT_INFO_SRC_8192E_1ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + if (i == 1) + bt_info = tmp_buf[i]; + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + if (BT_INFO_SRC_8192E_1ANT_WIFI_FW != rsp_source) { + coex_sta->bt_retry_cnt = /* [3:0] */ + coex_sta->bt_info_c2h[rsp_source][2] & 0xf; + + if (coex_sta->bt_retry_cnt >= 1) + coex_sta->pop_event_cnt++; + + if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) + coex_sta->c2h_bt_page = true; + else + coex_sta->c2h_bt_page = false; + + coex_sta->bt_rssi = + coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; + /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */ + + coex_sta->bt_info_ext = + coex_sta->bt_info_c2h[rsp_source][4]; + + coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] + & 0x40); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, + &coex_sta->bt_tx_rx_mask); + if (!coex_sta->bt_tx_rx_mask) { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, + 0x3c, 0x15); + } + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + if (coex_sta->bt_info_ext & BIT(1)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + if (wifi_connected) + ex_halbtc8192e1ant_media_status_notify( + btcoexist, BTC_MEDIA_CONNECT); + else + ex_halbtc8192e1ant_media_status_notify( + btcoexist, BTC_MEDIA_DISCONNECT); + } + + if (coex_sta->bt_info_ext & BIT(3)) { + if (!btcoexist->manual_control && + !btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8192e1ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, false); + } + } else { + /* BT already NOT ignore Wlan active, do nothing here. */ + } +#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 0) + if ((coex_sta->bt_info_ext & BIT(4))) { + /* BT auto report already enabled, do nothing */ + } else + halbtc8192e1ant_bt_auto_report(btcoexist, FORCE_EXEC, + true); +#endif + } + + /* check BIT2 first ==> check if bt is under inquiry or page scan */ + if (bt_info & BT_INFO_8192E_1ANT_B_INQ_PAGE) + coex_sta->c2h_bt_inquiry_page = true; + else + coex_sta->c2h_bt_inquiry_page = false; + + /* set link exist status */ + if (!(bt_info & BT_INFO_8192E_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (bt_info & BT_INFO_8192E_1ANT_B_FTP) + coex_sta->pan_exist = true; + else + coex_sta->pan_exist = false; + if (bt_info & BT_INFO_8192E_1ANT_B_A2DP) + coex_sta->a2dp_exist = true; + else + coex_sta->a2dp_exist = false; + if (bt_info & BT_INFO_8192E_1ANT_B_HID) + coex_sta->hid_exist = true; + else + coex_sta->hid_exist = false; + if (bt_info & BT_INFO_8192E_1ANT_B_SCO_ESCO) + coex_sta->sco_exist = true; + else + coex_sta->sco_exist = false; + } + + halbtc8192e1ant_update_bt_link_info(btcoexist); + + bt_info = bt_info & + 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ + + if (!(bt_info & BT_INFO_8192E_1ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info == + BT_INFO_8192E_1ANT_B_CONNECTION) { /* connection exists but no busy */ + coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + BTC_TRACE(trace_buf); + } else if ((bt_info & BT_INFO_8192E_1ANT_B_SCO_ESCO) || + (bt_info & BT_INFO_8192E_1ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info & BT_INFO_8192E_1ANT_B_ACL_BUSY) { + if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) + coex_dm->auto_tdma_adjust = false; + coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + BTC_TRACE(trace_buf); + } + + if ((BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + bt_busy = true; + else + bt_busy = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + halbtc8192e1ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8192e1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u32 u32tmp; + u8 u8tmpa, u8tmpb, u8tmpc; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_RF_ON == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned ON!!\n"); + BTC_TRACE(trace_buf); + btcoexist->stop_coex_dm = false; + } else if (BTC_RF_OFF == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned OFF!!\n"); + BTC_TRACE(trace_buf); + + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, + true); + + halbtc8192e1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + btcoexist->stop_coex_dm = true; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); + u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); + u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); + u8tmpc = btcoexist->btc_read_1byte(btcoexist, 0x76e); + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n", + u32tmp, u8tmpa, u8tmpb, u8tmpc); + BTC_TRACE(trace_buf); + + } +} + +void ex_halbtc8192e1ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true); + + halbtc8192e1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + + ex_halbtc8192e1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + + btcoexist->stop_coex_dm = true; +} + +void ex_halbtc8192e1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_WIFI_PNP_SLEEP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + + halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, + true); + + /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ + /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ + /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ + coex_sta->under_ips = false; + coex_sta->under_lps = false; + btcoexist->stop_coex_dm = true; + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); + btcoexist->stop_coex_dm = false; + halbtc8192e1ant_init_hw_config(btcoexist, false); + halbtc8192e1ant_init_coex_dm(btcoexist); + halbtc8192e1ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8192e1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], *****************Coex DM Reset*****************\n"); + BTC_TRACE(trace_buf); + + halbtc8192e1ant_init_hw_config(btcoexist, false); + /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ + /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); */ + halbtc8192e1ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8192e1ant_periodical(IN struct btc_coexist *btcoexist) +{ +#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 0) + halbtc8192e1ant_query_bt_info(btcoexist); + halbtc8192e1ant_monitor_bt_enable_disable(btcoexist); +#else + halbtc8192e1ant_monitor_bt_ctr(btcoexist); + halbtc8192e1ant_monitor_wifi_ctr(btcoexist); + + if (halbtc8192e1ant_is_wifi_status_changed(btcoexist) || + coex_dm->auto_tdma_adjust) + + halbtc8192e1ant_run_coexist_mechanism(btcoexist); + + coex_sta->specific_pkt_period_cnt++; +#endif +} + + +void ex_halbtc8192e1ant_dbg_control(IN struct btc_coexist *btcoexist, + IN u8 op_code, IN u8 op_len, IN u8 *pdata) +{ + switch (op_code) { + case BTC_DBG_SET_COEX_NORMAL: + btcoexist->manual_control = false; + halbtc8192e1ant_init_coex_dm(btcoexist); + break; + case BTC_DBG_SET_COEX_WIFI_ONLY: + btcoexist->manual_control = true; + halbtc8192e1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 9); + break; + case BTC_DBG_SET_COEX_BT_ONLY: + /* todo */ + break; + default: + break; + } +} + +#endif /* #if (RTL8192E_SUPPORT == 1) */ + +#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ diff --git a/hal/btc/halbtc8192e1ant.h b/hal/btc/halbtc8192e1ant.h new file mode 100644 index 0000000..10c34c1 --- /dev/null +++ b/hal/btc/halbtc8192e1ant.h @@ -0,0 +1,240 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8192E_SUPPORT == 1) + +/* ******************************************* + * The following is for 8192E 1ANT BT Co-exist definition + * ******************************************* */ +#define BT_AUTO_REPORT_ONLY_8192E_1ANT 1 + +#define BT_INFO_8192E_1ANT_B_FTP BIT(7) +#define BT_INFO_8192E_1ANT_B_A2DP BIT(6) +#define BT_INFO_8192E_1ANT_B_HID BIT(5) +#define BT_INFO_8192E_1ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8192E_1ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8192E_1ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8192E_1ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8192E_1ANT_B_CONNECTION BIT(0) + +#define BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT(0))) ? true : false) + +#define BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT 2 + +#define BT_8192E_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ + +enum bt_info_src_8192e_1ant { + BT_INFO_SRC_8192E_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8192E_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8192E_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8192E_1ANT_MAX +}; + +enum bt_8192e_1ant_bt_status { + BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8192E_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8192E_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8192E_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8192E_1ANT_BT_STATUS_MAX +}; + +enum bt_8192e_1ant_wifi_status { + BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8192E_1ANT_WIFI_STATUS_MAX +}; + +enum bt_8192e_1ant_coex_algo { + BT_8192E_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8192E_1ANT_COEX_ALGO_SCO = 0x1, + BT_8192E_1ANT_COEX_ALGO_HID = 0x2, + BT_8192E_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8192E_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8192E_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8192E_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8192E_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8192E_1ANT_COEX_ALGO_MAX = 0xb, +}; + +struct coex_dm_8192e_1ant { + /* fw mechanism */ + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean auto_tdma_adjust; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + /* sw mechanism */ + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + + u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ + u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ + u16 backup_retry_limit; + u8 backup_ampdu_max_time; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + u32 pre_ra_mask; + u32 cur_ra_mask; + u8 pre_arfr_type; + u8 cur_arfr_type; + u8 pre_retry_limit_type; + u8 cur_retry_limit_type; + u8 pre_ampdu_time_type; + u8 cur_ampdu_time_type; + u32 arp_cnt; + + u8 error_condition; +}; + +struct coex_sta_8192e_1ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + + boolean under_lps; + boolean under_ips; + u32 specific_pkt_period_cnt; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + s8 bt_rssi; + boolean bt_tx_rx_mask; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + boolean c2h_bt_info_req_sent; + u8 bt_info_c2h[BT_INFO_SRC_8192E_1ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8192E_1ANT_MAX]; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_page; /* Add for win8.1 page out issue */ + boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ + u8 bt_retry_cnt; + u8 bt_info_ext; + u32 pop_event_cnt; + u8 scan_ap_num; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_agg; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_agg; + + boolean cck_lock; + boolean pre_ccklock; + u8 coex_table_type; + + boolean force_lps_on; +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8192e1ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8192e1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); +void ex_halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8192e1ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e1ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8192e1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e1ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8192e1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8192e1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); +void ex_halbtc8192e1ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8192e1ant_display_coex_info(IN struct btc_coexist *btcoexist); +void ex_halbtc8192e1ant_dbg_control(IN struct btc_coexist *btcoexist, + IN u8 op_code, IN u8 op_len, IN u8 *pdata); + +#else /* #if (RTL8192E_SUPPORT == 1) */ +#define ex_halbtc8192e1ant_power_on_setting(btcoexist) +#define ex_halbtc8192e1ant_pre_load_firmware(btcoexist) +#define ex_halbtc8192e1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8192e1ant_init_coex_dm(btcoexist) +#define ex_halbtc8192e1ant_ips_notify(btcoexist, type) +#define ex_halbtc8192e1ant_lps_notify(btcoexist, type) +#define ex_halbtc8192e1ant_scan_notify(btcoexist, type) +#define ex_halbtc8192e1ant_connect_notify(btcoexist, type) +#define ex_halbtc8192e1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8192e1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8192e1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8192e1ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8192e1ant_halt_notify(btcoexist) +#define ex_halbtc8192e1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8192e1ant_coex_dm_reset(btcoexist) +#define ex_halbtc8192e1ant_periodical(btcoexist) +#define ex_halbtc8192e1ant_display_coex_info(btcoexist) +#define ex_halbtc8192e1ant_dbg_control(btcoexist, op_code, op_len, pdata) + +#endif + +#endif diff --git a/hal/btc/halbtc8192e2ant.c b/hal/btc/halbtc8192e2ant.c new file mode 100644 index 0000000..9936a8b --- /dev/null +++ b/hal/btc/halbtc8192e2ant.c @@ -0,0 +1,4391 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for RTL8192E Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8192E_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8192e_2ant glcoex_dm_8192e_2ant; +static struct coex_dm_8192e_2ant *coex_dm = &glcoex_dm_8192e_2ant; +static struct coex_sta_8192e_2ant glcoex_sta_8192e_2ant; +static struct coex_sta_8192e_2ant *coex_sta = &glcoex_sta_8192e_2ant; + +const char *const glbt_info_src_8192e_2ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; +/* ************************************************************ + * BtCoex Version Format: + * 1. date : glcoex_ver_date_XXXXX_1ant + * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant + * 3. BtCoexVersion : glcoex_ver_btdesired_XXXXX_1ant + * 4. others : glcoex_ver_XXXXXX_XXXXX_1ant + * + * Variable should be indicated IC and Antenna numbers !!! + * Please strictly follow this order and naming style !!! + * + * ************************************************************ */ +u32 glcoex_ver_date_8192e_2ant = 20160818; +u32 glcoex_ver_8192e_2ant = 0x44; +u32 glcoex_ver_btdesired_8192e_2ant = 0x44; +/*1. add coex. log for wifi/BT coex. version*/ +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8192e2ant_ + * ************************************************************ */ +u8 halbtc8192e2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_bt_rssi_state; + } + + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + +u8 halbtc8192e2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_wifi_rssi_state[index]; + } + + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; + + return wifi_rssi_state; +} + +void halbtc8192e2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = true, bt_disabled = false; + + /* This function check if bt is disabled */ + + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = false; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = false; + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + BTC_TRACE(trace_buf); + } else { + bt_disable_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt all counters=0, %d times!!\n", + bt_disable_cnt); + BTC_TRACE(trace_buf); + if (bt_disable_cnt >= 2) { + bt_disabled = true; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + BTC_TRACE(trace_buf); + } + } + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + /* if (!bt_disabled) { + } else { + } */ + } +} + +u32 halbtc8192e2ant_decide_ra_mask(IN struct btc_coexist *btcoexist, + IN u8 ss_type, IN u32 ra_mask_type) +{ + u32 dis_ra_mask = 0x0; + + switch (ra_mask_type) { + case 0: /* normal mode */ + if (ss_type == 2) + dis_ra_mask = 0x0; /* enable 2ss */ + else + dis_ra_mask = 0xfff00000; /* disable 2ss */ + break; + case 1: /* disable cck 1/2 */ + if (ss_type == 2) + dis_ra_mask = 0x00000003; /* enable 2ss */ + else + dis_ra_mask = 0xfff00003; /* disable 2ss */ + break; + case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ + if (ss_type == 2) + dis_ra_mask = 0x0001f1f7; /* enable 2ss */ + else + dis_ra_mask = 0xfff1f1f7; /* disable 2ss */ + break; + default: + break; + } + + return dis_ra_mask; +} + +void halbtc8192e2ant_update_ra_mask(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 dis_rate_mask) +{ + coex_dm->cur_ra_mask = dis_rate_mask; + + if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) + btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, + &coex_dm->cur_ra_mask); + coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; +} + +void halbtc8192e2ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + boolean wifi_under_b_mode = false; + + coex_dm->cur_arfr_type = type; + + if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { + switch (coex_dm->cur_arfr_type) { + case 0: /* normal mode */ + btcoexist->btc_write_4byte(btcoexist, 0x430, + coex_dm->backup_arfr_cnt1); + btcoexist->btc_write_4byte(btcoexist, 0x434, + coex_dm->backup_arfr_cnt2); + break; + case 1: + btcoexist->btc_get(btcoexist, + BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + if (wifi_under_b_mode) { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x01010101); + } else { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x04030201); + } + break; + default: + break; + } + } + + coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; +} + +void halbtc8192e2ant_retry_limit(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_retry_limit_type = type; + + if (force_exec || + (coex_dm->pre_retry_limit_type != + coex_dm->cur_retry_limit_type)) { + switch (coex_dm->cur_retry_limit_type) { + case 0: /* normal mode */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + coex_dm->backup_retry_limit); + break; + case 1: /* retry limit=8 */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + 0x0808); + break; + default: + break; + } + } + + coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; +} + +void halbtc8192e2ant_ampdu_max_time(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_ampdu_time_type = type; + + if (force_exec || + (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { + switch (coex_dm->cur_ampdu_time_type) { + case 0: /* normal mode */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + coex_dm->backup_ampdu_max_time); + break; + case 1: /* AMPDU timw = 0x38 * 32us */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + 0x38); + break; + default: + break; + } + } + + coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; +} + +void halbtc8192e2ant_limited_tx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, + IN u8 retry_limit_type, IN u8 ampdu_time_type) +{ + u32 dis_ra_mask = 0x0; + + coex_dm->cur_ra_mask_type = ra_mask_type; + dis_ra_mask = halbtc8192e2ant_decide_ra_mask(btcoexist, + coex_dm->cur_ss_type, ra_mask_type); + halbtc8192e2ant_update_ra_mask(btcoexist, force_exec, dis_ra_mask); + + halbtc8192e2ant_auto_rate_fallback_retry(btcoexist, force_exec, + arfr_type); + halbtc8192e2ant_retry_limit(btcoexist, force_exec, retry_limit_type); + halbtc8192e2ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); +} + +void halbtc8192e2ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +void halbtc8192e2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); + BTC_TRACE(trace_buf); + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); +} + + +void halbtc8192e2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ +#if 1 + + coex_sta->crc_ok_cck = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_VHT); +#endif +} + + + +void halbtc8192e2ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + coex_sta->c2h_bt_info_req_sent = true; + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],Query BT info!!!! H2C 0x61 = 0x1\n"); + BTC_TRACE(trace_buf); +} + +boolean halbtc8192e2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) +{ + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + + wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, + 2, 34, 0); + + if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) || + (BTC_RSSI_STATE_LOW == wifi_rssi_state)) + return true; + } + + return false; +} + +void halbtc8192e2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = true; + bt_link_info->bt_link_exist = true; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = true; + else + bt_link_info->sco_only = false; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = true; + else + bt_link_info->a2dp_only = false; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = true; + else + bt_link_info->pan_only = false; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = true; + else + bt_link_info->hid_only = false; +} + +u8 halbtc8192e2ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + struct btc_stack_info *stack_info = &btcoexist->stack_info; + boolean bt_hs_on = false; + u8 algorithm = BT_8192E_2ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_2ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_SCO_PAN; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + if (stack_info->num_of_hid >= 2) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID*2 + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_HID_A2DP; + } + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_2ANT_COEX_ALGO_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_SCO_PAN; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +void halbtc8192e2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, + IN u8 dac_swing_lvl) +{ + u8 h2c_parameter[1] = {0}; + + /* There are several type of dacswing */ + /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ + h2c_parameter[0] = dac_swing_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); +} + +void halbtc8192e2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN u8 dec_bt_pwr_lvl) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = dec_bt_pwr_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); +} + +void halbtc8192e2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 dec_bt_pwr_lvl) +{ + coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; + + if (!force_exec) { +#if 0 /* work around, avoid h2c command fail. */ + if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) + return; +#endif + } + halbtc8192e2ant_set_fw_dec_bt_pwr(btcoexist, + coex_dm->cur_bt_dec_pwr_lvl); + + coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; +} + +void halbtc8192e2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean enable_auto_report) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = 0; + + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); + + btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); +} + +void halbtc8192e2ant_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable_auto_report) +{ + coex_dm->cur_bt_auto_report = enable_auto_report; + + if (!force_exec) { + if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) + return; + } + halbtc8192e2ant_set_bt_auto_report(btcoexist, + coex_dm->cur_bt_auto_report); + + coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; +} + +void halbtc8192e2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 fw_dac_swing_lvl) +{ + coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; + + if (!force_exec) { + if (coex_dm->pre_fw_dac_swing_lvl == + coex_dm->cur_fw_dac_swing_lvl) + return; + } + + halbtc8192e2ant_set_fw_dac_swing_level(btcoexist, + coex_dm->cur_fw_dac_swing_lvl); + + coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; +} + +void halbtc8192e2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist, + IN boolean rx_rf_shrink_on) +{ + if (rx_rf_shrink_on) { + /* Shrink RF Rx LPF corner */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Shrink RF Rx LPF corner!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, + 0xffffc); + } else { + /* Resume RF Rx LPF corner */ + /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ + if (btcoexist->initilized) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Resume RF Rx LPF corner!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, + 0xfffff, coex_dm->bt_rf_0x1e_backup); + } + } +} + +void halbtc8192e2ant_rf_shrink(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rx_rf_shrink_on) +{ + coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; + + if (!force_exec) { + if (coex_dm->pre_rf_rx_lpf_shrink == + coex_dm->cur_rf_rx_lpf_shrink) + return; + } + halbtc8192e2ant_set_sw_rf_rx_lpf_corner(btcoexist, + coex_dm->cur_rf_rx_lpf_shrink); + + coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; +} + +void halbtc8192e2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist + *btcoexist, IN boolean low_penalty_ra) +{ + u8 h2c_parameter[6] = {0}; + + h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ + + if (low_penalty_ra) { + h2c_parameter[1] |= BIT(0); + h2c_parameter[2] = + 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ + h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ + h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ + h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ + } + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); +} + +void halbtc8192e2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) + return; + } + halbtc8192e2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, + coex_dm->cur_low_penalty_ra); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; +} + +void halbtc8192e2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, + IN u32 level) +{ + u8 val = (u8)level; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Write SwDacSwing = 0x%x\n", level); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val); +} + +void halbtc8192e2ant_set_sw_full_time_dac_swing(IN struct btc_coexist + *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) +{ + if (sw_dac_swing_on) + halbtc8192e2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl); + else + halbtc8192e2ant_set_dac_swing_reg(btcoexist, 0x18); +} + + +void halbtc8192e2ant_dac_swing(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) +{ + coex_dm->cur_dac_swing_on = dac_swing_on; + coex_dm->cur_dac_swing_lvl = dac_swing_lvl; + + if (!force_exec) { + if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && + (coex_dm->pre_dac_swing_lvl == + coex_dm->cur_dac_swing_lvl)) + return; + } + delay_ms(30); + halbtc8192e2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, + dac_swing_lvl); + + coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; + coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; +} + +void halbtc8192e2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, + IN boolean adc_back_off) +{ + if (adc_back_off) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB BackOff Level On!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x3); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB BackOff Level Off!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x1); + } +} + +void halbtc8192e2ant_adc_back_off(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean adc_back_off) +{ + coex_dm->cur_adc_back_off = adc_back_off; + + if (!force_exec) { + if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) + return; + } + halbtc8192e2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off); + + coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; +} + +void halbtc8192e2ant_set_agc_table(IN struct btc_coexist *btcoexist, + IN boolean agc_table_en) +{ + /* =================BB AGC Gain Table */ + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table On!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x0a1A0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x091B0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x081C0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x071D0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x061E0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x051F0001); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table Off!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001); + } +} + +void halbtc8192e2ant_agc_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean agc_table_en) +{ + coex_dm->cur_agc_table_en = agc_table_en; + + if (!force_exec) { + if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) + return; + } + halbtc8192e2ant_set_agc_table(btcoexist, agc_table_en); + + coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; +} + +void halbtc8192e2ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8192e2ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8192e2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8192e2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + switch (type) { + case 0: + halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555, + 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 1: + halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a, + 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 2: + halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55dd55dd, + 0x5ada5ada, 0xffffff, 0x3); + break; + case 3: + halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5fdf5fdf, + 0x5fdb5fdb, 0xffffff, 0x3); + break; + case 4: + halbtc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff, + 0x5ffb5ffb, 0xffffff, 0x3); + break; + case 5: + halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5ddd5ddd, + 0x5fdb5fdb, 0xffffff, 0x3); + break; + case 6: + halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5fff5fff, + 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 7: + if (coex_sta->scan_ap_num <= NOISY_AP_NUM_THRESH_8192E) + halbtc8192e2ant_coex_table(btcoexist, force_exec, + 0xffffffff, 0xfafafafa, 0xffffff, 0x3); + else + halbtc8192e2ant_coex_table(btcoexist, force_exec, + 0xffffffff, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 8: + halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5f5f5f5f, + 0x5a5a5a5a, 0xffffff, 0x3); + break; + default: + break; + } +} + +void halbtc8192e2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 h2c_parameter[1] = {0}; + + if (enable) + h2c_parameter[0] |= BIT(0); /* function enable */ + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + +void halbtc8192e2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8192e2ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8192e2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8192e2ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8192e2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8192e2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if (ap_enable) { + if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], FW for 1Ant AP mode\n"); + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + } + } + + h2c_parameter[0] = byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = byte5; + + coex_dm->ps_tdma_para[0] = byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); +} + +void halbtc8192e2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, + IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, + IN boolean limited_dig, IN boolean bt_lna_constrain) +{ + /* + u32 wifi_bw; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if(BTC_WIFI_BW_HT40 != wifi_bw) + { + if (shrink_rx_lpf) + shrink_rx_lpf = false; + } + */ + + halbtc8192e2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); + /* halbtc8192e2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); */ +} + +void halbtc8192e2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, + IN boolean agc_table_shift, IN boolean adc_back_off, + IN boolean sw_dac_swing, IN u32 dac_swing_lvl) +{ + halbtc8192e2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); + /* halbtc8192e2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */ + halbtc8192e2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, + dac_swing_lvl); +} + +void halbtc8192e2ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) +{ + u32 u32tmp = 0; + + if (init_hwcfg) { + btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24); + btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700); + if (btcoexist->chip_interface == BTC_INTF_USB) + btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); + else + btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); + + /* 0x4c[27][24]='00', Set Antenna to BB */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp &= ~BIT(24); + u32tmp &= ~BIT(27); + btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); + } else if (wifi_off) { + if (btcoexist->chip_interface == BTC_INTF_USB) + btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); + else + btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); + + /* 0x4c[27][24]='11', Set Antenna to BT, 0x64[8:7]=0, 0x64[2]=1 */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp |= BIT(24); + u32tmp |= BIT(27); + btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); + } + + /* ext switch setting */ + switch (ant_pos_type) { + case BTC_ANT_PATH_WIFI: + btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); + break; + case BTC_ANT_PATH_BT: + btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20); + break; + default: + case BTC_ANT_PATH_PTA: + btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); + break; + } +} + +void halbtc8192e2ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + s8 wifi_duration_adjust = 0x0; + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) + return; + } + + if (coex_sta->scan_ap_num >= 40) + wifi_duration_adjust = -15; + else if (coex_sta->scan_ap_num >= 20) + wifi_duration_adjust = -10; + + + if (turn_on) { + switch (type) { + case 1: + default: /*d1,wb*/ + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x3c, + 0x03, 0x11, 0x10); + break; + case 2: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x32, + 0x03, 0x11, 0x10); + break; + case 3: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x28, + 0x03, 0x11, 0x10); + break; + case 4: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1e, + 0x03, 0x11, 0x10); + break; + case 5: /*d1,pb,TXpause*/ + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x3c, + 0x03, 0x90, 0x10); + break; + case 6: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x32, + 0x03, 0x90, 0x10); + break; + case 7: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x28, + 0x03, 0x90, 0x10); + break; + case 8: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x1e, + 0x03, 0x90, 0x10); + break; + case 9: /*d1,bb*/ + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x3c, + 0x03, 0x31, 0x10); + break; + case 10: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x32, + 0x03, 0x31, 0x10); + break; + case 11: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x28, + 0x03, 0x31, 0x10); + break; + case 12: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1e, + 0x03, 0x31, 0x10); + break; + case 13: /*d1,bb,TXpause*/ + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x3c, + 0x03, 0x30, 0x10); + break; + case 14: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x32, + 0x03, 0x30, 0x10); + break; + case 15: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x28, + 0x03, 0x30, 0x10); + break; + case 16: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1e, + 0x03, 0x30, 0x10); + break; + case 17: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x61, 0x20, + 0x03, 0x10, 0x10); + break; + case 18: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, + 0xe1, 0x90); + break; + case 19: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x25, + 0x25, 0xe1, 0x90); + break; + case 20: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x25, + 0x25, 0x60, 0x90); + break; + case 21: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x61, 0x35, + 0x03, 0x11, 0x11); + break; + case 22: /* d1,wb */ + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x14, + 0x03, 0x11, 0x14); + break; + case 23: /* d1,pb,TXpause */ + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x14, + 0x03, 0x90, 0x14); + break; + case 24: /* d1,bb */ + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x14, + 0x03, 0x31, 0x14); + break; + case 25: /* d1,bb,TXpause */ + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x14, + 0x03, 0x30, 0x14); + break; + case 71: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, + 0x1a, 0xe1, 0x90); + break; + /* following cases is for wifi rssi low // bad antenna isolation, started from 81 */ + case 80: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x3c, + 0x3, 0x10, 0x50); + break; + case 81: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, + 0x3a + wifi_duration_adjust, 0x3, 0x10, 0x50); + break; + case 82: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, + 0x30 + wifi_duration_adjust, 0x03, 0x10, 0x50); + break; + case 83: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x21, + 0x03, 0x10, 0x50); + break; + case 84: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x15, + 0x3, 0x10, 0x50); + break; + case 85: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x3a, + 0x03, 0x10, 0x50); + break; + case 86: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x21, + 0x03, 0x10, 0x50); + break; + case 87: + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x14, + 0x03, 0x10, 0x54); + break; + + } + } else { + /* disable PS tdma */ + switch (type) { + default: + case 0: /* ANT2PTA, 0x778=1 */ + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x8, + 0x0, 0x0, 0x0, 0x0); + halbtc8192e2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_PTA, false, false); + break; + case 1: /* ANT2BT, 0x778=3 */ + halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x8, 0x0); + delay_ms(5); + halbtc8192e2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_BT, false, false); + break; + + } + } + + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; +} + +void halbtc8192e2ant_set_switch_ss_type(IN struct btc_coexist *btcoexist, + IN u8 ss_type) +{ + u8 mimo_ps = BTC_MIMO_PS_DYNAMIC; + u32 dis_ra_mask = 0x0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], REAL set SS Type = %d\n", ss_type); + BTC_TRACE(trace_buf); + + dis_ra_mask = halbtc8192e2ant_decide_ra_mask(btcoexist, ss_type, + coex_dm->cur_ra_mask_type); + halbtc8192e2ant_update_ra_mask(btcoexist, FORCE_EXEC, dis_ra_mask); + + if (ss_type == 1) { + halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); + /* switch ofdm path */ + btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x11); + btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x1); + btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81111111); + /* switch cck patch */ + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x1); */ + /* btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x81); */ + mimo_ps = BTC_MIMO_PS_STATIC; + } else if (ss_type == 2) { + halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x33); + btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x3); + btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81121313); + /* remove, if 0xe77[2]=0x0 then CCK will fail, advised by Jenyu */ + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x0); */ + /* btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x41); */ + mimo_ps = BTC_MIMO_PS_DYNAMIC; + } + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_SEND_MIMO_PS, + &mimo_ps); /* set rx 1ss or 2ss */ +} + +void halbtc8192e2ant_switch_ss_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 new_ss_type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s Switch SS Type = %d\n", + (force_exec ? "force to" : ""), new_ss_type); + BTC_TRACE(trace_buf); + coex_dm->cur_ss_type = new_ss_type; + + if (!force_exec) { + if (coex_dm->pre_ss_type == coex_dm->cur_ss_type) + return; + } + halbtc8192e2ant_set_switch_ss_type(btcoexist, coex_dm->cur_ss_type); + + coex_dm->pre_ss_type = coex_dm->cur_ss_type; +} + +void halbtc8192e2ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + +void halbtc8192e2ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = false; + boolean ap_enable = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if (ap_enable) { + ps_type = BTC_PS_WIFI_NATIVE; + lps_val = 0x0; + rpwm_val = 0x0; + } + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + break; + case BTC_PS_LPS_ON: + halbtc8192e2ant_ps_tdma_check_for_power_save_state( + btcoexist, true); + halbtc8192e2ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + break; + default: + break; + } +} + + +void halbtc8192e2ant_coex_all_off(IN struct btc_coexist *btcoexist) +{ + /* fw all off */ + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* sw all off */ + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + + /* hw all off */ + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + /* force to reset coex mechanism */ + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); + halbtc8192e2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0); + + halbtc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + halbtc8192e2ant_switch_ss_type(btcoexist, FORCE_EXEC, 2); + + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); +} + +void halbtc8192e2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + + + /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);*/ + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); +} + +boolean halbtc8192e2ant_is_common_action(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean common = false, wifi_connected = false, wifi_busy = false; + boolean bt_hs_on = false, low_pwr_disable = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (bt_link_info->sco_exist || bt_link_info->hid_exist) + halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0); + else + halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + + if (!wifi_connected) { + + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non-connected idle!!\n"); + BTC_TRACE(trace_buf); + + if ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) || + (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);*/ + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + } else { + /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);*/ + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); + } + + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, + false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + + common = true; + } else { + if (BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);*/ + + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, + 6); + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + + common = true; + } else if (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status) { + + if (bt_hs_on) + return false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);*/ + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, + 6); + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + + common = true; + } else { + + if (wifi_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); + BTC_TRACE(trace_buf); + common = false; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);*/ + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 21); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, + NORMAL_EXEC, 6); + halbtc8192e2ant_dec_bt_pwr(btcoexist, + NORMAL_EXEC, 0); + halbtc8192e2ant_sw_mechanism1(btcoexist, false, + false, false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, + false, false, 0x18); + common = true; + } + } + } + + return common; +} +void halbtc8192e2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, + IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) +{ + static s32 up, dn, m, n, wait_count; + s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ + u8 retry_count = 0; + + + if (!coex_dm->auto_tdma_adjust) { + coex_dm->auto_tdma_adjust = true; + { + if (sco_hid) { + if (tx_pause) { + if (max_interval == 1) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 13); + coex_dm->ps_tdma_du_adj_type = + 13; + } else if (max_interval == 2) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (max_interval == 3) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } + } else { + if (max_interval == 1) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = + 9; + } else if (max_interval == 2) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (max_interval == 3) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } + } + } else { + if (tx_pause) { + if (max_interval == 1) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 5); + coex_dm->ps_tdma_du_adj_type = + 5; + } else if (max_interval == 2) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (max_interval == 3) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } + } else { + if (max_interval == 1) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = + 1; + } else if (max_interval == 2) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (max_interval == 3) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } + } + } + } + /* ============ */ + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } else { + /* acquire the BT TRx retry count from BT_Info byte2 */ + retry_count = coex_sta->bt_retry_cnt; + result = 0; + wait_count++; + + if (retry_count == + 0) { /* no retry in the last 2-second duration */ + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ + wait_count = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + } + } else if (retry_count <= + 3) { /* <=3 retry in the last 2-second duration */ + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ + if (wait_count <= 2) + m++; /* to avoid loop between the two levels */ + else + m = 1; + + if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ + if (wait_count == 1) + m++; /* to avoid loop between the two levels */ + else + m = 1; + + if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + + if (max_interval == 1) { + if (tx_pause) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 5); + coex_dm->ps_tdma_du_adj_type = 5; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 6); + coex_dm->ps_tdma_du_adj_type = 6; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 4) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 8); + coex_dm->ps_tdma_du_adj_type = 8; + } + if (coex_dm->cur_ps_tdma == 9) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 13); + coex_dm->ps_tdma_du_adj_type = 13; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + coex_dm->ps_tdma_du_adj_type = 14; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 16); + coex_dm->ps_tdma_du_adj_type = 16; + } + + if (result == -1) { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 8); + coex_dm->ps_tdma_du_adj_type = + 8; + } else if (coex_dm->cur_ps_tdma == 13) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 16); + coex_dm->ps_tdma_du_adj_type = + 16; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 8) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 5); + coex_dm->ps_tdma_du_adj_type = + 5; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 13); + coex_dm->ps_tdma_du_adj_type = + 13; + } + } + } else { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 1); + coex_dm->ps_tdma_du_adj_type = 1; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 8) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 4); + coex_dm->ps_tdma_du_adj_type = 4; + } + if (coex_dm->cur_ps_tdma == 13) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 10); + coex_dm->ps_tdma_du_adj_type = 10; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 12); + coex_dm->ps_tdma_du_adj_type = 12; + } + + if (result == -1) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 4); + coex_dm->ps_tdma_du_adj_type = + 4; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 12); + coex_dm->ps_tdma_du_adj_type = + 12; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 4) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = + 1; + } else if (coex_dm->cur_ps_tdma == 1) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 71); + coex_dm->ps_tdma_du_adj_type = + 71; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = + 9; + } + } + } + } else if (max_interval == 2) { + if (tx_pause) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 6); + coex_dm->ps_tdma_du_adj_type = 6; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 6); + coex_dm->ps_tdma_du_adj_type = 6; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 4) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 8); + coex_dm->ps_tdma_du_adj_type = 8; + } + if (coex_dm->cur_ps_tdma == 9) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + coex_dm->ps_tdma_du_adj_type = 14; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + coex_dm->ps_tdma_du_adj_type = 14; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 16); + coex_dm->ps_tdma_du_adj_type = 16; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 8); + coex_dm->ps_tdma_du_adj_type = + 8; + } else if (coex_dm->cur_ps_tdma == 13) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 16); + coex_dm->ps_tdma_du_adj_type = + 16; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 8) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } + } + } else { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 8) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 4); + coex_dm->ps_tdma_du_adj_type = 4; + } + if (coex_dm->cur_ps_tdma == 13) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 10); + coex_dm->ps_tdma_du_adj_type = 10; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 10); + coex_dm->ps_tdma_du_adj_type = 10; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 12); + coex_dm->ps_tdma_du_adj_type = 12; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 4); + coex_dm->ps_tdma_du_adj_type = + 4; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 12); + coex_dm->ps_tdma_du_adj_type = + 12; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 4) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } + } + } + } else if (max_interval == 3) { + if (tx_pause) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 4) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 8); + coex_dm->ps_tdma_du_adj_type = 8; + } + if (coex_dm->cur_ps_tdma == 9) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 16); + coex_dm->ps_tdma_du_adj_type = 16; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 8); + coex_dm->ps_tdma_du_adj_type = + 8; + } else if (coex_dm->cur_ps_tdma == 13) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 16); + coex_dm->ps_tdma_du_adj_type = + 16; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 8) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } + } + } else { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 8) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 4); + coex_dm->ps_tdma_du_adj_type = 4; + } + if (coex_dm->cur_ps_tdma == 13) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8192e2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 12); + coex_dm->ps_tdma_du_adj_type = 12; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 4); + coex_dm->ps_tdma_du_adj_type = + 4; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 12); + coex_dm->ps_tdma_du_adj_type = + 12; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 4) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8192e2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } + } + } + } + } + + /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ + /* then we have to adjust it back to the previous record one. */ + if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { + boolean scan = false, link = false, roam = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", + coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + if (!scan && !link && !roam) + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + coex_dm->ps_tdma_du_adj_type); + else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); + BTC_TRACE(trace_buf); + } + } +} + +/* ****************** + * pstdma for wifi rssi low + * ****************** */ +void halbtc8192e2ant_tdma_duration_adjust_for_wifi_rssi_low( + IN struct btc_coexist *btcoexist/* , */ /* IN u8 wifi_status */) +{ + static s32 up, dn, m, n, wait_count; + s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ + u8 retry_count = 0, bt_info_ext; + + coex_dm->auto_tdma_adjust = false; + + retry_count = coex_sta->bt_retry_cnt; + bt_info_ext = coex_sta->bt_info_ext; + + if (!coex_dm->auto_tdma_adjust_low_rssi) { + coex_dm->auto_tdma_adjust_low_rssi = true; + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 81); + coex_dm->ps_tdma_du_adj_type = 81; + /* ============ */ + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } else { + /* acquire the BT TRx retry count from BT_Info byte2 + * retry_count = coex_sta->bt_retry_cnt; + * bt_info_ext = coex_sta->bt_info_ext; */ + result = 0; + wait_count++; + + if ((coex_sta->low_priority_tx) > 1050 || + (coex_sta->low_priority_rx) > 1250) + retry_count++; + + if (retry_count == + 0) { /* no retry in the last 2-second duration */ + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ + wait_count = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + } + } else if (retry_count <= + 3) { /* <=3 retry in the last 2-second duration */ + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ + if (wait_count <= 2) + m++; /* to avoid loop between the two levels */ + else + m = 1; + + if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ + if (wait_count == 1) + m++; /* to avoid loop between the two levels */ + else + m = 1; + + if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + + if (result == -1) { + if (coex_dm->cur_ps_tdma == 80) { + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 81); + coex_dm->ps_tdma_du_adj_type = 81; + } else if (coex_dm->cur_ps_tdma == 81) { + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 82); + coex_dm->ps_tdma_du_adj_type = 82; + } else if (coex_dm->cur_ps_tdma == 82) { + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 83); + coex_dm->ps_tdma_du_adj_type = 83; + } else if (coex_dm->cur_ps_tdma == 83) { + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 84); + coex_dm->ps_tdma_du_adj_type = 84; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 84) { + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 83); + coex_dm->ps_tdma_du_adj_type = 83; + } else if (coex_dm->cur_ps_tdma == 83) { + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 82); + coex_dm->ps_tdma_du_adj_type = 82; + } else if (coex_dm->cur_ps_tdma == 82) { + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 81); + coex_dm->ps_tdma_du_adj_type = 81; + } else if ((coex_dm->cur_ps_tdma == 81) && + (coex_sta->scan_ap_num <= 5)) { + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 81); + coex_dm->ps_tdma_du_adj_type = 81; + } + } + + if (coex_dm->cur_ps_tdma != 80 && + coex_dm->cur_ps_tdma != 81 && + coex_dm->cur_ps_tdma != 82 && + coex_dm->cur_ps_tdma != 83 && + coex_dm->cur_ps_tdma != 84) { + /* recover to previous adjust type */ + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + coex_dm->ps_tdma_du_adj_type); + } + } +} + + +void halbtc8192e2ant_get_bt_rssi_threshold(IN struct btc_coexist *btcoexist, + IN u8 *pThres0, IN u8 *pThres1) +{ + u8 ant_type; + + struct btc_board_info *board_info = &btcoexist->board_info; + + ant_type = board_info->ant_type; + + switch (ant_type) { + case BTC_ANT_TYPE_0: + *pThres0 = 100; + *pThres1 = 100; + break; + case BTC_ANT_TYPE_1: + *pThres0 = 34; + *pThres1 = 42; + break; + case BTC_ANT_TYPE_2: + *pThres0 = 34; + *pThres1 = 42; + break; + case BTC_ANT_TYPE_3: + *pThres0 = 34; + *pThres1 = 42; + break; + case BTC_ANT_TYPE_4: + *pThres0 = 34; + *pThres1 = 42; + break; + default: + break; + } +} + + + + +/* SCO only or SCO+PAN(HS) */ +void halbtc8192e2ant_action_sco(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, + &bt_thresh1); + bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + + wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + else + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + else + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + + + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); +} + +void halbtc8192e2ant_action_sco_pan(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + + halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, + &bt_thresh1); + bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + + wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + + if ((BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))) + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + else + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); + else + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); + + halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + else + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); +} + + +void halbtc8192e2ant_action_hid(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 anttype = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype); + + wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); + + if (anttype == 0) { + /*ANTTYPE = 0 92E 2ant with SPDT*/ + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (anttype == 1) { + /*92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation*/ + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (anttype == 2) { + /*ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation*/ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) { + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 9); + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + } else { + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 9); + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + } + } else if (anttype == 3) { + /*ANTTYPE = 3, 92E 3ant with good ant. isolation*/ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) { + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + } else { + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + } + } + + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); +} + +/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ +void halbtc8192e2ant_action_a2dp(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + boolean long_dist = false; + u8 anttype = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype); + + wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); + + if (anttype == 0) { + /*ANTTYPE = 0 92E 2ant with SPDT*/ + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 87); + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + } else if (anttype == 1) { + /*92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation*/ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) { + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 25); + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } else { + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 87); + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } + } else if (anttype == 2) { + /*ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation*/ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) { + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 22); + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 5); + } else { + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 87); + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } + } else if (anttype == 3) { + /*ANTTYPE = 3, 92E 3ant with good ant. isolation*/ + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } + + halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, true, + 0x06); + else + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); +} + +void halbtc8192e2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + + wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); + + halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + + if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 2); + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { + halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false, + 2); + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false, + 2); + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); + } + + /* sw mechanism */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, + true, 0x6); + } else { + halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, + true, 0x6); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, + true, 0x6); + } else { + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, + true, 0x6); + } + } +} + +void halbtc8192e2ant_action_pan_edr(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, + &bt_thresh1); + bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + /* wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, 0); */ + wifi_rssi_state = BTC_RSSI_STATE_LOW; + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + else + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); + else + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85); + + halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + else + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); +} + +/* PAN(HS) only */ +void halbtc8192e2ant_action_pan_hs(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + + wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); + + /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);*/ + halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + + if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) + halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +/* PAN(EDR)+A2DP */ +void halbtc8192e2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, + &bt_thresh1); + bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + /* wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, 0); */ + wifi_rssi_state = BTC_RSSI_STATE_LOW; + + if ((BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))) + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + else + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 4); + else + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); + + halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + else + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + +} + +void halbtc8192e2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, + &bt_thresh1); + bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + + wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + + if ((BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))) + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + else + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); + else + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); + + halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + else + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + + +} + +/* HID+A2DP+PAN(EDR) */ +void halbtc8192e2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, + &bt_thresh1); + bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + + if ((BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))) + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + else + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 4); + else + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); + + halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + else + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); +} + +void halbtc8192e2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0, anttype = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype); + + wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); + + if (anttype == 0) { + /*92E 2ant with SPDT*/ + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 87); + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + } else if (anttype == 1) { + /*92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation*/ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) { + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 25); + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + } else { + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 87); + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + } + } else if (anttype == 2) { + /*ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation*/ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) { + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 25); + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + } else { + halbtc8192e2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 87); + halbtc8192e2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + } + } else if (anttype == 3) { + /*ANTTYPE = 3, 92E 3ant with good ant. isolation*/ + halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } + + halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, true, + 0x06); + else + halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); +} + +void halbtc8192e2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + u8 algorithm = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + algorithm = halbtc8192e2ant_action_algorithm(btcoexist); + if (coex_sta->c2h_bt_inquiry_page && + (BT_8192E_2ANT_COEX_ALGO_PANHS != algorithm)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_action_bt_inquiry(btcoexist); + return; + } + + coex_dm->cur_algorithm = algorithm; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", + coex_dm->cur_algorithm); + BTC_TRACE(trace_buf); + + if (halbtc8192e2ant_is_common_action(btcoexist)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant common.\n"); + BTC_TRACE(trace_buf); + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + + } else { + if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", + coex_dm->pre_algorithm, coex_dm->cur_algorithm); + BTC_TRACE(trace_buf); + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + + } + switch (coex_dm->cur_algorithm) { + case BT_8192E_2ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_action_sco(btcoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_SCO_PAN: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = SCO+PAN(EDR).\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_action_sco_pan(btcoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID.\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_action_hid(btcoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_action_a2dp(btcoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_action_a2dp_pan_hs(btcoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_action_pan_edr(btcoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_action_pan_hs(btcoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_action_pan_edr_a2dp(btcoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_action_pan_edr_hid(btcoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_action_hid_a2dp_pan_edr( + btcoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_action_hid_a2dp(btcoexist); + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = unknown!!\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_coex_all_off(btcoexist); + break; + } + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + } +} + +void halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean back_up) +{ + u16 u16tmp = 0; + u8 u8tmp = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 2Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + if (back_up) { + /* backup rf 0x1e value */ + coex_dm->bt_rf_0x1e_backup = + btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, + 0xfffff); + + coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, + 0x430); + coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, + 0x434); + coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( + btcoexist, 0x42a); + coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( + btcoexist, 0x456); + } + + /* antenna sw ctrl to bt */ + halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, false); + + halbtc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + /* antenna switch control parameter */ + /* btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555); */ + + /* coex parameters */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); + /* 0x790[5:0]=0x5 */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); + u8tmp &= 0xc0; + u8tmp |= 0x5; + btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); + + /* enable counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); + + /* enable PTA */ + btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); + /* enable mailbox interface */ + u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40); + u16tmp |= BIT(9); + btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp); + + /* enable PTA I2C mailbox */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101); + u8tmp |= BIT(4); + btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp); + + /* enable bt clock when wifi is disabled. */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93); + u8tmp |= BIT(0); + btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp); + /* enable bt clock when suspend. */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); + u8tmp |= BIT(0); + btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); + + /* Give bt_coex_supported_version the default value */ + coex_sta->bt_coex_supported_version = 0; +} + +/* ************************************************************ + * work around function start with wa_halbtc8192e2ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8192e2ant_ + * ************************************************************ */ +void ex_halbtc8192e2ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ +} + +void ex_halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8192e2ant_init_hw_config(btcoexist, true); +} + +void ex_halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + halbtc8192e2ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8192e2ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_stack_info *stack_info = &btcoexist->stack_info; + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u16 u16tmp[4]; + u32 u32tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + u32 phyver = 0; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", + "Ant PG number/ Ant mechanism:", + board_info->pg_ant_num, board_info->btdm_ant_num); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Antenna type:", + board_info->ant_type); + CL_PRINTF(cli_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant, + glcoex_ver_btdesired_8192e_2ant, bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : (bt_coex_ver >= + glcoex_ver_btdesired_8192e_2ant ? "Match" : + "Mis-Match"))); + CL_PRINTF(cli_buf); + + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d", + "W_FW/ B_FW/ Phy", fw_ver, bt_patch_ver, phyver); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "Wifi channel informed to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", + "BT [status/ rssi/ retryCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") + : ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi, coex_sta->bt_retry_cnt); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", + "SCO/HID/PAN/A2DP", + stack_info->sco_exist, stack_info->hid_exist, + stack_info->pan_exist, stack_info->a2dp_exist); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); + + bt_info_ext = coex_sta->bt_info_ext; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "BT Info A2DP rate", + (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); + CL_PRINTF(cli_buf); + + for (i = 0; i < BT_INFO_SRC_8192E_2ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8192e_2ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "SS Type", + coex_dm->cur_ss_type); + CL_PRINTF(cli_buf); + + /* Sw mechanism */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Sw mechanism]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", + "SM1[ShRf/ LpRA/ LimDig]", + coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, + coex_dm->limited_dig); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", + "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", + coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, + coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); + CL_PRINTF(cli_buf); + + /* Fw mechanism */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Fw mechanism]============"); + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", + "PS TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + coex_dm->auto_tdma_adjust); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", + "DecBtPwr/ IgnWlanAct", + coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act); + CL_PRINTF(cli_buf); + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", + "RF-A, 0x1e initVal", + coex_dm->bt_rf_0x1e_backup); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", + "backup ARFR1/ARFR2/RL/AMaxTime", + coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2, + coex_dm->backup_retry_limit, + coex_dm->backup_ampdu_max_time); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); + u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", + "0x430/0x434/0x42a/0x456", + u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0xc04/ 0xd04/ 0x90c", + u32tmp[0], u32tmp[1], u32tmp[2]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", + u8tmp[0]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x92c/ 0x930", + (u8tmp[0]), u32tmp[0]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x40/ 0x4f", + u8tmp[0], u8tmp[1]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x550(bcn ctrl)/0x522", + u32tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", + u32tmp[0]); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_CCK); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11n-agg", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_Err CCK/11g/11n/11n-agg", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", + u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(hp rx[31:16]/tx[15:0])", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x774(lp rx[31:16]/tx[15:0])", + coex_sta->low_priority_rx, coex_sta->low_priority_tx); + CL_PRINTF(cli_buf); +#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 1) + halbtc8192e2ant_monitor_bt_ctr(btcoexist); +#endif + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +void ex_halbtc8192e2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = true; + halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, + true); + halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = false; + halbtc8192e2ant_init_hw_config(btcoexist, false); + halbtc8192e2ant_init_coex_dm(btcoexist); + halbtc8192e2ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8192e2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = true; + + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = false; + } +} + +void ex_halbtc8192e2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (BTC_SCAN_START == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify\n"); + BTC_TRACE(trace_buf); + } else if (BTC_SCAN_FINISH == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + + } +} + +void ex_halbtc8192e2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (BTC_ASSOCIATE_START == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify\n"); + BTC_TRACE(trace_buf); + } else if (BTC_ASSOCIATE_FINISH == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify\n"); + BTC_TRACE(trace_buf); + } +} + +void ex_halbtc8192e2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm || + coex_sta->bt_disabled) + return; + + if (BTC_MEDIA_CONNECT == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + } + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + h2c_parameter[0] = 0x1; + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); +} + +void ex_halbtc8192e2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (type == BTC_PACKET_DHCP) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], DHCP Packet notify\n"); + BTC_TRACE(trace_buf); + } +} + +void ex_halbtc8192e2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 bt_info = 0; + u8 i, rsp_source = 0; + boolean bt_busy = false, limited_dig = false; + boolean wifi_connected = false; + + coex_sta->c2h_bt_info_req_sent = false; + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8192E_2ANT_MAX) + rsp_source = BT_INFO_SRC_8192E_2ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + if (i == 1) + bt_info = tmp_buf[i]; + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + if (BT_INFO_SRC_8192E_2ANT_WIFI_FW != rsp_source) { + coex_sta->bt_retry_cnt = /* [3:0] */ + coex_sta->bt_info_c2h[rsp_source][2] & 0xf; + + coex_sta->bt_rssi = + coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; + + coex_sta->bt_info_ext = + coex_sta->bt_info_c2h[rsp_source][4]; + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + if (wifi_connected) + ex_halbtc8192e2ant_media_status_notify( + btcoexist, BTC_MEDIA_CONNECT); + else + ex_halbtc8192e2ant_media_status_notify( + btcoexist, BTC_MEDIA_DISCONNECT); + } + + if ((coex_sta->bt_info_ext & BIT(3))) { + if (!btcoexist->manual_control && + !btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8192e2ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, false); + } + } else { + /* BT already NOT ignore Wlan active, do nothing here. */ + } + +#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0) + if ((coex_sta->bt_info_ext & BIT(4))) { + /* BT auto report already enabled, do nothing */ + } else + halbtc8192e2ant_bt_auto_report(btcoexist, FORCE_EXEC, + true); +#endif + } + + /* check BIT2 first ==> check if bt is under inquiry or page scan */ + if (bt_info & BT_INFO_8192E_2ANT_B_INQ_PAGE) + coex_sta->c2h_bt_inquiry_page = true; + else + coex_sta->c2h_bt_inquiry_page = false; + + /* set link exist status */ + if (!(bt_info & BT_INFO_8192E_2ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (bt_info & BT_INFO_8192E_2ANT_B_FTP) + coex_sta->pan_exist = true; + else + coex_sta->pan_exist = false; + if (bt_info & BT_INFO_8192E_2ANT_B_A2DP) + coex_sta->a2dp_exist = true; + else + coex_sta->a2dp_exist = false; + if (bt_info & BT_INFO_8192E_2ANT_B_HID) + coex_sta->hid_exist = true; + else + coex_sta->hid_exist = false; + if (bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO) + coex_sta->sco_exist = true; + else + coex_sta->sco_exist = false; + } + + halbtc8192e2ant_update_bt_link_info(btcoexist); + + if (!(bt_info & BT_INFO_8192E_2ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info == + BT_INFO_8192E_2ANT_B_CONNECTION) { /* connection exists but no busy */ + coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + BTC_TRACE(trace_buf); + } else if ((bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO) || + (bt_info & BT_INFO_8192E_2ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info & BT_INFO_8192E_2ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + BTC_TRACE(trace_buf); + } + + if ((BT_8192E_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8192E_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { + bt_busy = true; + limited_dig = true; + } else { + bt_busy = false; + limited_dig = false; + } + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + coex_dm->limited_dig = limited_dig; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); + + halbtc8192e2ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8192e2ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true); + halbtc8192e2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + ex_halbtc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); +} + +void ex_halbtc8192e2ant_periodical(IN struct btc_coexist *btcoexist) +{ + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + coex_sta->bt_coex_supported_version = + btcoexist->btc_get_bt_coex_supported_version(btcoexist); + +#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0) + halbtc8192e2ant_query_bt_info(btcoexist); + halbtc8192e2ant_monitor_bt_ctr(btcoexist); + halbtc8192e2ant_monitor_wifi_ctr(btcoexist); + halbtc8192e2ant_monitor_bt_enable_disable(btcoexist); +#else + halbtc8192e2ant_monitor_wifi_ctr(btcoexist); + + if (halbtc8192e2ant_is_wifi_status_changed(btcoexist) || + coex_dm->auto_tdma_adjust) + halbtc8192e2ant_run_coexist_mechanism(btcoexist); +#endif +} + +#endif + +#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ + + diff --git a/hal/btc/halbtc8192e2ant.h b/hal/btc/halbtc8192e2ant.h new file mode 100644 index 0000000..b77b3c4 --- /dev/null +++ b/hal/btc/halbtc8192e2ant.h @@ -0,0 +1,225 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8192E_SUPPORT == 1) +/* ******************************************* + * The following is for 8192E 2Ant BT Co-exist definition + * ******************************************* */ +#define BT_AUTO_REPORT_ONLY_8192E_2ANT 0 + +#define BT_INFO_8192E_2ANT_B_FTP BIT(7) +#define BT_INFO_8192E_2ANT_B_A2DP BIT(6) +#define BT_INFO_8192E_2ANT_B_HID BIT(5) +#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8192E_2ANT_B_CONNECTION BIT(0) + +#define BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT 2 +#define NOISY_AP_NUM_THRESH_8192E 10 + +enum bt_info_src_8192e_2ant { + BT_INFO_SRC_8192E_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8192E_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8192E_2ANT_MAX +}; + +enum bt_8192e_2ant_bt_status { + BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8192E_2ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8192E_2ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8192E_2ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8192E_2ANT_BT_STATUS_MAX +}; + +enum bt_8192e_2ant_coex_algo { + BT_8192E_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8192E_2ANT_COEX_ALGO_SCO = 0x1, + BT_8192E_2ANT_COEX_ALGO_SCO_PAN = 0x2, + BT_8192E_2ANT_COEX_ALGO_HID = 0x3, + BT_8192E_2ANT_COEX_ALGO_A2DP = 0x4, + BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS = 0x5, + BT_8192E_2ANT_COEX_ALGO_PANEDR = 0x6, + BT_8192E_2ANT_COEX_ALGO_PANHS = 0x7, + BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8, + BT_8192E_2ANT_COEX_ALGO_PANEDR_HID = 0x9, + BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa, + BT_8192E_2ANT_COEX_ALGO_HID_A2DP = 0xb, + BT_8192E_2ANT_COEX_ALGO_MAX = 0xc +}; + +struct coex_dm_8192e_2ant { + /* fw mechanism */ + u8 pre_bt_dec_pwr_lvl; + u8 cur_bt_dec_pwr_lvl; + u8 pre_fw_dac_swing_lvl; + u8 cur_fw_dac_swing_lvl; + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean reset_tdma_adjust; + boolean auto_tdma_adjust; + boolean auto_tdma_adjust_low_rssi; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + + /* sw mechanism */ + boolean pre_rf_rx_lpf_shrink; + boolean cur_rf_rx_lpf_shrink; + u32 bt_rf_0x1e_backup; + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + boolean pre_dac_swing_on; + u32 pre_dac_swing_lvl; + boolean cur_dac_swing_on; + u32 cur_dac_swing_lvl; + boolean pre_adc_back_off; + boolean cur_adc_back_off; + boolean pre_agc_table_en; + boolean cur_agc_table_en; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + + u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ + u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ + u16 backup_retry_limit; + u8 backup_ampdu_max_time; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + u8 pre_ss_type; + u8 cur_ss_type; + + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + + u32 pre_ra_mask; + u32 cur_ra_mask; + u8 cur_ra_mask_type; + u8 pre_arfr_type; + u8 cur_arfr_type; + u8 pre_retry_limit_type; + u8 cur_retry_limit_type; + u8 pre_ampdu_time_type; + u8 cur_ampdu_time_type; +}; + +struct coex_sta_8192e_2ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + + boolean under_lps; + boolean under_ips; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + u8 bt_rssi; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + boolean c2h_bt_info_req_sent; + u8 bt_info_c2h[BT_INFO_SRC_8192E_2ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8192E_2ANT_MAX]; + boolean c2h_bt_inquiry_page; + u8 bt_retry_cnt; + u8 bt_info_ext; + u8 scan_ap_num; + u32 bt_coex_supported_version; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8192e2ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8192e2ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e2ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8192e2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8192e2ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8192e2ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8192e2ant_display_coex_info(IN struct btc_coexist *btcoexist); + +#else /* #if (RTL8192E_SUPPORT == 1) */ +#define ex_halbtc8192e2ant_power_on_setting(btcoexist) +#define ex_halbtc8192e2ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8192e2ant_init_coex_dm(btcoexist) +#define ex_halbtc8192e2ant_ips_notify(btcoexist, type) +#define ex_halbtc8192e2ant_lps_notify(btcoexist, type) +#define ex_halbtc8192e2ant_scan_notify(btcoexist, type) +#define ex_halbtc8192e2ant_connect_notify(btcoexist, type) +#define ex_halbtc8192e2ant_media_status_notify(btcoexist, type) +#define ex_halbtc8192e2ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8192e2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8192e2ant_halt_notify(btcoexist) +#define ex_halbtc8192e2ant_periodical(btcoexist) +#define ex_halbtc8192e2ant_display_coex_info(btcoexist) + +#endif + +#endif + + diff --git a/hal/btc/halbtc8703b1ant.c b/hal/btc/halbtc8703b1ant.c new file mode 100644 index 0000000..34f11f1 --- /dev/null +++ b/hal/btc/halbtc8703b1ant.c @@ -0,0 +1,4307 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for RTL8703B Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8703B_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8703b_1ant glcoex_dm_8703b_1ant; +static struct coex_dm_8703b_1ant *coex_dm = &glcoex_dm_8703b_1ant; +static struct coex_sta_8703b_1ant glcoex_sta_8703b_1ant; +static struct coex_sta_8703b_1ant *coex_sta = &glcoex_sta_8703b_1ant; +static struct psdscan_sta_8703b_1ant gl_psd_scan_8703b_1ant; +static struct psdscan_sta_8703b_1ant *psd_scan = &gl_psd_scan_8703b_1ant; + + +const char *const glbt_info_src_8703b_1ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; +/* ************************************************************ + * BtCoex Version Format: + * 1. date : glcoex_ver_date_XXXXX_1ant + * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant + * 3. BtCoexVersion : glcoex_ver_btdesired_XXXXX_1ant + * 4. others : glcoex_ver_XXXXXX_XXXXX_1ant + * + * Variable should be indicated IC and Antenna numbers !!! + * Please strictly follow this order and naming style !!! + * + * ************************************************************ */ +u32 glcoex_ver_date_8703b_1ant = 20161027; +u32 glcoex_ver_8703b_1ant = 0x0f; +u32 glcoex_ver_btdesired_8703b_1ant = 0x0d; + + +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8703b1ant_ + * ************************************************************ */ +u8 halbtc8703b1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_bt_rssi_state; + } + + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + +u8 halbtc8703b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_wifi_rssi_state[index]; + } + + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; + + return wifi_rssi_state; +} + +void halbtc8703b1ant_update_ra_mask(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 dis_rate_mask) +{ + coex_dm->cur_ra_mask = dis_rate_mask; + + if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) + btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, + &coex_dm->cur_ra_mask); + coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; +} + +void halbtc8703b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + boolean wifi_under_b_mode = false; + + coex_dm->cur_arfr_type = type; + + if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { + switch (coex_dm->cur_arfr_type) { + case 0: /* normal mode */ + btcoexist->btc_write_4byte(btcoexist, 0x430, + coex_dm->backup_arfr_cnt1); + btcoexist->btc_write_4byte(btcoexist, 0x434, + coex_dm->backup_arfr_cnt2); + break; + case 1: + btcoexist->btc_get(btcoexist, + BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + if (wifi_under_b_mode) { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x01010101); + } else { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x04030201); + } + break; + default: + break; + } + } + + coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; +} + +void halbtc8703b1ant_retry_limit(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_retry_limit_type = type; + + if (force_exec || + (coex_dm->pre_retry_limit_type != + coex_dm->cur_retry_limit_type)) { + switch (coex_dm->cur_retry_limit_type) { + case 0: /* normal mode */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + coex_dm->backup_retry_limit); + break; + case 1: /* retry limit=8 */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + 0x0808); + break; + default: + break; + } + } + + coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; +} + +void halbtc8703b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_ampdu_time_type = type; + + if (force_exec || + (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { + switch (coex_dm->cur_ampdu_time_type) { + case 0: /* normal mode */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + coex_dm->backup_ampdu_max_time); + break; + case 1: /* AMPDU timw = 0x38 * 32us */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + 0x38); + break; + default: + break; + } + } + + coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; +} + +void halbtc8703b1ant_limited_tx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, + IN u8 retry_limit_type, IN u8 ampdu_time_type) +{ + switch (ra_mask_type) { + case 0: /* normal mode */ + halbtc8703b1ant_update_ra_mask(btcoexist, force_exec, + 0x0); + break; + case 1: /* disable cck 1/2 */ + halbtc8703b1ant_update_ra_mask(btcoexist, force_exec, + 0x00000003); + break; + case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ + halbtc8703b1ant_update_ra_mask(btcoexist, force_exec, + 0x0001f1f7); + break; + default: + break; + } + + halbtc8703b1ant_auto_rate_fallback_retry(btcoexist, force_exec, + arfr_type); + halbtc8703b1ant_retry_limit(btcoexist, force_exec, retry_limit_type); + halbtc8703b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); +} + +void halbtc8703b1ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +void halbtc8703b1ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); +} + +void halbtc8703b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, + cnt_autoslot_hang = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ + /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + if (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + if (coex_sta->high_priority_rx >= 15) { + if (cnt_overhead < 3) + cnt_overhead++; + + if (cnt_overhead == 3) + coex_sta->is_hiPri_rx_overhead = true; + } else { + if (cnt_overhead > 0) + cnt_overhead--; + + if (cnt_overhead == 0) + coex_sta->is_hiPri_rx_overhead = false; + } + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); + + BTC_TRACE(trace_buf); + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + + if ((coex_sta->low_priority_tx > 1150) && + (!coex_sta->c2h_bt_inquiry_page)) + coex_sta->pop_event_cnt++; + + if ((coex_sta->low_priority_rx >= 1150) && + (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) + && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && + (coex_sta->bt_link_exist)) { + if (cnt_slave >= 2) { + bt_link_info->slave_role = true; + cnt_slave = 2; + } else + cnt_slave++; + } else { + if (cnt_slave == 0) { + bt_link_info->slave_role = false; + cnt_slave = 0; + } else + cnt_slave--; + + } + + if (coex_sta->is_tdma_btautoslot) { + if ((coex_sta->low_priority_tx >= 1300) && + (coex_sta->low_priority_rx <= 150)) { + if (cnt_autoslot_hang >= 2) { + coex_sta->is_tdma_btautoslot_hang = true; + cnt_autoslot_hang = 2; + } else + cnt_autoslot_hang++; + } else { + if (cnt_autoslot_hang == 0) { + coex_sta->is_tdma_btautoslot_hang = false; + cnt_autoslot_hang = 0; + } else + cnt_autoslot_hang--; + } + } + + if (!coex_sta->bt_disabled) { + if ((coex_sta->high_priority_tx == 0) && + (coex_sta->high_priority_rx == 0) && + (coex_sta->low_priority_tx == 0) && + (coex_sta->low_priority_rx == 0)) { + num_of_bt_counter_chk++; + if (num_of_bt_counter_chk >= 3) { + halbtc8703b1ant_query_bt_info(btcoexist); + num_of_bt_counter_chk = 0; + } + } + } + +} + + +void halbtc8703b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ +#if 1 + s32 wifi_rssi = 0; + boolean wifi_busy = false, wifi_under_b_mode = false, + wifi_scan = false; + boolean bt_idle = false, wl_idle = false; + static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, + wl_noisy_count1 = 3, wl_noisy_count2 = 0; + u32 total_cnt, reg_val1, reg_val2, cck_cnt; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_VHT); + + cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; + + if (cck_cnt > 250) { + if (wl_noisy_count2 < 3) + wl_noisy_count2++; + + if (wl_noisy_count2 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count1 = 0; + } + } else if (cck_cnt < 50) { + if (wl_noisy_count0 < 3) + wl_noisy_count0++; + + if (wl_noisy_count0 == 3) { + wl_noisy_count1 = 0; + wl_noisy_count2 = 0; + } + } else { + if (wl_noisy_count1 < 3) + wl_noisy_count1++; + + if (wl_noisy_count1 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count2 = 0; + } + } + + if (wl_noisy_count2 == 3) + coex_sta->wl_noisy_level = 2; + else if (wl_noisy_count1 == 3) + coex_sta->wl_noisy_level = 1; + else + coex_sta->wl_noisy_level = 0; + + if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { + total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht; + + if ((coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_SCO_BUSY)) { + if (coex_sta->crc_ok_cck > (total_cnt - + coex_sta->crc_ok_cck)) { + if (cck_lock_counter < 3) + cck_lock_counter++; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + if (!coex_sta->pre_ccklock) { + + if (cck_lock_counter >= 3) + coex_sta->cck_lock = true; + else + coex_sta->cck_lock = false; + } else { + if (cck_lock_counter == 0) + coex_sta->cck_lock = false; + else + coex_sta->cck_lock = true; + } + + if (coex_sta->cck_lock) + coex_sta->cck_ever_lock = true; + + coex_sta->pre_ccklock = coex_sta->cck_lock; + +#endif +} + + + +boolean halbtc8703b1ant_is_wifibt_status_changed(IN struct btc_coexist + *btcoexist) +{ + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false, pre_bt_off = false, pre_bt_slave = false; + static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (coex_sta->bt_disabled != pre_bt_off) { + pre_bt_off = coex_sta->bt_disabled; + + if (coex_sta->bt_disabled) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + + return true; + } + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { + pre_wl_noisy_level = coex_sta->wl_noisy_level; + return true; + } + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->hid_busy_num != pre_hid_busy_num) { + pre_hid_busy_num = coex_sta->hid_busy_num; + return true; + } + } + + if (bt_link_info->slave_role != pre_bt_slave) { + pre_bt_slave = bt_link_info->slave_role; + return true; + } + + return false; +} + + +void halbtc8703b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + boolean bt_busy = false; + + + coex_sta->num_of_profile = 0; + + /* set link exist status */ + if (!(coex_sta->bt_info & BT_INFO_8703B_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_FTP) { + coex_sta->pan_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->pan_exist = false; + + if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_A2DP) { + coex_sta->a2dp_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->a2dp_exist = false; + + if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_HID) { + coex_sta->hid_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->hid_exist = false; + + if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) { + coex_sta->sco_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->sco_exist = false; + + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + bt_link_info->acl_busy = coex_sta->acl_busy; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = true; + bt_link_info->bt_link_exist = true; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = true; + else + bt_link_info->sco_only = false; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = true; + else + bt_link_info->a2dp_only = false; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = true; + else + bt_link_info->pan_only = false; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = true; + else + bt_link_info->hid_only = false; + + if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_INQ_PAGE) { + coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_INQ_PAGE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); + } else if (!(coex_sta->bt_info & BT_INFO_8703B_1ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + } else if (coex_sta->bt_info == BT_INFO_8703B_1ANT_B_CONNECTION) { + /* connection exists but no busy */ + coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + } else if (((coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_BUSY)) && + (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_ACL_BUSY)) { + coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); + } else if ((coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + } else if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + } else { + coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + } + + BTC_TRACE(trace_buf); + + if ((BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + bt_busy = true; + else + bt_busy = false; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); +} + + +void halbtc8703b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + h2c_parameter[0] = + 0x1; /* enable BT AFH skip WL channel for 8703b because BT Rx LO interference */ + /* h2c_parameter[0] = 0x0; */ + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); + +} + +void halbtc8703b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean enable_auto_report) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = 0; + + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); + + btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); +} + +void halbtc8703b1ant_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable_auto_report) +{ + coex_dm->cur_bt_auto_report = enable_auto_report; + + if (!force_exec) { + if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) + return; + } + halbtc8703b1ant_set_bt_auto_report(btcoexist, + coex_dm->cur_bt_auto_report); + + coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; +} + +void halbtc8703b1ant_set_fw_low_penalty_ra(IN struct btc_coexist + *btcoexist, IN boolean low_penalty_ra) +{ + u8 h2c_parameter[6] = {0}; + + h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ + + if (low_penalty_ra) { + h2c_parameter[1] |= BIT(0); + h2c_parameter[2] = + 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ + h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ + h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ + h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ + } + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); +} + +void halbtc8703b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) + return; + } + + halbtc8703b1ant_set_fw_low_penalty_ra(btcoexist, + coex_dm->cur_low_penalty_ra); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; +} + +void halbtc8703b1ant_write_score_board( + IN struct btc_coexist *btcoexist, + IN u16 bitpos, + IN boolean state +) +{ + + static u16 originalval = 0x8002; + + if (state) + originalval = originalval | bitpos; + else + originalval = originalval & (~bitpos); + + + btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); +#if 0 + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "\n [BTCoex], ********** Write Scoreboard = %x**********\n", + originalval); + BTC_TRACE(trace_buf); +#endif + +} + +void halbtc8703b1ant_read_score_board( + IN struct btc_coexist *btcoexist, + IN u16 *score_board_val +) +{ + + *score_board_val = (btcoexist->btc_read_2byte(btcoexist, + 0xaa)) & 0x7fff; +} + +void halbtc8703b1ant_post_state_to_bt( + IN struct btc_coexist *btcoexist, + IN u16 type, + IN boolean state +) +{ + halbtc8703b1ant_write_score_board(btcoexist, (u16) type, state); +} + +void halbtc8703b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = true, bt_disabled = false; + u16 u16tmp; + + /* This function check if bt is disabled */ +#if 1 + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = false; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = false; + + +#else /* 8703b BT can't show correct on/off status in scoreboard[1] 2015/11/26 */ + + halbtc8703b1ant_read_score_board(btcoexist, &u16tmp); + + bt_active = u16tmp & BIT(1); + + +#endif + + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } else { + + bt_disable_cnt++; + if (bt_disable_cnt >= 2) { + bt_disabled = true; + bt_disable_cnt = 2; + } + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } + + if (bt_disabled) + halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); + else + halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true); + + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + + } +} + + + +void halbtc8703b1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, + IN boolean isenable) +{ + +#if (BT_8703B_1ANT_ENABLE_GNTBT_TO_GPIO14 == 1) + if (isenable) { + /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); + + /* enable GNT_BT debug to GPIO */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0); + } else { + /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); + + /* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1); + } +#endif +} + +u32 halbtc8703b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, + IN u16 reg_addr) +{ + u32 j = 0; + + + /* wait for ready bit before access 0x7c0 */ + btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr); + + do { + j++; + } while (((btcoexist->btc_read_1byte(btcoexist, + 0x7c3)&BIT(5)) == 0) && + (j < BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); + + + return btcoexist->btc_read_4byte(btcoexist, + 0x7c8); /* get read data */ + +} + +void halbtc8703b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist + *btcoexist, + IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) +{ + u32 val, i = 0, j = 0, bitpos = 0; + + + if (bit_mask == 0x0) + return; + if (bit_mask == 0xffffffff) { + btcoexist->btc_write_4byte(btcoexist, 0x7c4, + reg_value); /* put write data */ + + /* wait for ready bit before access 0x7c0 */ + do { + j++; + } while (((btcoexist->btc_read_1byte(btcoexist, + 0x7c3)&BIT(5)) == 0) && + (j < BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); + + + btcoexist->btc_write_4byte(btcoexist, 0x7c0, + 0xc00F0000 | reg_addr); + } else { + for (i = 0; i <= 31; i++) { + if (((bit_mask >> i) & 0x1) == 0x1) { + bitpos = i; + break; + } + } + + /* read back register value before write */ + val = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, + reg_addr); + val = (val & (~bit_mask)) | (reg_value << bitpos); + + btcoexist->btc_write_4byte(btcoexist, 0x7c4, + val); /* put write data */ + + /* wait for ready bit before access 0x7c0 */ + do { + j++; + } while (((btcoexist->btc_read_1byte(btcoexist, + 0x7c3)&BIT(5)) == 0) && + (j < BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); + + + btcoexist->btc_write_4byte(btcoexist, 0x7c0, + 0xc00F0000 | reg_addr); + + } + +} + +void halbtc8703b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 val; + + val = (enable) ? 1 : 0; + halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, + val); /* 0x38[7] */ + +} + +void halbtc8703b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, + IN boolean wifi_control) +{ + u8 val; + + val = (wifi_control) ? 1 : 0; + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, + val); /* 0x70[26] */ + +} + +void halbtc8703b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; + + val_orig = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + switch (control_block) { + case BT_8703B_1ANT_GNT_BLOCK_RFC_BB: + default: + val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff); + break; + case BT_8703B_1ANT_GNT_BLOCK_RFC: + val = (val << 14) | (val_orig & 0xffff3fff); + break; + case BT_8703B_1ANT_GNT_BLOCK_BB: + val = (val << 10) | (val_orig & 0xfffff3ff); + break; + } + + halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); +} + + +void halbtc8703b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; + + val_orig = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + switch (control_block) { + case BT_8703B_1ANT_GNT_BLOCK_RFC_BB: + default: + val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff); + break; + case BT_8703B_1ANT_GNT_BLOCK_RFC: + val = (val << 12) | (val_orig & 0xffffcfff); + break; + case BT_8703B_1ANT_GNT_BLOCK_BB: + val = (val << 8) | (val_orig & 0xfffffcff); + break; + } + + halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); +} + + +void halbtc8703b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u16 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8703B_1ANT_CTT_WL_VS_LTE: + reg_addr = 0xa0; + break; + case BT_8703B_1ANT_CTT_BT_VS_LTE: + reg_addr = 0xa4; + break; + } + + if (reg_addr != 0x0000) + halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ + + +} + + +void halbtc8703b1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u8 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8703B_1ANT_LBTT_WL_BREAK_LTE: + reg_addr = 0xa8; + break; + case BT_8703B_1ANT_LBTT_BT_BREAK_LTE: + reg_addr = 0xac; + break; + case BT_8703B_1ANT_LBTT_LTE_BREAK_WL: + reg_addr = 0xb0; + break; + case BT_8703B_1ANT_LBTT_LTE_BREAK_BT: + reg_addr = 0xb4; + break; + } + + if (reg_addr != 0x0000) + halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ + + +} + +void halbtc8703b1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 interval, + IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, + IN u8 val0x6c4_b3) +{ + static u8 pre_h2c_parameter[6] = {0}; + u8 cur_h2c_parameter[6] = {0}; + u8 i, match_cnt = 0; + + cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ + + cur_h2c_parameter[1] = interval; + cur_h2c_parameter[2] = val0x6c4_b0; + cur_h2c_parameter[3] = val0x6c4_b1; + cur_h2c_parameter[4] = val0x6c4_b2; + cur_h2c_parameter[5] = val0x6c4_b3; + + if (!force_exec) { + for (i = 1; i <= 5; i++) { + if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) + break; + + match_cnt++; + } + + if (match_cnt == 5) + return; + } + + for (i = 1; i <= 5; i++) + pre_h2c_parameter[i] = cur_h2c_parameter[i]; + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); +} + + +void halbtc8703b1ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8703b1ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8703b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8703b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + u32 break_table; + u8 select_table; + + coex_sta->coex_table_type = type; + + if (coex_sta->concurrent_rx_mode_on == true) { + break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ + select_table = + 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ + } else { + break_table = 0xffffff; + select_table = 0x3; + } + + switch (type) { + case 0: + halbtc8703b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, break_table, + select_table); + break; + case 1: + halbtc8703b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 2: + halbtc8703b1ant_coex_table(btcoexist, force_exec, + 0xaa5a5a5a, 0xaa5a5a5a, break_table, + select_table); + break; + case 3: + halbtc8703b1ant_coex_table(btcoexist, force_exec, + 0xaa555555, 0xaa5a5a5a, break_table, + select_table); + break; + case 4: + halbtc8703b1ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 5: + halbtc8703b1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, break_table, + select_table); + break; + case 6: + halbtc8703b1ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 7: + halbtc8703b1ant_coex_table(btcoexist, force_exec, + 0xaaaaaaaa, 0xaaaaaaaa, break_table, + select_table); + break; + case 8: + halbtc8703b1ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xaaaaaaaa, break_table, + select_table); + break; + case 9: + halbtc8703b1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0xaaaa5aaa, break_table, + select_table); + break; + default: + break; + } +} + +void halbtc8703b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 h2c_parameter[1] = {0}; + + if (enable) + h2c_parameter[0] |= BIT(0);/* function enable */ + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + +void halbtc8703b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8703b1ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8703b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8703b1ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8703b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8703b1ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + /*halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); */ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + /*halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8);*/ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + +void halbtc8703b1ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = false; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + /* recover to original 32k low power setting */ + coex_sta->force_lps_on = false; + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + + break; + case BTC_PS_LPS_ON: + coex_sta->force_lps_on = true; + halbtc8703b1ant_ps_tdma_check_for_power_save_state( + btcoexist, true); + halbtc8703b1ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + + break; + case BTC_PS_LPS_OFF: + coex_sta->force_lps_on = false; + halbtc8703b1ant_ps_tdma_check_for_power_save_state( + btcoexist, false); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + + break; + default: + break; + } +} + + + +void halbtc8703b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if (byte5 & BIT(2)) + coex_sta->is_tdma_btautoslot = true; + else + coex_sta->is_tdma_btautoslot = false; + + /* release bt-auto slot for auto-slot hang is detected!! */ + if (coex_sta->is_tdma_btautoslot) + if ((coex_sta->is_tdma_btautoslot_hang) || + (bt_link_info->slave_role)) + byte5 = byte5 & 0xfb; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if (ap_enable) { + if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], FW for 1Ant AP mode\n"); + BTC_TRACE(trace_buf); + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + + halbtc8703b1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + } + } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + + halbtc8703b1ant_power_save_state( + btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + } else { + halbtc8703b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, + 0x0); + } + + + h2c_parameter[0] = real_byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = real_byte5; + + coex_dm->ps_tdma_para[0] = real_byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = real_byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); +} + + +void halbtc8703b1ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = false; + u8 rssi_adjust_val = 0; + static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; + static boolean pre_wifi_busy = false; + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (wifi_busy != pre_wifi_busy) { + force_exec = true; + pre_wifi_busy = wifi_busy; + } + + /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ + if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist)) + psTdmaByte4Modify = 0x1; + else + psTdmaByte4Modify = 0x0; + + if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { + + force_exec = true; + pre_psTdmaByte4Modify = psTdmaByte4Modify; + } + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) + return; + } + + if (coex_dm->cur_ps_tdma_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(on, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } + + if (turn_on) { + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + } + + + if (turn_on) { + switch (type) { + default: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x03, 0x11, 0x11); + break; + + case 3: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x3a, 0x03, 0x10, 0x50); + break; + case 4: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x21, 0x03, 0x10, 0x50); + break; + case 5: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x15, 0x03, 0x11, 0x11); + break; + case 6: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x20, 0x03, 0x11, 0x11); + break; + case 7: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 8: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 9: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x55, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 10: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x30, 0x03, 0x11, 0x10); + break; + case 11: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x65, 0x25, 0x03, 0x11, 0x11 | + psTdmaByte4Modify); + break; + case 12: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x55, 0x30, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 13: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x25, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 14: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x15, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 15: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x20, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 16: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x15 | + psTdmaByte4Modify); + break; + case 17: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x14); + break; + case 18: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x30, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 19: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x15, 0x03, 0x11, 0x10); + break; + case 20: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x30, 0x03, 0x11, 0x10); + break; + case 21: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x30, 0x03, 0x11, 0x10); + break; + case 22: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x25, 0x03, 0x11, 0x10); + break; + case 23: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x10); + break; + case 32: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x03, 0x11, 0x11); + break; + case 33: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x03, 0x11, 0x10); + break; + case 57: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 58: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 67: + halbtc8703b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x10 | + psTdmaByte4Modify); + break; + } + } else { + + /* disable PS tdma */ + switch (type) { + case 8: /* PTA Control */ + halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x8, + 0x0, 0x0, 0x0, 0x0); + break; + case 0: + default: /* Software control, Antenna at BT side */ + halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x0, 0x0); + break; + case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */ + halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x48, 0x0); + break; + } + } + + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; +} + +void halbtc8703b1ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean force_exec, + IN u8 phase) +{ + u32 cnt_bt_cal_chk = 0; + boolean is_in_mp_mode = false; + u8 u8tmp = 0; + u32 u32tmp1 = 0, u32tmp2 = 0; + + + u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + /* To avoid indirect access fail */ + if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { + force_exec = true; + coex_sta->gnt_error_cnt++; + } + +#if 1 + u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, + 0x54); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (Before Ant Setup) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", + u8tmp, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); +#endif + + coex_dm->cur_ant_pos_type = ant_pos_type; + + if (!force_exec) { + if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Skip Antenna Path Setup because no change!!**********\n"); + BTC_TRACE(trace_buf); + return; + } + } + + coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; + + switch (phase) { + case BT_8703B_1ANT_PHASE_COEX_INIT: + /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ + halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8703b1ant_ltecoex_set_coex_table( + btcoexist, + BT_8703B_1ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8703b1ant_ltecoex_set_coex_table( + btcoexist, + BT_8703B_1ANT_CTT_BT_VS_LTE, + 0xffff); + + /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ + while (cnt_bt_cal_chk <= 20) { + u8tmp = btcoexist->btc_read_1byte( + btcoexist, + 0x49d); + cnt_bt_cal_chk++; + if (u8tmp & BIT(0)) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + break; + } + } + + + /* set Path control owner to WL at initial step */ + halbtc8703b1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8703B_1ANT_PCO_WLSIDE); + + /* set GNT_BT to SW high */ + halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8703B_1ANT_GNT_BLOCK_RFC_BB, + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW low */ + halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8703B_1ANT_GNT_BLOCK_RFC_BB, + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8703B_1ANT_SIG_STA_SET_TO_LOW); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = false; + break; + case BT_8703B_1ANT_PHASE_WLANONLY_INIT: + /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ + halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8703b1ant_ltecoex_set_coex_table( + btcoexist, + BT_8703B_1ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8703b1ant_ltecoex_set_coex_table( + btcoexist, + BT_8703B_1ANT_CTT_BT_VS_LTE, + 0xffff); + + /* set Path control owner to WL at initial step */ + halbtc8703b1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8703B_1ANT_PCO_WLSIDE); + + /* set GNT_BT to SW low */ + halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8703B_1ANT_GNT_BLOCK_RFC_BB, + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8703B_1ANT_SIG_STA_SET_TO_LOW); + /* Set GNT_WL to SW high */ + halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8703B_1ANT_GNT_BLOCK_RFC_BB, + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = + BTC_ANT_PATH_WIFI; + + coex_sta->run_time_state = false; + break; + case BT_8703B_1ANT_PHASE_WLAN_OFF: + /* Disable LTE Coex Function in WiFi side */ + halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0); + + /* set Path control owner to BT */ + halbtc8703b1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8703B_1ANT_PCO_BTSIDE); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = false; + break; + case BT_8703B_1ANT_PHASE_2G_RUNTIME: + halbtc8703b1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8703B_1ANT_PCO_WLSIDE); + + /* set GNT_BT to PTA */ + halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8703B_1ANT_GNT_BLOCK_RFC_BB, + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8703B_1ANT_SIG_STA_SET_BY_HW); + /* Set GNT_WL to PTA */ + halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8703B_1ANT_GNT_BLOCK_RFC_BB, + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8703B_1ANT_SIG_STA_SET_BY_HW); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_PTA; + + coex_sta->run_time_state = true; + break; + case BT_8703B_1ANT_PHASE_BTMPMODE: + halbtc8703b1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8703B_1ANT_PCO_WLSIDE); + + /* set GNT_BT to high */ + halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8703B_1ANT_GNT_BLOCK_RFC_BB, + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to low */ + halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8703B_1ANT_GNT_BLOCK_RFC_BB, + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8703B_1ANT_SIG_STA_SET_TO_LOW); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = false; + break; + } + + +#if 1 + u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (After Ant-Setup) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", + u8tmp, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); + +#endif +} + + +boolean halbtc8703b1ant_is_common_action(IN struct btc_coexist *btcoexist) +{ + boolean common = false, wifi_connected = false, wifi_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_connected && + BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + common = true; + } else if (wifi_connected && + (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + common = true; + } else if (!wifi_connected && + (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + common = true; + } else if (wifi_connected && + (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + common = true; + } else if (!wifi_connected && + (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE != + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + common = true; + } else { + if (wifi_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } + + common = false; + } + + return common; +} + + +/* ********************************************* + * + * Non-Software Coex Mechanism start + * + * ********************************************* */ +u8 halbtc8703b1ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + u8 algorithm = BT_8703B_1ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8703B_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8703B_1ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8703B_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8703B_1ANT_COEX_ALGO_HID_A2DP; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8703B_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +void halbtc8703b1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) +{ + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8703B_1ANT_PHASE_2G_RUNTIME); + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8703b1ant_action_bt_hs(IN struct btc_coexist *btcoexist) +{ + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8703b1ant_action_bt_relink(IN struct btc_coexist *btcoexist) +{ + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + coex_sta->bt_relink_downcount = 2; +} + +void halbtc8703b1ant_action_bt_idle(IN struct btc_coexist *btcoexist) +{ + boolean wifi_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_busy) { + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 2); + } else {/* if wl busy */ + + if (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + if (coex_sta->is_hiPri_rx_overhead) + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + else + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 33); + } else { + + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + } + } +} + +void halbtc8703b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, wifi_busy = false, bt_busy = false; + boolean wifi_scan = false, wifi_link = false, wifi_roam = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) + || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + + if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17); + else + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); + } else if ((!wifi_connected) && (!wifi_scan)) { + + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (bt_link_info->pan_exist) { + + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); + + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if (bt_link_info->a2dp_exist) { + + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); + + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) + || (coex_sta->wifi_is_high_pri_task)) + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); + else + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); + + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } +} + + +void halbtc8703b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, wifi_busy = false; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + + if (bt_link_info->sco_exist) { + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + } else if (coex_sta->hid_busy_num >= 2) {/*for 4/18 hid */ + /* if 11bg mode */ + if (wifi_bw == 0) { + + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8703b1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11); + } else { + + if (wifi_busy) { + + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8703b1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11); + } else { + + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + } + } + } else { + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 6); + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + } +} + + +void halbtc8703b1ant_action_wifi_only(IN struct btc_coexist *btcoexist) +{ + halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8703B_1ANT_PHASE_2G_RUNTIME); + halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); +} + +void halbtc8703b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8703B_1ANT_PHASE_2G_RUNTIME); + + if (!bt_link_info->pan_exist) + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + else + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8703b1ant_action_wifi_linkscan_process(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if (bt_link_info->pan_exist) { + + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); + + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + } else if (bt_link_info->a2dp_exist) { + + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17); + + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); + + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } +} + +void halbtc8703b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = false, wifi_turbo = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif + + if ((coex_sta->bt_relink_downcount != 0) + && (!bt_link_info->pan_exist) && (wifi_busy)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + + /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);*/ + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + } else if (bt_link_info->a2dp_only) { /* A2DP */ + if (!wifi_busy) { + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else { + + if (coex_sta->wl_noisy_level == 2) + halbtc8703b1ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 17); + else + halbtc8703b1ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + + if (wifi_turbo) + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else if (((bt_link_info->a2dp_exist) && + (bt_link_info->pan_exist)) || + (bt_link_info->hid_exist && bt_link_info->a2dp_exist && + bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ + + if ((bt_link_info->hid_exist) && (coex_sta->hid_busy_num >= 2)) { + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8703b1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 12); + } else if (wifi_busy) { + if (((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) || + (!coex_sta->is_A2DP_3M)) + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 15); + else if (wifi_turbo) + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 18); + else + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 13); + } else + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 14); + + if (bt_link_info->hid_exist) + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + else if (wifi_turbo) + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) {/* HID+A2DP */ + + if ((wifi_busy) && (coex_sta->hid_busy_num >= 2)) { /*for 4/18 hid */ + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8703b1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 9); + } else { + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 8); + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + } + + } else if ((bt_link_info->pan_only) + || (bt_link_info->hid_exist && bt_link_info->pan_exist)) { + /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ + + if ((bt_link_info->hid_exist) && (bt_link_info->pan_exist) && + (coex_sta->hid_busy_num >= 2)) { + + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); + halbtc8703b1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 12); + } else { + + if (!wifi_busy) + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 4); + else + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 3); + + if (bt_link_info->hid_exist) + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + else if (wifi_turbo) + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else + halbtc8703b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else { + /* BT no-profile busy (0x9) */ + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } +} + +void halbtc8703b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +{ + /* tdma and coex table */ + halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8703b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect()===>\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8703B_1ANT_PHASE_2G_RUNTIME); + + if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + + if (bt_link_info->hid_only)/* HID only */ + halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist); + else + halbtc8703b1ant_action_wifi_connected_bt_acl_busy(btcoexist); + + } else if ((BT_8703B_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist); + } else + halbtc8703b1ant_action_bt_idle(btcoexist); +} + + +void halbtc8703b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + u8 algorithm = 0; + + algorithm = halbtc8703b1ant_action_algorithm(btcoexist); + coex_dm->cur_algorithm = algorithm; + + if (halbtc8703b1ant_is_common_action(btcoexist)) { + + } else { + switch (coex_dm->cur_algorithm) { + case BT_8703B_1ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + break; + case BT_8703B_1ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID.\n"); + BTC_TRACE(trace_buf); + break; + case BT_8703B_1ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + break; + case BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + break; + case BT_8703B_1ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + break; + case BT_8703B_1ANT_COEX_ALGO_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HS mode.\n"); + BTC_TRACE(trace_buf); + break; + case BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + break; + case BT_8703B_1ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + break; + case BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + break; + case BT_8703B_1ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + break; + } + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + } +} + +void halbtc8703b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, bt_hs_on = false; + boolean increase_scan_dev_num = false; + boolean bt_ctrl_agg_buf_size = false; + boolean miracast_plus_bt = false, wifi_under_5g = false; + u8 agg_buf_size = 5; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0, wifi_bw; + u8 iot_peer = BTC_IOT_PEER_UNKNOWN; + boolean scan = false, link = false, roam = false, under_4way = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (!coex_sta->run_time_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], return for run_time_state = false !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->freeze_coexrun_by_btinfo) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->bt_whck_test) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under WHCK TEST!!!\n"); + BTC_TRACE(trace_buf); + halbtc8703b1ant_action_bt_whql_test(btcoexist); + return; + } + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!!\n"); + halbtc8703b1ant_action_wifi_only(btcoexist); + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8703b1ant_action_bt_inquiry(btcoexist); + return; + } + + if (coex_sta->is_setupLink) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is re-link !!!\n"); + halbtc8703b1ant_action_bt_relink(btcoexist); + return; + } + + if ((BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + increase_scan_dev_num = true; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, + &increase_scan_dev_num); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + + num_of_wifi_link = wifi_link_status >> 16; + + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", + num_of_wifi_link, wifi_link_status); + BTC_TRACE(trace_buf); + + if (bt_link_info->bt_link_exist) + miracast_plus_bt = true; + else + miracast_plus_bt = false; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + false, 0x5); + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_action_wifi_linkscan_process(btcoexist); + } else + halbtc8703b1ant_action_wifi_multi_port(btcoexist); + + return; + } else { + + miracast_plus_bt = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + } + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + + if ((bt_link_info->bt_link_exist) && (wifi_connected)) { + + btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); + + if (BTC_IOT_PEER_CISCO == iot_peer) { + + if (BTC_WIFI_BW_HT40 == wifi_bw) + halbtc8703b1ant_limited_rx(btcoexist, + NORMAL_EXEC, false, true, 0x10); + else + halbtc8703b1ant_limited_rx(btcoexist, + NORMAL_EXEC, false, true, 0x8); + } else + halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x5); + } + + halbtc8703b1ant_run_sw_coexist_mechanism( + btcoexist); /* just print debug message */ + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is hs\n"); + BTC_TRACE(trace_buf); + halbtc8703b1ant_action_bt_hs(btcoexist); + return; + } + + if ((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) || + (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is idle\n"); + BTC_TRACE(trace_buf); + halbtc8703b1ant_action_bt_idle(btcoexist); + return; + } + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under linkscan process!!\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_action_wifi_linkscan_process(btcoexist); + } else if (wifi_connected) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under connected!!\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_action_wifi_connected(btcoexist); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under not-connected!!\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_action_wifi_not_connected(btcoexist); + } +} + + +void halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + /* force to reset coex mechanism */ + + halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->pop_event_cnt = 0; + coex_sta->cnt_RemoteNameReq = 0; + coex_sta->cnt_ReInit = 0; + coex_sta->cnt_setupLink = 0; + coex_sta->cnt_IgnWlanAct = 0; + coex_sta->cnt_Page = 0; +} + +void halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean back_up, IN boolean wifi_only) +{ + u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0; + u8 i = 0; + + u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70), + u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "\n [BTCoex], ********** 0x70/ 0x38/ 0x54 (Before Init HW config) = 0x%x/ 0x%x/ 0x%x**********\n", + u32tmp0, + u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 1Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->gnt_error_cnt = 0; + coex_sta->bt_relink_downcount = 0; + + for (i = 0; i <= 9; i++) + coex_sta->bt_afh_map[i] = 0; + + /* 0xf0[15:12] --> Chip Cut information */ + coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, + 0xf1) & 0xf0) >> 4; + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + + /* BT report packet sample rate */ + btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); + + /* Enable BT counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + + /* Enable PTA (3-wire function form BT side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); + + /* Enable PTA (tx/rx signal form WiFi side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); + + halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, false); + + if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ONOFF, true); + + halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + + /* Antenna config */ + if (wifi_only) { + coex_sta->concurrent_rx_mode_on = false; + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, + FORCE_EXEC, + BT_8703B_1ANT_PHASE_WLANONLY_INIT); + } else { + coex_sta->concurrent_rx_mode_on = true; + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); + /* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0); + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8703B_1ANT_PHASE_COEX_INIT); + } + + /* PTA parameter */ + halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70), + u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** 0x70/ 0x38/ 0x54 (After Init HW config) = 0x%x/ 0x%x/ 0x%x**********\n", + u32tmp0, + u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); + +} + + + +/* ************************************************************ + * work around function start with wa_halbtc8703b1ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8703b1ant_ + * ************************************************************ */ +void ex_halbtc8703b1ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x0; + u16 u16tmp = 0x0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx Execute 8703b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "Ant Det Finish = %s, Ant Det Number = %d\n", + (board_info->btdm_ant_det_finish ? "Yes" : "No"), + board_info->btdm_ant_num_by_ant_det); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = true; + + /* enable BB, REG_SYS_FUNC_EN such that we can write BB/MAC reg correctly. */ + u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); + btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); + + /* set Path control owner to WiFi */ + halbtc8703b1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8703B_1ANT_PCO_WLSIDE); + + /* set GNT_BT to high */ + halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8703B_1ANT_GNT_BLOCK_RFC_BB, + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to low */ + halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8703B_1ANT_GNT_BLOCK_RFC_BB, + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8703B_1ANT_SIG_STA_SET_TO_LOW); + + /* set WLAN_ACT = 0 */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); + + halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, false); + + /* */ + /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + + u8tmp = 0; + board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; + + if (btcoexist->chip_interface == BTC_INTF_USB) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); + + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** 0x70(MAC)/0x38/0x54 (Power-On) =0x%x/ 0x%x/ 0x%x**********\n", + btcoexist->btc_read_4byte(btcoexist, 0x70), + halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38), + halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54)); + BTC_TRACE(trace_buf); + + +} + +void ex_halbtc8703b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{ +} + +void ex_halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8703b1ant_init_hw_config(btcoexist, true, wifi_only); + btcoexist->stop_coex_dm = false; +} + +void ex_halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8703b1ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_stack_info *stack_info = &btcoexist->stack_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u16 u16tmp[4]; + u32 u32tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + static u8 pop_report_in_10s = 0; + u32 phyver = 0; + boolean lte_coex_on = false; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + if (btcoexist->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + if (psd_scan->ant_det_try_count == 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", + "Ant PG Num/ Mech/ Pos", + board_info->pg_ant_num, board_info->btdm_ant_num, + board_info->btdm_ant_pos); + CL_PRINTF(cli_buf); + } else { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %d (%d/%d/%d)", + "Ant PG Num/ Mech(Ant_Det)/ Pos", + board_info->pg_ant_num, + board_info->btdm_ant_num_by_ant_det, + board_info->btdm_ant_pos, + psd_scan->ant_det_try_count, + psd_scan->ant_det_fail_count, + psd_scan->ant_det_result); + CL_PRINTF(cli_buf); + + if (board_info->btdm_ant_det_finish) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "Ant Det PSD Value", + psd_scan->ant_det_peak_val); + CL_PRINTF(cli_buf); + } + } + + + /*bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;*/ + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + + bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8703b_1ant, glcoex_ver_8703b_1ant, + glcoex_ver_btdesired_8703b_1ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (bt_coex_ver >= glcoex_ver_btdesired_8703b_1ant ? + "Match":"Mis-Match"))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "Wifi channel informed to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", + "WifibHiPri/ Ccklock/ CckEverLock", + (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + (coex_sta->cck_lock ? "Yes" : "No"), + (coex_sta->cck_ever_lock ? "Yes" : "No")); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + pop_report_in_10s++; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", + "BT [status/ rssi/ retryCnt/ popCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + : ((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, + coex_sta->pop_event_cnt); + CL_PRINTF(cli_buf); + + if (pop_report_in_10s >= 5) { + coex_sta->pop_event_cnt = 0; + pop_report_in_10s = 0; + } + + if (coex_sta->num_of_profile != 0) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s%s%s%s%s", + "Profiles", + ((bt_link_info->a2dp_exist) ? "A2DP," : ""), + ((bt_link_info->sco_exist) ? "SCO," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : + "HID(2/18),") : ""), + ((bt_link_info->pan_exist) ? "PAN," : ""), + ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = None", + "Profiles"); + + CL_PRINTF(cli_buf); + + if (bt_link_info->a2dp_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", + "A2DP Rate/Bitpool/Auto_Slot", + ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), + coex_sta->a2dp_bit_pool, + ((coex_sta->is_autoslot) ? "On" : "Off") + ); + CL_PRINTF(cli_buf); + } + + if (bt_link_info->hid_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "HID PairNum/Forbid_Slot", + coex_sta->hid_pair_cnt, + coex_sta->forbidden_slot + ); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ 0x%x", + "Role/IgnWlanAct/Feature", + ((bt_link_info->slave_role) ? "Slave" : "Master"), + ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), + coex_sta->bt_coex_supported_feature); + CL_PRINTF(cli_buf); + + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "ReInit/ReLink/IgnWlact/Page/NameReq", + coex_sta->cnt_ReInit, + coex_sta->cnt_setupLink, + coex_sta->cnt_IgnWlanAct, + coex_sta->cnt_Page, + coex_sta->cnt_RemoteNameReq + ); + CL_PRINTF(cli_buf); + + halbtc8703b1ant_read_score_board(btcoexist, &u16tmp[0]); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x", + "ScoreBoard[14:0] (from BT)", u16tmp[0]); + CL_PRINTF(cli_buf); + + if (coex_sta->num_of_profile > 0) { + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + "AFH MAP", + coex_sta->bt_afh_map[0], + coex_sta->bt_afh_map[1], + coex_sta->bt_afh_map[2], + coex_sta->bt_afh_map[3], + coex_sta->bt_afh_map[4], + coex_sta->bt_afh_map[5], + coex_sta->bt_afh_map[6], + coex_sta->bt_afh_map[7], + coex_sta->bt_afh_map[8], + coex_sta->bt_afh_map[9] + ); + CL_PRINTF(cli_buf); + } + + for (i = 0; i < BT_INFO_SRC_8703B_1ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8703b_1ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + if (btcoexist->manual_control) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanisms] (before Manual)============"); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanisms]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "SM[LowPenaltyRA]", + coex_dm->cur_low_penalty_ra); + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", + "PS TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + (coex_dm->cur_ps_tdma_on ? "On" : "Off"), + (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); + + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "WL/BT Coex Table Type", + coex_sta->coex_table_type); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x6c0/0x6c4/0x6c8(coexTable)", + u32tmp[0], u32tmp[1], u32tmp[2]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x778/0x6cc/IgnWlanAct", + u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? true : false; + + if (lte_coex_on) { + u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa0); + u32tmp[1] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "LTE Coex Table W_L/B_L", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa8); + u32tmp[1] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xac); + u32tmp[2] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xb0); + u32tmp[3] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xb4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "LTE Break Table W_L/B_L/L_W/L_B", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, + u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); + CL_PRINTF(cli_buf); + } + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s", + "LTE CoexOn/Path Ctrl Owner", + (int)((u32tmp[0] & BIT(7)) >> 7), + ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); + CL_PRINTF(cli_buf); + + if (lte_coex_on) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "LTE 3Wire/OPMode/UART/UARTMode", + (int)((u32tmp[0] & BIT(6)) >> 6), + (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), + (int)((u32tmp[0] & BIT(3)) >> 3), + (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); + CL_PRINTF(cli_buf); + } + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", + ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), + ((u8tmp[0] & BIT(3)) ? "On" : "Off"), + coex_sta->gnt_error_cnt); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "GNT_WL/GNT_BT/LTE_Busy/UART_Busy", + (int)((u32tmp[0] & BIT(2)) >> 2), + (int)((u32tmp[0] & BIT(3)) >> 3), + (int)((u32tmp[0] & BIT(1)) >> 1), (int)(u32tmp[0] & BIT(0))); + CL_PRINTF(cli_buf); + + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x4c6[4]/0x40[5] (WL/BT PTA)", + (int)((u8tmp[0] & BIT(4)) >> 4), + (int)((u8tmp[1] & BIT(5)) >> 5)); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s", + "0x550(bcn ctrl)/0x522/4-RxAGC", + u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off"); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); + CL_PRINTF(cli_buf); + +#if 1 + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11n-agg", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_Err CCK/11g/11n/11n-agg", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); + CL_PRINTF(cli_buf); +#endif + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "WlHiPri/ Locking/ Locked/ Noisy", + (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + (coex_sta->cck_lock ? "Yes" : "No"), + (coex_sta->cck_ever_lock ? "Yes" : "No"), + coex_sta->wl_noisy_level); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx, + (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : "")); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : ( + coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); + CL_PRINTF(cli_buf); + + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +void ex_halbtc8703b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = true; + coex_sta->under_lps = false; + + /* Write WL "Active" in Score-board for LPS off */ + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, false); + + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ONOFF, false); + + halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8703B_1ANT_PHASE_WLAN_OFF); + + halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); + + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ONOFF, true); + + halbtc8703b1ant_init_hw_config(btcoexist, false, false); + halbtc8703b1ant_init_coex_dm(btcoexist); + halbtc8703b1ant_query_bt_info(btcoexist); + + coex_sta->under_ips = false; + } +} + +void ex_halbtc8703b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = true; + coex_sta->under_ips = false; + + if (coex_sta->force_lps_on == true) { /* LPS No-32K */ + /* Write WL "Active" in Score-board for PS-TDMA */ + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); + + } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ + /* Write WL "Non-Active" in Score-board for Native-PS */ + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, false); + } + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = false; + + + /* Write WL "Active" in Score-board for LPS off */ + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); + } +} + +void ex_halbtc8703b1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + halbtc8703b1ant_query_bt_info(btcoexist); + + if (BTC_SCAN_START == type) { + + coex_sta->wifi_is_high_pri_task = true; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_SCAN, true); + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); + + halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 8); + + /* Force antenna setup for no scan result issue */ + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8703B_1ANT_PHASE_2G_RUNTIME); + + halbtc8703b1ant_run_coexist_mechanism(btcoexist); + + } else { + + coex_sta->wifi_is_high_pri_task = false; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", + coex_sta->scan_ap_num); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_run_coexist_mechanism(btcoexist); + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START Notify() end\n"); + BTC_TRACE(trace_buf); + +} + +void ex_halbtc8703b1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + if (BTC_ASSOCIATE_START == type) { + coex_sta->wifi_is_high_pri_task = true; + + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_SCAN, true); + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); + + halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 8); + + /* Force antenna setup for no scan result issue */ + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8703B_1ANT_PHASE_2G_RUNTIME); + /* psd_scan->ant_det_is_ant_det_available = true; */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify\n"); + BTC_TRACE(trace_buf); + coex_dm->arp_cnt = 0; + + halbtc8703b1ant_run_coexist_mechanism(btcoexist); + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_run_coexist_mechanism(btcoexist); + } + +} + +void ex_halbtc8703b1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_under_b_mode = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + if (BTC_MEDIA_CONNECT == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); + halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 8); + + /* Force antenna setup for no scan result issue */ + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8703B_1ANT_PHASE_2G_RUNTIME); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x00); /* CCK Rx */ + } else { + /* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */ + /* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x10); /* CCK Rx */ + } + + coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, + 0x430); + coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, + 0x434); + coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( + btcoexist, 0x42a); + coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( + btcoexist, 0x456); + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, false); + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + + coex_sta->cck_ever_lock = false; + } + + halbtc8703b1ant_update_wifi_channel_info(btcoexist, type); + +} + +void ex_halbtc8703b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean under_4way = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (under_4way) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ---- under_4way!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = true; + coex_sta->specific_pkt_period_cnt = 2; + } else if (BTC_PACKET_ARP == type) { + + coex_dm->arp_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ARP notify -cnt = %d\n", + coex_dm->arp_cnt); + BTC_TRACE(trace_buf); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", + type); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = true; + coex_sta->specific_pkt_period_cnt = 2; + } + + if (coex_sta->wifi_is_high_pri_task) { + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_SCAN, true); + halbtc8703b1ant_run_coexist_mechanism(btcoexist); + } +} + +void ex_halbtc8703b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 i, rsp_source = 0; + boolean wifi_connected = false; + boolean wifi_scan = false, wifi_link = false, wifi_roam = false, + wifi_busy = false; + + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8703B_1ANT_MAX) + rsp_source = BT_INFO_SRC_8703B_1ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; + coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; + coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; + + if (BT_INFO_SRC_8703B_1ANT_WIFI_FW != rsp_source) { + + /* if 0xff, it means BT is under WHCK test */ + coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true : + false); + + coex_sta->bt_create_connection = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true : + false); + + /* unit: %, value-100 to translate to unit: dBm */ + coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + + 10; + + coex_sta->c2h_bt_remote_name_req = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true : + false); + + coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & + 0x10) ? true : false); + + coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & + 0x9) ? true : false); + + coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? + true : false); + + coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & + BT_INFO_8703B_1ANT_B_INQ_PAGE) ? true : false); + + coex_sta->a2dp_bit_pool = ((( + coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? + coex_sta->bt_info_c2h[rsp_source][6] : 0); + + coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & + 0xf; + + coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; + + coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; + + coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; + + coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; + + if (coex_sta->bt_retry_cnt >= 1) + coex_sta->pop_event_cnt++; + + if (coex_sta->c2h_bt_remote_name_req) + coex_sta->cnt_RemoteNameReq++; + + if (coex_sta->bt_info_ext & BIT(1)) + coex_sta->cnt_ReInit++; + + if (coex_sta->bt_info_ext & BIT(2)) { + coex_sta->cnt_setupLink++; + coex_sta->is_setupLink = true; + } else + coex_sta->is_setupLink = false; + + if (coex_sta->bt_info_ext & BIT(3)) + coex_sta->cnt_IgnWlanAct++; + + if (coex_sta->bt_create_connection) { + coex_sta->cnt_Page++; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || + (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { + + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_SCAN, true); + + } else { + + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_SCAN, false); + } + } else + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_SCAN, false); + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + + if ((!btcoexist->manual_control) && + (!btcoexist->stop_coex_dm)) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* Re-Init */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + if (wifi_connected) + halbtc8703b1ant_update_wifi_channel_info( + btcoexist, BTC_MEDIA_CONNECT); + else + halbtc8703b1ant_update_wifi_channel_info( + btcoexist, + BTC_MEDIA_DISCONNECT); + } + + + /* If Ignore_WLanAct && not SetUp_Link */ + if ((coex_sta->bt_info_ext & BIT(3)) && + (!(coex_sta->bt_info_ext & BIT(2))) && + (!(coex_sta->bt_info_ext & BIT(6)))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8703b1ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, false); + } else { + if (coex_sta->bt_info_ext & BIT(2)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ignore Wlan active because Re-link!!\n"); + BTC_TRACE(trace_buf); + } else if (coex_sta->bt_info_ext & BIT(6)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ignore Wlan active because Role-Switch!!\n"); + BTC_TRACE(trace_buf); + } + } + } + + } + if ((coex_sta->bt_info_ext & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + BTC_TRACE(trace_buf); + coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist); + + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x4); + } + + halbtc8703b1ant_update_bt_link_info(btcoexist); + + halbtc8703b1ant_run_coexist_mechanism(btcoexist); +} + + +void ex_halbtc8703b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_RF_ON == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned ON!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = false; + + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ONOFF, true); + + /* halbtc8703b1ant_init_hw_config(btcoexist, false, false); */ + } else if (BTC_RF_OFF == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned OFF!!\n"); + BTC_TRACE(trace_buf); + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, false); + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ONOFF, false); + + halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8703B_1ANT_PHASE_WLAN_OFF); + + btcoexist->stop_coex_dm = true; + + } +} + +void ex_halbtc8703b1ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, false); + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ONOFF, false); + + halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8703B_1ANT_PHASE_WLAN_OFF); + + ex_halbtc8703b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + + halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, false); + + btcoexist->stop_coex_dm = true; +} + +void ex_halbtc8703b1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); + BTC_TRACE(trace_buf); + + if ((BTC_WIFI_PNP_SLEEP == pnp_state) || + (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, false); + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ONOFF, false); + + if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { + + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8703B_1ANT_PHASE_2G_RUNTIME); + } else { + + halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8703B_1ANT_PHASE_WLAN_OFF); + } + + btcoexist->stop_coex_dm = true; + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_ONOFF, true); + + btcoexist->stop_coex_dm = false; + } +} + +void ex_halbtc8703b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], *****************Coex DM Reset*****************\n"); + BTC_TRACE(trace_buf); + + halbtc8703b1ant_init_hw_config(btcoexist, false, false); + halbtc8703b1ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8703b1ant_periodical(IN struct btc_coexist *btcoexist) +{ + u32 bt_patch_ver; + boolean wifi_busy = false; + static u8 cnt = 0; + boolean bt_relink_finish = false; + +#if (BT_AUTO_REPORT_ONLY_8703B_1ANT == 0) + halbtc8703b1ant_query_bt_info(btcoexist); +#endif + + halbtc8703b1ant_monitor_bt_ctr(btcoexist); + halbtc8703b1ant_monitor_wifi_ctr(btcoexist); + + halbtc8703b1ant_monitor_bt_enable_disable(btcoexist); + +# if 1 + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + /* halbtc8703b1ant_read_score_board(btcoexist, &bt_scoreboard_val); */ + + if (wifi_busy) { + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_UNDERTEST, true); + /* + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_WLBUSY, true); + + if (bt_scoreboard_val & BIT(6)) + halbtc8703b1ant_query_bt_info(btcoexist); */ + } else { + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_UNDERTEST, false); + /* + halbtc8703b1ant_post_state_to_bt(btcoexist, + BT_8703B_1ANT_SCOREBOARD_WLBUSY, + false); */ + } +#endif + + if (coex_sta->bt_relink_downcount != 0) { + coex_sta->bt_relink_downcount--; + + if (coex_sta->bt_relink_downcount == 0) + bt_relink_finish = true; + } + + /* for 4-way, DHCP, EAPOL packet */ + if (coex_sta->specific_pkt_period_cnt > 0) { + + coex_sta->specific_pkt_period_cnt--; + + if ((coex_sta->specific_pkt_period_cnt == 0) && + (coex_sta->wifi_is_high_pri_task)) + coex_sta->wifi_is_high_pri_task = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", + (coex_sta->wifi_is_high_pri_task ? "Yes" : + "No")); + BTC_TRACE(trace_buf); + + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->bt_coex_supported_feature == 0) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) { + cnt++; + + if (cnt >= 3) { + btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, + &coex_sta->bt_afh_map[0]); + cnt = 0; + } + } + } + + if (halbtc8703b1ant_is_wifibt_status_changed(btcoexist)) + halbtc8703b1ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8703b1ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + /* No Antenna Detection required because 8730b is only 1-Ant */ +} + +void ex_halbtc8703b1ant_antenna_isolation(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + + +} + +void ex_halbtc8703b1ant_psd_scan(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + + +} + +void ex_halbtc8703b1ant_display_ant_detection(IN struct btc_coexist *btcoexist) +{ + +} + +#endif + +#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ + diff --git a/hal/btc/halbtc8703b1ant.h b/hal/btc/halbtc8703b1ant.h new file mode 100644 index 0000000..a2a9711 --- /dev/null +++ b/hal/btc/halbtc8703b1ant.h @@ -0,0 +1,418 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8703B_SUPPORT == 1) +/* ******************************************* + * The following is for 8703B 1ANT BT Co-exist definition + * ******************************************* */ +#define BT_AUTO_REPORT_ONLY_8703B_1ANT 1 +#define BT_8703B_1ANT_ENABLE_GNTBT_TO_GPIO14 0 + +#define BT_INFO_8703B_1ANT_B_FTP BIT(7) +#define BT_INFO_8703B_1ANT_B_A2DP BIT(6) +#define BT_INFO_8703B_1ANT_B_HID BIT(5) +#define BT_INFO_8703B_1ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8703B_1ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8703B_1ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8703B_1ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8703B_1ANT_B_CONNECTION BIT(0) + +#define BT_INFO_8703B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT(0))) ? true : false) + +#define BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT 2 + +#define BT_8703B_1ANT_WIFI_NOISY_THRESH 50 /* max: 255 */ + +/* for Antenna detection */ +#define BT_8703B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 +#define BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 +#define BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 +#define BT_8703B_1ANT_ANTDET_PSDTHRES_1ANT 35 +#define BT_8703B_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ +#define BT_8703B_1ANT_ANTDET_SWEEPPOINT_DELAY 40000 +#define BT_8703B_1ANT_ANTDET_ENABLE 0 +#define BT_8703B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0 + +#define BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 + +enum bt_8703b_1ant_signal_state { + BT_8703B_1ANT_SIG_STA_SET_TO_LOW = 0x0, + BT_8703B_1ANT_SIG_STA_SET_BY_HW = 0x0, + BT_8703B_1ANT_SIG_STA_SET_TO_HIGH = 0x1, + BT_8703B_1ANT_SIG_STA_MAX +}; + +enum bt_8703b_1ant_path_ctrl_owner { + BT_8703B_1ANT_PCO_BTSIDE = 0x0, + BT_8703B_1ANT_PCO_WLSIDE = 0x1, + BT_8703B_1ANT_PCO_MAX +}; + +enum bt_8703b_1ant_gnt_ctrl_type { + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW = 0x1, + BT_8703B_1ANT_GNT_TYPE_MAX +}; + +enum bt_8703b_1ant_gnt_ctrl_block { + BT_8703B_1ANT_GNT_BLOCK_RFC_BB = 0x0, + BT_8703B_1ANT_GNT_BLOCK_RFC = 0x1, + BT_8703B_1ANT_GNT_BLOCK_BB = 0x2, + BT_8703B_1ANT_GNT_BLOCK_MAX +}; + +enum bt_8703b_1ant_lte_coex_table_type { + BT_8703B_1ANT_CTT_WL_VS_LTE = 0x0, + BT_8703B_1ANT_CTT_BT_VS_LTE = 0x1, + BT_8703B_1ANT_CTT_MAX +}; + +enum bt_8703b_1ant_lte_break_table_type { + BT_8703B_1ANT_LBTT_WL_BREAK_LTE = 0x0, + BT_8703B_1ANT_LBTT_BT_BREAK_LTE = 0x1, + BT_8703B_1ANT_LBTT_LTE_BREAK_WL = 0x2, + BT_8703B_1ANT_LBTT_LTE_BREAK_BT = 0x3, + BT_8703B_1ANT_LBTT_MAX +}; + +enum bt_info_src_8703b_1ant { + BT_INFO_SRC_8703B_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8703B_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8703B_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8703B_1ANT_MAX +}; + +enum bt_8703b_1ant_bt_status { + BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8703B_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8703B_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8703B_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8703B_1ANT_BT_STATUS_MAX +}; + +enum bt_8703b_1ant_wifi_status { + BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8703B_1ANT_WIFI_STATUS_MAX +}; + +enum bt_8703b_1ant_coex_algo { + BT_8703B_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8703B_1ANT_COEX_ALGO_SCO = 0x1, + BT_8703B_1ANT_COEX_ALGO_HID = 0x2, + BT_8703B_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8703B_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8703B_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8703B_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8703B_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8703B_1ANT_COEX_ALGO_MAX = 0xb, +}; + +enum bt_8703b_1ant_phase { + BT_8703B_1ANT_PHASE_COEX_INIT = 0x0, + BT_8703B_1ANT_PHASE_WLANONLY_INIT = 0x1, + BT_8703B_1ANT_PHASE_WLAN_OFF = 0x2, + BT_8703B_1ANT_PHASE_2G_RUNTIME = 0x3, + BT_8703B_1ANT_PHASE_5G_RUNTIME = 0x4, + BT_8703B_1ANT_PHASE_BTMPMODE = 0x5, + BT_8703B_1ANT_PHASE_ANTENNA_DET = 0x6, + BT_8703B_1ANT_PHASE_MAX +}; + +enum bt_8703b_1ant_Scoreboard { + BT_8703B_1ANT_SCOREBOARD_ACTIVE = BIT(0), + BT_8703B_1ANT_SCOREBOARD_ONOFF = BIT(1), + BT_8703B_1ANT_SCOREBOARD_SCAN = BIT(2), + BT_8703B_1ANT_SCOREBOARD_UNDERTEST = BIT(3), + BT_8703B_1ANT_SCOREBOARD_WLBUSY = BIT(6) +}; + + +struct coex_dm_8703b_1ant { + /* hw setting */ + u8 pre_ant_pos_type; + u8 cur_ant_pos_type; + /* fw mechanism */ + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean auto_tdma_adjust; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + /* sw mechanism */ + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + + u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ + u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ + u16 backup_retry_limit; + u8 backup_ampdu_max_time; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + u32 pre_ra_mask; + u32 cur_ra_mask; + u8 pre_arfr_type; + u8 cur_arfr_type; + u8 pre_retry_limit_type; + u8 cur_retry_limit_type; + u8 pre_ampdu_time_type; + u8 cur_ampdu_time_type; + u32 arp_cnt; + + u8 error_condition; +}; + +struct coex_sta_8703b_1ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + boolean bt_hi_pri_link_exist; + u8 num_of_profile; + + boolean under_lps; + boolean under_ips; + u32 specific_pkt_period_cnt; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + boolean is_hiPri_rx_overhead; + s8 bt_rssi; + boolean bt_tx_rx_mask; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + u8 bt_info_c2h[BT_INFO_SRC_8703B_1ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8703B_1ANT_MAX]; + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; + boolean c2h_bt_page; /* Add for win8.1 page out issue */ + boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ + u8 bt_retry_cnt; + u8 bt_info_ext; + u8 bt_info_ext2; + u32 pop_event_cnt; + u8 scan_ap_num; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + + boolean cck_lock; + boolean pre_ccklock; + boolean cck_ever_lock; + u8 coex_table_type; + + boolean force_lps_on; + + boolean concurrent_rx_mode_on; + + u16 score_board; + u8 isolation_btween_wb; /* 0~ 50 */ + + u8 a2dp_bit_pool; + u8 cut_version; + boolean acl_busy; + boolean bt_create_connection; + + u32 bt_coex_supported_feature; + u32 bt_coex_supported_version; + + u8 bt_ble_scan_type; + u32 bt_ble_scan_para[3]; + + boolean run_time_state; + boolean freeze_coexrun_by_btinfo; + + boolean is_A2DP_3M; + boolean voice_over_HOGP; + u8 bt_info; + boolean is_autoslot; + u8 forbidden_slot; + u8 hid_busy_num; + u8 hid_pair_cnt; + + u32 cnt_RemoteNameReq; + u32 cnt_setupLink; + u32 cnt_ReInit; + u32 cnt_IgnWlanAct; + u32 cnt_Page; + + u16 bt_reg_vendor_ac; + u16 bt_reg_vendor_ae; + + boolean is_setupLink; + u8 wl_noisy_level; + u32 gnt_error_cnt; + + u8 bt_afh_map[10]; + u8 bt_relink_downcount; + boolean is_tdma_btautoslot; + boolean is_tdma_btautoslot_hang; +}; + +#define BT_8703B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ +#define BT_8703B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ +#define BT_8703B_1ANT_ANTDET_BUF_LEN 16 + +struct psdscan_sta_8703b_1ant { + + u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ + u32 ant_det_bt_tx_time; + u32 ant_det_pre_psdscan_peak_val; + boolean ant_det_is_ant_det_available; + u32 ant_det_psd_scan_peak_val; + boolean ant_det_is_btreply_available; + u32 ant_det_psd_scan_peak_freq; + + u8 ant_det_result; + u8 ant_det_peak_val[BT_8703B_1ANT_ANTDET_BUF_LEN]; + u8 ant_det_peak_freq[BT_8703B_1ANT_ANTDET_BUF_LEN]; + u32 ant_det_try_count; + u32 ant_det_fail_count; + u32 ant_det_inteval_count; + u32 ant_det_thres_offset; + + u32 real_cent_freq; + s32 real_offset; + u32 real_span; + + u32 psd_band_width; /* unit: Hz */ + u32 psd_point; /* 128/256/512/1024 */ + u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_start_point; + u32 psd_stop_point; + u32 psd_max_value_point; + u32 psd_max_value; + u32 psd_start_base; + u32 psd_avg_num; /* 1/8/16/32 */ + u32 psd_gen_count; + boolean is_psd_running; + boolean is_psd_show_max_only; +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8703b1ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8703b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); +void ex_halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8703b1ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8703b1ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8703b1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8703b1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8703b1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8703b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8703b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8703b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8703b1ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8703b1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8703b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); +void ex_halbtc8703b1ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8703b1ant_display_coex_info(IN struct btc_coexist *btcoexist); +void ex_halbtc8703b1ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); +void ex_halbtc8703b1ant_antenna_isolation(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); + +void ex_halbtc8703b1ant_psd_scan(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); +void ex_halbtc8703b1ant_display_ant_detection(IN struct btc_coexist *btcoexist); + +#else +#define ex_halbtc8703b1ant_power_on_setting(btcoexist) +#define ex_halbtc8703b1ant_pre_load_firmware(btcoexist) +#define ex_halbtc8703b1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8703b1ant_init_coex_dm(btcoexist) +#define ex_halbtc8703b1ant_ips_notify(btcoexist, type) +#define ex_halbtc8703b1ant_lps_notify(btcoexist, type) +#define ex_halbtc8703b1ant_scan_notify(btcoexist, type) +#define ex_halbtc8703b1ant_connect_notify(btcoexist, type) +#define ex_halbtc8703b1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8703b1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8703b1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8703b1ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8703b1ant_halt_notify(btcoexist) +#define ex_halbtc8703b1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8703b1ant_coex_dm_reset(btcoexist) +#define ex_halbtc8703b1ant_periodical(btcoexist) +#define ex_halbtc8703b1ant_display_coex_info(btcoexist) +#define ex_halbtc8703b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8703b1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8703b1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8703b1ant_display_ant_detection(btcoexist) + +#endif + + +#endif + diff --git a/hal/btc/halbtc8723b1ant.c b/hal/btc/halbtc8723b1ant.c new file mode 100644 index 0000000..b5392fb --- /dev/null +++ b/hal/btc/halbtc8723b1ant.c @@ -0,0 +1,5127 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for RTL8723B Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8723B_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8723b_1ant glcoex_dm_8723b_1ant; +static struct coex_dm_8723b_1ant *coex_dm = &glcoex_dm_8723b_1ant; +static struct coex_sta_8723b_1ant glcoex_sta_8723b_1ant; +static struct coex_sta_8723b_1ant *coex_sta = &glcoex_sta_8723b_1ant; +static struct psdscan_sta_8723b_1ant gl_psd_scan_8723b_1ant; +static struct psdscan_sta_8723b_1ant *psd_scan = &gl_psd_scan_8723b_1ant; + + +const char *const glbt_info_src_8723b_1ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u32 glcoex_ver_date_8723b_1ant = 20161007; +u32 glcoex_ver_8723b_1ant = 0x69; +u32 glcoex_ver_btdesired_8723b_1ant = 0x69; + +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8723b1ant_ + * ************************************************************ */ + +void halbtc8723b1ant_update_ra_mask(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 dis_rate_mask) +{ + coex_dm->cur_ra_mask = dis_rate_mask; + + if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) + btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, + &coex_dm->cur_ra_mask); + coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; +} + +void halbtc8723b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + boolean wifi_under_b_mode = false; + + coex_dm->cur_arfr_type = type; + + if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { + switch (coex_dm->cur_arfr_type) { + case 0: /* normal mode */ + btcoexist->btc_write_4byte(btcoexist, 0x430, + coex_dm->backup_arfr_cnt1); + btcoexist->btc_write_4byte(btcoexist, 0x434, + coex_dm->backup_arfr_cnt2); + break; + case 1: + btcoexist->btc_get(btcoexist, + BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + if (wifi_under_b_mode) { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x01010101); + } else { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x04030201); + } + break; + default: + break; + } + } + + coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; +} + +void halbtc8723b1ant_retry_limit(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_retry_limit_type = type; + + if (force_exec || + (coex_dm->pre_retry_limit_type != + coex_dm->cur_retry_limit_type)) { + switch (coex_dm->cur_retry_limit_type) { + case 0: /* normal mode */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + coex_dm->backup_retry_limit); + break; + case 1: /* retry limit=8 */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + 0x0808); + break; + default: + break; + } + } + + coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; +} + +void halbtc8723b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_ampdu_time_type = type; + + if (force_exec || + (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { + switch (coex_dm->cur_ampdu_time_type) { + case 0: /* normal mode */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + coex_dm->backup_ampdu_max_time); + break; + case 1: /* AMPDU timw = 0x38 * 32us */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + 0x38); + break; + default: + break; + } + } + + coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; +} + +void halbtc8723b1ant_limited_tx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, + IN u8 retry_limit_type, IN u8 ampdu_time_type) +{ + switch (ra_mask_type) { + case 0: /* normal mode */ + halbtc8723b1ant_update_ra_mask(btcoexist, force_exec, + 0x0); + break; + case 1: /* disable cck 1/2 */ + halbtc8723b1ant_update_ra_mask(btcoexist, force_exec, + 0x00000003); + break; + case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ + halbtc8723b1ant_update_ra_mask(btcoexist, force_exec, + 0x0001f1f7); + break; + default: + break; + } + + halbtc8723b1ant_auto_rate_fallback_retry(btcoexist, force_exec, + arfr_type); + halbtc8723b1ant_retry_limit(btcoexist, force_exec, retry_limit_type); + halbtc8723b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); +} + +void halbtc8723b1ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +void halbtc8723b1ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + coex_sta->c2h_bt_info_req_sent = true; + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); +} + +void halbtc8723b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u32 num_of_bt_counter_chk = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ + /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + if ((coex_sta->high_priority_tx + coex_sta->high_priority_rx < 50) && + (bt_link_info->hid_exist == true)) + bt_link_info->hid_exist = false; + + if ((coex_sta->low_priority_tx > 1050) && + (!coex_sta->c2h_bt_inquiry_page)) + coex_sta->pop_event_cnt++; + + if ((coex_sta->low_priority_rx >= 950) && (!coex_sta->under_ips) + && (coex_sta->low_priority_rx >= + coex_sta->low_priority_tx) && + (!coex_sta->c2h_bt_inquiry_page)) + bt_link_info->slave_role = true; + else + bt_link_info->slave_role = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); + BTC_TRACE(trace_buf); + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + + /* This part is for wifi FW and driver to update BT's status as disabled. */ + /* The flow is as the following */ + /* 1. disable BT */ + /* 2. if all BT Tx/Rx counter=0, after 6 sec we query bt info */ + /* 3. Because BT will not rsp from mailbox, so wifi fw will know BT is disabled */ + /* 4. FW will rsp c2h for BT that driver will know BT is disabled. */ + if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) && + (reg_lp_rx == 0)) { + num_of_bt_counter_chk++; + if (num_of_bt_counter_chk >= 3) { + halbtc8723b1ant_query_bt_info(btcoexist); + num_of_bt_counter_chk = 0; + } + } + +} + + +void halbtc8723b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ + s32 wifi_rssi = 0; + boolean wifi_busy = false, wifi_under_b_mode = false; + static u8 cck_lock_counter = 0; + u32 total_cnt; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + +#if 1 + + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_VHT); + +#endif + + if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { + total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + + coex_sta->crc_ok_11n_vht; + + if ((coex_dm->bt_status == BT_8723B_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == + BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (coex_dm->bt_status == + BT_8723B_1ANT_BT_STATUS_SCO_BUSY)) { + if (coex_sta->crc_ok_cck > (total_cnt - + coex_sta->crc_ok_cck)) { + if (cck_lock_counter < 3) + cck_lock_counter++; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + if (!coex_sta->pre_ccklock) { + + if (cck_lock_counter >= 3) + coex_sta->cck_lock = true; + else + coex_sta->cck_lock = false; + } else { + if (cck_lock_counter == 0) + coex_sta->cck_lock = false; + else + coex_sta->cck_lock = true; + } + + if (coex_sta->cck_lock) + coex_sta->cck_ever_lock = true; + + coex_sta->pre_ccklock = coex_sta->cck_lock; + + +} + +boolean halbtc8723b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) +{ + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + + + } + + return false; +} + +void halbtc8723b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = true, bt_disabled = false, bt_change = false; + + /* This function check if bt is disabled */ + + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = false; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = false; + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = false; + } else { + bt_disable_cnt++; + if (bt_disable_cnt >= 10) + bt_disabled = true; + } + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + bt_change = true; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + + btcoexist->btc_set(btcoexist, + BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE, + &bt_change); + + coex_sta->bt_disabled = bt_disabled; + } else { + btcoexist->btc_set(btcoexist, + BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE, + &bt_change); + } +} + +void halbtc8723b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + bt_link_info->bt_hi_pri_link_exist = coex_sta->bt_hi_pri_link_exist; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = true; + bt_link_info->bt_link_exist = true; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = true; + else + bt_link_info->sco_only = false; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = true; + else + bt_link_info->a2dp_only = false; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = true; + else + bt_link_info->pan_only = false; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = true; + else + bt_link_info->hid_only = false; +} + +void halbtc8723b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean enable_auto_report) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = 0; + + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); + + btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); +} + +void halbtc8723b1ant_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable_auto_report) +{ + coex_dm->cur_bt_auto_report = enable_auto_report; + + if (!force_exec) { + if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) + return; + } + halbtc8723b1ant_set_bt_auto_report(btcoexist, + coex_dm->cur_bt_auto_report); + + coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; +} + +void halbtc8723b1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist + *btcoexist, IN boolean low_penalty_ra) +{ + u8 h2c_parameter[6] = {0}; + + h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ + + if (low_penalty_ra) { + h2c_parameter[1] |= BIT(0); + h2c_parameter[2] = + 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ + h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ + h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ + h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ + } + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); +} + +void halbtc8723b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) + return; + } + halbtc8723b1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, + coex_dm->cur_low_penalty_ra); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; +} + +void halbtc8723b1ant_sw_mechanism(IN struct btc_coexist *btcoexist, + IN boolean low_penalty_ra) +{ + halbtc8723b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); +} + +void halbtc8723b1ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + + + +void halbtc8723b1ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8723b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8723b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + +#if BT_8723B_1ANT_ANTDET_ENABLE +#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE + if (board_info->btdm_ant_num_by_ant_det == 2) { + if (type == 3) + type = 14; + else if (type == 4) + type = 13; + else if (type == 5) + type = 8; + } +#endif +#endif + + coex_sta->coex_table_type = type; + + switch (type) { + case 0: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 2: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 3: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 4: + if ((coex_sta->cck_ever_lock) && + (coex_sta->scan_ap_num <= 5)) + halbtc8723b1ant_coex_table(btcoexist, + force_exec, 0x55555555, 0xaaaa5a5a, + 0xffffff, 0x3); + else + halbtc8723b1ant_coex_table(btcoexist, + force_exec, 0x55555555, 0x5a5a5a5a, + 0xffffff, 0x3); + break; + case 5: + if ((coex_sta->cck_ever_lock) && + (coex_sta->scan_ap_num <= 5)) + halbtc8723b1ant_coex_table(btcoexist, + force_exec, 0x5a5a5a5a, 0x5aaa5a5a, + 0xffffff, 0x3); + else + halbtc8723b1ant_coex_table(btcoexist, + force_exec, 0x5a5a5a5a, 0x5aaa5a5a, + 0xffffff, 0x3); + break; + case 6: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 7: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 8: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 9: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 10: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 11: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 12: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 13: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 14: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); + break; + case 15: + halbtc8723b1ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); + break; + default: + break; + } +} + +void halbtc8723b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 h2c_parameter[1] = {0}; + + if (enable) + h2c_parameter[0] |= BIT(0); /* function enable */ + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + +void halbtc8723b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8723b1ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8723b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8723b1ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8723b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8723b1ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg, + IN boolean wifi_off) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u32 fw_ver = 0, u32tmp = 0, cnt_bt_cal_chk = 0; + boolean pg_ext_switch = false; + boolean use_ext_switch = false; + boolean is_in_mp_mode = false; + u8 h2c_parameter[2] = {0}, u8tmp = 0; + u32 u32tmp_1[4]; + boolean is_fw_ready; + + coex_dm->cur_ant_pos_type = ant_pos_type; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_EXT_SWITCH, &pg_ext_switch); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, + &fw_ver); /* [31:16]=fw ver, [15:0]=fw sub ver */ + + if ((fw_ver > 0 && fw_ver < 0xc0000) || pg_ext_switch) + use_ext_switch = true; + +#if BT_8723B_1ANT_ANTDET_ENABLE +#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE + if (ant_pos_type == BTC_ANT_PATH_PTA) { + if ((board_info->btdm_ant_det_finish) && + (board_info->btdm_ant_num_by_ant_det == 2)) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = BTC_ANT_PATH_WIFI; + else + ant_pos_type = BTC_ANT_PATH_BT; + } + } +#endif +#endif + + if (init_hwcfg) { + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, + 0x780); /* WiFi TRx Mask on */ + /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */ + /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); */ /*BT TRx Mask on */ + + if (fw_ver >= 0x180000) { + /* Use H2C to set GNT_BT to HIGH */ + h2c_parameter[0] = 1; + btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, + h2c_parameter); + + cnt_bt_cal_chk = 0; + while (1) { + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready); + if (is_fw_ready == false) { + BTC_SPRINTF(trace_buf , BT_TMP_BUF_SIZE, + ("halbtc8723b1ant_set_ant_path(): we don't need to wait for H2C command completion because of Fw download fail!!!\n")); + BTC_TRACE(trace_buf); + break; + } + + if (btcoexist->btc_read_1byte(btcoexist, + 0x765) == 0x18) + break; + + cnt_bt_cal_chk++; + if (cnt_bt_cal_chk > 20) + break; + } + } else { + /* set grant_bt to high */ + btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); + } + /* set wlan_act control by PTA */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x0); /* BT select s0/s1 is controlled by BT */ + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x39, 0x8, 0x1); + btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x944, 0x3, 0x3); + btcoexist->btc_write_1byte(btcoexist, 0x930, 0x77); + } else if (wifi_off) { + if (fw_ver >= 0x180000) { + /* Use H2C to set GNT_BT to HIGH */ + h2c_parameter[0] = 1; + btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, + h2c_parameter); + + cnt_bt_cal_chk = 0; + while (1) { + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready); + if (is_fw_ready == false) { + BTC_SPRINTF(trace_buf , BT_TMP_BUF_SIZE, + ("halbtc8723b1ant_set_ant_path(): we don't need to wait for H2C command completion because of Fw download fail!!!\n")); + BTC_TRACE(trace_buf); + break; + } + + if (btcoexist->btc_read_1byte(btcoexist, + 0x765) == 0x18) + break; + + cnt_bt_cal_chk++; + if (cnt_bt_cal_chk > 20) + break; + } + } else { + /* set grant_bt to high */ + btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); + } + /* set wlan_act to always low */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE, + &is_in_mp_mode); + if (!is_in_mp_mode) + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, + 0x20, 0x0); /* BT select s0/s1 is controlled by BT */ + else + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, + 0x20, 0x1); /* BT select s0/s1 is controlled by WiFi */ + + /* 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL BT Vendor 0xac=0xf002 */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp &= ~BIT(23); + u32tmp &= ~BIT(24); + btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); + } else { + /* Use H2C to set GNT_BT to LOW */ + if (fw_ver >= 0x180000) { + if (btcoexist->btc_read_1byte(btcoexist, 0x765) != 0) { + h2c_parameter[0] = 0; + btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, + h2c_parameter); + + cnt_bt_cal_chk = 0; + while (1) { + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready); + if (is_fw_ready == false) { + BTC_SPRINTF(trace_buf , + BT_TMP_BUF_SIZE, + ("halbtc8723b1ant_set_ant_path(): we don't need to wait for H2C command completion because of Fw download fail!!!\n")); + BTC_TRACE(trace_buf); + break; + } + + if (btcoexist->btc_read_1byte(btcoexist, + 0x765) == 0x0) + break; + + cnt_bt_cal_chk++; + if (cnt_bt_cal_chk > 20) + break; + } + } + } else { + /* BT calibration check */ + while (cnt_bt_cal_chk <= 20) { + u8tmp = btcoexist->btc_read_1byte(btcoexist, + 0x49d); + cnt_bt_cal_chk++; + if (u8tmp & BIT(0)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + break; + } + } + + /* set grant_bt to PTA */ + btcoexist->btc_write_1byte(btcoexist, 0x765, 0x0); + } + + if (btcoexist->btc_read_1byte(btcoexist, 0x76e) != 0xc) { + /* set wlan_act control by PTA */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + } + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x1); /* BT select s0/s1 is controlled by WiFi */ + } + + if (use_ext_switch) { + if (init_hwcfg) { + /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp &= ~BIT(23); + u32tmp |= BIT(24); + btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); + + + u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, + 0x948); + if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) + btcoexist->btc_write_4byte(btcoexist, 0x948, + u32tmp_1[0]); + else + btcoexist->btc_write_4byte(btcoexist, 0x948, + 0x0); + + + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) { + /* tell firmware "no antenna inverse" */ + h2c_parameter[0] = 0; + h2c_parameter[1] = 1; /* ext switch type */ + btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, + h2c_parameter); + } else { + /* tell firmware "antenna inverse" */ + h2c_parameter[0] = 1; + h2c_parameter[1] = 1; /* ext switch type */ + btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, + h2c_parameter); + } + } + + if (force_exec || + (coex_dm->cur_ant_pos_type != + coex_dm->pre_ant_pos_type)) { + /* ext switch setting */ + switch (ant_pos_type) { + case BTC_ANT_PATH_WIFI: + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x92c, 0x3, + 0x1); + else + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x92c, 0x3, + 0x2); + break; + case BTC_ANT_PATH_BT: + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x92c, 0x3, + 0x2); + else + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x92c, 0x3, + 0x1); + break; + default: + case BTC_ANT_PATH_PTA: + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x92c, 0x3, + 0x1); + else + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x92c, 0x3, + 0x2); + break; + } + } + } else { + if (init_hwcfg) { + /* 0x4c[23]=1, 0x4c[24]=0 Antenna control by 0x64 */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp |= BIT(23); + u32tmp &= ~BIT(24); + btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); + + /* Fix Ext switch Main->S1, Aux->S0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, + 0x0); + + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) { + + /* tell firmware "no antenna inverse" */ + h2c_parameter[0] = 0; + h2c_parameter[1] = + 0; /* internal switch type */ + btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, + h2c_parameter); + } else { + + /* tell firmware "antenna inverse" */ + h2c_parameter[0] = 1; + h2c_parameter[1] = + 0; /* internal switch type */ + btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, + h2c_parameter); + } + } + + if (force_exec || + (coex_dm->cur_ant_pos_type != + coex_dm->pre_ant_pos_type)) { + /* internal switch setting */ + switch (ant_pos_type) { + case BTC_ANT_PATH_WIFI: + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) { + u32tmp_1[0] = btcoexist->btc_read_4byte( + btcoexist, 0x948); + if ((u32tmp_1[0] == 0x40) || + (u32tmp_1[0] == 0x240)) + btcoexist->btc_write_4byte( + btcoexist, 0x948, + u32tmp_1[0]); + else + btcoexist->btc_write_4byte( + btcoexist, 0x948, 0x0); + } else { + u32tmp_1[0] = btcoexist->btc_read_4byte( + btcoexist, 0x948); + if ((u32tmp_1[0] == 0x40) || + (u32tmp_1[0] == 0x240)) + btcoexist->btc_write_4byte( + btcoexist, 0x948, + u32tmp_1[0]); + else + btcoexist->btc_write_4byte( + btcoexist, 0x948, + 0x280); + } + break; + case BTC_ANT_PATH_BT: + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) { + u32tmp_1[0] = btcoexist->btc_read_4byte( + btcoexist, 0x948); + if ((u32tmp_1[0] == 0x40) || + (u32tmp_1[0] == 0x240)) + btcoexist->btc_write_4byte( + btcoexist, 0x948, + u32tmp_1[0]); + else + btcoexist->btc_write_4byte( + btcoexist, 0x948, + 0x280); + } else { + u32tmp_1[0] = btcoexist->btc_read_4byte( + btcoexist, 0x948); + if ((u32tmp_1[0] == 0x40) || + (u32tmp_1[0] == 0x240)) + btcoexist->btc_write_4byte( + btcoexist, 0x948, + u32tmp_1[0]); + else + btcoexist->btc_write_4byte( + btcoexist, 0x948, 0x0); + } + break; + default: + case BTC_ANT_PATH_PTA: + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + btcoexist->btc_write_4byte( + btcoexist, 0x948, + 0x200); + else + btcoexist->btc_write_4byte( + btcoexist, 0x948, 0x80); + break; + } + } + } + + coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; +} + +void halbtc8723b1ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + /* halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); */ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + /* halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); */ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + + +void halbtc8723b1ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = false; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + /* recover to original 32k low power setting */ + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + case BTC_PS_LPS_ON: + halbtc8723b1ant_ps_tdma_check_for_power_save_state( + btcoexist, true); + halbtc8723b1ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + coex_sta->force_lps_on = true; + break; + case BTC_PS_LPS_OFF: + halbtc8723b1ant_ps_tdma_check_for_power_save_state( + btcoexist, false); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + default: + break; + } +} + + +void halbtc8723b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if (ap_enable) { + if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + + halbtc8723b1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + halbtc8723b1ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + + } else { + halbtc8723b1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + + h2c_parameter[0] = real_byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = real_byte5; + + coex_dm->ps_tdma_para[0] = real_byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = real_byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); +} + + +void halbtc8723b1ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = false; + u8 rssi_adjust_val = 0; + u8 ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51, + ps_tdma_byte3_val = 0x10; + s8 wifi_duration_adjust = 0x0; + static boolean pre_wifi_busy = false; + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + +#if BT_8723B_1ANT_ANTDET_ENABLE +#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE + if (board_info->btdm_ant_num_by_ant_det == 2) { + if (turn_on) + type = type + + 100; /* for WiFi RSSI low or BT RSSI low */ + else + type = 1; /* always translate to TDMA(off,1) for TDMA-off case */ + } + +#endif +#endif + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (wifi_busy != pre_wifi_busy) { + force_exec = true; + pre_wifi_busy = wifi_busy; + } + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) + return; + } + + if (coex_sta->scan_ap_num <= 5) { + wifi_duration_adjust = 5; + + if (coex_sta->a2dp_bit_pool >= 35) + wifi_duration_adjust = -10; + else if (coex_sta->a2dp_bit_pool >= 45) + wifi_duration_adjust = -15; + } else if (coex_sta->scan_ap_num >= 40) { + wifi_duration_adjust = -15; + + if (coex_sta->a2dp_bit_pool < 35) + wifi_duration_adjust = -5; + else if (coex_sta->a2dp_bit_pool < 45) + wifi_duration_adjust = -10; + } else if (coex_sta->scan_ap_num >= 20) { + wifi_duration_adjust = -10; + + if (coex_sta->a2dp_bit_pool >= 45) + wifi_duration_adjust = -15; + } else { + wifi_duration_adjust = 0; + + if (coex_sta->a2dp_bit_pool >= 35) + wifi_duration_adjust = -10; + else if (coex_sta->a2dp_bit_pool >= 45) + wifi_duration_adjust = -15; + } + + if ((type == 1) || (type == 2) || (type == 9) || (type == 11) || + (type == 101) + || (type == 102) || (type == 109) || (type == 101)) { + if (!coex_sta->force_lps_on) { /* Native power save TDMA, only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */ + ps_tdma_byte0_val = 0x61; /* no null-pkt */ + ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */ + ps_tdma_byte4_val = + 0x10; /* 0x778 = d/1 toggle, no dynamic slot */ + } else { + ps_tdma_byte0_val = 0x51; /* null-pkt */ + ps_tdma_byte3_val = 0x10; /* tx-pause at BT-slot */ + ps_tdma_byte4_val = + 0x50; /* 0x778 = d/1 toggle, dynamic slot */ + } + } else if ((type == 3) || (type == 13) || (type == 14) || + (type == 103) || (type == 113) || (type == 114)) { + ps_tdma_byte0_val = 0x51; /* null-pkt */ + ps_tdma_byte3_val = 0x10; /* tx-pause at BT-slot */ + ps_tdma_byte4_val = + 0x10; /* 0x778 = d/1 toggle, no dynamic slot */ +#if 0 + if (!wifi_busy) + ps_tdma_byte4_val = ps_tdma_byte4_val | + 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ +#endif + } else { /* native power save case */ + ps_tdma_byte0_val = 0x61; /* no null-pkt */ + ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */ + ps_tdma_byte4_val = + 0x11; /* 0x778 = d/1 toggle, no dynamic slot */ + /* psTdmaByte4Va is not defne for 0x778 = d/1, 1/1 case */ + } + + /* if (bt_link_info->slave_role == true) */ + if ((bt_link_info->slave_role == true) && (bt_link_info->a2dp_exist)) + ps_tdma_byte4_val = ps_tdma_byte4_val | + 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ + + if (type > 100) { + ps_tdma_byte0_val = ps_tdma_byte0_val | + 0x82; /* set antenna control by SW */ + ps_tdma_byte3_val = ps_tdma_byte3_val | + 0x60; /* set antenna no toggle, control by antenna diversity */ + } + + + if (turn_on) { + switch (type) { + default: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, + 0x1a, 0x1a, 0x0, ps_tdma_byte4_val); + break; + case 1: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x3a + + wifi_duration_adjust, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 2: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x2d + + wifi_duration_adjust, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 3: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x30, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 4: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93, + 0x15, 0x3, 0x14, 0x0); + break; + case 5: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x1f, 0x3, + ps_tdma_byte3_val, 0x11); + break; + case 6: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x20, 0x3, + ps_tdma_byte3_val, 0x11); + break; + case 7: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13, + 0xc, 0x5, 0x0, 0x0); + break; + case 8: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93, + 0x25, 0x3, 0x10, 0x0); + break; + case 9: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x21, 0x3, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 10: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13, + 0xa, 0xa, 0x0, 0x40); + break; + case 11: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x21, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 12: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, + 0x0a, 0x0a, 0x0, 0x50); + break; + case 13: + if (coex_sta->scan_ap_num <= 3) + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x40, 0x3, + ps_tdma_byte3_val, + ps_tdma_byte4_val); + else + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x21, 0x3, + ps_tdma_byte3_val, + ps_tdma_byte4_val); + break; + case 14: + if (coex_sta->scan_ap_num <= 3) + halbtc8723b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x30, 0x3, 0x10, 0x50); + else + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x21, 0x3, + ps_tdma_byte3_val, + ps_tdma_byte4_val); + break; + case 15: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13, + 0xa, 0x3, 0x8, 0x0); + break; + case 16: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93, + 0x15, 0x3, 0x10, 0x0); + break; + case 18: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93, + 0x25, 0x3, 0x10, 0x0); + break; + case 20: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x3f, 0x03, + ps_tdma_byte3_val, 0x10); + break; + case 21: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, 0x11); + break; + case 22: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x25, 0x03, + ps_tdma_byte3_val, 0x10); + break; + case 23: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x3, 0x31, 0x18); + break; + case 24: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, + 0x15, 0x3, 0x31, 0x18); + break; + case 25: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, + 0xa, 0x3, 0x31, 0x18); + break; + case 26: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, + 0xa, 0x3, 0x31, 0x18); + break; + case 27: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x3, 0x31, 0x98); + break; + case 28: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x69, + 0x25, 0x3, 0x31, 0x0); + break; + case 29: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xab, + 0x1a, 0x1a, 0x1, 0x10); + break; + case 30: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, 0x10); + break; + case 31: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xd3, + 0x1a, 0x1a, 0, 0x58); + break; + case 32: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x35, 0x3, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 33: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x35, 0x3, + ps_tdma_byte3_val, 0x10); + break; + case 34: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x53, + 0x1a, 0x1a, 0x0, 0x10); + break; + case 35: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x63, + 0x1a, 0x1a, 0x0, 0x10); + break; + case 36: + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xd3, + 0x12, 0x3, 0x14, 0x50); + break; + case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */ + /* here softap mode screen off will cost 70-80mA for phone */ + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x23, + 0x18, 0x00, 0x10, 0x24); + break; + + /* for 1-Ant translate to 2-Ant */ + case 101: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x3a + + wifi_duration_adjust, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 102: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x2d + + wifi_duration_adjust, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 103: + /* halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, 0x1d, 0x1d, 0x0, ps_tdma_byte4_val); */ + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x3a, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 105: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x15, 0x3, + ps_tdma_byte3_val, 0x11); + break; + case 106: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x20, 0x3, + ps_tdma_byte3_val, 0x11); + break; + case 109: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x21, 0x3, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 111: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x21, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 113: + /* halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, 0x12, 0x12, 0x0, ps_tdma_byte4_val); */ + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x21, 0x3, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 114: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x21, 0x3, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 120: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x3f, 0x03, + ps_tdma_byte3_val, 0x10); + break; + case 122: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x25, 0x03, + ps_tdma_byte3_val, 0x10); + break; + case 132: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x25, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 133: + halbtc8723b1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x25, 0x03, + ps_tdma_byte3_val, 0x11); + break; + + } + } else { + + /* disable PS tdma */ + switch (type) { + case 8: /* PTA Control */ + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x8, + 0x0, 0x0, 0x0, 0x0); + break; + case 0: + default: /* Software control, Antenna at BT side */ + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x0, 0x0); + break; + case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */ + halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x48, 0x0); + break; + } + } + rssi_adjust_val = 0; + btcoexist->btc_set(btcoexist, + BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", + btcoexist->btc_read_4byte(btcoexist, 0x948), + btcoexist->btc_read_1byte(btcoexist, 0x765), + btcoexist->btc_read_1byte(btcoexist, 0x67)); + BTC_TRACE(trace_buf); + + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; +} + +void halbtc8723b1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist + *btcoexist, IN u8 wifi_status) +{ + static s32 up, dn, m, n, wait_count; + s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ + u8 retry_count = 0, bt_info_ext; + boolean wifi_busy = false; + + if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status) + wifi_busy = true; + else + wifi_busy = false; + + if ((BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == + wifi_status) || + (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) || + (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT == + wifi_status)) { + if (coex_dm->cur_ps_tdma != 1 && + coex_dm->cur_ps_tdma != 2 && + coex_dm->cur_ps_tdma != 3 && + coex_dm->cur_ps_tdma != 9) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 9); + coex_dm->ps_tdma_du_adj_type = 9; + + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } + return; + } + + if (!coex_dm->auto_tdma_adjust) { + coex_dm->auto_tdma_adjust = true; + + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + /* ============ */ + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } else { + /* acquire the BT TRx retry count from BT_Info byte2 */ + retry_count = coex_sta->bt_retry_cnt; + bt_info_ext = coex_sta->bt_info_ext; + + if ((coex_sta->low_priority_tx) > 1050 || + (coex_sta->low_priority_rx) > 1250) + retry_count++; + + result = 0; + wait_count++; + + if (retry_count == + 0) { /* no retry in the last 2-second duration */ + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ + wait_count = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + } + } else if (retry_count <= + 3) { /* <=3 retry in the last 2-second duration */ + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ + if (wait_count <= 2) + m++; /* to avoid loop between the two levels */ + else + m = 1; + + if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ + if (wait_count == 1) + m++; /* to avoid loop between the two levels */ + else + m = 1; + + if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + + if (result == -1) { + /* if( (BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && + ((coex_dm->cur_ps_tdma == 1) ||(coex_dm->cur_ps_tdma == 2)) ) + { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } + else */ if (coex_dm->cur_ps_tdma == 1) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } + } else if (result == 1) { + /* if( (BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && + ((coex_dm->cur_ps_tdma == 1) ||(coex_dm->cur_ps_tdma == 2)) ) + { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } + else */ if (coex_dm->cur_ps_tdma == 11) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = 1; + } + } else { /* no change */ + /* Bryant Modify + if(wifi_busy != pre_wifi_busy) + { + pre_wifi_busy = wifi_busy; + halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma); + } + */ + + } + + if (coex_dm->cur_ps_tdma != 1 && + coex_dm->cur_ps_tdma != 2 && + coex_dm->cur_ps_tdma != 9 && + coex_dm->cur_ps_tdma != 11) { + /* recover to previous adjust type */ + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + coex_dm->ps_tdma_du_adj_type); + } + } +} + + +/* ********************************************* + * + * Non-Software Coex Mechanism start + * + * ********************************************* */ +void halbtc8723b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) +{ + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, + false, false); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + + +void halbtc8723b1ant_action_hs(IN struct btc_coexist *btcoexist) +{ + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8723b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, ap_enable = false, wifi_busy = false, + bt_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + if (coex_sta->bt_abnormal_scan) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 33); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + } else if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + NORMAL_EXEC, false, false); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || + (bt_link_info->a2dp_exist)) { + /* SCO/HID/A2DP busy */ + + if (coex_sta->c2h_bt_remote_name_req) + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 33); + else + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if ((bt_link_info->pan_exist) || (wifi_busy)) { + + if (coex_sta->c2h_bt_remote_name_req) + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 33); + else + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + NORMAL_EXEC, false, false); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + + } +} + +void halbtc8723b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist + *btcoexist, IN u8 wifi_status) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* tdma and coex table */ + + if (bt_link_info->sco_exist) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + } else { /* HID */ + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + } +} + +void halbtc8723b1ant_action_wifi_only(IN struct btc_coexist *btcoexist) +{ + halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, + false, false); +} + +void halbtc8723b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, + false, false); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8723b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist + *btcoexist, IN u8 wifi_status) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if ((coex_sta->low_priority_rx >= 950) && (!coex_sta->under_ips)) + bt_link_info->slave_role = true; + else + bt_link_info->slave_role = false; + + if (bt_link_info->hid_only) { /* HID */ + halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, + wifi_status); + coex_dm->auto_tdma_adjust = false; + return; + } else if (bt_link_info->a2dp_only) { /* A2DP */ + if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = false; + } else { + halbtc8723b1ant_tdma_duration_adjust_for_acl(btcoexist, + wifi_status); + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = true; + } + } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || + (bt_link_info->hid_exist && bt_link_info->a2dp_exist && + bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = false; + } else if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { /* HID+A2DP */ + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); + coex_dm->auto_tdma_adjust = false; + + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && + bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ + + if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 9); + else + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 3); + + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = false; + } else { + /* BT no-profile busy (0x9) */ + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = false; + } +} + +void halbtc8723b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +{ + + /* tdma and coex table */ + halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, + false, false); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8723b1ant_action_wifi_not_connected_scan(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + /* tdma and coex table */ + if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + if (bt_link_info->a2dp_exist) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else if (bt_link_info->a2dp_exist && + bt_link_info->pan_exist) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 22); + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 20); + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } else { + /* Bryant Add */ + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + NORMAL_EXEC, false, false); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8723b1ant_action_wifi_not_connected_asso_auth( + IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + /* tdma and coex table */ + if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || + (bt_link_info->a2dp_exist)) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); + } else if (bt_link_info->pan_exist) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); + } else { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + NORMAL_EXEC, false, false); + halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2); + } +} + +void halbtc8723b1ant_action_wifi_connected_scan(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + /* tdma and coex table */ + if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + if (bt_link_info->a2dp_exist) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else if (bt_link_info->a2dp_exist && + bt_link_info->pan_exist) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 22); + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 20); + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } else { + /* Bryant Add */ + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + NORMAL_EXEC, false, false); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8723b1ant_action_wifi_connected_specific_packet( + IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + /* no specific packet process for both WiFi and BT very busy */ + if ((wifi_busy) && ((bt_link_info->pan_exist) || + (coex_sta->num_of_profile >= 2))) + return; + + /* tdma and coex table */ + if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + } else if (bt_link_info->a2dp_exist) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if (bt_link_info->pan_exist) { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + NORMAL_EXEC, false, false); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8723b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +{ + boolean wifi_busy = false; + boolean scan = false, link = false, roam = false; + boolean under_4way = false, ap_enable = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect()===>\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + if (under_4way) { + halbtc8723b1ant_action_wifi_connected_specific_packet( + btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + if (scan || link || roam) { + if (scan) + halbtc8723b1ant_action_wifi_connected_scan(btcoexist); + else + halbtc8723b1ant_action_wifi_connected_specific_packet( + btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + + /* tdma and coex table */ + if (!wifi_busy) { + if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + halbtc8723b1ant_action_wifi_connected_bt_acl_busy( + btcoexist, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } else { + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); + halbtc8723b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); + /* if ((coex_sta->high_priority_tx) + + (coex_sta->high_priority_rx) <= 60) */ + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 2); + /* else + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); */ + } + } else { + if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + halbtc8723b1ant_action_wifi_connected_bt_acl_busy( + btcoexist, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } else { + /* halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); + halbtc8723b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); + if ((coex_sta->high_priority_tx) + + (coex_sta->high_priority_rx) <= 60) + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 2); + else + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); */ + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + halbtc8723b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); + halbtc8723b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + + } + } +} + +void halbtc8723b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, bt_hs_on = false, wifi_busy = false; + boolean increase_scan_dev_num = false; + boolean bt_ctrl_agg_buf_size = false; + boolean miracast_plus_bt = false; + u8 agg_buf_size = 5; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0, wifi_bw; + u8 iot_peer = BTC_IOT_PEER_UNKNOWN; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->bt_whck_test) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under WHCK TEST!!!\n"); + BTC_TRACE(trace_buf); + halbtc8723b1ant_action_bt_whck_test(btcoexist); + return; + } + + if ((BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + increase_scan_dev_num = true; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, + &increase_scan_dev_num); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + if (bt_link_info->bt_link_exist) { + halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, + 0, 1); + miracast_plus_bt = true; + } else { + halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, + 0, 0); + miracast_plus_bt = false; + } + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + + if (((bt_link_info->a2dp_exist) || (wifi_busy)) && + (coex_sta->c2h_bt_inquiry_page)) + halbtc8723b1ant_action_bt_inquiry(btcoexist); + else + halbtc8723b1ant_action_wifi_multi_port(btcoexist); + + return; + } + + miracast_plus_bt = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if ((bt_link_info->bt_link_exist) && (wifi_connected)) { + halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); + + /* if(BTC_IOT_PEER_CISCO != iot_peer) */ + if ((BTC_IOT_PEER_CISCO != iot_peer) && + (BTC_IOT_PEER_BROADCOM != iot_peer)) { + if (bt_link_info->sco_exist) /* if (bt_link_info->bt_hi_pri_link_exist) */ + /* halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, true, false, 0x5); */ + halbtc8723b1ant_limited_rx(btcoexist, + NORMAL_EXEC, true, false, 0x5); + else + halbtc8723b1ant_limited_rx(btcoexist, + NORMAL_EXEC, false, false, 0x5); + /* halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8); */ + } else { + if (bt_link_info->sco_exist) + halbtc8723b1ant_limited_rx(btcoexist, + NORMAL_EXEC, true, false, 0x5); + else if (bt_link_info->hid_exist) + halbtc8723b1ant_limited_rx(btcoexist, + NORMAL_EXEC, false, true, 0x3); + else { + if (BTC_WIFI_BW_HT40 == wifi_bw) + halbtc8723b1ant_limited_rx(btcoexist, + NORMAL_EXEC, false, true, 0x10); + else + halbtc8723b1ant_limited_rx(btcoexist, + NORMAL_EXEC, false, true, 0x8); + } + } + + halbtc8723b1ant_sw_mechanism(btcoexist, true); + + /* low pelnaty ra in pcr ra */ + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 35); + + } else { + halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + + halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x5); + + halbtc8723b1ant_sw_mechanism(btcoexist, false); + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8723b1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8723b1ant_action_hs(btcoexist); + return; + } + + + if (!wifi_connected) { + boolean scan = false, link = false, roam = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is non connected-idle !!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + if (scan || link || roam) { + if (scan) + halbtc8723b1ant_action_wifi_not_connected_scan( + btcoexist); + else + halbtc8723b1ant_action_wifi_not_connected_asso_auth( + btcoexist); + } else + halbtc8723b1ant_action_wifi_not_connected(btcoexist); + } else /* wifi LPS/Busy */ + halbtc8723b1ant_action_wifi_connected(btcoexist); +} + +void halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + /* force to reset coex mechanism */ + + /* sw all off */ + halbtc8723b1ant_sw_mechanism(btcoexist, false); + + /* halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ + /* halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */ + + coex_sta->pop_event_cnt = 0; +} + +void halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean back_up, IN boolean wifi_only) +{ + u32 u32tmp = 0; /* , fw_ver; */ + u8 u8tmpa = 0, u8tmpb = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 1Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + psd_scan->ant_det_is_ant_det_available = false; + + + /* Give bt_coex_supported_version the default value */ + coex_sta->bt_coex_supported_version = 0; + + /* 0xf0[15:12] --> Chip Cut information */ + coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, + 0xf1) & 0xf0) >> 4; + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + + /* 0x790[5:0]=0x5 */ + btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); + + /* Enable counter statistics */ + /* btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); */ /*0x76e[3] =1, WLAN_Act control by PTA */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); + + + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1); */ /*BT select s0/s1 is controlled by WiFi */ + + halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + + /* Antenna config */ + if (wifi_only) + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, + FORCE_EXEC, true, false); + else + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, + FORCE_EXEC, true, false); + + /* PTA parameter */ + halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); + u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); + u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", + u32tmp, u8tmpa, u8tmpb); + BTC_TRACE(trace_buf); + +} + +/* Donot remove optimize off flag, otherwise antenna detection would trigger BT collapsed */ +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif +void halbtc8723b1ant_mechanism_switch(IN struct btc_coexist *btcoexist, + IN boolean bSwitchTo2Antenna) +{ + + if (bSwitchTo2Antenna) { + + /* BT TRx mask off */ + btcoexist->btc_set_bt_trx_mask(btcoexist, 0); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT TRx Mask off for mechanism_switch\n"); + + BTC_TRACE(trace_buf); + + } else { + + /* BT TRx mask on */ + btcoexist->btc_set_bt_trx_mask(btcoexist, 1); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT TRx Mask on for mechanism_switch\n"); + + BTC_TRACE(trace_buf); + } + + +#if 0 + if (bSwitchTo2Antenna) { /* 1-Ant -> 2-Ant */ + /* un-lock TRx Mask setup for 8723b f-cut */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, 0x80, 0x1); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, 0x1, 0x1); + /* WiFi TRx Mask on */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, + 0x0); + + /* BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 */ + btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x2c, + 0x7c45); + btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x30, + 0x7c45); + + /* BT TRx Mask on */ + btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x1); + + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, + FORCE_EXEC, false, false); + } else { + /* WiFi TRx Mask on */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, + 0x780); + + /* lock TRx Mask setup for 8723b f-cut */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, 0x80, 0x0); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, 0x1, 0x0); + + /* BT TRx Mask on */ + btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); + + /* BT TRx Mask ock 0x2c[0], 0x30[0] = 0 */ + btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x2c, + 0x7c44); + btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x30, + 0x7c44); + + + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + FORCE_EXEC, false, false); + } + +#endif +} + +u32 halbtc8723b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val) +{ + u8 j; + u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0; + u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200, + 174, 151, 132, 115, 100, 86, 74, 62, 51, 42, + 32, 23, 15, 7, 0 + }; + + if (val == 0) + return 0; + + tmp = val; + + while (1) { + if (tmp == 1) + break; + + tmp = (tmp >> 1); + shiftcount++; + } + + + val_integerd_b = shiftcount + 1; + + tmp2 = 1; + for (j = 1; j <= val_integerd_b; j++) + tmp2 = tmp2 * 2; + + tmp = (val * 100) / tmp2; + tindex = tmp / 5; + + if (tindex > 20) + tindex = 20; + + val_fractiond_b = table_fraction[tindex]; + + result = val_integerd_b * 100 - val_fractiond_b; + + return result; + + +} + +void halbtc8723b1ant_psd_show_antenna_detect_result(IN struct btc_coexist + *btcoexist) +{ + u8 *cli_buf = btcoexist->cli_buf; + struct btc_board_info *board_info = &btcoexist->board_info; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n============[Antenna Detection info] ============\n"); + CL_PRINTF(cli_buf); + + if (psd_scan->ant_det_result == 1) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)", + "Ant Det Result", "2-Antenna (Bad-Isolation)", + BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); + else if (psd_scan->ant_det_result == 2) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)", + "Ant Det Result", "2-Antenna (Good-Isolation)", + BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION + + psd_scan->ant_det_thres_offset, + BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)", + "Ant Det Result", "1-Antenna", + BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT, + BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION + + psd_scan->ant_det_thres_offset); + + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ", + "Antenna Detection Finish", + (board_info->btdm_ant_det_finish + ? "Yes" : "No")); + CL_PRINTF(cli_buf); + + switch (psd_scan->ant_det_result) { + case 0: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(BT is not available)"); + break; + case 1: /* 2-Ant bad-isolation */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(BT is available)"); + break; + case 2: /* 2-Ant good-isolation */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(BT is available)"); + break; + case 3: /* 1-Ant */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(BT is available)"); + break; + case 4: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(Uncertainty result)"); + break; + case 5: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(Pre-Scan fai)"); + break; + case 6: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(WiFi is Scanning)"); + break; + case 7: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(BT is not idle)"); + break; + case 8: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(Abort by WiFi Scanning)"); + break; + case 9: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(Antenna Init is not ready)"); + break; + case 10: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(BT is Inquiry or page)"); + break; + case 11: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "(BT is Disabled)"); + break; + } + CL_PRINTF(cli_buf); + + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "Ant Detect Total Count", psd_scan->ant_det_try_count); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "Ant Detect Fail Count", psd_scan->ant_det_fail_count); + CL_PRINTF(cli_buf); + + if ((!board_info->btdm_ant_det_finish) && + (psd_scan->ant_det_result != 5)) + return; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Response", + (psd_scan->ant_det_result ? "ok" : "fail")); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ms", "BT Tx Time", + psd_scan->ant_det_bt_tx_time); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "BT Tx Ch", + psd_scan->ant_det_bt_le_channel); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", + "WiFi PSD Cent-Ch/Offset/Span", + psd_scan->real_cent_freq, psd_scan->real_offset, + psd_scan->real_span); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB", + "PSD Pre-Scan Peak Value", + psd_scan->ant_det_pre_psdscan_peak_val / 100); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (<= %d)", + "PSD Pre-Scan result", + (psd_scan->ant_det_result != 5 ? "ok" : "fail"), + BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND + + psd_scan->ant_det_thres_offset); + CL_PRINTF(cli_buf); + + if (psd_scan->ant_det_result == 5) + return; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s dB", + "PSD Scan Peak Value", psd_scan->ant_det_peak_val); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s MHz", + "PSD Scan Peak Freq", psd_scan->ant_det_peak_freq); + CL_PRINTF(cli_buf); + + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package", + (board_info->tfbga_package) ? "Yes" : "No"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "PSD Threshold Offset", psd_scan->ant_det_thres_offset); + CL_PRINTF(cli_buf); + +} + +void halbtc8723b1ant_psd_showdata(IN struct btc_coexist *btcoexist) +{ + u8 *cli_buf = btcoexist->cli_buf; + u32 delta_freq_per_point; + u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n\n============[PSD info] (%d)============\n", + psd_scan->psd_gen_count); + CL_PRINTF(cli_buf); + + if (psd_scan->psd_gen_count == 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n"); + CL_PRINTF(cli_buf); + return; + } + + if (psd_scan->psd_point == 0) + delta_freq_per_point = 0; + else + delta_freq_per_point = psd_scan->psd_band_width / + psd_scan->psd_point; + + /* if (psd_scan->is_psd_show_max_only) */ + if (0) { + psd_rep1 = psd_scan->psd_max_value / 100; + psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100; + + freq = ((psd_scan->real_cent_freq - 20) * 1000000 + + psd_scan->psd_max_value_point * delta_freq_per_point); + freq1 = freq / 1000000; + freq2 = freq / 1000 - freq1 * 1000; + + if (freq2 < 100) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n Freq = %d.0%d MHz", + freq1, freq2); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n Freq = %d.%d MHz", + freq1, freq2); + + if (psd_rep2 < 10) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + ", Value = %d.0%d dB, (%d)\n", + psd_rep1, psd_rep2, psd_scan->psd_max_value); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + ", Value = %d.%d dB, (%d)\n", + psd_rep1, psd_rep2, psd_scan->psd_max_value); + + CL_PRINTF(cli_buf); + } else { + m = psd_scan->psd_start_point; + n = psd_scan->psd_start_point; + i = 1; + j = 1; + + while (1) { + do { + freq = ((psd_scan->real_cent_freq - 20) * + 1000000 + m * + delta_freq_per_point); + freq1 = freq / 1000000; + freq2 = freq / 1000 - freq1 * 1000; + + if (i == 1) { + if (freq2 == 0) + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Freq%6d.000", + freq1); + else if (freq2 < 100) + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Freq%6d.0%2d", + freq1, + freq2); + else + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Freq%6d.%3d", + freq1, + freq2); + } else if ((i % 8 == 0) || + (m == psd_scan->psd_stop_point)) { + if (freq2 == 0) + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.000\n", freq1); + else if (freq2 < 100) + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.0%2d\n", freq1, + freq2); + else + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.%3d\n", freq1, + freq2); + } else { + if (freq2 == 0) + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.000", freq1); + else if (freq2 < 100) + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.0%2d", freq1, + freq2); + else + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%6d.%3d", freq1, + freq2); + } + + i++; + m++; + CL_PRINTF(cli_buf); + + } while ((i <= 8) && (m <= psd_scan->psd_stop_point)); + + + do { + psd_rep1 = psd_scan->psd_report_max_hold[n] / + 100; + psd_rep2 = psd_scan->psd_report_max_hold[n] - + psd_rep1 * + 100; + + if (j == 1) { + if (psd_rep2 < 10) + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Val %7d.0%d", + psd_rep1, + psd_rep2); + else + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "\r\n Val %7d.%d", + psd_rep1, + psd_rep2); + } else if ((j % 8 == 0) || + (n == psd_scan->psd_stop_point)) { + if (psd_rep2 < 10) + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%7d.0%d\n", psd_rep1, + psd_rep2); + else + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%7d.%d\n", psd_rep1, + psd_rep2); + } else { + if (psd_rep2 < 10) + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%7d.0%d", psd_rep1, + psd_rep2); + else + CL_SPRINTF(cli_buf, + BT_TMP_BUF_SIZE, + "%7d.%d", psd_rep1, + psd_rep2); + } + + j++; + n++; + CL_PRINTF(cli_buf); + + } while ((j <= 8) && (n <= psd_scan->psd_stop_point)); + + if ((m > psd_scan->psd_stop_point) || + (n > psd_scan->psd_stop_point)) + break; + + i = 1; + j = 1; + } + } + + +} + +void halbtc8723b1ant_psd_max_holddata(IN struct btc_coexist *btcoexist, + IN u32 gen_count) +{ + u32 i = 0, i_max = 0, val_max = 0; + + if (gen_count == 1) { + memcpy(psd_scan->psd_report_max_hold, + psd_scan->psd_report, + BT_8723B_1ANT_ANTDET_PSD_POINTS * sizeof(u32)); + + psd_scan->psd_max_value_point = 0; + psd_scan->psd_max_value = 0; + + } else { + for (i = psd_scan->psd_start_point; + i <= psd_scan->psd_stop_point; i++) { + if (psd_scan->psd_report[i] > + psd_scan->psd_report_max_hold[i]) + psd_scan->psd_report_max_hold[i] = + psd_scan->psd_report[i]; + + /* search Max Value */ + if (i == psd_scan->psd_start_point) { + i_max = i; + val_max = psd_scan->psd_report_max_hold[i]; + } else { + if (psd_scan->psd_report_max_hold[i] > + val_max) { + i_max = i; + val_max = psd_scan->psd_report_max_hold[i]; + } + } + + } + + psd_scan->psd_max_value_point = i_max; + psd_scan->psd_max_value = val_max; + + } + + +} + +u32 halbtc8723b1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) +{ + /* reg 0x808[9:0]: FFT data x */ + /* reg 0x808[22]: 0-->1 to get 1 FFT data y */ + /* reg 0x8b4[15:0]: FFT data y report */ + + u32 val = 0, psd_report = 0; + int k = 0; + + val = btcoexist->btc_read_4byte(btcoexist, 0x808); + + val &= 0xffbffc00; + val |= point; + + btcoexist->btc_write_4byte(btcoexist, 0x808, val); + + val |= 0x00400000; + btcoexist->btc_write_4byte(btcoexist, 0x808, val); + + while (1) { + if (k++ > BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY) + break; + } + + val = btcoexist->btc_read_4byte(btcoexist, 0x8b4); + + psd_report = val & 0x0000ffff; + + return psd_report; +} + + +boolean halbtc8723b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points, + IN u32 avgnum, IN u32 loopcnt) +{ + u32 i, val, n, k = 0, j, point_index = 0; + u32 points1 = 0, psd_report = 0; + u32 start_p = 0, stop_p = 0, delta_freq_per_point = 156250; + u32 psd_center_freq = 20 * 10 ^ 6; + boolean outloop = false, scan , roam, is_sweep_ok = true; + u8 flag = 0; + u32 tmp; + u32 wifi_original_channel = 1; + + psd_scan->is_psd_running = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n"); + BTC_TRACE(trace_buf); + + do { + switch (flag) { + case 0: /* Get PSD parameters */ + default: + + psd_scan->psd_band_width = 40 * 1000000; + psd_scan->psd_point = points; + psd_scan->psd_start_base = points / 2; + psd_scan->psd_avg_num = avgnum; + psd_scan->real_cent_freq = cent_freq; + psd_scan->real_offset = offset; + psd_scan->real_span = span; + + + points1 = psd_scan->psd_point; + delta_freq_per_point = psd_scan->psd_band_width / + psd_scan->psd_point; + + /* PSD point setup */ + val = btcoexist->btc_read_4byte(btcoexist, 0x808); + val &= 0xffff0fff; + + switch (psd_scan->psd_point) { + case 128: + val |= 0x0; + break; + case 256: + default: + val |= 0x00004000; + break; + case 512: + val |= 0x00008000; + break; + case 1024: + val |= 0x0000c000; + break; + } + + switch (psd_scan->psd_avg_num) { + case 1: + val |= 0x0; + break; + case 8: + val |= 0x00001000; + break; + case 16: + val |= 0x00002000; + break; + case 32: + default: + val |= 0x00003000; + break; + } + btcoexist->btc_write_4byte(btcoexist, 0x808, val); + + flag = 1; + break; + case 1: /* calculate the PSD point index from freq/offset/span */ + psd_center_freq = psd_scan->psd_band_width / 2 + + offset * (1000000); + + start_p = psd_scan->psd_start_base + (psd_center_freq - + span * (1000000) / 2) / delta_freq_per_point; + psd_scan->psd_start_point = start_p - + psd_scan->psd_start_base; + + stop_p = psd_scan->psd_start_base + (psd_center_freq + + span * (1000000) / 2) / delta_freq_per_point; + psd_scan->psd_stop_point = stop_p - + psd_scan->psd_start_base - 1; + + flag = 2; + break; + case 2: /* set RF channel/BW/Mode */ + + /* set 3-wire off */ + val = btcoexist->btc_read_4byte(btcoexist, 0x88c); + val |= 0x00300000; + btcoexist->btc_write_4byte(btcoexist, 0x88c, val); + + /* CCK off */ + val = btcoexist->btc_read_4byte(btcoexist, 0x800); + val &= 0xfeffffff; + btcoexist->btc_write_4byte(btcoexist, 0x800, val); + + /* store WiFi original channel */ + wifi_original_channel = btcoexist->btc_get_rf_reg( + btcoexist, BTC_RF_A, 0x18, 0x3ff); + + /* Set RF channel */ + if (cent_freq == 2484) + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, + 0x18, 0x3ff, 0xe); + else + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, + 0x18, 0x3ff, (cent_freq - 2412) / 5 + + 1); /* WiFi TRx Mask on */ + + + /* Set RF Rx filter corner */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, + 0xfffff, 0x3e4); + + /* Set TRx mask off */ + /* un-lock TRx Mask setup */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, + 0x80, 0x1); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, + 0x1, 0x1); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, + 0xfffff, 0x0); + + /* Set RF mode = Rx, RF Gain = 0x8a0 */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0, + 0xfffff, 0x308a0); + + while (1) { + if (k++ > BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY) + break; + } + flag = 3; + break; + case 3: + psd_scan->psd_gen_count = 0; + for (j = 1; j <= loopcnt; j++) { + + btcoexist->btc_get(btcoexist, + BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, + BTC_GET_BL_WIFI_ROAM, &roam); + + if (scan || roam) { + is_sweep_ok = false; + break; + } + memset(psd_scan->psd_report, 0, + psd_scan->psd_point * sizeof(u32)); + start_p = psd_scan->psd_start_point + + psd_scan->psd_start_base; + stop_p = psd_scan->psd_stop_point + + psd_scan->psd_start_base + 1; + + i = start_p; + point_index = 0; + + while (i < stop_p) { + if (i >= points1) + psd_report = + halbtc8723b1ant_psd_getdata( + btcoexist, i - points1); + else + psd_report = + halbtc8723b1ant_psd_getdata( + btcoexist, i); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "Point=%d, psd_raw_data = 0x%08x\n", + i, psd_report); + BTC_TRACE(trace_buf); + if (psd_report == 0) + tmp = 0; + else + /* tmp = 20*log10((double)psd_report); */ + /* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */ + tmp = 6 * halbtc8723b1ant_psd_log2base( + btcoexist, psd_report); + + n = i - psd_scan->psd_start_base; + psd_scan->psd_report[n] = tmp; + + + halbtc8723b1ant_psd_max_holddata( + btcoexist, j); + + i++; + + } + + psd_scan->psd_gen_count = j; + } + + flag = 100; + break; + case 99: /* error */ + + outloop = true; + break; + case 100: /* recovery */ + + /* set 3-wire on */ + val = btcoexist->btc_read_4byte(btcoexist, 0x88c); + val &= 0xffcfffff; + btcoexist->btc_write_4byte(btcoexist, 0x88c, val); + + /* CCK on */ + val = btcoexist->btc_read_4byte(btcoexist, 0x800); + val |= 0x01000000; + btcoexist->btc_write_4byte(btcoexist, 0x800, val); + + /* PSD off */ + val = btcoexist->btc_read_4byte(btcoexist, 0x808); + val &= 0xffbfffff; + btcoexist->btc_write_4byte(btcoexist, 0x808, val); + + /* TRx Mask on */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, + 0xfffff, 0x780); + + /* lock TRx Mask setup */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, + 0x80, 0x0); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, + 0x1, 0x0); + + /* Set RF Rx filter corner */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, + 0xfffff, 0x0); + + /* restore WiFi original channel */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18, + 0x3ff, wifi_original_channel); + + outloop = true; + break; + + } + + } while (!outloop); + + + + psd_scan->is_psd_running = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n"); + BTC_TRACE(trace_buf); + return is_sweep_ok; + +} + +void halbtc8723b1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 bt_tx_time, IN u32 bt_le_channel) +{ + u32 i = 0; + u32 wlpsd_cent_freq = 2484, wlpsd_span = 2, wlpsd_sweep_count = 50; + s32 wlpsd_offset = -4; + u8 bt_le_ch[13] = {3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 33}; + + u8 h2c_parameter[3] = {0}, u8tmpa, u8tmpb; + + u8 state = 0; + boolean outloop = false, bt_resp = false; + u32 freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point, + u32tmp; + struct btc_board_info *board_info = &btcoexist->board_info; + + board_info->btdm_ant_det_finish = false; + memset(psd_scan->ant_det_peak_val, 0, 16 * sizeof(u8)); + memset(psd_scan->ant_det_peak_freq, 0, 16 * sizeof(u8)); + + if (board_info->tfbga_package) /* for TFBGA */ + psd_scan->ant_det_thres_offset = 5; + else + psd_scan->ant_det_thres_offset = 0; + + do { + switch (state) { + case 0: + if (bt_le_channel == 39) + wlpsd_cent_freq = 2484; + else { + for (i = 1; i <= 13; i++) { + if (bt_le_ch[i - 1] == + bt_le_channel) { + wlpsd_cent_freq = 2412 + + (i - 1) * 5; + break; + } + } + + if (i == 14) { + + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Abort!!, Invalid LE channel = %d\n ", + bt_le_channel); + BTC_TRACE(trace_buf); + outloop = true; + break; + } + } + + wlpsd_sweep_count = bt_tx_time * 238 / + 100; /* bt_tx_time/0.42 */ + wlpsd_sweep_count = wlpsd_sweep_count / 5; + + if (wlpsd_sweep_count % 5 != 0) + wlpsd_sweep_count = (wlpsd_sweep_count / + 5 + 1) * 5; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n", + bt_tx_time, bt_le_channel); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), wlpsd_cent_freq=%d, wlpsd_offset = %d, wlpsd_span = %d, wlpsd_sweep_count = %d\n", + wlpsd_cent_freq, + wlpsd_offset, + wlpsd_span, + wlpsd_sweep_count); + BTC_TRACE(trace_buf); + + state = 1; + break; + case 1: /* stop coex DM & set antenna path */ + /* Stop Coex DM */ + + /* + btcoexist->stop_coex_dm = true; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n"); + BTC_TRACE(trace_buf); */ + + /* Set TDMA off, */ + halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, + false, 0); + + /* Set coex table */ + halbtc8723b1ant_coex_table_with_type(btcoexist, + FORCE_EXEC, 0); + + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n"); + BTC_TRACE(trace_buf); + } + + /* Set Antenna path, switch WiFi to un-certain antenna port */ + halbtc8723b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_BT, FORCE_EXEC, false, + false); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n"); + BTC_TRACE(trace_buf); + + /* Set AFH mask on at WiFi channel 2472MHz +/- 10MHz */ + h2c_parameter[0] = 0x1; + h2c_parameter[1] = 0xd; + h2c_parameter[2] = 0x14; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n", + h2c_parameter[1], + h2c_parameter[2]); + BTC_TRACE(trace_buf); + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, + h2c_parameter); + + u32tmp = btcoexist->btc_read_4byte(btcoexist, + 0x948); + u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); + u8tmpb = btcoexist->btc_read_1byte(btcoexist, + 0x778); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x778=0x%x\n", + u32tmp, u8tmpa, u8tmpb); + BTC_TRACE(trace_buf); + + state = 2; + break; + case 2: /* Pre-sweep background psd */ + if (!halbtc8723b1ant_psd_sweep_point(btcoexist, + wlpsd_cent_freq, wlpsd_offset, wlpsd_span, + BT_8723B_1ANT_ANTDET_PSD_POINTS, + BT_8723B_1ANT_ANTDET_PSD_AVGNUM, 3)) { + board_info->btdm_ant_det_finish = false; + board_info->btdm_ant_num_by_ant_det = 1; + psd_scan->ant_det_result = 8; + state = 99; + break; + } + + psd_scan->ant_det_pre_psdscan_peak_val = + psd_scan->psd_max_value; + + if (psd_scan->psd_max_value > + (BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND + + psd_scan->ant_det_thres_offset) * 100) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n", + psd_scan->psd_max_value / 100, + BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND + + psd_scan->ant_det_thres_offset); + BTC_TRACE(trace_buf); + board_info->btdm_ant_det_finish = false; + board_info->btdm_ant_num_by_ant_det = 1; + psd_scan->ant_det_result = 5; + state = 99; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n", + psd_scan->psd_max_value / 100, + BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND + + psd_scan->ant_det_thres_offset); + BTC_TRACE(trace_buf); + state = 3; + } + break; + case 3: + bt_resp = btcoexist->btc_set_bt_ant_detection( + btcoexist, (u8)(bt_tx_time & 0xff), + (u8)(bt_le_channel & 0xff)); + + if (!halbtc8723b1ant_psd_sweep_point(btcoexist, + wlpsd_cent_freq, wlpsd_offset, + wlpsd_span, + BT_8723B_1ANT_ANTDET_PSD_POINTS, + BT_8723B_1ANT_ANTDET_PSD_AVGNUM, + wlpsd_sweep_count)) { + board_info->btdm_ant_det_finish = false; + board_info->btdm_ant_num_by_ant_det = 1; + psd_scan->ant_det_result = 8; + state = 99; + break; + } + + psd_scan->ant_det_psd_scan_peak_val = + psd_scan->psd_max_value; + psd_scan->ant_det_psd_scan_peak_freq = + psd_scan->psd_max_value_point; + state = 4; + break; + case 4: + + if (psd_scan->psd_point == 0) + delta_freq_per_point = 0; + else + delta_freq_per_point = + psd_scan->psd_band_width / + psd_scan->psd_point; + + psd_rep1 = psd_scan->psd_max_value / 100; + psd_rep2 = psd_scan->psd_max_value - psd_rep1 * + 100; + + freq = ((psd_scan->real_cent_freq - 20) * + 1000000 + psd_scan->psd_max_value_point + * delta_freq_per_point); + freq1 = freq / 1000000; + freq2 = freq / 1000 - freq1 * 1000; + + if (freq2 < 100) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.0%d MHz", + freq1, freq2); + BTC_TRACE(trace_buf); + CL_SPRINTF(psd_scan->ant_det_peak_freq, + BT_8723B_1ANT_ANTDET_BUF_LEN, + "%d.0%d", freq1, freq2); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.%d MHz", + freq1, freq2); + BTC_TRACE(trace_buf); + CL_SPRINTF(psd_scan->ant_det_peak_freq, + BT_8723B_1ANT_ANTDET_BUF_LEN, + "%d.%d", freq1, freq2); + } + + if (psd_rep2 < 10) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + ", Value = %d.0%d dB\n", + psd_rep1, psd_rep2); + BTC_TRACE(trace_buf); + CL_SPRINTF(psd_scan->ant_det_peak_val, + BT_8723B_1ANT_ANTDET_BUF_LEN, + "%d.0%d", psd_rep1, psd_rep2); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + ", Value = %d.%d dB\n", + psd_rep1, psd_rep2); + BTC_TRACE(trace_buf); + CL_SPRINTF(psd_scan->ant_det_peak_val, + BT_8723B_1ANT_ANTDET_BUF_LEN, + "%d.%d", psd_rep1, psd_rep2); + } + + psd_scan->ant_det_is_btreply_available = true; + + if (bt_resp == false) { + psd_scan->ant_det_is_btreply_available = + false; + psd_scan->ant_det_result = 0; + board_info->btdm_ant_det_finish = false; + board_info->btdm_ant_num_by_ant_det = 1; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n "); + BTC_TRACE(trace_buf); + } else if (psd_scan->psd_max_value > + (BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION) + * 100) { + psd_scan->ant_det_result = 1; + board_info->btdm_ant_det_finish = true; + board_info->btdm_ant_det_already_init_phydm = + true; + board_info->btdm_ant_num_by_ant_det = 2; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n"); + BTC_TRACE(trace_buf); + } else if (psd_scan->psd_max_value > + (BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION + + psd_scan->ant_det_thres_offset) * 100) { + psd_scan->ant_det_result = 2; + board_info->btdm_ant_det_finish = true; + board_info->btdm_ant_det_already_init_phydm = + true; + board_info->btdm_ant_num_by_ant_det = 2; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n"); + BTC_TRACE(trace_buf); + } else if (psd_scan->psd_max_value > + (BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT) * + 100) { + psd_scan->ant_det_result = 3; + board_info->btdm_ant_det_finish = true; + board_info->btdm_ant_det_already_init_phydm = + true; + board_info->btdm_ant_num_by_ant_det = 1; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n"); + BTC_TRACE(trace_buf); + } else { + psd_scan->ant_det_result = 4; + board_info->btdm_ant_det_finish = false; + board_info->btdm_ant_num_by_ant_det = 1; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n"); + BTC_TRACE(trace_buf); + } + + state = 99; + break; + case 99: /* restore setup */ + + /* Set AFH mask off at WiFi channel 2472MHz +/- 10MHz */ + h2c_parameter[0] = 0x0; + h2c_parameter[1] = 0x0; + h2c_parameter[2] = 0x0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n", + h2c_parameter[1], h2c_parameter[2]); + BTC_TRACE(trace_buf); + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, + h2c_parameter); + + /* Set Antenna Path */ + halbtc8723b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_PTA, FORCE_EXEC, false, + false); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!"); + BTC_TRACE(trace_buf); + + /* Resume Coex DM */ + /* + btcoexist->stop_coex_dm = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); + BTC_TRACE(trace_buf); */ + + /* stimulate coex running */ + /* + halbtc8723b1ant_run_coexist_mechanism( + btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); + BTC_TRACE(trace_buf); + */ + + outloop = true; + break; + } + + } while (!outloop); + + + +} + +void halbtc8723b1ant_psd_antenna_detection_check(IN struct btc_coexist + *btcoexist) +{ + static u32 ant_det_count = 0, ant_det_fail_count = 0; + struct btc_board_info *board_info = &btcoexist->board_info; + + boolean scan, roam; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + + /* psd_scan->ant_det_bt_tx_time = 20; */ + psd_scan->ant_det_bt_tx_time = + BT_8723B_1ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */ + psd_scan->ant_det_bt_le_channel = BT_8723B_1ANT_ANTDET_BTTXCHANNEL; + + ant_det_count++; + + psd_scan->ant_det_try_count = ant_det_count; + + if (scan || roam) { + board_info->btdm_ant_det_finish = false; + psd_scan->ant_det_result = 6; + } else if (coex_sta->bt_disabled) { + board_info->btdm_ant_det_finish = false; + psd_scan->ant_det_result = 11; + } else if (coex_sta->num_of_profile >= 1) { + board_info->btdm_ant_det_finish = false; + psd_scan->ant_det_result = 7; + } else if ( + !psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */ + board_info->btdm_ant_det_finish = false; + psd_scan->ant_det_result = 9; + } else if (coex_sta->c2h_bt_inquiry_page) { + board_info->btdm_ant_det_finish = false; + psd_scan->ant_det_result = 10; + } else { + btcoexist->stop_coex_dm = true; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n"); + BTC_TRACE(trace_buf); + + halbtc8723b1ant_psd_antenna_detection(btcoexist, + psd_scan->ant_det_bt_tx_time, + psd_scan->ant_det_bt_le_channel); + + delay_ms(psd_scan->ant_det_bt_tx_time); + + btcoexist->stop_coex_dm = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); + BTC_TRACE(trace_buf); + + /* stimulate coex running */ + + halbtc8723b1ant_run_coexist_mechanism( + btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); + BTC_TRACE(trace_buf); + } + + board_info->ant_det_result = psd_scan->ant_det_result; + if (!board_info->btdm_ant_det_finish) + ant_det_fail_count++; + + psd_scan->ant_det_fail_count = ant_det_fail_count; + +} + + +/* ************************************************************ + * work around function start with wa_halbtc8723b1ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8723b1ant_ + * ************************************************************ */ +void ex_halbtc8723b1ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x0; + u16 u16tmp = 0x0; + u32 value; + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx Execute 8723b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "Ant Det Finish = %s, Ant Det Number = %d\n", + (board_info->btdm_ant_det_finish ? "Yes" : "No"), + board_info->btdm_ant_num_by_ant_det); + BTC_TRACE(trace_buf); + + + btcoexist->stop_coex_dm = true; + + btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20); + + /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ + u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); + btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); + + /* set GRAN_BT = 1 */ + btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); + /* set WLAN_ACT = 0 */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); + + /* */ + /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + if (btcoexist->chip_interface == BTC_INTF_USB) { + /* fixed at S0 for USB interface */ + btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); + + u8tmp |= 0x1; /* antenna inverse */ + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + + board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; + } else { + /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ + if (board_info->single_ant_path == 0) { + /* set to S1 */ + btcoexist->btc_write_4byte(btcoexist, 0x948, 0x280); + board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; + value = 1; + } else if (board_info->single_ant_path == 1) { + /* set to S0 */ + btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); + u8tmp |= 0x1; /* antenna inverse */ + board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; + value = 0; + } + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, + &value); + + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384, + u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, + u8tmp); + } +} + +void ex_halbtc8723b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{ +} + +void ex_halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8723b1ant_init_hw_config(btcoexist, true, wifi_only); + btcoexist->stop_coex_dm = false; +} + +void ex_halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = false; + + halbtc8723b1ant_init_coex_dm(btcoexist); + + halbtc8723b1ant_query_bt_info(btcoexist); +} + +void ex_halbtc8723b1ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u16 u16tmp[4]; + u32 u32tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0; + u32 bt_coex_ver = 0; + static u8 pop_report_in_10s = 0; + u32 phyver = 0; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + if (btcoexist->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + if (psd_scan->ant_det_try_count == 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", + "Ant PG Num/ Mech/ Pos", + board_info->pg_ant_num, board_info->btdm_ant_num, + board_info->btdm_ant_pos); + CL_PRINTF(cli_buf); + } else { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %d (%d/%d/%d)", + "Ant PG Num/ Mech(Ant_Det)/ Pos", + board_info->pg_ant_num, + board_info->btdm_ant_num_by_ant_det, + board_info->btdm_ant_pos, + psd_scan->ant_det_try_count, + psd_scan->ant_det_fail_count, + psd_scan->ant_det_result); + CL_PRINTF(cli_buf); + + if (board_info->btdm_ant_det_finish) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "Ant Det PSD Value", + psd_scan->ant_det_peak_val); + CL_PRINTF(cli_buf); + } + } + + if (board_info->ant_det_result_five_complete) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d", + "Ant number by AntDet", + board_info->btdm_ant_num_by_ant_det); + CL_PRINTF(cli_buf); + } + + /* btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); */ + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8723b_1ant, glcoex_ver_8723b_1ant, + glcoex_ver_btdesired_8723b_1ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (bt_coex_ver >= glcoex_ver_btdesired_8723b_1ant ? + "Match" : "Mis-Match"))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "Wifi channel informed to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", + "WifibHiPri/ Ccklock/ CckEverLock", + (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + (coex_sta->cck_lock ? "Yes" : "No"), + (coex_sta->cck_ever_lock ? "Yes" : "No")); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "BT Abnormal scan", + (coex_sta->bt_abnormal_scan) ? "Yes" : "No"); + CL_PRINTF(cli_buf); + + pop_report_in_10s++; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", + "BT [status/ rssi/ retryCnt/ popCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") + : ((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi, coex_sta->bt_retry_cnt, + coex_sta->pop_event_cnt); + CL_PRINTF(cli_buf); + + if (pop_report_in_10s >= 5) { + coex_sta->pop_event_cnt = 0; + pop_report_in_10s = 0; + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d / %d / %d / %d / %d / %d", + "SCO/HID/PAN/A2DP/NameReq/WHQL", + bt_link_info->sco_exist, bt_link_info->hid_exist, + bt_link_info->pan_exist, bt_link_info->a2dp_exist, + coex_sta->c2h_bt_remote_name_req, + coex_sta->bt_whck_test); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "BT Role", + (bt_link_info->slave_role) ? "Slave" : "Master"); + CL_PRINTF(cli_buf); + + bt_info_ext = coex_sta->bt_info_ext; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d", + "A2DP Rate/Bitpool", + (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool); + CL_PRINTF(cli_buf); + + for (i = 0; i < BT_INFO_SRC_8723B_1ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8723b_1ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + + if (btcoexist->manual_control) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanisms] (before Manual)============"); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanisms]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "SM[LowPenaltyRA]", + coex_dm->cur_low_penalty_ra); + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + if (board_info->btdm_ant_num_by_ant_det == 2) { + if (coex_dm->cur_ps_tdma_on) + ps_tdma_case = ps_tdma_case + + 100; /* for WiFi RSSI low or BT RSSI low */ + else + ps_tdma_case = + 1; /* always translate to TDMA(off,1) for TDMA-off case */ + } + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", + "PS TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + (coex_dm->cur_ps_tdma_on ? "On" : "Off"), + (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); + + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "Coex Table Type", + coex_sta->coex_table_type); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "IgnWlanAct", + coex_dm->cur_ignore_wlan_act); + CL_PRINTF(cli_buf); + + /* + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Latest error condition(should be 0)", + coex_dm->error_condition); + CL_PRINTF(cli_buf); + */ + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", + "backup ARFR1/ARFR2/RL/AMaxTime", + coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2, + coex_dm->backup_retry_limit, + coex_dm->backup_ampdu_max_time); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); + u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", + "0x430/0x434/0x42a/0x456", + u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x880); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x778/0x6cc/0x880[29:25]", + u8tmp[0], u32tmp[0], (u32tmp[1] & 0x3e000000) >> 25); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x764); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x76e); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "0x948/ 0x67[5] / 0x764 / 0x76e", + u32tmp[0], ((u8tmp[0] & 0x20) >> 5), (u32tmp[1] & 0xffff), + u8tmp[1]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x92c); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x930); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x944); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]", + u32tmp[0] & 0x3, u32tmp[1] & 0xff, u32tmp[2] & 0x3); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x39); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "0x38[11]/0x40/0x4c[24:23]/0x64[0]", + ((u8tmp[0] & 0x8) >> 3), u8tmp[1], + ((u32tmp[0] & 0x01800000) >> 23), u8tmp[2] & 0x1); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x550(bcn ctrl)/0x522", + u32tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0xc50(dig)/0x49c(null-drop)", + u32tmp[0] & 0xff, u8tmp[0]); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_CCK); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11n-agg", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_Err CCK/11g/11n/11n-agg", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x6c0/0x6c4/0x6c8(coexTable)", + u32tmp[0], u32tmp[1], u32tmp[2]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(high-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x774(low-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx); + CL_PRINTF(cli_buf); +#if (BT_AUTO_REPORT_ONLY_8723B_1ANT == 1) + /* halbtc8723b1ant_monitor_bt_ctr(btcoexist); */ +#endif + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +void ex_halbtc8723b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = true; + + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, + FORCE_EXEC, false, true); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + + halbtc8723b1ant_init_hw_config(btcoexist, false, false); + halbtc8723b1ant_init_coex_dm(btcoexist); + halbtc8723b1ant_query_bt_info(btcoexist); + + coex_sta->under_ips = false; + } +} + +void ex_halbtc8723b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = true; + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = false; + } +} + +void ex_halbtc8723b1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false, bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + + u8 u8tmpa, u8tmpb; + u32 u32tmp; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + if (BTC_SCAN_START == type) { + coex_sta->wifi_is_high_pri_task = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify\n"); + BTC_TRACE(trace_buf); + psd_scan->ant_det_is_ant_det_available = true; + halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 8); /* Force antenna setup for no scan result issue */ + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + FORCE_EXEC, false, false); + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); + u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); + u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", + u32tmp, u8tmpa, u8tmpb); + BTC_TRACE(trace_buf); + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + } + + if (coex_sta->bt_disabled) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + halbtc8723b1ant_query_bt_info(btcoexist); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8723b1ant_action_wifi_multi_port(btcoexist); + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8723b1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8723b1ant_action_hs(btcoexist); + return; + } + + if (BTC_SCAN_START == type) { + if (!wifi_connected) /* non-connected scan */ + halbtc8723b1ant_action_wifi_not_connected_scan( + btcoexist); + else /* wifi is connected */ + halbtc8723b1ant_action_wifi_connected_scan(btcoexist); + } else if (BTC_SCAN_FINISH == type) { + if (!wifi_connected) /* non-connected scan */ + halbtc8723b1ant_action_wifi_not_connected(btcoexist); + else + halbtc8723b1ant_action_wifi_connected(btcoexist); + } +} + +void ex_halbtc8723b1ant_set_antenna_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (type == 2) /* two antenna */ + halbtc8723b1ant_mechanism_switch(btcoexist, true); + else /* one antenna */ + halbtc8723b1ant_mechanism_switch(btcoexist, false); +} + +void ex_halbtc8723b1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false, bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + if (BTC_ASSOCIATE_START == type) { + coex_sta->wifi_is_high_pri_task = true; + psd_scan->ant_det_is_ant_det_available = true; + halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 8); /* Force antenna setup for no scan result issue */ + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + FORCE_EXEC, false, false); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify\n"); + BTC_TRACE(trace_buf); + coex_dm->arp_cnt = 0; + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify\n"); + BTC_TRACE(trace_buf); + /* coex_dm->arp_cnt = 0; */ + } + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8723b1ant_action_wifi_multi_port(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8723b1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8723b1ant_action_hs(btcoexist); + return; + } + + if (BTC_ASSOCIATE_START == type) + halbtc8723b1ant_action_wifi_not_connected_asso_auth(btcoexist); + else if (BTC_ASSOCIATE_FINISH == type) { + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + if (!wifi_connected) /* non-connected scan */ + halbtc8723b1ant_action_wifi_not_connected(btcoexist); + else + halbtc8723b1ant_action_wifi_connected(btcoexist); + } +} + +void ex_halbtc8723b1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + boolean wifi_under_b_mode = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + if (BTC_MEDIA_CONNECT == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 8); /* Force antenna setup for no scan result issue */ + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + FORCE_EXEC, false, false); + psd_scan->ant_det_is_ant_det_available = true; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x00); /* CCK Rx */ + } else { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x10); /* CCK Rx */ + } + + coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, + 0x430); + coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, + 0x434); + coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( + btcoexist, 0x42a); + coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( + btcoexist, 0x456); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + coex_dm->arp_cnt = 0; + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + + coex_sta->cck_ever_lock = false; + } + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + /* h2c_parameter[0] = 0x1; */ + h2c_parameter[0] = 0x0; + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); +} + +void ex_halbtc8723b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false, under_4way = false; + u8 agg_buf_size = 5; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + if (BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + BTC_PACKET_ARP == type) { + if (BTC_PACKET_ARP == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ARP notify\n"); + BTC_TRACE(trace_buf); + + coex_dm->arp_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ARP Packet Count = %d\n", + coex_dm->arp_cnt); + BTC_TRACE(trace_buf); + + if ((coex_dm->arp_cnt >= 10) && + (!under_4way)) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */ + coex_sta->wifi_is_high_pri_task = false; + else + coex_sta->wifi_is_high_pri_task = true; + } else { + coex_sta->wifi_is_high_pri_task = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet DHCP or EAPOL notify\n"); + BTC_TRACE(trace_buf); + } + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet [Type = %d] notify\n", type); + BTC_TRACE(trace_buf); + } + + coex_sta->specific_pkt_period_cnt = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8723b1ant_action_wifi_multi_port(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8723b1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8723b1ant_action_hs(btcoexist); + return; + } + + if (BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task))) + halbtc8723b1ant_action_wifi_connected_specific_packet( + btcoexist); +} + +/* Donot remove optimize off flag, otherwise antenna detection would trigger BT collapsed */ +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif +void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 bt_info = 0; + u8 i, rsp_source = 0; + boolean wifi_connected = false; + boolean bt_busy = false; + struct btc_board_info *board_info = &btcoexist->board_info; + + coex_sta->c2h_bt_info_req_sent = false; + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8723B_1ANT_MAX) + rsp_source = BT_INFO_SRC_8723B_1ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + if (i == 1) + bt_info = tmp_buf[i]; + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + /* if 0xff, it means BT is under WHCK test */ + if (bt_info == 0xff) + coex_sta->bt_whck_test = true; + else + coex_sta->bt_whck_test = false; + + if (BT_INFO_SRC_8723B_1ANT_WIFI_FW != rsp_source) { + coex_sta->bt_retry_cnt = /* [3:0] */ + coex_sta->bt_info_c2h[rsp_source][2] & 0xf; + + if (coex_sta->bt_retry_cnt >= 1) + coex_sta->pop_event_cnt++; + + if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) + coex_sta->c2h_bt_remote_name_req = true; + else + coex_sta->c2h_bt_remote_name_req = false; + + coex_sta->bt_rssi = + coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; + /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */ + + coex_sta->bt_info_ext = + coex_sta->bt_info_c2h[rsp_source][4]; + + if (coex_sta->bt_info_c2h[rsp_source][1] == 0x49) { + coex_sta->a2dp_bit_pool = + coex_sta->bt_info_c2h[rsp_source][6]; + } else + coex_sta->a2dp_bit_pool = 0; + + coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] + & 0x40); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, + &coex_sta->bt_tx_rx_mask); + + if (btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT info Notify() return because stop_coex_dm\n"); + BTC_TRACE(trace_buf); + + return; + } + + +#if BT_8723B_1ANT_ANTDET_ENABLE +#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE + if ((board_info->btdm_ant_det_finish) && + (board_info->btdm_ant_num_by_ant_det == 2)) { + if (coex_sta->bt_tx_rx_mask) { + + /* BT TRx mask off */ + btcoexist->btc_set_bt_trx_mask(btcoexist, 0); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT TRx Mask off for BT Info Notify\n"); + BTC_TRACE(trace_buf); +#if 0 + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x1\n"); + BTC_TRACE(trace_buf); + + /* BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 */ + btcoexist->btc_set_bt_reg(btcoexist, + BTC_BT_REG_RF, 0x2c, 0x7c45); + btcoexist->btc_set_bt_reg(btcoexist, + BTC_BT_REG_RF, 0x30, 0x7c45); + + btcoexist->btc_set_bt_reg(btcoexist, + BTC_BT_REG_RF, 0x3c, 0x1); +#endif + } + } else +#endif +#endif + + { + if (!coex_sta->bt_tx_rx_mask) { + + /* BT TRx mask on */ + btcoexist->btc_set_bt_trx_mask(btcoexist, 1); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT TRx Mask on for BT Info Notify\n"); + BTC_TRACE(trace_buf); +#if 0 + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_bt_reg(btcoexist, + BTC_BT_REG_RF, + 0x3c, 0x15); + + /* BT TRx Mask lock 0x2c[0], 0x30[0] = 0 */ + btcoexist->btc_set_bt_reg(btcoexist, + BTC_BT_REG_RF, + 0x2c, 0x7c44); + btcoexist->btc_set_bt_reg(btcoexist, + BTC_BT_REG_RF, + 0x30, 0x7c44); +#endif + } + } + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + if (coex_sta->bt_info_ext & BIT(1)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + if (wifi_connected) + ex_halbtc8723b1ant_media_status_notify( + btcoexist, BTC_MEDIA_CONNECT); + else + ex_halbtc8723b1ant_media_status_notify( + btcoexist, BTC_MEDIA_DISCONNECT); + } + + if (coex_sta->bt_info_ext & BIT(3)) { + if (!btcoexist->manual_control && + !btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8723b1ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, false); + } + } else { + /* BT already NOT ignore Wlan active, do nothing here. */ + } +#if (BT_AUTO_REPORT_ONLY_8723B_1ANT == 0) + if ((coex_sta->bt_info_ext & BIT(4))) { + /* BT auto report already enabled, do nothing */ + } else + halbtc8723b1ant_bt_auto_report(btcoexist, FORCE_EXEC, + true); +#endif + } + + /* check BIT2 first ==> check if bt is under inquiry or page scan */ + if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE) + coex_sta->c2h_bt_inquiry_page = true; + else + coex_sta->c2h_bt_inquiry_page = false; + + coex_sta->num_of_profile = 0; + + /* set link exist status */ + if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + + coex_sta->bt_hi_pri_link_exist = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (bt_info & BT_INFO_8723B_1ANT_B_FTP) { + coex_sta->pan_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->pan_exist = false; + if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) { + coex_sta->a2dp_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->a2dp_exist = false; + if (bt_info & BT_INFO_8723B_1ANT_B_HID) { + coex_sta->hid_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->hid_exist = false; + if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) { + coex_sta->sco_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->sco_exist = false; + + if ((coex_sta->hid_exist == false) && + (coex_sta->c2h_bt_inquiry_page == false) && + (coex_sta->sco_exist == false)) { + if (coex_sta->high_priority_tx + + coex_sta->high_priority_rx >= 160) { + coex_sta->hid_exist = true; + coex_sta->wrong_profile_notification++; + coex_sta->num_of_profile++; + bt_info = bt_info | 0x28; + } + } + + /* Add Hi-Pri Tx/Rx counter to avoid false detection */ + if (((coex_sta->hid_exist) || (coex_sta->sco_exist)) && + (coex_sta->high_priority_tx + + coex_sta->high_priority_rx >= 160) + && (!coex_sta->c2h_bt_inquiry_page)) + coex_sta->bt_hi_pri_link_exist = true; + + if ((bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) && + (coex_sta->num_of_profile == 0)) { + if (coex_sta->low_priority_tx + + coex_sta->low_priority_rx >= 160) { + coex_sta->pan_exist = true; + coex_sta->num_of_profile++; + coex_sta->wrong_profile_notification++; + bt_info = bt_info | 0x88; + } + } + } + + halbtc8723b1ant_update_bt_link_info(btcoexist); + + bt_info = bt_info & + 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ + + if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) + coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + else if (bt_info == + BT_INFO_8723B_1ANT_B_CONNECTION) /* connection exists but no busy */ + coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE; + else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) || + (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY)) + coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_SCO_BUSY; + else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) { + if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) + coex_dm->auto_tdma_adjust = false; + coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_ACL_BUSY; + } else + coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_MAX; + + if ((BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + bt_busy = true; + else + bt_busy = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + halbtc8723b1ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8723b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u32 u32tmp; + u8 u8tmpa, u8tmpb, u8tmpc; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_RF_ON == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned ON!!\n"); + BTC_TRACE(trace_buf); + btcoexist->stop_coex_dm = false; + } else if (BTC_RF_OFF == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned OFF!!\n"); + BTC_TRACE(trace_buf); + + halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, + FORCE_EXEC, false, true); + + halbtc8723b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + btcoexist->stop_coex_dm = true; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); + u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); + u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); + u8tmpc = btcoexist->btc_read_1byte(btcoexist, 0x76e); + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n", + u32tmp, u8tmpa, u8tmpb, u8tmpc); + BTC_TRACE(trace_buf); + + } +} + +void ex_halbtc8723b1ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, + false, true); + + halbtc8723b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + + ex_halbtc8723b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + + btcoexist->stop_coex_dm = true; +} + +void ex_halbtc8723b1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + if (BTC_WIFI_PNP_SLEEP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + + halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, + FORCE_EXEC, false, true); + halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + + /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ + /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ + /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ + coex_sta->under_ips = false; + coex_sta->under_lps = false; + btcoexist->stop_coex_dm = true; + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); + btcoexist->stop_coex_dm = false; + halbtc8723b1ant_init_hw_config(btcoexist, false, false); + halbtc8723b1ant_init_coex_dm(btcoexist); + halbtc8723b1ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8723b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) +{ + + halbtc8723b1ant_init_hw_config(btcoexist, false, false); + /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ + /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); */ + halbtc8723b1ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8723b1ant_periodical(IN struct btc_coexist *btcoexist) +{ + u32 bt_patch_ver; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ==========================Periodical===========================\n"); + BTC_TRACE(trace_buf); + +#if (BT_AUTO_REPORT_ONLY_8723B_1ANT == 0) + halbtc8723b1ant_query_bt_info(btcoexist); +#endif + halbtc8723b1ant_monitor_bt_ctr(btcoexist); + halbtc8723b1ant_monitor_wifi_ctr(btcoexist); + + halbtc8723b1ant_monitor_bt_enable_disable(btcoexist); + + + if (halbtc8723b1ant_is_wifi_status_changed(btcoexist) || + coex_dm->auto_tdma_adjust || + btcoexist->bt_info.bt_enable_disable_change) + halbtc8723b1ant_run_coexist_mechanism(btcoexist); + + if (((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) && (!coex_sta->bt_disabled)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, &coex_sta->bt_coex_supported_version); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + coex_sta->specific_pkt_period_cnt++; + + /* sample to set bt to execute Ant detection */ + /* btcoexist->btc_set_bt_ant_detection(btcoexist, 20, 14); + * + if (psd_scan->is_ant_det_enable) + { + if (psd_scan->psd_gen_count > psd_scan->realseconds) + psd_scan->psd_gen_count = 0; + + halbtc8723b1ant_antenna_detection(btcoexist, psd_scan->realcent_freq, psd_scan->realoffset, psd_scan->realspan, psd_scan->realseconds); + psd_scan->psd_gen_total_count +=2; + psd_scan->psd_gen_count += 2; + } + */ +} + +/* Donot remove optimize off flag, otherwise antenna detection would trigger BT collapsed */ +#ifdef PLATFORM_WINDOWS +#pragma optimize("", off) +#endif +void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ +#if BT_8723B_1ANT_ANTDET_ENABLE + static u32 ant_det_count = 0, ant_det_fail_count = 0; + struct btc_board_info *board_info = &btcoexist->board_info; + /*boolean scan, roam;*/ + + if (seconds == 0) { + psd_scan->ant_det_try_count = 0; + psd_scan->ant_det_fail_count = 0; + ant_det_count = 0; + ant_det_fail_count = 0; + board_info->btdm_ant_det_finish = false; + board_info->btdm_ant_num_by_ant_det = 1; + return; + } + + if (!board_info->btdm_ant_det_finish) { + psd_scan->ant_det_inteval_count = + psd_scan->ant_det_inteval_count + 2; + + if (psd_scan->ant_det_inteval_count >= + BT_8723B_1ANT_ANTDET_RETRY_INTERVAL) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n"); + BTC_TRACE(trace_buf); + halbtc8723b1ant_psd_antenna_detection_check(btcoexist); + + if (board_info->btdm_ant_det_finish) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n"); + BTC_TRACE(trace_buf); + + +#if 1 + if (board_info->btdm_ant_num_by_ant_det == 2) + halbtc8723b1ant_mechanism_switch( + btcoexist, true); + else + halbtc8723b1ant_mechanism_switch( + btcoexist, false); +#endif + + board_info->btdm_ant_det_complete_fail = false; + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n"); + BTC_TRACE(trace_buf); + + board_info->btdm_ant_det_complete_fail = true; + } + psd_scan->ant_det_inteval_count = 0; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n", + psd_scan->ant_det_inteval_count); + BTC_TRACE(trace_buf); + } + + } +#endif + + + /* + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + + psd_scan->ant_det_bt_tx_time = seconds; + psd_scan->ant_det_bt_le_channel = cent_freq; + + if (seconds == 0) + { + psd_scan->ant_det_try_count = 0; + psd_scan->ant_det_fail_count = 0; + ant_det_count = 0; + ant_det_fail_count = 0; + board_info->btdm_ant_det_finish = false; + board_info->btdm_ant_num_by_ant_det = 1; + return; + } + else + { + ant_det_count++; + + psd_scan->ant_det_try_count = ant_det_count; + + if (scan ||roam) + { + board_info->btdm_ant_det_finish = false; + psd_scan->ant_det_result = 6; + } + else if (coex_sta->num_of_profile >= 1) + { + board_info->btdm_ant_det_finish = false; + psd_scan->ant_det_result = 7; + } + else if (!psd_scan->ant_det_is_ant_det_available) + { + board_info->btdm_ant_det_finish = false; + psd_scan->ant_det_result = 9; + } + else if (coex_sta->c2h_bt_inquiry_page) + { + board_info->btdm_ant_det_finish = false; + psd_scan->ant_det_result = 10; + } + else + { + + } + + if (!board_info->btdm_ant_det_finish) + ant_det_fail_count++; + + psd_scan->ant_det_fail_count = ant_det_fail_count; + } + */ +} + + +void ex_halbtc8723b1ant_display_ant_detection(IN struct btc_coexist *btcoexist) +{ +#if BT_8723B_1ANT_ANTDET_ENABLE + struct btc_board_info *board_info = &btcoexist->board_info; + + if (psd_scan->ant_det_try_count != 0) { + halbtc8723b1ant_psd_show_antenna_detect_result(btcoexist); + + if (board_info->btdm_ant_det_finish) + halbtc8723b1ant_psd_showdata(btcoexist); + return; + } +#endif + + /* halbtc8723b1ant_show_psd_data(btcoexist); */ +} + +#endif + +#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ + + + diff --git a/hal/btc/halbtc8723b1ant.h b/hal/btc/halbtc8723b1ant.h new file mode 100644 index 0000000..adb29d4 --- /dev/null +++ b/hal/btc/halbtc8723b1ant.h @@ -0,0 +1,307 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8723B_SUPPORT == 1) +/* ******************************************* + * The following is for 8723B 1ANT BT Co-exist definition + * ******************************************* */ +#define BT_AUTO_REPORT_ONLY_8723B_1ANT 1 + +#define BT_INFO_8723B_1ANT_B_FTP BIT(7) +#define BT_INFO_8723B_1ANT_B_A2DP BIT(6) +#define BT_INFO_8723B_1ANT_B_HID BIT(5) +#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0) + +#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT(0))) ? true : false) + +#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2 + +#define BT_8723B_1ANT_WIFI_NOISY_THRESH 50 /* 30 /max: 255 */ + +/* for Antenna detection */ +#define BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 +#define BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 +#define BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 48 +#define BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT 32 +#define BT_8723B_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ +#define BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY 40000 +#define BT_8723B_1ANT_ANTDET_ENABLE 1 +#define BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 1 +#define BT_8723B_1ANT_ANTDET_BTTXTIME 100 +#define BT_8723B_1ANT_ANTDET_BTTXCHANNEL 39 + +enum bt_info_src_8723b_1ant { + BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8723B_1ANT_MAX +}; + +enum bt_8723b_1ant_bt_status { + BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8723B_1ANT_BT_STATUS_MAX +}; + +enum bt_8723b_1ant_wifi_status { + BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8723B_1ANT_WIFI_STATUS_MAX +}; + +enum bt_8723b_1ant_coex_algo { + BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8723B_1ANT_COEX_ALGO_SCO = 0x1, + BT_8723B_1ANT_COEX_ALGO_HID = 0x2, + BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8723B_1ANT_COEX_ALGO_MAX = 0xb, +}; + +struct coex_dm_8723b_1ant { + /* hw setting */ + u8 pre_ant_pos_type; + u8 cur_ant_pos_type; + /* fw mechanism */ + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean auto_tdma_adjust; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + /* sw mechanism */ + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + + u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ + u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ + u16 backup_retry_limit; + u8 backup_ampdu_max_time; + + /* algorithm related */ + u8 bt_status; + u8 wifi_chnl_info[3]; + + u32 pre_ra_mask; + u32 cur_ra_mask; + u8 pre_arfr_type; + u8 cur_arfr_type; + u8 pre_retry_limit_type; + u8 cur_retry_limit_type; + u8 pre_ampdu_time_type; + u8 cur_ampdu_time_type; + u32 arp_cnt; + + u8 error_condition; +}; + +struct coex_sta_8723b_1ant { + boolean bt_disabled; + boolean bt_enable_disable_change; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + boolean bt_hi_pri_link_exist; + u8 num_of_profile; + boolean bt_abnormal_scan; + + boolean under_lps; + boolean under_ips; + u32 specific_pkt_period_cnt; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + s8 bt_rssi; + boolean bt_tx_rx_mask; + boolean c2h_bt_info_req_sent; + u8 bt_info_c2h[BT_INFO_SRC_8723B_1ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_1ANT_MAX]; + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; + boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ + u8 bt_retry_cnt; + u8 bt_info_ext; + u32 pop_event_cnt; + u8 scan_ap_num; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + + boolean cck_lock; + boolean pre_ccklock; + boolean cck_ever_lock; + u8 coex_table_type; + + boolean force_lps_on; + u32 wrong_profile_notification; + u32 bt_coex_supported_version; + u8 a2dp_bit_pool; + u8 cut_version; +}; + +#define BT_8723B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ +#define BT_8723B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ +#define BT_8723B_1ANT_ANTDET_BUF_LEN 16 + +struct psdscan_sta_8723b_1ant { + + u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ + u32 ant_det_bt_tx_time; + u32 ant_det_pre_psdscan_peak_val; + boolean ant_det_is_ant_det_available; + u32 ant_det_psd_scan_peak_val; + boolean ant_det_is_btreply_available; + u32 ant_det_psd_scan_peak_freq; + + u8 ant_det_result; + u8 ant_det_peak_val[BT_8723B_1ANT_ANTDET_BUF_LEN]; + u8 ant_det_peak_freq[BT_8723B_1ANT_ANTDET_BUF_LEN]; + u32 ant_det_try_count; + u32 ant_det_fail_count; + u32 ant_det_inteval_count; + u32 ant_det_thres_offset; + + u32 real_cent_freq; + s32 real_offset; + u32 real_span; + + u32 psd_band_width; /* unit: Hz */ + u32 psd_point; /* 128/256/512/1024 */ + u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_start_point; + u32 psd_stop_point; + u32 psd_max_value_point; + u32 psd_max_value; + u32 psd_start_base; + u32 psd_avg_num; /* 1/8/16/32 */ + u32 psd_gen_count; + boolean is_psd_running; + boolean is_psd_show_max_only; +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8723b1ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8723b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); +void ex_halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8723b1ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b1ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b1ant_set_antenna_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8723b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b1ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8723b1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8723b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); +void ex_halbtc8723b1ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8723b1ant_display_coex_info(IN struct btc_coexist *btcoexist); +void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); + +void ex_halbtc8723b1ant_display_ant_detection(IN struct btc_coexist *btcoexist); + +#else +#define ex_halbtc8723b1ant_power_on_setting(btcoexist) +#define ex_halbtc8723b1ant_pre_load_firmware(btcoexist) +#define ex_halbtc8723b1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8723b1ant_init_coex_dm(btcoexist) +#define ex_halbtc8723b1ant_ips_notify(btcoexist, type) +#define ex_halbtc8723b1ant_lps_notify(btcoexist, type) +#define ex_halbtc8723b1ant_scan_notify(btcoexist, type) +#define ex_halbtc8723b1ant_set_antenna_notify(btcoexist, type) +#define ex_halbtc8723b1ant_connect_notify(btcoexist, type) +#define ex_halbtc8723b1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8723b1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8723b1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8723b1ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8723b1ant_halt_notify(btcoexist) +#define ex_halbtc8723b1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8723b1ant_coex_dm_reset(btcoexist) +#define ex_halbtc8723b1ant_periodical(btcoexist) +#define ex_halbtc8723b1ant_display_coex_info(btcoexist) +#define ex_halbtc8723b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8723b1ant_display_ant_detection(btcoexist) + +#endif + +#endif + diff --git a/hal/btc/halbtc8723b2ant.c b/hal/btc/halbtc8723b2ant.c new file mode 100644 index 0000000..d74f103 --- /dev/null +++ b/hal/btc/halbtc8723b2ant.c @@ -0,0 +1,4972 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for RTL8723B Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8723B_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8723b_2ant glcoex_dm_8723b_2ant; +static struct coex_dm_8723b_2ant *coex_dm = &glcoex_dm_8723b_2ant; +static struct coex_sta_8723b_2ant glcoex_sta_8723b_2ant; +static struct coex_sta_8723b_2ant *coex_sta = &glcoex_sta_8723b_2ant; + +const char *const glbt_info_src_8723b_2ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u32 glcoex_ver_date_8723b_2ant = 20161007; +u32 glcoex_ver_8723b_2ant = 0x4c; +u32 glcoex_ver_btdesired_8723b_2ant = 0x4c; + +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8723b2ant_ + * ************************************************************ */ +u8 halbtc8723b2ant_bt_rssi_state(u8 *ppre_bt_rssi_state, u8 level_num, + u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = *ppre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return *ppre_bt_rssi_state; + } + + if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + *ppre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + +u8 halbtc8723b2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh, + IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = *pprewifi_rssi_state; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return *pprewifi_rssi_state; + } + + if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + *pprewifi_rssi_state = wifi_rssi_state; + + return wifi_rssi_state; +} + +void halbtc8723b2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = true, bt_disabled = false; + + /* This function check if bt is disabled */ + + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = false; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = false; + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = false; + } else { + bt_disable_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt all counters=0, %d times!!\n", + bt_disable_cnt); + BTC_TRACE(trace_buf); + if (bt_disable_cnt >= 10) + bt_disabled = true; + } + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + + coex_sta->bt_disabled = bt_disabled; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + if (bt_disabled) { + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + } + } +} + + +void halbtc8723b2ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); +} + +void halbtc8723b2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + if ((coex_sta->low_priority_tx > 1050) && + (!coex_sta->c2h_bt_inquiry_page)) + coex_sta->pop_event_cnt++; + + if ((coex_sta->low_priority_rx >= 950) && + (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) && + (!coex_sta->under_ips)) + bt_link_info->slave_role = true; + else + bt_link_info->slave_role = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); + BTC_TRACE(trace_buf); + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); +} + +void halbtc8723b2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ +#if 1 + + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_VHT); + +#endif +} + +void halbtc8723b2ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + coex_sta->c2h_bt_info_req_sent = true; + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); +} + +boolean halbtc8723b2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) +{ + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false; + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + + if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) || + (BTC_RSSI_STATE_LOW == wifi_rssi_state)) + return true; + + } + + return false; +} + +void halbtc8723b2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = true; + bt_link_info->bt_link_exist = true; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = true; + else + bt_link_info->sco_only = false; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = true; + else + bt_link_info->a2dp_only = false; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = true; + else + bt_link_info->pan_only = false; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = true; + else + bt_link_info->hid_only = false; +} + +u8 halbtc8723b2ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + u8 algorithm = BT_8723B_2ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8723B_2ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8723B_2ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8723B_2ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8723B_2ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_HID_A2DP; + } + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8723B_2ANT_COEX_ALGO_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +void halbtc8723b2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, + IN u8 dac_swing_lvl) +{ + u8 h2c_parameter[1] = {0}; + + /* There are several type of dacswing */ + /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ + h2c_parameter[0] = dac_swing_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); +} + +void halbtc8723b2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN u8 dec_bt_pwr_lvl) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = dec_bt_pwr_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); +} + +void halbtc8723b2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 dec_bt_pwr_lvl) +{ + coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; + + if (!force_exec) { + if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) + return; + } + halbtc8723b2ant_set_fw_dec_bt_pwr(btcoexist, + coex_dm->cur_bt_dec_pwr_lvl); + + coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; +} + +void halbtc8723b2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean enable_auto_report) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = 0; + + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); + + btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); +} + +void halbtc8723b2ant_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable_auto_report) +{ + coex_dm->cur_bt_auto_report = enable_auto_report; + + if (!force_exec) { + if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) + return; + } + halbtc8723b2ant_set_bt_auto_report(btcoexist, + coex_dm->cur_bt_auto_report); + + coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; +} + +void halbtc8723b2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 fw_dac_swing_lvl) +{ + coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; + + if (!force_exec) { + if (coex_dm->pre_fw_dac_swing_lvl == + coex_dm->cur_fw_dac_swing_lvl) + return; + } + + halbtc8723b2ant_set_fw_dac_swing_level(btcoexist, + coex_dm->cur_fw_dac_swing_lvl); + + coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; +} + +void halbtc8723b2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist, + IN boolean rx_rf_shrink_on) +{ + if (rx_rf_shrink_on) { + /* Shrink RF Rx LPF corner */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Shrink RF Rx LPF corner!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, + 0xffffc); + } else { + /* Resume RF Rx LPF corner */ + /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ + if (btcoexist->initilized) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Resume RF Rx LPF corner!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, + 0xfffff, coex_dm->bt_rf_0x1e_backup); + } + } +} + +void halbtc8723b2ant_rf_shrink(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rx_rf_shrink_on) +{ + coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; + + if (!force_exec) { + if (coex_dm->pre_rf_rx_lpf_shrink == + coex_dm->cur_rf_rx_lpf_shrink) + return; + } + halbtc8723b2ant_set_sw_rf_rx_lpf_corner(btcoexist, + coex_dm->cur_rf_rx_lpf_shrink); + + coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; +} + +void halbtc8723b2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist + *btcoexist, IN boolean low_penalty_ra) +{ + u8 h2c_parameter[6] = {0}; + + h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ + + if (low_penalty_ra) { + h2c_parameter[1] |= BIT(0); + h2c_parameter[2] = + 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ + h2c_parameter[3] = 0xf4; /* MCS7 or OFDM54 */ + h2c_parameter[4] = 0xf5; /* MCS6 or OFDM48 */ + h2c_parameter[5] = 0xf6; /* MCS5 or OFDM36 */ + } + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); +} + +void halbtc8723b2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) + return; + } + halbtc8723b2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, + coex_dm->cur_low_penalty_ra); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; +} + +void halbtc8723b2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, + IN u32 level) +{ + u8 val = (u8)level; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Write SwDacSwing = 0x%x\n", level); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val); +} + +void halbtc8723b2ant_set_sw_full_time_dac_swing(IN struct btc_coexist + *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) +{ + if (sw_dac_swing_on) + halbtc8723b2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl); + else + halbtc8723b2ant_set_dac_swing_reg(btcoexist, 0x18); +} + + +void halbtc8723b2ant_dac_swing(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) +{ + coex_dm->cur_dac_swing_on = dac_swing_on; + coex_dm->cur_dac_swing_lvl = dac_swing_lvl; + + if (!force_exec) { + if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && + (coex_dm->pre_dac_swing_lvl == + coex_dm->cur_dac_swing_lvl)) + return; + } + delay_ms(30); + halbtc8723b2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, + dac_swing_lvl); + + coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; + coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; +} + +void halbtc8723b2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, + IN boolean adc_back_off) +{ + if (adc_back_off) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB BackOff Level On!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x3); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB BackOff Level Off!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x1); + } +} + +void halbtc8723b2ant_adc_back_off(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean adc_back_off) +{ + coex_dm->cur_adc_back_off = adc_back_off; + + if (!force_exec) { + if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) + return; + } + halbtc8723b2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off); + + coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; +} + +void halbtc8723b2ant_set_agc_table(IN struct btc_coexist *btcoexist, + IN boolean agc_table_en) +{ + u8 rssi_adjust_val = 0; + + /* =================BB AGC Gain Table */ + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table On!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6e1A0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6d1B0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6c1C0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6b1D0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6a1E0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x691F0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x68200001); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table Off!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa4200001); + } + + + /* =================RF Gain */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Agc Table On!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, + 0x38fff); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, + 0x38ffe); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Agc Table Off!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, + 0x380c3); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, + 0x28ce6); + } + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x1); + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Agc Table On!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, + 0x38fff); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, + 0x38ffe); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Agc Table Off!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, + 0x380c3); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, + 0x28ce6); + } + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x0); + + /* set rssi_adjust_val for wifi module. */ + if (agc_table_en) + rssi_adjust_val = 8; + btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, + &rssi_adjust_val); +} + +void halbtc8723b2ant_agc_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean agc_table_en) +{ + coex_dm->cur_agc_table_en = agc_table_en; + + if (!force_exec) { + if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) + return; + } + halbtc8723b2ant_set_agc_table(btcoexist, agc_table_en); + + coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; +} + +void halbtc8723b2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, + IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, + IN boolean limited_dig, IN boolean bt_lna_constrain) +{ + /* + u32 wifi_bw; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if(BTC_WIFI_BW_HT40 != wifi_bw) + { + if (shrink_rx_lpf) + shrink_rx_lpf = false; + } + */ + + /* halbtc8723b2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); */ + halbtc8723b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); +} + +void halbtc8723b2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, + IN boolean agc_table_shift, IN boolean adc_back_off, + IN boolean sw_dac_swing, IN u32 dac_swing_lvl) +{ + /* halbtc8723b2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */ + /* halbtc8723b2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */ + /* halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, dac_swing_lvl); */ +} + +void halbtc8723b2ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8723b2ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8723b2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8723b2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_sta->coex_table_type = type; + + switch (type) { + case 0: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5afa5afa, 0xffffff, 0x3); + break; + case 2: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3); + break; + case 3: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 4: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0xffffffff, 0xffffffff, 0xffffff, 0x3); + break; + case 5: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3); + break; + case 6: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 7: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 8: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 9: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 10: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 11: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 12: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 13: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 14: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); + break; + case 15: + halbtc8723b2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); + break; + default: + break; + } +} + +void halbtc8723b2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 h2c_parameter[1] = {0}; + + if (enable) + h2c_parameter[0] |= BIT(0); /* function enable */ + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + +void halbtc8723b2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8723b2ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8723b2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8723b2ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8723b2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8723b2ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + u8 h2c_parameter[5] = {0x0, 0, 0, 48, 0}; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + /* halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); */ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + /* halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); */ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + +void halbtc8723b2ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = false; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + /* recover to original 32k low power setting */ + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + case BTC_PS_LPS_ON: + halbtc8723b2ant_ps_tdma_check_for_power_save_state( + btcoexist, true); + halbtc8723b2ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + coex_sta->force_lps_on = true; + break; + case BTC_PS_LPS_OFF: + halbtc8723b2ant_ps_tdma_check_for_power_save_state( + btcoexist, false); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + default: + break; + } +} + + +void halbtc8723b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = false; + + if ((coex_sta->a2dp_exist) && (coex_sta->hid_exist)) + byte5 = byte5 | 0x1; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if (ap_enable) { + if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + + halbtc8723b2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + halbtc8723b2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + + } else { + halbtc8723b2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + + h2c_parameter[0] = byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = byte5; + + coex_dm->ps_tdma_para[0] = byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); +} + +void halbtc8723b2ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state1, bt_rssi_state; + s8 wifi_duration_adjust = 0x0; + u8 psTdmaByte4Modify = 0x0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES + - coex_dm->switch_thres_offset, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s turn %s PS TDMA, type=%d\n", + (force_exec ? "force to" : ""), (turn_on ? "ON" : "OFF"), type); + BTC_TRACE(trace_buf); + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + if (!(BTC_RSSI_HIGH(wifi_rssi_state1) && + BTC_RSSI_HIGH(bt_rssi_state)) && turn_on) + /* if (halbtc8723b2ant_CoexSwitchThresCheck(btcoexist) && turn_on) */ + { + type = type + 100; /* for WiFi RSSI low or BT RSSI low */ + coex_dm->is_switch_to_1dot5_ant = true; + } else + coex_dm->is_switch_to_1dot5_ant = false; + + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) + return; + } + + if (coex_sta->scan_ap_num <= 5) { + if (coex_sta->a2dp_bit_pool >= 45) + wifi_duration_adjust = -15; + else if (coex_sta->a2dp_bit_pool >= 35) + wifi_duration_adjust = -10; + else + wifi_duration_adjust = 5; + } else if (coex_sta->scan_ap_num <= 20) { + if (coex_sta->a2dp_bit_pool >= 45) + wifi_duration_adjust = -15; + else if (coex_sta->a2dp_bit_pool >= 35) + wifi_duration_adjust = -10; + else + wifi_duration_adjust = 0; + } else if (coex_sta->scan_ap_num <= 40) { + if (coex_sta->a2dp_bit_pool >= 45) + wifi_duration_adjust = -15; + else if (coex_sta->a2dp_bit_pool >= 35) + wifi_duration_adjust = -10; + else + wifi_duration_adjust = -5; + } else { + if (coex_sta->a2dp_bit_pool >= 45) + wifi_duration_adjust = -15; + else if (coex_sta->a2dp_bit_pool >= 35) + wifi_duration_adjust = -10; + else + wifi_duration_adjust = -10; + } + + if ((bt_link_info->slave_role == true) && (bt_link_info->a2dp_exist)) + psTdmaByte4Modify = + 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ + + + if (turn_on) { + switch (type) { + case 1: + default: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c + wifi_duration_adjust, 0x03, 0xf1, + 0x90 | psTdmaByte4Modify); + break; + case 2: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x2d + wifi_duration_adjust, 0x03, 0xf1, + 0x90 | psTdmaByte4Modify); + break; + case 3: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1c, 0x3, 0xf1, 0x90 | + psTdmaByte4Modify); + break; + case 4: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x10, 0x03, 0xf1, 0x90 | + psTdmaByte4Modify); + break; + case 5: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c + wifi_duration_adjust, 0x3, 0x70, + 0x90 | psTdmaByte4Modify); + break; + case 6: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x2d + wifi_duration_adjust, 0x3, 0x70, + 0x90 | psTdmaByte4Modify); + break; + case 7: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1c, 0x3, 0x70, 0x90 | + psTdmaByte4Modify); + break; + case 8: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xa3, + 0x10, 0x3, 0x70, 0x90 | + psTdmaByte4Modify); + break; + case 9: + /* + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c + wifi_duration_adjust, 0x03, 0xf1, + 0x90 | psTdmaByte4Modify); + */ + /* Bryant Modify for BT no-profile busy case */ + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c + wifi_duration_adjust, 0x03, 0xf1, + 0x91); + + break; + case 10: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x2d + wifi_duration_adjust, 0x03, 0xf1, + 0x90 | psTdmaByte4Modify); + break; + case 11: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1c, 0x3, 0xf1, 0x90 | + psTdmaByte4Modify); + break; + case 12: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x10, 0x3, 0xf1, 0x90 | + psTdmaByte4Modify); + break; + case 13: + /* + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c + wifi_duration_adjust, 0x3, 0x70, + 0x90 | psTdmaByte4Modify); + */ + /* Bryant Modify for BT no-profile busy case */ + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c + wifi_duration_adjust, 0x3, 0x70, + 0x91); + break; + case 14: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x2d + wifi_duration_adjust, 0x3, 0x70, + 0x90 | psTdmaByte4Modify); + break; + case 15: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1c, 0x3, 0x70, 0x90 | + psTdmaByte4Modify); + break; + case 16: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x10, 0x3, 0x70, 0x90 | + psTdmaByte4Modify); + break; + case 17: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xa3, + 0x2f, 0x2f, 0x60, 0x90); + break; + case 18: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x5, 0x5, 0xe1, 0x90); + break; + case 19: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x25, 0xe1, 0x90); + break; + case 20: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x25, 0x60, 0x90); + break; + case 21: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x15, 0x03, 0x70, 0x90); + break; + case 22: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x35, 0x03, 0xf1, 0x90); + break; + case 23: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x35, 0x03, 0x71, 0x10); + break; + + case 25: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x30, 0x03, 0x71, 0x10); + break; + + case 33: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1c, 0x3, 0xf1, 0x91); + + break; + case 71: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c + wifi_duration_adjust, 0x03, 0xf1, + 0x90); + break; + case 101: + case 105: + case 113: + case 171: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x3a + wifi_duration_adjust, 0x03, 0x70, + 0x50 | psTdmaByte4Modify); + break; + case 102: + case 106: + case 110: + case 114: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x2d + wifi_duration_adjust, 0x03, 0x70, + 0x50 | psTdmaByte4Modify); + break; + case 103: + case 107: + case 111: + case 115: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x1c, 0x03, 0x70, 0x50 | + psTdmaByte4Modify); + break; + case 104: + case 108: + case 112: + case 116: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x10, 0x03, 0x70, 0x50 | + psTdmaByte4Modify); + break; + case 109: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c, 0x03, 0xf1, 0x90 | + psTdmaByte4Modify); + break; + /* case 113: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c, 0x03, 0x70, 0x90 | + psTdmaByte4Modify); + break; */ + case 121: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x15, 0x03, 0x70, 0x90 | + psTdmaByte4Modify); + break; + case 122: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x35, 0x03, 0x71, 0x11); + break; + case 123: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x35, 0x03, 0x71, 0x10); + break; + case 125: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x30, 0x03, 0x70, 0x51); + break; + + case 133: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x1c, 0x3, 0x70, 0x51); + + break; + } + } else { + /* disable PS tdma */ + switch (type) { + case 0: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x40, 0x0); + break; + case 1: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x48, 0x0); + break; + default: + halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x40, 0x0); + break; + } + } + + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; +} + + +void halbtc8723b2ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u32 fw_ver = 0, u32tmp = 0, cnt_bt_cal_chk = 0; + boolean pg_ext_switch = false; + boolean use_ext_switch = false; + u8 h2c_parameter[2] = {0}; + u32 u32tmp_1[4]; + boolean is_fw_ready; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_EXT_SWITCH, &pg_ext_switch); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, + &fw_ver); /* [31:16]=fw ver, [15:0]=fw sub ver */ + + if ((fw_ver > 0 && fw_ver < 0xc0000) || pg_ext_switch) + use_ext_switch = true; + + if (init_hwcfg) { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x39, 0x8, 0x1); + btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x944, 0x3, 0x3); + btcoexist->btc_write_1byte(btcoexist, 0x930, 0x77); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1); + + if (fw_ver >= 0x180000) { + /* Use H2C to set GNT_BT to High to avoid A2DP click */ + h2c_parameter[0] = 1; + btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, + h2c_parameter); + + cnt_bt_cal_chk = 0; + while (1) { + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready); + if (is_fw_ready == false) + break; + + if (btcoexist->btc_read_1byte(btcoexist, + 0x765) == 0x18) + break; + + cnt_bt_cal_chk++; + if (cnt_bt_cal_chk > 20) + break; + } + } else + btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); + u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); + if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) + btcoexist->btc_write_4byte(btcoexist, 0x948, + u32tmp_1[0]); + else + btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, + 0x0); /* WiFi TRx Mask off */ + /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */ + /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x01); */ /*BT TRx Mask off */ + + if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { + /* tell firmware "no antenna inverse" */ + h2c_parameter[0] = 0; + } else { + /* tell firmware "antenna inverse" */ + h2c_parameter[0] = 1; + } + + if (use_ext_switch) { + /* ext switch type */ + h2c_parameter[1] = 1; + } else { + /* int switch type */ + h2c_parameter[1] = 0; + } + btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, h2c_parameter); + } else { + if (fw_ver >= 0x180000) { + /* Use H2C to set GNT_BT to "Control by PTA"*/ + h2c_parameter[0] = 0; + btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, + h2c_parameter); + + cnt_bt_cal_chk = 0; + while (1) { + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready); + if (is_fw_ready == false) + break; + + if (btcoexist->btc_read_1byte(btcoexist, + 0x765) == 0x0) + break; + + cnt_bt_cal_chk++; + if (cnt_bt_cal_chk > 20) + break; + } + } else + btcoexist->btc_write_1byte(btcoexist, 0x765, 0x0); + } + + /* ext switch setting */ + if (use_ext_switch) { + if (init_hwcfg) { + /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp &= ~BIT(23); + u32tmp |= BIT(24); + btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); + } + u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); + if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) + btcoexist->btc_write_4byte(btcoexist, 0x948, + u32tmp_1[0]); + else + btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); + + switch (ant_pos_type) { + case BTC_ANT_WIFI_AT_MAIN: + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0x92c, 0x3, + 0x1); /* ext switch main at wifi */ + break; + case BTC_ANT_WIFI_AT_AUX: + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0x92c, 0x3, + 0x2); /* ext switch aux at wifi */ + break; + } + } else { /* internal switch */ + if (init_hwcfg) { + /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp |= BIT(23); + u32tmp &= ~BIT(24); + btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); + } + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, + 0x0); /* fixed external switch S1->Main, S0->Aux */ + switch (ant_pos_type) { + case BTC_ANT_WIFI_AT_MAIN: + u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, + 0x948); + if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) + btcoexist->btc_write_4byte(btcoexist, 0x948, + u32tmp_1[0]); + else + btcoexist->btc_write_4byte(btcoexist, 0x948, + 0x0); + break; + case BTC_ANT_WIFI_AT_AUX: + u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, + 0x948); + if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) + btcoexist->btc_write_4byte(btcoexist, 0x948, + u32tmp_1[0]); + else + btcoexist->btc_write_4byte(btcoexist, 0x948, + 0x280); + break; + } + } +} +#if 0 +boolean halbtc8723b2ant_CoexSwitchThresCheck(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state1, bt_rssi_state; + u32 vendor; + u8 offset = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor); + + /* if (vendor == BTC_VENDOR_LENOVO) */ + /* offset = 20; */ + + wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES + - coex_dm->switch_thres_offset, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + + if (BTC_RSSI_LOW(wifi_rssi_state1) || BTC_RSSI_LOW(bt_rssi_state)) + return true; + + return false; +} +#endif + + +void halbtc8723b2ant_coex_all_off(IN struct btc_coexist *btcoexist) +{ + /* fw all off */ + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* sw all off */ + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + + /* hw all off */ + /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + /* force to reset coex mechanism */ + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); + halbtc8723b2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0); + + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + + coex_sta->pop_event_cnt = 0; + +} + +void halbtc8723b2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, + prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + boolean wifi_connected = false; + boolean low_pwr_disable = true; + boolean scan = false, link = false, roam = false; + boolean wifi_busy = false; + + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, 15, 0); + wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state1, 2, + BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + + if (coex_sta->bt_abnormal_scan) { + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 23); + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + } else if (scan || link || roam) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi link process + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 7); + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); + } else if (wifi_connected) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 7); + + if (wifi_busy) + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 3); + else + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi no-link + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + } + + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + /* + coex_dm->need_recover0x948 = true; + coex_dm->backup0x948 = btcoexist->btc_read_4byte(btcoexist, 0x948); + + halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_AUX, false, false); + */ +} + + +void halbtc8723b2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist) +{ + u32 u32tmp; + u8 u8tmpa, u8tmpb; + + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 15); + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); + + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + + + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); + u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); + u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n", + u32tmp, u8tmpa, u8tmpb); + BTC_TRACE(trace_buf); +} + +boolean halbtc8723b2ant_action_wifi_idle_process(IN struct btc_coexist + *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, + prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u8 ap_num = 0; + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, 15, 0); + /* wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES-coex_dm->switch_thres_offset-coex_dm->switch_thres_offset, 0); */ + wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state1, 2, + BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset - coex_dm->switch_thres_offset, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset - coex_dm->switch_thres_offset, 0); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); + + /* define the office environment */ + if (BTC_RSSI_HIGH(wifi_rssi_state1) && + (coex_sta->hid_exist == true) && + (coex_sta->a2dp_exist == true)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi idle process for BT HID+A2DP exist!!\n"); + BTC_TRACE(trace_buf); + + halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6); + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* sw all off */ + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, + false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + + return true; + } + + halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x18); + return false; +} + + + +boolean halbtc8723b2ant_is_common_action(IN struct btc_coexist *btcoexist) +{ + boolean common = false, wifi_connected = false, wifi_busy = false; + boolean bt_hs_on = false, low_pwr_disable = false; + boolean asus_8723b = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_connected) { + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x8); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non-connected idle!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, + 0x0); + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, + false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + + common = true; + } else { + if (BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, + false, false, 0x8); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, + 0xfffff, 0x0); + halbtc8723b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, + 0xb); + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, + false, + false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + + common = true; + } else if (BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status) { + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + + if (bt_hs_on) + return false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, + false, false, 0x8); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, + 0xfffff, 0x0); + halbtc8723b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, + 0xb); + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + + common = true; + } else { + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + + if (wifi_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); + BTC_TRACE(trace_buf); + /* btcoexist->btc_get(btcoexist, + BTC_GET_BL_IS_ASUS_8723B, &asus_8723b); + if (!asus_8723b) + common = false; + else + common = halbtc8723b2ant_action_wifi_idle_process( + btcoexist); */ + common = false; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + /* common = false; */ + common = halbtc8723b2ant_action_wifi_idle_process( + btcoexist); + } + } + } + + return common; +} +void halbtc8723b2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, + IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) +{ + static s32 up, dn, m, n, wait_count; + s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ + u8 retry_count = 0; + + if (!coex_dm->auto_tdma_adjust) { + coex_dm->auto_tdma_adjust = true; + { + if (sco_hid) { + if (tx_pause) { + if (max_interval == 1) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 13); + coex_dm->ps_tdma_du_adj_type = + 13; + } else if (max_interval == 2) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (max_interval == 3) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } + } else { + if (max_interval == 1) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = + 9; + } else if (max_interval == 2) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (max_interval == 3) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } + } + } else { + if (tx_pause) { + if (max_interval == 1) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 5); + coex_dm->ps_tdma_du_adj_type = + 5; + } else if (max_interval == 2) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (max_interval == 3) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } + } else { + if (max_interval == 1) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = + 1; + } else if (max_interval == 2) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (max_interval == 3) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } + } + } + } + /* ============ */ + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } else { + /* acquire the BT TRx retry count from BT_Info byte2 */ + retry_count = coex_sta->bt_retry_cnt; + + if ((coex_sta->low_priority_tx) > 1050 || + (coex_sta->low_priority_rx) > 1250) + retry_count++; + + result = 0; + wait_count++; + + if (retry_count == + 0) { /* no retry in the last 2-second duration */ + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ + wait_count = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + } + } else if (retry_count <= + 3) { /* <=3 retry in the last 2-second duration */ + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) {/* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ + if (wait_count <= 2) + m++; /* to avoid loop between the two levels */ + else + m = 1; + + if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ + if (wait_count == 1) + m++; /* to avoid loop between the two levels */ + else + m = 1; + + if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + + if (max_interval == 1) { + if (tx_pause) { + if (coex_dm->cur_ps_tdma == 71) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 5); + coex_dm->ps_tdma_du_adj_type = 5; + } else if (coex_dm->cur_ps_tdma == 1) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 5); + coex_dm->ps_tdma_du_adj_type = 5; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 6); + coex_dm->ps_tdma_du_adj_type = 6; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 4) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 8); + coex_dm->ps_tdma_du_adj_type = 8; + } + if (coex_dm->cur_ps_tdma == 9) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 13); + coex_dm->ps_tdma_du_adj_type = 13; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + coex_dm->ps_tdma_du_adj_type = 14; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 16); + coex_dm->ps_tdma_du_adj_type = 16; + } + + if (result == -1) { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 8); + coex_dm->ps_tdma_du_adj_type = + 8; + } else if (coex_dm->cur_ps_tdma == 13) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 16); + coex_dm->ps_tdma_du_adj_type = + 16; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 8) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 5); + coex_dm->ps_tdma_du_adj_type = + 5; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 13); + coex_dm->ps_tdma_du_adj_type = + 13; + } + } + } else { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 71); + coex_dm->ps_tdma_du_adj_type = 71; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 8) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 4); + coex_dm->ps_tdma_du_adj_type = 4; + } + if (coex_dm->cur_ps_tdma == 13) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 10); + coex_dm->ps_tdma_du_adj_type = 10; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 12); + coex_dm->ps_tdma_du_adj_type = 12; + } + + if (result == -1) { + if (coex_dm->cur_ps_tdma == 71) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = + 1; + } else if (coex_dm->cur_ps_tdma == 1) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 4); + coex_dm->ps_tdma_du_adj_type = + 4; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 12); + coex_dm->ps_tdma_du_adj_type = + 12; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 4) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = + 1; + } else if (coex_dm->cur_ps_tdma == 1) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 71); + coex_dm->ps_tdma_du_adj_type = + 71; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = + 9; + } + } + } + } else if (max_interval == 2) { + if (tx_pause) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 6); + coex_dm->ps_tdma_du_adj_type = 6; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 6); + coex_dm->ps_tdma_du_adj_type = 6; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 4) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 8); + coex_dm->ps_tdma_du_adj_type = 8; + } + if (coex_dm->cur_ps_tdma == 9) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + coex_dm->ps_tdma_du_adj_type = 14; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + coex_dm->ps_tdma_du_adj_type = 14; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 16); + coex_dm->ps_tdma_du_adj_type = 16; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 8); + coex_dm->ps_tdma_du_adj_type = + 8; + } else if (coex_dm->cur_ps_tdma == 13) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 16); + coex_dm->ps_tdma_du_adj_type = + 16; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 8) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } + } + } else { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 8) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 4); + coex_dm->ps_tdma_du_adj_type = 4; + } + if (coex_dm->cur_ps_tdma == 13) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 10); + coex_dm->ps_tdma_du_adj_type = 10; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 10); + coex_dm->ps_tdma_du_adj_type = 10; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 12); + coex_dm->ps_tdma_du_adj_type = 12; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 4); + coex_dm->ps_tdma_du_adj_type = + 4; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 12); + coex_dm->ps_tdma_du_adj_type = + 12; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 4) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } + } + } + } else if (max_interval == 3) { + if (tx_pause) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 4) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 8); + coex_dm->ps_tdma_du_adj_type = 8; + } + if (coex_dm->cur_ps_tdma == 9) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 16); + coex_dm->ps_tdma_du_adj_type = 16; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 8); + coex_dm->ps_tdma_du_adj_type = + 8; + } else if (coex_dm->cur_ps_tdma == 13) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 16); + coex_dm->ps_tdma_du_adj_type = + 16; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 8) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } + } + } else { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 8) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 4); + coex_dm->ps_tdma_du_adj_type = 4; + } + if (coex_dm->cur_ps_tdma == 13) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8723b2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 12); + coex_dm->ps_tdma_du_adj_type = 12; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 4); + coex_dm->ps_tdma_du_adj_type = + 4; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 12); + coex_dm->ps_tdma_du_adj_type = + 12; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 4) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8723b2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } + } + } + } + } + + /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ + /* then we have to adjust it back to the previous record one. */ + if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { + boolean scan = false, link = false, roam = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", + coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + if (!scan && !link && !roam) + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + coex_dm->ps_tdma_du_adj_type); + else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); + BTC_TRACE(trace_buf); + } + } +} + +/* SCO only or SCO+PAN(HS) */ +void halbtc8723b2ant_action_sco(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + u32 wifi_bw; + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, 15, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for SCO quality at 11b/g mode */ + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + else /* for SCO quality & wifi performance balance at 11n mode */ + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); /* for voice quality */ + + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + true, 0x4); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + true, 0x4); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + true, 0x4); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + true, 0x4); + } + } +} + + +void halbtc8723b2ant_action_hid(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + u32 wifi_bw; + + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, 15, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */ + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + else /* for HID quality & wifi performance balance at 11n mode */ + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9); + + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); + else + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); + + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ +void halbtc8723b2ant_action_a2dp(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, + prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + u8 ap_num = 0; + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, 15, 0); + wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state1, 2, + BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); + + /* define the office environment */ + if ((ap_num >= 10) && BTC_RSSI_HIGH(wifi_rssi_state1) && + BTC_RSSI_HIGH(bt_rssi_state)) { + /* dbg_print(" AP#>10(%d)\n", ap_num); */ + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, + 0x0); + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x8); + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + + /* sw mechanism */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + true, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + true, 0x18); + } + return; + + } + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + + } else { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 13); + } + + + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) + halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, false, + 1); + else + halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, true, 1); + + /* sw mechanism */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8723b2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, + prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, 15, 0); + wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state1, 2, + BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + + } else { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 13); + } + + halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, true, 2); + + /* sw mechanism */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8723b2ant_action_pan_edr(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, + prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, 15, 0); + wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state1, 2, + BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 10); + } else { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 13); + } + + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); + else + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + + /* sw mechanism */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + + +/* PAN(HS) only */ +void halbtc8723b2ant_action_pan_hs(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, + prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, 15, 0); + wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state1, 2, + BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +/* PAN(EDR)+A2DP */ +void halbtc8723b2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, + prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u8 ap_num = 0; + u32 wifi_bw; + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, 15, 0); + wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state1, 2, + BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &ap_num); + + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 12); + + if (ap_num < 10) + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, + false, 1); + else + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, + false, 3); + + } else { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 13); + if (ap_num < 10) + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, + true, 1); + else + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, + true, 3); + } + + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8723b2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, + prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, 15, 0); + wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state1, 2, + BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + } else { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 14); + } + + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + if (BTC_WIFI_BW_HT40 == wifi_bw) { + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, + 3); + /* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, + 0xfffff, 0x780); + } else { + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, + 6); + /* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, + 0xfffff, 0x0); + } + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 2); + } else { + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + /* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, + 0x0); + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 2); + } + + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +/* HID+A2DP+PAN(EDR) */ +void halbtc8723b2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, + prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, 15, 0); + wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state1, 2, + BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + } else { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 14); + } + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + if (BTC_WIFI_BW_HT40 == wifi_bw) + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, + true, 3); + else + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, + false, 3); + } else + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 3); + + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8723b2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, + prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + u8 ap_num = 0; + + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 35); + + + wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, 15, 0); + /* bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0); */ + wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state1, 2, + BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 0); + bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 3, + BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - + coex_dm->switch_thres_offset, 37); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &ap_num); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x5); + + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_LEGACY == wifi_bw) { + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else if (BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + } else { + /* only 802.11N mode we have to dec bt power to 4 degree */ + if (BTC_RSSI_HIGH(bt_rssi_state)) { + /* need to check ap Number of Not */ + if (ap_num < 10) + halbtc8723b2ant_dec_bt_pwr(btcoexist, + NORMAL_EXEC, 4); + else + halbtc8723b2ant_dec_bt_pwr(btcoexist, + NORMAL_EXEC, 2); + } else if (BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + } + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + } else { + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 14); + } + + if (BTC_RSSI_HIGH(bt_rssi_state)) { + if (ap_num < 10) + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, + false, 2); + + else + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, + false, 3); + } else { + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 18); + btcoexist->btc_write_1byte(btcoexist, 0x456, 0x38); + btcoexist->btc_write_2byte(btcoexist, 0x42a, 0x0808); + btcoexist->btc_write_4byte(btcoexist, 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, 0x434, 0x01010000); + + if (ap_num < 10) + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, + true, 2); + + else + halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, + true, 3); + } + + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8723b2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) +{ + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* sw all off */ + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8723b2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* sw all off */ + halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + + /* hw all off */ + /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ + halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); +} + +void halbtc8723b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + u8 algorithm = 0; + u32 num_of_wifi_link = 0; + u32 wifi_link_status = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean miracast_plus_bt = false; + boolean scan = false, link = false, roam = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->bt_whck_test) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under WHCK TEST!!!\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_bt_whck_test(btcoexist); + return; + } + + algorithm = halbtc8723b2ant_action_algorithm(btcoexist); + if (coex_sta->c2h_bt_inquiry_page && + (BT_8723B_2ANT_COEX_ALGO_PANHS != algorithm)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_bt_inquiry(btcoexist); + return; + } + + /* + if(coex_dm->need_recover0x948) + { + coex_dm->need_recover0x948 = false; + btcoexist->btc_write_4byte(btcoexist, 0x948, coex_dm->backup0x948); + } + */ + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + if (scan || link || roam) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under Link Process !!\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_wifi_link_process(btcoexist); + return; + } + + /* for P2P */ + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", + num_of_wifi_link, wifi_link_status); + BTC_TRACE(trace_buf); + + if (bt_link_info->bt_link_exist) + miracast_plus_bt = true; + else + miracast_plus_bt = false; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + halbtc8723b2ant_action_wifi_multi_port(btcoexist); + + return; + } + + miracast_plus_bt = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + coex_dm->cur_algorithm = algorithm; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", + coex_dm->cur_algorithm); + BTC_TRACE(trace_buf); + + if (halbtc8723b2ant_is_common_action(btcoexist)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant common.\n"); + BTC_TRACE(trace_buf); + coex_dm->auto_tdma_adjust = false; + } else { + if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", + coex_dm->pre_algorithm, coex_dm->cur_algorithm); + BTC_TRACE(trace_buf); + coex_dm->auto_tdma_adjust = false; + } + switch (coex_dm->cur_algorithm) { + case BT_8723B_2ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_sco(btcoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID.\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_hid(btcoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_a2dp(btcoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_a2dp_pan_hs(btcoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_pan_edr(btcoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_pan_hs(btcoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_pan_edr_a2dp(btcoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_pan_edr_hid(btcoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_hid_a2dp_pan_edr( + btcoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_action_hid_a2dp(btcoexist); + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_coex_all_off(btcoexist); + break; + } + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + } +} + +void halbtc8723b2ant_wifi_off_hw_cfg(IN struct btc_coexist *btcoexist) +{ + boolean is_in_mp_mode = false; + u8 h2c_parameter[2] = {0}; + u32 fw_ver = 0; + + /* set wlan_act to low */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, + 0x780); /* WiFi goto standby while GNT_BT 0-->1 */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + if (fw_ver >= 0x180000) { + /* Use H2C to set GNT_BT to HIGH */ + h2c_parameter[0] = 1; + btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, h2c_parameter); + } else + btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE, + &is_in_mp_mode); + if (!is_in_mp_mode) + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x0); /* BT select s0/s1 is controlled by BT */ + else + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x1); /* BT select s0/s1 is controlled by WiFi */ +} + +void halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean back_up) +{ + u8 u8tmp = 0; + u32 vendor; + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 2Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor); + if (vendor == BTC_VENDOR_LENOVO) + coex_dm->switch_thres_offset = 0; + else if (vendor == BTC_VENDOR_ASUS) + coex_dm->switch_thres_offset = 0; + else + coex_dm->switch_thres_offset = 20; + + /* 0xf0[15:12] --> Chip Cut information */ + coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, + 0xf1) & 0xf0) >> 4; + + /* backup rf 0x1e value */ + coex_dm->bt_rf_0x1e_backup = + btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff); + + /* 0x790[5:0]=0x5 */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); + u8tmp &= 0xc0; + u8tmp |= 0x5; + btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); + + /* Antenna config */ + halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true, + false); + coex_sta->dis_ver_info_cnt = 0; + + /* PTA parameter */ + halbtc8723b2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + /* Enable counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, + 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); + + /* Give bt_coex_supported_version the default value */ + coex_sta->bt_coex_supported_version = 0; + +} + +/* ************************************************************ + * work around function start with wa_halbtc8723b2ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8723b2ant_ + * ************************************************************ */ +void ex_halbtc8723b2ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u16 u16tmp = 0x0; + u32 value = 0; + u32 u32tmp_1[4]; + + btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20); + + /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ + u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); + btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); + + btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); + + if (btcoexist->chip_interface == BTC_INTF_USB) { + /* fixed at S0 for USB interface */ + board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; + } else { + /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ + if (board_info->single_ant_path == 0) { + /* set to S1 */ + board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; + } else if (board_info->single_ant_path == 1) { + /* set to S0 */ + board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; + } + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, + &value); + } +} + +void ex_halbtc8723b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ + + /* */ + /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + if (btcoexist->chip_interface == BTC_INTF_USB) { + /* fixed at S0 for USB interface */ + u8tmp |= 0x1; /* antenna inverse */ + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + } else { + if (board_info->single_ant_path == 1) { + /* set to S0 */ + u8tmp |= 0x1; /* antenna inverse */ + } + + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384, + u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, + u8tmp); + } +} + +void ex_halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8723b2ant_init_hw_config(btcoexist, true); +} + +void ex_halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + halbtc8723b2ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8723b2ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u32 u32tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0; + u32 bt_coex_ver = 0; + static u8 pop_report_in_10s = 0; + u32 phyver = 0; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", + "Ant PG number/ Ant mechanism:", + board_info->pg_ant_num, board_info->btdm_ant_num); + CL_PRINTF(cli_buf); + + /* btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); */ + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8723b_2ant, glcoex_ver_8723b_2ant, + glcoex_ver_btdesired_8723b_2ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (bt_coex_ver >= glcoex_ver_btdesired_8723b_2ant ? + "Match" : "Mis-Match"))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "Wifi channel informed to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "BT Abnormal scan", + (coex_sta->bt_abnormal_scan) ? "Yes" : "No"); + CL_PRINTF(cli_buf); + + pop_report_in_10s++; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", + "BT [status/ rssi/ retryCnt/ popCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") + : ((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, + coex_sta->pop_event_cnt); + CL_PRINTF(cli_buf); + + if (pop_report_in_10s >= 5) { + coex_sta->pop_event_cnt = 0; + pop_report_in_10s = 0; + } + + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d / %d / %d / %d / %d / %d", + "SCO/HID/PAN/A2DP/NameReq/WHQL", + bt_link_info->sco_exist, bt_link_info->hid_exist, + bt_link_info->pan_exist, bt_link_info->a2dp_exist, + coex_sta->c2h_bt_remote_name_req, + coex_sta->bt_whck_test); + CL_PRINTF(cli_buf); + + { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "BT Role", + (bt_link_info->slave_role) ? "Slave" : "Master"); + CL_PRINTF(cli_buf); + } + + bt_info_ext = coex_sta->bt_info_ext; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", + "A2DP Rate/Bitpool", + (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool); + CL_PRINTF(cli_buf); + + for (i = 0; i < BT_INFO_SRC_8723B_2ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8723b_2ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + /* Sw mechanism */ + if (btcoexist->manual_control) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Sw mechanism] (before Manual)============"); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Sw mechanism]============"); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", + "SM1[ShRf/ LpRA/ LimDig]", + coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, + coex_dm->limited_dig); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", + "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", + coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, + coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); + CL_PRINTF(cli_buf); + + /* Fw mechanism */ + if (btcoexist->manual_control) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Fw mechanism] (before Manual) ============"); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Fw mechanism]============"); + + ps_tdma_case = coex_dm->cur_ps_tdma; + + if (coex_dm->is_switch_to_1dot5_ant) + ps_tdma_case = ps_tdma_case + 100; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", + "PS TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + (coex_dm->cur_ps_tdma_on ? "On" : "Off"), + (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "Coex Table Type", + coex_sta->coex_table_type); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", + "DecBtPwr/ IgnWlanAct", + coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act); + CL_PRINTF(cli_buf); + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", + "RF-A, 0x1e initVal", + coex_dm->bt_rf_0x1e_backup); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x880); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x778/0x880[29:25]", + u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25); + CL_PRINTF(cli_buf); + + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x765); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x948/ 0x67[5] / 0x765", + u32tmp[0], ((u8tmp[0] & 0x20) >> 5), u8tmp[1]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x92c); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x930); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x944); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]", + u32tmp[0] & 0x3, u32tmp[1] & 0xff, u32tmp[2] & 0x3); + CL_PRINTF(cli_buf); + + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x39); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "0x38[11]/0x40/0x4c[24:23]/0x64[0]", + ((u8tmp[0] & 0x8) >> 3), u8tmp[1], + ((u32tmp[0] & 0x01800000) >> 23), u8tmp[2] & 0x1); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x550(bcn ctrl)/0x522", + u32tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0xc50(dig)/0x49c(null-drop)", + u32tmp[0] & 0xff, u8tmp[0]); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_CCK); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11n-agg", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_Err CCK/11g/11n/11n-agg", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", + u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(high-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x774(low-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx); + CL_PRINTF(cli_buf); +#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 1) + /* halbtc8723b2ant_monitor_bt_ctr(btcoexist); */ +#endif + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +void ex_halbtc8723b2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = true; + halbtc8723b2ant_wifi_off_hw_cfg(btcoexist); + halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + halbtc8723b2ant_coex_all_off(btcoexist); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = false; + halbtc8723b2ant_init_hw_config(btcoexist, false); + halbtc8723b2ant_init_coex_dm(btcoexist); + halbtc8723b2ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8723b2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = true; + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = false; + } +} + +void ex_halbtc8723b2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u32 u32tmp; + u8 u8tmpa, u8tmpb; + + + + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); + u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); + u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); + + if (BTC_SCAN_START == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, + false, false); + } else if (BTC_SCAN_FINISH == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n", + u32tmp, u8tmpa, u8tmpb); + BTC_TRACE(trace_buf); +} + +void ex_halbtc8723b2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (BTC_ASSOCIATE_START == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, + false, false); + } else if (BTC_ASSOCIATE_FINISH == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify\n"); + BTC_TRACE(trace_buf); + } +} + +void ex_halbtc8723b2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + u8 ap_num = 0; + + if (BTC_MEDIA_CONNECT == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, + false, false); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + } + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + h2c_parameter[0] = 0x1; + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else { + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &ap_num); + if (ap_num < 10) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); +} + +void ex_halbtc8723b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (type == BTC_PACKET_DHCP) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], DHCP Packet notify\n"); + BTC_TRACE(trace_buf); + } +} + +void ex_halbtc8723b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 bt_info = 0; + u8 i, rsp_source = 0; + boolean bt_busy = false, limited_dig = false; + boolean wifi_connected = false; + + coex_sta->c2h_bt_info_req_sent = false; + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8723B_2ANT_MAX) + rsp_source = BT_INFO_SRC_8723B_2ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + if (i == 1) + bt_info = tmp_buf[i]; + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n"); + BTC_TRACE(trace_buf); + return; + } + + /* if 0xff, it means BT is under WHCK test */ + if (bt_info == 0xff) + coex_sta->bt_whck_test = true; + else + coex_sta->bt_whck_test = false; + + if (BT_INFO_SRC_8723B_2ANT_WIFI_FW != rsp_source) { + coex_sta->bt_retry_cnt = /* [3:0] */ + coex_sta->bt_info_c2h[rsp_source][2] & 0xf; + + if (coex_sta->bt_retry_cnt >= 1) + coex_sta->pop_event_cnt++; + + coex_sta->bt_rssi = + coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; + + coex_sta->bt_info_ext = + coex_sta->bt_info_c2h[rsp_source][4]; + + if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) + coex_sta->c2h_bt_remote_name_req = true; + else + coex_sta->c2h_bt_remote_name_req = false; + + if (coex_sta->bt_info_c2h[rsp_source][1] == 0x49) { + coex_sta->a2dp_bit_pool = + coex_sta->bt_info_c2h[rsp_source][6]; + } else + coex_sta->a2dp_bit_pool = 0; + + coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] + & 0x40); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, + &coex_sta->bt_tx_rx_mask); + if (coex_sta->bt_tx_rx_mask) { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */ + /* BT TRx mask off */ + btcoexist->btc_set_bt_trx_mask(btcoexist, 0); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT TRx Mask off for BT Info Notify\n"); + BTC_TRACE(trace_buf); +#if 0 + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, + 0x3c, 0x01); +#endif + } + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + if (wifi_connected) + ex_halbtc8723b2ant_media_status_notify( + btcoexist, BTC_MEDIA_CONNECT); + else + ex_halbtc8723b2ant_media_status_notify( + btcoexist, BTC_MEDIA_DISCONNECT); + } + + if ((coex_sta->bt_info_ext & BIT(3))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, + false); + } else { + /* BT already NOT ignore Wlan active, do nothing here. */ + } +#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 0) + if ((coex_sta->bt_info_ext & BIT(4))) { + /* BT auto report already enabled, do nothing */ + } else + halbtc8723b2ant_bt_auto_report(btcoexist, FORCE_EXEC, + true); +#endif + } + + /* check BIT2 first ==> check if bt is under inquiry or page scan */ + if (bt_info & BT_INFO_8723B_2ANT_B_INQ_PAGE) + coex_sta->c2h_bt_inquiry_page = true; + else + coex_sta->c2h_bt_inquiry_page = false; + + /* set link exist status */ + if (!(bt_info & BT_INFO_8723B_2ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (bt_info & BT_INFO_8723B_2ANT_B_FTP) + coex_sta->pan_exist = true; + else + coex_sta->pan_exist = false; + if (bt_info & BT_INFO_8723B_2ANT_B_A2DP) + coex_sta->a2dp_exist = true; + else + coex_sta->a2dp_exist = false; + if (bt_info & BT_INFO_8723B_2ANT_B_HID) + coex_sta->hid_exist = true; + else + coex_sta->hid_exist = false; + if (bt_info & BT_INFO_8723B_2ANT_B_SCO_ESCO) + coex_sta->sco_exist = true; + else + coex_sta->sco_exist = false; + + if ((coex_sta->hid_exist == false) && + (coex_sta->c2h_bt_inquiry_page == false) && + (coex_sta->sco_exist == false)) { + if (coex_sta->high_priority_tx + + coex_sta->high_priority_rx >= 160) { + coex_sta->hid_exist = true; + bt_info = bt_info | 0x28; + } + } + } + + halbtc8723b2ant_update_bt_link_info(btcoexist); + + if (!(bt_info & BT_INFO_8723B_2ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info == + BT_INFO_8723B_2ANT_B_CONNECTION) { /* connection exists but no busy */ + coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + BTC_TRACE(trace_buf); + } else if ((bt_info & BT_INFO_8723B_2ANT_B_SCO_ESCO) || + (bt_info & BT_INFO_8723B_2ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info & BT_INFO_8723B_2ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + BTC_TRACE(trace_buf); + } + + if ((BT_8723B_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8723B_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { + bt_busy = true; + limited_dig = true; + } else { + bt_busy = false; + limited_dig = false; + } + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + coex_dm->limited_dig = limited_dig; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); + + halbtc8723b2ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8723b2ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8723b2ant_wifi_off_hw_cfg(btcoexist); + /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */ + /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); */ /*BT goto standby while GNT_BT 1-->0 */ + halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + + ex_halbtc8723b2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); +} + +void ex_halbtc8723b2ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_WIFI_PNP_SLEEP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + + /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ + /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ + /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ + coex_sta->under_ips = false; + coex_sta->under_lps = false; + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_init_hw_config(btcoexist, false); + halbtc8723b2ant_init_coex_dm(btcoexist); + halbtc8723b2ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8723b2ant_periodical(IN struct btc_coexist *btcoexist) +{ + u32 bt_patch_ver; + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ==========================Periodical===========================\n"); + BTC_TRACE(trace_buf); + if (coex_sta->dis_ver_info_cnt <= 5) { + coex_sta->dis_ver_info_cnt += 1; + if (coex_sta->dis_ver_info_cnt == 3) { + /* Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set GNT_BT control by PTA\n"); + BTC_TRACE(trace_buf); + halbtc8723b2ant_set_ant_path(btcoexist, + BTC_ANT_WIFI_AT_MAIN, false, false); + } + } + + if (((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) && (!coex_sta->bt_disabled)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, &coex_sta->bt_coex_supported_version); + + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + +#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 0) + halbtc8723b2ant_query_bt_info(btcoexist); + halbtc8723b2ant_monitor_bt_enable_disable(btcoexist); +#else + halbtc8723b2ant_monitor_bt_ctr(btcoexist); + halbtc8723b2ant_monitor_wifi_ctr(btcoexist); + + /* for some BT speaker that Hi-Pri pkt appear begore start play, this will cause HID exist */ + if ((coex_sta->high_priority_tx + coex_sta->high_priority_rx < 50) && + (bt_link_info->hid_exist == true)) + bt_link_info->hid_exist = false; + + if (halbtc8723b2ant_is_wifi_status_changed(btcoexist) || + coex_dm->auto_tdma_adjust) + halbtc8723b2ant_run_coexist_mechanism(btcoexist); +#endif +} + +#endif + +#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ + + diff --git a/hal/btc/halbtc8723b2ant.h b/hal/btc/halbtc8723b2ant.h new file mode 100644 index 0000000..fb6149a --- /dev/null +++ b/hal/btc/halbtc8723b2ant.h @@ -0,0 +1,231 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8723B_SUPPORT == 1) +/* ******************************************* + * The following is for 8723B 2Ant BT Co-exist definition + * ******************************************* */ +#define BT_AUTO_REPORT_ONLY_8723B_2ANT 1 + + +#define BT_INFO_8723B_2ANT_B_FTP BIT(7) +#define BT_INFO_8723B_2ANT_B_A2DP BIT(6) +#define BT_INFO_8723B_2ANT_B_HID BIT(5) +#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8723B_2ANT_B_CONNECTION BIT(0) + +#define BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT 2 + + +#define BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 /* WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */ +#define BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES 46 /* BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */ + +enum bt_info_src_8723b_2ant { + BT_INFO_SRC_8723B_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8723B_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8723B_2ANT_MAX +}; + +enum bt_8723b_2ant_bt_status { + BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8723B_2ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8723B_2ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8723B_2ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8723B_2ANT_BT_STATUS_MAX +}; + +enum bt_8723b_2ant_coex_algo { + BT_8723B_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8723B_2ANT_COEX_ALGO_SCO = 0x1, + BT_8723B_2ANT_COEX_ALGO_HID = 0x2, + BT_8723B_2ANT_COEX_ALGO_A2DP = 0x3, + BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8723B_2ANT_COEX_ALGO_PANEDR = 0x5, + BT_8723B_2ANT_COEX_ALGO_PANHS = 0x6, + BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8723B_2ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8723B_2ANT_COEX_ALGO_MAX = 0xb, +}; + +struct coex_dm_8723b_2ant { + /* fw mechanism */ + u8 pre_bt_dec_pwr_lvl; + u8 cur_bt_dec_pwr_lvl; + u8 pre_fw_dac_swing_lvl; + u8 cur_fw_dac_swing_lvl; + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean reset_tdma_adjust; + boolean auto_tdma_adjust; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + + /* sw mechanism */ + boolean pre_rf_rx_lpf_shrink; + boolean cur_rf_rx_lpf_shrink; + u32 bt_rf_0x1e_backup; + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + boolean pre_dac_swing_on; + u32 pre_dac_swing_lvl; + boolean cur_dac_swing_on; + u32 cur_dac_swing_lvl; + boolean pre_adc_back_off; + boolean cur_adc_back_off; + boolean pre_agc_table_en; + boolean cur_agc_table_en; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + boolean need_recover0x948; + u32 backup0x948; + + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + boolean is_switch_to_1dot5_ant; + u8 switch_thres_offset; +}; + +struct coex_sta_8723b_2ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + boolean bt_abnormal_scan; + boolean under_lps; + boolean under_ips; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + u8 bt_rssi; + boolean bt_tx_rx_mask; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + boolean c2h_bt_info_req_sent; + u8 bt_info_c2h[BT_INFO_SRC_8723B_2ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_2ANT_MAX]; + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; + u8 bt_retry_cnt; + u8 bt_info_ext; + u32 pop_event_cnt; + u8 scan_ap_num; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + + u32 bt_coex_supported_version; + + u8 coex_table_type; + boolean force_lps_on; + + u8 dis_ver_info_cnt; + + u8 a2dp_bit_pool; + u8 cut_version; +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8723b2ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8723b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist); +void ex_halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8723b2ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b2ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8723b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8723b2ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8723b2ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8723b2ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8723b2ant_display_coex_info(IN struct btc_coexist *btcoexist); + +#else +#define ex_halbtc8723b2ant_power_on_setting(btcoexist) +#define ex_halbtc8723b2ant_pre_load_firmware(btcoexist) +#define ex_halbtc8723b2ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8723b2ant_init_coex_dm(btcoexist) +#define ex_halbtc8723b2ant_ips_notify(btcoexist, type) +#define ex_halbtc8723b2ant_lps_notify(btcoexist, type) +#define ex_halbtc8723b2ant_scan_notify(btcoexist, type) +#define ex_halbtc8723b2ant_connect_notify(btcoexist, type) +#define ex_halbtc8723b2ant_media_status_notify(btcoexist, type) +#define ex_halbtc8723b2ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8723b2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8723b2ant_halt_notify(btcoexist) +#define ex_halbtc8723b2ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8723b2ant_periodical(btcoexist) +#define ex_halbtc8723b2ant_display_coex_info(btcoexist) + +#endif + +#endif + diff --git a/hal/btc/halbtc8723bwifionly.c b/hal/btc/halbtc8723bwifionly.c new file mode 100644 index 0000000..d1a8361 --- /dev/null +++ b/hal/btc/halbtc8723bwifionly.c @@ -0,0 +1,82 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "mp_precomp.h" + + +VOID +ex_hal8723b_wifi_only_hw_config( + IN struct wifi_only_cfg *pwifionlycfg + ) +{ + struct wifi_only_haldata *pwifionly_haldata = &pwifionlycfg->haldata_info; + + + halwifionly_write1byte(pwifionlycfg, 0x778, 0x3); /* Set pta for wifi first priority, 0x1 need to reference pta table to determine wifi and bt priority */ + halwifionly_bitmaskwrite1byte(pwifionlycfg, 0x40, 0x20, 0x1); + + /* Set Antenna path to Wifi */ + halwifionly_write2byte(pwifionlycfg, 0x0765, 0x8); /* Set pta for wifi first priority, 0x0 need to reference pta table to determine wifi and bt priority */ + halwifionly_write2byte(pwifionlycfg, 0x076e, 0xc); + + halwifionly_write4byte(pwifionlycfg, 0x000006c0, 0xaaaaaaaa); /* pta table, 0xaaaaaaaa means wifi is higher priority than bt */ + halwifionly_write4byte(pwifionlycfg, 0x000006c4, 0xaaaaaaaa); + + halwifionly_bitmaskwrite1byte(pwifionlycfg, 0x67, 0x20, 0x1); /* BT select s0/s1 is controlled by WiFi */ + + /* 0x948 setting */ + if (pwifionlycfg->chip_interface == WIFIONLY_INTF_PCI) { + /* HP Foxconn NGFF at S0 + not sure HP pg correct or not(EEPROMBluetoothSingleAntPath), so here we just write + 0x948=0x280 for HP HW id NIC. */ + if (pwifionly_haldata->customer_id == CUSTOMER_HP_1) { + halwifionly_write4byte(pwifionlycfg, 0x948, 0x280); + halwifionly_phy_set_rf_reg(pwifionlycfg, 0, 0x1, 0xfffff, 0x0); /* WiFi TRx Mask off */ + return; + } + } + + if (pwifionly_haldata->efuse_pg_antnum == 2) { + halwifionly_write4byte(pwifionlycfg, 0x948, 0x0); + } else { + /* 3Attention !!! For 8723BU !!!! + For 8723BU single ant case: jira [USB-1237] + Because of 8723BU S1 has HW problem, we only can use S0 instead. + Whether Efuse 0xc3 [6] is 0 or 1, we should always use S0 and write 0x948 to 80/280 + + -------------------------------------------------- + BT Team : + When in Single Ant case, Reg[0x948] has two case : 0x80 or 0x200 + When in Two Ant case, Reg[0x948] has two case : 0x280 or 0x0 + Efuse 0xc3 [6] Antenna Path + 0xc3 [6] = 0 ==> S1 ==> 0x948 = 0/40/200 + 0xc3 [6] = 1 ==> S0 ==> 0x948 = 80/240/280 */ + + if (pwifionlycfg->chip_interface == WIFIONLY_INTF_USB) + halwifionly_write4byte(pwifionlycfg, 0x948, 0x80); + else { + if (pwifionly_haldata->efuse_pg_antpath == 0) + halwifionly_write4byte(pwifionlycfg, 0x948, 0x0); + else + halwifionly_write4byte(pwifionlycfg, 0x948, 0x280); + } + + } + + + /* after 8723B F-cut, TRx Mask should be set when 0x948=0x0 or 0x280 + PHY_SetRFReg(Adapter, 0, 0x1, 0xfffff, 0x780); WiFi TRx Mask on */ + halwifionly_phy_set_rf_reg(pwifionlycfg, 0, 0x1, 0xfffff, 0x0); /*WiFi TRx Mask off */ + +} diff --git a/hal/btc/halbtc8723bwifionly.h b/hal/btc/halbtc8723bwifionly.h new file mode 100644 index 0000000..9d38664 --- /dev/null +++ b/hal/btc/halbtc8723bwifionly.h @@ -0,0 +1,22 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __INC_HAL8723BWIFIONLYHWCFG_H +#define __INC_HAL8723BWIFIONLYHWCFG_H + +VOID +ex_hal8723b_wifi_only_hw_config( + IN struct wifi_only_cfg *pwifionlycfg + ); +#endif diff --git a/hal/btc/halbtc8812a1ant.c b/hal/btc/halbtc8812a1ant.c new file mode 100644 index 0000000..0ac288e --- /dev/null +++ b/hal/btc/halbtc8812a1ant.c @@ -0,0 +1,3475 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for RTL8812A Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8812A_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8812a_1ant glcoex_dm_8812a_1ant; +static struct coex_dm_8812a_1ant *coex_dm = &glcoex_dm_8812a_1ant; +static struct coex_sta_8812a_1ant glcoex_sta_8812a_1ant; +static struct coex_sta_8812a_1ant *coex_sta = &glcoex_sta_8812a_1ant; + +const char *const glbt_info_src_8812a_1ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u32 glcoex_ver_date_8812a_1ant = 20140708; +u32 glcoex_ver_8812a_1ant = 0x52; + +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8812a1ant_ + * ************************************************************ */ +u8 halbtc8812a1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_bt_rssi_state; + } + + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + +u8 halbtc8812a1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_wifi_rssi_state[index]; + } + + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; + + return wifi_rssi_state; +} + +void halbtc8812a1ant_update_ra_mask(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 dis_rate_mask) +{ + coex_dm->cur_ra_mask = dis_rate_mask; + + if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) + btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, + &coex_dm->cur_ra_mask); + coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; +} + +/* to check 0x430/0x434 is correct?? */ +void halbtc8812a1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + boolean wifi_under_b_mode = false; + + coex_dm->cur_arfr_type = type; + + if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { + switch (coex_dm->cur_arfr_type) { + case 0: /* normal mode */ + btcoexist->btc_write_4byte(btcoexist, 0x430, + coex_dm->backup_arfr_cnt1); + btcoexist->btc_write_4byte(btcoexist, 0x434, + coex_dm->backup_arfr_cnt2); + break; + case 1: + btcoexist->btc_get(btcoexist, + BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + if (wifi_under_b_mode) { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x01010101); + } else { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x04030201); + } + break; + default: + break; + } + } + + coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; +} + +/* to check 0x42a ?? */ +void halbtc8812a1ant_retry_limit(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_retry_limit_type = type; + + if (force_exec || + (coex_dm->pre_retry_limit_type != + coex_dm->cur_retry_limit_type)) { + switch (coex_dm->cur_retry_limit_type) { + case 0: /* normal mode */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + coex_dm->backup_retry_limit); + break; + case 1: /* retry limit=8 */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + 0x0808); + break; + default: + break; + } + } + + coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; +} + +/* to check 0x456?? */ +void halbtc8812a1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_ampdu_time_type = type; + + if (force_exec || + (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { + switch (coex_dm->cur_ampdu_time_type) { + case 0: /* normal mode */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + coex_dm->backup_ampdu_max_time); + break; + case 1: /* AMPDU timw = 0x38 * 32us */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + 0x38); + break; + default: + break; + } + } + + coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; +} + +void halbtc8812a1ant_limited_tx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, + IN u8 retry_limit_type, IN u8 ampdu_time_type) +{ + switch (ra_mask_type) { + case 0: /* normal mode */ + halbtc8812a1ant_update_ra_mask(btcoexist, force_exec, + 0x0); + break; + case 1: /* disable cck 1/2 */ + halbtc8812a1ant_update_ra_mask(btcoexist, force_exec, + 0x00000003); + break; + case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ + halbtc8812a1ant_update_ra_mask(btcoexist, force_exec, + 0x0001f1f7); + break; + default: + break; + } + + halbtc8812a1ant_auto_rate_fallback_retry(btcoexist, force_exec, + arfr_type); + halbtc8812a1ant_retry_limit(btcoexist, force_exec, retry_limit_type); + halbtc8812a1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); +} + +void halbtc8812a1ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +void halbtc8812a1ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 data_len = 3; + u8 buf[5] = {0}; + + if (!coex_sta->bt_disabled) { + if (!coex_sta->bt_info_query_cnt || + (coex_sta->bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_BT_RSP] + - coex_sta->bt_info_query_cnt) > 2) { + buf[0] = data_len; + buf[1] = 0x1; /* polling enable, 1=enable, 0=disable */ + buf[2] = 0x2; /* polling time in seconds */ + buf[3] = 0x1; /* auto report enable, 1=enable, 0=disable */ + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_INFO, + (void *)&buf[0]); + } + } + coex_sta->bt_info_query_cnt++; +} + +void halbtc8812a1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u8 num_of_bt_counter_chk = 0; + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + if ((coex_sta->low_priority_tx > 1150) && + (!coex_sta->c2h_bt_inquiry_page)) + coex_sta->pop_event_cnt++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); + BTC_TRACE(trace_buf); + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + + if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) && + (reg_lp_rx == 0)) { + num_of_bt_counter_chk++; + if (num_of_bt_counter_chk >= 3) { + halbtc8812a1ant_query_bt_info(btcoexist); + num_of_bt_counter_chk = 0; + } + } +} + +/* to check registers */ +void halbtc8812a1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ + s32 wifi_rssi = 0; + boolean wifi_busy = false, wifi_under_b_mode = false; + static u8 cck_lock_counter = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + if (coex_sta->under_ips) { + coex_sta->crc_ok_cck = 0; + coex_sta->crc_ok_11g = 0; + coex_sta->crc_ok_11n = 0; + coex_sta->crc_ok_11n_agg = 0; + + coex_sta->crc_err_cck = 0; + coex_sta->crc_err_11g = 0; + coex_sta->crc_err_11n = 0; + coex_sta->crc_err_11n_agg = 0; + } else { + coex_sta->crc_ok_cck = btcoexist->btc_read_2byte(btcoexist, + 0xf04); + coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, + 0xf14); + coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, + 0xf10); + coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, + 0xf40); + + coex_sta->crc_err_cck = btcoexist->btc_read_2byte(btcoexist, + 0xf06); + coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, + 0xf16); + coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, + 0xf12); + coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, + 0xf42); + } + + + /* reset counter */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x0); + + if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { + if ((coex_dm->bt_status == BT_8812A_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == + BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (coex_dm->bt_status == + BT_8812A_1ANT_BT_STATUS_SCO_BUSY)) { + if (coex_sta->crc_ok_cck > (coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + + coex_sta->crc_ok_11n_agg)) { + if (cck_lock_counter < 5) + cck_lock_counter++; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + if (!coex_sta->pre_ccklock) { + + if (cck_lock_counter >= 5) + coex_sta->cck_lock = true; + else + coex_sta->cck_lock = false; + } else { + if (cck_lock_counter == 0) + coex_sta->cck_lock = false; + else + coex_sta->cck_lock = true; + } + + coex_sta->pre_ccklock = coex_sta->cck_lock; + + +} + +boolean halbtc8812a1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) +{ + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + } + + return false; +} + +void halbtc8812a1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = true; + bt_link_info->bt_link_exist = true; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = true; + else + bt_link_info->sco_only = false; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = true; + else + bt_link_info->a2dp_only = false; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = true; + else + bt_link_info->pan_only = false; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = true; + else + bt_link_info->hid_only = false; +} + +u8 halbtc8812a1ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + u8 algorithm = BT_8812A_1ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_1ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +void halbtc8812a1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean enable_auto_report) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = 0; + + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); + + btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); +} + +void halbtc8812a1ant_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable_auto_report) +{ + coex_dm->cur_bt_auto_report = enable_auto_report; + + if (!force_exec) { + if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) + return; + } + halbtc8812a1ant_set_bt_auto_report(btcoexist, + coex_dm->cur_bt_auto_report); + + coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; +} + +/* to check */ +void halbtc8812a1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist + *btcoexist, IN boolean low_penalty_ra) +{ + u8 tmp_u1; + + tmp_u1 = btcoexist->btc_read_1byte(btcoexist, 0x4fd); + tmp_u1 |= BIT(0); + if (low_penalty_ra) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Tx rate adaptive, set low penalty!!\n"); + BTC_TRACE(trace_buf); + tmp_u1 &= ~BIT(2); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Tx rate adaptive, set normal!!\n"); + BTC_TRACE(trace_buf); + tmp_u1 |= BIT(2); + } + + btcoexist->btc_write_1byte(btcoexist, 0x4fd, tmp_u1); +} + +void halbtc8812a1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) + return; + } + halbtc8812a1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, + coex_dm->cur_low_penalty_ra); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; +} + +void halbtc8812a1ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8812a1ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8812a1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8812a1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** CoexTable(%d) **********\n", type); + BTC_TRACE(trace_buf); + + coex_sta->coex_table_type = type; + + switch (type) { + case 0: + halbtc8812a1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8812a1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 2: + halbtc8812a1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 3: + halbtc8812a1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 4: + halbtc8812a1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); + break; + case 5: + halbtc8812a1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0xaa5a5a5a, 0xffffff, 0x3); + break; + case 6: + halbtc8812a1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 7: + halbtc8812a1ant_coex_table(btcoexist, force_exec, + 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + default: + break; + } +} + +void halbtc8812a1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 data_len = 3; + u8 buf[5] = {0}; + + buf[0] = data_len; + buf[1] = 0x1; /* OP_Code */ + buf[2] = 0x1; /* OP_Code_Length */ + if (enable) + buf[3] = 0x1; /* OP_Code_Content */ + else + buf[3] = 0x0; + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, + (void *)&buf[0]); +} + +void halbtc8812a1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8812a1ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8812a1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8812a1ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8812a1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8812a1ant_sw_mechanism(IN struct btc_coexist *btcoexist, + IN boolean low_penalty_ra) +{ + halbtc8812a1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); +} + +/* to check force_exec */ +void halbtc8812a1ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg, + IN boolean wifi_off) +{ + u8 u8tmp = 0; + + coex_dm->cur_ant_pos_type = ant_pos_type; + + if (init_hwcfg) { + btcoexist->btc_write_1byte(btcoexist, 0xcb3, 0x77); + btcoexist->btc_write_4byte(btcoexist, 0x900, 0x00000400); + btcoexist->btc_write_1byte(btcoexist, 0x76d, 0x1); + } else if (wifi_off) { + btcoexist->btc_write_1byte(btcoexist, 0xcb3, 0x77); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7); + u8tmp &= ~BIT(3); + u8tmp |= BIT(2); + btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp); + } + + if (force_exec || + (coex_dm->cur_ant_pos_type != coex_dm->pre_ant_pos_type)) { + /* ext switch setting */ + switch (ant_pos_type) { + case BTC_ANT_PATH_WIFI: + u8tmp = btcoexist->btc_read_1byte(btcoexist, + 0xcb7); + u8tmp |= BIT(3); + u8tmp &= ~BIT(2); + btcoexist->btc_write_1byte(btcoexist, 0xcb7, + u8tmp); + break; + case BTC_ANT_PATH_BT: + u8tmp = btcoexist->btc_read_1byte(btcoexist, + 0xcb7); + u8tmp &= ~BIT(3); + u8tmp |= BIT(2); + btcoexist->btc_write_1byte(btcoexist, 0xcb7, + u8tmp); + break; + default: + case BTC_ANT_PATH_PTA: + u8tmp = btcoexist->btc_read_1byte(btcoexist, + 0xcb7); + u8tmp |= BIT(3); + u8tmp &= ~BIT(2); + btcoexist->btc_write_1byte(btcoexist, 0xcb7, + u8tmp); + break; + } + } + + coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; +} + +void halbtc8812a1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if (ap_enable) { + if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], FW for 1Ant AP mode\n"); + BTC_TRACE(trace_buf); + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + } + } + + h2c_parameter[0] = real_byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = real_byte5; + + coex_dm->ps_tdma_para[0] = real_byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = real_byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); +} + + +void halbtc8812a1ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = false; + u8 rssi_adjust_val = 0; + u8 ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51, + ps_tdma_byte3_val = 0x10; + s8 wifi_duration_adjust = 0x0; + static boolean pre_wifi_busy = false; + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (wifi_busy != pre_wifi_busy) { + force_exec = true; + pre_wifi_busy = wifi_busy; + } + + if (coex_dm->cur_ps_tdma_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(on, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) + return; + } + + if (coex_sta->scan_ap_num <= 5) + wifi_duration_adjust = 2; + else if (coex_sta->scan_ap_num >= 40) + wifi_duration_adjust = -15; + else if (coex_sta->scan_ap_num >= 20) + wifi_duration_adjust = -10; + + if (!coex_sta->force_lps_on) { /* only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */ + ps_tdma_byte0_val = 0x61; /* no null-pkt */ + ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */ + ps_tdma_byte4_val = 0x10; /* 0x778 = d/1 toggle */ + } + + if ((type == 3) || (type == 13) || (type == 14)) { + ps_tdma_byte4_val = ps_tdma_byte4_val & + 0xbf; /* no dynamic slot for multi-profile */ + + if (!wifi_busy) + ps_tdma_byte4_val = ps_tdma_byte4_val | + 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ + } + + if (bt_link_info->slave_role == true) + ps_tdma_byte4_val = ps_tdma_byte4_val | + 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ + + if (turn_on) { + switch (type) { + default: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x1a, 0x1a, 0x0, ps_tdma_byte4_val); + break; + case 1: + halbtc8812a1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x3a + + wifi_duration_adjust, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 2: + halbtc8812a1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x2d + + wifi_duration_adjust, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 3: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x1d, 0x1d, 0x0, ps_tdma_byte4_val); + break; + case 4: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93, + 0x15, 0x3, 0x14, 0x0); + break; + case 5: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, + 0x15, 0x3, 0x11, 0x11); + break; + case 6: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, + 0x20, 0x3, 0x11, 0x11); + break; + case 7: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13, + 0xc, 0x5, 0x0, 0x0); + break; + case 8: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93, + 0x25, 0x3, 0x10, 0x0); + break; + case 9: + halbtc8812a1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x21, 0x3, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 10: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13, + 0xa, 0xa, 0x0, 0x40); + break; + case 11: + halbtc8812a1ant_set_fw_pstdma(btcoexist, + ps_tdma_byte0_val, 0x21, 0x03, + ps_tdma_byte3_val, ps_tdma_byte4_val); + break; + case 12: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x0a, 0x0a, 0x0, 0x50); + break; + case 13: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x12, 0x12, 0x0, ps_tdma_byte4_val); + break; + case 14: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x21, 0x3, 0x10, ps_tdma_byte4_val); + break; + case 15: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13, + 0xa, 0x3, 0x8, 0x0); + break; + case 16: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93, + 0x15, 0x3, 0x10, 0x0); + break; + case 18: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93, + 0x25, 0x3, 0x10, 0x0); + break; + case 20: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, + 0x3f, 0x03, 0x11, 0x10); + break; + case 21: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, 0x11); + break; + case 22: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, 0x10); + break; + case 23: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x3, 0x31, 0x18); + break; + case 24: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, + 0x15, 0x3, 0x31, 0x18); + break; + case 25: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, + 0xa, 0x3, 0x31, 0x18); + break; + case 26: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, + 0xa, 0x3, 0x31, 0x18); + break; + case 27: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x3, 0x31, 0x98); + break; + case 28: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x69, + 0x25, 0x3, 0x31, 0x0); + break; + case 29: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xab, + 0x1a, 0x1a, 0x1, 0x10); + break; + case 30: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, 0x10); + break; + case 31: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xd3, + 0x1a, 0x1a, 0, 0x58); + break; + case 32: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x3, 0x11, 0x11); + break; + case 33: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xa3, + 0x25, 0x3, 0x30, 0x90); + break; + case 34: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x53, + 0x1a, 0x1a, 0x0, 0x10); + break; + case 35: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x63, + 0x1a, 0x1a, 0x0, 0x10); + break; + case 36: + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xd3, + 0x12, 0x3, 0x14, 0x50); + break; + case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */ + /* here softap mode screen off will cost 70-80mA for phone */ + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x23, + 0x18, 0x00, 0x10, 0x24); + break; + } + } else { + + /* disable PS tdma */ + switch (type) { + case 8: /* PTA Control */ + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x8, + 0x0, 0x0, 0x0, 0x0); + break; + case 0: + default: /* Software control, Antenna at BT side */ + halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x0, 0x0); + break; + } + } + rssi_adjust_val = 0; + btcoexist->btc_set(btcoexist, + BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val); + + + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; +} + +boolean halbtc8812a1ant_is_common_action(IN struct btc_coexist *btcoexist) +{ + boolean common = false, wifi_connected = false, wifi_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_connected && + BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + + /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ + + common = true; + } else if (wifi_connected && + (BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + + /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ + + common = true; + } else if (!wifi_connected && + (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + + /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ + + common = true; + } else if (wifi_connected && + (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + + /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ + + common = true; + } else if (!wifi_connected && + (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + + /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ + + common = true; + } else { + if (wifi_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } + + common = false; + } + + return common; +} + + +void halbtc8812a1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist + *btcoexist, IN u8 wifi_status) +{ + static s32 up, dn, m, n, wait_count; + s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ + u8 retry_count = 0, bt_info_ext; + boolean wifi_busy = false; + + if (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status) + wifi_busy = true; + else + wifi_busy = false; + + if ((BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == + wifi_status) || + (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) || + (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT == + wifi_status)) { + if (coex_dm->cur_ps_tdma != 1 && + coex_dm->cur_ps_tdma != 2 && + coex_dm->cur_ps_tdma != 3 && + coex_dm->cur_ps_tdma != 9) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 9); + coex_dm->ps_tdma_du_adj_type = 9; + + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } + return; + } + + if (!coex_dm->auto_tdma_adjust) { + coex_dm->auto_tdma_adjust = true; + + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + /* ============ */ + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } else { + /* acquire the BT TRx retry count from BT_Info byte2 */ + retry_count = coex_sta->bt_retry_cnt; + bt_info_ext = coex_sta->bt_info_ext; + + if ((coex_sta->low_priority_tx) > 1150 || + (coex_sta->low_priority_rx) > 1250) + retry_count++; + + result = 0; + wait_count++; + + if (retry_count == + 0) { /* no retry in the last 2-second duration */ + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ + wait_count = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + } + } else if (retry_count <= + 3) { /* <=3 retry in the last 2-second duration */ + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ + if (wait_count <= 2) + m++; /* to avoid loop between the two levels */ + else + m = 1; + + if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ + if (wait_count == 1) + m++; /* to avoid loop between the two levels */ + else + m = 1; + + if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + + if (result == -1) { + if ((BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && + ((coex_dm->cur_ps_tdma == 1) || + (coex_dm->cur_ps_tdma == 2))) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 1) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } + } else if (result == 1) { + if ((BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && + ((coex_dm->cur_ps_tdma == 1) || + (coex_dm->cur_ps_tdma == 2))) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = 1; + } + } else { /* no change */ + /* Bryant Modify + if(wifi_busy != pre_wifi_busy) + { + pre_wifi_busy = wifi_busy; + halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma); + } + */ + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(on, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } + + if (coex_dm->cur_ps_tdma != 1 && + coex_dm->cur_ps_tdma != 2 && + coex_dm->cur_ps_tdma != 9 && + coex_dm->cur_ps_tdma != 11) { + /* recover to previous adjust type */ + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + coex_dm->ps_tdma_du_adj_type); + } + } +} + +void halbtc8812a1ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + +void halbtc8812a1ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = false; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + /* recover to original 32k low power setting */ + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + case BTC_PS_LPS_ON: + halbtc8812a1ant_ps_tdma_check_for_power_save_state( + btcoexist, true); + halbtc8812a1ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + coex_sta->force_lps_on = true; + break; + case BTC_PS_LPS_OFF: + halbtc8812a1ant_ps_tdma_check_for_power_save_state( + btcoexist, false); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + default: + break; + } +} + +void halbtc8812a1ant_action_wifi_only(IN struct btc_coexist *btcoexist) +{ + halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, + false, false); +} + +void halbtc8812a1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = true, bt_disabled = false; + + /* This function check if bt is disabled */ + + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = false; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = false; + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + BTC_TRACE(trace_buf); + } else { + bt_disable_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt all counters=0, %d times!!\n", + bt_disable_cnt); + BTC_TRACE(trace_buf); + if (bt_disable_cnt >= 2) { + bt_disabled = true; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + BTC_TRACE(trace_buf); + halbtc8812a1ant_action_wifi_only(btcoexist); + } + } + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + if (!bt_disabled) { + } else { + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + } + } +} + +/* ********************************************* + * + * Software Coex Mechanism start + * + * ********************************************* */ + +/* SCO only or SCO+PAN(HS) */ + +/* +void halbtc8812a1ant_action_sco(IN struct btc_coexist* btcoexist) +{ + halbtc8812a1ant_sw_mechanism(btcoexist, true); +} + + +void halbtc8812a1ant_action_hid(IN struct btc_coexist* btcoexist) +{ + halbtc8812a1ant_sw_mechanism(btcoexist, true); +} + + +void halbtc8812a1ant_action_a2dp(IN struct btc_coexist* btcoexist) +{ + halbtc8812a1ant_sw_mechanism(btcoexist, false); +} + +void halbtc8812a1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist) +{ + halbtc8812a1ant_sw_mechanism(btcoexist, false); +} + +void halbtc8812a1ant_action_pan_edr(IN struct btc_coexist* btcoexist) +{ + halbtc8812a1ant_sw_mechanism(btcoexist, false); +} + + +void halbtc8812a1ant_action_pan_hs(IN struct btc_coexist* btcoexist) +{ + halbtc8812a1ant_sw_mechanism(btcoexist, false); +} + + +void halbtc8812a1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist) +{ + halbtc8812a1ant_sw_mechanism(btcoexist, false); +} + +void halbtc8812a1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist) +{ + halbtc8812a1ant_sw_mechanism(btcoexist, true); +} + + +void halbtc8812a1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist) +{ + halbtc8812a1ant_sw_mechanism(btcoexist, true); +} + +void halbtc8812a1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist) +{ + halbtc8812a1ant_sw_mechanism(btcoexist, true); +} + +*/ + +/* ********************************************* + * + * Non-Software Coex Mechanism start + * + * ********************************************* */ +void halbtc8812a1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, + false, false); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8812a1ant_action_hs(IN struct btc_coexist *btcoexist) +{ + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8812a1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, ap_enable = false, wifi_busy = false, + bt_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) { + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + NORMAL_EXEC, false, false); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || + (bt_link_info->a2dp_exist)) { + /* SCO/HID/A2DP busy */ + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if ((bt_link_info->pan_exist) || (wifi_busy)) { + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + NORMAL_EXEC, false, false); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + } +} + +void halbtc8812a1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist + *btcoexist, IN u8 wifi_status) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* tdma and coex table */ + + if (bt_link_info->sco_exist) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + } else { /* HID */ + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + } +} + +void halbtc8812a1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist + *btcoexist, IN u8 wifi_status) +{ + u8 bt_rssi_state; + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + bt_rssi_state = halbtc8812a1ant_bt_rssi_state(2, 28, 0); + + if ((coex_sta->low_priority_rx >= 950) && (!coex_sta->under_ips)) + bt_link_info->slave_role = true; + else + bt_link_info->slave_role = false; + + if (bt_link_info->hid_only) { /* HID */ + halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, + wifi_status); + coex_dm->auto_tdma_adjust = false; + return; + } else if (bt_link_info->a2dp_only) { /* A2DP */ + if (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + halbtc8812a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = false; + } else { + halbtc8812a1ant_tdma_duration_adjust_for_acl(btcoexist, + wifi_status); + halbtc8812a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = true; + } + } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || + (bt_link_info->hid_exist && bt_link_info->a2dp_exist && + bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = false; + } else if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { /* HID+A2DP */ + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); + coex_dm->auto_tdma_adjust = false; + + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && + bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = false; + } else { + /* BT no-profile busy (0x9) */ + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + coex_dm->auto_tdma_adjust = false; + } +} + +void halbtc8812a1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +{ + /* power save state */ + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, + false, false); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8812a1ant_action_wifi_not_connected_scan(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + if (bt_link_info->a2dp_exist) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + halbtc8812a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else if (bt_link_info->a2dp_exist && + bt_link_info->pan_exist) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 22); + halbtc8812a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 20); + halbtc8812a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } else { + /* Bryant Add */ + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + NORMAL_EXEC, false, false); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8812a1ant_action_wifi_not_connected_asso_auth( + IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || + (bt_link_info->a2dp_exist)) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); + } else if (bt_link_info->pan_exist) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); + } else { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + NORMAL_EXEC, false, false); + halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2); + } +} + +void halbtc8812a1ant_action_wifi_connected_scan(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + if (bt_link_info->a2dp_exist) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + halbtc8812a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else if (bt_link_info->a2dp_exist && + bt_link_info->pan_exist) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 22); + halbtc8812a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 20); + halbtc8812a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } else { + /* Bryant Add */ + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + NORMAL_EXEC, false, false); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8812a1ant_action_wifi_connected_specific_packet( + IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || + (bt_link_info->a2dp_exist)) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if (bt_link_info->pan_exist) { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + NORMAL_EXEC, false, false); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8812a1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +{ + boolean wifi_busy = false; + boolean scan = false, link = false, roam = false; + boolean under_4way = false, ap_enable = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect()===>\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + if (under_4way) { + halbtc8812a1ant_action_wifi_connected_specific_packet(btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + if (scan || link || roam) { + if (scan) + halbtc8812a1ant_action_wifi_connected_scan(btcoexist); + else + halbtc8812a1ant_action_wifi_connected_specific_packet( + btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + /* power save state */ + if (!ap_enable && + BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status && + !btcoexist->bt_link_info.hid_only) { + if (btcoexist->bt_link_info.a2dp_only) { /* A2DP */ + if (!wifi_busy) + halbtc8812a1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else { /* busy */ + if (coex_sta->scan_ap_num >= + BT_8812A_1ANT_WIFI_NOISY_THRESH) /* no force LPS, no PS-TDMA, use pure TDMA */ + halbtc8812a1ant_power_save_state( + btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8812a1ant_power_save_state( + btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + } + } else if ((coex_sta->pan_exist == false) && + (coex_sta->a2dp_exist == false) && + (coex_sta->hid_exist == false)) + halbtc8812a1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8812a1ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + } else + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + + /* tdma and coex table */ + if (!wifi_busy) { + if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + halbtc8812a1ant_action_wifi_connected_bt_acl_busy( + btcoexist, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } else { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); + halbtc8812a1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); + if ((coex_sta->high_priority_tx) + + (coex_sta->high_priority_rx) <= 60) + halbtc8812a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 2); + else + halbtc8812a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } + } else { + if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + halbtc8812a1ant_action_wifi_connected_bt_acl_busy( + btcoexist, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } else { + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); + halbtc8812a1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); + if ((coex_sta->high_priority_tx) + + (coex_sta->high_priority_rx) <= 60) + halbtc8812a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 2); + else + halbtc8812a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } + } +} + +void halbtc8812a1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + u8 algorithm = 0; + + algorithm = halbtc8812a1ant_action_algorithm(btcoexist); + coex_dm->cur_algorithm = algorithm; + + if (halbtc8812a1ant_is_common_action(btcoexist)) { + + } else { + switch (coex_dm->cur_algorithm) { + case BT_8812A_1ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + /* halbtc8812a1ant_action_sco(btcoexist); */ + break; + case BT_8812A_1ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID.\n"); + BTC_TRACE(trace_buf); + /* halbtc8812a1ant_action_hid(btcoexist); */ + break; + case BT_8812A_1ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + /* halbtc8812a1ant_action_a2dp(btcoexist); */ + break; + case BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + /* halbtc8812a1ant_action_a2dp_pan_hs(btcoexist); */ + break; + case BT_8812A_1ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + /* halbtc8812a1ant_action_pan_edr(btcoexist); */ + break; + case BT_8812A_1ANT_COEX_ALGO_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HS mode.\n"); + BTC_TRACE(trace_buf); + /* halbtc8812a1ant_action_pan_hs(btcoexist); */ + break; + case BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + /* halbtc8812a1ant_action_pan_edr_a2dp(btcoexist); */ + break; + case BT_8812A_1ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + /* halbtc8812a1ant_action_pan_edr_hid(btcoexist); */ + break; + case BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + /* halbtc8812a1ant_action_hid_a2dp_pan_edr(btcoexist); */ + break; + case BT_8812A_1ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + /* halbtc8812a1ant_action_hid_a2dp(btcoexist); */ + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + /* halbtc8812a1ant_coex_all_off(btcoexist); */ + break; + } + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + } +} + +void halbtc8812a1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, bt_hs_on = false; + boolean increase_scan_dev_num = false; + boolean bt_ctrl_agg_buf_size = false; + boolean miracast_plus_bt = false; + u8 agg_buf_size = 5; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0, wifi_bw; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if ((BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + increase_scan_dev_num = true; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, + &increase_scan_dev_num); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", + num_of_wifi_link, wifi_link_status); + BTC_TRACE(trace_buf); + + if (bt_link_info->bt_link_exist) { + halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, + 0, 1); + miracast_plus_bt = true; + } else { + halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, + 0, 0); + miracast_plus_bt = false; + } + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + + if ((bt_link_info->a2dp_exist) && + (coex_sta->c2h_bt_inquiry_page)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is Inquirying\n"); + BTC_TRACE(trace_buf); + halbtc8812a1ant_action_bt_inquiry(btcoexist); + } else + halbtc8812a1ant_action_wifi_multi_port(btcoexist); + + return; + } + + miracast_plus_bt = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if ((bt_link_info->bt_link_exist) && (wifi_connected)) { + halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); + + if (bt_link_info->sco_exist) + halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, true, + false, 0x5); + else { + if (BTC_WIFI_BW_HT40 == wifi_bw) + halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, + false, true, 0x10); + else + halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, + false, true, 0x8); + } + + halbtc8812a1ant_sw_mechanism(btcoexist, true); + halbtc8812a1ant_run_sw_coexist_mechanism( + btcoexist); /* just print debug message */ + } else { + halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + + halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x5); + + halbtc8812a1ant_sw_mechanism(btcoexist, false); + halbtc8812a1ant_run_sw_coexist_mechanism( + btcoexist); /* //just print debug message */ + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is Inquirying\n"); + BTC_TRACE(trace_buf); + halbtc8812a1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8812a1ant_action_hs(btcoexist); + return; + } + + + if (!wifi_connected) { + boolean scan = false, link = false, roam = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is non connected-idle !!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + if (scan || link || roam) { + if (scan) + halbtc8812a1ant_action_wifi_not_connected_scan( + btcoexist); + else + halbtc8812a1ant_action_wifi_not_connected_asso_auth( + btcoexist); + } else + halbtc8812a1ant_action_wifi_not_connected(btcoexist); + } else /* wifi LPS/Busy */ + halbtc8812a1ant_action_wifi_connected(btcoexist); +} + +void halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + /* force to reset coex mechanism */ + + /* sw all off */ + halbtc8812a1ant_sw_mechanism(btcoexist, false); + + /* halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ + /* halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */ + + coex_sta->pop_event_cnt = 0; +} + +void halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean back_up, IN boolean wifi_only) +{ + u8 u8tmp = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 1Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + /* ant sw control to BT */ + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, + true, false); + + /* 0x790[5:0]=0x5 */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); + u8tmp &= 0xc0; + u8tmp |= 0x5; + btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); + + /* PTA parameter */ + btcoexist->btc_write_1byte(btcoexist, 0x6cc, 0x0); + btcoexist->btc_write_4byte(btcoexist, 0x6c8, 0xffff); + btcoexist->btc_write_4byte(btcoexist, 0x6c4, 0x55555555); + btcoexist->btc_write_4byte(btcoexist, 0x6c0, 0x55555555); + + /* coex parameters */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + + /* enable counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); + + /* enable PTA */ + btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); + + /* bt clock related */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x4); + u8tmp |= BIT(7); + btcoexist->btc_write_1byte(btcoexist, 0x4, u8tmp); + + /* bt clock related */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); + u8tmp |= BIT(1); + btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); +} + +/* ************************************************************ + * work around function start with wa_halbtc8812a1ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8812a1ant_ + * ************************************************************ */ +void ex_halbtc8812a1ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ +} + +void ex_halbtc8812a1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{ +} + +void ex_halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8812a1ant_init_hw_config(btcoexist, true, wifi_only); + btcoexist->stop_coex_dm = false; +} + +void ex_halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = false; + + halbtc8812a1ant_init_coex_dm(btcoexist); + + halbtc8812a1ant_query_bt_info(btcoexist); +} + +void ex_halbtc8812a1ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u32 u32tmp[4]; + u32 fw_ver = 0, bt_patch_ver = 0; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + if (btcoexist->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", + "Ant PG number/ Ant mechanism:", + board_info->pg_ant_num, board_info->btdm_ant_num); + CL_PRINTF(cli_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", + "CoexVer/ FwVer/ PatchVer", + glcoex_ver_date_8812a_1ant, glcoex_ver_8812a_1ant, fw_ver, + bt_patch_ver, bt_patch_ver); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "Wifi channel informed to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", + "BT [status/ rssi/ retryCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") + : ((BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi, coex_sta->bt_retry_cnt); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", + "SCO/HID/PAN/A2DP", + bt_link_info->sco_exist, bt_link_info->hid_exist, + bt_link_info->pan_exist, bt_link_info->a2dp_exist); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); + + bt_info_ext = coex_sta->bt_info_ext; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "BT Info A2DP rate", + (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); + CL_PRINTF(cli_buf); + + for (i = 0; i < BT_INFO_SRC_8812A_1ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8812a_1ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + if (!btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanisms]============"); + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", + "PS TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", + "Latest error condition(should be 0)", + coex_dm->error_condition); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", + "IgnWlanAct", + coex_dm->cur_ignore_wlan_act); + CL_PRINTF(cli_buf); + } + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", + u8tmp[0]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcb3); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb7); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x900); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0xcb3/0xcb7/0x900", + u8tmp[0], u8tmp[1], u32tmp[0]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", + u8tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x550(bcn ctrl)/0x522", + u32tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", + u32tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", + u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(hp rx[31:16]/tx[15:0])", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x774(lp rx[31:16]/tx[15:0])", + coex_sta->low_priority_rx, coex_sta->low_priority_tx); + CL_PRINTF(cli_buf); + + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + + +void ex_halbtc8812a1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = true; + + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, + FORCE_EXEC, false, true); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + + halbtc8812a1ant_init_hw_config(btcoexist, false, false); + halbtc8812a1ant_init_coex_dm(btcoexist); + halbtc8812a1ant_query_bt_info(btcoexist); + + coex_sta->under_ips = false; + } +} + +void ex_halbtc8812a1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = true; + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = false; + } +} + +void ex_halbtc8812a1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false, bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + if (BTC_SCAN_START == type) { + coex_sta->wifi_is_high_pri_task = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify\n"); + BTC_TRACE(trace_buf); + + halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 8); /* Force antenna setup for no scan result issue */ + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + FORCE_EXEC, false, false); + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + } + + if (coex_sta->bt_disabled) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + halbtc8812a1ant_query_bt_info(btcoexist); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8812a1ant_action_wifi_multi_port(btcoexist); + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8812a1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8812a1ant_action_hs(btcoexist); + return; + } + + if (BTC_SCAN_START == type) { + if (!wifi_connected) /* non-connected scan */ + halbtc8812a1ant_action_wifi_not_connected_scan( + btcoexist); + else /* wifi is connected */ + halbtc8812a1ant_action_wifi_connected_scan(btcoexist); + } else if (BTC_SCAN_FINISH == type) { + if (!wifi_connected) /* non-connected scan */ + halbtc8812a1ant_action_wifi_not_connected(btcoexist); + else + halbtc8812a1ant_action_wifi_connected(btcoexist); + } +} + +void ex_halbtc8812a1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false, bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm || + coex_sta->bt_disabled) + return; + + if (BTC_ASSOCIATE_START == type) { + coex_sta->wifi_is_high_pri_task = true; + halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 8); /* Force antenna setup for no scan result issue */ + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + FORCE_EXEC, false, false); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify\n"); + BTC_TRACE(trace_buf); + coex_dm->arp_cnt = 0; + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify\n"); + BTC_TRACE(trace_buf); + /* coex_dm->arp_cnt = 0; */ + } + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8812a1ant_action_wifi_multi_port(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8812a1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8812a1ant_action_hs(btcoexist); + return; + } + + if (BTC_ASSOCIATE_START == type) + halbtc8812a1ant_action_wifi_not_connected_asso_auth(btcoexist); + else if (BTC_ASSOCIATE_FINISH == type) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + if (!wifi_connected) /* non-connected scan */ + halbtc8812a1ant_action_wifi_not_connected(btcoexist); + else + halbtc8812a1ant_action_wifi_connected(btcoexist); + } +} + +/* to check registers... */ +void ex_halbtc8812a1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 data_len = 5; + u8 buf[6] = {0}; + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + boolean wifi_under_b_mode = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm || + coex_sta->bt_disabled) + return; + + if (BTC_MEDIA_CONNECT == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 8); /* Force antenna setup for no scan result issue */ + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, + FORCE_EXEC, false, false); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); +#if 0 + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x00); /* CCK Rx */ + } else { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x10); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x10); /* CCK Rx */ + } +#endif + coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, + 0x430); + coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, + 0x434); + coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( + btcoexist, 0x42a); + coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( + btcoexist, 0x456); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + coex_dm->arp_cnt = 0; + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + } + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + /* h2c_parameter[0] = 0x1; */ + h2c_parameter[0] = 0x0; + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + buf[0] = data_len; + buf[1] = 0x5; /* OP_Code */ + buf[2] = 0x3; /* OP_Code_Length */ + buf[3] = h2c_parameter[0]; /* OP_Code_Content */ + buf[4] = h2c_parameter[1]; + buf[5] = h2c_parameter[2]; + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, + (void *)&buf[0]); +} + +void ex_halbtc8812a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm || + coex_sta->bt_disabled) + return; + + if (BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + BTC_PACKET_ARP == type) { + if (BTC_PACKET_ARP == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ARP notify\n"); + BTC_TRACE(trace_buf); + + coex_dm->arp_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ARP Packet Count = %d\n", + coex_dm->arp_cnt); + BTC_TRACE(trace_buf); + + if (coex_dm->arp_cnt >= + 10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */ + coex_sta->wifi_is_high_pri_task = false; + else + coex_sta->wifi_is_high_pri_task = true; + } else { + coex_sta->wifi_is_high_pri_task = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet DHCP or EAPOL notify\n"); + BTC_TRACE(trace_buf); + } + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet [Type = %d] notify\n", type); + BTC_TRACE(trace_buf); + } + + coex_sta->specific_pkt_period_cnt = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8812a1ant_action_wifi_multi_port(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8812a1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8812a1ant_action_hs(btcoexist); + return; + } + + if (BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task))) + halbtc8812a1ant_action_wifi_connected_specific_packet(btcoexist); +} + +void ex_halbtc8812a1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 bt_info = 0; + u8 i, rsp_source = 0; + boolean wifi_connected = false; + boolean bt_busy = false; + + coex_sta->c2h_bt_info_req_sent = false; + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8812A_1ANT_MAX) + rsp_source = BT_INFO_SRC_8812A_1ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + if (i == 1) + bt_info = tmp_buf[i]; + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + if (BT_INFO_SRC_8812A_1ANT_WIFI_FW != rsp_source) { + coex_sta->bt_retry_cnt = /* [3:0] */ + coex_sta->bt_info_c2h[rsp_source][2] & 0xf; + + if (coex_sta->bt_retry_cnt >= 1) + coex_sta->pop_event_cnt++; + + if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) + coex_sta->c2h_bt_page = true; + else + coex_sta->c2h_bt_page = false; + + coex_sta->bt_rssi = + coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; + /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */ + + coex_sta->bt_info_ext = + coex_sta->bt_info_c2h[rsp_source][4]; + + coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] + & 0x40); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, + &coex_sta->bt_tx_rx_mask); + if (!coex_sta->bt_tx_rx_mask) { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, + 0x3c, 0x15); + } + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + if (coex_sta->bt_info_ext & BIT(1)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + if (wifi_connected) + ex_halbtc8812a1ant_media_status_notify( + btcoexist, BTC_MEDIA_CONNECT); + else + ex_halbtc8812a1ant_media_status_notify( + btcoexist, BTC_MEDIA_DISCONNECT); + } + + if (coex_sta->bt_info_ext & BIT(3)) { + if (!btcoexist->manual_control && + !btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8812a1ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, false); + } + } else { + /* BT already NOT ignore Wlan active, do nothing here. */ + } +#if (BT_AUTO_REPORT_ONLY_8812A_1ANT == 0) + if ((coex_sta->bt_info_ext & BIT(4))) { + /* BT auto report already enabled, do nothing */ + } else + halbtc8812a1ant_bt_auto_report(btcoexist, FORCE_EXEC, + true); +#endif + } + + /* check BIT2 first ==> check if bt is under inquiry or page scan */ + if (bt_info & BT_INFO_8812A_1ANT_B_INQ_PAGE) + coex_sta->c2h_bt_inquiry_page = true; + else + coex_sta->c2h_bt_inquiry_page = false; + + /* set link exist status */ + if (!(bt_info & BT_INFO_8812A_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (bt_info & BT_INFO_8812A_1ANT_B_FTP) + coex_sta->pan_exist = true; + else + coex_sta->pan_exist = false; + if (bt_info & BT_INFO_8812A_1ANT_B_A2DP) + coex_sta->a2dp_exist = true; + else + coex_sta->a2dp_exist = false; + if (bt_info & BT_INFO_8812A_1ANT_B_HID) + coex_sta->hid_exist = true; + else + coex_sta->hid_exist = false; + if (bt_info & BT_INFO_8812A_1ANT_B_SCO_ESCO) + coex_sta->sco_exist = true; + else + coex_sta->sco_exist = false; + } + + halbtc8812a1ant_update_bt_link_info(btcoexist); + + bt_info = bt_info & + 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ + + if (!(bt_info & BT_INFO_8812A_1ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info == + BT_INFO_8812A_1ANT_B_CONNECTION) { /* connection exists but no busy */ + coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + BTC_TRACE(trace_buf); + } else if ((bt_info & BT_INFO_8812A_1ANT_B_SCO_ESCO) || + (bt_info & BT_INFO_8812A_1ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info & BT_INFO_8812A_1ANT_B_ACL_BUSY) { + if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) + coex_dm->auto_tdma_adjust = false; + coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + BTC_TRACE(trace_buf); + } + + if ((BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + bt_busy = true; + else + bt_busy = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + halbtc8812a1ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8812a1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_RF_ON == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned ON!!\n"); + BTC_TRACE(trace_buf); + btcoexist->stop_coex_dm = false; + } else if (BTC_RF_OFF == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned OFF!!\n"); + BTC_TRACE(trace_buf); + + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, + FORCE_EXEC, false, true); + + halbtc8812a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + btcoexist->stop_coex_dm = true; + } +} + +void ex_halbtc8812a1ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, + false, true); + + halbtc8812a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + + ex_halbtc8812a1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + + btcoexist->stop_coex_dm = true; +} + +void ex_halbtc8812a1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_WIFI_PNP_SLEEP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + + halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, + FORCE_EXEC, false, true); + halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + + /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ + /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ + /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ + coex_sta->under_ips = false; + coex_sta->under_lps = false; + btcoexist->stop_coex_dm = true; + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); + btcoexist->stop_coex_dm = false; + halbtc8812a1ant_init_hw_config(btcoexist, false, false); + halbtc8812a1ant_init_coex_dm(btcoexist); + halbtc8812a1ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8812a1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], *****************Coex DM Reset*****************\n"); + BTC_TRACE(trace_buf); + + halbtc8812a1ant_init_hw_config(btcoexist, false, false); + halbtc8812a1ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8812a1ant_periodical(IN struct btc_coexist *btcoexist) +{ +#if (BT_AUTO_REPORT_ONLY_8812A_1ANT == 0) + halbtc8812a1ant_query_bt_info(btcoexist); + halbtc8812a1ant_monitor_bt_enable_disable(btcoexist); +#else + halbtc8812a1ant_monitor_bt_ctr(btcoexist); + halbtc8812a1ant_monitor_wifi_ctr(btcoexist); + + if (halbtc8812a1ant_is_wifi_status_changed(btcoexist) || + coex_dm->auto_tdma_adjust) + halbtc8812a1ant_run_coexist_mechanism(btcoexist); + + coex_sta->specific_pkt_period_cnt++; +#endif +} + +void ex_halbtc8812a1ant_dbg_control(IN struct btc_coexist *btcoexist, + IN u8 op_code, IN u8 op_len, IN u8 *pdata) +{ + switch (op_code) { + case BTC_DBG_SET_COEX_NORMAL: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set CoexMode to Normal\n"); + BTC_TRACE(trace_buf); + btcoexist->manual_control = false; + halbtc8812a1ant_init_coex_dm(btcoexist); + break; + case BTC_DBG_SET_COEX_WIFI_ONLY: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set CoexMode to Wifi Only\n"); + BTC_TRACE(trace_buf); + btcoexist->manual_control = true; + halbtc8812a1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 9); + break; + case BTC_DBG_SET_COEX_BT_ONLY: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set CoexMode to BT only\n"); + BTC_TRACE(trace_buf); + btcoexist->manual_control = true; + halbtc8812a1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + break; + case BTC_DBG_SET_COEX_DEC_BT_PWR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set Dec BT power\n"); + BTC_TRACE(trace_buf); + { + u8 data_len = 4; + u8 buf[6] = {0}; + u8 dec_bt_pwr = 0, pwr_level = 0; + + if (op_len == 2) { + dec_bt_pwr = pdata[0]; + pwr_level = pdata[1]; + + buf[0] = data_len; + buf[1] = 0x3; /* OP_Code */ + buf[2] = 0x2; /* OP_Code_Length */ + + buf[3] = dec_bt_pwr; /* OP_Code_Content */ + buf[4] = pwr_level; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set Dec BT power=%d, pwr_level=%d\n", + dec_bt_pwr, pwr_level); + BTC_TRACE(trace_buf); + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_CTRL_BT_COEX, + (void *)&buf[0]); + } + } + break; + + case BTC_DBG_SET_COEX_BT_AFH_MAP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set BT AFH Map\n"); + BTC_TRACE(trace_buf); + { + u8 data_len = 5; + u8 buf[6] = {0}; + + if (op_len == 3) { + buf[0] = data_len; + buf[1] = 0x5; /* OP_Code */ + buf[2] = 0x3; /* OP_Code_Length */ + + buf[3] = pdata[0]; /* OP_Code_Content */ + buf[4] = pdata[1]; + buf[5] = pdata[2]; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set BT AFH Map = %02x %02x %02x\n", + pdata[0], pdata[1], pdata[2]); + BTC_TRACE(trace_buf); + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_CTRL_BT_COEX, + (void *)&buf[0]); + } + } + break; + + case BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set BT Ignore Wlan Active\n"); + BTC_TRACE(trace_buf); + { + u8 data_len = 3; + u8 buf[6] = {0}; + + if (op_len == 1) { + buf[0] = data_len; + buf[1] = 0x1; /* OP_Code */ + buf[2] = 0x1; /* OP_Code_Length */ + + buf[3] = pdata[0]; /* OP_Code_Content */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set BT Ignore Wlan Active = 0x%x\n", + pdata[0]); + BTC_TRACE(trace_buf); + + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_CTRL_BT_COEX, + (void *)&buf[0]); + } + } + break; + default: + break; + } +} + +#endif + +#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ diff --git a/hal/btc/halbtc8812a1ant.h b/hal/btc/halbtc8812a1ant.h new file mode 100644 index 0000000..08fbad2 --- /dev/null +++ b/hal/btc/halbtc8812a1ant.h @@ -0,0 +1,244 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8812A_SUPPORT == 1) + +/* ******************************************* + * The following is for 8812A 1ANT BT Co-exist definition + * ******************************************* */ +#define BT_AUTO_REPORT_ONLY_8812A_1ANT 1 + +#define BT_INFO_8812A_1ANT_B_FTP BIT(7) +#define BT_INFO_8812A_1ANT_B_A2DP BIT(6) +#define BT_INFO_8812A_1ANT_B_HID BIT(5) +#define BT_INFO_8812A_1ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8812A_1ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8812A_1ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8812A_1ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8812A_1ANT_B_CONNECTION BIT(0) + +#define BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT(0))) ? true : false) + +#define BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT 2 + +#define BT_8812A_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ + +enum bt_info_src_8812a_1ant { + BT_INFO_SRC_8812A_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8812A_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8812A_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8812A_1ANT_MAX +}; + +enum bt_8812a_1ant_bt_status { + BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8812A_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8812A_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8812A_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8812A_1ANT_BT_STATUS_MAX +}; + +enum bt_8812a_1ant_wifi_status { + BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8812A_1ANT_WIFI_STATUS_MAX +}; + +enum bt_8812a_1ant_coex_algo { + BT_8812A_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8812A_1ANT_COEX_ALGO_SCO = 0x1, + BT_8812A_1ANT_COEX_ALGO_HID = 0x2, + BT_8812A_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8812A_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8812A_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8812A_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8812A_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8812A_1ANT_COEX_ALGO_MAX = 0xb, +}; + +struct coex_dm_8812a_1ant { + /* hw setting */ + u8 pre_ant_pos_type; + u8 cur_ant_pos_type; + /* fw mechanism */ + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean auto_tdma_adjust; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + /* sw mechanism */ + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + + u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ + u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ + u16 backup_retry_limit; + u8 backup_ampdu_max_time; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + u32 pre_ra_mask; + u32 cur_ra_mask; + u8 pre_arfr_type; + u8 cur_arfr_type; + u8 pre_retry_limit_type; + u8 cur_retry_limit_type; + u8 pre_ampdu_time_type; + u8 cur_ampdu_time_type; + u32 arp_cnt; + + u8 error_condition; +}; + +struct coex_sta_8812a_1ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + + boolean under_lps; + boolean under_ips; + u32 specific_pkt_period_cnt; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + s8 bt_rssi; + boolean bt_tx_rx_mask; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + boolean c2h_bt_info_req_sent; + u8 bt_info_c2h[BT_INFO_SRC_8812A_1ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_MAX]; + u32 bt_info_query_cnt; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_page; /* Add for win8.1 page out issue */ + boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ + u8 bt_retry_cnt; + u8 bt_info_ext; + u32 pop_event_cnt; + u8 scan_ap_num; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_agg; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_agg; + + boolean cck_lock; + boolean pre_ccklock; + u8 coex_table_type; + + boolean force_lps_on; +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8812a1ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8812a1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); +void ex_halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8812a1ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a1ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8812a1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a1ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8812a1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8812a1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); +void ex_halbtc8812a1ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8812a1ant_dbg_control(IN struct btc_coexist *btcoexist, + IN u8 op_code, IN u8 op_len, IN u8 *pdata); +void ex_halbtc8812a1ant_display_coex_info(IN struct btc_coexist *btcoexist); + +#else +#define ex_halbtc8812a1ant_power_on_setting(btcoexist) +#define ex_halbtc8812a1ant_pre_load_firmware(btcoexist) +#define ex_halbtc8812a1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8812a1ant_init_coex_dm(btcoexist) +#define ex_halbtc8812a1ant_ips_notify(btcoexist, type) +#define ex_halbtc8812a1ant_lps_notify(btcoexist, type) +#define ex_halbtc8812a1ant_scan_notify(btcoexist, type) +#define ex_halbtc8812a1ant_connect_notify(btcoexist, type) +#define ex_halbtc8812a1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8812a1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8812a1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8812a1ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8812a1ant_halt_notify(btcoexist) +#define ex_halbtc8812a1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8812a1ant_coex_dm_reset(btcoexist) +#define ex_halbtc8812a1ant_periodical(btcoexist) +#define ex_halbtc8812a1ant_dbg_control(btcoexist, op_code, op_len, pdata) +#define ex_halbtc8812a1ant_display_coex_info(btcoexist) + +#endif + +#endif diff --git a/hal/btc/halbtc8812a2ant.c b/hal/btc/halbtc8812a2ant.c new file mode 100644 index 0000000..e1e6572 --- /dev/null +++ b/hal/btc/halbtc8812a2ant.c @@ -0,0 +1,5638 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for RTL8812A Co-exist mechanism + * + * History + * 2012/08/22 Cosa first check in. + * 2012/11/14 Cosa Revise for 8812A 2Ant out sourcing. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + + +#if (RTL8812A_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8812a_2ant glcoex_dm_8812a_2ant; +static struct coex_dm_8812a_2ant *coex_dm = &glcoex_dm_8812a_2ant; +static struct coex_sta_8812a_2ant glcoex_sta_8812a_2ant; +static struct coex_sta_8812a_2ant *coex_sta = &glcoex_sta_8812a_2ant; + +const char *const glbt_info_src_8812a_2ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; +/* ************************************************************ + * BtCoex Version Format: + * 1. date : glcoex_ver_date_XXXXX_1ant + * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant + * 3. BtCoexVersion : glcoex_ver_btdesired_XXXXX_1ant + * 4. others : glcoex_ver_XXXXXX_XXXXX_1ant + * + * Variable should be indicated IC and Antenna numbers !!! + * Please strictly follow this order and naming style !!! + * + * ************************************************************ */ +u32 glcoex_ver_date_8812a_2ant = 20160818; +u32 glcoex_ver_8812a_2ant = 0x3c; +u32 glcoex_ver_btdesired_8812a_2ant = 0x3c; +/*1. add coex. log for wifi/BT coex. version*/ + +/* ************************************************************ +* local function proto type if needed +* ************************************************************ +* ************************************************************ +* local function start with halbtc8812a2ant_ +* ************************************************************ */ +u8 halbtc8812a2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_bt_rssi_state; + } + + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + + +u8 halbtc8812a2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_wifi_rssi_state[index]; + } + + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; + + return wifi_rssi_state; +} + + +void halbtc8812a2ant_set_enable_pta(IN struct btc_coexist *btcoexist, + IN boolean enablePTA) +{ + if (enablePTA) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PTA is enable!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PTA is disable!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte(btcoexist, 0x40, 0x00); + + } +} + +void halbtc8812a2ant_enable_pta(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s turn Enable PTA %s\n", + (force_exec ? "force to" : ""), (enable ? "ON" : "OFF")); + BTC_TRACE(trace_buf); + coex_dm->cur_enable_pta = enable; + + if (!force_exec) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], pre_enable_pta = %d, cur_enable_pta = %d!!\n", + coex_dm->pre_enable_pta, coex_dm->cur_enable_pta); + BTC_TRACE(trace_buf); + + if (coex_dm->pre_enable_pta == coex_dm->cur_enable_pta) + return; + } + halbtc8812a2ant_set_enable_pta(btcoexist, enable); + + + coex_dm->pre_enable_pta = coex_dm->cur_enable_pta; +} + +u32 halbtc8812a2ant_decide_ra_mask(IN struct btc_coexist *btcoexist, + IN u32 ra_mask_type) +{ + u32 dis_ra_mask = 0x0; + + switch (ra_mask_type) { + case 0: /* normal mode */ + dis_ra_mask = 0x0; + break; + case 1: /* disable cck 1/2 */ + dis_ra_mask = 0x00000003; + break; + case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ + dis_ra_mask = 0x0001f1f7; + break; + default: + break; + } + + return dis_ra_mask; +} + +void halbtc8812a2ant_update_ra_mask(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 dis_rate_mask) +{ + coex_dm->cur_ra_mask = dis_rate_mask; + + if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) + btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, + &coex_dm->cur_ra_mask); + coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; +} + +void halbtc8812a2ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + boolean wifi_under_b_mode = false; + + coex_dm->cur_arfr_type = type; + + if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { + switch (coex_dm->cur_arfr_type) { + case 0: /* normal mode */ + btcoexist->btc_write_4byte(btcoexist, 0x430, + coex_dm->backup_arfr_cnt1); + btcoexist->btc_write_4byte(btcoexist, 0x434, + coex_dm->backup_arfr_cnt2); + break; + case 1: + btcoexist->btc_get(btcoexist, + BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + if (wifi_under_b_mode) { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x01010101); + } else { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x04030201); + } + break; + default: + break; + } + } + + coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; +} + +void halbtc8812a2ant_retry_limit(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_retry_limit_type = type; + + if (force_exec || + (coex_dm->pre_retry_limit_type != + coex_dm->cur_retry_limit_type)) { + switch (coex_dm->cur_retry_limit_type) { + case 0: /* normal mode */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + coex_dm->backup_retry_limit); + break; + case 1: /* retry limit=8 */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + 0x0808); + break; + default: + break; + } + } + + coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; +} + +void halbtc8812a2ant_ampdu_max_time(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_ampdu_time_type = type; + + if (force_exec || + (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { + switch (coex_dm->cur_ampdu_time_type) { + case 0: /* normal mode */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + coex_dm->backup_ampdu_max_time); + break; + case 1: /* AMPDU timw = 0x38 * 32us */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + 0x38); + break; + default: + break; + } + } + + coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; +} + +void halbtc8812a2ant_limited_tx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, + IN u8 retry_limit_type, IN u8 ampdu_time_type) +{ + u32 dis_ra_mask = 0x0; + + coex_dm->cur_ra_mask_type = ra_mask_type; + dis_ra_mask = halbtc8812a2ant_decide_ra_mask(btcoexist, ra_mask_type); + halbtc8812a2ant_update_ra_mask(btcoexist, force_exec, dis_ra_mask); + + halbtc8812a2ant_auto_rate_fallback_retry(btcoexist, force_exec, + arfr_type); + halbtc8812a2ant_retry_limit(btcoexist, force_exec, retry_limit_type); + halbtc8812a2ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); +} + +void halbtc8812a2ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +void halbtc8812a2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); + BTC_TRACE(trace_buf); + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); +} + + +void halbtc8812a2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ +#if 1 + + coex_sta->crc_ok_cck = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_VHT); +#endif +} + + +void halbtc8812a2ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 data_len = 3; + u8 buf[5] = {0}; + /* 8812a watch btifo to check BT enable/disable + * if(!btcoexist->bt_info.bt_disabled) */ + { + if (!coex_sta->bt_info_query_cnt || + (coex_sta->bt_info_c2h_cnt[BT_INFO_SRC_8812A_2ANT_BT_RSP] + - coex_sta->bt_info_query_cnt) > 2) { + buf[0] = data_len; + buf[1] = 0x1; /* polling enable, 1=enable, 0=disable */ + buf[2] = 0x2; /* polling time in seconds */ + buf[3] = 0x1; /* auto report enable, 1=enable, 0=disable */ + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_INFO, + (void *)&buf[0]); + } + } + coex_sta->bt_info_query_cnt++; +} + +boolean halbtc8812a2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) +{ + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + } + + return false; +} + +void halbtc8812a2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + +#if 1/* (BT_AUTO_REPORT_ONLY_8812A_2ANT == 1) / profile from bt patch */ + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + bt_link_info->acl_busy = coex_sta->acl_busy; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = true; + bt_link_info->bt_link_exist = true; + } +#else /* profile from bt stack */ + bt_link_info->bt_link_exist = stack_info->bt_link_exist; + bt_link_info->sco_exist = stack_info->sco_exist; + bt_link_info->a2dp_exist = stack_info->a2dp_exist; + bt_link_info->pan_exist = stack_info->pan_exist; + bt_link_info->hid_exist = stack_info->hid_exist; + + /* for win-8 stack HID report error */ + if (!stack_info->hid_exist) + stack_info->hid_exist = + coex_sta->hid_exist; /* sync BTInfo with BT firmware and stack */ + /* when stack HID report error, here we use the info from bt fw. */ + if (!stack_info->bt_link_exist) + stack_info->bt_link_exist = coex_sta->bt_link_exist; +#endif + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = true; + else + bt_link_info->sco_only = false; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = true; + else + bt_link_info->a2dp_only = false; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = true; + else + bt_link_info->pan_only = false; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = true; + else + bt_link_info->hid_only = false; +} + +u8 halbtc8812a2ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + struct btc_stack_info *stack_info = &btcoexist->stack_info; + boolean bt_hs_on = false; + u8 algorithm = BT_8812A_2ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 0) { + if (bt_link_info->acl_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ACL Busy only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR; + } + } else if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_2ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_2ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_2ANT_COEX_ALGO_SCO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + if (stack_info->num_of_hid >= 2) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID*2 + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_HID_A2DP; + } + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_SCO_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_SCO_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +void halbtc8812a2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, + IN u8 dac_swing_lvl) +{ + u8 h2c_parameter[1] = {0}; + + /* There are several type of dacswing */ + /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ + h2c_parameter[0] = dac_swing_lvl; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set Dac Swing Level=0x%x\n", + dac_swing_lvl); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], FW write 0x64=0x%x\n", + h2c_parameter[0]); + BTC_TRACE(trace_buf); + + btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); +} + +void halbtc8812a2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN u8 dec_bt_pwr_lvl) +{ + u8 data_len = 4; + u8 buf[6] = {0}; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], decrease Bt Power level = %d\n", + dec_bt_pwr_lvl); + BTC_TRACE(trace_buf); + + buf[0] = data_len; + buf[1] = 0x3; /* OP_Code */ + buf[2] = 0x2; /* OP_Code_Length */ + if (dec_bt_pwr_lvl) + buf[3] = 0x1; /* OP_Code_Content */ + else + buf[3] = 0x0; + buf[4] = dec_bt_pwr_lvl;/* pwr_level */ + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, + (void *)&buf[0]); +} + +void halbtc8812a2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 dec_bt_pwr_lvl) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s Dec BT power level = %d\n", + (force_exec ? "force to" : ""), dec_bt_pwr_lvl); + BTC_TRACE(trace_buf); + + coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; + + if (!force_exec) { + if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) + return; + } + halbtc8812a2ant_set_fw_dec_bt_pwr(btcoexist, + coex_dm->cur_bt_dec_pwr_lvl); + + coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; +} + +void halbtc8812a2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 fw_dac_swing_lvl) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s set FW Dac Swing level = %d\n", + (force_exec ? "force to" : ""), fw_dac_swing_lvl); + BTC_TRACE(trace_buf); + coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; + + if (!force_exec) { + if (coex_dm->pre_fw_dac_swing_lvl == + coex_dm->cur_fw_dac_swing_lvl) + return; + } + + halbtc8812a2ant_set_fw_dac_swing_level(btcoexist, + coex_dm->cur_fw_dac_swing_lvl); + + coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; +} + +void halbtc8812a2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist, + IN boolean rx_rf_shrink_on) +{ + if (rx_rf_shrink_on) { + /* Shrink RF Rx LPF corner */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Shrink RF Rx LPF corner!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, + 0xffffc); + } else { + /* Resume RF Rx LPF corner */ + /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ + if (btcoexist->initilized) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Resume RF Rx LPF corner!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, + 0xfffff, coex_dm->bt_rf_0x1e_backup); + } + } +} + +void halbtc8812a2ant_rf_shrink(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rx_rf_shrink_on) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s turn Rx RF Shrink = %s\n", + (force_exec ? "force to" : ""), + ((rx_rf_shrink_on) ? "ON" : "OFF")); + BTC_TRACE(trace_buf); + coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; + + if (!force_exec) { + if (coex_dm->pre_rf_rx_lpf_shrink == + coex_dm->cur_rf_rx_lpf_shrink) + return; + } + halbtc8812a2ant_set_sw_rf_rx_lpf_corner(btcoexist, + coex_dm->cur_rf_rx_lpf_shrink); + + coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; +} + +void halbtc8812a2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist + *btcoexist, IN boolean low_penalty_ra) +{ + u8 tmp_u1; + + tmp_u1 = btcoexist->btc_read_1byte(btcoexist, 0x4fd); + tmp_u1 |= BIT(0); + if (low_penalty_ra) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Tx rate adaptive, set low penalty!!\n"); + BTC_TRACE(trace_buf); + tmp_u1 &= ~BIT(2); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Tx rate adaptive, set normal!!\n"); + BTC_TRACE(trace_buf); + tmp_u1 |= BIT(2); + } + + btcoexist->btc_write_1byte(btcoexist, 0x4fd, tmp_u1); +} + +void halbtc8812a2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + return; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s turn LowPenaltyRA = %s\n", + (force_exec ? "force to" : ""), + ((low_penalty_ra) ? "ON" : "OFF")); + BTC_TRACE(trace_buf); + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) + return; + } + halbtc8812a2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, + coex_dm->cur_low_penalty_ra); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; +} + +void halbtc8812a2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, + IN u32 level) +{ + u8 val = (u8)level; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Write SwDacSwing = 0x%x\n", + level); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val); +} + +void halbtc8812a2ant_set_sw_full_time_dac_swing(IN struct btc_coexist + *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) +{ + if (sw_dac_swing_on) + halbtc8812a2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl); + else + halbtc8812a2ant_set_dac_swing_reg(btcoexist, 0x18); +} + + +void halbtc8812a2ant_dac_swing(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s turn DacSwing=%s, dac_swing_lvl=0x%x\n", + (force_exec ? "force to" : ""), ((dac_swing_on) ? "ON" : "OFF"), + dac_swing_lvl); + BTC_TRACE(trace_buf); + coex_dm->cur_dac_swing_on = dac_swing_on; + coex_dm->cur_dac_swing_lvl = dac_swing_lvl; + + if (!force_exec) { + if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && + (coex_dm->pre_dac_swing_lvl == + coex_dm->cur_dac_swing_lvl)) + return; + } + delay_ms(30); + halbtc8812a2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, + dac_swing_lvl); + + coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; + coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; +} + +void halbtc8812a2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, + IN boolean adc_back_off) +{ + if (adc_back_off) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB BackOff Level On!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB BackOff Level Off!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1); + } +} + +void halbtc8812a2ant_adc_back_off(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean adc_back_off) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s turn AdcBackOff = %s\n", + (force_exec ? "force to" : ""), + ((adc_back_off) ? "ON" : "OFF")); + BTC_TRACE(trace_buf); + + coex_dm->cur_adc_back_off = adc_back_off; + + if (!force_exec) { + if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) + return; + } + halbtc8812a2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off); + + coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; +} + +void halbtc8812a2ant_set_agc_table(IN struct btc_coexist *btcoexist, + IN boolean agc_table_en) +{ + u8 rssi_adjust_val = 0; + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Agc Table On!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, + 0x28F4B); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, + 0x10AB2); + rssi_adjust_val = 8; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Agc Table Off!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, + 0x2884B); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, + 0x104B2); + } + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); + + /* set rssi_adjust_val for wifi module. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, + &rssi_adjust_val); +} + +void halbtc8812a2ant_agc_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean agc_table_en) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], %s %s Agc Table\n", + (force_exec ? "force to" : ""), + ((agc_table_en) ? "Enable" : "Disable")); + BTC_TRACE(trace_buf); + coex_dm->cur_agc_table_en = agc_table_en; + + if (!force_exec) { + if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) + return; + } + halbtc8812a2ant_set_agc_table(btcoexist, agc_table_en); + + coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; +} + +void halbtc8812a2ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0); + BTC_TRACE(trace_buf); + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4); + BTC_TRACE(trace_buf); + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8); + BTC_TRACE(trace_buf); + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8812a2ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", + (force_exec ? "force to" : ""), val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + BTC_TRACE(trace_buf); + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8812a2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8812a2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + switch (type) { + case 0: + halbtc8812a2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 1: + halbtc8812a2ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 2: + halbtc8812a2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5ffb5ffb, 0xffffff, 0x3); + break; + case 3: + halbtc8812a2ant_coex_table(btcoexist, force_exec, + 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3); + break; + case 4: + halbtc8812a2ant_coex_table(btcoexist, force_exec, + 0xdfffdfff, 0x5fdb5fdb, 0xffffff, 0x3); + break; + case 5: + halbtc8812a2ant_coex_table(btcoexist, force_exec, + 0x5ddd5ddd, 0x5fdb5fdb, 0xffffff, 0x3); + break; + case 6: + halbtc8812a2ant_coex_table(btcoexist, force_exec, + 0x5fff5fff, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 7: + if (coex_sta->scan_ap_num <= 5) + halbtc8812a2ant_coex_table(btcoexist, + force_exec, 0xffffffff, 0xfafafafa, + 0xffffff, 0x3); + else + halbtc8812a2ant_coex_table(btcoexist, + force_exec, 0xffffffff, 0x5a5a5a5a, + 0xffffff, 0x3); + break; + case 8: + halbtc8812a2ant_coex_table(btcoexist, force_exec, + 0x5f5f5f5f, 0x5a5a5a5a, 0xffffff, 0x3); + break; + + default: + break; + } +} + +void halbtc8812a2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 data_len = 3; + u8 buf[5] = {0}; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s BT Ignore Wlan_Act\n", + (enable ? "Enable" : "Disable")); + BTC_TRACE(trace_buf); + + buf[0] = data_len; + buf[1] = 0x1; /* OP_Code */ + buf[2] = 0x1; /* OP_Code_Length */ + if (enable) + buf[3] = 0x1; /* OP_Code_Content */ + else + buf[3] = 0x0; + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, + (void *)&buf[0]); +} + +void halbtc8812a2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s turn Ignore WlanAct %s\n", + (force_exec ? "force to" : ""), (enable ? "ON" : "OFF")); + BTC_TRACE(trace_buf); + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8812a2ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8812a2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if (ap_enable) { + if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], FW for 1Ant AP mode\n"); + BTC_TRACE(trace_buf); + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + } + } + + h2c_parameter[0] = real_byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = real_byte5; + + + coex_dm->ps_tdma_para[0] = real_byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = real_byte5; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PS-TDMA H2C cmd =0x%x%08x\n", + h2c_parameter[0], + h2c_parameter[1] << 24 | h2c_parameter[2] << 16 | + h2c_parameter[3] << 8 | h2c_parameter[4]); + + BTC_TRACE(trace_buf); + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); +} + +void halbtc8812a2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8812a2ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8812a2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8812a2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, + IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, + IN boolean limited_dig, IN boolean bt_lna_constrain) +{ + /* + u32 wifi_bw; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if(BTC_WIFI_BW_HT40 != wifi_bw) + { + if (shrink_rx_lpf) + shrink_rx_lpf = false; + } + */ + + halbtc8812a2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); + /* halbtc8812a2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); */ +} + +void halbtc8812a2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, + IN boolean agc_table_shift, IN boolean adc_back_off, + IN boolean sw_dac_swing, IN u32 dac_swing_lvl) +{ + /* halbtc8812a2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */ + halbtc8812a2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); + halbtc8812a2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, + dac_swing_lvl); +} + +void halbtc8812a2ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) +{ + u8 u8tmp = 0; + + if (init_hwcfg) { + btcoexist->btc_write_4byte(btcoexist, 0x900, 0x00000400); + btcoexist->btc_write_1byte(btcoexist, 0x76d, 0x1); + } else if (wifi_off) { + + } + + /* ext switch setting */ + switch (ant_pos_type) { + case BTC_ANT_WIFI_AT_CPL_MAIN: + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7); + u8tmp &= ~BIT(2); + u8tmp |= BIT(3); + btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp); + break; + case BTC_ANT_WIFI_AT_CPL_AUX: + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7); + u8tmp &= ~BIT(3); + u8tmp |= BIT(2); + btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp); + break; + default: + break; + } +} + +void halbtc8812a2ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + s8 wifi_duration_adjust = 0x0; + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + if (!force_exec) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], pre_ps_tdma_on = %d, cur_ps_tdma_on = %d!!\n", + coex_dm->pre_ps_tdma_on, coex_dm->cur_ps_tdma_on); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], pre_ps_tdma = %d, cur_ps_tdma = %d!!\n", + coex_dm->pre_ps_tdma, coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) + return; + } + + if (coex_sta->scan_ap_num >= 40) + wifi_duration_adjust = -15; + else if (coex_sta->scan_ap_num >= 20) + wifi_duration_adjust = -10; + + /* + if (!coex_sta->force_lps_on) + { + ps_tdma_byte0_val = 0x61; + ps_tdma_byte3_val = 0x11; + ps_tdma_byte4_val = 0x10; + } + + + if ( (type == 3) || (type == 13) || (type == 14) ) + { + ps_tdma_byte4_val = ps_tdma_byte4_val & 0xbf; + + if (!wifi_busy) + ps_tdma_byte4_val = ps_tdma_byte4_val | 0x1; + } + + if (bt_link_info->slave_role == true) + ps_tdma_byte4_val = ps_tdma_byte4_val | 0x1; + + */ + if (turn_on) { + switch (type) { + case 1: + default: /* d1,wb */ + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c, 0x03, 0x11, 0x10); + break; + case 2: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x32, 0x03, 0x11, 0x10); + break; + case 3: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x28, 0x03, 0x11, 0x10); + break; + case 4: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1e, 0x03, 0x11, 0x10); + break; + case 5: /* d1,pb,TXpause */ + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x63, + 0x3c, 0x03, 0x90, 0x10); + break; + case 6: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x63, + 0x32, 0x03, 0x90, 0x10); + break; + case 7: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x63, + 0x28, 0x03, 0x90, 0x10); + break; + case 8: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x63, + 0x1e, 0x03, 0x90, 0x10); + break; + case 9: /* d1,bb */ + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c, 0x03, 0x31, 0x10); + break; + case 10: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x32, 0x03, 0x31, 0x10); + break; + case 11: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x28, 0x03, 0x31, 0x10); + break; + case 12: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1e, 0x03, 0x31, 0x10); + break; + case 13: /* d1,bb,TXpause */ + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c, 0x03, 0x30, 0x10); + break; + case 14: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x32, 0x03, 0x30, 0x10); + break; + case 15: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x28, 0x03, 0x30, 0x10); + break; + case 16: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1e, 0x03, 0x30, 0x10); + break; + case 17: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x3, 0x11, 0x11); + break; + case 18: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x5, 0x5, 0xe1, 0x90); + break; + case 19: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x25, 0xe1, 0x90); + break; + case 20: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x25, 0x60, 0x90); + break; + case 21: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x15, 0x3, 0x70, 0x90); + break; + case 22: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x61, + 0x1a, 0x1a, 0x21, 0x10); + break; + case 23: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1c, 0x03, 0x31, 0x10); + break; + + case 71: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1a, 0x1a, 0xe1, 0x90); + break; + + /* following cases is for wifi rssi low, started from 81 */ + case 80: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, + 0x3c, 0x3, 0x90, 0x50); + break; + case 81: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, + 0x3a + wifi_duration_adjust, 0x3, 0x90, + 0x50); + break; + case 82: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, + 0x30 + wifi_duration_adjust, 0x03, 0x90, + 0x50); + break; + case 83: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, + 0x21, 0x03, 0x90, 0x50); + break; + case 84: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, + 0x15, 0x3, 0x90, 0x50); + break; + case 85: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, + 0x1d, 0x1d, 0x80, 0x50); + break; + case 86: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, + 0x15, 0x15, 0x80, 0x50); + break; + } + } else { + /* disable PS tdma */ + switch (type) { + case 0: /* ANT2PTA, 0x778=0x1 */ + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x8, + 0x0, 0x0, 0x0, 0x0); + break; + case 1: /* ANT2BT, 0x778=3 */ + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x8, 0x0); + delay_ms(5); + halbtc8812a2ant_set_ant_path(btcoexist, + BTC_ANT_WIFI_AT_CPL_AUX, false, false); + break; + case 2: /* ANT2BT, 0x778=3 */ + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x8, 0x0); + delay_ms(5); + halbtc8812a2ant_set_ant_path(btcoexist, + BTC_ANT_WIFI_AT_CPL_MAIN, false, false); + break; + default: + halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x0, 0x0); + break; + } + } + + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; +} + + +void halbtc8812a2ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + + +void halbtc8812a2ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = false; + boolean ap_enable = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if (ap_enable) { + ps_type = BTC_PS_WIFI_NATIVE; + lps_val = 0x0; + rpwm_val = 0x0; + } + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + /* recover to original 32k low power setting */ + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + case BTC_PS_LPS_ON: + halbtc8812a2ant_ps_tdma_check_for_power_save_state( + btcoexist, true); + halbtc8812a2ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + coex_sta->force_lps_on = true; + break; + case BTC_PS_LPS_OFF: + halbtc8812a2ant_ps_tdma_check_for_power_save_state( + btcoexist, false); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + default: + break; + } +} + +void halbtc8812a2ant_coex_all_off(IN struct btc_coexist *btcoexist) +{ + /* fw all off */ + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* sw all off */ + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + + /* hw all off */ + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + /* force to reset coex mechanism */ + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); + halbtc8812a2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0); + + halbtc8812a2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); +} + +void halbtc8812a2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + struct btc_stack_info *stack_info = &btcoexist->stack_info; + static u32 bt_disable_cnt = 0; + boolean bt_active = true, bt_disabled = false; + + /* This function check if bt is disabled */ + + /* only 8812a need to consider if core stack is installed. */ + /*if (!stack_info->hci_version)*/ + /*bt_active = false;*/ + + bt_disabled = btcoexist->bt_info.bt_disabled; + + if (coex_sta->pre_bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->pre_bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->pre_bt_disabled = bt_disabled; + + if (bt_disabled) { + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 2); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + } + } +} + + +void halbtc8812a2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); +} + + +boolean halbtc8812a2ant_is_common_action(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean common = false, wifi_connected = false, wifi_busy = false; + boolean bt_hs_on = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_bt_inquiry(btcoexist); + return true; + } + + if (bt_link_info->sco_exist || bt_link_info->hid_exist) + halbtc8812a2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0); + else + halbtc8812a2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + + if (!wifi_connected) { + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x8); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non-connected idle!!\n"); + BTC_TRACE(trace_buf); + + if ((BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) || + (BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + } else { + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); + } + + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, + false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + + common = true; + } else { + if (BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, + false, false, 0x8); + + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, + 6); + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + + common = true; + } else if (BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status) { + if (bt_hs_on) + return false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, + false, false, 0x8); + + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, + 6); + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + + common = true; + } else { + if (wifi_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); + BTC_TRACE(trace_buf); + common = false; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8812a2ant_limited_rx(btcoexist, + NORMAL_EXEC, false, false, 0x8); + + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 17); + + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, + NORMAL_EXEC, 6); + halbtc8812a2ant_dec_bt_pwr(btcoexist, + NORMAL_EXEC, 0); + halbtc8812a2ant_sw_mechanism1(btcoexist, false, + false, false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, + false, false, 0x18); + common = true; + } + } + } + + return common; +} + +void halbtc8812a2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, + IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) +{ + static s32 up, dn, m, n, wait_count; + s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ + u8 retry_count = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], TdmaDurationAdjust()\n"); + BTC_TRACE(trace_buf); + + coex_dm->auto_tdma_adjust_low_rssi = false; + + if (!coex_dm->auto_tdma_adjust) { + coex_dm->auto_tdma_adjust = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], first run TdmaDurationAdjust()!!\n"); + BTC_TRACE(trace_buf); + { + if (sco_hid) { + if (tx_pause) { + if (max_interval == 1) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 13); + coex_dm->ps_tdma_du_adj_type = + 13; + } else if (max_interval == 2) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (max_interval == 3) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } + } else { + if (max_interval == 1) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = + 9; + } else if (max_interval == 2) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (max_interval == 3) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } + } + } else { + if (tx_pause) { + if (max_interval == 1) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 5); + coex_dm->ps_tdma_du_adj_type = + 5; + } else if (max_interval == 2) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (max_interval == 3) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } + } else { + if (max_interval == 1) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = + 1; + } else if (max_interval == 2) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (max_interval == 3) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } + } + } + } + /* ============ */ + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } else { + /* acquire the BT TRx retry count from BT_Info byte2 */ + retry_count = coex_sta->bt_retry_cnt; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], retry_count = %d\n", + retry_count); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_count=%d\n", + up, dn, m, n, wait_count); + BTC_TRACE(trace_buf); + + result = 0; + wait_count++; + + if (retry_count == + 0) { /* no retry in the last 2-second duration */ + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if (up >= n) { /* if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration */ + wait_count = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Increase wifi duration!!\n"); + BTC_TRACE(trace_buf); + } + } else if (retry_count <= + 3) { /* <=3 retry in the last 2-second duration */ + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) { /* if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration */ + if (wait_count <= 2) + m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ + else + m = 1; + + if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Decrease wifi duration for retry_counter<3!!\n"); + BTC_TRACE(trace_buf); + } + } else { /* retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration */ + if (wait_count == 1) + m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ + else + m = 1; + + if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Decrease wifi duration for retry_counter>3!!\n"); + BTC_TRACE(trace_buf); + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], max Interval = %d\n", + max_interval); + BTC_TRACE(trace_buf); + + if (max_interval == 1) { + if (tx_pause) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], TxPause = 1\n"); + BTC_TRACE(trace_buf); + + if (coex_dm->cur_ps_tdma == 1) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 5); + coex_dm->ps_tdma_du_adj_type = 5; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 6); + coex_dm->ps_tdma_du_adj_type = 6; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 4) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 8); + coex_dm->ps_tdma_du_adj_type = 8; + } + if (coex_dm->cur_ps_tdma == 9) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 13); + coex_dm->ps_tdma_du_adj_type = 13; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + coex_dm->ps_tdma_du_adj_type = 14; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 16); + coex_dm->ps_tdma_du_adj_type = 16; + } + + if (result == -1) { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 8); + coex_dm->ps_tdma_du_adj_type = + 8; + } else if (coex_dm->cur_ps_tdma == 13) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 16); + coex_dm->ps_tdma_du_adj_type = + 16; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 8) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 5); + coex_dm->ps_tdma_du_adj_type = + 5; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 13); + coex_dm->ps_tdma_du_adj_type = + 13; + } + } + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], TxPause = 0\n"); + BTC_TRACE(trace_buf); + + if (coex_dm->cur_ps_tdma == 5) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 1); + coex_dm->ps_tdma_du_adj_type = 1; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 8) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 4); + coex_dm->ps_tdma_du_adj_type = 4; + } + if (coex_dm->cur_ps_tdma == 13) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 10); + coex_dm->ps_tdma_du_adj_type = 10; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 12); + coex_dm->ps_tdma_du_adj_type = 12; + } + + if (result == -1) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 4); + coex_dm->ps_tdma_du_adj_type = + 4; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 12); + coex_dm->ps_tdma_du_adj_type = + 12; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 4) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = + 1; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = + 9; + } + } + } + } else if (max_interval == 2) { + if (tx_pause) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], TxPause = 1\n"); + BTC_TRACE(trace_buf); + + if (coex_dm->cur_ps_tdma == 1) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 6); + coex_dm->ps_tdma_du_adj_type = 6; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 6); + coex_dm->ps_tdma_du_adj_type = 6; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 4) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 8); + coex_dm->ps_tdma_du_adj_type = 8; + } + if (coex_dm->cur_ps_tdma == 9) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + coex_dm->ps_tdma_du_adj_type = 14; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + coex_dm->ps_tdma_du_adj_type = 14; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 16); + coex_dm->ps_tdma_du_adj_type = 16; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 8); + coex_dm->ps_tdma_du_adj_type = + 8; + } else if (coex_dm->cur_ps_tdma == 13) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 16); + coex_dm->ps_tdma_du_adj_type = + 16; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 8) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } + } + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], TxPause = 0\n"); + BTC_TRACE(trace_buf); + + if (coex_dm->cur_ps_tdma == 5) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 8) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 4); + coex_dm->ps_tdma_du_adj_type = 4; + } + if (coex_dm->cur_ps_tdma == 13) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 10); + coex_dm->ps_tdma_du_adj_type = 10; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 10); + coex_dm->ps_tdma_du_adj_type = 10; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 12); + coex_dm->ps_tdma_du_adj_type = 12; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 4); + coex_dm->ps_tdma_du_adj_type = + 4; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 12); + coex_dm->ps_tdma_du_adj_type = + 12; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 4) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } + } + } + } else if (max_interval == 3) { + if (tx_pause) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], TxPause = 1\n"); + BTC_TRACE(trace_buf); + + if (coex_dm->cur_ps_tdma == 1) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 4) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 8); + coex_dm->ps_tdma_du_adj_type = 8; + } + if (coex_dm->cur_ps_tdma == 9) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 16); + coex_dm->ps_tdma_du_adj_type = 16; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 8); + coex_dm->ps_tdma_du_adj_type = + 8; + } else if (coex_dm->cur_ps_tdma == 13) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 16); + coex_dm->ps_tdma_du_adj_type = + 16; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 8) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } + } + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], TxPause = 0\n"); + BTC_TRACE(trace_buf); + + if (coex_dm->cur_ps_tdma == 5) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 8) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 4); + coex_dm->ps_tdma_du_adj_type = 4; + } + if (coex_dm->cur_ps_tdma == 13) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8812a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 12); + coex_dm->ps_tdma_du_adj_type = 12; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 4); + coex_dm->ps_tdma_du_adj_type = + 4; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 12); + coex_dm->ps_tdma_du_adj_type = + 12; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 4) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8812a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } + } + } + } + } + + /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ + /* then we have to adjust it back to the previous record one. */ + if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { + boolean scan = false, link = false, roam = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", + coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + if (!scan && !link && !roam) + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + coex_dm->ps_tdma_du_adj_type); + else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); + BTC_TRACE(trace_buf); + } + } +} + +/* ****************** + * pstdma for wifi rssi low + * ****************** */ +void halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + IN struct btc_coexist *btcoexist/* , */ /* IN u8 wifi_status */) +{ + static s32 up, dn, m, n, wait_count; + s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ + u8 retry_count = 0, bt_info_ext; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low()\n"); + BTC_TRACE(trace_buf); +#if 0 + if ((BT_8812A_2ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == + wifi_status) || + (BT_8812A_2ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) || + (BT_8812A_2ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT == + wifi_status)) { + if (coex_dm->cur_ps_tdma != 81 && + coex_dm->cur_ps_tdma != 82 && + coex_dm->cur_ps_tdma != 83 && + coex_dm->cur_ps_tdma != 84) { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 82); + coex_dm->ps_tdma_du_adj_type = 82; + + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } + return; + } +#endif + coex_dm->auto_tdma_adjust = false; + + retry_count = coex_sta->bt_retry_cnt; + bt_info_ext = coex_sta->bt_info_ext; + + if (!coex_dm->auto_tdma_adjust_low_rssi) { + coex_dm->auto_tdma_adjust_low_rssi = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], first run TdmaDurationAdjustForWifiRssiLow()!!\n"); + BTC_TRACE(trace_buf); + + if (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 83); + coex_dm->ps_tdma_du_adj_type = 83; + } else { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 82); + coex_dm->ps_tdma_du_adj_type = 82; + } + /* ============ */ + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } else { + /* acquire the BT TRx retry count from BT_Info byte2 + * retry_count = coex_sta->bt_retry_cnt; + * bt_info_ext = coex_sta->bt_info_ext; */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], retry_count = %d\n", + retry_count); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_count=%d\n", + up, dn, m, n, wait_count); + BTC_TRACE(trace_buf); + result = 0; + wait_count++; + + if ((coex_sta->low_priority_tx) > 1050 || + (coex_sta->low_priority_rx) > 1250) + retry_count++; + + if (retry_count == + 0) { /* no retry in the last 2-second duration */ + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if (up >= n) { /* if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration */ + wait_count = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Increase wifi duration!!\n"); + BTC_TRACE(trace_buf); + } + } else if (retry_count <= + 3) { /* <=3 retry in the last 2-second duration */ + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) { /* if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration */ + if (wait_count <= 2) + m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ + else + m = 1; + + if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Decrease wifi duration for retry_counter<3!!\n"); + BTC_TRACE(trace_buf); + } + } else { /* retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration */ + if (wait_count == 1) + m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ + else + m = 1; + + if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Decrease wifi duration for retry_counter>3!!\n"); + BTC_TRACE(trace_buf); + } + + if (result == -1) { + /* + if( (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) && + ((coex_dm->cur_ps_tdma == 81) ||(coex_dm->cur_ps_tdma == 82)) ) + { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 84); + coex_dm->ps_tdma_du_adj_type = 84; + } + */ + if (coex_dm->cur_ps_tdma == 80) { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 82); + coex_dm->ps_tdma_du_adj_type = 82; + } else if (coex_dm->cur_ps_tdma == 81) { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 82); + coex_dm->ps_tdma_du_adj_type = 82; + } else if (coex_dm->cur_ps_tdma == 82) { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 83); + coex_dm->ps_tdma_du_adj_type = 83; + } else if (coex_dm->cur_ps_tdma == 83) { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 84); + coex_dm->ps_tdma_du_adj_type = 84; + } + } else if (result == 1) { + /* + if( (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) && + ((coex_dm->cur_ps_tdma == 81) ||(coex_dm->cur_ps_tdma == 82)) ) + { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 83); + coex_dm->ps_tdma_du_adj_type = 83; + } + */ + if (coex_dm->cur_ps_tdma == 84) { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 83); + coex_dm->ps_tdma_du_adj_type = 83; + } else if (coex_dm->cur_ps_tdma == 83) { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 82); + coex_dm->ps_tdma_du_adj_type = 82; + } else if (coex_dm->cur_ps_tdma == 82) { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 81); + coex_dm->ps_tdma_du_adj_type = 81; + } else if ((coex_dm->cur_ps_tdma == 81) && + ((coex_sta->scan_ap_num <= 5))) { + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 81); + coex_dm->ps_tdma_du_adj_type = 81; + } + } + + if (coex_dm->cur_ps_tdma != 80 && + coex_dm->cur_ps_tdma != 81 && + coex_dm->cur_ps_tdma != 82 && + coex_dm->cur_ps_tdma != 83 && + coex_dm->cur_ps_tdma != 84) { + /* recover to previous adjust type */ + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + coex_dm->ps_tdma_du_adj_type); + } + } +} + +void halbtc8812a2ant_get_bt_rssi_threshold(IN struct btc_coexist *btcoexist, + IN u8 *pThres0, IN u8 *pThres1) +{ + u8 ant_type; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &ant_type); + + + switch (ant_type) { + case BTC_ANT_TYPE_0: + *pThres0 = 100; + *pThres1 = 100; + break; + case BTC_ANT_TYPE_1: + *pThres0 = 34; + *pThres1 = 42; + break; + case BTC_ANT_TYPE_2: + *pThres0 = 34; + *pThres1 = 42; + break; + case BTC_ANT_TYPE_3: + *pThres0 = 34; + *pThres1 = 42; + break; + case BTC_ANT_TYPE_4: + *pThres0 = 34; + *pThres1 = 42; + break; + default: + break; + } +} + + + +void halbtc8812a2ant_action_sco(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, + bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + + /* halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); */ + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + + wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); + + /* power save state */ + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* coex table */ + if (BTC_RSSI_LOW(bt_rssi_state)) + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + else + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + /* pstdma */ + if (BTC_RSSI_LOW(bt_rssi_state)) + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); + else + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); + + /* decrease BT power */ + if (BTC_RSSI_LOW(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + else if (BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); + + /* limited Rx */ + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + /* fw dac swing level */ + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + true, 0x6); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + true, 0x6); + } + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + true, 0x6); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + true, 0x6); + } + } +} + +void halbtc8812a2ant_action_sco_hid(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, + bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + /* halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); */ + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + + wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); + + /* power save state */ + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* coex table */ + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + /* pstdma */ + if (BTC_RSSI_LOW(bt_rssi_state)) + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); + else + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); + + /* decrease BT power */ + if (BTC_RSSI_LOW(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + else if (BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); + + /* limited Rx */ + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8); + + /* fw dac swing level */ + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x6); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x6); + } + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x6); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x6); + } + } +} + +void halbtc8812a2ant_action_hid(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, + bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 anttype = 0; + + + btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype); + + + /* halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); + * bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, bt_thresh1); */ + + wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); + + + if (anttype == 0) { /* ANTTYPE = 0 92E 2ant with SPDT */ + /* power save state & pstdma & coex table */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (anttype == + 1) { /* 92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation */ + /* power save state & pstdma & coex table */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (anttype == + 2) { /* ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation */ + /* power save state & pstdma & coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & shielding room */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, 9); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + } else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & noisy environment */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, 9); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + } else { /* WIFI RSSI || BT RSSI == low */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, 9); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + } + } else if (anttype == + 3) { /* ANTTYPE = 3, 92E 3ant with good ant. isolation */ + /* power save state & pstdma & coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & shielding room */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 1); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + } else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & noisy environment */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 1); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + } else { /* WIFI RSSI || BT RSSI == low */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 1); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + } + } else { /* ANTTYPE = 4 for test */ + /* power save state & pstdma & coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & shielding room */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & noisy environment */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } else { /* WIFI RSSI || BT RSSI == low */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } + } + + + /* power save state */ + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* coex table */ + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + /* pstdma */ + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + + /* decrease BT power */ + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* limited Rx */ + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + /* fw dac swing level */ + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ +void halbtc8812a2ant_action_a2dp(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, + bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 anttype = 0; + boolean ap_enable = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype); + + /* halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); + * bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, bt_thresh1); */ + + wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); + + /* anttype = 4; */ + + if (anttype == 0) { /* ANTTYPE = 0 92E 2ant with SPDT */ + + if (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A) { + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 0); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) { + /* WIFI RSSI = high & BT RSSI = high & shielding room */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } else { /* WIFI RSSI || BT RSSI == low */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } + } + + /* power save state & pstdma & coex table + * + if(BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) + { + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + } + else if (BTC_RSSI_HIGH(wifi_rssi_state)&&(!BTC_RSSI_LOW(bt_rssi_state)) && (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) + { + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } + else + { + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + } + */ + } else if (anttype == + 1) { /* 92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation */ + /* power save state & pstdma & coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & shielding room */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, + false, 1); /* shielding room */ + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & noisy environment */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 1); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + } else { /* WIFI RSSI || BT RSSI == low */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } + + } else if (anttype == + 2) { /* ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation */ + /* power save state & pstdma & coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & shielding room */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, + false, 1); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 5); + } else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & noisy environment */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 1); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + } else { /* WIFI RSSI || BT RSSI == low */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } + } else if (anttype == + 3) { /* ANTTYPE = 3, 92E 3ant with good ant. isolation */ + /* power save state & pstdma & coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & shielding room */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 1); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + } else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & noisy environment */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 1); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + } else { /* WIFI RSSI || BT RSSI == low */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 1); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + } + } else { /* ANTTYPE = 4 for test */ + /* power save state & pstdma & coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & shielding room */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & noisy environment */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } else { /* WIFI RSSI || BT RSSI == low */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } + } + + /* decrease BT power */ + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* decrease BT power + * + if(BTC_RSSI_LOW(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else if (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); + */ + /* limited Rx */ + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + /* fw dac swing level */ + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + + /* sw mechanism */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8812a2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, + bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + /* halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); */ + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + + wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); + + /* power save state */ + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + + /* pstdma */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, false, + 2); + else + halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, true, 2); + + /* decrease BT power */ + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + /* + + if(BTC_RSSI_LOW(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); + */ + /* limited Rx */ + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + /* fw dac swing level */ + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + + /* sw mechanism */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + true, 0x6); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + true, 0x6); + } + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + true, 0x6); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + true, 0x6); + } + } +} + +void halbtc8812a2ant_action_pan_edr(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, + bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + + + halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, + &bt_thresh1); + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + + wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ + + /* power save state */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + + /* coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + /* pstdma */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); + else + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85); + + /* decrease BT power */ + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* limited Rx */ + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + /* fw dac swing level */ + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + + /* sw mechanism */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +/* PAN(HS) only */ +void halbtc8812a2ant_action_pan_hs(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, + bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + + wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); + + /* power save state */ + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* coex table */ + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + + /* pstdma */ + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + + /* decrease BT power */ + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* + + if(BTC_RSSI_LOW(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); + */ + /* limited Rx */ + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + /* fw dac swing level */ + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +/* PAN(EDR)+A2DP */ +void halbtc8812a2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, + bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, + &bt_thresh1); + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + + wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ + + /* power save state */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + + /* coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + /* pstdma */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, false, + 3); + else { + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); + } + + /* decrease BT power */ + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* limited Rx */ + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + /* fw dac swing level */ + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + + +void halbtc8812a2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, + bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + + halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, + &bt_thresh1); + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + + wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ + + /* power save state */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else if (BTC_RSSI_LOW(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + + /* coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + else if (BTC_RSSI_LOW(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + else + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + /* pstdma */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); + else if (BTC_RSSI_LOW(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); + else + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85); + + /* decrease BT power */ + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* + + if(BTC_RSSI_LOW(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); + */ + /* limited Rx */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x8); + else if (BTC_RSSI_LOW(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x8); + else + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, + 0x8); + + /* fw dac swing level */ + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +/* HID+A2DP+PAN(EDR) */ +void halbtc8812a2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, + bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, + &bt_thresh1); + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + + wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ + + /* power save state */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else if (BTC_RSSI_LOW(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + + /* coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + else if (BTC_RSSI_LOW(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + else + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + /* pstdma */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, false, 3); + else if (BTC_RSSI_LOW(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 3); + else { + coex_dm->auto_tdma_adjust = false; + halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); + } + + /* decrease BT power */ + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + /* + + if(BTC_RSSI_LOW(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); + */ + /* limited Rx */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x8); + else if (BTC_RSSI_LOW(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x8); + else + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, + 0x8); + + + /* fw dac swing level */ + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8812a2ant_action_hid_a2dp_pan_hs(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, + bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 bt_thresh0 = 0, bt_thresh1 = 0; + + halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, + &bt_thresh1); + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, + bt_thresh1); + + + wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ + + /* power save state */ + halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + else if (BTC_RSSI_LOW(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + else + halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + /* pstdma */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, false, 2); + else if (BTC_RSSI_LOW(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 2); + else + halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 2); + + /* decrease BT power */ + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* + + if(BTC_RSSI_LOW(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); + */ + /* limited Rx */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x8); + else if (BTC_RSSI_LOW(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state))) + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x8); + else + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, + 0x8); + + /* fw dac swing level */ + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8812a2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, + bt_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_bw; + u8 anttype = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype); + + + /* halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); + * bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, bt_thresh1); */ + + wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, + 0); + bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); + + if (anttype == 0) { /* ANTTYPE = 0 92E 2ant with SPDT */ + /* power save state & pstdma & coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, + 83); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + + } else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 0); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + } else { + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, + 83); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + } + } else if (anttype == + 1) { /* 92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation */ + /* power save state & pstdma & coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, + true, 2); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + } else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 0); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + } else { + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, + 83); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + } + } else if (anttype == + 2) { /* ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation */ + /* power save state & pstdma & coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & shielding room */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, + true, 2); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + } else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & noisy environment */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 0); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + } else { /* WIFI RSSI || BT RSSI == low */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, + 83); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + } + } else if (anttype == + 3) { /* ANTTYPE = 3, 92E 3ant with good ant. isolation */ + /* power save state & pstdma & coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & shielding room */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 1); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + } else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & noisy environment */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 1); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + } else { /* WIFI RSSI || BT RSSI == low */ + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 1); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + } + } else { /* ANTTYPE = 4 for test */ + /* power save state & pstdma & coex table */ + if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & shielding room */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } else if (BTC_RSSI_HIGH(wifi_rssi_state) && + (!BTC_RSSI_LOW(bt_rssi_state)) && + (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { + /* WIFI RSSI = high & BT RSSI = high & noisy environment */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } else { /* WIFI RSSI || BT RSSI == low */ + halbtc8812a2ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( + btcoexist); + halbtc8812a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 7); + } + } + + /* decrease BT power */ + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* + + if(BTC_RSSI_LOW(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else if (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A) + halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); + */ + /* limited Rx */ + halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + /* fw dac swing level */ + halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if (BTC_RSSI_HIGH(wifi_rssi_state)) { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8812a2ant_coex_under_5g(IN struct btc_coexist *btcoexist) +{ + halbtc8812a2ant_coex_all_off(btcoexist); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Under 5G, force set BT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true); +} +/* **************************************************** */ +void halbtc8812a2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + boolean wifi_under_5g = false; + u8 algorithm = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_coex_under_5g(btcoexist); + return; + } + + + algorithm = halbtc8812a2ant_action_algorithm(btcoexist); + if (coex_sta->c2h_bt_inquiry_page && + (BT_8812A_2ANT_COEX_ALGO_PANHS != algorithm)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_bt_inquiry(btcoexist); + return; + } + + coex_dm->cur_algorithm = algorithm; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", + coex_dm->cur_algorithm); + BTC_TRACE(trace_buf); + + if (halbtc8812a2ant_is_common_action(btcoexist)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant common.\n"); + BTC_TRACE(trace_buf); + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + } else { + if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", + coex_dm->pre_algorithm, coex_dm->cur_algorithm); + BTC_TRACE(trace_buf); + coex_dm->auto_tdma_adjust = false; + coex_dm->auto_tdma_adjust_low_rssi = false; + } + switch (coex_dm->cur_algorithm) { + case BT_8812A_2ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_sco(btcoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_SCO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = SCO+HID.\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_sco_hid(btcoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID.\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_hid(btcoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_a2dp(btcoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_a2dp_pan_hs(btcoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_pan_edr(btcoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_pan_hs(btcoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_pan_edr_a2dp(btcoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_pan_edr_hid(btcoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_hid_a2dp_pan_edr( + btcoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_hid_a2dp_pan_hs( + btcoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_action_hid_a2dp(btcoexist); + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_coex_all_off(btcoexist); + break; + } + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + } + +} + +void halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean back_up) +{ + u8 u8tmp = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 2Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + if (back_up) { + /* backup rf 0x1e value */ + coex_dm->bt_rf_0x1e_backup = + btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, + 0xfffff); + + coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, + 0x430); + coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, + 0x434); + coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( + btcoexist, 0x42a); + coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( + btcoexist, 0x456); + } + + /* ant sw control to BT */ + halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, true, + false); + + /* 0x790[5:0]=0x5 */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); + u8tmp &= 0xc0; + u8tmp |= 0x5; + btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); + + /* PTA parameter */ + btcoexist->btc_write_1byte(btcoexist, 0x6cc, 0x0); + btcoexist->btc_write_4byte(btcoexist, 0x6c8, 0xffff); + btcoexist->btc_write_4byte(btcoexist, 0x6c4, 0x55555555); + btcoexist->btc_write_4byte(btcoexist, 0x6c0, 0x55555555); + + /* coex parameters */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + + /* enable counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); + + /* disable PTA to avoid BT insn't on */ + btcoexist->btc_write_1byte(btcoexist, 0x40, 0x00); + + /* bt clock related */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x4); + u8tmp |= BIT(7); + btcoexist->btc_write_1byte(btcoexist, 0x4, u8tmp); + + /* bt clock related */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); + u8tmp |= BIT(1); + btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); + + /* Give bt_coex_supported_version the default value */ + coex_sta->bt_coex_supported_version = 0; + +} + +/* ************************************************************ + * work around function start with wa_halbtc8812a2ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8812a2ant_ + * ************************************************************ */ +void ex_halbtc8812a2ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ +} + +void ex_halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8812a2ant_init_hw_config(btcoexist, true); +} + +void ex_halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + halbtc8812a2ant_init_coex_dm(btcoexist); +} + + +void ex_halbtc8812a2ant_pta_off_on_notify(IN struct btc_coexist *btcoexist, + IN u8 bt_status) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BToff/on notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_BT_OFF == bt_status) { + /* PTA off */ + btcoexist->bt_info.bt_disabled = true; + halbtc8812a2ant_enable_pta(btcoexist, FORCE_EXEC, false); + + } else { + /* PTA on */ + btcoexist->bt_info.bt_disabled = false; + halbtc8812a2ant_enable_pta(btcoexist, FORCE_EXEC, true); + } + +} + + +void ex_halbtc8812a2ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_stack_info *stack_info = &btcoexist->stack_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u16 u16tmp[4]; + u32 u32tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + u32 phyver = 0; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", + "Ant PG number/ Ant mechanism:", + board_info->pg_ant_num, board_info->btdm_ant_num); + CL_PRINTF(cli_buf); + +#if 0 + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Antenna type:", + board_info->ant_type); + CL_PRINTF(cli_buf); +#endif + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", + "BT stack/ hci ext ver", + ((stack_info->profile_notified) ? "Yes" : "No"), + stack_info->hci_version); + CL_PRINTF(cli_buf); + + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8812a_2ant, glcoex_ver_8812a_2ant, + glcoex_ver_btdesired_8812a_2ant, bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : (bt_coex_ver >= + glcoex_ver_btdesired_8812a_2ant ? "Match" : + "Mis-Match"))); + CL_PRINTF(cli_buf); + + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d", + "W_FW/ B_FW/ Phy", + fw_ver, bt_patch_ver, phyver); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "Wifi channel informed to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", + "BT [status/ rssi/ retryCnt]", + ((btcoexist->bt_info.bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") + : ((BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi, coex_sta->bt_retry_cnt); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", + "SCO/HID/PAN/A2DP", + bt_link_info->sco_exist, bt_link_info->hid_exist, + bt_link_info->pan_exist, bt_link_info->a2dp_exist); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); + + bt_info_ext = coex_sta->bt_info_ext; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "BT Info A2DP rate", + (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); + CL_PRINTF(cli_buf); + + for (i = 0; i < BT_INFO_SRC_8812A_2ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8812a_2ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + /* Sw mechanism */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Sw mechanism]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", + "SM1[ShRf/ LpRA/ LimDig]", + coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, + coex_dm->limited_dig); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", + "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", + coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, + coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Rate Mask", + btcoexist->bt_info.ra_mask); + CL_PRINTF(cli_buf); + + /* Fw mechanism */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Fw mechanism]============"); + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d/%d)", + "PS TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + coex_dm->auto_tdma_adjust, + coex_dm->auto_tdma_adjust_low_rssi); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", + "DecBtPwr/ IgnWlanAct", + coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act); + CL_PRINTF(cli_buf); + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", + "RF-A, 0x1e initVal", + coex_dm->bt_rf_0x1e_backup); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", + "backup ARFR1/ARFR2/RL/AMaxTime", + coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2, + coex_dm->backup_retry_limit, + coex_dm->backup_ampdu_max_time); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); + u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", + "0x430/0x434/0x42a/0x456", + u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x ", + "0x778 (W_Act)/ 0x6cc (CoTab Sel)", + u8tmp[0], u8tmp[1]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x8db); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xc5b); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x8db(ADC)/0xc5b[29:25](DAC)", + ((u8tmp[0] & 0x60) >> 5), ((u8tmp[1] & 0x3e) >> 1)); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcb3); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb7); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0xcb3/ 0xcb7", + u8tmp[0], u8tmp[1]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x974); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x40/ 0x4c[24:23]/ 0x974", + u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u32tmp[1]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x550(bcn ctrl)/0x522", + u32tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa0a); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0xc50(DIG)/0xa0a(CCK-TH)", + u32tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_CCK); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11n-agg", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_Err CCK/11g/11n/11n-agg", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", + u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(high-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x774(low-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx); + CL_PRINTF(cli_buf); +#if (BT_AUTO_REPORT_ONLY_8812A_2ANT == 1) + halbtc8812a2ant_monitor_bt_ctr(btcoexist); +#endif + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +void ex_halbtc8812a2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + boolean wifi_under_5g = false; + + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + + coex_sta->under_ips = true; + halbtc8812a2ant_coex_all_off(btcoexist); + halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, + false, true); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS notify, force set BT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + + halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + ex_halbtc8812a2ant_media_status_notify(btcoexist, + BTC_MEDIA_DISCONNECT); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + + coex_sta->under_ips = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, + &wifi_under_5g); + if (!wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS notify, force set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + + halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, + false); + } + } +} + +void ex_halbtc8812a2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + + coex_sta->under_lps = true; + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + + coex_sta->under_lps = false; + } +} + +void ex_halbtc8812a2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (BTC_SCAN_START == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify\n"); + BTC_TRACE(trace_buf); + } else if (BTC_SCAN_FINISH == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + } +} + +void ex_halbtc8812a2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (BTC_ASSOCIATE_START == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify\n"); + BTC_TRACE(trace_buf); + } else if (BTC_ASSOCIATE_FINISH == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify\n"); + BTC_TRACE(trace_buf); + } +} + +void ex_halbtc8812a2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 data_len = 5; + u8 buf[6] = {0}; + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm || + btcoexist->bt_info.bt_disabled) + return; + + if (BTC_MEDIA_CONNECT == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + } + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + h2c_parameter[0] = 0x1; + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + buf[0] = data_len; + buf[1] = 0x5; /* OP_Code */ + buf[2] = 0x3; /* OP_Code_Length */ + buf[3] = h2c_parameter[0]; /* OP_Code_Content */ + buf[4] = h2c_parameter[1]; + buf[5] = h2c_parameter[2]; + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, + (void *)&buf[0]); +} + +void ex_halbtc8812a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (type == BTC_PACKET_DHCP) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], DHCP Packet notify\n"); + BTC_TRACE(trace_buf); + } +} + +void ex_halbtc8812a2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 bt_info = 0; + u8 i, rsp_source = 0; + boolean bt_busy = false, limited_dig = false; + boolean wifi_connected = false, wifi_under_5g = false; + + coex_sta->c2h_bt_info_req_sent = false; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8812A_2ANT_MAX) + rsp_source = BT_INFO_SRC_8812A_2ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + if (i == 1) + bt_info = tmp_buf[i]; + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + if (BT_INFO_SRC_8812A_2ANT_WIFI_FW != rsp_source) { + coex_sta->bt_retry_cnt = /* [3:0] */ + coex_sta->bt_info_c2h[rsp_source][2] & 0xf; + + coex_sta->bt_rssi = + coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; + + coex_sta->bt_info_ext = + coex_sta->bt_info_c2h[rsp_source][4]; + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + if (wifi_connected) + ex_halbtc8812a2ant_media_status_notify( + btcoexist, BTC_MEDIA_CONNECT); + else + ex_halbtc8812a2ant_media_status_notify( + btcoexist, BTC_MEDIA_DISCONNECT); + } + + if ((coex_sta->bt_info_ext & BIT(3)) && !wifi_under_5g) { + /* BT already ignored WlanAct */ + if (!btcoexist->manual_control && + !btcoexist->stop_coex_dm) { + if (!coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_ignore_wlan_act( + btcoexist, FORCE_EXEC, false); + } + } + } else { + /* BT already NOT ignore Wlan active, do nothing here. */ + + if (coex_sta->under_ips) { + /* work around for 8812a combo hw bug => when IPS, wlanAct is always high. */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS, set BT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8812a2ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, true); + } + } + } + + /* check BIT2 first ==> check if bt is under inquiry or page scan */ + if (bt_info & BT_INFO_8812A_2ANT_B_INQ_PAGE) + coex_sta->c2h_bt_inquiry_page = true; + else + coex_sta->c2h_bt_inquiry_page = false; + + /* set link exist status */ + if (!(bt_info & BT_INFO_8812A_2ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + coex_sta->acl_busy = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (bt_info & BT_INFO_8812A_2ANT_B_FTP) + coex_sta->pan_exist = true; + else + coex_sta->pan_exist = false; + if (bt_info & BT_INFO_8812A_2ANT_B_A2DP) + coex_sta->a2dp_exist = true; + else + coex_sta->a2dp_exist = false; + if (bt_info & BT_INFO_8812A_2ANT_B_HID) + coex_sta->hid_exist = true; + else + coex_sta->hid_exist = false; + if (bt_info & BT_INFO_8812A_2ANT_B_SCO_ESCO) + coex_sta->sco_exist = true; + else + coex_sta->sco_exist = false; + if (bt_info & BT_INFO_8812A_2ANT_B_ACL_BUSY) + coex_sta->acl_busy = true; + else + coex_sta->acl_busy = false; + + } + + halbtc8812a2ant_update_bt_link_info(btcoexist); + + if (!(bt_info & BT_INFO_8812A_2ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info == + BT_INFO_8812A_2ANT_B_CONNECTION) { /* connection exists but no busy */ + coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + BTC_TRACE(trace_buf); + } else if ((bt_info & BT_INFO_8812A_2ANT_B_SCO_ESCO) || + (bt_info & BT_INFO_8812A_2ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info & BT_INFO_8812A_2ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + BTC_TRACE(trace_buf); + } + + if ((BT_8812A_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8812A_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { + bt_busy = true; + if (!wifi_under_5g) + limited_dig = true; + } else { + bt_busy = false; + limited_dig = false; + } + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + coex_dm->limited_dig = limited_dig; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); + + halbtc8812a2ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8812a2ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, false, + true); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Halt notify, force set BT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + + halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + ex_halbtc8812a2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + + /* 0x522=0xff, pause tx */ + btcoexist->btc_write_1byte(btcoexist, 0x522, 0xff); + /* 0x40[7:6]=2'b01, modify BT mode. */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0xc0, 0x2); + /* PTA off. */ +#ifndef CONFIG_PCI_HCI + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x0); +#endif +} + +void ex_halbtc8812a2ant_periodical(IN struct btc_coexist *btcoexist) +{ + static u8 dis_ver_info_cnt = 0; + u32 fw_ver = 0, bt_patch_ver = 0; + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_stack_info *stack_info = &btcoexist->stack_info; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ==========================Periodical===========================\n"); + BTC_TRACE(trace_buf); + + if (dis_ver_info_cnt <= 5) { + dis_ver_info_cnt += 1; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ****************************************************************\n"); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", + board_info->pg_ant_num, board_info->btdm_ant_num, + board_info->btdm_ant_pos); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT stack/ hci ext ver = %s / %d\n", + ((stack_info->profile_notified) ? "Yes" : "No"), + stack_info->hci_version); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, + &bt_patch_ver); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", + glcoex_ver_date_8812a_2ant, glcoex_ver_8812a_2ant, + fw_ver, bt_patch_ver, bt_patch_ver); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ****************************************************************\n"); + BTC_TRACE(trace_buf); + } + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + coex_sta->bt_coex_supported_version = + btcoexist->btc_get_bt_coex_supported_version(btcoexist); + +#if (BT_AUTO_REPORT_ONLY_8812A_2ANT == 0) + halbtc8812a2ant_query_bt_info(btcoexist); + halbtc8812a2ant_monitor_bt_ctr(btcoexist); + halbtc8812a2ant_monitor_wifi_ctr(btcoexist); + halbtc8812a2ant_monitor_bt_enable_disable(btcoexist); +#else + halbtc8812a2ant_monitor_wifi_ctr(btcoexist); + + if (halbtc8812a2ant_is_wifi_status_changed(btcoexist) || + coex_dm->auto_tdma_adjust || + coex_dm->auto_tdma_adjust_low_rssi) + halbtc8812a2ant_run_coexist_mechanism(btcoexist); +#endif +} + +void ex_halbtc8812a2ant_dbg_control(IN struct btc_coexist *btcoexist, + IN u8 op_code, IN u8 op_len, IN u8 *pdata) +{ + switch (op_code) { + case BTC_DBG_SET_COEX_DEC_BT_PWR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set Dec BT power\n"); + BTC_TRACE(trace_buf); + + { + u8 data_len = 4; + u8 buf[6] = {0}; + u8 dec_bt_pwr = 0, pwr_level = 0; + + if (op_len == 2) { + dec_bt_pwr = pdata[0]; + pwr_level = pdata[1]; + + buf[0] = data_len; + buf[1] = 0x3; /* OP_Code */ + buf[2] = 0x2; /* OP_Code_Length */ + + buf[3] = dec_bt_pwr; /* OP_Code_Content */ + buf[4] = pwr_level; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set Dec BT power=%d, pwr_level=%d\n", + dec_bt_pwr, pwr_level); + BTC_TRACE(trace_buf); + + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_CTRL_BT_COEX, + (void *)&buf[0]); + } + } + break; + + case BTC_DBG_SET_COEX_BT_AFH_MAP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set BT AFH Map\n"); + BTC_TRACE(trace_buf); + { + u8 data_len = 5; + u8 buf[6] = {0}; + + if (op_len == 3) { + buf[0] = data_len; + buf[1] = 0x5; /* OP_Code */ + buf[2] = 0x3; /* OP_Code_Length */ + + buf[3] = pdata[0]; /* OP_Code_Content */ + buf[4] = pdata[1]; + buf[5] = pdata[2]; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set BT AFH Map = %02x %02x %02x\n", + pdata[0], pdata[1], pdata[2]); + BTC_TRACE(trace_buf); + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_CTRL_BT_COEX, + (void *)&buf[0]); + } + } + break; + + case BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set BT Ignore Wlan Active\n"); + BTC_TRACE(trace_buf); + { + u8 data_len = 3; + u8 buf[6] = {0}; + + if (op_len == 1) { + buf[0] = data_len; + buf[1] = 0x1; /* OP_Code */ + buf[2] = 0x1; /* OP_Code_Length */ + + buf[3] = pdata[0]; /* OP_Code_Content */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set BT Ignore Wlan Active = 0x%x\n", + pdata[0]); + BTC_TRACE(trace_buf); + + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_CTRL_BT_COEX, + (void *)&buf[0]); + } + } + break; + + default: + break; + } +} + +#endif + +#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ + diff --git a/hal/btc/halbtc8812a2ant.h b/hal/btc/halbtc8812a2ant.h new file mode 100644 index 0000000..2b7f4aa --- /dev/null +++ b/hal/btc/halbtc8812a2ant.h @@ -0,0 +1,241 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8812A_SUPPORT == 1) + +/* ******************************************* + * The following is for 8812A 2Ant BT Co-exist definition + * ******************************************* */ +#define BT_AUTO_REPORT_ONLY_8812A_2ANT 0 + +#define BT_INFO_8812A_2ANT_B_FTP BIT(7) +#define BT_INFO_8812A_2ANT_B_A2DP BIT(6) +#define BT_INFO_8812A_2ANT_B_HID BIT(5) +#define BT_INFO_8812A_2ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8812A_2ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8812A_2ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8812A_2ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8812A_2ANT_B_CONNECTION BIT(0) + +#define BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT(0))) ? true : false) + +#define BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT 2 +#define NOISY_AP_NUM_THRESH_8812A 50 + +enum bt_info_src_8812a_2ant { + BT_INFO_SRC_8812A_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8812A_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8812A_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8812A_2ANT_MAX +}; + +enum bt_8812a_2ant_bt_status { + BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8812A_2ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8812A_2ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8812A_2ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8812A_2ANT_BT_STATUS_MAX +}; + +enum bt_8812a_2ant_coex_algo { + BT_8812A_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8812A_2ANT_COEX_ALGO_SCO = 0x1, + BT_8812A_2ANT_COEX_ALGO_SCO_HID = 0x2, + BT_8812A_2ANT_COEX_ALGO_HID = 0x3, + BT_8812A_2ANT_COEX_ALGO_A2DP = 0x4, + BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS = 0x5, + BT_8812A_2ANT_COEX_ALGO_PANEDR = 0x6, + BT_8812A_2ANT_COEX_ALGO_PANHS = 0x7, + BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8, + BT_8812A_2ANT_COEX_ALGO_PANEDR_HID = 0x9, + BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa, + BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS = 0xb, + BT_8812A_2ANT_COEX_ALGO_HID_A2DP = 0xc, + BT_8812A_2ANT_COEX_ALGO_MAX = 0xd +}; + +struct coex_dm_8812a_2ant { + /* fw mechanism */ + u8 pre_bt_dec_pwr_lvl; + u8 cur_bt_dec_pwr_lvl; + u8 pre_fw_dac_swing_lvl; + u8 cur_fw_dac_swing_lvl; + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean auto_tdma_adjust; + boolean auto_tdma_adjust_low_rssi; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + /* sw mechanism */ + boolean pre_rf_rx_lpf_shrink; + boolean cur_rf_rx_lpf_shrink; + u32 bt_rf_0x1e_backup; + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + boolean pre_dac_swing_on; + u32 pre_dac_swing_lvl; + boolean cur_dac_swing_on; + u32 cur_dac_swing_lvl; + boolean pre_adc_back_off; + boolean cur_adc_back_off; + boolean pre_agc_table_en; + boolean cur_agc_table_en; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ + u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ + u16 backup_retry_limit; + u8 backup_ampdu_max_time; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + u32 pre_ra_mask; + u32 cur_ra_mask; + u8 cur_ra_mask_type; + u8 pre_arfr_type; + u8 cur_arfr_type; + u8 pre_retry_limit_type; + u8 cur_retry_limit_type; + u8 pre_ampdu_time_type; + u8 cur_ampdu_time_type; + + boolean cur_enable_pta; + boolean pre_enable_pta; +}; + +struct coex_sta_8812a_2ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + boolean acl_busy; + + boolean under_lps; + boolean under_ips; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + u8 bt_rssi; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + boolean c2h_bt_info_req_sent; + u8 bt_info_c2h[BT_INFO_SRC_8812A_2ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8812A_2ANT_MAX]; + u32 bt_info_query_cnt; + boolean c2h_bt_inquiry_page; + u8 bt_retry_cnt; + u8 bt_info_ext; + u8 scan_ap_num; + boolean pre_bt_disabled; + u32 pre_bt_info_c2h_cnt_bt_rsp; + u32 pre_bt_info_c2h_cnt_bt_send; + boolean force_lps_on; + u32 bt_coex_supported_version; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8812a2ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8812a2ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a2ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8812a2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8812a2ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); + +void ex_halbtc8812a2ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8812a2ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8812a2ant_display_coex_info(IN struct btc_coexist *btcoexist); +void ex_halbtc8812a2ant_dbg_control(IN struct btc_coexist *btcoexist, + IN u8 op_code, IN u8 op_len, IN u8 *pdata); +void ex_halbtc8812a2ant_pta_off_on_notify(IN struct btc_coexist *btcoexist, + IN u8 bt_status); + +#else +#define ex_halbtc8812a2ant_power_on_setting(btcoexist) +#define ex_halbtc8812a2ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8812a2ant_init_coex_dm(btcoexist) +#define ex_halbtc8812a2ant_ips_notify(btcoexist, type) +#define ex_halbtc8812a2ant_lps_notify(btcoexist, type) +#define ex_halbtc8812a2ant_scan_notify(btcoexist, type) +#define ex_halbtc8812a2ant_connect_notify(btcoexist, type) +#define ex_halbtc8812a2ant_media_status_notify(btcoexist, type) +#define ex_halbtc8812a2ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8812a2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8812a2ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8812a2ant_halt_notify(btcoexist) +#define ex_halbtc8812a2ant_periodical(btcoexist) +#define ex_halbtc8812a2ant_display_coex_info(btcoexist) +#define ex_halbtc8812a2ant_dbg_control(btcoexist, op_code, op_len, pdata) +#define ex_halbtc8812a2ant_pta_off_on_notify(btcoexist, bt_status) + +#endif + +#endif + diff --git a/hal/btc/halbtc8821a1ant.c b/hal/btc/halbtc8821a1ant.c new file mode 100644 index 0000000..5070897 --- /dev/null +++ b/hal/btc/halbtc8821a1ant.c @@ -0,0 +1,3303 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for 8821A_1ANT Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ + * SY modify 2015/04/27 + * ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8821A_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8821a_1ant glcoex_dm_8821a_1ant; +static struct coex_dm_8821a_1ant *coex_dm = &glcoex_dm_8821a_1ant; +static struct coex_sta_8821a_1ant glcoex_sta_8821a_1ant; +static struct coex_sta_8821a_1ant *coex_sta = &glcoex_sta_8821a_1ant; + +const char *const glbt_info_src_8821a_1ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u32 glcoex_ver_date_8821a_1ant = 20160816; +u32 glcoex_ver_8821a_1ant = 0x63; +u32 glcoex_ver_btdesired_8821a_1ant = 0x62; + +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8821a1ant_ + * ************************************************************ */ +u8 halbtc8821a1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_bt_rssi_state; + } + + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + +u8 halbtc8821a1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_wifi_rssi_state[index]; + } + + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; + + return wifi_rssi_state; +} + +void halbtc8821a1ant_update_ra_mask(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 dis_rate_mask) +{ + coex_dm->cur_ra_mask = dis_rate_mask; + + if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) + btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, + &coex_dm->cur_ra_mask); + coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; +} + +void halbtc8821a1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + boolean wifi_under_b_mode = false; + + coex_dm->cur_arfr_type = type; + + if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { + switch (coex_dm->cur_arfr_type) { + case 0: /* normal mode */ + btcoexist->btc_write_4byte(btcoexist, 0x430, + coex_dm->backup_arfr_cnt1); + btcoexist->btc_write_4byte(btcoexist, 0x434, + coex_dm->backup_arfr_cnt2); + break; + case 1: + btcoexist->btc_get(btcoexist, + BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + if (wifi_under_b_mode) { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x01010101); + } else { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x04030201); + } + break; + default: + break; + } + } + + coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; +} + +void halbtc8821a1ant_retry_limit(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_retry_limit_type = type; + + if (force_exec || + (coex_dm->pre_retry_limit_type != + coex_dm->cur_retry_limit_type)) { + switch (coex_dm->cur_retry_limit_type) { + case 0: /* normal mode */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + coex_dm->backup_retry_limit); + break; + case 1: /* retry limit=8 */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + 0x0808); + break; + default: + break; + } + } + + coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; +} + +void halbtc8821a1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_ampdu_time_type = type; + + if (force_exec || + (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { + switch (coex_dm->cur_ampdu_time_type) { + case 0: /* normal mode */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + coex_dm->backup_ampdu_max_time); + break; + case 1: /* AMPDU timw = 0x38 * 32us */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + 0x38); + break; + default: + break; + } + } + + coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; +} + +void halbtc8821a1ant_limited_tx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, + IN u8 retry_limit_type, IN u8 ampdu_time_type) +{ + switch (ra_mask_type) { + case 0: /* normal mode */ + halbtc8821a1ant_update_ra_mask(btcoexist, force_exec, + 0x0); + break; + case 1: /* disable cck 1/2 */ + halbtc8821a1ant_update_ra_mask(btcoexist, force_exec, + 0x00000003); + break; + case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ + halbtc8821a1ant_update_ra_mask(btcoexist, force_exec, + 0x0001f1f7); + break; + default: + break; + } + + halbtc8821a1ant_auto_rate_fallback_retry(btcoexist, force_exec, + arfr_type); + halbtc8821a1ant_retry_limit(btcoexist, force_exec, retry_limit_type); + halbtc8821a1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); +} + + +/* true/xxxx/x:1 + * false/false/x: 64 + * false/true/x:x */ +void halbtc8821a1ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +void halbtc8821a1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; +#if 0 + /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ + if (!(btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8)) { + coex_sta->high_priority_tx = 65535; + coex_sta->high_priority_rx = 65535; + coex_sta->low_priority_tx = 65535; + coex_sta->low_priority_rx = 65535; + return; + } +#endif + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); +} + +void halbtc8821a1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ +#if 1 + + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_VHT); + +#endif +} + + +void halbtc8821a1ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + coex_sta->c2h_bt_info_req_sent = true; + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); +} + +boolean halbtc8821a1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) +{ + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + } + + return false; +} + +void halbtc8821a1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = true; + bt_link_info->bt_link_exist = true; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = true; + else + bt_link_info->sco_only = false; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = true; + else + bt_link_info->a2dp_only = false; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = true; + else + bt_link_info->pan_only = false; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = true; + else + bt_link_info->hid_only = false; +} + +u8 halbtc8821a1ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + u8 algorithm = BT_8821A_1ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_1ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_1ANT_COEX_ALGO_HID_A2DP; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +void halbtc8821a1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean enable_auto_report) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = 0; + + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); + + btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); +} + +void halbtc8821a1ant_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable_auto_report) +{ + coex_dm->cur_bt_auto_report = enable_auto_report; + + if (!force_exec) { + if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) + return; + } + halbtc8821a1ant_set_bt_auto_report(btcoexist, + coex_dm->cur_bt_auto_report); + + coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; +} + +void halbtc8821a1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist + *btcoexist, IN boolean low_penalty_ra) +{ + u8 h2c_parameter[6] = {0}; + + h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ + + if (low_penalty_ra) { + h2c_parameter[1] |= BIT(0); + h2c_parameter[2] = + 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ + h2c_parameter[3] = 0xf5; /* MCS7 or OFDM54 */ + h2c_parameter[4] = 0xa0; /* MCS6 or OFDM48 */ + h2c_parameter[5] = 0xa0; /* MCS5 or OFDM36 */ + } + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); +} + +void halbtc8821a1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) + return; + } + halbtc8821a1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, + coex_dm->cur_low_penalty_ra); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; +} + +void halbtc8821a1ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8821a1ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8821a1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8821a1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** CoexTable(%d) **********\n", type); + BTC_TRACE(trace_buf); + + switch (type) { + case 0: + halbtc8821a1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8821a1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 2: + halbtc8821a1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 3: + halbtc8821a1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 4: + halbtc8821a1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 5: + halbtc8821a1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0xaaaa5a5a, 0xffffff, 0x3); + break; + case 6: + halbtc8821a1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); + break; + case 7: + halbtc8821a1ant_coex_table(btcoexist, force_exec, + 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + default: + break; + } +} + +void halbtc8821a1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 h2c_parameter[1] = {0}; + + if (enable) + h2c_parameter[0] |= BIT(0); /* function enable */ + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + +void halbtc8821a1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8821a1ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8821a1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if (ap_enable) { + if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], FW for 1Ant AP mode\n"); + BTC_TRACE(trace_buf); + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + } + } + + h2c_parameter[0] = real_byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = real_byte5; + + coex_dm->ps_tdma_para[0] = real_byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = real_byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); +} + +void halbtc8821a1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8821a1ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8821a1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8821a1ant_sw_mechanism(IN struct btc_coexist *btcoexist, + IN boolean low_penalty_ra) +{ + halbtc8821a1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); +} + +void halbtc8821a1ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u32 u32tmp = 0; + u8 h2c_parameter[2] = {0}; + + if (init_hwcfg) { + /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp &= ~BIT(23); + u32tmp |= BIT(24); + btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); + + /* 0x765 = 0x18 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x3); + + if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { + /* tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ + h2c_parameter[0] = 1; + h2c_parameter[1] = 1; + btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, + h2c_parameter); + + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, 0x1); */ /*Main Ant to BT for IPS case 0x4c[23]=1 */ + } else { + /* tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ + h2c_parameter[0] = 0; + h2c_parameter[1] = 1; + btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, + h2c_parameter); + + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, 0x0); */ /*Aux Ant to BT for IPS case 0x4c[23]=1 */ + } + } else if (wifi_off) { + /* 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL BT Vendor 0xac=0xf002 */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp &= ~BIT(23); + u32tmp &= ~BIT(24); + btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); + + /* 0x765 = 0x18 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x3); + } else { + /* 0x765 = 0x0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x0); + } + + /* ext switch setting */ + switch (ant_pos_type) { + case BTC_ANT_PATH_WIFI: + btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77); + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0xcb7, 0x30, 0x1); + else + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0xcb7, 0x30, 0x2); + break; + case BTC_ANT_PATH_BT: + btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77); + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0xcb7, 0x30, 0x2); + else + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0xcb7, 0x30, 0x1); + break; + default: + case BTC_ANT_PATH_PTA: + btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x66); + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0xcb7, 0x30, 0x1); + else + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0xcb7, 0x30, 0x2); + break; + } +} + +void halbtc8821a1ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + u8 rssi_adjust_val = 0; + /* u32 fw_ver=0; */ + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + if (coex_dm->cur_ps_tdma_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(on, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) + return; + } + if (turn_on) { + switch (type) { + default: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x1a, 0x1a, 0x0, 0x50); + break; + case 1: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x3a, 0x03, 0x10, 0x50); + rssi_adjust_val = 11; + break; + case 2: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x2b, 0x03, 0x10, 0x50); + rssi_adjust_val = 14; + break; + case 3: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x1d, 0x1d, 0x0, 0x52); + break; + case 4: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93, + 0x15, 0x3, 0x14, 0x0); + rssi_adjust_val = 17; + break; + case 5: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, + 0x15, 0x3, 0x11, 0x10); + break; + case 6: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, + 0x20, 0x3, 0x11, 0x13); + break; + case 7: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13, + 0xc, 0x5, 0x0, 0x0); + break; + case 8: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93, + 0x25, 0x3, 0x10, 0x0); + break; + case 9: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x21, 0x3, 0x10, 0x50); + rssi_adjust_val = 18; + break; + case 10: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13, + 0xa, 0xa, 0x0, 0x40); + break; + case 11: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x15, 0x03, 0x10, 0x50); + rssi_adjust_val = 20; + break; + case 12: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x0a, 0x0a, 0x0, 0x50); + break; + case 13: + if (coex_sta->scan_ap_num <= 5) + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x40, 0x3, 0x10, 0x50); + else + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x12, 0x12, 0x0, 0x50); + break; + case 14: + if (coex_sta->scan_ap_num <= 5) + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, 0x50); + else + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x1e, 0x3, 0x10, 0x14); + break; + case 15: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13, + 0xa, 0x3, 0x8, 0x0); + break; + case 16: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93, + 0x15, 0x3, 0x10, 0x0); + rssi_adjust_val = 18; + break; + case 18: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93, + 0x25, 0x3, 0x10, 0x0); + rssi_adjust_val = 14; + break; + case 20: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, 0x10); + break; + case 21: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, 0x11); + break; + case 22: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, 0x10); + break; + case 23: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x3, 0x31, 0x18); + rssi_adjust_val = 22; + break; + case 24: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, + 0x15, 0x3, 0x31, 0x18); + rssi_adjust_val = 22; + break; + case 25: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, + 0xa, 0x3, 0x31, 0x18); + rssi_adjust_val = 22; + break; + case 26: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, + 0xa, 0x3, 0x31, 0x18); + rssi_adjust_val = 22; + break; + case 27: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x3, 0x31, 0x98); + rssi_adjust_val = 22; + break; + case 28: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x69, + 0x25, 0x3, 0x31, 0x0); + break; + case 29: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xab, + 0x1a, 0x1a, 0x1, 0x10); + break; + case 30: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, 0x10); + break; + case 31: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xd3, + 0x1a, 0x1a, 0, 0x58); + break; + case 32: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x3, 0x11, 0x11); + break; + case 33: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xa3, + 0x25, 0x3, 0x30, 0x90); + break; + case 34: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x53, + 0x1a, 0x1a, 0x0, 0x10); + break; + case 35: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x63, + 0x1a, 0x1a, 0x0, 0x10); + break; + case 36: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xd3, + 0x12, 0x3, 0x14, 0x50); + break; + case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */ + /* here softap mode screen off will cost 70-80mA for phone */ + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x23, + 0x18, 0x00, 0x10, 0x24); + break; + case 41: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x15, 0x3, 0x11, 0x11); + break; + case 42: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x20, 0x3, 0x11, 0x11); + break; + case 43: + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, 0x11); + break; + } + } else { + /* disable PS tdma */ + switch (type) { + case 8: /* PTA Control */ + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x8, + 0x0, 0x0, 0x0, 0x0); + halbtc8821a1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_PTA, false, false); + break; + case 0: + default: /* Software control, Antenna at BT side */ + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x0, 0x0); + halbtc8821a1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_BT, false, false); + break; + case 9: /* Software control, Antenna at WiFi side */ + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x0, 0x0); + halbtc8821a1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_WIFI, false, false); + break; + case 10: /* under 5G */ + halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x8, 0x0); + halbtc8821a1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_BT, false, false); + break; + } + } + rssi_adjust_val = 0; + btcoexist->btc_set(btcoexist, + BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val); + + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; +} + +void halbtc8821a1ant_coex_all_off(IN struct btc_coexist *btcoexist) +{ + /* sw all off */ + halbtc8821a1ant_sw_mechanism(btcoexist, false); + + /* hw all off */ + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +boolean halbtc8821a1ant_is_common_action(IN struct btc_coexist *btcoexist) +{ + boolean common = false, wifi_connected = false, wifi_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_connected && + BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_sw_mechanism(btcoexist, false); + + common = true; + } else if (wifi_connected && + (BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_sw_mechanism(btcoexist, false); + + common = true; + } else if (!wifi_connected && + (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_sw_mechanism(btcoexist, false); + + common = true; + } else if (wifi_connected && + (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_sw_mechanism(btcoexist, false); + + common = true; + } else if (!wifi_connected && + (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE != + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_sw_mechanism(btcoexist, false); + + common = true; + } else { + if (wifi_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } + + common = false; + } + + return common; +} + +void halbtc8821a1ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + +void halbtc8821a1ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = false; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + /* recover to original 32k low power setting */ + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + break; + case BTC_PS_LPS_ON: + halbtc8821a1ant_ps_tdma_check_for_power_save_state( + btcoexist, true); + halbtc8821a1ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + break; + case BTC_PS_LPS_OFF: + halbtc8821a1ant_ps_tdma_check_for_power_save_state( + btcoexist, false); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + break; + default: + break; + } +} + +void halbtc8821a1ant_coex_under_5g(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + halbtc8821a1ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true); + + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 10); + + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + + halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 5); +} + +void halbtc8821a1ant_action_wifi_only(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 9); +} + +void halbtc8821a1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = true, bt_disabled = false; + + /* This function check if bt is disabled */ + + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = false; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = false; + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + BTC_TRACE(trace_buf); + } else { + bt_disable_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt all counters=0, %d times!!\n", + bt_disable_cnt); + BTC_TRACE(trace_buf); + if (bt_disable_cnt >= 10) { + bt_disabled = true; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_action_wifi_only(btcoexist); + } + } + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + if (!bt_disabled) { + } else { + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + } + } +} + +/* ********************************************* + * + * Software Coex Mechanism start + * + * ********************************************* */ + +void halbtc8821a1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + /* halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); */ + halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, false, false); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} +/* SCO only or SCO+PAN(HS) */ +void halbtc8821a1ant_action_sco(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_sw_mechanism(btcoexist, true); +} + +void halbtc8821a1ant_action_hid(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_sw_mechanism(btcoexist, true); +} + +/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ +void halbtc8821a1ant_action_a2dp(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_sw_mechanism(btcoexist, false); +} + +void halbtc8821a1ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_sw_mechanism(btcoexist, false); +} + +void halbtc8821a1ant_action_pan_edr(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_sw_mechanism(btcoexist, false); +} + +/* PAN(HS) only */ +void halbtc8821a1ant_action_pan_hs(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_sw_mechanism(btcoexist, false); +} + +/* PAN(EDR)+A2DP */ +void halbtc8821a1ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_sw_mechanism(btcoexist, false); +} + +void halbtc8821a1ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_sw_mechanism(btcoexist, true); +} + +/* HID+A2DP+PAN(EDR) */ +void halbtc8821a1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_sw_mechanism(btcoexist, true); +} + +void halbtc8821a1ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_sw_mechanism(btcoexist, true); +} + +/* ********************************************* + * + * Non-Software Coex Mechanism start + * + * ********************************************* */ +void halbtc8821a1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8821a1ant_action_hs(IN struct btc_coexist *btcoexist) +{ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8821a1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, ap_enable = false, wifi_busy = false, + bt_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) { + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } + + /* sy modify */ + else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || + (bt_link_info->a2dp_exist)) { + /* SCO/HID/A2DP busy */ + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } + + /* sy modify */ + + else if ((bt_link_info->a2dp_exist) && + (bt_link_info->hid_exist)) { + /* A2DP+HID busy */ + halbtc8821a1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 14); + + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + } + + + else if ((bt_link_info->pan_exist) || (wifi_busy)) { + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + } +} + +void halbtc8821a1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist + *btcoexist, IN u8 wifi_status) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* tdma and coex table */ + + if (bt_link_info->sco_exist) { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 41); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } else { /* HID */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 42); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8821a1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist + *btcoexist, IN u8 wifi_status) +{ + u8 bt_rssi_state; + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + bt_rssi_state = halbtc8821a1ant_bt_rssi_state(2, 28, 0); + + if (bt_link_info->hid_only) { /* HID */ + halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, + wifi_status); + coex_dm->auto_tdma_adjust = false; + return; + } else if (bt_link_info->a2dp_only) { /* A2DP */ + if (BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { + /* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); */ + /* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + coex_dm->auto_tdma_adjust = false; + } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + /* halbtc8821a1ant_tdma_duration_adjust_for_acl(btcoexist, wifi_status); */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 14); + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + } else { /* for low BT RSSI */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 14); + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + coex_dm->auto_tdma_adjust = false; + } + } else if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { /* HID+A2DP */ + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 14); + coex_dm->auto_tdma_adjust = false; + } else { /* for low BT RSSI */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 14); + coex_dm->auto_tdma_adjust = false; + } + + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && + bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); + coex_dm->auto_tdma_adjust = false; + } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || + (bt_link_info->hid_exist && bt_link_info->a2dp_exist && + bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 43); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + coex_dm->auto_tdma_adjust = false; + } else { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + coex_dm->auto_tdma_adjust = false; + } +} + +void halbtc8821a1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +{ + /* power save state */ + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8821a1ant_action_wifi_not_connected_scan(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + if (bt_link_info->a2dp_exist) { + /* sy modify */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 14); + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + } else if (bt_link_info->a2dp_exist && + bt_link_info->pan_exist) { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 22); + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 20); + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } else { + /* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); */ + /* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); */ + + /* Bryant Add */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8821a1ant_action_wifi_not_connected_asso_auth( + IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) { + /* sy modify */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + } else if ((bt_link_info->a2dp_exist) || (bt_link_info->pan_exist)) { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8821a1ant_action_wifi_connected_scan(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + if (bt_link_info->a2dp_exist) { + /* sy modify */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 14); + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + } else if (bt_link_info->a2dp_exist && + bt_link_info->pan_exist) { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 22); + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 20); + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } else { + /* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); */ + /* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); */ + + /* Bryant Add */ + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8821a1ant_action_wifi_connected_specific_packet( + IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + /* tdma and coex table */ + /* sy modify */ + if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || + (bt_link_info->a2dp_exist)) { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } + + if ((bt_link_info->hid_exist) && (bt_link_info->a2dp_exist)) { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 14); + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + } + + + else if (bt_link_info->pan_exist) { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + } +} + +void halbtc8821a1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +{ + boolean wifi_busy = false; + boolean scan = false, link = false, roam = false; + boolean under_4way = false, ap_enable = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect()===>\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + if (under_4way) { + halbtc8821a1ant_action_wifi_connected_specific_packet( + btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + if (scan || link || roam) { + if (scan) + halbtc8821a1ant_action_wifi_connected_scan(btcoexist); + else + halbtc8821a1ant_action_wifi_connected_specific_packet( + btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + /* power save state */ + if (!ap_enable && + BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status && + !btcoexist->bt_link_info.hid_only) { + if (!wifi_busy && btcoexist->bt_link_info.a2dp_only) /* A2DP */ + halbtc8821a1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8821a1ant_power_save_state(btcoexist, + BTC_PS_LPS_ON, 0x50, 0x4); + } else + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + + /* tdma and coex table */ + if (!wifi_busy) { + if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + halbtc8821a1ant_action_wifi_connected_bt_acl_busy( + btcoexist, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } else { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 2); + } + } else { + if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + halbtc8821a1ant_action_wifi_connected_bt_acl_busy( + btcoexist, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } else { + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); + halbtc8821a1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 2); + } + } +} + +void halbtc8821a1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + u8 algorithm = 0; + + algorithm = halbtc8821a1ant_action_algorithm(btcoexist); + coex_dm->cur_algorithm = algorithm; + + if (halbtc8821a1ant_is_common_action(btcoexist)) { + + } else { + switch (coex_dm->cur_algorithm) { + case BT_8821A_1ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_action_sco(btcoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID.\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_action_hid(btcoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_action_a2dp(btcoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_action_a2dp_pan_hs(btcoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_action_pan_edr(btcoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HS mode.\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_action_pan_hs(btcoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_action_pan_edr_a2dp(btcoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_action_pan_edr_hid(btcoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_action_hid_a2dp_pan_edr( + btcoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_action_hid_a2dp(btcoexist); + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + /* halbtc8821a1ant_coex_all_off(btcoexist); */ + break; + } + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + } +} + +void halbtc8821a1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, bt_hs_on = false; + boolean increase_scan_dev_num = false; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean wifi_under_5g = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_coex_under_5g(btcoexist); + return; + } + if (coex_sta->bt_whck_test) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under WHCK TEST!!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_action_bt_whck_test(btcoexist); + return; + } + + if ((BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + increase_scan_dev_num = true; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, + &increase_scan_dev_num); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8821a1ant_action_wifi_multi_port(btcoexist); + return; + } + + if (!bt_link_info->sco_exist && !bt_link_info->hid_exist) + halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + else { + if (wifi_connected) { + wifi_rssi_state = halbtc8821a1ant_wifi_rssi_state( + btcoexist, 1, 2, 30, 0); + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + /* halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 1, 1); */ + halbtc8821a1ant_limited_tx(btcoexist, + NORMAL_EXEC, 1, 1, 0, 1); + } else { + /* halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 1, 1); */ + halbtc8821a1ant_limited_tx(btcoexist, + NORMAL_EXEC, 1, 1, 0, 1); + } + } else + halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, + 0, 0); + + } + + if (bt_link_info->sco_exist) { + bt_ctrl_agg_buf_size = true; + agg_buf_size = 0x3; + } else if (bt_link_info->hid_exist) { + bt_ctrl_agg_buf_size = true; + agg_buf_size = 0x5; + } else if (bt_link_info->a2dp_exist || bt_link_info->pan_exist) { + bt_ctrl_agg_buf_size = true; + agg_buf_size = 0x8; + } + halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + + halbtc8821a1ant_run_sw_coexist_mechanism(btcoexist); + + /* low pelnaty ra in pcr ra */ + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8821a1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8821a1ant_action_hs(btcoexist); + return; + } + + + if (!wifi_connected) { + boolean scan = false, link = false, roam = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is non connected-idle !!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + if (scan || link || roam) { + if (scan) + halbtc8821a1ant_action_wifi_not_connected_scan( + btcoexist); + else + halbtc8821a1ant_action_wifi_not_connected_asso_auth( + btcoexist); + } else + halbtc8821a1ant_action_wifi_not_connected(btcoexist); + } else /* wifi LPS/Busy */ + halbtc8821a1ant_action_wifi_connected(btcoexist); +} + +void halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + /* force to reset coex mechanism */ + /* sw all off */ + halbtc8821a1ant_sw_mechanism(btcoexist, false); + + /* halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ + halbtc8821a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); +} + +void halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean back_up, IN boolean wifi_only) +{ + u8 u8tmp = 0; + boolean wifi_under_5g = false; + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 1Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + if (wifi_only) + return; + + if (back_up) { + coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, + 0x430); + coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, + 0x434); + coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( + btcoexist, 0x42a); + coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( + btcoexist, 0x456); + } + + /* 0x790[5:0]=0x5 */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); + u8tmp &= 0xc0; + u8tmp |= 0x5; + btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + /* Give bt_coex_supported_version the default value */ + coex_sta->bt_coex_supported_version = 0; + + /* 0xf0[15:12] --> Chip Cut information */ + coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, + 0xf1) & 0xf0) >> 4; + + /* Antenna config */ + if (wifi_under_5g) + halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, + false); + else + halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, true, + false); + + /* PTA parameter */ + halbtc8821a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + /* Enable counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, + 0xc); /* 0x76e[3] =1, WLAN_Act control by PTA */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); +} + +/* ************************************************************ + * work around function start with wa_halbtc8821a1ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8821a1ant_ + * ************************************************************ */ +void ex_halbtc8821a1ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ +} + +void ex_halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8821a1ant_init_hw_config(btcoexist, true, wifi_only); +} + +void ex_halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = false; + + halbtc8821a1ant_init_coex_dm(btcoexist); + + halbtc8821a1ant_query_bt_info(btcoexist); +} + +void ex_halbtc8821a1ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u16 u16tmp[4]; + u32 u32tmp[4]; + u32 fw_ver = 0, bt_patch_ver = 0; + u32 bt_coex_ver = 0; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 phyver = 0; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + if (btcoexist->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", + "Ant PG Num/ Ant Mech/ Ant Pos:", + board_info->pg_ant_num, board_info->btdm_ant_num, + board_info->btdm_ant_pos); + CL_PRINTF(cli_buf); + + /* btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); */ + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8821a_1ant, glcoex_ver_8821a_1ant, + glcoex_ver_btdesired_8821a_1ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (bt_coex_ver >= glcoex_ver_btdesired_8821a_1ant ? + "Match" : "Mis-Match"))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "Wifi channel informed to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", + "BT [status/ rssi/ retryCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") + : ((BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi, coex_sta->bt_retry_cnt); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", + "SCO/HID/PAN/A2DP", + bt_link_info->sco_exist, bt_link_info->hid_exist, + bt_link_info->pan_exist, bt_link_info->a2dp_exist); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); + + bt_info_ext = coex_sta->bt_info_ext; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "BT Info A2DP rate", + (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); + CL_PRINTF(cli_buf); + + for (i = 0; i < BT_INFO_SRC_8821A_1ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8821a_1ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + if (!btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "SM[LowPenaltyRA]", + coex_dm->cur_low_penalty_ra); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanisms]============"); + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", + "PS TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + coex_dm->auto_tdma_adjust); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", + "IgnWlanAct", + coex_dm->cur_ignore_wlan_act); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", + "Latest error condition(should be 0)", + coex_dm->error_condition); + CL_PRINTF(cli_buf); + } + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", + "backup ARFR1/ARFR2/RL/AMaxTime", + coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2, + coex_dm->backup_retry_limit, + coex_dm->backup_ampdu_max_time); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); + u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", + "0x430/0x434/0x42a/0x456", + u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc58); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x778/ 0xc58[29:25]", + u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x8db); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8db[6:5]", + ((u8tmp[0] & 0x60) >> 5)); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x975); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0xcb4[29:28]/0xcb4[7:0]/0x974[9:8]", + (u32tmp[0] & 0x30000000) >> 28, u32tmp[0] & 0xff, + u8tmp[0] & 0x3); + CL_PRINTF(cli_buf); + + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x64); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x40/0x4c[24:23]/0x64[0]", + u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u8tmp[1] & 0x1); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x550(bcn ctrl)/0x522", + u32tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", + u32tmp[0] & 0xff); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_CCK); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11n-agg", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_Err CCK/11g/11n/11n-agg", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); + CL_PRINTF(cli_buf); + + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x6c0/0x6c4/0x6c8(coexTable)", + u32tmp[0], u32tmp[1], u32tmp[2]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(high-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x774(low-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx); + CL_PRINTF(cli_buf); +#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 1) + halbtc8821a1ant_monitor_bt_ctr(btcoexist); +#endif + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +void ex_halbtc8821a1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + boolean wifi_under_5g = false; + + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, + &wifi_under_5g); + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_coex_under_5g(btcoexist); + return; + } + + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = true; + + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, + true); + /* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */ + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = false; + + halbtc8821a1ant_init_hw_config(btcoexist, false, false); + halbtc8821a1ant_init_coex_dm(btcoexist); + halbtc8821a1ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8821a1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + + + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = true; + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = false; + } +} + +void ex_halbtc8821a1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false, bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + boolean wifi_under_5g = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_coex_under_5g(btcoexist); + return; + } + + if (BTC_SCAN_START == type) { + coex_sta->wifi_is_high_pri_task = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 8); /* Force antenna setup for no scan result issue */ + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify\n"); + BTC_TRACE(trace_buf); + } + + if (coex_sta->bt_disabled) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + halbtc8821a1ant_query_bt_info(btcoexist); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8821a1ant_action_wifi_multi_port(btcoexist); + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8821a1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8821a1ant_action_hs(btcoexist); + return; + } + + if (BTC_SCAN_START == type) { + if (!wifi_connected) /* non-connected scan */ + halbtc8821a1ant_action_wifi_not_connected_scan( + btcoexist); + else /* wifi is connected */ + halbtc8821a1ant_action_wifi_connected_scan(btcoexist); + } else if (BTC_SCAN_FINISH == type) { + if (!wifi_connected) /* non-connected scan */ + halbtc8821a1ant_action_wifi_not_connected(btcoexist); + else + halbtc8821a1ant_action_wifi_connected(btcoexist); + } +} + +/* copy scan notify content to switch band notify */ +void ex_halbtc8821a1ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false, bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + boolean wifi_under_5g = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_coex_under_5g(btcoexist); + return; + } + + if (BTC_SCAN_START == type) { + coex_sta->wifi_is_high_pri_task = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, + 8); /* Force antenna setup for no scan result issue */ + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify\n"); + BTC_TRACE(trace_buf); + } + + if (coex_sta->bt_disabled) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + halbtc8821a1ant_query_bt_info(btcoexist); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8821a1ant_action_wifi_multi_port(btcoexist); + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8821a1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8821a1ant_action_hs(btcoexist); + return; + } + + if (BTC_SCAN_START == type) { + if (!wifi_connected) /* non-connected scan */ + halbtc8821a1ant_action_wifi_not_connected_scan( + btcoexist); + else /* wifi is connected */ + halbtc8821a1ant_action_wifi_connected_scan(btcoexist); + } else if (BTC_SCAN_FINISH == type) { + if (!wifi_connected) /* non-connected scan */ + halbtc8821a1ant_action_wifi_not_connected(btcoexist); + else + halbtc8821a1ant_action_wifi_connected(btcoexist); + } +} +void ex_halbtc8821a1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false, bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + boolean wifi_under_5g = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm || + coex_sta->bt_disabled) + return; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_coex_under_5g(btcoexist); + return; + } + + if (BTC_ASSOCIATE_START == type) { + coex_sta->wifi_is_high_pri_task = true; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify\n"); + BTC_TRACE(trace_buf); + coex_dm->arp_cnt = 0; + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify\n"); + BTC_TRACE(trace_buf); + coex_dm->arp_cnt = 0; + } + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8821a1ant_action_wifi_multi_port(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8821a1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8821a1ant_action_hs(btcoexist); + return; + } + + if (BTC_ASSOCIATE_START == type) + halbtc8821a1ant_action_wifi_not_connected_asso_auth(btcoexist); + else if (BTC_ASSOCIATE_FINISH == type) { + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + if (!wifi_connected) /* non-connected scan */ + halbtc8821a1ant_action_wifi_not_connected(btcoexist); + else + halbtc8821a1ant_action_wifi_connected(btcoexist); + } +} + +void ex_halbtc8821a1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + boolean wifi_under_5g = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm || + coex_sta->bt_disabled) + return; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_coex_under_5g(btcoexist); + return; + } + + if (BTC_MEDIA_CONNECT == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + coex_dm->arp_cnt = 0; + } + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + /* h2c_parameter[0] = 0x1; */ + h2c_parameter[0] = 0x0; + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); +} + +void ex_halbtc8821a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + boolean wifi_under_5g = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm || + coex_sta->bt_disabled) + return; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_coex_under_5g(btcoexist); + return; + } + + if (BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + BTC_PACKET_ARP == type) { + coex_sta->wifi_is_high_pri_task = true; + + if (BTC_PACKET_ARP == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ARP notify\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet DHCP or EAPOL notify\n"); + BTC_TRACE(trace_buf); + } + } else { + coex_sta->wifi_is_high_pri_task = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet [Type = %d] notify\n", type); + BTC_TRACE(trace_buf); + } + + coex_sta->specific_pkt_period_cnt = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + if (num_of_wifi_link >= 2) { + halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8821a1ant_action_wifi_multi_port(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8821a1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8821a1ant_action_hs(btcoexist); + return; + } + + if (BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + BTC_PACKET_ARP == type) { + if (BTC_PACKET_ARP == type) { + coex_dm->arp_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ARP Packet Count = %d\n", + coex_dm->arp_cnt); + BTC_TRACE(trace_buf); + if (coex_dm->arp_cnt >= + 10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */ + return; + } + + halbtc8821a1ant_action_wifi_connected_specific_packet( + btcoexist); + } +} + +void ex_halbtc8821a1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 bt_info = 0; + u8 i, rsp_source = 0; + boolean wifi_connected = false; + boolean bt_busy = false; + boolean wifi_under_5g = false; + + + coex_sta->c2h_bt_info_req_sent = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8821A_1ANT_MAX) + rsp_source = BT_INFO_SRC_8821A_1ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + if (i == 1) + bt_info = tmp_buf[i]; + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + /* if 0xff, it means BT is under WHCK test */ + if (bt_info == 0xff) + coex_sta->bt_whck_test = true; + else + coex_sta->bt_whck_test = false; + + if (BT_INFO_SRC_8821A_1ANT_WIFI_FW != rsp_source) { + coex_sta->bt_retry_cnt = /* [3:0] */ + coex_sta->bt_info_c2h[rsp_source][2] & 0xf; + + if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) + coex_sta->c2h_bt_page = true; + else + coex_sta->c2h_bt_page = false; + + coex_sta->bt_rssi = + coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; + + coex_sta->bt_info_ext = + coex_sta->bt_info_c2h[rsp_source][4]; + + coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] + & 0x40); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, + &coex_sta->bt_tx_rx_mask); + if (!coex_sta->bt_tx_rx_mask) { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, + 0x3c, 0x15); + } + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + if (coex_sta->bt_info_ext & BIT(1)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + if (wifi_connected) + ex_halbtc8821a1ant_media_status_notify( + btcoexist, BTC_MEDIA_CONNECT); + else + ex_halbtc8821a1ant_media_status_notify( + btcoexist, BTC_MEDIA_DISCONNECT); + } + + if ((coex_sta->bt_info_ext & BIT(3)) && !wifi_under_5g) { + if (!btcoexist->manual_control && + !btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, false); + } + } else { + /* BT already NOT ignore Wlan active, do nothing here. */ + } +#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 0) + if ((coex_sta->bt_info_ext & BIT(4))) { + /* BT auto report already enabled, do nothing */ + } else + halbtc8821a1ant_bt_auto_report(btcoexist, FORCE_EXEC, + true); +#endif + } + + /* check BIT2 first ==> check if bt is under inquiry or page scan */ + if (bt_info & BT_INFO_8821A_1ANT_B_INQ_PAGE) + coex_sta->c2h_bt_inquiry_page = true; + else + coex_sta->c2h_bt_inquiry_page = false; + + /* set link exist status */ + if (!(bt_info & BT_INFO_8821A_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (bt_info & BT_INFO_8821A_1ANT_B_FTP) + coex_sta->pan_exist = true; + else + coex_sta->pan_exist = false; + if (bt_info & BT_INFO_8821A_1ANT_B_A2DP) + coex_sta->a2dp_exist = true; + else + coex_sta->a2dp_exist = false; + if (bt_info & BT_INFO_8821A_1ANT_B_HID) + coex_sta->hid_exist = true; + else + coex_sta->hid_exist = false; + if (bt_info & BT_INFO_8821A_1ANT_B_SCO_ESCO) + coex_sta->sco_exist = true; + else + coex_sta->sco_exist = false; + } + + halbtc8821a1ant_update_bt_link_info(btcoexist); + + bt_info = bt_info & + 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ + + if (!(bt_info & BT_INFO_8821A_1ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info == + BT_INFO_8821A_1ANT_B_CONNECTION) { /* connection exists but no busy */ + coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + BTC_TRACE(trace_buf); + } else if ((bt_info & BT_INFO_8821A_1ANT_B_SCO_ESCO) || + (bt_info & BT_INFO_8821A_1ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info & BT_INFO_8821A_1ANT_B_ACL_BUSY) { + if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) + coex_dm->auto_tdma_adjust = false; + coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + BTC_TRACE(trace_buf); + } + + if ((BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + bt_busy = true; + else + bt_busy = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + halbtc8821a1ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8821a1ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + boolean wifi_under_5g = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_coex_under_5g(btcoexist); + return; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true); + /* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */ + + halbtc8821a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + + ex_halbtc8821a1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + + btcoexist->stop_coex_dm = true; +} + +void ex_halbtc8821a1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + boolean wifi_under_5g = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); + BTC_TRACE(trace_buf); + halbtc8821a1ant_coex_under_5g(btcoexist); + return; + } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_WIFI_PNP_SLEEP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + + halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, + true); + /* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */ + + /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ + /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ + /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ + coex_sta->under_ips = false; + coex_sta->under_lps = false; + btcoexist->stop_coex_dm = true; + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); + btcoexist->stop_coex_dm = false; + halbtc8821a1ant_init_hw_config(btcoexist, false, false); + halbtc8821a1ant_init_coex_dm(btcoexist); + halbtc8821a1ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8821a1ant_periodical(IN struct btc_coexist *btcoexist) +{ + + if (((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) && + (!coex_sta->bt_disabled)) + coex_sta->bt_coex_supported_version = + btcoexist->btc_get_bt_coex_supported_version(btcoexist); + +#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 0) + halbtc8821a1ant_query_bt_info(btcoexist); + halbtc8821a1ant_monitor_bt_enable_disable(btcoexist); +#else + halbtc8821a1ant_monitor_bt_ctr(btcoexist); + halbtc8821a1ant_monitor_wifi_ctr(btcoexist); + halbtc8821a1ant_monitor_bt_enable_disable(btcoexist); + if (halbtc8821a1ant_is_wifi_status_changed(btcoexist) || + coex_dm->auto_tdma_adjust) { + /* if(coex_sta->specific_pkt_period_cnt > 2) */ + /* { */ + halbtc8821a1ant_run_coexist_mechanism(btcoexist); + /* } */ + } + + coex_sta->specific_pkt_period_cnt++; +#endif +} + +#endif + +#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ + + diff --git a/hal/btc/halbtc8821a1ant.h b/hal/btc/halbtc8821a1ant.h new file mode 100644 index 0000000..c9c141c --- /dev/null +++ b/hal/btc/halbtc8821a1ant.h @@ -0,0 +1,228 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8821A_SUPPORT == 1) + +/* ******************************************* + * The following is for 8821A 1ANT BT Co-exist definition + * ******************************************* */ +#define BT_AUTO_REPORT_ONLY_8821A_1ANT 1 + +#define BT_INFO_8821A_1ANT_B_FTP BIT(7) +#define BT_INFO_8821A_1ANT_B_A2DP BIT(6) +#define BT_INFO_8821A_1ANT_B_HID BIT(5) +#define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8821A_1ANT_B_CONNECTION BIT(0) + +#define BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT(0))) ? true : false) + +#define BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT 2 + +enum bt_info_src_8821a_1ant { + BT_INFO_SRC_8821A_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8821A_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8821A_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8821A_1ANT_MAX +}; + +enum bt_8821a_1ant_bt_status { + BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8821A_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8821A_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8821A_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8821A_1ANT_BT_STATUS_MAX +}; + +enum bt_8821a_1ant_wifi_status { + BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8821A_1ANT_WIFI_STATUS_MAX +}; + +enum bt_8821a_1ant_coex_algo { + BT_8821A_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8821A_1ANT_COEX_ALGO_SCO = 0x1, + BT_8821A_1ANT_COEX_ALGO_HID = 0x2, + BT_8821A_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8821A_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8821A_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8821A_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8821A_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8821A_1ANT_COEX_ALGO_MAX = 0xb, +}; + +struct coex_dm_8821a_1ant { + /* fw mechanism */ + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean auto_tdma_adjust; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + /* sw mechanism */ + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + + u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ + u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ + u16 backup_retry_limit; + u8 backup_ampdu_max_time; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + u32 pre_ra_mask; + u32 cur_ra_mask; + u8 pre_arfr_type; + u8 cur_arfr_type; + u8 pre_retry_limit_type; + u8 cur_retry_limit_type; + u8 pre_ampdu_time_type; + u8 cur_ampdu_time_type; + u32 arp_cnt; + + u8 error_condition; +}; + +struct coex_sta_8821a_1ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + + boolean under_lps; + boolean under_ips; + u32 specific_pkt_period_cnt; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + + u32 bt_coex_supported_version; + u8 cut_version; + u8 bt_rssi; + u8 scan_ap_num; + boolean bt_tx_rx_mask; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + boolean c2h_bt_info_req_sent; + u8 bt_info_c2h[BT_INFO_SRC_8821A_1ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8821A_1ANT_MAX]; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_page; /* Add for win8.1 page out issue */ + boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ + u8 bt_retry_cnt; + u8 bt_info_ext; + boolean bt_whck_test; /* Add for ASUS WHQL TEST that enable wifi test bt */ +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8821a1ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8821a1ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a1ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a1ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8821a1ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8821a1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8821a1ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8821a1ant_display_coex_info(IN struct btc_coexist *btcoexist); + +#else +#define ex_halbtc8821a1ant_power_on_setting(btcoexist) +#define ex_halbtc8821a1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8821a1ant_init_coex_dm(btcoexist) +#define ex_halbtc8821a1ant_ips_notify(btcoexist, type) +#define ex_halbtc8821a1ant_lps_notify(btcoexist, type) +#define ex_halbtc8821a1ant_scan_notify(btcoexist, type) +#define ex_halbtc8821a1ant_switchband_notify(btcoexist, type) +#define ex_halbtc8821a1ant_connect_notify(btcoexist, type) +#define ex_halbtc8821a1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8821a1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8821a1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8821a1ant_halt_notify(btcoexist) +#define ex_halbtc8821a1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8821a1ant_periodical(btcoexist) +#define ex_halbtc8821a1ant_display_coex_info(btcoexist) + +#endif + +#endif + diff --git a/hal/btc/halbtc8821a2ant.c b/hal/btc/halbtc8821a2ant.c new file mode 100644 index 0000000..3fcb757 --- /dev/null +++ b/hal/btc/halbtc8821a2ant.c @@ -0,0 +1,4651 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for RTL8821A Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8821A_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8821a_2ant glcoex_dm_8821a_2ant; +static struct coex_dm_8821a_2ant *coex_dm = &glcoex_dm_8821a_2ant; +static struct coex_sta_8821a_2ant glcoex_sta_8821a_2ant; +static struct coex_sta_8821a_2ant *coex_sta = &glcoex_sta_8821a_2ant; + +const char *const glbt_info_src_8821a_2ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u32 glcoex_ver_date_8821a_2ant = 20160816; +u32 glcoex_ver_8821a_2ant = 0x5d; +u32 glcoex_ver_btdesired_8821a_2ant = 0x5c; + +/* modify 20140903v43 a2dpandhid tdmaonoff a2dp glitch _ tdma off 778=3(case1)->778=1(case0) + * and to improve tp while a2dphid case23->case25 , case123->case125 for asus spec + * and modify for asus bt WHQL test _ tdma off_ 778=3->1_ + * ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8821a2ant_ + * ************************************************************ */ +u8 halbtc8821a2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_bt_rssi_state; + } + + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + +u8 halbtc8821a2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_wifi_rssi_state[index]; + } + + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; + + return wifi_rssi_state; +} + +void halbtc8821a2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = true, bt_disabled = false; + + /* This function check if bt is disabled */ + + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = false; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = false; + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + BTC_TRACE(trace_buf); + } else { + bt_disable_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt all counters=0, %d times!!\n", + bt_disable_cnt); + BTC_TRACE(trace_buf); + if (bt_disable_cnt >= 10) { + bt_disabled = true; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + BTC_TRACE(trace_buf); + } + } + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + /* if (!bt_disabled) { + } else { + } */ + } +} + +void halbtc8821a2ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); +} + +void halbtc8821a2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + if ((coex_sta->low_priority_rx >= 950) && + (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) && + (!coex_sta->under_ips)) + bt_link_info->slave_role = true; + else + bt_link_info->slave_role = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); + BTC_TRACE(trace_buf); + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); +} + +void halbtc8821a2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ +#if 1 + + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_VHT); + +#endif +} + +void halbtc8821a2ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + coex_sta->c2h_bt_info_req_sent = true; + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); +} + +boolean halbtc8821a2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) +{ + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 3, + 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + + if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) || + (BTC_RSSI_STATE_LOW == wifi_rssi_state)) + return true; + + } + + return false; +} + +void halbtc8821a2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = true; + bt_link_info->bt_link_exist = true; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = true; + else + bt_link_info->sco_only = false; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = true; + else + bt_link_info->a2dp_only = false; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = true; + else + bt_link_info->pan_only = false; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = true; + else + bt_link_info->hid_only = false; +} + +u8 halbtc8821a2ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + u8 algorithm = BT_8821A_2ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_2ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_2ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_2ANT_COEX_ALGO_HID_A2DP; + } + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_2ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(HS) ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(EDR) ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_2ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + } + } + } + + return algorithm; +} + +void halbtc8821a2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, + IN u8 dac_swing_lvl) +{ + u8 h2c_parameter[1] = {0}; + + /* There are several type of dacswing */ + /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ + h2c_parameter[0] = dac_swing_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); +} + +void halbtc8821a2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN u8 dec_bt_pwr_lvl) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = dec_bt_pwr_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); +} + +void halbtc8821a2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 dec_bt_pwr_lvl) +{ + coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; + + if (!force_exec) { + if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) + return; + } + halbtc8821a2ant_set_fw_dec_bt_pwr(btcoexist, + coex_dm->cur_bt_dec_pwr_lvl); + + coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; +} + +void halbtc8821a2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean enable_auto_report) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = 0; + + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); + + btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); +} + +void halbtc8821a2ant_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable_auto_report) +{ + coex_dm->cur_bt_auto_report = enable_auto_report; + + if (!force_exec) { + if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) + return; + } + halbtc8821a2ant_set_bt_auto_report(btcoexist, + coex_dm->cur_bt_auto_report); + + coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; +} + +void halbtc8821a2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 fw_dac_swing_lvl) +{ + coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; + + if (!force_exec) { + if (coex_dm->pre_fw_dac_swing_lvl == + coex_dm->cur_fw_dac_swing_lvl) + return; + } + + halbtc8821a2ant_set_fw_dac_swing_level(btcoexist, + coex_dm->cur_fw_dac_swing_lvl); + + coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; +} + +void halbtc8821a2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist, + IN boolean rx_rf_shrink_on) +{ + if (rx_rf_shrink_on) { + /* Shrink RF Rx LPF corner */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Shrink RF Rx LPF corner!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, + 0xffffc); + } else { + /* Resume RF Rx LPF corner */ + /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ + if (btcoexist->initilized) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Resume RF Rx LPF corner!!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, + 0xfffff, coex_dm->bt_rf_0x1e_backup); + } + } +} + +void halbtc8821a2ant_rf_shrink(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rx_rf_shrink_on) +{ + coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; + + if (!force_exec) { + if (coex_dm->pre_rf_rx_lpf_shrink == + coex_dm->cur_rf_rx_lpf_shrink) + return; + } + halbtc8821a2ant_set_sw_rf_rx_lpf_corner(btcoexist, + coex_dm->cur_rf_rx_lpf_shrink); + + coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; +} + +void halbtc8821a2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist + *btcoexist, IN boolean low_penalty_ra) +{ + u8 h2c_parameter[6] = {0}; + + h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ + + if (low_penalty_ra) { + h2c_parameter[1] |= BIT(0); + h2c_parameter[2] = + 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ + h2c_parameter[3] = 0xf3; /* MCS7 or OFDM54 */ + h2c_parameter[4] = 0xa0; /* MCS6 or OFDM48 */ + h2c_parameter[5] = 0xa0; /* MCS5 or OFDM36 */ + /* h2c_parameter[3] = 0xf7; */ /*MCS7 or OFDM54 */ + /* h2c_parameter[4] = 0xf8; */ /*MCS6 or OFDM48 */ + /* h2c_parameter[5] = 0xf9; /MCS5 or OFDM36 */ + } + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); +} + +void halbtc8821a2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) + return; + } + halbtc8821a2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, + coex_dm->cur_low_penalty_ra); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; +} + +void halbtc8821a2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, + IN u32 level) +{ + u8 val = (u8)level; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Write SwDacSwing = 0x%x\n", level); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val); +} + +void halbtc8821a2ant_set_sw_full_time_dac_swing(IN struct btc_coexist + *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) +{ + if (sw_dac_swing_on) + halbtc8821a2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl); + else + halbtc8821a2ant_set_dac_swing_reg(btcoexist, 0x18); +} + + +void halbtc8821a2ant_dac_swing(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) +{ + coex_dm->cur_dac_swing_on = dac_swing_on; + coex_dm->cur_dac_swing_lvl = dac_swing_lvl; + + if (!force_exec) { + if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && + (coex_dm->pre_dac_swing_lvl == + coex_dm->cur_dac_swing_lvl)) + return; + } + delay_ms(30); + halbtc8821a2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, + dac_swing_lvl); + + coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; + coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; +} + +void halbtc8821a2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, + IN boolean adc_back_off) +{ + if (adc_back_off) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB BackOff Level On!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB BackOff Level Off!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1); + } +} + +void halbtc8821a2ant_adc_back_off(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean adc_back_off) +{ + coex_dm->cur_adc_back_off = adc_back_off; + + if (!force_exec) { + if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) + return; + } + halbtc8821a2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off); + + coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; +} + +void halbtc8821a2ant_set_agc_table(IN struct btc_coexist *btcoexist, + IN boolean agc_table_en) +{ + u8 rssi_adjust_val = 0; + + /* =================BB AGC Gain Table */ + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table On!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6e1A0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6d1B0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6c1C0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6b1D0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6a1E0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x691F0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x68200001); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table Off!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001); + btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa4200001); + } + + + /* =================RF Gain */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Agc Table On!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, + 0x38fff); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, + 0x38ffe); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Agc Table Off!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, + 0x380c3); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, + 0x28ce6); + } + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x1); + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Agc Table On!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, + 0x38fff); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, + 0x38ffe); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Agc Table Off!\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, + 0x380c3); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, + 0x28ce6); + } + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x0); + + /* set rssi_adjust_val for wifi module. */ + if (agc_table_en) + rssi_adjust_val = 8; + btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, + &rssi_adjust_val); +} + +void halbtc8821a2ant_agc_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean agc_table_en) +{ + coex_dm->cur_agc_table_en = agc_table_en; + + if (!force_exec) { + if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) + return; + } + halbtc8821a2ant_set_agc_table(btcoexist, agc_table_en); + + coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; +} + +void halbtc8821a2ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8821a2ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8821a2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8821a2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_sta->coex_table_type = type; + + switch (type) { + case 0: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5afa5afa, 0xffffff, 0x3); + break; + case 2: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3); + break; + case 3: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 4: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0xffffffff, 0xffffffff, 0xffffff, 0x3); + break; + case 5: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3); + break; + case 6: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 7: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 8: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 9: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 10: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 11: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 12: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 13: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 14: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); + break; + case 15: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 16: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3); + break; + case 17: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0xfafafafa, 0xfafafafa, 0xffffff, 0x3); + break; + case 18: + halbtc8821a2ant_coex_table(btcoexist, force_exec, + 0x5555555f, 0x5ada5ada, 0xffffff, 0x3); + break; + default: + break; + } +} + +void halbtc8821a2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 h2c_parameter[1] = {0}; + + if (enable) + h2c_parameter[0] |= BIT(0); /* function enable */ + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + +void halbtc8821a2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8821a2ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8821a2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8821a2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8821a2ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8821a2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + + h2c_parameter[0] = byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = byte5; + + coex_dm->ps_tdma_para[0] = byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); +} + +void halbtc8821a2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, + IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, + IN boolean limited_dig, IN boolean bt_lna_constrain) +{ + /* + u32 wifi_bw; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if(BTC_WIFI_BW_HT40 != wifi_bw) + { + if (shrink_rx_lpf) + shrink_rx_lpf = false; + } + */ + + /* halbtc8821a2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); */ + halbtc8821a2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); +} + +void halbtc8821a2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, + IN boolean agc_table_shift, IN boolean adc_back_off, + IN boolean sw_dac_swing, IN u32 dac_swing_lvl) +{ + /* halbtc8821a2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */ + /* halbtc8821a2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */ + halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, + dac_swing_lvl); +} + +void halbtc8821a2ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u32 u32tmp = 0; + u8 h2c_parameter[2] = {0}; + + if (init_hwcfg) { + /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ + u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp &= ~BIT(23); + u32tmp |= BIT(24); + btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); + + btcoexist->btc_write_4byte(btcoexist, 0x974, 0x3ff); + /* btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77); */ + + if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { + /* tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ + h2c_parameter[0] = 1; + h2c_parameter[1] = 1; + btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, + h2c_parameter); + } else { + /* tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ + h2c_parameter[0] = 0; + h2c_parameter[1] = 1; + btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, + h2c_parameter); + } + } + + /* ext switch setting */ + switch (ant_pos_type) { + case BTC_ANT_WIFI_AT_MAIN: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, + 0x30, 0x1); + break; + case BTC_ANT_WIFI_AT_AUX: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, + 0x30, 0x2); + break; + } +} + +void halbtc8821a2ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + u8 wifi_rssi_state1, bt_rssi_state; + + + wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, + BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + if (!(BTC_RSSI_HIGH(wifi_rssi_state1) && + BTC_RSSI_HIGH(bt_rssi_state)) && turn_on) { + type = type + 100; /* for WiFi RSSI low or BT RSSI low */ + } + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) + return; + } + if (turn_on) { + switch (type) { + case 1: + default: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */ + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c, 0x03, 0xf1, 0x90); + break; + case 2: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); */ + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x2d, 0x03, 0xf1, 0x90); + break; + case 3: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1c, 0x3, 0xf1, 0x90); + break; + case 4: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x10, 0x03, 0xf1, 0x90); + break; + case 5: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); */ + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c, 0x3, 0x70, 0x90); + break; + case 6: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); */ + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x2d, 0x3, 0x70, 0x90); + break; + case 7: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1c, 0x3, 0x70, 0x90); + break; + case 8: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xa3, + 0x10, 0x3, 0x70, 0x90); + break; + case 9: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */ + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c, 0x03, 0xf1, 0x90); + break; + case 10: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); */ + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x2d, 0x03, 0xf1, 0x90); + break; + case 11: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0xa, 0xa, 0xe1, 0x90); */ + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1c, 0x3, 0xf1, 0x90); + break; + case 12: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); */ + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x10, 0x3, 0xf1, 0x90); + break; + case 13: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); */ + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c, 0x3, 0x70, 0x90); + break; + case 14: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); */ + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x2d, 0x3, 0x70, 0x90); + break; + case 15: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0xa, 0xa, 0x60, 0x90); */ + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1c, 0x3, 0x70, 0x90); + break; + case 16: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, 0x60, 0x90); */ + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x10, 0x3, 0x70, 0x90); + break; + case 17: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xa3, + 0x2f, 0x2f, 0x60, 0x90); + break; + case 18: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x5, 0x5, 0xe1, 0x90); + break; + case 19: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x25, 0xe1, 0x90); + break; + case 20: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x25, 0x25, 0x60, 0x90); + break; + case 21: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x15, 0x03, 0x70, 0x90); + break; + case 23: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x1e, 0x03, 0xf0, 0x14); + break; + case 24: + case 124: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x3c, 0x03, 0x70, 0x50); + break; + /* case25/case125 : for lenovo bt pan tp degrade<30% while wifi downlink */ + case 25: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x14, 0x03, 0xf1, 0x90); + break; + case 26: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x30, 0x03, 0xf1, 0x90); + break; + case 27: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x23, 0x03, 0x70, 0x50); + break; + case 28: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x1e, 0x03, 0x70, 0x50); + break; + case 71: + /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */ + + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c, 0x03, 0xf1, 0x90); + break; + case 101: + case 105: + case 171: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x3a, 0x03, 0x70, 0x50); + break; + case 102: + case 106: + case 110: + case 114: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x2d, 0x03, 0x70, 0x50); + break; + case 103: + case 107: + case 111: + case 115: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x1c, 0x03, 0x70, 0x50); + break; + case 104: + case 108: + case 112: + case 116: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x10, 0x03, 0x70, 0x50); + break; + case 109: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c, 0x03, 0xf1, 0x90); + break; + case 113: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x3c, 0x03, 0x70, 0x90); + break; + case 121: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x15, 0x03, 0x70, 0x90); + break; + case 22: + case 122: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, + 0x35, 0x03, 0x71, 0x11); + break; + case 123: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x1c, 0x03, 0x70, 0x54); + break; + /* case25/case125 : for lenovo bt pan tp degrade<30% while wifi downlink */ + case 125: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x14, 0x03, 0x70, 0x50); + break; + case 126: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x30, 0x03, 0x70, 0x50); + break; + case 127: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, + 0x28, 0x03, 0x70, 0x50); + break; + } + } else { + /* disable PS tdma */ + switch (type) { + case 0: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x40, 0x0); + break; + case 1: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x48, 0x0); + break; + default: + halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x40, 0x0); + break; + } + } + + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; +} + +void halbtc8821a2ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + +void halbtc8821a2ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = false; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + /* recover to original 32k low power setting */ + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + case BTC_PS_LPS_ON: + halbtc8821a2ant_ps_tdma_check_for_power_save_state( + btcoexist, true); + halbtc8821a2ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + coex_sta->force_lps_on = true; + break; + case BTC_PS_LPS_OFF: + halbtc8821a2ant_ps_tdma_check_for_power_save_state( + btcoexist, false); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + default: + break; + } +} + + +void halbtc8821a2ant_coex_all_off(IN struct btc_coexist *btcoexist) +{ + /* fw all off */ + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* sw all off */ + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + + /* hw all off */ + /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8821a2ant_coex_under_5g(IN struct btc_coexist *btcoexist) +{ + halbtc8821a2ant_coex_all_off(btcoexist); + + halbtc8821a2ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true); +} + +void halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + /* force to reset coex mechanism */ + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8821a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); + halbtc8821a2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0); + + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); +} + +void halbtc8821a2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + boolean wifi_connected = false; + boolean low_pwr_disable = true; + boolean scan = false, link = false, roam = false; + + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, + BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + if (scan || link || roam) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi link process + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 7); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); + } else if (wifi_connected) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 7); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi no-link + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + } + + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + +} + + +void halbtc8821a2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist) +{ + u8 u8tmpa, u8tmpb; + + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); + + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + + + + u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); + u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa, + u8tmpb); + BTC_TRACE(trace_buf); +} + +boolean halbtc8821a2ant_action_wifi_idle_process(IN struct btc_coexist + *btcoexist) +{ + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u8 ap_num = 0; + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + /* wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); */ + wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, + BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES - 20, 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); + + /* define the office environment */ + if (BTC_RSSI_HIGH(wifi_rssi_state1) && + (coex_sta->hid_exist == true) && + (coex_sta->a2dp_exist == true)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi idle process for BT HID+A2DP exist!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6); + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* sw all off */ + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, + false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + + return true; + } + + /* */ + else if (coex_sta->pan_exist == true) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi idle process for BT PAN exist!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6); + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* sw all off */ + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, + false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + + return true; + } + + else { + halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x18); + return false; + } + + +} + + + +boolean halbtc8821a2ant_is_common_action(IN struct btc_coexist *btcoexist) +{ + boolean common = false, wifi_connected = false, wifi_busy = false; + boolean bt_hs_on = false, low_pwr_disable = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_connected) { + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x8); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non-connected idle!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, + 0x0); + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, + false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, + 0x18); + + common = true; + } else { + if (BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, + false, false, 0x8); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, + 0xfffff, 0x0); + halbtc8821a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + halbtc8821a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, + 0xb); + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, + false, + false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + + common = true; + } else if (BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status) { + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + + if (bt_hs_on) + return false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, + false, false, 0x8); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, + 0xfffff, 0x0); + halbtc8821a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + halbtc8821a2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 1); + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, + 0xb); + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + + common = true; + } else { + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + + if (wifi_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); + BTC_TRACE(trace_buf); + common = false; + /* common = halbtc8821a2ant_action_wifi_idle_process(btcoexist); */ + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + /* common = false; */ + common = halbtc8821a2ant_action_wifi_idle_process( + btcoexist); + } + } + } + + return common; +} +void halbtc8821a2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, + IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) +{ + static s32 up, dn, m, n, wait_count; + s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ + u8 retry_count = 0; + + if (!coex_dm->auto_tdma_adjust) { + coex_dm->auto_tdma_adjust = true; + { + if (sco_hid) { + if (tx_pause) { + if (max_interval == 1) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 13); + coex_dm->ps_tdma_du_adj_type = + 13; + } else if (max_interval == 2) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (max_interval == 3) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } + } else { + if (max_interval == 1) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = + 9; + } else if (max_interval == 2) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (max_interval == 3) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } + } + } else { + if (tx_pause) { + if (max_interval == 1) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 5); + coex_dm->ps_tdma_du_adj_type = + 5; + } else if (max_interval == 2) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (max_interval == 3) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } + } else { + if (max_interval == 1) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = + 1; + } else if (max_interval == 2) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (max_interval == 3) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } + } + } + } + /* ============ */ + up = 0; + dn = 0; + m = 1; + n = 3; + result = 0; + wait_count = 0; + } else { + /* acquire the BT TRx retry count from BT_Info byte2 */ + retry_count = coex_sta->bt_retry_cnt; + result = 0; + wait_count++; + + if (retry_count == + 0) { /* no retry in the last 2-second duration */ + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if (up >= n) { /* if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration */ + wait_count = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + } + } else if (retry_count <= + 3) { /* <=3 retry in the last 2-second duration */ + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) { /* if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration */ + if (wait_count <= 2) + m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ + else + m = 1; + + if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + } else { /* retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration */ + if (wait_count == 1) + m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ + else + m = 1; + + if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ + m = 20; + + n = 3 * m; + up = 0; + dn = 0; + wait_count = 0; + result = -1; + } + + if (max_interval == 1) { + if (tx_pause) { + if (coex_dm->cur_ps_tdma == 71) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 5); + coex_dm->ps_tdma_du_adj_type = 5; + } else if (coex_dm->cur_ps_tdma == 1) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 5); + coex_dm->ps_tdma_du_adj_type = 5; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 6); + coex_dm->ps_tdma_du_adj_type = 6; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 4) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 8); + coex_dm->ps_tdma_du_adj_type = 8; + } + if (coex_dm->cur_ps_tdma == 9) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 13); + coex_dm->ps_tdma_du_adj_type = 13; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + coex_dm->ps_tdma_du_adj_type = 14; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 16); + coex_dm->ps_tdma_du_adj_type = 16; + } + + if (result == -1) { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 8); + coex_dm->ps_tdma_du_adj_type = + 8; + } else if (coex_dm->cur_ps_tdma == 13) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 16); + coex_dm->ps_tdma_du_adj_type = + 16; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 8) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 5); + coex_dm->ps_tdma_du_adj_type = + 5; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 13); + coex_dm->ps_tdma_du_adj_type = + 13; + } + } + } else { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 71); + coex_dm->ps_tdma_du_adj_type = 71; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 8) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 4); + coex_dm->ps_tdma_du_adj_type = 4; + } + if (coex_dm->cur_ps_tdma == 13) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 9); + coex_dm->ps_tdma_du_adj_type = 9; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 10); + coex_dm->ps_tdma_du_adj_type = 10; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 12); + coex_dm->ps_tdma_du_adj_type = 12; + } + + if (result == -1) { + if (coex_dm->cur_ps_tdma == 71) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = + 1; + } else if (coex_dm->cur_ps_tdma == 1) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 4); + coex_dm->ps_tdma_du_adj_type = + 4; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 12); + coex_dm->ps_tdma_du_adj_type = + 12; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 4) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 1); + coex_dm->ps_tdma_du_adj_type = + 1; + } else if (coex_dm->cur_ps_tdma == 1) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 71); + coex_dm->ps_tdma_du_adj_type = + 71; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 9); + coex_dm->ps_tdma_du_adj_type = + 9; + } + } + } + } else if (max_interval == 2) { + if (tx_pause) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 6); + coex_dm->ps_tdma_du_adj_type = 6; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 6); + coex_dm->ps_tdma_du_adj_type = 6; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 4) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 8); + coex_dm->ps_tdma_du_adj_type = 8; + } + if (coex_dm->cur_ps_tdma == 9) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + coex_dm->ps_tdma_du_adj_type = 14; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + coex_dm->ps_tdma_du_adj_type = 14; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 16); + coex_dm->ps_tdma_du_adj_type = 16; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 8); + coex_dm->ps_tdma_du_adj_type = + 8; + } else if (coex_dm->cur_ps_tdma == 13) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 16); + coex_dm->ps_tdma_du_adj_type = + 16; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 8) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 6); + coex_dm->ps_tdma_du_adj_type = + 6; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 14); + coex_dm->ps_tdma_du_adj_type = + 14; + } + } + } else { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 2); + coex_dm->ps_tdma_du_adj_type = 2; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 8) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 4); + coex_dm->ps_tdma_du_adj_type = 4; + } + if (coex_dm->cur_ps_tdma == 13) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 10); + coex_dm->ps_tdma_du_adj_type = 10; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 10); + coex_dm->ps_tdma_du_adj_type = 10; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 12); + coex_dm->ps_tdma_du_adj_type = 12; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 4); + coex_dm->ps_tdma_du_adj_type = + 4; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 12); + coex_dm->ps_tdma_du_adj_type = + 12; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 4) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 2); + coex_dm->ps_tdma_du_adj_type = + 2; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 10); + coex_dm->ps_tdma_du_adj_type = + 10; + } + } + } + } else if (max_interval == 3) { + if (tx_pause) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + coex_dm->ps_tdma_du_adj_type = 7; + } else if (coex_dm->cur_ps_tdma == 4) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 8); + coex_dm->ps_tdma_du_adj_type = 8; + } + if (coex_dm->cur_ps_tdma == 9) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 15); + coex_dm->ps_tdma_du_adj_type = 15; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 16); + coex_dm->ps_tdma_du_adj_type = 16; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 8); + coex_dm->ps_tdma_du_adj_type = + 8; + } else if (coex_dm->cur_ps_tdma == 13) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 16); + coex_dm->ps_tdma_du_adj_type = + 16; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 8) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 7); + coex_dm->ps_tdma_du_adj_type = + 7; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 15); + coex_dm->ps_tdma_du_adj_type = + 15; + } + } + } else { + if (coex_dm->cur_ps_tdma == 5) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 6) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 7) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 3); + coex_dm->ps_tdma_du_adj_type = 3; + } else if (coex_dm->cur_ps_tdma == 8) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 4); + coex_dm->ps_tdma_du_adj_type = 4; + } + if (coex_dm->cur_ps_tdma == 13) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 14) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 15) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 11); + coex_dm->ps_tdma_du_adj_type = 11; + } else if (coex_dm->cur_ps_tdma == 16) { + halbtc8821a2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 12); + coex_dm->ps_tdma_du_adj_type = 12; + } + if (result == -1) { + if (coex_dm->cur_ps_tdma == 1) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 4); + coex_dm->ps_tdma_du_adj_type = + 4; + } else if (coex_dm->cur_ps_tdma == 9) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 12); + coex_dm->ps_tdma_du_adj_type = + 12; + } + } else if (result == 1) { + if (coex_dm->cur_ps_tdma == 4) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 3) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 2) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 3); + coex_dm->ps_tdma_du_adj_type = + 3; + } else if (coex_dm->cur_ps_tdma == 12) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 11) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } else if (coex_dm->cur_ps_tdma == 10) { + halbtc8821a2ant_ps_tdma( + btcoexist, NORMAL_EXEC, + true, 11); + coex_dm->ps_tdma_du_adj_type = + 11; + } + } + } + } + } + + /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ + /* then we have to adjust it back to the previous record one. */ + if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { + boolean scan = false, link = false, roam = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", + coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + if (!scan && !link && !roam) + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + coex_dm->ps_tdma_du_adj_type); + else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); + BTC_TRACE(trace_buf); + } + } +} + +/* SCO only or SCO+PAN(HS) */ +void halbtc8821a2ant_action_sco(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 wifi_rssi_state, bt_rssi_state; + u32 wifi_bw; + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for SCO quality at 11b/g mode */ + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + else { /* for SCO quality & wifi performance balance at 11n mode */ + if (BTC_WIFI_BW_HT40 == wifi_bw) + halbtc8821a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else { + if (bt_link_info->sco_only) + halbtc8821a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 17); + else + halbtc8821a2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 12); + } + } + + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 0); /* for voice quality */ + + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + true, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + true, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + true, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + true, 0x18); + } + } +} + + +void halbtc8821a2ant_action_hid(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, bt_rssi_state; + u32 wifi_bw; + + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */ + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + else /* for HID quality & wifi performance balance at 11n mode */ + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 24); + + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ +void halbtc8821a2ant_action_a2dp(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + u8 ap_num = 0; + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, + BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); + + /* define the office environment */ + if ((ap_num >= 10) && BTC_RSSI_HIGH(wifi_rssi_state1) && + BTC_RSSI_HIGH(bt_rssi_state)) { + /* dbg_print(" AP#>10(%d)\n", ap_num); */ + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, + 0x0); + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x8); + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + /* halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); */ + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); + + /* sw mechanism */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + true, 0x6); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + true, 0x6); + } + return; + + } + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + } else { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 13); + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + } + + + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, false, 1); */ + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); + } else { + /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 1); */ + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); + } + + /* sw mechanism */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8821a2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, + BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + } else { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 13); + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + } + + halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 2); + + /* sw mechanism */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8821a2ant_action_pan_edr(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, + BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 10); + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + } else { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 13); + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + } + + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 26); + else + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 26); + + /* sw mechanism */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + + +/* PAN(HS) only */ +void halbtc8821a2ant_action_pan_hs(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, + BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +/* PAN(EDR)+A2DP */ +void halbtc8821a2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, + BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + else + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 12); + + if (BTC_WIFI_BW_HT40 == wifi_bw) + halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, + true, 3); + else + halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, + false, 3); + } else { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 13); + halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 3); + } + + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8821a2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, + BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + } else { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 14); + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + } + + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + if (BTC_WIFI_BW_HT40 == wifi_bw) { + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, + 3); + /* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, + 0xfffff, 0x780); + } else { + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, + 6); + /* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, + 0xfffff, 0x0); + } + halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, false, 2); + } else { + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + /* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, + 0x0); + halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 2); + } + + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +/* HID+A2DP+PAN(EDR) */ +void halbtc8821a2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, + BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); + + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + } else { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 14); + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + } + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + if (BTC_WIFI_BW_HT40 == wifi_bw) + halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, + true, 3); + else + halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, + false, 3); + } else + halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 3); + + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8821a2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) +{ + u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; + u32 wifi_bw; + u8 ap_num = 0; + + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); + + wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, + 0); + /* bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, 29, 0); */ + wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, + BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + bt_rssi_state = halbtc8821a2ant_bt_rssi_state(3, + BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 37); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x6); + + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_LEGACY == wifi_bw) { + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else if (BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + } else { + /* only 802.11N mode we have to dec bt power to 4 degree */ + if (BTC_RSSI_HIGH(bt_rssi_state)) { + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &ap_num); + /* need to check ap Number of Not */ + if (ap_num < 10) + halbtc8821a2ant_dec_bt_pwr(btcoexist, + NORMAL_EXEC, 4); + else + halbtc8821a2ant_dec_bt_pwr(btcoexist, + NORMAL_EXEC, 2); + } else if (BTC_RSSI_MEDIUM(bt_rssi_state)) + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + } + + if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 18); + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, 0x0); + } else { + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 18); + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + } + + if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || + (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, false, 3); */ + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 28); + } else { + /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 3); */ + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 28); + } + + /* sw mechanism */ + if (BTC_WIFI_BW_HT40 == wifi_bw) { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } else { + if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || + (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, + false, 0x18); + } else { + halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, + false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, + false, 0x18); + } + } +} + +void halbtc8821a2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) +{ + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* sw all off */ + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8821a2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); + halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* sw all off */ + halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); + halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); + + /* hw all off */ + /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ + halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); +} + +void halbtc8821a2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + boolean wifi_under_5g = false; + u8 algorithm = 0; + u32 num_of_wifi_link = 0; + u32 wifi_link_status = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean miracast_plus_bt = false; + boolean scan = false, link = false, roam = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_coex_under_5g(btcoexist); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->bt_whck_test) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under WHCK TEST!!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_bt_whck_test(btcoexist); + return; + } + + algorithm = halbtc8821a2ant_action_algorithm(btcoexist); + if (coex_sta->c2h_bt_inquiry_page && + (BT_8821A_2ANT_COEX_ALGO_PANHS != algorithm)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_bt_inquiry(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + if (scan || link || roam) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under Link Process !!\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_wifi_link_process(btcoexist); + return; + } + + /* for P2P */ + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", + num_of_wifi_link, wifi_link_status); + BTC_TRACE(trace_buf); + + if (bt_link_info->bt_link_exist) + miracast_plus_bt = true; + else + miracast_plus_bt = false; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + halbtc8821a2ant_action_wifi_multi_port(btcoexist); + + return; + } + + miracast_plus_bt = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + coex_dm->cur_algorithm = algorithm; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", + coex_dm->cur_algorithm); + BTC_TRACE(trace_buf); + + if (halbtc8821a2ant_is_common_action(btcoexist)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant common.\n"); + BTC_TRACE(trace_buf); + coex_dm->auto_tdma_adjust = false; + } else { + if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", + coex_dm->pre_algorithm, coex_dm->cur_algorithm); + BTC_TRACE(trace_buf); + coex_dm->auto_tdma_adjust = false; + } + switch (coex_dm->cur_algorithm) { + case BT_8821A_2ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_sco(btcoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID.\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_hid(btcoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_a2dp(btcoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_a2dp_pan_hs(btcoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_pan_edr(btcoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_pan_hs(btcoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_pan_edr_a2dp(btcoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_pan_edr_hid(btcoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_hid_a2dp_pan_edr( + btcoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_action_hid_a2dp(btcoexist); + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_coex_all_off(btcoexist); + break; + } + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + } +} + +void halbtc8821a2ant_wifi_off_hw_cfg(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[2] = {0}; + u32 fw_ver = 0; + + /* set wlan_act to low */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); + + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, + 0x780); /* WiFi goto standby while GNT_BT 0-->1 */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + if (fw_ver >= 0x180000) { + /* Use H2C to set GNT_BT to HIGH */ + h2c_parameter[0] = 1; + btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, h2c_parameter); + } else + btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); +} + +void halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean back_up) +{ + u8 u8tmp = 0; + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 2Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + /* Give bt_coex_supported_version the default value */ + coex_sta->bt_coex_supported_version = 0; + + /* 0xf0[15:12] --> Chip Cut information */ + coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, + 0xf1) & 0xf0) >> 4; + + /* backup rf 0x1e value */ + coex_dm->bt_rf_0x1e_backup = + btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff); + + /* 0x790[5:0]=0x5 */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); + u8tmp &= 0xc0; + u8tmp |= 0x5; + btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); + + /* Antenna config */ + halbtc8821a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true, + false); + coex_sta->dis_ver_info_cnt = 0; + + /* PTA parameter */ + halbtc8821a2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + /* Enable counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, + 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); +} + +/* ************************************************************ + * work around function start with wa_halbtc8821a2ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8821a2ant_ + * ************************************************************ */ +void ex_halbtc8821a2ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ + +} + +void ex_halbtc8821a2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ + + /* */ + /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + if (btcoexist->chip_interface == BTC_INTF_USB) { + /* fixed at S0 for USB interface */ + u8tmp |= 0x1; /* antenna inverse */ + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + } else { + /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ + if (board_info->single_ant_path == 0) { + } else if (board_info->single_ant_path == 1) { + /* set to S0 */ + u8tmp |= 0x1; /* antenna inverse */ + } + + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384, + u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, + u8tmp); + } +} + +void ex_halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8821a2ant_init_hw_config(btcoexist, true); +} + +void ex_halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821a2ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8821a2ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u32 u32tmp[4]; + u32 fw_ver = 0, bt_patch_ver = 0; + u32 bt_coex_ver = 0; + u32 phyver = 0; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", + "Ant PG number/ Ant mechanism:", + board_info->pg_ant_num, board_info->btdm_ant_num); + CL_PRINTF(cli_buf); + + /* btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); */ + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8821a_2ant, glcoex_ver_8821a_2ant, + glcoex_ver_btdesired_8821a_2ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (bt_coex_ver >= glcoex_ver_btdesired_8821a_2ant ? + "Match" : "Mis-Match"))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "Wifi channel informed to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %ddBm/ %d] ", + "BT [status/ rssi/ retryCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") + : ((BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", + "SCO/HID/PAN/A2DP", + bt_link_info->sco_exist, bt_link_info->hid_exist, + bt_link_info->pan_exist, bt_link_info->a2dp_exist); + CL_PRINTF(cli_buf); + + { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "BT Role", + (bt_link_info->slave_role) ? "Slave" : "Master"); + CL_PRINTF(cli_buf); + } + + bt_info_ext = coex_sta->bt_info_ext; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "BT Info A2DP rate", + (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); + CL_PRINTF(cli_buf); + + for (i = 0; i < BT_INFO_SRC_8821A_2ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8821a_2ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + /* Sw mechanism */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Sw mechanism]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", + "SM1[ShRf/ LpRA/ LimDig]", + coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, + coex_dm->limited_dig); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", + "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", + coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, + coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); + CL_PRINTF(cli_buf); + + /* Fw mechanism */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Fw mechanism]============"); + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", + "PS TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + coex_dm->auto_tdma_adjust); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "Coex Table Type", + coex_sta->coex_table_type); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", + "DecBtPwr/ IgnWlanAct", + coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act); + CL_PRINTF(cli_buf); + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", + "RF-A, 0x1e initVal", + coex_dm->bt_rf_0x1e_backup); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xc5b); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x880); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x778/0x880[29:25]/0xc58[29:25]", + u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25, + ((u8tmp[1] & 0x3e) >> 1)); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x764); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x76e); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x764/ 0x765/ 0x76e", + (u32tmp[0] & 0xff), (u32tmp[0] & 0xff00) >> 8, u8tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0xcb4[7:0](ctrl)/ 0xcb4[29:28](val)", + u32tmp[0] & 0xff, ((u32tmp[0] & 0x30000000) >> 28)); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x974); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x40/ 0x4c[24:23]/ 0x974", + u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u32tmp[1]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x550(bcn ctrl)/0x522", + u32tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0xc50(dig)/0x49c(null-drop)", + u32tmp[0] & 0xff, u8tmp[0]); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_CCK); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11n-agg", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_Err CCK/11g/11n/11n-agg", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", + u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(high-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x774(low-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx); + CL_PRINTF(cli_buf); +#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 1) + /* halbtc8821a2ant_monitor_bt_ctr(btcoexist); */ +#endif + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +void ex_halbtc8821a2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = true; + halbtc8821a2ant_wifi_off_hw_cfg(btcoexist); + halbtc8821a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + halbtc8821a2ant_coex_all_off(btcoexist); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = false; + halbtc8821a2ant_init_hw_config(btcoexist, false); + halbtc8821a2ant_init_coex_dm(btcoexist); + halbtc8821a2ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8821a2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = true; + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = false; + } +} + +void ex_halbtc8821a2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 u8tmpa, u8tmpb; + + u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); + u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); + + if (BTC_SCAN_START == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify\n"); + BTC_TRACE(trace_buf); + } else if (BTC_SCAN_FINISH == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify\n"); + BTC_TRACE(trace_buf); + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa, + u8tmpb); + BTC_TRACE(trace_buf); +} + +/* copy scan notify content to switch band notify */ +void ex_halbtc8821a2ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 u8tmpa, u8tmpb; + + u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); + u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); + + if (BTC_SCAN_START == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify\n"); + BTC_TRACE(trace_buf); + } else if (BTC_SCAN_FINISH == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify\n"); + BTC_TRACE(trace_buf); + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa, + u8tmpb); + BTC_TRACE(trace_buf); +} + +void ex_halbtc8821a2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (BTC_ASSOCIATE_START == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify\n"); + BTC_TRACE(trace_buf); + } else if (BTC_ASSOCIATE_FINISH == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify\n"); + BTC_TRACE(trace_buf); + } +} + +void ex_halbtc8821a2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + u8 ap_num = 0; + + if (BTC_MEDIA_CONNECT == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + } + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + h2c_parameter[0] = 0x1; + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else { + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &ap_num); + if (ap_num < 10) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); +} + +void ex_halbtc8821a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (type == BTC_PACKET_DHCP) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], DHCP Packet notify\n"); + BTC_TRACE(trace_buf); + } +} + +void ex_halbtc8821a2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 bt_info = 0; + u8 i, rsp_source = 0; + boolean bt_busy = false, limited_dig = false; + boolean wifi_connected = false, wifi_under_5g = false; + + coex_sta->c2h_bt_info_req_sent = false; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8821A_2ANT_MAX) + rsp_source = BT_INFO_SRC_8821A_2ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + if (i == 1) + bt_info = tmp_buf[i]; + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n"); + BTC_TRACE(trace_buf); + return; + } + + /* if 0xff, it means BT is under WHCK test */ + if (bt_info == 0xff) + coex_sta->bt_whck_test = true; + else + coex_sta->bt_whck_test = false; + + if (BT_INFO_SRC_8821A_2ANT_WIFI_FW != rsp_source) { + coex_sta->bt_retry_cnt = /* [3:0] */ + coex_sta->bt_info_c2h[rsp_source][2] & 0xf; + + coex_sta->bt_rssi = + coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; + + coex_sta->bt_info_ext = + coex_sta->bt_info_c2h[rsp_source][4]; + + coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] + & 0x40); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, + &coex_sta->bt_tx_rx_mask); + if (coex_sta->bt_tx_rx_mask) { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, + 0x3c, 0x01); + } + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + if (wifi_connected) + ex_halbtc8821a2ant_media_status_notify( + btcoexist, BTC_MEDIA_CONNECT); + else + ex_halbtc8821a2ant_media_status_notify( + btcoexist, BTC_MEDIA_DISCONNECT); + } + + + if (!btcoexist->manual_control && !wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info = 0x%x!!\n", + coex_sta->bt_info_ext); + BTC_TRACE(trace_buf); + if ((coex_sta->bt_info_ext & BIT(3))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3=1, wifi_connected=%d\n", + wifi_connected); + BTC_TRACE(trace_buf); + if (wifi_connected) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_ignore_wlan_act( + btcoexist, FORCE_EXEC, false); + } + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3=0, wifi_connected=%d\n", + wifi_connected); + BTC_TRACE(trace_buf); + /* BT already NOT ignore Wlan active, do nothing here. */ + if (!wifi_connected) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_ignore_wlan_act( + btcoexist, FORCE_EXEC, true); + } + } + } + +#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 0) + if ((coex_sta->bt_info_ext & BIT(4))) { + /* BT auto report already enabled, do nothing */ + } else + halbtc8821a2ant_bt_auto_report(btcoexist, FORCE_EXEC, + true); +#endif + } + + /* check BIT2 first ==> check if bt is under inquiry or page scan */ + if (bt_info & BT_INFO_8821A_2ANT_B_INQ_PAGE) + coex_sta->c2h_bt_inquiry_page = true; + else + coex_sta->c2h_bt_inquiry_page = false; + + /* set link exist status */ + if (!(bt_info & BT_INFO_8821A_2ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (bt_info & BT_INFO_8821A_2ANT_B_FTP) + coex_sta->pan_exist = true; + else + coex_sta->pan_exist = false; + if (bt_info & BT_INFO_8821A_2ANT_B_A2DP) + coex_sta->a2dp_exist = true; + else + coex_sta->a2dp_exist = false; + if (bt_info & BT_INFO_8821A_2ANT_B_HID) + coex_sta->hid_exist = true; + else + coex_sta->hid_exist = false; + if (bt_info & BT_INFO_8821A_2ANT_B_SCO_ESCO) + coex_sta->sco_exist = true; + else + coex_sta->sco_exist = false; + + if ((coex_sta->hid_exist == false) && + (coex_sta->c2h_bt_inquiry_page == false) && + (coex_sta->sco_exist == false)) { + if (coex_sta->high_priority_tx + + coex_sta->high_priority_rx >= 160) + coex_sta->hid_exist = true; + } + } + + halbtc8821a2ant_update_bt_link_info(btcoexist); + + if (!(bt_info & BT_INFO_8821A_2ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info == + BT_INFO_8821A_2ANT_B_CONNECTION) { /* connection exists but no busy */ + coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + BTC_TRACE(trace_buf); + } else if ((bt_info & BT_INFO_8821A_2ANT_B_SCO_ESCO) || + (bt_info & BT_INFO_8821A_2ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + BTC_TRACE(trace_buf); + } else if (bt_info & BT_INFO_8821A_2ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + BTC_TRACE(trace_buf); + } + + if ((BT_8821A_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8821A_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { + bt_busy = true; + limited_dig = true; + } else { + bt_busy = false; + limited_dig = false; + } + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + coex_dm->limited_dig = limited_dig; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); + + halbtc8821a2ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8821a2ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821a2ant_wifi_off_hw_cfg(btcoexist); + /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */ + /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); */ /*BT goto standby while GNT_BT 1-->0 */ + halbtc8821a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + + ex_halbtc8821a2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); +} + +void ex_halbtc8821a2ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_WIFI_PNP_SLEEP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_init_hw_config(btcoexist, false); + halbtc8821a2ant_init_coex_dm(btcoexist); + halbtc8821a2ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8821a2ant_periodical(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ==========================Periodical===========================\n"); + BTC_TRACE(trace_buf); + + if (coex_sta->dis_ver_info_cnt <= 5) { + coex_sta->dis_ver_info_cnt += 1; + if (coex_sta->dis_ver_info_cnt == 3) { + /* Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Set GNT_BT control by PTA\n"); + BTC_TRACE(trace_buf); + halbtc8821a2ant_set_ant_path(btcoexist, + BTC_ANT_WIFI_AT_MAIN, false, false); + } + } + + if (((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) && + (!coex_sta->bt_disabled)) + coex_sta->bt_coex_supported_version = + btcoexist->btc_get_bt_coex_supported_version(btcoexist); + + +#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 0) + halbtc8821a2ant_query_bt_info(btcoexist); + halbtc8821a2ant_monitor_bt_enable_disable(btcoexist); +#else + halbtc8821a2ant_monitor_bt_ctr(btcoexist); + halbtc8821a2ant_monitor_wifi_ctr(btcoexist); + halbtc8821a2ant_monitor_bt_enable_disable(btcoexist); + + if (halbtc8821a2ant_is_wifi_status_changed(btcoexist) || + coex_dm->auto_tdma_adjust) + halbtc8821a2ant_run_coexist_mechanism(btcoexist); +#endif +} + +#endif + +#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ diff --git a/hal/btc/halbtc8821a2ant.h b/hal/btc/halbtc8821a2ant.h new file mode 100644 index 0000000..d76f566 --- /dev/null +++ b/hal/btc/halbtc8821a2ant.h @@ -0,0 +1,225 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8821A_SUPPORT == 1) + +/* ******************************************* + * The following is for 8821A 2Ant BT Co-exist definition + * ******************************************* */ +#define BT_AUTO_REPORT_ONLY_8821A_2ANT 1 + + +#define BT_INFO_8821A_2ANT_B_FTP BIT(7) +#define BT_INFO_8821A_2ANT_B_A2DP BIT(6) +#define BT_INFO_8821A_2ANT_B_HID BIT(5) +#define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8821A_2ANT_B_CONNECTION BIT(0) + +#define BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT 2 + + +#define BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 /* WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */ +#define BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES 46 /* BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */ + +enum bt_info_src_8821a_2ant { + BT_INFO_SRC_8821A_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8821A_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8821A_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8821A_2ANT_MAX +}; + +enum bt_8821a_2ant_bt_status { + BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8821A_2ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8821A_2ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8821A_2ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8821A_2ANT_BT_STATUS_MAX +}; + +enum bt_8821a_2ant_coex_algo { + BT_8821A_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8821A_2ANT_COEX_ALGO_SCO = 0x1, + BT_8821A_2ANT_COEX_ALGO_HID = 0x2, + BT_8821A_2ANT_COEX_ALGO_A2DP = 0x3, + BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8821A_2ANT_COEX_ALGO_PANEDR = 0x5, + BT_8821A_2ANT_COEX_ALGO_PANHS = 0x6, + BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8821A_2ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8821A_2ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8821A_2ANT_COEX_ALGO_MAX = 0xb, +}; + +struct coex_dm_8821a_2ant { + /* fw mechanism */ + u8 pre_bt_dec_pwr_lvl; + u8 cur_bt_dec_pwr_lvl; + u8 pre_fw_dac_swing_lvl; + u8 cur_fw_dac_swing_lvl; + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean reset_tdma_adjust; + boolean auto_tdma_adjust; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + + /* sw mechanism */ + boolean pre_rf_rx_lpf_shrink; + boolean cur_rf_rx_lpf_shrink; + u32 bt_rf_0x1e_backup; + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + boolean pre_dac_swing_on; + u32 pre_dac_swing_lvl; + boolean cur_dac_swing_on; + u32 cur_dac_swing_lvl; + boolean pre_adc_back_off; + boolean cur_adc_back_off; + boolean pre_agc_table_en; + boolean cur_agc_table_en; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + boolean need_recover0x948; + u32 backup0x948; + + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; +}; + +struct coex_sta_8821a_2ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + + boolean under_lps; + boolean under_ips; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + u8 bt_rssi; + boolean bt_tx_rx_mask; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + boolean c2h_bt_info_req_sent; + u8 bt_info_c2h[BT_INFO_SRC_8821A_2ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8821A_2ANT_MAX]; + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + u8 bt_retry_cnt; + u8 bt_info_ext; + u8 scan_ap_num; + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + + u32 bt_coex_supported_version; + u8 cut_version; + u8 coex_table_type; + boolean force_lps_on; + + u8 dis_ver_info_cnt; +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8821a2ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8821a2ant_pre_load_firmware(IN struct btc_coexist *btcoexist); +void ex_halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8821a2ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a2ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a2ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821a2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8821a2ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8821a2ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8821a2ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8821a2ant_display_coex_info(IN struct btc_coexist *btcoexist); + +#else +#define ex_halbtc8821a2ant_power_on_setting(btcoexist) +#define ex_halbtc8821a2ant_pre_load_firmware(btcoexist) +#define ex_halbtc8821a2ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8821a2ant_init_coex_dm(btcoexist) +#define ex_halbtc8821a2ant_ips_notify(btcoexist, type) +#define ex_halbtc8821a2ant_lps_notify(btcoexist, type) +#define ex_halbtc8821a2ant_scan_notify(btcoexist, type) +#define ex_halbtc8821a2ant_switchband_notify(btcoexist, type) +#define ex_halbtc8821a2ant_connect_notify(btcoexist, type) +#define ex_halbtc8821a2ant_media_status_notify(btcoexist, type) +#define ex_halbtc8821a2ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8821a2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8821a2ant_halt_notify(btcoexist) +#define ex_halbtc8821a2ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8821a2ant_periodical(btcoexist) +#define ex_halbtc8821a2ant_display_coex_info(btcoexist) +#endif + +#endif + diff --git a/hal/btc/halbtc8821c1ant.c b/hal/btc/halbtc8821c1ant.c new file mode 100644 index 0000000..f9f2081 --- /dev/null +++ b/hal/btc/halbtc8821c1ant.c @@ -0,0 +1,5357 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for RTL8821C Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8821C_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8821c_1ant glcoex_dm_8821c_1ant; +static struct coex_dm_8821c_1ant *coex_dm = &glcoex_dm_8821c_1ant; +static struct coex_sta_8821c_1ant glcoex_sta_8821c_1ant; +static struct coex_sta_8821c_1ant *coex_sta = &glcoex_sta_8821c_1ant; +static struct psdscan_sta_8821c_1ant gl_psd_scan_8821c_1ant; +static struct psdscan_sta_8821c_1ant *psd_scan = &gl_psd_scan_8821c_1ant; +static struct rfe_type_8821c_1ant gl_rfe_type_8821c_1ant; +static struct rfe_type_8821c_1ant *rfe_type = &gl_rfe_type_8821c_1ant; + + +const char *const glbt_info_src_8821c_1ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u32 glcoex_ver_date_8821c_1ant = 20161107; +u32 glcoex_ver_8821c_1ant = 0x0a; +u32 glcoex_ver_btdesired_8821c_1ant = 0x0a; + + +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8821c1ant_ + * ************************************************************ */ +u8 halbtc8821c1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_bt_rssi_state; + } + + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + +u8 halbtc8821c1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_wifi_rssi_state[index]; + } + + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; + + return wifi_rssi_state; +} + +void halbtc8821c1ant_update_ra_mask(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 dis_rate_mask) +{ + coex_dm->cur_ra_mask = dis_rate_mask; + + if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) + btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, + &coex_dm->cur_ra_mask); + coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; +} + +void halbtc8821c1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + boolean wifi_under_b_mode = false; + + coex_dm->cur_arfr_type = type; + + if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { + switch (coex_dm->cur_arfr_type) { + case 0: /* normal mode */ + btcoexist->btc_write_4byte(btcoexist, 0x430, + coex_dm->backup_arfr_cnt1); + btcoexist->btc_write_4byte(btcoexist, 0x434, + coex_dm->backup_arfr_cnt2); + break; + case 1: + btcoexist->btc_get(btcoexist, + BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + if (wifi_under_b_mode) { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x01010101); + } else { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x04030201); + } + break; + default: + break; + } + } + + coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; +} + +void halbtc8821c1ant_retry_limit(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_retry_limit_type = type; + + if (force_exec || + (coex_dm->pre_retry_limit_type != + coex_dm->cur_retry_limit_type)) { + switch (coex_dm->cur_retry_limit_type) { + case 0: /* normal mode */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + coex_dm->backup_retry_limit); + break; + case 1: /* retry limit=8 */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + 0x0808); + break; + default: + break; + } + } + + coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; +} + +void halbtc8821c1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_ampdu_time_type = type; + + if (force_exec || + (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { + switch (coex_dm->cur_ampdu_time_type) { + case 0: /* normal mode */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + coex_dm->backup_ampdu_max_time); + break; + case 1: /* AMPDU timw = 0x38 * 32us */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + 0x38); + break; + default: + break; + } + } + + coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; +} + +void halbtc8821c1ant_limited_tx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, + IN u8 retry_limit_type, IN u8 ampdu_time_type) +{ + switch (ra_mask_type) { + case 0: /* normal mode */ + halbtc8821c1ant_update_ra_mask(btcoexist, force_exec, + 0x0); + break; + case 1: /* disable cck 1/2 */ + halbtc8821c1ant_update_ra_mask(btcoexist, force_exec, + 0x00000003); + break; + case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ + halbtc8821c1ant_update_ra_mask(btcoexist, force_exec, + 0x0001f1f7); + break; + default: + break; + } + + halbtc8821c1ant_auto_rate_fallback_retry(btcoexist, force_exec, + arfr_type); + halbtc8821c1ant_retry_limit(btcoexist, force_exec, retry_limit_type); + halbtc8821c1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); +} + +void halbtc8821c1ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +void halbtc8821c1ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No query BT info because BT is disabled!\n"); + BTC_TRACE(trace_buf); + return; + } + + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WL query BT info!!\n"); + BTC_TRACE(trace_buf); +} + +void halbtc8821c1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, + cnt_autoslot_hang = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ + /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); + + BTC_TRACE(trace_buf); + + if (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + if (coex_sta->high_priority_rx >= 15) { + if (cnt_overhead < 3) + cnt_overhead++; + + if (cnt_overhead == 3) + coex_sta->is_hiPri_rx_overhead = true; + + } else { + if (cnt_overhead > 0) + cnt_overhead--; + + if (cnt_overhead == 0) + coex_sta->is_hiPri_rx_overhead = false; + } + } + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + + if ((coex_sta->low_priority_tx > 1150) && + (!coex_sta->c2h_bt_inquiry_page)) + coex_sta->pop_event_cnt++; + + if ((coex_sta->low_priority_rx >= 1150) && + (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) + && (!coex_sta->under_ips) + && (!coex_sta->c2h_bt_inquiry_page) + && ((bt_link_info->a2dp_exist) || (bt_link_info->pan_exist))) { + if (cnt_slave >= 2) { + bt_link_info->slave_role = true; + cnt_slave = 2; + } else + cnt_slave++; + } else { + if (cnt_slave == 0) { + bt_link_info->slave_role = false; + cnt_slave = 0; + } else + cnt_slave--; + } + + if (coex_sta->is_tdma_btautoslot) { + if ((coex_sta->low_priority_tx >= 1300) && + (coex_sta->low_priority_rx <= 150)) { + if (cnt_autoslot_hang >= 2) { + coex_sta->is_tdma_btautoslot_hang = true; + cnt_autoslot_hang = 2; + } else + cnt_autoslot_hang++; + } else { + if (cnt_autoslot_hang == 0) { + coex_sta->is_tdma_btautoslot_hang = false; + cnt_autoslot_hang = 0; + } else + cnt_autoslot_hang--; + } + } + + if (!coex_sta->bt_disabled) { + + if ((coex_sta->high_priority_tx == 0) && + (coex_sta->high_priority_rx == 0) && + (coex_sta->low_priority_tx == 0) && + (coex_sta->low_priority_rx == 0)) { + num_of_bt_counter_chk++; + if (num_of_bt_counter_chk >= 3) { + halbtc8821c1ant_query_bt_info(btcoexist); + num_of_bt_counter_chk = 0; + } + } + } + +} + + + +void halbtc8821c1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ +#if 1 + s32 wifi_rssi = 0; + boolean wifi_busy = false, wifi_under_b_mode = false, + wifi_scan = false; + boolean bt_idle = false, wl_idle = false; + static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, + wl_noisy_count1 = 3, wl_noisy_count2 = 0; + u32 total_cnt, reg_val1, reg_val2, cck_cnt; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_VHT); + + cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; + + if (cck_cnt > 250) { + if (wl_noisy_count2 < 3) + wl_noisy_count2++; + + if (wl_noisy_count2 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count1 = 0; + } + + } else if (cck_cnt < 50) { + if (wl_noisy_count0 < 3) + wl_noisy_count0++; + + if (wl_noisy_count0 == 3) { + wl_noisy_count1 = 0; + wl_noisy_count2 = 0; + } + + } else { + if (wl_noisy_count1 < 3) + wl_noisy_count1++; + + if (wl_noisy_count1 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count2 = 0; + } + } + + if (wl_noisy_count2 == 3) + coex_sta->wl_noisy_level = 2; + else if (wl_noisy_count1 == 3) + coex_sta->wl_noisy_level = 1; + else + coex_sta->wl_noisy_level = 0; + + if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { + total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht; + + if ((coex_dm->bt_status == BT_8821C_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY) + || + (coex_dm->bt_status == BT_8821C_1ANT_BT_STATUS_SCO_BUSY)) { + if (coex_sta->crc_ok_cck > (total_cnt - + coex_sta->crc_ok_cck)) { + if (cck_lock_counter < 3) + cck_lock_counter++; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + if (!coex_sta->pre_ccklock) { + + if (cck_lock_counter >= 3) + coex_sta->cck_lock = true; + else + coex_sta->cck_lock = false; + } else { + if (cck_lock_counter == 0) + coex_sta->cck_lock = false; + else + coex_sta->cck_lock = true; + } + + if (coex_sta->cck_lock) + coex_sta->cck_ever_lock = true; + + coex_sta->pre_ccklock = coex_sta->cck_lock; + +#endif +} + +void halbtc8821c1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + boolean bt_busy = false; + + + coex_sta->num_of_profile = 0; + + /* set link exist status */ + if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_FTP) { + coex_sta->pan_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->pan_exist = false; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_A2DP) { + coex_sta->a2dp_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->a2dp_exist = false; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_HID) { + coex_sta->hid_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->hid_exist = false; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) { + coex_sta->sco_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->sco_exist = false; + + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + bt_link_info->acl_busy = coex_sta->acl_busy; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = true; + bt_link_info->bt_link_exist = true; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = true; + else + bt_link_info->sco_only = false; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = true; + else + bt_link_info->a2dp_only = false; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = true; + else + bt_link_info->pan_only = false; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = true; + else + bt_link_info->hid_only = false; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_INQ_PAGE) { + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_INQ_PAGE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); + } else if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + } else if (coex_sta->bt_info == BT_INFO_8821C_1ANT_B_CONNECTION) { + /* connection exists but no busy */ + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + } else if (((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_BUSY)) && + (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_ACL_BUSY)) { + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); + } else if ((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + } else if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + } else { + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + } + + BTC_TRACE(trace_buf); + + if ((BT_8821C_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + bt_busy = true; + else + bt_busy = false; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); +} + +void halbtc8821c1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + h2c_parameter[0] = + 0x1; /* enable BT AFH skip WL channel for 8821c because BT Rx LO interference */ + /* h2c_parameter[0] = 0x0; */ + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); + +} + +u8 halbtc8821c1ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + u8 algorithm = BT_8821C_1ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_HID_A2DP; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +void halbtc8821c1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean enable_auto_report) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = 0; + + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); + + btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); +} + +void halbtc8821c1ant_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable_auto_report) +{ + coex_dm->cur_bt_auto_report = enable_auto_report; + + if (!force_exec) { + if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) + return; + } + halbtc8821c1ant_set_bt_auto_report(btcoexist, + coex_dm->cur_bt_auto_report); + + coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; +} + + +void halbtc8821c1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + +#if 1 + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == + coex_dm->cur_low_penalty_ra) + return; + } + + if (low_penalty_ra) + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15); + else + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; + +#endif + +} + +void halbtc8821c1ant_write_score_board( + IN struct btc_coexist *btcoexist, + IN u16 bitpos, + IN boolean state +) +{ + + static u16 originalval = 0x8002, preval = 0x0; + + if (state) + originalval = originalval | bitpos; + else + originalval = originalval & (~bitpos); + + if (originalval != preval) { + + preval = originalval; + btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c1ant_write_score_board: return for nochange\n"); + BTC_TRACE(trace_buf); + } +} + +void halbtc8821c1ant_read_score_board( + IN struct btc_coexist *btcoexist, + IN u16 *score_board_val +) +{ + + *score_board_val = (btcoexist->btc_read_2byte(btcoexist, + 0xaa)) & 0x7fff; +} + +void halbtc8821c1ant_post_state_to_bt( + IN struct btc_coexist *btcoexist, + IN u16 type, + IN boolean state +) +{ + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c1ant_post_state_to_bt: type = %d, state =%d\n", + type, state); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_write_score_board(btcoexist, (u16) type, state); +} + +boolean halbtc8821c1ant_is_wifibt_status_changed(IN struct btc_coexist + *btcoexist) +{ + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false, pre_bt_off = false, + pre_bt_slave = false; + static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (coex_sta->bt_disabled != pre_bt_off) { + pre_bt_off = coex_sta->bt_disabled; + + if (coex_sta->bt_disabled) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + return true; + } + + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + + if (wifi_busy) + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, true); + else + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, false); + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { + pre_wl_noisy_level = coex_sta->wl_noisy_level; + return true; + } + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->hid_busy_num != pre_hid_busy_num) { + pre_hid_busy_num = coex_sta->hid_busy_num; + return true; + } + } + + if (bt_link_info->slave_role != pre_bt_slave) { + pre_bt_slave = bt_link_info->slave_role; + return true; + } + + return false; +} + + +void halbtc8821c1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = true, bt_disabled = false, wifi_under_5g = false; + u16 u16tmp; + + /* This function check if bt is disabled */ +#if 0 + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = false; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = false; + + +#else + + /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */ + halbtc8821c1ant_read_score_board(btcoexist, &u16tmp); + + bt_active = u16tmp & BIT(1); + + +#endif + + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } else { + + bt_disable_cnt++; + if (bt_disable_cnt >= 10) { + bt_disabled = true; + bt_disable_cnt = 10; + } + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((wifi_under_5g) || (bt_disabled)) + halbtc8821c1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); + else + halbtc8821c1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true); + + + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + } + +} + +void halbtc8821c1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, + boolean isenable) +{ +#if BT_8821C_1ANT_COEX_DBG + static u8 bitVal[5] = {0, 0, 0, 0, 0}; + static boolean state = false; + /* + if (state ==isenable) + return; + else + state = isenable; + */ + if (isenable) { + + /* enable GNT_WL, GNT_BT to GPIO for debug */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); + + /* store original value */ + bitVal[0] = (btcoexist->btc_read_1byte(btcoexist, + 0x66) & BIT(4)) >> 4; /*0x66[4] */ + bitVal[1] = (btcoexist->btc_read_1byte(btcoexist, + 0x67) & BIT(0)); /*0x66[8] */ + bitVal[2] = (btcoexist->btc_read_1byte(btcoexist, + 0x42) & BIT(3)) >> 3; /*0x40[19] */ + bitVal[3] = (btcoexist->btc_read_1byte(btcoexist, + 0x65) & BIT(7)) >> 7; /*0x64[15] */ + bitVal[4] = (btcoexist->btc_read_1byte(btcoexist, + 0x72) & BIT(2)) >> 2; /*0x70[18] */ + + /* switch GPIO Mux */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), + 0x0); /*0x66[4] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), + 0x0); /*0x66[8] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), + 0x0); /*0x40[19] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), + 0x0); /*0x64[15] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), + 0x0); /*0x70[18] = 0 */ + + + } else { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); + + /* Restore original value */ + /* switch GPIO Mux */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), + bitVal[0]); /*0x66[4] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), + bitVal[1]); /*0x66[8] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), + bitVal[2]); /*0x40[19] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), + bitVal[3]); /*0x64[15] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), + bitVal[4]); /*0x70[18] = 0 */ + } + +#endif +} + +u32 halbtc8821c1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, + IN u16 reg_addr) +{ + u32 j = 0; + + + /* wait for ready bit before access 0x1700 */ + btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr); + + do { + j++; + } while (((btcoexist->btc_read_1byte(btcoexist, + 0x1703)&BIT(5)) == 0) && + (j < BT_8821C_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); + + return btcoexist->btc_read_4byte(btcoexist, + 0x1708); /* get read data */ + +} + +void halbtc8821c1ant_ltecoex_indirect_write_reg(IN struct btc_coexist + *btcoexist, + IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) +{ + u32 val, i = 0, j = 0, bitpos = 0; + + + if (bit_mask == 0x0) + return; + if (bit_mask == 0xffffffff) { + btcoexist->btc_write_4byte(btcoexist, 0x1704, + reg_value); /* put write data */ + + /* wait for ready bit before access 0x1700 */ + do { + j++; + } while (((btcoexist->btc_read_1byte(btcoexist, + 0x1703)&BIT(5)) == 0) && + (j < BT_8821C_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); + + + btcoexist->btc_write_4byte(btcoexist, 0x1700, + 0xc00F0000 | reg_addr); + } else { + for (i = 0; i <= 31; i++) { + if (((bit_mask >> i) & 0x1) == 0x1) { + bitpos = i; + break; + } + } + + /* read back register value before write */ + val = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + reg_addr); + val = (val & (~bit_mask)) | (reg_value << bitpos); + + btcoexist->btc_write_4byte(btcoexist, 0x1704, + val); /* put write data */ + + /* wait for ready bit before access 0x1700 */ + do { + j++; + } while (((btcoexist->btc_read_1byte(btcoexist, + 0x1703)&BIT(5)) == 0) && + (j < BT_8821C_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); + + + btcoexist->btc_write_4byte(btcoexist, 0x1700, + 0xc00F0000 | reg_addr); + + } + +} + +void halbtc8821c1ant_ltecoex_enable(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 val; + + val = (enable) ? 1 : 0; + halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, + val); /* 0x38[7] */ + +} + +void halbtc8821c1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, + IN boolean wifi_control) +{ + u8 val; + + val = (wifi_control) ? 1 : 0; + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, + val); /* 0x70[26] */ + +} + +void halbtc8821c1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; + + val_orig = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + switch (control_block) { + case BT_8821C_1ANT_GNT_BLOCK_RFC_BB: + default: + val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff); + break; + case BT_8821C_1ANT_GNT_BLOCK_RFC: + val = (val << 14) | (val_orig & 0xffff3fff); + break; + case BT_8821C_1ANT_GNT_BLOCK_BB: + val = (val << 10) | (val_orig & 0xfffff3ff); + break; + } + + halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); +} + +void halbtc8821c1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; + + val_orig = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + switch (control_block) { + case BT_8821C_1ANT_GNT_BLOCK_RFC_BB: + default: + val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff); + break; + case BT_8821C_1ANT_GNT_BLOCK_RFC: + val = (val << 12) | (val_orig & 0xffffcfff); + break; + case BT_8821C_1ANT_GNT_BLOCK_BB: + val = (val << 8) | (val_orig & 0xfffffcff); + break; + } + + halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); +} + +void halbtc8821c1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u16 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8821C_1ANT_CTT_WL_VS_LTE: + reg_addr = 0xa0; + break; + case BT_8821C_1ANT_CTT_BT_VS_LTE: + reg_addr = 0xa4; + break; + } + + if (reg_addr != 0x0000) + halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ + + +} + + +void halbtc8821c1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u8 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8821C_1ANT_LBTT_WL_BREAK_LTE: + reg_addr = 0xa8; + break; + case BT_8821C_1ANT_LBTT_BT_BREAK_LTE: + reg_addr = 0xac; + break; + case BT_8821C_1ANT_LBTT_LTE_BREAK_WL: + reg_addr = 0xb0; + break; + case BT_8821C_1ANT_LBTT_LTE_BREAK_BT: + reg_addr = 0xb4; + break; + } + + if (reg_addr != 0x0000) + halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ + + +} + +void halbtc8821c1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 interval, + IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, + IN u8 val0x6c4_b3) +{ + static u8 pre_h2c_parameter[6] = {0}; + u8 cur_h2c_parameter[6] = {0}; + u8 i, match_cnt = 0; + + cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ + + cur_h2c_parameter[1] = interval; + cur_h2c_parameter[2] = val0x6c4_b0; + cur_h2c_parameter[3] = val0x6c4_b1; + cur_h2c_parameter[4] = val0x6c4_b2; + cur_h2c_parameter[5] = val0x6c4_b3; + + if (!force_exec) { + for (i = 1; i <= 5; i++) { + if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) + break; + + match_cnt++; + } + + if (match_cnt == 5) + return; + } + + for (i = 1; i <= 5; i++) + pre_h2c_parameter[i] = cur_h2c_parameter[i]; + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); +} + + +void halbtc8821c1ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8821c1ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + + halbtc8821c1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8821c1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + u32 break_table; + u8 select_table; + + coex_sta->coex_table_type = type; + + if (coex_sta->concurrent_rx_mode_on == true) { + break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ + select_table = + 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ + } else { + break_table = 0xffffff; + select_table = 0x3; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Table-%d **********\n", + coex_sta->coex_table_type); + BTC_TRACE(trace_buf); + + switch (type) { + case 0: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, break_table, + select_table); + break; + case 1: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 2: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0xaa5a5a5a, 0xaa5a5a5a, break_table, + select_table); + break; + case 3: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 4: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 5: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, break_table, + select_table); + break; + case 6: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 7: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0xaaaaaaaa, 0xaaaaaaaa, break_table, + select_table); + break; + case 8: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xaaaa5aaa, break_table, + select_table); + break; + case 9: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0xaaaa5aaa, break_table, + select_table); + break; + default: + break; + } +} + +void halbtc8821c1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 h2c_parameter[1] = {0}; + + if (enable) + h2c_parameter[0] |= BIT(0); /* function enable */ + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + +void halbtc8821c1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8821c1ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8821c1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8821c1ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8821c1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8821c1ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); */ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8);*/ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + +void halbtc8821c1ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = false; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + /* recover to original 32k low power setting */ + coex_sta->force_lps_on = false; + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + + break; + case BTC_PS_LPS_ON: + coex_sta->force_lps_on = true; + halbtc8821c1ant_ps_tdma_check_for_power_save_state( + btcoexist, true); + halbtc8821c1ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + + break; + case BTC_PS_LPS_OFF: + coex_sta->force_lps_on = false; + halbtc8821c1ant_ps_tdma_check_for_power_save_state( + btcoexist, false); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + + break; + default: + break; + } +} + + +void halbtc8821c1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if (byte5 & BIT(2)) + coex_sta->is_tdma_btautoslot = true; + else + coex_sta->is_tdma_btautoslot = false; + + /* release bt-auto slot for auto-slot hang is detected!! */ + if (coex_sta->is_tdma_btautoslot) + if ((coex_sta->is_tdma_btautoslot_hang) || + (bt_link_info->slave_role)) + byte5 = byte5 & 0xfb; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if (ap_enable) { + if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], FW for 1Ant AP mode\n"); + BTC_TRACE(trace_buf); + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + + halbtc8821c1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + } + } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + + halbtc8821c1ant_power_save_state( + btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + } else { + halbtc8821c1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, + 0x0); + } + + h2c_parameter[0] = real_byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = real_byte5; + + coex_dm->ps_tdma_para[0] = real_byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = real_byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); +} + + +void halbtc8821c1ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + struct btc_board_info *board_info = &btcoexist->board_info; + boolean wifi_busy = false; + static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; + static boolean pre_wifi_busy = false; + + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (wifi_busy != pre_wifi_busy) { + force_exec = true; + pre_wifi_busy = wifi_busy; + } + + /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ + if (bt_link_info->slave_role) + psTdmaByte4Modify = 0x1; + else + psTdmaByte4Modify = 0x0; + + if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { + force_exec = true; + pre_psTdmaByte4Modify = psTdmaByte4Modify; + } + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n", + (coex_dm->cur_ps_tdma_on ? "on" : "off"), + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + return; + } + } + + if (coex_dm->cur_ps_tdma_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(on, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } + + + if (turn_on) { + switch (type) { + default: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x03, 0x11, 0x11); + break; + + case 3: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x3a, 0x03, 0x10, 0x50); + break; + case 4: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x21, 0x03, 0x10, 0x50); + break; + case 5: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x15, 0x03, 0x11, 0x11); + break; + case 6: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x20, 0x03, 0x11, 0x11); + break; + case 7: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 8: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 9: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x55, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 10: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x30, 0x03, 0x11, 0x10); + break; + case 11: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x65, 0x25, 0x03, 0x11, 0x11 | + psTdmaByte4Modify); + break; + case 12: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x55, 0x30, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 13: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x25, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 14: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x15, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 15: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x20, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 16: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x15 | + psTdmaByte4Modify); + break; + case 17: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x14 | + psTdmaByte4Modify); + break; + case 18: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x30, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 19: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x15, 0x03, 0x11, 0x10); + break; + case 20: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x30, 0x03, 0x11, 0x10); + break; + case 21: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x30, 0x03, 0x11, 0x10); + break; + case 22: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x25, 0x03, 0x11, 0x10); + break; + case 23: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x10); + break; + case 27: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x15); + break; + case 32: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x03, 0x11, 0x11); + break; + case 33: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x03, 0x11, 0x10); + break; + case 57: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 58: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 67: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x10 | + psTdmaByte4Modify); + break; + + /* 1-Ant to 2-Ant TDMA case */ + case 103: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x3a, 0x03, 0x70, 0x10); + break; + case 104: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x21, 0x03, 0x70, 0x10); + break; + case 105: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x15, 0x03, 0x71, 0x11); + break; + case 106: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x20, 0x03, 0x71, 0x11); + break; + case 107: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x10, 0x03, 0x70, 0x14 | + psTdmaByte4Modify); + break; + case 108: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x10, 0x03, 0x70, 0x14 | + psTdmaByte4Modify); + break; + case 113: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x25, 0x03, 0x70, 0x10 | + psTdmaByte4Modify); + break; + case 114: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x15, 0x03, 0x70, 0x10 | + psTdmaByte4Modify); + break; + case 115: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x20, 0x03, 0x70, 0x10 | + psTdmaByte4Modify); + break; + case 117: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x10, 0x03, 0x71, 0x14 | + psTdmaByte4Modify); + break; + case 119: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x15, 0x03, 0x71, 0x10); + break; + case 120: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x30, 0x03, 0x71, 0x10); + break; + case 121: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x30, 0x03, 0x71, 0x10); + break; + case 122: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x25, 0x03, 0x71, 0x10); + break; + case 132: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x35, 0x03, 0x71, 0x11); + break; + case 133: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x35, 0x03, 0x71, 0x10); + break; + + } + } else { + + /* disable PS tdma */ + switch (type) { + case 8: /* PTA Control */ + halbtc8821c1ant_set_fw_pstdma(btcoexist, 0x8, + 0x0, 0x0, 0x0, 0x0); + break; + case 0: + default: /* Software control, Antenna at BT side */ + halbtc8821c1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x0, 0x0); + break; + case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */ + halbtc8821c1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x48, 0x0); + break; + } + } + + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; +} + +void halbtc8821c1ant_set_int_block(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 pos_type) +{ +#if 0 + u8 regval_0xcba; + u32 u32tmp1 = 0; + + coex_dm->cur_int_block_status = pos_type; + + if (!force_exec) { + if (coex_dm->pre_int_block_status == + coex_dm->cur_int_block_status) + return; + } + + coex_dm->pre_int_block_status = coex_dm->cur_int_block_status; + + regval_0xcba = btcoexist->btc_read_1byte(btcoexist, 0xcba); + + switch (pos_type) { + + case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG: + regval_0xcba = (regval_0xcba | BIT(0)) & (~(BIT( + 2))); /* 0xcb8[16] = 1, 0xcb8[18] = 0, WL_G select BTG */ + regval_0xcba = regval_0xcba & 0x0f; + + /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc1d, 0x0f, 0x5); */ /* Gain Table */ + /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xa9e, 0x0f, 0x2); */ /* CCK Gain Table */ + + break; + case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG: + regval_0xcba = regval_0xcba & (~(BIT(2) | BIT( + 0))); /* 0xcb8[16] = 0, 0xcb8[18] = 0, WL_G select WLAG */ + + /* regval_0xcba = regval_0xcba | BIT(4) | BIT(5) ; */ /* 0xcb8[21:20] = 2b'11, WL_G @ WLAG on */ + /* regval_0xcba = (regval_0xcba | BIT(6)) & (~(BIT(7)) ) ; */ /* 0xcb8[23:22] = 2b'01, WL_A @ WLAG off */ + /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc1d, 0x0f, 0x0); */ /* Gain Table */ + /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xa9e, 0x0f, 0x6); */ /* CCK Gain Table */ + + break; + case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG: + regval_0xcba = regval_0xcba & (~(BIT(2) | BIT( + 0))); /* 0xcb8[16] = 0, 0xcb8[18] = 0, WL_G select WLAG */ + /*regval_0xcba = (regval_0xcba | BIT(4)) & (~(BIT(5))); */ /* 0xcb8[21:20] = 2b'01, WL_G @ WLAG off */ + /*regval_0xcba = regval_0xcba | BIT(6) | BIT(7); */ /* 0xcb8[23:22] = 2b'11, WL_A @ WLAG on */ + + break; + } + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcba, 0xff, + regval_0xcba); + + u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb8); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (After Int Block setup) 0xcb8 = 0x%08x **********\n", + u32tmp1); + BTC_TRACE(trace_buf); + +#endif +} + +void halbtc8821c1ant_set_ext_band_switch(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 pos_type) +{ + +#if 0 + boolean switch_polatiry_inverse = false; + u8 regval_0xcb6; + u32 u32tmp1 = 0, u32tmp2 = 0; + + if (!rfe_type->ext_band_switch_exist) + return; + + coex_dm->cur_ext_band_switch_status = pos_type; + + if (!force_exec) { + if (coex_dm->pre_ext_band_switch_status == + coex_dm->cur_ext_band_switch_status) + return; + } + + coex_dm->pre_ext_band_switch_status = + coex_dm->cur_ext_band_switch_status; + + /* swap control polarity if use different switch control polarity*/ + switch_polatiry_inverse = (rfe_type->ext_band_switch_ctrl_polarity == 1 + ? ~switch_polatiry_inverse : switch_polatiry_inverse); + + /*swap control polarity for WL_A, default polarity 0xcb4[21] = 0 && 0xcb4[23] = 1 is for WL_G */ + switch_polatiry_inverse = (pos_type == + BT_8821C_1ANT_EXT_BAND_SWITCH_TO_WLA ? ~switch_polatiry_inverse + : switch_polatiry_inverse); + + regval_0xcb6 = btcoexist->btc_read_1byte(btcoexist, 0xcb6); + + /* for normal switch polrity, 0xcb4[21] =1 && 0xcb4[23] = 0 for WL_A, vice versa */ + regval_0xcb6 = (switch_polatiry_inverse == 1 ? ((regval_0xcb6 & (~(BIT( + 7)))) | BIT(5)) : ((regval_0xcb6 & (~(BIT(5)))) | BIT(7))); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb6, 0xff, + regval_0xcb6); + + u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb0); + u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (After Ext Band switch setup) 0xcb0 = 0x%08x, 0xcb4 = 0x%08x**********\n", + u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); +#endif + +} + +void halbtc8821c1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + boolean switch_polatiry_inverse = false; + u8 regval_0xcb7 = 0, regval_0x64; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + + if (!rfe_type->ext_ant_switch_exist) + return; + + coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; + + if (!force_exec) { + if (coex_dm->pre_ext_ant_switch_status == + coex_dm->cur_ext_ant_switch_status) + return; + } + + coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status; + + /* swap control polarity if use different switch control polarity*/ + /* Normal switch polarity for DPDT, 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main */ + /* Normal switch polarity for SPDT, 0xcb4[29:28] = 2b'01 => Ant to BTG, 0xcb4[29:28] = 2b'10 => Ant to WLG */ + if (rfe_type->ext_ant_switch_ctrl_polarity) + switch_polatiry_inverse = ~switch_polatiry_inverse; + + /* swap control polarity if 1-Ant at Aux */ + if (rfe_type->ant_at_main_port == false) + switch_polatiry_inverse = ~switch_polatiry_inverse; + + switch (pos_type) { + default: + case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_BT: + case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE: + case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLA: + + break; + case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLG: + if (!rfe_type->wlg_Locate_at_btg) + switch_polatiry_inverse = ~switch_polatiry_inverse; + break; + } + + if (board_info->ant_div_cfg) + ctrl_type = BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; + + + switch (ctrl_type) { + default: + case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x77); /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + + regval_0xcb7 = (switch_polatiry_inverse == false ? + 0x1 : 0x2); /* 0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, + 0x30, regval_0xcb7); + + break; + case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x66); /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + + regval_0xcb7 = (switch_polatiry_inverse == false ? + 0x2 : 0x1); /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, + 0x30, regval_0xcb7); + + break; + case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x88); /* */ + + /* no regval_0xcb7 setup required, because antenna switch control value by antenna diversity */ + + break; + case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x1); /* 0x4c[23] = 1 */ + + regval_0x64 = (switch_polatiry_inverse == false ? 0x0 : + 0x1); /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, + regval_0x64); + break; + case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x0); /* 0x4c[24] = 0 */ + + /* no setup required, because antenna switch control value by BT vendor 0xac[1:0] */ + break; + } + + /* PAPE, LNA_ON control by BT while WLAN off for current leakage issue */ + if (ctrl_type == BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT) { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x0); /* PAPE 0x64[29] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, + 0x0); /* LNA_ON 0x64[28] = 0 */ + } else { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x1); /* PAPE 0x64[29] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, + 0x1); /* LNA_ON 0x64[28] = 1 */ + } + +#if BT_8821C_1ANT_COEX_DBG + u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (After Ext Ant switch setup) 0xcb4 = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n", + u32tmp1, u32tmp2, u32tmp3); + BTC_TRACE(trace_buf); +#endif + +} + +void halbtc8821c1ant_set_rfe_type(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + + + /* the following setup should be got from Efuse in the future */ + rfe_type->rfe_module_type = board_info->rfe_type & 0x1f; + + rfe_type->ext_ant_switch_ctrl_polarity = 0; + + switch (rfe_type->rfe_module_type) { + case 0: + default: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; /*2-Ant, DPDT, WLG*/ + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 1: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, WLG */ + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 2: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, BTG */ + rfe_type->wlg_Locate_at_btg = true; + rfe_type->ant_at_main_port = true; + break; + case 3: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, WLG */ + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = false; + break; + case 4: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, BTG */ + rfe_type->wlg_Locate_at_btg = true; + rfe_type->ant_at_main_port = false; + break; + case 5: + rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_NONE; + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 6: + rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_NONE; + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 7: + rfe_type->ext_ant_switch_exist = true; /*2-Ant, DPDT, BTG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; + rfe_type->wlg_Locate_at_btg = true; + rfe_type->ant_at_main_port = true; + break; + } + +#if 0 + if (rfe_type->wlg_Locate_at_btg) + halbtc8821c1ant_set_int_block(btcoexist, FORCE_EXEC, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); + else + halbtc8821c1ant_set_int_block(btcoexist, FORCE_EXEC, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); +#endif + +} + + +void halbtc8821c1ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean force_exec, + IN u8 phase) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u32 cnt_bt_cal_chk = 0; + boolean is_in_mp_mode = false; + u8 u8tmp = 0; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + u16 u16tmp1 = 0; + + + u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + /* To avoid indirect access fail */ + if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { + force_exec = true; + coex_sta->gnt_error_cnt++; + } + + +#if BT_8821C_1ANT_COEX_DBG + + u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0x54); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],(Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + u32tmp3, u8tmp, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); +#endif + + coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],(Before Ant Setup) pre_ant_pos_type = 0x%x, cur_ant_pos_type = 0x%x\n", + coex_dm->pre_ant_pos_type, + coex_dm->cur_ant_pos_type); + BTC_TRACE(trace_buf); + + + if (!force_exec) { + if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) + return; + } + + coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; + + + switch (phase) { + case BT_8821C_1ANT_PHASE_COEX_POWERON: + + /* set Path control owner to WL at initial step */ + halbtc8821c1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8821C_1ANT_PCO_BTSIDE); + + /* set GNT_BT to SW high */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW high */ + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = false; + + break; + case BT_8821C_1ANT_PHASE_COEX_INIT: + /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ + halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c1ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_1ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c1ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_1ANT_CTT_BT_VS_LTE, + 0xffff); + + /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ + while (cnt_bt_cal_chk <= 20) { + u8tmp = btcoexist->btc_read_1byte( + btcoexist, + 0x49c); + cnt_bt_cal_chk++; + if (u8tmp & BIT(1)) { + BTC_SPRINTF( + trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", + cnt_bt_cal_chk); + BTC_TRACE( + trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF( + trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", + cnt_bt_cal_chk); + BTC_TRACE( + trace_buf); + break; + } + } + + /* set Path control owner to WL at initial step */ + halbtc8821c1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to SW high */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW low */ + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_LOW); + + coex_sta->run_time_state = false; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + break; + case BT_8821C_1ANT_PHASE_WLANONLY_INIT: + /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ + halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c1ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_1ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c1ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_1ANT_CTT_BT_VS_LTE, + 0xffff); + + /* set Path control owner to WL at initial step */ + halbtc8821c1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Low */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_LOW); + /* Set GNT_WL to SW high */ + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = false; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_WIFI; + + break; + case BT_8821C_1ANT_PHASE_WLAN_OFF: + /* Disable LTE Coex Function in WiFi side */ + halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); + + /* set Path control owner to BT */ + halbtc8821c1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_1ANT_PCO_BTSIDE); + + /* Set Ext Ant Switch to BT control at wifi off step */ + halbtc8821c1ant_set_ext_ant_switch(btcoexist, + FORCE_EXEC, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE); + + coex_sta->run_time_state = false; + break; + case BT_8821C_1ANT_PHASE_2G_RUNTIME: + + while (cnt_bt_cal_chk <= 20) { + /* 0x49c[0]=1 WL IQK, 0x49c[1]=1 BT IQK*/ + u8tmp = btcoexist->btc_read_1byte( + btcoexist, + 0x49c); + + cnt_bt_cal_chk++; + if (u8tmp & BIT(0)) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### WL is IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else if (u8tmp & BIT(1)) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + break; + } + } + + /* set Path control owner to WL at runtime step */ + halbtc8821c1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to PTA */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_1ANT_SIG_STA_SET_BY_HW); + + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_1ANT_SIG_STA_SET_BY_HW); + + coex_sta->run_time_state = true; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (rfe_type->wlg_Locate_at_btg) + ant_pos_type = + BTC_ANT_PATH_WIFI; + else + ant_pos_type = BTC_ANT_PATH_PTA; + } + + if (rfe_type->wlg_Locate_at_btg) + halbtc8821c1ant_set_int_block(btcoexist, + NORMAL_EXEC, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); + else + halbtc8821c1ant_set_int_block(btcoexist, + NORMAL_EXEC, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); + + break; + case BT_8821C_1ANT_PHASE_5G_RUNTIME: + + /* set Path control owner to WL at runtime step */ + halbtc8821c1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Hi */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_1ANT_SIG_STA_SET_BY_HW); + + /* Set GNT_WL to SW Hi */ + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = true; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + /* if (rfe_type->ext_band_switch_exist) + ant_pos_type = BTC_ANT_PATH_PTA; + else */ + ant_pos_type = + BTC_ANT_PATH_WIFI5G; + } + + halbtc8821c1ant_set_int_block(btcoexist, + NORMAL_EXEC, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG); + + break; + case BT_8821C_1ANT_PHASE_BTMPMODE: + /* Disable LTE Coex Function in WiFi side */ + halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); + + /* set Path control owner to WL */ + halbtc8821c1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Hi */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + + /* Set GNT_WL to SW Lo */ + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_LOW); + + coex_sta->run_time_state = false; + + /* Set Ext Ant Switch to BT side at BT MP mode */ + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + break; + case BT_8821C_1ANT_PHASE_ANTENNA_DET: + halbtc8821c1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to high */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to high */ + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = false; + + break; + } + + if (phase != BT_8821C_1ANT_PHASE_WLAN_OFF) { + switch (ant_pos_type) { + case BTC_ANT_PATH_WIFI: + halbtc8821c1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLG); + break; + case BTC_ANT_PATH_WIFI5G + : + halbtc8821c1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLA); + break; + case BTC_ANT_PATH_BT: + halbtc8821c1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_BT); + break; + default: + case BTC_ANT_PATH_PTA: + halbtc8821c1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE); + break; + } + + } + +#if BT_8821C_1ANT_COEX_DBG + u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],(After Ant-Setup phase---%d) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + phase, u32tmp3, u8tmp, u32tmp1, u32tmp2); + + BTC_TRACE(trace_buf); +#endif +} + + +boolean halbtc8821c1ant_is_common_action(IN struct btc_coexist *btcoexist) +{ + boolean common = false, wifi_connected = false, wifi_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_connected && + BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + + common = true; + } else if (wifi_connected && + (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + + common = true; + } else if (!wifi_connected && + (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + + common = true; + } else if (wifi_connected && + (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + + common = true; + } else if (!wifi_connected && + (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE != + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + + common = true; + } else { + if (wifi_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } + + common = false; + } + + return common; +} + + +/* ********************************************* + * + * Software Coex Mechanism start + * + * ********************************************* */ + + + +/* ********************************************* + * + * Non-Software Coex Mechanism start + * + * ********************************************* */ +void halbtc8821c1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) +{ + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8821c1ant_action_bt_hs(IN struct btc_coexist *btcoexist) +{ + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8821c1ant_action_bt_relink(IN struct btc_coexist *btcoexist) +{ + /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); */ + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + coex_sta->bt_relink_downcount = 2; +} + +void halbtc8821c1ant_action_bt_idle(IN struct btc_coexist *btcoexist) +{ + boolean wifi_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_busy) { + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 6); + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + + } else { /* if wl busy */ + + if (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 33); + } else { + + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); + + } + + } + +} + +void halbtc8821c1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, wifi_busy = false, + bt_busy = false; + boolean wifi_scan = false, wifi_link = false, wifi_roam = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + + if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) + || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + + if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17); + else + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); + } else if ((!wifi_connected) && (!wifi_scan)) { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (bt_link_info->pan_exist) { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + } else if (bt_link_info->a2dp_exist) { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) + || (coex_sta->wifi_is_high_pri_task)) + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); + else + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } +} + +void halbtc8821c1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, wifi_busy = false; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + + if (bt_link_info->sco_exist) { + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 5); + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 5); + } else if (coex_sta->hid_busy_num >= 2) { /*for 4/18 hid */ + + /* if 11bg mode */ + if (wifi_bw == 0) { + + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8821c1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 11); + } else { + + if (wifi_busy) { + + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8821c1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 11); + } else { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 6); + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + + } + } + } else { + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 6); + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + } +} + +void halbtc8821c1ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) +{ + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8821C_1ANT_PHASE_5G_RUNTIME); +} + + +void halbtc8821c1ant_action_wifi_only(IN struct btc_coexist *btcoexist) +{ + halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + halbtc8821c1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 7); +} + +void halbtc8821c1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + + if (!bt_link_info->pan_exist) + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + else + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + + +void halbtc8821c1ant_action_wifi_linkscan_process(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if (bt_link_info->pan_exist) { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + } else if (bt_link_info->a2dp_exist) { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 27); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } + +} + +void halbtc8821c1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = false, wifi_turbo = false; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif + + if ((coex_sta->bt_relink_downcount != 0) + && (!bt_link_info->pan_exist) && (wifi_busy)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + + /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);*/ + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + } else if (bt_link_info->a2dp_only) { /* A2DP */ + if (!wifi_busy) { + + /* halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 32); */ + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 27); + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else { + + if (coex_sta->wl_noisy_level == 2) + halbtc8821c1ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 17); + else + halbtc8821c1ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 7); + + if (wifi_turbo) + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else if (((bt_link_info->a2dp_exist) && + (bt_link_info->pan_exist)) || + (bt_link_info->hid_exist && bt_link_info->a2dp_exist && + bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ + + if ((bt_link_info->hid_exist) && + (coex_sta->hid_busy_num >= 2)) { + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8821c1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 12); + } else if (wifi_busy) { + if (((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) || + (!coex_sta->is_A2DP_3M)) + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 15); + else if (wifi_turbo) + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 18); + else + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 13); + } else + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 14); + + if (bt_link_info->hid_exist) + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + else if (wifi_turbo) + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { /* HID+A2DP */ + + if ((wifi_busy) && (coex_sta->hid_busy_num >= 2)) {/*for 4/18 hid */ + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + + if (wifi_bw == 0) /* 11bg mode */ + halbtc8821c1ant_set_wltoggle_coex_table( + btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + else + halbtc8821c1ant_set_wltoggle_coex_table( + btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, + 9); + } else { + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, + 8); + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + } + + } else if ((bt_link_info->pan_only) + || (bt_link_info->hid_exist && bt_link_info->pan_exist)) { + /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ + + if ((bt_link_info->hid_exist) && (bt_link_info->pan_exist) && + (coex_sta->hid_busy_num >= 2)) { + + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + if (wifi_bw == 0) /* 11bg mode */ + halbtc8821c1ant_set_wltoggle_coex_table( + btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + else + halbtc8821c1ant_set_wltoggle_coex_table( + btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 12); + } else { + + if (!wifi_busy) + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 4); + else + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 3); + + if (bt_link_info->hid_exist) + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + else if (wifi_turbo) + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } + } else { + /* BT no-profile busy (0x9) */ + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } + +} + +void halbtc8821c1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +{ + /* tdma and coex table */ + halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8821c1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = false; + boolean wifi_under_5g = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect()===>\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + return; + } + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + + if (BT_8821C_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + + if (bt_link_info->hid_only) /* HID only */ + halbtc8821c1ant_action_bt_sco_hid_only_busy(btcoexist); + else + halbtc8821c1ant_action_wifi_connected_bt_acl_busy( + btcoexist); + + } else if ((BT_8821C_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) + halbtc8821c1ant_action_bt_sco_hid_only_busy(btcoexist); + else + halbtc8821c1ant_action_bt_idle(btcoexist); + +} + +void halbtc8821c1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + u8 algorithm = 0; + + algorithm = halbtc8821c1ant_action_algorithm(btcoexist); + coex_dm->cur_algorithm = algorithm; + + if (!halbtc8821c1ant_is_common_action(btcoexist)) { + switch (coex_dm->cur_algorithm) { + case BT_8821C_1ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_sco(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_hid(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_a2dp(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_a2dp_pan_hs(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_pan_edr(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HS mode.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_pan_hs(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_pan_edr_a2dp(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_pan_edr_hid(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_hid_a2dp_pan_edr(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_hid_a2dp(btcoexist); */ + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_coex_all_off(btcoexist); */ + break; + } + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + } +} + + +void halbtc8821c1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = false, bt_hs_on = false; + boolean increase_scan_dev_num = false; + boolean bt_ctrl_agg_buf_size = false; + boolean miracast_plus_bt = false, wifi_under_5g = false; + u8 agg_buf_size = 5; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0, wifi_bw; + u8 iot_peer = BTC_IOT_PEER_UNKNOWN; + boolean scan = false, link = false, roam = false, under_4way = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (!coex_sta->run_time_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], return for run_time_state = false !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->freeze_coexrun_by_btinfo) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + return; + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 2G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + } + + if (coex_sta->bt_whck_test) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under WHCK TEST!!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_action_bt_whql_test(btcoexist); + return; + } + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!!\n"); + halbtc8821c1ant_action_wifi_only(btcoexist); + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_action_bt_inquiry(btcoexist); + return; + } + + if (coex_sta->is_setupLink) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is re-link !!!\n"); + halbtc8821c1ant_action_bt_relink(btcoexist); + return; + } + + if ((BT_8821C_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + increase_scan_dev_num = true; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, + &increase_scan_dev_num); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + + num_of_wifi_link = wifi_link_status >> 16; + + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", + num_of_wifi_link, wifi_link_status); + BTC_TRACE(trace_buf); + + if (bt_link_info->bt_link_exist) + miracast_plus_bt = true; + else + miracast_plus_bt = false; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + halbtc8821c1ant_limited_rx(btcoexist, NORMAL_EXEC, false, + false, 0x5); + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_linkscan_process(btcoexist); + } else + halbtc8821c1ant_action_wifi_multi_port(btcoexist); + + return; + } else { + + miracast_plus_bt = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + } + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + if ((bt_link_info->bt_link_exist) && (wifi_connected)) { + + btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); + + if (BTC_IOT_PEER_CISCO == iot_peer) { + + if (BTC_WIFI_BW_HT40 == wifi_bw) + halbtc8821c1ant_limited_rx(btcoexist, + NORMAL_EXEC, false, true, 0x10); + else + halbtc8821c1ant_limited_rx(btcoexist, + NORMAL_EXEC, false, true, 0x8); + } else + halbtc8821c1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, + 0x5); + } + + halbtc8821c1ant_run_sw_coexist_mechanism( + btcoexist); /* just print debug message */ + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is hs\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_action_bt_hs(btcoexist); + return; + } + + if ((BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is idle\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_action_bt_idle(btcoexist); + return; + } + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under linkscan process!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_linkscan_process(btcoexist); + } else if (wifi_connected) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under connected!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_connected(btcoexist); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under not-connected!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_not_connected(btcoexist); + } +} + +void halbtc8821c1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + /* force to reset coex mechanism */ + halbtc8821c1ant_low_penalty_ra(btcoexist, FORCE_EXEC, false); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->pop_event_cnt = 0; + coex_sta->cnt_RemoteNameReq = 0; + coex_sta->cnt_ReInit = 0; + coex_sta->cnt_setupLink = 0; + coex_sta->cnt_IgnWlanAct = 0; + coex_sta->cnt_Page = 0; + coex_sta->cnt_RoleSwitch = 0; + + halbtc8821c1ant_query_bt_info(btcoexist); +} + +void halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean back_up, IN boolean wifi_only) +{ + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + u16 u16tmp1 = 0; + u8 i; + struct btc_board_info *board_info = &btcoexist->board_info; + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 1Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],(Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + u32tmp3, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); + + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + coex_sta->isolation_btween_wb = BT_8821C_1ANT_DEFAULT_ISOLATION; + coex_sta->gnt_error_cnt = 0; + coex_sta->bt_relink_downcount = 0; + + for (i = 0; i <= 9; i++) + coex_sta->bt_afh_map[i] = 0; + + /* Setup RF front end type */ + halbtc8821c1ant_set_rfe_type(btcoexist); + + /* 0xf0[15:12] --> Chip Cut information */ + coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, + 0xf1) & 0xf0) >> 4; + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + + /* BT report packet sample rate */ + btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); + + /* Init 0x778 = 0x1 for 1-Ant */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + + /* Enable PTA (3-wire function form BT side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); + + /* Enable PTA (tx/rx signal form WiFi side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); + + /* set GNT_BT=1 for coex table select both */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1); + + halbtc8821c1ant_enable_gnt_to_gpio(btcoexist, true); + +#if 0 + /* check if WL firmware download ok */ + /*if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)*/ + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ONOFF, true); +#endif + + /* PTA parameter */ + halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); + + halbtc8821c1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + psd_scan->ant_det_is_ant_det_available = true; + + /* Antenna config */ + if (wifi_only) { + coex_sta->concurrent_rx_mode_on = false; + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_WLANONLY_INIT); + + btcoexist->stop_coex_dm = true; + } else { + /*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); + + coex_sta->concurrent_rx_mode_on = true; + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */ + + /* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx, mask Tx only */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0); + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_COEX_INIT); + + btcoexist->stop_coex_dm = false; + } + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (After Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + u32tmp3, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); + +} + + +/* ************************************************************ + * work around function start with wa_halbtc8821c1ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8821c1ant_ + * ************************************************************ */ +void ex_halbtc8821c1ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x0; + u16 u16tmp = 0x0; + u32 value = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx Execute 8821c 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "Ant Det Finish = %s, Ant Det Number = %d\n", + (board_info->btdm_ant_det_finish ? "Yes" : "No"), + board_info->btdm_ant_num_by_ant_det); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = true; + psd_scan->ant_det_is_ant_det_available = false; + + /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */ + u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); + btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); + + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + + /* Set Antenna Path to BT side */ + /* Check efuse 0xc3[6] for Single Antenna Path */ + if (board_info->single_ant_path == 0) { + + board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; + u8tmp = 1; + } else if (board_info->single_ant_path == 1) { + + board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; + u8tmp = 0; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d\n", + board_info->single_ant_path , board_info->btdm_ant_pos); + BTC_TRACE(trace_buf); + + /* Setup RF front end type */ + halbtc8821c1ant_set_rfe_type(btcoexist); + + /* Set Antenna Path to BT side */ + halbtc8821c1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_COEX_POWERON); + + /* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at power on */ + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_USB) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); + + /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ + halbtc8821c1ant_enable_gnt_to_gpio(btcoexist, true); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x\n", + halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38)); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcb4 (Power-On) = 0x%x / 0x%x\n", + btcoexist->btc_read_4byte(btcoexist, 0x70), + btcoexist->btc_read_4byte(btcoexist, 0xcb4)); + BTC_TRACE(trace_buf); + +} + +void ex_halbtc8821c1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{ +} + +void ex_halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8821c1ant_init_hw_config(btcoexist, true, wifi_only); +} + +void ex_halbtc8821c1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + halbtc8821c1ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_stack_info *stack_info = &btcoexist->stack_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u16 u16tmp[4]; + u32 u32tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + static u8 pop_report_in_10s = 0; + u32 phyver = 0; + boolean lte_coex_on = false; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + if (btcoexist->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + if (psd_scan->ant_det_try_count == 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s / %d", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, board_info->btdm_ant_num, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type); + CL_PRINTF(cli_buf); + } else { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", + "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", + board_info->pg_ant_num, + board_info->btdm_ant_num_by_ant_det, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type, + psd_scan->ant_det_try_count, + psd_scan->ant_det_fail_count, + psd_scan->ant_det_result); + CL_PRINTF(cli_buf); + + if (board_info->btdm_ant_det_finish) { + + if (psd_scan->ant_det_result != 12) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", + "Ant Det PSD Value", + psd_scan->ant_det_peak_val); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d", + "Ant Det PSD Value", + psd_scan->ant_det_psd_scan_peak_val + / 100); + CL_PRINTF(cli_buf); + } + } + + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + + bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8821c_1ant, glcoex_ver_8821c_1ant, + glcoex_ver_btdesired_8821c_1ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8821c_1ant ? + "Match" : "Mis-Match")))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "AFH Map to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + pop_report_in_10s++; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", + "BT [status/ rssi/ retryCnt/ popCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + : ((BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, + coex_sta->pop_event_cnt); + CL_PRINTF(cli_buf); + + if (pop_report_in_10s >= 5) { + coex_sta->pop_event_cnt = 0; + pop_report_in_10s = 0; + } + + if (coex_sta->num_of_profile != 0) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s%s%s%s%s", + "Profiles", + ((bt_link_info->a2dp_exist) ? "A2DP," : ""), + ((bt_link_info->sco_exist) ? "HFP," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : + "HID(2/18),") : ""), + ((bt_link_info->pan_exist) ? "PAN," : ""), + ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = None", "Profiles"); + + CL_PRINTF(cli_buf); + + if (bt_link_info->a2dp_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", + "A2DP Rate/Bitpool/Auto_Slot", + ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), + coex_sta->a2dp_bit_pool, + ((coex_sta->is_autoslot) ? "On" : "Off") + ); + CL_PRINTF(cli_buf); + } + + if (bt_link_info->hid_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "HID PairNum/Forbid_Slot", + coex_sta->hid_pair_cnt, + coex_sta->forbidden_slot + ); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x", + "Role/RoleSwCnt/IgnWlact/Feature", + ((bt_link_info->slave_role) ? "Slave" : "Master"), + coex_sta->cnt_RoleSwitch, + ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), + coex_sta->bt_coex_supported_feature); + CL_PRINTF(cli_buf); + + if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "BLEScan Type/TV/Init/Ble", + coex_sta->bt_ble_scan_type, + (coex_sta->bt_ble_scan_type & 0x1 ? + coex_sta->bt_ble_scan_para[0] : 0x0), + (coex_sta->bt_ble_scan_type & 0x2 ? + coex_sta->bt_ble_scan_para[1] : 0x0), + (coex_sta->bt_ble_scan_type & 0x4 ? + coex_sta->bt_ble_scan_para[2] : 0x0)); + CL_PRINTF(cli_buf); + } + + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "ReInit/ReLink/IgnWlact/Page/NameReq", + coex_sta->cnt_ReInit, + coex_sta->cnt_setupLink, + coex_sta->cnt_IgnWlanAct, + coex_sta->cnt_Page, + coex_sta->cnt_RemoteNameReq + ); + CL_PRINTF(cli_buf); + + halbtc8821c1ant_read_score_board(btcoexist, &u16tmp[0]); + + if ((coex_sta->bt_reg_vendor_ae == 0xffff) || + (coex_sta->bt_reg_vendor_ac == 0xffff)) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", + ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), + coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); + CL_PRINTF(cli_buf); + + if (coex_sta->num_of_profile > 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + "AFH MAP", + coex_sta->bt_afh_map[0], + coex_sta->bt_afh_map[1], + coex_sta->bt_afh_map[2], + coex_sta->bt_afh_map[3], + coex_sta->bt_afh_map[4], + coex_sta->bt_afh_map[5], + coex_sta->bt_afh_map[6], + coex_sta->bt_afh_map[7], + coex_sta->bt_afh_map[8], + coex_sta->bt_afh_map[9] + ); + CL_PRINTF(cli_buf); + } + + for (i = 0; i < BT_INFO_SRC_8821C_1ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8821c_1ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + + if (btcoexist->manual_control) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanisms] (before Manual)============"); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Mechanisms]============"); + + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s)", + "TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off")); + + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", + "Table/0x6c0/0x6c4/0x6c8", + coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x", + "0x778/0x6cc", + u8tmp[0], u32tmp[0]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", + "AntDiv/ForceLPS/LPRA", + ((board_info->ant_div_cfg) ? "On" : "Off"), + ((coex_sta->force_lps_on) ? "On" : "Off"), + ((coex_dm->cur_low_penalty_ra) ? "On" : "Off")); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? true : false; + + if (lte_coex_on) { + + u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa0); + u32tmp[1] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "LTE Coex Table W_L/B_L", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa8); + u32tmp[1] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0xac); + u32tmp[2] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0xb0); + u32tmp[3] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0xb4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "LTE Break Table W_L/B_L/L_W/L_B", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, + u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); + CL_PRINTF(cli_buf); + } + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp[1] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", + "LTE Coex/Path Owner", + ((lte_coex_on) ? "On" : "Off") , + ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); + CL_PRINTF(cli_buf); + + if (lte_coex_on) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %d/ %d", + "LTE 3Wire/OPMode/UART/UARTMode", + (int)((u32tmp[0] & BIT(6)) >> 6), + (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), + (int)((u32tmp[0] & BIT(3)) >> 3), + (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "LTE_Busy/UART_Busy", + (int)((u32tmp[1] & BIT(1)) >> 1), + (int)(u32tmp[1] & BIT(0))); + CL_PRINTF(cli_buf); + } + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", + ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), + ((u8tmp[0] & BIT(3)) ? "On" : "Off"), + coex_sta->gnt_error_cnt); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "GNT_WL/GNT_BT", + (int)((u32tmp[1] & BIT(2)) >> 2), + (int)((u32tmp[1] & BIT(3)) >> 3)); + CL_PRINTF(cli_buf); + + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s", + "0xcb0/0xcb4/0xcb8[23:16]", + u32tmp[0], u32tmp[1], u8tmp[0], + ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "4c[24:23]/64[0]/4c6[4]/40[5]", + (u32tmp[0] & (BIT(24) | BIT(23))) >> 23 , u8tmp[2] & 0x1 , + (int)((u8tmp[0] & BIT(4)) >> 4), + (int)((u8tmp[1] & BIT(5)) >> 5)); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x", + "0x550/0x522/4-RxAGC/0xc50", + u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_CCK); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); + CL_PRINTF(cli_buf); + + +#if 1 + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11ac", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_Err CCK/11g/11n/11ac", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); + CL_PRINTF(cli_buf); +#endif + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "WlHiPri/ Locking/ Locked/ Noisy", + (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + (coex_sta->cck_lock ? "Yes" : "No"), + (coex_sta->cck_ever_lock ? "Yes" : "No"), + coex_sta->wl_noisy_level); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx, + (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : "")); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : ( + coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); + CL_PRINTF(cli_buf); + + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +void ex_halbtc8821c1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = true; + + /* Write WL "Active" in Score-board for LPS off */ + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_ONOFF | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, + false); + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_WLAN_OFF); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE, true); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ONOFF, true); +#endif + halbtc8821c1ant_init_hw_config(btcoexist, false, false); + halbtc8821c1ant_init_coex_dm(btcoexist); + + coex_sta->under_ips = false; + } +} + +void ex_halbtc8821c1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = true; + + if (coex_sta->force_lps_on == true) { /* LPS No-32K */ + /* Write WL "Active" in Score-board for PS-TDMA */ + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE, true); + + } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ + /* Write WL "Non-Active" in Score-board for Native-PS */ + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE, false); + + } + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = false; + + /* Write WL "Active" in Score-board for LPS off */ + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE, true); + + } +} + +void ex_halbtc8821c1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false; + boolean wifi_under_5g = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + coex_sta->freeze_coexrun_by_btinfo = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + if (wifi_connected) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL connected before SCAN\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL is not connected before SCAN\n"); + + BTC_TRACE(trace_buf); + + halbtc8821c1ant_query_bt_info(btcoexist); + + if (BTC_SCAN_START == type) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, + &wifi_under_5g); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_ONOFF, + true); + + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** SCAN START notify (5g)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + return; + } + + coex_sta->wifi_is_high_pri_task = true; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** SCAN START notify (2g)\n"); + BTC_TRACE(trace_buf); + + /* Force antenna setup for no scan result issue */ + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + + return; + } + + if (BTC_SCAN_START_2G == type) { + + if (!wifi_connected) + coex_sta->wifi_is_high_pri_task = true; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_ONOFF, + true); + + /* Force antenna setup for no scan result issue */ + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + + } else { + + coex_sta->wifi_is_high_pri_task = false; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", + coex_sta->scan_ap_num); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + } + + +} + +void ex_halbtc8821c1ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + + boolean wifi_connected = false, bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + + if (type == BTC_SWITCH_TO_5G) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], switchband_notify --- switch to 5G\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + + } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** switchband_notify BTC_SWITCH_TO_2G (no for scan)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], switchband_notify --- switch to 2G\n"); + BTC_TRACE(trace_buf); + + ex_halbtc8821c1ant_scan_notify(btcoexist, + BTC_SCAN_START_2G); + } +} + + +void ex_halbtc8821c1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_ONOFF, + true); + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + if ((BTC_ASSOCIATE_5G_START == type) || + (BTC_ASSOCIATE_5G_FINISH == type)) { + + if (BTC_ASSOCIATE_5G_START == type) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], connect_notify --- 5G start\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], connect_notify --- 5G finish\n"); + + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + return; + } + + if (BTC_ASSOCIATE_START == type) { + + coex_sta->wifi_is_high_pri_task = true; + + /* Force antenna setup for no scan result issue */ + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify (2G)\n"); + BTC_TRACE(trace_buf); + + coex_dm->arp_cnt = 0; + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + + /* To keep TDMA case during connect process, + to avoid changed by Btinfo and runcoexmechanism */ + coex_sta->freeze_coexrun_by_btinfo = true; + } else { + + coex_sta->wifi_is_high_pri_task = false; + coex_sta->freeze_coexrun_by_btinfo = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + } + +} + +void ex_halbtc8821c1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_under_b_mode = false, wifi_under_5g = false; + + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (BTC_MEDIA_CONNECT == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_ONOFF, + true); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + return; + } + + /* Force antenna setup for no scan result issue */ + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x00); /* CCK Rx */ + } else { + /* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */ + /* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x10); /* CCK Rx */ + } + + coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, + 0x430); + coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, + 0x434); + coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( + btcoexist, 0x42a); + coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( + btcoexist, 0x456); + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE, false); + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + + coex_sta->cck_ever_lock = false; + } + + halbtc8821c1ant_update_wifi_channel_info(btcoexist, type); + +} + +void ex_halbtc8821c1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean under_4way = false, wifi_under_5g = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (under_4way) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ---- under_4way!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = true; + coex_sta->specific_pkt_period_cnt = 2; + } else if (BTC_PACKET_ARP == type) { + + coex_dm->arp_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ARP notify -cnt = %d\n", + coex_dm->arp_cnt); + BTC_TRACE(trace_buf); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", + type); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = true; + coex_sta->specific_pkt_period_cnt = 2; + } + + if (coex_sta->wifi_is_high_pri_task) { + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_SCAN, true); + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + } + +} + +void ex_halbtc8821c1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 i, rsp_source = 0; + boolean wifi_connected = false; + boolean wifi_scan = false, wifi_link = false, wifi_roam = false, + wifi_busy = false; + static boolean is_scoreboard_scan = false; + + if (psd_scan->is_AntDet_running == true) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt_info_notify return for AntDet is running\n"); + BTC_TRACE(trace_buf); + return; + } + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8821C_1ANT_MAX) + rsp_source = BT_INFO_SRC_8821C_1ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; + coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; + coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; + + if (BT_INFO_SRC_8821C_1ANT_WIFI_FW != rsp_source) { + + /* if 0xff, it means BT is under WHCK test */ + coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true : + false); + + coex_sta->bt_create_connection = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true : + false); + + /* unit: %, value-100 to translate to unit: dBm */ + coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + + 10; + + coex_sta->c2h_bt_remote_name_req = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true : + false); + + coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & + 0x10) ? true : false); + + coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & + 0x9) ? true : false); + + coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? + true : false); + + coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & + BT_INFO_8821C_1ANT_B_INQ_PAGE) ? true : false); + + coex_sta->a2dp_bit_pool = ((( + coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? + coex_sta->bt_info_c2h[rsp_source][6] : 0); + + coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & + 0xf; + + coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; + + coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; + + coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; + + coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; + + if (coex_sta->bt_retry_cnt >= 1) + coex_sta->pop_event_cnt++; + + if (coex_sta->c2h_bt_remote_name_req) + coex_sta->cnt_RemoteNameReq++; + + if (coex_sta->bt_info_ext & BIT(1)) + coex_sta->cnt_ReInit++; + + if (coex_sta->bt_info_ext & BIT(2)) { + coex_sta->cnt_setupLink++; + coex_sta->is_setupLink = true; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link start in BT info!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_sta->is_setupLink = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link stop in BT info!!\n"); + BTC_TRACE(trace_buf); + } + + if (coex_sta->bt_info_ext & BIT(3)) + coex_sta->cnt_IgnWlanAct++; + + if (coex_sta->bt_info_ext & BIT(6)) + coex_sta->cnt_RoleSwitch++; + + if (coex_sta->bt_create_connection) { + coex_sta->cnt_Page++; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, + &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || + (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { + + is_scoreboard_scan = true; + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_SCAN, true); + + } else + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_SCAN, false); + + } else { + if (is_scoreboard_scan) { + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_SCAN, false); + is_scoreboard_scan = false; + } + } + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + + if ((!btcoexist->manual_control) && + (!btcoexist->stop_coex_dm)) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* Re-Init */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + if (wifi_connected) + halbtc8821c1ant_update_wifi_channel_info( + btcoexist, BTC_MEDIA_CONNECT); + else + halbtc8821c1ant_update_wifi_channel_info( + btcoexist, + BTC_MEDIA_DISCONNECT); + } + + /* If Ignore_WLanAct && not SetUp_Link */ + if ((coex_sta->bt_info_ext & BIT(3)) && + (!(coex_sta->bt_info_ext & BIT(2)))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, false); + } + } + + } + + if ((coex_sta->bt_info_ext & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + BTC_TRACE(trace_buf); + coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( + btcoexist); + + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x4); + + } + + halbtc8821c1ant_update_bt_link_info(btcoexist); + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); +} + + + +void ex_halbtc8821c1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_RF_ON == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned ON!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = false; +#if 0 + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_ONOFF, + true); +#endif + } else if (BTC_RF_OFF == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned OFF!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_ONOFF | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, + false); + + halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_WLAN_OFF); + + btcoexist->stop_coex_dm = true; + } +} + +void ex_halbtc8821c1ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_ONOFF | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, + false); + + halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_1ANT_PHASE_WLAN_OFF); + + halbtc8821c1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); + + ex_halbtc8821c1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + + btcoexist->stop_coex_dm = true; +} + +void ex_halbtc8821c1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + boolean wifi_under_5g = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((BTC_WIFI_PNP_SLEEP == pnp_state) || + (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_ONOFF | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, + false); + + if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { + + if (wifi_under_5g) + halbtc8821c1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_1ANT_PHASE_5G_RUNTIME); + else + halbtc8821c1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + } else { + + halbtc8821c1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_WLAN_OFF); + } + + btcoexist->stop_coex_dm = true; + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_ONOFF, + true); +#endif + btcoexist->stop_coex_dm = false; + } +} + + +void ex_halbtc8821c1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], *****************Coex DM Reset*****************\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_init_hw_config(btcoexist, false, false); + halbtc8821c1ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8821c1ant_periodical(IN struct btc_coexist *btcoexist) +{ + + struct btc_board_info *board_info = &btcoexist->board_info; + boolean wifi_busy = false; + u16 bt_scoreboard_val = 0; + u32 bt_patch_ver; + static u8 cnt = 0; + boolean bt_relink_finish = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ************* Periodical *************\n"); + BTC_TRACE(trace_buf); + +#if (BT_AUTO_REPORT_ONLY_8821C_1ANT == 0) + halbtc8821c1ant_query_bt_info(btcoexist); + +#endif + + halbtc8821c1ant_monitor_bt_ctr(btcoexist); + halbtc8821c1ant_monitor_wifi_ctr(btcoexist); + + halbtc8821c1ant_monitor_bt_enable_disable(btcoexist); + +#if 0 + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + /* halbtc8821c1ant_read_score_board(btcoexist, &bt_scoreboard_val); */ + + if (wifi_busy) { + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, true); + /* + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_WLBUSY, true); + + if (bt_scoreboard_val & BIT(6)) + halbtc8821c1ant_query_bt_info(btcoexist); */ + } else { + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, false); + } +#endif + + if (coex_sta->bt_relink_downcount != 0) { + coex_sta->bt_relink_downcount--; + + if (coex_sta->bt_relink_downcount == 0) + bt_relink_finish = true; + } + + /* for 4-way, DHCP, EAPOL packet */ + if (coex_sta->specific_pkt_period_cnt > 0) { + + coex_sta->specific_pkt_period_cnt--; + + if ((coex_sta->specific_pkt_period_cnt == 0) && + (coex_sta->wifi_is_high_pri_task)) + coex_sta->wifi_is_high_pri_task = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ***************** Hi-Pri Task = %s\n", + (coex_sta->wifi_is_high_pri_task ? "Yes" : + "No")); + BTC_TRACE(trace_buf); + + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->bt_coex_supported_feature == 0) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + if (coex_sta->bt_reg_vendor_ac == 0xffff) + coex_sta->bt_reg_vendor_ac = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xac) & 0xffff); + + if (coex_sta->bt_reg_vendor_ae == 0xffff) + coex_sta->bt_reg_vendor_ae = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xae) & 0xffff); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, + &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) { + cnt++; + + if (cnt >= 3) { + btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, + &coex_sta->bt_afh_map[0]); + cnt = 0; + } + } + } + + if (halbtc8821c1ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish)) + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + +} + +/*#pragma optimize( "", off )*/ +void ex_halbtc8821c1ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + +} + + +void ex_halbtc8821c1ant_display_ant_detection(IN struct btc_coexist *btcoexist) +{ + +} + +void ex_halbtc8821c1ant_antenna_isolation(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + + +} + +void ex_halbtc8821c1ant_psd_scan(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + + +} + + +#endif + +#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ + + diff --git a/hal/btc/halbtc8821c1ant.h b/hal/btc/halbtc8821c1ant.h new file mode 100644 index 0000000..25752cd --- /dev/null +++ b/hal/btc/halbtc8821c1ant.h @@ -0,0 +1,497 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8821C_SUPPORT == 1) + +/* ******************************************* + * The following is for 8821C 1ANT BT Co-exist definition + * ******************************************* */ +#define BT_8821C_1ANT_COEX_DBG 0 +#define BT_AUTO_REPORT_ONLY_8821C_1ANT 1 + +#define BT_INFO_8821C_1ANT_B_FTP BIT(7) +#define BT_INFO_8821C_1ANT_B_A2DP BIT(6) +#define BT_INFO_8821C_1ANT_B_HID BIT(5) +#define BT_INFO_8821C_1ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8821C_1ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8821C_1ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8821C_1ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8821C_1ANT_B_CONNECTION BIT(0) + +#define BT_INFO_8821C_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT(0))) ? true : false) + +#define BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT 2 + +#define BT_8821C_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ +#define BT_8821C_1ANT_DEFAULT_ISOLATION 15 /* unit: dB */ + + +/* for Antenna detection */ +#define BT_8821C_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 +#define BT_8821C_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 +#define BT_8821C_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 +#define BT_8821C_1ANT_ANTDET_PSDTHRES_1ANT 35 +#define BT_8821C_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ +#define BT_8821C_1ANT_ANTDET_SWEEPPOINT_DELAY 60000 +#define BT_8821C_1ANT_ANTDET_ENABLE 0 +#define BT_8821C_1ANT_ANTDET_BTTXTIME 100 +#define BT_8821C_1ANT_ANTDET_BTTXCHANNEL 39 +#define BT_8821C_1ANT_ANTDET_PSD_SWWEEPCOUNT 50 + +#define BT_8821C_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 + +enum bt_8821c_1ant_signal_state { + BT_8821C_1ANT_SIG_STA_SET_TO_LOW = 0x0, + BT_8821C_1ANT_SIG_STA_SET_BY_HW = 0x0, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH = 0x1, + BT_8821C_1ANT_SIG_STA_MAX +}; + +enum bt_8821c_1ant_path_ctrl_owner { + BT_8821C_1ANT_PCO_BTSIDE = 0x0, + BT_8821C_1ANT_PCO_WLSIDE = 0x1, + BT_8821C_1ANT_PCO_MAX +}; + +enum bt_8821c_1ant_gnt_ctrl_type { + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW = 0x1, + BT_8821C_1ANT_GNT_TYPE_MAX +}; + +enum bt_8821c_1ant_gnt_ctrl_block { + BT_8821C_1ANT_GNT_BLOCK_RFC_BB = 0x0, + BT_8821C_1ANT_GNT_BLOCK_RFC = 0x1, + BT_8821C_1ANT_GNT_BLOCK_BB = 0x2, + BT_8821C_1ANT_GNT_BLOCK_MAX +}; + +enum bt_8821c_1ant_lte_coex_table_type { + BT_8821C_1ANT_CTT_WL_VS_LTE = 0x0, + BT_8821C_1ANT_CTT_BT_VS_LTE = 0x1, + BT_8821C_1ANT_CTT_MAX +}; + +enum bt_8821c_1ant_lte_break_table_type { + BT_8821C_1ANT_LBTT_WL_BREAK_LTE = 0x0, + BT_8821C_1ANT_LBTT_BT_BREAK_LTE = 0x1, + BT_8821C_1ANT_LBTT_LTE_BREAK_WL = 0x2, + BT_8821C_1ANT_LBTT_LTE_BREAK_BT = 0x3, + BT_8821C_1ANT_LBTT_MAX +}; + +enum bt_info_src_8821c_1ant { + BT_INFO_SRC_8821C_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8821C_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8821C_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8821C_1ANT_MAX +}; + +enum bt_8821c_1ant_bt_status { + BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8821C_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8821C_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8821C_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8821C_1ANT_BT_STATUS_MAX +}; + +enum bt_8821c_1ant_wifi_status { + BT_8821C_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8821C_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8821C_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8821C_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, + BT_8821C_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8821C_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8821C_1ANT_WIFI_STATUS_MAX +}; + +enum bt_8821c_1ant_coex_algo { + BT_8821C_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8821C_1ANT_COEX_ALGO_SCO = 0x1, + BT_8821C_1ANT_COEX_ALGO_HID = 0x2, + BT_8821C_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8821C_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8821C_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8821C_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8821C_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8821C_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8821C_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8821C_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8821C_1ANT_COEX_ALGO_MAX = 0xb, +}; + +enum bt_8821c_1ant_ext_ant_switch_type { + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0, + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1, + BT_8821C_1ANT_EXT_ANT_SWITCH_NONE = 0x2, + BT_8821C_1ANT_EXT_ANT_SWITCH_MAX +}; + + +enum bt_8821c_1ant_ext_ant_switch_ctrl_type { + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_MAX +}; + +enum bt_8821c_1ant_ext_ant_switch_pos_type { + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_BT = 0x0, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLG = 0x1, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLA = 0x2, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE = 0x3, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_MAX +}; + +enum bt_8821c_1ant_ext_band_switch_pos_type { + BT_8821C_1ANT_EXT_BAND_SWITCH_TO_WLG = 0x0, + BT_8821C_1ANT_EXT_BAND_SWITCH_TO_WLA = 0x1, + BT_8821C_1ANT_EXT_BAND_SWITCH_TO_MAX +}; + +enum bt_8821c_1ant_int_block { + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_MAX +}; + +enum bt_8821c_1ant_phase { + BT_8821C_1ANT_PHASE_COEX_INIT = 0x0, + BT_8821C_1ANT_PHASE_WLANONLY_INIT = 0x1, + BT_8821C_1ANT_PHASE_WLAN_OFF = 0x2, + BT_8821C_1ANT_PHASE_2G_RUNTIME = 0x3, + BT_8821C_1ANT_PHASE_5G_RUNTIME = 0x4, + BT_8821C_1ANT_PHASE_BTMPMODE = 0x5, + BT_8821C_1ANT_PHASE_ANTENNA_DET = 0x6, + BT_8821C_1ANT_PHASE_COEX_POWERON = 0x7, + BT_8821C_1ANT_PHASE_MAX +}; + +enum bt_8821c_1ant_Scoreboard { + BT_8821C_1ANT_SCOREBOARD_ACTIVE = BIT(0), + BT_8821C_1ANT_SCOREBOARD_ONOFF = BIT(1), + BT_8821C_1ANT_SCOREBOARD_SCAN = BIT(2), + BT_8821C_1ANT_SCOREBOARD_UNDERTEST = BIT(3), + BT_8821C_1ANT_SCOREBOARD_WLBUSY = BIT(6) +}; + +struct coex_dm_8821c_1ant { + /* hw setting */ + u32 pre_ant_pos_type; + u32 cur_ant_pos_type; + /* fw mechanism */ + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + /* sw mechanism */ + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + + u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ + u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ + u16 backup_retry_limit; + u8 backup_ampdu_max_time; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + u32 pre_ra_mask; + u32 cur_ra_mask; + u8 pre_arfr_type; + u8 cur_arfr_type; + u8 pre_retry_limit_type; + u8 cur_retry_limit_type; + u8 pre_ampdu_time_type; + u8 cur_ampdu_time_type; + u32 arp_cnt; + + u32 pre_ext_ant_switch_status; + u32 cur_ext_ant_switch_status; + + u8 pre_ext_band_switch_status; + u8 cur_ext_band_switch_status; + + u8 pre_int_block_status; + u8 cur_int_block_status; + + u8 error_condition; +}; + +struct coex_sta_8821c_1ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + u8 num_of_profile; + + boolean under_lps; + boolean under_ips; + u32 specific_pkt_period_cnt; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + boolean is_hiPri_rx_overhead; + s8 bt_rssi; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + u8 bt_info_c2h[BT_INFO_SRC_8821C_1ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8821C_1ANT_MAX]; + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; + boolean c2h_bt_page; /* Add for win8.1 page out issue */ + boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ + + u8 bt_info_ext; + u8 bt_info_ext2; + u32 pop_event_cnt; + u8 scan_ap_num; + u8 bt_retry_cnt; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + + boolean cck_lock; + boolean pre_ccklock; + boolean cck_ever_lock; + u8 coex_table_type; + + boolean force_lps_on; + + boolean concurrent_rx_mode_on; + + u16 score_board; + u8 isolation_btween_wb; /* 0~ 50 */ + + u8 a2dp_bit_pool; + u8 cut_version; + boolean acl_busy; + boolean bt_create_connection; + + u32 bt_coex_supported_feature; + u32 bt_coex_supported_version; + + u8 bt_ble_scan_type; + u32 bt_ble_scan_para[3]; + + boolean run_time_state; + boolean freeze_coexrun_by_btinfo; + + boolean is_A2DP_3M; + boolean voice_over_HOGP; + u8 bt_info; + boolean is_autoslot; + u8 forbidden_slot; + u8 hid_busy_num; + u8 hid_pair_cnt; + + u32 cnt_RemoteNameReq; + u32 cnt_setupLink; + u32 cnt_ReInit; + u32 cnt_IgnWlanAct; + u32 cnt_Page; + u32 cnt_RoleSwitch; + + u16 bt_reg_vendor_ac; + u16 bt_reg_vendor_ae; + + boolean is_setupLink; + u8 wl_noisy_level; + u32 gnt_error_cnt; + + u8 bt_afh_map[10]; + u8 bt_relink_downcount; + boolean is_tdma_btautoslot; + boolean is_tdma_btautoslot_hang; +}; + + +#define BT_8821C_1ANT_EXT_BAND_SWITCH_USE_DPDT 0 +#define BT_8821C_1ANT_EXT_BAND_SWITCH_USE_SPDT 1 + + +struct rfe_type_8821c_1ant { + + u8 rfe_module_type; + boolean ext_ant_switch_exist; + u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */ + u8 ext_ant_switch_ctrl_polarity; /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ + + boolean ext_band_switch_exist; + u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */ + u8 ext_band_switch_ctrl_polarity; + + boolean ant_at_main_port; + + boolean wlg_Locate_at_btg; /* If true: WLG at BTG, If false: WLG at WLAG */ + + boolean ext_ant_switch_diversity; /* If diversity on */ +}; + +#define BT_8821C_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ +#define BT_8821C_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ +#define BT_8821C_1ANT_ANTDET_BUF_LEN 16 + +struct psdscan_sta_8821c_1ant { + + u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ + u32 ant_det_bt_tx_time; + u32 ant_det_pre_psdscan_peak_val; + boolean ant_det_is_ant_det_available; + u32 ant_det_psd_scan_peak_val; + boolean ant_det_is_btreply_available; + u32 ant_det_psd_scan_peak_freq; + + u8 ant_det_result; + u8 ant_det_peak_val[BT_8821C_1ANT_ANTDET_BUF_LEN]; + u8 ant_det_peak_freq[BT_8821C_1ANT_ANTDET_BUF_LEN]; + u32 ant_det_try_count; + u32 ant_det_fail_count; + u32 ant_det_inteval_count; + u32 ant_det_thres_offset; + + u32 real_cent_freq; + s32 real_offset; + u32 real_span; + + u32 psd_band_width; /* unit: Hz */ + u32 psd_point; /* 128/256/512/1024 */ + u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_start_point; + u32 psd_stop_point; + u32 psd_max_value_point; + u32 psd_max_value; + u32 psd_max_value2; + u32 psd_avg_value; /* filter loop_max_value that below BT_8821C_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/ + u32 psd_loop_max_value[BT_8821C_1ANT_ANTDET_PSD_SWWEEPCOUNT]; /*max value in each loop */ + u32 psd_start_base; + u32 psd_avg_num; /* 1/8/16/32 */ + u32 psd_gen_count; + boolean is_AntDet_running; + boolean is_psd_show_max_only; +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8821c1ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8821c1ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8821c1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8821c1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); +void ex_halbtc8821c1ant_antenna_isolation(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); + +void ex_halbtc8821c1ant_psd_scan(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); +void ex_halbtc8821c1ant_display_ant_detection(IN struct btc_coexist *btcoexist); + +#else +#define ex_halbtc8821c1ant_power_on_setting(btcoexist) +#define ex_halbtc8821c1ant_pre_load_firmware(btcoexist) +#define ex_halbtc8821c1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8821c1ant_init_coex_dm(btcoexist) +#define ex_halbtc8821c1ant_ips_notify(btcoexist, type) +#define ex_halbtc8821c1ant_lps_notify(btcoexist, type) +#define ex_halbtc8821c1ant_scan_notify(btcoexist, type) +#define ex_halbtc8821c1ant_switchband_notify(btcoexist,type) +#define ex_halbtc8821c1ant_connect_notify(btcoexist, type) +#define ex_halbtc8821c1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8821c1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8821c1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8821c1ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8821c1ant_halt_notify(btcoexist) +#define ex_halbtc8821c1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8821c1ant_coex_dm_reset(btcoexist) +#define ex_halbtc8821c1ant_periodical(btcoexist) +#define ex_halbtc8821c1ant_display_coex_info(btcoexist) +#define ex_halbtc8821c1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8821c1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8821c1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8821c1ant_display_ant_detection(btcoexist) +#endif + +#endif + + diff --git a/hal/btc/halbtc8821c2ant.c b/hal/btc/halbtc8821c2ant.c new file mode 100644 index 0000000..aa550b4 --- /dev/null +++ b/hal/btc/halbtc8821c2ant.c @@ -0,0 +1,5965 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for RTL8821C Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8821C_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8821c_2ant glcoex_dm_8821c_2ant; +static struct coex_dm_8821c_2ant *coex_dm = &glcoex_dm_8821c_2ant; +static struct coex_sta_8821c_2ant glcoex_sta_8821c_2ant; +static struct coex_sta_8821c_2ant *coex_sta = &glcoex_sta_8821c_2ant; +static struct psdscan_sta_8821c_2ant gl_psd_scan_8821c_2ant; +static struct psdscan_sta_8821c_2ant *psd_scan = &gl_psd_scan_8821c_2ant; +static struct rfe_type_8821c_2ant gl_rfe_type_8821c_2ant; +static struct rfe_type_8821c_2ant *rfe_type = &gl_rfe_type_8821c_2ant; + +const char *const glbt_info_src_8821c_2ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u32 glcoex_ver_date_8821c_2ant = 20161107; +u32 glcoex_ver_8821c_2ant = 0x0a; +u32 glcoex_ver_btdesired_8821c_2ant = 0x0a; + + +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8821c2ant_ + * ************************************************************ */ +u8 halbtc8821c2ant_bt_rssi_state(u8 *ppre_bt_rssi_state, u8 level_num, + u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = *ppre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return *ppre_bt_rssi_state; + } + + if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + *ppre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + +u8 halbtc8821c2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh, + IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = *pprewifi_rssi_state; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return *pprewifi_rssi_state; + } + + if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + *pprewifi_rssi_state = wifi_rssi_state; + + return wifi_rssi_state; +} + +void halbtc8821c2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist, + IN u8 isolation_measuared) +{ + s8 interference_wl_tx = 0, interference_bt_tx = 0; + + + interference_wl_tx = BT_8821C_2ANT_WIFI_MAX_TX_POWER - + isolation_measuared; + interference_bt_tx = BT_8821C_2ANT_BT_MAX_TX_POWER - + isolation_measuared; + + + + coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; + coex_sta->wifi_coex_thres2 = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES2; + + coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1; + coex_sta->bt_coex_thres2 = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES2; + + + /* + coex_sta->wifi_coex_thres = interference_wl_tx + BT_8821C_2ANT_WIFI_SIR_THRES1; + coex_sta->wifi_coex_thres2 = interference_wl_tx + BT_8821C_2ANT_WIFI_SIR_THRES2; + + coex_sta->bt_coex_thres = interference_bt_tx + BT_8821C_2ANT_BT_SIR_THRES1; + coex_sta->bt_coex_thres2 = interference_bt_tx + BT_8821C_2ANT_BT_SIR_THRES2; + */ + + + + + + /* + if ( BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - + BT_8821C_2ANT_DEFAULT_ISOLATION) ) + coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; + else + coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 - (isolation_measuared - + BT_8821C_2ANT_DEFAULT_ISOLATION); + + if ( BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - + BT_8821C_2ANT_DEFAULT_ISOLATION) ) + coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1; + else + coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 - (isolation_measuared - + BT_8821C_2ANT_DEFAULT_ISOLATION); + + */ +} + + +void halbtc8821c2ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); +} + +void halbtc8821c2ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No query BT info because BT is disabled!\n"); + BTC_TRACE(trace_buf); + return; + } + + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); +} + +void halbtc8821c2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, + cnt_autoslot_hang = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); + + BTC_TRACE(trace_buf); + + if (BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + if (coex_sta->high_priority_rx >= 15) { + if (cnt_overhead < 3) + cnt_overhead++; + + if (cnt_overhead == 3) + coex_sta->is_hiPri_rx_overhead = true; + + } else { + if (cnt_overhead > 0) + cnt_overhead--; + + if (cnt_overhead == 0) + coex_sta->is_hiPri_rx_overhead = false; + } + } + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + + if ((coex_sta->low_priority_tx > 1150) && + (!coex_sta->c2h_bt_inquiry_page)) + coex_sta->pop_event_cnt++; + + if ((coex_sta->low_priority_rx >= 1150) && + (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) + && (!coex_sta->under_ips) + && (!coex_sta->c2h_bt_inquiry_page) + && ((bt_link_info->a2dp_exist) || (bt_link_info->pan_exist))) { + if (cnt_slave >= 2) { + bt_link_info->slave_role = true; + cnt_slave = 2; + } else + cnt_slave++; + } else { + if (cnt_slave == 0) { + bt_link_info->slave_role = false; + cnt_slave = 0; + } else + cnt_slave--; + } + + if (coex_sta->is_tdma_btautoslot) { + if ((coex_sta->low_priority_tx >= 1300) && + (coex_sta->low_priority_rx <= 150)) { + if (cnt_autoslot_hang >= 2) { + coex_sta->is_tdma_btautoslot_hang = true; + cnt_autoslot_hang = 2; + } else + cnt_autoslot_hang++; + } else { + if (cnt_autoslot_hang == 0) { + coex_sta->is_tdma_btautoslot_hang = false; + cnt_autoslot_hang = 0; + } else + cnt_autoslot_hang--; + } + } + + if (!coex_sta->bt_disabled) { + + if ((coex_sta->high_priority_tx == 0) && + (coex_sta->high_priority_rx == 0) && + (coex_sta->low_priority_tx == 0) && + (coex_sta->low_priority_rx == 0)) { + num_of_bt_counter_chk++; + if (num_of_bt_counter_chk >= 3) { + halbtc8821c2ant_query_bt_info(btcoexist); + num_of_bt_counter_chk = 0; + } + } + } + +} + + +void halbtc8821c2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ +#if 1 + s32 wifi_rssi = 0; + boolean wifi_busy = false, wifi_under_b_mode = false, + wifi_scan = false; + boolean bt_idle = false, wl_idle = false; + static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, + wl_noisy_count1 = 3, wl_noisy_count2 = 0; + u32 total_cnt, reg_val1, reg_val2, cck_cnt; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_VHT); + + cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; + + if ((coex_dm->bt_status == + BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE) || + (coex_dm->bt_status == + BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE) || + (coex_sta->bt_disabled)) + bt_idle = true; + + if (cck_cnt > 250) { + if (wl_noisy_count2 < 3) + wl_noisy_count2++; + + if (wl_noisy_count2 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count1 = 0; + } + + } else if (cck_cnt < 50) { + if (wl_noisy_count0 < 3) + wl_noisy_count0++; + + if (wl_noisy_count0 == 3) { + wl_noisy_count1 = 0; + wl_noisy_count2 = 0; + } + + } else { + if (wl_noisy_count1 < 3) + wl_noisy_count1++; + + if (wl_noisy_count1 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count2 = 0; + } + } + + if (wl_noisy_count2 == 3) + coex_sta->wl_noisy_level = 2; + else if (wl_noisy_count1 == 3) + coex_sta->wl_noisy_level = 1; + else + coex_sta->wl_noisy_level = 0; + + if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { + total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + + coex_sta->crc_ok_11n_vht; + + if ((coex_dm->bt_status == + BT_8821C_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == + BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (coex_dm->bt_status == + BT_8821C_1ANT_BT_STATUS_SCO_BUSY)) { + if (coex_sta->crc_ok_cck > (total_cnt - + coex_sta->crc_ok_cck)) { + if (cck_lock_counter < 3) + cck_lock_counter++; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + if (!coex_sta->pre_ccklock) { + + if (cck_lock_counter >= 3) + coex_sta->cck_lock = true; + else + coex_sta->cck_lock = false; + } else { + if (cck_lock_counter == 0) + coex_sta->cck_lock = false; + else + coex_sta->cck_lock = true; + } + + if (coex_sta->cck_lock) + coex_sta->cck_ever_lock = true; + + coex_sta->pre_ccklock = coex_sta->cck_lock; + +#endif +} + +void halbtc8821c2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + boolean bt_busy = false; + + coex_sta->num_of_profile = 0; + + /* set link exist status */ + if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = false; + coex_sta->pan_exist = false; + coex_sta->a2dp_exist = false; + coex_sta->hid_exist = false; + coex_sta->sco_exist = false; + } else { /* connection exists */ + coex_sta->bt_link_exist = true; + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_FTP) { + coex_sta->pan_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->pan_exist = false; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_A2DP) { + coex_sta->a2dp_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->a2dp_exist = false; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_HID) { + coex_sta->hid_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->hid_exist = false; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) { + coex_sta->sco_exist = true; + coex_sta->num_of_profile++; + } else + coex_sta->sco_exist = false; + + } + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + bt_link_info->acl_busy = coex_sta->acl_busy; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = true; + bt_link_info->bt_link_exist = true; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = true; + else + bt_link_info->sco_only = false; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = true; + else + bt_link_info->a2dp_only = false; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = true; + else + bt_link_info->pan_only = false; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = true; + else + bt_link_info->hid_only = false; + + if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_INQ_PAGE) { + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_INQ_PAGE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); + } else if (!(coex_sta->bt_info & BT_INFO_8821C_2ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + } else if (coex_sta->bt_info == BT_INFO_8821C_2ANT_B_CONNECTION) { + /* connection exists but no busy */ + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + } else if (((coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_BUSY)) && + (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_ACL_BUSY)) { + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_ACL_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); + } else if ((coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + } else if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + } else { + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + } + + BTC_TRACE(trace_buf); + + if ((BT_8821C_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8821C_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8821C_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + bt_busy = true; + else + bt_busy = false; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); +} + +void halbtc8821c2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + h2c_parameter[0] = + 0x1; /* enable BT AFH skip WL channel for 8821c because BT Rx LO interference */ + /* h2c_parameter[0] = 0x0; */ + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); + +} + +void halbtc8821c2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, + IN u8 dac_swing_lvl) +{ + u8 h2c_parameter[1] = {0}; + + /* There are several type of dacswing */ + /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ + h2c_parameter[0] = dac_swing_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); +} + +void halbtc8821c2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 fw_dac_swing_lvl) +{ + coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; + + if (!force_exec) { + if (coex_dm->pre_fw_dac_swing_lvl == + coex_dm->cur_fw_dac_swing_lvl) + return; + } + + halbtc8821c2ant_set_fw_dac_swing_level(btcoexist, + coex_dm->cur_fw_dac_swing_lvl); + + coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; +} + +void halbtc8821c2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN u8 dec_bt_pwr_lvl) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = dec_bt_pwr_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); +} + +void halbtc8821c2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 dec_bt_pwr_lvl) +{ + coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; + + if (!force_exec) { + if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) + return; + } + halbtc8821c2ant_set_fw_dec_bt_pwr(btcoexist, + coex_dm->cur_bt_dec_pwr_lvl); + + coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; +} + + +void halbtc8821c2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + +#if 1 + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == + coex_dm->cur_low_penalty_ra) + return; + } + + if (low_penalty_ra) + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15); + else + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; + +#endif + +} + + +void halbtc8821c2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean enable_auto_report) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = 0; + + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); + + btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); +} + +void halbtc8821c2ant_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable_auto_report) +{ + coex_dm->cur_bt_auto_report = enable_auto_report; + + if (!force_exec) { + if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) + return; + } + halbtc8821c2ant_set_bt_auto_report(btcoexist, + coex_dm->cur_bt_auto_report); + + coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; +} + +void halbtc8821c2ant_write_score_board( + IN struct btc_coexist *btcoexist, + IN u16 bitpos, + IN boolean state +) +{ + + static u16 originalval = 0x8002; + + if (state) + originalval = originalval | bitpos; + else + originalval = originalval & (~bitpos); + + + btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); + +} + +void halbtc8821c2ant_read_score_board( + IN struct btc_coexist *btcoexist, + IN u16 *score_board_val +) +{ + + *score_board_val = (btcoexist->btc_read_2byte(btcoexist, + 0xaa)) & 0x7fff; +} + + +void halbtc8821c2ant_post_state_to_bt( + IN struct btc_coexist *btcoexist, + IN u16 type, + IN boolean state +) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c2ant_post_state_to_bt: type = %d, state =%d\n", + type, state); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_write_score_board(btcoexist, (u16) type, state); +} + + +boolean halbtc8821c2ant_is_wifibt_status_changed(IN struct btc_coexist + *btcoexist) +{ + static boolean pre_wifi_busy = false, pre_under_4way = false, + pre_bt_hs_on = false, pre_bt_off = false, + pre_bt_slave = false; + static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0; + boolean wifi_busy = false, under_4way = false, bt_hs_on = false; + boolean wifi_connected = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (coex_sta->bt_disabled != pre_bt_off) { + pre_bt_off = coex_sta->bt_disabled; + + if (coex_sta->bt_disabled) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + return true; + } + + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + + if (wifi_busy) + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, true); + else + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, false); + return true; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return true; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return true; + } + if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { + pre_wl_noisy_level = coex_sta->wl_noisy_level; + return true; + } + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->hid_busy_num != pre_hid_busy_num) { + pre_hid_busy_num = coex_sta->hid_busy_num; + return true; + } + } + + if (bt_link_info->slave_role != pre_bt_slave) { + pre_bt_slave = bt_link_info->slave_role; + return true; + } + + return false; +} + +void halbtc8821c2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = true, bt_disabled = false, wifi_under_5g = false; + u16 u16tmp; + + /* This function check if bt is disabled */ +#if 0 + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = false; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = false; + + +#else + + /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */ + halbtc8821c2ant_read_score_board(btcoexist, &u16tmp); + + bt_active = u16tmp & BIT(1); + + +#endif + + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } else { + + bt_disable_cnt++; + if (bt_disable_cnt >= 10) { + bt_disabled = true; + bt_disable_cnt = 10; + } + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((wifi_under_5g) || (bt_disabled)) + halbtc8821c2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); + else + halbtc8821c2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true); + + + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + } + +} + +void halbtc8821c2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, + boolean isenable) +{ +#if BT_8821C_2ANT_COEX_DBG + static u8 bitVal[5] = {0, 0, 0, 0, 0}; + static boolean state = false; + /* + if (state ==isenable) + return; + else + state = isenable; + */ + if (isenable) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], enable_gnt_to_gpio!!\n"); + BTC_TRACE(trace_buf); + + /* enable GNT_WL, GNT_BT to GPIO for debug */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); + + /* store original value */ + bitVal[0] = (btcoexist->btc_read_1byte(btcoexist, + 0x66) & BIT(4)) >> 4; /*0x66[4] */ + bitVal[1] = (btcoexist->btc_read_1byte(btcoexist, + 0x67) & BIT(0)); /*0x66[8] */ + bitVal[2] = (btcoexist->btc_read_1byte(btcoexist, + 0x42) & BIT(3)) >> 3; /*0x40[19] */ + bitVal[3] = (btcoexist->btc_read_1byte(btcoexist, + 0x65) & BIT(7)) >> 7; /*0x64[15] */ + bitVal[4] = (btcoexist->btc_read_1byte(btcoexist, + 0x72) & BIT(2)) >> 2; /*0x70[18] */ + + /* switch GPIO Mux */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), + 0x0); /*0x66[4] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), + 0x0); /*0x66[8] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), + 0x0); /*0x40[19] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), + 0x0); /*0x64[15] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), + 0x0); /*0x70[18] = 0 */ + + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], disable_gnt_to_gpio!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); + + /* Restore original value */ + /* switch GPIO Mux */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), + bitVal[0]); /*0x66[4] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), + bitVal[1]); /*0x66[8] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), + bitVal[2]); /*0x40[19] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), + bitVal[3]); /*0x64[15] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), + bitVal[4]); /*0x70[18] = 0 */ + } + +#endif +} + +u32 halbtc8821c2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, + IN u16 reg_addr) +{ + u32 j = 0; + + + /* wait for ready bit before access 0x1700 */ + btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr); + + do { + j++; + } while (((btcoexist->btc_read_1byte(btcoexist, + 0x1703)&BIT(5)) == 0) && + (j < BT_8821C_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); + + + return btcoexist->btc_read_4byte(btcoexist, + 0x1708); /* get read data */ + +} + +void halbtc8821c2ant_ltecoex_indirect_write_reg(IN struct btc_coexist + *btcoexist, + IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) +{ + u32 val, i = 0, j = 0, bitpos = 0; + + + if (bit_mask == 0x0) + return; + if (bit_mask == 0xffffffff) { + btcoexist->btc_write_4byte(btcoexist, 0x1704, + reg_value); /* put write data */ + + /* wait for ready bit before access 0x1700 */ + do { + j++; + } while (((btcoexist->btc_read_1byte(btcoexist, + 0x1703)&BIT(5)) == 0) && + (j < BT_8821C_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); + + + btcoexist->btc_write_4byte(btcoexist, 0x1700, + 0xc00F0000 | reg_addr); + } else { + for (i = 0; i <= 31; i++) { + if (((bit_mask >> i) & 0x1) == 0x1) { + bitpos = i; + break; + } + } + + /* read back register value before write */ + val = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + reg_addr); + val = (val & (~bit_mask)) | (reg_value << bitpos); + + btcoexist->btc_write_4byte(btcoexist, 0x1704, + val); /* put write data */ + + /* wait for ready bit before access 0x7c0 */ + do { + j++; + } while (((btcoexist->btc_read_1byte(btcoexist, + 0x1703)&BIT(5)) == 0) && + (j < BT_8821C_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); + + + btcoexist->btc_write_4byte(btcoexist, 0x1700, + 0xc00F0000 | reg_addr); + + } + +} + +void halbtc8821c2ant_ltecoex_enable(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 val; + + val = (enable) ? 1 : 0; + halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, + val); /* 0x38[7] */ + +} + +void halbtc8821c2ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, + IN boolean wifi_control) +{ + u8 val; + + val = (wifi_control) ? 1 : 0; + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, + val); /* 0x70[26] */ + +} + +void halbtc8821c2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; + + val_orig = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + switch (control_block) { + case BT_8821C_2ANT_GNT_BLOCK_RFC_BB: + default: + val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff); + break; + case BT_8821C_2ANT_GNT_BLOCK_RFC: + val = (val << 14) | (val_orig & 0xffff3fff); + break; + case BT_8821C_2ANT_GNT_BLOCK_BB: + val = (val << 10) | (val_orig & 0xfffff3ff); + break; + } + + halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); +} + +void halbtc8821c2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; + + val_orig = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + switch (control_block) { + case BT_8821C_2ANT_GNT_BLOCK_RFC_BB: + default: + val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff); + break; + case BT_8821C_2ANT_GNT_BLOCK_RFC: + val = (val << 12) | (val_orig & 0xffffcfff); + break; + case BT_8821C_2ANT_GNT_BLOCK_BB: + val = (val << 8) | (val_orig & 0xfffffcff); + break; + } + + halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); +} + +void halbtc8821c2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u16 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8821C_2ANT_CTT_WL_VS_LTE: + reg_addr = 0xa0; + break; + case BT_8821C_2ANT_CTT_BT_VS_LTE: + reg_addr = 0xa4; + break; + } + + if (reg_addr != 0x0000) + halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ + + +} + + +void halbtc8821c2ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u8 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8821C_2ANT_LBTT_WL_BREAK_LTE: + reg_addr = 0xa8; + break; + case BT_8821C_2ANT_LBTT_BT_BREAK_LTE: + reg_addr = 0xac; + break; + case BT_8821C_2ANT_LBTT_LTE_BREAK_WL: + reg_addr = 0xb0; + break; + case BT_8821C_2ANT_LBTT_LTE_BREAK_BT: + reg_addr = 0xb4; + break; + } + + if (reg_addr != 0x0000) + halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ + + +} + +void halbtc8821c2ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 interval, + IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, + IN u8 val0x6c4_b3) +{ + static u8 pre_h2c_parameter[6] = {0}; + u8 cur_h2c_parameter[6] = {0}; + u8 i, match_cnt = 0; + + cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ + + cur_h2c_parameter[1] = interval; + cur_h2c_parameter[2] = val0x6c4_b0; + cur_h2c_parameter[3] = val0x6c4_b1; + cur_h2c_parameter[4] = val0x6c4_b2; + cur_h2c_parameter[5] = val0x6c4_b3; + + if (!force_exec) { + for (i = 1; i <= 5; i++) { + if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) + break; + + match_cnt++; + } + + if (match_cnt == 5) + return; + } + + for (i = 1; i <= 5; i++) + pre_h2c_parameter[i] = cur_h2c_parameter[i]; + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); +} + + + +void halbtc8821c2ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8821c2ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8821c2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8821c2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + u32 break_table; + u8 select_table; + + coex_sta->coex_table_type = type; + + if (coex_sta->concurrent_rx_mode_on == true) { + break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ + select_table = + 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ + } else { + break_table = 0xffffff; + select_table = 0x3; + } + + switch (type) { + case 0: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0xffffffff, 0xffffffff, break_table, select_table); + break; + case 1: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, select_table); + break; + case 2: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table); + break; + case 3: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, select_table); + break; + case 4: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, select_table); + break; + case 5: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, break_table, select_table); + break; + case 6: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xfafafafa, break_table, select_table); + break; + case 7: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xaa5a5a5a, break_table, select_table); + break; + case 8: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xfafafafa, break_table, select_table); + break; + case 9: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0xaaaa5aaa, break_table, select_table); + break; + default: + break; + } +} + +void halbtc8821c2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 h2c_parameter[1] = {0}; + + if (enable) { + h2c_parameter[0] |= BIT(0); /* function enable */ + } + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + +void halbtc8821c2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8821c2ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8821c2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8821c2ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8821c2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8821c2ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + u8 h2c_parameter[5] = {0, 0, 0, 0x40, 0}; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + /*halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8); */ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + /*halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, + 8);*/ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + +void halbtc8821c2ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = false; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + /* recover to original 32k low power setting */ + low_pwr_disable = false; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + case BTC_PS_LPS_ON: + halbtc8821c2ant_ps_tdma_check_for_power_save_state( + btcoexist, true); + halbtc8821c2ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = true; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + coex_sta->force_lps_on = true; + break; + case BTC_PS_LPS_OFF: + halbtc8821c2ant_ps_tdma_check_for_power_save_state( + btcoexist, false); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + coex_sta->force_lps_on = false; + break; + default: + break; + } +} + + + +void halbtc8821c2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if (byte5 & BIT(2)) + coex_sta->is_tdma_btautoslot = true; + else + coex_sta->is_tdma_btautoslot = false; + + /* release bt-auto slot for auto-slot hang is detected!! */ + if (coex_sta->is_tdma_btautoslot) + if ((coex_sta->is_tdma_btautoslot_hang) || + (bt_link_info->slave_role)) + byte5 = byte5 & 0xfb; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if (ap_enable) { + if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], FW for AP mode\n"); + BTC_TRACE(trace_buf); + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + + halbtc8821c2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + } + } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + + halbtc8821c2ant_power_save_state( + btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); + } else { + halbtc8821c2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, + 0x0); + } + + + h2c_parameter[0] = real_byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = real_byte5; + + coex_dm->ps_tdma_para[0] = real_byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = real_byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); +} + +void halbtc8821c2ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ + if (bt_link_info->slave_role) + psTdmaByte4Modify = 0x1; + else + psTdmaByte4Modify = 0x0; + + if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { + force_exec = true; + pre_psTdmaByte4Modify = psTdmaByte4Modify; + } + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n", + (coex_dm->cur_ps_tdma_on ? "on" : "off"), + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + return; + } + } + + if (coex_dm->cur_ps_tdma_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(on, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } + + + if (turn_on) { + switch (type) { + case 1: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x91, + 0x54 | psTdmaByte4Modify); + break; + case 2: + default: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); + break; + case 3: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x3a, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 4: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x21, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 5: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 6: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 7: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x20, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 8: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x15, 0x03, 0x11, + 0x11); + break; + case 10: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x30, 0x03, 0x11, + 0x10); + break; + case 11: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, + 0x10 | psTdmaByte4Modify); + break; + case 12: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, 0x11); + break; + case 13: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x1c, 0x03, 0x11, + 0x10 | psTdmaByte4Modify); + break; + case 14: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x20, 0x03, 0x11, + 0x11); + break; + case 15: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x14); + break; + case 16: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x15); + break; + case 21: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x30, 0x03, 0x11, + 0x10); + break; + case 22: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, + 0x10); + break; + case 23: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x10); + break; + case 51: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 101: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x03, 0x10, + 0x54 | psTdmaByte4Modify); + break; + case 102: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); + break; + case 103: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x3a, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 104: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x21, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 105: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x25, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 106: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 107: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x20, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 108: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 109: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x55, + 0x10, 0x03, 0x10, + 0x54 | psTdmaByte4Modify); + break; + case 110: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x55, + 0x30, 0x03, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 111: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x65, + 0x25, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); + break; + case 151: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x03, 0x10, + 0x50 | psTdmaByte4Modify); + break; + } + } else { + /* disable PS tdma */ + switch (type) { + case 0: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x40, 0x0); + break; + case 1: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x48, 0x0); + break; + default: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x40, 0x0); + break; + } + } + + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; +} + +void halbtc8821c2ant_set_int_block(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 pos_type) +{ +#if 0 + u8 regval_0xcba; + u32 u32tmp1 = 0; + + coex_dm->cur_int_block_status = pos_type; + + if (!force_exec) { + if (coex_dm->pre_int_block_status == + coex_dm->cur_int_block_status) + return; + } + + coex_dm->pre_int_block_status = coex_dm->cur_int_block_status; + + regval_0xcba = btcoexist->btc_read_1byte(btcoexist, 0xcba); + + switch (pos_type) { + + case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG: + regval_0xcba = (regval_0xcba | BIT(0)) & (~(BIT( + 2))); /* 0xcb8[16] = 1, 0xcb8[18] = 0, WL_G select BTG */ + regval_0xcba = regval_0xcba & 0x0f; + + /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc1d, 0x0f, 0x5); */ /* Gain Table */ + /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xa9e, 0x0f, 0x2); */ /* CCK Gain Table */ + + break; + case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG: + regval_0xcba = regval_0xcba & (~(BIT(2) | BIT( + 0))); /* 0xcb8[16] = 0, 0xcb8[18] = 0, WL_G select WLAG */ + + /* regval_0xcba = regval_0xcba | BIT(4) | BIT(5) ; */ /* 0xcb8[21:20] = 2b'11, WL_G @ WLAG on */ + /* regval_0xcba = (regval_0xcba | BIT(6)) & (~(BIT(7)) ) ; */ /* 0xcb8[23:22] = 2b'01, WL_A @ WLAG off */ + /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc1d, 0x0f, 0x0); */ /* Gain Table */ + /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xa9e, 0x0f, 0x6); */ /* CCK Gain Table */ + + break; + case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG: + regval_0xcba = regval_0xcba & (~(BIT(2) | BIT( + 0))); /* 0xcb8[16] = 0, 0xcb8[18] = 0, WL_G select WLAG */ + /*regval_0xcba = (regval_0xcba | BIT(4)) & (~(BIT(5))); */ /* 0xcb8[21:20] = 2b'01, WL_G @ WLAG off */ + /*regval_0xcba = regval_0xcba | BIT(6) | BIT(7); */ /* 0xcb8[23:22] = 2b'11, WL_A @ WLAG on */ + + break; + } + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcba, 0xff, + regval_0xcba); + + u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb8); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (After Int Block setup) 0xcb8 = 0x%08x **********\n", + u32tmp1); + BTC_TRACE(trace_buf); + +#endif +} + +void halbtc8821c2ant_set_ext_band_switch(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 pos_type) +{ + +#if 0 + boolean switch_polatiry_inverse = false; + u8 regval_0xcb6; + u32 u32tmp1 = 0, u32tmp2 = 0; + + if (!rfe_type->ext_band_switch_exist) + return; + + coex_dm->cur_ext_band_switch_status = pos_type; + + if (!force_exec) { + if (coex_dm->pre_ext_band_switch_status == + coex_dm->cur_ext_band_switch_status) + return; + } + + coex_dm->pre_ext_band_switch_status = + coex_dm->cur_ext_band_switch_status; + + /* swap control polarity if use different switch control polarity*/ + switch_polatiry_inverse = (rfe_type->ext_band_switch_ctrl_polarity == 1 + ? ~switch_polatiry_inverse : switch_polatiry_inverse); + + /*swap control polarity for WL_A, default polarity 0xcb4[21] = 0 && 0xcb4[23] = 1 is for WL_G */ + switch_polatiry_inverse = (pos_type == + BT_8821C_2ANT_EXT_BAND_SWITCH_TO_WLA ? ~switch_polatiry_inverse + : switch_polatiry_inverse); + + regval_0xcb6 = btcoexist->btc_read_1byte(btcoexist, 0xcb6); + + /* for normal switch polrity, 0xcb4[21] =1 && 0xcb4[23] = 0 for WL_A, vice versa */ + regval_0xcb6 = (switch_polatiry_inverse == 1 ? ((regval_0xcb6 & (~(BIT( + 7)))) | BIT(5)) : ((regval_0xcb6 & (~(BIT(5)))) | BIT(7))); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb6, 0xff, + regval_0xcb6); + + u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb0); + u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (After Ext Band switch setup) 0xcb0 = 0x%08x, 0xcb4 = 0x%08x**********\n", + u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); +#endif + +} + +void halbtc8821c2ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + boolean switch_polatiry_inverse = false; + u8 regval_0xcb7 = 0, regval_0x64; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + + if (!rfe_type->ext_ant_switch_exist) + return; + + coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; + + if (!force_exec) { + if (coex_dm->pre_ext_ant_switch_status == + coex_dm->cur_ext_ant_switch_status) + return; + } + + coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status; + + /* swap control polarity if use different switch control polarity*/ + /* Normal switch polarity for DPDT, 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main */ + /* Normal switch polarity for SPDT, 0xcb4[29:28] = 2b'01 => Ant to BTG, 0xcb4[29:28] = 2b'10 => Ant to WLG */ + if (rfe_type->ext_ant_switch_ctrl_polarity) + switch_polatiry_inverse = ~switch_polatiry_inverse; + + /* swap control polarity if 1-Ant at Aux */ + if (rfe_type->ant_at_main_port == false) + switch_polatiry_inverse = ~switch_polatiry_inverse; + + switch (pos_type) { + default: + case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT: + case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE: + case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA: + + break; + case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG: + if (!rfe_type->wlg_Locate_at_btg) + switch_polatiry_inverse = ~switch_polatiry_inverse; + + break; + } + + if (board_info->ant_div_cfg) + ctrl_type = BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; + + + switch (ctrl_type) { + default: + case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x77); /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + + regval_0xcb7 = (switch_polatiry_inverse == false ? + 0x1 : 0x2); /* 0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, + 0x30, regval_0xcb7); + + break; + case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x66); /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + + regval_0xcb7 = (switch_polatiry_inverse == false ? + 0x2 : 0x1); /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, + 0x30, regval_0xcb7); + + break; + case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x88); /* */ + + /* no regval_0xcb7 setup required, because antenna switch control value by antenna diversity */ + + break; + case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x1); /* 0x4c[23] = 1 */ + + regval_0x64 = (switch_polatiry_inverse == false ? 0x0 : + 0x1); /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, + regval_0x64); + break; + case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x0); /* 0x4c[24] = 0 */ + + /* no setup required, because antenna switch control value by BT vendor 0x1c[1:0] */ + break; + } + + /* PAPE, LNA_ON control by BT while WLAN off for current leakage issue */ + if (ctrl_type == BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT) { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x0); /* PAPE 0x64[29] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, + 0x0); /* LNA_ON 0x64[28] = 0 */ + } else { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x1); /* PAPE 0x64[29] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, + 0x1); /* LNA_ON 0x64[28] = 1 */ + } + +#if BT_8821C_2ANT_COEX_DBG + + u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (After Ext Ant switch setup) 0xcb4 = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n", + u32tmp1, u32tmp2, u32tmp3); + BTC_TRACE(trace_buf); +#endif + +} + +void halbtc8821c2ant_set_rfe_type(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + + + /* the following setup should be got from Efuse in the future */ + rfe_type->rfe_module_type = board_info->rfe_type & 0x1f; + + rfe_type->ext_ant_switch_ctrl_polarity = 0; + + switch (rfe_type->rfe_module_type) { + case 0: + default: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; /*2-Ant, DPDT, WLG*/ + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 1: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, WLG */ + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 2: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, BTG */ + rfe_type->wlg_Locate_at_btg = true; + rfe_type->ant_at_main_port = true; + break; + case 3: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, WLG */ + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = false; + break; + case 4: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, BTG */ + rfe_type->wlg_Locate_at_btg = true; + rfe_type->ant_at_main_port = false; + break; + case 5: + rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_NONE; + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 6: + rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_NONE; + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 7: + rfe_type->ext_ant_switch_exist = true; /*2-Ant, DPDT, BTG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; + rfe_type->wlg_Locate_at_btg = true; + rfe_type->ant_at_main_port = true; + break; + } + +#if 0 + if (rfe_type->wlg_Locate_at_btg) + halbtc8821c2ant_set_int_block(btcoexist, FORCE_EXEC, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); + else + halbtc8821c2ant_set_int_block(btcoexist, FORCE_EXEC, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); +#endif + +} + + +void halbtc8821c2ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean force_exec, + IN u8 phase) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u32 cnt_bt_cal_chk = 0; + boolean is_in_mp_mode = false; + u8 u8tmp = 0; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + u16 u16tmp1 = 0; + + u32tmp1 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + /* To avoid indirect access fail */ + if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { + force_exec = true; + coex_sta->gnt_error_cnt++; + } + + +#if BT_8821C_2ANT_COEX_DBG + + u32tmp2 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0x54); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + u32tmp3, u8tmp, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); +#endif + + coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; + + if (!force_exec) { + if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) + return; + } + + coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; + + + switch (phase) { + case BT_8821C_2ANT_PHASE_COEX_POWERON: + + /* set Path control owner to WL at initial step */ + halbtc8821c2ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8821C_2ANT_PCO_BTSIDE); + + /* set GNT_BT to SW high */ + halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW high */ + halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + coex_sta->run_time_state = false; + + break; + case BT_8821C_2ANT_PHASE_COEX_INIT: + /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ + halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c2ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_2ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c2ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_2ANT_CTT_BT_VS_LTE, + 0xffff); + + + /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ + while (cnt_bt_cal_chk <= 20) { + u8tmp = btcoexist->btc_read_1byte( + btcoexist, 0x49c); + cnt_bt_cal_chk++; + + if (u8tmp & BIT(1)) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + break; + } + } + + /* set Path control owner to WL at initial step */ + halbtc8821c2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW high */ + halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW high */ + halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = false; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + break; + case BT_8821C_2ANT_PHASE_WLANONLY_INIT: + /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ + halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c2ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_2ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c2ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_2ANT_CTT_BT_VS_LTE, + 0xffff); + + /* set Path control owner to WL at initial step */ + halbtc8821c2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Low */ + halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_LOW); + /* Set GNT_WL to SW high */ + halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = false; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + break; + case BT_8821C_2ANT_PHASE_WLAN_OFF: + /* Disable LTE Coex Function in WiFi side */ + halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); + + /* set Path control owner to BT */ + halbtc8821c2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_2ANT_PCO_BTSIDE); + + /* Set Ext Ant Switch to BT control at wifi off step */ + halbtc8821c2ant_set_ext_ant_switch(btcoexist, + FORCE_EXEC, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE); + coex_sta->run_time_state = false; + break; + case BT_8821C_2ANT_PHASE_2G_RUNTIME: + case BT_8821C_2ANT_PHASE_2G_RUNTIME_CONCURRENT: + + while (cnt_bt_cal_chk <= 20) { + /* 0x49c[0]=1 WL IQK, 0x49c[1]=1 BT IQK*/ + u8tmp = btcoexist->btc_read_1byte(btcoexist, + 0x49c); + + cnt_bt_cal_chk++; + if (u8tmp & BIT(0)) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### WL is IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else if (u8tmp & BIT(1)) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + break; + } + } + + /* set Path control owner to WL at runtime step */ + halbtc8821c2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_2ANT_PCO_WLSIDE); + + if (phase == + BT_8821C_2ANT_PHASE_2G_RUNTIME_CONCURRENT) { + /* set GNT_BT to PTA */ + halbtc8821c2ant_ltecoex_set_gnt_bt( + btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_2ANT_SIG_STA_SET_BY_HW); + + /* Set GNT_WL to SW High */ + halbtc8821c2ant_ltecoex_set_gnt_wl( + btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + } else { + /* set GNT_BT to PTA */ + halbtc8821c2ant_ltecoex_set_gnt_bt( + btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_2ANT_SIG_STA_SET_BY_HW); + + /* Set GNT_WL to PTA */ + halbtc8821c2ant_ltecoex_set_gnt_wl( + btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_2ANT_SIG_STA_SET_BY_HW); + } + coex_sta->run_time_state = true; + + if (rfe_type->wlg_Locate_at_btg) + halbtc8821c2ant_set_int_block(btcoexist, + NORMAL_EXEC, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); + else + halbtc8821c2ant_set_int_block(btcoexist, + NORMAL_EXEC, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + break; + case BT_8821C_2ANT_PHASE_5G_RUNTIME: + + /* set Path control owner to WL at runtime step */ + halbtc8821c2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Hi */ + halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_2ANT_SIG_STA_SET_BY_HW); + + /* Set GNT_WL to SW Hi */ + halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = true; + + halbtc8821c2ant_set_int_block(btcoexist, + NORMAL_EXEC, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG); + + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + + break; + case BT_8821C_2ANT_PHASE_BTMPMODE: + /* Disable LTE Coex Function in WiFi side */ + halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); + + /* set Path control owner to WL */ + halbtc8821c2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Hi */ + halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + + /* Set GNT_WL to SW Lo */ + halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_LOW); + + coex_sta->run_time_state = false; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + break; + case BT_8821C_2ANT_PHASE_ANTENNA_DET: + halbtc8821c2ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8821C_2ANT_PCO_WLSIDE); + + /* set GNT_BT to high */ + halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to high */ + halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + coex_sta->run_time_state = false; + + break; + } + + if (phase != BT_8821C_2ANT_PHASE_WLAN_OFF) { + switch (ant_pos_type) { + default: + case BTC_ANT_WIFI_AT_MAIN + : + halbtc8821c2ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG); + break; + case BTC_ANT_WIFI_AT_AUX + : + halbtc8821c2ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT); + break; + case BTC_ANT_WIFI_AT_DIVERSITY + : + halbtc8821c2ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE); + break; + } + + } + + + +#if BT_8821C_2ANT_COEX_DBG + u32tmp1 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (After Ant-Setup phase---%d) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + phase, u32tmp3, u8tmp, u32tmp1, u32tmp2); + + BTC_TRACE(trace_buf); +#endif + +} + + +u8 halbtc8821c2ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = false; + u8 algorithm = BT_8821C_2ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 0) { + + if (bt_link_info->acl_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No-Profile busy\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_NOPROFILEBUSY; + } + } else if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_SCO; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP ==> A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_HID_A2DP; + } + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP ==> HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_HID_A2DP; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + + return algorithm; +} + + + +void halbtc8821c2ant_action_coex_all_off(IN struct btc_coexist *btcoexist) +{ + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + /* fw all off */ + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + +} + +void halbtc8821c2ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) +{ + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); +} + +void halbtc8821c2ant_action_bt_hs(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false, wifi_turbo = false; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif + + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres , 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2 , 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres , 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2 , 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + + + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = true; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } + +} + + +void halbtc8821c2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + + boolean wifi_connected = false; + boolean wifi_scan = false, wifi_link = false, wifi_roam = false; + boolean wifi_busy = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) + || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 8); + + if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 15); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 11); + } else if ((!wifi_connected) && (!wifi_scan)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi no-link + no-scan + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else if (bt_link_info->pan_exist) { + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + } else if (bt_link_info->a2dp_exist) { + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + } else { + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) + || (coex_sta->wifi_is_high_pri_task)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + } + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); +} + + +void halbtc8821c2ant_action_bt_relink(IN struct btc_coexist *btcoexist) +{ + /*halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8); + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); */ + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + coex_sta->bt_relink_downcount = 2; +} + + +void halbtc8821c2ant_action_bt_idle(IN struct btc_coexist *btcoexist) +{ + + boolean wifi_busy = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_busy) { + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); + } else { /* if wl busy */ + + if (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else { + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 8); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 12); + } + } + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + +} + + +/* SCO only or SCO+PAN(HS) */ +void halbtc8821c2ant_action_sco(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres , 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2 , 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres , 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2 , 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 1); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8); + } + +} + + +void halbtc8821c2ant_action_hid(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false; + u32 wifi_bw = 1; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres , 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2 , 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres , 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2 , 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + /*for 4/18 hid */ + if (coex_sta->hid_busy_num >= 2) { + + if (wifi_bw == 0) { /* if 11bg mode */ + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8821c2ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 111); + } else { + + if (wifi_busy) { + halbtc8821c2ant_coex_table_with_type( + btcoexist, + NORMAL_EXEC, 8); + halbtc8821c2ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 111); + } else { + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 3); + halbtc8821c2ant_ps_tdma(btcoexist, + NORMAL_EXEC, true, 14); + } + } + } else { + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 3); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 14); + } + } + +} + +/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ +void halbtc8821c2ant_action_a2dp(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false, wifi_turbo = false; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres , 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2 , 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres , 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2 , 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 1); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 16); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = true; + + if ((coex_sta->bt_relink_downcount != 0) + && (wifi_busy)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + + } else { + + if (wifi_turbo) + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + else + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 7); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 101); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 16); + /* halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 102); */ + } + + } + +} + +void halbtc8821c2ant_action_pan_edr(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false, wifi_turbo = false; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres , 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2 , 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres , 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2 , 0); + +#if 0 + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); +#endif + + +#if 1 + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 3); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 4); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = true; + + if (wifi_turbo) + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + else + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 7); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 103); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 104); + + } + +#endif + +} + +void halbtc8821c2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false; + u32 wifi_bw = 1; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres , 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2 , 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres , 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2 , 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 1); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 1); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = true; + + if ((coex_sta->bt_relink_downcount != 0) + && (wifi_busy)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + } else if (wifi_busy) { + if (coex_sta->hid_busy_num >= 2) { + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + + if (wifi_bw == 0) /* 11bg mode */ + halbtc8821c2ant_set_wltoggle_coex_table( + btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + else + halbtc8821c2ant_set_wltoggle_coex_table( + btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 109); + } else { + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 101); + } + } else { + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 1); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 15); + /* halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 102); */ + } + + } + +} + + +void halbtc8821c2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false, wifi_turbo = false; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif + + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres , 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2 , 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres , 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2 , 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) { + + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 7); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 5); + } else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 6); + + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = true; + + if (wifi_turbo) + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + else + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 7); + + if (wifi_busy) { + + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 107); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 105); + } else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 106); + + } + +} + + + +/* PAN(EDR)+A2DP */ +void halbtc8821c2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false, wifi_turbo = false; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = true; +#endif + + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres , 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2 , 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres , 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2 , 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) { + + if (((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) || + (!coex_sta->is_A2DP_3M)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 7); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 5); + } else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 6); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = true; + + if (wifi_turbo) + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + else + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 7); + + if (wifi_busy) { + + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 107); + else if (wifi_turbo) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 108); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 105); + } else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 106); + + } + +} + +void halbtc8821c2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres , 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2 , 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres , 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2 , 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 3); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 4); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = true; + + if (coex_sta->hid_busy_num >= 2) { + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + if (wifi_bw == 0) /* 11bg mode */ + halbtc8821c2ant_set_wltoggle_coex_table( + btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + else + halbtc8821c2ant_set_wltoggle_coex_table( + btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 110); + } else { + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 103); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 104); + } + + } + +} + +/* HID+A2DP+PAN(EDR) */ +void halbtc8821c2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = false; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres , 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2 , 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres , 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2 , 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = false; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) { + + if (((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) || + (!coex_sta->is_A2DP_3M)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 7); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 5); + } else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 6); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = true; + + if (coex_sta->hid_busy_num >= 2) { + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + + if (wifi_bw == 0) /* 11bg mode */ + halbtc8821c2ant_set_wltoggle_coex_table( + btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + else + halbtc8821c2ant_set_wltoggle_coex_table( + btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 110); + } else { + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + + if (wifi_busy) { + + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 107); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + true, 105); + } else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, + 106); + } + } + +} + +void halbtc8821c2ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) +{ + + /* fw all off */ + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8821C_2ANT_PHASE_5G_RUNTIME); +} + +void halbtc8821c2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* hw all off */ + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); +} +void halbtc8821c2ant_action_wifi_linkscan_process(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + if (bt_link_info->pan_exist) { + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + } else if (bt_link_info->a2dp_exist) { + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + } else { + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + } + +} + +void halbtc8821c2ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +{ + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + /* fw all off */ + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8821c2ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +{ + switch (coex_dm->cur_algorithm) { + + case BT_8821C_2ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_sco(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_hid(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_a2dp(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_a2dp_pan_hs(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_pan_edr(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_pan_edr_a2dp(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_pan_edr_hid(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_hid_a2dp_pan_edr( + btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_hid_a2dp(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_NOPROFILEBUSY: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_bt_idle(btcoexist); + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_coex_all_off(btcoexist); + break; + } + + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + +} + + +void halbtc8821c2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + u8 algorithm = 0; + u32 num_of_wifi_link = 0; + u32 wifi_link_status = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean miracast_plus_bt = false; + boolean scan = false, link = false, roam = false, + under_4way = false, + wifi_connected = false, wifi_under_5g = + false, + bt_hs_on = false; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (!coex_sta->run_time_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], return for run_time_state = false !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->freeze_coexrun_by_btinfo) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); + BTC_TRACE(trace_buf); + return; + } + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_under5g(btcoexist); + return; + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 2G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8821C_2ANT_PHASE_2G_RUNTIME); + } + + + if (coex_sta->bt_whck_test) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under WHCK TEST!!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_bt_whql_test(btcoexist); + return; + } + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled!!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_coex_all_off(btcoexist); + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_bt_inquiry(btcoexist); + return; + } + + if (coex_sta->is_setupLink) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is re-link !!!\n"); + halbtc8821c2ant_action_bt_relink(btcoexist); + return; + } + + /* for P2P */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", + num_of_wifi_link, wifi_link_status); + BTC_TRACE(trace_buf); + + if (bt_link_info->bt_link_exist) + miracast_plus_bt = true; + else + miracast_plus_bt = false; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_linkscan_process(btcoexist); + } else + halbtc8821c2ant_action_wifi_multi_port(btcoexist); + + return; + } else { + miracast_plus_bt = false; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + } + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is hs\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_bt_hs(btcoexist); + return; + } + + if ((BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) || + (BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, bt idle!!.\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_bt_idle(btcoexist); + return; + } + + algorithm = halbtc8821c2ant_action_algorithm(btcoexist); + coex_dm->cur_algorithm = algorithm; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", + coex_dm->cur_algorithm); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under Link Process !!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_wifi_linkscan_process(btcoexist); + } else if (wifi_connected) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, wifi connected!!.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_wifi_connected(btcoexist); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, wifi not-connected!!.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_wifi_not_connected(btcoexist); + } +} + +void halbtc8821c2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + /* fw all off */ + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_sta->pop_event_cnt = 0; + coex_sta->cnt_RemoteNameReq = 0; + coex_sta->cnt_ReInit = 0; + coex_sta->cnt_setupLink = 0; + coex_sta->cnt_IgnWlanAct = 0; + coex_sta->cnt_Page = 0; + coex_sta->cnt_RoleSwitch = 0; + + halbtc8821c2ant_query_bt_info(btcoexist); +} + + +void halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + u8 u8tmp = 0; + u32 vendor; + u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + u8 i; + + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp1 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + u32tmp3, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf);; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 2Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + coex_sta->isolation_btween_wb = BT_8821C_2ANT_DEFAULT_ISOLATION; + coex_sta->gnt_error_cnt = 0; + coex_sta->bt_relink_downcount = 0; + + for (i = 0; i <= 9; i++) + coex_sta->bt_afh_map[i] = 0; + + /* 0xf0[15:12] --> Chip Cut information */ + coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, + 0xf1) & 0xf0) >> 4; + + coex_sta->dis_ver_info_cnt = 0; + + halbtc8821c2ant_coex_switch_threshold(btcoexist, + coex_sta->isolation_btween_wb); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + + /* BT report packet sample rate */ + btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); + + /* Init 0x778 = 0x1 for 2-Ant */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + + /* Enable PTA (3-wire function form BT side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); + + /* Enable PTA (tx/rx signal form WiFi side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); + + /* set GNT_BT=1 for coex table select both */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1); + + halbtc8821c2ant_enable_gnt_to_gpio(btcoexist, true); + +#if 0 + /* check if WL firmware download ok */ + /*if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)*/ + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ONOFF, true); +#endif + + /* Enable counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, + 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ + + /* WLAN_Tx by GNT_WL 0x950[29] = 0 */ + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0); */ + + halbtc8821c2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); + + psd_scan->ant_det_is_ant_det_available = true; + + if (wifi_only) { + coex_sta->concurrent_rx_mode_on = false; + /* Path config */ + /* Set Antenna Path */ + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_WLANONLY_INIT); + + btcoexist->stop_coex_dm = true; + } else { + /*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); + + coex_sta->concurrent_rx_mode_on = true; + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */ + + /* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx, mask Tx only */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0); + + /* Set Antenna Path */ + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_COEX_INIT); + + btcoexist->stop_coex_dm = false; + } + + +} + + + +/* ************************************************************ + * work around function start with wa_halbtc8821c2ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8821c2ant_ + * ************************************************************ */ +void ex_halbtc8821c2ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x0; + u16 u16tmp = 0x0; + u32 value = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx Execute 8821c 2-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "Ant Det Finish = %s, Ant Det Number = %d\n", + (board_info->btdm_ant_det_finish ? "Yes" : "No"), + board_info->btdm_ant_num_by_ant_det); + BTC_TRACE(trace_buf); + + + btcoexist->stop_coex_dm = true; + psd_scan->ant_det_is_ant_det_available = false; + + /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */ + u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); + btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); + + + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + + /* Check efuse 0xc3[6] for Single Antenna Path */ + if (board_info->single_ant_path == 0) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Single Antenna, Antenna at Aux Port\n"); + BTC_TRACE(trace_buf); + + board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; + + u8tmp = 7; + } else if (board_info->single_ant_path == 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Single Antenna, Antenna at Main Port\n"); + BTC_TRACE(trace_buf); + + board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; + + u8tmp = 6; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d\n", + board_info->single_ant_path , board_info->btdm_ant_pos); + BTC_TRACE(trace_buf); + + /* Setup RF front end type */ + halbtc8821c2ant_set_rfe_type(btcoexist); + + /* Set Antenna Path to BT side */ + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_2ANT_PHASE_COEX_POWERON); + + /* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at power on */ + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_USB) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); + + /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ + halbtc8821c2ant_enable_gnt_to_gpio(btcoexist, true); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n", + halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38)); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcb4 (Power-On) = 0x%x / 0x%x\n", + btcoexist->btc_read_4byte(btcoexist, 0x70), + btcoexist->btc_read_4byte(btcoexist, 0xcb4)); + BTC_TRACE(trace_buf); + +} + +void ex_halbtc8821c2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ + + /* */ + /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + if (btcoexist->chip_interface == BTC_INTF_USB) { + /* fixed at S0 for USB interface */ + u8tmp |= 0x1; /* antenna inverse */ + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + } else { + /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ + if (board_info->single_ant_path == 0) { + } else if (board_info->single_ant_path == 1) { + /* set to S0 */ + u8tmp |= 0x1; /* antenna inverse */ + } + + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, + u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, + u8tmp); + } +} + + +void ex_halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8821c2ant_init_hw_config(btcoexist, wifi_only); +} + +void ex_halbtc8821c2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + + halbtc8821c2ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, ps_tdma_case = 0; + u32 u32tmp[4]; + u16 u16tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + static u8 pop_report_in_10s = 0; + u32 phyver = 0; + boolean lte_coex_on = false; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + if (psd_scan->ant_det_try_count == 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s / %d", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, board_info->btdm_ant_num, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type); + CL_PRINTF(cli_buf); + } else { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", + "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", + board_info->pg_ant_num, + board_info->btdm_ant_num_by_ant_det, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type, + psd_scan->ant_det_try_count, + psd_scan->ant_det_fail_count, + psd_scan->ant_det_result); + CL_PRINTF(cli_buf); + + + if (board_info->btdm_ant_det_finish) { + + if (psd_scan->ant_det_result != 12) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", + "Ant Det PSD Value", + psd_scan->ant_det_peak_val); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d", + "Ant Det PSD Value", + psd_scan->ant_det_psd_scan_peak_val + / 100); + CL_PRINTF(cli_buf); + } + } + + + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + + bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8821c_2ant, glcoex_ver_8821c_2ant, + glcoex_ver_btdesired_8821c_2ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8821c_2ant ? + "Match" : "Mis-Match")))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "AFH Map to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ", + "Isolation/WL_Thres/BT_Thres", + coex_sta->isolation_btween_wb, + coex_sta->wifi_coex_thres, + coex_sta->bt_coex_thres); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + pop_report_in_10s++; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", + "BT [status/ rssi/ retryCnt/ popCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + : ((BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, + coex_sta->pop_event_cnt); + CL_PRINTF(cli_buf); + + if (pop_report_in_10s >= 5) { + coex_sta->pop_event_cnt = 0; + pop_report_in_10s = 0; + } + + + if (coex_sta->num_of_profile != 0) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s%s%s%s%s", + "Profiles", + ((bt_link_info->a2dp_exist) ? "A2DP," : ""), + ((bt_link_info->sco_exist) ? "HFP," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : + "HID(2/18),") : ""), + ((bt_link_info->pan_exist) ? "PAN," : ""), + ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = None", "Profiles"); + + CL_PRINTF(cli_buf); + + + if (bt_link_info->a2dp_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", + "A2DP Rate/Bitpool/Auto_Slot", + ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), + coex_sta->a2dp_bit_pool, + ((coex_sta->is_autoslot) ? "On" : "Off") + ); + CL_PRINTF(cli_buf); + } + + if (bt_link_info->hid_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "HID PairNum/Forbid_Slot", + coex_sta->hid_pair_cnt, + coex_sta->forbidden_slot + ); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x", + "Role/RoleSwCnt/IgnWlact/Feature", + ((bt_link_info->slave_role) ? "Slave" : "Master"), + coex_sta->cnt_RoleSwitch, + ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), + coex_sta->bt_coex_supported_feature); + CL_PRINTF(cli_buf); + + if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "BLEScan Type/TV/Init/Ble", + coex_sta->bt_ble_scan_type, + (coex_sta->bt_ble_scan_type & 0x1 ? + coex_sta->bt_ble_scan_para[0] : 0x0), + (coex_sta->bt_ble_scan_type & 0x2 ? + coex_sta->bt_ble_scan_para[1] : 0x0), + (coex_sta->bt_ble_scan_type & 0x4 ? + coex_sta->bt_ble_scan_para[2] : 0x0)); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "ReInit/ReLink/IgnWlact/Page/NameReq", + coex_sta->cnt_ReInit, + coex_sta->cnt_setupLink, + coex_sta->cnt_IgnWlanAct, + coex_sta->cnt_Page, + coex_sta->cnt_RemoteNameReq + ); + CL_PRINTF(cli_buf); + + halbtc8821c2ant_read_score_board(btcoexist, &u16tmp[0]); + + if ((coex_sta->bt_reg_vendor_ae == 0xffff) || + (coex_sta->bt_reg_vendor_ac == 0xffff)) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", + ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), + coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); + CL_PRINTF(cli_buf); + + if (coex_sta->num_of_profile > 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + "AFH MAP", + coex_sta->bt_afh_map[0], + coex_sta->bt_afh_map[1], + coex_sta->bt_afh_map[2], + coex_sta->bt_afh_map[3], + coex_sta->bt_afh_map[4], + coex_sta->bt_afh_map[5], + coex_sta->bt_afh_map[6], + coex_sta->bt_afh_map[7], + coex_sta->bt_afh_map[8], + coex_sta->bt_afh_map[9] + ); + CL_PRINTF(cli_buf); + } + + for (i = 0; i < BT_INFO_SRC_8821C_2ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8821c_2ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + /* Sw mechanism */ + if (btcoexist->manual_control) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanism] (before Manual)============"); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Mechanism]============"); + + CL_PRINTF(cli_buf); + + + ps_tdma_case = coex_dm->cur_ps_tdma; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, %s)", + "TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"), + (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant")); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", + "Table/0x6c0/0x6c4/0x6c8", + coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x", + "0x778/0x6cc", + u8tmp[0], u32tmp[0]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", + "AntDiv/ForceLPS/LPRA", + ((board_info->ant_div_cfg) ? "On" : "Off"), + ((coex_sta->force_lps_on) ? "On" : "Off"), + ((coex_dm->cur_low_penalty_ra) ? "On" : "Off")); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "WL_DACSwing/ BT_Dec_Pwr", coex_dm->cur_fw_dac_swing_lvl, + coex_dm->cur_bt_dec_pwr_lvl); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? true : false; + + if (lte_coex_on) { + + u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0xa0); + u32tmp[1] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0xa4); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "LTE Coex Table W_L/B_L", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + CL_PRINTF(cli_buf); + + + u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0xa8); + u32tmp[1] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0xac); + u32tmp[2] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0xb0); + u32tmp[3] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0xb4); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "LTE Break Table W_L/B_L/L_W/L_B", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, + u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); + CL_PRINTF(cli_buf); + + } + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp[1] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", + "LTE Coex/Path Owner", + ((lte_coex_on) ? "On" : "Off") , + ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); + CL_PRINTF(cli_buf); + + if (lte_coex_on) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %d/ %d", + "LTE 3Wire/OPMode/UART/UARTMode", + (int)((u32tmp[0] & BIT(6)) >> 6), + (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), + (int)((u32tmp[0] & BIT(3)) >> 3), + (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "LTE_Busy/UART_Busy", + (int)((u32tmp[1] & BIT(1)) >> 1), + (int)(u32tmp[1] & BIT(0))); + CL_PRINTF(cli_buf); + } + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", + ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), + ((u8tmp[0] & BIT(3)) ? "On" : "Off"), + coex_sta->gnt_error_cnt); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "GNT_WL/GNT_BT", + (int)((u32tmp[1] & BIT(2)) >> 2), + (int)((u32tmp[1] & BIT(3)) >> 3)); + CL_PRINTF(cli_buf); + + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s", + "0xcb0/0xcb4/0xcb8[23:16]", + u32tmp[0], u32tmp[1], u8tmp[0], + ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "4c[24:23]/64[0]/4c6[4]/40[5]", + (u32tmp[0] & (BIT(24) | BIT(23))) >> 23 , u8tmp[2] & 0x1 , + (int)((u8tmp[0] & BIT(4)) >> 4), + (int)((u8tmp[1] & BIT(5)) >> 5)); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x", + "0x550/0x522/4-RxAGC/0xc50", + u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_CCK); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); + CL_PRINTF(cli_buf); + +#if 1 + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11ac", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_Err CCK/11g/11n/11ac", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); + CL_PRINTF(cli_buf); +#endif + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "WlHiPri/ Locking/ Locked/ Noisy", + (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + (coex_sta->cck_lock ? "Yes" : "No"), + (coex_sta->cck_ever_lock ? "Yes" : "No"), + coex_sta->wl_noisy_level); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx, + (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : + "")); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : ( + coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); + CL_PRINTF(cli_buf); + + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +void ex_halbtc8821c2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = true; + coex_sta->under_lps = false; + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_ONOFF | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, + false); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_WLAN_OFF); + + halbtc8821c2ant_action_coex_all_off(btcoexist); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = false; +#if 0 + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE, true); + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ONOFF, true); +#endif + + halbtc8821c2ant_init_hw_config(btcoexist, false); + halbtc8821c2ant_init_coex_dm(btcoexist); + halbtc8821c2ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8821c2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = true; + coex_sta->under_ips = false; + + if (coex_sta->force_lps_on == true) { /* LPS No-32K */ + /* Write WL "Active" in Score-board for PS-TDMA */ + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE, true); + + } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ + /* Write WL "Non-Active" in Score-board for Native-PS */ + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE, false); + } + + + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = false; + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE, true); + } +} + +void ex_halbtc8821c2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = false; + boolean wifi_under_5g = false; + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN notify()\n"); + BTC_TRACE(trace_buf); + + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* this can't be removed for RF off_on event, or BT would dis-connect */ + halbtc8821c2ant_query_bt_info(btcoexist); + + if (BTC_SCAN_START == type) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, + &wifi_under_5g); + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_ONOFF, + true); + + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** SCAN START notify (5g)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_under5g(btcoexist); + return; + } + + coex_sta->wifi_is_high_pri_task = true; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** SCAN START notify (2g)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_2G_RUNTIME); + + halbtc8821c2ant_run_coexist_mechanism( + btcoexist); + + return; + } + + + if (BTC_SCAN_START_2G == type) { + + if (!wifi_connected) + coex_sta->wifi_is_high_pri_task = true; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_ONOFF, + true); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_2G_RUNTIME); + + halbtc8821c2ant_run_coexist_mechanism(btcoexist); + + } else if (BTC_SCAN_FINISH == type) { + + coex_sta->wifi_is_high_pri_task = false; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", + coex_sta->scan_ap_num); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_run_coexist_mechanism(btcoexist); + } + +} + +void ex_halbtc8821c2ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + + boolean wifi_connected = false, bt_hs_on = false; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = false; + u8 agg_buf_size = 5; + + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + if (type == BTC_SWITCH_TO_5G) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], switchband_notify --- switch to 5G\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_under5g(btcoexist); + + } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** switchband_notify BTC_SWITCH_TO_2G (no for scan)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_run_coexist_mechanism(btcoexist); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], switchband_notify --- switch to 2G\n"); + BTC_TRACE(trace_buf); + + ex_halbtc8821c2ant_scan_notify(btcoexist, + BTC_SCAN_START_2G); + } +} + + +void ex_halbtc8821c2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_ONOFF, + true); + + if ((BTC_ASSOCIATE_5G_START == type) || + (BTC_ASSOCIATE_5G_FINISH == type)) { + + if (BTC_ASSOCIATE_5G_START == type) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], connect_notify --- 5G start\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], connect_notify --- 5G finish\n"); + + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_under5g(btcoexist); + return; + } + + + if (BTC_ASSOCIATE_START == type) { + + coex_sta->wifi_is_high_pri_task = true; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_2G_RUNTIME); + + halbtc8821c2ant_run_coexist_mechanism(btcoexist); + + /* To keep TDMA case during connect process, + to avoid changed by Btinfo and runcoexmechanism */ + coex_sta->freeze_coexrun_by_btinfo = true; + + coex_dm->arp_cnt = 0; + + } else if (BTC_ASSOCIATE_FINISH == type) { + + coex_sta->wifi_is_high_pri_task = false; + coex_sta->freeze_coexrun_by_btinfo = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_run_coexist_mechanism(btcoexist); + } +} + +void ex_halbtc8821c2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + u8 ap_num = 0; + boolean wifi_under_b_mode = false, wifi_under_5g = false; + + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (BTC_MEDIA_CONNECT == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_ONOFF, + true); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_under5g(btcoexist); + return; + } + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_2G_RUNTIME); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x00); /* CCK Rx */ + } else { + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x10); /* CCK Rx */ + } + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE, false); + } + + + halbtc8821c2ant_update_wifi_channel_info(btcoexist, type); +} + +void ex_halbtc8821c2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean under_4way = false, wifi_under_5g = false; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_under5g(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (under_4way) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ---- under_4way!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = true; + coex_sta->specific_pkt_period_cnt = 2; + + } else if (BTC_PACKET_ARP == type) { + + coex_dm->arp_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ARP notify -cnt = %d\n", + coex_dm->arp_cnt); + BTC_TRACE(trace_buf); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", + type); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = true; + coex_sta->specific_pkt_period_cnt = 2; + } + + if (coex_sta->wifi_is_high_pri_task) { + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_SCAN, true); + halbtc8821c2ant_run_coexist_mechanism(btcoexist); + } + +} + +void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 i, rsp_source = 0; + boolean wifi_connected = false; + boolean wifi_scan = false, wifi_link = false, wifi_roam = false, + wifi_busy = false; + static boolean is_scoreboard_scan = false; + + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8821C_2ANT_MAX) + rsp_source = BT_INFO_SRC_8821C_2ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; + coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; + coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; + + if (BT_INFO_SRC_8821C_2ANT_WIFI_FW != rsp_source) { + + /* if 0xff, it means BT is under WHCK test */ + coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true : + false); + + coex_sta->bt_create_connection = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true : + false); + + /* unit: %, value-100 to translate to unit: dBm */ + coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + + 10; + + coex_sta->c2h_bt_remote_name_req = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true : + false); + + coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & + 0x10) ? true : false); + + coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & + 0x9) ? true : false); + + coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? + true : false); + + coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & + BT_INFO_8821C_2ANT_B_INQ_PAGE) ? true : false); + + coex_sta->a2dp_bit_pool = ((( + coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? + coex_sta->bt_info_c2h[rsp_source][6] : 0); + + coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & + 0xf; + + coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; + + coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; + + coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; + + coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; + + if (coex_sta->bt_retry_cnt >= 1) + coex_sta->pop_event_cnt++; + + if (coex_sta->c2h_bt_remote_name_req) + coex_sta->cnt_RemoteNameReq++; + + if (coex_sta->bt_info_ext & BIT(1)) + coex_sta->cnt_ReInit++; + + + if (coex_sta->bt_info_ext & BIT(2)) { + coex_sta->cnt_setupLink++; + coex_sta->is_setupLink = true; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link start in BT info!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_sta->is_setupLink = false; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link stop in BT info!!\n"); + BTC_TRACE(trace_buf); + } + + + if (coex_sta->bt_info_ext & BIT(3)) + coex_sta->cnt_IgnWlanAct++; + + if (coex_sta->bt_info_ext & BIT(6)) + coex_sta->cnt_RoleSwitch++; + + if (coex_sta->bt_create_connection) { + coex_sta->cnt_Page++; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, + &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || + (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { + + is_scoreboard_scan = true; + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_SCAN, true); + + } else + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_SCAN, false); + + } else { + if (is_scoreboard_scan) { + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_SCAN, false); + is_scoreboard_scan = false; + } + } + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + + if ((!btcoexist->manual_control) && + (!btcoexist->stop_coex_dm)) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* Re-Init */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + if (wifi_connected) + halbtc8821c2ant_update_wifi_channel_info( + btcoexist, BTC_MEDIA_CONNECT); + else + halbtc8821c2ant_update_wifi_channel_info( + btcoexist, + BTC_MEDIA_DISCONNECT); + } + + + /* If Ignore_WLanAct && not SetUp_Link */ + if ((coex_sta->bt_info_ext & BIT(3)) && + (!(coex_sta->bt_info_ext & BIT(2))) && + (!(coex_sta->bt_info_ext & BIT(6)))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, false); + } else { + if (coex_sta->bt_info_ext & BIT(2)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ignore Wlan active because Re-link!!\n"); + BTC_TRACE(trace_buf); + } else if (coex_sta->bt_info_ext & BIT(6)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ignore Wlan active because Role-Switch!!\n"); + BTC_TRACE(trace_buf); + } + } + } + + } + + if ((coex_sta->bt_info_ext & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + BTC_TRACE(trace_buf); + coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( + btcoexist); + + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x4); + } + + halbtc8821c2ant_update_bt_link_info(btcoexist); + + halbtc8821c2ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8821c2ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_RF_ON == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned ON!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = false; +#if 0 + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE, true); + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ONOFF, true); +#endif + } else if (BTC_RF_OFF == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned OFF!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_WLAN_OFF); + + halbtc8821c2ant_action_coex_all_off(btcoexist); + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_ONOFF | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, + false); + + btcoexist->stop_coex_dm = true; + + } +} + +void ex_halbtc8821c2ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_2ANT_PHASE_WLAN_OFF); + + ex_halbtc8821c2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_ONOFF | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, + false); +} + +void ex_halbtc8821c2ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + boolean wifi_under_5g = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((BTC_WIFI_PNP_SLEEP == pnp_state) || + (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + + /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ + /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ + /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ + coex_sta->under_ips = false; + coex_sta->under_lps = false; + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_ONOFF | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, + false); + + if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { + + if (wifi_under_5g) + halbtc8821c2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_2ANT_PHASE_5G_RUNTIME); + else + halbtc8821c2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_2ANT_PHASE_2G_RUNTIME); + } else { + + halbtc8821c2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_WLAN_OFF); + } + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE, true); + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ONOFF, true); +#endif + } +} + +void ex_halbtc8821c2ant_periodical(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + boolean wifi_busy = false; + u32 bt_patch_ver; + static u8 cnt = 0; + boolean bt_relink_finish = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ************* Periodical *************\n"); + BTC_TRACE(trace_buf); + +#if (BT_AUTO_REPORT_ONLY_8821C_2ANT == 0) + halbtc8821c2ant_query_bt_info(btcoexist); +#endif + + halbtc8821c2ant_monitor_bt_ctr(btcoexist); + halbtc8821c2ant_monitor_wifi_ctr(btcoexist); + halbtc8821c2ant_monitor_bt_enable_disable(btcoexist); + +#if 0 + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + /* halbtc8821c2ant_read_score_board(btcoexist, &bt_scoreboard_val); */ + + if (wifi_busy) { + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, true); + /* + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_WLBUSY, true); + + if (bt_scoreboard_val & BIT(6)) + halbtc8821c2ant_query_bt_info(btcoexist); */ + } else { + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, false); + /* + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_WLBUSY, + false); */ + } +#endif + + if (coex_sta->bt_relink_downcount != 0) { + coex_sta->bt_relink_downcount--; + + if (coex_sta->bt_relink_downcount == 0) + bt_relink_finish = true; + } + + /* for 4-way, DHCP, EAPOL packet */ + if (coex_sta->specific_pkt_period_cnt > 0) { + + coex_sta->specific_pkt_period_cnt--; + + if ((coex_sta->specific_pkt_period_cnt == 0) && + (coex_sta->wifi_is_high_pri_task)) + coex_sta->wifi_is_high_pri_task = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ***************** Hi-Pri Task = %s\n", + (coex_sta->wifi_is_high_pri_task ? "Yes" : + "No")); + BTC_TRACE(trace_buf); + + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->bt_coex_supported_feature == 0) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + if (coex_sta->bt_reg_vendor_ac == 0xffff) + coex_sta->bt_reg_vendor_ac = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xac) & 0xffff); + + if (coex_sta->bt_reg_vendor_ae == 0xffff) + coex_sta->bt_reg_vendor_ae = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xae) & 0xffff); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, + &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) { + cnt++; + + if (cnt >= 3) { + btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, + &coex_sta->bt_afh_map[0]); + cnt = 0; + } + } + } + + if (halbtc8821c2ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish)) + halbtc8821c2ant_run_coexist_mechanism(btcoexist); +} + + +/*#pragma optimize( "", off )*/ +void ex_halbtc8821c2ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + +} + + +void ex_halbtc8821c2ant_display_ant_detection(IN struct btc_coexist *btcoexist) +{ + +} + + +#endif + +#endif /* #if (RTL8821C_SUPPORT == 1) */ + + diff --git a/hal/btc/halbtc8821c2ant.h b/hal/btc/halbtc8821c2ant.h new file mode 100644 index 0000000..ae42803 --- /dev/null +++ b/hal/btc/halbtc8821c2ant.h @@ -0,0 +1,504 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8821C_SUPPORT == 1) + +/* ******************************************* + * The following is for 8821C 2Ant BT Co-exist definition + * ******************************************* */ +#define BT_8821C_2ANT_COEX_DBG 0 +#define BT_AUTO_REPORT_ONLY_8821C_2ANT 1 + + +#define BT_INFO_8821C_2ANT_B_FTP BIT(7) +#define BT_INFO_8821C_2ANT_B_A2DP BIT(6) +#define BT_INFO_8821C_2ANT_B_HID BIT(5) +#define BT_INFO_8821C_2ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8821C_2ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8821C_2ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8821C_2ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8821C_2ANT_B_CONNECTION BIT(0) + +#define BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT 2 + + +#define BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 80 /* unit: % WiFi RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation, default = 42 */ +#define BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 80 /* unit: % BT RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation, default = 46 */ +#define BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 80 /* unit: % WiFi RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation, default = 42 */ +#define BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES2 80 /* unit: % BT RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation, default = 46 */ +#define BT_8821C_2ANT_DEFAULT_ISOLATION 15 /* unit: dB */ +#define BT_8821C_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */ +#define BT_8821C_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */ +#define BT_8821C_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */ +#define BT_8821C_2ANT_WIFI_SIR_THRES2 -30 /* unit: dB */ +#define BT_8821C_2ANT_BT_SIR_THRES1 -15 /* unit: dB */ +#define BT_8821C_2ANT_BT_SIR_THRES2 -30 /* unit: dB */ + + +/* for Antenna detection */ +#define BT_8821C_2ANT_ANTDET_PSDTHRES_BACKGROUND 50 +#define BT_8821C_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 +#define BT_8821C_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 52 +#define BT_8821C_2ANT_ANTDET_PSDTHRES_1ANT 40 +#define BT_8821C_2ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ +#define BT_8821C_2ANT_ANTDET_SWEEPPOINT_DELAY 60000 +#define BT_8821C_2ANT_ANTDET_ENABLE 0 +#define BT_8821C_2ANT_ANTDET_BTTXTIME 100 +#define BT_8821C_2ANT_ANTDET_BTTXCHANNEL 39 +#define BT_8821C_2ANT_ANTDET_PSD_SWWEEPCOUNT 50 + + +#define BT_8821C_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 + +enum bt_8821c_2ant_signal_state { + BT_8821C_2ANT_SIG_STA_SET_TO_LOW = 0x0, + BT_8821C_2ANT_SIG_STA_SET_BY_HW = 0x0, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH = 0x1, + BT_8821C_2ANT_SIG_STA_MAX +}; + +enum bt_8821c_2ant_path_ctrl_owner { + BT_8821C_2ANT_PCO_BTSIDE = 0x0, + BT_8821C_2ANT_PCO_WLSIDE = 0x1, + BT_8821C_2ANT_PCO_MAX +}; + +enum bt_8821c_2ant_gnt_ctrl_type { + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW = 0x1, + BT_8821C_2ANT_GNT_TYPE_MAX +}; + +enum bt_8821c_2ant_gnt_ctrl_block { + BT_8821C_2ANT_GNT_BLOCK_RFC_BB = 0x0, + BT_8821C_2ANT_GNT_BLOCK_RFC = 0x1, + BT_8821C_2ANT_GNT_BLOCK_BB = 0x2, + BT_8821C_2ANT_GNT_BLOCK_MAX +}; + +enum bt_8821c_2ant_lte_coex_table_type { + BT_8821C_2ANT_CTT_WL_VS_LTE = 0x0, + BT_8821C_2ANT_CTT_BT_VS_LTE = 0x1, + BT_8821C_2ANT_CTT_MAX +}; + +enum bt_8821c_2ant_lte_break_table_type { + BT_8821C_2ANT_LBTT_WL_BREAK_LTE = 0x0, + BT_8821C_2ANT_LBTT_BT_BREAK_LTE = 0x1, + BT_8821C_2ANT_LBTT_LTE_BREAK_WL = 0x2, + BT_8821C_2ANT_LBTT_LTE_BREAK_BT = 0x3, + BT_8821C_2ANT_LBTT_MAX +}; + +enum bt_info_src_8821c_2ant { + BT_INFO_SRC_8821C_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8821C_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8821C_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8821C_2ANT_MAX +}; + +enum bt_8821c_2ant_bt_status { + BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8821C_2ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8821C_2ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8821C_2ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8821C_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8821C_2ANT_BT_STATUS_MAX +}; + +enum bt_8821c_2ant_coex_algo { + BT_8821C_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8821C_2ANT_COEX_ALGO_SCO = 0x1, + BT_8821C_2ANT_COEX_ALGO_HID = 0x2, + BT_8821C_2ANT_COEX_ALGO_A2DP = 0x3, + BT_8821C_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8821C_2ANT_COEX_ALGO_PANEDR = 0x5, + BT_8821C_2ANT_COEX_ALGO_PANHS = 0x6, + BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8821C_2ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8821C_2ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8821C_2ANT_COEX_ALGO_NOPROFILEBUSY = 0xb, + BT_8821C_2ANT_COEX_ALGO_MAX +}; + +enum bt_8821c_2ant_ext_ant_switch_type { + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0, + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1, + BT_8821C_2ANT_EXT_ANT_SWITCH_NONE = 0x2, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAX +}; + +enum bt_8821c_2ant_ext_ant_switch_ctrl_type { + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_MAX +}; + +enum bt_8821c_2ant_ext_ant_switch_pos_type { + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT = 0x0, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG = 0x1, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA = 0x2, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE = 0x3, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_MAX +}; + +enum bt_8821c_2ant_ext_band_switch_pos_type { + BT_8821C_2ANT_EXT_BAND_SWITCH_TO_WLG = 0x0, + BT_8821C_2ANT_EXT_BAND_SWITCH_TO_WLA = 0x1, + BT_8821C_2ANT_EXT_BAND_SWITCH_TO_MAX +}; + +enum bt_8821c_2ant_int_block { + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_MAX +}; + +enum bt_8821c_2ant_phase { + BT_8821C_2ANT_PHASE_COEX_INIT = 0x0, + BT_8821C_2ANT_PHASE_WLANONLY_INIT = 0x1, + BT_8821C_2ANT_PHASE_WLAN_OFF = 0x2, + BT_8821C_2ANT_PHASE_2G_RUNTIME = 0x3, + BT_8821C_2ANT_PHASE_5G_RUNTIME = 0x4, + BT_8821C_2ANT_PHASE_BTMPMODE = 0x5, + BT_8821C_2ANT_PHASE_ANTENNA_DET = 0x6, + BT_8821C_2ANT_PHASE_COEX_POWERON = 0x7, + BT_8821C_2ANT_PHASE_2G_RUNTIME_CONCURRENT = 0x8, + BT_8821C_2ANT_PHASE_MAX +}; + +enum bt_8821c_2ant_Scoreboard { + BT_8821C_2ANT_SCOREBOARD_ACTIVE = BIT(0), + BT_8821C_2ANT_SCOREBOARD_ONOFF = BIT(1), + BT_8821C_2ANT_SCOREBOARD_SCAN = BIT(2), + BT_8821C_2ANT_SCOREBOARD_UNDERTEST = BIT(3), + BT_8821C_2ANT_SCOREBOARD_WLBUSY = BIT(6) +}; + + + +struct coex_dm_8821c_2ant { + /* hw setting */ + u32 pre_ant_pos_type; + u32 cur_ant_pos_type; + /* fw mechanism */ + u8 pre_bt_dec_pwr_lvl; + u8 cur_bt_dec_pwr_lvl; + u8 pre_fw_dac_swing_lvl; + u8 cur_fw_dac_swing_lvl; + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean reset_tdma_adjust; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + + /* sw mechanism */ + boolean pre_rf_rx_lpf_shrink; + boolean cur_rf_rx_lpf_shrink; + u32 bt_rf_0x1e_backup; + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + boolean pre_dac_swing_on; + u32 pre_dac_swing_lvl; + boolean cur_dac_swing_on; + u32 cur_dac_swing_lvl; + boolean pre_adc_back_off; + boolean cur_adc_back_off; + boolean pre_agc_table_en; + boolean cur_agc_table_en; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + boolean need_recover0x948; + u32 backup0x948; + + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + boolean is_switch_to_1dot5_ant; + u8 switch_thres_offset; + u32 arp_cnt; + + u32 pre_ext_ant_switch_status; + u32 cur_ext_ant_switch_status; + + u8 pre_ext_band_switch_status; + u8 cur_ext_band_switch_status; + + u8 pre_int_block_status; + u8 cur_int_block_status; +}; + +struct coex_sta_8821c_2ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + + boolean under_lps; + boolean under_ips; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + boolean is_hiPri_rx_overhead; + u8 bt_rssi; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + u8 bt_info_c2h[BT_INFO_SRC_8821C_2ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8821C_2ANT_MAX]; + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; + + u8 bt_info_ext; + u8 bt_info_ext2; + u32 pop_event_cnt; + u8 scan_ap_num; + u8 bt_retry_cnt; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + + boolean cck_lock; + boolean pre_ccklock; + boolean cck_ever_lock; + + u8 coex_table_type; + boolean force_lps_on; + + u8 dis_ver_info_cnt; + + u8 a2dp_bit_pool; + u8 cut_version; + + boolean concurrent_rx_mode_on; + + u16 score_board; + u8 isolation_btween_wb; /* 0~ 50 */ + u8 wifi_coex_thres; + u8 bt_coex_thres; + u8 wifi_coex_thres2; + u8 bt_coex_thres2; + + u8 num_of_profile; + boolean acl_busy; + boolean bt_create_connection; + boolean wifi_is_high_pri_task; + u32 specific_pkt_period_cnt; + u32 bt_coex_supported_feature; + u32 bt_coex_supported_version; + + u8 bt_ble_scan_type; + u32 bt_ble_scan_para[3]; + + boolean run_time_state; + boolean freeze_coexrun_by_btinfo; + + boolean is_A2DP_3M; + boolean voice_over_HOGP; + u8 bt_info; + boolean is_autoslot; + u8 forbidden_slot; + u8 hid_busy_num; + u8 hid_pair_cnt; + + u32 cnt_RemoteNameReq; + u32 cnt_setupLink; + u32 cnt_ReInit; + u32 cnt_IgnWlanAct; + u32 cnt_Page; + u32 cnt_RoleSwitch; + + u16 bt_reg_vendor_ac; + u16 bt_reg_vendor_ae; + + boolean is_setupLink; + u8 wl_noisy_level; + u32 gnt_error_cnt; + + u8 bt_afh_map[10]; + u8 bt_relink_downcount; + boolean is_tdma_btautoslot; + boolean is_tdma_btautoslot_hang; +}; + + +#define BT_8821C_2ANT_EXT_BAND_SWITCH_USE_DPDT 0 +#define BT_8821C_2ANT_EXT_BAND_SWITCH_USE_SPDT 1 + + +struct rfe_type_8821c_2ant { + + u8 rfe_module_type; + boolean ext_ant_switch_exist; + u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */ + u8 ext_ant_switch_ctrl_polarity; /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ + + boolean ext_band_switch_exist; + u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */ + u8 ext_band_switch_ctrl_polarity; + + boolean ant_at_main_port; + + boolean wlg_Locate_at_btg; /* If true: WLG at BTG, If false: WLG at WLAG */ + + boolean ext_ant_switch_diversity; /* If diversity on */ +}; + +#define BT_8821C_2ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ +#define BT_8821C_2ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ +#define BT_8821C_2ANT_ANTDET_BUF_LEN 16 + +struct psdscan_sta_8821c_2ant { + + u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ + u32 ant_det_bt_tx_time; + u32 ant_det_pre_psdscan_peak_val; + boolean ant_det_is_ant_det_available; + u32 ant_det_psd_scan_peak_val; + boolean ant_det_is_btreply_available; + u32 ant_det_psd_scan_peak_freq; + + u8 ant_det_result; + u8 ant_det_peak_val[BT_8821C_2ANT_ANTDET_BUF_LEN]; + u8 ant_det_peak_freq[BT_8821C_2ANT_ANTDET_BUF_LEN]; + u32 ant_det_try_count; + u32 ant_det_fail_count; + u32 ant_det_inteval_count; + u32 ant_det_thres_offset; + + u32 real_cent_freq; + s32 real_offset; + u32 real_span; + + u32 psd_band_width; /* unit: Hz */ + u32 psd_point; /* 128/256/512/1024 */ + u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_start_point; + u32 psd_stop_point; + u32 psd_max_value_point; + u32 psd_max_value; + u32 psd_max_value2; + u32 psd_avg_value; /* filter loop_max_value that below BT_8821C_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/ + u32 psd_loop_max_value[BT_8821C_2ANT_ANTDET_PSD_SWWEEPCOUNT]; /*max value in each loop */ + u32 psd_start_base; + u32 psd_avg_num; /* 1/8/16/32 */ + u32 psd_gen_count; + boolean is_AntDet_running; + boolean is_psd_show_max_only; +}; + + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8821c2ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c2ant_pre_load_firmware(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8821c2ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c2ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8821c2ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c2ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8821c2ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c2ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); +void ex_halbtc8821c2ant_display_ant_detection(IN struct btc_coexist *btcoexist); + + +#else +#define ex_halbtc8821c2ant_power_on_setting(btcoexist) +#define ex_halbtc8821c2ant_pre_load_firmware(btcoexist) +#define ex_halbtc8821c2ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8821c2ant_init_coex_dm(btcoexist) +#define ex_halbtc8821c2ant_ips_notify(btcoexist, type) +#define ex_halbtc8821c2ant_lps_notify(btcoexist, type) +#define ex_halbtc8821c2ant_scan_notify(btcoexist, type) +#define ex_halbtc8821c2ant_switchband_notify(btcoexist,type) +#define ex_halbtc8821c2ant_connect_notify(btcoexist, type) +#define ex_halbtc8821c2ant_media_status_notify(btcoexist, type) +#define ex_halbtc8821c2ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8821c2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8821c2ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8821c2ant_halt_notify(btcoexist) +#define ex_halbtc8821c2ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8821c2ant_periodical(btcoexist) +#define ex_halbtc8821c2ant_display_coex_info(btcoexist) +#define ex_halbtc8821c2ant_display_ant_detection(btcoexist) +#define ex_halbtc8821c2ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) +#endif + +#endif + + diff --git a/hal/btc/halbtc8821cwifionly.c b/hal/btc/halbtc8821cwifionly.c new file mode 100644 index 0000000..ffa32ed --- /dev/null +++ b/hal/btc/halbtc8821cwifionly.c @@ -0,0 +1,200 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "mp_precomp.h" + +static struct rfe_type_8821c_wifi_only gl_rfe_type_8821c_1ant; +static struct rfe_type_8821c_wifi_only *rfe_type = &gl_rfe_type_8821c_1ant; + + + +VOID hal8821c_wifi_only_switch_antenna( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ) +{ + boolean switch_polatiry_inverse = false; + u8 regval_0xcb7 = 0; + u8 pos_type, ctrl_type; + + if (!rfe_type->ext_ant_switch_exist) + return; + + /* swap control polarity if use different switch control polarity*/ + /* Normal switch polarity for DPDT, 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main */ + /* Normal switch polarity for SPDT, 0xcb4[29:28] = 2b'01 => Ant to BTG, 0xcb4[29:28] = 2b'10 => Ant to WLG */ + if (rfe_type->ext_ant_switch_ctrl_polarity) + switch_polatiry_inverse = !switch_polatiry_inverse; + + /* swap control polarity if 1-Ant at Aux */ + if (rfe_type->ant_at_main_port == false) + switch_polatiry_inverse = !switch_polatiry_inverse; + + if (is_5g) + pos_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLA; + else + pos_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLG; + + switch (pos_type) { + default: + case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLA: + + break; + case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLG: + if (!rfe_type->wlg_Locate_at_btg) + switch_polatiry_inverse = !switch_polatiry_inverse; + break; + } + + if (pwifionlycfg->haldata_info.ant_div_cfg) + ctrl_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; + else + ctrl_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BBSW; + + + switch (ctrl_type) { + default: + case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BBSW: + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2); + + /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0x000000ff, 0x77); + + regval_0xcb7 = (switch_polatiry_inverse == false ? 0x1 : 0x2); + + /* 0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0x30000000, regval_0xcb7); + break; + + case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2); + + /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0x000000ff, 0x88); + + /* no regval_0xcb7 setup required, because antenna switch control value by antenna diversity */ + + break; + + } + +} + + +VOID halbtc8821c_wifi_only_set_rfe_type( + IN struct wifi_only_cfg *pwifionlycfg + ) +{ + + /* the following setup should be got from Efuse in the future */ + rfe_type->rfe_module_type = (pwifionlycfg->haldata_info.rfe_type) & 0x1f; + + rfe_type->ext_ant_switch_ctrl_polarity = 0; + + switch (rfe_type->rfe_module_type) { + case 0: + default: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT; /*2-Ant, DPDT, WLG*/ + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 1: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, WLG */ + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 2: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, BTG */ + rfe_type->wlg_Locate_at_btg = true; + rfe_type->ant_at_main_port = true; + break; + case 3: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, WLG */ + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = false; + break; + case 4: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, BTG */ + rfe_type->wlg_Locate_at_btg = true; + rfe_type->ant_at_main_port = false; + break; + case 5: + rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_NONE; + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 6: + rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_NONE; + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 7: + rfe_type->ext_ant_switch_exist = true; /*2-Ant, DPDT, BTG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT; + rfe_type->wlg_Locate_at_btg = true; + rfe_type->ant_at_main_port = true; + break; + } + +} + + +VOID +ex_hal8821c_wifi_only_hw_config( + IN struct wifi_only_cfg *pwifionlycfg + ) +{ + halbtc8821c_wifi_only_set_rfe_type(pwifionlycfg); + + /* set gnt_wl, gnt_bt control owner to WL*/ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0x400000, 0x1); + + /*gnt_wl=1 , gnt_bt=0*/ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700); + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); +} + +VOID +ex_hal8821c_wifi_only_scannotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ) +{ + hal8821c_wifi_only_switch_antenna(pwifionlycfg, is_5g); +} + +VOID +ex_hal8821c_wifi_only_switchbandnotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ) +{ + hal8821c_wifi_only_switch_antenna(pwifionlycfg, is_5g); +} + diff --git a/hal/btc/halbtc8821cwifionly.h b/hal/btc/halbtc8821cwifionly.h new file mode 100644 index 0000000..1949b59 --- /dev/null +++ b/hal/btc/halbtc8821cwifionly.h @@ -0,0 +1,84 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __INC_HAL8821CWIFIONLYHWCFG_H +#define __INC_HAL8821CWIFIONLYHWCFG_H + + +struct rfe_type_8821c_wifi_only { + + u8 rfe_module_type; + boolean ext_ant_switch_exist; + u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */ + u8 ext_ant_switch_ctrl_polarity; /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ + + boolean ant_at_main_port; + + boolean wlg_Locate_at_btg; /* If true: WLG at BTG, If false: WLG at WLAG */ + + boolean ext_ant_switch_diversity; /* If diversity on */ +}; + +enum bt_8821c_wifi_only_ext_ant_switch_type { + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT = 0x0, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_SPDT = 0x1, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_NONE = 0x2, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_MAX +}; + +enum bt_8821c_wifi_only_ext_ant_switch_ctrl_type { + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_MAX +}; + +enum bt_8821c_wifi_only_ext_ant_switch_pos_type { + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_BT = 0x0, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLG = 0x1, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLA = 0x2, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_NOCARE = 0x3, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_MAX +}; + + +VOID +hal8821c_wifi_only_switch_antenna( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ); + +VOID +halbtc8821c_wifi_only_set_rfe_type( + IN struct wifi_only_cfg *pwifionlycfg + ); + + +VOID +ex_hal8821c_wifi_only_hw_config( + IN struct wifi_only_cfg *pwifionlycfg + ); +VOID +ex_hal8821c_wifi_only_scannotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ); +VOID +ex_hal8821c_wifi_only_switchbandnotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ); +#endif diff --git a/hal/btc/halbtc8822b1ant.c b/hal/btc/halbtc8822b1ant.c new file mode 100644 index 0000000..7ec25e2 --- /dev/null +++ b/hal/btc/halbtc8822b1ant.c @@ -0,0 +1,7130 @@ +/* ************************************************************ + * Description: + * + * This file is for RTL8822B Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +/*only for rf4ce*/ +#include "mp_precomp.h" + + + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8822B_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8822b_1ant glcoex_dm_8822b_1ant; +static struct coex_dm_8822b_1ant *coex_dm = &glcoex_dm_8822b_1ant; +static struct coex_sta_8822b_1ant glcoex_sta_8822b_1ant; +static struct coex_sta_8822b_1ant *coex_sta = &glcoex_sta_8822b_1ant; +static struct psdscan_sta_8822b_1ant gl_psd_scan_8822b_1ant; +static struct psdscan_sta_8822b_1ant *psd_scan = &gl_psd_scan_8822b_1ant; +static struct rfe_type_8822b_1ant gl_rfe_type_8822b_1ant; +static struct rfe_type_8822b_1ant *rfe_type = &gl_rfe_type_8822b_1ant; + + + +static const char *const glbt_info_src_8822b_1ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +static u32 glcoex_ver_date_8822b_1ant = 20170518; +static u32 glcoex_ver_8822b_1ant = 0x44; +static u32 glcoex_ver_btdesired_8822b_1ant = 0x42; + + +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8822b1ant_ + * ************************************************************ */ +#if 0 +static +u8 halbtc8822b1ant_bt_rssi_state(IN struct btc_coexist *btcoexist, + u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_bt_rssi_state; + } + + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} +#endif + +static +u8 halbtc8822b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_wifi_rssi_state[index]; + } + + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; + + return wifi_rssi_state; +} + +static +void halbtc8822b1ant_update_ra_mask(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 dis_rate_mask) +{ + coex_dm->cur_ra_mask = dis_rate_mask; + + if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) + btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, + &coex_dm->cur_ra_mask); + coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; +} + +static +void halbtc8822b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + boolean wifi_under_b_mode = FALSE; + + coex_dm->cur_arfr_type = type; + + if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { + switch (coex_dm->cur_arfr_type) { + case 0: /* normal mode */ + btcoexist->btc_write_4byte(btcoexist, 0x430, + coex_dm->backup_arfr_cnt1); + btcoexist->btc_write_4byte(btcoexist, 0x434, + coex_dm->backup_arfr_cnt2); + break; + case 1: + btcoexist->btc_get(btcoexist, + BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + if (wifi_under_b_mode) { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x01010101); + } else { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x04030201); + } + break; + default: + break; + } + } + + coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; +} + +static +void halbtc8822b1ant_retry_limit(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_retry_limit_type = type; + + if (force_exec || + (coex_dm->pre_retry_limit_type != + coex_dm->cur_retry_limit_type)) { + switch (coex_dm->cur_retry_limit_type) { + case 0: /* normal mode */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + coex_dm->backup_retry_limit); + break; + case 1: /* retry limit=8 */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + 0x0808); + break; + default: + break; + } + } + + coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; +} + +static +void halbtc8822b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_ampdu_time_type = type; + + if (force_exec || + (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { + switch (coex_dm->cur_ampdu_time_type) { + case 0: /* normal mode */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + coex_dm->backup_ampdu_max_time); + break; + case 1: /* AMPDU timw = 0x38 * 32us */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + 0x38); + break; + default: + break; + } + } + + coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; +} + +static +void halbtc8822b1ant_limited_tx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, + IN u8 retry_limit_type, IN u8 ampdu_time_type) +{ + switch (ra_mask_type) { + case 0: /* normal mode */ + halbtc8822b1ant_update_ra_mask(btcoexist, force_exec, + 0x0); + break; + case 1: /* disable cck 1/2 */ + halbtc8822b1ant_update_ra_mask(btcoexist, force_exec, + 0x00000003); + break; + case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ + halbtc8822b1ant_update_ra_mask(btcoexist, force_exec, + 0x0001f1f7); + break; + default: + break; + } + + halbtc8822b1ant_auto_rate_fallback_retry(btcoexist, force_exec, + arfr_type); + halbtc8822b1ant_retry_limit(btcoexist, force_exec, retry_limit_type); + halbtc8822b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); +} + +/* + * rx agg size setting : + * 1: TRUE / don't care / don't care + * max: FALSE / FALSE / don't care + * 7: FALSE / TRUE / 7 + */ + +static +void halbtc8822b1ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size*/ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +static +void halbtc8822b1ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No query BT info because BT is disabled!\n"); + BTC_TRACE(trace_buf); + return; + } + + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WL query BT info!!\n"); + BTC_TRACE(trace_buf); +} + + + +static +void halbtc8822b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_autoslot_hang = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + +#if 0 + /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ + if (!(btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8)) +#endif + +#if 0 + if (coex_sta->under_ips) { + /* coex_sta->high_priority_tx = 65535; */ + /* coex_sta->high_priority_rx = 65535; */ + /* coex_sta->low_priority_tx = 65535; */ + /* coex_sta->low_priority_rx = 65535; */ + /* return; */ + } +#endif + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); + BTC_TRACE(trace_buf); + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + + if ((coex_sta->low_priority_tx > 1150) && + (!coex_sta->c2h_bt_inquiry_page)) + coex_sta->pop_event_cnt++; + + if ((coex_sta->low_priority_rx >= 1150) && + (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) + && (!coex_sta->under_ips) && + (!coex_sta->c2h_bt_inquiry_page) && + (coex_sta->bt_link_exist)) { + if (cnt_slave >= 3) { + bt_link_info->slave_role = TRUE; + cnt_slave = 3; + } else { + cnt_slave++; + } + } else { + if (cnt_slave == 0) { + bt_link_info->slave_role = FALSE; + cnt_slave = 0; + } else { + cnt_slave--; + } + + } + + if (coex_sta->is_tdma_btautoslot) { + if ((coex_sta->low_priority_tx >= 1300) && + (coex_sta->low_priority_rx <= 150)) { + if (cnt_autoslot_hang >= 2) { + coex_sta->is_tdma_btautoslot_hang = TRUE; + cnt_autoslot_hang = 2; + } else { + cnt_autoslot_hang++; + } + } else { + if (cnt_autoslot_hang == 0) { + coex_sta->is_tdma_btautoslot_hang = FALSE; + cnt_autoslot_hang = 0; + } else { + cnt_autoslot_hang--; + } + } + } + + if (bt_link_info->hid_only) { + if (coex_sta->low_priority_rx > 50) + coex_sta->is_hid_low_pri_tx_overhead = true; + else + coex_sta->is_hid_low_pri_tx_overhead = false; + } + + if ((coex_sta->high_priority_tx == 0) && + (coex_sta->high_priority_rx == 0) && + (coex_sta->low_priority_tx == 0) && + (coex_sta->low_priority_rx == 0)) { + num_of_bt_counter_chk++; + + if (num_of_bt_counter_chk >= 3) { + halbtc8822b1ant_query_bt_info( + btcoexist); + num_of_bt_counter_chk = 0; + } + } + +} + + +static +void halbtc8822b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ +#if 1 + s32 wifi_rssi = 0; + boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE, + wifi_scan = FALSE; + static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, + wl_noisy_count1 = 3, wl_noisy_count2 = 0; + u32 total_cnt, cck_cnt; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_VHT); + + cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; + + if (cck_cnt > 250) { + if (wl_noisy_count2 < 3) + wl_noisy_count2++; + + if (wl_noisy_count2 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count1 = 0; + } + + } else if (cck_cnt < 50) { + if (wl_noisy_count0 < 3) + wl_noisy_count0++; + + if (wl_noisy_count0 == 3) { + wl_noisy_count1 = 0; + wl_noisy_count2 = 0; + } + + } else { + if (wl_noisy_count1 < 3) + wl_noisy_count1++; + + if (wl_noisy_count1 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count2 = 0; + } + } + + if (wl_noisy_count2 == 3) + coex_sta->wl_noisy_level = 2; + else if (wl_noisy_count1 == 3) + coex_sta->wl_noisy_level = 1; + else + coex_sta->wl_noisy_level = 0; + + if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { + total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht; + + if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY) + || + (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY)) { + if (coex_sta->crc_ok_cck > (total_cnt - + coex_sta->crc_ok_cck)) { + if (cck_lock_counter < 3) + cck_lock_counter++; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + if (!coex_sta->pre_ccklock) { + + if (cck_lock_counter >= 3) + coex_sta->cck_lock = TRUE; + else + coex_sta->cck_lock = FALSE; + } else { + if (cck_lock_counter == 0) + coex_sta->cck_lock = FALSE; + else + coex_sta->cck_lock = TRUE; + } + + if (coex_sta->cck_lock) + coex_sta->cck_ever_lock = TRUE; + + coex_sta->pre_ccklock = coex_sta->cck_lock; + +#endif +} + + +static +boolean halbtc8822b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) +{ + static boolean pre_wifi_busy = FALSE, pre_under_4way = FALSE, + pre_bt_hs_on = FALSE, pre_rf4ce_enabled = FALSE, pre_bt_off = FALSE, + pre_bt_slave = FALSE, pre_hid_low_pri_tx_overhead = FALSE, + pre_wifi_under_lps = FALSE, pre_bt_setup_link = FALSE; + static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0; + boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE, rf4ce_enabled = FALSE; + boolean wifi_connected = FALSE; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (coex_sta->bt_disabled != pre_bt_off) { + pre_bt_off = coex_sta->bt_disabled; + + if (coex_sta->bt_disabled) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + return TRUE; + } + btcoexist->btc_get(btcoexist, BTC_GET_BL_RF4CE_CONNECTED, &rf4ce_enabled); + + if (rf4ce_enabled != pre_rf4ce_enabled) { + pre_rf4ce_enabled = rf4ce_enabled; + + if (rf4ce_enabled) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], rf4ce is enabled !!\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], rf4ce is disabled !!\n"); + + BTC_TRACE(trace_buf); + + + return TRUE; + } + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return TRUE; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return TRUE; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return TRUE; + } + if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { + pre_wl_noisy_level = coex_sta->wl_noisy_level; + return TRUE; + } + if (coex_sta->under_lps != pre_wifi_under_lps) { + pre_wifi_under_lps = coex_sta->under_lps; + if (coex_sta->under_lps) + return TRUE; + } + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->hid_busy_num != pre_hid_busy_num) { + pre_hid_busy_num = coex_sta->hid_busy_num; + return TRUE; + } + + if (bt_link_info->slave_role != pre_bt_slave) { + pre_bt_slave = bt_link_info->slave_role; + return TRUE; + } + + if (pre_hid_low_pri_tx_overhead != coex_sta->is_hid_low_pri_tx_overhead) { + pre_hid_low_pri_tx_overhead = coex_sta->is_hid_low_pri_tx_overhead; + return TRUE; + } + + if (pre_bt_setup_link != coex_sta->is_setupLink) { + pre_bt_setup_link = coex_sta->is_setupLink; + return TRUE; + } + } + + return FALSE; +} + + + +static +void halbtc8822b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = FALSE; + boolean bt_busy = FALSE; + + + coex_sta->num_of_profile = 0; + + /* set link exist status */ + if (!(coex_sta->bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = FALSE; + coex_sta->pan_exist = FALSE; + coex_sta->a2dp_exist = FALSE; + coex_sta->hid_exist = FALSE; + coex_sta->sco_exist = FALSE; + } else { /* connection exists */ + coex_sta->bt_link_exist = TRUE; + if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_FTP) { + coex_sta->pan_exist = TRUE; + coex_sta->num_of_profile++; + } else { + coex_sta->pan_exist = FALSE; + } + + if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_A2DP) { + coex_sta->a2dp_exist = TRUE; + coex_sta->num_of_profile++; + } else { + coex_sta->a2dp_exist = FALSE; + } + + if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_HID) { + coex_sta->hid_exist = TRUE; + coex_sta->num_of_profile++; + } else { + coex_sta->hid_exist = FALSE; + } + + if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) { + coex_sta->sco_exist = TRUE; + coex_sta->num_of_profile++; + } else { + coex_sta->sco_exist = FALSE; + } + + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + bt_link_info->acl_busy = coex_sta->acl_busy; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = TRUE; + bt_link_info->bt_link_exist = TRUE; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = TRUE; + else + bt_link_info->sco_only = FALSE; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = TRUE; + else + bt_link_info->a2dp_only = FALSE; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = TRUE; + else + bt_link_info->pan_only = FALSE; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = TRUE; + else + bt_link_info->hid_only = FALSE; + + if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_INQ_PAGE) { + coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_INQ_PAGE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); + } else if (!(coex_sta->bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + } else if (coex_sta->bt_info == BT_INFO_8822B_1ANT_B_CONNECTION) { + /* connection exists but no busy */ + coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + } else if (((coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_BUSY)) && + (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_ACL_BUSY)) { + coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); + } else if ((coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + } else if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + } else { + coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + } + + BTC_TRACE(trace_buf); + + if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY) || + (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY)) + bt_busy = TRUE; + else + bt_busy = FALSE; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); +} + + +static +void halbtc8822b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + + /* enable BT AFH skip WL channel for 8822b + * because BT Rx LO interference + */ + h2c_parameter[0] = 0x1; + h2c_parameter[1] = wifi_central_chnl; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); + +} + +static +u8 halbtc8822b1ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = FALSE; + u8 algorithm = BT_8822B_1ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_1ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_1ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_1ANT_COEX_ALGO_SCO; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_1ANT_COEX_ALGO_HID_A2DP; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + + + + + + + +static +void halbtc8822b1ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, + IN u8 dac_swing_lvl) +{ + u8 h2c_parameter[1] = {0}; + u32 RTL97F_8822B = 0; + + if (RTL97F_8822B) + return; + + /* There are several type of dacswing */ + /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ + h2c_parameter[0] = dac_swing_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); +} + + +static +void halbtc8822b1ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 fw_dac_swing_lvl) +{ + u32 RTL97F_8822B = 0; + + if (RTL97F_8822B) + return; + + coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; + + if (!force_exec) { + if (coex_dm->pre_fw_dac_swing_lvl == + coex_dm->cur_fw_dac_swing_lvl) + return; + } + + halbtc8822b1ant_set_fw_dac_swing_level(btcoexist, + coex_dm->cur_fw_dac_swing_lvl); + + coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; +} + +static +void halbtc8822b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ +#if 1 + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == + coex_dm->cur_low_penalty_ra) + return; + } + + if (low_penalty_ra) + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); + else + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; + +#endif +} + +static +void halbtc8822b1ant_write_score_board( + IN struct btc_coexist *btcoexist, + IN u16 bitpos, + IN boolean state +) +{ + + static u16 originalval = 0x8002; + + if (state) + originalval = originalval | bitpos; + else + originalval = originalval & (~bitpos); + + btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); +} + +static +void halbtc8822b1ant_read_score_board( + IN struct btc_coexist *btcoexist, + IN u16 *score_board_val +) +{ + + *score_board_val = (btcoexist->btc_read_2byte(btcoexist, + 0xaa)) & 0x7fff; +} + +static +void halbtc8822b1ant_post_state_to_bt( + IN struct btc_coexist *btcoexist, + IN u16 type, + IN boolean state +) +{ + + halbtc8822b1ant_write_score_board(btcoexist, (u16) type, state); + +} + + +static +void halbtc8822b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = TRUE, bt_disabled = FALSE, + wifi_under_5g = FALSE; + u16 u16tmp; + + /* This function check if bt is disabled */ +#if 0 + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = FALSE; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = FALSE; + + +#else + + /* Read BT on/off status from scoreboard[1], + * enable this only if BT patch support this feature + */ + halbtc8822b1ant_read_score_board(btcoexist, &u16tmp); + + bt_active = u16tmp & BIT(1); + + +#endif + + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = FALSE; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } else { + + bt_disable_cnt++; + if (bt_disable_cnt >= 2) { + bt_disabled = TRUE; + bt_disable_cnt = 2; + } + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, + &wifi_under_5g); + + if ((wifi_under_5g) || (bt_disabled)) + halbtc8822b1ant_low_penalty_ra(btcoexist, + NORMAL_EXEC, FALSE); + else + halbtc8822b1ant_low_penalty_ra(btcoexist, + NORMAL_EXEC, TRUE); + + + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : + "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + } + +} + + + +static +void halbtc8822b1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, + boolean isenable) +{ +#if BT_8822B_1ANT_COEX_DBG + static u8 bitVal[5] = {0, 0, 0, 0, 0}; + static boolean state = FALSE; + + if (state == isenable) + return; + + state = isenable; + + if (isenable) { + + /* enable GNT_WL, GNT_BT to GPIO for debug */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); + + /* store original value */ + bitVal[0] = (btcoexist->btc_read_1byte(btcoexist, + 0x66) & BIT(4)) >> 4; /*0x66[4] */ + bitVal[1] = (btcoexist->btc_read_1byte(btcoexist, + 0x67) & BIT(0)); /*0x66[8] */ + bitVal[2] = (btcoexist->btc_read_1byte(btcoexist, + 0x42) & BIT(3)) >> 3; /*0x40[19] */ + bitVal[3] = (btcoexist->btc_read_1byte(btcoexist, + 0x65) & BIT(7)) >> 7; /*0x64[15] */ + bitVal[4] = (btcoexist->btc_read_1byte(btcoexist, + 0x72) & BIT(2)) >> 2; /*0x70[18] */ + + /* switch GPIO Mux */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), + 0x0); /*0x66[4] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), + 0x0); /*0x66[8] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), + 0x0); /*0x40[19] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), + 0x0); /*0x64[15] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), + 0x0); /*0x70[18] = 0 */ + + + } else { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); + + /* Restore original value */ + /* switch GPIO Mux */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), + bitVal[0]); /*0x66[4] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), + bitVal[1]); /*0x66[8] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), + bitVal[2]); /*0x40[19] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), + bitVal[3]); /*0x64[15] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), + bitVal[4]); /*0x70[18] = 0 */ + } +#endif +} + + + +static +u32 halbtc8822b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, + IN u16 reg_addr) +{ + u32 delay_count = 0; + + /* wait for ready bit before access 0x1700 */ + while (1) { + if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { + delay_ms(50); + delay_count++; + if (delay_count >= 10) { + delay_count = 0; + break; + } + } else { + break; + } + } + + btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr); + + return btcoexist->btc_read_4byte(btcoexist, + 0x1708); /* get read data */ +} + + +static +void halbtc8822b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist + *btcoexist, + IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) +{ + u32 val, i = 0, bitpos = 0, delay_count = 0; + + + if (bit_mask == 0x0) + return; + + if (bit_mask == 0xffffffff) { + /* wait for ready bit before access 0x1700/0x1704 */ + while (1) { + if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { + delay_ms(50); + delay_count++; + if (delay_count >= 10) { + delay_count = 0; + break; + } + } else { + break; + } + } + + btcoexist->btc_write_4byte(btcoexist, 0x1704, + reg_value); /* put write data */ + + btcoexist->btc_write_4byte(btcoexist, 0x1700, + 0xc00F0000 | reg_addr); + } else { + for (i = 0; i <= 31; i++) { + if (((bit_mask >> i) & 0x1) == 0x1) { + bitpos = i; + break; + } + } + + /* read back register value before write */ + val = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + reg_addr); + val = (val & (~bit_mask)) | (reg_value << bitpos); + + /* wait for ready bit before access 0x1700/0x1704 */ + while (1) { + if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { + delay_ms(50); + delay_count++; + if (delay_count >= 10) { + delay_count = 0; + break; + } + } else { + break; + } + } + + btcoexist->btc_write_4byte(btcoexist, 0x1704, + val); /* put write data */ + + btcoexist->btc_write_4byte(btcoexist, 0x1700, + 0xc00F0000 | reg_addr); + + } + +} + + +static +void halbtc8822b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 val; + + val = (enable) ? 1 : 0; + /* 0x38[7] */ + halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, val); + +} + + + +static +void halbtc8822b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, + IN boolean wifi_control) +{ + u8 val; + + val = (wifi_control) ? 1 : 0; + /* 0x70[26] */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, val); + +} + + +static +void halbtc8822b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, bit_mask; + + state = state & 0x1; + /*LTE indirect 0x38=0xccxx (sw : gnt_wl=1,sw gnt_bt=1) + *0x38=0xddxx (sw : gnt_bt=1 , sw gnt_wl=0) + *0x38=0x55xx(hw pta :gnt_wl /gnt_bt ) + */ + val = (sw_control) ? ((state << 1) | 0x1) : 0; + + switch (control_block) { + case BT_8822B_1ANT_GNT_BLOCK_RFC_BB: + default: + bit_mask = 0xc000; + halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[15:14] */ + bit_mask = 0x0c00; + halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[11:10] */ + break; + case BT_8822B_1ANT_GNT_BLOCK_RFC: + bit_mask = 0xc000; + halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[15:14] */ + break; + case BT_8822B_1ANT_GNT_BLOCK_BB: + bit_mask = 0x0c00; + halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[11:10] */ + break; + + } + +} + + +static +void halbtc8822b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, bit_mask; + /*LTE indirect 0x38=0xccxx (sw : gnt_wl=1,sw gnt_bt=1) + *0x38=0xddxx (sw : gnt_bt=1 , sw gnt_wl=0) + *0x38=0x55xx(hw pta :gnt_wl /gnt_bt ) + */ + + state = state & 0x1; + val = (sw_control) ? ((state << 1) | 0x1) : 0; + + switch (control_block) { + case BT_8822B_1ANT_GNT_BLOCK_RFC_BB: + default: + bit_mask = 0x3000; + halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[13:12] */ + bit_mask = 0x0300; + halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[9:8] */ + break; + case BT_8822B_1ANT_GNT_BLOCK_RFC: + bit_mask = 0x3000; + halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[13:12] */ + break; + case BT_8822B_1ANT_GNT_BLOCK_BB: + bit_mask = 0x0300; + halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[9:8] */ + break; + + } + +} + + +static +void halbtc8822b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u16 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8822B_1ANT_CTT_WL_VS_LTE: + reg_addr = 0xa0; + break; + case BT_8822B_1ANT_CTT_BT_VS_LTE: + reg_addr = 0xa4; + break; + } + + if (reg_addr != 0x0000) + halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ + + +} + + + +#if 0 +static +void halbtc8822b1ant_ltcoex_set_break_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u8 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8822B_1ANT_LBTT_WL_BREAK_LTE: + reg_addr = 0xa8; + break; + case BT_8822B_1ANT_LBTT_BT_BREAK_LTE: + reg_addr = 0xac; + break; + case BT_8822B_1ANT_LBTT_LTE_BREAK_WL: + reg_addr = 0xb0; + break; + case BT_8822B_1ANT_LBTT_LTE_BREAK_BT: + reg_addr = 0xb4; + break; + } + + if (reg_addr != 0x0000) + halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ + + +} +#endif + + + + +static +void halbtc8822b1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 interval, + IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, + IN u8 val0x6c4_b3) +{ + static u8 pre_h2c_parameter[6] = {0}; + u8 cur_h2c_parameter[6] = {0}; + u8 i, match_cnt = 0; + + cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ + + cur_h2c_parameter[1] = interval; + cur_h2c_parameter[2] = val0x6c4_b0; + cur_h2c_parameter[3] = val0x6c4_b1; + cur_h2c_parameter[4] = val0x6c4_b2; + cur_h2c_parameter[5] = val0x6c4_b3; + + if (!force_exec) { + for (i = 1; i <= 5; i++) { + if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) + break; + + match_cnt++; + } + + if (match_cnt == 5) + return; + } + + for (i = 1; i <= 5; i++) + pre_h2c_parameter[i] = cur_h2c_parameter[i]; + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); +} + + + +static +void halbtc8822b1ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + + +static +void halbtc8822b1ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8822b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + + +static +void halbtc8822b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + u32 break_table; + u8 select_table; + + + + coex_sta->coex_table_type = type; + + if (coex_sta->concurrent_rx_mode_on) { + break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ + select_table = 0x3; /* set Tx response = Hi-Pri + * (ex: Transmitting ACK,BA,CTS) + */ + } else { + break_table = 0xffffff; + select_table = 0x3; + } + + switch (type) { + case 0: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, break_table, + select_table); + break; + case 1: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 2: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xaa5a5a5a, 0xaa5a5a5a, break_table, + select_table); + break; + case 3: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xaa5a5a5a, break_table, + select_table); + break; + case 4: + halbtc8822b1ant_coex_table(btcoexist, + force_exec, 0xaa555555, 0xaa5a5a5a, + break_table, select_table); + break; + case 5: + halbtc8822b1ant_coex_table(btcoexist, + force_exec, 0x5a5a5a5a, 0x5a5a5a5a, + break_table, select_table); + break; + case 6: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xaaaaaaaa, break_table, + select_table); + break; + case 7: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xaaaaaaaa, 0xaaaaaaaa, break_table, + select_table); + break; + case 8: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xffffffff, 0xffffffff, break_table, + select_table); + break; + case 9: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x5a5a5555, 0xaaaa5a5a, break_table, + select_table); + break; + case 10: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xaaaa5aaa, 0xaaaa5aaa, break_table, + select_table); + break; + case 11: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xaaaaa5aa, 0xaaaaaaaa, break_table, + select_table); + break; + case 12: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xaaaaa5aa, 0xaaaaa5aa, break_table, + select_table); + break; + case 13: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xaaaa5a5a, break_table, + select_table); + break; + case 14: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x5a5a555a, 0xaaaa5a5a, break_table, + select_table); + break; + case 15: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xaaaa55aa, break_table, + select_table); + break; + case 16: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x5a5a555a, 0x5a5a555a, break_table, + select_table); + break; + case 17: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xaaaa55aa, 0xaaaa55aa, break_table, + select_table); + break; + case 18: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5aaa5a5a, break_table, + select_table); + break; + case 19: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xaaaa5aaa, break_table, + select_table); + break; + case 20: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xaaaa5aaa, break_table, + select_table); + break; + case 21: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555a5a, break_table, + select_table); + break; + default: + break; + } +} + + +static +void halbtc8822b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + + + u8 h2c_parameter[1] = {0}; + + if (enable) + h2c_parameter[0] |= BIT(0); /* function enable */ + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + + +static +void halbtc8822b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) { + + coex_dm->pre_ignore_wlan_act = + coex_dm->cur_ignore_wlan_act; + return; + } + } + + halbtc8822b1ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + + +static +void halbtc8822b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + + +static +void halbtc8822b1ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8822b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + + + +static +void halbtc8822b1ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + + + + +static +boolean halbtc8822b1ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = FALSE, result = TRUE; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + /* recover to original 32k low power setting */ + coex_sta->force_lps_ctrl = FALSE; + low_pwr_disable = FALSE; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + break; + case BTC_PS_LPS_ON: + + coex_sta->force_lps_ctrl = TRUE; + halbtc8822b1ant_ps_tdma_check_for_power_save_state( + btcoexist, TRUE); + halbtc8822b1ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = TRUE; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + + break; + case BTC_PS_LPS_OFF: + + coex_sta->force_lps_ctrl = TRUE; + halbtc8822b1ant_ps_tdma_check_for_power_save_state( + btcoexist, FALSE); + result = btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + + break; + default: + break; + } + + return result; +} + + + + +static +void halbtc8822b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = FALSE, result = FALSE; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if (byte5 & BIT(2)) + coex_sta->is_tdma_btautoslot = TRUE; + else + coex_sta->is_tdma_btautoslot = FALSE; + + /* release bt-auto slot for auto-slot hang is detected!! */ + if (coex_sta->is_tdma_btautoslot) + if ((coex_sta->is_tdma_btautoslot_hang) || + (bt_link_info->slave_role)) + byte5 = byte5 & 0xfb; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b1ant_set_fw_pstdma == FW for 1Ant AP mode\n"); + BTC_TRACE(trace_buf); + + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + + halbtc8822b1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + + } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b1ant_set_fw_pstdma == Force LPS (byte1 = 0x%x)\n", byte1); + BTC_TRACE(trace_buf); + if (!halbtc8822b1ant_power_save_state(btcoexist, BTC_PS_LPS_OFF, 0x50, 0x4)) + result = TRUE; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b1ant_set_fw_pstdma == native power save (byte1 = 0x%x)\n", byte1); + BTC_TRACE(trace_buf); + halbtc8822b1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + } + + + coex_sta->is_set_ps_state_fail = result; + + if (!coex_sta->is_set_ps_state_fail) { + h2c_parameter[0] = real_byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = real_byte5; + + coex_dm->ps_tdma_para[0] = real_byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = real_byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); + + } else { + coex_sta->cnt_set_ps_state_fail++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b1ant_set_fw_pstdma == Force Leave LPS Fail (cnt = %d)\n", + coex_sta->cnt_set_ps_state_fail); + BTC_TRACE(trace_buf); + } +} + + + +static +void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = FALSE; + static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; + static boolean pre_wifi_busy = FALSE; + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (wifi_busy != pre_wifi_busy) { + force_exec = TRUE; + pre_wifi_busy = wifi_busy; + } + + /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ + if (bt_link_info->slave_role) + psTdmaByte4Modify = 0x1; + else + psTdmaByte4Modify = 0x0; + + if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { + + force_exec = TRUE; + pre_psTdmaByte4Modify = psTdmaByte4Modify; + } + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n", + (coex_dm->cur_ps_tdma_on ? "on" : "off"), + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + return; + } + } + + if (coex_dm->cur_ps_tdma_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(on, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } + + + + if (turn_on) { + + /* enable TBTT nterrupt */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, 0x1); + + switch (type) { + default: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x03, 0x11, 0x11); + break; + case 1: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x3a, 0x03, 0x11, 0x10); + break; + case 3: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x30, 0x03, 0x10, 0x50); + break; + case 4: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x21, 0x03, 0x10, 0x50); + break; + case 5: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x15, 0x3, 0x11, 0x11); + break; + case 6: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x20, 0x3, 0x11, 0x10); + break; + case 7: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 8: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x14 | + psTdmaByte4Modify); + break; + case 11: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x25, 0x03, 0x11, 0x10 | + psTdmaByte4Modify); + break; + case 12: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x30, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 13: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x07, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 14: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x15, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 15: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x20, 0x03, 0x10, 0x10 | + psTdmaByte4Modify); + break; + case 17: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x14 | + psTdmaByte4Modify); + break; + case 18: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + + case 20: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x30, 0x03, 0x11, 0x10); + break; + case 22: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x25, 0x03, 0x11, 0x10); + break; + case 27: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x15); + break; + case 32: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x3, 0x11, 0x11); + break; + case 33: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x03, 0x11, 0x10); + break; + case 41: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x45, 0x3, 0x11, 0x11); + break; + case 42: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x1e, 0x3, 0x10, 0x14 | + psTdmaByte4Modify); + break; + case 43: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x45, 0x3, 0x10, 0x14); + break; + case 44: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x25, 0x3, 0x10, 0x10); + break; + case 45: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x29, 0x3, 0x10, 0x10); + break; + case 46: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x1a, 0x3, 0x10, 0x10); + break; + case 47: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x32, 0x3, 0x10, 0x10); + break; + case 48: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x29, 0x3, 0x10, 0x10); + break; + case 49: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x55, 0x10, 0x3, 0x10, 0x54); + break; + case 50: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x4a, 0x3, 0x10, 0x10); + break; + case 51: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x3, 0x10, 0x11); + break; + + } + } else { + + switch (type) { + case 0: + default: /* Software control, Antenna at BT side */ + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x0, 0x0, 0x0, 0x0, 0x0); +#if 0 + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, + FALSE); +#endif + break; +#if 0 +/* 08:1ant:PTA Control -0x778=1-ant hw control,40:2ant:sw control-diversity */ +#endif + case 8: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x8, 0x0, 0x0, 0x0, 0x0); +#if 0 + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, + FALSE); +#endif + break; + case 9: /* Software control, Antenna at WiFi side */ + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x0, 0x0, 0x0, 0x0, 0x0); +#if 0 + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_WIFI, FORCE_EXEC, FALSE, FALSE); +#endif + break; + case 10: /* under 5G , 0x778=1*/ + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x0, 0x0, 0x0, 0x0, 0x0); + +#if 0 + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_WIFI5G, FORCE_EXEC, FALSE, + FALSE); +#endif + break; + } + } + + + if (!coex_sta->is_set_ps_state_fail) { + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; + } +} + + + +static +void halbtc8822b1ant_sw_mechanism(IN struct btc_coexist *btcoexist, + IN boolean low_penalty_ra) +{ + halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); +} + +/* rf4 type by efuse, and for ant at main aux inverse use, + * because is 2x2, and control types are the same, does not need + */ + +static +void halbtc8822b1ant_set_rfe_type(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + + /* Ext switch buffer mux */ + btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); + + /* the following setup should be got from Efuse in the future */ + rfe_type->rfe_module_type = board_info->rfe_type; + + rfe_type->ext_ant_switch_ctrl_polarity = 0; + + switch (rfe_type->rfe_module_type) { + case 0: + default: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 1: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 2: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 3: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 4: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 5: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 6: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 7: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + } + + +} + +/*anttenna control by bb mac bt antdiv pta to write 0x4c 0xcb4,0xcbd*/ + + +static +void halbtc8822b1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) +{ + boolean switch_polatiry_inverse = FALSE; + u8 regval_0xcbd = 0, regval_0x64; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + + /* Ext switch buffer mux */ + btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); + + if (!rfe_type->ext_ant_switch_exist) + return; + + coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; + + if (!force_exec) { + if (coex_dm->pre_ext_ant_switch_status == + coex_dm->cur_ext_ant_switch_status) + return; + } + + coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status; + + /* swap control polarity if use different switch control polarity*/ + /* Normal switch polarity for SPDT, + * 0xcbd[1:0] = 2b'01 => Ant to BTG, + * 0xcbd[1:0] = 2b'10 => Ant to WLG + */ + switch_polatiry_inverse = (rfe_type->ext_ant_switch_ctrl_polarity == 1 ? + ~switch_polatiry_inverse : switch_polatiry_inverse); + + + switch (pos_type) { + default: + case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT: + case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE: + + break; + case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG: + break; + case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA: + break; + } + + + if (rfe_type->ext_ant_switch_type == + BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT) { + switch (ctrl_type) { + default: + case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW: + /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x4e, 0x80, + 0x0); + /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x4f, 0x01, + 0x1); + /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin*/ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcb4, 0xff, + 0x77); + + /* 0xcbd[1:0] = 2b'01 for no switch_polatiry_inverse, + * ANTSWB =1, ANTSW =0 + */ + regval_0xcbd = (!switch_polatiry_inverse ? 0x1 : 0x2); + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, + regval_0xcbd); + + break; + case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: + /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x4e, 0x80, + 0x0); + /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x4f, 0x01, + 0x1); + /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcb4, 0xff, + 0x66); + + /* 0xcbd[1:0] = 2b'10 for no switch_polatiry_inverse, + * ANTSWB =1, ANTSW =0 @ GNT_BT=1 + */ + regval_0xcbd = (!switch_polatiry_inverse ? 0x2 : 0x1); + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, + regval_0xcbd); + + break; + case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: + /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x4e, 0x80, + 0x0); + /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x4f, 0x01, + 0x1); + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcb4, 0xff, + 0x88); + + /* no regval_0xcbd setup required, because + * antenna switch control value by antenna diversity + */ + + break; + case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC: + /* 0x4c[23] = 1 */ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x4e, 0x80, + 0x1); + + /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, + * DPDT_SEL_N =1, DPDT_SEL_P =0 + */ + regval_0x64 = (!switch_polatiry_inverse ? 0x0 : 0x1); + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x64, 0x1, + regval_0x64); + break; + case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT: + /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x4e, 0x80, + 0x0); + /* 0x4c[24] = 0 */ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x4f, 0x01, + 0x0); + + /* no setup required, because antenna switch control + * value by BT vendor 0xac[1:0] + */ + break; + } + } + + u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcbc); + u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (After Ext Ant switch setup) 0xcbc = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x**********\n", + u32tmp1, u32tmp2, u32tmp3); + BTC_TRACE(trace_buf); + + +} + +/* set gnt_wl gnt_bt control by sw high low, or + * hwpta while in power on, ini, wlan off, wlan only, wl2g non-currrent, + * wl2g current, wl5g + */ + + +static +void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean force_exec, + IN u8 phase) + +{ +#if BT_8822B_1ANT_COEX_DBG + u8 u8tmp = 0; +#endif + u32 u32tmp1 = 0; +#if BT_8822B_1ANT_COEX_DBG + u32 u32tmp2 = 0, u32tmp3 = 0; +#endif + + u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + /* To avoid indirect access fail */ + if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { + force_exec = TRUE; + coex_sta->gnt_error_cnt++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],(Before Ant Setup) 0x38= 0x%x\n", + u32tmp1); + BTC_TRACE(trace_buf); + } + + /* Ext switch buffer mux */ + btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); + + coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; + + if (!force_exec) { + if (coex_dm->cur_ant_pos_type == + coex_dm->pre_ant_pos_type) + return; + } + + coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; + +#if BT_8822B_1ANT_COEX_DBG + u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0x54); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", + u32tmp3, u8tmp, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); +#endif + + switch (phase) { + case BT_8822B_1ANT_PHASE_COEX_INIT: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_COEX_INIT) **********\n"); + BTC_TRACE(trace_buf); + + /* Disable LTE Coex Function in WiFi side + * (this should be on if LTE coex is required) + */ + halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8822b1ant_ltecoex_set_coex_table(btcoexist, + BT_8822B_1ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8822b1ant_ltecoex_set_coex_table(btcoexist, + BT_8822B_1ANT_CTT_BT_VS_LTE, + 0xffff); + + /* set GNT_BT to SW high */ + halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); + + /* set GNT_WL to SW low */ + halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_LOW); + + /* set Path control owner to WL at initial step */ + halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8822B_1ANT_PCO_WLSIDE); + + coex_sta->run_time_state = FALSE; + + /* Ext switch buffer mux */ + btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, + 0x3, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, + 0x8, 0x0); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + break; + case BT_8822B_1ANT_PHASE_WLANONLY_INIT: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLANONLY_INIT) **********\n"); + BTC_TRACE(trace_buf); + + /* Disable LTE Coex Function in WiFi side + * (this should be on if LTE coex is required) + */ + halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8822b1ant_ltecoex_set_coex_table(btcoexist, + BT_8822B_1ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8822b1ant_ltecoex_set_coex_table(btcoexist, + BT_8822B_1ANT_CTT_BT_VS_LTE, + 0xffff); + + /* set GNT_BT to SW Low */ + halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_LOW); + + /* Set GNT_WL to SW high */ + halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); + + /* set Path control owner to WL at initial step */ + halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8822B_1ANT_PCO_WLSIDE); + + coex_sta->run_time_state = FALSE; + + /* Ext switch buffer mux */ + btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, + 0x3, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, + 0x8, 0x0); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_WIFI; + + break; + case BT_8822B_1ANT_PHASE_WLAN_OFF: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLAN_OFF) **********\n"); + BTC_TRACE(trace_buf); + + /* Disable LTE Coex Function in WiFi side */ + halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0); + + /* set Path control owner to BT */ + halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8822B_1ANT_PCO_BTSIDE); + + /* Set Ext Ant Switch to BT control at wifi off step */ + halbtc8822b1ant_set_ext_ant_switch(btcoexist, + FORCE_EXEC, + BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT, + BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE); + + coex_sta->run_time_state = FALSE; + + break; + case BT_8822B_1ANT_PHASE_2G_RUNTIME: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_2G_RUNTIME) **********\n"); + BTC_TRACE(trace_buf); + + /* set GNT_BT to PTA */ + halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_PTA, + BT_8822B_1ANT_SIG_STA_SET_BY_HW); + + /* Set GNT_WL to PTA */ + halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_PTA, + BT_8822B_1ANT_SIG_STA_SET_BY_HW); + + /* set Path control owner to WL at runtime step */ + halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8822B_1ANT_PCO_WLSIDE); + + coex_sta->run_time_state = TRUE; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_PTA; + + break; + case BT_8822B_1ANT_PHASE_5G_RUNTIME: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_5G_RUNTIME) **********\n"); + BTC_TRACE(trace_buf); + + /* set GNT_BT to SW Hi */ + halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); + + /* Set GNT_WL to SW Hi */ + halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); + + /* set Path control owner to WL at runtime step */ + halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8822B_1ANT_PCO_WLSIDE); + + coex_sta->run_time_state = TRUE; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = + BTC_ANT_PATH_WIFI5G; + + break; + case BT_8822B_1ANT_PHASE_BTMPMODE: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_BTMPMODE) **********\n"); + BTC_TRACE(trace_buf); + + /* Disable LTE Coex Function in WiFi side */ + halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0); + + /* set GNT_BT to SW Hi */ + halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); + + /* Set GNT_WL to SW Lo */ + halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_LOW); + + /* set Path control owner to WL */ + halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8822B_1ANT_PCO_WLSIDE); + + coex_sta->run_time_state = FALSE; + + /* Set Ext Ant Switch to BT side at BT MP mode */ + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + break; + } + + + if (phase != BT_8822B_1ANT_PHASE_WLAN_OFF) { + switch (ant_pos_type) { + case BTC_ANT_PATH_WIFI: + halbtc8822b1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG); + break; + case BTC_ANT_PATH_WIFI5G + : + halbtc8822b1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA); + break; + case BTC_ANT_PATH_BT: + halbtc8822b1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT); + break; + default: + case BTC_ANT_PATH_PTA: + halbtc8822b1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA, + BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE); + break; + } + + } +#if BT_8822B_1ANT_COEX_DBG + u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (After Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", + u32tmp3, u8tmp, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); + +#endif + +} + + + +static +void halbtc8822b1ant_set_rx_gain(IN struct btc_coexist *btcoexist, + IN boolean agc_table_en) +{ + u8 rssi_adjust_val = 0; + + /* =================BB AGC Gain Table */ + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table On!\n"); + BTC_TRACE(trace_buf); + + + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + btcoexist->btc_write_1byte(btcoexist, 0xc5b, 0xc8); + btcoexist->btc_write_1byte(btcoexist, 0xe5b, 0xc8); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xff000003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xae2e0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xad300003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xac320003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xab360003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8d380003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8c3a0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8b3c0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8a3e0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6e400003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6d420003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6c440003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6b460003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6a480003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x694a0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x684c0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x674e0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x66500003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x65520003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x64540003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x64560003); + + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x007e0403); + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table Off!\n"); + BTC_TRACE(trace_buf); + + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + btcoexist->btc_write_1byte(btcoexist, 0xc5b, 0xd8); + btcoexist->btc_write_1byte(btcoexist, 0xe5b, 0xd8); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xff000003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xe62e0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xe5300003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc8320003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc6360003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc5380003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc43a0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc33c0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc23e0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc1400003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc0420003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa5440003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa4460003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa3480003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa24a0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa14c0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x834e0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x82500003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x81520003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x80540003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x65560003); + + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x007e0403); + } + + +} + + +static +void halbtc8822b1ant_rx_gain(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean agc_table_en) +{ + coex_dm->cur_agc_table_en = agc_table_en; + + if (!force_exec) { + if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) + return; + } + halbtc8822b1ant_set_rx_gain(btcoexist, agc_table_en); + + coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; +} + + +static +void halbtc8822b1ant_action_bt_idle(IN struct btc_coexist *btcoexist) +{ + + boolean wifi_busy = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (bt idle) **********\n"); + BTC_TRACE(trace_buf); + + if (!wifi_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (bt idle wl not busy) **********\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + } else { /* if wl busy */ + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + + if (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, + 8); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** else(bt non connect idle wl not busy) **********\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 12); + } + } + +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif +} + + +static +boolean halbtc8822b1ant_is_common_action(IN struct btc_coexist *btcoexist) +{ + boolean common = FALSE, wifi_connected = FALSE, wifi_busy = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_connected && + coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + + /* halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); */ + + common = TRUE; + } else if (wifi_connected && + (coex_dm->bt_status == + BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + + /* halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); */ + + common = TRUE; + } else if (!wifi_connected && + (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + + /* halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); */ + + common = TRUE; + } else if (wifi_connected && + (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + + /* halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); */ + + common = TRUE; + } else if (!wifi_connected && + (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE != + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + + /* halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); */ + + common = TRUE; + } else { + if (wifi_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } + + common = FALSE; + } + + return common; +} + + +static +void halbtc8822b1ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], under 5g start\n"); + BTC_TRACE(trace_buf); + /* for test : s3 bt disappear , fail rate 1/600*/ +#if 0 + halbtc8822b1ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, TRUE); +#endif + /*set sw gnt wl bt high*/ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, 1); + halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); +#if 0 + halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + + halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, FALSE, 5); +#endif +} + + + + +static +void halbtc8822b1ant_action_wifi_only(IN struct btc_coexist *btcoexist) +{ + boolean wifi_under_5g = FALSE, rf4ce_enabled = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + halbtc8822b1ant_action_wifi_under5g(btcoexist); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (wlan only -- under 5g ) **********\n"); + BTC_TRACE(trace_buf); + return; + } + + if (rf4ce_enabled) { + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x45e, 0x8, 0x1); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, + 50); + + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + return; + } + halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); + + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (wlan only -- under 2g ) **********\n"); + BTC_TRACE(trace_buf); + +} + +static +void halbtc8822b1ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist) +{ + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 5); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); +} + + +/* ********************************************* + * + * Non-Software Coex Mechanism start + * + * ********************************************* */ + +static +void halbtc8822b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],action_bt_whck_test\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +static +void halbtc8822b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],action_wifi_multi_port\n"); + BTC_TRACE(trace_buf); + + /*halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);*/ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 1); + halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + + + +} + + +static +void halbtc8822b1ant_action_hs(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], action_hs\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5); + + +} + +static +void halbtc8822b1ant_action_bt_relink(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], run bt multi link function\n"); + BTC_TRACE(trace_buf); + + if (coex_sta->is_bt_multi_link) + return; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], run bt_re-link function\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + +} + +#if 0 +static +void halbtc8822b1ant_action_bt_idle(IN struct btc_coexist *btcoexist) +{ + boolean wifi_busy = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_busy) { + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 6); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + + } else { /* if wl busy */ + + if (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 33); + } else { + + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 32); + + } + + } + +} +#endif + +/*"""bt inquiry"""" + wifi any + bt any*/ + +static +void halbtc8822b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = FALSE, ap_enable = FALSE, wifi_busy = FALSE, + bt_busy = FALSE, rf4ce_enabled = FALSE; + + + boolean wifi_scan = FALSE, link = FALSE, roam = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (bt inquiry) **********\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** scan = %d, link =%d, roam = %d**********\n", + wifi_scan, link, roam); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + + if ((link) || (roam) || (coex_sta->wifi_is_high_pri_task)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (bt inquiry wifi connect or scan ) **********\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 1); + + } else if ((wifi_scan) && (coex_sta->bt_create_connection)) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + + } else if ((!wifi_connected) && (!wifi_scan)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (bt inquiry wifi non connect) **********\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + + } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + + } else if (bt_link_info->a2dp_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); + + } else if (wifi_scan) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20); + + + } else if (wifi_busy) { + + /* for BT inquiry/page fail after S4 resume */ +#if 0 + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20); +#endif + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 15); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); + /*aaaa->55aa for bt connect while wl busy*/ + + if (rf4ce_enabled) { + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x45e, 0x8, 0x1); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, + 50); + } + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (bt inquiry wifi connect) **********\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 4); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + + } + +#if 0 + if ((wifi_link) || (wifi_roam) || (coex_sta->wifi_is_high_pri_task)) { + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); + + } else if ((wifi_scan) && (coex_sta->bt_create_connection)) { + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); + + } else if ((!wifi_connected) && (!wifi_scan)) { + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) { + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + } else if (bt_link_info->a2dp_exist) { + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else if (wifi_scan) { + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + } else if (wifi_busy) { + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 19); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } +#endif +} + +static +void halbtc8822b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = FALSE, wifi_busy = FALSE; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + + + if (bt_link_info->sco_exist) { + /*halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 5); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 5);*/ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, 1); + halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + + } else { + + if (coex_sta->is_hid_low_pri_tx_overhead) { + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 18); + } else if (wifi_bw == 0) { /* if 11bg mode */ + + if (coex_sta->is_bt_multi_link) { + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, 1); + halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + /*halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 11); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 11);*/ + } else { + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, 1); + halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + /*halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 11);*/ + } + } else { + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, 1); + halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + /*halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 11);*/ + } + } +} + +static +void halbtc8822b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + u32 wifi_bw = 1; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; + + if ((coex_sta->bt_relink_downcount != 0) + && (!bt_link_info->pan_exist) && (wifi_busy)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + + /*halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);*/ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, 1); + halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + + } else if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) { + /*halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 12); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6);*/ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, 1); + halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + } else if (bt_link_info->a2dp_only) { /* A2DP */ + + /*halbtc8822b1ant_ps_tdma(btcoexist, + NORMAL_EXEC, TRUE, 7); + + if (wifi_turbo) + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 19); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4);*/ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, 1); + halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + } else if (((bt_link_info->a2dp_exist) && + (bt_link_info->pan_exist)) || + (bt_link_info->hid_exist && bt_link_info->a2dp_exist && + bt_link_info->pan_exist)) { + /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ + + if (wifi_busy) + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 13); + else + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 14); + + if (bt_link_info->hid_exist) + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + else if (wifi_turbo) + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 19); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { /* HID+A2DP */ + + if (wifi_bw == 0) {/* if 11bg mode */ + /*halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 21);*/ + /*halbtc8822b1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, 1, 0x55, 0x55, 0x5a, 0x5a);*/ + /*halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, + 49);*/ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, 1); + halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + } else { + /*halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 21);*/ + /*halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, + TRUE, 8);*/ + /*halbtc8822b1ant_set_wltoggle_coex_table(btcoexist, + NORMAL_EXEC, 1, 0x55, 0x55, 0x5a, 0x5a);*/ + /*halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, + 49);*/ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, 1); + halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + } + /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ + + } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && bt_link_info->pan_exist)) { + + if (!wifi_busy) + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 4); + else + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 3); + + if (bt_link_info->hid_exist) + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + else if (wifi_turbo) + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 19); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else { + /* BT no-profile busy (0x9) */ + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33); + } + +} + + +/*wifi not connected + bt action*/ + +static +void halbtc8822b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +{ + boolean rf4ce_enabled = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (wifi not connect) **********\n"); + BTC_TRACE(trace_buf); + + /* tdma and coex table */ + if (rf4ce_enabled) { + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x45e, 0x8, 0x1); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, + 50); + return; + } + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); +} + +/*""""wl not connected scan"""" + bt action*/ +static +void halbtc8822b1ant_action_wifi_not_connected_scan(IN struct btc_coexist + *btcoexist) +{ + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = FALSE; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = FALSE; + u8 agg_buf_size = 5; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (wifi non connect scan) **********\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + + num_of_wifi_link = wifi_link_status >> 16; + + if (num_of_wifi_link >= 2) { + halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, + bt_ctrl_agg_buf_size, agg_buf_size); + + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is Inquirying\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_bt_inquiry(btcoexist); + } else { + halbtc8822b1ant_action_wifi_multi_port(btcoexist); + } + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8822b1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8822b1ant_action_hs(btcoexist); + return; + } + /* tdma and coex table */ + if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + if (bt_link_info->a2dp_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 32); + } else if (bt_link_info->a2dp_exist && + bt_link_info->pan_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 22); + } else { + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 20); + } + } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist); + } else { + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 5); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + } +} + +/*""""wl not connected asso"""" + bt action*/ + +static +void halbtc8822b1ant_action_wifi_not_connected_asso_auth( + IN struct btc_coexist *btcoexist) +{ + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = FALSE; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = FALSE; + u8 agg_buf_size = 5; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (wifi non connect asso_auth) **********\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + + num_of_wifi_link = wifi_link_status >> 16; + + if (num_of_wifi_link >= 2) { + + halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, + bt_ctrl_agg_buf_size, + agg_buf_size); + + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is Inquirying\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_bt_inquiry(btcoexist); + } else { + halbtc8822b1ant_action_wifi_multi_port( + btcoexist); + } + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8822b1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8822b1ant_action_hs(btcoexist); + return; + } + + + /* tdma and coex table */ + if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || + (bt_link_info->a2dp_exist)) { + halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); + + } else if (bt_link_info->pan_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20); + + } else { + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + + + } +} + +/*""""wl connected scan"""" + bt action*/ + +static +void halbtc8822b1ant_action_wifi_connected_scan(IN struct btc_coexist + *btcoexist) +{ + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = FALSE; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = FALSE; + u8 agg_buf_size = 5; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (wifi connect scan) **********\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + + num_of_wifi_link = wifi_link_status >> 16; + + if (num_of_wifi_link >= 2) { + halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, + bt_ctrl_agg_buf_size, agg_buf_size); + + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is Inquirying\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_bt_inquiry(btcoexist); + } else { + halbtc8822b1ant_action_wifi_multi_port(btcoexist); + } + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8822b1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8822b1ant_action_hs(btcoexist); + return; + } + + /* tdma and coex table */ + if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + if (bt_link_info->a2dp_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 32); + } else if (bt_link_info->a2dp_exist && + bt_link_info->pan_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 22); + + } else { + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 20); + } + } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist); + } else { +#if 0 + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); +#endif + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 1); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20); +#if 0 + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 6); +#endif + + } +} + +/*""""wl connected specific packet"""" + bt action*/ + +static +void halbtc8822b1ant_action_wifi_connected_specific_packet( + IN struct btc_coexist *btcoexist) +{ + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = FALSE; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = FALSE; + u8 agg_buf_size = 5; + boolean wifi_busy = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (wifi connect specific packet) **********\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + + num_of_wifi_link = wifi_link_status >> 16; + + if (num_of_wifi_link >= 2) { + halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, + bt_ctrl_agg_buf_size, agg_buf_size); + + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is Inquirying\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_bt_inquiry(btcoexist); + } else { + halbtc8822b1ant_action_wifi_multi_port(btcoexist); + } + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + halbtc8822b1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8822b1ant_action_hs(btcoexist); + return; + } + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + /* no specific packet process for both WiFi and BT very busy */ + if ((wifi_busy) && ((bt_link_info->pan_exist) || + (coex_sta->num_of_profile >= 2))) + return; + + /* tdma and coex table */ + if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); + + } else if (bt_link_info->a2dp_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 15); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); + /*for a2dp glitch,change from 1 to 15*/ + + } else if (bt_link_info->pan_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20); + + } else { + + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 5); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + + } +} + +static +void halbtc8822b1ant_action_a2dpsink(IN struct btc_coexist *btcoexist) +{ + + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0xcbd, 0x3, 1); + halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + +} + +/* wifi connected input point: + * to set different ps and tdma case (+bt different case) + */ + +static +void halbtc8822b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +{ + + boolean wifi_busy = FALSE, rf4ce_enabled = FALSE; + boolean scan = FALSE, link = FALSE, roam = FALSE; + boolean under_4way = FALSE, ap_enable = FALSE, wifi_under_5g = FALSE; + u8 wifi_rssi_state; + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect()===>\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect(), return for wifi is under 5g<===\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_action_wifi_under5g(btcoexist); + + return; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect(), return for wifi is under 2g<===\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (under_4way) { + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_action_wifi_connected_specific_packet( + btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + if (scan || link || roam) { + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + if (scan) + halbtc8822b1ant_action_wifi_connected_scan(btcoexist); + else + halbtc8822b1ant_action_wifi_connected_specific_packet( + btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + /* tdma and coex table */ + if (!wifi_busy) { + if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + halbtc8822b1ant_action_wifi_connected_bt_acl_busy( + btcoexist); + } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist); + } else { + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, + 8); + + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + if ((coex_sta->high_priority_tx) + + (coex_sta->high_priority_rx) <= 60) + /*sy modify case16 -> case17*/ + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + } + } else { + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + halbtc8822b1ant_action_wifi_connected_bt_acl_busy( + btcoexist); + } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) { + halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist); + } else { + if (rf4ce_enabled) { + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x45e, 0x8, 0x1); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, + 50); + return; + } + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, + 8); + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + +#if 0 + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 32); + + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, NORMAL_EXEC, BT_8822B_1ANT_PHASE_2G_RUNTIME); +#endif + + + + wifi_rssi_state = halbtc8822b1ant_wifi_rssi_state( + btcoexist, 1, 2, 25, 0); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** before **********\n"); + BTC_TRACE(trace_buf); +#if 0 + if ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) && + (coex_sta->scan_ap_num <= 3) && + (wifi_rssi_state == BTC_RSSI_STATE_LOW || + wifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { +#endif + if (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + if (rf4ce_enabled) { + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x45e, 0x8, 0x1); + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, + 50); + return; + } + + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + } else + + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); +#if 0 + else if ((coex_sta->high_priority_tx + + coex_sta->high_priority_rx) <= 60) + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); +#endif + } + } +} + +static +void halbtc8822b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + + u8 algorithm = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (run sw coexmech) **********\n"); + BTC_TRACE(trace_buf); + algorithm = halbtc8822b1ant_action_algorithm(btcoexist); + coex_dm->cur_algorithm = algorithm; + + if (halbtc8822b1ant_is_common_action(btcoexist)) { + + } else { + switch (coex_dm->cur_algorithm) { + case BT_8822B_1ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = SCO.\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8822b1ant_action_sco(btcoexist); +#endif + break; + case BT_8822B_1ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID.\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8822b1ant_action_hid(btcoexist); +#endif + break; + case BT_8822B_1ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8822b1ant_action_a2dp(btcoexist); +#endif + break; + case BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8822b1ant_action_a2dp_pan_hs(btcoexist); +#endif + break; + case BT_8822B_1ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8822b1ant_action_pan_edr(btcoexist); +#endif + break; + case BT_8822B_1ANT_COEX_ALGO_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HS mode.\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8822b1ant_action_pan_hs(btcoexist); +#endif + break; + case BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8822b1ant_action_pan_edr_a2dp(btcoexist); +#endif + break; + case BT_8822B_1ANT_COEX_ALGO_A2DPSINK: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP Sink.\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_a2dpsink(btcoexist); + break; + + case BT_8822B_1ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8822b1ant_action_pan_edr_hid(btcoexist); +#endif + break; + case BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8822b1ant_action_hid_a2dp_pan_edr(btcoexist); +#endif + break; + case BT_8822B_1ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8822b1ant_action_hid_a2dp(btcoexist); +#endif + break; + case BT_8822B_1ANT_COEX_ALGO_NOPROFILEBUSY: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_bt_idle(btcoexist); + break; + + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8822b1ant_coex_all_off(btcoexist); +#endif + break; + } + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + } +} + +static +void halbtc8822b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = FALSE, bt_hs_on = FALSE; + boolean increase_scan_dev_num = FALSE; + boolean bt_ctrl_agg_buf_size = FALSE; + boolean miracast_plus_bt = FALSE; + u8 agg_buf_size = 5; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0, wifi_bw; + u8 iot_peer = BTC_IOT_PEER_UNKNOWN; + boolean wifi_under_5g = FALSE; + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if ((coex_sta->under_lps) && + (coex_dm->bt_status != BT_8822B_1ANT_BT_STATUS_ACL_BUSY)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_wifi_native_lps(btcoexist); + return; + } + + if (!coex_sta->run_time_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], return for run_time_state = FALSE !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->freeze_coexrun_by_btinfo) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + halbtc8822b1ant_action_wifi_under5g(btcoexist); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + return; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 2G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + if (coex_sta->bt_whck_test) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under WHCK TEST!!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_bt_whck_test(btcoexist); + return; + } + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_action_wifi_only(btcoexist); + return; + } + + if (coex_sta->is_setupLink) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is re-link !!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_bt_relink(btcoexist); + return; + } + + if ((BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + increase_scan_dev_num = TRUE; + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + + btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, + &increase_scan_dev_num); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", + num_of_wifi_link, wifi_link_status); + BTC_TRACE(trace_buf); + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + + if (bt_link_info->bt_link_exist) { + halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, + 0, 1); + miracast_plus_bt = TRUE; + } else { + halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, + 0, 0); + miracast_plus_bt = FALSE; + } + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, + bt_ctrl_agg_buf_size, agg_buf_size); + + if ((bt_link_info->a2dp_exist) && + (coex_sta->c2h_bt_inquiry_page)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is Inquirying\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_bt_inquiry(btcoexist); + } else { + halbtc8822b1ant_action_wifi_multi_port(btcoexist); + } + + return; + } + + miracast_plus_bt = FALSE; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if ((bt_link_info->bt_link_exist) && (wifi_connected)) { + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); + + if (BTC_IOT_PEER_CISCO != iot_peer) { +#if 0 + if (bt_link_info->bt_hi_pri_link_exist) +#endif + if (bt_link_info->sco_exist) + halbtc8822b1ant_limited_rx(btcoexist, + NORMAL_EXEC, TRUE, FALSE, 0x5); + else + halbtc8822b1ant_limited_rx(btcoexist, + NORMAL_EXEC, FALSE, FALSE, 0x5); + } else { + halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + if (bt_link_info->sco_exist) + halbtc8822b1ant_limited_rx(btcoexist, + NORMAL_EXEC, TRUE, FALSE, 0x5); + else { + if (BTC_WIFI_BW_HT40 == wifi_bw) + halbtc8822b1ant_limited_rx(btcoexist, + NORMAL_EXEC, FALSE, TRUE, 0x10); + else + halbtc8822b1ant_limited_rx(btcoexist, + NORMAL_EXEC, FALSE, TRUE, 0x8); + } + } + + halbtc8822b1ant_sw_mechanism(btcoexist, TRUE); + halbtc8822b1ant_run_sw_coexist_mechanism( + btcoexist); /* just print debug message */ + } else { + halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); + + halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, FALSE, + 0x5); + + halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); + halbtc8822b1ant_run_sw_coexist_mechanism( + btcoexist); /* just print debug message */ + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is Inquirying\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_bt_inquiry(btcoexist); + return; + } else if (bt_hs_on) { + halbtc8822b1ant_action_hs(btcoexist); + return; + } + + + if (!wifi_connected) { + boolean scan = FALSE, link = FALSE, roam = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is non connected-idle !!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + if (scan) + halbtc8822b1ant_action_wifi_not_connected_scan( + btcoexist); + else if (link || roam) + halbtc8822b1ant_action_wifi_not_connected_asso_auth( + btcoexist); + else + halbtc8822b1ant_action_wifi_not_connected(btcoexist); + } else /* wifi LPS/Busy */ + halbtc8822b1ant_action_wifi_connected(btcoexist); +} + +static +void halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + /* force to reset coex mechanism */ + + halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); + + /* sw all off */ + halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); + +#if 0 + halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); + halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); +#endif + + coex_sta->pop_event_cnt = 0; +} + +static +void halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean back_up, IN boolean wifi_only) +{ + + u8 u8tmp = 0, i = 0; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", + u32tmp3, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 1Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + coex_sta->isolation_btween_wb = BT_8822B_1ANT_DEFAULT_ISOLATION; + coex_sta->gnt_error_cnt = 0; + coex_sta->bt_relink_downcount = 0; + coex_sta->is_set_ps_state_fail = FALSE; + coex_sta->cnt_set_ps_state_fail = 0; + + for (i = 0; i <= 9; i++) + coex_sta->bt_afh_map[i] = 0; + + /* Setup RF front end type */ + halbtc8822b1ant_set_rfe_type(btcoexist); + + /* 0xf0[15:12] --> Chip Cut information */ + coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, + 0xf1) & 0xf0) >> 4; + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + + /* BT report packet sample rate */ + /* 0x790[5:0]=0x5 */ + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); + u8tmp &= 0xc0; + u8tmp |= 0x5; + btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); + + /* Enable BT counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + + /* Enable PTA (3-wire function form BT side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); + + /* Enable PTA (tx/rx signal form WiFi side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); + /*GNT_BT=1 while select both */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1); + +#if 0 + /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); +#endif + + /* enable GNT_WL */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0); + + if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ONOFF, TRUE); + + /* Antenna config */ + if (coex_sta->is_rf_state_off) { + + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_WLAN_OFF); + + btcoexist->stop_coex_dm = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** halbtc8822b1ant_init_hw_config (RF Off)**********\n"); + BTC_TRACE(trace_buf); + } else if (wifi_only) { + + coex_sta->concurrent_rx_mode_on = FALSE; + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_WIFI, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_WLANONLY_INIT); + } else { + + coex_sta->concurrent_rx_mode_on = TRUE; + + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_COEX_INIT); + } + + /* PTA parameter */ + halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, TRUE); + +} + +#if (BTC_COEX_OFFLOAD == 1) +void halbtc8822b1ant_wifi_info_notify(IN struct btc_coexist *btcoexist) +{ + u8 h2c_para[4] = {0}; + u8 opcode_ver = 0; + u8 ap_num = 0; + s32 wifi_rssi = 0; + boolean wifi_busy = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + h2c_para[0] = ap_num; /* AP number */ + h2c_para[1] = (u8)wifi_busy; /* Busy */ + h2c_para[2] = (u8)wifi_rssi; /* RSSI */ + + btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_INFO_NOTIFY, + opcode_ver, &h2c_para[0], 3); +} + +void halbtc8822b1ant_setManual(IN struct btc_coexist *btcoexist, + IN boolean manual) +{ + u8 h2c_para[4] = {0}; + u8 opcode_ver = 0; + u8 set_type = 0; + + if (manual) + set_type = 1; + else + set_type = 0; + + h2c_para[0] = set_type; /* set_type */ + + btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_SET_CONTROL, + opcode_ver, + &h2c_para[0], 1); +} + +/* ************************************************************ + * work around function start with wa_halbtc8822b1ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8822b1ant_ + * ************************************************************ */ + +void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ + coex_sta->is_rf_state_off = FALSE; + +} +void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{} +void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{} +static +void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{} +void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + u8 h2c_para[4] = {0}; + u8 opcode_ver = 0; + u8 ips_notify = 0; + + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + ips_notify = 1; + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + } + + h2c_para[0] = ips_notify; /* IPS notify */ + h2c_para[1] = 0xff; /* LPS notify */ + h2c_para[2] = 0xff; /* RF state notify */ + h2c_para[3] = 0xff; /* pnp notify */ + + btcoexist->btc_coex_h2c_process(btcoexist, + COL_OP_WIFI_POWER_STATE_NOTIFY, + opcode_ver, &h2c_para[0], 4); +} +void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + u8 h2c_para[4] = {0}; + u8 opcode_ver = 0; + u8 lps_notify = 0; + + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + lps_notify = 1; + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + } + + h2c_para[0] = 0xff; /* IPS notify */ + h2c_para[1] = lps_notify; /* LPS notify */ + h2c_para[2] = 0xff; /* RF state notify */ + h2c_para[3] = 0xff; /* pnp notify */ + + btcoexist->btc_coex_h2c_process(btcoexist, + COL_OP_WIFI_POWER_STATE_NOTIFY, + opcode_ver, &h2c_para[0], 4); +} + +void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_para[4] = {0}; + u8 opcode_ver = 0; + u8 scan_start = 0; + boolean under_4way = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + if (BTC_SCAN_START == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify\n"); + BTC_TRACE(trace_buf); + scan_start = 1; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify\n"); + BTC_TRACE(trace_buf); + } + + h2c_para[0] = scan_start; /* scan notify */ + h2c_para[1] = 0xff; /* connect notify */ + h2c_para[2] = 0xff; /* specific packet notify */ + if (under_4way) + h2c_para[3] = 1; /* under 4way progress */ + else + h2c_para[3] = 0; + + btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY, + opcode_ver, &h2c_para[0], 4); +} + +void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_para[4] = {0}; + u8 opcode_ver = 0; + u8 connect_start = 0; + boolean under_4way = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + if (BTC_ASSOCIATE_START == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify\n"); + BTC_TRACE(trace_buf); + connect_start = 1; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify\n"); + BTC_TRACE(trace_buf); + } + + h2c_para[0] = 0xff; /* scan notify */ + h2c_para[1] = connect_start; /* connect notify */ + h2c_para[2] = 0xff; /* specific packet notify */ + if (under_4way) + h2c_para[3] = 1; /* under 4way progress */ + else + h2c_para[3] = 0; + + btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY, + opcode_ver, &h2c_para[0], 4); +} + +void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u32 wifi_bw; + u8 wifi_central_chnl; + u8 h2c_para[5] = {0}; + u8 opcode_ver = 0; + u8 port = 0, connected = 0, freq = 0, bandwidth = 0, iot_peer = 0; + boolean wifi_under_5g = FALSE; + + if (BTC_MEDIA_CONNECT == type) + connected = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + bandwidth = (u8)wifi_bw; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) + freq = 1; + else + freq = 0; + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); + + /* port need to be implemented in the future (p2p port, ...) */ + h2c_para[0] = (connected << 4) | port; + h2c_para[1] = (freq << 4) | bandwidth; + h2c_para[2] = wifi_central_chnl; + h2c_para[3] = iot_peer; + btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_STATUS_NOTIFY, + opcode_ver, &h2c_para[0], 4); +} + +void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_para[4] = {0}; + u8 opcode_ver = 0; + u8 connect_start = 0; + boolean under_4way = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + h2c_para[0] = 0xff; /* scan notify */ + h2c_para[1] = 0xff; /* connect notify */ + h2c_para[2] = type; /* specific packet notify */ + if (under_4way) + h2c_para[3] = 1; /* under 4way progress */ + else + h2c_para[3] = 0; + + btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY, + opcode_ver, &h2c_para[0], 4); +} + +void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{} +void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_para[4] = {0}; + u8 opcode_ver = 0; + u8 rfstate_notify = 0; + + if (BTC_RF_ON == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned ON!!\n"); + BTC_TRACE(trace_buf); + rfstate_notify = 1; + coex_sta->is_rf_state_off = FALSE; + } else if (BTC_RF_OFF == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned OFF!!\n"); + BTC_TRACE(trace_buf); + coex_sta->is_rf_state_off = TRUE; + } + + h2c_para[0] = 0xff; /* IPS notify */ + h2c_para[1] = 0xff; /* LPS notify */ + h2c_para[2] = rfstate_notify; /* RF state notify */ + h2c_para[3] = 0xff; /* pnp notify */ + + btcoexist->btc_coex_h2c_process(btcoexist, + COL_OP_WIFI_POWER_STATE_NOTIFY, + opcode_ver, &h2c_para[0], 4); +} + +void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist) +{} +void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + u8 h2c_para[4] = {0}; + u8 opcode_ver = 0; + u8 pnp_notify = 0; + + if (BTC_WIFI_PNP_SLEEP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + pnp_notify = 1; + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); + } + + h2c_para[0] = 0xff; /* IPS notify */ + h2c_para[1] = 0xff; /* LPS notify */ + h2c_para[2] = 0xff; /* RF state notify */ + h2c_para[3] = pnp_notify; /* pnp notify */ + + btcoexist->btc_coex_h2c_process(btcoexist, + COL_OP_WIFI_POWER_STATE_NOTIFY, + opcode_ver, &h2c_para[0], 4); +} + +void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) +{} +void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist) +{ + + halbtc8822b1ant_wifi_info_notify(btcoexist); +} + +void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_stack_info *stack_info = &btcoexist->stack_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u16 u16tmp[4]; + u32 u32tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + static u8 pop_report_in_10s = 0; + u32 phyver = 0; + boolean lte_coex_on = FALSE; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + if (btcoexist->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + if (psd_scan->ant_det_try_count == 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s / %d", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, board_info->btdm_ant_num, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type); + CL_PRINTF(cli_buf); + } else { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", + "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", + board_info->pg_ant_num, + board_info->btdm_ant_num_by_ant_det, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type, + psd_scan->ant_det_try_count, + psd_scan->ant_det_fail_count, + psd_scan->ant_det_result); + CL_PRINTF(cli_buf); + + if (board_info->btdm_ant_det_finish) { + if (psd_scan->ant_det_result != 12) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "Ant Det PSD Value", + psd_scan->ant_det_peak_val); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d", + "Ant Det PSD Value", + psd_scan->ant_det_psd_scan_peak_val / 100); + + CL_PRINTF(cli_buf); + } + } + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)", + "CoexVer/ FwVer/ PatchVer", + glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant, fw_ver, + bt_patch_ver, bt_patch_ver); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "Wifi channel informed to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", + "WifibHiPri/ Ccklock/ CckEverLock", + (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + (coex_sta->cck_lock ? "Yes" : "No"), + (coex_sta->cck_ever_lock ? "Yes" : "No")); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + pop_report_in_10s++; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", + "BT [status/ rssi/ retryCnt/ popCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") + : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, + coex_sta->pop_event_cnt); + CL_PRINTF(cli_buf); + + if (pop_report_in_10s >= 5) { + coex_sta->pop_event_cnt = 0; + pop_report_in_10s = 0; + } + + if (coex_sta->num_of_profile != 0) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s%s%s%s%s", + "Profiles", + ((bt_link_info->a2dp_exist) ? "A2DP," : ""), + ((bt_link_info->sco_exist) ? "SCO," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : "HID(2/18),") : ""), + ((bt_link_info->pan_exist) ? "PAN," : ""), + ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = None", "Profiles"); + + CL_PRINTF(cli_buf); + + if (bt_link_info->a2dp_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", + "A2DP Rate/Bitpool/Auto_Slot", + ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), + coex_sta->a2dp_bit_pool, + ((coex_sta->is_autoslot) ? "On" : "Off")); + CL_PRINTF(cli_buf); + } + + if (bt_link_info->hid_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "HID PairNum/Forbid_Slot", + coex_sta->hid_pair_cnt, + coex_sta->forbidden_slot + ); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ 0x%x/ 0x%x", + "Role/IgnWlanAct/Feature/BLEScan", + ((bt_link_info->slave_role) ? "Slave" : "Master"), + ((coex_dm->cur_ignore_wlan_act) ? "Yes":"No"), + coex_sta->bt_coex_supported_feature, + coex_sta->bt_ble_scan_type); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "ReInit/ReLink/IgnWlact/Page/NameReq", + coex_sta->cnt_ReInit, + coex_sta->cnt_setupLink, + coex_sta->cnt_IgnWlanAct, + coex_sta->cnt_Page, + coex_sta->cnt_RemoteNameReq + ); + CL_PRINTF(cli_buf); + + halbtc8822b1ant_read_score_board(btcoexist, &u16tmp[0]); + + if ((coex_sta->bt_reg_vendor_ae == 0xffff) || + (coex_sta->bt_reg_vendor_ac == 0xffff)) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", + ((coex_sta->bt_reg_vendor_ae & BIT(4))>>4), + coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); + CL_PRINTF(cli_buf); + + for (i = 0; i < BT_INFO_SRC_8822B_1ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8822b_1ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + + if (btcoexist->manual_control) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanisms] (before Manual)============"); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanisms]============"); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "SM[LowPenaltyRA]", + coex_dm->cur_low_penalty_ra); + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", + "PS TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + (coex_dm->cur_ps_tdma_on ? "On" : "Off"), + (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); + + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "WL/BT Coex Table Type", + coex_sta->coex_table_type); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x6c0/0x6c4/0x6c8(coexTable)", + u32tmp[0], u32tmp[1], u32tmp[2]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", + "0x778/0x6cc/IgnWlanAct", + u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa0); + u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "LTE Coex Table W_L/B_L", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa8); + u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xac); + u32tmp[2] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xb0); + u32tmp[3] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xb4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "LTE Break Table W_L/B_L/L_W/L_B", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, + u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); + CL_PRINTF(cli_buf); + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); +#if 0 + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); + u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", + "0x430/0x434/0x42a/0x456", + u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); + CL_PRINTF(cli_buf); +#endif + + u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s", + "LTE CoexOn/Path Ctrl Owner", + (int)((u32tmp[0]&BIT(7)) >> 7), + ((u8tmp[0]&BIT(2)) ? "WL" : "BT")); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "LTE 3Wire/OPMode/UART/UARTMode", + (int)((u32tmp[0]&BIT(6)) >> 6), + (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), + (int)((u32tmp[0]&BIT(3)) >> 3), + (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s", + "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg", + (int)((u32tmp[0]&BIT(12)) >> 12), + (int)((u32tmp[0]&BIT(14)) >> 14), + ((u8tmp[0]&BIT(3)) ? "On" : "Off")); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "GNT_WL/GNT_BT/LTE_Busy/UART_Busy", + (int)((u32tmp[0]&BIT(2)) >> 2), + (int)((u32tmp[0]&BIT(3)) >> 3), + (int)((u32tmp[0]&BIT(1)) >> 1), (int)(u32tmp[0]&BIT(0))); + CL_PRINTF(cli_buf); + + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "0x4c6[4]/0x40[5] (WL/BT PTA)", + (int)((u8tmp[0] & BIT(4)) >> 4), + (int)((u8tmp[1] & BIT(5)) >> 5)); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s", + "0x550(bcn ctrl)/0x522/4-RxAGC", + u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off"); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8); + u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c); + + fa_ofdm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000) + >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) + + ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] & + 0xffff); + fa_cck = (u8tmp[0] << 8) + u8tmp[1]; + + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xc50); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "0xc50/OFDM-CCA/OFDM-FA/CCK-FA", + u32tmp[1] & 0xff, u32tmp[0] & 0xffff, fa_ofdm, fa_cck); + CL_PRINTF(cli_buf); + + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11n-Agg", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_Err CCK/11g/11n/11n-Agg", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(high-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x774(low-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx); + CL_PRINTF(cli_buf); +#if (BT_AUTO_REPORT_ONLY_8822B_1ANT == 1) + /* halbtc8822b1ant_monitor_bt_ctr(btcoexist); */ +#endif + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} +void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{} +void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist) +{} +void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist, + IN u8 op_code, IN u8 op_len, IN u8 *pdata) +{ + switch (op_code) { + case BTC_DBG_SET_COEX_MANUAL_CTRL: { + boolean manual = (boolean) *pdata; + + halbtc8822b1ant_setManual(btcoexist, manual); + } + break; + default: + break; + } +} + +#else +void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x0; + u16 u16tmp = 0x0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx Execute 8822b 1-Ant PowerOn Setting!! xxxxxxxxxxxxxxxx\n"); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "Ant Det Finish = %s, Ant Det Number = %d\n", + board_info->btdm_ant_det_finish ? "Yes" : "No", + board_info->btdm_ant_num_by_ant_det); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = TRUE; + + /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ + u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); + btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); + + /* set Path control owner to WiFi */ + halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8822B_1ANT_PCO_WLSIDE); + + /* set GNT_BT to high */ + halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to low */ + halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_LOW); + + /* set WLAN_ACT = 0 */ + /* btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); */ + + /* SD1 Chunchu red x issue */ + btcoexist->btc_write_1byte(btcoexist, 0xff1a, 0x0); + + halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, TRUE); + + /* */ + /* S0 or S1 setting and Local register setting + * (By the setting fw can get ant number, S0/S1, ... info) + */ + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> + * BIT1=0 and BIT2=0 + */ + + u8tmp = 0; + board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; + + if (btcoexist->chip_interface == BTC_INTF_USB) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); + + BTC_TRACE(trace_buf); + + +} + +void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{ +} + +void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (ini hw config) **********\n"); + + halbtc8822b1ant_init_hw_config(btcoexist, TRUE, wifi_only); + btcoexist->stop_coex_dm = FALSE; +} + +void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = FALSE; + + halbtc8822b1ant_init_coex_dm(btcoexist); + + halbtc8822b1ant_query_bt_info(btcoexist); +} + + +void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, ps_tdma_case = 0; + u16 u16tmp[4]; + u32 u32tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + static u8 pop_report_in_10s = 0; + u32 phyver = 0; + boolean lte_coex_on = FALSE; + static u8 cnt = 0; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + if (btcoexist->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->bt_coex_supported_feature == 0) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + if (coex_sta->bt_reg_vendor_ac == 0xffff) + coex_sta->bt_reg_vendor_ac = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xac) & 0xffff); + + if (coex_sta->bt_reg_vendor_ae == 0xffff) + coex_sta->bt_reg_vendor_ae = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xae) & 0xffff); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, + &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) { + cnt++; + + if (cnt >= 3) { + btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, + &coex_sta->bt_afh_map[0]); + cnt = 0; + } + } + } + + if (psd_scan->ant_det_try_count == 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s / %d", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, board_info->btdm_ant_num, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type); + CL_PRINTF(cli_buf); + } else { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", + "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", + board_info->pg_ant_num, + board_info->btdm_ant_num_by_ant_det, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type, + psd_scan->ant_det_try_count, + psd_scan->ant_det_fail_count, + psd_scan->ant_det_result); + CL_PRINTF(cli_buf); + + if (board_info->btdm_ant_det_finish) { + + if (psd_scan->ant_det_result != 12) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", + "Ant Det PSD Value", + psd_scan->ant_det_peak_val); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d", + "Ant Det PSD Value", + psd_scan->ant_det_psd_scan_peak_val + / 100); + CL_PRINTF(cli_buf); + } + } + + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + + bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant, + glcoex_ver_btdesired_8822b_1ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8822b_1ant ? + "Match" : "Mis-Match")))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "AFH Map to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + pop_report_in_10s++; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", + "BT [status/ rssi/ retryCnt/ popCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, + coex_sta->pop_event_cnt); + CL_PRINTF(cli_buf); + + if (pop_report_in_10s >= 5) { + coex_sta->pop_event_cnt = 0; + pop_report_in_10s = 0; + } + + if (coex_sta->num_of_profile != 0) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s%s%s%s%s", + "Profiles", + ((bt_link_info->a2dp_exist) ? + ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," : + "A2DP,") : ""), + ((bt_link_info->sco_exist) ? "HFP," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : + "HID(2/18),") : ""), + ((bt_link_info->pan_exist) ? "PAN," : ""), + ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = None", "Profiles"); + + CL_PRINTF(cli_buf); + + if (bt_link_info->a2dp_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", + "A2DP Rate/Bitpool/Auto_Slot", + ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), + coex_sta->a2dp_bit_pool, + ((coex_sta->is_autoslot) ? "On" : "Off") + ); + CL_PRINTF(cli_buf); + } + + if (bt_link_info->hid_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "HID PairNum/Forbid_Slot", + coex_sta->hid_pair_cnt, + coex_sta->forbidden_slot + ); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x", + "Role/RoleSwCnt/IgnWlact/Feature", + ((bt_link_info->slave_role) ? "Slave" : "Master"), + coex_sta->cnt_RoleSwitch, + ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), + coex_sta->bt_coex_supported_feature); + CL_PRINTF(cli_buf); + + if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "BLEScan Type/TV/Init/Ble", + coex_sta->bt_ble_scan_type, + (coex_sta->bt_ble_scan_type & 0x1 ? + coex_sta->bt_ble_scan_para[0] : 0x0), + (coex_sta->bt_ble_scan_type & 0x2 ? + coex_sta->bt_ble_scan_para[1] : 0x0), + (coex_sta->bt_ble_scan_type & 0x4 ? + coex_sta->bt_ble_scan_para[2] : 0x0)); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "ReInit/ReLink/IgnWlact/Page/NameReq", + coex_sta->cnt_ReInit, + coex_sta->cnt_setupLink, + coex_sta->cnt_IgnWlanAct, + coex_sta->cnt_Page, + coex_sta->cnt_RemoteNameReq + ); + CL_PRINTF(cli_buf); + + halbtc8822b1ant_read_score_board(btcoexist, &u16tmp[0]); + + if ((coex_sta->bt_reg_vendor_ae == 0xffff) || + (coex_sta->bt_reg_vendor_ac == 0xffff)) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", + (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), + coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); + CL_PRINTF(cli_buf); + + if (coex_sta->num_of_profile > 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + "AFH MAP", + coex_sta->bt_afh_map[0], + coex_sta->bt_afh_map[1], + coex_sta->bt_afh_map[2], + coex_sta->bt_afh_map[3], + coex_sta->bt_afh_map[4], + coex_sta->bt_afh_map[5], + coex_sta->bt_afh_map[6], + coex_sta->bt_afh_map[7], + coex_sta->bt_afh_map[8], + coex_sta->bt_afh_map[9] + ); + CL_PRINTF(cli_buf); + } + + for (i = 0; i < BT_INFO_SRC_8822B_1ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8822b_1ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + + if (btcoexist->manual_control) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanisms] (before Manual)============"); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Mechanisms]============"); + + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s)", + "TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off")); + + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", + "Table/0x6c0/0x6c4/0x6c8", + coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x", + "0x778/0x6cc", + u8tmp[0], u32tmp[0]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "AntDiv/BtCtrlLPS/LPRA/PsFail", + ((board_info->ant_div_cfg) ? "On" : "Off"), + ((coex_sta->force_lps_ctrl) ? "On" : "Off"), + ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"), + coex_sta->cnt_set_ps_state_fail); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? TRUE : FALSE; + + if (lte_coex_on) { + + u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa0); + u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "LTE Coex Table W_L/B_L", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa8); + u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xac); + u32tmp[2] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xb0); + u32tmp[3] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, + 0xb4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "LTE Break Table W_L/B_L/L_W/L_B", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, + u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); + CL_PRINTF(cli_buf); + } + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", + "LTE Coex/Path Owner", + ((lte_coex_on) ? "On" : "Off"), + ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); + CL_PRINTF(cli_buf); + + if (lte_coex_on) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %d/ %d", + "LTE 3Wire/OPMode/UART/UARTMode", + (int)((u32tmp[0] & BIT(6)) >> 6), + (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), + (int)((u32tmp[0] & BIT(3)) >> 3), + (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "LTE_Busy/UART_Busy", + (int)((u32tmp[1] & BIT(1)) >> 1), + (int)(u32tmp[1] & BIT(0))); + CL_PRINTF(cli_buf); + } + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", + ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), + ((u8tmp[0] & BIT(3)) ? "On" : "Off"), + coex_sta->gnt_error_cnt); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "GNT_WL/GNT_BT", + (int)((u32tmp[1] & BIT(2)) >> 2), + (int)((u32tmp[1] & BIT(3)) >> 3)); + CL_PRINTF(cli_buf); + + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s", + "0xcb0/0xcb4/0xcb8[23:16]", + u32tmp[0], u32tmp[1], u8tmp[0], + ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "4c[24:23]/64[0]/4c6[4]/40[5]", + (int)((u32tmp[0] & (BIT(24) | BIT(23))) >> 23), + u8tmp[2] & 0x1, + (int)((u8tmp[0] & BIT(4)) >> 4), + (int)((u8tmp[1] & BIT(5)) >> 5)); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x", + "0x550/0x522/4-RxAGC/0xc50", + u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_CCK); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); + CL_PRINTF(cli_buf); + + +#if 1 + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11ac", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_Err CCK/11g/11n/11ac", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); + CL_PRINTF(cli_buf); +#endif + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "WlHiPri/ Locking/ Locked/ Noisy", + (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + (coex_sta->cck_lock ? "Yes" : "No"), + (coex_sta->cck_ever_lock ? "Yes" : "No"), + coex_sta->wl_noisy_level); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : ( + coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); + CL_PRINTF(cli_buf); + + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + +void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + + if (BTC_IPS_ENTER == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = TRUE; + + /* Write WL "Active" in Score-board for LPS off */ + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE, FALSE); + + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ONOFF, FALSE); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_WLAN_OFF); + + + } else if (BTC_IPS_LEAVE == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE, TRUE); + + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ONOFF, TRUE); + + /*leave IPS : run ini hw config (exclude wifi only)*/ + halbtc8822b1ant_init_hw_config(btcoexist, FALSE, FALSE); + /*sw all off*/ + halbtc8822b1ant_init_coex_dm(btcoexist); + /*leave IPS : Query bt info*/ + halbtc8822b1ant_query_bt_info(btcoexist); + + coex_sta->under_ips = FALSE; + } +} + +void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + static boolean pre_force_lps_on = FALSE; + + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (type == BTC_LPS_ENABLE) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = TRUE; + + if (coex_sta->force_lps_ctrl) { /* LPS No-32K */ + /* Write WL "Active" in Score-board for PS-TDMA */ + pre_force_lps_on = TRUE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify-force LPS control\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE, TRUE); + } else { + /* LPS-32K, need check if this h2c 0x71 can work?? + * (2015/08/28) + */ + /* Write WL "Non-Active" in Score-board for Native-PS */ + pre_force_lps_on = FALSE; + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE, FALSE); + } + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = FALSE; + + /* Write WL "Active" in Score-board for LPS off */ + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE, TRUE); + + if ((!pre_force_lps_on) && (!coex_sta->force_lps_ctrl)) + halbtc8822b1ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = FALSE; + boolean wifi_under_5g = FALSE; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + coex_sta->freeze_coexrun_by_btinfo = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + if (wifi_connected) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL connected before SCAN\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL is not connected before SCAN\n"); + + BTC_TRACE(trace_buf); + + halbtc8822b1ant_query_bt_info(btcoexist); + + /*2.4 g 1*/ + if (BTC_SCAN_START == type) { + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + /*5 g 1*/ + + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (scan_notify_5g_scan_action 1) **********\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_wifi_under5g(btcoexist); + return; + } + + /* 2.4G.2.3*/ + coex_sta->wifi_is_high_pri_task = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (scan_notify_start action) **********\n"); + BTC_TRACE(trace_buf); + + if (!wifi_connected) { /* non-connected scan */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** wifi not connected 2g scan action 1 **********\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_wifi_not_connected_scan( + btcoexist); + } else { /* wifi is connected */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** wifi connected 2g scan action 2 **********\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_wifi_connected_scan( + btcoexist); + } + + return; + } + + if (BTC_SCAN_START_2G == type) { + coex_sta->wifi_is_high_pri_task = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (scan_notify_2g_sacn_start_for_switch_band_used) **********\n"); + BTC_TRACE(trace_buf); + + if (!wifi_connected) { /* non-connected scan */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** wifi not connected 2g scan action 3 **********\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_action_wifi_not_connected_scan( + btcoexist); + } else { /* wifi is connected */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** wifi connected 2g sacn action 4**********\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_wifi_connected_scan(btcoexist); + } + } else { + coex_sta->wifi_is_high_pri_task = FALSE; + + /* 2.4G 5 WL scan finish, then get and update sacn ap numbers */ + /*5 g 4*/ + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (scan_finish_notify) **********\n"); + BTC_TRACE(trace_buf); + + if (!wifi_connected) /* non-connected scan */ + halbtc8822b1ant_action_wifi_not_connected(btcoexist); + else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** scan_finish_notify action wifi connected **********\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_wifi_connected(btcoexist); + } + } +} + + + +void ex_halbtc8822b1ant_scan_notify_without_bt(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + + boolean wifi_under_5g = FALSE; + + if (BTC_SCAN_START == type) { + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (wifi_under_5g) { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, + 0x3, 1); + return; + } + + /* under 2.4G */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, + 0x3, 2); + return; + } + if (BTC_SCAN_START_2G == type) + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2); +} + +void ex_halbtc8822b1ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (switchband_notify) **********\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + coex_sta->switch_band_notify_to = type; + /*2.4g 4.*//*5 g 2*/ + if (type == BTC_SWITCH_TO_5G) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (switchband_notify 5g action 2) **********\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_action_wifi_under5g(btcoexist); + return; + } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_2G (no for scan)) **********\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_run_coexist_mechanism(btcoexist); + /*5 g 3*/ + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (switchband_notify 2g action 5) **********\n"); + BTC_TRACE(trace_buf); + + ex_halbtc8822b1ant_scan_notify(btcoexist, + BTC_SCAN_START_2G); + } + coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; + +} + + +void ex_halbtc8822b1ant_switchband_notify_without_bt(IN struct btc_coexist + *btcoexist, + IN u8 type) +{ + boolean wifi_under_5g = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (type == BTC_SWITCH_TO_5G) { + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, + 0x3, 1); + return; + } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { + + if (wifi_under_5g) + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, + 0x3, 1); + + else + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0xcbd, 0x3, 2); + } else { + + ex_halbtc8822b1ant_scan_notify_without_bt(btcoexist, + BTC_SCAN_START_2G); + } + +} + +void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (connect notify) **********\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_SCAN, TRUE); + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + + if ((BTC_ASSOCIATE_5G_START == type) || + (BTC_ASSOCIATE_5G_FINISH == type)) { + + if (BTC_ASSOCIATE_5G_START == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (5G associate start notify) **********\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_action_wifi_under5g(btcoexist); + + } else if (BTC_ASSOCIATE_5G_FINISH == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (5G associate finish notify) **********\n"); + BTC_TRACE(trace_buf); + + } + + return; + + } + + + if (BTC_ASSOCIATE_START == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 2G CONNECT START notify\n"); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = TRUE; + + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + coex_dm->arp_cnt = 0; + + halbtc8822b1ant_action_wifi_not_connected_asso_auth(btcoexist); + + coex_sta->freeze_coexrun_by_btinfo = TRUE; + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 2G CONNECT Finish notify\n"); + BTC_TRACE(trace_buf); + coex_sta->wifi_is_high_pri_task = FALSE; + coex_sta->freeze_coexrun_by_btinfo = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + if (!wifi_connected) /* non-connected scan */ + halbtc8822b1ant_action_wifi_not_connected(btcoexist); + else + halbtc8822b1ant_action_wifi_connected(btcoexist); + } + +} + +void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_under_b_mode = FALSE; + boolean wifi_under_5g = FALSE; + + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + + + + if (BTC_MEDIA_CONNECT == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 2g media connect notify"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE, TRUE); + + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 5g media notify\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_action_wifi_under5g(btcoexist); + return; + } + /* Force antenna setup for no scan result issue */ + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (media status notity under b mode) **********\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x00); /* CCK Rx */ + } else { +#if 0 + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); /*CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); /*CCK Rx */ +#endif + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (media status notity not under b mode) **********\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x10); /* CCK Rx */ + } + + coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, + 0x430); + coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, + 0x434); + coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( + btcoexist, 0x42a); + coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( + btcoexist, 0x456); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 2g media disconnect notify\n"); + BTC_TRACE(trace_buf); + coex_dm->arp_cnt = 0; + + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE, FALSE); + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + + coex_sta->cck_ever_lock = FALSE; + } + + halbtc8822b1ant_update_wifi_channel_info(btcoexist, type); + +} + +void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean under_4way = FALSE, wifi_under_5g = FALSE; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 5g special packet notify\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_action_wifi_under5g(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (under_4way) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ---- under_4way!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = TRUE; + coex_sta->specific_pkt_period_cnt = 2; + } else if (BTC_PACKET_ARP == type) { + + coex_dm->arp_cnt++; + + if (coex_sta->wifi_is_high_pri_task) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ARP notify -cnt = %d\n", + coex_dm->arp_cnt); + BTC_TRACE(trace_buf); + } + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", + type); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = TRUE; + coex_sta->specific_pkt_period_cnt = 2; + } + + if (coex_sta->wifi_is_high_pri_task) + halbtc8822b1ant_action_wifi_connected_specific_packet( + btcoexist); + +} + + +void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 i, rsp_source = 0; + boolean wifi_connected = FALSE; + boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE, + wifi_busy = FALSE; + static boolean is_scoreboard_scan = FALSE; + + if (psd_scan->is_AntDet_running) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt_info_notify return for AntDet is running\n"); + BTC_TRACE(trace_buf); + return; + } + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8822B_1ANT_MAX) + rsp_source = BT_INFO_SRC_8822B_1ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + + if (i == length - 1) { + /* last one */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + /* normal */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; + coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; + coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; + + if (BT_INFO_SRC_8822B_1ANT_WIFI_FW != rsp_source) { + + /* if 0xff, it means BT is under WHCK test */ + coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? TRUE : + FALSE); + + coex_sta->bt_create_connection = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE : + FALSE); + + /* unit: %, value-100 to translate to unit: dBm */ + coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + + 10; + + coex_sta->c2h_bt_remote_name_req = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE : + FALSE); + + coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & + 0x10) ? TRUE : FALSE); + + coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & + 0x9) ? TRUE : FALSE); + + coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? + TRUE : FALSE); + + coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & + BT_INFO_8822B_1ANT_B_INQ_PAGE) ? TRUE : FALSE); + + coex_sta->a2dp_bit_pool = ((( + coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? + (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) : 0); + + coex_sta->is_bt_a2dp_sink = (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ? + TRUE : FALSE; + + coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & + 0xf; + + coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; + + coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; + + coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; + + coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; + if (coex_sta->bt_retry_cnt >= 1) + coex_sta->pop_event_cnt++; + + if (coex_sta->c2h_bt_remote_name_req) + coex_sta->cnt_RemoteNameReq++; + + if (coex_sta->bt_info_ext & BIT(1)) + coex_sta->cnt_ReInit++; + + if (coex_sta->bt_info_ext & BIT(2)) { + coex_sta->cnt_setupLink++; + coex_sta->is_setupLink = TRUE; + coex_sta->bt_relink_downcount = 2; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link start in BT info!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_sta->is_setupLink = FALSE; + coex_sta->bt_relink_downcount = 0; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link stop in BT info!!\n"); + BTC_TRACE(trace_buf); + } + + if (coex_sta->bt_info_ext & BIT(3)) + coex_sta->cnt_IgnWlanAct++; + + if (coex_sta->bt_info_ext & BIT(6)) + coex_sta->cnt_RoleSwitch++; + + if (coex_sta->bt_info_ext & BIT(7)) + coex_sta->is_bt_multi_link = TRUE; + else + coex_sta->is_bt_multi_link = FALSE; + + if (coex_sta->bt_create_connection) { + coex_sta->cnt_Page++; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, + &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || + (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { + + is_scoreboard_scan = TRUE; + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_SCAN, TRUE); + + } else + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_SCAN, FALSE); + + } else { + if (is_scoreboard_scan) { + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_SCAN, FALSE); + is_scoreboard_scan = FALSE; + } + } + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + + if ((!btcoexist->manual_control) && + (!btcoexist->stop_coex_dm)) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* Re-Init */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + if (wifi_connected) + halbtc8822b1ant_update_wifi_channel_info( + btcoexist, BTC_MEDIA_CONNECT); + else + halbtc8822b1ant_update_wifi_channel_info( + btcoexist, + BTC_MEDIA_DISCONNECT); + } + + /* If Ignore_WLanAct && not SetUp_Link */ + if ((coex_sta->bt_info_ext & BIT(3)) && + (!(coex_sta->bt_info_ext & BIT(2)))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, FALSE); + } + } + + } + + if ((coex_sta->bt_info_ext & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + BTC_TRACE(trace_buf); + coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( + btcoexist); + + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x4); + + } + + + halbtc8822b1ant_update_bt_link_info(btcoexist); + + halbtc8822b1ant_run_coexist_mechanism(btcoexist); +} + + +void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_RF_ON == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned ON!!\n"); + BTC_TRACE(trace_buf); + btcoexist->stop_coex_dm = FALSE; + + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE, TRUE); + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ONOFF, TRUE); + + } else if (BTC_RF_OFF == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned OFF!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE, FALSE); + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ONOFF, FALSE); + halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); + + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_WLAN_OFF); + /* for test : s3 bt disppear , fail rate 1/600*/ + + halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, TRUE); + + btcoexist->stop_coex_dm = TRUE; + } +} + +void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE, FALSE); + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ONOFF, FALSE); + + halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); + + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_WLAN_OFF); + /* for test : s3 bt disppear , fail rate 1/600*/ + + halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, TRUE); + + ex_halbtc8822b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + btcoexist->stop_coex_dm = TRUE; +} + + +void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + boolean wifi_under_5g = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((pnp_state == BTC_WIFI_PNP_SLEEP) || + (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE | + BT_8822B_1ANT_SCOREBOARD_ONOFF | + BT_8822B_1ANT_SCOREBOARD_SCAN | + BT_8822B_1ANT_SCOREBOARD_UNDERTEST, + FALSE); + + if (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) { + + if (wifi_under_5g) + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + else + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + } else { + + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_WLAN_OFF); + } + + btcoexist->stop_coex_dm = TRUE; + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); +#if 0 + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE | + BT_8822B_1ANT_SCOREBOARD_ONOFF, + TRUE); +#endif + btcoexist->stop_coex_dm = FALSE; + } +} + +void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], *****************Coex DM Reset*****************\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_init_hw_config(btcoexist, FALSE, FALSE); + halbtc8822b1ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist) +{ + boolean bt_relink_finish = FALSE; + +#if 0 + boolean rf4ce_connected = FALSE; +#endif + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ==========================Periodical===========================\n"); + BTC_TRACE(trace_buf); + +#if (BT_AUTO_REPORT_ONLY_8822B_1ANT == 0) + halbtc8822b1ant_query_bt_info(btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ==========================Periodical-auto report only===========================\n"); + BTC_TRACE(trace_buf); + +#endif + + halbtc8822b1ant_monitor_bt_ctr(btcoexist); + halbtc8822b1ant_monitor_wifi_ctr(btcoexist); + + halbtc8822b1ant_monitor_bt_enable_disable(btcoexist); + +#if 0 + /*RF4CE for arris , rf4ce always on*/ + btcoexist->btc_get(btcoexist, BTC_GET_BL_RF4CE_CONNECTED, &rf4ce_connected); + if (rf4ce_connected){ + btcoexist->btc_write_1byte_bitmask( + btcoexist, 0x45e, 0x8, 0x1); + + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, + 50); + + halbtc8822b1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + return; + } +#endif + + if (coex_sta->bt_relink_downcount != 0) { + coex_sta->bt_relink_downcount--; + + if (coex_sta->bt_relink_downcount == 0) { + coex_sta->is_setupLink = FALSE; + bt_relink_finish = TRUE; + } + } + + /* for 4-way, DHCP, EAPOL packet */ + if (coex_sta->specific_pkt_period_cnt > 0) { + + coex_sta->specific_pkt_period_cnt--; + + if ((coex_sta->specific_pkt_period_cnt == 0) && + (coex_sta->wifi_is_high_pri_task)) + coex_sta->wifi_is_high_pri_task = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", + (coex_sta->wifi_is_high_pri_task ? "Yes" : + "No")); + BTC_TRACE(trace_buf); + } + + if (halbtc8822b1ant_is_wifi_status_changed(btcoexist) || (bt_relink_finish) + || (coex_sta->is_set_ps_state_fail)) + halbtc8822b1ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ +} + +void ex_halbtc8822b1ant_antenna_isolation(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + + +} + +void ex_halbtc8822b1ant_psd_scan(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + + +} + +void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist) +{ + +} + +void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist, + IN u8 op_code, IN u8 op_len, IN u8 *pdata) +{} +#endif /* #if(BTC_COEX_OFFLOAD == 1) */ + +#endif + +#else + +void ex_halbtc8822b1ant_switch_band_without_bt(IN struct btc_coexist *btcoexist, + IN boolean wifi_only_5g) +{ + /* ant switch WL2G or WL5G*/ + if (wifi_only_5g) + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 1); + + else + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2); + +} + +#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ diff --git a/hal/btc/halbtc8822b1ant.h b/hal/btc/halbtc8822b1ant.h new file mode 100644 index 0000000..0ba1193 --- /dev/null +++ b/hal/btc/halbtc8822b1ant.h @@ -0,0 +1,480 @@ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8822B_SUPPORT == 1) + +/* ******************************************* + * The following is for 8822B 1ANT BT Co-exist definition + * ******************************************* */ +#define BT_8822B_1ANT_COEX_DBG 0 +#define BT_AUTO_REPORT_ONLY_8822B_1ANT 1 + +#define BT_INFO_8822B_1ANT_B_FTP BIT(7) +#define BT_INFO_8822B_1ANT_B_A2DP BIT(6) +#define BT_INFO_8822B_1ANT_B_HID BIT(5) +#define BT_INFO_8822B_1ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8822B_1ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8822B_1ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8822B_1ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8822B_1ANT_B_CONNECTION BIT(0) + +#define BT_INFO_8822B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT(0))) ? true : false) + +#define BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT 2 + +#define BT_8822B_1ANT_WIFI_NOISY_THRESH 150 /* max: 255 */ +#define BT_8822B_1ANT_DEFAULT_ISOLATION 15 /* unit: dB */ + +/* for Antenna detection */ +#define BT_8822B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 +#define BT_8822B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 +#define BT_8822B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 +#define BT_8822B_1ANT_ANTDET_PSDTHRES_1ANT 35 +#define BT_8822B_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ +#define BT_8822B_1ANT_ANTDET_ENABLE 0 +#define BT_8822B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0 + +#define BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 + + + +enum bt_8822b_1ant_signal_state { + BT_8822B_1ANT_SIG_STA_SET_TO_LOW = 0x0, + BT_8822B_1ANT_SIG_STA_SET_BY_HW = 0x0, + BT_8822B_1ANT_SIG_STA_SET_TO_HIGH = 0x1, + BT_8822B_1ANT_SIG_STA_MAX +}; + +enum bt_8822b_1ant_path_ctrl_owner { + BT_8822B_1ANT_PCO_BTSIDE = 0x0, + BT_8822B_1ANT_PCO_WLSIDE = 0x1, + BT_8822B_1ANT_PCO_MAX +}; + +enum bt_8822b_1ant_gnt_ctrl_type { + BT_8822B_1ANT_GNT_CTRL_BY_PTA = 0x0, + BT_8822B_1ANT_GNT_CTRL_BY_SW = 0x1, + BT_8822B_1ANT_GNT_CTRL_MAX +}; + +enum bt_8822b_1ant_gnt_ctrl_block { + BT_8822B_1ANT_GNT_BLOCK_RFC_BB = 0x0, + BT_8822B_1ANT_GNT_BLOCK_RFC = 0x1, + BT_8822B_1ANT_GNT_BLOCK_BB = 0x2, + BT_8822B_1ANT_GNT_BLOCK_MAX +}; + +enum bt_8822b_1ant_lte_coex_table_type { + BT_8822B_1ANT_CTT_WL_VS_LTE = 0x0, + BT_8822B_1ANT_CTT_BT_VS_LTE = 0x1, + BT_8822B_1ANT_CTT_MAX +}; + +enum bt_8822b_1ant_lte_break_table_type { + BT_8822B_1ANT_LBTT_WL_BREAK_LTE = 0x0, + BT_8822B_1ANT_LBTT_BT_BREAK_LTE = 0x1, + BT_8822B_1ANT_LBTT_LTE_BREAK_WL = 0x2, + BT_8822B_1ANT_LBTT_LTE_BREAK_BT = 0x3, + BT_8822B_1ANT_LBTT_MAX +}; + +enum bt_info_src_8822b_1ant { + BT_INFO_SRC_8822B_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8822B_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8822B_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8822B_1ANT_MAX +}; + +enum bt_8822b_1ant_bt_status { + BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8822B_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8822B_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8822B_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8822B_1ANT_BT_STATUS_MAX +}; + +enum bt_8822b_1ant_wifi_status { + BT_8822B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8822B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, + BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8822B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8822B_1ANT_WIFI_STATUS_MAX +}; + +enum bt_8822b_1ant_coex_algo { + BT_8822B_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8822B_1ANT_COEX_ALGO_SCO = 0x1, + BT_8822B_1ANT_COEX_ALGO_HID = 0x2, + BT_8822B_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8822B_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8822B_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8822B_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8822B_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8822B_1ANT_COEX_ALGO_NOPROFILEBUSY = 0xb, + BT_8822B_1ANT_COEX_ALGO_A2DPSINK = 0xc, + BT_8822B_1ANT_COEX_ALGO_MAX +}; + +enum bt_8822b_1ant_ext_ant_switch_type { + BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT = 0x0, + BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SP3T = 0x1, + BT_8822B_1ANT_EXT_ANT_SWITCH_MAX +}; + +enum bt_8822b_1ant_ext_ant_switch_ctrl_type { + BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, + BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, + BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, + BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, + BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, + BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_MAX +}; + +enum bt_8822b_1ant_ext_ant_switch_pos_type { + BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT = 0x0, + BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG = 0x1, + BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA = 0x2, + BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE = 0x3, + BT_8822B_1ANT_EXT_ANT_SWITCH_TO_MAX +}; + +enum bt_8822b_1ant_phase { + BT_8822B_1ANT_PHASE_COEX_INIT = 0x0, + BT_8822B_1ANT_PHASE_WLANONLY_INIT = 0x1, + BT_8822B_1ANT_PHASE_WLAN_OFF = 0x2, + BT_8822B_1ANT_PHASE_2G_RUNTIME = 0x3, + BT_8822B_1ANT_PHASE_5G_RUNTIME = 0x4, + BT_8822B_1ANT_PHASE_BTMPMODE = 0x5, + BT_8822B_1ANT_PHASE_MAX +}; + +/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/ +enum bt_8822b_1ant_Scoreboard { + BT_8822B_1ANT_SCOREBOARD_ACTIVE = BIT(0), + BT_8822B_1ANT_SCOREBOARD_ONOFF = BIT(1), + BT_8822B_1ANT_SCOREBOARD_SCAN = BIT(2), + BT_8822B_1ANT_SCOREBOARD_UNDERTEST = BIT(3), + BT_8822B_1ANT_SCOREBOARD_WLBUSY = BIT(6) +}; + +struct coex_dm_8822b_1ant { + /* hw setting */ + u32 pre_ant_pos_type; + u32 cur_ant_pos_type; + /* fw mechanism */ + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean auto_tdma_adjust; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + u8 pre_fw_dac_swing_lvl; + u8 cur_fw_dac_swing_lvl; + + /* sw mechanism */ + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + + u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ + u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ + u16 backup_retry_limit; + u8 backup_ampdu_max_time; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + u32 pre_ra_mask; + u32 cur_ra_mask; + u8 pre_arfr_type; + u8 cur_arfr_type; + u8 pre_retry_limit_type; + u8 cur_retry_limit_type; + u8 pre_ampdu_time_type; + u8 cur_ampdu_time_type; + u32 arp_cnt; + + u32 pre_ext_ant_switch_status; + u32 cur_ext_ant_switch_status; + + u8 error_condition; + boolean pre_agc_table_en; + boolean cur_agc_table_en; +}; + +struct coex_sta_8822b_1ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + u8 num_of_profile; + + boolean under_lps; + boolean under_ips; + u32 specific_pkt_period_cnt; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + boolean is_hiPri_rx_overhead; + s8 bt_rssi; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + u8 bt_info_c2h[BT_INFO_SRC_8822B_1ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8822B_1ANT_MAX]; + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; + boolean c2h_bt_page; /* Add for win8.1 page out issue */ + boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ + + u8 bt_info_ext; + u8 bt_info_ext2; + u32 pop_event_cnt; + u8 scan_ap_num; + u8 bt_retry_cnt; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + + boolean cck_lock; + boolean pre_ccklock; + boolean cck_ever_lock; + u8 coex_table_type; + + boolean force_lps_ctrl; + + boolean concurrent_rx_mode_on; + + u16 score_board; + u8 isolation_btween_wb; /* 0~ 50 */ + + u8 a2dp_bit_pool; + u8 cut_version; + boolean acl_busy; + boolean bt_create_connection; + + u32 bt_coex_supported_feature; + u32 bt_coex_supported_version; + + u8 bt_ble_scan_type; + u32 bt_ble_scan_para[3]; + + boolean run_time_state; + boolean freeze_coexrun_by_btinfo; + + boolean is_A2DP_3M; + boolean voice_over_HOGP; + u8 bt_info; + boolean is_autoslot; + u8 forbidden_slot; + u8 hid_busy_num; + u8 hid_pair_cnt; + + u32 cnt_RemoteNameReq; + u32 cnt_setupLink; + u32 cnt_ReInit; + u32 cnt_IgnWlanAct; + u32 cnt_Page; + u32 cnt_RoleSwitch; + + u16 bt_reg_vendor_ac; + u16 bt_reg_vendor_ae; + + boolean is_setupLink; + u8 wl_noisy_level; + u32 gnt_error_cnt; + u8 bt_afh_map[10]; + u8 bt_relink_downcount; + boolean is_tdma_btautoslot; + boolean is_tdma_btautoslot_hang; + + u8 switch_band_notify_to; + boolean is_rf_state_off; + + boolean is_hid_low_pri_tx_overhead; + boolean is_bt_multi_link; + boolean is_bt_a2dp_sink; + boolean rf4ce_enabled; + + boolean is_set_ps_state_fail; + u8 cnt_set_ps_state_fail; +}; + +struct rfe_type_8822b_1ant { + + u8 rfe_module_type; + boolean ext_ant_switch_exist; + u8 ext_ant_switch_type; + /* iF 0: ANTSW(rfe_sel9)=0, ANTSWB(rfe_sel8)=1 => Ant to BT/5G */ + u8 ext_ant_switch_ctrl_polarity; +}; + + +#define BT_8822B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ +#define BT_8822B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ +#define BT_8822B_1ANT_ANTDET_BUF_LEN 16 + +struct psdscan_sta_8822b_1ant { + + u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ + u32 ant_det_bt_tx_time; + u32 ant_det_pre_psdscan_peak_val; + boolean ant_det_is_ant_det_available; + u32 ant_det_psd_scan_peak_val; + boolean ant_det_is_btreply_available; + u32 ant_det_psd_scan_peak_freq; + + u8 ant_det_result; + u8 ant_det_peak_val[BT_8822B_1ANT_ANTDET_BUF_LEN]; + u8 ant_det_peak_freq[BT_8822B_1ANT_ANTDET_BUF_LEN]; + u32 ant_det_try_count; + u32 ant_det_fail_count; + u32 ant_det_inteval_count; + u32 ant_det_thres_offset; + + u32 real_cent_freq; + s32 real_offset; + u32 real_span; + + u32 psd_band_width; /* unit: Hz */ + u32 psd_point; /* 128/256/512/1024 */ + u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_start_point; + u32 psd_stop_point; + u32 psd_max_value_point; + u32 psd_max_value; + u32 psd_start_base; + u32 psd_avg_num; /* 1/8/16/32 */ + u32 psd_gen_count; + boolean is_psd_running; + boolean is_psd_show_max_only; + boolean is_AntDet_running; +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b1ant_scan_notify_without_bt(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b1ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b1ant_switchband_notify_without_bt(IN struct btc_coexist + *btcoexist, + IN u8 type); +void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8822b1ant_ScoreBoardStatusNotify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); +void ex_halbtc8822b1ant_antenna_isolation(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); + +void ex_halbtc8822b1ant_psd_scan(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); +void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist); + +void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist, + IN u8 op_code, IN u8 op_len, IN u8 *pdata); + +#else +#define ex_halbtc8822b1ant_power_on_setting(btcoexist) +#define ex_halbtc8822b1ant_pre_load_firmware(btcoexist) +#define ex_halbtc8822b1ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8822b1ant_init_coex_dm(btcoexist) +#define ex_halbtc8822b1ant_ips_notify(btcoexist, type) +#define ex_halbtc8822b1ant_lps_notify(btcoexist, type) +#define ex_halbtc8822b1ant_scan_notify(btcoexist, type) +#define ex_halbtc8822b1ant_scan_notify_without_bt(btcoexist, type) +#define ex_halbtc8822b1ant_switchband_notify(btcoexist, type) +#define ex_halbtc8822b1ant_switchband_notify_without_bt(btcoexist, type) +#define ex_halbtc8822b1ant_connect_notify(btcoexist, type) +#define ex_halbtc8822b1ant_media_status_notify(btcoexist, type) +#define ex_halbtc8822b1ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8822b1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8822b1ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8822b1ant_halt_notify(btcoexist) +#define ex_halbtc8822b1ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8822b1ant_ScoreBoardStatusNotify(btcoexist, tmp_buf, length) +#define ex_halbtc8822b1ant_coex_dm_reset(btcoexist) +#define ex_halbtc8822b1ant_periodical(btcoexist) +#define ex_halbtc8822b1ant_display_coex_info(btcoexist) +#define ex_halbtc8822b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8822b1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8822b1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8822b1ant_display_ant_detection(btcoexist) +#define ex_halbtc8822b1ant_dbg_control(btcoexist, op_code, op_len, pdata) +#endif +#else + +void ex_halbtc8822b1ant_init_hw_config_without_bt(IN struct btc_coexist + *btcoexist); +void ex_halbtc8822b1ant_switch_band_without_bt(IN struct btc_coexist *btcoexist, + IN boolean wifi_only_5g); + + +#endif diff --git a/hal/btc/halbtc8822b2ant.c b/hal/btc/halbtc8822b2ant.c new file mode 100644 index 0000000..4dc1bb4 --- /dev/null +++ b/hal/btc/halbtc8822b2ant.c @@ -0,0 +1,6112 @@ +/* ************************************************************ + * Description: + * + * This file is for RTL8822B Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8822B_SUPPORT == 1) +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8822b_2ant glcoex_dm_8822b_2ant; +static struct coex_dm_8822b_2ant *coex_dm = &glcoex_dm_8822b_2ant; +static struct coex_sta_8822b_2ant glcoex_sta_8822b_2ant; +static struct coex_sta_8822b_2ant *coex_sta = &glcoex_sta_8822b_2ant; +static struct psdscan_sta_8822b_2ant gl_psd_scan_8822b_2ant; +static struct psdscan_sta_8822b_2ant *psd_scan = &gl_psd_scan_8822b_2ant; +static struct rfe_type_8822b_2ant gl_rfe_type_8822b_2ant; +static struct rfe_type_8822b_2ant *rfe_type = &gl_rfe_type_8822b_2ant; + +static const char *const glbt_info_src_8822b_2ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +static u32 glcoex_ver_date_8822b_2ant = 20170518; +static u32 glcoex_ver_8822b_2ant = 0x44; +static u32 glcoex_ver_btdesired_8822b_2ant = 0x42; + + +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8822b2ant_ + * ************************************************************ */ +static +u8 halbtc8822b2ant_bt_rssi_state(IN struct btc_coexist *btcoexist, + u8 *ppre_bt_rssi_state, u8 level_num, + u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = *ppre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return *ppre_bt_rssi_state; + } + + if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + *ppre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + + +static +u8 halbtc8822b2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh, + IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = *pprewifi_rssi_state; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return *pprewifi_rssi_state; + } + + if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + *pprewifi_rssi_state = wifi_rssi_state; + + return wifi_rssi_state; +} + + +static +void halbtc8822b2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist, + IN u8 isolation_measuared) +{ + s8 interference_wl_tx = 0, interference_bt_tx = 0; + + + interference_wl_tx = BT_8822B_2ANT_WIFI_MAX_TX_POWER - + isolation_measuared; + interference_bt_tx = BT_8822B_2ANT_BT_MAX_TX_POWER - + isolation_measuared; + + + + coex_sta->wifi_coex_thres = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; + coex_sta->wifi_coex_thres2 = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2; + + coex_sta->bt_coex_thres = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1; + coex_sta->bt_coex_thres2 = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2; + + +#if 0 + coex_sta->wifi_coex_thres = interference_wl_tx + BT_8822B_2ANT_WIFI_SIR_THRES1; + coex_sta->wifi_coex_thres2 = interference_wl_tx + BT_8822B_2ANT_WIFI_SIR_THRES2; + + coex_sta->bt_coex_thres = interference_bt_tx + BT_8822B_2ANT_BT_SIR_THRES1; + coex_sta->bt_coex_thres2 = interference_bt_tx + BT_8822B_2ANT_BT_SIR_THRES2; +#endif + + + + + +#if 0 + if (BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - + BT_8822B_2ANT_DEFAULT_ISOLATION)) + coex_sta->wifi_coex_thres = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; + else + coex_sta->wifi_coex_thres = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 - (isolation_measuared - + BT_8822B_2ANT_DEFAULT_ISOLATION); + + if (BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - + BT_8822B_2ANT_DEFAULT_ISOLATION)) + coex_sta->bt_coex_thres = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1; + else + coex_sta->bt_coex_thres = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 - (isolation_measuared - + BT_8822B_2ANT_DEFAULT_ISOLATION); + +#endif +} + +static +void halbtc8822b2ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No query BT info because BT is disabled!\n"); + BTC_TRACE(trace_buf); + return; + } + + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); +} + + +static +void halbtc8822b2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_autoslot_hang = 0; + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + + if ((coex_sta->low_priority_tx > 1050) && + (!coex_sta->c2h_bt_inquiry_page)) + coex_sta->pop_event_cnt++; + + if ((coex_sta->low_priority_rx >= 950) && + (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) + && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && + (coex_sta->bt_link_exist)) { + if (cnt_slave >= 2) { + bt_link_info->slave_role = TRUE; + cnt_slave = 2; + } else { + cnt_slave++; + } + } else { + if (cnt_slave == 0) { + bt_link_info->slave_role = FALSE; + cnt_slave = 0; + } else { + cnt_slave--; + } + + } + + if (coex_sta->is_tdma_btautoslot) { + if ((coex_sta->low_priority_tx >= 1300) && + (coex_sta->low_priority_rx <= 150)) { + if (cnt_autoslot_hang >= 2) { + coex_sta->is_tdma_btautoslot_hang = TRUE; + cnt_autoslot_hang = 2; + } else { + cnt_autoslot_hang++; + } + } else { + if (cnt_autoslot_hang == 0) { + coex_sta->is_tdma_btautoslot_hang = FALSE; + cnt_autoslot_hang = 0; + } else { + cnt_autoslot_hang--; + } + } + } + + if (coex_sta->sco_exist) { + if ((coex_sta->high_priority_tx >= 400) && + (coex_sta->high_priority_rx >= 400)) + coex_sta->is_eSCO_mode = FALSE; + else + coex_sta->is_eSCO_mode = TRUE; + } + + if (bt_link_info->hid_only) { + if (coex_sta->low_priority_rx > 50) + coex_sta->is_hid_low_pri_tx_overhead = true; + else + coex_sta->is_hid_low_pri_tx_overhead = false; + } + + if ((coex_sta->high_priority_tx == 0) && + (coex_sta->high_priority_rx == 0) && + (coex_sta->low_priority_tx == 0) && + (coex_sta->low_priority_rx == 0)) { + num_of_bt_counter_chk++; + if (num_of_bt_counter_chk >= 3) { + halbtc8822b2ant_query_bt_info(btcoexist); + num_of_bt_counter_chk = 0; + } + } + +} + +static +void halbtc8822b2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ +#if 1 + s32 wifi_rssi = 0; + boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE, + wifi_scan = FALSE; + boolean bt_idle = FALSE; + static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, + wl_noisy_count1 = 3, wl_noisy_count2 = 0; + u32 total_cnt, cck_cnt; + u32 cnt_crcok = 0, cnt_crcerr = 0; + static u8 cnt = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_VHT); + + cnt_crcok = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + + coex_sta->crc_ok_11n_vht; + + cnt_crcerr = coex_sta->crc_err_cck + coex_sta->crc_err_11g + + coex_sta->crc_err_11n + + coex_sta->crc_err_11n_vht; + + if ((wifi_busy) && (cnt_crcerr != 0)) { + + coex_sta->now_crc_ratio = cnt_crcok/cnt_crcerr; + + if (cnt == 0) + coex_sta->acc_crc_ratio = coex_sta->now_crc_ratio; + else + coex_sta->acc_crc_ratio = (coex_sta->acc_crc_ratio * 7 + + coex_sta->now_crc_ratio * 3)/10; + + if (cnt >= 10) + cnt = 0; + else + cnt++; + } + + cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; + + if ((coex_dm->bt_status == + BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE) || + (coex_dm->bt_status == + BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE) || + (coex_sta->bt_disabled)) + bt_idle = TRUE; + + if (cck_cnt > 250) { + if (wl_noisy_count2 < 3) + wl_noisy_count2++; + + if (wl_noisy_count2 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count1 = 0; + } + + } else if (cck_cnt < 50) { + if (wl_noisy_count0 < 3) + wl_noisy_count0++; + + if (wl_noisy_count0 == 3) { + wl_noisy_count1 = 0; + wl_noisy_count2 = 0; + } + + } else { + if (wl_noisy_count1 < 3) + wl_noisy_count1++; + + if (wl_noisy_count1 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count2 = 0; + } + } + + if (wl_noisy_count2 == 3) + coex_sta->wl_noisy_level = 2; + else if (wl_noisy_count1 == 3) + coex_sta->wl_noisy_level = 1; + else + coex_sta->wl_noisy_level = 0; + + if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { + total_cnt = cnt_crcok; + + if ((coex_dm->bt_status == + BT_8822B_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == + BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (coex_dm->bt_status == + BT_8822B_1ANT_BT_STATUS_SCO_BUSY)) { + if (coex_sta->crc_ok_cck > (total_cnt - + coex_sta->crc_ok_cck)) { + if (cck_lock_counter < 3) + cck_lock_counter++; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + if (!coex_sta->pre_ccklock) { + + if (cck_lock_counter >= 3) + coex_sta->cck_lock = TRUE; + else + coex_sta->cck_lock = FALSE; + } else { + if (cck_lock_counter == 0) + coex_sta->cck_lock = FALSE; + else + coex_sta->cck_lock = TRUE; + } + + if (coex_sta->cck_lock) + coex_sta->cck_ever_lock = TRUE; + + coex_sta->pre_ccklock = coex_sta->cck_lock; + +#endif +} + + +static +boolean halbtc8822b2ant_is_wifibt_status_changed(IN struct btc_coexist + *btcoexist) +{ + static boolean pre_wifi_busy = FALSE, pre_under_4way = FALSE, + pre_bt_hs_on = FALSE, pre_bt_off = FALSE, + pre_bt_slave = FALSE, pre_hid_low_pri_tx_overhead = FALSE, + pre_wifi_under_lps = FALSE, pre_bt_setup_link = FALSE; + static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0; + boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE; + boolean wifi_connected = FALSE; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (coex_sta->bt_disabled != pre_bt_off) { + pre_bt_off = coex_sta->bt_disabled; + + if (coex_sta->bt_disabled) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + return TRUE; + } + + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return TRUE; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return TRUE; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return TRUE; + } + if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { + pre_wl_noisy_level = coex_sta->wl_noisy_level; + return TRUE; + } + if (coex_sta->under_lps != pre_wifi_under_lps) { + pre_wifi_under_lps = coex_sta->under_lps; + if (coex_sta->under_lps) + return TRUE; + } + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->hid_busy_num != pre_hid_busy_num) { + pre_hid_busy_num = coex_sta->hid_busy_num; + return TRUE; + } + + if (bt_link_info->slave_role != pre_bt_slave) { + pre_bt_slave = bt_link_info->slave_role; + return TRUE; + } + + if (pre_hid_low_pri_tx_overhead != coex_sta->is_hid_low_pri_tx_overhead) { + pre_hid_low_pri_tx_overhead = coex_sta->is_hid_low_pri_tx_overhead; + return TRUE; + } + + if (pre_bt_setup_link != coex_sta->is_setupLink) { + pre_bt_setup_link = coex_sta->is_setupLink; + return TRUE; + } + } + + return FALSE; +} + + +static +void halbtc8822b2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = FALSE; + boolean bt_busy = FALSE; + + coex_sta->num_of_profile = 0; + + /* set link exist status */ + if (!(coex_sta->bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = FALSE; + coex_sta->pan_exist = FALSE; + coex_sta->a2dp_exist = FALSE; + coex_sta->hid_exist = FALSE; + coex_sta->sco_exist = FALSE; + } else { /* connection exists */ + coex_sta->bt_link_exist = TRUE; + if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_FTP) { + coex_sta->pan_exist = TRUE; + coex_sta->num_of_profile++; + } else { + coex_sta->pan_exist = FALSE; + } + + if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_A2DP) { + coex_sta->a2dp_exist = TRUE; + coex_sta->num_of_profile++; + } else { + coex_sta->a2dp_exist = FALSE; + } + + if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_HID) { + coex_sta->hid_exist = TRUE; + coex_sta->num_of_profile++; + } else { + coex_sta->hid_exist = FALSE; + } + + if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) { + coex_sta->sco_exist = TRUE; + coex_sta->num_of_profile++; + } else { + coex_sta->sco_exist = FALSE; + } + + } + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + bt_link_info->acl_busy = coex_sta->acl_busy; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = TRUE; + bt_link_info->bt_link_exist = TRUE; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = TRUE; + else + bt_link_info->sco_only = FALSE; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = TRUE; + else + bt_link_info->a2dp_only = FALSE; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = TRUE; + else + bt_link_info->pan_only = FALSE; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = TRUE; + else + bt_link_info->hid_only = FALSE; + + if (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_INQ_PAGE) { + coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_INQ_PAGE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); + } else if (!(coex_sta->bt_info & BT_INFO_8822B_2ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + } else if (coex_sta->bt_info == BT_INFO_8822B_2ANT_B_CONNECTION) { + /* connection exists but no busy */ + coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + } else if (((coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_BUSY)) && + (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_ACL_BUSY)) { + coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); + } else if ((coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + } else if (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + } else { + coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + } + + BTC_TRACE(trace_buf); + + if ((BT_8822B_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8822B_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + bt_busy = TRUE; + else + bt_busy = FALSE; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); +} + + +static +void halbtc8822b2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + u32 RTL97F_8822B = 0; + + if (RTL97F_8822B) + return; + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + /* enable BT AFH skip WL channel for 8822b + * because BT Rx LO interference + */ + h2c_parameter[0] = 0x1; +#if 0 + h2c_parameter[0] = 0x0; +#endif + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); + +} + + +static +void halbtc8822b2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, + IN u8 dac_swing_lvl) +{ + u8 h2c_parameter[1] = {0}; + u32 RTL97F_8822B = 0; + + if (RTL97F_8822B) + return; + + /* There are several type of dacswing */ + /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ + h2c_parameter[0] = dac_swing_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); +} + + +static +void halbtc8822b2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 fw_dac_swing_lvl) +{ + u32 RTL97F_8822B = 0; + + if (RTL97F_8822B) + return; + + coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; + + if (!force_exec) { + if (coex_dm->pre_fw_dac_swing_lvl == + coex_dm->cur_fw_dac_swing_lvl) + return; + } + + halbtc8822b2ant_set_fw_dac_swing_level(btcoexist, + coex_dm->cur_fw_dac_swing_lvl); + + coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; +} + +static +void halbtc8822b2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN u8 dec_bt_pwr_lvl) +{ + u32 RTL97F_8822B = 0; + u8 h2c_parameter[1] = {0}; + + if (RTL97F_8822B) + return; + + h2c_parameter[0] = dec_bt_pwr_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); +} + +static +void halbtc8822b2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 dec_bt_pwr_lvl) +{ + coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; + + if (!force_exec) { + if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) + return; + } + halbtc8822b2ant_set_fw_dec_bt_pwr(btcoexist, + coex_dm->cur_bt_dec_pwr_lvl); + + coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; +} + +static +void halbtc8822b2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + +#if 1 + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == + coex_dm->cur_low_penalty_ra) + return; + } + + if (low_penalty_ra) + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 50); + else + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; + +#endif + +} + +static +void halbtc8822b2ant_write_score_board( + IN struct btc_coexist *btcoexist, + IN u16 bitpos, + IN boolean state +) +{ + + static u16 originalval = 0x8002; + + if (state) + originalval = originalval | bitpos; + else + originalval = originalval & (~bitpos); + + + btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); + +} + +static +void halbtc8822b2ant_read_score_board( + IN struct btc_coexist *btcoexist, + IN u16 *score_board_val +) +{ + + *score_board_val = (btcoexist->btc_read_2byte(btcoexist, + 0xaa)) & 0x7fff; +} + +static +void halbtc8822b2ant_post_state_to_bt( + IN struct btc_coexist *btcoexist, + IN u16 type, + IN BOOLEAN state +) +{ + + halbtc8822b2ant_write_score_board(btcoexist, (u16) type, state); + +} + + + +static +void halbtc8822b2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = TRUE, bt_disabled = FALSE, wifi_under_5g = FALSE; + u16 u16tmp; + + /* This function check if bt is disabled */ +#if 0 + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = FALSE; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = FALSE; + + +#else + + /* Read BT on/off status from scoreboard[1], + * enable this only if BT patch support this feature + */ + halbtc8822b2ant_read_score_board(btcoexist, &u16tmp); + + bt_active = u16tmp & BIT(1); + + +#endif + + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = FALSE; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } else { + + bt_disable_cnt++; + if (bt_disable_cnt >= 10) { + bt_disabled = TRUE; + bt_disable_cnt = 10; + } + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((wifi_under_5g) || (bt_disabled)) + halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); + else + halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE); + + + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + } + +} + +static +void halbtc8822b2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, + boolean isenable) +{ +#if BT_8822B_2ANT_COEX_DBG + static u8 bitVal[5] = {0, 0, 0, 0, 0}; +#if 0 + static boolean state = FALSE; + + if (state == isenable) + return; + + state = isenable; +#endif + + if (isenable) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], enable_gnt_to_gpio!!\n"); + BTC_TRACE(trace_buf); + + /* enable GNT_WL, GNT_BT to GPIO for debug */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); + + /* store original value */ + bitVal[0] = (btcoexist->btc_read_1byte(btcoexist, + 0x66) & BIT(4)) >> 4; /*0x66[4] */ + bitVal[1] = (btcoexist->btc_read_1byte(btcoexist, + 0x67) & BIT(0)); /*0x66[8] */ + bitVal[2] = (btcoexist->btc_read_1byte(btcoexist, + 0x42) & BIT(3)) >> 3; /*0x40[19] */ + bitVal[3] = (btcoexist->btc_read_1byte(btcoexist, + 0x65) & BIT(7)) >> 7; /*0x64[15] */ + bitVal[4] = (btcoexist->btc_read_1byte(btcoexist, + 0x72) & BIT(2)) >> 2; /*0x70[18] */ + + /* switch GPIO Mux */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), + 0x0); /*0x66[4] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), + 0x0); /*0x66[8] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), + 0x0); /*0x40[19] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), + 0x0); /*0x64[15] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), + 0x0); /*0x70[18] = 0 */ + + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], disable_gnt_to_gpio!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); + + /* Restore original value */ + /* switch GPIO Mux */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), + bitVal[0]); /*0x66[4] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), + bitVal[1]); /*0x66[8] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), + bitVal[2]); /*0x40[19] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), + bitVal[3]); /*0x64[15] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), + bitVal[4]); /*0x70[18] = 0 */ + } + +#endif +} + + +static +u32 halbtc8822b2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, + IN u16 reg_addr) +{ + u32 delay_count = 0; + + while (1) { + if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { + delay_ms(50); + delay_count++; + if (delay_count >= 10) { + delay_count = 0; + break; + } + } else { + break; + } + } + + /* wait for ready bit before access 0x1700 */ + btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr); + + return btcoexist->btc_read_4byte(btcoexist, + 0x1708); /* get read data */ + +} + + +static +void halbtc8822b2ant_ltecoex_indirect_write_reg(IN struct btc_coexist + *btcoexist, + IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) +{ + u32 val, i = 0, bitpos = 0, delay_count = 0; + + + if (bit_mask == 0x0) + return; + if (bit_mask == 0xffffffff) { + /* wait for ready bit before access 0x1700/0x1704 */ + while (1) { + if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { + delay_ms(50); + delay_count++; + if (delay_count >= 10) { + delay_count = 0; + break; + } + } else { + break; + } + } + + btcoexist->btc_write_4byte(btcoexist, 0x1704, + reg_value); /* put write data */ + + btcoexist->btc_write_4byte(btcoexist, 0x1700, + 0xc00F0000 | reg_addr); + } else { + for (i = 0; i <= 31; i++) { + if (((bit_mask >> i) & 0x1) == 0x1) { + bitpos = i; + break; + } + } + + /* read back register value before write */ + val = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, + reg_addr); + val = (val & (~bit_mask)) | (reg_value << bitpos); + + /* wait for ready bit before access 0x1700/0x1704 */ + while (1) { + if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { + delay_ms(50); + delay_count++; + if (delay_count >= 10) { + delay_count = 0; + break; + } + } else { + break; + } + } + + btcoexist->btc_write_4byte(btcoexist, 0x1704, + val); /* put write data */ + + btcoexist->btc_write_4byte(btcoexist, 0x1700, + 0xc00F0000 | reg_addr); + } + +} + + +static +void halbtc8822b2ant_ltecoex_enable(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 val; + + val = (enable) ? 1 : 0; + halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, + val); /* 0x38[7] */ + +} + +static +void halbtc8822b2ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, + IN boolean wifi_control) +{ + u8 val; + + val = (wifi_control) ? 1 : 0; + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, + val); /* 0x70[26] */ + +} + +static +void halbtc8822b2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, bit_mask; + + state = state & 0x1; + val = (sw_control) ? ((state << 1) | 0x1) : 0; + + switch (control_block) { + case BT_8822B_2ANT_GNT_BLOCK_RFC_BB: + default: + bit_mask = 0xc000; + halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[15:14] */ + bit_mask = 0x0c00; + halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[11:10] */ + break; + case BT_8822B_2ANT_GNT_BLOCK_RFC: + bit_mask = 0xc000; + halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[15:14] */ + break; + case BT_8822B_2ANT_GNT_BLOCK_BB: + bit_mask = 0x0c00; + halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[11:10] */ + break; + + } + +} + +static +void halbtc8822b2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, bit_mask; + + state = state & 0x1; + val = (sw_control) ? ((state << 1) | 0x1) : 0; + + switch (control_block) { + case BT_8822B_2ANT_GNT_BLOCK_RFC_BB: + default: + bit_mask = 0x3000; + halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[13:12] */ + bit_mask = 0x0300; + halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[9:8] */ + break; + case BT_8822B_2ANT_GNT_BLOCK_RFC: + bit_mask = 0x3000; + halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[13:12] */ + break; + case BT_8822B_2ANT_GNT_BLOCK_BB: + bit_mask = 0x0300; + halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, bit_mask, val); /* 0x38[9:8] */ + break; + + } + +} + +static +void halbtc8822b2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u16 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8822B_2ANT_CTT_WL_VS_LTE: + reg_addr = 0xa0; + break; + case BT_8822B_2ANT_CTT_BT_VS_LTE: + reg_addr = 0xa4; + break; + } + + if (reg_addr != 0x0000) + halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ + + +} + + +static +void halbtc8822b2ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 interval, + IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, + IN u8 val0x6c4_b3) +{ + static u8 pre_h2c_parameter[6] = {0}; + u8 cur_h2c_parameter[6] = {0}; + u8 i, match_cnt = 0; + + cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ + + cur_h2c_parameter[1] = interval; + cur_h2c_parameter[2] = val0x6c4_b0; + cur_h2c_parameter[3] = val0x6c4_b1; + cur_h2c_parameter[4] = val0x6c4_b2; + cur_h2c_parameter[5] = val0x6c4_b3; + + if (!force_exec) { + for (i = 1; i <= 5; i++) { + if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) + break; + + match_cnt++; + } + + if (match_cnt == 5) + return; + } + + for (i = 1; i <= 5; i++) + pre_h2c_parameter[i] = cur_h2c_parameter[i]; + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); +} + +static +void halbtc8822b2ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +static +void halbtc8822b2ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8822b2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +static +void halbtc8822b2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + u32 break_table; + u8 select_table; + + coex_sta->coex_table_type = type; + + if (coex_sta->concurrent_rx_mode_on) { + break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ + /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ + select_table = 0xb; + } else { + break_table = 0xffffff; + select_table = 0x3; + } + + switch (type) { + case 0: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0xffffffff, 0xffffffff, break_table, select_table); + break; + case 1: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, select_table); + break; + case 2: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table); + break; + case 3: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, select_table); + break; + case 4: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, select_table); + break; + case 5: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, break_table, select_table); + break; + case 6: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xfafafafa, break_table, select_table); + break; + case 7: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xaa5a5a5a, break_table, select_table); + break; + case 8: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xfafafafa, break_table, select_table); + break; + case 9: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0xaaaa5aaa, break_table, select_table); + break; + case 10: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a555a, break_table, select_table); + break; + default: + break; + } +} + +static +void halbtc8822b2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 h2c_parameter[1] = {0}; + u32 RTL97F_8822B = 0; + + if (RTL97F_8822B) + return; + + if (enable) + h2c_parameter[0] |= BIT(0); /* function enable */ + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + +static +void halbtc8822b2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8822b2ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +static +void halbtc8822b2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +static +void halbtc8822b2ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8822b2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + + +static +void halbtc8822b2ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + u8 h2c_parameter[5] = {0, 0, 0, 0x40, 0}; + u32 RTL97F_8822B = 0; + + if (RTL97F_8822B) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ +#if 0 + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, + 8); +#endif + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ +#if 0 + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, + 8); +#endif + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + + +static +boolean halbtc8822b2ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = FALSE, result = TRUE; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + coex_sta->force_lps_ctrl = FALSE; + /* recover to original 32k low power setting */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b2ant_power_save_state == BTC_PS_WIFI_NATIVE\n"); + BTC_TRACE(trace_buf); + + low_pwr_disable = FALSE; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + break; + case BTC_PS_LPS_ON: + coex_sta->force_lps_ctrl = TRUE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b2ant_power_save_state == BTC_PS_LPS_ON\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_ps_tdma_check_for_power_save_state( + btcoexist, TRUE); + halbtc8822b2ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = TRUE; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + break; + case BTC_PS_LPS_OFF: + coex_sta->force_lps_ctrl = TRUE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b2ant_power_save_state == BTC_PS_LPS_OFF\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_ps_tdma_check_for_power_save_state( + btcoexist, FALSE); + result = btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + break; + default: + break; + } + + return result; +} + + + + +static +void halbtc8822b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = FALSE, result = FALSE; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if (byte5 & BIT(2)) + coex_sta->is_tdma_btautoslot = TRUE; + else + coex_sta->is_tdma_btautoslot = FALSE; + + /* release bt-auto slot for auto-slot hang is detected!! */ + if (coex_sta->is_tdma_btautoslot) + if ((coex_sta->is_tdma_btautoslot_hang) || + (bt_link_info->slave_role)) + byte5 = byte5 & 0xfb; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b2ant_set_fw_pstdma == FW for AP mode\n"); + BTC_TRACE(trace_buf); + + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + + halbtc8822b2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b2ant_set_fw_pstdma == Force LPS (byte1 = 0x%x)\n", byte1); + BTC_TRACE(trace_buf); + +#if 0 + halbtc8822b2ant_power_save_state( + btcoexist, BTC_PS_LPS_ON, 0x50, + 0x4); +#endif + if (!halbtc8822b2ant_power_save_state(btcoexist, BTC_PS_LPS_OFF, 0x50, 0x4)) + result = TRUE; + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b2ant_set_fw_pstdma == Native LPS (byte1 = 0x%x)\n", byte1); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, + 0x0); + } + + + coex_sta->is_set_ps_state_fail = result; + + if (!coex_sta->is_set_ps_state_fail) { + h2c_parameter[0] = real_byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = real_byte5; + + coex_dm->ps_tdma_para[0] = real_byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = real_byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); + + } else { + coex_sta->cnt_set_ps_state_fail++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b2ant_set_fw_pstdma == Force Leave LPS Fail (cnt = %d)\n", + coex_sta->cnt_set_ps_state_fail); + BTC_TRACE(trace_buf); + } +} + + +static +void halbtc8822b2ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ + if (bt_link_info->slave_role) + psTdmaByte4Modify = 0x1; + else + psTdmaByte4Modify = 0x0; + + if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { + force_exec = TRUE; + pre_psTdmaByte4Modify = psTdmaByte4Modify; + } + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n", + (coex_dm->cur_ps_tdma_on ? "on" : "off"), + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + return; + } + } + + if (coex_dm->cur_ps_tdma_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(on, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } + + + if (turn_on) { + switch (type) { + case 1: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x91, + 0x54 | psTdmaByte4Modify); + break; + case 2: + default: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); + break; + case 3: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x3a, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 4: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x21, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 5: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 6: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 7: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x20, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 8: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x15, 0x03, 0x11, + 0x11); + break; + case 10: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x30, 0x03, 0x11, + 0x10); + break; + case 11: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, + 0x10 | psTdmaByte4Modify); + break; + case 12: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, 0x11); + break; + case 13: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x1c, 0x03, 0x11, + 0x10 | psTdmaByte4Modify); + break; + case 14: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x20, 0x03, 0x11, + 0x11); + break; + case 15: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x14); + break; + case 16: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x15); + break; + case 21: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x30, 0x03, 0x11, + 0x10); + break; + case 22: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, + 0x10); + break; + case 23: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x10); + break; + case 51: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 101: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); + break; + case 102: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); + break; + case 103: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51, + 0x3a, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 104: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51, + 0x21, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 105: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 106: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 107: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x7, 0x10, + 0x54 | psTdmaByte4Modify); + break; + case 108: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 109: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x03, 0x10, + 0x54 | psTdmaByte4Modify); + break; + case 110: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x55, + 0x30, 0x03, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 111: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); + break; + case 151: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x03, 0x10, + 0x50 | psTdmaByte4Modify); + break; + } + } else { + /* disable PS tdma */ + switch (type) { +#if 0 +/* 08:1ant:PTA Control -0x778=1-ant hw control,40:2ant:sw control-diversity */ +#endif + + case 0: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x40, 0x0); + break; + default: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x40, 0x0); + break; + } + } + + if (!coex_sta->is_set_ps_state_fail) { + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; + } +} + +/*anttenna control by bb mac bt antdiv pta to write 0x4c 0xcb4,0xcbd*/ +static +void halbtc8822b2ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) +{ +#if 0 + struct btc_board_info *board_info = &btcoexist->board_info; +#endif + boolean switch_polatiry_inverse = FALSE; + u8 regval_0xcbc = 0, regval_0x64; +#if BT_8822B_2ANT_COEX_DBG + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; +#endif + + if (!rfe_type->ext_ant_switch_exist) + return; + + coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; + + if (!force_exec) { + if (coex_dm->pre_ext_ant_switch_status == + coex_dm->cur_ext_ant_switch_status) + return; + } + coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status; + +#if 0 + switch (pos_type) { + default: + case BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT: + case BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE: + break; + case BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG: + break; + case BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA: + break; + } +#endif + +#if 0 + if (board_info->ant_div_cfg) + ctrl_type = BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; +#endif + + /* Ext switch buffer mux */ + btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); + + + switch (ctrl_type) { + default: + case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as conctrol pin */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x77); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, + 0x03, 01); + + break; + case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as conctrol pin */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x66); + + /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse, + * DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1 + */ + regval_0xcbc = (!switch_polatiry_inverse ? 0x2 : 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbc, + 0x03, regval_0xcbc); + + break; + case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1);/* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff, 0x88); + break; + case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x1); /* 0x4c[23] = 1 */ + + /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, + * DPDT_SEL_N =1, DPDT_SEL_P =0 + */ + regval_0x64 = (!switch_polatiry_inverse ? 0x0 : 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, + regval_0x64); + break; + case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x0); /* 0x4c[24] = 0 */ + + /* no setup required, because antenna switch control value by + * BT vendor 0x1c[1:0] + */ + break; + } + + /* PAPE, LNA_ON control by BT while WLAN off for current leakage issue*/ + if (ctrl_type == BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT) { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x0); /* PAPE 0x64[29] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, + 0x0); /* LNA_ON 0x64[28] = 0 */ + } else { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x1); /* PAPE 0x64[29] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, + 0x1); /* LNA_ON 0x64[28] = 1 */ + } + +#if BT_8822B_2ANT_COEX_DBG + + u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (After Ext Ant switch setup) 0xcb4 = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n", + u32tmp1, u32tmp2, u32tmp3); + BTC_TRACE(trace_buf); +#endif + + + +} + +/* rf4 type by efuse, and for ant at main aux inverse use, + * because is 2x2, and control types are the same, does not need + */ +static +void halbtc8822b2ant_set_rfe_type(IN struct btc_coexist *btcoexist) +{ + + struct btc_board_info *board_info = &btcoexist->board_info; + + + rfe_type->ext_band_switch_exist = FALSE; + rfe_type->ext_band_switch_type = + BT_8822B_2ANT_EXT_BAND_SWITCH_USE_SPDT; /* SPDT; */ + rfe_type->ext_band_switch_ctrl_polarity = 0; + /* Ext switch buffer mux */ + btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); + + if (rfe_type->ext_band_switch_exist) { + + /* band switch use RFE_ctrl1 (pin name: PAPE_A) and + * RFE_ctrl3 (pin name: LNAON_A) + */ + + /* set RFE_ctrl1 as software control */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb0, 0xf0, 0x7); + + /* set RFE_ctrl3 as software control */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb1, 0xf0, 0x7); + + } + + + /* the following setup should be got from Efuse in the future */ + rfe_type->rfe_module_type = board_info->rfe_type; + + rfe_type->ext_ant_switch_ctrl_polarity = 0; + + switch (rfe_type->rfe_module_type) { + case 0: + default: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 1: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 2: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 3: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 4: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 5: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 6: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + case 7: + rfe_type->ext_ant_switch_exist = TRUE; +rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT; + break; + } + +#if 0 + + if (rfe_type->wlg_Locate_at_btg) + halbtc8822b2ant_set_int_block(btcoexist, FORCE_EXEC, + BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); + else + halbtc8822b2ant_set_int_block(btcoexist, FORCE_EXEC, + BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); +#endif + +} + +/* set gnt_wl gnt_bt control by sw high low, or hwpta while in + * power on, ini, wlan off, wlan only, wl2g non-currrent, wl2g current, wl5g + */ +static +void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean force_exec, + IN u8 phase) +{ +#if BT_8822B_2ANT_COEX_DBG + u8 u8tmp = 0; +#endif + u32 u32tmp1 = 0; +#if BT_8822B_2ANT_COEX_DBG + u32 u32tmp2 = 0, u32tmp3 = 0; +#endif + + u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + /* To avoid indirect access fail */ + if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { + force_exec = TRUE; + coex_sta->gnt_error_cnt++; + } + + /* Ext switch buffer mux */ + btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + + coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; + + if (!force_exec) { + if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) + return; + } + + coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; + +#if BT_8822B_2ANT_COEX_DBG + u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + u32tmp2 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, + 0x54); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + u32tmp3, u8tmp, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); +#endif + + switch (phase) { + case BT_8822B_2ANT_PHASE_COEX_POWERON: + + /* set Path control owner to WL at initial step */ + halbtc8822b2ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8822B_2ANT_PCO_BTSIDE); + + /* set GNT_BT to SW high */ + halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW high */ + halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = FALSE; + + break; + case BT_8822B_2ANT_PHASE_COEX_INIT: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + /* Disable LTE Coex Function in WiFi side + * (this should be on if LTE coex is required) + */ + halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8822b2ant_ltecoex_set_coex_table( + btcoexist, + BT_8822B_2ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8822b2ant_ltecoex_set_coex_table( + btcoexist, + BT_8822B_2ANT_CTT_BT_VS_LTE, + 0xffff); + + /* set Path control owner to WL at initial step */ + halbtc8822b2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8822B_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW high */ + halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW high */ + halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = FALSE; + + break; + case BT_8822B_2ANT_PHASE_WLANONLY_INIT: + /* Disable LTE Coex Function in WiFi side + * (this should be on if LTE coex is required) + */ + halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8822b2ant_ltecoex_set_coex_table( + btcoexist, + BT_8822B_2ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8822b2ant_ltecoex_set_coex_table( + btcoexist, + BT_8822B_2ANT_CTT_BT_VS_LTE, + 0xffff); + + /* set Path control owner to WL at initial step */ + halbtc8822b2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8822B_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Low */ + halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_LOW); + /* Set GNT_WL to SW high */ + halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = FALSE; + + + break; + case BT_8822B_2ANT_PHASE_WLAN_OFF: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x0); /* 0x4c[24] = 0 */ + /* Disable LTE Coex Function in WiFi side */ + halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0); + + /* set Path control owner to BT */ + halbtc8822b2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8822B_2ANT_PCO_BTSIDE); + + /* Set Ext Ant Switch to BT control at wifi off step */ + halbtc8822b2ant_set_ext_ant_switch(btcoexist, + FORCE_EXEC, + BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT, + BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE); + coex_sta->run_time_state = FALSE; + break; + case BT_8822B_2ANT_PHASE_2G_RUNTIME: + case BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT: + + /* set Path control owner to WL at runtime step */ + halbtc8822b2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8822B_2ANT_PCO_WLSIDE); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x66); + if (phase == + BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT) { + /* set GNT_BT to PTA */ + halbtc8822b2ant_ltecoex_set_gnt_bt( + btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8822B_2ANT_SIG_STA_SET_BY_HW); + + /* Set GNT_WL to SW High */ + halbtc8822b2ant_ltecoex_set_gnt_wl( + btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + } else { + /* set GNT_BT to PTA */ + halbtc8822b2ant_ltecoex_set_gnt_bt( + btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8822B_2ANT_SIG_STA_SET_BY_HW); + + /* Set GNT_WL to PTA */ + halbtc8822b2ant_ltecoex_set_gnt_wl( + btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8822B_2ANT_SIG_STA_SET_BY_HW); + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ************* under2g 0xcbd setting =2 *************\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 02); + break; + + case BT_8822B_2ANT_PHASE_5G_RUNTIME: + + /* set Path control owner to WL at runtime step */ + halbtc8822b2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8822B_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Hi */ + halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW Hi */ + halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + coex_sta->run_time_state = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ************* under5g 0xcbd setting =1 *************\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, + 0x03, 01); + + break; + case BT_8822B_2ANT_PHASE_BTMPMODE: + /* Disable LTE Coex Function in WiFi side */ + halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0); + + /* set Path control owner to WL */ + halbtc8822b2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8822B_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Hi */ + halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + + /* Set GNT_WL to SW Lo */ + halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_LOW); + + coex_sta->run_time_state = FALSE; + break; + } +#if BT_8822B_2ANT_COEX_DBG + u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (After Ant-Setup phase---%d) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + phase, u32tmp3, u8tmp, u32tmp1, u32tmp2); + + BTC_TRACE(trace_buf); +#endif + +} + + +static +void halbtc8822b2ant_set_rx_gain(IN struct btc_coexist *btcoexist, + IN boolean agc_table_en) +{ + u8 rssi_adjust_val = 0; + + /* =================BB AGC Gain Table */ + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table On!\n"); + BTC_TRACE(trace_buf); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + btcoexist->btc_write_1byte(btcoexist, 0xc5b, 0xc8); + btcoexist->btc_write_1byte(btcoexist, 0xe5b, 0xc8); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xff000003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xae2e0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xad300003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xac320003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xab360003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8d380003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8c3a0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8b3c0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8a3e0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6e400003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6d420003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6c440003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6b460003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6a480003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x694a0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x684c0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x674e0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x66500003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x65520003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x64540003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x64560003); + + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x007e0403); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table Off!\n"); + BTC_TRACE(trace_buf); + coex_dm->is_switch_to_1dot5_ant = TRUE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + btcoexist->btc_write_1byte(btcoexist, 0xc5b, 0xd8); + btcoexist->btc_write_1byte(btcoexist, 0xe5b, 0xd8); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xff000003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xe62e0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xe5300003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc8320003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc6360003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc5380003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc43a0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc33c0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc23e0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc1400003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc0420003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa5440003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa4460003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa3480003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa24a0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa14c0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x834e0003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x82500003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x81520003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x80540003); + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x65560003); + + btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x007e0403); + } + +} + + +static +void halbtc8822b2ant_rx_gain(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean agc_table_en) +{ + coex_dm->cur_agc_table_en = agc_table_en; + + if (!force_exec) { + if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) + return; + } + halbtc8822b2ant_set_rx_gain(btcoexist, agc_table_en); + + coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; +} + + +static +u8 halbtc8822b2ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = FALSE; + u8 algorithm = BT_8822B_2ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 0) { + + if (bt_link_info->acl_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No-Profile busy\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY; + } + } else if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP Sink\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_2ANT_COEX_ALGO_A2DPSINK; + } else if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_2ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_2ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_2ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_2ANT_COEX_ALGO_SCO; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP ==> A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_2ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_2ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_PANEDR; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_HID_A2DP; + } + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_2ANT_COEX_ALGO_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP ==> HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8822B_2ANT_COEX_ALGO_HID_A2DP; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_PANEDR_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + + return algorithm; +} + + +static +void halbtc8822b2ant_action_coex_all_off(IN struct btc_coexist *btcoexist) +{ + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + +#if 0 + /*halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);*/ +#endif + + /* fw all off */ + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif + +} + +static +void halbtc8822b2ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) +{ + + /* fw all off */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ************* under5g *************\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_5G_RUNTIME); + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif + +} + +static +void halbtc8822b2ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist) +{ +#if 0 + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 2); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); +#endif + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + +} + + +static +void halbtc8822b2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + + boolean wifi_connected = FALSE; + boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE; + boolean wifi_busy = FALSE; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) + || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 8); + + if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 15); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 11); + } else if ((!wifi_connected) && (!wifi_scan)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi no-link + no-scan + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (bt_link_info->pan_exist) { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + + + } else if (bt_link_info->a2dp_exist) { +#if 0 + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16); + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); +#endif + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 10); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8); + + } else { + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) + || (coex_sta->wifi_is_high_pri_task)) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 23); + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + } + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif +} + +static +void halbtc8822b2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd4); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + if (bt_link_info->pan_exist) { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + + } else if (bt_link_info->a2dp_exist) { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16); + + } else { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); + + } + +} + +static +void halbtc8822b2ant_action_wifi_nonconnected(IN struct btc_coexist *btcoexist) +{ + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +#if 0 + /*halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);*/ +#endif + + /* fw all off */ + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif +} + +static +void halbtc8822b2ant_action_bt_relink(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], run bt multi link function\n"); + BTC_TRACE(trace_buf); + + if (coex_sta->is_bt_multi_link) + return; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], run bt re-link function\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + +} + +static +void halbtc8822b2ant_action_bt_idle(IN struct btc_coexist *btcoexist) +{ + + boolean wifi_busy = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_busy) { + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 14); + } else { /* if wl busy */ + + if (BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, + 0); + } else { + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 8); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 12); + } + } + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif +} + +/* SCO only or SCO+PAN(HS) */ +static +void halbtc8822b2ant_action_sco(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres , 0); + + wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + /*halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);*/ + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_5G_RUNTIME); + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + } else { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + if (coex_sta->is_eSCO_mode) + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + else /* 2-Ant free run if SCO mode */ + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8); + } + +} + + +static +void halbtc8822b2ant_action_hid(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; + u32 wifi_bw = 1; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + /*halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);*/ + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_5G_RUNTIME); + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + } else { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + if (coex_sta->is_hid_low_pri_tx_overhead) { + + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 108); + } else if (wifi_bw == 0) { /* if 11bg mode */ + + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 111); + } else { + + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 111); + } + } + +} + + +static +void halbtc8822b2ant_action_a2dpsink(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; +#if 0 + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); +#endif + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; +#endif + + wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + /*halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);*/ + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_5G_RUNTIME); + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 1); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 16); + } else { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + if ((coex_sta->bt_relink_downcount != 0) + && (wifi_busy)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + + } else { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 105); + } + + } + +} + +/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ +static +void halbtc8822b2ant_action_a2dp(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; + + wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + /*halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);*/ + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_5G_RUNTIME); + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 1); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 16); + } else { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + if ((coex_sta->bt_relink_downcount != 0) + && (wifi_busy)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + + } else { + + if (wifi_turbo) + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 10); + else + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 10); +#if 0 +halbtc8822b2ant_coex_table_with_type(btcoexist, +NORMAL_EXEC, +7); +#endif + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 109); + } + + } + +} + + +static +void halbtc8822b2ant_action_pan_edr(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; +#endif + + wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + +#if 0 + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); +#endif + + +#if 1 + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 3); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 4); + } else { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + + if (wifi_busy) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 103); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 104); + } + +#endif + +} + +static +void halbtc8822b2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + /*halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);*/ + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_5G_RUNTIME); + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 1); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 16); + } else { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + if ((coex_sta->bt_relink_downcount != 0) + && (wifi_busy)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + } else { + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 109); + } + } + +} + +static +void halbtc8822b2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; +#endif + + + wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);*/ + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) { + + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 7); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 5); + } else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 6); + + } else { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + if (wifi_turbo) + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + else + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 7); + + if (wifi_busy) { + + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 107); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 105); + } else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 106); + + } + +} + + + + +/* PAN(EDR)+A2DP */ +static +void halbtc8822b2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; + + wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) { + + if (((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) || + (!coex_sta->is_A2DP_3M)) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 7); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 5); + } else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 6); + } else { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 8); + if (wifi_busy) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 107); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 106); + } + +} + + +static +void halbtc8822b2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 3); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 4); + } else { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + if (wifi_busy) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 103); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 104); + } + +} + + +/* HID+A2DP+PAN(EDR) */ +static +void halbtc8822b2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) { + + if (((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) || + (!coex_sta->is_A2DP_3M)) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 7); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 5); + } else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 6); + } else { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + if (coex_sta->hid_busy_num >= 2) { + halbtc8822b2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + + if (wifi_bw == 0) { + halbtc8822b2ant_set_wltoggle_coex_table( + btcoexist, + NORMAL_EXEC, + 0x1, 0xaa, + 0x5a, 0xaa, + 0xaa); + } + else + halbtc8822b2ant_set_wltoggle_coex_table( + btcoexist, + NORMAL_EXEC, + 0x2, 0xaa, + 0x5a, 0xaa, + 0xaa); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 110); + } else { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + + if (wifi_busy) { + + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 107); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 105); + } else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 106); + } + } + +} + +static +void halbtc8822b2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) +{ + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +#if 0 + /*halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);*/ +#endif + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); +} + +static +void halbtc8822b2ant_action_bt_hs(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; +#endif + + + wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + + + } else { + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } + +} + +static +void halbtc8822b2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif + + /* hw all off */ + /*halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);*/ + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_5G_RUNTIME); + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + +#if 0 + /*halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);*/ +#endif + + /*halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);*/ +} + +static +void halbtc8822b2ant_action_wifi_connected(IN struct btc_coexist *btcoexist) + { + switch (coex_dm->cur_algorithm) { + + case BT_8822B_2ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_sco(btcoexist); + break; + case BT_8822B_2ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID.\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_hid(btcoexist); + break; + case BT_8822B_2ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_a2dp(btcoexist); + break; + case BT_8822B_2ANT_COEX_ALGO_A2DPSINK: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP Sink.\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_a2dpsink(btcoexist); + break; + case BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_a2dp_pan_hs(btcoexist); + break; + case BT_8822B_2ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_pan_edr(btcoexist); + break; + case BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_pan_edr_a2dp(btcoexist); + break; + case BT_8822B_2ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_pan_edr_hid(btcoexist); + break; + case BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_hid_a2dp_pan_edr( + btcoexist); + break; + case BT_8822B_2ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_hid_a2dp(btcoexist); + break; + case BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_bt_idle(btcoexist); + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_action_coex_all_off(btcoexist); + break; + } + + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + + } + +static +void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + u8 algorithm = 0; + u32 num_of_wifi_link = 0; + u32 wifi_link_status = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean miracast_plus_bt = FALSE; + boolean scan = FALSE, link = FALSE, roam = FALSE, + under_4way = FALSE, + wifi_connected = FALSE, wifi_under_5g = + FALSE, + bt_hs_on = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if ((coex_sta->under_lps) && + (coex_dm->bt_status != BT_8822B_2ANT_BT_STATUS_ACL_BUSY)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_wifi_native_lps(btcoexist); + return; + } + + if (!coex_sta->run_time_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], return for run_time_state = FALSE !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->freeze_coexrun_by_btinfo) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((wifi_under_5g) && + (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G) && + (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G_NOFORSCAN)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_action_wifi_under5g(btcoexist); + return; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 2G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME); + + + if (coex_sta->bt_whck_test) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under WHCK TEST!!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_bt_whck_test(btcoexist); + return; + } + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled!!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_action_coex_all_off(btcoexist); + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_action_bt_inquiry(btcoexist); + return; + } + + if (coex_sta->is_setupLink) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is re-link !!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_action_bt_relink(btcoexist); + return; + } + + /* for P2P */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", + num_of_wifi_link, wifi_link_status); + BTC_TRACE(trace_buf); + + if (bt_link_info->bt_link_exist) + miracast_plus_bt = TRUE; + else + miracast_plus_bt = FALSE; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_action_wifi_link_process(btcoexist); + } else { + halbtc8822b2ant_action_wifi_multi_port(btcoexist); + } + + return; + } + + miracast_plus_bt = FALSE; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is hs\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_bt_hs(btcoexist); + return; + } + + if ((BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) || + (BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, bt idle!!.\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_action_bt_idle(btcoexist); + return; + } + + algorithm = halbtc8822b2ant_action_algorithm(btcoexist); + coex_dm->cur_algorithm = algorithm; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", + coex_dm->cur_algorithm); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under Link Process !!\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_wifi_link_process(btcoexist); + } else if (wifi_connected) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, wifi connected!!.\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_wifi_connected(btcoexist); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, wifi not-connected!!.\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_wifi_nonconnected(btcoexist); + } +} + +static +void halbtc8822b2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); +#if 0 + /*halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);*/ +#endif + + /* fw all off */ + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + + halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); +#if 0 + /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +#endif + + coex_sta->pop_event_cnt = 0; + coex_sta->cnt_RemoteNameReq = 0; + coex_sta->cnt_ReInit = 0; + coex_sta->cnt_setupLink = 0; + coex_sta->cnt_IgnWlanAct = 0; + coex_sta->cnt_Page = 0; + coex_sta->cnt_RoleSwitch = 0; + coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; + + halbtc8822b2ant_query_bt_info(btcoexist); +} + + +static +void halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + u32 RTL97F_8822B = 0; + u8 i = 0; + + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + if (RTL97F_8822B) { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, 0x04, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x0); + + /* set GNT_BT to SW high */ + halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW high */ + halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_2ANT_GNT_BLOCK_RFC_BB, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + return; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + u32tmp3, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 2Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + coex_sta->isolation_btween_wb = BT_8822B_2ANT_DEFAULT_ISOLATION; + coex_sta->gnt_error_cnt = 0; + coex_sta->bt_relink_downcount = 0; + coex_sta->is_set_ps_state_fail = FALSE; + coex_sta->cnt_set_ps_state_fail = 0; + + for (i = 0; i <= 9; i++) + coex_sta->bt_afh_map[i] = 0; + + /* 0xf0[15:12] --> Chip Cut information */ + coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, + 0xf1) & 0xf0) >> 4; + + coex_sta->dis_ver_info_cnt = 0; + + halbtc8822b2ant_coex_switch_threshold(btcoexist, + coex_sta->isolation_btween_wb); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + + /* BT report packet sample rate */ + btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); + + /* Init 0x778 = 0x1 for 2-Ant */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + + /* Enable PTA (3-wire function form BT side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); + + /* Enable PTA (tx/rx signal form WiFi side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); + + halbtc8822b2ant_enable_gnt_to_gpio(btcoexist, TRUE); + + /*GNT_BT=1 while select both */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1); + + + /* check if WL firmware download ok */ +#if 0 + if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) +#endif + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ONOFF, TRUE); + + /* Enable counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, + 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ + +#if 0 + /* WLAN_Tx by GNT_WL 0x950[29] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0); +#endif + + halbtc8822b2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 5); + + halbtc8822b2ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); + + psd_scan->ant_det_is_ant_det_available = TRUE; + + if (coex_sta->is_rf_state_off) { + + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_WLAN_OFF); + + btcoexist->stop_coex_dm = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** halbtc8822b2ant_init_hw_config (RF Off)**********\n"); + BTC_TRACE(trace_buf); + } else if (wifi_only) { + coex_sta->concurrent_rx_mode_on = FALSE; + /* Path config */ + /* Set Antenna Path */ + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_WLANONLY_INIT); + + btcoexist->stop_coex_dm = TRUE; + } else { + /* Set BT polluted packet on for Tx rate adaptive not including + * Tx retry break by PTA, 0x45c[19] =1 + */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); + + coex_sta->concurrent_rx_mode_on = TRUE; +#if 0 + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); +#endif + + /* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 for + * con-current Rx, mask Tx only + */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0); + + /* Set Antenna Path */ + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_COEX_INIT); + + btcoexist->stop_coex_dm = FALSE; + } +} + + + +/* ************************************************************ + * work around function start with wa_halbtc8822b2ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8822b2ant_ + * ************************************************************ */ +void ex_halbtc8822b2ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x0; + u16 u16tmp = 0x0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx Execute 8822b 2-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "Ant Det Finish = %s, Ant Det Number = %d\n", + (board_info->btdm_ant_det_finish ? "Yes" : "No"), + board_info->btdm_ant_num_by_ant_det); + BTC_TRACE(trace_buf); + + + btcoexist->stop_coex_dm = TRUE; + psd_scan->ant_det_is_ant_det_available = FALSE; + + /* enable BB, REG_SYS_FUNC_EN such that we can write BB Reg correctly */ + u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); + btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); + + + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> + * BIT1=0 and BIT2=0 + */ + + /* Check efuse 0xc3[6] for Single Antenna Path */ +#if 0 + if (board_info->single_ant_path == 0) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Single Antenna, Antenna at Aux Port\n"); + BTC_TRACE(trace_buf); + + board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; + + u8tmp = 7; + } else if (board_info->single_ant_path == 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Single Antenna, Antenna at Main Port\n"); + BTC_TRACE(trace_buf); + + board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; + + u8tmp = 6; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d\n", + board_info->single_ant_path , board_info->btdm_ant_pos); + BTC_TRACE(trace_buf); +#endif + + /* Setup RF front end type */ + halbtc8822b2ant_set_rfe_type(btcoexist); + + /* Set Antenna Path to BT side */ + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_COEX_POWERON); + + /* Save"single antenna position" info in Local register setting for + * FW reading, because FW may not ready at power on + */ + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_USB) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); + + /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ + halbtc8822b2ant_enable_gnt_to_gpio(btcoexist, TRUE); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n", + halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38)); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcb4 (Power-On) = 0x%x / 0x%x\n", + btcoexist->btc_read_4byte(btcoexist, 0x70), + btcoexist->btc_read_4byte(btcoexist, 0xcb4)); + BTC_TRACE(trace_buf); + +} + +void ex_halbtc8822b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ + + /* */ + /* S0 or S1 setting and Local register setting + * (By the setting fw can get ant number, S0/S1, ... info) + */ + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> + * BIT1=0 and BIT2=0 + */ + if (btcoexist->chip_interface == BTC_INTF_USB) { + /* fixed at S0 for USB interface */ + u8tmp |= 0x1; /* antenna inverse */ + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + } else { + /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ + if (board_info->single_ant_path == 0) { + } else if (board_info->single_ant_path == 1) { + /* set to S0 */ + u8tmp |= 0x1; /* antenna inverse */ + } + + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, + u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, + u8tmp); + } +} + +void ex_halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8822b2ant_init_hw_config(btcoexist, wifi_only); +} + +void ex_halbtc8822b2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + + halbtc8822b2ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, ps_tdma_case = 0; + u32 u32tmp[4]; + u16 u16tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck, ratio_ofdm; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + static u8 pop_report_in_10s = 0; + u32 phyver = 0; + boolean lte_coex_on = FALSE; + static u8 cnt = 0; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->bt_coex_supported_feature == 0) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + if (coex_sta->bt_reg_vendor_ac == 0xffff) + coex_sta->bt_reg_vendor_ac = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xac) & 0xffff); + + if (coex_sta->bt_reg_vendor_ae == 0xffff) + coex_sta->bt_reg_vendor_ae = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xae) & 0xffff); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, + &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) { + cnt++; + + if (cnt >= 3) { + btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, + &coex_sta->bt_afh_map[0]); + cnt = 0; + } + } + } + + if (psd_scan->ant_det_try_count == 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s / %d", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, board_info->btdm_ant_num, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type); + CL_PRINTF(cli_buf); + } else { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", + "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", + board_info->pg_ant_num, + board_info->btdm_ant_num_by_ant_det, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type, + psd_scan->ant_det_try_count, + psd_scan->ant_det_fail_count, + psd_scan->ant_det_result); + CL_PRINTF(cli_buf); + + + if (board_info->btdm_ant_det_finish) { + + if (psd_scan->ant_det_result != 12) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", + "Ant Det PSD Value", + psd_scan->ant_det_peak_val); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d", + "Ant Det PSD Value", + psd_scan->ant_det_psd_scan_peak_val + / 100); + CL_PRINTF(cli_buf); + } + } + + + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + + bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8822b_2ant, glcoex_ver_8822b_2ant, + glcoex_ver_btdesired_8822b_2ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8822b_2ant ? + "Match" : "Mis-Match")))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "AFH Map to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ", + "Isolation/WL_Thres/BT_Thres", + coex_sta->isolation_btween_wb, + coex_sta->wifi_coex_thres, + coex_sta->bt_coex_thres); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + pop_report_in_10s++; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", + "BT [status/ rssi/ retryCnt/ popCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + : ((BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, + coex_sta->pop_event_cnt); + CL_PRINTF(cli_buf); + + if (pop_report_in_10s >= 5) { + coex_sta->pop_event_cnt = 0; + pop_report_in_10s = 0; + } + + + if (coex_sta->num_of_profile != 0) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s%s%s%s%s", + "Profiles", + ((bt_link_info->a2dp_exist) ? + ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," : + "A2DP,") : ""), + ((bt_link_info->sco_exist) ? "HFP," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : + "HID(2/18),") : ""), + ((bt_link_info->pan_exist) ? "PAN," : ""), + ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = None", "Profiles"); + + CL_PRINTF(cli_buf); + + + if (bt_link_info->a2dp_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", + "A2DP Rate/Bitpool/Auto_Slot", + ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), + coex_sta->a2dp_bit_pool, + ((coex_sta->is_autoslot) ? "On" : "Off") + ); + CL_PRINTF(cli_buf); + } + + if (bt_link_info->hid_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "HID PairNum/Forbid_Slot", + coex_sta->hid_pair_cnt, + coex_sta->forbidden_slot + ); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x", + "Role/RoleSwCnt/IgnWlact/Feature", + ((bt_link_info->slave_role) ? "Slave" : "Master"), + coex_sta->cnt_RoleSwitch, + ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), + coex_sta->bt_coex_supported_feature); + CL_PRINTF(cli_buf); + + if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "BLEScan Type/TV/Init/Ble", + coex_sta->bt_ble_scan_type, + (coex_sta->bt_ble_scan_type & 0x1 ? + coex_sta->bt_ble_scan_para[0] : 0x0), + (coex_sta->bt_ble_scan_type & 0x2 ? + coex_sta->bt_ble_scan_para[1] : 0x0), + (coex_sta->bt_ble_scan_type & 0x4 ? + coex_sta->bt_ble_scan_para[2] : 0x0)); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "ReInit/ReLink/IgnWlact/Page/NameReq", + coex_sta->cnt_ReInit, + coex_sta->cnt_setupLink, + coex_sta->cnt_IgnWlanAct, + coex_sta->cnt_Page, + coex_sta->cnt_RemoteNameReq + ); + CL_PRINTF(cli_buf); + + halbtc8822b2ant_read_score_board(btcoexist, &u16tmp[0]); + + if ((coex_sta->bt_reg_vendor_ae == 0xffff) || + (coex_sta->bt_reg_vendor_ac == 0xffff)) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", + (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), + coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); + CL_PRINTF(cli_buf); + + if (coex_sta->num_of_profile > 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + "AFH MAP", + coex_sta->bt_afh_map[0], + coex_sta->bt_afh_map[1], + coex_sta->bt_afh_map[2], + coex_sta->bt_afh_map[3], + coex_sta->bt_afh_map[4], + coex_sta->bt_afh_map[5], + coex_sta->bt_afh_map[6], + coex_sta->bt_afh_map[7], + coex_sta->bt_afh_map[8], + coex_sta->bt_afh_map[9] + ); + CL_PRINTF(cli_buf); + } + + for (i = 0; i < BT_INFO_SRC_8822B_2ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8822b_2ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + /* Sw mechanism */ + if (btcoexist->manual_control) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanism] (before Manual)============"); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Mechanism]============"); + + CL_PRINTF(cli_buf); + + + ps_tdma_case = coex_dm->cur_ps_tdma; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, %s)", + "TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"), + (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant")); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", + "Table/0x6c0/0x6c4/0x6c8", + coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x", + "0x778/0x6cc", + u8tmp[0], u32tmp[0]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "AntDiv/BtCtrlLPS/LPRA/PsFail", + ((board_info->ant_div_cfg) ? "On" : "Off"), + ((coex_sta->force_lps_ctrl) ? "On" : "Off"), + ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"), + coex_sta->cnt_set_ps_state_fail); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "WL_DACSwing/ BT_Dec_Pwr", coex_dm->cur_fw_dac_swing_lvl, + coex_dm->cur_bt_dec_pwr_lvl); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? TRUE : FALSE; + + if (lte_coex_on) { + + u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, + 0xa0); + u32tmp[1] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, + 0xa4); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "LTE Coex Table W_L/B_L", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + CL_PRINTF(cli_buf); + + + u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, + 0xa8); + u32tmp[1] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, + 0xac); + u32tmp[2] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, + 0xb0); + u32tmp[3] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, + 0xb4); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "LTE Break Table W_L/B_L/L_W/L_B", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, + u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); + CL_PRINTF(cli_buf); + + } + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp[1] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", + "LTE Coex/Path Owner", + ((lte_coex_on) ? "On" : "Off"), + ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); + CL_PRINTF(cli_buf); + + if (lte_coex_on) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %d/ %d", + "LTE 3Wire/OPMode/UART/UARTMode", + (int)((u32tmp[0] & BIT(6)) >> 6), + (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), + (int)((u32tmp[0] & BIT(3)) >> 3), + (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "LTE_Busy/UART_Busy", + (int)((u32tmp[1] & BIT(1)) >> 1), + (int)(u32tmp[1] & BIT(0))); + CL_PRINTF(cli_buf); + } + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", + ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), + ((u8tmp[0] & BIT(3)) ? "On" : "Off"), + coex_sta->gnt_error_cnt); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "GNT_WL/GNT_BT", + (int)((u32tmp[1] & BIT(2)) >> 2), + (int)((u32tmp[1] & BIT(3)) >> 3)); + CL_PRINTF(cli_buf); + + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcbc); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s", + "0xcbc/0xcb4/0xcb8[23:16]", + u32tmp[0], u32tmp[1], u8tmp[0], + ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "4c[24:23]/64[0]/4c6[4]/40[5]", + (int)(u32tmp[0] & (BIT(24) | BIT(23))) >> 23, u8tmp[2] & 0x1, + (int)((u8tmp[0] & BIT(4)) >> 4), + (int)((u8tmp[1] & BIT(5)) >> 5)); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x", + "0x550/0x522/4-RxAGC/0xc50", + u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_CCK); + + ratio_ofdm = (fa_ofdm == 0) ? 1000 : (cca_ofdm/fa_ofdm); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x (%d)", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm, + ratio_ofdm); + CL_PRINTF(cli_buf); + +#if 1 + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11ac", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d (%d, %d)", + "CRC_Err CCK/11g/11n/11ac", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht, + coex_sta->now_crc_ratio, coex_sta->acc_crc_ratio); + CL_PRINTF(cli_buf); +#endif + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "WlHiPri/ Locking/ Locked/ Noisy", + (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + (coex_sta->cck_lock ? "Yes" : "No"), + (coex_sta->cck_ever_lock ? "Yes" : "No"), + coex_sta->wl_noisy_level); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : ( + coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); + CL_PRINTF(cli_buf); + + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +void ex_halbtc8822b2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = TRUE; + coex_sta->under_lps = FALSE; + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE); + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ONOFF, FALSE); + + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_WLAN_OFF); + + halbtc8822b2ant_action_coex_all_off(btcoexist); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = FALSE; + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ONOFF, TRUE); + halbtc8822b2ant_init_hw_config(btcoexist, FALSE); + halbtc8822b2ant_init_coex_dm(btcoexist); + halbtc8822b2ant_query_bt_info(btcoexist); + } +} + + + +void ex_halbtc8822b2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + static boolean pre_force_lps_on = FALSE; + + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = TRUE; + coex_sta->under_ips = FALSE; + + if (coex_sta->force_lps_ctrl) { /* LPS No-32K */ + /* Write WL "Active" in Score-board for PS-TDMA */ + pre_force_lps_on = TRUE; + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); + + } else { + /* LPS-32K, need check if this h2c 0x71 can work?? + * (2015/08/28) + */ + /* Write WL "Non-Active" in Score-board for Native-PS */ + pre_force_lps_on = FALSE; + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE); + } + + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = FALSE; + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); + + if ((!pre_force_lps_on) && (!coex_sta->force_lps_ctrl)) + halbtc8822b2ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8822b2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = FALSE; + boolean wifi_under_5g = FALSE; + + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN notify()\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* this can't be removed for RF off_on event, or BT would dis-connect */ + halbtc8822b2ant_query_bt_info(btcoexist); + + if (BTC_SCAN_START == type) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, + &wifi_under_5g); + + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** SCAN START notify (5g)\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_action_wifi_under5g(btcoexist); + return; + } + + coex_sta->wifi_is_high_pri_task = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** SCAN START notify (2g)\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_run_coexist_mechanism( + btcoexist); + + return; + } + + + if (BTC_SCAN_START_2G == type) { + + if (!wifi_connected) + coex_sta->wifi_is_high_pri_task = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_SCAN, TRUE); + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); + + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME); + + halbtc8822b2ant_run_coexist_mechanism(btcoexist); + + } else if (BTC_SCAN_FINISH == type) { + + coex_sta->wifi_is_high_pri_task = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", + coex_sta->scan_ap_num); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_SCAN, FALSE); + + halbtc8822b2ant_run_coexist_mechanism(btcoexist); + } + +} + +void ex_halbtc8822b2ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + coex_sta->switch_band_notify_to = type; + + if (type == BTC_SWITCH_TO_5G) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], switchband_notify --- switch to 5G\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_action_wifi_under5g(btcoexist); + + } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** switchband_notify BTC_SWITCH_TO_2G (no for scan)\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_run_coexist_mechanism(btcoexist); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], switchband_notify --- switch to 2G\n"); + BTC_TRACE(trace_buf); + + ex_halbtc8822b2ant_scan_notify(btcoexist, + BTC_SCAN_START_2G); + } + coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; +} + + +void ex_halbtc8822b2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + if ((BTC_ASSOCIATE_5G_START == type) || + (BTC_ASSOCIATE_5G_FINISH == type)) { + + if (BTC_ASSOCIATE_5G_START == type) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], connect_notify --- 5G start\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], connect_notify --- 5G finish\n"); + + BTC_TRACE(trace_buf); + + halbtc8822b2ant_action_wifi_under5g(btcoexist); + return; + } + + + if (BTC_ASSOCIATE_START == type) { + + coex_sta->wifi_is_high_pri_task = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME); + + halbtc8822b2ant_action_wifi_link_process(btcoexist); + + /* To keep TDMA case during connect process, + * to avoid changed by Btinfo and runcoexmechanism + */ + coex_sta->freeze_coexrun_by_btinfo = TRUE; + + coex_dm->arp_cnt = 0; + + } else if (BTC_ASSOCIATE_FINISH == type) { + + coex_sta->wifi_is_high_pri_task = FALSE; + coex_sta->freeze_coexrun_by_btinfo = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_run_coexist_mechanism(btcoexist); + } +} + +void ex_halbtc8822b2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_under_b_mode = FALSE, wifi_under_5g = FALSE; + + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (BTC_MEDIA_CONNECT == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_action_wifi_under5g(btcoexist); + return; + } + + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x00); /* CCK Rx */ + } else { + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x10); /* CCK Rx */ + } + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE); + } + + + halbtc8822b2ant_update_wifi_channel_info(btcoexist, type); +} + +void ex_halbtc8822b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean under_4way = FALSE, wifi_under_5g = FALSE; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_action_wifi_under5g(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (under_4way) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ---- under_4way!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = TRUE; + coex_sta->specific_pkt_period_cnt = 2; + + } else if (BTC_PACKET_ARP == type) { + + coex_dm->arp_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ARP notify -cnt = %d\n", + coex_dm->arp_cnt); + BTC_TRACE(trace_buf); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", + type); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = TRUE; + coex_sta->specific_pkt_period_cnt = 2; + } + + if (coex_sta->wifi_is_high_pri_task) + halbtc8822b2ant_run_coexist_mechanism(btcoexist); + +} + + +void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 i, rsp_source = 0; + boolean wifi_connected = FALSE; + boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE, + wifi_busy = FALSE; + static boolean is_scoreboard_scan = FALSE; + + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8822B_2ANT_MAX) + rsp_source = BT_INFO_SRC_8822B_2ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; + coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; + coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; + + if (BT_INFO_SRC_8822B_2ANT_WIFI_FW != rsp_source) { + + /* if 0xff, it means BT is under WHCK test */ + coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? TRUE : + FALSE); + + coex_sta->bt_create_connection = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE : + FALSE); + + /* unit: %, value-100 to translate to unit: dBm */ + coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + + 10; + + coex_sta->c2h_bt_remote_name_req = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE : + FALSE); + + coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & + 0x10) ? TRUE : FALSE); + + coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & + 0x9) ? TRUE : FALSE); + + coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? + TRUE : FALSE); + + coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & + BT_INFO_8822B_2ANT_B_INQ_PAGE) ? TRUE : FALSE); + + coex_sta->a2dp_bit_pool = ((( + coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? + (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) : 0); + + coex_sta->is_bt_a2dp_sink = (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ? + TRUE : FALSE; + + coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & + 0xf; + + coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; + + coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; + + coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; + + coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; + + if (coex_sta->bt_retry_cnt >= 1) + coex_sta->pop_event_cnt++; + + if (coex_sta->c2h_bt_remote_name_req) + coex_sta->cnt_RemoteNameReq++; + + if (coex_sta->bt_info_ext & BIT(1)) + coex_sta->cnt_ReInit++; + + if (coex_sta->bt_info_ext & BIT(2)) { + coex_sta->cnt_setupLink++; + coex_sta->is_setupLink = TRUE; + coex_sta->bt_relink_downcount = 2; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link start in BT info!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_sta->is_setupLink = FALSE; + coex_sta->bt_relink_downcount = 0; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link stop in BT info!!\n"); + BTC_TRACE(trace_buf); + } + + + if (coex_sta->bt_info_ext & BIT(3)) + coex_sta->cnt_IgnWlanAct++; + + if (coex_sta->bt_info_ext & BIT(6)) + coex_sta->cnt_RoleSwitch++; + + if (coex_sta->bt_info_ext & BIT(7)) + coex_sta->is_bt_multi_link = TRUE; + else + coex_sta->is_bt_multi_link = FALSE; + + if (coex_sta->bt_create_connection) { + coex_sta->cnt_Page++; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, + &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || + (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { + + is_scoreboard_scan = TRUE; + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_SCAN, TRUE); + + } else + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_SCAN, FALSE); + + } else { + if (is_scoreboard_scan) { + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_SCAN, FALSE); + is_scoreboard_scan = FALSE; + } + } + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + + if ((!btcoexist->manual_control) && + (!btcoexist->stop_coex_dm)) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* Re-Init */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + if (wifi_connected) + halbtc8822b2ant_update_wifi_channel_info( + btcoexist, BTC_MEDIA_CONNECT); + else + halbtc8822b2ant_update_wifi_channel_info( + btcoexist, + BTC_MEDIA_DISCONNECT); + } + + + /* If Ignore_WLanAct && not SetUp_Link */ + if ((coex_sta->bt_info_ext & BIT(3)) && + (!(coex_sta->bt_info_ext & BIT(2))) && + (!(coex_sta->bt_info_ext & BIT(6)))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, FALSE); + } else { + if (coex_sta->bt_info_ext & BIT(2)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ignore Wlan active because Re-link!!\n"); + BTC_TRACE(trace_buf); + } else if (coex_sta->bt_info_ext & BIT(6)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ignore Wlan active because Role-Switch!!\n"); + BTC_TRACE(trace_buf); + } + } + } + + } + + if ((coex_sta->bt_info_ext & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + BTC_TRACE(trace_buf); + coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( + btcoexist); + + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x4); + } + + halbtc8822b2ant_update_bt_link_info(btcoexist); + + halbtc8822b2ant_run_coexist_mechanism(btcoexist); +} + + +void ex_halbtc8822b2ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_RF_ON == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned ON!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = FALSE; + coex_sta->is_rf_state_off = FALSE; +#if 0 + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ONOFF, TRUE); +#endif + } else if (BTC_RF_OFF == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned OFF!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_WLAN_OFF); + + halbtc8822b2ant_action_coex_all_off(btcoexist); + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE | + BT_8822B_2ANT_SCOREBOARD_ONOFF | + BT_8822B_2ANT_SCOREBOARD_SCAN | + BT_8822B_2ANT_SCOREBOARD_UNDERTEST, + FALSE); + + btcoexist->stop_coex_dm = TRUE; + coex_sta->is_rf_state_off = TRUE; + } +} + +void ex_halbtc8822b2ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_WLAN_OFF); + + ex_halbtc8822b2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE); + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ONOFF, FALSE); +} + +void ex_halbtc8822b2ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + boolean wifi_under_5g = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((BTC_WIFI_PNP_SLEEP == pnp_state) || + (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + + /* Sinda 20150819, workaround for driver skip leave IPS/LPS to + * speed up sleep time. + * Driver do not leave IPS/LPS when driver is going to sleep, + * so BTCoexistence think wifi is still under IPS/LPS. + * BT should clear UnderIPS/UnderLPS state to avoid mismatch + * state after wakeup. + */ + coex_sta->under_ips = FALSE; + coex_sta->under_lps = FALSE; + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE); + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ONOFF, FALSE); + + + if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { + + if (wifi_under_5g) + halbtc8822b2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_5G_RUNTIME); + else + halbtc8822b2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME); + } else { + + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_WLAN_OFF); + } + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ONOFF, TRUE); + } +} + +void ex_halbtc8822b2ant_periodical(IN struct btc_coexist *btcoexist) +{ + boolean wifi_busy = FALSE; + u16 bt_scoreboard_val = 0; + boolean bt_relink_finish = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ************* Periodical *************\n"); + BTC_TRACE(trace_buf); + +#if (BT_AUTO_REPORT_ONLY_8822B_2ANT == 0) + halbtc8822b2ant_query_bt_info(btcoexist); +#endif + + halbtc8822b2ant_monitor_bt_ctr(btcoexist); + halbtc8822b2ant_monitor_wifi_ctr(btcoexist); + halbtc8822b2ant_monitor_bt_enable_disable(btcoexist); + +#if 1 + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + halbtc8822b2ant_read_score_board(btcoexist, &bt_scoreboard_val); + + if (wifi_busy) { + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_UNDERTEST, TRUE); + /*for bt lps32 clock offset*/ + if (bt_scoreboard_val & BIT(6)) + halbtc8822b2ant_query_bt_info(btcoexist); + } else { + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_UNDERTEST, FALSE); +#if 0 + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_WLBUSY, + FALSE); +#endif + } +#endif + + if (coex_sta->bt_relink_downcount != 0) { + coex_sta->bt_relink_downcount--; + + if (coex_sta->bt_relink_downcount == 0) { + coex_sta->is_setupLink = FALSE; + bt_relink_finish = TRUE; + } + } + + /* for 4-way, DHCP, EAPOL packet */ + if (coex_sta->specific_pkt_period_cnt > 0) { + + coex_sta->specific_pkt_period_cnt--; + + if ((coex_sta->specific_pkt_period_cnt == 0) && + (coex_sta->wifi_is_high_pri_task)) + coex_sta->wifi_is_high_pri_task = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", + (coex_sta->wifi_is_high_pri_task ? "Yes" : + "No")); + BTC_TRACE(trace_buf); + + } + + if (halbtc8822b2ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish) + || (coex_sta->is_set_ps_state_fail)) + halbtc8822b2ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8822b2ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + +} + + +void ex_halbtc8822b2ant_display_ant_detection(IN struct btc_coexist *btcoexist) +{ +} + + +#endif + +#endif /* #if (RTL8822B_SUPPORT == 1) */ diff --git a/hal/btc/halbtc8822b2ant.h b/hal/btc/halbtc8822b2ant.h new file mode 100644 index 0000000..5338473 --- /dev/null +++ b/hal/btc/halbtc8822b2ant.h @@ -0,0 +1,526 @@ + +#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) + +#if (RTL8822B_SUPPORT == 1) + +/* ******************************************* + * The following is for 8822B 2Ant BT Co-exist definition + * ******************************************* */ +#define BT_8822B_2ANT_COEX_DBG 0 +#define BT_AUTO_REPORT_ONLY_8822B_2ANT 1 + + + + +#define BT_INFO_8822B_2ANT_B_FTP BIT(7) +#define BT_INFO_8822B_2ANT_B_A2DP BIT(6) +#define BT_INFO_8822B_2ANT_B_HID BIT(5) +#define BT_INFO_8822B_2ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8822B_2ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8822B_2ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8822B_2ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8822B_2ANT_B_CONNECTION BIT(0) + +#define BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT 2 + + +/* unit: % WiFi RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation. + * (default = 42) + */ +#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 10 +/* unit: % BT RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation. + * (default = 46) + */ +#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 10 +/* unit: % WiFi RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation. + * (default = 42) + */ +#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 10 +/* unit: % BT RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation. + * (default = 46) + */ +#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2 10 +#define BT_8822B_2ANT_DEFAULT_ISOLATION 15 /* unit: dB */ +#define BT_8822B_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */ +#define BT_8822B_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */ +#define BT_8822B_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */ +#define BT_8822B_2ANT_WIFI_SIR_THRES2 -30 /* unit: dB */ +#define BT_8822B_2ANT_BT_SIR_THRES1 -15 /* unit: dB */ +#define BT_8822B_2ANT_BT_SIR_THRES2 -30 /* unit: dB */ + + +/* for Antenna detection */ +#define BT_8822B_2ANT_ANTDET_PSDTHRES_BACKGROUND 50 +#define BT_8822B_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 +#define BT_8822B_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 52 +#define BT_8822B_2ANT_ANTDET_PSDTHRES_1ANT 40 +#define BT_8822B_2ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ +#define BT_8822B_2ANT_ANTDET_SWEEPPOINT_DELAY 60000 +#define BT_8822B_2ANT_ANTDET_ENABLE 0 +#define BT_8822B_2ANT_ANTDET_BTTXTIME 100 +#define BT_8822B_2ANT_ANTDET_BTTXCHANNEL 39 +#define BT_8822B_2ANT_ANTDET_PSD_SWWEEPCOUNT 50 + + +#define BT_8822B_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 + +enum bt_8822b_2ant_signal_state { + BT_8822B_2ANT_SIG_STA_SET_TO_LOW = 0x0, + BT_8822B_2ANT_SIG_STA_SET_BY_HW = 0x0, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH = 0x1, + BT_8822B_2ANT_SIG_STA_MAX +}; + +enum bt_8822b_2ant_path_ctrl_owner { + BT_8822B_2ANT_PCO_BTSIDE = 0x0, + BT_8822B_2ANT_PCO_WLSIDE = 0x1, + BT_8822B_2ANT_PCO_MAX +}; + +enum bt_8822b_2ant_gnt_ctrl_type { + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW = 0x1, + BT_8822B_2ANT_GNT_TYPE_MAX +}; + +enum bt_8822b_2ant_gnt_ctrl_block { + BT_8822B_2ANT_GNT_BLOCK_RFC_BB = 0x0, + BT_8822B_2ANT_GNT_BLOCK_RFC = 0x1, + BT_8822B_2ANT_GNT_BLOCK_BB = 0x2, + BT_8822B_2ANT_GNT_BLOCK_MAX +}; + +enum bt_8822b_2ant_lte_coex_table_type { + BT_8822B_2ANT_CTT_WL_VS_LTE = 0x0, + BT_8822B_2ANT_CTT_BT_VS_LTE = 0x1, + BT_8822B_2ANT_CTT_MAX +}; + +enum bt_8822b_2ant_lte_break_table_type { + BT_8822B_2ANT_LBTT_WL_BREAK_LTE = 0x0, + BT_8822B_2ANT_LBTT_BT_BREAK_LTE = 0x1, + BT_8822B_2ANT_LBTT_LTE_BREAK_WL = 0x2, + BT_8822B_2ANT_LBTT_LTE_BREAK_BT = 0x3, + BT_8822B_2ANT_LBTT_MAX +}; + +enum bt_info_src_8822b_2ant { + BT_INFO_SRC_8822B_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8822B_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8822B_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8822B_2ANT_MAX +}; + +enum bt_8822b_2ant_bt_status { + BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8822B_2ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8822B_2ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8822B_2ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8822B_2ANT_BT_STATUS_MAX +}; + +enum bt_8822b_2ant_coex_algo { + BT_8822B_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8822B_2ANT_COEX_ALGO_SCO = 0x1, + BT_8822B_2ANT_COEX_ALGO_HID = 0x2, + BT_8822B_2ANT_COEX_ALGO_A2DP = 0x3, + BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8822B_2ANT_COEX_ALGO_PANEDR = 0x5, + BT_8822B_2ANT_COEX_ALGO_PANHS = 0x6, + BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8822B_2ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8822B_2ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY = 0xb, + BT_8822B_2ANT_COEX_ALGO_A2DPSINK = 0xc, + BT_8822B_2ANT_COEX_ALGO_MAX +}; + +enum bt_8822b_2ant_ext_ant_switch_type { + BT_8822B_2ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0, + BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1, + BT_8822B_2ANT_EXT_ANT_SWITCH_NONE = 0x2, + BT_8822B_2ANT_EXT_ANT_SWITCH_MAX +}; + +enum bt_8822b_2ant_ext_ant_switch_ctrl_type { + BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, + BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, + BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, + BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, + BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, + BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_MAX +}; + +enum bt_8822b_2ant_ext_ant_switch_pos_type { + BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT = 0x0, + BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG = 0x1, + BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA = 0x2, + BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE = 0x3, + BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_MAX +}; + +enum bt_8822b_2ant_ext_band_switch_pos_type { + BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLG = 0x0, + BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLA = 0x1, + BT_8822B_2ANT_EXT_BAND_SWITCH_TO_MAX +}; + +enum bt_8822b_2ant_int_block { + BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0, + BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1, + BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2, + BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_MAX +}; + +enum bt_8822b_2ant_phase { + BT_8822B_2ANT_PHASE_COEX_INIT = 0x0, + BT_8822B_2ANT_PHASE_WLANONLY_INIT = 0x1, + BT_8822B_2ANT_PHASE_WLAN_OFF = 0x2, + BT_8822B_2ANT_PHASE_2G_RUNTIME = 0x3, + BT_8822B_2ANT_PHASE_5G_RUNTIME = 0x4, + BT_8822B_2ANT_PHASE_BTMPMODE = 0x5, + BT_8822B_2ANT_PHASE_ANTENNA_DET = 0x6, + BT_8822B_2ANT_PHASE_COEX_POWERON = 0x7, + BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT = 0x8, + BT_8822B_2ANT_PHASE_MAX +}; + +/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/ + +enum bt_8822b_2ant_Scoreboard { + BT_8822B_2ANT_SCOREBOARD_ACTIVE = BIT(0), + BT_8822B_2ANT_SCOREBOARD_ONOFF = BIT(1), + BT_8822B_2ANT_SCOREBOARD_SCAN = BIT(2), + BT_8822B_2ANT_SCOREBOARD_UNDERTEST = BIT(3), + BT_8822B_2ANT_SCOREBOARD_WLBUSY = BIT(6) +}; + + + + + +struct coex_dm_8822b_2ant { + /* hw setting */ + u32 pre_ant_pos_type; + u32 cur_ant_pos_type; + /* fw mechanism */ + u8 pre_bt_dec_pwr_lvl; + u8 cur_bt_dec_pwr_lvl; + u8 pre_fw_dac_swing_lvl; + u8 cur_fw_dac_swing_lvl; + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean reset_tdma_adjust; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + + /* sw mechanism */ + boolean pre_rf_rx_lpf_shrink; + boolean cur_rf_rx_lpf_shrink; + u32 bt_rf_0x1e_backup; + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + boolean pre_dac_swing_on; + u32 pre_dac_swing_lvl; + boolean cur_dac_swing_on; + u32 cur_dac_swing_lvl; + boolean pre_adc_back_off; + boolean cur_adc_back_off; + boolean pre_agc_table_en; + boolean cur_agc_table_en; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + boolean need_recover0x948; + u32 backup0x948; + + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + boolean is_switch_to_1dot5_ant; + u8 switch_thres_offset; + u32 arp_cnt; + + u32 pre_ext_ant_switch_status; + u32 cur_ext_ant_switch_status; + + u8 pre_ext_band_switch_status; + u8 cur_ext_band_switch_status; + + u8 pre_int_block_status; + u8 cur_int_block_status; +}; + + +struct coex_sta_8822b_2ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + + boolean under_lps; + boolean under_ips; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + boolean is_hiPri_rx_overhead; + u8 bt_rssi; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + u8 bt_info_c2h[BT_INFO_SRC_8822B_2ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8822B_2ANT_MAX]; + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; + + u8 bt_info_ext; + u8 bt_info_ext2; + u32 pop_event_cnt; + u8 scan_ap_num; + u8 bt_retry_cnt; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + + u32 acc_crc_ratio; + u32 now_crc_ratio; + + boolean cck_lock; + boolean pre_ccklock; + boolean cck_ever_lock; + + u8 coex_table_type; + boolean force_lps_ctrl; + + u8 dis_ver_info_cnt; + + u8 a2dp_bit_pool; + u8 cut_version; + + boolean concurrent_rx_mode_on; + + u16 score_board; + u8 isolation_btween_wb; /* 0~ 50 */ + u8 wifi_coex_thres; + u8 bt_coex_thres; + u8 wifi_coex_thres2; + u8 bt_coex_thres2; + + u8 num_of_profile; + boolean acl_busy; + boolean bt_create_connection; + boolean wifi_is_high_pri_task; + u32 specific_pkt_period_cnt; + u32 bt_coex_supported_feature; + u32 bt_coex_supported_version; + + u8 bt_ble_scan_type; + u32 bt_ble_scan_para[3]; + + boolean run_time_state; + boolean freeze_coexrun_by_btinfo; + + boolean is_A2DP_3M; + boolean voice_over_HOGP; + u8 bt_info; + boolean is_autoslot; + u8 forbidden_slot; + u8 hid_busy_num; + u8 hid_pair_cnt; + + u32 cnt_RemoteNameReq; + u32 cnt_setupLink; + u32 cnt_ReInit; + u32 cnt_IgnWlanAct; + u32 cnt_Page; + u32 cnt_RoleSwitch; + + u16 bt_reg_vendor_ac; + u16 bt_reg_vendor_ae; + + boolean is_setupLink; + u8 wl_noisy_level; + u32 gnt_error_cnt; + + u8 bt_afh_map[10]; + u8 bt_relink_downcount; + boolean is_tdma_btautoslot; + boolean is_tdma_btautoslot_hang; + + boolean is_eSCO_mode; + u8 switch_band_notify_to; + boolean is_rf_state_off; + + boolean is_hid_low_pri_tx_overhead; + boolean is_bt_multi_link; + boolean is_bt_a2dp_sink; + + boolean is_set_ps_state_fail; + u8 cnt_set_ps_state_fail; +}; + + +#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_DPDT 0 +#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_SPDT 1 + + +struct rfe_type_8822b_2ant { + + u8 rfe_module_type; + boolean ext_ant_switch_exist; + u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */ + /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ + u8 ext_ant_switch_ctrl_polarity; + + boolean ext_band_switch_exist; + u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */ + u8 ext_band_switch_ctrl_polarity; + + /* If true: WLG at BTG, If false: WLG at WLAG */ + boolean wlg_Locate_at_btg; + + boolean ext_ant_switch_diversity; /* If diversity on */ +}; + +#define BT_8822B_2ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ +#define BT_8822B_2ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ +#define BT_8822B_2ANT_ANTDET_BUF_LEN 16 + +struct psdscan_sta_8822b_2ant { + + u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ + u32 ant_det_bt_tx_time; + u32 ant_det_pre_psdscan_peak_val; + boolean ant_det_is_ant_det_available; + u32 ant_det_psd_scan_peak_val; + boolean ant_det_is_btreply_available; + u32 ant_det_psd_scan_peak_freq; + + u8 ant_det_result; + u8 ant_det_peak_val[BT_8822B_2ANT_ANTDET_BUF_LEN]; + u8 ant_det_peak_freq[BT_8822B_2ANT_ANTDET_BUF_LEN]; + u32 ant_det_try_count; + u32 ant_det_fail_count; + u32 ant_det_inteval_count; + u32 ant_det_thres_offset; + + u32 real_cent_freq; + s32 real_offset; + u32 real_span; + + u32 psd_band_width; /* unit: Hz */ + u32 psd_point; /* 128/256/512/1024 */ + u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_start_point; + u32 psd_stop_point; + u32 psd_max_value_point; + u32 psd_max_value; + u32 psd_max_value2; + /* filter loop_max_value that below BT_8822B_1ANT_ANTDET_PSDTHRES_1ANT, + * and average the rest + */ + u32 psd_avg_value; + /*max value in each loop */ + u32 psd_loop_max_value[BT_8822B_2ANT_ANTDET_PSD_SWWEEPCOUNT]; + u32 psd_start_base; + u32 psd_avg_num; /* 1/8/16/32 */ + u32 psd_gen_count; + boolean is_AntDet_running; + boolean is_psd_show_max_only; +}; + + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8822b2ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8822b2ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b2ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b2ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b2ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8822b2ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8822b2ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b2ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8822b2ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b2ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); +void ex_halbtc8822b2ant_display_ant_detection(IN struct btc_coexist *btcoexist); + + +#else +#define ex_halbtc8822b2ant_power_on_setting(btcoexist) +#define ex_halbtc8822b2ant_pre_load_firmware(btcoexist) +#define ex_halbtc8822b2ant_init_hw_config(btcoexist, wifi_only) +#define ex_halbtc8822b2ant_init_coex_dm(btcoexist) +#define ex_halbtc8822b2ant_ips_notify(btcoexist, type) +#define ex_halbtc8822b2ant_lps_notify(btcoexist, type) +#define ex_halbtc8822b2ant_scan_notify(btcoexist, type) +#define ex_halbtc8822b2ant_switchband_notify(btcoexist, type) +#define ex_halbtc8822b2ant_connect_notify(btcoexist, type) +#define ex_halbtc8822b2ant_media_status_notify(btcoexist, type) +#define ex_halbtc8822b2ant_specific_packet_notify(btcoexist, type) +#define ex_halbtc8822b2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8822b2ant_rf_status_notify(btcoexist, type) +#define ex_halbtc8822b2ant_halt_notify(btcoexist) +#define ex_halbtc8822b2ant_pnp_notify(btcoexist, pnp_state) +#define ex_halbtc8822b2ant_periodical(btcoexist) +#define ex_halbtc8822b2ant_display_coex_info(btcoexist) +#define ex_halbtc8822b2ant_display_ant_detection(btcoexist) +#define ex_halbtc8822b2ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) +#endif + +#endif diff --git a/hal/btc/halbtc8822bwifionly.c b/hal/btc/halbtc8822bwifionly.c new file mode 100644 index 0000000..8de6409 --- /dev/null +++ b/hal/btc/halbtc8822bwifionly.c @@ -0,0 +1,68 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "mp_precomp.h" + + +VOID +ex_hal8822b_wifi_only_hw_config( + IN struct wifi_only_cfg *pwifionlycfg + ) +{ + /*BB control*/ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2); + /*SW control*/ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0xff, 0x77); + /*antenna mux switch */ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x974, 0x300, 0x3); + + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1990, 0x300, 0x0); + + halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x80000, 0x0); + /*switch to WL side controller and gnt_wl gnt_bt debug signal */ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e); + /*gnt_wl=1 , gnt_bt=0*/ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700); + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); +} + +VOID +ex_hal8822b_wifi_only_scannotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ) +{ + hal8822b_wifi_only_switch_antenna(pwifionlycfg, is_5g); +} + +VOID +ex_hal8822b_wifi_only_switchbandnotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ) +{ + hal8822b_wifi_only_switch_antenna(pwifionlycfg, is_5g); +} + +VOID +hal8822b_wifi_only_switch_antenna(IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ) +{ + + if (is_5g) + halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x300, 0x1); + else + halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x300, 0x2); +} diff --git a/hal/btc/halbtc8822bwifionly.h b/hal/btc/halbtc8822bwifionly.h new file mode 100644 index 0000000..4ca6f48 --- /dev/null +++ b/hal/btc/halbtc8822bwifionly.h @@ -0,0 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __INC_HAL8822BWIFIONLYHWCFG_H +#define __INC_HAL8822BWIFIONLYHWCFG_H + +VOID +ex_hal8822b_wifi_only_hw_config( + IN struct wifi_only_cfg *pwifionlycfg + ); +VOID +ex_hal8822b_wifi_only_scannotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ); +VOID +ex_hal8822b_wifi_only_switchbandnotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ); +VOID +hal8822b_wifi_only_switch_antenna(IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ); +#endif diff --git a/hal/btc/halbtcoutsrc.h b/hal/btc/halbtcoutsrc.h new file mode 100644 index 0000000..2005e1e --- /dev/null +++ b/hal/btc/halbtcoutsrc.h @@ -0,0 +1,1030 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __HALBTC_OUT_SRC_H__ +#define __HALBTC_OUT_SRC_H__ + + +#define BTC_COEX_OFFLOAD 0 +#define BTC_TMP_BUF_SHORT 20 + +extern u1Byte gl_btc_trace_buf[]; +#define BTC_SPRINTF rsprintf +#define BTC_TRACE(_MSG_)\ +do {\ + if (GLBtcDbgType[COMP_COEX] & BIT(DBG_LOUD)) {\ + RTW_INFO("%s", _MSG_);\ + } \ +} while (0) +#define BT_PrintData(adapter, _MSG_, len, data) RTW_DBG_DUMP((_MSG_), data, len) + + +#define NORMAL_EXEC FALSE +#define FORCE_EXEC TRUE + +#define BTC_RF_OFF 0x0 +#define BTC_RF_ON 0x1 + +#define BTC_RF_A 0x0 +#define BTC_RF_B 0x1 +#define BTC_RF_C 0x2 +#define BTC_RF_D 0x3 + +#define BTC_SMSP SINGLEMAC_SINGLEPHY +#define BTC_DMDP DUALMAC_DUALPHY +#define BTC_DMSP DUALMAC_SINGLEPHY +#define BTC_MP_UNKNOWN 0xff + +#define BT_COEX_ANT_TYPE_PG 0 +#define BT_COEX_ANT_TYPE_ANTDIV 1 +#define BT_COEX_ANT_TYPE_DETECTED 2 + +#define BTC_MIMO_PS_STATIC 0 /* 1ss */ +#define BTC_MIMO_PS_DYNAMIC 1 /* 2ss */ + +#define BTC_RATE_DISABLE 0 +#define BTC_RATE_ENABLE 1 + +/* single Antenna definition */ +#define BTC_ANT_PATH_WIFI 0 +#define BTC_ANT_PATH_BT 1 +#define BTC_ANT_PATH_PTA 2 +#define BTC_ANT_PATH_WIFI5G 3 +#define BTC_ANT_PATH_AUTO 4 +/* dual Antenna definition */ +#define BTC_ANT_WIFI_AT_MAIN 0 +#define BTC_ANT_WIFI_AT_AUX 1 +#define BTC_ANT_WIFI_AT_DIVERSITY 2 +/* coupler Antenna definition */ +#define BTC_ANT_WIFI_AT_CPL_MAIN 0 +#define BTC_ANT_WIFI_AT_CPL_AUX 1 + +typedef enum _BTC_POWERSAVE_TYPE { + BTC_PS_WIFI_NATIVE = 0, /* wifi original power save behavior */ + BTC_PS_LPS_ON = 1, + BTC_PS_LPS_OFF = 2, + BTC_PS_MAX +} BTC_POWERSAVE_TYPE, *PBTC_POWERSAVE_TYPE; + +typedef enum _BTC_BT_REG_TYPE { + BTC_BT_REG_RF = 0, + BTC_BT_REG_MODEM = 1, + BTC_BT_REG_BLUEWIZE = 2, + BTC_BT_REG_VENDOR = 3, + BTC_BT_REG_LE = 4, + BTC_BT_REG_MAX +} BTC_BT_REG_TYPE, *PBTC_BT_REG_TYPE; + +typedef enum _BTC_CHIP_INTERFACE { + BTC_INTF_UNKNOWN = 0, + BTC_INTF_PCI = 1, + BTC_INTF_USB = 2, + BTC_INTF_SDIO = 3, + BTC_INTF_MAX +} BTC_CHIP_INTERFACE, *PBTC_CHIP_INTERFACE; + +typedef enum _BTC_CHIP_TYPE { + BTC_CHIP_UNDEF = 0, + BTC_CHIP_CSR_BC4 = 1, + BTC_CHIP_CSR_BC8 = 2, + BTC_CHIP_RTL8723A = 3, + BTC_CHIP_RTL8821 = 4, + BTC_CHIP_RTL8723B = 5, + BTC_CHIP_MAX +} BTC_CHIP_TYPE, *PBTC_CHIP_TYPE; + +/* following is for wifi link status */ +#define WIFI_STA_CONNECTED BIT0 +#define WIFI_AP_CONNECTED BIT1 +#define WIFI_HS_CONNECTED BIT2 +#define WIFI_P2P_GO_CONNECTED BIT3 +#define WIFI_P2P_GC_CONNECTED BIT4 + +/* following is for command line utility */ +#define CL_SPRINTF rsprintf +#define CL_PRINTF DCMD_Printf + +struct btc_board_info { + /* The following is some board information */ + u8 bt_chip_type; + u8 pg_ant_num; /* pg ant number */ + u8 btdm_ant_num; /* ant number for btdm */ + u8 btdm_ant_num_by_ant_det; /* ant number for btdm after antenna detection */ + u8 btdm_ant_pos; /* Bryant Add to indicate Antenna Position for (pg_ant_num = 2) && (btdm_ant_num =1) (DPDT+1Ant case) */ + u8 single_ant_path; /* current used for 8723b only, 1=>s0, 0=>s1 */ + boolean tfbga_package; /* for Antenna detect threshold */ + boolean btdm_ant_det_finish; + boolean btdm_ant_det_already_init_phydm; + u8 ant_type; + u8 rfe_type; + u8 ant_div_cfg; + boolean btdm_ant_det_complete_fail; + u8 ant_det_result; + boolean ant_det_result_five_complete; + u32 antdetval; +}; + +typedef enum _BTC_DBG_OPCODE { + BTC_DBG_SET_COEX_NORMAL = 0x0, + BTC_DBG_SET_COEX_WIFI_ONLY = 0x1, + BTC_DBG_SET_COEX_BT_ONLY = 0x2, + BTC_DBG_SET_COEX_DEC_BT_PWR = 0x3, + BTC_DBG_SET_COEX_BT_AFH_MAP = 0x4, + BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT = 0x5, + BTC_DBG_SET_COEX_MANUAL_CTRL = 0x6, + BTC_DBG_MAX +} BTC_DBG_OPCODE, *PBTC_DBG_OPCODE; + +typedef enum _BTC_RSSI_STATE { + BTC_RSSI_STATE_HIGH = 0x0, + BTC_RSSI_STATE_MEDIUM = 0x1, + BTC_RSSI_STATE_LOW = 0x2, + BTC_RSSI_STATE_STAY_HIGH = 0x3, + BTC_RSSI_STATE_STAY_MEDIUM = 0x4, + BTC_RSSI_STATE_STAY_LOW = 0x5, + BTC_RSSI_MAX +} BTC_RSSI_STATE, *PBTC_RSSI_STATE; +#define BTC_RSSI_HIGH(_rssi_) ((_rssi_ == BTC_RSSI_STATE_HIGH || _rssi_ == BTC_RSSI_STATE_STAY_HIGH) ? TRUE:FALSE) +#define BTC_RSSI_MEDIUM(_rssi_) ((_rssi_ == BTC_RSSI_STATE_MEDIUM || _rssi_ == BTC_RSSI_STATE_STAY_MEDIUM) ? TRUE:FALSE) +#define BTC_RSSI_LOW(_rssi_) ((_rssi_ == BTC_RSSI_STATE_LOW || _rssi_ == BTC_RSSI_STATE_STAY_LOW) ? TRUE:FALSE) + +typedef enum _BTC_WIFI_ROLE { + BTC_ROLE_STATION = 0x0, + BTC_ROLE_AP = 0x1, + BTC_ROLE_IBSS = 0x2, + BTC_ROLE_HS_MODE = 0x3, + BTC_ROLE_MAX +} BTC_WIFI_ROLE, *PBTC_WIFI_ROLE; + +typedef enum _BTC_WIRELESS_FREQ { + BTC_FREQ_2_4G = 0x0, + BTC_FREQ_5G = 0x1, + BTC_FREQ_MAX +} BTC_WIRELESS_FREQ, *PBTC_WIRELESS_FREQ; + +typedef enum _BTC_WIFI_BW_MODE { + BTC_WIFI_BW_LEGACY = 0x0, + BTC_WIFI_BW_HT20 = 0x1, + BTC_WIFI_BW_HT40 = 0x2, + BTC_WIFI_BW_HT80 = 0x3, + BTC_WIFI_BW_HT160 = 0x4, + BTC_WIFI_BW_MAX +} BTC_WIFI_BW_MODE, *PBTC_WIFI_BW_MODE; + +typedef enum _BTC_WIFI_TRAFFIC_DIR { + BTC_WIFI_TRAFFIC_TX = 0x0, + BTC_WIFI_TRAFFIC_RX = 0x1, + BTC_WIFI_TRAFFIC_MAX +} BTC_WIFI_TRAFFIC_DIR, *PBTC_WIFI_TRAFFIC_DIR; + +typedef enum _BTC_WIFI_PNP { + BTC_WIFI_PNP_WAKE_UP = 0x0, + BTC_WIFI_PNP_SLEEP = 0x1, + BTC_WIFI_PNP_SLEEP_KEEP_ANT = 0x2, + BTC_WIFI_PNP_MAX +} BTC_WIFI_PNP, *PBTC_WIFI_PNP; + +typedef enum _BTC_IOT_PEER { + BTC_IOT_PEER_UNKNOWN = 0, + BTC_IOT_PEER_REALTEK = 1, + BTC_IOT_PEER_REALTEK_92SE = 2, + BTC_IOT_PEER_BROADCOM = 3, + BTC_IOT_PEER_RALINK = 4, + BTC_IOT_PEER_ATHEROS = 5, + BTC_IOT_PEER_CISCO = 6, + BTC_IOT_PEER_MERU = 7, + BTC_IOT_PEER_MARVELL = 8, + BTC_IOT_PEER_REALTEK_SOFTAP = 9, /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */ + BTC_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */ + BTC_IOT_PEER_AIRGO = 11, + BTC_IOT_PEER_INTEL = 12, + BTC_IOT_PEER_RTK_APCLIENT = 13, + BTC_IOT_PEER_REALTEK_81XX = 14, + BTC_IOT_PEER_REALTEK_WOW = 15, + BTC_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16, + BTC_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17, + BTC_IOT_PEER_MAX, +} BTC_IOT_PEER, *PBTC_IOT_PEER; + +/* for 8723b-d cut large current issue */ +typedef enum _BTC_WIFI_COEX_STATE { + BTC_WIFI_STAT_INIT, + BTC_WIFI_STAT_IQK, + BTC_WIFI_STAT_NORMAL_OFF, + BTC_WIFI_STAT_MP_OFF, + BTC_WIFI_STAT_NORMAL, + BTC_WIFI_STAT_ANT_DIV, + BTC_WIFI_STAT_MAX +} BTC_WIFI_COEX_STATE, *PBTC_WIFI_COEX_STATE; + +typedef enum _BTC_ANT_TYPE { + BTC_ANT_TYPE_0, + BTC_ANT_TYPE_1, + BTC_ANT_TYPE_2, + BTC_ANT_TYPE_3, + BTC_ANT_TYPE_4, + BTC_ANT_TYPE_MAX +} BTC_ANT_TYPE, *PBTC_ANT_TYPE; + +typedef enum _BTC_VENDOR { + BTC_VENDOR_LENOVO, + BTC_VENDOR_ASUS, + BTC_VENDOR_OTHER +} BTC_VENDOR, *PBTC_VENDOR; + + +/* defined for BFP_BTC_GET */ +typedef enum _BTC_GET_TYPE { + /* type BOOLEAN */ + BTC_GET_BL_HS_OPERATION, + BTC_GET_BL_HS_CONNECTING, + BTC_GET_BL_WIFI_FW_READY, + BTC_GET_BL_WIFI_CONNECTED, + BTC_GET_BL_WIFI_BUSY, + BTC_GET_BL_WIFI_SCAN, + BTC_GET_BL_WIFI_LINK, + BTC_GET_BL_WIFI_ROAM, + BTC_GET_BL_WIFI_4_WAY_PROGRESS, + BTC_GET_BL_WIFI_UNDER_5G, + BTC_GET_BL_WIFI_AP_MODE_ENABLE, + BTC_GET_BL_WIFI_ENABLE_ENCRYPTION, + BTC_GET_BL_WIFI_UNDER_B_MODE, + BTC_GET_BL_EXT_SWITCH, + BTC_GET_BL_WIFI_IS_IN_MP_MODE, + BTC_GET_BL_IS_ASUS_8723B, + BTC_GET_BL_RF4CE_CONNECTED, + + /* type s4Byte */ + BTC_GET_S4_WIFI_RSSI, + BTC_GET_S4_HS_RSSI, + + /* type u4Byte */ + BTC_GET_U4_WIFI_BW, + BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, + BTC_GET_U4_WIFI_FW_VER, + BTC_GET_U4_WIFI_LINK_STATUS, + BTC_GET_U4_BT_PATCH_VER, + BTC_GET_U4_VENDOR, + BTC_GET_U4_SUPPORTED_VERSION, + BTC_GET_U4_SUPPORTED_FEATURE, + BTC_GET_U4_WIFI_IQK_TOTAL, + BTC_GET_U4_WIFI_IQK_OK, + BTC_GET_U4_WIFI_IQK_FAIL, + + /* type u1Byte */ + BTC_GET_U1_WIFI_DOT11_CHNL, + BTC_GET_U1_WIFI_CENTRAL_CHNL, + BTC_GET_U1_WIFI_HS_CHNL, + BTC_GET_U1_WIFI_P2P_CHNL, + BTC_GET_U1_MAC_PHY_MODE, + BTC_GET_U1_AP_NUM, + BTC_GET_U1_ANT_TYPE, + BTC_GET_U1_IOT_PEER, + + /*===== for 1Ant ======*/ + BTC_GET_U1_LPS_MODE, + + BTC_GET_MAX +} BTC_GET_TYPE, *PBTC_GET_TYPE; + +/* defined for BFP_BTC_SET */ +typedef enum _BTC_SET_TYPE { + /* type BOOLEAN */ + BTC_SET_BL_BT_DISABLE, + BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE, + BTC_SET_BL_BT_TRAFFIC_BUSY, + BTC_SET_BL_BT_LIMITED_DIG, + BTC_SET_BL_FORCE_TO_ROAM, + BTC_SET_BL_TO_REJ_AP_AGG_PKT, + BTC_SET_BL_BT_CTRL_AGG_SIZE, + BTC_SET_BL_INC_SCAN_DEV_NUM, + BTC_SET_BL_BT_TX_RX_MASK, + BTC_SET_BL_MIRACAST_PLUS_BT, + + /* type u1Byte */ + BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, + BTC_SET_U1_AGG_BUF_SIZE, + + /* type trigger some action */ + BTC_SET_ACT_GET_BT_RSSI, + BTC_SET_ACT_AGGREGATE_CTRL, + BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, + /*===== for 1Ant ======*/ + /* type BOOLEAN */ + + /* type u1Byte */ + BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, + BTC_SET_U1_LPS_VAL, + BTC_SET_U1_RPWM_VAL, + /* type trigger some action */ + BTC_SET_ACT_LEAVE_LPS, + BTC_SET_ACT_ENTER_LPS, + BTC_SET_ACT_NORMAL_LPS, + BTC_SET_ACT_PRE_NORMAL_LPS, + BTC_SET_ACT_POST_NORMAL_LPS, + BTC_SET_ACT_DISABLE_LOW_POWER, + BTC_SET_ACT_UPDATE_RAMASK, + BTC_SET_ACT_SEND_MIMO_PS, + /* BT Coex related */ + BTC_SET_ACT_CTRL_BT_INFO, + BTC_SET_ACT_CTRL_BT_COEX, + BTC_SET_ACT_CTRL_8723B_ANT, + /*=================*/ + BTC_SET_MAX +} BTC_SET_TYPE, *PBTC_SET_TYPE; + +typedef enum _BTC_DBG_DISP_TYPE { + BTC_DBG_DISP_COEX_STATISTICS = 0x0, + BTC_DBG_DISP_BT_LINK_INFO = 0x1, + BTC_DBG_DISP_WIFI_STATUS = 0x2, + BTC_DBG_DISP_MAX +} BTC_DBG_DISP_TYPE, *PBTC_DBG_DISP_TYPE; + +typedef enum _BTC_NOTIFY_TYPE_IPS { + BTC_IPS_LEAVE = 0x0, + BTC_IPS_ENTER = 0x1, + BTC_IPS_MAX +} BTC_NOTIFY_TYPE_IPS, *PBTC_NOTIFY_TYPE_IPS; +typedef enum _BTC_NOTIFY_TYPE_LPS { + BTC_LPS_DISABLE = 0x0, + BTC_LPS_ENABLE = 0x1, + BTC_LPS_MAX +} BTC_NOTIFY_TYPE_LPS, *PBTC_NOTIFY_TYPE_LPS; +typedef enum _BTC_NOTIFY_TYPE_SCAN { + BTC_SCAN_FINISH = 0x0, + BTC_SCAN_START = 0x1, + BTC_SCAN_START_2G = 0x2, + BTC_SCAN_MAX +} BTC_NOTIFY_TYPE_SCAN, *PBTC_NOTIFY_TYPE_SCAN; +typedef enum _BTC_NOTIFY_TYPE_SWITCHBAND { + BTC_NOT_SWITCH = 0x0, + BTC_SWITCH_TO_24G = 0x1, + BTC_SWITCH_TO_5G = 0x2, + BTC_SWITCH_TO_24G_NOFORSCAN = 0x3, + BTC_SWITCH_MAX +} BTC_NOTIFY_TYPE_SWITCHBAND, *PBTC_NOTIFY_TYPE_SWITCHBAND; +typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE { + BTC_ASSOCIATE_FINISH = 0x0, + BTC_ASSOCIATE_START = 0x1, + BTC_ASSOCIATE_5G_FINISH = 0x2, + BTC_ASSOCIATE_5G_START = 0x3, + BTC_ASSOCIATE_MAX +} BTC_NOTIFY_TYPE_ASSOCIATE, *PBTC_NOTIFY_TYPE_ASSOCIATE; +typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS { + BTC_MEDIA_DISCONNECT = 0x0, + BTC_MEDIA_CONNECT = 0x1, + BTC_MEDIA_MAX +} BTC_NOTIFY_TYPE_MEDIA_STATUS, *PBTC_NOTIFY_TYPE_MEDIA_STATUS; +typedef enum _BTC_NOTIFY_TYPE_SPECIFIC_PACKET { + BTC_PACKET_UNKNOWN = 0x0, + BTC_PACKET_DHCP = 0x1, + BTC_PACKET_ARP = 0x2, + BTC_PACKET_EAPOL = 0x3, + BTC_PACKET_MAX +} BTC_NOTIFY_TYPE_SPECIFIC_PACKET, *PBTC_NOTIFY_TYPE_SPECIFIC_PACKET; +typedef enum _BTC_NOTIFY_TYPE_STACK_OPERATION { + BTC_STACK_OP_NONE = 0x0, + BTC_STACK_OP_INQ_PAGE_PAIR_START = 0x1, + BTC_STACK_OP_INQ_PAGE_PAIR_FINISH = 0x2, + BTC_STACK_OP_MAX +} BTC_NOTIFY_TYPE_STACK_OPERATION, *PBTC_NOTIFY_TYPE_STACK_OPERATION; + +/* Bryant Add */ +typedef enum _BTC_ANTENNA_POS { + BTC_ANTENNA_AT_MAIN_PORT = 0x1, + BTC_ANTENNA_AT_AUX_PORT = 0x2, +} BTC_ANTENNA_POS, *PBTC_ANTENNA_POS; + +/* Bryant Add */ +typedef enum _BTC_BT_OFFON { + BTC_BT_OFF = 0x0, + BTC_BT_ON = 0x1, +} BTC_BTOFFON, *PBTC_BT_OFFON; + +/*================================================== +For following block is for coex offload +==================================================*/ +typedef struct _COL_H2C { + u1Byte opcode; + u1Byte opcode_ver:4; + u1Byte req_num:4; + u1Byte buf[1]; +} COL_H2C, *PCOL_H2C; + +#define COL_C2H_ACK_HDR_LEN 3 +typedef struct _COL_C2H_ACK { + u1Byte status; + u1Byte opcode_ver:4; + u1Byte req_num:4; + u1Byte ret_len; + u1Byte buf[1]; +} COL_C2H_ACK, *PCOL_C2H_ACK; + +#define COL_C2H_IND_HDR_LEN 3 +typedef struct _COL_C2H_IND { + u1Byte type; + u1Byte version; + u1Byte length; + u1Byte data[1]; +} COL_C2H_IND, *PCOL_C2H_IND; + +/*============================================ +NOTE: for debug message, the following define should match +the strings in coexH2cResultString. +============================================*/ +typedef enum _COL_H2C_STATUS { + /* c2h status */ + COL_STATUS_C2H_OK = 0x00, /* Wifi received H2C request and check content ok. */ + COL_STATUS_C2H_UNKNOWN = 0x01, /* Not handled routine */ + COL_STATUS_C2H_UNKNOWN_OPCODE = 0x02, /* Invalid OP code, It means that wifi firmware received an undefiend OP code. */ + COL_STATUS_C2H_OPCODE_VER_MISMATCH = 0x03, /* Wifi firmware and wifi driver mismatch, need to update wifi driver or wifi or. */ + COL_STATUS_C2H_PARAMETER_ERROR = 0x04, /* Error paraneter.(ex: parameters = NULL but it should have values) */ + COL_STATUS_C2H_PARAMETER_OUT_OF_RANGE = 0x05, /* Wifi firmware needs to check the parameters from H2C request and return the status.(ex: ch = 500, it's wrong) */ + /* other COL status start from here */ + COL_STATUS_C2H_REQ_NUM_MISMATCH , /* c2h req_num mismatch, means this c2h is not we expected. */ + COL_STATUS_H2C_HALMAC_FAIL , /* HALMAC return fail. */ + COL_STATUS_H2C_TIMTOUT , /* not received the c2h response from fw */ + COL_STATUS_INVALID_C2H_LEN , /* invalid coex offload c2h ack length, must >= 3 */ + COL_STATUS_COEX_DATA_OVERFLOW , /* coex returned length over the c2h ack length. */ + COL_STATUS_MAX +} COL_H2C_STATUS, *PCOL_H2C_STATUS; + +#define COL_MAX_H2C_REQ_NUM 16 + +#define COL_H2C_BUF_LEN 20 +typedef enum _COL_OPCODE { + COL_OP_WIFI_STATUS_NOTIFY = 0x0, + COL_OP_WIFI_PROGRESS_NOTIFY = 0x1, + COL_OP_WIFI_INFO_NOTIFY = 0x2, + COL_OP_WIFI_POWER_STATE_NOTIFY = 0x3, + COL_OP_SET_CONTROL = 0x4, + COL_OP_GET_CONTROL = 0x5, + COL_OP_WIFI_OPCODE_MAX +} COL_OPCODE, *PCOL_OPCODE; + +typedef enum _COL_IND_TYPE { + COL_IND_BT_INFO = 0x0, + COL_IND_PSTDMA = 0x1, + COL_IND_LIMITED_TX_RX = 0x2, + COL_IND_COEX_TABLE = 0x3, + COL_IND_REQ = 0x4, + COL_IND_MAX +} COL_IND_TYPE, *PCOL_IND_TYPE; + +typedef struct _COL_SINGLE_H2C_RECORD { + u1Byte h2c_buf[COL_H2C_BUF_LEN]; /* the latest sent h2c buffer */ + u4Byte h2c_len; + u1Byte c2h_ack_buf[COL_H2C_BUF_LEN]; /* the latest received c2h buffer */ + u4Byte c2h_ack_len; + u4Byte count; /* the total number of the sent h2c command */ + u4Byte status[COL_STATUS_MAX]; /* the c2h status for the sent h2c command */ +} COL_SINGLE_H2C_RECORD, *PCOL_SINGLE_H2C_RECORD; + +typedef struct _COL_SINGLE_C2H_IND_RECORD { + u1Byte ind_buf[COL_H2C_BUF_LEN]; /* the latest received c2h indication buffer */ + u4Byte ind_len; + u4Byte count; /* the total number of the rcvd c2h indication */ + u4Byte status[COL_STATUS_MAX]; /* the c2h indication verified status */ +} COL_SINGLE_C2H_IND_RECORD, *PCOL_SINGLE_C2H_IND_RECORD; + +typedef struct _BTC_OFFLOAD { + /* H2C command related */ + u1Byte h2c_req_num; + u4Byte cnt_h2c_sent; + COL_SINGLE_H2C_RECORD h2c_record[COL_OP_WIFI_OPCODE_MAX]; + + /* C2H Ack related */ + u4Byte cnt_c2h_ack; + u4Byte status[COL_STATUS_MAX]; + struct completion c2h_event[COL_MAX_H2C_REQ_NUM]; /* for req_num = 1~COL_MAX_H2C_REQ_NUM */ + u1Byte c2h_ack_buf[COL_MAX_H2C_REQ_NUM][COL_H2C_BUF_LEN]; + u1Byte c2h_ack_len[COL_MAX_H2C_REQ_NUM]; + + /* C2H Indication related */ + u4Byte cnt_c2h_ind; + COL_SINGLE_C2H_IND_RECORD c2h_ind_record[COL_IND_MAX]; + u4Byte c2h_ind_status[COL_STATUS_MAX]; + u1Byte c2h_ind_buf[COL_H2C_BUF_LEN]; + u1Byte c2h_ind_len; +} BTC_OFFLOAD, *PBTC_OFFLOAD; +extern BTC_OFFLOAD gl_coex_offload; +/*==================================================*/ + +typedef u1Byte +(*BFP_BTC_R1)( + IN PVOID pBtcContext, + IN u4Byte RegAddr + ); +typedef u2Byte +(*BFP_BTC_R2)( + IN PVOID pBtcContext, + IN u4Byte RegAddr + ); +typedef u4Byte +(*BFP_BTC_R4)( + IN PVOID pBtcContext, + IN u4Byte RegAddr + ); +typedef VOID +(*BFP_BTC_W1)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u1Byte Data + ); +typedef VOID +(*BFP_BTC_W1_BIT_MASK)( + IN PVOID pBtcContext, + IN u4Byte regAddr, + IN u1Byte bitMask, + IN u1Byte data1b + ); +typedef VOID +(*BFP_BTC_W2)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u2Byte Data + ); +typedef VOID +(*BFP_BTC_W4)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u4Byte Data + ); +typedef VOID +(*BFP_BTC_LOCAL_REG_W1)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u1Byte Data + ); +typedef VOID +(*BFP_BTC_SET_BB_REG)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); +typedef u4Byte +(*BFP_BTC_GET_BB_REG)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); +typedef VOID +(*BFP_BTC_SET_RF_REG)( + IN PVOID pBtcContext, + IN u1Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); +typedef u4Byte +(*BFP_BTC_GET_RF_REG)( + IN PVOID pBtcContext, + IN u1Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); +typedef VOID +(*BFP_BTC_FILL_H2C)( + IN PVOID pBtcContext, + IN u1Byte elementId, + IN u4Byte cmdLen, + IN pu1Byte pCmdBuffer + ); + +typedef BOOLEAN +(*BFP_BTC_GET)( + IN PVOID pBtCoexist, + IN u1Byte getType, + OUT PVOID pOutBuf + ); + +typedef BOOLEAN +(*BFP_BTC_SET)( + IN PVOID pBtCoexist, + IN u1Byte setType, + OUT PVOID pInBuf + ); +typedef u2Byte +(*BFP_BTC_SET_BT_REG)( + IN PVOID pBtcContext, + IN u1Byte regType, + IN u4Byte offset, + IN u4Byte value + ); +typedef BOOLEAN +(*BFP_BTC_SET_BT_ANT_DETECTION)( + IN PVOID pBtcContext, + IN u1Byte txTime, + IN u1Byte btChnl + ); + +typedef BOOLEAN +(*BFP_BTC_SET_BT_TRX_MASK)( + IN PVOID pBtcContext, + IN u1Byte bt_trx_mask + ); + +typedef u4Byte +(*BFP_BTC_GET_BT_REG)( + IN PVOID pBtcContext, + IN u1Byte regType, + IN u4Byte offset + ); +typedef VOID +(*BFP_BTC_DISP_DBG_MSG)( + IN PVOID pBtCoexist, + IN u1Byte dispType + ); + +typedef COL_H2C_STATUS +(*BFP_BTC_COEX_H2C_PROCESS)( + IN PVOID pBtCoexist, + IN u1Byte opcode, + IN u1Byte opcode_ver, + IN pu1Byte ph2c_par, + IN u1Byte h2c_par_len + ); + +typedef u4Byte +(*BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE)( + IN PVOID pBtcContext + ); + +typedef u4Byte +(*BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION)( + IN PVOID pBtcContext + ); + +typedef u4Byte +(*BFP_BTC_GET_PHYDM_VERSION)( + IN PVOID pBtcContext + ); + +typedef VOID +(*BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD)( + IN PVOID pDM_Odm, + IN u1Byte RA_offset_direction, + IN u1Byte RA_threshold_offset + ); + +typedef u4Byte +(*BTC_PHYDM_CMNINFOQUERY)( + IN PVOID pDM_Odm, + IN u1Byte info_type + ); + +typedef u1Byte +(*BFP_BTC_GET_ANT_DET_VAL_FROM_BT)( + + IN PVOID pBtcContext + ); + +typedef u1Byte +(*BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT)( + IN PVOID pBtcContext + ); + +typedef u4Byte +(*BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT)( + IN PVOID pBtcContext, + IN u1Byte scanType + ); + +typedef BOOLEAN +(*BFP_BTC_GET_BT_AFH_MAP_FROM_BT)( + IN PVOID pBtcContext, + IN u1Byte mapType, + OUT pu1Byte afhMap + ); + +struct btc_bt_info { + boolean bt_disabled; + boolean bt_enable_disable_change; + u8 rssi_adjust_for_agc_table_on; + u8 rssi_adjust_for_1ant_coex_type; + boolean pre_bt_ctrl_agg_buf_size; + boolean bt_ctrl_agg_buf_size; + boolean pre_reject_agg_pkt; + boolean reject_agg_pkt; + boolean increase_scan_dev_num; + boolean bt_tx_rx_mask; + u8 pre_agg_buf_size; + u8 agg_buf_size; + boolean bt_busy; + boolean limited_dig; + u16 bt_hci_ver; + u16 bt_real_fw_ver; + u8 bt_fw_ver; + u32 get_bt_fw_ver_cnt; + u32 bt_get_fw_ver; + boolean miracast_plus_bt; + + boolean bt_disable_low_pwr; + + boolean bt_ctrl_lps; + boolean bt_lps_on; + boolean force_to_roam; /* for 1Ant solution */ + u8 lps_val; + u8 rpwm_val; + u32 ra_mask; +}; + +struct btc_stack_info { + boolean profile_notified; + u16 hci_version; /* stack hci version */ + u8 num_of_link; + boolean bt_link_exist; + boolean sco_exist; + boolean acl_exist; + boolean a2dp_exist; + boolean hid_exist; + u8 num_of_hid; + boolean pan_exist; + boolean unknown_acl_exist; + s8 min_bt_rssi; +}; + +struct btc_bt_link_info { + boolean bt_link_exist; + boolean bt_hi_pri_link_exist; + boolean sco_exist; + boolean sco_only; + boolean a2dp_exist; + boolean a2dp_only; + boolean hid_exist; + boolean hid_only; + boolean pan_exist; + boolean pan_only; + boolean slave_role; + boolean acl_busy; +}; + +#ifdef CONFIG_RF4CE_COEXIST +struct btc_rf4ce_info { + u8 link_state; +}; +#endif + +struct btc_statistics { + u32 cnt_bind; + u32 cnt_power_on; + u32 cnt_pre_load_firmware; + u32 cnt_init_hw_config; + u32 cnt_init_coex_dm; + u32 cnt_ips_notify; + u32 cnt_lps_notify; + u32 cnt_scan_notify; + u32 cnt_connect_notify; + u32 cnt_media_status_notify; + u32 cnt_specific_packet_notify; + u32 cnt_bt_info_notify; + u32 cnt_rf_status_notify; + u32 cnt_periodical; + u32 cnt_coex_dm_switch; + u32 cnt_stack_operation_notify; + u32 cnt_dbg_ctrl; +}; + +struct btc_coexist { + BOOLEAN bBinded; /*make sure only one adapter can bind the data context*/ + PVOID Adapter; /*default adapter*/ + struct btc_board_info board_info; + struct btc_bt_info bt_info; /*some bt info referenced by non-bt module*/ + struct btc_stack_info stack_info; + struct btc_bt_link_info bt_link_info; + +#ifdef CONFIG_RF4CE_COEXIST + struct btc_rf4ce_info rf4ce_info; +#endif + BTC_CHIP_INTERFACE chip_interface; + PVOID odm_priv; + + BOOLEAN initilized; + BOOLEAN stop_coex_dm; + BOOLEAN manual_control; + BOOLEAN bdontenterLPS; + pu1Byte cli_buf; + struct btc_statistics statistics; + u1Byte pwrModeVal[10]; + + /* function pointers */ + /* io related */ + BFP_BTC_R1 btc_read_1byte; + BFP_BTC_W1 btc_write_1byte; + BFP_BTC_W1_BIT_MASK btc_write_1byte_bitmask; + BFP_BTC_R2 btc_read_2byte; + BFP_BTC_W2 btc_write_2byte; + BFP_BTC_R4 btc_read_4byte; + BFP_BTC_W4 btc_write_4byte; + BFP_BTC_LOCAL_REG_W1 btc_write_local_reg_1byte; + /* read/write bb related */ + BFP_BTC_SET_BB_REG btc_set_bb_reg; + BFP_BTC_GET_BB_REG btc_get_bb_reg; + + /* read/write rf related */ + BFP_BTC_SET_RF_REG btc_set_rf_reg; + BFP_BTC_GET_RF_REG btc_get_rf_reg; + + /* fill h2c related */ + BFP_BTC_FILL_H2C btc_fill_h2c; + /* other */ + BFP_BTC_DISP_DBG_MSG btc_disp_dbg_msg; + /* normal get/set related */ + BFP_BTC_GET btc_get; + BFP_BTC_SET btc_set; + + BFP_BTC_GET_BT_REG btc_get_bt_reg; + BFP_BTC_SET_BT_REG btc_set_bt_reg; + + BFP_BTC_SET_BT_ANT_DETECTION btc_set_bt_ant_detection; + + BFP_BTC_COEX_H2C_PROCESS btc_coex_h2c_process; + BFP_BTC_SET_BT_TRX_MASK btc_set_bt_trx_mask; + BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE btc_get_bt_coex_supported_feature; + BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION btc_get_bt_coex_supported_version; + BFP_BTC_GET_PHYDM_VERSION btc_get_bt_phydm_version; + BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD btc_phydm_modify_RA_PCR_threshold; + BTC_PHYDM_CMNINFOQUERY btc_phydm_query_PHY_counter; + BFP_BTC_GET_ANT_DET_VAL_FROM_BT btc_get_ant_det_val_from_bt; + BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT btc_get_ble_scan_type_from_bt; + BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT btc_get_ble_scan_para_from_bt; + BFP_BTC_GET_BT_AFH_MAP_FROM_BT btc_get_bt_afh_map_from_bt; +}; +typedef struct btc_coexist *PBTC_COEXIST; + +extern struct btc_coexist GLBtCoexist; + +BOOLEAN +EXhalbtcoutsrc_InitlizeVariables( + IN PVOID Adapter + ); +VOID +EXhalbtcoutsrc_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtcoutsrc_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_SetAntennaPathNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte action + ); +VOID +EXhalbtcoutsrc_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN RT_MEDIA_STATUS mediaStatus + ); +VOID +EXhalbtcoutsrc_SpecificPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pktType + ); +VOID +EXhalbtcoutsrc_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtcoutsrc_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_StackOperationNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ); +VOID +EXhalbtcoutsrc_CoexDmSwitch( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_DbgControl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte opCode, + IN u1Byte opLen, + IN pu1Byte pData + ); +VOID +EXhalbtcoutsrc_AntennaDetection( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ); +VOID +EXhalbtcoutsrc_StackUpdateProfileInfo( + VOID + ); +VOID +EXhalbtcoutsrc_SetHciVersion( + IN u2Byte hciVersion + ); +VOID +EXhalbtcoutsrc_SetBtPatchVersion( + IN u2Byte btHciVersion, + IN u2Byte btPatchVersion + ); +VOID +EXhalbtcoutsrc_UpdateMinBtRssi( + IN s1Byte btRssi + ); +#if 0 +VOID +EXhalbtcoutsrc_SetBtExist( + IN BOOLEAN bBtExist + ); +#endif +VOID +EXhalbtcoutsrc_SetChipType( + IN u1Byte chipType + ); +VOID +EXhalbtcoutsrc_SetAntNum( + IN u1Byte type, + IN u1Byte antNum + ); +VOID +EXhalbtcoutsrc_SetSingleAntPath( + IN u1Byte singleAntPath + ); +VOID +EXhalbtcoutsrc_DisplayBtCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_DisplayAntDetection( + IN PBTC_COEXIST pBtCoexist + ); + +#define MASKBYTE0 0xff +#define MASKBYTE1 0xff00 +#define MASKBYTE2 0xff0000 +#define MASKBYTE3 0xff000000 +#define MASKHWORD 0xffff0000 +#define MASKLWORD 0x0000ffff +#define MASKDWORD 0xffffffff +#define MASK12BITS 0xfff +#define MASKH4BITS 0xf0000000 +#define MASKOFDM_D 0xffc00000 +#define MASKCCK 0x3f3f3f3f + +#endif diff --git a/hal/btc/mp_precomp.h b/hal/btc/mp_precomp.h new file mode 100644 index 0000000..b7402aa --- /dev/null +++ b/hal/btc/mp_precomp.h @@ -0,0 +1,85 @@ +/****************************************************************************** + * + * Copyright(c) 2013 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __MP_PRECOMP_H__ +#define __MP_PRECOMP_H__ + +#include +#include + +#define BT_TMP_BUF_SIZE 100 + +#ifdef PLATFORM_LINUX +#define rsprintf snprintf +#elif defined(PLATFORM_WINDOWS) +#define rsprintf sprintf_s +#endif + +#define DCMD_Printf DBG_BT_INFO + +#define delay_ms(ms) rtw_mdelay_os(ms) + +#ifdef bEnable +#undef bEnable +#endif + +#define WPP_SOFTWARE_TRACE 0 + +typedef enum _BTC_MSG_COMP_TYPE { + COMP_COEX = 0, + COMP_MAX +} BTC_MSG_COMP_TYPE; +extern u4Byte GLBtcDbgType[]; + +#define DBG_OFF 0 +#define DBG_SEC 1 +#define DBG_SERIOUS 2 +#define DBG_WARNING 3 +#define DBG_LOUD 4 +#define DBG_TRACE 5 + +#ifdef CONFIG_BT_COEXIST +#define BT_SUPPORT 1 +#define COEX_SUPPORT 1 +#define HS_SUPPORT 1 +#else +#define BT_SUPPORT 0 +#define COEX_SUPPORT 0 +#define HS_SUPPORT 0 +#endif + +#include "halbtcoutsrc.h" +#include "halbtc8192e1ant.h" +#include "halbtc8192e2ant.h" +#include "halbtc8723b1ant.h" +#include "halbtc8723b2ant.h" +#include "halbtc8812a1ant.h" +#include "halbtc8812a2ant.h" +#include "halbtc8821a1ant.h" +#include "halbtc8821a2ant.h" +#include "halbtc8703b1ant.h" +#include "halbtc8723d1ant.h" +#include "halbtc8723d2ant.h" +#include "halbtc8822b1ant.h" +#include "halbtc8822b2ant.h" +#include "halbtc8821c1ant.h" +#include "halbtc8821c2ant.h" + +/* for wifi only mode */ +#include "hal_btcoex_wifionly.h" +#include "halbtc8723bwifionly.h" +#include "halbtc8822bwifionly.h" +#include "halbtc8821cwifionly.h" + +#endif /* __MP_PRECOMP_H__ */ diff --git a/hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.c b/hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.c new file mode 100644 index 0000000..313fa8d --- /dev/null +++ b/hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.c @@ -0,0 +1,100 @@ +/****************************************************************************** + * + * Copyright(c) 2015 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include + +#include "HalEfuseMask8822B_SDIO.h" + +/****************************************************************************** +* MSDIO.TXT +******************************************************************************/ + +u1Byte Array_MP_8822B_MSDIO[] = { +0xFF, +0xF7, +0xEF, +0xDE, +0xFC, +0xFB, +0x10, +0x00, +0x00, +0x00, +0x00, +0x03, +0xF7, +0xFF, +0xFF, +0xFF, +0xFF, +0xFF, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +}; + +u2Byte EFUSE_GetArrayLen_MP_8822B_MSDIO(VOID) +{ + return sizeof(Array_MP_8822B_MSDIO) / sizeof(u1Byte); +} + +VOID EFUSE_GetMaskArray_MP_8822B_MSDIO(pu1Byte Array) +{ + u2Byte len = EFUSE_GetArrayLen_MP_8822B_MSDIO(), i = 0; + + for (i = 0; i < len; ++i) + Array[i] = Array_MP_8822B_MSDIO[i]; +} + +BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MSDIO(u2Byte Offset) +{ + int r = Offset / 16; + int c = (Offset % 16) / 2; + int result = 0; + + if (c < 4) /*Upper double word*/ + result = (Array_MP_8822B_MSDIO[r] & (0x10 << c)); + else + result = (Array_MP_8822B_MSDIO[r] & (0x01 << (c - 4))); + + return (result > 0) ? 0 : 1; +} diff --git a/hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.h b/hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.h new file mode 100644 index 0000000..7ace94e --- /dev/null +++ b/hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.h @@ -0,0 +1,27 @@ +/****************************************************************************** + * + * Copyright(c) 2015 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + + + +/****************************************************************************** +* MSDIO.TXT +******************************************************************************/ + + +u2Byte EFUSE_GetArrayLen_MP_8822B_MSDIO(VOID); + +VOID EFUSE_GetMaskArray_MP_8822B_MSDIO(pu1Byte Array); + +BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MSDIO(u2Byte Offset); diff --git a/hal/hal_btcoex_wifionly.c b/hal/hal_btcoex_wifionly.c new file mode 100644 index 0000000..1abfeb0 --- /dev/null +++ b/hal/hal_btcoex_wifionly.c @@ -0,0 +1,170 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "btc/mp_precomp.h" +#include + +struct wifi_only_cfg GLBtCoexistWifiOnly; + +void halwifionly_write1byte(PVOID pwifionlyContext, u32 RegAddr, u8 Data) +{ + struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; + PADAPTER Adapter = pwifionlycfg->Adapter; + + rtw_write8(Adapter, RegAddr, Data); +} + +void halwifionly_write2byte(PVOID pwifionlyContext, u32 RegAddr, u16 Data) +{ + struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; + PADAPTER Adapter = pwifionlycfg->Adapter; + + rtw_write16(Adapter, RegAddr, Data); +} + +void halwifionly_write4byte(PVOID pwifionlyContext, u32 RegAddr, u32 Data) +{ + struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; + PADAPTER Adapter = pwifionlycfg->Adapter; + + rtw_write32(Adapter, RegAddr, Data); +} + +u8 halwifionly_read1byte(PVOID pwifionlyContext, u32 RegAddr) +{ + struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; + PADAPTER Adapter = pwifionlycfg->Adapter; + + return rtw_read8(Adapter, RegAddr); +} + +u16 halwifionly_read2byte(PVOID pwifionlyContext, u32 RegAddr) +{ + struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; + PADAPTER Adapter = pwifionlycfg->Adapter; + + return rtw_read16(Adapter, RegAddr); +} + +u32 halwifionly_read4byte(PVOID pwifionlyContext, u32 RegAddr) +{ + struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; + PADAPTER Adapter = pwifionlycfg->Adapter; + + return rtw_read32(Adapter, RegAddr); +} + +void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMask, u8 data) +{ + u8 originalValue, bitShift = 0; + u8 i; + + struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; + PADAPTER Adapter = pwifionlycfg->Adapter; + + if (bitMask != 0xff) { + originalValue = rtw_read8(Adapter, regAddr); + for (i = 0; i <= 7; i++) { + if ((bitMask >> i) & 0x1) + break; + } + bitShift = i; + data = ((originalValue) & (~bitMask)) | (((data << bitShift)) & bitMask); + } + rtw_write8(Adapter, regAddr, data); +} + +void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +{ + struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; + PADAPTER Adapter = pwifionlycfg->Adapter; + + phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data); +} + +void halwifionly_phy_set_bb_reg(PVOID pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data) +{ + struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; + PADAPTER Adapter = pwifionlycfg->Adapter; + + phy_set_bb_reg(Adapter, RegAddr, BitMask, Data); +} + +void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 is_5g = _FALSE; + + if (pHalData->current_band_type == BAND_ON_5G) + is_5g = _TRUE; + + if (IS_HARDWARE_TYPE_8822B(padapter)) + ex_hal8822b_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g); + else if (IS_HARDWARE_TYPE_8821C(padapter)) + ex_hal8821c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g); +} + +void hal_btcoex_wifionly_scan_notify(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 is_5g = _FALSE; + + if (pHalData->current_band_type == BAND_ON_5G) + is_5g = _TRUE; + + if (IS_HARDWARE_TYPE_8822B(padapter)) + ex_hal8822b_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g); + else if (IS_HARDWARE_TYPE_8821C(padapter)) + ex_hal8821c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g); +} + +void hal_btcoex_wifionly_hw_config(PADAPTER padapter) +{ + struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly; + + if (IS_HARDWARE_TYPE_8723B(padapter)) + ex_hal8723b_wifi_only_hw_config(pwifionlycfg); + else if (IS_HARDWARE_TYPE_8822B(padapter)) + ex_hal8822b_wifi_only_hw_config(pwifionlycfg); + else if (IS_HARDWARE_TYPE_8821C(padapter)) + ex_hal8821c_wifi_only_hw_config(pwifionlycfg); +} + +void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter) +{ + struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly; + struct wifi_only_haldata *pwifionly_haldata = &pwifionlycfg->haldata_info; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + _rtw_memset(&GLBtCoexistWifiOnly, 0, sizeof(GLBtCoexistWifiOnly)); + + pwifionlycfg->Adapter = padapter; + +#ifdef CONFIG_PCI_HCI + pwifionlycfg->chip_interface = WIFIONLY_INTF_PCI; +#elif defined(CONFIG_USB_HCI) + pwifionlycfg->chip_interface = WIFIONLY_INTF_USB; +#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pwifionlycfg->chip_interface = WIFIONLY_INTF_SDIO; +#else + pwifionlycfg->chip_interface = WIFIONLY_INTF_UNKNOWN; +#endif + + pwifionly_haldata->customer_id = CUSTOMER_NORMAL; + pwifionly_haldata->efuse_pg_antnum = pHalData->EEPROMBluetoothAntNum; + pwifionly_haldata->efuse_pg_antpath = pHalData->ant_path; + pwifionly_haldata->rfe_type = pHalData->rfe_type; + pwifionly_haldata->ant_div_cfg = pHalData->AntDivCfg; +} + diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.c new file mode 100644 index 0000000..5ccbac7 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.c @@ -0,0 +1,73 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "../halmac_88xx_cfg.h" +#include "halmac_8822b_cfg.h" + +/** + * ============ip sel item list============ + * HALMAC_IP_SEL_INTF_PHY + * USB2 : usb2 phy, 1byte value + * USB3 : usb3 phy, 2byte value + * PCIE1 : pcie gen1 mdio, 2byte value + * PCIE2 : pcie gen2 mdio, 2byte value + * HALMAC_IP_SEL_MAC + * USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value + * HALMAC_IP_SEL_PCIE_DBI + * USB2 USB3 : none + * PCIE1, PCIE2 : pcie dbi, 1byte value + */ + +HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_USB2_PHY[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0xFFFF, 0x00, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_USB3_PHY[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_D, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_PCIE_PHY_GEN1[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0002, 0x60C6, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0008, 0x3596, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0009, 0x321C, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x000A, 0x9623, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0020, 0x94FF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0021, 0xFFCF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0026, 0xC006, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0029, 0xFF0E, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x002A, 0x1840, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_PCIE_PHY_GEN2[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0002, 0x60C6, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0008, 0x3597, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0009, 0x321C, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x000A, 0x9623, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0020, 0x94FF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0021, 0xFFCF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0026, 0xC006, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0029, 0xFF0E, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x002A, 0x3040, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, + {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c new file mode 100644 index 0000000..d336323 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c @@ -0,0 +1,559 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_gpio_8822b.h" +#include "../halmac_gpio_88xx.h" + +#if HALMAC_8822B_SUPPORT + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO0_8822B[] = { + HALMAC_GPIO0_BT_GPIO0_8822B, + HALMAC_GPIO0_BT_ACT_8822B, + HALMAC_GPIO0_WL_ACT_8822B, + HALMAC_GPIO0_WLMAC_DBG_GPIO0_8822B, + HALMAC_GPIO0_WLPHY_DBG_GPIO0_8822B, + HALMAC_GPIO0_BT_DBG_GPIO0_8822B, + HALMAC_GPIO0_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO1_8822B[] = { + HALMAC_GPIO1_BT_GPIO1_8822B, + HALMAC_GPIO1_BT_3DD_SYNC_A_8822B, + HALMAC_GPIO1_WL_CK_8822B, + HALMAC_GPIO1_BT_CK_8822B, + HALMAC_GPIO1_WLMAC_DBG_GPIO1_8822B, + HALMAC_GPIO1_WLPHY_DBG_GPIO1_8822B, + HALMAC_GPIO1_BT_DBG_GPIO1_8822B, + HALMAC_GPIO1_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO2_8822B[] = { + HALMAC_GPIO2_BT_GPIO2_8822B, + HALMAC_GPIO2_WL_STATE_8822B, + HALMAC_GPIO2_BT_STATE_8822B, + HALMAC_GPIO2_WLMAC_DBG_GPIO2_8822B, + HALMAC_GPIO2_WLPHY_DBG_GPIO2_8822B, + HALMAC_GPIO2_BT_DBG_GPIO2_8822B, + HALMAC_GPIO2_RFE_CTRL_5_8822B, + HALMAC_GPIO2_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO3_8822B[] = { + HALMAC_GPIO3_BT_GPIO3_8822B, + HALMAC_GPIO3_WL_PRI_8822B, + HALMAC_GPIO3_BT_PRI_8822B, + HALMAC_GPIO3_WLMAC_DBG_GPIO3_8822B, + HALMAC_GPIO3_WLPHY_DBG_GPIO3_8822B, + HALMAC_GPIO3_BT_DBG_GPIO3_8822B, + HALMAC_GPIO3_RFE_CTRL_4_8822B, + HALMAC_GPIO3_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO4_8822B[] = { + HALMAC_GPIO4_BT_SPI_D0_8822B, + HALMAC_GPIO4_WL_SPI_D0_8822B, + HALMAC_GPIO4_SDIO_INT_8822B, + HALMAC_GPIO4_JTAG_TRST_8822B, + HALMAC_GPIO4_DBG_GNT_WL_8822B, + HALMAC_GPIO4_WLMAC_DBG_GPIO4_8822B, + HALMAC_GPIO4_WLPHY_DBG_GPIO4_8822B, + HALMAC_GPIO4_BT_DBG_GPIO4_8822B, + HALMAC_GPIO4_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO5_8822B[] = { + HALMAC_GPIO5_BT_SPI_D1_8822B, + HALMAC_GPIO5_WL_SPI_D1_8822B, + HALMAC_GPIO5_JTAG_TDI_8822B, + HALMAC_GPIO5_DBG_GNT_BT, + HALMAC_GPIO5_WLMAC_DBG_GPIO5_8822B, + HALMAC_GPIO5_WLPHY_DBG_GPIO5_8822B, + HALMAC_GPIO5_BT_DBG_GPIO5_8822B, + HALMAC_GPIO5_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO6_8822B[] = { + HALMAC_GPIO6_BT_SPI_D2_8822B, + HALMAC_GPIO6_WL_SPI_D2_8822B, + HALMAC_GPIO6_EEDO_8822B, + HALMAC_GPIO6_JTAG_TDO_8822B, + HALMAC_GPIO6_BT_3DD_SYNC_B_8822B, + HALMAC_GPIO6_BT_GPIO18_8822B, + HALMAC_GPIO6_SIN_8822B, + HALMAC_GPIO6_WLMAC_DBG_GPIO6_8822B, + HALMAC_GPIO6_WLPHY_DBG_GPIO6_8822B, + HALMAC_GPIO6_BT_DBG_GPIO6_8822B, + HALMAC_GPIO6_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO7_8822B[] = { + HALMAC_GPIO7_BT_SPI_D3_8822B, + HALMAC_GPIO7_WL_SPI_D3_8822B, + HALMAC_GPIO7_EEDI_8822B, + HALMAC_GPIO7_JTAG_TMS_8822B, + HALMAC_GPIO7_BT_GPIO16_8822B, + HALMAC_GPIO7_SOUT_8822B, + HALMAC_GPIO7_WLMAC_DBG_GPIO7_8822B, + HALMAC_GPIO7_WLPHY_DBG_GPIO7_8822B, + HALMAC_GPIO7_BT_DBG_GPIO7_8822B, + HALMAC_GPIO7_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO8_8822B[] = { + HALMAC_GPIO8_WL_EXT_WOL_8822B, + HALMAC_GPIO8_WL_LED, + HALMAC_GPIO8_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO9_8822B[] = { + HALMAC_GPIO9_DIS_WL_N_8822B, + HALMAC_GPIO9_WL_EXT_WOL_8822B, + HALMAC_GPIO9_USCTS0_8822B, + HALMAC_GPIO9_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO10_8822B[] = { + HALMAC_GPIO10_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO11_8822B[] = { + HALMAC_GPIO11_DIS_BT_N_8822B, + HALMAC_GPIO11_USOUT0_8822B, + HALMAC_GPIO11_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO12_8822B[] = { + HALMAC_GPIO12_USIN0_8822B, + HALMAC_GPIO12_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO13_8822B[] = { + HALMAC_GPIO13_BT_WAKE_8822B, + HALMAC_GPIO13_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO14_8822B[] = { + HALMAC_GPIO14_UART_WAKE_8822B, + HALMAC_GPIO14_SW_IO_8822B +}; + +const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO15_8822B[] = { + HALMAC_GPIO15_EXT_XTAL_8822B, + HALMAC_GPIO15_SW_IO_8822B +}; + +static HALMAC_RET_STATUS +halmac_get_pinmux_list_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_GPIO_FUNC gpio_func, + OUT const HALMAC_GPIO_PIMUX_LIST **ppPinmux_list, + OUT u32 *pList_size, + OUT u32 *pGpio_id +); + +static HALMAC_RET_STATUS +halmac_chk_pinmux_valid_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_GPIO_FUNC gpio_func +); + +/** + * halmac_pinmux_get_func_8822b() -get current gpio status + * @pHalmac_adapter : the adapter of halmac + * @gpio_func : gpio function + * @pEnable : function is enable(1) or disable(0) + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_pinmux_get_func_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_GPIO_FUNC gpio_func, + OUT u8 *pEnable +) +{ + u32 list_size; + u32 curr_func; + u32 gpio_id; + HALMAC_RET_STATUS status; + const HALMAC_GPIO_PIMUX_LIST *pPinmux_list = NULL; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_get_func_8822b ==========>\n"); + + status = halmac_get_pinmux_list_8822b(pHalmac_adapter, gpio_func, &pPinmux_list, &list_size, &gpio_id); + if (status != HALMAC_RET_SUCCESS) + return status; + + status = halmac_pinmux_parser_88xx(pHalmac_adapter, pPinmux_list, list_size, gpio_id, &curr_func); + if (status != HALMAC_RET_SUCCESS) + return status; + + switch (gpio_func) { + case HALMAC_GPIO_FUNC_WL_LED: + *pEnable = (curr_func == HALMAC_WL_LED) ? 1 : 0; + break; + case HALMAC_GPIO_FUNC_SDIO_INT: + *pEnable = (curr_func == HALMAC_SDIO_INT) ? 1 : 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_0: + case HALMAC_GPIO_FUNC_SW_IO_1: + case HALMAC_GPIO_FUNC_SW_IO_2: + case HALMAC_GPIO_FUNC_SW_IO_3: + case HALMAC_GPIO_FUNC_SW_IO_4: + case HALMAC_GPIO_FUNC_SW_IO_5: + case HALMAC_GPIO_FUNC_SW_IO_6: + case HALMAC_GPIO_FUNC_SW_IO_7: + case HALMAC_GPIO_FUNC_SW_IO_8: + case HALMAC_GPIO_FUNC_SW_IO_9: + case HALMAC_GPIO_FUNC_SW_IO_10: + case HALMAC_GPIO_FUNC_SW_IO_11: + case HALMAC_GPIO_FUNC_SW_IO_12: + case HALMAC_GPIO_FUNC_SW_IO_13: + case HALMAC_GPIO_FUNC_SW_IO_14: + case HALMAC_GPIO_FUNC_SW_IO_15: + *pEnable = (curr_func == HALMAC_SW_IO) ? 1 : 0; + break; + default: + *pEnable = 0; + return HALMAC_RET_GET_PINMUX_ERR; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_get_func_8822b <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pinmux_set_func_8822b() -set gpio function + * @pHalmac_adapter : the adapter of halmac + * @gpio_func : gpio function + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_pinmux_set_func_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_GPIO_FUNC gpio_func +) +{ + u32 list_size; + u32 gpio_id; + HALMAC_RET_STATUS status; + const HALMAC_GPIO_PIMUX_LIST *pPinmux_list = NULL; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_set_func_8822b ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]func name : %d\n", gpio_func); + + status = halmac_chk_pinmux_valid_8822b(pHalmac_adapter, gpio_func); + if (status != HALMAC_RET_SUCCESS) + return status; + + status = halmac_get_pinmux_list_8822b(pHalmac_adapter, gpio_func, &pPinmux_list, &list_size, &gpio_id); + if (status != HALMAC_RET_SUCCESS) + return status; + + status = halmac_pinmux_switch_88xx(pHalmac_adapter, pPinmux_list, list_size, gpio_id, gpio_func); + if (status != HALMAC_RET_SUCCESS) + return status; + + status = halmac_pinmux_record_88xx(pHalmac_adapter, gpio_func, 1); + if (status != HALMAC_RET_SUCCESS) + return status; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_set_func_8822b <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pinmux_free_func_8822b() -free locked gpio function + * @pHalmac_adapter : the adapter of halmac + * @gpio_func : gpio function + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_pinmux_free_func_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_GPIO_FUNC gpio_func +) +{ + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_free_func_8822b ==========>\n"); + + switch (gpio_func) { + case HALMAC_GPIO_FUNC_SW_IO_0: + pHalmac_adapter->pinmux_info.sw_io_0 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_1: + pHalmac_adapter->pinmux_info.sw_io_1 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_2: + pHalmac_adapter->pinmux_info.sw_io_2 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_3: + pHalmac_adapter->pinmux_info.sw_io_3 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_4: + case HALMAC_GPIO_FUNC_SDIO_INT: + pHalmac_adapter->pinmux_info.sw_io_4 = 0; + pHalmac_adapter->pinmux_info.sdio_int = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_5: + pHalmac_adapter->pinmux_info.sw_io_5 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_6: + pHalmac_adapter->pinmux_info.sw_io_6 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_7: + pHalmac_adapter->pinmux_info.sw_io_7 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_8: + case HALMAC_GPIO_FUNC_WL_LED: + pHalmac_adapter->pinmux_info.sw_io_8 = 0; + pHalmac_adapter->pinmux_info.wl_led = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_9: + pHalmac_adapter->pinmux_info.sw_io_9 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_10: + pHalmac_adapter->pinmux_info.sw_io_10 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_11: + pHalmac_adapter->pinmux_info.sw_io_11 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_12: + pHalmac_adapter->pinmux_info.sw_io_12 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_13: + pHalmac_adapter->pinmux_info.sw_io_13 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_14: + pHalmac_adapter->pinmux_info.sw_io_14 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_15: + pHalmac_adapter->pinmux_info.sw_io_15 = 0; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]func : %X\n", gpio_func); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_free_func_8822b <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +static HALMAC_RET_STATUS +halmac_get_pinmux_list_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_GPIO_FUNC gpio_func, + OUT const HALMAC_GPIO_PIMUX_LIST **ppPinmux_list, + OUT u32 *pList_size, + OUT u32 *pGpio_id +) +{ + switch (gpio_func) { + case HALMAC_GPIO_FUNC_SW_IO_0: + *ppPinmux_list = PIMUX_LIST_GPIO0_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO0_8822B); + *pGpio_id = HALMAC_GPIO0; + break; + case HALMAC_GPIO_FUNC_SW_IO_1: + *ppPinmux_list = PIMUX_LIST_GPIO1_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO1_8822B); + *pGpio_id = HALMAC_GPIO1; + break; + case HALMAC_GPIO_FUNC_SW_IO_2: + *ppPinmux_list = PIMUX_LIST_GPIO2_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO2_8822B); + *pGpio_id = HALMAC_GPIO2; + break; + case HALMAC_GPIO_FUNC_SW_IO_3: + *ppPinmux_list = PIMUX_LIST_GPIO3_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO3_8822B); + *pGpio_id = HALMAC_GPIO3; + break; + case HALMAC_GPIO_FUNC_SW_IO_4: + case HALMAC_GPIO_FUNC_SDIO_INT: + *ppPinmux_list = PIMUX_LIST_GPIO4_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO4_8822B); + *pGpio_id = HALMAC_GPIO4; + break; + case HALMAC_GPIO_FUNC_SW_IO_5: + *ppPinmux_list = PIMUX_LIST_GPIO5_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO5_8822B); + *pGpio_id = HALMAC_GPIO5; + break; + case HALMAC_GPIO_FUNC_SW_IO_6: + *ppPinmux_list = PIMUX_LIST_GPIO6_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO6_8822B); + *pGpio_id = HALMAC_GPIO6; + break; + case HALMAC_GPIO_FUNC_SW_IO_7: + *ppPinmux_list = PIMUX_LIST_GPIO7_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO7_8822B); + *pGpio_id = HALMAC_GPIO7; + break; + case HALMAC_GPIO_FUNC_SW_IO_8: + case HALMAC_GPIO_FUNC_WL_LED: + *ppPinmux_list = PIMUX_LIST_GPIO8_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO8_8822B); + *pGpio_id = HALMAC_GPIO8; + break; + case HALMAC_GPIO_FUNC_SW_IO_9: + *ppPinmux_list = PIMUX_LIST_GPIO9_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO9_8822B); + *pGpio_id = HALMAC_GPIO9; + break; + case HALMAC_GPIO_FUNC_SW_IO_10: + *ppPinmux_list = PIMUX_LIST_GPIO10_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO10_8822B); + *pGpio_id = HALMAC_GPIO10; + break; + case HALMAC_GPIO_FUNC_SW_IO_11: + *ppPinmux_list = PIMUX_LIST_GPIO11_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO11_8822B); + *pGpio_id = HALMAC_GPIO11; + break; + case HALMAC_GPIO_FUNC_SW_IO_12: + *ppPinmux_list = PIMUX_LIST_GPIO12_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO12_8822B); + *pGpio_id = HALMAC_GPIO12; + break; + case HALMAC_GPIO_FUNC_SW_IO_13: + *ppPinmux_list = PIMUX_LIST_GPIO13_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO13_8822B); + *pGpio_id = HALMAC_GPIO13; + break; + case HALMAC_GPIO_FUNC_SW_IO_14: + *ppPinmux_list = PIMUX_LIST_GPIO14_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO14_8822B); + *pGpio_id = HALMAC_GPIO14; + break; + case HALMAC_GPIO_FUNC_SW_IO_15: + *ppPinmux_list = PIMUX_LIST_GPIO15_8822B; + *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO15_8822B); + *pGpio_id = HALMAC_GPIO15; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + return HALMAC_RET_SUCCESS; +} + +static HALMAC_RET_STATUS +halmac_chk_pinmux_valid_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_GPIO_FUNC gpio_func +) +{ + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + switch (gpio_func) { + case HALMAC_GPIO_FUNC_SW_IO_0: + if (pHalmac_adapter->pinmux_info.sw_io_0 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_1: + if (pHalmac_adapter->pinmux_info.sw_io_1 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_2: + if (pHalmac_adapter->pinmux_info.sw_io_2 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_3: + if (pHalmac_adapter->pinmux_info.sw_io_3 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_4: + case HALMAC_GPIO_FUNC_SDIO_INT: + if ((pHalmac_adapter->pinmux_info.sw_io_4 == 1) || (pHalmac_adapter->pinmux_info.sdio_int == 1)) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_5: + if (pHalmac_adapter->pinmux_info.sw_io_5 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_6: + if (pHalmac_adapter->pinmux_info.sw_io_6 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_7: + if (pHalmac_adapter->pinmux_info.sw_io_7 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_8: + case HALMAC_GPIO_FUNC_WL_LED: + if ((pHalmac_adapter->pinmux_info.sw_io_8 == 1) || (pHalmac_adapter->pinmux_info.wl_led == 1)) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_9: + if (pHalmac_adapter->pinmux_info.sw_io_9 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_10: + if (pHalmac_adapter->pinmux_info.sw_io_10 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_11: + if (pHalmac_adapter->pinmux_info.sw_io_11 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_12: + if (pHalmac_adapter->pinmux_info.sw_io_12 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_13: + if (pHalmac_adapter->pinmux_info.sw_io_13 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_14: + if (pHalmac_adapter->pinmux_info.sw_io_14 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_15: + if (pHalmac_adapter->pinmux_info.sw_io_15 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]chk_pinmux_valid func : %X status : %X\n", + gpio_func, status); + + return status; +} + +#endif /* HALMAC_8822B_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h new file mode 100644 index 0000000..2bbf97e --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h @@ -0,0 +1,168 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_GPIO_8822B_H_ +#define _HALMAC_GPIO_8822B_H_ + +#include "../../halmac_api.h" +#include "../../halmac_gpio_cmd.h" + +#if HALMAC_8822B_SUPPORT + +/* P_LED0 definition */ +#define HALMAC_GPIO0_BT_GPIO0_8822B {HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, 0x66, BIT(2), BIT(2)} + +/* GPIO0 definition */ +#define HALMAC_GPIO0_BT_GPIO0_8822B {HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, 0x66, BIT(2), BIT(2)} +#define HALMAC_GPIO0_BT_ACT_8822B {HALMAC_BT_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, 0x41, BIT(1), 0} +#define HALMAC_GPIO0_WL_ACT_8822B {HALMAC_WL_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, 0x41, BIT(2), BIT(2)} +#define HALMAC_GPIO0_WLMAC_DBG_GPIO0_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} +#define HALMAC_GPIO0_WLPHY_DBG_GPIO0_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} +#define HALMAC_GPIO0_BT_DBG_GPIO0_8822B {HALMAC_BT_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define HALMAC_GPIO0_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO1 definition */ +#define HALMAC_GPIO1_BT_GPIO1_8822B {HALMAC_BT_GPIO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, 0x66, BIT(2), BIT(2)} +#define HALMAC_GPIO1_BT_3DD_SYNC_A_8822B {HALMAC_BT_3DDLS_A, HALMAC_GPIO1, HALMAC_GPIO_IN, 0x66, BIT(2), BIT(2)} +#define HALMAC_GPIO1_WL_CK_8822B {HALMAC_BT_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, 0x41, BIT(1), 0} +#define HALMAC_GPIO1_BT_CK_8822B {HALMAC_WL_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, 0x41, BIT(2), BIT(2)} +#define HALMAC_GPIO1_WLMAC_DBG_GPIO1_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} +#define HALMAC_GPIO1_WLPHY_DBG_GPIO1_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} +#define HALMAC_GPIO1_BT_DBG_GPIO1_8822B {HALMAC_BT_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define HALMAC_GPIO1_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO2 definition */ +#define HALMAC_GPIO2_BT_GPIO2_8822B {HALMAC_BT_GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, 0x66, BIT(2), BIT(2)} +#define HALMAC_GPIO2_WL_STATE_8822B {HALMAC_BT_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, 0x41, BIT(1), 0} +#define HALMAC_GPIO2_BT_STATE_8822B {HALMAC_WL_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, 0x41, BIT(2), BIT(2)} +#define HALMAC_GPIO2_WLMAC_DBG_GPIO2_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} +#define HALMAC_GPIO2_WLPHY_DBG_GPIO2_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} +#define HALMAC_GPIO2_BT_DBG_GPIO2_8822B {HALMAC_BT_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define HALMAC_GPIO2_RFE_CTRL_5_8822B {HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, 0x40, BIT(2), BIT(2)} +#define HALMAC_GPIO2_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO3 definition */ +#define HALMAC_GPIO3_BT_GPIO3_8822B {HALMAC_BT_GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, 0x66, BIT(2), BIT(2)} +#define HALMAC_GPIO3_WL_PRI_8822B {HALMAC_BT_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, 0x41, BIT(1), 0} +#define HALMAC_GPIO3_BT_PRI_8822B {HALMAC_WL_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, 0x41, BIT(2), BIT(2)} +#define HALMAC_GPIO3_WLMAC_DBG_GPIO3_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} +#define HALMAC_GPIO3_WLPHY_DBG_GPIO3_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} +#define HALMAC_GPIO3_BT_DBG_GPIO3_8822B {HALMAC_BT_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define HALMAC_GPIO3_RFE_CTRL_4_8822B {HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, 0x40, BIT(2), BIT(2)} +#define HALMAC_GPIO3_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO4 definition */ +#define HALMAC_GPIO4_BT_SPI_D0_8822B {HALMAC_BT_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, 0x66, BIT(4), BIT(4)} +#define HALMAC_GPIO4_WL_SPI_D0_8822B {HALMAC_WL_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, 0x42, BIT(3), BIT(3)} +#define HALMAC_GPIO4_SDIO_INT_8822B {HALMAC_SDIO_INT, HALMAC_GPIO4, HALMAC_GPIO_OUT, 0x72, BIT(2), BIT(2)} +#define HALMAC_GPIO4_JTAG_TRST_8822B {HALMAC_JTAG, HALMAC_GPIO4, HALMAC_GPIO_IN, 0x67, BIT(0), BIT(0)} +#define HALMAC_GPIO4_DBG_GNT_WL_8822B {HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO4, HALMAC_GPIO_OUT, 0x73, BIT(3), BIT(3)} +#define HALMAC_GPIO4_WLMAC_DBG_GPIO4_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} +#define HALMAC_GPIO4_WLPHY_DBG_GPIO4_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} +#define HALMAC_GPIO4_BT_DBG_GPIO4_8822B {HALMAC_BT_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define HALMAC_GPIO4_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO5 definition */ +#define HALMAC_GPIO5_BT_SPI_D1_8822B {HALMAC_BT_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, 0x66, BIT(4), BIT(4)} +#define HALMAC_GPIO5_WL_SPI_D1_8822B {HALMAC_WL_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, 0x42, BIT(3), BIT(3)} +#define HALMAC_GPIO5_JTAG_TDI_8822B {HALMAC_JTAG, HALMAC_GPIO5, HALMAC_GPIO_IN, 0x67, BIT(0), BIT(0)} +#define HALMAC_GPIO5_DBG_GNT_BT {HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO5, HALMAC_GPIO_OUT, 0x73, BIT(3), BIT(3)} +#define HALMAC_GPIO5_WLMAC_DBG_GPIO5_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} +#define HALMAC_GPIO5_WLPHY_DBG_GPIO5_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} +#define HALMAC_GPIO5_BT_DBG_GPIO5_8822B {HALMAC_BT_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define HALMAC_GPIO5_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO6 definition */ +#define HALMAC_GPIO6_BT_SPI_D2_8822B {HALMAC_BT_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, 0x66, BIT(4), BIT(4)} +#define HALMAC_GPIO6_WL_SPI_D2_8822B {HALMAC_WL_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, 0x42, BIT(3), BIT(3)} +#define HALMAC_GPIO6_EEDO_8822B {HALMAC_EEPROM, HALMAC_GPIO6, HALMAC_GPIO_IN, 0x40, BIT(4), BIT(4)} +#define HALMAC_GPIO6_JTAG_TDO_8822B {HALMAC_JTAG, HALMAC_GPIO6, HALMAC_GPIO_OUT, 0x67, BIT(0), BIT(0)} +#define HALMAC_GPIO6_BT_3DD_SYNC_B_8822B {HALMAC_BT_3DDLS_B, HALMAC_GPIO6, HALMAC_GPIO_IN, 0x67, BIT(1), BIT(1)} +#define HALMAC_GPIO6_BT_GPIO18_8822B {HALMAC_BT_GPIO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, 0x67, BIT(1), BIT(1)} +#define HALMAC_GPIO6_SIN_8822B {HALMAC_WL_UART, HALMAC_GPIO6, HALMAC_GPIO_IN, 0x41, BIT(0), BIT(0)} +#define HALMAC_GPIO6_WLMAC_DBG_GPIO6_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} +#define HALMAC_GPIO6_WLPHY_DBG_GPIO6_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} +#define HALMAC_GPIO6_BT_DBG_GPIO6_8822B {HALMAC_BT_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define HALMAC_GPIO6_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO7 definition */ +#define HALMAC_GPIO7_BT_SPI_D3_8822B {HALMAC_BT_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, 0x66, BIT(4), BIT(4)} +#define HALMAC_GPIO7_WL_SPI_D3_8822B {HALMAC_WL_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, 0x42, BIT(3), BIT(3)} +#define HALMAC_GPIO7_EEDI_8822B {HALMAC_EEPROM, HALMAC_GPIO7, HALMAC_GPIO_OUT, 0x40, BIT(4), BIT(4)} +#define HALMAC_GPIO7_JTAG_TMS_8822B {HALMAC_JTAG, HALMAC_GPIO7, HALMAC_GPIO_IN, 0x67, BIT(0), BIT(0)} +#define HALMAC_GPIO7_BT_GPIO16_8822B {HALMAC_BT_GPIO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, 0x67, BIT(2), BIT(2)} +#define HALMAC_GPIO7_SOUT_8822B {HALMAC_WL_UART, HALMAC_GPIO7, HALMAC_GPIO_OUT, 0x41, BIT(0), BIT(0)} +#define HALMAC_GPIO7_WLMAC_DBG_GPIO7_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} +#define HALMAC_GPIO7_WLPHY_DBG_GPIO7_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} +#define HALMAC_GPIO7_BT_DBG_GPIO7_8822B {HALMAC_BT_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define HALMAC_GPIO7_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO8 definition */ +#define HALMAC_GPIO8_WL_EXT_WOL_8822B {HALMAC_WL_HW_EXTWOL, HALMAC_GPIO8, HALMAC_GPIO_IN, 0x4a, BIT(0) | BIT(1), BIT(0) | BIT(1)} +#define HALMAC_GPIO8_WL_LED {HALMAC_WL_LED, HALMAC_GPIO8, HALMAC_GPIO_OUT, 0x4e, BIT(5), BIT(5)} +#define HALMAC_GPIO8_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO8, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO9 definition */ +#define HALMAC_GPIO9_DIS_WL_N_8822B {HALMAC_WL_HWPDN, HALMAC_GPIO9, HALMAC_GPIO_IN, 0x68, BIT(3) | BIT(0), BIT(3) | BIT(0)} +#define HALMAC_GPIO9_WL_EXT_WOL_8822B {HALMAC_WL_HW_EXTWOL, HALMAC_GPIO9, HALMAC_GPIO_IN, 0x4a, BIT(0) | BIT(1), BIT(0)} +#define HALMAC_GPIO9_USCTS0_8822B {HALMAC_UART0, HALMAC_GPIO9, HALMAC_GPIO_IN, 0x66, BIT(6), BIT(6)} +#define HALMAC_GPIO9_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO9, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO10 definition */ +#define HALMAC_GPIO10_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO10, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO11 definition */ +#define HALMAC_GPIO11_DIS_BT_N_8822B {HALMAC_BT_HWPDN, HALMAC_GPIO11, HALMAC_GPIO_IN, 0x6a, BIT(0), BIT(0)} +#define HALMAC_GPIO11_USOUT0_8822B {HALMAC_UART0, HALMAC_GPIO11, HALMAC_GPIO_OUT, 0x66, BIT(6), BIT(6)} +#define HALMAC_GPIO11_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO11, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO12 definition */ +#define HALMAC_GPIO12_USIN0_8822B {HALMAC_UART0, HALMAC_GPIO12, HALMAC_GPIO_IN, 0x66, BIT(6), BIT(6)} +#define HALMAC_GPIO12_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO12, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO13 definition */ +#define HALMAC_GPIO13_BT_WAKE_8822B {HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO13, HALMAC_GPIO_IN, 0x4e, BIT(6), BIT(6)} +#define HALMAC_GPIO13_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO14 definition */ +#define HALMAC_GPIO14_UART_WAKE_8822B {HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO14, HALMAC_GPIO_OUT, 0x4e, BIT(6), BIT(6)} +#define HALMAC_GPIO14_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO14, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +/* GPIO15 definition */ +#define HALMAC_GPIO15_EXT_XTAL_8822B {HALMAC_EXT_XTAL, HALMAC_GPIO15, HALMAC_GPIO_OUT, 0x66, BIT(7), BIT(7)} +#define HALMAC_GPIO15_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO15, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} + +HALMAC_RET_STATUS +halmac_pinmux_get_func_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_GPIO_FUNC gpio_func, + OUT u8 *pEnable +); + +HALMAC_RET_STATUS +halmac_pinmux_set_func_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_GPIO_FUNC gpio_func +); + +HALMAC_RET_STATUS +halmac_pinmux_free_func_8822b( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_GPIO_FUNC gpio_func +); + +#endif /* HALMAC_8822B_SUPPORT */ + +#endif/* _HALMAC_GPIO_8822B_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_gpio_88xx.c b/hal/halmac/halmac_88xx/halmac_gpio_88xx.c new file mode 100644 index 0000000..436220c --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_gpio_88xx.c @@ -0,0 +1,453 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_gpio_88xx.h" + +/** + * halmac_pinmux_wl_led_mode_88xx() -control wlan led gpio function + * @pHalmac_adapter : the adapter of halmac + * @wlled_mode : wlan led mode + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_pinmux_wl_led_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_WLLED_MODE wlled_mode +) +{ + u8 value8; + PHALMAC_API pHalmac_api; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_wl_led_mode_88xx ==========>\n"); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_LED_CFG + 2); + value8 &= ~(BIT(6)); + value8 |= BIT(3); + value8 &= ~(BIT(0) | BIT(1) | BIT(2)); + + switch (wlled_mode) { + case HALMAC_WLLED_MODE_TRX: + value8 |= 2; + break; + case HALMAC_WLLED_MODE_TX: + value8 |= 4; + break; + case HALMAC_WLLED_MODE_RX: + value8 |= 6; + break; + case HALMAC_WLLED_MODE_SW_CTRL: + value8 |= 0; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LED_CFG + 2, value8); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_wl_led_mode_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pinmux_wl_led_sw_ctrl_88xx() -control wlan led on/off + * @pHalmac_adapter : the adapter of halmac + * @led_on : on(1), off(0) + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +VOID +halmac_pinmux_wl_led_sw_ctrl_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 led_on +) +{ + u8 value8; + PHALMAC_API pHalmac_api; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_LED_CFG + 2); + value8 = (led_on == 0) ? value8 | BIT(3) : value8 & ~(BIT(3)); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LED_CFG + 2, value8); +} + +/** + * halmac_pinmux_sdio_int_polarity_88xx() -control sdio int polarity + * @pHalmac_adapter : the adapter of halmac + * @low_active : low active(1), high active(0) + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +VOID +halmac_pinmux_sdio_int_polarity_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 low_active +) +{ + u8 value8; + PHALMAC_API pHalmac_api; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_SDIO_CTRL + 2); + value8 = (low_active == 0) ? value8 | BIT(3) : value8 & ~(BIT(3)); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_SDIO_CTRL + 2, value8); +} + +/** + * halmac_pinmux_gpio_mode_88xx() -control gpio io mode + * @pHalmac_adapter : the adapter of halmac + * @gpio_id : gpio0~15(0~15) + * @output : output(1), input(0) + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_pinmux_gpio_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 gpio_id, + IN u8 output +) +{ + u16 value16; + u8 in_out; + u32 offset; + PHALMAC_API pHalmac_api; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (gpio_id <= 7) + offset = REG_GPIO_PIN_CTRL + 2; + else if (gpio_id >= 8 && gpio_id <= 15) + offset = REG_GPIO_EXT_CTRL + 2; + else + return HALMAC_RET_WRONG_GPIO; + + in_out = (output == 0) ? 0 : 1; + gpio_id &= (8 - 1); + + value16 = HALMAC_REG_READ_16(pHalmac_adapter, offset); + value16 &= ~((1 << gpio_id) | (1 << gpio_id << 8)); + value16 |= (in_out << gpio_id); + HALMAC_REG_WRITE_16(pHalmac_adapter, offset, value16); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pinmux_gpio_output_88xx() -control gpio output high/low + * @pHalmac_adapter : the adapter of halmac + * @gpio_id : gpio0~15(0~15) + * @high : high(1), low(0) + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_pinmux_gpio_output_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 gpio_id, + IN u8 high +) +{ + u8 value8; + u8 hi_low; + u32 offset; + PHALMAC_API pHalmac_api; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (gpio_id <= 7) + offset = REG_GPIO_PIN_CTRL + 1; + else if (gpio_id >= 8 && gpio_id <= 15) + offset = REG_GPIO_EXT_CTRL + 1; + else + return HALMAC_RET_WRONG_GPIO; + + hi_low = (high == 0) ? 0 : 1; + gpio_id &= (8 - 1); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, offset); + value8 &= ~(1 << gpio_id); + value8 |= (hi_low << gpio_id); + HALMAC_REG_WRITE_8(pHalmac_adapter, offset, value8); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pinmux_status_88xx() -get current gpio status(high/low) + * @pHalmac_adapter : the adapter of halmac + * @pin_id : 0~15(0~15) + * @phigh : high(1), low(0) + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_pinmux_pin_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 pin_id, + OUT u8 *pHigh +) +{ + u8 value8; + u32 offset; + PHALMAC_API pHalmac_api; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (pin_id <= 7) + offset = REG_GPIO_PIN_CTRL; + else if (pin_id >= 8 && pin_id <= 15) + offset = REG_GPIO_EXT_CTRL; + else + return HALMAC_RET_WRONG_GPIO; + + pin_id &= (8 - 1); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, offset); + *pHigh = (value8 & (1 << pin_id)) >> pin_id; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_pinmux_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN const HALMAC_GPIO_PIMUX_LIST *pPinmux_list, + IN u32 list_size, + IN u32 gpio_id, + OUT u32 *pCur_func +) +{ + u8 value8; + u32 i; + const HALMAC_GPIO_PIMUX_LIST *pCurr_func; + HALMAC_GPIO_CFG_STATE *pGpio_state = &pHalmac_adapter->halmac_state.gpio_cfg_state; + PHALMAC_API pHalmac_api; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + pCurr_func = pPinmux_list; + + if (*pGpio_state == HALMAC_GPIO_CFG_STATE_BUSY) + return HALMAC_RET_BUSY_STATE; + + *pGpio_state = HALMAC_GPIO_CFG_STATE_BUSY; + + for (i = 0; i < list_size; i++) { + if (gpio_id != pCurr_func->id) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]offset : %X, value : %X, func : %X\n", + pCurr_func->offset, pCurr_func->value, pCurr_func->func); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]id1 : %X, id2 : %X\n", gpio_id, pCurr_func->id); + *pGpio_state = HALMAC_GPIO_CFG_STATE_IDLE; + return HALMAC_RET_GET_PINMUX_ERR; + } + value8 = HALMAC_REG_READ_8(pHalmac_adapter, pCurr_func->offset); + value8 &= pCurr_func->msk; + if (value8 == pCurr_func->value) { + *pCur_func = pCurr_func->func; + break; + } + pCurr_func++; + } + + *pGpio_state = HALMAC_GPIO_CFG_STATE_IDLE; + + if (i == list_size) + return HALMAC_RET_GET_PINMUX_ERR; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_pinmux_switch_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN const HALMAC_GPIO_PIMUX_LIST *pPinmux_list, + IN u32 list_size, + IN u32 gpio_id, + IN HALMAC_GPIO_FUNC gpio_func +) +{ + u32 i; + u8 value8; + u16 switch_func; + const HALMAC_GPIO_PIMUX_LIST *pCurr_func; + HALMAC_GPIO_CFG_STATE *pGpio_state = &pHalmac_adapter->halmac_state.gpio_cfg_state; + PHALMAC_API pHalmac_api; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + pCurr_func = pPinmux_list; + + if (*pGpio_state == HALMAC_GPIO_CFG_STATE_BUSY) + return HALMAC_RET_BUSY_STATE; + + switch (gpio_func) { + case HALMAC_GPIO_FUNC_WL_LED: + switch_func = HALMAC_WL_LED; + break; + case HALMAC_GPIO_FUNC_SDIO_INT: + switch_func = HALMAC_SDIO_INT; + break; + case HALMAC_GPIO_FUNC_SW_IO_0: + case HALMAC_GPIO_FUNC_SW_IO_1: + case HALMAC_GPIO_FUNC_SW_IO_2: + case HALMAC_GPIO_FUNC_SW_IO_3: + case HALMAC_GPIO_FUNC_SW_IO_4: + case HALMAC_GPIO_FUNC_SW_IO_5: + case HALMAC_GPIO_FUNC_SW_IO_6: + case HALMAC_GPIO_FUNC_SW_IO_7: + case HALMAC_GPIO_FUNC_SW_IO_8: + case HALMAC_GPIO_FUNC_SW_IO_9: + case HALMAC_GPIO_FUNC_SW_IO_10: + case HALMAC_GPIO_FUNC_SW_IO_11: + case HALMAC_GPIO_FUNC_SW_IO_12: + case HALMAC_GPIO_FUNC_SW_IO_13: + case HALMAC_GPIO_FUNC_SW_IO_14: + case HALMAC_GPIO_FUNC_SW_IO_15: + switch_func = HALMAC_SW_IO; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + for (i = 0; i < list_size; i++) { + if (gpio_id != pCurr_func->id) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]offset : %X, value : %X, func : %X\n", + pCurr_func->offset, pCurr_func->value, pCurr_func->func); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]id1 : %X, id2 : %X\n", gpio_id, pCurr_func->id); + return HALMAC_RET_GET_PINMUX_ERR; + } + + if (switch_func == pCurr_func->func) + break; + + pCurr_func++; + } + + if (i == list_size) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]gpio func error : %X %X\n", gpio_id, pCurr_func->id); + return HALMAC_RET_GET_PINMUX_ERR; + } + + *pGpio_state = HALMAC_GPIO_CFG_STATE_BUSY; + + pCurr_func = pPinmux_list; + for (i = 0; i < list_size; i++) { + value8 = HALMAC_REG_READ_8(pHalmac_adapter, pCurr_func->offset); + value8 &= ~(pCurr_func->msk); + + if (switch_func == pCurr_func->func) { + value8 |= (pCurr_func->value & pCurr_func->msk); + HALMAC_REG_WRITE_8(pHalmac_adapter, pCurr_func->offset, value8); + break; + } + + value8 |= (~pCurr_func->value & pCurr_func->msk); + HALMAC_REG_WRITE_8(pHalmac_adapter, pCurr_func->offset, value8); + + pCurr_func++; + } + + *pGpio_state = HALMAC_GPIO_CFG_STATE_IDLE; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_pinmux_record_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_GPIO_FUNC gpio_func, + IN u8 val +) +{ + switch (gpio_func) { + case HALMAC_GPIO_FUNC_WL_LED: + pHalmac_adapter->pinmux_info.wl_led = val; + break; + case HALMAC_GPIO_FUNC_SDIO_INT: + pHalmac_adapter->pinmux_info.sdio_int = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_0: + pHalmac_adapter->pinmux_info.sw_io_0 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_1: + pHalmac_adapter->pinmux_info.sw_io_1 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_2: + pHalmac_adapter->pinmux_info.sw_io_2 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_3: + pHalmac_adapter->pinmux_info.sw_io_3 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_4: + pHalmac_adapter->pinmux_info.sw_io_4 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_5: + pHalmac_adapter->pinmux_info.sw_io_5 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_6: + pHalmac_adapter->pinmux_info.sw_io_6 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_7: + pHalmac_adapter->pinmux_info.sw_io_7 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_8: + pHalmac_adapter->pinmux_info.sw_io_8 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_9: + pHalmac_adapter->pinmux_info.sw_io_9 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_10: + pHalmac_adapter->pinmux_info.sw_io_10 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_11: + pHalmac_adapter->pinmux_info.sw_io_11 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_12: + pHalmac_adapter->pinmux_info.sw_io_12 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_13: + pHalmac_adapter->pinmux_info.sw_io_13 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_14: + pHalmac_adapter->pinmux_info.sw_io_14 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_15: + pHalmac_adapter->pinmux_info.sw_io_15 = val; + break; + default: + return HALMAC_RET_GET_PINMUX_ERR; + } + + return HALMAC_RET_SUCCESS; +} + diff --git a/hal/halmac/halmac_88xx/halmac_gpio_88xx.h b/hal/halmac/halmac_88xx/halmac_gpio_88xx.h new file mode 100644 index 0000000..c2f31b0 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_gpio_88xx.h @@ -0,0 +1,86 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_GPIO_88XX_H_ +#define _HALMAC_GPIO_88XX_H_ + +#include "../halmac_api.h" +#include "../halmac_gpio_cmd.h" + +HALMAC_RET_STATUS +halmac_pinmux_wl_led_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_WLLED_MODE wlled_mode +); + +VOID +halmac_pinmux_wl_led_sw_ctrl_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 led_on +); + +VOID +halmac_pinmux_sdio_int_polarity_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 low_active +); + +HALMAC_RET_STATUS +halmac_pinmux_gpio_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 gpio_id, + IN u8 output +); + +HALMAC_RET_STATUS +halmac_pinmux_gpio_output_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 gpio_id, + IN u8 high +); + +HALMAC_RET_STATUS +halmac_pinmux_pin_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 pin_id, + OUT u8 *pHigh +); + +HALMAC_RET_STATUS +halmac_pinmux_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN const HALMAC_GPIO_PIMUX_LIST *pPinmux_list, + IN u32 list_size, + IN u32 gpio_id, + OUT u32 *pCur_func +); + +HALMAC_RET_STATUS +halmac_pinmux_switch_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN const HALMAC_GPIO_PIMUX_LIST *pPinmux_list, + IN u32 list_size, + IN u32 gpio_id, + IN HALMAC_GPIO_FUNC gpio_func +); + +HALMAC_RET_STATUS +halmac_pinmux_record_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_GPIO_FUNC gpio_func, + IN u8 val +); + +#endif/* _HALMAC_GPIO_88XX_H_ */ diff --git a/hal/halmac/halmac_bit_8197f.h b/hal/halmac/halmac_bit_8197f.h new file mode 100644 index 0000000..2661a70 --- /dev/null +++ b/hal/halmac/halmac_bit_8197f.h @@ -0,0 +1,13080 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef __INC_HALMAC_BIT_8197F_H +#define __INC_HALMAC_BIT_8197F_H + +#define CPU_OPT_WIDTH 0x1F + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_SYS_ISO_CTRL_8197F */ +#define BIT_PWC_EV12V_8197F BIT(15) +#define BIT_PWC_EV25V_8197F BIT(14) +#define BIT_PA33V_EN_8197F BIT(13) +#define BIT_PA12V_EN_8197F BIT(12) +#define BIT_UA33V_EN_8197F BIT(11) +#define BIT_UA12V_EN_8197F BIT(10) +#define BIT_ISO_RFDIO_8197F BIT(9) +#define BIT_ISO_EB2CORE_8197F BIT(8) +#define BIT_ISO_DIOE_8197F BIT(7) +#define BIT_ISO_WLPON2PP_8197F BIT(6) +#define BIT_ISO_IP2MAC_WA2PP_8197F BIT(5) +#define BIT_ISO_PD2CORE_8197F BIT(4) +#define BIT_ISO_PA2PCIE_8197F BIT(3) +#define BIT_ISO_UD2CORE_8197F BIT(2) +#define BIT_ISO_UA2USB_8197F BIT(1) +#define BIT_ISO_WD2PP_8197F BIT(0) + +/* 2 REG_SYS_FUNC_EN_8197F */ +#define BIT_FEN_MREGEN_8197F BIT(15) +#define BIT_FEN_HWPDN_8197F BIT(14) +#define BIT_EN_25_1_8197F BIT(13) +#define BIT_FEN_ELDR_8197F BIT(12) +#define BIT_FEN_DCORE_8197F BIT(11) +#define BIT_FEN_CPUEN_8197F BIT(10) +#define BIT_FEN_DIOE_8197F BIT(9) +#define BIT_FEN_PCIED_8197F BIT(8) +#define BIT_FEN_PPLL_8197F BIT(7) +#define BIT_FEN_PCIEA_8197F BIT(6) +#define BIT_FEN_DIO_PCIE_8197F BIT(5) +#define BIT_FEN_USBD_8197F BIT(4) +#define BIT_FEN_UPLL_8197F BIT(3) +#define BIT_FEN_USBA_8197F BIT(2) +#define BIT_FEN_BB_GLB_RSTN_8197F BIT(1) +#define BIT_FEN_BBRSTB_8197F BIT(0) + +/* 2 REG_SYS_PW_CTRL_8197F */ +#define BIT_SOP_EABM_8197F BIT(31) +#define BIT_SOP_ACKF_8197F BIT(30) +#define BIT_SOP_ERCK_8197F BIT(29) +#define BIT_SOP_ESWR_8197F BIT(28) +#define BIT_SOP_PWMM_8197F BIT(27) +#define BIT_SOP_EECK_8197F BIT(26) +#define BIT_SOP_EXTL_8197F BIT(24) +#define BIT_SYM_OP_RING_12M_8197F BIT(22) +#define BIT_ROP_SWPR_8197F BIT(21) +#define BIT_DIS_HW_LPLDM_8197F BIT(20) +#define BIT_OPT_SWRST_WLMCU_8197F BIT(19) +#define BIT_RDY_SYSPWR_8197F BIT(17) +#define BIT_EN_WLON_8197F BIT(16) +#define BIT_APDM_HPDN_8197F BIT(15) +#define BIT_AFSM_PCIE_SUS_EN_8197F BIT(12) +#define BIT_AFSM_WLSUS_EN_8197F BIT(11) +#define BIT_APFM_SWLPS_8197F BIT(10) +#define BIT_APFM_OFFMAC_8197F BIT(9) +#define BIT_APFN_ONMAC_8197F BIT(8) +#define BIT_CHIP_PDN_EN_8197F BIT(7) +#define BIT_RDY_MACDIS_8197F BIT(6) +#define BIT_RING_CLK_12M_EN_8197F BIT(4) +#define BIT_PFM_WOWL_8197F BIT(3) +#define BIT_PFM_LDKP_8197F BIT(2) +#define BIT_WL_HCI_ALD_8197F BIT(1) +#define BIT_PFM_LDALL_8197F BIT(0) + +/* 2 REG_SYS_CLK_CTRL_8197F */ +#define BIT_LDO_DUMMY_8197F BIT(15) +#define BIT_CPU_CLK_EN_8197F BIT(14) +#define BIT_SYMREG_CLK_EN_8197F BIT(13) +#define BIT_HCI_CLK_EN_8197F BIT(12) +#define BIT_MAC_CLK_EN_8197F BIT(11) +#define BIT_SEC_CLK_EN_8197F BIT(10) +#define BIT_PHY_SSC_RSTB_8197F BIT(9) +#define BIT_EXT_32K_EN_8197F BIT(8) +#define BIT_WL_CLK_TEST_8197F BIT(7) +#define BIT_OP_SPS_PWM_EN_8197F BIT(6) +#define BIT_LOADER_CLK_EN_8197F BIT(5) +#define BIT_MACSLP_8197F BIT(4) +#define BIT_WAKEPAD_EN_8197F BIT(3) +#define BIT_ROMD16V_EN_8197F BIT(2) +#define BIT_CKANA12M_EN_8197F BIT(1) +#define BIT_CNTD16V_EN_8197F BIT(0) + +/* 2 REG_SYS_EEPROM_CTRL_8197F */ + +#define BIT_SHIFT_VPDIDX_8197F 8 +#define BIT_MASK_VPDIDX_8197F 0xff +#define BIT_VPDIDX_8197F(x) (((x) & BIT_MASK_VPDIDX_8197F) << BIT_SHIFT_VPDIDX_8197F) +#define BITS_VPDIDX_8197F (BIT_MASK_VPDIDX_8197F << BIT_SHIFT_VPDIDX_8197F) +#define BIT_CLEAR_VPDIDX_8197F(x) ((x) & (~BITS_VPDIDX_8197F)) +#define BIT_GET_VPDIDX_8197F(x) (((x) >> BIT_SHIFT_VPDIDX_8197F) & BIT_MASK_VPDIDX_8197F) +#define BIT_SET_VPDIDX_8197F(x, v) (BIT_CLEAR_VPDIDX_8197F(x) | BIT_VPDIDX_8197F(v)) + + +#define BIT_SHIFT_EEM1_0_8197F 6 +#define BIT_MASK_EEM1_0_8197F 0x3 +#define BIT_EEM1_0_8197F(x) (((x) & BIT_MASK_EEM1_0_8197F) << BIT_SHIFT_EEM1_0_8197F) +#define BITS_EEM1_0_8197F (BIT_MASK_EEM1_0_8197F << BIT_SHIFT_EEM1_0_8197F) +#define BIT_CLEAR_EEM1_0_8197F(x) ((x) & (~BITS_EEM1_0_8197F)) +#define BIT_GET_EEM1_0_8197F(x) (((x) >> BIT_SHIFT_EEM1_0_8197F) & BIT_MASK_EEM1_0_8197F) +#define BIT_SET_EEM1_0_8197F(x, v) (BIT_CLEAR_EEM1_0_8197F(x) | BIT_EEM1_0_8197F(v)) + +#define BIT_AUTOLOAD_SUS_8197F BIT(5) +#define BIT_EERPOMSEL_8197F BIT(4) +#define BIT_EECS_V1_8197F BIT(3) +#define BIT_EESK_V1_8197F BIT(2) +#define BIT_EEDI_V1_8197F BIT(1) +#define BIT_EEDO_V1_8197F BIT(0) + +/* 2 REG_EE_VPD_8197F */ + +#define BIT_SHIFT_VPD_DATA_8197F 0 +#define BIT_MASK_VPD_DATA_8197F 0xffffffffL +#define BIT_VPD_DATA_8197F(x) (((x) & BIT_MASK_VPD_DATA_8197F) << BIT_SHIFT_VPD_DATA_8197F) +#define BITS_VPD_DATA_8197F (BIT_MASK_VPD_DATA_8197F << BIT_SHIFT_VPD_DATA_8197F) +#define BIT_CLEAR_VPD_DATA_8197F(x) ((x) & (~BITS_VPD_DATA_8197F)) +#define BIT_GET_VPD_DATA_8197F(x) (((x) >> BIT_SHIFT_VPD_DATA_8197F) & BIT_MASK_VPD_DATA_8197F) +#define BIT_SET_VPD_DATA_8197F(x, v) (BIT_CLEAR_VPD_DATA_8197F(x) | BIT_VPD_DATA_8197F(v)) + + +/* 2 REG_SYS_SWR_CTRL1_8197F */ +#define BIT_SW18_C2_BIT0_8197F BIT(31) + +#define BIT_SHIFT_SW18_C1_8197F 29 +#define BIT_MASK_SW18_C1_8197F 0x3 +#define BIT_SW18_C1_8197F(x) (((x) & BIT_MASK_SW18_C1_8197F) << BIT_SHIFT_SW18_C1_8197F) +#define BITS_SW18_C1_8197F (BIT_MASK_SW18_C1_8197F << BIT_SHIFT_SW18_C1_8197F) +#define BIT_CLEAR_SW18_C1_8197F(x) ((x) & (~BITS_SW18_C1_8197F)) +#define BIT_GET_SW18_C1_8197F(x) (((x) >> BIT_SHIFT_SW18_C1_8197F) & BIT_MASK_SW18_C1_8197F) +#define BIT_SET_SW18_C1_8197F(x, v) (BIT_CLEAR_SW18_C1_8197F(x) | BIT_SW18_C1_8197F(v)) + + +#define BIT_SHIFT_REG_FREQ_L_8197F 25 +#define BIT_MASK_REG_FREQ_L_8197F 0x7 +#define BIT_REG_FREQ_L_8197F(x) (((x) & BIT_MASK_REG_FREQ_L_8197F) << BIT_SHIFT_REG_FREQ_L_8197F) +#define BITS_REG_FREQ_L_8197F (BIT_MASK_REG_FREQ_L_8197F << BIT_SHIFT_REG_FREQ_L_8197F) +#define BIT_CLEAR_REG_FREQ_L_8197F(x) ((x) & (~BITS_REG_FREQ_L_8197F)) +#define BIT_GET_REG_FREQ_L_8197F(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8197F) & BIT_MASK_REG_FREQ_L_8197F) +#define BIT_SET_REG_FREQ_L_8197F(x, v) (BIT_CLEAR_REG_FREQ_L_8197F(x) | BIT_REG_FREQ_L_8197F(v)) + +#define BIT_REG_EN_DUTY_8197F BIT(24) + +#define BIT_SHIFT_REG_MODE_8197F 22 +#define BIT_MASK_REG_MODE_8197F 0x3 +#define BIT_REG_MODE_8197F(x) (((x) & BIT_MASK_REG_MODE_8197F) << BIT_SHIFT_REG_MODE_8197F) +#define BITS_REG_MODE_8197F (BIT_MASK_REG_MODE_8197F << BIT_SHIFT_REG_MODE_8197F) +#define BIT_CLEAR_REG_MODE_8197F(x) ((x) & (~BITS_REG_MODE_8197F)) +#define BIT_GET_REG_MODE_8197F(x) (((x) >> BIT_SHIFT_REG_MODE_8197F) & BIT_MASK_REG_MODE_8197F) +#define BIT_SET_REG_MODE_8197F(x, v) (BIT_CLEAR_REG_MODE_8197F(x) | BIT_REG_MODE_8197F(v)) + +#define BIT_REG_EN_SP_8197F BIT(21) +#define BIT_REG_AUTO_L_8197F BIT(20) +#define BIT_SW18_SELD_BIT0_8197F BIT(19) +#define BIT_SW18_POWOCP_8197F BIT(18) + +#define BIT_SHIFT_SW18_OCP_8197F 15 +#define BIT_MASK_SW18_OCP_8197F 0x7 +#define BIT_SW18_OCP_8197F(x) (((x) & BIT_MASK_SW18_OCP_8197F) << BIT_SHIFT_SW18_OCP_8197F) +#define BITS_SW18_OCP_8197F (BIT_MASK_SW18_OCP_8197F << BIT_SHIFT_SW18_OCP_8197F) +#define BIT_CLEAR_SW18_OCP_8197F(x) ((x) & (~BITS_SW18_OCP_8197F)) +#define BIT_GET_SW18_OCP_8197F(x) (((x) >> BIT_SHIFT_SW18_OCP_8197F) & BIT_MASK_SW18_OCP_8197F) +#define BIT_SET_SW18_OCP_8197F(x, v) (BIT_CLEAR_SW18_OCP_8197F(x) | BIT_SW18_OCP_8197F(v)) + + +#define BIT_SHIFT_CF_L_BIT0_TO_1_8197F 13 +#define BIT_MASK_CF_L_BIT0_TO_1_8197F 0x3 +#define BIT_CF_L_BIT0_TO_1_8197F(x) (((x) & BIT_MASK_CF_L_BIT0_TO_1_8197F) << BIT_SHIFT_CF_L_BIT0_TO_1_8197F) +#define BITS_CF_L_BIT0_TO_1_8197F (BIT_MASK_CF_L_BIT0_TO_1_8197F << BIT_SHIFT_CF_L_BIT0_TO_1_8197F) +#define BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) ((x) & (~BITS_CF_L_BIT0_TO_1_8197F)) +#define BIT_GET_CF_L_BIT0_TO_1_8197F(x) (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1_8197F) & BIT_MASK_CF_L_BIT0_TO_1_8197F) +#define BIT_SET_CF_L_BIT0_TO_1_8197F(x, v) (BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) | BIT_CF_L_BIT0_TO_1_8197F(v)) + +#define BIT_SW18_FPWM_8197F BIT(11) +#define BIT_SW18_SWEN_8197F BIT(9) +#define BIT_SW18_LDEN_8197F BIT(8) +#define BIT_MAC_ID_EN_8197F BIT(7) +#define BIT_WL_CTRL_XTAL_CADJ_8197F BIT(6) +#define BIT_AFE_BGEN_8197F BIT(0) + +/* 2 REG_SYS_SWR_CTRL2_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_SYS_SWR_CTRL3_8197F */ +#define BIT_SPS18_OCP_DIS_8197F BIT(31) + +#define BIT_SHIFT_SPS18_OCP_TH_8197F 16 +#define BIT_MASK_SPS18_OCP_TH_8197F 0x7fff +#define BIT_SPS18_OCP_TH_8197F(x) (((x) & BIT_MASK_SPS18_OCP_TH_8197F) << BIT_SHIFT_SPS18_OCP_TH_8197F) +#define BITS_SPS18_OCP_TH_8197F (BIT_MASK_SPS18_OCP_TH_8197F << BIT_SHIFT_SPS18_OCP_TH_8197F) +#define BIT_CLEAR_SPS18_OCP_TH_8197F(x) ((x) & (~BITS_SPS18_OCP_TH_8197F)) +#define BIT_GET_SPS18_OCP_TH_8197F(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8197F) & BIT_MASK_SPS18_OCP_TH_8197F) +#define BIT_SET_SPS18_OCP_TH_8197F(x, v) (BIT_CLEAR_SPS18_OCP_TH_8197F(x) | BIT_SPS18_OCP_TH_8197F(v)) + + +#define BIT_SHIFT_OCP_WINDOW_8197F 0 +#define BIT_MASK_OCP_WINDOW_8197F 0xffff +#define BIT_OCP_WINDOW_8197F(x) (((x) & BIT_MASK_OCP_WINDOW_8197F) << BIT_SHIFT_OCP_WINDOW_8197F) +#define BITS_OCP_WINDOW_8197F (BIT_MASK_OCP_WINDOW_8197F << BIT_SHIFT_OCP_WINDOW_8197F) +#define BIT_CLEAR_OCP_WINDOW_8197F(x) ((x) & (~BITS_OCP_WINDOW_8197F)) +#define BIT_GET_OCP_WINDOW_8197F(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8197F) & BIT_MASK_OCP_WINDOW_8197F) +#define BIT_SET_OCP_WINDOW_8197F(x, v) (BIT_CLEAR_OCP_WINDOW_8197F(x) | BIT_OCP_WINDOW_8197F(v)) + + +/* 2 REG_RSV_CTRL_8197F */ +#define BIT_HREG_DBG_8197F BIT(23) +#define BIT_WLMCUIOIF_8197F BIT(8) +#define BIT_LOCK_ALL_EN_8197F BIT(7) +#define BIT_R_DIS_PRST_8197F BIT(6) +#define BIT_WLOCK_1C_B6_8197F BIT(5) +#define BIT_WLOCK_40_8197F BIT(4) +#define BIT_WLOCK_08_8197F BIT(3) +#define BIT_WLOCK_04_8197F BIT(2) +#define BIT_WLOCK_00_8197F BIT(1) +#define BIT_WLOCK_ALL_8197F BIT(0) + +/* 2 REG_RF0_CTRL_8197F */ +#define BIT_RF0_SDMRSTB_8197F BIT(2) +#define BIT_RF0_RSTB_8197F BIT(1) +#define BIT_RF0_EN_8197F BIT(0) + +/* 2 REG_AFE_LDO_CTRL_8197F */ + +#define BIT_SHIFT_LPLDH12_RSV_8197F 29 +#define BIT_MASK_LPLDH12_RSV_8197F 0x7 +#define BIT_LPLDH12_RSV_8197F(x) (((x) & BIT_MASK_LPLDH12_RSV_8197F) << BIT_SHIFT_LPLDH12_RSV_8197F) +#define BITS_LPLDH12_RSV_8197F (BIT_MASK_LPLDH12_RSV_8197F << BIT_SHIFT_LPLDH12_RSV_8197F) +#define BIT_CLEAR_LPLDH12_RSV_8197F(x) ((x) & (~BITS_LPLDH12_RSV_8197F)) +#define BIT_GET_LPLDH12_RSV_8197F(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8197F) & BIT_MASK_LPLDH12_RSV_8197F) +#define BIT_SET_LPLDH12_RSV_8197F(x, v) (BIT_CLEAR_LPLDH12_RSV_8197F(x) | BIT_LPLDH12_RSV_8197F(v)) + +#define BIT_LPLDH12_SLP_8197F BIT(28) + +#define BIT_SHIFT_LPLDH12_VADJ_8197F 24 +#define BIT_MASK_LPLDH12_VADJ_8197F 0xf +#define BIT_LPLDH12_VADJ_8197F(x) (((x) & BIT_MASK_LPLDH12_VADJ_8197F) << BIT_SHIFT_LPLDH12_VADJ_8197F) +#define BITS_LPLDH12_VADJ_8197F (BIT_MASK_LPLDH12_VADJ_8197F << BIT_SHIFT_LPLDH12_VADJ_8197F) +#define BIT_CLEAR_LPLDH12_VADJ_8197F(x) ((x) & (~BITS_LPLDH12_VADJ_8197F)) +#define BIT_GET_LPLDH12_VADJ_8197F(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8197F) & BIT_MASK_LPLDH12_VADJ_8197F) +#define BIT_SET_LPLDH12_VADJ_8197F(x, v) (BIT_CLEAR_LPLDH12_VADJ_8197F(x) | BIT_LPLDH12_VADJ_8197F(v)) + +#define BIT_LDH12_EN_8197F BIT(16) +#define BIT_POW_REGU_P1_8197F BIT(10) +#define BIT_LDOV12W_EN_8197F BIT(8) +#define BIT_EX_XTAL_DRV_DIGI_8197F BIT(7) +#define BIT_EX_XTAL_DRV_USB_8197F BIT(6) +#define BIT_EX_XTAL_DRV_AFE_8197F BIT(5) +#define BIT_EX_XTAL_DRV_RF2_8197F BIT(4) +#define BIT_EX_XTAL_DRV_RF1_8197F BIT(3) +#define BIT_POW_REGU_P0_8197F BIT(2) + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_POW_PLL_LDO_8197F BIT(0) + +/* 2 REG_AFE_CTRL1_8197F */ +#define BIT_AGPIO_GPE_8197F BIT(31) + +#define BIT_SHIFT_XTAL_CAP_XI_8197F 25 +#define BIT_MASK_XTAL_CAP_XI_8197F 0x3f +#define BIT_XTAL_CAP_XI_8197F(x) (((x) & BIT_MASK_XTAL_CAP_XI_8197F) << BIT_SHIFT_XTAL_CAP_XI_8197F) +#define BITS_XTAL_CAP_XI_8197F (BIT_MASK_XTAL_CAP_XI_8197F << BIT_SHIFT_XTAL_CAP_XI_8197F) +#define BIT_CLEAR_XTAL_CAP_XI_8197F(x) ((x) & (~BITS_XTAL_CAP_XI_8197F)) +#define BIT_GET_XTAL_CAP_XI_8197F(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8197F) & BIT_MASK_XTAL_CAP_XI_8197F) +#define BIT_SET_XTAL_CAP_XI_8197F(x, v) (BIT_CLEAR_XTAL_CAP_XI_8197F(x) | BIT_XTAL_CAP_XI_8197F(v)) + + +#define BIT_SHIFT_XTAL_DRV_DIGI_8197F 23 +#define BIT_MASK_XTAL_DRV_DIGI_8197F 0x3 +#define BIT_XTAL_DRV_DIGI_8197F(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8197F) << BIT_SHIFT_XTAL_DRV_DIGI_8197F) +#define BITS_XTAL_DRV_DIGI_8197F (BIT_MASK_XTAL_DRV_DIGI_8197F << BIT_SHIFT_XTAL_DRV_DIGI_8197F) +#define BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) ((x) & (~BITS_XTAL_DRV_DIGI_8197F)) +#define BIT_GET_XTAL_DRV_DIGI_8197F(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8197F) & BIT_MASK_XTAL_DRV_DIGI_8197F) +#define BIT_SET_XTAL_DRV_DIGI_8197F(x, v) (BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) | BIT_XTAL_DRV_DIGI_8197F(v)) + +#define BIT_XTAL_DRV_USB_BIT1_8197F BIT(22) + +#define BIT_SHIFT_MAC_CLK_SEL_8197F 20 +#define BIT_MASK_MAC_CLK_SEL_8197F 0x3 +#define BIT_MAC_CLK_SEL_8197F(x) (((x) & BIT_MASK_MAC_CLK_SEL_8197F) << BIT_SHIFT_MAC_CLK_SEL_8197F) +#define BITS_MAC_CLK_SEL_8197F (BIT_MASK_MAC_CLK_SEL_8197F << BIT_SHIFT_MAC_CLK_SEL_8197F) +#define BIT_CLEAR_MAC_CLK_SEL_8197F(x) ((x) & (~BITS_MAC_CLK_SEL_8197F)) +#define BIT_GET_MAC_CLK_SEL_8197F(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8197F) & BIT_MASK_MAC_CLK_SEL_8197F) +#define BIT_SET_MAC_CLK_SEL_8197F(x, v) (BIT_CLEAR_MAC_CLK_SEL_8197F(x) | BIT_MAC_CLK_SEL_8197F(v)) + +#define BIT_XTAL_DRV_USB_BIT0_8197F BIT(19) + +#define BIT_SHIFT_XTAL_DRV_AFE_8197F 17 +#define BIT_MASK_XTAL_DRV_AFE_8197F 0x3 +#define BIT_XTAL_DRV_AFE_8197F(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8197F) << BIT_SHIFT_XTAL_DRV_AFE_8197F) +#define BITS_XTAL_DRV_AFE_8197F (BIT_MASK_XTAL_DRV_AFE_8197F << BIT_SHIFT_XTAL_DRV_AFE_8197F) +#define BIT_CLEAR_XTAL_DRV_AFE_8197F(x) ((x) & (~BITS_XTAL_DRV_AFE_8197F)) +#define BIT_GET_XTAL_DRV_AFE_8197F(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8197F) & BIT_MASK_XTAL_DRV_AFE_8197F) +#define BIT_SET_XTAL_DRV_AFE_8197F(x, v) (BIT_CLEAR_XTAL_DRV_AFE_8197F(x) | BIT_XTAL_DRV_AFE_8197F(v)) + + +#define BIT_SHIFT_XTAL_DRV_RF2_8197F 15 +#define BIT_MASK_XTAL_DRV_RF2_8197F 0x3 +#define BIT_XTAL_DRV_RF2_8197F(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8197F) << BIT_SHIFT_XTAL_DRV_RF2_8197F) +#define BITS_XTAL_DRV_RF2_8197F (BIT_MASK_XTAL_DRV_RF2_8197F << BIT_SHIFT_XTAL_DRV_RF2_8197F) +#define BIT_CLEAR_XTAL_DRV_RF2_8197F(x) ((x) & (~BITS_XTAL_DRV_RF2_8197F)) +#define BIT_GET_XTAL_DRV_RF2_8197F(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8197F) & BIT_MASK_XTAL_DRV_RF2_8197F) +#define BIT_SET_XTAL_DRV_RF2_8197F(x, v) (BIT_CLEAR_XTAL_DRV_RF2_8197F(x) | BIT_XTAL_DRV_RF2_8197F(v)) + + +#define BIT_SHIFT_XTAL_DRV_RF1_8197F 13 +#define BIT_MASK_XTAL_DRV_RF1_8197F 0x3 +#define BIT_XTAL_DRV_RF1_8197F(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8197F) << BIT_SHIFT_XTAL_DRV_RF1_8197F) +#define BITS_XTAL_DRV_RF1_8197F (BIT_MASK_XTAL_DRV_RF1_8197F << BIT_SHIFT_XTAL_DRV_RF1_8197F) +#define BIT_CLEAR_XTAL_DRV_RF1_8197F(x) ((x) & (~BITS_XTAL_DRV_RF1_8197F)) +#define BIT_GET_XTAL_DRV_RF1_8197F(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8197F) & BIT_MASK_XTAL_DRV_RF1_8197F) +#define BIT_SET_XTAL_DRV_RF1_8197F(x, v) (BIT_CLEAR_XTAL_DRV_RF1_8197F(x) | BIT_XTAL_DRV_RF1_8197F(v)) + +#define BIT_XTAL_DELAY_DIGI_8197F BIT(12) +#define BIT_XTAL_DELAY_USB_8197F BIT(11) +#define BIT_XTAL_DELAY_AFE_8197F BIT(10) +#define BIT_XTAL_LP_V1_8197F BIT(9) +#define BIT_XTAL_GM_SEP_V1_8197F BIT(8) +#define BIT_XTAL_LDO_VREF_V1_8197F BIT(7) +#define BIT_XTAL_XQSEL_RF_8197F BIT(6) +#define BIT_XTAL_XQSEL_8197F BIT(5) + +#define BIT_SHIFT_XTAL_GMN_V1_8197F 3 +#define BIT_MASK_XTAL_GMN_V1_8197F 0x3 +#define BIT_XTAL_GMN_V1_8197F(x) (((x) & BIT_MASK_XTAL_GMN_V1_8197F) << BIT_SHIFT_XTAL_GMN_V1_8197F) +#define BITS_XTAL_GMN_V1_8197F (BIT_MASK_XTAL_GMN_V1_8197F << BIT_SHIFT_XTAL_GMN_V1_8197F) +#define BIT_CLEAR_XTAL_GMN_V1_8197F(x) ((x) & (~BITS_XTAL_GMN_V1_8197F)) +#define BIT_GET_XTAL_GMN_V1_8197F(x) (((x) >> BIT_SHIFT_XTAL_GMN_V1_8197F) & BIT_MASK_XTAL_GMN_V1_8197F) +#define BIT_SET_XTAL_GMN_V1_8197F(x, v) (BIT_CLEAR_XTAL_GMN_V1_8197F(x) | BIT_XTAL_GMN_V1_8197F(v)) + + +#define BIT_SHIFT_XTAL_GMP_V1_8197F 1 +#define BIT_MASK_XTAL_GMP_V1_8197F 0x3 +#define BIT_XTAL_GMP_V1_8197F(x) (((x) & BIT_MASK_XTAL_GMP_V1_8197F) << BIT_SHIFT_XTAL_GMP_V1_8197F) +#define BITS_XTAL_GMP_V1_8197F (BIT_MASK_XTAL_GMP_V1_8197F << BIT_SHIFT_XTAL_GMP_V1_8197F) +#define BIT_CLEAR_XTAL_GMP_V1_8197F(x) ((x) & (~BITS_XTAL_GMP_V1_8197F)) +#define BIT_GET_XTAL_GMP_V1_8197F(x) (((x) >> BIT_SHIFT_XTAL_GMP_V1_8197F) & BIT_MASK_XTAL_GMP_V1_8197F) +#define BIT_SET_XTAL_GMP_V1_8197F(x, v) (BIT_CLEAR_XTAL_GMP_V1_8197F(x) | BIT_XTAL_GMP_V1_8197F(v)) + +#define BIT_XTAL_EN_8197F BIT(0) + +/* 2 REG_AFE_CTRL2_8197F */ + +#define BIT_SHIFT_RS_SET_V2_8197F 26 +#define BIT_MASK_RS_SET_V2_8197F 0x7 +#define BIT_RS_SET_V2_8197F(x) (((x) & BIT_MASK_RS_SET_V2_8197F) << BIT_SHIFT_RS_SET_V2_8197F) +#define BITS_RS_SET_V2_8197F (BIT_MASK_RS_SET_V2_8197F << BIT_SHIFT_RS_SET_V2_8197F) +#define BIT_CLEAR_RS_SET_V2_8197F(x) ((x) & (~BITS_RS_SET_V2_8197F)) +#define BIT_GET_RS_SET_V2_8197F(x) (((x) >> BIT_SHIFT_RS_SET_V2_8197F) & BIT_MASK_RS_SET_V2_8197F) +#define BIT_SET_RS_SET_V2_8197F(x, v) (BIT_CLEAR_RS_SET_V2_8197F(x) | BIT_RS_SET_V2_8197F(v)) + + +#define BIT_SHIFT_CP_BIAS_V2_8197F 18 +#define BIT_MASK_CP_BIAS_V2_8197F 0x7 +#define BIT_CP_BIAS_V2_8197F(x) (((x) & BIT_MASK_CP_BIAS_V2_8197F) << BIT_SHIFT_CP_BIAS_V2_8197F) +#define BITS_CP_BIAS_V2_8197F (BIT_MASK_CP_BIAS_V2_8197F << BIT_SHIFT_CP_BIAS_V2_8197F) +#define BIT_CLEAR_CP_BIAS_V2_8197F(x) ((x) & (~BITS_CP_BIAS_V2_8197F)) +#define BIT_GET_CP_BIAS_V2_8197F(x) (((x) >> BIT_SHIFT_CP_BIAS_V2_8197F) & BIT_MASK_CP_BIAS_V2_8197F) +#define BIT_SET_CP_BIAS_V2_8197F(x, v) (BIT_CLEAR_CP_BIAS_V2_8197F(x) | BIT_CP_BIAS_V2_8197F(v)) + +#define BIT_FREF_SEL_8197F BIT(16) + +#define BIT_SHIFT_MCCO_V2_8197F 14 +#define BIT_MASK_MCCO_V2_8197F 0x3 +#define BIT_MCCO_V2_8197F(x) (((x) & BIT_MASK_MCCO_V2_8197F) << BIT_SHIFT_MCCO_V2_8197F) +#define BITS_MCCO_V2_8197F (BIT_MASK_MCCO_V2_8197F << BIT_SHIFT_MCCO_V2_8197F) +#define BIT_CLEAR_MCCO_V2_8197F(x) ((x) & (~BITS_MCCO_V2_8197F)) +#define BIT_GET_MCCO_V2_8197F(x) (((x) >> BIT_SHIFT_MCCO_V2_8197F) & BIT_MASK_MCCO_V2_8197F) +#define BIT_SET_MCCO_V2_8197F(x, v) (BIT_CLEAR_MCCO_V2_8197F(x) | BIT_MCCO_V2_8197F(v)) + + +#define BIT_SHIFT_CK320_EN_8197F 12 +#define BIT_MASK_CK320_EN_8197F 0x3 +#define BIT_CK320_EN_8197F(x) (((x) & BIT_MASK_CK320_EN_8197F) << BIT_SHIFT_CK320_EN_8197F) +#define BITS_CK320_EN_8197F (BIT_MASK_CK320_EN_8197F << BIT_SHIFT_CK320_EN_8197F) +#define BIT_CLEAR_CK320_EN_8197F(x) ((x) & (~BITS_CK320_EN_8197F)) +#define BIT_GET_CK320_EN_8197F(x) (((x) >> BIT_SHIFT_CK320_EN_8197F) & BIT_MASK_CK320_EN_8197F) +#define BIT_SET_CK320_EN_8197F(x, v) (BIT_CLEAR_CK320_EN_8197F(x) | BIT_CK320_EN_8197F(v)) + +#define BIT_AGPIO_GPO_8197F BIT(9) + +#define BIT_SHIFT_AGPIO_DRV_8197F 7 +#define BIT_MASK_AGPIO_DRV_8197F 0x3 +#define BIT_AGPIO_DRV_8197F(x) (((x) & BIT_MASK_AGPIO_DRV_8197F) << BIT_SHIFT_AGPIO_DRV_8197F) +#define BITS_AGPIO_DRV_8197F (BIT_MASK_AGPIO_DRV_8197F << BIT_SHIFT_AGPIO_DRV_8197F) +#define BIT_CLEAR_AGPIO_DRV_8197F(x) ((x) & (~BITS_AGPIO_DRV_8197F)) +#define BIT_GET_AGPIO_DRV_8197F(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8197F) & BIT_MASK_AGPIO_DRV_8197F) +#define BIT_SET_AGPIO_DRV_8197F(x, v) (BIT_CLEAR_AGPIO_DRV_8197F(x) | BIT_AGPIO_DRV_8197F(v)) + + +#define BIT_SHIFT_XTAL_CAP_XO_8197F 1 +#define BIT_MASK_XTAL_CAP_XO_8197F 0x3f +#define BIT_XTAL_CAP_XO_8197F(x) (((x) & BIT_MASK_XTAL_CAP_XO_8197F) << BIT_SHIFT_XTAL_CAP_XO_8197F) +#define BITS_XTAL_CAP_XO_8197F (BIT_MASK_XTAL_CAP_XO_8197F << BIT_SHIFT_XTAL_CAP_XO_8197F) +#define BIT_CLEAR_XTAL_CAP_XO_8197F(x) ((x) & (~BITS_XTAL_CAP_XO_8197F)) +#define BIT_GET_XTAL_CAP_XO_8197F(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8197F) & BIT_MASK_XTAL_CAP_XO_8197F) +#define BIT_SET_XTAL_CAP_XO_8197F(x, v) (BIT_CLEAR_XTAL_CAP_XO_8197F(x) | BIT_XTAL_CAP_XO_8197F(v)) + +#define BIT_POW_PLL_8197F BIT(0) + +/* 2 REG_AFE_CTRL3_8197F */ + +#define BIT_SHIFT_PS_V2_8197F 7 +#define BIT_MASK_PS_V2_8197F 0x7 +#define BIT_PS_V2_8197F(x) (((x) & BIT_MASK_PS_V2_8197F) << BIT_SHIFT_PS_V2_8197F) +#define BITS_PS_V2_8197F (BIT_MASK_PS_V2_8197F << BIT_SHIFT_PS_V2_8197F) +#define BIT_CLEAR_PS_V2_8197F(x) ((x) & (~BITS_PS_V2_8197F)) +#define BIT_GET_PS_V2_8197F(x) (((x) >> BIT_SHIFT_PS_V2_8197F) & BIT_MASK_PS_V2_8197F) +#define BIT_SET_PS_V2_8197F(x, v) (BIT_CLEAR_PS_V2_8197F(x) | BIT_PS_V2_8197F(v)) + +#define BIT_PSEN_8197F BIT(6) +#define BIT_DOGENB_8197F BIT(5) + +/* 2 REG_EFUSE_CTRL_8197F */ +#define BIT_EF_FLAG_8197F BIT(31) + +#define BIT_SHIFT_EF_PGPD_8197F 28 +#define BIT_MASK_EF_PGPD_8197F 0x7 +#define BIT_EF_PGPD_8197F(x) (((x) & BIT_MASK_EF_PGPD_8197F) << BIT_SHIFT_EF_PGPD_8197F) +#define BITS_EF_PGPD_8197F (BIT_MASK_EF_PGPD_8197F << BIT_SHIFT_EF_PGPD_8197F) +#define BIT_CLEAR_EF_PGPD_8197F(x) ((x) & (~BITS_EF_PGPD_8197F)) +#define BIT_GET_EF_PGPD_8197F(x) (((x) >> BIT_SHIFT_EF_PGPD_8197F) & BIT_MASK_EF_PGPD_8197F) +#define BIT_SET_EF_PGPD_8197F(x, v) (BIT_CLEAR_EF_PGPD_8197F(x) | BIT_EF_PGPD_8197F(v)) + + +#define BIT_SHIFT_EF_RDT_8197F 24 +#define BIT_MASK_EF_RDT_8197F 0xf +#define BIT_EF_RDT_8197F(x) (((x) & BIT_MASK_EF_RDT_8197F) << BIT_SHIFT_EF_RDT_8197F) +#define BITS_EF_RDT_8197F (BIT_MASK_EF_RDT_8197F << BIT_SHIFT_EF_RDT_8197F) +#define BIT_CLEAR_EF_RDT_8197F(x) ((x) & (~BITS_EF_RDT_8197F)) +#define BIT_GET_EF_RDT_8197F(x) (((x) >> BIT_SHIFT_EF_RDT_8197F) & BIT_MASK_EF_RDT_8197F) +#define BIT_SET_EF_RDT_8197F(x, v) (BIT_CLEAR_EF_RDT_8197F(x) | BIT_EF_RDT_8197F(v)) + + +#define BIT_SHIFT_EF_PGTS_8197F 20 +#define BIT_MASK_EF_PGTS_8197F 0xf +#define BIT_EF_PGTS_8197F(x) (((x) & BIT_MASK_EF_PGTS_8197F) << BIT_SHIFT_EF_PGTS_8197F) +#define BITS_EF_PGTS_8197F (BIT_MASK_EF_PGTS_8197F << BIT_SHIFT_EF_PGTS_8197F) +#define BIT_CLEAR_EF_PGTS_8197F(x) ((x) & (~BITS_EF_PGTS_8197F)) +#define BIT_GET_EF_PGTS_8197F(x) (((x) >> BIT_SHIFT_EF_PGTS_8197F) & BIT_MASK_EF_PGTS_8197F) +#define BIT_SET_EF_PGTS_8197F(x, v) (BIT_CLEAR_EF_PGTS_8197F(x) | BIT_EF_PGTS_8197F(v)) + +#define BIT_EF_PDWN_8197F BIT(19) +#define BIT_EF_ALDEN_8197F BIT(18) + +#define BIT_SHIFT_EF_ADDR_8197F 8 +#define BIT_MASK_EF_ADDR_8197F 0x3ff +#define BIT_EF_ADDR_8197F(x) (((x) & BIT_MASK_EF_ADDR_8197F) << BIT_SHIFT_EF_ADDR_8197F) +#define BITS_EF_ADDR_8197F (BIT_MASK_EF_ADDR_8197F << BIT_SHIFT_EF_ADDR_8197F) +#define BIT_CLEAR_EF_ADDR_8197F(x) ((x) & (~BITS_EF_ADDR_8197F)) +#define BIT_GET_EF_ADDR_8197F(x) (((x) >> BIT_SHIFT_EF_ADDR_8197F) & BIT_MASK_EF_ADDR_8197F) +#define BIT_SET_EF_ADDR_8197F(x, v) (BIT_CLEAR_EF_ADDR_8197F(x) | BIT_EF_ADDR_8197F(v)) + + +#define BIT_SHIFT_EF_DATA_8197F 0 +#define BIT_MASK_EF_DATA_8197F 0xff +#define BIT_EF_DATA_8197F(x) (((x) & BIT_MASK_EF_DATA_8197F) << BIT_SHIFT_EF_DATA_8197F) +#define BITS_EF_DATA_8197F (BIT_MASK_EF_DATA_8197F << BIT_SHIFT_EF_DATA_8197F) +#define BIT_CLEAR_EF_DATA_8197F(x) ((x) & (~BITS_EF_DATA_8197F)) +#define BIT_GET_EF_DATA_8197F(x) (((x) >> BIT_SHIFT_EF_DATA_8197F) & BIT_MASK_EF_DATA_8197F) +#define BIT_SET_EF_DATA_8197F(x, v) (BIT_CLEAR_EF_DATA_8197F(x) | BIT_EF_DATA_8197F(v)) + + +/* 2 REG_LDO_EFUSE_CTRL_8197F */ +#define BIT_LDOE25_EN_8197F BIT(31) + +#define BIT_SHIFT_LDOE25_V12ADJ_L_8197F 27 +#define BIT_MASK_LDOE25_V12ADJ_L_8197F 0xf +#define BIT_LDOE25_V12ADJ_L_8197F(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8197F) << BIT_SHIFT_LDOE25_V12ADJ_L_8197F) +#define BITS_LDOE25_V12ADJ_L_8197F (BIT_MASK_LDOE25_V12ADJ_L_8197F << BIT_SHIFT_LDOE25_V12ADJ_L_8197F) +#define BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8197F)) +#define BIT_GET_LDOE25_V12ADJ_L_8197F(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8197F) & BIT_MASK_LDOE25_V12ADJ_L_8197F) +#define BIT_SET_LDOE25_V12ADJ_L_8197F(x, v) (BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) | BIT_LDOE25_V12ADJ_L_8197F(v)) + + +#define BIT_SHIFT_EF_SCAN_START_V1_8197F 16 +#define BIT_MASK_EF_SCAN_START_V1_8197F 0x3ff +#define BIT_EF_SCAN_START_V1_8197F(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8197F) << BIT_SHIFT_EF_SCAN_START_V1_8197F) +#define BITS_EF_SCAN_START_V1_8197F (BIT_MASK_EF_SCAN_START_V1_8197F << BIT_SHIFT_EF_SCAN_START_V1_8197F) +#define BIT_CLEAR_EF_SCAN_START_V1_8197F(x) ((x) & (~BITS_EF_SCAN_START_V1_8197F)) +#define BIT_GET_EF_SCAN_START_V1_8197F(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8197F) & BIT_MASK_EF_SCAN_START_V1_8197F) +#define BIT_SET_EF_SCAN_START_V1_8197F(x, v) (BIT_CLEAR_EF_SCAN_START_V1_8197F(x) | BIT_EF_SCAN_START_V1_8197F(v)) + + +#define BIT_SHIFT_EF_SCAN_END_8197F 12 +#define BIT_MASK_EF_SCAN_END_8197F 0xf +#define BIT_EF_SCAN_END_8197F(x) (((x) & BIT_MASK_EF_SCAN_END_8197F) << BIT_SHIFT_EF_SCAN_END_8197F) +#define BITS_EF_SCAN_END_8197F (BIT_MASK_EF_SCAN_END_8197F << BIT_SHIFT_EF_SCAN_END_8197F) +#define BIT_CLEAR_EF_SCAN_END_8197F(x) ((x) & (~BITS_EF_SCAN_END_8197F)) +#define BIT_GET_EF_SCAN_END_8197F(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8197F) & BIT_MASK_EF_SCAN_END_8197F) +#define BIT_SET_EF_SCAN_END_8197F(x, v) (BIT_CLEAR_EF_SCAN_END_8197F(x) | BIT_EF_SCAN_END_8197F(v)) + + +#define BIT_SHIFT_EF_CELL_SEL_8197F 8 +#define BIT_MASK_EF_CELL_SEL_8197F 0x3 +#define BIT_EF_CELL_SEL_8197F(x) (((x) & BIT_MASK_EF_CELL_SEL_8197F) << BIT_SHIFT_EF_CELL_SEL_8197F) +#define BITS_EF_CELL_SEL_8197F (BIT_MASK_EF_CELL_SEL_8197F << BIT_SHIFT_EF_CELL_SEL_8197F) +#define BIT_CLEAR_EF_CELL_SEL_8197F(x) ((x) & (~BITS_EF_CELL_SEL_8197F)) +#define BIT_GET_EF_CELL_SEL_8197F(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8197F) & BIT_MASK_EF_CELL_SEL_8197F) +#define BIT_SET_EF_CELL_SEL_8197F(x, v) (BIT_CLEAR_EF_CELL_SEL_8197F(x) | BIT_EF_CELL_SEL_8197F(v)) + +#define BIT_EF_TRPT_8197F BIT(7) + +#define BIT_SHIFT_EF_TTHD_8197F 0 +#define BIT_MASK_EF_TTHD_8197F 0x7f +#define BIT_EF_TTHD_8197F(x) (((x) & BIT_MASK_EF_TTHD_8197F) << BIT_SHIFT_EF_TTHD_8197F) +#define BITS_EF_TTHD_8197F (BIT_MASK_EF_TTHD_8197F << BIT_SHIFT_EF_TTHD_8197F) +#define BIT_CLEAR_EF_TTHD_8197F(x) ((x) & (~BITS_EF_TTHD_8197F)) +#define BIT_GET_EF_TTHD_8197F(x) (((x) >> BIT_SHIFT_EF_TTHD_8197F) & BIT_MASK_EF_TTHD_8197F) +#define BIT_SET_EF_TTHD_8197F(x, v) (BIT_CLEAR_EF_TTHD_8197F(x) | BIT_EF_TTHD_8197F(v)) + + +/* 2 REG_PWR_OPTION_CTRL_8197F */ + +#define BIT_SHIFT_DBG_SEL_V1_8197F 16 +#define BIT_MASK_DBG_SEL_V1_8197F 0xff +#define BIT_DBG_SEL_V1_8197F(x) (((x) & BIT_MASK_DBG_SEL_V1_8197F) << BIT_SHIFT_DBG_SEL_V1_8197F) +#define BITS_DBG_SEL_V1_8197F (BIT_MASK_DBG_SEL_V1_8197F << BIT_SHIFT_DBG_SEL_V1_8197F) +#define BIT_CLEAR_DBG_SEL_V1_8197F(x) ((x) & (~BITS_DBG_SEL_V1_8197F)) +#define BIT_GET_DBG_SEL_V1_8197F(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8197F) & BIT_MASK_DBG_SEL_V1_8197F) +#define BIT_SET_DBG_SEL_V1_8197F(x, v) (BIT_CLEAR_DBG_SEL_V1_8197F(x) | BIT_DBG_SEL_V1_8197F(v)) + + +#define BIT_SHIFT_DBG_SEL_BYTE_8197F 14 +#define BIT_MASK_DBG_SEL_BYTE_8197F 0x3 +#define BIT_DBG_SEL_BYTE_8197F(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8197F) << BIT_SHIFT_DBG_SEL_BYTE_8197F) +#define BITS_DBG_SEL_BYTE_8197F (BIT_MASK_DBG_SEL_BYTE_8197F << BIT_SHIFT_DBG_SEL_BYTE_8197F) +#define BIT_CLEAR_DBG_SEL_BYTE_8197F(x) ((x) & (~BITS_DBG_SEL_BYTE_8197F)) +#define BIT_GET_DBG_SEL_BYTE_8197F(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8197F) & BIT_MASK_DBG_SEL_BYTE_8197F) +#define BIT_SET_DBG_SEL_BYTE_8197F(x, v) (BIT_CLEAR_DBG_SEL_BYTE_8197F(x) | BIT_DBG_SEL_BYTE_8197F(v)) + + +#define BIT_SHIFT_STD_L1_V1_8197F 12 +#define BIT_MASK_STD_L1_V1_8197F 0x3 +#define BIT_STD_L1_V1_8197F(x) (((x) & BIT_MASK_STD_L1_V1_8197F) << BIT_SHIFT_STD_L1_V1_8197F) +#define BITS_STD_L1_V1_8197F (BIT_MASK_STD_L1_V1_8197F << BIT_SHIFT_STD_L1_V1_8197F) +#define BIT_CLEAR_STD_L1_V1_8197F(x) ((x) & (~BITS_STD_L1_V1_8197F)) +#define BIT_GET_STD_L1_V1_8197F(x) (((x) >> BIT_SHIFT_STD_L1_V1_8197F) & BIT_MASK_STD_L1_V1_8197F) +#define BIT_SET_STD_L1_V1_8197F(x, v) (BIT_CLEAR_STD_L1_V1_8197F(x) | BIT_STD_L1_V1_8197F(v)) + +#define BIT_SYSON_DBG_PAD_E2_8197F BIT(11) +#define BIT_SYSON_LED_PAD_E2_8197F BIT(10) +#define BIT_SYSON_GPEE_PAD_E2_8197F BIT(9) +#define BIT_SYSON_PCI_PAD_E2_8197F BIT(8) +#define BIT_AUTO_SW_LDO_VOL_EN_8197F BIT(7) + +#define BIT_SHIFT_SYSON_SPS0WWV_WT_8197F 4 +#define BIT_MASK_SYSON_SPS0WWV_WT_8197F 0x3 +#define BIT_SYSON_SPS0WWV_WT_8197F(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8197F) << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) +#define BITS_SYSON_SPS0WWV_WT_8197F (BIT_MASK_SYSON_SPS0WWV_WT_8197F << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) +#define BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) ((x) & (~BITS_SYSON_SPS0WWV_WT_8197F)) +#define BIT_GET_SYSON_SPS0WWV_WT_8197F(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) & BIT_MASK_SYSON_SPS0WWV_WT_8197F) +#define BIT_SET_SYSON_SPS0WWV_WT_8197F(x, v) (BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) | BIT_SYSON_SPS0WWV_WT_8197F(v)) + + +#define BIT_SHIFT_SYSON_SPS0LDO_WT_8197F 2 +#define BIT_MASK_SYSON_SPS0LDO_WT_8197F 0x3 +#define BIT_SYSON_SPS0LDO_WT_8197F(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8197F) << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) +#define BITS_SYSON_SPS0LDO_WT_8197F (BIT_MASK_SYSON_SPS0LDO_WT_8197F << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) +#define BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) ((x) & (~BITS_SYSON_SPS0LDO_WT_8197F)) +#define BIT_GET_SYSON_SPS0LDO_WT_8197F(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) & BIT_MASK_SYSON_SPS0LDO_WT_8197F) +#define BIT_SET_SYSON_SPS0LDO_WT_8197F(x, v) (BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) | BIT_SYSON_SPS0LDO_WT_8197F(v)) + + +#define BIT_SHIFT_SYSON_RCLK_SCALE_8197F 0 +#define BIT_MASK_SYSON_RCLK_SCALE_8197F 0x3 +#define BIT_SYSON_RCLK_SCALE_8197F(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8197F) << BIT_SHIFT_SYSON_RCLK_SCALE_8197F) +#define BITS_SYSON_RCLK_SCALE_8197F (BIT_MASK_SYSON_RCLK_SCALE_8197F << BIT_SHIFT_SYSON_RCLK_SCALE_8197F) +#define BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) ((x) & (~BITS_SYSON_RCLK_SCALE_8197F)) +#define BIT_GET_SYSON_RCLK_SCALE_8197F(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8197F) & BIT_MASK_SYSON_RCLK_SCALE_8197F) +#define BIT_SET_SYSON_RCLK_SCALE_8197F(x, v) (BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) | BIT_SYSON_RCLK_SCALE_8197F(v)) + + +/* 2 REG_CAL_TIMER_8197F */ + +#define BIT_SHIFT_MATCH_CNT_8197F 8 +#define BIT_MASK_MATCH_CNT_8197F 0xff +#define BIT_MATCH_CNT_8197F(x) (((x) & BIT_MASK_MATCH_CNT_8197F) << BIT_SHIFT_MATCH_CNT_8197F) +#define BITS_MATCH_CNT_8197F (BIT_MASK_MATCH_CNT_8197F << BIT_SHIFT_MATCH_CNT_8197F) +#define BIT_CLEAR_MATCH_CNT_8197F(x) ((x) & (~BITS_MATCH_CNT_8197F)) +#define BIT_GET_MATCH_CNT_8197F(x) (((x) >> BIT_SHIFT_MATCH_CNT_8197F) & BIT_MASK_MATCH_CNT_8197F) +#define BIT_SET_MATCH_CNT_8197F(x, v) (BIT_CLEAR_MATCH_CNT_8197F(x) | BIT_MATCH_CNT_8197F(v)) + + +#define BIT_SHIFT_CAL_SCAL_8197F 0 +#define BIT_MASK_CAL_SCAL_8197F 0xff +#define BIT_CAL_SCAL_8197F(x) (((x) & BIT_MASK_CAL_SCAL_8197F) << BIT_SHIFT_CAL_SCAL_8197F) +#define BITS_CAL_SCAL_8197F (BIT_MASK_CAL_SCAL_8197F << BIT_SHIFT_CAL_SCAL_8197F) +#define BIT_CLEAR_CAL_SCAL_8197F(x) ((x) & (~BITS_CAL_SCAL_8197F)) +#define BIT_GET_CAL_SCAL_8197F(x) (((x) >> BIT_SHIFT_CAL_SCAL_8197F) & BIT_MASK_CAL_SCAL_8197F) +#define BIT_SET_CAL_SCAL_8197F(x, v) (BIT_CLEAR_CAL_SCAL_8197F(x) | BIT_CAL_SCAL_8197F(v)) + + +/* 2 REG_ACLK_MON_8197F */ + +#define BIT_SHIFT_RCLK_MON_8197F 5 +#define BIT_MASK_RCLK_MON_8197F 0x7ff +#define BIT_RCLK_MON_8197F(x) (((x) & BIT_MASK_RCLK_MON_8197F) << BIT_SHIFT_RCLK_MON_8197F) +#define BITS_RCLK_MON_8197F (BIT_MASK_RCLK_MON_8197F << BIT_SHIFT_RCLK_MON_8197F) +#define BIT_CLEAR_RCLK_MON_8197F(x) ((x) & (~BITS_RCLK_MON_8197F)) +#define BIT_GET_RCLK_MON_8197F(x) (((x) >> BIT_SHIFT_RCLK_MON_8197F) & BIT_MASK_RCLK_MON_8197F) +#define BIT_SET_RCLK_MON_8197F(x, v) (BIT_CLEAR_RCLK_MON_8197F(x) | BIT_RCLK_MON_8197F(v)) + +#define BIT_CAL_EN_8197F BIT(4) + +#define BIT_SHIFT_DPSTU_8197F 2 +#define BIT_MASK_DPSTU_8197F 0x3 +#define BIT_DPSTU_8197F(x) (((x) & BIT_MASK_DPSTU_8197F) << BIT_SHIFT_DPSTU_8197F) +#define BITS_DPSTU_8197F (BIT_MASK_DPSTU_8197F << BIT_SHIFT_DPSTU_8197F) +#define BIT_CLEAR_DPSTU_8197F(x) ((x) & (~BITS_DPSTU_8197F)) +#define BIT_GET_DPSTU_8197F(x) (((x) >> BIT_SHIFT_DPSTU_8197F) & BIT_MASK_DPSTU_8197F) +#define BIT_SET_DPSTU_8197F(x, v) (BIT_CLEAR_DPSTU_8197F(x) | BIT_DPSTU_8197F(v)) + +#define BIT_SUS_16X_8197F BIT(1) + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_GPIO_MUXCFG_8197F */ +#define BIT_SIC_LOWEST_PRIORITY_8197F BIT(28) + +#define BIT_SHIFT_PIN_USECASE_8197F 24 +#define BIT_MASK_PIN_USECASE_8197F 0xf +#define BIT_PIN_USECASE_8197F(x) (((x) & BIT_MASK_PIN_USECASE_8197F) << BIT_SHIFT_PIN_USECASE_8197F) +#define BITS_PIN_USECASE_8197F (BIT_MASK_PIN_USECASE_8197F << BIT_SHIFT_PIN_USECASE_8197F) +#define BIT_CLEAR_PIN_USECASE_8197F(x) ((x) & (~BITS_PIN_USECASE_8197F)) +#define BIT_GET_PIN_USECASE_8197F(x) (((x) >> BIT_SHIFT_PIN_USECASE_8197F) & BIT_MASK_PIN_USECASE_8197F) +#define BIT_SET_PIN_USECASE_8197F(x, v) (BIT_CLEAR_PIN_USECASE_8197F(x) | BIT_PIN_USECASE_8197F(v)) + +#define BIT_FSPI_EN_8197F BIT(19) +#define BIT_WL_RTS_EXT_32K_SEL_8197F BIT(18) +#define BIT_WLGP_SPI_EN_8197F BIT(16) +#define BIT_SIC_LBK_8197F BIT(15) +#define BIT_ENHTP_8197F BIT(14) +#define BIT_WLPHY_DBG_EN_8197F BIT(13) +#define BIT_ENSIC_8197F BIT(12) +#define BIT_SIC_SWRST_8197F BIT(11) +#define BIT_PO_WIFI_PTA_PINS_8197F BIT(10) +#define BIT_BTCOEX_MBOX_EN_8197F BIT(9) +#define BIT_ENUART_8197F BIT(8) + +#define BIT_SHIFT_BTMODE_8197F 6 +#define BIT_MASK_BTMODE_8197F 0x3 +#define BIT_BTMODE_8197F(x) (((x) & BIT_MASK_BTMODE_8197F) << BIT_SHIFT_BTMODE_8197F) +#define BITS_BTMODE_8197F (BIT_MASK_BTMODE_8197F << BIT_SHIFT_BTMODE_8197F) +#define BIT_CLEAR_BTMODE_8197F(x) ((x) & (~BITS_BTMODE_8197F)) +#define BIT_GET_BTMODE_8197F(x) (((x) >> BIT_SHIFT_BTMODE_8197F) & BIT_MASK_BTMODE_8197F) +#define BIT_SET_BTMODE_8197F(x, v) (BIT_CLEAR_BTMODE_8197F(x) | BIT_BTMODE_8197F(v)) + +#define BIT_ENBT_8197F BIT(5) +#define BIT_EROM_EN_8197F BIT(4) +#define BIT_WLRFE_6_7_EN_8197F BIT(3) +#define BIT_WLRFE_4_5_EN_8197F BIT(2) + +#define BIT_SHIFT_GPIOSEL_8197F 0 +#define BIT_MASK_GPIOSEL_8197F 0x3 +#define BIT_GPIOSEL_8197F(x) (((x) & BIT_MASK_GPIOSEL_8197F) << BIT_SHIFT_GPIOSEL_8197F) +#define BITS_GPIOSEL_8197F (BIT_MASK_GPIOSEL_8197F << BIT_SHIFT_GPIOSEL_8197F) +#define BIT_CLEAR_GPIOSEL_8197F(x) ((x) & (~BITS_GPIOSEL_8197F)) +#define BIT_GET_GPIOSEL_8197F(x) (((x) >> BIT_SHIFT_GPIOSEL_8197F) & BIT_MASK_GPIOSEL_8197F) +#define BIT_SET_GPIOSEL_8197F(x, v) (BIT_CLEAR_GPIOSEL_8197F(x) | BIT_GPIOSEL_8197F(v)) + + +/* 2 REG_GPIO_PIN_CTRL_8197F */ + +#define BIT_SHIFT_GPIO_MOD_7_TO_0_8197F 24 +#define BIT_MASK_GPIO_MOD_7_TO_0_8197F 0xff +#define BIT_GPIO_MOD_7_TO_0_8197F(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8197F) << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) +#define BITS_GPIO_MOD_7_TO_0_8197F (BIT_MASK_GPIO_MOD_7_TO_0_8197F << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) +#define BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8197F)) +#define BIT_GET_GPIO_MOD_7_TO_0_8197F(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) & BIT_MASK_GPIO_MOD_7_TO_0_8197F) +#define BIT_SET_GPIO_MOD_7_TO_0_8197F(x, v) (BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) | BIT_GPIO_MOD_7_TO_0_8197F(v)) + + +#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F 16 +#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F 0xff +#define BIT_GPIO_IO_SEL_7_TO_0_8197F(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) +#define BITS_GPIO_IO_SEL_7_TO_0_8197F (BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8197F)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8197F(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F) +#define BIT_SET_GPIO_IO_SEL_7_TO_0_8197F(x, v) (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) | BIT_GPIO_IO_SEL_7_TO_0_8197F(v)) + + +#define BIT_SHIFT_GPIO_OUT_7_TO_0_8197F 8 +#define BIT_MASK_GPIO_OUT_7_TO_0_8197F 0xff +#define BIT_GPIO_OUT_7_TO_0_8197F(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8197F) << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) +#define BITS_GPIO_OUT_7_TO_0_8197F (BIT_MASK_GPIO_OUT_7_TO_0_8197F << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) +#define BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8197F)) +#define BIT_GET_GPIO_OUT_7_TO_0_8197F(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) & BIT_MASK_GPIO_OUT_7_TO_0_8197F) +#define BIT_SET_GPIO_OUT_7_TO_0_8197F(x, v) (BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) | BIT_GPIO_OUT_7_TO_0_8197F(v)) + + +#define BIT_SHIFT_GPIO_IN_7_TO_0_8197F 0 +#define BIT_MASK_GPIO_IN_7_TO_0_8197F 0xff +#define BIT_GPIO_IN_7_TO_0_8197F(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8197F) << BIT_SHIFT_GPIO_IN_7_TO_0_8197F) +#define BITS_GPIO_IN_7_TO_0_8197F (BIT_MASK_GPIO_IN_7_TO_0_8197F << BIT_SHIFT_GPIO_IN_7_TO_0_8197F) +#define BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8197F)) +#define BIT_GET_GPIO_IN_7_TO_0_8197F(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8197F) & BIT_MASK_GPIO_IN_7_TO_0_8197F) +#define BIT_SET_GPIO_IN_7_TO_0_8197F(x, v) (BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) | BIT_GPIO_IN_7_TO_0_8197F(v)) + + +/* 2 REG_GPIO_INTM_8197F */ + +#define BIT_SHIFT_MUXDBG_SEL_8197F 30 +#define BIT_MASK_MUXDBG_SEL_8197F 0x3 +#define BIT_MUXDBG_SEL_8197F(x) (((x) & BIT_MASK_MUXDBG_SEL_8197F) << BIT_SHIFT_MUXDBG_SEL_8197F) +#define BITS_MUXDBG_SEL_8197F (BIT_MASK_MUXDBG_SEL_8197F << BIT_SHIFT_MUXDBG_SEL_8197F) +#define BIT_CLEAR_MUXDBG_SEL_8197F(x) ((x) & (~BITS_MUXDBG_SEL_8197F)) +#define BIT_GET_MUXDBG_SEL_8197F(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8197F) & BIT_MASK_MUXDBG_SEL_8197F) +#define BIT_SET_MUXDBG_SEL_8197F(x, v) (BIT_CLEAR_MUXDBG_SEL_8197F(x) | BIT_MUXDBG_SEL_8197F(v)) + +#define BIT_EXTWOL_SEL_8197F BIT(17) +#define BIT_EXTWOL_EN_8197F BIT(16) +#define BIT_GPIOF_INT_MD_8197F BIT(15) +#define BIT_GPIOE_INT_MD_8197F BIT(14) +#define BIT_GPIOD_INT_MD_8197F BIT(13) +#define BIT_GPIOC_INT_MD_8197F BIT(12) +#define BIT_GPIOB_INT_MD_8197F BIT(11) +#define BIT_GPIOA_INT_MD_8197F BIT(10) +#define BIT_GPIO9_INT_MD_8197F BIT(9) +#define BIT_GPIO8_INT_MD_8197F BIT(8) +#define BIT_GPIO7_INT_MD_8197F BIT(7) +#define BIT_GPIO6_INT_MD_8197F BIT(6) +#define BIT_GPIO5_INT_MD_8197F BIT(5) +#define BIT_GPIO4_INT_MD_8197F BIT(4) +#define BIT_GPIO3_INT_MD_8197F BIT(3) +#define BIT_GPIO2_INT_MD_8197F BIT(2) +#define BIT_GPIO1_INT_MD_8197F BIT(1) +#define BIT_GPIO0_INT_MD_8197F BIT(0) + +/* 2 REG_LED_CFG_8197F */ +#define BIT_LNAON_SEL_EN_8197F BIT(26) +#define BIT_PAPE_SEL_EN_8197F BIT(25) +#define BIT_DPDT_WLBT_SEL_8197F BIT(24) +#define BIT_DPDT_SEL_EN_8197F BIT(23) +#define BIT_LED2DIS_V1_8197F BIT(22) +#define BIT_LED2EN_8197F BIT(21) +#define BIT_LED2PL_8197F BIT(20) +#define BIT_LED2SV_8197F BIT(19) + +#define BIT_SHIFT_LED2CM_8197F 16 +#define BIT_MASK_LED2CM_8197F 0x7 +#define BIT_LED2CM_8197F(x) (((x) & BIT_MASK_LED2CM_8197F) << BIT_SHIFT_LED2CM_8197F) +#define BITS_LED2CM_8197F (BIT_MASK_LED2CM_8197F << BIT_SHIFT_LED2CM_8197F) +#define BIT_CLEAR_LED2CM_8197F(x) ((x) & (~BITS_LED2CM_8197F)) +#define BIT_GET_LED2CM_8197F(x) (((x) >> BIT_SHIFT_LED2CM_8197F) & BIT_MASK_LED2CM_8197F) +#define BIT_SET_LED2CM_8197F(x, v) (BIT_CLEAR_LED2CM_8197F(x) | BIT_LED2CM_8197F(v)) + +#define BIT_LED1DIS_8197F BIT(15) +#define BIT_LED1PL_8197F BIT(12) +#define BIT_LED1SV_8197F BIT(11) + +#define BIT_SHIFT_LED1CM_8197F 8 +#define BIT_MASK_LED1CM_8197F 0x7 +#define BIT_LED1CM_8197F(x) (((x) & BIT_MASK_LED1CM_8197F) << BIT_SHIFT_LED1CM_8197F) +#define BITS_LED1CM_8197F (BIT_MASK_LED1CM_8197F << BIT_SHIFT_LED1CM_8197F) +#define BIT_CLEAR_LED1CM_8197F(x) ((x) & (~BITS_LED1CM_8197F)) +#define BIT_GET_LED1CM_8197F(x) (((x) >> BIT_SHIFT_LED1CM_8197F) & BIT_MASK_LED1CM_8197F) +#define BIT_SET_LED1CM_8197F(x, v) (BIT_CLEAR_LED1CM_8197F(x) | BIT_LED1CM_8197F(v)) + +#define BIT_LED0DIS_8197F BIT(7) + +#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F 5 +#define BIT_MASK_AFE_LDO_SWR_CHECK_8197F 0x3 +#define BIT_AFE_LDO_SWR_CHECK_8197F(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8197F) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) +#define BITS_AFE_LDO_SWR_CHECK_8197F (BIT_MASK_AFE_LDO_SWR_CHECK_8197F << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) ((x) & (~BITS_AFE_LDO_SWR_CHECK_8197F)) +#define BIT_GET_AFE_LDO_SWR_CHECK_8197F(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) & BIT_MASK_AFE_LDO_SWR_CHECK_8197F) +#define BIT_SET_AFE_LDO_SWR_CHECK_8197F(x, v) (BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) | BIT_AFE_LDO_SWR_CHECK_8197F(v)) + +#define BIT_LED0PL_8197F BIT(4) +#define BIT_LED0SV_8197F BIT(3) + +#define BIT_SHIFT_LED0CM_8197F 0 +#define BIT_MASK_LED0CM_8197F 0x7 +#define BIT_LED0CM_8197F(x) (((x) & BIT_MASK_LED0CM_8197F) << BIT_SHIFT_LED0CM_8197F) +#define BITS_LED0CM_8197F (BIT_MASK_LED0CM_8197F << BIT_SHIFT_LED0CM_8197F) +#define BIT_CLEAR_LED0CM_8197F(x) ((x) & (~BITS_LED0CM_8197F)) +#define BIT_GET_LED0CM_8197F(x) (((x) >> BIT_SHIFT_LED0CM_8197F) & BIT_MASK_LED0CM_8197F) +#define BIT_SET_LED0CM_8197F(x, v) (BIT_CLEAR_LED0CM_8197F(x) | BIT_LED0CM_8197F(v)) + + +/* 2 REG_FSIMR_8197F */ +#define BIT_FS_PDNINT_EN_8197F BIT(31) +#define BIT_FS_SPS_OCP_INT_EN_8197F BIT(29) +#define BIT_FS_PWMERR_INT_EN_8197F BIT(28) +#define BIT_FS_GPIOF_INT_EN_8197F BIT(27) +#define BIT_FS_GPIOE_INT_EN_8197F BIT(26) +#define BIT_FS_GPIOD_INT_EN_8197F BIT(25) +#define BIT_FS_GPIOC_INT_EN_8197F BIT(24) +#define BIT_FS_GPIOB_INT_EN_8197F BIT(23) +#define BIT_FS_GPIOA_INT_EN_8197F BIT(22) +#define BIT_FS_GPIO9_INT_EN_8197F BIT(21) +#define BIT_FS_GPIO8_INT_EN_8197F BIT(20) +#define BIT_FS_GPIO7_INT_EN_8197F BIT(19) +#define BIT_FS_GPIO6_INT_EN_8197F BIT(18) +#define BIT_FS_GPIO5_INT_EN_8197F BIT(17) +#define BIT_FS_GPIO4_INT_EN_8197F BIT(16) +#define BIT_FS_GPIO3_INT_EN_8197F BIT(15) +#define BIT_FS_GPIO2_INT_EN_8197F BIT(14) +#define BIT_FS_GPIO1_INT_EN_8197F BIT(13) +#define BIT_FS_GPIO0_INT_EN_8197F BIT(12) +#define BIT_FS_HCI_SUS_EN_8197F BIT(11) +#define BIT_FS_HCI_RES_EN_8197F BIT(10) +#define BIT_FS_HCI_RESET_EN_8197F BIT(9) +#define BIT_AXI_EXCEPT_FINT_EN_8197F BIT(8) +#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8197F BIT(7) +#define BIT_ACT2RECOVERY_INT_EN_V1_8197F BIT(6) +#define BIT_FS_TRPC_TO_INT_EN_8197F BIT(5) +#define BIT_FS_RPC_O_T_INT_EN_8197F BIT(4) +#define BIT_FS_32K_LEAVE_SETTING_MAK_8197F BIT(3) +#define BIT_FS_32K_ENTER_SETTING_MAK_8197F BIT(2) +#define BIT_FS_USB_LPMRSM_MSK_8197F BIT(1) +#define BIT_FS_USB_LPMINT_MSK_8197F BIT(0) + +/* 2 REG_FSISR_8197F */ +#define BIT_FS_PDNINT_8197F BIT(31) +#define BIT_FS_SPS_OCP_INT_8197F BIT(29) +#define BIT_FS_PWMERR_INT_8197F BIT(28) +#define BIT_FS_GPIOF_INT_8197F BIT(27) +#define BIT_FS_GPIOE_INT_8197F BIT(26) +#define BIT_FS_GPIOD_INT_8197F BIT(25) +#define BIT_FS_GPIOC_INT_8197F BIT(24) +#define BIT_FS_GPIOB_INT_8197F BIT(23) +#define BIT_FS_GPIOA_INT_8197F BIT(22) +#define BIT_FS_GPIO9_INT_8197F BIT(21) +#define BIT_FS_GPIO8_INT_8197F BIT(20) +#define BIT_FS_GPIO7_INT_8197F BIT(19) +#define BIT_FS_GPIO6_INT_8197F BIT(18) +#define BIT_FS_GPIO5_INT_8197F BIT(17) +#define BIT_FS_GPIO4_INT_8197F BIT(16) +#define BIT_FS_GPIO3_INT_8197F BIT(15) +#define BIT_FS_GPIO2_INT_8197F BIT(14) +#define BIT_FS_GPIO1_INT_8197F BIT(13) +#define BIT_FS_GPIO0_INT_8197F BIT(12) +#define BIT_FS_HCI_SUS_INT_8197F BIT(11) +#define BIT_FS_HCI_RES_INT_8197F BIT(10) +#define BIT_FS_HCI_RESET_INT_8197F BIT(9) +#define BIT_AXI_EXCEPT_FINT_8197F BIT(8) +#define BIT_FS_BTON_STS_UPDATE_INT_8197F BIT(7) +#define BIT_ACT2RECOVERY_INT_V1_8197F BIT(6) +#define BIT_FS_TRPC_TO_INT_INT_8197F BIT(5) +#define BIT_FS_RPC_O_T_INT_INT_8197F BIT(4) +#define BIT_FS_32K_LEAVE_SETTING_INT_8197F BIT(3) +#define BIT_FS_32K_ENTER_SETTING_INT_8197F BIT(2) +#define BIT_FS_USB_LPMRSM_INT_8197F BIT(1) +#define BIT_FS_USB_LPMINT_INT_8197F BIT(0) + +/* 2 REG_HSIMR_8197F */ +#define BIT_GPIOF_INT_EN_8197F BIT(31) +#define BIT_GPIOE_INT_EN_8197F BIT(30) +#define BIT_GPIOD_INT_EN_8197F BIT(29) +#define BIT_GPIOC_INT_EN_8197F BIT(28) +#define BIT_GPIOB_INT_EN_8197F BIT(27) +#define BIT_GPIOA_INT_EN_8197F BIT(26) +#define BIT_GPIO9_INT_EN_8197F BIT(25) +#define BIT_GPIO8_INT_EN_8197F BIT(24) +#define BIT_GPIO7_INT_EN_8197F BIT(23) +#define BIT_GPIO6_INT_EN_8197F BIT(22) +#define BIT_GPIO5_INT_EN_8197F BIT(21) +#define BIT_GPIO4_INT_EN_8197F BIT(20) +#define BIT_GPIO3_INT_EN_8197F BIT(19) +#define BIT_GPIO2_INT_EN_8197F BIT(18) +#define BIT_GPIO1_INT_EN_8197F BIT(17) +#define BIT_GPIO0_INT_EN_8197F BIT(16) +#define BIT_AXI_EXCEPT_HINT_EN_8197F BIT(9) +#define BIT_PDNINT_EN_V2_8197F BIT(8) +#define BIT_PDNINT_EN_V1_8197F BIT(7) +#define BIT_RON_INT_EN_V1_8197F BIT(6) +#define BIT_SPS_OCP_INT_EN_V1_8197F BIT(5) +#define BIT_GPIO15_0_INT_EN_V1_8197F BIT(0) + +/* 2 REG_HSISR_8197F */ +#define BIT_GPIOF_INT_8197F BIT(31) +#define BIT_GPIOE_INT_8197F BIT(30) +#define BIT_GPIOD_INT_8197F BIT(29) +#define BIT_GPIOC_INT_8197F BIT(28) +#define BIT_GPIOB_INT_8197F BIT(27) +#define BIT_GPIOA_INT_8197F BIT(26) +#define BIT_GPIO9_INT_8197F BIT(25) +#define BIT_GPIO8_INT_8197F BIT(24) +#define BIT_GPIO7_INT_8197F BIT(23) +#define BIT_GPIO6_INT_8197F BIT(22) +#define BIT_GPIO5_INT_8197F BIT(21) +#define BIT_GPIO4_INT_8197F BIT(20) +#define BIT_GPIO3_INT_8197F BIT(19) +#define BIT_GPIO2_INT_8197F BIT(18) +#define BIT_GPIO1_INT_8197F BIT(17) +#define BIT_GPIO0_INT_8197F BIT(16) +#define BIT_AXI_EXCEPT_HINT_8197F BIT(8) +#define BIT_PDNINT_V1_8197F BIT(7) +#define BIT_RON_INT_V1_8197F BIT(6) +#define BIT_SPS_OCP_INT_V1_8197F BIT(5) +#define BIT_GPIO15_0_INT_V1_8197F BIT(0) + +/* 2 REG_GPIO_EXT_CTRL_8197F */ + +#define BIT_SHIFT_GPIO_MOD_15_TO_8_8197F 24 +#define BIT_MASK_GPIO_MOD_15_TO_8_8197F 0xff +#define BIT_GPIO_MOD_15_TO_8_8197F(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8197F) << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) +#define BITS_GPIO_MOD_15_TO_8_8197F (BIT_MASK_GPIO_MOD_15_TO_8_8197F << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) +#define BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_MOD_15_TO_8_8197F)) +#define BIT_GET_GPIO_MOD_15_TO_8_8197F(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) & BIT_MASK_GPIO_MOD_15_TO_8_8197F) +#define BIT_SET_GPIO_MOD_15_TO_8_8197F(x, v) (BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) | BIT_GPIO_MOD_15_TO_8_8197F(v)) + + +#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F 16 +#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F 0xff +#define BIT_GPIO_IO_SEL_15_TO_8_8197F(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) +#define BITS_GPIO_IO_SEL_15_TO_8_8197F (BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8197F)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8197F(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F) +#define BIT_SET_GPIO_IO_SEL_15_TO_8_8197F(x, v) (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) | BIT_GPIO_IO_SEL_15_TO_8_8197F(v)) + + +#define BIT_SHIFT_GPIO_OUT_15_TO_8_8197F 8 +#define BIT_MASK_GPIO_OUT_15_TO_8_8197F 0xff +#define BIT_GPIO_OUT_15_TO_8_8197F(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8197F) << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) +#define BITS_GPIO_OUT_15_TO_8_8197F (BIT_MASK_GPIO_OUT_15_TO_8_8197F << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) +#define BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_OUT_15_TO_8_8197F)) +#define BIT_GET_GPIO_OUT_15_TO_8_8197F(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) & BIT_MASK_GPIO_OUT_15_TO_8_8197F) +#define BIT_SET_GPIO_OUT_15_TO_8_8197F(x, v) (BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) | BIT_GPIO_OUT_15_TO_8_8197F(v)) + + +#define BIT_SHIFT_GPIO_IN_15_TO_8_8197F 0 +#define BIT_MASK_GPIO_IN_15_TO_8_8197F 0xff +#define BIT_GPIO_IN_15_TO_8_8197F(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8197F) << BIT_SHIFT_GPIO_IN_15_TO_8_8197F) +#define BITS_GPIO_IN_15_TO_8_8197F (BIT_MASK_GPIO_IN_15_TO_8_8197F << BIT_SHIFT_GPIO_IN_15_TO_8_8197F) +#define BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8197F)) +#define BIT_GET_GPIO_IN_15_TO_8_8197F(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8197F) & BIT_MASK_GPIO_IN_15_TO_8_8197F) +#define BIT_SET_GPIO_IN_15_TO_8_8197F(x, v) (BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) | BIT_GPIO_IN_15_TO_8_8197F(v)) + + +/* 2 REG_PAD_CTRL1_8197F */ +#define BIT_PAPE_WLBT_SEL_8197F BIT(29) +#define BIT_LNAON_WLBT_SEL_8197F BIT(28) +#define BIT_BTGP_GPG3_FEN_8197F BIT(26) +#define BIT_BTGP_GPG2_FEN_8197F BIT(25) +#define BIT_BTGP_JTAG_EN_8197F BIT(24) +#define BIT_XTAL_CLK_EXTARNAL_EN_8197F BIT(23) +#define BIT_BTGP_UART0_EN_8197F BIT(22) +#define BIT_BTGP_UART1_EN_8197F BIT(21) +#define BIT_BTGP_SPI_EN_8197F BIT(20) +#define BIT_BTGP_GPIO_E2_8197F BIT(19) +#define BIT_BTGP_GPIO_EN_8197F BIT(18) + +#define BIT_SHIFT_BTGP_GPIO_SL_8197F 16 +#define BIT_MASK_BTGP_GPIO_SL_8197F 0x3 +#define BIT_BTGP_GPIO_SL_8197F(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8197F) << BIT_SHIFT_BTGP_GPIO_SL_8197F) +#define BITS_BTGP_GPIO_SL_8197F (BIT_MASK_BTGP_GPIO_SL_8197F << BIT_SHIFT_BTGP_GPIO_SL_8197F) +#define BIT_CLEAR_BTGP_GPIO_SL_8197F(x) ((x) & (~BITS_BTGP_GPIO_SL_8197F)) +#define BIT_GET_BTGP_GPIO_SL_8197F(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8197F) & BIT_MASK_BTGP_GPIO_SL_8197F) +#define BIT_SET_BTGP_GPIO_SL_8197F(x, v) (BIT_CLEAR_BTGP_GPIO_SL_8197F(x) | BIT_BTGP_GPIO_SL_8197F(v)) + +#define BIT_PAD_SDIO_SR_8197F BIT(14) +#define BIT_GPIO14_OUTPUT_PL_8197F BIT(13) +#define BIT_HOST_WAKE_PAD_PULL_EN_8197F BIT(12) +#define BIT_HOST_WAKE_PAD_SL_8197F BIT(11) +#define BIT_PAD_LNAON_SR_8197F BIT(10) +#define BIT_PAD_LNAON_E2_8197F BIT(9) +#define BIT_SW_LNAON_G_SEL_DATA_8197F BIT(8) +#define BIT_SW_LNAON_A_SEL_DATA_8197F BIT(7) +#define BIT_PAD_PAPE_SR_8197F BIT(6) +#define BIT_PAD_PAPE_E2_8197F BIT(5) +#define BIT_SW_PAPE_G_SEL_DATA_8197F BIT(4) +#define BIT_SW_PAPE_A_SEL_DATA_8197F BIT(3) +#define BIT_PAD_DPDT_SR_8197F BIT(2) +#define BIT_PAD_DPDT_PAD_E2_8197F BIT(1) +#define BIT_SW_DPDT_SEL_DATA_8197F BIT(0) + +/* 2 REG_WL_BT_PWR_CTRL_8197F */ +#define BIT_ISO_BD2PP_8197F BIT(31) +#define BIT_LDOV12B_EN_8197F BIT(30) +#define BIT_CKEN_BTGPS_8197F BIT(29) +#define BIT_FEN_BTGPS_8197F BIT(28) +#define BIT_BTCPU_BOOTSEL_8197F BIT(27) +#define BIT_SPI_SPEEDUP_8197F BIT(26) +#define BIT_DEVWAKE_PAD_TYPE_SEL_8197F BIT(24) +#define BIT_CLKREQ_PAD_TYPE_SEL_8197F BIT(23) +#define BIT_ISO_BTPON2PP_8197F BIT(22) +#define BIT_BT_HWROF_EN_8197F BIT(19) +#define BIT_BT_FUNC_EN_8197F BIT(18) +#define BIT_BT_HWPDN_SL_8197F BIT(17) +#define BIT_BT_DISN_EN_8197F BIT(16) +#define BIT_BT_PDN_PULL_EN_8197F BIT(15) +#define BIT_WL_PDN_PULL_EN_8197F BIT(14) +#define BIT_EXTERNAL_REQUEST_PL_8197F BIT(13) +#define BIT_GPIO0_2_3_PULL_LOW_EN_8197F BIT(12) +#define BIT_ISO_BA2PP_8197F BIT(11) +#define BIT_BT_AFE_LDO_EN_8197F BIT(10) +#define BIT_BT_AFE_PLL_EN_8197F BIT(9) +#define BIT_BT_DIG_CLK_EN_8197F BIT(8) +#define BIT_WL_DRV_EXIST_IDX_8197F BIT(5) +#define BIT_DOP_EHPAD_8197F BIT(4) +#define BIT_WL_HWROF_EN_8197F BIT(3) +#define BIT_WL_FUNC_EN_8197F BIT(2) +#define BIT_WL_HWPDN_SL_8197F BIT(1) +#define BIT_WL_HWPDN_EN_8197F BIT(0) + +/* 2 REG_SDM_DEBUG_8197F */ + +#define BIT_SHIFT_WLCLK_PHASE_8197F 0 +#define BIT_MASK_WLCLK_PHASE_8197F 0x1f +#define BIT_WLCLK_PHASE_8197F(x) (((x) & BIT_MASK_WLCLK_PHASE_8197F) << BIT_SHIFT_WLCLK_PHASE_8197F) +#define BITS_WLCLK_PHASE_8197F (BIT_MASK_WLCLK_PHASE_8197F << BIT_SHIFT_WLCLK_PHASE_8197F) +#define BIT_CLEAR_WLCLK_PHASE_8197F(x) ((x) & (~BITS_WLCLK_PHASE_8197F)) +#define BIT_GET_WLCLK_PHASE_8197F(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8197F) & BIT_MASK_WLCLK_PHASE_8197F) +#define BIT_SET_WLCLK_PHASE_8197F(x, v) (BIT_CLEAR_WLCLK_PHASE_8197F(x) | BIT_WLCLK_PHASE_8197F(v)) + + +/* 2 REG_SYS_SDIO_CTRL_8197F */ +#define BIT_DBG_GNT_WL_BT_8197F BIT(27) +#define BIT_LTE_MUX_CTRL_PATH_8197F BIT(26) +#define BIT_SDIO_INT_POLARITY_8197F BIT(19) +#define BIT_SDIO_INT_8197F BIT(18) +#define BIT_SDIO_OFF_EN_8197F BIT(17) +#define BIT_SDIO_ON_EN_8197F BIT(16) + +/* 2 REG_HCI_OPT_CTRL_8197F */ +#define BIT_USB_HOST_PWR_OFF_EN_8197F BIT(12) +#define BIT_SYM_LPS_BLOCK_EN_8197F BIT(11) +#define BIT_USB_LPM_ACT_EN_8197F BIT(10) +#define BIT_USB_LPM_NY_8197F BIT(9) +#define BIT_USB_SUS_DIS_8197F BIT(8) + +#define BIT_SHIFT_SDIO_PAD_E_8197F 5 +#define BIT_MASK_SDIO_PAD_E_8197F 0x7 +#define BIT_SDIO_PAD_E_8197F(x) (((x) & BIT_MASK_SDIO_PAD_E_8197F) << BIT_SHIFT_SDIO_PAD_E_8197F) +#define BITS_SDIO_PAD_E_8197F (BIT_MASK_SDIO_PAD_E_8197F << BIT_SHIFT_SDIO_PAD_E_8197F) +#define BIT_CLEAR_SDIO_PAD_E_8197F(x) ((x) & (~BITS_SDIO_PAD_E_8197F)) +#define BIT_GET_SDIO_PAD_E_8197F(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8197F) & BIT_MASK_SDIO_PAD_E_8197F) +#define BIT_SET_SDIO_PAD_E_8197F(x, v) (BIT_CLEAR_SDIO_PAD_E_8197F(x) | BIT_SDIO_PAD_E_8197F(v)) + +#define BIT_USB_LPPLL_EN_8197F BIT(4) +#define BIT_ROP_SW15_8197F BIT(2) +#define BIT_PCI_CKRDY_OPT_8197F BIT(1) +#define BIT_PCI_VAUX_EN_8197F BIT(0) + +/* 2 REG_AFE_CTRL4_8197F */ +#define BIT_RF1_SDMRSTB_8197F BIT(26) +#define BIT_RF1_RSTB_8197F BIT(25) +#define BIT_RF1_EN_8197F BIT(24) + +#define BIT_SHIFT_XTAL_LDO_8197F 20 +#define BIT_MASK_XTAL_LDO_8197F 0x7 +#define BIT_XTAL_LDO_8197F(x) (((x) & BIT_MASK_XTAL_LDO_8197F) << BIT_SHIFT_XTAL_LDO_8197F) +#define BITS_XTAL_LDO_8197F (BIT_MASK_XTAL_LDO_8197F << BIT_SHIFT_XTAL_LDO_8197F) +#define BIT_CLEAR_XTAL_LDO_8197F(x) ((x) & (~BITS_XTAL_LDO_8197F)) +#define BIT_GET_XTAL_LDO_8197F(x) (((x) >> BIT_SHIFT_XTAL_LDO_8197F) & BIT_MASK_XTAL_LDO_8197F) +#define BIT_SET_XTAL_LDO_8197F(x, v) (BIT_CLEAR_XTAL_LDO_8197F(x) | BIT_XTAL_LDO_8197F(v)) + +#define BIT_ADC_CK_SYNC_EN_8197F BIT(16) + +/* 2 REG_LDO_SWR_CTRL_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_MCUFW_CTRL_8197F */ + +#define BIT_SHIFT_RPWM_8197F 24 +#define BIT_MASK_RPWM_8197F 0xff +#define BIT_RPWM_8197F(x) (((x) & BIT_MASK_RPWM_8197F) << BIT_SHIFT_RPWM_8197F) +#define BITS_RPWM_8197F (BIT_MASK_RPWM_8197F << BIT_SHIFT_RPWM_8197F) +#define BIT_CLEAR_RPWM_8197F(x) ((x) & (~BITS_RPWM_8197F)) +#define BIT_GET_RPWM_8197F(x) (((x) >> BIT_SHIFT_RPWM_8197F) & BIT_MASK_RPWM_8197F) +#define BIT_SET_RPWM_8197F(x, v) (BIT_CLEAR_RPWM_8197F(x) | BIT_RPWM_8197F(v)) + +#define BIT_CPRST_8197F BIT(23) +#define BIT_ANA_PORT_EN_8197F BIT(22) +#define BIT_MAC_PORT_EN_8197F BIT(21) +#define BIT_BOOT_FSPI_EN_8197F BIT(20) +#define BIT_ROM_DLEN_8197F BIT(19) + +#define BIT_SHIFT_ROM_PGE_8197F 16 +#define BIT_MASK_ROM_PGE_8197F 0x7 +#define BIT_ROM_PGE_8197F(x) (((x) & BIT_MASK_ROM_PGE_8197F) << BIT_SHIFT_ROM_PGE_8197F) +#define BITS_ROM_PGE_8197F (BIT_MASK_ROM_PGE_8197F << BIT_SHIFT_ROM_PGE_8197F) +#define BIT_CLEAR_ROM_PGE_8197F(x) ((x) & (~BITS_ROM_PGE_8197F)) +#define BIT_GET_ROM_PGE_8197F(x) (((x) >> BIT_SHIFT_ROM_PGE_8197F) & BIT_MASK_ROM_PGE_8197F) +#define BIT_SET_ROM_PGE_8197F(x, v) (BIT_CLEAR_ROM_PGE_8197F(x) | BIT_ROM_PGE_8197F(v)) + +#define BIT_FW_INIT_RDY_8197F BIT(15) +#define BIT_FW_DW_RDY_8197F BIT(14) + +#define BIT_SHIFT_CPU_CLK_SEL_8197F 12 +#define BIT_MASK_CPU_CLK_SEL_8197F 0x3 +#define BIT_CPU_CLK_SEL_8197F(x) (((x) & BIT_MASK_CPU_CLK_SEL_8197F) << BIT_SHIFT_CPU_CLK_SEL_8197F) +#define BITS_CPU_CLK_SEL_8197F (BIT_MASK_CPU_CLK_SEL_8197F << BIT_SHIFT_CPU_CLK_SEL_8197F) +#define BIT_CLEAR_CPU_CLK_SEL_8197F(x) ((x) & (~BITS_CPU_CLK_SEL_8197F)) +#define BIT_GET_CPU_CLK_SEL_8197F(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8197F) & BIT_MASK_CPU_CLK_SEL_8197F) +#define BIT_SET_CPU_CLK_SEL_8197F(x, v) (BIT_CLEAR_CPU_CLK_SEL_8197F(x) | BIT_CPU_CLK_SEL_8197F(v)) + +#define BIT_CCLK_CHG_MASK_8197F BIT(11) +#define BIT_FW_INIT_RDY_V1_8197F BIT(10) +#define BIT_R_8051_SPD_8197F BIT(9) +#define BIT_MCU_CLK_EN_8197F BIT(8) +#define BIT_RAM_DL_SEL_8197F BIT(7) +#define BIT_WINTINI_RDY_8197F BIT(6) +#define BIT_RF_INIT_RDY_8197F BIT(5) +#define BIT_BB_INIT_RDY_8197F BIT(4) +#define BIT_MAC_INIT_RDY_8197F BIT(3) +#define BIT_MCU_FWDL_RDY_8197F BIT(1) +#define BIT_MCU_FWDL_EN_8197F BIT(0) + +/* 2 REG_MCU_TST_CFG_8197F */ + +#define BIT_SHIFT_LBKTST_8197F 0 +#define BIT_MASK_LBKTST_8197F 0xffff +#define BIT_LBKTST_8197F(x) (((x) & BIT_MASK_LBKTST_8197F) << BIT_SHIFT_LBKTST_8197F) +#define BITS_LBKTST_8197F (BIT_MASK_LBKTST_8197F << BIT_SHIFT_LBKTST_8197F) +#define BIT_CLEAR_LBKTST_8197F(x) ((x) & (~BITS_LBKTST_8197F)) +#define BIT_GET_LBKTST_8197F(x) (((x) >> BIT_SHIFT_LBKTST_8197F) & BIT_MASK_LBKTST_8197F) +#define BIT_SET_LBKTST_8197F(x, v) (BIT_CLEAR_LBKTST_8197F(x) | BIT_LBKTST_8197F(v)) + + +/* 2 REG_HMEBOX_E0_E1_8197F */ + +#define BIT_SHIFT_HOST_MSG_E1_8197F 16 +#define BIT_MASK_HOST_MSG_E1_8197F 0xffff +#define BIT_HOST_MSG_E1_8197F(x) (((x) & BIT_MASK_HOST_MSG_E1_8197F) << BIT_SHIFT_HOST_MSG_E1_8197F) +#define BITS_HOST_MSG_E1_8197F (BIT_MASK_HOST_MSG_E1_8197F << BIT_SHIFT_HOST_MSG_E1_8197F) +#define BIT_CLEAR_HOST_MSG_E1_8197F(x) ((x) & (~BITS_HOST_MSG_E1_8197F)) +#define BIT_GET_HOST_MSG_E1_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8197F) & BIT_MASK_HOST_MSG_E1_8197F) +#define BIT_SET_HOST_MSG_E1_8197F(x, v) (BIT_CLEAR_HOST_MSG_E1_8197F(x) | BIT_HOST_MSG_E1_8197F(v)) + + +#define BIT_SHIFT_HOST_MSG_E0_8197F 0 +#define BIT_MASK_HOST_MSG_E0_8197F 0xffff +#define BIT_HOST_MSG_E0_8197F(x) (((x) & BIT_MASK_HOST_MSG_E0_8197F) << BIT_SHIFT_HOST_MSG_E0_8197F) +#define BITS_HOST_MSG_E0_8197F (BIT_MASK_HOST_MSG_E0_8197F << BIT_SHIFT_HOST_MSG_E0_8197F) +#define BIT_CLEAR_HOST_MSG_E0_8197F(x) ((x) & (~BITS_HOST_MSG_E0_8197F)) +#define BIT_GET_HOST_MSG_E0_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8197F) & BIT_MASK_HOST_MSG_E0_8197F) +#define BIT_SET_HOST_MSG_E0_8197F(x, v) (BIT_CLEAR_HOST_MSG_E0_8197F(x) | BIT_HOST_MSG_E0_8197F(v)) + + +/* 2 REG_HMEBOX_E2_E3_8197F */ + +#define BIT_SHIFT_HOST_MSG_E3_8197F 16 +#define BIT_MASK_HOST_MSG_E3_8197F 0xffff +#define BIT_HOST_MSG_E3_8197F(x) (((x) & BIT_MASK_HOST_MSG_E3_8197F) << BIT_SHIFT_HOST_MSG_E3_8197F) +#define BITS_HOST_MSG_E3_8197F (BIT_MASK_HOST_MSG_E3_8197F << BIT_SHIFT_HOST_MSG_E3_8197F) +#define BIT_CLEAR_HOST_MSG_E3_8197F(x) ((x) & (~BITS_HOST_MSG_E3_8197F)) +#define BIT_GET_HOST_MSG_E3_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8197F) & BIT_MASK_HOST_MSG_E3_8197F) +#define BIT_SET_HOST_MSG_E3_8197F(x, v) (BIT_CLEAR_HOST_MSG_E3_8197F(x) | BIT_HOST_MSG_E3_8197F(v)) + + +#define BIT_SHIFT_HOST_MSG_E2_8197F 0 +#define BIT_MASK_HOST_MSG_E2_8197F 0xffff +#define BIT_HOST_MSG_E2_8197F(x) (((x) & BIT_MASK_HOST_MSG_E2_8197F) << BIT_SHIFT_HOST_MSG_E2_8197F) +#define BITS_HOST_MSG_E2_8197F (BIT_MASK_HOST_MSG_E2_8197F << BIT_SHIFT_HOST_MSG_E2_8197F) +#define BIT_CLEAR_HOST_MSG_E2_8197F(x) ((x) & (~BITS_HOST_MSG_E2_8197F)) +#define BIT_GET_HOST_MSG_E2_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8197F) & BIT_MASK_HOST_MSG_E2_8197F) +#define BIT_SET_HOST_MSG_E2_8197F(x, v) (BIT_CLEAR_HOST_MSG_E2_8197F(x) | BIT_HOST_MSG_E2_8197F(v)) + + +/* 2 REG_WLLPS_CTRL_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_AFE_CTRL5_8197F */ +#define BIT_BB_DBG_SEL_AFE_SDM_V3_8197F BIT(31) +#define BIT_ORDER_SDM_8197F BIT(30) +#define BIT_RFE_SEL_SDM_8197F BIT(29) + +#define BIT_SHIFT_REF_SEL_8197F 25 +#define BIT_MASK_REF_SEL_8197F 0xf +#define BIT_REF_SEL_8197F(x) (((x) & BIT_MASK_REF_SEL_8197F) << BIT_SHIFT_REF_SEL_8197F) +#define BITS_REF_SEL_8197F (BIT_MASK_REF_SEL_8197F << BIT_SHIFT_REF_SEL_8197F) +#define BIT_CLEAR_REF_SEL_8197F(x) ((x) & (~BITS_REF_SEL_8197F)) +#define BIT_GET_REF_SEL_8197F(x) (((x) >> BIT_SHIFT_REF_SEL_8197F) & BIT_MASK_REF_SEL_8197F) +#define BIT_SET_REF_SEL_8197F(x, v) (BIT_CLEAR_REF_SEL_8197F(x) | BIT_REF_SEL_8197F(v)) + + +#define BIT_SHIFT_F0F_SDM_V2_8197F 12 +#define BIT_MASK_F0F_SDM_V2_8197F 0x1fff +#define BIT_F0F_SDM_V2_8197F(x) (((x) & BIT_MASK_F0F_SDM_V2_8197F) << BIT_SHIFT_F0F_SDM_V2_8197F) +#define BITS_F0F_SDM_V2_8197F (BIT_MASK_F0F_SDM_V2_8197F << BIT_SHIFT_F0F_SDM_V2_8197F) +#define BIT_CLEAR_F0F_SDM_V2_8197F(x) ((x) & (~BITS_F0F_SDM_V2_8197F)) +#define BIT_GET_F0F_SDM_V2_8197F(x) (((x) >> BIT_SHIFT_F0F_SDM_V2_8197F) & BIT_MASK_F0F_SDM_V2_8197F) +#define BIT_SET_F0F_SDM_V2_8197F(x, v) (BIT_CLEAR_F0F_SDM_V2_8197F(x) | BIT_F0F_SDM_V2_8197F(v)) + + +#define BIT_SHIFT_F0N_SDM_V2_8197F 9 +#define BIT_MASK_F0N_SDM_V2_8197F 0x7 +#define BIT_F0N_SDM_V2_8197F(x) (((x) & BIT_MASK_F0N_SDM_V2_8197F) << BIT_SHIFT_F0N_SDM_V2_8197F) +#define BITS_F0N_SDM_V2_8197F (BIT_MASK_F0N_SDM_V2_8197F << BIT_SHIFT_F0N_SDM_V2_8197F) +#define BIT_CLEAR_F0N_SDM_V2_8197F(x) ((x) & (~BITS_F0N_SDM_V2_8197F)) +#define BIT_GET_F0N_SDM_V2_8197F(x) (((x) >> BIT_SHIFT_F0N_SDM_V2_8197F) & BIT_MASK_F0N_SDM_V2_8197F) +#define BIT_SET_F0N_SDM_V2_8197F(x, v) (BIT_CLEAR_F0N_SDM_V2_8197F(x) | BIT_F0N_SDM_V2_8197F(v)) + + +#define BIT_SHIFT_DIVN_SDM_V2_8197F 3 +#define BIT_MASK_DIVN_SDM_V2_8197F 0x3f +#define BIT_DIVN_SDM_V2_8197F(x) (((x) & BIT_MASK_DIVN_SDM_V2_8197F) << BIT_SHIFT_DIVN_SDM_V2_8197F) +#define BITS_DIVN_SDM_V2_8197F (BIT_MASK_DIVN_SDM_V2_8197F << BIT_SHIFT_DIVN_SDM_V2_8197F) +#define BIT_CLEAR_DIVN_SDM_V2_8197F(x) ((x) & (~BITS_DIVN_SDM_V2_8197F)) +#define BIT_GET_DIVN_SDM_V2_8197F(x) (((x) >> BIT_SHIFT_DIVN_SDM_V2_8197F) & BIT_MASK_DIVN_SDM_V2_8197F) +#define BIT_SET_DIVN_SDM_V2_8197F(x, v) (BIT_CLEAR_DIVN_SDM_V2_8197F(x) | BIT_DIVN_SDM_V2_8197F(v)) + + +#define BIT_SHIFT_DITHER_SDM_V2_8197F 0 +#define BIT_MASK_DITHER_SDM_V2_8197F 0x7 +#define BIT_DITHER_SDM_V2_8197F(x) (((x) & BIT_MASK_DITHER_SDM_V2_8197F) << BIT_SHIFT_DITHER_SDM_V2_8197F) +#define BITS_DITHER_SDM_V2_8197F (BIT_MASK_DITHER_SDM_V2_8197F << BIT_SHIFT_DITHER_SDM_V2_8197F) +#define BIT_CLEAR_DITHER_SDM_V2_8197F(x) ((x) & (~BITS_DITHER_SDM_V2_8197F)) +#define BIT_GET_DITHER_SDM_V2_8197F(x) (((x) >> BIT_SHIFT_DITHER_SDM_V2_8197F) & BIT_MASK_DITHER_SDM_V2_8197F) +#define BIT_SET_DITHER_SDM_V2_8197F(x, v) (BIT_CLEAR_DITHER_SDM_V2_8197F(x) | BIT_DITHER_SDM_V2_8197F(v)) + + +/* 2 REG_GPIO_DEBOUNCE_CTRL_8197F */ +#define BIT_WLGP_DBC1EN_8197F BIT(15) + +#define BIT_SHIFT_WLGP_DBC1_8197F 8 +#define BIT_MASK_WLGP_DBC1_8197F 0xf +#define BIT_WLGP_DBC1_8197F(x) (((x) & BIT_MASK_WLGP_DBC1_8197F) << BIT_SHIFT_WLGP_DBC1_8197F) +#define BITS_WLGP_DBC1_8197F (BIT_MASK_WLGP_DBC1_8197F << BIT_SHIFT_WLGP_DBC1_8197F) +#define BIT_CLEAR_WLGP_DBC1_8197F(x) ((x) & (~BITS_WLGP_DBC1_8197F)) +#define BIT_GET_WLGP_DBC1_8197F(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8197F) & BIT_MASK_WLGP_DBC1_8197F) +#define BIT_SET_WLGP_DBC1_8197F(x, v) (BIT_CLEAR_WLGP_DBC1_8197F(x) | BIT_WLGP_DBC1_8197F(v)) + +#define BIT_WLGP_DBC0EN_8197F BIT(7) + +#define BIT_SHIFT_WLGP_DBC0_8197F 0 +#define BIT_MASK_WLGP_DBC0_8197F 0xf +#define BIT_WLGP_DBC0_8197F(x) (((x) & BIT_MASK_WLGP_DBC0_8197F) << BIT_SHIFT_WLGP_DBC0_8197F) +#define BITS_WLGP_DBC0_8197F (BIT_MASK_WLGP_DBC0_8197F << BIT_SHIFT_WLGP_DBC0_8197F) +#define BIT_CLEAR_WLGP_DBC0_8197F(x) ((x) & (~BITS_WLGP_DBC0_8197F)) +#define BIT_GET_WLGP_DBC0_8197F(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8197F) & BIT_MASK_WLGP_DBC0_8197F) +#define BIT_SET_WLGP_DBC0_8197F(x, v) (BIT_CLEAR_WLGP_DBC0_8197F(x) | BIT_WLGP_DBC0_8197F(v)) + + +/* 2 REG_RPWM2_8197F */ + +#define BIT_SHIFT_RPWM2_8197F 16 +#define BIT_MASK_RPWM2_8197F 0xffff +#define BIT_RPWM2_8197F(x) (((x) & BIT_MASK_RPWM2_8197F) << BIT_SHIFT_RPWM2_8197F) +#define BITS_RPWM2_8197F (BIT_MASK_RPWM2_8197F << BIT_SHIFT_RPWM2_8197F) +#define BIT_CLEAR_RPWM2_8197F(x) ((x) & (~BITS_RPWM2_8197F)) +#define BIT_GET_RPWM2_8197F(x) (((x) >> BIT_SHIFT_RPWM2_8197F) & BIT_MASK_RPWM2_8197F) +#define BIT_SET_RPWM2_8197F(x, v) (BIT_CLEAR_RPWM2_8197F(x) | BIT_RPWM2_8197F(v)) + + +/* 2 REG_SYSON_FSM_MON_8197F */ + +#define BIT_SHIFT_FSM_MON_SEL_8197F 24 +#define BIT_MASK_FSM_MON_SEL_8197F 0x7 +#define BIT_FSM_MON_SEL_8197F(x) (((x) & BIT_MASK_FSM_MON_SEL_8197F) << BIT_SHIFT_FSM_MON_SEL_8197F) +#define BITS_FSM_MON_SEL_8197F (BIT_MASK_FSM_MON_SEL_8197F << BIT_SHIFT_FSM_MON_SEL_8197F) +#define BIT_CLEAR_FSM_MON_SEL_8197F(x) ((x) & (~BITS_FSM_MON_SEL_8197F)) +#define BIT_GET_FSM_MON_SEL_8197F(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8197F) & BIT_MASK_FSM_MON_SEL_8197F) +#define BIT_SET_FSM_MON_SEL_8197F(x, v) (BIT_CLEAR_FSM_MON_SEL_8197F(x) | BIT_FSM_MON_SEL_8197F(v)) + +#define BIT_DOP_ELDO_8197F BIT(23) +#define BIT_FSM_MON_UPD_8197F BIT(15) + +#define BIT_SHIFT_FSM_PAR_8197F 0 +#define BIT_MASK_FSM_PAR_8197F 0x7fff +#define BIT_FSM_PAR_8197F(x) (((x) & BIT_MASK_FSM_PAR_8197F) << BIT_SHIFT_FSM_PAR_8197F) +#define BITS_FSM_PAR_8197F (BIT_MASK_FSM_PAR_8197F << BIT_SHIFT_FSM_PAR_8197F) +#define BIT_CLEAR_FSM_PAR_8197F(x) ((x) & (~BITS_FSM_PAR_8197F)) +#define BIT_GET_FSM_PAR_8197F(x) (((x) >> BIT_SHIFT_FSM_PAR_8197F) & BIT_MASK_FSM_PAR_8197F) +#define BIT_SET_FSM_PAR_8197F(x, v) (BIT_CLEAR_FSM_PAR_8197F(x) | BIT_FSM_PAR_8197F(v)) + + +/* 2 REG_AFE_CTRL6_8197F */ + +#define BIT_SHIFT_TSFT_SEL_V1_8197F 0 +#define BIT_MASK_TSFT_SEL_V1_8197F 0x7 +#define BIT_TSFT_SEL_V1_8197F(x) (((x) & BIT_MASK_TSFT_SEL_V1_8197F) << BIT_SHIFT_TSFT_SEL_V1_8197F) +#define BITS_TSFT_SEL_V1_8197F (BIT_MASK_TSFT_SEL_V1_8197F << BIT_SHIFT_TSFT_SEL_V1_8197F) +#define BIT_CLEAR_TSFT_SEL_V1_8197F(x) ((x) & (~BITS_TSFT_SEL_V1_8197F)) +#define BIT_GET_TSFT_SEL_V1_8197F(x) (((x) >> BIT_SHIFT_TSFT_SEL_V1_8197F) & BIT_MASK_TSFT_SEL_V1_8197F) +#define BIT_SET_TSFT_SEL_V1_8197F(x, v) (BIT_CLEAR_TSFT_SEL_V1_8197F(x) | BIT_TSFT_SEL_V1_8197F(v)) + + +/* 2 REG_PMC_DBG_CTRL1_8197F */ +#define BIT_BT_INT_EN_8197F BIT(31) + +#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F 16 +#define BIT_MASK_RD_WR_WIFI_BT_INFO_8197F 0x7fff +#define BIT_RD_WR_WIFI_BT_INFO_8197F(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8197F) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) +#define BITS_RD_WR_WIFI_BT_INFO_8197F (BIT_MASK_RD_WR_WIFI_BT_INFO_8197F << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8197F)) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8197F(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) & BIT_MASK_RD_WR_WIFI_BT_INFO_8197F) +#define BIT_SET_RD_WR_WIFI_BT_INFO_8197F(x, v) (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) | BIT_RD_WR_WIFI_BT_INFO_8197F(v)) + +#define BIT_PMC_WR_OVF_8197F BIT(8) + +#define BIT_SHIFT_WLPMC_ERRINT_8197F 0 +#define BIT_MASK_WLPMC_ERRINT_8197F 0xff +#define BIT_WLPMC_ERRINT_8197F(x) (((x) & BIT_MASK_WLPMC_ERRINT_8197F) << BIT_SHIFT_WLPMC_ERRINT_8197F) +#define BITS_WLPMC_ERRINT_8197F (BIT_MASK_WLPMC_ERRINT_8197F << BIT_SHIFT_WLPMC_ERRINT_8197F) +#define BIT_CLEAR_WLPMC_ERRINT_8197F(x) ((x) & (~BITS_WLPMC_ERRINT_8197F)) +#define BIT_GET_WLPMC_ERRINT_8197F(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8197F) & BIT_MASK_WLPMC_ERRINT_8197F) +#define BIT_SET_WLPMC_ERRINT_8197F(x, v) (BIT_CLEAR_WLPMC_ERRINT_8197F(x) | BIT_WLPMC_ERRINT_8197F(v)) + + +/* 2 REG_AFE_CTRL7_8197F */ + +#define BIT_SHIFT_SEL_V_8197F 30 +#define BIT_MASK_SEL_V_8197F 0x3 +#define BIT_SEL_V_8197F(x) (((x) & BIT_MASK_SEL_V_8197F) << BIT_SHIFT_SEL_V_8197F) +#define BITS_SEL_V_8197F (BIT_MASK_SEL_V_8197F << BIT_SHIFT_SEL_V_8197F) +#define BIT_CLEAR_SEL_V_8197F(x) ((x) & (~BITS_SEL_V_8197F)) +#define BIT_GET_SEL_V_8197F(x) (((x) >> BIT_SHIFT_SEL_V_8197F) & BIT_MASK_SEL_V_8197F) +#define BIT_SET_SEL_V_8197F(x, v) (BIT_CLEAR_SEL_V_8197F(x) | BIT_SEL_V_8197F(v)) + +#define BIT_SEL_LDO_PC_8197F BIT(29) + +#define BIT_SHIFT_CK_MON_SEL_V2_8197F 26 +#define BIT_MASK_CK_MON_SEL_V2_8197F 0x7 +#define BIT_CK_MON_SEL_V2_8197F(x) (((x) & BIT_MASK_CK_MON_SEL_V2_8197F) << BIT_SHIFT_CK_MON_SEL_V2_8197F) +#define BITS_CK_MON_SEL_V2_8197F (BIT_MASK_CK_MON_SEL_V2_8197F << BIT_SHIFT_CK_MON_SEL_V2_8197F) +#define BIT_CLEAR_CK_MON_SEL_V2_8197F(x) ((x) & (~BITS_CK_MON_SEL_V2_8197F)) +#define BIT_GET_CK_MON_SEL_V2_8197F(x) (((x) >> BIT_SHIFT_CK_MON_SEL_V2_8197F) & BIT_MASK_CK_MON_SEL_V2_8197F) +#define BIT_SET_CK_MON_SEL_V2_8197F(x, v) (BIT_CLEAR_CK_MON_SEL_V2_8197F(x) | BIT_CK_MON_SEL_V2_8197F(v)) + +#define BIT_CK_MON_EN_8197F BIT(25) +#define BIT_FREF_EDGE_8197F BIT(24) +#define BIT_CK320M_EN_8197F BIT(23) +#define BIT_CK_5M_EN_8197F BIT(22) +#define BIT_TESTEN_8197F BIT(21) + +/* 2 REG_HIMR0_8197F */ +#define BIT_TIMEOUT_INTERRUPT2_MASK_8197F BIT(31) +#define BIT_TIMEOUT_INTERRUTP1_MASK_8197F BIT(30) +#define BIT_PSTIMEOUT_MSK_8197F BIT(29) +#define BIT_GTINT4_MSK_8197F BIT(28) +#define BIT_GTINT3_MSK_8197F BIT(27) +#define BIT_TXBCN0ERR_MSK_8197F BIT(26) +#define BIT_TXBCN0OK_MSK_8197F BIT(25) +#define BIT_TSF_BIT32_TOGGLE_MSK_8197F BIT(24) +#define BIT_BCNDMAINT0_MSK_8197F BIT(20) +#define BIT_BCNDERR0_MSK_8197F BIT(16) +#define BIT_HSISR_IND_ON_INT_MSK_8197F BIT(15) +#define BIT_BCNDMAINT_E_MSK_8197F BIT(14) +#define BIT_CTWEND_MSK_8197F BIT(12) +#define BIT_HISR1_IND_MSK_8197F BIT(11) +#define BIT_C2HCMD_MSK_8197F BIT(10) +#define BIT_CPWM2_MSK_8197F BIT(9) +#define BIT_CPWM_MSK_8197F BIT(8) +#define BIT_HIGHDOK_MSK_8197F BIT(7) +#define BIT_MGTDOK_MSK_8197F BIT(6) +#define BIT_BKDOK_MSK_8197F BIT(5) +#define BIT_BEDOK_MSK_8197F BIT(4) +#define BIT_VIDOK_MSK_8197F BIT(3) +#define BIT_VODOK_MSK_8197F BIT(2) +#define BIT_RDU_MSK_8197F BIT(1) +#define BIT_RXOK_MSK_8197F BIT(0) + +/* 2 REG_HISR0_8197F */ +#define BIT_TIMEOUT_INTERRUPT2_8197F BIT(31) +#define BIT_TIMEOUT_INTERRUTP1_8197F BIT(30) +#define BIT_PSTIMEOUT_8197F BIT(29) +#define BIT_GTINT4_8197F BIT(28) +#define BIT_GTINT3_8197F BIT(27) +#define BIT_TXBCN0ERR_8197F BIT(26) +#define BIT_TXBCN0OK_8197F BIT(25) +#define BIT_TSF_BIT32_TOGGLE_8197F BIT(24) +#define BIT_BCNDMAINT0_8197F BIT(20) +#define BIT_BCNDERR0_8197F BIT(16) +#define BIT_HSISR_IND_ON_INT_8197F BIT(15) +#define BIT_BCNDMAINT_E_8197F BIT(14) +#define BIT_CTWEND_8197F BIT(12) +#define BIT_HISR1_IND_INT_8197F BIT(11) +#define BIT_C2HCMD_8197F BIT(10) +#define BIT_CPWM2_8197F BIT(9) +#define BIT_CPWM_8197F BIT(8) +#define BIT_HIGHDOK_8197F BIT(7) +#define BIT_MGTDOK_8197F BIT(6) +#define BIT_BKDOK_8197F BIT(5) +#define BIT_BEDOK_8197F BIT(4) +#define BIT_VIDOK_8197F BIT(3) +#define BIT_VODOK_8197F BIT(2) +#define BIT_RDU_8197F BIT(1) +#define BIT_RXOK_8197F BIT(0) + +/* 2 REG_HIMR1_8197F */ +#define BIT_BTON_STS_UPDATE_MSK_8197F BIT(29) +#define BIT_MCU_ERR_MASK_8197F BIT(28) +#define BIT_BCNDMAINT7__MSK_8197F BIT(27) +#define BIT_BCNDMAINT6__MSK_8197F BIT(26) +#define BIT_BCNDMAINT5__MSK_8197F BIT(25) +#define BIT_BCNDMAINT4__MSK_8197F BIT(24) +#define BIT_BCNDMAINT3_MSK_8197F BIT(23) +#define BIT_BCNDMAINT2_MSK_8197F BIT(22) +#define BIT_BCNDMAINT1_MSK_8197F BIT(21) +#define BIT_BCNDERR7_MSK_8197F BIT(20) +#define BIT_BCNDERR6_MSK_8197F BIT(19) +#define BIT_BCNDERR5_MSK_8197F BIT(18) +#define BIT_BCNDERR4_MSK_8197F BIT(17) +#define BIT_BCNDERR3_MSK_8197F BIT(16) +#define BIT_BCNDERR2_MSK_8197F BIT(15) +#define BIT_BCNDERR1_MSK_8197F BIT(14) +#define BIT_ATIMEND_E_MSK_8197F BIT(13) +#define BIT_ATIMEND__MSK_8197F BIT(12) +#define BIT_TXERR_MSK_8197F BIT(11) +#define BIT_RXERR_MSK_8197F BIT(10) +#define BIT_TXFOVW_MSK_8197F BIT(9) +#define BIT_FOVW_MSK_8197F BIT(8) + +/* 2 REG_HISR1_8197F */ +#define BIT_BTON_STS_UPDATE_INT_8197F BIT(29) +#define BIT_MCU_ERR_8197F BIT(28) +#define BIT_BCNDMAINT7_8197F BIT(27) +#define BIT_BCNDMAINT6_8197F BIT(26) +#define BIT_BCNDMAINT5_8197F BIT(25) +#define BIT_BCNDMAINT4_8197F BIT(24) +#define BIT_BCNDMAINT3_8197F BIT(23) +#define BIT_BCNDMAINT2_8197F BIT(22) +#define BIT_BCNDMAINT1_8197F BIT(21) +#define BIT_BCNDERR7_8197F BIT(20) +#define BIT_BCNDERR6_8197F BIT(19) +#define BIT_BCNDERR5_8197F BIT(18) +#define BIT_BCNDERR4_8197F BIT(17) +#define BIT_BCNDERR3_8197F BIT(16) +#define BIT_BCNDERR2_8197F BIT(15) +#define BIT_BCNDERR1_8197F BIT(14) +#define BIT_ATIMEND_E_8197F BIT(13) +#define BIT_ATIMEND_8197F BIT(12) +#define BIT_TXERR_INT_8197F BIT(11) +#define BIT_RXERR_INT_8197F BIT(10) +#define BIT_TXFOVW_8197F BIT(9) +#define BIT_FOVW_8197F BIT(8) + +/* 2 REG_DBG_PORT_SEL_8197F */ + +#define BIT_SHIFT_DEBUG_ST_8197F 0 +#define BIT_MASK_DEBUG_ST_8197F 0xffffffffL +#define BIT_DEBUG_ST_8197F(x) (((x) & BIT_MASK_DEBUG_ST_8197F) << BIT_SHIFT_DEBUG_ST_8197F) +#define BITS_DEBUG_ST_8197F (BIT_MASK_DEBUG_ST_8197F << BIT_SHIFT_DEBUG_ST_8197F) +#define BIT_CLEAR_DEBUG_ST_8197F(x) ((x) & (~BITS_DEBUG_ST_8197F)) +#define BIT_GET_DEBUG_ST_8197F(x) (((x) >> BIT_SHIFT_DEBUG_ST_8197F) & BIT_MASK_DEBUG_ST_8197F) +#define BIT_SET_DEBUG_ST_8197F(x, v) (BIT_CLEAR_DEBUG_ST_8197F(x) | BIT_DEBUG_ST_8197F(v)) + + +/* 2 REG_PAD_CTRL2_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_LD_B12V_EN_V1_8197F BIT(7) +#define BIT_EECS_IOSEL_V1_8197F BIT(6) +#define BIT_EECS_DATA_O_V1_8197F BIT(5) +#define BIT_EECS_DATA_I_V1_8197F BIT(4) +#define BIT_EESK_IOSEL_V1_8197F BIT(2) +#define BIT_EESK_DATA_O_V1_8197F BIT(1) +#define BIT_EESK_DATA_I_V1_8197F BIT(0) + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_PMC_DBG_CTRL2_8197F */ + +#define BIT_SHIFT_EFUSE_BURN_GNT_8197F 24 +#define BIT_MASK_EFUSE_BURN_GNT_8197F 0xff +#define BIT_EFUSE_BURN_GNT_8197F(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8197F) << BIT_SHIFT_EFUSE_BURN_GNT_8197F) +#define BITS_EFUSE_BURN_GNT_8197F (BIT_MASK_EFUSE_BURN_GNT_8197F << BIT_SHIFT_EFUSE_BURN_GNT_8197F) +#define BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) ((x) & (~BITS_EFUSE_BURN_GNT_8197F)) +#define BIT_GET_EFUSE_BURN_GNT_8197F(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8197F) & BIT_MASK_EFUSE_BURN_GNT_8197F) +#define BIT_SET_EFUSE_BURN_GNT_8197F(x, v) (BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) | BIT_EFUSE_BURN_GNT_8197F(v)) + +#define BIT_STOP_WL_PMC_8197F BIT(9) +#define BIT_STOP_SYM_PMC_8197F BIT(8) +#define BIT_REG_RST_WLPMC_8197F BIT(5) +#define BIT_REG_RST_PD12N_8197F BIT(4) +#define BIT_SYSON_DIS_WLREG_WRMSK_8197F BIT(3) +#define BIT_SYSON_DIS_PMCREG_WRMSK_8197F BIT(2) + +#define BIT_SHIFT_SYSON_REG_ARB_8197F 0 +#define BIT_MASK_SYSON_REG_ARB_8197F 0x3 +#define BIT_SYSON_REG_ARB_8197F(x) (((x) & BIT_MASK_SYSON_REG_ARB_8197F) << BIT_SHIFT_SYSON_REG_ARB_8197F) +#define BITS_SYSON_REG_ARB_8197F (BIT_MASK_SYSON_REG_ARB_8197F << BIT_SHIFT_SYSON_REG_ARB_8197F) +#define BIT_CLEAR_SYSON_REG_ARB_8197F(x) ((x) & (~BITS_SYSON_REG_ARB_8197F)) +#define BIT_GET_SYSON_REG_ARB_8197F(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8197F) & BIT_MASK_SYSON_REG_ARB_8197F) +#define BIT_SET_SYSON_REG_ARB_8197F(x, v) (BIT_CLEAR_SYSON_REG_ARB_8197F(x) | BIT_SYSON_REG_ARB_8197F(v)) + + +/* 2 REG_BIST_CTRL_8197F */ +#define BIT_BIST_USB_DIS_8197F BIT(27) +#define BIT_BIST_PCI_DIS_8197F BIT(26) +#define BIT_BIST_BT_DIS_8197F BIT(25) +#define BIT_BIST_WL_DIS_8197F BIT(24) + +#define BIT_SHIFT_BIST_RPT_SEL_8197F 16 +#define BIT_MASK_BIST_RPT_SEL_8197F 0xf +#define BIT_BIST_RPT_SEL_8197F(x) (((x) & BIT_MASK_BIST_RPT_SEL_8197F) << BIT_SHIFT_BIST_RPT_SEL_8197F) +#define BITS_BIST_RPT_SEL_8197F (BIT_MASK_BIST_RPT_SEL_8197F << BIT_SHIFT_BIST_RPT_SEL_8197F) +#define BIT_CLEAR_BIST_RPT_SEL_8197F(x) ((x) & (~BITS_BIST_RPT_SEL_8197F)) +#define BIT_GET_BIST_RPT_SEL_8197F(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8197F) & BIT_MASK_BIST_RPT_SEL_8197F) +#define BIT_SET_BIST_RPT_SEL_8197F(x, v) (BIT_CLEAR_BIST_RPT_SEL_8197F(x) | BIT_BIST_RPT_SEL_8197F(v)) + +#define BIT_BIST_RESUME_PS_8197F BIT(4) +#define BIT_BIST_RESUME_8197F BIT(3) +#define BIT_BIST_NORMAL_8197F BIT(2) +#define BIT_BIST_RSTN_8197F BIT(1) +#define BIT_BIST_CLK_EN_8197F BIT(0) + +/* 2 REG_BIST_RPT_8197F */ + +#define BIT_SHIFT_MBIST_REPORT_8197F 0 +#define BIT_MASK_MBIST_REPORT_8197F 0xffffffffL +#define BIT_MBIST_REPORT_8197F(x) (((x) & BIT_MASK_MBIST_REPORT_8197F) << BIT_SHIFT_MBIST_REPORT_8197F) +#define BITS_MBIST_REPORT_8197F (BIT_MASK_MBIST_REPORT_8197F << BIT_SHIFT_MBIST_REPORT_8197F) +#define BIT_CLEAR_MBIST_REPORT_8197F(x) ((x) & (~BITS_MBIST_REPORT_8197F)) +#define BIT_GET_MBIST_REPORT_8197F(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8197F) & BIT_MASK_MBIST_REPORT_8197F) +#define BIT_SET_MBIST_REPORT_8197F(x, v) (BIT_CLEAR_MBIST_REPORT_8197F(x) | BIT_MBIST_REPORT_8197F(v)) + + +/* 2 REG_MEM_CTRL_8197F */ +#define BIT_UMEM_RME_8197F BIT(31) + +#define BIT_SHIFT_BT_SPRAM_8197F 28 +#define BIT_MASK_BT_SPRAM_8197F 0x3 +#define BIT_BT_SPRAM_8197F(x) (((x) & BIT_MASK_BT_SPRAM_8197F) << BIT_SHIFT_BT_SPRAM_8197F) +#define BITS_BT_SPRAM_8197F (BIT_MASK_BT_SPRAM_8197F << BIT_SHIFT_BT_SPRAM_8197F) +#define BIT_CLEAR_BT_SPRAM_8197F(x) ((x) & (~BITS_BT_SPRAM_8197F)) +#define BIT_GET_BT_SPRAM_8197F(x) (((x) >> BIT_SHIFT_BT_SPRAM_8197F) & BIT_MASK_BT_SPRAM_8197F) +#define BIT_SET_BT_SPRAM_8197F(x, v) (BIT_CLEAR_BT_SPRAM_8197F(x) | BIT_BT_SPRAM_8197F(v)) + + +#define BIT_SHIFT_BT_ROM_8197F 24 +#define BIT_MASK_BT_ROM_8197F 0xf +#define BIT_BT_ROM_8197F(x) (((x) & BIT_MASK_BT_ROM_8197F) << BIT_SHIFT_BT_ROM_8197F) +#define BITS_BT_ROM_8197F (BIT_MASK_BT_ROM_8197F << BIT_SHIFT_BT_ROM_8197F) +#define BIT_CLEAR_BT_ROM_8197F(x) ((x) & (~BITS_BT_ROM_8197F)) +#define BIT_GET_BT_ROM_8197F(x) (((x) >> BIT_SHIFT_BT_ROM_8197F) & BIT_MASK_BT_ROM_8197F) +#define BIT_SET_BT_ROM_8197F(x, v) (BIT_CLEAR_BT_ROM_8197F(x) | BIT_BT_ROM_8197F(v)) + + +#define BIT_SHIFT_PCI_DPRAM_8197F 10 +#define BIT_MASK_PCI_DPRAM_8197F 0x3 +#define BIT_PCI_DPRAM_8197F(x) (((x) & BIT_MASK_PCI_DPRAM_8197F) << BIT_SHIFT_PCI_DPRAM_8197F) +#define BITS_PCI_DPRAM_8197F (BIT_MASK_PCI_DPRAM_8197F << BIT_SHIFT_PCI_DPRAM_8197F) +#define BIT_CLEAR_PCI_DPRAM_8197F(x) ((x) & (~BITS_PCI_DPRAM_8197F)) +#define BIT_GET_PCI_DPRAM_8197F(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8197F) & BIT_MASK_PCI_DPRAM_8197F) +#define BIT_SET_PCI_DPRAM_8197F(x, v) (BIT_CLEAR_PCI_DPRAM_8197F(x) | BIT_PCI_DPRAM_8197F(v)) + + +#define BIT_SHIFT_PCI_SPRAM_8197F 8 +#define BIT_MASK_PCI_SPRAM_8197F 0x3 +#define BIT_PCI_SPRAM_8197F(x) (((x) & BIT_MASK_PCI_SPRAM_8197F) << BIT_SHIFT_PCI_SPRAM_8197F) +#define BITS_PCI_SPRAM_8197F (BIT_MASK_PCI_SPRAM_8197F << BIT_SHIFT_PCI_SPRAM_8197F) +#define BIT_CLEAR_PCI_SPRAM_8197F(x) ((x) & (~BITS_PCI_SPRAM_8197F)) +#define BIT_GET_PCI_SPRAM_8197F(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8197F) & BIT_MASK_PCI_SPRAM_8197F) +#define BIT_SET_PCI_SPRAM_8197F(x, v) (BIT_CLEAR_PCI_SPRAM_8197F(x) | BIT_PCI_SPRAM_8197F(v)) + + +#define BIT_SHIFT_USB_SPRAM_8197F 6 +#define BIT_MASK_USB_SPRAM_8197F 0x3 +#define BIT_USB_SPRAM_8197F(x) (((x) & BIT_MASK_USB_SPRAM_8197F) << BIT_SHIFT_USB_SPRAM_8197F) +#define BITS_USB_SPRAM_8197F (BIT_MASK_USB_SPRAM_8197F << BIT_SHIFT_USB_SPRAM_8197F) +#define BIT_CLEAR_USB_SPRAM_8197F(x) ((x) & (~BITS_USB_SPRAM_8197F)) +#define BIT_GET_USB_SPRAM_8197F(x) (((x) >> BIT_SHIFT_USB_SPRAM_8197F) & BIT_MASK_USB_SPRAM_8197F) +#define BIT_SET_USB_SPRAM_8197F(x, v) (BIT_CLEAR_USB_SPRAM_8197F(x) | BIT_USB_SPRAM_8197F(v)) + + +#define BIT_SHIFT_USB_SPRF_8197F 4 +#define BIT_MASK_USB_SPRF_8197F 0x3 +#define BIT_USB_SPRF_8197F(x) (((x) & BIT_MASK_USB_SPRF_8197F) << BIT_SHIFT_USB_SPRF_8197F) +#define BITS_USB_SPRF_8197F (BIT_MASK_USB_SPRF_8197F << BIT_SHIFT_USB_SPRF_8197F) +#define BIT_CLEAR_USB_SPRF_8197F(x) ((x) & (~BITS_USB_SPRF_8197F)) +#define BIT_GET_USB_SPRF_8197F(x) (((x) >> BIT_SHIFT_USB_SPRF_8197F) & BIT_MASK_USB_SPRF_8197F) +#define BIT_SET_USB_SPRF_8197F(x, v) (BIT_CLEAR_USB_SPRF_8197F(x) | BIT_USB_SPRF_8197F(v)) + + +#define BIT_SHIFT_MCU_ROM_8197F 0 +#define BIT_MASK_MCU_ROM_8197F 0xf +#define BIT_MCU_ROM_8197F(x) (((x) & BIT_MASK_MCU_ROM_8197F) << BIT_SHIFT_MCU_ROM_8197F) +#define BITS_MCU_ROM_8197F (BIT_MASK_MCU_ROM_8197F << BIT_SHIFT_MCU_ROM_8197F) +#define BIT_CLEAR_MCU_ROM_8197F(x) ((x) & (~BITS_MCU_ROM_8197F)) +#define BIT_GET_MCU_ROM_8197F(x) (((x) >> BIT_SHIFT_MCU_ROM_8197F) & BIT_MASK_MCU_ROM_8197F) +#define BIT_SET_MCU_ROM_8197F(x, v) (BIT_CLEAR_MCU_ROM_8197F(x) | BIT_MCU_ROM_8197F(v)) + + +/* 2 REG_AFE_CTRL8_8197F */ + +#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F 26 +#define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F 0x7 +#define BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) +#define BITS_BB_DBG_SEL_AFE_SDM_V4_8197F (BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4_8197F)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4_8197F(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4_8197F(x, v) (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) | BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(v)) + +#define BIT_SYN_AGPIO_8197F BIT(20) + +#define BIT_SHIFT_XTAL_SEL_TOK_V2_8197F 0 +#define BIT_MASK_XTAL_SEL_TOK_V2_8197F 0x7 +#define BIT_XTAL_SEL_TOK_V2_8197F(x) (((x) & BIT_MASK_XTAL_SEL_TOK_V2_8197F) << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) +#define BITS_XTAL_SEL_TOK_V2_8197F (BIT_MASK_XTAL_SEL_TOK_V2_8197F << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) +#define BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) ((x) & (~BITS_XTAL_SEL_TOK_V2_8197F)) +#define BIT_GET_XTAL_SEL_TOK_V2_8197F(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) & BIT_MASK_XTAL_SEL_TOK_V2_8197F) +#define BIT_SET_XTAL_SEL_TOK_V2_8197F(x, v) (BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) | BIT_XTAL_SEL_TOK_V2_8197F(v)) + + +/* 2 REG_USB_SIE_INTF_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_PCIE_MIO_INTF_8197F */ +#define BIT_PCIE_MIO_BYIOREG_8197F BIT(13) +#define BIT_PCIE_MIO_RE_8197F BIT(12) + +#define BIT_SHIFT_PCIE_MIO_WE_8197F 8 +#define BIT_MASK_PCIE_MIO_WE_8197F 0xf +#define BIT_PCIE_MIO_WE_8197F(x) (((x) & BIT_MASK_PCIE_MIO_WE_8197F) << BIT_SHIFT_PCIE_MIO_WE_8197F) +#define BITS_PCIE_MIO_WE_8197F (BIT_MASK_PCIE_MIO_WE_8197F << BIT_SHIFT_PCIE_MIO_WE_8197F) +#define BIT_CLEAR_PCIE_MIO_WE_8197F(x) ((x) & (~BITS_PCIE_MIO_WE_8197F)) +#define BIT_GET_PCIE_MIO_WE_8197F(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8197F) & BIT_MASK_PCIE_MIO_WE_8197F) +#define BIT_SET_PCIE_MIO_WE_8197F(x, v) (BIT_CLEAR_PCIE_MIO_WE_8197F(x) | BIT_PCIE_MIO_WE_8197F(v)) + + +#define BIT_SHIFT_PCIE_MIO_ADDR_8197F 0 +#define BIT_MASK_PCIE_MIO_ADDR_8197F 0xff +#define BIT_PCIE_MIO_ADDR_8197F(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8197F) << BIT_SHIFT_PCIE_MIO_ADDR_8197F) +#define BITS_PCIE_MIO_ADDR_8197F (BIT_MASK_PCIE_MIO_ADDR_8197F << BIT_SHIFT_PCIE_MIO_ADDR_8197F) +#define BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) ((x) & (~BITS_PCIE_MIO_ADDR_8197F)) +#define BIT_GET_PCIE_MIO_ADDR_8197F(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8197F) & BIT_MASK_PCIE_MIO_ADDR_8197F) +#define BIT_SET_PCIE_MIO_ADDR_8197F(x, v) (BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) | BIT_PCIE_MIO_ADDR_8197F(v)) + + +/* 2 REG_PCIE_MIO_INTD_8197F */ + +#define BIT_SHIFT_PCIE_MIO_DATA_8197F 0 +#define BIT_MASK_PCIE_MIO_DATA_8197F 0xffffffffL +#define BIT_PCIE_MIO_DATA_8197F(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8197F) << BIT_SHIFT_PCIE_MIO_DATA_8197F) +#define BITS_PCIE_MIO_DATA_8197F (BIT_MASK_PCIE_MIO_DATA_8197F << BIT_SHIFT_PCIE_MIO_DATA_8197F) +#define BIT_CLEAR_PCIE_MIO_DATA_8197F(x) ((x) & (~BITS_PCIE_MIO_DATA_8197F)) +#define BIT_GET_PCIE_MIO_DATA_8197F(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8197F) & BIT_MASK_PCIE_MIO_DATA_8197F) +#define BIT_SET_PCIE_MIO_DATA_8197F(x, v) (BIT_CLEAR_PCIE_MIO_DATA_8197F(x) | BIT_PCIE_MIO_DATA_8197F(v)) + + +/* 2 REG_WLRF1_8197F */ + +/* 2 REG_SYS_CFG1_8197F */ + +#define BIT_SHIFT_TRP_ICFG_8197F 28 +#define BIT_MASK_TRP_ICFG_8197F 0xf +#define BIT_TRP_ICFG_8197F(x) (((x) & BIT_MASK_TRP_ICFG_8197F) << BIT_SHIFT_TRP_ICFG_8197F) +#define BITS_TRP_ICFG_8197F (BIT_MASK_TRP_ICFG_8197F << BIT_SHIFT_TRP_ICFG_8197F) +#define BIT_CLEAR_TRP_ICFG_8197F(x) ((x) & (~BITS_TRP_ICFG_8197F)) +#define BIT_GET_TRP_ICFG_8197F(x) (((x) >> BIT_SHIFT_TRP_ICFG_8197F) & BIT_MASK_TRP_ICFG_8197F) +#define BIT_SET_TRP_ICFG_8197F(x, v) (BIT_CLEAR_TRP_ICFG_8197F(x) | BIT_TRP_ICFG_8197F(v)) + +#define BIT_RF_TYPE_ID_8197F BIT(27) +#define BIT_BD_HCI_SEL_8197F BIT(26) +#define BIT_BD_PKG_SEL_8197F BIT(25) +#define BIT_SPSLDO_SEL_8197F BIT(24) +#define BIT_RTL_ID_8197F BIT(23) +#define BIT_PAD_HWPD_IDN_8197F BIT(22) +#define BIT_TESTMODE_8197F BIT(20) + +#define BIT_SHIFT_VENDOR_ID_8197F 16 +#define BIT_MASK_VENDOR_ID_8197F 0xf +#define BIT_VENDOR_ID_8197F(x) (((x) & BIT_MASK_VENDOR_ID_8197F) << BIT_SHIFT_VENDOR_ID_8197F) +#define BITS_VENDOR_ID_8197F (BIT_MASK_VENDOR_ID_8197F << BIT_SHIFT_VENDOR_ID_8197F) +#define BIT_CLEAR_VENDOR_ID_8197F(x) ((x) & (~BITS_VENDOR_ID_8197F)) +#define BIT_GET_VENDOR_ID_8197F(x) (((x) >> BIT_SHIFT_VENDOR_ID_8197F) & BIT_MASK_VENDOR_ID_8197F) +#define BIT_SET_VENDOR_ID_8197F(x, v) (BIT_CLEAR_VENDOR_ID_8197F(x) | BIT_VENDOR_ID_8197F(v)) + + +#define BIT_SHIFT_CHIP_VER_8197F 12 +#define BIT_MASK_CHIP_VER_8197F 0xf +#define BIT_CHIP_VER_8197F(x) (((x) & BIT_MASK_CHIP_VER_8197F) << BIT_SHIFT_CHIP_VER_8197F) +#define BITS_CHIP_VER_8197F (BIT_MASK_CHIP_VER_8197F << BIT_SHIFT_CHIP_VER_8197F) +#define BIT_CLEAR_CHIP_VER_8197F(x) ((x) & (~BITS_CHIP_VER_8197F)) +#define BIT_GET_CHIP_VER_8197F(x) (((x) >> BIT_SHIFT_CHIP_VER_8197F) & BIT_MASK_CHIP_VER_8197F) +#define BIT_SET_CHIP_VER_8197F(x, v) (BIT_CLEAR_CHIP_VER_8197F(x) | BIT_CHIP_VER_8197F(v)) + +#define BIT_BD_MAC1_8197F BIT(10) +#define BIT_BD_MAC2_8197F BIT(9) +#define BIT_SIC_IDLE_8197F BIT(8) +#define BIT_SW_OFFLOAD_EN_8197F BIT(7) +#define BIT_OCP_SHUTDN_8197F BIT(6) +#define BIT_V15_VLD_8197F BIT(5) +#define BIT_PCIRSTB_8197F BIT(4) +#define BIT_PCLK_VLD_8197F BIT(3) +#define BIT_UCLK_VLD_8197F BIT(2) +#define BIT_ACLK_VLD_8197F BIT(1) +#define BIT_XCLK_VLD_8197F BIT(0) + +/* 2 REG_SYS_STATUS1_8197F */ + +#define BIT_SHIFT_RF_RL_ID_8197F 28 +#define BIT_MASK_RF_RL_ID_8197F 0xf +#define BIT_RF_RL_ID_8197F(x) (((x) & BIT_MASK_RF_RL_ID_8197F) << BIT_SHIFT_RF_RL_ID_8197F) +#define BITS_RF_RL_ID_8197F (BIT_MASK_RF_RL_ID_8197F << BIT_SHIFT_RF_RL_ID_8197F) +#define BIT_CLEAR_RF_RL_ID_8197F(x) ((x) & (~BITS_RF_RL_ID_8197F)) +#define BIT_GET_RF_RL_ID_8197F(x) (((x) >> BIT_SHIFT_RF_RL_ID_8197F) & BIT_MASK_RF_RL_ID_8197F) +#define BIT_SET_RF_RL_ID_8197F(x, v) (BIT_CLEAR_RF_RL_ID_8197F(x) | BIT_RF_RL_ID_8197F(v)) + +#define BIT_HPHY_ICFG_8197F BIT(19) + +#define BIT_SHIFT_SEL_0XC0_8197F 16 +#define BIT_MASK_SEL_0XC0_8197F 0x3 +#define BIT_SEL_0XC0_8197F(x) (((x) & BIT_MASK_SEL_0XC0_8197F) << BIT_SHIFT_SEL_0XC0_8197F) +#define BITS_SEL_0XC0_8197F (BIT_MASK_SEL_0XC0_8197F << BIT_SHIFT_SEL_0XC0_8197F) +#define BIT_CLEAR_SEL_0XC0_8197F(x) ((x) & (~BITS_SEL_0XC0_8197F)) +#define BIT_GET_SEL_0XC0_8197F(x) (((x) >> BIT_SHIFT_SEL_0XC0_8197F) & BIT_MASK_SEL_0XC0_8197F) +#define BIT_SET_SEL_0XC0_8197F(x, v) (BIT_CLEAR_SEL_0XC0_8197F(x) | BIT_SEL_0XC0_8197F(v)) + +#define BIT_USB_OPERATION_MODE_8197F BIT(10) +#define BIT_BT_PDN_8197F BIT(9) +#define BIT_AUTO_WLPON_8197F BIT(8) +#define BIT_WL_MODE_8197F BIT(7) +#define BIT_PKG_SEL_HCI_8197F BIT(6) + +#define BIT_SHIFT_HCI_SEL_8197F 4 +#define BIT_MASK_HCI_SEL_8197F 0x3 +#define BIT_HCI_SEL_8197F(x) (((x) & BIT_MASK_HCI_SEL_8197F) << BIT_SHIFT_HCI_SEL_8197F) +#define BITS_HCI_SEL_8197F (BIT_MASK_HCI_SEL_8197F << BIT_SHIFT_HCI_SEL_8197F) +#define BIT_CLEAR_HCI_SEL_8197F(x) ((x) & (~BITS_HCI_SEL_8197F)) +#define BIT_GET_HCI_SEL_8197F(x) (((x) >> BIT_SHIFT_HCI_SEL_8197F) & BIT_MASK_HCI_SEL_8197F) +#define BIT_SET_HCI_SEL_8197F(x, v) (BIT_CLEAR_HCI_SEL_8197F(x) | BIT_HCI_SEL_8197F(v)) + + +#define BIT_SHIFT_PAD_HCI_SEL_8197F 2 +#define BIT_MASK_PAD_HCI_SEL_8197F 0x3 +#define BIT_PAD_HCI_SEL_8197F(x) (((x) & BIT_MASK_PAD_HCI_SEL_8197F) << BIT_SHIFT_PAD_HCI_SEL_8197F) +#define BITS_PAD_HCI_SEL_8197F (BIT_MASK_PAD_HCI_SEL_8197F << BIT_SHIFT_PAD_HCI_SEL_8197F) +#define BIT_CLEAR_PAD_HCI_SEL_8197F(x) ((x) & (~BITS_PAD_HCI_SEL_8197F)) +#define BIT_GET_PAD_HCI_SEL_8197F(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_8197F) & BIT_MASK_PAD_HCI_SEL_8197F) +#define BIT_SET_PAD_HCI_SEL_8197F(x, v) (BIT_CLEAR_PAD_HCI_SEL_8197F(x) | BIT_PAD_HCI_SEL_8197F(v)) + + +#define BIT_SHIFT_EFS_HCI_SEL_8197F 0 +#define BIT_MASK_EFS_HCI_SEL_8197F 0x3 +#define BIT_EFS_HCI_SEL_8197F(x) (((x) & BIT_MASK_EFS_HCI_SEL_8197F) << BIT_SHIFT_EFS_HCI_SEL_8197F) +#define BITS_EFS_HCI_SEL_8197F (BIT_MASK_EFS_HCI_SEL_8197F << BIT_SHIFT_EFS_HCI_SEL_8197F) +#define BIT_CLEAR_EFS_HCI_SEL_8197F(x) ((x) & (~BITS_EFS_HCI_SEL_8197F)) +#define BIT_GET_EFS_HCI_SEL_8197F(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_8197F) & BIT_MASK_EFS_HCI_SEL_8197F) +#define BIT_SET_EFS_HCI_SEL_8197F(x, v) (BIT_CLEAR_EFS_HCI_SEL_8197F(x) | BIT_EFS_HCI_SEL_8197F(v)) + + +/* 2 REG_SYS_STATUS2_8197F */ +#define BIT_SIO_ALDN_8197F BIT(19) +#define BIT_USB_ALDN_8197F BIT(18) +#define BIT_PCI_ALDN_8197F BIT(17) +#define BIT_SYS_ALDN_8197F BIT(16) + +#define BIT_SHIFT_EPVID1_8197F 8 +#define BIT_MASK_EPVID1_8197F 0xff +#define BIT_EPVID1_8197F(x) (((x) & BIT_MASK_EPVID1_8197F) << BIT_SHIFT_EPVID1_8197F) +#define BITS_EPVID1_8197F (BIT_MASK_EPVID1_8197F << BIT_SHIFT_EPVID1_8197F) +#define BIT_CLEAR_EPVID1_8197F(x) ((x) & (~BITS_EPVID1_8197F)) +#define BIT_GET_EPVID1_8197F(x) (((x) >> BIT_SHIFT_EPVID1_8197F) & BIT_MASK_EPVID1_8197F) +#define BIT_SET_EPVID1_8197F(x, v) (BIT_CLEAR_EPVID1_8197F(x) | BIT_EPVID1_8197F(v)) + + +#define BIT_SHIFT_EPVID0_8197F 0 +#define BIT_MASK_EPVID0_8197F 0xff +#define BIT_EPVID0_8197F(x) (((x) & BIT_MASK_EPVID0_8197F) << BIT_SHIFT_EPVID0_8197F) +#define BITS_EPVID0_8197F (BIT_MASK_EPVID0_8197F << BIT_SHIFT_EPVID0_8197F) +#define BIT_CLEAR_EPVID0_8197F(x) ((x) & (~BITS_EPVID0_8197F)) +#define BIT_GET_EPVID0_8197F(x) (((x) >> BIT_SHIFT_EPVID0_8197F) & BIT_MASK_EPVID0_8197F) +#define BIT_SET_EPVID0_8197F(x, v) (BIT_CLEAR_EPVID0_8197F(x) | BIT_EPVID0_8197F(v)) + + +/* 2 REG_SYS_CFG2_8197F */ + +#define BIT_SHIFT_HW_ID_8197F 0 +#define BIT_MASK_HW_ID_8197F 0xff +#define BIT_HW_ID_8197F(x) (((x) & BIT_MASK_HW_ID_8197F) << BIT_SHIFT_HW_ID_8197F) +#define BITS_HW_ID_8197F (BIT_MASK_HW_ID_8197F << BIT_SHIFT_HW_ID_8197F) +#define BIT_CLEAR_HW_ID_8197F(x) ((x) & (~BITS_HW_ID_8197F)) +#define BIT_GET_HW_ID_8197F(x) (((x) >> BIT_SHIFT_HW_ID_8197F) & BIT_MASK_HW_ID_8197F) +#define BIT_SET_HW_ID_8197F(x, v) (BIT_CLEAR_HW_ID_8197F(x) | BIT_HW_ID_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_SYS_CFG3_8197F */ + +/* 2 REG_SYS_CFG4_8197F */ + +/* 2 REG_CPU_DMEM_CON_8197F */ +#define BIT_ANA_PORT_IDLE_8197F BIT(18) +#define BIT_MAC_PORT_IDLE_8197F BIT(17) +#define BIT_WL_PLATFORM_RST_8197F BIT(16) +#define BIT_WL_SECURITY_CLK_8197F BIT(15) + +#define BIT_SHIFT_CPU_DMEM_CON_8197F 0 +#define BIT_MASK_CPU_DMEM_CON_8197F 0xff +#define BIT_CPU_DMEM_CON_8197F(x) (((x) & BIT_MASK_CPU_DMEM_CON_8197F) << BIT_SHIFT_CPU_DMEM_CON_8197F) +#define BITS_CPU_DMEM_CON_8197F (BIT_MASK_CPU_DMEM_CON_8197F << BIT_SHIFT_CPU_DMEM_CON_8197F) +#define BIT_CLEAR_CPU_DMEM_CON_8197F(x) ((x) & (~BITS_CPU_DMEM_CON_8197F)) +#define BIT_GET_CPU_DMEM_CON_8197F(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8197F) & BIT_MASK_CPU_DMEM_CON_8197F) +#define BIT_SET_CPU_DMEM_CON_8197F(x, v) (BIT_CLEAR_CPU_DMEM_CON_8197F(x) | BIT_CPU_DMEM_CON_8197F(v)) + + +/* 2 REG_HIMR2_8197F */ +#define BIT_BCNDMAINT_P4_MSK_8197F BIT(31) +#define BIT_BCNDMAINT_P3_MSK_8197F BIT(30) +#define BIT_BCNDMAINT_P2_MSK_8197F BIT(29) +#define BIT_BCNDMAINT_P1_MSK_8197F BIT(28) +#define BIT_ATIMEND7_MSK_8197F BIT(22) +#define BIT_ATIMEND6_MSK_8197F BIT(21) +#define BIT_ATIMEND5_MSK_8197F BIT(20) +#define BIT_ATIMEND4_MSK_8197F BIT(19) +#define BIT_ATIMEND3_MSK_8197F BIT(18) +#define BIT_ATIMEND2_MSK_8197F BIT(17) +#define BIT_ATIMEND1_MSK_8197F BIT(16) +#define BIT_TXBCN7OK_MSK_8197F BIT(14) +#define BIT_TXBCN6OK_MSK_8197F BIT(13) +#define BIT_TXBCN5OK_MSK_8197F BIT(12) +#define BIT_TXBCN4OK_MSK_8197F BIT(11) +#define BIT_TXBCN3OK_MSK_8197F BIT(10) +#define BIT_TXBCN2OK_MSK_8197F BIT(9) +#define BIT_TXBCN1OK_MSK_V1_8197F BIT(8) +#define BIT_TXBCN7ERR_MSK_8197F BIT(6) +#define BIT_TXBCN6ERR_MSK_8197F BIT(5) +#define BIT_TXBCN5ERR_MSK_8197F BIT(4) +#define BIT_TXBCN4ERR_MSK_8197F BIT(3) +#define BIT_TXBCN3ERR_MSK_8197F BIT(2) +#define BIT_TXBCN2ERR_MSK_8197F BIT(1) +#define BIT_TXBCN1ERR_MSK_V1_8197F BIT(0) + +/* 2 REG_HISR2_8197F */ +#define BIT_BCNDMAINT_P4_8197F BIT(31) +#define BIT_BCNDMAINT_P3_8197F BIT(30) +#define BIT_BCNDMAINT_P2_8197F BIT(29) +#define BIT_BCNDMAINT_P1_8197F BIT(28) +#define BIT_ATIMEND7_8197F BIT(22) +#define BIT_ATIMEND6_8197F BIT(21) +#define BIT_ATIMEND5_8197F BIT(20) +#define BIT_ATIMEND4_8197F BIT(19) +#define BIT_ATIMEND3_8197F BIT(18) +#define BIT_ATIMEND2_8197F BIT(17) +#define BIT_ATIMEND1_8197F BIT(16) +#define BIT_TXBCN7OK_8197F BIT(14) +#define BIT_TXBCN6OK_8197F BIT(13) +#define BIT_TXBCN5OK_8197F BIT(12) +#define BIT_TXBCN4OK_8197F BIT(11) +#define BIT_TXBCN3OK_8197F BIT(10) +#define BIT_TXBCN2OK_8197F BIT(9) +#define BIT_TXBCN1OK_8197F BIT(8) +#define BIT_TXBCN7ERR_8197F BIT(6) +#define BIT_TXBCN6ERR_8197F BIT(5) +#define BIT_TXBCN5ERR_8197F BIT(4) +#define BIT_TXBCN4ERR_8197F BIT(3) +#define BIT_TXBCN3ERR_8197F BIT(2) +#define BIT_TXBCN2ERR_8197F BIT(1) +#define BIT_TXBCN1ERR_8197F BIT(0) + +/* 2 REG_HIMR3_8197F */ +#define BIT_SETH2CDOK_MASK_8197F BIT(16) +#define BIT_H2C_CMD_FULL_MASK_8197F BIT(15) +#define BIT_PWR_INT_127_MASK_8197F BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8197F BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8197F BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8197F BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8197F BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8197F BIT(9) +#define BIT_PWR_INT_127_MASK_V1_8197F BIT(8) +#define BIT_PWR_INT_126TO96_MASK_8197F BIT(7) +#define BIT_PWR_INT_95TO64_MASK_8197F BIT(6) +#define BIT_PWR_INT_63TO32_MASK_8197F BIT(5) +#define BIT_PWR_INT_31TO0_MASK_8197F BIT(4) +#define BIT_DDMA0_LP_INT_MSK_8197F BIT(1) +#define BIT_DDMA0_HP_INT_MSK_8197F BIT(0) + +/* 2 REG_HISR3_8197F */ +#define BIT_SETH2CDOK_8197F BIT(16) +#define BIT_H2C_CMD_FULL_8197F BIT(15) +#define BIT_PWR_INT_127_8197F BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_8197F BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_8197F BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_8197F BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_8197F BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_8197F BIT(9) +#define BIT_PWR_INT_127_V1_8197F BIT(8) +#define BIT_PWR_INT_126TO96_8197F BIT(7) +#define BIT_PWR_INT_95TO64_8197F BIT(6) +#define BIT_PWR_INT_63TO32_8197F BIT(5) +#define BIT_PWR_INT_31TO0_8197F BIT(4) +#define BIT_DDMA0_LP_INT_8197F BIT(1) +#define BIT_DDMA0_HP_INT_8197F BIT(0) + +/* 2 REG_SW_MDIO_8197F */ + +/* 2 REG_SW_FLUSH_8197F */ +#define BIT_FLUSH_HOLDN_EN_8197F BIT(25) +#define BIT_FLUSH_WR_EN_8197F BIT(24) +#define BIT_SW_FLASH_CONTROL_8197F BIT(23) +#define BIT_SW_FLASH_WEN_E_8197F BIT(19) +#define BIT_SW_FLASH_HOLDN_E_8197F BIT(18) +#define BIT_SW_FLASH_SO_E_8197F BIT(17) +#define BIT_SW_FLASH_SI_E_8197F BIT(16) +#define BIT_SW_FLASH_SK_O_8197F BIT(13) +#define BIT_SW_FLASH_CEN_O_8197F BIT(12) +#define BIT_SW_FLASH_WEN_O_8197F BIT(11) +#define BIT_SW_FLASH_HOLDN_O_8197F BIT(10) +#define BIT_SW_FLASH_SO_O_8197F BIT(9) +#define BIT_SW_FLASH_SI_O_8197F BIT(8) +#define BIT_SW_FLASH_WEN_I_8197F BIT(3) +#define BIT_SW_FLASH_HOLDN_I_8197F BIT(2) +#define BIT_SW_FLASH_SO_I_8197F BIT(1) +#define BIT_SW_FLASH_SI_I_8197F BIT(0) + +/* 2 REG_DBG_GPIO_BMUX_8197F */ + +#define BIT_SHIFT_DBG_GPIO_BMUX_7_8197F 21 +#define BIT_MASK_DBG_GPIO_BMUX_7_8197F 0x7 +#define BIT_DBG_GPIO_BMUX_7_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_7_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) +#define BITS_DBG_GPIO_BMUX_7_8197F (BIT_MASK_DBG_GPIO_BMUX_7_8197F << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) +#define BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_7_8197F)) +#define BIT_GET_DBG_GPIO_BMUX_7_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) & BIT_MASK_DBG_GPIO_BMUX_7_8197F) +#define BIT_SET_DBG_GPIO_BMUX_7_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) | BIT_DBG_GPIO_BMUX_7_8197F(v)) + + +#define BIT_SHIFT_DBG_GPIO_BMUX_6_8197F 18 +#define BIT_MASK_DBG_GPIO_BMUX_6_8197F 0x7 +#define BIT_DBG_GPIO_BMUX_6_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_6_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) +#define BITS_DBG_GPIO_BMUX_6_8197F (BIT_MASK_DBG_GPIO_BMUX_6_8197F << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) +#define BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_6_8197F)) +#define BIT_GET_DBG_GPIO_BMUX_6_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) & BIT_MASK_DBG_GPIO_BMUX_6_8197F) +#define BIT_SET_DBG_GPIO_BMUX_6_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) | BIT_DBG_GPIO_BMUX_6_8197F(v)) + + +#define BIT_SHIFT_DBG_GPIO_BMUX_5_8197F 15 +#define BIT_MASK_DBG_GPIO_BMUX_5_8197F 0x7 +#define BIT_DBG_GPIO_BMUX_5_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_5_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) +#define BITS_DBG_GPIO_BMUX_5_8197F (BIT_MASK_DBG_GPIO_BMUX_5_8197F << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) +#define BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_5_8197F)) +#define BIT_GET_DBG_GPIO_BMUX_5_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) & BIT_MASK_DBG_GPIO_BMUX_5_8197F) +#define BIT_SET_DBG_GPIO_BMUX_5_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) | BIT_DBG_GPIO_BMUX_5_8197F(v)) + + +#define BIT_SHIFT_DBG_GPIO_BMUX_4_8197F 12 +#define BIT_MASK_DBG_GPIO_BMUX_4_8197F 0x7 +#define BIT_DBG_GPIO_BMUX_4_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_4_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) +#define BITS_DBG_GPIO_BMUX_4_8197F (BIT_MASK_DBG_GPIO_BMUX_4_8197F << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) +#define BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_4_8197F)) +#define BIT_GET_DBG_GPIO_BMUX_4_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) & BIT_MASK_DBG_GPIO_BMUX_4_8197F) +#define BIT_SET_DBG_GPIO_BMUX_4_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) | BIT_DBG_GPIO_BMUX_4_8197F(v)) + + +#define BIT_SHIFT_DBG_GPIO_BMUX_3_8197F 9 +#define BIT_MASK_DBG_GPIO_BMUX_3_8197F 0x7 +#define BIT_DBG_GPIO_BMUX_3_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_3_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) +#define BITS_DBG_GPIO_BMUX_3_8197F (BIT_MASK_DBG_GPIO_BMUX_3_8197F << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) +#define BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_3_8197F)) +#define BIT_GET_DBG_GPIO_BMUX_3_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) & BIT_MASK_DBG_GPIO_BMUX_3_8197F) +#define BIT_SET_DBG_GPIO_BMUX_3_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) | BIT_DBG_GPIO_BMUX_3_8197F(v)) + + +#define BIT_SHIFT_DBG_GPIO_BMUX_2_8197F 6 +#define BIT_MASK_DBG_GPIO_BMUX_2_8197F 0x7 +#define BIT_DBG_GPIO_BMUX_2_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_2_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) +#define BITS_DBG_GPIO_BMUX_2_8197F (BIT_MASK_DBG_GPIO_BMUX_2_8197F << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) +#define BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_2_8197F)) +#define BIT_GET_DBG_GPIO_BMUX_2_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) & BIT_MASK_DBG_GPIO_BMUX_2_8197F) +#define BIT_SET_DBG_GPIO_BMUX_2_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) | BIT_DBG_GPIO_BMUX_2_8197F(v)) + + +#define BIT_SHIFT_DBG_GPIO_BMUX_1_8197F 3 +#define BIT_MASK_DBG_GPIO_BMUX_1_8197F 0x7 +#define BIT_DBG_GPIO_BMUX_1_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_1_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) +#define BITS_DBG_GPIO_BMUX_1_8197F (BIT_MASK_DBG_GPIO_BMUX_1_8197F << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) +#define BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_1_8197F)) +#define BIT_GET_DBG_GPIO_BMUX_1_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) & BIT_MASK_DBG_GPIO_BMUX_1_8197F) +#define BIT_SET_DBG_GPIO_BMUX_1_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) | BIT_DBG_GPIO_BMUX_1_8197F(v)) + + +#define BIT_SHIFT_DBG_GPIO_BMUX_0_8197F 0 +#define BIT_MASK_DBG_GPIO_BMUX_0_8197F 0x7 +#define BIT_DBG_GPIO_BMUX_0_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_0_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) +#define BITS_DBG_GPIO_BMUX_0_8197F (BIT_MASK_DBG_GPIO_BMUX_0_8197F << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) +#define BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_0_8197F)) +#define BIT_GET_DBG_GPIO_BMUX_0_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) & BIT_MASK_DBG_GPIO_BMUX_0_8197F) +#define BIT_SET_DBG_GPIO_BMUX_0_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) | BIT_DBG_GPIO_BMUX_0_8197F(v)) + + +/* 2 REG_FPGA_TAG_8197F (NO USE IN ASIC) */ + +#define BIT_SHIFT_FPGA_TAG_8197F 0 +#define BIT_MASK_FPGA_TAG_8197F 0xffffffffL +#define BIT_FPGA_TAG_8197F(x) (((x) & BIT_MASK_FPGA_TAG_8197F) << BIT_SHIFT_FPGA_TAG_8197F) +#define BITS_FPGA_TAG_8197F (BIT_MASK_FPGA_TAG_8197F << BIT_SHIFT_FPGA_TAG_8197F) +#define BIT_CLEAR_FPGA_TAG_8197F(x) ((x) & (~BITS_FPGA_TAG_8197F)) +#define BIT_GET_FPGA_TAG_8197F(x) (((x) >> BIT_SHIFT_FPGA_TAG_8197F) & BIT_MASK_FPGA_TAG_8197F) +#define BIT_SET_FPGA_TAG_8197F(x, v) (BIT_CLEAR_FPGA_TAG_8197F(x) | BIT_FPGA_TAG_8197F(v)) + + +/* 2 REG_WL_DSS_CTRL0_8197F */ +#define BIT_WL_DSS_RSTN_8197F BIT(27) +#define BIT_WL_DSS_EN_CLK_8197F BIT(26) +#define BIT_WL_DSS_SPEED_EN_8197F BIT(25) + +#define BIT_SHIFT_WL_DSS_COUNT_OUT_8197F 0 +#define BIT_MASK_WL_DSS_COUNT_OUT_8197F 0xfffff +#define BIT_WL_DSS_COUNT_OUT_8197F(x) (((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) +#define BITS_WL_DSS_COUNT_OUT_8197F (BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) +#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) ((x) & (~BITS_WL_DSS_COUNT_OUT_8197F)) +#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x) (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) +#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v) (BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v)) + + +/* 2 REG_WL_DSS_CTRL1_8197F */ +#define BIT_WL_DSS_RSTN_8197F BIT(27) +#define BIT_WL_DSS_EN_CLK_8197F BIT(26) +#define BIT_WL_DSS_SPEED_EN_8197F BIT(25) +#define BIT_WL_DSS_WIRE_SEL_8197F BIT(24) + +#define BIT_SHIFT_WL_DSS_RO_SEL_8197F 20 +#define BIT_MASK_WL_DSS_RO_SEL_8197F 0x7 +#define BIT_WL_DSS_RO_SEL_8197F(x) (((x) & BIT_MASK_WL_DSS_RO_SEL_8197F) << BIT_SHIFT_WL_DSS_RO_SEL_8197F) +#define BITS_WL_DSS_RO_SEL_8197F (BIT_MASK_WL_DSS_RO_SEL_8197F << BIT_SHIFT_WL_DSS_RO_SEL_8197F) +#define BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) ((x) & (~BITS_WL_DSS_RO_SEL_8197F)) +#define BIT_GET_WL_DSS_RO_SEL_8197F(x) (((x) >> BIT_SHIFT_WL_DSS_RO_SEL_8197F) & BIT_MASK_WL_DSS_RO_SEL_8197F) +#define BIT_SET_WL_DSS_RO_SEL_8197F(x, v) (BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) | BIT_WL_DSS_RO_SEL_8197F(v)) + + +#define BIT_SHIFT_WL_DSS_DATA_IN_8197F 0 +#define BIT_MASK_WL_DSS_DATA_IN_8197F 0xfffff +#define BIT_WL_DSS_DATA_IN_8197F(x) (((x) & BIT_MASK_WL_DSS_DATA_IN_8197F) << BIT_SHIFT_WL_DSS_DATA_IN_8197F) +#define BITS_WL_DSS_DATA_IN_8197F (BIT_MASK_WL_DSS_DATA_IN_8197F << BIT_SHIFT_WL_DSS_DATA_IN_8197F) +#define BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) ((x) & (~BITS_WL_DSS_DATA_IN_8197F)) +#define BIT_GET_WL_DSS_DATA_IN_8197F(x) (((x) >> BIT_SHIFT_WL_DSS_DATA_IN_8197F) & BIT_MASK_WL_DSS_DATA_IN_8197F) +#define BIT_SET_WL_DSS_DATA_IN_8197F(x, v) (BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) | BIT_WL_DSS_DATA_IN_8197F(v)) + + +/* 2 REG_WL_DSS_STATUS1_8197F */ +#define BIT_WL_DSS_READY_8197F BIT(21) +#define BIT_WL_DSS_WSORT_GO_8197F BIT(20) + +#define BIT_SHIFT_WL_DSS_COUNT_OUT_8197F 0 +#define BIT_MASK_WL_DSS_COUNT_OUT_8197F 0xfffff +#define BIT_WL_DSS_COUNT_OUT_8197F(x) (((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) +#define BITS_WL_DSS_COUNT_OUT_8197F (BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) +#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) ((x) & (~BITS_WL_DSS_COUNT_OUT_8197F)) +#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x) (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) +#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v) (BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v)) + + +/* 2 REG_FW_DBG0_8197F */ + +#define BIT_SHIFT_FW_DBG0_8197F 0 +#define BIT_MASK_FW_DBG0_8197F 0xffffffffL +#define BIT_FW_DBG0_8197F(x) (((x) & BIT_MASK_FW_DBG0_8197F) << BIT_SHIFT_FW_DBG0_8197F) +#define BITS_FW_DBG0_8197F (BIT_MASK_FW_DBG0_8197F << BIT_SHIFT_FW_DBG0_8197F) +#define BIT_CLEAR_FW_DBG0_8197F(x) ((x) & (~BITS_FW_DBG0_8197F)) +#define BIT_GET_FW_DBG0_8197F(x) (((x) >> BIT_SHIFT_FW_DBG0_8197F) & BIT_MASK_FW_DBG0_8197F) +#define BIT_SET_FW_DBG0_8197F(x, v) (BIT_CLEAR_FW_DBG0_8197F(x) | BIT_FW_DBG0_8197F(v)) + + +/* 2 REG_FW_DBG1_8197F */ + +#define BIT_SHIFT_FW_DBG1_8197F 0 +#define BIT_MASK_FW_DBG1_8197F 0xffffffffL +#define BIT_FW_DBG1_8197F(x) (((x) & BIT_MASK_FW_DBG1_8197F) << BIT_SHIFT_FW_DBG1_8197F) +#define BITS_FW_DBG1_8197F (BIT_MASK_FW_DBG1_8197F << BIT_SHIFT_FW_DBG1_8197F) +#define BIT_CLEAR_FW_DBG1_8197F(x) ((x) & (~BITS_FW_DBG1_8197F)) +#define BIT_GET_FW_DBG1_8197F(x) (((x) >> BIT_SHIFT_FW_DBG1_8197F) & BIT_MASK_FW_DBG1_8197F) +#define BIT_SET_FW_DBG1_8197F(x, v) (BIT_CLEAR_FW_DBG1_8197F(x) | BIT_FW_DBG1_8197F(v)) + + +/* 2 REG_FW_DBG2_8197F */ + +#define BIT_SHIFT_FW_DBG2_8197F 0 +#define BIT_MASK_FW_DBG2_8197F 0xffffffffL +#define BIT_FW_DBG2_8197F(x) (((x) & BIT_MASK_FW_DBG2_8197F) << BIT_SHIFT_FW_DBG2_8197F) +#define BITS_FW_DBG2_8197F (BIT_MASK_FW_DBG2_8197F << BIT_SHIFT_FW_DBG2_8197F) +#define BIT_CLEAR_FW_DBG2_8197F(x) ((x) & (~BITS_FW_DBG2_8197F)) +#define BIT_GET_FW_DBG2_8197F(x) (((x) >> BIT_SHIFT_FW_DBG2_8197F) & BIT_MASK_FW_DBG2_8197F) +#define BIT_SET_FW_DBG2_8197F(x, v) (BIT_CLEAR_FW_DBG2_8197F(x) | BIT_FW_DBG2_8197F(v)) + + +/* 2 REG_FW_DBG3_8197F */ + +#define BIT_SHIFT_FW_DBG3_8197F 0 +#define BIT_MASK_FW_DBG3_8197F 0xffffffffL +#define BIT_FW_DBG3_8197F(x) (((x) & BIT_MASK_FW_DBG3_8197F) << BIT_SHIFT_FW_DBG3_8197F) +#define BITS_FW_DBG3_8197F (BIT_MASK_FW_DBG3_8197F << BIT_SHIFT_FW_DBG3_8197F) +#define BIT_CLEAR_FW_DBG3_8197F(x) ((x) & (~BITS_FW_DBG3_8197F)) +#define BIT_GET_FW_DBG3_8197F(x) (((x) >> BIT_SHIFT_FW_DBG3_8197F) & BIT_MASK_FW_DBG3_8197F) +#define BIT_SET_FW_DBG3_8197F(x, v) (BIT_CLEAR_FW_DBG3_8197F(x) | BIT_FW_DBG3_8197F(v)) + + +/* 2 REG_FW_DBG4_8197F */ + +#define BIT_SHIFT_FW_DBG4_8197F 0 +#define BIT_MASK_FW_DBG4_8197F 0xffffffffL +#define BIT_FW_DBG4_8197F(x) (((x) & BIT_MASK_FW_DBG4_8197F) << BIT_SHIFT_FW_DBG4_8197F) +#define BITS_FW_DBG4_8197F (BIT_MASK_FW_DBG4_8197F << BIT_SHIFT_FW_DBG4_8197F) +#define BIT_CLEAR_FW_DBG4_8197F(x) ((x) & (~BITS_FW_DBG4_8197F)) +#define BIT_GET_FW_DBG4_8197F(x) (((x) >> BIT_SHIFT_FW_DBG4_8197F) & BIT_MASK_FW_DBG4_8197F) +#define BIT_SET_FW_DBG4_8197F(x, v) (BIT_CLEAR_FW_DBG4_8197F(x) | BIT_FW_DBG4_8197F(v)) + + +/* 2 REG_FW_DBG5_8197F */ + +#define BIT_SHIFT_FW_DBG5_8197F 0 +#define BIT_MASK_FW_DBG5_8197F 0xffffffffL +#define BIT_FW_DBG5_8197F(x) (((x) & BIT_MASK_FW_DBG5_8197F) << BIT_SHIFT_FW_DBG5_8197F) +#define BITS_FW_DBG5_8197F (BIT_MASK_FW_DBG5_8197F << BIT_SHIFT_FW_DBG5_8197F) +#define BIT_CLEAR_FW_DBG5_8197F(x) ((x) & (~BITS_FW_DBG5_8197F)) +#define BIT_GET_FW_DBG5_8197F(x) (((x) >> BIT_SHIFT_FW_DBG5_8197F) & BIT_MASK_FW_DBG5_8197F) +#define BIT_SET_FW_DBG5_8197F(x, v) (BIT_CLEAR_FW_DBG5_8197F(x) | BIT_FW_DBG5_8197F(v)) + + +/* 2 REG_FW_DBG6_8197F */ + +#define BIT_SHIFT_FW_DBG6_8197F 0 +#define BIT_MASK_FW_DBG6_8197F 0xffffffffL +#define BIT_FW_DBG6_8197F(x) (((x) & BIT_MASK_FW_DBG6_8197F) << BIT_SHIFT_FW_DBG6_8197F) +#define BITS_FW_DBG6_8197F (BIT_MASK_FW_DBG6_8197F << BIT_SHIFT_FW_DBG6_8197F) +#define BIT_CLEAR_FW_DBG6_8197F(x) ((x) & (~BITS_FW_DBG6_8197F)) +#define BIT_GET_FW_DBG6_8197F(x) (((x) >> BIT_SHIFT_FW_DBG6_8197F) & BIT_MASK_FW_DBG6_8197F) +#define BIT_SET_FW_DBG6_8197F(x, v) (BIT_CLEAR_FW_DBG6_8197F(x) | BIT_FW_DBG6_8197F(v)) + + +/* 2 REG_FW_DBG7_8197F */ + +#define BIT_SHIFT_FW_DBG7_8197F 0 +#define BIT_MASK_FW_DBG7_8197F 0xffffffffL +#define BIT_FW_DBG7_8197F(x) (((x) & BIT_MASK_FW_DBG7_8197F) << BIT_SHIFT_FW_DBG7_8197F) +#define BITS_FW_DBG7_8197F (BIT_MASK_FW_DBG7_8197F << BIT_SHIFT_FW_DBG7_8197F) +#define BIT_CLEAR_FW_DBG7_8197F(x) ((x) & (~BITS_FW_DBG7_8197F)) +#define BIT_GET_FW_DBG7_8197F(x) (((x) >> BIT_SHIFT_FW_DBG7_8197F) & BIT_MASK_FW_DBG7_8197F) +#define BIT_SET_FW_DBG7_8197F(x, v) (BIT_CLEAR_FW_DBG7_8197F(x) | BIT_FW_DBG7_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_CR_8197F (ENABLE FUNCTION REGISTER) */ +#define BIT_MACIO_TIMEOUT_EN_8197F BIT(29) + +#define BIT_SHIFT_LBMODE_8197F 24 +#define BIT_MASK_LBMODE_8197F 0x1f +#define BIT_LBMODE_8197F(x) (((x) & BIT_MASK_LBMODE_8197F) << BIT_SHIFT_LBMODE_8197F) +#define BITS_LBMODE_8197F (BIT_MASK_LBMODE_8197F << BIT_SHIFT_LBMODE_8197F) +#define BIT_CLEAR_LBMODE_8197F(x) ((x) & (~BITS_LBMODE_8197F)) +#define BIT_GET_LBMODE_8197F(x) (((x) >> BIT_SHIFT_LBMODE_8197F) & BIT_MASK_LBMODE_8197F) +#define BIT_SET_LBMODE_8197F(x, v) (BIT_CLEAR_LBMODE_8197F(x) | BIT_LBMODE_8197F(v)) + + +#define BIT_SHIFT_NETYPE1_8197F 18 +#define BIT_MASK_NETYPE1_8197F 0x3 +#define BIT_NETYPE1_8197F(x) (((x) & BIT_MASK_NETYPE1_8197F) << BIT_SHIFT_NETYPE1_8197F) +#define BITS_NETYPE1_8197F (BIT_MASK_NETYPE1_8197F << BIT_SHIFT_NETYPE1_8197F) +#define BIT_CLEAR_NETYPE1_8197F(x) ((x) & (~BITS_NETYPE1_8197F)) +#define BIT_GET_NETYPE1_8197F(x) (((x) >> BIT_SHIFT_NETYPE1_8197F) & BIT_MASK_NETYPE1_8197F) +#define BIT_SET_NETYPE1_8197F(x, v) (BIT_CLEAR_NETYPE1_8197F(x) | BIT_NETYPE1_8197F(v)) + + +#define BIT_SHIFT_NETYPE0_8197F 16 +#define BIT_MASK_NETYPE0_8197F 0x3 +#define BIT_NETYPE0_8197F(x) (((x) & BIT_MASK_NETYPE0_8197F) << BIT_SHIFT_NETYPE0_8197F) +#define BITS_NETYPE0_8197F (BIT_MASK_NETYPE0_8197F << BIT_SHIFT_NETYPE0_8197F) +#define BIT_CLEAR_NETYPE0_8197F(x) ((x) & (~BITS_NETYPE0_8197F)) +#define BIT_GET_NETYPE0_8197F(x) (((x) >> BIT_SHIFT_NETYPE0_8197F) & BIT_MASK_NETYPE0_8197F) +#define BIT_SET_NETYPE0_8197F(x, v) (BIT_CLEAR_NETYPE0_8197F(x) | BIT_NETYPE0_8197F(v)) + +#define BIT_STAT_FUNC_RST_8197F BIT(13) +#define BIT_I2C_MAILBOX_EN_8197F BIT(12) +#define BIT_SHCUT_EN_8197F BIT(11) +#define BIT_32K_CAL_TMR_EN_8197F BIT(10) +#define BIT_MAC_SEC_EN_8197F BIT(9) +#define BIT_ENSWBCN_8197F BIT(8) +#define BIT_MACRXEN_8197F BIT(7) +#define BIT_MACTXEN_8197F BIT(6) +#define BIT_SCHEDULE_EN_8197F BIT(5) +#define BIT_PROTOCOL_EN_8197F BIT(4) +#define BIT_RXDMA_EN_8197F BIT(3) +#define BIT_TXDMA_EN_8197F BIT(2) +#define BIT_HCI_RXDMA_EN_8197F BIT(1) +#define BIT_HCI_TXDMA_EN_8197F BIT(0) + +/* 2 REG_TSF_CLK_STATE_8197F */ +#define BIT_TSF_CLK_STABLE_8197F BIT(15) + +/* 2 REG_TXDMA_PQ_MAP_8197F */ + +#define BIT_SHIFT_TXDMA_HIQ_MAP_8197F 14 +#define BIT_MASK_TXDMA_HIQ_MAP_8197F 0x3 +#define BIT_TXDMA_HIQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8197F) << BIT_SHIFT_TXDMA_HIQ_MAP_8197F) +#define BITS_TXDMA_HIQ_MAP_8197F (BIT_MASK_TXDMA_HIQ_MAP_8197F << BIT_SHIFT_TXDMA_HIQ_MAP_8197F) +#define BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8197F)) +#define BIT_GET_TXDMA_HIQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8197F) & BIT_MASK_TXDMA_HIQ_MAP_8197F) +#define BIT_SET_TXDMA_HIQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) | BIT_TXDMA_HIQ_MAP_8197F(v)) + + +#define BIT_SHIFT_TXDMA_MGQ_MAP_8197F 12 +#define BIT_MASK_TXDMA_MGQ_MAP_8197F 0x3 +#define BIT_TXDMA_MGQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8197F) << BIT_SHIFT_TXDMA_MGQ_MAP_8197F) +#define BITS_TXDMA_MGQ_MAP_8197F (BIT_MASK_TXDMA_MGQ_MAP_8197F << BIT_SHIFT_TXDMA_MGQ_MAP_8197F) +#define BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8197F)) +#define BIT_GET_TXDMA_MGQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8197F) & BIT_MASK_TXDMA_MGQ_MAP_8197F) +#define BIT_SET_TXDMA_MGQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) | BIT_TXDMA_MGQ_MAP_8197F(v)) + + +#define BIT_SHIFT_TXDMA_BKQ_MAP_8197F 10 +#define BIT_MASK_TXDMA_BKQ_MAP_8197F 0x3 +#define BIT_TXDMA_BKQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8197F) << BIT_SHIFT_TXDMA_BKQ_MAP_8197F) +#define BITS_TXDMA_BKQ_MAP_8197F (BIT_MASK_TXDMA_BKQ_MAP_8197F << BIT_SHIFT_TXDMA_BKQ_MAP_8197F) +#define BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8197F)) +#define BIT_GET_TXDMA_BKQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8197F) & BIT_MASK_TXDMA_BKQ_MAP_8197F) +#define BIT_SET_TXDMA_BKQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) | BIT_TXDMA_BKQ_MAP_8197F(v)) + + +#define BIT_SHIFT_TXDMA_BEQ_MAP_8197F 8 +#define BIT_MASK_TXDMA_BEQ_MAP_8197F 0x3 +#define BIT_TXDMA_BEQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8197F) << BIT_SHIFT_TXDMA_BEQ_MAP_8197F) +#define BITS_TXDMA_BEQ_MAP_8197F (BIT_MASK_TXDMA_BEQ_MAP_8197F << BIT_SHIFT_TXDMA_BEQ_MAP_8197F) +#define BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8197F)) +#define BIT_GET_TXDMA_BEQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8197F) & BIT_MASK_TXDMA_BEQ_MAP_8197F) +#define BIT_SET_TXDMA_BEQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) | BIT_TXDMA_BEQ_MAP_8197F(v)) + + +#define BIT_SHIFT_TXDMA_VIQ_MAP_8197F 6 +#define BIT_MASK_TXDMA_VIQ_MAP_8197F 0x3 +#define BIT_TXDMA_VIQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8197F) << BIT_SHIFT_TXDMA_VIQ_MAP_8197F) +#define BITS_TXDMA_VIQ_MAP_8197F (BIT_MASK_TXDMA_VIQ_MAP_8197F << BIT_SHIFT_TXDMA_VIQ_MAP_8197F) +#define BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8197F)) +#define BIT_GET_TXDMA_VIQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8197F) & BIT_MASK_TXDMA_VIQ_MAP_8197F) +#define BIT_SET_TXDMA_VIQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) | BIT_TXDMA_VIQ_MAP_8197F(v)) + + +#define BIT_SHIFT_TXDMA_VOQ_MAP_8197F 4 +#define BIT_MASK_TXDMA_VOQ_MAP_8197F 0x3 +#define BIT_TXDMA_VOQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8197F) << BIT_SHIFT_TXDMA_VOQ_MAP_8197F) +#define BITS_TXDMA_VOQ_MAP_8197F (BIT_MASK_TXDMA_VOQ_MAP_8197F << BIT_SHIFT_TXDMA_VOQ_MAP_8197F) +#define BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8197F)) +#define BIT_GET_TXDMA_VOQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8197F) & BIT_MASK_TXDMA_VOQ_MAP_8197F) +#define BIT_SET_TXDMA_VOQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) | BIT_TXDMA_VOQ_MAP_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_RXDMA_AGG_EN_8197F BIT(2) +#define BIT_RXSHFT_EN_8197F BIT(1) +#define BIT_RXDMA_ARBBW_EN_8197F BIT(0) + +/* 2 REG_TRXFF_BNDY_8197F */ + +#define BIT_SHIFT_RXFFOVFL_RSV_V2_8197F 8 +#define BIT_MASK_RXFFOVFL_RSV_V2_8197F 0xf +#define BIT_RXFFOVFL_RSV_V2_8197F(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8197F) << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) +#define BITS_RXFFOVFL_RSV_V2_8197F (BIT_MASK_RXFFOVFL_RSV_V2_8197F << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) +#define BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8197F)) +#define BIT_GET_RXFFOVFL_RSV_V2_8197F(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) & BIT_MASK_RXFFOVFL_RSV_V2_8197F) +#define BIT_SET_RXFFOVFL_RSV_V2_8197F(x, v) (BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) | BIT_RXFFOVFL_RSV_V2_8197F(v)) + + +#define BIT_SHIFT_TXPKTBUF_PGBNDY_8197F 0 +#define BIT_MASK_TXPKTBUF_PGBNDY_8197F 0xff +#define BIT_TXPKTBUF_PGBNDY_8197F(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8197F) << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) +#define BITS_TXPKTBUF_PGBNDY_8197F (BIT_MASK_TXPKTBUF_PGBNDY_8197F << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) +#define BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) ((x) & (~BITS_TXPKTBUF_PGBNDY_8197F)) +#define BIT_GET_TXPKTBUF_PGBNDY_8197F(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) & BIT_MASK_TXPKTBUF_PGBNDY_8197F) +#define BIT_SET_TXPKTBUF_PGBNDY_8197F(x, v) (BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) | BIT_TXPKTBUF_PGBNDY_8197F(v)) + + +/* 2 REG_PTA_I2C_MBOX_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_I2C_M_STATUS_8197F 8 +#define BIT_MASK_I2C_M_STATUS_8197F 0xf +#define BIT_I2C_M_STATUS_8197F(x) (((x) & BIT_MASK_I2C_M_STATUS_8197F) << BIT_SHIFT_I2C_M_STATUS_8197F) +#define BITS_I2C_M_STATUS_8197F (BIT_MASK_I2C_M_STATUS_8197F << BIT_SHIFT_I2C_M_STATUS_8197F) +#define BIT_CLEAR_I2C_M_STATUS_8197F(x) ((x) & (~BITS_I2C_M_STATUS_8197F)) +#define BIT_GET_I2C_M_STATUS_8197F(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8197F) & BIT_MASK_I2C_M_STATUS_8197F) +#define BIT_SET_I2C_M_STATUS_8197F(x, v) (BIT_CLEAR_I2C_M_STATUS_8197F(x) | BIT_I2C_M_STATUS_8197F(v)) + + +#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F 4 +#define BIT_MASK_I2C_M_BUS_GNT_FW_8197F 0x7 +#define BIT_I2C_M_BUS_GNT_FW_8197F(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8197F) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) +#define BITS_I2C_M_BUS_GNT_FW_8197F (BIT_MASK_I2C_M_BUS_GNT_FW_8197F << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) ((x) & (~BITS_I2C_M_BUS_GNT_FW_8197F)) +#define BIT_GET_I2C_M_BUS_GNT_FW_8197F(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) & BIT_MASK_I2C_M_BUS_GNT_FW_8197F) +#define BIT_SET_I2C_M_BUS_GNT_FW_8197F(x, v) (BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) | BIT_I2C_M_BUS_GNT_FW_8197F(v)) + +#define BIT_I2C_M_GNT_FW_8197F BIT(3) + +#define BIT_SHIFT_I2C_M_SPEED_8197F 1 +#define BIT_MASK_I2C_M_SPEED_8197F 0x3 +#define BIT_I2C_M_SPEED_8197F(x) (((x) & BIT_MASK_I2C_M_SPEED_8197F) << BIT_SHIFT_I2C_M_SPEED_8197F) +#define BITS_I2C_M_SPEED_8197F (BIT_MASK_I2C_M_SPEED_8197F << BIT_SHIFT_I2C_M_SPEED_8197F) +#define BIT_CLEAR_I2C_M_SPEED_8197F(x) ((x) & (~BITS_I2C_M_SPEED_8197F)) +#define BIT_GET_I2C_M_SPEED_8197F(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8197F) & BIT_MASK_I2C_M_SPEED_8197F) +#define BIT_SET_I2C_M_SPEED_8197F(x, v) (BIT_CLEAR_I2C_M_SPEED_8197F(x) | BIT_I2C_M_SPEED_8197F(v)) + +#define BIT_I2C_M_UNLOCK_8197F BIT(0) + +/* 2 REG_RXFF_BNDY_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_RXFF0_BNDY_V2_8197F 0 +#define BIT_MASK_RXFF0_BNDY_V2_8197F 0x3ffff +#define BIT_RXFF0_BNDY_V2_8197F(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8197F) << BIT_SHIFT_RXFF0_BNDY_V2_8197F) +#define BITS_RXFF0_BNDY_V2_8197F (BIT_MASK_RXFF0_BNDY_V2_8197F << BIT_SHIFT_RXFF0_BNDY_V2_8197F) +#define BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) ((x) & (~BITS_RXFF0_BNDY_V2_8197F)) +#define BIT_GET_RXFF0_BNDY_V2_8197F(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8197F) & BIT_MASK_RXFF0_BNDY_V2_8197F) +#define BIT_SET_RXFF0_BNDY_V2_8197F(x, v) (BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) | BIT_RXFF0_BNDY_V2_8197F(v)) + + +/* 2 REG_FE1IMR_8197F */ +#define BIT_BB_STOP_RX_INT_EN_8197F BIT(29) +#define BIT_FS_RXDMA2_DONE_INT_EN_8197F BIT(28) +#define BIT_FS_RXDONE3_INT_EN_8197F BIT(27) +#define BIT_FS_RXDONE2_INT_EN_8197F BIT(26) +#define BIT_FS_RX_BCN_P4_INT_EN_8197F BIT(25) +#define BIT_FS_RX_BCN_P3_INT_EN_8197F BIT(24) +#define BIT_FS_RX_BCN_P2_INT_EN_8197F BIT(23) +#define BIT_FS_RX_BCN_P1_INT_EN_8197F BIT(22) +#define BIT_FS_RX_BCN_P0_INT_EN_8197F BIT(21) +#define BIT_FS_RX_UMD0_INT_EN_8197F BIT(20) +#define BIT_FS_RX_UMD1_INT_EN_8197F BIT(19) +#define BIT_FS_RX_BMD0_INT_EN_8197F BIT(18) +#define BIT_FS_RX_BMD1_INT_EN_8197F BIT(17) +#define BIT_FS_RXDONE_INT_EN_8197F BIT(16) +#define BIT_FS_WWLAN_INT_EN_8197F BIT(15) +#define BIT_FS_SOUND_DONE_INT_EN_8197F BIT(14) +#define BIT_FS_LP_STBY_INT_EN_8197F BIT(13) +#define BIT_FS_TRL_MTR_INT_EN_8197F BIT(12) +#define BIT_FS_BF1_PRETO_INT_EN_8197F BIT(11) +#define BIT_FS_BF0_PRETO_INT_EN_8197F BIT(10) +#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8197F BIT(9) +#define BIT_FS_LTE_COEX_EN_8197F BIT(6) +#define BIT_FS_WLACTOFF_INT_EN_8197F BIT(5) +#define BIT_FS_WLACTON_INT_EN_8197F BIT(4) +#define BIT_FS_BTCMD_INT_EN_8197F BIT(3) +#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8197F BIT(2) +#define BIT_FS_TRPC_TO_INT_EN_V1_8197F BIT(1) +#define BIT_FS_RPC_O_T_INT_EN_V1_8197F BIT(0) + +/* 2 REG_FE1ISR_8197F */ +#define BIT_BB_STOP_RX_INT_8197F BIT(29) +#define BIT_FS_RXDMA2_DONE_INT_8197F BIT(28) +#define BIT_FS_RXDONE3_INT_8197F BIT(27) +#define BIT_FS_RXDONE2_INT_8197F BIT(26) +#define BIT_FS_RX_BCN_P4_INT_8197F BIT(25) +#define BIT_FS_RX_BCN_P3_INT_8197F BIT(24) +#define BIT_FS_RX_BCN_P2_INT_8197F BIT(23) +#define BIT_FS_RX_BCN_P1_INT_8197F BIT(22) +#define BIT_FS_RX_BCN_P0_INT_8197F BIT(21) +#define BIT_FS_RX_UMD0_INT_8197F BIT(20) +#define BIT_FS_RX_UMD1_INT_8197F BIT(19) +#define BIT_FS_RX_BMD0_INT_8197F BIT(18) +#define BIT_FS_RX_BMD1_INT_8197F BIT(17) +#define BIT_FS_RXDONE_INT_8197F BIT(16) +#define BIT_FS_WWLAN_INT_8197F BIT(15) +#define BIT_FS_SOUND_DONE_INT_8197F BIT(14) +#define BIT_FS_LP_STBY_INT_8197F BIT(13) +#define BIT_FS_TRL_MTR_INT_8197F BIT(12) +#define BIT_FS_BF1_PRETO_INT_8197F BIT(11) +#define BIT_FS_BF0_PRETO_INT_8197F BIT(10) +#define BIT_FS_PTCL_RELEASE_MACID_INT_8197F BIT(9) +#define BIT_FS_LTE_COEX_INT_8197F BIT(6) +#define BIT_FS_WLACTOFF_INT_8197F BIT(5) +#define BIT_FS_WLACTON_INT_8197F BIT(4) +#define BIT_FS_BCN_RX_INT_INT_8197F BIT(3) +#define BIT_FS_MAILBOX_TO_I2C_INT_8197F BIT(2) +#define BIT_FS_TRPC_TO_INT_8197F BIT(1) +#define BIT_FS_RPC_O_T_INT_8197F BIT(0) + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_CPWM_8197F */ +#define BIT_CPWM_TOGGLING_8197F BIT(31) + +#define BIT_SHIFT_CPWM_MOD_8197F 24 +#define BIT_MASK_CPWM_MOD_8197F 0x7f +#define BIT_CPWM_MOD_8197F(x) (((x) & BIT_MASK_CPWM_MOD_8197F) << BIT_SHIFT_CPWM_MOD_8197F) +#define BITS_CPWM_MOD_8197F (BIT_MASK_CPWM_MOD_8197F << BIT_SHIFT_CPWM_MOD_8197F) +#define BIT_CLEAR_CPWM_MOD_8197F(x) ((x) & (~BITS_CPWM_MOD_8197F)) +#define BIT_GET_CPWM_MOD_8197F(x) (((x) >> BIT_SHIFT_CPWM_MOD_8197F) & BIT_MASK_CPWM_MOD_8197F) +#define BIT_SET_CPWM_MOD_8197F(x, v) (BIT_CLEAR_CPWM_MOD_8197F(x) | BIT_CPWM_MOD_8197F(v)) + + +/* 2 REG_FWIMR_8197F */ +#define BIT_FS_TXBCNOK_MB7_INT_EN_8197F BIT(31) +#define BIT_FS_TXBCNOK_MB6_INT_EN_8197F BIT(30) +#define BIT_FS_TXBCNOK_MB5_INT_EN_8197F BIT(29) +#define BIT_FS_TXBCNOK_MB4_INT_EN_8197F BIT(28) +#define BIT_FS_TXBCNOK_MB3_INT_EN_8197F BIT(27) +#define BIT_FS_TXBCNOK_MB2_INT_EN_8197F BIT(26) +#define BIT_FS_TXBCNOK_MB1_INT_EN_8197F BIT(25) +#define BIT_FS_TXBCNOK_MB0_INT_EN_8197F BIT(24) +#define BIT_FS_TXBCNERR_MB7_INT_EN_8197F BIT(23) +#define BIT_FS_TXBCNERR_MB6_INT_EN_8197F BIT(22) +#define BIT_FS_TXBCNERR_MB5_INT_EN_8197F BIT(21) +#define BIT_FS_TXBCNERR_MB4_INT_EN_8197F BIT(20) +#define BIT_FS_TXBCNERR_MB3_INT_EN_8197F BIT(19) +#define BIT_FS_TXBCNERR_MB2_INT_EN_8197F BIT(18) +#define BIT_FS_TXBCNERR_MB1_INT_EN_8197F BIT(17) +#define BIT_FS_TXBCNERR_MB0_INT_EN_8197F BIT(16) +#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN_8197F BIT(15) +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8197F BIT(13) +#define BIT_FS_MGNTQFF_TO_INT_EN_8197F BIT(12) +#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN_8197F BIT(11) +#define BIT_FS_DDMA1_HP_INT_EN_8197F BIT(10) +#define BIT_FS_DDMA0_LP_INT_EN_8197F BIT(9) +#define BIT_FS_DDMA0_HP_INT_EN_8197F BIT(8) +#define BIT_FS_TRXRPT_INT_EN_8197F BIT(7) +#define BIT_FS_C2H_W_READY_INT_EN_8197F BIT(6) +#define BIT_FS_HRCV_INT_EN_8197F BIT(5) +#define BIT_FS_H2CCMD_INT_EN_8197F BIT(4) +#define BIT_FS_TXPKTIN_INT_EN_8197F BIT(3) +#define BIT_FS_ERRORHDL_INT_EN_8197F BIT(2) +#define BIT_FS_TXCCX_INT_EN_8197F BIT(1) +#define BIT_FS_TXCLOSE_INT_EN_8197F BIT(0) + +/* 2 REG_FWISR_8197F */ +#define BIT_FS_TXBCNOK_MB7_INT_8197F BIT(31) +#define BIT_FS_TXBCNOK_MB6_INT_8197F BIT(30) +#define BIT_FS_TXBCNOK_MB5_INT_8197F BIT(29) +#define BIT_FS_TXBCNOK_MB4_INT_8197F BIT(28) +#define BIT_FS_TXBCNOK_MB3_INT_8197F BIT(27) +#define BIT_FS_TXBCNOK_MB2_INT_8197F BIT(26) +#define BIT_FS_TXBCNOK_MB1_INT_8197F BIT(25) +#define BIT_FS_TXBCNOK_MB0_INT_8197F BIT(24) +#define BIT_FS_TXBCNERR_MB7_INT_8197F BIT(23) +#define BIT_FS_TXBCNERR_MB6_INT_8197F BIT(22) +#define BIT_FS_TXBCNERR_MB5_INT_8197F BIT(21) +#define BIT_FS_TXBCNERR_MB4_INT_8197F BIT(20) +#define BIT_FS_TXBCNERR_MB3_INT_8197F BIT(19) +#define BIT_FS_TXBCNERR_MB2_INT_8197F BIT(18) +#define BIT_FS_TXBCNERR_MB1_INT_8197F BIT(17) +#define BIT_FS_TXBCNERR_MB0_INT_8197F BIT(16) +#define BIT_CPUMGN_POLLED_PKT_DONE_INT_8197F BIT(15) +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8197F BIT(13) +#define BIT_FS_MGNTQFF_TO_INT_8197F BIT(12) +#define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_8197F BIT(11) +#define BIT_FS_DDMA1_HP_INT_8197F BIT(10) +#define BIT_FS_DDMA0_LP_INT_8197F BIT(9) +#define BIT_FS_DDMA0_HP_INT_8197F BIT(8) +#define BIT_FS_TRXRPT_INT_8197F BIT(7) +#define BIT_FS_C2H_W_READY_INT_8197F BIT(6) +#define BIT_FS_HRCV_INT_8197F BIT(5) +#define BIT_FS_H2CCMD_INT_8197F BIT(4) +#define BIT_FS_TXPKTIN_INT_8197F BIT(3) +#define BIT_FS_ERRORHDL_INT_8197F BIT(2) +#define BIT_FS_TXCCX_INT_8197F BIT(1) +#define BIT_FS_TXCLOSE_INT_8197F BIT(0) + +/* 2 REG_FTIMR_8197F */ +#define BIT_PS_TIMER_C_EARLY_INT_EN_8197F BIT(23) +#define BIT_PS_TIMER_B_EARLY_INT_EN_8197F BIT(22) +#define BIT_PS_TIMER_A_EARLY_INT_EN_8197F BIT(21) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8197F BIT(20) +#define BIT_PS_TIMER_C_INT_EN_8197F BIT(19) +#define BIT_PS_TIMER_B_INT_EN_8197F BIT(18) +#define BIT_PS_TIMER_A_INT_EN_8197F BIT(17) +#define BIT_CPUMGQ_TX_TIMER_INT_EN_8197F BIT(16) +#define BIT_FS_PS_TIMEOUT2_EN_8197F BIT(15) +#define BIT_FS_PS_TIMEOUT1_EN_8197F BIT(14) +#define BIT_FS_PS_TIMEOUT0_EN_8197F BIT(13) +#define BIT_FS_GTINT8_EN_8197F BIT(8) +#define BIT_FS_GTINT7_EN_8197F BIT(7) +#define BIT_FS_GTINT6_EN_8197F BIT(6) +#define BIT_FS_GTINT5_EN_8197F BIT(5) +#define BIT_FS_GTINT4_EN_8197F BIT(4) +#define BIT_FS_GTINT3_EN_8197F BIT(3) +#define BIT_FS_GTINT2_EN_8197F BIT(2) +#define BIT_FS_GTINT1_EN_8197F BIT(1) +#define BIT_FS_GTINT0_EN_8197F BIT(0) + +/* 2 REG_FTISR_8197F */ +#define BIT_PS_TIMER_C_EARLY__INT_8197F BIT(23) +#define BIT_PS_TIMER_B_EARLY__INT_8197F BIT(22) +#define BIT_PS_TIMER_A_EARLY__INT_8197F BIT(21) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8197F BIT(20) +#define BIT_PS_TIMER_C_INT_8197F BIT(19) +#define BIT_PS_TIMER_B_INT_8197F BIT(18) +#define BIT_PS_TIMER_A_INT_8197F BIT(17) +#define BIT_CPUMGQ_TX_TIMER_INT_8197F BIT(16) +#define BIT_FS_PS_TIMEOUT2_INT_8197F BIT(15) +#define BIT_FS_PS_TIMEOUT1_INT_8197F BIT(14) +#define BIT_FS_PS_TIMEOUT0_INT_8197F BIT(13) +#define BIT_FS_GTINT8_INT_8197F BIT(8) +#define BIT_FS_GTINT7_INT_8197F BIT(7) +#define BIT_FS_GTINT6_INT_8197F BIT(6) +#define BIT_FS_GTINT5_INT_8197F BIT(5) +#define BIT_FS_GTINT4_INT_8197F BIT(4) +#define BIT_FS_GTINT3_INT_8197F BIT(3) +#define BIT_FS_GTINT2_INT_8197F BIT(2) +#define BIT_FS_GTINT1_INT_8197F BIT(1) +#define BIT_FS_GTINT0_INT_8197F BIT(0) + +/* 2 REG_PKTBUF_DBG_CTRL_8197F */ + +#define BIT_SHIFT_PKTBUF_WRITE_EN_8197F 24 +#define BIT_MASK_PKTBUF_WRITE_EN_8197F 0xff +#define BIT_PKTBUF_WRITE_EN_8197F(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8197F) << BIT_SHIFT_PKTBUF_WRITE_EN_8197F) +#define BITS_PKTBUF_WRITE_EN_8197F (BIT_MASK_PKTBUF_WRITE_EN_8197F << BIT_SHIFT_PKTBUF_WRITE_EN_8197F) +#define BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8197F)) +#define BIT_GET_PKTBUF_WRITE_EN_8197F(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8197F) & BIT_MASK_PKTBUF_WRITE_EN_8197F) +#define BIT_SET_PKTBUF_WRITE_EN_8197F(x, v) (BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) | BIT_PKTBUF_WRITE_EN_8197F(v)) + +#define BIT_TXRPTBUF_DBG_8197F BIT(23) + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_TXPKTBUF_DBG_V2_8197F BIT(20) +#define BIT_RXPKTBUF_DBG_8197F BIT(16) + +#define BIT_SHIFT_PKTBUF_DBG_ADDR_8197F 0 +#define BIT_MASK_PKTBUF_DBG_ADDR_8197F 0x1fff +#define BIT_PKTBUF_DBG_ADDR_8197F(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8197F) << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) +#define BITS_PKTBUF_DBG_ADDR_8197F (BIT_MASK_PKTBUF_DBG_ADDR_8197F << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) +#define BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8197F)) +#define BIT_GET_PKTBUF_DBG_ADDR_8197F(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) & BIT_MASK_PKTBUF_DBG_ADDR_8197F) +#define BIT_SET_PKTBUF_DBG_ADDR_8197F(x, v) (BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) | BIT_PKTBUF_DBG_ADDR_8197F(v)) + + +/* 2 REG_PKTBUF_DBG_DATA_L_8197F */ + +#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F 0 +#define BIT_MASK_PKTBUF_DBG_DATA_L_8197F 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_L_8197F(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8197F) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) +#define BITS_PKTBUF_DBG_DATA_L_8197F (BIT_MASK_PKTBUF_DBG_DATA_L_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) ((x) & (~BITS_PKTBUF_DBG_DATA_L_8197F)) +#define BIT_GET_PKTBUF_DBG_DATA_L_8197F(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) & BIT_MASK_PKTBUF_DBG_DATA_L_8197F) +#define BIT_SET_PKTBUF_DBG_DATA_L_8197F(x, v) (BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) | BIT_PKTBUF_DBG_DATA_L_8197F(v)) + + +/* 2 REG_PKTBUF_DBG_DATA_H_8197F */ + +#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F 0 +#define BIT_MASK_PKTBUF_DBG_DATA_H_8197F 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_H_8197F(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8197F) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) +#define BITS_PKTBUF_DBG_DATA_H_8197F (BIT_MASK_PKTBUF_DBG_DATA_H_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) ((x) & (~BITS_PKTBUF_DBG_DATA_H_8197F)) +#define BIT_GET_PKTBUF_DBG_DATA_H_8197F(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) & BIT_MASK_PKTBUF_DBG_DATA_H_8197F) +#define BIT_SET_PKTBUF_DBG_DATA_H_8197F(x, v) (BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) | BIT_PKTBUF_DBG_DATA_H_8197F(v)) + + +/* 2 REG_CPWM2_8197F */ + +#define BIT_SHIFT_L0S_TO_RCVY_NUM_8197F 16 +#define BIT_MASK_L0S_TO_RCVY_NUM_8197F 0xff +#define BIT_L0S_TO_RCVY_NUM_8197F(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8197F) << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) +#define BITS_L0S_TO_RCVY_NUM_8197F (BIT_MASK_L0S_TO_RCVY_NUM_8197F << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) +#define BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8197F)) +#define BIT_GET_L0S_TO_RCVY_NUM_8197F(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) & BIT_MASK_L0S_TO_RCVY_NUM_8197F) +#define BIT_SET_L0S_TO_RCVY_NUM_8197F(x, v) (BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) | BIT_L0S_TO_RCVY_NUM_8197F(v)) + +#define BIT_CPWM2_TOGGLING_8197F BIT(15) + +#define BIT_SHIFT_CPWM2_MOD_8197F 0 +#define BIT_MASK_CPWM2_MOD_8197F 0x7fff +#define BIT_CPWM2_MOD_8197F(x) (((x) & BIT_MASK_CPWM2_MOD_8197F) << BIT_SHIFT_CPWM2_MOD_8197F) +#define BITS_CPWM2_MOD_8197F (BIT_MASK_CPWM2_MOD_8197F << BIT_SHIFT_CPWM2_MOD_8197F) +#define BIT_CLEAR_CPWM2_MOD_8197F(x) ((x) & (~BITS_CPWM2_MOD_8197F)) +#define BIT_GET_CPWM2_MOD_8197F(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8197F) & BIT_MASK_CPWM2_MOD_8197F) +#define BIT_SET_CPWM2_MOD_8197F(x, v) (BIT_CLEAR_CPWM2_MOD_8197F(x) | BIT_CPWM2_MOD_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_TC0_CTRL_8197F */ +#define BIT_TC0INT_EN_8197F BIT(26) +#define BIT_TC0MODE_8197F BIT(25) +#define BIT_TC0EN_8197F BIT(24) + +#define BIT_SHIFT_TC0DATA_8197F 0 +#define BIT_MASK_TC0DATA_8197F 0xffffff +#define BIT_TC0DATA_8197F(x) (((x) & BIT_MASK_TC0DATA_8197F) << BIT_SHIFT_TC0DATA_8197F) +#define BITS_TC0DATA_8197F (BIT_MASK_TC0DATA_8197F << BIT_SHIFT_TC0DATA_8197F) +#define BIT_CLEAR_TC0DATA_8197F(x) ((x) & (~BITS_TC0DATA_8197F)) +#define BIT_GET_TC0DATA_8197F(x) (((x) >> BIT_SHIFT_TC0DATA_8197F) & BIT_MASK_TC0DATA_8197F) +#define BIT_SET_TC0DATA_8197F(x, v) (BIT_CLEAR_TC0DATA_8197F(x) | BIT_TC0DATA_8197F(v)) + + +/* 2 REG_TC1_CTRL_8197F */ +#define BIT_TC1INT_EN_8197F BIT(26) +#define BIT_TC1MODE_8197F BIT(25) +#define BIT_TC1EN_8197F BIT(24) + +#define BIT_SHIFT_TC1DATA_8197F 0 +#define BIT_MASK_TC1DATA_8197F 0xffffff +#define BIT_TC1DATA_8197F(x) (((x) & BIT_MASK_TC1DATA_8197F) << BIT_SHIFT_TC1DATA_8197F) +#define BITS_TC1DATA_8197F (BIT_MASK_TC1DATA_8197F << BIT_SHIFT_TC1DATA_8197F) +#define BIT_CLEAR_TC1DATA_8197F(x) ((x) & (~BITS_TC1DATA_8197F)) +#define BIT_GET_TC1DATA_8197F(x) (((x) >> BIT_SHIFT_TC1DATA_8197F) & BIT_MASK_TC1DATA_8197F) +#define BIT_SET_TC1DATA_8197F(x, v) (BIT_CLEAR_TC1DATA_8197F(x) | BIT_TC1DATA_8197F(v)) + + +/* 2 REG_TC2_CTRL_8197F */ +#define BIT_TC2INT_EN_8197F BIT(26) +#define BIT_TC2MODE_8197F BIT(25) +#define BIT_TC2EN_8197F BIT(24) + +#define BIT_SHIFT_TC2DATA_8197F 0 +#define BIT_MASK_TC2DATA_8197F 0xffffff +#define BIT_TC2DATA_8197F(x) (((x) & BIT_MASK_TC2DATA_8197F) << BIT_SHIFT_TC2DATA_8197F) +#define BITS_TC2DATA_8197F (BIT_MASK_TC2DATA_8197F << BIT_SHIFT_TC2DATA_8197F) +#define BIT_CLEAR_TC2DATA_8197F(x) ((x) & (~BITS_TC2DATA_8197F)) +#define BIT_GET_TC2DATA_8197F(x) (((x) >> BIT_SHIFT_TC2DATA_8197F) & BIT_MASK_TC2DATA_8197F) +#define BIT_SET_TC2DATA_8197F(x, v) (BIT_CLEAR_TC2DATA_8197F(x) | BIT_TC2DATA_8197F(v)) + + +/* 2 REG_TC3_CTRL_8197F */ +#define BIT_TC3INT_EN_8197F BIT(26) +#define BIT_TC3MODE_8197F BIT(25) +#define BIT_TC3EN_8197F BIT(24) + +#define BIT_SHIFT_TC3DATA_8197F 0 +#define BIT_MASK_TC3DATA_8197F 0xffffff +#define BIT_TC3DATA_8197F(x) (((x) & BIT_MASK_TC3DATA_8197F) << BIT_SHIFT_TC3DATA_8197F) +#define BITS_TC3DATA_8197F (BIT_MASK_TC3DATA_8197F << BIT_SHIFT_TC3DATA_8197F) +#define BIT_CLEAR_TC3DATA_8197F(x) ((x) & (~BITS_TC3DATA_8197F)) +#define BIT_GET_TC3DATA_8197F(x) (((x) >> BIT_SHIFT_TC3DATA_8197F) & BIT_MASK_TC3DATA_8197F) +#define BIT_SET_TC3DATA_8197F(x, v) (BIT_CLEAR_TC3DATA_8197F(x) | BIT_TC3DATA_8197F(v)) + + +/* 2 REG_TC4_CTRL_8197F */ +#define BIT_TC4INT_EN_8197F BIT(26) +#define BIT_TC4MODE_8197F BIT(25) +#define BIT_TC4EN_8197F BIT(24) + +#define BIT_SHIFT_TC4DATA_8197F 0 +#define BIT_MASK_TC4DATA_8197F 0xffffff +#define BIT_TC4DATA_8197F(x) (((x) & BIT_MASK_TC4DATA_8197F) << BIT_SHIFT_TC4DATA_8197F) +#define BITS_TC4DATA_8197F (BIT_MASK_TC4DATA_8197F << BIT_SHIFT_TC4DATA_8197F) +#define BIT_CLEAR_TC4DATA_8197F(x) ((x) & (~BITS_TC4DATA_8197F)) +#define BIT_GET_TC4DATA_8197F(x) (((x) >> BIT_SHIFT_TC4DATA_8197F) & BIT_MASK_TC4DATA_8197F) +#define BIT_SET_TC4DATA_8197F(x, v) (BIT_CLEAR_TC4DATA_8197F(x) | BIT_TC4DATA_8197F(v)) + + +/* 2 REG_TCUNIT_BASE_8197F */ + +#define BIT_SHIFT_TCUNIT_BASE_8197F 0 +#define BIT_MASK_TCUNIT_BASE_8197F 0x3fff +#define BIT_TCUNIT_BASE_8197F(x) (((x) & BIT_MASK_TCUNIT_BASE_8197F) << BIT_SHIFT_TCUNIT_BASE_8197F) +#define BITS_TCUNIT_BASE_8197F (BIT_MASK_TCUNIT_BASE_8197F << BIT_SHIFT_TCUNIT_BASE_8197F) +#define BIT_CLEAR_TCUNIT_BASE_8197F(x) ((x) & (~BITS_TCUNIT_BASE_8197F)) +#define BIT_GET_TCUNIT_BASE_8197F(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8197F) & BIT_MASK_TCUNIT_BASE_8197F) +#define BIT_SET_TCUNIT_BASE_8197F(x, v) (BIT_CLEAR_TCUNIT_BASE_8197F(x) | BIT_TCUNIT_BASE_8197F(v)) + + +/* 2 REG_TC5_CTRL_8197F */ +#define BIT_TC5INT_EN_8197F BIT(26) +#define BIT_TC5MODE_8197F BIT(25) +#define BIT_TC5EN_8197F BIT(24) + +#define BIT_SHIFT_TC5DATA_8197F 0 +#define BIT_MASK_TC5DATA_8197F 0xffffff +#define BIT_TC5DATA_8197F(x) (((x) & BIT_MASK_TC5DATA_8197F) << BIT_SHIFT_TC5DATA_8197F) +#define BITS_TC5DATA_8197F (BIT_MASK_TC5DATA_8197F << BIT_SHIFT_TC5DATA_8197F) +#define BIT_CLEAR_TC5DATA_8197F(x) ((x) & (~BITS_TC5DATA_8197F)) +#define BIT_GET_TC5DATA_8197F(x) (((x) >> BIT_SHIFT_TC5DATA_8197F) & BIT_MASK_TC5DATA_8197F) +#define BIT_SET_TC5DATA_8197F(x, v) (BIT_CLEAR_TC5DATA_8197F(x) | BIT_TC5DATA_8197F(v)) + + +/* 2 REG_TC6_CTRL_8197F */ +#define BIT_TC6INT_EN_8197F BIT(26) +#define BIT_TC6MODE_8197F BIT(25) +#define BIT_TC6EN_8197F BIT(24) + +#define BIT_SHIFT_TC6DATA_8197F 0 +#define BIT_MASK_TC6DATA_8197F 0xffffff +#define BIT_TC6DATA_8197F(x) (((x) & BIT_MASK_TC6DATA_8197F) << BIT_SHIFT_TC6DATA_8197F) +#define BITS_TC6DATA_8197F (BIT_MASK_TC6DATA_8197F << BIT_SHIFT_TC6DATA_8197F) +#define BIT_CLEAR_TC6DATA_8197F(x) ((x) & (~BITS_TC6DATA_8197F)) +#define BIT_GET_TC6DATA_8197F(x) (((x) >> BIT_SHIFT_TC6DATA_8197F) & BIT_MASK_TC6DATA_8197F) +#define BIT_SET_TC6DATA_8197F(x, v) (BIT_CLEAR_TC6DATA_8197F(x) | BIT_TC6DATA_8197F(v)) + + +/* 2 REG_MBIST_FAIL_8197F */ + +#define BIT_SHIFT_8051_MBIST_FAIL_8197F 26 +#define BIT_MASK_8051_MBIST_FAIL_8197F 0x7 +#define BIT_8051_MBIST_FAIL_8197F(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8197F) << BIT_SHIFT_8051_MBIST_FAIL_8197F) +#define BITS_8051_MBIST_FAIL_8197F (BIT_MASK_8051_MBIST_FAIL_8197F << BIT_SHIFT_8051_MBIST_FAIL_8197F) +#define BIT_CLEAR_8051_MBIST_FAIL_8197F(x) ((x) & (~BITS_8051_MBIST_FAIL_8197F)) +#define BIT_GET_8051_MBIST_FAIL_8197F(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8197F) & BIT_MASK_8051_MBIST_FAIL_8197F) +#define BIT_SET_8051_MBIST_FAIL_8197F(x, v) (BIT_CLEAR_8051_MBIST_FAIL_8197F(x) | BIT_8051_MBIST_FAIL_8197F(v)) + + +#define BIT_SHIFT_USB_MBIST_FAIL_8197F 24 +#define BIT_MASK_USB_MBIST_FAIL_8197F 0x3 +#define BIT_USB_MBIST_FAIL_8197F(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8197F) << BIT_SHIFT_USB_MBIST_FAIL_8197F) +#define BITS_USB_MBIST_FAIL_8197F (BIT_MASK_USB_MBIST_FAIL_8197F << BIT_SHIFT_USB_MBIST_FAIL_8197F) +#define BIT_CLEAR_USB_MBIST_FAIL_8197F(x) ((x) & (~BITS_USB_MBIST_FAIL_8197F)) +#define BIT_GET_USB_MBIST_FAIL_8197F(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8197F) & BIT_MASK_USB_MBIST_FAIL_8197F) +#define BIT_SET_USB_MBIST_FAIL_8197F(x, v) (BIT_CLEAR_USB_MBIST_FAIL_8197F(x) | BIT_USB_MBIST_FAIL_8197F(v)) + + +#define BIT_SHIFT_PCIE_MBIST_FAIL_8197F 16 +#define BIT_MASK_PCIE_MBIST_FAIL_8197F 0x3f +#define BIT_PCIE_MBIST_FAIL_8197F(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8197F) << BIT_SHIFT_PCIE_MBIST_FAIL_8197F) +#define BITS_PCIE_MBIST_FAIL_8197F (BIT_MASK_PCIE_MBIST_FAIL_8197F << BIT_SHIFT_PCIE_MBIST_FAIL_8197F) +#define BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) ((x) & (~BITS_PCIE_MBIST_FAIL_8197F)) +#define BIT_GET_PCIE_MBIST_FAIL_8197F(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8197F) & BIT_MASK_PCIE_MBIST_FAIL_8197F) +#define BIT_SET_PCIE_MBIST_FAIL_8197F(x, v) (BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) | BIT_PCIE_MBIST_FAIL_8197F(v)) + + +#define BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F 0 +#define BIT_MASK_MAC_MBIST_FAIL_DRF_8197F 0x3ffff +#define BIT_MAC_MBIST_FAIL_DRF_8197F(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF_8197F) << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) +#define BITS_MAC_MBIST_FAIL_DRF_8197F (BIT_MASK_MAC_MBIST_FAIL_DRF_8197F << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) +#define BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) ((x) & (~BITS_MAC_MBIST_FAIL_DRF_8197F)) +#define BIT_GET_MAC_MBIST_FAIL_DRF_8197F(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) & BIT_MASK_MAC_MBIST_FAIL_DRF_8197F) +#define BIT_SET_MAC_MBIST_FAIL_DRF_8197F(x, v) (BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) | BIT_MAC_MBIST_FAIL_DRF_8197F(v)) + + +/* 2 REG_MBIST_START_PAUSE_8197F */ + +#define BIT_SHIFT_8051_MBIST_START_PAUSE_8197F 26 +#define BIT_MASK_8051_MBIST_START_PAUSE_8197F 0x7 +#define BIT_8051_MBIST_START_PAUSE_8197F(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8197F) << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) +#define BITS_8051_MBIST_START_PAUSE_8197F (BIT_MASK_8051_MBIST_START_PAUSE_8197F << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) +#define BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) ((x) & (~BITS_8051_MBIST_START_PAUSE_8197F)) +#define BIT_GET_8051_MBIST_START_PAUSE_8197F(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) & BIT_MASK_8051_MBIST_START_PAUSE_8197F) +#define BIT_SET_8051_MBIST_START_PAUSE_8197F(x, v) (BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) | BIT_8051_MBIST_START_PAUSE_8197F(v)) + + +#define BIT_SHIFT_USB_MBIST_START_PAUSE_8197F 24 +#define BIT_MASK_USB_MBIST_START_PAUSE_8197F 0x3 +#define BIT_USB_MBIST_START_PAUSE_8197F(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8197F) << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) +#define BITS_USB_MBIST_START_PAUSE_8197F (BIT_MASK_USB_MBIST_START_PAUSE_8197F << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) +#define BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) ((x) & (~BITS_USB_MBIST_START_PAUSE_8197F)) +#define BIT_GET_USB_MBIST_START_PAUSE_8197F(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) & BIT_MASK_USB_MBIST_START_PAUSE_8197F) +#define BIT_SET_USB_MBIST_START_PAUSE_8197F(x, v) (BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) | BIT_USB_MBIST_START_PAUSE_8197F(v)) + + +#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F 16 +#define BIT_MASK_PCIE_MBIST_START_PAUSE_8197F 0x3f +#define BIT_PCIE_MBIST_START_PAUSE_8197F(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8197F) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) +#define BITS_PCIE_MBIST_START_PAUSE_8197F (BIT_MASK_PCIE_MBIST_START_PAUSE_8197F << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) ((x) & (~BITS_PCIE_MBIST_START_PAUSE_8197F)) +#define BIT_GET_PCIE_MBIST_START_PAUSE_8197F(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) & BIT_MASK_PCIE_MBIST_START_PAUSE_8197F) +#define BIT_SET_PCIE_MBIST_START_PAUSE_8197F(x, v) (BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) | BIT_PCIE_MBIST_START_PAUSE_8197F(v)) + + +#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F 0 +#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F 0x3ffff +#define BIT_MAC_MBIST_START_PAUSE_V1_8197F(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F) << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) +#define BITS_MAC_MBIST_START_PAUSE_V1_8197F (BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8197F)) +#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8197F(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F) +#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8197F(x, v) (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) | BIT_MAC_MBIST_START_PAUSE_V1_8197F(v)) + + +/* 2 REG_MBIST_DONE_8197F */ + +#define BIT_SHIFT_8051_MBIST_DONE_8197F 26 +#define BIT_MASK_8051_MBIST_DONE_8197F 0x7 +#define BIT_8051_MBIST_DONE_8197F(x) (((x) & BIT_MASK_8051_MBIST_DONE_8197F) << BIT_SHIFT_8051_MBIST_DONE_8197F) +#define BITS_8051_MBIST_DONE_8197F (BIT_MASK_8051_MBIST_DONE_8197F << BIT_SHIFT_8051_MBIST_DONE_8197F) +#define BIT_CLEAR_8051_MBIST_DONE_8197F(x) ((x) & (~BITS_8051_MBIST_DONE_8197F)) +#define BIT_GET_8051_MBIST_DONE_8197F(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8197F) & BIT_MASK_8051_MBIST_DONE_8197F) +#define BIT_SET_8051_MBIST_DONE_8197F(x, v) (BIT_CLEAR_8051_MBIST_DONE_8197F(x) | BIT_8051_MBIST_DONE_8197F(v)) + + +#define BIT_SHIFT_USB_MBIST_DONE_8197F 24 +#define BIT_MASK_USB_MBIST_DONE_8197F 0x3 +#define BIT_USB_MBIST_DONE_8197F(x) (((x) & BIT_MASK_USB_MBIST_DONE_8197F) << BIT_SHIFT_USB_MBIST_DONE_8197F) +#define BITS_USB_MBIST_DONE_8197F (BIT_MASK_USB_MBIST_DONE_8197F << BIT_SHIFT_USB_MBIST_DONE_8197F) +#define BIT_CLEAR_USB_MBIST_DONE_8197F(x) ((x) & (~BITS_USB_MBIST_DONE_8197F)) +#define BIT_GET_USB_MBIST_DONE_8197F(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8197F) & BIT_MASK_USB_MBIST_DONE_8197F) +#define BIT_SET_USB_MBIST_DONE_8197F(x, v) (BIT_CLEAR_USB_MBIST_DONE_8197F(x) | BIT_USB_MBIST_DONE_8197F(v)) + + +#define BIT_SHIFT_PCIE_MBIST_DONE_8197F 16 +#define BIT_MASK_PCIE_MBIST_DONE_8197F 0x3f +#define BIT_PCIE_MBIST_DONE_8197F(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8197F) << BIT_SHIFT_PCIE_MBIST_DONE_8197F) +#define BITS_PCIE_MBIST_DONE_8197F (BIT_MASK_PCIE_MBIST_DONE_8197F << BIT_SHIFT_PCIE_MBIST_DONE_8197F) +#define BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) ((x) & (~BITS_PCIE_MBIST_DONE_8197F)) +#define BIT_GET_PCIE_MBIST_DONE_8197F(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8197F) & BIT_MASK_PCIE_MBIST_DONE_8197F) +#define BIT_SET_PCIE_MBIST_DONE_8197F(x, v) (BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) | BIT_PCIE_MBIST_DONE_8197F(v)) + + +#define BIT_SHIFT_MAC_MBIST_DONE_V1_8197F 0 +#define BIT_MASK_MAC_MBIST_DONE_V1_8197F 0x3ffff +#define BIT_MAC_MBIST_DONE_V1_8197F(x) (((x) & BIT_MASK_MAC_MBIST_DONE_V1_8197F) << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) +#define BITS_MAC_MBIST_DONE_V1_8197F (BIT_MASK_MAC_MBIST_DONE_V1_8197F << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) +#define BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) ((x) & (~BITS_MAC_MBIST_DONE_V1_8197F)) +#define BIT_GET_MAC_MBIST_DONE_V1_8197F(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) & BIT_MASK_MAC_MBIST_DONE_V1_8197F) +#define BIT_SET_MAC_MBIST_DONE_V1_8197F(x, v) (BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) | BIT_MAC_MBIST_DONE_V1_8197F(v)) + + +/* 2 REG_MBIST_FAIL_NRML_8197F */ + +#define BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F 0 +#define BIT_MASK_MBIST_FAIL_NRML_V1_8197F 0x3ffff +#define BIT_MBIST_FAIL_NRML_V1_8197F(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_V1_8197F) << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) +#define BITS_MBIST_FAIL_NRML_V1_8197F (BIT_MASK_MBIST_FAIL_NRML_V1_8197F << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) +#define BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) ((x) & (~BITS_MBIST_FAIL_NRML_V1_8197F)) +#define BIT_GET_MBIST_FAIL_NRML_V1_8197F(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) & BIT_MASK_MBIST_FAIL_NRML_V1_8197F) +#define BIT_SET_MBIST_FAIL_NRML_V1_8197F(x, v) (BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) | BIT_MBIST_FAIL_NRML_V1_8197F(v)) + + +/* 2 REG_AES_DECRPT_DATA_8197F */ + +#define BIT_SHIFT_IPS_CFG_ADDR_8197F 0 +#define BIT_MASK_IPS_CFG_ADDR_8197F 0xff +#define BIT_IPS_CFG_ADDR_8197F(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8197F) << BIT_SHIFT_IPS_CFG_ADDR_8197F) +#define BITS_IPS_CFG_ADDR_8197F (BIT_MASK_IPS_CFG_ADDR_8197F << BIT_SHIFT_IPS_CFG_ADDR_8197F) +#define BIT_CLEAR_IPS_CFG_ADDR_8197F(x) ((x) & (~BITS_IPS_CFG_ADDR_8197F)) +#define BIT_GET_IPS_CFG_ADDR_8197F(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8197F) & BIT_MASK_IPS_CFG_ADDR_8197F) +#define BIT_SET_IPS_CFG_ADDR_8197F(x, v) (BIT_CLEAR_IPS_CFG_ADDR_8197F(x) | BIT_IPS_CFG_ADDR_8197F(v)) + + +/* 2 REG_AES_DECRPT_CFG_8197F */ + +#define BIT_SHIFT_IPS_CFG_DATA_8197F 0 +#define BIT_MASK_IPS_CFG_DATA_8197F 0xffffffffL +#define BIT_IPS_CFG_DATA_8197F(x) (((x) & BIT_MASK_IPS_CFG_DATA_8197F) << BIT_SHIFT_IPS_CFG_DATA_8197F) +#define BITS_IPS_CFG_DATA_8197F (BIT_MASK_IPS_CFG_DATA_8197F << BIT_SHIFT_IPS_CFG_DATA_8197F) +#define BIT_CLEAR_IPS_CFG_DATA_8197F(x) ((x) & (~BITS_IPS_CFG_DATA_8197F)) +#define BIT_GET_IPS_CFG_DATA_8197F(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8197F) & BIT_MASK_IPS_CFG_DATA_8197F) +#define BIT_SET_IPS_CFG_DATA_8197F(x, v) (BIT_CLEAR_IPS_CFG_DATA_8197F(x) | BIT_IPS_CFG_DATA_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_MACCLKFRQ_8197F */ + +#define BIT_SHIFT_MACCLK_FREQ_LOW32_8197F 0 +#define BIT_MASK_MACCLK_FREQ_LOW32_8197F 0xffffffffL +#define BIT_MACCLK_FREQ_LOW32_8197F(x) (((x) & BIT_MASK_MACCLK_FREQ_LOW32_8197F) << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) +#define BITS_MACCLK_FREQ_LOW32_8197F (BIT_MASK_MACCLK_FREQ_LOW32_8197F << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) +#define BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) ((x) & (~BITS_MACCLK_FREQ_LOW32_8197F)) +#define BIT_GET_MACCLK_FREQ_LOW32_8197F(x) (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) & BIT_MASK_MACCLK_FREQ_LOW32_8197F) +#define BIT_SET_MACCLK_FREQ_LOW32_8197F(x, v) (BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) | BIT_MACCLK_FREQ_LOW32_8197F(v)) + + +/* 2 REG_TMETER_8197F */ + +#define BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F 0 +#define BIT_MASK_MACCLK_FREQ_HIGH10_8197F 0x3ff +#define BIT_MACCLK_FREQ_HIGH10_8197F(x) (((x) & BIT_MASK_MACCLK_FREQ_HIGH10_8197F) << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) +#define BITS_MACCLK_FREQ_HIGH10_8197F (BIT_MASK_MACCLK_FREQ_HIGH10_8197F << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) +#define BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) ((x) & (~BITS_MACCLK_FREQ_HIGH10_8197F)) +#define BIT_GET_MACCLK_FREQ_HIGH10_8197F(x) (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) & BIT_MASK_MACCLK_FREQ_HIGH10_8197F) +#define BIT_SET_MACCLK_FREQ_HIGH10_8197F(x, v) (BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) | BIT_MACCLK_FREQ_HIGH10_8197F(v)) + + +/* 2 REG_OSC_32K_CTRL_8197F */ +#define BIT_32K_CLK_OUT_RDY_8197F BIT(12) + +#define BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F 8 +#define BIT_MASK_MONITOR_CYCLE_LOG2_8197F 0xf +#define BIT_MONITOR_CYCLE_LOG2_8197F(x) (((x) & BIT_MASK_MONITOR_CYCLE_LOG2_8197F) << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) +#define BITS_MONITOR_CYCLE_LOG2_8197F (BIT_MASK_MONITOR_CYCLE_LOG2_8197F << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) +#define BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) ((x) & (~BITS_MONITOR_CYCLE_LOG2_8197F)) +#define BIT_GET_MONITOR_CYCLE_LOG2_8197F(x) (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) & BIT_MASK_MONITOR_CYCLE_LOG2_8197F) +#define BIT_SET_MONITOR_CYCLE_LOG2_8197F(x, v) (BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) | BIT_MONITOR_CYCLE_LOG2_8197F(v)) + + +/* 2 REG_32K_CAL_REG1_8197F */ + +#define BIT_SHIFT_FREQVALUE_UNREGCLK_8197F 8 +#define BIT_MASK_FREQVALUE_UNREGCLK_8197F 0xffffff +#define BIT_FREQVALUE_UNREGCLK_8197F(x) (((x) & BIT_MASK_FREQVALUE_UNREGCLK_8197F) << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) +#define BITS_FREQVALUE_UNREGCLK_8197F (BIT_MASK_FREQVALUE_UNREGCLK_8197F << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) +#define BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) ((x) & (~BITS_FREQVALUE_UNREGCLK_8197F)) +#define BIT_GET_FREQVALUE_UNREGCLK_8197F(x) (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) & BIT_MASK_FREQVALUE_UNREGCLK_8197F) +#define BIT_SET_FREQVALUE_UNREGCLK_8197F(x, v) (BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) | BIT_FREQVALUE_UNREGCLK_8197F(v)) + +#define BIT_CAL32K_DBGMOD_8197F BIT(7) + +#define BIT_SHIFT_NCO_THRS_8197F 0 +#define BIT_MASK_NCO_THRS_8197F 0x7f +#define BIT_NCO_THRS_8197F(x) (((x) & BIT_MASK_NCO_THRS_8197F) << BIT_SHIFT_NCO_THRS_8197F) +#define BITS_NCO_THRS_8197F (BIT_MASK_NCO_THRS_8197F << BIT_SHIFT_NCO_THRS_8197F) +#define BIT_CLEAR_NCO_THRS_8197F(x) ((x) & (~BITS_NCO_THRS_8197F)) +#define BIT_GET_NCO_THRS_8197F(x) (((x) >> BIT_SHIFT_NCO_THRS_8197F) & BIT_MASK_NCO_THRS_8197F) +#define BIT_SET_NCO_THRS_8197F(x, v) (BIT_CLEAR_NCO_THRS_8197F(x) | BIT_NCO_THRS_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_C2HEVT_8197F */ + +#define BIT_SHIFT_C2HEVT_MSG_8197F 0 +#define BIT_MASK_C2HEVT_MSG_8197F 0xffffffffffffffffffffffffffffffffL +#define BIT_C2HEVT_MSG_8197F(x) (((x) & BIT_MASK_C2HEVT_MSG_8197F) << BIT_SHIFT_C2HEVT_MSG_8197F) +#define BITS_C2HEVT_MSG_8197F (BIT_MASK_C2HEVT_MSG_8197F << BIT_SHIFT_C2HEVT_MSG_8197F) +#define BIT_CLEAR_C2HEVT_MSG_8197F(x) ((x) & (~BITS_C2HEVT_MSG_8197F)) +#define BIT_GET_C2HEVT_MSG_8197F(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_8197F) & BIT_MASK_C2HEVT_MSG_8197F) +#define BIT_SET_C2HEVT_MSG_8197F(x, v) (BIT_CLEAR_C2HEVT_MSG_8197F(x) | BIT_C2HEVT_MSG_8197F(v)) + + +/* 2 REG_SW_DEFINED_PAGE1_8197F */ + +#define BIT_SHIFT_SW_DEFINED_PAGE1_8197F 0 +#define BIT_MASK_SW_DEFINED_PAGE1_8197F 0xffffffffffffffffL +#define BIT_SW_DEFINED_PAGE1_8197F(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_8197F) << BIT_SHIFT_SW_DEFINED_PAGE1_8197F) +#define BITS_SW_DEFINED_PAGE1_8197F (BIT_MASK_SW_DEFINED_PAGE1_8197F << BIT_SHIFT_SW_DEFINED_PAGE1_8197F) +#define BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) ((x) & (~BITS_SW_DEFINED_PAGE1_8197F)) +#define BIT_GET_SW_DEFINED_PAGE1_8197F(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8197F) & BIT_MASK_SW_DEFINED_PAGE1_8197F) +#define BIT_SET_SW_DEFINED_PAGE1_8197F(x, v) (BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) | BIT_SW_DEFINED_PAGE1_8197F(v)) + + +/* 2 REG_MCUTST_I_8197F */ + +#define BIT_SHIFT_MCUDMSG_I_8197F 0 +#define BIT_MASK_MCUDMSG_I_8197F 0xffffffffL +#define BIT_MCUDMSG_I_8197F(x) (((x) & BIT_MASK_MCUDMSG_I_8197F) << BIT_SHIFT_MCUDMSG_I_8197F) +#define BITS_MCUDMSG_I_8197F (BIT_MASK_MCUDMSG_I_8197F << BIT_SHIFT_MCUDMSG_I_8197F) +#define BIT_CLEAR_MCUDMSG_I_8197F(x) ((x) & (~BITS_MCUDMSG_I_8197F)) +#define BIT_GET_MCUDMSG_I_8197F(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8197F) & BIT_MASK_MCUDMSG_I_8197F) +#define BIT_SET_MCUDMSG_I_8197F(x, v) (BIT_CLEAR_MCUDMSG_I_8197F(x) | BIT_MCUDMSG_I_8197F(v)) + + +/* 2 REG_MCUTST_II_8197F */ + +#define BIT_SHIFT_MCUDMSG_II_8197F 0 +#define BIT_MASK_MCUDMSG_II_8197F 0xffffffffL +#define BIT_MCUDMSG_II_8197F(x) (((x) & BIT_MASK_MCUDMSG_II_8197F) << BIT_SHIFT_MCUDMSG_II_8197F) +#define BITS_MCUDMSG_II_8197F (BIT_MASK_MCUDMSG_II_8197F << BIT_SHIFT_MCUDMSG_II_8197F) +#define BIT_CLEAR_MCUDMSG_II_8197F(x) ((x) & (~BITS_MCUDMSG_II_8197F)) +#define BIT_GET_MCUDMSG_II_8197F(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8197F) & BIT_MASK_MCUDMSG_II_8197F) +#define BIT_SET_MCUDMSG_II_8197F(x, v) (BIT_CLEAR_MCUDMSG_II_8197F(x) | BIT_MCUDMSG_II_8197F(v)) + + +/* 2 REG_FMETHR_8197F */ +#define BIT_FMSG_INT_8197F BIT(31) + +#define BIT_SHIFT_FW_MSG_8197F 0 +#define BIT_MASK_FW_MSG_8197F 0xffffffffL +#define BIT_FW_MSG_8197F(x) (((x) & BIT_MASK_FW_MSG_8197F) << BIT_SHIFT_FW_MSG_8197F) +#define BITS_FW_MSG_8197F (BIT_MASK_FW_MSG_8197F << BIT_SHIFT_FW_MSG_8197F) +#define BIT_CLEAR_FW_MSG_8197F(x) ((x) & (~BITS_FW_MSG_8197F)) +#define BIT_GET_FW_MSG_8197F(x) (((x) >> BIT_SHIFT_FW_MSG_8197F) & BIT_MASK_FW_MSG_8197F) +#define BIT_SET_FW_MSG_8197F(x, v) (BIT_CLEAR_FW_MSG_8197F(x) | BIT_FW_MSG_8197F(v)) + + +/* 2 REG_HMETFR_8197F */ + +#define BIT_SHIFT_HRCV_MSG_8197F 24 +#define BIT_MASK_HRCV_MSG_8197F 0xff +#define BIT_HRCV_MSG_8197F(x) (((x) & BIT_MASK_HRCV_MSG_8197F) << BIT_SHIFT_HRCV_MSG_8197F) +#define BITS_HRCV_MSG_8197F (BIT_MASK_HRCV_MSG_8197F << BIT_SHIFT_HRCV_MSG_8197F) +#define BIT_CLEAR_HRCV_MSG_8197F(x) ((x) & (~BITS_HRCV_MSG_8197F)) +#define BIT_GET_HRCV_MSG_8197F(x) (((x) >> BIT_SHIFT_HRCV_MSG_8197F) & BIT_MASK_HRCV_MSG_8197F) +#define BIT_SET_HRCV_MSG_8197F(x, v) (BIT_CLEAR_HRCV_MSG_8197F(x) | BIT_HRCV_MSG_8197F(v)) + +#define BIT_INT_BOX3_8197F BIT(3) +#define BIT_INT_BOX2_8197F BIT(2) +#define BIT_INT_BOX1_8197F BIT(1) +#define BIT_INT_BOX0_8197F BIT(0) + +/* 2 REG_HMEBOX0_8197F */ + +#define BIT_SHIFT_HOST_MSG_0_8197F 0 +#define BIT_MASK_HOST_MSG_0_8197F 0xffffffffL +#define BIT_HOST_MSG_0_8197F(x) (((x) & BIT_MASK_HOST_MSG_0_8197F) << BIT_SHIFT_HOST_MSG_0_8197F) +#define BITS_HOST_MSG_0_8197F (BIT_MASK_HOST_MSG_0_8197F << BIT_SHIFT_HOST_MSG_0_8197F) +#define BIT_CLEAR_HOST_MSG_0_8197F(x) ((x) & (~BITS_HOST_MSG_0_8197F)) +#define BIT_GET_HOST_MSG_0_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8197F) & BIT_MASK_HOST_MSG_0_8197F) +#define BIT_SET_HOST_MSG_0_8197F(x, v) (BIT_CLEAR_HOST_MSG_0_8197F(x) | BIT_HOST_MSG_0_8197F(v)) + + +/* 2 REG_HMEBOX1_8197F */ + +#define BIT_SHIFT_HOST_MSG_1_8197F 0 +#define BIT_MASK_HOST_MSG_1_8197F 0xffffffffL +#define BIT_HOST_MSG_1_8197F(x) (((x) & BIT_MASK_HOST_MSG_1_8197F) << BIT_SHIFT_HOST_MSG_1_8197F) +#define BITS_HOST_MSG_1_8197F (BIT_MASK_HOST_MSG_1_8197F << BIT_SHIFT_HOST_MSG_1_8197F) +#define BIT_CLEAR_HOST_MSG_1_8197F(x) ((x) & (~BITS_HOST_MSG_1_8197F)) +#define BIT_GET_HOST_MSG_1_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8197F) & BIT_MASK_HOST_MSG_1_8197F) +#define BIT_SET_HOST_MSG_1_8197F(x, v) (BIT_CLEAR_HOST_MSG_1_8197F(x) | BIT_HOST_MSG_1_8197F(v)) + + +/* 2 REG_HMEBOX2_8197F */ + +#define BIT_SHIFT_HOST_MSG_2_8197F 0 +#define BIT_MASK_HOST_MSG_2_8197F 0xffffffffL +#define BIT_HOST_MSG_2_8197F(x) (((x) & BIT_MASK_HOST_MSG_2_8197F) << BIT_SHIFT_HOST_MSG_2_8197F) +#define BITS_HOST_MSG_2_8197F (BIT_MASK_HOST_MSG_2_8197F << BIT_SHIFT_HOST_MSG_2_8197F) +#define BIT_CLEAR_HOST_MSG_2_8197F(x) ((x) & (~BITS_HOST_MSG_2_8197F)) +#define BIT_GET_HOST_MSG_2_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8197F) & BIT_MASK_HOST_MSG_2_8197F) +#define BIT_SET_HOST_MSG_2_8197F(x, v) (BIT_CLEAR_HOST_MSG_2_8197F(x) | BIT_HOST_MSG_2_8197F(v)) + + +/* 2 REG_HMEBOX3_8197F */ + +#define BIT_SHIFT_HOST_MSG_3_8197F 0 +#define BIT_MASK_HOST_MSG_3_8197F 0xffffffffL +#define BIT_HOST_MSG_3_8197F(x) (((x) & BIT_MASK_HOST_MSG_3_8197F) << BIT_SHIFT_HOST_MSG_3_8197F) +#define BITS_HOST_MSG_3_8197F (BIT_MASK_HOST_MSG_3_8197F << BIT_SHIFT_HOST_MSG_3_8197F) +#define BIT_CLEAR_HOST_MSG_3_8197F(x) ((x) & (~BITS_HOST_MSG_3_8197F)) +#define BIT_GET_HOST_MSG_3_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8197F) & BIT_MASK_HOST_MSG_3_8197F) +#define BIT_SET_HOST_MSG_3_8197F(x, v) (BIT_CLEAR_HOST_MSG_3_8197F(x) | BIT_HOST_MSG_3_8197F(v)) + + +/* 2 REG_LLT_INIT_8197F */ + +#define BIT_SHIFT_LLTE_RWM_8197F 30 +#define BIT_MASK_LLTE_RWM_8197F 0x3 +#define BIT_LLTE_RWM_8197F(x) (((x) & BIT_MASK_LLTE_RWM_8197F) << BIT_SHIFT_LLTE_RWM_8197F) +#define BITS_LLTE_RWM_8197F (BIT_MASK_LLTE_RWM_8197F << BIT_SHIFT_LLTE_RWM_8197F) +#define BIT_CLEAR_LLTE_RWM_8197F(x) ((x) & (~BITS_LLTE_RWM_8197F)) +#define BIT_GET_LLTE_RWM_8197F(x) (((x) >> BIT_SHIFT_LLTE_RWM_8197F) & BIT_MASK_LLTE_RWM_8197F) +#define BIT_SET_LLTE_RWM_8197F(x, v) (BIT_CLEAR_LLTE_RWM_8197F(x) | BIT_LLTE_RWM_8197F(v)) + + +#define BIT_SHIFT_LLTINI_PDATA_V1_8197F 16 +#define BIT_MASK_LLTINI_PDATA_V1_8197F 0xfff +#define BIT_LLTINI_PDATA_V1_8197F(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8197F) << BIT_SHIFT_LLTINI_PDATA_V1_8197F) +#define BITS_LLTINI_PDATA_V1_8197F (BIT_MASK_LLTINI_PDATA_V1_8197F << BIT_SHIFT_LLTINI_PDATA_V1_8197F) +#define BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) ((x) & (~BITS_LLTINI_PDATA_V1_8197F)) +#define BIT_GET_LLTINI_PDATA_V1_8197F(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8197F) & BIT_MASK_LLTINI_PDATA_V1_8197F) +#define BIT_SET_LLTINI_PDATA_V1_8197F(x, v) (BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) | BIT_LLTINI_PDATA_V1_8197F(v)) + + +#define BIT_SHIFT_LLTINI_HDATA_V1_8197F 0 +#define BIT_MASK_LLTINI_HDATA_V1_8197F 0xfff +#define BIT_LLTINI_HDATA_V1_8197F(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8197F) << BIT_SHIFT_LLTINI_HDATA_V1_8197F) +#define BITS_LLTINI_HDATA_V1_8197F (BIT_MASK_LLTINI_HDATA_V1_8197F << BIT_SHIFT_LLTINI_HDATA_V1_8197F) +#define BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) ((x) & (~BITS_LLTINI_HDATA_V1_8197F)) +#define BIT_GET_LLTINI_HDATA_V1_8197F(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8197F) & BIT_MASK_LLTINI_HDATA_V1_8197F) +#define BIT_SET_LLTINI_HDATA_V1_8197F(x, v) (BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) | BIT_LLTINI_HDATA_V1_8197F(v)) + + +/* 2 REG_LLT_INIT_ADDR_8197F */ + +#define BIT_SHIFT_LLTINI_ADDR_V1_8197F 0 +#define BIT_MASK_LLTINI_ADDR_V1_8197F 0xfff +#define BIT_LLTINI_ADDR_V1_8197F(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8197F) << BIT_SHIFT_LLTINI_ADDR_V1_8197F) +#define BITS_LLTINI_ADDR_V1_8197F (BIT_MASK_LLTINI_ADDR_V1_8197F << BIT_SHIFT_LLTINI_ADDR_V1_8197F) +#define BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) ((x) & (~BITS_LLTINI_ADDR_V1_8197F)) +#define BIT_GET_LLTINI_ADDR_V1_8197F(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8197F) & BIT_MASK_LLTINI_ADDR_V1_8197F) +#define BIT_SET_LLTINI_ADDR_V1_8197F(x, v) (BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) | BIT_LLTINI_ADDR_V1_8197F(v)) + + +/* 2 REG_BB_ACCESS_CTRL_8197F */ + +#define BIT_SHIFT_BB_WRITE_READ_8197F 30 +#define BIT_MASK_BB_WRITE_READ_8197F 0x3 +#define BIT_BB_WRITE_READ_8197F(x) (((x) & BIT_MASK_BB_WRITE_READ_8197F) << BIT_SHIFT_BB_WRITE_READ_8197F) +#define BITS_BB_WRITE_READ_8197F (BIT_MASK_BB_WRITE_READ_8197F << BIT_SHIFT_BB_WRITE_READ_8197F) +#define BIT_CLEAR_BB_WRITE_READ_8197F(x) ((x) & (~BITS_BB_WRITE_READ_8197F)) +#define BIT_GET_BB_WRITE_READ_8197F(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8197F) & BIT_MASK_BB_WRITE_READ_8197F) +#define BIT_SET_BB_WRITE_READ_8197F(x, v) (BIT_CLEAR_BB_WRITE_READ_8197F(x) | BIT_BB_WRITE_READ_8197F(v)) + + +#define BIT_SHIFT_BB_WRITE_EN_V1_8197F 16 +#define BIT_MASK_BB_WRITE_EN_V1_8197F 0xf +#define BIT_BB_WRITE_EN_V1_8197F(x) (((x) & BIT_MASK_BB_WRITE_EN_V1_8197F) << BIT_SHIFT_BB_WRITE_EN_V1_8197F) +#define BITS_BB_WRITE_EN_V1_8197F (BIT_MASK_BB_WRITE_EN_V1_8197F << BIT_SHIFT_BB_WRITE_EN_V1_8197F) +#define BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) ((x) & (~BITS_BB_WRITE_EN_V1_8197F)) +#define BIT_GET_BB_WRITE_EN_V1_8197F(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_V1_8197F) & BIT_MASK_BB_WRITE_EN_V1_8197F) +#define BIT_SET_BB_WRITE_EN_V1_8197F(x, v) (BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) | BIT_BB_WRITE_EN_V1_8197F(v)) + + +#define BIT_SHIFT_BB_ADDR_V1_8197F 2 +#define BIT_MASK_BB_ADDR_V1_8197F 0xfff +#define BIT_BB_ADDR_V1_8197F(x) (((x) & BIT_MASK_BB_ADDR_V1_8197F) << BIT_SHIFT_BB_ADDR_V1_8197F) +#define BITS_BB_ADDR_V1_8197F (BIT_MASK_BB_ADDR_V1_8197F << BIT_SHIFT_BB_ADDR_V1_8197F) +#define BIT_CLEAR_BB_ADDR_V1_8197F(x) ((x) & (~BITS_BB_ADDR_V1_8197F)) +#define BIT_GET_BB_ADDR_V1_8197F(x) (((x) >> BIT_SHIFT_BB_ADDR_V1_8197F) & BIT_MASK_BB_ADDR_V1_8197F) +#define BIT_SET_BB_ADDR_V1_8197F(x, v) (BIT_CLEAR_BB_ADDR_V1_8197F(x) | BIT_BB_ADDR_V1_8197F(v)) + +#define BIT_BB_ERRACC_8197F BIT(0) + +/* 2 REG_BB_ACCESS_DATA_8197F */ + +#define BIT_SHIFT_BB_DATA_8197F 0 +#define BIT_MASK_BB_DATA_8197F 0xffffffffL +#define BIT_BB_DATA_8197F(x) (((x) & BIT_MASK_BB_DATA_8197F) << BIT_SHIFT_BB_DATA_8197F) +#define BITS_BB_DATA_8197F (BIT_MASK_BB_DATA_8197F << BIT_SHIFT_BB_DATA_8197F) +#define BIT_CLEAR_BB_DATA_8197F(x) ((x) & (~BITS_BB_DATA_8197F)) +#define BIT_GET_BB_DATA_8197F(x) (((x) >> BIT_SHIFT_BB_DATA_8197F) & BIT_MASK_BB_DATA_8197F) +#define BIT_SET_BB_DATA_8197F(x, v) (BIT_CLEAR_BB_DATA_8197F(x) | BIT_BB_DATA_8197F(v)) + + +/* 2 REG_HMEBOX_E0_8197F */ + +#define BIT_SHIFT_HMEBOX_E0_8197F 0 +#define BIT_MASK_HMEBOX_E0_8197F 0xffffffffL +#define BIT_HMEBOX_E0_8197F(x) (((x) & BIT_MASK_HMEBOX_E0_8197F) << BIT_SHIFT_HMEBOX_E0_8197F) +#define BITS_HMEBOX_E0_8197F (BIT_MASK_HMEBOX_E0_8197F << BIT_SHIFT_HMEBOX_E0_8197F) +#define BIT_CLEAR_HMEBOX_E0_8197F(x) ((x) & (~BITS_HMEBOX_E0_8197F)) +#define BIT_GET_HMEBOX_E0_8197F(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8197F) & BIT_MASK_HMEBOX_E0_8197F) +#define BIT_SET_HMEBOX_E0_8197F(x, v) (BIT_CLEAR_HMEBOX_E0_8197F(x) | BIT_HMEBOX_E0_8197F(v)) + + +/* 2 REG_HMEBOX_E1_8197F */ + +#define BIT_SHIFT_HMEBOX_E1_8197F 0 +#define BIT_MASK_HMEBOX_E1_8197F 0xffffffffL +#define BIT_HMEBOX_E1_8197F(x) (((x) & BIT_MASK_HMEBOX_E1_8197F) << BIT_SHIFT_HMEBOX_E1_8197F) +#define BITS_HMEBOX_E1_8197F (BIT_MASK_HMEBOX_E1_8197F << BIT_SHIFT_HMEBOX_E1_8197F) +#define BIT_CLEAR_HMEBOX_E1_8197F(x) ((x) & (~BITS_HMEBOX_E1_8197F)) +#define BIT_GET_HMEBOX_E1_8197F(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8197F) & BIT_MASK_HMEBOX_E1_8197F) +#define BIT_SET_HMEBOX_E1_8197F(x, v) (BIT_CLEAR_HMEBOX_E1_8197F(x) | BIT_HMEBOX_E1_8197F(v)) + + +/* 2 REG_HMEBOX_E2_8197F */ + +#define BIT_SHIFT_HMEBOX_E2_8197F 0 +#define BIT_MASK_HMEBOX_E2_8197F 0xffffffffL +#define BIT_HMEBOX_E2_8197F(x) (((x) & BIT_MASK_HMEBOX_E2_8197F) << BIT_SHIFT_HMEBOX_E2_8197F) +#define BITS_HMEBOX_E2_8197F (BIT_MASK_HMEBOX_E2_8197F << BIT_SHIFT_HMEBOX_E2_8197F) +#define BIT_CLEAR_HMEBOX_E2_8197F(x) ((x) & (~BITS_HMEBOX_E2_8197F)) +#define BIT_GET_HMEBOX_E2_8197F(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8197F) & BIT_MASK_HMEBOX_E2_8197F) +#define BIT_SET_HMEBOX_E2_8197F(x, v) (BIT_CLEAR_HMEBOX_E2_8197F(x) | BIT_HMEBOX_E2_8197F(v)) + + +/* 2 REG_HMEBOX_E3_8197F */ + +#define BIT_SHIFT_HMEBOX_E3_8197F 0 +#define BIT_MASK_HMEBOX_E3_8197F 0xffffffffL +#define BIT_HMEBOX_E3_8197F(x) (((x) & BIT_MASK_HMEBOX_E3_8197F) << BIT_SHIFT_HMEBOX_E3_8197F) +#define BITS_HMEBOX_E3_8197F (BIT_MASK_HMEBOX_E3_8197F << BIT_SHIFT_HMEBOX_E3_8197F) +#define BIT_CLEAR_HMEBOX_E3_8197F(x) ((x) & (~BITS_HMEBOX_E3_8197F)) +#define BIT_GET_HMEBOX_E3_8197F(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8197F) & BIT_MASK_HMEBOX_E3_8197F) +#define BIT_SET_HMEBOX_E3_8197F(x, v) (BIT_CLEAR_HMEBOX_E3_8197F(x) | BIT_HMEBOX_E3_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_CR_EXT_8197F */ + +#define BIT_SHIFT_PHY_REQ_DELAY_8197F 24 +#define BIT_MASK_PHY_REQ_DELAY_8197F 0xf +#define BIT_PHY_REQ_DELAY_8197F(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8197F) << BIT_SHIFT_PHY_REQ_DELAY_8197F) +#define BITS_PHY_REQ_DELAY_8197F (BIT_MASK_PHY_REQ_DELAY_8197F << BIT_SHIFT_PHY_REQ_DELAY_8197F) +#define BIT_CLEAR_PHY_REQ_DELAY_8197F(x) ((x) & (~BITS_PHY_REQ_DELAY_8197F)) +#define BIT_GET_PHY_REQ_DELAY_8197F(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8197F) & BIT_MASK_PHY_REQ_DELAY_8197F) +#define BIT_SET_PHY_REQ_DELAY_8197F(x, v) (BIT_CLEAR_PHY_REQ_DELAY_8197F(x) | BIT_PHY_REQ_DELAY_8197F(v)) + +#define BIT_SPD_DOWN_8197F BIT(16) + +#define BIT_SHIFT_NETYPE4_8197F 4 +#define BIT_MASK_NETYPE4_8197F 0x3 +#define BIT_NETYPE4_8197F(x) (((x) & BIT_MASK_NETYPE4_8197F) << BIT_SHIFT_NETYPE4_8197F) +#define BITS_NETYPE4_8197F (BIT_MASK_NETYPE4_8197F << BIT_SHIFT_NETYPE4_8197F) +#define BIT_CLEAR_NETYPE4_8197F(x) ((x) & (~BITS_NETYPE4_8197F)) +#define BIT_GET_NETYPE4_8197F(x) (((x) >> BIT_SHIFT_NETYPE4_8197F) & BIT_MASK_NETYPE4_8197F) +#define BIT_SET_NETYPE4_8197F(x, v) (BIT_CLEAR_NETYPE4_8197F(x) | BIT_NETYPE4_8197F(v)) + + +#define BIT_SHIFT_NETYPE3_8197F 2 +#define BIT_MASK_NETYPE3_8197F 0x3 +#define BIT_NETYPE3_8197F(x) (((x) & BIT_MASK_NETYPE3_8197F) << BIT_SHIFT_NETYPE3_8197F) +#define BITS_NETYPE3_8197F (BIT_MASK_NETYPE3_8197F << BIT_SHIFT_NETYPE3_8197F) +#define BIT_CLEAR_NETYPE3_8197F(x) ((x) & (~BITS_NETYPE3_8197F)) +#define BIT_GET_NETYPE3_8197F(x) (((x) >> BIT_SHIFT_NETYPE3_8197F) & BIT_MASK_NETYPE3_8197F) +#define BIT_SET_NETYPE3_8197F(x, v) (BIT_CLEAR_NETYPE3_8197F(x) | BIT_NETYPE3_8197F(v)) + + +#define BIT_SHIFT_NETYPE2_8197F 0 +#define BIT_MASK_NETYPE2_8197F 0x3 +#define BIT_NETYPE2_8197F(x) (((x) & BIT_MASK_NETYPE2_8197F) << BIT_SHIFT_NETYPE2_8197F) +#define BITS_NETYPE2_8197F (BIT_MASK_NETYPE2_8197F << BIT_SHIFT_NETYPE2_8197F) +#define BIT_CLEAR_NETYPE2_8197F(x) ((x) & (~BITS_NETYPE2_8197F)) +#define BIT_GET_NETYPE2_8197F(x) (((x) >> BIT_SHIFT_NETYPE2_8197F) & BIT_MASK_NETYPE2_8197F) +#define BIT_SET_NETYPE2_8197F(x, v) (BIT_CLEAR_NETYPE2_8197F(x) | BIT_NETYPE2_8197F(v)) + + +/* 2 REG_FWFF_8197F */ + +#define BIT_SHIFT_PKTNUM_TH_8197F 24 +#define BIT_MASK_PKTNUM_TH_8197F 0xff +#define BIT_PKTNUM_TH_8197F(x) (((x) & BIT_MASK_PKTNUM_TH_8197F) << BIT_SHIFT_PKTNUM_TH_8197F) +#define BITS_PKTNUM_TH_8197F (BIT_MASK_PKTNUM_TH_8197F << BIT_SHIFT_PKTNUM_TH_8197F) +#define BIT_CLEAR_PKTNUM_TH_8197F(x) ((x) & (~BITS_PKTNUM_TH_8197F)) +#define BIT_GET_PKTNUM_TH_8197F(x) (((x) >> BIT_SHIFT_PKTNUM_TH_8197F) & BIT_MASK_PKTNUM_TH_8197F) +#define BIT_SET_PKTNUM_TH_8197F(x, v) (BIT_CLEAR_PKTNUM_TH_8197F(x) | BIT_PKTNUM_TH_8197F(v)) + + +#define BIT_SHIFT_TIMER_TH_8197F 16 +#define BIT_MASK_TIMER_TH_8197F 0xff +#define BIT_TIMER_TH_8197F(x) (((x) & BIT_MASK_TIMER_TH_8197F) << BIT_SHIFT_TIMER_TH_8197F) +#define BITS_TIMER_TH_8197F (BIT_MASK_TIMER_TH_8197F << BIT_SHIFT_TIMER_TH_8197F) +#define BIT_CLEAR_TIMER_TH_8197F(x) ((x) & (~BITS_TIMER_TH_8197F)) +#define BIT_GET_TIMER_TH_8197F(x) (((x) >> BIT_SHIFT_TIMER_TH_8197F) & BIT_MASK_TIMER_TH_8197F) +#define BIT_SET_TIMER_TH_8197F(x, v) (BIT_CLEAR_TIMER_TH_8197F(x) | BIT_TIMER_TH_8197F(v)) + + +#define BIT_SHIFT_RXPKT1ENADDR_8197F 0 +#define BIT_MASK_RXPKT1ENADDR_8197F 0xffff +#define BIT_RXPKT1ENADDR_8197F(x) (((x) & BIT_MASK_RXPKT1ENADDR_8197F) << BIT_SHIFT_RXPKT1ENADDR_8197F) +#define BITS_RXPKT1ENADDR_8197F (BIT_MASK_RXPKT1ENADDR_8197F << BIT_SHIFT_RXPKT1ENADDR_8197F) +#define BIT_CLEAR_RXPKT1ENADDR_8197F(x) ((x) & (~BITS_RXPKT1ENADDR_8197F)) +#define BIT_GET_RXPKT1ENADDR_8197F(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8197F) & BIT_MASK_RXPKT1ENADDR_8197F) +#define BIT_SET_RXPKT1ENADDR_8197F(x, v) (BIT_CLEAR_RXPKT1ENADDR_8197F(x) | BIT_RXPKT1ENADDR_8197F(v)) + + +/* 2 REG_RXFF_PTR_V1_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_RXFF0_RDPTR_V2_8197F 0 +#define BIT_MASK_RXFF0_RDPTR_V2_8197F 0x3ffff +#define BIT_RXFF0_RDPTR_V2_8197F(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8197F) << BIT_SHIFT_RXFF0_RDPTR_V2_8197F) +#define BITS_RXFF0_RDPTR_V2_8197F (BIT_MASK_RXFF0_RDPTR_V2_8197F << BIT_SHIFT_RXFF0_RDPTR_V2_8197F) +#define BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8197F)) +#define BIT_GET_RXFF0_RDPTR_V2_8197F(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8197F) & BIT_MASK_RXFF0_RDPTR_V2_8197F) +#define BIT_SET_RXFF0_RDPTR_V2_8197F(x, v) (BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) | BIT_RXFF0_RDPTR_V2_8197F(v)) + + +/* 2 REG_RXFF_WTR_V1_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_RXFF0_WTPTR_V2_8197F 0 +#define BIT_MASK_RXFF0_WTPTR_V2_8197F 0x3ffff +#define BIT_RXFF0_WTPTR_V2_8197F(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8197F) << BIT_SHIFT_RXFF0_WTPTR_V2_8197F) +#define BITS_RXFF0_WTPTR_V2_8197F (BIT_MASK_RXFF0_WTPTR_V2_8197F << BIT_SHIFT_RXFF0_WTPTR_V2_8197F) +#define BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8197F)) +#define BIT_GET_RXFF0_WTPTR_V2_8197F(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8197F) & BIT_MASK_RXFF0_WTPTR_V2_8197F) +#define BIT_SET_RXFF0_WTPTR_V2_8197F(x, v) (BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) | BIT_RXFF0_WTPTR_V2_8197F(v)) + + +/* 2 REG_FE2IMR_8197F */ +#define BIT_FS_TXSC_DESC_DONE_INT_EN_8197F BIT(28) +#define BIT_FS_TXSC_BKDONE_INT_EN_8197F BIT(27) +#define BIT_FS_TXSC_BEDONE_INT_EN_8197F BIT(26) +#define BIT_FS_TXSC_VIDONE_INT_EN_8197F BIT(25) +#define BIT_FS_TXSC_VODONE_INT_EN_8197F BIT(24) +#define BIT_FS_ATIM_MB7_INT_EN_8197F BIT(23) +#define BIT_FS_ATIM_MB6_INT_EN_8197F BIT(22) +#define BIT_FS_ATIM_MB5_INT_EN_8197F BIT(21) +#define BIT_FS_ATIM_MB4_INT_EN_8197F BIT(20) +#define BIT_FS_ATIM_MB3_INT_EN_8197F BIT(19) +#define BIT_FS_ATIM_MB2_INT_EN_8197F BIT(18) +#define BIT_FS_ATIM_MB1_INT_EN_8197F BIT(17) +#define BIT_FS_ATIM_MB0_INT_EN_8197F BIT(16) +#define BIT_FS_TBTT4INT_EN_8197F BIT(11) +#define BIT_FS_TBTT3INT_EN_8197F BIT(10) +#define BIT_FS_TBTT2INT_EN_8197F BIT(9) +#define BIT_FS_TBTT1INT_EN_8197F BIT(8) +#define BIT_FS_TBTT0_MB7INT_EN_8197F BIT(7) +#define BIT_FS_TBTT0_MB6INT_EN_8197F BIT(6) +#define BIT_FS_TBTT0_MB5INT_EN_8197F BIT(5) +#define BIT_FS_TBTT0_MB4INT_EN_8197F BIT(4) +#define BIT_FS_TBTT0_MB3INT_EN_8197F BIT(3) +#define BIT_FS_TBTT0_MB2INT_EN_8197F BIT(2) +#define BIT_FS_TBTT0_MB1INT_EN_8197F BIT(1) +#define BIT_FS_TBTT0_INT_EN_8197F BIT(0) + +/* 2 REG_FE2ISR_8197F */ +#define BIT_FS_TXSC_DESC_DONE_INT_8197F BIT(28) +#define BIT_FS_TXSC_BKDONE_INT_8197F BIT(27) +#define BIT_FS_TXSC_BEDONE_INT_8197F BIT(26) +#define BIT_FS_TXSC_VIDONE_INT_8197F BIT(25) +#define BIT_FS_TXSC_VODONE_INT_8197F BIT(24) +#define BIT_FS_ATIM_MB7_INT_8197F BIT(23) +#define BIT_FS_ATIM_MB6_INT_8197F BIT(22) +#define BIT_FS_ATIM_MB5_INT_8197F BIT(21) +#define BIT_FS_ATIM_MB4_INT_8197F BIT(20) +#define BIT_FS_ATIM_MB3_INT_8197F BIT(19) +#define BIT_FS_ATIM_MB2_INT_8197F BIT(18) +#define BIT_FS_ATIM_MB1_INT_8197F BIT(17) +#define BIT_FS_ATIM_MB0_INT_8197F BIT(16) +#define BIT_FS_TBTT4INT_8197F BIT(11) +#define BIT_FS_TBTT3INT_8197F BIT(10) +#define BIT_FS_TBTT2INT_8197F BIT(9) +#define BIT_FS_TBTT1INT_8197F BIT(8) +#define BIT_FS_TBTT0_MB7INT_8197F BIT(7) +#define BIT_FS_TBTT0_MB6INT_8197F BIT(6) +#define BIT_FS_TBTT0_MB5INT_8197F BIT(5) +#define BIT_FS_TBTT0_MB4INT_8197F BIT(4) +#define BIT_FS_TBTT0_MB3INT_8197F BIT(3) +#define BIT_FS_TBTT0_MB2INT_8197F BIT(2) +#define BIT_FS_TBTT0_MB1INT_8197F BIT(1) +#define BIT_FS_TBTT0_INT_8197F BIT(0) + +/* 2 REG_FE3IMR_8197F */ +#define BIT_FS_BCNELY4_AGGR_INT_EN_8197F BIT(31) +#define BIT_FS_BCNELY3_AGGR_INT_EN_8197F BIT(30) +#define BIT_FS_BCNELY2_AGGR_INT_EN_8197F BIT(29) +#define BIT_FS_BCNELY1_AGGR_INT_EN_8197F BIT(28) +#define BIT_FS_BCNDMA4_INT_EN_8197F BIT(27) +#define BIT_FS_BCNDMA3_INT_EN_8197F BIT(26) +#define BIT_FS_BCNDMA2_INT_EN_8197F BIT(25) +#define BIT_FS_BCNDMA1_INT_EN_8197F BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT_EN_8197F BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT_EN_8197F BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT_EN_8197F BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT_EN_8197F BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT_EN_8197F BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT_EN_8197F BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT_EN_8197F BIT(17) +#define BIT_FS_BCNDMA0_INT_EN_8197F BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8197F BIT(15) +#define BIT_FS_BCNERLY4_INT_EN_8197F BIT(11) +#define BIT_FS_BCNERLY3_INT_EN_8197F BIT(10) +#define BIT_FS_BCNERLY2_INT_EN_8197F BIT(9) +#define BIT_FS_BCNERLY1_INT_EN_8197F BIT(8) +#define BIT_FS_BCNERLY0_MB7INT_EN_8197F BIT(7) +#define BIT_FS_BCNERLY0_MB6INT_EN_8197F BIT(6) +#define BIT_FS_BCNERLY0_MB5INT_EN_8197F BIT(5) +#define BIT_FS_BCNERLY0_MB4INT_EN_8197F BIT(4) +#define BIT_FS_BCNERLY0_MB3INT_EN_8197F BIT(3) +#define BIT_FS_BCNERLY0_MB2INT_EN_8197F BIT(2) +#define BIT_FS_BCNERLY0_MB1INT_EN_8197F BIT(1) +#define BIT_FS_BCNERLY0_INT_EN_8197F BIT(0) + +/* 2 REG_FE3ISR_8197F */ +#define BIT_FS_BCNELY4_AGGR_INT_8197F BIT(31) +#define BIT_FS_BCNELY3_AGGR_INT_8197F BIT(30) +#define BIT_FS_BCNELY2_AGGR_INT_8197F BIT(29) +#define BIT_FS_BCNELY1_AGGR_INT_8197F BIT(28) +#define BIT_FS_BCNDMA4_INT_8197F BIT(27) +#define BIT_FS_BCNDMA3_INT_8197F BIT(26) +#define BIT_FS_BCNDMA2_INT_8197F BIT(25) +#define BIT_FS_BCNDMA1_INT_8197F BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT_8197F BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT_8197F BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT_8197F BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT_8197F BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT_8197F BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT_8197F BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT_8197F BIT(17) +#define BIT_FS_BCNDMA0_INT_8197F BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT_8197F BIT(15) +#define BIT_FS_BCNERLY4_INT_8197F BIT(11) +#define BIT_FS_BCNERLY3_INT_8197F BIT(10) +#define BIT_FS_BCNERLY2_INT_8197F BIT(9) +#define BIT_FS_BCNERLY1_INT_8197F BIT(8) +#define BIT_FS_BCNERLY0_MB7INT_8197F BIT(7) +#define BIT_FS_BCNERLY0_MB6INT_8197F BIT(6) +#define BIT_FS_BCNERLY0_MB5INT_8197F BIT(5) +#define BIT_FS_BCNERLY0_MB4INT_8197F BIT(4) +#define BIT_FS_BCNERLY0_MB3INT_8197F BIT(3) +#define BIT_FS_BCNERLY0_MB2INT_8197F BIT(2) +#define BIT_FS_BCNERLY0_MB1INT_8197F BIT(1) +#define BIT_FS_BCNERLY0_INT_8197F BIT(0) + +/* 2 REG_FE4IMR_8197F */ +#define BIT_PORT4_PKTIN_INT_EN_8197F BIT(19) +#define BIT_PORT3_PKTIN_INT_EN_8197F BIT(18) +#define BIT_PORT2_PKTIN_INT_EN_8197F BIT(17) +#define BIT_PORT1_PKTIN_INT_EN_8197F BIT(16) +#define BIT_PORT4_RXUCMD0_OK_INT_EN_8197F BIT(15) +#define BIT_PORT4_RXUCMD1_OK_INT_EN_8197F BIT(14) +#define BIT_PORT4_RXBCMD0_OK_INT_EN_8197F BIT(13) +#define BIT_PORT4_RXBCMD1_OK_INT_EN_8197F BIT(12) +#define BIT_PORT3_RXUCMD0_OK_INT_EN_8197F BIT(11) +#define BIT_PORT3_RXUCMD1_OK_INT_EN_8197F BIT(10) +#define BIT_PORT3_RXBCMD0_OK_INT_EN_8197F BIT(9) +#define BIT_PORT3_RXBCMD1_OK_INT_EN_8197F BIT(8) +#define BIT_PORT2_RXUCMD0_OK_INT_EN_8197F BIT(7) +#define BIT_PORT2_RXUCMD1_OK_INT_EN_8197F BIT(6) +#define BIT_PORT2_RXBCMD0_OK_INT_EN_8197F BIT(5) +#define BIT_PORT2_RXBCMD1_OK_INT_EN_8197F BIT(4) +#define BIT_PORT1_RXUCMD0_OK_INT_EN_8197F BIT(3) +#define BIT_PORT1_RXUCMD1_OK_INT_EN_8197F BIT(2) +#define BIT_PORT1_RXBCMD0_OK_INT_EN_8197F BIT(1) +#define BIT_PORT1_RXBCMD1_OK_INT_EN_8197F BIT(0) + +/* 2 REG_FE4ISR_8197F */ +#define BIT_PORT4_PKTIN_INT_8197F BIT(19) +#define BIT_PORT3_PKTIN_INT_8197F BIT(18) +#define BIT_PORT2_PKTIN_INT_8197F BIT(17) +#define BIT_PORT1_PKTIN_INT_8197F BIT(16) +#define BIT_PORT4_RXUCMD0_OK_INT_8197F BIT(15) +#define BIT_PORT4_RXUCMD1_OK_INT_8197F BIT(14) +#define BIT_PORT4_RXBCMD0_OK_INT_8197F BIT(13) +#define BIT_PORT4_RXBCMD1_OK_INT_8197F BIT(12) +#define BIT_PORT3_RXUCMD0_OK_INT_8197F BIT(11) +#define BIT_PORT3_RXUCMD1_OK_INT_8197F BIT(10) +#define BIT_PORT3_RXBCMD0_OK_INT_8197F BIT(9) +#define BIT_PORT3_RXBCMD1_OK_INT_8197F BIT(8) +#define BIT_PORT2_RXUCMD0_OK_INT_8197F BIT(7) +#define BIT_PORT2_RXUCMD1_OK_INT_8197F BIT(6) +#define BIT_PORT2_RXBCMD0_OK_INT_8197F BIT(5) +#define BIT_PORT2_RXBCMD1_OK_INT_8197F BIT(4) +#define BIT_PORT1_RXUCMD0_OK_INT_8197F BIT(3) +#define BIT_PORT1_RXUCMD1_OK_INT_8197F BIT(2) +#define BIT_PORT1_RXBCMD0_OK_INT_8197F BIT(1) +#define BIT_PORT1_RXBCMD1_OK_INT_8197F BIT(0) + +/* 2 REG_FT1IMR_8197F */ +#define BIT__FT2ISR__IND_MSK_8197F BIT(30) +#define BIT_FTM_PTT_INT_EN_8197F BIT(29) +#define BIT_RXFTMREQ_INT_EN_8197F BIT(28) +#define BIT_RXFTM_INT_EN_8197F BIT(27) +#define BIT_TXFTM_INT_EN_8197F BIT(26) +#define BIT_FS_H2C_CMD_OK_INT_EN_8197F BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT_EN_8197F BIT(24) +#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8197F BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8197F BIT(22) +#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8197F BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8197F BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8197F BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8197F BIT(18) +#define BIT_FS_CTWEND2_INT_EN_8197F BIT(17) +#define BIT_FS_CTWEND1_INT_EN_8197F BIT(16) +#define BIT_FS_CTWEND0_INT_EN_8197F BIT(15) +#define BIT_FS_TX_NULL1_INT_EN_8197F BIT(14) +#define BIT_FS_TX_NULL0_INT_EN_8197F BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_EN_8197F BIT(12) +#define BIT_FS_P2P_RFON2_INT_EN_8197F BIT(11) +#define BIT_FS_P2P_RFOFF2_INT_EN_8197F BIT(10) +#define BIT_FS_P2P_RFON1_INT_EN_8197F BIT(9) +#define BIT_FS_P2P_RFOFF1_INT_EN_8197F BIT(8) +#define BIT_FS_P2P_RFON0_INT_EN_8197F BIT(7) +#define BIT_FS_P2P_RFOFF0_INT_EN_8197F BIT(6) +#define BIT_FS_RX_UAPSDMD1_EN_8197F BIT(5) +#define BIT_FS_RX_UAPSDMD0_EN_8197F BIT(4) +#define BIT_FS_TRIGGER_PKT_EN_8197F BIT(3) +#define BIT_FS_EOSP_INT_EN_8197F BIT(2) +#define BIT_FS_RPWM2_INT_EN_8197F BIT(1) +#define BIT_FS_RPWM_INT_EN_8197F BIT(0) + +/* 2 REG_FT1ISR_8197F */ +#define BIT__FT2ISR__IND_INT_8197F BIT(30) +#define BIT_FTM_PTT_INT_8197F BIT(29) +#define BIT_RXFTMREQ_INT_8197F BIT(28) +#define BIT_RXFTM_INT_8197F BIT(27) +#define BIT_TXFTM_INT_8197F BIT(26) +#define BIT_FS_H2C_CMD_OK_INT_8197F BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT_8197F BIT(24) +#define BIT_FS_MACID_PWRCHANGE5_INT_8197F BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT_8197F BIT(22) +#define BIT_FS_MACID_PWRCHANGE3_INT_8197F BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT_8197F BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT_8197F BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT_8197F BIT(18) +#define BIT_FS_CTWEND2_INT_8197F BIT(17) +#define BIT_FS_CTWEND1_INT_8197F BIT(16) +#define BIT_FS_CTWEND0_INT_8197F BIT(15) +#define BIT_FS_TX_NULL1_INT_8197F BIT(14) +#define BIT_FS_TX_NULL0_INT_8197F BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_INT_8197F BIT(12) +#define BIT_FS_P2P_RFON2_INT_8197F BIT(11) +#define BIT_FS_P2P_RFOFF2_INT_8197F BIT(10) +#define BIT_FS_P2P_RFON1_INT_8197F BIT(9) +#define BIT_FS_P2P_RFOFF1_INT_8197F BIT(8) +#define BIT_FS_P2P_RFON0_INT_8197F BIT(7) +#define BIT_FS_P2P_RFOFF0_INT_8197F BIT(6) +#define BIT_FS_RX_UAPSDMD1_INT_8197F BIT(5) +#define BIT_FS_RX_UAPSDMD0_INT_8197F BIT(4) +#define BIT_FS_TRIGGER_PKT_INT_8197F BIT(3) +#define BIT_FS_EOSP_INT_8197F BIT(2) +#define BIT_FS_RPWM2_INT_8197F BIT(1) +#define BIT_FS_RPWM_INT_8197F BIT(0) + +/* 2 REG_SPWR0_8197F */ + +#define BIT_SHIFT_MID_31TO0_8197F 0 +#define BIT_MASK_MID_31TO0_8197F 0xffffffffL +#define BIT_MID_31TO0_8197F(x) (((x) & BIT_MASK_MID_31TO0_8197F) << BIT_SHIFT_MID_31TO0_8197F) +#define BITS_MID_31TO0_8197F (BIT_MASK_MID_31TO0_8197F << BIT_SHIFT_MID_31TO0_8197F) +#define BIT_CLEAR_MID_31TO0_8197F(x) ((x) & (~BITS_MID_31TO0_8197F)) +#define BIT_GET_MID_31TO0_8197F(x) (((x) >> BIT_SHIFT_MID_31TO0_8197F) & BIT_MASK_MID_31TO0_8197F) +#define BIT_SET_MID_31TO0_8197F(x, v) (BIT_CLEAR_MID_31TO0_8197F(x) | BIT_MID_31TO0_8197F(v)) + + +/* 2 REG_SPWR1_8197F */ + +#define BIT_SHIFT_MID_63TO32_8197F 0 +#define BIT_MASK_MID_63TO32_8197F 0xffffffffL +#define BIT_MID_63TO32_8197F(x) (((x) & BIT_MASK_MID_63TO32_8197F) << BIT_SHIFT_MID_63TO32_8197F) +#define BITS_MID_63TO32_8197F (BIT_MASK_MID_63TO32_8197F << BIT_SHIFT_MID_63TO32_8197F) +#define BIT_CLEAR_MID_63TO32_8197F(x) ((x) & (~BITS_MID_63TO32_8197F)) +#define BIT_GET_MID_63TO32_8197F(x) (((x) >> BIT_SHIFT_MID_63TO32_8197F) & BIT_MASK_MID_63TO32_8197F) +#define BIT_SET_MID_63TO32_8197F(x, v) (BIT_CLEAR_MID_63TO32_8197F(x) | BIT_MID_63TO32_8197F(v)) + + +/* 2 REG_SPWR2_8197F */ + +#define BIT_SHIFT_MID_95O64_8197F 0 +#define BIT_MASK_MID_95O64_8197F 0xffffffffL +#define BIT_MID_95O64_8197F(x) (((x) & BIT_MASK_MID_95O64_8197F) << BIT_SHIFT_MID_95O64_8197F) +#define BITS_MID_95O64_8197F (BIT_MASK_MID_95O64_8197F << BIT_SHIFT_MID_95O64_8197F) +#define BIT_CLEAR_MID_95O64_8197F(x) ((x) & (~BITS_MID_95O64_8197F)) +#define BIT_GET_MID_95O64_8197F(x) (((x) >> BIT_SHIFT_MID_95O64_8197F) & BIT_MASK_MID_95O64_8197F) +#define BIT_SET_MID_95O64_8197F(x, v) (BIT_CLEAR_MID_95O64_8197F(x) | BIT_MID_95O64_8197F(v)) + + +/* 2 REG_SPWR3_8197F */ + +#define BIT_SHIFT_MID_127TO96_8197F 0 +#define BIT_MASK_MID_127TO96_8197F 0xffffffffL +#define BIT_MID_127TO96_8197F(x) (((x) & BIT_MASK_MID_127TO96_8197F) << BIT_SHIFT_MID_127TO96_8197F) +#define BITS_MID_127TO96_8197F (BIT_MASK_MID_127TO96_8197F << BIT_SHIFT_MID_127TO96_8197F) +#define BIT_CLEAR_MID_127TO96_8197F(x) ((x) & (~BITS_MID_127TO96_8197F)) +#define BIT_GET_MID_127TO96_8197F(x) (((x) >> BIT_SHIFT_MID_127TO96_8197F) & BIT_MASK_MID_127TO96_8197F) +#define BIT_SET_MID_127TO96_8197F(x, v) (BIT_CLEAR_MID_127TO96_8197F(x) | BIT_MID_127TO96_8197F(v)) + + +/* 2 REG_POWSEQ_8197F */ + +#define BIT_SHIFT_SEQNUM_MID_8197F 16 +#define BIT_MASK_SEQNUM_MID_8197F 0xffff +#define BIT_SEQNUM_MID_8197F(x) (((x) & BIT_MASK_SEQNUM_MID_8197F) << BIT_SHIFT_SEQNUM_MID_8197F) +#define BITS_SEQNUM_MID_8197F (BIT_MASK_SEQNUM_MID_8197F << BIT_SHIFT_SEQNUM_MID_8197F) +#define BIT_CLEAR_SEQNUM_MID_8197F(x) ((x) & (~BITS_SEQNUM_MID_8197F)) +#define BIT_GET_SEQNUM_MID_8197F(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8197F) & BIT_MASK_SEQNUM_MID_8197F) +#define BIT_SET_SEQNUM_MID_8197F(x, v) (BIT_CLEAR_SEQNUM_MID_8197F(x) | BIT_SEQNUM_MID_8197F(v)) + + +#define BIT_SHIFT_REF_MID_8197F 0 +#define BIT_MASK_REF_MID_8197F 0x7f +#define BIT_REF_MID_8197F(x) (((x) & BIT_MASK_REF_MID_8197F) << BIT_SHIFT_REF_MID_8197F) +#define BITS_REF_MID_8197F (BIT_MASK_REF_MID_8197F << BIT_SHIFT_REF_MID_8197F) +#define BIT_CLEAR_REF_MID_8197F(x) ((x) & (~BITS_REF_MID_8197F)) +#define BIT_GET_REF_MID_8197F(x) (((x) >> BIT_SHIFT_REF_MID_8197F) & BIT_MASK_REF_MID_8197F) +#define BIT_SET_REF_MID_8197F(x, v) (BIT_CLEAR_REF_MID_8197F(x) | BIT_REF_MID_8197F(v)) + + +/* 2 REG_TC7_CTRL_V1_8197F */ +#define BIT_TC7INT_EN_8197F BIT(26) +#define BIT_TC7MODE_8197F BIT(25) +#define BIT_TC7EN_8197F BIT(24) + +#define BIT_SHIFT_TC7DATA_8197F 0 +#define BIT_MASK_TC7DATA_8197F 0xffffff +#define BIT_TC7DATA_8197F(x) (((x) & BIT_MASK_TC7DATA_8197F) << BIT_SHIFT_TC7DATA_8197F) +#define BITS_TC7DATA_8197F (BIT_MASK_TC7DATA_8197F << BIT_SHIFT_TC7DATA_8197F) +#define BIT_CLEAR_TC7DATA_8197F(x) ((x) & (~BITS_TC7DATA_8197F)) +#define BIT_GET_TC7DATA_8197F(x) (((x) >> BIT_SHIFT_TC7DATA_8197F) & BIT_MASK_TC7DATA_8197F) +#define BIT_SET_TC7DATA_8197F(x, v) (BIT_CLEAR_TC7DATA_8197F(x) | BIT_TC7DATA_8197F(v)) + + +/* 2 REG_TC8_CTRL_V1_8197F */ +#define BIT_TC8INT_EN_8197F BIT(26) +#define BIT_TC8MODE_8197F BIT(25) +#define BIT_TC8EN_8197F BIT(24) + +#define BIT_SHIFT_TC8DATA_8197F 0 +#define BIT_MASK_TC8DATA_8197F 0xffffff +#define BIT_TC8DATA_8197F(x) (((x) & BIT_MASK_TC8DATA_8197F) << BIT_SHIFT_TC8DATA_8197F) +#define BITS_TC8DATA_8197F (BIT_MASK_TC8DATA_8197F << BIT_SHIFT_TC8DATA_8197F) +#define BIT_CLEAR_TC8DATA_8197F(x) ((x) & (~BITS_TC8DATA_8197F)) +#define BIT_GET_TC8DATA_8197F(x) (((x) >> BIT_SHIFT_TC8DATA_8197F) & BIT_MASK_TC8DATA_8197F) +#define BIT_SET_TC8DATA_8197F(x, v) (BIT_CLEAR_TC8DATA_8197F(x) | BIT_TC8DATA_8197F(v)) + + +/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F */ + +/* 2 REG_RXBCN_TBTT_INTERVAL_PORT4_8197F */ + +/* 2 REG_EXT_QUEUE_REG_8197F */ + +#define BIT_SHIFT_PCIE_PRIORITY_SEL_8197F 0 +#define BIT_MASK_PCIE_PRIORITY_SEL_8197F 0x3 +#define BIT_PCIE_PRIORITY_SEL_8197F(x) (((x) & BIT_MASK_PCIE_PRIORITY_SEL_8197F) << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) +#define BITS_PCIE_PRIORITY_SEL_8197F (BIT_MASK_PCIE_PRIORITY_SEL_8197F << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) +#define BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) ((x) & (~BITS_PCIE_PRIORITY_SEL_8197F)) +#define BIT_GET_PCIE_PRIORITY_SEL_8197F(x) (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) & BIT_MASK_PCIE_PRIORITY_SEL_8197F) +#define BIT_SET_PCIE_PRIORITY_SEL_8197F(x, v) (BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) | BIT_PCIE_PRIORITY_SEL_8197F(v)) + + +/* 2 REG_COUNTER_CONTROL_8197F */ + +#define BIT_SHIFT_COUNTER_BASE_8197F 16 +#define BIT_MASK_COUNTER_BASE_8197F 0x1fff +#define BIT_COUNTER_BASE_8197F(x) (((x) & BIT_MASK_COUNTER_BASE_8197F) << BIT_SHIFT_COUNTER_BASE_8197F) +#define BITS_COUNTER_BASE_8197F (BIT_MASK_COUNTER_BASE_8197F << BIT_SHIFT_COUNTER_BASE_8197F) +#define BIT_CLEAR_COUNTER_BASE_8197F(x) ((x) & (~BITS_COUNTER_BASE_8197F)) +#define BIT_GET_COUNTER_BASE_8197F(x) (((x) >> BIT_SHIFT_COUNTER_BASE_8197F) & BIT_MASK_COUNTER_BASE_8197F) +#define BIT_SET_COUNTER_BASE_8197F(x, v) (BIT_CLEAR_COUNTER_BASE_8197F(x) | BIT_COUNTER_BASE_8197F(v)) + +#define BIT_EN_RTS_REQ_8197F BIT(9) +#define BIT_EN_EDCA_REQ_8197F BIT(8) +#define BIT_EN_PTCL_REQ_8197F BIT(7) +#define BIT_EN_SCH_REQ_8197F BIT(6) +#define BIT_EN_USB_CNT_8197F BIT(5) +#define BIT_EN_PCIE_CNT_8197F BIT(4) +#define BIT_RQPN_CNT_8197F BIT(3) +#define BIT_RDE_CNT_8197F BIT(2) +#define BIT_TDE_CNT_8197F BIT(1) +#define BIT_DIS_CNT_8197F BIT(0) + +/* 2 REG_COUNTER_TH_8197F */ +#define BIT_CNT_ALL_MACID_8197F BIT(31) + +#define BIT_SHIFT_CNT_MACID_8197F 24 +#define BIT_MASK_CNT_MACID_8197F 0x7f +#define BIT_CNT_MACID_8197F(x) (((x) & BIT_MASK_CNT_MACID_8197F) << BIT_SHIFT_CNT_MACID_8197F) +#define BITS_CNT_MACID_8197F (BIT_MASK_CNT_MACID_8197F << BIT_SHIFT_CNT_MACID_8197F) +#define BIT_CLEAR_CNT_MACID_8197F(x) ((x) & (~BITS_CNT_MACID_8197F)) +#define BIT_GET_CNT_MACID_8197F(x) (((x) >> BIT_SHIFT_CNT_MACID_8197F) & BIT_MASK_CNT_MACID_8197F) +#define BIT_SET_CNT_MACID_8197F(x, v) (BIT_CLEAR_CNT_MACID_8197F(x) | BIT_CNT_MACID_8197F(v)) + + +#define BIT_SHIFT_AGG_VALUE2_8197F 16 +#define BIT_MASK_AGG_VALUE2_8197F 0x7f +#define BIT_AGG_VALUE2_8197F(x) (((x) & BIT_MASK_AGG_VALUE2_8197F) << BIT_SHIFT_AGG_VALUE2_8197F) +#define BITS_AGG_VALUE2_8197F (BIT_MASK_AGG_VALUE2_8197F << BIT_SHIFT_AGG_VALUE2_8197F) +#define BIT_CLEAR_AGG_VALUE2_8197F(x) ((x) & (~BITS_AGG_VALUE2_8197F)) +#define BIT_GET_AGG_VALUE2_8197F(x) (((x) >> BIT_SHIFT_AGG_VALUE2_8197F) & BIT_MASK_AGG_VALUE2_8197F) +#define BIT_SET_AGG_VALUE2_8197F(x, v) (BIT_CLEAR_AGG_VALUE2_8197F(x) | BIT_AGG_VALUE2_8197F(v)) + + +#define BIT_SHIFT_AGG_VALUE1_8197F 8 +#define BIT_MASK_AGG_VALUE1_8197F 0x7f +#define BIT_AGG_VALUE1_8197F(x) (((x) & BIT_MASK_AGG_VALUE1_8197F) << BIT_SHIFT_AGG_VALUE1_8197F) +#define BITS_AGG_VALUE1_8197F (BIT_MASK_AGG_VALUE1_8197F << BIT_SHIFT_AGG_VALUE1_8197F) +#define BIT_CLEAR_AGG_VALUE1_8197F(x) ((x) & (~BITS_AGG_VALUE1_8197F)) +#define BIT_GET_AGG_VALUE1_8197F(x) (((x) >> BIT_SHIFT_AGG_VALUE1_8197F) & BIT_MASK_AGG_VALUE1_8197F) +#define BIT_SET_AGG_VALUE1_8197F(x, v) (BIT_CLEAR_AGG_VALUE1_8197F(x) | BIT_AGG_VALUE1_8197F(v)) + + +#define BIT_SHIFT_AGG_VALUE0_8197F 0 +#define BIT_MASK_AGG_VALUE0_8197F 0x7f +#define BIT_AGG_VALUE0_8197F(x) (((x) & BIT_MASK_AGG_VALUE0_8197F) << BIT_SHIFT_AGG_VALUE0_8197F) +#define BITS_AGG_VALUE0_8197F (BIT_MASK_AGG_VALUE0_8197F << BIT_SHIFT_AGG_VALUE0_8197F) +#define BIT_CLEAR_AGG_VALUE0_8197F(x) ((x) & (~BITS_AGG_VALUE0_8197F)) +#define BIT_GET_AGG_VALUE0_8197F(x) (((x) >> BIT_SHIFT_AGG_VALUE0_8197F) & BIT_MASK_AGG_VALUE0_8197F) +#define BIT_SET_AGG_VALUE0_8197F(x, v) (BIT_CLEAR_AGG_VALUE0_8197F(x) | BIT_AGG_VALUE0_8197F(v)) + + +/* 2 REG_COUNTER_SET_8197F */ +#define BIT_RTS_RST_8197F BIT(24) +#define BIT_PTCL_RST_8197F BIT(23) +#define BIT_SCH_RST_8197F BIT(22) +#define BIT_EDCA_RST_8197F BIT(21) +#define BIT_RQPN_RST_8197F BIT(20) +#define BIT_USB_RST_8197F BIT(19) +#define BIT_PCIE_RST_8197F BIT(18) +#define BIT_RXDMA_RST_8197F BIT(17) +#define BIT_TXDMA_RST_8197F BIT(16) +#define BIT_EN_RTS_START_8197F BIT(8) +#define BIT_EN_PTCL_START_8197F BIT(7) +#define BIT_EN_SCH_START_8197F BIT(6) +#define BIT_EN_EDCA_START_8197F BIT(5) +#define BIT_EN_RQPN_START_8197F BIT(4) +#define BIT_EN_USB_START_8197F BIT(3) +#define BIT_EN_PCIE_START_8197F BIT(2) +#define BIT_EN_RXDMA_START_8197F BIT(1) +#define BIT_EN_TXDMA_START_8197F BIT(0) + +/* 2 REG_COUNTER_OVERFLOW_8197F */ +#define BIT_RTS_OVF_8197F BIT(8) +#define BIT_PTCL_OVF_8197F BIT(7) +#define BIT_SCH_OVF_8197F BIT(6) +#define BIT_EDCA_OVF_8197F BIT(5) +#define BIT_RQPN_OVF_8197F BIT(4) +#define BIT_USB_OVF_8197F BIT(3) +#define BIT_PCIE_OVF_8197F BIT(2) +#define BIT_RXDMA_OVF_8197F BIT(1) +#define BIT_TXDMA_OVF_8197F BIT(0) + +/* 2 REG_TDE_LEN_TH_8197F */ + +#define BIT_SHIFT_TXDMA_LEN_TH0_8197F 16 +#define BIT_MASK_TXDMA_LEN_TH0_8197F 0xffff +#define BIT_TXDMA_LEN_TH0_8197F(x) (((x) & BIT_MASK_TXDMA_LEN_TH0_8197F) << BIT_SHIFT_TXDMA_LEN_TH0_8197F) +#define BITS_TXDMA_LEN_TH0_8197F (BIT_MASK_TXDMA_LEN_TH0_8197F << BIT_SHIFT_TXDMA_LEN_TH0_8197F) +#define BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) ((x) & (~BITS_TXDMA_LEN_TH0_8197F)) +#define BIT_GET_TXDMA_LEN_TH0_8197F(x) (((x) >> BIT_SHIFT_TXDMA_LEN_TH0_8197F) & BIT_MASK_TXDMA_LEN_TH0_8197F) +#define BIT_SET_TXDMA_LEN_TH0_8197F(x, v) (BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) | BIT_TXDMA_LEN_TH0_8197F(v)) + + +#define BIT_SHIFT_TXDMA_LEN_TH1_8197F 0 +#define BIT_MASK_TXDMA_LEN_TH1_8197F 0xffff +#define BIT_TXDMA_LEN_TH1_8197F(x) (((x) & BIT_MASK_TXDMA_LEN_TH1_8197F) << BIT_SHIFT_TXDMA_LEN_TH1_8197F) +#define BITS_TXDMA_LEN_TH1_8197F (BIT_MASK_TXDMA_LEN_TH1_8197F << BIT_SHIFT_TXDMA_LEN_TH1_8197F) +#define BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) ((x) & (~BITS_TXDMA_LEN_TH1_8197F)) +#define BIT_GET_TXDMA_LEN_TH1_8197F(x) (((x) >> BIT_SHIFT_TXDMA_LEN_TH1_8197F) & BIT_MASK_TXDMA_LEN_TH1_8197F) +#define BIT_SET_TXDMA_LEN_TH1_8197F(x, v) (BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) | BIT_TXDMA_LEN_TH1_8197F(v)) + + +/* 2 REG_RDE_LEN_TH_8197F */ + +#define BIT_SHIFT_RXDMA_LEN_TH0_8197F 16 +#define BIT_MASK_RXDMA_LEN_TH0_8197F 0xffff +#define BIT_RXDMA_LEN_TH0_8197F(x) (((x) & BIT_MASK_RXDMA_LEN_TH0_8197F) << BIT_SHIFT_RXDMA_LEN_TH0_8197F) +#define BITS_RXDMA_LEN_TH0_8197F (BIT_MASK_RXDMA_LEN_TH0_8197F << BIT_SHIFT_RXDMA_LEN_TH0_8197F) +#define BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) ((x) & (~BITS_RXDMA_LEN_TH0_8197F)) +#define BIT_GET_RXDMA_LEN_TH0_8197F(x) (((x) >> BIT_SHIFT_RXDMA_LEN_TH0_8197F) & BIT_MASK_RXDMA_LEN_TH0_8197F) +#define BIT_SET_RXDMA_LEN_TH0_8197F(x, v) (BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) | BIT_RXDMA_LEN_TH0_8197F(v)) + + +#define BIT_SHIFT_RXDMA_LEN_TH1_8197F 0 +#define BIT_MASK_RXDMA_LEN_TH1_8197F 0xffff +#define BIT_RXDMA_LEN_TH1_8197F(x) (((x) & BIT_MASK_RXDMA_LEN_TH1_8197F) << BIT_SHIFT_RXDMA_LEN_TH1_8197F) +#define BITS_RXDMA_LEN_TH1_8197F (BIT_MASK_RXDMA_LEN_TH1_8197F << BIT_SHIFT_RXDMA_LEN_TH1_8197F) +#define BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) ((x) & (~BITS_RXDMA_LEN_TH1_8197F)) +#define BIT_GET_RXDMA_LEN_TH1_8197F(x) (((x) >> BIT_SHIFT_RXDMA_LEN_TH1_8197F) & BIT_MASK_RXDMA_LEN_TH1_8197F) +#define BIT_SET_RXDMA_LEN_TH1_8197F(x, v) (BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) | BIT_RXDMA_LEN_TH1_8197F(v)) + + +/* 2 REG_PCIE_EXEC_TIME_8197F */ + +#define BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F 16 +#define BIT_MASK_COUNTER_INTERVAL_SEL_8197F 0x3 +#define BIT_COUNTER_INTERVAL_SEL_8197F(x) (((x) & BIT_MASK_COUNTER_INTERVAL_SEL_8197F) << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) +#define BITS_COUNTER_INTERVAL_SEL_8197F (BIT_MASK_COUNTER_INTERVAL_SEL_8197F << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) +#define BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) ((x) & (~BITS_COUNTER_INTERVAL_SEL_8197F)) +#define BIT_GET_COUNTER_INTERVAL_SEL_8197F(x) (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) & BIT_MASK_COUNTER_INTERVAL_SEL_8197F) +#define BIT_SET_COUNTER_INTERVAL_SEL_8197F(x, v) (BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) | BIT_COUNTER_INTERVAL_SEL_8197F(v)) + + +#define BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F 0 +#define BIT_MASK_PCIE_TRANS_DATA_TH1_8197F 0xffff +#define BIT_PCIE_TRANS_DATA_TH1_8197F(x) (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1_8197F) << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) +#define BITS_PCIE_TRANS_DATA_TH1_8197F (BIT_MASK_PCIE_TRANS_DATA_TH1_8197F << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) +#define BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) ((x) & (~BITS_PCIE_TRANS_DATA_TH1_8197F)) +#define BIT_GET_PCIE_TRANS_DATA_TH1_8197F(x) (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) & BIT_MASK_PCIE_TRANS_DATA_TH1_8197F) +#define BIT_SET_PCIE_TRANS_DATA_TH1_8197F(x, v) (BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) | BIT_PCIE_TRANS_DATA_TH1_8197F(v)) + + +/* 2 REG_FT2IMR_8197F */ +#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(31) +#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(30) +#define BIT_PORT4_TRIPKT_OK_INT_EN_8197F BIT(29) +#define BIT_PORT4_RX_EOSP_OK_INT_EN_8197F BIT(28) +#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(27) +#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(26) +#define BIT_PORT3_TRIPKT_OK_INT_EN_8197F BIT(25) +#define BIT_PORT3_RX_EOSP_OK_INT_EN_8197F BIT(24) +#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(23) +#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(22) +#define BIT_PORT2_TRIPKT_OK_INT_EN_8197F BIT(21) +#define BIT_PORT2_RX_EOSP_OK_INT_EN_8197F BIT(20) +#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(19) +#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(18) +#define BIT_PORT1_TRIPKT_OK_INT_EN_8197F BIT(17) +#define BIT_PORT1_RX_EOSP_OK_INT_EN_8197F BIT(16) +#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN_8197F BIT(9) +#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN_8197F BIT(8) +#define BIT_PORT4_TX_NULL1_DONE_INT_EN_8197F BIT(7) +#define BIT_PORT4_TX_NULL0_DONE_INT_EN_8197F BIT(6) +#define BIT_PORT3_TX_NULL1_DONE_INT_EN_8197F BIT(5) +#define BIT_PORT3_TX_NULL0_DONE_INT_EN_8197F BIT(4) +#define BIT_PORT2_TX_NULL1_DONE_INT_EN_8197F BIT(3) +#define BIT_PORT2_TX_NULL0_DONE_INT_EN_8197F BIT(2) +#define BIT_PORT1_TX_NULL1_DONE_INT_EN_8197F BIT(1) +#define BIT_PORT1_TX_NULL0_DONE_INT_EN_8197F BIT(0) + +/* 2 REG_FT2ISR_8197F */ +#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(31) +#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(30) +#define BIT_PORT4_TRIPKT_OK_INT_8197F BIT(29) +#define BIT_PORT4_RX_EOSP_OK_INT_8197F BIT(28) +#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(27) +#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(26) +#define BIT_PORT3_TRIPKT_OK_INT_8197F BIT(25) +#define BIT_PORT3_RX_EOSP_OK_INT_8197F BIT(24) +#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(23) +#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(22) +#define BIT_PORT2_TRIPKT_OK_INT_8197F BIT(21) +#define BIT_PORT2_RX_EOSP_OK_INT_8197F BIT(20) +#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(19) +#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(18) +#define BIT_PORT1_TRIPKT_OK_INT_8197F BIT(17) +#define BIT_PORT1_RX_EOSP_OK_INT_8197F BIT(16) +#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_8197F BIT(9) +#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_8197F BIT(8) +#define BIT_PORT4_TX_NULL1_DONE_INT_8197F BIT(7) +#define BIT_PORT4_TX_NULL0_DONE_INT_8197F BIT(6) +#define BIT_PORT3_TX_NULL1_DONE_INT_8197F BIT(5) +#define BIT_PORT3_TX_NULL0_DONE_INT_8197F BIT(4) +#define BIT_PORT2_TX_NULL1_DONE_INT_8197F BIT(3) +#define BIT_PORT2_TX_NULL0_DONE_INT_8197F BIT(2) +#define BIT_PORT1_TX_NULL1_DONE_INT_8197F BIT(1) +#define BIT_PORT1_TX_NULL0_DONE_INT_8197F BIT(0) + +/* 2 REG_MSG2_8197F */ + +#define BIT_SHIFT_FW_MSG2_8197F 0 +#define BIT_MASK_FW_MSG2_8197F 0xffffffffL +#define BIT_FW_MSG2_8197F(x) (((x) & BIT_MASK_FW_MSG2_8197F) << BIT_SHIFT_FW_MSG2_8197F) +#define BITS_FW_MSG2_8197F (BIT_MASK_FW_MSG2_8197F << BIT_SHIFT_FW_MSG2_8197F) +#define BIT_CLEAR_FW_MSG2_8197F(x) ((x) & (~BITS_FW_MSG2_8197F)) +#define BIT_GET_FW_MSG2_8197F(x) (((x) >> BIT_SHIFT_FW_MSG2_8197F) & BIT_MASK_FW_MSG2_8197F) +#define BIT_SET_FW_MSG2_8197F(x, v) (BIT_CLEAR_FW_MSG2_8197F(x) | BIT_FW_MSG2_8197F(v)) + + +/* 2 REG_MSG3_8197F */ + +#define BIT_SHIFT_FW_MSG3_8197F 0 +#define BIT_MASK_FW_MSG3_8197F 0xffffffffL +#define BIT_FW_MSG3_8197F(x) (((x) & BIT_MASK_FW_MSG3_8197F) << BIT_SHIFT_FW_MSG3_8197F) +#define BITS_FW_MSG3_8197F (BIT_MASK_FW_MSG3_8197F << BIT_SHIFT_FW_MSG3_8197F) +#define BIT_CLEAR_FW_MSG3_8197F(x) ((x) & (~BITS_FW_MSG3_8197F)) +#define BIT_GET_FW_MSG3_8197F(x) (((x) >> BIT_SHIFT_FW_MSG3_8197F) & BIT_MASK_FW_MSG3_8197F) +#define BIT_SET_FW_MSG3_8197F(x, v) (BIT_CLEAR_FW_MSG3_8197F(x) | BIT_FW_MSG3_8197F(v)) + + +/* 2 REG_MSG4_8197F */ + +#define BIT_SHIFT_FW_MSG4_8197F 0 +#define BIT_MASK_FW_MSG4_8197F 0xffffffffL +#define BIT_FW_MSG4_8197F(x) (((x) & BIT_MASK_FW_MSG4_8197F) << BIT_SHIFT_FW_MSG4_8197F) +#define BITS_FW_MSG4_8197F (BIT_MASK_FW_MSG4_8197F << BIT_SHIFT_FW_MSG4_8197F) +#define BIT_CLEAR_FW_MSG4_8197F(x) ((x) & (~BITS_FW_MSG4_8197F)) +#define BIT_GET_FW_MSG4_8197F(x) (((x) >> BIT_SHIFT_FW_MSG4_8197F) & BIT_MASK_FW_MSG4_8197F) +#define BIT_SET_FW_MSG4_8197F(x, v) (BIT_CLEAR_FW_MSG4_8197F(x) | BIT_FW_MSG4_8197F(v)) + + +/* 2 REG_MSG5_8197F */ + +#define BIT_SHIFT_FW_MSG5_8197F 0 +#define BIT_MASK_FW_MSG5_8197F 0xffffffffL +#define BIT_FW_MSG5_8197F(x) (((x) & BIT_MASK_FW_MSG5_8197F) << BIT_SHIFT_FW_MSG5_8197F) +#define BITS_FW_MSG5_8197F (BIT_MASK_FW_MSG5_8197F << BIT_SHIFT_FW_MSG5_8197F) +#define BIT_CLEAR_FW_MSG5_8197F(x) ((x) & (~BITS_FW_MSG5_8197F)) +#define BIT_GET_FW_MSG5_8197F(x) (((x) >> BIT_SHIFT_FW_MSG5_8197F) & BIT_MASK_FW_MSG5_8197F) +#define BIT_SET_FW_MSG5_8197F(x, v) (BIT_CLEAR_FW_MSG5_8197F(x) | BIT_FW_MSG5_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_FIFOPAGE_CTRL_1_8197F */ + +#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F 16 +#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F 0xff +#define BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) +#define BITS_TX_OQT_HE_FREE_SPACE_V1_8197F (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8197F)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8197F(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F) +#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8197F(x, v) (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) | BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(v)) + + +#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F 0 +#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F 0xff +#define BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) +#define BITS_TX_OQT_NL_FREE_SPACE_V1_8197F (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8197F)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8197F(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F) +#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8197F(x, v) (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) | BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(v)) + + +/* 2 REG_FIFOPAGE_CTRL_2_8197F */ +#define BIT_BCN_VALID_1_V1_8197F BIT(31) + +#define BIT_SHIFT_BCN_HEAD_1_V1_8197F 16 +#define BIT_MASK_BCN_HEAD_1_V1_8197F 0xfff +#define BIT_BCN_HEAD_1_V1_8197F(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8197F) << BIT_SHIFT_BCN_HEAD_1_V1_8197F) +#define BITS_BCN_HEAD_1_V1_8197F (BIT_MASK_BCN_HEAD_1_V1_8197F << BIT_SHIFT_BCN_HEAD_1_V1_8197F) +#define BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) ((x) & (~BITS_BCN_HEAD_1_V1_8197F)) +#define BIT_GET_BCN_HEAD_1_V1_8197F(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8197F) & BIT_MASK_BCN_HEAD_1_V1_8197F) +#define BIT_SET_BCN_HEAD_1_V1_8197F(x, v) (BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) | BIT_BCN_HEAD_1_V1_8197F(v)) + +#define BIT_BCN_VALID_V1_8197F BIT(15) + +#define BIT_SHIFT_BCN_HEAD_V1_8197F 0 +#define BIT_MASK_BCN_HEAD_V1_8197F 0xfff +#define BIT_BCN_HEAD_V1_8197F(x) (((x) & BIT_MASK_BCN_HEAD_V1_8197F) << BIT_SHIFT_BCN_HEAD_V1_8197F) +#define BITS_BCN_HEAD_V1_8197F (BIT_MASK_BCN_HEAD_V1_8197F << BIT_SHIFT_BCN_HEAD_V1_8197F) +#define BIT_CLEAR_BCN_HEAD_V1_8197F(x) ((x) & (~BITS_BCN_HEAD_V1_8197F)) +#define BIT_GET_BCN_HEAD_V1_8197F(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8197F) & BIT_MASK_BCN_HEAD_V1_8197F) +#define BIT_SET_BCN_HEAD_V1_8197F(x, v) (BIT_CLEAR_BCN_HEAD_V1_8197F(x) | BIT_BCN_HEAD_V1_8197F(v)) + + +/* 2 REG_AUTO_LLT_V1_8197F */ + +#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F 24 +#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F 0xff +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) +#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) +#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) +#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x, v) (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) | BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(v)) + + +#define BIT_SHIFT_LLT_FREE_PAGE_V1_8197F 8 +#define BIT_MASK_LLT_FREE_PAGE_V1_8197F 0xffff +#define BIT_LLT_FREE_PAGE_V1_8197F(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8197F) << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) +#define BITS_LLT_FREE_PAGE_V1_8197F (BIT_MASK_LLT_FREE_PAGE_V1_8197F << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) +#define BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) ((x) & (~BITS_LLT_FREE_PAGE_V1_8197F)) +#define BIT_GET_LLT_FREE_PAGE_V1_8197F(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) & BIT_MASK_LLT_FREE_PAGE_V1_8197F) +#define BIT_SET_LLT_FREE_PAGE_V1_8197F(x, v) (BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) | BIT_LLT_FREE_PAGE_V1_8197F(v)) + + +#define BIT_SHIFT_BLK_DESC_NUM_8197F 4 +#define BIT_MASK_BLK_DESC_NUM_8197F 0xf +#define BIT_BLK_DESC_NUM_8197F(x) (((x) & BIT_MASK_BLK_DESC_NUM_8197F) << BIT_SHIFT_BLK_DESC_NUM_8197F) +#define BITS_BLK_DESC_NUM_8197F (BIT_MASK_BLK_DESC_NUM_8197F << BIT_SHIFT_BLK_DESC_NUM_8197F) +#define BIT_CLEAR_BLK_DESC_NUM_8197F(x) ((x) & (~BITS_BLK_DESC_NUM_8197F)) +#define BIT_GET_BLK_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8197F) & BIT_MASK_BLK_DESC_NUM_8197F) +#define BIT_SET_BLK_DESC_NUM_8197F(x, v) (BIT_CLEAR_BLK_DESC_NUM_8197F(x) | BIT_BLK_DESC_NUM_8197F(v)) + +#define BIT_R_BCN_HEAD_SEL_8197F BIT(3) +#define BIT_R_EN_BCN_SW_HEAD_SEL_8197F BIT(2) +#define BIT_LLT_DBG_SEL_8197F BIT(1) +#define BIT_AUTO_INIT_LLT_V1_8197F BIT(0) + +/* 2 REG_TXDMA_OFFSET_CHK_8197F */ +#define BIT_EM_CHKSUM_FIN_8197F BIT(31) +#define BIT_EMN_PCIE_DMA_MOD_8197F BIT(30) +#define BIT_EN_TXQUE_CLR_8197F BIT(29) +#define BIT_EN_PCIE_FIFO_MODE_8197F BIT(28) + +#define BIT_SHIFT_PG_UNDER_TH_V1_8197F 16 +#define BIT_MASK_PG_UNDER_TH_V1_8197F 0xfff +#define BIT_PG_UNDER_TH_V1_8197F(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8197F) << BIT_SHIFT_PG_UNDER_TH_V1_8197F) +#define BITS_PG_UNDER_TH_V1_8197F (BIT_MASK_PG_UNDER_TH_V1_8197F << BIT_SHIFT_PG_UNDER_TH_V1_8197F) +#define BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) ((x) & (~BITS_PG_UNDER_TH_V1_8197F)) +#define BIT_GET_PG_UNDER_TH_V1_8197F(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8197F) & BIT_MASK_PG_UNDER_TH_V1_8197F) +#define BIT_SET_PG_UNDER_TH_V1_8197F(x, v) (BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) | BIT_PG_UNDER_TH_V1_8197F(v)) + +#define BIT_EN_RESET_RESTORE_H2C_8197F BIT(15) +#define BIT_SDIO_TDE_FINISH_8197F BIT(14) +#define BIT_SDIO_TXDESC_CHKSUM_EN_8197F BIT(13) +#define BIT_RST_RDPTR_8197F BIT(12) +#define BIT_RST_WRPTR_8197F BIT(11) +#define BIT_CHK_PG_TH_EN_8197F BIT(10) +#define BIT_DROP_DATA_EN_8197F BIT(9) +#define BIT_CHECK_OFFSET_EN_8197F BIT(8) + +#define BIT_SHIFT_CHECK_OFFSET_8197F 0 +#define BIT_MASK_CHECK_OFFSET_8197F 0xff +#define BIT_CHECK_OFFSET_8197F(x) (((x) & BIT_MASK_CHECK_OFFSET_8197F) << BIT_SHIFT_CHECK_OFFSET_8197F) +#define BITS_CHECK_OFFSET_8197F (BIT_MASK_CHECK_OFFSET_8197F << BIT_SHIFT_CHECK_OFFSET_8197F) +#define BIT_CLEAR_CHECK_OFFSET_8197F(x) ((x) & (~BITS_CHECK_OFFSET_8197F)) +#define BIT_GET_CHECK_OFFSET_8197F(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8197F) & BIT_MASK_CHECK_OFFSET_8197F) +#define BIT_SET_CHECK_OFFSET_8197F(x, v) (BIT_CLEAR_CHECK_OFFSET_8197F(x) | BIT_CHECK_OFFSET_8197F(v)) + + +/* 2 REG_TXDMA_STATUS_8197F */ +#define BIT_HI_OQT_UDN_8197F BIT(17) +#define BIT_HI_OQT_OVF_8197F BIT(16) +#define BIT_PAYLOAD_CHKSUM_ERR_8197F BIT(15) +#define BIT_PAYLOAD_UDN_8197F BIT(14) +#define BIT_PAYLOAD_OVF_8197F BIT(13) +#define BIT_DSC_CHKSUM_FAIL_8197F BIT(12) +#define BIT_UNKNOWN_QSEL_8197F BIT(11) +#define BIT_EP_QSEL_DIFF_8197F BIT(10) +#define BIT_TX_OFFS_UNMATCH_8197F BIT(9) +#define BIT_TXOQT_UDN_8197F BIT(8) +#define BIT_TXOQT_OVF_8197F BIT(7) +#define BIT_TXDMA_SFF_UDN_8197F BIT(6) +#define BIT_TXDMA_SFF_OVF_8197F BIT(5) +#define BIT_LLT_NULL_PG_8197F BIT(4) +#define BIT_PAGE_UDN_8197F BIT(3) +#define BIT_PAGE_OVF_8197F BIT(2) +#define BIT_TXFF_PG_UDN_8197F BIT(1) +#define BIT_TXFF_PG_OVF_8197F BIT(0) + +/* 2 REG_TX_DMA_DBG_8197F */ + +/* 2 REG_TQPNT1_8197F */ + +#define BIT_SHIFT_HPQ_HIGH_TH_V1_8197F 16 +#define BIT_MASK_HPQ_HIGH_TH_V1_8197F 0xfff +#define BIT_HPQ_HIGH_TH_V1_8197F(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8197F) << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) +#define BITS_HPQ_HIGH_TH_V1_8197F (BIT_MASK_HPQ_HIGH_TH_V1_8197F << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) +#define BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8197F)) +#define BIT_GET_HPQ_HIGH_TH_V1_8197F(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) & BIT_MASK_HPQ_HIGH_TH_V1_8197F) +#define BIT_SET_HPQ_HIGH_TH_V1_8197F(x, v) (BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) | BIT_HPQ_HIGH_TH_V1_8197F(v)) + + +#define BIT_SHIFT_HPQ_LOW_TH_V1_8197F 0 +#define BIT_MASK_HPQ_LOW_TH_V1_8197F 0xfff +#define BIT_HPQ_LOW_TH_V1_8197F(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8197F) << BIT_SHIFT_HPQ_LOW_TH_V1_8197F) +#define BITS_HPQ_LOW_TH_V1_8197F (BIT_MASK_HPQ_LOW_TH_V1_8197F << BIT_SHIFT_HPQ_LOW_TH_V1_8197F) +#define BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8197F)) +#define BIT_GET_HPQ_LOW_TH_V1_8197F(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8197F) & BIT_MASK_HPQ_LOW_TH_V1_8197F) +#define BIT_SET_HPQ_LOW_TH_V1_8197F(x, v) (BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) | BIT_HPQ_LOW_TH_V1_8197F(v)) + + +/* 2 REG_TQPNT2_8197F */ + +#define BIT_SHIFT_NPQ_HIGH_TH_V1_8197F 16 +#define BIT_MASK_NPQ_HIGH_TH_V1_8197F 0xfff +#define BIT_NPQ_HIGH_TH_V1_8197F(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8197F) << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) +#define BITS_NPQ_HIGH_TH_V1_8197F (BIT_MASK_NPQ_HIGH_TH_V1_8197F << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) +#define BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8197F)) +#define BIT_GET_NPQ_HIGH_TH_V1_8197F(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) & BIT_MASK_NPQ_HIGH_TH_V1_8197F) +#define BIT_SET_NPQ_HIGH_TH_V1_8197F(x, v) (BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) | BIT_NPQ_HIGH_TH_V1_8197F(v)) + + +#define BIT_SHIFT_NPQ_LOW_TH_V1_8197F 0 +#define BIT_MASK_NPQ_LOW_TH_V1_8197F 0xfff +#define BIT_NPQ_LOW_TH_V1_8197F(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8197F) << BIT_SHIFT_NPQ_LOW_TH_V1_8197F) +#define BITS_NPQ_LOW_TH_V1_8197F (BIT_MASK_NPQ_LOW_TH_V1_8197F << BIT_SHIFT_NPQ_LOW_TH_V1_8197F) +#define BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8197F)) +#define BIT_GET_NPQ_LOW_TH_V1_8197F(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8197F) & BIT_MASK_NPQ_LOW_TH_V1_8197F) +#define BIT_SET_NPQ_LOW_TH_V1_8197F(x, v) (BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) | BIT_NPQ_LOW_TH_V1_8197F(v)) + + +/* 2 REG_TQPNT3_8197F */ + +#define BIT_SHIFT_LPQ_HIGH_TH_V1_8197F 16 +#define BIT_MASK_LPQ_HIGH_TH_V1_8197F 0xfff +#define BIT_LPQ_HIGH_TH_V1_8197F(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8197F) << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) +#define BITS_LPQ_HIGH_TH_V1_8197F (BIT_MASK_LPQ_HIGH_TH_V1_8197F << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) +#define BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8197F)) +#define BIT_GET_LPQ_HIGH_TH_V1_8197F(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) & BIT_MASK_LPQ_HIGH_TH_V1_8197F) +#define BIT_SET_LPQ_HIGH_TH_V1_8197F(x, v) (BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) | BIT_LPQ_HIGH_TH_V1_8197F(v)) + + +#define BIT_SHIFT_LPQ_LOW_TH_V1_8197F 0 +#define BIT_MASK_LPQ_LOW_TH_V1_8197F 0xfff +#define BIT_LPQ_LOW_TH_V1_8197F(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8197F) << BIT_SHIFT_LPQ_LOW_TH_V1_8197F) +#define BITS_LPQ_LOW_TH_V1_8197F (BIT_MASK_LPQ_LOW_TH_V1_8197F << BIT_SHIFT_LPQ_LOW_TH_V1_8197F) +#define BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8197F)) +#define BIT_GET_LPQ_LOW_TH_V1_8197F(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8197F) & BIT_MASK_LPQ_LOW_TH_V1_8197F) +#define BIT_SET_LPQ_LOW_TH_V1_8197F(x, v) (BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) | BIT_LPQ_LOW_TH_V1_8197F(v)) + + +/* 2 REG_TQPNT4_8197F */ + +#define BIT_SHIFT_EXQ_HIGH_TH_V1_8197F 16 +#define BIT_MASK_EXQ_HIGH_TH_V1_8197F 0xfff +#define BIT_EXQ_HIGH_TH_V1_8197F(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8197F) << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) +#define BITS_EXQ_HIGH_TH_V1_8197F (BIT_MASK_EXQ_HIGH_TH_V1_8197F << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) +#define BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8197F)) +#define BIT_GET_EXQ_HIGH_TH_V1_8197F(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) & BIT_MASK_EXQ_HIGH_TH_V1_8197F) +#define BIT_SET_EXQ_HIGH_TH_V1_8197F(x, v) (BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) | BIT_EXQ_HIGH_TH_V1_8197F(v)) + + +#define BIT_SHIFT_EXQ_LOW_TH_V1_8197F 0 +#define BIT_MASK_EXQ_LOW_TH_V1_8197F 0xfff +#define BIT_EXQ_LOW_TH_V1_8197F(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8197F) << BIT_SHIFT_EXQ_LOW_TH_V1_8197F) +#define BITS_EXQ_LOW_TH_V1_8197F (BIT_MASK_EXQ_LOW_TH_V1_8197F << BIT_SHIFT_EXQ_LOW_TH_V1_8197F) +#define BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8197F)) +#define BIT_GET_EXQ_LOW_TH_V1_8197F(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8197F) & BIT_MASK_EXQ_LOW_TH_V1_8197F) +#define BIT_SET_EXQ_LOW_TH_V1_8197F(x, v) (BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) | BIT_EXQ_LOW_TH_V1_8197F(v)) + + +/* 2 REG_RQPN_CTRL_1_8197F */ + +#define BIT_SHIFT_TXPKTNUM_H_8197F 16 +#define BIT_MASK_TXPKTNUM_H_8197F 0xffff +#define BIT_TXPKTNUM_H_8197F(x) (((x) & BIT_MASK_TXPKTNUM_H_8197F) << BIT_SHIFT_TXPKTNUM_H_8197F) +#define BITS_TXPKTNUM_H_8197F (BIT_MASK_TXPKTNUM_H_8197F << BIT_SHIFT_TXPKTNUM_H_8197F) +#define BIT_CLEAR_TXPKTNUM_H_8197F(x) ((x) & (~BITS_TXPKTNUM_H_8197F)) +#define BIT_GET_TXPKTNUM_H_8197F(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8197F) & BIT_MASK_TXPKTNUM_H_8197F) +#define BIT_SET_TXPKTNUM_H_8197F(x, v) (BIT_CLEAR_TXPKTNUM_H_8197F(x) | BIT_TXPKTNUM_H_8197F(v)) + + +#define BIT_SHIFT_TXPKTNUM_H_V1_8197F 0 +#define BIT_MASK_TXPKTNUM_H_V1_8197F 0xffff +#define BIT_TXPKTNUM_H_V1_8197F(x) (((x) & BIT_MASK_TXPKTNUM_H_V1_8197F) << BIT_SHIFT_TXPKTNUM_H_V1_8197F) +#define BITS_TXPKTNUM_H_V1_8197F (BIT_MASK_TXPKTNUM_H_V1_8197F << BIT_SHIFT_TXPKTNUM_H_V1_8197F) +#define BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) ((x) & (~BITS_TXPKTNUM_H_V1_8197F)) +#define BIT_GET_TXPKTNUM_H_V1_8197F(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_V1_8197F) & BIT_MASK_TXPKTNUM_H_V1_8197F) +#define BIT_SET_TXPKTNUM_H_V1_8197F(x, v) (BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) | BIT_TXPKTNUM_H_V1_8197F(v)) + + +/* 2 REG_RQPN_CTRL_2_8197F */ +#define BIT_LD_RQPN_8197F BIT(31) +#define BIT_EXQ_PUBLIC_DIS_V1_8197F BIT(19) +#define BIT_NPQ_PUBLIC_DIS_V1_8197F BIT(18) +#define BIT_LPQ_PUBLIC_DIS_V1_8197F BIT(17) +#define BIT_HPQ_PUBLIC_DIS_V1_8197F BIT(16) + +/* 2 REG_FIFOPAGE_INFO_1_8197F */ + +#define BIT_SHIFT_HPQ_AVAL_PG_V1_8197F 16 +#define BIT_MASK_HPQ_AVAL_PG_V1_8197F 0xfff +#define BIT_HPQ_AVAL_PG_V1_8197F(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8197F) << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) +#define BITS_HPQ_AVAL_PG_V1_8197F (BIT_MASK_HPQ_AVAL_PG_V1_8197F << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) +#define BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8197F)) +#define BIT_GET_HPQ_AVAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) & BIT_MASK_HPQ_AVAL_PG_V1_8197F) +#define BIT_SET_HPQ_AVAL_PG_V1_8197F(x, v) (BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) | BIT_HPQ_AVAL_PG_V1_8197F(v)) + + +#define BIT_SHIFT_HPQ_V1_8197F 0 +#define BIT_MASK_HPQ_V1_8197F 0xfff +#define BIT_HPQ_V1_8197F(x) (((x) & BIT_MASK_HPQ_V1_8197F) << BIT_SHIFT_HPQ_V1_8197F) +#define BITS_HPQ_V1_8197F (BIT_MASK_HPQ_V1_8197F << BIT_SHIFT_HPQ_V1_8197F) +#define BIT_CLEAR_HPQ_V1_8197F(x) ((x) & (~BITS_HPQ_V1_8197F)) +#define BIT_GET_HPQ_V1_8197F(x) (((x) >> BIT_SHIFT_HPQ_V1_8197F) & BIT_MASK_HPQ_V1_8197F) +#define BIT_SET_HPQ_V1_8197F(x, v) (BIT_CLEAR_HPQ_V1_8197F(x) | BIT_HPQ_V1_8197F(v)) + + +/* 2 REG_FIFOPAGE_INFO_2_8197F */ + +#define BIT_SHIFT_LPQ_AVAL_PG_V1_8197F 16 +#define BIT_MASK_LPQ_AVAL_PG_V1_8197F 0xfff +#define BIT_LPQ_AVAL_PG_V1_8197F(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8197F) << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) +#define BITS_LPQ_AVAL_PG_V1_8197F (BIT_MASK_LPQ_AVAL_PG_V1_8197F << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) +#define BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8197F)) +#define BIT_GET_LPQ_AVAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) & BIT_MASK_LPQ_AVAL_PG_V1_8197F) +#define BIT_SET_LPQ_AVAL_PG_V1_8197F(x, v) (BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) | BIT_LPQ_AVAL_PG_V1_8197F(v)) + + +#define BIT_SHIFT_LPQ_V1_8197F 0 +#define BIT_MASK_LPQ_V1_8197F 0xfff +#define BIT_LPQ_V1_8197F(x) (((x) & BIT_MASK_LPQ_V1_8197F) << BIT_SHIFT_LPQ_V1_8197F) +#define BITS_LPQ_V1_8197F (BIT_MASK_LPQ_V1_8197F << BIT_SHIFT_LPQ_V1_8197F) +#define BIT_CLEAR_LPQ_V1_8197F(x) ((x) & (~BITS_LPQ_V1_8197F)) +#define BIT_GET_LPQ_V1_8197F(x) (((x) >> BIT_SHIFT_LPQ_V1_8197F) & BIT_MASK_LPQ_V1_8197F) +#define BIT_SET_LPQ_V1_8197F(x, v) (BIT_CLEAR_LPQ_V1_8197F(x) | BIT_LPQ_V1_8197F(v)) + + +/* 2 REG_FIFOPAGE_INFO_3_8197F */ + +#define BIT_SHIFT_NPQ_AVAL_PG_8197F 8 +#define BIT_MASK_NPQ_AVAL_PG_8197F 0xff +#define BIT_NPQ_AVAL_PG_8197F(x) (((x) & BIT_MASK_NPQ_AVAL_PG_8197F) << BIT_SHIFT_NPQ_AVAL_PG_8197F) +#define BITS_NPQ_AVAL_PG_8197F (BIT_MASK_NPQ_AVAL_PG_8197F << BIT_SHIFT_NPQ_AVAL_PG_8197F) +#define BIT_CLEAR_NPQ_AVAL_PG_8197F(x) ((x) & (~BITS_NPQ_AVAL_PG_8197F)) +#define BIT_GET_NPQ_AVAL_PG_8197F(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_8197F) & BIT_MASK_NPQ_AVAL_PG_8197F) +#define BIT_SET_NPQ_AVAL_PG_8197F(x, v) (BIT_CLEAR_NPQ_AVAL_PG_8197F(x) | BIT_NPQ_AVAL_PG_8197F(v)) + + +#define BIT_SHIFT_NPQ_V1_8197F 0 +#define BIT_MASK_NPQ_V1_8197F 0xfff +#define BIT_NPQ_V1_8197F(x) (((x) & BIT_MASK_NPQ_V1_8197F) << BIT_SHIFT_NPQ_V1_8197F) +#define BITS_NPQ_V1_8197F (BIT_MASK_NPQ_V1_8197F << BIT_SHIFT_NPQ_V1_8197F) +#define BIT_CLEAR_NPQ_V1_8197F(x) ((x) & (~BITS_NPQ_V1_8197F)) +#define BIT_GET_NPQ_V1_8197F(x) (((x) >> BIT_SHIFT_NPQ_V1_8197F) & BIT_MASK_NPQ_V1_8197F) +#define BIT_SET_NPQ_V1_8197F(x, v) (BIT_CLEAR_NPQ_V1_8197F(x) | BIT_NPQ_V1_8197F(v)) + + +/* 2 REG_FIFOPAGE_INFO_4_8197F */ + +#define BIT_SHIFT_EXQ_AVAL_PG_V1_8197F 16 +#define BIT_MASK_EXQ_AVAL_PG_V1_8197F 0xfff +#define BIT_EXQ_AVAL_PG_V1_8197F(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8197F) << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) +#define BITS_EXQ_AVAL_PG_V1_8197F (BIT_MASK_EXQ_AVAL_PG_V1_8197F << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) +#define BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8197F)) +#define BIT_GET_EXQ_AVAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) & BIT_MASK_EXQ_AVAL_PG_V1_8197F) +#define BIT_SET_EXQ_AVAL_PG_V1_8197F(x, v) (BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) | BIT_EXQ_AVAL_PG_V1_8197F(v)) + + +#define BIT_SHIFT_EXQ_V1_8197F 0 +#define BIT_MASK_EXQ_V1_8197F 0xfff +#define BIT_EXQ_V1_8197F(x) (((x) & BIT_MASK_EXQ_V1_8197F) << BIT_SHIFT_EXQ_V1_8197F) +#define BITS_EXQ_V1_8197F (BIT_MASK_EXQ_V1_8197F << BIT_SHIFT_EXQ_V1_8197F) +#define BIT_CLEAR_EXQ_V1_8197F(x) ((x) & (~BITS_EXQ_V1_8197F)) +#define BIT_GET_EXQ_V1_8197F(x) (((x) >> BIT_SHIFT_EXQ_V1_8197F) & BIT_MASK_EXQ_V1_8197F) +#define BIT_SET_EXQ_V1_8197F(x, v) (BIT_CLEAR_EXQ_V1_8197F(x) | BIT_EXQ_V1_8197F(v)) + + +/* 2 REG_FIFOPAGE_INFO_5_8197F */ + +#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F 16 +#define BIT_MASK_PUBQ_AVAL_PG_V1_8197F 0xfff +#define BIT_PUBQ_AVAL_PG_V1_8197F(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8197F) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) +#define BITS_PUBQ_AVAL_PG_V1_8197F (BIT_MASK_PUBQ_AVAL_PG_V1_8197F << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) +#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8197F)) +#define BIT_GET_PUBQ_AVAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) & BIT_MASK_PUBQ_AVAL_PG_V1_8197F) +#define BIT_SET_PUBQ_AVAL_PG_V1_8197F(x, v) (BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) | BIT_PUBQ_AVAL_PG_V1_8197F(v)) + + +#define BIT_SHIFT_PUBQ_V1_8197F 0 +#define BIT_MASK_PUBQ_V1_8197F 0xfff +#define BIT_PUBQ_V1_8197F(x) (((x) & BIT_MASK_PUBQ_V1_8197F) << BIT_SHIFT_PUBQ_V1_8197F) +#define BITS_PUBQ_V1_8197F (BIT_MASK_PUBQ_V1_8197F << BIT_SHIFT_PUBQ_V1_8197F) +#define BIT_CLEAR_PUBQ_V1_8197F(x) ((x) & (~BITS_PUBQ_V1_8197F)) +#define BIT_GET_PUBQ_V1_8197F(x) (((x) >> BIT_SHIFT_PUBQ_V1_8197F) & BIT_MASK_PUBQ_V1_8197F) +#define BIT_SET_PUBQ_V1_8197F(x, v) (BIT_CLEAR_PUBQ_V1_8197F(x) | BIT_PUBQ_V1_8197F(v)) + + +/* 2 REG_H2C_HEAD_8197F */ + +#define BIT_SHIFT_H2C_HEAD_8197F 0 +#define BIT_MASK_H2C_HEAD_8197F 0x3ffff +#define BIT_H2C_HEAD_8197F(x) (((x) & BIT_MASK_H2C_HEAD_8197F) << BIT_SHIFT_H2C_HEAD_8197F) +#define BITS_H2C_HEAD_8197F (BIT_MASK_H2C_HEAD_8197F << BIT_SHIFT_H2C_HEAD_8197F) +#define BIT_CLEAR_H2C_HEAD_8197F(x) ((x) & (~BITS_H2C_HEAD_8197F)) +#define BIT_GET_H2C_HEAD_8197F(x) (((x) >> BIT_SHIFT_H2C_HEAD_8197F) & BIT_MASK_H2C_HEAD_8197F) +#define BIT_SET_H2C_HEAD_8197F(x, v) (BIT_CLEAR_H2C_HEAD_8197F(x) | BIT_H2C_HEAD_8197F(v)) + + +/* 2 REG_H2C_TAIL_8197F */ + +#define BIT_SHIFT_H2C_TAIL_8197F 0 +#define BIT_MASK_H2C_TAIL_8197F 0x3ffff +#define BIT_H2C_TAIL_8197F(x) (((x) & BIT_MASK_H2C_TAIL_8197F) << BIT_SHIFT_H2C_TAIL_8197F) +#define BITS_H2C_TAIL_8197F (BIT_MASK_H2C_TAIL_8197F << BIT_SHIFT_H2C_TAIL_8197F) +#define BIT_CLEAR_H2C_TAIL_8197F(x) ((x) & (~BITS_H2C_TAIL_8197F)) +#define BIT_GET_H2C_TAIL_8197F(x) (((x) >> BIT_SHIFT_H2C_TAIL_8197F) & BIT_MASK_H2C_TAIL_8197F) +#define BIT_SET_H2C_TAIL_8197F(x, v) (BIT_CLEAR_H2C_TAIL_8197F(x) | BIT_H2C_TAIL_8197F(v)) + + +/* 2 REG_H2C_READ_ADDR_8197F */ + +#define BIT_SHIFT_H2C_READ_ADDR_8197F 0 +#define BIT_MASK_H2C_READ_ADDR_8197F 0x3ffff +#define BIT_H2C_READ_ADDR_8197F(x) (((x) & BIT_MASK_H2C_READ_ADDR_8197F) << BIT_SHIFT_H2C_READ_ADDR_8197F) +#define BITS_H2C_READ_ADDR_8197F (BIT_MASK_H2C_READ_ADDR_8197F << BIT_SHIFT_H2C_READ_ADDR_8197F) +#define BIT_CLEAR_H2C_READ_ADDR_8197F(x) ((x) & (~BITS_H2C_READ_ADDR_8197F)) +#define BIT_GET_H2C_READ_ADDR_8197F(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8197F) & BIT_MASK_H2C_READ_ADDR_8197F) +#define BIT_SET_H2C_READ_ADDR_8197F(x, v) (BIT_CLEAR_H2C_READ_ADDR_8197F(x) | BIT_H2C_READ_ADDR_8197F(v)) + + +/* 2 REG_H2C_WR_ADDR_8197F */ + +#define BIT_SHIFT_H2C_WR_ADDR_8197F 0 +#define BIT_MASK_H2C_WR_ADDR_8197F 0x3ffff +#define BIT_H2C_WR_ADDR_8197F(x) (((x) & BIT_MASK_H2C_WR_ADDR_8197F) << BIT_SHIFT_H2C_WR_ADDR_8197F) +#define BITS_H2C_WR_ADDR_8197F (BIT_MASK_H2C_WR_ADDR_8197F << BIT_SHIFT_H2C_WR_ADDR_8197F) +#define BIT_CLEAR_H2C_WR_ADDR_8197F(x) ((x) & (~BITS_H2C_WR_ADDR_8197F)) +#define BIT_GET_H2C_WR_ADDR_8197F(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8197F) & BIT_MASK_H2C_WR_ADDR_8197F) +#define BIT_SET_H2C_WR_ADDR_8197F(x, v) (BIT_CLEAR_H2C_WR_ADDR_8197F(x) | BIT_H2C_WR_ADDR_8197F(v)) + + +/* 2 REG_H2C_INFO_8197F */ +#define BIT_EXQ_EN_PUBLIC_LIMIT_8197F BIT(11) +#define BIT_NPQ_EN_PUBLIC_LIMIT_8197F BIT(10) +#define BIT_LPQ_EN_PUBLIC_LIMIT_8197F BIT(9) +#define BIT_HPQ_EN_PUBLIC_LIMIT_8197F BIT(8) +#define BIT_H2C_SPACE_VLD_8197F BIT(3) +#define BIT_H2C_WR_ADDR_RST_8197F BIT(2) + +#define BIT_SHIFT_H2C_LEN_SEL_8197F 0 +#define BIT_MASK_H2C_LEN_SEL_8197F 0x3 +#define BIT_H2C_LEN_SEL_8197F(x) (((x) & BIT_MASK_H2C_LEN_SEL_8197F) << BIT_SHIFT_H2C_LEN_SEL_8197F) +#define BITS_H2C_LEN_SEL_8197F (BIT_MASK_H2C_LEN_SEL_8197F << BIT_SHIFT_H2C_LEN_SEL_8197F) +#define BIT_CLEAR_H2C_LEN_SEL_8197F(x) ((x) & (~BITS_H2C_LEN_SEL_8197F)) +#define BIT_GET_H2C_LEN_SEL_8197F(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8197F) & BIT_MASK_H2C_LEN_SEL_8197F) +#define BIT_SET_H2C_LEN_SEL_8197F(x, v) (BIT_CLEAR_H2C_LEN_SEL_8197F(x) | BIT_H2C_LEN_SEL_8197F(v)) + + +#define BIT_SHIFT_VI_PUB_LIMIT_8197F 16 +#define BIT_MASK_VI_PUB_LIMIT_8197F 0xfff +#define BIT_VI_PUB_LIMIT_8197F(x) (((x) & BIT_MASK_VI_PUB_LIMIT_8197F) << BIT_SHIFT_VI_PUB_LIMIT_8197F) +#define BITS_VI_PUB_LIMIT_8197F (BIT_MASK_VI_PUB_LIMIT_8197F << BIT_SHIFT_VI_PUB_LIMIT_8197F) +#define BIT_CLEAR_VI_PUB_LIMIT_8197F(x) ((x) & (~BITS_VI_PUB_LIMIT_8197F)) +#define BIT_GET_VI_PUB_LIMIT_8197F(x) (((x) >> BIT_SHIFT_VI_PUB_LIMIT_8197F) & BIT_MASK_VI_PUB_LIMIT_8197F) +#define BIT_SET_VI_PUB_LIMIT_8197F(x, v) (BIT_CLEAR_VI_PUB_LIMIT_8197F(x) | BIT_VI_PUB_LIMIT_8197F(v)) + + +#define BIT_SHIFT_VO_PUB_LIMIT_8197F 0 +#define BIT_MASK_VO_PUB_LIMIT_8197F 0xfff +#define BIT_VO_PUB_LIMIT_8197F(x) (((x) & BIT_MASK_VO_PUB_LIMIT_8197F) << BIT_SHIFT_VO_PUB_LIMIT_8197F) +#define BITS_VO_PUB_LIMIT_8197F (BIT_MASK_VO_PUB_LIMIT_8197F << BIT_SHIFT_VO_PUB_LIMIT_8197F) +#define BIT_CLEAR_VO_PUB_LIMIT_8197F(x) ((x) & (~BITS_VO_PUB_LIMIT_8197F)) +#define BIT_GET_VO_PUB_LIMIT_8197F(x) (((x) >> BIT_SHIFT_VO_PUB_LIMIT_8197F) & BIT_MASK_VO_PUB_LIMIT_8197F) +#define BIT_SET_VO_PUB_LIMIT_8197F(x, v) (BIT_CLEAR_VO_PUB_LIMIT_8197F(x) | BIT_VO_PUB_LIMIT_8197F(v)) + + +#define BIT_SHIFT_BK_PUB_LIMIT_8197F 16 +#define BIT_MASK_BK_PUB_LIMIT_8197F 0xfff +#define BIT_BK_PUB_LIMIT_8197F(x) (((x) & BIT_MASK_BK_PUB_LIMIT_8197F) << BIT_SHIFT_BK_PUB_LIMIT_8197F) +#define BITS_BK_PUB_LIMIT_8197F (BIT_MASK_BK_PUB_LIMIT_8197F << BIT_SHIFT_BK_PUB_LIMIT_8197F) +#define BIT_CLEAR_BK_PUB_LIMIT_8197F(x) ((x) & (~BITS_BK_PUB_LIMIT_8197F)) +#define BIT_GET_BK_PUB_LIMIT_8197F(x) (((x) >> BIT_SHIFT_BK_PUB_LIMIT_8197F) & BIT_MASK_BK_PUB_LIMIT_8197F) +#define BIT_SET_BK_PUB_LIMIT_8197F(x, v) (BIT_CLEAR_BK_PUB_LIMIT_8197F(x) | BIT_BK_PUB_LIMIT_8197F(v)) + + +#define BIT_SHIFT_BE_PUB_LIMIT_8197F 0 +#define BIT_MASK_BE_PUB_LIMIT_8197F 0xfff +#define BIT_BE_PUB_LIMIT_8197F(x) (((x) & BIT_MASK_BE_PUB_LIMIT_8197F) << BIT_SHIFT_BE_PUB_LIMIT_8197F) +#define BITS_BE_PUB_LIMIT_8197F (BIT_MASK_BE_PUB_LIMIT_8197F << BIT_SHIFT_BE_PUB_LIMIT_8197F) +#define BIT_CLEAR_BE_PUB_LIMIT_8197F(x) ((x) & (~BITS_BE_PUB_LIMIT_8197F)) +#define BIT_GET_BE_PUB_LIMIT_8197F(x) (((x) >> BIT_SHIFT_BE_PUB_LIMIT_8197F) & BIT_MASK_BE_PUB_LIMIT_8197F) +#define BIT_SET_BE_PUB_LIMIT_8197F(x, v) (BIT_CLEAR_BE_PUB_LIMIT_8197F(x) | BIT_BE_PUB_LIMIT_8197F(v)) + + +/* 2 REG_RXDMA_AGG_PG_TH_8197F */ +#define BIT_DMA_STORE_MODE_8197F BIT(31) +#define BIT_EN_FW_ADD_8197F BIT(30) +#define BIT_EN_PRE_CALC_8197F BIT(29) +#define BIT_RXAGG_SW_EN_8197F BIT(28) + +#define BIT_SHIFT_PKT_NUM_WOL_8197F 16 +#define BIT_MASK_PKT_NUM_WOL_8197F 0xff +#define BIT_PKT_NUM_WOL_8197F(x) (((x) & BIT_MASK_PKT_NUM_WOL_8197F) << BIT_SHIFT_PKT_NUM_WOL_8197F) +#define BITS_PKT_NUM_WOL_8197F (BIT_MASK_PKT_NUM_WOL_8197F << BIT_SHIFT_PKT_NUM_WOL_8197F) +#define BIT_CLEAR_PKT_NUM_WOL_8197F(x) ((x) & (~BITS_PKT_NUM_WOL_8197F)) +#define BIT_GET_PKT_NUM_WOL_8197F(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8197F) & BIT_MASK_PKT_NUM_WOL_8197F) +#define BIT_SET_PKT_NUM_WOL_8197F(x, v) (BIT_CLEAR_PKT_NUM_WOL_8197F(x) | BIT_PKT_NUM_WOL_8197F(v)) + + +#define BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH_8197F 8 +#define BIT_MASK_RXDMA_AGG_TIMEOUT_TH_8197F 0xff +#define BIT_RXDMA_AGG_TIMEOUT_TH_8197F(x) (((x) & BIT_MASK_RXDMA_AGG_TIMEOUT_TH_8197F) << BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH_8197F) +#define BITS_RXDMA_AGG_TIMEOUT_TH_8197F (BIT_MASK_RXDMA_AGG_TIMEOUT_TH_8197F << BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH_8197F) +#define BIT_CLEAR_RXDMA_AGG_TIMEOUT_TH_8197F(x) ((x) & (~BITS_RXDMA_AGG_TIMEOUT_TH_8197F)) +#define BIT_GET_RXDMA_AGG_TIMEOUT_TH_8197F(x) (((x) >> BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH_8197F) & BIT_MASK_RXDMA_AGG_TIMEOUT_TH_8197F) +#define BIT_SET_RXDMA_AGG_TIMEOUT_TH_8197F(x, v) (BIT_CLEAR_RXDMA_AGG_TIMEOUT_TH_8197F(x) | BIT_RXDMA_AGG_TIMEOUT_TH_8197F(v)) + + +#define BIT_SHIFT_RXDMA_AGG_PG_TH_8197F 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_8197F 0xff +#define BIT_RXDMA_AGG_PG_TH_8197F(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8197F) << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) +#define BITS_RXDMA_AGG_PG_TH_8197F (BIT_MASK_RXDMA_AGG_PG_TH_8197F << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8197F)) +#define BIT_GET_RXDMA_AGG_PG_TH_8197F(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) & BIT_MASK_RXDMA_AGG_PG_TH_8197F) +#define BIT_SET_RXDMA_AGG_PG_TH_8197F(x, v) (BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) | BIT_RXDMA_AGG_PG_TH_8197F(v)) + + +/* 2 REG_RXPKT_NUM_8197F */ + +#define BIT_SHIFT_RXPKT_NUM_8197F 24 +#define BIT_MASK_RXPKT_NUM_8197F 0xff +#define BIT_RXPKT_NUM_8197F(x) (((x) & BIT_MASK_RXPKT_NUM_8197F) << BIT_SHIFT_RXPKT_NUM_8197F) +#define BITS_RXPKT_NUM_8197F (BIT_MASK_RXPKT_NUM_8197F << BIT_SHIFT_RXPKT_NUM_8197F) +#define BIT_CLEAR_RXPKT_NUM_8197F(x) ((x) & (~BITS_RXPKT_NUM_8197F)) +#define BIT_GET_RXPKT_NUM_8197F(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8197F) & BIT_MASK_RXPKT_NUM_8197F) +#define BIT_SET_RXPKT_NUM_8197F(x, v) (BIT_CLEAR_RXPKT_NUM_8197F(x) | BIT_RXPKT_NUM_8197F(v)) + + +#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F 20 +#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F 0xf +#define BIT_FW_UPD_RDPTR19_TO_16_8197F(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) +#define BITS_FW_UPD_RDPTR19_TO_16_8197F (BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8197F)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8197F(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F) +#define BIT_SET_FW_UPD_RDPTR19_TO_16_8197F(x, v) (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) | BIT_FW_UPD_RDPTR19_TO_16_8197F(v)) + +#define BIT_RXDMA_REQ_8197F BIT(19) +#define BIT_RW_RELEASE_EN_8197F BIT(18) +#define BIT_RXDMA_IDLE_8197F BIT(17) +#define BIT_RXPKT_RELEASE_POLL_8197F BIT(16) + +#define BIT_SHIFT_FW_UPD_RDPTR_8197F 0 +#define BIT_MASK_FW_UPD_RDPTR_8197F 0xffff +#define BIT_FW_UPD_RDPTR_8197F(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8197F) << BIT_SHIFT_FW_UPD_RDPTR_8197F) +#define BITS_FW_UPD_RDPTR_8197F (BIT_MASK_FW_UPD_RDPTR_8197F << BIT_SHIFT_FW_UPD_RDPTR_8197F) +#define BIT_CLEAR_FW_UPD_RDPTR_8197F(x) ((x) & (~BITS_FW_UPD_RDPTR_8197F)) +#define BIT_GET_FW_UPD_RDPTR_8197F(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8197F) & BIT_MASK_FW_UPD_RDPTR_8197F) +#define BIT_SET_FW_UPD_RDPTR_8197F(x, v) (BIT_CLEAR_FW_UPD_RDPTR_8197F(x) | BIT_FW_UPD_RDPTR_8197F(v)) + + +/* 2 REG_RXDMA_STATUS_8197F */ +#define BIT_FC2H_PKT_OVERFLOW_8197F BIT(8) +#define BIT_C2H_PKT_OVF_8197F BIT(7) +#define BIT_AGG_CONFGI_ISSUE_8197F BIT(6) +#define BIT_FW_POLL_ISSUE_8197F BIT(5) +#define BIT_RX_DATA_UDN_8197F BIT(4) +#define BIT_RX_SFF_UDN_8197F BIT(3) +#define BIT_RX_SFF_OVF_8197F BIT(2) +#define BIT_RXPKT_OVF_8197F BIT(0) + +/* 2 REG_RXDMA_DPR_8197F */ + +#define BIT_SHIFT_RDE_DEBUG_8197F 0 +#define BIT_MASK_RDE_DEBUG_8197F 0xffffffffL +#define BIT_RDE_DEBUG_8197F(x) (((x) & BIT_MASK_RDE_DEBUG_8197F) << BIT_SHIFT_RDE_DEBUG_8197F) +#define BITS_RDE_DEBUG_8197F (BIT_MASK_RDE_DEBUG_8197F << BIT_SHIFT_RDE_DEBUG_8197F) +#define BIT_CLEAR_RDE_DEBUG_8197F(x) ((x) & (~BITS_RDE_DEBUG_8197F)) +#define BIT_GET_RDE_DEBUG_8197F(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8197F) & BIT_MASK_RDE_DEBUG_8197F) +#define BIT_SET_RDE_DEBUG_8197F(x, v) (BIT_CLEAR_RDE_DEBUG_8197F(x) | BIT_RDE_DEBUG_8197F(v)) + + +/* 2 REG_RXDMA_MODE_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_EN_SPD_8197F BIT(6) + +#define BIT_SHIFT_BURST_SIZE_8197F 4 +#define BIT_MASK_BURST_SIZE_8197F 0x3 +#define BIT_BURST_SIZE_8197F(x) (((x) & BIT_MASK_BURST_SIZE_8197F) << BIT_SHIFT_BURST_SIZE_8197F) +#define BITS_BURST_SIZE_8197F (BIT_MASK_BURST_SIZE_8197F << BIT_SHIFT_BURST_SIZE_8197F) +#define BIT_CLEAR_BURST_SIZE_8197F(x) ((x) & (~BITS_BURST_SIZE_8197F)) +#define BIT_GET_BURST_SIZE_8197F(x) (((x) >> BIT_SHIFT_BURST_SIZE_8197F) & BIT_MASK_BURST_SIZE_8197F) +#define BIT_SET_BURST_SIZE_8197F(x, v) (BIT_CLEAR_BURST_SIZE_8197F(x) | BIT_BURST_SIZE_8197F(v)) + + +#define BIT_SHIFT_BURST_CNT_8197F 2 +#define BIT_MASK_BURST_CNT_8197F 0x3 +#define BIT_BURST_CNT_8197F(x) (((x) & BIT_MASK_BURST_CNT_8197F) << BIT_SHIFT_BURST_CNT_8197F) +#define BITS_BURST_CNT_8197F (BIT_MASK_BURST_CNT_8197F << BIT_SHIFT_BURST_CNT_8197F) +#define BIT_CLEAR_BURST_CNT_8197F(x) ((x) & (~BITS_BURST_CNT_8197F)) +#define BIT_GET_BURST_CNT_8197F(x) (((x) >> BIT_SHIFT_BURST_CNT_8197F) & BIT_MASK_BURST_CNT_8197F) +#define BIT_SET_BURST_CNT_8197F(x, v) (BIT_CLEAR_BURST_CNT_8197F(x) | BIT_BURST_CNT_8197F(v)) + +#define BIT_DMA_MODE_8197F BIT(1) + +/* 2 REG_C2H_PKT_8197F */ + +#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F 24 +#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F 0xf +#define BIT_R_C2H_STR_ADDR_16_TO_19_8197F(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) +#define BITS_R_C2H_STR_ADDR_16_TO_19_8197F (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8197F)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8197F(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8197F(x, v) (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) | BIT_R_C2H_STR_ADDR_16_TO_19_8197F(v)) + +#define BIT_R_C2H_PKT_REQ_8197F BIT(16) + +#define BIT_SHIFT_R_C2H_STR_ADDR_8197F 0 +#define BIT_MASK_R_C2H_STR_ADDR_8197F 0xffff +#define BIT_R_C2H_STR_ADDR_8197F(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8197F) << BIT_SHIFT_R_C2H_STR_ADDR_8197F) +#define BITS_R_C2H_STR_ADDR_8197F (BIT_MASK_R_C2H_STR_ADDR_8197F << BIT_SHIFT_R_C2H_STR_ADDR_8197F) +#define BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) ((x) & (~BITS_R_C2H_STR_ADDR_8197F)) +#define BIT_GET_R_C2H_STR_ADDR_8197F(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8197F) & BIT_MASK_R_C2H_STR_ADDR_8197F) +#define BIT_SET_R_C2H_STR_ADDR_8197F(x, v) (BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) | BIT_R_C2H_STR_ADDR_8197F(v)) + + +/* 2 REG_FWFF_C2H_8197F */ + +#define BIT_SHIFT_C2H_DMA_ADDR_8197F 0 +#define BIT_MASK_C2H_DMA_ADDR_8197F 0x3ffff +#define BIT_C2H_DMA_ADDR_8197F(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8197F) << BIT_SHIFT_C2H_DMA_ADDR_8197F) +#define BITS_C2H_DMA_ADDR_8197F (BIT_MASK_C2H_DMA_ADDR_8197F << BIT_SHIFT_C2H_DMA_ADDR_8197F) +#define BIT_CLEAR_C2H_DMA_ADDR_8197F(x) ((x) & (~BITS_C2H_DMA_ADDR_8197F)) +#define BIT_GET_C2H_DMA_ADDR_8197F(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8197F) & BIT_MASK_C2H_DMA_ADDR_8197F) +#define BIT_SET_C2H_DMA_ADDR_8197F(x, v) (BIT_CLEAR_C2H_DMA_ADDR_8197F(x) | BIT_C2H_DMA_ADDR_8197F(v)) + + +/* 2 REG_FWFF_CTRL_8197F */ +#define BIT_FWFF_DMAPKT_REQ_8197F BIT(31) + +#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F 16 +#define BIT_MASK_FWFF_DMA_PKT_NUM_8197F 0xff +#define BIT_FWFF_DMA_PKT_NUM_8197F(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8197F) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) +#define BITS_FWFF_DMA_PKT_NUM_8197F (BIT_MASK_FWFF_DMA_PKT_NUM_8197F << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM_8197F)) +#define BIT_GET_FWFF_DMA_PKT_NUM_8197F(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) & BIT_MASK_FWFF_DMA_PKT_NUM_8197F) +#define BIT_SET_FWFF_DMA_PKT_NUM_8197F(x, v) (BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) | BIT_FWFF_DMA_PKT_NUM_8197F(v)) + + +#define BIT_SHIFT_FWFF_STR_ADDR_8197F 0 +#define BIT_MASK_FWFF_STR_ADDR_8197F 0xffff +#define BIT_FWFF_STR_ADDR_8197F(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8197F) << BIT_SHIFT_FWFF_STR_ADDR_8197F) +#define BITS_FWFF_STR_ADDR_8197F (BIT_MASK_FWFF_STR_ADDR_8197F << BIT_SHIFT_FWFF_STR_ADDR_8197F) +#define BIT_CLEAR_FWFF_STR_ADDR_8197F(x) ((x) & (~BITS_FWFF_STR_ADDR_8197F)) +#define BIT_GET_FWFF_STR_ADDR_8197F(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8197F) & BIT_MASK_FWFF_STR_ADDR_8197F) +#define BIT_SET_FWFF_STR_ADDR_8197F(x, v) (BIT_CLEAR_FWFF_STR_ADDR_8197F(x) | BIT_FWFF_STR_ADDR_8197F(v)) + + +/* 2 REG_FWFF_PKT_INFO_8197F */ + +#define BIT_SHIFT_FWFF_PKT_QUEUED_8197F 16 +#define BIT_MASK_FWFF_PKT_QUEUED_8197F 0xff +#define BIT_FWFF_PKT_QUEUED_8197F(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8197F) << BIT_SHIFT_FWFF_PKT_QUEUED_8197F) +#define BITS_FWFF_PKT_QUEUED_8197F (BIT_MASK_FWFF_PKT_QUEUED_8197F << BIT_SHIFT_FWFF_PKT_QUEUED_8197F) +#define BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8197F)) +#define BIT_GET_FWFF_PKT_QUEUED_8197F(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8197F) & BIT_MASK_FWFF_PKT_QUEUED_8197F) +#define BIT_SET_FWFF_PKT_QUEUED_8197F(x, v) (BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) | BIT_FWFF_PKT_QUEUED_8197F(v)) + + +#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F 0 +#define BIT_MASK_FWFF_PKT_STR_ADDR_8197F 0xffff +#define BIT_FWFF_PKT_STR_ADDR_8197F(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8197F) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) +#define BITS_FWFF_PKT_STR_ADDR_8197F (BIT_MASK_FWFF_PKT_STR_ADDR_8197F << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_8197F)) +#define BIT_GET_FWFF_PKT_STR_ADDR_8197F(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) & BIT_MASK_FWFF_PKT_STR_ADDR_8197F) +#define BIT_SET_FWFF_PKT_STR_ADDR_8197F(x, v) (BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) | BIT_FWFF_PKT_STR_ADDR_8197F(v)) + + +/* 2 REG_FC2H_INFO_8197F */ +#define BIT_FC2H_PKT_REQ_8197F BIT(16) + +#define BIT_SHIFT_FC2H_STR_ADDR_8197F 17 +#define BIT_MASK_FC2H_STR_ADDR_8197F 0x7fff +#define BIT_FC2H_STR_ADDR_8197F(x) (((x) & BIT_MASK_FC2H_STR_ADDR_8197F) << BIT_SHIFT_FC2H_STR_ADDR_8197F) +#define BITS_FC2H_STR_ADDR_8197F (BIT_MASK_FC2H_STR_ADDR_8197F << BIT_SHIFT_FC2H_STR_ADDR_8197F) +#define BIT_CLEAR_FC2H_STR_ADDR_8197F(x) ((x) & (~BITS_FC2H_STR_ADDR_8197F)) +#define BIT_GET_FC2H_STR_ADDR_8197F(x) (((x) >> BIT_SHIFT_FC2H_STR_ADDR_8197F) & BIT_MASK_FC2H_STR_ADDR_8197F) +#define BIT_SET_FC2H_STR_ADDR_8197F(x, v) (BIT_CLEAR_FC2H_STR_ADDR_8197F(x) | BIT_FC2H_STR_ADDR_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_DDMA_CH0SA_8197F */ + +#define BIT_SHIFT_DDMACH0_SA_8197F 0 +#define BIT_MASK_DDMACH0_SA_8197F 0xffffffffL +#define BIT_DDMACH0_SA_8197F(x) (((x) & BIT_MASK_DDMACH0_SA_8197F) << BIT_SHIFT_DDMACH0_SA_8197F) +#define BITS_DDMACH0_SA_8197F (BIT_MASK_DDMACH0_SA_8197F << BIT_SHIFT_DDMACH0_SA_8197F) +#define BIT_CLEAR_DDMACH0_SA_8197F(x) ((x) & (~BITS_DDMACH0_SA_8197F)) +#define BIT_GET_DDMACH0_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8197F) & BIT_MASK_DDMACH0_SA_8197F) +#define BIT_SET_DDMACH0_SA_8197F(x, v) (BIT_CLEAR_DDMACH0_SA_8197F(x) | BIT_DDMACH0_SA_8197F(v)) + + +/* 2 REG_DDMA_CH0DA_8197F */ + +#define BIT_SHIFT_DDMACH0_DA_8197F 0 +#define BIT_MASK_DDMACH0_DA_8197F 0xffffffffL +#define BIT_DDMACH0_DA_8197F(x) (((x) & BIT_MASK_DDMACH0_DA_8197F) << BIT_SHIFT_DDMACH0_DA_8197F) +#define BITS_DDMACH0_DA_8197F (BIT_MASK_DDMACH0_DA_8197F << BIT_SHIFT_DDMACH0_DA_8197F) +#define BIT_CLEAR_DDMACH0_DA_8197F(x) ((x) & (~BITS_DDMACH0_DA_8197F)) +#define BIT_GET_DDMACH0_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8197F) & BIT_MASK_DDMACH0_DA_8197F) +#define BIT_SET_DDMACH0_DA_8197F(x, v) (BIT_CLEAR_DDMACH0_DA_8197F(x) | BIT_DDMACH0_DA_8197F(v)) + + +/* 2 REG_DDMA_CH0CTRL_8197F */ +#define BIT_DDMACH0_OWN_8197F BIT(31) +#define BIT_DDMACH0_CHKSUM_EN_8197F BIT(29) +#define BIT_DDMACH0_DA_W_DISABLE_8197F BIT(28) +#define BIT_DDMACH0_CHKSUM_STS_8197F BIT(27) +#define BIT_DDMACH0_DDMA_MODE_8197F BIT(26) +#define BIT_DDMACH0_RESET_CHKSUM_STS_8197F BIT(25) +#define BIT_DDMACH0_CHKSUM_CONT_8197F BIT(24) + +#define BIT_SHIFT_DDMACH0_DLEN_8197F 0 +#define BIT_MASK_DDMACH0_DLEN_8197F 0x3ffff +#define BIT_DDMACH0_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH0_DLEN_8197F) << BIT_SHIFT_DDMACH0_DLEN_8197F) +#define BITS_DDMACH0_DLEN_8197F (BIT_MASK_DDMACH0_DLEN_8197F << BIT_SHIFT_DDMACH0_DLEN_8197F) +#define BIT_CLEAR_DDMACH0_DLEN_8197F(x) ((x) & (~BITS_DDMACH0_DLEN_8197F)) +#define BIT_GET_DDMACH0_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8197F) & BIT_MASK_DDMACH0_DLEN_8197F) +#define BIT_SET_DDMACH0_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH0_DLEN_8197F(x) | BIT_DDMACH0_DLEN_8197F(v)) + + +/* 2 REG_DDMA_CH1SA_8197F */ + +#define BIT_SHIFT_DDMACH1_SA_8197F 0 +#define BIT_MASK_DDMACH1_SA_8197F 0xffffffffL +#define BIT_DDMACH1_SA_8197F(x) (((x) & BIT_MASK_DDMACH1_SA_8197F) << BIT_SHIFT_DDMACH1_SA_8197F) +#define BITS_DDMACH1_SA_8197F (BIT_MASK_DDMACH1_SA_8197F << BIT_SHIFT_DDMACH1_SA_8197F) +#define BIT_CLEAR_DDMACH1_SA_8197F(x) ((x) & (~BITS_DDMACH1_SA_8197F)) +#define BIT_GET_DDMACH1_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8197F) & BIT_MASK_DDMACH1_SA_8197F) +#define BIT_SET_DDMACH1_SA_8197F(x, v) (BIT_CLEAR_DDMACH1_SA_8197F(x) | BIT_DDMACH1_SA_8197F(v)) + + +/* 2 REG_DDMA_CH1DA_8197F */ + +#define BIT_SHIFT_DDMACH1_DA_8197F 0 +#define BIT_MASK_DDMACH1_DA_8197F 0xffffffffL +#define BIT_DDMACH1_DA_8197F(x) (((x) & BIT_MASK_DDMACH1_DA_8197F) << BIT_SHIFT_DDMACH1_DA_8197F) +#define BITS_DDMACH1_DA_8197F (BIT_MASK_DDMACH1_DA_8197F << BIT_SHIFT_DDMACH1_DA_8197F) +#define BIT_CLEAR_DDMACH1_DA_8197F(x) ((x) & (~BITS_DDMACH1_DA_8197F)) +#define BIT_GET_DDMACH1_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8197F) & BIT_MASK_DDMACH1_DA_8197F) +#define BIT_SET_DDMACH1_DA_8197F(x, v) (BIT_CLEAR_DDMACH1_DA_8197F(x) | BIT_DDMACH1_DA_8197F(v)) + + +/* 2 REG_DDMA_CH1CTRL_8197F */ +#define BIT_DDMACH1_OWN_8197F BIT(31) +#define BIT_DDMACH1_CHKSUM_EN_8197F BIT(29) +#define BIT_DDMACH1_DA_W_DISABLE_8197F BIT(28) +#define BIT_DDMACH1_CHKSUM_STS_8197F BIT(27) +#define BIT_DDMACH1_DDMA_MODE_8197F BIT(26) +#define BIT_DDMACH1_RESET_CHKSUM_STS_8197F BIT(25) +#define BIT_DDMACH1_CHKSUM_CONT_8197F BIT(24) + +#define BIT_SHIFT_DDMACH1_DLEN_8197F 0 +#define BIT_MASK_DDMACH1_DLEN_8197F 0x3ffff +#define BIT_DDMACH1_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH1_DLEN_8197F) << BIT_SHIFT_DDMACH1_DLEN_8197F) +#define BITS_DDMACH1_DLEN_8197F (BIT_MASK_DDMACH1_DLEN_8197F << BIT_SHIFT_DDMACH1_DLEN_8197F) +#define BIT_CLEAR_DDMACH1_DLEN_8197F(x) ((x) & (~BITS_DDMACH1_DLEN_8197F)) +#define BIT_GET_DDMACH1_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8197F) & BIT_MASK_DDMACH1_DLEN_8197F) +#define BIT_SET_DDMACH1_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH1_DLEN_8197F(x) | BIT_DDMACH1_DLEN_8197F(v)) + + +/* 2 REG_DDMA_CH2SA_8197F */ + +#define BIT_SHIFT_DDMACH2_SA_8197F 0 +#define BIT_MASK_DDMACH2_SA_8197F 0xffffffffL +#define BIT_DDMACH2_SA_8197F(x) (((x) & BIT_MASK_DDMACH2_SA_8197F) << BIT_SHIFT_DDMACH2_SA_8197F) +#define BITS_DDMACH2_SA_8197F (BIT_MASK_DDMACH2_SA_8197F << BIT_SHIFT_DDMACH2_SA_8197F) +#define BIT_CLEAR_DDMACH2_SA_8197F(x) ((x) & (~BITS_DDMACH2_SA_8197F)) +#define BIT_GET_DDMACH2_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8197F) & BIT_MASK_DDMACH2_SA_8197F) +#define BIT_SET_DDMACH2_SA_8197F(x, v) (BIT_CLEAR_DDMACH2_SA_8197F(x) | BIT_DDMACH2_SA_8197F(v)) + + +/* 2 REG_DDMA_CH2DA_8197F */ + +#define BIT_SHIFT_DDMACH2_DA_8197F 0 +#define BIT_MASK_DDMACH2_DA_8197F 0xffffffffL +#define BIT_DDMACH2_DA_8197F(x) (((x) & BIT_MASK_DDMACH2_DA_8197F) << BIT_SHIFT_DDMACH2_DA_8197F) +#define BITS_DDMACH2_DA_8197F (BIT_MASK_DDMACH2_DA_8197F << BIT_SHIFT_DDMACH2_DA_8197F) +#define BIT_CLEAR_DDMACH2_DA_8197F(x) ((x) & (~BITS_DDMACH2_DA_8197F)) +#define BIT_GET_DDMACH2_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8197F) & BIT_MASK_DDMACH2_DA_8197F) +#define BIT_SET_DDMACH2_DA_8197F(x, v) (BIT_CLEAR_DDMACH2_DA_8197F(x) | BIT_DDMACH2_DA_8197F(v)) + + +/* 2 REG_DDMA_CH2CTRL_8197F */ +#define BIT_DDMACH2_OWN_8197F BIT(31) +#define BIT_DDMACH2_CHKSUM_EN_8197F BIT(29) +#define BIT_DDMACH2_DA_W_DISABLE_8197F BIT(28) +#define BIT_DDMACH2_CHKSUM_STS_8197F BIT(27) +#define BIT_DDMACH2_DDMA_MODE_8197F BIT(26) +#define BIT_DDMACH2_RESET_CHKSUM_STS_8197F BIT(25) +#define BIT_DDMACH2_CHKSUM_CONT_8197F BIT(24) + +#define BIT_SHIFT_DDMACH2_DLEN_8197F 0 +#define BIT_MASK_DDMACH2_DLEN_8197F 0x3ffff +#define BIT_DDMACH2_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH2_DLEN_8197F) << BIT_SHIFT_DDMACH2_DLEN_8197F) +#define BITS_DDMACH2_DLEN_8197F (BIT_MASK_DDMACH2_DLEN_8197F << BIT_SHIFT_DDMACH2_DLEN_8197F) +#define BIT_CLEAR_DDMACH2_DLEN_8197F(x) ((x) & (~BITS_DDMACH2_DLEN_8197F)) +#define BIT_GET_DDMACH2_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8197F) & BIT_MASK_DDMACH2_DLEN_8197F) +#define BIT_SET_DDMACH2_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH2_DLEN_8197F(x) | BIT_DDMACH2_DLEN_8197F(v)) + + +/* 2 REG_DDMA_CH3SA_8197F */ + +#define BIT_SHIFT_DDMACH3_SA_8197F 0 +#define BIT_MASK_DDMACH3_SA_8197F 0xffffffffL +#define BIT_DDMACH3_SA_8197F(x) (((x) & BIT_MASK_DDMACH3_SA_8197F) << BIT_SHIFT_DDMACH3_SA_8197F) +#define BITS_DDMACH3_SA_8197F (BIT_MASK_DDMACH3_SA_8197F << BIT_SHIFT_DDMACH3_SA_8197F) +#define BIT_CLEAR_DDMACH3_SA_8197F(x) ((x) & (~BITS_DDMACH3_SA_8197F)) +#define BIT_GET_DDMACH3_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8197F) & BIT_MASK_DDMACH3_SA_8197F) +#define BIT_SET_DDMACH3_SA_8197F(x, v) (BIT_CLEAR_DDMACH3_SA_8197F(x) | BIT_DDMACH3_SA_8197F(v)) + + +/* 2 REG_DDMA_CH3DA_8197F */ + +#define BIT_SHIFT_DDMACH3_DA_8197F 0 +#define BIT_MASK_DDMACH3_DA_8197F 0xffffffffL +#define BIT_DDMACH3_DA_8197F(x) (((x) & BIT_MASK_DDMACH3_DA_8197F) << BIT_SHIFT_DDMACH3_DA_8197F) +#define BITS_DDMACH3_DA_8197F (BIT_MASK_DDMACH3_DA_8197F << BIT_SHIFT_DDMACH3_DA_8197F) +#define BIT_CLEAR_DDMACH3_DA_8197F(x) ((x) & (~BITS_DDMACH3_DA_8197F)) +#define BIT_GET_DDMACH3_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8197F) & BIT_MASK_DDMACH3_DA_8197F) +#define BIT_SET_DDMACH3_DA_8197F(x, v) (BIT_CLEAR_DDMACH3_DA_8197F(x) | BIT_DDMACH3_DA_8197F(v)) + + +/* 2 REG_DDMA_CH3CTRL_8197F */ +#define BIT_DDMACH3_OWN_8197F BIT(31) +#define BIT_DDMACH3_CHKSUM_EN_8197F BIT(29) +#define BIT_DDMACH3_DA_W_DISABLE_8197F BIT(28) +#define BIT_DDMACH3_CHKSUM_STS_8197F BIT(27) +#define BIT_DDMACH3_DDMA_MODE_8197F BIT(26) +#define BIT_DDMACH3_RESET_CHKSUM_STS_8197F BIT(25) +#define BIT_DDMACH3_CHKSUM_CONT_8197F BIT(24) + +#define BIT_SHIFT_DDMACH3_DLEN_8197F 0 +#define BIT_MASK_DDMACH3_DLEN_8197F 0x3ffff +#define BIT_DDMACH3_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH3_DLEN_8197F) << BIT_SHIFT_DDMACH3_DLEN_8197F) +#define BITS_DDMACH3_DLEN_8197F (BIT_MASK_DDMACH3_DLEN_8197F << BIT_SHIFT_DDMACH3_DLEN_8197F) +#define BIT_CLEAR_DDMACH3_DLEN_8197F(x) ((x) & (~BITS_DDMACH3_DLEN_8197F)) +#define BIT_GET_DDMACH3_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8197F) & BIT_MASK_DDMACH3_DLEN_8197F) +#define BIT_SET_DDMACH3_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH3_DLEN_8197F(x) | BIT_DDMACH3_DLEN_8197F(v)) + + +/* 2 REG_DDMA_CH4SA_8197F */ + +#define BIT_SHIFT_DDMACH4_SA_8197F 0 +#define BIT_MASK_DDMACH4_SA_8197F 0xffffffffL +#define BIT_DDMACH4_SA_8197F(x) (((x) & BIT_MASK_DDMACH4_SA_8197F) << BIT_SHIFT_DDMACH4_SA_8197F) +#define BITS_DDMACH4_SA_8197F (BIT_MASK_DDMACH4_SA_8197F << BIT_SHIFT_DDMACH4_SA_8197F) +#define BIT_CLEAR_DDMACH4_SA_8197F(x) ((x) & (~BITS_DDMACH4_SA_8197F)) +#define BIT_GET_DDMACH4_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8197F) & BIT_MASK_DDMACH4_SA_8197F) +#define BIT_SET_DDMACH4_SA_8197F(x, v) (BIT_CLEAR_DDMACH4_SA_8197F(x) | BIT_DDMACH4_SA_8197F(v)) + + +/* 2 REG_DDMA_CH4DA_8197F */ + +#define BIT_SHIFT_DDMACH4_DA_8197F 0 +#define BIT_MASK_DDMACH4_DA_8197F 0xffffffffL +#define BIT_DDMACH4_DA_8197F(x) (((x) & BIT_MASK_DDMACH4_DA_8197F) << BIT_SHIFT_DDMACH4_DA_8197F) +#define BITS_DDMACH4_DA_8197F (BIT_MASK_DDMACH4_DA_8197F << BIT_SHIFT_DDMACH4_DA_8197F) +#define BIT_CLEAR_DDMACH4_DA_8197F(x) ((x) & (~BITS_DDMACH4_DA_8197F)) +#define BIT_GET_DDMACH4_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8197F) & BIT_MASK_DDMACH4_DA_8197F) +#define BIT_SET_DDMACH4_DA_8197F(x, v) (BIT_CLEAR_DDMACH4_DA_8197F(x) | BIT_DDMACH4_DA_8197F(v)) + + +/* 2 REG_DDMA_CH4CTRL_8197F */ +#define BIT_DDMACH4_OWN_8197F BIT(31) +#define BIT_DDMACH4_CHKSUM_EN_8197F BIT(29) +#define BIT_DDMACH4_DA_W_DISABLE_8197F BIT(28) +#define BIT_DDMACH4_CHKSUM_STS_8197F BIT(27) +#define BIT_DDMACH4_DDMA_MODE_8197F BIT(26) +#define BIT_DDMACH4_RESET_CHKSUM_STS_8197F BIT(25) +#define BIT_DDMACH4_CHKSUM_CONT_8197F BIT(24) + +#define BIT_SHIFT_DDMACH4_DLEN_8197F 0 +#define BIT_MASK_DDMACH4_DLEN_8197F 0x3ffff +#define BIT_DDMACH4_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH4_DLEN_8197F) << BIT_SHIFT_DDMACH4_DLEN_8197F) +#define BITS_DDMACH4_DLEN_8197F (BIT_MASK_DDMACH4_DLEN_8197F << BIT_SHIFT_DDMACH4_DLEN_8197F) +#define BIT_CLEAR_DDMACH4_DLEN_8197F(x) ((x) & (~BITS_DDMACH4_DLEN_8197F)) +#define BIT_GET_DDMACH4_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8197F) & BIT_MASK_DDMACH4_DLEN_8197F) +#define BIT_SET_DDMACH4_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH4_DLEN_8197F(x) | BIT_DDMACH4_DLEN_8197F(v)) + + +/* 2 REG_DDMA_CH5SA_8197F */ + +#define BIT_SHIFT_DDMACH5_SA_8197F 0 +#define BIT_MASK_DDMACH5_SA_8197F 0xffffffffL +#define BIT_DDMACH5_SA_8197F(x) (((x) & BIT_MASK_DDMACH5_SA_8197F) << BIT_SHIFT_DDMACH5_SA_8197F) +#define BITS_DDMACH5_SA_8197F (BIT_MASK_DDMACH5_SA_8197F << BIT_SHIFT_DDMACH5_SA_8197F) +#define BIT_CLEAR_DDMACH5_SA_8197F(x) ((x) & (~BITS_DDMACH5_SA_8197F)) +#define BIT_GET_DDMACH5_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8197F) & BIT_MASK_DDMACH5_SA_8197F) +#define BIT_SET_DDMACH5_SA_8197F(x, v) (BIT_CLEAR_DDMACH5_SA_8197F(x) | BIT_DDMACH5_SA_8197F(v)) + + +/* 2 REG_DDMA_CH5DA_8197F */ + +#define BIT_SHIFT_DDMACH5_DA_8197F 0 +#define BIT_MASK_DDMACH5_DA_8197F 0xffffffffL +#define BIT_DDMACH5_DA_8197F(x) (((x) & BIT_MASK_DDMACH5_DA_8197F) << BIT_SHIFT_DDMACH5_DA_8197F) +#define BITS_DDMACH5_DA_8197F (BIT_MASK_DDMACH5_DA_8197F << BIT_SHIFT_DDMACH5_DA_8197F) +#define BIT_CLEAR_DDMACH5_DA_8197F(x) ((x) & (~BITS_DDMACH5_DA_8197F)) +#define BIT_GET_DDMACH5_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8197F) & BIT_MASK_DDMACH5_DA_8197F) +#define BIT_SET_DDMACH5_DA_8197F(x, v) (BIT_CLEAR_DDMACH5_DA_8197F(x) | BIT_DDMACH5_DA_8197F(v)) + + +/* 2 REG_REG_DDMA_CH5CTRL_8197F */ +#define BIT_DDMACH5_OWN_8197F BIT(31) +#define BIT_DDMACH5_CHKSUM_EN_8197F BIT(29) +#define BIT_DDMACH5_DA_W_DISABLE_8197F BIT(28) +#define BIT_DDMACH5_CHKSUM_STS_8197F BIT(27) +#define BIT_DDMACH5_DDMA_MODE_8197F BIT(26) +#define BIT_DDMACH5_RESET_CHKSUM_STS_8197F BIT(25) +#define BIT_DDMACH5_CHKSUM_CONT_8197F BIT(24) + +#define BIT_SHIFT_DDMACH5_DLEN_8197F 0 +#define BIT_MASK_DDMACH5_DLEN_8197F 0x3ffff +#define BIT_DDMACH5_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH5_DLEN_8197F) << BIT_SHIFT_DDMACH5_DLEN_8197F) +#define BITS_DDMACH5_DLEN_8197F (BIT_MASK_DDMACH5_DLEN_8197F << BIT_SHIFT_DDMACH5_DLEN_8197F) +#define BIT_CLEAR_DDMACH5_DLEN_8197F(x) ((x) & (~BITS_DDMACH5_DLEN_8197F)) +#define BIT_GET_DDMACH5_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8197F) & BIT_MASK_DDMACH5_DLEN_8197F) +#define BIT_SET_DDMACH5_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH5_DLEN_8197F(x) | BIT_DDMACH5_DLEN_8197F(v)) + + +/* 2 REG_DDMA_INT_MSK_8197F */ +#define BIT_DDMACH5_MSK_8197F BIT(5) +#define BIT_DDMACH4_MSK_8197F BIT(4) +#define BIT_DDMACH3_MSK_8197F BIT(3) +#define BIT_DDMACH2_MSK_8197F BIT(2) +#define BIT_DDMACH1_MSK_8197F BIT(1) +#define BIT_DDMACH0_MSK_8197F BIT(0) + +/* 2 REG_DDMA_CHSTATUS_8197F */ +#define BIT_DDMACH5_BUSY_8197F BIT(5) +#define BIT_DDMACH4_BUSY_8197F BIT(4) +#define BIT_DDMACH3_BUSY_8197F BIT(3) +#define BIT_DDMACH2_BUSY_8197F BIT(2) +#define BIT_DDMACH1_BUSY_8197F BIT(1) +#define BIT_DDMACH0_BUSY_8197F BIT(0) + +/* 2 REG_DDMA_CHKSUM_8197F */ + +#define BIT_SHIFT_IDDMA0_CHKSUM_8197F 0 +#define BIT_MASK_IDDMA0_CHKSUM_8197F 0xffff +#define BIT_IDDMA0_CHKSUM_8197F(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8197F) << BIT_SHIFT_IDDMA0_CHKSUM_8197F) +#define BITS_IDDMA0_CHKSUM_8197F (BIT_MASK_IDDMA0_CHKSUM_8197F << BIT_SHIFT_IDDMA0_CHKSUM_8197F) +#define BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) ((x) & (~BITS_IDDMA0_CHKSUM_8197F)) +#define BIT_GET_IDDMA0_CHKSUM_8197F(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8197F) & BIT_MASK_IDDMA0_CHKSUM_8197F) +#define BIT_SET_IDDMA0_CHKSUM_8197F(x, v) (BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) | BIT_IDDMA0_CHKSUM_8197F(v)) + + +/* 2 REG_DDMA_MONITOR_8197F */ +#define BIT_IDDMA0_PERMU_UNDERFLOW_8197F BIT(14) +#define BIT_IDDMA0_FIFO_UNDERFLOW_8197F BIT(13) +#define BIT_IDDMA0_FIFO_OVERFLOW_8197F BIT(12) +#define BIT_CH5_ERR_8197F BIT(5) +#define BIT_CH4_ERR_8197F BIT(4) +#define BIT_CH3_ERR_8197F BIT(3) +#define BIT_CH2_ERR_8197F BIT(2) +#define BIT_CH1_ERR_8197F BIT(1) +#define BIT_CH0_ERR_8197F BIT(0) + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_HCI_CTRL_8197F */ +#define BIT_HCIIO_PERSTB_SEL_8197F BIT(31) + +#define BIT_SHIFT_HCI_MAX_RXDMA_8197F 28 +#define BIT_MASK_HCI_MAX_RXDMA_8197F 0x7 +#define BIT_HCI_MAX_RXDMA_8197F(x) (((x) & BIT_MASK_HCI_MAX_RXDMA_8197F) << BIT_SHIFT_HCI_MAX_RXDMA_8197F) +#define BITS_HCI_MAX_RXDMA_8197F (BIT_MASK_HCI_MAX_RXDMA_8197F << BIT_SHIFT_HCI_MAX_RXDMA_8197F) +#define BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) ((x) & (~BITS_HCI_MAX_RXDMA_8197F)) +#define BIT_GET_HCI_MAX_RXDMA_8197F(x) (((x) >> BIT_SHIFT_HCI_MAX_RXDMA_8197F) & BIT_MASK_HCI_MAX_RXDMA_8197F) +#define BIT_SET_HCI_MAX_RXDMA_8197F(x, v) (BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) | BIT_HCI_MAX_RXDMA_8197F(v)) + +#define BIT_MULRW_8197F BIT(27) + +#define BIT_SHIFT_HCI_MAX_TXDMA_8197F 24 +#define BIT_MASK_HCI_MAX_TXDMA_8197F 0x7 +#define BIT_HCI_MAX_TXDMA_8197F(x) (((x) & BIT_MASK_HCI_MAX_TXDMA_8197F) << BIT_SHIFT_HCI_MAX_TXDMA_8197F) +#define BITS_HCI_MAX_TXDMA_8197F (BIT_MASK_HCI_MAX_TXDMA_8197F << BIT_SHIFT_HCI_MAX_TXDMA_8197F) +#define BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) ((x) & (~BITS_HCI_MAX_TXDMA_8197F)) +#define BIT_GET_HCI_MAX_TXDMA_8197F(x) (((x) >> BIT_SHIFT_HCI_MAX_TXDMA_8197F) & BIT_MASK_HCI_MAX_TXDMA_8197F) +#define BIT_SET_HCI_MAX_TXDMA_8197F(x, v) (BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) | BIT_HCI_MAX_TXDMA_8197F(v)) + +#define BIT_EN_CPL_TIMEOUT_PS_8197F BIT(22) +#define BIT_REG_TXDMA_FAIL_PS_8197F BIT(21) +#define BIT_HCI_RST_TRXDMA_INTF_8197F BIT(20) +#define BIT_EN_HWENTR_L1_8197F BIT(19) +#define BIT_EN_ADV_CLKGATE_8197F BIT(18) +#define BIT_HCI_EN_SWENT_L23_8197F BIT(17) +#define BIT_HCI_EN_HWEXT_L1_8197F BIT(16) +#define BIT_RX_CLOSE_EN_8197F BIT(15) +#define BIT_STOP_BCNQ_8197F BIT(14) +#define BIT_STOP_MGQ_8197F BIT(13) +#define BIT_STOP_VOQ_8197F BIT(12) +#define BIT_STOP_VIQ_8197F BIT(11) +#define BIT_STOP_BEQ_8197F BIT(10) +#define BIT_STOP_BKQ_8197F BIT(9) +#define BIT_STOP_RXQ_8197F BIT(8) +#define BIT_STOP_HI7Q_8197F BIT(7) +#define BIT_STOP_HI6Q_8197F BIT(6) +#define BIT_STOP_HI5Q_8197F BIT(5) +#define BIT_STOP_HI4Q_8197F BIT(4) +#define BIT_STOP_HI3Q_8197F BIT(3) +#define BIT_STOP_HI2Q_8197F BIT(2) +#define BIT_STOP_HI1Q_8197F BIT(1) +#define BIT_STOP_HI0Q_8197F BIT(0) + +/* 2 REG_INT_MIG_8197F */ + +#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F 28 +#define BIT_MASK_TXTTIMER_MATCH_NUM_8197F 0xf +#define BIT_TXTTIMER_MATCH_NUM_8197F(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8197F) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) +#define BITS_TXTTIMER_MATCH_NUM_8197F (BIT_MASK_TXTTIMER_MATCH_NUM_8197F << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) +#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) ((x) & (~BITS_TXTTIMER_MATCH_NUM_8197F)) +#define BIT_GET_TXTTIMER_MATCH_NUM_8197F(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) & BIT_MASK_TXTTIMER_MATCH_NUM_8197F) +#define BIT_SET_TXTTIMER_MATCH_NUM_8197F(x, v) (BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) | BIT_TXTTIMER_MATCH_NUM_8197F(v)) + + +#define BIT_SHIFT_TXPKT_NUM_MATCH_8197F 24 +#define BIT_MASK_TXPKT_NUM_MATCH_8197F 0xf +#define BIT_TXPKT_NUM_MATCH_8197F(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8197F) << BIT_SHIFT_TXPKT_NUM_MATCH_8197F) +#define BITS_TXPKT_NUM_MATCH_8197F (BIT_MASK_TXPKT_NUM_MATCH_8197F << BIT_SHIFT_TXPKT_NUM_MATCH_8197F) +#define BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8197F)) +#define BIT_GET_TXPKT_NUM_MATCH_8197F(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8197F) & BIT_MASK_TXPKT_NUM_MATCH_8197F) +#define BIT_SET_TXPKT_NUM_MATCH_8197F(x, v) (BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) | BIT_TXPKT_NUM_MATCH_8197F(v)) + + +#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F 20 +#define BIT_MASK_RXTTIMER_MATCH_NUM_8197F 0xf +#define BIT_RXTTIMER_MATCH_NUM_8197F(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8197F) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) +#define BITS_RXTTIMER_MATCH_NUM_8197F (BIT_MASK_RXTTIMER_MATCH_NUM_8197F << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) +#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) ((x) & (~BITS_RXTTIMER_MATCH_NUM_8197F)) +#define BIT_GET_RXTTIMER_MATCH_NUM_8197F(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) & BIT_MASK_RXTTIMER_MATCH_NUM_8197F) +#define BIT_SET_RXTTIMER_MATCH_NUM_8197F(x, v) (BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) | BIT_RXTTIMER_MATCH_NUM_8197F(v)) + + +#define BIT_SHIFT_RXPKT_NUM_MATCH_8197F 16 +#define BIT_MASK_RXPKT_NUM_MATCH_8197F 0xf +#define BIT_RXPKT_NUM_MATCH_8197F(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8197F) << BIT_SHIFT_RXPKT_NUM_MATCH_8197F) +#define BITS_RXPKT_NUM_MATCH_8197F (BIT_MASK_RXPKT_NUM_MATCH_8197F << BIT_SHIFT_RXPKT_NUM_MATCH_8197F) +#define BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8197F)) +#define BIT_GET_RXPKT_NUM_MATCH_8197F(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8197F) & BIT_MASK_RXPKT_NUM_MATCH_8197F) +#define BIT_SET_RXPKT_NUM_MATCH_8197F(x, v) (BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) | BIT_RXPKT_NUM_MATCH_8197F(v)) + + +#define BIT_SHIFT_MIGRATE_TIMER_8197F 0 +#define BIT_MASK_MIGRATE_TIMER_8197F 0xffff +#define BIT_MIGRATE_TIMER_8197F(x) (((x) & BIT_MASK_MIGRATE_TIMER_8197F) << BIT_SHIFT_MIGRATE_TIMER_8197F) +#define BITS_MIGRATE_TIMER_8197F (BIT_MASK_MIGRATE_TIMER_8197F << BIT_SHIFT_MIGRATE_TIMER_8197F) +#define BIT_CLEAR_MIGRATE_TIMER_8197F(x) ((x) & (~BITS_MIGRATE_TIMER_8197F)) +#define BIT_GET_MIGRATE_TIMER_8197F(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8197F) & BIT_MASK_MIGRATE_TIMER_8197F) +#define BIT_SET_MIGRATE_TIMER_8197F(x, v) (BIT_CLEAR_MIGRATE_TIMER_8197F(x) | BIT_MIGRATE_TIMER_8197F(v)) + + +/* 2 REG_BCNQ_TXBD_DESA_8197F */ + +#define BIT_SHIFT_BCNQ_TXBD_DESA_8197F 0 +#define BIT_MASK_BCNQ_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_BCNQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8197F) << BIT_SHIFT_BCNQ_TXBD_DESA_8197F) +#define BITS_BCNQ_TXBD_DESA_8197F (BIT_MASK_BCNQ_TXBD_DESA_8197F << BIT_SHIFT_BCNQ_TXBD_DESA_8197F) +#define BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8197F)) +#define BIT_GET_BCNQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8197F) & BIT_MASK_BCNQ_TXBD_DESA_8197F) +#define BIT_SET_BCNQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) | BIT_BCNQ_TXBD_DESA_8197F(v)) + + +/* 2 REG_MGQ_TXBD_DESA_8197F */ + +#define BIT_SHIFT_MGQ_TXBD_DESA_8197F 0 +#define BIT_MASK_MGQ_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_MGQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8197F) << BIT_SHIFT_MGQ_TXBD_DESA_8197F) +#define BITS_MGQ_TXBD_DESA_8197F (BIT_MASK_MGQ_TXBD_DESA_8197F << BIT_SHIFT_MGQ_TXBD_DESA_8197F) +#define BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) ((x) & (~BITS_MGQ_TXBD_DESA_8197F)) +#define BIT_GET_MGQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8197F) & BIT_MASK_MGQ_TXBD_DESA_8197F) +#define BIT_SET_MGQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) | BIT_MGQ_TXBD_DESA_8197F(v)) + + +/* 2 REG_VOQ_TXBD_DESA_8197F */ + +#define BIT_SHIFT_VOQ_TXBD_DESA_8197F 0 +#define BIT_MASK_VOQ_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_VOQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8197F) << BIT_SHIFT_VOQ_TXBD_DESA_8197F) +#define BITS_VOQ_TXBD_DESA_8197F (BIT_MASK_VOQ_TXBD_DESA_8197F << BIT_SHIFT_VOQ_TXBD_DESA_8197F) +#define BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) ((x) & (~BITS_VOQ_TXBD_DESA_8197F)) +#define BIT_GET_VOQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8197F) & BIT_MASK_VOQ_TXBD_DESA_8197F) +#define BIT_SET_VOQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) | BIT_VOQ_TXBD_DESA_8197F(v)) + + +/* 2 REG_VIQ_TXBD_DESA_8197F */ + +#define BIT_SHIFT_VIQ_TXBD_DESA_8197F 0 +#define BIT_MASK_VIQ_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_VIQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8197F) << BIT_SHIFT_VIQ_TXBD_DESA_8197F) +#define BITS_VIQ_TXBD_DESA_8197F (BIT_MASK_VIQ_TXBD_DESA_8197F << BIT_SHIFT_VIQ_TXBD_DESA_8197F) +#define BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) ((x) & (~BITS_VIQ_TXBD_DESA_8197F)) +#define BIT_GET_VIQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8197F) & BIT_MASK_VIQ_TXBD_DESA_8197F) +#define BIT_SET_VIQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) | BIT_VIQ_TXBD_DESA_8197F(v)) + + +/* 2 REG_BEQ_TXBD_DESA_8197F */ + +#define BIT_SHIFT_BEQ_TXBD_DESA_8197F 0 +#define BIT_MASK_BEQ_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_BEQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8197F) << BIT_SHIFT_BEQ_TXBD_DESA_8197F) +#define BITS_BEQ_TXBD_DESA_8197F (BIT_MASK_BEQ_TXBD_DESA_8197F << BIT_SHIFT_BEQ_TXBD_DESA_8197F) +#define BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BEQ_TXBD_DESA_8197F)) +#define BIT_GET_BEQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8197F) & BIT_MASK_BEQ_TXBD_DESA_8197F) +#define BIT_SET_BEQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) | BIT_BEQ_TXBD_DESA_8197F(v)) + + +/* 2 REG_BKQ_TXBD_DESA_8197F */ + +#define BIT_SHIFT_BKQ_TXBD_DESA_8197F 0 +#define BIT_MASK_BKQ_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_BKQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8197F) << BIT_SHIFT_BKQ_TXBD_DESA_8197F) +#define BITS_BKQ_TXBD_DESA_8197F (BIT_MASK_BKQ_TXBD_DESA_8197F << BIT_SHIFT_BKQ_TXBD_DESA_8197F) +#define BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BKQ_TXBD_DESA_8197F)) +#define BIT_GET_BKQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8197F) & BIT_MASK_BKQ_TXBD_DESA_8197F) +#define BIT_SET_BKQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) | BIT_BKQ_TXBD_DESA_8197F(v)) + + +/* 2 REG_RXQ_RXBD_DESA_8197F */ + +#define BIT_SHIFT_RXQ_RXBD_DESA_8197F 0 +#define BIT_MASK_RXQ_RXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_RXQ_RXBD_DESA_8197F(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8197F) << BIT_SHIFT_RXQ_RXBD_DESA_8197F) +#define BITS_RXQ_RXBD_DESA_8197F (BIT_MASK_RXQ_RXBD_DESA_8197F << BIT_SHIFT_RXQ_RXBD_DESA_8197F) +#define BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) ((x) & (~BITS_RXQ_RXBD_DESA_8197F)) +#define BIT_GET_RXQ_RXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8197F) & BIT_MASK_RXQ_RXBD_DESA_8197F) +#define BIT_SET_RXQ_RXBD_DESA_8197F(x, v) (BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) | BIT_RXQ_RXBD_DESA_8197F(v)) + + +/* 2 REG_HI0Q_TXBD_DESA_8197F */ + +#define BIT_SHIFT_HI0Q_TXBD_DESA_8197F 0 +#define BIT_MASK_HI0Q_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_HI0Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8197F) << BIT_SHIFT_HI0Q_TXBD_DESA_8197F) +#define BITS_HI0Q_TXBD_DESA_8197F (BIT_MASK_HI0Q_TXBD_DESA_8197F << BIT_SHIFT_HI0Q_TXBD_DESA_8197F) +#define BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8197F)) +#define BIT_GET_HI0Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8197F) & BIT_MASK_HI0Q_TXBD_DESA_8197F) +#define BIT_SET_HI0Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) | BIT_HI0Q_TXBD_DESA_8197F(v)) + + +/* 2 REG_HI1Q_TXBD_DESA_8197F */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_8197F 0 +#define BIT_MASK_HI1Q_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_HI1Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8197F) << BIT_SHIFT_HI1Q_TXBD_DESA_8197F) +#define BITS_HI1Q_TXBD_DESA_8197F (BIT_MASK_HI1Q_TXBD_DESA_8197F << BIT_SHIFT_HI1Q_TXBD_DESA_8197F) +#define BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8197F)) +#define BIT_GET_HI1Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8197F) & BIT_MASK_HI1Q_TXBD_DESA_8197F) +#define BIT_SET_HI1Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) | BIT_HI1Q_TXBD_DESA_8197F(v)) + + +/* 2 REG_HI2Q_TXBD_DESA_8197F */ + +#define BIT_SHIFT_HI2Q_TXBD_DESA_8197F 0 +#define BIT_MASK_HI2Q_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_HI2Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8197F) << BIT_SHIFT_HI2Q_TXBD_DESA_8197F) +#define BITS_HI2Q_TXBD_DESA_8197F (BIT_MASK_HI2Q_TXBD_DESA_8197F << BIT_SHIFT_HI2Q_TXBD_DESA_8197F) +#define BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8197F)) +#define BIT_GET_HI2Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8197F) & BIT_MASK_HI2Q_TXBD_DESA_8197F) +#define BIT_SET_HI2Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) | BIT_HI2Q_TXBD_DESA_8197F(v)) + + +/* 2 REG_HI3Q_TXBD_DESA_8197F */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_8197F 0 +#define BIT_MASK_HI3Q_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_HI3Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8197F) << BIT_SHIFT_HI3Q_TXBD_DESA_8197F) +#define BITS_HI3Q_TXBD_DESA_8197F (BIT_MASK_HI3Q_TXBD_DESA_8197F << BIT_SHIFT_HI3Q_TXBD_DESA_8197F) +#define BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8197F)) +#define BIT_GET_HI3Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8197F) & BIT_MASK_HI3Q_TXBD_DESA_8197F) +#define BIT_SET_HI3Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) | BIT_HI3Q_TXBD_DESA_8197F(v)) + + +/* 2 REG_HI4Q_TXBD_DESA_8197F */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_8197F 0 +#define BIT_MASK_HI4Q_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_HI4Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8197F) << BIT_SHIFT_HI4Q_TXBD_DESA_8197F) +#define BITS_HI4Q_TXBD_DESA_8197F (BIT_MASK_HI4Q_TXBD_DESA_8197F << BIT_SHIFT_HI4Q_TXBD_DESA_8197F) +#define BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8197F)) +#define BIT_GET_HI4Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8197F) & BIT_MASK_HI4Q_TXBD_DESA_8197F) +#define BIT_SET_HI4Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) | BIT_HI4Q_TXBD_DESA_8197F(v)) + + +/* 2 REG_HI5Q_TXBD_DESA_8197F */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_8197F 0 +#define BIT_MASK_HI5Q_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_HI5Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8197F) << BIT_SHIFT_HI5Q_TXBD_DESA_8197F) +#define BITS_HI5Q_TXBD_DESA_8197F (BIT_MASK_HI5Q_TXBD_DESA_8197F << BIT_SHIFT_HI5Q_TXBD_DESA_8197F) +#define BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8197F)) +#define BIT_GET_HI5Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8197F) & BIT_MASK_HI5Q_TXBD_DESA_8197F) +#define BIT_SET_HI5Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) | BIT_HI5Q_TXBD_DESA_8197F(v)) + + +/* 2 REG_HI6Q_TXBD_DESA_8197F */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_8197F 0 +#define BIT_MASK_HI6Q_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_HI6Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8197F) << BIT_SHIFT_HI6Q_TXBD_DESA_8197F) +#define BITS_HI6Q_TXBD_DESA_8197F (BIT_MASK_HI6Q_TXBD_DESA_8197F << BIT_SHIFT_HI6Q_TXBD_DESA_8197F) +#define BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8197F)) +#define BIT_GET_HI6Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8197F) & BIT_MASK_HI6Q_TXBD_DESA_8197F) +#define BIT_SET_HI6Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) | BIT_HI6Q_TXBD_DESA_8197F(v)) + + +/* 2 REG_HI7Q_TXBD_DESA_8197F */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_8197F 0 +#define BIT_MASK_HI7Q_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_HI7Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8197F) << BIT_SHIFT_HI7Q_TXBD_DESA_8197F) +#define BITS_HI7Q_TXBD_DESA_8197F (BIT_MASK_HI7Q_TXBD_DESA_8197F << BIT_SHIFT_HI7Q_TXBD_DESA_8197F) +#define BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8197F)) +#define BIT_GET_HI7Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8197F) & BIT_MASK_HI7Q_TXBD_DESA_8197F) +#define BIT_SET_HI7Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) | BIT_HI7Q_TXBD_DESA_8197F(v)) + + +/* 2 REG_MGQ_TXBD_NUM_8197F */ +#define BIT_HCI_MGQ_FLAG_8197F BIT(14) + +#define BIT_SHIFT_MGQ_DESC_MODE_8197F 12 +#define BIT_MASK_MGQ_DESC_MODE_8197F 0x3 +#define BIT_MGQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8197F) << BIT_SHIFT_MGQ_DESC_MODE_8197F) +#define BITS_MGQ_DESC_MODE_8197F (BIT_MASK_MGQ_DESC_MODE_8197F << BIT_SHIFT_MGQ_DESC_MODE_8197F) +#define BIT_CLEAR_MGQ_DESC_MODE_8197F(x) ((x) & (~BITS_MGQ_DESC_MODE_8197F)) +#define BIT_GET_MGQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8197F) & BIT_MASK_MGQ_DESC_MODE_8197F) +#define BIT_SET_MGQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_MGQ_DESC_MODE_8197F(x) | BIT_MGQ_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_MGQ_DESC_NUM_8197F 0 +#define BIT_MASK_MGQ_DESC_NUM_8197F 0xfff +#define BIT_MGQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8197F) << BIT_SHIFT_MGQ_DESC_NUM_8197F) +#define BITS_MGQ_DESC_NUM_8197F (BIT_MASK_MGQ_DESC_NUM_8197F << BIT_SHIFT_MGQ_DESC_NUM_8197F) +#define BIT_CLEAR_MGQ_DESC_NUM_8197F(x) ((x) & (~BITS_MGQ_DESC_NUM_8197F)) +#define BIT_GET_MGQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8197F) & BIT_MASK_MGQ_DESC_NUM_8197F) +#define BIT_SET_MGQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_MGQ_DESC_NUM_8197F(x) | BIT_MGQ_DESC_NUM_8197F(v)) + + +/* 2 REG_RX_RXBD_NUM_8197F */ +#define BIT_SYS_32_64_8197F BIT(15) + +#define BIT_SHIFT_BCNQ_DESC_MODE_8197F 13 +#define BIT_MASK_BCNQ_DESC_MODE_8197F 0x3 +#define BIT_BCNQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8197F) << BIT_SHIFT_BCNQ_DESC_MODE_8197F) +#define BITS_BCNQ_DESC_MODE_8197F (BIT_MASK_BCNQ_DESC_MODE_8197F << BIT_SHIFT_BCNQ_DESC_MODE_8197F) +#define BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) ((x) & (~BITS_BCNQ_DESC_MODE_8197F)) +#define BIT_GET_BCNQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8197F) & BIT_MASK_BCNQ_DESC_MODE_8197F) +#define BIT_SET_BCNQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) | BIT_BCNQ_DESC_MODE_8197F(v)) + +#define BIT_HCI_BCNQ_FLAG_8197F BIT(12) + +#define BIT_SHIFT_RXQ_DESC_NUM_8197F 0 +#define BIT_MASK_RXQ_DESC_NUM_8197F 0xfff +#define BIT_RXQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8197F) << BIT_SHIFT_RXQ_DESC_NUM_8197F) +#define BITS_RXQ_DESC_NUM_8197F (BIT_MASK_RXQ_DESC_NUM_8197F << BIT_SHIFT_RXQ_DESC_NUM_8197F) +#define BIT_CLEAR_RXQ_DESC_NUM_8197F(x) ((x) & (~BITS_RXQ_DESC_NUM_8197F)) +#define BIT_GET_RXQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8197F) & BIT_MASK_RXQ_DESC_NUM_8197F) +#define BIT_SET_RXQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_RXQ_DESC_NUM_8197F(x) | BIT_RXQ_DESC_NUM_8197F(v)) + + +/* 2 REG_VOQ_TXBD_NUM_8197F */ +#define BIT_HCI_VOQ_FLAG_8197F BIT(14) + +#define BIT_SHIFT_VOQ_DESC_MODE_8197F 12 +#define BIT_MASK_VOQ_DESC_MODE_8197F 0x3 +#define BIT_VOQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8197F) << BIT_SHIFT_VOQ_DESC_MODE_8197F) +#define BITS_VOQ_DESC_MODE_8197F (BIT_MASK_VOQ_DESC_MODE_8197F << BIT_SHIFT_VOQ_DESC_MODE_8197F) +#define BIT_CLEAR_VOQ_DESC_MODE_8197F(x) ((x) & (~BITS_VOQ_DESC_MODE_8197F)) +#define BIT_GET_VOQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8197F) & BIT_MASK_VOQ_DESC_MODE_8197F) +#define BIT_SET_VOQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_VOQ_DESC_MODE_8197F(x) | BIT_VOQ_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_VOQ_DESC_NUM_8197F 0 +#define BIT_MASK_VOQ_DESC_NUM_8197F 0xfff +#define BIT_VOQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8197F) << BIT_SHIFT_VOQ_DESC_NUM_8197F) +#define BITS_VOQ_DESC_NUM_8197F (BIT_MASK_VOQ_DESC_NUM_8197F << BIT_SHIFT_VOQ_DESC_NUM_8197F) +#define BIT_CLEAR_VOQ_DESC_NUM_8197F(x) ((x) & (~BITS_VOQ_DESC_NUM_8197F)) +#define BIT_GET_VOQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8197F) & BIT_MASK_VOQ_DESC_NUM_8197F) +#define BIT_SET_VOQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_VOQ_DESC_NUM_8197F(x) | BIT_VOQ_DESC_NUM_8197F(v)) + + +/* 2 REG_VIQ_TXBD_NUM_8197F */ +#define BIT_HCI_VIQ_FLAG_8197F BIT(14) + +#define BIT_SHIFT_VIQ_DESC_MODE_8197F 12 +#define BIT_MASK_VIQ_DESC_MODE_8197F 0x3 +#define BIT_VIQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8197F) << BIT_SHIFT_VIQ_DESC_MODE_8197F) +#define BITS_VIQ_DESC_MODE_8197F (BIT_MASK_VIQ_DESC_MODE_8197F << BIT_SHIFT_VIQ_DESC_MODE_8197F) +#define BIT_CLEAR_VIQ_DESC_MODE_8197F(x) ((x) & (~BITS_VIQ_DESC_MODE_8197F)) +#define BIT_GET_VIQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8197F) & BIT_MASK_VIQ_DESC_MODE_8197F) +#define BIT_SET_VIQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_VIQ_DESC_MODE_8197F(x) | BIT_VIQ_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_VIQ_DESC_NUM_8197F 0 +#define BIT_MASK_VIQ_DESC_NUM_8197F 0xfff +#define BIT_VIQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8197F) << BIT_SHIFT_VIQ_DESC_NUM_8197F) +#define BITS_VIQ_DESC_NUM_8197F (BIT_MASK_VIQ_DESC_NUM_8197F << BIT_SHIFT_VIQ_DESC_NUM_8197F) +#define BIT_CLEAR_VIQ_DESC_NUM_8197F(x) ((x) & (~BITS_VIQ_DESC_NUM_8197F)) +#define BIT_GET_VIQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8197F) & BIT_MASK_VIQ_DESC_NUM_8197F) +#define BIT_SET_VIQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_VIQ_DESC_NUM_8197F(x) | BIT_VIQ_DESC_NUM_8197F(v)) + + +/* 2 REG_BEQ_TXBD_NUM_8197F */ +#define BIT_HCI_BEQ_FLAG_8197F BIT(14) + +#define BIT_SHIFT_BEQ_DESC_MODE_8197F 12 +#define BIT_MASK_BEQ_DESC_MODE_8197F 0x3 +#define BIT_BEQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8197F) << BIT_SHIFT_BEQ_DESC_MODE_8197F) +#define BITS_BEQ_DESC_MODE_8197F (BIT_MASK_BEQ_DESC_MODE_8197F << BIT_SHIFT_BEQ_DESC_MODE_8197F) +#define BIT_CLEAR_BEQ_DESC_MODE_8197F(x) ((x) & (~BITS_BEQ_DESC_MODE_8197F)) +#define BIT_GET_BEQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8197F) & BIT_MASK_BEQ_DESC_MODE_8197F) +#define BIT_SET_BEQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_BEQ_DESC_MODE_8197F(x) | BIT_BEQ_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_BEQ_DESC_NUM_8197F 0 +#define BIT_MASK_BEQ_DESC_NUM_8197F 0xfff +#define BIT_BEQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8197F) << BIT_SHIFT_BEQ_DESC_NUM_8197F) +#define BITS_BEQ_DESC_NUM_8197F (BIT_MASK_BEQ_DESC_NUM_8197F << BIT_SHIFT_BEQ_DESC_NUM_8197F) +#define BIT_CLEAR_BEQ_DESC_NUM_8197F(x) ((x) & (~BITS_BEQ_DESC_NUM_8197F)) +#define BIT_GET_BEQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8197F) & BIT_MASK_BEQ_DESC_NUM_8197F) +#define BIT_SET_BEQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_BEQ_DESC_NUM_8197F(x) | BIT_BEQ_DESC_NUM_8197F(v)) + + +/* 2 REG_BKQ_TXBD_NUM_8197F */ +#define BIT_HCI_BKQ_FLAG_8197F BIT(14) + +#define BIT_SHIFT_BKQ_DESC_MODE_8197F 12 +#define BIT_MASK_BKQ_DESC_MODE_8197F 0x3 +#define BIT_BKQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8197F) << BIT_SHIFT_BKQ_DESC_MODE_8197F) +#define BITS_BKQ_DESC_MODE_8197F (BIT_MASK_BKQ_DESC_MODE_8197F << BIT_SHIFT_BKQ_DESC_MODE_8197F) +#define BIT_CLEAR_BKQ_DESC_MODE_8197F(x) ((x) & (~BITS_BKQ_DESC_MODE_8197F)) +#define BIT_GET_BKQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8197F) & BIT_MASK_BKQ_DESC_MODE_8197F) +#define BIT_SET_BKQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_BKQ_DESC_MODE_8197F(x) | BIT_BKQ_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_BKQ_DESC_NUM_8197F 0 +#define BIT_MASK_BKQ_DESC_NUM_8197F 0xfff +#define BIT_BKQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8197F) << BIT_SHIFT_BKQ_DESC_NUM_8197F) +#define BITS_BKQ_DESC_NUM_8197F (BIT_MASK_BKQ_DESC_NUM_8197F << BIT_SHIFT_BKQ_DESC_NUM_8197F) +#define BIT_CLEAR_BKQ_DESC_NUM_8197F(x) ((x) & (~BITS_BKQ_DESC_NUM_8197F)) +#define BIT_GET_BKQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8197F) & BIT_MASK_BKQ_DESC_NUM_8197F) +#define BIT_SET_BKQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_BKQ_DESC_NUM_8197F(x) | BIT_BKQ_DESC_NUM_8197F(v)) + + +/* 2 REG_HI0Q_TXBD_NUM_8197F */ +#define BIT_HI0Q_FLAG_8197F BIT(14) + +#define BIT_SHIFT_HI0Q_DESC_MODE_8197F 12 +#define BIT_MASK_HI0Q_DESC_MODE_8197F 0x3 +#define BIT_HI0Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8197F) << BIT_SHIFT_HI0Q_DESC_MODE_8197F) +#define BITS_HI0Q_DESC_MODE_8197F (BIT_MASK_HI0Q_DESC_MODE_8197F << BIT_SHIFT_HI0Q_DESC_MODE_8197F) +#define BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI0Q_DESC_MODE_8197F)) +#define BIT_GET_HI0Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8197F) & BIT_MASK_HI0Q_DESC_MODE_8197F) +#define BIT_SET_HI0Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) | BIT_HI0Q_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_HI0Q_DESC_NUM_8197F 0 +#define BIT_MASK_HI0Q_DESC_NUM_8197F 0xfff +#define BIT_HI0Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8197F) << BIT_SHIFT_HI0Q_DESC_NUM_8197F) +#define BITS_HI0Q_DESC_NUM_8197F (BIT_MASK_HI0Q_DESC_NUM_8197F << BIT_SHIFT_HI0Q_DESC_NUM_8197F) +#define BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI0Q_DESC_NUM_8197F)) +#define BIT_GET_HI0Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8197F) & BIT_MASK_HI0Q_DESC_NUM_8197F) +#define BIT_SET_HI0Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) | BIT_HI0Q_DESC_NUM_8197F(v)) + + +/* 2 REG_HI1Q_TXBD_NUM_8197F */ +#define BIT_HI1Q_FLAG_8197F BIT(14) + +#define BIT_SHIFT_HI1Q_DESC_MODE_8197F 12 +#define BIT_MASK_HI1Q_DESC_MODE_8197F 0x3 +#define BIT_HI1Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8197F) << BIT_SHIFT_HI1Q_DESC_MODE_8197F) +#define BITS_HI1Q_DESC_MODE_8197F (BIT_MASK_HI1Q_DESC_MODE_8197F << BIT_SHIFT_HI1Q_DESC_MODE_8197F) +#define BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI1Q_DESC_MODE_8197F)) +#define BIT_GET_HI1Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8197F) & BIT_MASK_HI1Q_DESC_MODE_8197F) +#define BIT_SET_HI1Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) | BIT_HI1Q_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_HI1Q_DESC_NUM_8197F 0 +#define BIT_MASK_HI1Q_DESC_NUM_8197F 0xfff +#define BIT_HI1Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8197F) << BIT_SHIFT_HI1Q_DESC_NUM_8197F) +#define BITS_HI1Q_DESC_NUM_8197F (BIT_MASK_HI1Q_DESC_NUM_8197F << BIT_SHIFT_HI1Q_DESC_NUM_8197F) +#define BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI1Q_DESC_NUM_8197F)) +#define BIT_GET_HI1Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8197F) & BIT_MASK_HI1Q_DESC_NUM_8197F) +#define BIT_SET_HI1Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) | BIT_HI1Q_DESC_NUM_8197F(v)) + + +/* 2 REG_HI2Q_TXBD_NUM_8197F */ +#define BIT_HI2Q_FLAG_8197F BIT(14) + +#define BIT_SHIFT_HI2Q_DESC_MODE_8197F 12 +#define BIT_MASK_HI2Q_DESC_MODE_8197F 0x3 +#define BIT_HI2Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8197F) << BIT_SHIFT_HI2Q_DESC_MODE_8197F) +#define BITS_HI2Q_DESC_MODE_8197F (BIT_MASK_HI2Q_DESC_MODE_8197F << BIT_SHIFT_HI2Q_DESC_MODE_8197F) +#define BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI2Q_DESC_MODE_8197F)) +#define BIT_GET_HI2Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8197F) & BIT_MASK_HI2Q_DESC_MODE_8197F) +#define BIT_SET_HI2Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) | BIT_HI2Q_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_HI2Q_DESC_NUM_8197F 0 +#define BIT_MASK_HI2Q_DESC_NUM_8197F 0xfff +#define BIT_HI2Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8197F) << BIT_SHIFT_HI2Q_DESC_NUM_8197F) +#define BITS_HI2Q_DESC_NUM_8197F (BIT_MASK_HI2Q_DESC_NUM_8197F << BIT_SHIFT_HI2Q_DESC_NUM_8197F) +#define BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI2Q_DESC_NUM_8197F)) +#define BIT_GET_HI2Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8197F) & BIT_MASK_HI2Q_DESC_NUM_8197F) +#define BIT_SET_HI2Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) | BIT_HI2Q_DESC_NUM_8197F(v)) + + +/* 2 REG_HI3Q_TXBD_NUM_8197F */ +#define BIT_HI3Q_FLAG_8197F BIT(14) + +#define BIT_SHIFT_HI3Q_DESC_MODE_8197F 12 +#define BIT_MASK_HI3Q_DESC_MODE_8197F 0x3 +#define BIT_HI3Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8197F) << BIT_SHIFT_HI3Q_DESC_MODE_8197F) +#define BITS_HI3Q_DESC_MODE_8197F (BIT_MASK_HI3Q_DESC_MODE_8197F << BIT_SHIFT_HI3Q_DESC_MODE_8197F) +#define BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI3Q_DESC_MODE_8197F)) +#define BIT_GET_HI3Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8197F) & BIT_MASK_HI3Q_DESC_MODE_8197F) +#define BIT_SET_HI3Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) | BIT_HI3Q_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_HI3Q_DESC_NUM_8197F 0 +#define BIT_MASK_HI3Q_DESC_NUM_8197F 0xfff +#define BIT_HI3Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8197F) << BIT_SHIFT_HI3Q_DESC_NUM_8197F) +#define BITS_HI3Q_DESC_NUM_8197F (BIT_MASK_HI3Q_DESC_NUM_8197F << BIT_SHIFT_HI3Q_DESC_NUM_8197F) +#define BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI3Q_DESC_NUM_8197F)) +#define BIT_GET_HI3Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8197F) & BIT_MASK_HI3Q_DESC_NUM_8197F) +#define BIT_SET_HI3Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) | BIT_HI3Q_DESC_NUM_8197F(v)) + + +/* 2 REG_HI4Q_TXBD_NUM_8197F */ +#define BIT_HI4Q_FLAG_8197F BIT(14) + +#define BIT_SHIFT_HI4Q_DESC_MODE_8197F 12 +#define BIT_MASK_HI4Q_DESC_MODE_8197F 0x3 +#define BIT_HI4Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8197F) << BIT_SHIFT_HI4Q_DESC_MODE_8197F) +#define BITS_HI4Q_DESC_MODE_8197F (BIT_MASK_HI4Q_DESC_MODE_8197F << BIT_SHIFT_HI4Q_DESC_MODE_8197F) +#define BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI4Q_DESC_MODE_8197F)) +#define BIT_GET_HI4Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8197F) & BIT_MASK_HI4Q_DESC_MODE_8197F) +#define BIT_SET_HI4Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) | BIT_HI4Q_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_HI4Q_DESC_NUM_8197F 0 +#define BIT_MASK_HI4Q_DESC_NUM_8197F 0xfff +#define BIT_HI4Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8197F) << BIT_SHIFT_HI4Q_DESC_NUM_8197F) +#define BITS_HI4Q_DESC_NUM_8197F (BIT_MASK_HI4Q_DESC_NUM_8197F << BIT_SHIFT_HI4Q_DESC_NUM_8197F) +#define BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI4Q_DESC_NUM_8197F)) +#define BIT_GET_HI4Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8197F) & BIT_MASK_HI4Q_DESC_NUM_8197F) +#define BIT_SET_HI4Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) | BIT_HI4Q_DESC_NUM_8197F(v)) + + +/* 2 REG_HI5Q_TXBD_NUM_8197F */ +#define BIT_HI5Q_FLAG_8197F BIT(14) + +#define BIT_SHIFT_HI5Q_DESC_MODE_8197F 12 +#define BIT_MASK_HI5Q_DESC_MODE_8197F 0x3 +#define BIT_HI5Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8197F) << BIT_SHIFT_HI5Q_DESC_MODE_8197F) +#define BITS_HI5Q_DESC_MODE_8197F (BIT_MASK_HI5Q_DESC_MODE_8197F << BIT_SHIFT_HI5Q_DESC_MODE_8197F) +#define BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI5Q_DESC_MODE_8197F)) +#define BIT_GET_HI5Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8197F) & BIT_MASK_HI5Q_DESC_MODE_8197F) +#define BIT_SET_HI5Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) | BIT_HI5Q_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_HI5Q_DESC_NUM_8197F 0 +#define BIT_MASK_HI5Q_DESC_NUM_8197F 0xfff +#define BIT_HI5Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8197F) << BIT_SHIFT_HI5Q_DESC_NUM_8197F) +#define BITS_HI5Q_DESC_NUM_8197F (BIT_MASK_HI5Q_DESC_NUM_8197F << BIT_SHIFT_HI5Q_DESC_NUM_8197F) +#define BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI5Q_DESC_NUM_8197F)) +#define BIT_GET_HI5Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8197F) & BIT_MASK_HI5Q_DESC_NUM_8197F) +#define BIT_SET_HI5Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) | BIT_HI5Q_DESC_NUM_8197F(v)) + + +/* 2 REG_HI6Q_TXBD_NUM_8197F */ +#define BIT_HI6Q_FLAG_8197F BIT(14) + +#define BIT_SHIFT_HI6Q_DESC_MODE_8197F 12 +#define BIT_MASK_HI6Q_DESC_MODE_8197F 0x3 +#define BIT_HI6Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8197F) << BIT_SHIFT_HI6Q_DESC_MODE_8197F) +#define BITS_HI6Q_DESC_MODE_8197F (BIT_MASK_HI6Q_DESC_MODE_8197F << BIT_SHIFT_HI6Q_DESC_MODE_8197F) +#define BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI6Q_DESC_MODE_8197F)) +#define BIT_GET_HI6Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8197F) & BIT_MASK_HI6Q_DESC_MODE_8197F) +#define BIT_SET_HI6Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) | BIT_HI6Q_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_HI6Q_DESC_NUM_8197F 0 +#define BIT_MASK_HI6Q_DESC_NUM_8197F 0xfff +#define BIT_HI6Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8197F) << BIT_SHIFT_HI6Q_DESC_NUM_8197F) +#define BITS_HI6Q_DESC_NUM_8197F (BIT_MASK_HI6Q_DESC_NUM_8197F << BIT_SHIFT_HI6Q_DESC_NUM_8197F) +#define BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI6Q_DESC_NUM_8197F)) +#define BIT_GET_HI6Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8197F) & BIT_MASK_HI6Q_DESC_NUM_8197F) +#define BIT_SET_HI6Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) | BIT_HI6Q_DESC_NUM_8197F(v)) + + +/* 2 REG_HI7Q_TXBD_NUM_8197F */ +#define BIT_HI7Q_FLAG_8197F BIT(14) + +#define BIT_SHIFT_HI7Q_DESC_MODE_8197F 12 +#define BIT_MASK_HI7Q_DESC_MODE_8197F 0x3 +#define BIT_HI7Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8197F) << BIT_SHIFT_HI7Q_DESC_MODE_8197F) +#define BITS_HI7Q_DESC_MODE_8197F (BIT_MASK_HI7Q_DESC_MODE_8197F << BIT_SHIFT_HI7Q_DESC_MODE_8197F) +#define BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI7Q_DESC_MODE_8197F)) +#define BIT_GET_HI7Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8197F) & BIT_MASK_HI7Q_DESC_MODE_8197F) +#define BIT_SET_HI7Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) | BIT_HI7Q_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_HI7Q_DESC_NUM_8197F 0 +#define BIT_MASK_HI7Q_DESC_NUM_8197F 0xfff +#define BIT_HI7Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8197F) << BIT_SHIFT_HI7Q_DESC_NUM_8197F) +#define BITS_HI7Q_DESC_NUM_8197F (BIT_MASK_HI7Q_DESC_NUM_8197F << BIT_SHIFT_HI7Q_DESC_NUM_8197F) +#define BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI7Q_DESC_NUM_8197F)) +#define BIT_GET_HI7Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8197F) & BIT_MASK_HI7Q_DESC_NUM_8197F) +#define BIT_SET_HI7Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) | BIT_HI7Q_DESC_NUM_8197F(v)) + + +/* 2 REG_TSFTIMER_HCI_8197F */ + +#define BIT_SHIFT_TSFT2_HCI_8197F 16 +#define BIT_MASK_TSFT2_HCI_8197F 0xffff +#define BIT_TSFT2_HCI_8197F(x) (((x) & BIT_MASK_TSFT2_HCI_8197F) << BIT_SHIFT_TSFT2_HCI_8197F) +#define BITS_TSFT2_HCI_8197F (BIT_MASK_TSFT2_HCI_8197F << BIT_SHIFT_TSFT2_HCI_8197F) +#define BIT_CLEAR_TSFT2_HCI_8197F(x) ((x) & (~BITS_TSFT2_HCI_8197F)) +#define BIT_GET_TSFT2_HCI_8197F(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8197F) & BIT_MASK_TSFT2_HCI_8197F) +#define BIT_SET_TSFT2_HCI_8197F(x, v) (BIT_CLEAR_TSFT2_HCI_8197F(x) | BIT_TSFT2_HCI_8197F(v)) + + +#define BIT_SHIFT_TSFT1_HCI_8197F 0 +#define BIT_MASK_TSFT1_HCI_8197F 0xffff +#define BIT_TSFT1_HCI_8197F(x) (((x) & BIT_MASK_TSFT1_HCI_8197F) << BIT_SHIFT_TSFT1_HCI_8197F) +#define BITS_TSFT1_HCI_8197F (BIT_MASK_TSFT1_HCI_8197F << BIT_SHIFT_TSFT1_HCI_8197F) +#define BIT_CLEAR_TSFT1_HCI_8197F(x) ((x) & (~BITS_TSFT1_HCI_8197F)) +#define BIT_GET_TSFT1_HCI_8197F(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8197F) & BIT_MASK_TSFT1_HCI_8197F) +#define BIT_SET_TSFT1_HCI_8197F(x, v) (BIT_CLEAR_TSFT1_HCI_8197F(x) | BIT_TSFT1_HCI_8197F(v)) + + +/* 2 REG_BD_RWPTR_CLR_8197F */ +#define BIT_CLR_HI7Q_HW_IDX_8197F BIT(29) +#define BIT_CLR_HI6Q_HW_IDX_8197F BIT(28) +#define BIT_CLR_HI5Q_HW_IDX_8197F BIT(27) +#define BIT_CLR_HI4Q_HW_IDX_8197F BIT(26) +#define BIT_CLR_HI3Q_HW_IDX_8197F BIT(25) +#define BIT_CLR_HI2Q_HW_IDX_8197F BIT(24) +#define BIT_CLR_HI1Q_HW_IDX_8197F BIT(23) +#define BIT_CLR_HI0Q_HW_IDX_8197F BIT(22) +#define BIT_CLR_BKQ_HW_IDX_8197F BIT(21) +#define BIT_CLR_BEQ_HW_IDX_8197F BIT(20) +#define BIT_CLR_VIQ_HW_IDX_8197F BIT(19) +#define BIT_CLR_VOQ_HW_IDX_8197F BIT(18) +#define BIT_CLR_MGQ_HW_IDX_8197F BIT(17) +#define BIT_CLR_RXQ_HW_IDX_8197F BIT(16) +#define BIT_CLR_HI7Q_HOST_IDX_8197F BIT(13) +#define BIT_CLR_HI6Q_HOST_IDX_8197F BIT(12) +#define BIT_CLR_HI5Q_HOST_IDX_8197F BIT(11) +#define BIT_CLR_HI4Q_HOST_IDX_8197F BIT(10) +#define BIT_CLR_HI3Q_HOST_IDX_8197F BIT(9) +#define BIT_CLR_HI2Q_HOST_IDX_8197F BIT(8) +#define BIT_CLR_HI1Q_HOST_IDX_8197F BIT(7) +#define BIT_CLR_HI0Q_HOST_IDX_8197F BIT(6) +#define BIT_CLR_BKQ_HOST_IDX_8197F BIT(5) +#define BIT_CLR_BEQ_HOST_IDX_8197F BIT(4) +#define BIT_CLR_VIQ_HOST_IDX_8197F BIT(3) +#define BIT_CLR_VOQ_HOST_IDX_8197F BIT(2) +#define BIT_CLR_MGQ_HOST_IDX_8197F BIT(1) +#define BIT_CLR_RXQ_HOST_IDX_8197F BIT(0) + +/* 2 REG_VOQ_TXBD_IDX_8197F */ + +#define BIT_SHIFT_VOQ_HW_IDX_8197F 16 +#define BIT_MASK_VOQ_HW_IDX_8197F 0xfff +#define BIT_VOQ_HW_IDX_8197F(x) (((x) & BIT_MASK_VOQ_HW_IDX_8197F) << BIT_SHIFT_VOQ_HW_IDX_8197F) +#define BITS_VOQ_HW_IDX_8197F (BIT_MASK_VOQ_HW_IDX_8197F << BIT_SHIFT_VOQ_HW_IDX_8197F) +#define BIT_CLEAR_VOQ_HW_IDX_8197F(x) ((x) & (~BITS_VOQ_HW_IDX_8197F)) +#define BIT_GET_VOQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8197F) & BIT_MASK_VOQ_HW_IDX_8197F) +#define BIT_SET_VOQ_HW_IDX_8197F(x, v) (BIT_CLEAR_VOQ_HW_IDX_8197F(x) | BIT_VOQ_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_VOQ_HOST_IDX_8197F 0 +#define BIT_MASK_VOQ_HOST_IDX_8197F 0xfff +#define BIT_VOQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8197F) << BIT_SHIFT_VOQ_HOST_IDX_8197F) +#define BITS_VOQ_HOST_IDX_8197F (BIT_MASK_VOQ_HOST_IDX_8197F << BIT_SHIFT_VOQ_HOST_IDX_8197F) +#define BIT_CLEAR_VOQ_HOST_IDX_8197F(x) ((x) & (~BITS_VOQ_HOST_IDX_8197F)) +#define BIT_GET_VOQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8197F) & BIT_MASK_VOQ_HOST_IDX_8197F) +#define BIT_SET_VOQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_VOQ_HOST_IDX_8197F(x) | BIT_VOQ_HOST_IDX_8197F(v)) + + +/* 2 REG_VIQ_TXBD_IDX_8197F */ + +#define BIT_SHIFT_VIQ_HW_IDX_8197F 16 +#define BIT_MASK_VIQ_HW_IDX_8197F 0xfff +#define BIT_VIQ_HW_IDX_8197F(x) (((x) & BIT_MASK_VIQ_HW_IDX_8197F) << BIT_SHIFT_VIQ_HW_IDX_8197F) +#define BITS_VIQ_HW_IDX_8197F (BIT_MASK_VIQ_HW_IDX_8197F << BIT_SHIFT_VIQ_HW_IDX_8197F) +#define BIT_CLEAR_VIQ_HW_IDX_8197F(x) ((x) & (~BITS_VIQ_HW_IDX_8197F)) +#define BIT_GET_VIQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8197F) & BIT_MASK_VIQ_HW_IDX_8197F) +#define BIT_SET_VIQ_HW_IDX_8197F(x, v) (BIT_CLEAR_VIQ_HW_IDX_8197F(x) | BIT_VIQ_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_VIQ_HOST_IDX_8197F 0 +#define BIT_MASK_VIQ_HOST_IDX_8197F 0xfff +#define BIT_VIQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8197F) << BIT_SHIFT_VIQ_HOST_IDX_8197F) +#define BITS_VIQ_HOST_IDX_8197F (BIT_MASK_VIQ_HOST_IDX_8197F << BIT_SHIFT_VIQ_HOST_IDX_8197F) +#define BIT_CLEAR_VIQ_HOST_IDX_8197F(x) ((x) & (~BITS_VIQ_HOST_IDX_8197F)) +#define BIT_GET_VIQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8197F) & BIT_MASK_VIQ_HOST_IDX_8197F) +#define BIT_SET_VIQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_VIQ_HOST_IDX_8197F(x) | BIT_VIQ_HOST_IDX_8197F(v)) + + +/* 2 REG_BEQ_TXBD_IDX_8197F */ + +#define BIT_SHIFT_BEQ_HW_IDX_8197F 16 +#define BIT_MASK_BEQ_HW_IDX_8197F 0xfff +#define BIT_BEQ_HW_IDX_8197F(x) (((x) & BIT_MASK_BEQ_HW_IDX_8197F) << BIT_SHIFT_BEQ_HW_IDX_8197F) +#define BITS_BEQ_HW_IDX_8197F (BIT_MASK_BEQ_HW_IDX_8197F << BIT_SHIFT_BEQ_HW_IDX_8197F) +#define BIT_CLEAR_BEQ_HW_IDX_8197F(x) ((x) & (~BITS_BEQ_HW_IDX_8197F)) +#define BIT_GET_BEQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8197F) & BIT_MASK_BEQ_HW_IDX_8197F) +#define BIT_SET_BEQ_HW_IDX_8197F(x, v) (BIT_CLEAR_BEQ_HW_IDX_8197F(x) | BIT_BEQ_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_BEQ_HOST_IDX_8197F 0 +#define BIT_MASK_BEQ_HOST_IDX_8197F 0xfff +#define BIT_BEQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8197F) << BIT_SHIFT_BEQ_HOST_IDX_8197F) +#define BITS_BEQ_HOST_IDX_8197F (BIT_MASK_BEQ_HOST_IDX_8197F << BIT_SHIFT_BEQ_HOST_IDX_8197F) +#define BIT_CLEAR_BEQ_HOST_IDX_8197F(x) ((x) & (~BITS_BEQ_HOST_IDX_8197F)) +#define BIT_GET_BEQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8197F) & BIT_MASK_BEQ_HOST_IDX_8197F) +#define BIT_SET_BEQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_BEQ_HOST_IDX_8197F(x) | BIT_BEQ_HOST_IDX_8197F(v)) + + +/* 2 REG_BKQ_TXBD_IDX_8197F */ + +#define BIT_SHIFT_BKQ_HW_IDX_8197F 16 +#define BIT_MASK_BKQ_HW_IDX_8197F 0xfff +#define BIT_BKQ_HW_IDX_8197F(x) (((x) & BIT_MASK_BKQ_HW_IDX_8197F) << BIT_SHIFT_BKQ_HW_IDX_8197F) +#define BITS_BKQ_HW_IDX_8197F (BIT_MASK_BKQ_HW_IDX_8197F << BIT_SHIFT_BKQ_HW_IDX_8197F) +#define BIT_CLEAR_BKQ_HW_IDX_8197F(x) ((x) & (~BITS_BKQ_HW_IDX_8197F)) +#define BIT_GET_BKQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8197F) & BIT_MASK_BKQ_HW_IDX_8197F) +#define BIT_SET_BKQ_HW_IDX_8197F(x, v) (BIT_CLEAR_BKQ_HW_IDX_8197F(x) | BIT_BKQ_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_BKQ_HOST_IDX_8197F 0 +#define BIT_MASK_BKQ_HOST_IDX_8197F 0xfff +#define BIT_BKQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8197F) << BIT_SHIFT_BKQ_HOST_IDX_8197F) +#define BITS_BKQ_HOST_IDX_8197F (BIT_MASK_BKQ_HOST_IDX_8197F << BIT_SHIFT_BKQ_HOST_IDX_8197F) +#define BIT_CLEAR_BKQ_HOST_IDX_8197F(x) ((x) & (~BITS_BKQ_HOST_IDX_8197F)) +#define BIT_GET_BKQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8197F) & BIT_MASK_BKQ_HOST_IDX_8197F) +#define BIT_SET_BKQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_BKQ_HOST_IDX_8197F(x) | BIT_BKQ_HOST_IDX_8197F(v)) + + +/* 2 REG_MGQ_TXBD_IDX_8197F */ + +#define BIT_SHIFT_MGQ_HW_IDX_8197F 16 +#define BIT_MASK_MGQ_HW_IDX_8197F 0xfff +#define BIT_MGQ_HW_IDX_8197F(x) (((x) & BIT_MASK_MGQ_HW_IDX_8197F) << BIT_SHIFT_MGQ_HW_IDX_8197F) +#define BITS_MGQ_HW_IDX_8197F (BIT_MASK_MGQ_HW_IDX_8197F << BIT_SHIFT_MGQ_HW_IDX_8197F) +#define BIT_CLEAR_MGQ_HW_IDX_8197F(x) ((x) & (~BITS_MGQ_HW_IDX_8197F)) +#define BIT_GET_MGQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8197F) & BIT_MASK_MGQ_HW_IDX_8197F) +#define BIT_SET_MGQ_HW_IDX_8197F(x, v) (BIT_CLEAR_MGQ_HW_IDX_8197F(x) | BIT_MGQ_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_MGQ_HOST_IDX_8197F 0 +#define BIT_MASK_MGQ_HOST_IDX_8197F 0xfff +#define BIT_MGQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8197F) << BIT_SHIFT_MGQ_HOST_IDX_8197F) +#define BITS_MGQ_HOST_IDX_8197F (BIT_MASK_MGQ_HOST_IDX_8197F << BIT_SHIFT_MGQ_HOST_IDX_8197F) +#define BIT_CLEAR_MGQ_HOST_IDX_8197F(x) ((x) & (~BITS_MGQ_HOST_IDX_8197F)) +#define BIT_GET_MGQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8197F) & BIT_MASK_MGQ_HOST_IDX_8197F) +#define BIT_SET_MGQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_MGQ_HOST_IDX_8197F(x) | BIT_MGQ_HOST_IDX_8197F(v)) + + +/* 2 REG_RXQ_RXBD_IDX_8197F */ + +#define BIT_SHIFT_RXQ_HW_IDX_8197F 16 +#define BIT_MASK_RXQ_HW_IDX_8197F 0xfff +#define BIT_RXQ_HW_IDX_8197F(x) (((x) & BIT_MASK_RXQ_HW_IDX_8197F) << BIT_SHIFT_RXQ_HW_IDX_8197F) +#define BITS_RXQ_HW_IDX_8197F (BIT_MASK_RXQ_HW_IDX_8197F << BIT_SHIFT_RXQ_HW_IDX_8197F) +#define BIT_CLEAR_RXQ_HW_IDX_8197F(x) ((x) & (~BITS_RXQ_HW_IDX_8197F)) +#define BIT_GET_RXQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8197F) & BIT_MASK_RXQ_HW_IDX_8197F) +#define BIT_SET_RXQ_HW_IDX_8197F(x, v) (BIT_CLEAR_RXQ_HW_IDX_8197F(x) | BIT_RXQ_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_RXQ_HOST_IDX_8197F 0 +#define BIT_MASK_RXQ_HOST_IDX_8197F 0xfff +#define BIT_RXQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8197F) << BIT_SHIFT_RXQ_HOST_IDX_8197F) +#define BITS_RXQ_HOST_IDX_8197F (BIT_MASK_RXQ_HOST_IDX_8197F << BIT_SHIFT_RXQ_HOST_IDX_8197F) +#define BIT_CLEAR_RXQ_HOST_IDX_8197F(x) ((x) & (~BITS_RXQ_HOST_IDX_8197F)) +#define BIT_GET_RXQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8197F) & BIT_MASK_RXQ_HOST_IDX_8197F) +#define BIT_SET_RXQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_RXQ_HOST_IDX_8197F(x) | BIT_RXQ_HOST_IDX_8197F(v)) + + +/* 2 REG_HI0Q_TXBD_IDX_8197F */ + +#define BIT_SHIFT_HI0Q_HW_IDX_8197F 16 +#define BIT_MASK_HI0Q_HW_IDX_8197F 0xfff +#define BIT_HI0Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8197F) << BIT_SHIFT_HI0Q_HW_IDX_8197F) +#define BITS_HI0Q_HW_IDX_8197F (BIT_MASK_HI0Q_HW_IDX_8197F << BIT_SHIFT_HI0Q_HW_IDX_8197F) +#define BIT_CLEAR_HI0Q_HW_IDX_8197F(x) ((x) & (~BITS_HI0Q_HW_IDX_8197F)) +#define BIT_GET_HI0Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8197F) & BIT_MASK_HI0Q_HW_IDX_8197F) +#define BIT_SET_HI0Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI0Q_HW_IDX_8197F(x) | BIT_HI0Q_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_HI0Q_HOST_IDX_8197F 0 +#define BIT_MASK_HI0Q_HOST_IDX_8197F 0xfff +#define BIT_HI0Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8197F) << BIT_SHIFT_HI0Q_HOST_IDX_8197F) +#define BITS_HI0Q_HOST_IDX_8197F (BIT_MASK_HI0Q_HOST_IDX_8197F << BIT_SHIFT_HI0Q_HOST_IDX_8197F) +#define BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI0Q_HOST_IDX_8197F)) +#define BIT_GET_HI0Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8197F) & BIT_MASK_HI0Q_HOST_IDX_8197F) +#define BIT_SET_HI0Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) | BIT_HI0Q_HOST_IDX_8197F(v)) + + +/* 2 REG_HI1Q_TXBD_IDX_8197F */ + +#define BIT_SHIFT_HI1Q_HW_IDX_8197F 16 +#define BIT_MASK_HI1Q_HW_IDX_8197F 0xfff +#define BIT_HI1Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8197F) << BIT_SHIFT_HI1Q_HW_IDX_8197F) +#define BITS_HI1Q_HW_IDX_8197F (BIT_MASK_HI1Q_HW_IDX_8197F << BIT_SHIFT_HI1Q_HW_IDX_8197F) +#define BIT_CLEAR_HI1Q_HW_IDX_8197F(x) ((x) & (~BITS_HI1Q_HW_IDX_8197F)) +#define BIT_GET_HI1Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8197F) & BIT_MASK_HI1Q_HW_IDX_8197F) +#define BIT_SET_HI1Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI1Q_HW_IDX_8197F(x) | BIT_HI1Q_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_HI1Q_HOST_IDX_8197F 0 +#define BIT_MASK_HI1Q_HOST_IDX_8197F 0xfff +#define BIT_HI1Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8197F) << BIT_SHIFT_HI1Q_HOST_IDX_8197F) +#define BITS_HI1Q_HOST_IDX_8197F (BIT_MASK_HI1Q_HOST_IDX_8197F << BIT_SHIFT_HI1Q_HOST_IDX_8197F) +#define BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI1Q_HOST_IDX_8197F)) +#define BIT_GET_HI1Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8197F) & BIT_MASK_HI1Q_HOST_IDX_8197F) +#define BIT_SET_HI1Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) | BIT_HI1Q_HOST_IDX_8197F(v)) + + +/* 2 REG_HI2Q_TXBD_IDX_8197F */ + +#define BIT_SHIFT_HI2Q_HW_IDX_8197F 16 +#define BIT_MASK_HI2Q_HW_IDX_8197F 0xfff +#define BIT_HI2Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8197F) << BIT_SHIFT_HI2Q_HW_IDX_8197F) +#define BITS_HI2Q_HW_IDX_8197F (BIT_MASK_HI2Q_HW_IDX_8197F << BIT_SHIFT_HI2Q_HW_IDX_8197F) +#define BIT_CLEAR_HI2Q_HW_IDX_8197F(x) ((x) & (~BITS_HI2Q_HW_IDX_8197F)) +#define BIT_GET_HI2Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8197F) & BIT_MASK_HI2Q_HW_IDX_8197F) +#define BIT_SET_HI2Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI2Q_HW_IDX_8197F(x) | BIT_HI2Q_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_HI2Q_HOST_IDX_8197F 0 +#define BIT_MASK_HI2Q_HOST_IDX_8197F 0xfff +#define BIT_HI2Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8197F) << BIT_SHIFT_HI2Q_HOST_IDX_8197F) +#define BITS_HI2Q_HOST_IDX_8197F (BIT_MASK_HI2Q_HOST_IDX_8197F << BIT_SHIFT_HI2Q_HOST_IDX_8197F) +#define BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI2Q_HOST_IDX_8197F)) +#define BIT_GET_HI2Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8197F) & BIT_MASK_HI2Q_HOST_IDX_8197F) +#define BIT_SET_HI2Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) | BIT_HI2Q_HOST_IDX_8197F(v)) + + +/* 2 REG_HI3Q_TXBD_IDX_8197F */ + +#define BIT_SHIFT_HI3Q_HW_IDX_8197F 16 +#define BIT_MASK_HI3Q_HW_IDX_8197F 0xfff +#define BIT_HI3Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8197F) << BIT_SHIFT_HI3Q_HW_IDX_8197F) +#define BITS_HI3Q_HW_IDX_8197F (BIT_MASK_HI3Q_HW_IDX_8197F << BIT_SHIFT_HI3Q_HW_IDX_8197F) +#define BIT_CLEAR_HI3Q_HW_IDX_8197F(x) ((x) & (~BITS_HI3Q_HW_IDX_8197F)) +#define BIT_GET_HI3Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8197F) & BIT_MASK_HI3Q_HW_IDX_8197F) +#define BIT_SET_HI3Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI3Q_HW_IDX_8197F(x) | BIT_HI3Q_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_HI3Q_HOST_IDX_8197F 0 +#define BIT_MASK_HI3Q_HOST_IDX_8197F 0xfff +#define BIT_HI3Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8197F) << BIT_SHIFT_HI3Q_HOST_IDX_8197F) +#define BITS_HI3Q_HOST_IDX_8197F (BIT_MASK_HI3Q_HOST_IDX_8197F << BIT_SHIFT_HI3Q_HOST_IDX_8197F) +#define BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI3Q_HOST_IDX_8197F)) +#define BIT_GET_HI3Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8197F) & BIT_MASK_HI3Q_HOST_IDX_8197F) +#define BIT_SET_HI3Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) | BIT_HI3Q_HOST_IDX_8197F(v)) + + +/* 2 REG_HI4Q_TXBD_IDX_8197F */ + +#define BIT_SHIFT_HI4Q_HW_IDX_8197F 16 +#define BIT_MASK_HI4Q_HW_IDX_8197F 0xfff +#define BIT_HI4Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8197F) << BIT_SHIFT_HI4Q_HW_IDX_8197F) +#define BITS_HI4Q_HW_IDX_8197F (BIT_MASK_HI4Q_HW_IDX_8197F << BIT_SHIFT_HI4Q_HW_IDX_8197F) +#define BIT_CLEAR_HI4Q_HW_IDX_8197F(x) ((x) & (~BITS_HI4Q_HW_IDX_8197F)) +#define BIT_GET_HI4Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8197F) & BIT_MASK_HI4Q_HW_IDX_8197F) +#define BIT_SET_HI4Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI4Q_HW_IDX_8197F(x) | BIT_HI4Q_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_HI4Q_HOST_IDX_8197F 0 +#define BIT_MASK_HI4Q_HOST_IDX_8197F 0xfff +#define BIT_HI4Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8197F) << BIT_SHIFT_HI4Q_HOST_IDX_8197F) +#define BITS_HI4Q_HOST_IDX_8197F (BIT_MASK_HI4Q_HOST_IDX_8197F << BIT_SHIFT_HI4Q_HOST_IDX_8197F) +#define BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI4Q_HOST_IDX_8197F)) +#define BIT_GET_HI4Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8197F) & BIT_MASK_HI4Q_HOST_IDX_8197F) +#define BIT_SET_HI4Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) | BIT_HI4Q_HOST_IDX_8197F(v)) + + +/* 2 REG_HI5Q_TXBD_IDX_8197F */ + +#define BIT_SHIFT_HI5Q_HW_IDX_8197F 16 +#define BIT_MASK_HI5Q_HW_IDX_8197F 0xfff +#define BIT_HI5Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8197F) << BIT_SHIFT_HI5Q_HW_IDX_8197F) +#define BITS_HI5Q_HW_IDX_8197F (BIT_MASK_HI5Q_HW_IDX_8197F << BIT_SHIFT_HI5Q_HW_IDX_8197F) +#define BIT_CLEAR_HI5Q_HW_IDX_8197F(x) ((x) & (~BITS_HI5Q_HW_IDX_8197F)) +#define BIT_GET_HI5Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8197F) & BIT_MASK_HI5Q_HW_IDX_8197F) +#define BIT_SET_HI5Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI5Q_HW_IDX_8197F(x) | BIT_HI5Q_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_HI5Q_HOST_IDX_8197F 0 +#define BIT_MASK_HI5Q_HOST_IDX_8197F 0xfff +#define BIT_HI5Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8197F) << BIT_SHIFT_HI5Q_HOST_IDX_8197F) +#define BITS_HI5Q_HOST_IDX_8197F (BIT_MASK_HI5Q_HOST_IDX_8197F << BIT_SHIFT_HI5Q_HOST_IDX_8197F) +#define BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI5Q_HOST_IDX_8197F)) +#define BIT_GET_HI5Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8197F) & BIT_MASK_HI5Q_HOST_IDX_8197F) +#define BIT_SET_HI5Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) | BIT_HI5Q_HOST_IDX_8197F(v)) + + +/* 2 REG_HI6Q_TXBD_IDX_8197F */ + +#define BIT_SHIFT_HI6Q_HW_IDX_8197F 16 +#define BIT_MASK_HI6Q_HW_IDX_8197F 0xfff +#define BIT_HI6Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8197F) << BIT_SHIFT_HI6Q_HW_IDX_8197F) +#define BITS_HI6Q_HW_IDX_8197F (BIT_MASK_HI6Q_HW_IDX_8197F << BIT_SHIFT_HI6Q_HW_IDX_8197F) +#define BIT_CLEAR_HI6Q_HW_IDX_8197F(x) ((x) & (~BITS_HI6Q_HW_IDX_8197F)) +#define BIT_GET_HI6Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8197F) & BIT_MASK_HI6Q_HW_IDX_8197F) +#define BIT_SET_HI6Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI6Q_HW_IDX_8197F(x) | BIT_HI6Q_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_HI6Q_HOST_IDX_8197F 0 +#define BIT_MASK_HI6Q_HOST_IDX_8197F 0xfff +#define BIT_HI6Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8197F) << BIT_SHIFT_HI6Q_HOST_IDX_8197F) +#define BITS_HI6Q_HOST_IDX_8197F (BIT_MASK_HI6Q_HOST_IDX_8197F << BIT_SHIFT_HI6Q_HOST_IDX_8197F) +#define BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI6Q_HOST_IDX_8197F)) +#define BIT_GET_HI6Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8197F) & BIT_MASK_HI6Q_HOST_IDX_8197F) +#define BIT_SET_HI6Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) | BIT_HI6Q_HOST_IDX_8197F(v)) + + +/* 2 REG_HI7Q_TXBD_IDX_8197F */ + +#define BIT_SHIFT_HI7Q_HW_IDX_8197F 16 +#define BIT_MASK_HI7Q_HW_IDX_8197F 0xfff +#define BIT_HI7Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8197F) << BIT_SHIFT_HI7Q_HW_IDX_8197F) +#define BITS_HI7Q_HW_IDX_8197F (BIT_MASK_HI7Q_HW_IDX_8197F << BIT_SHIFT_HI7Q_HW_IDX_8197F) +#define BIT_CLEAR_HI7Q_HW_IDX_8197F(x) ((x) & (~BITS_HI7Q_HW_IDX_8197F)) +#define BIT_GET_HI7Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8197F) & BIT_MASK_HI7Q_HW_IDX_8197F) +#define BIT_SET_HI7Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI7Q_HW_IDX_8197F(x) | BIT_HI7Q_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_HI7Q_HOST_IDX_8197F 0 +#define BIT_MASK_HI7Q_HOST_IDX_8197F 0xfff +#define BIT_HI7Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8197F) << BIT_SHIFT_HI7Q_HOST_IDX_8197F) +#define BITS_HI7Q_HOST_IDX_8197F (BIT_MASK_HI7Q_HOST_IDX_8197F << BIT_SHIFT_HI7Q_HOST_IDX_8197F) +#define BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI7Q_HOST_IDX_8197F)) +#define BIT_GET_HI7Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8197F) & BIT_MASK_HI7Q_HOST_IDX_8197F) +#define BIT_SET_HI7Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) | BIT_HI7Q_HOST_IDX_8197F(v)) + + +/* 2 REG_DBG_SEL_V1_8197F */ + +#define BIT_SHIFT_DBG_SEL_8197F 0 +#define BIT_MASK_DBG_SEL_8197F 0xff +#define BIT_DBG_SEL_8197F(x) (((x) & BIT_MASK_DBG_SEL_8197F) << BIT_SHIFT_DBG_SEL_8197F) +#define BITS_DBG_SEL_8197F (BIT_MASK_DBG_SEL_8197F << BIT_SHIFT_DBG_SEL_8197F) +#define BIT_CLEAR_DBG_SEL_8197F(x) ((x) & (~BITS_DBG_SEL_8197F)) +#define BIT_GET_DBG_SEL_8197F(x) (((x) >> BIT_SHIFT_DBG_SEL_8197F) & BIT_MASK_DBG_SEL_8197F) +#define BIT_SET_DBG_SEL_8197F(x, v) (BIT_CLEAR_DBG_SEL_8197F(x) | BIT_DBG_SEL_8197F(v)) + + +/* 2 REG_HCI_HRPWM1_V1_8197F */ + +#define BIT_SHIFT_HCI_HRPWM_8197F 0 +#define BIT_MASK_HCI_HRPWM_8197F 0xff +#define BIT_HCI_HRPWM_8197F(x) (((x) & BIT_MASK_HCI_HRPWM_8197F) << BIT_SHIFT_HCI_HRPWM_8197F) +#define BITS_HCI_HRPWM_8197F (BIT_MASK_HCI_HRPWM_8197F << BIT_SHIFT_HCI_HRPWM_8197F) +#define BIT_CLEAR_HCI_HRPWM_8197F(x) ((x) & (~BITS_HCI_HRPWM_8197F)) +#define BIT_GET_HCI_HRPWM_8197F(x) (((x) >> BIT_SHIFT_HCI_HRPWM_8197F) & BIT_MASK_HCI_HRPWM_8197F) +#define BIT_SET_HCI_HRPWM_8197F(x, v) (BIT_CLEAR_HCI_HRPWM_8197F(x) | BIT_HCI_HRPWM_8197F(v)) + + +/* 2 REG_HCI_HCPWM1_V1_8197F */ + +#define BIT_SHIFT_HCI_HCPWM_8197F 0 +#define BIT_MASK_HCI_HCPWM_8197F 0xff +#define BIT_HCI_HCPWM_8197F(x) (((x) & BIT_MASK_HCI_HCPWM_8197F) << BIT_SHIFT_HCI_HCPWM_8197F) +#define BITS_HCI_HCPWM_8197F (BIT_MASK_HCI_HCPWM_8197F << BIT_SHIFT_HCI_HCPWM_8197F) +#define BIT_CLEAR_HCI_HCPWM_8197F(x) ((x) & (~BITS_HCI_HCPWM_8197F)) +#define BIT_GET_HCI_HCPWM_8197F(x) (((x) >> BIT_SHIFT_HCI_HCPWM_8197F) & BIT_MASK_HCI_HCPWM_8197F) +#define BIT_SET_HCI_HCPWM_8197F(x, v) (BIT_CLEAR_HCI_HCPWM_8197F(x) | BIT_HCI_HCPWM_8197F(v)) + + +/* 2 REG_HCI_CTRL2_8197F */ +#define BIT_DIS_TXDMA_PRE_8197F BIT(7) +#define BIT_DIS_RXDMA_PRE_8197F BIT(6) + +#define BIT_SHIFT_HPS_CLKR_HCI_8197F 4 +#define BIT_MASK_HPS_CLKR_HCI_8197F 0x3 +#define BIT_HPS_CLKR_HCI_8197F(x) (((x) & BIT_MASK_HPS_CLKR_HCI_8197F) << BIT_SHIFT_HPS_CLKR_HCI_8197F) +#define BITS_HPS_CLKR_HCI_8197F (BIT_MASK_HPS_CLKR_HCI_8197F << BIT_SHIFT_HPS_CLKR_HCI_8197F) +#define BIT_CLEAR_HPS_CLKR_HCI_8197F(x) ((x) & (~BITS_HPS_CLKR_HCI_8197F)) +#define BIT_GET_HPS_CLKR_HCI_8197F(x) (((x) >> BIT_SHIFT_HPS_CLKR_HCI_8197F) & BIT_MASK_HPS_CLKR_HCI_8197F) +#define BIT_SET_HPS_CLKR_HCI_8197F(x, v) (BIT_CLEAR_HPS_CLKR_HCI_8197F(x) | BIT_HPS_CLKR_HCI_8197F(v)) + +#define BIT_HCI_INT_8197F BIT(3) +#define BIT_TXFLAG_EXIT_L1_EN_8197F BIT(2) +#define BIT_EN_RXDMA_ALIGN_V1_8197F BIT(1) +#define BIT_EN_TXDMA_ALIGN_V1_8197F BIT(0) + +/* 2 REG_HCI_HRPWM2_V1_8197F */ + +#define BIT_SHIFT_HCI_HRPWM2_8197F 0 +#define BIT_MASK_HCI_HRPWM2_8197F 0xffff +#define BIT_HCI_HRPWM2_8197F(x) (((x) & BIT_MASK_HCI_HRPWM2_8197F) << BIT_SHIFT_HCI_HRPWM2_8197F) +#define BITS_HCI_HRPWM2_8197F (BIT_MASK_HCI_HRPWM2_8197F << BIT_SHIFT_HCI_HRPWM2_8197F) +#define BIT_CLEAR_HCI_HRPWM2_8197F(x) ((x) & (~BITS_HCI_HRPWM2_8197F)) +#define BIT_GET_HCI_HRPWM2_8197F(x) (((x) >> BIT_SHIFT_HCI_HRPWM2_8197F) & BIT_MASK_HCI_HRPWM2_8197F) +#define BIT_SET_HCI_HRPWM2_8197F(x, v) (BIT_CLEAR_HCI_HRPWM2_8197F(x) | BIT_HCI_HRPWM2_8197F(v)) + + +/* 2 REG_HCI_HCPWM2_V1_8197F */ + +#define BIT_SHIFT_HCI_HCPWM2_8197F 0 +#define BIT_MASK_HCI_HCPWM2_8197F 0xffff +#define BIT_HCI_HCPWM2_8197F(x) (((x) & BIT_MASK_HCI_HCPWM2_8197F) << BIT_SHIFT_HCI_HCPWM2_8197F) +#define BITS_HCI_HCPWM2_8197F (BIT_MASK_HCI_HCPWM2_8197F << BIT_SHIFT_HCI_HCPWM2_8197F) +#define BIT_CLEAR_HCI_HCPWM2_8197F(x) ((x) & (~BITS_HCI_HCPWM2_8197F)) +#define BIT_GET_HCI_HCPWM2_8197F(x) (((x) >> BIT_SHIFT_HCI_HCPWM2_8197F) & BIT_MASK_HCI_HCPWM2_8197F) +#define BIT_SET_HCI_HCPWM2_8197F(x, v) (BIT_CLEAR_HCI_HCPWM2_8197F(x) | BIT_HCI_HCPWM2_8197F(v)) + + +/* 2 REG_HCI_H2C_MSG_V1_8197F */ + +#define BIT_SHIFT_DRV2FW_INFO_8197F 0 +#define BIT_MASK_DRV2FW_INFO_8197F 0xffffffffL +#define BIT_DRV2FW_INFO_8197F(x) (((x) & BIT_MASK_DRV2FW_INFO_8197F) << BIT_SHIFT_DRV2FW_INFO_8197F) +#define BITS_DRV2FW_INFO_8197F (BIT_MASK_DRV2FW_INFO_8197F << BIT_SHIFT_DRV2FW_INFO_8197F) +#define BIT_CLEAR_DRV2FW_INFO_8197F(x) ((x) & (~BITS_DRV2FW_INFO_8197F)) +#define BIT_GET_DRV2FW_INFO_8197F(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8197F) & BIT_MASK_DRV2FW_INFO_8197F) +#define BIT_SET_DRV2FW_INFO_8197F(x, v) (BIT_CLEAR_DRV2FW_INFO_8197F(x) | BIT_DRV2FW_INFO_8197F(v)) + + +/* 2 REG_HCI_C2H_MSG_V1_8197F */ + +#define BIT_SHIFT_HCI_C2H_MSG_8197F 0 +#define BIT_MASK_HCI_C2H_MSG_8197F 0xffffffffL +#define BIT_HCI_C2H_MSG_8197F(x) (((x) & BIT_MASK_HCI_C2H_MSG_8197F) << BIT_SHIFT_HCI_C2H_MSG_8197F) +#define BITS_HCI_C2H_MSG_8197F (BIT_MASK_HCI_C2H_MSG_8197F << BIT_SHIFT_HCI_C2H_MSG_8197F) +#define BIT_CLEAR_HCI_C2H_MSG_8197F(x) ((x) & (~BITS_HCI_C2H_MSG_8197F)) +#define BIT_GET_HCI_C2H_MSG_8197F(x) (((x) >> BIT_SHIFT_HCI_C2H_MSG_8197F) & BIT_MASK_HCI_C2H_MSG_8197F) +#define BIT_SET_HCI_C2H_MSG_8197F(x, v) (BIT_CLEAR_HCI_C2H_MSG_8197F(x) | BIT_HCI_C2H_MSG_8197F(v)) + + +/* 2 REG_DBI_WDATA_V1_8197F */ + +#define BIT_SHIFT_DBI_WDATA_8197F 0 +#define BIT_MASK_DBI_WDATA_8197F 0xffffffffL +#define BIT_DBI_WDATA_8197F(x) (((x) & BIT_MASK_DBI_WDATA_8197F) << BIT_SHIFT_DBI_WDATA_8197F) +#define BITS_DBI_WDATA_8197F (BIT_MASK_DBI_WDATA_8197F << BIT_SHIFT_DBI_WDATA_8197F) +#define BIT_CLEAR_DBI_WDATA_8197F(x) ((x) & (~BITS_DBI_WDATA_8197F)) +#define BIT_GET_DBI_WDATA_8197F(x) (((x) >> BIT_SHIFT_DBI_WDATA_8197F) & BIT_MASK_DBI_WDATA_8197F) +#define BIT_SET_DBI_WDATA_8197F(x, v) (BIT_CLEAR_DBI_WDATA_8197F(x) | BIT_DBI_WDATA_8197F(v)) + + +/* 2 REG_DBI_RDATA_V1_8197F */ + +#define BIT_SHIFT_DBI_RDATA_8197F 0 +#define BIT_MASK_DBI_RDATA_8197F 0xffffffffL +#define BIT_DBI_RDATA_8197F(x) (((x) & BIT_MASK_DBI_RDATA_8197F) << BIT_SHIFT_DBI_RDATA_8197F) +#define BITS_DBI_RDATA_8197F (BIT_MASK_DBI_RDATA_8197F << BIT_SHIFT_DBI_RDATA_8197F) +#define BIT_CLEAR_DBI_RDATA_8197F(x) ((x) & (~BITS_DBI_RDATA_8197F)) +#define BIT_GET_DBI_RDATA_8197F(x) (((x) >> BIT_SHIFT_DBI_RDATA_8197F) & BIT_MASK_DBI_RDATA_8197F) +#define BIT_SET_DBI_RDATA_8197F(x, v) (BIT_CLEAR_DBI_RDATA_8197F(x) | BIT_DBI_RDATA_8197F(v)) + + +/* 2 REG_STUCK_FLAG_V1_8197F */ +#define BIT_EN_STUCK_DBG_8197F BIT(26) +#define BIT_RX_STUCK_8197F BIT(25) +#define BIT_TX_STUCK_8197F BIT(24) +#define BIT_DBI_RFLAG_8197F BIT(17) +#define BIT_DBI_WFLAG_8197F BIT(16) + +#define BIT_SHIFT_DBI_WREN_8197F 12 +#define BIT_MASK_DBI_WREN_8197F 0xf +#define BIT_DBI_WREN_8197F(x) (((x) & BIT_MASK_DBI_WREN_8197F) << BIT_SHIFT_DBI_WREN_8197F) +#define BITS_DBI_WREN_8197F (BIT_MASK_DBI_WREN_8197F << BIT_SHIFT_DBI_WREN_8197F) +#define BIT_CLEAR_DBI_WREN_8197F(x) ((x) & (~BITS_DBI_WREN_8197F)) +#define BIT_GET_DBI_WREN_8197F(x) (((x) >> BIT_SHIFT_DBI_WREN_8197F) & BIT_MASK_DBI_WREN_8197F) +#define BIT_SET_DBI_WREN_8197F(x, v) (BIT_CLEAR_DBI_WREN_8197F(x) | BIT_DBI_WREN_8197F(v)) + + +#define BIT_SHIFT_DBI_ADDR_8197F 0 +#define BIT_MASK_DBI_ADDR_8197F 0xfff +#define BIT_DBI_ADDR_8197F(x) (((x) & BIT_MASK_DBI_ADDR_8197F) << BIT_SHIFT_DBI_ADDR_8197F) +#define BITS_DBI_ADDR_8197F (BIT_MASK_DBI_ADDR_8197F << BIT_SHIFT_DBI_ADDR_8197F) +#define BIT_CLEAR_DBI_ADDR_8197F(x) ((x) & (~BITS_DBI_ADDR_8197F)) +#define BIT_GET_DBI_ADDR_8197F(x) (((x) >> BIT_SHIFT_DBI_ADDR_8197F) & BIT_MASK_DBI_ADDR_8197F) +#define BIT_SET_DBI_ADDR_8197F(x, v) (BIT_CLEAR_DBI_ADDR_8197F(x) | BIT_DBI_ADDR_8197F(v)) + + +/* 2 REG_MDIO_V1_8197F */ + +#define BIT_SHIFT_MDIO_RDATA_8197F 16 +#define BIT_MASK_MDIO_RDATA_8197F 0xffff +#define BIT_MDIO_RDATA_8197F(x) (((x) & BIT_MASK_MDIO_RDATA_8197F) << BIT_SHIFT_MDIO_RDATA_8197F) +#define BITS_MDIO_RDATA_8197F (BIT_MASK_MDIO_RDATA_8197F << BIT_SHIFT_MDIO_RDATA_8197F) +#define BIT_CLEAR_MDIO_RDATA_8197F(x) ((x) & (~BITS_MDIO_RDATA_8197F)) +#define BIT_GET_MDIO_RDATA_8197F(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8197F) & BIT_MASK_MDIO_RDATA_8197F) +#define BIT_SET_MDIO_RDATA_8197F(x, v) (BIT_CLEAR_MDIO_RDATA_8197F(x) | BIT_MDIO_RDATA_8197F(v)) + + +#define BIT_SHIFT_MDIO_WDATA_8197F 0 +#define BIT_MASK_MDIO_WDATA_8197F 0xffff +#define BIT_MDIO_WDATA_8197F(x) (((x) & BIT_MASK_MDIO_WDATA_8197F) << BIT_SHIFT_MDIO_WDATA_8197F) +#define BITS_MDIO_WDATA_8197F (BIT_MASK_MDIO_WDATA_8197F << BIT_SHIFT_MDIO_WDATA_8197F) +#define BIT_CLEAR_MDIO_WDATA_8197F(x) ((x) & (~BITS_MDIO_WDATA_8197F)) +#define BIT_GET_MDIO_WDATA_8197F(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8197F) & BIT_MASK_MDIO_WDATA_8197F) +#define BIT_SET_MDIO_WDATA_8197F(x, v) (BIT_CLEAR_MDIO_WDATA_8197F(x) | BIT_MDIO_WDATA_8197F(v)) + + +/* 2 REG_WDT_CFG_8197F */ + +#define BIT_SHIFT_MDIO_PHY_ADDR_8197F 24 +#define BIT_MASK_MDIO_PHY_ADDR_8197F 0x1f +#define BIT_MDIO_PHY_ADDR_8197F(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8197F) << BIT_SHIFT_MDIO_PHY_ADDR_8197F) +#define BITS_MDIO_PHY_ADDR_8197F (BIT_MASK_MDIO_PHY_ADDR_8197F << BIT_SHIFT_MDIO_PHY_ADDR_8197F) +#define BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) ((x) & (~BITS_MDIO_PHY_ADDR_8197F)) +#define BIT_GET_MDIO_PHY_ADDR_8197F(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8197F) & BIT_MASK_MDIO_PHY_ADDR_8197F) +#define BIT_SET_MDIO_PHY_ADDR_8197F(x, v) (BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) | BIT_MDIO_PHY_ADDR_8197F(v)) + + +#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F 10 +#define BIT_MASK_WATCH_DOG_RECORD_V1_8197F 0x3fff +#define BIT_WATCH_DOG_RECORD_V1_8197F(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8197F) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) +#define BITS_WATCH_DOG_RECORD_V1_8197F (BIT_MASK_WATCH_DOG_RECORD_V1_8197F << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) ((x) & (~BITS_WATCH_DOG_RECORD_V1_8197F)) +#define BIT_GET_WATCH_DOG_RECORD_V1_8197F(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) & BIT_MASK_WATCH_DOG_RECORD_V1_8197F) +#define BIT_SET_WATCH_DOG_RECORD_V1_8197F(x, v) (BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) | BIT_WATCH_DOG_RECORD_V1_8197F(v)) + +#define BIT_R_IO_TIMEOUT_FLAG_V1_8197F BIT(9) +#define BIT_EN_WATCH_DOG_V1_8197F BIT(8) +#define BIT_ECRC_EN_V1_8197F BIT(7) +#define BIT_MDIO_RFLAG_V1_8197F BIT(6) +#define BIT_MDIO_WFLAG_V1_8197F BIT(5) + +#define BIT_SHIFT_MDIO_REG_ADDR_8197F 0 +#define BIT_MASK_MDIO_REG_ADDR_8197F 0x1f +#define BIT_MDIO_REG_ADDR_8197F(x) (((x) & BIT_MASK_MDIO_REG_ADDR_8197F) << BIT_SHIFT_MDIO_REG_ADDR_8197F) +#define BITS_MDIO_REG_ADDR_8197F (BIT_MASK_MDIO_REG_ADDR_8197F << BIT_SHIFT_MDIO_REG_ADDR_8197F) +#define BIT_CLEAR_MDIO_REG_ADDR_8197F(x) ((x) & (~BITS_MDIO_REG_ADDR_8197F)) +#define BIT_GET_MDIO_REG_ADDR_8197F(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_8197F) & BIT_MASK_MDIO_REG_ADDR_8197F) +#define BIT_SET_MDIO_REG_ADDR_8197F(x, v) (BIT_CLEAR_MDIO_REG_ADDR_8197F(x) | BIT_MDIO_REG_ADDR_8197F(v)) + + +/* 2 REG_HCI_MIX_CFG_8197F */ +#define BIT_RXRST_BACKDOOR_8197F BIT(31) +#define BIT_TXRST_BACKDOOR_8197F BIT(30) +#define BIT_RXIDX_RSTB_8197F BIT(29) +#define BIT_TXIDX_RSTB_8197F BIT(28) +#define BIT_DROP_NEXT_RXPKT_8197F BIT(27) +#define BIT_SHORT_CORE_RST_SEL_8197F BIT(26) +#define BIT_EXCEPT_RESUME_EN_8197F BIT(25) +#define BIT_EXCEPT_RESUME_FLAG_8197F BIT(24) +#define BIT_ALIGN_MTU_8197F BIT(23) +#define BIT_HOST_GEN2_SUPPORT_8197F BIT(20) + +#define BIT_SHIFT_TXDMA_ERR_FLAG_8197F 16 +#define BIT_MASK_TXDMA_ERR_FLAG_8197F 0xf +#define BIT_TXDMA_ERR_FLAG_8197F(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8197F) << BIT_SHIFT_TXDMA_ERR_FLAG_8197F) +#define BITS_TXDMA_ERR_FLAG_8197F (BIT_MASK_TXDMA_ERR_FLAG_8197F << BIT_SHIFT_TXDMA_ERR_FLAG_8197F) +#define BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8197F)) +#define BIT_GET_TXDMA_ERR_FLAG_8197F(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8197F) & BIT_MASK_TXDMA_ERR_FLAG_8197F) +#define BIT_SET_TXDMA_ERR_FLAG_8197F(x, v) (BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) | BIT_TXDMA_ERR_FLAG_8197F(v)) + + +#define BIT_SHIFT_EARLY_MODE_SEL_8197F 12 +#define BIT_MASK_EARLY_MODE_SEL_8197F 0xf +#define BIT_EARLY_MODE_SEL_8197F(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8197F) << BIT_SHIFT_EARLY_MODE_SEL_8197F) +#define BITS_EARLY_MODE_SEL_8197F (BIT_MASK_EARLY_MODE_SEL_8197F << BIT_SHIFT_EARLY_MODE_SEL_8197F) +#define BIT_CLEAR_EARLY_MODE_SEL_8197F(x) ((x) & (~BITS_EARLY_MODE_SEL_8197F)) +#define BIT_GET_EARLY_MODE_SEL_8197F(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8197F) & BIT_MASK_EARLY_MODE_SEL_8197F) +#define BIT_SET_EARLY_MODE_SEL_8197F(x, v) (BIT_CLEAR_EARLY_MODE_SEL_8197F(x) | BIT_EARLY_MODE_SEL_8197F(v)) + +#define BIT_EPHY_RX50_EN_8197F BIT(11) + +#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F 8 +#define BIT_MASK_MSI_TIMEOUT_ID_V1_8197F 0x7 +#define BIT_MSI_TIMEOUT_ID_V1_8197F(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8197F) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) +#define BITS_MSI_TIMEOUT_ID_V1_8197F (BIT_MASK_MSI_TIMEOUT_ID_V1_8197F << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8197F)) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8197F(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) & BIT_MASK_MSI_TIMEOUT_ID_V1_8197F) +#define BIT_SET_MSI_TIMEOUT_ID_V1_8197F(x, v) (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) | BIT_MSI_TIMEOUT_ID_V1_8197F(v)) + +#define BIT_RADDR_RD_8197F BIT(7) +#define BIT_EN_MUL_TAG_8197F BIT(6) +#define BIT_EN_EARLY_MODE_8197F BIT(5) +#define BIT_L0S_LINK_OFF_8197F BIT(4) +#define BIT_ACT_LINK_OFF_8197F BIT(3) + +/* 2 REG_STC_INT_CS_8197F(HCI STATE CHANGE INTERRUPT CONTROL AND STATUS) */ +#define BIT_STC_INT_EN_8197F BIT(31) + +#define BIT_SHIFT_STC_INT_FLAG_8197F 16 +#define BIT_MASK_STC_INT_FLAG_8197F 0xff +#define BIT_STC_INT_FLAG_8197F(x) (((x) & BIT_MASK_STC_INT_FLAG_8197F) << BIT_SHIFT_STC_INT_FLAG_8197F) +#define BITS_STC_INT_FLAG_8197F (BIT_MASK_STC_INT_FLAG_8197F << BIT_SHIFT_STC_INT_FLAG_8197F) +#define BIT_CLEAR_STC_INT_FLAG_8197F(x) ((x) & (~BITS_STC_INT_FLAG_8197F)) +#define BIT_GET_STC_INT_FLAG_8197F(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8197F) & BIT_MASK_STC_INT_FLAG_8197F) +#define BIT_SET_STC_INT_FLAG_8197F(x, v) (BIT_CLEAR_STC_INT_FLAG_8197F(x) | BIT_STC_INT_FLAG_8197F(v)) + + +#define BIT_SHIFT_STC_INT_IDX_8197F 8 +#define BIT_MASK_STC_INT_IDX_8197F 0x7 +#define BIT_STC_INT_IDX_8197F(x) (((x) & BIT_MASK_STC_INT_IDX_8197F) << BIT_SHIFT_STC_INT_IDX_8197F) +#define BITS_STC_INT_IDX_8197F (BIT_MASK_STC_INT_IDX_8197F << BIT_SHIFT_STC_INT_IDX_8197F) +#define BIT_CLEAR_STC_INT_IDX_8197F(x) ((x) & (~BITS_STC_INT_IDX_8197F)) +#define BIT_GET_STC_INT_IDX_8197F(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8197F) & BIT_MASK_STC_INT_IDX_8197F) +#define BIT_SET_STC_INT_IDX_8197F(x, v) (BIT_CLEAR_STC_INT_IDX_8197F(x) | BIT_STC_INT_IDX_8197F(v)) + + +#define BIT_SHIFT_STC_INT_REALTIME_CS_8197F 0 +#define BIT_MASK_STC_INT_REALTIME_CS_8197F 0x3f +#define BIT_STC_INT_REALTIME_CS_8197F(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8197F) << BIT_SHIFT_STC_INT_REALTIME_CS_8197F) +#define BITS_STC_INT_REALTIME_CS_8197F (BIT_MASK_STC_INT_REALTIME_CS_8197F << BIT_SHIFT_STC_INT_REALTIME_CS_8197F) +#define BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) ((x) & (~BITS_STC_INT_REALTIME_CS_8197F)) +#define BIT_GET_STC_INT_REALTIME_CS_8197F(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8197F) & BIT_MASK_STC_INT_REALTIME_CS_8197F) +#define BIT_SET_STC_INT_REALTIME_CS_8197F(x, v) (BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) | BIT_STC_INT_REALTIME_CS_8197F(v)) + + +/* 2 REG_ST_INT_CFG_8197F(HCI STATE CHANGE INTERRUPT CONFIGURATION) */ +#define BIT_STC_INT_GRP_EN_8197F BIT(31) + +#define BIT_SHIFT_STC_INT_EXPECT_LS_8197F 8 +#define BIT_MASK_STC_INT_EXPECT_LS_8197F 0x3f +#define BIT_STC_INT_EXPECT_LS_8197F(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8197F) << BIT_SHIFT_STC_INT_EXPECT_LS_8197F) +#define BITS_STC_INT_EXPECT_LS_8197F (BIT_MASK_STC_INT_EXPECT_LS_8197F << BIT_SHIFT_STC_INT_EXPECT_LS_8197F) +#define BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) ((x) & (~BITS_STC_INT_EXPECT_LS_8197F)) +#define BIT_GET_STC_INT_EXPECT_LS_8197F(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8197F) & BIT_MASK_STC_INT_EXPECT_LS_8197F) +#define BIT_SET_STC_INT_EXPECT_LS_8197F(x, v) (BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) | BIT_STC_INT_EXPECT_LS_8197F(v)) + + +#define BIT_SHIFT_STC_INT_EXPECT_CS_8197F 0 +#define BIT_MASK_STC_INT_EXPECT_CS_8197F 0x3f +#define BIT_STC_INT_EXPECT_CS_8197F(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8197F) << BIT_SHIFT_STC_INT_EXPECT_CS_8197F) +#define BITS_STC_INT_EXPECT_CS_8197F (BIT_MASK_STC_INT_EXPECT_CS_8197F << BIT_SHIFT_STC_INT_EXPECT_CS_8197F) +#define BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) ((x) & (~BITS_STC_INT_EXPECT_CS_8197F)) +#define BIT_GET_STC_INT_EXPECT_CS_8197F(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8197F) & BIT_MASK_STC_INT_EXPECT_CS_8197F) +#define BIT_SET_STC_INT_EXPECT_CS_8197F(x, v) (BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) | BIT_STC_INT_EXPECT_CS_8197F(v)) + + +/* 2 REG_CMU_DLY_CTRL_8197F(HCI PHY CLOCK MGT UNIT DELAY CONTROL ) */ +#define BIT_CMU_DLY_EN_8197F BIT(31) +#define BIT_CMU_DLY_MODE_8197F BIT(30) + +#define BIT_SHIFT_CMU_DLY_PRE_DIV_8197F 0 +#define BIT_MASK_CMU_DLY_PRE_DIV_8197F 0xff +#define BIT_CMU_DLY_PRE_DIV_8197F(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8197F) << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) +#define BITS_CMU_DLY_PRE_DIV_8197F (BIT_MASK_CMU_DLY_PRE_DIV_8197F << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) +#define BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8197F)) +#define BIT_GET_CMU_DLY_PRE_DIV_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) & BIT_MASK_CMU_DLY_PRE_DIV_8197F) +#define BIT_SET_CMU_DLY_PRE_DIV_8197F(x, v) (BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) | BIT_CMU_DLY_PRE_DIV_8197F(v)) + + +/* 2 REG_CMU_DLY_CFG_8197F(HCI PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ + +#define BIT_SHIFT_CMU_DLY_LTR_A2I_8197F 24 +#define BIT_MASK_CMU_DLY_LTR_A2I_8197F 0xff +#define BIT_CMU_DLY_LTR_A2I_8197F(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8197F) << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) +#define BITS_CMU_DLY_LTR_A2I_8197F (BIT_MASK_CMU_DLY_LTR_A2I_8197F << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) +#define BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8197F)) +#define BIT_GET_CMU_DLY_LTR_A2I_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) & BIT_MASK_CMU_DLY_LTR_A2I_8197F) +#define BIT_SET_CMU_DLY_LTR_A2I_8197F(x, v) (BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) | BIT_CMU_DLY_LTR_A2I_8197F(v)) + + +#define BIT_SHIFT_CMU_DLY_LTR_I2A_8197F 16 +#define BIT_MASK_CMU_DLY_LTR_I2A_8197F 0xff +#define BIT_CMU_DLY_LTR_I2A_8197F(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8197F) << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) +#define BITS_CMU_DLY_LTR_I2A_8197F (BIT_MASK_CMU_DLY_LTR_I2A_8197F << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) +#define BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8197F)) +#define BIT_GET_CMU_DLY_LTR_I2A_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) & BIT_MASK_CMU_DLY_LTR_I2A_8197F) +#define BIT_SET_CMU_DLY_LTR_I2A_8197F(x, v) (BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) | BIT_CMU_DLY_LTR_I2A_8197F(v)) + + +#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F 8 +#define BIT_MASK_CMU_DLY_LTR_IDLE_8197F 0xff +#define BIT_CMU_DLY_LTR_IDLE_8197F(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8197F) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) +#define BITS_CMU_DLY_LTR_IDLE_8197F (BIT_MASK_CMU_DLY_LTR_IDLE_8197F << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) +#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_IDLE_8197F)) +#define BIT_GET_CMU_DLY_LTR_IDLE_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) & BIT_MASK_CMU_DLY_LTR_IDLE_8197F) +#define BIT_SET_CMU_DLY_LTR_IDLE_8197F(x, v) (BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) | BIT_CMU_DLY_LTR_IDLE_8197F(v)) + + +#define BIT_SHIFT_CMU_DLY_LTR_ACT_8197F 0 +#define BIT_MASK_CMU_DLY_LTR_ACT_8197F 0xff +#define BIT_CMU_DLY_LTR_ACT_8197F(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8197F) << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) +#define BITS_CMU_DLY_LTR_ACT_8197F (BIT_MASK_CMU_DLY_LTR_ACT_8197F << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) +#define BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8197F)) +#define BIT_GET_CMU_DLY_LTR_ACT_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) & BIT_MASK_CMU_DLY_LTR_ACT_8197F) +#define BIT_SET_CMU_DLY_LTR_ACT_8197F(x, v) (BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) | BIT_CMU_DLY_LTR_ACT_8197F(v)) + + +/* 2 REG_H2CQ_TXBD_DESA_8197F */ + +#define BIT_SHIFT_H2CQ_TXBD_DESA_8197F 0 +#define BIT_MASK_H2CQ_TXBD_DESA_8197F 0xffffffffffffffffL +#define BIT_H2CQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8197F) << BIT_SHIFT_H2CQ_TXBD_DESA_8197F) +#define BITS_H2CQ_TXBD_DESA_8197F (BIT_MASK_H2CQ_TXBD_DESA_8197F << BIT_SHIFT_H2CQ_TXBD_DESA_8197F) +#define BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8197F)) +#define BIT_GET_H2CQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8197F) & BIT_MASK_H2CQ_TXBD_DESA_8197F) +#define BIT_SET_H2CQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) | BIT_H2CQ_TXBD_DESA_8197F(v)) + + +/* 2 REG_H2CQ_TXBD_NUM_8197F */ +#define BIT_HCI_H2CQ_FLAG_8197F BIT(14) + +#define BIT_SHIFT_H2CQ_DESC_MODE_8197F 12 +#define BIT_MASK_H2CQ_DESC_MODE_8197F 0x3 +#define BIT_H2CQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8197F) << BIT_SHIFT_H2CQ_DESC_MODE_8197F) +#define BITS_H2CQ_DESC_MODE_8197F (BIT_MASK_H2CQ_DESC_MODE_8197F << BIT_SHIFT_H2CQ_DESC_MODE_8197F) +#define BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) ((x) & (~BITS_H2CQ_DESC_MODE_8197F)) +#define BIT_GET_H2CQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8197F) & BIT_MASK_H2CQ_DESC_MODE_8197F) +#define BIT_SET_H2CQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) | BIT_H2CQ_DESC_MODE_8197F(v)) + + +#define BIT_SHIFT_H2CQ_DESC_NUM_8197F 0 +#define BIT_MASK_H2CQ_DESC_NUM_8197F 0xfff +#define BIT_H2CQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8197F) << BIT_SHIFT_H2CQ_DESC_NUM_8197F) +#define BITS_H2CQ_DESC_NUM_8197F (BIT_MASK_H2CQ_DESC_NUM_8197F << BIT_SHIFT_H2CQ_DESC_NUM_8197F) +#define BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) ((x) & (~BITS_H2CQ_DESC_NUM_8197F)) +#define BIT_GET_H2CQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8197F) & BIT_MASK_H2CQ_DESC_NUM_8197F) +#define BIT_SET_H2CQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) | BIT_H2CQ_DESC_NUM_8197F(v)) + + +/* 2 REG_H2CQ_TXBD_IDX_8197F */ + +#define BIT_SHIFT_H2CQ_HW_IDX_8197F 16 +#define BIT_MASK_H2CQ_HW_IDX_8197F 0xfff +#define BIT_H2CQ_HW_IDX_8197F(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8197F) << BIT_SHIFT_H2CQ_HW_IDX_8197F) +#define BITS_H2CQ_HW_IDX_8197F (BIT_MASK_H2CQ_HW_IDX_8197F << BIT_SHIFT_H2CQ_HW_IDX_8197F) +#define BIT_CLEAR_H2CQ_HW_IDX_8197F(x) ((x) & (~BITS_H2CQ_HW_IDX_8197F)) +#define BIT_GET_H2CQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8197F) & BIT_MASK_H2CQ_HW_IDX_8197F) +#define BIT_SET_H2CQ_HW_IDX_8197F(x, v) (BIT_CLEAR_H2CQ_HW_IDX_8197F(x) | BIT_H2CQ_HW_IDX_8197F(v)) + + +#define BIT_SHIFT_H2CQ_HOST_IDX_8197F 0 +#define BIT_MASK_H2CQ_HOST_IDX_8197F 0xfff +#define BIT_H2CQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8197F) << BIT_SHIFT_H2CQ_HOST_IDX_8197F) +#define BITS_H2CQ_HOST_IDX_8197F (BIT_MASK_H2CQ_HOST_IDX_8197F << BIT_SHIFT_H2CQ_HOST_IDX_8197F) +#define BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) ((x) & (~BITS_H2CQ_HOST_IDX_8197F)) +#define BIT_GET_H2CQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8197F) & BIT_MASK_H2CQ_HOST_IDX_8197F) +#define BIT_SET_H2CQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) | BIT_H2CQ_HOST_IDX_8197F(v)) + + +/* 2 REG_H2CQ_CSR_8197F[31:0] (H2CQ CONTROL AND STATUS) */ +#define BIT_H2CQ_FULL_8197F BIT(31) +#define BIT_CLR_H2CQ_HOST_IDX_8197F BIT(16) +#define BIT_CLR_H2CQ_HW_IDX_8197F BIT(8) +#define BIT_STOP_H2CQ_8197F BIT(0) + +/* 2 REG_AXI_EXCEPT_CS_8197F[31:0] (AXI EXCEPTION CONTROL AND STATUS) */ +#define BIT_AXI_RXDMA_TIMEOUT_RE_8197F BIT(21) +#define BIT_AXI_TXDMA_TIMEOUT_RE_8197F BIT(20) +#define BIT_AXI_DECERR_W_RE_8197F BIT(19) +#define BIT_AXI_DECERR_R_RE_8197F BIT(18) +#define BIT_AXI_SLVERR_W_RE_8197F BIT(17) +#define BIT_AXI_SLVERR_R_RE_8197F BIT(16) +#define BIT_AXI_RXDMA_TIMEOUT_IE_8197F BIT(13) +#define BIT_AXI_TXDMA_TIMEOUT_IE_8197F BIT(12) +#define BIT_AXI_DECERR_W_IE_8197F BIT(11) +#define BIT_AXI_DECERR_R_IE_8197F BIT(10) +#define BIT_AXI_SLVERR_W_IE_8197F BIT(9) +#define BIT_AXI_SLVERR_R_IE_8197F BIT(8) +#define BIT_AXI_RXDMA_TIMEOUT_FLAG_8197F BIT(5) +#define BIT_AXI_TXDMA_TIMEOUT_FLAG_8197F BIT(4) +#define BIT_AXI_DECERR_W_FLAG_8197F BIT(3) +#define BIT_AXI_DECERR_R_FLAG_8197F BIT(2) +#define BIT_AXI_SLVERR_W_FLAG_8197F BIT(1) +#define BIT_AXI_SLVERR_R_FLAG_8197F BIT(0) + +/* 2 REG_AXI_EXCEPT_TIME_8197F[31:0] (AXI EXCEPTION TIME CONTROL) */ + +#define BIT_SHIFT_AXI_RECOVERY_TIME_8197F 24 +#define BIT_MASK_AXI_RECOVERY_TIME_8197F 0xff +#define BIT_AXI_RECOVERY_TIME_8197F(x) (((x) & BIT_MASK_AXI_RECOVERY_TIME_8197F) << BIT_SHIFT_AXI_RECOVERY_TIME_8197F) +#define BITS_AXI_RECOVERY_TIME_8197F (BIT_MASK_AXI_RECOVERY_TIME_8197F << BIT_SHIFT_AXI_RECOVERY_TIME_8197F) +#define BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) ((x) & (~BITS_AXI_RECOVERY_TIME_8197F)) +#define BIT_GET_AXI_RECOVERY_TIME_8197F(x) (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME_8197F) & BIT_MASK_AXI_RECOVERY_TIME_8197F) +#define BIT_SET_AXI_RECOVERY_TIME_8197F(x, v) (BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) | BIT_AXI_RECOVERY_TIME_8197F(v)) + + +#define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F 12 +#define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F 0xfff +#define BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(x) (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F) << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) +#define BITS_AXI_RXDMA_TIMEOUT_VAL_8197F (BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) +#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) ((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL_8197F)) +#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL_8197F(x) (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F) +#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL_8197F(x, v) (BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) | BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(v)) + + +#define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F 0 +#define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F 0xfff +#define BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(x) (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F) << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) +#define BITS_AXI_TXDMA_TIMEOUT_VAL_8197F (BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) +#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) ((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL_8197F)) +#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL_8197F(x) (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F) +#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL_8197F(x, v) (BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) | BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(v)) + + +/* 2 REG_Q0_INFO_8197F */ + +#define BIT_SHIFT_QUEUEMACID_Q0_V1_8197F 25 +#define BIT_MASK_QUEUEMACID_Q0_V1_8197F 0x7f +#define BIT_QUEUEMACID_Q0_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) +#define BITS_QUEUEMACID_Q0_V1_8197F (BIT_MASK_QUEUEMACID_Q0_V1_8197F << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q0_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q0_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) & BIT_MASK_QUEUEMACID_Q0_V1_8197F) +#define BIT_SET_QUEUEMACID_Q0_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) | BIT_QUEUEMACID_Q0_V1_8197F(v)) + + +#define BIT_SHIFT_QUEUEAC_Q0_V1_8197F 23 +#define BIT_MASK_QUEUEAC_Q0_V1_8197F 0x3 +#define BIT_QUEUEAC_Q0_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8197F) << BIT_SHIFT_QUEUEAC_Q0_V1_8197F) +#define BITS_QUEUEAC_Q0_V1_8197F (BIT_MASK_QUEUEAC_Q0_V1_8197F << BIT_SHIFT_QUEUEAC_Q0_V1_8197F) +#define BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8197F)) +#define BIT_GET_QUEUEAC_Q0_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8197F) & BIT_MASK_QUEUEAC_Q0_V1_8197F) +#define BIT_SET_QUEUEAC_Q0_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) | BIT_QUEUEAC_Q0_V1_8197F(v)) + +#define BIT_TIDEMPTY_Q0_V1_8197F BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q0_V2_8197F 11 +#define BIT_MASK_TAIL_PKT_Q0_V2_8197F 0x7ff +#define BIT_TAIL_PKT_Q0_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) +#define BITS_TAIL_PKT_Q0_V2_8197F (BIT_MASK_TAIL_PKT_Q0_V2_8197F << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8197F)) +#define BIT_GET_TAIL_PKT_Q0_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) & BIT_MASK_TAIL_PKT_Q0_V2_8197F) +#define BIT_SET_TAIL_PKT_Q0_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) | BIT_TAIL_PKT_Q0_V2_8197F(v)) + + +#define BIT_SHIFT_HEAD_PKT_Q0_V1_8197F 0 +#define BIT_MASK_HEAD_PKT_Q0_V1_8197F 0x7ff +#define BIT_HEAD_PKT_Q0_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) +#define BITS_HEAD_PKT_Q0_V1_8197F (BIT_MASK_HEAD_PKT_Q0_V1_8197F << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8197F)) +#define BIT_GET_HEAD_PKT_Q0_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) & BIT_MASK_HEAD_PKT_Q0_V1_8197F) +#define BIT_SET_HEAD_PKT_Q0_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) | BIT_HEAD_PKT_Q0_V1_8197F(v)) + + +/* 2 REG_Q1_INFO_8197F */ + +#define BIT_SHIFT_QUEUEMACID_Q1_V1_8197F 25 +#define BIT_MASK_QUEUEMACID_Q1_V1_8197F 0x7f +#define BIT_QUEUEMACID_Q1_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) +#define BITS_QUEUEMACID_Q1_V1_8197F (BIT_MASK_QUEUEMACID_Q1_V1_8197F << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q1_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q1_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) & BIT_MASK_QUEUEMACID_Q1_V1_8197F) +#define BIT_SET_QUEUEMACID_Q1_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) | BIT_QUEUEMACID_Q1_V1_8197F(v)) + + +#define BIT_SHIFT_QUEUEAC_Q1_V1_8197F 23 +#define BIT_MASK_QUEUEAC_Q1_V1_8197F 0x3 +#define BIT_QUEUEAC_Q1_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8197F) << BIT_SHIFT_QUEUEAC_Q1_V1_8197F) +#define BITS_QUEUEAC_Q1_V1_8197F (BIT_MASK_QUEUEAC_Q1_V1_8197F << BIT_SHIFT_QUEUEAC_Q1_V1_8197F) +#define BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8197F)) +#define BIT_GET_QUEUEAC_Q1_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8197F) & BIT_MASK_QUEUEAC_Q1_V1_8197F) +#define BIT_SET_QUEUEAC_Q1_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) | BIT_QUEUEAC_Q1_V1_8197F(v)) + +#define BIT_TIDEMPTY_Q1_V1_8197F BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q1_V2_8197F 11 +#define BIT_MASK_TAIL_PKT_Q1_V2_8197F 0x7ff +#define BIT_TAIL_PKT_Q1_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) +#define BITS_TAIL_PKT_Q1_V2_8197F (BIT_MASK_TAIL_PKT_Q1_V2_8197F << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8197F)) +#define BIT_GET_TAIL_PKT_Q1_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) & BIT_MASK_TAIL_PKT_Q1_V2_8197F) +#define BIT_SET_TAIL_PKT_Q1_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) | BIT_TAIL_PKT_Q1_V2_8197F(v)) + + +#define BIT_SHIFT_HEAD_PKT_Q1_V1_8197F 0 +#define BIT_MASK_HEAD_PKT_Q1_V1_8197F 0x7ff +#define BIT_HEAD_PKT_Q1_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) +#define BITS_HEAD_PKT_Q1_V1_8197F (BIT_MASK_HEAD_PKT_Q1_V1_8197F << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8197F)) +#define BIT_GET_HEAD_PKT_Q1_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) & BIT_MASK_HEAD_PKT_Q1_V1_8197F) +#define BIT_SET_HEAD_PKT_Q1_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) | BIT_HEAD_PKT_Q1_V1_8197F(v)) + + +/* 2 REG_Q2_INFO_8197F */ + +#define BIT_SHIFT_QUEUEMACID_Q2_V1_8197F 25 +#define BIT_MASK_QUEUEMACID_Q2_V1_8197F 0x7f +#define BIT_QUEUEMACID_Q2_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) +#define BITS_QUEUEMACID_Q2_V1_8197F (BIT_MASK_QUEUEMACID_Q2_V1_8197F << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q2_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q2_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) & BIT_MASK_QUEUEMACID_Q2_V1_8197F) +#define BIT_SET_QUEUEMACID_Q2_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) | BIT_QUEUEMACID_Q2_V1_8197F(v)) + + +#define BIT_SHIFT_QUEUEAC_Q2_V1_8197F 23 +#define BIT_MASK_QUEUEAC_Q2_V1_8197F 0x3 +#define BIT_QUEUEAC_Q2_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8197F) << BIT_SHIFT_QUEUEAC_Q2_V1_8197F) +#define BITS_QUEUEAC_Q2_V1_8197F (BIT_MASK_QUEUEAC_Q2_V1_8197F << BIT_SHIFT_QUEUEAC_Q2_V1_8197F) +#define BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8197F)) +#define BIT_GET_QUEUEAC_Q2_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8197F) & BIT_MASK_QUEUEAC_Q2_V1_8197F) +#define BIT_SET_QUEUEAC_Q2_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) | BIT_QUEUEAC_Q2_V1_8197F(v)) + +#define BIT_TIDEMPTY_Q2_V1_8197F BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q2_V2_8197F 11 +#define BIT_MASK_TAIL_PKT_Q2_V2_8197F 0x7ff +#define BIT_TAIL_PKT_Q2_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) +#define BITS_TAIL_PKT_Q2_V2_8197F (BIT_MASK_TAIL_PKT_Q2_V2_8197F << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8197F)) +#define BIT_GET_TAIL_PKT_Q2_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) & BIT_MASK_TAIL_PKT_Q2_V2_8197F) +#define BIT_SET_TAIL_PKT_Q2_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) | BIT_TAIL_PKT_Q2_V2_8197F(v)) + + +#define BIT_SHIFT_HEAD_PKT_Q2_V1_8197F 0 +#define BIT_MASK_HEAD_PKT_Q2_V1_8197F 0x7ff +#define BIT_HEAD_PKT_Q2_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) +#define BITS_HEAD_PKT_Q2_V1_8197F (BIT_MASK_HEAD_PKT_Q2_V1_8197F << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8197F)) +#define BIT_GET_HEAD_PKT_Q2_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) & BIT_MASK_HEAD_PKT_Q2_V1_8197F) +#define BIT_SET_HEAD_PKT_Q2_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) | BIT_HEAD_PKT_Q2_V1_8197F(v)) + + +/* 2 REG_Q3_INFO_8197F */ + +#define BIT_SHIFT_QUEUEMACID_Q3_V1_8197F 25 +#define BIT_MASK_QUEUEMACID_Q3_V1_8197F 0x7f +#define BIT_QUEUEMACID_Q3_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) +#define BITS_QUEUEMACID_Q3_V1_8197F (BIT_MASK_QUEUEMACID_Q3_V1_8197F << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q3_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q3_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) & BIT_MASK_QUEUEMACID_Q3_V1_8197F) +#define BIT_SET_QUEUEMACID_Q3_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) | BIT_QUEUEMACID_Q3_V1_8197F(v)) + + +#define BIT_SHIFT_QUEUEAC_Q3_V1_8197F 23 +#define BIT_MASK_QUEUEAC_Q3_V1_8197F 0x3 +#define BIT_QUEUEAC_Q3_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8197F) << BIT_SHIFT_QUEUEAC_Q3_V1_8197F) +#define BITS_QUEUEAC_Q3_V1_8197F (BIT_MASK_QUEUEAC_Q3_V1_8197F << BIT_SHIFT_QUEUEAC_Q3_V1_8197F) +#define BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8197F)) +#define BIT_GET_QUEUEAC_Q3_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8197F) & BIT_MASK_QUEUEAC_Q3_V1_8197F) +#define BIT_SET_QUEUEAC_Q3_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) | BIT_QUEUEAC_Q3_V1_8197F(v)) + +#define BIT_TIDEMPTY_Q3_V1_8197F BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q3_V2_8197F 11 +#define BIT_MASK_TAIL_PKT_Q3_V2_8197F 0x7ff +#define BIT_TAIL_PKT_Q3_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) +#define BITS_TAIL_PKT_Q3_V2_8197F (BIT_MASK_TAIL_PKT_Q3_V2_8197F << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8197F)) +#define BIT_GET_TAIL_PKT_Q3_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) & BIT_MASK_TAIL_PKT_Q3_V2_8197F) +#define BIT_SET_TAIL_PKT_Q3_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) | BIT_TAIL_PKT_Q3_V2_8197F(v)) + + +#define BIT_SHIFT_HEAD_PKT_Q3_V1_8197F 0 +#define BIT_MASK_HEAD_PKT_Q3_V1_8197F 0x7ff +#define BIT_HEAD_PKT_Q3_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) +#define BITS_HEAD_PKT_Q3_V1_8197F (BIT_MASK_HEAD_PKT_Q3_V1_8197F << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8197F)) +#define BIT_GET_HEAD_PKT_Q3_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) & BIT_MASK_HEAD_PKT_Q3_V1_8197F) +#define BIT_SET_HEAD_PKT_Q3_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) | BIT_HEAD_PKT_Q3_V1_8197F(v)) + + +/* 2 REG_MGQ_INFO_8197F */ + +#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F 25 +#define BIT_MASK_QUEUEMACID_MGQ_V1_8197F 0x7f +#define BIT_QUEUEMACID_MGQ_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8197F) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) +#define BITS_QUEUEMACID_MGQ_V1_8197F (BIT_MASK_QUEUEMACID_MGQ_V1_8197F << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_MGQ_V1_8197F)) +#define BIT_GET_QUEUEMACID_MGQ_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) & BIT_MASK_QUEUEMACID_MGQ_V1_8197F) +#define BIT_SET_QUEUEMACID_MGQ_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) | BIT_QUEUEMACID_MGQ_V1_8197F(v)) + + +#define BIT_SHIFT_QUEUEAC_MGQ_V1_8197F 23 +#define BIT_MASK_QUEUEAC_MGQ_V1_8197F 0x3 +#define BIT_QUEUEAC_MGQ_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8197F) << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) +#define BITS_QUEUEAC_MGQ_V1_8197F (BIT_MASK_QUEUEAC_MGQ_V1_8197F << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) +#define BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8197F)) +#define BIT_GET_QUEUEAC_MGQ_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) & BIT_MASK_QUEUEAC_MGQ_V1_8197F) +#define BIT_SET_QUEUEAC_MGQ_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) | BIT_QUEUEAC_MGQ_V1_8197F(v)) + +#define BIT_TIDEMPTY_MGQ_V1_8197F BIT(22) + +#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F 11 +#define BIT_MASK_TAIL_PKT_MGQ_V2_8197F 0x7ff +#define BIT_TAIL_PKT_MGQ_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8197F) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) +#define BITS_TAIL_PKT_MGQ_V2_8197F (BIT_MASK_TAIL_PKT_MGQ_V2_8197F << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8197F)) +#define BIT_GET_TAIL_PKT_MGQ_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) & BIT_MASK_TAIL_PKT_MGQ_V2_8197F) +#define BIT_SET_TAIL_PKT_MGQ_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) | BIT_TAIL_PKT_MGQ_V2_8197F(v)) + + +#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F 0 +#define BIT_MASK_HEAD_PKT_MGQ_V1_8197F 0x7ff +#define BIT_HEAD_PKT_MGQ_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8197F) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) +#define BITS_HEAD_PKT_MGQ_V1_8197F (BIT_MASK_HEAD_PKT_MGQ_V1_8197F << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8197F)) +#define BIT_GET_HEAD_PKT_MGQ_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) & BIT_MASK_HEAD_PKT_MGQ_V1_8197F) +#define BIT_SET_HEAD_PKT_MGQ_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) | BIT_HEAD_PKT_MGQ_V1_8197F(v)) + + +/* 2 REG_HIQ_INFO_8197F */ + +#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F 25 +#define BIT_MASK_QUEUEMACID_HIQ_V1_8197F 0x7f +#define BIT_QUEUEMACID_HIQ_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8197F) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) +#define BITS_QUEUEMACID_HIQ_V1_8197F (BIT_MASK_QUEUEMACID_HIQ_V1_8197F << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_HIQ_V1_8197F)) +#define BIT_GET_QUEUEMACID_HIQ_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) & BIT_MASK_QUEUEMACID_HIQ_V1_8197F) +#define BIT_SET_QUEUEMACID_HIQ_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) | BIT_QUEUEMACID_HIQ_V1_8197F(v)) + + +#define BIT_SHIFT_QUEUEAC_HIQ_V1_8197F 23 +#define BIT_MASK_QUEUEAC_HIQ_V1_8197F 0x3 +#define BIT_QUEUEAC_HIQ_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8197F) << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) +#define BITS_QUEUEAC_HIQ_V1_8197F (BIT_MASK_QUEUEAC_HIQ_V1_8197F << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) +#define BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8197F)) +#define BIT_GET_QUEUEAC_HIQ_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) & BIT_MASK_QUEUEAC_HIQ_V1_8197F) +#define BIT_SET_QUEUEAC_HIQ_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) | BIT_QUEUEAC_HIQ_V1_8197F(v)) + +#define BIT_TIDEMPTY_HIQ_V1_8197F BIT(22) + +#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F 11 +#define BIT_MASK_TAIL_PKT_HIQ_V2_8197F 0x7ff +#define BIT_TAIL_PKT_HIQ_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8197F) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) +#define BITS_TAIL_PKT_HIQ_V2_8197F (BIT_MASK_TAIL_PKT_HIQ_V2_8197F << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8197F)) +#define BIT_GET_TAIL_PKT_HIQ_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) & BIT_MASK_TAIL_PKT_HIQ_V2_8197F) +#define BIT_SET_TAIL_PKT_HIQ_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) | BIT_TAIL_PKT_HIQ_V2_8197F(v)) + + +#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F 0 +#define BIT_MASK_HEAD_PKT_HIQ_V1_8197F 0x7ff +#define BIT_HEAD_PKT_HIQ_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8197F) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) +#define BITS_HEAD_PKT_HIQ_V1_8197F (BIT_MASK_HEAD_PKT_HIQ_V1_8197F << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8197F)) +#define BIT_GET_HEAD_PKT_HIQ_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) & BIT_MASK_HEAD_PKT_HIQ_V1_8197F) +#define BIT_SET_HEAD_PKT_HIQ_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) | BIT_HEAD_PKT_HIQ_V1_8197F(v)) + + +/* 2 REG_BCNQ_INFO_8197F */ + +#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F 0 +#define BIT_MASK_BCNQ_HEAD_PG_V1_8197F 0xfff +#define BIT_BCNQ_HEAD_PG_V1_8197F(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8197F) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) +#define BITS_BCNQ_HEAD_PG_V1_8197F (BIT_MASK_BCNQ_HEAD_PG_V1_8197F << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) +#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8197F)) +#define BIT_GET_BCNQ_HEAD_PG_V1_8197F(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) & BIT_MASK_BCNQ_HEAD_PG_V1_8197F) +#define BIT_SET_BCNQ_HEAD_PG_V1_8197F(x, v) (BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) | BIT_BCNQ_HEAD_PG_V1_8197F(v)) + + +/* 2 REG_TXPKT_EMPTY_8197F */ +#define BIT_BCNQ_EMPTY_8197F BIT(11) +#define BIT_HQQ_EMPTY_8197F BIT(10) +#define BIT_MQQ_EMPTY_8197F BIT(9) +#define BIT_MGQ_CPU_EMPTY_8197F BIT(8) +#define BIT_AC7Q_EMPTY_8197F BIT(7) +#define BIT_AC6Q_EMPTY_8197F BIT(6) +#define BIT_AC5Q_EMPTY_8197F BIT(5) +#define BIT_AC4Q_EMPTY_8197F BIT(4) +#define BIT_AC3Q_EMPTY_8197F BIT(3) +#define BIT_AC2Q_EMPTY_8197F BIT(2) +#define BIT_AC1Q_EMPTY_8197F BIT(1) +#define BIT_AC0Q_EMPTY_8197F BIT(0) + +/* 2 REG_CPU_MGQ_INFO_8197F */ +#define BIT_BCN1_POLL_8197F BIT(30) +#define BIT_CPUMGT_POLL_8197F BIT(29) +#define BIT_BCN_POLL_8197F BIT(28) +#define BIT_CPUMGQ_FW_NUM_V1_8197F BIT(12) + +#define BIT_SHIFT_FW_FREE_TAIL_V1_8197F 0 +#define BIT_MASK_FW_FREE_TAIL_V1_8197F 0xfff +#define BIT_FW_FREE_TAIL_V1_8197F(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8197F) << BIT_SHIFT_FW_FREE_TAIL_V1_8197F) +#define BITS_FW_FREE_TAIL_V1_8197F (BIT_MASK_FW_FREE_TAIL_V1_8197F << BIT_SHIFT_FW_FREE_TAIL_V1_8197F) +#define BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8197F)) +#define BIT_GET_FW_FREE_TAIL_V1_8197F(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8197F) & BIT_MASK_FW_FREE_TAIL_V1_8197F) +#define BIT_SET_FW_FREE_TAIL_V1_8197F(x, v) (BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) | BIT_FW_FREE_TAIL_V1_8197F(v)) + + +/* 2 REG_FWHW_TXQ_CTRL_8197F */ +#define BIT_RTS_LIMIT_IN_OFDM_8197F BIT(23) +#define BIT_EN_BCNQ_DL_8197F BIT(22) +#define BIT_EN_RD_RESP_NAV_BK_8197F BIT(21) +#define BIT_EN_WR_FREE_TAIL_8197F BIT(20) + +#define BIT_SHIFT_EN_QUEUE_RPT_8197F 8 +#define BIT_MASK_EN_QUEUE_RPT_8197F 0xff +#define BIT_EN_QUEUE_RPT_8197F(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8197F) << BIT_SHIFT_EN_QUEUE_RPT_8197F) +#define BITS_EN_QUEUE_RPT_8197F (BIT_MASK_EN_QUEUE_RPT_8197F << BIT_SHIFT_EN_QUEUE_RPT_8197F) +#define BIT_CLEAR_EN_QUEUE_RPT_8197F(x) ((x) & (~BITS_EN_QUEUE_RPT_8197F)) +#define BIT_GET_EN_QUEUE_RPT_8197F(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8197F) & BIT_MASK_EN_QUEUE_RPT_8197F) +#define BIT_SET_EN_QUEUE_RPT_8197F(x, v) (BIT_CLEAR_EN_QUEUE_RPT_8197F(x) | BIT_EN_QUEUE_RPT_8197F(v)) + +#define BIT_EN_RTY_BK_8197F BIT(7) +#define BIT_EN_USE_INI_RAT_8197F BIT(6) +#define BIT_EN_RTS_NAV_BK_8197F BIT(5) +#define BIT_DIS_SSN_CHECK_8197F BIT(4) +#define BIT_MACID_MATCH_RTS_8197F BIT(3) +#define BIT_EN_BCN_TRXRPT_V1_8197F BIT(2) +#define BIT_R_EN_FTMRPT_8197F BIT(1) +#define BIT_R_BMC_NAV_PROTECT_8197F BIT(0) + +/* 2 REG_NOT_VALID_8197F */ +#define BIT__R_EN_RTY_BK_COD_8197F BIT(2) + +#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F 0 +#define BIT_MASK__R_DATA_FALLBACK_SEL_8197F 0x3 +#define BIT__R_DATA_FALLBACK_SEL_8197F(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8197F) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) +#define BITS__R_DATA_FALLBACK_SEL_8197F (BIT_MASK__R_DATA_FALLBACK_SEL_8197F << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) +#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) ((x) & (~BITS__R_DATA_FALLBACK_SEL_8197F)) +#define BIT_GET__R_DATA_FALLBACK_SEL_8197F(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) & BIT_MASK__R_DATA_FALLBACK_SEL_8197F) +#define BIT_SET__R_DATA_FALLBACK_SEL_8197F(x, v) (BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) | BIT__R_DATA_FALLBACK_SEL_8197F(v)) + + +/* 2 REG_BCNQ_BDNY_V1_8197F */ + +#define BIT_SHIFT_BCNQ_PGBNDY_V1_8197F 0 +#define BIT_MASK_BCNQ_PGBNDY_V1_8197F 0xfff +#define BIT_BCNQ_PGBNDY_V1_8197F(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8197F) << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) +#define BITS_BCNQ_PGBNDY_V1_8197F (BIT_MASK_BCNQ_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) +#define BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8197F)) +#define BIT_GET_BCNQ_PGBNDY_V1_8197F(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) & BIT_MASK_BCNQ_PGBNDY_V1_8197F) +#define BIT_SET_BCNQ_PGBNDY_V1_8197F(x, v) (BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) | BIT_BCNQ_PGBNDY_V1_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_LIFETIME_EN_8197F */ +#define BIT_BT_INT_CPU_8197F BIT(7) +#define BIT_BT_INT_PTA_8197F BIT(6) +#define BIT_EN_CTRL_RTYBIT_8197F BIT(4) +#define BIT_LIFETIME_BK_EN_8197F BIT(3) +#define BIT_LIFETIME_BE_EN_8197F BIT(2) +#define BIT_LIFETIME_VI_EN_8197F BIT(1) +#define BIT_LIFETIME_VO_EN_8197F BIT(0) + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_SPEC_SIFS_8197F */ + +#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F 8 +#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F 0xff +#define BIT_SPEC_SIFS_OFDM_PTCL_8197F(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) +#define BITS_SPEC_SIFS_OFDM_PTCL_8197F (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8197F)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8197F(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8197F(x, v) (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) | BIT_SPEC_SIFS_OFDM_PTCL_8197F(v)) + + +#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F 0 +#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F 0xff +#define BIT_SPEC_SIFS_CCK_PTCL_8197F(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) +#define BITS_SPEC_SIFS_CCK_PTCL_8197F (BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8197F)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8197F(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F) +#define BIT_SET_SPEC_SIFS_CCK_PTCL_8197F(x, v) (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) | BIT_SPEC_SIFS_CCK_PTCL_8197F(v)) + + +/* 2 REG_RETRY_LIMIT_8197F */ + +#define BIT_SHIFT_SRL_8197F 8 +#define BIT_MASK_SRL_8197F 0x3f +#define BIT_SRL_8197F(x) (((x) & BIT_MASK_SRL_8197F) << BIT_SHIFT_SRL_8197F) +#define BITS_SRL_8197F (BIT_MASK_SRL_8197F << BIT_SHIFT_SRL_8197F) +#define BIT_CLEAR_SRL_8197F(x) ((x) & (~BITS_SRL_8197F)) +#define BIT_GET_SRL_8197F(x) (((x) >> BIT_SHIFT_SRL_8197F) & BIT_MASK_SRL_8197F) +#define BIT_SET_SRL_8197F(x, v) (BIT_CLEAR_SRL_8197F(x) | BIT_SRL_8197F(v)) + + +#define BIT_SHIFT_LRL_8197F 0 +#define BIT_MASK_LRL_8197F 0x3f +#define BIT_LRL_8197F(x) (((x) & BIT_MASK_LRL_8197F) << BIT_SHIFT_LRL_8197F) +#define BITS_LRL_8197F (BIT_MASK_LRL_8197F << BIT_SHIFT_LRL_8197F) +#define BIT_CLEAR_LRL_8197F(x) ((x) & (~BITS_LRL_8197F)) +#define BIT_GET_LRL_8197F(x) (((x) >> BIT_SHIFT_LRL_8197F) & BIT_MASK_LRL_8197F) +#define BIT_SET_LRL_8197F(x, v) (BIT_CLEAR_LRL_8197F(x) | BIT_LRL_8197F(v)) + + +/* 2 REG_TXBF_CTRL_8197F */ +#define BIT_R_ENABLE_NDPA_8197F BIT(31) +#define BIT_USE_NDPA_PARAMETER_8197F BIT(30) +#define BIT_R_PROP_TXBF_8197F BIT(29) +#define BIT_R_EN_NDPA_INT_8197F BIT(28) +#define BIT_R_TXBF1_80M_8197F BIT(27) +#define BIT_R_TXBF1_40M_8197F BIT(26) +#define BIT_R_TXBF1_20M_8197F BIT(25) + +#define BIT_SHIFT_R_TXBF1_AID_8197F 16 +#define BIT_MASK_R_TXBF1_AID_8197F 0x1ff +#define BIT_R_TXBF1_AID_8197F(x) (((x) & BIT_MASK_R_TXBF1_AID_8197F) << BIT_SHIFT_R_TXBF1_AID_8197F) +#define BITS_R_TXBF1_AID_8197F (BIT_MASK_R_TXBF1_AID_8197F << BIT_SHIFT_R_TXBF1_AID_8197F) +#define BIT_CLEAR_R_TXBF1_AID_8197F(x) ((x) & (~BITS_R_TXBF1_AID_8197F)) +#define BIT_GET_R_TXBF1_AID_8197F(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8197F) & BIT_MASK_R_TXBF1_AID_8197F) +#define BIT_SET_R_TXBF1_AID_8197F(x, v) (BIT_CLEAR_R_TXBF1_AID_8197F(x) | BIT_R_TXBF1_AID_8197F(v)) + +#define BIT_DIS_NDP_BFEN_8197F BIT(15) +#define BIT_R_TXBCN_NOBLOCK_NDP_8197F BIT(14) +#define BIT_R_TXBF0_80M_8197F BIT(11) +#define BIT_R_TXBF0_40M_8197F BIT(10) +#define BIT_R_TXBF0_20M_8197F BIT(9) + +#define BIT_SHIFT_R_TXBF0_AID_8197F 0 +#define BIT_MASK_R_TXBF0_AID_8197F 0x1ff +#define BIT_R_TXBF0_AID_8197F(x) (((x) & BIT_MASK_R_TXBF0_AID_8197F) << BIT_SHIFT_R_TXBF0_AID_8197F) +#define BITS_R_TXBF0_AID_8197F (BIT_MASK_R_TXBF0_AID_8197F << BIT_SHIFT_R_TXBF0_AID_8197F) +#define BIT_CLEAR_R_TXBF0_AID_8197F(x) ((x) & (~BITS_R_TXBF0_AID_8197F)) +#define BIT_GET_R_TXBF0_AID_8197F(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8197F) & BIT_MASK_R_TXBF0_AID_8197F) +#define BIT_SET_R_TXBF0_AID_8197F(x, v) (BIT_CLEAR_R_TXBF0_AID_8197F(x) | BIT_R_TXBF0_AID_8197F(v)) + + +/* 2 REG_DARFRC_8197F */ + +#define BIT_SHIFT_DARF_RC8_8197F (56 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC8_8197F 0x1f +#define BIT_DARF_RC8_8197F(x) (((x) & BIT_MASK_DARF_RC8_8197F) << BIT_SHIFT_DARF_RC8_8197F) +#define BITS_DARF_RC8_8197F (BIT_MASK_DARF_RC8_8197F << BIT_SHIFT_DARF_RC8_8197F) +#define BIT_CLEAR_DARF_RC8_8197F(x) ((x) & (~BITS_DARF_RC8_8197F)) +#define BIT_GET_DARF_RC8_8197F(x) (((x) >> BIT_SHIFT_DARF_RC8_8197F) & BIT_MASK_DARF_RC8_8197F) +#define BIT_SET_DARF_RC8_8197F(x, v) (BIT_CLEAR_DARF_RC8_8197F(x) | BIT_DARF_RC8_8197F(v)) + + +#define BIT_SHIFT_DARF_RC7_8197F (48 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC7_8197F 0x1f +#define BIT_DARF_RC7_8197F(x) (((x) & BIT_MASK_DARF_RC7_8197F) << BIT_SHIFT_DARF_RC7_8197F) +#define BITS_DARF_RC7_8197F (BIT_MASK_DARF_RC7_8197F << BIT_SHIFT_DARF_RC7_8197F) +#define BIT_CLEAR_DARF_RC7_8197F(x) ((x) & (~BITS_DARF_RC7_8197F)) +#define BIT_GET_DARF_RC7_8197F(x) (((x) >> BIT_SHIFT_DARF_RC7_8197F) & BIT_MASK_DARF_RC7_8197F) +#define BIT_SET_DARF_RC7_8197F(x, v) (BIT_CLEAR_DARF_RC7_8197F(x) | BIT_DARF_RC7_8197F(v)) + + +#define BIT_SHIFT_DARF_RC6_8197F (40 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC6_8197F 0x1f +#define BIT_DARF_RC6_8197F(x) (((x) & BIT_MASK_DARF_RC6_8197F) << BIT_SHIFT_DARF_RC6_8197F) +#define BITS_DARF_RC6_8197F (BIT_MASK_DARF_RC6_8197F << BIT_SHIFT_DARF_RC6_8197F) +#define BIT_CLEAR_DARF_RC6_8197F(x) ((x) & (~BITS_DARF_RC6_8197F)) +#define BIT_GET_DARF_RC6_8197F(x) (((x) >> BIT_SHIFT_DARF_RC6_8197F) & BIT_MASK_DARF_RC6_8197F) +#define BIT_SET_DARF_RC6_8197F(x, v) (BIT_CLEAR_DARF_RC6_8197F(x) | BIT_DARF_RC6_8197F(v)) + + +#define BIT_SHIFT_DARF_RC5_8197F (32 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC5_8197F 0x1f +#define BIT_DARF_RC5_8197F(x) (((x) & BIT_MASK_DARF_RC5_8197F) << BIT_SHIFT_DARF_RC5_8197F) +#define BITS_DARF_RC5_8197F (BIT_MASK_DARF_RC5_8197F << BIT_SHIFT_DARF_RC5_8197F) +#define BIT_CLEAR_DARF_RC5_8197F(x) ((x) & (~BITS_DARF_RC5_8197F)) +#define BIT_GET_DARF_RC5_8197F(x) (((x) >> BIT_SHIFT_DARF_RC5_8197F) & BIT_MASK_DARF_RC5_8197F) +#define BIT_SET_DARF_RC5_8197F(x, v) (BIT_CLEAR_DARF_RC5_8197F(x) | BIT_DARF_RC5_8197F(v)) + + +#define BIT_SHIFT_DARF_RC4_8197F 24 +#define BIT_MASK_DARF_RC4_8197F 0x1f +#define BIT_DARF_RC4_8197F(x) (((x) & BIT_MASK_DARF_RC4_8197F) << BIT_SHIFT_DARF_RC4_8197F) +#define BITS_DARF_RC4_8197F (BIT_MASK_DARF_RC4_8197F << BIT_SHIFT_DARF_RC4_8197F) +#define BIT_CLEAR_DARF_RC4_8197F(x) ((x) & (~BITS_DARF_RC4_8197F)) +#define BIT_GET_DARF_RC4_8197F(x) (((x) >> BIT_SHIFT_DARF_RC4_8197F) & BIT_MASK_DARF_RC4_8197F) +#define BIT_SET_DARF_RC4_8197F(x, v) (BIT_CLEAR_DARF_RC4_8197F(x) | BIT_DARF_RC4_8197F(v)) + + +#define BIT_SHIFT_DARF_RC3_8197F 16 +#define BIT_MASK_DARF_RC3_8197F 0x1f +#define BIT_DARF_RC3_8197F(x) (((x) & BIT_MASK_DARF_RC3_8197F) << BIT_SHIFT_DARF_RC3_8197F) +#define BITS_DARF_RC3_8197F (BIT_MASK_DARF_RC3_8197F << BIT_SHIFT_DARF_RC3_8197F) +#define BIT_CLEAR_DARF_RC3_8197F(x) ((x) & (~BITS_DARF_RC3_8197F)) +#define BIT_GET_DARF_RC3_8197F(x) (((x) >> BIT_SHIFT_DARF_RC3_8197F) & BIT_MASK_DARF_RC3_8197F) +#define BIT_SET_DARF_RC3_8197F(x, v) (BIT_CLEAR_DARF_RC3_8197F(x) | BIT_DARF_RC3_8197F(v)) + + +#define BIT_SHIFT_DARF_RC2_8197F 8 +#define BIT_MASK_DARF_RC2_8197F 0x1f +#define BIT_DARF_RC2_8197F(x) (((x) & BIT_MASK_DARF_RC2_8197F) << BIT_SHIFT_DARF_RC2_8197F) +#define BITS_DARF_RC2_8197F (BIT_MASK_DARF_RC2_8197F << BIT_SHIFT_DARF_RC2_8197F) +#define BIT_CLEAR_DARF_RC2_8197F(x) ((x) & (~BITS_DARF_RC2_8197F)) +#define BIT_GET_DARF_RC2_8197F(x) (((x) >> BIT_SHIFT_DARF_RC2_8197F) & BIT_MASK_DARF_RC2_8197F) +#define BIT_SET_DARF_RC2_8197F(x, v) (BIT_CLEAR_DARF_RC2_8197F(x) | BIT_DARF_RC2_8197F(v)) + + +#define BIT_SHIFT_DARF_RC1_8197F 0 +#define BIT_MASK_DARF_RC1_8197F 0x1f +#define BIT_DARF_RC1_8197F(x) (((x) & BIT_MASK_DARF_RC1_8197F) << BIT_SHIFT_DARF_RC1_8197F) +#define BITS_DARF_RC1_8197F (BIT_MASK_DARF_RC1_8197F << BIT_SHIFT_DARF_RC1_8197F) +#define BIT_CLEAR_DARF_RC1_8197F(x) ((x) & (~BITS_DARF_RC1_8197F)) +#define BIT_GET_DARF_RC1_8197F(x) (((x) >> BIT_SHIFT_DARF_RC1_8197F) & BIT_MASK_DARF_RC1_8197F) +#define BIT_SET_DARF_RC1_8197F(x, v) (BIT_CLEAR_DARF_RC1_8197F(x) | BIT_DARF_RC1_8197F(v)) + + +/* 2 REG_RARFRC_8197F */ + +#define BIT_SHIFT_RARF_RC8_8197F (56 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC8_8197F 0x1f +#define BIT_RARF_RC8_8197F(x) (((x) & BIT_MASK_RARF_RC8_8197F) << BIT_SHIFT_RARF_RC8_8197F) +#define BITS_RARF_RC8_8197F (BIT_MASK_RARF_RC8_8197F << BIT_SHIFT_RARF_RC8_8197F) +#define BIT_CLEAR_RARF_RC8_8197F(x) ((x) & (~BITS_RARF_RC8_8197F)) +#define BIT_GET_RARF_RC8_8197F(x) (((x) >> BIT_SHIFT_RARF_RC8_8197F) & BIT_MASK_RARF_RC8_8197F) +#define BIT_SET_RARF_RC8_8197F(x, v) (BIT_CLEAR_RARF_RC8_8197F(x) | BIT_RARF_RC8_8197F(v)) + + +#define BIT_SHIFT_RARF_RC7_8197F (48 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC7_8197F 0x1f +#define BIT_RARF_RC7_8197F(x) (((x) & BIT_MASK_RARF_RC7_8197F) << BIT_SHIFT_RARF_RC7_8197F) +#define BITS_RARF_RC7_8197F (BIT_MASK_RARF_RC7_8197F << BIT_SHIFT_RARF_RC7_8197F) +#define BIT_CLEAR_RARF_RC7_8197F(x) ((x) & (~BITS_RARF_RC7_8197F)) +#define BIT_GET_RARF_RC7_8197F(x) (((x) >> BIT_SHIFT_RARF_RC7_8197F) & BIT_MASK_RARF_RC7_8197F) +#define BIT_SET_RARF_RC7_8197F(x, v) (BIT_CLEAR_RARF_RC7_8197F(x) | BIT_RARF_RC7_8197F(v)) + + +#define BIT_SHIFT_RARF_RC6_8197F (40 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC6_8197F 0x1f +#define BIT_RARF_RC6_8197F(x) (((x) & BIT_MASK_RARF_RC6_8197F) << BIT_SHIFT_RARF_RC6_8197F) +#define BITS_RARF_RC6_8197F (BIT_MASK_RARF_RC6_8197F << BIT_SHIFT_RARF_RC6_8197F) +#define BIT_CLEAR_RARF_RC6_8197F(x) ((x) & (~BITS_RARF_RC6_8197F)) +#define BIT_GET_RARF_RC6_8197F(x) (((x) >> BIT_SHIFT_RARF_RC6_8197F) & BIT_MASK_RARF_RC6_8197F) +#define BIT_SET_RARF_RC6_8197F(x, v) (BIT_CLEAR_RARF_RC6_8197F(x) | BIT_RARF_RC6_8197F(v)) + + +#define BIT_SHIFT_RARF_RC5_8197F (32 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC5_8197F 0x1f +#define BIT_RARF_RC5_8197F(x) (((x) & BIT_MASK_RARF_RC5_8197F) << BIT_SHIFT_RARF_RC5_8197F) +#define BITS_RARF_RC5_8197F (BIT_MASK_RARF_RC5_8197F << BIT_SHIFT_RARF_RC5_8197F) +#define BIT_CLEAR_RARF_RC5_8197F(x) ((x) & (~BITS_RARF_RC5_8197F)) +#define BIT_GET_RARF_RC5_8197F(x) (((x) >> BIT_SHIFT_RARF_RC5_8197F) & BIT_MASK_RARF_RC5_8197F) +#define BIT_SET_RARF_RC5_8197F(x, v) (BIT_CLEAR_RARF_RC5_8197F(x) | BIT_RARF_RC5_8197F(v)) + + +#define BIT_SHIFT_RARF_RC4_8197F 24 +#define BIT_MASK_RARF_RC4_8197F 0x1f +#define BIT_RARF_RC4_8197F(x) (((x) & BIT_MASK_RARF_RC4_8197F) << BIT_SHIFT_RARF_RC4_8197F) +#define BITS_RARF_RC4_8197F (BIT_MASK_RARF_RC4_8197F << BIT_SHIFT_RARF_RC4_8197F) +#define BIT_CLEAR_RARF_RC4_8197F(x) ((x) & (~BITS_RARF_RC4_8197F)) +#define BIT_GET_RARF_RC4_8197F(x) (((x) >> BIT_SHIFT_RARF_RC4_8197F) & BIT_MASK_RARF_RC4_8197F) +#define BIT_SET_RARF_RC4_8197F(x, v) (BIT_CLEAR_RARF_RC4_8197F(x) | BIT_RARF_RC4_8197F(v)) + + +#define BIT_SHIFT_RARF_RC3_8197F 16 +#define BIT_MASK_RARF_RC3_8197F 0x1f +#define BIT_RARF_RC3_8197F(x) (((x) & BIT_MASK_RARF_RC3_8197F) << BIT_SHIFT_RARF_RC3_8197F) +#define BITS_RARF_RC3_8197F (BIT_MASK_RARF_RC3_8197F << BIT_SHIFT_RARF_RC3_8197F) +#define BIT_CLEAR_RARF_RC3_8197F(x) ((x) & (~BITS_RARF_RC3_8197F)) +#define BIT_GET_RARF_RC3_8197F(x) (((x) >> BIT_SHIFT_RARF_RC3_8197F) & BIT_MASK_RARF_RC3_8197F) +#define BIT_SET_RARF_RC3_8197F(x, v) (BIT_CLEAR_RARF_RC3_8197F(x) | BIT_RARF_RC3_8197F(v)) + + +#define BIT_SHIFT_RARF_RC2_8197F 8 +#define BIT_MASK_RARF_RC2_8197F 0x1f +#define BIT_RARF_RC2_8197F(x) (((x) & BIT_MASK_RARF_RC2_8197F) << BIT_SHIFT_RARF_RC2_8197F) +#define BITS_RARF_RC2_8197F (BIT_MASK_RARF_RC2_8197F << BIT_SHIFT_RARF_RC2_8197F) +#define BIT_CLEAR_RARF_RC2_8197F(x) ((x) & (~BITS_RARF_RC2_8197F)) +#define BIT_GET_RARF_RC2_8197F(x) (((x) >> BIT_SHIFT_RARF_RC2_8197F) & BIT_MASK_RARF_RC2_8197F) +#define BIT_SET_RARF_RC2_8197F(x, v) (BIT_CLEAR_RARF_RC2_8197F(x) | BIT_RARF_RC2_8197F(v)) + + +#define BIT_SHIFT_RARF_RC1_8197F 0 +#define BIT_MASK_RARF_RC1_8197F 0x1f +#define BIT_RARF_RC1_8197F(x) (((x) & BIT_MASK_RARF_RC1_8197F) << BIT_SHIFT_RARF_RC1_8197F) +#define BITS_RARF_RC1_8197F (BIT_MASK_RARF_RC1_8197F << BIT_SHIFT_RARF_RC1_8197F) +#define BIT_CLEAR_RARF_RC1_8197F(x) ((x) & (~BITS_RARF_RC1_8197F)) +#define BIT_GET_RARF_RC1_8197F(x) (((x) >> BIT_SHIFT_RARF_RC1_8197F) & BIT_MASK_RARF_RC1_8197F) +#define BIT_SET_RARF_RC1_8197F(x, v) (BIT_CLEAR_RARF_RC1_8197F(x) | BIT_RARF_RC1_8197F(v)) + + +/* 2 REG_RRSR_8197F */ +#define BIT_EN_VHTBW_FALL_8197F BIT(31) +#define BIT_EN_HTBW_FALL_8197F BIT(30) + +#define BIT_SHIFT_RRSR_RSC_8197F 21 +#define BIT_MASK_RRSR_RSC_8197F 0x3 +#define BIT_RRSR_RSC_8197F(x) (((x) & BIT_MASK_RRSR_RSC_8197F) << BIT_SHIFT_RRSR_RSC_8197F) +#define BITS_RRSR_RSC_8197F (BIT_MASK_RRSR_RSC_8197F << BIT_SHIFT_RRSR_RSC_8197F) +#define BIT_CLEAR_RRSR_RSC_8197F(x) ((x) & (~BITS_RRSR_RSC_8197F)) +#define BIT_GET_RRSR_RSC_8197F(x) (((x) >> BIT_SHIFT_RRSR_RSC_8197F) & BIT_MASK_RRSR_RSC_8197F) +#define BIT_SET_RRSR_RSC_8197F(x, v) (BIT_CLEAR_RRSR_RSC_8197F(x) | BIT_RRSR_RSC_8197F(v)) + +#define BIT_RRSR_BW_8197F BIT(20) + +#define BIT_SHIFT_RRSC_BITMAP_8197F 0 +#define BIT_MASK_RRSC_BITMAP_8197F 0xfffff +#define BIT_RRSC_BITMAP_8197F(x) (((x) & BIT_MASK_RRSC_BITMAP_8197F) << BIT_SHIFT_RRSC_BITMAP_8197F) +#define BITS_RRSC_BITMAP_8197F (BIT_MASK_RRSC_BITMAP_8197F << BIT_SHIFT_RRSC_BITMAP_8197F) +#define BIT_CLEAR_RRSC_BITMAP_8197F(x) ((x) & (~BITS_RRSC_BITMAP_8197F)) +#define BIT_GET_RRSC_BITMAP_8197F(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8197F) & BIT_MASK_RRSC_BITMAP_8197F) +#define BIT_SET_RRSC_BITMAP_8197F(x, v) (BIT_CLEAR_RRSC_BITMAP_8197F(x) | BIT_RRSC_BITMAP_8197F(v)) + + +/* 2 REG_ARFR0_8197F */ + +#define BIT_SHIFT_ARFR0_V1_8197F 0 +#define BIT_MASK_ARFR0_V1_8197F 0xffffffffffffffffL +#define BIT_ARFR0_V1_8197F(x) (((x) & BIT_MASK_ARFR0_V1_8197F) << BIT_SHIFT_ARFR0_V1_8197F) +#define BITS_ARFR0_V1_8197F (BIT_MASK_ARFR0_V1_8197F << BIT_SHIFT_ARFR0_V1_8197F) +#define BIT_CLEAR_ARFR0_V1_8197F(x) ((x) & (~BITS_ARFR0_V1_8197F)) +#define BIT_GET_ARFR0_V1_8197F(x) (((x) >> BIT_SHIFT_ARFR0_V1_8197F) & BIT_MASK_ARFR0_V1_8197F) +#define BIT_SET_ARFR0_V1_8197F(x, v) (BIT_CLEAR_ARFR0_V1_8197F(x) | BIT_ARFR0_V1_8197F(v)) + + +/* 2 REG_ARFR1_V1_8197F */ + +#define BIT_SHIFT_ARFR1_V1_8197F 0 +#define BIT_MASK_ARFR1_V1_8197F 0xffffffffffffffffL +#define BIT_ARFR1_V1_8197F(x) (((x) & BIT_MASK_ARFR1_V1_8197F) << BIT_SHIFT_ARFR1_V1_8197F) +#define BITS_ARFR1_V1_8197F (BIT_MASK_ARFR1_V1_8197F << BIT_SHIFT_ARFR1_V1_8197F) +#define BIT_CLEAR_ARFR1_V1_8197F(x) ((x) & (~BITS_ARFR1_V1_8197F)) +#define BIT_GET_ARFR1_V1_8197F(x) (((x) >> BIT_SHIFT_ARFR1_V1_8197F) & BIT_MASK_ARFR1_V1_8197F) +#define BIT_SET_ARFR1_V1_8197F(x, v) (BIT_CLEAR_ARFR1_V1_8197F(x) | BIT_ARFR1_V1_8197F(v)) + + +/* 2 REG_CCK_CHECK_8197F */ +#define BIT_CHECK_CCK_EN_8197F BIT(7) +#define BIT_EN_BCN_PKT_REL_8197F BIT(6) +#define BIT_BCN_PORT_SEL_8197F BIT(5) +#define BIT_MOREDATA_BYPASS_8197F BIT(4) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_8197F BIT(3) +#define BIT_R_EN_SET_MOREDATA_8197F BIT(2) +#define BIT__R_DIS_CLEAR_MACID_RELEASE_8197F BIT(1) +#define BIT__R_MACID_RELEASE_EN_8197F BIT(0) + +/* 2 REG_AMPDU_MAX_TIME_V1_8197F */ + +#define BIT_SHIFT_AMPDU_MAX_TIME_8197F 0 +#define BIT_MASK_AMPDU_MAX_TIME_8197F 0xff +#define BIT_AMPDU_MAX_TIME_8197F(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8197F) << BIT_SHIFT_AMPDU_MAX_TIME_8197F) +#define BITS_AMPDU_MAX_TIME_8197F (BIT_MASK_AMPDU_MAX_TIME_8197F << BIT_SHIFT_AMPDU_MAX_TIME_8197F) +#define BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) ((x) & (~BITS_AMPDU_MAX_TIME_8197F)) +#define BIT_GET_AMPDU_MAX_TIME_8197F(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8197F) & BIT_MASK_AMPDU_MAX_TIME_8197F) +#define BIT_SET_AMPDU_MAX_TIME_8197F(x, v) (BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) | BIT_AMPDU_MAX_TIME_8197F(v)) + + +/* 2 REG_BCNQ1_BDNY_V1_8197F */ + +#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F 0 +#define BIT_MASK_BCNQ1_PGBNDY_V1_8197F 0xfff +#define BIT_BCNQ1_PGBNDY_V1_8197F(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8197F) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) +#define BITS_BCNQ1_PGBNDY_V1_8197F (BIT_MASK_BCNQ1_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) +#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8197F)) +#define BIT_GET_BCNQ1_PGBNDY_V1_8197F(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) & BIT_MASK_BCNQ1_PGBNDY_V1_8197F) +#define BIT_SET_BCNQ1_PGBNDY_V1_8197F(x, v) (BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) | BIT_BCNQ1_PGBNDY_V1_8197F(v)) + + +/* 2 REG_AMPDU_MAX_LENGTH_8197F */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_8197F 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_8197F 0xffffffffL +#define BIT_AMPDU_MAX_LENGTH_8197F(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8197F) << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) +#define BITS_AMPDU_MAX_LENGTH_8197F (BIT_MASK_AMPDU_MAX_LENGTH_8197F << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_8197F)) +#define BIT_GET_AMPDU_MAX_LENGTH_8197F(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) & BIT_MASK_AMPDU_MAX_LENGTH_8197F) +#define BIT_SET_AMPDU_MAX_LENGTH_8197F(x, v) (BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) | BIT_AMPDU_MAX_LENGTH_8197F(v)) + + +/* 2 REG_ACQ_STOP_8197F */ +#define BIT_AC7Q_STOP_8197F BIT(7) +#define BIT_AC6Q_STOP_8197F BIT(6) +#define BIT_AC5Q_STOP_8197F BIT(5) +#define BIT_AC4Q_STOP_8197F BIT(4) +#define BIT_AC3Q_STOP_8197F BIT(3) +#define BIT_AC2Q_STOP_8197F BIT(2) +#define BIT_AC1Q_STOP_8197F BIT(1) +#define BIT_AC0Q_STOP_8197F BIT(0) + +/* 2 REG_NDPA_RATE_8197F */ + +#define BIT_SHIFT_R_NDPA_RATE_V1_8197F 0 +#define BIT_MASK_R_NDPA_RATE_V1_8197F 0xff +#define BIT_R_NDPA_RATE_V1_8197F(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8197F) << BIT_SHIFT_R_NDPA_RATE_V1_8197F) +#define BITS_R_NDPA_RATE_V1_8197F (BIT_MASK_R_NDPA_RATE_V1_8197F << BIT_SHIFT_R_NDPA_RATE_V1_8197F) +#define BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) ((x) & (~BITS_R_NDPA_RATE_V1_8197F)) +#define BIT_GET_R_NDPA_RATE_V1_8197F(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8197F) & BIT_MASK_R_NDPA_RATE_V1_8197F) +#define BIT_SET_R_NDPA_RATE_V1_8197F(x, v) (BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) | BIT_R_NDPA_RATE_V1_8197F(v)) + + +/* 2 REG_TX_HANG_CTRL_8197F */ +#define BIT_R_EN_GNT_BT_AWAKE_8197F BIT(3) +#define BIT_EN_EOF_V1_8197F BIT(2) +#define BIT_DIS_OQT_BLOCK_8197F BIT(1) +#define BIT_SEARCH_QUEUE_EN_8197F BIT(0) + +/* 2 REG_NDPA_OPT_CTRL_8197F */ +#define BIT_R_DIS_MACID_RELEASE_RTY_8197F BIT(5) + +#define BIT_SHIFT_BW_SIGTA_8197F 3 +#define BIT_MASK_BW_SIGTA_8197F 0x3 +#define BIT_BW_SIGTA_8197F(x) (((x) & BIT_MASK_BW_SIGTA_8197F) << BIT_SHIFT_BW_SIGTA_8197F) +#define BITS_BW_SIGTA_8197F (BIT_MASK_BW_SIGTA_8197F << BIT_SHIFT_BW_SIGTA_8197F) +#define BIT_CLEAR_BW_SIGTA_8197F(x) ((x) & (~BITS_BW_SIGTA_8197F)) +#define BIT_GET_BW_SIGTA_8197F(x) (((x) >> BIT_SHIFT_BW_SIGTA_8197F) & BIT_MASK_BW_SIGTA_8197F) +#define BIT_SET_BW_SIGTA_8197F(x, v) (BIT_CLEAR_BW_SIGTA_8197F(x) | BIT_BW_SIGTA_8197F(v)) + +#define BIT_EN_BAR_SIGTA_8197F BIT(2) + +#define BIT_SHIFT_R_NDPA_BW_8197F 0 +#define BIT_MASK_R_NDPA_BW_8197F 0x3 +#define BIT_R_NDPA_BW_8197F(x) (((x) & BIT_MASK_R_NDPA_BW_8197F) << BIT_SHIFT_R_NDPA_BW_8197F) +#define BITS_R_NDPA_BW_8197F (BIT_MASK_R_NDPA_BW_8197F << BIT_SHIFT_R_NDPA_BW_8197F) +#define BIT_CLEAR_R_NDPA_BW_8197F(x) ((x) & (~BITS_R_NDPA_BW_8197F)) +#define BIT_GET_R_NDPA_BW_8197F(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8197F) & BIT_MASK_R_NDPA_BW_8197F) +#define BIT_SET_R_NDPA_BW_8197F(x, v) (BIT_CLEAR_R_NDPA_BW_8197F(x) | BIT_R_NDPA_BW_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_RD_RESP_PKT_TH_8197F */ + +#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F 0 +#define BIT_MASK_RD_RESP_PKT_TH_V1_8197F 0x3f +#define BIT_RD_RESP_PKT_TH_V1_8197F(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8197F) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) +#define BITS_RD_RESP_PKT_TH_V1_8197F (BIT_MASK_RD_RESP_PKT_TH_V1_8197F << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) ((x) & (~BITS_RD_RESP_PKT_TH_V1_8197F)) +#define BIT_GET_RD_RESP_PKT_TH_V1_8197F(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) & BIT_MASK_RD_RESP_PKT_TH_V1_8197F) +#define BIT_SET_RD_RESP_PKT_TH_V1_8197F(x, v) (BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) | BIT_RD_RESP_PKT_TH_V1_8197F(v)) + + +/* 2 REG_CMDQ_INFO_8197F */ + +#define BIT_SHIFT_PKT_NUM_8197F 23 +#define BIT_MASK_PKT_NUM_8197F 0x1ff +#define BIT_PKT_NUM_8197F(x) (((x) & BIT_MASK_PKT_NUM_8197F) << BIT_SHIFT_PKT_NUM_8197F) +#define BITS_PKT_NUM_8197F (BIT_MASK_PKT_NUM_8197F << BIT_SHIFT_PKT_NUM_8197F) +#define BIT_CLEAR_PKT_NUM_8197F(x) ((x) & (~BITS_PKT_NUM_8197F)) +#define BIT_GET_PKT_NUM_8197F(x) (((x) >> BIT_SHIFT_PKT_NUM_8197F) & BIT_MASK_PKT_NUM_8197F) +#define BIT_SET_PKT_NUM_8197F(x, v) (BIT_CLEAR_PKT_NUM_8197F(x) | BIT_PKT_NUM_8197F(v)) + +#define BIT_TIDEMPTY_CMDQ_V1_8197F BIT(22) + +#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F 11 +#define BIT_MASK_TAIL_PKT_CMDQ_V2_8197F 0x7ff +#define BIT_TAIL_PKT_CMDQ_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8197F) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) +#define BITS_TAIL_PKT_CMDQ_V2_8197F (BIT_MASK_TAIL_PKT_CMDQ_V2_8197F << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_CMDQ_V2_8197F)) +#define BIT_GET_TAIL_PKT_CMDQ_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) & BIT_MASK_TAIL_PKT_CMDQ_V2_8197F) +#define BIT_SET_TAIL_PKT_CMDQ_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) | BIT_TAIL_PKT_CMDQ_V2_8197F(v)) + + +#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F 0 +#define BIT_MASK_HEAD_PKT_CMDQ_V1_8197F 0x7ff +#define BIT_HEAD_PKT_CMDQ_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8197F) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) +#define BITS_HEAD_PKT_CMDQ_V1_8197F (BIT_MASK_HEAD_PKT_CMDQ_V1_8197F << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8197F)) +#define BIT_GET_HEAD_PKT_CMDQ_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) & BIT_MASK_HEAD_PKT_CMDQ_V1_8197F) +#define BIT_SET_HEAD_PKT_CMDQ_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) | BIT_HEAD_PKT_CMDQ_V1_8197F(v)) + + +/* 2 REG_Q4_INFO_8197F */ + +#define BIT_SHIFT_QUEUEMACID_Q4_V1_8197F 25 +#define BIT_MASK_QUEUEMACID_Q4_V1_8197F 0x7f +#define BIT_QUEUEMACID_Q4_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) +#define BITS_QUEUEMACID_Q4_V1_8197F (BIT_MASK_QUEUEMACID_Q4_V1_8197F << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q4_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q4_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) & BIT_MASK_QUEUEMACID_Q4_V1_8197F) +#define BIT_SET_QUEUEMACID_Q4_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) | BIT_QUEUEMACID_Q4_V1_8197F(v)) + + +#define BIT_SHIFT_QUEUEAC_Q4_V1_8197F 23 +#define BIT_MASK_QUEUEAC_Q4_V1_8197F 0x3 +#define BIT_QUEUEAC_Q4_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8197F) << BIT_SHIFT_QUEUEAC_Q4_V1_8197F) +#define BITS_QUEUEAC_Q4_V1_8197F (BIT_MASK_QUEUEAC_Q4_V1_8197F << BIT_SHIFT_QUEUEAC_Q4_V1_8197F) +#define BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8197F)) +#define BIT_GET_QUEUEAC_Q4_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8197F) & BIT_MASK_QUEUEAC_Q4_V1_8197F) +#define BIT_SET_QUEUEAC_Q4_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) | BIT_QUEUEAC_Q4_V1_8197F(v)) + +#define BIT_TIDEMPTY_Q4_V1_8197F BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q4_V2_8197F 11 +#define BIT_MASK_TAIL_PKT_Q4_V2_8197F 0x7ff +#define BIT_TAIL_PKT_Q4_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) +#define BITS_TAIL_PKT_Q4_V2_8197F (BIT_MASK_TAIL_PKT_Q4_V2_8197F << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8197F)) +#define BIT_GET_TAIL_PKT_Q4_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) & BIT_MASK_TAIL_PKT_Q4_V2_8197F) +#define BIT_SET_TAIL_PKT_Q4_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) | BIT_TAIL_PKT_Q4_V2_8197F(v)) + + +#define BIT_SHIFT_HEAD_PKT_Q4_V1_8197F 0 +#define BIT_MASK_HEAD_PKT_Q4_V1_8197F 0x7ff +#define BIT_HEAD_PKT_Q4_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) +#define BITS_HEAD_PKT_Q4_V1_8197F (BIT_MASK_HEAD_PKT_Q4_V1_8197F << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8197F)) +#define BIT_GET_HEAD_PKT_Q4_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) & BIT_MASK_HEAD_PKT_Q4_V1_8197F) +#define BIT_SET_HEAD_PKT_Q4_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) | BIT_HEAD_PKT_Q4_V1_8197F(v)) + + +/* 2 REG_Q5_INFO_8197F */ + +#define BIT_SHIFT_QUEUEMACID_Q5_V1_8197F 25 +#define BIT_MASK_QUEUEMACID_Q5_V1_8197F 0x7f +#define BIT_QUEUEMACID_Q5_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) +#define BITS_QUEUEMACID_Q5_V1_8197F (BIT_MASK_QUEUEMACID_Q5_V1_8197F << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q5_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q5_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) & BIT_MASK_QUEUEMACID_Q5_V1_8197F) +#define BIT_SET_QUEUEMACID_Q5_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) | BIT_QUEUEMACID_Q5_V1_8197F(v)) + + +#define BIT_SHIFT_QUEUEAC_Q5_V1_8197F 23 +#define BIT_MASK_QUEUEAC_Q5_V1_8197F 0x3 +#define BIT_QUEUEAC_Q5_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8197F) << BIT_SHIFT_QUEUEAC_Q5_V1_8197F) +#define BITS_QUEUEAC_Q5_V1_8197F (BIT_MASK_QUEUEAC_Q5_V1_8197F << BIT_SHIFT_QUEUEAC_Q5_V1_8197F) +#define BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8197F)) +#define BIT_GET_QUEUEAC_Q5_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8197F) & BIT_MASK_QUEUEAC_Q5_V1_8197F) +#define BIT_SET_QUEUEAC_Q5_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) | BIT_QUEUEAC_Q5_V1_8197F(v)) + +#define BIT_TIDEMPTY_Q5_V1_8197F BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q5_V2_8197F 11 +#define BIT_MASK_TAIL_PKT_Q5_V2_8197F 0x7ff +#define BIT_TAIL_PKT_Q5_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) +#define BITS_TAIL_PKT_Q5_V2_8197F (BIT_MASK_TAIL_PKT_Q5_V2_8197F << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8197F)) +#define BIT_GET_TAIL_PKT_Q5_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) & BIT_MASK_TAIL_PKT_Q5_V2_8197F) +#define BIT_SET_TAIL_PKT_Q5_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) | BIT_TAIL_PKT_Q5_V2_8197F(v)) + + +#define BIT_SHIFT_HEAD_PKT_Q5_V1_8197F 0 +#define BIT_MASK_HEAD_PKT_Q5_V1_8197F 0x7ff +#define BIT_HEAD_PKT_Q5_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) +#define BITS_HEAD_PKT_Q5_V1_8197F (BIT_MASK_HEAD_PKT_Q5_V1_8197F << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8197F)) +#define BIT_GET_HEAD_PKT_Q5_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) & BIT_MASK_HEAD_PKT_Q5_V1_8197F) +#define BIT_SET_HEAD_PKT_Q5_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) | BIT_HEAD_PKT_Q5_V1_8197F(v)) + + +/* 2 REG_Q6_INFO_8197F */ + +#define BIT_SHIFT_QUEUEMACID_Q6_V1_8197F 25 +#define BIT_MASK_QUEUEMACID_Q6_V1_8197F 0x7f +#define BIT_QUEUEMACID_Q6_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) +#define BITS_QUEUEMACID_Q6_V1_8197F (BIT_MASK_QUEUEMACID_Q6_V1_8197F << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q6_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q6_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) & BIT_MASK_QUEUEMACID_Q6_V1_8197F) +#define BIT_SET_QUEUEMACID_Q6_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) | BIT_QUEUEMACID_Q6_V1_8197F(v)) + + +#define BIT_SHIFT_QUEUEAC_Q6_V1_8197F 23 +#define BIT_MASK_QUEUEAC_Q6_V1_8197F 0x3 +#define BIT_QUEUEAC_Q6_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8197F) << BIT_SHIFT_QUEUEAC_Q6_V1_8197F) +#define BITS_QUEUEAC_Q6_V1_8197F (BIT_MASK_QUEUEAC_Q6_V1_8197F << BIT_SHIFT_QUEUEAC_Q6_V1_8197F) +#define BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8197F)) +#define BIT_GET_QUEUEAC_Q6_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8197F) & BIT_MASK_QUEUEAC_Q6_V1_8197F) +#define BIT_SET_QUEUEAC_Q6_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) | BIT_QUEUEAC_Q6_V1_8197F(v)) + +#define BIT_TIDEMPTY_Q6_V1_8197F BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q6_V2_8197F 11 +#define BIT_MASK_TAIL_PKT_Q6_V2_8197F 0x7ff +#define BIT_TAIL_PKT_Q6_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) +#define BITS_TAIL_PKT_Q6_V2_8197F (BIT_MASK_TAIL_PKT_Q6_V2_8197F << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8197F)) +#define BIT_GET_TAIL_PKT_Q6_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) & BIT_MASK_TAIL_PKT_Q6_V2_8197F) +#define BIT_SET_TAIL_PKT_Q6_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) | BIT_TAIL_PKT_Q6_V2_8197F(v)) + + +#define BIT_SHIFT_HEAD_PKT_Q6_V1_8197F 0 +#define BIT_MASK_HEAD_PKT_Q6_V1_8197F 0x7ff +#define BIT_HEAD_PKT_Q6_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) +#define BITS_HEAD_PKT_Q6_V1_8197F (BIT_MASK_HEAD_PKT_Q6_V1_8197F << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8197F)) +#define BIT_GET_HEAD_PKT_Q6_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) & BIT_MASK_HEAD_PKT_Q6_V1_8197F) +#define BIT_SET_HEAD_PKT_Q6_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) | BIT_HEAD_PKT_Q6_V1_8197F(v)) + + +/* 2 REG_Q7_INFO_8197F */ + +#define BIT_SHIFT_QUEUEMACID_Q7_V1_8197F 25 +#define BIT_MASK_QUEUEMACID_Q7_V1_8197F 0x7f +#define BIT_QUEUEMACID_Q7_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) +#define BITS_QUEUEMACID_Q7_V1_8197F (BIT_MASK_QUEUEMACID_Q7_V1_8197F << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q7_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q7_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) & BIT_MASK_QUEUEMACID_Q7_V1_8197F) +#define BIT_SET_QUEUEMACID_Q7_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) | BIT_QUEUEMACID_Q7_V1_8197F(v)) + + +#define BIT_SHIFT_QUEUEAC_Q7_V1_8197F 23 +#define BIT_MASK_QUEUEAC_Q7_V1_8197F 0x3 +#define BIT_QUEUEAC_Q7_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8197F) << BIT_SHIFT_QUEUEAC_Q7_V1_8197F) +#define BITS_QUEUEAC_Q7_V1_8197F (BIT_MASK_QUEUEAC_Q7_V1_8197F << BIT_SHIFT_QUEUEAC_Q7_V1_8197F) +#define BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8197F)) +#define BIT_GET_QUEUEAC_Q7_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8197F) & BIT_MASK_QUEUEAC_Q7_V1_8197F) +#define BIT_SET_QUEUEAC_Q7_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) | BIT_QUEUEAC_Q7_V1_8197F(v)) + +#define BIT_TIDEMPTY_Q7_V1_8197F BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q7_V2_8197F 11 +#define BIT_MASK_TAIL_PKT_Q7_V2_8197F 0x7ff +#define BIT_TAIL_PKT_Q7_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) +#define BITS_TAIL_PKT_Q7_V2_8197F (BIT_MASK_TAIL_PKT_Q7_V2_8197F << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8197F)) +#define BIT_GET_TAIL_PKT_Q7_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) & BIT_MASK_TAIL_PKT_Q7_V2_8197F) +#define BIT_SET_TAIL_PKT_Q7_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) | BIT_TAIL_PKT_Q7_V2_8197F(v)) + + +#define BIT_SHIFT_HEAD_PKT_Q7_V1_8197F 0 +#define BIT_MASK_HEAD_PKT_Q7_V1_8197F 0x7ff +#define BIT_HEAD_PKT_Q7_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) +#define BITS_HEAD_PKT_Q7_V1_8197F (BIT_MASK_HEAD_PKT_Q7_V1_8197F << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8197F)) +#define BIT_GET_HEAD_PKT_Q7_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) & BIT_MASK_HEAD_PKT_Q7_V1_8197F) +#define BIT_SET_HEAD_PKT_Q7_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) | BIT_HEAD_PKT_Q7_V1_8197F(v)) + + +/* 2 REG_WMAC_LBK_BUF_HD_V1_8197F */ + +#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F 0 +#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F 0xfff +#define BIT_WMAC_LBK_BUF_HEAD_V1_8197F(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) +#define BITS_WMAC_LBK_BUF_HEAD_V1_8197F (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8197F)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8197F(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8197F(x, v) (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) | BIT_WMAC_LBK_BUF_HEAD_V1_8197F(v)) + + +/* 2 REG_MGQ_BDNY_V1_8197F */ + +#define BIT_SHIFT_MGQ_PGBNDY_V1_8197F 0 +#define BIT_MASK_MGQ_PGBNDY_V1_8197F 0xfff +#define BIT_MGQ_PGBNDY_V1_8197F(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8197F) << BIT_SHIFT_MGQ_PGBNDY_V1_8197F) +#define BITS_MGQ_PGBNDY_V1_8197F (BIT_MASK_MGQ_PGBNDY_V1_8197F << BIT_SHIFT_MGQ_PGBNDY_V1_8197F) +#define BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8197F)) +#define BIT_GET_MGQ_PGBNDY_V1_8197F(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8197F) & BIT_MASK_MGQ_PGBNDY_V1_8197F) +#define BIT_SET_MGQ_PGBNDY_V1_8197F(x, v) (BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) | BIT_MGQ_PGBNDY_V1_8197F(v)) + + +/* 2 REG_TXRPT_CTRL_8197F */ + +#define BIT_SHIFT_TRXRPT_TIMER_TH_8197F 24 +#define BIT_MASK_TRXRPT_TIMER_TH_8197F 0xff +#define BIT_TRXRPT_TIMER_TH_8197F(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8197F) << BIT_SHIFT_TRXRPT_TIMER_TH_8197F) +#define BITS_TRXRPT_TIMER_TH_8197F (BIT_MASK_TRXRPT_TIMER_TH_8197F << BIT_SHIFT_TRXRPT_TIMER_TH_8197F) +#define BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8197F)) +#define BIT_GET_TRXRPT_TIMER_TH_8197F(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8197F) & BIT_MASK_TRXRPT_TIMER_TH_8197F) +#define BIT_SET_TRXRPT_TIMER_TH_8197F(x, v) (BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) | BIT_TRXRPT_TIMER_TH_8197F(v)) + + +#define BIT_SHIFT_TRXRPT_LEN_TH_8197F 16 +#define BIT_MASK_TRXRPT_LEN_TH_8197F 0xff +#define BIT_TRXRPT_LEN_TH_8197F(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8197F) << BIT_SHIFT_TRXRPT_LEN_TH_8197F) +#define BITS_TRXRPT_LEN_TH_8197F (BIT_MASK_TRXRPT_LEN_TH_8197F << BIT_SHIFT_TRXRPT_LEN_TH_8197F) +#define BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) ((x) & (~BITS_TRXRPT_LEN_TH_8197F)) +#define BIT_GET_TRXRPT_LEN_TH_8197F(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8197F) & BIT_MASK_TRXRPT_LEN_TH_8197F) +#define BIT_SET_TRXRPT_LEN_TH_8197F(x, v) (BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) | BIT_TRXRPT_LEN_TH_8197F(v)) + + +#define BIT_SHIFT_TRXRPT_READ_PTR_8197F 8 +#define BIT_MASK_TRXRPT_READ_PTR_8197F 0xff +#define BIT_TRXRPT_READ_PTR_8197F(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8197F) << BIT_SHIFT_TRXRPT_READ_PTR_8197F) +#define BITS_TRXRPT_READ_PTR_8197F (BIT_MASK_TRXRPT_READ_PTR_8197F << BIT_SHIFT_TRXRPT_READ_PTR_8197F) +#define BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) ((x) & (~BITS_TRXRPT_READ_PTR_8197F)) +#define BIT_GET_TRXRPT_READ_PTR_8197F(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8197F) & BIT_MASK_TRXRPT_READ_PTR_8197F) +#define BIT_SET_TRXRPT_READ_PTR_8197F(x, v) (BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) | BIT_TRXRPT_READ_PTR_8197F(v)) + + +#define BIT_SHIFT_TRXRPT_WRITE_PTR_8197F 0 +#define BIT_MASK_TRXRPT_WRITE_PTR_8197F 0xff +#define BIT_TRXRPT_WRITE_PTR_8197F(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8197F) << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) +#define BITS_TRXRPT_WRITE_PTR_8197F (BIT_MASK_TRXRPT_WRITE_PTR_8197F << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) +#define BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) ((x) & (~BITS_TRXRPT_WRITE_PTR_8197F)) +#define BIT_GET_TRXRPT_WRITE_PTR_8197F(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) & BIT_MASK_TRXRPT_WRITE_PTR_8197F) +#define BIT_SET_TRXRPT_WRITE_PTR_8197F(x, v) (BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) | BIT_TRXRPT_WRITE_PTR_8197F(v)) + + +/* 2 REG_INIRTS_RATE_SEL_8197F */ +#define BIT_LEAG_RTS_BW_DUP_8197F BIT(5) + +/* 2 REG_BASIC_CFEND_RATE_8197F */ + +#define BIT_SHIFT_BASIC_CFEND_RATE_8197F 0 +#define BIT_MASK_BASIC_CFEND_RATE_8197F 0x1f +#define BIT_BASIC_CFEND_RATE_8197F(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8197F) << BIT_SHIFT_BASIC_CFEND_RATE_8197F) +#define BITS_BASIC_CFEND_RATE_8197F (BIT_MASK_BASIC_CFEND_RATE_8197F << BIT_SHIFT_BASIC_CFEND_RATE_8197F) +#define BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) ((x) & (~BITS_BASIC_CFEND_RATE_8197F)) +#define BIT_GET_BASIC_CFEND_RATE_8197F(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8197F) & BIT_MASK_BASIC_CFEND_RATE_8197F) +#define BIT_SET_BASIC_CFEND_RATE_8197F(x, v) (BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) | BIT_BASIC_CFEND_RATE_8197F(v)) + + +/* 2 REG_STBC_CFEND_RATE_8197F */ + +#define BIT_SHIFT_STBC_CFEND_RATE_8197F 0 +#define BIT_MASK_STBC_CFEND_RATE_8197F 0x1f +#define BIT_STBC_CFEND_RATE_8197F(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8197F) << BIT_SHIFT_STBC_CFEND_RATE_8197F) +#define BITS_STBC_CFEND_RATE_8197F (BIT_MASK_STBC_CFEND_RATE_8197F << BIT_SHIFT_STBC_CFEND_RATE_8197F) +#define BIT_CLEAR_STBC_CFEND_RATE_8197F(x) ((x) & (~BITS_STBC_CFEND_RATE_8197F)) +#define BIT_GET_STBC_CFEND_RATE_8197F(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8197F) & BIT_MASK_STBC_CFEND_RATE_8197F) +#define BIT_SET_STBC_CFEND_RATE_8197F(x, v) (BIT_CLEAR_STBC_CFEND_RATE_8197F(x) | BIT_STBC_CFEND_RATE_8197F(v)) + + +/* 2 REG_DATA_SC_8197F */ + +#define BIT_SHIFT_TXSC_40M_8197F 4 +#define BIT_MASK_TXSC_40M_8197F 0xf +#define BIT_TXSC_40M_8197F(x) (((x) & BIT_MASK_TXSC_40M_8197F) << BIT_SHIFT_TXSC_40M_8197F) +#define BITS_TXSC_40M_8197F (BIT_MASK_TXSC_40M_8197F << BIT_SHIFT_TXSC_40M_8197F) +#define BIT_CLEAR_TXSC_40M_8197F(x) ((x) & (~BITS_TXSC_40M_8197F)) +#define BIT_GET_TXSC_40M_8197F(x) (((x) >> BIT_SHIFT_TXSC_40M_8197F) & BIT_MASK_TXSC_40M_8197F) +#define BIT_SET_TXSC_40M_8197F(x, v) (BIT_CLEAR_TXSC_40M_8197F(x) | BIT_TXSC_40M_8197F(v)) + + +#define BIT_SHIFT_TXSC_20M_8197F 0 +#define BIT_MASK_TXSC_20M_8197F 0xf +#define BIT_TXSC_20M_8197F(x) (((x) & BIT_MASK_TXSC_20M_8197F) << BIT_SHIFT_TXSC_20M_8197F) +#define BITS_TXSC_20M_8197F (BIT_MASK_TXSC_20M_8197F << BIT_SHIFT_TXSC_20M_8197F) +#define BIT_CLEAR_TXSC_20M_8197F(x) ((x) & (~BITS_TXSC_20M_8197F)) +#define BIT_GET_TXSC_20M_8197F(x) (((x) >> BIT_SHIFT_TXSC_20M_8197F) & BIT_MASK_TXSC_20M_8197F) +#define BIT_SET_TXSC_20M_8197F(x, v) (BIT_CLEAR_TXSC_20M_8197F(x) | BIT_TXSC_20M_8197F(v)) + + +/* 2 REG_MACID_SLEEP3_8197F */ + +#define BIT_SHIFT_MACID127_96_PKTSLEEP_8197F 0 +#define BIT_MASK_MACID127_96_PKTSLEEP_8197F 0xffffffffL +#define BIT_MACID127_96_PKTSLEEP_8197F(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8197F) << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) +#define BITS_MACID127_96_PKTSLEEP_8197F (BIT_MASK_MACID127_96_PKTSLEEP_8197F << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) +#define BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) ((x) & (~BITS_MACID127_96_PKTSLEEP_8197F)) +#define BIT_GET_MACID127_96_PKTSLEEP_8197F(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) & BIT_MASK_MACID127_96_PKTSLEEP_8197F) +#define BIT_SET_MACID127_96_PKTSLEEP_8197F(x, v) (BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) | BIT_MACID127_96_PKTSLEEP_8197F(v)) + + +/* 2 REG_MACID_SLEEP1_8197F */ + +#define BIT_SHIFT_MACID63_32_PKTSLEEP_8197F 0 +#define BIT_MASK_MACID63_32_PKTSLEEP_8197F 0xffffffffL +#define BIT_MACID63_32_PKTSLEEP_8197F(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8197F) << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) +#define BITS_MACID63_32_PKTSLEEP_8197F (BIT_MASK_MACID63_32_PKTSLEEP_8197F << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) +#define BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) ((x) & (~BITS_MACID63_32_PKTSLEEP_8197F)) +#define BIT_GET_MACID63_32_PKTSLEEP_8197F(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) & BIT_MASK_MACID63_32_PKTSLEEP_8197F) +#define BIT_SET_MACID63_32_PKTSLEEP_8197F(x, v) (BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) | BIT_MACID63_32_PKTSLEEP_8197F(v)) + + +/* 2 REG_ARFR2_V1_8197F */ + +#define BIT_SHIFT_ARFR2_V1_8197F 0 +#define BIT_MASK_ARFR2_V1_8197F 0xffffffffffffffffL +#define BIT_ARFR2_V1_8197F(x) (((x) & BIT_MASK_ARFR2_V1_8197F) << BIT_SHIFT_ARFR2_V1_8197F) +#define BITS_ARFR2_V1_8197F (BIT_MASK_ARFR2_V1_8197F << BIT_SHIFT_ARFR2_V1_8197F) +#define BIT_CLEAR_ARFR2_V1_8197F(x) ((x) & (~BITS_ARFR2_V1_8197F)) +#define BIT_GET_ARFR2_V1_8197F(x) (((x) >> BIT_SHIFT_ARFR2_V1_8197F) & BIT_MASK_ARFR2_V1_8197F) +#define BIT_SET_ARFR2_V1_8197F(x, v) (BIT_CLEAR_ARFR2_V1_8197F(x) | BIT_ARFR2_V1_8197F(v)) + + +/* 2 REG_ARFR3_V1_8197F */ + +#define BIT_SHIFT_ARFR3_V1_8197F 0 +#define BIT_MASK_ARFR3_V1_8197F 0xffffffffffffffffL +#define BIT_ARFR3_V1_8197F(x) (((x) & BIT_MASK_ARFR3_V1_8197F) << BIT_SHIFT_ARFR3_V1_8197F) +#define BITS_ARFR3_V1_8197F (BIT_MASK_ARFR3_V1_8197F << BIT_SHIFT_ARFR3_V1_8197F) +#define BIT_CLEAR_ARFR3_V1_8197F(x) ((x) & (~BITS_ARFR3_V1_8197F)) +#define BIT_GET_ARFR3_V1_8197F(x) (((x) >> BIT_SHIFT_ARFR3_V1_8197F) & BIT_MASK_ARFR3_V1_8197F) +#define BIT_SET_ARFR3_V1_8197F(x, v) (BIT_CLEAR_ARFR3_V1_8197F(x) | BIT_ARFR3_V1_8197F(v)) + + +/* 2 REG_ARFR4_8197F */ + +#define BIT_SHIFT_ARFR4_8197F 0 +#define BIT_MASK_ARFR4_8197F 0xffffffffffffffffL +#define BIT_ARFR4_8197F(x) (((x) & BIT_MASK_ARFR4_8197F) << BIT_SHIFT_ARFR4_8197F) +#define BITS_ARFR4_8197F (BIT_MASK_ARFR4_8197F << BIT_SHIFT_ARFR4_8197F) +#define BIT_CLEAR_ARFR4_8197F(x) ((x) & (~BITS_ARFR4_8197F)) +#define BIT_GET_ARFR4_8197F(x) (((x) >> BIT_SHIFT_ARFR4_8197F) & BIT_MASK_ARFR4_8197F) +#define BIT_SET_ARFR4_8197F(x, v) (BIT_CLEAR_ARFR4_8197F(x) | BIT_ARFR4_8197F(v)) + + +/* 2 REG_ARFR5_8197F */ + +#define BIT_SHIFT_ARFR5_8197F 0 +#define BIT_MASK_ARFR5_8197F 0xffffffffffffffffL +#define BIT_ARFR5_8197F(x) (((x) & BIT_MASK_ARFR5_8197F) << BIT_SHIFT_ARFR5_8197F) +#define BITS_ARFR5_8197F (BIT_MASK_ARFR5_8197F << BIT_SHIFT_ARFR5_8197F) +#define BIT_CLEAR_ARFR5_8197F(x) ((x) & (~BITS_ARFR5_8197F)) +#define BIT_GET_ARFR5_8197F(x) (((x) >> BIT_SHIFT_ARFR5_8197F) & BIT_MASK_ARFR5_8197F) +#define BIT_SET_ARFR5_8197F(x, v) (BIT_CLEAR_ARFR5_8197F(x) | BIT_ARFR5_8197F(v)) + + +/* 2 REG_TXRPT_START_OFFSET_8197F */ +#define BIT_SHCUT_PARSE_DASA_8197F BIT(25) +#define BIT_SHCUT_BYPASS_8197F BIT(24) +#define BIT__R_RPTFIFO_1K_8197F BIT(16) + +#define BIT_SHIFT_MACID_CTRL_OFFSET_8197F 8 +#define BIT_MASK_MACID_CTRL_OFFSET_8197F 0xff +#define BIT_MACID_CTRL_OFFSET_8197F(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8197F) << BIT_SHIFT_MACID_CTRL_OFFSET_8197F) +#define BITS_MACID_CTRL_OFFSET_8197F (BIT_MASK_MACID_CTRL_OFFSET_8197F << BIT_SHIFT_MACID_CTRL_OFFSET_8197F) +#define BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) ((x) & (~BITS_MACID_CTRL_OFFSET_8197F)) +#define BIT_GET_MACID_CTRL_OFFSET_8197F(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8197F) & BIT_MASK_MACID_CTRL_OFFSET_8197F) +#define BIT_SET_MACID_CTRL_OFFSET_8197F(x, v) (BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) | BIT_MACID_CTRL_OFFSET_8197F(v)) + + +#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F 0 +#define BIT_MASK_AMPDU_TXRPT_OFFSET_8197F 0xff +#define BIT_AMPDU_TXRPT_OFFSET_8197F(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8197F) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) +#define BITS_AMPDU_TXRPT_OFFSET_8197F (BIT_MASK_AMPDU_TXRPT_OFFSET_8197F << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8197F)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_8197F(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) & BIT_MASK_AMPDU_TXRPT_OFFSET_8197F) +#define BIT_SET_AMPDU_TXRPT_OFFSET_8197F(x, v) (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) | BIT_AMPDU_TXRPT_OFFSET_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_POWER_STAGE1_8197F */ +#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8197F BIT(31) +#define BIT_PTA_WL_PRI_MASK_BCNQ_8197F BIT(30) +#define BIT_PTA_WL_PRI_MASK_HIQ_8197F BIT(29) +#define BIT_PTA_WL_PRI_MASK_MGQ_8197F BIT(28) +#define BIT_PTA_WL_PRI_MASK_BK_8197F BIT(27) +#define BIT_PTA_WL_PRI_MASK_BE_8197F BIT(26) +#define BIT_PTA_WL_PRI_MASK_VI_8197F BIT(25) +#define BIT_PTA_WL_PRI_MASK_VO_8197F BIT(24) + +#define BIT_SHIFT_POWER_STAGE1_8197F 0 +#define BIT_MASK_POWER_STAGE1_8197F 0xffffff +#define BIT_POWER_STAGE1_8197F(x) (((x) & BIT_MASK_POWER_STAGE1_8197F) << BIT_SHIFT_POWER_STAGE1_8197F) +#define BITS_POWER_STAGE1_8197F (BIT_MASK_POWER_STAGE1_8197F << BIT_SHIFT_POWER_STAGE1_8197F) +#define BIT_CLEAR_POWER_STAGE1_8197F(x) ((x) & (~BITS_POWER_STAGE1_8197F)) +#define BIT_GET_POWER_STAGE1_8197F(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8197F) & BIT_MASK_POWER_STAGE1_8197F) +#define BIT_SET_POWER_STAGE1_8197F(x, v) (BIT_CLEAR_POWER_STAGE1_8197F(x) | BIT_POWER_STAGE1_8197F(v)) + + +/* 2 REG_POWER_STAGE2_8197F */ +#define BIT__R_CTRL_PKT_POW_ADJ_8197F BIT(24) + +#define BIT_SHIFT_POWER_STAGE2_8197F 0 +#define BIT_MASK_POWER_STAGE2_8197F 0xffffff +#define BIT_POWER_STAGE2_8197F(x) (((x) & BIT_MASK_POWER_STAGE2_8197F) << BIT_SHIFT_POWER_STAGE2_8197F) +#define BITS_POWER_STAGE2_8197F (BIT_MASK_POWER_STAGE2_8197F << BIT_SHIFT_POWER_STAGE2_8197F) +#define BIT_CLEAR_POWER_STAGE2_8197F(x) ((x) & (~BITS_POWER_STAGE2_8197F)) +#define BIT_GET_POWER_STAGE2_8197F(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8197F) & BIT_MASK_POWER_STAGE2_8197F) +#define BIT_SET_POWER_STAGE2_8197F(x, v) (BIT_CLEAR_POWER_STAGE2_8197F(x) | BIT_POWER_STAGE2_8197F(v)) + + +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8197F */ + +#define BIT_SHIFT_PAD_NUM_THRES_8197F 24 +#define BIT_MASK_PAD_NUM_THRES_8197F 0x3f +#define BIT_PAD_NUM_THRES_8197F(x) (((x) & BIT_MASK_PAD_NUM_THRES_8197F) << BIT_SHIFT_PAD_NUM_THRES_8197F) +#define BITS_PAD_NUM_THRES_8197F (BIT_MASK_PAD_NUM_THRES_8197F << BIT_SHIFT_PAD_NUM_THRES_8197F) +#define BIT_CLEAR_PAD_NUM_THRES_8197F(x) ((x) & (~BITS_PAD_NUM_THRES_8197F)) +#define BIT_GET_PAD_NUM_THRES_8197F(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8197F) & BIT_MASK_PAD_NUM_THRES_8197F) +#define BIT_SET_PAD_NUM_THRES_8197F(x, v) (BIT_CLEAR_PAD_NUM_THRES_8197F(x) | BIT_PAD_NUM_THRES_8197F(v)) + +#define BIT_R_DMA_THIS_QUEUE_BK_8197F BIT(23) +#define BIT_R_DMA_THIS_QUEUE_BE_8197F BIT(22) +#define BIT_R_DMA_THIS_QUEUE_VI_8197F BIT(21) +#define BIT_R_DMA_THIS_QUEUE_VO_8197F BIT(20) + +#define BIT_SHIFT_R_TOTAL_LEN_TH_8197F 8 +#define BIT_MASK_R_TOTAL_LEN_TH_8197F 0xfff +#define BIT_R_TOTAL_LEN_TH_8197F(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8197F) << BIT_SHIFT_R_TOTAL_LEN_TH_8197F) +#define BITS_R_TOTAL_LEN_TH_8197F (BIT_MASK_R_TOTAL_LEN_TH_8197F << BIT_SHIFT_R_TOTAL_LEN_TH_8197F) +#define BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8197F)) +#define BIT_GET_R_TOTAL_LEN_TH_8197F(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8197F) & BIT_MASK_R_TOTAL_LEN_TH_8197F) +#define BIT_SET_R_TOTAL_LEN_TH_8197F(x, v) (BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) | BIT_R_TOTAL_LEN_TH_8197F(v)) + +#define BIT_EN_NEW_EARLY_8197F BIT(7) +#define BIT_PRE_TX_CMD_8197F BIT(6) + +#define BIT_SHIFT_NUM_SCL_EN_8197F 4 +#define BIT_MASK_NUM_SCL_EN_8197F 0x3 +#define BIT_NUM_SCL_EN_8197F(x) (((x) & BIT_MASK_NUM_SCL_EN_8197F) << BIT_SHIFT_NUM_SCL_EN_8197F) +#define BITS_NUM_SCL_EN_8197F (BIT_MASK_NUM_SCL_EN_8197F << BIT_SHIFT_NUM_SCL_EN_8197F) +#define BIT_CLEAR_NUM_SCL_EN_8197F(x) ((x) & (~BITS_NUM_SCL_EN_8197F)) +#define BIT_GET_NUM_SCL_EN_8197F(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8197F) & BIT_MASK_NUM_SCL_EN_8197F) +#define BIT_SET_NUM_SCL_EN_8197F(x, v) (BIT_CLEAR_NUM_SCL_EN_8197F(x) | BIT_NUM_SCL_EN_8197F(v)) + +#define BIT_BK_EN_8197F BIT(3) +#define BIT_BE_EN_8197F BIT(2) +#define BIT_VI_EN_8197F BIT(1) +#define BIT_VO_EN_8197F BIT(0) + +/* 2 REG_PKT_LIFE_TIME_8197F */ + +#define BIT_SHIFT_PKT_LIFTIME_BEBK_8197F 16 +#define BIT_MASK_PKT_LIFTIME_BEBK_8197F 0xffff +#define BIT_PKT_LIFTIME_BEBK_8197F(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8197F) << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) +#define BITS_PKT_LIFTIME_BEBK_8197F (BIT_MASK_PKT_LIFTIME_BEBK_8197F << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) +#define BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) ((x) & (~BITS_PKT_LIFTIME_BEBK_8197F)) +#define BIT_GET_PKT_LIFTIME_BEBK_8197F(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) & BIT_MASK_PKT_LIFTIME_BEBK_8197F) +#define BIT_SET_PKT_LIFTIME_BEBK_8197F(x, v) (BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) | BIT_PKT_LIFTIME_BEBK_8197F(v)) + + +#define BIT_SHIFT_PKT_LIFTIME_VOVI_8197F 0 +#define BIT_MASK_PKT_LIFTIME_VOVI_8197F 0xffff +#define BIT_PKT_LIFTIME_VOVI_8197F(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8197F) << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) +#define BITS_PKT_LIFTIME_VOVI_8197F (BIT_MASK_PKT_LIFTIME_VOVI_8197F << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) +#define BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) ((x) & (~BITS_PKT_LIFTIME_VOVI_8197F)) +#define BIT_GET_PKT_LIFTIME_VOVI_8197F(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) & BIT_MASK_PKT_LIFTIME_VOVI_8197F) +#define BIT_SET_PKT_LIFTIME_VOVI_8197F(x, v) (BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) | BIT_PKT_LIFTIME_VOVI_8197F(v)) + + +/* 2 REG_STBC_SETTING_8197F */ + +#define BIT_SHIFT_CDEND_TXTIME_L_8197F 4 +#define BIT_MASK_CDEND_TXTIME_L_8197F 0xf +#define BIT_CDEND_TXTIME_L_8197F(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8197F) << BIT_SHIFT_CDEND_TXTIME_L_8197F) +#define BITS_CDEND_TXTIME_L_8197F (BIT_MASK_CDEND_TXTIME_L_8197F << BIT_SHIFT_CDEND_TXTIME_L_8197F) +#define BIT_CLEAR_CDEND_TXTIME_L_8197F(x) ((x) & (~BITS_CDEND_TXTIME_L_8197F)) +#define BIT_GET_CDEND_TXTIME_L_8197F(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8197F) & BIT_MASK_CDEND_TXTIME_L_8197F) +#define BIT_SET_CDEND_TXTIME_L_8197F(x, v) (BIT_CLEAR_CDEND_TXTIME_L_8197F(x) | BIT_CDEND_TXTIME_L_8197F(v)) + + +#define BIT_SHIFT_NESS_8197F 2 +#define BIT_MASK_NESS_8197F 0x3 +#define BIT_NESS_8197F(x) (((x) & BIT_MASK_NESS_8197F) << BIT_SHIFT_NESS_8197F) +#define BITS_NESS_8197F (BIT_MASK_NESS_8197F << BIT_SHIFT_NESS_8197F) +#define BIT_CLEAR_NESS_8197F(x) ((x) & (~BITS_NESS_8197F)) +#define BIT_GET_NESS_8197F(x) (((x) >> BIT_SHIFT_NESS_8197F) & BIT_MASK_NESS_8197F) +#define BIT_SET_NESS_8197F(x, v) (BIT_CLEAR_NESS_8197F(x) | BIT_NESS_8197F(v)) + + +#define BIT_SHIFT_STBC_CFEND_8197F 0 +#define BIT_MASK_STBC_CFEND_8197F 0x3 +#define BIT_STBC_CFEND_8197F(x) (((x) & BIT_MASK_STBC_CFEND_8197F) << BIT_SHIFT_STBC_CFEND_8197F) +#define BITS_STBC_CFEND_8197F (BIT_MASK_STBC_CFEND_8197F << BIT_SHIFT_STBC_CFEND_8197F) +#define BIT_CLEAR_STBC_CFEND_8197F(x) ((x) & (~BITS_STBC_CFEND_8197F)) +#define BIT_GET_STBC_CFEND_8197F(x) (((x) >> BIT_SHIFT_STBC_CFEND_8197F) & BIT_MASK_STBC_CFEND_8197F) +#define BIT_SET_STBC_CFEND_8197F(x, v) (BIT_CLEAR_STBC_CFEND_8197F(x) | BIT_STBC_CFEND_8197F(v)) + + +/* 2 REG_STBC_SETTING2_8197F */ + +#define BIT_SHIFT_CDEND_TXTIME_H_8197F 0 +#define BIT_MASK_CDEND_TXTIME_H_8197F 0x1f +#define BIT_CDEND_TXTIME_H_8197F(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8197F) << BIT_SHIFT_CDEND_TXTIME_H_8197F) +#define BITS_CDEND_TXTIME_H_8197F (BIT_MASK_CDEND_TXTIME_H_8197F << BIT_SHIFT_CDEND_TXTIME_H_8197F) +#define BIT_CLEAR_CDEND_TXTIME_H_8197F(x) ((x) & (~BITS_CDEND_TXTIME_H_8197F)) +#define BIT_GET_CDEND_TXTIME_H_8197F(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8197F) & BIT_MASK_CDEND_TXTIME_H_8197F) +#define BIT_SET_CDEND_TXTIME_H_8197F(x, v) (BIT_CLEAR_CDEND_TXTIME_H_8197F(x) | BIT_CDEND_TXTIME_H_8197F(v)) + + +/* 2 REG_QUEUE_CTRL_8197F */ +#define BIT_PTA_EDCCA_EN_8197F BIT(5) +#define BIT_PTA_WL_TX_EN_8197F BIT(4) +#define BIT_R_USE_DATA_BW_8197F BIT(3) +#define BIT_TRI_PKT_INT_MODE1_8197F BIT(2) +#define BIT_TRI_PKT_INT_MODE0_8197F BIT(1) +#define BIT_ACQ_MODE_SEL_8197F BIT(0) + +/* 2 REG_SINGLE_AMPDU_CTRL_8197F */ +#define BIT_EN_SINGLE_APMDU_8197F BIT(7) + +/* 2 REG_PROT_MODE_CTRL_8197F */ + +#define BIT_SHIFT_RTS_MAX_AGG_NUM_8197F 24 +#define BIT_MASK_RTS_MAX_AGG_NUM_8197F 0x3f +#define BIT_RTS_MAX_AGG_NUM_8197F(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8197F) << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) +#define BITS_RTS_MAX_AGG_NUM_8197F (BIT_MASK_RTS_MAX_AGG_NUM_8197F << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) +#define BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8197F)) +#define BIT_GET_RTS_MAX_AGG_NUM_8197F(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) & BIT_MASK_RTS_MAX_AGG_NUM_8197F) +#define BIT_SET_RTS_MAX_AGG_NUM_8197F(x, v) (BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) | BIT_RTS_MAX_AGG_NUM_8197F(v)) + + +#define BIT_SHIFT_MAX_AGG_NUM_8197F 16 +#define BIT_MASK_MAX_AGG_NUM_8197F 0x3f +#define BIT_MAX_AGG_NUM_8197F(x) (((x) & BIT_MASK_MAX_AGG_NUM_8197F) << BIT_SHIFT_MAX_AGG_NUM_8197F) +#define BITS_MAX_AGG_NUM_8197F (BIT_MASK_MAX_AGG_NUM_8197F << BIT_SHIFT_MAX_AGG_NUM_8197F) +#define BIT_CLEAR_MAX_AGG_NUM_8197F(x) ((x) & (~BITS_MAX_AGG_NUM_8197F)) +#define BIT_GET_MAX_AGG_NUM_8197F(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8197F) & BIT_MASK_MAX_AGG_NUM_8197F) +#define BIT_SET_MAX_AGG_NUM_8197F(x, v) (BIT_CLEAR_MAX_AGG_NUM_8197F(x) | BIT_MAX_AGG_NUM_8197F(v)) + + +#define BIT_SHIFT_RTS_TXTIME_TH_8197F 8 +#define BIT_MASK_RTS_TXTIME_TH_8197F 0xff +#define BIT_RTS_TXTIME_TH_8197F(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8197F) << BIT_SHIFT_RTS_TXTIME_TH_8197F) +#define BITS_RTS_TXTIME_TH_8197F (BIT_MASK_RTS_TXTIME_TH_8197F << BIT_SHIFT_RTS_TXTIME_TH_8197F) +#define BIT_CLEAR_RTS_TXTIME_TH_8197F(x) ((x) & (~BITS_RTS_TXTIME_TH_8197F)) +#define BIT_GET_RTS_TXTIME_TH_8197F(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8197F) & BIT_MASK_RTS_TXTIME_TH_8197F) +#define BIT_SET_RTS_TXTIME_TH_8197F(x, v) (BIT_CLEAR_RTS_TXTIME_TH_8197F(x) | BIT_RTS_TXTIME_TH_8197F(v)) + + +#define BIT_SHIFT_RTS_LEN_TH_8197F 0 +#define BIT_MASK_RTS_LEN_TH_8197F 0xff +#define BIT_RTS_LEN_TH_8197F(x) (((x) & BIT_MASK_RTS_LEN_TH_8197F) << BIT_SHIFT_RTS_LEN_TH_8197F) +#define BITS_RTS_LEN_TH_8197F (BIT_MASK_RTS_LEN_TH_8197F << BIT_SHIFT_RTS_LEN_TH_8197F) +#define BIT_CLEAR_RTS_LEN_TH_8197F(x) ((x) & (~BITS_RTS_LEN_TH_8197F)) +#define BIT_GET_RTS_LEN_TH_8197F(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8197F) & BIT_MASK_RTS_LEN_TH_8197F) +#define BIT_SET_RTS_LEN_TH_8197F(x, v) (BIT_CLEAR_RTS_LEN_TH_8197F(x) | BIT_RTS_LEN_TH_8197F(v)) + + +/* 2 REG_BAR_MODE_CTRL_8197F */ + +#define BIT_SHIFT_BAR_RTY_LMT_8197F 16 +#define BIT_MASK_BAR_RTY_LMT_8197F 0x3 +#define BIT_BAR_RTY_LMT_8197F(x) (((x) & BIT_MASK_BAR_RTY_LMT_8197F) << BIT_SHIFT_BAR_RTY_LMT_8197F) +#define BITS_BAR_RTY_LMT_8197F (BIT_MASK_BAR_RTY_LMT_8197F << BIT_SHIFT_BAR_RTY_LMT_8197F) +#define BIT_CLEAR_BAR_RTY_LMT_8197F(x) ((x) & (~BITS_BAR_RTY_LMT_8197F)) +#define BIT_GET_BAR_RTY_LMT_8197F(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8197F) & BIT_MASK_BAR_RTY_LMT_8197F) +#define BIT_SET_BAR_RTY_LMT_8197F(x, v) (BIT_CLEAR_BAR_RTY_LMT_8197F(x) | BIT_BAR_RTY_LMT_8197F(v)) + + +#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F 8 +#define BIT_MASK_BAR_PKT_TXTIME_TH_8197F 0xff +#define BIT_BAR_PKT_TXTIME_TH_8197F(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8197F) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) +#define BITS_BAR_PKT_TXTIME_TH_8197F (BIT_MASK_BAR_PKT_TXTIME_TH_8197F << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) ((x) & (~BITS_BAR_PKT_TXTIME_TH_8197F)) +#define BIT_GET_BAR_PKT_TXTIME_TH_8197F(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) & BIT_MASK_BAR_PKT_TXTIME_TH_8197F) +#define BIT_SET_BAR_PKT_TXTIME_TH_8197F(x, v) (BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) | BIT_BAR_PKT_TXTIME_TH_8197F(v)) + +#define BIT_BAR_EN_V1_8197F BIT(6) + +#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F 0 +#define BIT_MASK_BAR_PKTNUM_TH_V1_8197F 0x3f +#define BIT_BAR_PKTNUM_TH_V1_8197F(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8197F) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) +#define BITS_BAR_PKTNUM_TH_V1_8197F (BIT_MASK_BAR_PKTNUM_TH_V1_8197F << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) ((x) & (~BITS_BAR_PKTNUM_TH_V1_8197F)) +#define BIT_GET_BAR_PKTNUM_TH_V1_8197F(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) & BIT_MASK_BAR_PKTNUM_TH_V1_8197F) +#define BIT_SET_BAR_PKTNUM_TH_V1_8197F(x, v) (BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) | BIT_BAR_PKTNUM_TH_V1_8197F(v)) + + +/* 2 REG_RA_TRY_RATE_AGG_LMT_8197F */ + +#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F 0 +#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F 0x3f +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) +#define BITS_RA_TRY_RATE_AGG_LMT_V1_8197F (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8197F)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8197F(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8197F(x, v) (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) | BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(v)) + + +/* 2 REG_MACID_SLEEP2_8197F */ + +#define BIT_SHIFT_MACID95_64PKTSLEEP_8197F 0 +#define BIT_MASK_MACID95_64PKTSLEEP_8197F 0xffffffffL +#define BIT_MACID95_64PKTSLEEP_8197F(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8197F) << BIT_SHIFT_MACID95_64PKTSLEEP_8197F) +#define BITS_MACID95_64PKTSLEEP_8197F (BIT_MASK_MACID95_64PKTSLEEP_8197F << BIT_SHIFT_MACID95_64PKTSLEEP_8197F) +#define BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) ((x) & (~BITS_MACID95_64PKTSLEEP_8197F)) +#define BIT_GET_MACID95_64PKTSLEEP_8197F(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8197F) & BIT_MASK_MACID95_64PKTSLEEP_8197F) +#define BIT_SET_MACID95_64PKTSLEEP_8197F(x, v) (BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) | BIT_MACID95_64PKTSLEEP_8197F(v)) + + +/* 2 REG_MACID_SLEEP_8197F */ + +#define BIT_SHIFT_MACID31_0_PKTSLEEP_8197F 0 +#define BIT_MASK_MACID31_0_PKTSLEEP_8197F 0xffffffffL +#define BIT_MACID31_0_PKTSLEEP_8197F(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8197F) << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) +#define BITS_MACID31_0_PKTSLEEP_8197F (BIT_MASK_MACID31_0_PKTSLEEP_8197F << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) +#define BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) ((x) & (~BITS_MACID31_0_PKTSLEEP_8197F)) +#define BIT_GET_MACID31_0_PKTSLEEP_8197F(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) & BIT_MASK_MACID31_0_PKTSLEEP_8197F) +#define BIT_SET_MACID31_0_PKTSLEEP_8197F(x, v) (BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) | BIT_MACID31_0_PKTSLEEP_8197F(v)) + + +/* 2 REG_HW_SEQ0_8197F */ + +#define BIT_SHIFT_HW_SSN_SEQ0_8197F 0 +#define BIT_MASK_HW_SSN_SEQ0_8197F 0xfff +#define BIT_HW_SSN_SEQ0_8197F(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8197F) << BIT_SHIFT_HW_SSN_SEQ0_8197F) +#define BITS_HW_SSN_SEQ0_8197F (BIT_MASK_HW_SSN_SEQ0_8197F << BIT_SHIFT_HW_SSN_SEQ0_8197F) +#define BIT_CLEAR_HW_SSN_SEQ0_8197F(x) ((x) & (~BITS_HW_SSN_SEQ0_8197F)) +#define BIT_GET_HW_SSN_SEQ0_8197F(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8197F) & BIT_MASK_HW_SSN_SEQ0_8197F) +#define BIT_SET_HW_SSN_SEQ0_8197F(x, v) (BIT_CLEAR_HW_SSN_SEQ0_8197F(x) | BIT_HW_SSN_SEQ0_8197F(v)) + + +/* 2 REG_HW_SEQ1_8197F */ + +#define BIT_SHIFT_HW_SSN_SEQ1_8197F 0 +#define BIT_MASK_HW_SSN_SEQ1_8197F 0xfff +#define BIT_HW_SSN_SEQ1_8197F(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8197F) << BIT_SHIFT_HW_SSN_SEQ1_8197F) +#define BITS_HW_SSN_SEQ1_8197F (BIT_MASK_HW_SSN_SEQ1_8197F << BIT_SHIFT_HW_SSN_SEQ1_8197F) +#define BIT_CLEAR_HW_SSN_SEQ1_8197F(x) ((x) & (~BITS_HW_SSN_SEQ1_8197F)) +#define BIT_GET_HW_SSN_SEQ1_8197F(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8197F) & BIT_MASK_HW_SSN_SEQ1_8197F) +#define BIT_SET_HW_SSN_SEQ1_8197F(x, v) (BIT_CLEAR_HW_SSN_SEQ1_8197F(x) | BIT_HW_SSN_SEQ1_8197F(v)) + + +/* 2 REG_HW_SEQ2_8197F */ + +#define BIT_SHIFT_HW_SSN_SEQ2_8197F 0 +#define BIT_MASK_HW_SSN_SEQ2_8197F 0xfff +#define BIT_HW_SSN_SEQ2_8197F(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8197F) << BIT_SHIFT_HW_SSN_SEQ2_8197F) +#define BITS_HW_SSN_SEQ2_8197F (BIT_MASK_HW_SSN_SEQ2_8197F << BIT_SHIFT_HW_SSN_SEQ2_8197F) +#define BIT_CLEAR_HW_SSN_SEQ2_8197F(x) ((x) & (~BITS_HW_SSN_SEQ2_8197F)) +#define BIT_GET_HW_SSN_SEQ2_8197F(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8197F) & BIT_MASK_HW_SSN_SEQ2_8197F) +#define BIT_SET_HW_SSN_SEQ2_8197F(x, v) (BIT_CLEAR_HW_SSN_SEQ2_8197F(x) | BIT_HW_SSN_SEQ2_8197F(v)) + + +/* 2 REG_HW_SEQ3_8197F */ + +#define BIT_SHIFT_CSI_HWSSN_SEL_8197F 12 +#define BIT_MASK_CSI_HWSSN_SEL_8197F 0x3 +#define BIT_CSI_HWSSN_SEL_8197F(x) (((x) & BIT_MASK_CSI_HWSSN_SEL_8197F) << BIT_SHIFT_CSI_HWSSN_SEL_8197F) +#define BITS_CSI_HWSSN_SEL_8197F (BIT_MASK_CSI_HWSSN_SEL_8197F << BIT_SHIFT_CSI_HWSSN_SEL_8197F) +#define BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) ((x) & (~BITS_CSI_HWSSN_SEL_8197F)) +#define BIT_GET_CSI_HWSSN_SEL_8197F(x) (((x) >> BIT_SHIFT_CSI_HWSSN_SEL_8197F) & BIT_MASK_CSI_HWSSN_SEL_8197F) +#define BIT_SET_CSI_HWSSN_SEL_8197F(x, v) (BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) | BIT_CSI_HWSSN_SEL_8197F(v)) + + +#define BIT_SHIFT_HW_SSN_SEQ3_8197F 0 +#define BIT_MASK_HW_SSN_SEQ3_8197F 0xfff +#define BIT_HW_SSN_SEQ3_8197F(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8197F) << BIT_SHIFT_HW_SSN_SEQ3_8197F) +#define BITS_HW_SSN_SEQ3_8197F (BIT_MASK_HW_SSN_SEQ3_8197F << BIT_SHIFT_HW_SSN_SEQ3_8197F) +#define BIT_CLEAR_HW_SSN_SEQ3_8197F(x) ((x) & (~BITS_HW_SSN_SEQ3_8197F)) +#define BIT_GET_HW_SSN_SEQ3_8197F(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8197F) & BIT_MASK_HW_SSN_SEQ3_8197F) +#define BIT_SET_HW_SSN_SEQ3_8197F(x, v) (BIT_CLEAR_HW_SSN_SEQ3_8197F(x) | BIT_HW_SSN_SEQ3_8197F(v)) + + +/* 2 REG_NULL_PKT_STATUS_V1_8197F */ + +#define BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F 2 +#define BIT_MASK_PTCL_TOTAL_PG_V1_8197F 0x1fff +#define BIT_PTCL_TOTAL_PG_V1_8197F(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V1_8197F) << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) +#define BITS_PTCL_TOTAL_PG_V1_8197F (BIT_MASK_PTCL_TOTAL_PG_V1_8197F << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) +#define BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) ((x) & (~BITS_PTCL_TOTAL_PG_V1_8197F)) +#define BIT_GET_PTCL_TOTAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) & BIT_MASK_PTCL_TOTAL_PG_V1_8197F) +#define BIT_SET_PTCL_TOTAL_PG_V1_8197F(x, v) (BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) | BIT_PTCL_TOTAL_PG_V1_8197F(v)) + +#define BIT_TX_NULL_1_8197F BIT(1) +#define BIT_TX_NULL_0_8197F BIT(0) + +/* 2 REG_PTCL_ERR_STATUS_8197F */ +#define BIT_PTCL_RATE_TABLE_INVALID_8197F BIT(7) +#define BIT_FTM_T2R_ERROR_8197F BIT(6) +#define BIT_PTCL_ERR0_8197F BIT(5) +#define BIT_PTCL_ERR1_8197F BIT(4) +#define BIT_PTCL_ERR2_8197F BIT(3) +#define BIT_PTCL_ERR3_8197F BIT(2) +#define BIT_PTCL_ERR4_8197F BIT(1) +#define BIT_PTCL_ERR5_8197F BIT(0) + +/* 2 REG_NULL_PKT_STATUS_EXTEND_8197F */ +#define BIT_CLI3_TX_NULL_1_8197F BIT(7) +#define BIT_CLI3_TX_NULL_0_8197F BIT(6) +#define BIT_CLI2_TX_NULL_1_8197F BIT(5) +#define BIT_CLI2_TX_NULL_0_8197F BIT(4) +#define BIT_CLI1_TX_NULL_1_8197F BIT(3) +#define BIT_CLI1_TX_NULL_0_8197F BIT(2) +#define BIT_CLI0_TX_NULL_1_8197F BIT(1) +#define BIT_CLI0_TX_NULL_0_8197F BIT(0) + +/* 2 REG_VIDEO_ENHANCEMENT_FUN_8197F */ +#define BIT_VIDEO_JUST_DROP_8197F BIT(1) +#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8197F BIT(0) + +/* 2 REG_BT_POLLUTE_PKT_CNT_8197F */ + +#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F 0 +#define BIT_MASK_BT_POLLUTE_PKT_CNT_8197F 0xffff +#define BIT_BT_POLLUTE_PKT_CNT_8197F(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8197F) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) +#define BITS_BT_POLLUTE_PKT_CNT_8197F (BIT_MASK_BT_POLLUTE_PKT_CNT_8197F << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) +#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8197F)) +#define BIT_GET_BT_POLLUTE_PKT_CNT_8197F(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) & BIT_MASK_BT_POLLUTE_PKT_CNT_8197F) +#define BIT_SET_BT_POLLUTE_PKT_CNT_8197F(x, v) (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) | BIT_BT_POLLUTE_PKT_CNT_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_PTCL_DBG_8197F */ + +#define BIT_SHIFT_PTCL_DBG_8197F 0 +#define BIT_MASK_PTCL_DBG_8197F 0xffffffffL +#define BIT_PTCL_DBG_8197F(x) (((x) & BIT_MASK_PTCL_DBG_8197F) << BIT_SHIFT_PTCL_DBG_8197F) +#define BITS_PTCL_DBG_8197F (BIT_MASK_PTCL_DBG_8197F << BIT_SHIFT_PTCL_DBG_8197F) +#define BIT_CLEAR_PTCL_DBG_8197F(x) ((x) & (~BITS_PTCL_DBG_8197F)) +#define BIT_GET_PTCL_DBG_8197F(x) (((x) >> BIT_SHIFT_PTCL_DBG_8197F) & BIT_MASK_PTCL_DBG_8197F) +#define BIT_SET_PTCL_DBG_8197F(x, v) (BIT_CLEAR_PTCL_DBG_8197F(x) | BIT_PTCL_DBG_8197F(v)) + + +/* 2 REG_TXOP_EXTRA_CTRL_8197F */ +#define BIT_TXOP_EFFICIENCY_EN_8197F BIT(0) + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_CPUMGQ_TIMER_CTRL2_8197F */ + +#define BIT_SHIFT_TRI_HEAD_ADDR_8197F 16 +#define BIT_MASK_TRI_HEAD_ADDR_8197F 0xfff +#define BIT_TRI_HEAD_ADDR_8197F(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8197F) << BIT_SHIFT_TRI_HEAD_ADDR_8197F) +#define BITS_TRI_HEAD_ADDR_8197F (BIT_MASK_TRI_HEAD_ADDR_8197F << BIT_SHIFT_TRI_HEAD_ADDR_8197F) +#define BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) ((x) & (~BITS_TRI_HEAD_ADDR_8197F)) +#define BIT_GET_TRI_HEAD_ADDR_8197F(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8197F) & BIT_MASK_TRI_HEAD_ADDR_8197F) +#define BIT_SET_TRI_HEAD_ADDR_8197F(x, v) (BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) | BIT_TRI_HEAD_ADDR_8197F(v)) + +#define BIT_DROP_TH_EN_8197F BIT(8) + +#define BIT_SHIFT_DROP_TH_8197F 0 +#define BIT_MASK_DROP_TH_8197F 0xff +#define BIT_DROP_TH_8197F(x) (((x) & BIT_MASK_DROP_TH_8197F) << BIT_SHIFT_DROP_TH_8197F) +#define BITS_DROP_TH_8197F (BIT_MASK_DROP_TH_8197F << BIT_SHIFT_DROP_TH_8197F) +#define BIT_CLEAR_DROP_TH_8197F(x) ((x) & (~BITS_DROP_TH_8197F)) +#define BIT_GET_DROP_TH_8197F(x) (((x) >> BIT_SHIFT_DROP_TH_8197F) & BIT_MASK_DROP_TH_8197F) +#define BIT_SET_DROP_TH_8197F(x, v) (BIT_CLEAR_DROP_TH_8197F(x) | BIT_DROP_TH_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_DUMMY_PAGE4_8197F */ +#define BIT_MOREDATA_CTRL2_EN_V2_8197F BIT(19) +#define BIT_MOREDATA_CTRL1_EN_V2_8197F BIT(18) +#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_8197F BIT(16) + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_Q0_Q1_INFO_8197F */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31) + +#define BIT_SHIFT_GTAB_ID_8197F 28 +#define BIT_MASK_GTAB_ID_8197F 0x7 +#define BIT_GTAB_ID_8197F(x) (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) +#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F) +#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F)) +#define BIT_GET_GTAB_ID_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) +#define BIT_SET_GTAB_ID_8197F(x, v) (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) + + +#define BIT_SHIFT_AC1_PKT_INFO_8197F 16 +#define BIT_MASK_AC1_PKT_INFO_8197F 0xfff +#define BIT_AC1_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC1_PKT_INFO_8197F) << BIT_SHIFT_AC1_PKT_INFO_8197F) +#define BITS_AC1_PKT_INFO_8197F (BIT_MASK_AC1_PKT_INFO_8197F << BIT_SHIFT_AC1_PKT_INFO_8197F) +#define BIT_CLEAR_AC1_PKT_INFO_8197F(x) ((x) & (~BITS_AC1_PKT_INFO_8197F)) +#define BIT_GET_AC1_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8197F) & BIT_MASK_AC1_PKT_INFO_8197F) +#define BIT_SET_AC1_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC1_PKT_INFO_8197F(x) | BIT_AC1_PKT_INFO_8197F(v)) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8197F 12 +#define BIT_MASK_GTAB_ID_V1_8197F 0x7 +#define BIT_GTAB_ID_V1_8197F(x) (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BITS_GTAB_ID_V1_8197F (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F)) +#define BIT_GET_GTAB_ID_V1_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) +#define BIT_SET_GTAB_ID_V1_8197F(x, v) (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) + + +#define BIT_SHIFT_AC0_PKT_INFO_8197F 0 +#define BIT_MASK_AC0_PKT_INFO_8197F 0xfff +#define BIT_AC0_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC0_PKT_INFO_8197F) << BIT_SHIFT_AC0_PKT_INFO_8197F) +#define BITS_AC0_PKT_INFO_8197F (BIT_MASK_AC0_PKT_INFO_8197F << BIT_SHIFT_AC0_PKT_INFO_8197F) +#define BIT_CLEAR_AC0_PKT_INFO_8197F(x) ((x) & (~BITS_AC0_PKT_INFO_8197F)) +#define BIT_GET_AC0_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8197F) & BIT_MASK_AC0_PKT_INFO_8197F) +#define BIT_SET_AC0_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC0_PKT_INFO_8197F(x) | BIT_AC0_PKT_INFO_8197F(v)) + + +/* 2 REG_Q2_Q3_INFO_8197F */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31) + +#define BIT_SHIFT_GTAB_ID_8197F 28 +#define BIT_MASK_GTAB_ID_8197F 0x7 +#define BIT_GTAB_ID_8197F(x) (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) +#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F) +#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F)) +#define BIT_GET_GTAB_ID_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) +#define BIT_SET_GTAB_ID_8197F(x, v) (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) + + +#define BIT_SHIFT_AC3_PKT_INFO_8197F 16 +#define BIT_MASK_AC3_PKT_INFO_8197F 0xfff +#define BIT_AC3_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC3_PKT_INFO_8197F) << BIT_SHIFT_AC3_PKT_INFO_8197F) +#define BITS_AC3_PKT_INFO_8197F (BIT_MASK_AC3_PKT_INFO_8197F << BIT_SHIFT_AC3_PKT_INFO_8197F) +#define BIT_CLEAR_AC3_PKT_INFO_8197F(x) ((x) & (~BITS_AC3_PKT_INFO_8197F)) +#define BIT_GET_AC3_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8197F) & BIT_MASK_AC3_PKT_INFO_8197F) +#define BIT_SET_AC3_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC3_PKT_INFO_8197F(x) | BIT_AC3_PKT_INFO_8197F(v)) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8197F 12 +#define BIT_MASK_GTAB_ID_V1_8197F 0x7 +#define BIT_GTAB_ID_V1_8197F(x) (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BITS_GTAB_ID_V1_8197F (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F)) +#define BIT_GET_GTAB_ID_V1_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) +#define BIT_SET_GTAB_ID_V1_8197F(x, v) (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) + + +#define BIT_SHIFT_AC2_PKT_INFO_8197F 0 +#define BIT_MASK_AC2_PKT_INFO_8197F 0xfff +#define BIT_AC2_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC2_PKT_INFO_8197F) << BIT_SHIFT_AC2_PKT_INFO_8197F) +#define BITS_AC2_PKT_INFO_8197F (BIT_MASK_AC2_PKT_INFO_8197F << BIT_SHIFT_AC2_PKT_INFO_8197F) +#define BIT_CLEAR_AC2_PKT_INFO_8197F(x) ((x) & (~BITS_AC2_PKT_INFO_8197F)) +#define BIT_GET_AC2_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8197F) & BIT_MASK_AC2_PKT_INFO_8197F) +#define BIT_SET_AC2_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC2_PKT_INFO_8197F(x) | BIT_AC2_PKT_INFO_8197F(v)) + + +/* 2 REG_Q4_Q5_INFO_8197F */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31) + +#define BIT_SHIFT_GTAB_ID_8197F 28 +#define BIT_MASK_GTAB_ID_8197F 0x7 +#define BIT_GTAB_ID_8197F(x) (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) +#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F) +#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F)) +#define BIT_GET_GTAB_ID_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) +#define BIT_SET_GTAB_ID_8197F(x, v) (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) + + +#define BIT_SHIFT_AC5_PKT_INFO_8197F 16 +#define BIT_MASK_AC5_PKT_INFO_8197F 0xfff +#define BIT_AC5_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC5_PKT_INFO_8197F) << BIT_SHIFT_AC5_PKT_INFO_8197F) +#define BITS_AC5_PKT_INFO_8197F (BIT_MASK_AC5_PKT_INFO_8197F << BIT_SHIFT_AC5_PKT_INFO_8197F) +#define BIT_CLEAR_AC5_PKT_INFO_8197F(x) ((x) & (~BITS_AC5_PKT_INFO_8197F)) +#define BIT_GET_AC5_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8197F) & BIT_MASK_AC5_PKT_INFO_8197F) +#define BIT_SET_AC5_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC5_PKT_INFO_8197F(x) | BIT_AC5_PKT_INFO_8197F(v)) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8197F 12 +#define BIT_MASK_GTAB_ID_V1_8197F 0x7 +#define BIT_GTAB_ID_V1_8197F(x) (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BITS_GTAB_ID_V1_8197F (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F)) +#define BIT_GET_GTAB_ID_V1_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) +#define BIT_SET_GTAB_ID_V1_8197F(x, v) (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) + + +#define BIT_SHIFT_AC4_PKT_INFO_8197F 0 +#define BIT_MASK_AC4_PKT_INFO_8197F 0xfff +#define BIT_AC4_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC4_PKT_INFO_8197F) << BIT_SHIFT_AC4_PKT_INFO_8197F) +#define BITS_AC4_PKT_INFO_8197F (BIT_MASK_AC4_PKT_INFO_8197F << BIT_SHIFT_AC4_PKT_INFO_8197F) +#define BIT_CLEAR_AC4_PKT_INFO_8197F(x) ((x) & (~BITS_AC4_PKT_INFO_8197F)) +#define BIT_GET_AC4_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8197F) & BIT_MASK_AC4_PKT_INFO_8197F) +#define BIT_SET_AC4_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC4_PKT_INFO_8197F(x) | BIT_AC4_PKT_INFO_8197F(v)) + + +/* 2 REG_Q6_Q7_INFO_8197F */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31) + +#define BIT_SHIFT_GTAB_ID_8197F 28 +#define BIT_MASK_GTAB_ID_8197F 0x7 +#define BIT_GTAB_ID_8197F(x) (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) +#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F) +#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F)) +#define BIT_GET_GTAB_ID_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) +#define BIT_SET_GTAB_ID_8197F(x, v) (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) + + +#define BIT_SHIFT_AC7_PKT_INFO_8197F 16 +#define BIT_MASK_AC7_PKT_INFO_8197F 0xfff +#define BIT_AC7_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC7_PKT_INFO_8197F) << BIT_SHIFT_AC7_PKT_INFO_8197F) +#define BITS_AC7_PKT_INFO_8197F (BIT_MASK_AC7_PKT_INFO_8197F << BIT_SHIFT_AC7_PKT_INFO_8197F) +#define BIT_CLEAR_AC7_PKT_INFO_8197F(x) ((x) & (~BITS_AC7_PKT_INFO_8197F)) +#define BIT_GET_AC7_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8197F) & BIT_MASK_AC7_PKT_INFO_8197F) +#define BIT_SET_AC7_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC7_PKT_INFO_8197F(x) | BIT_AC7_PKT_INFO_8197F(v)) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8197F 12 +#define BIT_MASK_GTAB_ID_V1_8197F 0x7 +#define BIT_GTAB_ID_V1_8197F(x) (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BITS_GTAB_ID_V1_8197F (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F)) +#define BIT_GET_GTAB_ID_V1_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) +#define BIT_SET_GTAB_ID_V1_8197F(x, v) (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) + + +#define BIT_SHIFT_AC6_PKT_INFO_8197F 0 +#define BIT_MASK_AC6_PKT_INFO_8197F 0xfff +#define BIT_AC6_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC6_PKT_INFO_8197F) << BIT_SHIFT_AC6_PKT_INFO_8197F) +#define BITS_AC6_PKT_INFO_8197F (BIT_MASK_AC6_PKT_INFO_8197F << BIT_SHIFT_AC6_PKT_INFO_8197F) +#define BIT_CLEAR_AC6_PKT_INFO_8197F(x) ((x) & (~BITS_AC6_PKT_INFO_8197F)) +#define BIT_GET_AC6_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8197F) & BIT_MASK_AC6_PKT_INFO_8197F) +#define BIT_SET_AC6_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC6_PKT_INFO_8197F(x) | BIT_AC6_PKT_INFO_8197F(v)) + + +/* 2 REG_MGQ_HIQ_INFO_8197F */ + +#define BIT_SHIFT_HIQ_PKT_INFO_8197F 16 +#define BIT_MASK_HIQ_PKT_INFO_8197F 0xfff +#define BIT_HIQ_PKT_INFO_8197F(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8197F) << BIT_SHIFT_HIQ_PKT_INFO_8197F) +#define BITS_HIQ_PKT_INFO_8197F (BIT_MASK_HIQ_PKT_INFO_8197F << BIT_SHIFT_HIQ_PKT_INFO_8197F) +#define BIT_CLEAR_HIQ_PKT_INFO_8197F(x) ((x) & (~BITS_HIQ_PKT_INFO_8197F)) +#define BIT_GET_HIQ_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8197F) & BIT_MASK_HIQ_PKT_INFO_8197F) +#define BIT_SET_HIQ_PKT_INFO_8197F(x, v) (BIT_CLEAR_HIQ_PKT_INFO_8197F(x) | BIT_HIQ_PKT_INFO_8197F(v)) + + +#define BIT_SHIFT_MGQ_PKT_INFO_8197F 0 +#define BIT_MASK_MGQ_PKT_INFO_8197F 0xfff +#define BIT_MGQ_PKT_INFO_8197F(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8197F) << BIT_SHIFT_MGQ_PKT_INFO_8197F) +#define BITS_MGQ_PKT_INFO_8197F (BIT_MASK_MGQ_PKT_INFO_8197F << BIT_SHIFT_MGQ_PKT_INFO_8197F) +#define BIT_CLEAR_MGQ_PKT_INFO_8197F(x) ((x) & (~BITS_MGQ_PKT_INFO_8197F)) +#define BIT_GET_MGQ_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8197F) & BIT_MASK_MGQ_PKT_INFO_8197F) +#define BIT_SET_MGQ_PKT_INFO_8197F(x, v) (BIT_CLEAR_MGQ_PKT_INFO_8197F(x) | BIT_MGQ_PKT_INFO_8197F(v)) + + +/* 2 REG_CMDQ_BCNQ_INFO_8197F */ + +#define BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F 16 +#define BIT_MASK_BCNQ_PKT_INFO_V1_8197F 0xfff +#define BIT_BCNQ_PKT_INFO_V1_8197F(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_V1_8197F) << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) +#define BITS_BCNQ_PKT_INFO_V1_8197F (BIT_MASK_BCNQ_PKT_INFO_V1_8197F << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) +#define BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) ((x) & (~BITS_BCNQ_PKT_INFO_V1_8197F)) +#define BIT_GET_BCNQ_PKT_INFO_V1_8197F(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) & BIT_MASK_BCNQ_PKT_INFO_V1_8197F) +#define BIT_SET_BCNQ_PKT_INFO_V1_8197F(x, v) (BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) | BIT_BCNQ_PKT_INFO_V1_8197F(v)) + + +#define BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F 0 +#define BIT_MASK_CMDQ_PKT_INFO_V1_8197F 0xfff +#define BIT_CMDQ_PKT_INFO_V1_8197F(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_V1_8197F) << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) +#define BITS_CMDQ_PKT_INFO_V1_8197F (BIT_MASK_CMDQ_PKT_INFO_V1_8197F << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) +#define BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) ((x) & (~BITS_CMDQ_PKT_INFO_V1_8197F)) +#define BIT_GET_CMDQ_PKT_INFO_V1_8197F(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) & BIT_MASK_CMDQ_PKT_INFO_V1_8197F) +#define BIT_SET_CMDQ_PKT_INFO_V1_8197F(x, v) (BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) | BIT_CMDQ_PKT_INFO_V1_8197F(v)) + + +/* 2 REG_USEREG_SETTING_8197F */ +#define BIT_NDPA_USEREG_8197F BIT(21) + +#define BIT_SHIFT_RETRY_USEREG_8197F 19 +#define BIT_MASK_RETRY_USEREG_8197F 0x3 +#define BIT_RETRY_USEREG_8197F(x) (((x) & BIT_MASK_RETRY_USEREG_8197F) << BIT_SHIFT_RETRY_USEREG_8197F) +#define BITS_RETRY_USEREG_8197F (BIT_MASK_RETRY_USEREG_8197F << BIT_SHIFT_RETRY_USEREG_8197F) +#define BIT_CLEAR_RETRY_USEREG_8197F(x) ((x) & (~BITS_RETRY_USEREG_8197F)) +#define BIT_GET_RETRY_USEREG_8197F(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8197F) & BIT_MASK_RETRY_USEREG_8197F) +#define BIT_SET_RETRY_USEREG_8197F(x, v) (BIT_CLEAR_RETRY_USEREG_8197F(x) | BIT_RETRY_USEREG_8197F(v)) + + +#define BIT_SHIFT_TRYPKT_USEREG_8197F 17 +#define BIT_MASK_TRYPKT_USEREG_8197F 0x3 +#define BIT_TRYPKT_USEREG_8197F(x) (((x) & BIT_MASK_TRYPKT_USEREG_8197F) << BIT_SHIFT_TRYPKT_USEREG_8197F) +#define BITS_TRYPKT_USEREG_8197F (BIT_MASK_TRYPKT_USEREG_8197F << BIT_SHIFT_TRYPKT_USEREG_8197F) +#define BIT_CLEAR_TRYPKT_USEREG_8197F(x) ((x) & (~BITS_TRYPKT_USEREG_8197F)) +#define BIT_GET_TRYPKT_USEREG_8197F(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8197F) & BIT_MASK_TRYPKT_USEREG_8197F) +#define BIT_SET_TRYPKT_USEREG_8197F(x, v) (BIT_CLEAR_TRYPKT_USEREG_8197F(x) | BIT_TRYPKT_USEREG_8197F(v)) + +#define BIT_CTLPKT_USEREG_8197F BIT(16) + +/* 2 REG_AESIV_SETTING_8197F */ + +#define BIT_SHIFT_AESIV_OFFSET_8197F 0 +#define BIT_MASK_AESIV_OFFSET_8197F 0xfff +#define BIT_AESIV_OFFSET_8197F(x) (((x) & BIT_MASK_AESIV_OFFSET_8197F) << BIT_SHIFT_AESIV_OFFSET_8197F) +#define BITS_AESIV_OFFSET_8197F (BIT_MASK_AESIV_OFFSET_8197F << BIT_SHIFT_AESIV_OFFSET_8197F) +#define BIT_CLEAR_AESIV_OFFSET_8197F(x) ((x) & (~BITS_AESIV_OFFSET_8197F)) +#define BIT_GET_AESIV_OFFSET_8197F(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8197F) & BIT_MASK_AESIV_OFFSET_8197F) +#define BIT_SET_AESIV_OFFSET_8197F(x, v) (BIT_CLEAR_AESIV_OFFSET_8197F(x) | BIT_AESIV_OFFSET_8197F(v)) + + +/* 2 REG_BF0_TIME_SETTING_8197F */ +#define BIT_BF0_TIMER_SET_8197F BIT(31) +#define BIT_BF0_TIMER_CLR_8197F BIT(30) +#define BIT_BF0_UPDATE_EN_8197F BIT(29) +#define BIT_BF0_TIMER_EN_8197F BIT(28) + +#define BIT_SHIFT_BF0_PRETIME_OVER_8197F 16 +#define BIT_MASK_BF0_PRETIME_OVER_8197F 0xfff +#define BIT_BF0_PRETIME_OVER_8197F(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8197F) << BIT_SHIFT_BF0_PRETIME_OVER_8197F) +#define BITS_BF0_PRETIME_OVER_8197F (BIT_MASK_BF0_PRETIME_OVER_8197F << BIT_SHIFT_BF0_PRETIME_OVER_8197F) +#define BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) ((x) & (~BITS_BF0_PRETIME_OVER_8197F)) +#define BIT_GET_BF0_PRETIME_OVER_8197F(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8197F) & BIT_MASK_BF0_PRETIME_OVER_8197F) +#define BIT_SET_BF0_PRETIME_OVER_8197F(x, v) (BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) | BIT_BF0_PRETIME_OVER_8197F(v)) + + +#define BIT_SHIFT_BF0_LIFETIME_8197F 0 +#define BIT_MASK_BF0_LIFETIME_8197F 0xffff +#define BIT_BF0_LIFETIME_8197F(x) (((x) & BIT_MASK_BF0_LIFETIME_8197F) << BIT_SHIFT_BF0_LIFETIME_8197F) +#define BITS_BF0_LIFETIME_8197F (BIT_MASK_BF0_LIFETIME_8197F << BIT_SHIFT_BF0_LIFETIME_8197F) +#define BIT_CLEAR_BF0_LIFETIME_8197F(x) ((x) & (~BITS_BF0_LIFETIME_8197F)) +#define BIT_GET_BF0_LIFETIME_8197F(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8197F) & BIT_MASK_BF0_LIFETIME_8197F) +#define BIT_SET_BF0_LIFETIME_8197F(x, v) (BIT_CLEAR_BF0_LIFETIME_8197F(x) | BIT_BF0_LIFETIME_8197F(v)) + + +/* 2 REG_BF1_TIME_SETTING_8197F */ +#define BIT_BF1_TIMER_SET_8197F BIT(31) +#define BIT_BF1_TIMER_CLR_8197F BIT(30) +#define BIT_BF1_UPDATE_EN_8197F BIT(29) +#define BIT_BF1_TIMER_EN_8197F BIT(28) + +#define BIT_SHIFT_BF1_PRETIME_OVER_8197F 16 +#define BIT_MASK_BF1_PRETIME_OVER_8197F 0xfff +#define BIT_BF1_PRETIME_OVER_8197F(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8197F) << BIT_SHIFT_BF1_PRETIME_OVER_8197F) +#define BITS_BF1_PRETIME_OVER_8197F (BIT_MASK_BF1_PRETIME_OVER_8197F << BIT_SHIFT_BF1_PRETIME_OVER_8197F) +#define BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) ((x) & (~BITS_BF1_PRETIME_OVER_8197F)) +#define BIT_GET_BF1_PRETIME_OVER_8197F(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8197F) & BIT_MASK_BF1_PRETIME_OVER_8197F) +#define BIT_SET_BF1_PRETIME_OVER_8197F(x, v) (BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) | BIT_BF1_PRETIME_OVER_8197F(v)) + + +#define BIT_SHIFT_BF1_LIFETIME_8197F 0 +#define BIT_MASK_BF1_LIFETIME_8197F 0xffff +#define BIT_BF1_LIFETIME_8197F(x) (((x) & BIT_MASK_BF1_LIFETIME_8197F) << BIT_SHIFT_BF1_LIFETIME_8197F) +#define BITS_BF1_LIFETIME_8197F (BIT_MASK_BF1_LIFETIME_8197F << BIT_SHIFT_BF1_LIFETIME_8197F) +#define BIT_CLEAR_BF1_LIFETIME_8197F(x) ((x) & (~BITS_BF1_LIFETIME_8197F)) +#define BIT_GET_BF1_LIFETIME_8197F(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8197F) & BIT_MASK_BF1_LIFETIME_8197F) +#define BIT_SET_BF1_LIFETIME_8197F(x, v) (BIT_CLEAR_BF1_LIFETIME_8197F(x) | BIT_BF1_LIFETIME_8197F(v)) + + +/* 2 REG_BF_TIMEOUT_EN_8197F */ +#define BIT_EN_VHT_LDPC_8197F BIT(9) +#define BIT_EN_HT_LDPC_8197F BIT(8) +#define BIT_BF1_TIMEOUT_EN_8197F BIT(1) +#define BIT_BF0_TIMEOUT_EN_8197F BIT(0) + +/* 2 REG_MACID_RELEASE0_8197F */ + +#define BIT_SHIFT_MACID31_0_RELEASE_8197F 0 +#define BIT_MASK_MACID31_0_RELEASE_8197F 0xffffffffL +#define BIT_MACID31_0_RELEASE_8197F(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8197F) << BIT_SHIFT_MACID31_0_RELEASE_8197F) +#define BITS_MACID31_0_RELEASE_8197F (BIT_MASK_MACID31_0_RELEASE_8197F << BIT_SHIFT_MACID31_0_RELEASE_8197F) +#define BIT_CLEAR_MACID31_0_RELEASE_8197F(x) ((x) & (~BITS_MACID31_0_RELEASE_8197F)) +#define BIT_GET_MACID31_0_RELEASE_8197F(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8197F) & BIT_MASK_MACID31_0_RELEASE_8197F) +#define BIT_SET_MACID31_0_RELEASE_8197F(x, v) (BIT_CLEAR_MACID31_0_RELEASE_8197F(x) | BIT_MACID31_0_RELEASE_8197F(v)) + + +/* 2 REG_MACID_RELEASE1_8197F */ + +#define BIT_SHIFT_MACID63_32_RELEASE_8197F 0 +#define BIT_MASK_MACID63_32_RELEASE_8197F 0xffffffffL +#define BIT_MACID63_32_RELEASE_8197F(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8197F) << BIT_SHIFT_MACID63_32_RELEASE_8197F) +#define BITS_MACID63_32_RELEASE_8197F (BIT_MASK_MACID63_32_RELEASE_8197F << BIT_SHIFT_MACID63_32_RELEASE_8197F) +#define BIT_CLEAR_MACID63_32_RELEASE_8197F(x) ((x) & (~BITS_MACID63_32_RELEASE_8197F)) +#define BIT_GET_MACID63_32_RELEASE_8197F(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8197F) & BIT_MASK_MACID63_32_RELEASE_8197F) +#define BIT_SET_MACID63_32_RELEASE_8197F(x, v) (BIT_CLEAR_MACID63_32_RELEASE_8197F(x) | BIT_MACID63_32_RELEASE_8197F(v)) + + +/* 2 REG_MACID_RELEASE2_8197F */ + +#define BIT_SHIFT_MACID95_64_RELEASE_8197F 0 +#define BIT_MASK_MACID95_64_RELEASE_8197F 0xffffffffL +#define BIT_MACID95_64_RELEASE_8197F(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8197F) << BIT_SHIFT_MACID95_64_RELEASE_8197F) +#define BITS_MACID95_64_RELEASE_8197F (BIT_MASK_MACID95_64_RELEASE_8197F << BIT_SHIFT_MACID95_64_RELEASE_8197F) +#define BIT_CLEAR_MACID95_64_RELEASE_8197F(x) ((x) & (~BITS_MACID95_64_RELEASE_8197F)) +#define BIT_GET_MACID95_64_RELEASE_8197F(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8197F) & BIT_MASK_MACID95_64_RELEASE_8197F) +#define BIT_SET_MACID95_64_RELEASE_8197F(x, v) (BIT_CLEAR_MACID95_64_RELEASE_8197F(x) | BIT_MACID95_64_RELEASE_8197F(v)) + + +/* 2 REG_MACID_RELEASE3_8197F */ + +#define BIT_SHIFT_MACID127_96_RELEASE_8197F 0 +#define BIT_MASK_MACID127_96_RELEASE_8197F 0xffffffffL +#define BIT_MACID127_96_RELEASE_8197F(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8197F) << BIT_SHIFT_MACID127_96_RELEASE_8197F) +#define BITS_MACID127_96_RELEASE_8197F (BIT_MASK_MACID127_96_RELEASE_8197F << BIT_SHIFT_MACID127_96_RELEASE_8197F) +#define BIT_CLEAR_MACID127_96_RELEASE_8197F(x) ((x) & (~BITS_MACID127_96_RELEASE_8197F)) +#define BIT_GET_MACID127_96_RELEASE_8197F(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8197F) & BIT_MASK_MACID127_96_RELEASE_8197F) +#define BIT_SET_MACID127_96_RELEASE_8197F(x, v) (BIT_CLEAR_MACID127_96_RELEASE_8197F(x) | BIT_MACID127_96_RELEASE_8197F(v)) + + +/* 2 REG_MACID_RELEASE_SETTING_8197F */ +#define BIT_MACID_VALUE_8197F BIT(7) + +#define BIT_SHIFT_MACID_OFFSET_8197F 0 +#define BIT_MASK_MACID_OFFSET_8197F 0x7f +#define BIT_MACID_OFFSET_8197F(x) (((x) & BIT_MASK_MACID_OFFSET_8197F) << BIT_SHIFT_MACID_OFFSET_8197F) +#define BITS_MACID_OFFSET_8197F (BIT_MASK_MACID_OFFSET_8197F << BIT_SHIFT_MACID_OFFSET_8197F) +#define BIT_CLEAR_MACID_OFFSET_8197F(x) ((x) & (~BITS_MACID_OFFSET_8197F)) +#define BIT_GET_MACID_OFFSET_8197F(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8197F) & BIT_MASK_MACID_OFFSET_8197F) +#define BIT_SET_MACID_OFFSET_8197F(x, v) (BIT_CLEAR_MACID_OFFSET_8197F(x) | BIT_MACID_OFFSET_8197F(v)) + + +/* 2 REG_FAST_EDCA_VOVI_SETTING_8197F */ + +#define BIT_SHIFT_VI_FAST_EDCA_TO_8197F 24 +#define BIT_MASK_VI_FAST_EDCA_TO_8197F 0xff +#define BIT_VI_FAST_EDCA_TO_8197F(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8197F) << BIT_SHIFT_VI_FAST_EDCA_TO_8197F) +#define BITS_VI_FAST_EDCA_TO_8197F (BIT_MASK_VI_FAST_EDCA_TO_8197F << BIT_SHIFT_VI_FAST_EDCA_TO_8197F) +#define BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8197F)) +#define BIT_GET_VI_FAST_EDCA_TO_8197F(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8197F) & BIT_MASK_VI_FAST_EDCA_TO_8197F) +#define BIT_SET_VI_FAST_EDCA_TO_8197F(x, v) (BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) | BIT_VI_FAST_EDCA_TO_8197F(v)) + +#define BIT_VI_THRESHOLD_SEL_8197F BIT(23) + +#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F 16 +#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F 0x7f +#define BIT_VI_FAST_EDCA_PKT_TH_8197F(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) +#define BITS_VI_FAST_EDCA_PKT_TH_8197F (BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8197F)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8197F(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F) +#define BIT_SET_VI_FAST_EDCA_PKT_TH_8197F(x, v) (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) | BIT_VI_FAST_EDCA_PKT_TH_8197F(v)) + + +#define BIT_SHIFT_VO_FAST_EDCA_TO_8197F 8 +#define BIT_MASK_VO_FAST_EDCA_TO_8197F 0xff +#define BIT_VO_FAST_EDCA_TO_8197F(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8197F) << BIT_SHIFT_VO_FAST_EDCA_TO_8197F) +#define BITS_VO_FAST_EDCA_TO_8197F (BIT_MASK_VO_FAST_EDCA_TO_8197F << BIT_SHIFT_VO_FAST_EDCA_TO_8197F) +#define BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8197F)) +#define BIT_GET_VO_FAST_EDCA_TO_8197F(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8197F) & BIT_MASK_VO_FAST_EDCA_TO_8197F) +#define BIT_SET_VO_FAST_EDCA_TO_8197F(x, v) (BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) | BIT_VO_FAST_EDCA_TO_8197F(v)) + +#define BIT_VO_THRESHOLD_SEL_8197F BIT(7) + +#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F 0 +#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F 0x7f +#define BIT_VO_FAST_EDCA_PKT_TH_8197F(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) +#define BITS_VO_FAST_EDCA_PKT_TH_8197F (BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8197F)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8197F(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F) +#define BIT_SET_VO_FAST_EDCA_PKT_TH_8197F(x, v) (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) | BIT_VO_FAST_EDCA_PKT_TH_8197F(v)) + + +/* 2 REG_FAST_EDCA_BEBK_SETTING_8197F */ + +#define BIT_SHIFT_BK_FAST_EDCA_TO_8197F 24 +#define BIT_MASK_BK_FAST_EDCA_TO_8197F 0xff +#define BIT_BK_FAST_EDCA_TO_8197F(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8197F) << BIT_SHIFT_BK_FAST_EDCA_TO_8197F) +#define BITS_BK_FAST_EDCA_TO_8197F (BIT_MASK_BK_FAST_EDCA_TO_8197F << BIT_SHIFT_BK_FAST_EDCA_TO_8197F) +#define BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8197F)) +#define BIT_GET_BK_FAST_EDCA_TO_8197F(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8197F) & BIT_MASK_BK_FAST_EDCA_TO_8197F) +#define BIT_SET_BK_FAST_EDCA_TO_8197F(x, v) (BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) | BIT_BK_FAST_EDCA_TO_8197F(v)) + +#define BIT_BK_THRESHOLD_SEL_8197F BIT(23) + +#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F 16 +#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F 0x7f +#define BIT_BK_FAST_EDCA_PKT_TH_8197F(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) +#define BITS_BK_FAST_EDCA_PKT_TH_8197F (BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8197F)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8197F(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F) +#define BIT_SET_BK_FAST_EDCA_PKT_TH_8197F(x, v) (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) | BIT_BK_FAST_EDCA_PKT_TH_8197F(v)) + + +#define BIT_SHIFT_BE_FAST_EDCA_TO_8197F 8 +#define BIT_MASK_BE_FAST_EDCA_TO_8197F 0xff +#define BIT_BE_FAST_EDCA_TO_8197F(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8197F) << BIT_SHIFT_BE_FAST_EDCA_TO_8197F) +#define BITS_BE_FAST_EDCA_TO_8197F (BIT_MASK_BE_FAST_EDCA_TO_8197F << BIT_SHIFT_BE_FAST_EDCA_TO_8197F) +#define BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8197F)) +#define BIT_GET_BE_FAST_EDCA_TO_8197F(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8197F) & BIT_MASK_BE_FAST_EDCA_TO_8197F) +#define BIT_SET_BE_FAST_EDCA_TO_8197F(x, v) (BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) | BIT_BE_FAST_EDCA_TO_8197F(v)) + +#define BIT_BE_THRESHOLD_SEL_8197F BIT(7) + +#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F 0 +#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F 0x7f +#define BIT_BE_FAST_EDCA_PKT_TH_8197F(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) +#define BITS_BE_FAST_EDCA_PKT_TH_8197F (BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8197F)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8197F(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F) +#define BIT_SET_BE_FAST_EDCA_PKT_TH_8197F(x, v) (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) | BIT_BE_FAST_EDCA_PKT_TH_8197F(v)) + + +/* 2 REG_MACID_DROP0_8197F */ + +#define BIT_SHIFT_MACID31_0_DROP_8197F 0 +#define BIT_MASK_MACID31_0_DROP_8197F 0xffffffffL +#define BIT_MACID31_0_DROP_8197F(x) (((x) & BIT_MASK_MACID31_0_DROP_8197F) << BIT_SHIFT_MACID31_0_DROP_8197F) +#define BITS_MACID31_0_DROP_8197F (BIT_MASK_MACID31_0_DROP_8197F << BIT_SHIFT_MACID31_0_DROP_8197F) +#define BIT_CLEAR_MACID31_0_DROP_8197F(x) ((x) & (~BITS_MACID31_0_DROP_8197F)) +#define BIT_GET_MACID31_0_DROP_8197F(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8197F) & BIT_MASK_MACID31_0_DROP_8197F) +#define BIT_SET_MACID31_0_DROP_8197F(x, v) (BIT_CLEAR_MACID31_0_DROP_8197F(x) | BIT_MACID31_0_DROP_8197F(v)) + + +/* 2 REG_MACID_DROP1_8197F */ + +#define BIT_SHIFT_MACID63_32_DROP_8197F 0 +#define BIT_MASK_MACID63_32_DROP_8197F 0xffffffffL +#define BIT_MACID63_32_DROP_8197F(x) (((x) & BIT_MASK_MACID63_32_DROP_8197F) << BIT_SHIFT_MACID63_32_DROP_8197F) +#define BITS_MACID63_32_DROP_8197F (BIT_MASK_MACID63_32_DROP_8197F << BIT_SHIFT_MACID63_32_DROP_8197F) +#define BIT_CLEAR_MACID63_32_DROP_8197F(x) ((x) & (~BITS_MACID63_32_DROP_8197F)) +#define BIT_GET_MACID63_32_DROP_8197F(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8197F) & BIT_MASK_MACID63_32_DROP_8197F) +#define BIT_SET_MACID63_32_DROP_8197F(x, v) (BIT_CLEAR_MACID63_32_DROP_8197F(x) | BIT_MACID63_32_DROP_8197F(v)) + + +/* 2 REG_MACID_DROP2_8197F */ + +#define BIT_SHIFT_MACID95_64_DROP_8197F 0 +#define BIT_MASK_MACID95_64_DROP_8197F 0xffffffffL +#define BIT_MACID95_64_DROP_8197F(x) (((x) & BIT_MASK_MACID95_64_DROP_8197F) << BIT_SHIFT_MACID95_64_DROP_8197F) +#define BITS_MACID95_64_DROP_8197F (BIT_MASK_MACID95_64_DROP_8197F << BIT_SHIFT_MACID95_64_DROP_8197F) +#define BIT_CLEAR_MACID95_64_DROP_8197F(x) ((x) & (~BITS_MACID95_64_DROP_8197F)) +#define BIT_GET_MACID95_64_DROP_8197F(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8197F) & BIT_MASK_MACID95_64_DROP_8197F) +#define BIT_SET_MACID95_64_DROP_8197F(x, v) (BIT_CLEAR_MACID95_64_DROP_8197F(x) | BIT_MACID95_64_DROP_8197F(v)) + + +/* 2 REG_MACID_DROP3_8197F */ + +#define BIT_SHIFT_MACID127_96_DROP_8197F 0 +#define BIT_MASK_MACID127_96_DROP_8197F 0xffffffffL +#define BIT_MACID127_96_DROP_8197F(x) (((x) & BIT_MASK_MACID127_96_DROP_8197F) << BIT_SHIFT_MACID127_96_DROP_8197F) +#define BITS_MACID127_96_DROP_8197F (BIT_MASK_MACID127_96_DROP_8197F << BIT_SHIFT_MACID127_96_DROP_8197F) +#define BIT_CLEAR_MACID127_96_DROP_8197F(x) ((x) & (~BITS_MACID127_96_DROP_8197F)) +#define BIT_GET_MACID127_96_DROP_8197F(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8197F) & BIT_MASK_MACID127_96_DROP_8197F) +#define BIT_SET_MACID127_96_DROP_8197F(x, v) (BIT_CLEAR_MACID127_96_DROP_8197F(x) | BIT_MACID127_96_DROP_8197F(v)) + + +/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8197F */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_0_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_0_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_0_8197F(v)) + + +/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8197F */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_1_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_1_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_1_8197F(v)) + + +/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8197F */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_2_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_2_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_2_8197F(v)) + + +/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8197F */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_3_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_3_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_3_8197F(v)) + + +/* 2 REG_MGG_FIFO_CRTL_8197F */ +#define BIT_R_MGG_FIFO_EN_8197F BIT(31) + +#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F 28 +#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F 0x7 +#define BIT_R_MGG_FIFO_PG_SIZE_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) +#define BITS_R_MGG_FIFO_PG_SIZE_8197F (BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) +#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) ((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8197F)) +#define BIT_GET_R_MGG_FIFO_PG_SIZE_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F) +#define BIT_SET_R_MGG_FIFO_PG_SIZE_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) | BIT_R_MGG_FIFO_PG_SIZE_8197F(v)) + + +#define BIT_SHIFT_R_MGG_FIFO_START_PG_8197F 16 +#define BIT_MASK_R_MGG_FIFO_START_PG_8197F 0xfff +#define BIT_R_MGG_FIFO_START_PG_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8197F) << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) +#define BITS_R_MGG_FIFO_START_PG_8197F (BIT_MASK_R_MGG_FIFO_START_PG_8197F << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) +#define BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) ((x) & (~BITS_R_MGG_FIFO_START_PG_8197F)) +#define BIT_GET_R_MGG_FIFO_START_PG_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) & BIT_MASK_R_MGG_FIFO_START_PG_8197F) +#define BIT_SET_R_MGG_FIFO_START_PG_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) | BIT_R_MGG_FIFO_START_PG_8197F(v)) + + +#define BIT_SHIFT_R_MGG_FIFO_SIZE_8197F 14 +#define BIT_MASK_R_MGG_FIFO_SIZE_8197F 0x3 +#define BIT_R_MGG_FIFO_SIZE_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8197F) << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) +#define BITS_R_MGG_FIFO_SIZE_8197F (BIT_MASK_R_MGG_FIFO_SIZE_8197F << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) +#define BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) ((x) & (~BITS_R_MGG_FIFO_SIZE_8197F)) +#define BIT_GET_R_MGG_FIFO_SIZE_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) & BIT_MASK_R_MGG_FIFO_SIZE_8197F) +#define BIT_SET_R_MGG_FIFO_SIZE_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) | BIT_R_MGG_FIFO_SIZE_8197F(v)) + +#define BIT_R_MGG_FIFO_PAUSE_8197F BIT(13) + +#define BIT_SHIFT_R_MGG_FIFO_RPTR_8197F 8 +#define BIT_MASK_R_MGG_FIFO_RPTR_8197F 0x1f +#define BIT_R_MGG_FIFO_RPTR_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8197F) << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) +#define BITS_R_MGG_FIFO_RPTR_8197F (BIT_MASK_R_MGG_FIFO_RPTR_8197F << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) +#define BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) ((x) & (~BITS_R_MGG_FIFO_RPTR_8197F)) +#define BIT_GET_R_MGG_FIFO_RPTR_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) & BIT_MASK_R_MGG_FIFO_RPTR_8197F) +#define BIT_SET_R_MGG_FIFO_RPTR_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) | BIT_R_MGG_FIFO_RPTR_8197F(v)) + +#define BIT_R_MGG_FIFO_OV_8197F BIT(7) +#define BIT_R_MGG_FIFO_WPTR_ERROR_8197F BIT(6) +#define BIT_R_EN_CPU_LIFETIME_8197F BIT(5) + +#define BIT_SHIFT_R_MGG_FIFO_WPTR_8197F 0 +#define BIT_MASK_R_MGG_FIFO_WPTR_8197F 0x1f +#define BIT_R_MGG_FIFO_WPTR_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8197F) << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) +#define BITS_R_MGG_FIFO_WPTR_8197F (BIT_MASK_R_MGG_FIFO_WPTR_8197F << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) +#define BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) ((x) & (~BITS_R_MGG_FIFO_WPTR_8197F)) +#define BIT_GET_R_MGG_FIFO_WPTR_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) & BIT_MASK_R_MGG_FIFO_WPTR_8197F) +#define BIT_SET_R_MGG_FIFO_WPTR_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) | BIT_R_MGG_FIFO_WPTR_8197F(v)) + + +/* 2 REG_MGG_FIFO_INT_8197F */ + +#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F 16 +#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F 0xffff +#define BIT_R_MGG_FIFO_INT_FLAG_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) +#define BITS_R_MGG_FIFO_INT_FLAG_8197F (BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) +#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) ((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8197F)) +#define BIT_GET_R_MGG_FIFO_INT_FLAG_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F) +#define BIT_SET_R_MGG_FIFO_INT_FLAG_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) | BIT_R_MGG_FIFO_INT_FLAG_8197F(v)) + + +#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F 0 +#define BIT_MASK_R_MGG_FIFO_INT_MASK_8197F 0xffff +#define BIT_R_MGG_FIFO_INT_MASK_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8197F) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) +#define BITS_R_MGG_FIFO_INT_MASK_8197F (BIT_MASK_R_MGG_FIFO_INT_MASK_8197F << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) +#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) ((x) & (~BITS_R_MGG_FIFO_INT_MASK_8197F)) +#define BIT_GET_R_MGG_FIFO_INT_MASK_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) & BIT_MASK_R_MGG_FIFO_INT_MASK_8197F) +#define BIT_SET_R_MGG_FIFO_INT_MASK_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) | BIT_R_MGG_FIFO_INT_MASK_8197F(v)) + + +/* 2 REG_MGG_FIFO_LIFETIME_8197F */ + +#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F 16 +#define BIT_MASK_R_MGG_FIFO_LIFETIME_8197F 0xffff +#define BIT_R_MGG_FIFO_LIFETIME_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8197F) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) +#define BITS_R_MGG_FIFO_LIFETIME_8197F (BIT_MASK_R_MGG_FIFO_LIFETIME_8197F << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) +#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) ((x) & (~BITS_R_MGG_FIFO_LIFETIME_8197F)) +#define BIT_GET_R_MGG_FIFO_LIFETIME_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) & BIT_MASK_R_MGG_FIFO_LIFETIME_8197F) +#define BIT_SET_R_MGG_FIFO_LIFETIME_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) | BIT_R_MGG_FIFO_LIFETIME_8197F(v)) + + +#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F 0 +#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F 0xffff +#define BIT_R_MGG_FIFO_VALID_MAP_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) +#define BITS_R_MGG_FIFO_VALID_MAP_8197F (BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) +#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) ((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8197F)) +#define BIT_GET_R_MGG_FIFO_VALID_MAP_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F) +#define BIT_SET_R_MGG_FIFO_VALID_MAP_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) | BIT_R_MGG_FIFO_VALID_MAP_8197F(v)) + + +/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x7f +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(v)) + + +/* 2 REG_SHCUT_SETTING_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE0_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE1_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_SHCUT_LLC_OUI0_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_SHCUT_LLC_OUI1_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_SHCUT_LLC_OUI2_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_SHCUT_LLC_OUI3_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_CHNL_REF_RXNAV_8197F BIT(7) +#define BIT_CHNL_REF_VBON_8197F BIT(6) +#define BIT_CHNL_REF_EDCCA_8197F BIT(5) +#define BIT_RST_CHNL_BUSY_8197F BIT(3) +#define BIT_RST_CHNL_IDLE_8197F BIT(2) +#define BIT_CHNL_INFO_RST_8197F BIT(1) +#define BIT_ATM_AIRTIME_EN_8197F BIT(0) + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_CHNL_IDLE_TIME_8197F 0 +#define BIT_MASK_CHNL_IDLE_TIME_8197F 0xffffffffL +#define BIT_CHNL_IDLE_TIME_8197F(x) (((x) & BIT_MASK_CHNL_IDLE_TIME_8197F) << BIT_SHIFT_CHNL_IDLE_TIME_8197F) +#define BITS_CHNL_IDLE_TIME_8197F (BIT_MASK_CHNL_IDLE_TIME_8197F << BIT_SHIFT_CHNL_IDLE_TIME_8197F) +#define BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) ((x) & (~BITS_CHNL_IDLE_TIME_8197F)) +#define BIT_GET_CHNL_IDLE_TIME_8197F(x) (((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8197F) & BIT_MASK_CHNL_IDLE_TIME_8197F) +#define BIT_SET_CHNL_IDLE_TIME_8197F(x, v) (BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) | BIT_CHNL_IDLE_TIME_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_CHNL_BUSY_TIME_8197F 0 +#define BIT_MASK_CHNL_BUSY_TIME_8197F 0xffffffffL +#define BIT_CHNL_BUSY_TIME_8197F(x) (((x) & BIT_MASK_CHNL_BUSY_TIME_8197F) << BIT_SHIFT_CHNL_BUSY_TIME_8197F) +#define BITS_CHNL_BUSY_TIME_8197F (BIT_MASK_CHNL_BUSY_TIME_8197F << BIT_SHIFT_CHNL_BUSY_TIME_8197F) +#define BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) ((x) & (~BITS_CHNL_BUSY_TIME_8197F)) +#define BIT_GET_CHNL_BUSY_TIME_8197F(x) (((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8197F) & BIT_MASK_CHNL_BUSY_TIME_8197F) +#define BIT_SET_CHNL_BUSY_TIME_8197F(x, v) (BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) | BIT_CHNL_BUSY_TIME_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_EDCA_VO_PARAM_8197F */ + +#define BIT_SHIFT_TXOPLIMIT_8197F 16 +#define BIT_MASK_TXOPLIMIT_8197F 0x7ff +#define BIT_TXOPLIMIT_8197F(x) (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) +#define BITS_TXOPLIMIT_8197F (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) +#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F)) +#define BIT_GET_TXOPLIMIT_8197F(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) +#define BIT_SET_TXOPLIMIT_8197F(x, v) (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) + + +#define BIT_SHIFT_CW_8197F 8 +#define BIT_MASK_CW_8197F 0xff +#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F) +#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F) +#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F)) +#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F) +#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v)) + + +#define BIT_SHIFT_AIFS_8197F 0 +#define BIT_MASK_AIFS_8197F 0xff +#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F) +#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F) +#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F)) +#define BIT_GET_AIFS_8197F(x) (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) +#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v)) + + +/* 2 REG_EDCA_VI_PARAM_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_TXOPLIMIT_8197F 16 +#define BIT_MASK_TXOPLIMIT_8197F 0x7ff +#define BIT_TXOPLIMIT_8197F(x) (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) +#define BITS_TXOPLIMIT_8197F (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) +#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F)) +#define BIT_GET_TXOPLIMIT_8197F(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) +#define BIT_SET_TXOPLIMIT_8197F(x, v) (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) + + +#define BIT_SHIFT_CW_8197F 8 +#define BIT_MASK_CW_8197F 0xff +#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F) +#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F) +#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F)) +#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F) +#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v)) + + +#define BIT_SHIFT_AIFS_8197F 0 +#define BIT_MASK_AIFS_8197F 0xff +#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F) +#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F) +#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F)) +#define BIT_GET_AIFS_8197F(x) (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) +#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v)) + + +/* 2 REG_EDCA_BE_PARAM_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_TXOPLIMIT_8197F 16 +#define BIT_MASK_TXOPLIMIT_8197F 0x7ff +#define BIT_TXOPLIMIT_8197F(x) (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) +#define BITS_TXOPLIMIT_8197F (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) +#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F)) +#define BIT_GET_TXOPLIMIT_8197F(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) +#define BIT_SET_TXOPLIMIT_8197F(x, v) (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) + + +#define BIT_SHIFT_CW_8197F 8 +#define BIT_MASK_CW_8197F 0xff +#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F) +#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F) +#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F)) +#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F) +#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v)) + + +#define BIT_SHIFT_AIFS_8197F 0 +#define BIT_MASK_AIFS_8197F 0xff +#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F) +#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F) +#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F)) +#define BIT_GET_AIFS_8197F(x) (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) +#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v)) + + +/* 2 REG_EDCA_BK_PARAM_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_TXOPLIMIT_8197F 16 +#define BIT_MASK_TXOPLIMIT_8197F 0x7ff +#define BIT_TXOPLIMIT_8197F(x) (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) +#define BITS_TXOPLIMIT_8197F (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) +#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F)) +#define BIT_GET_TXOPLIMIT_8197F(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) +#define BIT_SET_TXOPLIMIT_8197F(x, v) (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) + + +#define BIT_SHIFT_CW_8197F 8 +#define BIT_MASK_CW_8197F 0xff +#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F) +#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F) +#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F)) +#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F) +#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v)) + + +#define BIT_SHIFT_AIFS_8197F 0 +#define BIT_MASK_AIFS_8197F 0xff +#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F) +#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F) +#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F)) +#define BIT_GET_AIFS_8197F(x) (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) +#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v)) + + +/* 2 REG_BCNTCFG_8197F */ + +#define BIT_SHIFT_BCNCW_MAX_8197F 12 +#define BIT_MASK_BCNCW_MAX_8197F 0xf +#define BIT_BCNCW_MAX_8197F(x) (((x) & BIT_MASK_BCNCW_MAX_8197F) << BIT_SHIFT_BCNCW_MAX_8197F) +#define BITS_BCNCW_MAX_8197F (BIT_MASK_BCNCW_MAX_8197F << BIT_SHIFT_BCNCW_MAX_8197F) +#define BIT_CLEAR_BCNCW_MAX_8197F(x) ((x) & (~BITS_BCNCW_MAX_8197F)) +#define BIT_GET_BCNCW_MAX_8197F(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8197F) & BIT_MASK_BCNCW_MAX_8197F) +#define BIT_SET_BCNCW_MAX_8197F(x, v) (BIT_CLEAR_BCNCW_MAX_8197F(x) | BIT_BCNCW_MAX_8197F(v)) + + +#define BIT_SHIFT_BCNCW_MIN_8197F 8 +#define BIT_MASK_BCNCW_MIN_8197F 0xf +#define BIT_BCNCW_MIN_8197F(x) (((x) & BIT_MASK_BCNCW_MIN_8197F) << BIT_SHIFT_BCNCW_MIN_8197F) +#define BITS_BCNCW_MIN_8197F (BIT_MASK_BCNCW_MIN_8197F << BIT_SHIFT_BCNCW_MIN_8197F) +#define BIT_CLEAR_BCNCW_MIN_8197F(x) ((x) & (~BITS_BCNCW_MIN_8197F)) +#define BIT_GET_BCNCW_MIN_8197F(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8197F) & BIT_MASK_BCNCW_MIN_8197F) +#define BIT_SET_BCNCW_MIN_8197F(x, v) (BIT_CLEAR_BCNCW_MIN_8197F(x) | BIT_BCNCW_MIN_8197F(v)) + + +#define BIT_SHIFT_BCNIFS_8197F 0 +#define BIT_MASK_BCNIFS_8197F 0xff +#define BIT_BCNIFS_8197F(x) (((x) & BIT_MASK_BCNIFS_8197F) << BIT_SHIFT_BCNIFS_8197F) +#define BITS_BCNIFS_8197F (BIT_MASK_BCNIFS_8197F << BIT_SHIFT_BCNIFS_8197F) +#define BIT_CLEAR_BCNIFS_8197F(x) ((x) & (~BITS_BCNIFS_8197F)) +#define BIT_GET_BCNIFS_8197F(x) (((x) >> BIT_SHIFT_BCNIFS_8197F) & BIT_MASK_BCNIFS_8197F) +#define BIT_SET_BCNIFS_8197F(x, v) (BIT_CLEAR_BCNIFS_8197F(x) | BIT_BCNIFS_8197F(v)) + + +/* 2 REG_PIFS_8197F */ + +#define BIT_SHIFT_PIFS_8197F 0 +#define BIT_MASK_PIFS_8197F 0xff +#define BIT_PIFS_8197F(x) (((x) & BIT_MASK_PIFS_8197F) << BIT_SHIFT_PIFS_8197F) +#define BITS_PIFS_8197F (BIT_MASK_PIFS_8197F << BIT_SHIFT_PIFS_8197F) +#define BIT_CLEAR_PIFS_8197F(x) ((x) & (~BITS_PIFS_8197F)) +#define BIT_GET_PIFS_8197F(x) (((x) >> BIT_SHIFT_PIFS_8197F) & BIT_MASK_PIFS_8197F) +#define BIT_SET_PIFS_8197F(x, v) (BIT_CLEAR_PIFS_8197F(x) | BIT_PIFS_8197F(v)) + + +/* 2 REG_RDG_PIFS_8197F */ + +#define BIT_SHIFT_RDG_PIFS_8197F 0 +#define BIT_MASK_RDG_PIFS_8197F 0xff +#define BIT_RDG_PIFS_8197F(x) (((x) & BIT_MASK_RDG_PIFS_8197F) << BIT_SHIFT_RDG_PIFS_8197F) +#define BITS_RDG_PIFS_8197F (BIT_MASK_RDG_PIFS_8197F << BIT_SHIFT_RDG_PIFS_8197F) +#define BIT_CLEAR_RDG_PIFS_8197F(x) ((x) & (~BITS_RDG_PIFS_8197F)) +#define BIT_GET_RDG_PIFS_8197F(x) (((x) >> BIT_SHIFT_RDG_PIFS_8197F) & BIT_MASK_RDG_PIFS_8197F) +#define BIT_SET_RDG_PIFS_8197F(x, v) (BIT_CLEAR_RDG_PIFS_8197F(x) | BIT_RDG_PIFS_8197F(v)) + + +/* 2 REG_SIFS_8197F */ + +#define BIT_SHIFT_SIFS_OFDM_TRX_8197F 24 +#define BIT_MASK_SIFS_OFDM_TRX_8197F 0xff +#define BIT_SIFS_OFDM_TRX_8197F(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8197F) << BIT_SHIFT_SIFS_OFDM_TRX_8197F) +#define BITS_SIFS_OFDM_TRX_8197F (BIT_MASK_SIFS_OFDM_TRX_8197F << BIT_SHIFT_SIFS_OFDM_TRX_8197F) +#define BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) ((x) & (~BITS_SIFS_OFDM_TRX_8197F)) +#define BIT_GET_SIFS_OFDM_TRX_8197F(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8197F) & BIT_MASK_SIFS_OFDM_TRX_8197F) +#define BIT_SET_SIFS_OFDM_TRX_8197F(x, v) (BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) | BIT_SIFS_OFDM_TRX_8197F(v)) + + +#define BIT_SHIFT_SIFS_CCK_TRX_8197F 16 +#define BIT_MASK_SIFS_CCK_TRX_8197F 0xff +#define BIT_SIFS_CCK_TRX_8197F(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8197F) << BIT_SHIFT_SIFS_CCK_TRX_8197F) +#define BITS_SIFS_CCK_TRX_8197F (BIT_MASK_SIFS_CCK_TRX_8197F << BIT_SHIFT_SIFS_CCK_TRX_8197F) +#define BIT_CLEAR_SIFS_CCK_TRX_8197F(x) ((x) & (~BITS_SIFS_CCK_TRX_8197F)) +#define BIT_GET_SIFS_CCK_TRX_8197F(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8197F) & BIT_MASK_SIFS_CCK_TRX_8197F) +#define BIT_SET_SIFS_CCK_TRX_8197F(x, v) (BIT_CLEAR_SIFS_CCK_TRX_8197F(x) | BIT_SIFS_CCK_TRX_8197F(v)) + + +#define BIT_SHIFT_SIFS_OFDM_CTX_8197F 8 +#define BIT_MASK_SIFS_OFDM_CTX_8197F 0xff +#define BIT_SIFS_OFDM_CTX_8197F(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8197F) << BIT_SHIFT_SIFS_OFDM_CTX_8197F) +#define BITS_SIFS_OFDM_CTX_8197F (BIT_MASK_SIFS_OFDM_CTX_8197F << BIT_SHIFT_SIFS_OFDM_CTX_8197F) +#define BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) ((x) & (~BITS_SIFS_OFDM_CTX_8197F)) +#define BIT_GET_SIFS_OFDM_CTX_8197F(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8197F) & BIT_MASK_SIFS_OFDM_CTX_8197F) +#define BIT_SET_SIFS_OFDM_CTX_8197F(x, v) (BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) | BIT_SIFS_OFDM_CTX_8197F(v)) + + +#define BIT_SHIFT_SIFS_CCK_CTX_8197F 0 +#define BIT_MASK_SIFS_CCK_CTX_8197F 0xff +#define BIT_SIFS_CCK_CTX_8197F(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8197F) << BIT_SHIFT_SIFS_CCK_CTX_8197F) +#define BITS_SIFS_CCK_CTX_8197F (BIT_MASK_SIFS_CCK_CTX_8197F << BIT_SHIFT_SIFS_CCK_CTX_8197F) +#define BIT_CLEAR_SIFS_CCK_CTX_8197F(x) ((x) & (~BITS_SIFS_CCK_CTX_8197F)) +#define BIT_GET_SIFS_CCK_CTX_8197F(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8197F) & BIT_MASK_SIFS_CCK_CTX_8197F) +#define BIT_SET_SIFS_CCK_CTX_8197F(x, v) (BIT_CLEAR_SIFS_CCK_CTX_8197F(x) | BIT_SIFS_CCK_CTX_8197F(v)) + + +/* 2 REG_TSFTR_SYN_OFFSET_8197F */ + +#define BIT_SHIFT_TSFTR_SNC_OFFSET_8197F 0 +#define BIT_MASK_TSFTR_SNC_OFFSET_8197F 0xffff +#define BIT_TSFTR_SNC_OFFSET_8197F(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8197F) << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) +#define BITS_TSFTR_SNC_OFFSET_8197F (BIT_MASK_TSFTR_SNC_OFFSET_8197F << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) ((x) & (~BITS_TSFTR_SNC_OFFSET_8197F)) +#define BIT_GET_TSFTR_SNC_OFFSET_8197F(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) & BIT_MASK_TSFTR_SNC_OFFSET_8197F) +#define BIT_SET_TSFTR_SNC_OFFSET_8197F(x, v) (BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) | BIT_TSFTR_SNC_OFFSET_8197F(v)) + + +/* 2 REG_AGGR_BREAK_TIME_8197F */ + +#define BIT_SHIFT_AGGR_BK_TIME_8197F 0 +#define BIT_MASK_AGGR_BK_TIME_8197F 0xff +#define BIT_AGGR_BK_TIME_8197F(x) (((x) & BIT_MASK_AGGR_BK_TIME_8197F) << BIT_SHIFT_AGGR_BK_TIME_8197F) +#define BITS_AGGR_BK_TIME_8197F (BIT_MASK_AGGR_BK_TIME_8197F << BIT_SHIFT_AGGR_BK_TIME_8197F) +#define BIT_CLEAR_AGGR_BK_TIME_8197F(x) ((x) & (~BITS_AGGR_BK_TIME_8197F)) +#define BIT_GET_AGGR_BK_TIME_8197F(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8197F) & BIT_MASK_AGGR_BK_TIME_8197F) +#define BIT_SET_AGGR_BK_TIME_8197F(x, v) (BIT_CLEAR_AGGR_BK_TIME_8197F(x) | BIT_AGGR_BK_TIME_8197F(v)) + + +/* 2 REG_SLOT_8197F */ + +#define BIT_SHIFT_SLOT_8197F 0 +#define BIT_MASK_SLOT_8197F 0xff +#define BIT_SLOT_8197F(x) (((x) & BIT_MASK_SLOT_8197F) << BIT_SHIFT_SLOT_8197F) +#define BITS_SLOT_8197F (BIT_MASK_SLOT_8197F << BIT_SHIFT_SLOT_8197F) +#define BIT_CLEAR_SLOT_8197F(x) ((x) & (~BITS_SLOT_8197F)) +#define BIT_GET_SLOT_8197F(x) (((x) >> BIT_SHIFT_SLOT_8197F) & BIT_MASK_SLOT_8197F) +#define BIT_SET_SLOT_8197F(x, v) (BIT_CLEAR_SLOT_8197F(x) | BIT_SLOT_8197F(v)) + + +/* 2 REG_TX_PTCL_CTRL_8197F */ +#define BIT_DIS_EDCCA_8197F BIT(15) +#define BIT_DIS_CCA_8197F BIT(14) +#define BIT_LSIG_TXOP_TXCMD_NAV_8197F BIT(13) +#define BIT_SIFS_BK_EN_8197F BIT(12) + +#define BIT_SHIFT_TXQ_NAV_MSK_8197F 8 +#define BIT_MASK_TXQ_NAV_MSK_8197F 0xf +#define BIT_TXQ_NAV_MSK_8197F(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8197F) << BIT_SHIFT_TXQ_NAV_MSK_8197F) +#define BITS_TXQ_NAV_MSK_8197F (BIT_MASK_TXQ_NAV_MSK_8197F << BIT_SHIFT_TXQ_NAV_MSK_8197F) +#define BIT_CLEAR_TXQ_NAV_MSK_8197F(x) ((x) & (~BITS_TXQ_NAV_MSK_8197F)) +#define BIT_GET_TXQ_NAV_MSK_8197F(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8197F) & BIT_MASK_TXQ_NAV_MSK_8197F) +#define BIT_SET_TXQ_NAV_MSK_8197F(x, v) (BIT_CLEAR_TXQ_NAV_MSK_8197F(x) | BIT_TXQ_NAV_MSK_8197F(v)) + +#define BIT_DIS_CW_8197F BIT(7) +#define BIT_NAV_END_TXOP_8197F BIT(6) +#define BIT_RDG_END_TXOP_8197F BIT(5) +#define BIT_AC_INBCN_HOLD_8197F BIT(4) +#define BIT_MGTQ_TXOP_EN_8197F BIT(3) +#define BIT_MGTQ_RTSMF_EN_8197F BIT(2) +#define BIT_HIQ_RTSMF_EN_8197F BIT(1) +#define BIT_BCN_RTSMF_EN_8197F BIT(0) + +/* 2 REG_TXPAUSE_8197F */ +#define BIT_STOP_BCN_HI_MGT_8197F BIT(7) +#define BIT_MAC_STOPBCNQ_8197F BIT(6) +#define BIT_MAC_STOPHIQ_8197F BIT(5) +#define BIT_MAC_STOPMGQ_8197F BIT(4) +#define BIT_MAC_STOPBK_8197F BIT(3) +#define BIT_MAC_STOPBE_8197F BIT(2) +#define BIT_MAC_STOPVI_8197F BIT(1) +#define BIT_MAC_STOPVO_8197F BIT(0) + +/* 2 REG_DIS_TXREQ_CLR_8197F */ +#define BIT_DIS_BT_CCA_8197F BIT(7) +#define BIT_DIS_TXREQ_CLR_CPUMGQ_8197F BIT(6) +#define BIT_DIS_TXREQ_CLR_HI_8197F BIT(5) +#define BIT_DIS_TXREQ_CLR_MGQ_8197F BIT(4) +#define BIT_DIS_TXREQ_CLR_VO_8197F BIT(3) +#define BIT_DIS_TXREQ_CLR_VI_8197F BIT(2) +#define BIT_DIS_TXREQ_CLR_BE_8197F BIT(1) +#define BIT_DIS_TXREQ_CLR_BK_8197F BIT(0) + +/* 2 REG_RD_CTRL_8197F */ +#define BIT_EN_CLR_TXREQ_INCCA_8197F BIT(15) +#define BIT_DIS_TX_OVER_BCNQ_8197F BIT(14) +#define BIT_EN_BCNERR_INCCA_8197F BIT(13) +#define BIT_EN_BCNERR_INEDCCA_8197F BIT(12) +#define BIT_EDCCA_MSK_CNTDOWN_EN_8197F BIT(11) +#define BIT_DIS_TXOP_CFE_8197F BIT(10) +#define BIT_DIS_LSIG_CFE_8197F BIT(9) +#define BIT_DIS_STBC_CFE_8197F BIT(8) +#define BIT_BKQ_RD_INIT_EN_8197F BIT(7) +#define BIT_BEQ_RD_INIT_EN_8197F BIT(6) +#define BIT_VIQ_RD_INIT_EN_8197F BIT(5) +#define BIT_VOQ_RD_INIT_EN_8197F BIT(4) +#define BIT_BKQ_RD_RESP_EN_8197F BIT(3) +#define BIT_BEQ_RD_RESP_EN_8197F BIT(2) +#define BIT_VIQ_RD_RESP_EN_8197F BIT(1) +#define BIT_VOQ_RD_RESP_EN_8197F BIT(0) + +/* 2 REG_MBSSID_CTRL_8197F */ +#define BIT_MBID_BCNQ7_EN_8197F BIT(7) +#define BIT_MBID_BCNQ6_EN_8197F BIT(6) +#define BIT_MBID_BCNQ5_EN_8197F BIT(5) +#define BIT_MBID_BCNQ4_EN_8197F BIT(4) +#define BIT_MBID_BCNQ3_EN_8197F BIT(3) +#define BIT_MBID_BCNQ2_EN_8197F BIT(2) +#define BIT_MBID_BCNQ1_EN_8197F BIT(1) +#define BIT_MBID_BCNQ0_EN_8197F BIT(0) + +/* 2 REG_P2PPS_CTRL_8197F */ +#define BIT_P2P_CTW_ALLSTASLEEP_8197F BIT(7) +#define BIT_P2P_OFF_DISTX_EN_8197F BIT(6) +#define BIT_PWR_MGT_EN_8197F BIT(5) +#define BIT_P2P_NOA1_EN_8197F BIT(2) +#define BIT_P2P_NOA0_EN_8197F BIT(1) + +/* 2 REG_PKT_LIFETIME_CTRL_8197F */ +#define BIT_EN_TBTT_AREA_FOR_BB_8197F BIT(23) +#define BIT_EN_BKF_CLR_TXREQ_8197F BIT(22) +#define BIT_EN_TSFBIT32_RST_P2P_8197F BIT(21) +#define BIT_EN_BCN_TX_BTCCA_8197F BIT(20) +#define BIT_DIS_PKT_TX_ATIM_8197F BIT(19) +#define BIT_DIS_BCN_DIS_CTN_8197F BIT(18) +#define BIT_EN_NAVEND_RST_TXOP_8197F BIT(17) +#define BIT_EN_FILTER_CCA_8197F BIT(16) + +#define BIT_SHIFT_CCA_FILTER_THRS_8197F 8 +#define BIT_MASK_CCA_FILTER_THRS_8197F 0xff +#define BIT_CCA_FILTER_THRS_8197F(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8197F) << BIT_SHIFT_CCA_FILTER_THRS_8197F) +#define BITS_CCA_FILTER_THRS_8197F (BIT_MASK_CCA_FILTER_THRS_8197F << BIT_SHIFT_CCA_FILTER_THRS_8197F) +#define BIT_CLEAR_CCA_FILTER_THRS_8197F(x) ((x) & (~BITS_CCA_FILTER_THRS_8197F)) +#define BIT_GET_CCA_FILTER_THRS_8197F(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8197F) & BIT_MASK_CCA_FILTER_THRS_8197F) +#define BIT_SET_CCA_FILTER_THRS_8197F(x, v) (BIT_CLEAR_CCA_FILTER_THRS_8197F(x) | BIT_CCA_FILTER_THRS_8197F(v)) + + +#define BIT_SHIFT_EDCCA_THRS_8197F 0 +#define BIT_MASK_EDCCA_THRS_8197F 0xff +#define BIT_EDCCA_THRS_8197F(x) (((x) & BIT_MASK_EDCCA_THRS_8197F) << BIT_SHIFT_EDCCA_THRS_8197F) +#define BITS_EDCCA_THRS_8197F (BIT_MASK_EDCCA_THRS_8197F << BIT_SHIFT_EDCCA_THRS_8197F) +#define BIT_CLEAR_EDCCA_THRS_8197F(x) ((x) & (~BITS_EDCCA_THRS_8197F)) +#define BIT_GET_EDCCA_THRS_8197F(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8197F) & BIT_MASK_EDCCA_THRS_8197F) +#define BIT_SET_EDCCA_THRS_8197F(x, v) (BIT_CLEAR_EDCCA_THRS_8197F(x) | BIT_EDCCA_THRS_8197F(v)) + + +/* 2 REG_P2PPS_SPEC_STATE_8197F */ +#define BIT_SPEC_POWER_STATE_8197F BIT(7) +#define BIT_SPEC_CTWINDOW_ON_8197F BIT(6) +#define BIT_SPEC_BEACON_AREA_ON_8197F BIT(5) +#define BIT_SPEC_CTWIN_EARLY_DISTX_8197F BIT(4) +#define BIT_SPEC_NOA1_OFF_PERIOD_8197F BIT(3) +#define BIT_SPEC_FORCE_DOZE1_8197F BIT(2) +#define BIT_SPEC_NOA0_OFF_PERIOD_8197F BIT(1) +#define BIT_SPEC_FORCE_DOZE0_8197F BIT(0) + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_P2PON_DIS_TXTIME_8197F 0 +#define BIT_MASK_P2PON_DIS_TXTIME_8197F 0xff +#define BIT_P2PON_DIS_TXTIME_8197F(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8197F) << BIT_SHIFT_P2PON_DIS_TXTIME_8197F) +#define BITS_P2PON_DIS_TXTIME_8197F (BIT_MASK_P2PON_DIS_TXTIME_8197F << BIT_SHIFT_P2PON_DIS_TXTIME_8197F) +#define BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) ((x) & (~BITS_P2PON_DIS_TXTIME_8197F)) +#define BIT_GET_P2PON_DIS_TXTIME_8197F(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8197F) & BIT_MASK_P2PON_DIS_TXTIME_8197F) +#define BIT_SET_P2PON_DIS_TXTIME_8197F(x, v) (BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) | BIT_P2PON_DIS_TXTIME_8197F(v)) + + +/* 2 REG_QUEUE_INCOL_THR_8197F */ + +#define BIT_SHIFT_BK_QUEUE_THR_8197F 24 +#define BIT_MASK_BK_QUEUE_THR_8197F 0xff +#define BIT_BK_QUEUE_THR_8197F(x) (((x) & BIT_MASK_BK_QUEUE_THR_8197F) << BIT_SHIFT_BK_QUEUE_THR_8197F) +#define BITS_BK_QUEUE_THR_8197F (BIT_MASK_BK_QUEUE_THR_8197F << BIT_SHIFT_BK_QUEUE_THR_8197F) +#define BIT_CLEAR_BK_QUEUE_THR_8197F(x) ((x) & (~BITS_BK_QUEUE_THR_8197F)) +#define BIT_GET_BK_QUEUE_THR_8197F(x) (((x) >> BIT_SHIFT_BK_QUEUE_THR_8197F) & BIT_MASK_BK_QUEUE_THR_8197F) +#define BIT_SET_BK_QUEUE_THR_8197F(x, v) (BIT_CLEAR_BK_QUEUE_THR_8197F(x) | BIT_BK_QUEUE_THR_8197F(v)) + + +#define BIT_SHIFT_BE_QUEUE_THR_8197F 16 +#define BIT_MASK_BE_QUEUE_THR_8197F 0xff +#define BIT_BE_QUEUE_THR_8197F(x) (((x) & BIT_MASK_BE_QUEUE_THR_8197F) << BIT_SHIFT_BE_QUEUE_THR_8197F) +#define BITS_BE_QUEUE_THR_8197F (BIT_MASK_BE_QUEUE_THR_8197F << BIT_SHIFT_BE_QUEUE_THR_8197F) +#define BIT_CLEAR_BE_QUEUE_THR_8197F(x) ((x) & (~BITS_BE_QUEUE_THR_8197F)) +#define BIT_GET_BE_QUEUE_THR_8197F(x) (((x) >> BIT_SHIFT_BE_QUEUE_THR_8197F) & BIT_MASK_BE_QUEUE_THR_8197F) +#define BIT_SET_BE_QUEUE_THR_8197F(x, v) (BIT_CLEAR_BE_QUEUE_THR_8197F(x) | BIT_BE_QUEUE_THR_8197F(v)) + + +#define BIT_SHIFT_VI_QUEUE_THR_8197F 8 +#define BIT_MASK_VI_QUEUE_THR_8197F 0xff +#define BIT_VI_QUEUE_THR_8197F(x) (((x) & BIT_MASK_VI_QUEUE_THR_8197F) << BIT_SHIFT_VI_QUEUE_THR_8197F) +#define BITS_VI_QUEUE_THR_8197F (BIT_MASK_VI_QUEUE_THR_8197F << BIT_SHIFT_VI_QUEUE_THR_8197F) +#define BIT_CLEAR_VI_QUEUE_THR_8197F(x) ((x) & (~BITS_VI_QUEUE_THR_8197F)) +#define BIT_GET_VI_QUEUE_THR_8197F(x) (((x) >> BIT_SHIFT_VI_QUEUE_THR_8197F) & BIT_MASK_VI_QUEUE_THR_8197F) +#define BIT_SET_VI_QUEUE_THR_8197F(x, v) (BIT_CLEAR_VI_QUEUE_THR_8197F(x) | BIT_VI_QUEUE_THR_8197F(v)) + + +#define BIT_SHIFT_VO_QUEUE_THR_8197F 0 +#define BIT_MASK_VO_QUEUE_THR_8197F 0xff +#define BIT_VO_QUEUE_THR_8197F(x) (((x) & BIT_MASK_VO_QUEUE_THR_8197F) << BIT_SHIFT_VO_QUEUE_THR_8197F) +#define BITS_VO_QUEUE_THR_8197F (BIT_MASK_VO_QUEUE_THR_8197F << BIT_SHIFT_VO_QUEUE_THR_8197F) +#define BIT_CLEAR_VO_QUEUE_THR_8197F(x) ((x) & (~BITS_VO_QUEUE_THR_8197F)) +#define BIT_GET_VO_QUEUE_THR_8197F(x) (((x) >> BIT_SHIFT_VO_QUEUE_THR_8197F) & BIT_MASK_VO_QUEUE_THR_8197F) +#define BIT_SET_VO_QUEUE_THR_8197F(x, v) (BIT_CLEAR_VO_QUEUE_THR_8197F(x) | BIT_VO_QUEUE_THR_8197F(v)) + + +/* 2 REG_QUEUE_INCOL_EN_8197F */ +#define BIT_QUEUE_INCOL_EN_8197F BIT(16) + +#define BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F 12 +#define BIT_MASK_BK_TRIGGER_NUM_V1_8197F 0xf +#define BIT_BK_TRIGGER_NUM_V1_8197F(x) (((x) & BIT_MASK_BK_TRIGGER_NUM_V1_8197F) << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) +#define BITS_BK_TRIGGER_NUM_V1_8197F (BIT_MASK_BK_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) +#define BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) ((x) & (~BITS_BK_TRIGGER_NUM_V1_8197F)) +#define BIT_GET_BK_TRIGGER_NUM_V1_8197F(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) & BIT_MASK_BK_TRIGGER_NUM_V1_8197F) +#define BIT_SET_BK_TRIGGER_NUM_V1_8197F(x, v) (BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) | BIT_BK_TRIGGER_NUM_V1_8197F(v)) + + +#define BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F 8 +#define BIT_MASK_BE_TRIGGER_NUM_V1_8197F 0xf +#define BIT_BE_TRIGGER_NUM_V1_8197F(x) (((x) & BIT_MASK_BE_TRIGGER_NUM_V1_8197F) << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) +#define BITS_BE_TRIGGER_NUM_V1_8197F (BIT_MASK_BE_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) +#define BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) ((x) & (~BITS_BE_TRIGGER_NUM_V1_8197F)) +#define BIT_GET_BE_TRIGGER_NUM_V1_8197F(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) & BIT_MASK_BE_TRIGGER_NUM_V1_8197F) +#define BIT_SET_BE_TRIGGER_NUM_V1_8197F(x, v) (BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) | BIT_BE_TRIGGER_NUM_V1_8197F(v)) + + +#define BIT_SHIFT_VI_TRIGGER_NUM_8197F 4 +#define BIT_MASK_VI_TRIGGER_NUM_8197F 0xf +#define BIT_VI_TRIGGER_NUM_8197F(x) (((x) & BIT_MASK_VI_TRIGGER_NUM_8197F) << BIT_SHIFT_VI_TRIGGER_NUM_8197F) +#define BITS_VI_TRIGGER_NUM_8197F (BIT_MASK_VI_TRIGGER_NUM_8197F << BIT_SHIFT_VI_TRIGGER_NUM_8197F) +#define BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) ((x) & (~BITS_VI_TRIGGER_NUM_8197F)) +#define BIT_GET_VI_TRIGGER_NUM_8197F(x) (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8197F) & BIT_MASK_VI_TRIGGER_NUM_8197F) +#define BIT_SET_VI_TRIGGER_NUM_8197F(x, v) (BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) | BIT_VI_TRIGGER_NUM_8197F(v)) + + +#define BIT_SHIFT_VO_TRIGGER_NUM_8197F 0 +#define BIT_MASK_VO_TRIGGER_NUM_8197F 0xf +#define BIT_VO_TRIGGER_NUM_8197F(x) (((x) & BIT_MASK_VO_TRIGGER_NUM_8197F) << BIT_SHIFT_VO_TRIGGER_NUM_8197F) +#define BITS_VO_TRIGGER_NUM_8197F (BIT_MASK_VO_TRIGGER_NUM_8197F << BIT_SHIFT_VO_TRIGGER_NUM_8197F) +#define BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) ((x) & (~BITS_VO_TRIGGER_NUM_8197F)) +#define BIT_GET_VO_TRIGGER_NUM_8197F(x) (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8197F) & BIT_MASK_VO_TRIGGER_NUM_8197F) +#define BIT_SET_VO_TRIGGER_NUM_8197F(x, v) (BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) | BIT_VO_TRIGGER_NUM_8197F(v)) + + +/* 2 REG_TBTT_PROHIBIT_8197F */ + +#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F 8 +#define BIT_MASK_TBTT_HOLD_TIME_AP_8197F 0xfff +#define BIT_TBTT_HOLD_TIME_AP_8197F(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8197F) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) +#define BITS_TBTT_HOLD_TIME_AP_8197F (BIT_MASK_TBTT_HOLD_TIME_AP_8197F << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) +#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) ((x) & (~BITS_TBTT_HOLD_TIME_AP_8197F)) +#define BIT_GET_TBTT_HOLD_TIME_AP_8197F(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) & BIT_MASK_TBTT_HOLD_TIME_AP_8197F) +#define BIT_SET_TBTT_HOLD_TIME_AP_8197F(x, v) (BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) | BIT_TBTT_HOLD_TIME_AP_8197F(v)) + + +#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F 0 +#define BIT_MASK_TBTT_PROHIBIT_SETUP_8197F 0xf +#define BIT_TBTT_PROHIBIT_SETUP_8197F(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8197F) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) +#define BITS_TBTT_PROHIBIT_SETUP_8197F (BIT_MASK_TBTT_PROHIBIT_SETUP_8197F << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8197F)) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8197F(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) & BIT_MASK_TBTT_PROHIBIT_SETUP_8197F) +#define BIT_SET_TBTT_PROHIBIT_SETUP_8197F(x, v) (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) | BIT_TBTT_PROHIBIT_SETUP_8197F(v)) + + +/* 2 REG_P2PPS_STATE_8197F */ +#define BIT_POWER_STATE_8197F BIT(7) +#define BIT_CTWINDOW_ON_8197F BIT(6) +#define BIT_BEACON_AREA_ON_8197F BIT(5) +#define BIT_CTWIN_EARLY_DISTX_8197F BIT(4) +#define BIT_NOA1_OFF_PERIOD_8197F BIT(3) +#define BIT_FORCE_DOZE1_8197F BIT(2) +#define BIT_NOA0_OFF_PERIOD_8197F BIT(1) +#define BIT_FORCE_DOZE0_8197F BIT(0) + +/* 2 REG_RD_NAV_NXT_8197F */ + +#define BIT_SHIFT_RD_NAV_PROT_NXT_8197F 0 +#define BIT_MASK_RD_NAV_PROT_NXT_8197F 0xffff +#define BIT_RD_NAV_PROT_NXT_8197F(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8197F) << BIT_SHIFT_RD_NAV_PROT_NXT_8197F) +#define BITS_RD_NAV_PROT_NXT_8197F (BIT_MASK_RD_NAV_PROT_NXT_8197F << BIT_SHIFT_RD_NAV_PROT_NXT_8197F) +#define BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8197F)) +#define BIT_GET_RD_NAV_PROT_NXT_8197F(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8197F) & BIT_MASK_RD_NAV_PROT_NXT_8197F) +#define BIT_SET_RD_NAV_PROT_NXT_8197F(x, v) (BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) | BIT_RD_NAV_PROT_NXT_8197F(v)) + + +/* 2 REG_NAV_PROT_LEN_8197F */ + +#define BIT_SHIFT_NAV_PROT_LEN_8197F 0 +#define BIT_MASK_NAV_PROT_LEN_8197F 0xffff +#define BIT_NAV_PROT_LEN_8197F(x) (((x) & BIT_MASK_NAV_PROT_LEN_8197F) << BIT_SHIFT_NAV_PROT_LEN_8197F) +#define BITS_NAV_PROT_LEN_8197F (BIT_MASK_NAV_PROT_LEN_8197F << BIT_SHIFT_NAV_PROT_LEN_8197F) +#define BIT_CLEAR_NAV_PROT_LEN_8197F(x) ((x) & (~BITS_NAV_PROT_LEN_8197F)) +#define BIT_GET_NAV_PROT_LEN_8197F(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8197F) & BIT_MASK_NAV_PROT_LEN_8197F) +#define BIT_SET_NAV_PROT_LEN_8197F(x, v) (BIT_CLEAR_NAV_PROT_LEN_8197F(x) | BIT_NAV_PROT_LEN_8197F(v)) + + +/* 2 REG_FTM_CTRL_8197F */ + +#define BIT_SHIFT_FTM_TSF_R2T_PORT_8197F 22 +#define BIT_MASK_FTM_TSF_R2T_PORT_8197F 0x7 +#define BIT_FTM_TSF_R2T_PORT_8197F(x) (((x) & BIT_MASK_FTM_TSF_R2T_PORT_8197F) << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) +#define BITS_FTM_TSF_R2T_PORT_8197F (BIT_MASK_FTM_TSF_R2T_PORT_8197F << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) +#define BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) ((x) & (~BITS_FTM_TSF_R2T_PORT_8197F)) +#define BIT_GET_FTM_TSF_R2T_PORT_8197F(x) (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) & BIT_MASK_FTM_TSF_R2T_PORT_8197F) +#define BIT_SET_FTM_TSF_R2T_PORT_8197F(x, v) (BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) | BIT_FTM_TSF_R2T_PORT_8197F(v)) + + +#define BIT_SHIFT_FTM_TSF_T2R_PORT_8197F 19 +#define BIT_MASK_FTM_TSF_T2R_PORT_8197F 0x7 +#define BIT_FTM_TSF_T2R_PORT_8197F(x) (((x) & BIT_MASK_FTM_TSF_T2R_PORT_8197F) << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) +#define BITS_FTM_TSF_T2R_PORT_8197F (BIT_MASK_FTM_TSF_T2R_PORT_8197F << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) +#define BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) ((x) & (~BITS_FTM_TSF_T2R_PORT_8197F)) +#define BIT_GET_FTM_TSF_T2R_PORT_8197F(x) (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) & BIT_MASK_FTM_TSF_T2R_PORT_8197F) +#define BIT_SET_FTM_TSF_T2R_PORT_8197F(x, v) (BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) | BIT_FTM_TSF_T2R_PORT_8197F(v)) + + +#define BIT_SHIFT_FTM_PTT_PORT_8197F 16 +#define BIT_MASK_FTM_PTT_PORT_8197F 0x7 +#define BIT_FTM_PTT_PORT_8197F(x) (((x) & BIT_MASK_FTM_PTT_PORT_8197F) << BIT_SHIFT_FTM_PTT_PORT_8197F) +#define BITS_FTM_PTT_PORT_8197F (BIT_MASK_FTM_PTT_PORT_8197F << BIT_SHIFT_FTM_PTT_PORT_8197F) +#define BIT_CLEAR_FTM_PTT_PORT_8197F(x) ((x) & (~BITS_FTM_PTT_PORT_8197F)) +#define BIT_GET_FTM_PTT_PORT_8197F(x) (((x) >> BIT_SHIFT_FTM_PTT_PORT_8197F) & BIT_MASK_FTM_PTT_PORT_8197F) +#define BIT_SET_FTM_PTT_PORT_8197F(x, v) (BIT_CLEAR_FTM_PTT_PORT_8197F(x) | BIT_FTM_PTT_PORT_8197F(v)) + + +#define BIT_SHIFT_FTM_PTT_8197F 0 +#define BIT_MASK_FTM_PTT_8197F 0xffff +#define BIT_FTM_PTT_8197F(x) (((x) & BIT_MASK_FTM_PTT_8197F) << BIT_SHIFT_FTM_PTT_8197F) +#define BITS_FTM_PTT_8197F (BIT_MASK_FTM_PTT_8197F << BIT_SHIFT_FTM_PTT_8197F) +#define BIT_CLEAR_FTM_PTT_8197F(x) ((x) & (~BITS_FTM_PTT_8197F)) +#define BIT_GET_FTM_PTT_8197F(x) (((x) >> BIT_SHIFT_FTM_PTT_8197F) & BIT_MASK_FTM_PTT_8197F) +#define BIT_SET_FTM_PTT_8197F(x, v) (BIT_CLEAR_FTM_PTT_8197F(x) | BIT_FTM_PTT_8197F(v)) + + +/* 2 REG_FTM_TSF_CNT_8197F */ + +#define BIT_SHIFT_FTM_TSF_R2T_8197F 16 +#define BIT_MASK_FTM_TSF_R2T_8197F 0xffff +#define BIT_FTM_TSF_R2T_8197F(x) (((x) & BIT_MASK_FTM_TSF_R2T_8197F) << BIT_SHIFT_FTM_TSF_R2T_8197F) +#define BITS_FTM_TSF_R2T_8197F (BIT_MASK_FTM_TSF_R2T_8197F << BIT_SHIFT_FTM_TSF_R2T_8197F) +#define BIT_CLEAR_FTM_TSF_R2T_8197F(x) ((x) & (~BITS_FTM_TSF_R2T_8197F)) +#define BIT_GET_FTM_TSF_R2T_8197F(x) (((x) >> BIT_SHIFT_FTM_TSF_R2T_8197F) & BIT_MASK_FTM_TSF_R2T_8197F) +#define BIT_SET_FTM_TSF_R2T_8197F(x, v) (BIT_CLEAR_FTM_TSF_R2T_8197F(x) | BIT_FTM_TSF_R2T_8197F(v)) + + +#define BIT_SHIFT_FTM_TSF_T2R_8197F 0 +#define BIT_MASK_FTM_TSF_T2R_8197F 0xffff +#define BIT_FTM_TSF_T2R_8197F(x) (((x) & BIT_MASK_FTM_TSF_T2R_8197F) << BIT_SHIFT_FTM_TSF_T2R_8197F) +#define BITS_FTM_TSF_T2R_8197F (BIT_MASK_FTM_TSF_T2R_8197F << BIT_SHIFT_FTM_TSF_T2R_8197F) +#define BIT_CLEAR_FTM_TSF_T2R_8197F(x) ((x) & (~BITS_FTM_TSF_T2R_8197F)) +#define BIT_GET_FTM_TSF_T2R_8197F(x) (((x) >> BIT_SHIFT_FTM_TSF_T2R_8197F) & BIT_MASK_FTM_TSF_T2R_8197F) +#define BIT_SET_FTM_TSF_T2R_8197F(x, v) (BIT_CLEAR_FTM_TSF_T2R_8197F(x) | BIT_FTM_TSF_T2R_8197F(v)) + + +/* 2 REG_BCN_CTRL_8197F */ +#define BIT_DIS_RX_BSSID_FIT_8197F BIT(6) +#define BIT_P0_EN_TXBCN_RPT_8197F BIT(5) +#define BIT_DIS_TSF_UDT_8197F BIT(4) +#define BIT_EN_BCN_FUNCTION_8197F BIT(3) +#define BIT_P0_EN_RXBCN_RPT_8197F BIT(2) +#define BIT_EN_P2P_CTWINDOW_8197F BIT(1) +#define BIT_EN_P2P_BCNQ_AREA_8197F BIT(0) + +/* 2 REG_BCN_CTRL_CLINT0_8197F */ +#define BIT_CLI0_DIS_RX_BSSID_FIT_8197F BIT(6) +#define BIT_CLI0_DIS_TSF_UDT_8197F BIT(4) +#define BIT_CLI0_EN_BCN_FUNCTION_8197F BIT(3) +#define BIT_CLI0_EN_RXBCN_RPT_8197F BIT(2) +#define BIT_CLI0_ENP2P_CTWINDOW_8197F BIT(1) +#define BIT_CLI0_ENP2P_BCNQ_AREA_8197F BIT(0) + +/* 2 REG_MBID_NUM_8197F */ +#define BIT_EN_PRE_DL_BEACON_8197F BIT(3) + +#define BIT_SHIFT_MBID_BCN_NUM_8197F 0 +#define BIT_MASK_MBID_BCN_NUM_8197F 0x7 +#define BIT_MBID_BCN_NUM_8197F(x) (((x) & BIT_MASK_MBID_BCN_NUM_8197F) << BIT_SHIFT_MBID_BCN_NUM_8197F) +#define BITS_MBID_BCN_NUM_8197F (BIT_MASK_MBID_BCN_NUM_8197F << BIT_SHIFT_MBID_BCN_NUM_8197F) +#define BIT_CLEAR_MBID_BCN_NUM_8197F(x) ((x) & (~BITS_MBID_BCN_NUM_8197F)) +#define BIT_GET_MBID_BCN_NUM_8197F(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8197F) & BIT_MASK_MBID_BCN_NUM_8197F) +#define BIT_SET_MBID_BCN_NUM_8197F(x, v) (BIT_CLEAR_MBID_BCN_NUM_8197F(x) | BIT_MBID_BCN_NUM_8197F(v)) + + +/* 2 REG_DUAL_TSF_RST_8197F */ +#define BIT_FREECNT_RST_8197F BIT(5) +#define BIT_TSFTR_CLI3_RST_8197F BIT(4) +#define BIT_TSFTR_CLI2_RST_8197F BIT(3) +#define BIT_TSFTR_CLI1_RST_8197F BIT(2) +#define BIT_TSFTR_CLI0_RST_8197F BIT(1) +#define BIT_TSFTR_RST_8197F BIT(0) + +/* 2 REG_MBSSID_BCN_SPACE_8197F */ + +#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F 28 +#define BIT_MASK_BCN_TIMER_SEL_FWRD_8197F 0x7 +#define BIT_BCN_TIMER_SEL_FWRD_8197F(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8197F) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) +#define BITS_BCN_TIMER_SEL_FWRD_8197F (BIT_MASK_BCN_TIMER_SEL_FWRD_8197F << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8197F)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_8197F(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) & BIT_MASK_BCN_TIMER_SEL_FWRD_8197F) +#define BIT_SET_BCN_TIMER_SEL_FWRD_8197F(x, v) (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) | BIT_BCN_TIMER_SEL_FWRD_8197F(v)) + + +#define BIT_SHIFT_BCN_SPACE_CLINT0_8197F 16 +#define BIT_MASK_BCN_SPACE_CLINT0_8197F 0xfff +#define BIT_BCN_SPACE_CLINT0_8197F(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8197F) << BIT_SHIFT_BCN_SPACE_CLINT0_8197F) +#define BITS_BCN_SPACE_CLINT0_8197F (BIT_MASK_BCN_SPACE_CLINT0_8197F << BIT_SHIFT_BCN_SPACE_CLINT0_8197F) +#define BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) ((x) & (~BITS_BCN_SPACE_CLINT0_8197F)) +#define BIT_GET_BCN_SPACE_CLINT0_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8197F) & BIT_MASK_BCN_SPACE_CLINT0_8197F) +#define BIT_SET_BCN_SPACE_CLINT0_8197F(x, v) (BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) | BIT_BCN_SPACE_CLINT0_8197F(v)) + + +#define BIT_SHIFT_BCN_SPACE0_8197F 0 +#define BIT_MASK_BCN_SPACE0_8197F 0xffff +#define BIT_BCN_SPACE0_8197F(x) (((x) & BIT_MASK_BCN_SPACE0_8197F) << BIT_SHIFT_BCN_SPACE0_8197F) +#define BITS_BCN_SPACE0_8197F (BIT_MASK_BCN_SPACE0_8197F << BIT_SHIFT_BCN_SPACE0_8197F) +#define BIT_CLEAR_BCN_SPACE0_8197F(x) ((x) & (~BITS_BCN_SPACE0_8197F)) +#define BIT_GET_BCN_SPACE0_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8197F) & BIT_MASK_BCN_SPACE0_8197F) +#define BIT_SET_BCN_SPACE0_8197F(x, v) (BIT_CLEAR_BCN_SPACE0_8197F(x) | BIT_BCN_SPACE0_8197F(v)) + + +/* 2 REG_DRVERLYINT_8197F */ + +#define BIT_SHIFT_DRVERLYITV_8197F 0 +#define BIT_MASK_DRVERLYITV_8197F 0xff +#define BIT_DRVERLYITV_8197F(x) (((x) & BIT_MASK_DRVERLYITV_8197F) << BIT_SHIFT_DRVERLYITV_8197F) +#define BITS_DRVERLYITV_8197F (BIT_MASK_DRVERLYITV_8197F << BIT_SHIFT_DRVERLYITV_8197F) +#define BIT_CLEAR_DRVERLYITV_8197F(x) ((x) & (~BITS_DRVERLYITV_8197F)) +#define BIT_GET_DRVERLYITV_8197F(x) (((x) >> BIT_SHIFT_DRVERLYITV_8197F) & BIT_MASK_DRVERLYITV_8197F) +#define BIT_SET_DRVERLYITV_8197F(x, v) (BIT_CLEAR_DRVERLYITV_8197F(x) | BIT_DRVERLYITV_8197F(v)) + + +/* 2 REG_BCNDMATIM_8197F */ + +#define BIT_SHIFT_BCNDMATIM_8197F 0 +#define BIT_MASK_BCNDMATIM_8197F 0xff +#define BIT_BCNDMATIM_8197F(x) (((x) & BIT_MASK_BCNDMATIM_8197F) << BIT_SHIFT_BCNDMATIM_8197F) +#define BITS_BCNDMATIM_8197F (BIT_MASK_BCNDMATIM_8197F << BIT_SHIFT_BCNDMATIM_8197F) +#define BIT_CLEAR_BCNDMATIM_8197F(x) ((x) & (~BITS_BCNDMATIM_8197F)) +#define BIT_GET_BCNDMATIM_8197F(x) (((x) >> BIT_SHIFT_BCNDMATIM_8197F) & BIT_MASK_BCNDMATIM_8197F) +#define BIT_SET_BCNDMATIM_8197F(x, v) (BIT_CLEAR_BCNDMATIM_8197F(x) | BIT_BCNDMATIM_8197F(v)) + + +/* 2 REG_ATIMWND_8197F */ + +#define BIT_SHIFT_ATIMWND0_8197F 0 +#define BIT_MASK_ATIMWND0_8197F 0xffff +#define BIT_ATIMWND0_8197F(x) (((x) & BIT_MASK_ATIMWND0_8197F) << BIT_SHIFT_ATIMWND0_8197F) +#define BITS_ATIMWND0_8197F (BIT_MASK_ATIMWND0_8197F << BIT_SHIFT_ATIMWND0_8197F) +#define BIT_CLEAR_ATIMWND0_8197F(x) ((x) & (~BITS_ATIMWND0_8197F)) +#define BIT_GET_ATIMWND0_8197F(x) (((x) >> BIT_SHIFT_ATIMWND0_8197F) & BIT_MASK_ATIMWND0_8197F) +#define BIT_SET_ATIMWND0_8197F(x, v) (BIT_CLEAR_ATIMWND0_8197F(x) | BIT_ATIMWND0_8197F(v)) + + +/* 2 REG_USTIME_TSF_8197F */ + +#define BIT_SHIFT_USTIME_TSF_V1_8197F 0 +#define BIT_MASK_USTIME_TSF_V1_8197F 0xff +#define BIT_USTIME_TSF_V1_8197F(x) (((x) & BIT_MASK_USTIME_TSF_V1_8197F) << BIT_SHIFT_USTIME_TSF_V1_8197F) +#define BITS_USTIME_TSF_V1_8197F (BIT_MASK_USTIME_TSF_V1_8197F << BIT_SHIFT_USTIME_TSF_V1_8197F) +#define BIT_CLEAR_USTIME_TSF_V1_8197F(x) ((x) & (~BITS_USTIME_TSF_V1_8197F)) +#define BIT_GET_USTIME_TSF_V1_8197F(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8197F) & BIT_MASK_USTIME_TSF_V1_8197F) +#define BIT_SET_USTIME_TSF_V1_8197F(x, v) (BIT_CLEAR_USTIME_TSF_V1_8197F(x) | BIT_USTIME_TSF_V1_8197F(v)) + + +/* 2 REG_BCN_MAX_ERR_8197F */ + +#define BIT_SHIFT_BCN_MAX_ERR_8197F 0 +#define BIT_MASK_BCN_MAX_ERR_8197F 0xff +#define BIT_BCN_MAX_ERR_8197F(x) (((x) & BIT_MASK_BCN_MAX_ERR_8197F) << BIT_SHIFT_BCN_MAX_ERR_8197F) +#define BITS_BCN_MAX_ERR_8197F (BIT_MASK_BCN_MAX_ERR_8197F << BIT_SHIFT_BCN_MAX_ERR_8197F) +#define BIT_CLEAR_BCN_MAX_ERR_8197F(x) ((x) & (~BITS_BCN_MAX_ERR_8197F)) +#define BIT_GET_BCN_MAX_ERR_8197F(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8197F) & BIT_MASK_BCN_MAX_ERR_8197F) +#define BIT_SET_BCN_MAX_ERR_8197F(x, v) (BIT_CLEAR_BCN_MAX_ERR_8197F(x) | BIT_BCN_MAX_ERR_8197F(v)) + + +/* 2 REG_RXTSF_OFFSET_CCK_8197F */ + +#define BIT_SHIFT_CCK_RXTSF_OFFSET_8197F 0 +#define BIT_MASK_CCK_RXTSF_OFFSET_8197F 0xff +#define BIT_CCK_RXTSF_OFFSET_8197F(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8197F) << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) +#define BITS_CCK_RXTSF_OFFSET_8197F (BIT_MASK_CCK_RXTSF_OFFSET_8197F << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) +#define BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) ((x) & (~BITS_CCK_RXTSF_OFFSET_8197F)) +#define BIT_GET_CCK_RXTSF_OFFSET_8197F(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) & BIT_MASK_CCK_RXTSF_OFFSET_8197F) +#define BIT_SET_CCK_RXTSF_OFFSET_8197F(x, v) (BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) | BIT_CCK_RXTSF_OFFSET_8197F(v)) + + +/* 2 REG_RXTSF_OFFSET_OFDM_8197F */ + +#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F 0 +#define BIT_MASK_OFDM_RXTSF_OFFSET_8197F 0xff +#define BIT_OFDM_RXTSF_OFFSET_8197F(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8197F) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) +#define BITS_OFDM_RXTSF_OFFSET_8197F (BIT_MASK_OFDM_RXTSF_OFFSET_8197F << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) ((x) & (~BITS_OFDM_RXTSF_OFFSET_8197F)) +#define BIT_GET_OFDM_RXTSF_OFFSET_8197F(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) & BIT_MASK_OFDM_RXTSF_OFFSET_8197F) +#define BIT_SET_OFDM_RXTSF_OFFSET_8197F(x, v) (BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) | BIT_OFDM_RXTSF_OFFSET_8197F(v)) + + +/* 2 REG_TSFTR_8197F */ + +#define BIT_SHIFT_TSF_TIMER_8197F 0 +#define BIT_MASK_TSF_TIMER_8197F 0xffffffffffffffffL +#define BIT_TSF_TIMER_8197F(x) (((x) & BIT_MASK_TSF_TIMER_8197F) << BIT_SHIFT_TSF_TIMER_8197F) +#define BITS_TSF_TIMER_8197F (BIT_MASK_TSF_TIMER_8197F << BIT_SHIFT_TSF_TIMER_8197F) +#define BIT_CLEAR_TSF_TIMER_8197F(x) ((x) & (~BITS_TSF_TIMER_8197F)) +#define BIT_GET_TSF_TIMER_8197F(x) (((x) >> BIT_SHIFT_TSF_TIMER_8197F) & BIT_MASK_TSF_TIMER_8197F) +#define BIT_SET_TSF_TIMER_8197F(x, v) (BIT_CLEAR_TSF_TIMER_8197F(x) | BIT_TSF_TIMER_8197F(v)) + + +/* 2 REG_FREERUN_CNT_8197F */ + +#define BIT_SHIFT_FREERUN_CNT_8197F 0 +#define BIT_MASK_FREERUN_CNT_8197F 0xffffffffffffffffL +#define BIT_FREERUN_CNT_8197F(x) (((x) & BIT_MASK_FREERUN_CNT_8197F) << BIT_SHIFT_FREERUN_CNT_8197F) +#define BITS_FREERUN_CNT_8197F (BIT_MASK_FREERUN_CNT_8197F << BIT_SHIFT_FREERUN_CNT_8197F) +#define BIT_CLEAR_FREERUN_CNT_8197F(x) ((x) & (~BITS_FREERUN_CNT_8197F)) +#define BIT_GET_FREERUN_CNT_8197F(x) (((x) >> BIT_SHIFT_FREERUN_CNT_8197F) & BIT_MASK_FREERUN_CNT_8197F) +#define BIT_SET_FREERUN_CNT_8197F(x, v) (BIT_CLEAR_FREERUN_CNT_8197F(x) | BIT_FREERUN_CNT_8197F(v)) + + +/* 2 REG_ATIMWND1_8197F */ + +#define BIT_SHIFT_ATIMWND1_V1_8197F 0 +#define BIT_MASK_ATIMWND1_V1_8197F 0xff +#define BIT_ATIMWND1_V1_8197F(x) (((x) & BIT_MASK_ATIMWND1_V1_8197F) << BIT_SHIFT_ATIMWND1_V1_8197F) +#define BITS_ATIMWND1_V1_8197F (BIT_MASK_ATIMWND1_V1_8197F << BIT_SHIFT_ATIMWND1_V1_8197F) +#define BIT_CLEAR_ATIMWND1_V1_8197F(x) ((x) & (~BITS_ATIMWND1_V1_8197F)) +#define BIT_GET_ATIMWND1_V1_8197F(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8197F) & BIT_MASK_ATIMWND1_V1_8197F) +#define BIT_SET_ATIMWND1_V1_8197F(x, v) (BIT_CLEAR_ATIMWND1_V1_8197F(x) | BIT_ATIMWND1_V1_8197F(v)) + + +/* 2 REG_TBTT_PROHIBIT_INFRA_8197F */ + +#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F 0 +#define BIT_MASK_TBTT_PROHIBIT_INFRA_8197F 0xff +#define BIT_TBTT_PROHIBIT_INFRA_8197F(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8197F) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) +#define BITS_TBTT_PROHIBIT_INFRA_8197F (BIT_MASK_TBTT_PROHIBIT_INFRA_8197F << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) +#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8197F)) +#define BIT_GET_TBTT_PROHIBIT_INFRA_8197F(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) & BIT_MASK_TBTT_PROHIBIT_INFRA_8197F) +#define BIT_SET_TBTT_PROHIBIT_INFRA_8197F(x, v) (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) | BIT_TBTT_PROHIBIT_INFRA_8197F(v)) + + +/* 2 REG_CTWND_8197F */ + +#define BIT_SHIFT_CTWND_8197F 0 +#define BIT_MASK_CTWND_8197F 0xff +#define BIT_CTWND_8197F(x) (((x) & BIT_MASK_CTWND_8197F) << BIT_SHIFT_CTWND_8197F) +#define BITS_CTWND_8197F (BIT_MASK_CTWND_8197F << BIT_SHIFT_CTWND_8197F) +#define BIT_CLEAR_CTWND_8197F(x) ((x) & (~BITS_CTWND_8197F)) +#define BIT_GET_CTWND_8197F(x) (((x) >> BIT_SHIFT_CTWND_8197F) & BIT_MASK_CTWND_8197F) +#define BIT_SET_CTWND_8197F(x, v) (BIT_CLEAR_CTWND_8197F(x) | BIT_CTWND_8197F(v)) + + +/* 2 REG_BCNIVLCUNT_8197F */ + +#define BIT_SHIFT_BCNIVLCUNT_8197F 0 +#define BIT_MASK_BCNIVLCUNT_8197F 0x7f +#define BIT_BCNIVLCUNT_8197F(x) (((x) & BIT_MASK_BCNIVLCUNT_8197F) << BIT_SHIFT_BCNIVLCUNT_8197F) +#define BITS_BCNIVLCUNT_8197F (BIT_MASK_BCNIVLCUNT_8197F << BIT_SHIFT_BCNIVLCUNT_8197F) +#define BIT_CLEAR_BCNIVLCUNT_8197F(x) ((x) & (~BITS_BCNIVLCUNT_8197F)) +#define BIT_GET_BCNIVLCUNT_8197F(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8197F) & BIT_MASK_BCNIVLCUNT_8197F) +#define BIT_SET_BCNIVLCUNT_8197F(x, v) (BIT_CLEAR_BCNIVLCUNT_8197F(x) | BIT_BCNIVLCUNT_8197F(v)) + + +/* 2 REG_BCNDROPCTRL_8197F */ +#define BIT_BEACON_DROP_EN_8197F BIT(7) + +#define BIT_SHIFT_BEACON_DROP_IVL_8197F 0 +#define BIT_MASK_BEACON_DROP_IVL_8197F 0x7f +#define BIT_BEACON_DROP_IVL_8197F(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8197F) << BIT_SHIFT_BEACON_DROP_IVL_8197F) +#define BITS_BEACON_DROP_IVL_8197F (BIT_MASK_BEACON_DROP_IVL_8197F << BIT_SHIFT_BEACON_DROP_IVL_8197F) +#define BIT_CLEAR_BEACON_DROP_IVL_8197F(x) ((x) & (~BITS_BEACON_DROP_IVL_8197F)) +#define BIT_GET_BEACON_DROP_IVL_8197F(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8197F) & BIT_MASK_BEACON_DROP_IVL_8197F) +#define BIT_SET_BEACON_DROP_IVL_8197F(x, v) (BIT_CLEAR_BEACON_DROP_IVL_8197F(x) | BIT_BEACON_DROP_IVL_8197F(v)) + + +/* 2 REG_HGQ_TIMEOUT_PERIOD_8197F */ + +#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F 0 +#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F 0xff +#define BIT_HGQ_TIMEOUT_PERIOD_8197F(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) +#define BITS_HGQ_TIMEOUT_PERIOD_8197F (BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8197F)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8197F(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F) +#define BIT_SET_HGQ_TIMEOUT_PERIOD_8197F(x, v) (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) | BIT_HGQ_TIMEOUT_PERIOD_8197F(v)) + + +/* 2 REG_TXCMD_TIMEOUT_PERIOD_8197F */ + +#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F 0 +#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F 0xff +#define BIT_TXCMD_TIMEOUT_PERIOD_8197F(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) +#define BITS_TXCMD_TIMEOUT_PERIOD_8197F (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8197F)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8197F(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8197F(x, v) (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) | BIT_TXCMD_TIMEOUT_PERIOD_8197F(v)) + + +/* 2 REG_MISC_CTRL_8197F */ +#define BIT_DIS_MARK_TSF_US_8197F BIT(7) +#define BIT_EN_TSFAUTO_SYNC_8197F BIT(6) +#define BIT_DIS_TRX_CAL_BCN_8197F BIT(5) +#define BIT_DIS_TX_CAL_TBTT_8197F BIT(4) +#define BIT_EN_FREECNT_8197F BIT(3) +#define BIT_BCN_AGGRESSION_8197F BIT(2) + +#define BIT_SHIFT_DIS_SECONDARY_CCA_8197F 0 +#define BIT_MASK_DIS_SECONDARY_CCA_8197F 0x3 +#define BIT_DIS_SECONDARY_CCA_8197F(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8197F) << BIT_SHIFT_DIS_SECONDARY_CCA_8197F) +#define BITS_DIS_SECONDARY_CCA_8197F (BIT_MASK_DIS_SECONDARY_CCA_8197F << BIT_SHIFT_DIS_SECONDARY_CCA_8197F) +#define BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) ((x) & (~BITS_DIS_SECONDARY_CCA_8197F)) +#define BIT_GET_DIS_SECONDARY_CCA_8197F(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8197F) & BIT_MASK_DIS_SECONDARY_CCA_8197F) +#define BIT_SET_DIS_SECONDARY_CCA_8197F(x, v) (BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) | BIT_DIS_SECONDARY_CCA_8197F(v)) + + +/* 2 REG_BCN_CTRL_CLINT1_8197F */ +#define BIT_CLI1_DIS_RX_BSSID_FIT_8197F BIT(6) +#define BIT_CLI1_DIS_TSF_UDT_8197F BIT(4) +#define BIT_CLI1_EN_BCN_FUNCTION_8197F BIT(3) +#define BIT_CLI1_EN_RXBCN_RPT_8197F BIT(2) +#define BIT_CLI1_ENP2P_CTWINDOW_8197F BIT(1) +#define BIT_CLI1_ENP2P_BCNQ_AREA_8197F BIT(0) + +/* 2 REG_BCN_CTRL_CLINT2_8197F */ +#define BIT_CLI2_DIS_RX_BSSID_FIT_8197F BIT(6) +#define BIT_CLI2_DIS_TSF_UDT_8197F BIT(4) +#define BIT_CLI2_EN_BCN_FUNCTION_8197F BIT(3) +#define BIT_CLI2_EN_RXBCN_RPT_8197F BIT(2) +#define BIT_CLI2_ENP2P_CTWINDOW_8197F BIT(1) +#define BIT_CLI2_ENP2P_BCNQ_AREA_8197F BIT(0) + +/* 2 REG_BCN_CTRL_CLINT3_8197F */ +#define BIT_CLI3_DIS_RX_BSSID_FIT_8197F BIT(6) +#define BIT_CLI3_DIS_TSF_UDT_8197F BIT(4) +#define BIT_CLI3_EN_BCN_FUNCTION_8197F BIT(3) +#define BIT_CLI3_EN_RXBCN_RPT_8197F BIT(2) +#define BIT_CLI3_ENP2P_CTWINDOW_8197F BIT(1) +#define BIT_CLI3_ENP2P_BCNQ_AREA_8197F BIT(0) + +/* 2 REG_EXTEND_CTRL_8197F */ +#define BIT_EN_TSFBIT32_RST_P2P2_8197F BIT(5) +#define BIT_EN_TSFBIT32_RST_P2P1_8197F BIT(4) + +#define BIT_SHIFT_PORT_SEL_8197F 0 +#define BIT_MASK_PORT_SEL_8197F 0x7 +#define BIT_PORT_SEL_8197F(x) (((x) & BIT_MASK_PORT_SEL_8197F) << BIT_SHIFT_PORT_SEL_8197F) +#define BITS_PORT_SEL_8197F (BIT_MASK_PORT_SEL_8197F << BIT_SHIFT_PORT_SEL_8197F) +#define BIT_CLEAR_PORT_SEL_8197F(x) ((x) & (~BITS_PORT_SEL_8197F)) +#define BIT_GET_PORT_SEL_8197F(x) (((x) >> BIT_SHIFT_PORT_SEL_8197F) & BIT_MASK_PORT_SEL_8197F) +#define BIT_SET_PORT_SEL_8197F(x, v) (BIT_CLEAR_PORT_SEL_8197F(x) | BIT_PORT_SEL_8197F(v)) + + +/* 2 REG_P2PPS1_SPEC_STATE_8197F */ +#define BIT_P2P1_SPEC_POWER_STATE_8197F BIT(7) +#define BIT_P2P1_SPEC_CTWINDOW_ON_8197F BIT(6) +#define BIT_P2P1_SPEC_BCN_AREA_ON_8197F BIT(5) +#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8197F BIT(4) +#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8197F BIT(3) +#define BIT_P2P1_SPEC_FORCE_DOZE1_8197F BIT(2) +#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8197F BIT(1) +#define BIT_P2P1_SPEC_FORCE_DOZE0_8197F BIT(0) + +/* 2 REG_P2PPS1_STATE_8197F */ +#define BIT_P2P1_POWER_STATE_8197F BIT(7) +#define BIT_P2P1_CTWINDOW_ON_8197F BIT(6) +#define BIT_P2P1_BEACON_AREA_ON_8197F BIT(5) +#define BIT_P2P1_CTWIN_EARLY_DISTX_8197F BIT(4) +#define BIT_P2P1_NOA1_OFF_PERIOD_8197F BIT(3) +#define BIT_P2P1_FORCE_DOZE1_8197F BIT(2) +#define BIT_P2P1_NOA0_OFF_PERIOD_8197F BIT(1) +#define BIT_P2P1_FORCE_DOZE0_8197F BIT(0) + +/* 2 REG_P2PPS2_SPEC_STATE_8197F */ +#define BIT_P2P2_SPEC_POWER_STATE_8197F BIT(7) +#define BIT_P2P2_SPEC_CTWINDOW_ON_8197F BIT(6) +#define BIT_P2P2_SPEC_BCN_AREA_ON_8197F BIT(5) +#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8197F BIT(4) +#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8197F BIT(3) +#define BIT_P2P2_SPEC_FORCE_DOZE1_8197F BIT(2) +#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8197F BIT(1) +#define BIT_P2P2_SPEC_FORCE_DOZE0_8197F BIT(0) + +/* 2 REG_P2PPS2_STATE_8197F */ +#define BIT_P2P2_POWER_STATE_8197F BIT(7) +#define BIT_P2P2_CTWINDOW_ON_8197F BIT(6) +#define BIT_P2P2_BEACON_AREA_ON_8197F BIT(5) +#define BIT_P2P2_CTWIN_EARLY_DISTX_8197F BIT(4) +#define BIT_P2P2_NOA1_OFF_PERIOD_8197F BIT(3) +#define BIT_P2P2_FORCE_DOZE1_8197F BIT(2) +#define BIT_P2P2_NOA0_OFF_PERIOD_8197F BIT(1) +#define BIT_P2P2_FORCE_DOZE0_8197F BIT(0) + +/* 2 REG_PS_TIMER0_8197F */ + +#define BIT_SHIFT_PSTIMER0_INT_8197F 5 +#define BIT_MASK_PSTIMER0_INT_8197F 0x7ffffff +#define BIT_PSTIMER0_INT_8197F(x) (((x) & BIT_MASK_PSTIMER0_INT_8197F) << BIT_SHIFT_PSTIMER0_INT_8197F) +#define BITS_PSTIMER0_INT_8197F (BIT_MASK_PSTIMER0_INT_8197F << BIT_SHIFT_PSTIMER0_INT_8197F) +#define BIT_CLEAR_PSTIMER0_INT_8197F(x) ((x) & (~BITS_PSTIMER0_INT_8197F)) +#define BIT_GET_PSTIMER0_INT_8197F(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8197F) & BIT_MASK_PSTIMER0_INT_8197F) +#define BIT_SET_PSTIMER0_INT_8197F(x, v) (BIT_CLEAR_PSTIMER0_INT_8197F(x) | BIT_PSTIMER0_INT_8197F(v)) + + +/* 2 REG_PS_TIMER1_8197F */ + +#define BIT_SHIFT_PSTIMER1_INT_8197F 5 +#define BIT_MASK_PSTIMER1_INT_8197F 0x7ffffff +#define BIT_PSTIMER1_INT_8197F(x) (((x) & BIT_MASK_PSTIMER1_INT_8197F) << BIT_SHIFT_PSTIMER1_INT_8197F) +#define BITS_PSTIMER1_INT_8197F (BIT_MASK_PSTIMER1_INT_8197F << BIT_SHIFT_PSTIMER1_INT_8197F) +#define BIT_CLEAR_PSTIMER1_INT_8197F(x) ((x) & (~BITS_PSTIMER1_INT_8197F)) +#define BIT_GET_PSTIMER1_INT_8197F(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8197F) & BIT_MASK_PSTIMER1_INT_8197F) +#define BIT_SET_PSTIMER1_INT_8197F(x, v) (BIT_CLEAR_PSTIMER1_INT_8197F(x) | BIT_PSTIMER1_INT_8197F(v)) + + +/* 2 REG_PS_TIMER2_8197F */ + +#define BIT_SHIFT_PSTIMER2_INT_8197F 5 +#define BIT_MASK_PSTIMER2_INT_8197F 0x7ffffff +#define BIT_PSTIMER2_INT_8197F(x) (((x) & BIT_MASK_PSTIMER2_INT_8197F) << BIT_SHIFT_PSTIMER2_INT_8197F) +#define BITS_PSTIMER2_INT_8197F (BIT_MASK_PSTIMER2_INT_8197F << BIT_SHIFT_PSTIMER2_INT_8197F) +#define BIT_CLEAR_PSTIMER2_INT_8197F(x) ((x) & (~BITS_PSTIMER2_INT_8197F)) +#define BIT_GET_PSTIMER2_INT_8197F(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8197F) & BIT_MASK_PSTIMER2_INT_8197F) +#define BIT_SET_PSTIMER2_INT_8197F(x, v) (BIT_CLEAR_PSTIMER2_INT_8197F(x) | BIT_PSTIMER2_INT_8197F(v)) + + +/* 2 REG_TBTT_CTN_AREA_8197F */ + +#define BIT_SHIFT_TBTT_CTN_AREA_8197F 0 +#define BIT_MASK_TBTT_CTN_AREA_8197F 0xff +#define BIT_TBTT_CTN_AREA_8197F(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8197F) << BIT_SHIFT_TBTT_CTN_AREA_8197F) +#define BITS_TBTT_CTN_AREA_8197F (BIT_MASK_TBTT_CTN_AREA_8197F << BIT_SHIFT_TBTT_CTN_AREA_8197F) +#define BIT_CLEAR_TBTT_CTN_AREA_8197F(x) ((x) & (~BITS_TBTT_CTN_AREA_8197F)) +#define BIT_GET_TBTT_CTN_AREA_8197F(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8197F) & BIT_MASK_TBTT_CTN_AREA_8197F) +#define BIT_SET_TBTT_CTN_AREA_8197F(x, v) (BIT_CLEAR_TBTT_CTN_AREA_8197F(x) | BIT_TBTT_CTN_AREA_8197F(v)) + + +/* 2 REG_FORCE_BCN_IFS_8197F */ + +#define BIT_SHIFT_FORCE_BCN_IFS_8197F 0 +#define BIT_MASK_FORCE_BCN_IFS_8197F 0xff +#define BIT_FORCE_BCN_IFS_8197F(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8197F) << BIT_SHIFT_FORCE_BCN_IFS_8197F) +#define BITS_FORCE_BCN_IFS_8197F (BIT_MASK_FORCE_BCN_IFS_8197F << BIT_SHIFT_FORCE_BCN_IFS_8197F) +#define BIT_CLEAR_FORCE_BCN_IFS_8197F(x) ((x) & (~BITS_FORCE_BCN_IFS_8197F)) +#define BIT_GET_FORCE_BCN_IFS_8197F(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8197F) & BIT_MASK_FORCE_BCN_IFS_8197F) +#define BIT_SET_FORCE_BCN_IFS_8197F(x, v) (BIT_CLEAR_FORCE_BCN_IFS_8197F(x) | BIT_FORCE_BCN_IFS_8197F(v)) + + +/* 2 REG_TXOP_MIN_8197F */ +#define BIT_NAV_BLK_HGQ_8197F BIT(15) +#define BIT_NAV_BLK_MGQ_8197F BIT(14) + +#define BIT_SHIFT_TXOP_MIN_8197F 0 +#define BIT_MASK_TXOP_MIN_8197F 0x3fff +#define BIT_TXOP_MIN_8197F(x) (((x) & BIT_MASK_TXOP_MIN_8197F) << BIT_SHIFT_TXOP_MIN_8197F) +#define BITS_TXOP_MIN_8197F (BIT_MASK_TXOP_MIN_8197F << BIT_SHIFT_TXOP_MIN_8197F) +#define BIT_CLEAR_TXOP_MIN_8197F(x) ((x) & (~BITS_TXOP_MIN_8197F)) +#define BIT_GET_TXOP_MIN_8197F(x) (((x) >> BIT_SHIFT_TXOP_MIN_8197F) & BIT_MASK_TXOP_MIN_8197F) +#define BIT_SET_TXOP_MIN_8197F(x, v) (BIT_CLEAR_TXOP_MIN_8197F(x) | BIT_TXOP_MIN_8197F(v)) + + +/* 2 REG_PRE_BKF_TIME_8197F */ + +#define BIT_SHIFT_PRE_BKF_TIME_8197F 0 +#define BIT_MASK_PRE_BKF_TIME_8197F 0xff +#define BIT_PRE_BKF_TIME_8197F(x) (((x) & BIT_MASK_PRE_BKF_TIME_8197F) << BIT_SHIFT_PRE_BKF_TIME_8197F) +#define BITS_PRE_BKF_TIME_8197F (BIT_MASK_PRE_BKF_TIME_8197F << BIT_SHIFT_PRE_BKF_TIME_8197F) +#define BIT_CLEAR_PRE_BKF_TIME_8197F(x) ((x) & (~BITS_PRE_BKF_TIME_8197F)) +#define BIT_GET_PRE_BKF_TIME_8197F(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8197F) & BIT_MASK_PRE_BKF_TIME_8197F) +#define BIT_SET_PRE_BKF_TIME_8197F(x, v) (BIT_CLEAR_PRE_BKF_TIME_8197F(x) | BIT_PRE_BKF_TIME_8197F(v)) + + +/* 2 REG_CROSS_TXOP_CTRL_8197F */ +#define BIT_DTIM_BYPASS_8197F BIT(2) +#define BIT_RTS_NAV_TXOP_8197F BIT(1) +#define BIT_NOT_CROSS_TXOP_8197F BIT(0) + +/* 2 REG_TBTT_INT_SHIFT_CLI0_8197F */ +#define BIT_TBTT_INT_SHIFT_DIR_CLI0_8197F BIT(7) + +#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F 0 +#define BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F 0x7f +#define BIT_TBTT_INT_SHIFT_CLI0_8197F(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) +#define BITS_TBTT_INT_SHIFT_CLI0_8197F (BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI0_8197F)) +#define BIT_GET_TBTT_INT_SHIFT_CLI0_8197F(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) & BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F) +#define BIT_SET_TBTT_INT_SHIFT_CLI0_8197F(x, v) (BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) | BIT_TBTT_INT_SHIFT_CLI0_8197F(v)) + + +/* 2 REG_TBTT_INT_SHIFT_CLI1_8197F */ +#define BIT_TBTT_INT_SHIFT_DIR_CLI1_8197F BIT(7) + +#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F 0 +#define BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F 0x7f +#define BIT_TBTT_INT_SHIFT_CLI1_8197F(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) +#define BITS_TBTT_INT_SHIFT_CLI1_8197F (BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI1_8197F)) +#define BIT_GET_TBTT_INT_SHIFT_CLI1_8197F(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) & BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F) +#define BIT_SET_TBTT_INT_SHIFT_CLI1_8197F(x, v) (BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) | BIT_TBTT_INT_SHIFT_CLI1_8197F(v)) + + +/* 2 REG_TBTT_INT_SHIFT_CLI2_8197F */ +#define BIT_TBTT_INT_SHIFT_DIR_CLI2_8197F BIT(7) + +#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F 0 +#define BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F 0x7f +#define BIT_TBTT_INT_SHIFT_CLI2_8197F(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) +#define BITS_TBTT_INT_SHIFT_CLI2_8197F (BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI2_8197F)) +#define BIT_GET_TBTT_INT_SHIFT_CLI2_8197F(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) & BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F) +#define BIT_SET_TBTT_INT_SHIFT_CLI2_8197F(x, v) (BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) | BIT_TBTT_INT_SHIFT_CLI2_8197F(v)) + + +/* 2 REG_TBTT_INT_SHIFT_CLI3_8197F */ +#define BIT_TBTT_INT_SHIFT_DIR_CLI3_8197F BIT(7) + +#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F 0 +#define BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F 0x7f +#define BIT_TBTT_INT_SHIFT_CLI3_8197F(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) +#define BITS_TBTT_INT_SHIFT_CLI3_8197F (BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI3_8197F)) +#define BIT_GET_TBTT_INT_SHIFT_CLI3_8197F(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) & BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F) +#define BIT_SET_TBTT_INT_SHIFT_CLI3_8197F(x, v) (BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) | BIT_TBTT_INT_SHIFT_CLI3_8197F(v)) + + +/* 2 REG_TBTT_INT_SHIFT_ENABLE_8197F */ +#define BIT_EN_TBTT_RTY_8197F BIT(1) +#define BIT_TBTT_INT_SHIFT_ENABLE_8197F BIT(0) + +/* 2 REG_ATIMWND2_8197F */ + +#define BIT_SHIFT_ATIMWND2_8197F 0 +#define BIT_MASK_ATIMWND2_8197F 0xff +#define BIT_ATIMWND2_8197F(x) (((x) & BIT_MASK_ATIMWND2_8197F) << BIT_SHIFT_ATIMWND2_8197F) +#define BITS_ATIMWND2_8197F (BIT_MASK_ATIMWND2_8197F << BIT_SHIFT_ATIMWND2_8197F) +#define BIT_CLEAR_ATIMWND2_8197F(x) ((x) & (~BITS_ATIMWND2_8197F)) +#define BIT_GET_ATIMWND2_8197F(x) (((x) >> BIT_SHIFT_ATIMWND2_8197F) & BIT_MASK_ATIMWND2_8197F) +#define BIT_SET_ATIMWND2_8197F(x, v) (BIT_CLEAR_ATIMWND2_8197F(x) | BIT_ATIMWND2_8197F(v)) + + +/* 2 REG_ATIMWND3_8197F */ + +#define BIT_SHIFT_ATIMWND3_8197F 0 +#define BIT_MASK_ATIMWND3_8197F 0xff +#define BIT_ATIMWND3_8197F(x) (((x) & BIT_MASK_ATIMWND3_8197F) << BIT_SHIFT_ATIMWND3_8197F) +#define BITS_ATIMWND3_8197F (BIT_MASK_ATIMWND3_8197F << BIT_SHIFT_ATIMWND3_8197F) +#define BIT_CLEAR_ATIMWND3_8197F(x) ((x) & (~BITS_ATIMWND3_8197F)) +#define BIT_GET_ATIMWND3_8197F(x) (((x) >> BIT_SHIFT_ATIMWND3_8197F) & BIT_MASK_ATIMWND3_8197F) +#define BIT_SET_ATIMWND3_8197F(x, v) (BIT_CLEAR_ATIMWND3_8197F(x) | BIT_ATIMWND3_8197F(v)) + + +/* 2 REG_ATIMWND4_8197F */ + +#define BIT_SHIFT_ATIMWND4_8197F 0 +#define BIT_MASK_ATIMWND4_8197F 0xff +#define BIT_ATIMWND4_8197F(x) (((x) & BIT_MASK_ATIMWND4_8197F) << BIT_SHIFT_ATIMWND4_8197F) +#define BITS_ATIMWND4_8197F (BIT_MASK_ATIMWND4_8197F << BIT_SHIFT_ATIMWND4_8197F) +#define BIT_CLEAR_ATIMWND4_8197F(x) ((x) & (~BITS_ATIMWND4_8197F)) +#define BIT_GET_ATIMWND4_8197F(x) (((x) >> BIT_SHIFT_ATIMWND4_8197F) & BIT_MASK_ATIMWND4_8197F) +#define BIT_SET_ATIMWND4_8197F(x, v) (BIT_CLEAR_ATIMWND4_8197F(x) | BIT_ATIMWND4_8197F(v)) + + +/* 2 REG_ATIMWND5_8197F */ + +#define BIT_SHIFT_ATIMWND5_8197F 0 +#define BIT_MASK_ATIMWND5_8197F 0xff +#define BIT_ATIMWND5_8197F(x) (((x) & BIT_MASK_ATIMWND5_8197F) << BIT_SHIFT_ATIMWND5_8197F) +#define BITS_ATIMWND5_8197F (BIT_MASK_ATIMWND5_8197F << BIT_SHIFT_ATIMWND5_8197F) +#define BIT_CLEAR_ATIMWND5_8197F(x) ((x) & (~BITS_ATIMWND5_8197F)) +#define BIT_GET_ATIMWND5_8197F(x) (((x) >> BIT_SHIFT_ATIMWND5_8197F) & BIT_MASK_ATIMWND5_8197F) +#define BIT_SET_ATIMWND5_8197F(x, v) (BIT_CLEAR_ATIMWND5_8197F(x) | BIT_ATIMWND5_8197F(v)) + + +/* 2 REG_ATIMWND6_8197F */ + +#define BIT_SHIFT_ATIMWND6_8197F 0 +#define BIT_MASK_ATIMWND6_8197F 0xff +#define BIT_ATIMWND6_8197F(x) (((x) & BIT_MASK_ATIMWND6_8197F) << BIT_SHIFT_ATIMWND6_8197F) +#define BITS_ATIMWND6_8197F (BIT_MASK_ATIMWND6_8197F << BIT_SHIFT_ATIMWND6_8197F) +#define BIT_CLEAR_ATIMWND6_8197F(x) ((x) & (~BITS_ATIMWND6_8197F)) +#define BIT_GET_ATIMWND6_8197F(x) (((x) >> BIT_SHIFT_ATIMWND6_8197F) & BIT_MASK_ATIMWND6_8197F) +#define BIT_SET_ATIMWND6_8197F(x, v) (BIT_CLEAR_ATIMWND6_8197F(x) | BIT_ATIMWND6_8197F(v)) + + +/* 2 REG_ATIMWND7_8197F */ + +#define BIT_SHIFT_ATIMWND7_8197F 0 +#define BIT_MASK_ATIMWND7_8197F 0xff +#define BIT_ATIMWND7_8197F(x) (((x) & BIT_MASK_ATIMWND7_8197F) << BIT_SHIFT_ATIMWND7_8197F) +#define BITS_ATIMWND7_8197F (BIT_MASK_ATIMWND7_8197F << BIT_SHIFT_ATIMWND7_8197F) +#define BIT_CLEAR_ATIMWND7_8197F(x) ((x) & (~BITS_ATIMWND7_8197F)) +#define BIT_GET_ATIMWND7_8197F(x) (((x) >> BIT_SHIFT_ATIMWND7_8197F) & BIT_MASK_ATIMWND7_8197F) +#define BIT_SET_ATIMWND7_8197F(x, v) (BIT_CLEAR_ATIMWND7_8197F(x) | BIT_ATIMWND7_8197F(v)) + + +/* 2 REG_ATIMUGT_8197F */ + +#define BIT_SHIFT_ATIM_URGENT_8197F 0 +#define BIT_MASK_ATIM_URGENT_8197F 0xff +#define BIT_ATIM_URGENT_8197F(x) (((x) & BIT_MASK_ATIM_URGENT_8197F) << BIT_SHIFT_ATIM_URGENT_8197F) +#define BITS_ATIM_URGENT_8197F (BIT_MASK_ATIM_URGENT_8197F << BIT_SHIFT_ATIM_URGENT_8197F) +#define BIT_CLEAR_ATIM_URGENT_8197F(x) ((x) & (~BITS_ATIM_URGENT_8197F)) +#define BIT_GET_ATIM_URGENT_8197F(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8197F) & BIT_MASK_ATIM_URGENT_8197F) +#define BIT_SET_ATIM_URGENT_8197F(x, v) (BIT_CLEAR_ATIM_URGENT_8197F(x) | BIT_ATIM_URGENT_8197F(v)) + + +/* 2 REG_HIQ_NO_LMT_EN_8197F */ +#define BIT_HIQ_NO_LMT_EN_VAP7_8197F BIT(7) +#define BIT_HIQ_NO_LMT_EN_VAP6_8197F BIT(6) +#define BIT_HIQ_NO_LMT_EN_VAP5_8197F BIT(5) +#define BIT_HIQ_NO_LMT_EN_VAP4_8197F BIT(4) +#define BIT_HIQ_NO_LMT_EN_VAP3_8197F BIT(3) +#define BIT_HIQ_NO_LMT_EN_VAP2_8197F BIT(2) +#define BIT_HIQ_NO_LMT_EN_VAP1_8197F BIT(1) +#define BIT_HIQ_NO_LMT_EN_ROOT_8197F BIT(0) + +/* 2 REG_DTIM_COUNTER_ROOT_8197F */ + +#define BIT_SHIFT_DTIM_COUNT_ROOT_8197F 0 +#define BIT_MASK_DTIM_COUNT_ROOT_8197F 0xff +#define BIT_DTIM_COUNT_ROOT_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8197F) << BIT_SHIFT_DTIM_COUNT_ROOT_8197F) +#define BITS_DTIM_COUNT_ROOT_8197F (BIT_MASK_DTIM_COUNT_ROOT_8197F << BIT_SHIFT_DTIM_COUNT_ROOT_8197F) +#define BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8197F)) +#define BIT_GET_DTIM_COUNT_ROOT_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8197F) & BIT_MASK_DTIM_COUNT_ROOT_8197F) +#define BIT_SET_DTIM_COUNT_ROOT_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) | BIT_DTIM_COUNT_ROOT_8197F(v)) + + +/* 2 REG_DTIM_COUNTER_VAP1_8197F */ + +#define BIT_SHIFT_DTIM_COUNT_VAP1_8197F 0 +#define BIT_MASK_DTIM_COUNT_VAP1_8197F 0xff +#define BIT_DTIM_COUNT_VAP1_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8197F) << BIT_SHIFT_DTIM_COUNT_VAP1_8197F) +#define BITS_DTIM_COUNT_VAP1_8197F (BIT_MASK_DTIM_COUNT_VAP1_8197F << BIT_SHIFT_DTIM_COUNT_VAP1_8197F) +#define BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8197F)) +#define BIT_GET_DTIM_COUNT_VAP1_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8197F) & BIT_MASK_DTIM_COUNT_VAP1_8197F) +#define BIT_SET_DTIM_COUNT_VAP1_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) | BIT_DTIM_COUNT_VAP1_8197F(v)) + + +/* 2 REG_DTIM_COUNTER_VAP2_8197F */ + +#define BIT_SHIFT_DTIM_COUNT_VAP2_8197F 0 +#define BIT_MASK_DTIM_COUNT_VAP2_8197F 0xff +#define BIT_DTIM_COUNT_VAP2_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8197F) << BIT_SHIFT_DTIM_COUNT_VAP2_8197F) +#define BITS_DTIM_COUNT_VAP2_8197F (BIT_MASK_DTIM_COUNT_VAP2_8197F << BIT_SHIFT_DTIM_COUNT_VAP2_8197F) +#define BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8197F)) +#define BIT_GET_DTIM_COUNT_VAP2_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8197F) & BIT_MASK_DTIM_COUNT_VAP2_8197F) +#define BIT_SET_DTIM_COUNT_VAP2_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) | BIT_DTIM_COUNT_VAP2_8197F(v)) + + +/* 2 REG_DTIM_COUNTER_VAP3_8197F */ + +#define BIT_SHIFT_DTIM_COUNT_VAP3_8197F 0 +#define BIT_MASK_DTIM_COUNT_VAP3_8197F 0xff +#define BIT_DTIM_COUNT_VAP3_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8197F) << BIT_SHIFT_DTIM_COUNT_VAP3_8197F) +#define BITS_DTIM_COUNT_VAP3_8197F (BIT_MASK_DTIM_COUNT_VAP3_8197F << BIT_SHIFT_DTIM_COUNT_VAP3_8197F) +#define BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8197F)) +#define BIT_GET_DTIM_COUNT_VAP3_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8197F) & BIT_MASK_DTIM_COUNT_VAP3_8197F) +#define BIT_SET_DTIM_COUNT_VAP3_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) | BIT_DTIM_COUNT_VAP3_8197F(v)) + + +/* 2 REG_DTIM_COUNTER_VAP4_8197F */ + +#define BIT_SHIFT_DTIM_COUNT_VAP4_8197F 0 +#define BIT_MASK_DTIM_COUNT_VAP4_8197F 0xff +#define BIT_DTIM_COUNT_VAP4_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8197F) << BIT_SHIFT_DTIM_COUNT_VAP4_8197F) +#define BITS_DTIM_COUNT_VAP4_8197F (BIT_MASK_DTIM_COUNT_VAP4_8197F << BIT_SHIFT_DTIM_COUNT_VAP4_8197F) +#define BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8197F)) +#define BIT_GET_DTIM_COUNT_VAP4_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8197F) & BIT_MASK_DTIM_COUNT_VAP4_8197F) +#define BIT_SET_DTIM_COUNT_VAP4_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) | BIT_DTIM_COUNT_VAP4_8197F(v)) + + +/* 2 REG_DTIM_COUNTER_VAP5_8197F */ + +#define BIT_SHIFT_DTIM_COUNT_VAP5_8197F 0 +#define BIT_MASK_DTIM_COUNT_VAP5_8197F 0xff +#define BIT_DTIM_COUNT_VAP5_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8197F) << BIT_SHIFT_DTIM_COUNT_VAP5_8197F) +#define BITS_DTIM_COUNT_VAP5_8197F (BIT_MASK_DTIM_COUNT_VAP5_8197F << BIT_SHIFT_DTIM_COUNT_VAP5_8197F) +#define BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8197F)) +#define BIT_GET_DTIM_COUNT_VAP5_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8197F) & BIT_MASK_DTIM_COUNT_VAP5_8197F) +#define BIT_SET_DTIM_COUNT_VAP5_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) | BIT_DTIM_COUNT_VAP5_8197F(v)) + + +/* 2 REG_DTIM_COUNTER_VAP6_8197F */ + +#define BIT_SHIFT_DTIM_COUNT_VAP6_8197F 0 +#define BIT_MASK_DTIM_COUNT_VAP6_8197F 0xff +#define BIT_DTIM_COUNT_VAP6_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8197F) << BIT_SHIFT_DTIM_COUNT_VAP6_8197F) +#define BITS_DTIM_COUNT_VAP6_8197F (BIT_MASK_DTIM_COUNT_VAP6_8197F << BIT_SHIFT_DTIM_COUNT_VAP6_8197F) +#define BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8197F)) +#define BIT_GET_DTIM_COUNT_VAP6_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8197F) & BIT_MASK_DTIM_COUNT_VAP6_8197F) +#define BIT_SET_DTIM_COUNT_VAP6_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) | BIT_DTIM_COUNT_VAP6_8197F(v)) + + +/* 2 REG_DTIM_COUNTER_VAP7_8197F */ + +#define BIT_SHIFT_DTIM_COUNT_VAP7_8197F 0 +#define BIT_MASK_DTIM_COUNT_VAP7_8197F 0xff +#define BIT_DTIM_COUNT_VAP7_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8197F) << BIT_SHIFT_DTIM_COUNT_VAP7_8197F) +#define BITS_DTIM_COUNT_VAP7_8197F (BIT_MASK_DTIM_COUNT_VAP7_8197F << BIT_SHIFT_DTIM_COUNT_VAP7_8197F) +#define BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8197F)) +#define BIT_GET_DTIM_COUNT_VAP7_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8197F) & BIT_MASK_DTIM_COUNT_VAP7_8197F) +#define BIT_SET_DTIM_COUNT_VAP7_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) | BIT_DTIM_COUNT_VAP7_8197F(v)) + + +/* 2 REG_DIS_ATIM_8197F */ +#define BIT_DIS_ATIM_VAP7_8197F BIT(7) +#define BIT_DIS_ATIM_VAP6_8197F BIT(6) +#define BIT_DIS_ATIM_VAP5_8197F BIT(5) +#define BIT_DIS_ATIM_VAP4_8197F BIT(4) +#define BIT_DIS_ATIM_VAP3_8197F BIT(3) +#define BIT_DIS_ATIM_VAP2_8197F BIT(2) +#define BIT_DIS_ATIM_VAP1_8197F BIT(1) +#define BIT_DIS_ATIM_ROOT_8197F BIT(0) + +/* 2 REG_EARLY_128US_8197F */ + +#define BIT_SHIFT_TSFT_SEL_TIMER1_8197F 3 +#define BIT_MASK_TSFT_SEL_TIMER1_8197F 0x7 +#define BIT_TSFT_SEL_TIMER1_8197F(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8197F) << BIT_SHIFT_TSFT_SEL_TIMER1_8197F) +#define BITS_TSFT_SEL_TIMER1_8197F (BIT_MASK_TSFT_SEL_TIMER1_8197F << BIT_SHIFT_TSFT_SEL_TIMER1_8197F) +#define BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8197F)) +#define BIT_GET_TSFT_SEL_TIMER1_8197F(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8197F) & BIT_MASK_TSFT_SEL_TIMER1_8197F) +#define BIT_SET_TSFT_SEL_TIMER1_8197F(x, v) (BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) | BIT_TSFT_SEL_TIMER1_8197F(v)) + + +#define BIT_SHIFT_EARLY_128US_8197F 0 +#define BIT_MASK_EARLY_128US_8197F 0x7 +#define BIT_EARLY_128US_8197F(x) (((x) & BIT_MASK_EARLY_128US_8197F) << BIT_SHIFT_EARLY_128US_8197F) +#define BITS_EARLY_128US_8197F (BIT_MASK_EARLY_128US_8197F << BIT_SHIFT_EARLY_128US_8197F) +#define BIT_CLEAR_EARLY_128US_8197F(x) ((x) & (~BITS_EARLY_128US_8197F)) +#define BIT_GET_EARLY_128US_8197F(x) (((x) >> BIT_SHIFT_EARLY_128US_8197F) & BIT_MASK_EARLY_128US_8197F) +#define BIT_SET_EARLY_128US_8197F(x, v) (BIT_CLEAR_EARLY_128US_8197F(x) | BIT_EARLY_128US_8197F(v)) + + +/* 2 REG_P2PPS1_CTRL_8197F */ +#define BIT_P2P1_CTW_ALLSTASLEEP_8197F BIT(7) +#define BIT_P2P1_OFF_DISTX_EN_8197F BIT(6) +#define BIT_P2P1_PWR_MGT_EN_8197F BIT(5) +#define BIT_P2P1_NOA1_EN_8197F BIT(2) +#define BIT_P2P1_NOA0_EN_8197F BIT(1) + +/* 2 REG_P2PPS2_CTRL_8197F */ +#define BIT_P2P2_CTW_ALLSTASLEEP_8197F BIT(7) +#define BIT_P2P2_OFF_DISTX_EN_8197F BIT(6) +#define BIT_P2P2_PWR_MGT_EN_8197F BIT(5) +#define BIT_P2P2_NOA1_EN_8197F BIT(2) +#define BIT_P2P2_NOA0_EN_8197F BIT(1) + +/* 2 REG_TIMER0_SRC_SEL_8197F */ + +#define BIT_SHIFT_SYNC_CLI_SEL_8197F 4 +#define BIT_MASK_SYNC_CLI_SEL_8197F 0x7 +#define BIT_SYNC_CLI_SEL_8197F(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8197F) << BIT_SHIFT_SYNC_CLI_SEL_8197F) +#define BITS_SYNC_CLI_SEL_8197F (BIT_MASK_SYNC_CLI_SEL_8197F << BIT_SHIFT_SYNC_CLI_SEL_8197F) +#define BIT_CLEAR_SYNC_CLI_SEL_8197F(x) ((x) & (~BITS_SYNC_CLI_SEL_8197F)) +#define BIT_GET_SYNC_CLI_SEL_8197F(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8197F) & BIT_MASK_SYNC_CLI_SEL_8197F) +#define BIT_SET_SYNC_CLI_SEL_8197F(x, v) (BIT_CLEAR_SYNC_CLI_SEL_8197F(x) | BIT_SYNC_CLI_SEL_8197F(v)) + + +#define BIT_SHIFT_TSFT_SEL_TIMER0_8197F 0 +#define BIT_MASK_TSFT_SEL_TIMER0_8197F 0x7 +#define BIT_TSFT_SEL_TIMER0_8197F(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8197F) << BIT_SHIFT_TSFT_SEL_TIMER0_8197F) +#define BITS_TSFT_SEL_TIMER0_8197F (BIT_MASK_TSFT_SEL_TIMER0_8197F << BIT_SHIFT_TSFT_SEL_TIMER0_8197F) +#define BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8197F)) +#define BIT_GET_TSFT_SEL_TIMER0_8197F(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8197F) & BIT_MASK_TSFT_SEL_TIMER0_8197F) +#define BIT_SET_TSFT_SEL_TIMER0_8197F(x, v) (BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) | BIT_TSFT_SEL_TIMER0_8197F(v)) + + +/* 2 REG_NOA_UNIT_SEL_8197F */ + +#define BIT_SHIFT_NOA_UNIT2_SEL_8197F 8 +#define BIT_MASK_NOA_UNIT2_SEL_8197F 0x7 +#define BIT_NOA_UNIT2_SEL_8197F(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8197F) << BIT_SHIFT_NOA_UNIT2_SEL_8197F) +#define BITS_NOA_UNIT2_SEL_8197F (BIT_MASK_NOA_UNIT2_SEL_8197F << BIT_SHIFT_NOA_UNIT2_SEL_8197F) +#define BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT2_SEL_8197F)) +#define BIT_GET_NOA_UNIT2_SEL_8197F(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8197F) & BIT_MASK_NOA_UNIT2_SEL_8197F) +#define BIT_SET_NOA_UNIT2_SEL_8197F(x, v) (BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) | BIT_NOA_UNIT2_SEL_8197F(v)) + + +#define BIT_SHIFT_NOA_UNIT1_SEL_8197F 4 +#define BIT_MASK_NOA_UNIT1_SEL_8197F 0x7 +#define BIT_NOA_UNIT1_SEL_8197F(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8197F) << BIT_SHIFT_NOA_UNIT1_SEL_8197F) +#define BITS_NOA_UNIT1_SEL_8197F (BIT_MASK_NOA_UNIT1_SEL_8197F << BIT_SHIFT_NOA_UNIT1_SEL_8197F) +#define BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT1_SEL_8197F)) +#define BIT_GET_NOA_UNIT1_SEL_8197F(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8197F) & BIT_MASK_NOA_UNIT1_SEL_8197F) +#define BIT_SET_NOA_UNIT1_SEL_8197F(x, v) (BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) | BIT_NOA_UNIT1_SEL_8197F(v)) + + +#define BIT_SHIFT_NOA_UNIT0_SEL_8197F 0 +#define BIT_MASK_NOA_UNIT0_SEL_8197F 0x7 +#define BIT_NOA_UNIT0_SEL_8197F(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8197F) << BIT_SHIFT_NOA_UNIT0_SEL_8197F) +#define BITS_NOA_UNIT0_SEL_8197F (BIT_MASK_NOA_UNIT0_SEL_8197F << BIT_SHIFT_NOA_UNIT0_SEL_8197F) +#define BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT0_SEL_8197F)) +#define BIT_GET_NOA_UNIT0_SEL_8197F(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8197F) & BIT_MASK_NOA_UNIT0_SEL_8197F) +#define BIT_SET_NOA_UNIT0_SEL_8197F(x, v) (BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) | BIT_NOA_UNIT0_SEL_8197F(v)) + + +/* 2 REG_P2POFF_DIS_TXTIME_8197F */ + +#define BIT_SHIFT_P2POFF_DIS_TXTIME_8197F 0 +#define BIT_MASK_P2POFF_DIS_TXTIME_8197F 0xff +#define BIT_P2POFF_DIS_TXTIME_8197F(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8197F) << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) +#define BITS_P2POFF_DIS_TXTIME_8197F (BIT_MASK_P2POFF_DIS_TXTIME_8197F << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) +#define BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) ((x) & (~BITS_P2POFF_DIS_TXTIME_8197F)) +#define BIT_GET_P2POFF_DIS_TXTIME_8197F(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) & BIT_MASK_P2POFF_DIS_TXTIME_8197F) +#define BIT_SET_P2POFF_DIS_TXTIME_8197F(x, v) (BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) | BIT_P2POFF_DIS_TXTIME_8197F(v)) + + +/* 2 REG_MBSSID_BCN_SPACE2_8197F */ + +#define BIT_SHIFT_BCN_SPACE_CLINT2_8197F 16 +#define BIT_MASK_BCN_SPACE_CLINT2_8197F 0xfff +#define BIT_BCN_SPACE_CLINT2_8197F(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8197F) << BIT_SHIFT_BCN_SPACE_CLINT2_8197F) +#define BITS_BCN_SPACE_CLINT2_8197F (BIT_MASK_BCN_SPACE_CLINT2_8197F << BIT_SHIFT_BCN_SPACE_CLINT2_8197F) +#define BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) ((x) & (~BITS_BCN_SPACE_CLINT2_8197F)) +#define BIT_GET_BCN_SPACE_CLINT2_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8197F) & BIT_MASK_BCN_SPACE_CLINT2_8197F) +#define BIT_SET_BCN_SPACE_CLINT2_8197F(x, v) (BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) | BIT_BCN_SPACE_CLINT2_8197F(v)) + + +#define BIT_SHIFT_BCN_SPACE_CLINT1_8197F 0 +#define BIT_MASK_BCN_SPACE_CLINT1_8197F 0xfff +#define BIT_BCN_SPACE_CLINT1_8197F(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8197F) << BIT_SHIFT_BCN_SPACE_CLINT1_8197F) +#define BITS_BCN_SPACE_CLINT1_8197F (BIT_MASK_BCN_SPACE_CLINT1_8197F << BIT_SHIFT_BCN_SPACE_CLINT1_8197F) +#define BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) ((x) & (~BITS_BCN_SPACE_CLINT1_8197F)) +#define BIT_GET_BCN_SPACE_CLINT1_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8197F) & BIT_MASK_BCN_SPACE_CLINT1_8197F) +#define BIT_SET_BCN_SPACE_CLINT1_8197F(x, v) (BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) | BIT_BCN_SPACE_CLINT1_8197F(v)) + + +/* 2 REG_MBSSID_BCN_SPACE3_8197F */ + +#define BIT_SHIFT_SUB_BCN_SPACE_V1_8197F 16 +#define BIT_MASK_SUB_BCN_SPACE_V1_8197F 0xfff +#define BIT_SUB_BCN_SPACE_V1_8197F(x) (((x) & BIT_MASK_SUB_BCN_SPACE_V1_8197F) << BIT_SHIFT_SUB_BCN_SPACE_V1_8197F) +#define BITS_SUB_BCN_SPACE_V1_8197F (BIT_MASK_SUB_BCN_SPACE_V1_8197F << BIT_SHIFT_SUB_BCN_SPACE_V1_8197F) +#define BIT_CLEAR_SUB_BCN_SPACE_V1_8197F(x) ((x) & (~BITS_SUB_BCN_SPACE_V1_8197F)) +#define BIT_GET_SUB_BCN_SPACE_V1_8197F(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V1_8197F) & BIT_MASK_SUB_BCN_SPACE_V1_8197F) +#define BIT_SET_SUB_BCN_SPACE_V1_8197F(x, v) (BIT_CLEAR_SUB_BCN_SPACE_V1_8197F(x) | BIT_SUB_BCN_SPACE_V1_8197F(v)) + + +#define BIT_SHIFT_BCN_SPACE_CLINT3_8197F 0 +#define BIT_MASK_BCN_SPACE_CLINT3_8197F 0xfff +#define BIT_BCN_SPACE_CLINT3_8197F(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8197F) << BIT_SHIFT_BCN_SPACE_CLINT3_8197F) +#define BITS_BCN_SPACE_CLINT3_8197F (BIT_MASK_BCN_SPACE_CLINT3_8197F << BIT_SHIFT_BCN_SPACE_CLINT3_8197F) +#define BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) ((x) & (~BITS_BCN_SPACE_CLINT3_8197F)) +#define BIT_GET_BCN_SPACE_CLINT3_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8197F) & BIT_MASK_BCN_SPACE_CLINT3_8197F) +#define BIT_SET_BCN_SPACE_CLINT3_8197F(x, v) (BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) | BIT_BCN_SPACE_CLINT3_8197F(v)) + + +/* 2 REG_ACMHWCTRL_8197F */ +#define BIT_BEQ_ACM_STATUS_8197F BIT(7) +#define BIT_VIQ_ACM_STATUS_8197F BIT(6) +#define BIT_VOQ_ACM_STATUS_8197F BIT(5) +#define BIT_BEQ_ACM_EN_8197F BIT(3) +#define BIT_VIQ_ACM_EN_8197F BIT(2) +#define BIT_VOQ_ACM_EN_8197F BIT(1) +#define BIT_ACMHWEN_8197F BIT(0) + +/* 2 REG_ACMRSTCTRL_8197F */ +#define BIT_BE_ACM_RESET_USED_TIME_8197F BIT(2) +#define BIT_VI_ACM_RESET_USED_TIME_8197F BIT(1) +#define BIT_VO_ACM_RESET_USED_TIME_8197F BIT(0) + +/* 2 REG_ACMAVG_8197F */ + +#define BIT_SHIFT_AVGPERIOD_8197F 0 +#define BIT_MASK_AVGPERIOD_8197F 0xffff +#define BIT_AVGPERIOD_8197F(x) (((x) & BIT_MASK_AVGPERIOD_8197F) << BIT_SHIFT_AVGPERIOD_8197F) +#define BITS_AVGPERIOD_8197F (BIT_MASK_AVGPERIOD_8197F << BIT_SHIFT_AVGPERIOD_8197F) +#define BIT_CLEAR_AVGPERIOD_8197F(x) ((x) & (~BITS_AVGPERIOD_8197F)) +#define BIT_GET_AVGPERIOD_8197F(x) (((x) >> BIT_SHIFT_AVGPERIOD_8197F) & BIT_MASK_AVGPERIOD_8197F) +#define BIT_SET_AVGPERIOD_8197F(x, v) (BIT_CLEAR_AVGPERIOD_8197F(x) | BIT_AVGPERIOD_8197F(v)) + + +/* 2 REG_VO_ADMTIME_8197F */ + +#define BIT_SHIFT_VO_ADMITTED_TIME_8197F 0 +#define BIT_MASK_VO_ADMITTED_TIME_8197F 0xffff +#define BIT_VO_ADMITTED_TIME_8197F(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8197F) << BIT_SHIFT_VO_ADMITTED_TIME_8197F) +#define BITS_VO_ADMITTED_TIME_8197F (BIT_MASK_VO_ADMITTED_TIME_8197F << BIT_SHIFT_VO_ADMITTED_TIME_8197F) +#define BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) ((x) & (~BITS_VO_ADMITTED_TIME_8197F)) +#define BIT_GET_VO_ADMITTED_TIME_8197F(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8197F) & BIT_MASK_VO_ADMITTED_TIME_8197F) +#define BIT_SET_VO_ADMITTED_TIME_8197F(x, v) (BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) | BIT_VO_ADMITTED_TIME_8197F(v)) + + +/* 2 REG_VI_ADMTIME_8197F */ + +#define BIT_SHIFT_VI_ADMITTED_TIME_8197F 0 +#define BIT_MASK_VI_ADMITTED_TIME_8197F 0xffff +#define BIT_VI_ADMITTED_TIME_8197F(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8197F) << BIT_SHIFT_VI_ADMITTED_TIME_8197F) +#define BITS_VI_ADMITTED_TIME_8197F (BIT_MASK_VI_ADMITTED_TIME_8197F << BIT_SHIFT_VI_ADMITTED_TIME_8197F) +#define BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) ((x) & (~BITS_VI_ADMITTED_TIME_8197F)) +#define BIT_GET_VI_ADMITTED_TIME_8197F(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8197F) & BIT_MASK_VI_ADMITTED_TIME_8197F) +#define BIT_SET_VI_ADMITTED_TIME_8197F(x, v) (BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) | BIT_VI_ADMITTED_TIME_8197F(v)) + + +/* 2 REG_BE_ADMTIME_8197F */ + +#define BIT_SHIFT_BE_ADMITTED_TIME_8197F 0 +#define BIT_MASK_BE_ADMITTED_TIME_8197F 0xffff +#define BIT_BE_ADMITTED_TIME_8197F(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8197F) << BIT_SHIFT_BE_ADMITTED_TIME_8197F) +#define BITS_BE_ADMITTED_TIME_8197F (BIT_MASK_BE_ADMITTED_TIME_8197F << BIT_SHIFT_BE_ADMITTED_TIME_8197F) +#define BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) ((x) & (~BITS_BE_ADMITTED_TIME_8197F)) +#define BIT_GET_BE_ADMITTED_TIME_8197F(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8197F) & BIT_MASK_BE_ADMITTED_TIME_8197F) +#define BIT_SET_BE_ADMITTED_TIME_8197F(x, v) (BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) | BIT_BE_ADMITTED_TIME_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_CHANGE_POW_BCN_AREA_8197F BIT(1) + +/* 2 REG_EDCA_RANDOM_GEN_8197F */ + +#define BIT_SHIFT_RANDOM_GEN_8197F 0 +#define BIT_MASK_RANDOM_GEN_8197F 0xffffff +#define BIT_RANDOM_GEN_8197F(x) (((x) & BIT_MASK_RANDOM_GEN_8197F) << BIT_SHIFT_RANDOM_GEN_8197F) +#define BITS_RANDOM_GEN_8197F (BIT_MASK_RANDOM_GEN_8197F << BIT_SHIFT_RANDOM_GEN_8197F) +#define BIT_CLEAR_RANDOM_GEN_8197F(x) ((x) & (~BITS_RANDOM_GEN_8197F)) +#define BIT_GET_RANDOM_GEN_8197F(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8197F) & BIT_MASK_RANDOM_GEN_8197F) +#define BIT_SET_RANDOM_GEN_8197F(x, v) (BIT_CLEAR_RANDOM_GEN_8197F(x) | BIT_RANDOM_GEN_8197F(v)) + + +/* 2 REG_TXCMD_NOA_SEL_8197F */ + +#define BIT_SHIFT_NOA_SEL_8197F 4 +#define BIT_MASK_NOA_SEL_8197F 0x7 +#define BIT_NOA_SEL_8197F(x) (((x) & BIT_MASK_NOA_SEL_8197F) << BIT_SHIFT_NOA_SEL_8197F) +#define BITS_NOA_SEL_8197F (BIT_MASK_NOA_SEL_8197F << BIT_SHIFT_NOA_SEL_8197F) +#define BIT_CLEAR_NOA_SEL_8197F(x) ((x) & (~BITS_NOA_SEL_8197F)) +#define BIT_GET_NOA_SEL_8197F(x) (((x) >> BIT_SHIFT_NOA_SEL_8197F) & BIT_MASK_NOA_SEL_8197F) +#define BIT_SET_NOA_SEL_8197F(x, v) (BIT_CLEAR_NOA_SEL_8197F(x) | BIT_NOA_SEL_8197F(v)) + + +#define BIT_SHIFT_TXCMD_SEG_SEL_8197F 0 +#define BIT_MASK_TXCMD_SEG_SEL_8197F 0xf +#define BIT_TXCMD_SEG_SEL_8197F(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8197F) << BIT_SHIFT_TXCMD_SEG_SEL_8197F) +#define BITS_TXCMD_SEG_SEL_8197F (BIT_MASK_TXCMD_SEG_SEL_8197F << BIT_SHIFT_TXCMD_SEG_SEL_8197F) +#define BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) ((x) & (~BITS_TXCMD_SEG_SEL_8197F)) +#define BIT_GET_TXCMD_SEG_SEL_8197F(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8197F) & BIT_MASK_TXCMD_SEG_SEL_8197F) +#define BIT_SET_TXCMD_SEG_SEL_8197F(x, v) (BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) | BIT_TXCMD_SEG_SEL_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_BCNERR_CNT_EN_8197F BIT(20) + +#define BIT_SHIFT_BCNERR_PORT_SEL_8197F 16 +#define BIT_MASK_BCNERR_PORT_SEL_8197F 0x7 +#define BIT_BCNERR_PORT_SEL_8197F(x) (((x) & BIT_MASK_BCNERR_PORT_SEL_8197F) << BIT_SHIFT_BCNERR_PORT_SEL_8197F) +#define BITS_BCNERR_PORT_SEL_8197F (BIT_MASK_BCNERR_PORT_SEL_8197F << BIT_SHIFT_BCNERR_PORT_SEL_8197F) +#define BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) ((x) & (~BITS_BCNERR_PORT_SEL_8197F)) +#define BIT_GET_BCNERR_PORT_SEL_8197F(x) (((x) >> BIT_SHIFT_BCNERR_PORT_SEL_8197F) & BIT_MASK_BCNERR_PORT_SEL_8197F) +#define BIT_SET_BCNERR_PORT_SEL_8197F(x, v) (BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) | BIT_BCNERR_PORT_SEL_8197F(v)) + + +#define BIT_SHIFT_TXPAUSE1_8197F 8 +#define BIT_MASK_TXPAUSE1_8197F 0xff +#define BIT_TXPAUSE1_8197F(x) (((x) & BIT_MASK_TXPAUSE1_8197F) << BIT_SHIFT_TXPAUSE1_8197F) +#define BITS_TXPAUSE1_8197F (BIT_MASK_TXPAUSE1_8197F << BIT_SHIFT_TXPAUSE1_8197F) +#define BIT_CLEAR_TXPAUSE1_8197F(x) ((x) & (~BITS_TXPAUSE1_8197F)) +#define BIT_GET_TXPAUSE1_8197F(x) (((x) >> BIT_SHIFT_TXPAUSE1_8197F) & BIT_MASK_TXPAUSE1_8197F) +#define BIT_SET_TXPAUSE1_8197F(x, v) (BIT_CLEAR_TXPAUSE1_8197F(x) | BIT_TXPAUSE1_8197F(v)) + + +#define BIT_SHIFT_BW_CFG_8197F 0 +#define BIT_MASK_BW_CFG_8197F 0x3 +#define BIT_BW_CFG_8197F(x) (((x) & BIT_MASK_BW_CFG_8197F) << BIT_SHIFT_BW_CFG_8197F) +#define BITS_BW_CFG_8197F (BIT_MASK_BW_CFG_8197F << BIT_SHIFT_BW_CFG_8197F) +#define BIT_CLEAR_BW_CFG_8197F(x) ((x) & (~BITS_BW_CFG_8197F)) +#define BIT_GET_BW_CFG_8197F(x) (((x) >> BIT_SHIFT_BW_CFG_8197F) & BIT_MASK_BW_CFG_8197F) +#define BIT_SET_BW_CFG_8197F(x, v) (BIT_CLEAR_BW_CFG_8197F(x) | BIT_BW_CFG_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_RXBCN_TIMER_8197F 16 +#define BIT_MASK_RXBCN_TIMER_8197F 0xffff +#define BIT_RXBCN_TIMER_8197F(x) (((x) & BIT_MASK_RXBCN_TIMER_8197F) << BIT_SHIFT_RXBCN_TIMER_8197F) +#define BITS_RXBCN_TIMER_8197F (BIT_MASK_RXBCN_TIMER_8197F << BIT_SHIFT_RXBCN_TIMER_8197F) +#define BIT_CLEAR_RXBCN_TIMER_8197F(x) ((x) & (~BITS_RXBCN_TIMER_8197F)) +#define BIT_GET_RXBCN_TIMER_8197F(x) (((x) >> BIT_SHIFT_RXBCN_TIMER_8197F) & BIT_MASK_RXBCN_TIMER_8197F) +#define BIT_SET_RXBCN_TIMER_8197F(x, v) (BIT_CLEAR_RXBCN_TIMER_8197F(x) | BIT_RXBCN_TIMER_8197F(v)) + + +#define BIT_SHIFT_BCN_ELY_ADJ_8197F 0 +#define BIT_MASK_BCN_ELY_ADJ_8197F 0xffff +#define BIT_BCN_ELY_ADJ_8197F(x) (((x) & BIT_MASK_BCN_ELY_ADJ_8197F) << BIT_SHIFT_BCN_ELY_ADJ_8197F) +#define BITS_BCN_ELY_ADJ_8197F (BIT_MASK_BCN_ELY_ADJ_8197F << BIT_SHIFT_BCN_ELY_ADJ_8197F) +#define BIT_CLEAR_BCN_ELY_ADJ_8197F(x) ((x) & (~BITS_BCN_ELY_ADJ_8197F)) +#define BIT_GET_BCN_ELY_ADJ_8197F(x) (((x) >> BIT_SHIFT_BCN_ELY_ADJ_8197F) & BIT_MASK_BCN_ELY_ADJ_8197F) +#define BIT_SET_BCN_ELY_ADJ_8197F(x, v) (BIT_CLEAR_BCN_ELY_ADJ_8197F(x) | BIT_BCN_ELY_ADJ_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_BCNERR_CNT_OTHERS_8197F 24 +#define BIT_MASK_BCNERR_CNT_OTHERS_8197F 0xff +#define BIT_BCNERR_CNT_OTHERS_8197F(x) (((x) & BIT_MASK_BCNERR_CNT_OTHERS_8197F) << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) +#define BITS_BCNERR_CNT_OTHERS_8197F (BIT_MASK_BCNERR_CNT_OTHERS_8197F << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) +#define BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) ((x) & (~BITS_BCNERR_CNT_OTHERS_8197F)) +#define BIT_GET_BCNERR_CNT_OTHERS_8197F(x) (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) & BIT_MASK_BCNERR_CNT_OTHERS_8197F) +#define BIT_SET_BCNERR_CNT_OTHERS_8197F(x, v) (BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) | BIT_BCNERR_CNT_OTHERS_8197F(v)) + + +#define BIT_SHIFT_BCNERR_CNT_INVALID_8197F 16 +#define BIT_MASK_BCNERR_CNT_INVALID_8197F 0xff +#define BIT_BCNERR_CNT_INVALID_8197F(x) (((x) & BIT_MASK_BCNERR_CNT_INVALID_8197F) << BIT_SHIFT_BCNERR_CNT_INVALID_8197F) +#define BITS_BCNERR_CNT_INVALID_8197F (BIT_MASK_BCNERR_CNT_INVALID_8197F << BIT_SHIFT_BCNERR_CNT_INVALID_8197F) +#define BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) ((x) & (~BITS_BCNERR_CNT_INVALID_8197F)) +#define BIT_GET_BCNERR_CNT_INVALID_8197F(x) (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8197F) & BIT_MASK_BCNERR_CNT_INVALID_8197F) +#define BIT_SET_BCNERR_CNT_INVALID_8197F(x, v) (BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) | BIT_BCNERR_CNT_INVALID_8197F(v)) + + +#define BIT_SHIFT_BCNERR_CNT_MAC_8197F 8 +#define BIT_MASK_BCNERR_CNT_MAC_8197F 0xff +#define BIT_BCNERR_CNT_MAC_8197F(x) (((x) & BIT_MASK_BCNERR_CNT_MAC_8197F) << BIT_SHIFT_BCNERR_CNT_MAC_8197F) +#define BITS_BCNERR_CNT_MAC_8197F (BIT_MASK_BCNERR_CNT_MAC_8197F << BIT_SHIFT_BCNERR_CNT_MAC_8197F) +#define BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) ((x) & (~BITS_BCNERR_CNT_MAC_8197F)) +#define BIT_GET_BCNERR_CNT_MAC_8197F(x) (((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8197F) & BIT_MASK_BCNERR_CNT_MAC_8197F) +#define BIT_SET_BCNERR_CNT_MAC_8197F(x, v) (BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) | BIT_BCNERR_CNT_MAC_8197F(v)) + + +#define BIT_SHIFT_BCNERR_CNT_CCA_8197F 0 +#define BIT_MASK_BCNERR_CNT_CCA_8197F 0xff +#define BIT_BCNERR_CNT_CCA_8197F(x) (((x) & BIT_MASK_BCNERR_CNT_CCA_8197F) << BIT_SHIFT_BCNERR_CNT_CCA_8197F) +#define BITS_BCNERR_CNT_CCA_8197F (BIT_MASK_BCNERR_CNT_CCA_8197F << BIT_SHIFT_BCNERR_CNT_CCA_8197F) +#define BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) ((x) & (~BITS_BCNERR_CNT_CCA_8197F)) +#define BIT_GET_BCNERR_CNT_CCA_8197F(x) (((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8197F) & BIT_MASK_BCNERR_CNT_CCA_8197F) +#define BIT_SET_BCNERR_CNT_CCA_8197F(x, v) (BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) | BIT_BCNERR_CNT_CCA_8197F(v)) + + +/* 2 REG_NOA_PARAM_8197F */ + +#define BIT_SHIFT_NOA_COUNT_8197F (96 & CPU_OPT_WIDTH) +#define BIT_MASK_NOA_COUNT_8197F 0xff +#define BIT_NOA_COUNT_8197F(x) (((x) & BIT_MASK_NOA_COUNT_8197F) << BIT_SHIFT_NOA_COUNT_8197F) +#define BITS_NOA_COUNT_8197F (BIT_MASK_NOA_COUNT_8197F << BIT_SHIFT_NOA_COUNT_8197F) +#define BIT_CLEAR_NOA_COUNT_8197F(x) ((x) & (~BITS_NOA_COUNT_8197F)) +#define BIT_GET_NOA_COUNT_8197F(x) (((x) >> BIT_SHIFT_NOA_COUNT_8197F) & BIT_MASK_NOA_COUNT_8197F) +#define BIT_SET_NOA_COUNT_8197F(x, v) (BIT_CLEAR_NOA_COUNT_8197F(x) | BIT_NOA_COUNT_8197F(v)) + + +#define BIT_SHIFT_NOA_START_TIME_8197F (64 & CPU_OPT_WIDTH) +#define BIT_MASK_NOA_START_TIME_8197F 0xffffffffL +#define BIT_NOA_START_TIME_8197F(x) (((x) & BIT_MASK_NOA_START_TIME_8197F) << BIT_SHIFT_NOA_START_TIME_8197F) +#define BITS_NOA_START_TIME_8197F (BIT_MASK_NOA_START_TIME_8197F << BIT_SHIFT_NOA_START_TIME_8197F) +#define BIT_CLEAR_NOA_START_TIME_8197F(x) ((x) & (~BITS_NOA_START_TIME_8197F)) +#define BIT_GET_NOA_START_TIME_8197F(x) (((x) >> BIT_SHIFT_NOA_START_TIME_8197F) & BIT_MASK_NOA_START_TIME_8197F) +#define BIT_SET_NOA_START_TIME_8197F(x, v) (BIT_CLEAR_NOA_START_TIME_8197F(x) | BIT_NOA_START_TIME_8197F(v)) + + +#define BIT_SHIFT_NOA_INTERVAL_8197F (32 & CPU_OPT_WIDTH) +#define BIT_MASK_NOA_INTERVAL_8197F 0xffffffffL +#define BIT_NOA_INTERVAL_8197F(x) (((x) & BIT_MASK_NOA_INTERVAL_8197F) << BIT_SHIFT_NOA_INTERVAL_8197F) +#define BITS_NOA_INTERVAL_8197F (BIT_MASK_NOA_INTERVAL_8197F << BIT_SHIFT_NOA_INTERVAL_8197F) +#define BIT_CLEAR_NOA_INTERVAL_8197F(x) ((x) & (~BITS_NOA_INTERVAL_8197F)) +#define BIT_GET_NOA_INTERVAL_8197F(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_8197F) & BIT_MASK_NOA_INTERVAL_8197F) +#define BIT_SET_NOA_INTERVAL_8197F(x, v) (BIT_CLEAR_NOA_INTERVAL_8197F(x) | BIT_NOA_INTERVAL_8197F(v)) + + +#define BIT_SHIFT_NOA_DURATION_8197F 0 +#define BIT_MASK_NOA_DURATION_8197F 0xffffffffL +#define BIT_NOA_DURATION_8197F(x) (((x) & BIT_MASK_NOA_DURATION_8197F) << BIT_SHIFT_NOA_DURATION_8197F) +#define BITS_NOA_DURATION_8197F (BIT_MASK_NOA_DURATION_8197F << BIT_SHIFT_NOA_DURATION_8197F) +#define BIT_CLEAR_NOA_DURATION_8197F(x) ((x) & (~BITS_NOA_DURATION_8197F)) +#define BIT_GET_NOA_DURATION_8197F(x) (((x) >> BIT_SHIFT_NOA_DURATION_8197F) & BIT_MASK_NOA_DURATION_8197F) +#define BIT_SET_NOA_DURATION_8197F(x, v) (BIT_CLEAR_NOA_DURATION_8197F(x) | BIT_NOA_DURATION_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_P2P_RST_8197F */ +#define BIT_P2P2_PWR_RST1_8197F BIT(5) +#define BIT_P2P2_PWR_RST0_8197F BIT(4) +#define BIT_P2P1_PWR_RST1_8197F BIT(3) +#define BIT_P2P1_PWR_RST0_8197F BIT(2) +#define BIT_P2P_PWR_RST1_V1_8197F BIT(1) +#define BIT_P2P_PWR_RST0_V1_8197F BIT(0) + +/* 2 REG_SCHEDULER_RST_8197F */ +#define BIT_SYNC_TSF_NOW_8197F BIT(2) +#define BIT_SYNC_CLI_8197F BIT(1) +#define BIT_SCHEDULER_RST_V1_8197F BIT(0) + +/* 2 REG_SCH_TXCMD_8197F */ + +#define BIT_SHIFT_SCH_TXCMD_8197F 0 +#define BIT_MASK_SCH_TXCMD_8197F 0xffffffffL +#define BIT_SCH_TXCMD_8197F(x) (((x) & BIT_MASK_SCH_TXCMD_8197F) << BIT_SHIFT_SCH_TXCMD_8197F) +#define BITS_SCH_TXCMD_8197F (BIT_MASK_SCH_TXCMD_8197F << BIT_SHIFT_SCH_TXCMD_8197F) +#define BIT_CLEAR_SCH_TXCMD_8197F(x) ((x) & (~BITS_SCH_TXCMD_8197F)) +#define BIT_GET_SCH_TXCMD_8197F(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8197F) & BIT_MASK_SCH_TXCMD_8197F) +#define BIT_SET_SCH_TXCMD_8197F(x, v) (BIT_CLEAR_SCH_TXCMD_8197F(x) | BIT_SCH_TXCMD_8197F(v)) + + +/* 2 REG_PAGE5_DUMMY_8197F */ + +/* 2 REG_CPUMGQ_TX_TIMER_8197F */ + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F 0xffffffffL +#define BIT_CPUMGQ_TX_TIMER_V1_8197F(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) +#define BITS_CPUMGQ_TX_TIMER_V1_8197F (BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8197F)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8197F(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F) +#define BIT_SET_CPUMGQ_TX_TIMER_V1_8197F(x, v) (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) | BIT_CPUMGQ_TX_TIMER_V1_8197F(v)) + + +/* 2 REG_PS_TIMER_A_8197F */ + +#define BIT_SHIFT_PS_TIMER_A_V1_8197F 0 +#define BIT_MASK_PS_TIMER_A_V1_8197F 0xffffffffL +#define BIT_PS_TIMER_A_V1_8197F(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8197F) << BIT_SHIFT_PS_TIMER_A_V1_8197F) +#define BITS_PS_TIMER_A_V1_8197F (BIT_MASK_PS_TIMER_A_V1_8197F << BIT_SHIFT_PS_TIMER_A_V1_8197F) +#define BIT_CLEAR_PS_TIMER_A_V1_8197F(x) ((x) & (~BITS_PS_TIMER_A_V1_8197F)) +#define BIT_GET_PS_TIMER_A_V1_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8197F) & BIT_MASK_PS_TIMER_A_V1_8197F) +#define BIT_SET_PS_TIMER_A_V1_8197F(x, v) (BIT_CLEAR_PS_TIMER_A_V1_8197F(x) | BIT_PS_TIMER_A_V1_8197F(v)) + + +/* 2 REG_PS_TIMER_B_8197F */ + +#define BIT_SHIFT_PS_TIMER_B_V1_8197F 0 +#define BIT_MASK_PS_TIMER_B_V1_8197F 0xffffffffL +#define BIT_PS_TIMER_B_V1_8197F(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8197F) << BIT_SHIFT_PS_TIMER_B_V1_8197F) +#define BITS_PS_TIMER_B_V1_8197F (BIT_MASK_PS_TIMER_B_V1_8197F << BIT_SHIFT_PS_TIMER_B_V1_8197F) +#define BIT_CLEAR_PS_TIMER_B_V1_8197F(x) ((x) & (~BITS_PS_TIMER_B_V1_8197F)) +#define BIT_GET_PS_TIMER_B_V1_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8197F) & BIT_MASK_PS_TIMER_B_V1_8197F) +#define BIT_SET_PS_TIMER_B_V1_8197F(x, v) (BIT_CLEAR_PS_TIMER_B_V1_8197F(x) | BIT_PS_TIMER_B_V1_8197F(v)) + + +/* 2 REG_PS_TIMER_C_8197F */ + +#define BIT_SHIFT_PS_TIMER_C_V1_8197F 0 +#define BIT_MASK_PS_TIMER_C_V1_8197F 0xffffffffL +#define BIT_PS_TIMER_C_V1_8197F(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8197F) << BIT_SHIFT_PS_TIMER_C_V1_8197F) +#define BITS_PS_TIMER_C_V1_8197F (BIT_MASK_PS_TIMER_C_V1_8197F << BIT_SHIFT_PS_TIMER_C_V1_8197F) +#define BIT_CLEAR_PS_TIMER_C_V1_8197F(x) ((x) & (~BITS_PS_TIMER_C_V1_8197F)) +#define BIT_GET_PS_TIMER_C_V1_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8197F) & BIT_MASK_PS_TIMER_C_V1_8197F) +#define BIT_SET_PS_TIMER_C_V1_8197F(x, v) (BIT_CLEAR_PS_TIMER_C_V1_8197F(x) | BIT_PS_TIMER_C_V1_8197F(v)) + + +/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F */ +#define BIT_CPUMGQ_TIMER_EN_8197F BIT(31) +#define BIT_CPUMGQ_TX_EN_8197F BIT(28) + +#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F 24 +#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F 0x7 +#define BIT_CPUMGQ_TIMER_TSF_SEL_8197F(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) +#define BITS_CPUMGQ_TIMER_TSF_SEL_8197F (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8197F)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8197F(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8197F(x, v) (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) | BIT_CPUMGQ_TIMER_TSF_SEL_8197F(v)) + +#define BIT_PS_TIMER_C_EN_8197F BIT(23) + +#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F 16 +#define BIT_MASK_PS_TIMER_C_TSF_SEL_8197F 0x7 +#define BIT_PS_TIMER_C_TSF_SEL_8197F(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8197F) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) +#define BITS_PS_TIMER_C_TSF_SEL_8197F (BIT_MASK_PS_TIMER_C_TSF_SEL_8197F << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) +#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8197F)) +#define BIT_GET_PS_TIMER_C_TSF_SEL_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) & BIT_MASK_PS_TIMER_C_TSF_SEL_8197F) +#define BIT_SET_PS_TIMER_C_TSF_SEL_8197F(x, v) (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) | BIT_PS_TIMER_C_TSF_SEL_8197F(v)) + +#define BIT_PS_TIMER_B_EN_8197F BIT(15) + +#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F 8 +#define BIT_MASK_PS_TIMER_B_TSF_SEL_8197F 0x7 +#define BIT_PS_TIMER_B_TSF_SEL_8197F(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8197F) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) +#define BITS_PS_TIMER_B_TSF_SEL_8197F (BIT_MASK_PS_TIMER_B_TSF_SEL_8197F << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) +#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8197F)) +#define BIT_GET_PS_TIMER_B_TSF_SEL_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) & BIT_MASK_PS_TIMER_B_TSF_SEL_8197F) +#define BIT_SET_PS_TIMER_B_TSF_SEL_8197F(x, v) (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) | BIT_PS_TIMER_B_TSF_SEL_8197F(v)) + +#define BIT_PS_TIMER_A_EN_8197F BIT(7) + +#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F 0 +#define BIT_MASK_PS_TIMER_A_TSF_SEL_8197F 0x7 +#define BIT_PS_TIMER_A_TSF_SEL_8197F(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8197F) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) +#define BITS_PS_TIMER_A_TSF_SEL_8197F (BIT_MASK_PS_TIMER_A_TSF_SEL_8197F << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) +#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8197F)) +#define BIT_GET_PS_TIMER_A_TSF_SEL_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) & BIT_MASK_PS_TIMER_A_TSF_SEL_8197F) +#define BIT_SET_PS_TIMER_A_TSF_SEL_8197F(x, v) (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) | BIT_PS_TIMER_A_TSF_SEL_8197F(v)) + + +/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8197F */ + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F 0xff +#define BIT_CPUMGQ_TX_TIMER_EARLY_8197F(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) +#define BITS_CPUMGQ_TX_TIMER_EARLY_8197F (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8197F)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8197F(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8197F(x, v) (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) | BIT_CPUMGQ_TX_TIMER_EARLY_8197F(v)) + + +/* 2 REG_PS_TIMER_A_EARLY_8197F */ + +#define BIT_SHIFT_PS_TIMER_A_EARLY_8197F 0 +#define BIT_MASK_PS_TIMER_A_EARLY_8197F 0xff +#define BIT_PS_TIMER_A_EARLY_8197F(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8197F) << BIT_SHIFT_PS_TIMER_A_EARLY_8197F) +#define BITS_PS_TIMER_A_EARLY_8197F (BIT_MASK_PS_TIMER_A_EARLY_8197F << BIT_SHIFT_PS_TIMER_A_EARLY_8197F) +#define BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) ((x) & (~BITS_PS_TIMER_A_EARLY_8197F)) +#define BIT_GET_PS_TIMER_A_EARLY_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8197F) & BIT_MASK_PS_TIMER_A_EARLY_8197F) +#define BIT_SET_PS_TIMER_A_EARLY_8197F(x, v) (BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) | BIT_PS_TIMER_A_EARLY_8197F(v)) + + +/* 2 REG_PS_TIMER_B_EARLY_8197F */ + +#define BIT_SHIFT_PS_TIMER_B_EARLY_8197F 0 +#define BIT_MASK_PS_TIMER_B_EARLY_8197F 0xff +#define BIT_PS_TIMER_B_EARLY_8197F(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8197F) << BIT_SHIFT_PS_TIMER_B_EARLY_8197F) +#define BITS_PS_TIMER_B_EARLY_8197F (BIT_MASK_PS_TIMER_B_EARLY_8197F << BIT_SHIFT_PS_TIMER_B_EARLY_8197F) +#define BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) ((x) & (~BITS_PS_TIMER_B_EARLY_8197F)) +#define BIT_GET_PS_TIMER_B_EARLY_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8197F) & BIT_MASK_PS_TIMER_B_EARLY_8197F) +#define BIT_SET_PS_TIMER_B_EARLY_8197F(x, v) (BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) | BIT_PS_TIMER_B_EARLY_8197F(v)) + + +/* 2 REG_PS_TIMER_C_EARLY_8197F */ + +#define BIT_SHIFT_PS_TIMER_C_EARLY_8197F 0 +#define BIT_MASK_PS_TIMER_C_EARLY_8197F 0xff +#define BIT_PS_TIMER_C_EARLY_8197F(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8197F) << BIT_SHIFT_PS_TIMER_C_EARLY_8197F) +#define BITS_PS_TIMER_C_EARLY_8197F (BIT_MASK_PS_TIMER_C_EARLY_8197F << BIT_SHIFT_PS_TIMER_C_EARLY_8197F) +#define BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) ((x) & (~BITS_PS_TIMER_C_EARLY_8197F)) +#define BIT_GET_PS_TIMER_C_EARLY_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8197F) & BIT_MASK_PS_TIMER_C_EARLY_8197F) +#define BIT_SET_PS_TIMER_C_EARLY_8197F(x, v) (BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) | BIT_PS_TIMER_C_EARLY_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_STOP_CPUMGQ_8197F BIT(16) + +#define BIT_SHIFT_CPUMGQ_PARAMETER_8197F 0 +#define BIT_MASK_CPUMGQ_PARAMETER_8197F 0xffff +#define BIT_CPUMGQ_PARAMETER_8197F(x) (((x) & BIT_MASK_CPUMGQ_PARAMETER_8197F) << BIT_SHIFT_CPUMGQ_PARAMETER_8197F) +#define BITS_CPUMGQ_PARAMETER_8197F (BIT_MASK_CPUMGQ_PARAMETER_8197F << BIT_SHIFT_CPUMGQ_PARAMETER_8197F) +#define BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) ((x) & (~BITS_CPUMGQ_PARAMETER_8197F)) +#define BIT_GET_CPUMGQ_PARAMETER_8197F(x) (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER_8197F) & BIT_MASK_CPUMGQ_PARAMETER_8197F) +#define BIT_SET_CPUMGQ_PARAMETER_8197F(x, v) (BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) | BIT_CPUMGQ_PARAMETER_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_BWOPMODE_8197F (BW OPERATION MODE REGISTER) */ + +/* 2 REG_WMAC_FWPKT_CR_8197F */ +#define BIT_FWEN_8197F BIT(7) +#define BIT_PHYSTS_PKT_CTRL_8197F BIT(6) +#define BIT_APPHDR_MIDSRCH_FAIL_8197F BIT(4) +#define BIT_FWPARSING_EN_8197F BIT(3) + +#define BIT_SHIFT_APPEND_MHDR_LEN_8197F 0 +#define BIT_MASK_APPEND_MHDR_LEN_8197F 0x7 +#define BIT_APPEND_MHDR_LEN_8197F(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8197F) << BIT_SHIFT_APPEND_MHDR_LEN_8197F) +#define BITS_APPEND_MHDR_LEN_8197F (BIT_MASK_APPEND_MHDR_LEN_8197F << BIT_SHIFT_APPEND_MHDR_LEN_8197F) +#define BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) ((x) & (~BITS_APPEND_MHDR_LEN_8197F)) +#define BIT_GET_APPEND_MHDR_LEN_8197F(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8197F) & BIT_MASK_APPEND_MHDR_LEN_8197F) +#define BIT_SET_APPEND_MHDR_LEN_8197F(x, v) (BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) | BIT_APPEND_MHDR_LEN_8197F(v)) + + +/* 2 REG_WMAC_CR_8197F (WMAC CR AND APSD CONTROL REGISTER) */ +#define BIT_APSDOFF_8197F BIT(6) +#define BIT_IC_MACPHY_M_8197F BIT(0) + +/* 2 REG_TCR_8197F (TRANSMISSION CONFIGURATION REGISTER) */ +#define BIT_WMAC_EN_RTS_ADDR_8197F BIT(31) +#define BIT_WMAC_DISABLE_CCK_8197F BIT(30) +#define BIT_WMAC_RAW_LEN_8197F BIT(29) +#define BIT_WMAC_NOTX_IN_RXNDP_8197F BIT(28) +#define BIT_WMAC_EN_EOF_8197F BIT(27) +#define BIT_WMAC_BF_SEL_8197F BIT(26) +#define BIT_WMAC_ANTMODE_SEL_8197F BIT(25) +#define BIT_WMAC_TCRPWRMGT_HWCTL_8197F BIT(24) +#define BIT_WMAC_SMOOTH_VAL_8197F BIT(23) +#define BIT_UNDERFLOWEN_CMPLEN_SEL_8197F BIT(21) +#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8197F BIT(20) +#define BIT_WMAC_TCR_EN_20MST_8197F BIT(19) +#define BIT_WMAC_DIS_SIGTA_8197F BIT(18) +#define BIT_WMAC_DIS_A2B0_8197F BIT(17) +#define BIT_WMAC_MSK_SIGBCRC_8197F BIT(16) +#define BIT_WMAC_TCR_ERRSTEN_3_8197F BIT(15) +#define BIT_WMAC_TCR_ERRSTEN_2_8197F BIT(14) +#define BIT_WMAC_TCR_ERRSTEN_1_8197F BIT(13) +#define BIT_WMAC_TCR_ERRSTEN_0_8197F BIT(12) +#define BIT_WMAC_TCR_TXSK_PERPKT_8197F BIT(11) +#define BIT_ICV_8197F BIT(10) +#define BIT_CFEND_FORMAT_8197F BIT(9) +#define BIT_CRC_8197F BIT(8) +#define BIT_PWRBIT_OW_EN_8197F BIT(7) +#define BIT_PWR_ST_8197F BIT(6) +#define BIT_WMAC_TCR_UPD_TIMIE_8197F BIT(5) +#define BIT_WMAC_TCR_UPD_HGQMD_8197F BIT(4) +#define BIT_VHTSIGA1_TXPS_8197F BIT(3) +#define BIT_PAD_SEL_8197F BIT(2) +#define BIT_DIS_GCLK_8197F BIT(1) + +/* 2 REG_RCR_8197F (RECEIVE CONFIGURATION REGISTER) */ +#define BIT_APP_FCS_8197F BIT(31) +#define BIT_APP_MIC_8197F BIT(30) +#define BIT_APP_ICV_8197F BIT(29) +#define BIT_APP_PHYSTS_8197F BIT(28) +#define BIT_APP_BASSN_8197F BIT(27) +#define BIT_VHT_DACK_8197F BIT(26) +#define BIT_TCPOFLD_EN_8197F BIT(25) +#define BIT_ENMBID_8197F BIT(24) +#define BIT_LSIGEN_8197F BIT(23) +#define BIT_MFBEN_8197F BIT(22) +#define BIT_DISCHKPPDLLEN_8197F BIT(21) +#define BIT_PKTCTL_DLEN_8197F BIT(20) +#define BIT_TIM_PARSER_EN_8197F BIT(18) +#define BIT_BC_MD_EN_8197F BIT(17) +#define BIT_UC_MD_EN_8197F BIT(16) +#define BIT_RXSK_PERPKT_8197F BIT(15) +#define BIT_HTC_LOC_CTRL_8197F BIT(14) +#define BIT_TA_BCN_8197F BIT(11) +#define BIT_DISDECMYPKT_8197F BIT(10) +#define BIT_AICV_8197F BIT(9) +#define BIT_ACRC32_8197F BIT(8) +#define BIT_CBSSID_BCN_8197F BIT(7) +#define BIT_CBSSID_DATA_8197F BIT(6) +#define BIT_APWRMGT_8197F BIT(5) +#define BIT_ADD3_8197F BIT(4) +#define BIT_AB_8197F BIT(3) +#define BIT_AM_8197F BIT(2) +#define BIT_APM_8197F BIT(1) +#define BIT_AAP_8197F BIT(0) + +/* 2 REG_RX_DRVINFO_SZ_8197F (RX DRIVER INFO SIZE REGISTER) */ +#define BIT_APP_PHYSTS_PER_SUBMPDU_8197F BIT(7) +#define BIT_APP_MH_SHIFT_VAL_8197F BIT(6) +#define BIT_WMAC_ENSHIFT_8197F BIT(5) + +#define BIT_SHIFT_DRVINFO_SZ_V1_8197F 0 +#define BIT_MASK_DRVINFO_SZ_V1_8197F 0xf +#define BIT_DRVINFO_SZ_V1_8197F(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8197F) << BIT_SHIFT_DRVINFO_SZ_V1_8197F) +#define BITS_DRVINFO_SZ_V1_8197F (BIT_MASK_DRVINFO_SZ_V1_8197F << BIT_SHIFT_DRVINFO_SZ_V1_8197F) +#define BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) ((x) & (~BITS_DRVINFO_SZ_V1_8197F)) +#define BIT_GET_DRVINFO_SZ_V1_8197F(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8197F) & BIT_MASK_DRVINFO_SZ_V1_8197F) +#define BIT_SET_DRVINFO_SZ_V1_8197F(x, v) (BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) | BIT_DRVINFO_SZ_V1_8197F(v)) + + +/* 2 REG_RX_DLK_TIME_8197F (RX DEADLOCK TIME REGISTER) */ + +#define BIT_SHIFT_RX_DLK_TIME_8197F 0 +#define BIT_MASK_RX_DLK_TIME_8197F 0xff +#define BIT_RX_DLK_TIME_8197F(x) (((x) & BIT_MASK_RX_DLK_TIME_8197F) << BIT_SHIFT_RX_DLK_TIME_8197F) +#define BITS_RX_DLK_TIME_8197F (BIT_MASK_RX_DLK_TIME_8197F << BIT_SHIFT_RX_DLK_TIME_8197F) +#define BIT_CLEAR_RX_DLK_TIME_8197F(x) ((x) & (~BITS_RX_DLK_TIME_8197F)) +#define BIT_GET_RX_DLK_TIME_8197F(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8197F) & BIT_MASK_RX_DLK_TIME_8197F) +#define BIT_SET_RX_DLK_TIME_8197F(x, v) (BIT_CLEAR_RX_DLK_TIME_8197F(x) | BIT_RX_DLK_TIME_8197F(v)) + + +/* 2 REG_RX_PKT_LIMIT_8197F (RX PACKET LENGTH LIMIT REGISTER) */ + +#define BIT_SHIFT_RXPKTLMT_8197F 0 +#define BIT_MASK_RXPKTLMT_8197F 0x3f +#define BIT_RXPKTLMT_8197F(x) (((x) & BIT_MASK_RXPKTLMT_8197F) << BIT_SHIFT_RXPKTLMT_8197F) +#define BITS_RXPKTLMT_8197F (BIT_MASK_RXPKTLMT_8197F << BIT_SHIFT_RXPKTLMT_8197F) +#define BIT_CLEAR_RXPKTLMT_8197F(x) ((x) & (~BITS_RXPKTLMT_8197F)) +#define BIT_GET_RXPKTLMT_8197F(x) (((x) >> BIT_SHIFT_RXPKTLMT_8197F) & BIT_MASK_RXPKTLMT_8197F) +#define BIT_SET_RXPKTLMT_8197F(x, v) (BIT_CLEAR_RXPKTLMT_8197F(x) | BIT_RXPKTLMT_8197F(v)) + + +/* 2 REG_MACID_8197F (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_8197F 0 +#define BIT_MASK_MACID_8197F 0xffffffffffffL +#define BIT_MACID_8197F(x) (((x) & BIT_MASK_MACID_8197F) << BIT_SHIFT_MACID_8197F) +#define BITS_MACID_8197F (BIT_MASK_MACID_8197F << BIT_SHIFT_MACID_8197F) +#define BIT_CLEAR_MACID_8197F(x) ((x) & (~BITS_MACID_8197F)) +#define BIT_GET_MACID_8197F(x) (((x) >> BIT_SHIFT_MACID_8197F) & BIT_MASK_MACID_8197F) +#define BIT_SET_MACID_8197F(x, v) (BIT_CLEAR_MACID_8197F(x) | BIT_MACID_8197F(v)) + + +/* 2 REG_BSSID_8197F (BSSID REGISTER) */ + +#define BIT_SHIFT_BSSID_8197F 0 +#define BIT_MASK_BSSID_8197F 0xffffffffffffL +#define BIT_BSSID_8197F(x) (((x) & BIT_MASK_BSSID_8197F) << BIT_SHIFT_BSSID_8197F) +#define BITS_BSSID_8197F (BIT_MASK_BSSID_8197F << BIT_SHIFT_BSSID_8197F) +#define BIT_CLEAR_BSSID_8197F(x) ((x) & (~BITS_BSSID_8197F)) +#define BIT_GET_BSSID_8197F(x) (((x) >> BIT_SHIFT_BSSID_8197F) & BIT_MASK_BSSID_8197F) +#define BIT_SET_BSSID_8197F(x, v) (BIT_CLEAR_BSSID_8197F(x) | BIT_BSSID_8197F(v)) + + +/* 2 REG_MAR_8197F (MULTICAST ADDRESS REGISTER) */ + +#define BIT_SHIFT_MAR_8197F 0 +#define BIT_MASK_MAR_8197F 0xffffffffffffffffL +#define BIT_MAR_8197F(x) (((x) & BIT_MASK_MAR_8197F) << BIT_SHIFT_MAR_8197F) +#define BITS_MAR_8197F (BIT_MASK_MAR_8197F << BIT_SHIFT_MAR_8197F) +#define BIT_CLEAR_MAR_8197F(x) ((x) & (~BITS_MAR_8197F)) +#define BIT_GET_MAR_8197F(x) (((x) >> BIT_SHIFT_MAR_8197F) & BIT_MASK_MAR_8197F) +#define BIT_SET_MAR_8197F(x, v) (BIT_CLEAR_MAR_8197F(x) | BIT_MAR_8197F(v)) + + +/* 2 REG_MBIDCAMCFG_1_8197F (MBSSID CAM CONFIGURATION REGISTER) */ + +#define BIT_SHIFT_MBIDCAM_RWDATA_L_8197F 0 +#define BIT_MASK_MBIDCAM_RWDATA_L_8197F 0xffffffffL +#define BIT_MBIDCAM_RWDATA_L_8197F(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8197F) << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) +#define BITS_MBIDCAM_RWDATA_L_8197F (BIT_MASK_MBIDCAM_RWDATA_L_8197F << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) +#define BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) ((x) & (~BITS_MBIDCAM_RWDATA_L_8197F)) +#define BIT_GET_MBIDCAM_RWDATA_L_8197F(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) & BIT_MASK_MBIDCAM_RWDATA_L_8197F) +#define BIT_SET_MBIDCAM_RWDATA_L_8197F(x, v) (BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) | BIT_MBIDCAM_RWDATA_L_8197F(v)) + + +/* 2 REG_MBIDCAMCFG_2_8197F (MBSSID CAM CONFIGURATION REGISTER) */ +#define BIT_MBIDCAM_POLL_8197F BIT(31) +#define BIT_MBIDCAM_WT_EN_8197F BIT(30) + +#define BIT_SHIFT_MBIDCAM_ADDR_8197F 24 +#define BIT_MASK_MBIDCAM_ADDR_8197F 0x1f +#define BIT_MBIDCAM_ADDR_8197F(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8197F) << BIT_SHIFT_MBIDCAM_ADDR_8197F) +#define BITS_MBIDCAM_ADDR_8197F (BIT_MASK_MBIDCAM_ADDR_8197F << BIT_SHIFT_MBIDCAM_ADDR_8197F) +#define BIT_CLEAR_MBIDCAM_ADDR_8197F(x) ((x) & (~BITS_MBIDCAM_ADDR_8197F)) +#define BIT_GET_MBIDCAM_ADDR_8197F(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8197F) & BIT_MASK_MBIDCAM_ADDR_8197F) +#define BIT_SET_MBIDCAM_ADDR_8197F(x, v) (BIT_CLEAR_MBIDCAM_ADDR_8197F(x) | BIT_MBIDCAM_ADDR_8197F(v)) + +#define BIT_MBIDCAM_VALID_8197F BIT(23) +#define BIT_LSIC_TXOP_EN_8197F BIT(17) +#define BIT_REPEAT_MODE_EN_8197F BIT(16) + +#define BIT_SHIFT_MBIDCAM_RWDATA_H_8197F 0 +#define BIT_MASK_MBIDCAM_RWDATA_H_8197F 0xffff +#define BIT_MBIDCAM_RWDATA_H_8197F(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8197F) << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) +#define BITS_MBIDCAM_RWDATA_H_8197F (BIT_MASK_MBIDCAM_RWDATA_H_8197F << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) +#define BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) ((x) & (~BITS_MBIDCAM_RWDATA_H_8197F)) +#define BIT_GET_MBIDCAM_RWDATA_H_8197F(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) & BIT_MASK_MBIDCAM_RWDATA_H_8197F) +#define BIT_SET_MBIDCAM_RWDATA_H_8197F(x, v) (BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) | BIT_MBIDCAM_RWDATA_H_8197F(v)) + + +/* 2 REG_ZLD_NUM_8197F */ + +#define BIT_SHIFT_ZLD_NUM_8197F 0 +#define BIT_MASK_ZLD_NUM_8197F 0xff +#define BIT_ZLD_NUM_8197F(x) (((x) & BIT_MASK_ZLD_NUM_8197F) << BIT_SHIFT_ZLD_NUM_8197F) +#define BITS_ZLD_NUM_8197F (BIT_MASK_ZLD_NUM_8197F << BIT_SHIFT_ZLD_NUM_8197F) +#define BIT_CLEAR_ZLD_NUM_8197F(x) ((x) & (~BITS_ZLD_NUM_8197F)) +#define BIT_GET_ZLD_NUM_8197F(x) (((x) >> BIT_SHIFT_ZLD_NUM_8197F) & BIT_MASK_ZLD_NUM_8197F) +#define BIT_SET_ZLD_NUM_8197F(x, v) (BIT_CLEAR_ZLD_NUM_8197F(x) | BIT_ZLD_NUM_8197F(v)) + + +/* 2 REG_UDF_THSD_8197F */ + +#define BIT_SHIFT_UDF_THSD_8197F 0 +#define BIT_MASK_UDF_THSD_8197F 0xff +#define BIT_UDF_THSD_8197F(x) (((x) & BIT_MASK_UDF_THSD_8197F) << BIT_SHIFT_UDF_THSD_8197F) +#define BITS_UDF_THSD_8197F (BIT_MASK_UDF_THSD_8197F << BIT_SHIFT_UDF_THSD_8197F) +#define BIT_CLEAR_UDF_THSD_8197F(x) ((x) & (~BITS_UDF_THSD_8197F)) +#define BIT_GET_UDF_THSD_8197F(x) (((x) >> BIT_SHIFT_UDF_THSD_8197F) & BIT_MASK_UDF_THSD_8197F) +#define BIT_SET_UDF_THSD_8197F(x, v) (BIT_CLEAR_UDF_THSD_8197F(x) | BIT_UDF_THSD_8197F(v)) + + +/* 2 REG_WMAC_TCR_TSFT_OFS_8197F */ + +#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F 0 +#define BIT_MASK_WMAC_TCR_TSFT_OFS_8197F 0xffff +#define BIT_WMAC_TCR_TSFT_OFS_8197F(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8197F) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) +#define BITS_WMAC_TCR_TSFT_OFS_8197F (BIT_MASK_WMAC_TCR_TSFT_OFS_8197F << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8197F)) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8197F(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) & BIT_MASK_WMAC_TCR_TSFT_OFS_8197F) +#define BIT_SET_WMAC_TCR_TSFT_OFS_8197F(x, v) (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) | BIT_WMAC_TCR_TSFT_OFS_8197F(v)) + + +/* 2 REG_MCU_TEST_2_V1_8197F */ + +#define BIT_SHIFT_MCU_RSVD_2_V1_8197F 0 +#define BIT_MASK_MCU_RSVD_2_V1_8197F 0xffff +#define BIT_MCU_RSVD_2_V1_8197F(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8197F) << BIT_SHIFT_MCU_RSVD_2_V1_8197F) +#define BITS_MCU_RSVD_2_V1_8197F (BIT_MASK_MCU_RSVD_2_V1_8197F << BIT_SHIFT_MCU_RSVD_2_V1_8197F) +#define BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) ((x) & (~BITS_MCU_RSVD_2_V1_8197F)) +#define BIT_GET_MCU_RSVD_2_V1_8197F(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8197F) & BIT_MASK_MCU_RSVD_2_V1_8197F) +#define BIT_SET_MCU_RSVD_2_V1_8197F(x, v) (BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) | BIT_MCU_RSVD_2_V1_8197F(v)) + + +/* 2 REG_WMAC_TXTIMEOUT_8197F */ + +#define BIT_SHIFT_WMAC_TXTIMEOUT_8197F 0 +#define BIT_MASK_WMAC_TXTIMEOUT_8197F 0xff +#define BIT_WMAC_TXTIMEOUT_8197F(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8197F) << BIT_SHIFT_WMAC_TXTIMEOUT_8197F) +#define BITS_WMAC_TXTIMEOUT_8197F (BIT_MASK_WMAC_TXTIMEOUT_8197F << BIT_SHIFT_WMAC_TXTIMEOUT_8197F) +#define BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8197F)) +#define BIT_GET_WMAC_TXTIMEOUT_8197F(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8197F) & BIT_MASK_WMAC_TXTIMEOUT_8197F) +#define BIT_SET_WMAC_TXTIMEOUT_8197F(x, v) (BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) | BIT_WMAC_TXTIMEOUT_8197F(v)) + + +/* 2 REG_STMP_THSD_8197F */ + +#define BIT_SHIFT_STMP_THSD_8197F 0 +#define BIT_MASK_STMP_THSD_8197F 0xff +#define BIT_STMP_THSD_8197F(x) (((x) & BIT_MASK_STMP_THSD_8197F) << BIT_SHIFT_STMP_THSD_8197F) +#define BITS_STMP_THSD_8197F (BIT_MASK_STMP_THSD_8197F << BIT_SHIFT_STMP_THSD_8197F) +#define BIT_CLEAR_STMP_THSD_8197F(x) ((x) & (~BITS_STMP_THSD_8197F)) +#define BIT_GET_STMP_THSD_8197F(x) (((x) >> BIT_SHIFT_STMP_THSD_8197F) & BIT_MASK_STMP_THSD_8197F) +#define BIT_SET_STMP_THSD_8197F(x, v) (BIT_CLEAR_STMP_THSD_8197F(x) | BIT_STMP_THSD_8197F(v)) + + +/* 2 REG_MAC_SPEC_SIFS_8197F (SPECIFICATION SIFS REGISTER) */ + +#define BIT_SHIFT_SPEC_SIFS_OFDM_8197F 8 +#define BIT_MASK_SPEC_SIFS_OFDM_8197F 0xff +#define BIT_SPEC_SIFS_OFDM_8197F(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8197F) << BIT_SHIFT_SPEC_SIFS_OFDM_8197F) +#define BITS_SPEC_SIFS_OFDM_8197F (BIT_MASK_SPEC_SIFS_OFDM_8197F << BIT_SHIFT_SPEC_SIFS_OFDM_8197F) +#define BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8197F)) +#define BIT_GET_SPEC_SIFS_OFDM_8197F(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8197F) & BIT_MASK_SPEC_SIFS_OFDM_8197F) +#define BIT_SET_SPEC_SIFS_OFDM_8197F(x, v) (BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) | BIT_SPEC_SIFS_OFDM_8197F(v)) + + +#define BIT_SHIFT_SPEC_SIFS_CCK_8197F 0 +#define BIT_MASK_SPEC_SIFS_CCK_8197F 0xff +#define BIT_SPEC_SIFS_CCK_8197F(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8197F) << BIT_SHIFT_SPEC_SIFS_CCK_8197F) +#define BITS_SPEC_SIFS_CCK_8197F (BIT_MASK_SPEC_SIFS_CCK_8197F << BIT_SHIFT_SPEC_SIFS_CCK_8197F) +#define BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) ((x) & (~BITS_SPEC_SIFS_CCK_8197F)) +#define BIT_GET_SPEC_SIFS_CCK_8197F(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8197F) & BIT_MASK_SPEC_SIFS_CCK_8197F) +#define BIT_SET_SPEC_SIFS_CCK_8197F(x, v) (BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) | BIT_SPEC_SIFS_CCK_8197F(v)) + + +/* 2 REG_USTIME_EDCA_8197F (US TIME TUNING FOR EDCA REGISTER) */ + +#define BIT_SHIFT_USTIME_EDCA_8197F 0 +#define BIT_MASK_USTIME_EDCA_8197F 0xff +#define BIT_USTIME_EDCA_8197F(x) (((x) & BIT_MASK_USTIME_EDCA_8197F) << BIT_SHIFT_USTIME_EDCA_8197F) +#define BITS_USTIME_EDCA_8197F (BIT_MASK_USTIME_EDCA_8197F << BIT_SHIFT_USTIME_EDCA_8197F) +#define BIT_CLEAR_USTIME_EDCA_8197F(x) ((x) & (~BITS_USTIME_EDCA_8197F)) +#define BIT_GET_USTIME_EDCA_8197F(x) (((x) >> BIT_SHIFT_USTIME_EDCA_8197F) & BIT_MASK_USTIME_EDCA_8197F) +#define BIT_SET_USTIME_EDCA_8197F(x, v) (BIT_CLEAR_USTIME_EDCA_8197F(x) | BIT_USTIME_EDCA_8197F(v)) + + +/* 2 REG_RESP_SIFS_OFDM_8197F (RESPONSE SIFS FOR OFDM REGISTER) */ + +#define BIT_SHIFT_SIFS_R2T_OFDM_8197F 8 +#define BIT_MASK_SIFS_R2T_OFDM_8197F 0xff +#define BIT_SIFS_R2T_OFDM_8197F(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8197F) << BIT_SHIFT_SIFS_R2T_OFDM_8197F) +#define BITS_SIFS_R2T_OFDM_8197F (BIT_MASK_SIFS_R2T_OFDM_8197F << BIT_SHIFT_SIFS_R2T_OFDM_8197F) +#define BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) ((x) & (~BITS_SIFS_R2T_OFDM_8197F)) +#define BIT_GET_SIFS_R2T_OFDM_8197F(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8197F) & BIT_MASK_SIFS_R2T_OFDM_8197F) +#define BIT_SET_SIFS_R2T_OFDM_8197F(x, v) (BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) | BIT_SIFS_R2T_OFDM_8197F(v)) + + +#define BIT_SHIFT_SIFS_T2T_OFDM_8197F 0 +#define BIT_MASK_SIFS_T2T_OFDM_8197F 0xff +#define BIT_SIFS_T2T_OFDM_8197F(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8197F) << BIT_SHIFT_SIFS_T2T_OFDM_8197F) +#define BITS_SIFS_T2T_OFDM_8197F (BIT_MASK_SIFS_T2T_OFDM_8197F << BIT_SHIFT_SIFS_T2T_OFDM_8197F) +#define BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) ((x) & (~BITS_SIFS_T2T_OFDM_8197F)) +#define BIT_GET_SIFS_T2T_OFDM_8197F(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8197F) & BIT_MASK_SIFS_T2T_OFDM_8197F) +#define BIT_SET_SIFS_T2T_OFDM_8197F(x, v) (BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) | BIT_SIFS_T2T_OFDM_8197F(v)) + + +/* 2 REG_RESP_SIFS_CCK_8197F (RESPONSE SIFS FOR CCK REGISTER) */ + +#define BIT_SHIFT_SIFS_R2T_CCK_8197F 8 +#define BIT_MASK_SIFS_R2T_CCK_8197F 0xff +#define BIT_SIFS_R2T_CCK_8197F(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8197F) << BIT_SHIFT_SIFS_R2T_CCK_8197F) +#define BITS_SIFS_R2T_CCK_8197F (BIT_MASK_SIFS_R2T_CCK_8197F << BIT_SHIFT_SIFS_R2T_CCK_8197F) +#define BIT_CLEAR_SIFS_R2T_CCK_8197F(x) ((x) & (~BITS_SIFS_R2T_CCK_8197F)) +#define BIT_GET_SIFS_R2T_CCK_8197F(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8197F) & BIT_MASK_SIFS_R2T_CCK_8197F) +#define BIT_SET_SIFS_R2T_CCK_8197F(x, v) (BIT_CLEAR_SIFS_R2T_CCK_8197F(x) | BIT_SIFS_R2T_CCK_8197F(v)) + + +#define BIT_SHIFT_SIFS_T2T_CCK_8197F 0 +#define BIT_MASK_SIFS_T2T_CCK_8197F 0xff +#define BIT_SIFS_T2T_CCK_8197F(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8197F) << BIT_SHIFT_SIFS_T2T_CCK_8197F) +#define BITS_SIFS_T2T_CCK_8197F (BIT_MASK_SIFS_T2T_CCK_8197F << BIT_SHIFT_SIFS_T2T_CCK_8197F) +#define BIT_CLEAR_SIFS_T2T_CCK_8197F(x) ((x) & (~BITS_SIFS_T2T_CCK_8197F)) +#define BIT_GET_SIFS_T2T_CCK_8197F(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8197F) & BIT_MASK_SIFS_T2T_CCK_8197F) +#define BIT_SET_SIFS_T2T_CCK_8197F(x, v) (BIT_CLEAR_SIFS_T2T_CCK_8197F(x) | BIT_SIFS_T2T_CCK_8197F(v)) + + +/* 2 REG_EIFS_8197F (EIFS REGISTER) */ + +#define BIT_SHIFT_EIFS_8197F 0 +#define BIT_MASK_EIFS_8197F 0xffff +#define BIT_EIFS_8197F(x) (((x) & BIT_MASK_EIFS_8197F) << BIT_SHIFT_EIFS_8197F) +#define BITS_EIFS_8197F (BIT_MASK_EIFS_8197F << BIT_SHIFT_EIFS_8197F) +#define BIT_CLEAR_EIFS_8197F(x) ((x) & (~BITS_EIFS_8197F)) +#define BIT_GET_EIFS_8197F(x) (((x) >> BIT_SHIFT_EIFS_8197F) & BIT_MASK_EIFS_8197F) +#define BIT_SET_EIFS_8197F(x, v) (BIT_CLEAR_EIFS_8197F(x) | BIT_EIFS_8197F(v)) + + +/* 2 REG_CTS2TO_8197F (CTS2 TIMEOUT REGISTER) */ + +#define BIT_SHIFT_CTS2TO_8197F 0 +#define BIT_MASK_CTS2TO_8197F 0xff +#define BIT_CTS2TO_8197F(x) (((x) & BIT_MASK_CTS2TO_8197F) << BIT_SHIFT_CTS2TO_8197F) +#define BITS_CTS2TO_8197F (BIT_MASK_CTS2TO_8197F << BIT_SHIFT_CTS2TO_8197F) +#define BIT_CLEAR_CTS2TO_8197F(x) ((x) & (~BITS_CTS2TO_8197F)) +#define BIT_GET_CTS2TO_8197F(x) (((x) >> BIT_SHIFT_CTS2TO_8197F) & BIT_MASK_CTS2TO_8197F) +#define BIT_SET_CTS2TO_8197F(x, v) (BIT_CLEAR_CTS2TO_8197F(x) | BIT_CTS2TO_8197F(v)) + + +/* 2 REG_ACKTO_8197F (ACK TIMEOUT REGISTER) */ + +#define BIT_SHIFT_ACKTO_8197F 0 +#define BIT_MASK_ACKTO_8197F 0xff +#define BIT_ACKTO_8197F(x) (((x) & BIT_MASK_ACKTO_8197F) << BIT_SHIFT_ACKTO_8197F) +#define BITS_ACKTO_8197F (BIT_MASK_ACKTO_8197F << BIT_SHIFT_ACKTO_8197F) +#define BIT_CLEAR_ACKTO_8197F(x) ((x) & (~BITS_ACKTO_8197F)) +#define BIT_GET_ACKTO_8197F(x) (((x) >> BIT_SHIFT_ACKTO_8197F) & BIT_MASK_ACKTO_8197F) +#define BIT_SET_ACKTO_8197F(x, v) (BIT_CLEAR_ACKTO_8197F(x) | BIT_ACKTO_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NAV_CTRL_8197F (NAV CONTROL REGISTER) */ + +#define BIT_SHIFT_NAV_UPPER_8197F 16 +#define BIT_MASK_NAV_UPPER_8197F 0xff +#define BIT_NAV_UPPER_8197F(x) (((x) & BIT_MASK_NAV_UPPER_8197F) << BIT_SHIFT_NAV_UPPER_8197F) +#define BITS_NAV_UPPER_8197F (BIT_MASK_NAV_UPPER_8197F << BIT_SHIFT_NAV_UPPER_8197F) +#define BIT_CLEAR_NAV_UPPER_8197F(x) ((x) & (~BITS_NAV_UPPER_8197F)) +#define BIT_GET_NAV_UPPER_8197F(x) (((x) >> BIT_SHIFT_NAV_UPPER_8197F) & BIT_MASK_NAV_UPPER_8197F) +#define BIT_SET_NAV_UPPER_8197F(x, v) (BIT_CLEAR_NAV_UPPER_8197F(x) | BIT_NAV_UPPER_8197F(v)) + + +#define BIT_SHIFT_RXMYRTS_NAV_8197F 8 +#define BIT_MASK_RXMYRTS_NAV_8197F 0xf +#define BIT_RXMYRTS_NAV_8197F(x) (((x) & BIT_MASK_RXMYRTS_NAV_8197F) << BIT_SHIFT_RXMYRTS_NAV_8197F) +#define BITS_RXMYRTS_NAV_8197F (BIT_MASK_RXMYRTS_NAV_8197F << BIT_SHIFT_RXMYRTS_NAV_8197F) +#define BIT_CLEAR_RXMYRTS_NAV_8197F(x) ((x) & (~BITS_RXMYRTS_NAV_8197F)) +#define BIT_GET_RXMYRTS_NAV_8197F(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8197F) & BIT_MASK_RXMYRTS_NAV_8197F) +#define BIT_SET_RXMYRTS_NAV_8197F(x, v) (BIT_CLEAR_RXMYRTS_NAV_8197F(x) | BIT_RXMYRTS_NAV_8197F(v)) + + +#define BIT_SHIFT_RTSRST_8197F 0 +#define BIT_MASK_RTSRST_8197F 0xff +#define BIT_RTSRST_8197F(x) (((x) & BIT_MASK_RTSRST_8197F) << BIT_SHIFT_RTSRST_8197F) +#define BITS_RTSRST_8197F (BIT_MASK_RTSRST_8197F << BIT_SHIFT_RTSRST_8197F) +#define BIT_CLEAR_RTSRST_8197F(x) ((x) & (~BITS_RTSRST_8197F)) +#define BIT_GET_RTSRST_8197F(x) (((x) >> BIT_SHIFT_RTSRST_8197F) & BIT_MASK_RTSRST_8197F) +#define BIT_SET_RTSRST_8197F(x, v) (BIT_CLEAR_RTSRST_8197F(x) | BIT_RTSRST_8197F(v)) + + +/* 2 REG_BACAMCMD_8197F (BLOCK ACK CAM COMMAND REGISTER) */ +#define BIT_BACAM_POLL_8197F BIT(31) +#define BIT_BACAM_RST_8197F BIT(17) +#define BIT_BACAM_RW_8197F BIT(16) + +#define BIT_SHIFT_TXSBM_8197F 14 +#define BIT_MASK_TXSBM_8197F 0x3 +#define BIT_TXSBM_8197F(x) (((x) & BIT_MASK_TXSBM_8197F) << BIT_SHIFT_TXSBM_8197F) +#define BITS_TXSBM_8197F (BIT_MASK_TXSBM_8197F << BIT_SHIFT_TXSBM_8197F) +#define BIT_CLEAR_TXSBM_8197F(x) ((x) & (~BITS_TXSBM_8197F)) +#define BIT_GET_TXSBM_8197F(x) (((x) >> BIT_SHIFT_TXSBM_8197F) & BIT_MASK_TXSBM_8197F) +#define BIT_SET_TXSBM_8197F(x, v) (BIT_CLEAR_TXSBM_8197F(x) | BIT_TXSBM_8197F(v)) + + +#define BIT_SHIFT_BACAM_ADDR_8197F 0 +#define BIT_MASK_BACAM_ADDR_8197F 0x3f +#define BIT_BACAM_ADDR_8197F(x) (((x) & BIT_MASK_BACAM_ADDR_8197F) << BIT_SHIFT_BACAM_ADDR_8197F) +#define BITS_BACAM_ADDR_8197F (BIT_MASK_BACAM_ADDR_8197F << BIT_SHIFT_BACAM_ADDR_8197F) +#define BIT_CLEAR_BACAM_ADDR_8197F(x) ((x) & (~BITS_BACAM_ADDR_8197F)) +#define BIT_GET_BACAM_ADDR_8197F(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8197F) & BIT_MASK_BACAM_ADDR_8197F) +#define BIT_SET_BACAM_ADDR_8197F(x, v) (BIT_CLEAR_BACAM_ADDR_8197F(x) | BIT_BACAM_ADDR_8197F(v)) + + +/* 2 REG_BACAMCONTENT_8197F (BLOCK ACK CAM CONTENT REGISTER) */ + +#define BIT_SHIFT_BA_CONTENT_H_8197F (32 & CPU_OPT_WIDTH) +#define BIT_MASK_BA_CONTENT_H_8197F 0xffffffffL +#define BIT_BA_CONTENT_H_8197F(x) (((x) & BIT_MASK_BA_CONTENT_H_8197F) << BIT_SHIFT_BA_CONTENT_H_8197F) +#define BITS_BA_CONTENT_H_8197F (BIT_MASK_BA_CONTENT_H_8197F << BIT_SHIFT_BA_CONTENT_H_8197F) +#define BIT_CLEAR_BA_CONTENT_H_8197F(x) ((x) & (~BITS_BA_CONTENT_H_8197F)) +#define BIT_GET_BA_CONTENT_H_8197F(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8197F) & BIT_MASK_BA_CONTENT_H_8197F) +#define BIT_SET_BA_CONTENT_H_8197F(x, v) (BIT_CLEAR_BA_CONTENT_H_8197F(x) | BIT_BA_CONTENT_H_8197F(v)) + + +#define BIT_SHIFT_BA_CONTENT_L_8197F 0 +#define BIT_MASK_BA_CONTENT_L_8197F 0xffffffffL +#define BIT_BA_CONTENT_L_8197F(x) (((x) & BIT_MASK_BA_CONTENT_L_8197F) << BIT_SHIFT_BA_CONTENT_L_8197F) +#define BITS_BA_CONTENT_L_8197F (BIT_MASK_BA_CONTENT_L_8197F << BIT_SHIFT_BA_CONTENT_L_8197F) +#define BIT_CLEAR_BA_CONTENT_L_8197F(x) ((x) & (~BITS_BA_CONTENT_L_8197F)) +#define BIT_GET_BA_CONTENT_L_8197F(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8197F) & BIT_MASK_BA_CONTENT_L_8197F) +#define BIT_SET_BA_CONTENT_L_8197F(x, v) (BIT_CLEAR_BA_CONTENT_L_8197F(x) | BIT_BA_CONTENT_L_8197F(v)) + + +/* 2 REG_WMAC_BITMAP_CTL_8197F */ +#define BIT_BITMAP_VO_8197F BIT(7) +#define BIT_BITMAP_VI_8197F BIT(6) +#define BIT_BITMAP_BE_8197F BIT(5) +#define BIT_BITMAP_BK_8197F BIT(4) + +#define BIT_SHIFT_BITMAP_CONDITION_8197F 2 +#define BIT_MASK_BITMAP_CONDITION_8197F 0x3 +#define BIT_BITMAP_CONDITION_8197F(x) (((x) & BIT_MASK_BITMAP_CONDITION_8197F) << BIT_SHIFT_BITMAP_CONDITION_8197F) +#define BITS_BITMAP_CONDITION_8197F (BIT_MASK_BITMAP_CONDITION_8197F << BIT_SHIFT_BITMAP_CONDITION_8197F) +#define BIT_CLEAR_BITMAP_CONDITION_8197F(x) ((x) & (~BITS_BITMAP_CONDITION_8197F)) +#define BIT_GET_BITMAP_CONDITION_8197F(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8197F) & BIT_MASK_BITMAP_CONDITION_8197F) +#define BIT_SET_BITMAP_CONDITION_8197F(x, v) (BIT_CLEAR_BITMAP_CONDITION_8197F(x) | BIT_BITMAP_CONDITION_8197F(v)) + +#define BIT_BITMAP_SSNBK_COUNTER_CLR_8197F BIT(1) +#define BIT_BITMAP_FORCE_8197F BIT(0) + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_RXPKT_TYPE_8197F 2 +#define BIT_MASK_RXPKT_TYPE_8197F 0x3f +#define BIT_RXPKT_TYPE_8197F(x) (((x) & BIT_MASK_RXPKT_TYPE_8197F) << BIT_SHIFT_RXPKT_TYPE_8197F) +#define BITS_RXPKT_TYPE_8197F (BIT_MASK_RXPKT_TYPE_8197F << BIT_SHIFT_RXPKT_TYPE_8197F) +#define BIT_CLEAR_RXPKT_TYPE_8197F(x) ((x) & (~BITS_RXPKT_TYPE_8197F)) +#define BIT_GET_RXPKT_TYPE_8197F(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8197F) & BIT_MASK_RXPKT_TYPE_8197F) +#define BIT_SET_RXPKT_TYPE_8197F(x, v) (BIT_CLEAR_RXPKT_TYPE_8197F(x) | BIT_RXPKT_TYPE_8197F(v)) + +#define BIT_TXACT_IND_8197F BIT(1) +#define BIT_RXACT_IND_8197F BIT(0) + +/* 2 REG_WMAC_BACAM_RPMEN_8197F */ + +#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F 2 +#define BIT_MASK_BITMAP_SSNBK_COUNTER_8197F 0x3f +#define BIT_BITMAP_SSNBK_COUNTER_8197F(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8197F) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) +#define BITS_BITMAP_SSNBK_COUNTER_8197F (BIT_MASK_BITMAP_SSNBK_COUNTER_8197F << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8197F)) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8197F(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) & BIT_MASK_BITMAP_SSNBK_COUNTER_8197F) +#define BIT_SET_BITMAP_SSNBK_COUNTER_8197F(x, v) (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) | BIT_BITMAP_SSNBK_COUNTER_8197F(v)) + +#define BIT_BITMAP_EN_8197F BIT(1) +#define BIT_WMAC_BACAM_RPMEN_8197F BIT(0) + +/* 2 REG_LBDLY_8197F (LOOPBACK DELAY REGISTER) */ + +#define BIT_SHIFT_LBDLY_8197F 0 +#define BIT_MASK_LBDLY_8197F 0x1f +#define BIT_LBDLY_8197F(x) (((x) & BIT_MASK_LBDLY_8197F) << BIT_SHIFT_LBDLY_8197F) +#define BITS_LBDLY_8197F (BIT_MASK_LBDLY_8197F << BIT_SHIFT_LBDLY_8197F) +#define BIT_CLEAR_LBDLY_8197F(x) ((x) & (~BITS_LBDLY_8197F)) +#define BIT_GET_LBDLY_8197F(x) (((x) >> BIT_SHIFT_LBDLY_8197F) & BIT_MASK_LBDLY_8197F) +#define BIT_SET_LBDLY_8197F(x, v) (BIT_CLEAR_LBDLY_8197F(x) | BIT_LBDLY_8197F(v)) + + +/* 2 REG_RXERR_RPT_8197F (RX ERROR REPORT REGISTER) */ + +#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F 28 +#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F 0xf +#define BIT_RXERR_RPT_SEL_V1_3_0_8197F(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) +#define BITS_RXERR_RPT_SEL_V1_3_0_8197F (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8197F)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8197F(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8197F(x, v) (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) | BIT_RXERR_RPT_SEL_V1_3_0_8197F(v)) + +#define BIT_RXERR_RPT_RST_8197F BIT(27) +#define BIT_RXERR_RPT_SEL_V1_4_8197F BIT(26) + +#define BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F 24 +#define BIT_MASK_UD_SELECT_BSSID_2_1_8197F 0x3 +#define BIT_UD_SELECT_BSSID_2_1_8197F(x) (((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8197F) << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) +#define BITS_UD_SELECT_BSSID_2_1_8197F (BIT_MASK_UD_SELECT_BSSID_2_1_8197F << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) +#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) ((x) & (~BITS_UD_SELECT_BSSID_2_1_8197F)) +#define BIT_GET_UD_SELECT_BSSID_2_1_8197F(x) (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) & BIT_MASK_UD_SELECT_BSSID_2_1_8197F) +#define BIT_SET_UD_SELECT_BSSID_2_1_8197F(x, v) (BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) | BIT_UD_SELECT_BSSID_2_1_8197F(v)) + +#define BIT_W1S_8197F BIT(23) +#define BIT_UD_SELECT_BSSID_0_8197F BIT(22) + +#define BIT_SHIFT_UD_SUB_TYPE_8197F 18 +#define BIT_MASK_UD_SUB_TYPE_8197F 0xf +#define BIT_UD_SUB_TYPE_8197F(x) (((x) & BIT_MASK_UD_SUB_TYPE_8197F) << BIT_SHIFT_UD_SUB_TYPE_8197F) +#define BITS_UD_SUB_TYPE_8197F (BIT_MASK_UD_SUB_TYPE_8197F << BIT_SHIFT_UD_SUB_TYPE_8197F) +#define BIT_CLEAR_UD_SUB_TYPE_8197F(x) ((x) & (~BITS_UD_SUB_TYPE_8197F)) +#define BIT_GET_UD_SUB_TYPE_8197F(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8197F) & BIT_MASK_UD_SUB_TYPE_8197F) +#define BIT_SET_UD_SUB_TYPE_8197F(x, v) (BIT_CLEAR_UD_SUB_TYPE_8197F(x) | BIT_UD_SUB_TYPE_8197F(v)) + + +#define BIT_SHIFT_UD_TYPE_8197F 16 +#define BIT_MASK_UD_TYPE_8197F 0x3 +#define BIT_UD_TYPE_8197F(x) (((x) & BIT_MASK_UD_TYPE_8197F) << BIT_SHIFT_UD_TYPE_8197F) +#define BITS_UD_TYPE_8197F (BIT_MASK_UD_TYPE_8197F << BIT_SHIFT_UD_TYPE_8197F) +#define BIT_CLEAR_UD_TYPE_8197F(x) ((x) & (~BITS_UD_TYPE_8197F)) +#define BIT_GET_UD_TYPE_8197F(x) (((x) >> BIT_SHIFT_UD_TYPE_8197F) & BIT_MASK_UD_TYPE_8197F) +#define BIT_SET_UD_TYPE_8197F(x, v) (BIT_CLEAR_UD_TYPE_8197F(x) | BIT_UD_TYPE_8197F(v)) + + +#define BIT_SHIFT_RPT_COUNTER_8197F 0 +#define BIT_MASK_RPT_COUNTER_8197F 0xffff +#define BIT_RPT_COUNTER_8197F(x) (((x) & BIT_MASK_RPT_COUNTER_8197F) << BIT_SHIFT_RPT_COUNTER_8197F) +#define BITS_RPT_COUNTER_8197F (BIT_MASK_RPT_COUNTER_8197F << BIT_SHIFT_RPT_COUNTER_8197F) +#define BIT_CLEAR_RPT_COUNTER_8197F(x) ((x) & (~BITS_RPT_COUNTER_8197F)) +#define BIT_GET_RPT_COUNTER_8197F(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8197F) & BIT_MASK_RPT_COUNTER_8197F) +#define BIT_SET_RPT_COUNTER_8197F(x, v) (BIT_CLEAR_RPT_COUNTER_8197F(x) | BIT_RPT_COUNTER_8197F(v)) + + +/* 2 REG_WMAC_TRXPTCL_CTL_8197F (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ + +#define BIT_SHIFT_ACKBA_TYPSEL_8197F (60 & CPU_OPT_WIDTH) +#define BIT_MASK_ACKBA_TYPSEL_8197F 0xf +#define BIT_ACKBA_TYPSEL_8197F(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8197F) << BIT_SHIFT_ACKBA_TYPSEL_8197F) +#define BITS_ACKBA_TYPSEL_8197F (BIT_MASK_ACKBA_TYPSEL_8197F << BIT_SHIFT_ACKBA_TYPSEL_8197F) +#define BIT_CLEAR_ACKBA_TYPSEL_8197F(x) ((x) & (~BITS_ACKBA_TYPSEL_8197F)) +#define BIT_GET_ACKBA_TYPSEL_8197F(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8197F) & BIT_MASK_ACKBA_TYPSEL_8197F) +#define BIT_SET_ACKBA_TYPSEL_8197F(x, v) (BIT_CLEAR_ACKBA_TYPSEL_8197F(x) | BIT_ACKBA_TYPSEL_8197F(v)) + + +#define BIT_SHIFT_ACKBA_ACKPCHK_8197F (56 & CPU_OPT_WIDTH) +#define BIT_MASK_ACKBA_ACKPCHK_8197F 0xf +#define BIT_ACKBA_ACKPCHK_8197F(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8197F) << BIT_SHIFT_ACKBA_ACKPCHK_8197F) +#define BITS_ACKBA_ACKPCHK_8197F (BIT_MASK_ACKBA_ACKPCHK_8197F << BIT_SHIFT_ACKBA_ACKPCHK_8197F) +#define BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) ((x) & (~BITS_ACKBA_ACKPCHK_8197F)) +#define BIT_GET_ACKBA_ACKPCHK_8197F(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8197F) & BIT_MASK_ACKBA_ACKPCHK_8197F) +#define BIT_SET_ACKBA_ACKPCHK_8197F(x, v) (BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) | BIT_ACKBA_ACKPCHK_8197F(v)) + + +#define BIT_SHIFT_ACKBAR_TYPESEL_8197F (48 & CPU_OPT_WIDTH) +#define BIT_MASK_ACKBAR_TYPESEL_8197F 0xff +#define BIT_ACKBAR_TYPESEL_8197F(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8197F) << BIT_SHIFT_ACKBAR_TYPESEL_8197F) +#define BITS_ACKBAR_TYPESEL_8197F (BIT_MASK_ACKBAR_TYPESEL_8197F << BIT_SHIFT_ACKBAR_TYPESEL_8197F) +#define BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) ((x) & (~BITS_ACKBAR_TYPESEL_8197F)) +#define BIT_GET_ACKBAR_TYPESEL_8197F(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8197F) & BIT_MASK_ACKBAR_TYPESEL_8197F) +#define BIT_SET_ACKBAR_TYPESEL_8197F(x, v) (BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) | BIT_ACKBAR_TYPESEL_8197F(v)) + + +#define BIT_SHIFT_ACKBAR_ACKPCHK_8197F (44 & CPU_OPT_WIDTH) +#define BIT_MASK_ACKBAR_ACKPCHK_8197F 0xf +#define BIT_ACKBAR_ACKPCHK_8197F(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8197F) << BIT_SHIFT_ACKBAR_ACKPCHK_8197F) +#define BITS_ACKBAR_ACKPCHK_8197F (BIT_MASK_ACKBAR_ACKPCHK_8197F << BIT_SHIFT_ACKBAR_ACKPCHK_8197F) +#define BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8197F)) +#define BIT_GET_ACKBAR_ACKPCHK_8197F(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8197F) & BIT_MASK_ACKBAR_ACKPCHK_8197F) +#define BIT_SET_ACKBAR_ACKPCHK_8197F(x, v) (BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) | BIT_ACKBAR_ACKPCHK_8197F(v)) + +#define BIT_RXBA_IGNOREA2_8197F BIT(42) +#define BIT_EN_SAVE_ALL_TXOPADDR_8197F BIT(41) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8197F BIT(40) +#define BIT_DIS_TXBA_AMPDUFCSERR_8197F BIT(39) +#define BIT_DIS_TXBA_RXBARINFULL_8197F BIT(38) +#define BIT_DIS_TXCFE_INFULL_8197F BIT(37) +#define BIT_DIS_TXCTS_INFULL_8197F BIT(36) +#define BIT_EN_TXACKBA_IN_TX_RDG_8197F BIT(35) +#define BIT_EN_TXACKBA_IN_TXOP_8197F BIT(34) +#define BIT_EN_TXCTS_IN_RXNAV_8197F BIT(33) +#define BIT_EN_TXCTS_INTXOP_8197F BIT(32) +#define BIT_BLK_EDCA_BBSLP_8197F BIT(31) +#define BIT_BLK_EDCA_BBSBY_8197F BIT(30) +#define BIT_ACKTO_BLOCK_SCH_EN_8197F BIT(27) +#define BIT_EIFS_BLOCK_SCH_EN_8197F BIT(26) +#define BIT_PLCPCHK_RST_EIFS_8197F BIT(25) +#define BIT_CCA_RST_EIFS_8197F BIT(24) +#define BIT_DIS_UPD_MYRXPKTNAV_8197F BIT(23) +#define BIT_EARLY_TXBA_8197F BIT(22) + +#define BIT_SHIFT_RESP_CHNBUSY_8197F 20 +#define BIT_MASK_RESP_CHNBUSY_8197F 0x3 +#define BIT_RESP_CHNBUSY_8197F(x) (((x) & BIT_MASK_RESP_CHNBUSY_8197F) << BIT_SHIFT_RESP_CHNBUSY_8197F) +#define BITS_RESP_CHNBUSY_8197F (BIT_MASK_RESP_CHNBUSY_8197F << BIT_SHIFT_RESP_CHNBUSY_8197F) +#define BIT_CLEAR_RESP_CHNBUSY_8197F(x) ((x) & (~BITS_RESP_CHNBUSY_8197F)) +#define BIT_GET_RESP_CHNBUSY_8197F(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8197F) & BIT_MASK_RESP_CHNBUSY_8197F) +#define BIT_SET_RESP_CHNBUSY_8197F(x, v) (BIT_CLEAR_RESP_CHNBUSY_8197F(x) | BIT_RESP_CHNBUSY_8197F(v)) + +#define BIT_RESP_DCTS_EN_8197F BIT(19) +#define BIT_RESP_DCFE_EN_8197F BIT(18) +#define BIT_RESP_SPLCPEN_8197F BIT(17) +#define BIT_RESP_SGIEN_8197F BIT(16) +#define BIT_RESP_LDPC_EN_8197F BIT(15) +#define BIT_DIS_RESP_ACKINCCA_8197F BIT(14) +#define BIT_DIS_RESP_CTSINCCA_8197F BIT(13) + +#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F 10 +#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F 0x7 +#define BIT_R_WMAC_SECOND_CCA_TIMER_8197F(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) +#define BITS_R_WMAC_SECOND_CCA_TIMER_8197F (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8197F)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8197F(x, v) (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) | BIT_R_WMAC_SECOND_CCA_TIMER_8197F(v)) + + +#define BIT_SHIFT_RFMOD_8197F 7 +#define BIT_MASK_RFMOD_8197F 0x3 +#define BIT_RFMOD_8197F(x) (((x) & BIT_MASK_RFMOD_8197F) << BIT_SHIFT_RFMOD_8197F) +#define BITS_RFMOD_8197F (BIT_MASK_RFMOD_8197F << BIT_SHIFT_RFMOD_8197F) +#define BIT_CLEAR_RFMOD_8197F(x) ((x) & (~BITS_RFMOD_8197F)) +#define BIT_GET_RFMOD_8197F(x) (((x) >> BIT_SHIFT_RFMOD_8197F) & BIT_MASK_RFMOD_8197F) +#define BIT_SET_RFMOD_8197F(x, v) (BIT_CLEAR_RFMOD_8197F(x) | BIT_RFMOD_8197F(v)) + + +#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F 5 +#define BIT_MASK_RESP_CTS_DYNBW_SEL_8197F 0x3 +#define BIT_RESP_CTS_DYNBW_SEL_8197F(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8197F) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) +#define BITS_RESP_CTS_DYNBW_SEL_8197F (BIT_MASK_RESP_CTS_DYNBW_SEL_8197F << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8197F)) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8197F(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) & BIT_MASK_RESP_CTS_DYNBW_SEL_8197F) +#define BIT_SET_RESP_CTS_DYNBW_SEL_8197F(x, v) (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) | BIT_RESP_CTS_DYNBW_SEL_8197F(v)) + +#define BIT_DLY_TX_WAIT_RXANTSEL_8197F BIT(4) +#define BIT_TXRESP_BY_RXANTSEL_8197F BIT(3) + +#define BIT_SHIFT_ORIG_DCTS_CHK_8197F 0 +#define BIT_MASK_ORIG_DCTS_CHK_8197F 0x3 +#define BIT_ORIG_DCTS_CHK_8197F(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8197F) << BIT_SHIFT_ORIG_DCTS_CHK_8197F) +#define BITS_ORIG_DCTS_CHK_8197F (BIT_MASK_ORIG_DCTS_CHK_8197F << BIT_SHIFT_ORIG_DCTS_CHK_8197F) +#define BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) ((x) & (~BITS_ORIG_DCTS_CHK_8197F)) +#define BIT_GET_ORIG_DCTS_CHK_8197F(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8197F) & BIT_MASK_ORIG_DCTS_CHK_8197F) +#define BIT_SET_ORIG_DCTS_CHK_8197F(x, v) (BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) | BIT_ORIG_DCTS_CHK_8197F(v)) + + +/* 2 REG_CAMCMD_8197F (CAM COMMAND REGISTER) */ +#define BIT_SECCAM_POLLING_8197F BIT(31) +#define BIT_SECCAM_CLR_8197F BIT(30) +#define BIT_MFBCAM_CLR_8197F BIT(29) +#define BIT_SECCAM_WE_8197F BIT(16) + +#define BIT_SHIFT_SECCAM_ADDR_V2_8197F 0 +#define BIT_MASK_SECCAM_ADDR_V2_8197F 0x3ff +#define BIT_SECCAM_ADDR_V2_8197F(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8197F) << BIT_SHIFT_SECCAM_ADDR_V2_8197F) +#define BITS_SECCAM_ADDR_V2_8197F (BIT_MASK_SECCAM_ADDR_V2_8197F << BIT_SHIFT_SECCAM_ADDR_V2_8197F) +#define BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) ((x) & (~BITS_SECCAM_ADDR_V2_8197F)) +#define BIT_GET_SECCAM_ADDR_V2_8197F(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8197F) & BIT_MASK_SECCAM_ADDR_V2_8197F) +#define BIT_SET_SECCAM_ADDR_V2_8197F(x, v) (BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) | BIT_SECCAM_ADDR_V2_8197F(v)) + + +/* 2 REG_CAMWRITE_8197F (CAM WRITE REGISTER) */ + +#define BIT_SHIFT_CAMW_DATA_8197F 0 +#define BIT_MASK_CAMW_DATA_8197F 0xffffffffL +#define BIT_CAMW_DATA_8197F(x) (((x) & BIT_MASK_CAMW_DATA_8197F) << BIT_SHIFT_CAMW_DATA_8197F) +#define BITS_CAMW_DATA_8197F (BIT_MASK_CAMW_DATA_8197F << BIT_SHIFT_CAMW_DATA_8197F) +#define BIT_CLEAR_CAMW_DATA_8197F(x) ((x) & (~BITS_CAMW_DATA_8197F)) +#define BIT_GET_CAMW_DATA_8197F(x) (((x) >> BIT_SHIFT_CAMW_DATA_8197F) & BIT_MASK_CAMW_DATA_8197F) +#define BIT_SET_CAMW_DATA_8197F(x, v) (BIT_CLEAR_CAMW_DATA_8197F(x) | BIT_CAMW_DATA_8197F(v)) + + +/* 2 REG_CAMREAD_8197F (CAM READ REGISTER) */ + +#define BIT_SHIFT_CAMR_DATA_8197F 0 +#define BIT_MASK_CAMR_DATA_8197F 0xffffffffL +#define BIT_CAMR_DATA_8197F(x) (((x) & BIT_MASK_CAMR_DATA_8197F) << BIT_SHIFT_CAMR_DATA_8197F) +#define BITS_CAMR_DATA_8197F (BIT_MASK_CAMR_DATA_8197F << BIT_SHIFT_CAMR_DATA_8197F) +#define BIT_CLEAR_CAMR_DATA_8197F(x) ((x) & (~BITS_CAMR_DATA_8197F)) +#define BIT_GET_CAMR_DATA_8197F(x) (((x) >> BIT_SHIFT_CAMR_DATA_8197F) & BIT_MASK_CAMR_DATA_8197F) +#define BIT_SET_CAMR_DATA_8197F(x, v) (BIT_CLEAR_CAMR_DATA_8197F(x) | BIT_CAMR_DATA_8197F(v)) + + +/* 2 REG_CAMDBG_8197F (CAM DEBUG REGISTER) */ +#define BIT_SECCAM_INFO_8197F BIT(31) +#define BIT_SEC_KEYFOUND_8197F BIT(15) + +#define BIT_SHIFT_CAMDBG_SEC_TYPE_8197F 12 +#define BIT_MASK_CAMDBG_SEC_TYPE_8197F 0x7 +#define BIT_CAMDBG_SEC_TYPE_8197F(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8197F) << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) +#define BITS_CAMDBG_SEC_TYPE_8197F (BIT_MASK_CAMDBG_SEC_TYPE_8197F << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) +#define BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8197F)) +#define BIT_GET_CAMDBG_SEC_TYPE_8197F(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) & BIT_MASK_CAMDBG_SEC_TYPE_8197F) +#define BIT_SET_CAMDBG_SEC_TYPE_8197F(x, v) (BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) | BIT_CAMDBG_SEC_TYPE_8197F(v)) + +#define BIT_CAMDBG_EXT_SEC_TYPE_8197F BIT(11) + +#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F 5 +#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F 0x1f +#define BIT_CAMDBG_MIC_KEY_IDX_8197F(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) +#define BITS_CAMDBG_MIC_KEY_IDX_8197F (BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8197F)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8197F(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_8197F(x, v) (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) | BIT_CAMDBG_MIC_KEY_IDX_8197F(v)) + + +#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F 0 +#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F 0x1f +#define BIT_CAMDBG_SEC_KEY_IDX_8197F(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) +#define BITS_CAMDBG_SEC_KEY_IDX_8197F (BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8197F)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8197F(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_8197F(x, v) (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) | BIT_CAMDBG_SEC_KEY_IDX_8197F(v)) + + +/* 2 REG_RXFILTER_ACTION_1_8197F */ + +#define BIT_SHIFT_RXFILTER_ACTION_1_8197F 0 +#define BIT_MASK_RXFILTER_ACTION_1_8197F 0xff +#define BIT_RXFILTER_ACTION_1_8197F(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8197F) << BIT_SHIFT_RXFILTER_ACTION_1_8197F) +#define BITS_RXFILTER_ACTION_1_8197F (BIT_MASK_RXFILTER_ACTION_1_8197F << BIT_SHIFT_RXFILTER_ACTION_1_8197F) +#define BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) ((x) & (~BITS_RXFILTER_ACTION_1_8197F)) +#define BIT_GET_RXFILTER_ACTION_1_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8197F) & BIT_MASK_RXFILTER_ACTION_1_8197F) +#define BIT_SET_RXFILTER_ACTION_1_8197F(x, v) (BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) | BIT_RXFILTER_ACTION_1_8197F(v)) + + +/* 2 REG_RXFILTER_CATEGORY_1_8197F */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_1_8197F 0 +#define BIT_MASK_RXFILTER_CATEGORY_1_8197F 0xff +#define BIT_RXFILTER_CATEGORY_1_8197F(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8197F) << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) +#define BITS_RXFILTER_CATEGORY_1_8197F (BIT_MASK_RXFILTER_CATEGORY_1_8197F << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) +#define BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) ((x) & (~BITS_RXFILTER_CATEGORY_1_8197F)) +#define BIT_GET_RXFILTER_CATEGORY_1_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) & BIT_MASK_RXFILTER_CATEGORY_1_8197F) +#define BIT_SET_RXFILTER_CATEGORY_1_8197F(x, v) (BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) | BIT_RXFILTER_CATEGORY_1_8197F(v)) + + +/* 2 REG_SECCFG_8197F (SECURITY CONFIGURATION REGISTER) */ +#define BIT_DIS_GCLK_WAPI_8197F BIT(15) +#define BIT_DIS_GCLK_AES_8197F BIT(14) +#define BIT_DIS_GCLK_TKIP_8197F BIT(13) +#define BIT_AES_SEL_QC_1_8197F BIT(12) +#define BIT_AES_SEL_QC_0_8197F BIT(11) +#define BIT_WMAC_CKECK_BMC_8197F BIT(9) +#define BIT_CHK_KEYID_8197F BIT(8) +#define BIT_RXBCUSEDK_8197F BIT(7) +#define BIT_TXBCUSEDK_8197F BIT(6) +#define BIT_NOSKMC_8197F BIT(5) +#define BIT_SKBYA2_8197F BIT(4) +#define BIT_RXDEC_8197F BIT(3) +#define BIT_TXENC_8197F BIT(2) +#define BIT_RXUHUSEDK_8197F BIT(1) +#define BIT_TXUHUSEDK_8197F BIT(0) + +/* 2 REG_RXFILTER_ACTION_3_8197F */ + +#define BIT_SHIFT_RXFILTER_ACTION_3_8197F 0 +#define BIT_MASK_RXFILTER_ACTION_3_8197F 0xff +#define BIT_RXFILTER_ACTION_3_8197F(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8197F) << BIT_SHIFT_RXFILTER_ACTION_3_8197F) +#define BITS_RXFILTER_ACTION_3_8197F (BIT_MASK_RXFILTER_ACTION_3_8197F << BIT_SHIFT_RXFILTER_ACTION_3_8197F) +#define BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) ((x) & (~BITS_RXFILTER_ACTION_3_8197F)) +#define BIT_GET_RXFILTER_ACTION_3_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8197F) & BIT_MASK_RXFILTER_ACTION_3_8197F) +#define BIT_SET_RXFILTER_ACTION_3_8197F(x, v) (BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) | BIT_RXFILTER_ACTION_3_8197F(v)) + + +/* 2 REG_RXFILTER_CATEGORY_3_8197F */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_3_8197F 0 +#define BIT_MASK_RXFILTER_CATEGORY_3_8197F 0xff +#define BIT_RXFILTER_CATEGORY_3_8197F(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8197F) << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) +#define BITS_RXFILTER_CATEGORY_3_8197F (BIT_MASK_RXFILTER_CATEGORY_3_8197F << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) +#define BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) ((x) & (~BITS_RXFILTER_CATEGORY_3_8197F)) +#define BIT_GET_RXFILTER_CATEGORY_3_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) & BIT_MASK_RXFILTER_CATEGORY_3_8197F) +#define BIT_SET_RXFILTER_CATEGORY_3_8197F(x, v) (BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) | BIT_RXFILTER_CATEGORY_3_8197F(v)) + + +/* 2 REG_RXFILTER_ACTION_2_8197F */ + +#define BIT_SHIFT_RXFILTER_ACTION_2_8197F 0 +#define BIT_MASK_RXFILTER_ACTION_2_8197F 0xff +#define BIT_RXFILTER_ACTION_2_8197F(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8197F) << BIT_SHIFT_RXFILTER_ACTION_2_8197F) +#define BITS_RXFILTER_ACTION_2_8197F (BIT_MASK_RXFILTER_ACTION_2_8197F << BIT_SHIFT_RXFILTER_ACTION_2_8197F) +#define BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) ((x) & (~BITS_RXFILTER_ACTION_2_8197F)) +#define BIT_GET_RXFILTER_ACTION_2_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8197F) & BIT_MASK_RXFILTER_ACTION_2_8197F) +#define BIT_SET_RXFILTER_ACTION_2_8197F(x, v) (BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) | BIT_RXFILTER_ACTION_2_8197F(v)) + + +/* 2 REG_RXFILTER_CATEGORY_2_8197F */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_2_8197F 0 +#define BIT_MASK_RXFILTER_CATEGORY_2_8197F 0xff +#define BIT_RXFILTER_CATEGORY_2_8197F(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8197F) << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) +#define BITS_RXFILTER_CATEGORY_2_8197F (BIT_MASK_RXFILTER_CATEGORY_2_8197F << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) +#define BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) ((x) & (~BITS_RXFILTER_CATEGORY_2_8197F)) +#define BIT_GET_RXFILTER_CATEGORY_2_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) & BIT_MASK_RXFILTER_CATEGORY_2_8197F) +#define BIT_SET_RXFILTER_CATEGORY_2_8197F(x, v) (BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) | BIT_RXFILTER_CATEGORY_2_8197F(v)) + + +/* 2 REG_RXFLTMAP4_8197F (RX FILTER MAP GROUP 4) */ +#define BIT_CTRLFLT15EN_FW_8197F BIT(15) +#define BIT_CTRLFLT14EN_FW_8197F BIT(14) +#define BIT_CTRLFLT13EN_FW_8197F BIT(13) +#define BIT_CTRLFLT12EN_FW_8197F BIT(12) +#define BIT_CTRLFLT11EN_FW_8197F BIT(11) +#define BIT_CTRLFLT10EN_FW_8197F BIT(10) +#define BIT_CTRLFLT9EN_FW_8197F BIT(9) +#define BIT_CTRLFLT8EN_FW_8197F BIT(8) +#define BIT_CTRLFLT7EN_FW_8197F BIT(7) +#define BIT_CTRLFLT6EN_FW_8197F BIT(6) +#define BIT_CTRLFLT5EN_FW_8197F BIT(5) +#define BIT_CTRLFLT4EN_FW_8197F BIT(4) +#define BIT_CTRLFLT3EN_FW_8197F BIT(3) +#define BIT_CTRLFLT2EN_FW_8197F BIT(2) +#define BIT_CTRLFLT1EN_FW_8197F BIT(1) +#define BIT_CTRLFLT0EN_FW_8197F BIT(0) + +/* 2 REG_RXFLTMAP3_8197F (RX FILTER MAP GROUP 3) */ +#define BIT_MGTFLT15EN_FW_8197F BIT(15) +#define BIT_MGTFLT14EN_FW_8197F BIT(14) +#define BIT_MGTFLT13EN_FW_8197F BIT(13) +#define BIT_MGTFLT12EN_FW_8197F BIT(12) +#define BIT_MGTFLT11EN_FW_8197F BIT(11) +#define BIT_MGTFLT10EN_FW_8197F BIT(10) +#define BIT_MGTFLT9EN_FW_8197F BIT(9) +#define BIT_MGTFLT8EN_FW_8197F BIT(8) +#define BIT_MGTFLT7EN_FW_8197F BIT(7) +#define BIT_MGTFLT6EN_FW_8197F BIT(6) +#define BIT_MGTFLT5EN_FW_8197F BIT(5) +#define BIT_MGTFLT4EN_FW_8197F BIT(4) +#define BIT_MGTFLT3EN_FW_8197F BIT(3) +#define BIT_MGTFLT2EN_FW_8197F BIT(2) +#define BIT_MGTFLT1EN_FW_8197F BIT(1) +#define BIT_MGTFLT0EN_FW_8197F BIT(0) + +/* 2 REG_RXFLTMAP6_8197F (RX FILTER MAP GROUP 3) */ +#define BIT_ACTIONFLT15EN_FW_8197F BIT(15) +#define BIT_ACTIONFLT14EN_FW_8197F BIT(14) +#define BIT_ACTIONFLT13EN_FW_8197F BIT(13) +#define BIT_ACTIONFLT12EN_FW_8197F BIT(12) +#define BIT_ACTIONFLT11EN_FW_8197F BIT(11) +#define BIT_ACTIONFLT10EN_FW_8197F BIT(10) +#define BIT_ACTIONFLT9EN_FW_8197F BIT(9) +#define BIT_ACTIONFLT8EN_FW_8197F BIT(8) +#define BIT_ACTIONFLT7EN_FW_8197F BIT(7) +#define BIT_ACTIONFLT6EN_FW_8197F BIT(6) +#define BIT_ACTIONFLT5EN_FW_8197F BIT(5) +#define BIT_ACTIONFLT4EN_FW_8197F BIT(4) +#define BIT_ACTIONFLT3EN_FW_8197F BIT(3) +#define BIT_ACTIONFLT2EN_FW_8197F BIT(2) +#define BIT_ACTIONFLT1EN_FW_8197F BIT(1) +#define BIT_ACTIONFLT0EN_FW_8197F BIT(0) + +/* 2 REG_RXFLTMAP5_8197F (RX FILTER MAP GROUP 3) */ +#define BIT_DATAFLT15EN_FW_8197F BIT(15) +#define BIT_DATAFLT14EN_FW_8197F BIT(14) +#define BIT_DATAFLT13EN_FW_8197F BIT(13) +#define BIT_DATAFLT12EN_FW_8197F BIT(12) +#define BIT_DATAFLT11EN_FW_8197F BIT(11) +#define BIT_DATAFLT10EN_FW_8197F BIT(10) +#define BIT_DATAFLT9EN_FW_8197F BIT(9) +#define BIT_DATAFLT8EN_FW_8197F BIT(8) +#define BIT_DATAFLT7EN_FW_8197F BIT(7) +#define BIT_DATAFLT6EN_FW_8197F BIT(6) +#define BIT_DATAFLT5EN_FW_8197F BIT(5) +#define BIT_DATAFLT4EN_FW_8197F BIT(4) +#define BIT_DATAFLT3EN_FW_8197F BIT(3) +#define BIT_DATAFLT2EN_FW_8197F BIT(2) +#define BIT_DATAFLT1EN_FW_8197F BIT(1) +#define BIT_DATAFLT0EN_FW_8197F BIT(0) + +/* 2 REG_WMMPS_UAPSD_TID_8197F (WMM POWER SAVE UAPSD TID REGISTER) */ +#define BIT_WMMPS_UAPSD_TID7_8197F BIT(7) +#define BIT_WMMPS_UAPSD_TID6_8197F BIT(6) +#define BIT_WMMPS_UAPSD_TID5_8197F BIT(5) +#define BIT_WMMPS_UAPSD_TID4_8197F BIT(4) +#define BIT_WMMPS_UAPSD_TID3_8197F BIT(3) +#define BIT_WMMPS_UAPSD_TID2_8197F BIT(2) +#define BIT_WMMPS_UAPSD_TID1_8197F BIT(1) +#define BIT_WMMPS_UAPSD_TID0_8197F BIT(0) + +/* 2 REG_PS_RX_INFO_8197F (POWER SAVE RX INFORMATION REGISTER) */ + +#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F 5 +#define BIT_MASK_PORTSEL__PS_RX_INFO_8197F 0x7 +#define BIT_PORTSEL__PS_RX_INFO_8197F(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8197F) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) +#define BITS_PORTSEL__PS_RX_INFO_8197F (BIT_MASK_PORTSEL__PS_RX_INFO_8197F << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) ((x) & (~BITS_PORTSEL__PS_RX_INFO_8197F)) +#define BIT_GET_PORTSEL__PS_RX_INFO_8197F(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) & BIT_MASK_PORTSEL__PS_RX_INFO_8197F) +#define BIT_SET_PORTSEL__PS_RX_INFO_8197F(x, v) (BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) | BIT_PORTSEL__PS_RX_INFO_8197F(v)) + +#define BIT_RXCTRLIN0_8197F BIT(4) +#define BIT_RXMGTIN0_8197F BIT(3) +#define BIT_RXDATAIN2_8197F BIT(2) +#define BIT_RXDATAIN1_8197F BIT(1) +#define BIT_RXDATAIN0_8197F BIT(0) + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_CHK_TSF_TA_8197F BIT(2) +#define BIT_CHK_TSF_CBSSID_8197F BIT(1) +#define BIT_CHK_TSF_EN_8197F BIT(0) + +/* 2 REG_WOW_CTRL_8197F (WAKE ON WLAN CONTROL REGISTER) */ + +#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F 6 +#define BIT_MASK_PSF_BSSIDSEL_B2B1_8197F 0x3 +#define BIT_PSF_BSSIDSEL_B2B1_8197F(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8197F) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) +#define BITS_PSF_BSSIDSEL_B2B1_8197F (BIT_MASK_PSF_BSSIDSEL_B2B1_8197F << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8197F)) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8197F(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) & BIT_MASK_PSF_BSSIDSEL_B2B1_8197F) +#define BIT_SET_PSF_BSSIDSEL_B2B1_8197F(x, v) (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) | BIT_PSF_BSSIDSEL_B2B1_8197F(v)) + +#define BIT_WOWHCI_8197F BIT(5) +#define BIT_PSF_BSSIDSEL_B0_8197F BIT(4) +#define BIT_UWF_8197F BIT(3) +#define BIT_MAGIC_8197F BIT(2) +#define BIT_WOWEN_8197F BIT(1) +#define BIT_FORCE_WAKEUP_8197F BIT(0) + +/* 2 REG_LPNAV_CTRL_8197F (LOW POWER NAV CONTROL REGISTER) */ +#define BIT_LPNAV_EN_8197F BIT(31) + +#define BIT_SHIFT_LPNAV_EARLY_8197F 16 +#define BIT_MASK_LPNAV_EARLY_8197F 0x7fff +#define BIT_LPNAV_EARLY_8197F(x) (((x) & BIT_MASK_LPNAV_EARLY_8197F) << BIT_SHIFT_LPNAV_EARLY_8197F) +#define BITS_LPNAV_EARLY_8197F (BIT_MASK_LPNAV_EARLY_8197F << BIT_SHIFT_LPNAV_EARLY_8197F) +#define BIT_CLEAR_LPNAV_EARLY_8197F(x) ((x) & (~BITS_LPNAV_EARLY_8197F)) +#define BIT_GET_LPNAV_EARLY_8197F(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8197F) & BIT_MASK_LPNAV_EARLY_8197F) +#define BIT_SET_LPNAV_EARLY_8197F(x, v) (BIT_CLEAR_LPNAV_EARLY_8197F(x) | BIT_LPNAV_EARLY_8197F(v)) + + +#define BIT_SHIFT_LPNAV_TH_8197F 0 +#define BIT_MASK_LPNAV_TH_8197F 0xffff +#define BIT_LPNAV_TH_8197F(x) (((x) & BIT_MASK_LPNAV_TH_8197F) << BIT_SHIFT_LPNAV_TH_8197F) +#define BITS_LPNAV_TH_8197F (BIT_MASK_LPNAV_TH_8197F << BIT_SHIFT_LPNAV_TH_8197F) +#define BIT_CLEAR_LPNAV_TH_8197F(x) ((x) & (~BITS_LPNAV_TH_8197F)) +#define BIT_GET_LPNAV_TH_8197F(x) (((x) >> BIT_SHIFT_LPNAV_TH_8197F) & BIT_MASK_LPNAV_TH_8197F) +#define BIT_SET_LPNAV_TH_8197F(x, v) (BIT_CLEAR_LPNAV_TH_8197F(x) | BIT_LPNAV_TH_8197F(v)) + + +/* 2 REG_WKFMCAM_CMD_8197F (WAKEUP FRAME CAM COMMAND REGISTER) */ +#define BIT_WKFCAM_POLLING_V1_8197F BIT(31) +#define BIT_WKFCAM_CLR_V1_8197F BIT(30) +#define BIT_WKFCAM_WE_8197F BIT(16) + +#define BIT_SHIFT_WKFCAM_ADDR_V2_8197F 8 +#define BIT_MASK_WKFCAM_ADDR_V2_8197F 0xff +#define BIT_WKFCAM_ADDR_V2_8197F(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8197F) << BIT_SHIFT_WKFCAM_ADDR_V2_8197F) +#define BITS_WKFCAM_ADDR_V2_8197F (BIT_MASK_WKFCAM_ADDR_V2_8197F << BIT_SHIFT_WKFCAM_ADDR_V2_8197F) +#define BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8197F)) +#define BIT_GET_WKFCAM_ADDR_V2_8197F(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8197F) & BIT_MASK_WKFCAM_ADDR_V2_8197F) +#define BIT_SET_WKFCAM_ADDR_V2_8197F(x, v) (BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) | BIT_WKFCAM_ADDR_V2_8197F(v)) + + +#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F 0 +#define BIT_MASK_WKFCAM_CAM_NUM_V1_8197F 0xff +#define BIT_WKFCAM_CAM_NUM_V1_8197F(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8197F) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) +#define BITS_WKFCAM_CAM_NUM_V1_8197F (BIT_MASK_WKFCAM_CAM_NUM_V1_8197F << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8197F)) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8197F(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) & BIT_MASK_WKFCAM_CAM_NUM_V1_8197F) +#define BIT_SET_WKFCAM_CAM_NUM_V1_8197F(x, v) (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) | BIT_WKFCAM_CAM_NUM_V1_8197F(v)) + + +/* 2 REG_WKFMCAM_RWD_8197F (WAKEUP FRAME READ/WRITE DATA) */ + +#define BIT_SHIFT_WKFMCAM_RWD_8197F 0 +#define BIT_MASK_WKFMCAM_RWD_8197F 0xffffffffL +#define BIT_WKFMCAM_RWD_8197F(x) (((x) & BIT_MASK_WKFMCAM_RWD_8197F) << BIT_SHIFT_WKFMCAM_RWD_8197F) +#define BITS_WKFMCAM_RWD_8197F (BIT_MASK_WKFMCAM_RWD_8197F << BIT_SHIFT_WKFMCAM_RWD_8197F) +#define BIT_CLEAR_WKFMCAM_RWD_8197F(x) ((x) & (~BITS_WKFMCAM_RWD_8197F)) +#define BIT_GET_WKFMCAM_RWD_8197F(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8197F) & BIT_MASK_WKFMCAM_RWD_8197F) +#define BIT_SET_WKFMCAM_RWD_8197F(x, v) (BIT_CLEAR_WKFMCAM_RWD_8197F(x) | BIT_WKFMCAM_RWD_8197F(v)) + + +/* 2 REG_RXFLTMAP1_8197F (RX FILTER MAP GROUP 1) */ +#define BIT_CTRLFLT15EN_8197F BIT(15) +#define BIT_CTRLFLT14EN_8197F BIT(14) +#define BIT_CTRLFLT13EN_8197F BIT(13) +#define BIT_CTRLFLT12EN_8197F BIT(12) +#define BIT_CTRLFLT11EN_8197F BIT(11) +#define BIT_CTRLFLT10EN_8197F BIT(10) +#define BIT_CTRLFLT9EN_8197F BIT(9) +#define BIT_CTRLFLT8EN_8197F BIT(8) +#define BIT_CTRLFLT7EN_8197F BIT(7) +#define BIT_CTRLFLT6EN_8197F BIT(6) +#define BIT_CTRLFLT5EN_8197F BIT(5) +#define BIT_CTRLFLT4EN_8197F BIT(4) +#define BIT_CTRLFLT3EN_8197F BIT(3) +#define BIT_CTRLFLT2EN_8197F BIT(2) +#define BIT_CTRLFLT1EN_8197F BIT(1) +#define BIT_CTRLFLT0EN_8197F BIT(0) + +/* 2 REG_RXFLTMAP0_8197F (RX FILTER MAP GROUP 0) */ +#define BIT_MGTFLT15EN_8197F BIT(15) +#define BIT_MGTFLT14EN_8197F BIT(14) +#define BIT_MGTFLT13EN_8197F BIT(13) +#define BIT_MGTFLT12EN_8197F BIT(12) +#define BIT_MGTFLT11EN_8197F BIT(11) +#define BIT_MGTFLT10EN_8197F BIT(10) +#define BIT_MGTFLT9EN_8197F BIT(9) +#define BIT_MGTFLT8EN_8197F BIT(8) +#define BIT_MGTFLT7EN_8197F BIT(7) +#define BIT_MGTFLT6EN_8197F BIT(6) +#define BIT_MGTFLT5EN_8197F BIT(5) +#define BIT_MGTFLT4EN_8197F BIT(4) +#define BIT_MGTFLT3EN_8197F BIT(3) +#define BIT_MGTFLT2EN_8197F BIT(2) +#define BIT_MGTFLT1EN_8197F BIT(1) +#define BIT_MGTFLT0EN_8197F BIT(0) + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_RXFLTMAP_8197F (RX FILTER MAP GROUP 2) */ +#define BIT_DATAFLT15EN_8197F BIT(15) +#define BIT_DATAFLT14EN_8197F BIT(14) +#define BIT_DATAFLT13EN_8197F BIT(13) +#define BIT_DATAFLT12EN_8197F BIT(12) +#define BIT_DATAFLT11EN_8197F BIT(11) +#define BIT_DATAFLT10EN_8197F BIT(10) +#define BIT_DATAFLT9EN_8197F BIT(9) +#define BIT_DATAFLT8EN_8197F BIT(8) +#define BIT_DATAFLT7EN_8197F BIT(7) +#define BIT_DATAFLT6EN_8197F BIT(6) +#define BIT_DATAFLT5EN_8197F BIT(5) +#define BIT_DATAFLT4EN_8197F BIT(4) +#define BIT_DATAFLT3EN_8197F BIT(3) +#define BIT_DATAFLT2EN_8197F BIT(2) +#define BIT_DATAFLT1EN_8197F BIT(1) +#define BIT_DATAFLT0EN_8197F BIT(0) + +/* 2 REG_BCN_PSR_RPT_8197F (BEACON PARSER REPORT REGISTER) */ + +#define BIT_SHIFT_DTIM_CNT_8197F 24 +#define BIT_MASK_DTIM_CNT_8197F 0xff +#define BIT_DTIM_CNT_8197F(x) (((x) & BIT_MASK_DTIM_CNT_8197F) << BIT_SHIFT_DTIM_CNT_8197F) +#define BITS_DTIM_CNT_8197F (BIT_MASK_DTIM_CNT_8197F << BIT_SHIFT_DTIM_CNT_8197F) +#define BIT_CLEAR_DTIM_CNT_8197F(x) ((x) & (~BITS_DTIM_CNT_8197F)) +#define BIT_GET_DTIM_CNT_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT_8197F) & BIT_MASK_DTIM_CNT_8197F) +#define BIT_SET_DTIM_CNT_8197F(x, v) (BIT_CLEAR_DTIM_CNT_8197F(x) | BIT_DTIM_CNT_8197F(v)) + + +#define BIT_SHIFT_DTIM_PERIOD_8197F 16 +#define BIT_MASK_DTIM_PERIOD_8197F 0xff +#define BIT_DTIM_PERIOD_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD_8197F) << BIT_SHIFT_DTIM_PERIOD_8197F) +#define BITS_DTIM_PERIOD_8197F (BIT_MASK_DTIM_PERIOD_8197F << BIT_SHIFT_DTIM_PERIOD_8197F) +#define BIT_CLEAR_DTIM_PERIOD_8197F(x) ((x) & (~BITS_DTIM_PERIOD_8197F)) +#define BIT_GET_DTIM_PERIOD_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8197F) & BIT_MASK_DTIM_PERIOD_8197F) +#define BIT_SET_DTIM_PERIOD_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD_8197F(x) | BIT_DTIM_PERIOD_8197F(v)) + +#define BIT_DTIM_8197F BIT(15) +#define BIT_TIM_8197F BIT(14) + +#define BIT_SHIFT_PS_AID_0_8197F 0 +#define BIT_MASK_PS_AID_0_8197F 0x7ff +#define BIT_PS_AID_0_8197F(x) (((x) & BIT_MASK_PS_AID_0_8197F) << BIT_SHIFT_PS_AID_0_8197F) +#define BITS_PS_AID_0_8197F (BIT_MASK_PS_AID_0_8197F << BIT_SHIFT_PS_AID_0_8197F) +#define BIT_CLEAR_PS_AID_0_8197F(x) ((x) & (~BITS_PS_AID_0_8197F)) +#define BIT_GET_PS_AID_0_8197F(x) (((x) >> BIT_SHIFT_PS_AID_0_8197F) & BIT_MASK_PS_AID_0_8197F) +#define BIT_SET_PS_AID_0_8197F(x, v) (BIT_CLEAR_PS_AID_0_8197F(x) | BIT_PS_AID_0_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_FLC_RPCT_V1_8197F BIT(7) +#define BIT_MODE_8197F BIT(6) + +#define BIT_SHIFT_TRPCD_8197F 0 +#define BIT_MASK_TRPCD_8197F 0x3f +#define BIT_TRPCD_8197F(x) (((x) & BIT_MASK_TRPCD_8197F) << BIT_SHIFT_TRPCD_8197F) +#define BITS_TRPCD_8197F (BIT_MASK_TRPCD_8197F << BIT_SHIFT_TRPCD_8197F) +#define BIT_CLEAR_TRPCD_8197F(x) ((x) & (~BITS_TRPCD_8197F)) +#define BIT_GET_TRPCD_8197F(x) (((x) >> BIT_SHIFT_TRPCD_8197F) & BIT_MASK_TRPCD_8197F) +#define BIT_SET_TRPCD_8197F(x, v) (BIT_CLEAR_TRPCD_8197F(x) | BIT_TRPCD_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_CMF_8197F BIT(2) +#define BIT_CCF_8197F BIT(1) +#define BIT_CDF_8197F BIT(0) + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_FLC_RPCT_8197F 0 +#define BIT_MASK_FLC_RPCT_8197F 0xff +#define BIT_FLC_RPCT_8197F(x) (((x) & BIT_MASK_FLC_RPCT_8197F) << BIT_SHIFT_FLC_RPCT_8197F) +#define BITS_FLC_RPCT_8197F (BIT_MASK_FLC_RPCT_8197F << BIT_SHIFT_FLC_RPCT_8197F) +#define BIT_CLEAR_FLC_RPCT_8197F(x) ((x) & (~BITS_FLC_RPCT_8197F)) +#define BIT_GET_FLC_RPCT_8197F(x) (((x) >> BIT_SHIFT_FLC_RPCT_8197F) & BIT_MASK_FLC_RPCT_8197F) +#define BIT_SET_FLC_RPCT_8197F(x, v) (BIT_CLEAR_FLC_RPCT_8197F(x) | BIT_FLC_RPCT_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +#define BIT_SHIFT_FLC_RPC_8197F 0 +#define BIT_MASK_FLC_RPC_8197F 0xff +#define BIT_FLC_RPC_8197F(x) (((x) & BIT_MASK_FLC_RPC_8197F) << BIT_SHIFT_FLC_RPC_8197F) +#define BITS_FLC_RPC_8197F (BIT_MASK_FLC_RPC_8197F << BIT_SHIFT_FLC_RPC_8197F) +#define BIT_CLEAR_FLC_RPC_8197F(x) ((x) & (~BITS_FLC_RPC_8197F)) +#define BIT_GET_FLC_RPC_8197F(x) (((x) >> BIT_SHIFT_FLC_RPC_8197F) & BIT_MASK_FLC_RPC_8197F) +#define BIT_SET_FLC_RPC_8197F(x, v) (BIT_CLEAR_FLC_RPC_8197F(x) | BIT_FLC_RPC_8197F(v)) + + +/* 2 REG_RXPKTMON_CTRL_8197F */ + +#define BIT_SHIFT_RXBKQPKT_SEQ_8197F 20 +#define BIT_MASK_RXBKQPKT_SEQ_8197F 0xf +#define BIT_RXBKQPKT_SEQ_8197F(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8197F) << BIT_SHIFT_RXBKQPKT_SEQ_8197F) +#define BITS_RXBKQPKT_SEQ_8197F (BIT_MASK_RXBKQPKT_SEQ_8197F << BIT_SHIFT_RXBKQPKT_SEQ_8197F) +#define BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) ((x) & (~BITS_RXBKQPKT_SEQ_8197F)) +#define BIT_GET_RXBKQPKT_SEQ_8197F(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8197F) & BIT_MASK_RXBKQPKT_SEQ_8197F) +#define BIT_SET_RXBKQPKT_SEQ_8197F(x, v) (BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) | BIT_RXBKQPKT_SEQ_8197F(v)) + + +#define BIT_SHIFT_RXBEQPKT_SEQ_8197F 16 +#define BIT_MASK_RXBEQPKT_SEQ_8197F 0xf +#define BIT_RXBEQPKT_SEQ_8197F(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8197F) << BIT_SHIFT_RXBEQPKT_SEQ_8197F) +#define BITS_RXBEQPKT_SEQ_8197F (BIT_MASK_RXBEQPKT_SEQ_8197F << BIT_SHIFT_RXBEQPKT_SEQ_8197F) +#define BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) ((x) & (~BITS_RXBEQPKT_SEQ_8197F)) +#define BIT_GET_RXBEQPKT_SEQ_8197F(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8197F) & BIT_MASK_RXBEQPKT_SEQ_8197F) +#define BIT_SET_RXBEQPKT_SEQ_8197F(x, v) (BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) | BIT_RXBEQPKT_SEQ_8197F(v)) + + +#define BIT_SHIFT_RXVIQPKT_SEQ_8197F 12 +#define BIT_MASK_RXVIQPKT_SEQ_8197F 0xf +#define BIT_RXVIQPKT_SEQ_8197F(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8197F) << BIT_SHIFT_RXVIQPKT_SEQ_8197F) +#define BITS_RXVIQPKT_SEQ_8197F (BIT_MASK_RXVIQPKT_SEQ_8197F << BIT_SHIFT_RXVIQPKT_SEQ_8197F) +#define BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) ((x) & (~BITS_RXVIQPKT_SEQ_8197F)) +#define BIT_GET_RXVIQPKT_SEQ_8197F(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8197F) & BIT_MASK_RXVIQPKT_SEQ_8197F) +#define BIT_SET_RXVIQPKT_SEQ_8197F(x, v) (BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) | BIT_RXVIQPKT_SEQ_8197F(v)) + + +#define BIT_SHIFT_RXVOQPKT_SEQ_8197F 8 +#define BIT_MASK_RXVOQPKT_SEQ_8197F 0xf +#define BIT_RXVOQPKT_SEQ_8197F(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8197F) << BIT_SHIFT_RXVOQPKT_SEQ_8197F) +#define BITS_RXVOQPKT_SEQ_8197F (BIT_MASK_RXVOQPKT_SEQ_8197F << BIT_SHIFT_RXVOQPKT_SEQ_8197F) +#define BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) ((x) & (~BITS_RXVOQPKT_SEQ_8197F)) +#define BIT_GET_RXVOQPKT_SEQ_8197F(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8197F) & BIT_MASK_RXVOQPKT_SEQ_8197F) +#define BIT_SET_RXVOQPKT_SEQ_8197F(x, v) (BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) | BIT_RXVOQPKT_SEQ_8197F(v)) + +#define BIT_RXBKQPKT_ERR_8197F BIT(7) +#define BIT_RXBEQPKT_ERR_8197F BIT(6) +#define BIT_RXVIQPKT_ERR_8197F BIT(5) +#define BIT_RXVOQPKT_ERR_8197F BIT(4) +#define BIT_RXDMA_MON_EN_8197F BIT(2) +#define BIT_RXPKT_MON_RST_8197F BIT(1) +#define BIT_RXPKT_MON_EN_8197F BIT(0) + +/* 2 REG_STATE_MON_8197F */ + +#define BIT_SHIFT_STATE_SEL_8197F 24 +#define BIT_MASK_STATE_SEL_8197F 0x1f +#define BIT_STATE_SEL_8197F(x) (((x) & BIT_MASK_STATE_SEL_8197F) << BIT_SHIFT_STATE_SEL_8197F) +#define BITS_STATE_SEL_8197F (BIT_MASK_STATE_SEL_8197F << BIT_SHIFT_STATE_SEL_8197F) +#define BIT_CLEAR_STATE_SEL_8197F(x) ((x) & (~BITS_STATE_SEL_8197F)) +#define BIT_GET_STATE_SEL_8197F(x) (((x) >> BIT_SHIFT_STATE_SEL_8197F) & BIT_MASK_STATE_SEL_8197F) +#define BIT_SET_STATE_SEL_8197F(x, v) (BIT_CLEAR_STATE_SEL_8197F(x) | BIT_STATE_SEL_8197F(v)) + + +#define BIT_SHIFT_STATE_INFO_8197F 8 +#define BIT_MASK_STATE_INFO_8197F 0xff +#define BIT_STATE_INFO_8197F(x) (((x) & BIT_MASK_STATE_INFO_8197F) << BIT_SHIFT_STATE_INFO_8197F) +#define BITS_STATE_INFO_8197F (BIT_MASK_STATE_INFO_8197F << BIT_SHIFT_STATE_INFO_8197F) +#define BIT_CLEAR_STATE_INFO_8197F(x) ((x) & (~BITS_STATE_INFO_8197F)) +#define BIT_GET_STATE_INFO_8197F(x) (((x) >> BIT_SHIFT_STATE_INFO_8197F) & BIT_MASK_STATE_INFO_8197F) +#define BIT_SET_STATE_INFO_8197F(x, v) (BIT_CLEAR_STATE_INFO_8197F(x) | BIT_STATE_INFO_8197F(v)) + +#define BIT_UPD_NXT_STATE_8197F BIT(7) + +#define BIT_SHIFT_CUR_STATE_8197F 0 +#define BIT_MASK_CUR_STATE_8197F 0x7f +#define BIT_CUR_STATE_8197F(x) (((x) & BIT_MASK_CUR_STATE_8197F) << BIT_SHIFT_CUR_STATE_8197F) +#define BITS_CUR_STATE_8197F (BIT_MASK_CUR_STATE_8197F << BIT_SHIFT_CUR_STATE_8197F) +#define BIT_CLEAR_CUR_STATE_8197F(x) ((x) & (~BITS_CUR_STATE_8197F)) +#define BIT_GET_CUR_STATE_8197F(x) (((x) >> BIT_SHIFT_CUR_STATE_8197F) & BIT_MASK_CUR_STATE_8197F) +#define BIT_SET_CUR_STATE_8197F(x, v) (BIT_CLEAR_CUR_STATE_8197F(x) | BIT_CUR_STATE_8197F(v)) + + +/* 2 REG_ERROR_MON_8197F */ +#define BIT_MACRX_ERR_1_8197F BIT(17) +#define BIT_MACRX_ERR_0_8197F BIT(16) +#define BIT_MACTX_ERR_3_8197F BIT(3) +#define BIT_MACTX_ERR_2_8197F BIT(2) +#define BIT_MACTX_ERR_1_8197F BIT(1) +#define BIT_MACTX_ERR_0_8197F BIT(0) + +/* 2 REG_SEARCH_MACID_8197F */ +#define BIT_EN_TXRPTBUF_CLK_8197F BIT(31) + +#define BIT_SHIFT_INFO_INDEX_OFFSET_8197F 16 +#define BIT_MASK_INFO_INDEX_OFFSET_8197F 0x1fff +#define BIT_INFO_INDEX_OFFSET_8197F(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8197F) << BIT_SHIFT_INFO_INDEX_OFFSET_8197F) +#define BITS_INFO_INDEX_OFFSET_8197F (BIT_MASK_INFO_INDEX_OFFSET_8197F << BIT_SHIFT_INFO_INDEX_OFFSET_8197F) +#define BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) ((x) & (~BITS_INFO_INDEX_OFFSET_8197F)) +#define BIT_GET_INFO_INDEX_OFFSET_8197F(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8197F) & BIT_MASK_INFO_INDEX_OFFSET_8197F) +#define BIT_SET_INFO_INDEX_OFFSET_8197F(x, v) (BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) | BIT_INFO_INDEX_OFFSET_8197F(v)) + +#define BIT_DIS_INFOSRCH_8197F BIT(14) +#define BIT_DISABLE_B0_8197F BIT(13) + +#define BIT_SHIFT_INFO_ADDR_OFFSET_8197F 0 +#define BIT_MASK_INFO_ADDR_OFFSET_8197F 0x1fff +#define BIT_INFO_ADDR_OFFSET_8197F(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8197F) << BIT_SHIFT_INFO_ADDR_OFFSET_8197F) +#define BITS_INFO_ADDR_OFFSET_8197F (BIT_MASK_INFO_ADDR_OFFSET_8197F << BIT_SHIFT_INFO_ADDR_OFFSET_8197F) +#define BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) ((x) & (~BITS_INFO_ADDR_OFFSET_8197F)) +#define BIT_GET_INFO_ADDR_OFFSET_8197F(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8197F) & BIT_MASK_INFO_ADDR_OFFSET_8197F) +#define BIT_SET_INFO_ADDR_OFFSET_8197F(x, v) (BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) | BIT_INFO_ADDR_OFFSET_8197F(v)) + + +/* 2 REG_BT_COEX_TABLE_8197F (BT-COEXISTENCE CONTROL REGISTER) */ +#define BIT_PRI_MASK_RX_RESP_8197F BIT(126) +#define BIT_PRI_MASK_RXOFDM_8197F BIT(125) +#define BIT_PRI_MASK_RXCCK_8197F BIT(124) + +#define BIT_SHIFT_PRI_MASK_TXAC_8197F (117 & CPU_OPT_WIDTH) +#define BIT_MASK_PRI_MASK_TXAC_8197F 0x7f +#define BIT_PRI_MASK_TXAC_8197F(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8197F) << BIT_SHIFT_PRI_MASK_TXAC_8197F) +#define BITS_PRI_MASK_TXAC_8197F (BIT_MASK_PRI_MASK_TXAC_8197F << BIT_SHIFT_PRI_MASK_TXAC_8197F) +#define BIT_CLEAR_PRI_MASK_TXAC_8197F(x) ((x) & (~BITS_PRI_MASK_TXAC_8197F)) +#define BIT_GET_PRI_MASK_TXAC_8197F(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8197F) & BIT_MASK_PRI_MASK_TXAC_8197F) +#define BIT_SET_PRI_MASK_TXAC_8197F(x, v) (BIT_CLEAR_PRI_MASK_TXAC_8197F(x) | BIT_PRI_MASK_TXAC_8197F(v)) + + +#define BIT_SHIFT_PRI_MASK_NAV_8197F (109 & CPU_OPT_WIDTH) +#define BIT_MASK_PRI_MASK_NAV_8197F 0xff +#define BIT_PRI_MASK_NAV_8197F(x) (((x) & BIT_MASK_PRI_MASK_NAV_8197F) << BIT_SHIFT_PRI_MASK_NAV_8197F) +#define BITS_PRI_MASK_NAV_8197F (BIT_MASK_PRI_MASK_NAV_8197F << BIT_SHIFT_PRI_MASK_NAV_8197F) +#define BIT_CLEAR_PRI_MASK_NAV_8197F(x) ((x) & (~BITS_PRI_MASK_NAV_8197F)) +#define BIT_GET_PRI_MASK_NAV_8197F(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8197F) & BIT_MASK_PRI_MASK_NAV_8197F) +#define BIT_SET_PRI_MASK_NAV_8197F(x, v) (BIT_CLEAR_PRI_MASK_NAV_8197F(x) | BIT_PRI_MASK_NAV_8197F(v)) + +#define BIT_PRI_MASK_CCK_8197F BIT(108) +#define BIT_PRI_MASK_OFDM_8197F BIT(107) +#define BIT_PRI_MASK_RTY_8197F BIT(106) + +#define BIT_SHIFT_PRI_MASK_NUM_8197F (102 & CPU_OPT_WIDTH) +#define BIT_MASK_PRI_MASK_NUM_8197F 0xf +#define BIT_PRI_MASK_NUM_8197F(x) (((x) & BIT_MASK_PRI_MASK_NUM_8197F) << BIT_SHIFT_PRI_MASK_NUM_8197F) +#define BITS_PRI_MASK_NUM_8197F (BIT_MASK_PRI_MASK_NUM_8197F << BIT_SHIFT_PRI_MASK_NUM_8197F) +#define BIT_CLEAR_PRI_MASK_NUM_8197F(x) ((x) & (~BITS_PRI_MASK_NUM_8197F)) +#define BIT_GET_PRI_MASK_NUM_8197F(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8197F) & BIT_MASK_PRI_MASK_NUM_8197F) +#define BIT_SET_PRI_MASK_NUM_8197F(x, v) (BIT_CLEAR_PRI_MASK_NUM_8197F(x) | BIT_PRI_MASK_NUM_8197F(v)) + + +#define BIT_SHIFT_PRI_MASK_TYPE_8197F (98 & CPU_OPT_WIDTH) +#define BIT_MASK_PRI_MASK_TYPE_8197F 0xf +#define BIT_PRI_MASK_TYPE_8197F(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8197F) << BIT_SHIFT_PRI_MASK_TYPE_8197F) +#define BITS_PRI_MASK_TYPE_8197F (BIT_MASK_PRI_MASK_TYPE_8197F << BIT_SHIFT_PRI_MASK_TYPE_8197F) +#define BIT_CLEAR_PRI_MASK_TYPE_8197F(x) ((x) & (~BITS_PRI_MASK_TYPE_8197F)) +#define BIT_GET_PRI_MASK_TYPE_8197F(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8197F) & BIT_MASK_PRI_MASK_TYPE_8197F) +#define BIT_SET_PRI_MASK_TYPE_8197F(x, v) (BIT_CLEAR_PRI_MASK_TYPE_8197F(x) | BIT_PRI_MASK_TYPE_8197F(v)) + +#define BIT_OOB_8197F BIT(97) +#define BIT_ANT_SEL_8197F BIT(96) + +#define BIT_SHIFT_BREAK_TABLE_2_8197F (80 & CPU_OPT_WIDTH) +#define BIT_MASK_BREAK_TABLE_2_8197F 0xffff +#define BIT_BREAK_TABLE_2_8197F(x) (((x) & BIT_MASK_BREAK_TABLE_2_8197F) << BIT_SHIFT_BREAK_TABLE_2_8197F) +#define BITS_BREAK_TABLE_2_8197F (BIT_MASK_BREAK_TABLE_2_8197F << BIT_SHIFT_BREAK_TABLE_2_8197F) +#define BIT_CLEAR_BREAK_TABLE_2_8197F(x) ((x) & (~BITS_BREAK_TABLE_2_8197F)) +#define BIT_GET_BREAK_TABLE_2_8197F(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8197F) & BIT_MASK_BREAK_TABLE_2_8197F) +#define BIT_SET_BREAK_TABLE_2_8197F(x, v) (BIT_CLEAR_BREAK_TABLE_2_8197F(x) | BIT_BREAK_TABLE_2_8197F(v)) + + +#define BIT_SHIFT_BREAK_TABLE_1_8197F (64 & CPU_OPT_WIDTH) +#define BIT_MASK_BREAK_TABLE_1_8197F 0xffff +#define BIT_BREAK_TABLE_1_8197F(x) (((x) & BIT_MASK_BREAK_TABLE_1_8197F) << BIT_SHIFT_BREAK_TABLE_1_8197F) +#define BITS_BREAK_TABLE_1_8197F (BIT_MASK_BREAK_TABLE_1_8197F << BIT_SHIFT_BREAK_TABLE_1_8197F) +#define BIT_CLEAR_BREAK_TABLE_1_8197F(x) ((x) & (~BITS_BREAK_TABLE_1_8197F)) +#define BIT_GET_BREAK_TABLE_1_8197F(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8197F) & BIT_MASK_BREAK_TABLE_1_8197F) +#define BIT_SET_BREAK_TABLE_1_8197F(x, v) (BIT_CLEAR_BREAK_TABLE_1_8197F(x) | BIT_BREAK_TABLE_1_8197F(v)) + + +#define BIT_SHIFT_COEX_TABLE_2_8197F (32 & CPU_OPT_WIDTH) +#define BIT_MASK_COEX_TABLE_2_8197F 0xffffffffL +#define BIT_COEX_TABLE_2_8197F(x) (((x) & BIT_MASK_COEX_TABLE_2_8197F) << BIT_SHIFT_COEX_TABLE_2_8197F) +#define BITS_COEX_TABLE_2_8197F (BIT_MASK_COEX_TABLE_2_8197F << BIT_SHIFT_COEX_TABLE_2_8197F) +#define BIT_CLEAR_COEX_TABLE_2_8197F(x) ((x) & (~BITS_COEX_TABLE_2_8197F)) +#define BIT_GET_COEX_TABLE_2_8197F(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8197F) & BIT_MASK_COEX_TABLE_2_8197F) +#define BIT_SET_COEX_TABLE_2_8197F(x, v) (BIT_CLEAR_COEX_TABLE_2_8197F(x) | BIT_COEX_TABLE_2_8197F(v)) + + +#define BIT_SHIFT_COEX_TABLE_1_8197F 0 +#define BIT_MASK_COEX_TABLE_1_8197F 0xffffffffL +#define BIT_COEX_TABLE_1_8197F(x) (((x) & BIT_MASK_COEX_TABLE_1_8197F) << BIT_SHIFT_COEX_TABLE_1_8197F) +#define BITS_COEX_TABLE_1_8197F (BIT_MASK_COEX_TABLE_1_8197F << BIT_SHIFT_COEX_TABLE_1_8197F) +#define BIT_CLEAR_COEX_TABLE_1_8197F(x) ((x) & (~BITS_COEX_TABLE_1_8197F)) +#define BIT_GET_COEX_TABLE_1_8197F(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8197F) & BIT_MASK_COEX_TABLE_1_8197F) +#define BIT_SET_COEX_TABLE_1_8197F(x, v) (BIT_CLEAR_COEX_TABLE_1_8197F(x) | BIT_COEX_TABLE_1_8197F(v)) + + +/* 2 REG_RXCMD_0_8197F */ +#define BIT_RXCMD_EN_8197F BIT(31) + +#define BIT_SHIFT_RXCMD_INFO_8197F 0 +#define BIT_MASK_RXCMD_INFO_8197F 0x7fffffffL +#define BIT_RXCMD_INFO_8197F(x) (((x) & BIT_MASK_RXCMD_INFO_8197F) << BIT_SHIFT_RXCMD_INFO_8197F) +#define BITS_RXCMD_INFO_8197F (BIT_MASK_RXCMD_INFO_8197F << BIT_SHIFT_RXCMD_INFO_8197F) +#define BIT_CLEAR_RXCMD_INFO_8197F(x) ((x) & (~BITS_RXCMD_INFO_8197F)) +#define BIT_GET_RXCMD_INFO_8197F(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8197F) & BIT_MASK_RXCMD_INFO_8197F) +#define BIT_SET_RXCMD_INFO_8197F(x, v) (BIT_CLEAR_RXCMD_INFO_8197F(x) | BIT_RXCMD_INFO_8197F(v)) + + +/* 2 REG_RXCMD_1_8197F */ + +#define BIT_SHIFT_RXCMD_PRD_8197F 0 +#define BIT_MASK_RXCMD_PRD_8197F 0xffff +#define BIT_RXCMD_PRD_8197F(x) (((x) & BIT_MASK_RXCMD_PRD_8197F) << BIT_SHIFT_RXCMD_PRD_8197F) +#define BITS_RXCMD_PRD_8197F (BIT_MASK_RXCMD_PRD_8197F << BIT_SHIFT_RXCMD_PRD_8197F) +#define BIT_CLEAR_RXCMD_PRD_8197F(x) ((x) & (~BITS_RXCMD_PRD_8197F)) +#define BIT_GET_RXCMD_PRD_8197F(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8197F) & BIT_MASK_RXCMD_PRD_8197F) +#define BIT_SET_RXCMD_PRD_8197F(x, v) (BIT_CLEAR_RXCMD_PRD_8197F(x) | BIT_RXCMD_PRD_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_WMAC_RESP_TXINFO_8197F (RESPONSE TXINFO REGISTER) */ + +#define BIT_SHIFT_WMAC_RESP_MFB_8197F 25 +#define BIT_MASK_WMAC_RESP_MFB_8197F 0x7f +#define BIT_WMAC_RESP_MFB_8197F(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8197F) << BIT_SHIFT_WMAC_RESP_MFB_8197F) +#define BITS_WMAC_RESP_MFB_8197F (BIT_MASK_WMAC_RESP_MFB_8197F << BIT_SHIFT_WMAC_RESP_MFB_8197F) +#define BIT_CLEAR_WMAC_RESP_MFB_8197F(x) ((x) & (~BITS_WMAC_RESP_MFB_8197F)) +#define BIT_GET_WMAC_RESP_MFB_8197F(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8197F) & BIT_MASK_WMAC_RESP_MFB_8197F) +#define BIT_SET_WMAC_RESP_MFB_8197F(x, v) (BIT_CLEAR_WMAC_RESP_MFB_8197F(x) | BIT_WMAC_RESP_MFB_8197F(v)) + + +#define BIT_SHIFT_WMAC_ANTINF_SEL_8197F 23 +#define BIT_MASK_WMAC_ANTINF_SEL_8197F 0x3 +#define BIT_WMAC_ANTINF_SEL_8197F(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8197F) << BIT_SHIFT_WMAC_ANTINF_SEL_8197F) +#define BITS_WMAC_ANTINF_SEL_8197F (BIT_MASK_WMAC_ANTINF_SEL_8197F << BIT_SHIFT_WMAC_ANTINF_SEL_8197F) +#define BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8197F)) +#define BIT_GET_WMAC_ANTINF_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8197F) & BIT_MASK_WMAC_ANTINF_SEL_8197F) +#define BIT_SET_WMAC_ANTINF_SEL_8197F(x, v) (BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) | BIT_WMAC_ANTINF_SEL_8197F(v)) + + +#define BIT_SHIFT_WMAC_ANTSEL_SEL_8197F 21 +#define BIT_MASK_WMAC_ANTSEL_SEL_8197F 0x3 +#define BIT_WMAC_ANTSEL_SEL_8197F(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8197F) << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) +#define BITS_WMAC_ANTSEL_SEL_8197F (BIT_MASK_WMAC_ANTSEL_SEL_8197F << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) +#define BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8197F)) +#define BIT_GET_WMAC_ANTSEL_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) & BIT_MASK_WMAC_ANTSEL_SEL_8197F) +#define BIT_SET_WMAC_ANTSEL_SEL_8197F(x, v) (BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) | BIT_WMAC_ANTSEL_SEL_8197F(v)) + + +#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F 18 +#define BIT_MASK_R_WMAC_RESP_TXPOWER_8197F 0x7 +#define BIT_R_WMAC_RESP_TXPOWER_8197F(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8197F) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) +#define BITS_R_WMAC_RESP_TXPOWER_8197F (BIT_MASK_R_WMAC_RESP_TXPOWER_8197F << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) +#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) ((x) & (~BITS_R_WMAC_RESP_TXPOWER_8197F)) +#define BIT_GET_R_WMAC_RESP_TXPOWER_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) & BIT_MASK_R_WMAC_RESP_TXPOWER_8197F) +#define BIT_SET_R_WMAC_RESP_TXPOWER_8197F(x, v) (BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) | BIT_R_WMAC_RESP_TXPOWER_8197F(v)) + + +#define BIT_SHIFT_WMAC_RESP_TXANT_8197F 0 +#define BIT_MASK_WMAC_RESP_TXANT_8197F 0x3ffff +#define BIT_WMAC_RESP_TXANT_8197F(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8197F) << BIT_SHIFT_WMAC_RESP_TXANT_8197F) +#define BITS_WMAC_RESP_TXANT_8197F (BIT_MASK_WMAC_RESP_TXANT_8197F << BIT_SHIFT_WMAC_RESP_TXANT_8197F) +#define BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) ((x) & (~BITS_WMAC_RESP_TXANT_8197F)) +#define BIT_GET_WMAC_RESP_TXANT_8197F(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8197F) & BIT_MASK_WMAC_RESP_TXANT_8197F) +#define BIT_SET_WMAC_RESP_TXANT_8197F(x, v) (BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) | BIT_WMAC_RESP_TXANT_8197F(v)) + + +/* 2 REG_BBPSF_CTRL_8197F */ +#define BIT_CTL_IDLE_CLR_CSI_RPT_8197F BIT(31) +#define BIT_WMAC_USE_NDPARATE_8197F BIT(30) + +#define BIT_SHIFT_WMAC_CSI_RATE_8197F 24 +#define BIT_MASK_WMAC_CSI_RATE_8197F 0x3f +#define BIT_WMAC_CSI_RATE_8197F(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8197F) << BIT_SHIFT_WMAC_CSI_RATE_8197F) +#define BITS_WMAC_CSI_RATE_8197F (BIT_MASK_WMAC_CSI_RATE_8197F << BIT_SHIFT_WMAC_CSI_RATE_8197F) +#define BIT_CLEAR_WMAC_CSI_RATE_8197F(x) ((x) & (~BITS_WMAC_CSI_RATE_8197F)) +#define BIT_GET_WMAC_CSI_RATE_8197F(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8197F) & BIT_MASK_WMAC_CSI_RATE_8197F) +#define BIT_SET_WMAC_CSI_RATE_8197F(x, v) (BIT_CLEAR_WMAC_CSI_RATE_8197F(x) | BIT_WMAC_CSI_RATE_8197F(v)) + + +#define BIT_SHIFT_WMAC_RESP_TXRATE_8197F 16 +#define BIT_MASK_WMAC_RESP_TXRATE_8197F 0xff +#define BIT_WMAC_RESP_TXRATE_8197F(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8197F) << BIT_SHIFT_WMAC_RESP_TXRATE_8197F) +#define BITS_WMAC_RESP_TXRATE_8197F (BIT_MASK_WMAC_RESP_TXRATE_8197F << BIT_SHIFT_WMAC_RESP_TXRATE_8197F) +#define BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) ((x) & (~BITS_WMAC_RESP_TXRATE_8197F)) +#define BIT_GET_WMAC_RESP_TXRATE_8197F(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8197F) & BIT_MASK_WMAC_RESP_TXRATE_8197F) +#define BIT_SET_WMAC_RESP_TXRATE_8197F(x, v) (BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) | BIT_WMAC_RESP_TXRATE_8197F(v)) + +#define BIT_BBPSF_MPDUCHKEN_8197F BIT(5) +#define BIT_BBPSF_MHCHKEN_8197F BIT(4) +#define BIT_BBPSF_ERRCHKEN_8197F BIT(3) + +#define BIT_SHIFT_BBPSF_ERRTHR_8197F 0 +#define BIT_MASK_BBPSF_ERRTHR_8197F 0x7 +#define BIT_BBPSF_ERRTHR_8197F(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8197F) << BIT_SHIFT_BBPSF_ERRTHR_8197F) +#define BITS_BBPSF_ERRTHR_8197F (BIT_MASK_BBPSF_ERRTHR_8197F << BIT_SHIFT_BBPSF_ERRTHR_8197F) +#define BIT_CLEAR_BBPSF_ERRTHR_8197F(x) ((x) & (~BITS_BBPSF_ERRTHR_8197F)) +#define BIT_GET_BBPSF_ERRTHR_8197F(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8197F) & BIT_MASK_BBPSF_ERRTHR_8197F) +#define BIT_SET_BBPSF_ERRTHR_8197F(x, v) (BIT_CLEAR_BBPSF_ERRTHR_8197F(x) | BIT_BBPSF_ERRTHR_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_P2P_RX_BCN_NOA_8197F (P2P RX BEACON NOA REGISTER) */ +#define BIT_NOA_PARSER_EN_8197F BIT(15) + +#define BIT_SHIFT_BSSID_SEL_8197F 12 +#define BIT_MASK_BSSID_SEL_8197F 0x7 +#define BIT_BSSID_SEL_8197F(x) (((x) & BIT_MASK_BSSID_SEL_8197F) << BIT_SHIFT_BSSID_SEL_8197F) +#define BITS_BSSID_SEL_8197F (BIT_MASK_BSSID_SEL_8197F << BIT_SHIFT_BSSID_SEL_8197F) +#define BIT_CLEAR_BSSID_SEL_8197F(x) ((x) & (~BITS_BSSID_SEL_8197F)) +#define BIT_GET_BSSID_SEL_8197F(x) (((x) >> BIT_SHIFT_BSSID_SEL_8197F) & BIT_MASK_BSSID_SEL_8197F) +#define BIT_SET_BSSID_SEL_8197F(x, v) (BIT_CLEAR_BSSID_SEL_8197F(x) | BIT_BSSID_SEL_8197F(v)) + + +#define BIT_SHIFT_P2P_OUI_TYPE_8197F 0 +#define BIT_MASK_P2P_OUI_TYPE_8197F 0xff +#define BIT_P2P_OUI_TYPE_8197F(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8197F) << BIT_SHIFT_P2P_OUI_TYPE_8197F) +#define BITS_P2P_OUI_TYPE_8197F (BIT_MASK_P2P_OUI_TYPE_8197F << BIT_SHIFT_P2P_OUI_TYPE_8197F) +#define BIT_CLEAR_P2P_OUI_TYPE_8197F(x) ((x) & (~BITS_P2P_OUI_TYPE_8197F)) +#define BIT_GET_P2P_OUI_TYPE_8197F(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8197F) & BIT_MASK_P2P_OUI_TYPE_8197F) +#define BIT_SET_P2P_OUI_TYPE_8197F(x, v) (BIT_CLEAR_P2P_OUI_TYPE_8197F(x) | BIT_P2P_OUI_TYPE_8197F(v)) + + +/* 2 REG_ASSOCIATED_BFMER0_INFO_8197F (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F (48 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_TXCSI_AID0_8197F 0x1ff +#define BIT_R_WMAC_TXCSI_AID0_8197F(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8197F) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) +#define BITS_R_WMAC_TXCSI_AID0_8197F (BIT_MASK_R_WMAC_TXCSI_AID0_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) +#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) ((x) & (~BITS_R_WMAC_TXCSI_AID0_8197F)) +#define BIT_GET_R_WMAC_TXCSI_AID0_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) & BIT_MASK_R_WMAC_TXCSI_AID0_8197F) +#define BIT_SET_R_WMAC_TXCSI_AID0_8197F(x, v) (BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) | BIT_R_WMAC_TXCSI_AID0_8197F(v)) + + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F 0xffffffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_8197F (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8197F)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8197F(x, v) (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) | BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(v)) + + +/* 2 REG_ASSOCIATED_BFMER1_INFO_8197F (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F (48 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_TXCSI_AID1_8197F 0x1ff +#define BIT_R_WMAC_TXCSI_AID1_8197F(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8197F) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) +#define BITS_R_WMAC_TXCSI_AID1_8197F (BIT_MASK_R_WMAC_TXCSI_AID1_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) +#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) ((x) & (~BITS_R_WMAC_TXCSI_AID1_8197F)) +#define BIT_GET_R_WMAC_TXCSI_AID1_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) & BIT_MASK_R_WMAC_TXCSI_AID1_8197F) +#define BIT_SET_R_WMAC_TXCSI_AID1_8197F(x, v) (BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) | BIT_R_WMAC_TXCSI_AID1_8197F(v)) + + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F 0xffffffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_8197F (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8197F)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8197F(x, v) (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) | BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_TX_CSI_RPT_PARAM_BW20_8197F (TX CSI REPORT PARAMETER_BW20 REGISTER) */ + +#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F 16 +#define BIT_MASK_R_WMAC_BFINFO_20M_1_8197F 0xfff +#define BIT_R_WMAC_BFINFO_20M_1_8197F(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8197F) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) +#define BITS_R_WMAC_BFINFO_20M_1_8197F (BIT_MASK_R_WMAC_BFINFO_20M_1_8197F << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8197F)) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) & BIT_MASK_R_WMAC_BFINFO_20M_1_8197F) +#define BIT_SET_R_WMAC_BFINFO_20M_1_8197F(x, v) (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) | BIT_R_WMAC_BFINFO_20M_1_8197F(v)) + + +#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F 0 +#define BIT_MASK_R_WMAC_BFINFO_20M_0_8197F 0xfff +#define BIT_R_WMAC_BFINFO_20M_0_8197F(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8197F) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) +#define BITS_R_WMAC_BFINFO_20M_0_8197F (BIT_MASK_R_WMAC_BFINFO_20M_0_8197F << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8197F)) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) & BIT_MASK_R_WMAC_BFINFO_20M_0_8197F) +#define BIT_SET_R_WMAC_BFINFO_20M_0_8197F(x, v) (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) | BIT_R_WMAC_BFINFO_20M_0_8197F(v)) + + +/* 2 REG_TX_CSI_RPT_PARAM_BW40_8197F (TX CSI REPORT PARAMETER_BW40 REGISTER) */ + +#define BIT_SHIFT_WMAC_RESP_ANTCD_8197F 0 +#define BIT_MASK_WMAC_RESP_ANTCD_8197F 0xf +#define BIT_WMAC_RESP_ANTCD_8197F(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8197F) << BIT_SHIFT_WMAC_RESP_ANTCD_8197F) +#define BITS_WMAC_RESP_ANTCD_8197F (BIT_MASK_WMAC_RESP_ANTCD_8197F << BIT_SHIFT_WMAC_RESP_ANTCD_8197F) +#define BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8197F)) +#define BIT_GET_WMAC_RESP_ANTCD_8197F(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8197F) & BIT_MASK_WMAC_RESP_ANTCD_8197F) +#define BIT_SET_WMAC_RESP_ANTCD_8197F(x, v) (BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) | BIT_WMAC_RESP_ANTCD_8197F(v)) + + +/* 2 REG_TX_CSI_RPT_PARAM_BW80_8197F (TX CSI REPORT PARAMETER_BW80 REGISTER) */ + +/* 2 REG_BCN_PSR_RPT2_8197F (BEACON PARSER REPORT REGISTER2) */ + +#define BIT_SHIFT_DTIM_CNT2_8197F 24 +#define BIT_MASK_DTIM_CNT2_8197F 0xff +#define BIT_DTIM_CNT2_8197F(x) (((x) & BIT_MASK_DTIM_CNT2_8197F) << BIT_SHIFT_DTIM_CNT2_8197F) +#define BITS_DTIM_CNT2_8197F (BIT_MASK_DTIM_CNT2_8197F << BIT_SHIFT_DTIM_CNT2_8197F) +#define BIT_CLEAR_DTIM_CNT2_8197F(x) ((x) & (~BITS_DTIM_CNT2_8197F)) +#define BIT_GET_DTIM_CNT2_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8197F) & BIT_MASK_DTIM_CNT2_8197F) +#define BIT_SET_DTIM_CNT2_8197F(x, v) (BIT_CLEAR_DTIM_CNT2_8197F(x) | BIT_DTIM_CNT2_8197F(v)) + + +#define BIT_SHIFT_DTIM_PERIOD2_8197F 16 +#define BIT_MASK_DTIM_PERIOD2_8197F 0xff +#define BIT_DTIM_PERIOD2_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD2_8197F) << BIT_SHIFT_DTIM_PERIOD2_8197F) +#define BITS_DTIM_PERIOD2_8197F (BIT_MASK_DTIM_PERIOD2_8197F << BIT_SHIFT_DTIM_PERIOD2_8197F) +#define BIT_CLEAR_DTIM_PERIOD2_8197F(x) ((x) & (~BITS_DTIM_PERIOD2_8197F)) +#define BIT_GET_DTIM_PERIOD2_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8197F) & BIT_MASK_DTIM_PERIOD2_8197F) +#define BIT_SET_DTIM_PERIOD2_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD2_8197F(x) | BIT_DTIM_PERIOD2_8197F(v)) + +#define BIT_DTIM2_8197F BIT(15) +#define BIT_TIM2_8197F BIT(14) + +#define BIT_SHIFT_PS_AID_2_8197F 0 +#define BIT_MASK_PS_AID_2_8197F 0x7ff +#define BIT_PS_AID_2_8197F(x) (((x) & BIT_MASK_PS_AID_2_8197F) << BIT_SHIFT_PS_AID_2_8197F) +#define BITS_PS_AID_2_8197F (BIT_MASK_PS_AID_2_8197F << BIT_SHIFT_PS_AID_2_8197F) +#define BIT_CLEAR_PS_AID_2_8197F(x) ((x) & (~BITS_PS_AID_2_8197F)) +#define BIT_GET_PS_AID_2_8197F(x) (((x) >> BIT_SHIFT_PS_AID_2_8197F) & BIT_MASK_PS_AID_2_8197F) +#define BIT_SET_PS_AID_2_8197F(x, v) (BIT_CLEAR_PS_AID_2_8197F(x) | BIT_PS_AID_2_8197F(v)) + + +/* 2 REG_BCN_PSR_RPT3_8197F (BEACON PARSER REPORT REGISTER3) */ + +#define BIT_SHIFT_DTIM_CNT3_8197F 24 +#define BIT_MASK_DTIM_CNT3_8197F 0xff +#define BIT_DTIM_CNT3_8197F(x) (((x) & BIT_MASK_DTIM_CNT3_8197F) << BIT_SHIFT_DTIM_CNT3_8197F) +#define BITS_DTIM_CNT3_8197F (BIT_MASK_DTIM_CNT3_8197F << BIT_SHIFT_DTIM_CNT3_8197F) +#define BIT_CLEAR_DTIM_CNT3_8197F(x) ((x) & (~BITS_DTIM_CNT3_8197F)) +#define BIT_GET_DTIM_CNT3_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8197F) & BIT_MASK_DTIM_CNT3_8197F) +#define BIT_SET_DTIM_CNT3_8197F(x, v) (BIT_CLEAR_DTIM_CNT3_8197F(x) | BIT_DTIM_CNT3_8197F(v)) + + +#define BIT_SHIFT_DTIM_PERIOD3_8197F 16 +#define BIT_MASK_DTIM_PERIOD3_8197F 0xff +#define BIT_DTIM_PERIOD3_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD3_8197F) << BIT_SHIFT_DTIM_PERIOD3_8197F) +#define BITS_DTIM_PERIOD3_8197F (BIT_MASK_DTIM_PERIOD3_8197F << BIT_SHIFT_DTIM_PERIOD3_8197F) +#define BIT_CLEAR_DTIM_PERIOD3_8197F(x) ((x) & (~BITS_DTIM_PERIOD3_8197F)) +#define BIT_GET_DTIM_PERIOD3_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8197F) & BIT_MASK_DTIM_PERIOD3_8197F) +#define BIT_SET_DTIM_PERIOD3_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD3_8197F(x) | BIT_DTIM_PERIOD3_8197F(v)) + +#define BIT_DTIM3_8197F BIT(15) +#define BIT_TIM3_8197F BIT(14) + +#define BIT_SHIFT_PS_AID_3_8197F 0 +#define BIT_MASK_PS_AID_3_8197F 0x7ff +#define BIT_PS_AID_3_8197F(x) (((x) & BIT_MASK_PS_AID_3_8197F) << BIT_SHIFT_PS_AID_3_8197F) +#define BITS_PS_AID_3_8197F (BIT_MASK_PS_AID_3_8197F << BIT_SHIFT_PS_AID_3_8197F) +#define BIT_CLEAR_PS_AID_3_8197F(x) ((x) & (~BITS_PS_AID_3_8197F)) +#define BIT_GET_PS_AID_3_8197F(x) (((x) >> BIT_SHIFT_PS_AID_3_8197F) & BIT_MASK_PS_AID_3_8197F) +#define BIT_SET_PS_AID_3_8197F(x, v) (BIT_CLEAR_PS_AID_3_8197F(x) | BIT_PS_AID_3_8197F(v)) + + +/* 2 REG_BCN_PSR_RPT4_8197F (BEACON PARSER REPORT REGISTER4) */ + +#define BIT_SHIFT_DTIM_CNT4_8197F 24 +#define BIT_MASK_DTIM_CNT4_8197F 0xff +#define BIT_DTIM_CNT4_8197F(x) (((x) & BIT_MASK_DTIM_CNT4_8197F) << BIT_SHIFT_DTIM_CNT4_8197F) +#define BITS_DTIM_CNT4_8197F (BIT_MASK_DTIM_CNT4_8197F << BIT_SHIFT_DTIM_CNT4_8197F) +#define BIT_CLEAR_DTIM_CNT4_8197F(x) ((x) & (~BITS_DTIM_CNT4_8197F)) +#define BIT_GET_DTIM_CNT4_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8197F) & BIT_MASK_DTIM_CNT4_8197F) +#define BIT_SET_DTIM_CNT4_8197F(x, v) (BIT_CLEAR_DTIM_CNT4_8197F(x) | BIT_DTIM_CNT4_8197F(v)) + + +#define BIT_SHIFT_DTIM_PERIOD4_8197F 16 +#define BIT_MASK_DTIM_PERIOD4_8197F 0xff +#define BIT_DTIM_PERIOD4_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD4_8197F) << BIT_SHIFT_DTIM_PERIOD4_8197F) +#define BITS_DTIM_PERIOD4_8197F (BIT_MASK_DTIM_PERIOD4_8197F << BIT_SHIFT_DTIM_PERIOD4_8197F) +#define BIT_CLEAR_DTIM_PERIOD4_8197F(x) ((x) & (~BITS_DTIM_PERIOD4_8197F)) +#define BIT_GET_DTIM_PERIOD4_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8197F) & BIT_MASK_DTIM_PERIOD4_8197F) +#define BIT_SET_DTIM_PERIOD4_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD4_8197F(x) | BIT_DTIM_PERIOD4_8197F(v)) + +#define BIT_DTIM4_8197F BIT(15) +#define BIT_TIM4_8197F BIT(14) + +#define BIT_SHIFT_PS_AID_4_8197F 0 +#define BIT_MASK_PS_AID_4_8197F 0x7ff +#define BIT_PS_AID_4_8197F(x) (((x) & BIT_MASK_PS_AID_4_8197F) << BIT_SHIFT_PS_AID_4_8197F) +#define BITS_PS_AID_4_8197F (BIT_MASK_PS_AID_4_8197F << BIT_SHIFT_PS_AID_4_8197F) +#define BIT_CLEAR_PS_AID_4_8197F(x) ((x) & (~BITS_PS_AID_4_8197F)) +#define BIT_GET_PS_AID_4_8197F(x) (((x) >> BIT_SHIFT_PS_AID_4_8197F) & BIT_MASK_PS_AID_4_8197F) +#define BIT_SET_PS_AID_4_8197F(x, v) (BIT_CLEAR_PS_AID_4_8197F(x) | BIT_PS_AID_4_8197F(v)) + + +/* 2 REG_A1_ADDR_MASK_8197F (A1 ADDR MASK REGISTER) */ + +#define BIT_SHIFT_A1_ADDR_MASK_8197F 0 +#define BIT_MASK_A1_ADDR_MASK_8197F 0xffffffffL +#define BIT_A1_ADDR_MASK_8197F(x) (((x) & BIT_MASK_A1_ADDR_MASK_8197F) << BIT_SHIFT_A1_ADDR_MASK_8197F) +#define BITS_A1_ADDR_MASK_8197F (BIT_MASK_A1_ADDR_MASK_8197F << BIT_SHIFT_A1_ADDR_MASK_8197F) +#define BIT_CLEAR_A1_ADDR_MASK_8197F(x) ((x) & (~BITS_A1_ADDR_MASK_8197F)) +#define BIT_GET_A1_ADDR_MASK_8197F(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8197F) & BIT_MASK_A1_ADDR_MASK_8197F) +#define BIT_SET_A1_ADDR_MASK_8197F(x, v) (BIT_CLEAR_A1_ADDR_MASK_8197F(x) | BIT_A1_ADDR_MASK_8197F(v)) + + +/* 2 REG_MACID2_8197F (MAC ID2 REGISTER) */ + +#define BIT_SHIFT_MACID2_8197F 0 +#define BIT_MASK_MACID2_8197F 0xffffffffffffL +#define BIT_MACID2_8197F(x) (((x) & BIT_MASK_MACID2_8197F) << BIT_SHIFT_MACID2_8197F) +#define BITS_MACID2_8197F (BIT_MASK_MACID2_8197F << BIT_SHIFT_MACID2_8197F) +#define BIT_CLEAR_MACID2_8197F(x) ((x) & (~BITS_MACID2_8197F)) +#define BIT_GET_MACID2_8197F(x) (((x) >> BIT_SHIFT_MACID2_8197F) & BIT_MASK_MACID2_8197F) +#define BIT_SET_MACID2_8197F(x, v) (BIT_CLEAR_MACID2_8197F(x) | BIT_MACID2_8197F(v)) + + +/* 2 REG_BSSID2_8197F (BSSID2 REGISTER) */ + +#define BIT_SHIFT_BSSID2_8197F 0 +#define BIT_MASK_BSSID2_8197F 0xffffffffffffL +#define BIT_BSSID2_8197F(x) (((x) & BIT_MASK_BSSID2_8197F) << BIT_SHIFT_BSSID2_8197F) +#define BITS_BSSID2_8197F (BIT_MASK_BSSID2_8197F << BIT_SHIFT_BSSID2_8197F) +#define BIT_CLEAR_BSSID2_8197F(x) ((x) & (~BITS_BSSID2_8197F)) +#define BIT_GET_BSSID2_8197F(x) (((x) >> BIT_SHIFT_BSSID2_8197F) & BIT_MASK_BSSID2_8197F) +#define BIT_SET_BSSID2_8197F(x, v) (BIT_CLEAR_BSSID2_8197F(x) | BIT_BSSID2_8197F(v)) + + +/* 2 REG_MACID3_8197F (MAC ID3 REGISTER) */ + +#define BIT_SHIFT_MACID3_8197F 0 +#define BIT_MASK_MACID3_8197F 0xffffffffffffL +#define BIT_MACID3_8197F(x) (((x) & BIT_MASK_MACID3_8197F) << BIT_SHIFT_MACID3_8197F) +#define BITS_MACID3_8197F (BIT_MASK_MACID3_8197F << BIT_SHIFT_MACID3_8197F) +#define BIT_CLEAR_MACID3_8197F(x) ((x) & (~BITS_MACID3_8197F)) +#define BIT_GET_MACID3_8197F(x) (((x) >> BIT_SHIFT_MACID3_8197F) & BIT_MASK_MACID3_8197F) +#define BIT_SET_MACID3_8197F(x, v) (BIT_CLEAR_MACID3_8197F(x) | BIT_MACID3_8197F(v)) + + +/* 2 REG_BSSID3_8197F (BSSID3 REGISTER) */ + +#define BIT_SHIFT_BSSID3_8197F 0 +#define BIT_MASK_BSSID3_8197F 0xffffffffffffL +#define BIT_BSSID3_8197F(x) (((x) & BIT_MASK_BSSID3_8197F) << BIT_SHIFT_BSSID3_8197F) +#define BITS_BSSID3_8197F (BIT_MASK_BSSID3_8197F << BIT_SHIFT_BSSID3_8197F) +#define BIT_CLEAR_BSSID3_8197F(x) ((x) & (~BITS_BSSID3_8197F)) +#define BIT_GET_BSSID3_8197F(x) (((x) >> BIT_SHIFT_BSSID3_8197F) & BIT_MASK_BSSID3_8197F) +#define BIT_SET_BSSID3_8197F(x, v) (BIT_CLEAR_BSSID3_8197F(x) | BIT_BSSID3_8197F(v)) + + +/* 2 REG_MACID4_8197F (MAC ID4 REGISTER) */ + +#define BIT_SHIFT_MACID4_8197F 0 +#define BIT_MASK_MACID4_8197F 0xffffffffffffL +#define BIT_MACID4_8197F(x) (((x) & BIT_MASK_MACID4_8197F) << BIT_SHIFT_MACID4_8197F) +#define BITS_MACID4_8197F (BIT_MASK_MACID4_8197F << BIT_SHIFT_MACID4_8197F) +#define BIT_CLEAR_MACID4_8197F(x) ((x) & (~BITS_MACID4_8197F)) +#define BIT_GET_MACID4_8197F(x) (((x) >> BIT_SHIFT_MACID4_8197F) & BIT_MASK_MACID4_8197F) +#define BIT_SET_MACID4_8197F(x, v) (BIT_CLEAR_MACID4_8197F(x) | BIT_MACID4_8197F(v)) + + +/* 2 REG_BSSID4_8197F (BSSID4 REGISTER) */ + +#define BIT_SHIFT_BSSID4_8197F 0 +#define BIT_MASK_BSSID4_8197F 0xffffffffffffL +#define BIT_BSSID4_8197F(x) (((x) & BIT_MASK_BSSID4_8197F) << BIT_SHIFT_BSSID4_8197F) +#define BITS_BSSID4_8197F (BIT_MASK_BSSID4_8197F << BIT_SHIFT_BSSID4_8197F) +#define BIT_CLEAR_BSSID4_8197F(x) ((x) & (~BITS_BSSID4_8197F)) +#define BIT_GET_BSSID4_8197F(x) (((x) >> BIT_SHIFT_BSSID4_8197F) & BIT_MASK_BSSID4_8197F) +#define BIT_SET_BSSID4_8197F(x, v) (BIT_CLEAR_BSSID4_8197F(x) | BIT_BSSID4_8197F(v)) + + +/* 2 REG_NOA_REPORT_8197F */ + +/* 2 REG_PWRBIT_SETTING_8197F */ +#define BIT_CLI3_PWRBIT_OW_EN_8197F BIT(7) +#define BIT_CLI3_PWR_ST_8197F BIT(6) +#define BIT_CLI2_PWRBIT_OW_EN_8197F BIT(5) +#define BIT_CLI2_PWR_ST_8197F BIT(4) +#define BIT_CLI1_PWRBIT_OW_EN_8197F BIT(3) +#define BIT_CLI1_PWR_ST_8197F BIT(2) +#define BIT_CLI0_PWRBIT_OW_EN_8197F BIT(1) +#define BIT_CLI0_PWR_ST_8197F BIT(0) + +/* 2 REG_WMAC_MU_BF_OPTION_8197F */ +#define BIT_WMAC_RESP_NONSTA1_DIS_8197F BIT(7) +#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN_8197F BIT(6) + +#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F 4 +#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F 0x3 +#define BIT_WMAC_TXMU_ACKPOLICY_8197F(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) +#define BITS_WMAC_TXMU_ACKPOLICY_8197F (BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8197F)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8197F(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F) +#define BIT_SET_WMAC_TXMU_ACKPOLICY_8197F(x, v) (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) | BIT_WMAC_TXMU_ACKPOLICY_8197F(v)) + + +#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F 1 +#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F 0x7 +#define BIT_WMAC_MU_BFEE_PORT_SEL_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) +#define BITS_WMAC_MU_BFEE_PORT_SEL_8197F (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8197F)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) | BIT_WMAC_MU_BFEE_PORT_SEL_8197F(v)) + +#define BIT_WMAC_MU_BFEE_DIS_8197F BIT(0) + +/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8197F */ + +#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F 0 +#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F 0xff +#define BIT_WMAC_PAUSE_BB_CLR_TH_8197F(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) +#define BITS_WMAC_PAUSE_BB_CLR_TH_8197F (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8197F)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8197F(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8197F(x, v) (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) | BIT_WMAC_PAUSE_BB_CLR_TH_8197F(v)) + + +/* 2 REG_WMAC_MU_ARB_8197F */ +#define BIT_WMAC_ARB_HW_ADAPT_EN_8197F BIT(7) +#define BIT_WMAC_ARB_SW_EN_8197F BIT(6) + +#define BIT_SHIFT_WMAC_ARB_SW_STATE_8197F 0 +#define BIT_MASK_WMAC_ARB_SW_STATE_8197F 0x3f +#define BIT_WMAC_ARB_SW_STATE_8197F(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8197F) << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) +#define BITS_WMAC_ARB_SW_STATE_8197F (BIT_MASK_WMAC_ARB_SW_STATE_8197F << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) +#define BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) ((x) & (~BITS_WMAC_ARB_SW_STATE_8197F)) +#define BIT_GET_WMAC_ARB_SW_STATE_8197F(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) & BIT_MASK_WMAC_ARB_SW_STATE_8197F) +#define BIT_SET_WMAC_ARB_SW_STATE_8197F(x, v) (BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) | BIT_WMAC_ARB_SW_STATE_8197F(v)) + + +/* 2 REG_WMAC_MU_OPTION_8197F */ + +#define BIT_SHIFT_WMAC_MU_DBGSEL_8197F 5 +#define BIT_MASK_WMAC_MU_DBGSEL_8197F 0x3 +#define BIT_WMAC_MU_DBGSEL_8197F(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8197F) << BIT_SHIFT_WMAC_MU_DBGSEL_8197F) +#define BITS_WMAC_MU_DBGSEL_8197F (BIT_MASK_WMAC_MU_DBGSEL_8197F << BIT_SHIFT_WMAC_MU_DBGSEL_8197F) +#define BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8197F)) +#define BIT_GET_WMAC_MU_DBGSEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8197F) & BIT_MASK_WMAC_MU_DBGSEL_8197F) +#define BIT_SET_WMAC_MU_DBGSEL_8197F(x, v) (BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) | BIT_WMAC_MU_DBGSEL_8197F(v)) + + +#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F 0 +#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F 0x1f +#define BIT_WMAC_MU_CPRD_TIMEOUT_8197F(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) +#define BITS_WMAC_MU_CPRD_TIMEOUT_8197F (BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) +#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8197F)) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F) +#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8197F(x, v) (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) | BIT_WMAC_MU_CPRD_TIMEOUT_8197F(v)) + + +/* 2 REG_WMAC_MU_BF_CTL_8197F */ +#define BIT_WMAC_INVLD_BFPRT_CHK_8197F BIT(15) +#define BIT_WMAC_RETXBFRPTSEQ_UPD_8197F BIT(14) + +#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F 12 +#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F 0x3 +#define BIT_WMAC_MU_BFRPTSEG_SEL_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) +#define BITS_WMAC_MU_BFRPTSEG_SEL_8197F (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8197F)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) | BIT_WMAC_MU_BFRPTSEG_SEL_8197F(v)) + + +#define BIT_SHIFT_WMAC_MU_BF_MYAID_8197F 0 +#define BIT_MASK_WMAC_MU_BF_MYAID_8197F 0xfff +#define BIT_WMAC_MU_BF_MYAID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8197F) << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) +#define BITS_WMAC_MU_BF_MYAID_8197F (BIT_MASK_WMAC_MU_BF_MYAID_8197F << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) ((x) & (~BITS_WMAC_MU_BF_MYAID_8197F)) +#define BIT_GET_WMAC_MU_BF_MYAID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) & BIT_MASK_WMAC_MU_BF_MYAID_8197F) +#define BIT_SET_WMAC_MU_BF_MYAID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) | BIT_WMAC_MU_BF_MYAID_8197F(v)) + + +/* 2 REG_WMAC_MU_BFRPT_PARA_8197F */ + +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F 12 +#define BIT_MASK_BFRPT_PARA_USERID_SEL_8197F 0x7 +#define BIT_BFRPT_PARA_USERID_SEL_8197F(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8197F) << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) +#define BITS_BFRPT_PARA_USERID_SEL_8197F (BIT_MASK_BFRPT_PARA_USERID_SEL_8197F << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) ((x) & (~BITS_BFRPT_PARA_USERID_SEL_8197F)) +#define BIT_GET_BFRPT_PARA_USERID_SEL_8197F(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) & BIT_MASK_BFRPT_PARA_USERID_SEL_8197F) +#define BIT_SET_BFRPT_PARA_USERID_SEL_8197F(x, v) (BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) | BIT_BFRPT_PARA_USERID_SEL_8197F(v)) + + +#define BIT_SHIFT_BFRPT_PARA_8197F 0 +#define BIT_MASK_BFRPT_PARA_8197F 0xfff +#define BIT_BFRPT_PARA_8197F(x) (((x) & BIT_MASK_BFRPT_PARA_8197F) << BIT_SHIFT_BFRPT_PARA_8197F) +#define BITS_BFRPT_PARA_8197F (BIT_MASK_BFRPT_PARA_8197F << BIT_SHIFT_BFRPT_PARA_8197F) +#define BIT_CLEAR_BFRPT_PARA_8197F(x) ((x) & (~BITS_BFRPT_PARA_8197F)) +#define BIT_GET_BFRPT_PARA_8197F(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8197F) & BIT_MASK_BFRPT_PARA_8197F) +#define BIT_SET_BFRPT_PARA_8197F(x, v) (BIT_CLEAR_BFRPT_PARA_8197F(x) | BIT_BFRPT_PARA_8197F(v)) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F */ +#define BIT_STATUS_BFEE2_8197F BIT(10) +#define BIT_WMAC_MU_BFEE2_EN_8197F BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F 0 +#define BIT_MASK_WMAC_MU_BFEE2_AID_8197F 0x1ff +#define BIT_WMAC_MU_BFEE2_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) +#define BITS_WMAC_MU_BFEE2_AID_8197F (BIT_MASK_WMAC_MU_BFEE2_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE2_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE2_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) & BIT_MASK_WMAC_MU_BFEE2_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE2_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) | BIT_WMAC_MU_BFEE2_AID_8197F(v)) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F */ +#define BIT_STATUS_BFEE3_8197F BIT(10) +#define BIT_WMAC_MU_BFEE3_EN_8197F BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F 0 +#define BIT_MASK_WMAC_MU_BFEE3_AID_8197F 0x1ff +#define BIT_WMAC_MU_BFEE3_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) +#define BITS_WMAC_MU_BFEE3_AID_8197F (BIT_MASK_WMAC_MU_BFEE3_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE3_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE3_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) & BIT_MASK_WMAC_MU_BFEE3_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE3_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) | BIT_WMAC_MU_BFEE3_AID_8197F(v)) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F */ +#define BIT_STATUS_BFEE4_8197F BIT(10) +#define BIT_WMAC_MU_BFEE4_EN_8197F BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F 0 +#define BIT_MASK_WMAC_MU_BFEE4_AID_8197F 0x1ff +#define BIT_WMAC_MU_BFEE4_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) +#define BITS_WMAC_MU_BFEE4_AID_8197F (BIT_MASK_WMAC_MU_BFEE4_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE4_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE4_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) & BIT_MASK_WMAC_MU_BFEE4_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE4_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) | BIT_WMAC_MU_BFEE4_AID_8197F(v)) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F */ +#define BIT_STATUS_BFEE5_8197F BIT(10) +#define BIT_WMAC_MU_BFEE5_EN_8197F BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F 0 +#define BIT_MASK_WMAC_MU_BFEE5_AID_8197F 0x1ff +#define BIT_WMAC_MU_BFEE5_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) +#define BITS_WMAC_MU_BFEE5_AID_8197F (BIT_MASK_WMAC_MU_BFEE5_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE5_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE5_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) & BIT_MASK_WMAC_MU_BFEE5_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE5_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) | BIT_WMAC_MU_BFEE5_AID_8197F(v)) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F */ +#define BIT_STATUS_BFEE6_8197F BIT(10) +#define BIT_WMAC_MU_BFEE6_EN_8197F BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F 0 +#define BIT_MASK_WMAC_MU_BFEE6_AID_8197F 0x1ff +#define BIT_WMAC_MU_BFEE6_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) +#define BITS_WMAC_MU_BFEE6_AID_8197F (BIT_MASK_WMAC_MU_BFEE6_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE6_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE6_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) & BIT_MASK_WMAC_MU_BFEE6_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE6_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) | BIT_WMAC_MU_BFEE6_AID_8197F(v)) + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F */ +#define BIT_BIT_STATUS_BFEE4_8197F BIT(10) +#define BIT_WMAC_MU_BFEE7_EN_8197F BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F 0 +#define BIT_MASK_WMAC_MU_BFEE7_AID_8197F 0x1ff +#define BIT_WMAC_MU_BFEE7_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) +#define BITS_WMAC_MU_BFEE7_AID_8197F (BIT_MASK_WMAC_MU_BFEE7_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE7_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE7_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) & BIT_MASK_WMAC_MU_BFEE7_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE7_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) | BIT_WMAC_MU_BFEE7_AID_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_RST_ALL_COUNTER_8197F BIT(31) + +#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F 16 +#define BIT_MASK_ABORT_RX_VBON_COUNTER_8197F 0xff +#define BIT_ABORT_RX_VBON_COUNTER_8197F(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8197F) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) +#define BITS_ABORT_RX_VBON_COUNTER_8197F (BIT_MASK_ABORT_RX_VBON_COUNTER_8197F << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8197F)) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8197F(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) & BIT_MASK_ABORT_RX_VBON_COUNTER_8197F) +#define BIT_SET_ABORT_RX_VBON_COUNTER_8197F(x, v) (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) | BIT_ABORT_RX_VBON_COUNTER_8197F(v)) + + +#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F 8 +#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F 0xff +#define BIT_ABORT_RX_RDRDY_COUNTER_8197F(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) +#define BITS_ABORT_RX_RDRDY_COUNTER_8197F (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8197F)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8197F(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8197F(x, v) (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) | BIT_ABORT_RX_RDRDY_COUNTER_8197F(v)) + + +#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F 0 +#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F 0xff +#define BIT_VBON_EARLY_FALLING_COUNTER_8197F(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) +#define BITS_VBON_EARLY_FALLING_COUNTER_8197F (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8197F)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8197F(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8197F(x, v) (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) | BIT_VBON_EARLY_FALLING_COUNTER_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ +#define BIT_WMAC_PLCP_TRX_SEL_8197F BIT(31) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F 28 +#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F 0x7 +#define BIT_WMAC_PLCP_RDSIG_SEL_8197F(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) +#define BITS_WMAC_PLCP_RDSIG_SEL_8197F (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8197F)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8197F(x, v) (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) | BIT_WMAC_PLCP_RDSIG_SEL_8197F(v)) + + +#define BIT_SHIFT_WMAC_RATE_IDX_8197F 24 +#define BIT_MASK_WMAC_RATE_IDX_8197F 0xf +#define BIT_WMAC_RATE_IDX_8197F(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8197F) << BIT_SHIFT_WMAC_RATE_IDX_8197F) +#define BITS_WMAC_RATE_IDX_8197F (BIT_MASK_WMAC_RATE_IDX_8197F << BIT_SHIFT_WMAC_RATE_IDX_8197F) +#define BIT_CLEAR_WMAC_RATE_IDX_8197F(x) ((x) & (~BITS_WMAC_RATE_IDX_8197F)) +#define BIT_GET_WMAC_RATE_IDX_8197F(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8197F) & BIT_MASK_WMAC_RATE_IDX_8197F) +#define BIT_SET_WMAC_RATE_IDX_8197F(x, v) (BIT_CLEAR_WMAC_RATE_IDX_8197F(x) | BIT_WMAC_RATE_IDX_8197F(v)) + + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8197F 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8197F 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8197F(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8197F) << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) +#define BITS_WMAC_PLCP_RDSIG_8197F (BIT_MASK_WMAC_PLCP_RDSIG_8197F << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8197F)) +#define BIT_GET_WMAC_PLCP_RDSIG_8197F(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) & BIT_MASK_WMAC_PLCP_RDSIG_8197F) +#define BIT_SET_WMAC_PLCP_RDSIG_8197F(x, v) (BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) | BIT_WMAC_PLCP_RDSIG_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_TRANSMIT_ADDRSS_0_8197F (TA0 REGISTER) */ + +#define BIT_SHIFT_TA0_8197F 0 +#define BIT_MASK_TA0_8197F 0xffffffffffffL +#define BIT_TA0_8197F(x) (((x) & BIT_MASK_TA0_8197F) << BIT_SHIFT_TA0_8197F) +#define BITS_TA0_8197F (BIT_MASK_TA0_8197F << BIT_SHIFT_TA0_8197F) +#define BIT_CLEAR_TA0_8197F(x) ((x) & (~BITS_TA0_8197F)) +#define BIT_GET_TA0_8197F(x) (((x) >> BIT_SHIFT_TA0_8197F) & BIT_MASK_TA0_8197F) +#define BIT_SET_TA0_8197F(x, v) (BIT_CLEAR_TA0_8197F(x) | BIT_TA0_8197F(v)) + + +/* 2 REG_TRANSMIT_ADDRSS_1_8197F (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_8197F 0 +#define BIT_MASK_TA1_8197F 0xffffffffffffL +#define BIT_TA1_8197F(x) (((x) & BIT_MASK_TA1_8197F) << BIT_SHIFT_TA1_8197F) +#define BITS_TA1_8197F (BIT_MASK_TA1_8197F << BIT_SHIFT_TA1_8197F) +#define BIT_CLEAR_TA1_8197F(x) ((x) & (~BITS_TA1_8197F)) +#define BIT_GET_TA1_8197F(x) (((x) >> BIT_SHIFT_TA1_8197F) & BIT_MASK_TA1_8197F) +#define BIT_SET_TA1_8197F(x, v) (BIT_CLEAR_TA1_8197F(x) | BIT_TA1_8197F(v)) + + +/* 2 REG_TRANSMIT_ADDRSS_2_8197F (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_8197F 0 +#define BIT_MASK_TA2_8197F 0xffffffffffffL +#define BIT_TA2_8197F(x) (((x) & BIT_MASK_TA2_8197F) << BIT_SHIFT_TA2_8197F) +#define BITS_TA2_8197F (BIT_MASK_TA2_8197F << BIT_SHIFT_TA2_8197F) +#define BIT_CLEAR_TA2_8197F(x) ((x) & (~BITS_TA2_8197F)) +#define BIT_GET_TA2_8197F(x) (((x) >> BIT_SHIFT_TA2_8197F) & BIT_MASK_TA2_8197F) +#define BIT_SET_TA2_8197F(x, v) (BIT_CLEAR_TA2_8197F(x) | BIT_TA2_8197F(v)) + + +/* 2 REG_TRANSMIT_ADDRSS_3_8197F (TA3 REGISTER) */ + +#define BIT_SHIFT_TA3_8197F 0 +#define BIT_MASK_TA3_8197F 0xffffffffffffL +#define BIT_TA3_8197F(x) (((x) & BIT_MASK_TA3_8197F) << BIT_SHIFT_TA3_8197F) +#define BITS_TA3_8197F (BIT_MASK_TA3_8197F << BIT_SHIFT_TA3_8197F) +#define BIT_CLEAR_TA3_8197F(x) ((x) & (~BITS_TA3_8197F)) +#define BIT_GET_TA3_8197F(x) (((x) >> BIT_SHIFT_TA3_8197F) & BIT_MASK_TA3_8197F) +#define BIT_SET_TA3_8197F(x, v) (BIT_CLEAR_TA3_8197F(x) | BIT_TA3_8197F(v)) + + +/* 2 REG_TRANSMIT_ADDRSS_4_8197F (TA4 REGISTER) */ + +#define BIT_SHIFT_TA4_8197F 0 +#define BIT_MASK_TA4_8197F 0xffffffffffffL +#define BIT_TA4_8197F(x) (((x) & BIT_MASK_TA4_8197F) << BIT_SHIFT_TA4_8197F) +#define BITS_TA4_8197F (BIT_MASK_TA4_8197F << BIT_SHIFT_TA4_8197F) +#define BIT_CLEAR_TA4_8197F(x) ((x) & (~BITS_TA4_8197F)) +#define BIT_GET_TA4_8197F(x) (((x) >> BIT_SHIFT_TA4_8197F) & BIT_MASK_TA4_8197F) +#define BIT_SET_TA4_8197F(x, v) (BIT_CLEAR_TA4_8197F(x) | BIT_TA4_8197F(v)) + + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_MACID1_8197F */ + +#define BIT_SHIFT_MACID1_8197F 0 +#define BIT_MASK_MACID1_8197F 0xffffffffffffL +#define BIT_MACID1_8197F(x) (((x) & BIT_MASK_MACID1_8197F) << BIT_SHIFT_MACID1_8197F) +#define BITS_MACID1_8197F (BIT_MASK_MACID1_8197F << BIT_SHIFT_MACID1_8197F) +#define BIT_CLEAR_MACID1_8197F(x) ((x) & (~BITS_MACID1_8197F)) +#define BIT_GET_MACID1_8197F(x) (((x) >> BIT_SHIFT_MACID1_8197F) & BIT_MASK_MACID1_8197F) +#define BIT_SET_MACID1_8197F(x, v) (BIT_CLEAR_MACID1_8197F(x) | BIT_MACID1_8197F(v)) + + +/* 2 REG_BSSID1_8197F */ + +#define BIT_SHIFT_BSSID1_8197F 0 +#define BIT_MASK_BSSID1_8197F 0xffffffffffffL +#define BIT_BSSID1_8197F(x) (((x) & BIT_MASK_BSSID1_8197F) << BIT_SHIFT_BSSID1_8197F) +#define BITS_BSSID1_8197F (BIT_MASK_BSSID1_8197F << BIT_SHIFT_BSSID1_8197F) +#define BIT_CLEAR_BSSID1_8197F(x) ((x) & (~BITS_BSSID1_8197F)) +#define BIT_GET_BSSID1_8197F(x) (((x) >> BIT_SHIFT_BSSID1_8197F) & BIT_MASK_BSSID1_8197F) +#define BIT_SET_BSSID1_8197F(x, v) (BIT_CLEAR_BSSID1_8197F(x) | BIT_BSSID1_8197F(v)) + + +/* 2 REG_BCN_PSR_RPT1_8197F */ + +#define BIT_SHIFT_DTIM_CNT1_8197F 24 +#define BIT_MASK_DTIM_CNT1_8197F 0xff +#define BIT_DTIM_CNT1_8197F(x) (((x) & BIT_MASK_DTIM_CNT1_8197F) << BIT_SHIFT_DTIM_CNT1_8197F) +#define BITS_DTIM_CNT1_8197F (BIT_MASK_DTIM_CNT1_8197F << BIT_SHIFT_DTIM_CNT1_8197F) +#define BIT_CLEAR_DTIM_CNT1_8197F(x) ((x) & (~BITS_DTIM_CNT1_8197F)) +#define BIT_GET_DTIM_CNT1_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8197F) & BIT_MASK_DTIM_CNT1_8197F) +#define BIT_SET_DTIM_CNT1_8197F(x, v) (BIT_CLEAR_DTIM_CNT1_8197F(x) | BIT_DTIM_CNT1_8197F(v)) + + +#define BIT_SHIFT_DTIM_PERIOD1_8197F 16 +#define BIT_MASK_DTIM_PERIOD1_8197F 0xff +#define BIT_DTIM_PERIOD1_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD1_8197F) << BIT_SHIFT_DTIM_PERIOD1_8197F) +#define BITS_DTIM_PERIOD1_8197F (BIT_MASK_DTIM_PERIOD1_8197F << BIT_SHIFT_DTIM_PERIOD1_8197F) +#define BIT_CLEAR_DTIM_PERIOD1_8197F(x) ((x) & (~BITS_DTIM_PERIOD1_8197F)) +#define BIT_GET_DTIM_PERIOD1_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8197F) & BIT_MASK_DTIM_PERIOD1_8197F) +#define BIT_SET_DTIM_PERIOD1_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD1_8197F(x) | BIT_DTIM_PERIOD1_8197F(v)) + +#define BIT_DTIM1_8197F BIT(15) +#define BIT_TIM1_8197F BIT(14) + +#define BIT_SHIFT_PS_AID_1_8197F 0 +#define BIT_MASK_PS_AID_1_8197F 0x7ff +#define BIT_PS_AID_1_8197F(x) (((x) & BIT_MASK_PS_AID_1_8197F) << BIT_SHIFT_PS_AID_1_8197F) +#define BITS_PS_AID_1_8197F (BIT_MASK_PS_AID_1_8197F << BIT_SHIFT_PS_AID_1_8197F) +#define BIT_CLEAR_PS_AID_1_8197F(x) ((x) & (~BITS_PS_AID_1_8197F)) +#define BIT_GET_PS_AID_1_8197F(x) (((x) >> BIT_SHIFT_PS_AID_1_8197F) & BIT_MASK_PS_AID_1_8197F) +#define BIT_SET_PS_AID_1_8197F(x, v) (BIT_CLEAR_PS_AID_1_8197F(x) | BIT_PS_AID_1_8197F(v)) + + +/* 2 REG_ASSOCIATED_BFMEE_SEL_8197F */ +#define BIT_TXUSER_ID1_8197F BIT(25) + +#define BIT_SHIFT_AID1_8197F 16 +#define BIT_MASK_AID1_8197F 0x1ff +#define BIT_AID1_8197F(x) (((x) & BIT_MASK_AID1_8197F) << BIT_SHIFT_AID1_8197F) +#define BITS_AID1_8197F (BIT_MASK_AID1_8197F << BIT_SHIFT_AID1_8197F) +#define BIT_CLEAR_AID1_8197F(x) ((x) & (~BITS_AID1_8197F)) +#define BIT_GET_AID1_8197F(x) (((x) >> BIT_SHIFT_AID1_8197F) & BIT_MASK_AID1_8197F) +#define BIT_SET_AID1_8197F(x, v) (BIT_CLEAR_AID1_8197F(x) | BIT_AID1_8197F(v)) + +#define BIT_TXUSER_ID0_8197F BIT(9) + +#define BIT_SHIFT_AID0_8197F 0 +#define BIT_MASK_AID0_8197F 0x1ff +#define BIT_AID0_8197F(x) (((x) & BIT_MASK_AID0_8197F) << BIT_SHIFT_AID0_8197F) +#define BITS_AID0_8197F (BIT_MASK_AID0_8197F << BIT_SHIFT_AID0_8197F) +#define BIT_CLEAR_AID0_8197F(x) ((x) & (~BITS_AID0_8197F)) +#define BIT_GET_AID0_8197F(x) (((x) >> BIT_SHIFT_AID0_8197F) & BIT_MASK_AID0_8197F) +#define BIT_SET_AID0_8197F(x, v) (BIT_CLEAR_AID0_8197F(x) | BIT_AID0_8197F(v)) + + +/* 2 REG_SND_PTCL_CTRL_8197F */ + +#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F 24 +#define BIT_MASK_NDP_RX_STANDBY_TIMER_8197F 0xff +#define BIT_NDP_RX_STANDBY_TIMER_8197F(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8197F) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) +#define BITS_NDP_RX_STANDBY_TIMER_8197F (BIT_MASK_NDP_RX_STANDBY_TIMER_8197F << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8197F)) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8197F(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) & BIT_MASK_NDP_RX_STANDBY_TIMER_8197F) +#define BIT_SET_NDP_RX_STANDBY_TIMER_8197F(x, v) (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) | BIT_NDP_RX_STANDBY_TIMER_8197F(v)) + + +#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F 16 +#define BIT_MASK_CSI_RPT_OFFSET_HT_8197F 0xff +#define BIT_CSI_RPT_OFFSET_HT_8197F(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8197F) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) +#define BITS_CSI_RPT_OFFSET_HT_8197F (BIT_MASK_CSI_RPT_OFFSET_HT_8197F << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT_8197F)) +#define BIT_GET_CSI_RPT_OFFSET_HT_8197F(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) & BIT_MASK_CSI_RPT_OFFSET_HT_8197F) +#define BIT_SET_CSI_RPT_OFFSET_HT_8197F(x, v) (BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) | BIT_CSI_RPT_OFFSET_HT_8197F(v)) + + +#define BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F 8 +#define BIT_MASK_CSI_RPT_OFFSET_VHT_8197F 0xff +#define BIT_CSI_RPT_OFFSET_VHT_8197F(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_8197F) << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) +#define BITS_CSI_RPT_OFFSET_VHT_8197F (BIT_MASK_CSI_RPT_OFFSET_VHT_8197F << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) +#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT_8197F)) +#define BIT_GET_CSI_RPT_OFFSET_VHT_8197F(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) & BIT_MASK_CSI_RPT_OFFSET_VHT_8197F) +#define BIT_SET_CSI_RPT_OFFSET_VHT_8197F(x, v) (BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) | BIT_CSI_RPT_OFFSET_VHT_8197F(v)) + +#define BIT_R_WMAC_USE_NSTS_8197F BIT(7) +#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8197F BIT(6) +#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8197F BIT(5) +#define BIT_R_WMAC_BFPARAM_SEL_8197F BIT(4) +#define BIT_R_WMAC_CSISEQ_SEL_8197F BIT(3) +#define BIT_R_WMAC_CSI_WITHHTC_EN_8197F BIT(2) +#define BIT_R_WMAC_HT_NDPA_EN_8197F BIT(1) +#define BIT_R_WMAC_VHT_NDPA_EN_8197F BIT(0) + +/* 2 REG_RX_CSI_RPT_INFO_8197F */ + +/* 2 REG_NS_ARP_CTRL_8197F */ +#define BIT_R_WMAC_NSARP_RSPEN_8197F BIT(15) +#define BIT_R_WMAC_NSARP_RARP_8197F BIT(9) +#define BIT_R_WMAC_NSARP_RIPV6_8197F BIT(8) + +#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F 6 +#define BIT_MASK_R_WMAC_NSARP_MODEN_8197F 0x3 +#define BIT_R_WMAC_NSARP_MODEN_8197F(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8197F) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) +#define BITS_R_WMAC_NSARP_MODEN_8197F (BIT_MASK_R_WMAC_NSARP_MODEN_8197F << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) ((x) & (~BITS_R_WMAC_NSARP_MODEN_8197F)) +#define BIT_GET_R_WMAC_NSARP_MODEN_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) & BIT_MASK_R_WMAC_NSARP_MODEN_8197F) +#define BIT_SET_R_WMAC_NSARP_MODEN_8197F(x, v) (BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) | BIT_R_WMAC_NSARP_MODEN_8197F(v)) + + +#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F 4 +#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F 0x3 +#define BIT_R_WMAC_NSARP_RSPFTP_8197F(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) +#define BITS_R_WMAC_NSARP_RSPFTP_8197F (BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8197F)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F) +#define BIT_SET_R_WMAC_NSARP_RSPFTP_8197F(x, v) (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) | BIT_R_WMAC_NSARP_RSPFTP_8197F(v)) + + +#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F 0 +#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F 0xf +#define BIT_R_WMAC_NSARP_RSPSEC_8197F(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) +#define BITS_R_WMAC_NSARP_RSPSEC_8197F (BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8197F)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F) +#define BIT_SET_R_WMAC_NSARP_RSPSEC_8197F(x, v) (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) | BIT_R_WMAC_NSARP_RSPSEC_8197F(v)) + + +/* 2 REG_NS_ARP_INFO_8197F */ + +/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8197F */ + +/* 2 REG_BEAMFORMING_INFO_NSARP_8197F */ + +/* 2 REG_NOT_VALID_8197F */ + +/* 2 REG_RSVD_0X740_8197F */ + +/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8197F */ + +#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F 4 +#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F 0xf +#define BIT_R_WMAC_CTX_SUBTYPE_8197F(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) +#define BITS_R_WMAC_CTX_SUBTYPE_8197F (BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8197F)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F) +#define BIT_SET_R_WMAC_CTX_SUBTYPE_8197F(x, v) (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) | BIT_R_WMAC_CTX_SUBTYPE_8197F(v)) + + +#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F 0 +#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F 0xf +#define BIT_R_WMAC_RTX_SUBTYPE_8197F(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) +#define BITS_R_WMAC_RTX_SUBTYPE_8197F (BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8197F)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F) +#define BIT_SET_R_WMAC_RTX_SUBTYPE_8197F(x, v) (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) | BIT_R_WMAC_RTX_SUBTYPE_8197F(v)) + + +/* 2 REG_WMAC_SWAES_CFG_8197F */ + +/* 2 REG_BT_COEX_V2_8197F */ +#define BIT_GNT_BT_POLARITY_8197F BIT(12) +#define BIT_GNT_BT_BYPASS_PRIORITY_8197F BIT(8) + +#define BIT_SHIFT_TIMER_8197F 0 +#define BIT_MASK_TIMER_8197F 0xff +#define BIT_TIMER_8197F(x) (((x) & BIT_MASK_TIMER_8197F) << BIT_SHIFT_TIMER_8197F) +#define BITS_TIMER_8197F (BIT_MASK_TIMER_8197F << BIT_SHIFT_TIMER_8197F) +#define BIT_CLEAR_TIMER_8197F(x) ((x) & (~BITS_TIMER_8197F)) +#define BIT_GET_TIMER_8197F(x) (((x) >> BIT_SHIFT_TIMER_8197F) & BIT_MASK_TIMER_8197F) +#define BIT_SET_TIMER_8197F(x, v) (BIT_CLEAR_TIMER_8197F(x) | BIT_TIMER_8197F(v)) + + +/* 2 REG_BT_COEX_8197F */ +#define BIT_R_GNT_BT_RFC_SW_8197F BIT(12) +#define BIT_R_GNT_BT_RFC_SW_EN_8197F BIT(11) +#define BIT_R_GNT_BT_BB_SW_8197F BIT(10) +#define BIT_R_GNT_BT_BB_SW_EN_8197F BIT(9) +#define BIT_R_BT_CNT_THREN_8197F BIT(8) + +#define BIT_SHIFT_R_BT_CNT_THR_8197F 0 +#define BIT_MASK_R_BT_CNT_THR_8197F 0xff +#define BIT_R_BT_CNT_THR_8197F(x) (((x) & BIT_MASK_R_BT_CNT_THR_8197F) << BIT_SHIFT_R_BT_CNT_THR_8197F) +#define BITS_R_BT_CNT_THR_8197F (BIT_MASK_R_BT_CNT_THR_8197F << BIT_SHIFT_R_BT_CNT_THR_8197F) +#define BIT_CLEAR_R_BT_CNT_THR_8197F(x) ((x) & (~BITS_R_BT_CNT_THR_8197F)) +#define BIT_GET_R_BT_CNT_THR_8197F(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8197F) & BIT_MASK_R_BT_CNT_THR_8197F) +#define BIT_SET_R_BT_CNT_THR_8197F(x, v) (BIT_CLEAR_R_BT_CNT_THR_8197F(x) | BIT_R_BT_CNT_THR_8197F(v)) + + +/* 2 REG_WLAN_ACT_MASK_CTRL_8197F */ +#define BIT_WLRX_TER_BY_CTL_8197F BIT(43) +#define BIT_WLRX_TER_BY_AD_8197F BIT(42) +#define BIT_ANT_DIVERSITY_SEL_8197F BIT(41) +#define BIT_ANTSEL_FOR_BT_CTRL_EN_8197F BIT(40) +#define BIT_WLACT_LOW_GNTWL_EN_8197F BIT(34) +#define BIT_WLACT_HIGH_GNTBT_EN_8197F BIT(33) + +#define BIT_SHIFT_RXMYRTS_NAV_V1_8197F 8 +#define BIT_MASK_RXMYRTS_NAV_V1_8197F 0xff +#define BIT_RXMYRTS_NAV_V1_8197F(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8197F) << BIT_SHIFT_RXMYRTS_NAV_V1_8197F) +#define BITS_RXMYRTS_NAV_V1_8197F (BIT_MASK_RXMYRTS_NAV_V1_8197F << BIT_SHIFT_RXMYRTS_NAV_V1_8197F) +#define BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8197F)) +#define BIT_GET_RXMYRTS_NAV_V1_8197F(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8197F) & BIT_MASK_RXMYRTS_NAV_V1_8197F) +#define BIT_SET_RXMYRTS_NAV_V1_8197F(x, v) (BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) | BIT_RXMYRTS_NAV_V1_8197F(v)) + + +#define BIT_SHIFT_RTSRST_V1_8197F 0 +#define BIT_MASK_RTSRST_V1_8197F 0xff +#define BIT_RTSRST_V1_8197F(x) (((x) & BIT_MASK_RTSRST_V1_8197F) << BIT_SHIFT_RTSRST_V1_8197F) +#define BITS_RTSRST_V1_8197F (BIT_MASK_RTSRST_V1_8197F << BIT_SHIFT_RTSRST_V1_8197F) +#define BIT_CLEAR_RTSRST_V1_8197F(x) ((x) & (~BITS_RTSRST_V1_8197F)) +#define BIT_GET_RTSRST_V1_8197F(x) (((x) >> BIT_SHIFT_RTSRST_V1_8197F) & BIT_MASK_RTSRST_V1_8197F) +#define BIT_SET_RTSRST_V1_8197F(x, v) (BIT_CLEAR_RTSRST_V1_8197F(x) | BIT_RTSRST_V1_8197F(v)) + + +/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8197F */ + +#define BIT_SHIFT_BT_STAT_DELAY_8197F 12 +#define BIT_MASK_BT_STAT_DELAY_8197F 0xf +#define BIT_BT_STAT_DELAY_8197F(x) (((x) & BIT_MASK_BT_STAT_DELAY_8197F) << BIT_SHIFT_BT_STAT_DELAY_8197F) +#define BITS_BT_STAT_DELAY_8197F (BIT_MASK_BT_STAT_DELAY_8197F << BIT_SHIFT_BT_STAT_DELAY_8197F) +#define BIT_CLEAR_BT_STAT_DELAY_8197F(x) ((x) & (~BITS_BT_STAT_DELAY_8197F)) +#define BIT_GET_BT_STAT_DELAY_8197F(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8197F) & BIT_MASK_BT_STAT_DELAY_8197F) +#define BIT_SET_BT_STAT_DELAY_8197F(x, v) (BIT_CLEAR_BT_STAT_DELAY_8197F(x) | BIT_BT_STAT_DELAY_8197F(v)) + + +#define BIT_SHIFT_BT_TRX_INIT_DETECT_8197F 8 +#define BIT_MASK_BT_TRX_INIT_DETECT_8197F 0xf +#define BIT_BT_TRX_INIT_DETECT_8197F(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8197F) << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) +#define BITS_BT_TRX_INIT_DETECT_8197F (BIT_MASK_BT_TRX_INIT_DETECT_8197F << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) +#define BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) ((x) & (~BITS_BT_TRX_INIT_DETECT_8197F)) +#define BIT_GET_BT_TRX_INIT_DETECT_8197F(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) & BIT_MASK_BT_TRX_INIT_DETECT_8197F) +#define BIT_SET_BT_TRX_INIT_DETECT_8197F(x, v) (BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) | BIT_BT_TRX_INIT_DETECT_8197F(v)) + + +#define BIT_SHIFT_BT_PRI_DETECT_TO_8197F 4 +#define BIT_MASK_BT_PRI_DETECT_TO_8197F 0xf +#define BIT_BT_PRI_DETECT_TO_8197F(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8197F) << BIT_SHIFT_BT_PRI_DETECT_TO_8197F) +#define BITS_BT_PRI_DETECT_TO_8197F (BIT_MASK_BT_PRI_DETECT_TO_8197F << BIT_SHIFT_BT_PRI_DETECT_TO_8197F) +#define BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) ((x) & (~BITS_BT_PRI_DETECT_TO_8197F)) +#define BIT_GET_BT_PRI_DETECT_TO_8197F(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8197F) & BIT_MASK_BT_PRI_DETECT_TO_8197F) +#define BIT_SET_BT_PRI_DETECT_TO_8197F(x, v) (BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) | BIT_BT_PRI_DETECT_TO_8197F(v)) + +#define BIT_R_GRANTALL_WLMASK_8197F BIT(3) +#define BIT_STATIS_BT_EN_8197F BIT(2) +#define BIT_WL_ACT_MASK_ENABLE_8197F BIT(1) +#define BIT_ENHANCED_BT_8197F BIT(0) + +/* 2 REG_BT_ACT_STATISTICS_8197F */ + +#define BIT_SHIFT_STATIS_BT_LO_RX_8197F (48 & CPU_OPT_WIDTH) +#define BIT_MASK_STATIS_BT_LO_RX_8197F 0xffff +#define BIT_STATIS_BT_LO_RX_8197F(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_8197F) << BIT_SHIFT_STATIS_BT_LO_RX_8197F) +#define BITS_STATIS_BT_LO_RX_8197F (BIT_MASK_STATIS_BT_LO_RX_8197F << BIT_SHIFT_STATIS_BT_LO_RX_8197F) +#define BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) ((x) & (~BITS_STATIS_BT_LO_RX_8197F)) +#define BIT_GET_STATIS_BT_LO_RX_8197F(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8197F) & BIT_MASK_STATIS_BT_LO_RX_8197F) +#define BIT_SET_STATIS_BT_LO_RX_8197F(x, v) (BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) | BIT_STATIS_BT_LO_RX_8197F(v)) + + +#define BIT_SHIFT_STATIS_BT_LO_TX_8197F (32 & CPU_OPT_WIDTH) +#define BIT_MASK_STATIS_BT_LO_TX_8197F 0xffff +#define BIT_STATIS_BT_LO_TX_8197F(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_8197F) << BIT_SHIFT_STATIS_BT_LO_TX_8197F) +#define BITS_STATIS_BT_LO_TX_8197F (BIT_MASK_STATIS_BT_LO_TX_8197F << BIT_SHIFT_STATIS_BT_LO_TX_8197F) +#define BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) ((x) & (~BITS_STATIS_BT_LO_TX_8197F)) +#define BIT_GET_STATIS_BT_LO_TX_8197F(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8197F) & BIT_MASK_STATIS_BT_LO_TX_8197F) +#define BIT_SET_STATIS_BT_LO_TX_8197F(x, v) (BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) | BIT_STATIS_BT_LO_TX_8197F(v)) + + +#define BIT_SHIFT_STATIS_BT_HI_RX_8197F 16 +#define BIT_MASK_STATIS_BT_HI_RX_8197F 0xffff +#define BIT_STATIS_BT_HI_RX_8197F(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8197F) << BIT_SHIFT_STATIS_BT_HI_RX_8197F) +#define BITS_STATIS_BT_HI_RX_8197F (BIT_MASK_STATIS_BT_HI_RX_8197F << BIT_SHIFT_STATIS_BT_HI_RX_8197F) +#define BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) ((x) & (~BITS_STATIS_BT_HI_RX_8197F)) +#define BIT_GET_STATIS_BT_HI_RX_8197F(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8197F) & BIT_MASK_STATIS_BT_HI_RX_8197F) +#define BIT_SET_STATIS_BT_HI_RX_8197F(x, v) (BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) | BIT_STATIS_BT_HI_RX_8197F(v)) + + +#define BIT_SHIFT_STATIS_BT_HI_TX_8197F 0 +#define BIT_MASK_STATIS_BT_HI_TX_8197F 0xffff +#define BIT_STATIS_BT_HI_TX_8197F(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8197F) << BIT_SHIFT_STATIS_BT_HI_TX_8197F) +#define BITS_STATIS_BT_HI_TX_8197F (BIT_MASK_STATIS_BT_HI_TX_8197F << BIT_SHIFT_STATIS_BT_HI_TX_8197F) +#define BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) ((x) & (~BITS_STATIS_BT_HI_TX_8197F)) +#define BIT_GET_STATIS_BT_HI_TX_8197F(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8197F) & BIT_MASK_STATIS_BT_HI_TX_8197F) +#define BIT_SET_STATIS_BT_HI_TX_8197F(x, v) (BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) | BIT_STATIS_BT_HI_TX_8197F(v)) + + +/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8197F */ + +#define BIT_SHIFT_R_BT_CMD_RPT_8197F 16 +#define BIT_MASK_R_BT_CMD_RPT_8197F 0xffff +#define BIT_R_BT_CMD_RPT_8197F(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8197F) << BIT_SHIFT_R_BT_CMD_RPT_8197F) +#define BITS_R_BT_CMD_RPT_8197F (BIT_MASK_R_BT_CMD_RPT_8197F << BIT_SHIFT_R_BT_CMD_RPT_8197F) +#define BIT_CLEAR_R_BT_CMD_RPT_8197F(x) ((x) & (~BITS_R_BT_CMD_RPT_8197F)) +#define BIT_GET_R_BT_CMD_RPT_8197F(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8197F) & BIT_MASK_R_BT_CMD_RPT_8197F) +#define BIT_SET_R_BT_CMD_RPT_8197F(x, v) (BIT_CLEAR_R_BT_CMD_RPT_8197F(x) | BIT_R_BT_CMD_RPT_8197F(v)) + + +#define BIT_SHIFT_R_RPT_FROM_BT_8197F 8 +#define BIT_MASK_R_RPT_FROM_BT_8197F 0xff +#define BIT_R_RPT_FROM_BT_8197F(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8197F) << BIT_SHIFT_R_RPT_FROM_BT_8197F) +#define BITS_R_RPT_FROM_BT_8197F (BIT_MASK_R_RPT_FROM_BT_8197F << BIT_SHIFT_R_RPT_FROM_BT_8197F) +#define BIT_CLEAR_R_RPT_FROM_BT_8197F(x) ((x) & (~BITS_R_RPT_FROM_BT_8197F)) +#define BIT_GET_R_RPT_FROM_BT_8197F(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8197F) & BIT_MASK_R_RPT_FROM_BT_8197F) +#define BIT_SET_R_RPT_FROM_BT_8197F(x, v) (BIT_CLEAR_R_RPT_FROM_BT_8197F(x) | BIT_R_RPT_FROM_BT_8197F(v)) + + +#define BIT_SHIFT_BT_HID_ISR_SET_8197F 6 +#define BIT_MASK_BT_HID_ISR_SET_8197F 0x3 +#define BIT_BT_HID_ISR_SET_8197F(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8197F) << BIT_SHIFT_BT_HID_ISR_SET_8197F) +#define BITS_BT_HID_ISR_SET_8197F (BIT_MASK_BT_HID_ISR_SET_8197F << BIT_SHIFT_BT_HID_ISR_SET_8197F) +#define BIT_CLEAR_BT_HID_ISR_SET_8197F(x) ((x) & (~BITS_BT_HID_ISR_SET_8197F)) +#define BIT_GET_BT_HID_ISR_SET_8197F(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8197F) & BIT_MASK_BT_HID_ISR_SET_8197F) +#define BIT_SET_BT_HID_ISR_SET_8197F(x, v) (BIT_CLEAR_BT_HID_ISR_SET_8197F(x) | BIT_BT_HID_ISR_SET_8197F(v)) + +#define BIT_TDMA_BT_START_NOTIFY_8197F BIT(5) +#define BIT_ENABLE_TDMA_FW_MODE_8197F BIT(4) +#define BIT_ENABLE_PTA_TDMA_MODE_8197F BIT(3) +#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8197F BIT(2) +#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8197F BIT(1) +#define BIT_RTK_BT_ENABLE_8197F BIT(0) + +/* 2 REG_BT_STATUS_REPORT_REGISTER_8197F */ + +#define BIT_SHIFT_BT_PROFILE_8197F 24 +#define BIT_MASK_BT_PROFILE_8197F 0xff +#define BIT_BT_PROFILE_8197F(x) (((x) & BIT_MASK_BT_PROFILE_8197F) << BIT_SHIFT_BT_PROFILE_8197F) +#define BITS_BT_PROFILE_8197F (BIT_MASK_BT_PROFILE_8197F << BIT_SHIFT_BT_PROFILE_8197F) +#define BIT_CLEAR_BT_PROFILE_8197F(x) ((x) & (~BITS_BT_PROFILE_8197F)) +#define BIT_GET_BT_PROFILE_8197F(x) (((x) >> BIT_SHIFT_BT_PROFILE_8197F) & BIT_MASK_BT_PROFILE_8197F) +#define BIT_SET_BT_PROFILE_8197F(x, v) (BIT_CLEAR_BT_PROFILE_8197F(x) | BIT_BT_PROFILE_8197F(v)) + + +#define BIT_SHIFT_BT_POWER_8197F 16 +#define BIT_MASK_BT_POWER_8197F 0xff +#define BIT_BT_POWER_8197F(x) (((x) & BIT_MASK_BT_POWER_8197F) << BIT_SHIFT_BT_POWER_8197F) +#define BITS_BT_POWER_8197F (BIT_MASK_BT_POWER_8197F << BIT_SHIFT_BT_POWER_8197F) +#define BIT_CLEAR_BT_POWER_8197F(x) ((x) & (~BITS_BT_POWER_8197F)) +#define BIT_GET_BT_POWER_8197F(x) (((x) >> BIT_SHIFT_BT_POWER_8197F) & BIT_MASK_BT_POWER_8197F) +#define BIT_SET_BT_POWER_8197F(x, v) (BIT_CLEAR_BT_POWER_8197F(x) | BIT_BT_POWER_8197F(v)) + + +#define BIT_SHIFT_BT_PREDECT_STATUS_8197F 8 +#define BIT_MASK_BT_PREDECT_STATUS_8197F 0xff +#define BIT_BT_PREDECT_STATUS_8197F(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8197F) << BIT_SHIFT_BT_PREDECT_STATUS_8197F) +#define BITS_BT_PREDECT_STATUS_8197F (BIT_MASK_BT_PREDECT_STATUS_8197F << BIT_SHIFT_BT_PREDECT_STATUS_8197F) +#define BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) ((x) & (~BITS_BT_PREDECT_STATUS_8197F)) +#define BIT_GET_BT_PREDECT_STATUS_8197F(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8197F) & BIT_MASK_BT_PREDECT_STATUS_8197F) +#define BIT_SET_BT_PREDECT_STATUS_8197F(x, v) (BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) | BIT_BT_PREDECT_STATUS_8197F(v)) + + +#define BIT_SHIFT_BT_CMD_INFO_8197F 0 +#define BIT_MASK_BT_CMD_INFO_8197F 0xff +#define BIT_BT_CMD_INFO_8197F(x) (((x) & BIT_MASK_BT_CMD_INFO_8197F) << BIT_SHIFT_BT_CMD_INFO_8197F) +#define BITS_BT_CMD_INFO_8197F (BIT_MASK_BT_CMD_INFO_8197F << BIT_SHIFT_BT_CMD_INFO_8197F) +#define BIT_CLEAR_BT_CMD_INFO_8197F(x) ((x) & (~BITS_BT_CMD_INFO_8197F)) +#define BIT_GET_BT_CMD_INFO_8197F(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8197F) & BIT_MASK_BT_CMD_INFO_8197F) +#define BIT_SET_BT_CMD_INFO_8197F(x, v) (BIT_CLEAR_BT_CMD_INFO_8197F(x) | BIT_BT_CMD_INFO_8197F(v)) + + +/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8197F */ +#define BIT_EN_MAC_NULL_PKT_NOTIFY_8197F BIT(31) +#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8197F BIT(30) +#define BIT_EN_BT_STSTUS_RPT_8197F BIT(29) +#define BIT_EN_BT_POWER_8197F BIT(28) +#define BIT_EN_BT_CHANNEL_8197F BIT(27) +#define BIT_EN_BT_SLOT_CHANGE_8197F BIT(26) +#define BIT_EN_BT_PROFILE_OR_HID_8197F BIT(25) +#define BIT_WLAN_RPT_NOTIFY_8197F BIT(24) + +#define BIT_SHIFT_WLAN_RPT_DATA_8197F 16 +#define BIT_MASK_WLAN_RPT_DATA_8197F 0xff +#define BIT_WLAN_RPT_DATA_8197F(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8197F) << BIT_SHIFT_WLAN_RPT_DATA_8197F) +#define BITS_WLAN_RPT_DATA_8197F (BIT_MASK_WLAN_RPT_DATA_8197F << BIT_SHIFT_WLAN_RPT_DATA_8197F) +#define BIT_CLEAR_WLAN_RPT_DATA_8197F(x) ((x) & (~BITS_WLAN_RPT_DATA_8197F)) +#define BIT_GET_WLAN_RPT_DATA_8197F(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8197F) & BIT_MASK_WLAN_RPT_DATA_8197F) +#define BIT_SET_WLAN_RPT_DATA_8197F(x, v) (BIT_CLEAR_WLAN_RPT_DATA_8197F(x) | BIT_WLAN_RPT_DATA_8197F(v)) + + +#define BIT_SHIFT_CMD_ID_8197F 8 +#define BIT_MASK_CMD_ID_8197F 0xff +#define BIT_CMD_ID_8197F(x) (((x) & BIT_MASK_CMD_ID_8197F) << BIT_SHIFT_CMD_ID_8197F) +#define BITS_CMD_ID_8197F (BIT_MASK_CMD_ID_8197F << BIT_SHIFT_CMD_ID_8197F) +#define BIT_CLEAR_CMD_ID_8197F(x) ((x) & (~BITS_CMD_ID_8197F)) +#define BIT_GET_CMD_ID_8197F(x) (((x) >> BIT_SHIFT_CMD_ID_8197F) & BIT_MASK_CMD_ID_8197F) +#define BIT_SET_CMD_ID_8197F(x, v) (BIT_CLEAR_CMD_ID_8197F(x) | BIT_CMD_ID_8197F(v)) + + +#define BIT_SHIFT_BT_DATA_8197F 0 +#define BIT_MASK_BT_DATA_8197F 0xff +#define BIT_BT_DATA_8197F(x) (((x) & BIT_MASK_BT_DATA_8197F) << BIT_SHIFT_BT_DATA_8197F) +#define BITS_BT_DATA_8197F (BIT_MASK_BT_DATA_8197F << BIT_SHIFT_BT_DATA_8197F) +#define BIT_CLEAR_BT_DATA_8197F(x) ((x) & (~BITS_BT_DATA_8197F)) +#define BIT_GET_BT_DATA_8197F(x) (((x) >> BIT_SHIFT_BT_DATA_8197F) & BIT_MASK_BT_DATA_8197F) +#define BIT_SET_BT_DATA_8197F(x, v) (BIT_CLEAR_BT_DATA_8197F(x) | BIT_BT_DATA_8197F(v)) + + +/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F */ + +#define BIT_SHIFT_WLAN_RPT_TO_8197F 0 +#define BIT_MASK_WLAN_RPT_TO_8197F 0xff +#define BIT_WLAN_RPT_TO_8197F(x) (((x) & BIT_MASK_WLAN_RPT_TO_8197F) << BIT_SHIFT_WLAN_RPT_TO_8197F) +#define BITS_WLAN_RPT_TO_8197F (BIT_MASK_WLAN_RPT_TO_8197F << BIT_SHIFT_WLAN_RPT_TO_8197F) +#define BIT_CLEAR_WLAN_RPT_TO_8197F(x) ((x) & (~BITS_WLAN_RPT_TO_8197F)) +#define BIT_GET_WLAN_RPT_TO_8197F(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8197F) & BIT_MASK_WLAN_RPT_TO_8197F) +#define BIT_SET_WLAN_RPT_TO_8197F(x, v) (BIT_CLEAR_WLAN_RPT_TO_8197F(x) | BIT_WLAN_RPT_TO_8197F(v)) + + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F */ + +#define BIT_SHIFT_ISOLATION_CHK_8197F 1 +#define BIT_MASK_ISOLATION_CHK_8197F 0x7fffffffffffffffffffL +#define BIT_ISOLATION_CHK_8197F(x) (((x) & BIT_MASK_ISOLATION_CHK_8197F) << BIT_SHIFT_ISOLATION_CHK_8197F) +#define BITS_ISOLATION_CHK_8197F (BIT_MASK_ISOLATION_CHK_8197F << BIT_SHIFT_ISOLATION_CHK_8197F) +#define BIT_CLEAR_ISOLATION_CHK_8197F(x) ((x) & (~BITS_ISOLATION_CHK_8197F)) +#define BIT_GET_ISOLATION_CHK_8197F(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_8197F) & BIT_MASK_ISOLATION_CHK_8197F) +#define BIT_SET_ISOLATION_CHK_8197F(x, v) (BIT_CLEAR_ISOLATION_CHK_8197F(x) | BIT_ISOLATION_CHK_8197F(v)) + +#define BIT_ISOLATION_EN_8197F BIT(0) + +/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8197F */ +#define BIT_BT_HID_ISR_8197F BIT(7) +#define BIT_BT_QUERY_ISR_8197F BIT(6) +#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8197F BIT(5) +#define BIT_WLAN_RPT_ISR_8197F BIT(4) +#define BIT_BT_POWER_ISR_8197F BIT(3) +#define BIT_BT_CHANNEL_ISR_8197F BIT(2) +#define BIT_BT_SLOT_CHANGE_ISR_8197F BIT(1) +#define BIT_BT_PROFILE_ISR_8197F BIT(0) + +/* 2 REG_BT_TDMA_TIME_REGISTER_8197F */ + +#define BIT_SHIFT_BT_TIME_8197F 6 +#define BIT_MASK_BT_TIME_8197F 0x3ffffff +#define BIT_BT_TIME_8197F(x) (((x) & BIT_MASK_BT_TIME_8197F) << BIT_SHIFT_BT_TIME_8197F) +#define BITS_BT_TIME_8197F (BIT_MASK_BT_TIME_8197F << BIT_SHIFT_BT_TIME_8197F) +#define BIT_CLEAR_BT_TIME_8197F(x) ((x) & (~BITS_BT_TIME_8197F)) +#define BIT_GET_BT_TIME_8197F(x) (((x) >> BIT_SHIFT_BT_TIME_8197F) & BIT_MASK_BT_TIME_8197F) +#define BIT_SET_BT_TIME_8197F(x, v) (BIT_CLEAR_BT_TIME_8197F(x) | BIT_BT_TIME_8197F(v)) + + +#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F 0 +#define BIT_MASK_BT_RPT_SAMPLE_RATE_8197F 0x3f +#define BIT_BT_RPT_SAMPLE_RATE_8197F(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8197F) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) +#define BITS_BT_RPT_SAMPLE_RATE_8197F (BIT_MASK_BT_RPT_SAMPLE_RATE_8197F << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8197F)) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8197F(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) & BIT_MASK_BT_RPT_SAMPLE_RATE_8197F) +#define BIT_SET_BT_RPT_SAMPLE_RATE_8197F(x, v) (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) | BIT_BT_RPT_SAMPLE_RATE_8197F(v)) + + +/* 2 REG_BT_ACT_REGISTER_8197F */ + +#define BIT_SHIFT_BT_EISR_EN_8197F 16 +#define BIT_MASK_BT_EISR_EN_8197F 0xff +#define BIT_BT_EISR_EN_8197F(x) (((x) & BIT_MASK_BT_EISR_EN_8197F) << BIT_SHIFT_BT_EISR_EN_8197F) +#define BITS_BT_EISR_EN_8197F (BIT_MASK_BT_EISR_EN_8197F << BIT_SHIFT_BT_EISR_EN_8197F) +#define BIT_CLEAR_BT_EISR_EN_8197F(x) ((x) & (~BITS_BT_EISR_EN_8197F)) +#define BIT_GET_BT_EISR_EN_8197F(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8197F) & BIT_MASK_BT_EISR_EN_8197F) +#define BIT_SET_BT_EISR_EN_8197F(x, v) (BIT_CLEAR_BT_EISR_EN_8197F(x) | BIT_BT_EISR_EN_8197F(v)) + +#define BIT_BT_ACT_FALLING_ISR_8197F BIT(10) +#define BIT_BT_ACT_RISING_ISR_8197F BIT(9) +#define BIT_TDMA_TO_ISR_8197F BIT(8) + +#define BIT_SHIFT_BT_CH_8197F 0 +#define BIT_MASK_BT_CH_8197F 0xff +#define BIT_BT_CH_8197F(x) (((x) & BIT_MASK_BT_CH_8197F) << BIT_SHIFT_BT_CH_8197F) +#define BITS_BT_CH_8197F (BIT_MASK_BT_CH_8197F << BIT_SHIFT_BT_CH_8197F) +#define BIT_CLEAR_BT_CH_8197F(x) ((x) & (~BITS_BT_CH_8197F)) +#define BIT_GET_BT_CH_8197F(x) (((x) >> BIT_SHIFT_BT_CH_8197F) & BIT_MASK_BT_CH_8197F) +#define BIT_SET_BT_CH_8197F(x, v) (BIT_CLEAR_BT_CH_8197F(x) | BIT_BT_CH_8197F(v)) + + +/* 2 REG_OBFF_CTRL_BASIC_8197F */ +#define BIT_OBFF_EN_V1_8197F BIT(31) + +#define BIT_SHIFT_OBFF_STATE_V1_8197F 28 +#define BIT_MASK_OBFF_STATE_V1_8197F 0x3 +#define BIT_OBFF_STATE_V1_8197F(x) (((x) & BIT_MASK_OBFF_STATE_V1_8197F) << BIT_SHIFT_OBFF_STATE_V1_8197F) +#define BITS_OBFF_STATE_V1_8197F (BIT_MASK_OBFF_STATE_V1_8197F << BIT_SHIFT_OBFF_STATE_V1_8197F) +#define BIT_CLEAR_OBFF_STATE_V1_8197F(x) ((x) & (~BITS_OBFF_STATE_V1_8197F)) +#define BIT_GET_OBFF_STATE_V1_8197F(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8197F) & BIT_MASK_OBFF_STATE_V1_8197F) +#define BIT_SET_OBFF_STATE_V1_8197F(x, v) (BIT_CLEAR_OBFF_STATE_V1_8197F(x) | BIT_OBFF_STATE_V1_8197F(v)) + +#define BIT_OBFF_ACT_RXDMA_EN_8197F BIT(27) +#define BIT_OBFF_BLOCK_INT_EN_8197F BIT(26) +#define BIT_OBFF_AUTOACT_EN_8197F BIT(25) +#define BIT_OBFF_AUTOIDLE_EN_8197F BIT(24) + +#define BIT_SHIFT_WAKE_MAX_PLS_8197F 20 +#define BIT_MASK_WAKE_MAX_PLS_8197F 0x7 +#define BIT_WAKE_MAX_PLS_8197F(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8197F) << BIT_SHIFT_WAKE_MAX_PLS_8197F) +#define BITS_WAKE_MAX_PLS_8197F (BIT_MASK_WAKE_MAX_PLS_8197F << BIT_SHIFT_WAKE_MAX_PLS_8197F) +#define BIT_CLEAR_WAKE_MAX_PLS_8197F(x) ((x) & (~BITS_WAKE_MAX_PLS_8197F)) +#define BIT_GET_WAKE_MAX_PLS_8197F(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8197F) & BIT_MASK_WAKE_MAX_PLS_8197F) +#define BIT_SET_WAKE_MAX_PLS_8197F(x, v) (BIT_CLEAR_WAKE_MAX_PLS_8197F(x) | BIT_WAKE_MAX_PLS_8197F(v)) + + +#define BIT_SHIFT_WAKE_MIN_PLS_8197F 16 +#define BIT_MASK_WAKE_MIN_PLS_8197F 0x7 +#define BIT_WAKE_MIN_PLS_8197F(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8197F) << BIT_SHIFT_WAKE_MIN_PLS_8197F) +#define BITS_WAKE_MIN_PLS_8197F (BIT_MASK_WAKE_MIN_PLS_8197F << BIT_SHIFT_WAKE_MIN_PLS_8197F) +#define BIT_CLEAR_WAKE_MIN_PLS_8197F(x) ((x) & (~BITS_WAKE_MIN_PLS_8197F)) +#define BIT_GET_WAKE_MIN_PLS_8197F(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8197F) & BIT_MASK_WAKE_MIN_PLS_8197F) +#define BIT_SET_WAKE_MIN_PLS_8197F(x, v) (BIT_CLEAR_WAKE_MIN_PLS_8197F(x) | BIT_WAKE_MIN_PLS_8197F(v)) + + +#define BIT_SHIFT_WAKE_MAX_F2F_8197F 12 +#define BIT_MASK_WAKE_MAX_F2F_8197F 0x7 +#define BIT_WAKE_MAX_F2F_8197F(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8197F) << BIT_SHIFT_WAKE_MAX_F2F_8197F) +#define BITS_WAKE_MAX_F2F_8197F (BIT_MASK_WAKE_MAX_F2F_8197F << BIT_SHIFT_WAKE_MAX_F2F_8197F) +#define BIT_CLEAR_WAKE_MAX_F2F_8197F(x) ((x) & (~BITS_WAKE_MAX_F2F_8197F)) +#define BIT_GET_WAKE_MAX_F2F_8197F(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8197F) & BIT_MASK_WAKE_MAX_F2F_8197F) +#define BIT_SET_WAKE_MAX_F2F_8197F(x, v) (BIT_CLEAR_WAKE_MAX_F2F_8197F(x) | BIT_WAKE_MAX_F2F_8197F(v)) + + +#define BIT_SHIFT_WAKE_MIN_F2F_8197F 8 +#define BIT_MASK_WAKE_MIN_F2F_8197F 0x7 +#define BIT_WAKE_MIN_F2F_8197F(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8197F) << BIT_SHIFT_WAKE_MIN_F2F_8197F) +#define BITS_WAKE_MIN_F2F_8197F (BIT_MASK_WAKE_MIN_F2F_8197F << BIT_SHIFT_WAKE_MIN_F2F_8197F) +#define BIT_CLEAR_WAKE_MIN_F2F_8197F(x) ((x) & (~BITS_WAKE_MIN_F2F_8197F)) +#define BIT_GET_WAKE_MIN_F2F_8197F(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8197F) & BIT_MASK_WAKE_MIN_F2F_8197F) +#define BIT_SET_WAKE_MIN_F2F_8197F(x, v) (BIT_CLEAR_WAKE_MIN_F2F_8197F(x) | BIT_WAKE_MIN_F2F_8197F(v)) + +#define BIT_APP_CPU_ACT_V1_8197F BIT(3) +#define BIT_APP_OBFF_V1_8197F BIT(2) +#define BIT_APP_IDLE_V1_8197F BIT(1) +#define BIT_APP_INIT_V1_8197F BIT(0) + +/* 2 REG_OBFF_CTRL2_TIMER_8197F */ + +#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F 24 +#define BIT_MASK_RX_HIGH_TIMER_IDX_8197F 0x7 +#define BIT_RX_HIGH_TIMER_IDX_8197F(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8197F) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) +#define BITS_RX_HIGH_TIMER_IDX_8197F (BIT_MASK_RX_HIGH_TIMER_IDX_8197F << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) ((x) & (~BITS_RX_HIGH_TIMER_IDX_8197F)) +#define BIT_GET_RX_HIGH_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) & BIT_MASK_RX_HIGH_TIMER_IDX_8197F) +#define BIT_SET_RX_HIGH_TIMER_IDX_8197F(x, v) (BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) | BIT_RX_HIGH_TIMER_IDX_8197F(v)) + + +#define BIT_SHIFT_RX_MED_TIMER_IDX_8197F 16 +#define BIT_MASK_RX_MED_TIMER_IDX_8197F 0x7 +#define BIT_RX_MED_TIMER_IDX_8197F(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8197F) << BIT_SHIFT_RX_MED_TIMER_IDX_8197F) +#define BITS_RX_MED_TIMER_IDX_8197F (BIT_MASK_RX_MED_TIMER_IDX_8197F << BIT_SHIFT_RX_MED_TIMER_IDX_8197F) +#define BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) ((x) & (~BITS_RX_MED_TIMER_IDX_8197F)) +#define BIT_GET_RX_MED_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8197F) & BIT_MASK_RX_MED_TIMER_IDX_8197F) +#define BIT_SET_RX_MED_TIMER_IDX_8197F(x, v) (BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) | BIT_RX_MED_TIMER_IDX_8197F(v)) + + +#define BIT_SHIFT_RX_LOW_TIMER_IDX_8197F 8 +#define BIT_MASK_RX_LOW_TIMER_IDX_8197F 0x7 +#define BIT_RX_LOW_TIMER_IDX_8197F(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8197F) << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) +#define BITS_RX_LOW_TIMER_IDX_8197F (BIT_MASK_RX_LOW_TIMER_IDX_8197F << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) +#define BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) ((x) & (~BITS_RX_LOW_TIMER_IDX_8197F)) +#define BIT_GET_RX_LOW_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) & BIT_MASK_RX_LOW_TIMER_IDX_8197F) +#define BIT_SET_RX_LOW_TIMER_IDX_8197F(x, v) (BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) | BIT_RX_LOW_TIMER_IDX_8197F(v)) + + +#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F 0 +#define BIT_MASK_OBFF_INT_TIMER_IDX_8197F 0x7 +#define BIT_OBFF_INT_TIMER_IDX_8197F(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8197F) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) +#define BITS_OBFF_INT_TIMER_IDX_8197F (BIT_MASK_OBFF_INT_TIMER_IDX_8197F << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) ((x) & (~BITS_OBFF_INT_TIMER_IDX_8197F)) +#define BIT_GET_OBFF_INT_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) & BIT_MASK_OBFF_INT_TIMER_IDX_8197F) +#define BIT_SET_OBFF_INT_TIMER_IDX_8197F(x, v) (BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) | BIT_OBFF_INT_TIMER_IDX_8197F(v)) + + +/* 2 REG_LTR_CTRL_BASIC_8197F */ +#define BIT_LTR_EN_V1_8197F BIT(31) +#define BIT_LTR_HW_EN_V1_8197F BIT(30) +#define BIT_LRT_ACT_CTS_EN_8197F BIT(29) +#define BIT_LTR_ACT_RXPKT_EN_8197F BIT(28) +#define BIT_LTR_ACT_RXDMA_EN_8197F BIT(27) +#define BIT_LTR_IDLE_NO_SNOOP_8197F BIT(26) +#define BIT_SPDUP_MGTPKT_8197F BIT(25) +#define BIT_RX_AGG_EN_8197F BIT(24) +#define BIT_APP_LTR_ACT_8197F BIT(23) +#define BIT_APP_LTR_IDLE_8197F BIT(22) + +#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F 20 +#define BIT_MASK_HIGH_RATE_TRIG_SEL_8197F 0x3 +#define BIT_HIGH_RATE_TRIG_SEL_8197F(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8197F) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) +#define BITS_HIGH_RATE_TRIG_SEL_8197F (BIT_MASK_HIGH_RATE_TRIG_SEL_8197F << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8197F)) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8197F(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) & BIT_MASK_HIGH_RATE_TRIG_SEL_8197F) +#define BIT_SET_HIGH_RATE_TRIG_SEL_8197F(x, v) (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) | BIT_HIGH_RATE_TRIG_SEL_8197F(v)) + + +#define BIT_SHIFT_MED_RATE_TRIG_SEL_8197F 18 +#define BIT_MASK_MED_RATE_TRIG_SEL_8197F 0x3 +#define BIT_MED_RATE_TRIG_SEL_8197F(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8197F) << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) +#define BITS_MED_RATE_TRIG_SEL_8197F (BIT_MASK_MED_RATE_TRIG_SEL_8197F << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) +#define BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) ((x) & (~BITS_MED_RATE_TRIG_SEL_8197F)) +#define BIT_GET_MED_RATE_TRIG_SEL_8197F(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) & BIT_MASK_MED_RATE_TRIG_SEL_8197F) +#define BIT_SET_MED_RATE_TRIG_SEL_8197F(x, v) (BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) | BIT_MED_RATE_TRIG_SEL_8197F(v)) + + +#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F 16 +#define BIT_MASK_LOW_RATE_TRIG_SEL_8197F 0x3 +#define BIT_LOW_RATE_TRIG_SEL_8197F(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8197F) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) +#define BITS_LOW_RATE_TRIG_SEL_8197F (BIT_MASK_LOW_RATE_TRIG_SEL_8197F << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) ((x) & (~BITS_LOW_RATE_TRIG_SEL_8197F)) +#define BIT_GET_LOW_RATE_TRIG_SEL_8197F(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) & BIT_MASK_LOW_RATE_TRIG_SEL_8197F) +#define BIT_SET_LOW_RATE_TRIG_SEL_8197F(x, v) (BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) | BIT_LOW_RATE_TRIG_SEL_8197F(v)) + + +#define BIT_SHIFT_HIGH_RATE_BD_IDX_8197F 8 +#define BIT_MASK_HIGH_RATE_BD_IDX_8197F 0x7f +#define BIT_HIGH_RATE_BD_IDX_8197F(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8197F) << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) +#define BITS_HIGH_RATE_BD_IDX_8197F (BIT_MASK_HIGH_RATE_BD_IDX_8197F << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) +#define BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) ((x) & (~BITS_HIGH_RATE_BD_IDX_8197F)) +#define BIT_GET_HIGH_RATE_BD_IDX_8197F(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) & BIT_MASK_HIGH_RATE_BD_IDX_8197F) +#define BIT_SET_HIGH_RATE_BD_IDX_8197F(x, v) (BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) | BIT_HIGH_RATE_BD_IDX_8197F(v)) + + +#define BIT_SHIFT_LOW_RATE_BD_IDX_8197F 0 +#define BIT_MASK_LOW_RATE_BD_IDX_8197F 0x7f +#define BIT_LOW_RATE_BD_IDX_8197F(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8197F) << BIT_SHIFT_LOW_RATE_BD_IDX_8197F) +#define BITS_LOW_RATE_BD_IDX_8197F (BIT_MASK_LOW_RATE_BD_IDX_8197F << BIT_SHIFT_LOW_RATE_BD_IDX_8197F) +#define BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8197F)) +#define BIT_GET_LOW_RATE_BD_IDX_8197F(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8197F) & BIT_MASK_LOW_RATE_BD_IDX_8197F) +#define BIT_SET_LOW_RATE_BD_IDX_8197F(x, v) (BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) | BIT_LOW_RATE_BD_IDX_8197F(v)) + + +/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8197F */ + +#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F 24 +#define BIT_MASK_RX_EMPTY_TIMER_IDX_8197F 0x7 +#define BIT_RX_EMPTY_TIMER_IDX_8197F(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8197F) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) +#define BITS_RX_EMPTY_TIMER_IDX_8197F (BIT_MASK_RX_EMPTY_TIMER_IDX_8197F << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8197F)) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) & BIT_MASK_RX_EMPTY_TIMER_IDX_8197F) +#define BIT_SET_RX_EMPTY_TIMER_IDX_8197F(x, v) (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) | BIT_RX_EMPTY_TIMER_IDX_8197F(v)) + + +#define BIT_SHIFT_RX_AFULL_TH_IDX_8197F 20 +#define BIT_MASK_RX_AFULL_TH_IDX_8197F 0x7 +#define BIT_RX_AFULL_TH_IDX_8197F(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8197F) << BIT_SHIFT_RX_AFULL_TH_IDX_8197F) +#define BITS_RX_AFULL_TH_IDX_8197F (BIT_MASK_RX_AFULL_TH_IDX_8197F << BIT_SHIFT_RX_AFULL_TH_IDX_8197F) +#define BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8197F)) +#define BIT_GET_RX_AFULL_TH_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8197F) & BIT_MASK_RX_AFULL_TH_IDX_8197F) +#define BIT_SET_RX_AFULL_TH_IDX_8197F(x, v) (BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) | BIT_RX_AFULL_TH_IDX_8197F(v)) + + +#define BIT_SHIFT_RX_HIGH_TH_IDX_8197F 16 +#define BIT_MASK_RX_HIGH_TH_IDX_8197F 0x7 +#define BIT_RX_HIGH_TH_IDX_8197F(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8197F) << BIT_SHIFT_RX_HIGH_TH_IDX_8197F) +#define BITS_RX_HIGH_TH_IDX_8197F (BIT_MASK_RX_HIGH_TH_IDX_8197F << BIT_SHIFT_RX_HIGH_TH_IDX_8197F) +#define BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8197F)) +#define BIT_GET_RX_HIGH_TH_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8197F) & BIT_MASK_RX_HIGH_TH_IDX_8197F) +#define BIT_SET_RX_HIGH_TH_IDX_8197F(x, v) (BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) | BIT_RX_HIGH_TH_IDX_8197F(v)) + + +#define BIT_SHIFT_RX_MED_TH_IDX_8197F 12 +#define BIT_MASK_RX_MED_TH_IDX_8197F 0x7 +#define BIT_RX_MED_TH_IDX_8197F(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8197F) << BIT_SHIFT_RX_MED_TH_IDX_8197F) +#define BITS_RX_MED_TH_IDX_8197F (BIT_MASK_RX_MED_TH_IDX_8197F << BIT_SHIFT_RX_MED_TH_IDX_8197F) +#define BIT_CLEAR_RX_MED_TH_IDX_8197F(x) ((x) & (~BITS_RX_MED_TH_IDX_8197F)) +#define BIT_GET_RX_MED_TH_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8197F) & BIT_MASK_RX_MED_TH_IDX_8197F) +#define BIT_SET_RX_MED_TH_IDX_8197F(x, v) (BIT_CLEAR_RX_MED_TH_IDX_8197F(x) | BIT_RX_MED_TH_IDX_8197F(v)) + + +#define BIT_SHIFT_RX_LOW_TH_IDX_8197F 8 +#define BIT_MASK_RX_LOW_TH_IDX_8197F 0x7 +#define BIT_RX_LOW_TH_IDX_8197F(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8197F) << BIT_SHIFT_RX_LOW_TH_IDX_8197F) +#define BITS_RX_LOW_TH_IDX_8197F (BIT_MASK_RX_LOW_TH_IDX_8197F << BIT_SHIFT_RX_LOW_TH_IDX_8197F) +#define BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) ((x) & (~BITS_RX_LOW_TH_IDX_8197F)) +#define BIT_GET_RX_LOW_TH_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8197F) & BIT_MASK_RX_LOW_TH_IDX_8197F) +#define BIT_SET_RX_LOW_TH_IDX_8197F(x, v) (BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) | BIT_RX_LOW_TH_IDX_8197F(v)) + + +#define BIT_SHIFT_LTR_SPACE_IDX_8197F 4 +#define BIT_MASK_LTR_SPACE_IDX_8197F 0x3 +#define BIT_LTR_SPACE_IDX_8197F(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8197F) << BIT_SHIFT_LTR_SPACE_IDX_8197F) +#define BITS_LTR_SPACE_IDX_8197F (BIT_MASK_LTR_SPACE_IDX_8197F << BIT_SHIFT_LTR_SPACE_IDX_8197F) +#define BIT_CLEAR_LTR_SPACE_IDX_8197F(x) ((x) & (~BITS_LTR_SPACE_IDX_8197F)) +#define BIT_GET_LTR_SPACE_IDX_8197F(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8197F) & BIT_MASK_LTR_SPACE_IDX_8197F) +#define BIT_SET_LTR_SPACE_IDX_8197F(x, v) (BIT_CLEAR_LTR_SPACE_IDX_8197F(x) | BIT_LTR_SPACE_IDX_8197F(v)) + + +#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F 0 +#define BIT_MASK_LTR_IDLE_TIMER_IDX_8197F 0x7 +#define BIT_LTR_IDLE_TIMER_IDX_8197F(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8197F) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) +#define BITS_LTR_IDLE_TIMER_IDX_8197F (BIT_MASK_LTR_IDLE_TIMER_IDX_8197F << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8197F)) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) & BIT_MASK_LTR_IDLE_TIMER_IDX_8197F) +#define BIT_SET_LTR_IDLE_TIMER_IDX_8197F(x, v) (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) | BIT_LTR_IDLE_TIMER_IDX_8197F(v)) + + +/* 2 REG_LTR_IDLE_LATENCY_V1_8197F */ + +#define BIT_SHIFT_LTR_IDLE_L_8197F 0 +#define BIT_MASK_LTR_IDLE_L_8197F 0xffffffffL +#define BIT_LTR_IDLE_L_8197F(x) (((x) & BIT_MASK_LTR_IDLE_L_8197F) << BIT_SHIFT_LTR_IDLE_L_8197F) +#define BITS_LTR_IDLE_L_8197F (BIT_MASK_LTR_IDLE_L_8197F << BIT_SHIFT_LTR_IDLE_L_8197F) +#define BIT_CLEAR_LTR_IDLE_L_8197F(x) ((x) & (~BITS_LTR_IDLE_L_8197F)) +#define BIT_GET_LTR_IDLE_L_8197F(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8197F) & BIT_MASK_LTR_IDLE_L_8197F) +#define BIT_SET_LTR_IDLE_L_8197F(x, v) (BIT_CLEAR_LTR_IDLE_L_8197F(x) | BIT_LTR_IDLE_L_8197F(v)) + + +/* 2 REG_LTR_ACTIVE_LATENCY_V1_8197F */ + +#define BIT_SHIFT_LTR_ACT_L_8197F 0 +#define BIT_MASK_LTR_ACT_L_8197F 0xffffffffL +#define BIT_LTR_ACT_L_8197F(x) (((x) & BIT_MASK_LTR_ACT_L_8197F) << BIT_SHIFT_LTR_ACT_L_8197F) +#define BITS_LTR_ACT_L_8197F (BIT_MASK_LTR_ACT_L_8197F << BIT_SHIFT_LTR_ACT_L_8197F) +#define BIT_CLEAR_LTR_ACT_L_8197F(x) ((x) & (~BITS_LTR_ACT_L_8197F)) +#define BIT_GET_LTR_ACT_L_8197F(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8197F) & BIT_MASK_LTR_ACT_L_8197F) +#define BIT_SET_LTR_ACT_L_8197F(x, v) (BIT_CLEAR_LTR_ACT_L_8197F(x) | BIT_LTR_ACT_L_8197F(v)) + + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F */ +#define BIT_APPEND_MACID_IN_RESP_EN_8197F BIT(50) +#define BIT_ADDR2_MATCH_EN_8197F BIT(49) +#define BIT_ANTTRN_EN_8197F BIT(48) + +#define BIT_SHIFT_TRAIN_STA_ADDR_8197F 0 +#define BIT_MASK_TRAIN_STA_ADDR_8197F 0xffffffffffffL +#define BIT_TRAIN_STA_ADDR_8197F(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_8197F) << BIT_SHIFT_TRAIN_STA_ADDR_8197F) +#define BITS_TRAIN_STA_ADDR_8197F (BIT_MASK_TRAIN_STA_ADDR_8197F << BIT_SHIFT_TRAIN_STA_ADDR_8197F) +#define BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) ((x) & (~BITS_TRAIN_STA_ADDR_8197F)) +#define BIT_GET_TRAIN_STA_ADDR_8197F(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8197F) & BIT_MASK_TRAIN_STA_ADDR_8197F) +#define BIT_SET_TRAIN_STA_ADDR_8197F(x, v) (BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) | BIT_TRAIN_STA_ADDR_8197F(v)) + + +/* 2 REG_RSVD_0X7B4_8197F */ + +/* 2 REG_WMAC_PKTCNT_RWD_8197F */ + +#define BIT_SHIFT_PKTCNT_BSSIDMAP_8197F 4 +#define BIT_MASK_PKTCNT_BSSIDMAP_8197F 0xf +#define BIT_PKTCNT_BSSIDMAP_8197F(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8197F) << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) +#define BITS_PKTCNT_BSSIDMAP_8197F (BIT_MASK_PKTCNT_BSSIDMAP_8197F << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) +#define BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8197F)) +#define BIT_GET_PKTCNT_BSSIDMAP_8197F(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) & BIT_MASK_PKTCNT_BSSIDMAP_8197F) +#define BIT_SET_PKTCNT_BSSIDMAP_8197F(x, v) (BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) | BIT_PKTCNT_BSSIDMAP_8197F(v)) + +#define BIT_PKTCNT_CNTRST_8197F BIT(1) +#define BIT_PKTCNT_CNTEN_8197F BIT(0) + +/* 2 REG_WMAC_PKTCNT_CTRL_8197F */ +#define BIT_WMAC_PKTCNT_TRST_8197F BIT(9) +#define BIT_WMAC_PKTCNT_FEN_8197F BIT(8) + +#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F 0 +#define BIT_MASK_WMAC_PKTCNT_CFGAD_8197F 0xff +#define BIT_WMAC_PKTCNT_CFGAD_8197F(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8197F) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) +#define BITS_WMAC_PKTCNT_CFGAD_8197F (BIT_MASK_WMAC_PKTCNT_CFGAD_8197F << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) +#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8197F)) +#define BIT_GET_WMAC_PKTCNT_CFGAD_8197F(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) & BIT_MASK_WMAC_PKTCNT_CFGAD_8197F) +#define BIT_SET_WMAC_PKTCNT_CFGAD_8197F(x, v) (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) | BIT_WMAC_PKTCNT_CFGAD_8197F(v)) + + +/* 2 REG_IQ_DUMP_8197F */ + +#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F (64 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F 0xffffffffL +#define BIT_R_WMAC_MATCH_REF_MAC_8197F(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) +#define BITS_R_WMAC_MATCH_REF_MAC_8197F (BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8197F)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_8197F(x, v) (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) | BIT_R_WMAC_MATCH_REF_MAC_8197F(v)) + + +#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F (32 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_MASK_LA_MAC_8197F 0xffffffffL +#define BIT_R_WMAC_MASK_LA_MAC_8197F(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8197F) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) +#define BITS_R_WMAC_MASK_LA_MAC_8197F (BIT_MASK_R_WMAC_MASK_LA_MAC_8197F << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC_8197F)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) & BIT_MASK_R_WMAC_MASK_LA_MAC_8197F) +#define BIT_SET_R_WMAC_MASK_LA_MAC_8197F(x, v) (BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) | BIT_R_WMAC_MASK_LA_MAC_8197F(v)) + + +#define BIT_SHIFT_DUMP_OK_ADDR_8197F 16 +#define BIT_MASK_DUMP_OK_ADDR_8197F 0xffff +#define BIT_DUMP_OK_ADDR_8197F(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8197F) << BIT_SHIFT_DUMP_OK_ADDR_8197F) +#define BITS_DUMP_OK_ADDR_8197F (BIT_MASK_DUMP_OK_ADDR_8197F << BIT_SHIFT_DUMP_OK_ADDR_8197F) +#define BIT_CLEAR_DUMP_OK_ADDR_8197F(x) ((x) & (~BITS_DUMP_OK_ADDR_8197F)) +#define BIT_GET_DUMP_OK_ADDR_8197F(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8197F) & BIT_MASK_DUMP_OK_ADDR_8197F) +#define BIT_SET_DUMP_OK_ADDR_8197F(x, v) (BIT_CLEAR_DUMP_OK_ADDR_8197F(x) | BIT_DUMP_OK_ADDR_8197F(v)) + + +#define BIT_SHIFT_R_TRIG_TIME_SEL_8197F 8 +#define BIT_MASK_R_TRIG_TIME_SEL_8197F 0x7f +#define BIT_R_TRIG_TIME_SEL_8197F(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8197F) << BIT_SHIFT_R_TRIG_TIME_SEL_8197F) +#define BITS_R_TRIG_TIME_SEL_8197F (BIT_MASK_R_TRIG_TIME_SEL_8197F << BIT_SHIFT_R_TRIG_TIME_SEL_8197F) +#define BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8197F)) +#define BIT_GET_R_TRIG_TIME_SEL_8197F(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8197F) & BIT_MASK_R_TRIG_TIME_SEL_8197F) +#define BIT_SET_R_TRIG_TIME_SEL_8197F(x, v) (BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) | BIT_R_TRIG_TIME_SEL_8197F(v)) + + +#define BIT_SHIFT_R_MAC_TRIG_SEL_8197F 6 +#define BIT_MASK_R_MAC_TRIG_SEL_8197F 0x3 +#define BIT_R_MAC_TRIG_SEL_8197F(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8197F) << BIT_SHIFT_R_MAC_TRIG_SEL_8197F) +#define BITS_R_MAC_TRIG_SEL_8197F (BIT_MASK_R_MAC_TRIG_SEL_8197F << BIT_SHIFT_R_MAC_TRIG_SEL_8197F) +#define BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8197F)) +#define BIT_GET_R_MAC_TRIG_SEL_8197F(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8197F) & BIT_MASK_R_MAC_TRIG_SEL_8197F) +#define BIT_SET_R_MAC_TRIG_SEL_8197F(x, v) (BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) | BIT_R_MAC_TRIG_SEL_8197F(v)) + +#define BIT_MAC_TRIG_REG_8197F BIT(5) + +#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F 3 +#define BIT_MASK_R_LEVEL_PULSE_SEL_8197F 0x3 +#define BIT_R_LEVEL_PULSE_SEL_8197F(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8197F) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) +#define BITS_R_LEVEL_PULSE_SEL_8197F (BIT_MASK_R_LEVEL_PULSE_SEL_8197F << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) ((x) & (~BITS_R_LEVEL_PULSE_SEL_8197F)) +#define BIT_GET_R_LEVEL_PULSE_SEL_8197F(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) & BIT_MASK_R_LEVEL_PULSE_SEL_8197F) +#define BIT_SET_R_LEVEL_PULSE_SEL_8197F(x, v) (BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) | BIT_R_LEVEL_PULSE_SEL_8197F(v)) + +#define BIT_EN_LA_MAC_8197F BIT(2) +#define BIT_R_EN_IQDUMP_8197F BIT(1) +#define BIT_R_IQDATA_DUMP_8197F BIT(0) + +/* 2 REG_WMAC_FTM_CTL_8197F */ +#define BIT_RXFTM_TXACK_SC_8197F BIT(6) +#define BIT_RXFTM_TXACK_BW_8197F BIT(5) +#define BIT_RXFTM_EN_8197F BIT(3) +#define BIT_RXFTMREQ_BYDRV_8197F BIT(2) +#define BIT_RXFTMREQ_EN_8197F BIT(1) +#define BIT_FTM_EN_8197F BIT(0) + +/* 2 REG_IQ_DUMP_EXT_8197F */ + +#define BIT_SHIFT_R_TIME_UNIT_SEL_8197F 0 +#define BIT_MASK_R_TIME_UNIT_SEL_8197F 0x7 +#define BIT_R_TIME_UNIT_SEL_8197F(x) (((x) & BIT_MASK_R_TIME_UNIT_SEL_8197F) << BIT_SHIFT_R_TIME_UNIT_SEL_8197F) +#define BITS_R_TIME_UNIT_SEL_8197F (BIT_MASK_R_TIME_UNIT_SEL_8197F << BIT_SHIFT_R_TIME_UNIT_SEL_8197F) +#define BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) ((x) & (~BITS_R_TIME_UNIT_SEL_8197F)) +#define BIT_GET_R_TIME_UNIT_SEL_8197F(x) (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL_8197F) & BIT_MASK_R_TIME_UNIT_SEL_8197F) +#define BIT_SET_R_TIME_UNIT_SEL_8197F(x, v) (BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) | BIT_R_TIME_UNIT_SEL_8197F(v)) + + +/* 2 REG_OFDM_CCK_LEN_MASK_8197F */ + +#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F (64 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_RX_FIL_LEN_8197F 0xffff +#define BIT_R_WMAC_RX_FIL_LEN_8197F(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8197F) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) +#define BITS_R_WMAC_RX_FIL_LEN_8197F (BIT_MASK_R_WMAC_RX_FIL_LEN_8197F << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) ((x) & (~BITS_R_WMAC_RX_FIL_LEN_8197F)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) & BIT_MASK_R_WMAC_RX_FIL_LEN_8197F) +#define BIT_SET_R_WMAC_RX_FIL_LEN_8197F(x, v) (BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) | BIT_R_WMAC_RX_FIL_LEN_8197F(v)) + + +#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F (56 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F 0xff +#define BIT_R_WMAC_RXFIFO_FULL_TH_8197F(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) +#define BITS_R_WMAC_RXFIFO_FULL_TH_8197F (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8197F)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8197F(x, v) (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) | BIT_R_WMAC_RXFIFO_FULL_TH_8197F(v)) + +#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8197F BIT(55) +#define BIT_R_WMAC_RXRST_DLY_8197F BIT(54) +#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_8197F BIT(53) +#define BIT_R_WMAC_SRCH_TXRPT_UA1_8197F BIT(52) +#define BIT_R_WMAC_SRCH_TXRPT_TYPE_8197F BIT(51) +#define BIT_R_WMAC_NDP_RST_8197F BIT(50) +#define BIT_R_WMAC_POWINT_EN_8197F BIT(49) +#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_8197F BIT(48) +#define BIT_R_WMAC_SRCH_TXRPT_MID_8197F BIT(47) +#define BIT_R_WMAC_PFIN_TOEN_8197F BIT(46) +#define BIT_R_WMAC_FIL_SECERR_8197F BIT(45) +#define BIT_R_WMAC_FIL_CTLPKTLEN_8197F BIT(44) +#define BIT_R_WMAC_FIL_FCTYPE_8197F BIT(43) +#define BIT_R_WMAC_FIL_FCPROVER_8197F BIT(42) +#define BIT_R_WMAC_PHYSTS_SNIF_8197F BIT(41) +#define BIT_R_WMAC_PHYSTS_PLCP_8197F BIT(40) +#define BIT_R_MAC_TCR_VBONF_RD_8197F BIT(39) +#define BIT_R_WMAC_TCR_MPAR_NDP_8197F BIT(38) +#define BIT_R_WMAC_NDP_FILTER_8197F BIT(37) +#define BIT_R_WMAC_RXLEN_SEL_8197F BIT(36) +#define BIT_R_WMAC_RXLEN_SEL1_8197F BIT(35) +#define BIT_R_OFDM_FILTER_8197F BIT(34) +#define BIT_R_WMAC_CHK_OFDM_LEN_8197F BIT(33) +#define BIT_R_WMAC_CHK_CCK_LEN_8197F BIT(32) + +#define BIT_SHIFT_R_OFDM_LEN_8197F 26 +#define BIT_MASK_R_OFDM_LEN_8197F 0x3f +#define BIT_R_OFDM_LEN_8197F(x) (((x) & BIT_MASK_R_OFDM_LEN_8197F) << BIT_SHIFT_R_OFDM_LEN_8197F) +#define BITS_R_OFDM_LEN_8197F (BIT_MASK_R_OFDM_LEN_8197F << BIT_SHIFT_R_OFDM_LEN_8197F) +#define BIT_CLEAR_R_OFDM_LEN_8197F(x) ((x) & (~BITS_R_OFDM_LEN_8197F)) +#define BIT_GET_R_OFDM_LEN_8197F(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8197F) & BIT_MASK_R_OFDM_LEN_8197F) +#define BIT_SET_R_OFDM_LEN_8197F(x, v) (BIT_CLEAR_R_OFDM_LEN_8197F(x) | BIT_R_OFDM_LEN_8197F(v)) + + +#define BIT_SHIFT_R_CCK_LEN_8197F 0 +#define BIT_MASK_R_CCK_LEN_8197F 0xffff +#define BIT_R_CCK_LEN_8197F(x) (((x) & BIT_MASK_R_CCK_LEN_8197F) << BIT_SHIFT_R_CCK_LEN_8197F) +#define BITS_R_CCK_LEN_8197F (BIT_MASK_R_CCK_LEN_8197F << BIT_SHIFT_R_CCK_LEN_8197F) +#define BIT_CLEAR_R_CCK_LEN_8197F(x) ((x) & (~BITS_R_CCK_LEN_8197F)) +#define BIT_GET_R_CCK_LEN_8197F(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8197F) & BIT_MASK_R_CCK_LEN_8197F) +#define BIT_SET_R_CCK_LEN_8197F(x, v) (BIT_CLEAR_R_CCK_LEN_8197F(x) | BIT_R_CCK_LEN_8197F(v)) + + +/* 2 REG_RX_FILTER_FUNCTION_8197F */ +#define BIT_R_WMAC_RXHANG_EN_8197F BIT(15) +#define BIT_R_WMAC_MHRDDY_LATCH_8197F BIT(14) +#define BIT_R_MHRDDY_CLR_8197F BIT(13) +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8197F BIT(12) +#define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU_8197F BIT(11) +#define BIT_R_CHK_DELIMIT_LEN_8197F BIT(10) +#define BIT_R_REAPTER_ADDR_MATCH_8197F BIT(9) +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8197F BIT(8) +#define BIT_R_LATCH_MACHRDY_8197F BIT(7) +#define BIT_R_WMAC_RXFIL_REND_8197F BIT(6) +#define BIT_R_WMAC_MPDURDY_CLR_8197F BIT(5) +#define BIT_R_WMAC_CLRRXSEC_8197F BIT(4) +#define BIT_R_WMAC_RXFIL_RDEL_8197F BIT(3) +#define BIT_R_WMAC_RXFIL_FCSE_8197F BIT(2) +#define BIT_R_WMAC_RXFIL_MESH_DEL_8197F BIT(1) +#define BIT_R_WMAC_RXFIL_MASKM_8197F BIT(0) + +/* 2 REG_NDP_SIG_8197F */ + +#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F 0 +#define BIT_MASK_R_WMAC_TXNDP_SIGB_8197F 0x1fffff +#define BIT_R_WMAC_TXNDP_SIGB_8197F(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8197F) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) +#define BITS_R_WMAC_TXNDP_SIGB_8197F (BIT_MASK_R_WMAC_TXNDP_SIGB_8197F << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8197F)) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) & BIT_MASK_R_WMAC_TXNDP_SIGB_8197F) +#define BIT_SET_R_WMAC_TXNDP_SIGB_8197F(x, v) (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) | BIT_R_WMAC_TXNDP_SIGB_8197F(v)) + + +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8197F */ + +#define BIT_SHIFT_R_MAC_DEBUG_8197F (32 & CPU_OPT_WIDTH) +#define BIT_MASK_R_MAC_DEBUG_8197F 0xffffffffL +#define BIT_R_MAC_DEBUG_8197F(x) (((x) & BIT_MASK_R_MAC_DEBUG_8197F) << BIT_SHIFT_R_MAC_DEBUG_8197F) +#define BITS_R_MAC_DEBUG_8197F (BIT_MASK_R_MAC_DEBUG_8197F << BIT_SHIFT_R_MAC_DEBUG_8197F) +#define BIT_CLEAR_R_MAC_DEBUG_8197F(x) ((x) & (~BITS_R_MAC_DEBUG_8197F)) +#define BIT_GET_R_MAC_DEBUG_8197F(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_8197F) & BIT_MASK_R_MAC_DEBUG_8197F) +#define BIT_SET_R_MAC_DEBUG_8197F(x, v) (BIT_CLEAR_R_MAC_DEBUG_8197F(x) | BIT_R_MAC_DEBUG_8197F(v)) + + +#define BIT_SHIFT_R_MAC_DBG_SHIFT_8197F 8 +#define BIT_MASK_R_MAC_DBG_SHIFT_8197F 0x7 +#define BIT_R_MAC_DBG_SHIFT_8197F(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8197F) << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) +#define BITS_R_MAC_DBG_SHIFT_8197F (BIT_MASK_R_MAC_DBG_SHIFT_8197F << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) +#define BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8197F)) +#define BIT_GET_R_MAC_DBG_SHIFT_8197F(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) & BIT_MASK_R_MAC_DBG_SHIFT_8197F) +#define BIT_SET_R_MAC_DBG_SHIFT_8197F(x, v) (BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) | BIT_R_MAC_DBG_SHIFT_8197F(v)) + + +#define BIT_SHIFT_R_MAC_DBG_SEL_8197F 0 +#define BIT_MASK_R_MAC_DBG_SEL_8197F 0x3 +#define BIT_R_MAC_DBG_SEL_8197F(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8197F) << BIT_SHIFT_R_MAC_DBG_SEL_8197F) +#define BITS_R_MAC_DBG_SEL_8197F (BIT_MASK_R_MAC_DBG_SEL_8197F << BIT_SHIFT_R_MAC_DBG_SEL_8197F) +#define BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) ((x) & (~BITS_R_MAC_DBG_SEL_8197F)) +#define BIT_GET_R_MAC_DBG_SEL_8197F(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8197F) & BIT_MASK_R_MAC_DBG_SEL_8197F) +#define BIT_SET_R_MAC_DBG_SEL_8197F(x, v) (BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) | BIT_R_MAC_DBG_SEL_8197F(v)) + + +/* 2 REG_SEC_OPT_V2_8197F */ +#define BIT_MASK_IV_8197F BIT(18) +#define BIT_EIVL_ENDIAN_8197F BIT(17) +#define BIT_EIVH_ENDIAN_8197F BIT(16) + +#define BIT_SHIFT_BT_TIME_CNT_8197F 0 +#define BIT_MASK_BT_TIME_CNT_8197F 0xff +#define BIT_BT_TIME_CNT_8197F(x) (((x) & BIT_MASK_BT_TIME_CNT_8197F) << BIT_SHIFT_BT_TIME_CNT_8197F) +#define BITS_BT_TIME_CNT_8197F (BIT_MASK_BT_TIME_CNT_8197F << BIT_SHIFT_BT_TIME_CNT_8197F) +#define BIT_CLEAR_BT_TIME_CNT_8197F(x) ((x) & (~BITS_BT_TIME_CNT_8197F)) +#define BIT_GET_BT_TIME_CNT_8197F(x) (((x) >> BIT_SHIFT_BT_TIME_CNT_8197F) & BIT_MASK_BT_TIME_CNT_8197F) +#define BIT_SET_BT_TIME_CNT_8197F(x, v) (BIT_CLEAR_BT_TIME_CNT_8197F(x) | BIT_BT_TIME_CNT_8197F(v)) + + +/* 2 REG_RTS_ADDRESS_0_8197F */ + +/* 2 REG_RTS_ADDRESS_1_8197F */ + +#endif diff --git a/hal/halmac/halmac_bit_8814b.h b/hal/halmac/halmac_bit_8814b.h new file mode 100644 index 0000000..0db3a36 --- /dev/null +++ b/hal/halmac/halmac_bit_8814b.h @@ -0,0 +1,11725 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef __INC_HALMAC_BIT_8814B_H +#define __INC_HALMAC_BIT_8814B_H + +#define CPU_OPT_WIDTH 0x1F + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_SYS_ISO_CTRL_8814B */ +#define BIT_PWC_EV12V_8814B BIT(15) +#define BIT_PWC_EV25V_8814B BIT(14) +#define BIT_PA33V_EN_8814B BIT(13) +#define BIT_PA12V_EN_8814B BIT(12) +#define BIT_UA33V_EN_8814B BIT(11) +#define BIT_UA12V_EN_8814B BIT(10) +#define BIT_ISO_RFDIO_8814B BIT(9) +#define BIT_ISO_EB2CORE_8814B BIT(8) +#define BIT_ISO_DIOE_8814B BIT(7) +#define BIT_ISO_WLPON2PP_8814B BIT(6) +#define BIT_ISO_IP2MAC_WA2PP_8814B BIT(5) +#define BIT_ISO_PD2CORE_8814B BIT(4) +#define BIT_ISO_PA2PCIE_8814B BIT(3) +#define BIT_ISO_UD2CORE_8814B BIT(2) +#define BIT_ISO_UA2USB_8814B BIT(1) +#define BIT_ISO_WD2PP_8814B BIT(0) + +/* 2 REG_SYS_FUNC_EN_8814B */ +#define BIT_FEN_MREGEN_8814B BIT(15) +#define BIT_FEN_HWPDN_8814B BIT(14) +#define BIT_EN_25_1_8814B BIT(13) +#define BIT_FEN_ELDR_8814B BIT(12) +#define BIT_FEN_DCORE_8814B BIT(11) +#define BIT_FEN_CPUEN_8814B BIT(10) +#define BIT_FEN_DIOE_8814B BIT(9) +#define BIT_FEN_PCIED_8814B BIT(8) +#define BIT_FEN_PPLL_8814B BIT(7) +#define BIT_FEN_PCIEA_8814B BIT(6) +#define BIT_FEN_DIO_PCIE_8814B BIT(5) +#define BIT_FEN_USBD_8814B BIT(4) +#define BIT_FEN_UPLL_8814B BIT(3) +#define BIT_FEN_USBA_8814B BIT(2) +#define BIT_FEN_BB_GLB_RSTN_8814B BIT(1) +#define BIT_FEN_BBRSTB_8814B BIT(0) + +/* 2 REG_SYS_PW_CTRL_8814B */ +#define BIT_SOP_EABM_8814B BIT(31) +#define BIT_SOP_ACKF_8814B BIT(30) +#define BIT_SOP_ERCK_8814B BIT(29) +#define BIT_SOP_ESWR_8814B BIT(28) +#define BIT_SOP_PWMM_8814B BIT(27) +#define BIT_SOP_EECK_8814B BIT(26) +#define BIT_SOP_EXTL_8814B BIT(24) +#define BIT_SYM_OP_RING_12M_8814B BIT(22) +#define BIT_ROP_SWPR_8814B BIT(21) +#define BIT_DIS_HW_LPLDM_8814B BIT(20) +#define BIT_OPT_SWRST_WLMCU_8814B BIT(19) +#define BIT_RDY_SYSPWR_8814B BIT(17) +#define BIT_EN_WLON_8814B BIT(16) +#define BIT_APDM_HPDN_8814B BIT(15) +#define BIT_AFSM_PCIE_SUS_EN_8814B BIT(12) +#define BIT_AFSM_WLSUS_EN_8814B BIT(11) +#define BIT_APFM_SWLPS_8814B BIT(10) +#define BIT_APFM_OFFMAC_8814B BIT(9) +#define BIT_APFN_ONMAC_8814B BIT(8) +#define BIT_CHIP_PDN_EN_8814B BIT(7) +#define BIT_RDY_MACDIS_8814B BIT(6) +#define BIT_RING_CLK_12M_EN_8814B BIT(4) +#define BIT_PFM_WOWL_8814B BIT(3) +#define BIT_PFM_LDKP_8814B BIT(2) +#define BIT_WL_HCI_ALD_8814B BIT(1) +#define BIT_PFM_LDALL_8814B BIT(0) + +/* 2 REG_SYS_CLK_CTRL_8814B */ +#define BIT_LDO_DUMMY_8814B BIT(15) +#define BIT_CPU_CLK_EN_8814B BIT(14) +#define BIT_SYMREG_CLK_EN_8814B BIT(13) +#define BIT_HCI_CLK_EN_8814B BIT(12) +#define BIT_MAC_CLK_EN_8814B BIT(11) +#define BIT_SEC_CLK_EN_8814B BIT(10) +#define BIT_PHY_SSC_RSTB_8814B BIT(9) +#define BIT_EXT_32K_EN_8814B BIT(8) +#define BIT_WL_CLK_TEST_8814B BIT(7) +#define BIT_OP_SPS_PWM_EN_8814B BIT(6) +#define BIT_LOADER_CLK_EN_8814B BIT(5) +#define BIT_MACSLP_8814B BIT(4) +#define BIT_WAKEPAD_EN_8814B BIT(3) +#define BIT_ROMD16V_EN_8814B BIT(2) +#define BIT_CKANA12M_EN_8814B BIT(1) +#define BIT_CNTD16V_EN_8814B BIT(0) + +/* 2 REG_SYS_EEPROM_CTRL_8814B */ + +#define BIT_SHIFT_VPDIDX_8814B 8 +#define BIT_MASK_VPDIDX_8814B 0xff +#define BIT_VPDIDX_8814B(x) (((x) & BIT_MASK_VPDIDX_8814B) << BIT_SHIFT_VPDIDX_8814B) +#define BIT_GET_VPDIDX_8814B(x) (((x) >> BIT_SHIFT_VPDIDX_8814B) & BIT_MASK_VPDIDX_8814B) + + + +#define BIT_SHIFT_EEM1_0_8814B 6 +#define BIT_MASK_EEM1_0_8814B 0x3 +#define BIT_EEM1_0_8814B(x) (((x) & BIT_MASK_EEM1_0_8814B) << BIT_SHIFT_EEM1_0_8814B) +#define BIT_GET_EEM1_0_8814B(x) (((x) >> BIT_SHIFT_EEM1_0_8814B) & BIT_MASK_EEM1_0_8814B) + + +#define BIT_AUTOLOAD_SUS_8814B BIT(5) +#define BIT_EERPOMSEL_8814B BIT(4) +#define BIT_EECS_V1_8814B BIT(3) +#define BIT_EESK_V1_8814B BIT(2) +#define BIT_EEDI_V1_8814B BIT(1) +#define BIT_EEDO_V1_8814B BIT(0) + +/* 2 REG_EE_VPD_8814B */ + +#define BIT_SHIFT_VPD_DATA_8814B 0 +#define BIT_MASK_VPD_DATA_8814B 0xffffffffL +#define BIT_VPD_DATA_8814B(x) (((x) & BIT_MASK_VPD_DATA_8814B) << BIT_SHIFT_VPD_DATA_8814B) +#define BIT_GET_VPD_DATA_8814B(x) (((x) >> BIT_SHIFT_VPD_DATA_8814B) & BIT_MASK_VPD_DATA_8814B) + + + +/* 2 REG_SYS_SWR_CTRL1_8814B */ +#define BIT_C2_L_BIT0_8814B BIT(31) + +#define BIT_SHIFT_C1_L_8814B 29 +#define BIT_MASK_C1_L_8814B 0x3 +#define BIT_C1_L_8814B(x) (((x) & BIT_MASK_C1_L_8814B) << BIT_SHIFT_C1_L_8814B) +#define BIT_GET_C1_L_8814B(x) (((x) >> BIT_SHIFT_C1_L_8814B) & BIT_MASK_C1_L_8814B) + + + +#define BIT_SHIFT_REG_FREQ_L_8814B 25 +#define BIT_MASK_REG_FREQ_L_8814B 0x7 +#define BIT_REG_FREQ_L_8814B(x) (((x) & BIT_MASK_REG_FREQ_L_8814B) << BIT_SHIFT_REG_FREQ_L_8814B) +#define BIT_GET_REG_FREQ_L_8814B(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8814B) & BIT_MASK_REG_FREQ_L_8814B) + + +#define BIT_REG_EN_DUTY_8814B BIT(24) + +#define BIT_SHIFT_REG_MODE_8814B 22 +#define BIT_MASK_REG_MODE_8814B 0x3 +#define BIT_REG_MODE_8814B(x) (((x) & BIT_MASK_REG_MODE_8814B) << BIT_SHIFT_REG_MODE_8814B) +#define BIT_GET_REG_MODE_8814B(x) (((x) >> BIT_SHIFT_REG_MODE_8814B) & BIT_MASK_REG_MODE_8814B) + + +#define BIT_REG_EN_SP_8814B BIT(21) +#define BIT_REG_AUTO_L_8814B BIT(20) +#define BIT_SW18_SELD_BIT0_8814B BIT(19) +#define BIT_SW18_POWOCP_8814B BIT(18) + +#define BIT_SHIFT_OCP_L1_8814B 15 +#define BIT_MASK_OCP_L1_8814B 0x7 +#define BIT_OCP_L1_8814B(x) (((x) & BIT_MASK_OCP_L1_8814B) << BIT_SHIFT_OCP_L1_8814B) +#define BIT_GET_OCP_L1_8814B(x) (((x) >> BIT_SHIFT_OCP_L1_8814B) & BIT_MASK_OCP_L1_8814B) + + + +#define BIT_SHIFT_CF_L_8814B 13 +#define BIT_MASK_CF_L_8814B 0x3 +#define BIT_CF_L_8814B(x) (((x) & BIT_MASK_CF_L_8814B) << BIT_SHIFT_CF_L_8814B) +#define BIT_GET_CF_L_8814B(x) (((x) >> BIT_SHIFT_CF_L_8814B) & BIT_MASK_CF_L_8814B) + + +#define BIT_SW18_FPWM_8814B BIT(11) +#define BIT_SW18_SWEN_8814B BIT(9) +#define BIT_SW18_LDEN_8814B BIT(8) +#define BIT_MAC_ID_EN_8814B BIT(7) +#define BIT_AFE_BGEN_8814B BIT(0) + +/* 2 REG_SYS_SWR_CTRL2_8814B */ +#define BIT_POW_ZCD_L_8814B BIT(31) +#define BIT_AUTOZCD_L_8814B BIT(30) + +#define BIT_SHIFT_REG_DELAY_8814B 28 +#define BIT_MASK_REG_DELAY_8814B 0x3 +#define BIT_REG_DELAY_8814B(x) (((x) & BIT_MASK_REG_DELAY_8814B) << BIT_SHIFT_REG_DELAY_8814B) +#define BIT_GET_REG_DELAY_8814B(x) (((x) >> BIT_SHIFT_REG_DELAY_8814B) & BIT_MASK_REG_DELAY_8814B) + + + +#define BIT_SHIFT_V15ADJ_L1_V1_8814B 24 +#define BIT_MASK_V15ADJ_L1_V1_8814B 0x7 +#define BIT_V15ADJ_L1_V1_8814B(x) (((x) & BIT_MASK_V15ADJ_L1_V1_8814B) << BIT_SHIFT_V15ADJ_L1_V1_8814B) +#define BIT_GET_V15ADJ_L1_V1_8814B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8814B) & BIT_MASK_V15ADJ_L1_V1_8814B) + + + +#define BIT_SHIFT_VOL_L1_V1_8814B 20 +#define BIT_MASK_VOL_L1_V1_8814B 0xf +#define BIT_VOL_L1_V1_8814B(x) (((x) & BIT_MASK_VOL_L1_V1_8814B) << BIT_SHIFT_VOL_L1_V1_8814B) +#define BIT_GET_VOL_L1_V1_8814B(x) (((x) >> BIT_SHIFT_VOL_L1_V1_8814B) & BIT_MASK_VOL_L1_V1_8814B) + + + +#define BIT_SHIFT_IN_L1_V1_8814B 17 +#define BIT_MASK_IN_L1_V1_8814B 0x7 +#define BIT_IN_L1_V1_8814B(x) (((x) & BIT_MASK_IN_L1_V1_8814B) << BIT_SHIFT_IN_L1_V1_8814B) +#define BIT_GET_IN_L1_V1_8814B(x) (((x) >> BIT_SHIFT_IN_L1_V1_8814B) & BIT_MASK_IN_L1_V1_8814B) + + + +#define BIT_SHIFT_TBOX_L1_8814B 15 +#define BIT_MASK_TBOX_L1_8814B 0x3 +#define BIT_TBOX_L1_8814B(x) (((x) & BIT_MASK_TBOX_L1_8814B) << BIT_SHIFT_TBOX_L1_8814B) +#define BIT_GET_TBOX_L1_8814B(x) (((x) >> BIT_SHIFT_TBOX_L1_8814B) & BIT_MASK_TBOX_L1_8814B) + + +#define BIT_SW18_SEL_8814B BIT(13) + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SW18_SD_8814B BIT(10) + +#define BIT_SHIFT_R3_L_8814B 7 +#define BIT_MASK_R3_L_8814B 0x3 +#define BIT_R3_L_8814B(x) (((x) & BIT_MASK_R3_L_8814B) << BIT_SHIFT_R3_L_8814B) +#define BIT_GET_R3_L_8814B(x) (((x) >> BIT_SHIFT_R3_L_8814B) & BIT_MASK_R3_L_8814B) + + + +#define BIT_SHIFT_SW18_R2_8814B 5 +#define BIT_MASK_SW18_R2_8814B 0x3 +#define BIT_SW18_R2_8814B(x) (((x) & BIT_MASK_SW18_R2_8814B) << BIT_SHIFT_SW18_R2_8814B) +#define BIT_GET_SW18_R2_8814B(x) (((x) >> BIT_SHIFT_SW18_R2_8814B) & BIT_MASK_SW18_R2_8814B) + + + +#define BIT_SHIFT_SW18_R1_8814B 3 +#define BIT_MASK_SW18_R1_8814B 0x3 +#define BIT_SW18_R1_8814B(x) (((x) & BIT_MASK_SW18_R1_8814B) << BIT_SHIFT_SW18_R1_8814B) +#define BIT_GET_SW18_R1_8814B(x) (((x) >> BIT_SHIFT_SW18_R1_8814B) & BIT_MASK_SW18_R1_8814B) + + + +#define BIT_SHIFT_C3_L_C3_8814B 1 +#define BIT_MASK_C3_L_C3_8814B 0x3 +#define BIT_C3_L_C3_8814B(x) (((x) & BIT_MASK_C3_L_C3_8814B) << BIT_SHIFT_C3_L_C3_8814B) +#define BIT_GET_C3_L_C3_8814B(x) (((x) >> BIT_SHIFT_C3_L_C3_8814B) & BIT_MASK_C3_L_C3_8814B) + + +#define BIT_C2_L_BIT1_8814B BIT(0) + +/* 2 REG_SYS_SWR_CTRL3_8814B */ +#define BIT_SPS18_OCP_DIS_8814B BIT(31) + +#define BIT_SHIFT_SPS18_OCP_TH_8814B 16 +#define BIT_MASK_SPS18_OCP_TH_8814B 0x7fff +#define BIT_SPS18_OCP_TH_8814B(x) (((x) & BIT_MASK_SPS18_OCP_TH_8814B) << BIT_SHIFT_SPS18_OCP_TH_8814B) +#define BIT_GET_SPS18_OCP_TH_8814B(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8814B) & BIT_MASK_SPS18_OCP_TH_8814B) + + + +#define BIT_SHIFT_OCP_WINDOW_8814B 0 +#define BIT_MASK_OCP_WINDOW_8814B 0xffff +#define BIT_OCP_WINDOW_8814B(x) (((x) & BIT_MASK_OCP_WINDOW_8814B) << BIT_SHIFT_OCP_WINDOW_8814B) +#define BIT_GET_OCP_WINDOW_8814B(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8814B) & BIT_MASK_OCP_WINDOW_8814B) + + + +/* 2 REG_RSV_CTRL_8814B */ +#define BIT_HREG_DBG_8814B BIT(23) +#define BIT_WLMCUIOIF_8814B BIT(8) +#define BIT_LOCK_ALL_EN_8814B BIT(7) +#define BIT_R_DIS_PRST_8814B BIT(6) +#define BIT_WLOCK_1C_B6_8814B BIT(5) +#define BIT_WLOCK_40_8814B BIT(4) +#define BIT_WLOCK_08_8814B BIT(3) +#define BIT_WLOCK_04_8814B BIT(2) +#define BIT_WLOCK_00_8814B BIT(1) +#define BIT_WLOCK_ALL_8814B BIT(0) + +/* 2 REG_RF_CTRL_8814B */ +#define BIT_RF_SDMRSTB_8814B BIT(2) +#define BIT_RF_RSTB_8814B BIT(1) +#define BIT_RF_EN_8814B BIT(0) + +/* 2 REG_AFE_LDO_CTRL_8814B */ + +#define BIT_SHIFT_LPLDH12_RSV_8814B 29 +#define BIT_MASK_LPLDH12_RSV_8814B 0x7 +#define BIT_LPLDH12_RSV_8814B(x) (((x) & BIT_MASK_LPLDH12_RSV_8814B) << BIT_SHIFT_LPLDH12_RSV_8814B) +#define BIT_GET_LPLDH12_RSV_8814B(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8814B) & BIT_MASK_LPLDH12_RSV_8814B) + + +#define BIT_LPLDH12_SLP_8814B BIT(28) + +#define BIT_SHIFT_LPLDH12_VADJ_8814B 24 +#define BIT_MASK_LPLDH12_VADJ_8814B 0xf +#define BIT_LPLDH12_VADJ_8814B(x) (((x) & BIT_MASK_LPLDH12_VADJ_8814B) << BIT_SHIFT_LPLDH12_VADJ_8814B) +#define BIT_GET_LPLDH12_VADJ_8814B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8814B) & BIT_MASK_LPLDH12_VADJ_8814B) + + +#define BIT_PCIE_CALIB_EN_8814B BIT(17) +#define BIT_LDH12_EN_8814B BIT(16) +#define BIT_WLBBOFF_BIG_PWC_EN_8814B BIT(14) +#define BIT_WLBBOFF_SMALL_PWC_EN_8814B BIT(13) +#define BIT_WLMACOFF_BIG_PWC_EN_8814B BIT(12) +#define BIT_WLPON_PWC_EN_8814B BIT(11) +#define BIT_POW_REGU_P1_8814B BIT(10) +#define BIT_LDOV12W_EN_8814B BIT(8) +#define BIT_EX_XTAL_DRV_DIGI_8814B BIT(7) +#define BIT_EX_XTAL_DRV_USB_8814B BIT(6) +#define BIT_EX_XTAL_DRV_AFE_8814B BIT(5) +#define BIT_EX_XTAL_DRV_RF2_8814B BIT(4) +#define BIT_EX_XTAL_DRV_RF1_8814B BIT(3) +#define BIT_POW_REGU_P0_8814B BIT(2) + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_POW_PLL_LDO_8814B BIT(0) + +/* 2 REG_AFE_CTRL1_8814B */ +#define BIT_AGPIO_GPE_8814B BIT(31) + +#define BIT_SHIFT_XTAL_CAP_XI_8814B 25 +#define BIT_MASK_XTAL_CAP_XI_8814B 0x3f +#define BIT_XTAL_CAP_XI_8814B(x) (((x) & BIT_MASK_XTAL_CAP_XI_8814B) << BIT_SHIFT_XTAL_CAP_XI_8814B) +#define BIT_GET_XTAL_CAP_XI_8814B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8814B) & BIT_MASK_XTAL_CAP_XI_8814B) + + + +#define BIT_SHIFT_XTAL_DRV_DIGI_8814B 23 +#define BIT_MASK_XTAL_DRV_DIGI_8814B 0x3 +#define BIT_XTAL_DRV_DIGI_8814B(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8814B) << BIT_SHIFT_XTAL_DRV_DIGI_8814B) +#define BIT_GET_XTAL_DRV_DIGI_8814B(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8814B) & BIT_MASK_XTAL_DRV_DIGI_8814B) + + +#define BIT_XTAL_DRV_USB_BIT1_8814B BIT(22) + +#define BIT_SHIFT_MAC_CLK_SEL_8814B 20 +#define BIT_MASK_MAC_CLK_SEL_8814B 0x3 +#define BIT_MAC_CLK_SEL_8814B(x) (((x) & BIT_MASK_MAC_CLK_SEL_8814B) << BIT_SHIFT_MAC_CLK_SEL_8814B) +#define BIT_GET_MAC_CLK_SEL_8814B(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8814B) & BIT_MASK_MAC_CLK_SEL_8814B) + + +#define BIT_XTAL_DRV_USB_BIT0_8814B BIT(19) + +#define BIT_SHIFT_XTAL_DRV_AFE_8814B 17 +#define BIT_MASK_XTAL_DRV_AFE_8814B 0x3 +#define BIT_XTAL_DRV_AFE_8814B(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8814B) << BIT_SHIFT_XTAL_DRV_AFE_8814B) +#define BIT_GET_XTAL_DRV_AFE_8814B(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8814B) & BIT_MASK_XTAL_DRV_AFE_8814B) + + + +#define BIT_SHIFT_XTAL_DRV_RF2_8814B 15 +#define BIT_MASK_XTAL_DRV_RF2_8814B 0x3 +#define BIT_XTAL_DRV_RF2_8814B(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8814B) << BIT_SHIFT_XTAL_DRV_RF2_8814B) +#define BIT_GET_XTAL_DRV_RF2_8814B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8814B) & BIT_MASK_XTAL_DRV_RF2_8814B) + + + +#define BIT_SHIFT_XTAL_DRV_RF1_8814B 13 +#define BIT_MASK_XTAL_DRV_RF1_8814B 0x3 +#define BIT_XTAL_DRV_RF1_8814B(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8814B) << BIT_SHIFT_XTAL_DRV_RF1_8814B) +#define BIT_GET_XTAL_DRV_RF1_8814B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8814B) & BIT_MASK_XTAL_DRV_RF1_8814B) + + +#define BIT_XTAL_DELAY_DIGI_8814B BIT(12) +#define BIT_XTAL_DELAY_USB_8814B BIT(11) +#define BIT_XTAL_DELAY_AFE_8814B BIT(10) + +#define BIT_SHIFT_XTAL_LDO_VREF_8814B 7 +#define BIT_MASK_XTAL_LDO_VREF_8814B 0x7 +#define BIT_XTAL_LDO_VREF_8814B(x) (((x) & BIT_MASK_XTAL_LDO_VREF_8814B) << BIT_SHIFT_XTAL_LDO_VREF_8814B) +#define BIT_GET_XTAL_LDO_VREF_8814B(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8814B) & BIT_MASK_XTAL_LDO_VREF_8814B) + + +#define BIT_XTAL_XQSEL_RF_8814B BIT(6) +#define BIT_XTAL_XQSEL_8814B BIT(5) + +#define BIT_SHIFT_XTAL_GMN_V2_8814B 3 +#define BIT_MASK_XTAL_GMN_V2_8814B 0x3 +#define BIT_XTAL_GMN_V2_8814B(x) (((x) & BIT_MASK_XTAL_GMN_V2_8814B) << BIT_SHIFT_XTAL_GMN_V2_8814B) +#define BIT_GET_XTAL_GMN_V2_8814B(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2_8814B) & BIT_MASK_XTAL_GMN_V2_8814B) + + + +#define BIT_SHIFT_XTAL_GMP_V2_8814B 1 +#define BIT_MASK_XTAL_GMP_V2_8814B 0x3 +#define BIT_XTAL_GMP_V2_8814B(x) (((x) & BIT_MASK_XTAL_GMP_V2_8814B) << BIT_SHIFT_XTAL_GMP_V2_8814B) +#define BIT_GET_XTAL_GMP_V2_8814B(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2_8814B) & BIT_MASK_XTAL_GMP_V2_8814B) + + +#define BIT_XTAL_EN_8814B BIT(0) + +/* 2 REG_AFE_CTRL2_8814B */ + +#define BIT_SHIFT_REG_C3_V4_8814B 30 +#define BIT_MASK_REG_C3_V4_8814B 0x3 +#define BIT_REG_C3_V4_8814B(x) (((x) & BIT_MASK_REG_C3_V4_8814B) << BIT_SHIFT_REG_C3_V4_8814B) +#define BIT_GET_REG_C3_V4_8814B(x) (((x) >> BIT_SHIFT_REG_C3_V4_8814B) & BIT_MASK_REG_C3_V4_8814B) + + +#define BIT_REG_CP_BIT1_8814B BIT(29) + +#define BIT_SHIFT_REG_RS_V4_8814B 26 +#define BIT_MASK_REG_RS_V4_8814B 0x7 +#define BIT_REG_RS_V4_8814B(x) (((x) & BIT_MASK_REG_RS_V4_8814B) << BIT_SHIFT_REG_RS_V4_8814B) +#define BIT_GET_REG_RS_V4_8814B(x) (((x) >> BIT_SHIFT_REG_RS_V4_8814B) & BIT_MASK_REG_RS_V4_8814B) + + + +#define BIT_SHIFT_REG__CS_8814B 24 +#define BIT_MASK_REG__CS_8814B 0x3 +#define BIT_REG__CS_8814B(x) (((x) & BIT_MASK_REG__CS_8814B) << BIT_SHIFT_REG__CS_8814B) +#define BIT_GET_REG__CS_8814B(x) (((x) >> BIT_SHIFT_REG__CS_8814B) & BIT_MASK_REG__CS_8814B) + + + +#define BIT_SHIFT_REG_CP_OFFSET_8814B 21 +#define BIT_MASK_REG_CP_OFFSET_8814B 0x7 +#define BIT_REG_CP_OFFSET_8814B(x) (((x) & BIT_MASK_REG_CP_OFFSET_8814B) << BIT_SHIFT_REG_CP_OFFSET_8814B) +#define BIT_GET_REG_CP_OFFSET_8814B(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_8814B) & BIT_MASK_REG_CP_OFFSET_8814B) + + + +#define BIT_SHIFT_CP_BIAS_8814B 18 +#define BIT_MASK_CP_BIAS_8814B 0x7 +#define BIT_CP_BIAS_8814B(x) (((x) & BIT_MASK_CP_BIAS_8814B) << BIT_SHIFT_CP_BIAS_8814B) +#define BIT_GET_CP_BIAS_8814B(x) (((x) >> BIT_SHIFT_CP_BIAS_8814B) & BIT_MASK_CP_BIAS_8814B) + + +#define BIT_REG_IDOUBLE_V2_8814B BIT(17) +#define BIT_EN_SYN_8814B BIT(16) + +#define BIT_SHIFT_MCCO_8814B 14 +#define BIT_MASK_MCCO_8814B 0x3 +#define BIT_MCCO_8814B(x) (((x) & BIT_MASK_MCCO_8814B) << BIT_SHIFT_MCCO_8814B) +#define BIT_GET_MCCO_8814B(x) (((x) >> BIT_SHIFT_MCCO_8814B) & BIT_MASK_MCCO_8814B) + + + +#define BIT_SHIFT_REG_LDO_SEL_8814B 12 +#define BIT_MASK_REG_LDO_SEL_8814B 0x3 +#define BIT_REG_LDO_SEL_8814B(x) (((x) & BIT_MASK_REG_LDO_SEL_8814B) << BIT_SHIFT_REG_LDO_SEL_8814B) +#define BIT_GET_REG_LDO_SEL_8814B(x) (((x) >> BIT_SHIFT_REG_LDO_SEL_8814B) & BIT_MASK_REG_LDO_SEL_8814B) + + +#define BIT_REG_KVCO_V2_8814B BIT(10) +#define BIT_AGPIO_GPO_8814B BIT(9) + +#define BIT_SHIFT_AGPIO_DRV_8814B 7 +#define BIT_MASK_AGPIO_DRV_8814B 0x3 +#define BIT_AGPIO_DRV_8814B(x) (((x) & BIT_MASK_AGPIO_DRV_8814B) << BIT_SHIFT_AGPIO_DRV_8814B) +#define BIT_GET_AGPIO_DRV_8814B(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8814B) & BIT_MASK_AGPIO_DRV_8814B) + + + +#define BIT_SHIFT_XTAL_CAP_XO_8814B 1 +#define BIT_MASK_XTAL_CAP_XO_8814B 0x3f +#define BIT_XTAL_CAP_XO_8814B(x) (((x) & BIT_MASK_XTAL_CAP_XO_8814B) << BIT_SHIFT_XTAL_CAP_XO_8814B) +#define BIT_GET_XTAL_CAP_XO_8814B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8814B) & BIT_MASK_XTAL_CAP_XO_8814B) + + +#define BIT_POW_PLL_8814B BIT(0) + +/* 2 REG_AFE_CTRL3_8814B */ + +#define BIT_SHIFT_PS_8814B 7 +#define BIT_MASK_PS_8814B 0x7 +#define BIT_PS_8814B(x) (((x) & BIT_MASK_PS_8814B) << BIT_SHIFT_PS_8814B) +#define BIT_GET_PS_8814B(x) (((x) >> BIT_SHIFT_PS_8814B) & BIT_MASK_PS_8814B) + + +#define BIT_PSEN_8814B BIT(6) +#define BIT_DOGENB_8814B BIT(5) +#define BIT_REG_MBIAS_8814B BIT(4) + +#define BIT_SHIFT_REG_R3_V4_8814B 1 +#define BIT_MASK_REG_R3_V4_8814B 0x7 +#define BIT_REG_R3_V4_8814B(x) (((x) & BIT_MASK_REG_R3_V4_8814B) << BIT_SHIFT_REG_R3_V4_8814B) +#define BIT_GET_REG_R3_V4_8814B(x) (((x) >> BIT_SHIFT_REG_R3_V4_8814B) & BIT_MASK_REG_R3_V4_8814B) + + +#define BIT_REG_CP_BIT0_8814B BIT(0) + +/* 2 REG_EFUSE_CTRL_8814B */ +#define BIT_EF_FLAG_8814B BIT(31) + +#define BIT_SHIFT_EF_PGPD_8814B 28 +#define BIT_MASK_EF_PGPD_8814B 0x7 +#define BIT_EF_PGPD_8814B(x) (((x) & BIT_MASK_EF_PGPD_8814B) << BIT_SHIFT_EF_PGPD_8814B) +#define BIT_GET_EF_PGPD_8814B(x) (((x) >> BIT_SHIFT_EF_PGPD_8814B) & BIT_MASK_EF_PGPD_8814B) + + + +#define BIT_SHIFT_EF_RDT_8814B 24 +#define BIT_MASK_EF_RDT_8814B 0xf +#define BIT_EF_RDT_8814B(x) (((x) & BIT_MASK_EF_RDT_8814B) << BIT_SHIFT_EF_RDT_8814B) +#define BIT_GET_EF_RDT_8814B(x) (((x) >> BIT_SHIFT_EF_RDT_8814B) & BIT_MASK_EF_RDT_8814B) + + + +#define BIT_SHIFT_EF_PGTS_8814B 20 +#define BIT_MASK_EF_PGTS_8814B 0xf +#define BIT_EF_PGTS_8814B(x) (((x) & BIT_MASK_EF_PGTS_8814B) << BIT_SHIFT_EF_PGTS_8814B) +#define BIT_GET_EF_PGTS_8814B(x) (((x) >> BIT_SHIFT_EF_PGTS_8814B) & BIT_MASK_EF_PGTS_8814B) + + +#define BIT_EF_PDWN_8814B BIT(19) +#define BIT_EF_ALDEN_8814B BIT(18) + +#define BIT_SHIFT_EF_ADDR_8814B 8 +#define BIT_MASK_EF_ADDR_8814B 0x3ff +#define BIT_EF_ADDR_8814B(x) (((x) & BIT_MASK_EF_ADDR_8814B) << BIT_SHIFT_EF_ADDR_8814B) +#define BIT_GET_EF_ADDR_8814B(x) (((x) >> BIT_SHIFT_EF_ADDR_8814B) & BIT_MASK_EF_ADDR_8814B) + + + +#define BIT_SHIFT_EF_DATA_8814B 0 +#define BIT_MASK_EF_DATA_8814B 0xff +#define BIT_EF_DATA_8814B(x) (((x) & BIT_MASK_EF_DATA_8814B) << BIT_SHIFT_EF_DATA_8814B) +#define BIT_GET_EF_DATA_8814B(x) (((x) >> BIT_SHIFT_EF_DATA_8814B) & BIT_MASK_EF_DATA_8814B) + + + +/* 2 REG_LDO_EFUSE_CTRL_8814B */ +#define BIT_LDOE25_EN_8814B BIT(31) + +#define BIT_SHIFT_LDOE25_V12ADJ_L_8814B 27 +#define BIT_MASK_LDOE25_V12ADJ_L_8814B 0xf +#define BIT_LDOE25_V12ADJ_L_8814B(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8814B) << BIT_SHIFT_LDOE25_V12ADJ_L_8814B) +#define BIT_GET_LDOE25_V12ADJ_L_8814B(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8814B) & BIT_MASK_LDOE25_V12ADJ_L_8814B) + + +#define BIT_EF_CRES_SEL_8814B BIT(26) + +#define BIT_SHIFT_EF_SCAN_START_V1_8814B 16 +#define BIT_MASK_EF_SCAN_START_V1_8814B 0x3ff +#define BIT_EF_SCAN_START_V1_8814B(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8814B) << BIT_SHIFT_EF_SCAN_START_V1_8814B) +#define BIT_GET_EF_SCAN_START_V1_8814B(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8814B) & BIT_MASK_EF_SCAN_START_V1_8814B) + + + +#define BIT_SHIFT_EF_SCAN_END_8814B 12 +#define BIT_MASK_EF_SCAN_END_8814B 0xf +#define BIT_EF_SCAN_END_8814B(x) (((x) & BIT_MASK_EF_SCAN_END_8814B) << BIT_SHIFT_EF_SCAN_END_8814B) +#define BIT_GET_EF_SCAN_END_8814B(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8814B) & BIT_MASK_EF_SCAN_END_8814B) + + +#define BIT_EF_PD_DIS_8814B BIT(11) + +#define BIT_SHIFT_EF_CELL_SEL_8814B 8 +#define BIT_MASK_EF_CELL_SEL_8814B 0x3 +#define BIT_EF_CELL_SEL_8814B(x) (((x) & BIT_MASK_EF_CELL_SEL_8814B) << BIT_SHIFT_EF_CELL_SEL_8814B) +#define BIT_GET_EF_CELL_SEL_8814B(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8814B) & BIT_MASK_EF_CELL_SEL_8814B) + + +#define BIT_EF_TRPT_8814B BIT(7) + +#define BIT_SHIFT_EF_TTHD_8814B 0 +#define BIT_MASK_EF_TTHD_8814B 0x7f +#define BIT_EF_TTHD_8814B(x) (((x) & BIT_MASK_EF_TTHD_8814B) << BIT_SHIFT_EF_TTHD_8814B) +#define BIT_GET_EF_TTHD_8814B(x) (((x) >> BIT_SHIFT_EF_TTHD_8814B) & BIT_MASK_EF_TTHD_8814B) + + + +/* 2 REG_PWR_OPTION_CTRL_8814B */ + +#define BIT_SHIFT_DBG_SEL_V1_8814B 16 +#define BIT_MASK_DBG_SEL_V1_8814B 0xff +#define BIT_DBG_SEL_V1_8814B(x) (((x) & BIT_MASK_DBG_SEL_V1_8814B) << BIT_SHIFT_DBG_SEL_V1_8814B) +#define BIT_GET_DBG_SEL_V1_8814B(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8814B) & BIT_MASK_DBG_SEL_V1_8814B) + + + +#define BIT_SHIFT_DBG_SEL_BYTE_8814B 14 +#define BIT_MASK_DBG_SEL_BYTE_8814B 0x3 +#define BIT_DBG_SEL_BYTE_8814B(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8814B) << BIT_SHIFT_DBG_SEL_BYTE_8814B) +#define BIT_GET_DBG_SEL_BYTE_8814B(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8814B) & BIT_MASK_DBG_SEL_BYTE_8814B) + + + +#define BIT_SHIFT_STD_L1_V1_8814B 12 +#define BIT_MASK_STD_L1_V1_8814B 0x3 +#define BIT_STD_L1_V1_8814B(x) (((x) & BIT_MASK_STD_L1_V1_8814B) << BIT_SHIFT_STD_L1_V1_8814B) +#define BIT_GET_STD_L1_V1_8814B(x) (((x) >> BIT_SHIFT_STD_L1_V1_8814B) & BIT_MASK_STD_L1_V1_8814B) + + +#define BIT_SYSON_DBG_PAD_E2_8814B BIT(11) +#define BIT_SYSON_LED_PAD_E2_8814B BIT(10) +#define BIT_SYSON_GPEE_PAD_E2_8814B BIT(9) +#define BIT_SYSON_PCI_PAD_E2_8814B BIT(8) +#define BIT_AUTO_SW_LDO_VOL_EN_8814B BIT(7) + +#define BIT_SHIFT_SYSON_SPS0WWV_WT_8814B 4 +#define BIT_MASK_SYSON_SPS0WWV_WT_8814B 0x3 +#define BIT_SYSON_SPS0WWV_WT_8814B(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8814B) << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) +#define BIT_GET_SYSON_SPS0WWV_WT_8814B(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) & BIT_MASK_SYSON_SPS0WWV_WT_8814B) + + + +#define BIT_SHIFT_SYSON_SPS0LDO_WT_8814B 2 +#define BIT_MASK_SYSON_SPS0LDO_WT_8814B 0x3 +#define BIT_SYSON_SPS0LDO_WT_8814B(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8814B) << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) +#define BIT_GET_SYSON_SPS0LDO_WT_8814B(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) & BIT_MASK_SYSON_SPS0LDO_WT_8814B) + + + +#define BIT_SHIFT_SYSON_RCLK_SCALE_8814B 0 +#define BIT_MASK_SYSON_RCLK_SCALE_8814B 0x3 +#define BIT_SYSON_RCLK_SCALE_8814B(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8814B) << BIT_SHIFT_SYSON_RCLK_SCALE_8814B) +#define BIT_GET_SYSON_RCLK_SCALE_8814B(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8814B) & BIT_MASK_SYSON_RCLK_SCALE_8814B) + + + +/* 2 REG_CAL_TIMER_8814B */ + +#define BIT_SHIFT_MATCH_CNT_8814B 8 +#define BIT_MASK_MATCH_CNT_8814B 0xff +#define BIT_MATCH_CNT_8814B(x) (((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B) +#define BIT_GET_MATCH_CNT_8814B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B) + + + +#define BIT_SHIFT_CAL_SCAL_8814B 0 +#define BIT_MASK_CAL_SCAL_8814B 0xff +#define BIT_CAL_SCAL_8814B(x) (((x) & BIT_MASK_CAL_SCAL_8814B) << BIT_SHIFT_CAL_SCAL_8814B) +#define BIT_GET_CAL_SCAL_8814B(x) (((x) >> BIT_SHIFT_CAL_SCAL_8814B) & BIT_MASK_CAL_SCAL_8814B) + + + +/* 2 REG_ACLK_MON_8814B */ + +#define BIT_SHIFT_RCLK_MON_8814B 5 +#define BIT_MASK_RCLK_MON_8814B 0x7ff +#define BIT_RCLK_MON_8814B(x) (((x) & BIT_MASK_RCLK_MON_8814B) << BIT_SHIFT_RCLK_MON_8814B) +#define BIT_GET_RCLK_MON_8814B(x) (((x) >> BIT_SHIFT_RCLK_MON_8814B) & BIT_MASK_RCLK_MON_8814B) + + +#define BIT_CAL_EN_8814B BIT(4) + +#define BIT_SHIFT_DPSTU_8814B 2 +#define BIT_MASK_DPSTU_8814B 0x3 +#define BIT_DPSTU_8814B(x) (((x) & BIT_MASK_DPSTU_8814B) << BIT_SHIFT_DPSTU_8814B) +#define BIT_GET_DPSTU_8814B(x) (((x) >> BIT_SHIFT_DPSTU_8814B) & BIT_MASK_DPSTU_8814B) + + +#define BIT_SUS_16X_8814B BIT(1) + +/* 2 REG_GPIO_MUXCFG_8814B */ +#define BIT_FSPI_EN_8814B BIT(19) +#define BIT_WL_RTS_EXT_32K_SEL_8814B BIT(18) +#define BIT_WLGP_SPI_EN_8814B BIT(16) +#define BIT_SIC_LBK_8814B BIT(15) +#define BIT_ENHTP_8814B BIT(14) +#define BIT_ENSIC_8814B BIT(12) +#define BIT_SIC_SWRST_8814B BIT(11) +#define BIT_PO_WIFI_PTA_PINS_8814B BIT(10) +#define BIT_PO_BT_PTA_PINS_8814B BIT(9) +#define BIT_ENUART_8814B BIT(8) + +#define BIT_SHIFT_BTMODE_8814B 6 +#define BIT_MASK_BTMODE_8814B 0x3 +#define BIT_BTMODE_8814B(x) (((x) & BIT_MASK_BTMODE_8814B) << BIT_SHIFT_BTMODE_8814B) +#define BIT_GET_BTMODE_8814B(x) (((x) >> BIT_SHIFT_BTMODE_8814B) & BIT_MASK_BTMODE_8814B) + + +#define BIT_ENBT_8814B BIT(5) +#define BIT_EROM_EN_8814B BIT(4) +#define BIT_WLRFE_6_7_EN_8814B BIT(3) +#define BIT_WLRFE_4_5_EN_8814B BIT(2) + +#define BIT_SHIFT_GPIOSEL_8814B 0 +#define BIT_MASK_GPIOSEL_8814B 0x3 +#define BIT_GPIOSEL_8814B(x) (((x) & BIT_MASK_GPIOSEL_8814B) << BIT_SHIFT_GPIOSEL_8814B) +#define BIT_GET_GPIOSEL_8814B(x) (((x) >> BIT_SHIFT_GPIOSEL_8814B) & BIT_MASK_GPIOSEL_8814B) + + + +/* 2 REG_GPIO_PIN_CTRL_8814B */ + +#define BIT_SHIFT_GPIO_MOD_7_TO_0_8814B 24 +#define BIT_MASK_GPIO_MOD_7_TO_0_8814B 0xff +#define BIT_GPIO_MOD_7_TO_0_8814B(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8814B) << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) +#define BIT_GET_GPIO_MOD_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) & BIT_MASK_GPIO_MOD_7_TO_0_8814B) + + + +#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B 16 +#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B 0xff +#define BIT_GPIO_IO_SEL_7_TO_0_8814B(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B) + + + +#define BIT_SHIFT_GPIO_OUT_7_TO_0_8814B 8 +#define BIT_MASK_GPIO_OUT_7_TO_0_8814B 0xff +#define BIT_GPIO_OUT_7_TO_0_8814B(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8814B) << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) +#define BIT_GET_GPIO_OUT_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) & BIT_MASK_GPIO_OUT_7_TO_0_8814B) + + + +#define BIT_SHIFT_GPIO_IN_7_TO_0_8814B 0 +#define BIT_MASK_GPIO_IN_7_TO_0_8814B 0xff +#define BIT_GPIO_IN_7_TO_0_8814B(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8814B) << BIT_SHIFT_GPIO_IN_7_TO_0_8814B) +#define BIT_GET_GPIO_IN_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8814B) & BIT_MASK_GPIO_IN_7_TO_0_8814B) + + + +/* 2 REG_GPIO_INTM_8814B */ + +#define BIT_SHIFT_MUXDBG_SEL_8814B 30 +#define BIT_MASK_MUXDBG_SEL_8814B 0x3 +#define BIT_MUXDBG_SEL_8814B(x) (((x) & BIT_MASK_MUXDBG_SEL_8814B) << BIT_SHIFT_MUXDBG_SEL_8814B) +#define BIT_GET_MUXDBG_SEL_8814B(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8814B) & BIT_MASK_MUXDBG_SEL_8814B) + + +#define BIT_EXTWOL_SEL_8814B BIT(17) +#define BIT_EXTWOL_EN_8814B BIT(16) +#define BIT_GPIOF_INT_MD_8814B BIT(15) +#define BIT_GPIOE_INT_MD_8814B BIT(14) +#define BIT_GPIOD_INT_MD_8814B BIT(13) +#define BIT_GPIOF_INT_MD_8814B BIT(15) +#define BIT_GPIOE_INT_MD_8814B BIT(14) +#define BIT_GPIOD_INT_MD_8814B BIT(13) +#define BIT_GPIOC_INT_MD_8814B BIT(12) +#define BIT_GPIOB_INT_MD_8814B BIT(11) +#define BIT_GPIOA_INT_MD_8814B BIT(10) +#define BIT_GPIO9_INT_MD_8814B BIT(9) +#define BIT_GPIO8_INT_MD_8814B BIT(8) +#define BIT_GPIO7_INT_MD_8814B BIT(7) +#define BIT_GPIO6_INT_MD_8814B BIT(6) +#define BIT_GPIO5_INT_MD_8814B BIT(5) +#define BIT_GPIO4_INT_MD_8814B BIT(4) +#define BIT_GPIO3_INT_MD_8814B BIT(3) +#define BIT_GPIO2_INT_MD_8814B BIT(2) +#define BIT_GPIO1_INT_MD_8814B BIT(1) +#define BIT_GPIO0_INT_MD_8814B BIT(0) + +/* 2 REG_LED_CFG_8814B */ +#define BIT_GPIO3_WL_CTRL_EN_8814B BIT(27) +#define BIT_LNAON_SEL_EN_8814B BIT(26) +#define BIT_PAPE_SEL_EN_8814B BIT(25) +#define BIT_DPDT_WLBT_SEL_8814B BIT(24) +#define BIT_DPDT_SEL_EN_8814B BIT(23) +#define BIT_GPIO13_14_WL_CTRL_EN_8814B BIT(22) +#define BIT_GPIO13_14_WL_CTRL_EN_8814B BIT(22) +#define BIT_LED2DIS_8814B BIT(21) +#define BIT_LED2PL_8814B BIT(20) +#define BIT_LED2SV_8814B BIT(19) + +#define BIT_SHIFT_LED2CM_8814B 16 +#define BIT_MASK_LED2CM_8814B 0x7 +#define BIT_LED2CM_8814B(x) (((x) & BIT_MASK_LED2CM_8814B) << BIT_SHIFT_LED2CM_8814B) +#define BIT_GET_LED2CM_8814B(x) (((x) >> BIT_SHIFT_LED2CM_8814B) & BIT_MASK_LED2CM_8814B) + + +#define BIT_LED1DIS_8814B BIT(15) +#define BIT_LED1PL_8814B BIT(12) +#define BIT_LED1SV_8814B BIT(11) + +#define BIT_SHIFT_LED1CM_8814B 8 +#define BIT_MASK_LED1CM_8814B 0x7 +#define BIT_LED1CM_8814B(x) (((x) & BIT_MASK_LED1CM_8814B) << BIT_SHIFT_LED1CM_8814B) +#define BIT_GET_LED1CM_8814B(x) (((x) >> BIT_SHIFT_LED1CM_8814B) & BIT_MASK_LED1CM_8814B) + + +#define BIT_LED0DIS_8814B BIT(7) + +#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B 5 +#define BIT_MASK_AFE_LDO_SWR_CHECK_8814B 0x3 +#define BIT_AFE_LDO_SWR_CHECK_8814B(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8814B) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) +#define BIT_GET_AFE_LDO_SWR_CHECK_8814B(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) & BIT_MASK_AFE_LDO_SWR_CHECK_8814B) + + +#define BIT_LED0PL_8814B BIT(4) +#define BIT_LED0SV_8814B BIT(3) + +#define BIT_SHIFT_LED0CM_8814B 0 +#define BIT_MASK_LED0CM_8814B 0x7 +#define BIT_LED0CM_8814B(x) (((x) & BIT_MASK_LED0CM_8814B) << BIT_SHIFT_LED0CM_8814B) +#define BIT_GET_LED0CM_8814B(x) (((x) >> BIT_SHIFT_LED0CM_8814B) & BIT_MASK_LED0CM_8814B) + + + +/* 2 REG_FSIMR_8814B */ +#define BIT_FS_PDNINT_EN_8814B BIT(31) +#define BIT_NFC_INT_PAD_EN_8814B BIT(30) +#define BIT_FS_SPS_OCP_INT_EN_8814B BIT(29) +#define BIT_FS_PWMERR_INT_EN_8814B BIT(28) +#define BIT_FS_GPIOF_INT_EN_8814B BIT(27) +#define BIT_FS_GPIOE_INT_EN_8814B BIT(26) +#define BIT_FS_GPIOD_INT_EN_8814B BIT(25) +#define BIT_FS_GPIOC_INT_EN_8814B BIT(24) +#define BIT_FS_GPIOB_INT_EN_8814B BIT(23) +#define BIT_FS_GPIOA_INT_EN_8814B BIT(22) +#define BIT_FS_GPIO9_INT_EN_8814B BIT(21) +#define BIT_FS_GPIO8_INT_EN_8814B BIT(20) +#define BIT_FS_GPIO7_INT_EN_8814B BIT(19) +#define BIT_FS_GPIO6_INT_EN_8814B BIT(18) +#define BIT_FS_GPIO5_INT_EN_8814B BIT(17) +#define BIT_FS_GPIO4_INT_EN_8814B BIT(16) +#define BIT_FS_GPIO3_INT_EN_8814B BIT(15) +#define BIT_FS_GPIO2_INT_EN_8814B BIT(14) +#define BIT_FS_GPIO1_INT_EN_8814B BIT(13) +#define BIT_FS_GPIO0_INT_EN_8814B BIT(12) +#define BIT_FS_HCI_SUS_EN_8814B BIT(11) +#define BIT_FS_HCI_RES_EN_8814B BIT(10) +#define BIT_FS_HCI_RESET_EN_8814B BIT(9) +#define BIT_USB_SCSI_CMD_EN_8814B BIT(8) +#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8814B BIT(7) +#define BIT_ACT2RECOVERY_INT_EN_V1_8814B BIT(6) +#define BIT_GEN1GEN2_SWITCH_8814B BIT(5) +#define BIT_HCI_TXDMA_REQ_HIMR_8814B BIT(4) +#define BIT_FS_32K_LEAVE_SETTING_MAK_8814B BIT(3) +#define BIT_FS_32K_ENTER_SETTING_MAK_8814B BIT(2) +#define BIT_FS_USB_LPMRSM_MSK_8814B BIT(1) +#define BIT_FS_USB_LPMINT_MSK_8814B BIT(0) + +/* 2 REG_FSISR_8814B */ +#define BIT_FS_PDNINT_8814B BIT(31) +#define BIT_FS_SPS_OCP_INT_8814B BIT(29) +#define BIT_FS_PWMERR_INT_8814B BIT(28) +#define BIT_FS_GPIOF_INT_8814B BIT(27) +#define BIT_FS_GPIOE_INT_8814B BIT(26) +#define BIT_FS_GPIOD_INT_8814B BIT(25) +#define BIT_FS_GPIOC_INT_8814B BIT(24) +#define BIT_FS_GPIOB_INT_8814B BIT(23) +#define BIT_FS_GPIOA_INT_8814B BIT(22) +#define BIT_FS_GPIO9_INT_8814B BIT(21) +#define BIT_FS_GPIO8_INT_8814B BIT(20) +#define BIT_FS_GPIO7_INT_8814B BIT(19) +#define BIT_FS_GPIO6_INT_8814B BIT(18) +#define BIT_FS_GPIO5_INT_8814B BIT(17) +#define BIT_FS_GPIO4_INT_8814B BIT(16) +#define BIT_FS_GPIO3_INT_8814B BIT(15) +#define BIT_FS_GPIO2_INT_8814B BIT(14) +#define BIT_FS_GPIO1_INT_8814B BIT(13) +#define BIT_FS_GPIO0_INT_8814B BIT(12) +#define BIT_FS_HCI_SUS_INT_8814B BIT(11) +#define BIT_FS_HCI_RES_INT_8814B BIT(10) +#define BIT_FS_HCI_RESET_INT_8814B BIT(9) +#define BIT_USB_SCSI_CMD_INT_8814B BIT(8) +#define BIT_ACT2RECOVERY_8814B BIT(6) +#define BIT_GEN1GEN2_SWITCH_8814B BIT(5) +#define BIT_HCI_TXDMA_REQ_HISR_8814B BIT(4) +#define BIT_FS_32K_LEAVE_SETTING_INT_8814B BIT(3) +#define BIT_FS_32K_ENTER_SETTING_INT_8814B BIT(2) +#define BIT_FS_USB_LPMRSM_INT_8814B BIT(1) +#define BIT_FS_USB_LPMINT_INT_8814B BIT(0) + +/* 2 REG_HSIMR_8814B */ +#define BIT_GPIOF_INT_EN_8814B BIT(31) +#define BIT_GPIOE_INT_EN_8814B BIT(30) +#define BIT_GPIOD_INT_EN_8814B BIT(29) +#define BIT_GPIOC_INT_EN_8814B BIT(28) +#define BIT_GPIOB_INT_EN_8814B BIT(27) +#define BIT_GPIOA_INT_EN_8814B BIT(26) +#define BIT_GPIO9_INT_EN_8814B BIT(25) +#define BIT_GPIO8_INT_EN_8814B BIT(24) +#define BIT_GPIO7_INT_EN_8814B BIT(23) +#define BIT_GPIO6_INT_EN_8814B BIT(22) +#define BIT_GPIO5_INT_EN_8814B BIT(21) +#define BIT_GPIO4_INT_EN_8814B BIT(20) +#define BIT_GPIO3_INT_EN_8814B BIT(19) +#define BIT_GPIO2_INT_EN_V1_8814B BIT(16) +#define BIT_GPIO1_INT_EN_8814B BIT(17) +#define BIT_GPIO0_INT_EN_8814B BIT(16) +#define BIT_PDNINT_EN_8814B BIT(7) +#define BIT_RON_INT_EN_8814B BIT(6) +#define BIT_SPS_OCP_INT_EN_8814B BIT(5) +#define BIT_GPIO15_0_INT_EN_8814B BIT(0) + +/* 2 REG_HSISR_8814B */ +#define BIT_GPIOF_INT_8814B BIT(31) +#define BIT_GPIOE_INT_8814B BIT(30) +#define BIT_GPIOD_INT_8814B BIT(29) +#define BIT_GPIOC_INT_8814B BIT(28) +#define BIT_GPIOB_INT_8814B BIT(27) +#define BIT_GPIOA_INT_8814B BIT(26) +#define BIT_GPIO9_INT_8814B BIT(25) +#define BIT_GPIO8_INT_8814B BIT(24) +#define BIT_GPIO7_INT_8814B BIT(23) +#define BIT_GPIO6_INT_8814B BIT(22) +#define BIT_GPIO5_INT_8814B BIT(21) +#define BIT_GPIO4_INT_8814B BIT(20) +#define BIT_GPIO3_INT_8814B BIT(19) +#define BIT_GPIO2_INT_V1_8814B BIT(16) +#define BIT_GPIO1_INT_8814B BIT(17) +#define BIT_GPIO0_INT_8814B BIT(16) +#define BIT_PDNINT_8814B BIT(7) +#define BIT_RON_INT_8814B BIT(6) +#define BIT_SPS_OCP_INT_8814B BIT(5) +#define BIT_GPIO15_0_INT_8814B BIT(0) + +/* 2 REG_GPIO_EXT_CTRL_8814B */ + +#define BIT_SHIFT_GPIO_MOD_15_TO_8_8814B 24 +#define BIT_MASK_GPIO_MOD_15_TO_8_8814B 0xff +#define BIT_GPIO_MOD_15_TO_8_8814B(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8814B) << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) +#define BIT_GET_GPIO_MOD_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) & BIT_MASK_GPIO_MOD_15_TO_8_8814B) + + + +#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B 16 +#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B 0xff +#define BIT_GPIO_IO_SEL_15_TO_8_8814B(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B) + + + +#define BIT_SHIFT_GPIO_OUT_15_TO_8_8814B 8 +#define BIT_MASK_GPIO_OUT_15_TO_8_8814B 0xff +#define BIT_GPIO_OUT_15_TO_8_8814B(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8814B) << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) +#define BIT_GET_GPIO_OUT_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) & BIT_MASK_GPIO_OUT_15_TO_8_8814B) + + + +#define BIT_SHIFT_GPIO_IN_15_TO_8_8814B 0 +#define BIT_MASK_GPIO_IN_15_TO_8_8814B 0xff +#define BIT_GPIO_IN_15_TO_8_8814B(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8814B) << BIT_SHIFT_GPIO_IN_15_TO_8_8814B) +#define BIT_GET_GPIO_IN_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8814B) & BIT_MASK_GPIO_IN_15_TO_8_8814B) + + + +/* 2 REG_PAD_CTRL1_8814B */ +#define BIT_PAPE_WLBT_SEL_8814B BIT(29) +#define BIT_LNAON_WLBT_SEL_8814B BIT(28) +#define BIT_BTGP_GPG3_FEN_8814B BIT(26) +#define BIT_BTGP_GPG2_FEN_8814B BIT(25) +#define BIT_BTGP_JTAG_EN_8814B BIT(24) +#define BIT_XTAL_CLK_EXTARNAL_EN_8814B BIT(23) +#define BIT_BTGP_UART0_EN_8814B BIT(22) +#define BIT_BTGP_UART1_EN_8814B BIT(21) +#define BIT_BTGP_SPI_EN_8814B BIT(20) +#define BIT_BTGP_GPIO_E2_8814B BIT(19) +#define BIT_BTGP_GPIO_EN_8814B BIT(18) + +#define BIT_SHIFT_BTGP_GPIO_SL_8814B 16 +#define BIT_MASK_BTGP_GPIO_SL_8814B 0x3 +#define BIT_BTGP_GPIO_SL_8814B(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8814B) << BIT_SHIFT_BTGP_GPIO_SL_8814B) +#define BIT_GET_BTGP_GPIO_SL_8814B(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8814B) & BIT_MASK_BTGP_GPIO_SL_8814B) + + +#define BIT_PAD_SDIO_SR_8814B BIT(14) +#define BIT_GPIO14_OUTPUT_PL_8814B BIT(13) +#define BIT_HOST_WAKE_PAD_PULL_EN_8814B BIT(12) +#define BIT_HOST_WAKE_PAD_SL_8814B BIT(11) +#define BIT_PAD_LNAON_SR_8814B BIT(10) +#define BIT_PAD_LNAON_E2_8814B BIT(9) +#define BIT_SW_LNAON_G_SEL_DATA_8814B BIT(8) +#define BIT_SW_LNAON_A_SEL_DATA_8814B BIT(7) +#define BIT_PAD_PAPE_SR_8814B BIT(6) +#define BIT_PAD_PAPE_E2_8814B BIT(5) +#define BIT_SW_PAPE_G_SEL_DATA_8814B BIT(4) +#define BIT_SW_PAPE_A_SEL_DATA_8814B BIT(3) +#define BIT_PAD_DPDT_SR_8814B BIT(2) +#define BIT_PAD_DPDT_PAD_E2_8814B BIT(1) +#define BIT_SW_DPDT_SEL_DATA_8814B BIT(0) + +/* 2 REG_WL_BT_PWR_CTRL_8814B */ +#define BIT_ISO_BD2PP_8814B BIT(31) +#define BIT_LDOV12B_EN_8814B BIT(30) +#define BIT_CKEN_BTGPS_8814B BIT(29) +#define BIT_FEN_BTGPS_8814B BIT(28) +#define BIT_BTCPU_BOOTSEL_8814B BIT(27) +#define BIT_SPI_SPEEDUP_8814B BIT(26) +#define BIT_DEVWAKE_PAD_TYPE_SEL_8814B BIT(24) +#define BIT_CLKREQ_PAD_TYPE_SEL_8814B BIT(23) +#define BIT_ISO_BTPON2PP_8814B BIT(22) +#define BIT_BT_HWROF_EN_8814B BIT(19) +#define BIT_BT_FUNC_EN_8814B BIT(18) +#define BIT_BT_HWPDN_SL_8814B BIT(17) +#define BIT_BT_DISN_EN_8814B BIT(16) +#define BIT_BT_PDN_PULL_EN_8814B BIT(15) +#define BIT_WL_PDN_PULL_EN_8814B BIT(14) +#define BIT_EXTERNAL_REQUEST_PL_8814B BIT(13) +#define BIT_GPIO0_2_3_PULL_LOW_EN_8814B BIT(12) +#define BIT_ISO_BA2PP_8814B BIT(11) +#define BIT_BT_AFE_LDO_EN_8814B BIT(10) +#define BIT_BT_AFE_PLL_EN_8814B BIT(9) +#define BIT_BT_DIG_CLK_EN_8814B BIT(8) +#define BIT_WL_DRV_EXIST_IDX_8814B BIT(5) +#define BIT_DOP_EHPAD_8814B BIT(4) +#define BIT_WL_HWROF_EN_8814B BIT(3) +#define BIT_WL_FUNC_EN_8814B BIT(2) +#define BIT_WL_HWPDN_SL_8814B BIT(1) +#define BIT_WL_HWPDN_EN_8814B BIT(0) + +/* 2 REG_SDM_DEBUG_8814B */ + +#define BIT_SHIFT_WLCLK_PHASE_8814B 0 +#define BIT_MASK_WLCLK_PHASE_8814B 0x1f +#define BIT_WLCLK_PHASE_8814B(x) (((x) & BIT_MASK_WLCLK_PHASE_8814B) << BIT_SHIFT_WLCLK_PHASE_8814B) +#define BIT_GET_WLCLK_PHASE_8814B(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8814B) & BIT_MASK_WLCLK_PHASE_8814B) + + + +/* 2 REG_SYS_SDIO_CTRL_8814B */ +#define BIT_DBG_GNT_WL_BT_8814B BIT(27) +#define BIT_LTE_MUX_CTRL_PATH_8814B BIT(26) +#define BIT_LTE_COEX_UART_8814B BIT(25) +#define BIT_3W_LTE_WL_GPIO_8814B BIT(24) +#define BIT_SDIO_INT_POLARITY_8814B BIT(19) +#define BIT_SDIO_INT_8814B BIT(18) +#define BIT_SDIO_OFF_EN_8814B BIT(17) +#define BIT_SDIO_ON_EN_8814B BIT(16) +#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8814B BIT(10) +#define BIT_PCIE_WAIT_TIME_8814B BIT(9) +#define BIT_MPCIE_REFCLK_XTAL_SEL_8814B BIT(8) +#define BIT_RES_USB_MASS_STORAGE_DESC_8814B BIT(1) +#define BIT_USB_WAIT_TIME_8814B BIT(0) + +/* 2 REG_HCI_OPT_CTRL_8814B */ + +#define BIT_SHIFT_TSFT_SEL_8814B 29 +#define BIT_MASK_TSFT_SEL_8814B 0x7 +#define BIT_TSFT_SEL_8814B(x) (((x) & BIT_MASK_TSFT_SEL_8814B) << BIT_SHIFT_TSFT_SEL_8814B) +#define BIT_GET_TSFT_SEL_8814B(x) (((x) >> BIT_SHIFT_TSFT_SEL_8814B) & BIT_MASK_TSFT_SEL_8814B) + + +#define BIT_USB_HOST_PWR_OFF_EN_8814B BIT(12) +#define BIT_SYM_LPS_BLOCK_EN_8814B BIT(11) +#define BIT_USB_LPM_ACT_EN_8814B BIT(10) +#define BIT_USB_LPM_NY_8814B BIT(9) +#define BIT_USB_SUS_DIS_8814B BIT(8) + +#define BIT_SHIFT_SDIO_PAD_E_8814B 5 +#define BIT_MASK_SDIO_PAD_E_8814B 0x7 +#define BIT_SDIO_PAD_E_8814B(x) (((x) & BIT_MASK_SDIO_PAD_E_8814B) << BIT_SHIFT_SDIO_PAD_E_8814B) +#define BIT_GET_SDIO_PAD_E_8814B(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8814B) & BIT_MASK_SDIO_PAD_E_8814B) + + +#define BIT_USB_LPPLL_EN_8814B BIT(4) +#define BIT_ROP_SW15_8814B BIT(2) +#define BIT_PCI_CKRDY_OPT_8814B BIT(1) +#define BIT_PCI_VAUX_EN_8814B BIT(0) + +/* 2 REG_AFE_CTRL4_8814B */ + +/* 2 REG_LDO_SWR_CTRL_8814B */ +#define BIT_ZCD_HW_AUTO_EN_8814B BIT(27) +#define BIT_ZCD_REGSEL_8814B BIT(26) + +#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B 21 +#define BIT_MASK_AUTO_ZCD_IN_CODE_8814B 0x1f +#define BIT_AUTO_ZCD_IN_CODE_8814B(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8814B) << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) +#define BIT_GET_AUTO_ZCD_IN_CODE_8814B(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) & BIT_MASK_AUTO_ZCD_IN_CODE_8814B) + + + +#define BIT_SHIFT_ZCD_CODE_IN_L_8814B 16 +#define BIT_MASK_ZCD_CODE_IN_L_8814B 0x1f +#define BIT_ZCD_CODE_IN_L_8814B(x) (((x) & BIT_MASK_ZCD_CODE_IN_L_8814B) << BIT_SHIFT_ZCD_CODE_IN_L_8814B) +#define BIT_GET_ZCD_CODE_IN_L_8814B(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8814B) & BIT_MASK_ZCD_CODE_IN_L_8814B) + + + +#define BIT_SHIFT_LDO_HV5_DUMMY_8814B 14 +#define BIT_MASK_LDO_HV5_DUMMY_8814B 0x3 +#define BIT_LDO_HV5_DUMMY_8814B(x) (((x) & BIT_MASK_LDO_HV5_DUMMY_8814B) << BIT_SHIFT_LDO_HV5_DUMMY_8814B) +#define BIT_GET_LDO_HV5_DUMMY_8814B(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8814B) & BIT_MASK_LDO_HV5_DUMMY_8814B) + + + +#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8814B 12 +#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8814B 0x3 +#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8814B(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8814B) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8814B) +#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8814B(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8814B) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8814B) + + + +#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8814B 10 +#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8814B 0x3 +#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8814B(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8814B) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8814B) +#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8814B(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8814B) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8814B) + + + +#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8814B 8 +#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8814B 0x3 +#define BIT_REG_LOAD33_BIT0_TO_BIT1_8814B(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8814B) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8814B) +#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8814B(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8814B) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8814B) + + +#define BIT_REG_BYPASS_L_8814B BIT(7) +#define BIT_REG_LDOF_L_8814B BIT(6) +#define BIT_REG_OCPS_L_8814B BIT(5) +#define BIT_ARENB_L_8814B BIT(3) + +#define BIT_SHIFT_CFC_L_8814B 1 +#define BIT_MASK_CFC_L_8814B 0x3 +#define BIT_CFC_L_8814B(x) (((x) & BIT_MASK_CFC_L_8814B) << BIT_SHIFT_CFC_L_8814B) +#define BIT_GET_CFC_L_8814B(x) (((x) >> BIT_SHIFT_CFC_L_8814B) & BIT_MASK_CFC_L_8814B) + + +#define BIT_REG_TYPE_L_8814B BIT(0) + +/* 2 REG_MCUFW_CTRL_8814B */ + +#define BIT_SHIFT_RPWM_8814B 24 +#define BIT_MASK_RPWM_8814B 0xff +#define BIT_RPWM_8814B(x) (((x) & BIT_MASK_RPWM_8814B) << BIT_SHIFT_RPWM_8814B) +#define BIT_GET_RPWM_8814B(x) (((x) >> BIT_SHIFT_RPWM_8814B) & BIT_MASK_RPWM_8814B) + + +#define BIT_ANA_PORT_EN_8814B BIT(22) +#define BIT_MAC_PORT_EN_8814B BIT(21) +#define BIT_BOOT_FSPI_EN_8814B BIT(20) +#define BIT_ROM_DLEN_8814B BIT(19) + +#define BIT_SHIFT_ROM_PGE_8814B 16 +#define BIT_MASK_ROM_PGE_8814B 0x7 +#define BIT_ROM_PGE_8814B(x) (((x) & BIT_MASK_ROM_PGE_8814B) << BIT_SHIFT_ROM_PGE_8814B) +#define BIT_GET_ROM_PGE_8814B(x) (((x) >> BIT_SHIFT_ROM_PGE_8814B) & BIT_MASK_ROM_PGE_8814B) + + +#define BIT_FW_INIT_RDY_8814B BIT(15) +#define BIT_FW_DW_RDY_8814B BIT(14) + +#define BIT_SHIFT_CPU_CLK_SEL_8814B 12 +#define BIT_MASK_CPU_CLK_SEL_8814B 0x3 +#define BIT_CPU_CLK_SEL_8814B(x) (((x) & BIT_MASK_CPU_CLK_SEL_8814B) << BIT_SHIFT_CPU_CLK_SEL_8814B) +#define BIT_GET_CPU_CLK_SEL_8814B(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8814B) & BIT_MASK_CPU_CLK_SEL_8814B) + + +#define BIT_CCLK_CHG_MASK_8814B BIT(11) +#define BIT_EMEM__TXBUF_CHKSUM_OK_8814B BIT(10) +#define BIT_EMEM_TXBUF_DW_RDY_8814B BIT(9) +#define BIT_EMEM_CHKSUM_OK_8814B BIT(8) +#define BIT_EMEM_DW_OK_8814B BIT(7) +#define BIT_DMEM_CHKSUM_OK_8814B BIT(6) +#define BIT_DMEM_DW_OK_8814B BIT(5) +#define BIT_IMEM_CHKSUM_OK_8814B BIT(4) +#define BIT_IMEM_DW_OK_8814B BIT(3) +#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8814B BIT(2) +#define BIT_IMEM_BOOT_LOAD_DW_OK_8814B BIT(1) +#define BIT_MCUFWDL_EN_8814B BIT(0) + +/* 2 REG_MCU_TST_CFG_8814B */ + +#define BIT_SHIFT_LBKTST_8814B 0 +#define BIT_MASK_LBKTST_8814B 0xffff +#define BIT_LBKTST_8814B(x) (((x) & BIT_MASK_LBKTST_8814B) << BIT_SHIFT_LBKTST_8814B) +#define BIT_GET_LBKTST_8814B(x) (((x) >> BIT_SHIFT_LBKTST_8814B) & BIT_MASK_LBKTST_8814B) + + + +/* 2 REG_HMEBOX_E0_E1_8814B */ + +#define BIT_SHIFT_HOST_MSG_E1_8814B 16 +#define BIT_MASK_HOST_MSG_E1_8814B 0xffff +#define BIT_HOST_MSG_E1_8814B(x) (((x) & BIT_MASK_HOST_MSG_E1_8814B) << BIT_SHIFT_HOST_MSG_E1_8814B) +#define BIT_GET_HOST_MSG_E1_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8814B) & BIT_MASK_HOST_MSG_E1_8814B) + + + +#define BIT_SHIFT_HOST_MSG_E0_8814B 0 +#define BIT_MASK_HOST_MSG_E0_8814B 0xffff +#define BIT_HOST_MSG_E0_8814B(x) (((x) & BIT_MASK_HOST_MSG_E0_8814B) << BIT_SHIFT_HOST_MSG_E0_8814B) +#define BIT_GET_HOST_MSG_E0_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8814B) & BIT_MASK_HOST_MSG_E0_8814B) + + + +/* 2 REG_HMEBOX_E2_E3_8814B */ + +#define BIT_SHIFT_HOST_MSG_E3_8814B 16 +#define BIT_MASK_HOST_MSG_E3_8814B 0xffff +#define BIT_HOST_MSG_E3_8814B(x) (((x) & BIT_MASK_HOST_MSG_E3_8814B) << BIT_SHIFT_HOST_MSG_E3_8814B) +#define BIT_GET_HOST_MSG_E3_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8814B) & BIT_MASK_HOST_MSG_E3_8814B) + + + +#define BIT_SHIFT_HOST_MSG_E2_8814B 0 +#define BIT_MASK_HOST_MSG_E2_8814B 0xffff +#define BIT_HOST_MSG_E2_8814B(x) (((x) & BIT_MASK_HOST_MSG_E2_8814B) << BIT_SHIFT_HOST_MSG_E2_8814B) +#define BIT_GET_HOST_MSG_E2_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8814B) & BIT_MASK_HOST_MSG_E2_8814B) + + + +/* 2 REG_WLLPS_CTRL_8814B */ +#define BIT_WLLPSOP_EABM_8814B BIT(31) +#define BIT_WLLPSOP_ACKF_8814B BIT(30) +#define BIT_WLLPSOP_DLDM_8814B BIT(29) +#define BIT_WLLPSOP_ESWR_8814B BIT(28) +#define BIT_WLLPSOP_PWMM_8814B BIT(27) +#define BIT_WLLPSOP_EECK_8814B BIT(26) +#define BIT_WLLPSOP_WLMACOFF_8814B BIT(25) +#define BIT_WLLPSOP_EXTAL_8814B BIT(24) +#define BIT_WL_SYNPON_VOLTSPDN_8814B BIT(23) +#define BIT_WLLPSOP_WLBBOFF_8814B BIT(22) +#define BIT_WLLPSOP_WLMEM_DS_8814B BIT(21) + +#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B 12 +#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B 0xf +#define BIT_LPLDH12_VADJ_STEP_DN_8814B(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) +#define BIT_GET_LPLDH12_VADJ_STEP_DN_8814B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B) + + + +#define BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B 8 +#define BIT_MASK_V15ADJ_L1_STEP_DN_8814B 0x7 +#define BIT_V15ADJ_L1_STEP_DN_8814B(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8814B) << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) +#define BIT_GET_V15ADJ_L1_STEP_DN_8814B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) & BIT_MASK_V15ADJ_L1_STEP_DN_8814B) + + +#define BIT_REGU_32K_CLK_EN_8814B BIT(1) +#define BIT_WL_LPS_EN_8814B BIT(0) + +/* 2 REG_AFE_CTRL5_8814B */ +#define BIT_BB_DBG_SEL_AFE_SDM_BIT0_8814B BIT(31) +#define BIT_ORDER_SDM_8814B BIT(30) +#define BIT_RFE_SEL_SDM_8814B BIT(29) + +#define BIT_SHIFT_REF_SEL_8814B 25 +#define BIT_MASK_REF_SEL_8814B 0xf +#define BIT_REF_SEL_8814B(x) (((x) & BIT_MASK_REF_SEL_8814B) << BIT_SHIFT_REF_SEL_8814B) +#define BIT_GET_REF_SEL_8814B(x) (((x) >> BIT_SHIFT_REF_SEL_8814B) & BIT_MASK_REF_SEL_8814B) + + + +#define BIT_SHIFT_F0F_SDM_8814B 12 +#define BIT_MASK_F0F_SDM_8814B 0x1fff +#define BIT_F0F_SDM_8814B(x) (((x) & BIT_MASK_F0F_SDM_8814B) << BIT_SHIFT_F0F_SDM_8814B) +#define BIT_GET_F0F_SDM_8814B(x) (((x) >> BIT_SHIFT_F0F_SDM_8814B) & BIT_MASK_F0F_SDM_8814B) + + + +#define BIT_SHIFT_F0N_SDM_8814B 9 +#define BIT_MASK_F0N_SDM_8814B 0x7 +#define BIT_F0N_SDM_8814B(x) (((x) & BIT_MASK_F0N_SDM_8814B) << BIT_SHIFT_F0N_SDM_8814B) +#define BIT_GET_F0N_SDM_8814B(x) (((x) >> BIT_SHIFT_F0N_SDM_8814B) & BIT_MASK_F0N_SDM_8814B) + + + +#define BIT_SHIFT_DIVN_SDM_8814B 3 +#define BIT_MASK_DIVN_SDM_8814B 0x3f +#define BIT_DIVN_SDM_8814B(x) (((x) & BIT_MASK_DIVN_SDM_8814B) << BIT_SHIFT_DIVN_SDM_8814B) +#define BIT_GET_DIVN_SDM_8814B(x) (((x) >> BIT_SHIFT_DIVN_SDM_8814B) & BIT_MASK_DIVN_SDM_8814B) + + + +/* 2 REG_GPIO_DEBOUNCE_CTRL_8814B */ +#define BIT_WLGP_DBC1EN_8814B BIT(15) + +#define BIT_SHIFT_WLGP_DBC1_8814B 8 +#define BIT_MASK_WLGP_DBC1_8814B 0xf +#define BIT_WLGP_DBC1_8814B(x) (((x) & BIT_MASK_WLGP_DBC1_8814B) << BIT_SHIFT_WLGP_DBC1_8814B) +#define BIT_GET_WLGP_DBC1_8814B(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8814B) & BIT_MASK_WLGP_DBC1_8814B) + + +#define BIT_WLGP_DBC0EN_8814B BIT(7) + +#define BIT_SHIFT_WLGP_DBC0_8814B 0 +#define BIT_MASK_WLGP_DBC0_8814B 0xf +#define BIT_WLGP_DBC0_8814B(x) (((x) & BIT_MASK_WLGP_DBC0_8814B) << BIT_SHIFT_WLGP_DBC0_8814B) +#define BIT_GET_WLGP_DBC0_8814B(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8814B) & BIT_MASK_WLGP_DBC0_8814B) + + + +/* 2 REG_RPWM2_8814B */ + +#define BIT_SHIFT_RPWM2_8814B 16 +#define BIT_MASK_RPWM2_8814B 0xffff +#define BIT_RPWM2_8814B(x) (((x) & BIT_MASK_RPWM2_8814B) << BIT_SHIFT_RPWM2_8814B) +#define BIT_GET_RPWM2_8814B(x) (((x) >> BIT_SHIFT_RPWM2_8814B) & BIT_MASK_RPWM2_8814B) + + + +/* 2 REG_SYSON_FSM_MON_8814B */ + +#define BIT_SHIFT_FSM_MON_SEL_8814B 24 +#define BIT_MASK_FSM_MON_SEL_8814B 0x7 +#define BIT_FSM_MON_SEL_8814B(x) (((x) & BIT_MASK_FSM_MON_SEL_8814B) << BIT_SHIFT_FSM_MON_SEL_8814B) +#define BIT_GET_FSM_MON_SEL_8814B(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8814B) & BIT_MASK_FSM_MON_SEL_8814B) + + +#define BIT_DOP_ELDO_8814B BIT(23) +#define BIT_FSM_MON_UPD_8814B BIT(15) + +#define BIT_SHIFT_FSM_PAR_8814B 0 +#define BIT_MASK_FSM_PAR_8814B 0x7fff +#define BIT_FSM_PAR_8814B(x) (((x) & BIT_MASK_FSM_PAR_8814B) << BIT_SHIFT_FSM_PAR_8814B) +#define BIT_GET_FSM_PAR_8814B(x) (((x) >> BIT_SHIFT_FSM_PAR_8814B) & BIT_MASK_FSM_PAR_8814B) + + + +/* 2 REG_AFE_CTRL6_8814B */ + +#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B 0 +#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B 0x7 +#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B) + + + +/* 2 REG_PMC_DBG_CTRL1_8814B */ +#define BIT_BT_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B 16 +#define BIT_MASK_RD_WR_WIFI_BT_INFO_8814B 0x7fff +#define BIT_RD_WR_WIFI_BT_INFO_8814B(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8814B) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8814B(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) & BIT_MASK_RD_WR_WIFI_BT_INFO_8814B) + + +#define BIT_PMC_WR_OVF_8814B BIT(8) + +#define BIT_SHIFT_WLPMC_ERRINT_8814B 0 +#define BIT_MASK_WLPMC_ERRINT_8814B 0xff +#define BIT_WLPMC_ERRINT_8814B(x) (((x) & BIT_MASK_WLPMC_ERRINT_8814B) << BIT_SHIFT_WLPMC_ERRINT_8814B) +#define BIT_GET_WLPMC_ERRINT_8814B(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8814B) & BIT_MASK_WLPMC_ERRINT_8814B) + + + +/* 2 REG_AFE_CTRL7_8814B */ + +#define BIT_SHIFT_SEL_V_8814B 30 +#define BIT_MASK_SEL_V_8814B 0x3 +#define BIT_SEL_V_8814B(x) (((x) & BIT_MASK_SEL_V_8814B) << BIT_SHIFT_SEL_V_8814B) +#define BIT_GET_SEL_V_8814B(x) (((x) >> BIT_SHIFT_SEL_V_8814B) & BIT_MASK_SEL_V_8814B) + + +#define BIT_SEL_LDO_PC_8814B BIT(29) + +#define BIT_SHIFT_CK_MON_SEL_8814B 26 +#define BIT_MASK_CK_MON_SEL_8814B 0x7 +#define BIT_CK_MON_SEL_8814B(x) (((x) & BIT_MASK_CK_MON_SEL_8814B) << BIT_SHIFT_CK_MON_SEL_8814B) +#define BIT_GET_CK_MON_SEL_8814B(x) (((x) >> BIT_SHIFT_CK_MON_SEL_8814B) & BIT_MASK_CK_MON_SEL_8814B) + + +#define BIT_CK_MON_EN_8814B BIT(25) +#define BIT_FREF_EDGE_8814B BIT(24) +#define BIT_CK320M_EN_8814B BIT(23) +#define BIT_CK_5M_EN_8814B BIT(22) +#define BIT_TESTEN_8814B BIT(21) + +/* 2 REG_HIMR0_8814B */ +#define BIT_TIMEOUT_INTERRUPT2_MASK_8814B BIT(31) +#define BIT_TIMEOUT_INTERRUTP1_MASK_8814B BIT(30) +#define BIT_PSTIMEOUT_MSK_8814B BIT(29) +#define BIT_GTINT4_MSK_8814B BIT(28) +#define BIT_GTINT3_MSK_8814B BIT(27) +#define BIT_TXBCN0ERR_MSK_8814B BIT(26) +#define BIT_TXBCN0OK_MSK_8814B BIT(25) +#define BIT_TSF_BIT32_TOGGLE_MSK_8814B BIT(24) +#define BIT_BCNDMAINT0_MSK_8814B BIT(20) +#define BIT_BCNDERR0_MSK_8814B BIT(16) +#define BIT_HSISR_IND_ON_INT_MSK_8814B BIT(15) +#define BIT_BCNDMAINT_E_MSK_8814B BIT(14) +#define BIT_CTWEND_MSK_8814B BIT(12) +#define BIT_HISR1_IND_MSK_8814B BIT(11) +#define BIT_C2HCMD_MSK_8814B BIT(10) +#define BIT_CPWM2_MSK_8814B BIT(9) +#define BIT_CPWM_MSK_8814B BIT(8) +#define BIT_HIGHDOK_MSK_8814B BIT(7) +#define BIT_MGTDOK_MSK_8814B BIT(6) +#define BIT_BKDOK_MSK_8814B BIT(5) +#define BIT_BEDOK_MSK_8814B BIT(4) +#define BIT_VIDOK_MSK_8814B BIT(3) +#define BIT_VODOK_MSK_8814B BIT(2) +#define BIT_RDU_MSK_8814B BIT(1) +#define BIT_RXOK_MSK_8814B BIT(0) + +/* 2 REG_HISR0_8814B */ +#define BIT_TIMEOUT_INTERRUPT2_8814B BIT(31) +#define BIT_TIMEOUT_INTERRUTP1_8814B BIT(30) +#define BIT_PSTIMEOUT_8814B BIT(29) +#define BIT_GTINT4_8814B BIT(28) +#define BIT_GTINT3_8814B BIT(27) +#define BIT_TXBCN0ERR_8814B BIT(26) +#define BIT_TXBCN0OK_8814B BIT(25) +#define BIT_TSF_BIT32_TOGGLE_8814B BIT(24) +#define BIT_BCNDMAINT0_8814B BIT(20) +#define BIT_BCNDERR0_8814B BIT(16) +#define BIT_HSISR_IND_ON_INT_8814B BIT(15) +#define BIT_BCNDMAINT_E_8814B BIT(14) +#define BIT_CTWEND_8814B BIT(12) +#define BIT_HISR1_IND_INT_8814B BIT(11) +#define BIT_C2HCMD_8814B BIT(10) +#define BIT_CPWM2_8814B BIT(9) +#define BIT_CPWM_8814B BIT(8) +#define BIT_HIGHDOK_8814B BIT(7) +#define BIT_MGTDOK_8814B BIT(6) +#define BIT_BKDOK_8814B BIT(5) +#define BIT_BEDOK_8814B BIT(4) +#define BIT_VIDOK_8814B BIT(3) +#define BIT_VODOK_8814B BIT(2) +#define BIT_RDU_8814B BIT(1) +#define BIT_RXOK_8814B BIT(0) + +/* 2 REG_HIMR1_8814B */ +#define BIT_TXFIFO_TH_INT_8814B BIT(30) +#define BIT_BTON_STS_UPDATE_MASK_8814B BIT(29) +#define BIT_MCU_ERR_MASK_8814B BIT(28) +#define BIT_BCNDMAINT7__MSK_8814B BIT(27) +#define BIT_BCNDMAINT6__MSK_8814B BIT(26) +#define BIT_BCNDMAINT5__MSK_8814B BIT(25) +#define BIT_BCNDMAINT4__MSK_8814B BIT(24) +#define BIT_BCNDMAINT3_MSK_8814B BIT(23) +#define BIT_BCNDMAINT2_MSK_8814B BIT(22) +#define BIT_BCNDMAINT1_MSK_8814B BIT(21) +#define BIT_BCNDERR7_MSK_8814B BIT(20) +#define BIT_BCNDERR6_MSK_8814B BIT(19) +#define BIT_BCNDERR5_MSK_8814B BIT(18) +#define BIT_BCNDERR4_MSK_8814B BIT(17) +#define BIT_BCNDERR3_MSK_8814B BIT(16) +#define BIT_BCNDERR2_MSK_8814B BIT(15) +#define BIT_BCNDERR1_MSK_8814B BIT(14) +#define BIT_ATIMEND_E_MSK_8814B BIT(13) +#define BIT_ATIMEND__MSK_8814B BIT(12) +#define BIT_TXERR_MSK_8814B BIT(11) +#define BIT_RXERR_MSK_8814B BIT(10) +#define BIT_TXFOVW_MSK_8814B BIT(9) +#define BIT_FOVW_MSK_8814B BIT(8) +#define BIT_CPU_MGQ_TXDONE_MSK_8814B BIT(5) +#define BIT_PS_TIMER_C_MSK_8814B BIT(4) +#define BIT_PS_TIMER_B_MSK_8814B BIT(3) +#define BIT_PS_TIMER_A_MSK_8814B BIT(2) +#define BIT_CPUMGQ_TX_TIMER_MSK_8814B BIT(1) + +/* 2 REG_HISR1_8814B */ +#define BIT_TXFIFO_TH_INT_8814B BIT(30) +#define BIT_BTON_STS_UPDATE_INT_8814B BIT(29) +#define BIT_MCU_ERR_8814B BIT(28) +#define BIT_BCNDMAINT7_8814B BIT(27) +#define BIT_BCNDMAINT6_8814B BIT(26) +#define BIT_BCNDMAINT5_8814B BIT(25) +#define BIT_BCNDMAINT4_8814B BIT(24) +#define BIT_BCNDMAINT3_8814B BIT(23) +#define BIT_BCNDMAINT2_8814B BIT(22) +#define BIT_BCNDMAINT1_8814B BIT(21) +#define BIT_BCNDERR7_8814B BIT(20) +#define BIT_BCNDERR6_8814B BIT(19) +#define BIT_BCNDERR5_8814B BIT(18) +#define BIT_BCNDERR4_8814B BIT(17) +#define BIT_BCNDERR3_8814B BIT(16) +#define BIT_BCNDERR2_8814B BIT(15) +#define BIT_BCNDERR1_8814B BIT(14) +#define BIT_ATIMEND_E_8814B BIT(13) +#define BIT_ATIMEND_8814B BIT(12) +#define BIT_TXERR_INT_8814B BIT(11) +#define BIT_RXERR_INT_8814B BIT(10) +#define BIT_TXFOVW_8814B BIT(9) +#define BIT_FOVW_8814B BIT(8) + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CPU_MGQ_TXDONE_8814B BIT(5) +#define BIT_PS_TIMER_C_8814B BIT(4) +#define BIT_PS_TIMER_B_8814B BIT(3) +#define BIT_PS_TIMER_A_8814B BIT(2) +#define BIT_CPUMGQ_TX_TIMER_8814B BIT(1) + +/* 2 REG_DBG_PORT_SEL_8814B */ + +#define BIT_SHIFT_DEBUG_ST_8814B 0 +#define BIT_MASK_DEBUG_ST_8814B 0xffffffffL +#define BIT_DEBUG_ST_8814B(x) (((x) & BIT_MASK_DEBUG_ST_8814B) << BIT_SHIFT_DEBUG_ST_8814B) +#define BIT_GET_DEBUG_ST_8814B(x) (((x) >> BIT_SHIFT_DEBUG_ST_8814B) & BIT_MASK_DEBUG_ST_8814B) + + + +/* 2 REG_PAD_CTRL2_8814B */ +#define BIT_USB3_USB2_TRANSITION_8814B BIT(20) + +#define BIT_SHIFT_USB23_SW_MODE_V1_8814B 18 +#define BIT_MASK_USB23_SW_MODE_V1_8814B 0x3 +#define BIT_USB23_SW_MODE_V1_8814B(x) (((x) & BIT_MASK_USB23_SW_MODE_V1_8814B) << BIT_SHIFT_USB23_SW_MODE_V1_8814B) +#define BIT_GET_USB23_SW_MODE_V1_8814B(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8814B) & BIT_MASK_USB23_SW_MODE_V1_8814B) + + +#define BIT_NO_PDN_CHIPOFF_V1_8814B BIT(17) +#define BIT_RSM_EN_V1_8814B BIT(16) + +#define BIT_SHIFT_MATCH_CNT_8814B 8 +#define BIT_MASK_MATCH_CNT_8814B 0xff +#define BIT_MATCH_CNT_8814B(x) (((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B) +#define BIT_GET_MATCH_CNT_8814B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B) + + +#define BIT_LD_B12V_EN_8814B BIT(7) +#define BIT_EECS_IOSEL_V1_8814B BIT(6) +#define BIT_EECS_DATA_O_V1_8814B BIT(5) +#define BIT_EECS_DATA_I_V1_8814B BIT(4) +#define BIT_EESK_IOSEL_V1_8814B BIT(2) +#define BIT_EESK_DATA_O_V1_8814B BIT(1) +#define BIT_EESK_DATA_I_V1_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_PMC_DBG_CTRL2_8814B */ + +#define BIT_SHIFT_EFUSE_BURN_GNT_8814B 24 +#define BIT_MASK_EFUSE_BURN_GNT_8814B 0xff +#define BIT_EFUSE_BURN_GNT_8814B(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8814B) << BIT_SHIFT_EFUSE_BURN_GNT_8814B) +#define BIT_GET_EFUSE_BURN_GNT_8814B(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8814B) & BIT_MASK_EFUSE_BURN_GNT_8814B) + + +#define BIT_STOP_WL_PMC_8814B BIT(9) +#define BIT_STOP_SYM_PMC_8814B BIT(8) +#define BIT_BT_ACCESS_WL_PAGE0_8814B BIT(6) +#define BIT_REG_RST_WLPMC_8814B BIT(5) +#define BIT_REG_RST_PD12N_8814B BIT(4) +#define BIT_SYSON_DIS_WLREG_WRMSK_8814B BIT(3) +#define BIT_SYSON_DIS_PMCREG_WRMSK_8814B BIT(2) + +#define BIT_SHIFT_SYSON_REG_ARB_8814B 0 +#define BIT_MASK_SYSON_REG_ARB_8814B 0x3 +#define BIT_SYSON_REG_ARB_8814B(x) (((x) & BIT_MASK_SYSON_REG_ARB_8814B) << BIT_SHIFT_SYSON_REG_ARB_8814B) +#define BIT_GET_SYSON_REG_ARB_8814B(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8814B) & BIT_MASK_SYSON_REG_ARB_8814B) + + + +/* 2 REG_BIST_CTRL_8814B */ +#define BIT_BIST_USB_DIS_8814B BIT(27) +#define BIT_BIST_PCI_DIS_8814B BIT(26) +#define BIT_BIST_BT_DIS_8814B BIT(25) +#define BIT_BIST_WL_DIS_8814B BIT(24) + +#define BIT_SHIFT_BIST_RPT_SEL_8814B 16 +#define BIT_MASK_BIST_RPT_SEL_8814B 0xf +#define BIT_BIST_RPT_SEL_8814B(x) (((x) & BIT_MASK_BIST_RPT_SEL_8814B) << BIT_SHIFT_BIST_RPT_SEL_8814B) +#define BIT_GET_BIST_RPT_SEL_8814B(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8814B) & BIT_MASK_BIST_RPT_SEL_8814B) + + +#define BIT_BIST_RESUME_PS_8814B BIT(4) +#define BIT_BIST_RESUME_8814B BIT(3) +#define BIT_BIST_NORMAL_8814B BIT(2) +#define BIT_BIST_RSTN_8814B BIT(1) +#define BIT_BIST_CLK_EN_8814B BIT(0) + +/* 2 REG_BIST_RPT_8814B */ + +#define BIT_SHIFT_MBIST_REPORT_8814B 0 +#define BIT_MASK_MBIST_REPORT_8814B 0xffffffffL +#define BIT_MBIST_REPORT_8814B(x) (((x) & BIT_MASK_MBIST_REPORT_8814B) << BIT_SHIFT_MBIST_REPORT_8814B) +#define BIT_GET_MBIST_REPORT_8814B(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8814B) & BIT_MASK_MBIST_REPORT_8814B) + + + +/* 2 REG_MEM_CTRL_8814B */ +#define BIT_UMEM_RME_8814B BIT(31) + +#define BIT_SHIFT_BT_SPRAM_8814B 28 +#define BIT_MASK_BT_SPRAM_8814B 0x3 +#define BIT_BT_SPRAM_8814B(x) (((x) & BIT_MASK_BT_SPRAM_8814B) << BIT_SHIFT_BT_SPRAM_8814B) +#define BIT_GET_BT_SPRAM_8814B(x) (((x) >> BIT_SHIFT_BT_SPRAM_8814B) & BIT_MASK_BT_SPRAM_8814B) + + + +#define BIT_SHIFT_BT_ROM_8814B 24 +#define BIT_MASK_BT_ROM_8814B 0xf +#define BIT_BT_ROM_8814B(x) (((x) & BIT_MASK_BT_ROM_8814B) << BIT_SHIFT_BT_ROM_8814B) +#define BIT_GET_BT_ROM_8814B(x) (((x) >> BIT_SHIFT_BT_ROM_8814B) & BIT_MASK_BT_ROM_8814B) + + + +#define BIT_SHIFT_PCI_DPRAM_8814B 10 +#define BIT_MASK_PCI_DPRAM_8814B 0x3 +#define BIT_PCI_DPRAM_8814B(x) (((x) & BIT_MASK_PCI_DPRAM_8814B) << BIT_SHIFT_PCI_DPRAM_8814B) +#define BIT_GET_PCI_DPRAM_8814B(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8814B) & BIT_MASK_PCI_DPRAM_8814B) + + + +#define BIT_SHIFT_PCI_SPRAM_8814B 8 +#define BIT_MASK_PCI_SPRAM_8814B 0x3 +#define BIT_PCI_SPRAM_8814B(x) (((x) & BIT_MASK_PCI_SPRAM_8814B) << BIT_SHIFT_PCI_SPRAM_8814B) +#define BIT_GET_PCI_SPRAM_8814B(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8814B) & BIT_MASK_PCI_SPRAM_8814B) + + + +#define BIT_SHIFT_USB_SPRAM_8814B 6 +#define BIT_MASK_USB_SPRAM_8814B 0x3 +#define BIT_USB_SPRAM_8814B(x) (((x) & BIT_MASK_USB_SPRAM_8814B) << BIT_SHIFT_USB_SPRAM_8814B) +#define BIT_GET_USB_SPRAM_8814B(x) (((x) >> BIT_SHIFT_USB_SPRAM_8814B) & BIT_MASK_USB_SPRAM_8814B) + + + +#define BIT_SHIFT_USB_SPRF_8814B 4 +#define BIT_MASK_USB_SPRF_8814B 0x3 +#define BIT_USB_SPRF_8814B(x) (((x) & BIT_MASK_USB_SPRF_8814B) << BIT_SHIFT_USB_SPRF_8814B) +#define BIT_GET_USB_SPRF_8814B(x) (((x) >> BIT_SHIFT_USB_SPRF_8814B) & BIT_MASK_USB_SPRF_8814B) + + + +#define BIT_SHIFT_MCU_ROM_8814B 0 +#define BIT_MASK_MCU_ROM_8814B 0xf +#define BIT_MCU_ROM_8814B(x) (((x) & BIT_MASK_MCU_ROM_8814B) << BIT_SHIFT_MCU_ROM_8814B) +#define BIT_GET_MCU_ROM_8814B(x) (((x) >> BIT_SHIFT_MCU_ROM_8814B) & BIT_MASK_MCU_ROM_8814B) + + + +/* 2 REG_AFE_CTRL8_8814B */ +#define BIT_SYN_AGPIO_8814B BIT(20) +#define BIT_XTAL_LP_8814B BIT(4) +#define BIT_XTAL_GM_SEP_8814B BIT(3) + +#define BIT_SHIFT_XTAL_SEL_TOK_8814B 0 +#define BIT_MASK_XTAL_SEL_TOK_8814B 0x7 +#define BIT_XTAL_SEL_TOK_8814B(x) (((x) & BIT_MASK_XTAL_SEL_TOK_8814B) << BIT_SHIFT_XTAL_SEL_TOK_8814B) +#define BIT_GET_XTAL_SEL_TOK_8814B(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8814B) & BIT_MASK_XTAL_SEL_TOK_8814B) + + + +/* 2 REG_USB_SIE_INTF_8814B */ +#define BIT_RD_SEL_8814B BIT(31) +#define BIT_USB_SIE_INTF_WE_V1_8814B BIT(30) +#define BIT_USB_SIE_INTF_BYIOREG_V1_8814B BIT(29) +#define BIT_USB_SIE_SELECT_8814B BIT(28) + +#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B 16 +#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B 0x1ff +#define BIT_USB_SIE_INTF_ADDR_V1_8814B(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) +#define BIT_GET_USB_SIE_INTF_ADDR_V1_8814B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B) + + + +#define BIT_SHIFT_USB_SIE_INTF_RD_8814B 8 +#define BIT_MASK_USB_SIE_INTF_RD_8814B 0xff +#define BIT_USB_SIE_INTF_RD_8814B(x) (((x) & BIT_MASK_USB_SIE_INTF_RD_8814B) << BIT_SHIFT_USB_SIE_INTF_RD_8814B) +#define BIT_GET_USB_SIE_INTF_RD_8814B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8814B) & BIT_MASK_USB_SIE_INTF_RD_8814B) + + + +#define BIT_SHIFT_USB_SIE_INTF_WD_8814B 0 +#define BIT_MASK_USB_SIE_INTF_WD_8814B 0xff +#define BIT_USB_SIE_INTF_WD_8814B(x) (((x) & BIT_MASK_USB_SIE_INTF_WD_8814B) << BIT_SHIFT_USB_SIE_INTF_WD_8814B) +#define BIT_GET_USB_SIE_INTF_WD_8814B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8814B) & BIT_MASK_USB_SIE_INTF_WD_8814B) + + + +/* 2 REG_PCIE_MIO_INTF_8814B */ +#define BIT_PCIE_MIO_BYIOREG_8814B BIT(13) +#define BIT_PCIE_MIO_RE_8814B BIT(12) + +#define BIT_SHIFT_PCIE_MIO_WE_8814B 8 +#define BIT_MASK_PCIE_MIO_WE_8814B 0xf +#define BIT_PCIE_MIO_WE_8814B(x) (((x) & BIT_MASK_PCIE_MIO_WE_8814B) << BIT_SHIFT_PCIE_MIO_WE_8814B) +#define BIT_GET_PCIE_MIO_WE_8814B(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8814B) & BIT_MASK_PCIE_MIO_WE_8814B) + + + +#define BIT_SHIFT_PCIE_MIO_ADDR_8814B 0 +#define BIT_MASK_PCIE_MIO_ADDR_8814B 0xff +#define BIT_PCIE_MIO_ADDR_8814B(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8814B) << BIT_SHIFT_PCIE_MIO_ADDR_8814B) +#define BIT_GET_PCIE_MIO_ADDR_8814B(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8814B) & BIT_MASK_PCIE_MIO_ADDR_8814B) + + + +/* 2 REG_PCIE_MIO_INTD_8814B */ + +#define BIT_SHIFT_PCIE_MIO_DATA_8814B 0 +#define BIT_MASK_PCIE_MIO_DATA_8814B 0xffffffffL +#define BIT_PCIE_MIO_DATA_8814B(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8814B) << BIT_SHIFT_PCIE_MIO_DATA_8814B) +#define BIT_GET_PCIE_MIO_DATA_8814B(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8814B) & BIT_MASK_PCIE_MIO_DATA_8814B) + + + +/* 2 REG_WLRF1_8814B */ + +#define BIT_SHIFT_WLRF1_CTRL_8814B 24 +#define BIT_MASK_WLRF1_CTRL_8814B 0xff +#define BIT_WLRF1_CTRL_8814B(x) (((x) & BIT_MASK_WLRF1_CTRL_8814B) << BIT_SHIFT_WLRF1_CTRL_8814B) +#define BIT_GET_WLRF1_CTRL_8814B(x) (((x) >> BIT_SHIFT_WLRF1_CTRL_8814B) & BIT_MASK_WLRF1_CTRL_8814B) + + + +/* 2 REG_SYS_CFG1_8814B */ + +#define BIT_SHIFT_TRP_ICFG_8814B 28 +#define BIT_MASK_TRP_ICFG_8814B 0xf +#define BIT_TRP_ICFG_8814B(x) (((x) & BIT_MASK_TRP_ICFG_8814B) << BIT_SHIFT_TRP_ICFG_8814B) +#define BIT_GET_TRP_ICFG_8814B(x) (((x) >> BIT_SHIFT_TRP_ICFG_8814B) & BIT_MASK_TRP_ICFG_8814B) + + +#define BIT_RF_TYPE_ID_8814B BIT(27) +#define BIT_BD_HCI_SEL_8814B BIT(26) +#define BIT_BD_PKG_SEL_8814B BIT(25) +#define BIT_SPSLDO_SEL_8814B BIT(24) +#define BIT_RTL_ID_8814B BIT(23) +#define BIT_PAD_HWPD_IDN_8814B BIT(22) +#define BIT_TESTMODE_8814B BIT(20) + +#define BIT_SHIFT_VENDOR_ID_8814B 16 +#define BIT_MASK_VENDOR_ID_8814B 0xf +#define BIT_VENDOR_ID_8814B(x) (((x) & BIT_MASK_VENDOR_ID_8814B) << BIT_SHIFT_VENDOR_ID_8814B) +#define BIT_GET_VENDOR_ID_8814B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8814B) & BIT_MASK_VENDOR_ID_8814B) + + + +#define BIT_SHIFT_CHIP_VER_8814B 12 +#define BIT_MASK_CHIP_VER_8814B 0xf +#define BIT_CHIP_VER_8814B(x) (((x) & BIT_MASK_CHIP_VER_8814B) << BIT_SHIFT_CHIP_VER_8814B) +#define BIT_GET_CHIP_VER_8814B(x) (((x) >> BIT_SHIFT_CHIP_VER_8814B) & BIT_MASK_CHIP_VER_8814B) + + +#define BIT_BD_MAC3_8814B BIT(11) +#define BIT_BD_MAC1_8814B BIT(10) +#define BIT_BD_MAC2_8814B BIT(9) +#define BIT_SIC_IDLE_8814B BIT(8) +#define BIT_SW_OFFLOAD_EN_8814B BIT(7) +#define BIT_OCP_SHUTDN_8814B BIT(6) +#define BIT_V15_VLD_8814B BIT(5) +#define BIT_PCIRSTB_8814B BIT(4) +#define BIT_PCLK_VLD_8814B BIT(3) +#define BIT_UCLK_VLD_8814B BIT(2) +#define BIT_ACLK_VLD_8814B BIT(1) +#define BIT_XCLK_VLD_8814B BIT(0) + +/* 2 REG_SYS_STATUS1_8814B */ + +#define BIT_SHIFT_RF_RL_ID_8814B 28 +#define BIT_MASK_RF_RL_ID_8814B 0xf +#define BIT_RF_RL_ID_8814B(x) (((x) & BIT_MASK_RF_RL_ID_8814B) << BIT_SHIFT_RF_RL_ID_8814B) +#define BIT_GET_RF_RL_ID_8814B(x) (((x) >> BIT_SHIFT_RF_RL_ID_8814B) & BIT_MASK_RF_RL_ID_8814B) + + +#define BIT_HPHY_ICFG_8814B BIT(19) + +#define BIT_SHIFT_SEL_0XC0_8814B 16 +#define BIT_MASK_SEL_0XC0_8814B 0x3 +#define BIT_SEL_0XC0_8814B(x) (((x) & BIT_MASK_SEL_0XC0_8814B) << BIT_SHIFT_SEL_0XC0_8814B) +#define BIT_GET_SEL_0XC0_8814B(x) (((x) >> BIT_SHIFT_SEL_0XC0_8814B) & BIT_MASK_SEL_0XC0_8814B) + + +#define BIT_USB_OPERATION_MODE_8814B BIT(10) +#define BIT_BT_PDN_8814B BIT(9) +#define BIT_AUTO_WLPON_8814B BIT(8) +#define BIT_WL_MODE_8814B BIT(7) +#define BIT_PKG_SEL_HCI_8814B BIT(6) + +#define BIT_SHIFT_HCI_SEL_8814B 4 +#define BIT_MASK_HCI_SEL_8814B 0x3 +#define BIT_HCI_SEL_8814B(x) (((x) & BIT_MASK_HCI_SEL_8814B) << BIT_SHIFT_HCI_SEL_8814B) +#define BIT_GET_HCI_SEL_8814B(x) (((x) >> BIT_SHIFT_HCI_SEL_8814B) & BIT_MASK_HCI_SEL_8814B) + + + +#define BIT_SHIFT_PAD_HCI_SEL_8814B 2 +#define BIT_MASK_PAD_HCI_SEL_8814B 0x3 +#define BIT_PAD_HCI_SEL_8814B(x) (((x) & BIT_MASK_PAD_HCI_SEL_8814B) << BIT_SHIFT_PAD_HCI_SEL_8814B) +#define BIT_GET_PAD_HCI_SEL_8814B(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_8814B) & BIT_MASK_PAD_HCI_SEL_8814B) + + + +#define BIT_SHIFT_EFS_HCI_SEL_8814B 0 +#define BIT_MASK_EFS_HCI_SEL_8814B 0x3 +#define BIT_EFS_HCI_SEL_8814B(x) (((x) & BIT_MASK_EFS_HCI_SEL_8814B) << BIT_SHIFT_EFS_HCI_SEL_8814B) +#define BIT_GET_EFS_HCI_SEL_8814B(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_8814B) & BIT_MASK_EFS_HCI_SEL_8814B) + + + +/* 2 REG_SYS_STATUS2_8814B */ +#define BIT_SIO_ALDN_8814B BIT(19) +#define BIT_USB_ALDN_8814B BIT(18) +#define BIT_PCI_ALDN_8814B BIT(17) +#define BIT_SYS_ALDN_8814B BIT(16) + +#define BIT_SHIFT_EPVID1_8814B 8 +#define BIT_MASK_EPVID1_8814B 0xff +#define BIT_EPVID1_8814B(x) (((x) & BIT_MASK_EPVID1_8814B) << BIT_SHIFT_EPVID1_8814B) +#define BIT_GET_EPVID1_8814B(x) (((x) >> BIT_SHIFT_EPVID1_8814B) & BIT_MASK_EPVID1_8814B) + + + +#define BIT_SHIFT_EPVID0_8814B 0 +#define BIT_MASK_EPVID0_8814B 0xff +#define BIT_EPVID0_8814B(x) (((x) & BIT_MASK_EPVID0_8814B) << BIT_SHIFT_EPVID0_8814B) +#define BIT_GET_EPVID0_8814B(x) (((x) >> BIT_SHIFT_EPVID0_8814B) & BIT_MASK_EPVID0_8814B) + + + +/* 2 REG_SYS_CFG2_8814B */ +#define BIT_HCI_SEL_EMBEDED_8814B BIT(8) + +#define BIT_SHIFT_HW_ID_8814B 0 +#define BIT_MASK_HW_ID_8814B 0xff +#define BIT_HW_ID_8814B(x) (((x) & BIT_MASK_HW_ID_8814B) << BIT_SHIFT_HW_ID_8814B) +#define BIT_GET_HW_ID_8814B(x) (((x) >> BIT_SHIFT_HW_ID_8814B) & BIT_MASK_HW_ID_8814B) + + + +/* 2 REG_SYS_CFG3_8814B */ +#define BIT_PWC_MA33V_8814B BIT(15) +#define BIT_PWC_MA12V_8814B BIT(14) +#define BIT_PWC_MD12V_8814B BIT(13) +#define BIT_PWC_PD12V_8814B BIT(12) +#define BIT_PWC_UD12V_8814B BIT(11) +#define BIT_ISO_MA2MD_8814B BIT(1) +#define BIT_ISO_MD2PP_8814B BIT(0) + +/* 2 REG_SYS_CFG4_8814B */ + +/* 2 REG_SYS_CFG5_8814B */ +#define BIT_LPS_STATUS_8814B BIT(3) +#define BIT_HCI_TXDMA_BUSY_8814B BIT(2) +#define BIT_HCI_TXDMA_ALLOW_8814B BIT(1) +#define BIT_FW_CTRL_HCI_TXDMA_EN_8814B BIT(0) + +/* 2 REG_CPU_DMEM_CON_8814B */ +#define BIT_WDT_AUTO_MODE_8814B BIT(22) +#define BIT_WDT_PLATFORM_EN_8814B BIT(21) +#define BIT_WDT_CPU_EN_8814B BIT(20) +#define BIT_WDT_OPT_IOWRAPPER_8814B BIT(19) +#define BIT_ANA_PORT_IDLE_8814B BIT(18) +#define BIT_MAC_PORT_IDLE_8814B BIT(17) +#define BIT_WL_PLATFORM_RST_8814B BIT(16) +#define BIT_WL_SECURITY_CLK_8814B BIT(15) + +#define BIT_SHIFT_CPU_DMEM_CON_8814B 0 +#define BIT_MASK_CPU_DMEM_CON_8814B 0xff +#define BIT_CPU_DMEM_CON_8814B(x) (((x) & BIT_MASK_CPU_DMEM_CON_8814B) << BIT_SHIFT_CPU_DMEM_CON_8814B) +#define BIT_GET_CPU_DMEM_CON_8814B(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8814B) & BIT_MASK_CPU_DMEM_CON_8814B) + + + +/* 2 REG_BOOT_REASON_8814B */ + +#define BIT_SHIFT_BOOT_REASON_8814B 0 +#define BIT_MASK_BOOT_REASON_8814B 0x7 +#define BIT_BOOT_REASON_8814B(x) (((x) & BIT_MASK_BOOT_REASON_8814B) << BIT_SHIFT_BOOT_REASON_8814B) +#define BIT_GET_BOOT_REASON_8814B(x) (((x) >> BIT_SHIFT_BOOT_REASON_8814B) & BIT_MASK_BOOT_REASON_8814B) + + + +/* 2 REG_NFCPAD_CTRL_8814B */ +#define BIT_PAD_SHUTDW_8814B BIT(18) +#define BIT_SYSON_NFC_PAD_8814B BIT(17) +#define BIT_NFC_INT_PAD_CTRL_8814B BIT(16) +#define BIT_NFC_RFDIS_PAD_CTRL_8814B BIT(15) +#define BIT_NFC_CLK_PAD_CTRL_8814B BIT(14) +#define BIT_NFC_DATA_PAD_CTRL_8814B BIT(13) +#define BIT_NFC_PAD_PULL_CTRL_8814B BIT(12) + +#define BIT_SHIFT_NFCPAD_IO_SEL_8814B 8 +#define BIT_MASK_NFCPAD_IO_SEL_8814B 0xf +#define BIT_NFCPAD_IO_SEL_8814B(x) (((x) & BIT_MASK_NFCPAD_IO_SEL_8814B) << BIT_SHIFT_NFCPAD_IO_SEL_8814B) +#define BIT_GET_NFCPAD_IO_SEL_8814B(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8814B) & BIT_MASK_NFCPAD_IO_SEL_8814B) + + + +#define BIT_SHIFT_NFCPAD_OUT_8814B 4 +#define BIT_MASK_NFCPAD_OUT_8814B 0xf +#define BIT_NFCPAD_OUT_8814B(x) (((x) & BIT_MASK_NFCPAD_OUT_8814B) << BIT_SHIFT_NFCPAD_OUT_8814B) +#define BIT_GET_NFCPAD_OUT_8814B(x) (((x) >> BIT_SHIFT_NFCPAD_OUT_8814B) & BIT_MASK_NFCPAD_OUT_8814B) + + + +#define BIT_SHIFT_NFCPAD_IN_8814B 0 +#define BIT_MASK_NFCPAD_IN_8814B 0xf +#define BIT_NFCPAD_IN_8814B(x) (((x) & BIT_MASK_NFCPAD_IN_8814B) << BIT_SHIFT_NFCPAD_IN_8814B) +#define BIT_GET_NFCPAD_IN_8814B(x) (((x) >> BIT_SHIFT_NFCPAD_IN_8814B) & BIT_MASK_NFCPAD_IN_8814B) + + + +/* 2 REG_HIMR2_8814B */ +#define BIT_BCNDMAINT_P4_MSK_8814B BIT(31) +#define BIT_BCNDMAINT_P3_MSK_8814B BIT(30) +#define BIT_BCNDMAINT_P2_MSK_8814B BIT(29) +#define BIT_BCNDMAINT_P1_MSK_8814B BIT(28) +#define BIT_ATIMEND7_MSK_8814B BIT(22) +#define BIT_ATIMEND6_MSK_8814B BIT(21) +#define BIT_ATIMEND5_MSK_8814B BIT(20) +#define BIT_ATIMEND4_MSK_8814B BIT(19) +#define BIT_ATIMEND3_MSK_8814B BIT(18) +#define BIT_ATIMEND2_MSK_8814B BIT(17) +#define BIT_ATIMEND1_MSK_8814B BIT(16) +#define BIT_TXBCN7OK_MSK_8814B BIT(14) +#define BIT_TXBCN6OK_MSK_8814B BIT(13) +#define BIT_TXBCN5OK_MSK_8814B BIT(12) +#define BIT_TXBCN4OK_MSK_8814B BIT(11) +#define BIT_TXBCN3OK_MSK_8814B BIT(10) +#define BIT_TXBCN2OK_MSK_8814B BIT(9) +#define BIT_TXBCN1OK_MSK_V1_8814B BIT(8) +#define BIT_TXBCN7ERR_MSK_8814B BIT(6) +#define BIT_TXBCN6ERR_MSK_8814B BIT(5) +#define BIT_TXBCN5ERR_MSK_8814B BIT(4) +#define BIT_TXBCN4ERR_MSK_8814B BIT(3) +#define BIT_TXBCN3ERR_MSK_8814B BIT(2) +#define BIT_TXBCN2ERR_MSK_8814B BIT(1) +#define BIT_TXBCN1ERR_MSK_V1_8814B BIT(0) + +/* 2 REG_HISR2_8814B */ +#define BIT_BCNDMAINT_P4_8814B BIT(31) +#define BIT_BCNDMAINT_P3_8814B BIT(30) +#define BIT_BCNDMAINT_P2_8814B BIT(29) +#define BIT_BCNDMAINT_P1_8814B BIT(28) +#define BIT_ATIMEND7_8814B BIT(22) +#define BIT_ATIMEND6_8814B BIT(21) +#define BIT_ATIMEND5_8814B BIT(20) +#define BIT_ATIMEND4_8814B BIT(19) +#define BIT_ATIMEND3_8814B BIT(18) +#define BIT_ATIMEND2_8814B BIT(17) +#define BIT_ATIMEND1_8814B BIT(16) +#define BIT_TXBCN7OK_8814B BIT(14) +#define BIT_TXBCN6OK_8814B BIT(13) +#define BIT_TXBCN5OK_8814B BIT(12) +#define BIT_TXBCN4OK_8814B BIT(11) +#define BIT_TXBCN3OK_8814B BIT(10) +#define BIT_TXBCN2OK_8814B BIT(9) +#define BIT_TXBCN1OK_8814B BIT(8) +#define BIT_TXBCN7ERR_8814B BIT(6) +#define BIT_TXBCN6ERR_8814B BIT(5) +#define BIT_TXBCN5ERR_8814B BIT(4) +#define BIT_TXBCN4ERR_8814B BIT(3) +#define BIT_TXBCN3ERR_8814B BIT(2) +#define BIT_TXBCN2ERR_8814B BIT(1) +#define BIT_TXBCN1ERR_8814B BIT(0) + +/* 2 REG_HIMR3_8814B */ +#define BIT_WDT_PLATFORM_INT_MSK_8814B BIT(18) +#define BIT_WDT_CPU_INT_MSK_8814B BIT(17) +#define BIT_SETH2CDOK_MASK_8814B BIT(16) +#define BIT_H2C_CMD_FULL_MASK_8814B BIT(15) +#define BIT_PWR_INT_127_MASK_8814B BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8814B BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8814B BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8814B BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8814B BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8814B BIT(9) +#define BIT_PWR_INT_127_MASK_V1_8814B BIT(8) +#define BIT_PWR_INT_126TO96_MASK_8814B BIT(7) +#define BIT_PWR_INT_95TO64_MASK_8814B BIT(6) +#define BIT_PWR_INT_63TO32_MASK_8814B BIT(5) +#define BIT_PWR_INT_31TO0_MASK_8814B BIT(4) +#define BIT_DDMA0_LP_INT_MSK_8814B BIT(1) +#define BIT_DDMA0_HP_INT_MSK_8814B BIT(0) + +/* 2 REG_HISR3_8814B */ +#define BIT_WDT_PLATFORM_INT_8814B BIT(18) +#define BIT_WDT_CPU_INT_8814B BIT(17) +#define BIT_SETH2CDOK_8814B BIT(16) +#define BIT_H2C_CMD_FULL_8814B BIT(15) +#define BIT_PWR_INT_127_8814B BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_8814B BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_8814B BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_8814B BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_8814B BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_8814B BIT(9) +#define BIT_PWR_INT_127_V1_8814B BIT(8) +#define BIT_PWR_INT_126TO96_8814B BIT(7) +#define BIT_PWR_INT_95TO64_8814B BIT(6) +#define BIT_PWR_INT_63TO32_8814B BIT(5) +#define BIT_PWR_INT_31TO0_8814B BIT(4) +#define BIT_DDMA0_LP_INT_8814B BIT(1) +#define BIT_DDMA0_HP_INT_8814B BIT(0) + +/* 2 REG_SW_MDIO_8814B */ +#define BIT_DIS_TIMEOUT_IO_8814B BIT(24) + +/* 2 REG_SW_FLUSH_8814B */ +#define BIT_FLUSH_HOLDN_EN_8814B BIT(25) +#define BIT_FLUSH_WR_EN_8814B BIT(24) +#define BIT_SW_FLASH_CONTROL_8814B BIT(23) +#define BIT_SW_FLASH_WEN_E_8814B BIT(19) +#define BIT_SW_FLASH_HOLDN_E_8814B BIT(18) +#define BIT_SW_FLASH_SO_E_8814B BIT(17) +#define BIT_SW_FLASH_SI_E_8814B BIT(16) +#define BIT_SW_FLASH_SK_O_8814B BIT(13) +#define BIT_SW_FLASH_CEN_O_8814B BIT(12) +#define BIT_SW_FLASH_WEN_O_8814B BIT(11) +#define BIT_SW_FLASH_HOLDN_O_8814B BIT(10) +#define BIT_SW_FLASH_SO_O_8814B BIT(9) +#define BIT_SW_FLASH_SI_O_8814B BIT(8) +#define BIT_SW_FLASH_WEN_I_8814B BIT(3) +#define BIT_SW_FLASH_HOLDN_I_8814B BIT(2) +#define BIT_SW_FLASH_SO_I_8814B BIT(1) +#define BIT_SW_FLASH_SI_I_8814B BIT(0) + +/* 2 REG_H2C_PKT_READADDR_8814B */ + +#define BIT_SHIFT_H2C_PKT_READADDR_8814B 0 +#define BIT_MASK_H2C_PKT_READADDR_8814B 0x3ffff +#define BIT_H2C_PKT_READADDR_8814B(x) (((x) & BIT_MASK_H2C_PKT_READADDR_8814B) << BIT_SHIFT_H2C_PKT_READADDR_8814B) +#define BIT_GET_H2C_PKT_READADDR_8814B(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8814B) & BIT_MASK_H2C_PKT_READADDR_8814B) + + + +/* 2 REG_H2C_PKT_WRITEADDR_8814B */ + +#define BIT_SHIFT_H2C_PKT_WRITEADDR_8814B 0 +#define BIT_MASK_H2C_PKT_WRITEADDR_8814B 0x3ffff +#define BIT_H2C_PKT_WRITEADDR_8814B(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8814B) << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) +#define BIT_GET_H2C_PKT_WRITEADDR_8814B(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) & BIT_MASK_H2C_PKT_WRITEADDR_8814B) + + + +/* 2 REG_MEM_PWR_CRTL_8814B */ +#define BIT_MEM_BB_SD_8814B BIT(17) +#define BIT_MEM_BB_DS_8814B BIT(16) +#define BIT_MEM_BT_DS_8814B BIT(10) +#define BIT_MEM_SDIO_LS_8814B BIT(9) +#define BIT_MEM_SDIO_DS_8814B BIT(8) +#define BIT_MEM_USB_LS_8814B BIT(7) +#define BIT_MEM_USB_DS_8814B BIT(6) +#define BIT_MEM_PCI_LS_8814B BIT(5) +#define BIT_MEM_PCI_DS_8814B BIT(4) +#define BIT_MEM_WLMAC_LS_8814B BIT(3) +#define BIT_MEM_WLMAC_DS_8814B BIT(2) +#define BIT_MEM_WLMCU_LS_8814B BIT(1) +#define BIT_MEM_WLMCU_DS_8814B BIT(0) + +/* 2 REG_FW_DBG0_8814B */ + +#define BIT_SHIFT_FW_DBG0_8814B 0 +#define BIT_MASK_FW_DBG0_8814B 0xffffffffL +#define BIT_FW_DBG0_8814B(x) (((x) & BIT_MASK_FW_DBG0_8814B) << BIT_SHIFT_FW_DBG0_8814B) +#define BIT_GET_FW_DBG0_8814B(x) (((x) >> BIT_SHIFT_FW_DBG0_8814B) & BIT_MASK_FW_DBG0_8814B) + + + +/* 2 REG_FW_DBG1_8814B */ + +#define BIT_SHIFT_FW_DBG1_8814B 0 +#define BIT_MASK_FW_DBG1_8814B 0xffffffffL +#define BIT_FW_DBG1_8814B(x) (((x) & BIT_MASK_FW_DBG1_8814B) << BIT_SHIFT_FW_DBG1_8814B) +#define BIT_GET_FW_DBG1_8814B(x) (((x) >> BIT_SHIFT_FW_DBG1_8814B) & BIT_MASK_FW_DBG1_8814B) + + + +/* 2 REG_FW_DBG2_8814B */ + +#define BIT_SHIFT_FW_DBG2_8814B 0 +#define BIT_MASK_FW_DBG2_8814B 0xffffffffL +#define BIT_FW_DBG2_8814B(x) (((x) & BIT_MASK_FW_DBG2_8814B) << BIT_SHIFT_FW_DBG2_8814B) +#define BIT_GET_FW_DBG2_8814B(x) (((x) >> BIT_SHIFT_FW_DBG2_8814B) & BIT_MASK_FW_DBG2_8814B) + + + +/* 2 REG_FW_DBG3_8814B */ + +#define BIT_SHIFT_FW_DBG3_8814B 0 +#define BIT_MASK_FW_DBG3_8814B 0xffffffffL +#define BIT_FW_DBG3_8814B(x) (((x) & BIT_MASK_FW_DBG3_8814B) << BIT_SHIFT_FW_DBG3_8814B) +#define BIT_GET_FW_DBG3_8814B(x) (((x) >> BIT_SHIFT_FW_DBG3_8814B) & BIT_MASK_FW_DBG3_8814B) + + + +/* 2 REG_FW_DBG4_8814B */ + +#define BIT_SHIFT_FW_DBG4_8814B 0 +#define BIT_MASK_FW_DBG4_8814B 0xffffffffL +#define BIT_FW_DBG4_8814B(x) (((x) & BIT_MASK_FW_DBG4_8814B) << BIT_SHIFT_FW_DBG4_8814B) +#define BIT_GET_FW_DBG4_8814B(x) (((x) >> BIT_SHIFT_FW_DBG4_8814B) & BIT_MASK_FW_DBG4_8814B) + + + +/* 2 REG_FW_DBG5_8814B */ + +#define BIT_SHIFT_FW_DBG5_8814B 0 +#define BIT_MASK_FW_DBG5_8814B 0xffffffffL +#define BIT_FW_DBG5_8814B(x) (((x) & BIT_MASK_FW_DBG5_8814B) << BIT_SHIFT_FW_DBG5_8814B) +#define BIT_GET_FW_DBG5_8814B(x) (((x) >> BIT_SHIFT_FW_DBG5_8814B) & BIT_MASK_FW_DBG5_8814B) + + + +/* 2 REG_FW_DBG6_8814B */ + +#define BIT_SHIFT_FW_DBG6_8814B 0 +#define BIT_MASK_FW_DBG6_8814B 0xffffffffL +#define BIT_FW_DBG6_8814B(x) (((x) & BIT_MASK_FW_DBG6_8814B) << BIT_SHIFT_FW_DBG6_8814B) +#define BIT_GET_FW_DBG6_8814B(x) (((x) >> BIT_SHIFT_FW_DBG6_8814B) & BIT_MASK_FW_DBG6_8814B) + + + +/* 2 REG_FW_DBG7_8814B */ + +#define BIT_SHIFT_FW_DBG7_8814B 0 +#define BIT_MASK_FW_DBG7_8814B 0xffffffffL +#define BIT_FW_DBG7_8814B(x) (((x) & BIT_MASK_FW_DBG7_8814B) << BIT_SHIFT_FW_DBG7_8814B) +#define BIT_GET_FW_DBG7_8814B(x) (((x) >> BIT_SHIFT_FW_DBG7_8814B) & BIT_MASK_FW_DBG7_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_CR_8814B */ + +#define BIT_SHIFT_LBMODE_8814B 24 +#define BIT_MASK_LBMODE_8814B 0x1f +#define BIT_LBMODE_8814B(x) (((x) & BIT_MASK_LBMODE_8814B) << BIT_SHIFT_LBMODE_8814B) +#define BIT_GET_LBMODE_8814B(x) (((x) >> BIT_SHIFT_LBMODE_8814B) & BIT_MASK_LBMODE_8814B) + + + +#define BIT_SHIFT_NETYPE1_8814B 18 +#define BIT_MASK_NETYPE1_8814B 0x3 +#define BIT_NETYPE1_8814B(x) (((x) & BIT_MASK_NETYPE1_8814B) << BIT_SHIFT_NETYPE1_8814B) +#define BIT_GET_NETYPE1_8814B(x) (((x) >> BIT_SHIFT_NETYPE1_8814B) & BIT_MASK_NETYPE1_8814B) + + + +#define BIT_SHIFT_NETYPE0_8814B 16 +#define BIT_MASK_NETYPE0_8814B 0x3 +#define BIT_NETYPE0_8814B(x) (((x) & BIT_MASK_NETYPE0_8814B) << BIT_SHIFT_NETYPE0_8814B) +#define BIT_GET_NETYPE0_8814B(x) (((x) >> BIT_SHIFT_NETYPE0_8814B) & BIT_MASK_NETYPE0_8814B) + + +#define BIT_I2C_MAILBOX_EN_8814B BIT(12) +#define BIT_SHCUT_EN_8814B BIT(11) +#define BIT_32K_CAL_TMR_EN_8814B BIT(10) +#define BIT_MAC_SEC_EN_8814B BIT(9) +#define BIT_ENSWBCN_8814B BIT(8) +#define BIT_MACRXEN_8814B BIT(7) +#define BIT_MACTXEN_8814B BIT(6) +#define BIT_SCHEDULE_EN_8814B BIT(5) +#define BIT_PROTOCOL_EN_8814B BIT(4) +#define BIT_RXDMA_EN_8814B BIT(3) +#define BIT_TXDMA_EN_8814B BIT(2) +#define BIT_HCI_RXDMA_EN_8814B BIT(1) +#define BIT_HCI_TXDMA_EN_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_PKT_BUFF_ACCESS_CTRL_8814B */ + +#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B 0 +#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B 0xff +#define BIT_PKT_BUFF_ACCESS_CTRL_8814B(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) +#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8814B(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B) + + + +/* 2 REG_TSF_CLK_STATE_8814B */ +#define BIT_TSF_CLK_STABLE_8814B BIT(15) + +/* 2 REG_TXDMA_PQ_MAP_8814B */ + +#define BIT_SHIFT_TXDMA_HIQ_MAP_8814B 14 +#define BIT_MASK_TXDMA_HIQ_MAP_8814B 0x3 +#define BIT_TXDMA_HIQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8814B) << BIT_SHIFT_TXDMA_HIQ_MAP_8814B) +#define BIT_GET_TXDMA_HIQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8814B) & BIT_MASK_TXDMA_HIQ_MAP_8814B) + + + +#define BIT_SHIFT_TXDMA_MGQ_MAP_8814B 12 +#define BIT_MASK_TXDMA_MGQ_MAP_8814B 0x3 +#define BIT_TXDMA_MGQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8814B) << BIT_SHIFT_TXDMA_MGQ_MAP_8814B) +#define BIT_GET_TXDMA_MGQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8814B) & BIT_MASK_TXDMA_MGQ_MAP_8814B) + + + +#define BIT_SHIFT_TXDMA_BKQ_MAP_8814B 10 +#define BIT_MASK_TXDMA_BKQ_MAP_8814B 0x3 +#define BIT_TXDMA_BKQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8814B) << BIT_SHIFT_TXDMA_BKQ_MAP_8814B) +#define BIT_GET_TXDMA_BKQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8814B) & BIT_MASK_TXDMA_BKQ_MAP_8814B) + + + +#define BIT_SHIFT_TXDMA_BEQ_MAP_8814B 8 +#define BIT_MASK_TXDMA_BEQ_MAP_8814B 0x3 +#define BIT_TXDMA_BEQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8814B) << BIT_SHIFT_TXDMA_BEQ_MAP_8814B) +#define BIT_GET_TXDMA_BEQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8814B) & BIT_MASK_TXDMA_BEQ_MAP_8814B) + + + +#define BIT_SHIFT_TXDMA_VIQ_MAP_8814B 6 +#define BIT_MASK_TXDMA_VIQ_MAP_8814B 0x3 +#define BIT_TXDMA_VIQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8814B) << BIT_SHIFT_TXDMA_VIQ_MAP_8814B) +#define BIT_GET_TXDMA_VIQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8814B) & BIT_MASK_TXDMA_VIQ_MAP_8814B) + + + +#define BIT_SHIFT_TXDMA_VOQ_MAP_8814B 4 +#define BIT_MASK_TXDMA_VOQ_MAP_8814B 0x3 +#define BIT_TXDMA_VOQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8814B) << BIT_SHIFT_TXDMA_VOQ_MAP_8814B) +#define BIT_GET_TXDMA_VOQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8814B) & BIT_MASK_TXDMA_VOQ_MAP_8814B) + + +#define BIT_RXDMA_AGG_EN_8814B BIT(2) +#define BIT_RXSHFT_EN_8814B BIT(1) +#define BIT_RXDMA_ARBBW_EN_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_TRXFF_BNDY_8814B */ + +#define BIT_SHIFT_RXFFOVFL_RSV_V2_8814B 8 +#define BIT_MASK_RXFFOVFL_RSV_V2_8814B 0xf +#define BIT_RXFFOVFL_RSV_V2_8814B(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8814B) << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) +#define BIT_GET_RXFFOVFL_RSV_V2_8814B(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) & BIT_MASK_RXFFOVFL_RSV_V2_8814B) + + + +#define BIT_SHIFT_TXPKTBUF_PGBNDY_8814B 0 +#define BIT_MASK_TXPKTBUF_PGBNDY_8814B 0xff +#define BIT_TXPKTBUF_PGBNDY_8814B(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8814B) << BIT_SHIFT_TXPKTBUF_PGBNDY_8814B) +#define BIT_GET_TXPKTBUF_PGBNDY_8814B(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8814B) & BIT_MASK_TXPKTBUF_PGBNDY_8814B) + + + +/* 2 REG_PTA_I2C_MBOX_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_I2C_M_STATUS_8814B 8 +#define BIT_MASK_I2C_M_STATUS_8814B 0xf +#define BIT_I2C_M_STATUS_8814B(x) (((x) & BIT_MASK_I2C_M_STATUS_8814B) << BIT_SHIFT_I2C_M_STATUS_8814B) +#define BIT_GET_I2C_M_STATUS_8814B(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8814B) & BIT_MASK_I2C_M_STATUS_8814B) + + + +#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B 4 +#define BIT_MASK_I2C_M_BUS_GNT_FW_8814B 0x7 +#define BIT_I2C_M_BUS_GNT_FW_8814B(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8814B) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) +#define BIT_GET_I2C_M_BUS_GNT_FW_8814B(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) & BIT_MASK_I2C_M_BUS_GNT_FW_8814B) + + +#define BIT_I2C_M_GNT_FW_8814B BIT(3) + +#define BIT_SHIFT_I2C_M_SPEED_8814B 1 +#define BIT_MASK_I2C_M_SPEED_8814B 0x3 +#define BIT_I2C_M_SPEED_8814B(x) (((x) & BIT_MASK_I2C_M_SPEED_8814B) << BIT_SHIFT_I2C_M_SPEED_8814B) +#define BIT_GET_I2C_M_SPEED_8814B(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8814B) & BIT_MASK_I2C_M_SPEED_8814B) + + +#define BIT_I2C_M_UNLOCK_8814B BIT(0) + +/* 2 REG_RXFF_BNDY_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_RXFF0_BNDY_V2_8814B 0 +#define BIT_MASK_RXFF0_BNDY_V2_8814B 0x3ffff +#define BIT_RXFF0_BNDY_V2_8814B(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8814B) << BIT_SHIFT_RXFF0_BNDY_V2_8814B) +#define BIT_GET_RXFF0_BNDY_V2_8814B(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8814B) & BIT_MASK_RXFF0_BNDY_V2_8814B) + + + +/* 2 REG_FE1IMR_8814B */ +#define BIT_FS_RXDMA2_DONE_INT_EN_8814B BIT(28) +#define BIT_FS_RXDONE3_INT_EN_8814B BIT(27) +#define BIT_FS_RXDONE2_INT_EN_8814B BIT(26) +#define BIT_FS_RX_BCN_P4_INT_EN_8814B BIT(25) +#define BIT_FS_RX_BCN_P3_INT_EN_8814B BIT(24) +#define BIT_FS_RX_BCN_P2_INT_EN_8814B BIT(23) +#define BIT_FS_RX_BCN_P1_INT_EN_8814B BIT(22) +#define BIT_FS_RX_BCN_P0_INT_EN_8814B BIT(21) +#define BIT_FS_RX_UMD0_INT_EN_8814B BIT(20) +#define BIT_FS_RX_UMD1_INT_EN_8814B BIT(19) +#define BIT_FS_RX_BMD0_INT_EN_8814B BIT(18) +#define BIT_FS_RX_BMD1_INT_EN_8814B BIT(17) +#define BIT_FS_RXDONE_INT_EN_8814B BIT(16) +#define BIT_FS_WWLAN_INT_EN_8814B BIT(15) +#define BIT_FS_SOUND_DONE_INT_EN_8814B BIT(14) +#define BIT_FS_LP_STBY_INT_EN_8814B BIT(13) +#define BIT_FS_TRL_MTR_INT_EN_8814B BIT(12) +#define BIT_FS_BF1_PRETO_INT_EN_8814B BIT(11) +#define BIT_FS_BF0_PRETO_INT_EN_8814B BIT(10) +#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8814B BIT(9) +#define BIT_FS_LTE_COEX_EN_8814B BIT(6) +#define BIT_FS_WLACTOFF_INT_EN_8814B BIT(5) +#define BIT_FS_WLACTON_INT_EN_8814B BIT(4) +#define BIT_FS_BTCMD_INT_EN_8814B BIT(3) +#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8814B BIT(2) +#define BIT_FS_TRPC_TO_INT_EN_V1_8814B BIT(1) +#define BIT_FS_RPC_O_T_INT_EN_V1_8814B BIT(0) + +/* 2 REG_FE1ISR_8814B */ +#define BIT_FS_RXDMA2_DONE_INT_8814B BIT(28) +#define BIT_FS_RXDONE3_INT_8814B BIT(27) +#define BIT_FS_RXDONE2_INT_8814B BIT(26) +#define BIT_FS_RX_BCN_P4_INT_8814B BIT(25) +#define BIT_FS_RX_BCN_P3_INT_8814B BIT(24) +#define BIT_FS_RX_BCN_P2_INT_8814B BIT(23) +#define BIT_FS_RX_BCN_P1_INT_8814B BIT(22) +#define BIT_FS_RX_BCN_P0_INT_8814B BIT(21) +#define BIT_FS_RX_UMD0_INT_8814B BIT(20) +#define BIT_FS_RX_UMD1_INT_8814B BIT(19) +#define BIT_FS_RX_BMD0_INT_8814B BIT(18) +#define BIT_FS_RX_BMD1_INT_8814B BIT(17) +#define BIT_FS_RXDONE_INT_8814B BIT(16) +#define BIT_FS_WWLAN_INT_8814B BIT(15) +#define BIT_FS_SOUND_DONE_INT_8814B BIT(14) +#define BIT_FS_LP_STBY_INT_8814B BIT(13) +#define BIT_FS_TRL_MTR_INT_8814B BIT(12) +#define BIT_FS_BF1_PRETO_INT_8814B BIT(11) +#define BIT_FS_BF0_PRETO_INT_8814B BIT(10) +#define BIT_FS_PTCL_RELEASE_MACID_INT_8814B BIT(9) +#define BIT_FS_LTE_COEX_INT_8814B BIT(6) +#define BIT_FS_WLACTOFF_INT_8814B BIT(5) +#define BIT_FS_WLACTON_INT_8814B BIT(4) +#define BIT_FS_BCN_RX_INT_INT_8814B BIT(3) +#define BIT_FS_MAILBOX_TO_I2C_INT_8814B BIT(2) +#define BIT_FS_TRPC_TO_INT_8814B BIT(1) +#define BIT_FS_RPC_O_T_INT_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_CPWM_8814B */ +#define BIT_CPWM_TOGGLING_8814B BIT(31) + +#define BIT_SHIFT_CPWM_MOD_8814B 24 +#define BIT_MASK_CPWM_MOD_8814B 0x7f +#define BIT_CPWM_MOD_8814B(x) (((x) & BIT_MASK_CPWM_MOD_8814B) << BIT_SHIFT_CPWM_MOD_8814B) +#define BIT_GET_CPWM_MOD_8814B(x) (((x) >> BIT_SHIFT_CPWM_MOD_8814B) & BIT_MASK_CPWM_MOD_8814B) + + + +/* 2 REG_FWIMR_8814B */ +#define BIT_FS_TXBCNOK_MB7_INT_EN_8814B BIT(31) +#define BIT_FS_TXBCNOK_MB6_INT_EN_8814B BIT(30) +#define BIT_FS_TXBCNOK_MB5_INT_EN_8814B BIT(29) +#define BIT_FS_TXBCNOK_MB4_INT_EN_8814B BIT(28) +#define BIT_FS_TXBCNOK_MB3_INT_EN_8814B BIT(27) +#define BIT_FS_TXBCNOK_MB2_INT_EN_8814B BIT(26) +#define BIT_FS_TXBCNOK_MB1_INT_EN_8814B BIT(25) +#define BIT_FS_TXBCNOK_MB0_INT_EN_8814B BIT(24) +#define BIT_FS_TXBCNERR_MB7_INT_EN_8814B BIT(23) +#define BIT_FS_TXBCNERR_MB6_INT_EN_8814B BIT(22) +#define BIT_FS_TXBCNERR_MB5_INT_EN_8814B BIT(21) +#define BIT_FS_TXBCNERR_MB4_INT_EN_8814B BIT(20) +#define BIT_FS_TXBCNERR_MB3_INT_EN_8814B BIT(19) +#define BIT_FS_TXBCNERR_MB2_INT_EN_8814B BIT(18) +#define BIT_FS_TXBCNERR_MB1_INT_EN_8814B BIT(17) +#define BIT_FS_TXBCNERR_MB0_INT_EN_8814B BIT(16) +#define BIT_CPU_MGQ_TXDONE_INT_EN_8814B BIT(15) +#define BIT_SIFS_OVERSPEC_INT_EN_8814B BIT(14) +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8814B BIT(13) +#define BIT_FS_MGNTQFF_TO_INT_EN_8814B BIT(12) +#define BIT_FS_DDMA1_LP_INT_EN_8814B BIT(11) +#define BIT_FS_DDMA1_HP_INT_EN_8814B BIT(10) +#define BIT_FS_DDMA0_LP_INT_EN_8814B BIT(9) +#define BIT_FS_DDMA0_HP_INT_EN_8814B BIT(8) +#define BIT_FS_TRXRPT_INT_EN_8814B BIT(7) +#define BIT_FS_C2H_W_READY_INT_EN_8814B BIT(6) +#define BIT_FS_HRCV_INT_EN_8814B BIT(5) +#define BIT_FS_H2CCMD_INT_EN_8814B BIT(4) +#define BIT_FS_TXPKTIN_INT_EN_8814B BIT(3) +#define BIT_FS_ERRORHDL_INT_EN_8814B BIT(2) +#define BIT_FS_TXCCX_INT_EN_8814B BIT(1) +#define BIT_FS_TXCLOSE_INT_EN_8814B BIT(0) + +/* 2 REG_FWISR_8814B */ +#define BIT_FS_TXBCNOK_MB7_INT_8814B BIT(31) +#define BIT_FS_TXBCNOK_MB6_INT_8814B BIT(30) +#define BIT_FS_TXBCNOK_MB5_INT_8814B BIT(29) +#define BIT_FS_TXBCNOK_MB4_INT_8814B BIT(28) +#define BIT_FS_TXBCNOK_MB3_INT_8814B BIT(27) +#define BIT_FS_TXBCNOK_MB2_INT_8814B BIT(26) +#define BIT_FS_TXBCNOK_MB1_INT_8814B BIT(25) +#define BIT_FS_TXBCNOK_MB0_INT_8814B BIT(24) +#define BIT_FS_TXBCNERR_MB7_INT_8814B BIT(23) +#define BIT_FS_TXBCNERR_MB6_INT_8814B BIT(22) +#define BIT_FS_TXBCNERR_MB5_INT_8814B BIT(21) +#define BIT_FS_TXBCNERR_MB4_INT_8814B BIT(20) +#define BIT_FS_TXBCNERR_MB3_INT_8814B BIT(19) +#define BIT_FS_TXBCNERR_MB2_INT_8814B BIT(18) +#define BIT_FS_TXBCNERR_MB1_INT_8814B BIT(17) +#define BIT_FS_TXBCNERR_MB0_INT_8814B BIT(16) +#define BIT_CPU_MGQ_TXDONE_INT_8814B BIT(15) +#define BIT_SIFS_OVERSPEC_INT_8814B BIT(14) +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8814B BIT(13) +#define BIT_FS_MGNTQFF_TO_INT_8814B BIT(12) +#define BIT_FS_DDMA1_LP_INT_8814B BIT(11) +#define BIT_FS_DDMA1_HP_INT_8814B BIT(10) +#define BIT_FS_DDMA0_LP_INT_8814B BIT(9) +#define BIT_FS_DDMA0_HP_INT_8814B BIT(8) +#define BIT_FS_TRXRPT_INT_8814B BIT(7) +#define BIT_FS_C2H_W_READY_INT_8814B BIT(6) +#define BIT_FS_HRCV_INT_8814B BIT(5) +#define BIT_FS_H2CCMD_INT_8814B BIT(4) +#define BIT_FS_TXPKTIN_INT_8814B BIT(3) +#define BIT_FS_ERRORHDL_INT_8814B BIT(2) +#define BIT_FS_TXCCX_INT_8814B BIT(1) +#define BIT_FS_TXCLOSE_INT_8814B BIT(0) + +/* 2 REG_FTIMR_8814B */ +#define BIT_PS_TIMER_C_EARLY_INT_EN_8814B BIT(23) +#define BIT_PS_TIMER_B_EARLY_INT_EN_8814B BIT(22) +#define BIT_PS_TIMER_A_EARLY_INT_EN_8814B BIT(21) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8814B BIT(20) +#define BIT_PS_TIMER_C_INT_EN_8814B BIT(19) +#define BIT_PS_TIMER_B_INT_EN_8814B BIT(18) +#define BIT_PS_TIMER_A_INT_EN_8814B BIT(17) +#define BIT_CPUMGQ_TX_TIMER_INT_EN_8814B BIT(16) +#define BIT_FS_PS_TIMEOUT2_EN_8814B BIT(15) +#define BIT_FS_PS_TIMEOUT1_EN_8814B BIT(14) +#define BIT_FS_PS_TIMEOUT0_EN_8814B BIT(13) +#define BIT_FS_GTINT8_EN_8814B BIT(8) +#define BIT_FS_GTINT7_EN_8814B BIT(7) +#define BIT_FS_GTINT6_EN_8814B BIT(6) +#define BIT_FS_GTINT5_EN_8814B BIT(5) +#define BIT_FS_GTINT4_EN_8814B BIT(4) +#define BIT_FS_GTINT3_EN_8814B BIT(3) +#define BIT_FS_GTINT2_EN_8814B BIT(2) +#define BIT_FS_GTINT1_EN_8814B BIT(1) +#define BIT_FS_GTINT0_EN_8814B BIT(0) + +/* 2 REG_FTISR_8814B */ +#define BIT_PS_TIMER_C_EARLY__INT_8814B BIT(23) +#define BIT_PS_TIMER_B_EARLY__INT_8814B BIT(22) +#define BIT_PS_TIMER_A_EARLY__INT_8814B BIT(21) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8814B BIT(20) +#define BIT_PS_TIMER_C_INT_8814B BIT(19) +#define BIT_PS_TIMER_B_INT_8814B BIT(18) +#define BIT_PS_TIMER_A_INT_8814B BIT(17) +#define BIT_CPUMGQ_TX_TIMER_INT_8814B BIT(16) +#define BIT_FS_PS_TIMEOUT2_INT_8814B BIT(15) +#define BIT_FS_PS_TIMEOUT1_INT_8814B BIT(14) +#define BIT_FS_PS_TIMEOUT0_INT_8814B BIT(13) +#define BIT_FS_GTINT8_INT_8814B BIT(8) +#define BIT_FS_GTINT7_INT_8814B BIT(7) +#define BIT_FS_GTINT6_INT_8814B BIT(6) +#define BIT_FS_GTINT5_INT_8814B BIT(5) +#define BIT_FS_GTINT4_INT_8814B BIT(4) +#define BIT_FS_GTINT3_INT_8814B BIT(3) +#define BIT_FS_GTINT2_INT_8814B BIT(2) +#define BIT_FS_GTINT1_INT_8814B BIT(1) +#define BIT_FS_GTINT0_INT_8814B BIT(0) + +/* 2 REG_PKTBUF_DBG_CTRL_8814B */ + +#define BIT_SHIFT_PKTBUF_WRITE_EN_8814B 24 +#define BIT_MASK_PKTBUF_WRITE_EN_8814B 0xff +#define BIT_PKTBUF_WRITE_EN_8814B(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8814B) << BIT_SHIFT_PKTBUF_WRITE_EN_8814B) +#define BIT_GET_PKTBUF_WRITE_EN_8814B(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8814B) & BIT_MASK_PKTBUF_WRITE_EN_8814B) + + +#define BIT_TXRPTBUF_DBG_8814B BIT(23) + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_TXPKTBUF_DBG_V2_8814B BIT(20) +#define BIT_RXPKTBUF_DBG_8814B BIT(16) + +#define BIT_SHIFT_PKTBUF_DBG_ADDR_8814B 0 +#define BIT_MASK_PKTBUF_DBG_ADDR_8814B 0x1fff +#define BIT_PKTBUF_DBG_ADDR_8814B(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8814B) << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) +#define BIT_GET_PKTBUF_DBG_ADDR_8814B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) & BIT_MASK_PKTBUF_DBG_ADDR_8814B) + + + +/* 2 REG_PKTBUF_DBG_DATA_L_8814B */ + +#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B 0 +#define BIT_MASK_PKTBUF_DBG_DATA_L_8814B 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_L_8814B(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8814B) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) +#define BIT_GET_PKTBUF_DBG_DATA_L_8814B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) & BIT_MASK_PKTBUF_DBG_DATA_L_8814B) + + + +/* 2 REG_PKTBUF_DBG_DATA_H_8814B */ + +#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B 0 +#define BIT_MASK_PKTBUF_DBG_DATA_H_8814B 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_H_8814B(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8814B) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) +#define BIT_GET_PKTBUF_DBG_DATA_H_8814B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) & BIT_MASK_PKTBUF_DBG_DATA_H_8814B) + + + +/* 2 REG_CPWM2_8814B */ + +#define BIT_SHIFT_L0S_TO_RCVY_NUM_8814B 16 +#define BIT_MASK_L0S_TO_RCVY_NUM_8814B 0xff +#define BIT_L0S_TO_RCVY_NUM_8814B(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8814B) << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) +#define BIT_GET_L0S_TO_RCVY_NUM_8814B(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) & BIT_MASK_L0S_TO_RCVY_NUM_8814B) + + +#define BIT_CPWM2_TOGGLING_8814B BIT(15) + +#define BIT_SHIFT_CPWM2_MOD_8814B 0 +#define BIT_MASK_CPWM2_MOD_8814B 0x7fff +#define BIT_CPWM2_MOD_8814B(x) (((x) & BIT_MASK_CPWM2_MOD_8814B) << BIT_SHIFT_CPWM2_MOD_8814B) +#define BIT_GET_CPWM2_MOD_8814B(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8814B) & BIT_MASK_CPWM2_MOD_8814B) + + + +/* 2 REG_TC0_CTRL_8814B */ +#define BIT_TC0INT_EN_8814B BIT(26) +#define BIT_TC0MODE_8814B BIT(25) +#define BIT_TC0EN_8814B BIT(24) + +#define BIT_SHIFT_TC0DATA_8814B 0 +#define BIT_MASK_TC0DATA_8814B 0xffffff +#define BIT_TC0DATA_8814B(x) (((x) & BIT_MASK_TC0DATA_8814B) << BIT_SHIFT_TC0DATA_8814B) +#define BIT_GET_TC0DATA_8814B(x) (((x) >> BIT_SHIFT_TC0DATA_8814B) & BIT_MASK_TC0DATA_8814B) + + + +/* 2 REG_TC1_CTRL_8814B */ +#define BIT_TC1INT_EN_8814B BIT(26) +#define BIT_TC1MODE_8814B BIT(25) +#define BIT_TC1EN_8814B BIT(24) + +#define BIT_SHIFT_TC1DATA_8814B 0 +#define BIT_MASK_TC1DATA_8814B 0xffffff +#define BIT_TC1DATA_8814B(x) (((x) & BIT_MASK_TC1DATA_8814B) << BIT_SHIFT_TC1DATA_8814B) +#define BIT_GET_TC1DATA_8814B(x) (((x) >> BIT_SHIFT_TC1DATA_8814B) & BIT_MASK_TC1DATA_8814B) + + + +/* 2 REG_TC2_CTRL_8814B */ +#define BIT_TC2INT_EN_8814B BIT(26) +#define BIT_TC2MODE_8814B BIT(25) +#define BIT_TC2EN_8814B BIT(24) + +#define BIT_SHIFT_TC2DATA_8814B 0 +#define BIT_MASK_TC2DATA_8814B 0xffffff +#define BIT_TC2DATA_8814B(x) (((x) & BIT_MASK_TC2DATA_8814B) << BIT_SHIFT_TC2DATA_8814B) +#define BIT_GET_TC2DATA_8814B(x) (((x) >> BIT_SHIFT_TC2DATA_8814B) & BIT_MASK_TC2DATA_8814B) + + + +/* 2 REG_TC3_CTRL_8814B */ +#define BIT_TC3INT_EN_8814B BIT(26) +#define BIT_TC3MODE_8814B BIT(25) +#define BIT_TC3EN_8814B BIT(24) + +#define BIT_SHIFT_TC3DATA_8814B 0 +#define BIT_MASK_TC3DATA_8814B 0xffffff +#define BIT_TC3DATA_8814B(x) (((x) & BIT_MASK_TC3DATA_8814B) << BIT_SHIFT_TC3DATA_8814B) +#define BIT_GET_TC3DATA_8814B(x) (((x) >> BIT_SHIFT_TC3DATA_8814B) & BIT_MASK_TC3DATA_8814B) + + + +/* 2 REG_TC4_CTRL_8814B */ +#define BIT_TC4INT_EN_8814B BIT(26) +#define BIT_TC4MODE_8814B BIT(25) +#define BIT_TC4EN_8814B BIT(24) + +#define BIT_SHIFT_TC4DATA_8814B 0 +#define BIT_MASK_TC4DATA_8814B 0xffffff +#define BIT_TC4DATA_8814B(x) (((x) & BIT_MASK_TC4DATA_8814B) << BIT_SHIFT_TC4DATA_8814B) +#define BIT_GET_TC4DATA_8814B(x) (((x) >> BIT_SHIFT_TC4DATA_8814B) & BIT_MASK_TC4DATA_8814B) + + + +/* 2 REG_TCUNIT_BASE_8814B */ + +#define BIT_SHIFT_TCUNIT_BASE_8814B 0 +#define BIT_MASK_TCUNIT_BASE_8814B 0x3fff +#define BIT_TCUNIT_BASE_8814B(x) (((x) & BIT_MASK_TCUNIT_BASE_8814B) << BIT_SHIFT_TCUNIT_BASE_8814B) +#define BIT_GET_TCUNIT_BASE_8814B(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8814B) & BIT_MASK_TCUNIT_BASE_8814B) + + + +/* 2 REG_TC5_CTRL_8814B */ +#define BIT_TC5INT_EN_8814B BIT(26) +#define BIT_TC5MODE_8814B BIT(25) +#define BIT_TC5EN_8814B BIT(24) + +#define BIT_SHIFT_TC5DATA_8814B 0 +#define BIT_MASK_TC5DATA_8814B 0xffffff +#define BIT_TC5DATA_8814B(x) (((x) & BIT_MASK_TC5DATA_8814B) << BIT_SHIFT_TC5DATA_8814B) +#define BIT_GET_TC5DATA_8814B(x) (((x) >> BIT_SHIFT_TC5DATA_8814B) & BIT_MASK_TC5DATA_8814B) + + + +/* 2 REG_TC6_CTRL_8814B */ +#define BIT_TC6INT_EN_8814B BIT(26) +#define BIT_TC6MODE_8814B BIT(25) +#define BIT_TC6EN_8814B BIT(24) + +#define BIT_SHIFT_TC6DATA_8814B 0 +#define BIT_MASK_TC6DATA_8814B 0xffffff +#define BIT_TC6DATA_8814B(x) (((x) & BIT_MASK_TC6DATA_8814B) << BIT_SHIFT_TC6DATA_8814B) +#define BIT_GET_TC6DATA_8814B(x) (((x) >> BIT_SHIFT_TC6DATA_8814B) & BIT_MASK_TC6DATA_8814B) + + + +/* 2 REG_MBIST_FAIL_8814B */ + +#define BIT_SHIFT_8051_MBIST_FAIL_8814B 26 +#define BIT_MASK_8051_MBIST_FAIL_8814B 0x7 +#define BIT_8051_MBIST_FAIL_8814B(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8814B) << BIT_SHIFT_8051_MBIST_FAIL_8814B) +#define BIT_GET_8051_MBIST_FAIL_8814B(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8814B) & BIT_MASK_8051_MBIST_FAIL_8814B) + + + +#define BIT_SHIFT_USB_MBIST_FAIL_8814B 24 +#define BIT_MASK_USB_MBIST_FAIL_8814B 0x3 +#define BIT_USB_MBIST_FAIL_8814B(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8814B) << BIT_SHIFT_USB_MBIST_FAIL_8814B) +#define BIT_GET_USB_MBIST_FAIL_8814B(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8814B) & BIT_MASK_USB_MBIST_FAIL_8814B) + + + +#define BIT_SHIFT_PCIE_MBIST_FAIL_8814B 16 +#define BIT_MASK_PCIE_MBIST_FAIL_8814B 0x3f +#define BIT_PCIE_MBIST_FAIL_8814B(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8814B) << BIT_SHIFT_PCIE_MBIST_FAIL_8814B) +#define BIT_GET_PCIE_MBIST_FAIL_8814B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8814B) & BIT_MASK_PCIE_MBIST_FAIL_8814B) + + + +#define BIT_SHIFT_MAC_MBIST_FAIL_8814B 0 +#define BIT_MASK_MAC_MBIST_FAIL_8814B 0xfff +#define BIT_MAC_MBIST_FAIL_8814B(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_8814B) << BIT_SHIFT_MAC_MBIST_FAIL_8814B) +#define BIT_GET_MAC_MBIST_FAIL_8814B(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8814B) & BIT_MASK_MAC_MBIST_FAIL_8814B) + + + +/* 2 REG_MBIST_START_PAUSE_8814B */ + +#define BIT_SHIFT_8051_MBIST_START_PAUSE_8814B 26 +#define BIT_MASK_8051_MBIST_START_PAUSE_8814B 0x7 +#define BIT_8051_MBIST_START_PAUSE_8814B(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8814B) << BIT_SHIFT_8051_MBIST_START_PAUSE_8814B) +#define BIT_GET_8051_MBIST_START_PAUSE_8814B(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8814B) & BIT_MASK_8051_MBIST_START_PAUSE_8814B) + + + +#define BIT_SHIFT_USB_MBIST_START_PAUSE_8814B 24 +#define BIT_MASK_USB_MBIST_START_PAUSE_8814B 0x3 +#define BIT_USB_MBIST_START_PAUSE_8814B(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8814B) << BIT_SHIFT_USB_MBIST_START_PAUSE_8814B) +#define BIT_GET_USB_MBIST_START_PAUSE_8814B(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8814B) & BIT_MASK_USB_MBIST_START_PAUSE_8814B) + + + +#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8814B 16 +#define BIT_MASK_PCIE_MBIST_START_PAUSE_8814B 0x3f +#define BIT_PCIE_MBIST_START_PAUSE_8814B(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8814B) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8814B) +#define BIT_GET_PCIE_MBIST_START_PAUSE_8814B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8814B) & BIT_MASK_PCIE_MBIST_START_PAUSE_8814B) + + + +#define BIT_SHIFT_MAC_MBIST_START_PAUSE_8814B 0 +#define BIT_MASK_MAC_MBIST_START_PAUSE_8814B 0xfff +#define BIT_MAC_MBIST_START_PAUSE_8814B(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8814B) << BIT_SHIFT_MAC_MBIST_START_PAUSE_8814B) +#define BIT_GET_MAC_MBIST_START_PAUSE_8814B(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8814B) & BIT_MASK_MAC_MBIST_START_PAUSE_8814B) + + + +/* 2 REG_MBIST_DONE_8814B */ + +#define BIT_SHIFT_8051_MBIST_DONE_8814B 26 +#define BIT_MASK_8051_MBIST_DONE_8814B 0x7 +#define BIT_8051_MBIST_DONE_8814B(x) (((x) & BIT_MASK_8051_MBIST_DONE_8814B) << BIT_SHIFT_8051_MBIST_DONE_8814B) +#define BIT_GET_8051_MBIST_DONE_8814B(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8814B) & BIT_MASK_8051_MBIST_DONE_8814B) + + + +#define BIT_SHIFT_USB_MBIST_DONE_8814B 24 +#define BIT_MASK_USB_MBIST_DONE_8814B 0x3 +#define BIT_USB_MBIST_DONE_8814B(x) (((x) & BIT_MASK_USB_MBIST_DONE_8814B) << BIT_SHIFT_USB_MBIST_DONE_8814B) +#define BIT_GET_USB_MBIST_DONE_8814B(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8814B) & BIT_MASK_USB_MBIST_DONE_8814B) + + + +#define BIT_SHIFT_PCIE_MBIST_DONE_8814B 16 +#define BIT_MASK_PCIE_MBIST_DONE_8814B 0x3f +#define BIT_PCIE_MBIST_DONE_8814B(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8814B) << BIT_SHIFT_PCIE_MBIST_DONE_8814B) +#define BIT_GET_PCIE_MBIST_DONE_8814B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8814B) & BIT_MASK_PCIE_MBIST_DONE_8814B) + + + +#define BIT_SHIFT_MAC_MBIST_DONE_8814B 0 +#define BIT_MASK_MAC_MBIST_DONE_8814B 0xfff +#define BIT_MAC_MBIST_DONE_8814B(x) (((x) & BIT_MASK_MAC_MBIST_DONE_8814B) << BIT_SHIFT_MAC_MBIST_DONE_8814B) +#define BIT_GET_MAC_MBIST_DONE_8814B(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8814B) & BIT_MASK_MAC_MBIST_DONE_8814B) + + + +/* 2 REG_MBIST_FAIL_NRML_8814B */ + +#define BIT_SHIFT_MBIST_FAIL_NRML_8814B 0 +#define BIT_MASK_MBIST_FAIL_NRML_8814B 0xffffffffL +#define BIT_MBIST_FAIL_NRML_8814B(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_8814B) << BIT_SHIFT_MBIST_FAIL_NRML_8814B) +#define BIT_GET_MBIST_FAIL_NRML_8814B(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8814B) & BIT_MASK_MBIST_FAIL_NRML_8814B) + + + +/* 2 REG_AES_DECRPT_DATA_8814B */ + +#define BIT_SHIFT_IPS_CFG_ADDR_8814B 0 +#define BIT_MASK_IPS_CFG_ADDR_8814B 0xff +#define BIT_IPS_CFG_ADDR_8814B(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8814B) << BIT_SHIFT_IPS_CFG_ADDR_8814B) +#define BIT_GET_IPS_CFG_ADDR_8814B(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8814B) & BIT_MASK_IPS_CFG_ADDR_8814B) + + + +/* 2 REG_AES_DECRPT_CFG_8814B */ + +#define BIT_SHIFT_IPS_CFG_DATA_8814B 0 +#define BIT_MASK_IPS_CFG_DATA_8814B 0xffffffffL +#define BIT_IPS_CFG_DATA_8814B(x) (((x) & BIT_MASK_IPS_CFG_DATA_8814B) << BIT_SHIFT_IPS_CFG_DATA_8814B) +#define BIT_GET_IPS_CFG_DATA_8814B(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8814B) & BIT_MASK_IPS_CFG_DATA_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_TMETER_8814B */ +#define BIT_TEMP_VALID_8814B BIT(31) + +#define BIT_SHIFT_TEMP_VALUE_8814B 24 +#define BIT_MASK_TEMP_VALUE_8814B 0x3f +#define BIT_TEMP_VALUE_8814B(x) (((x) & BIT_MASK_TEMP_VALUE_8814B) << BIT_SHIFT_TEMP_VALUE_8814B) +#define BIT_GET_TEMP_VALUE_8814B(x) (((x) >> BIT_SHIFT_TEMP_VALUE_8814B) & BIT_MASK_TEMP_VALUE_8814B) + + + +#define BIT_SHIFT_REG_TMETER_TIMER_8814B 8 +#define BIT_MASK_REG_TMETER_TIMER_8814B 0xfff +#define BIT_REG_TMETER_TIMER_8814B(x) (((x) & BIT_MASK_REG_TMETER_TIMER_8814B) << BIT_SHIFT_REG_TMETER_TIMER_8814B) +#define BIT_GET_REG_TMETER_TIMER_8814B(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8814B) & BIT_MASK_REG_TMETER_TIMER_8814B) + + + +#define BIT_SHIFT_REG_TEMP_DELTA_8814B 2 +#define BIT_MASK_REG_TEMP_DELTA_8814B 0x3f +#define BIT_REG_TEMP_DELTA_8814B(x) (((x) & BIT_MASK_REG_TEMP_DELTA_8814B) << BIT_SHIFT_REG_TEMP_DELTA_8814B) +#define BIT_GET_REG_TEMP_DELTA_8814B(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8814B) & BIT_MASK_REG_TEMP_DELTA_8814B) + + +#define BIT_REG_TMETER_EN_8814B BIT(0) + +/* 2 REG_OSC_32K_CTRL_8814B */ + +#define BIT_SHIFT_OSC_32K_CLKGEN_0_8814B 16 +#define BIT_MASK_OSC_32K_CLKGEN_0_8814B 0xffff +#define BIT_OSC_32K_CLKGEN_0_8814B(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8814B) << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) +#define BIT_GET_OSC_32K_CLKGEN_0_8814B(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) & BIT_MASK_OSC_32K_CLKGEN_0_8814B) + + + +#define BIT_SHIFT_OSC_32K_RES_COMP_8814B 4 +#define BIT_MASK_OSC_32K_RES_COMP_8814B 0x3 +#define BIT_OSC_32K_RES_COMP_8814B(x) (((x) & BIT_MASK_OSC_32K_RES_COMP_8814B) << BIT_SHIFT_OSC_32K_RES_COMP_8814B) +#define BIT_GET_OSC_32K_RES_COMP_8814B(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8814B) & BIT_MASK_OSC_32K_RES_COMP_8814B) + + +#define BIT_OSC_32K_OUT_SEL_8814B BIT(3) +#define BIT_ISO_WL_2_OSC_32K_8814B BIT(1) +#define BIT_POW_CKGEN_8814B BIT(0) + +/* 2 REG_32K_CAL_REG1_8814B */ +#define BIT_CAL_32K_REG_WR_8814B BIT(31) +#define BIT_CAL_32K_DBG_SEL_8814B BIT(22) + +#define BIT_SHIFT_CAL_32K_REG_ADDR_8814B 16 +#define BIT_MASK_CAL_32K_REG_ADDR_8814B 0x3f +#define BIT_CAL_32K_REG_ADDR_8814B(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR_8814B) << BIT_SHIFT_CAL_32K_REG_ADDR_8814B) +#define BIT_GET_CAL_32K_REG_ADDR_8814B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8814B) & BIT_MASK_CAL_32K_REG_ADDR_8814B) + + + +#define BIT_SHIFT_CAL_32K_REG_DATA_8814B 0 +#define BIT_MASK_CAL_32K_REG_DATA_8814B 0xffff +#define BIT_CAL_32K_REG_DATA_8814B(x) (((x) & BIT_MASK_CAL_32K_REG_DATA_8814B) << BIT_SHIFT_CAL_32K_REG_DATA_8814B) +#define BIT_GET_CAL_32K_REG_DATA_8814B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8814B) & BIT_MASK_CAL_32K_REG_DATA_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_C2HEVT_8814B */ + +#define BIT_SHIFT_C2HEVT_MSG_V1_8814B 0 +#define BIT_MASK_C2HEVT_MSG_V1_8814B 0xffffffffL +#define BIT_C2HEVT_MSG_V1_8814B(x) (((x) & BIT_MASK_C2HEVT_MSG_V1_8814B) << BIT_SHIFT_C2HEVT_MSG_V1_8814B) +#define BIT_GET_C2HEVT_MSG_V1_8814B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8814B) & BIT_MASK_C2HEVT_MSG_V1_8814B) + + + +/* 2 REG_C2HEVT_1_8814B */ + +#define BIT_SHIFT_C2HEVT_MSG_1_8814B 0 +#define BIT_MASK_C2HEVT_MSG_1_8814B 0xffffffffL +#define BIT_C2HEVT_MSG_1_8814B(x) (((x) & BIT_MASK_C2HEVT_MSG_1_8814B) << BIT_SHIFT_C2HEVT_MSG_1_8814B) +#define BIT_GET_C2HEVT_MSG_1_8814B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8814B) & BIT_MASK_C2HEVT_MSG_1_8814B) + + + +/* 2 REG_C2HEVT_2_8814B */ + +#define BIT_SHIFT_C2HEVT_MSG_2_8814B 0 +#define BIT_MASK_C2HEVT_MSG_2_8814B 0xffffffffL +#define BIT_C2HEVT_MSG_2_8814B(x) (((x) & BIT_MASK_C2HEVT_MSG_2_8814B) << BIT_SHIFT_C2HEVT_MSG_2_8814B) +#define BIT_GET_C2HEVT_MSG_2_8814B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8814B) & BIT_MASK_C2HEVT_MSG_2_8814B) + + + +/* 2 REG_C2HEVT_3_8814B */ + +#define BIT_SHIFT_C2HEVT_MSG_3_8814B 0 +#define BIT_MASK_C2HEVT_MSG_3_8814B 0xffffffffL +#define BIT_C2HEVT_MSG_3_8814B(x) (((x) & BIT_MASK_C2HEVT_MSG_3_8814B) << BIT_SHIFT_C2HEVT_MSG_3_8814B) +#define BIT_GET_C2HEVT_MSG_3_8814B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8814B) & BIT_MASK_C2HEVT_MSG_3_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_SW_DEFINED_PAGE1_8814B */ + +#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B 0 +#define BIT_MASK_SW_DEFINED_PAGE1_V1_8814B 0xffffffffL +#define BIT_SW_DEFINED_PAGE1_V1_8814B(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8814B) << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) +#define BIT_GET_SW_DEFINED_PAGE1_V1_8814B(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) & BIT_MASK_SW_DEFINED_PAGE1_V1_8814B) + + + +/* 2 REG_SW_DEFINED_PAGE2_8814B */ + +#define BIT_SHIFT_SW_DEFINED_PAGE2_8814B 0 +#define BIT_MASK_SW_DEFINED_PAGE2_8814B 0xffffffffL +#define BIT_SW_DEFINED_PAGE2_8814B(x) (((x) & BIT_MASK_SW_DEFINED_PAGE2_8814B) << BIT_SHIFT_SW_DEFINED_PAGE2_8814B) +#define BIT_GET_SW_DEFINED_PAGE2_8814B(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8814B) & BIT_MASK_SW_DEFINED_PAGE2_8814B) + + + +/* 2 REG_MCUTST_I_8814B */ + +#define BIT_SHIFT_MCUDMSG_I_8814B 0 +#define BIT_MASK_MCUDMSG_I_8814B 0xffffffffL +#define BIT_MCUDMSG_I_8814B(x) (((x) & BIT_MASK_MCUDMSG_I_8814B) << BIT_SHIFT_MCUDMSG_I_8814B) +#define BIT_GET_MCUDMSG_I_8814B(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8814B) & BIT_MASK_MCUDMSG_I_8814B) + + + +/* 2 REG_MCUTST_II_8814B */ + +#define BIT_SHIFT_MCUDMSG_II_8814B 0 +#define BIT_MASK_MCUDMSG_II_8814B 0xffffffffL +#define BIT_MCUDMSG_II_8814B(x) (((x) & BIT_MASK_MCUDMSG_II_8814B) << BIT_SHIFT_MCUDMSG_II_8814B) +#define BIT_GET_MCUDMSG_II_8814B(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8814B) & BIT_MASK_MCUDMSG_II_8814B) + + + +/* 2 REG_FMETHR_8814B */ +#define BIT_FMSG_INT_8814B BIT(31) + +#define BIT_SHIFT_FW_MSG_8814B 0 +#define BIT_MASK_FW_MSG_8814B 0xffffffffL +#define BIT_FW_MSG_8814B(x) (((x) & BIT_MASK_FW_MSG_8814B) << BIT_SHIFT_FW_MSG_8814B) +#define BIT_GET_FW_MSG_8814B(x) (((x) >> BIT_SHIFT_FW_MSG_8814B) & BIT_MASK_FW_MSG_8814B) + + + +/* 2 REG_HMETFR_8814B */ + +#define BIT_SHIFT_HRCV_MSG_8814B 24 +#define BIT_MASK_HRCV_MSG_8814B 0xff +#define BIT_HRCV_MSG_8814B(x) (((x) & BIT_MASK_HRCV_MSG_8814B) << BIT_SHIFT_HRCV_MSG_8814B) +#define BIT_GET_HRCV_MSG_8814B(x) (((x) >> BIT_SHIFT_HRCV_MSG_8814B) & BIT_MASK_HRCV_MSG_8814B) + + +#define BIT_INT_BOX3_8814B BIT(3) +#define BIT_INT_BOX2_8814B BIT(2) +#define BIT_INT_BOX1_8814B BIT(1) +#define BIT_INT_BOX0_8814B BIT(0) + +/* 2 REG_HMEBOX0_8814B */ + +#define BIT_SHIFT_HOST_MSG_0_8814B 0 +#define BIT_MASK_HOST_MSG_0_8814B 0xffffffffL +#define BIT_HOST_MSG_0_8814B(x) (((x) & BIT_MASK_HOST_MSG_0_8814B) << BIT_SHIFT_HOST_MSG_0_8814B) +#define BIT_GET_HOST_MSG_0_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8814B) & BIT_MASK_HOST_MSG_0_8814B) + + + +/* 2 REG_HMEBOX1_8814B */ + +#define BIT_SHIFT_HOST_MSG_1_8814B 0 +#define BIT_MASK_HOST_MSG_1_8814B 0xffffffffL +#define BIT_HOST_MSG_1_8814B(x) (((x) & BIT_MASK_HOST_MSG_1_8814B) << BIT_SHIFT_HOST_MSG_1_8814B) +#define BIT_GET_HOST_MSG_1_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8814B) & BIT_MASK_HOST_MSG_1_8814B) + + + +/* 2 REG_HMEBOX2_8814B */ + +#define BIT_SHIFT_HOST_MSG_2_8814B 0 +#define BIT_MASK_HOST_MSG_2_8814B 0xffffffffL +#define BIT_HOST_MSG_2_8814B(x) (((x) & BIT_MASK_HOST_MSG_2_8814B) << BIT_SHIFT_HOST_MSG_2_8814B) +#define BIT_GET_HOST_MSG_2_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8814B) & BIT_MASK_HOST_MSG_2_8814B) + + + +/* 2 REG_HMEBOX3_8814B */ + +#define BIT_SHIFT_HOST_MSG_3_8814B 0 +#define BIT_MASK_HOST_MSG_3_8814B 0xffffffffL +#define BIT_HOST_MSG_3_8814B(x) (((x) & BIT_MASK_HOST_MSG_3_8814B) << BIT_SHIFT_HOST_MSG_3_8814B) +#define BIT_GET_HOST_MSG_3_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8814B) & BIT_MASK_HOST_MSG_3_8814B) + + + +/* 2 REG_LLT_INIT_8814B */ + +#define BIT_SHIFT_LLTE_RWM_8814B 30 +#define BIT_MASK_LLTE_RWM_8814B 0x3 +#define BIT_LLTE_RWM_8814B(x) (((x) & BIT_MASK_LLTE_RWM_8814B) << BIT_SHIFT_LLTE_RWM_8814B) +#define BIT_GET_LLTE_RWM_8814B(x) (((x) >> BIT_SHIFT_LLTE_RWM_8814B) & BIT_MASK_LLTE_RWM_8814B) + + + +#define BIT_SHIFT_LLTINI_PDATA_V1_8814B 16 +#define BIT_MASK_LLTINI_PDATA_V1_8814B 0xfff +#define BIT_LLTINI_PDATA_V1_8814B(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8814B) << BIT_SHIFT_LLTINI_PDATA_V1_8814B) +#define BIT_GET_LLTINI_PDATA_V1_8814B(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8814B) & BIT_MASK_LLTINI_PDATA_V1_8814B) + + + +#define BIT_SHIFT_LLTINI_HDATA_V1_8814B 0 +#define BIT_MASK_LLTINI_HDATA_V1_8814B 0xfff +#define BIT_LLTINI_HDATA_V1_8814B(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8814B) << BIT_SHIFT_LLTINI_HDATA_V1_8814B) +#define BIT_GET_LLTINI_HDATA_V1_8814B(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8814B) & BIT_MASK_LLTINI_HDATA_V1_8814B) + + + +/* 2 REG_LLT_INIT_ADDR_8814B */ + +#define BIT_SHIFT_LLTINI_ADDR_V1_8814B 0 +#define BIT_MASK_LLTINI_ADDR_V1_8814B 0xfff +#define BIT_LLTINI_ADDR_V1_8814B(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8814B) << BIT_SHIFT_LLTINI_ADDR_V1_8814B) +#define BIT_GET_LLTINI_ADDR_V1_8814B(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8814B) & BIT_MASK_LLTINI_ADDR_V1_8814B) + + + +/* 2 REG_BB_ACCESS_CTRL_8814B */ + +#define BIT_SHIFT_BB_WRITE_READ_8814B 30 +#define BIT_MASK_BB_WRITE_READ_8814B 0x3 +#define BIT_BB_WRITE_READ_8814B(x) (((x) & BIT_MASK_BB_WRITE_READ_8814B) << BIT_SHIFT_BB_WRITE_READ_8814B) +#define BIT_GET_BB_WRITE_READ_8814B(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8814B) & BIT_MASK_BB_WRITE_READ_8814B) + + + +#define BIT_SHIFT_BB_WRITE_EN_8814B 12 +#define BIT_MASK_BB_WRITE_EN_8814B 0xf +#define BIT_BB_WRITE_EN_8814B(x) (((x) & BIT_MASK_BB_WRITE_EN_8814B) << BIT_SHIFT_BB_WRITE_EN_8814B) +#define BIT_GET_BB_WRITE_EN_8814B(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_8814B) & BIT_MASK_BB_WRITE_EN_8814B) + + + +#define BIT_SHIFT_BB_ADDR_8814B 2 +#define BIT_MASK_BB_ADDR_8814B 0x1ff +#define BIT_BB_ADDR_8814B(x) (((x) & BIT_MASK_BB_ADDR_8814B) << BIT_SHIFT_BB_ADDR_8814B) +#define BIT_GET_BB_ADDR_8814B(x) (((x) >> BIT_SHIFT_BB_ADDR_8814B) & BIT_MASK_BB_ADDR_8814B) + + +#define BIT_BB_ERRACC_8814B BIT(0) + +/* 2 REG_BB_ACCESS_DATA_8814B */ + +#define BIT_SHIFT_BB_DATA_8814B 0 +#define BIT_MASK_BB_DATA_8814B 0xffffffffL +#define BIT_BB_DATA_8814B(x) (((x) & BIT_MASK_BB_DATA_8814B) << BIT_SHIFT_BB_DATA_8814B) +#define BIT_GET_BB_DATA_8814B(x) (((x) >> BIT_SHIFT_BB_DATA_8814B) & BIT_MASK_BB_DATA_8814B) + + + +/* 2 REG_HMEBOX_E0_8814B */ + +#define BIT_SHIFT_HMEBOX_E0_8814B 0 +#define BIT_MASK_HMEBOX_E0_8814B 0xffffffffL +#define BIT_HMEBOX_E0_8814B(x) (((x) & BIT_MASK_HMEBOX_E0_8814B) << BIT_SHIFT_HMEBOX_E0_8814B) +#define BIT_GET_HMEBOX_E0_8814B(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8814B) & BIT_MASK_HMEBOX_E0_8814B) + + + +/* 2 REG_HMEBOX_E1_8814B */ + +#define BIT_SHIFT_HMEBOX_E1_8814B 0 +#define BIT_MASK_HMEBOX_E1_8814B 0xffffffffL +#define BIT_HMEBOX_E1_8814B(x) (((x) & BIT_MASK_HMEBOX_E1_8814B) << BIT_SHIFT_HMEBOX_E1_8814B) +#define BIT_GET_HMEBOX_E1_8814B(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8814B) & BIT_MASK_HMEBOX_E1_8814B) + + + +/* 2 REG_HMEBOX_E2_8814B */ + +#define BIT_SHIFT_HMEBOX_E2_8814B 0 +#define BIT_MASK_HMEBOX_E2_8814B 0xffffffffL +#define BIT_HMEBOX_E2_8814B(x) (((x) & BIT_MASK_HMEBOX_E2_8814B) << BIT_SHIFT_HMEBOX_E2_8814B) +#define BIT_GET_HMEBOX_E2_8814B(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8814B) & BIT_MASK_HMEBOX_E2_8814B) + + + +/* 2 REG_HMEBOX_E3_8814B */ + +#define BIT_SHIFT_HMEBOX_E3_8814B 0 +#define BIT_MASK_HMEBOX_E3_8814B 0xffffffffL +#define BIT_HMEBOX_E3_8814B(x) (((x) & BIT_MASK_HMEBOX_E3_8814B) << BIT_SHIFT_HMEBOX_E3_8814B) +#define BIT_GET_HMEBOX_E3_8814B(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8814B) & BIT_MASK_HMEBOX_E3_8814B) + + + +/* 2 REG_CR_EXT_8814B */ + +#define BIT_SHIFT_PHY_REQ_DELAY_8814B 24 +#define BIT_MASK_PHY_REQ_DELAY_8814B 0xf +#define BIT_PHY_REQ_DELAY_8814B(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8814B) << BIT_SHIFT_PHY_REQ_DELAY_8814B) +#define BIT_GET_PHY_REQ_DELAY_8814B(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8814B) & BIT_MASK_PHY_REQ_DELAY_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SPD_DOWN_8814B BIT(16) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_NETYPE4_8814B 4 +#define BIT_MASK_NETYPE4_8814B 0x3 +#define BIT_NETYPE4_8814B(x) (((x) & BIT_MASK_NETYPE4_8814B) << BIT_SHIFT_NETYPE4_8814B) +#define BIT_GET_NETYPE4_8814B(x) (((x) >> BIT_SHIFT_NETYPE4_8814B) & BIT_MASK_NETYPE4_8814B) + + + +#define BIT_SHIFT_NETYPE3_8814B 2 +#define BIT_MASK_NETYPE3_8814B 0x3 +#define BIT_NETYPE3_8814B(x) (((x) & BIT_MASK_NETYPE3_8814B) << BIT_SHIFT_NETYPE3_8814B) +#define BIT_GET_NETYPE3_8814B(x) (((x) >> BIT_SHIFT_NETYPE3_8814B) & BIT_MASK_NETYPE3_8814B) + + + +#define BIT_SHIFT_NETYPE2_8814B 0 +#define BIT_MASK_NETYPE2_8814B 0x3 +#define BIT_NETYPE2_8814B(x) (((x) & BIT_MASK_NETYPE2_8814B) << BIT_SHIFT_NETYPE2_8814B) +#define BIT_GET_NETYPE2_8814B(x) (((x) >> BIT_SHIFT_NETYPE2_8814B) & BIT_MASK_NETYPE2_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_FWFF_8814B */ + +#define BIT_SHIFT_PKTNUM_TH_V1_8814B 24 +#define BIT_MASK_PKTNUM_TH_V1_8814B 0xff +#define BIT_PKTNUM_TH_V1_8814B(x) (((x) & BIT_MASK_PKTNUM_TH_V1_8814B) << BIT_SHIFT_PKTNUM_TH_V1_8814B) +#define BIT_GET_PKTNUM_TH_V1_8814B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8814B) & BIT_MASK_PKTNUM_TH_V1_8814B) + + + +#define BIT_SHIFT_TIMER_TH_8814B 16 +#define BIT_MASK_TIMER_TH_8814B 0xff +#define BIT_TIMER_TH_8814B(x) (((x) & BIT_MASK_TIMER_TH_8814B) << BIT_SHIFT_TIMER_TH_8814B) +#define BIT_GET_TIMER_TH_8814B(x) (((x) >> BIT_SHIFT_TIMER_TH_8814B) & BIT_MASK_TIMER_TH_8814B) + + + +#define BIT_SHIFT_RXPKT1ENADDR_8814B 0 +#define BIT_MASK_RXPKT1ENADDR_8814B 0xffff +#define BIT_RXPKT1ENADDR_8814B(x) (((x) & BIT_MASK_RXPKT1ENADDR_8814B) << BIT_SHIFT_RXPKT1ENADDR_8814B) +#define BIT_GET_RXPKT1ENADDR_8814B(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8814B) & BIT_MASK_RXPKT1ENADDR_8814B) + + + +/* 2 REG_RXFF_PTR_V1_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_RXFF0_RDPTR_V2_8814B 0 +#define BIT_MASK_RXFF0_RDPTR_V2_8814B 0x3ffff +#define BIT_RXFF0_RDPTR_V2_8814B(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8814B) << BIT_SHIFT_RXFF0_RDPTR_V2_8814B) +#define BIT_GET_RXFF0_RDPTR_V2_8814B(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8814B) & BIT_MASK_RXFF0_RDPTR_V2_8814B) + + + +/* 2 REG_RXFF_WTR_V1_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_RXFF0_WTPTR_V2_8814B 0 +#define BIT_MASK_RXFF0_WTPTR_V2_8814B 0x3ffff +#define BIT_RXFF0_WTPTR_V2_8814B(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8814B) << BIT_SHIFT_RXFF0_WTPTR_V2_8814B) +#define BIT_GET_RXFF0_WTPTR_V2_8814B(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8814B) & BIT_MASK_RXFF0_WTPTR_V2_8814B) + + + +/* 2 REG_FE2IMR_8814B */ +#define BIT__FE4ISR__IND_MSK_8814B BIT(29) +#define BIT_FS_TXSC_DESC_DONE_INT_EN_8814B BIT(28) +#define BIT_FS_TXSC_BKDONE_INT_EN_8814B BIT(27) +#define BIT_FS_TXSC_BEDONE_INT_EN_8814B BIT(26) +#define BIT_FS_TXSC_VIDONE_INT_EN_8814B BIT(25) +#define BIT_FS_TXSC_VODONE_INT_EN_8814B BIT(24) +#define BIT_FS_ATIM_MB7_INT_EN_8814B BIT(23) +#define BIT_FS_ATIM_MB6_INT_EN_8814B BIT(22) +#define BIT_FS_ATIM_MB5_INT_EN_8814B BIT(21) +#define BIT_FS_ATIM_MB4_INT_EN_8814B BIT(20) +#define BIT_FS_ATIM_MB3_INT_EN_8814B BIT(19) +#define BIT_FS_ATIM_MB2_INT_EN_8814B BIT(18) +#define BIT_FS_ATIM_MB1_INT_EN_8814B BIT(17) +#define BIT_FS_ATIM_MB0_INT_EN_8814B BIT(16) +#define BIT_FS_TBTT4INT_EN_8814B BIT(11) +#define BIT_FS_TBTT3INT_EN_8814B BIT(10) +#define BIT_FS_TBTT2INT_EN_8814B BIT(9) +#define BIT_FS_TBTT1INT_EN_8814B BIT(8) +#define BIT_FS_TBTT0_MB7INT_EN_8814B BIT(7) +#define BIT_FS_TBTT0_MB6INT_EN_8814B BIT(6) +#define BIT_FS_TBTT0_MB5INT_EN_8814B BIT(5) +#define BIT_FS_TBTT0_MB4INT_EN_8814B BIT(4) +#define BIT_FS_TBTT0_MB3INT_EN_8814B BIT(3) +#define BIT_FS_TBTT0_MB2INT_EN_8814B BIT(2) +#define BIT_FS_TBTT0_MB1INT_EN_8814B BIT(1) +#define BIT_FS_TBTT0_INT_EN_8814B BIT(0) + +/* 2 REG_FE2ISR_8814B */ +#define BIT__FE4ISR__IND_INT_8814B BIT(29) +#define BIT_FS_TXSC_DESC_DONE_INT_8814B BIT(28) +#define BIT_FS_TXSC_BKDONE_INT_8814B BIT(27) +#define BIT_FS_TXSC_BEDONE_INT_8814B BIT(26) +#define BIT_FS_TXSC_VIDONE_INT_8814B BIT(25) +#define BIT_FS_TXSC_VODONE_INT_8814B BIT(24) +#define BIT_FS_ATIM_MB7_INT_8814B BIT(23) +#define BIT_FS_ATIM_MB6_INT_8814B BIT(22) +#define BIT_FS_ATIM_MB5_INT_8814B BIT(21) +#define BIT_FS_ATIM_MB4_INT_8814B BIT(20) +#define BIT_FS_ATIM_MB3_INT_8814B BIT(19) +#define BIT_FS_ATIM_MB2_INT_8814B BIT(18) +#define BIT_FS_ATIM_MB1_INT_8814B BIT(17) +#define BIT_FS_ATIM_MB0_INT_8814B BIT(16) +#define BIT_FS_TBTT4INT_8814B BIT(11) +#define BIT_FS_TBTT3INT_8814B BIT(10) +#define BIT_FS_TBTT2INT_8814B BIT(9) +#define BIT_FS_TBTT1INT_8814B BIT(8) +#define BIT_FS_TBTT0_MB7INT_8814B BIT(7) +#define BIT_FS_TBTT0_MB6INT_8814B BIT(6) +#define BIT_FS_TBTT0_MB5INT_8814B BIT(5) +#define BIT_FS_TBTT0_MB4INT_8814B BIT(4) +#define BIT_FS_TBTT0_MB3INT_8814B BIT(3) +#define BIT_FS_TBTT0_MB2INT_8814B BIT(2) +#define BIT_FS_TBTT0_MB1INT_8814B BIT(1) +#define BIT_FS_TBTT0_INT_8814B BIT(0) + +/* 2 REG_FE3IMR_8814B */ +#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8814B BIT(31) +#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8814B BIT(30) +#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8814B BIT(29) +#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8814B BIT(28) +#define BIT_FS_BCNDMA4_INT_EN_8814B BIT(27) +#define BIT_FS_BCNDMA3_INT_EN_8814B BIT(26) +#define BIT_FS_BCNDMA2_INT_EN_8814B BIT(25) +#define BIT_FS_BCNDMA1_INT_EN_8814B BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT_EN_8814B BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT_EN_8814B BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT_EN_8814B BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT_EN_8814B BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT_EN_8814B BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT_EN_8814B BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT_EN_8814B BIT(17) +#define BIT_FS_BCNDMA0_INT_EN_8814B BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8814B BIT(15) +#define BIT_FS_BCNERLY4_INT_EN_8814B BIT(11) +#define BIT_FS_BCNERLY3_INT_EN_8814B BIT(10) +#define BIT_FS_BCNERLY2_INT_EN_8814B BIT(9) +#define BIT_FS_BCNERLY1_INT_EN_8814B BIT(8) +#define BIT_FS_BCNERLY0_MB7INT_EN_8814B BIT(7) +#define BIT_FS_BCNERLY0_MB6INT_EN_8814B BIT(6) +#define BIT_FS_BCNERLY0_MB5INT_EN_8814B BIT(5) +#define BIT_FS_BCNERLY0_MB4INT_EN_8814B BIT(4) +#define BIT_FS_BCNERLY0_MB3INT_EN_8814B BIT(3) +#define BIT_FS_BCNERLY0_MB2INT_EN_8814B BIT(2) +#define BIT_FS_BCNERLY0_MB1INT_EN_8814B BIT(1) +#define BIT_FS_BCNERLY0_INT_EN_8814B BIT(0) + +/* 2 REG_FE3ISR_8814B */ +#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8814B BIT(31) +#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8814B BIT(30) +#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8814B BIT(29) +#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8814B BIT(28) +#define BIT_FS_BCNDMA4_INT_8814B BIT(27) +#define BIT_FS_BCNDMA3_INT_8814B BIT(26) +#define BIT_FS_BCNDMA2_INT_8814B BIT(25) +#define BIT_FS_BCNDMA1_INT_8814B BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT_8814B BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT_8814B BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT_8814B BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT_8814B BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT_8814B BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT_8814B BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT_8814B BIT(17) +#define BIT_FS_BCNDMA0_INT_8814B BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT_8814B BIT(15) +#define BIT_FS_BCNERLY4_INT_8814B BIT(11) +#define BIT_FS_BCNERLY3_INT_8814B BIT(10) +#define BIT_FS_BCNERLY2_INT_8814B BIT(9) +#define BIT_FS_BCNERLY1_INT_8814B BIT(8) +#define BIT_FS_BCNERLY0_MB7INT_8814B BIT(7) +#define BIT_FS_BCNERLY0_MB6INT_8814B BIT(6) +#define BIT_FS_BCNERLY0_MB5INT_8814B BIT(5) +#define BIT_FS_BCNERLY0_MB4INT_8814B BIT(4) +#define BIT_FS_BCNERLY0_MB3INT_8814B BIT(3) +#define BIT_FS_BCNERLY0_MB2INT_8814B BIT(2) +#define BIT_FS_BCNERLY0_MB1INT_8814B BIT(1) +#define BIT_FS_BCNERLY0_INT_8814B BIT(0) + +/* 2 REG_FE4IMR_8814B */ +#define BIT_FS_CLI3_TXPKTIN_INT_EN_8814B BIT(19) +#define BIT_FS_CLI2_TXPKTIN_INT_EN_8814B BIT(18) +#define BIT_FS_CLI1_TXPKTIN_INT_EN_8814B BIT(17) +#define BIT_FS_CLI0_TXPKTIN_INT_EN_8814B BIT(16) +#define BIT_FS_CLI3_RX_UMD0_INT_EN_8814B BIT(15) +#define BIT_FS_CLI3_RX_UMD1_INT_EN_8814B BIT(14) +#define BIT_FS_CLI3_RX_BMD0_INT_EN_8814B BIT(13) +#define BIT_FS_CLI3_RX_BMD1_INT_EN_8814B BIT(12) +#define BIT_FS_CLI2_RX_UMD0_INT_EN_8814B BIT(11) +#define BIT_FS_CLI2_RX_UMD1_INT_EN_8814B BIT(10) +#define BIT_FS_CLI2_RX_BMD0_INT_EN_8814B BIT(9) +#define BIT_FS_CLI2_RX_BMD1_INT_EN_8814B BIT(8) +#define BIT_FS_CLI1_RX_UMD0_INT_EN_8814B BIT(7) +#define BIT_FS_CLI1_RX_UMD1_INT_EN_8814B BIT(6) +#define BIT_FS_CLI1_RX_BMD0_INT_EN_8814B BIT(5) +#define BIT_FS_CLI1_RX_BMD1_INT_EN_8814B BIT(4) +#define BIT_FS_CLI0_RX_UMD0_INT_EN_8814B BIT(3) +#define BIT_FS_CLI0_RX_UMD1_INT_EN_8814B BIT(2) +#define BIT_FS_CLI0_RX_BMD0_INT_EN_8814B BIT(1) +#define BIT_FS_CLI0_RX_BMD1_INT_EN_8814B BIT(0) + +/* 2 REG_FE4ISR_8814B */ +#define BIT_FS_CLI3_TXPKTIN_INT_8814B BIT(19) +#define BIT_FS_CLI2_TXPKTIN_INT_8814B BIT(18) +#define BIT_FS_CLI1_TXPKTIN_INT_8814B BIT(17) +#define BIT_FS_CLI0_TXPKTIN_INT_8814B BIT(16) +#define BIT_FS_CLI3_RX_UMD0_INT_8814B BIT(15) +#define BIT_FS_CLI3_RX_UMD1_INT_8814B BIT(14) +#define BIT_FS_CLI3_RX_BMD0_INT_8814B BIT(13) +#define BIT_FS_CLI3_RX_BMD1_INT_8814B BIT(12) +#define BIT_FS_CLI2_RX_UMD0_INT_8814B BIT(11) +#define BIT_FS_CLI2_RX_UMD1_INT_8814B BIT(10) +#define BIT_FS_CLI2_RX_BMD0_INT_8814B BIT(9) +#define BIT_FS_CLI2_RX_BMD1_INT_8814B BIT(8) +#define BIT_FS_CLI1_RX_UMD0_INT_8814B BIT(7) +#define BIT_FS_CLI1_RX_UMD1_INT_8814B BIT(6) +#define BIT_FS_CLI1_RX_BMD0_INT_8814B BIT(5) +#define BIT_FS_CLI1_RX_BMD1_INT_8814B BIT(4) +#define BIT_FS_CLI0_RX_UMD0_INT_8814B BIT(3) +#define BIT_FS_CLI0_RX_UMD1_INT_8814B BIT(2) +#define BIT_FS_CLI0_RX_BMD0_INT_8814B BIT(1) +#define BIT_FS_CLI0_RX_BMD1_INT_8814B BIT(0) + +/* 2 REG_FT1IMR_8814B */ +#define BIT__FT2ISR__IND_MSK_8814B BIT(30) +#define BIT_FTM_PTT_INT_EN_8814B BIT(29) +#define BIT_RXFTMREQ_INT_EN_8814B BIT(28) +#define BIT_RXFTM_INT_EN_8814B BIT(27) +#define BIT_TXFTM_INT_EN_8814B BIT(26) +#define BIT_FS_H2C_CMD_OK_INT_EN_8814B BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT_EN_8814B BIT(24) +#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8814B BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8814B BIT(22) +#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8814B BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8814B BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8814B BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8814B BIT(18) +#define BIT_FS_CTWEND2_INT_EN_8814B BIT(17) +#define BIT_FS_CTWEND1_INT_EN_8814B BIT(16) +#define BIT_FS_CTWEND0_INT_EN_8814B BIT(15) +#define BIT_FS_TX_NULL1_INT_EN_8814B BIT(14) +#define BIT_FS_TX_NULL0_INT_EN_8814B BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_EN_8814B BIT(12) +#define BIT_FS_P2P_RFON2_INT_EN_8814B BIT(11) +#define BIT_FS_P2P_RFOFF2_INT_EN_8814B BIT(10) +#define BIT_FS_P2P_RFON1_INT_EN_8814B BIT(9) +#define BIT_FS_P2P_RFOFF1_INT_EN_8814B BIT(8) +#define BIT_FS_P2P_RFON0_INT_EN_8814B BIT(7) +#define BIT_FS_P2P_RFOFF0_INT_EN_8814B BIT(6) +#define BIT_FS_RX_UAPSDMD1_EN_8814B BIT(5) +#define BIT_FS_RX_UAPSDMD0_EN_8814B BIT(4) +#define BIT_FS_TRIGGER_PKT_EN_8814B BIT(3) +#define BIT_FS_EOSP_INT_EN_8814B BIT(2) +#define BIT_FS_RPWM2_INT_EN_8814B BIT(1) +#define BIT_FS_RPWM_INT_EN_8814B BIT(0) + +/* 2 REG_FT1ISR_8814B */ +#define BIT__FT2ISR__IND_INT_8814B BIT(30) +#define BIT_FTM_PTT_INT_8814B BIT(29) +#define BIT_RXFTMREQ_INT_8814B BIT(28) +#define BIT_RXFTM_INT_8814B BIT(27) +#define BIT_TXFTM_INT_8814B BIT(26) +#define BIT_FS_H2C_CMD_OK_INT_8814B BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT_8814B BIT(24) +#define BIT_FS_MACID_PWRCHANGE5_INT_8814B BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT_8814B BIT(22) +#define BIT_FS_MACID_PWRCHANGE3_INT_8814B BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT_8814B BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT_8814B BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT_8814B BIT(18) +#define BIT_FS_CTWEND2_INT_8814B BIT(17) +#define BIT_FS_CTWEND1_INT_8814B BIT(16) +#define BIT_FS_CTWEND0_INT_8814B BIT(15) +#define BIT_FS_TX_NULL1_INT_8814B BIT(14) +#define BIT_FS_TX_NULL0_INT_8814B BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_INT_8814B BIT(12) +#define BIT_FS_P2P_RFON2_INT_8814B BIT(11) +#define BIT_FS_P2P_RFOFF2_INT_8814B BIT(10) +#define BIT_FS_P2P_RFON1_INT_8814B BIT(9) +#define BIT_FS_P2P_RFOFF1_INT_8814B BIT(8) +#define BIT_FS_P2P_RFON0_INT_8814B BIT(7) +#define BIT_FS_P2P_RFOFF0_INT_8814B BIT(6) +#define BIT_FS_RX_UAPSDMD1_INT_8814B BIT(5) +#define BIT_FS_RX_UAPSDMD0_INT_8814B BIT(4) +#define BIT_FS_TRIGGER_PKT_INT_8814B BIT(3) +#define BIT_FS_EOSP_INT_8814B BIT(2) +#define BIT_FS_RPWM2_INT_8814B BIT(1) +#define BIT_FS_RPWM_INT_8814B BIT(0) + +/* 2 REG_SPWR0_8814B */ + +#define BIT_SHIFT_MID_31TO0_8814B 0 +#define BIT_MASK_MID_31TO0_8814B 0xffffffffL +#define BIT_MID_31TO0_8814B(x) (((x) & BIT_MASK_MID_31TO0_8814B) << BIT_SHIFT_MID_31TO0_8814B) +#define BIT_GET_MID_31TO0_8814B(x) (((x) >> BIT_SHIFT_MID_31TO0_8814B) & BIT_MASK_MID_31TO0_8814B) + + + +/* 2 REG_SPWR1_8814B */ + +#define BIT_SHIFT_MID_63TO32_8814B 0 +#define BIT_MASK_MID_63TO32_8814B 0xffffffffL +#define BIT_MID_63TO32_8814B(x) (((x) & BIT_MASK_MID_63TO32_8814B) << BIT_SHIFT_MID_63TO32_8814B) +#define BIT_GET_MID_63TO32_8814B(x) (((x) >> BIT_SHIFT_MID_63TO32_8814B) & BIT_MASK_MID_63TO32_8814B) + + + +/* 2 REG_SPWR2_8814B */ + +#define BIT_SHIFT_MID_95O64_8814B 0 +#define BIT_MASK_MID_95O64_8814B 0xffffffffL +#define BIT_MID_95O64_8814B(x) (((x) & BIT_MASK_MID_95O64_8814B) << BIT_SHIFT_MID_95O64_8814B) +#define BIT_GET_MID_95O64_8814B(x) (((x) >> BIT_SHIFT_MID_95O64_8814B) & BIT_MASK_MID_95O64_8814B) + + + +/* 2 REG_SPWR3_8814B */ + +#define BIT_SHIFT_MID_127TO96_8814B 0 +#define BIT_MASK_MID_127TO96_8814B 0xffffffffL +#define BIT_MID_127TO96_8814B(x) (((x) & BIT_MASK_MID_127TO96_8814B) << BIT_SHIFT_MID_127TO96_8814B) +#define BIT_GET_MID_127TO96_8814B(x) (((x) >> BIT_SHIFT_MID_127TO96_8814B) & BIT_MASK_MID_127TO96_8814B) + + + +/* 2 REG_POWSEQ_8814B */ + +#define BIT_SHIFT_SEQNUM_MID_8814B 16 +#define BIT_MASK_SEQNUM_MID_8814B 0xffff +#define BIT_SEQNUM_MID_8814B(x) (((x) & BIT_MASK_SEQNUM_MID_8814B) << BIT_SHIFT_SEQNUM_MID_8814B) +#define BIT_GET_SEQNUM_MID_8814B(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8814B) & BIT_MASK_SEQNUM_MID_8814B) + + + +#define BIT_SHIFT_REF_MID_8814B 0 +#define BIT_MASK_REF_MID_8814B 0x7f +#define BIT_REF_MID_8814B(x) (((x) & BIT_MASK_REF_MID_8814B) << BIT_SHIFT_REF_MID_8814B) +#define BIT_GET_REF_MID_8814B(x) (((x) >> BIT_SHIFT_REF_MID_8814B) & BIT_MASK_REF_MID_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_TC7_CTRL_V1_8814B */ +#define BIT_TC7INT_EN_8814B BIT(26) +#define BIT_TC7MODE_8814B BIT(25) +#define BIT_TC7EN_8814B BIT(24) + +#define BIT_SHIFT_TC7DATA_8814B 0 +#define BIT_MASK_TC7DATA_8814B 0xffffff +#define BIT_TC7DATA_8814B(x) (((x) & BIT_MASK_TC7DATA_8814B) << BIT_SHIFT_TC7DATA_8814B) +#define BIT_GET_TC7DATA_8814B(x) (((x) >> BIT_SHIFT_TC7DATA_8814B) & BIT_MASK_TC7DATA_8814B) + + + +/* 2 REG_TC8_CTRL_V1_8814B */ +#define BIT_TC8INT_EN_8814B BIT(26) +#define BIT_TC8MODE_8814B BIT(25) +#define BIT_TC8EN_8814B BIT(24) + +#define BIT_SHIFT_TC8DATA_8814B 0 +#define BIT_MASK_TC8DATA_8814B 0xffffff +#define BIT_TC8DATA_8814B(x) (((x) & BIT_MASK_TC8DATA_8814B) << BIT_SHIFT_TC8DATA_8814B) +#define BIT_GET_TC8DATA_8814B(x) (((x) >> BIT_SHIFT_TC8DATA_8814B) & BIT_MASK_TC8DATA_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_FT2IMR_8814B */ +#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8814B BIT(31) +#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8814B BIT(30) +#define BIT_FS_CLI3_TRIGGER_PKT_EN_8814B BIT(29) +#define BIT_FS_CLI3_EOSP_INT_EN_8814B BIT(28) +#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8814B BIT(27) +#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8814B BIT(26) +#define BIT_FS_CLI2_TRIGGER_PKT_EN_8814B BIT(25) +#define BIT_FS_CLI2_EOSP_INT_EN_8814B BIT(24) +#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8814B BIT(23) +#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8814B BIT(22) +#define BIT_FS_CLI1_TRIGGER_PKT_EN_8814B BIT(21) +#define BIT_FS_CLI1_EOSP_INT_EN_8814B BIT(20) +#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8814B BIT(19) +#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8814B BIT(18) +#define BIT_FS_CLI0_TRIGGER_PKT_EN_8814B BIT(17) +#define BIT_FS_CLI0_EOSP_INT_EN_8814B BIT(16) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8814B BIT(9) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8814B BIT(8) +#define BIT_FS_CLI3_TX_NULL1_INT_EN_8814B BIT(7) +#define BIT_FS_CLI3_TX_NULL0_INT_EN_8814B BIT(6) +#define BIT_FS_CLI2_TX_NULL1_INT_EN_8814B BIT(5) +#define BIT_FS_CLI2_TX_NULL0_INT_EN_8814B BIT(4) +#define BIT_FS_CLI1_TX_NULL1_INT_EN_8814B BIT(3) +#define BIT_FS_CLI1_TX_NULL0_INT_EN_8814B BIT(2) +#define BIT_FS_CLI0_TX_NULL1_INT_EN_8814B BIT(1) +#define BIT_FS_CLI0_TX_NULL0_INT_EN_8814B BIT(0) + +/* 2 REG_FT2ISR_8814B */ +#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8814B BIT(31) +#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8814B BIT(30) +#define BIT_FS_CLI3_TRIGGER_PKT_INT_8814B BIT(29) +#define BIT_FS_CLI3_EOSP_INT_8814B BIT(28) +#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8814B BIT(27) +#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8814B BIT(26) +#define BIT_FS_CLI2_TRIGGER_PKT_INT_8814B BIT(25) +#define BIT_FS_CLI2_EOSP_INT_8814B BIT(24) +#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8814B BIT(23) +#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8814B BIT(22) +#define BIT_FS_CLI1_TRIGGER_PKT_INT_8814B BIT(21) +#define BIT_FS_CLI1_EOSP_INT_8814B BIT(20) +#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8814B BIT(19) +#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8814B BIT(18) +#define BIT_FS_CLI0_TRIGGER_PKT_INT_8814B BIT(17) +#define BIT_FS_CLI0_EOSP_INT_8814B BIT(16) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8814B BIT(9) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8814B BIT(8) +#define BIT_FS_CLI3_TX_NULL1_INT_8814B BIT(7) +#define BIT_FS_CLI3_TX_NULL0_INT_8814B BIT(6) +#define BIT_FS_CLI2_TX_NULL1_INT_8814B BIT(5) +#define BIT_FS_CLI2_TX_NULL0_INT_8814B BIT(4) +#define BIT_FS_CLI1_TX_NULL1_INT_8814B BIT(3) +#define BIT_FS_CLI1_TX_NULL0_INT_8814B BIT(2) +#define BIT_FS_CLI0_TX_NULL1_INT_8814B BIT(1) +#define BIT_FS_CLI0_TX_NULL0_INT_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_MSG2_8814B */ + +#define BIT_SHIFT_FW_MSG2_8814B 0 +#define BIT_MASK_FW_MSG2_8814B 0xffffffffL +#define BIT_FW_MSG2_8814B(x) (((x) & BIT_MASK_FW_MSG2_8814B) << BIT_SHIFT_FW_MSG2_8814B) +#define BIT_GET_FW_MSG2_8814B(x) (((x) >> BIT_SHIFT_FW_MSG2_8814B) & BIT_MASK_FW_MSG2_8814B) + + + +/* 2 REG_MSG3_8814B */ + +#define BIT_SHIFT_FW_MSG3_8814B 0 +#define BIT_MASK_FW_MSG3_8814B 0xffffffffL +#define BIT_FW_MSG3_8814B(x) (((x) & BIT_MASK_FW_MSG3_8814B) << BIT_SHIFT_FW_MSG3_8814B) +#define BIT_GET_FW_MSG3_8814B(x) (((x) >> BIT_SHIFT_FW_MSG3_8814B) & BIT_MASK_FW_MSG3_8814B) + + + +/* 2 REG_MSG4_8814B */ + +#define BIT_SHIFT_FW_MSG4_8814B 0 +#define BIT_MASK_FW_MSG4_8814B 0xffffffffL +#define BIT_FW_MSG4_8814B(x) (((x) & BIT_MASK_FW_MSG4_8814B) << BIT_SHIFT_FW_MSG4_8814B) +#define BIT_GET_FW_MSG4_8814B(x) (((x) >> BIT_SHIFT_FW_MSG4_8814B) & BIT_MASK_FW_MSG4_8814B) + + + +/* 2 REG_MSG5_8814B */ + +#define BIT_SHIFT_FW_MSG5_8814B 0 +#define BIT_MASK_FW_MSG5_8814B 0xffffffffL +#define BIT_FW_MSG5_8814B(x) (((x) & BIT_MASK_FW_MSG5_8814B) << BIT_SHIFT_FW_MSG5_8814B) +#define BIT_GET_FW_MSG5_8814B(x) (((x) >> BIT_SHIFT_FW_MSG5_8814B) & BIT_MASK_FW_MSG5_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_FIFOPAGE_CTRL_1_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8814B 16 +#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8814B 0xff +#define BIT_TX_OQT_HE_FREE_SPACE_V1_8814B(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8814B) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8814B) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8814B(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8814B) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8814B 0 +#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8814B 0xff +#define BIT_TX_OQT_NL_FREE_SPACE_V1_8814B(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8814B) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8814B) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8814B(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8814B) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8814B) + + + +/* 2 REG_FIFOPAGE_CTRL_2_8814B */ +#define BIT_BCN_VALID_1_V1_8814B BIT(31) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_BCN_HEAD_1_V1_8814B 16 +#define BIT_MASK_BCN_HEAD_1_V1_8814B 0xfff +#define BIT_BCN_HEAD_1_V1_8814B(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8814B) << BIT_SHIFT_BCN_HEAD_1_V1_8814B) +#define BIT_GET_BCN_HEAD_1_V1_8814B(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8814B) & BIT_MASK_BCN_HEAD_1_V1_8814B) + + +#define BIT_BCN_VALID_V1_8814B BIT(15) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_BCN_HEAD_V1_8814B 0 +#define BIT_MASK_BCN_HEAD_V1_8814B 0xfff +#define BIT_BCN_HEAD_V1_8814B(x) (((x) & BIT_MASK_BCN_HEAD_V1_8814B) << BIT_SHIFT_BCN_HEAD_V1_8814B) +#define BIT_GET_BCN_HEAD_V1_8814B(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8814B) & BIT_MASK_BCN_HEAD_V1_8814B) + + + +/* 2 REG_AUTO_LLT_V1_8814B */ + +#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B 24 +#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B 0xff +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B) + + + +#define BIT_SHIFT_LLT_FREE_PAGE_V1_8814B 8 +#define BIT_MASK_LLT_FREE_PAGE_V1_8814B 0xffff +#define BIT_LLT_FREE_PAGE_V1_8814B(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8814B) << BIT_SHIFT_LLT_FREE_PAGE_V1_8814B) +#define BIT_GET_LLT_FREE_PAGE_V1_8814B(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8814B) & BIT_MASK_LLT_FREE_PAGE_V1_8814B) + + + +#define BIT_SHIFT_BLK_DESC_NUM_8814B 4 +#define BIT_MASK_BLK_DESC_NUM_8814B 0xf +#define BIT_BLK_DESC_NUM_8814B(x) (((x) & BIT_MASK_BLK_DESC_NUM_8814B) << BIT_SHIFT_BLK_DESC_NUM_8814B) +#define BIT_GET_BLK_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8814B) & BIT_MASK_BLK_DESC_NUM_8814B) + + +#define BIT_R_BCN_HEAD_SEL_8814B BIT(3) +#define BIT_R_EN_BCN_SW_HEAD_SEL_8814B BIT(2) +#define BIT_LLT_DBG_SEL_8814B BIT(1) +#define BIT_AUTO_INIT_LLT_V1_8814B BIT(0) + +/* 2 REG_TXDMA_OFFSET_CHK_8814B */ +#define BIT_EM_CHKSUM_FIN_8814B BIT(31) +#define BIT_EMN_PCIE_DMA_MOD_8814B BIT(30) +#define BIT_EN_TXQUE_CLR_8814B BIT(29) +#define BIT_EN_PCIE_FIFO_MODE_8814B BIT(28) + +#define BIT_SHIFT_PG_UNDER_TH_V1_8814B 16 +#define BIT_MASK_PG_UNDER_TH_V1_8814B 0xfff +#define BIT_PG_UNDER_TH_V1_8814B(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8814B) << BIT_SHIFT_PG_UNDER_TH_V1_8814B) +#define BIT_GET_PG_UNDER_TH_V1_8814B(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8814B) & BIT_MASK_PG_UNDER_TH_V1_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SDIO_TXDESC_CHKSUM_EN_8814B BIT(13) +#define BIT_RST_RDPTR_8814B BIT(12) +#define BIT_RST_WRPTR_8814B BIT(11) +#define BIT_CHK_PG_TH_EN_8814B BIT(10) +#define BIT_DROP_DATA_EN_8814B BIT(9) +#define BIT_CHECK_OFFSET_EN_8814B BIT(8) + +#define BIT_SHIFT_CHECK_OFFSET_8814B 0 +#define BIT_MASK_CHECK_OFFSET_8814B 0xff +#define BIT_CHECK_OFFSET_8814B(x) (((x) & BIT_MASK_CHECK_OFFSET_8814B) << BIT_SHIFT_CHECK_OFFSET_8814B) +#define BIT_GET_CHECK_OFFSET_8814B(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8814B) & BIT_MASK_CHECK_OFFSET_8814B) + + + +/* 2 REG_TXDMA_STATUS_8814B */ +#define BIT_TXPKTBUF_REQ_ERR_8814B BIT(18) +#define BIT_HI_OQT_UDN_8814B BIT(17) +#define BIT_HI_OQT_OVF_8814B BIT(16) +#define BIT_PAYLOAD_CHKSUM_ERR_8814B BIT(15) +#define BIT_PAYLOAD_UDN_8814B BIT(14) +#define BIT_PAYLOAD_OVF_8814B BIT(13) +#define BIT_DSC_CHKSUM_FAIL_8814B BIT(12) +#define BIT_UNKNOWN_QSEL_8814B BIT(11) +#define BIT_EP_QSEL_DIFF_8814B BIT(10) +#define BIT_TX_OFFS_UNMATCH_8814B BIT(9) +#define BIT_TXOQT_UDN_8814B BIT(8) +#define BIT_TXOQT_OVF_8814B BIT(7) +#define BIT_TXDMA_SFF_UDN_8814B BIT(6) +#define BIT_TXDMA_SFF_OVF_8814B BIT(5) +#define BIT_LLT_NULL_PG_8814B BIT(4) +#define BIT_PAGE_UDN_8814B BIT(3) +#define BIT_PAGE_OVF_8814B BIT(2) +#define BIT_TXFF_PG_UDN_8814B BIT(1) +#define BIT_TXFF_PG_OVF_8814B BIT(0) + +/* 2 REG_TX_DMA_DBG_8814B */ + +/* 2 REG_TQPNT1_8814B */ + +#define BIT_SHIFT_HPQ_HIGH_TH_V1_8814B 16 +#define BIT_MASK_HPQ_HIGH_TH_V1_8814B 0xfff +#define BIT_HPQ_HIGH_TH_V1_8814B(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8814B) << BIT_SHIFT_HPQ_HIGH_TH_V1_8814B) +#define BIT_GET_HPQ_HIGH_TH_V1_8814B(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8814B) & BIT_MASK_HPQ_HIGH_TH_V1_8814B) + + + +#define BIT_SHIFT_HPQ_LOW_TH_V1_8814B 0 +#define BIT_MASK_HPQ_LOW_TH_V1_8814B 0xfff +#define BIT_HPQ_LOW_TH_V1_8814B(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8814B) << BIT_SHIFT_HPQ_LOW_TH_V1_8814B) +#define BIT_GET_HPQ_LOW_TH_V1_8814B(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8814B) & BIT_MASK_HPQ_LOW_TH_V1_8814B) + + + +/* 2 REG_TQPNT2_8814B */ + +#define BIT_SHIFT_NPQ_HIGH_TH_V1_8814B 16 +#define BIT_MASK_NPQ_HIGH_TH_V1_8814B 0xfff +#define BIT_NPQ_HIGH_TH_V1_8814B(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8814B) << BIT_SHIFT_NPQ_HIGH_TH_V1_8814B) +#define BIT_GET_NPQ_HIGH_TH_V1_8814B(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8814B) & BIT_MASK_NPQ_HIGH_TH_V1_8814B) + + + +#define BIT_SHIFT_NPQ_LOW_TH_V1_8814B 0 +#define BIT_MASK_NPQ_LOW_TH_V1_8814B 0xfff +#define BIT_NPQ_LOW_TH_V1_8814B(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8814B) << BIT_SHIFT_NPQ_LOW_TH_V1_8814B) +#define BIT_GET_NPQ_LOW_TH_V1_8814B(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8814B) & BIT_MASK_NPQ_LOW_TH_V1_8814B) + + + +/* 2 REG_TQPNT3_8814B */ + +#define BIT_SHIFT_LPQ_HIGH_TH_V1_8814B 16 +#define BIT_MASK_LPQ_HIGH_TH_V1_8814B 0xfff +#define BIT_LPQ_HIGH_TH_V1_8814B(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8814B) << BIT_SHIFT_LPQ_HIGH_TH_V1_8814B) +#define BIT_GET_LPQ_HIGH_TH_V1_8814B(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8814B) & BIT_MASK_LPQ_HIGH_TH_V1_8814B) + + + +#define BIT_SHIFT_LPQ_LOW_TH_V1_8814B 0 +#define BIT_MASK_LPQ_LOW_TH_V1_8814B 0xfff +#define BIT_LPQ_LOW_TH_V1_8814B(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8814B) << BIT_SHIFT_LPQ_LOW_TH_V1_8814B) +#define BIT_GET_LPQ_LOW_TH_V1_8814B(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8814B) & BIT_MASK_LPQ_LOW_TH_V1_8814B) + + + +/* 2 REG_TQPNT4_8814B */ + +#define BIT_SHIFT_EXQ_HIGH_TH_V1_8814B 16 +#define BIT_MASK_EXQ_HIGH_TH_V1_8814B 0xfff +#define BIT_EXQ_HIGH_TH_V1_8814B(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8814B) << BIT_SHIFT_EXQ_HIGH_TH_V1_8814B) +#define BIT_GET_EXQ_HIGH_TH_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8814B) & BIT_MASK_EXQ_HIGH_TH_V1_8814B) + + + +#define BIT_SHIFT_EXQ_LOW_TH_V1_8814B 0 +#define BIT_MASK_EXQ_LOW_TH_V1_8814B 0xfff +#define BIT_EXQ_LOW_TH_V1_8814B(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8814B) << BIT_SHIFT_EXQ_LOW_TH_V1_8814B) +#define BIT_GET_EXQ_LOW_TH_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8814B) & BIT_MASK_EXQ_LOW_TH_V1_8814B) + + + +/* 2 REG_RQPN_CTRL_1_8814B */ + +#define BIT_SHIFT_TXPKTNUM_H_8814B 16 +#define BIT_MASK_TXPKTNUM_H_8814B 0xffff +#define BIT_TXPKTNUM_H_8814B(x) (((x) & BIT_MASK_TXPKTNUM_H_8814B) << BIT_SHIFT_TXPKTNUM_H_8814B) +#define BIT_GET_TXPKTNUM_H_8814B(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8814B) & BIT_MASK_TXPKTNUM_H_8814B) + + + +#define BIT_SHIFT_TXPKTNUM_V2_8814B 0 +#define BIT_MASK_TXPKTNUM_V2_8814B 0xffff +#define BIT_TXPKTNUM_V2_8814B(x) (((x) & BIT_MASK_TXPKTNUM_V2_8814B) << BIT_SHIFT_TXPKTNUM_V2_8814B) +#define BIT_GET_TXPKTNUM_V2_8814B(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2_8814B) & BIT_MASK_TXPKTNUM_V2_8814B) + + + +/* 2 REG_RQPN_CTRL_2_8814B */ +#define BIT_LD_RQPN_8814B BIT(31) +#define BIT_EXQ_PUBLIC_DIS_V1_8814B BIT(19) +#define BIT_NPQ_PUBLIC_DIS_V1_8814B BIT(18) +#define BIT_LPQ_PUBLIC_DIS_V1_8814B BIT(17) +#define BIT_HPQ_PUBLIC_DIS_V1_8814B BIT(16) +#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_8814B BIT(15) + +#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8814B 0 +#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8814B 0xfff +#define BIT_SDIO_TXAGG_ALIGN_SIZE_8814B(x) (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8814B) << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8814B) +#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8814B(x) (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8814B) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8814B) + + + +/* 2 REG_FIFOPAGE_INFO_1_8814B */ + +#define BIT_SHIFT_HPQ_AVAL_PG_V1_8814B 16 +#define BIT_MASK_HPQ_AVAL_PG_V1_8814B 0xfff +#define BIT_HPQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8814B) << BIT_SHIFT_HPQ_AVAL_PG_V1_8814B) +#define BIT_GET_HPQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8814B) & BIT_MASK_HPQ_AVAL_PG_V1_8814B) + + + +#define BIT_SHIFT_HPQ_V1_8814B 0 +#define BIT_MASK_HPQ_V1_8814B 0xfff +#define BIT_HPQ_V1_8814B(x) (((x) & BIT_MASK_HPQ_V1_8814B) << BIT_SHIFT_HPQ_V1_8814B) +#define BIT_GET_HPQ_V1_8814B(x) (((x) >> BIT_SHIFT_HPQ_V1_8814B) & BIT_MASK_HPQ_V1_8814B) + + + +/* 2 REG_FIFOPAGE_INFO_2_8814B */ + +#define BIT_SHIFT_LPQ_AVAL_PG_V1_8814B 16 +#define BIT_MASK_LPQ_AVAL_PG_V1_8814B 0xfff +#define BIT_LPQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8814B) << BIT_SHIFT_LPQ_AVAL_PG_V1_8814B) +#define BIT_GET_LPQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8814B) & BIT_MASK_LPQ_AVAL_PG_V1_8814B) + + + +#define BIT_SHIFT_LPQ_V1_8814B 0 +#define BIT_MASK_LPQ_V1_8814B 0xfff +#define BIT_LPQ_V1_8814B(x) (((x) & BIT_MASK_LPQ_V1_8814B) << BIT_SHIFT_LPQ_V1_8814B) +#define BIT_GET_LPQ_V1_8814B(x) (((x) >> BIT_SHIFT_LPQ_V1_8814B) & BIT_MASK_LPQ_V1_8814B) + + + +/* 2 REG_FIFOPAGE_INFO_3_8814B */ + +#define BIT_SHIFT_NPQ_AVAL_PG_V1_8814B 16 +#define BIT_MASK_NPQ_AVAL_PG_V1_8814B 0xfff +#define BIT_NPQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8814B) << BIT_SHIFT_NPQ_AVAL_PG_V1_8814B) +#define BIT_GET_NPQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8814B) & BIT_MASK_NPQ_AVAL_PG_V1_8814B) + + + +#define BIT_SHIFT_NPQ_V1_8814B 0 +#define BIT_MASK_NPQ_V1_8814B 0xfff +#define BIT_NPQ_V1_8814B(x) (((x) & BIT_MASK_NPQ_V1_8814B) << BIT_SHIFT_NPQ_V1_8814B) +#define BIT_GET_NPQ_V1_8814B(x) (((x) >> BIT_SHIFT_NPQ_V1_8814B) & BIT_MASK_NPQ_V1_8814B) + + + +/* 2 REG_FIFOPAGE_INFO_4_8814B */ + +#define BIT_SHIFT_EXQ_AVAL_PG_V1_8814B 16 +#define BIT_MASK_EXQ_AVAL_PG_V1_8814B 0xfff +#define BIT_EXQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8814B) << BIT_SHIFT_EXQ_AVAL_PG_V1_8814B) +#define BIT_GET_EXQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8814B) & BIT_MASK_EXQ_AVAL_PG_V1_8814B) + + + +#define BIT_SHIFT_EXQ_V1_8814B 0 +#define BIT_MASK_EXQ_V1_8814B 0xfff +#define BIT_EXQ_V1_8814B(x) (((x) & BIT_MASK_EXQ_V1_8814B) << BIT_SHIFT_EXQ_V1_8814B) +#define BIT_GET_EXQ_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_V1_8814B) & BIT_MASK_EXQ_V1_8814B) + + + +/* 2 REG_FIFOPAGE_INFO_5_8814B */ + +#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8814B 16 +#define BIT_MASK_PUBQ_AVAL_PG_V1_8814B 0xfff +#define BIT_PUBQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8814B) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8814B) +#define BIT_GET_PUBQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8814B) & BIT_MASK_PUBQ_AVAL_PG_V1_8814B) + + + +#define BIT_SHIFT_PUBQ_V1_8814B 0 +#define BIT_MASK_PUBQ_V1_8814B 0xfff +#define BIT_PUBQ_V1_8814B(x) (((x) & BIT_MASK_PUBQ_V1_8814B) << BIT_SHIFT_PUBQ_V1_8814B) +#define BIT_GET_PUBQ_V1_8814B(x) (((x) >> BIT_SHIFT_PUBQ_V1_8814B) & BIT_MASK_PUBQ_V1_8814B) + + + +/* 2 REG_H2C_HEAD_8814B */ + +#define BIT_SHIFT_H2C_HEAD_8814B 0 +#define BIT_MASK_H2C_HEAD_8814B 0x3ffff +#define BIT_H2C_HEAD_8814B(x) (((x) & BIT_MASK_H2C_HEAD_8814B) << BIT_SHIFT_H2C_HEAD_8814B) +#define BIT_GET_H2C_HEAD_8814B(x) (((x) >> BIT_SHIFT_H2C_HEAD_8814B) & BIT_MASK_H2C_HEAD_8814B) + + + +/* 2 REG_H2C_TAIL_8814B */ + +#define BIT_SHIFT_H2C_TAIL_8814B 0 +#define BIT_MASK_H2C_TAIL_8814B 0x3ffff +#define BIT_H2C_TAIL_8814B(x) (((x) & BIT_MASK_H2C_TAIL_8814B) << BIT_SHIFT_H2C_TAIL_8814B) +#define BIT_GET_H2C_TAIL_8814B(x) (((x) >> BIT_SHIFT_H2C_TAIL_8814B) & BIT_MASK_H2C_TAIL_8814B) + + + +/* 2 REG_H2C_READ_ADDR_8814B */ + +#define BIT_SHIFT_H2C_READ_ADDR_8814B 0 +#define BIT_MASK_H2C_READ_ADDR_8814B 0x3ffff +#define BIT_H2C_READ_ADDR_8814B(x) (((x) & BIT_MASK_H2C_READ_ADDR_8814B) << BIT_SHIFT_H2C_READ_ADDR_8814B) +#define BIT_GET_H2C_READ_ADDR_8814B(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8814B) & BIT_MASK_H2C_READ_ADDR_8814B) + + + +/* 2 REG_H2C_WR_ADDR_8814B */ + +#define BIT_SHIFT_H2C_WR_ADDR_8814B 0 +#define BIT_MASK_H2C_WR_ADDR_8814B 0x3ffff +#define BIT_H2C_WR_ADDR_8814B(x) (((x) & BIT_MASK_H2C_WR_ADDR_8814B) << BIT_SHIFT_H2C_WR_ADDR_8814B) +#define BIT_GET_H2C_WR_ADDR_8814B(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8814B) & BIT_MASK_H2C_WR_ADDR_8814B) + + + +/* 2 REG_H2C_INFO_8814B */ +#define BIT_H2C_SPACE_VLD_8814B BIT(3) +#define BIT_H2C_WR_ADDR_RST_8814B BIT(2) + +#define BIT_SHIFT_H2C_LEN_SEL_8814B 0 +#define BIT_MASK_H2C_LEN_SEL_8814B 0x3 +#define BIT_H2C_LEN_SEL_8814B(x) (((x) & BIT_MASK_H2C_LEN_SEL_8814B) << BIT_SHIFT_H2C_LEN_SEL_8814B) +#define BIT_GET_H2C_LEN_SEL_8814B(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8814B) & BIT_MASK_H2C_LEN_SEL_8814B) + + + +/* 2 REG_RXDMA_AGG_PG_TH_8814B */ + +#define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8814B 24 +#define BIT_MASK_RXDMA_AGG_OLD_MOD_8814B 0xff +#define BIT_RXDMA_AGG_OLD_MOD_8814B(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD_8814B) << BIT_SHIFT_RXDMA_AGG_OLD_MOD_8814B) +#define BIT_GET_RXDMA_AGG_OLD_MOD_8814B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8814B) & BIT_MASK_RXDMA_AGG_OLD_MOD_8814B) + + + +#define BIT_SHIFT_PKT_NUM_WOL_8814B 16 +#define BIT_MASK_PKT_NUM_WOL_8814B 0xff +#define BIT_PKT_NUM_WOL_8814B(x) (((x) & BIT_MASK_PKT_NUM_WOL_8814B) << BIT_SHIFT_PKT_NUM_WOL_8814B) +#define BIT_GET_PKT_NUM_WOL_8814B(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8814B) & BIT_MASK_PKT_NUM_WOL_8814B) + + + +#define BIT_SHIFT_DMA_AGG_TO_8814B 8 +#define BIT_MASK_DMA_AGG_TO_8814B 0xf +#define BIT_DMA_AGG_TO_8814B(x) (((x) & BIT_MASK_DMA_AGG_TO_8814B) << BIT_SHIFT_DMA_AGG_TO_8814B) +#define BIT_GET_DMA_AGG_TO_8814B(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_8814B) & BIT_MASK_DMA_AGG_TO_8814B) + + + +#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8814B 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_V1_8814B 0xf +#define BIT_RXDMA_AGG_PG_TH_V1_8814B(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8814B) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8814B) +#define BIT_GET_RXDMA_AGG_PG_TH_V1_8814B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8814B) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8814B) + + + +/* 2 REG_RXPKT_NUM_8814B */ + +#define BIT_SHIFT_RXPKT_NUM_8814B 24 +#define BIT_MASK_RXPKT_NUM_8814B 0xff +#define BIT_RXPKT_NUM_8814B(x) (((x) & BIT_MASK_RXPKT_NUM_8814B) << BIT_SHIFT_RXPKT_NUM_8814B) +#define BIT_GET_RXPKT_NUM_8814B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8814B) & BIT_MASK_RXPKT_NUM_8814B) + + + +#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B 20 +#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B 0xf +#define BIT_FW_UPD_RDPTR19_TO_16_8814B(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8814B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B) + + +#define BIT_RXDMA_REQ_8814B BIT(19) +#define BIT_RW_RELEASE_EN_8814B BIT(18) +#define BIT_RXDMA_IDLE_8814B BIT(17) +#define BIT_RXPKT_RELEASE_POLL_8814B BIT(16) + +#define BIT_SHIFT_FW_UPD_RDPTR_8814B 0 +#define BIT_MASK_FW_UPD_RDPTR_8814B 0xffff +#define BIT_FW_UPD_RDPTR_8814B(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8814B) << BIT_SHIFT_FW_UPD_RDPTR_8814B) +#define BIT_GET_FW_UPD_RDPTR_8814B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8814B) & BIT_MASK_FW_UPD_RDPTR_8814B) + + + +/* 2 REG_RXDMA_STATUS_8814B */ +#define BIT_C2H_PKT_OVF_8814B BIT(7) +#define BIT_AGG_CONFGI_ISSUE_8814B BIT(6) +#define BIT_FW_POLL_ISSUE_8814B BIT(5) +#define BIT_RX_DATA_UDN_8814B BIT(4) +#define BIT_RX_SFF_UDN_8814B BIT(3) +#define BIT_RX_SFF_OVF_8814B BIT(2) +#define BIT_RXPKT_OVF_8814B BIT(0) + +/* 2 REG_RXDMA_DPR_8814B */ + +#define BIT_SHIFT_RDE_DEBUG_8814B 0 +#define BIT_MASK_RDE_DEBUG_8814B 0xffffffffL +#define BIT_RDE_DEBUG_8814B(x) (((x) & BIT_MASK_RDE_DEBUG_8814B) << BIT_SHIFT_RDE_DEBUG_8814B) +#define BIT_GET_RDE_DEBUG_8814B(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8814B) & BIT_MASK_RDE_DEBUG_8814B) + + + +/* 2 REG_RXDMA_MODE_8814B */ + +#define BIT_SHIFT_PKTNUM_TH_V2_8814B 24 +#define BIT_MASK_PKTNUM_TH_V2_8814B 0x1f +#define BIT_PKTNUM_TH_V2_8814B(x) (((x) & BIT_MASK_PKTNUM_TH_V2_8814B) << BIT_SHIFT_PKTNUM_TH_V2_8814B) +#define BIT_GET_PKTNUM_TH_V2_8814B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8814B) & BIT_MASK_PKTNUM_TH_V2_8814B) + + +#define BIT_TXBA_BREAK_USBAGG_8814B BIT(23) + +#define BIT_SHIFT_PKTLEN_PARA_8814B 16 +#define BIT_MASK_PKTLEN_PARA_8814B 0x7 +#define BIT_PKTLEN_PARA_8814B(x) (((x) & BIT_MASK_PKTLEN_PARA_8814B) << BIT_SHIFT_PKTLEN_PARA_8814B) +#define BIT_GET_PKTLEN_PARA_8814B(x) (((x) >> BIT_SHIFT_PKTLEN_PARA_8814B) & BIT_MASK_PKTLEN_PARA_8814B) + + + +#define BIT_SHIFT_BURST_SIZE_8814B 4 +#define BIT_MASK_BURST_SIZE_8814B 0x3 +#define BIT_BURST_SIZE_8814B(x) (((x) & BIT_MASK_BURST_SIZE_8814B) << BIT_SHIFT_BURST_SIZE_8814B) +#define BIT_GET_BURST_SIZE_8814B(x) (((x) >> BIT_SHIFT_BURST_SIZE_8814B) & BIT_MASK_BURST_SIZE_8814B) + + + +#define BIT_SHIFT_BURST_CNT_8814B 2 +#define BIT_MASK_BURST_CNT_8814B 0x3 +#define BIT_BURST_CNT_8814B(x) (((x) & BIT_MASK_BURST_CNT_8814B) << BIT_SHIFT_BURST_CNT_8814B) +#define BIT_GET_BURST_CNT_8814B(x) (((x) >> BIT_SHIFT_BURST_CNT_8814B) & BIT_MASK_BURST_CNT_8814B) + + +#define BIT_DMA_MODE_8814B BIT(1) + +/* 2 REG_C2H_PKT_8814B */ + +#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B 24 +#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B 0xf +#define BIT_R_C2H_STR_ADDR_16_TO_19_8814B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8814B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B) + + +#define BIT_R_C2H_PKT_REQ_8814B BIT(16) + +#define BIT_SHIFT_R_C2H_STR_ADDR_8814B 0 +#define BIT_MASK_R_C2H_STR_ADDR_8814B 0xffff +#define BIT_R_C2H_STR_ADDR_8814B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8814B) << BIT_SHIFT_R_C2H_STR_ADDR_8814B) +#define BIT_GET_R_C2H_STR_ADDR_8814B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8814B) & BIT_MASK_R_C2H_STR_ADDR_8814B) + + + +/* 2 REG_FWFF_C2H_8814B */ + +#define BIT_SHIFT_C2H_DMA_ADDR_8814B 0 +#define BIT_MASK_C2H_DMA_ADDR_8814B 0x3ffff +#define BIT_C2H_DMA_ADDR_8814B(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8814B) << BIT_SHIFT_C2H_DMA_ADDR_8814B) +#define BIT_GET_C2H_DMA_ADDR_8814B(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8814B) & BIT_MASK_C2H_DMA_ADDR_8814B) + + + +/* 2 REG_FWFF_CTRL_8814B */ +#define BIT_FWFF_DMAPKT_REQ_8814B BIT(31) + +#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8814B 16 +#define BIT_MASK_FWFF_DMA_PKT_NUM_8814B 0xff +#define BIT_FWFF_DMA_PKT_NUM_8814B(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8814B) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8814B) +#define BIT_GET_FWFF_DMA_PKT_NUM_8814B(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8814B) & BIT_MASK_FWFF_DMA_PKT_NUM_8814B) + + + +#define BIT_SHIFT_FWFF_STR_ADDR_8814B 0 +#define BIT_MASK_FWFF_STR_ADDR_8814B 0xffff +#define BIT_FWFF_STR_ADDR_8814B(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8814B) << BIT_SHIFT_FWFF_STR_ADDR_8814B) +#define BIT_GET_FWFF_STR_ADDR_8814B(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8814B) & BIT_MASK_FWFF_STR_ADDR_8814B) + + + +/* 2 REG_FWFF_PKT_INFO_8814B */ + +#define BIT_SHIFT_FWFF_PKT_QUEUED_8814B 16 +#define BIT_MASK_FWFF_PKT_QUEUED_8814B 0xff +#define BIT_FWFF_PKT_QUEUED_8814B(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8814B) << BIT_SHIFT_FWFF_PKT_QUEUED_8814B) +#define BIT_GET_FWFF_PKT_QUEUED_8814B(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8814B) & BIT_MASK_FWFF_PKT_QUEUED_8814B) + + + +#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8814B 0 +#define BIT_MASK_FWFF_PKT_STR_ADDR_8814B 0xffff +#define BIT_FWFF_PKT_STR_ADDR_8814B(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8814B) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8814B) +#define BIT_GET_FWFF_PKT_STR_ADDR_8814B(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8814B) & BIT_MASK_FWFF_PKT_STR_ADDR_8814B) + + + +/* 2 REG_DDMA_CH0SA_8814B */ + +#define BIT_SHIFT_DDMACH0_SA_8814B 0 +#define BIT_MASK_DDMACH0_SA_8814B 0xffffffffL +#define BIT_DDMACH0_SA_8814B(x) (((x) & BIT_MASK_DDMACH0_SA_8814B) << BIT_SHIFT_DDMACH0_SA_8814B) +#define BIT_GET_DDMACH0_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8814B) & BIT_MASK_DDMACH0_SA_8814B) + + + +/* 2 REG_DDMA_CH0DA_8814B */ + +#define BIT_SHIFT_DDMACH0_DA_8814B 0 +#define BIT_MASK_DDMACH0_DA_8814B 0xffffffffL +#define BIT_DDMACH0_DA_8814B(x) (((x) & BIT_MASK_DDMACH0_DA_8814B) << BIT_SHIFT_DDMACH0_DA_8814B) +#define BIT_GET_DDMACH0_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8814B) & BIT_MASK_DDMACH0_DA_8814B) + + + +/* 2 REG_DDMA_CH0CTRL_8814B */ +#define BIT_DDMACH0_OWN_8814B BIT(31) +#define BIT_DDMACH0_CHKSUM_EN_8814B BIT(29) +#define BIT_DDMACH0_DA_W_DISABLE_8814B BIT(28) +#define BIT_DDMACH0_CHKSUM_STS_8814B BIT(27) +#define BIT_DDMACH0_DDMA_MODE_8814B BIT(26) +#define BIT_DDMACH0_RESET_CHKSUM_STS_8814B BIT(25) +#define BIT_DDMACH0_CHKSUM_CONT_8814B BIT(24) + +#define BIT_SHIFT_DDMACH0_DLEN_8814B 0 +#define BIT_MASK_DDMACH0_DLEN_8814B 0x3ffff +#define BIT_DDMACH0_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH0_DLEN_8814B) << BIT_SHIFT_DDMACH0_DLEN_8814B) +#define BIT_GET_DDMACH0_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8814B) & BIT_MASK_DDMACH0_DLEN_8814B) + + + +/* 2 REG_DDMA_CH1SA_8814B */ + +#define BIT_SHIFT_DDMACH1_SA_8814B 0 +#define BIT_MASK_DDMACH1_SA_8814B 0xffffffffL +#define BIT_DDMACH1_SA_8814B(x) (((x) & BIT_MASK_DDMACH1_SA_8814B) << BIT_SHIFT_DDMACH1_SA_8814B) +#define BIT_GET_DDMACH1_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8814B) & BIT_MASK_DDMACH1_SA_8814B) + + + +/* 2 REG_DDMA_CH1DA_8814B */ + +#define BIT_SHIFT_DDMACH1_DA_8814B 0 +#define BIT_MASK_DDMACH1_DA_8814B 0xffffffffL +#define BIT_DDMACH1_DA_8814B(x) (((x) & BIT_MASK_DDMACH1_DA_8814B) << BIT_SHIFT_DDMACH1_DA_8814B) +#define BIT_GET_DDMACH1_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8814B) & BIT_MASK_DDMACH1_DA_8814B) + + + +/* 2 REG_DDMA_CH1CTRL_8814B */ +#define BIT_DDMACH1_OWN_8814B BIT(31) +#define BIT_DDMACH1_CHKSUM_EN_8814B BIT(29) +#define BIT_DDMACH1_DA_W_DISABLE_8814B BIT(28) +#define BIT_DDMACH1_CHKSUM_STS_8814B BIT(27) +#define BIT_DDMACH1_DDMA_MODE_8814B BIT(26) +#define BIT_DDMACH1_RESET_CHKSUM_STS_8814B BIT(25) +#define BIT_DDMACH1_CHKSUM_CONT_8814B BIT(24) + +#define BIT_SHIFT_DDMACH1_DLEN_8814B 0 +#define BIT_MASK_DDMACH1_DLEN_8814B 0x3ffff +#define BIT_DDMACH1_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH1_DLEN_8814B) << BIT_SHIFT_DDMACH1_DLEN_8814B) +#define BIT_GET_DDMACH1_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8814B) & BIT_MASK_DDMACH1_DLEN_8814B) + + + +/* 2 REG_DDMA_CH2SA_8814B */ + +#define BIT_SHIFT_DDMACH2_SA_8814B 0 +#define BIT_MASK_DDMACH2_SA_8814B 0xffffffffL +#define BIT_DDMACH2_SA_8814B(x) (((x) & BIT_MASK_DDMACH2_SA_8814B) << BIT_SHIFT_DDMACH2_SA_8814B) +#define BIT_GET_DDMACH2_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8814B) & BIT_MASK_DDMACH2_SA_8814B) + + + +/* 2 REG_DDMA_CH2DA_8814B */ + +#define BIT_SHIFT_DDMACH2_DA_8814B 0 +#define BIT_MASK_DDMACH2_DA_8814B 0xffffffffL +#define BIT_DDMACH2_DA_8814B(x) (((x) & BIT_MASK_DDMACH2_DA_8814B) << BIT_SHIFT_DDMACH2_DA_8814B) +#define BIT_GET_DDMACH2_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8814B) & BIT_MASK_DDMACH2_DA_8814B) + + + +/* 2 REG_DDMA_CH2CTRL_8814B */ +#define BIT_DDMACH2_OWN_8814B BIT(31) +#define BIT_DDMACH2_CHKSUM_EN_8814B BIT(29) +#define BIT_DDMACH2_DA_W_DISABLE_8814B BIT(28) +#define BIT_DDMACH2_CHKSUM_STS_8814B BIT(27) +#define BIT_DDMACH2_DDMA_MODE_8814B BIT(26) +#define BIT_DDMACH2_RESET_CHKSUM_STS_8814B BIT(25) +#define BIT_DDMACH2_CHKSUM_CONT_8814B BIT(24) + +#define BIT_SHIFT_DDMACH2_DLEN_8814B 0 +#define BIT_MASK_DDMACH2_DLEN_8814B 0x3ffff +#define BIT_DDMACH2_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH2_DLEN_8814B) << BIT_SHIFT_DDMACH2_DLEN_8814B) +#define BIT_GET_DDMACH2_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8814B) & BIT_MASK_DDMACH2_DLEN_8814B) + + + +/* 2 REG_DDMA_CH3SA_8814B */ + +#define BIT_SHIFT_DDMACH3_SA_8814B 0 +#define BIT_MASK_DDMACH3_SA_8814B 0xffffffffL +#define BIT_DDMACH3_SA_8814B(x) (((x) & BIT_MASK_DDMACH3_SA_8814B) << BIT_SHIFT_DDMACH3_SA_8814B) +#define BIT_GET_DDMACH3_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8814B) & BIT_MASK_DDMACH3_SA_8814B) + + + +/* 2 REG_DDMA_CH3DA_8814B */ + +#define BIT_SHIFT_DDMACH3_DA_8814B 0 +#define BIT_MASK_DDMACH3_DA_8814B 0xffffffffL +#define BIT_DDMACH3_DA_8814B(x) (((x) & BIT_MASK_DDMACH3_DA_8814B) << BIT_SHIFT_DDMACH3_DA_8814B) +#define BIT_GET_DDMACH3_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8814B) & BIT_MASK_DDMACH3_DA_8814B) + + + +/* 2 REG_DDMA_CH3CTRL_8814B */ +#define BIT_DDMACH3_OWN_8814B BIT(31) +#define BIT_DDMACH3_CHKSUM_EN_8814B BIT(29) +#define BIT_DDMACH3_DA_W_DISABLE_8814B BIT(28) +#define BIT_DDMACH3_CHKSUM_STS_8814B BIT(27) +#define BIT_DDMACH3_DDMA_MODE_8814B BIT(26) +#define BIT_DDMACH3_RESET_CHKSUM_STS_8814B BIT(25) +#define BIT_DDMACH3_CHKSUM_CONT_8814B BIT(24) + +#define BIT_SHIFT_DDMACH3_DLEN_8814B 0 +#define BIT_MASK_DDMACH3_DLEN_8814B 0x3ffff +#define BIT_DDMACH3_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH3_DLEN_8814B) << BIT_SHIFT_DDMACH3_DLEN_8814B) +#define BIT_GET_DDMACH3_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8814B) & BIT_MASK_DDMACH3_DLEN_8814B) + + + +/* 2 REG_DDMA_CH4SA_8814B */ + +#define BIT_SHIFT_DDMACH4_SA_8814B 0 +#define BIT_MASK_DDMACH4_SA_8814B 0xffffffffL +#define BIT_DDMACH4_SA_8814B(x) (((x) & BIT_MASK_DDMACH4_SA_8814B) << BIT_SHIFT_DDMACH4_SA_8814B) +#define BIT_GET_DDMACH4_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8814B) & BIT_MASK_DDMACH4_SA_8814B) + + + +/* 2 REG_DDMA_CH4DA_8814B */ + +#define BIT_SHIFT_DDMACH4_DA_8814B 0 +#define BIT_MASK_DDMACH4_DA_8814B 0xffffffffL +#define BIT_DDMACH4_DA_8814B(x) (((x) & BIT_MASK_DDMACH4_DA_8814B) << BIT_SHIFT_DDMACH4_DA_8814B) +#define BIT_GET_DDMACH4_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8814B) & BIT_MASK_DDMACH4_DA_8814B) + + + +/* 2 REG_DDMA_CH4CTRL_8814B */ +#define BIT_DDMACH4_OWN_8814B BIT(31) +#define BIT_DDMACH4_CHKSUM_EN_8814B BIT(29) +#define BIT_DDMACH4_DA_W_DISABLE_8814B BIT(28) +#define BIT_DDMACH4_CHKSUM_STS_8814B BIT(27) +#define BIT_DDMACH4_DDMA_MODE_8814B BIT(26) +#define BIT_DDMACH4_RESET_CHKSUM_STS_8814B BIT(25) +#define BIT_DDMACH4_CHKSUM_CONT_8814B BIT(24) + +#define BIT_SHIFT_DDMACH4_DLEN_8814B 0 +#define BIT_MASK_DDMACH4_DLEN_8814B 0x3ffff +#define BIT_DDMACH4_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH4_DLEN_8814B) << BIT_SHIFT_DDMACH4_DLEN_8814B) +#define BIT_GET_DDMACH4_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8814B) & BIT_MASK_DDMACH4_DLEN_8814B) + + + +/* 2 REG_DDMA_CH5SA_8814B */ + +#define BIT_SHIFT_DDMACH5_SA_8814B 0 +#define BIT_MASK_DDMACH5_SA_8814B 0xffffffffL +#define BIT_DDMACH5_SA_8814B(x) (((x) & BIT_MASK_DDMACH5_SA_8814B) << BIT_SHIFT_DDMACH5_SA_8814B) +#define BIT_GET_DDMACH5_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8814B) & BIT_MASK_DDMACH5_SA_8814B) + + + +/* 2 REG_DDMA_CH5DA_8814B */ + +#define BIT_SHIFT_DDMACH5_DA_8814B 0 +#define BIT_MASK_DDMACH5_DA_8814B 0xffffffffL +#define BIT_DDMACH5_DA_8814B(x) (((x) & BIT_MASK_DDMACH5_DA_8814B) << BIT_SHIFT_DDMACH5_DA_8814B) +#define BIT_GET_DDMACH5_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8814B) & BIT_MASK_DDMACH5_DA_8814B) + + + +/* 2 REG_DDMA_CH5CTRL_8814B */ +#define BIT_DDMACH5_OWN_8814B BIT(31) +#define BIT_DDMACH5_CHKSUM_EN_8814B BIT(29) +#define BIT_DDMACH5_DA_W_DISABLE_8814B BIT(28) +#define BIT_DDMACH5_CHKSUM_STS_8814B BIT(27) +#define BIT_DDMACH5_DDMA_MODE_8814B BIT(26) +#define BIT_DDMACH5_RESET_CHKSUM_STS_8814B BIT(25) +#define BIT_DDMACH5_CHKSUM_CONT_8814B BIT(24) + +#define BIT_SHIFT_DDMACH5_DLEN_8814B 0 +#define BIT_MASK_DDMACH5_DLEN_8814B 0x3ffff +#define BIT_DDMACH5_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH5_DLEN_8814B) << BIT_SHIFT_DDMACH5_DLEN_8814B) +#define BIT_GET_DDMACH5_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8814B) & BIT_MASK_DDMACH5_DLEN_8814B) + + + +/* 2 REG_DDMA_INT_MSK_8814B */ +#define BIT_DDMACH5_MSK_8814B BIT(5) +#define BIT_DDMACH4_MSK_8814B BIT(4) +#define BIT_DDMACH3_MSK_8814B BIT(3) +#define BIT_DDMACH2_MSK_8814B BIT(2) +#define BIT_DDMACH1_MSK_8814B BIT(1) +#define BIT_DDMACH0_MSK_8814B BIT(0) + +/* 2 REG_DDMA_CHSTATUS_8814B */ +#define BIT_DDMACH5_BUSY_8814B BIT(5) +#define BIT_DDMACH4_BUSY_8814B BIT(4) +#define BIT_DDMACH3_BUSY_8814B BIT(3) +#define BIT_DDMACH2_BUSY_8814B BIT(2) +#define BIT_DDMACH1_BUSY_8814B BIT(1) +#define BIT_DDMACH0_BUSY_8814B BIT(0) + +/* 2 REG_DDMA_CHKSUM_8814B */ + +#define BIT_SHIFT_IDDMA0_CHKSUM_8814B 0 +#define BIT_MASK_IDDMA0_CHKSUM_8814B 0xffff +#define BIT_IDDMA0_CHKSUM_8814B(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8814B) << BIT_SHIFT_IDDMA0_CHKSUM_8814B) +#define BIT_GET_IDDMA0_CHKSUM_8814B(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8814B) & BIT_MASK_IDDMA0_CHKSUM_8814B) + + + +/* 2 REG_DDMA_MONITOR_8814B */ +#define BIT_IDDMA0_PERMU_UNDERFLOW_8814B BIT(14) +#define BIT_IDDMA0_FIFO_UNDERFLOW_8814B BIT(13) +#define BIT_IDDMA0_FIFO_OVERFLOW_8814B BIT(12) +#define BIT_CH5_ERR_8814B BIT(5) +#define BIT_CH4_ERR_8814B BIT(4) +#define BIT_CH3_ERR_8814B BIT(3) +#define BIT_CH2_ERR_8814B BIT(2) +#define BIT_CH1_ERR_8814B BIT(1) +#define BIT_CH0_ERR_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_PCIE_CTRL_8814B */ +#define BIT_PCIEIO_PERSTB_SEL_8814B BIT(31) + +#define BIT_SHIFT_PCIE_MAX_RXDMA_8814B 28 +#define BIT_MASK_PCIE_MAX_RXDMA_8814B 0x7 +#define BIT_PCIE_MAX_RXDMA_8814B(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA_8814B) << BIT_SHIFT_PCIE_MAX_RXDMA_8814B) +#define BIT_GET_PCIE_MAX_RXDMA_8814B(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8814B) & BIT_MASK_PCIE_MAX_RXDMA_8814B) + + +#define BIT_MULRW_8814B BIT(27) + +#define BIT_SHIFT_PCIE_MAX_TXDMA_8814B 24 +#define BIT_MASK_PCIE_MAX_TXDMA_8814B 0x7 +#define BIT_PCIE_MAX_TXDMA_8814B(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA_8814B) << BIT_SHIFT_PCIE_MAX_TXDMA_8814B) +#define BIT_GET_PCIE_MAX_TXDMA_8814B(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8814B) & BIT_MASK_PCIE_MAX_TXDMA_8814B) + + +#define BIT_EN_CPL_TIMEOUT_PS_8814B BIT(22) +#define BIT_REG_TXDMA_FAIL_PS_8814B BIT(21) +#define BIT_PCIE_RST_TRXDMA_INTF_8814B BIT(20) +#define BIT_EN_HWENTR_L1_8814B BIT(19) +#define BIT_EN_ADV_CLKGATE_8814B BIT(18) +#define BIT_PCIE_EN_SWENT_L23_8814B BIT(17) +#define BIT_PCIE_EN_HWEXT_L1_8814B BIT(16) +#define BIT_RX_CLOSE_EN_8814B BIT(15) +#define BIT_STOP_BCNQ_8814B BIT(14) +#define BIT_STOP_MGQ_8814B BIT(13) +#define BIT_STOP_VOQ_8814B BIT(12) +#define BIT_STOP_VIQ_8814B BIT(11) +#define BIT_STOP_BEQ_8814B BIT(10) +#define BIT_STOP_BKQ_8814B BIT(9) +#define BIT_STOP_RXQ_8814B BIT(8) +#define BIT_STOP_HI7Q_8814B BIT(7) +#define BIT_STOP_HI6Q_8814B BIT(6) +#define BIT_STOP_HI5Q_8814B BIT(5) +#define BIT_STOP_HI4Q_8814B BIT(4) +#define BIT_STOP_HI3Q_8814B BIT(3) +#define BIT_STOP_HI2Q_8814B BIT(2) +#define BIT_STOP_HI1Q_8814B BIT(1) +#define BIT_STOP_HI0Q_8814B BIT(0) + +/* 2 REG_INT_MIG_8814B */ + +#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B 28 +#define BIT_MASK_TXTTIMER_MATCH_NUM_8814B 0xf +#define BIT_TXTTIMER_MATCH_NUM_8814B(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8814B) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) +#define BIT_GET_TXTTIMER_MATCH_NUM_8814B(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) & BIT_MASK_TXTTIMER_MATCH_NUM_8814B) + + + +#define BIT_SHIFT_TXPKT_NUM_MATCH_8814B 24 +#define BIT_MASK_TXPKT_NUM_MATCH_8814B 0xf +#define BIT_TXPKT_NUM_MATCH_8814B(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8814B) << BIT_SHIFT_TXPKT_NUM_MATCH_8814B) +#define BIT_GET_TXPKT_NUM_MATCH_8814B(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8814B) & BIT_MASK_TXPKT_NUM_MATCH_8814B) + + + +#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B 20 +#define BIT_MASK_RXTTIMER_MATCH_NUM_8814B 0xf +#define BIT_RXTTIMER_MATCH_NUM_8814B(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8814B) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) +#define BIT_GET_RXTTIMER_MATCH_NUM_8814B(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) & BIT_MASK_RXTTIMER_MATCH_NUM_8814B) + + + +#define BIT_SHIFT_RXPKT_NUM_MATCH_8814B 16 +#define BIT_MASK_RXPKT_NUM_MATCH_8814B 0xf +#define BIT_RXPKT_NUM_MATCH_8814B(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8814B) << BIT_SHIFT_RXPKT_NUM_MATCH_8814B) +#define BIT_GET_RXPKT_NUM_MATCH_8814B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8814B) & BIT_MASK_RXPKT_NUM_MATCH_8814B) + + + +#define BIT_SHIFT_MIGRATE_TIMER_8814B 0 +#define BIT_MASK_MIGRATE_TIMER_8814B 0xffff +#define BIT_MIGRATE_TIMER_8814B(x) (((x) & BIT_MASK_MIGRATE_TIMER_8814B) << BIT_SHIFT_MIGRATE_TIMER_8814B) +#define BIT_GET_MIGRATE_TIMER_8814B(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8814B) & BIT_MASK_MIGRATE_TIMER_8814B) + + + +/* 2 REG_BCNQ_TXBD_DESA_8814B */ + +#define BIT_SHIFT_BCNQ_TXBD_DESA_8814B 0 +#define BIT_MASK_BCNQ_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_BCNQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8814B) << BIT_SHIFT_BCNQ_TXBD_DESA_8814B) +#define BIT_GET_BCNQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8814B) & BIT_MASK_BCNQ_TXBD_DESA_8814B) + + + +/* 2 REG_MGQ_TXBD_DESA_8814B */ + +#define BIT_SHIFT_MGQ_TXBD_DESA_8814B 0 +#define BIT_MASK_MGQ_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_MGQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8814B) << BIT_SHIFT_MGQ_TXBD_DESA_8814B) +#define BIT_GET_MGQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8814B) & BIT_MASK_MGQ_TXBD_DESA_8814B) + + + +/* 2 REG_VOQ_TXBD_DESA_8814B */ + +#define BIT_SHIFT_VOQ_TXBD_DESA_8814B 0 +#define BIT_MASK_VOQ_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_VOQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8814B) << BIT_SHIFT_VOQ_TXBD_DESA_8814B) +#define BIT_GET_VOQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8814B) & BIT_MASK_VOQ_TXBD_DESA_8814B) + + + +/* 2 REG_VIQ_TXBD_DESA_8814B */ + +#define BIT_SHIFT_VIQ_TXBD_DESA_8814B 0 +#define BIT_MASK_VIQ_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_VIQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8814B) << BIT_SHIFT_VIQ_TXBD_DESA_8814B) +#define BIT_GET_VIQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8814B) & BIT_MASK_VIQ_TXBD_DESA_8814B) + + + +/* 2 REG_BEQ_TXBD_DESA_8814B */ + +#define BIT_SHIFT_BEQ_TXBD_DESA_8814B 0 +#define BIT_MASK_BEQ_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_BEQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8814B) << BIT_SHIFT_BEQ_TXBD_DESA_8814B) +#define BIT_GET_BEQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8814B) & BIT_MASK_BEQ_TXBD_DESA_8814B) + + + +/* 2 REG_BKQ_TXBD_DESA_8814B */ + +#define BIT_SHIFT_BKQ_TXBD_DESA_8814B 0 +#define BIT_MASK_BKQ_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_BKQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8814B) << BIT_SHIFT_BKQ_TXBD_DESA_8814B) +#define BIT_GET_BKQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8814B) & BIT_MASK_BKQ_TXBD_DESA_8814B) + + + +/* 2 REG_RXQ_RXBD_DESA_8814B */ + +#define BIT_SHIFT_RXQ_RXBD_DESA_8814B 0 +#define BIT_MASK_RXQ_RXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_RXQ_RXBD_DESA_8814B(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8814B) << BIT_SHIFT_RXQ_RXBD_DESA_8814B) +#define BIT_GET_RXQ_RXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8814B) & BIT_MASK_RXQ_RXBD_DESA_8814B) + + + +/* 2 REG_HI0Q_TXBD_DESA_8814B */ + +#define BIT_SHIFT_HI0Q_TXBD_DESA_8814B 0 +#define BIT_MASK_HI0Q_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_HI0Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8814B) << BIT_SHIFT_HI0Q_TXBD_DESA_8814B) +#define BIT_GET_HI0Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8814B) & BIT_MASK_HI0Q_TXBD_DESA_8814B) + + + +/* 2 REG_HI1Q_TXBD_DESA_8814B */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_8814B 0 +#define BIT_MASK_HI1Q_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_HI1Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8814B) << BIT_SHIFT_HI1Q_TXBD_DESA_8814B) +#define BIT_GET_HI1Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8814B) & BIT_MASK_HI1Q_TXBD_DESA_8814B) + + + +/* 2 REG_HI2Q_TXBD_DESA_8814B */ + +#define BIT_SHIFT_HI2Q_TXBD_DESA_8814B 0 +#define BIT_MASK_HI2Q_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_HI2Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8814B) << BIT_SHIFT_HI2Q_TXBD_DESA_8814B) +#define BIT_GET_HI2Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8814B) & BIT_MASK_HI2Q_TXBD_DESA_8814B) + + + +/* 2 REG_HI3Q_TXBD_DESA_8814B */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_8814B 0 +#define BIT_MASK_HI3Q_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_HI3Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8814B) << BIT_SHIFT_HI3Q_TXBD_DESA_8814B) +#define BIT_GET_HI3Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8814B) & BIT_MASK_HI3Q_TXBD_DESA_8814B) + + + +/* 2 REG_HI4Q_TXBD_DESA_8814B */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_8814B 0 +#define BIT_MASK_HI4Q_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_HI4Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8814B) << BIT_SHIFT_HI4Q_TXBD_DESA_8814B) +#define BIT_GET_HI4Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8814B) & BIT_MASK_HI4Q_TXBD_DESA_8814B) + + + +/* 2 REG_HI5Q_TXBD_DESA_8814B */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_8814B 0 +#define BIT_MASK_HI5Q_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_HI5Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8814B) << BIT_SHIFT_HI5Q_TXBD_DESA_8814B) +#define BIT_GET_HI5Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8814B) & BIT_MASK_HI5Q_TXBD_DESA_8814B) + + + +/* 2 REG_HI6Q_TXBD_DESA_8814B */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_8814B 0 +#define BIT_MASK_HI6Q_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_HI6Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8814B) << BIT_SHIFT_HI6Q_TXBD_DESA_8814B) +#define BIT_GET_HI6Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8814B) & BIT_MASK_HI6Q_TXBD_DESA_8814B) + + + +/* 2 REG_HI7Q_TXBD_DESA_8814B */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_8814B 0 +#define BIT_MASK_HI7Q_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_HI7Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8814B) << BIT_SHIFT_HI7Q_TXBD_DESA_8814B) +#define BIT_GET_HI7Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8814B) & BIT_MASK_HI7Q_TXBD_DESA_8814B) + + + +/* 2 REG_MGQ_TXBD_NUM_8814B */ +#define BIT_PCIE_MGQ_FLAG_8814B BIT(14) + +#define BIT_SHIFT_MGQ_DESC_MODE_8814B 12 +#define BIT_MASK_MGQ_DESC_MODE_8814B 0x3 +#define BIT_MGQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8814B) << BIT_SHIFT_MGQ_DESC_MODE_8814B) +#define BIT_GET_MGQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8814B) & BIT_MASK_MGQ_DESC_MODE_8814B) + + + +#define BIT_SHIFT_MGQ_DESC_NUM_8814B 0 +#define BIT_MASK_MGQ_DESC_NUM_8814B 0xfff +#define BIT_MGQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8814B) << BIT_SHIFT_MGQ_DESC_NUM_8814B) +#define BIT_GET_MGQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8814B) & BIT_MASK_MGQ_DESC_NUM_8814B) + + + +/* 2 REG_RX_RXBD_NUM_8814B */ +#define BIT_SYS_32_64_8814B BIT(15) + +#define BIT_SHIFT_BCNQ_DESC_MODE_8814B 13 +#define BIT_MASK_BCNQ_DESC_MODE_8814B 0x3 +#define BIT_BCNQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8814B) << BIT_SHIFT_BCNQ_DESC_MODE_8814B) +#define BIT_GET_BCNQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8814B) & BIT_MASK_BCNQ_DESC_MODE_8814B) + + +#define BIT_PCIE_BCNQ_FLAG_8814B BIT(12) + +#define BIT_SHIFT_RXQ_DESC_NUM_8814B 0 +#define BIT_MASK_RXQ_DESC_NUM_8814B 0xfff +#define BIT_RXQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8814B) << BIT_SHIFT_RXQ_DESC_NUM_8814B) +#define BIT_GET_RXQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8814B) & BIT_MASK_RXQ_DESC_NUM_8814B) + + + +/* 2 REG_VOQ_TXBD_NUM_8814B */ +#define BIT_PCIE_VOQ_FLAG_8814B BIT(14) + +#define BIT_SHIFT_VOQ_DESC_MODE_8814B 12 +#define BIT_MASK_VOQ_DESC_MODE_8814B 0x3 +#define BIT_VOQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8814B) << BIT_SHIFT_VOQ_DESC_MODE_8814B) +#define BIT_GET_VOQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8814B) & BIT_MASK_VOQ_DESC_MODE_8814B) + + + +#define BIT_SHIFT_VOQ_DESC_NUM_8814B 0 +#define BIT_MASK_VOQ_DESC_NUM_8814B 0xfff +#define BIT_VOQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8814B) << BIT_SHIFT_VOQ_DESC_NUM_8814B) +#define BIT_GET_VOQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8814B) & BIT_MASK_VOQ_DESC_NUM_8814B) + + + +/* 2 REG_VIQ_TXBD_NUM_8814B */ +#define BIT_PCIE_VIQ_FLAG_8814B BIT(14) + +#define BIT_SHIFT_VIQ_DESC_MODE_8814B 12 +#define BIT_MASK_VIQ_DESC_MODE_8814B 0x3 +#define BIT_VIQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8814B) << BIT_SHIFT_VIQ_DESC_MODE_8814B) +#define BIT_GET_VIQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8814B) & BIT_MASK_VIQ_DESC_MODE_8814B) + + + +#define BIT_SHIFT_VIQ_DESC_NUM_8814B 0 +#define BIT_MASK_VIQ_DESC_NUM_8814B 0xfff +#define BIT_VIQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8814B) << BIT_SHIFT_VIQ_DESC_NUM_8814B) +#define BIT_GET_VIQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8814B) & BIT_MASK_VIQ_DESC_NUM_8814B) + + + +/* 2 REG_BEQ_TXBD_NUM_8814B */ +#define BIT_PCIE_BEQ_FLAG_8814B BIT(14) + +#define BIT_SHIFT_BEQ_DESC_MODE_8814B 12 +#define BIT_MASK_BEQ_DESC_MODE_8814B 0x3 +#define BIT_BEQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8814B) << BIT_SHIFT_BEQ_DESC_MODE_8814B) +#define BIT_GET_BEQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8814B) & BIT_MASK_BEQ_DESC_MODE_8814B) + + + +#define BIT_SHIFT_BEQ_DESC_NUM_8814B 0 +#define BIT_MASK_BEQ_DESC_NUM_8814B 0xfff +#define BIT_BEQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8814B) << BIT_SHIFT_BEQ_DESC_NUM_8814B) +#define BIT_GET_BEQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8814B) & BIT_MASK_BEQ_DESC_NUM_8814B) + + + +/* 2 REG_BKQ_TXBD_NUM_8814B */ +#define BIT_PCIE_BKQ_FLAG_8814B BIT(14) + +#define BIT_SHIFT_BKQ_DESC_MODE_8814B 12 +#define BIT_MASK_BKQ_DESC_MODE_8814B 0x3 +#define BIT_BKQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8814B) << BIT_SHIFT_BKQ_DESC_MODE_8814B) +#define BIT_GET_BKQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8814B) & BIT_MASK_BKQ_DESC_MODE_8814B) + + + +#define BIT_SHIFT_BKQ_DESC_NUM_8814B 0 +#define BIT_MASK_BKQ_DESC_NUM_8814B 0xfff +#define BIT_BKQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8814B) << BIT_SHIFT_BKQ_DESC_NUM_8814B) +#define BIT_GET_BKQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8814B) & BIT_MASK_BKQ_DESC_NUM_8814B) + + + +/* 2 REG_HI0Q_TXBD_NUM_8814B */ +#define BIT_HI0Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_HI0Q_DESC_MODE_8814B 12 +#define BIT_MASK_HI0Q_DESC_MODE_8814B 0x3 +#define BIT_HI0Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8814B) << BIT_SHIFT_HI0Q_DESC_MODE_8814B) +#define BIT_GET_HI0Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8814B) & BIT_MASK_HI0Q_DESC_MODE_8814B) + + + +#define BIT_SHIFT_HI0Q_DESC_NUM_8814B 0 +#define BIT_MASK_HI0Q_DESC_NUM_8814B 0xfff +#define BIT_HI0Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8814B) << BIT_SHIFT_HI0Q_DESC_NUM_8814B) +#define BIT_GET_HI0Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8814B) & BIT_MASK_HI0Q_DESC_NUM_8814B) + + + +/* 2 REG_HI1Q_TXBD_NUM_8814B */ +#define BIT_HI1Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_HI1Q_DESC_MODE_8814B 12 +#define BIT_MASK_HI1Q_DESC_MODE_8814B 0x3 +#define BIT_HI1Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8814B) << BIT_SHIFT_HI1Q_DESC_MODE_8814B) +#define BIT_GET_HI1Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8814B) & BIT_MASK_HI1Q_DESC_MODE_8814B) + + + +#define BIT_SHIFT_HI1Q_DESC_NUM_8814B 0 +#define BIT_MASK_HI1Q_DESC_NUM_8814B 0xfff +#define BIT_HI1Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8814B) << BIT_SHIFT_HI1Q_DESC_NUM_8814B) +#define BIT_GET_HI1Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8814B) & BIT_MASK_HI1Q_DESC_NUM_8814B) + + + +/* 2 REG_HI2Q_TXBD_NUM_8814B */ +#define BIT_HI2Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_HI2Q_DESC_MODE_8814B 12 +#define BIT_MASK_HI2Q_DESC_MODE_8814B 0x3 +#define BIT_HI2Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8814B) << BIT_SHIFT_HI2Q_DESC_MODE_8814B) +#define BIT_GET_HI2Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8814B) & BIT_MASK_HI2Q_DESC_MODE_8814B) + + + +#define BIT_SHIFT_HI2Q_DESC_NUM_8814B 0 +#define BIT_MASK_HI2Q_DESC_NUM_8814B 0xfff +#define BIT_HI2Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8814B) << BIT_SHIFT_HI2Q_DESC_NUM_8814B) +#define BIT_GET_HI2Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8814B) & BIT_MASK_HI2Q_DESC_NUM_8814B) + + + +/* 2 REG_HI3Q_TXBD_NUM_8814B */ +#define BIT_HI3Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_HI3Q_DESC_MODE_8814B 12 +#define BIT_MASK_HI3Q_DESC_MODE_8814B 0x3 +#define BIT_HI3Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8814B) << BIT_SHIFT_HI3Q_DESC_MODE_8814B) +#define BIT_GET_HI3Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8814B) & BIT_MASK_HI3Q_DESC_MODE_8814B) + + + +#define BIT_SHIFT_HI3Q_DESC_NUM_8814B 0 +#define BIT_MASK_HI3Q_DESC_NUM_8814B 0xfff +#define BIT_HI3Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8814B) << BIT_SHIFT_HI3Q_DESC_NUM_8814B) +#define BIT_GET_HI3Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8814B) & BIT_MASK_HI3Q_DESC_NUM_8814B) + + + +/* 2 REG_HI4Q_TXBD_NUM_8814B */ +#define BIT_HI4Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_HI4Q_DESC_MODE_8814B 12 +#define BIT_MASK_HI4Q_DESC_MODE_8814B 0x3 +#define BIT_HI4Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8814B) << BIT_SHIFT_HI4Q_DESC_MODE_8814B) +#define BIT_GET_HI4Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8814B) & BIT_MASK_HI4Q_DESC_MODE_8814B) + + + +#define BIT_SHIFT_HI4Q_DESC_NUM_8814B 0 +#define BIT_MASK_HI4Q_DESC_NUM_8814B 0xfff +#define BIT_HI4Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8814B) << BIT_SHIFT_HI4Q_DESC_NUM_8814B) +#define BIT_GET_HI4Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8814B) & BIT_MASK_HI4Q_DESC_NUM_8814B) + + + +/* 2 REG_HI5Q_TXBD_NUM_8814B */ +#define BIT_HI5Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_HI5Q_DESC_MODE_8814B 12 +#define BIT_MASK_HI5Q_DESC_MODE_8814B 0x3 +#define BIT_HI5Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8814B) << BIT_SHIFT_HI5Q_DESC_MODE_8814B) +#define BIT_GET_HI5Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8814B) & BIT_MASK_HI5Q_DESC_MODE_8814B) + + + +#define BIT_SHIFT_HI5Q_DESC_NUM_8814B 0 +#define BIT_MASK_HI5Q_DESC_NUM_8814B 0xfff +#define BIT_HI5Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8814B) << BIT_SHIFT_HI5Q_DESC_NUM_8814B) +#define BIT_GET_HI5Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8814B) & BIT_MASK_HI5Q_DESC_NUM_8814B) + + + +/* 2 REG_HI6Q_TXBD_NUM_8814B */ +#define BIT_HI6Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_HI6Q_DESC_MODE_8814B 12 +#define BIT_MASK_HI6Q_DESC_MODE_8814B 0x3 +#define BIT_HI6Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8814B) << BIT_SHIFT_HI6Q_DESC_MODE_8814B) +#define BIT_GET_HI6Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8814B) & BIT_MASK_HI6Q_DESC_MODE_8814B) + + + +#define BIT_SHIFT_HI6Q_DESC_NUM_8814B 0 +#define BIT_MASK_HI6Q_DESC_NUM_8814B 0xfff +#define BIT_HI6Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8814B) << BIT_SHIFT_HI6Q_DESC_NUM_8814B) +#define BIT_GET_HI6Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8814B) & BIT_MASK_HI6Q_DESC_NUM_8814B) + + + +/* 2 REG_HI7Q_TXBD_NUM_8814B */ +#define BIT_HI7Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_HI7Q_DESC_MODE_8814B 12 +#define BIT_MASK_HI7Q_DESC_MODE_8814B 0x3 +#define BIT_HI7Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8814B) << BIT_SHIFT_HI7Q_DESC_MODE_8814B) +#define BIT_GET_HI7Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8814B) & BIT_MASK_HI7Q_DESC_MODE_8814B) + + + +#define BIT_SHIFT_HI7Q_DESC_NUM_8814B 0 +#define BIT_MASK_HI7Q_DESC_NUM_8814B 0xfff +#define BIT_HI7Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8814B) << BIT_SHIFT_HI7Q_DESC_NUM_8814B) +#define BIT_GET_HI7Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8814B) & BIT_MASK_HI7Q_DESC_NUM_8814B) + + + +/* 2 REG_TSFTIMER_HCI_8814B */ + +#define BIT_SHIFT_TSFT2_HCI_8814B 16 +#define BIT_MASK_TSFT2_HCI_8814B 0xffff +#define BIT_TSFT2_HCI_8814B(x) (((x) & BIT_MASK_TSFT2_HCI_8814B) << BIT_SHIFT_TSFT2_HCI_8814B) +#define BIT_GET_TSFT2_HCI_8814B(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8814B) & BIT_MASK_TSFT2_HCI_8814B) + + + +#define BIT_SHIFT_TSFT1_HCI_8814B 0 +#define BIT_MASK_TSFT1_HCI_8814B 0xffff +#define BIT_TSFT1_HCI_8814B(x) (((x) & BIT_MASK_TSFT1_HCI_8814B) << BIT_SHIFT_TSFT1_HCI_8814B) +#define BIT_GET_TSFT1_HCI_8814B(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8814B) & BIT_MASK_TSFT1_HCI_8814B) + + + +/* 2 REG_BD_RWPTR_CLR_8814B */ +#define BIT_CLR_HI7Q_HW_IDX_8814B BIT(29) +#define BIT_CLR_HI6Q_HW_IDX_8814B BIT(28) +#define BIT_CLR_HI5Q_HW_IDX_8814B BIT(27) +#define BIT_CLR_HI4Q_HW_IDX_8814B BIT(26) +#define BIT_CLR_HI3Q_HW_IDX_8814B BIT(25) +#define BIT_CLR_HI2Q_HW_IDX_8814B BIT(24) +#define BIT_CLR_HI1Q_HW_IDX_8814B BIT(23) +#define BIT_CLR_HI0Q_HW_IDX_8814B BIT(22) +#define BIT_CLR_BKQ_HW_IDX_8814B BIT(21) +#define BIT_CLR_BEQ_HW_IDX_8814B BIT(20) +#define BIT_CLR_VIQ_HW_IDX_8814B BIT(19) +#define BIT_CLR_VOQ_HW_IDX_8814B BIT(18) +#define BIT_CLR_MGQ_HW_IDX_8814B BIT(17) +#define BIT_CLR_RXQ_HW_IDX_8814B BIT(16) +#define BIT_CLR_HI7Q_HOST_IDX_8814B BIT(13) +#define BIT_CLR_HI6Q_HOST_IDX_8814B BIT(12) +#define BIT_CLR_HI5Q_HOST_IDX_8814B BIT(11) +#define BIT_CLR_HI4Q_HOST_IDX_8814B BIT(10) +#define BIT_CLR_HI3Q_HOST_IDX_8814B BIT(9) +#define BIT_CLR_HI2Q_HOST_IDX_8814B BIT(8) +#define BIT_CLR_HI1Q_HOST_IDX_8814B BIT(7) +#define BIT_CLR_HI0Q_HOST_IDX_8814B BIT(6) +#define BIT_CLR_BKQ_HOST_IDX_8814B BIT(5) +#define BIT_CLR_BEQ_HOST_IDX_8814B BIT(4) +#define BIT_CLR_VIQ_HOST_IDX_8814B BIT(3) +#define BIT_CLR_VOQ_HOST_IDX_8814B BIT(2) +#define BIT_CLR_MGQ_HOST_IDX_8814B BIT(1) +#define BIT_CLR_RXQ_HOST_IDX_8814B BIT(0) + +/* 2 REG_VOQ_TXBD_IDX_8814B */ + +#define BIT_SHIFT_VOQ_HW_IDX_8814B 16 +#define BIT_MASK_VOQ_HW_IDX_8814B 0xfff +#define BIT_VOQ_HW_IDX_8814B(x) (((x) & BIT_MASK_VOQ_HW_IDX_8814B) << BIT_SHIFT_VOQ_HW_IDX_8814B) +#define BIT_GET_VOQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8814B) & BIT_MASK_VOQ_HW_IDX_8814B) + + + +#define BIT_SHIFT_VOQ_HOST_IDX_8814B 0 +#define BIT_MASK_VOQ_HOST_IDX_8814B 0xfff +#define BIT_VOQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8814B) << BIT_SHIFT_VOQ_HOST_IDX_8814B) +#define BIT_GET_VOQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8814B) & BIT_MASK_VOQ_HOST_IDX_8814B) + + + +/* 2 REG_VIQ_TXBD_IDX_8814B */ + +#define BIT_SHIFT_VIQ_HW_IDX_8814B 16 +#define BIT_MASK_VIQ_HW_IDX_8814B 0xfff +#define BIT_VIQ_HW_IDX_8814B(x) (((x) & BIT_MASK_VIQ_HW_IDX_8814B) << BIT_SHIFT_VIQ_HW_IDX_8814B) +#define BIT_GET_VIQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8814B) & BIT_MASK_VIQ_HW_IDX_8814B) + + + +#define BIT_SHIFT_VIQ_HOST_IDX_8814B 0 +#define BIT_MASK_VIQ_HOST_IDX_8814B 0xfff +#define BIT_VIQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8814B) << BIT_SHIFT_VIQ_HOST_IDX_8814B) +#define BIT_GET_VIQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8814B) & BIT_MASK_VIQ_HOST_IDX_8814B) + + + +/* 2 REG_BEQ_TXBD_IDX_8814B */ + +#define BIT_SHIFT_BEQ_HW_IDX_8814B 16 +#define BIT_MASK_BEQ_HW_IDX_8814B 0xfff +#define BIT_BEQ_HW_IDX_8814B(x) (((x) & BIT_MASK_BEQ_HW_IDX_8814B) << BIT_SHIFT_BEQ_HW_IDX_8814B) +#define BIT_GET_BEQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8814B) & BIT_MASK_BEQ_HW_IDX_8814B) + + + +#define BIT_SHIFT_BEQ_HOST_IDX_8814B 0 +#define BIT_MASK_BEQ_HOST_IDX_8814B 0xfff +#define BIT_BEQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8814B) << BIT_SHIFT_BEQ_HOST_IDX_8814B) +#define BIT_GET_BEQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8814B) & BIT_MASK_BEQ_HOST_IDX_8814B) + + + +/* 2 REG_BKQ_TXBD_IDX_8814B */ + +#define BIT_SHIFT_BKQ_HW_IDX_8814B 16 +#define BIT_MASK_BKQ_HW_IDX_8814B 0xfff +#define BIT_BKQ_HW_IDX_8814B(x) (((x) & BIT_MASK_BKQ_HW_IDX_8814B) << BIT_SHIFT_BKQ_HW_IDX_8814B) +#define BIT_GET_BKQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8814B) & BIT_MASK_BKQ_HW_IDX_8814B) + + + +#define BIT_SHIFT_BKQ_HOST_IDX_8814B 0 +#define BIT_MASK_BKQ_HOST_IDX_8814B 0xfff +#define BIT_BKQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8814B) << BIT_SHIFT_BKQ_HOST_IDX_8814B) +#define BIT_GET_BKQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8814B) & BIT_MASK_BKQ_HOST_IDX_8814B) + + + +/* 2 REG_MGQ_TXBD_IDX_8814B */ + +#define BIT_SHIFT_MGQ_HW_IDX_8814B 16 +#define BIT_MASK_MGQ_HW_IDX_8814B 0xfff +#define BIT_MGQ_HW_IDX_8814B(x) (((x) & BIT_MASK_MGQ_HW_IDX_8814B) << BIT_SHIFT_MGQ_HW_IDX_8814B) +#define BIT_GET_MGQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8814B) & BIT_MASK_MGQ_HW_IDX_8814B) + + + +#define BIT_SHIFT_MGQ_HOST_IDX_8814B 0 +#define BIT_MASK_MGQ_HOST_IDX_8814B 0xfff +#define BIT_MGQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8814B) << BIT_SHIFT_MGQ_HOST_IDX_8814B) +#define BIT_GET_MGQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8814B) & BIT_MASK_MGQ_HOST_IDX_8814B) + + + +/* 2 REG_RXQ_RXBD_IDX_8814B */ + +#define BIT_SHIFT_RXQ_HW_IDX_8814B 16 +#define BIT_MASK_RXQ_HW_IDX_8814B 0xfff +#define BIT_RXQ_HW_IDX_8814B(x) (((x) & BIT_MASK_RXQ_HW_IDX_8814B) << BIT_SHIFT_RXQ_HW_IDX_8814B) +#define BIT_GET_RXQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8814B) & BIT_MASK_RXQ_HW_IDX_8814B) + + + +#define BIT_SHIFT_RXQ_HOST_IDX_8814B 0 +#define BIT_MASK_RXQ_HOST_IDX_8814B 0xfff +#define BIT_RXQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8814B) << BIT_SHIFT_RXQ_HOST_IDX_8814B) +#define BIT_GET_RXQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8814B) & BIT_MASK_RXQ_HOST_IDX_8814B) + + + +/* 2 REG_HI0Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_HI0Q_HW_IDX_8814B 16 +#define BIT_MASK_HI0Q_HW_IDX_8814B 0xfff +#define BIT_HI0Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8814B) << BIT_SHIFT_HI0Q_HW_IDX_8814B) +#define BIT_GET_HI0Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8814B) & BIT_MASK_HI0Q_HW_IDX_8814B) + + + +#define BIT_SHIFT_HI0Q_HOST_IDX_8814B 0 +#define BIT_MASK_HI0Q_HOST_IDX_8814B 0xfff +#define BIT_HI0Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8814B) << BIT_SHIFT_HI0Q_HOST_IDX_8814B) +#define BIT_GET_HI0Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8814B) & BIT_MASK_HI0Q_HOST_IDX_8814B) + + + +/* 2 REG_HI1Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_HI1Q_HW_IDX_8814B 16 +#define BIT_MASK_HI1Q_HW_IDX_8814B 0xfff +#define BIT_HI1Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8814B) << BIT_SHIFT_HI1Q_HW_IDX_8814B) +#define BIT_GET_HI1Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8814B) & BIT_MASK_HI1Q_HW_IDX_8814B) + + + +#define BIT_SHIFT_HI1Q_HOST_IDX_8814B 0 +#define BIT_MASK_HI1Q_HOST_IDX_8814B 0xfff +#define BIT_HI1Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8814B) << BIT_SHIFT_HI1Q_HOST_IDX_8814B) +#define BIT_GET_HI1Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8814B) & BIT_MASK_HI1Q_HOST_IDX_8814B) + + + +/* 2 REG_HI2Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_HI2Q_HW_IDX_8814B 16 +#define BIT_MASK_HI2Q_HW_IDX_8814B 0xfff +#define BIT_HI2Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8814B) << BIT_SHIFT_HI2Q_HW_IDX_8814B) +#define BIT_GET_HI2Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8814B) & BIT_MASK_HI2Q_HW_IDX_8814B) + + + +#define BIT_SHIFT_HI2Q_HOST_IDX_8814B 0 +#define BIT_MASK_HI2Q_HOST_IDX_8814B 0xfff +#define BIT_HI2Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8814B) << BIT_SHIFT_HI2Q_HOST_IDX_8814B) +#define BIT_GET_HI2Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8814B) & BIT_MASK_HI2Q_HOST_IDX_8814B) + + + +/* 2 REG_HI3Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_HI3Q_HW_IDX_8814B 16 +#define BIT_MASK_HI3Q_HW_IDX_8814B 0xfff +#define BIT_HI3Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8814B) << BIT_SHIFT_HI3Q_HW_IDX_8814B) +#define BIT_GET_HI3Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8814B) & BIT_MASK_HI3Q_HW_IDX_8814B) + + + +#define BIT_SHIFT_HI3Q_HOST_IDX_8814B 0 +#define BIT_MASK_HI3Q_HOST_IDX_8814B 0xfff +#define BIT_HI3Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8814B) << BIT_SHIFT_HI3Q_HOST_IDX_8814B) +#define BIT_GET_HI3Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8814B) & BIT_MASK_HI3Q_HOST_IDX_8814B) + + + +/* 2 REG_HI4Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_HI4Q_HW_IDX_8814B 16 +#define BIT_MASK_HI4Q_HW_IDX_8814B 0xfff +#define BIT_HI4Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8814B) << BIT_SHIFT_HI4Q_HW_IDX_8814B) +#define BIT_GET_HI4Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8814B) & BIT_MASK_HI4Q_HW_IDX_8814B) + + + +#define BIT_SHIFT_HI4Q_HOST_IDX_8814B 0 +#define BIT_MASK_HI4Q_HOST_IDX_8814B 0xfff +#define BIT_HI4Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8814B) << BIT_SHIFT_HI4Q_HOST_IDX_8814B) +#define BIT_GET_HI4Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8814B) & BIT_MASK_HI4Q_HOST_IDX_8814B) + + + +/* 2 REG_HI5Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_HI5Q_HW_IDX_8814B 16 +#define BIT_MASK_HI5Q_HW_IDX_8814B 0xfff +#define BIT_HI5Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8814B) << BIT_SHIFT_HI5Q_HW_IDX_8814B) +#define BIT_GET_HI5Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8814B) & BIT_MASK_HI5Q_HW_IDX_8814B) + + + +#define BIT_SHIFT_HI5Q_HOST_IDX_8814B 0 +#define BIT_MASK_HI5Q_HOST_IDX_8814B 0xfff +#define BIT_HI5Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8814B) << BIT_SHIFT_HI5Q_HOST_IDX_8814B) +#define BIT_GET_HI5Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8814B) & BIT_MASK_HI5Q_HOST_IDX_8814B) + + + +/* 2 REG_HI6Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_HI6Q_HW_IDX_8814B 16 +#define BIT_MASK_HI6Q_HW_IDX_8814B 0xfff +#define BIT_HI6Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8814B) << BIT_SHIFT_HI6Q_HW_IDX_8814B) +#define BIT_GET_HI6Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8814B) & BIT_MASK_HI6Q_HW_IDX_8814B) + + + +#define BIT_SHIFT_HI6Q_HOST_IDX_8814B 0 +#define BIT_MASK_HI6Q_HOST_IDX_8814B 0xfff +#define BIT_HI6Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8814B) << BIT_SHIFT_HI6Q_HOST_IDX_8814B) +#define BIT_GET_HI6Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8814B) & BIT_MASK_HI6Q_HOST_IDX_8814B) + + + +/* 2 REG_HI7Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_HI7Q_HW_IDX_8814B 16 +#define BIT_MASK_HI7Q_HW_IDX_8814B 0xfff +#define BIT_HI7Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8814B) << BIT_SHIFT_HI7Q_HW_IDX_8814B) +#define BIT_GET_HI7Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8814B) & BIT_MASK_HI7Q_HW_IDX_8814B) + + + +#define BIT_SHIFT_HI7Q_HOST_IDX_8814B 0 +#define BIT_MASK_HI7Q_HOST_IDX_8814B 0xfff +#define BIT_HI7Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8814B) << BIT_SHIFT_HI7Q_HOST_IDX_8814B) +#define BIT_GET_HI7Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8814B) & BIT_MASK_HI7Q_HOST_IDX_8814B) + + + +/* 2 REG_DBG_SEL_V1_8814B */ + +#define BIT_SHIFT_DBG_SEL_8814B 0 +#define BIT_MASK_DBG_SEL_8814B 0xff +#define BIT_DBG_SEL_8814B(x) (((x) & BIT_MASK_DBG_SEL_8814B) << BIT_SHIFT_DBG_SEL_8814B) +#define BIT_GET_DBG_SEL_8814B(x) (((x) >> BIT_SHIFT_DBG_SEL_8814B) & BIT_MASK_DBG_SEL_8814B) + + + +/* 2 REG_PCIE_HRPWM1_V1_8814B */ + +#define BIT_SHIFT_PCIE_HRPWM_8814B 0 +#define BIT_MASK_PCIE_HRPWM_8814B 0xff +#define BIT_PCIE_HRPWM_8814B(x) (((x) & BIT_MASK_PCIE_HRPWM_8814B) << BIT_SHIFT_PCIE_HRPWM_8814B) +#define BIT_GET_PCIE_HRPWM_8814B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM_8814B) & BIT_MASK_PCIE_HRPWM_8814B) + + + +/* 2 REG_PCIE_HCPWM1_V1_8814B */ + +#define BIT_SHIFT_PCIE_HCPWM_8814B 0 +#define BIT_MASK_PCIE_HCPWM_8814B 0xff +#define BIT_PCIE_HCPWM_8814B(x) (((x) & BIT_MASK_PCIE_HCPWM_8814B) << BIT_SHIFT_PCIE_HCPWM_8814B) +#define BIT_GET_PCIE_HCPWM_8814B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM_8814B) & BIT_MASK_PCIE_HCPWM_8814B) + + + +/* 2 REG_PCIE_CTRL2_8814B */ +#define BIT_DIS_TXDMA_PRE_8814B BIT(7) +#define BIT_DIS_RXDMA_PRE_8814B BIT(6) + +#define BIT_SHIFT_HPS_CLKR_PCIE_8814B 4 +#define BIT_MASK_HPS_CLKR_PCIE_8814B 0x3 +#define BIT_HPS_CLKR_PCIE_8814B(x) (((x) & BIT_MASK_HPS_CLKR_PCIE_8814B) << BIT_SHIFT_HPS_CLKR_PCIE_8814B) +#define BIT_GET_HPS_CLKR_PCIE_8814B(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8814B) & BIT_MASK_HPS_CLKR_PCIE_8814B) + + +#define BIT_PCIE_INT_8814B BIT(3) +#define BIT_TXFLAG_EXIT_L1_EN_8814B BIT(2) +#define BIT_EN_RXDMA_ALIGN_8814B BIT(1) +#define BIT_EN_TXDMA_ALIGN_8814B BIT(0) + +/* 2 REG_PCIE_HRPWM2_V1_8814B */ + +#define BIT_SHIFT_PCIE_HRPWM2_8814B 0 +#define BIT_MASK_PCIE_HRPWM2_8814B 0xffff +#define BIT_PCIE_HRPWM2_8814B(x) (((x) & BIT_MASK_PCIE_HRPWM2_8814B) << BIT_SHIFT_PCIE_HRPWM2_8814B) +#define BIT_GET_PCIE_HRPWM2_8814B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2_8814B) & BIT_MASK_PCIE_HRPWM2_8814B) + + + +/* 2 REG_PCIE_HCPWM2_V1_8814B */ + +#define BIT_SHIFT_PCIE_HCPWM2_8814B 0 +#define BIT_MASK_PCIE_HCPWM2_8814B 0xffff +#define BIT_PCIE_HCPWM2_8814B(x) (((x) & BIT_MASK_PCIE_HCPWM2_8814B) << BIT_SHIFT_PCIE_HCPWM2_8814B) +#define BIT_GET_PCIE_HCPWM2_8814B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2_8814B) & BIT_MASK_PCIE_HCPWM2_8814B) + + + +/* 2 REG_PCIE_H2C_MSG_V1_8814B */ + +#define BIT_SHIFT_DRV2FW_INFO_8814B 0 +#define BIT_MASK_DRV2FW_INFO_8814B 0xffffffffL +#define BIT_DRV2FW_INFO_8814B(x) (((x) & BIT_MASK_DRV2FW_INFO_8814B) << BIT_SHIFT_DRV2FW_INFO_8814B) +#define BIT_GET_DRV2FW_INFO_8814B(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8814B) & BIT_MASK_DRV2FW_INFO_8814B) + + + +/* 2 REG_PCIE_C2H_MSG_V1_8814B */ + +#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B 0 +#define BIT_MASK_HCI_PCIE_C2H_MSG_8814B 0xffffffffL +#define BIT_HCI_PCIE_C2H_MSG_8814B(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8814B) << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) +#define BIT_GET_HCI_PCIE_C2H_MSG_8814B(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) & BIT_MASK_HCI_PCIE_C2H_MSG_8814B) + + + +/* 2 REG_DBI_WDATA_V1_8814B */ + +#define BIT_SHIFT_DBI_WDATA_8814B 0 +#define BIT_MASK_DBI_WDATA_8814B 0xffffffffL +#define BIT_DBI_WDATA_8814B(x) (((x) & BIT_MASK_DBI_WDATA_8814B) << BIT_SHIFT_DBI_WDATA_8814B) +#define BIT_GET_DBI_WDATA_8814B(x) (((x) >> BIT_SHIFT_DBI_WDATA_8814B) & BIT_MASK_DBI_WDATA_8814B) + + + +/* 2 REG_DBI_RDATA_V1_8814B */ + +#define BIT_SHIFT_DBI_RDATA_8814B 0 +#define BIT_MASK_DBI_RDATA_8814B 0xffffffffL +#define BIT_DBI_RDATA_8814B(x) (((x) & BIT_MASK_DBI_RDATA_8814B) << BIT_SHIFT_DBI_RDATA_8814B) +#define BIT_GET_DBI_RDATA_8814B(x) (((x) >> BIT_SHIFT_DBI_RDATA_8814B) & BIT_MASK_DBI_RDATA_8814B) + + + +/* 2 REG_DBI_FLAG_V1_8814B */ +#define BIT_EN_STUCK_DBG_8814B BIT(26) +#define BIT_RX_STUCK_8814B BIT(25) +#define BIT_TX_STUCK_8814B BIT(24) +#define BIT_DBI_RFLAG_8814B BIT(17) +#define BIT_DBI_WFLAG_8814B BIT(16) + +#define BIT_SHIFT_DBI_WREN_8814B 12 +#define BIT_MASK_DBI_WREN_8814B 0xf +#define BIT_DBI_WREN_8814B(x) (((x) & BIT_MASK_DBI_WREN_8814B) << BIT_SHIFT_DBI_WREN_8814B) +#define BIT_GET_DBI_WREN_8814B(x) (((x) >> BIT_SHIFT_DBI_WREN_8814B) & BIT_MASK_DBI_WREN_8814B) + + + +#define BIT_SHIFT_DBI_ADDR_8814B 0 +#define BIT_MASK_DBI_ADDR_8814B 0xfff +#define BIT_DBI_ADDR_8814B(x) (((x) & BIT_MASK_DBI_ADDR_8814B) << BIT_SHIFT_DBI_ADDR_8814B) +#define BIT_GET_DBI_ADDR_8814B(x) (((x) >> BIT_SHIFT_DBI_ADDR_8814B) & BIT_MASK_DBI_ADDR_8814B) + + + +/* 2 REG_MDIO_V1_8814B */ + +#define BIT_SHIFT_MDIO_RDATA_8814B 16 +#define BIT_MASK_MDIO_RDATA_8814B 0xffff +#define BIT_MDIO_RDATA_8814B(x) (((x) & BIT_MASK_MDIO_RDATA_8814B) << BIT_SHIFT_MDIO_RDATA_8814B) +#define BIT_GET_MDIO_RDATA_8814B(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8814B) & BIT_MASK_MDIO_RDATA_8814B) + + + +#define BIT_SHIFT_MDIO_WDATA_8814B 0 +#define BIT_MASK_MDIO_WDATA_8814B 0xffff +#define BIT_MDIO_WDATA_8814B(x) (((x) & BIT_MASK_MDIO_WDATA_8814B) << BIT_SHIFT_MDIO_WDATA_8814B) +#define BIT_GET_MDIO_WDATA_8814B(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8814B) & BIT_MASK_MDIO_WDATA_8814B) + + + +/* 2 REG_PCIE_MIX_CFG_8814B */ + +#define BIT_SHIFT_MDIO_PHY_ADDR_8814B 24 +#define BIT_MASK_MDIO_PHY_ADDR_8814B 0x1f +#define BIT_MDIO_PHY_ADDR_8814B(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8814B) << BIT_SHIFT_MDIO_PHY_ADDR_8814B) +#define BIT_GET_MDIO_PHY_ADDR_8814B(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8814B) & BIT_MASK_MDIO_PHY_ADDR_8814B) + + + +#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B 10 +#define BIT_MASK_WATCH_DOG_RECORD_V1_8814B 0x3fff +#define BIT_WATCH_DOG_RECORD_V1_8814B(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8814B) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) +#define BIT_GET_WATCH_DOG_RECORD_V1_8814B(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) & BIT_MASK_WATCH_DOG_RECORD_V1_8814B) + + +#define BIT_R_IO_TIMEOUT_FLAG_V1_8814B BIT(9) +#define BIT_EN_WATCH_DOG_8814B BIT(8) +#define BIT_ECRC_EN_V1_8814B BIT(7) +#define BIT_MDIO_RFLAG_V1_8814B BIT(6) +#define BIT_MDIO_WFLAG_V1_8814B BIT(5) + +#define BIT_SHIFT_MDIO_REG_ADDR_V1_8814B 0 +#define BIT_MASK_MDIO_REG_ADDR_V1_8814B 0x1f +#define BIT_MDIO_REG_ADDR_V1_8814B(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8814B) << BIT_SHIFT_MDIO_REG_ADDR_V1_8814B) +#define BIT_GET_MDIO_REG_ADDR_V1_8814B(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8814B) & BIT_MASK_MDIO_REG_ADDR_V1_8814B) + + + +/* 2 REG_HCI_MIX_CFG_8814B */ +#define BIT_HOST_GEN2_SUPPORT_8814B BIT(20) + +#define BIT_SHIFT_TXDMA_ERR_FLAG_8814B 16 +#define BIT_MASK_TXDMA_ERR_FLAG_8814B 0xf +#define BIT_TXDMA_ERR_FLAG_8814B(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8814B) << BIT_SHIFT_TXDMA_ERR_FLAG_8814B) +#define BIT_GET_TXDMA_ERR_FLAG_8814B(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8814B) & BIT_MASK_TXDMA_ERR_FLAG_8814B) + + + +#define BIT_SHIFT_EARLY_MODE_SEL_8814B 12 +#define BIT_MASK_EARLY_MODE_SEL_8814B 0xf +#define BIT_EARLY_MODE_SEL_8814B(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8814B) << BIT_SHIFT_EARLY_MODE_SEL_8814B) +#define BIT_GET_EARLY_MODE_SEL_8814B(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8814B) & BIT_MASK_EARLY_MODE_SEL_8814B) + + +#define BIT_EPHY_RX50_EN_8814B BIT(11) + +#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B 8 +#define BIT_MASK_MSI_TIMEOUT_ID_V1_8814B 0x7 +#define BIT_MSI_TIMEOUT_ID_V1_8814B(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8814B) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8814B(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) & BIT_MASK_MSI_TIMEOUT_ID_V1_8814B) + + +#define BIT_RADDR_RD_8814B BIT(7) +#define BIT_EN_MUL_TAG_8814B BIT(6) +#define BIT_EN_EARLY_MODE_8814B BIT(5) +#define BIT_L0S_LINK_OFF_8814B BIT(4) +#define BIT_ACT_LINK_OFF_8814B BIT(3) +#define BIT_EN_SLOW_MAC_TX_8814B BIT(2) +#define BIT_EN_SLOW_MAC_RX_8814B BIT(1) + +/* 2 REG_STC_INT_CS_8814B(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */ +#define BIT_STC_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_STC_INT_FLAG_8814B 16 +#define BIT_MASK_STC_INT_FLAG_8814B 0xff +#define BIT_STC_INT_FLAG_8814B(x) (((x) & BIT_MASK_STC_INT_FLAG_8814B) << BIT_SHIFT_STC_INT_FLAG_8814B) +#define BIT_GET_STC_INT_FLAG_8814B(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8814B) & BIT_MASK_STC_INT_FLAG_8814B) + + + +#define BIT_SHIFT_STC_INT_IDX_8814B 8 +#define BIT_MASK_STC_INT_IDX_8814B 0x7 +#define BIT_STC_INT_IDX_8814B(x) (((x) & BIT_MASK_STC_INT_IDX_8814B) << BIT_SHIFT_STC_INT_IDX_8814B) +#define BIT_GET_STC_INT_IDX_8814B(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8814B) & BIT_MASK_STC_INT_IDX_8814B) + + + +#define BIT_SHIFT_STC_INT_REALTIME_CS_8814B 0 +#define BIT_MASK_STC_INT_REALTIME_CS_8814B 0x3f +#define BIT_STC_INT_REALTIME_CS_8814B(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8814B) << BIT_SHIFT_STC_INT_REALTIME_CS_8814B) +#define BIT_GET_STC_INT_REALTIME_CS_8814B(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8814B) & BIT_MASK_STC_INT_REALTIME_CS_8814B) + + + +/* 2 REG_ST_INT_CFG_8814B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */ +#define BIT_STC_INT_GRP_EN_8814B BIT(31) + +#define BIT_SHIFT_STC_INT_EXPECT_LS_8814B 8 +#define BIT_MASK_STC_INT_EXPECT_LS_8814B 0x3f +#define BIT_STC_INT_EXPECT_LS_8814B(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8814B) << BIT_SHIFT_STC_INT_EXPECT_LS_8814B) +#define BIT_GET_STC_INT_EXPECT_LS_8814B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8814B) & BIT_MASK_STC_INT_EXPECT_LS_8814B) + + + +#define BIT_SHIFT_STC_INT_EXPECT_CS_8814B 0 +#define BIT_MASK_STC_INT_EXPECT_CS_8814B 0x3f +#define BIT_STC_INT_EXPECT_CS_8814B(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8814B) << BIT_SHIFT_STC_INT_EXPECT_CS_8814B) +#define BIT_GET_STC_INT_EXPECT_CS_8814B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8814B) & BIT_MASK_STC_INT_EXPECT_CS_8814B) + + + +/* 2 REG_CMU_DLY_CTRL_8814B(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */ +#define BIT_CMU_DLY_EN_8814B BIT(31) +#define BIT_CMU_DLY_MODE_8814B BIT(30) + +#define BIT_SHIFT_CMU_DLY_PRE_DIV_8814B 0 +#define BIT_MASK_CMU_DLY_PRE_DIV_8814B 0xff +#define BIT_CMU_DLY_PRE_DIV_8814B(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8814B) << BIT_SHIFT_CMU_DLY_PRE_DIV_8814B) +#define BIT_GET_CMU_DLY_PRE_DIV_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8814B) & BIT_MASK_CMU_DLY_PRE_DIV_8814B) + + + +/* 2 REG_CMU_DLY_CFG_8814B(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ + +#define BIT_SHIFT_CMU_DLY_LTR_A2I_8814B 24 +#define BIT_MASK_CMU_DLY_LTR_A2I_8814B 0xff +#define BIT_CMU_DLY_LTR_A2I_8814B(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8814B) << BIT_SHIFT_CMU_DLY_LTR_A2I_8814B) +#define BIT_GET_CMU_DLY_LTR_A2I_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8814B) & BIT_MASK_CMU_DLY_LTR_A2I_8814B) + + + +#define BIT_SHIFT_CMU_DLY_LTR_I2A_8814B 16 +#define BIT_MASK_CMU_DLY_LTR_I2A_8814B 0xff +#define BIT_CMU_DLY_LTR_I2A_8814B(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8814B) << BIT_SHIFT_CMU_DLY_LTR_I2A_8814B) +#define BIT_GET_CMU_DLY_LTR_I2A_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8814B) & BIT_MASK_CMU_DLY_LTR_I2A_8814B) + + + +#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8814B 8 +#define BIT_MASK_CMU_DLY_LTR_IDLE_8814B 0xff +#define BIT_CMU_DLY_LTR_IDLE_8814B(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8814B) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8814B) +#define BIT_GET_CMU_DLY_LTR_IDLE_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8814B) & BIT_MASK_CMU_DLY_LTR_IDLE_8814B) + + + +#define BIT_SHIFT_CMU_DLY_LTR_ACT_8814B 0 +#define BIT_MASK_CMU_DLY_LTR_ACT_8814B 0xff +#define BIT_CMU_DLY_LTR_ACT_8814B(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8814B) << BIT_SHIFT_CMU_DLY_LTR_ACT_8814B) +#define BIT_GET_CMU_DLY_LTR_ACT_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8814B) & BIT_MASK_CMU_DLY_LTR_ACT_8814B) + + + +/* 2 REG_H2CQ_TXBD_DESA_8814B */ + +#define BIT_SHIFT_H2CQ_TXBD_DESA_8814B 0 +#define BIT_MASK_H2CQ_TXBD_DESA_8814B 0xffffffffffffffffL +#define BIT_H2CQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8814B) << BIT_SHIFT_H2CQ_TXBD_DESA_8814B) +#define BIT_GET_H2CQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8814B) & BIT_MASK_H2CQ_TXBD_DESA_8814B) + + + +/* 2 REG_H2CQ_TXBD_NUM_8814B */ +#define BIT_PCIE_H2CQ_FLAG_8814B BIT(14) + +#define BIT_SHIFT_H2CQ_DESC_MODE_8814B 12 +#define BIT_MASK_H2CQ_DESC_MODE_8814B 0x3 +#define BIT_H2CQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8814B) << BIT_SHIFT_H2CQ_DESC_MODE_8814B) +#define BIT_GET_H2CQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8814B) & BIT_MASK_H2CQ_DESC_MODE_8814B) + + + +#define BIT_SHIFT_H2CQ_DESC_NUM_8814B 0 +#define BIT_MASK_H2CQ_DESC_NUM_8814B 0xfff +#define BIT_H2CQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8814B) << BIT_SHIFT_H2CQ_DESC_NUM_8814B) +#define BIT_GET_H2CQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8814B) & BIT_MASK_H2CQ_DESC_NUM_8814B) + + + +/* 2 REG_H2CQ_TXBD_IDX_8814B */ + +#define BIT_SHIFT_H2CQ_HW_IDX_8814B 16 +#define BIT_MASK_H2CQ_HW_IDX_8814B 0xfff +#define BIT_H2CQ_HW_IDX_8814B(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8814B) << BIT_SHIFT_H2CQ_HW_IDX_8814B) +#define BIT_GET_H2CQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8814B) & BIT_MASK_H2CQ_HW_IDX_8814B) + + + +#define BIT_SHIFT_H2CQ_HOST_IDX_8814B 0 +#define BIT_MASK_H2CQ_HOST_IDX_8814B 0xfff +#define BIT_H2CQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8814B) << BIT_SHIFT_H2CQ_HOST_IDX_8814B) +#define BIT_GET_H2CQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8814B) & BIT_MASK_H2CQ_HOST_IDX_8814B) + + + +/* 2 REG_H2CQ_CSR_8814B[31:0] (H2CQ CONTROL AND STATUS) */ +#define BIT_H2CQ_FULL_8814B BIT(31) +#define BIT_CLR_H2CQ_HOST_IDX_8814B BIT(16) +#define BIT_CLR_H2CQ_HW_IDX_8814B BIT(8) + +/* 2 REG_Q0_INFO_8814B */ + +#define BIT_SHIFT_QUEUEMACID_Q0_V1_8814B 25 +#define BIT_MASK_QUEUEMACID_Q0_V1_8814B 0x7f +#define BIT_QUEUEMACID_Q0_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q0_V1_8814B) +#define BIT_GET_QUEUEMACID_Q0_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8814B) & BIT_MASK_QUEUEMACID_Q0_V1_8814B) + + + +#define BIT_SHIFT_QUEUEAC_Q0_V1_8814B 23 +#define BIT_MASK_QUEUEAC_Q0_V1_8814B 0x3 +#define BIT_QUEUEAC_Q0_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8814B) << BIT_SHIFT_QUEUEAC_Q0_V1_8814B) +#define BIT_GET_QUEUEAC_Q0_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8814B) & BIT_MASK_QUEUEAC_Q0_V1_8814B) + + +#define BIT_TIDEMPTY_Q0_V1_8814B BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q0_V2_8814B 11 +#define BIT_MASK_TAIL_PKT_Q0_V2_8814B 0x7ff +#define BIT_TAIL_PKT_Q0_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q0_V2_8814B) +#define BIT_GET_TAIL_PKT_Q0_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8814B) & BIT_MASK_TAIL_PKT_Q0_V2_8814B) + + + +#define BIT_SHIFT_HEAD_PKT_Q0_V1_8814B 0 +#define BIT_MASK_HEAD_PKT_Q0_V1_8814B 0x7ff +#define BIT_HEAD_PKT_Q0_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q0_V1_8814B) +#define BIT_GET_HEAD_PKT_Q0_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8814B) & BIT_MASK_HEAD_PKT_Q0_V1_8814B) + + + +/* 2 REG_Q1_INFO_8814B */ + +#define BIT_SHIFT_QUEUEMACID_Q1_V1_8814B 25 +#define BIT_MASK_QUEUEMACID_Q1_V1_8814B 0x7f +#define BIT_QUEUEMACID_Q1_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q1_V1_8814B) +#define BIT_GET_QUEUEMACID_Q1_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8814B) & BIT_MASK_QUEUEMACID_Q1_V1_8814B) + + + +#define BIT_SHIFT_QUEUEAC_Q1_V1_8814B 23 +#define BIT_MASK_QUEUEAC_Q1_V1_8814B 0x3 +#define BIT_QUEUEAC_Q1_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8814B) << BIT_SHIFT_QUEUEAC_Q1_V1_8814B) +#define BIT_GET_QUEUEAC_Q1_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8814B) & BIT_MASK_QUEUEAC_Q1_V1_8814B) + + +#define BIT_TIDEMPTY_Q1_V1_8814B BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q1_V2_8814B 11 +#define BIT_MASK_TAIL_PKT_Q1_V2_8814B 0x7ff +#define BIT_TAIL_PKT_Q1_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q1_V2_8814B) +#define BIT_GET_TAIL_PKT_Q1_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8814B) & BIT_MASK_TAIL_PKT_Q1_V2_8814B) + + + +#define BIT_SHIFT_HEAD_PKT_Q1_V1_8814B 0 +#define BIT_MASK_HEAD_PKT_Q1_V1_8814B 0x7ff +#define BIT_HEAD_PKT_Q1_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q1_V1_8814B) +#define BIT_GET_HEAD_PKT_Q1_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8814B) & BIT_MASK_HEAD_PKT_Q1_V1_8814B) + + + +/* 2 REG_Q2_INFO_8814B */ + +#define BIT_SHIFT_QUEUEMACID_Q2_V1_8814B 25 +#define BIT_MASK_QUEUEMACID_Q2_V1_8814B 0x7f +#define BIT_QUEUEMACID_Q2_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q2_V1_8814B) +#define BIT_GET_QUEUEMACID_Q2_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8814B) & BIT_MASK_QUEUEMACID_Q2_V1_8814B) + + + +#define BIT_SHIFT_QUEUEAC_Q2_V1_8814B 23 +#define BIT_MASK_QUEUEAC_Q2_V1_8814B 0x3 +#define BIT_QUEUEAC_Q2_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8814B) << BIT_SHIFT_QUEUEAC_Q2_V1_8814B) +#define BIT_GET_QUEUEAC_Q2_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8814B) & BIT_MASK_QUEUEAC_Q2_V1_8814B) + + +#define BIT_TIDEMPTY_Q2_V1_8814B BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q2_V2_8814B 11 +#define BIT_MASK_TAIL_PKT_Q2_V2_8814B 0x7ff +#define BIT_TAIL_PKT_Q2_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q2_V2_8814B) +#define BIT_GET_TAIL_PKT_Q2_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8814B) & BIT_MASK_TAIL_PKT_Q2_V2_8814B) + + + +#define BIT_SHIFT_HEAD_PKT_Q2_V1_8814B 0 +#define BIT_MASK_HEAD_PKT_Q2_V1_8814B 0x7ff +#define BIT_HEAD_PKT_Q2_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q2_V1_8814B) +#define BIT_GET_HEAD_PKT_Q2_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8814B) & BIT_MASK_HEAD_PKT_Q2_V1_8814B) + + + +/* 2 REG_Q3_INFO_8814B */ + +#define BIT_SHIFT_QUEUEMACID_Q3_V1_8814B 25 +#define BIT_MASK_QUEUEMACID_Q3_V1_8814B 0x7f +#define BIT_QUEUEMACID_Q3_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q3_V1_8814B) +#define BIT_GET_QUEUEMACID_Q3_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8814B) & BIT_MASK_QUEUEMACID_Q3_V1_8814B) + + + +#define BIT_SHIFT_QUEUEAC_Q3_V1_8814B 23 +#define BIT_MASK_QUEUEAC_Q3_V1_8814B 0x3 +#define BIT_QUEUEAC_Q3_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8814B) << BIT_SHIFT_QUEUEAC_Q3_V1_8814B) +#define BIT_GET_QUEUEAC_Q3_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8814B) & BIT_MASK_QUEUEAC_Q3_V1_8814B) + + +#define BIT_TIDEMPTY_Q3_V1_8814B BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q3_V2_8814B 11 +#define BIT_MASK_TAIL_PKT_Q3_V2_8814B 0x7ff +#define BIT_TAIL_PKT_Q3_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q3_V2_8814B) +#define BIT_GET_TAIL_PKT_Q3_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8814B) & BIT_MASK_TAIL_PKT_Q3_V2_8814B) + + + +#define BIT_SHIFT_HEAD_PKT_Q3_V1_8814B 0 +#define BIT_MASK_HEAD_PKT_Q3_V1_8814B 0x7ff +#define BIT_HEAD_PKT_Q3_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q3_V1_8814B) +#define BIT_GET_HEAD_PKT_Q3_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8814B) & BIT_MASK_HEAD_PKT_Q3_V1_8814B) + + + +/* 2 REG_MGQ_INFO_8814B */ + +#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8814B 25 +#define BIT_MASK_QUEUEMACID_MGQ_V1_8814B 0x7f +#define BIT_QUEUEMACID_MGQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8814B) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8814B) +#define BIT_GET_QUEUEMACID_MGQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8814B) & BIT_MASK_QUEUEMACID_MGQ_V1_8814B) + + + +#define BIT_SHIFT_QUEUEAC_MGQ_V1_8814B 23 +#define BIT_MASK_QUEUEAC_MGQ_V1_8814B 0x3 +#define BIT_QUEUEAC_MGQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8814B) << BIT_SHIFT_QUEUEAC_MGQ_V1_8814B) +#define BIT_GET_QUEUEAC_MGQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8814B) & BIT_MASK_QUEUEAC_MGQ_V1_8814B) + + +#define BIT_TIDEMPTY_MGQ_V1_8814B BIT(22) + +#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8814B 11 +#define BIT_MASK_TAIL_PKT_MGQ_V2_8814B 0x7ff +#define BIT_TAIL_PKT_MGQ_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8814B) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8814B) +#define BIT_GET_TAIL_PKT_MGQ_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8814B) & BIT_MASK_TAIL_PKT_MGQ_V2_8814B) + + + +#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8814B 0 +#define BIT_MASK_HEAD_PKT_MGQ_V1_8814B 0x7ff +#define BIT_HEAD_PKT_MGQ_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8814B) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8814B) +#define BIT_GET_HEAD_PKT_MGQ_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8814B) & BIT_MASK_HEAD_PKT_MGQ_V1_8814B) + + + +/* 2 REG_HIQ_INFO_8814B */ + +#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8814B 25 +#define BIT_MASK_QUEUEMACID_HIQ_V1_8814B 0x7f +#define BIT_QUEUEMACID_HIQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8814B) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8814B) +#define BIT_GET_QUEUEMACID_HIQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8814B) & BIT_MASK_QUEUEMACID_HIQ_V1_8814B) + + + +#define BIT_SHIFT_QUEUEAC_HIQ_V1_8814B 23 +#define BIT_MASK_QUEUEAC_HIQ_V1_8814B 0x3 +#define BIT_QUEUEAC_HIQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8814B) << BIT_SHIFT_QUEUEAC_HIQ_V1_8814B) +#define BIT_GET_QUEUEAC_HIQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8814B) & BIT_MASK_QUEUEAC_HIQ_V1_8814B) + + +#define BIT_TIDEMPTY_HIQ_V1_8814B BIT(22) + +#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8814B 11 +#define BIT_MASK_TAIL_PKT_HIQ_V2_8814B 0x7ff +#define BIT_TAIL_PKT_HIQ_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8814B) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8814B) +#define BIT_GET_TAIL_PKT_HIQ_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8814B) & BIT_MASK_TAIL_PKT_HIQ_V2_8814B) + + + +#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8814B 0 +#define BIT_MASK_HEAD_PKT_HIQ_V1_8814B 0x7ff +#define BIT_HEAD_PKT_HIQ_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8814B) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8814B) +#define BIT_GET_HEAD_PKT_HIQ_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8814B) & BIT_MASK_HEAD_PKT_HIQ_V1_8814B) + + + +/* 2 REG_BCNQ_INFO_8814B */ + +#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8814B 0 +#define BIT_MASK_BCNQ_HEAD_PG_V1_8814B 0xfff +#define BIT_BCNQ_HEAD_PG_V1_8814B(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8814B) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8814B) +#define BIT_GET_BCNQ_HEAD_PG_V1_8814B(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8814B) & BIT_MASK_BCNQ_HEAD_PG_V1_8814B) + + + +/* 2 REG_TXPKT_EMPTY_8814B */ +#define BIT_BCNQ_EMPTY_8814B BIT(11) +#define BIT_HQQ_EMPTY_8814B BIT(10) +#define BIT_MQQ_EMPTY_8814B BIT(9) +#define BIT_MGQ_CPU_EMPTY_8814B BIT(8) +#define BIT_AC7Q_EMPTY_8814B BIT(7) +#define BIT_AC6Q_EMPTY_8814B BIT(6) +#define BIT_AC5Q_EMPTY_8814B BIT(5) +#define BIT_AC4Q_EMPTY_8814B BIT(4) +#define BIT_AC3Q_EMPTY_8814B BIT(3) +#define BIT_AC2Q_EMPTY_8814B BIT(2) +#define BIT_AC1Q_EMPTY_8814B BIT(1) +#define BIT_AC0Q_EMPTY_8814B BIT(0) + +/* 2 REG_CPU_MGQ_INFO_8814B */ +#define BIT_BCN1_POLL_8814B BIT(30) +#define BIT_CPUMGT_POLL_8814B BIT(29) +#define BIT_BCN_POLL_8814B BIT(28) +#define BIT_CPUMGQ_FW_NUM_V1_8814B BIT(12) + +#define BIT_SHIFT_FW_FREE_TAIL_V1_8814B 0 +#define BIT_MASK_FW_FREE_TAIL_V1_8814B 0xfff +#define BIT_FW_FREE_TAIL_V1_8814B(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8814B) << BIT_SHIFT_FW_FREE_TAIL_V1_8814B) +#define BIT_GET_FW_FREE_TAIL_V1_8814B(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8814B) & BIT_MASK_FW_FREE_TAIL_V1_8814B) + + + +/* 2 REG_FWHW_TXQ_CTRL_8814B */ +#define BIT_RTS_LIMIT_IN_OFDM_8814B BIT(23) +#define BIT_EN_BCNQ_DL_8814B BIT(22) +#define BIT_EN_RD_RESP_NAV_BK_8814B BIT(21) +#define BIT_EN_WR_FREE_TAIL_8814B BIT(20) + +#define BIT_SHIFT_EN_QUEUE_RPT_8814B 8 +#define BIT_MASK_EN_QUEUE_RPT_8814B 0xff +#define BIT_EN_QUEUE_RPT_8814B(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8814B) << BIT_SHIFT_EN_QUEUE_RPT_8814B) +#define BIT_GET_EN_QUEUE_RPT_8814B(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8814B) & BIT_MASK_EN_QUEUE_RPT_8814B) + + +#define BIT_EN_RTY_BK_8814B BIT(7) +#define BIT_EN_USE_INI_RAT_8814B BIT(6) +#define BIT_EN_RTS_NAV_BK_8814B BIT(5) +#define BIT_DIS_SSN_CHECK_8814B BIT(4) +#define BIT_MACID_MATCH_RTS_8814B BIT(3) +#define BIT_EN_BCN_TRXRPT_V1_8814B BIT(2) +#define BIT_R_EN_FTMRPT_8814B BIT(1) +#define BIT_R_BMC_NAV_PROTECT_8814B BIT(0) + +/* 2 REG_DATAFB_SEL_8814B */ +#define BIT__R_EN_RTY_BK_COD_8814B BIT(2) + +#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8814B 0 +#define BIT_MASK__R_DATA_FALLBACK_SEL_8814B 0x3 +#define BIT__R_DATA_FALLBACK_SEL_8814B(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8814B) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8814B) +#define BIT_GET__R_DATA_FALLBACK_SEL_8814B(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8814B) & BIT_MASK__R_DATA_FALLBACK_SEL_8814B) + + + +/* 2 REG_BCNQ_BDNY_V1_8814B */ + +#define BIT_SHIFT_BCNQ_PGBNDY_V1_8814B 0 +#define BIT_MASK_BCNQ_PGBNDY_V1_8814B 0xfff +#define BIT_BCNQ_PGBNDY_V1_8814B(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8814B) << BIT_SHIFT_BCNQ_PGBNDY_V1_8814B) +#define BIT_GET_BCNQ_PGBNDY_V1_8814B(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8814B) & BIT_MASK_BCNQ_PGBNDY_V1_8814B) + + + +/* 2 REG_LIFETIME_EN_8814B */ +#define BIT_BT_INT_CPU_8814B BIT(7) +#define BIT_BT_INT_PTA_8814B BIT(6) +#define BIT_EN_CTRL_RTYBIT_8814B BIT(4) +#define BIT_LIFETIME_BK_EN_8814B BIT(3) +#define BIT_LIFETIME_BE_EN_8814B BIT(2) +#define BIT_LIFETIME_VI_EN_8814B BIT(1) +#define BIT_LIFETIME_VO_EN_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_SPEC_SIFS_8814B */ + +#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B 8 +#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B 0xff +#define BIT_SPEC_SIFS_OFDM_PTCL_8814B(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8814B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B) + + + +#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B 0 +#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B 0xff +#define BIT_SPEC_SIFS_CCK_PTCL_8814B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8814B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B) + + + +/* 2 REG_RETRY_LIMIT_8814B */ + +#define BIT_SHIFT_SRL_8814B 8 +#define BIT_MASK_SRL_8814B 0x3f +#define BIT_SRL_8814B(x) (((x) & BIT_MASK_SRL_8814B) << BIT_SHIFT_SRL_8814B) +#define BIT_GET_SRL_8814B(x) (((x) >> BIT_SHIFT_SRL_8814B) & BIT_MASK_SRL_8814B) + + + +#define BIT_SHIFT_LRL_8814B 0 +#define BIT_MASK_LRL_8814B 0x3f +#define BIT_LRL_8814B(x) (((x) & BIT_MASK_LRL_8814B) << BIT_SHIFT_LRL_8814B) +#define BIT_GET_LRL_8814B(x) (((x) >> BIT_SHIFT_LRL_8814B) & BIT_MASK_LRL_8814B) + + + +/* 2 REG_TXBF_CTRL_8814B */ +#define BIT_R_ENABLE_NDPA_8814B BIT(31) +#define BIT_USE_NDPA_PARAMETER_8814B BIT(30) +#define BIT_R_PROP_TXBF_8814B BIT(29) +#define BIT_R_EN_NDPA_INT_8814B BIT(28) +#define BIT_R_TXBF1_80M_8814B BIT(27) +#define BIT_R_TXBF1_40M_8814B BIT(26) +#define BIT_R_TXBF1_20M_8814B BIT(25) + +#define BIT_SHIFT_R_TXBF1_AID_8814B 16 +#define BIT_MASK_R_TXBF1_AID_8814B 0x1ff +#define BIT_R_TXBF1_AID_8814B(x) (((x) & BIT_MASK_R_TXBF1_AID_8814B) << BIT_SHIFT_R_TXBF1_AID_8814B) +#define BIT_GET_R_TXBF1_AID_8814B(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8814B) & BIT_MASK_R_TXBF1_AID_8814B) + + +#define BIT_DIS_NDP_BFEN_8814B BIT(15) +#define BIT_R_TXBCN_NOBLOCK_NDP_8814B BIT(14) +#define BIT_R_TXBF0_80M_8814B BIT(11) +#define BIT_R_TXBF0_40M_8814B BIT(10) +#define BIT_R_TXBF0_20M_8814B BIT(9) + +#define BIT_SHIFT_R_TXBF0_AID_8814B 0 +#define BIT_MASK_R_TXBF0_AID_8814B 0x1ff +#define BIT_R_TXBF0_AID_8814B(x) (((x) & BIT_MASK_R_TXBF0_AID_8814B) << BIT_SHIFT_R_TXBF0_AID_8814B) +#define BIT_GET_R_TXBF0_AID_8814B(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8814B) & BIT_MASK_R_TXBF0_AID_8814B) + + + +/* 2 REG_DARFRC_8814B */ + +#define BIT_SHIFT_DARF_RC8_8814B (56 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC8_8814B 0x1f +#define BIT_DARF_RC8_8814B(x) (((x) & BIT_MASK_DARF_RC8_8814B) << BIT_SHIFT_DARF_RC8_8814B) +#define BIT_GET_DARF_RC8_8814B(x) (((x) >> BIT_SHIFT_DARF_RC8_8814B) & BIT_MASK_DARF_RC8_8814B) + + + +#define BIT_SHIFT_DARF_RC7_8814B (48 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC7_8814B 0x1f +#define BIT_DARF_RC7_8814B(x) (((x) & BIT_MASK_DARF_RC7_8814B) << BIT_SHIFT_DARF_RC7_8814B) +#define BIT_GET_DARF_RC7_8814B(x) (((x) >> BIT_SHIFT_DARF_RC7_8814B) & BIT_MASK_DARF_RC7_8814B) + + + +#define BIT_SHIFT_DARF_RC6_8814B (40 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC6_8814B 0x1f +#define BIT_DARF_RC6_8814B(x) (((x) & BIT_MASK_DARF_RC6_8814B) << BIT_SHIFT_DARF_RC6_8814B) +#define BIT_GET_DARF_RC6_8814B(x) (((x) >> BIT_SHIFT_DARF_RC6_8814B) & BIT_MASK_DARF_RC6_8814B) + + + +#define BIT_SHIFT_DARF_RC5_8814B (32 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC5_8814B 0x1f +#define BIT_DARF_RC5_8814B(x) (((x) & BIT_MASK_DARF_RC5_8814B) << BIT_SHIFT_DARF_RC5_8814B) +#define BIT_GET_DARF_RC5_8814B(x) (((x) >> BIT_SHIFT_DARF_RC5_8814B) & BIT_MASK_DARF_RC5_8814B) + + + +#define BIT_SHIFT_DARF_RC4_8814B 24 +#define BIT_MASK_DARF_RC4_8814B 0x1f +#define BIT_DARF_RC4_8814B(x) (((x) & BIT_MASK_DARF_RC4_8814B) << BIT_SHIFT_DARF_RC4_8814B) +#define BIT_GET_DARF_RC4_8814B(x) (((x) >> BIT_SHIFT_DARF_RC4_8814B) & BIT_MASK_DARF_RC4_8814B) + + + +#define BIT_SHIFT_DARF_RC3_8814B 16 +#define BIT_MASK_DARF_RC3_8814B 0x1f +#define BIT_DARF_RC3_8814B(x) (((x) & BIT_MASK_DARF_RC3_8814B) << BIT_SHIFT_DARF_RC3_8814B) +#define BIT_GET_DARF_RC3_8814B(x) (((x) >> BIT_SHIFT_DARF_RC3_8814B) & BIT_MASK_DARF_RC3_8814B) + + + +#define BIT_SHIFT_DARF_RC2_8814B 8 +#define BIT_MASK_DARF_RC2_8814B 0x1f +#define BIT_DARF_RC2_8814B(x) (((x) & BIT_MASK_DARF_RC2_8814B) << BIT_SHIFT_DARF_RC2_8814B) +#define BIT_GET_DARF_RC2_8814B(x) (((x) >> BIT_SHIFT_DARF_RC2_8814B) & BIT_MASK_DARF_RC2_8814B) + + + +#define BIT_SHIFT_DARF_RC1_8814B 0 +#define BIT_MASK_DARF_RC1_8814B 0x1f +#define BIT_DARF_RC1_8814B(x) (((x) & BIT_MASK_DARF_RC1_8814B) << BIT_SHIFT_DARF_RC1_8814B) +#define BIT_GET_DARF_RC1_8814B(x) (((x) >> BIT_SHIFT_DARF_RC1_8814B) & BIT_MASK_DARF_RC1_8814B) + + + +/* 2 REG_RARFRC_8814B */ + +#define BIT_SHIFT_RARF_RC8_8814B (56 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC8_8814B 0x1f +#define BIT_RARF_RC8_8814B(x) (((x) & BIT_MASK_RARF_RC8_8814B) << BIT_SHIFT_RARF_RC8_8814B) +#define BIT_GET_RARF_RC8_8814B(x) (((x) >> BIT_SHIFT_RARF_RC8_8814B) & BIT_MASK_RARF_RC8_8814B) + + + +#define BIT_SHIFT_RARF_RC7_8814B (48 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC7_8814B 0x1f +#define BIT_RARF_RC7_8814B(x) (((x) & BIT_MASK_RARF_RC7_8814B) << BIT_SHIFT_RARF_RC7_8814B) +#define BIT_GET_RARF_RC7_8814B(x) (((x) >> BIT_SHIFT_RARF_RC7_8814B) & BIT_MASK_RARF_RC7_8814B) + + + +#define BIT_SHIFT_RARF_RC6_8814B (40 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC6_8814B 0x1f +#define BIT_RARF_RC6_8814B(x) (((x) & BIT_MASK_RARF_RC6_8814B) << BIT_SHIFT_RARF_RC6_8814B) +#define BIT_GET_RARF_RC6_8814B(x) (((x) >> BIT_SHIFT_RARF_RC6_8814B) & BIT_MASK_RARF_RC6_8814B) + + + +#define BIT_SHIFT_RARF_RC5_8814B (32 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC5_8814B 0x1f +#define BIT_RARF_RC5_8814B(x) (((x) & BIT_MASK_RARF_RC5_8814B) << BIT_SHIFT_RARF_RC5_8814B) +#define BIT_GET_RARF_RC5_8814B(x) (((x) >> BIT_SHIFT_RARF_RC5_8814B) & BIT_MASK_RARF_RC5_8814B) + + + +#define BIT_SHIFT_RARF_RC4_8814B 24 +#define BIT_MASK_RARF_RC4_8814B 0x1f +#define BIT_RARF_RC4_8814B(x) (((x) & BIT_MASK_RARF_RC4_8814B) << BIT_SHIFT_RARF_RC4_8814B) +#define BIT_GET_RARF_RC4_8814B(x) (((x) >> BIT_SHIFT_RARF_RC4_8814B) & BIT_MASK_RARF_RC4_8814B) + + + +#define BIT_SHIFT_RARF_RC3_8814B 16 +#define BIT_MASK_RARF_RC3_8814B 0x1f +#define BIT_RARF_RC3_8814B(x) (((x) & BIT_MASK_RARF_RC3_8814B) << BIT_SHIFT_RARF_RC3_8814B) +#define BIT_GET_RARF_RC3_8814B(x) (((x) >> BIT_SHIFT_RARF_RC3_8814B) & BIT_MASK_RARF_RC3_8814B) + + + +#define BIT_SHIFT_RARF_RC2_8814B 8 +#define BIT_MASK_RARF_RC2_8814B 0x1f +#define BIT_RARF_RC2_8814B(x) (((x) & BIT_MASK_RARF_RC2_8814B) << BIT_SHIFT_RARF_RC2_8814B) +#define BIT_GET_RARF_RC2_8814B(x) (((x) >> BIT_SHIFT_RARF_RC2_8814B) & BIT_MASK_RARF_RC2_8814B) + + + +#define BIT_SHIFT_RARF_RC1_8814B 0 +#define BIT_MASK_RARF_RC1_8814B 0x1f +#define BIT_RARF_RC1_8814B(x) (((x) & BIT_MASK_RARF_RC1_8814B) << BIT_SHIFT_RARF_RC1_8814B) +#define BIT_GET_RARF_RC1_8814B(x) (((x) >> BIT_SHIFT_RARF_RC1_8814B) & BIT_MASK_RARF_RC1_8814B) + + + +/* 2 REG_RRSR_8814B */ + +#define BIT_SHIFT_RRSR_RSC_8814B 21 +#define BIT_MASK_RRSR_RSC_8814B 0x3 +#define BIT_RRSR_RSC_8814B(x) (((x) & BIT_MASK_RRSR_RSC_8814B) << BIT_SHIFT_RRSR_RSC_8814B) +#define BIT_GET_RRSR_RSC_8814B(x) (((x) >> BIT_SHIFT_RRSR_RSC_8814B) & BIT_MASK_RRSR_RSC_8814B) + + +#define BIT_RRSR_BW_8814B BIT(20) + +#define BIT_SHIFT_RRSC_BITMAP_8814B 0 +#define BIT_MASK_RRSC_BITMAP_8814B 0xfffff +#define BIT_RRSC_BITMAP_8814B(x) (((x) & BIT_MASK_RRSC_BITMAP_8814B) << BIT_SHIFT_RRSC_BITMAP_8814B) +#define BIT_GET_RRSC_BITMAP_8814B(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8814B) & BIT_MASK_RRSC_BITMAP_8814B) + + + +/* 2 REG_ARFR0_8814B */ + +#define BIT_SHIFT_ARFR0_V1_8814B 0 +#define BIT_MASK_ARFR0_V1_8814B 0xffffffffffffffffL +#define BIT_ARFR0_V1_8814B(x) (((x) & BIT_MASK_ARFR0_V1_8814B) << BIT_SHIFT_ARFR0_V1_8814B) +#define BIT_GET_ARFR0_V1_8814B(x) (((x) >> BIT_SHIFT_ARFR0_V1_8814B) & BIT_MASK_ARFR0_V1_8814B) + + + +/* 2 REG_ARFR1_V1_8814B */ + +#define BIT_SHIFT_ARFR1_V1_8814B 0 +#define BIT_MASK_ARFR1_V1_8814B 0xffffffffffffffffL +#define BIT_ARFR1_V1_8814B(x) (((x) & BIT_MASK_ARFR1_V1_8814B) << BIT_SHIFT_ARFR1_V1_8814B) +#define BIT_GET_ARFR1_V1_8814B(x) (((x) >> BIT_SHIFT_ARFR1_V1_8814B) & BIT_MASK_ARFR1_V1_8814B) + + + +/* 2 REG_CCK_CHECK_8814B */ +#define BIT_CHECK_CCK_EN_8814B BIT(7) +#define BIT_EN_BCN_PKT_REL_8814B BIT(6) +#define BIT_BCN_PORT_SEL_8814B BIT(5) +#define BIT_MOREDATA_BYPASS_8814B BIT(4) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_8814B BIT(3) +#define BIT_R_EN_SET_MOREDATA_8814B BIT(2) +#define BIT__R_DIS_CLEAR_MACID_RELEASE_8814B BIT(1) +#define BIT__R_MACID_RELEASE_EN_8814B BIT(0) + +/* 2 REG_AMPDU_MAX_TIME_V1_8814B */ + +#define BIT_SHIFT_AMPDU_MAX_TIME_8814B 0 +#define BIT_MASK_AMPDU_MAX_TIME_8814B 0xff +#define BIT_AMPDU_MAX_TIME_8814B(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8814B) << BIT_SHIFT_AMPDU_MAX_TIME_8814B) +#define BIT_GET_AMPDU_MAX_TIME_8814B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8814B) & BIT_MASK_AMPDU_MAX_TIME_8814B) + + + +/* 2 REG_BCNQ1_BDNY_V1_8814B */ + +#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8814B 0 +#define BIT_MASK_BCNQ1_PGBNDY_V1_8814B 0xfff +#define BIT_BCNQ1_PGBNDY_V1_8814B(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8814B) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8814B) +#define BIT_GET_BCNQ1_PGBNDY_V1_8814B(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8814B) & BIT_MASK_BCNQ1_PGBNDY_V1_8814B) + + + +/* 2 REG_AMPDU_MAX_LENGTH_8814B */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_8814B 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_8814B 0xffffffffL +#define BIT_AMPDU_MAX_LENGTH_8814B(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8814B) << BIT_SHIFT_AMPDU_MAX_LENGTH_8814B) +#define BIT_GET_AMPDU_MAX_LENGTH_8814B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8814B) & BIT_MASK_AMPDU_MAX_LENGTH_8814B) + + + +/* 2 REG_ACQ_STOP_8814B */ +#define BIT_AC7Q_STOP_8814B BIT(7) +#define BIT_AC6Q_STOP_8814B BIT(6) +#define BIT_AC5Q_STOP_8814B BIT(5) +#define BIT_AC4Q_STOP_8814B BIT(4) +#define BIT_AC3Q_STOP_8814B BIT(3) +#define BIT_AC2Q_STOP_8814B BIT(2) +#define BIT_AC1Q_STOP_8814B BIT(1) +#define BIT_AC0Q_STOP_8814B BIT(0) + +/* 2 REG_NDPA_RATE_8814B */ + +#define BIT_SHIFT_R_NDPA_RATE_V1_8814B 0 +#define BIT_MASK_R_NDPA_RATE_V1_8814B 0xff +#define BIT_R_NDPA_RATE_V1_8814B(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8814B) << BIT_SHIFT_R_NDPA_RATE_V1_8814B) +#define BIT_GET_R_NDPA_RATE_V1_8814B(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8814B) & BIT_MASK_R_NDPA_RATE_V1_8814B) + + + +/* 2 REG_TX_HANG_CTRL_8814B */ +#define BIT_R_EN_GNT_BT_AWAKE_8814B BIT(3) +#define BIT_EN_EOF_V1_8814B BIT(2) +#define BIT_DIS_OQT_BLOCK_8814B BIT(1) +#define BIT_SEARCH_QUEUE_EN_8814B BIT(0) + +/* 2 REG_NDPA_OPT_CTRL_8814B */ +#define BIT_R_DIS_MACID_RELEASE_RTY_8814B BIT(5) + +#define BIT_SHIFT_BW_SIGTA_8814B 3 +#define BIT_MASK_BW_SIGTA_8814B 0x3 +#define BIT_BW_SIGTA_8814B(x) (((x) & BIT_MASK_BW_SIGTA_8814B) << BIT_SHIFT_BW_SIGTA_8814B) +#define BIT_GET_BW_SIGTA_8814B(x) (((x) >> BIT_SHIFT_BW_SIGTA_8814B) & BIT_MASK_BW_SIGTA_8814B) + + +#define BIT_EN_BAR_SIGTA_8814B BIT(2) + +#define BIT_SHIFT_R_NDPA_BW_8814B 0 +#define BIT_MASK_R_NDPA_BW_8814B 0x3 +#define BIT_R_NDPA_BW_8814B(x) (((x) & BIT_MASK_R_NDPA_BW_8814B) << BIT_SHIFT_R_NDPA_BW_8814B) +#define BIT_GET_R_NDPA_BW_8814B(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8814B) & BIT_MASK_R_NDPA_BW_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_RD_RESP_PKT_TH_8814B */ + +#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B 0 +#define BIT_MASK_RD_RESP_PKT_TH_V1_8814B 0x3f +#define BIT_RD_RESP_PKT_TH_V1_8814B(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8814B) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) +#define BIT_GET_RD_RESP_PKT_TH_V1_8814B(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) & BIT_MASK_RD_RESP_PKT_TH_V1_8814B) + + + +/* 2 REG_CMDQ_INFO_8814B */ + +#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8814B 25 +#define BIT_MASK_QUEUEMACID_CMDQ_V1_8814B 0x7f +#define BIT_QUEUEMACID_CMDQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8814B) << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8814B) +#define BIT_GET_QUEUEMACID_CMDQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8814B) & BIT_MASK_QUEUEMACID_CMDQ_V1_8814B) + + + +#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8814B 23 +#define BIT_MASK_QUEUEAC_CMDQ_V1_8814B 0x3 +#define BIT_QUEUEAC_CMDQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8814B) << BIT_SHIFT_QUEUEAC_CMDQ_V1_8814B) +#define BIT_GET_QUEUEAC_CMDQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8814B) & BIT_MASK_QUEUEAC_CMDQ_V1_8814B) + + +#define BIT_TIDEMPTY_CMDQ_V1_8814B BIT(22) + +#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8814B 11 +#define BIT_MASK_TAIL_PKT_CMDQ_V2_8814B 0x7ff +#define BIT_TAIL_PKT_CMDQ_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8814B) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8814B) +#define BIT_GET_TAIL_PKT_CMDQ_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8814B) & BIT_MASK_TAIL_PKT_CMDQ_V2_8814B) + + + +#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8814B 0 +#define BIT_MASK_HEAD_PKT_CMDQ_V1_8814B 0x7ff +#define BIT_HEAD_PKT_CMDQ_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8814B) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8814B) +#define BIT_GET_HEAD_PKT_CMDQ_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8814B) & BIT_MASK_HEAD_PKT_CMDQ_V1_8814B) + + + +/* 2 REG_Q4_INFO_8814B */ + +#define BIT_SHIFT_QUEUEMACID_Q4_V1_8814B 25 +#define BIT_MASK_QUEUEMACID_Q4_V1_8814B 0x7f +#define BIT_QUEUEMACID_Q4_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q4_V1_8814B) +#define BIT_GET_QUEUEMACID_Q4_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8814B) & BIT_MASK_QUEUEMACID_Q4_V1_8814B) + + + +#define BIT_SHIFT_QUEUEAC_Q4_V1_8814B 23 +#define BIT_MASK_QUEUEAC_Q4_V1_8814B 0x3 +#define BIT_QUEUEAC_Q4_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8814B) << BIT_SHIFT_QUEUEAC_Q4_V1_8814B) +#define BIT_GET_QUEUEAC_Q4_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8814B) & BIT_MASK_QUEUEAC_Q4_V1_8814B) + + +#define BIT_TIDEMPTY_Q4_V1_8814B BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q4_V2_8814B 11 +#define BIT_MASK_TAIL_PKT_Q4_V2_8814B 0x7ff +#define BIT_TAIL_PKT_Q4_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q4_V2_8814B) +#define BIT_GET_TAIL_PKT_Q4_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8814B) & BIT_MASK_TAIL_PKT_Q4_V2_8814B) + + + +#define BIT_SHIFT_HEAD_PKT_Q4_V1_8814B 0 +#define BIT_MASK_HEAD_PKT_Q4_V1_8814B 0x7ff +#define BIT_HEAD_PKT_Q4_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q4_V1_8814B) +#define BIT_GET_HEAD_PKT_Q4_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8814B) & BIT_MASK_HEAD_PKT_Q4_V1_8814B) + + + +/* 2 REG_Q5_INFO_8814B */ + +#define BIT_SHIFT_QUEUEMACID_Q5_V1_8814B 25 +#define BIT_MASK_QUEUEMACID_Q5_V1_8814B 0x7f +#define BIT_QUEUEMACID_Q5_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q5_V1_8814B) +#define BIT_GET_QUEUEMACID_Q5_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8814B) & BIT_MASK_QUEUEMACID_Q5_V1_8814B) + + + +#define BIT_SHIFT_QUEUEAC_Q5_V1_8814B 23 +#define BIT_MASK_QUEUEAC_Q5_V1_8814B 0x3 +#define BIT_QUEUEAC_Q5_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8814B) << BIT_SHIFT_QUEUEAC_Q5_V1_8814B) +#define BIT_GET_QUEUEAC_Q5_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8814B) & BIT_MASK_QUEUEAC_Q5_V1_8814B) + + +#define BIT_TIDEMPTY_Q5_V1_8814B BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q5_V2_8814B 11 +#define BIT_MASK_TAIL_PKT_Q5_V2_8814B 0x7ff +#define BIT_TAIL_PKT_Q5_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q5_V2_8814B) +#define BIT_GET_TAIL_PKT_Q5_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8814B) & BIT_MASK_TAIL_PKT_Q5_V2_8814B) + + + +#define BIT_SHIFT_HEAD_PKT_Q5_V1_8814B 0 +#define BIT_MASK_HEAD_PKT_Q5_V1_8814B 0x7ff +#define BIT_HEAD_PKT_Q5_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q5_V1_8814B) +#define BIT_GET_HEAD_PKT_Q5_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8814B) & BIT_MASK_HEAD_PKT_Q5_V1_8814B) + + + +/* 2 REG_Q6_INFO_8814B */ + +#define BIT_SHIFT_QUEUEMACID_Q6_V1_8814B 25 +#define BIT_MASK_QUEUEMACID_Q6_V1_8814B 0x7f +#define BIT_QUEUEMACID_Q6_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q6_V1_8814B) +#define BIT_GET_QUEUEMACID_Q6_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8814B) & BIT_MASK_QUEUEMACID_Q6_V1_8814B) + + + +#define BIT_SHIFT_QUEUEAC_Q6_V1_8814B 23 +#define BIT_MASK_QUEUEAC_Q6_V1_8814B 0x3 +#define BIT_QUEUEAC_Q6_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8814B) << BIT_SHIFT_QUEUEAC_Q6_V1_8814B) +#define BIT_GET_QUEUEAC_Q6_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8814B) & BIT_MASK_QUEUEAC_Q6_V1_8814B) + + +#define BIT_TIDEMPTY_Q6_V1_8814B BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q6_V2_8814B 11 +#define BIT_MASK_TAIL_PKT_Q6_V2_8814B 0x7ff +#define BIT_TAIL_PKT_Q6_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q6_V2_8814B) +#define BIT_GET_TAIL_PKT_Q6_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8814B) & BIT_MASK_TAIL_PKT_Q6_V2_8814B) + + + +#define BIT_SHIFT_HEAD_PKT_Q6_V1_8814B 0 +#define BIT_MASK_HEAD_PKT_Q6_V1_8814B 0x7ff +#define BIT_HEAD_PKT_Q6_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q6_V1_8814B) +#define BIT_GET_HEAD_PKT_Q6_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8814B) & BIT_MASK_HEAD_PKT_Q6_V1_8814B) + + + +/* 2 REG_Q7_INFO_8814B */ + +#define BIT_SHIFT_QUEUEMACID_Q7_V1_8814B 25 +#define BIT_MASK_QUEUEMACID_Q7_V1_8814B 0x7f +#define BIT_QUEUEMACID_Q7_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q7_V1_8814B) +#define BIT_GET_QUEUEMACID_Q7_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8814B) & BIT_MASK_QUEUEMACID_Q7_V1_8814B) + + + +#define BIT_SHIFT_QUEUEAC_Q7_V1_8814B 23 +#define BIT_MASK_QUEUEAC_Q7_V1_8814B 0x3 +#define BIT_QUEUEAC_Q7_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8814B) << BIT_SHIFT_QUEUEAC_Q7_V1_8814B) +#define BIT_GET_QUEUEAC_Q7_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8814B) & BIT_MASK_QUEUEAC_Q7_V1_8814B) + + +#define BIT_TIDEMPTY_Q7_V1_8814B BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q7_V2_8814B 11 +#define BIT_MASK_TAIL_PKT_Q7_V2_8814B 0x7ff +#define BIT_TAIL_PKT_Q7_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q7_V2_8814B) +#define BIT_GET_TAIL_PKT_Q7_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8814B) & BIT_MASK_TAIL_PKT_Q7_V2_8814B) + + + +#define BIT_SHIFT_HEAD_PKT_Q7_V1_8814B 0 +#define BIT_MASK_HEAD_PKT_Q7_V1_8814B 0x7ff +#define BIT_HEAD_PKT_Q7_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q7_V1_8814B) +#define BIT_GET_HEAD_PKT_Q7_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8814B) & BIT_MASK_HEAD_PKT_Q7_V1_8814B) + + + +/* 2 REG_WMAC_LBK_BUF_HD_V1_8814B */ + +#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B 0 +#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B 0xfff +#define BIT_WMAC_LBK_BUF_HEAD_V1_8814B(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8814B(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B) + + + +/* 2 REG_MGQ_BDNY_V1_8814B */ + +#define BIT_SHIFT_MGQ_PGBNDY_V1_8814B 0 +#define BIT_MASK_MGQ_PGBNDY_V1_8814B 0xfff +#define BIT_MGQ_PGBNDY_V1_8814B(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8814B) << BIT_SHIFT_MGQ_PGBNDY_V1_8814B) +#define BIT_GET_MGQ_PGBNDY_V1_8814B(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8814B) & BIT_MASK_MGQ_PGBNDY_V1_8814B) + + + +/* 2 REG_TXRPT_CTRL_8814B */ + +#define BIT_SHIFT_TRXRPT_TIMER_TH_8814B 24 +#define BIT_MASK_TRXRPT_TIMER_TH_8814B 0xff +#define BIT_TRXRPT_TIMER_TH_8814B(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8814B) << BIT_SHIFT_TRXRPT_TIMER_TH_8814B) +#define BIT_GET_TRXRPT_TIMER_TH_8814B(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8814B) & BIT_MASK_TRXRPT_TIMER_TH_8814B) + + + +#define BIT_SHIFT_TRXRPT_LEN_TH_8814B 16 +#define BIT_MASK_TRXRPT_LEN_TH_8814B 0xff +#define BIT_TRXRPT_LEN_TH_8814B(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8814B) << BIT_SHIFT_TRXRPT_LEN_TH_8814B) +#define BIT_GET_TRXRPT_LEN_TH_8814B(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8814B) & BIT_MASK_TRXRPT_LEN_TH_8814B) + + + +#define BIT_SHIFT_TRXRPT_READ_PTR_8814B 8 +#define BIT_MASK_TRXRPT_READ_PTR_8814B 0xff +#define BIT_TRXRPT_READ_PTR_8814B(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8814B) << BIT_SHIFT_TRXRPT_READ_PTR_8814B) +#define BIT_GET_TRXRPT_READ_PTR_8814B(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8814B) & BIT_MASK_TRXRPT_READ_PTR_8814B) + + + +#define BIT_SHIFT_TRXRPT_WRITE_PTR_8814B 0 +#define BIT_MASK_TRXRPT_WRITE_PTR_8814B 0xff +#define BIT_TRXRPT_WRITE_PTR_8814B(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8814B) << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) +#define BIT_GET_TRXRPT_WRITE_PTR_8814B(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) & BIT_MASK_TRXRPT_WRITE_PTR_8814B) + + + +/* 2 REG_INIRTS_RATE_SEL_8814B */ +#define BIT_LEAG_RTS_BW_DUP_8814B BIT(5) + +/* 2 REG_BASIC_CFEND_RATE_8814B */ + +#define BIT_SHIFT_BASIC_CFEND_RATE_8814B 0 +#define BIT_MASK_BASIC_CFEND_RATE_8814B 0x1f +#define BIT_BASIC_CFEND_RATE_8814B(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8814B) << BIT_SHIFT_BASIC_CFEND_RATE_8814B) +#define BIT_GET_BASIC_CFEND_RATE_8814B(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8814B) & BIT_MASK_BASIC_CFEND_RATE_8814B) + + + +/* 2 REG_STBC_CFEND_RATE_8814B */ + +#define BIT_SHIFT_STBC_CFEND_RATE_8814B 0 +#define BIT_MASK_STBC_CFEND_RATE_8814B 0x1f +#define BIT_STBC_CFEND_RATE_8814B(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8814B) << BIT_SHIFT_STBC_CFEND_RATE_8814B) +#define BIT_GET_STBC_CFEND_RATE_8814B(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8814B) & BIT_MASK_STBC_CFEND_RATE_8814B) + + + +/* 2 REG_DATA_SC_8814B */ + +#define BIT_SHIFT_TXSC_40M_8814B 4 +#define BIT_MASK_TXSC_40M_8814B 0xf +#define BIT_TXSC_40M_8814B(x) (((x) & BIT_MASK_TXSC_40M_8814B) << BIT_SHIFT_TXSC_40M_8814B) +#define BIT_GET_TXSC_40M_8814B(x) (((x) >> BIT_SHIFT_TXSC_40M_8814B) & BIT_MASK_TXSC_40M_8814B) + + + +#define BIT_SHIFT_TXSC_20M_8814B 0 +#define BIT_MASK_TXSC_20M_8814B 0xf +#define BIT_TXSC_20M_8814B(x) (((x) & BIT_MASK_TXSC_20M_8814B) << BIT_SHIFT_TXSC_20M_8814B) +#define BIT_GET_TXSC_20M_8814B(x) (((x) >> BIT_SHIFT_TXSC_20M_8814B) & BIT_MASK_TXSC_20M_8814B) + + + +/* 2 REG_MACID_SLEEP3_8814B */ + +#define BIT_SHIFT_MACID127_96_PKTSLEEP_8814B 0 +#define BIT_MASK_MACID127_96_PKTSLEEP_8814B 0xffffffffL +#define BIT_MACID127_96_PKTSLEEP_8814B(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8814B) << BIT_SHIFT_MACID127_96_PKTSLEEP_8814B) +#define BIT_GET_MACID127_96_PKTSLEEP_8814B(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8814B) & BIT_MASK_MACID127_96_PKTSLEEP_8814B) + + + +/* 2 REG_MACID_SLEEP1_8814B */ + +#define BIT_SHIFT_MACID63_32_PKTSLEEP_8814B 0 +#define BIT_MASK_MACID63_32_PKTSLEEP_8814B 0xffffffffL +#define BIT_MACID63_32_PKTSLEEP_8814B(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8814B) << BIT_SHIFT_MACID63_32_PKTSLEEP_8814B) +#define BIT_GET_MACID63_32_PKTSLEEP_8814B(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8814B) & BIT_MASK_MACID63_32_PKTSLEEP_8814B) + + + +/* 2 REG_ARFR2_V1_8814B */ + +#define BIT_SHIFT_ARFR2_V1_8814B 0 +#define BIT_MASK_ARFR2_V1_8814B 0xffffffffffffffffL +#define BIT_ARFR2_V1_8814B(x) (((x) & BIT_MASK_ARFR2_V1_8814B) << BIT_SHIFT_ARFR2_V1_8814B) +#define BIT_GET_ARFR2_V1_8814B(x) (((x) >> BIT_SHIFT_ARFR2_V1_8814B) & BIT_MASK_ARFR2_V1_8814B) + + + +/* 2 REG_ARFR3_V1_8814B */ + +#define BIT_SHIFT_ARFR3_V1_8814B 0 +#define BIT_MASK_ARFR3_V1_8814B 0xffffffffffffffffL +#define BIT_ARFR3_V1_8814B(x) (((x) & BIT_MASK_ARFR3_V1_8814B) << BIT_SHIFT_ARFR3_V1_8814B) +#define BIT_GET_ARFR3_V1_8814B(x) (((x) >> BIT_SHIFT_ARFR3_V1_8814B) & BIT_MASK_ARFR3_V1_8814B) + + + +/* 2 REG_ARFR4_8814B */ + +#define BIT_SHIFT_ARFR4_8814B 0 +#define BIT_MASK_ARFR4_8814B 0xffffffffffffffffL +#define BIT_ARFR4_8814B(x) (((x) & BIT_MASK_ARFR4_8814B) << BIT_SHIFT_ARFR4_8814B) +#define BIT_GET_ARFR4_8814B(x) (((x) >> BIT_SHIFT_ARFR4_8814B) & BIT_MASK_ARFR4_8814B) + + + +/* 2 REG_ARFR5_8814B */ + +#define BIT_SHIFT_ARFR5_8814B 0 +#define BIT_MASK_ARFR5_8814B 0xffffffffffffffffL +#define BIT_ARFR5_8814B(x) (((x) & BIT_MASK_ARFR5_8814B) << BIT_SHIFT_ARFR5_8814B) +#define BIT_GET_ARFR5_8814B(x) (((x) >> BIT_SHIFT_ARFR5_8814B) & BIT_MASK_ARFR5_8814B) + + + +/* 2 REG_TXRPT_START_OFFSET_8814B */ + +#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8814B 24 +#define BIT_MASK_R_MUTAB_TXRPT_OFFSET_8814B 0xff +#define BIT_R_MUTAB_TXRPT_OFFSET_8814B(x) (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8814B) << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8814B) +#define BIT_GET_R_MUTAB_TXRPT_OFFSET_8814B(x) (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8814B) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8814B) + + +#define BIT__R_RPTFIFO_1K_8814B BIT(16) + +#define BIT_SHIFT_MACID_CTRL_OFFSET_8814B 8 +#define BIT_MASK_MACID_CTRL_OFFSET_8814B 0xff +#define BIT_MACID_CTRL_OFFSET_8814B(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8814B) << BIT_SHIFT_MACID_CTRL_OFFSET_8814B) +#define BIT_GET_MACID_CTRL_OFFSET_8814B(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8814B) & BIT_MASK_MACID_CTRL_OFFSET_8814B) + + + +#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8814B 0 +#define BIT_MASK_AMPDU_TXRPT_OFFSET_8814B 0xff +#define BIT_AMPDU_TXRPT_OFFSET_8814B(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8814B) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8814B) +#define BIT_GET_AMPDU_TXRPT_OFFSET_8814B(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8814B) & BIT_MASK_AMPDU_TXRPT_OFFSET_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_POWER_STAGE1_8814B */ +#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8814B BIT(31) +#define BIT_PTA_WL_PRI_MASK_BCNQ_8814B BIT(30) +#define BIT_PTA_WL_PRI_MASK_HIQ_8814B BIT(29) +#define BIT_PTA_WL_PRI_MASK_MGQ_8814B BIT(28) +#define BIT_PTA_WL_PRI_MASK_BK_8814B BIT(27) +#define BIT_PTA_WL_PRI_MASK_BE_8814B BIT(26) +#define BIT_PTA_WL_PRI_MASK_VI_8814B BIT(25) +#define BIT_PTA_WL_PRI_MASK_VO_8814B BIT(24) + +#define BIT_SHIFT_POWER_STAGE1_8814B 0 +#define BIT_MASK_POWER_STAGE1_8814B 0xffffff +#define BIT_POWER_STAGE1_8814B(x) (((x) & BIT_MASK_POWER_STAGE1_8814B) << BIT_SHIFT_POWER_STAGE1_8814B) +#define BIT_GET_POWER_STAGE1_8814B(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8814B) & BIT_MASK_POWER_STAGE1_8814B) + + + +/* 2 REG_POWER_STAGE2_8814B */ +#define BIT__R_CTRL_PKT_POW_ADJ_8814B BIT(24) + +#define BIT_SHIFT_POWER_STAGE2_8814B 0 +#define BIT_MASK_POWER_STAGE2_8814B 0xffffff +#define BIT_POWER_STAGE2_8814B(x) (((x) & BIT_MASK_POWER_STAGE2_8814B) << BIT_SHIFT_POWER_STAGE2_8814B) +#define BIT_GET_POWER_STAGE2_8814B(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8814B) & BIT_MASK_POWER_STAGE2_8814B) + + + +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8814B */ + +#define BIT_SHIFT_PAD_NUM_THRES_8814B 24 +#define BIT_MASK_PAD_NUM_THRES_8814B 0x3f +#define BIT_PAD_NUM_THRES_8814B(x) (((x) & BIT_MASK_PAD_NUM_THRES_8814B) << BIT_SHIFT_PAD_NUM_THRES_8814B) +#define BIT_GET_PAD_NUM_THRES_8814B(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8814B) & BIT_MASK_PAD_NUM_THRES_8814B) + + +#define BIT_R_DMA_THIS_QUEUE_BK_8814B BIT(23) +#define BIT_R_DMA_THIS_QUEUE_BE_8814B BIT(22) +#define BIT_R_DMA_THIS_QUEUE_VI_8814B BIT(21) +#define BIT_R_DMA_THIS_QUEUE_VO_8814B BIT(20) + +#define BIT_SHIFT_R_TOTAL_LEN_TH_8814B 8 +#define BIT_MASK_R_TOTAL_LEN_TH_8814B 0xfff +#define BIT_R_TOTAL_LEN_TH_8814B(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8814B) << BIT_SHIFT_R_TOTAL_LEN_TH_8814B) +#define BIT_GET_R_TOTAL_LEN_TH_8814B(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8814B) & BIT_MASK_R_TOTAL_LEN_TH_8814B) + + +#define BIT_EN_NEW_EARLY_8814B BIT(7) +#define BIT_PRE_TX_CMD_8814B BIT(6) + +#define BIT_SHIFT_NUM_SCL_EN_8814B 4 +#define BIT_MASK_NUM_SCL_EN_8814B 0x3 +#define BIT_NUM_SCL_EN_8814B(x) (((x) & BIT_MASK_NUM_SCL_EN_8814B) << BIT_SHIFT_NUM_SCL_EN_8814B) +#define BIT_GET_NUM_SCL_EN_8814B(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8814B) & BIT_MASK_NUM_SCL_EN_8814B) + + +#define BIT_BK_EN_8814B BIT(3) +#define BIT_BE_EN_8814B BIT(2) +#define BIT_VI_EN_8814B BIT(1) +#define BIT_VO_EN_8814B BIT(0) + +/* 2 REG_PKT_LIFE_TIME_8814B */ + +#define BIT_SHIFT_PKT_LIFTIME_BEBK_8814B 16 +#define BIT_MASK_PKT_LIFTIME_BEBK_8814B 0xffff +#define BIT_PKT_LIFTIME_BEBK_8814B(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8814B) << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) +#define BIT_GET_PKT_LIFTIME_BEBK_8814B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) & BIT_MASK_PKT_LIFTIME_BEBK_8814B) + + + +#define BIT_SHIFT_PKT_LIFTIME_VOVI_8814B 0 +#define BIT_MASK_PKT_LIFTIME_VOVI_8814B 0xffff +#define BIT_PKT_LIFTIME_VOVI_8814B(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8814B) << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) +#define BIT_GET_PKT_LIFTIME_VOVI_8814B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) & BIT_MASK_PKT_LIFTIME_VOVI_8814B) + + + +/* 2 REG_STBC_SETTING_8814B */ + +#define BIT_SHIFT_CDEND_TXTIME_L_8814B 4 +#define BIT_MASK_CDEND_TXTIME_L_8814B 0xf +#define BIT_CDEND_TXTIME_L_8814B(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8814B) << BIT_SHIFT_CDEND_TXTIME_L_8814B) +#define BIT_GET_CDEND_TXTIME_L_8814B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8814B) & BIT_MASK_CDEND_TXTIME_L_8814B) + + + +#define BIT_SHIFT_NESS_8814B 2 +#define BIT_MASK_NESS_8814B 0x3 +#define BIT_NESS_8814B(x) (((x) & BIT_MASK_NESS_8814B) << BIT_SHIFT_NESS_8814B) +#define BIT_GET_NESS_8814B(x) (((x) >> BIT_SHIFT_NESS_8814B) & BIT_MASK_NESS_8814B) + + + +#define BIT_SHIFT_STBC_CFEND_8814B 0 +#define BIT_MASK_STBC_CFEND_8814B 0x3 +#define BIT_STBC_CFEND_8814B(x) (((x) & BIT_MASK_STBC_CFEND_8814B) << BIT_SHIFT_STBC_CFEND_8814B) +#define BIT_GET_STBC_CFEND_8814B(x) (((x) >> BIT_SHIFT_STBC_CFEND_8814B) & BIT_MASK_STBC_CFEND_8814B) + + + +/* 2 REG_STBC_SETTING2_8814B */ + +#define BIT_SHIFT_CDEND_TXTIME_H_8814B 0 +#define BIT_MASK_CDEND_TXTIME_H_8814B 0x1f +#define BIT_CDEND_TXTIME_H_8814B(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8814B) << BIT_SHIFT_CDEND_TXTIME_H_8814B) +#define BIT_GET_CDEND_TXTIME_H_8814B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8814B) & BIT_MASK_CDEND_TXTIME_H_8814B) + + + +/* 2 REG_QUEUE_CTRL_8814B */ +#define BIT_PTA_EDCCA_EN_8814B BIT(5) +#define BIT_PTA_WL_TX_EN_8814B BIT(4) +#define BIT_R_USE_DATA_BW_8814B BIT(3) +#define BIT_TRI_PKT_INT_MODE1_8814B BIT(2) +#define BIT_TRI_PKT_INT_MODE0_8814B BIT(1) +#define BIT_ACQ_MODE_SEL_8814B BIT(0) + +/* 2 REG_SINGLE_AMPDU_CTRL_8814B */ +#define BIT_EN_SINGLE_APMDU_8814B BIT(7) + +/* 2 REG_PROT_MODE_CTRL_8814B */ + +#define BIT_SHIFT_RTS_MAX_AGG_NUM_8814B 24 +#define BIT_MASK_RTS_MAX_AGG_NUM_8814B 0x3f +#define BIT_RTS_MAX_AGG_NUM_8814B(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8814B) << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) +#define BIT_GET_RTS_MAX_AGG_NUM_8814B(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) & BIT_MASK_RTS_MAX_AGG_NUM_8814B) + + + +#define BIT_SHIFT_MAX_AGG_NUM_8814B 16 +#define BIT_MASK_MAX_AGG_NUM_8814B 0x3f +#define BIT_MAX_AGG_NUM_8814B(x) (((x) & BIT_MASK_MAX_AGG_NUM_8814B) << BIT_SHIFT_MAX_AGG_NUM_8814B) +#define BIT_GET_MAX_AGG_NUM_8814B(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8814B) & BIT_MASK_MAX_AGG_NUM_8814B) + + + +#define BIT_SHIFT_RTS_TXTIME_TH_8814B 8 +#define BIT_MASK_RTS_TXTIME_TH_8814B 0xff +#define BIT_RTS_TXTIME_TH_8814B(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8814B) << BIT_SHIFT_RTS_TXTIME_TH_8814B) +#define BIT_GET_RTS_TXTIME_TH_8814B(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8814B) & BIT_MASK_RTS_TXTIME_TH_8814B) + + + +#define BIT_SHIFT_RTS_LEN_TH_8814B 0 +#define BIT_MASK_RTS_LEN_TH_8814B 0xff +#define BIT_RTS_LEN_TH_8814B(x) (((x) & BIT_MASK_RTS_LEN_TH_8814B) << BIT_SHIFT_RTS_LEN_TH_8814B) +#define BIT_GET_RTS_LEN_TH_8814B(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8814B) & BIT_MASK_RTS_LEN_TH_8814B) + + + +/* 2 REG_BAR_MODE_CTRL_8814B */ + +#define BIT_SHIFT_BAR_RTY_LMT_8814B 16 +#define BIT_MASK_BAR_RTY_LMT_8814B 0x3 +#define BIT_BAR_RTY_LMT_8814B(x) (((x) & BIT_MASK_BAR_RTY_LMT_8814B) << BIT_SHIFT_BAR_RTY_LMT_8814B) +#define BIT_GET_BAR_RTY_LMT_8814B(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8814B) & BIT_MASK_BAR_RTY_LMT_8814B) + + + +#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B 8 +#define BIT_MASK_BAR_PKT_TXTIME_TH_8814B 0xff +#define BIT_BAR_PKT_TXTIME_TH_8814B(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8814B) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) +#define BIT_GET_BAR_PKT_TXTIME_TH_8814B(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) & BIT_MASK_BAR_PKT_TXTIME_TH_8814B) + + +#define BIT_BAR_EN_V1_8814B BIT(6) + +#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B 0 +#define BIT_MASK_BAR_PKTNUM_TH_V1_8814B 0x3f +#define BIT_BAR_PKTNUM_TH_V1_8814B(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8814B) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) +#define BIT_GET_BAR_PKTNUM_TH_V1_8814B(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) & BIT_MASK_BAR_PKTNUM_TH_V1_8814B) + + + +/* 2 REG_RA_TRY_RATE_AGG_LMT_8814B */ + +#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B 0 +#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B 0x3f +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8814B(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B) + + + +/* 2 REG_MACID_SLEEP2_8814B */ + +#define BIT_SHIFT_MACID95_64PKTSLEEP_8814B 0 +#define BIT_MASK_MACID95_64PKTSLEEP_8814B 0xffffffffL +#define BIT_MACID95_64PKTSLEEP_8814B(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8814B) << BIT_SHIFT_MACID95_64PKTSLEEP_8814B) +#define BIT_GET_MACID95_64PKTSLEEP_8814B(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8814B) & BIT_MASK_MACID95_64PKTSLEEP_8814B) + + + +/* 2 REG_MACID_SLEEP_8814B */ + +#define BIT_SHIFT_MACID31_0_PKTSLEEP_8814B 0 +#define BIT_MASK_MACID31_0_PKTSLEEP_8814B 0xffffffffL +#define BIT_MACID31_0_PKTSLEEP_8814B(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8814B) << BIT_SHIFT_MACID31_0_PKTSLEEP_8814B) +#define BIT_GET_MACID31_0_PKTSLEEP_8814B(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8814B) & BIT_MASK_MACID31_0_PKTSLEEP_8814B) + + + +/* 2 REG_HW_SEQ0_8814B */ + +#define BIT_SHIFT_HW_SSN_SEQ0_8814B 0 +#define BIT_MASK_HW_SSN_SEQ0_8814B 0xfff +#define BIT_HW_SSN_SEQ0_8814B(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8814B) << BIT_SHIFT_HW_SSN_SEQ0_8814B) +#define BIT_GET_HW_SSN_SEQ0_8814B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8814B) & BIT_MASK_HW_SSN_SEQ0_8814B) + + + +/* 2 REG_HW_SEQ1_8814B */ + +#define BIT_SHIFT_HW_SSN_SEQ1_8814B 0 +#define BIT_MASK_HW_SSN_SEQ1_8814B 0xfff +#define BIT_HW_SSN_SEQ1_8814B(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8814B) << BIT_SHIFT_HW_SSN_SEQ1_8814B) +#define BIT_GET_HW_SSN_SEQ1_8814B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8814B) & BIT_MASK_HW_SSN_SEQ1_8814B) + + + +/* 2 REG_HW_SEQ2_8814B */ + +#define BIT_SHIFT_HW_SSN_SEQ2_8814B 0 +#define BIT_MASK_HW_SSN_SEQ2_8814B 0xfff +#define BIT_HW_SSN_SEQ2_8814B(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8814B) << BIT_SHIFT_HW_SSN_SEQ2_8814B) +#define BIT_GET_HW_SSN_SEQ2_8814B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8814B) & BIT_MASK_HW_SSN_SEQ2_8814B) + + + +/* 2 REG_HW_SEQ3_8814B */ + +#define BIT_SHIFT_HW_SSN_SEQ3_8814B 0 +#define BIT_MASK_HW_SSN_SEQ3_8814B 0xfff +#define BIT_HW_SSN_SEQ3_8814B(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8814B) << BIT_SHIFT_HW_SSN_SEQ3_8814B) +#define BIT_GET_HW_SSN_SEQ3_8814B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8814B) & BIT_MASK_HW_SSN_SEQ3_8814B) + + + +/* 2 REG_NULL_PKT_STATUS_V1_8814B */ + +#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8814B 2 +#define BIT_MASK_PTCL_TOTAL_PG_V2_8814B 0x3fff +#define BIT_PTCL_TOTAL_PG_V2_8814B(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8814B) << BIT_SHIFT_PTCL_TOTAL_PG_V2_8814B) +#define BIT_GET_PTCL_TOTAL_PG_V2_8814B(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8814B) & BIT_MASK_PTCL_TOTAL_PG_V2_8814B) + + +#define BIT_TX_NULL_1_8814B BIT(1) +#define BIT_TX_NULL_0_8814B BIT(0) + +/* 2 REG_PTCL_ERR_STATUS_8814B */ +#define BIT_PTCL_RATE_TABLE_INVALID_8814B BIT(7) +#define BIT_FTM_T2R_ERROR_8814B BIT(6) +#define BIT_PTCL_ERR0_8814B BIT(5) +#define BIT_PTCL_ERR1_8814B BIT(4) +#define BIT_PTCL_ERR2_8814B BIT(3) +#define BIT_PTCL_ERR3_8814B BIT(2) +#define BIT_PTCL_ERR4_8814B BIT(1) +#define BIT_PTCL_ERR5_8814B BIT(0) + +/* 2 REG_NULL_PKT_STATUS_EXTEND_8814B */ +#define BIT_CLI3_TX_NULL_1_8814B BIT(7) +#define BIT_CLI3_TX_NULL_0_8814B BIT(6) +#define BIT_CLI2_TX_NULL_1_8814B BIT(5) +#define BIT_CLI2_TX_NULL_0_8814B BIT(4) +#define BIT_CLI1_TX_NULL_1_8814B BIT(3) +#define BIT_CLI1_TX_NULL_0_8814B BIT(2) +#define BIT_CLI0_TX_NULL_1_8814B BIT(1) +#define BIT_CLI0_TX_NULL_0_8814B BIT(0) + +/* 2 REG_VIDEO_ENHANCEMENT_FUN_8814B */ +#define BIT_VIDEO_JUST_DROP_8814B BIT(1) +#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8814B BIT(0) + +/* 2 REG_BT_POLLUTE_PKT_CNT_8814B */ + +#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8814B 0 +#define BIT_MASK_BT_POLLUTE_PKT_CNT_8814B 0xffff +#define BIT_BT_POLLUTE_PKT_CNT_8814B(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8814B) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8814B) +#define BIT_GET_BT_POLLUTE_PKT_CNT_8814B(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8814B) & BIT_MASK_BT_POLLUTE_PKT_CNT_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_PTCL_DBG_8814B */ + +#define BIT_SHIFT_PTCL_DBG_8814B 0 +#define BIT_MASK_PTCL_DBG_8814B 0xffffffffL +#define BIT_PTCL_DBG_8814B(x) (((x) & BIT_MASK_PTCL_DBG_8814B) << BIT_SHIFT_PTCL_DBG_8814B) +#define BIT_GET_PTCL_DBG_8814B(x) (((x) >> BIT_SHIFT_PTCL_DBG_8814B) & BIT_MASK_PTCL_DBG_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_CPUMGQ_TIMER_CTRL2_8814B */ + +#define BIT_SHIFT_TRI_HEAD_ADDR_8814B 16 +#define BIT_MASK_TRI_HEAD_ADDR_8814B 0xfff +#define BIT_TRI_HEAD_ADDR_8814B(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8814B) << BIT_SHIFT_TRI_HEAD_ADDR_8814B) +#define BIT_GET_TRI_HEAD_ADDR_8814B(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8814B) & BIT_MASK_TRI_HEAD_ADDR_8814B) + + +#define BIT_DROP_TH_EN_8814B BIT(8) + +#define BIT_SHIFT_DROP_TH_8814B 0 +#define BIT_MASK_DROP_TH_8814B 0xff +#define BIT_DROP_TH_8814B(x) (((x) & BIT_MASK_DROP_TH_8814B) << BIT_SHIFT_DROP_TH_8814B) +#define BIT_GET_DROP_TH_8814B(x) (((x) >> BIT_SHIFT_DROP_TH_8814B) & BIT_MASK_DROP_TH_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_DUMMY_PAGE4_V1_8814B */ + +/* 2 REG_MOREDATA_8814B */ +#define BIT_MOREDATA_CTRL2_EN_V1_8814B BIT(3) +#define BIT_MOREDATA_CTRL1_EN_V1_8814B BIT(2) +#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_Q0_Q1_INFO_8814B */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8814B BIT(31) + +#define BIT_SHIFT_GTAB_ID_8814B 28 +#define BIT_MASK_GTAB_ID_8814B 0x7 +#define BIT_GTAB_ID_8814B(x) (((x) & BIT_MASK_GTAB_ID_8814B) << BIT_SHIFT_GTAB_ID_8814B) +#define BIT_GET_GTAB_ID_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_8814B) & BIT_MASK_GTAB_ID_8814B) + + + +#define BIT_SHIFT_AC1_PKT_INFO_8814B 16 +#define BIT_MASK_AC1_PKT_INFO_8814B 0xfff +#define BIT_AC1_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC1_PKT_INFO_8814B) << BIT_SHIFT_AC1_PKT_INFO_8814B) +#define BIT_GET_AC1_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8814B) & BIT_MASK_AC1_PKT_INFO_8814B) + + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8814B BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8814B 12 +#define BIT_MASK_GTAB_ID_V1_8814B 0x7 +#define BIT_GTAB_ID_V1_8814B(x) (((x) & BIT_MASK_GTAB_ID_V1_8814B) << BIT_SHIFT_GTAB_ID_V1_8814B) +#define BIT_GET_GTAB_ID_V1_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8814B) & BIT_MASK_GTAB_ID_V1_8814B) + + + +#define BIT_SHIFT_AC0_PKT_INFO_8814B 0 +#define BIT_MASK_AC0_PKT_INFO_8814B 0xfff +#define BIT_AC0_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC0_PKT_INFO_8814B) << BIT_SHIFT_AC0_PKT_INFO_8814B) +#define BIT_GET_AC0_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8814B) & BIT_MASK_AC0_PKT_INFO_8814B) + + + +/* 2 REG_Q2_Q3_INFO_8814B */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8814B BIT(31) + +#define BIT_SHIFT_GTAB_ID_8814B 28 +#define BIT_MASK_GTAB_ID_8814B 0x7 +#define BIT_GTAB_ID_8814B(x) (((x) & BIT_MASK_GTAB_ID_8814B) << BIT_SHIFT_GTAB_ID_8814B) +#define BIT_GET_GTAB_ID_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_8814B) & BIT_MASK_GTAB_ID_8814B) + + + +#define BIT_SHIFT_AC3_PKT_INFO_8814B 16 +#define BIT_MASK_AC3_PKT_INFO_8814B 0xfff +#define BIT_AC3_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC3_PKT_INFO_8814B) << BIT_SHIFT_AC3_PKT_INFO_8814B) +#define BIT_GET_AC3_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8814B) & BIT_MASK_AC3_PKT_INFO_8814B) + + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8814B BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8814B 12 +#define BIT_MASK_GTAB_ID_V1_8814B 0x7 +#define BIT_GTAB_ID_V1_8814B(x) (((x) & BIT_MASK_GTAB_ID_V1_8814B) << BIT_SHIFT_GTAB_ID_V1_8814B) +#define BIT_GET_GTAB_ID_V1_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8814B) & BIT_MASK_GTAB_ID_V1_8814B) + + + +#define BIT_SHIFT_AC2_PKT_INFO_8814B 0 +#define BIT_MASK_AC2_PKT_INFO_8814B 0xfff +#define BIT_AC2_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC2_PKT_INFO_8814B) << BIT_SHIFT_AC2_PKT_INFO_8814B) +#define BIT_GET_AC2_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8814B) & BIT_MASK_AC2_PKT_INFO_8814B) + + + +/* 2 REG_Q4_Q5_INFO_8814B */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8814B BIT(31) + +#define BIT_SHIFT_GTAB_ID_8814B 28 +#define BIT_MASK_GTAB_ID_8814B 0x7 +#define BIT_GTAB_ID_8814B(x) (((x) & BIT_MASK_GTAB_ID_8814B) << BIT_SHIFT_GTAB_ID_8814B) +#define BIT_GET_GTAB_ID_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_8814B) & BIT_MASK_GTAB_ID_8814B) + + + +#define BIT_SHIFT_AC5_PKT_INFO_8814B 16 +#define BIT_MASK_AC5_PKT_INFO_8814B 0xfff +#define BIT_AC5_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC5_PKT_INFO_8814B) << BIT_SHIFT_AC5_PKT_INFO_8814B) +#define BIT_GET_AC5_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8814B) & BIT_MASK_AC5_PKT_INFO_8814B) + + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8814B BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8814B 12 +#define BIT_MASK_GTAB_ID_V1_8814B 0x7 +#define BIT_GTAB_ID_V1_8814B(x) (((x) & BIT_MASK_GTAB_ID_V1_8814B) << BIT_SHIFT_GTAB_ID_V1_8814B) +#define BIT_GET_GTAB_ID_V1_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8814B) & BIT_MASK_GTAB_ID_V1_8814B) + + + +#define BIT_SHIFT_AC4_PKT_INFO_8814B 0 +#define BIT_MASK_AC4_PKT_INFO_8814B 0xfff +#define BIT_AC4_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC4_PKT_INFO_8814B) << BIT_SHIFT_AC4_PKT_INFO_8814B) +#define BIT_GET_AC4_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8814B) & BIT_MASK_AC4_PKT_INFO_8814B) + + + +/* 2 REG_Q6_Q7_INFO_8814B */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8814B BIT(31) + +#define BIT_SHIFT_GTAB_ID_8814B 28 +#define BIT_MASK_GTAB_ID_8814B 0x7 +#define BIT_GTAB_ID_8814B(x) (((x) & BIT_MASK_GTAB_ID_8814B) << BIT_SHIFT_GTAB_ID_8814B) +#define BIT_GET_GTAB_ID_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_8814B) & BIT_MASK_GTAB_ID_8814B) + + + +#define BIT_SHIFT_AC7_PKT_INFO_8814B 16 +#define BIT_MASK_AC7_PKT_INFO_8814B 0xfff +#define BIT_AC7_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC7_PKT_INFO_8814B) << BIT_SHIFT_AC7_PKT_INFO_8814B) +#define BIT_GET_AC7_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8814B) & BIT_MASK_AC7_PKT_INFO_8814B) + + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8814B BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8814B 12 +#define BIT_MASK_GTAB_ID_V1_8814B 0x7 +#define BIT_GTAB_ID_V1_8814B(x) (((x) & BIT_MASK_GTAB_ID_V1_8814B) << BIT_SHIFT_GTAB_ID_V1_8814B) +#define BIT_GET_GTAB_ID_V1_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8814B) & BIT_MASK_GTAB_ID_V1_8814B) + + + +#define BIT_SHIFT_AC6_PKT_INFO_8814B 0 +#define BIT_MASK_AC6_PKT_INFO_8814B 0xfff +#define BIT_AC6_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC6_PKT_INFO_8814B) << BIT_SHIFT_AC6_PKT_INFO_8814B) +#define BIT_GET_AC6_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8814B) & BIT_MASK_AC6_PKT_INFO_8814B) + + + +/* 2 REG_MGQ_HIQ_INFO_8814B */ + +#define BIT_SHIFT_HIQ_PKT_INFO_8814B 16 +#define BIT_MASK_HIQ_PKT_INFO_8814B 0xfff +#define BIT_HIQ_PKT_INFO_8814B(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8814B) << BIT_SHIFT_HIQ_PKT_INFO_8814B) +#define BIT_GET_HIQ_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8814B) & BIT_MASK_HIQ_PKT_INFO_8814B) + + + +#define BIT_SHIFT_MGQ_PKT_INFO_8814B 0 +#define BIT_MASK_MGQ_PKT_INFO_8814B 0xfff +#define BIT_MGQ_PKT_INFO_8814B(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8814B) << BIT_SHIFT_MGQ_PKT_INFO_8814B) +#define BIT_GET_MGQ_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8814B) & BIT_MASK_MGQ_PKT_INFO_8814B) + + + +/* 2 REG_CMDQ_BCNQ_INFO_8814B */ + +#define BIT_SHIFT_CMDQ_PKT_INFO_8814B 16 +#define BIT_MASK_CMDQ_PKT_INFO_8814B 0xfff +#define BIT_CMDQ_PKT_INFO_8814B(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_8814B) << BIT_SHIFT_CMDQ_PKT_INFO_8814B) +#define BIT_GET_CMDQ_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8814B) & BIT_MASK_CMDQ_PKT_INFO_8814B) + + + +#define BIT_SHIFT_BCNQ_PKT_INFO_8814B 0 +#define BIT_MASK_BCNQ_PKT_INFO_8814B 0xfff +#define BIT_BCNQ_PKT_INFO_8814B(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_8814B) << BIT_SHIFT_BCNQ_PKT_INFO_8814B) +#define BIT_GET_BCNQ_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8814B) & BIT_MASK_BCNQ_PKT_INFO_8814B) + + + +/* 2 REG_USEREG_SETTING_8814B */ +#define BIT_NDPA_USEREG_8814B BIT(21) + +#define BIT_SHIFT_RETRY_USEREG_8814B 19 +#define BIT_MASK_RETRY_USEREG_8814B 0x3 +#define BIT_RETRY_USEREG_8814B(x) (((x) & BIT_MASK_RETRY_USEREG_8814B) << BIT_SHIFT_RETRY_USEREG_8814B) +#define BIT_GET_RETRY_USEREG_8814B(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8814B) & BIT_MASK_RETRY_USEREG_8814B) + + + +#define BIT_SHIFT_TRYPKT_USEREG_8814B 17 +#define BIT_MASK_TRYPKT_USEREG_8814B 0x3 +#define BIT_TRYPKT_USEREG_8814B(x) (((x) & BIT_MASK_TRYPKT_USEREG_8814B) << BIT_SHIFT_TRYPKT_USEREG_8814B) +#define BIT_GET_TRYPKT_USEREG_8814B(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8814B) & BIT_MASK_TRYPKT_USEREG_8814B) + + +#define BIT_CTLPKT_USEREG_8814B BIT(16) + +/* 2 REG_AESIV_SETTING_8814B */ + +#define BIT_SHIFT_AESIV_OFFSET_8814B 0 +#define BIT_MASK_AESIV_OFFSET_8814B 0xfff +#define BIT_AESIV_OFFSET_8814B(x) (((x) & BIT_MASK_AESIV_OFFSET_8814B) << BIT_SHIFT_AESIV_OFFSET_8814B) +#define BIT_GET_AESIV_OFFSET_8814B(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8814B) & BIT_MASK_AESIV_OFFSET_8814B) + + + +/* 2 REG_BF0_TIME_SETTING_8814B */ +#define BIT_BF0_TIMER_SET_8814B BIT(31) +#define BIT_BF0_TIMER_CLR_8814B BIT(30) +#define BIT_BF0_UPDATE_EN_8814B BIT(29) +#define BIT_BF0_TIMER_EN_8814B BIT(28) + +#define BIT_SHIFT_BF0_PRETIME_OVER_8814B 16 +#define BIT_MASK_BF0_PRETIME_OVER_8814B 0xfff +#define BIT_BF0_PRETIME_OVER_8814B(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8814B) << BIT_SHIFT_BF0_PRETIME_OVER_8814B) +#define BIT_GET_BF0_PRETIME_OVER_8814B(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8814B) & BIT_MASK_BF0_PRETIME_OVER_8814B) + + + +#define BIT_SHIFT_BF0_LIFETIME_8814B 0 +#define BIT_MASK_BF0_LIFETIME_8814B 0xffff +#define BIT_BF0_LIFETIME_8814B(x) (((x) & BIT_MASK_BF0_LIFETIME_8814B) << BIT_SHIFT_BF0_LIFETIME_8814B) +#define BIT_GET_BF0_LIFETIME_8814B(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8814B) & BIT_MASK_BF0_LIFETIME_8814B) + + + +/* 2 REG_BF1_TIME_SETTING_8814B */ +#define BIT_BF1_TIMER_SET_8814B BIT(31) +#define BIT_BF1_TIMER_CLR_8814B BIT(30) +#define BIT_BF1_UPDATE_EN_8814B BIT(29) +#define BIT_BF1_TIMER_EN_8814B BIT(28) + +#define BIT_SHIFT_BF1_PRETIME_OVER_8814B 16 +#define BIT_MASK_BF1_PRETIME_OVER_8814B 0xfff +#define BIT_BF1_PRETIME_OVER_8814B(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8814B) << BIT_SHIFT_BF1_PRETIME_OVER_8814B) +#define BIT_GET_BF1_PRETIME_OVER_8814B(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8814B) & BIT_MASK_BF1_PRETIME_OVER_8814B) + + + +#define BIT_SHIFT_BF1_LIFETIME_8814B 0 +#define BIT_MASK_BF1_LIFETIME_8814B 0xffff +#define BIT_BF1_LIFETIME_8814B(x) (((x) & BIT_MASK_BF1_LIFETIME_8814B) << BIT_SHIFT_BF1_LIFETIME_8814B) +#define BIT_GET_BF1_LIFETIME_8814B(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8814B) & BIT_MASK_BF1_LIFETIME_8814B) + + + +/* 2 REG_BF_TIMEOUT_EN_8814B */ +#define BIT_EN_VHT_LDPC_8814B BIT(9) +#define BIT_EN_HT_LDPC_8814B BIT(8) +#define BIT_BF1_TIMEOUT_EN_8814B BIT(1) +#define BIT_BF0_TIMEOUT_EN_8814B BIT(0) + +/* 2 REG_MACID_RELEASE0_8814B */ + +#define BIT_SHIFT_MACID31_0_RELEASE_8814B 0 +#define BIT_MASK_MACID31_0_RELEASE_8814B 0xffffffffL +#define BIT_MACID31_0_RELEASE_8814B(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8814B) << BIT_SHIFT_MACID31_0_RELEASE_8814B) +#define BIT_GET_MACID31_0_RELEASE_8814B(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8814B) & BIT_MASK_MACID31_0_RELEASE_8814B) + + + +/* 2 REG_MACID_RELEASE1_8814B */ + +#define BIT_SHIFT_MACID63_32_RELEASE_8814B 0 +#define BIT_MASK_MACID63_32_RELEASE_8814B 0xffffffffL +#define BIT_MACID63_32_RELEASE_8814B(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8814B) << BIT_SHIFT_MACID63_32_RELEASE_8814B) +#define BIT_GET_MACID63_32_RELEASE_8814B(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8814B) & BIT_MASK_MACID63_32_RELEASE_8814B) + + + +/* 2 REG_MACID_RELEASE2_8814B */ + +#define BIT_SHIFT_MACID95_64_RELEASE_8814B 0 +#define BIT_MASK_MACID95_64_RELEASE_8814B 0xffffffffL +#define BIT_MACID95_64_RELEASE_8814B(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8814B) << BIT_SHIFT_MACID95_64_RELEASE_8814B) +#define BIT_GET_MACID95_64_RELEASE_8814B(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8814B) & BIT_MASK_MACID95_64_RELEASE_8814B) + + + +/* 2 REG_MACID_RELEASE3_8814B */ + +#define BIT_SHIFT_MACID127_96_RELEASE_8814B 0 +#define BIT_MASK_MACID127_96_RELEASE_8814B 0xffffffffL +#define BIT_MACID127_96_RELEASE_8814B(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8814B) << BIT_SHIFT_MACID127_96_RELEASE_8814B) +#define BIT_GET_MACID127_96_RELEASE_8814B(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8814B) & BIT_MASK_MACID127_96_RELEASE_8814B) + + + +/* 2 REG_MACID_RELEASE_SETTING_8814B */ +#define BIT_MACID_VALUE_8814B BIT(7) + +#define BIT_SHIFT_MACID_OFFSET_8814B 0 +#define BIT_MASK_MACID_OFFSET_8814B 0x7f +#define BIT_MACID_OFFSET_8814B(x) (((x) & BIT_MASK_MACID_OFFSET_8814B) << BIT_SHIFT_MACID_OFFSET_8814B) +#define BIT_GET_MACID_OFFSET_8814B(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8814B) & BIT_MASK_MACID_OFFSET_8814B) + + + +/* 2 REG_FAST_EDCA_VOVI_SETTING_8814B */ + +#define BIT_SHIFT_VI_FAST_EDCA_TO_8814B 24 +#define BIT_MASK_VI_FAST_EDCA_TO_8814B 0xff +#define BIT_VI_FAST_EDCA_TO_8814B(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8814B) << BIT_SHIFT_VI_FAST_EDCA_TO_8814B) +#define BIT_GET_VI_FAST_EDCA_TO_8814B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8814B) & BIT_MASK_VI_FAST_EDCA_TO_8814B) + + +#define BIT_VI_THRESHOLD_SEL_8814B BIT(23) + +#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B 16 +#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B 0x7f +#define BIT_VI_FAST_EDCA_PKT_TH_8814B(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8814B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B) + + + +#define BIT_SHIFT_VO_FAST_EDCA_TO_8814B 8 +#define BIT_MASK_VO_FAST_EDCA_TO_8814B 0xff +#define BIT_VO_FAST_EDCA_TO_8814B(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8814B) << BIT_SHIFT_VO_FAST_EDCA_TO_8814B) +#define BIT_GET_VO_FAST_EDCA_TO_8814B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8814B) & BIT_MASK_VO_FAST_EDCA_TO_8814B) + + +#define BIT_VO_THRESHOLD_SEL_8814B BIT(7) + +#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B 0 +#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B 0x7f +#define BIT_VO_FAST_EDCA_PKT_TH_8814B(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8814B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B) + + + +/* 2 REG_FAST_EDCA_BEBK_SETTING_8814B */ + +#define BIT_SHIFT_BK_FAST_EDCA_TO_8814B 24 +#define BIT_MASK_BK_FAST_EDCA_TO_8814B 0xff +#define BIT_BK_FAST_EDCA_TO_8814B(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8814B) << BIT_SHIFT_BK_FAST_EDCA_TO_8814B) +#define BIT_GET_BK_FAST_EDCA_TO_8814B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8814B) & BIT_MASK_BK_FAST_EDCA_TO_8814B) + + +#define BIT_BK_THRESHOLD_SEL_8814B BIT(23) + +#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B 16 +#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B 0x7f +#define BIT_BK_FAST_EDCA_PKT_TH_8814B(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8814B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B) + + + +#define BIT_SHIFT_BE_FAST_EDCA_TO_8814B 8 +#define BIT_MASK_BE_FAST_EDCA_TO_8814B 0xff +#define BIT_BE_FAST_EDCA_TO_8814B(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8814B) << BIT_SHIFT_BE_FAST_EDCA_TO_8814B) +#define BIT_GET_BE_FAST_EDCA_TO_8814B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8814B) & BIT_MASK_BE_FAST_EDCA_TO_8814B) + + +#define BIT_BE_THRESHOLD_SEL_8814B BIT(7) + +#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B 0 +#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B 0x7f +#define BIT_BE_FAST_EDCA_PKT_TH_8814B(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8814B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B) + + + +/* 2 REG_MACID_DROP0_8814B */ + +#define BIT_SHIFT_MACID31_0_DROP_8814B 0 +#define BIT_MASK_MACID31_0_DROP_8814B 0xffffffffL +#define BIT_MACID31_0_DROP_8814B(x) (((x) & BIT_MASK_MACID31_0_DROP_8814B) << BIT_SHIFT_MACID31_0_DROP_8814B) +#define BIT_GET_MACID31_0_DROP_8814B(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8814B) & BIT_MASK_MACID31_0_DROP_8814B) + + + +/* 2 REG_MACID_DROP1_8814B */ + +#define BIT_SHIFT_MACID63_32_DROP_8814B 0 +#define BIT_MASK_MACID63_32_DROP_8814B 0xffffffffL +#define BIT_MACID63_32_DROP_8814B(x) (((x) & BIT_MASK_MACID63_32_DROP_8814B) << BIT_SHIFT_MACID63_32_DROP_8814B) +#define BIT_GET_MACID63_32_DROP_8814B(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8814B) & BIT_MASK_MACID63_32_DROP_8814B) + + + +/* 2 REG_MACID_DROP2_8814B */ + +#define BIT_SHIFT_MACID95_64_DROP_8814B 0 +#define BIT_MASK_MACID95_64_DROP_8814B 0xffffffffL +#define BIT_MACID95_64_DROP_8814B(x) (((x) & BIT_MASK_MACID95_64_DROP_8814B) << BIT_SHIFT_MACID95_64_DROP_8814B) +#define BIT_GET_MACID95_64_DROP_8814B(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8814B) & BIT_MASK_MACID95_64_DROP_8814B) + + + +/* 2 REG_MACID_DROP3_8814B */ + +#define BIT_SHIFT_MACID127_96_DROP_8814B 0 +#define BIT_MASK_MACID127_96_DROP_8814B 0xffffffffL +#define BIT_MACID127_96_DROP_8814B(x) (((x) & BIT_MASK_MACID127_96_DROP_8814B) << BIT_SHIFT_MACID127_96_DROP_8814B) +#define BIT_GET_MACID127_96_DROP_8814B(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8814B) & BIT_MASK_MACID127_96_DROP_8814B) + + + +/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8814B */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8814B 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8814B 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_0_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8814B) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8814B) + + + +/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8814B */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8814B 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8814B 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_1_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8814B) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8814B) + + + +/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8814B */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8814B 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8814B 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_2_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8814B) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8814B) + + + +/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8814B */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8814B 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8814B 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_3_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8814B) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8814B) + + + +/* 2 REG_MGG_FIFO_CRTL_8814B */ +#define BIT_R_MGG_FIFO_EN_8814B BIT(31) + +#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8814B 28 +#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8814B 0x7 +#define BIT_R_MGG_FIFO_PG_SIZE_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8814B) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8814B) +#define BIT_GET_R_MGG_FIFO_PG_SIZE_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8814B) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8814B) + + + +#define BIT_SHIFT_R_MGG_FIFO_START_PG_8814B 16 +#define BIT_MASK_R_MGG_FIFO_START_PG_8814B 0xfff +#define BIT_R_MGG_FIFO_START_PG_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8814B) << BIT_SHIFT_R_MGG_FIFO_START_PG_8814B) +#define BIT_GET_R_MGG_FIFO_START_PG_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8814B) & BIT_MASK_R_MGG_FIFO_START_PG_8814B) + + + +#define BIT_SHIFT_R_MGG_FIFO_SIZE_8814B 14 +#define BIT_MASK_R_MGG_FIFO_SIZE_8814B 0x3 +#define BIT_R_MGG_FIFO_SIZE_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8814B) << BIT_SHIFT_R_MGG_FIFO_SIZE_8814B) +#define BIT_GET_R_MGG_FIFO_SIZE_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8814B) & BIT_MASK_R_MGG_FIFO_SIZE_8814B) + + +#define BIT_R_MGG_FIFO_PAUSE_8814B BIT(13) + +#define BIT_SHIFT_R_MGG_FIFO_RPTR_8814B 8 +#define BIT_MASK_R_MGG_FIFO_RPTR_8814B 0x1f +#define BIT_R_MGG_FIFO_RPTR_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8814B) << BIT_SHIFT_R_MGG_FIFO_RPTR_8814B) +#define BIT_GET_R_MGG_FIFO_RPTR_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8814B) & BIT_MASK_R_MGG_FIFO_RPTR_8814B) + + +#define BIT_R_MGG_FIFO_OV_8814B BIT(7) +#define BIT_R_MGG_FIFO_WPTR_ERROR_8814B BIT(6) +#define BIT_R_EN_CPU_LIFETIME_8814B BIT(5) + +#define BIT_SHIFT_R_MGG_FIFO_WPTR_8814B 0 +#define BIT_MASK_R_MGG_FIFO_WPTR_8814B 0x1f +#define BIT_R_MGG_FIFO_WPTR_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8814B) << BIT_SHIFT_R_MGG_FIFO_WPTR_8814B) +#define BIT_GET_R_MGG_FIFO_WPTR_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8814B) & BIT_MASK_R_MGG_FIFO_WPTR_8814B) + + + +/* 2 REG_MGG_FIFO_INT_8814B */ + +#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8814B 16 +#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8814B 0xffff +#define BIT_R_MGG_FIFO_INT_FLAG_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8814B) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8814B) +#define BIT_GET_R_MGG_FIFO_INT_FLAG_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8814B) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8814B) + + + +#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8814B 0 +#define BIT_MASK_R_MGG_FIFO_INT_MASK_8814B 0xffff +#define BIT_R_MGG_FIFO_INT_MASK_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8814B) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8814B) +#define BIT_GET_R_MGG_FIFO_INT_MASK_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8814B) & BIT_MASK_R_MGG_FIFO_INT_MASK_8814B) + + + +/* 2 REG_MGG_FIFO_LIFETIME_8814B */ + +#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8814B 16 +#define BIT_MASK_R_MGG_FIFO_LIFETIME_8814B 0xffff +#define BIT_R_MGG_FIFO_LIFETIME_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8814B) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8814B) +#define BIT_GET_R_MGG_FIFO_LIFETIME_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8814B) & BIT_MASK_R_MGG_FIFO_LIFETIME_8814B) + + + +#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8814B 0 +#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8814B 0xffff +#define BIT_R_MGG_FIFO_VALID_MAP_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8814B) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8814B) +#define BIT_GET_R_MGG_FIFO_VALID_MAP_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8814B) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8814B) + + + +/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B 0x7f +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B) + + + +/* 2 REG_MU_TX_CTL_8814B (NOT SUPPORT) */ +#define BIT_R_FORCE_P1_RATEDOWN_8814B BIT(11) + +#define BIT_SHIFT_R_MU_TAB_SEL_8814B 8 +#define BIT_MASK_R_MU_TAB_SEL_8814B 0x7 +#define BIT_R_MU_TAB_SEL_8814B(x) (((x) & BIT_MASK_R_MU_TAB_SEL_8814B) << BIT_SHIFT_R_MU_TAB_SEL_8814B) +#define BIT_GET_R_MU_TAB_SEL_8814B(x) (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8814B) & BIT_MASK_R_MU_TAB_SEL_8814B) + + +#define BIT_R_EN_MU_MIMO_8814B BIT(7) +#define BIT_R_EN_REVERS_GTAB_8814B BIT(6) + +#define BIT_SHIFT_R_MU_TABLE_VALID_8814B 0 +#define BIT_MASK_R_MU_TABLE_VALID_8814B 0x3f +#define BIT_R_MU_TABLE_VALID_8814B(x) (((x) & BIT_MASK_R_MU_TABLE_VALID_8814B) << BIT_SHIFT_R_MU_TABLE_VALID_8814B) +#define BIT_GET_R_MU_TABLE_VALID_8814B(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8814B) & BIT_MASK_R_MU_TABLE_VALID_8814B) + + + +/* 2 REG_MU_STA_GID_VLD_8814B (NOT SUPPORT) */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B 0 +#define BIT_MASK_R_MU_STA_GTAB_VALID_8814B 0xffffffffL +#define BIT_R_MU_STA_GTAB_VALID_8814B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8814B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B) +#define BIT_GET_R_MU_STA_GTAB_VALID_8814B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B) & BIT_MASK_R_MU_STA_GTAB_VALID_8814B) + + + +#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B 0 +#define BIT_MASK_R_MU_STA_GTAB_VALID_8814B 0xffffffffL +#define BIT_R_MU_STA_GTAB_VALID_8814B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8814B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B) +#define BIT_GET_R_MU_STA_GTAB_VALID_8814B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B) & BIT_MASK_R_MU_STA_GTAB_VALID_8814B) + + + +/* 2 REG_MU_STA_USER_POS_INFO_8814B (NOT SUPPORT) */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_8814B 0xffffffffffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_8814B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8814B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B) +#define BIT_GET_R_MU_STA_GTAB_POSITION_8814B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8814B) + + + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_8814B 0xffffffffffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_8814B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8814B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B) +#define BIT_GET_R_MU_STA_GTAB_POSITION_8814B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8814B) + + + +/* 2 REG_MU_TRX_DBG_CNT_8814B (NOT SUPPORT) */ +#define BIT_MU_DNGCNT_RST_8814B BIT(20) + +#define BIT_SHIFT_MU_DBGCNT_SEL_8814B 16 +#define BIT_MASK_MU_DBGCNT_SEL_8814B 0xf +#define BIT_MU_DBGCNT_SEL_8814B(x) (((x) & BIT_MASK_MU_DBGCNT_SEL_8814B) << BIT_SHIFT_MU_DBGCNT_SEL_8814B) +#define BIT_GET_MU_DBGCNT_SEL_8814B(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8814B) & BIT_MASK_MU_DBGCNT_SEL_8814B) + + + +#define BIT_SHIFT_MU_DNGCNT_8814B 0 +#define BIT_MASK_MU_DNGCNT_8814B 0xffff +#define BIT_MU_DNGCNT_8814B(x) (((x) & BIT_MASK_MU_DNGCNT_8814B) << BIT_SHIFT_MU_DNGCNT_8814B) +#define BIT_GET_MU_DNGCNT_8814B(x) (((x) >> BIT_SHIFT_MU_DNGCNT_8814B) & BIT_MASK_MU_DNGCNT_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_EDCA_VO_PARAM_8814B */ + +#define BIT_SHIFT_TXOPLIMIT_8814B 16 +#define BIT_MASK_TXOPLIMIT_8814B 0x7ff +#define BIT_TXOPLIMIT_8814B(x) (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) +#define BIT_GET_TXOPLIMIT_8814B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) + + + +#define BIT_SHIFT_CW_8814B 8 +#define BIT_MASK_CW_8814B 0xff +#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B) +#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B) + + + +#define BIT_SHIFT_AIFS_8814B 0 +#define BIT_MASK_AIFS_8814B 0xff +#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B) +#define BIT_GET_AIFS_8814B(x) (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) + + + +/* 2 REG_EDCA_VI_PARAM_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXOPLIMIT_8814B 16 +#define BIT_MASK_TXOPLIMIT_8814B 0x7ff +#define BIT_TXOPLIMIT_8814B(x) (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) +#define BIT_GET_TXOPLIMIT_8814B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) + + + +#define BIT_SHIFT_CW_8814B 8 +#define BIT_MASK_CW_8814B 0xff +#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B) +#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B) + + + +#define BIT_SHIFT_AIFS_8814B 0 +#define BIT_MASK_AIFS_8814B 0xff +#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B) +#define BIT_GET_AIFS_8814B(x) (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) + + + +/* 2 REG_EDCA_BE_PARAM_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXOPLIMIT_8814B 16 +#define BIT_MASK_TXOPLIMIT_8814B 0x7ff +#define BIT_TXOPLIMIT_8814B(x) (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) +#define BIT_GET_TXOPLIMIT_8814B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) + + + +#define BIT_SHIFT_CW_8814B 8 +#define BIT_MASK_CW_8814B 0xff +#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B) +#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B) + + + +#define BIT_SHIFT_AIFS_8814B 0 +#define BIT_MASK_AIFS_8814B 0xff +#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B) +#define BIT_GET_AIFS_8814B(x) (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) + + + +/* 2 REG_EDCA_BK_PARAM_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXOPLIMIT_8814B 16 +#define BIT_MASK_TXOPLIMIT_8814B 0x7ff +#define BIT_TXOPLIMIT_8814B(x) (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) +#define BIT_GET_TXOPLIMIT_8814B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) + + + +#define BIT_SHIFT_CW_8814B 8 +#define BIT_MASK_CW_8814B 0xff +#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B) +#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B) + + + +#define BIT_SHIFT_AIFS_8814B 0 +#define BIT_MASK_AIFS_8814B 0xff +#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B) +#define BIT_GET_AIFS_8814B(x) (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) + + + +/* 2 REG_BCNTCFG_8814B */ + +#define BIT_SHIFT_BCNCW_MAX_8814B 12 +#define BIT_MASK_BCNCW_MAX_8814B 0xf +#define BIT_BCNCW_MAX_8814B(x) (((x) & BIT_MASK_BCNCW_MAX_8814B) << BIT_SHIFT_BCNCW_MAX_8814B) +#define BIT_GET_BCNCW_MAX_8814B(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8814B) & BIT_MASK_BCNCW_MAX_8814B) + + + +#define BIT_SHIFT_BCNCW_MIN_8814B 8 +#define BIT_MASK_BCNCW_MIN_8814B 0xf +#define BIT_BCNCW_MIN_8814B(x) (((x) & BIT_MASK_BCNCW_MIN_8814B) << BIT_SHIFT_BCNCW_MIN_8814B) +#define BIT_GET_BCNCW_MIN_8814B(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8814B) & BIT_MASK_BCNCW_MIN_8814B) + + + +#define BIT_SHIFT_BCNIFS_8814B 0 +#define BIT_MASK_BCNIFS_8814B 0xff +#define BIT_BCNIFS_8814B(x) (((x) & BIT_MASK_BCNIFS_8814B) << BIT_SHIFT_BCNIFS_8814B) +#define BIT_GET_BCNIFS_8814B(x) (((x) >> BIT_SHIFT_BCNIFS_8814B) & BIT_MASK_BCNIFS_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_PIFS_8814B */ + +#define BIT_SHIFT_PIFS_8814B 0 +#define BIT_MASK_PIFS_8814B 0xff +#define BIT_PIFS_8814B(x) (((x) & BIT_MASK_PIFS_8814B) << BIT_SHIFT_PIFS_8814B) +#define BIT_GET_PIFS_8814B(x) (((x) >> BIT_SHIFT_PIFS_8814B) & BIT_MASK_PIFS_8814B) + + + +/* 2 REG_RDG_PIFS_8814B */ + +#define BIT_SHIFT_RDG_PIFS_8814B 0 +#define BIT_MASK_RDG_PIFS_8814B 0xff +#define BIT_RDG_PIFS_8814B(x) (((x) & BIT_MASK_RDG_PIFS_8814B) << BIT_SHIFT_RDG_PIFS_8814B) +#define BIT_GET_RDG_PIFS_8814B(x) (((x) >> BIT_SHIFT_RDG_PIFS_8814B) & BIT_MASK_RDG_PIFS_8814B) + + + +/* 2 REG_SIFS_8814B */ + +#define BIT_SHIFT_SIFS_OFDM_TRX_8814B 24 +#define BIT_MASK_SIFS_OFDM_TRX_8814B 0xff +#define BIT_SIFS_OFDM_TRX_8814B(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8814B) << BIT_SHIFT_SIFS_OFDM_TRX_8814B) +#define BIT_GET_SIFS_OFDM_TRX_8814B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8814B) & BIT_MASK_SIFS_OFDM_TRX_8814B) + + + +#define BIT_SHIFT_SIFS_CCK_TRX_8814B 16 +#define BIT_MASK_SIFS_CCK_TRX_8814B 0xff +#define BIT_SIFS_CCK_TRX_8814B(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8814B) << BIT_SHIFT_SIFS_CCK_TRX_8814B) +#define BIT_GET_SIFS_CCK_TRX_8814B(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8814B) & BIT_MASK_SIFS_CCK_TRX_8814B) + + + +#define BIT_SHIFT_SIFS_OFDM_CTX_8814B 8 +#define BIT_MASK_SIFS_OFDM_CTX_8814B 0xff +#define BIT_SIFS_OFDM_CTX_8814B(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8814B) << BIT_SHIFT_SIFS_OFDM_CTX_8814B) +#define BIT_GET_SIFS_OFDM_CTX_8814B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8814B) & BIT_MASK_SIFS_OFDM_CTX_8814B) + + + +#define BIT_SHIFT_SIFS_CCK_CTX_8814B 0 +#define BIT_MASK_SIFS_CCK_CTX_8814B 0xff +#define BIT_SIFS_CCK_CTX_8814B(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8814B) << BIT_SHIFT_SIFS_CCK_CTX_8814B) +#define BIT_GET_SIFS_CCK_CTX_8814B(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8814B) & BIT_MASK_SIFS_CCK_CTX_8814B) + + + +/* 2 REG_TSFTR_SYN_OFFSET_8814B */ + +#define BIT_SHIFT_TSFTR_SNC_OFFSET_8814B 0 +#define BIT_MASK_TSFTR_SNC_OFFSET_8814B 0xffff +#define BIT_TSFTR_SNC_OFFSET_8814B(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8814B) << BIT_SHIFT_TSFTR_SNC_OFFSET_8814B) +#define BIT_GET_TSFTR_SNC_OFFSET_8814B(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8814B) & BIT_MASK_TSFTR_SNC_OFFSET_8814B) + + + +/* 2 REG_AGGR_BREAK_TIME_8814B */ + +#define BIT_SHIFT_AGGR_BK_TIME_8814B 0 +#define BIT_MASK_AGGR_BK_TIME_8814B 0xff +#define BIT_AGGR_BK_TIME_8814B(x) (((x) & BIT_MASK_AGGR_BK_TIME_8814B) << BIT_SHIFT_AGGR_BK_TIME_8814B) +#define BIT_GET_AGGR_BK_TIME_8814B(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8814B) & BIT_MASK_AGGR_BK_TIME_8814B) + + + +/* 2 REG_SLOT_8814B */ + +#define BIT_SHIFT_SLOT_8814B 0 +#define BIT_MASK_SLOT_8814B 0xff +#define BIT_SLOT_8814B(x) (((x) & BIT_MASK_SLOT_8814B) << BIT_SHIFT_SLOT_8814B) +#define BIT_GET_SLOT_8814B(x) (((x) >> BIT_SHIFT_SLOT_8814B) & BIT_MASK_SLOT_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_TX_PTCL_CTRL_8814B */ +#define BIT_DIS_EDCCA_8814B BIT(15) +#define BIT_DIS_CCA_8814B BIT(14) +#define BIT_LSIG_TXOP_TXCMD_NAV_8814B BIT(13) +#define BIT_SIFS_BK_EN_8814B BIT(12) + +#define BIT_SHIFT_TXQ_NAV_MSK_8814B 8 +#define BIT_MASK_TXQ_NAV_MSK_8814B 0xf +#define BIT_TXQ_NAV_MSK_8814B(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8814B) << BIT_SHIFT_TXQ_NAV_MSK_8814B) +#define BIT_GET_TXQ_NAV_MSK_8814B(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8814B) & BIT_MASK_TXQ_NAV_MSK_8814B) + + +#define BIT_DIS_CW_8814B BIT(7) +#define BIT_NAV_END_TXOP_8814B BIT(6) +#define BIT_RDG_END_TXOP_8814B BIT(5) +#define BIT_AC_INBCN_HOLD_8814B BIT(4) +#define BIT_MGTQ_TXOP_EN_8814B BIT(3) +#define BIT_MGTQ_RTSMF_EN_8814B BIT(2) +#define BIT_HIQ_RTSMF_EN_8814B BIT(1) +#define BIT_BCN_RTSMF_EN_8814B BIT(0) + +/* 2 REG_TXPAUSE_8814B */ +#define BIT_STOP_BCN_HI_MGT_8814B BIT(7) +#define BIT_MAC_STOPBCNQ_8814B BIT(6) +#define BIT_MAC_STOPHIQ_8814B BIT(5) +#define BIT_MAC_STOPMGQ_8814B BIT(4) +#define BIT_MAC_STOPBK_8814B BIT(3) +#define BIT_MAC_STOPBE_8814B BIT(2) +#define BIT_MAC_STOPVI_8814B BIT(1) +#define BIT_MAC_STOPVO_8814B BIT(0) + +/* 2 REG_DIS_TXREQ_CLR_8814B */ +#define BIT_DIS_BT_CCA_8814B BIT(7) +#define BIT_DIS_TXREQ_CLR_HI_8814B BIT(5) +#define BIT_DIS_TXREQ_CLR_MGQ_8814B BIT(4) +#define BIT_DIS_TXREQ_CLR_VO_8814B BIT(3) +#define BIT_DIS_TXREQ_CLR_VI_8814B BIT(2) +#define BIT_DIS_TXREQ_CLR_BE_8814B BIT(1) +#define BIT_DIS_TXREQ_CLR_BK_8814B BIT(0) + +/* 2 REG_RD_CTRL_8814B */ +#define BIT_EN_CLR_TXREQ_INCCA_8814B BIT(15) +#define BIT_DIS_TX_OVER_BCNQ_8814B BIT(14) +#define BIT_EN_BCNERR_INCCCA_8814B BIT(13) +#define BIT_EDCCA_MSK_CNTDOWN_EN_8814B BIT(11) +#define BIT_DIS_TXOP_CFE_8814B BIT(10) +#define BIT_DIS_LSIG_CFE_8814B BIT(9) +#define BIT_DIS_STBC_CFE_8814B BIT(8) +#define BIT_BKQ_RD_INIT_EN_8814B BIT(7) +#define BIT_BEQ_RD_INIT_EN_8814B BIT(6) +#define BIT_VIQ_RD_INIT_EN_8814B BIT(5) +#define BIT_VOQ_RD_INIT_EN_8814B BIT(4) +#define BIT_BKQ_RD_RESP_EN_8814B BIT(3) +#define BIT_BEQ_RD_RESP_EN_8814B BIT(2) +#define BIT_VIQ_RD_RESP_EN_8814B BIT(1) +#define BIT_VOQ_RD_RESP_EN_8814B BIT(0) + +/* 2 REG_MBSSID_CTRL_8814B */ +#define BIT_MBID_BCNQ7_EN_8814B BIT(7) +#define BIT_MBID_BCNQ6_EN_8814B BIT(6) +#define BIT_MBID_BCNQ5_EN_8814B BIT(5) +#define BIT_MBID_BCNQ4_EN_8814B BIT(4) +#define BIT_MBID_BCNQ3_EN_8814B BIT(3) +#define BIT_MBID_BCNQ2_EN_8814B BIT(2) +#define BIT_MBID_BCNQ1_EN_8814B BIT(1) +#define BIT_MBID_BCNQ0_EN_8814B BIT(0) + +/* 2 REG_P2PPS_CTRL_8814B */ +#define BIT_P2P_CTW_ALLSTASLEEP_8814B BIT(7) +#define BIT_P2P_OFF_DISTX_EN_8814B BIT(6) +#define BIT_PWR_MGT_EN_8814B BIT(5) +#define BIT_P2P_NOA1_EN_8814B BIT(2) +#define BIT_P2P_NOA0_EN_8814B BIT(1) + +/* 2 REG_PKT_LIFETIME_CTRL_8814B */ +#define BIT_EN_P2P_CTWND1_8814B BIT(23) +#define BIT_EN_BKF_CLR_TXREQ_8814B BIT(22) +#define BIT_EN_TSFBIT32_RST_P2P_8814B BIT(21) +#define BIT_EN_BCN_TX_BTCCA_8814B BIT(20) +#define BIT_DIS_PKT_TX_ATIM_8814B BIT(19) +#define BIT_DIS_BCN_DIS_CTN_8814B BIT(18) +#define BIT_EN_NAVEND_RST_TXOP_8814B BIT(17) +#define BIT_EN_FILTER_CCA_8814B BIT(16) + +#define BIT_SHIFT_CCA_FILTER_THRS_8814B 8 +#define BIT_MASK_CCA_FILTER_THRS_8814B 0xff +#define BIT_CCA_FILTER_THRS_8814B(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8814B) << BIT_SHIFT_CCA_FILTER_THRS_8814B) +#define BIT_GET_CCA_FILTER_THRS_8814B(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8814B) & BIT_MASK_CCA_FILTER_THRS_8814B) + + + +#define BIT_SHIFT_EDCCA_THRS_8814B 0 +#define BIT_MASK_EDCCA_THRS_8814B 0xff +#define BIT_EDCCA_THRS_8814B(x) (((x) & BIT_MASK_EDCCA_THRS_8814B) << BIT_SHIFT_EDCCA_THRS_8814B) +#define BIT_GET_EDCCA_THRS_8814B(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8814B) & BIT_MASK_EDCCA_THRS_8814B) + + + +/* 2 REG_P2PPS_SPEC_STATE_8814B */ +#define BIT_SPEC_POWER_STATE_8814B BIT(7) +#define BIT_SPEC_CTWINDOW_ON_8814B BIT(6) +#define BIT_SPEC_BEACON_AREA_ON_8814B BIT(5) +#define BIT_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4) +#define BIT_SPEC_NOA1_OFF_PERIOD_8814B BIT(3) +#define BIT_SPEC_FORCE_DOZE1_8814B BIT(2) +#define BIT_SPEC_NOA0_OFF_PERIOD_8814B BIT(1) +#define BIT_SPEC_FORCE_DOZE0_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_BAR_TX_CTRL_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_P2PON_DIS_TXTIME_8814B 0 +#define BIT_MASK_P2PON_DIS_TXTIME_8814B 0xff +#define BIT_P2PON_DIS_TXTIME_8814B(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8814B) << BIT_SHIFT_P2PON_DIS_TXTIME_8814B) +#define BIT_GET_P2PON_DIS_TXTIME_8814B(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8814B) & BIT_MASK_P2PON_DIS_TXTIME_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_TBTT_PROHIBIT_8814B */ + +#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8814B 8 +#define BIT_MASK_TBTT_HOLD_TIME_AP_8814B 0xfff +#define BIT_TBTT_HOLD_TIME_AP_8814B(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8814B) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8814B) +#define BIT_GET_TBTT_HOLD_TIME_AP_8814B(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8814B) & BIT_MASK_TBTT_HOLD_TIME_AP_8814B) + + + +#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B 0 +#define BIT_MASK_TBTT_PROHIBIT_SETUP_8814B 0xf +#define BIT_TBTT_PROHIBIT_SETUP_8814B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8814B) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8814B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) & BIT_MASK_TBTT_PROHIBIT_SETUP_8814B) + + + +/* 2 REG_P2PPS_STATE_8814B */ +#define BIT_POWER_STATE_8814B BIT(7) +#define BIT_CTWINDOW_ON_8814B BIT(6) +#define BIT_BEACON_AREA_ON_8814B BIT(5) +#define BIT_CTWIN_EARLY_DISTX_8814B BIT(4) +#define BIT_NOA1_OFF_PERIOD_8814B BIT(3) +#define BIT_FORCE_DOZE1_8814B BIT(2) +#define BIT_NOA0_OFF_PERIOD_8814B BIT(1) +#define BIT_FORCE_DOZE0_8814B BIT(0) + +/* 2 REG_RD_NAV_NXT_8814B */ + +#define BIT_SHIFT_RD_NAV_PROT_NXT_8814B 0 +#define BIT_MASK_RD_NAV_PROT_NXT_8814B 0xffff +#define BIT_RD_NAV_PROT_NXT_8814B(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8814B) << BIT_SHIFT_RD_NAV_PROT_NXT_8814B) +#define BIT_GET_RD_NAV_PROT_NXT_8814B(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8814B) & BIT_MASK_RD_NAV_PROT_NXT_8814B) + + + +/* 2 REG_NAV_PROT_LEN_8814B */ + +#define BIT_SHIFT_NAV_PROT_LEN_8814B 0 +#define BIT_MASK_NAV_PROT_LEN_8814B 0xffff +#define BIT_NAV_PROT_LEN_8814B(x) (((x) & BIT_MASK_NAV_PROT_LEN_8814B) << BIT_SHIFT_NAV_PROT_LEN_8814B) +#define BIT_GET_NAV_PROT_LEN_8814B(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8814B) & BIT_MASK_NAV_PROT_LEN_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_BCN_CTRL_8814B */ +#define BIT_DIS_RX_BSSID_FIT_8814B BIT(6) +#define BIT_P0_EN_TXBCN_RPT_8814B BIT(5) +#define BIT_DIS_TSF_UDT_8814B BIT(4) +#define BIT_EN_BCN_FUNCTION_8814B BIT(3) +#define BIT_P0_EN_RXBCN_RPT_8814B BIT(2) +#define BIT_EN_P2P_CTWINDOW_8814B BIT(1) +#define BIT_EN_P2P_BCNQ_AREA_8814B BIT(0) + +/* 2 REG_BCN_CTRL_CLINT0_8814B */ +#define BIT_CLI0_DIS_RX_BSSID_FIT_8814B BIT(6) +#define BIT_CLI0_DIS_TSF_UDT_8814B BIT(4) +#define BIT_CLI0_EN_BCN_FUNCTION_8814B BIT(3) +#define BIT_CLI0_EN_RXBCN_RPT_8814B BIT(2) +#define BIT_CLI0_ENP2P_CTWINDOW_8814B BIT(1) +#define BIT_CLI0_ENP2P_BCNQ_AREA_8814B BIT(0) + +/* 2 REG_MBID_NUM_8814B */ +#define BIT_EN_PRE_DL_BEACON_8814B BIT(3) + +#define BIT_SHIFT_MBID_BCN_NUM_8814B 0 +#define BIT_MASK_MBID_BCN_NUM_8814B 0x7 +#define BIT_MBID_BCN_NUM_8814B(x) (((x) & BIT_MASK_MBID_BCN_NUM_8814B) << BIT_SHIFT_MBID_BCN_NUM_8814B) +#define BIT_GET_MBID_BCN_NUM_8814B(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8814B) & BIT_MASK_MBID_BCN_NUM_8814B) + + + +/* 2 REG_DUAL_TSF_RST_8814B */ +#define BIT_FREECNT_RST_8814B BIT(5) +#define BIT_TSFTR_CLI3_RST_8814B BIT(4) +#define BIT_TSFTR_CLI2_RST_8814B BIT(3) +#define BIT_TSFTR_CLI1_RST_8814B BIT(2) +#define BIT_TSFTR_CLI0_RST_8814B BIT(1) +#define BIT_TSFTR_RST_8814B BIT(0) + +/* 2 REG_MBSSID_BCN_SPACE_8814B */ + +#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8814B 28 +#define BIT_MASK_BCN_TIMER_SEL_FWRD_8814B 0x7 +#define BIT_BCN_TIMER_SEL_FWRD_8814B(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8814B) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8814B) +#define BIT_GET_BCN_TIMER_SEL_FWRD_8814B(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8814B) & BIT_MASK_BCN_TIMER_SEL_FWRD_8814B) + + + +#define BIT_SHIFT_BCN_SPACE_CLINT0_8814B 16 +#define BIT_MASK_BCN_SPACE_CLINT0_8814B 0xfff +#define BIT_BCN_SPACE_CLINT0_8814B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8814B) << BIT_SHIFT_BCN_SPACE_CLINT0_8814B) +#define BIT_GET_BCN_SPACE_CLINT0_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8814B) & BIT_MASK_BCN_SPACE_CLINT0_8814B) + + + +#define BIT_SHIFT_BCN_SPACE0_8814B 0 +#define BIT_MASK_BCN_SPACE0_8814B 0xffff +#define BIT_BCN_SPACE0_8814B(x) (((x) & BIT_MASK_BCN_SPACE0_8814B) << BIT_SHIFT_BCN_SPACE0_8814B) +#define BIT_GET_BCN_SPACE0_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8814B) & BIT_MASK_BCN_SPACE0_8814B) + + + +/* 2 REG_DRVERLYINT_8814B */ + +#define BIT_SHIFT_DRVERLYITV_8814B 0 +#define BIT_MASK_DRVERLYITV_8814B 0xff +#define BIT_DRVERLYITV_8814B(x) (((x) & BIT_MASK_DRVERLYITV_8814B) << BIT_SHIFT_DRVERLYITV_8814B) +#define BIT_GET_DRVERLYITV_8814B(x) (((x) >> BIT_SHIFT_DRVERLYITV_8814B) & BIT_MASK_DRVERLYITV_8814B) + + + +/* 2 REG_BCNDMATIM_8814B */ + +#define BIT_SHIFT_BCNDMATIM_8814B 0 +#define BIT_MASK_BCNDMATIM_8814B 0xff +#define BIT_BCNDMATIM_8814B(x) (((x) & BIT_MASK_BCNDMATIM_8814B) << BIT_SHIFT_BCNDMATIM_8814B) +#define BIT_GET_BCNDMATIM_8814B(x) (((x) >> BIT_SHIFT_BCNDMATIM_8814B) & BIT_MASK_BCNDMATIM_8814B) + + + +/* 2 REG_ATIMWND_8814B */ + +#define BIT_SHIFT_ATIMWND0_8814B 0 +#define BIT_MASK_ATIMWND0_8814B 0xffff +#define BIT_ATIMWND0_8814B(x) (((x) & BIT_MASK_ATIMWND0_8814B) << BIT_SHIFT_ATIMWND0_8814B) +#define BIT_GET_ATIMWND0_8814B(x) (((x) >> BIT_SHIFT_ATIMWND0_8814B) & BIT_MASK_ATIMWND0_8814B) + + + +/* 2 REG_USTIME_TSF_8814B */ + +#define BIT_SHIFT_USTIME_TSF_V1_8814B 0 +#define BIT_MASK_USTIME_TSF_V1_8814B 0xff +#define BIT_USTIME_TSF_V1_8814B(x) (((x) & BIT_MASK_USTIME_TSF_V1_8814B) << BIT_SHIFT_USTIME_TSF_V1_8814B) +#define BIT_GET_USTIME_TSF_V1_8814B(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8814B) & BIT_MASK_USTIME_TSF_V1_8814B) + + + +/* 2 REG_BCN_MAX_ERR_8814B */ + +#define BIT_SHIFT_BCN_MAX_ERR_8814B 0 +#define BIT_MASK_BCN_MAX_ERR_8814B 0xff +#define BIT_BCN_MAX_ERR_8814B(x) (((x) & BIT_MASK_BCN_MAX_ERR_8814B) << BIT_SHIFT_BCN_MAX_ERR_8814B) +#define BIT_GET_BCN_MAX_ERR_8814B(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8814B) & BIT_MASK_BCN_MAX_ERR_8814B) + + + +/* 2 REG_RXTSF_OFFSET_CCK_8814B */ + +#define BIT_SHIFT_CCK_RXTSF_OFFSET_8814B 0 +#define BIT_MASK_CCK_RXTSF_OFFSET_8814B 0xff +#define BIT_CCK_RXTSF_OFFSET_8814B(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8814B) << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) +#define BIT_GET_CCK_RXTSF_OFFSET_8814B(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) & BIT_MASK_CCK_RXTSF_OFFSET_8814B) + + + +/* 2 REG_RXTSF_OFFSET_OFDM_8814B */ + +#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B 0 +#define BIT_MASK_OFDM_RXTSF_OFFSET_8814B 0xff +#define BIT_OFDM_RXTSF_OFFSET_8814B(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8814B) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) +#define BIT_GET_OFDM_RXTSF_OFFSET_8814B(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) & BIT_MASK_OFDM_RXTSF_OFFSET_8814B) + + + +/* 2 REG_TSFTR_8814B */ + +#define BIT_SHIFT_TSF_TIMER_V1_8814B 0 +#define BIT_MASK_TSF_TIMER_V1_8814B 0xffffffffL +#define BIT_TSF_TIMER_V1_8814B(x) (((x) & BIT_MASK_TSF_TIMER_V1_8814B) << BIT_SHIFT_TSF_TIMER_V1_8814B) +#define BIT_GET_TSF_TIMER_V1_8814B(x) (((x) >> BIT_SHIFT_TSF_TIMER_V1_8814B) & BIT_MASK_TSF_TIMER_V1_8814B) + + + +/* 2 REG_TSFTR_1_8814B */ + +#define BIT_SHIFT_TSF_TIMER_V2_8814B 0 +#define BIT_MASK_TSF_TIMER_V2_8814B 0xffffffffL +#define BIT_TSF_TIMER_V2_8814B(x) (((x) & BIT_MASK_TSF_TIMER_V2_8814B) << BIT_SHIFT_TSF_TIMER_V2_8814B) +#define BIT_GET_TSF_TIMER_V2_8814B(x) (((x) >> BIT_SHIFT_TSF_TIMER_V2_8814B) & BIT_MASK_TSF_TIMER_V2_8814B) + + + +/* 2 REG_FREERUN_CNT_8814B */ + +#define BIT_SHIFT_FREERUN_CNT_V1_8814B 0 +#define BIT_MASK_FREERUN_CNT_V1_8814B 0xffffffffL +#define BIT_FREERUN_CNT_V1_8814B(x) (((x) & BIT_MASK_FREERUN_CNT_V1_8814B) << BIT_SHIFT_FREERUN_CNT_V1_8814B) +#define BIT_GET_FREERUN_CNT_V1_8814B(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8814B) & BIT_MASK_FREERUN_CNT_V1_8814B) + + + +/* 2 REG_FREERUN_CNT_1_8814B */ + +#define BIT_SHIFT_FREERUN_CNT_V2_8814B 0 +#define BIT_MASK_FREERUN_CNT_V2_8814B 0xffffffffL +#define BIT_FREERUN_CNT_V2_8814B(x) (((x) & BIT_MASK_FREERUN_CNT_V2_8814B) << BIT_SHIFT_FREERUN_CNT_V2_8814B) +#define BIT_GET_FREERUN_CNT_V2_8814B(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8814B) & BIT_MASK_FREERUN_CNT_V2_8814B) + + + +/* 2 REG_ATIMWND1_V1_8814B */ + +#define BIT_SHIFT_ATIMWND1_V1_8814B 0 +#define BIT_MASK_ATIMWND1_V1_8814B 0xff +#define BIT_ATIMWND1_V1_8814B(x) (((x) & BIT_MASK_ATIMWND1_V1_8814B) << BIT_SHIFT_ATIMWND1_V1_8814B) +#define BIT_GET_ATIMWND1_V1_8814B(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8814B) & BIT_MASK_ATIMWND1_V1_8814B) + + + +/* 2 REG_TBTT_PROHIBIT_INFRA_8814B */ + +#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8814B 0 +#define BIT_MASK_TBTT_PROHIBIT_INFRA_8814B 0xff +#define BIT_TBTT_PROHIBIT_INFRA_8814B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8814B) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8814B) +#define BIT_GET_TBTT_PROHIBIT_INFRA_8814B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8814B) & BIT_MASK_TBTT_PROHIBIT_INFRA_8814B) + + + +/* 2 REG_CTWND_8814B */ + +#define BIT_SHIFT_CTWND_8814B 0 +#define BIT_MASK_CTWND_8814B 0xff +#define BIT_CTWND_8814B(x) (((x) & BIT_MASK_CTWND_8814B) << BIT_SHIFT_CTWND_8814B) +#define BIT_GET_CTWND_8814B(x) (((x) >> BIT_SHIFT_CTWND_8814B) & BIT_MASK_CTWND_8814B) + + + +/* 2 REG_BCNIVLCUNT_8814B */ + +#define BIT_SHIFT_BCNIVLCUNT_8814B 0 +#define BIT_MASK_BCNIVLCUNT_8814B 0x7f +#define BIT_BCNIVLCUNT_8814B(x) (((x) & BIT_MASK_BCNIVLCUNT_8814B) << BIT_SHIFT_BCNIVLCUNT_8814B) +#define BIT_GET_BCNIVLCUNT_8814B(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8814B) & BIT_MASK_BCNIVLCUNT_8814B) + + + +/* 2 REG_BCNDROPCTRL_8814B */ +#define BIT_BEACON_DROP_EN_8814B BIT(7) + +#define BIT_SHIFT_BEACON_DROP_IVL_8814B 0 +#define BIT_MASK_BEACON_DROP_IVL_8814B 0x7f +#define BIT_BEACON_DROP_IVL_8814B(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8814B) << BIT_SHIFT_BEACON_DROP_IVL_8814B) +#define BIT_GET_BEACON_DROP_IVL_8814B(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8814B) & BIT_MASK_BEACON_DROP_IVL_8814B) + + + +/* 2 REG_HGQ_TIMEOUT_PERIOD_8814B */ + +#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B 0 +#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B 0xff +#define BIT_HGQ_TIMEOUT_PERIOD_8814B(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8814B(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B) + + + +/* 2 REG_TXCMD_TIMEOUT_PERIOD_8814B */ + +#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B 0 +#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B 0xff +#define BIT_TXCMD_TIMEOUT_PERIOD_8814B(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8814B(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B) + + + +/* 2 REG_MISC_CTRL_8814B */ +#define BIT_DIS_TRX_CAL_BCN_8814B BIT(5) +#define BIT_DIS_TX_CAL_TBTT_8814B BIT(4) +#define BIT_EN_FREECNT_8814B BIT(3) +#define BIT_BCN_AGGRESSION_8814B BIT(2) + +#define BIT_SHIFT_DIS_SECONDARY_CCA_8814B 0 +#define BIT_MASK_DIS_SECONDARY_CCA_8814B 0x3 +#define BIT_DIS_SECONDARY_CCA_8814B(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8814B) << BIT_SHIFT_DIS_SECONDARY_CCA_8814B) +#define BIT_GET_DIS_SECONDARY_CCA_8814B(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8814B) & BIT_MASK_DIS_SECONDARY_CCA_8814B) + + + +/* 2 REG_BCN_CTRL_CLINT1_8814B */ +#define BIT_CLI1_DIS_RX_BSSID_FIT_8814B BIT(6) +#define BIT_CLI1_DIS_TSF_UDT_8814B BIT(4) +#define BIT_CLI1_EN_BCN_FUNCTION_8814B BIT(3) +#define BIT_CLI1_EN_RXBCN_RPT_8814B BIT(2) +#define BIT_CLI1_ENP2P_CTWINDOW_8814B BIT(1) +#define BIT_CLI1_ENP2P_BCNQ_AREA_8814B BIT(0) + +/* 2 REG_BCN_CTRL_CLINT2_8814B */ +#define BIT_CLI2_DIS_RX_BSSID_FIT_8814B BIT(6) +#define BIT_CLI2_DIS_TSF_UDT_8814B BIT(4) +#define BIT_CLI2_EN_BCN_FUNCTION_8814B BIT(3) +#define BIT_CLI2_EN_RXBCN_RPT_8814B BIT(2) +#define BIT_CLI2_ENP2P_CTWINDOW_8814B BIT(1) +#define BIT_CLI2_ENP2P_BCNQ_AREA_8814B BIT(0) + +/* 2 REG_BCN_CTRL_CLINT3_8814B */ +#define BIT_CLI3_DIS_RX_BSSID_FIT_8814B BIT(6) +#define BIT_CLI3_DIS_TSF_UDT_8814B BIT(4) +#define BIT_CLI3_EN_BCN_FUNCTION_8814B BIT(3) +#define BIT_CLI3_EN_RXBCN_RPT_8814B BIT(2) +#define BIT_CLI3_ENP2P_CTWINDOW_8814B BIT(1) +#define BIT_CLI3_ENP2P_BCNQ_AREA_8814B BIT(0) + +/* 2 REG_EXTEND_CTRL_8814B */ +#define BIT_EN_TSFBIT32_RST_P2P2_8814B BIT(5) +#define BIT_EN_TSFBIT32_RST_P2P1_8814B BIT(4) + +#define BIT_SHIFT_PORT_SEL_8814B 0 +#define BIT_MASK_PORT_SEL_8814B 0x7 +#define BIT_PORT_SEL_8814B(x) (((x) & BIT_MASK_PORT_SEL_8814B) << BIT_SHIFT_PORT_SEL_8814B) +#define BIT_GET_PORT_SEL_8814B(x) (((x) >> BIT_SHIFT_PORT_SEL_8814B) & BIT_MASK_PORT_SEL_8814B) + + + +/* 2 REG_P2PPS1_SPEC_STATE_8814B */ +#define BIT_P2P1_SPEC_POWER_STATE_8814B BIT(7) +#define BIT_P2P1_SPEC_CTWINDOW_ON_8814B BIT(6) +#define BIT_P2P1_SPEC_BCN_AREA_ON_8814B BIT(5) +#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4) +#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8814B BIT(3) +#define BIT_P2P1_SPEC_FORCE_DOZE1_8814B BIT(2) +#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8814B BIT(1) +#define BIT_P2P1_SPEC_FORCE_DOZE0_8814B BIT(0) + +/* 2 REG_P2PPS1_STATE_8814B */ +#define BIT_P2P1_POWER_STATE_8814B BIT(7) +#define BIT_P2P1_CTWINDOW_ON_8814B BIT(6) +#define BIT_P2P1_BEACON_AREA_ON_8814B BIT(5) +#define BIT_P2P1_CTWIN_EARLY_DISTX_8814B BIT(4) +#define BIT_P2P1_NOA1_OFF_PERIOD_8814B BIT(3) +#define BIT_P2P1_FORCE_DOZE1_8814B BIT(2) +#define BIT_P2P1_NOA0_OFF_PERIOD_8814B BIT(1) +#define BIT_P2P1_FORCE_DOZE0_8814B BIT(0) + +/* 2 REG_P2PPS2_SPEC_STATE_8814B */ +#define BIT_P2P2_SPEC_POWER_STATE_8814B BIT(7) +#define BIT_P2P2_SPEC_CTWINDOW_ON_8814B BIT(6) +#define BIT_P2P2_SPEC_BCN_AREA_ON_8814B BIT(5) +#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4) +#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8814B BIT(3) +#define BIT_P2P2_SPEC_FORCE_DOZE1_8814B BIT(2) +#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8814B BIT(1) +#define BIT_P2P2_SPEC_FORCE_DOZE0_8814B BIT(0) + +/* 2 REG_P2PPS2_STATE_8814B */ +#define BIT_P2P2_POWER_STATE_8814B BIT(7) +#define BIT_P2P2_CTWINDOW_ON_8814B BIT(6) +#define BIT_P2P2_BEACON_AREA_ON_8814B BIT(5) +#define BIT_P2P2_CTWIN_EARLY_DISTX_8814B BIT(4) +#define BIT_P2P2_NOA1_OFF_PERIOD_8814B BIT(3) +#define BIT_P2P2_FORCE_DOZE1_8814B BIT(2) +#define BIT_P2P2_NOA0_OFF_PERIOD_8814B BIT(1) +#define BIT_P2P2_FORCE_DOZE0_8814B BIT(0) + +/* 2 REG_PS_TIMER0_8814B */ + +#define BIT_SHIFT_PSTIMER0_INT_8814B 5 +#define BIT_MASK_PSTIMER0_INT_8814B 0x7ffffff +#define BIT_PSTIMER0_INT_8814B(x) (((x) & BIT_MASK_PSTIMER0_INT_8814B) << BIT_SHIFT_PSTIMER0_INT_8814B) +#define BIT_GET_PSTIMER0_INT_8814B(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8814B) & BIT_MASK_PSTIMER0_INT_8814B) + + + +/* 2 REG_PS_TIMER1_8814B */ + +#define BIT_SHIFT_PSTIMER1_INT_8814B 5 +#define BIT_MASK_PSTIMER1_INT_8814B 0x7ffffff +#define BIT_PSTIMER1_INT_8814B(x) (((x) & BIT_MASK_PSTIMER1_INT_8814B) << BIT_SHIFT_PSTIMER1_INT_8814B) +#define BIT_GET_PSTIMER1_INT_8814B(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8814B) & BIT_MASK_PSTIMER1_INT_8814B) + + + +/* 2 REG_PS_TIMER2_8814B */ + +#define BIT_SHIFT_PSTIMER2_INT_8814B 5 +#define BIT_MASK_PSTIMER2_INT_8814B 0x7ffffff +#define BIT_PSTIMER2_INT_8814B(x) (((x) & BIT_MASK_PSTIMER2_INT_8814B) << BIT_SHIFT_PSTIMER2_INT_8814B) +#define BIT_GET_PSTIMER2_INT_8814B(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8814B) & BIT_MASK_PSTIMER2_INT_8814B) + + + +/* 2 REG_TBTT_CTN_AREA_8814B */ + +#define BIT_SHIFT_TBTT_CTN_AREA_8814B 0 +#define BIT_MASK_TBTT_CTN_AREA_8814B 0xff +#define BIT_TBTT_CTN_AREA_8814B(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8814B) << BIT_SHIFT_TBTT_CTN_AREA_8814B) +#define BIT_GET_TBTT_CTN_AREA_8814B(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8814B) & BIT_MASK_TBTT_CTN_AREA_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_FORCE_BCN_IFS_8814B */ + +#define BIT_SHIFT_FORCE_BCN_IFS_8814B 0 +#define BIT_MASK_FORCE_BCN_IFS_8814B 0xff +#define BIT_FORCE_BCN_IFS_8814B(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8814B) << BIT_SHIFT_FORCE_BCN_IFS_8814B) +#define BIT_GET_FORCE_BCN_IFS_8814B(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8814B) & BIT_MASK_FORCE_BCN_IFS_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_TXOP_MIN_8814B */ + +#define BIT_SHIFT_TXOP_MIN_8814B 0 +#define BIT_MASK_TXOP_MIN_8814B 0x3fff +#define BIT_TXOP_MIN_8814B(x) (((x) & BIT_MASK_TXOP_MIN_8814B) << BIT_SHIFT_TXOP_MIN_8814B) +#define BIT_GET_TXOP_MIN_8814B(x) (((x) >> BIT_SHIFT_TXOP_MIN_8814B) & BIT_MASK_TXOP_MIN_8814B) + + + +/* 2 REG_PRE_BKF_TIME_8814B */ + +#define BIT_SHIFT_PRE_BKF_TIME_8814B 0 +#define BIT_MASK_PRE_BKF_TIME_8814B 0xff +#define BIT_PRE_BKF_TIME_8814B(x) (((x) & BIT_MASK_PRE_BKF_TIME_8814B) << BIT_SHIFT_PRE_BKF_TIME_8814B) +#define BIT_GET_PRE_BKF_TIME_8814B(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8814B) & BIT_MASK_PRE_BKF_TIME_8814B) + + + +/* 2 REG_CROSS_TXOP_CTRL_8814B */ +#define BIT_TXFAIL_BREACK_TXOP_EN_8814B BIT(3) +#define BIT_DTIM_BYPASS_8814B BIT(2) +#define BIT_RTS_NAV_TXOP_8814B BIT(1) +#define BIT_NOT_CROSS_TXOP_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_ATIMWND2_8814B */ + +#define BIT_SHIFT_ATIMWND2_8814B 0 +#define BIT_MASK_ATIMWND2_8814B 0xff +#define BIT_ATIMWND2_8814B(x) (((x) & BIT_MASK_ATIMWND2_8814B) << BIT_SHIFT_ATIMWND2_8814B) +#define BIT_GET_ATIMWND2_8814B(x) (((x) >> BIT_SHIFT_ATIMWND2_8814B) & BIT_MASK_ATIMWND2_8814B) + + + +/* 2 REG_ATIMWND3_8814B */ + +#define BIT_SHIFT_ATIMWND3_8814B 0 +#define BIT_MASK_ATIMWND3_8814B 0xff +#define BIT_ATIMWND3_8814B(x) (((x) & BIT_MASK_ATIMWND3_8814B) << BIT_SHIFT_ATIMWND3_8814B) +#define BIT_GET_ATIMWND3_8814B(x) (((x) >> BIT_SHIFT_ATIMWND3_8814B) & BIT_MASK_ATIMWND3_8814B) + + + +/* 2 REG_ATIMWND4_8814B */ + +#define BIT_SHIFT_ATIMWND4_8814B 0 +#define BIT_MASK_ATIMWND4_8814B 0xff +#define BIT_ATIMWND4_8814B(x) (((x) & BIT_MASK_ATIMWND4_8814B) << BIT_SHIFT_ATIMWND4_8814B) +#define BIT_GET_ATIMWND4_8814B(x) (((x) >> BIT_SHIFT_ATIMWND4_8814B) & BIT_MASK_ATIMWND4_8814B) + + + +/* 2 REG_ATIMWND5_8814B */ + +#define BIT_SHIFT_ATIMWND5_8814B 0 +#define BIT_MASK_ATIMWND5_8814B 0xff +#define BIT_ATIMWND5_8814B(x) (((x) & BIT_MASK_ATIMWND5_8814B) << BIT_SHIFT_ATIMWND5_8814B) +#define BIT_GET_ATIMWND5_8814B(x) (((x) >> BIT_SHIFT_ATIMWND5_8814B) & BIT_MASK_ATIMWND5_8814B) + + + +/* 2 REG_ATIMWND6_8814B */ + +#define BIT_SHIFT_ATIMWND6_8814B 0 +#define BIT_MASK_ATIMWND6_8814B 0xff +#define BIT_ATIMWND6_8814B(x) (((x) & BIT_MASK_ATIMWND6_8814B) << BIT_SHIFT_ATIMWND6_8814B) +#define BIT_GET_ATIMWND6_8814B(x) (((x) >> BIT_SHIFT_ATIMWND6_8814B) & BIT_MASK_ATIMWND6_8814B) + + + +/* 2 REG_ATIMWND7_8814B */ + +#define BIT_SHIFT_ATIMWND7_8814B 0 +#define BIT_MASK_ATIMWND7_8814B 0xff +#define BIT_ATIMWND7_8814B(x) (((x) & BIT_MASK_ATIMWND7_8814B) << BIT_SHIFT_ATIMWND7_8814B) +#define BIT_GET_ATIMWND7_8814B(x) (((x) >> BIT_SHIFT_ATIMWND7_8814B) & BIT_MASK_ATIMWND7_8814B) + + + +/* 2 REG_ATIMUGT_8814B */ + +#define BIT_SHIFT_ATIM_URGENT_8814B 0 +#define BIT_MASK_ATIM_URGENT_8814B 0xff +#define BIT_ATIM_URGENT_8814B(x) (((x) & BIT_MASK_ATIM_URGENT_8814B) << BIT_SHIFT_ATIM_URGENT_8814B) +#define BIT_GET_ATIM_URGENT_8814B(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8814B) & BIT_MASK_ATIM_URGENT_8814B) + + + +/* 2 REG_HIQ_NO_LMT_EN_8814B */ +#define BIT_HIQ_NO_LMT_EN_VAP7_8814B BIT(7) +#define BIT_HIQ_NO_LMT_EN_VAP6_8814B BIT(6) +#define BIT_HIQ_NO_LMT_EN_VAP5_8814B BIT(5) +#define BIT_HIQ_NO_LMT_EN_VAP4_8814B BIT(4) +#define BIT_HIQ_NO_LMT_EN_VAP3_8814B BIT(3) +#define BIT_HIQ_NO_LMT_EN_VAP2_8814B BIT(2) +#define BIT_HIQ_NO_LMT_EN_VAP1_8814B BIT(1) +#define BIT_HIQ_NO_LMT_EN_ROOT_8814B BIT(0) + +/* 2 REG_DTIM_COUNTER_ROOT_8814B */ + +#define BIT_SHIFT_DTIM_COUNT_ROOT_8814B 0 +#define BIT_MASK_DTIM_COUNT_ROOT_8814B 0xff +#define BIT_DTIM_COUNT_ROOT_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8814B) << BIT_SHIFT_DTIM_COUNT_ROOT_8814B) +#define BIT_GET_DTIM_COUNT_ROOT_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8814B) & BIT_MASK_DTIM_COUNT_ROOT_8814B) + + + +/* 2 REG_DTIM_COUNTER_VAP1_8814B */ + +#define BIT_SHIFT_DTIM_COUNT_VAP1_8814B 0 +#define BIT_MASK_DTIM_COUNT_VAP1_8814B 0xff +#define BIT_DTIM_COUNT_VAP1_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8814B) << BIT_SHIFT_DTIM_COUNT_VAP1_8814B) +#define BIT_GET_DTIM_COUNT_VAP1_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8814B) & BIT_MASK_DTIM_COUNT_VAP1_8814B) + + + +/* 2 REG_DTIM_COUNTER_VAP2_8814B */ + +#define BIT_SHIFT_DTIM_COUNT_VAP2_8814B 0 +#define BIT_MASK_DTIM_COUNT_VAP2_8814B 0xff +#define BIT_DTIM_COUNT_VAP2_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8814B) << BIT_SHIFT_DTIM_COUNT_VAP2_8814B) +#define BIT_GET_DTIM_COUNT_VAP2_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8814B) & BIT_MASK_DTIM_COUNT_VAP2_8814B) + + + +/* 2 REG_DTIM_COUNTER_VAP3_8814B */ + +#define BIT_SHIFT_DTIM_COUNT_VAP3_8814B 0 +#define BIT_MASK_DTIM_COUNT_VAP3_8814B 0xff +#define BIT_DTIM_COUNT_VAP3_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8814B) << BIT_SHIFT_DTIM_COUNT_VAP3_8814B) +#define BIT_GET_DTIM_COUNT_VAP3_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8814B) & BIT_MASK_DTIM_COUNT_VAP3_8814B) + + + +/* 2 REG_DTIM_COUNTER_VAP4_8814B */ + +#define BIT_SHIFT_DTIM_COUNT_VAP4_8814B 0 +#define BIT_MASK_DTIM_COUNT_VAP4_8814B 0xff +#define BIT_DTIM_COUNT_VAP4_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8814B) << BIT_SHIFT_DTIM_COUNT_VAP4_8814B) +#define BIT_GET_DTIM_COUNT_VAP4_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8814B) & BIT_MASK_DTIM_COUNT_VAP4_8814B) + + + +/* 2 REG_DTIM_COUNTER_VAP5_8814B */ + +#define BIT_SHIFT_DTIM_COUNT_VAP5_8814B 0 +#define BIT_MASK_DTIM_COUNT_VAP5_8814B 0xff +#define BIT_DTIM_COUNT_VAP5_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8814B) << BIT_SHIFT_DTIM_COUNT_VAP5_8814B) +#define BIT_GET_DTIM_COUNT_VAP5_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8814B) & BIT_MASK_DTIM_COUNT_VAP5_8814B) + + + +/* 2 REG_DTIM_COUNTER_VAP6_8814B */ + +#define BIT_SHIFT_DTIM_COUNT_VAP6_8814B 0 +#define BIT_MASK_DTIM_COUNT_VAP6_8814B 0xff +#define BIT_DTIM_COUNT_VAP6_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8814B) << BIT_SHIFT_DTIM_COUNT_VAP6_8814B) +#define BIT_GET_DTIM_COUNT_VAP6_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8814B) & BIT_MASK_DTIM_COUNT_VAP6_8814B) + + + +/* 2 REG_DTIM_COUNTER_VAP7_8814B */ + +#define BIT_SHIFT_DTIM_COUNT_VAP7_8814B 0 +#define BIT_MASK_DTIM_COUNT_VAP7_8814B 0xff +#define BIT_DTIM_COUNT_VAP7_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8814B) << BIT_SHIFT_DTIM_COUNT_VAP7_8814B) +#define BIT_GET_DTIM_COUNT_VAP7_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8814B) & BIT_MASK_DTIM_COUNT_VAP7_8814B) + + + +/* 2 REG_DIS_ATIM_8814B */ +#define BIT_DIS_ATIM_VAP7_8814B BIT(7) +#define BIT_DIS_ATIM_VAP6_8814B BIT(6) +#define BIT_DIS_ATIM_VAP5_8814B BIT(5) +#define BIT_DIS_ATIM_VAP4_8814B BIT(4) +#define BIT_DIS_ATIM_VAP3_8814B BIT(3) +#define BIT_DIS_ATIM_VAP2_8814B BIT(2) +#define BIT_DIS_ATIM_VAP1_8814B BIT(1) +#define BIT_DIS_ATIM_ROOT_8814B BIT(0) + +/* 2 REG_EARLY_128US_8814B */ + +#define BIT_SHIFT_TSFT_SEL_TIMER1_8814B 3 +#define BIT_MASK_TSFT_SEL_TIMER1_8814B 0x7 +#define BIT_TSFT_SEL_TIMER1_8814B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8814B) << BIT_SHIFT_TSFT_SEL_TIMER1_8814B) +#define BIT_GET_TSFT_SEL_TIMER1_8814B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8814B) & BIT_MASK_TSFT_SEL_TIMER1_8814B) + + + +#define BIT_SHIFT_EARLY_128US_8814B 0 +#define BIT_MASK_EARLY_128US_8814B 0x7 +#define BIT_EARLY_128US_8814B(x) (((x) & BIT_MASK_EARLY_128US_8814B) << BIT_SHIFT_EARLY_128US_8814B) +#define BIT_GET_EARLY_128US_8814B(x) (((x) >> BIT_SHIFT_EARLY_128US_8814B) & BIT_MASK_EARLY_128US_8814B) + + + +/* 2 REG_P2PPS1_CTRL_8814B */ +#define BIT_P2P1_CTW_ALLSTASLEEP_8814B BIT(7) +#define BIT_P2P1_OFF_DISTX_EN_8814B BIT(6) +#define BIT_P2P1_PWR_MGT_EN_8814B BIT(5) +#define BIT_P2P1_NOA1_EN_8814B BIT(2) +#define BIT_P2P1_NOA0_EN_8814B BIT(1) + +/* 2 REG_P2PPS2_CTRL_8814B */ +#define BIT_P2P2_CTW_ALLSTASLEEP_8814B BIT(7) +#define BIT_P2P2_OFF_DISTX_EN_8814B BIT(6) +#define BIT_P2P2_PWR_MGT_EN_8814B BIT(5) +#define BIT_P2P2_NOA1_EN_8814B BIT(2) +#define BIT_P2P2_NOA0_EN_8814B BIT(1) + +/* 2 REG_TIMER0_SRC_SEL_8814B */ + +#define BIT_SHIFT_SYNC_CLI_SEL_8814B 4 +#define BIT_MASK_SYNC_CLI_SEL_8814B 0x7 +#define BIT_SYNC_CLI_SEL_8814B(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8814B) << BIT_SHIFT_SYNC_CLI_SEL_8814B) +#define BIT_GET_SYNC_CLI_SEL_8814B(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8814B) & BIT_MASK_SYNC_CLI_SEL_8814B) + + + +#define BIT_SHIFT_TSFT_SEL_TIMER0_8814B 0 +#define BIT_MASK_TSFT_SEL_TIMER0_8814B 0x7 +#define BIT_TSFT_SEL_TIMER0_8814B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8814B) << BIT_SHIFT_TSFT_SEL_TIMER0_8814B) +#define BIT_GET_TSFT_SEL_TIMER0_8814B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8814B) & BIT_MASK_TSFT_SEL_TIMER0_8814B) + + + +/* 2 REG_NOA_UNIT_SEL_8814B */ + +#define BIT_SHIFT_NOA_UNIT2_SEL_8814B 8 +#define BIT_MASK_NOA_UNIT2_SEL_8814B 0x7 +#define BIT_NOA_UNIT2_SEL_8814B(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8814B) << BIT_SHIFT_NOA_UNIT2_SEL_8814B) +#define BIT_GET_NOA_UNIT2_SEL_8814B(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8814B) & BIT_MASK_NOA_UNIT2_SEL_8814B) + + + +#define BIT_SHIFT_NOA_UNIT1_SEL_8814B 4 +#define BIT_MASK_NOA_UNIT1_SEL_8814B 0x7 +#define BIT_NOA_UNIT1_SEL_8814B(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8814B) << BIT_SHIFT_NOA_UNIT1_SEL_8814B) +#define BIT_GET_NOA_UNIT1_SEL_8814B(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8814B) & BIT_MASK_NOA_UNIT1_SEL_8814B) + + + +#define BIT_SHIFT_NOA_UNIT0_SEL_8814B 0 +#define BIT_MASK_NOA_UNIT0_SEL_8814B 0x7 +#define BIT_NOA_UNIT0_SEL_8814B(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8814B) << BIT_SHIFT_NOA_UNIT0_SEL_8814B) +#define BIT_GET_NOA_UNIT0_SEL_8814B(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8814B) & BIT_MASK_NOA_UNIT0_SEL_8814B) + + + +/* 2 REG_P2POFF_DIS_TXTIME_8814B */ + +#define BIT_SHIFT_P2POFF_DIS_TXTIME_8814B 0 +#define BIT_MASK_P2POFF_DIS_TXTIME_8814B 0xff +#define BIT_P2POFF_DIS_TXTIME_8814B(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8814B) << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) +#define BIT_GET_P2POFF_DIS_TXTIME_8814B(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) & BIT_MASK_P2POFF_DIS_TXTIME_8814B) + + + +/* 2 REG_MBSSID_BCN_SPACE2_8814B */ + +#define BIT_SHIFT_BCN_SPACE_CLINT2_8814B 16 +#define BIT_MASK_BCN_SPACE_CLINT2_8814B 0xfff +#define BIT_BCN_SPACE_CLINT2_8814B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8814B) << BIT_SHIFT_BCN_SPACE_CLINT2_8814B) +#define BIT_GET_BCN_SPACE_CLINT2_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8814B) & BIT_MASK_BCN_SPACE_CLINT2_8814B) + + + +#define BIT_SHIFT_BCN_SPACE_CLINT1_8814B 0 +#define BIT_MASK_BCN_SPACE_CLINT1_8814B 0xfff +#define BIT_BCN_SPACE_CLINT1_8814B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8814B) << BIT_SHIFT_BCN_SPACE_CLINT1_8814B) +#define BIT_GET_BCN_SPACE_CLINT1_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8814B) & BIT_MASK_BCN_SPACE_CLINT1_8814B) + + + +/* 2 REG_MBSSID_BCN_SPACE3_8814B */ + +#define BIT_SHIFT_SUB_BCN_SPACE_8814B 16 +#define BIT_MASK_SUB_BCN_SPACE_8814B 0xff +#define BIT_SUB_BCN_SPACE_8814B(x) (((x) & BIT_MASK_SUB_BCN_SPACE_8814B) << BIT_SHIFT_SUB_BCN_SPACE_8814B) +#define BIT_GET_SUB_BCN_SPACE_8814B(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8814B) & BIT_MASK_SUB_BCN_SPACE_8814B) + + + +#define BIT_SHIFT_BCN_SPACE_CLINT3_8814B 0 +#define BIT_MASK_BCN_SPACE_CLINT3_8814B 0xfff +#define BIT_BCN_SPACE_CLINT3_8814B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8814B) << BIT_SHIFT_BCN_SPACE_CLINT3_8814B) +#define BIT_GET_BCN_SPACE_CLINT3_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8814B) & BIT_MASK_BCN_SPACE_CLINT3_8814B) + + + +/* 2 REG_ACMHWCTRL_8814B */ +#define BIT_BEQ_ACM_STATUS_8814B BIT(7) +#define BIT_VIQ_ACM_STATUS_8814B BIT(6) +#define BIT_VOQ_ACM_STATUS_8814B BIT(5) +#define BIT_BEQ_ACM_EN_8814B BIT(3) +#define BIT_VIQ_ACM_EN_8814B BIT(2) +#define BIT_VOQ_ACM_EN_8814B BIT(1) +#define BIT_ACMHWEN_8814B BIT(0) + +/* 2 REG_ACMRSTCTRL_8814B */ +#define BIT_BE_ACM_RESET_USED_TIME_8814B BIT(2) +#define BIT_VI_ACM_RESET_USED_TIME_8814B BIT(1) +#define BIT_VO_ACM_RESET_USED_TIME_8814B BIT(0) + +/* 2 REG_ACMAVG_8814B */ + +#define BIT_SHIFT_AVGPERIOD_8814B 0 +#define BIT_MASK_AVGPERIOD_8814B 0xffff +#define BIT_AVGPERIOD_8814B(x) (((x) & BIT_MASK_AVGPERIOD_8814B) << BIT_SHIFT_AVGPERIOD_8814B) +#define BIT_GET_AVGPERIOD_8814B(x) (((x) >> BIT_SHIFT_AVGPERIOD_8814B) & BIT_MASK_AVGPERIOD_8814B) + + + +/* 2 REG_VO_ADMTIME_8814B */ + +#define BIT_SHIFT_VO_ADMITTED_TIME_8814B 0 +#define BIT_MASK_VO_ADMITTED_TIME_8814B 0xffff +#define BIT_VO_ADMITTED_TIME_8814B(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8814B) << BIT_SHIFT_VO_ADMITTED_TIME_8814B) +#define BIT_GET_VO_ADMITTED_TIME_8814B(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8814B) & BIT_MASK_VO_ADMITTED_TIME_8814B) + + + +/* 2 REG_VI_ADMTIME_8814B */ + +#define BIT_SHIFT_VI_ADMITTED_TIME_8814B 0 +#define BIT_MASK_VI_ADMITTED_TIME_8814B 0xffff +#define BIT_VI_ADMITTED_TIME_8814B(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8814B) << BIT_SHIFT_VI_ADMITTED_TIME_8814B) +#define BIT_GET_VI_ADMITTED_TIME_8814B(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8814B) & BIT_MASK_VI_ADMITTED_TIME_8814B) + + + +/* 2 REG_BE_ADMTIME_8814B */ + +#define BIT_SHIFT_BE_ADMITTED_TIME_8814B 0 +#define BIT_MASK_BE_ADMITTED_TIME_8814B 0xffff +#define BIT_BE_ADMITTED_TIME_8814B(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8814B) << BIT_SHIFT_BE_ADMITTED_TIME_8814B) +#define BIT_GET_BE_ADMITTED_TIME_8814B(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8814B) & BIT_MASK_BE_ADMITTED_TIME_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_EDCA_RANDOM_GEN_8814B */ + +#define BIT_SHIFT_RANDOM_GEN_8814B 0 +#define BIT_MASK_RANDOM_GEN_8814B 0xffffff +#define BIT_RANDOM_GEN_8814B(x) (((x) & BIT_MASK_RANDOM_GEN_8814B) << BIT_SHIFT_RANDOM_GEN_8814B) +#define BIT_GET_RANDOM_GEN_8814B(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8814B) & BIT_MASK_RANDOM_GEN_8814B) + + + +/* 2 REG_TXCMD_NOA_SEL_8814B */ + +#define BIT_SHIFT_NOA_SEL_8814B 4 +#define BIT_MASK_NOA_SEL_8814B 0x7 +#define BIT_NOA_SEL_8814B(x) (((x) & BIT_MASK_NOA_SEL_8814B) << BIT_SHIFT_NOA_SEL_8814B) +#define BIT_GET_NOA_SEL_8814B(x) (((x) >> BIT_SHIFT_NOA_SEL_8814B) & BIT_MASK_NOA_SEL_8814B) + + + +#define BIT_SHIFT_TXCMD_SEG_SEL_8814B 0 +#define BIT_MASK_TXCMD_SEG_SEL_8814B 0xf +#define BIT_TXCMD_SEG_SEL_8814B(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8814B) << BIT_SHIFT_TXCMD_SEG_SEL_8814B) +#define BIT_GET_TXCMD_SEG_SEL_8814B(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8814B) & BIT_MASK_TXCMD_SEG_SEL_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOA_PARAM_8814B */ + +#define BIT_SHIFT_NOA_DURATION_V1_8814B 0 +#define BIT_MASK_NOA_DURATION_V1_8814B 0xffffffffL +#define BIT_NOA_DURATION_V1_8814B(x) (((x) & BIT_MASK_NOA_DURATION_V1_8814B) << BIT_SHIFT_NOA_DURATION_V1_8814B) +#define BIT_GET_NOA_DURATION_V1_8814B(x) (((x) >> BIT_SHIFT_NOA_DURATION_V1_8814B) & BIT_MASK_NOA_DURATION_V1_8814B) + + + +/* 2 REG_NOA_PARAM_1_8814B */ + +#define BIT_SHIFT_NOA_INTERVAL_V1_8814B 0 +#define BIT_MASK_NOA_INTERVAL_V1_8814B 0xffffffffL +#define BIT_NOA_INTERVAL_V1_8814B(x) (((x) & BIT_MASK_NOA_INTERVAL_V1_8814B) << BIT_SHIFT_NOA_INTERVAL_V1_8814B) +#define BIT_GET_NOA_INTERVAL_V1_8814B(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8814B) & BIT_MASK_NOA_INTERVAL_V1_8814B) + + + +/* 2 REG_NOA_PARAM_2_8814B */ + +#define BIT_SHIFT_NOA_START_TIME_V1_8814B 0 +#define BIT_MASK_NOA_START_TIME_V1_8814B 0xffffffffL +#define BIT_NOA_START_TIME_V1_8814B(x) (((x) & BIT_MASK_NOA_START_TIME_V1_8814B) << BIT_SHIFT_NOA_START_TIME_V1_8814B) +#define BIT_GET_NOA_START_TIME_V1_8814B(x) (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8814B) & BIT_MASK_NOA_START_TIME_V1_8814B) + + + +/* 2 REG_NOA_PARAM_3_8814B */ + +#define BIT_SHIFT_NOA_COUNT_V1_8814B 0 +#define BIT_MASK_NOA_COUNT_V1_8814B 0xffffffffL +#define BIT_NOA_COUNT_V1_8814B(x) (((x) & BIT_MASK_NOA_COUNT_V1_8814B) << BIT_SHIFT_NOA_COUNT_V1_8814B) +#define BIT_GET_NOA_COUNT_V1_8814B(x) (((x) >> BIT_SHIFT_NOA_COUNT_V1_8814B) & BIT_MASK_NOA_COUNT_V1_8814B) + + + +/* 2 REG_P2P_RST_8814B */ +#define BIT_P2P2_PWR_RST1_8814B BIT(5) +#define BIT_P2P2_PWR_RST0_8814B BIT(4) +#define BIT_P2P1_PWR_RST1_8814B BIT(3) +#define BIT_P2P1_PWR_RST0_8814B BIT(2) +#define BIT_P2P_PWR_RST1_V1_8814B BIT(1) +#define BIT_P2P_PWR_RST0_V1_8814B BIT(0) + +/* 2 REG_SCHEDULER_RST_8814B */ +#define BIT_SYNC_CLI_8814B BIT(1) +#define BIT_SCHEDULER_RST_V1_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_SCH_TXCMD_8814B */ + +#define BIT_SHIFT_SCH_TXCMD_8814B 0 +#define BIT_MASK_SCH_TXCMD_8814B 0xffffffffL +#define BIT_SCH_TXCMD_8814B(x) (((x) & BIT_MASK_SCH_TXCMD_8814B) << BIT_SHIFT_SCH_TXCMD_8814B) +#define BIT_GET_SCH_TXCMD_8814B(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8814B) & BIT_MASK_SCH_TXCMD_8814B) + + + +/* 2 REG_PAGE5_DUMMY_8814B */ + +/* 2 REG_CPUMGQ_TX_TIMER_8814B */ + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B 0xffffffffL +#define BIT_CPUMGQ_TX_TIMER_V1_8814B(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8814B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B) + + + +/* 2 REG_PS_TIMER_A_8814B */ + +#define BIT_SHIFT_PS_TIMER_A_V1_8814B 0 +#define BIT_MASK_PS_TIMER_A_V1_8814B 0xffffffffL +#define BIT_PS_TIMER_A_V1_8814B(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8814B) << BIT_SHIFT_PS_TIMER_A_V1_8814B) +#define BIT_GET_PS_TIMER_A_V1_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8814B) & BIT_MASK_PS_TIMER_A_V1_8814B) + + + +/* 2 REG_PS_TIMER_B_8814B */ + +#define BIT_SHIFT_PS_TIMER_B_V1_8814B 0 +#define BIT_MASK_PS_TIMER_B_V1_8814B 0xffffffffL +#define BIT_PS_TIMER_B_V1_8814B(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8814B) << BIT_SHIFT_PS_TIMER_B_V1_8814B) +#define BIT_GET_PS_TIMER_B_V1_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8814B) & BIT_MASK_PS_TIMER_B_V1_8814B) + + + +/* 2 REG_PS_TIMER_C_8814B */ + +#define BIT_SHIFT_PS_TIMER_C_V1_8814B 0 +#define BIT_MASK_PS_TIMER_C_V1_8814B 0xffffffffL +#define BIT_PS_TIMER_C_V1_8814B(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8814B) << BIT_SHIFT_PS_TIMER_C_V1_8814B) +#define BIT_GET_PS_TIMER_C_V1_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8814B) & BIT_MASK_PS_TIMER_C_V1_8814B) + + + +/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8814B */ +#define BIT_CPUMGQ_TIMER_EN_8814B BIT(31) +#define BIT_CPUMGQ_TX_EN_8814B BIT(28) + +#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8814B 24 +#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8814B 0x7 +#define BIT_CPUMGQ_TIMER_TSF_SEL_8814B(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8814B) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8814B) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8814B(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8814B) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8814B) + + +#define BIT_PS_TIMER_C_EN_8814B BIT(23) + +#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8814B 16 +#define BIT_MASK_PS_TIMER_C_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_C_TSF_SEL_8814B(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8814B) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8814B) +#define BIT_GET_PS_TIMER_C_TSF_SEL_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8814B) & BIT_MASK_PS_TIMER_C_TSF_SEL_8814B) + + +#define BIT_PS_TIMER_B_EN_8814B BIT(15) + +#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8814B 8 +#define BIT_MASK_PS_TIMER_B_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_B_TSF_SEL_8814B(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8814B) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8814B) +#define BIT_GET_PS_TIMER_B_TSF_SEL_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8814B) & BIT_MASK_PS_TIMER_B_TSF_SEL_8814B) + + +#define BIT_PS_TIMER_A_EN_8814B BIT(7) + +#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8814B 0 +#define BIT_MASK_PS_TIMER_A_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_A_TSF_SEL_8814B(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8814B) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8814B) +#define BIT_GET_PS_TIMER_A_TSF_SEL_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8814B) & BIT_MASK_PS_TIMER_A_TSF_SEL_8814B) + + + +/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8814B */ + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8814B 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8814B 0xff +#define BIT_CPUMGQ_TX_TIMER_EARLY_8814B(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8814B) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8814B) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8814B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8814B) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8814B) + + + +/* 2 REG_PS_TIMER_A_EARLY_8814B */ + +#define BIT_SHIFT_PS_TIMER_A_EARLY_8814B 0 +#define BIT_MASK_PS_TIMER_A_EARLY_8814B 0xff +#define BIT_PS_TIMER_A_EARLY_8814B(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8814B) << BIT_SHIFT_PS_TIMER_A_EARLY_8814B) +#define BIT_GET_PS_TIMER_A_EARLY_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8814B) & BIT_MASK_PS_TIMER_A_EARLY_8814B) + + + +/* 2 REG_PS_TIMER_B_EARLY_8814B */ + +#define BIT_SHIFT_PS_TIMER_B_EARLY_8814B 0 +#define BIT_MASK_PS_TIMER_B_EARLY_8814B 0xff +#define BIT_PS_TIMER_B_EARLY_8814B(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8814B) << BIT_SHIFT_PS_TIMER_B_EARLY_8814B) +#define BIT_GET_PS_TIMER_B_EARLY_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8814B) & BIT_MASK_PS_TIMER_B_EARLY_8814B) + + + +/* 2 REG_PS_TIMER_C_EARLY_8814B */ + +#define BIT_SHIFT_PS_TIMER_C_EARLY_8814B 0 +#define BIT_MASK_PS_TIMER_C_EARLY_8814B 0xff +#define BIT_PS_TIMER_C_EARLY_8814B(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8814B) << BIT_SHIFT_PS_TIMER_C_EARLY_8814B) +#define BIT_GET_PS_TIMER_C_EARLY_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8814B) & BIT_MASK_PS_TIMER_C_EARLY_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_RSVD_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_BWOPMODE_8814B (BW OPERATION MODE REGISTER) */ + +/* 2 REG_WMAC_FWPKT_CR_8814B */ +#define BIT_FWEN_8814B BIT(7) +#define BIT_PHYSTS_PKT_CTRL_8814B BIT(6) +#define BIT_APPHDR_MIDSRCH_FAIL_8814B BIT(4) +#define BIT_FWPARSING_EN_8814B BIT(3) + +#define BIT_SHIFT_APPEND_MHDR_LEN_8814B 0 +#define BIT_MASK_APPEND_MHDR_LEN_8814B 0x7 +#define BIT_APPEND_MHDR_LEN_8814B(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8814B) << BIT_SHIFT_APPEND_MHDR_LEN_8814B) +#define BIT_GET_APPEND_MHDR_LEN_8814B(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8814B) & BIT_MASK_APPEND_MHDR_LEN_8814B) + + + +/* 2 REG_FW_STS_FILTER_8814B */ +#define BIT_DATA_FW_STS_FILTER_8814B BIT(2) +#define BIT_CTRL_FW_STS_FILTER_8814B BIT(1) +#define BIT_MGNT_FW_STS_FILTER_8814B BIT(0) + +/* 2 REG_WMAC_CR_8814B (WMAC CR AND APSD CONTROL REGISTER) */ +#define BIT_IC_MACPHY_M_8814B BIT(0) + +/* 2 REG_TCR_8814B (TRANSMISSION CONFIGURATION REGISTER) */ +#define BIT_WMAC_EN_RTS_ADDR_8814B BIT(31) +#define BIT_WMAC_DISABLE_CCK_8814B BIT(30) +#define BIT_WMAC_RAW_LEN_8814B BIT(29) +#define BIT_WMAC_NOTX_IN_RXNDP_8814B BIT(28) +#define BIT_WMAC_EN_EOF_8814B BIT(27) +#define BIT_WMAC_BF_SEL_8814B BIT(26) +#define BIT_WMAC_ANTMODE_SEL_8814B BIT(25) +#define BIT_WMAC_TCRPWRMGT_HWCTL_8814B BIT(24) +#define BIT_WMAC_SMOOTH_VAL_8814B BIT(23) +#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8814B BIT(20) +#define BIT_WMAC_TCR_EN_20MST_8814B BIT(19) +#define BIT_WMAC_DIS_SIGTA_8814B BIT(18) +#define BIT_WMAC_DIS_A2B0_8814B BIT(17) +#define BIT_WMAC_MSK_SIGBCRC_8814B BIT(16) +#define BIT_WMAC_TCR_ERRSTEN_3_8814B BIT(15) +#define BIT_WMAC_TCR_ERRSTEN_2_8814B BIT(14) +#define BIT_WMAC_TCR_ERRSTEN_1_8814B BIT(13) +#define BIT_WMAC_TCR_ERRSTEN_0_8814B BIT(12) +#define BIT_WMAC_TCR_TXSK_PERPKT_8814B BIT(11) +#define BIT_ICV_8814B BIT(10) +#define BIT_CFEND_FORMAT_8814B BIT(9) +#define BIT_CRC_8814B BIT(8) +#define BIT_PWRBIT_OW_EN_8814B BIT(7) +#define BIT_PWR_ST_8814B BIT(6) +#define BIT_WMAC_TCR_UPD_TIMIE_8814B BIT(5) +#define BIT_WMAC_TCR_UPD_HGQMD_8814B BIT(4) +#define BIT_VHTSIGA1_TXPS_8814B BIT(3) +#define BIT_PAD_SEL_8814B BIT(2) +#define BIT_DIS_GCLK_8814B BIT(1) + +/* 2 REG_RCR_8814B (RECEIVE CONFIGURATION REGISTER) */ +#define BIT_APP_FCS_8814B BIT(31) +#define BIT_APP_MIC_8814B BIT(30) +#define BIT_APP_ICV_8814B BIT(29) +#define BIT_APP_PHYSTS_8814B BIT(28) +#define BIT_APP_BASSN_8814B BIT(27) +#define BIT_VHT_DACK_8814B BIT(26) +#define BIT_TCPOFLD_EN_8814B BIT(25) +#define BIT_ENMBID_8814B BIT(24) +#define BIT_LSIGEN_8814B BIT(23) +#define BIT_MFBEN_8814B BIT(22) +#define BIT_DISCHKPPDLLEN_8814B BIT(21) +#define BIT_PKTCTL_DLEN_8814B BIT(20) +#define BIT_TIM_PARSER_EN_8814B BIT(18) +#define BIT_BC_MD_EN_8814B BIT(17) +#define BIT_UC_MD_EN_8814B BIT(16) +#define BIT_RXSK_PERPKT_8814B BIT(15) +#define BIT_HTC_LOC_CTRL_8814B BIT(14) +#define BIT_RPFM_CAM_ENABLE_8814B BIT(12) +#define BIT_TA_BCN_8814B BIT(11) +#define BIT_DISDECMYPKT_8814B BIT(10) +#define BIT_AICV_8814B BIT(9) +#define BIT_ACRC32_8814B BIT(8) +#define BIT_CBSSID_BCN_8814B BIT(7) +#define BIT_CBSSID_DATA_8814B BIT(6) +#define BIT_APWRMGT_8814B BIT(5) +#define BIT_ADD3_8814B BIT(4) +#define BIT_AB_8814B BIT(3) +#define BIT_AM_8814B BIT(2) +#define BIT_APM_8814B BIT(1) +#define BIT_AAP_8814B BIT(0) + +/* 2 REG_RX_DRVINFO_SZ_8814B (RX DRIVER INFO SIZE REGISTER) */ +#define BIT_PHYSTS_PER_PKT_MODE_8814B BIT(7) + +#define BIT_SHIFT_DRVINFO_SZ_V1_8814B 0 +#define BIT_MASK_DRVINFO_SZ_V1_8814B 0xf +#define BIT_DRVINFO_SZ_V1_8814B(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8814B) << BIT_SHIFT_DRVINFO_SZ_V1_8814B) +#define BIT_GET_DRVINFO_SZ_V1_8814B(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8814B) & BIT_MASK_DRVINFO_SZ_V1_8814B) + + + +/* 2 REG_RX_DLK_TIME_8814B (RX DEADLOCK TIME REGISTER) */ + +#define BIT_SHIFT_RX_DLK_TIME_8814B 0 +#define BIT_MASK_RX_DLK_TIME_8814B 0xff +#define BIT_RX_DLK_TIME_8814B(x) (((x) & BIT_MASK_RX_DLK_TIME_8814B) << BIT_SHIFT_RX_DLK_TIME_8814B) +#define BIT_GET_RX_DLK_TIME_8814B(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8814B) & BIT_MASK_RX_DLK_TIME_8814B) + + + +/* 2 REG_RX_PKT_LIMIT_8814B (RX PACKET LENGTH LIMIT REGISTER) */ + +#define BIT_SHIFT_RXPKTLMT_8814B 0 +#define BIT_MASK_RXPKTLMT_8814B 0x3f +#define BIT_RXPKTLMT_8814B(x) (((x) & BIT_MASK_RXPKTLMT_8814B) << BIT_SHIFT_RXPKTLMT_8814B) +#define BIT_GET_RXPKTLMT_8814B(x) (((x) >> BIT_SHIFT_RXPKTLMT_8814B) & BIT_MASK_RXPKTLMT_8814B) + + + +/* 2 REG_MACID_8814B (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_8814B 0 +#define BIT_MASK_MACID_8814B 0xffffffffffffL +#define BIT_MACID_8814B(x) (((x) & BIT_MASK_MACID_8814B) << BIT_SHIFT_MACID_8814B) +#define BIT_GET_MACID_8814B(x) (((x) >> BIT_SHIFT_MACID_8814B) & BIT_MASK_MACID_8814B) + + + +/* 2 REG_BSSID_8814B (BSSID REGISTER) */ + +#define BIT_SHIFT_BSSID_8814B 0 +#define BIT_MASK_BSSID_8814B 0xffffffffffffL +#define BIT_BSSID_8814B(x) (((x) & BIT_MASK_BSSID_8814B) << BIT_SHIFT_BSSID_8814B) +#define BIT_GET_BSSID_8814B(x) (((x) >> BIT_SHIFT_BSSID_8814B) & BIT_MASK_BSSID_8814B) + + + +/* 2 REG_MAR_8814B (MULTICAST ADDRESS REGISTER) */ + +#define BIT_SHIFT_MAR_8814B 0 +#define BIT_MASK_MAR_8814B 0xffffffffffffffffL +#define BIT_MAR_8814B(x) (((x) & BIT_MASK_MAR_8814B) << BIT_SHIFT_MAR_8814B) +#define BIT_GET_MAR_8814B(x) (((x) >> BIT_SHIFT_MAR_8814B) & BIT_MASK_MAR_8814B) + + + +/* 2 REG_MBIDCAMCFG_1_8814B (MBSSID CAM CONFIGURATION REGISTER) */ + +#define BIT_SHIFT_MBIDCAM_RWDATA_L_8814B 0 +#define BIT_MASK_MBIDCAM_RWDATA_L_8814B 0xffffffffL +#define BIT_MBIDCAM_RWDATA_L_8814B(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8814B) << BIT_SHIFT_MBIDCAM_RWDATA_L_8814B) +#define BIT_GET_MBIDCAM_RWDATA_L_8814B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8814B) & BIT_MASK_MBIDCAM_RWDATA_L_8814B) + + + +/* 2 REG_MBIDCAMCFG_2_8814B (MBSSID CAM CONFIGURATION REGISTER) */ +#define BIT_MBIDCAM_POLL_8814B BIT(31) +#define BIT_MBIDCAM_WT_EN_8814B BIT(30) + +#define BIT_SHIFT_MBIDCAM_ADDR_8814B 24 +#define BIT_MASK_MBIDCAM_ADDR_8814B 0x1f +#define BIT_MBIDCAM_ADDR_8814B(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8814B) << BIT_SHIFT_MBIDCAM_ADDR_8814B) +#define BIT_GET_MBIDCAM_ADDR_8814B(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8814B) & BIT_MASK_MBIDCAM_ADDR_8814B) + + +#define BIT_MBIDCAM_VALID_8814B BIT(23) +#define BIT_LSIC_TXOP_EN_8814B BIT(17) +#define BIT_CTS_EN_8814B BIT(16) + +#define BIT_SHIFT_MBIDCAM_RWDATA_H_8814B 0 +#define BIT_MASK_MBIDCAM_RWDATA_H_8814B 0xffff +#define BIT_MBIDCAM_RWDATA_H_8814B(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8814B) << BIT_SHIFT_MBIDCAM_RWDATA_H_8814B) +#define BIT_GET_MBIDCAM_RWDATA_H_8814B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8814B) & BIT_MASK_MBIDCAM_RWDATA_H_8814B) + + + +/* 2 REG_ZLD_NUM_8814B */ + +#define BIT_SHIFT_ZLD_NUM_8814B 0 +#define BIT_MASK_ZLD_NUM_8814B 0xff +#define BIT_ZLD_NUM_8814B(x) (((x) & BIT_MASK_ZLD_NUM_8814B) << BIT_SHIFT_ZLD_NUM_8814B) +#define BIT_GET_ZLD_NUM_8814B(x) (((x) >> BIT_SHIFT_ZLD_NUM_8814B) & BIT_MASK_ZLD_NUM_8814B) + + + +/* 2 REG_UDF_THSD_8814B */ + +#define BIT_SHIFT_UDF_THSD_8814B 0 +#define BIT_MASK_UDF_THSD_8814B 0xff +#define BIT_UDF_THSD_8814B(x) (((x) & BIT_MASK_UDF_THSD_8814B) << BIT_SHIFT_UDF_THSD_8814B) +#define BIT_GET_UDF_THSD_8814B(x) (((x) >> BIT_SHIFT_UDF_THSD_8814B) & BIT_MASK_UDF_THSD_8814B) + + + +/* 2 REG_WMAC_TCR_TSFT_OFS_8814B */ + +#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B 0 +#define BIT_MASK_WMAC_TCR_TSFT_OFS_8814B 0xffff +#define BIT_WMAC_TCR_TSFT_OFS_8814B(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8814B) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8814B(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) & BIT_MASK_WMAC_TCR_TSFT_OFS_8814B) + + + +/* 2 REG_MCU_TEST_2_V1_8814B */ + +#define BIT_SHIFT_MCU_RSVD_2_V1_8814B 0 +#define BIT_MASK_MCU_RSVD_2_V1_8814B 0xffff +#define BIT_MCU_RSVD_2_V1_8814B(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8814B) << BIT_SHIFT_MCU_RSVD_2_V1_8814B) +#define BIT_GET_MCU_RSVD_2_V1_8814B(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8814B) & BIT_MASK_MCU_RSVD_2_V1_8814B) + + + +/* 2 REG_WMAC_TXTIMEOUT_8814B */ + +#define BIT_SHIFT_WMAC_TXTIMEOUT_8814B 0 +#define BIT_MASK_WMAC_TXTIMEOUT_8814B 0xff +#define BIT_WMAC_TXTIMEOUT_8814B(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8814B) << BIT_SHIFT_WMAC_TXTIMEOUT_8814B) +#define BIT_GET_WMAC_TXTIMEOUT_8814B(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8814B) & BIT_MASK_WMAC_TXTIMEOUT_8814B) + + + +/* 2 REG_STMP_THSD_8814B */ + +#define BIT_SHIFT_STMP_THSD_8814B 0 +#define BIT_MASK_STMP_THSD_8814B 0xff +#define BIT_STMP_THSD_8814B(x) (((x) & BIT_MASK_STMP_THSD_8814B) << BIT_SHIFT_STMP_THSD_8814B) +#define BIT_GET_STMP_THSD_8814B(x) (((x) >> BIT_SHIFT_STMP_THSD_8814B) & BIT_MASK_STMP_THSD_8814B) + + + +/* 2 REG_MAC_SPEC_SIFS_8814B (SPECIFICATION SIFS REGISTER) */ + +#define BIT_SHIFT_SPEC_SIFS_OFDM_8814B 8 +#define BIT_MASK_SPEC_SIFS_OFDM_8814B 0xff +#define BIT_SPEC_SIFS_OFDM_8814B(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8814B) << BIT_SHIFT_SPEC_SIFS_OFDM_8814B) +#define BIT_GET_SPEC_SIFS_OFDM_8814B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8814B) & BIT_MASK_SPEC_SIFS_OFDM_8814B) + + + +#define BIT_SHIFT_SPEC_SIFS_CCK_8814B 0 +#define BIT_MASK_SPEC_SIFS_CCK_8814B 0xff +#define BIT_SPEC_SIFS_CCK_8814B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8814B) << BIT_SHIFT_SPEC_SIFS_CCK_8814B) +#define BIT_GET_SPEC_SIFS_CCK_8814B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8814B) & BIT_MASK_SPEC_SIFS_CCK_8814B) + + + +/* 2 REG_ACKTO_CCK_8814B (ACK TIMEOUT REGISTER FOR CCK RATE) */ + +#define BIT_SHIFT_ACKTO_CCK_8814B 0 +#define BIT_MASK_ACKTO_CCK_8814B 0xff +#define BIT_ACKTO_CCK_8814B(x) (((x) & BIT_MASK_ACKTO_CCK_8814B) << BIT_SHIFT_ACKTO_CCK_8814B) +#define BIT_GET_ACKTO_CCK_8814B(x) (((x) >> BIT_SHIFT_ACKTO_CCK_8814B) & BIT_MASK_ACKTO_CCK_8814B) + + + +/* 2 REG_USTIME_EDCA_8814B (US TIME TUNING FOR EDCA REGISTER) */ + +#define BIT_SHIFT_USTIME_EDCA_V1_8814B 0 +#define BIT_MASK_USTIME_EDCA_V1_8814B 0x1ff +#define BIT_USTIME_EDCA_V1_8814B(x) (((x) & BIT_MASK_USTIME_EDCA_V1_8814B) << BIT_SHIFT_USTIME_EDCA_V1_8814B) +#define BIT_GET_USTIME_EDCA_V1_8814B(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8814B) & BIT_MASK_USTIME_EDCA_V1_8814B) + + + +/* 2 REG_RESP_SIFS_OFDM_8814B (RESPONSE SIFS FOR OFDM REGISTER) */ + +#define BIT_SHIFT_SIFS_R2T_OFDM_8814B 8 +#define BIT_MASK_SIFS_R2T_OFDM_8814B 0xff +#define BIT_SIFS_R2T_OFDM_8814B(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8814B) << BIT_SHIFT_SIFS_R2T_OFDM_8814B) +#define BIT_GET_SIFS_R2T_OFDM_8814B(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8814B) & BIT_MASK_SIFS_R2T_OFDM_8814B) + + + +#define BIT_SHIFT_SIFS_T2T_OFDM_8814B 0 +#define BIT_MASK_SIFS_T2T_OFDM_8814B 0xff +#define BIT_SIFS_T2T_OFDM_8814B(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8814B) << BIT_SHIFT_SIFS_T2T_OFDM_8814B) +#define BIT_GET_SIFS_T2T_OFDM_8814B(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8814B) & BIT_MASK_SIFS_T2T_OFDM_8814B) + + + +/* 2 REG_RESP_SIFS_CCK_8814B (RESPONSE SIFS FOR CCK REGISTER) */ + +#define BIT_SHIFT_SIFS_R2T_CCK_8814B 8 +#define BIT_MASK_SIFS_R2T_CCK_8814B 0xff +#define BIT_SIFS_R2T_CCK_8814B(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8814B) << BIT_SHIFT_SIFS_R2T_CCK_8814B) +#define BIT_GET_SIFS_R2T_CCK_8814B(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8814B) & BIT_MASK_SIFS_R2T_CCK_8814B) + + + +#define BIT_SHIFT_SIFS_T2T_CCK_8814B 0 +#define BIT_MASK_SIFS_T2T_CCK_8814B 0xff +#define BIT_SIFS_T2T_CCK_8814B(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8814B) << BIT_SHIFT_SIFS_T2T_CCK_8814B) +#define BIT_GET_SIFS_T2T_CCK_8814B(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8814B) & BIT_MASK_SIFS_T2T_CCK_8814B) + + + +/* 2 REG_EIFS_8814B (EIFS REGISTER) */ + +#define BIT_SHIFT_EIFS_8814B 0 +#define BIT_MASK_EIFS_8814B 0xffff +#define BIT_EIFS_8814B(x) (((x) & BIT_MASK_EIFS_8814B) << BIT_SHIFT_EIFS_8814B) +#define BIT_GET_EIFS_8814B(x) (((x) >> BIT_SHIFT_EIFS_8814B) & BIT_MASK_EIFS_8814B) + + + +/* 2 REG_CTS2TO_8814B (CTS2 TIMEOUT REGISTER) */ + +#define BIT_SHIFT_CTS2TO_8814B 0 +#define BIT_MASK_CTS2TO_8814B 0xff +#define BIT_CTS2TO_8814B(x) (((x) & BIT_MASK_CTS2TO_8814B) << BIT_SHIFT_CTS2TO_8814B) +#define BIT_GET_CTS2TO_8814B(x) (((x) >> BIT_SHIFT_CTS2TO_8814B) & BIT_MASK_CTS2TO_8814B) + + + +/* 2 REG_ACKTO_8814B (ACK TIMEOUT REGISTER) */ + +#define BIT_SHIFT_ACKTO_8814B 0 +#define BIT_MASK_ACKTO_8814B 0xff +#define BIT_ACKTO_8814B(x) (((x) & BIT_MASK_ACKTO_8814B) << BIT_SHIFT_ACKTO_8814B) +#define BIT_GET_ACKTO_8814B(x) (((x) >> BIT_SHIFT_ACKTO_8814B) & BIT_MASK_ACKTO_8814B) + + + +/* 2 REG_RPFM_MAP0_8814B (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 0) */ +#define BIT_MGT_RPFM15EN_8814B BIT(15) +#define BIT_MGT_RPFM14EN_8814B BIT(14) +#define BIT_MGT_RPFM13EN_8814B BIT(13) +#define BIT_MGT_RPFM12EN_8814B BIT(12) +#define BIT_MGT_RPFM11EN_8814B BIT(11) +#define BIT_MGT_RPFM10EN_8814B BIT(10) +#define BIT_MGT_RPFM9EN_8814B BIT(9) +#define BIT_MGT_RPFM8EN_8814B BIT(8) +#define BIT_MGT_RPFM7EN_8814B BIT(7) +#define BIT_MGT_RPFM6EN_8814B BIT(6) +#define BIT_MGT_RPFM5EN_8814B BIT(5) +#define BIT_MGT_RPFM4EN_8814B BIT(4) +#define BIT_MGT_RPFM3EN_8814B BIT(3) +#define BIT_MGT_RPFM2EN_8814B BIT(2) +#define BIT_MGT_RPFM1EN_8814B BIT(1) +#define BIT_MGT_RPFM0EN_8814B BIT(0) + +/* 2 REG_RPFM_MAP1_8814B (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 1) */ +#define BIT_DATA_RPFM15EN_8814B BIT(15) +#define BIT_DATA_RPFM14EN_8814B BIT(14) +#define BIT_DATA_RPFM13EN_8814B BIT(13) +#define BIT_DATA_RPFM12EN_8814B BIT(12) +#define BIT_DATA_RPFM11EN_8814B BIT(11) +#define BIT_DATA_RPFM10EN_8814B BIT(10) +#define BIT_DATA_RPFM9EN_8814B BIT(9) +#define BIT_DATA_RPFM8EN_8814B BIT(8) +#define BIT_DATA_RPFM7EN_8814B BIT(7) +#define BIT_DATA_RPFM6EN_8814B BIT(6) +#define BIT_DATA_RPFM5EN_8814B BIT(5) +#define BIT_DATA_RPFM4EN_8814B BIT(4) +#define BIT_DATA_RPFM3EN_8814B BIT(3) +#define BIT_DATA_RPFM2EN_8814B BIT(2) +#define BIT_DATA_RPFM1EN_8814B BIT(1) +#define BIT_DATA_RPFM0EN_8814B BIT(0) + +/* 2 REG_RPFM_CAM_CMD_8814B (RX PAYLOAD FRAME MASK CAM COMMAND REGISTER) */ +#define BIT_RPFM_CAM_POLLING_8814B BIT(31) +#define BIT_RPFM_CAM_CLR_8814B BIT(30) +#define BIT_RPFM_CAM_WE_8814B BIT(16) + +#define BIT_SHIFT_RPFM_CAM_ADDR_8814B 0 +#define BIT_MASK_RPFM_CAM_ADDR_8814B 0x7f +#define BIT_RPFM_CAM_ADDR_8814B(x) (((x) & BIT_MASK_RPFM_CAM_ADDR_8814B) << BIT_SHIFT_RPFM_CAM_ADDR_8814B) +#define BIT_GET_RPFM_CAM_ADDR_8814B(x) (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8814B) & BIT_MASK_RPFM_CAM_ADDR_8814B) + + + +/* 2 REG_RPFM_CAM_RWD_8814B (ACK TIMEOUT REGISTER) */ + +#define BIT_SHIFT_RPFM_CAM_RWD_8814B 0 +#define BIT_MASK_RPFM_CAM_RWD_8814B 0xffffffffL +#define BIT_RPFM_CAM_RWD_8814B(x) (((x) & BIT_MASK_RPFM_CAM_RWD_8814B) << BIT_SHIFT_RPFM_CAM_RWD_8814B) +#define BIT_GET_RPFM_CAM_RWD_8814B(x) (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8814B) & BIT_MASK_RPFM_CAM_RWD_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NAV_CTRL_8814B (NAV CONTROL REGISTER) */ + +#define BIT_SHIFT_NAV_UPPER_8814B 16 +#define BIT_MASK_NAV_UPPER_8814B 0xff +#define BIT_NAV_UPPER_8814B(x) (((x) & BIT_MASK_NAV_UPPER_8814B) << BIT_SHIFT_NAV_UPPER_8814B) +#define BIT_GET_NAV_UPPER_8814B(x) (((x) >> BIT_SHIFT_NAV_UPPER_8814B) & BIT_MASK_NAV_UPPER_8814B) + + + +#define BIT_SHIFT_RXMYRTS_NAV_8814B 8 +#define BIT_MASK_RXMYRTS_NAV_8814B 0xf +#define BIT_RXMYRTS_NAV_8814B(x) (((x) & BIT_MASK_RXMYRTS_NAV_8814B) << BIT_SHIFT_RXMYRTS_NAV_8814B) +#define BIT_GET_RXMYRTS_NAV_8814B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8814B) & BIT_MASK_RXMYRTS_NAV_8814B) + + + +#define BIT_SHIFT_RTSRST_8814B 0 +#define BIT_MASK_RTSRST_8814B 0xff +#define BIT_RTSRST_8814B(x) (((x) & BIT_MASK_RTSRST_8814B) << BIT_SHIFT_RTSRST_8814B) +#define BIT_GET_RTSRST_8814B(x) (((x) >> BIT_SHIFT_RTSRST_8814B) & BIT_MASK_RTSRST_8814B) + + + +/* 2 REG_BACAMCMD_8814B (BLOCK ACK CAM COMMAND REGISTER) */ +#define BIT_BACAM_POLL_8814B BIT(31) +#define BIT_BACAM_RST_8814B BIT(17) +#define BIT_BACAM_RW_8814B BIT(16) + +#define BIT_SHIFT_TXSBM_8814B 14 +#define BIT_MASK_TXSBM_8814B 0x3 +#define BIT_TXSBM_8814B(x) (((x) & BIT_MASK_TXSBM_8814B) << BIT_SHIFT_TXSBM_8814B) +#define BIT_GET_TXSBM_8814B(x) (((x) >> BIT_SHIFT_TXSBM_8814B) & BIT_MASK_TXSBM_8814B) + + + +#define BIT_SHIFT_BACAM_ADDR_8814B 0 +#define BIT_MASK_BACAM_ADDR_8814B 0x3f +#define BIT_BACAM_ADDR_8814B(x) (((x) & BIT_MASK_BACAM_ADDR_8814B) << BIT_SHIFT_BACAM_ADDR_8814B) +#define BIT_GET_BACAM_ADDR_8814B(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8814B) & BIT_MASK_BACAM_ADDR_8814B) + + + +/* 2 REG_BACAMCONTENT_8814B (BLOCK ACK CAM CONTENT REGISTER) */ + +#define BIT_SHIFT_BA_CONTENT_H_8814B (32 & CPU_OPT_WIDTH) +#define BIT_MASK_BA_CONTENT_H_8814B 0xffffffffL +#define BIT_BA_CONTENT_H_8814B(x) (((x) & BIT_MASK_BA_CONTENT_H_8814B) << BIT_SHIFT_BA_CONTENT_H_8814B) +#define BIT_GET_BA_CONTENT_H_8814B(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8814B) & BIT_MASK_BA_CONTENT_H_8814B) + + + +#define BIT_SHIFT_BA_CONTENT_L_8814B 0 +#define BIT_MASK_BA_CONTENT_L_8814B 0xffffffffL +#define BIT_BA_CONTENT_L_8814B(x) (((x) & BIT_MASK_BA_CONTENT_L_8814B) << BIT_SHIFT_BA_CONTENT_L_8814B) +#define BIT_GET_BA_CONTENT_L_8814B(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8814B) & BIT_MASK_BA_CONTENT_L_8814B) + + + +/* 2 REG_WMAC_BITMAP_CTL_8814B */ +#define BIT_BITMAP_VO_8814B BIT(7) +#define BIT_BITMAP_VI_8814B BIT(6) +#define BIT_BITMAP_BE_8814B BIT(5) +#define BIT_BITMAP_BK_8814B BIT(4) + +#define BIT_SHIFT_BITMAP_CONDITION_8814B 2 +#define BIT_MASK_BITMAP_CONDITION_8814B 0x3 +#define BIT_BITMAP_CONDITION_8814B(x) (((x) & BIT_MASK_BITMAP_CONDITION_8814B) << BIT_SHIFT_BITMAP_CONDITION_8814B) +#define BIT_GET_BITMAP_CONDITION_8814B(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8814B) & BIT_MASK_BITMAP_CONDITION_8814B) + + +#define BIT_BITMAP_SSNBK_COUNTER_CLR_8814B BIT(1) +#define BIT_BITMAP_FORCE_8814B BIT(0) + +/* 2 REG_TX_RX_8814B STATUS */ + +#define BIT_SHIFT_RXPKT_TYPE_8814B 2 +#define BIT_MASK_RXPKT_TYPE_8814B 0x3f +#define BIT_RXPKT_TYPE_8814B(x) (((x) & BIT_MASK_RXPKT_TYPE_8814B) << BIT_SHIFT_RXPKT_TYPE_8814B) +#define BIT_GET_RXPKT_TYPE_8814B(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8814B) & BIT_MASK_RXPKT_TYPE_8814B) + + +#define BIT_TXACT_IND_8814B BIT(1) +#define BIT_RXACT_IND_8814B BIT(0) + +/* 2 REG_WMAC_BACAM_RPMEN_8814B */ + +#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B 2 +#define BIT_MASK_BITMAP_SSNBK_COUNTER_8814B 0x3f +#define BIT_BITMAP_SSNBK_COUNTER_8814B(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8814B) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8814B(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) & BIT_MASK_BITMAP_SSNBK_COUNTER_8814B) + + +#define BIT_BITMAP_EN_8814B BIT(1) +#define BIT_WMAC_BACAM_RPMEN_8814B BIT(0) + +/* 2 REG_LBDLY_8814B (LOOPBACK DELAY REGISTER) */ + +#define BIT_SHIFT_LBDLY_8814B 0 +#define BIT_MASK_LBDLY_8814B 0x1f +#define BIT_LBDLY_8814B(x) (((x) & BIT_MASK_LBDLY_8814B) << BIT_SHIFT_LBDLY_8814B) +#define BIT_GET_LBDLY_8814B(x) (((x) >> BIT_SHIFT_LBDLY_8814B) & BIT_MASK_LBDLY_8814B) + + + +/* 2 REG_RXERR_RPT_8814B (RX ERROR REPORT REGISTER) */ + +#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B 28 +#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B 0xf +#define BIT_RXERR_RPT_SEL_V1_3_0_8814B(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8814B(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B) + + +#define BIT_RXERR_RPT_RST_8814B BIT(27) +#define BIT_RXERR_RPT_SEL_V1_4_8814B BIT(26) +#define BIT_W1S_8814B BIT(23) +#define BIT_UD_SELECT_BSSID_8814B BIT(22) + +#define BIT_SHIFT_UD_SUB_TYPE_8814B 18 +#define BIT_MASK_UD_SUB_TYPE_8814B 0xf +#define BIT_UD_SUB_TYPE_8814B(x) (((x) & BIT_MASK_UD_SUB_TYPE_8814B) << BIT_SHIFT_UD_SUB_TYPE_8814B) +#define BIT_GET_UD_SUB_TYPE_8814B(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8814B) & BIT_MASK_UD_SUB_TYPE_8814B) + + + +#define BIT_SHIFT_UD_TYPE_8814B 16 +#define BIT_MASK_UD_TYPE_8814B 0x3 +#define BIT_UD_TYPE_8814B(x) (((x) & BIT_MASK_UD_TYPE_8814B) << BIT_SHIFT_UD_TYPE_8814B) +#define BIT_GET_UD_TYPE_8814B(x) (((x) >> BIT_SHIFT_UD_TYPE_8814B) & BIT_MASK_UD_TYPE_8814B) + + + +#define BIT_SHIFT_RPT_COUNTER_8814B 0 +#define BIT_MASK_RPT_COUNTER_8814B 0xffff +#define BIT_RPT_COUNTER_8814B(x) (((x) & BIT_MASK_RPT_COUNTER_8814B) << BIT_SHIFT_RPT_COUNTER_8814B) +#define BIT_GET_RPT_COUNTER_8814B(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8814B) & BIT_MASK_RPT_COUNTER_8814B) + + + +/* 2 REG_WMAC_TRXPTCL_CTL_8814B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ + +#define BIT_SHIFT_ACKBA_TYPSEL_8814B (60 & CPU_OPT_WIDTH) +#define BIT_MASK_ACKBA_TYPSEL_8814B 0xf +#define BIT_ACKBA_TYPSEL_8814B(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8814B) << BIT_SHIFT_ACKBA_TYPSEL_8814B) +#define BIT_GET_ACKBA_TYPSEL_8814B(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8814B) & BIT_MASK_ACKBA_TYPSEL_8814B) + + + +#define BIT_SHIFT_ACKBA_ACKPCHK_8814B (56 & CPU_OPT_WIDTH) +#define BIT_MASK_ACKBA_ACKPCHK_8814B 0xf +#define BIT_ACKBA_ACKPCHK_8814B(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8814B) << BIT_SHIFT_ACKBA_ACKPCHK_8814B) +#define BIT_GET_ACKBA_ACKPCHK_8814B(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8814B) & BIT_MASK_ACKBA_ACKPCHK_8814B) + + + +#define BIT_SHIFT_ACKBAR_TYPESEL_8814B (48 & CPU_OPT_WIDTH) +#define BIT_MASK_ACKBAR_TYPESEL_8814B 0xff +#define BIT_ACKBAR_TYPESEL_8814B(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8814B) << BIT_SHIFT_ACKBAR_TYPESEL_8814B) +#define BIT_GET_ACKBAR_TYPESEL_8814B(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8814B) & BIT_MASK_ACKBAR_TYPESEL_8814B) + + + +#define BIT_SHIFT_ACKBAR_ACKPCHK_8814B (44 & CPU_OPT_WIDTH) +#define BIT_MASK_ACKBAR_ACKPCHK_8814B 0xf +#define BIT_ACKBAR_ACKPCHK_8814B(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8814B) << BIT_SHIFT_ACKBAR_ACKPCHK_8814B) +#define BIT_GET_ACKBAR_ACKPCHK_8814B(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8814B) & BIT_MASK_ACKBAR_ACKPCHK_8814B) + + +#define BIT_RXBA_IGNOREA2_8814B BIT(42) +#define BIT_EN_SAVE_ALL_TXOPADDR_8814B BIT(41) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8814B BIT(40) +#define BIT_DIS_TXBA_AMPDUFCSERR_8814B BIT(39) +#define BIT_DIS_TXBA_RXBARINFULL_8814B BIT(38) +#define BIT_DIS_TXCFE_INFULL_8814B BIT(37) +#define BIT_DIS_TXCTS_INFULL_8814B BIT(36) +#define BIT_EN_TXACKBA_IN_TX_RDG_8814B BIT(35) +#define BIT_EN_TXACKBA_IN_TXOP_8814B BIT(34) +#define BIT_EN_TXCTS_IN_RXNAV_8814B BIT(33) +#define BIT_EN_TXCTS_INTXOP_8814B BIT(32) +#define BIT_BLK_EDCA_BBSLP_8814B BIT(31) +#define BIT_BLK_EDCA_BBSBY_8814B BIT(30) +#define BIT_ACKTO_BLOCK_SCH_EN_8814B BIT(27) +#define BIT_EIFS_BLOCK_SCH_EN_8814B BIT(26) +#define BIT_PLCPCHK_RST_EIFS_8814B BIT(25) +#define BIT_CCA_RST_EIFS_8814B BIT(24) +#define BIT_DIS_UPD_MYRXPKTNAV_8814B BIT(23) +#define BIT_EARLY_TXBA_8814B BIT(22) + +#define BIT_SHIFT_RESP_CHNBUSY_8814B 20 +#define BIT_MASK_RESP_CHNBUSY_8814B 0x3 +#define BIT_RESP_CHNBUSY_8814B(x) (((x) & BIT_MASK_RESP_CHNBUSY_8814B) << BIT_SHIFT_RESP_CHNBUSY_8814B) +#define BIT_GET_RESP_CHNBUSY_8814B(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8814B) & BIT_MASK_RESP_CHNBUSY_8814B) + + +#define BIT_RESP_DCTS_EN_8814B BIT(19) +#define BIT_RESP_DCFE_EN_8814B BIT(18) +#define BIT_RESP_SPLCPEN_8814B BIT(17) +#define BIT_RESP_SGIEN_8814B BIT(16) +#define BIT_RESP_LDPC_EN_8814B BIT(15) +#define BIT_DIS_RESP_ACKINCCA_8814B BIT(14) +#define BIT_DIS_RESP_CTSINCCA_8814B BIT(13) + +#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B 10 +#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B 0x7 +#define BIT_R_WMAC_SECOND_CCA_TIMER_8814B(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B) + + + +#define BIT_SHIFT_RFMOD_8814B 7 +#define BIT_MASK_RFMOD_8814B 0x3 +#define BIT_RFMOD_8814B(x) (((x) & BIT_MASK_RFMOD_8814B) << BIT_SHIFT_RFMOD_8814B) +#define BIT_GET_RFMOD_8814B(x) (((x) >> BIT_SHIFT_RFMOD_8814B) & BIT_MASK_RFMOD_8814B) + + + +#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B 5 +#define BIT_MASK_RESP_CTS_DYNBW_SEL_8814B 0x3 +#define BIT_RESP_CTS_DYNBW_SEL_8814B(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8814B) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8814B(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) & BIT_MASK_RESP_CTS_DYNBW_SEL_8814B) + + +#define BIT_DLY_TX_WAIT_RXANTSEL_8814B BIT(4) +#define BIT_TXRESP_BY_RXANTSEL_8814B BIT(3) + +#define BIT_SHIFT_ORIG_DCTS_CHK_8814B 0 +#define BIT_MASK_ORIG_DCTS_CHK_8814B 0x3 +#define BIT_ORIG_DCTS_CHK_8814B(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8814B) << BIT_SHIFT_ORIG_DCTS_CHK_8814B) +#define BIT_GET_ORIG_DCTS_CHK_8814B(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8814B) & BIT_MASK_ORIG_DCTS_CHK_8814B) + + + +/* 2 REG_CAMCMD_8814B (CAM COMMAND REGISTER) */ +#define BIT_SECCAM_POLLING_8814B BIT(31) +#define BIT_SECCAM_CLR_8814B BIT(30) +#define BIT_MFBCAM_CLR_8814B BIT(29) +#define BIT_SECCAM_WE_8814B BIT(16) + +#define BIT_SHIFT_SECCAM_ADDR_V2_8814B 0 +#define BIT_MASK_SECCAM_ADDR_V2_8814B 0x3ff +#define BIT_SECCAM_ADDR_V2_8814B(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8814B) << BIT_SHIFT_SECCAM_ADDR_V2_8814B) +#define BIT_GET_SECCAM_ADDR_V2_8814B(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8814B) & BIT_MASK_SECCAM_ADDR_V2_8814B) + + + +/* 2 REG_CAMWRITE_8814B (CAM WRITE REGISTER) */ + +#define BIT_SHIFT_CAMW_DATA_8814B 0 +#define BIT_MASK_CAMW_DATA_8814B 0xffffffffL +#define BIT_CAMW_DATA_8814B(x) (((x) & BIT_MASK_CAMW_DATA_8814B) << BIT_SHIFT_CAMW_DATA_8814B) +#define BIT_GET_CAMW_DATA_8814B(x) (((x) >> BIT_SHIFT_CAMW_DATA_8814B) & BIT_MASK_CAMW_DATA_8814B) + + + +/* 2 REG_CAMREAD_8814B (CAM READ REGISTER) */ + +#define BIT_SHIFT_CAMR_DATA_8814B 0 +#define BIT_MASK_CAMR_DATA_8814B 0xffffffffL +#define BIT_CAMR_DATA_8814B(x) (((x) & BIT_MASK_CAMR_DATA_8814B) << BIT_SHIFT_CAMR_DATA_8814B) +#define BIT_GET_CAMR_DATA_8814B(x) (((x) >> BIT_SHIFT_CAMR_DATA_8814B) & BIT_MASK_CAMR_DATA_8814B) + + + +/* 2 REG_CAMDBG_8814B (CAM DEBUG REGISTER) */ +#define BIT_SECCAM_INFO_8814B BIT(31) +#define BIT_SEC_KEYFOUND_8814B BIT(15) + +#define BIT_SHIFT_CAMDBG_SEC_TYPE_8814B 12 +#define BIT_MASK_CAMDBG_SEC_TYPE_8814B 0x7 +#define BIT_CAMDBG_SEC_TYPE_8814B(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8814B) << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) +#define BIT_GET_CAMDBG_SEC_TYPE_8814B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) & BIT_MASK_CAMDBG_SEC_TYPE_8814B) + + +#define BIT_CAMDBG_EXT_SECTYPE_8814B BIT(11) + +#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B 5 +#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B 0x1f +#define BIT_CAMDBG_MIC_KEY_IDX_8814B(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8814B(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B) + + + +#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B 0 +#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B 0x1f +#define BIT_CAMDBG_SEC_KEY_IDX_8814B(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8814B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B) + + + +/* 2 REG_RXFILTER_ACTION_1_8814B */ + +#define BIT_SHIFT_RXFILTER_ACTION_1_8814B 0 +#define BIT_MASK_RXFILTER_ACTION_1_8814B 0xff +#define BIT_RXFILTER_ACTION_1_8814B(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8814B) << BIT_SHIFT_RXFILTER_ACTION_1_8814B) +#define BIT_GET_RXFILTER_ACTION_1_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8814B) & BIT_MASK_RXFILTER_ACTION_1_8814B) + + + +/* 2 REG_RXFILTER_CATEGORY_1_8814B */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_1_8814B 0 +#define BIT_MASK_RXFILTER_CATEGORY_1_8814B 0xff +#define BIT_RXFILTER_CATEGORY_1_8814B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8814B) << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) +#define BIT_GET_RXFILTER_CATEGORY_1_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) & BIT_MASK_RXFILTER_CATEGORY_1_8814B) + + + +/* 2 REG_SECCFG_8814B (SECURITY CONFIGURATION REGISTER) */ +#define BIT_DIS_GCLK_WAPI_8814B BIT(15) +#define BIT_DIS_GCLK_AES_8814B BIT(14) +#define BIT_DIS_GCLK_TKIP_8814B BIT(13) +#define BIT_AES_SEL_QC_1_8814B BIT(12) +#define BIT_AES_SEL_QC_0_8814B BIT(11) +#define BIT_CHK_BMC_8814B BIT(9) +#define BIT_CHK_KEYID_8814B BIT(8) +#define BIT_RXBCUSEDK_8814B BIT(7) +#define BIT_TXBCUSEDK_8814B BIT(6) +#define BIT_NOSKMC_8814B BIT(5) +#define BIT_SKBYA2_8814B BIT(4) +#define BIT_RXDEC_8814B BIT(3) +#define BIT_TXENC_8814B BIT(2) +#define BIT_RXUHUSEDK_8814B BIT(1) +#define BIT_TXUHUSEDK_8814B BIT(0) + +/* 2 REG_RXFILTER_ACTION_3_8814B */ + +#define BIT_SHIFT_RXFILTER_ACTION_3_8814B 0 +#define BIT_MASK_RXFILTER_ACTION_3_8814B 0xff +#define BIT_RXFILTER_ACTION_3_8814B(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8814B) << BIT_SHIFT_RXFILTER_ACTION_3_8814B) +#define BIT_GET_RXFILTER_ACTION_3_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8814B) & BIT_MASK_RXFILTER_ACTION_3_8814B) + + + +/* 2 REG_RXFILTER_CATEGORY_3_8814B */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_3_8814B 0 +#define BIT_MASK_RXFILTER_CATEGORY_3_8814B 0xff +#define BIT_RXFILTER_CATEGORY_3_8814B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8814B) << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) +#define BIT_GET_RXFILTER_CATEGORY_3_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) & BIT_MASK_RXFILTER_CATEGORY_3_8814B) + + + +/* 2 REG_RXFILTER_ACTION_2_8814B */ + +#define BIT_SHIFT_RXFILTER_ACTION_2_8814B 0 +#define BIT_MASK_RXFILTER_ACTION_2_8814B 0xff +#define BIT_RXFILTER_ACTION_2_8814B(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8814B) << BIT_SHIFT_RXFILTER_ACTION_2_8814B) +#define BIT_GET_RXFILTER_ACTION_2_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8814B) & BIT_MASK_RXFILTER_ACTION_2_8814B) + + + +/* 2 REG_RXFILTER_CATEGORY_2_8814B */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_2_8814B 0 +#define BIT_MASK_RXFILTER_CATEGORY_2_8814B 0xff +#define BIT_RXFILTER_CATEGORY_2_8814B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8814B) << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) +#define BIT_GET_RXFILTER_CATEGORY_2_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) & BIT_MASK_RXFILTER_CATEGORY_2_8814B) + + + +/* 2 REG_RXFLTMAP4_8814B (RX FILTER MAP GROUP 4) */ +#define BIT_CTRLFLT15EN_FW_8814B BIT(15) +#define BIT_CTRLFLT14EN_FW_8814B BIT(14) +#define BIT_CTRLFLT13EN_FW_8814B BIT(13) +#define BIT_CTRLFLT12EN_FW_8814B BIT(12) +#define BIT_CTRLFLT11EN_FW_8814B BIT(11) +#define BIT_CTRLFLT10EN_FW_8814B BIT(10) +#define BIT_CTRLFLT9EN_FW_8814B BIT(9) +#define BIT_CTRLFLT8EN_FW_8814B BIT(8) +#define BIT_CTRLFLT7EN_FW_8814B BIT(7) +#define BIT_CTRLFLT6EN_FW_8814B BIT(6) +#define BIT_CTRLFLT5EN_FW_8814B BIT(5) +#define BIT_CTRLFLT4EN_FW_8814B BIT(4) +#define BIT_CTRLFLT3EN_FW_8814B BIT(3) +#define BIT_CTRLFLT2EN_FW_8814B BIT(2) +#define BIT_CTRLFLT1EN_FW_8814B BIT(1) +#define BIT_CTRLFLT0EN_FW_8814B BIT(0) + +/* 2 REG_RXFLTMAP3_8814B (RX FILTER MAP GROUP 3) */ +#define BIT_MGTFLT15EN_FW_8814B BIT(15) +#define BIT_MGTFLT14EN_FW_8814B BIT(14) +#define BIT_MGTFLT13EN_FW_8814B BIT(13) +#define BIT_MGTFLT12EN_FW_8814B BIT(12) +#define BIT_MGTFLT11EN_FW_8814B BIT(11) +#define BIT_MGTFLT10EN_FW_8814B BIT(10) +#define BIT_MGTFLT9EN_FW_8814B BIT(9) +#define BIT_MGTFLT8EN_FW_8814B BIT(8) +#define BIT_MGTFLT7EN_FW_8814B BIT(7) +#define BIT_MGTFLT6EN_FW_8814B BIT(6) +#define BIT_MGTFLT5EN_FW_8814B BIT(5) +#define BIT_MGTFLT4EN_FW_8814B BIT(4) +#define BIT_MGTFLT3EN_FW_8814B BIT(3) +#define BIT_MGTFLT2EN_FW_8814B BIT(2) +#define BIT_MGTFLT1EN_FW_8814B BIT(1) +#define BIT_MGTFLT0EN_FW_8814B BIT(0) + +/* 2 REG_RXFLTMAP6_8814B (RX FILTER MAP GROUP 3) */ +#define BIT_ACTIONFLT15EN_FW_8814B BIT(15) +#define BIT_ACTIONFLT14EN_FW_8814B BIT(14) +#define BIT_ACTIONFLT13EN_FW_8814B BIT(13) +#define BIT_ACTIONFLT12EN_FW_8814B BIT(12) +#define BIT_ACTIONFLT11EN_FW_8814B BIT(11) +#define BIT_ACTIONFLT10EN_FW_8814B BIT(10) +#define BIT_ACTIONFLT9EN_FW_8814B BIT(9) +#define BIT_ACTIONFLT8EN_FW_8814B BIT(8) +#define BIT_ACTIONFLT7EN_FW_8814B BIT(7) +#define BIT_ACTIONFLT6EN_FW_8814B BIT(6) +#define BIT_ACTIONFLT5EN_FW_8814B BIT(5) +#define BIT_ACTIONFLT4EN_FW_8814B BIT(4) +#define BIT_ACTIONFLT3EN_FW_8814B BIT(3) +#define BIT_ACTIONFLT2EN_FW_8814B BIT(2) +#define BIT_ACTIONFLT1EN_FW_8814B BIT(1) +#define BIT_ACTIONFLT0EN_FW_8814B BIT(0) + +/* 2 REG_RXFLTMAP5_8814B (RX FILTER MAP GROUP 3) */ +#define BIT_DATAFLT15EN_FW_8814B BIT(15) +#define BIT_DATAFLT14EN_FW_8814B BIT(14) +#define BIT_DATAFLT13EN_FW_8814B BIT(13) +#define BIT_DATAFLT12EN_FW_8814B BIT(12) +#define BIT_DATAFLT11EN_FW_8814B BIT(11) +#define BIT_DATAFLT10EN_FW_8814B BIT(10) +#define BIT_DATAFLT9EN_FW_8814B BIT(9) +#define BIT_DATAFLT8EN_FW_8814B BIT(8) +#define BIT_DATAFLT7EN_FW_8814B BIT(7) +#define BIT_DATAFLT6EN_FW_8814B BIT(6) +#define BIT_DATAFLT5EN_FW_8814B BIT(5) +#define BIT_DATAFLT4EN_FW_8814B BIT(4) +#define BIT_DATAFLT3EN_FW_8814B BIT(3) +#define BIT_DATAFLT2EN_FW_8814B BIT(2) +#define BIT_DATAFLT1EN_FW_8814B BIT(1) +#define BIT_DATAFLT0EN_FW_8814B BIT(0) + +/* 2 REG_WMMPS_UAPSD_TID_8814B (WMM POWER SAVE UAPSD TID REGISTER) */ +#define BIT_WMMPS_UAPSD_TID7_8814B BIT(7) +#define BIT_WMMPS_UAPSD_TID6_8814B BIT(6) +#define BIT_WMMPS_UAPSD_TID5_8814B BIT(5) +#define BIT_WMMPS_UAPSD_TID4_8814B BIT(4) +#define BIT_WMMPS_UAPSD_TID3_8814B BIT(3) +#define BIT_WMMPS_UAPSD_TID2_8814B BIT(2) +#define BIT_WMMPS_UAPSD_TID1_8814B BIT(1) +#define BIT_WMMPS_UAPSD_TID0_8814B BIT(0) + +/* 2 REG_PS_RX_INFO_8814B (POWER SAVE RX INFORMATION REGISTER) */ + +#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B 5 +#define BIT_MASK_PORTSEL__PS_RX_INFO_8814B 0x7 +#define BIT_PORTSEL__PS_RX_INFO_8814B(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8814B) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) +#define BIT_GET_PORTSEL__PS_RX_INFO_8814B(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) & BIT_MASK_PORTSEL__PS_RX_INFO_8814B) + + +#define BIT_RXCTRLIN0_8814B BIT(4) +#define BIT_RXMGTIN0_8814B BIT(3) +#define BIT_RXDATAIN2_8814B BIT(2) +#define BIT_RXDATAIN1_8814B BIT(1) +#define BIT_RXDATAIN0_8814B BIT(0) + +/* 2 REG_NAN_RX_TSF_FILTER_8814B(NAN_RX_TSF_ADDRESS_FILTER) */ +#define BIT_CHK_TSF_TA_8814B BIT(2) +#define BIT_CHK_TSF_CBSSID_8814B BIT(1) +#define BIT_CHK_TSF_EN_8814B BIT(0) + +/* 2 REG_WOW_CTRL_8814B (WAKE ON WLAN CONTROL REGISTER) */ + +#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B 6 +#define BIT_MASK_PSF_BSSIDSEL_B2B1_8814B 0x3 +#define BIT_PSF_BSSIDSEL_B2B1_8814B(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8814B) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8814B(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) & BIT_MASK_PSF_BSSIDSEL_B2B1_8814B) + + +#define BIT_WOWHCI_8814B BIT(5) +#define BIT_PSF_BSSIDSEL_B0_8814B BIT(4) +#define BIT_UWF_8814B BIT(3) +#define BIT_MAGIC_8814B BIT(2) +#define BIT_WOWEN_8814B BIT(1) +#define BIT_FORCE_WAKEUP_8814B BIT(0) + +/* 2 REG_LPNAV_CTRL_8814B (LOW POWER NAV CONTROL REGISTER) */ +#define BIT_LPNAV_EN_8814B BIT(31) + +#define BIT_SHIFT_LPNAV_EARLY_8814B 16 +#define BIT_MASK_LPNAV_EARLY_8814B 0x7fff +#define BIT_LPNAV_EARLY_8814B(x) (((x) & BIT_MASK_LPNAV_EARLY_8814B) << BIT_SHIFT_LPNAV_EARLY_8814B) +#define BIT_GET_LPNAV_EARLY_8814B(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8814B) & BIT_MASK_LPNAV_EARLY_8814B) + + + +#define BIT_SHIFT_LPNAV_TH_8814B 0 +#define BIT_MASK_LPNAV_TH_8814B 0xffff +#define BIT_LPNAV_TH_8814B(x) (((x) & BIT_MASK_LPNAV_TH_8814B) << BIT_SHIFT_LPNAV_TH_8814B) +#define BIT_GET_LPNAV_TH_8814B(x) (((x) >> BIT_SHIFT_LPNAV_TH_8814B) & BIT_MASK_LPNAV_TH_8814B) + + + +/* 2 REG_WKFMCAM_CMD_8814B (WAKEUP FRAME CAM COMMAND REGISTER) */ +#define BIT_WKFCAM_POLLING_V1_8814B BIT(31) +#define BIT_WKFCAM_CLR_V1_8814B BIT(30) +#define BIT_WKFCAM_WE_8814B BIT(16) + +#define BIT_SHIFT_WKFCAM_ADDR_V2_8814B 8 +#define BIT_MASK_WKFCAM_ADDR_V2_8814B 0xff +#define BIT_WKFCAM_ADDR_V2_8814B(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8814B) << BIT_SHIFT_WKFCAM_ADDR_V2_8814B) +#define BIT_GET_WKFCAM_ADDR_V2_8814B(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8814B) & BIT_MASK_WKFCAM_ADDR_V2_8814B) + + + +#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B 0 +#define BIT_MASK_WKFCAM_CAM_NUM_V1_8814B 0xff +#define BIT_WKFCAM_CAM_NUM_V1_8814B(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8814B) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8814B(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) & BIT_MASK_WKFCAM_CAM_NUM_V1_8814B) + + + +/* 2 REG_WKFMCAM_RWD_8814B (WAKEUP FRAME READ/WRITE DATA) */ + +#define BIT_SHIFT_WKFMCAM_RWD_8814B 0 +#define BIT_MASK_WKFMCAM_RWD_8814B 0xffffffffL +#define BIT_WKFMCAM_RWD_8814B(x) (((x) & BIT_MASK_WKFMCAM_RWD_8814B) << BIT_SHIFT_WKFMCAM_RWD_8814B) +#define BIT_GET_WKFMCAM_RWD_8814B(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8814B) & BIT_MASK_WKFMCAM_RWD_8814B) + + + +/* 2 REG_RXFLTMAP1_8814B (RX FILTER MAP GROUP 1) */ +#define BIT_CTRLFLT15EN_8814B BIT(15) +#define BIT_CTRLFLT14EN_8814B BIT(14) +#define BIT_CTRLFLT13EN_8814B BIT(13) +#define BIT_CTRLFLT12EN_8814B BIT(12) +#define BIT_CTRLFLT11EN_8814B BIT(11) +#define BIT_CTRLFLT10EN_8814B BIT(10) +#define BIT_CTRLFLT9EN_8814B BIT(9) +#define BIT_CTRLFLT8EN_8814B BIT(8) +#define BIT_CTRLFLT7EN_8814B BIT(7) +#define BIT_CTRLFLT6EN_8814B BIT(6) +#define BIT_CTRLFLT5EN_8814B BIT(5) +#define BIT_CTRLFLT4EN_8814B BIT(4) +#define BIT_CTRLFLT3EN_8814B BIT(3) +#define BIT_CTRLFLT2EN_8814B BIT(2) +#define BIT_CTRLFLT1EN_8814B BIT(1) +#define BIT_CTRLFLT0EN_8814B BIT(0) + +/* 2 REG_RXFLTMAP0_8814B (RX FILTER MAP GROUP 0) */ +#define BIT_MGTFLT15EN_8814B BIT(15) +#define BIT_MGTFLT14EN_8814B BIT(14) +#define BIT_MGTFLT13EN_8814B BIT(13) +#define BIT_MGTFLT12EN_8814B BIT(12) +#define BIT_MGTFLT11EN_8814B BIT(11) +#define BIT_MGTFLT10EN_8814B BIT(10) +#define BIT_MGTFLT9EN_8814B BIT(9) +#define BIT_MGTFLT8EN_8814B BIT(8) +#define BIT_MGTFLT7EN_8814B BIT(7) +#define BIT_MGTFLT6EN_8814B BIT(6) +#define BIT_MGTFLT5EN_8814B BIT(5) +#define BIT_MGTFLT4EN_8814B BIT(4) +#define BIT_MGTFLT3EN_8814B BIT(3) +#define BIT_MGTFLT2EN_8814B BIT(2) +#define BIT_MGTFLT1EN_8814B BIT(1) +#define BIT_MGTFLT0EN_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_RXFLTMAP_8814B (RX FILTER MAP GROUP 2) */ +#define BIT_DATAFLT15EN_8814B BIT(15) +#define BIT_DATAFLT14EN_8814B BIT(14) +#define BIT_DATAFLT13EN_8814B BIT(13) +#define BIT_DATAFLT12EN_8814B BIT(12) +#define BIT_DATAFLT11EN_8814B BIT(11) +#define BIT_DATAFLT10EN_8814B BIT(10) +#define BIT_DATAFLT9EN_8814B BIT(9) +#define BIT_DATAFLT8EN_8814B BIT(8) +#define BIT_DATAFLT7EN_8814B BIT(7) +#define BIT_DATAFLT6EN_8814B BIT(6) +#define BIT_DATAFLT5EN_8814B BIT(5) +#define BIT_DATAFLT4EN_8814B BIT(4) +#define BIT_DATAFLT3EN_8814B BIT(3) +#define BIT_DATAFLT2EN_8814B BIT(2) +#define BIT_DATAFLT1EN_8814B BIT(1) +#define BIT_DATAFLT0EN_8814B BIT(0) + +/* 2 REG_BCN_PSR_RPT_8814B (BEACON PARSER REPORT REGISTER) */ + +#define BIT_SHIFT_DTIM_CNT_8814B 24 +#define BIT_MASK_DTIM_CNT_8814B 0xff +#define BIT_DTIM_CNT_8814B(x) (((x) & BIT_MASK_DTIM_CNT_8814B) << BIT_SHIFT_DTIM_CNT_8814B) +#define BIT_GET_DTIM_CNT_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT_8814B) & BIT_MASK_DTIM_CNT_8814B) + + + +#define BIT_SHIFT_DTIM_PERIOD_8814B 16 +#define BIT_MASK_DTIM_PERIOD_8814B 0xff +#define BIT_DTIM_PERIOD_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD_8814B) << BIT_SHIFT_DTIM_PERIOD_8814B) +#define BIT_GET_DTIM_PERIOD_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8814B) & BIT_MASK_DTIM_PERIOD_8814B) + + +#define BIT_DTIM_8814B BIT(15) +#define BIT_TIM_8814B BIT(14) + +#define BIT_SHIFT_PS_AID_0_8814B 0 +#define BIT_MASK_PS_AID_0_8814B 0x7ff +#define BIT_PS_AID_0_8814B(x) (((x) & BIT_MASK_PS_AID_0_8814B) << BIT_SHIFT_PS_AID_0_8814B) +#define BIT_GET_PS_AID_0_8814B(x) (((x) >> BIT_SHIFT_PS_AID_0_8814B) & BIT_MASK_PS_AID_0_8814B) + + + +/* 2 REG_FLC_TRPC_8814B (TIMER OF FLC_RPC) */ +#define BIT_FLC_RPCT_V1_8814B BIT(7) +#define BIT_MODE_8814B BIT(6) + +#define BIT_SHIFT_TRPCD_8814B 0 +#define BIT_MASK_TRPCD_8814B 0x3f +#define BIT_TRPCD_8814B(x) (((x) & BIT_MASK_TRPCD_8814B) << BIT_SHIFT_TRPCD_8814B) +#define BIT_GET_TRPCD_8814B(x) (((x) >> BIT_SHIFT_TRPCD_8814B) & BIT_MASK_TRPCD_8814B) + + + +/* 2 REG_FLC_PTS_8814B (PKT TYPE SELECTION OF FLC_RPC T) */ +#define BIT_CMF_8814B BIT(2) +#define BIT_CCF_8814B BIT(1) +#define BIT_CDF_8814B BIT(0) + +/* 2 REG_FLC_RPCT_8814B (FLC_RPC THRESHOLD) */ + +#define BIT_SHIFT_FLC_RPCT_8814B 0 +#define BIT_MASK_FLC_RPCT_8814B 0xff +#define BIT_FLC_RPCT_8814B(x) (((x) & BIT_MASK_FLC_RPCT_8814B) << BIT_SHIFT_FLC_RPCT_8814B) +#define BIT_GET_FLC_RPCT_8814B(x) (((x) >> BIT_SHIFT_FLC_RPCT_8814B) & BIT_MASK_FLC_RPCT_8814B) + + + +/* 2 REG_FLC_RPC_8814B (FW LPS CONDITION -- RX PKT COUNTER) */ + +#define BIT_SHIFT_FLC_RPC_8814B 0 +#define BIT_MASK_FLC_RPC_8814B 0xff +#define BIT_FLC_RPC_8814B(x) (((x) & BIT_MASK_FLC_RPC_8814B) << BIT_SHIFT_FLC_RPC_8814B) +#define BIT_GET_FLC_RPC_8814B(x) (((x) >> BIT_SHIFT_FLC_RPC_8814B) & BIT_MASK_FLC_RPC_8814B) + + + +/* 2 REG_RXPKTMON_CTRL_8814B */ + +#define BIT_SHIFT_RXBKQPKT_SEQ_8814B 20 +#define BIT_MASK_RXBKQPKT_SEQ_8814B 0xf +#define BIT_RXBKQPKT_SEQ_8814B(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8814B) << BIT_SHIFT_RXBKQPKT_SEQ_8814B) +#define BIT_GET_RXBKQPKT_SEQ_8814B(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8814B) & BIT_MASK_RXBKQPKT_SEQ_8814B) + + + +#define BIT_SHIFT_RXBEQPKT_SEQ_8814B 16 +#define BIT_MASK_RXBEQPKT_SEQ_8814B 0xf +#define BIT_RXBEQPKT_SEQ_8814B(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8814B) << BIT_SHIFT_RXBEQPKT_SEQ_8814B) +#define BIT_GET_RXBEQPKT_SEQ_8814B(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8814B) & BIT_MASK_RXBEQPKT_SEQ_8814B) + + + +#define BIT_SHIFT_RXVIQPKT_SEQ_8814B 12 +#define BIT_MASK_RXVIQPKT_SEQ_8814B 0xf +#define BIT_RXVIQPKT_SEQ_8814B(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8814B) << BIT_SHIFT_RXVIQPKT_SEQ_8814B) +#define BIT_GET_RXVIQPKT_SEQ_8814B(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8814B) & BIT_MASK_RXVIQPKT_SEQ_8814B) + + + +#define BIT_SHIFT_RXVOQPKT_SEQ_8814B 8 +#define BIT_MASK_RXVOQPKT_SEQ_8814B 0xf +#define BIT_RXVOQPKT_SEQ_8814B(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8814B) << BIT_SHIFT_RXVOQPKT_SEQ_8814B) +#define BIT_GET_RXVOQPKT_SEQ_8814B(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8814B) & BIT_MASK_RXVOQPKT_SEQ_8814B) + + +#define BIT_RXBKQPKT_ERR_8814B BIT(7) +#define BIT_RXBEQPKT_ERR_8814B BIT(6) +#define BIT_RXVIQPKT_ERR_8814B BIT(5) +#define BIT_RXVOQPKT_ERR_8814B BIT(4) +#define BIT_RXDMA_MON_EN_8814B BIT(2) +#define BIT_RXPKT_MON_RST_8814B BIT(1) +#define BIT_RXPKT_MON_EN_8814B BIT(0) + +/* 2 REG_STATE_MON_8814B */ + +#define BIT_SHIFT_STATE_SEL_8814B 24 +#define BIT_MASK_STATE_SEL_8814B 0x1f +#define BIT_STATE_SEL_8814B(x) (((x) & BIT_MASK_STATE_SEL_8814B) << BIT_SHIFT_STATE_SEL_8814B) +#define BIT_GET_STATE_SEL_8814B(x) (((x) >> BIT_SHIFT_STATE_SEL_8814B) & BIT_MASK_STATE_SEL_8814B) + + + +#define BIT_SHIFT_STATE_INFO_8814B 8 +#define BIT_MASK_STATE_INFO_8814B 0xff +#define BIT_STATE_INFO_8814B(x) (((x) & BIT_MASK_STATE_INFO_8814B) << BIT_SHIFT_STATE_INFO_8814B) +#define BIT_GET_STATE_INFO_8814B(x) (((x) >> BIT_SHIFT_STATE_INFO_8814B) & BIT_MASK_STATE_INFO_8814B) + + +#define BIT_UPD_NXT_STATE_8814B BIT(7) + +#define BIT_SHIFT_CUR_STATE_8814B 0 +#define BIT_MASK_CUR_STATE_8814B 0x7f +#define BIT_CUR_STATE_8814B(x) (((x) & BIT_MASK_CUR_STATE_8814B) << BIT_SHIFT_CUR_STATE_8814B) +#define BIT_GET_CUR_STATE_8814B(x) (((x) >> BIT_SHIFT_CUR_STATE_8814B) & BIT_MASK_CUR_STATE_8814B) + + + +/* 2 REG_ERROR_MON_8814B */ +#define BIT_MACRX_ERR_1_8814B BIT(17) +#define BIT_MACRX_ERR_0_8814B BIT(16) +#define BIT_MACTX_ERR_3_8814B BIT(3) +#define BIT_MACTX_ERR_2_8814B BIT(2) +#define BIT_MACTX_ERR_1_8814B BIT(1) +#define BIT_MACTX_ERR_0_8814B BIT(0) + +/* 2 REG_SEARCH_MACID_8814B */ +#define BIT_EN_TXRPTBUF_CLK_8814B BIT(31) + +#define BIT_SHIFT_INFO_INDEX_OFFSET_8814B 16 +#define BIT_MASK_INFO_INDEX_OFFSET_8814B 0x1fff +#define BIT_INFO_INDEX_OFFSET_8814B(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8814B) << BIT_SHIFT_INFO_INDEX_OFFSET_8814B) +#define BIT_GET_INFO_INDEX_OFFSET_8814B(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8814B) & BIT_MASK_INFO_INDEX_OFFSET_8814B) + + +#define BIT_WMAC_SRCH_FIFOFULL_8814B BIT(15) +#define BIT_DIS_INFOSRCH_8814B BIT(14) +#define BIT_DISABLE_B0_8814B BIT(13) + +#define BIT_SHIFT_INFO_ADDR_OFFSET_8814B 0 +#define BIT_MASK_INFO_ADDR_OFFSET_8814B 0x1fff +#define BIT_INFO_ADDR_OFFSET_8814B(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8814B) << BIT_SHIFT_INFO_ADDR_OFFSET_8814B) +#define BIT_GET_INFO_ADDR_OFFSET_8814B(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8814B) & BIT_MASK_INFO_ADDR_OFFSET_8814B) + + + +/* 2 REG_BT_COEX_TABLE_8814B (BT-COEXISTENCE CONTROL REGISTER) */ +#define BIT_PRI_MASK_RX_RESP_8814B BIT(126) +#define BIT_PRI_MASK_RXOFDM_8814B BIT(125) +#define BIT_PRI_MASK_RXCCK_8814B BIT(124) + +#define BIT_SHIFT_PRI_MASK_TXAC_8814B (117 & CPU_OPT_WIDTH) +#define BIT_MASK_PRI_MASK_TXAC_8814B 0x7f +#define BIT_PRI_MASK_TXAC_8814B(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8814B) << BIT_SHIFT_PRI_MASK_TXAC_8814B) +#define BIT_GET_PRI_MASK_TXAC_8814B(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8814B) & BIT_MASK_PRI_MASK_TXAC_8814B) + + + +#define BIT_SHIFT_PRI_MASK_NAV_8814B (109 & CPU_OPT_WIDTH) +#define BIT_MASK_PRI_MASK_NAV_8814B 0xff +#define BIT_PRI_MASK_NAV_8814B(x) (((x) & BIT_MASK_PRI_MASK_NAV_8814B) << BIT_SHIFT_PRI_MASK_NAV_8814B) +#define BIT_GET_PRI_MASK_NAV_8814B(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8814B) & BIT_MASK_PRI_MASK_NAV_8814B) + + +#define BIT_PRI_MASK_CCK_8814B BIT(108) +#define BIT_PRI_MASK_OFDM_8814B BIT(107) +#define BIT_PRI_MASK_RTY_8814B BIT(106) + +#define BIT_SHIFT_PRI_MASK_NUM_8814B (102 & CPU_OPT_WIDTH) +#define BIT_MASK_PRI_MASK_NUM_8814B 0xf +#define BIT_PRI_MASK_NUM_8814B(x) (((x) & BIT_MASK_PRI_MASK_NUM_8814B) << BIT_SHIFT_PRI_MASK_NUM_8814B) +#define BIT_GET_PRI_MASK_NUM_8814B(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8814B) & BIT_MASK_PRI_MASK_NUM_8814B) + + + +#define BIT_SHIFT_PRI_MASK_TYPE_8814B (98 & CPU_OPT_WIDTH) +#define BIT_MASK_PRI_MASK_TYPE_8814B 0xf +#define BIT_PRI_MASK_TYPE_8814B(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8814B) << BIT_SHIFT_PRI_MASK_TYPE_8814B) +#define BIT_GET_PRI_MASK_TYPE_8814B(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8814B) & BIT_MASK_PRI_MASK_TYPE_8814B) + + +#define BIT_OOB_8814B BIT(97) +#define BIT_ANT_SEL_8814B BIT(96) + +#define BIT_SHIFT_BREAK_TABLE_2_8814B (80 & CPU_OPT_WIDTH) +#define BIT_MASK_BREAK_TABLE_2_8814B 0xffff +#define BIT_BREAK_TABLE_2_8814B(x) (((x) & BIT_MASK_BREAK_TABLE_2_8814B) << BIT_SHIFT_BREAK_TABLE_2_8814B) +#define BIT_GET_BREAK_TABLE_2_8814B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8814B) & BIT_MASK_BREAK_TABLE_2_8814B) + + + +#define BIT_SHIFT_BREAK_TABLE_1_8814B (64 & CPU_OPT_WIDTH) +#define BIT_MASK_BREAK_TABLE_1_8814B 0xffff +#define BIT_BREAK_TABLE_1_8814B(x) (((x) & BIT_MASK_BREAK_TABLE_1_8814B) << BIT_SHIFT_BREAK_TABLE_1_8814B) +#define BIT_GET_BREAK_TABLE_1_8814B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8814B) & BIT_MASK_BREAK_TABLE_1_8814B) + + + +#define BIT_SHIFT_COEX_TABLE_2_8814B (32 & CPU_OPT_WIDTH) +#define BIT_MASK_COEX_TABLE_2_8814B 0xffffffffL +#define BIT_COEX_TABLE_2_8814B(x) (((x) & BIT_MASK_COEX_TABLE_2_8814B) << BIT_SHIFT_COEX_TABLE_2_8814B) +#define BIT_GET_COEX_TABLE_2_8814B(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8814B) & BIT_MASK_COEX_TABLE_2_8814B) + + + +#define BIT_SHIFT_COEX_TABLE_1_8814B 0 +#define BIT_MASK_COEX_TABLE_1_8814B 0xffffffffL +#define BIT_COEX_TABLE_1_8814B(x) (((x) & BIT_MASK_COEX_TABLE_1_8814B) << BIT_SHIFT_COEX_TABLE_1_8814B) +#define BIT_GET_COEX_TABLE_1_8814B(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8814B) & BIT_MASK_COEX_TABLE_1_8814B) + + + +/* 2 REG_RXCMD_0_8814B */ +#define BIT_RXCMD_EN_8814B BIT(31) + +#define BIT_SHIFT_RXCMD_INFO_8814B 0 +#define BIT_MASK_RXCMD_INFO_8814B 0x7fffffffL +#define BIT_RXCMD_INFO_8814B(x) (((x) & BIT_MASK_RXCMD_INFO_8814B) << BIT_SHIFT_RXCMD_INFO_8814B) +#define BIT_GET_RXCMD_INFO_8814B(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8814B) & BIT_MASK_RXCMD_INFO_8814B) + + + +/* 2 REG_RXCMD_1_8814B */ + +#define BIT_SHIFT_RXCMD_PRD_8814B 0 +#define BIT_MASK_RXCMD_PRD_8814B 0xffff +#define BIT_RXCMD_PRD_8814B(x) (((x) & BIT_MASK_RXCMD_PRD_8814B) << BIT_SHIFT_RXCMD_PRD_8814B) +#define BIT_GET_RXCMD_PRD_8814B(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8814B) & BIT_MASK_RXCMD_PRD_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_WMAC_RESP_TXINFO_8814B (RESPONSE TXINFO REGISTER) */ + +#define BIT_SHIFT_WMAC_RESP_MFB_8814B 25 +#define BIT_MASK_WMAC_RESP_MFB_8814B 0x7f +#define BIT_WMAC_RESP_MFB_8814B(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8814B) << BIT_SHIFT_WMAC_RESP_MFB_8814B) +#define BIT_GET_WMAC_RESP_MFB_8814B(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8814B) & BIT_MASK_WMAC_RESP_MFB_8814B) + + + +#define BIT_SHIFT_WMAC_ANTINF_SEL_8814B 23 +#define BIT_MASK_WMAC_ANTINF_SEL_8814B 0x3 +#define BIT_WMAC_ANTINF_SEL_8814B(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8814B) << BIT_SHIFT_WMAC_ANTINF_SEL_8814B) +#define BIT_GET_WMAC_ANTINF_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8814B) & BIT_MASK_WMAC_ANTINF_SEL_8814B) + + + +#define BIT_SHIFT_WMAC_ANTSEL_SEL_8814B 21 +#define BIT_MASK_WMAC_ANTSEL_SEL_8814B 0x3 +#define BIT_WMAC_ANTSEL_SEL_8814B(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8814B) << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) +#define BIT_GET_WMAC_ANTSEL_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) & BIT_MASK_WMAC_ANTSEL_SEL_8814B) + + + +#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8814B 18 +#define BIT_MASK_R_WMAC_RESP_TXPOWER_8814B 0x7 +#define BIT_R_WMAC_RESP_TXPOWER_8814B(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8814B) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8814B) +#define BIT_GET_R_WMAC_RESP_TXPOWER_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8814B) & BIT_MASK_R_WMAC_RESP_TXPOWER_8814B) + + + +#define BIT_SHIFT_WMAC_RESP_TXANT_8814B 0 +#define BIT_MASK_WMAC_RESP_TXANT_8814B 0x3ffff +#define BIT_WMAC_RESP_TXANT_8814B(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8814B) << BIT_SHIFT_WMAC_RESP_TXANT_8814B) +#define BIT_GET_WMAC_RESP_TXANT_8814B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8814B) & BIT_MASK_WMAC_RESP_TXANT_8814B) + + + +/* 2 REG_BBPSF_CTRL_8814B */ +#define BIT_CTL_IDLE_CLR_CSI_RPT_8814B BIT(31) +#define BIT_WMAC_USE_NDPARATE_8814B BIT(30) + +#define BIT_SHIFT_WMAC_CSI_RATE_8814B 24 +#define BIT_MASK_WMAC_CSI_RATE_8814B 0x3f +#define BIT_WMAC_CSI_RATE_8814B(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8814B) << BIT_SHIFT_WMAC_CSI_RATE_8814B) +#define BIT_GET_WMAC_CSI_RATE_8814B(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8814B) & BIT_MASK_WMAC_CSI_RATE_8814B) + + + +#define BIT_SHIFT_WMAC_RESP_TXRATE_8814B 16 +#define BIT_MASK_WMAC_RESP_TXRATE_8814B 0xff +#define BIT_WMAC_RESP_TXRATE_8814B(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8814B) << BIT_SHIFT_WMAC_RESP_TXRATE_8814B) +#define BIT_GET_WMAC_RESP_TXRATE_8814B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8814B) & BIT_MASK_WMAC_RESP_TXRATE_8814B) + + +#define BIT_CSI_FORCE_RATE_EN_8814B BIT(15) + +#define BIT_SHIFT_CSI_RSC_8814B 13 +#define BIT_MASK_CSI_RSC_8814B 0x3 +#define BIT_CSI_RSC_8814B(x) (((x) & BIT_MASK_CSI_RSC_8814B) << BIT_SHIFT_CSI_RSC_8814B) +#define BIT_GET_CSI_RSC_8814B(x) (((x) >> BIT_SHIFT_CSI_RSC_8814B) & BIT_MASK_CSI_RSC_8814B) + + +#define BIT_CSI_GID_SEL_8814B BIT(12) +#define BIT_RDCSIMD_FLAG_TRIG_SEL_8814B BIT(11) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS_8814B BIT(10) +#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8814B BIT(9) +#define BIT_RDCSI_EMPTY_APPZERO_8814B BIT(8) +#define BIT_BBPSF_MPDUCHKEN_8814B BIT(5) +#define BIT_BBPSF_MHCHKEN_8814B BIT(4) +#define BIT_BBPSF_ERRCHKEN_8814B BIT(3) + +#define BIT_SHIFT_BBPSF_ERRTHR_8814B 0 +#define BIT_MASK_BBPSF_ERRTHR_8814B 0x7 +#define BIT_BBPSF_ERRTHR_8814B(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8814B) << BIT_SHIFT_BBPSF_ERRTHR_8814B) +#define BIT_GET_BBPSF_ERRTHR_8814B(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8814B) & BIT_MASK_BBPSF_ERRTHR_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_P2P_RX_BCN_NOA_8814B (P2P RX BEACON NOA REGISTER) */ +#define BIT_NOA_PARSER_EN_8814B BIT(15) +#define BIT_BSSID_SEL_8814B BIT(14) + +#define BIT_SHIFT_P2P_OUI_TYPE_8814B 0 +#define BIT_MASK_P2P_OUI_TYPE_8814B 0xff +#define BIT_P2P_OUI_TYPE_8814B(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8814B) << BIT_SHIFT_P2P_OUI_TYPE_8814B) +#define BIT_GET_P2P_OUI_TYPE_8814B(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8814B) & BIT_MASK_P2P_OUI_TYPE_8814B) + + + +/* 2 REG_ASSOCIATED_BFMER0_INFO_8814B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B (48 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_TXCSI_AID0_8814B 0x1ff +#define BIT_R_WMAC_TXCSI_AID0_8814B(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8814B) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) +#define BIT_GET_R_WMAC_TXCSI_AID0_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) & BIT_MASK_R_WMAC_TXCSI_AID0_8814B) + + + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8814B 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8814B 0xffffffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0_8814B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8814B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8814B) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8814B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8814B) + + + +/* 2 REG_ASSOCIATED_BFMER1_INFO_8814B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B (48 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_TXCSI_AID1_8814B 0x1ff +#define BIT_R_WMAC_TXCSI_AID1_8814B(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8814B) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) +#define BIT_GET_R_WMAC_TXCSI_AID1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) & BIT_MASK_R_WMAC_TXCSI_AID1_8814B) + + + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8814B 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8814B 0xffffffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1_8814B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8814B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8814B) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8814B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_TX_CSI_RPT_PARAM_BW20_8814B (TX CSI REPORT PARAMETER REGISTER) */ + +#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B 16 +#define BIT_MASK_R_WMAC_BFINFO_20M_1_8814B 0xfff +#define BIT_R_WMAC_BFINFO_20M_1_8814B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8814B) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) & BIT_MASK_R_WMAC_BFINFO_20M_1_8814B) + + + +#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B 0 +#define BIT_MASK_R_WMAC_BFINFO_20M_0_8814B 0xfff +#define BIT_R_WMAC_BFINFO_20M_0_8814B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8814B) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) & BIT_MASK_R_WMAC_BFINFO_20M_0_8814B) + + + +/* 2 REG_TX_CSI_RPT_PARAM_BW40_8814B (TX CSI REPORT PARAMETER_BW40 REGISTER) */ + +#define BIT_SHIFT_WMAC_RESP_ANTCD_8814B 0 +#define BIT_MASK_WMAC_RESP_ANTCD_8814B 0xf +#define BIT_WMAC_RESP_ANTCD_8814B(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8814B) << BIT_SHIFT_WMAC_RESP_ANTCD_8814B) +#define BIT_GET_WMAC_RESP_ANTCD_8814B(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8814B) & BIT_MASK_WMAC_RESP_ANTCD_8814B) + + + +/* 2 REG_TX_CSI_RPT_PARAM_BW80_8814B (TX CSI REPORT PARAMETER_BW80 REGISTER) */ + +/* 2 REG_BCN_PSR_RPT2_8814B (BEACON PARSER REPORT REGISTER2) */ + +#define BIT_SHIFT_DTIM_CNT2_8814B 24 +#define BIT_MASK_DTIM_CNT2_8814B 0xff +#define BIT_DTIM_CNT2_8814B(x) (((x) & BIT_MASK_DTIM_CNT2_8814B) << BIT_SHIFT_DTIM_CNT2_8814B) +#define BIT_GET_DTIM_CNT2_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8814B) & BIT_MASK_DTIM_CNT2_8814B) + + + +#define BIT_SHIFT_DTIM_PERIOD2_8814B 16 +#define BIT_MASK_DTIM_PERIOD2_8814B 0xff +#define BIT_DTIM_PERIOD2_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD2_8814B) << BIT_SHIFT_DTIM_PERIOD2_8814B) +#define BIT_GET_DTIM_PERIOD2_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8814B) & BIT_MASK_DTIM_PERIOD2_8814B) + + +#define BIT_DTIM2_8814B BIT(15) +#define BIT_TIM2_8814B BIT(14) + +#define BIT_SHIFT_PS_AID_2_8814B 0 +#define BIT_MASK_PS_AID_2_8814B 0x7ff +#define BIT_PS_AID_2_8814B(x) (((x) & BIT_MASK_PS_AID_2_8814B) << BIT_SHIFT_PS_AID_2_8814B) +#define BIT_GET_PS_AID_2_8814B(x) (((x) >> BIT_SHIFT_PS_AID_2_8814B) & BIT_MASK_PS_AID_2_8814B) + + + +/* 2 REG_BCN_PSR_RPT3_8814B (BEACON PARSER REPORT REGISTER3) */ + +#define BIT_SHIFT_DTIM_CNT3_8814B 24 +#define BIT_MASK_DTIM_CNT3_8814B 0xff +#define BIT_DTIM_CNT3_8814B(x) (((x) & BIT_MASK_DTIM_CNT3_8814B) << BIT_SHIFT_DTIM_CNT3_8814B) +#define BIT_GET_DTIM_CNT3_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8814B) & BIT_MASK_DTIM_CNT3_8814B) + + + +#define BIT_SHIFT_DTIM_PERIOD3_8814B 16 +#define BIT_MASK_DTIM_PERIOD3_8814B 0xff +#define BIT_DTIM_PERIOD3_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD3_8814B) << BIT_SHIFT_DTIM_PERIOD3_8814B) +#define BIT_GET_DTIM_PERIOD3_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8814B) & BIT_MASK_DTIM_PERIOD3_8814B) + + +#define BIT_DTIM3_8814B BIT(15) +#define BIT_TIM3_8814B BIT(14) + +#define BIT_SHIFT_PS_AID_3_8814B 0 +#define BIT_MASK_PS_AID_3_8814B 0x7ff +#define BIT_PS_AID_3_8814B(x) (((x) & BIT_MASK_PS_AID_3_8814B) << BIT_SHIFT_PS_AID_3_8814B) +#define BIT_GET_PS_AID_3_8814B(x) (((x) >> BIT_SHIFT_PS_AID_3_8814B) & BIT_MASK_PS_AID_3_8814B) + + + +/* 2 REG_BCN_PSR_RPT4_8814B (BEACON PARSER REPORT REGISTER4) */ + +#define BIT_SHIFT_DTIM_CNT4_8814B 24 +#define BIT_MASK_DTIM_CNT4_8814B 0xff +#define BIT_DTIM_CNT4_8814B(x) (((x) & BIT_MASK_DTIM_CNT4_8814B) << BIT_SHIFT_DTIM_CNT4_8814B) +#define BIT_GET_DTIM_CNT4_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8814B) & BIT_MASK_DTIM_CNT4_8814B) + + + +#define BIT_SHIFT_DTIM_PERIOD4_8814B 16 +#define BIT_MASK_DTIM_PERIOD4_8814B 0xff +#define BIT_DTIM_PERIOD4_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD4_8814B) << BIT_SHIFT_DTIM_PERIOD4_8814B) +#define BIT_GET_DTIM_PERIOD4_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8814B) & BIT_MASK_DTIM_PERIOD4_8814B) + + +#define BIT_DTIM4_8814B BIT(15) +#define BIT_TIM4_8814B BIT(14) + +#define BIT_SHIFT_PS_AID_4_8814B 0 +#define BIT_MASK_PS_AID_4_8814B 0x7ff +#define BIT_PS_AID_4_8814B(x) (((x) & BIT_MASK_PS_AID_4_8814B) << BIT_SHIFT_PS_AID_4_8814B) +#define BIT_GET_PS_AID_4_8814B(x) (((x) >> BIT_SHIFT_PS_AID_4_8814B) & BIT_MASK_PS_AID_4_8814B) + + + +/* 2 REG_A1_ADDR_MASK_8814B (A1 ADDR MASK REGISTER) */ + +#define BIT_SHIFT_A1_ADDR_MASK_8814B 0 +#define BIT_MASK_A1_ADDR_MASK_8814B 0xffffffffL +#define BIT_A1_ADDR_MASK_8814B(x) (((x) & BIT_MASK_A1_ADDR_MASK_8814B) << BIT_SHIFT_A1_ADDR_MASK_8814B) +#define BIT_GET_A1_ADDR_MASK_8814B(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8814B) & BIT_MASK_A1_ADDR_MASK_8814B) + + + +/* 2 REG_MACID2_8814B (MAC ID2 REGISTER) */ + +#define BIT_SHIFT_MACID2_8814B 0 +#define BIT_MASK_MACID2_8814B 0xffffffffffffL +#define BIT_MACID2_8814B(x) (((x) & BIT_MASK_MACID2_8814B) << BIT_SHIFT_MACID2_8814B) +#define BIT_GET_MACID2_8814B(x) (((x) >> BIT_SHIFT_MACID2_8814B) & BIT_MASK_MACID2_8814B) + + + +/* 2 REG_BSSID2_8814B (BSSID2 REGISTER) */ + +#define BIT_SHIFT_BSSID2_8814B 0 +#define BIT_MASK_BSSID2_8814B 0xffffffffffffL +#define BIT_BSSID2_8814B(x) (((x) & BIT_MASK_BSSID2_8814B) << BIT_SHIFT_BSSID2_8814B) +#define BIT_GET_BSSID2_8814B(x) (((x) >> BIT_SHIFT_BSSID2_8814B) & BIT_MASK_BSSID2_8814B) + + + +/* 2 REG_MACID3_8814B (MAC ID3 REGISTER) */ + +#define BIT_SHIFT_MACID3_8814B 0 +#define BIT_MASK_MACID3_8814B 0xffffffffffffL +#define BIT_MACID3_8814B(x) (((x) & BIT_MASK_MACID3_8814B) << BIT_SHIFT_MACID3_8814B) +#define BIT_GET_MACID3_8814B(x) (((x) >> BIT_SHIFT_MACID3_8814B) & BIT_MASK_MACID3_8814B) + + + +/* 2 REG_BSSID3_8814B (BSSID3 REGISTER) */ + +#define BIT_SHIFT_BSSID3_8814B 0 +#define BIT_MASK_BSSID3_8814B 0xffffffffffffL +#define BIT_BSSID3_8814B(x) (((x) & BIT_MASK_BSSID3_8814B) << BIT_SHIFT_BSSID3_8814B) +#define BIT_GET_BSSID3_8814B(x) (((x) >> BIT_SHIFT_BSSID3_8814B) & BIT_MASK_BSSID3_8814B) + + + +/* 2 REG_MACID4_8814B (MAC ID4 REGISTER) */ + +#define BIT_SHIFT_MACID4_8814B 0 +#define BIT_MASK_MACID4_8814B 0xffffffffffffL +#define BIT_MACID4_8814B(x) (((x) & BIT_MASK_MACID4_8814B) << BIT_SHIFT_MACID4_8814B) +#define BIT_GET_MACID4_8814B(x) (((x) >> BIT_SHIFT_MACID4_8814B) & BIT_MASK_MACID4_8814B) + + + +/* 2 REG_BSSID4_8814B (BSSID4 REGISTER) */ + +#define BIT_SHIFT_BSSID4_8814B 0 +#define BIT_MASK_BSSID4_8814B 0xffffffffffffL +#define BIT_BSSID4_8814B(x) (((x) & BIT_MASK_BSSID4_8814B) << BIT_SHIFT_BSSID4_8814B) +#define BIT_GET_BSSID4_8814B(x) (((x) >> BIT_SHIFT_BSSID4_8814B) & BIT_MASK_BSSID4_8814B) + + + +/* 2 REG_NOA_REPORT_8814B */ + +/* 2 REG_PWRBIT_SETTING_8814B */ +#define BIT_CLI3_PWRBIT_OW_EN_8814B BIT(7) +#define BIT_CLI3_PWR_ST_8814B BIT(6) +#define BIT_CLI2_PWRBIT_OW_EN_8814B BIT(5) +#define BIT_CLI2_PWR_ST_8814B BIT(4) +#define BIT_CLI1_PWRBIT_OW_EN_8814B BIT(3) +#define BIT_CLI1_PWR_ST_8814B BIT(2) +#define BIT_CLI0_PWRBIT_OW_EN_8814B BIT(1) +#define BIT_CLI0_PWR_ST_8814B BIT(0) + +/* 2 REG_WMAC_MU_BF_OPTION_8814B */ +#define BIT_WMAC_RESP_NONSTA1_DIS_8814B BIT(7) +#define BIT_WMAC_TXMU_ACKPOLICY_EN_8814B BIT(6) + +#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B 4 +#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B 0x3 +#define BIT_WMAC_TXMU_ACKPOLICY_8814B(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8814B(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B) + + + +#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B 1 +#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B 0x7 +#define BIT_WMAC_MU_BFEE_PORT_SEL_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B) + + +#define BIT_WMAC_MU_BFEE_DIS_8814B BIT(0) + +/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8814B */ + +#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B 0 +#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B 0xff +#define BIT_WMAC_PAUSE_BB_CLR_TH_8814B(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8814B(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B) + + + +/* 2 REG_WMAC_MU_ARB_8814B */ +#define BIT_WMAC_ARB_HW_ADAPT_EN_8814B BIT(7) +#define BIT_WMAC_ARB_SW_EN_8814B BIT(6) + +#define BIT_SHIFT_WMAC_ARB_SW_STATE_8814B 0 +#define BIT_MASK_WMAC_ARB_SW_STATE_8814B 0x3f +#define BIT_WMAC_ARB_SW_STATE_8814B(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8814B) << BIT_SHIFT_WMAC_ARB_SW_STATE_8814B) +#define BIT_GET_WMAC_ARB_SW_STATE_8814B(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8814B) & BIT_MASK_WMAC_ARB_SW_STATE_8814B) + + + +/* 2 REG_WMAC_MU_OPTION_8814B */ + +#define BIT_SHIFT_WMAC_MU_DBGSEL_8814B 5 +#define BIT_MASK_WMAC_MU_DBGSEL_8814B 0x3 +#define BIT_WMAC_MU_DBGSEL_8814B(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8814B) << BIT_SHIFT_WMAC_MU_DBGSEL_8814B) +#define BIT_GET_WMAC_MU_DBGSEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8814B) & BIT_MASK_WMAC_MU_DBGSEL_8814B) + + + +#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8814B 0 +#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8814B 0x1f +#define BIT_WMAC_MU_CPRD_TIMEOUT_8814B(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8814B) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8814B) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8814B) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8814B) + + + +/* 2 REG_WMAC_MU_BF_CTL_8814B */ +#define BIT_WMAC_INVLD_BFPRT_CHK_8814B BIT(15) +#define BIT_WMAC_RETXBFRPTSEQ_UPD_8814B BIT(14) + +#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B 12 +#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B 0x3 +#define BIT_WMAC_MU_BFRPTSEG_SEL_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B) + + + +#define BIT_SHIFT_WMAC_MU_BF_MYAID_8814B 0 +#define BIT_MASK_WMAC_MU_BF_MYAID_8814B 0xfff +#define BIT_WMAC_MU_BF_MYAID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8814B) << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) +#define BIT_GET_WMAC_MU_BF_MYAID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) & BIT_MASK_WMAC_MU_BF_MYAID_8814B) + + + +/* 2 REG_WMAC_MU_BIT_BFRPT_PARA_8814B */ + +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8814B 12 +#define BIT_MASK_BFRPT_PARA_USERID_SEL_8814B 0x7 +#define BIT_BFRPT_PARA_USERID_SEL_8814B(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8814B) << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8814B) +#define BIT_GET_BFRPT_PARA_USERID_SEL_8814B(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8814B) & BIT_MASK_BFRPT_PARA_USERID_SEL_8814B) + + + +#define BIT_SHIFT_BFRPT_PARA_8814B 0 +#define BIT_MASK_BFRPT_PARA_8814B 0xfff +#define BIT_BFRPT_PARA_8814B(x) (((x) & BIT_MASK_BFRPT_PARA_8814B) << BIT_SHIFT_BFRPT_PARA_8814B) +#define BIT_GET_BFRPT_PARA_8814B(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8814B) & BIT_MASK_BFRPT_PARA_8814B) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B */ +#define BIT_STATUS_BFEE2_8814B BIT(10) +#define BIT_WMAC_MU_BFEE2_EN_8814B BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B 0 +#define BIT_MASK_WMAC_MU_BFEE2_AID_8814B 0x1ff +#define BIT_WMAC_MU_BFEE2_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) +#define BIT_GET_WMAC_MU_BFEE2_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) & BIT_MASK_WMAC_MU_BFEE2_AID_8814B) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B */ +#define BIT_STATUS_BFEE3_8814B BIT(10) +#define BIT_WMAC_MU_BFEE3_EN_8814B BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B 0 +#define BIT_MASK_WMAC_MU_BFEE3_AID_8814B 0x1ff +#define BIT_WMAC_MU_BFEE3_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) +#define BIT_GET_WMAC_MU_BFEE3_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) & BIT_MASK_WMAC_MU_BFEE3_AID_8814B) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B */ +#define BIT_STATUS_BFEE4_8814B BIT(10) +#define BIT_WMAC_MU_BFEE4_EN_8814B BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B 0 +#define BIT_MASK_WMAC_MU_BFEE4_AID_8814B 0x1ff +#define BIT_WMAC_MU_BFEE4_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) +#define BIT_GET_WMAC_MU_BFEE4_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) & BIT_MASK_WMAC_MU_BFEE4_AID_8814B) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8814B */ +#define BIT_BIT_STATUS_BFEE5_8814B BIT(10) +#define BIT_WMAC_MU_BFEE5_EN_8814B BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B 0 +#define BIT_MASK_WMAC_MU_BFEE5_AID_8814B 0x1ff +#define BIT_WMAC_MU_BFEE5_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) +#define BIT_GET_WMAC_MU_BFEE5_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) & BIT_MASK_WMAC_MU_BFEE5_AID_8814B) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8814B */ +#define BIT_STATUS_BFEE6_8814B BIT(10) +#define BIT_WMAC_MU_BFEE6_EN_8814B BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B 0 +#define BIT_MASK_WMAC_MU_BFEE6_AID_8814B 0x1ff +#define BIT_WMAC_MU_BFEE6_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) +#define BIT_GET_WMAC_MU_BFEE6_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) & BIT_MASK_WMAC_MU_BFEE6_AID_8814B) + + + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B */ +#define BIT_BIT_STATUS_BFEE4_8814B BIT(10) +#define BIT_WMAC_MU_BFEE7_EN_8814B BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B 0 +#define BIT_MASK_WMAC_MU_BFEE7_AID_8814B 0x1ff +#define BIT_WMAC_MU_BFEE7_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) +#define BIT_GET_WMAC_MU_BFEE7_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) & BIT_MASK_WMAC_MU_BFEE7_AID_8814B) + + + +/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8814B */ +#define BIT_RST_ALL_COUNTER_8814B BIT(31) + +#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B 16 +#define BIT_MASK_ABORT_RX_VBON_COUNTER_8814B 0xff +#define BIT_ABORT_RX_VBON_COUNTER_8814B(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8814B) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8814B(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) & BIT_MASK_ABORT_RX_VBON_COUNTER_8814B) + + + +#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B 8 +#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B 0xff +#define BIT_ABORT_RX_RDRDY_COUNTER_8814B(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8814B(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B) + + + +#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B 0 +#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B 0xff +#define BIT_VBON_EARLY_FALLING_COUNTER_8814B(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8814B(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B) + + + +/* 2 REG_WMAC_PLCP_MONITOR_8814B */ +#define BIT_WMAC_PLCP_TRX_SEL_8814B BIT(31) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B 28 +#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B 0x7 +#define BIT_WMAC_PLCP_RDSIG_SEL_8814B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B) + + + +#define BIT_SHIFT_WMAC_RATE_IDX_8814B 24 +#define BIT_MASK_WMAC_RATE_IDX_8814B 0xf +#define BIT_WMAC_RATE_IDX_8814B(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8814B) << BIT_SHIFT_WMAC_RATE_IDX_8814B) +#define BIT_GET_WMAC_RATE_IDX_8814B(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8814B) & BIT_MASK_WMAC_RATE_IDX_8814B) + + + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8814B 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8814B 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8814B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) +#define BIT_GET_WMAC_PLCP_RDSIG_8814B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) + + + +/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8814B */ +#define BIT_WMAC_MUTX_IDX_8814B BIT(24) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8814B 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8814B 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8814B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) +#define BIT_GET_WMAC_PLCP_RDSIG_8814B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) + + + +/* 2 REG_TRANSMIT_ADDRSS_0_8814B (TA0 REGISTER) */ + +#define BIT_SHIFT_TA0_8814B 0 +#define BIT_MASK_TA0_8814B 0xffffffffffffL +#define BIT_TA0_8814B(x) (((x) & BIT_MASK_TA0_8814B) << BIT_SHIFT_TA0_8814B) +#define BIT_GET_TA0_8814B(x) (((x) >> BIT_SHIFT_TA0_8814B) & BIT_MASK_TA0_8814B) + + + +/* 2 REG_TRANSMIT_ADDRSS_1_8814B (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_8814B 0 +#define BIT_MASK_TA1_8814B 0xffffffffffffL +#define BIT_TA1_8814B(x) (((x) & BIT_MASK_TA1_8814B) << BIT_SHIFT_TA1_8814B) +#define BIT_GET_TA1_8814B(x) (((x) >> BIT_SHIFT_TA1_8814B) & BIT_MASK_TA1_8814B) + + + +/* 2 REG_TRANSMIT_ADDRSS_2_8814B (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_8814B 0 +#define BIT_MASK_TA2_8814B 0xffffffffffffL +#define BIT_TA2_8814B(x) (((x) & BIT_MASK_TA2_8814B) << BIT_SHIFT_TA2_8814B) +#define BIT_GET_TA2_8814B(x) (((x) >> BIT_SHIFT_TA2_8814B) & BIT_MASK_TA2_8814B) + + + +/* 2 REG_TRANSMIT_ADDRSS_3_8814B (TA3 REGISTER) */ + +#define BIT_SHIFT_TA3_8814B 0 +#define BIT_MASK_TA3_8814B 0xffffffffffffL +#define BIT_TA3_8814B(x) (((x) & BIT_MASK_TA3_8814B) << BIT_SHIFT_TA3_8814B) +#define BIT_GET_TA3_8814B(x) (((x) >> BIT_SHIFT_TA3_8814B) & BIT_MASK_TA3_8814B) + + + +/* 2 REG_TRANSMIT_ADDRSS_4_8814B (TA4 REGISTER) */ + +#define BIT_SHIFT_TA4_8814B 0 +#define BIT_MASK_TA4_8814B 0xffffffffffffL +#define BIT_TA4_8814B(x) (((x) & BIT_MASK_TA4_8814B) << BIT_SHIFT_TA4_8814B) +#define BIT_GET_TA4_8814B(x) (((x) >> BIT_SHIFT_TA4_8814B) & BIT_MASK_TA4_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_MACID1_8814B */ + +#define BIT_SHIFT_MACID1_0_8814B 0 +#define BIT_MASK_MACID1_0_8814B 0xffffffffL +#define BIT_MACID1_0_8814B(x) (((x) & BIT_MASK_MACID1_0_8814B) << BIT_SHIFT_MACID1_0_8814B) +#define BIT_GET_MACID1_0_8814B(x) (((x) >> BIT_SHIFT_MACID1_0_8814B) & BIT_MASK_MACID1_0_8814B) + + + +/* 2 REG_MACID1_1_8814B */ + +#define BIT_SHIFT_MACID1_1_8814B 0 +#define BIT_MASK_MACID1_1_8814B 0xffff +#define BIT_MACID1_1_8814B(x) (((x) & BIT_MASK_MACID1_1_8814B) << BIT_SHIFT_MACID1_1_8814B) +#define BIT_GET_MACID1_1_8814B(x) (((x) >> BIT_SHIFT_MACID1_1_8814B) & BIT_MASK_MACID1_1_8814B) + + + +/* 2 REG_BSSID1_8814B */ + +#define BIT_SHIFT_BSSID1_0_8814B 0 +#define BIT_MASK_BSSID1_0_8814B 0xffffffffL +#define BIT_BSSID1_0_8814B(x) (((x) & BIT_MASK_BSSID1_0_8814B) << BIT_SHIFT_BSSID1_0_8814B) +#define BIT_GET_BSSID1_0_8814B(x) (((x) >> BIT_SHIFT_BSSID1_0_8814B) & BIT_MASK_BSSID1_0_8814B) + + + +/* 2 REG_BSSID1_1_8814B */ + +#define BIT_SHIFT_BSSID1_1_8814B 0 +#define BIT_MASK_BSSID1_1_8814B 0xffff +#define BIT_BSSID1_1_8814B(x) (((x) & BIT_MASK_BSSID1_1_8814B) << BIT_SHIFT_BSSID1_1_8814B) +#define BIT_GET_BSSID1_1_8814B(x) (((x) >> BIT_SHIFT_BSSID1_1_8814B) & BIT_MASK_BSSID1_1_8814B) + + + +/* 2 REG_BCN_PSR_RPT1_8814B */ + +#define BIT_SHIFT_DTIM_CNT1_8814B 24 +#define BIT_MASK_DTIM_CNT1_8814B 0xff +#define BIT_DTIM_CNT1_8814B(x) (((x) & BIT_MASK_DTIM_CNT1_8814B) << BIT_SHIFT_DTIM_CNT1_8814B) +#define BIT_GET_DTIM_CNT1_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8814B) & BIT_MASK_DTIM_CNT1_8814B) + + + +#define BIT_SHIFT_DTIM_PERIOD1_8814B 16 +#define BIT_MASK_DTIM_PERIOD1_8814B 0xff +#define BIT_DTIM_PERIOD1_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD1_8814B) << BIT_SHIFT_DTIM_PERIOD1_8814B) +#define BIT_GET_DTIM_PERIOD1_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8814B) & BIT_MASK_DTIM_PERIOD1_8814B) + + +#define BIT_DTIM1_8814B BIT(15) +#define BIT_TIM1_8814B BIT(14) + +#define BIT_SHIFT_PS_AID_1_8814B 0 +#define BIT_MASK_PS_AID_1_8814B 0x7ff +#define BIT_PS_AID_1_8814B(x) (((x) & BIT_MASK_PS_AID_1_8814B) << BIT_SHIFT_PS_AID_1_8814B) +#define BIT_GET_PS_AID_1_8814B(x) (((x) >> BIT_SHIFT_PS_AID_1_8814B) & BIT_MASK_PS_AID_1_8814B) + + + +/* 2 REG_ASSOCIATED_BFMEE_SEL_8814B */ +#define BIT_TXUSER_ID1_8814B BIT(25) + +#define BIT_SHIFT_AID1_8814B 16 +#define BIT_MASK_AID1_8814B 0x1ff +#define BIT_AID1_8814B(x) (((x) & BIT_MASK_AID1_8814B) << BIT_SHIFT_AID1_8814B) +#define BIT_GET_AID1_8814B(x) (((x) >> BIT_SHIFT_AID1_8814B) & BIT_MASK_AID1_8814B) + + +#define BIT_TXUSER_ID0_8814B BIT(9) + +#define BIT_SHIFT_AID0_8814B 0 +#define BIT_MASK_AID0_8814B 0x1ff +#define BIT_AID0_8814B(x) (((x) & BIT_MASK_AID0_8814B) << BIT_SHIFT_AID0_8814B) +#define BIT_GET_AID0_8814B(x) (((x) >> BIT_SHIFT_AID0_8814B) & BIT_MASK_AID0_8814B) + + + +/* 2 REG_SND_PTCL_CTRL_8814B */ + +#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B 24 +#define BIT_MASK_NDP_RX_STANDBY_TIMER_8814B 0xff +#define BIT_NDP_RX_STANDBY_TIMER_8814B(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8814B) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8814B(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) & BIT_MASK_NDP_RX_STANDBY_TIMER_8814B) + + + +#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B 16 +#define BIT_MASK_CSI_RPT_OFFSET_HT_8814B 0xff +#define BIT_CSI_RPT_OFFSET_HT_8814B(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8814B) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) +#define BIT_GET_CSI_RPT_OFFSET_HT_8814B(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) & BIT_MASK_CSI_RPT_OFFSET_HT_8814B) + + + +#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8814B 8 +#define BIT_MASK_R_WMAC_VHT_CATEGORY_8814B 0xff +#define BIT_R_WMAC_VHT_CATEGORY_8814B(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8814B) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8814B) +#define BIT_GET_R_WMAC_VHT_CATEGORY_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8814B) & BIT_MASK_R_WMAC_VHT_CATEGORY_8814B) + + +#define BIT_R_WMAC_USE_NSTS_8814B BIT(7) +#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8814B BIT(6) +#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8814B BIT(5) +#define BIT_R_WMAC_BFPARAM_SEL_8814B BIT(4) +#define BIT_R_WMAC_CSISEQ_SEL_8814B BIT(3) +#define BIT_R_WMAC_CSI_WITHHTC_EN_8814B BIT(2) +#define BIT_R_WMAC_HT_NDPA_EN_8814B BIT(1) +#define BIT_R_WMAC_VHT_NDPA_EN_8814B BIT(0) + +/* 2 REG_RX_CSI_RPT_INFO_8814B */ + +/* 2 REG_NS_ARP_CTRL_8814B */ +#define BIT_R_WMAC_NSARP_RSPEN_8814B BIT(15) +#define BIT_R_WMAC_NSARP_RARP_8814B BIT(9) +#define BIT_R_WMAC_NSARP_RIPV6_8814B BIT(8) + +#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B 6 +#define BIT_MASK_R_WMAC_NSARP_MODEN_8814B 0x3 +#define BIT_R_WMAC_NSARP_MODEN_8814B(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8814B) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) +#define BIT_GET_R_WMAC_NSARP_MODEN_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) & BIT_MASK_R_WMAC_NSARP_MODEN_8814B) + + + +#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B 4 +#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B 0x3 +#define BIT_R_WMAC_NSARP_RSPFTP_8814B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B) + + + +#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B 0 +#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B 0xf +#define BIT_R_WMAC_NSARP_RSPSEC_8814B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B) + + + +/* 2 REG_NS_ARP_INFO_8814B */ +#define BIT_REQ_IS_MCNS_8814B BIT(23) +#define BIT_REQ_IS_UCNS_8814B BIT(22) +#define BIT_REQ_IS_USNS_8814B BIT(21) +#define BIT_REQ_IS_ARP_8814B BIT(20) +#define BIT_EXPRSP_MH_WITHQC_8814B BIT(19) + +#define BIT_SHIFT_EXPRSP_SECTYPE_8814B 16 +#define BIT_MASK_EXPRSP_SECTYPE_8814B 0x7 +#define BIT_EXPRSP_SECTYPE_8814B(x) (((x) & BIT_MASK_EXPRSP_SECTYPE_8814B) << BIT_SHIFT_EXPRSP_SECTYPE_8814B) +#define BIT_GET_EXPRSP_SECTYPE_8814B(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8814B) & BIT_MASK_EXPRSP_SECTYPE_8814B) + + + +#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B 8 +#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B 0xff +#define BIT_EXPRSP_CHKSM_7_TO_0_8814B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) +#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B) + + + +#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B 0 +#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B 0xff +#define BIT_EXPRSP_CHKSM_15_TO_8_8814B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) +#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B) + + + +/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8814B */ + +#define BIT_SHIFT_WMAC_ARPIP_8814B 0 +#define BIT_MASK_WMAC_ARPIP_8814B 0xffffffffL +#define BIT_WMAC_ARPIP_8814B(x) (((x) & BIT_MASK_WMAC_ARPIP_8814B) << BIT_SHIFT_WMAC_ARPIP_8814B) +#define BIT_GET_WMAC_ARPIP_8814B(x) (((x) >> BIT_SHIFT_WMAC_ARPIP_8814B) & BIT_MASK_WMAC_ARPIP_8814B) + + + +/* 2 REG_BEAMFORMING_INFO_NSARP_8814B */ + +#define BIT_SHIFT_BEAMFORMING_INFO_8814B 0 +#define BIT_MASK_BEAMFORMING_INFO_8814B 0xffffffffL +#define BIT_BEAMFORMING_INFO_8814B(x) (((x) & BIT_MASK_BEAMFORMING_INFO_8814B) << BIT_SHIFT_BEAMFORMING_INFO_8814B) +#define BIT_GET_BEAMFORMING_INFO_8814B(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8814B) & BIT_MASK_BEAMFORMING_INFO_8814B) + + + +/* 2 REG_IPV6_8814B */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_0_8814B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B) + + + +/* 2 REG_IPV6_1_8814B */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_1_8814B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B) + + + +/* 2 REG_IPV6_2_8814B */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_2_8814B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B) + + + +/* 2 REG_IPV6_3_8814B */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_3_8814B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8814B */ + +#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B 4 +#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B 0xf +#define BIT_R_WMAC_CTX_SUBTYPE_8814B(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B) + + + +#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B 0 +#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B 0xf +#define BIT_R_WMAC_RTX_SUBTYPE_8814B(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_WMAC_SWAES_CFG_8814B */ + +/* 2 REG_BT_COEX_V2_8814B */ +#define BIT_GNT_BT_POLARITY_8814B BIT(12) +#define BIT_GNT_BT_BYPASS_PRIORITY_8814B BIT(8) + +#define BIT_SHIFT_TIMER_8814B 0 +#define BIT_MASK_TIMER_8814B 0xff +#define BIT_TIMER_8814B(x) (((x) & BIT_MASK_TIMER_8814B) << BIT_SHIFT_TIMER_8814B) +#define BIT_GET_TIMER_8814B(x) (((x) >> BIT_SHIFT_TIMER_8814B) & BIT_MASK_TIMER_8814B) + + + +/* 2 REG_BT_COEX_8814B */ +#define BIT_R_GNT_BT_RFC_SW_8814B BIT(12) +#define BIT_R_GNT_BT_RFC_SW_EN_8814B BIT(11) +#define BIT_R_GNT_BT_BB_SW_8814B BIT(10) +#define BIT_R_GNT_BT_BB_SW_EN_8814B BIT(9) +#define BIT_R_BT_CNT_THREN_8814B BIT(8) + +#define BIT_SHIFT_R_BT_CNT_THR_8814B 0 +#define BIT_MASK_R_BT_CNT_THR_8814B 0xff +#define BIT_R_BT_CNT_THR_8814B(x) (((x) & BIT_MASK_R_BT_CNT_THR_8814B) << BIT_SHIFT_R_BT_CNT_THR_8814B) +#define BIT_GET_R_BT_CNT_THR_8814B(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8814B) & BIT_MASK_R_BT_CNT_THR_8814B) + + + +/* 2 REG_WLAN_ACT_MASK_CTRL_8814B */ + +#define BIT_SHIFT_RXMYRTS_NAV_V1_8814B 8 +#define BIT_MASK_RXMYRTS_NAV_V1_8814B 0xff +#define BIT_RXMYRTS_NAV_V1_8814B(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8814B) << BIT_SHIFT_RXMYRTS_NAV_V1_8814B) +#define BIT_GET_RXMYRTS_NAV_V1_8814B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8814B) & BIT_MASK_RXMYRTS_NAV_V1_8814B) + + + +#define BIT_SHIFT_RTSRST_V1_8814B 0 +#define BIT_MASK_RTSRST_V1_8814B 0xff +#define BIT_RTSRST_V1_8814B(x) (((x) & BIT_MASK_RTSRST_V1_8814B) << BIT_SHIFT_RTSRST_V1_8814B) +#define BIT_GET_RTSRST_V1_8814B(x) (((x) >> BIT_SHIFT_RTSRST_V1_8814B) & BIT_MASK_RTSRST_V1_8814B) + + + +/* 2 REG_WLAN_ACT_MASK_CTRL_1_8814B */ +#define BIT_WLRX_TER_BY_CTL_1_8814B BIT(11) +#define BIT_WLRX_TER_BY_AD_1_8814B BIT(10) +#define BIT_ANT_DIVERSITY_SEL_1_8814B BIT(9) +#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8814B BIT(8) +#define BIT_WLACT_LOW_GNTWL_EN_1_8814B BIT(2) +#define BIT_WLACT_HIGH_GNTBT_EN_1_8814B BIT(1) +#define BIT_NAV_UPPER_1_V1_8814B BIT(0) + +/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8814B */ + +#define BIT_SHIFT_BT_STAT_DELAY_8814B 12 +#define BIT_MASK_BT_STAT_DELAY_8814B 0xf +#define BIT_BT_STAT_DELAY_8814B(x) (((x) & BIT_MASK_BT_STAT_DELAY_8814B) << BIT_SHIFT_BT_STAT_DELAY_8814B) +#define BIT_GET_BT_STAT_DELAY_8814B(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8814B) & BIT_MASK_BT_STAT_DELAY_8814B) + + + +#define BIT_SHIFT_BT_TRX_INIT_DETECT_8814B 8 +#define BIT_MASK_BT_TRX_INIT_DETECT_8814B 0xf +#define BIT_BT_TRX_INIT_DETECT_8814B(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8814B) << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) +#define BIT_GET_BT_TRX_INIT_DETECT_8814B(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) & BIT_MASK_BT_TRX_INIT_DETECT_8814B) + + + +#define BIT_SHIFT_BT_PRI_DETECT_TO_8814B 4 +#define BIT_MASK_BT_PRI_DETECT_TO_8814B 0xf +#define BIT_BT_PRI_DETECT_TO_8814B(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8814B) << BIT_SHIFT_BT_PRI_DETECT_TO_8814B) +#define BIT_GET_BT_PRI_DETECT_TO_8814B(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8814B) & BIT_MASK_BT_PRI_DETECT_TO_8814B) + + +#define BIT_R_GRANTALL_WLMASK_8814B BIT(3) +#define BIT_STATIS_BT_EN_8814B BIT(2) +#define BIT_WL_ACT_MASK_ENABLE_8814B BIT(1) +#define BIT_ENHANCED_BT_8814B BIT(0) + +/* 2 REG_BT_ACT_STATISTICS_8814B */ + +#define BIT_SHIFT_STATIS_BT_HI_RX_8814B 16 +#define BIT_MASK_STATIS_BT_HI_RX_8814B 0xffff +#define BIT_STATIS_BT_HI_RX_8814B(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8814B) << BIT_SHIFT_STATIS_BT_HI_RX_8814B) +#define BIT_GET_STATIS_BT_HI_RX_8814B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8814B) & BIT_MASK_STATIS_BT_HI_RX_8814B) + + + +#define BIT_SHIFT_STATIS_BT_HI_TX_8814B 0 +#define BIT_MASK_STATIS_BT_HI_TX_8814B 0xffff +#define BIT_STATIS_BT_HI_TX_8814B(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8814B) << BIT_SHIFT_STATIS_BT_HI_TX_8814B) +#define BIT_GET_STATIS_BT_HI_TX_8814B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8814B) & BIT_MASK_STATIS_BT_HI_TX_8814B) + + + +/* 2 REG_BT_ACT_STATISTICS_1_8814B */ + +#define BIT_SHIFT_STATIS_BT_LO_RX_1_8814B 16 +#define BIT_MASK_STATIS_BT_LO_RX_1_8814B 0xffff +#define BIT_STATIS_BT_LO_RX_1_8814B(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8814B) << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) +#define BIT_GET_STATIS_BT_LO_RX_1_8814B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) & BIT_MASK_STATIS_BT_LO_RX_1_8814B) + + + +#define BIT_SHIFT_STATIS_BT_LO_TX_1_8814B 0 +#define BIT_MASK_STATIS_BT_LO_TX_1_8814B 0xffff +#define BIT_STATIS_BT_LO_TX_1_8814B(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8814B) << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) +#define BIT_GET_STATIS_BT_LO_TX_1_8814B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) & BIT_MASK_STATIS_BT_LO_TX_1_8814B) + + + +/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8814B */ + +#define BIT_SHIFT_R_BT_CMD_RPT_8814B 16 +#define BIT_MASK_R_BT_CMD_RPT_8814B 0xffff +#define BIT_R_BT_CMD_RPT_8814B(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8814B) << BIT_SHIFT_R_BT_CMD_RPT_8814B) +#define BIT_GET_R_BT_CMD_RPT_8814B(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8814B) & BIT_MASK_R_BT_CMD_RPT_8814B) + + + +#define BIT_SHIFT_R_RPT_FROM_BT_8814B 8 +#define BIT_MASK_R_RPT_FROM_BT_8814B 0xff +#define BIT_R_RPT_FROM_BT_8814B(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8814B) << BIT_SHIFT_R_RPT_FROM_BT_8814B) +#define BIT_GET_R_RPT_FROM_BT_8814B(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8814B) & BIT_MASK_R_RPT_FROM_BT_8814B) + + + +#define BIT_SHIFT_BT_HID_ISR_SET_8814B 6 +#define BIT_MASK_BT_HID_ISR_SET_8814B 0x3 +#define BIT_BT_HID_ISR_SET_8814B(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8814B) << BIT_SHIFT_BT_HID_ISR_SET_8814B) +#define BIT_GET_BT_HID_ISR_SET_8814B(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8814B) & BIT_MASK_BT_HID_ISR_SET_8814B) + + +#define BIT_TDMA_BT_START_NOTIFY_8814B BIT(5) +#define BIT_ENABLE_TDMA_FW_MODE_8814B BIT(4) +#define BIT_ENABLE_PTA_TDMA_MODE_8814B BIT(3) +#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8814B BIT(2) +#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8814B BIT(1) +#define BIT_RTK_BT_ENABLE_8814B BIT(0) + +/* 2 REG_BT_STATUS_REPORT_REGISTER_8814B */ + +#define BIT_SHIFT_BT_PROFILE_8814B 24 +#define BIT_MASK_BT_PROFILE_8814B 0xff +#define BIT_BT_PROFILE_8814B(x) (((x) & BIT_MASK_BT_PROFILE_8814B) << BIT_SHIFT_BT_PROFILE_8814B) +#define BIT_GET_BT_PROFILE_8814B(x) (((x) >> BIT_SHIFT_BT_PROFILE_8814B) & BIT_MASK_BT_PROFILE_8814B) + + + +#define BIT_SHIFT_BT_POWER_8814B 16 +#define BIT_MASK_BT_POWER_8814B 0xff +#define BIT_BT_POWER_8814B(x) (((x) & BIT_MASK_BT_POWER_8814B) << BIT_SHIFT_BT_POWER_8814B) +#define BIT_GET_BT_POWER_8814B(x) (((x) >> BIT_SHIFT_BT_POWER_8814B) & BIT_MASK_BT_POWER_8814B) + + + +#define BIT_SHIFT_BT_PREDECT_STATUS_8814B 8 +#define BIT_MASK_BT_PREDECT_STATUS_8814B 0xff +#define BIT_BT_PREDECT_STATUS_8814B(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8814B) << BIT_SHIFT_BT_PREDECT_STATUS_8814B) +#define BIT_GET_BT_PREDECT_STATUS_8814B(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8814B) & BIT_MASK_BT_PREDECT_STATUS_8814B) + + + +#define BIT_SHIFT_BT_CMD_INFO_8814B 0 +#define BIT_MASK_BT_CMD_INFO_8814B 0xff +#define BIT_BT_CMD_INFO_8814B(x) (((x) & BIT_MASK_BT_CMD_INFO_8814B) << BIT_SHIFT_BT_CMD_INFO_8814B) +#define BIT_GET_BT_CMD_INFO_8814B(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8814B) & BIT_MASK_BT_CMD_INFO_8814B) + + + +/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8814B */ +#define BIT_EN_MAC_NULL_PKT_NOTIFY_8814B BIT(31) +#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8814B BIT(30) +#define BIT_EN_BT_STSTUS_RPT_8814B BIT(29) +#define BIT_EN_BT_POWER_8814B BIT(28) +#define BIT_EN_BT_CHANNEL_8814B BIT(27) +#define BIT_EN_BT_SLOT_CHANGE_8814B BIT(26) +#define BIT_EN_BT_PROFILE_OR_HID_8814B BIT(25) +#define BIT_WLAN_RPT_NOTIFY_8814B BIT(24) + +#define BIT_SHIFT_WLAN_RPT_DATA_8814B 16 +#define BIT_MASK_WLAN_RPT_DATA_8814B 0xff +#define BIT_WLAN_RPT_DATA_8814B(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8814B) << BIT_SHIFT_WLAN_RPT_DATA_8814B) +#define BIT_GET_WLAN_RPT_DATA_8814B(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8814B) & BIT_MASK_WLAN_RPT_DATA_8814B) + + + +#define BIT_SHIFT_CMD_ID_8814B 8 +#define BIT_MASK_CMD_ID_8814B 0xff +#define BIT_CMD_ID_8814B(x) (((x) & BIT_MASK_CMD_ID_8814B) << BIT_SHIFT_CMD_ID_8814B) +#define BIT_GET_CMD_ID_8814B(x) (((x) >> BIT_SHIFT_CMD_ID_8814B) & BIT_MASK_CMD_ID_8814B) + + + +#define BIT_SHIFT_BT_DATA_8814B 0 +#define BIT_MASK_BT_DATA_8814B 0xff +#define BIT_BT_DATA_8814B(x) (((x) & BIT_MASK_BT_DATA_8814B) << BIT_SHIFT_BT_DATA_8814B) +#define BIT_GET_BT_DATA_8814B(x) (((x) >> BIT_SHIFT_BT_DATA_8814B) & BIT_MASK_BT_DATA_8814B) + + + +/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8814B */ + +#define BIT_SHIFT_WLAN_RPT_TO_8814B 0 +#define BIT_MASK_WLAN_RPT_TO_8814B 0xff +#define BIT_WLAN_RPT_TO_8814B(x) (((x) & BIT_MASK_WLAN_RPT_TO_8814B) << BIT_SHIFT_WLAN_RPT_TO_8814B) +#define BIT_GET_WLAN_RPT_TO_8814B(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8814B) & BIT_MASK_WLAN_RPT_TO_8814B) + + + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8814B */ + +#define BIT_SHIFT_ISOLATION_CHK_0_8814B 1 +#define BIT_MASK_ISOLATION_CHK_0_8814B 0x7fffff +#define BIT_ISOLATION_CHK_0_8814B(x) (((x) & BIT_MASK_ISOLATION_CHK_0_8814B) << BIT_SHIFT_ISOLATION_CHK_0_8814B) +#define BIT_GET_ISOLATION_CHK_0_8814B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8814B) & BIT_MASK_ISOLATION_CHK_0_8814B) + + +#define BIT_ISOLATION_EN_8814B BIT(0) + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8814B */ + +#define BIT_SHIFT_ISOLATION_CHK_1_8814B 0 +#define BIT_MASK_ISOLATION_CHK_1_8814B 0xffffffffL +#define BIT_ISOLATION_CHK_1_8814B(x) (((x) & BIT_MASK_ISOLATION_CHK_1_8814B) << BIT_SHIFT_ISOLATION_CHK_1_8814B) +#define BIT_GET_ISOLATION_CHK_1_8814B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8814B) & BIT_MASK_ISOLATION_CHK_1_8814B) + + + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8814B */ + +#define BIT_SHIFT_ISOLATION_CHK_2_8814B 0 +#define BIT_MASK_ISOLATION_CHK_2_8814B 0xffffff +#define BIT_ISOLATION_CHK_2_8814B(x) (((x) & BIT_MASK_ISOLATION_CHK_2_8814B) << BIT_SHIFT_ISOLATION_CHK_2_8814B) +#define BIT_GET_ISOLATION_CHK_2_8814B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8814B) & BIT_MASK_ISOLATION_CHK_2_8814B) + + + +/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8814B */ +#define BIT_BT_HID_ISR_8814B BIT(7) +#define BIT_BT_QUERY_ISR_8814B BIT(6) +#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8814B BIT(5) +#define BIT_WLAN_RPT_ISR_8814B BIT(4) +#define BIT_BT_POWER_ISR_8814B BIT(3) +#define BIT_BT_CHANNEL_ISR_8814B BIT(2) +#define BIT_BT_SLOT_CHANGE_ISR_8814B BIT(1) +#define BIT_BT_PROFILE_ISR_8814B BIT(0) + +/* 2 REG_BT_TDMA_TIME_REGISTER_8814B */ + +#define BIT_SHIFT_BT_TIME_8814B 6 +#define BIT_MASK_BT_TIME_8814B 0x3ffffff +#define BIT_BT_TIME_8814B(x) (((x) & BIT_MASK_BT_TIME_8814B) << BIT_SHIFT_BT_TIME_8814B) +#define BIT_GET_BT_TIME_8814B(x) (((x) >> BIT_SHIFT_BT_TIME_8814B) & BIT_MASK_BT_TIME_8814B) + + + +#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B 0 +#define BIT_MASK_BT_RPT_SAMPLE_RATE_8814B 0x3f +#define BIT_BT_RPT_SAMPLE_RATE_8814B(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8814B) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8814B(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) & BIT_MASK_BT_RPT_SAMPLE_RATE_8814B) + + + +/* 2 REG_BT_ACT_REGISTER_8814B */ + +#define BIT_SHIFT_BT_EISR_EN_8814B 16 +#define BIT_MASK_BT_EISR_EN_8814B 0xff +#define BIT_BT_EISR_EN_8814B(x) (((x) & BIT_MASK_BT_EISR_EN_8814B) << BIT_SHIFT_BT_EISR_EN_8814B) +#define BIT_GET_BT_EISR_EN_8814B(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8814B) & BIT_MASK_BT_EISR_EN_8814B) + + +#define BIT_BT_ACT_FALLING_ISR_8814B BIT(10) +#define BIT_BT_ACT_RISING_ISR_8814B BIT(9) +#define BIT_TDMA_TO_ISR_8814B BIT(8) + +#define BIT_SHIFT_BT_CH_8814B 0 +#define BIT_MASK_BT_CH_8814B 0xff +#define BIT_BT_CH_8814B(x) (((x) & BIT_MASK_BT_CH_8814B) << BIT_SHIFT_BT_CH_8814B) +#define BIT_GET_BT_CH_8814B(x) (((x) >> BIT_SHIFT_BT_CH_8814B) & BIT_MASK_BT_CH_8814B) + + + +/* 2 REG_OBFF_CTRL_BASIC_8814B */ +#define BIT_OBFF_EN_V1_8814B BIT(31) + +#define BIT_SHIFT_OBFF_STATE_V1_8814B 28 +#define BIT_MASK_OBFF_STATE_V1_8814B 0x3 +#define BIT_OBFF_STATE_V1_8814B(x) (((x) & BIT_MASK_OBFF_STATE_V1_8814B) << BIT_SHIFT_OBFF_STATE_V1_8814B) +#define BIT_GET_OBFF_STATE_V1_8814B(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8814B) & BIT_MASK_OBFF_STATE_V1_8814B) + + +#define BIT_OBFF_ACT_RXDMA_EN_8814B BIT(27) +#define BIT_OBFF_BLOCK_INT_EN_8814B BIT(26) +#define BIT_OBFF_AUTOACT_EN_8814B BIT(25) +#define BIT_OBFF_AUTOIDLE_EN_8814B BIT(24) + +#define BIT_SHIFT_WAKE_MAX_PLS_8814B 20 +#define BIT_MASK_WAKE_MAX_PLS_8814B 0x7 +#define BIT_WAKE_MAX_PLS_8814B(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8814B) << BIT_SHIFT_WAKE_MAX_PLS_8814B) +#define BIT_GET_WAKE_MAX_PLS_8814B(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8814B) & BIT_MASK_WAKE_MAX_PLS_8814B) + + + +#define BIT_SHIFT_WAKE_MIN_PLS_8814B 16 +#define BIT_MASK_WAKE_MIN_PLS_8814B 0x7 +#define BIT_WAKE_MIN_PLS_8814B(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8814B) << BIT_SHIFT_WAKE_MIN_PLS_8814B) +#define BIT_GET_WAKE_MIN_PLS_8814B(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8814B) & BIT_MASK_WAKE_MIN_PLS_8814B) + + + +#define BIT_SHIFT_WAKE_MAX_F2F_8814B 12 +#define BIT_MASK_WAKE_MAX_F2F_8814B 0x7 +#define BIT_WAKE_MAX_F2F_8814B(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8814B) << BIT_SHIFT_WAKE_MAX_F2F_8814B) +#define BIT_GET_WAKE_MAX_F2F_8814B(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8814B) & BIT_MASK_WAKE_MAX_F2F_8814B) + + + +#define BIT_SHIFT_WAKE_MIN_F2F_8814B 8 +#define BIT_MASK_WAKE_MIN_F2F_8814B 0x7 +#define BIT_WAKE_MIN_F2F_8814B(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8814B) << BIT_SHIFT_WAKE_MIN_F2F_8814B) +#define BIT_GET_WAKE_MIN_F2F_8814B(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8814B) & BIT_MASK_WAKE_MIN_F2F_8814B) + + +#define BIT_APP_CPU_ACT_V1_8814B BIT(3) +#define BIT_APP_OBFF_V1_8814B BIT(2) +#define BIT_APP_IDLE_V1_8814B BIT(1) +#define BIT_APP_INIT_V1_8814B BIT(0) + +/* 2 REG_OBFF_CTRL2_TIMER_8814B */ + +#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B 24 +#define BIT_MASK_RX_HIGH_TIMER_IDX_8814B 0x7 +#define BIT_RX_HIGH_TIMER_IDX_8814B(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8814B) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) +#define BIT_GET_RX_HIGH_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) & BIT_MASK_RX_HIGH_TIMER_IDX_8814B) + + + +#define BIT_SHIFT_RX_MED_TIMER_IDX_8814B 16 +#define BIT_MASK_RX_MED_TIMER_IDX_8814B 0x7 +#define BIT_RX_MED_TIMER_IDX_8814B(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8814B) << BIT_SHIFT_RX_MED_TIMER_IDX_8814B) +#define BIT_GET_RX_MED_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8814B) & BIT_MASK_RX_MED_TIMER_IDX_8814B) + + + +#define BIT_SHIFT_RX_LOW_TIMER_IDX_8814B 8 +#define BIT_MASK_RX_LOW_TIMER_IDX_8814B 0x7 +#define BIT_RX_LOW_TIMER_IDX_8814B(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8814B) << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) +#define BIT_GET_RX_LOW_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) & BIT_MASK_RX_LOW_TIMER_IDX_8814B) + + + +#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B 0 +#define BIT_MASK_OBFF_INT_TIMER_IDX_8814B 0x7 +#define BIT_OBFF_INT_TIMER_IDX_8814B(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8814B) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) +#define BIT_GET_OBFF_INT_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) & BIT_MASK_OBFF_INT_TIMER_IDX_8814B) + + + +/* 2 REG_LTR_CTRL_BASIC_8814B */ +#define BIT_LTR_EN_V1_8814B BIT(31) +#define BIT_LTR_HW_EN_V1_8814B BIT(30) +#define BIT_LRT_ACT_CTS_EN_8814B BIT(29) +#define BIT_LTR_ACT_RXPKT_EN_8814B BIT(28) +#define BIT_LTR_ACT_RXDMA_EN_8814B BIT(27) +#define BIT_LTR_IDLE_NO_SNOOP_8814B BIT(26) +#define BIT_SPDUP_MGTPKT_8814B BIT(25) +#define BIT_RX_AGG_EN_8814B BIT(24) +#define BIT_APP_LTR_ACT_8814B BIT(23) +#define BIT_APP_LTR_IDLE_8814B BIT(22) + +#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B 20 +#define BIT_MASK_HIGH_RATE_TRIG_SEL_8814B 0x3 +#define BIT_HIGH_RATE_TRIG_SEL_8814B(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8814B) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8814B(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) & BIT_MASK_HIGH_RATE_TRIG_SEL_8814B) + + + +#define BIT_SHIFT_MED_RATE_TRIG_SEL_8814B 18 +#define BIT_MASK_MED_RATE_TRIG_SEL_8814B 0x3 +#define BIT_MED_RATE_TRIG_SEL_8814B(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8814B) << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) +#define BIT_GET_MED_RATE_TRIG_SEL_8814B(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) & BIT_MASK_MED_RATE_TRIG_SEL_8814B) + + + +#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B 16 +#define BIT_MASK_LOW_RATE_TRIG_SEL_8814B 0x3 +#define BIT_LOW_RATE_TRIG_SEL_8814B(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8814B) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) +#define BIT_GET_LOW_RATE_TRIG_SEL_8814B(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) & BIT_MASK_LOW_RATE_TRIG_SEL_8814B) + + + +#define BIT_SHIFT_HIGH_RATE_BD_IDX_8814B 8 +#define BIT_MASK_HIGH_RATE_BD_IDX_8814B 0x7f +#define BIT_HIGH_RATE_BD_IDX_8814B(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8814B) << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) +#define BIT_GET_HIGH_RATE_BD_IDX_8814B(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) & BIT_MASK_HIGH_RATE_BD_IDX_8814B) + + + +#define BIT_SHIFT_LOW_RATE_BD_IDX_8814B 0 +#define BIT_MASK_LOW_RATE_BD_IDX_8814B 0x7f +#define BIT_LOW_RATE_BD_IDX_8814B(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8814B) << BIT_SHIFT_LOW_RATE_BD_IDX_8814B) +#define BIT_GET_LOW_RATE_BD_IDX_8814B(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8814B) & BIT_MASK_LOW_RATE_BD_IDX_8814B) + + + +/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8814B */ + +#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B 24 +#define BIT_MASK_RX_EMPTY_TIMER_IDX_8814B 0x7 +#define BIT_RX_EMPTY_TIMER_IDX_8814B(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8814B) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) & BIT_MASK_RX_EMPTY_TIMER_IDX_8814B) + + + +#define BIT_SHIFT_RX_AFULL_TH_IDX_8814B 20 +#define BIT_MASK_RX_AFULL_TH_IDX_8814B 0x7 +#define BIT_RX_AFULL_TH_IDX_8814B(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8814B) << BIT_SHIFT_RX_AFULL_TH_IDX_8814B) +#define BIT_GET_RX_AFULL_TH_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8814B) & BIT_MASK_RX_AFULL_TH_IDX_8814B) + + + +#define BIT_SHIFT_RX_HIGH_TH_IDX_8814B 16 +#define BIT_MASK_RX_HIGH_TH_IDX_8814B 0x7 +#define BIT_RX_HIGH_TH_IDX_8814B(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8814B) << BIT_SHIFT_RX_HIGH_TH_IDX_8814B) +#define BIT_GET_RX_HIGH_TH_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8814B) & BIT_MASK_RX_HIGH_TH_IDX_8814B) + + + +#define BIT_SHIFT_RX_MED_TH_IDX_8814B 12 +#define BIT_MASK_RX_MED_TH_IDX_8814B 0x7 +#define BIT_RX_MED_TH_IDX_8814B(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8814B) << BIT_SHIFT_RX_MED_TH_IDX_8814B) +#define BIT_GET_RX_MED_TH_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8814B) & BIT_MASK_RX_MED_TH_IDX_8814B) + + + +#define BIT_SHIFT_RX_LOW_TH_IDX_8814B 8 +#define BIT_MASK_RX_LOW_TH_IDX_8814B 0x7 +#define BIT_RX_LOW_TH_IDX_8814B(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8814B) << BIT_SHIFT_RX_LOW_TH_IDX_8814B) +#define BIT_GET_RX_LOW_TH_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8814B) & BIT_MASK_RX_LOW_TH_IDX_8814B) + + + +#define BIT_SHIFT_LTR_SPACE_IDX_8814B 4 +#define BIT_MASK_LTR_SPACE_IDX_8814B 0x3 +#define BIT_LTR_SPACE_IDX_8814B(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8814B) << BIT_SHIFT_LTR_SPACE_IDX_8814B) +#define BIT_GET_LTR_SPACE_IDX_8814B(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8814B) & BIT_MASK_LTR_SPACE_IDX_8814B) + + + +#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B 0 +#define BIT_MASK_LTR_IDLE_TIMER_IDX_8814B 0x7 +#define BIT_LTR_IDLE_TIMER_IDX_8814B(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8814B) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) & BIT_MASK_LTR_IDLE_TIMER_IDX_8814B) + + + +/* 2 REG_LTR_IDLE_LATENCY_V1_8814B */ + +#define BIT_SHIFT_LTR_IDLE_L_8814B 0 +#define BIT_MASK_LTR_IDLE_L_8814B 0xffffffffL +#define BIT_LTR_IDLE_L_8814B(x) (((x) & BIT_MASK_LTR_IDLE_L_8814B) << BIT_SHIFT_LTR_IDLE_L_8814B) +#define BIT_GET_LTR_IDLE_L_8814B(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8814B) & BIT_MASK_LTR_IDLE_L_8814B) + + + +/* 2 REG_LTR_ACTIVE_LATENCY_V1_8814B */ + +#define BIT_SHIFT_LTR_ACT_L_8814B 0 +#define BIT_MASK_LTR_ACT_L_8814B 0xffffffffL +#define BIT_LTR_ACT_L_8814B(x) (((x) & BIT_MASK_LTR_ACT_L_8814B) << BIT_SHIFT_LTR_ACT_L_8814B) +#define BIT_GET_LTR_ACT_L_8814B(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8814B) & BIT_MASK_LTR_ACT_L_8814B) + + + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8814B */ + +#define BIT_SHIFT_TRAIN_STA_ADDR_0_8814B 0 +#define BIT_MASK_TRAIN_STA_ADDR_0_8814B 0xffffffffL +#define BIT_TRAIN_STA_ADDR_0_8814B(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8814B) << BIT_SHIFT_TRAIN_STA_ADDR_0_8814B) +#define BIT_GET_TRAIN_STA_ADDR_0_8814B(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8814B) & BIT_MASK_TRAIN_STA_ADDR_0_8814B) + + + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8814B */ +#define BIT_APPEND_MACID_IN_RESP_EN_1_8814B BIT(18) +#define BIT_ADDR2_MATCH_EN_1_8814B BIT(17) +#define BIT_ANTTRN_EN_1_8814B BIT(16) + +#define BIT_SHIFT_TRAIN_STA_ADDR_1_8814B 0 +#define BIT_MASK_TRAIN_STA_ADDR_1_8814B 0xffff +#define BIT_TRAIN_STA_ADDR_1_8814B(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8814B) << BIT_SHIFT_TRAIN_STA_ADDR_1_8814B) +#define BIT_GET_TRAIN_STA_ADDR_1_8814B(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8814B) & BIT_MASK_TRAIN_STA_ADDR_1_8814B) + + + +/* 2 REG_WMAC_PKTCNT_RWD_8814B */ + +#define BIT_SHIFT_PKTCNT_BSSIDMAP_8814B 4 +#define BIT_MASK_PKTCNT_BSSIDMAP_8814B 0xf +#define BIT_PKTCNT_BSSIDMAP_8814B(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8814B) << BIT_SHIFT_PKTCNT_BSSIDMAP_8814B) +#define BIT_GET_PKTCNT_BSSIDMAP_8814B(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8814B) & BIT_MASK_PKTCNT_BSSIDMAP_8814B) + + +#define BIT_PKTCNT_CNTRST_8814B BIT(1) +#define BIT_PKTCNT_CNTEN_8814B BIT(0) + +/* 2 REG_WMAC_PKTCNT_CTRL_8814B */ +#define BIT_WMAC_PKTCNT_TRST_8814B BIT(9) +#define BIT_WMAC_PKTCNT_FEN_8814B BIT(8) + +#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8814B 0 +#define BIT_MASK_WMAC_PKTCNT_CFGAD_8814B 0xff +#define BIT_WMAC_PKTCNT_CFGAD_8814B(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8814B) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8814B) +#define BIT_GET_WMAC_PKTCNT_CFGAD_8814B(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8814B) & BIT_MASK_WMAC_PKTCNT_CFGAD_8814B) + + + +/* 2 REG_IQ_DUMP_8814B */ + +#define BIT_SHIFT_DUMP_OK_ADDR_8814B 15 +#define BIT_MASK_DUMP_OK_ADDR_8814B 0x1ffff +#define BIT_DUMP_OK_ADDR_8814B(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8814B) << BIT_SHIFT_DUMP_OK_ADDR_8814B) +#define BIT_GET_DUMP_OK_ADDR_8814B(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8814B) & BIT_MASK_DUMP_OK_ADDR_8814B) + + + +#define BIT_SHIFT_R_TRIG_TIME_SEL_8814B 8 +#define BIT_MASK_R_TRIG_TIME_SEL_8814B 0x7f +#define BIT_R_TRIG_TIME_SEL_8814B(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8814B) << BIT_SHIFT_R_TRIG_TIME_SEL_8814B) +#define BIT_GET_R_TRIG_TIME_SEL_8814B(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8814B) & BIT_MASK_R_TRIG_TIME_SEL_8814B) + + + +#define BIT_SHIFT_R_MAC_TRIG_SEL_8814B 6 +#define BIT_MASK_R_MAC_TRIG_SEL_8814B 0x3 +#define BIT_R_MAC_TRIG_SEL_8814B(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8814B) << BIT_SHIFT_R_MAC_TRIG_SEL_8814B) +#define BIT_GET_R_MAC_TRIG_SEL_8814B(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8814B) & BIT_MASK_R_MAC_TRIG_SEL_8814B) + + +#define BIT_MAC_TRIG_REG_8814B BIT(5) + +#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B 3 +#define BIT_MASK_R_LEVEL_PULSE_SEL_8814B 0x3 +#define BIT_R_LEVEL_PULSE_SEL_8814B(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8814B) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) +#define BIT_GET_R_LEVEL_PULSE_SEL_8814B(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) & BIT_MASK_R_LEVEL_PULSE_SEL_8814B) + + +#define BIT_EN_LA_MAC_8814B BIT(2) +#define BIT_R_EN_IQDUMP_8814B BIT(1) +#define BIT_R_IQDATA_DUMP_8814B BIT(0) + +/* 2 REG_IQ_DUMP_1_8814B */ + +#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B 0 +#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B 0xffffffffL +#define BIT_R_WMAC_MASK_LA_MAC_1_8814B(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) +#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B) + + + +/* 2 REG_IQ_DUMP_2_8814B */ + +#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B 0 +#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B 0xffffffffL +#define BIT_R_WMAC_MATCH_REF_MAC_2_8814B(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B) + + + +/* 2 REG_WMAC_FTM_CTL_8814B */ +#define BIT_RXFTM_TXACK_SC_8814B BIT(6) +#define BIT_RXFTM_TXACK_BW_8814B BIT(5) +#define BIT_RXFTM_EN_8814B BIT(3) +#define BIT_RXFTMREQ_BYDRV_8814B BIT(2) +#define BIT_RXFTMREQ_EN_8814B BIT(1) +#define BIT_FTM_EN_8814B BIT(0) + +/* 2 REG_WMAC_IQ_MDPK_FUNC_8814B */ + +/* 2 REG_WMAC_OPTION_FUNCTION_8814B */ + +#define BIT_SHIFT_R_OFDM_LEN_8814B 26 +#define BIT_MASK_R_OFDM_LEN_8814B 0x3f +#define BIT_R_OFDM_LEN_8814B(x) (((x) & BIT_MASK_R_OFDM_LEN_8814B) << BIT_SHIFT_R_OFDM_LEN_8814B) +#define BIT_GET_R_OFDM_LEN_8814B(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8814B) & BIT_MASK_R_OFDM_LEN_8814B) + + + +#define BIT_SHIFT_R_CCK_LEN_8814B 0 +#define BIT_MASK_R_CCK_LEN_8814B 0xffff +#define BIT_R_CCK_LEN_8814B(x) (((x) & BIT_MASK_R_CCK_LEN_8814B) << BIT_SHIFT_R_CCK_LEN_8814B) +#define BIT_GET_R_CCK_LEN_8814B(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8814B) & BIT_MASK_R_CCK_LEN_8814B) + + + +/* 2 REG_WMAC_OPTION_FUNCTION_1_8814B */ + +#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B 24 +#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B 0xff +#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B) + + +#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8814B BIT(23) +#define BIT_R_WMAC_RXRST_DLY_1_8814B BIT(22) +#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8814B BIT(21) +#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8814B BIT(20) +#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8814B BIT(19) +#define BIT_R_WMAC_NDP_RST_1_8814B BIT(18) +#define BIT_R_WMAC_POWINT_EN_1_8814B BIT(17) +#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8814B BIT(16) +#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8814B BIT(15) +#define BIT_R_WMAC_PFIN_TOEN_1_8814B BIT(14) +#define BIT_R_WMAC_FIL_SECERR_1_8814B BIT(13) +#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8814B BIT(12) +#define BIT_R_WMAC_FIL_FCTYPE_1_8814B BIT(11) +#define BIT_R_WMAC_FIL_FCPROVER_1_8814B BIT(10) +#define BIT_R_WMAC_PHYSTS_SNIF_1_8814B BIT(9) +#define BIT_R_WMAC_PHYSTS_PLCP_1_8814B BIT(8) +#define BIT_R_MAC_TCR_VBONF_RD_1_8814B BIT(7) +#define BIT_R_WMAC_TCR_MPAR_NDP_1_8814B BIT(6) +#define BIT_R_WMAC_NDP_FILTER_1_8814B BIT(5) +#define BIT_R_WMAC_RXLEN_SEL_1_8814B BIT(4) +#define BIT_R_WMAC_RXLEN_SEL1_1_8814B BIT(3) +#define BIT_R_OFDM_FILTER_1_8814B BIT(2) +#define BIT_R_WMAC_CHK_OFDM_LEN_1_8814B BIT(1) +#define BIT_R_WMAC_CHK_CCK_LEN_1_8814B BIT(0) + +/* 2 REG_WMAC_OPTION_FUNCTION_2_8814B */ + +#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B 0 +#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B 0xffff +#define BIT_R_WMAC_RX_FIL_LEN_2_8814B(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) +#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B) + + + +/* 2 REG_RX_FILTER_FUNCTION_8814B */ +#define BIT_R_WMAC_MHRDDY_LATCH_8814B BIT(14) +#define BIT_R_WMAC_MHRDDY_CLR_8814B BIT(13) +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8814B BIT(12) +#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8814B BIT(11) +#define BIT_R_CHK_DELIMIT_LEN_8814B BIT(10) +#define BIT_R_REAPTER_ADDR_MATCH_8814B BIT(9) +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8814B BIT(8) +#define BIT_R_LATCH_MACHRDY_8814B BIT(7) +#define BIT_R_WMAC_RXFIL_REND_8814B BIT(6) +#define BIT_R_WMAC_MPDURDY_CLR_8814B BIT(5) +#define BIT_R_WMAC_CLRRXSEC_8814B BIT(4) +#define BIT_R_WMAC_RXFIL_RDEL_8814B BIT(3) +#define BIT_R_WMAC_RXFIL_FCSE_8814B BIT(2) +#define BIT_R_WMAC_RXFIL_MESH_DEL_8814B BIT(1) +#define BIT_R_WMAC_RXFIL_MASKM_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NDP_SIG_8814B */ + +#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B 0 +#define BIT_MASK_R_WMAC_TXNDP_SIGB_8814B 0x1fffff +#define BIT_R_WMAC_TXNDP_SIGB_8814B(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8814B) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) & BIT_MASK_R_WMAC_TXNDP_SIGB_8814B) + + + +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8814B */ + +#define BIT_SHIFT_R_MAC_DBG_SHIFT_8814B 8 +#define BIT_MASK_R_MAC_DBG_SHIFT_8814B 0x7 +#define BIT_R_MAC_DBG_SHIFT_8814B(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8814B) << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) +#define BIT_GET_R_MAC_DBG_SHIFT_8814B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) & BIT_MASK_R_MAC_DBG_SHIFT_8814B) + + + +#define BIT_SHIFT_R_MAC_DBG_SEL_8814B 0 +#define BIT_MASK_R_MAC_DBG_SEL_8814B 0x3 +#define BIT_R_MAC_DBG_SEL_8814B(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8814B) << BIT_SHIFT_R_MAC_DBG_SEL_8814B) +#define BIT_GET_R_MAC_DBG_SEL_8814B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8814B) & BIT_MASK_R_MAC_DBG_SEL_8814B) + + + +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8814B */ + +#define BIT_SHIFT_R_MAC_DEBUG_1_8814B 0 +#define BIT_MASK_R_MAC_DEBUG_1_8814B 0xffffffffL +#define BIT_R_MAC_DEBUG_1_8814B(x) (((x) & BIT_MASK_R_MAC_DEBUG_1_8814B) << BIT_SHIFT_R_MAC_DEBUG_1_8814B) +#define BIT_GET_R_MAC_DEBUG_1_8814B(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8814B) & BIT_MASK_R_MAC_DEBUG_1_8814B) + + + +/* 2 REG_WSEC_OPTION_8814B */ +#define BIT_RXDEC_BM_MGNT_8814B BIT(22) +#define BIT_TXENC_BM_MGNT_8814B BIT(21) +#define BIT_RXDEC_UNI_MGNT_8814B BIT(20) +#define BIT_TXENC_UNI_MGNT_8814B BIT(19) + +/* 2 REG_RTS_ADDRESS_0_8814B */ + +/* 2 REG_RTS_ADDRESS_0_1_8814B */ + +/* 2 REG_RTS_ADDRESS_1_8814B */ + +/* 2 REG_RTS_ADDRESS_1_1_8814B */ + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8814B */ +#define BIT_LTECOEX_ACCESS_START_V1_8814B BIT(31) +#define BIT_LTECOEX_WRITE_MODE_V1_8814B BIT(30) +#define BIT_LTECOEX_READY_BIT_V1_8814B BIT(29) + +#define BIT_SHIFT_WRITE_BYTE_EN_V1_8814B 16 +#define BIT_MASK_WRITE_BYTE_EN_V1_8814B 0xf +#define BIT_WRITE_BYTE_EN_V1_8814B(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8814B) << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) +#define BIT_GET_WRITE_BYTE_EN_V1_8814B(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) & BIT_MASK_WRITE_BYTE_EN_V1_8814B) + + + +#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B 0 +#define BIT_MASK_LTECOEX_REG_ADDR_V1_8814B 0xffff +#define BIT_LTECOEX_REG_ADDR_V1_8814B(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8814B) << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) +#define BIT_GET_LTECOEX_REG_ADDR_V1_8814B(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) & BIT_MASK_LTECOEX_REG_ADDR_V1_8814B) + + + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B */ + +#define BIT_SHIFT_LTECOEX_W_DATA_V1_8814B 0 +#define BIT_MASK_LTECOEX_W_DATA_V1_8814B 0xffffffffL +#define BIT_LTECOEX_W_DATA_V1_8814B(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8814B) << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) +#define BIT_GET_LTECOEX_W_DATA_V1_8814B(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) & BIT_MASK_LTECOEX_W_DATA_V1_8814B) + + + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B */ + +#define BIT_SHIFT_LTECOEX_R_DATA_V1_8814B 0 +#define BIT_MASK_LTECOEX_R_DATA_V1_8814B 0xffffffffL +#define BIT_LTECOEX_R_DATA_V1_8814B(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8814B) << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) +#define BIT_GET_LTECOEX_R_DATA_V1_8814B(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) & BIT_MASK_LTECOEX_R_DATA_V1_8814B) + + + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_SDIO_TX_CTRL_8814B */ + +#define BIT_SHIFT_SDIO_INT_TIMEOUT_8814B 16 +#define BIT_MASK_SDIO_INT_TIMEOUT_8814B 0xffff +#define BIT_SDIO_INT_TIMEOUT_8814B(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8814B) << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) +#define BIT_GET_SDIO_INT_TIMEOUT_8814B(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) & BIT_MASK_SDIO_INT_TIMEOUT_8814B) + + +#define BIT_IO_ERR_STATUS_8814B BIT(15) +#define BIT_REPLY_ERRCRC_IN_DATA_8814B BIT(9) +#define BIT_EN_CMD53_OVERLAP_8814B BIT(8) +#define BIT_REPLY_ERR_IN_R5_8814B BIT(7) +#define BIT_R18A_EN_8814B BIT(6) +#define BIT_INIT_CMD_EN_8814B BIT(5) +#define BIT_EN_RXDMA_MASK_INT_8814B BIT(2) +#define BIT_EN_MASK_TIMER_8814B BIT(1) +#define BIT_CMD_ERR_STOP_INT_EN_8814B BIT(0) + +/* 2 REG_SDIO_HIMR_8814B */ +#define BIT_SDIO_CRCERR_MSK_8814B BIT(31) +#define BIT_SDIO_HSISR3_IND_MSK_8814B BIT(30) +#define BIT_SDIO_HSISR2_IND_MSK_8814B BIT(29) +#define BIT_SDIO_HEISR_IND_MSK_8814B BIT(28) +#define BIT_SDIO_CTWEND_MSK_8814B BIT(27) +#define BIT_SDIO_ATIMEND_E_MSK_8814B BIT(26) +#define BIT_SDIIO_ATIMEND_MSK_8814B BIT(25) +#define BIT_SDIO_OCPINT_MSK_8814B BIT(24) +#define BIT_SDIO_PSTIMEOUT_MSK_8814B BIT(23) +#define BIT_SDIO_GTINT4_MSK_8814B BIT(22) +#define BIT_SDIO_GTINT3_MSK_8814B BIT(21) +#define BIT_SDIO_HSISR_IND_MSK_8814B BIT(20) +#define BIT_SDIO_CPWM2_MSK_8814B BIT(19) +#define BIT_SDIO_CPWM1_MSK_8814B BIT(18) +#define BIT_SDIO_C2HCMD_INT_MSK_8814B BIT(17) +#define BIT_SDIO_BCNERLY_INT_MSK_8814B BIT(16) +#define BIT_SDIO_TXBCNERR_MSK_8814B BIT(7) +#define BIT_SDIO_TXBCNOK_MSK_8814B BIT(6) +#define BIT_SDIO_RXFOVW_MSK_8814B BIT(5) +#define BIT_SDIO_TXFOVW_MSK_8814B BIT(4) +#define BIT_SDIO_RXERR_MSK_8814B BIT(3) +#define BIT_SDIO_TXERR_MSK_8814B BIT(2) +#define BIT_SDIO_AVAL_MSK_8814B BIT(1) +#define BIT_RX_REQUEST_MSK_8814B BIT(0) + +/* 2 REG_SDIO_HISR_8814B */ +#define BIT_SDIO_CRCERR_8814B BIT(31) +#define BIT_SDIO_HSISR3_IND_8814B BIT(30) +#define BIT_SDIO_HSISR2_IND_8814B BIT(29) +#define BIT_SDIO_HEISR_IND_8814B BIT(28) +#define BIT_SDIO_CTWEND_8814B BIT(27) +#define BIT_SDIO_ATIMEND_E_8814B BIT(26) +#define BIT_SDIO_ATIMEND_8814B BIT(25) +#define BIT_SDIO_OCPINT_8814B BIT(24) +#define BIT_SDIO_PSTIMEOUT_8814B BIT(23) +#define BIT_SDIO_GTINT4_8814B BIT(22) +#define BIT_SDIO_GTINT3_8814B BIT(21) +#define BIT_SDIO_HSISR_IND_8814B BIT(20) +#define BIT_SDIO_CPWM2_8814B BIT(19) +#define BIT_SDIO_CPWM1_8814B BIT(18) +#define BIT_SDIO_C2HCMD_INT_8814B BIT(17) +#define BIT_SDIO_BCNERLY_INT_8814B BIT(16) +#define BIT_SDIO_TXBCNERR_8814B BIT(7) +#define BIT_SDIO_TXBCNOK_8814B BIT(6) +#define BIT_SDIO_RXFOVW_8814B BIT(5) +#define BIT_SDIO_TXFOVW_8814B BIT(4) +#define BIT_SDIO_RXERR_8814B BIT(3) +#define BIT_SDIO_TXERR_8814B BIT(2) +#define BIT_SDIO_AVAL_8814B BIT(1) +#define BIT_RX_REQUEST_8814B BIT(0) + +/* 2 REG_SDIO_RX_REQ_LEN_8814B */ + +#define BIT_SHIFT_RX_REQ_LEN_V1_8814B 0 +#define BIT_MASK_RX_REQ_LEN_V1_8814B 0x3ffff +#define BIT_RX_REQ_LEN_V1_8814B(x) (((x) & BIT_MASK_RX_REQ_LEN_V1_8814B) << BIT_SHIFT_RX_REQ_LEN_V1_8814B) +#define BIT_GET_RX_REQ_LEN_V1_8814B(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8814B) & BIT_MASK_RX_REQ_LEN_V1_8814B) + + + +/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8814B */ + +#define BIT_SHIFT_FREE_TXPG_SEQ_8814B 0 +#define BIT_MASK_FREE_TXPG_SEQ_8814B 0xff +#define BIT_FREE_TXPG_SEQ_8814B(x) (((x) & BIT_MASK_FREE_TXPG_SEQ_8814B) << BIT_SHIFT_FREE_TXPG_SEQ_8814B) +#define BIT_GET_FREE_TXPG_SEQ_8814B(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8814B) & BIT_MASK_FREE_TXPG_SEQ_8814B) + + + +/* 2 REG_SDIO_FREE_TXPG_8814B */ + +#define BIT_SHIFT_MID_FREEPG_V1_8814B 16 +#define BIT_MASK_MID_FREEPG_V1_8814B 0xfff +#define BIT_MID_FREEPG_V1_8814B(x) (((x) & BIT_MASK_MID_FREEPG_V1_8814B) << BIT_SHIFT_MID_FREEPG_V1_8814B) +#define BIT_GET_MID_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1_8814B) & BIT_MASK_MID_FREEPG_V1_8814B) + + + +#define BIT_SHIFT_HIQ_FREEPG_V1_8814B 0 +#define BIT_MASK_HIQ_FREEPG_V1_8814B 0xfff +#define BIT_HIQ_FREEPG_V1_8814B(x) (((x) & BIT_MASK_HIQ_FREEPG_V1_8814B) << BIT_SHIFT_HIQ_FREEPG_V1_8814B) +#define BIT_GET_HIQ_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8814B) & BIT_MASK_HIQ_FREEPG_V1_8814B) + + + +/* 2 REG_SDIO_FREE_TXPG2_8814B */ + +#define BIT_SHIFT_PUB_FREEPG_V1_8814B 16 +#define BIT_MASK_PUB_FREEPG_V1_8814B 0xfff +#define BIT_PUB_FREEPG_V1_8814B(x) (((x) & BIT_MASK_PUB_FREEPG_V1_8814B) << BIT_SHIFT_PUB_FREEPG_V1_8814B) +#define BIT_GET_PUB_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8814B) & BIT_MASK_PUB_FREEPG_V1_8814B) + + + +#define BIT_SHIFT_LOW_FREEPG_V1_8814B 0 +#define BIT_MASK_LOW_FREEPG_V1_8814B 0xfff +#define BIT_LOW_FREEPG_V1_8814B(x) (((x) & BIT_MASK_LOW_FREEPG_V1_8814B) << BIT_SHIFT_LOW_FREEPG_V1_8814B) +#define BIT_GET_LOW_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8814B) & BIT_MASK_LOW_FREEPG_V1_8814B) + + + +/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8814B */ + +#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B 24 +#define BIT_MASK_NOAC_OQT_FREEPG_V1_8814B 0xff +#define BIT_NOAC_OQT_FREEPG_V1_8814B(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8814B) << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) +#define BIT_GET_NOAC_OQT_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) & BIT_MASK_NOAC_OQT_FREEPG_V1_8814B) + + + +#define BIT_SHIFT_AC_OQT_FREEPG_V1_8814B 16 +#define BIT_MASK_AC_OQT_FREEPG_V1_8814B 0xff +#define BIT_AC_OQT_FREEPG_V1_8814B(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8814B) << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) +#define BIT_GET_AC_OQT_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) & BIT_MASK_AC_OQT_FREEPG_V1_8814B) + + + +#define BIT_SHIFT_EXQ_FREEPG_V1_8814B 0 +#define BIT_MASK_EXQ_FREEPG_V1_8814B 0xfff +#define BIT_EXQ_FREEPG_V1_8814B(x) (((x) & BIT_MASK_EXQ_FREEPG_V1_8814B) << BIT_SHIFT_EXQ_FREEPG_V1_8814B) +#define BIT_GET_EXQ_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8814B) & BIT_MASK_EXQ_FREEPG_V1_8814B) + + + +/* 2 REG_SDIO_HTSFR_INFO_8814B */ + +#define BIT_SHIFT_HTSFR1_8814B 16 +#define BIT_MASK_HTSFR1_8814B 0xffff +#define BIT_HTSFR1_8814B(x) (((x) & BIT_MASK_HTSFR1_8814B) << BIT_SHIFT_HTSFR1_8814B) +#define BIT_GET_HTSFR1_8814B(x) (((x) >> BIT_SHIFT_HTSFR1_8814B) & BIT_MASK_HTSFR1_8814B) + + + +#define BIT_SHIFT_HTSFR0_8814B 0 +#define BIT_MASK_HTSFR0_8814B 0xffff +#define BIT_HTSFR0_8814B(x) (((x) & BIT_MASK_HTSFR0_8814B) << BIT_SHIFT_HTSFR0_8814B) +#define BIT_GET_HTSFR0_8814B(x) (((x) >> BIT_SHIFT_HTSFR0_8814B) & BIT_MASK_HTSFR0_8814B) + + + +/* 2 REG_SDIO_HCPWM1_V2_8814B */ +#define BIT_TOGGLING_8814B BIT(7) +#define BIT_ACK_8814B BIT(6) +#define BIT_SYS_CLK_8814B BIT(0) + +/* 2 REG_SDIO_HCPWM2_V2_8814B */ + +/* 2 REG_SDIO_INDIRECT_REG_CFG_8814B */ +#define BIT_INDIRECT_REG_RDY_8814B BIT(20) +#define BIT_INDIRECT_REG_R_8814B BIT(19) +#define BIT_INDIRECT_REG_W_8814B BIT(18) + +#define BIT_SHIFT_INDIRECT_REG_SIZE_8814B 16 +#define BIT_MASK_INDIRECT_REG_SIZE_8814B 0x3 +#define BIT_INDIRECT_REG_SIZE_8814B(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE_8814B) << BIT_SHIFT_INDIRECT_REG_SIZE_8814B) +#define BIT_GET_INDIRECT_REG_SIZE_8814B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8814B) & BIT_MASK_INDIRECT_REG_SIZE_8814B) + + + +#define BIT_SHIFT_INDIRECT_REG_ADDR_8814B 0 +#define BIT_MASK_INDIRECT_REG_ADDR_8814B 0xffff +#define BIT_INDIRECT_REG_ADDR_8814B(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR_8814B) << BIT_SHIFT_INDIRECT_REG_ADDR_8814B) +#define BIT_GET_INDIRECT_REG_ADDR_8814B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8814B) & BIT_MASK_INDIRECT_REG_ADDR_8814B) + + + +/* 2 REG_SDIO_INDIRECT_REG_DATA_8814B */ + +#define BIT_SHIFT_INDIRECT_REG_DATA_8814B 0 +#define BIT_MASK_INDIRECT_REG_DATA_8814B 0xffffffffL +#define BIT_INDIRECT_REG_DATA_8814B(x) (((x) & BIT_MASK_INDIRECT_REG_DATA_8814B) << BIT_SHIFT_INDIRECT_REG_DATA_8814B) +#define BIT_GET_INDIRECT_REG_DATA_8814B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8814B) & BIT_MASK_INDIRECT_REG_DATA_8814B) + + + +/* 2 REG_SDIO_H2C_8814B */ + +#define BIT_SHIFT_SDIO_H2C_MSG_8814B 0 +#define BIT_MASK_SDIO_H2C_MSG_8814B 0xffffffffL +#define BIT_SDIO_H2C_MSG_8814B(x) (((x) & BIT_MASK_SDIO_H2C_MSG_8814B) << BIT_SHIFT_SDIO_H2C_MSG_8814B) +#define BIT_GET_SDIO_H2C_MSG_8814B(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8814B) & BIT_MASK_SDIO_H2C_MSG_8814B) + + + +/* 2 REG_SDIO_C2H_8814B */ + +#define BIT_SHIFT_SDIO_C2H_MSG_8814B 0 +#define BIT_MASK_SDIO_C2H_MSG_8814B 0xffffffffL +#define BIT_SDIO_C2H_MSG_8814B(x) (((x) & BIT_MASK_SDIO_C2H_MSG_8814B) << BIT_SHIFT_SDIO_C2H_MSG_8814B) +#define BIT_GET_SDIO_C2H_MSG_8814B(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8814B) & BIT_MASK_SDIO_C2H_MSG_8814B) + + + +/* 2 REG_SDIO_HRPWM1_8814B */ +#define BIT_TOGGLING_8814B BIT(7) +#define BIT_ACK_8814B BIT(6) +#define BIT_32K_PERMISSION_8814B BIT(0) + +/* 2 REG_SDIO_HRPWM2_8814B */ + +/* 2 REG_SDIO_HPS_CLKR_8814B */ + +/* 2 REG_SDIO_BUS_CTRL_8814B */ +#define BIT_PAD_CLK_XHGE_EN_8814B BIT(3) +#define BIT_INTER_CLK_EN_8814B BIT(2) +#define BIT_EN_RPT_TXCRC_8814B BIT(1) +#define BIT_DIS_RXDMA_STS_8814B BIT(0) + +/* 2 REG_SDIO_HSUS_CTRL_8814B */ +#define BIT_INTR_CTRL_8814B BIT(4) +#define BIT_SDIO_VOLTAGE_8814B BIT(3) +#define BIT_BYPASS_INIT_8814B BIT(2) +#define BIT_HCI_RESUME_RDY_8814B BIT(1) +#define BIT_HCI_SUS_REQ_8814B BIT(0) + +/* 2 REG_SDIO_RESPONSE_TIMER_8814B */ + +#define BIT_SHIFT_CMDIN_2RESP_TIMER_8814B 0 +#define BIT_MASK_CMDIN_2RESP_TIMER_8814B 0xffff +#define BIT_CMDIN_2RESP_TIMER_8814B(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8814B) << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) +#define BIT_GET_CMDIN_2RESP_TIMER_8814B(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) & BIT_MASK_CMDIN_2RESP_TIMER_8814B) + + + +/* 2 REG_SDIO_CMD_CRC_8814B */ + +#define BIT_SHIFT_SDIO_CMD_CRC_V1_8814B 0 +#define BIT_MASK_SDIO_CMD_CRC_V1_8814B 0xff +#define BIT_SDIO_CMD_CRC_V1_8814B(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8814B) << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) +#define BIT_GET_SDIO_CMD_CRC_V1_8814B(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) & BIT_MASK_SDIO_CMD_CRC_V1_8814B) + + + +/* 2 REG_SDIO_HSISR_8814B */ +#define BIT_DRV_WLAN_INT_CLR_8814B BIT(1) +#define BIT_DRV_WLAN_INT_8814B BIT(0) + +/* 2 REG_SDIO_HSIMR_8814B */ +#define BIT_HISR_MASK_8814B BIT(0) + +/* 2 REG_SDIO_ERR_RPT_8814B */ +#define BIT_HR_FF_OVF_8814B BIT(6) +#define BIT_HR_FF_UDN_8814B BIT(5) +#define BIT_TXDMA_BUSY_ERR_8814B BIT(4) +#define BIT_TXDMA_VLD_ERR_8814B BIT(3) +#define BIT_QSEL_UNKNOWN_ERR_8814B BIT(2) +#define BIT_QSEL_MIS_ERR_8814B BIT(1) +#define BIT_SDIO_OVERRD_ERR_8814B BIT(0) + +/* 2 REG_SDIO_CMD_ERRCNT_8814B */ + +#define BIT_SHIFT_CMD_CRC_ERR_CNT_8814B 0 +#define BIT_MASK_CMD_CRC_ERR_CNT_8814B 0xff +#define BIT_CMD_CRC_ERR_CNT_8814B(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8814B) << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) +#define BIT_GET_CMD_CRC_ERR_CNT_8814B(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) & BIT_MASK_CMD_CRC_ERR_CNT_8814B) + + + +/* 2 REG_SDIO_DATA_ERRCNT_8814B */ + +#define BIT_SHIFT_DATA_CRC_ERR_CNT_8814B 0 +#define BIT_MASK_DATA_CRC_ERR_CNT_8814B 0xff +#define BIT_DATA_CRC_ERR_CNT_8814B(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8814B) << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) +#define BIT_GET_DATA_CRC_ERR_CNT_8814B(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) & BIT_MASK_DATA_CRC_ERR_CNT_8814B) + + + +/* 2 REG_SDIO_CMD_ERR_CONTENT_8814B */ + +#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B 0 +#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B 0xffffffffffL +#define BIT_SDIO_CMD_ERR_CONTENT_8814B(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) +#define BIT_GET_SDIO_CMD_ERR_CONTENT_8814B(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B) + + + +/* 2 REG_SDIO_CRC_ERR_IDX_8814B */ +#define BIT_D3_CRC_ERR_8814B BIT(4) +#define BIT_D2_CRC_ERR_8814B BIT(3) +#define BIT_D1_CRC_ERR_8814B BIT(2) +#define BIT_D0_CRC_ERR_8814B BIT(1) +#define BIT_CMD_CRC_ERR_8814B BIT(0) + +/* 2 REG_SDIO_DATA_CRC_8814B */ + +#define BIT_SHIFT_SDIO_DATA_CRC_8814B 0 +#define BIT_MASK_SDIO_DATA_CRC_8814B 0xff +#define BIT_SDIO_DATA_CRC_8814B(x) (((x) & BIT_MASK_SDIO_DATA_CRC_8814B) << BIT_SHIFT_SDIO_DATA_CRC_8814B) +#define BIT_GET_SDIO_DATA_CRC_8814B(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8814B) & BIT_MASK_SDIO_DATA_CRC_8814B) + + + +/* 2 REG_SDIO_DATA_REPLY_TIME_8814B */ + +#define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B 0 +#define BIT_MASK_SDIO_DATA_REPLY_TIME_8814B 0x7 +#define BIT_SDIO_DATA_REPLY_TIME_8814B(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8814B) << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) +#define BIT_GET_SDIO_DATA_REPLY_TIME_8814B(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) & BIT_MASK_SDIO_DATA_REPLY_TIME_8814B) + + + +#endif diff --git a/hal/halmac/halmac_gpio_cmd.h b/hal/halmac/halmac_gpio_cmd.h new file mode 100644 index 0000000..27e1fb1 --- /dev/null +++ b/hal/halmac/halmac_gpio_cmd.h @@ -0,0 +1,84 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef HALMAC_GPIO_CMD +#define HALMAC_GPIO_CMD + +#include "halmac_2_platform.h" + +/* GPIO ID */ +#define HALMAC_GPIO0 0 +#define HALMAC_GPIO1 1 +#define HALMAC_GPIO2 2 +#define HALMAC_GPIO3 3 +#define HALMAC_GPIO4 4 +#define HALMAC_GPIO5 5 +#define HALMAC_GPIO6 6 +#define HALMAC_GPIO7 7 +#define HALMAC_GPIO8 8 +#define HALMAC_GPIO9 9 +#define HALMAC_GPIO10 10 +#define HALMAC_GPIO11 11 +#define HALMAC_GPIO12 12 +#define HALMAC_GPIO13 13 +#define HALMAC_GPIO14 14 +#define HALMAC_GPIO15 15 +#define HALMAC_GPIO_NUM 16 + +/* GPIO type */ +#define HALMAC_GPIO_IN 0 +#define HALMAC_GPIO_OUT 1 +#define HALMAC_GPIO_IN_OUT 2 + +/* Function name */ +#define HALMAC_WL_HWPDN 0 +#define HALMAC_BT_HWPDN 1 +#define HALMAC_BT_GPIO 2 +#define HALMAC_WL_HW_EXTWOL 3 +#define HALMAC_BT_HW_EXTWOL 4 +#define HALMAC_BT_SFLASH 5 +#define HALMAC_WL_SFLASH 6 +#define HALMAC_WL_LED 7 +#define HALMAC_SDIO_INT 8 +#define HALMAC_UART0 9 +#define HALMAC_EEPROM 10 +#define HALMAC_JTAG 11 +#define HALMAC_LTE_COEX_UART 12 +#define HALMAC_3W_LTE_WL_GPIO 13 +#define HALMAC_GPIO2_3_WL_CTRL_EN 14 +#define HALMAC_GPIO13_14_WL_CTRL_EN 15 +#define HALMAC_DBG_GNT_WL_BT 16 +#define HALMAC_BT_3DDLS_A 17 +#define HALMAC_BT_3DDLS_B 18 +#define HALMAC_BT_PTA 19 +#define HALMAC_WL_PTA 20 +#define HALMAC_WL_UART 21 +#define HALMAC_WLMAC_DBG 22 +#define HALMAC_WLPHY_DBG 23 +#define HALMAC_BT_DBG 24 +#define HALMAC_WLPHY_RFE_CTRL2GPIO 25 +#define HALMAC_EXT_XTAL 26 +#define HALMAC_SW_IO 27 + +typedef struct _HALMAC_GPIO_PIMUX_LIST { + u16 func; + u8 id; + u8 type; + u16 offset; + u8 msk; + u8 value; +} HALMAC_GPIO_PIMUX_LIST, *PHALMAC_GPIO_PIMUX_LIST; + +#endif diff --git a/hal/halmac/halmac_intf_phy_cmd.h b/hal/halmac/halmac_intf_phy_cmd.h new file mode 100644 index 0000000..a4be694 --- /dev/null +++ b/hal/halmac/halmac_intf_phy_cmd.h @@ -0,0 +1,45 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef HALMAC_INTF_PHY_CMD +#define HALMAC_INTF_PHY_CMD + +/* Cut mask */ +typedef enum _HALMAC_INTF_PHY_CUT { + HALMAC_INTF_PHY_CUT_TESTCHIP = BIT(0), + HALMAC_INTF_PHY_CUT_A = BIT(1), + HALMAC_INTF_PHY_CUT_B = BIT(2), + HALMAC_INTF_PHY_CUT_C = BIT(3), + HALMAC_INTF_PHY_CUT_D = BIT(4), + HALMAC_INTF_PHY_CUT_E = BIT(5), + HALMAC_INTF_PHY_CUT_F = BIT(6), + HALMAC_INTF_PHY_CUT_G = BIT(7), + HALMAC_INTF_PHY_CUT_ALL = 0x7FFF, +} HALMAC_INTF_PHY_CUT; + +/* IP selection */ +typedef enum _HALMAC_IP_SEL { + HALMAC_IP_SEL_INTF_PHY = 0, + HALMAC_IP_SEL_MAC = 1, + HALMAC_IP_SEL_PCIE_DBI = 2, + HALMAC_IP_SEL_UNDEFINE = 0x7FFF, +} HALMAC_IP_SEL; + +/* Platform mask */ +typedef enum _HALMAC_INTF_PHY_PLATFORM { + HALMAC_INTF_PHY_PLATFORM_ALL = 0x7FFF, +} HALMAC_INTF_PHY_PLATFORM; + +#endif diff --git a/hal/halmac/halmac_reg_8197f.h b/hal/halmac/halmac_reg_8197f.h new file mode 100644 index 0000000..997f6b0 --- /dev/null +++ b/hal/halmac/halmac_reg_8197f.h @@ -0,0 +1,697 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef __INC_HALMAC_REG_8197F_H +#define __INC_HALMAC_REG_8197F_H + +#define REG_SYS_ISO_CTRL_8197F 0x0000 +#define REG_SYS_FUNC_EN_8197F 0x0002 +#define REG_SYS_PW_CTRL_8197F 0x0004 +#define REG_SYS_CLK_CTRL_8197F 0x0008 +#define REG_SYS_EEPROM_CTRL_8197F 0x000A +#define REG_EE_VPD_8197F 0x000C +#define REG_SYS_SWR_CTRL1_8197F 0x0010 +#define REG_SYS_SWR_CTRL2_8197F 0x0014 +#define REG_SYS_SWR_CTRL3_8197F 0x0018 +#define REG_RSV_CTRL_8197F 0x001C +#define REG_RF0_CTRL_8197F 0x001F +#define REG_AFE_LDO_CTRL_8197F 0x0020 +#define REG_AFE_CTRL1_8197F 0x0024 +#define REG_AFE_CTRL2_8197F 0x0028 +#define REG_AFE_CTRL3_8197F 0x002C +#define REG_EFUSE_CTRL_8197F 0x0030 +#define REG_LDO_EFUSE_CTRL_8197F 0x0034 +#define REG_PWR_OPTION_CTRL_8197F 0x0038 +#define REG_CAL_TIMER_8197F 0x003C +#define REG_ACLK_MON_8197F 0x003E +#define REG_GPIO_MUXCFG_8197F 0x0040 +#define REG_GPIO_PIN_CTRL_8197F 0x0044 +#define REG_GPIO_INTM_8197F 0x0048 +#define REG_LED_CFG_8197F 0x004C +#define REG_FSIMR_8197F 0x0050 +#define REG_FSISR_8197F 0x0054 +#define REG_HSIMR_8197F 0x0058 +#define REG_HSISR_8197F 0x005C +#define REG_GPIO_EXT_CTRL_8197F 0x0060 +#define REG_PAD_CTRL1_8197F 0x0064 +#define REG_WL_BT_PWR_CTRL_8197F 0x0068 +#define REG_SDM_DEBUG_8197F 0x006C +#define REG_SYS_SDIO_CTRL_8197F 0x0070 +#define REG_HCI_OPT_CTRL_8197F 0x0074 +#define REG_AFE_CTRL4_8197F 0x0078 +#define REG_LDO_SWR_CTRL_8197F 0x007C +#define REG_MCUFW_CTRL_8197F 0x0080 +#define REG_MCU_TST_CFG_8197F 0x0084 +#define REG_HMEBOX_E0_E1_8197F 0x0088 +#define REG_HMEBOX_E2_E3_8197F 0x008C +#define REG_WLLPS_CTRL_8197F 0x0090 +#define REG_AFE_CTRL5_8197F 0x0094 +#define REG_GPIO_DEBOUNCE_CTRL_8197F 0x0098 +#define REG_RPWM2_8197F 0x009C +#define REG_SYSON_FSM_MON_8197F 0x00A0 +#define REG_AFE_CTRL6_8197F 0x00A4 +#define REG_PMC_DBG_CTRL1_8197F 0x00A8 +#define REG_AFE_CTRL7_8197F 0x00AC +#define REG_HIMR0_8197F 0x00B0 +#define REG_HISR0_8197F 0x00B4 +#define REG_HIMR1_8197F 0x00B8 +#define REG_HISR1_8197F 0x00BC +#define REG_DBG_PORT_SEL_8197F 0x00C0 +#define REG_PAD_CTRL2_8197F 0x00C4 +#define REG_PMC_DBG_CTRL2_8197F 0x00CC +#define REG_BIST_CTRL_8197F 0x00D0 +#define REG_BIST_RPT_8197F 0x00D4 +#define REG_MEM_CTRL_8197F 0x00D8 +#define REG_AFE_CTRL8_8197F 0x00DC +#define REG_USB_SIE_INTF_8197F 0x00E0 +#define REG_PCIE_MIO_INTF_8197F 0x00E4 +#define REG_PCIE_MIO_INTD_8197F 0x00E8 +#define REG_WLRF1_8197F 0x00EC +#define REG_SYS_CFG1_8197F 0x00F0 +#define REG_SYS_STATUS1_8197F 0x00F4 +#define REG_SYS_STATUS2_8197F 0x00F8 +#define REG_SYS_CFG2_8197F 0x00FC +#define REG_SYS_CFG3_8197F 0x1000 +#define REG_SYS_CFG4_8197F 0x1034 +#define REG_CPU_DMEM_CON_8197F 0x1080 +#define REG_HIMR2_8197F 0x10B0 +#define REG_HISR2_8197F 0x10B4 +#define REG_HIMR3_8197F 0x10B8 +#define REG_HISR3_8197F 0x10BC +#define REG_SW_MDIO_8197F 0x10C0 +#define REG_SW_FLUSH_8197F 0x10C4 +#define REG_DBG_GPIO_BMUX_8197F 0x10C8 +#define REG_FPGA_TAG_8197F 0x10CC +#define REG_WL_DSS_CTRL0_8197F 0x10D0 +#define REG_WL_DSS_CTRL1_8197F 0x10D8 +#define REG_WL_DSS_STATUS1_8197F 0x10DC +#define REG_FW_DBG0_8197F 0x10E0 +#define REG_FW_DBG1_8197F 0x10E4 +#define REG_FW_DBG2_8197F 0x10E8 +#define REG_FW_DBG3_8197F 0x10EC +#define REG_FW_DBG4_8197F 0x10F0 +#define REG_FW_DBG5_8197F 0x10F4 +#define REG_FW_DBG6_8197F 0x10F8 +#define REG_FW_DBG7_8197F 0x10FC +#define REG_CR_8197F 0x0100 +#define REG_TSF_CLK_STATE_8197F 0x0108 +#define REG_TXDMA_PQ_MAP_8197F 0x010C +#define REG_TRXFF_BNDY_8197F 0x0114 +#define REG_PTA_I2C_MBOX_8197F 0x0118 +#define REG_RXFF_BNDY_8197F 0x011C +#define REG_FE1IMR_8197F 0x0120 +#define REG_FE1ISR_8197F 0x0124 +#define REG_CPWM_8197F 0x012C +#define REG_FWIMR_8197F 0x0130 +#define REG_FWISR_8197F 0x0134 +#define REG_FTIMR_8197F 0x0138 +#define REG_FTISR_8197F 0x013C +#define REG_PKTBUF_DBG_CTRL_8197F 0x0140 +#define REG_PKTBUF_DBG_DATA_L_8197F 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8197F 0x0148 +#define REG_CPWM2_8197F 0x014C +#define REG_TC0_CTRL_8197F 0x0150 +#define REG_TC1_CTRL_8197F 0x0154 +#define REG_TC2_CTRL_8197F 0x0158 +#define REG_TC3_CTRL_8197F 0x015C +#define REG_TC4_CTRL_8197F 0x0160 +#define REG_TCUNIT_BASE_8197F 0x0164 +#define REG_TC5_CTRL_8197F 0x0168 +#define REG_TC6_CTRL_8197F 0x016C +#define REG_MBIST_FAIL_8197F 0x0170 +#define REG_MBIST_START_PAUSE_8197F 0x0174 +#define REG_MBIST_DONE_8197F 0x0178 +#define REG_MBIST_FAIL_NRML_8197F 0x017C +#define REG_AES_DECRPT_DATA_8197F 0x0180 +#define REG_AES_DECRPT_CFG_8197F 0x0184 +#define REG_MACCLKFRQ_8197F 0x018C +#define REG_TMETER_8197F 0x0190 +#define REG_OSC_32K_CTRL_8197F 0x0194 +#define REG_32K_CAL_REG1_8197F 0x0198 +#define REG_C2HEVT_8197F 0x01A0 +#define REG_SW_DEFINED_PAGE1_8197F 0x01B8 +#define REG_MCUTST_I_8197F 0x01C0 +#define REG_MCUTST_II_8197F 0x01C4 +#define REG_FMETHR_8197F 0x01C8 +#define REG_HMETFR_8197F 0x01CC +#define REG_HMEBOX0_8197F 0x01D0 +#define REG_HMEBOX1_8197F 0x01D4 +#define REG_HMEBOX2_8197F 0x01D8 +#define REG_HMEBOX3_8197F 0x01DC +#define REG_LLT_INIT_8197F 0x01E0 +#define REG_LLT_INIT_ADDR_8197F 0x01E4 +#define REG_BB_ACCESS_CTRL_8197F 0x01E8 +#define REG_BB_ACCESS_DATA_8197F 0x01EC +#define REG_HMEBOX_E0_8197F 0x01F0 +#define REG_HMEBOX_E1_8197F 0x01F4 +#define REG_HMEBOX_E2_8197F 0x01F8 +#define REG_HMEBOX_E3_8197F 0x01FC +#define REG_CR_EXT_8197F 0x1100 +#define REG_FWFF_8197F 0x1114 +#define REG_RXFF_PTR_V1_8197F 0x1118 +#define REG_RXFF_WTR_V1_8197F 0x111C +#define REG_FE2IMR_8197F 0x1120 +#define REG_FE2ISR_8197F 0x1124 +#define REG_FE3IMR_8197F 0x1128 +#define REG_FE3ISR_8197F 0x112C +#define REG_FE4IMR_8197F 0x1130 +#define REG_FE4ISR_8197F 0x1134 +#define REG_FT1IMR_8197F 0x1138 +#define REG_FT1ISR_8197F 0x113C +#define REG_SPWR0_8197F 0x1140 +#define REG_SPWR1_8197F 0x1144 +#define REG_SPWR2_8197F 0x1148 +#define REG_SPWR3_8197F 0x114C +#define REG_POWSEQ_8197F 0x1150 +#define REG_TC7_CTRL_V1_8197F 0x1158 +#define REG_TC8_CTRL_V1_8197F 0x115C +#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F 0x1160 +#define REG_RXBCN_TBTT_INTERVAL_PORT4_8197F 0x1164 +#define REG_EXT_QUEUE_REG_8197F 0x11C0 +#define REG_COUNTER_CONTROL_8197F 0x11C4 +#define REG_COUNTER_TH_8197F 0x11C8 +#define REG_COUNTER_SET_8197F 0x11CC +#define REG_COUNTER_OVERFLOW_8197F 0x11D0 +#define REG_TDE_LEN_TH_8197F 0x11D4 +#define REG_RDE_LEN_TH_8197F 0x11D8 +#define REG_PCIE_EXEC_TIME_8197F 0x11DC +#define REG_FT2IMR_8197F 0x11E0 +#define REG_FT2ISR_8197F 0x11E4 +#define REG_MSG2_8197F 0x11F0 +#define REG_MSG3_8197F 0x11F4 +#define REG_MSG4_8197F 0x11F8 +#define REG_MSG5_8197F 0x11FC +#define REG_FIFOPAGE_CTRL_1_8197F 0x0200 +#define REG_FIFOPAGE_CTRL_2_8197F 0x0204 +#define REG_AUTO_LLT_V1_8197F 0x0208 +#define REG_TXDMA_OFFSET_CHK_8197F 0x020C +#define REG_TXDMA_STATUS_8197F 0x0210 +#define REG_TX_DMA_DBG_8197F 0x0214 +#define REG_TQPNT1_8197F 0x0218 +#define REG_TQPNT2_8197F 0x021C +#define REG_TQPNT3_8197F 0x0220 +#define REG_TQPNT4_8197F 0x0224 +#define REG_RQPN_CTRL_1_8197F 0x0228 +#define REG_RQPN_CTRL_2_8197F 0x022C +#define REG_FIFOPAGE_INFO_1_8197F 0x0230 +#define REG_FIFOPAGE_INFO_2_8197F 0x0234 +#define REG_FIFOPAGE_INFO_3_8197F 0x0238 +#define REG_FIFOPAGE_INFO_4_8197F 0x023C +#define REG_FIFOPAGE_INFO_5_8197F 0x0240 +#define REG_H2C_HEAD_8197F 0x0244 +#define REG_H2C_TAIL_8197F 0x0248 +#define REG_H2C_READ_ADDR_8197F 0x024C +#define REG_H2C_WR_ADDR_8197F 0x0250 +#define REG_H2C_INFO_8197F 0x0254 +#define REG_RXDMA_AGG_PG_TH_8197F 0x0280 +#define REG_RXPKT_NUM_8197F 0x0284 +#define REG_RXDMA_STATUS_8197F 0x0288 +#define REG_RXDMA_DPR_8197F 0x028C +#define REG_RXDMA_MODE_8197F 0x0290 +#define REG_C2H_PKT_8197F 0x0294 +#define REG_FWFF_C2H_8197F 0x0298 +#define REG_FWFF_CTRL_8197F 0x029C +#define REG_FWFF_PKT_INFO_8197F 0x02A0 +#define REG_FC2H_INFO_8197F 0x02A6 +#define REG_DDMA_CH0SA_8197F 0x1200 +#define REG_DDMA_CH0DA_8197F 0x1204 +#define REG_DDMA_CH0CTRL_8197F 0x1208 +#define REG_DDMA_CH1SA_8197F 0x1210 +#define REG_DDMA_CH1DA_8197F 0x1214 +#define REG_DDMA_CH1CTRL_8197F 0x1218 +#define REG_DDMA_CH2SA_8197F 0x1220 +#define REG_DDMA_CH2DA_8197F 0x1224 +#define REG_DDMA_CH2CTRL_8197F 0x1228 +#define REG_DDMA_CH3SA_8197F 0x1230 +#define REG_DDMA_CH3DA_8197F 0x1234 +#define REG_DDMA_CH3CTRL_8197F 0x1238 +#define REG_DDMA_CH4SA_8197F 0x1240 +#define REG_DDMA_CH4DA_8197F 0x1244 +#define REG_DDMA_CH4CTRL_8197F 0x1248 +#define REG_DDMA_CH5SA_8197F 0x1250 +#define REG_DDMA_CH5DA_8197F 0x1254 +#define REG_REG_DDMA_CH5CTRL_8197F 0x1258 +#define REG_DDMA_INT_MSK_8197F 0x12E0 +#define REG_DDMA_CHSTATUS_8197F 0x12E8 +#define REG_DDMA_CHKSUM_8197F 0x12F0 +#define REG_DDMA_MONITOR_8197F 0x12FC +#define REG_HCI_CTRL_8197F 0x0300 +#define REG_INT_MIG_8197F 0x0304 +#define REG_BCNQ_TXBD_DESA_8197F 0x0308 +#define REG_MGQ_TXBD_DESA_8197F 0x0310 +#define REG_VOQ_TXBD_DESA_8197F 0x0318 +#define REG_VIQ_TXBD_DESA_8197F 0x0320 +#define REG_BEQ_TXBD_DESA_8197F 0x0328 +#define REG_BKQ_TXBD_DESA_8197F 0x0330 +#define REG_RXQ_RXBD_DESA_8197F 0x0338 +#define REG_HI0Q_TXBD_DESA_8197F 0x0340 +#define REG_HI1Q_TXBD_DESA_8197F 0x0348 +#define REG_HI2Q_TXBD_DESA_8197F 0x0350 +#define REG_HI3Q_TXBD_DESA_8197F 0x0358 +#define REG_HI4Q_TXBD_DESA_8197F 0x0360 +#define REG_HI5Q_TXBD_DESA_8197F 0x0368 +#define REG_HI6Q_TXBD_DESA_8197F 0x0370 +#define REG_HI7Q_TXBD_DESA_8197F 0x0378 +#define REG_MGQ_TXBD_NUM_8197F 0x0380 +#define REG_RX_RXBD_NUM_8197F 0x0382 +#define REG_VOQ_TXBD_NUM_8197F 0x0384 +#define REG_VIQ_TXBD_NUM_8197F 0x0386 +#define REG_BEQ_TXBD_NUM_8197F 0x0388 +#define REG_BKQ_TXBD_NUM_8197F 0x038A +#define REG_HI0Q_TXBD_NUM_8197F 0x038C +#define REG_HI1Q_TXBD_NUM_8197F 0x038E +#define REG_HI2Q_TXBD_NUM_8197F 0x0390 +#define REG_HI3Q_TXBD_NUM_8197F 0x0392 +#define REG_HI4Q_TXBD_NUM_8197F 0x0394 +#define REG_HI5Q_TXBD_NUM_8197F 0x0396 +#define REG_HI6Q_TXBD_NUM_8197F 0x0398 +#define REG_HI7Q_TXBD_NUM_8197F 0x039A +#define REG_TSFTIMER_HCI_8197F 0x039C +#define REG_BD_RWPTR_CLR_8197F 0x039C +#define REG_VOQ_TXBD_IDX_8197F 0x03A0 +#define REG_VIQ_TXBD_IDX_8197F 0x03A4 +#define REG_BEQ_TXBD_IDX_8197F 0x03A8 +#define REG_BKQ_TXBD_IDX_8197F 0x03AC +#define REG_MGQ_TXBD_IDX_8197F 0x03B0 +#define REG_RXQ_RXBD_IDX_8197F 0x03B4 +#define REG_HI0Q_TXBD_IDX_8197F 0x03B8 +#define REG_HI1Q_TXBD_IDX_8197F 0x03BC +#define REG_HI2Q_TXBD_IDX_8197F 0x03C0 +#define REG_HI3Q_TXBD_IDX_8197F 0x03C4 +#define REG_HI4Q_TXBD_IDX_8197F 0x03C8 +#define REG_HI5Q_TXBD_IDX_8197F 0x03CC +#define REG_HI6Q_TXBD_IDX_8197F 0x03D0 +#define REG_HI7Q_TXBD_IDX_8197F 0x03D4 +#define REG_DBG_SEL_V1_8197F 0x03D8 +#define REG_HCI_HRPWM1_V1_8197F 0x03D9 +#define REG_HCI_HCPWM1_V1_8197F 0x03DA +#define REG_HCI_CTRL2_8197F 0x03DB +#define REG_HCI_HRPWM2_V1_8197F 0x03DC +#define REG_HCI_HCPWM2_V1_8197F 0x03DE +#define REG_HCI_H2C_MSG_V1_8197F 0x03E0 +#define REG_HCI_C2H_MSG_V1_8197F 0x03E4 +#define REG_DBI_WDATA_V1_8197F 0x03E8 +#define REG_DBI_RDATA_V1_8197F 0x03EC +#define REG_STUCK_FLAG_V1_8197F 0x03F0 +#define REG_MDIO_V1_8197F 0x03F4 +#define REG_WDT_CFG_8197F 0x03F8 +#define REG_HCI_MIX_CFG_8197F 0x03FC +#define REG_STC_INT_CS_8197F 0x1300 +#define REG_ST_INT_CFG_8197F 0x1304 +#define REG_CMU_DLY_CTRL_8197F 0x1310 +#define REG_CMU_DLY_CFG_8197F 0x1314 +#define REG_H2CQ_TXBD_DESA_8197F 0x1320 +#define REG_H2CQ_TXBD_NUM_8197F 0x1328 +#define REG_H2CQ_TXBD_IDX_8197F 0x132C +#define REG_H2CQ_CSR_8197F 0x1330 +#define REG_AXI_EXCEPT_CS_8197F 0x1350 +#define REG_AXI_EXCEPT_TIME_8197F 0x1354 +#define REG_Q0_INFO_8197F 0x0400 +#define REG_Q1_INFO_8197F 0x0404 +#define REG_Q2_INFO_8197F 0x0408 +#define REG_Q3_INFO_8197F 0x040C +#define REG_MGQ_INFO_8197F 0x0410 +#define REG_HIQ_INFO_8197F 0x0414 +#define REG_BCNQ_INFO_8197F 0x0418 +#define REG_TXPKT_EMPTY_8197F 0x041A +#define REG_CPU_MGQ_INFO_8197F 0x041C +#define REG_FWHW_TXQ_CTRL_8197F 0x0420 +#define REG_BCNQ_BDNY_V1_8197F 0x0424 +#define REG_LIFETIME_EN_8197F 0x0426 +#define REG_SPEC_SIFS_8197F 0x0428 +#define REG_RETRY_LIMIT_8197F 0x042A +#define REG_TXBF_CTRL_8197F 0x042C +#define REG_DARFRC_8197F 0x0430 +#define REG_RARFRC_8197F 0x0438 +#define REG_RRSR_8197F 0x0440 +#define REG_ARFR0_8197F 0x0444 +#define REG_ARFR1_V1_8197F 0x044C +#define REG_CCK_CHECK_8197F 0x0454 +#define REG_AMPDU_MAX_TIME_V1_8197F 0x0455 +#define REG_BCNQ1_BDNY_V1_8197F 0x0456 +#define REG_AMPDU_MAX_LENGTH_8197F 0x0458 +#define REG_ACQ_STOP_8197F 0x045C +#define REG_NDPA_RATE_8197F 0x045D +#define REG_TX_HANG_CTRL_8197F 0x045E +#define REG_NDPA_OPT_CTRL_8197F 0x045F +#define REG_RD_RESP_PKT_TH_8197F 0x0463 +#define REG_CMDQ_INFO_8197F 0x0464 +#define REG_Q4_INFO_8197F 0x0468 +#define REG_Q5_INFO_8197F 0x046C +#define REG_Q6_INFO_8197F 0x0470 +#define REG_Q7_INFO_8197F 0x0474 +#define REG_WMAC_LBK_BUF_HD_V1_8197F 0x0478 +#define REG_MGQ_BDNY_V1_8197F 0x047A +#define REG_TXRPT_CTRL_8197F 0x047C +#define REG_INIRTS_RATE_SEL_8197F 0x0480 +#define REG_BASIC_CFEND_RATE_8197F 0x0481 +#define REG_STBC_CFEND_RATE_8197F 0x0482 +#define REG_DATA_SC_8197F 0x0483 +#define REG_MACID_SLEEP3_8197F 0x0484 +#define REG_MACID_SLEEP1_8197F 0x0488 +#define REG_ARFR2_V1_8197F 0x048C +#define REG_ARFR3_V1_8197F 0x0494 +#define REG_ARFR4_8197F 0x049C +#define REG_ARFR5_8197F 0x04A4 +#define REG_TXRPT_START_OFFSET_8197F 0x04AC +#define REG_POWER_STAGE1_8197F 0x04B4 +#define REG_POWER_STAGE2_8197F 0x04B8 +#define REG_SW_AMPDU_BURST_MODE_CTRL_8197F 0x04BC +#define REG_PKT_LIFE_TIME_8197F 0x04C0 +#define REG_STBC_SETTING_8197F 0x04C4 +#define REG_STBC_SETTING2_8197F 0x04C5 +#define REG_QUEUE_CTRL_8197F 0x04C6 +#define REG_SINGLE_AMPDU_CTRL_8197F 0x04C7 +#define REG_PROT_MODE_CTRL_8197F 0x04C8 +#define REG_BAR_MODE_CTRL_8197F 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8197F 0x04CF +#define REG_MACID_SLEEP2_8197F 0x04D0 +#define REG_MACID_SLEEP_8197F 0x04D4 +#define REG_HW_SEQ0_8197F 0x04D8 +#define REG_HW_SEQ1_8197F 0x04DA +#define REG_HW_SEQ2_8197F 0x04DC +#define REG_HW_SEQ3_8197F 0x04DE +#define REG_NULL_PKT_STATUS_V1_8197F 0x04E0 +#define REG_PTCL_ERR_STATUS_8197F 0x04E2 +#define REG_NULL_PKT_STATUS_EXTEND_8197F 0x04E3 +#define REG_VIDEO_ENHANCEMENT_FUN_8197F 0x04E4 +#define REG_BT_POLLUTE_PKT_CNT_8197F 0x04E8 +#define REG_PTCL_DBG_8197F 0x04EC +#define REG_TXOP_EXTRA_CTRL_8197F 0x04F0 +#define REG_CPUMGQ_TIMER_CTRL2_8197F 0x04F4 +#define REG_DUMMY_PAGE4_8197F 0x04FC +#define REG_Q0_Q1_INFO_8197F 0x1400 +#define REG_Q2_Q3_INFO_8197F 0x1404 +#define REG_Q4_Q5_INFO_8197F 0x1408 +#define REG_Q6_Q7_INFO_8197F 0x140C +#define REG_MGQ_HIQ_INFO_8197F 0x1410 +#define REG_CMDQ_BCNQ_INFO_8197F 0x1414 +#define REG_USEREG_SETTING_8197F 0x1420 +#define REG_AESIV_SETTING_8197F 0x1424 +#define REG_BF0_TIME_SETTING_8197F 0x1428 +#define REG_BF1_TIME_SETTING_8197F 0x142C +#define REG_BF_TIMEOUT_EN_8197F 0x1430 +#define REG_MACID_RELEASE0_8197F 0x1434 +#define REG_MACID_RELEASE1_8197F 0x1438 +#define REG_MACID_RELEASE2_8197F 0x143C +#define REG_MACID_RELEASE3_8197F 0x1440 +#define REG_MACID_RELEASE_SETTING_8197F 0x1444 +#define REG_FAST_EDCA_VOVI_SETTING_8197F 0x1448 +#define REG_FAST_EDCA_BEBK_SETTING_8197F 0x144C +#define REG_MACID_DROP0_8197F 0x1450 +#define REG_MACID_DROP1_8197F 0x1454 +#define REG_MACID_DROP2_8197F 0x1458 +#define REG_MACID_DROP3_8197F 0x145C +#define REG_R_MACID_RELEASE_SUCCESS_0_8197F 0x1460 +#define REG_R_MACID_RELEASE_SUCCESS_1_8197F 0x1464 +#define REG_R_MACID_RELEASE_SUCCESS_2_8197F 0x1468 +#define REG_R_MACID_RELEASE_SUCCESS_3_8197F 0x146C +#define REG_MGG_FIFO_CRTL_8197F 0x1470 +#define REG_MGG_FIFO_INT_8197F 0x1474 +#define REG_MGG_FIFO_LIFETIME_8197F 0x1478 +#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x147C +#define REG_SHCUT_SETTING_8197F 0x1480 +#define REG_SHCUT_LLC_ETH_TYPE0_8197F 0x1484 +#define REG_SHCUT_LLC_ETH_TYPE1_8197F 0x1488 +#define REG_SHCUT_LLC_OUI0_8197F 0x148C +#define REG_SHCUT_LLC_OUI1_8197F 0x1490 +#define REG_SHCUT_LLC_OUI2_8197F 0x1494 +#define REG_SHCUT_LLC_OUI3_8197F 0x1498 +#define REG_EDCA_VO_PARAM_8197F 0x0500 +#define REG_EDCA_VI_PARAM_8197F 0x0504 +#define REG_EDCA_BE_PARAM_8197F 0x0508 +#define REG_EDCA_BK_PARAM_8197F 0x050C +#define REG_BCNTCFG_8197F 0x0510 +#define REG_PIFS_8197F 0x0512 +#define REG_RDG_PIFS_8197F 0x0513 +#define REG_SIFS_8197F 0x0514 +#define REG_TSFTR_SYN_OFFSET_8197F 0x0518 +#define REG_AGGR_BREAK_TIME_8197F 0x051A +#define REG_SLOT_8197F 0x051B +#define REG_TX_PTCL_CTRL_8197F 0x0520 +#define REG_TXPAUSE_8197F 0x0522 +#define REG_DIS_TXREQ_CLR_8197F 0x0523 +#define REG_RD_CTRL_8197F 0x0524 +#define REG_MBSSID_CTRL_8197F 0x0526 +#define REG_P2PPS_CTRL_8197F 0x0527 +#define REG_PKT_LIFETIME_CTRL_8197F 0x0528 +#define REG_P2PPS_SPEC_STATE_8197F 0x052B +#define REG_QUEUE_INCOL_THR_8197F 0x0538 +#define REG_QUEUE_INCOL_EN_8197F 0x053C +#define REG_TBTT_PROHIBIT_8197F 0x0540 +#define REG_P2PPS_STATE_8197F 0x0543 +#define REG_RD_NAV_NXT_8197F 0x0544 +#define REG_NAV_PROT_LEN_8197F 0x0546 +#define REG_FTM_CTRL_8197F 0x0548 +#define REG_FTM_TSF_CNT_8197F 0x054C +#define REG_BCN_CTRL_8197F 0x0550 +#define REG_BCN_CTRL_CLINT0_8197F 0x0551 +#define REG_MBID_NUM_8197F 0x0552 +#define REG_DUAL_TSF_RST_8197F 0x0553 +#define REG_MBSSID_BCN_SPACE_8197F 0x0554 +#define REG_DRVERLYINT_8197F 0x0558 +#define REG_BCNDMATIM_8197F 0x0559 +#define REG_ATIMWND_8197F 0x055A +#define REG_USTIME_TSF_8197F 0x055C +#define REG_BCN_MAX_ERR_8197F 0x055D +#define REG_RXTSF_OFFSET_CCK_8197F 0x055E +#define REG_RXTSF_OFFSET_OFDM_8197F 0x055F +#define REG_TSFTR_8197F 0x0560 +#define REG_FREERUN_CNT_8197F 0x0568 +#define REG_ATIMWND1_8197F 0x0570 +#define REG_TBTT_PROHIBIT_INFRA_8197F 0x0571 +#define REG_CTWND_8197F 0x0572 +#define REG_BCNIVLCUNT_8197F 0x0573 +#define REG_BCNDROPCTRL_8197F 0x0574 +#define REG_HGQ_TIMEOUT_PERIOD_8197F 0x0575 +#define REG_TXCMD_TIMEOUT_PERIOD_8197F 0x0576 +#define REG_MISC_CTRL_8197F 0x0577 +#define REG_BCN_CTRL_CLINT1_8197F 0x0578 +#define REG_BCN_CTRL_CLINT2_8197F 0x0579 +#define REG_BCN_CTRL_CLINT3_8197F 0x057A +#define REG_EXTEND_CTRL_8197F 0x057B +#define REG_P2PPS1_SPEC_STATE_8197F 0x057C +#define REG_P2PPS1_STATE_8197F 0x057D +#define REG_P2PPS2_SPEC_STATE_8197F 0x057E +#define REG_P2PPS2_STATE_8197F 0x057F +#define REG_PS_TIMER0_8197F 0x0580 +#define REG_PS_TIMER1_8197F 0x0584 +#define REG_PS_TIMER2_8197F 0x0588 +#define REG_TBTT_CTN_AREA_8197F 0x058C +#define REG_FORCE_BCN_IFS_8197F 0x058E +#define REG_TXOP_MIN_8197F 0x0590 +#define REG_PRE_BKF_TIME_8197F 0x0592 +#define REG_CROSS_TXOP_CTRL_8197F 0x0593 +#define REG_TBTT_INT_SHIFT_CLI0_8197F 0x0594 +#define REG_TBTT_INT_SHIFT_CLI1_8197F 0x0595 +#define REG_TBTT_INT_SHIFT_CLI2_8197F 0x0596 +#define REG_TBTT_INT_SHIFT_CLI3_8197F 0x0597 +#define REG_TBTT_INT_SHIFT_ENABLE_8197F 0x0598 +#define REG_ATIMWND2_8197F 0x05A0 +#define REG_ATIMWND3_8197F 0x05A1 +#define REG_ATIMWND4_8197F 0x05A2 +#define REG_ATIMWND5_8197F 0x05A3 +#define REG_ATIMWND6_8197F 0x05A4 +#define REG_ATIMWND7_8197F 0x05A5 +#define REG_ATIMUGT_8197F 0x05A6 +#define REG_HIQ_NO_LMT_EN_8197F 0x05A7 +#define REG_DTIM_COUNTER_ROOT_8197F 0x05A8 +#define REG_DTIM_COUNTER_VAP1_8197F 0x05A9 +#define REG_DTIM_COUNTER_VAP2_8197F 0x05AA +#define REG_DTIM_COUNTER_VAP3_8197F 0x05AB +#define REG_DTIM_COUNTER_VAP4_8197F 0x05AC +#define REG_DTIM_COUNTER_VAP5_8197F 0x05AD +#define REG_DTIM_COUNTER_VAP6_8197F 0x05AE +#define REG_DTIM_COUNTER_VAP7_8197F 0x05AF +#define REG_DIS_ATIM_8197F 0x05B0 +#define REG_EARLY_128US_8197F 0x05B1 +#define REG_P2PPS1_CTRL_8197F 0x05B2 +#define REG_P2PPS2_CTRL_8197F 0x05B3 +#define REG_TIMER0_SRC_SEL_8197F 0x05B4 +#define REG_NOA_UNIT_SEL_8197F 0x05B5 +#define REG_P2POFF_DIS_TXTIME_8197F 0x05B7 +#define REG_MBSSID_BCN_SPACE2_8197F 0x05B8 +#define REG_MBSSID_BCN_SPACE3_8197F 0x05BC +#define REG_ACMHWCTRL_8197F 0x05C0 +#define REG_ACMRSTCTRL_8197F 0x05C1 +#define REG_ACMAVG_8197F 0x05C2 +#define REG_VO_ADMTIME_8197F 0x05C4 +#define REG_VI_ADMTIME_8197F 0x05C6 +#define REG_BE_ADMTIME_8197F 0x05C8 +#define REG_EDCA_RANDOM_GEN_8197F 0x05CC +#define REG_TXCMD_NOA_SEL_8197F 0x05CF +#define REG_NOA_PARAM_8197F 0x05E0 +#define REG_P2P_RST_8197F 0x05F0 +#define REG_SCHEDULER_RST_8197F 0x05F1 +#define REG_SCH_TXCMD_8197F 0x05F8 +#define REG_PAGE5_DUMMY_8197F 0x05FC +#define REG_CPUMGQ_TX_TIMER_8197F 0x1500 +#define REG_PS_TIMER_A_8197F 0x1504 +#define REG_PS_TIMER_B_8197F 0x1508 +#define REG_PS_TIMER_C_8197F 0x150C +#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F 0x1510 +#define REG_CPUMGQ_TX_TIMER_EARLY_8197F 0x1514 +#define REG_PS_TIMER_A_EARLY_8197F 0x1515 +#define REG_PS_TIMER_B_EARLY_8197F 0x1516 +#define REG_PS_TIMER_C_EARLY_8197F 0x1517 +#define REG_WMAC_CR_8197F 0x0600 +#define REG_WMAC_FWPKT_CR_8197F 0x0601 +#define REG_BWOPMODE_8197F 0x0603 +#define REG_TCR_8197F 0x0604 +#define REG_RCR_8197F 0x0608 +#define REG_RX_PKT_LIMIT_8197F 0x060C +#define REG_RX_DLK_TIME_8197F 0x060D +#define REG_RX_DRVINFO_SZ_8197F 0x060F +#define REG_MACID_8197F 0x0610 +#define REG_BSSID_8197F 0x0618 +#define REG_MAR_8197F 0x0620 +#define REG_MBIDCAMCFG_1_8197F 0x0628 +#define REG_MBIDCAMCFG_2_8197F 0x062C +#define REG_WMAC_TCR_TSFT_OFS_8197F 0x0630 +#define REG_UDF_THSD_8197F 0x0632 +#define REG_ZLD_NUM_8197F 0x0633 +#define REG_STMP_THSD_8197F 0x0634 +#define REG_WMAC_TXTIMEOUT_8197F 0x0635 +#define REG_MCU_TEST_2_V1_8197F 0x0636 +#define REG_USTIME_EDCA_8197F 0x0638 +#define REG_MAC_SPEC_SIFS_8197F 0x063A +#define REG_RESP_SIFS_CCK_8197F 0x063C +#define REG_RESP_SIFS_OFDM_8197F 0x063E +#define REG_ACKTO_8197F 0x0640 +#define REG_CTS2TO_8197F 0x0641 +#define REG_EIFS_8197F 0x0642 +#define REG_NAV_CTRL_8197F 0x0650 +#define REG_BACAMCMD_8197F 0x0654 +#define REG_BACAMCONTENT_8197F 0x0658 +#define REG_LBDLY_8197F 0x0660 +#define REG_WMAC_BACAM_RPMEN_8197F 0x0661 +#define REG_WMAC_BITMAP_CTL_8197F 0x0663 +#define REG_RXERR_RPT_8197F 0x0664 +#define REG_WMAC_TRXPTCL_CTL_8197F 0x0668 +#define REG_CAMCMD_8197F 0x0670 +#define REG_CAMWRITE_8197F 0x0674 +#define REG_CAMREAD_8197F 0x0678 +#define REG_CAMDBG_8197F 0x067C +#define REG_SECCFG_8197F 0x0680 +#define REG_RXFILTER_CATEGORY_1_8197F 0x0682 +#define REG_RXFILTER_ACTION_1_8197F 0x0683 +#define REG_RXFILTER_CATEGORY_2_8197F 0x0684 +#define REG_RXFILTER_ACTION_2_8197F 0x0685 +#define REG_RXFILTER_CATEGORY_3_8197F 0x0686 +#define REG_RXFILTER_ACTION_3_8197F 0x0687 +#define REG_RXFLTMAP3_8197F 0x0688 +#define REG_RXFLTMAP4_8197F 0x068A +#define REG_RXFLTMAP5_8197F 0x068C +#define REG_RXFLTMAP6_8197F 0x068E +#define REG_WOW_CTRL_8197F 0x0690 +#define REG_PS_RX_INFO_8197F 0x0692 +#define REG_WMMPS_UAPSD_TID_8197F 0x0693 +#define REG_LPNAV_CTRL_8197F 0x0694 +#define REG_WKFMCAM_CMD_8197F 0x0698 +#define REG_WKFMCAM_RWD_8197F 0x069C +#define REG_RXFLTMAP0_8197F 0x06A0 +#define REG_RXFLTMAP1_8197F 0x06A2 +#define REG_RXFLTMAP_8197F 0x06A4 +#define REG_BCN_PSR_RPT_8197F 0x06A8 +#define REG_RXPKTMON_CTRL_8197F 0x06B0 +#define REG_STATE_MON_8197F 0x06B4 +#define REG_ERROR_MON_8197F 0x06B8 +#define REG_SEARCH_MACID_8197F 0x06BC +#define REG_BT_COEX_TABLE_8197F 0x06C0 +#define REG_RXCMD_0_8197F 0x06D0 +#define REG_RXCMD_1_8197F 0x06D4 +#define REG_WMAC_RESP_TXINFO_8197F 0x06D8 +#define REG_BBPSF_CTRL_8197F 0x06DC +#define REG_P2P_RX_BCN_NOA_8197F 0x06E0 +#define REG_ASSOCIATED_BFMER0_INFO_8197F 0x06E4 +#define REG_ASSOCIATED_BFMER1_INFO_8197F 0x06EC +#define REG_TX_CSI_RPT_PARAM_BW20_8197F 0x06F4 +#define REG_TX_CSI_RPT_PARAM_BW40_8197F 0x06F8 +#define REG_TX_CSI_RPT_PARAM_BW80_8197F 0x06FC +#define REG_BCN_PSR_RPT2_8197F 0x1600 +#define REG_BCN_PSR_RPT3_8197F 0x1604 +#define REG_BCN_PSR_RPT4_8197F 0x1608 +#define REG_A1_ADDR_MASK_8197F 0x160C +#define REG_MACID2_8197F 0x1620 +#define REG_BSSID2_8197F 0x1628 +#define REG_MACID3_8197F 0x1630 +#define REG_BSSID3_8197F 0x1638 +#define REG_MACID4_8197F 0x1640 +#define REG_BSSID4_8197F 0x1648 +#define REG_NOA_REPORT_8197F 0x1650 +#define REG_PWRBIT_SETTING_8197F 0x1660 +#define REG_WMAC_MU_BF_OPTION_8197F 0x167C +#define REG_WMAC_PAUSE_BB_CLR_TH_8197F 0x167D +#define REG_WMAC_MU_ARB_8197F 0x167E +#define REG_WMAC_MU_OPTION_8197F 0x167F +#define REG_WMAC_MU_BF_CTL_8197F 0x1680 +#define REG_WMAC_MU_BFRPT_PARA_8197F 0x1682 +#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F 0x1684 +#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F 0x1686 +#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F 0x1688 +#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F 0x168A +#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F 0x168C +#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F 0x168E +#define REG_TRANSMIT_ADDRSS_0_8197F 0x16A0 +#define REG_TRANSMIT_ADDRSS_1_8197F 0x16A8 +#define REG_TRANSMIT_ADDRSS_2_8197F 0x16B0 +#define REG_TRANSMIT_ADDRSS_3_8197F 0x16B8 +#define REG_TRANSMIT_ADDRSS_4_8197F 0x16C0 +#define REG_MACID1_8197F 0x0700 +#define REG_BSSID1_8197F 0x0708 +#define REG_BCN_PSR_RPT1_8197F 0x0710 +#define REG_ASSOCIATED_BFMEE_SEL_8197F 0x0714 +#define REG_SND_PTCL_CTRL_8197F 0x0718 +#define REG_RX_CSI_RPT_INFO_8197F 0x071C +#define REG_NS_ARP_CTRL_8197F 0x0720 +#define REG_NS_ARP_INFO_8197F 0x0724 +#define REG_BEAMFORMING_INFO_NSARP_V1_8197F 0x0728 +#define REG_BEAMFORMING_INFO_NSARP_8197F 0x072C +#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8197F 0x0750 +#define REG_WMAC_SWAES_CFG_8197F 0x0760 +#define REG_BT_COEX_V2_8197F 0x0762 +#define REG_BT_COEX_8197F 0x0764 +#define REG_WLAN_ACT_MASK_CTRL_8197F 0x0768 +#define REG_BT_COEX_ENHANCED_INTR_CTRL_8197F 0x076E +#define REG_BT_ACT_STATISTICS_8197F 0x0770 +#define REG_BT_STATISTICS_CONTROL_REGISTER_8197F 0x0778 +#define REG_BT_STATUS_REPORT_REGISTER_8197F 0x077C +#define REG_BT_INTERRUPT_CONTROL_REGISTER_8197F 0x0780 +#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F 0x0784 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F 0x0785 +#define REG_BT_INTERRUPT_STATUS_REGISTER_8197F 0x078F +#define REG_BT_TDMA_TIME_REGISTER_8197F 0x0790 +#define REG_BT_ACT_REGISTER_8197F 0x0794 +#define REG_OBFF_CTRL_BASIC_8197F 0x0798 +#define REG_OBFF_CTRL2_TIMER_8197F 0x079C +#define REG_LTR_CTRL_BASIC_8197F 0x07A0 +#define REG_LTR_CTRL2_TIMER_THRESHOLD_8197F 0x07A4 +#define REG_LTR_IDLE_LATENCY_V1_8197F 0x07A8 +#define REG_LTR_ACTIVE_LATENCY_V1_8197F 0x07AC +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F 0x07B0 +#define REG_WMAC_PKTCNT_RWD_8197F 0x07B8 +#define REG_WMAC_PKTCNT_CTRL_8197F 0x07BC +#define REG_IQ_DUMP_8197F 0x07C0 +#define REG_WMAC_FTM_CTL_8197F 0x07CC +#define REG_IQ_DUMP_EXT_8197F 0x07CF +#define REG_OFDM_CCK_LEN_MASK_8197F 0x07D0 +#define REG_RX_FILTER_FUNCTION_8197F 0x07DA +#define REG_NDP_SIG_8197F 0x07E0 +#define REG_TXCMD_INFO_FOR_RSP_PKT_8197F 0x07E4 +#define REG_SEC_OPT_V2_8197F 0x07EC +#define REG_RTS_ADDRESS_0_8197F 0x07F0 +#define REG_RTS_ADDRESS_1_8197F 0x07F8 + +#endif diff --git a/hal/halmac/halmac_reg_8814b.h b/hal/halmac/halmac_reg_8814b.h new file mode 100644 index 0000000..ac587a5 --- /dev/null +++ b/hal/halmac/halmac_reg_8814b.h @@ -0,0 +1,751 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef __INC_HALMAC_REG_8814B_H +#define __INC_HALMAC_REG_8814B_H + +#define REG_SYS_ISO_CTRL_8814B 0x0000 +#define REG_SYS_FUNC_EN_8814B 0x0002 +#define REG_SYS_PW_CTRL_8814B 0x0004 +#define REG_SYS_CLK_CTRL_8814B 0x0008 +#define REG_SYS_EEPROM_CTRL_8814B 0x000A +#define REG_EE_VPD_8814B 0x000C +#define REG_SYS_SWR_CTRL1_8814B 0x0010 +#define REG_SYS_SWR_CTRL2_8814B 0x0014 +#define REG_SYS_SWR_CTRL3_8814B 0x0018 +#define REG_RSV_CTRL_8814B 0x001C +#define REG_RF_CTRL_8814B 0x001F +#define REG_AFE_LDO_CTRL_8814B 0x0020 +#define REG_AFE_CTRL1_8814B 0x0024 +#define REG_AFE_CTRL2_8814B 0x0028 +#define REG_AFE_CTRL3_8814B 0x002C +#define REG_EFUSE_CTRL_8814B 0x0030 +#define REG_LDO_EFUSE_CTRL_8814B 0x0034 +#define REG_PWR_OPTION_CTRL_8814B 0x0038 +#define REG_CAL_TIMER_8814B 0x003C +#define REG_ACLK_MON_8814B 0x003E +#define REG_GPIO_MUXCFG_8814B 0x0040 +#define REG_GPIO_PIN_CTRL_8814B 0x0044 +#define REG_GPIO_INTM_8814B 0x0048 +#define REG_LED_CFG_8814B 0x004C +#define REG_FSIMR_8814B 0x0050 +#define REG_FSISR_8814B 0x0054 +#define REG_HSIMR_8814B 0x0058 +#define REG_HSISR_8814B 0x005C +#define REG_GPIO_EXT_CTRL_8814B 0x0060 +#define REG_PAD_CTRL1_8814B 0x0064 +#define REG_WL_BT_PWR_CTRL_8814B 0x0068 +#define REG_SDM_DEBUG_8814B 0x006C +#define REG_SYS_SDIO_CTRL_8814B 0x0070 +#define REG_HCI_OPT_CTRL_8814B 0x0074 +#define REG_AFE_CTRL4_8814B 0x0078 +#define REG_LDO_SWR_CTRL_8814B 0x007C +#define REG_MCUFW_CTRL_8814B 0x0080 +#define REG_MCU_TST_CFG_8814B 0x0084 +#define REG_HMEBOX_E0_E1_8814B 0x0088 +#define REG_HMEBOX_E2_E3_8814B 0x008C +#define REG_WLLPS_CTRL_8814B 0x0090 +#define REG_AFE_CTRL5_8814B 0x0094 +#define REG_GPIO_DEBOUNCE_CTRL_8814B 0x0098 +#define REG_RPWM2_8814B 0x009C +#define REG_SYSON_FSM_MON_8814B 0x00A0 +#define REG_AFE_CTRL6_8814B 0x00A4 +#define REG_PMC_DBG_CTRL1_8814B 0x00A8 +#define REG_AFE_CTRL7_8814B 0x00AC +#define REG_HIMR0_8814B 0x00B0 +#define REG_HISR0_8814B 0x00B4 +#define REG_HIMR1_8814B 0x00B8 +#define REG_HISR1_8814B 0x00BC +#define REG_DBG_PORT_SEL_8814B 0x00C0 +#define REG_PAD_CTRL2_8814B 0x00C4 +#define REG_PMC_DBG_CTRL2_8814B 0x00CC +#define REG_BIST_CTRL_8814B 0x00D0 +#define REG_BIST_RPT_8814B 0x00D4 +#define REG_MEM_CTRL_8814B 0x00D8 +#define REG_AFE_CTRL8_8814B 0x00DC +#define REG_USB_SIE_INTF_8814B 0x00E0 +#define REG_PCIE_MIO_INTF_8814B 0x00E4 +#define REG_PCIE_MIO_INTD_8814B 0x00E8 +#define REG_WLRF1_8814B 0x00EC +#define REG_SYS_CFG1_8814B 0x00F0 +#define REG_SYS_STATUS1_8814B 0x00F4 +#define REG_SYS_STATUS2_8814B 0x00F8 +#define REG_SYS_CFG2_8814B 0x00FC +#define REG_SYS_CFG3_8814B 0x1000 +#define REG_SYS_CFG4_8814B 0x1034 +#define REG_SYS_CFG5_8814B 0x1070 +#define REG_CPU_DMEM_CON_8814B 0x1080 +#define REG_BOOT_REASON_8814B 0x1088 +#define REG_NFCPAD_CTRL_8814B 0x10A8 +#define REG_HIMR2_8814B 0x10B0 +#define REG_HISR2_8814B 0x10B4 +#define REG_HIMR3_8814B 0x10B8 +#define REG_HISR3_8814B 0x10BC +#define REG_SW_MDIO_8814B 0x10C0 +#define REG_SW_FLUSH_8814B 0x10C4 +#define REG_H2C_PKT_READADDR_8814B 0x10D0 +#define REG_H2C_PKT_WRITEADDR_8814B 0x10D4 +#define REG_MEM_PWR_CRTL_8814B 0x10D8 +#define REG_FW_DBG0_8814B 0x10E0 +#define REG_FW_DBG1_8814B 0x10E4 +#define REG_FW_DBG2_8814B 0x10E8 +#define REG_FW_DBG3_8814B 0x10EC +#define REG_FW_DBG4_8814B 0x10F0 +#define REG_FW_DBG5_8814B 0x10F4 +#define REG_FW_DBG6_8814B 0x10F8 +#define REG_FW_DBG7_8814B 0x10FC +#define REG_CR_8814B 0x0100 +#define REG_PKT_BUFF_ACCESS_CTRL_8814B 0x0106 +#define REG_TSF_CLK_STATE_8814B 0x0108 +#define REG_TXDMA_PQ_MAP_8814B 0x010C +#define REG_TRXFF_BNDY_8814B 0x0114 +#define REG_PTA_I2C_MBOX_8814B 0x0118 +#define REG_RXFF_BNDY_8814B 0x011C +#define REG_FE1IMR_8814B 0x0120 +#define REG_FE1ISR_8814B 0x0124 +#define REG_CPWM_8814B 0x012C +#define REG_FWIMR_8814B 0x0130 +#define REG_FWISR_8814B 0x0134 +#define REG_FTIMR_8814B 0x0138 +#define REG_FTISR_8814B 0x013C +#define REG_PKTBUF_DBG_CTRL_8814B 0x0140 +#define REG_PKTBUF_DBG_DATA_L_8814B 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8814B 0x0148 +#define REG_CPWM2_8814B 0x014C +#define REG_TC0_CTRL_8814B 0x0150 +#define REG_TC1_CTRL_8814B 0x0154 +#define REG_TC2_CTRL_8814B 0x0158 +#define REG_TC3_CTRL_8814B 0x015C +#define REG_TC4_CTRL_8814B 0x0160 +#define REG_TCUNIT_BASE_8814B 0x0164 +#define REG_TC5_CTRL_8814B 0x0168 +#define REG_TC6_CTRL_8814B 0x016C +#define REG_MBIST_FAIL_8814B 0x0170 +#define REG_MBIST_START_PAUSE_8814B 0x0174 +#define REG_MBIST_DONE_8814B 0x0178 +#define REG_MBIST_FAIL_NRML_8814B 0x017C +#define REG_AES_DECRPT_DATA_8814B 0x0180 +#define REG_AES_DECRPT_CFG_8814B 0x0184 +#define REG_TMETER_8814B 0x0190 +#define REG_OSC_32K_CTRL_8814B 0x0194 +#define REG_32K_CAL_REG1_8814B 0x0198 +#define REG_C2HEVT_8814B 0x01A0 +#define REG_C2HEVT_1_8814B 0x01A4 +#define REG_C2HEVT_2_8814B 0x01A8 +#define REG_C2HEVT_3_8814B 0x01AC +#define REG_SW_DEFINED_PAGE1_8814B 0x01B8 +#define REG_SW_DEFINED_PAGE2_8814B 0x01BC +#define REG_MCUTST_I_8814B 0x01C0 +#define REG_MCUTST_II_8814B 0x01C4 +#define REG_FMETHR_8814B 0x01C8 +#define REG_HMETFR_8814B 0x01CC +#define REG_HMEBOX0_8814B 0x01D0 +#define REG_HMEBOX1_8814B 0x01D4 +#define REG_HMEBOX2_8814B 0x01D8 +#define REG_HMEBOX3_8814B 0x01DC +#define REG_LLT_INIT_8814B 0x01E0 +#define REG_LLT_INIT_ADDR_8814B 0x01E4 +#define REG_BB_ACCESS_CTRL_8814B 0x01E8 +#define REG_BB_ACCESS_DATA_8814B 0x01EC +#define REG_HMEBOX_E0_8814B 0x01F0 +#define REG_HMEBOX_E1_8814B 0x01F4 +#define REG_HMEBOX_E2_8814B 0x01F8 +#define REG_HMEBOX_E3_8814B 0x01FC +#define REG_CR_EXT_8814B 0x1100 +#define REG_FWFF_8814B 0x1114 +#define REG_RXFF_PTR_V1_8814B 0x1118 +#define REG_RXFF_WTR_V1_8814B 0x111C +#define REG_FE2IMR_8814B 0x1120 +#define REG_FE2ISR_8814B 0x1124 +#define REG_FE3IMR_8814B 0x1128 +#define REG_FE3ISR_8814B 0x112C +#define REG_FE4IMR_8814B 0x1130 +#define REG_FE4ISR_8814B 0x1134 +#define REG_FT1IMR_8814B 0x1138 +#define REG_FT1ISR_8814B 0x113C +#define REG_SPWR0_8814B 0x1140 +#define REG_SPWR1_8814B 0x1144 +#define REG_SPWR2_8814B 0x1148 +#define REG_SPWR3_8814B 0x114C +#define REG_POWSEQ_8814B 0x1150 +#define REG_TC7_CTRL_V1_8814B 0x1158 +#define REG_TC8_CTRL_V1_8814B 0x115C +#define REG_FT2IMR_8814B 0x11E0 +#define REG_FT2ISR_8814B 0x11E4 +#define REG_MSG2_8814B 0x11F0 +#define REG_MSG3_8814B 0x11F4 +#define REG_MSG4_8814B 0x11F8 +#define REG_MSG5_8814B 0x11FC +#define REG_FIFOPAGE_CTRL_1_8814B 0x0200 +#define REG_FIFOPAGE_CTRL_2_8814B 0x0204 +#define REG_AUTO_LLT_V1_8814B 0x0208 +#define REG_TXDMA_OFFSET_CHK_8814B 0x020C +#define REG_TXDMA_STATUS_8814B 0x0210 +#define REG_TX_DMA_DBG_8814B 0x0214 +#define REG_TQPNT1_8814B 0x0218 +#define REG_TQPNT2_8814B 0x021C +#define REG_TQPNT3_8814B 0x0220 +#define REG_TQPNT4_8814B 0x0224 +#define REG_RQPN_CTRL_1_8814B 0x0228 +#define REG_RQPN_CTRL_2_8814B 0x022C +#define REG_FIFOPAGE_INFO_1_8814B 0x0230 +#define REG_FIFOPAGE_INFO_2_8814B 0x0234 +#define REG_FIFOPAGE_INFO_3_8814B 0x0238 +#define REG_FIFOPAGE_INFO_4_8814B 0x023C +#define REG_FIFOPAGE_INFO_5_8814B 0x0240 +#define REG_H2C_HEAD_8814B 0x0244 +#define REG_H2C_TAIL_8814B 0x0248 +#define REG_H2C_READ_ADDR_8814B 0x024C +#define REG_H2C_WR_ADDR_8814B 0x0250 +#define REG_H2C_INFO_8814B 0x0254 +#define REG_RXDMA_AGG_PG_TH_8814B 0x0280 +#define REG_RXPKT_NUM_8814B 0x0284 +#define REG_RXDMA_STATUS_8814B 0x0288 +#define REG_RXDMA_DPR_8814B 0x028C +#define REG_RXDMA_MODE_8814B 0x0290 +#define REG_C2H_PKT_8814B 0x0294 +#define REG_FWFF_C2H_8814B 0x0298 +#define REG_FWFF_CTRL_8814B 0x029C +#define REG_FWFF_PKT_INFO_8814B 0x02A0 +#define REG_DDMA_CH0SA_8814B 0x1200 +#define REG_DDMA_CH0DA_8814B 0x1204 +#define REG_DDMA_CH0CTRL_8814B 0x1208 +#define REG_DDMA_CH1SA_8814B 0x1210 +#define REG_DDMA_CH1DA_8814B 0x1214 +#define REG_DDMA_CH1CTRL_8814B 0x1218 +#define REG_DDMA_CH2SA_8814B 0x1220 +#define REG_DDMA_CH2DA_8814B 0x1224 +#define REG_DDMA_CH2CTRL_8814B 0x1228 +#define REG_DDMA_CH3SA_8814B 0x1230 +#define REG_DDMA_CH3DA_8814B 0x1234 +#define REG_DDMA_CH3CTRL_8814B 0x1238 +#define REG_DDMA_CH4SA_8814B 0x1240 +#define REG_DDMA_CH4DA_8814B 0x1244 +#define REG_DDMA_CH4CTRL_8814B 0x1248 +#define REG_DDMA_CH5SA_8814B 0x1250 +#define REG_DDMA_CH5DA_8814B 0x1254 +#define REG_DDMA_CH5CTRL_8814B 0x1258 +#define REG_DDMA_INT_MSK_8814B 0x12E0 +#define REG_DDMA_CHSTATUS_8814B 0x12E8 +#define REG_DDMA_CHKSUM_8814B 0x12F0 +#define REG_DDMA_MONITOR_8814B 0x12FC +#define REG_PCIE_CTRL_8814B 0x0300 +#define REG_INT_MIG_8814B 0x0304 +#define REG_BCNQ_TXBD_DESA_8814B 0x0308 +#define REG_MGQ_TXBD_DESA_8814B 0x0310 +#define REG_VOQ_TXBD_DESA_8814B 0x0318 +#define REG_VIQ_TXBD_DESA_8814B 0x0320 +#define REG_BEQ_TXBD_DESA_8814B 0x0328 +#define REG_BKQ_TXBD_DESA_8814B 0x0330 +#define REG_RXQ_RXBD_DESA_8814B 0x0338 +#define REG_HI0Q_TXBD_DESA_8814B 0x0340 +#define REG_HI1Q_TXBD_DESA_8814B 0x0348 +#define REG_HI2Q_TXBD_DESA_8814B 0x0350 +#define REG_HI3Q_TXBD_DESA_8814B 0x0358 +#define REG_HI4Q_TXBD_DESA_8814B 0x0360 +#define REG_HI5Q_TXBD_DESA_8814B 0x0368 +#define REG_HI6Q_TXBD_DESA_8814B 0x0370 +#define REG_HI7Q_TXBD_DESA_8814B 0x0378 +#define REG_MGQ_TXBD_NUM_8814B 0x0380 +#define REG_RX_RXBD_NUM_8814B 0x0382 +#define REG_VOQ_TXBD_NUM_8814B 0x0384 +#define REG_VIQ_TXBD_NUM_8814B 0x0386 +#define REG_BEQ_TXBD_NUM_8814B 0x0388 +#define REG_BKQ_TXBD_NUM_8814B 0x038A +#define REG_HI0Q_TXBD_NUM_8814B 0x038C +#define REG_HI1Q_TXBD_NUM_8814B 0x038E +#define REG_HI2Q_TXBD_NUM_8814B 0x0390 +#define REG_HI3Q_TXBD_NUM_8814B 0x0392 +#define REG_HI4Q_TXBD_NUM_8814B 0x0394 +#define REG_HI5Q_TXBD_NUM_8814B 0x0396 +#define REG_HI6Q_TXBD_NUM_8814B 0x0398 +#define REG_HI7Q_TXBD_NUM_8814B 0x039A +#define REG_TSFTIMER_HCI_8814B 0x039C +#define REG_BD_RWPTR_CLR_8814B 0x039C +#define REG_VOQ_TXBD_IDX_8814B 0x03A0 +#define REG_VIQ_TXBD_IDX_8814B 0x03A4 +#define REG_BEQ_TXBD_IDX_8814B 0x03A8 +#define REG_BKQ_TXBD_IDX_8814B 0x03AC +#define REG_MGQ_TXBD_IDX_8814B 0x03B0 +#define REG_RXQ_RXBD_IDX_8814B 0x03B4 +#define REG_HI0Q_TXBD_IDX_8814B 0x03B8 +#define REG_HI1Q_TXBD_IDX_8814B 0x03BC +#define REG_HI2Q_TXBD_IDX_8814B 0x03C0 +#define REG_HI3Q_TXBD_IDX_8814B 0x03C4 +#define REG_HI4Q_TXBD_IDX_8814B 0x03C8 +#define REG_HI5Q_TXBD_IDX_8814B 0x03CC +#define REG_HI6Q_TXBD_IDX_8814B 0x03D0 +#define REG_HI7Q_TXBD_IDX_8814B 0x03D4 +#define REG_DBG_SEL_V1_8814B 0x03D8 +#define REG_PCIE_HRPWM1_V1_8814B 0x03D9 +#define REG_PCIE_HCPWM1_V1_8814B 0x03DA +#define REG_PCIE_CTRL2_8814B 0x03DB +#define REG_PCIE_HRPWM2_V1_8814B 0x03DC +#define REG_PCIE_HCPWM2_V1_8814B 0x03DE +#define REG_PCIE_H2C_MSG_V1_8814B 0x03E0 +#define REG_PCIE_C2H_MSG_V1_8814B 0x03E4 +#define REG_DBI_WDATA_V1_8814B 0x03E8 +#define REG_DBI_RDATA_V1_8814B 0x03EC +#define REG_DBI_FLAG_V1_8814B 0x03F0 +#define REG_MDIO_V1_8814B 0x03F4 +#define REG_PCIE_MIX_CFG_8814B 0x03F8 +#define REG_HCI_MIX_CFG_8814B 0x03FC +#define REG_STC_INT_CS_8814B 0x1300 +#define REG_ST_INT_CFG_8814B 0x1304 +#define REG_CMU_DLY_CTRL_8814B 0x1310 +#define REG_CMU_DLY_CFG_8814B 0x1314 +#define REG_H2CQ_TXBD_DESA_8814B 0x1320 +#define REG_H2CQ_TXBD_NUM_8814B 0x1328 +#define REG_H2CQ_TXBD_IDX_8814B 0x132C +#define REG_H2CQ_CSR_8814B 0x1330 +#define REG_Q0_INFO_8814B 0x0400 +#define REG_Q1_INFO_8814B 0x0404 +#define REG_Q2_INFO_8814B 0x0408 +#define REG_Q3_INFO_8814B 0x040C +#define REG_MGQ_INFO_8814B 0x0410 +#define REG_HIQ_INFO_8814B 0x0414 +#define REG_BCNQ_INFO_8814B 0x0418 +#define REG_TXPKT_EMPTY_8814B 0x041A +#define REG_CPU_MGQ_INFO_8814B 0x041C +#define REG_FWHW_TXQ_CTRL_8814B 0x0420 +#define REG_DATAFB_SEL_8814B 0x0423 +#define REG_BCNQ_BDNY_V1_8814B 0x0424 +#define REG_LIFETIME_EN_8814B 0x0426 +#define REG_SPEC_SIFS_8814B 0x0428 +#define REG_RETRY_LIMIT_8814B 0x042A +#define REG_TXBF_CTRL_8814B 0x042C +#define REG_DARFRC_8814B 0x0430 +#define REG_RARFRC_8814B 0x0438 +#define REG_RRSR_8814B 0x0440 +#define REG_ARFR0_8814B 0x0444 +#define REG_ARFR1_V1_8814B 0x044C +#define REG_CCK_CHECK_8814B 0x0454 +#define REG_AMPDU_MAX_TIME_V1_8814B 0x0455 +#define REG_BCNQ1_BDNY_V1_8814B 0x0456 +#define REG_AMPDU_MAX_LENGTH_8814B 0x0458 +#define REG_ACQ_STOP_8814B 0x045C +#define REG_NDPA_RATE_8814B 0x045D +#define REG_TX_HANG_CTRL_8814B 0x045E +#define REG_NDPA_OPT_CTRL_8814B 0x045F +#define REG_RD_RESP_PKT_TH_8814B 0x0463 +#define REG_CMDQ_INFO_8814B 0x0464 +#define REG_Q4_INFO_8814B 0x0468 +#define REG_Q5_INFO_8814B 0x046C +#define REG_Q6_INFO_8814B 0x0470 +#define REG_Q7_INFO_8814B 0x0474 +#define REG_WMAC_LBK_BUF_HD_V1_8814B 0x0478 +#define REG_MGQ_BDNY_V1_8814B 0x047A +#define REG_TXRPT_CTRL_8814B 0x047C +#define REG_INIRTS_RATE_SEL_8814B 0x0480 +#define REG_BASIC_CFEND_RATE_8814B 0x0481 +#define REG_STBC_CFEND_RATE_8814B 0x0482 +#define REG_DATA_SC_8814B 0x0483 +#define REG_MACID_SLEEP3_8814B 0x0484 +#define REG_MACID_SLEEP1_8814B 0x0488 +#define REG_ARFR2_V1_8814B 0x048C +#define REG_ARFR3_V1_8814B 0x0494 +#define REG_ARFR4_8814B 0x049C +#define REG_ARFR5_8814B 0x04A4 +#define REG_TXRPT_START_OFFSET_8814B 0x04AC +#define REG_POWER_STAGE1_8814B 0x04B4 +#define REG_POWER_STAGE2_8814B 0x04B8 +#define REG_SW_AMPDU_BURST_MODE_CTRL_8814B 0x04BC +#define REG_PKT_LIFE_TIME_8814B 0x04C0 +#define REG_STBC_SETTING_8814B 0x04C4 +#define REG_STBC_SETTING2_8814B 0x04C5 +#define REG_QUEUE_CTRL_8814B 0x04C6 +#define REG_SINGLE_AMPDU_CTRL_8814B 0x04C7 +#define REG_PROT_MODE_CTRL_8814B 0x04C8 +#define REG_BAR_MODE_CTRL_8814B 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8814B 0x04CF +#define REG_MACID_SLEEP2_8814B 0x04D0 +#define REG_MACID_SLEEP_8814B 0x04D4 +#define REG_HW_SEQ0_8814B 0x04D8 +#define REG_HW_SEQ1_8814B 0x04DA +#define REG_HW_SEQ2_8814B 0x04DC +#define REG_HW_SEQ3_8814B 0x04DE +#define REG_NULL_PKT_STATUS_V1_8814B 0x04E0 +#define REG_PTCL_ERR_STATUS_8814B 0x04E2 +#define REG_NULL_PKT_STATUS_EXTEND_8814B 0x04E3 +#define REG_VIDEO_ENHANCEMENT_FUN_8814B 0x04E4 +#define REG_BT_POLLUTE_PKT_CNT_8814B 0x04E8 +#define REG_PTCL_DBG_8814B 0x04EC +#define REG_CPUMGQ_TIMER_CTRL2_8814B 0x04F4 +#define REG_DUMMY_PAGE4_V1_8814B 0x04FC +#define REG_MOREDATA_8814B 0x04FE +#define REG_Q0_Q1_INFO_8814B 0x1400 +#define REG_Q2_Q3_INFO_8814B 0x1404 +#define REG_Q4_Q5_INFO_8814B 0x1408 +#define REG_Q6_Q7_INFO_8814B 0x140C +#define REG_MGQ_HIQ_INFO_8814B 0x1410 +#define REG_CMDQ_BCNQ_INFO_8814B 0x1414 +#define REG_USEREG_SETTING_8814B 0x1420 +#define REG_AESIV_SETTING_8814B 0x1424 +#define REG_BF0_TIME_SETTING_8814B 0x1428 +#define REG_BF1_TIME_SETTING_8814B 0x142C +#define REG_BF_TIMEOUT_EN_8814B 0x1430 +#define REG_MACID_RELEASE0_8814B 0x1434 +#define REG_MACID_RELEASE1_8814B 0x1438 +#define REG_MACID_RELEASE2_8814B 0x143C +#define REG_MACID_RELEASE3_8814B 0x1440 +#define REG_MACID_RELEASE_SETTING_8814B 0x1444 +#define REG_FAST_EDCA_VOVI_SETTING_8814B 0x1448 +#define REG_FAST_EDCA_BEBK_SETTING_8814B 0x144C +#define REG_MACID_DROP0_8814B 0x1450 +#define REG_MACID_DROP1_8814B 0x1454 +#define REG_MACID_DROP2_8814B 0x1458 +#define REG_MACID_DROP3_8814B 0x145C +#define REG_R_MACID_RELEASE_SUCCESS_0_8814B 0x1460 +#define REG_R_MACID_RELEASE_SUCCESS_1_8814B 0x1464 +#define REG_R_MACID_RELEASE_SUCCESS_2_8814B 0x1468 +#define REG_R_MACID_RELEASE_SUCCESS_3_8814B 0x146C +#define REG_MGG_FIFO_CRTL_8814B 0x1470 +#define REG_MGG_FIFO_INT_8814B 0x1474 +#define REG_MGG_FIFO_LIFETIME_8814B 0x1478 +#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B 0x147C +#define REG_MU_TX_CTL_8814B 0x14C0 +#define REG_MU_STA_GID_VLD_8814B 0x14C4 +#define REG_MU_STA_USER_POS_INFO_8814B 0x14C8 +#define REG_MU_TRX_DBG_CNT_8814B 0x14D0 +#define REG_EDCA_VO_PARAM_8814B 0x0500 +#define REG_EDCA_VI_PARAM_8814B 0x0504 +#define REG_EDCA_BE_PARAM_8814B 0x0508 +#define REG_EDCA_BK_PARAM_8814B 0x050C +#define REG_BCNTCFG_8814B 0x0510 +#define REG_PIFS_8814B 0x0512 +#define REG_RDG_PIFS_8814B 0x0513 +#define REG_SIFS_8814B 0x0514 +#define REG_TSFTR_SYN_OFFSET_8814B 0x0518 +#define REG_AGGR_BREAK_TIME_8814B 0x051A +#define REG_SLOT_8814B 0x051B +#define REG_TX_PTCL_CTRL_8814B 0x0520 +#define REG_TXPAUSE_8814B 0x0522 +#define REG_DIS_TXREQ_CLR_8814B 0x0523 +#define REG_RD_CTRL_8814B 0x0524 +#define REG_MBSSID_CTRL_8814B 0x0526 +#define REG_P2PPS_CTRL_8814B 0x0527 +#define REG_PKT_LIFETIME_CTRL_8814B 0x0528 +#define REG_P2PPS_SPEC_STATE_8814B 0x052B +#define REG_BAR_TX_CTRL_8814B 0x0530 +#define REG_TBTT_PROHIBIT_8814B 0x0540 +#define REG_P2PPS_STATE_8814B 0x0543 +#define REG_RD_NAV_NXT_8814B 0x0544 +#define REG_NAV_PROT_LEN_8814B 0x0546 +#define REG_BCN_CTRL_8814B 0x0550 +#define REG_BCN_CTRL_CLINT0_8814B 0x0551 +#define REG_MBID_NUM_8814B 0x0552 +#define REG_DUAL_TSF_RST_8814B 0x0553 +#define REG_MBSSID_BCN_SPACE_8814B 0x0554 +#define REG_DRVERLYINT_8814B 0x0558 +#define REG_BCNDMATIM_8814B 0x0559 +#define REG_ATIMWND_8814B 0x055A +#define REG_USTIME_TSF_8814B 0x055C +#define REG_BCN_MAX_ERR_8814B 0x055D +#define REG_RXTSF_OFFSET_CCK_8814B 0x055E +#define REG_RXTSF_OFFSET_OFDM_8814B 0x055F +#define REG_TSFTR_8814B 0x0560 +#define REG_TSFTR_1_8814B 0x0564 +#define REG_FREERUN_CNT_8814B 0x0568 +#define REG_FREERUN_CNT_1_8814B 0x056C +#define REG_ATIMWND1_V1_8814B 0x0570 +#define REG_TBTT_PROHIBIT_INFRA_8814B 0x0571 +#define REG_CTWND_8814B 0x0572 +#define REG_BCNIVLCUNT_8814B 0x0573 +#define REG_BCNDROPCTRL_8814B 0x0574 +#define REG_HGQ_TIMEOUT_PERIOD_8814B 0x0575 +#define REG_TXCMD_TIMEOUT_PERIOD_8814B 0x0576 +#define REG_MISC_CTRL_8814B 0x0577 +#define REG_BCN_CTRL_CLINT1_8814B 0x0578 +#define REG_BCN_CTRL_CLINT2_8814B 0x0579 +#define REG_BCN_CTRL_CLINT3_8814B 0x057A +#define REG_EXTEND_CTRL_8814B 0x057B +#define REG_P2PPS1_SPEC_STATE_8814B 0x057C +#define REG_P2PPS1_STATE_8814B 0x057D +#define REG_P2PPS2_SPEC_STATE_8814B 0x057E +#define REG_P2PPS2_STATE_8814B 0x057F +#define REG_PS_TIMER0_8814B 0x0580 +#define REG_PS_TIMER1_8814B 0x0584 +#define REG_PS_TIMER2_8814B 0x0588 +#define REG_TBTT_CTN_AREA_8814B 0x058C +#define REG_FORCE_BCN_IFS_8814B 0x058E +#define REG_TXOP_MIN_8814B 0x0590 +#define REG_PRE_BKF_TIME_8814B 0x0592 +#define REG_CROSS_TXOP_CTRL_8814B 0x0593 +#define REG_ATIMWND2_8814B 0x05A0 +#define REG_ATIMWND3_8814B 0x05A1 +#define REG_ATIMWND4_8814B 0x05A2 +#define REG_ATIMWND5_8814B 0x05A3 +#define REG_ATIMWND6_8814B 0x05A4 +#define REG_ATIMWND7_8814B 0x05A5 +#define REG_ATIMUGT_8814B 0x05A6 +#define REG_HIQ_NO_LMT_EN_8814B 0x05A7 +#define REG_DTIM_COUNTER_ROOT_8814B 0x05A8 +#define REG_DTIM_COUNTER_VAP1_8814B 0x05A9 +#define REG_DTIM_COUNTER_VAP2_8814B 0x05AA +#define REG_DTIM_COUNTER_VAP3_8814B 0x05AB +#define REG_DTIM_COUNTER_VAP4_8814B 0x05AC +#define REG_DTIM_COUNTER_VAP5_8814B 0x05AD +#define REG_DTIM_COUNTER_VAP6_8814B 0x05AE +#define REG_DTIM_COUNTER_VAP7_8814B 0x05AF +#define REG_DIS_ATIM_8814B 0x05B0 +#define REG_EARLY_128US_8814B 0x05B1 +#define REG_P2PPS1_CTRL_8814B 0x05B2 +#define REG_P2PPS2_CTRL_8814B 0x05B3 +#define REG_TIMER0_SRC_SEL_8814B 0x05B4 +#define REG_NOA_UNIT_SEL_8814B 0x05B5 +#define REG_P2POFF_DIS_TXTIME_8814B 0x05B7 +#define REG_MBSSID_BCN_SPACE2_8814B 0x05B8 +#define REG_MBSSID_BCN_SPACE3_8814B 0x05BC +#define REG_ACMHWCTRL_8814B 0x05C0 +#define REG_ACMRSTCTRL_8814B 0x05C1 +#define REG_ACMAVG_8814B 0x05C2 +#define REG_VO_ADMTIME_8814B 0x05C4 +#define REG_VI_ADMTIME_8814B 0x05C6 +#define REG_BE_ADMTIME_8814B 0x05C8 +#define REG_EDCA_RANDOM_GEN_8814B 0x05CC +#define REG_TXCMD_NOA_SEL_8814B 0x05CF +#define REG_NOA_PARAM_8814B 0x05E0 +#define REG_NOA_PARAM_1_8814B 0x05E4 +#define REG_NOA_PARAM_2_8814B 0x05E8 +#define REG_NOA_PARAM_3_8814B 0x05EC +#define REG_P2P_RST_8814B 0x05F0 +#define REG_SCHEDULER_RST_8814B 0x05F1 +#define REG_SCH_TXCMD_8814B 0x05F8 +#define REG_PAGE5_DUMMY_8814B 0x05FC +#define REG_CPUMGQ_TX_TIMER_8814B 0x1500 +#define REG_PS_TIMER_A_8814B 0x1504 +#define REG_PS_TIMER_B_8814B 0x1508 +#define REG_PS_TIMER_C_8814B 0x150C +#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8814B 0x1510 +#define REG_CPUMGQ_TX_TIMER_EARLY_8814B 0x1514 +#define REG_PS_TIMER_A_EARLY_8814B 0x1515 +#define REG_PS_TIMER_B_EARLY_8814B 0x1516 +#define REG_PS_TIMER_C_EARLY_8814B 0x1517 +#define REG_WMAC_CR_8814B 0x0600 +#define REG_WMAC_FWPKT_CR_8814B 0x0601 +#define REG_FW_STS_FILTER_8814B 0x0602 +#define REG_BWOPMODE_8814B 0x0603 +#define REG_TCR_8814B 0x0604 +#define REG_RCR_8814B 0x0608 +#define REG_RX_PKT_LIMIT_8814B 0x060C +#define REG_RX_DLK_TIME_8814B 0x060D +#define REG_RX_DRVINFO_SZ_8814B 0x060F +#define REG_MACID_8814B 0x0610 +#define REG_BSSID_8814B 0x0618 +#define REG_MAR_8814B 0x0620 +#define REG_MBIDCAMCFG_1_8814B 0x0628 +#define REG_MBIDCAMCFG_2_8814B 0x062C +#define REG_WMAC_TCR_TSFT_OFS_8814B 0x0630 +#define REG_UDF_THSD_8814B 0x0632 +#define REG_ZLD_NUM_8814B 0x0633 +#define REG_STMP_THSD_8814B 0x0634 +#define REG_WMAC_TXTIMEOUT_8814B 0x0635 +#define REG_MCU_TEST_2_V1_8814B 0x0636 +#define REG_USTIME_EDCA_8814B 0x0638 +#define REG_ACKTO_CCK_8814B 0x0639 +#define REG_MAC_SPEC_SIFS_8814B 0x063A +#define REG_RESP_SIFS_CCK_8814B 0x063C +#define REG_RESP_SIFS_OFDM_8814B 0x063E +#define REG_ACKTO_8814B 0x0640 +#define REG_CTS2TO_8814B 0x0641 +#define REG_EIFS_8814B 0x0642 +#define REG_RPFM_MAP0_8814B 0x0644 +#define REG_RPFM_MAP1_8814B 0x0646 +#define REG_RPFM_CAM_CMD_8814B 0x0648 +#define REG_RPFM_CAM_RWD_8814B 0x064C +#define REG_NAV_CTRL_8814B 0x0650 +#define REG_BACAMCMD_8814B 0x0654 +#define REG_BACAMCONTENT_8814B 0x0658 +#define REG_LBDLY_8814B 0x0660 +#define REG_WMAC_BACAM_RPMEN_8814B 0x0661 +#define REG_TX_RX_8814B 0x0662 +#define REG_WMAC_BITMAP_CTL_8814B 0x0663 +#define REG_RXERR_RPT_8814B 0x0664 +#define REG_WMAC_TRXPTCL_CTL_8814B 0x0668 +#define REG_CAMCMD_8814B 0x0670 +#define REG_CAMWRITE_8814B 0x0674 +#define REG_CAMREAD_8814B 0x0678 +#define REG_CAMDBG_8814B 0x067C +#define REG_SECCFG_8814B 0x0680 +#define REG_RXFILTER_CATEGORY_1_8814B 0x0682 +#define REG_RXFILTER_ACTION_1_8814B 0x0683 +#define REG_RXFILTER_CATEGORY_2_8814B 0x0684 +#define REG_RXFILTER_ACTION_2_8814B 0x0685 +#define REG_RXFILTER_CATEGORY_3_8814B 0x0686 +#define REG_RXFILTER_ACTION_3_8814B 0x0687 +#define REG_RXFLTMAP3_8814B 0x0688 +#define REG_RXFLTMAP4_8814B 0x068A +#define REG_RXFLTMAP5_8814B 0x068C +#define REG_RXFLTMAP6_8814B 0x068E +#define REG_WOW_CTRL_8814B 0x0690 +#define REG_NAN_RX_TSF_FILTER_8814B 0x0691 +#define REG_PS_RX_INFO_8814B 0x0692 +#define REG_WMMPS_UAPSD_TID_8814B 0x0693 +#define REG_LPNAV_CTRL_8814B 0x0694 +#define REG_WKFMCAM_CMD_8814B 0x0698 +#define REG_WKFMCAM_RWD_8814B 0x069C +#define REG_RXFLTMAP0_8814B 0x06A0 +#define REG_RXFLTMAP1_8814B 0x06A2 +#define REG_RXFLTMAP_8814B 0x06A4 +#define REG_BCN_PSR_RPT_8814B 0x06A8 +#define REG_FLC_RPC_8814B 0x06AC +#define REG_FLC_RPCT_8814B 0x06AD +#define REG_FLC_PTS_8814B 0x06AE +#define REG_FLC_TRPC_8814B 0x06AF +#define REG_RXPKTMON_CTRL_8814B 0x06B0 +#define REG_STATE_MON_8814B 0x06B4 +#define REG_ERROR_MON_8814B 0x06B8 +#define REG_SEARCH_MACID_8814B 0x06BC +#define REG_BT_COEX_TABLE_8814B 0x06C0 +#define REG_RXCMD_0_8814B 0x06D0 +#define REG_RXCMD_1_8814B 0x06D4 +#define REG_WMAC_RESP_TXINFO_8814B 0x06D8 +#define REG_BBPSF_CTRL_8814B 0x06DC +#define REG_P2P_RX_BCN_NOA_8814B 0x06E0 +#define REG_ASSOCIATED_BFMER0_INFO_8814B 0x06E4 +#define REG_ASSOCIATED_BFMER1_INFO_8814B 0x06EC +#define REG_TX_CSI_RPT_PARAM_BW20_8814B 0x06F4 +#define REG_TX_CSI_RPT_PARAM_BW40_8814B 0x06F8 +#define REG_TX_CSI_RPT_PARAM_BW80_8814B 0x06FC +#define REG_BCN_PSR_RPT2_8814B 0x1600 +#define REG_BCN_PSR_RPT3_8814B 0x1604 +#define REG_BCN_PSR_RPT4_8814B 0x1608 +#define REG_A1_ADDR_MASK_8814B 0x160C +#define REG_MACID2_8814B 0x1620 +#define REG_BSSID2_8814B 0x1628 +#define REG_MACID3_8814B 0x1630 +#define REG_BSSID3_8814B 0x1638 +#define REG_MACID4_8814B 0x1640 +#define REG_BSSID4_8814B 0x1648 +#define REG_NOA_REPORT_8814B 0x1650 +#define REG_PWRBIT_SETTING_8814B 0x1660 +#define REG_WMAC_MU_BF_OPTION_8814B 0x167C +#define REG_WMAC_PAUSE_BB_CLR_TH_8814B 0x167D +#define REG_WMAC_MU_ARB_8814B 0x167E +#define REG_WMAC_MU_OPTION_8814B 0x167F +#define REG_WMAC_MU_BF_CTL_8814B 0x1680 +#define REG_WMAC_MU_BIT_BFRPT_PARA_8814B 0x1682 +#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B 0x1684 +#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B 0x1686 +#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B 0x1688 +#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8814B 0x168A +#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8814B 0x168C +#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B 0x168E +#define REG_WMAC_BB_STOP_RX_COUNTER_8814B 0x1690 +#define REG_WMAC_PLCP_MONITOR_8814B 0x1694 +#define REG_WMAC_PLCP_MONITOR_MUTX_8814B 0x1698 +#define REG_TRANSMIT_ADDRSS_0_8814B 0x16A0 +#define REG_TRANSMIT_ADDRSS_1_8814B 0x16A8 +#define REG_TRANSMIT_ADDRSS_2_8814B 0x16B0 +#define REG_TRANSMIT_ADDRSS_3_8814B 0x16B8 +#define REG_TRANSMIT_ADDRSS_4_8814B 0x16C0 +#define REG_MACID1_8814B 0x0700 +#define REG_MACID1_1_8814B 0x0704 +#define REG_BSSID1_8814B 0x0708 +#define REG_BSSID1_1_8814B 0x070C +#define REG_BCN_PSR_RPT1_8814B 0x0710 +#define REG_ASSOCIATED_BFMEE_SEL_8814B 0x0714 +#define REG_SND_PTCL_CTRL_8814B 0x0718 +#define REG_RX_CSI_RPT_INFO_8814B 0x071C +#define REG_NS_ARP_CTRL_8814B 0x0720 +#define REG_NS_ARP_INFO_8814B 0x0724 +#define REG_BEAMFORMING_INFO_NSARP_V1_8814B 0x0728 +#define REG_BEAMFORMING_INFO_NSARP_8814B 0x072C +#define REG_IPV6_8814B 0x0730 +#define REG_IPV6_1_8814B 0x0734 +#define REG_IPV6_2_8814B 0x0738 +#define REG_IPV6_3_8814B 0x073C +#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8814B 0x0750 +#define REG_WMAC_SWAES_CFG_8814B 0x0760 +#define REG_BT_COEX_V2_8814B 0x0762 +#define REG_BT_COEX_8814B 0x0764 +#define REG_WLAN_ACT_MASK_CTRL_8814B 0x0768 +#define REG_WLAN_ACT_MASK_CTRL_1_8814B 0x076C +#define REG_BT_COEX_ENHANCED_INTR_CTRL_8814B 0x076E +#define REG_BT_ACT_STATISTICS_8814B 0x0770 +#define REG_BT_ACT_STATISTICS_1_8814B 0x0774 +#define REG_BT_STATISTICS_CONTROL_REGISTER_8814B 0x0778 +#define REG_BT_STATUS_REPORT_REGISTER_8814B 0x077C +#define REG_BT_INTERRUPT_CONTROL_REGISTER_8814B 0x0780 +#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8814B 0x0784 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8814B 0x0785 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8814B 0x0788 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8814B 0x078C +#define REG_BT_INTERRUPT_STATUS_REGISTER_8814B 0x078F +#define REG_BT_TDMA_TIME_REGISTER_8814B 0x0790 +#define REG_BT_ACT_REGISTER_8814B 0x0794 +#define REG_OBFF_CTRL_BASIC_8814B 0x0798 +#define REG_OBFF_CTRL2_TIMER_8814B 0x079C +#define REG_LTR_CTRL_BASIC_8814B 0x07A0 +#define REG_LTR_CTRL2_TIMER_THRESHOLD_8814B 0x07A4 +#define REG_LTR_IDLE_LATENCY_V1_8814B 0x07A8 +#define REG_LTR_ACTIVE_LATENCY_V1_8814B 0x07AC +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8814B 0x07B0 +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8814B 0x07B4 +#define REG_WMAC_PKTCNT_RWD_8814B 0x07B8 +#define REG_WMAC_PKTCNT_CTRL_8814B 0x07BC +#define REG_IQ_DUMP_8814B 0x07C0 +#define REG_IQ_DUMP_1_8814B 0x07C4 +#define REG_IQ_DUMP_2_8814B 0x07C8 +#define REG_WMAC_FTM_CTL_8814B 0x07CC +#define REG_WMAC_IQ_MDPK_FUNC_8814B 0x07CE +#define REG_WMAC_OPTION_FUNCTION_8814B 0x07D0 +#define REG_WMAC_OPTION_FUNCTION_1_8814B 0x07D4 +#define REG_WMAC_OPTION_FUNCTION_2_8814B 0x07D8 +#define REG_RX_FILTER_FUNCTION_8814B 0x07DA +#define REG_NDP_SIG_8814B 0x07E0 +#define REG_TXCMD_INFO_FOR_RSP_PKT_8814B 0x07E4 +#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8814B 0x07E8 +#define REG_WSEC_OPTION_8814B 0x07EC +#define REG_RTS_ADDRESS_0_8814B 0x07F0 +#define REG_RTS_ADDRESS_0_1_8814B 0x07F4 +#define REG_RTS_ADDRESS_1_8814B 0x07F8 +#define REG_RTS_ADDRESS_1_1_8814B 0x07FC +#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8814B 0x1700 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B 0x1704 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B 0x1708 +#define REG_SDIO_TX_CTRL_8814B 0x10250000 +#define REG_SDIO_HIMR_8814B 0x10250014 +#define REG_SDIO_HISR_8814B 0x10250018 +#define REG_SDIO_RX_REQ_LEN_8814B 0x1025001C +#define REG_SDIO_FREE_TXPG_SEQ_V1_8814B 0x1025001F +#define REG_SDIO_FREE_TXPG_8814B 0x10250020 +#define REG_SDIO_FREE_TXPG2_8814B 0x10250024 +#define REG_SDIO_OQT_FREE_TXPG_V1_8814B 0x10250028 +#define REG_SDIO_HTSFR_INFO_8814B 0x10250030 +#define REG_SDIO_HCPWM1_V2_8814B 0x10250038 +#define REG_SDIO_HCPWM2_V2_8814B 0x1025003A +#define REG_SDIO_INDIRECT_REG_CFG_8814B 0x10250040 +#define REG_SDIO_INDIRECT_REG_DATA_8814B 0x10250044 +#define REG_SDIO_H2C_8814B 0x10250060 +#define REG_SDIO_C2H_8814B 0x10250064 +#define REG_SDIO_HRPWM1_8814B 0x10250080 +#define REG_SDIO_HRPWM2_8814B 0x10250082 +#define REG_SDIO_HPS_CLKR_8814B 0x10250084 +#define REG_SDIO_BUS_CTRL_8814B 0x10250085 +#define REG_SDIO_HSUS_CTRL_8814B 0x10250086 +#define REG_SDIO_RESPONSE_TIMER_8814B 0x10250088 +#define REG_SDIO_CMD_CRC_8814B 0x1025008A +#define REG_SDIO_HSISR_8814B 0x10250090 +#define REG_SDIO_HSIMR_8814B 0x10250091 +#define REG_SDIO_ERR_RPT_8814B 0x102500C0 +#define REG_SDIO_CMD_ERRCNT_8814B 0x102500C1 +#define REG_SDIO_DATA_ERRCNT_8814B 0x102500C2 +#define REG_SDIO_CMD_ERR_CONTENT_8814B 0x102500C4 +#define REG_SDIO_CRC_ERR_IDX_8814B 0x102500C9 +#define REG_SDIO_DATA_CRC_8814B 0x102500CA +#define REG_SDIO_DATA_REPLY_TIME_8814B 0x102500CB + +#endif diff --git a/hal/phydm/ap_makefile.mk b/hal/phydm/ap_makefile.mk new file mode 100644 index 0000000..5731398 --- /dev/null +++ b/hal/phydm/ap_makefile.mk @@ -0,0 +1,109 @@ + +_PHYDM_FILES :=\ + phydm/phydm.o \ + phydm/phydm_dig.o\ + phydm/phydm_antdiv.o\ + phydm/phydm_dynamicbbpowersaving.o\ + phydm/phydm_pathdiv.o\ + phydm/phydm_rainfo.o\ + phydm/phydm_dynamictxpower.o\ + phydm/phydm_adaptivity.o\ + phydm/phydm_debug.o\ + phydm/phydm_interface.o\ + phydm/phydm_hwconfig.o\ + phydm/phydm_dfs.o\ + phydm/phydm_cfotracking.o\ + phydm/phydm_acs.o\ + phydm/phydm_adc_sampling.o\ + phydm/phydm_ccx.o\ + phydm/txbf/phydm_hal_txbf_api.o\ + EdcaTurboCheck.o\ + phydm/halrf/halrf.o\ + phydm/halrf/halphyrf_ap.o\ + phydm/halrf/halrf_powertracking_ap.o\ + phydm/halrf/halrf_kfree.o + +ifeq ($(CONFIG_RTL_88E_SUPPORT),y) + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8188e/halhwimg8188e_bb.o\ + phydm/rtl8188e/halhwimg8188e_mac.o\ + phydm/rtl8188e/halhwimg8188e_rf.o\ + phydm/rtl8188e/phydm_regconfig8188e.o\ + phydm/rtl8188e/hal8188erateadaptive.o\ + phydm/rtl8188e/phydm_rtl8188e.o\ + phydm/halrf/rtl8188e/halrf_8188e_ap.o + endif +endif + +ifeq ($(CONFIG_RTL_8812_SUPPORT),y) + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8881A),y) + _PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o +endif + +ifeq ($(CONFIG_WLAN_HAL_8192EE),y) + _PHYDM_FILES += \ + phydm/halrf/rtl8192e/halrf_8192e_ap.o\ + phydm/rtl8192e/phydm_rtl8192e.o +endif + +ifeq ($(CONFIG_WLAN_HAL_8814AE),y) + rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o + rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + rtl8192cd-objs += \ + phydm/rtl8814a/halhwimg8814a_bb.o\ + phydm/rtl8814a/halhwimg8814a_mac.o\ + phydm/rtl8814a/halhwimg8814a_rf.o\ + phydm/rtl8814a/phydm_regconfig8814a.o\ + phydm/rtl8814a/phydm_rtl8814a.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8822BE),y) + _PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o + _PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8822b/halhwimg8822b_bb.o\ + phydm/rtl8822b/halhwimg8822b_mac.o\ + phydm/rtl8822b/halhwimg8822b_rf.o\ + phydm/rtl8822b/halhwimg8822b_fw.o\ + phydm/rtl8822b/phydm_regconfig8822b.o\ + phydm/rtl8822b/phydm_hal_api8822b.o\ + phydm/rtl8822b/phydm_rtl8822b.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8821CE),y) + _PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o + _PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8821c/halhwimg8821c_bb.o\ + phydm/rtl8821c/halhwimg8821c_mac.o\ + phydm/rtl8821c/halhwimg8821c_rf.o\ + phydm/rtl8821c/phydm_regconfig8821c.o\ + phydm/rtl8821c/phydm_hal_api8821c.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8197F),y) + _PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o + _PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o + _PHYDM_FILES += efuse_97f/efuse.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8197f/halhwimg8197f_bb.o\ + phydm/rtl8197f/halhwimg8197f_mac.o\ + phydm/rtl8197f/halhwimg8197f_rf.o\ + phydm/rtl8197f/phydm_hal_api8197f.o\ + phydm/rtl8197f/phydm_regconfig8197f.o\ + phydm/rtl8197f/phydm_rtl8197f.o + endif +endif diff --git a/hal/phydm/halrf/halphyrf_ap.c b/hal/phydm/halrf/halphyrf_ap.c new file mode 100644 index 0000000..22d6e53 --- /dev/null +++ b/hal/phydm/halrf/halphyrf_ap.c @@ -0,0 +1,1369 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifndef index_mapping_NUM_88E + #define index_mapping_NUM_88E 15 +#endif + +/* #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) */ + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \ + do {\ + for (_offset = 0; _offset < _size; _offset++) { \ + \ + if (_delta_thermal < thermal_threshold[_direction][_offset]) { \ + \ + if (_offset != 0)\ + _offset--;\ + break;\ + } \ + } \ + if (_offset >= _size)\ + _offset = _size-1;\ + } while (0) + + +void configure_txpower_track( + void *p_dm_void, + struct _TXPWRTRACK_CFG *p_config +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if RTL8812A_SUPPORT +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /* if (IS_HARDWARE_TYPE_8812(p_dm_odm->adapter)) */ + if (p_dm_odm->support_ic_type == ODM_RTL8812) + configure_txpower_track_8812a(p_config); + /* else */ +#endif +#endif + +#if RTL8814A_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8814A) + configure_txpower_track_8814a(p_config); +#endif + + +#if RTL8188E_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8188E) + configure_txpower_track_8188e(p_config); +#endif + +#if RTL8197F_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8197F) + configure_txpower_track_8197f(p_config); +#endif + +#if RTL8822B_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8822B) + configure_txpower_track_8822b(p_config); +#endif + + +} + +#if (RTL8192E_SUPPORT == 1) +void +odm_txpowertracking_callback_thermal_meter_92e( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 thermal_value = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode; + u8 thermal_value_avg_count = 0; + u8 OFDM_min_index = 10; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur */ + s8 OFDM_index[2], index ; + u32 thermal_value_avg = 0, reg0x18; + u32 i = 0, j = 0, rf; + s32 value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + + rf_mimo_mode = p_dm_odm->rf_type; + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode)); */ + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || *(p_dm_odm->p_mp_mode)) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == false) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + thermal_value = (unsigned char)odm_get_rf_reg(p_dm_odm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther)); + + + switch (rf_mimo_mode) { + case MIMO_1T1R: + rf = 1; + break; + case MIMO_2T2R: + rf = 2; + break; + default: + rf = 2; + break; + } + + /* Query OFDM path A default setting Bit[31:21] */ + ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D); + for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { + if (ele_D == (ofdm_swing_table_92e[i] >> 22)) { + OFDM_index[0] = (unsigned char)i; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0])); + break; + } + } + + /* Query OFDM path B default setting */ + if (rf_mimo_mode == MIMO_2T2R) { + ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKOFDM_D); + for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { + if (ele_D == (ofdm_swing_table_92e[i] >> 22)) { + OFDM_index[1] = (unsigned char)i; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1])); + break; + } + } + } + + /* calculate average thermal meter */ + { + priv->pshare->thermal_value_avg_88xx[priv->pshare->thermal_value_avg_index_88xx] = thermal_value; + priv->pshare->thermal_value_avg_index_88xx++; + if (priv->pshare->thermal_value_avg_index_88xx == AVG_THERMAL_NUM_88XX) + priv->pshare->thermal_value_avg_index_88xx = 0; + + for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) { + if (priv->pshare->thermal_value_avg_88xx[i]) { + thermal_value_avg += priv->pshare->thermal_value_avg_88xx[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { + thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("AVG Thermal Meter = 0x%x\n", thermal_value)); + } + } + + /* Initialize */ + if (!priv->pshare->thermal_value) { + priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther; + priv->pshare->thermal_value_iqk = thermal_value; + priv->pshare->thermal_value_lck = thermal_value; + } + + if (thermal_value != priv->pshare->thermal_value) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** START POWER TRACKING ********\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther)); + + delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther); + delta_IQK = RTL_ABS(thermal_value, priv->pshare->thermal_value_iqk); + delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck); + is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0); + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); + + if (is_decrease) { + for (i = 0; i < rf; i++) { + OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); + OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); + CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); + CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1))); + } + } else { + for (i = 0; i < rf; i++) { + OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); + OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); + CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); + CCK_index = ((CCK_index < 0) ? 0 : CCK_index); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1))); + } + } + } +#endif /* CFG_TRACKING_TABLE_FILE */ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]])); + + /* Adujst OFDM Ant_A according to IQK result */ + ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22; + X = priv->pshare->rege94; + Y = priv->pshare->rege9c; + + if (X != 0) { + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D) >> 8) & 0x000003FF; + + /* new element C = element D x Y */ + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D) >> 8) & 0x000003FF; + + /* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */ + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, value32); + + value32 = ((X * ele_D) >> 7) & 0x01; + phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), value32); + } else { + phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]); + phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, 0x00); + phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), 0x00); + } + + set_CCK_swing_index(priv, CCK_index); + + if (rf == 2) { + ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22; + X = priv->pshare->regeb4; + Y = priv->pshare->regebc; + + if (X != 0) { + if ((X & 0x00000200) != 0) /* consider minus */ + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D) >> 8) & 0x000003FF; + + /* new element C = element D x Y */ + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D) >> 8) & 0x00003FF; + + /* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */ + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, value32); + + value32 = ((X * ele_D) >> 7) & 0x01; + phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), value32); + } else { + phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]); + phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, 0x00); + phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), 0x00); + } + + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD))); + + if (delta_IQK > 3) { + priv->pshare->thermal_value_iqk = thermal_value; +#ifdef MP_TEST +#endif if (!(*(p_dm_odm->p_mp_mode) && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET)))) + + phy_iq_calibrate_8192e(p_dm_odm, false); + } + + if (delta_LCK > 8) { + RTL_W8(0x522, 0xff); + reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1); + phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1); + phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1); + delay_ms(1); + phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0); + phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18); + RTL_W8(0x522, 0x0); + priv->pshare->thermal_value_lck = thermal_value; + } + } + + /* update thermal meter value */ + priv->pshare->thermal_value = thermal_value; + for (i = 0 ; i < rf ; i++) + priv->pshare->OFDM_index[i] = OFDM_index[i]; + priv->pshare->CCK_index = CCK_index; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__)); +} +#endif + + + +#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) +void +odm_txpowertracking_callback_thermal_meter_jaguar_series3( + void *p_dm_void +) +{ +#if 1 + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase; + u8 thermal_value_avg_count = 0, p = 0, i = 0; + u32 thermal_value_avg = 0; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct _TXPWRTRACK_CFG c; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + /*4 1. The following TWO tables decide the final index of OFDM/CCK swing table.*/ + u8 *delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL; + u8 *delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL; + u8 *delta_swing_table_idx_tup_cck_a = NULL, *delta_swing_table_idx_tdown_cck_a = NULL; + u8 *delta_swing_table_idx_tup_cck_b = NULL, *delta_swing_table_idx_tdown_cck_b = NULL; + /*for 8814 add by Yu Chen*/ + u8 *delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL; + u8 *delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL; + u8 *delta_swing_table_idx_tup_cck_c = NULL, *delta_swing_table_idx_tdown_cck_c = NULL; + u8 *delta_swing_table_idx_tup_cck_d = NULL, *delta_swing_table_idx_tdown_cck_d = NULL; + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || *(p_dm_odm->p_mp_mode)) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == false) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + configure_txpower_track(p_dm_odm, &c); + + (*c.get_delta_all_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, + (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b, + (u8 **)&delta_swing_table_idx_tup_cck_a, (u8 **)&delta_swing_table_idx_tdown_cck_a, + (u8 **)&delta_swing_table_idx_tup_cck_b, (u8 **)&delta_swing_table_idx_tdown_cck_b); + + thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /*0x42: RF Reg[15:10] 88E*/ +#ifdef THER_TRIM + if (GET_CHIP_VER(priv) == VERSION_8197F) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("orig thermal_value=%d, ther_trim_val=%d\n", thermal_value, priv->pshare->rf_ft_var.ther_trim_val)); + + thermal_value += priv->pshare->rf_ft_var.ther_trim_val; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("after thermal trim, thermal_value=%d\n", thermal_value)); + } +#endif + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Readback Thermal Meter = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n" + , thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther)); + + /* Initialize */ + if (!p_dm_odm->rf_calibrate_info.thermal_value) + p_dm_odm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther; + + if (!p_dm_odm->rf_calibrate_info.thermal_value_lck) + p_dm_odm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther; + + if (!p_dm_odm->rf_calibrate_info.thermal_value_iqk) + p_dm_odm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther; + + /* calculate average thermal meter */ + p_dm_odm->rf_calibrate_info.thermal_value_avg[p_dm_odm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; + p_dm_odm->rf_calibrate_info.thermal_value_avg_index++; + + if (p_dm_odm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ + p_dm_odm->rf_calibrate_info.thermal_value_avg_index = 0; + + for (i = 0; i < c.average_thermal_num; i++) { + if (p_dm_odm->rf_calibrate_info.thermal_value_avg[i]) { + thermal_value_avg += p_dm_odm->rf_calibrate_info.thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) {/*Calculate Average thermal_value after average enough times*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("thermal_value_avg=0x%x(%d) thermal_value_avg_count = %d\n" + , thermal_value_avg, thermal_value_avg, thermal_value_avg_count)); + + thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther)); + } + + /*4 Calculate delta, delta_LCK, delta_IQK.*/ + delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther); + delta_LCK = RTL_ABS(thermal_value, p_dm_odm->rf_calibrate_info.thermal_value_lck); + delta_IQK = RTL_ABS(thermal_value, p_dm_odm->rf_calibrate_info.thermal_value_iqk); + is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1); + + if (delta > 29) { /* power track table index(thermal diff.) upper bound*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta(%d) > 29, set delta to 29\n", delta)); + delta = 29; + } + + + /*4 if necessary, do LCK.*/ + + if (delta_LCK > c.threshold_iqk) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk)); + p_dm_odm->rf_calibrate_info.thermal_value_lck = thermal_value; + if (c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(p_dm_odm); + } + + if (delta_IQK > c.threshold_iqk) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk)); + p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value; + if (c.do_iqk) + (*c.do_iqk)(p_dm_odm, true, 0, 0); + } + + if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ + return; + + /*4 Do Power Tracking*/ + + if (thermal_value != p_dm_odm->rf_calibrate_info.thermal_value) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n******** START POWER TRACKING ********\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", + thermal_value, p_dm_odm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther)); + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + if (is_increase) { /*thermal is higher than base*/ + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_b[%d] = %d delta_swing_table_idx_tup_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta], delta, delta_swing_table_idx_tup_cck_b[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; + p_rf_calibrate_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_b[delta]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_c[%d] = %d delta_swing_table_idx_tup_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta], delta, delta_swing_table_idx_tup_cck_c[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; + p_rf_calibrate_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_c[delta]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_d[%d] = %d delta_swing_table_idx_tup_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta], delta, delta_swing_table_idx_tup_cck_d[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; + p_rf_calibrate_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_d[delta]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + break; + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_a[%d] = %d delta_swing_table_idx_tup_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta], delta, delta_swing_table_idx_tup_cck_a[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; + p_rf_calibrate_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_a[delta]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + break; + } + } + } else { /* thermal is lower than base*/ + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_b[%d] = %d delta_swing_table_idx_tdown_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta], delta, delta_swing_table_idx_tdown_cck_b[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; + p_rf_calibrate_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_b[delta]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_c[%d] = %d delta_swing_table_idx_tdown_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta], delta, delta_swing_table_idx_tdown_cck_c[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; + p_rf_calibrate_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_c[delta]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_d[%d] = %d delta_swing_table_idx_tdown_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta], delta, delta_swing_table_idx_tdown_cck_d[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; + p_rf_calibrate_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_d[delta]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + break; + + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_a[%d] = %d delta_swing_table_idx_tdown_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta], delta, delta_swing_table_idx_tdown_cck_a[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; + p_rf_calibrate_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_a[delta]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + break; + } + } + } + + if (is_increase) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power --->\n")); + if (GET_CHIP_VER(priv) == VERSION_8197F) { + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, 0); + } else if (GET_CHIP_VER(priv) == VERSION_8822B) { + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + } + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power --->\n")); + if (GET_CHIP_VER(priv) == VERSION_8197F) { + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, 0); + } else if (GET_CHIP_VER(priv) == VERSION_8822B) { + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + } + } + } +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n\n", __func__)); + /*update thermal meter value*/ + p_dm_odm->rf_calibrate_info.thermal_value = thermal_value; + + } + +#endif +} +#endif + +/*#if (RTL8814A_SUPPORT == 1)*/ +#if (RTL8814A_SUPPORT == 1) + +void +odm_txpowertracking_callback_thermal_meter_jaguar_series2( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase; + u8 thermal_value_avg_count = 0, p = 0, i = 0; + u32 thermal_value_avg = 0, reg0x18; + u32 bb_swing_reg[4] = {REG_A_TX_SCALE_JAGUAR, REG_B_TX_SCALE_JAGUAR, REG_C_TX_SCALE_JAGUAR2, REG_D_TX_SCALE_JAGUAR2}; + s32 ele_D; + u32 bb_swing_idx; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct _TXPWRTRACK_CFG c; + boolean is_tssi_enable = false; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ + u8 *delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL; + u8 *delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL; + /* for 8814 add by Yu Chen */ + u8 *delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL; + u8 *delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL; + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || *(p_dm_odm->p_mp_mode)) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == false) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + configure_txpower_track(p_dm_odm, &c); + p_rf_calibrate_info->default_ofdm_index = priv->pshare->OFDM_index0[ODM_RF_PATH_A]; + + (*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, + (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b); + + if (p_dm_odm->support_ic_type & ODM_RTL8814A) /* for 8814 path C & D */ + (*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c, + (u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d); + + thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, p_dm_odm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther)); + + /* Initialize */ + if (!p_dm_odm->rf_calibrate_info.thermal_value) + p_dm_odm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther; + + if (!p_dm_odm->rf_calibrate_info.thermal_value_lck) + p_dm_odm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther; + + if (!p_dm_odm->rf_calibrate_info.thermal_value_iqk) + p_dm_odm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther; + + is_tssi_enable = (boolean)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, REG_RF_TX_GAIN_OFFSET, BIT(7)); /* check TSSI enable */ + + /* 4 Query OFDM BB swing default setting Bit[31:21] */ + for (p = ODM_RF_PATH_A ; p < c.rf_path_count ; p++) { + ele_D = odm_get_bb_reg(p_dm_odm, bb_swing_reg[p], 0xffe00000); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(p_dm_odm, bb_swing_reg[p], MASKDWORD), ele_D)); + + for (bb_swing_idx = 0; bb_swing_idx < TXSCALE_TABLE_SIZE; bb_swing_idx++) {/* 4 */ + if (ele_D == tx_scaling_table_jaguar[bb_swing_idx]) { + p_dm_odm->rf_calibrate_info.OFDM_index[p] = (u8)bb_swing_idx; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("OFDM_index[%d]=%d\n", p, p_dm_odm->rf_calibrate_info.OFDM_index[p])); + break; + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("kfree_offset[%d]=%d\n", p, p_rf_calibrate_info->kfree_offset[p])); + + } + + /* calculate average thermal meter */ + p_dm_odm->rf_calibrate_info.thermal_value_avg[p_dm_odm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; + p_dm_odm->rf_calibrate_info.thermal_value_avg_index++; + if (p_dm_odm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) /* Average times = c.average_thermal_num */ + p_dm_odm->rf_calibrate_info.thermal_value_avg_index = 0; + + for (i = 0; i < c.average_thermal_num; i++) { + if (p_dm_odm->rf_calibrate_info.thermal_value_avg[i]) { + thermal_value_avg += p_dm_odm->rf_calibrate_info.thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */ + thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther)); + } + + /* 4 Calculate delta, delta_LCK, delta_IQK. */ + delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther); + delta_LCK = RTL_ABS(thermal_value, p_dm_odm->rf_calibrate_info.thermal_value_lck); + delta_IQK = RTL_ABS(thermal_value, p_dm_odm->rf_calibrate_info.thermal_value_iqk); + is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1); + + /* 4 if necessary, do LCK. */ + if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) { + if (delta_LCK > c.threshold_iqk) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk)); + p_dm_odm->rf_calibrate_info.thermal_value_lck = thermal_value; + + /*Use RTLCK, so close power tracking driver LCK*/ +#if (RTL8814A_SUPPORT != 1) + if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) { + if (c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(p_dm_odm); + } +#endif + } + } + + if (delta_IQK > c.threshold_iqk) { + panic_printk("%s(%d)\n", __FUNCTION__, __LINE__); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk)); + p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value; + if (c.do_iqk) + (*c.do_iqk)(p_dm_odm, true, 0, 0); + } + + if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ + return; + + /* 4 Do Power Tracking */ + + if (is_tssi_enable == true) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter PURE TSSI MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0); + } else if (thermal_value != p_dm_odm->rf_calibrate_info.thermal_value) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n******** START POWER TRACKING ********\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, p_dm_odm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther)); + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + if (is_increase) { /* thermal is higher than base */ + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + } + } + } else { /* thermal is lower than base */ + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta])); + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + } + } + } + + if (is_increase) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power --->\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power --->\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + } + } +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__)); + /* update thermal meter value */ + p_dm_odm->rf_calibrate_info.thermal_value = thermal_value; + + } +} +#endif + +#if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1) +void +odm_txpowertracking_callback_thermal_meter_jaguar_series( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + unsigned char thermal_value = 0, delta, delta_LCK, channel, is_decrease; + unsigned char thermal_value_avg_count = 0; + unsigned int thermal_value_avg = 0, reg0x18; + unsigned int bb_swing_reg[4] = {0xc1c, 0xe1c, 0x181c, 0x1a1c}; + int ele_D, value32; + char OFDM_index[2], index; + unsigned int i = 0, j = 0, rf_path, max_rf_path = 2, rf; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + unsigned char OFDM_min_index = 7; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic */ + + + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || *(p_dm_odm->p_mp_mode)) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == false) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + +#if RTL8881A_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8881A) { + max_rf_path = 1; + if ((get_bonding_type_8881A() == BOND_8881AM || get_bonding_type_8881A() == BOND_8881AN) + && priv->pshare->rf_ft_var.use_intpa8881A && (*p_dm_odm->p_band_type == ODM_BAND_2_4G)) + OFDM_min_index = 6; /* intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phy_band_select == PHY_BAND_2G)) */ + else + OFDM_min_index = 10; /* OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic */ + } +#endif + + + thermal_value = (unsigned char)phy_query_rf_reg(priv, RF_PATH_A, 0x42, 0xfc00, 1); /* 0x42: RF Reg[15:10] 88E */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther)); + + + /* 4 Query OFDM BB swing default setting Bit[31:21] */ + for (rf_path = 0 ; rf_path < max_rf_path ; rf_path++) { + ele_D = phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D)); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */ + if (ele_D == ofdm_swing_table_8812[i]) { + OFDM_index[rf_path] = (unsigned char)i; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path])); + break; + } + } + } +#if 0 + /* Query OFDM path A default setting Bit[31:21] */ + ele_D = phy_query_bb_reg(priv, 0xc1c, 0xffe00000); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D)); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */ + if (ele_D == ofdm_swing_table_8812[i]) { + OFDM_index[0] = (unsigned char)i; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("OFDM_index[0]=%d\n", OFDM_index[0])); + break; + } + } + /* Query OFDM path B default setting */ + if (rf == 2) { + ele_D = phy_query_bb_reg(priv, 0xe1c, 0xffe00000); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D)); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) { + if (ele_D == ofdm_swing_table_8812[i]) { + OFDM_index[1] = (unsigned char)i; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("OFDM_index[1]=%d\n", OFDM_index[1])); + break; + } + } + } +#endif + /* Initialize */ + if (!priv->pshare->thermal_value) { + priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther; + priv->pshare->thermal_value_lck = thermal_value; + } + + /* calculate average thermal meter */ + { + priv->pshare->thermal_value_avg_8812[priv->pshare->thermal_value_avg_index_8812] = thermal_value; + priv->pshare->thermal_value_avg_index_8812++; + if (priv->pshare->thermal_value_avg_index_8812 == AVG_THERMAL_NUM_8812) + priv->pshare->thermal_value_avg_index_8812 = 0; + + for (i = 0; i < AVG_THERMAL_NUM_8812; i++) { + if (priv->pshare->thermal_value_avg_8812[i]) { + thermal_value_avg += priv->pshare->thermal_value_avg_8812[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { + thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count); + /* printk("AVG Thermal Meter = 0x%x\n", thermal_value); */ + } + } + + + /* 4 If necessary, do power tracking */ + + if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ + return; + + if (thermal_value != priv->pshare->thermal_value) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** START POWER TRACKING ********\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther)); + delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther); + delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck); + is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0); + /* if (*p_dm_odm->p_band_type == ODM_BAND_5G) */ + { +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + for (rf_path = 0; rf_path < max_rf_path; rf_path++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); + if (is_decrease) { + OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); + OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); +#if 0/* RTL8881A_SUPPORT */ + if (p_dm_odm->support_ic_type == ODM_RTL8881A) { + if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) { + if (priv->pshare->add_tx_agc) { /* tx_agc has been added */ + add_tx_power88xx_ac(priv, 0); + priv->pshare->add_tx_agc = 0; + priv->pshare->add_tx_agc_index = 0; + } + } + } +#endif + } else { + + OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); +#if 0/* RTL8881A_SUPPORT */ + if (p_dm_odm->support_ic_type == ODM_RTL8881A) { + if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) { + if (OFDM_index[i] < OFDM_min_index) { + priv->pshare->add_tx_agc_index = (OFDM_min_index - OFDM_index[i]) / 2; /* Calculate Remnant tx_agc value, 2 index for 1 tx_agc */ + add_tx_power88xx_ac(priv, priv->pshare->add_tx_agc_index); + priv->pshare->add_tx_agc = 1; /* add_tx_agc Flag = 1 */ + OFDM_index[i] = OFDM_min_index; + } else { + if (priv->pshare->add_tx_agc) { /* tx_agc been added */ + priv->pshare->add_tx_agc = 0; + priv->pshare->add_tx_agc_index = 0; + add_tx_power88xx_ac(priv, 0); /* minus the added TPI */ + } + } + } + } +#else + OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ? OFDM_min_index : OFDM_index[rf_path]); +#endif + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); + } + } + } +#endif + /* 4 Set new BB swing index */ + for (rf_path = 0; rf_path < max_rf_path; rf_path++) { + phy_set_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000, ofdm_swing_table_8812[(unsigned int)OFDM_index[rf_path]]); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path])); + } + + } + if (delta_LCK > 8) { + RTL_W8(0x522, 0xff); + reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1); + phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1); + phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1); + delay_ms(200); /* frequency deviation */ + phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0); + phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18); +#ifdef CONFIG_RTL_8812_SUPPORT + if (GET_CHIP_VER(priv) == VERSION_8812E) + update_bbrf_val8812(priv, priv->pmib->dot11RFEntry.dot11channel); +#endif + RTL_W8(0x522, 0x0); + priv->pshare->thermal_value_lck = thermal_value; + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__)); + + /* update thermal meter value */ + priv->pshare->thermal_value = thermal_value; + for (rf_path = 0; rf_path < max_rf_path; rf_path++) + priv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path]; + } +} + +#endif + + +void +odm_txpowertracking_callback_thermal_meter( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + +#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8197F || p_dm_odm->support_ic_type == ODM_RTL8822B) { + odm_txpowertracking_callback_thermal_meter_jaguar_series3(p_dm_odm); + return; + } +#endif +#if (RTL8814A_SUPPORT == 1) /*use this function to do power tracking after 8814 by YuChen*/ + if (p_dm_odm->support_ic_type & ODM_RTL8814A) { + odm_txpowertracking_callback_thermal_meter_jaguar_series2(p_dm_odm); + return; + } +#endif +#if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8812 || p_dm_odm->support_ic_type & ODM_RTL8881A) { + odm_txpowertracking_callback_thermal_meter_jaguar_series(p_dm_odm); + return; + } +#endif + +#if (RTL8192E_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + odm_txpowertracking_callback_thermal_meter_92e(p_dm_odm); + return; + } +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + /* PMGNT_INFO p_mgnt_info = &adapter->mgnt_info; */ +#endif + + + u8 thermal_value = 0, delta, delta_LCK, delta_IQK, offset; + u8 thermal_value_avg_count = 0; + u32 thermal_value_avg = 0; + /* s32 ele_A=0, ele_D, TempCCk, X, value32; + * s32 Y, ele_C=0; + * s8 OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index; + * s8 deltaPowerIndex = 0; */ + u32 i = 0;/* , j = 0; */ + boolean is2T = false; + /* bool bInteralPA = false; */ + + u8 OFDM_max_index = 34, rf = (is2T) ? 2 : 1; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ + u8 indexforchannel = 0;/*get_right_chnl_place_for_iqk(p_hal_data->current_channel)*/ + enum _POWER_DEC_INC { POWER_DEC, POWER_INC }; + + struct _TXPWRTRACK_CFG c; + + + /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ + s8 delta_swing_table_idx[2][index_mapping_NUM_88E] = { + /* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */ + {0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11}, {0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 7, 8, 9, 9, 10} + }; + u8 thermal_threshold[2][index_mapping_NUM_88E] = { + /* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */ + {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27}, {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25} + }; + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + struct rtl8192cd_priv *priv = p_dm_odm->priv; +#endif + + /* 4 2. Initilization ( 7 steps in total ) */ + + configure_txpower_track(p_dm_odm, &c); + + p_dm_odm->rf_calibrate_info.txpowertracking_callback_cnt++; /* cosa add for debug */ + p_dm_odm->rf_calibrate_info.is_txpowertracking_init = true; + +#if (MP_DRIVER == 1) + p_dm_odm->rf_calibrate_info.txpowertrack_control = p_hal_data->txpowertrack_control; /* We should keep updating the control variable according to HalData. + * rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */ + p_dm_odm->rf_calibrate_info.rega24 = 0x090e1317; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST) + if ((OPMODE & WIFI_MP_STATE) || *(p_dm_odm->p_mp_mode)) { + if (p_dm_odm->priv->pshare->mp_txpwr_tracking == false) + return; + } +#endif + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>odm_txpowertracking_callback_thermal_meter_8188e, p_dm_odm->bb_swing_idx_cck_base: %d, p_dm_odm->bb_swing_idx_ofdm_base: %d\n", p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base)); + /* + if (!p_dm_odm->rf_calibrate_info.tm_trigger) { + odm_set_rf_reg(p_dm_odm, RF_PATH_A, c.thermal_reg_addr, BIT(17) | BIT(16), 0x3); + p_dm_odm->rf_calibrate_info.tm_trigger = 1; + return; + } + */ + thermal_value = (u8)odm_get_rf_reg(p_dm_odm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (!thermal_value || !p_dm_odm->rf_calibrate_info.txpowertrack_control) +#else + if (!p_dm_odm->rf_calibrate_info.txpowertrack_control) +#endif + return; + + /* 4 3. Initialize ThermalValues of rf_calibrate_info */ + + if (!p_dm_odm->rf_calibrate_info.thermal_value) { + p_dm_odm->rf_calibrate_info.thermal_value_lck = thermal_value; + p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value; + } + + if (p_dm_odm->rf_calibrate_info.is_reloadtxpowerindex) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n")); + + /* 4 4. Calculate average thermal meter */ + + p_dm_odm->rf_calibrate_info.thermal_value_avg[p_dm_odm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; + p_dm_odm->rf_calibrate_info.thermal_value_avg_index++; + if (p_dm_odm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) + p_dm_odm->rf_calibrate_info.thermal_value_avg_index = 0; + + for (i = 0; i < c.average_thermal_num; i++) { + if (p_dm_odm->rf_calibrate_info.thermal_value_avg[i]) { + thermal_value_avg += p_dm_odm->rf_calibrate_info.thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { + /* Give the new thermo value a weighting */ + thermal_value_avg += (thermal_value * 4); + + thermal_value = (u8)(thermal_value_avg / (thermal_value_avg_count + 4)); + p_rf_calibrate_info->thermal_value_delta = thermal_value - priv->pmib->dot11RFEntry.ther; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("AVG Thermal Meter = 0x%x\n", thermal_value)); + } + + /* 4 5. Calculate delta, delta_LCK, delta_IQK. */ + + delta = (thermal_value > p_dm_odm->rf_calibrate_info.thermal_value) ? (thermal_value - p_dm_odm->rf_calibrate_info.thermal_value) : (p_dm_odm->rf_calibrate_info.thermal_value - thermal_value); + delta_LCK = (thermal_value > p_dm_odm->rf_calibrate_info.thermal_value_lck) ? (thermal_value - p_dm_odm->rf_calibrate_info.thermal_value_lck) : (p_dm_odm->rf_calibrate_info.thermal_value_lck - thermal_value); + delta_IQK = (thermal_value > p_dm_odm->rf_calibrate_info.thermal_value_iqk) ? (thermal_value - p_dm_odm->rf_calibrate_info.thermal_value_iqk) : (p_dm_odm->rf_calibrate_info.thermal_value_iqk - thermal_value); + + /* 4 6. If necessary, do LCK. */ + if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) { + /*if((delta_LCK > p_hal_data->delta_lck) && (p_hal_data->delta_lck != 0))*/ + if (delta_LCK >= c.threshold_iqk) { + /*Delta temperature is equal to or larger than 20 centigrade.*/ + p_dm_odm->rf_calibrate_info.thermal_value_lck = thermal_value; + (*c.phy_lc_calibrate)(p_dm_odm); + } + } + + /* 3 7. If necessary, move the index of swing table to adjust Tx power. */ + + if (delta > 0 && p_dm_odm->rf_calibrate_info.txpowertrack_control) { + + delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value); + + /* 4 7.1 The Final Power index = BaseIndex + power_index_offset */ + + if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) { + CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta); + p_dm_odm->rf_calibrate_info.delta_power_index_last = p_dm_odm->rf_calibrate_info.delta_power_index; + p_dm_odm->rf_calibrate_info.delta_power_index = delta_swing_table_idx[POWER_INC][offset]; + + } else { + + CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta); + p_dm_odm->rf_calibrate_info.delta_power_index_last = p_dm_odm->rf_calibrate_info.delta_power_index; + p_dm_odm->rf_calibrate_info.delta_power_index = (-1) * delta_swing_table_idx[POWER_DEC][offset]; + } + + if (p_dm_odm->rf_calibrate_info.delta_power_index == p_dm_odm->rf_calibrate_info.delta_power_index_last) + p_dm_odm->rf_calibrate_info.power_index_offset = 0; + else + p_dm_odm->rf_calibrate_info.power_index_offset = p_dm_odm->rf_calibrate_info.delta_power_index - p_dm_odm->rf_calibrate_info.delta_power_index_last; + + for (i = 0; i < rf; i++) + p_dm_odm->rf_calibrate_info.OFDM_index[i] = p_rf_calibrate_info->bb_swing_idx_ofdm_base + p_dm_odm->rf_calibrate_info.power_index_offset; + p_dm_odm->rf_calibrate_info.CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_dm_odm->rf_calibrate_info.power_index_offset; + + p_rf_calibrate_info->bb_swing_idx_cck = p_dm_odm->rf_calibrate_info.CCK_index; + p_rf_calibrate_info->bb_swing_idx_ofdm[RF_PATH_A] = p_dm_odm->rf_calibrate_info.OFDM_index[RF_PATH_A]; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_dm_odm->rf_calibrate_info.power_index_offset)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[RF_PATH_A], p_rf_calibrate_info->bb_swing_idx_ofdm_base, p_dm_odm->rf_calibrate_info.power_index_offset)); + + /* 4 7.1 Handle boundary conditions of index. */ + + + for (i = 0; i < rf; i++) { + if (p_dm_odm->rf_calibrate_info.OFDM_index[i] > OFDM_max_index) + p_dm_odm->rf_calibrate_info.OFDM_index[i] = OFDM_max_index; + else if (p_dm_odm->rf_calibrate_info.OFDM_index[i] < 0) + p_dm_odm->rf_calibrate_info.OFDM_index[i] = 0; + } + + if (p_dm_odm->rf_calibrate_info.CCK_index > c.swing_table_size_cck - 1) + p_dm_odm->rf_calibrate_info.CCK_index = c.swing_table_size_cck - 1; + else if (p_dm_odm->rf_calibrate_info.CCK_index < 0) + p_dm_odm->rf_calibrate_info.CCK_index = 0; + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, p_dm_odm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, p_dm_odm->rf_calibrate_info.thermal_value)); + p_dm_odm->rf_calibrate_info.power_index_offset = 0; + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", p_dm_odm->rf_calibrate_info.CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", p_dm_odm->rf_calibrate_info.OFDM_index[RF_PATH_A], p_rf_calibrate_info->bb_swing_idx_ofdm_base)); + + if (p_dm_odm->rf_calibrate_info.power_index_offset != 0 && p_dm_odm->rf_calibrate_info.txpowertrack_control) { + /* 4 7.2 Configure the Swing Table to adjust Tx Power. */ + + p_dm_odm->rf_calibrate_info.is_tx_power_changed = true; /* Always true after Tx Power is adjusted by power tracking. */ + /* */ + /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */ + /* to increase TX power. Otherwise, EVM will be bad. */ + /* */ + /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ + if (thermal_value > p_dm_odm->rf_calibrate_info.thermal_value) { + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, */ + /* ("Temperature Increasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */ + /* p_dm_odm->rf_calibrate_info.power_index_offset, delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_dm_odm->rf_calibrate_info.thermal_value)); */ + } else if (thermal_value < p_dm_odm->rf_calibrate_info.thermal_value) { /* Low temperature */ + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, */ + /* ("Temperature Decreasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */ + /* p_dm_odm->rf_calibrate_info.power_index_offset, delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_dm_odm->rf_calibrate_info.thermal_value)); */ + } + if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) + { + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, p_hal_data->eeprom_thermal_meter)); */ + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TXAGC, 0, 0); + } else { + /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, p_hal_data->eeprom_thermal_meter)); */ + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, RF_PATH_A, indexforchannel); + if (is2T) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, RF_PATH_B, indexforchannel); + } + + p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck; + p_rf_calibrate_info->bb_swing_idx_ofdm_base = p_rf_calibrate_info->bb_swing_idx_ofdm[RF_PATH_A]; + p_dm_odm->rf_calibrate_info.thermal_value = thermal_value; + + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n")); + + p_dm_odm->rf_calibrate_info.tx_powercount = 0; +} + +/* 3============================================================ + * 3 IQ Calibration + * 3============================================================ */ + +void +odm_reset_iqk_result( + void *p_dm_void +) +{ + return; +} +#if 1/* !(DM_ODM_SUPPORT_TYPE & ODM_AP) */ +u8 odm_get_right_chnl_place_for_iqk(u8 chnl) +{ + u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165 + }; + u8 place = chnl; + + + if (chnl > 14) { + for (place = 14; place < sizeof(channel_all); place++) { + if (channel_all[place] == chnl) + return place - 13; + } + } + return 0; + +} +#endif + +void +odm_iq_calibrate( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + if (p_dm_odm->is_linked) { + if ((*p_dm_odm->p_channel != p_dm_odm->pre_channel) && (!*p_dm_odm->p_is_scan_in_process)) { + p_dm_odm->pre_channel = *p_dm_odm->p_channel; + p_dm_odm->linked_interval = 0; + } + + if (p_dm_odm->linked_interval < 3) + p_dm_odm->linked_interval++; + + if (p_dm_odm->linked_interval == 2) { + +#if (RTL8814A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8814A) + phy_iq_calibrate_8814a(p_dm_odm, false); +#endif + +#if (RTL8822B_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8822B) + phy_iq_calibrate_8822b(p_dm_odm, false); +#endif + +#if (RTL8821C_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + phy_iq_calibrate_8821c(p_dm_odm, false); +#endif + +#if (RTL8821A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8821) + phy_iq_calibrate_8821a(p_dm_odm, false); +#endif + +#if (RTL8812A_SUPPORT == 1) + if (p_dm_odm->support_ic_type == ODM_RTL8812) + _phy_iq_calibrate_8812a(p_dm_odm, false); +#endif + } + } else + p_dm_odm->linked_interval = 0; + +} + +void phydm_rf_init(void *p_dm_void) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + odm_txpowertracking_init(p_dm_odm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8814A_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + phy_iq_calibrate_8814a_init(p_dm_odm); +#endif +#endif + +} + +void phydm_rf_watchdog(void *p_dm_void) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + odm_txpowertracking_check(p_dm_odm); + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + odm_iq_calibrate(p_dm_odm); +#endif +} diff --git a/hal/phydm/halrf/halphyrf_ap.h b/hal/phydm/halrf/halphyrf_ap.h new file mode 100644 index 0000000..f3e2eb6 --- /dev/null +++ b/hal/phydm/halrf/halphyrf_ap.h @@ -0,0 +1,127 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_H__ +#define __HAL_PHY_RF_H__ + +#include "halrf/halrf_powertracking_ap.h" +#include "halrf/halrf_kfree.h" + +#if (RTL8814A_SUPPORT == 1) + #include "halrf/rtl8814a/halrf_iqk_8814a.h" +#endif + +#if (RTL8822B_SUPPORT == 1) + #include "halrf/rtl8822b/halrf_iqk_8822b.h" +#endif + +#if (RTL8821C_SUPPORT == 1) + #include "halrf/rtl8822b/halrf_iqk_8821c.h" +#endif + +enum pwrtrack_method { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE +}; + +typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8); +typedef void(*func_iqk)(void *, u8, u8, u8); +typedef void (*func_lck)(void *); +/* refine by YuChen for 8814A */ +typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **); + + +struct _TXPWRTRACK_CFG { + u8 swing_table_size_cck; + u8 swing_table_size_ofdm; + u8 threshold_iqk; + u8 threshold_dpk; + u8 average_thermal_num; + u8 rf_path_count; + u32 thermal_reg_addr; + func_set_pwr odm_tx_pwr_track_set_pwr; + func_iqk do_iqk; + func_lck phy_lc_calibrate; + func_swing get_delta_swing_table; + func_swing8814only get_delta_swing_table8814only; + func_all_swing get_delta_all_swing_table; +}; + +void +configure_txpower_track( + void *p_dm_void, + struct _TXPWRTRACK_CFG *p_config +); + + +void +odm_txpowertracking_callback_thermal_meter( + void *p_dm_void +); + +#if (RTL8192E_SUPPORT == 1) +void +odm_txpowertracking_callback_thermal_meter_92e( + void *p_dm_void +); +#endif + +#if (RTL8814A_SUPPORT == 1) +void +odm_txpowertracking_callback_thermal_meter_jaguar_series2( + void *p_dm_void +); + +#elif ODM_IC_11AC_SERIES_SUPPORT +void +odm_txpowertracking_callback_thermal_meter_jaguar_series( + void *p_dm_void +); + +#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) +void +odm_txpowertracking_callback_thermal_meter_jaguar_series3( + void *p_dm_void +); + +#endif + +#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M) + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +void +odm_reset_iqk_result( + void *p_dm_void +); +u8 +odm_get_right_chnl_place_for_iqk( + u8 chnl +); + +void phydm_rf_init(void *p_dm_void); +void phydm_rf_watchdog(void *p_dm_void); + +#endif /* #ifndef __HAL_PHY_RF_H__ */ diff --git a/hal/phydm/halrf/halphyrf_ce.c b/hal/phydm/halrf/halphyrf_ce.c new file mode 100644 index 0000000..dcb2e87 --- /dev/null +++ b/hal/phydm/halrf/halphyrf_ce.c @@ -0,0 +1,914 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \ + do {\ + for (_offset = 0; _offset < _size; _offset++) { \ + \ + if (_delta_thermal < thermal_threshold[_direction][_offset]) { \ + \ + if (_offset != 0)\ + _offset--;\ + break;\ + } \ + } \ + if (_offset >= _size)\ + _offset = _size-1;\ + } while (0) + +void configure_txpower_track( + void *p_dm_void, + struct _TXPWRTRACK_CFG *p_config +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + +#if RTL8192E_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8192E) + configure_txpower_track_8192e(p_config); +#endif +#if RTL8821A_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8821) + configure_txpower_track_8821a(p_config); +#endif +#if RTL8812A_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8812) + configure_txpower_track_8812a(p_config); +#endif +#if RTL8188E_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8188E) + configure_txpower_track_8188e(p_config); +#endif + +#if RTL8723B_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8723B) + configure_txpower_track_8723b(p_config); +#endif + +#if RTL8814A_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8814A) + configure_txpower_track_8814a(p_config); +#endif + +#if RTL8703B_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8703B) + configure_txpower_track_8703b(p_config); +#endif + +#if RTL8188F_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8188F) + configure_txpower_track_8188f(p_config); +#endif +#if RTL8723D_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8723D) + configure_txpower_track_8723d(p_config); +#endif +/* JJ ADD 20161014 */ +#if RTL8710B_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8710B) + configure_txpower_track_8710b(p_config); +#endif + +#if RTL8822B_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8822B) + configure_txpower_track_8822b(p_config); +#endif +#if RTL8821C_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + configure_txpower_track_8821c(p_config); +#endif + +} + +/* ********************************************************************** + * <20121113, Kordan> This function should be called when tx_agc changed. + * Otherwise the previous compensation is gone, because we record the + * delta of temperature between two TxPowerTracking watch dogs. + * + * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still + * need to call this function. + * ********************************************************************** */ +void +odm_clear_txpowertracking_state( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv); +#else + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); +#endif + u8 p = 0; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index; + p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index; + p_dm_odm->rf_calibrate_info.CCK_index = 0; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) { + p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index; + + p_rf_calibrate_info->power_index_offset[p] = 0; + p_rf_calibrate_info->delta_power_index[p] = 0; + p_rf_calibrate_info->delta_power_index_last[p] = 0; + + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/ + p_rf_calibrate_info->remnant_ofdm_swing_idx[p] = 0; + p_rf_calibrate_info->kfree_offset[p] = 0; + } + + p_rf_calibrate_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/ + p_rf_calibrate_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/ + p_rf_calibrate_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/ + p_rf_calibrate_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/ + p_rf_calibrate_info->remnant_cck_swing_idx = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + p_rf_calibrate_info->thermal_value = rtlefu->eeprom_thermalmeter; +#else + p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter; +#endif + + p_rf_calibrate_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */ + p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */ + +} + +void +odm_txpowertracking_callback_thermal_meter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + struct PHY_DM_STRUCT *p_dm_odm +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *p_dm_void +#else + struct _ADAPTER *adapter +#endif +) +{ + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv); + void *adapter = p_dm_odm->adapter; +#elif !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; +#endif +#endif + + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; + s8 diff_DPK[4] = {0}; + u8 thermal_value_avg_count = 0; + u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4; + + u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ + u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(p_hal_data->current_channel) */ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + u8 power_tracking_type = 0; /* no specify type */ +#else + u8 power_tracking_type = p_hal_data->rf_power_tracking_type; +#endif + u8 xtal_offset_eanble = 0; + s8 thermal_value_temp = 0; + + struct _TXPWRTRACK_CFG c; + + /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ + u8 *delta_swing_table_idx_tup_a = NULL; + u8 *delta_swing_table_idx_tdown_a = NULL; + u8 *delta_swing_table_idx_tup_b = NULL; + u8 *delta_swing_table_idx_tdown_b = NULL; + /*for 8814 add by Yu Chen*/ + u8 *delta_swing_table_idx_tup_c = NULL; + u8 *delta_swing_table_idx_tdown_c = NULL; + u8 *delta_swing_table_idx_tup_d = NULL; + u8 *delta_swing_table_idx_tdown_d = NULL; + /*for Xtal Offset by James.Tung*/ + s8 *delta_swing_table_xtal_up = NULL; + s8 *delta_swing_table_xtal_down = NULL; + + /* 4 2. Initilization ( 7 steps in total ) */ + + configure_txpower_track(p_dm_odm, &c); + + (*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, + (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b); + + if (p_dm_odm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/ + (*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c, + (u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d); + /* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/ + (*c.get_delta_swing_xtal_table)(p_dm_odm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down); + + p_rf_calibrate_info->txpowertracking_callback_cnt++; /*cosa add for debug*/ + p_rf_calibrate_info->is_txpowertracking_init = true; + + /*p_rf_calibrate_info->txpowertrack_control = p_hal_data->txpowertrack_control; + We should keep updating the control variable according to HalData. + rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + p_rf_calibrate_info->rega24 = 0x090e1317; +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (*(p_dm_odm->p_mp_mode) == true) + p_rf_calibrate_info->rega24 = 0x090e1317; +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("===>odm_txpowertracking_callback_thermal_meter\n p_rf_calibrate_info->bb_swing_idx_cck_base: %d, p_rf_calibrate_info->bb_swing_idx_ofdm_base[A]: %d, p_rf_calibrate_info->default_ofdm_index: %d\n", + p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A], p_rf_calibrate_info->default_ofdm_index)); + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("p_rf_calibrate_info->txpowertrack_control=%d, rtlefu->eeprom_thermalmeter %d\n", p_rf_calibrate_info->txpowertrack_control, rtlefu->eeprom_thermalmeter)); +#else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("p_rf_calibrate_info->txpowertrack_control=%d, p_hal_data->eeprom_thermal_meter %d\n", p_rf_calibrate_info->txpowertrack_control, p_hal_data->eeprom_thermal_meter)); +#endif + + thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + + thermal_value_temp = thermal_value + phydm_get_thermal_offset(p_dm_odm); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("thermal_value_temp(%d) = thermal_value(%d) + power_trim_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(p_dm_odm))); + + if (thermal_value_temp > 63) + thermal_value = 63; + else if (thermal_value_temp < 0) + thermal_value = 0; + else + thermal_value = thermal_value_temp; + + /*add log by zhao he, check c80/c94/c14/ca0 value*/ + if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4)); + } + /* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4)); + } + + if (!p_rf_calibrate_info->txpowertrack_control) + return; + + if (p_hal_data->eeprom_thermal_meter == 0xff) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no pg, p_hal_data->eeprom_thermal_meter = 0x%x\n", p_hal_data->eeprom_thermal_meter)); + return; + } + + /*4 3. Initialize ThermalValues of rf_calibrate_info*/ + + if (p_rf_calibrate_info->is_reloadtxpowerindex) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n")); + + /*4 4. Calculate average thermal meter*/ + + p_rf_calibrate_info->thermal_value_avg[p_rf_calibrate_info->thermal_value_avg_index] = thermal_value; + p_rf_calibrate_info->thermal_value_avg_index++; + if (p_rf_calibrate_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ + p_rf_calibrate_info->thermal_value_avg_index = 0; + + for (i = 0; i < c.average_thermal_num; i++) { + if (p_rf_calibrate_info->thermal_value_avg[i]) { + thermal_value_avg += p_rf_calibrate_info->thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */ + thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + p_rf_calibrate_info->thermal_value_delta = thermal_value - rtlefu->eeprom_thermalmeter; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, rtlefu->eeprom_thermalmeter)); +#else + p_rf_calibrate_info->thermal_value_delta = thermal_value - p_hal_data->eeprom_thermal_meter; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, p_hal_data->eeprom_thermal_meter)); +#endif + } + + /* 4 5. Calculate delta, delta_LCK, delta_IQK. */ + + /* "delta" here is used to determine whether thermal value changes or not. */ + delta = (thermal_value > p_rf_calibrate_info->thermal_value) ? (thermal_value - p_rf_calibrate_info->thermal_value) : (p_rf_calibrate_info->thermal_value - thermal_value); + delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value); + delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value); + + if (p_rf_calibrate_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/ + p_rf_calibrate_info->thermal_value_iqk = thermal_value; + delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use thermal_value for IQK\n")); + } + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + diff_DPK[p] = (s8)thermal_value - (s8)p_rf_calibrate_info->dpk_thermal[p]; + + /*4 6. If necessary, do LCK.*/ + + if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/ + if (p_rf_calibrate_info->thermal_value_lck == 0xff) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); + p_rf_calibrate_info->thermal_value_lck = thermal_value; + + /*Use RTLCK, so close power tracking driver LCK*/ + if (!(p_dm_odm->support_ic_type & ODM_RTL8814A) && c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(p_dm_odm); + + delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value); + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); + + /* Wait sacn to do LCK by RF Jenyu*/ + if (*p_dm_odm->p_is_scan_in_process == false) { + /* Delta temperature is equal to or larger than 20 centigrade.*/ + if (delta_LCK >= c.threshold_iqk) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk)); + p_rf_calibrate_info->thermal_value_lck = thermal_value; + + /*Use RTLCK, so close power tracking driver LCK*/ + if (!(p_dm_odm->support_ic_type & ODM_RTL8814A) && c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(p_dm_odm); + } + } + } + + /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ + + if (delta > 0 && p_rf_calibrate_info->txpowertrack_control) { + /* "delta" here is used to record the absolute value of differrence. */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + delta = thermal_value > rtlefu->eeprom_thermalmeter ? (thermal_value - rtlefu->eeprom_thermalmeter) : (rtlefu->eeprom_thermalmeter - thermal_value); +#else + delta = thermal_value > p_hal_data->eeprom_thermal_meter ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value); +#endif +#else + delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value); +#endif + if (delta >= TXPWR_TRACK_TABLE_SIZE) + delta = TXPWR_TRACK_TABLE_SIZE - 1; + + /*4 7.1 The Final Power index = BaseIndex + power_index_offset*/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + if (thermal_value > rtlefu->eeprom_thermalmeter) { +#else + if (thermal_value > p_hal_data->eeprom_thermal_meter) { +#endif +#else + if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) { +#endif + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/ + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta])); + + p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta])); + + p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta])); + + p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta])); + + p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + } + } + /* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + /*Save xtal_offset from Xtal table*/ + p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta])); + p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_up[delta]; + xtal_offset_eanble = (p_rf_calibrate_info->xtal_offset_last != p_rf_calibrate_info->xtal_offset); + } + + } else { + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/ + + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta])); + p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta])); + p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta])); + p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta])); + p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + } + } + /* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + /*Save xtal_offset from Xtal table*/ + p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta])); + p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_down[delta]; + xtal_offset_eanble = (p_rf_calibrate_info->xtal_offset_last != p_rf_calibrate_info->xtal_offset); + } + + } + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p)); + + if (p_rf_calibrate_info->delta_power_index[p] == p_rf_calibrate_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/ + p_rf_calibrate_info->power_index_offset[p] = 0; + else + p_rf_calibrate_info->power_index_offset[p] = p_rf_calibrate_info->delta_power_index[p] - p_rf_calibrate_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, p_rf_calibrate_info->power_index_offset[p], p_rf_calibrate_info->delta_power_index[p], p_rf_calibrate_info->delta_power_index_last[p])); + + p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] + p_rf_calibrate_info->power_index_offset[p]; + p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_rf_calibrate_info->power_index_offset[p]; + + p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->CCK_index; + p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->OFDM_index[p]; + + /*************Print BB Swing base and index Offset*************/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->power_index_offset[p])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p], p_rf_calibrate_info->power_index_offset[p])); + + /*4 7.1 Handle boundary conditions of index.*/ + + if (p_rf_calibrate_info->OFDM_index[p] > c.swing_table_size_ofdm - 1) + p_rf_calibrate_info->OFDM_index[p] = c.swing_table_size_ofdm - 1; + else if (p_rf_calibrate_info->OFDM_index[p] <= OFDM_min_index) + p_rf_calibrate_info->OFDM_index[p] = OFDM_min_index; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n========================================================================================================\n")); + + if (p_rf_calibrate_info->CCK_index > c.swing_table_size_cck - 1) + p_rf_calibrate_info->CCK_index = c.swing_table_size_cck - 1; + else if (p_rf_calibrate_info->CCK_index <= 0) + p_rf_calibrate_info->CCK_index = 0; + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, p_rf_calibrate_info->thermal_value: %d\n", + p_rf_calibrate_info->txpowertrack_control, thermal_value, p_rf_calibrate_info->thermal_value)); + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + p_rf_calibrate_info->power_index_offset[p] = 0; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", + p_rf_calibrate_info->CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base)); /*Print Swing base & current*/ + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n", + p_rf_calibrate_info->OFDM_index[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p])); + } + + if ((p_dm_odm->support_ic_type & ODM_RTL8814A)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("power_tracking_type=%d\n", power_tracking_type)); + + if (power_tracking_type == 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + } else if (power_tracking_type == 1) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_2G_TSSI_5G_MODE, p, 0); + } else if (power_tracking_type == 2) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_5G_TSSI_2G_MODE, p, 0); + } else if (power_tracking_type == 3) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0); + } + p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + + } else if ((p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_A] != 0 || + p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_B] != 0 || + p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_C] != 0 || + p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_D] != 0) && +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + p_rf_calibrate_info->txpowertrack_control && (rtlefu->eeprom_thermalmeter != 0xff)) { +#else + p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) { +#endif + /* 4 7.2 Configure the Swing Table to adjust Tx Power. */ + + p_rf_calibrate_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/ + /* */ + /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */ + /* to increase TX power. Otherwise, EVM will be bad. */ + /* */ + /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ + if (thermal_value > p_rf_calibrate_info->thermal_value) { + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, rtlefu->eeprom_thermalmeter, p_rf_calibrate_info->thermal_value)); +#else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value)); +#endif + } + } else if (thermal_value < p_rf_calibrate_info->thermal_value) { /*Low temperature*/ + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, rtlefu->eeprom_thermalmeter, p_rf_calibrate_info->thermal_value)); +#else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value)); +#endif + } + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + if (thermal_value > rtlefu->eeprom_thermalmeter) +#else + if (thermal_value > p_hal_data->eeprom_thermal_meter) +#endif +#else + if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) +#endif + { +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter)); +#else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); +#endif + + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 || + p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A || + p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B || + p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel); + } + } else { +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter)); +#else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); +#endif + + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 || + p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A || + p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B || + p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, indexforchannel); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel); + } + + } + + p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/ + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->bb_swing_idx_ofdm[p]; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("p_rf_calibrate_info->thermal_value = %d thermal_value= %d\n", p_rf_calibrate_info->thermal_value, thermal_value)); + + p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + + } + + + if (p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + if (xtal_offset_eanble != 0 && p_rf_calibrate_info->txpowertrack_control && (rtlefu->eeprom_thermalmeter != 0xff)) { +#else + if (xtal_offset_eanble != 0 && p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) { +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n")); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + if (thermal_value > rtlefu->eeprom_thermalmeter) { +#else + if (thermal_value > p_hal_data->eeprom_thermal_meter) { +#endif +#else + if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) { +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter)); +#else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); +#endif + (*c.odm_txxtaltrack_set_xtal)(p_dm_odm); + } else { +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter)); +#else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); +#endif + (*c.odm_txxtaltrack_set_xtal)(p_dm_odm); + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n")); + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + /* Wait sacn to do IQK by RF Jenyu*/ + if (*p_dm_odm->p_is_scan_in_process == false) { + if (!IS_HARDWARE_TYPE_8723B(adapter)) { + /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ + if (delta_IQK >= c.threshold_iqk) { + p_rf_calibrate_info->thermal_value_iqk = thermal_value; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk)); + if (!p_rf_calibrate_info->is_iqk_in_progress) + (*c.do_iqk)(p_dm_odm, delta_IQK, thermal_value, 8); + } + } + } + if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_A] != 0) { + if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) { + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk)); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk); + + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } else { + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } + } + if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_B] != 0) { + if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) { + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk)); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk); + + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } else { + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } + } + +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===odm_txpowertracking_callback_thermal_meter\n")); + + p_rf_calibrate_info->tx_powercount = 0; +} + + + +/* 3============================================================ + * 3 IQ Calibration + * 3============================================================ */ + +void +odm_reset_iqk_result( + void *p_dm_void +) +{ + return; +} +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +u8 odm_get_right_chnl_place_for_iqk(u8 chnl) +{ + u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165 + }; + u8 place = chnl; + + + if (chnl > 14) { + for (place = 14; place < sizeof(channel_all); place++) { + if (channel_all[place] == chnl) + return place - 13; + } + } + return 0; + +} +#endif + +void +odm_iq_calibrate( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (*p_dm_odm->p_is_fcs_mode_enable) + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + if (IS_HARDWARE_TYPE_8812AU(adapter)) + return; +#endif + + if (p_dm_odm->is_linked) { + if ((*p_dm_odm->p_channel != p_dm_odm->pre_channel) && (!*p_dm_odm->p_is_scan_in_process)) { + p_dm_odm->pre_channel = *p_dm_odm->p_channel; + p_dm_odm->linked_interval = 0; + } + + if (p_dm_odm->linked_interval < 3) + p_dm_odm->linked_interval++; + + if (p_dm_odm->linked_interval == 2) { + if (IS_HARDWARE_TYPE_8814A(adapter)) { +#if (RTL8814A_SUPPORT == 1) + phy_iq_calibrate_8814a(p_dm_odm, false); +#endif + } + +#if (RTL8822B_SUPPORT == 1) + else if (IS_HARDWARE_TYPE_8822B(adapter)) + phy_iq_calibrate_8822b(p_dm_odm, false); +#endif + +#if (RTL8821C_SUPPORT == 1) + else if (IS_HARDWARE_TYPE_8821C(adapter)) + phy_iq_calibrate_8821c(p_dm_odm, false); +#endif + +#if (RTL8821A_SUPPORT == 1) + else if (IS_HARDWARE_TYPE_8821(adapter)) + phy_iq_calibrate_8821a(p_dm_odm, false); +#endif + } + } else + p_dm_odm->linked_interval = 0; +} + +void phydm_rf_init(void *p_dm_void) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + odm_txpowertracking_init(p_dm_odm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + odm_clear_txpowertracking_state(p_dm_odm); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8814A_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + phy_iq_calibrate_8814a_init(p_dm_odm); +#endif +#endif + +} + +void phydm_rf_watchdog(void *p_dm_void) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + odm_txpowertracking_check(p_dm_odm); + /*if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)*/ + /*odm_iq_calibrate(p_dm_odm);*/ +#endif +} diff --git a/hal/phydm/halrf/halphyrf_ce.h b/hal/phydm/halrf/halphyrf_ce.h new file mode 100644 index 0000000..731842f --- /dev/null +++ b/hal/phydm/halrf/halphyrf_ce.h @@ -0,0 +1,119 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_H__ +#define __HAL_PHY_RF_H__ + +#include "halrf/halrf_kfree.h" +#if (RTL8814A_SUPPORT == 1) + #include "halrf/rtl8814a/halrf_iqk_8814a.h" +#endif + +#if (RTL8822B_SUPPORT == 1) + #include "halrf/rtl8822b/halrf_iqk_8822b.h" +#endif + +#if (RTL8821C_SUPPORT == 1) + #include "halrf/rtl8821c/halrf_iqk_8821c.h" +#endif + +#include "halrf/halrf_powertracking_ce.h" + + +enum spur_cal_method { + PLL_RESET, + AFE_PHASE_SEL +}; + +enum pwrtrack_method { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE, + MIX_2G_TSSI_5G_MODE, + MIX_5G_TSSI_2G_MODE +}; + +typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8); +typedef void(*func_iqk)(void *, u8, u8, u8); +typedef void (*func_lck)(void *); +typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void(*func_swing_xtal)(void *, s8 **, s8 **); +typedef void(*func_set_xtal)(void *); + +struct _TXPWRTRACK_CFG { + u8 swing_table_size_cck; + u8 swing_table_size_ofdm; + u8 threshold_iqk; + u8 threshold_dpk; + u8 average_thermal_num; + u8 rf_path_count; + u32 thermal_reg_addr; + func_set_pwr odm_tx_pwr_track_set_pwr; + func_iqk do_iqk; + func_lck phy_lc_calibrate; + func_swing get_delta_swing_table; + func_swing8814only get_delta_swing_table8814only; + func_swing_xtal get_delta_swing_xtal_table; + func_set_xtal odm_txxtaltrack_set_xtal; +}; + +void +configure_txpower_track( + void *p_dm_void, + struct _TXPWRTRACK_CFG *p_config +); + + +void +odm_clear_txpowertracking_state( + void *p_dm_void +); + +void +odm_txpowertracking_callback_thermal_meter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + void *p_dm_void +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *p_dm_odm +#else + struct _ADAPTER *adapter +#endif +); + + + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +void +odm_reset_iqk_result( + void *p_dm_void +); +u8 +odm_get_right_chnl_place_for_iqk( + u8 chnl +); + +void phydm_rf_init(void *p_dm_void); +void phydm_rf_watchdog(void *p_dm_void); + +#endif /* #ifndef __HAL_PHY_RF_H__ */ diff --git a/hal/phydm/halrf/halphyrf_win.c b/hal/phydm/halrf/halphyrf_win.c new file mode 100644 index 0000000..980e0a8 --- /dev/null +++ b/hal/phydm/halrf/halphyrf_win.c @@ -0,0 +1,827 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \ + do {\ + for (_offset = 0; _offset < _size; _offset++) { \ + \ + if (_delta_thermal < thermal_threshold[_direction][_offset]) { \ + \ + if (_offset != 0)\ + _offset--;\ + break;\ + } \ + } \ + if (_offset >= _size)\ + _offset = _size-1;\ + } while (0) + +void configure_txpower_track( + struct PHY_DM_STRUCT *p_dm_odm, + struct _TXPWRTRACK_CFG *p_config +) +{ +#if RTL8192E_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8192E) + configure_txpower_track_8192e(p_config); +#endif +#if RTL8821A_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8821) + configure_txpower_track_8821a(p_config); +#endif +#if RTL8812A_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8812) + configure_txpower_track_8812a(p_config); +#endif +#if RTL8188E_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8188E) + configure_txpower_track_8188e(p_config); +#endif + +#if RTL8188F_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8188F) + configure_txpower_track_8188f(p_config); +#endif + +#if RTL8723B_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8723B) + configure_txpower_track_8723b(p_config); +#endif + +#if RTL8814A_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8814A) + configure_txpower_track_8814a(p_config); +#endif + +#if RTL8703B_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8703B) + configure_txpower_track_8703b(p_config); +#endif + +#if RTL8822B_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8822B) + configure_txpower_track_8822b(p_config); +#endif + +#if RTL8723D_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8723D) + configure_txpower_track_8723d(p_config); +#endif + +/* JJ ADD 20161014 */ +#if RTL8710B_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8710B) + configure_txpower_track_8710b(p_config); +#endif + +#if RTL8821C_SUPPORT + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + configure_txpower_track_8821c(p_config); +#endif + +} + +/* ********************************************************************** + * <20121113, Kordan> This function should be called when tx_agc changed. + * Otherwise the previous compensation is gone, because we record the + * delta of temperature between two TxPowerTracking watch dogs. + * + * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still + * need to call this function. + * ********************************************************************** */ +void +odm_clear_txpowertracking_state( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); + u8 p = 0; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index; + p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index; + p_rf_calibrate_info->CCK_index = 0; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) { + p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index; + + p_rf_calibrate_info->power_index_offset[p] = 0; + p_rf_calibrate_info->delta_power_index[p] = 0; + p_rf_calibrate_info->delta_power_index_last[p] = 0; + + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/ + p_rf_calibrate_info->remnant_ofdm_swing_idx[p] = 0; + p_rf_calibrate_info->kfree_offset[p] = 0; + } + + p_rf_calibrate_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/ + p_rf_calibrate_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/ + p_rf_calibrate_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/ + p_rf_calibrate_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/ + p_rf_calibrate_info->remnant_cck_swing_idx = 0; + p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter; + + p_rf_calibrate_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */ + p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */ + +} + +void +odm_txpowertracking_callback_thermal_meter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + struct PHY_DM_STRUCT *p_dm_odm +#else + struct _ADAPTER *adapter +#endif +) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; +#endif +#endif + + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; + s8 diff_DPK[4] = {0}; + u8 thermal_value_avg_count = 0; + u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4; + + u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ + u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(p_hal_data->current_channel) */ + u8 power_tracking_type = p_hal_data->RfPowerTrackingType; + u8 xtal_offset_eanble = 0; + s8 thermal_value_temp = 0; + + struct _TXPWRTRACK_CFG c; + + /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ + u8 *delta_swing_table_idx_tup_a = NULL; + u8 *delta_swing_table_idx_tdown_a = NULL; + u8 *delta_swing_table_idx_tup_b = NULL; + u8 *delta_swing_table_idx_tdown_b = NULL; + /*for 8814 add by Yu Chen*/ + u8 *delta_swing_table_idx_tup_c = NULL; + u8 *delta_swing_table_idx_tdown_c = NULL; + u8 *delta_swing_table_idx_tup_d = NULL; + u8 *delta_swing_table_idx_tdown_d = NULL; + /*for Xtal Offset by James.Tung*/ + s8 *delta_swing_table_xtal_up = NULL; + s8 *delta_swing_table_xtal_down = NULL; + + /* 4 2. Initilization ( 7 steps in total ) */ + + configure_txpower_track(p_dm_odm, &c); + + (*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, + (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b); + + if (p_dm_odm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/ + (*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c, + (u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d); + /* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/ + (*c.get_delta_swing_xtal_table)(p_dm_odm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down); + + + p_rf_calibrate_info->txpowertracking_callback_cnt++; /*cosa add for debug*/ + p_rf_calibrate_info->is_txpowertracking_init = true; + + /*p_rf_calibrate_info->txpowertrack_control = p_hal_data->txpowertrack_control; + We should keep updating the control variable according to HalData. + rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + p_rf_calibrate_info->rega24 = 0x090e1317; +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (*(p_dm_odm->p_mp_mode) == true) + p_rf_calibrate_info->rega24 = 0x090e1317; +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("===>odm_txpowertracking_callback_thermal_meter\n p_rf_calibrate_info->bb_swing_idx_cck_base: %d, p_rf_calibrate_info->bb_swing_idx_ofdm_base[A]: %d, p_rf_calibrate_info->default_ofdm_index: %d\n", + p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A], p_rf_calibrate_info->default_ofdm_index)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("p_rf_calibrate_info->txpowertrack_control=%d, p_hal_data->eeprom_thermal_meter %d\n", p_rf_calibrate_info->txpowertrack_control, p_hal_data->eeprom_thermal_meter)); + thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + + thermal_value_temp = thermal_value + phydm_get_thermal_offset(p_dm_odm); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("thermal_value_temp(%d) = thermal_value(%d) + power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(p_dm_odm))); + + if (thermal_value_temp > 63) + thermal_value = 63; + else if (thermal_value_temp < 0) + thermal_value = 0; + else + thermal_value = thermal_value_temp; + + /*add log by zhao he, check c80/c94/c14/ca0 value*/ + if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4)); + } + + /* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4)); + } + + if (!p_rf_calibrate_info->txpowertrack_control) + return; + + if (p_hal_data->eeprom_thermal_meter == 0xff) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no pg, p_hal_data->eeprom_thermal_meter = 0x%x\n", p_hal_data->eeprom_thermal_meter)); + return; + } + + /*4 3. Initialize ThermalValues of rf_calibrate_info*/ + + if (p_rf_calibrate_info->is_reloadtxpowerindex) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n")); + + /*4 4. Calculate average thermal meter*/ + + p_rf_calibrate_info->thermal_value_avg[p_rf_calibrate_info->thermal_value_avg_index] = thermal_value; + p_rf_calibrate_info->thermal_value_avg_index++; + if (p_rf_calibrate_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ + p_rf_calibrate_info->thermal_value_avg_index = 0; + + for (i = 0; i < c.average_thermal_num; i++) { + if (p_rf_calibrate_info->thermal_value_avg[i]) { + thermal_value_avg += p_rf_calibrate_info->thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */ + thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); + p_rf_calibrate_info->thermal_value_delta = thermal_value - p_hal_data->eeprom_thermal_meter; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + } + + /* 4 5. Calculate delta, delta_LCK, delta_IQK. */ + + /* "delta" here is used to determine whether thermal value changes or not. */ + delta = (thermal_value > p_rf_calibrate_info->thermal_value) ? (thermal_value - p_rf_calibrate_info->thermal_value) : (p_rf_calibrate_info->thermal_value - thermal_value); + delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value); + delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value); + + if (p_rf_calibrate_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/ + p_rf_calibrate_info->thermal_value_iqk = thermal_value; + delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use thermal_value for IQK\n")); + } + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + diff_DPK[p] = (s8)thermal_value - (s8)p_rf_calibrate_info->dpk_thermal[p]; + + /*4 6. If necessary, do LCK.*/ + + if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/ + if (p_rf_calibrate_info->thermal_value_lck == 0xff) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); + p_rf_calibrate_info->thermal_value_lck = thermal_value; + + /*Use RTLCK, so close power tracking driver LCK*/ + if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) { + if (c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(p_dm_odm); + } + + delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value); + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); + + /* Wait sacn to do LCK by RF Jenyu*/ + if (*p_dm_odm->p_is_scan_in_process == false) { + /* Delta temperature is equal to or larger than 20 centigrade.*/ + if (delta_LCK >= c.threshold_iqk) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk)); + p_rf_calibrate_info->thermal_value_lck = thermal_value; + + /*Use RTLCK, so close power tracking driver LCK*/ + if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) { + if (c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(p_dm_odm); + } + } + } + } + + /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ + + if (delta > 0 && p_rf_calibrate_info->txpowertrack_control) { + /* "delta" here is used to record the absolute value of differrence. */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + delta = thermal_value > p_hal_data->eeprom_thermal_meter ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value); +#else + delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value); +#endif + if (delta >= TXPWR_TRACK_TABLE_SIZE) + delta = TXPWR_TRACK_TABLE_SIZE - 1; + + /*4 7.1 The Final Power index = BaseIndex + power_index_offset*/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (thermal_value > p_hal_data->eeprom_thermal_meter) { +#else + if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) { +#endif + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/ + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta])); + + p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta])); + + p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta])); + + p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta])); + + p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + } + } + /* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + /*Save xtal_offset from Xtal table*/ + p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta])); + p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_up[delta]; + + if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset) + xtal_offset_eanble = 0; + else + xtal_offset_eanble = 1; + } + + } else { + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/ + + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta])); + p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta])); + p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta])); + p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta])); + p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + } + } + /* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + /*Save xtal_offset from Xtal table*/ + p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta])); + p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_down[delta]; + + if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset) + xtal_offset_eanble = 0; + else + xtal_offset_eanble = 1; + } + + } + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p)); + + if (p_rf_calibrate_info->delta_power_index[p] == p_rf_calibrate_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/ + p_rf_calibrate_info->power_index_offset[p] = 0; + else + p_rf_calibrate_info->power_index_offset[p] = p_rf_calibrate_info->delta_power_index[p] - p_rf_calibrate_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, p_rf_calibrate_info->power_index_offset[p], p_rf_calibrate_info->delta_power_index[p], p_rf_calibrate_info->delta_power_index_last[p])); + + p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] + p_rf_calibrate_info->power_index_offset[p]; + p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_rf_calibrate_info->power_index_offset[p]; + + p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->CCK_index; + p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->OFDM_index[p]; + + /*************Print BB Swing base and index Offset*************/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->power_index_offset[p])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p], p_rf_calibrate_info->power_index_offset[p])); + + /*4 7.1 Handle boundary conditions of index.*/ + + if (p_rf_calibrate_info->OFDM_index[p] > c.swing_table_size_ofdm - 1) + p_rf_calibrate_info->OFDM_index[p] = c.swing_table_size_ofdm - 1; + else if (p_rf_calibrate_info->OFDM_index[p] <= OFDM_min_index) + p_rf_calibrate_info->OFDM_index[p] = OFDM_min_index; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n========================================================================================================\n")); + + if (p_rf_calibrate_info->CCK_index > c.swing_table_size_cck - 1) + p_rf_calibrate_info->CCK_index = c.swing_table_size_cck - 1; + else if (p_rf_calibrate_info->CCK_index <= 0) + p_rf_calibrate_info->CCK_index = 0; + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, p_rf_calibrate_info->thermal_value: %d\n", + p_rf_calibrate_info->txpowertrack_control, thermal_value, p_rf_calibrate_info->thermal_value)); + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + p_rf_calibrate_info->power_index_offset[p] = 0; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", + p_rf_calibrate_info->CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base)); /*Print Swing base & current*/ + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n", + p_rf_calibrate_info->OFDM_index[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p])); + } + + if ((p_dm_odm->support_ic_type & ODM_RTL8814A)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("power_tracking_type=%d\n", power_tracking_type)); + + if (power_tracking_type == 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + } else if (power_tracking_type == 1) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_2G_TSSI_5G_MODE, p, 0); + } else if (power_tracking_type == 2) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_5G_TSSI_2G_MODE, p, 0); + } else if (power_tracking_type == 3) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0); + } + p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + + } else if ((p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_A] != 0 || + p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_B] != 0 || + p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_C] != 0 || + p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_D] != 0) && + p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) { + /* 4 7.2 Configure the Swing Table to adjust Tx Power. */ + + p_rf_calibrate_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/ + /* */ + /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */ + /* to increase TX power. Otherwise, EVM will be bad. */ + /* */ + /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ + if (thermal_value > p_rf_calibrate_info->thermal_value) { + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value)); + } + } else if (thermal_value < p_rf_calibrate_info->thermal_value) { /*Low temperature*/ + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value)); + } + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (thermal_value > p_hal_data->eeprom_thermal_meter) +#else + if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) +#endif + { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 || + p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A || + p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B || + p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel); + } + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 || + p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A || + p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B || + p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, indexforchannel); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel); + } + + } + + p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/ + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->bb_swing_idx_ofdm[p]; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("p_rf_calibrate_info->thermal_value = %d thermal_value= %d\n", p_rf_calibrate_info->thermal_value, thermal_value)); + + p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + + } + + + if (p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + + if (xtal_offset_eanble != 0 && p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n")); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (thermal_value > p_hal_data->eeprom_thermal_meter) { +#else + if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) { +#endif + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + (*c.odm_txxtaltrack_set_xtal)(p_dm_odm); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + (*c.odm_txxtaltrack_set_xtal)(p_dm_odm); + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n")); + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + /* Wait sacn to do IQK by RF Jenyu*/ + if (*p_dm_odm->p_is_scan_in_process == false) { + if (!IS_HARDWARE_TYPE_8723B(adapter)) { + /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ + if (delta_IQK >= c.threshold_iqk) { + p_rf_calibrate_info->thermal_value_iqk = thermal_value; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk)); + if (!p_rf_calibrate_info->is_iqk_in_progress) + (*c.do_iqk)(p_dm_odm, delta_IQK, thermal_value, 8); + } + } + } + if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_A] != 0) { + if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) { + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk)); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk); + + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } else { + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } + } + if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_B] != 0) { + if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) { + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk)); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk); + + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } else { + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } + } + +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===odm_txpowertracking_callback_thermal_meter\n")); + + p_rf_calibrate_info->tx_powercount = 0; +} + + + +/* 3============================================================ + * 3 IQ Calibration + * 3============================================================ */ + +void +odm_reset_iqk_result( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + return; +} +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +u8 odm_get_right_chnl_place_for_iqk(u8 chnl) +{ + u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165 + }; + u8 place = chnl; + + + if (chnl > 14) { + for (place = 14; place < sizeof(channel_all); place++) { + if (channel_all[place] == chnl) + return place - 13; + } + } + return 0; + +} +#endif + +void +odm_iq_calibrate( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + + RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("=>%s\n" , __FUNCTION__)); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (*p_dm_odm->p_is_fcs_mode_enable) + return; +#endif + + if (p_dm_odm->is_linked) { + RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("interval=%d ch=%d prech=%d scan=%s\n", p_dm_odm->linked_interval, + *p_dm_odm->p_channel, p_dm_odm->pre_channel, *p_dm_odm->p_is_scan_in_process == TRUE ? "TRUE":"FALSE")); + + if (*p_dm_odm->p_channel != p_dm_odm->pre_channel) { + p_dm_odm->pre_channel = *p_dm_odm->p_channel; + p_dm_odm->linked_interval = 0; + } + + if ((p_dm_odm->linked_interval < 3) && (!*p_dm_odm->p_is_scan_in_process)) + p_dm_odm->linked_interval++; + + if (p_dm_odm->linked_interval == 2) + PHY_IQCalibrate(adapter, false); + } else + p_dm_odm->linked_interval = 0; + + RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, p_dm_odm->linked_interval, + *p_dm_odm->p_channel, p_dm_odm->pre_channel, *p_dm_odm->p_is_scan_in_process == TRUE?"TRUE":"FALSE")); +} + +void phydm_rf_init(struct PHY_DM_STRUCT *p_dm_odm) +{ + + odm_txpowertracking_init(p_dm_odm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + odm_clear_txpowertracking_state(p_dm_odm); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8814A_SUPPORT == 1) + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + phy_iq_calibrate_8814a_init(p_dm_odm); +#endif +#endif + +} + +void phydm_rf_watchdog(struct PHY_DM_STRUCT *p_dm_odm) +{ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct _ADAPTER *adapter = p_dm_odm->adapter; + + odm_txpowertracking_check(p_dm_odm); + + if(!adapter->MgntInfo.IQKBeforeConnection) { + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + odm_iq_calibrate(p_dm_odm); + } +#endif +} diff --git a/hal/phydm/halrf/halphyrf_win.h b/hal/phydm/halrf/halphyrf_win.h new file mode 100644 index 0000000..e11433a --- /dev/null +++ b/hal/phydm/halrf/halphyrf_win.h @@ -0,0 +1,118 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_H__ +#define __HAL_PHY_RF_H__ + +#if (RTL8814A_SUPPORT == 1) + #include "halrf/rtl8814a/halrf_iqk_8814a.h" +#endif + +#if (RTL8822B_SUPPORT == 1) + #include "halrf/rtl8822b/halrf_iqk_8822b.h" + #include "../mac/Halmac_type.h" +#endif +#include "halrf/halrf_powertracking_win.h" +#include "halrf/halrf_kfree.h" +#if (RTL8821C_SUPPORT == 1) + #include "halrf/rtl8821c/halrf_iqk_8821c.h" +#endif + +enum spur_cal_method { + PLL_RESET, + AFE_PHASE_SEL +}; + +enum pwrtrack_method { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE, + MIX_2G_TSSI_5G_MODE, + MIX_5G_TSSI_2G_MODE +}; + +typedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8); +typedef void(*func_iqk)(void *, u8, u8, u8); +typedef void(*func_lck)(void *); +typedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_swing_xtal)(void *, s8 **, s8 **); +typedef void (*func_set_xtal)(void *); +typedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **); + +struct _TXPWRTRACK_CFG { + u8 swing_table_size_cck; + u8 swing_table_size_ofdm; + u8 threshold_iqk; + u8 threshold_dpk; + u8 average_thermal_num; + u8 rf_path_count; + u32 thermal_reg_addr; + func_set_pwr odm_tx_pwr_track_set_pwr; + func_iqk do_iqk; + func_lck phy_lc_calibrate; + func_swing get_delta_swing_table; + func_swing8814only get_delta_swing_table8814only; + func_swing_xtal get_delta_swing_xtal_table; + func_set_xtal odm_txxtaltrack_set_xtal; + func_all_swing get_delta_all_swing_table; +}; + +void +configure_txpower_track( + struct PHY_DM_STRUCT *p_dm_odm, + struct _TXPWRTRACK_CFG *p_config +); + + +void +odm_clear_txpowertracking_state( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +odm_txpowertracking_callback_thermal_meter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + struct PHY_DM_STRUCT *p_dm_odm +#else + struct _ADAPTER *adapter +#endif +); + + + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +void +odm_reset_iqk_result( + struct PHY_DM_STRUCT *p_dm_odm +); +u8 +odm_get_right_chnl_place_for_iqk( + u8 chnl +); + +void odm_iq_calibrate(struct PHY_DM_STRUCT *p_dm_odm); +void phydm_rf_init(struct PHY_DM_STRUCT *p_dm_odm); +void phydm_rf_watchdog(struct PHY_DM_STRUCT *p_dm_odm); + +#endif /* #ifndef __HAL_PHY_RF_H__ */ diff --git a/hal/phydm/halrf/halrf.c b/hal/phydm/halrf/halrf.c new file mode 100644 index 0000000..1e33d9d --- /dev/null +++ b/hal/phydm/halrf/halrf.c @@ -0,0 +1,291 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void phydm_rf_basic_profile( + void *p_dm_void, + u32 *_used, + char *output, + u32 *_out_len +) +{ +#if CONFIG_PHYDM_DEBUG_FUNCTION + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + /* HAL RF version List */ + PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% HAL RF version %")); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Power Tracking", HALRF_POWRTRACKING_VER)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "IQK", HALRF_IQK_VER)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "LCK", HALRF_LCK_VER)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "DPK", HALRF_DPK_VER)); + + *_used = used; + *_out_len = out_len; +#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +} + +void +halrf_support_ability_debug( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + u32 dm_value[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]); + } + } + + PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); + if (dm_value[0] == 100) { + PHYDM_SNPRINTF((output + used, out_len - used, "[RF Supportability]\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))Power Tracking\n", ((p_rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))IQK\n", ((p_rf->rf_supportability & HAL_RF_IQK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))LCK\n", ((p_rf->rf_supportability & HAL_RF_LCK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))DPK\n", ((p_rf->rf_supportability & HAL_RF_DPK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + } + else { + + if (dm_value[1] == 1) { /* enable */ + p_rf->rf_supportability |= BIT(dm_value[0]) ; + } else if (dm_value[1] == 2) /* disable */ + p_rf->rf_supportability &= ~(BIT(dm_value[0])) ; + else { + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); + } + } + PHYDM_SNPRINTF((output + used, out_len - used, "Curr-RF_supportability = 0x%x\n", p_rf->rf_supportability)); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); +} + +void +halrf_cmn_info_set( + void *p_dm_void, + u32 cmn_info, + u64 value +) +{ + /* */ + /* This init variable may be changed in run time. */ + /* */ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + + switch (cmn_info) { + + case HALRF_CMNINFO_ABILITY: + p_rf->rf_supportability = (u32)value; + break; + + case ODM_CMNINFO_DPK_EN: + p_rf->dpk_en = (u1Byte)value; + break; + + default: + /* do nothing */ + break; + } +} + +u64 +halrf_cmn_info_get( + void *p_dm_void, + u32 cmn_info +) +{ + /* */ + /* This init variable may be changed in run time. */ + /* */ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + u64 return_value = 0; + + switch (cmn_info) { + + case HALRF_CMNINFO_ABILITY: + return_value = (u32)p_rf->rf_supportability; + break; + default: + /* do nothing */ + break; + } + + return return_value; +} + +void +halrf_supportability_init_mp( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + + switch (p_dm_odm->support_ic_type) { + + case ODM_RTL8814B: + #if (RTL8814B_SUPPORT == 1) + p_rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; + #endif + break; + #if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + p_rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; + break; + #endif + + #if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + p_rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; + break; + #endif + + default: + p_rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; + break; + + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\n", p_dm_odm->support_ic_type, p_rf->rf_supportability)); +} + +void +halrf_supportability_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + + switch (p_dm_odm->support_ic_type) { + + case ODM_RTL8814B: + #if (RTL8814B_SUPPORT == 1) + p_rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; + #endif + break; + #if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + p_rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; + break; + #endif + + #if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + p_rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; + break; + #endif + + default: + p_rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; + break; + + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IC = ((0x%x)), RF_Supportability Init = ((0x%x))\n", p_dm_odm->support_ic_type, p_rf->rf_supportability)); +} + +void +halrf_watchdog( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + phydm_rf_watchdog(p_dm_odm); +} + +void +halrf_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("HALRF_Init\n")); + + if (*(p_dm_odm->p_mp_mode) == true) + halrf_supportability_init_mp(p_dm_odm); + else + halrf_supportability_init(p_dm_odm); +} + + + + diff --git a/hal/phydm/halrf/halrf.h b/hal/phydm/halrf/halrf.h new file mode 100644 index 0000000..cc28aff --- /dev/null +++ b/hal/phydm/halrf/halrf.h @@ -0,0 +1,125 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef _HALRF_H__ +#define _HALRF_H__ + +/*============================================================*/ +/*include files*/ +/*============================================================*/ + + + +/*============================================================*/ +/*Definition */ +/*============================================================*/ + + +#if 0/*(RTL8821C_SUPPORT == 1)*/ +#define HALRF_IQK_VER IQK_VERSION +#define HALRF_LCK_VER LCK_VERSION +#define HALRF_DPK_VER DPK_VERSION +#else +#define HALRF_IQK_VER "1.0" +#define HALRF_LCK_VER "1.0" +#define HALRF_DPK_VER "1.0" +#endif + +/*============================================================*/ +/* enumeration */ +/*============================================================*/ +enum halrf_ability_e { + + HAL_RF_TX_PWR_TRACK = BIT(0), + HAL_RF_IQK = BIT(1), + HAL_RF_LCK = BIT(2), + HAL_RF_DPK = BIT(3) +}; + +enum halrf_cmninfo_e { + + HALRF_CMNINFO_ABILITY = 0, + HALRF_CMNINFO_DPK_EN = 1, + HALRF_CMNINFO_tmp +}; + +/*============================================================*/ +/* structure */ +/*============================================================*/ + +struct _hal_rf_ { + u32 rf_supportability; + u8 dpk_en; /*Enable Function DPK OFF/ON = 0/1*/ + boolean dpk_done; + +}; + +/*============================================================*/ +/* function prototype */ +/*============================================================*/ + +void phydm_rf_basic_profile( + void *p_dm_void, + u32 *_used, + char *output, + u32 *_out_len +); + +void +halrf_support_ability_debug( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len +); + +void +halrf_cmn_info_set( + void *p_dm_void, + u32 cmn_info, + u64 value +); + +u64 +halrf_cmn_info_get( + void *p_dm_void, + u32 cmn_info +); + +void +halrf_watchdog( + void *p_dm_void +); + +void +halrf_supportability_init( + void *p_dm_void +); + +void +halrf_init( + void *p_dm_void +); + + + +#endif diff --git a/hal/phydm/halrf/halrf_features.h b/hal/phydm/halrf/halrf_features.h new file mode 100644 index 0000000..f8edbfd --- /dev/null +++ b/hal/phydm/halrf/halrf_features.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HALRF_FEATURES_H__ +#define __HALRF_FEATURES + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + #define CONFIG_HALRF_POWERTRACKING 1 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + #define CONFIG_HALRF_POWERTRACKING 1 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + #define CONFIG_HALRF_POWERTRACKING 1 + +#endif + +#endif diff --git a/hal/phydm/halrf/halrf_iqk.h b/hal/phydm/halrf/halrf_iqk.h new file mode 100644 index 0000000..006b554 --- /dev/null +++ b/hal/phydm/halrf/halrf_iqk.h @@ -0,0 +1,65 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMIQK_H__ +#define __PHYDMIQK_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define LOK_delay 1 +#define WBIQK_delay 10 +#define TX_IQK 0 +#define RX_IQK 1 +#define TXIQK 0 +#define RXIQK1 1 +#define RXIQK2 2 +#define kcount_limit_80m 2 +#define kcount_limit_others 4 +#define rxiqk_gs_limit 4 + +#define NUM 4 +/*---------------------------End Define Parameters-------------------------------*/ + +struct _IQK_INFORMATION { + boolean LOK_fail[NUM]; + boolean IQK_fail[2][NUM]; + u32 iqc_matrix[2][NUM]; + u8 iqk_times; + u32 rf_reg18; + u32 lna_idx; + u8 rxiqk_step; + u8 tmp1bcc; + u8 kcount; + + u32 iqk_channel[2]; + boolean IQK_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */ + u32 IQK_CFIR_real[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ + u32 IQK_CFIR_imag[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ + u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */ + u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */ + u8 RXIQK_fail_code[2][4]; /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */ + u32 LOK_IDAC[2][4]; /*channel / path*/ + u16 RXIQK_AGC[2][4]; /*channel / path*/ + u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/ + u32 tmp_GNTWL; + boolean is_BTG; + boolean isbnd; +}; + +#endif diff --git a/hal/phydm/halrf/halrf_kfree.c b/hal/phydm/halrf/halrf_kfree.c new file mode 100644 index 0000000..1e67dc0 --- /dev/null +++ b/hal/phydm/halrf/halrf_kfree.c @@ -0,0 +1,716 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/*============================================================*/ +/*include files*/ +/*============================================================*/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +/* Add for KFree Feature Requested by RF David.*/ +/*This is a phydm API*/ + +void +phydm_set_kfree_to_rf_8814a( + void *p_dm_void, + u8 e_rf_path, + u8 data +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + boolean is_odd; + + if ((data % 2) != 0) { /*odd->positive*/ + data = data - 1; + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 1); + is_odd = true; + } else { /*even->negative*/ + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 0); + is_odd = false; + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", is_odd)); + switch (data) { + case 0: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 0; + break; + case 2: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 0; + break; + case 4: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 1; + break; + case 6: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 1; + break; + case 8: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 2; + break; + case 10: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 2; + break; + case 12: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 3; + break; + case 14: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 3; + break; + case 16: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 4; + break; + case 18: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 4; + break; + case 20: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 5); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 5; + break; + + default: + break; + } + + if (is_odd == false) { + /*that means Kfree offset is negative, we need to record it.*/ + p_rf_calibrate_info->kfree_offset[e_rf_path] = (-1) * p_rf_calibrate_info->kfree_offset[e_rf_path]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): kfree_offset = %d\n", p_rf_calibrate_info->kfree_offset[e_rf_path])); + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): kfree_offset = %d\n", p_rf_calibrate_info->kfree_offset[e_rf_path])); + +} + + + +// +// +// +void +phydm_get_thermal_trim_offset_8821c( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + + u8 pg_therm = 0xff; + + odm_efuse_one_byte_read(p_dm_odm, PPG_THERMAL_OFFSET_8821C, &pg_therm, false); + + if (pg_therm != 0xff) { + pg_therm = pg_therm & 0x1f; + if ((pg_therm & BIT0) == 0) + p_power_trim_info->thermal = (-1 * (pg_therm >> 1)); + else + p_power_trim_info->thermal = (pg_therm >> 1); + + p_power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8821c thermal trim flag:0x%02x\n", p_power_trim_info->flag)); + + if (p_power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8821c thermal:%d\n", p_power_trim_info->thermal)); +} + + + +void +phydm_get_power_trim_offset_8821c( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + + u8 pg_power = 0xff, i; + + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_2G_TXAB_OFFSET_8821C, &pg_power, false); + + if (pg_power != 0xff) { + p_power_trim_info->bb_gain[0][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C, &pg_power, false); + p_power_trim_info->bb_gain[1][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C, &pg_power, false); + p_power_trim_info->bb_gain[2][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C, &pg_power, false); + p_power_trim_info->bb_gain[3][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C, &pg_power, false); + p_power_trim_info->bb_gain[4][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C, &pg_power, false); + p_power_trim_info->bb_gain[5][0] = pg_power; + p_power_trim_info->flag = p_power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G | KFREE_FLAG_ON_5G; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8821c power trim flag:0x%02x\n", p_power_trim_info->flag)); + + if (p_power_trim_info->flag & KFREE_FLAG_ON) { + for (i = 0; i < 6; i++) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8821c power_trim_data->bb_gain[%d][0]=0x%X\n", i, p_power_trim_info->bb_gain[i][0])); + } +} + + + +void +phydm_set_kfree_to_rf_8821c( + void *p_dm_void, + u8 e_rf_path, + boolean wlg_btg, + u8 data +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + boolean is_odd; + u8 wlg, btg; + + odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(0), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(5), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(6), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, BIT(6), 1); + + if (wlg_btg == true) { + wlg = data & 0xf; + btg = (data & 0xf0) >> 4; + + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(19), (wlg & BIT(0))); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (wlg >> 1)); + + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, BIT(19), (btg & BIT(0))); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (btg >> 1)); + } else { + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1)); + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, + ("[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n", + odm_get_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), + odm_get_rf_reg(p_dm_odm, e_rf_path, 0x65, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))) + )); +} + + + +void +phydm_get_thermal_trim_offset_8822b( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + + u8 pg_therm = 0xff, i; + +#if 0 + u32 thermal_trim_enable = 0xff; + + odm_efuse_logical_map_read(p_dm_odm, 1, 0xc8, &thermal_trim_enable); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b 0xc8:0x%2x\n", thermal_trim_enable)); + + thermal_trim_enable = (thermal_trim_enable & BIT(5)) >> 5; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b thermal trim Enable:%d\n", thermal_trim_enable)); + + if ((p_rf_calibrate_info->reg_rf_kfree_enable == 0 && thermal_trim_enable == 1) || + p_rf_calibrate_info->reg_rf_kfree_enable == 1) { +#endif + + odm_efuse_one_byte_read(p_dm_odm, PPG_THERMAL_OFFSET, &pg_therm, false); + + if (pg_therm != 0xff) { + pg_therm = pg_therm & 0x1f; + if ((pg_therm & BIT0) == 0) + p_power_trim_info->thermal = (-1 * (pg_therm >> 1)); + else + p_power_trim_info->thermal = (pg_therm >> 1); + + p_power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b thermal trim flag:0x%02x\n", p_power_trim_info->flag)); + + if (p_power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b thermal:%d\n", p_power_trim_info->thermal)); +#if 0 + } else + return; +#endif + +} + + + +void +phydm_get_power_trim_offset_8822b( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + u8 pg_power = 0xff, i, j; + +#if 0 + u32 power_trim_enable = 0xff; + + odm_efuse_logical_map_read(p_dm_odm, 1, 0xc8, &power_trim_enable); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b 0xc8:0x%2x\n", power_trim_enable)); + + power_trim_enable = (power_trim_enable & BIT(4)) >> 4; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b power trim Enable:%d\n", power_trim_enable)); + + if ((p_rf_calibrate_info->reg_rf_kfree_enable == 0 && power_trim_enable == 1) || + p_rf_calibrate_info->reg_rf_kfree_enable == 1) { +#endif + + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false); + + if (pg_power != 0xff) { + /*Path A*/ + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false); + p_power_trim_info->bb_gain[0][0] = (pg_power & 0xf); + + /*Path B*/ + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false); + p_power_trim_info->bb_gain[0][1] = ((pg_power & 0xf0) >> 4); + + p_power_trim_info->flag |= KFREE_FLAG_ON_2G; + p_power_trim_info->flag |= KFREE_FLAG_ON; + } + + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL1_TXA_OFFSET, &pg_power, false); + + if (pg_power != 0xff) { + /*Path A*/ + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL1_TXA_OFFSET, &pg_power, false); + p_power_trim_info->bb_gain[1][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL2_TXA_OFFSET, &pg_power, false); + p_power_trim_info->bb_gain[2][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM1_TXA_OFFSET, &pg_power, false); + p_power_trim_info->bb_gain[3][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM2_TXA_OFFSET, &pg_power, false); + p_power_trim_info->bb_gain[4][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GH1_TXA_OFFSET, &pg_power, false); + p_power_trim_info->bb_gain[5][0] = pg_power; + + /*Path B*/ + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL1_TXB_OFFSET, &pg_power, false); + p_power_trim_info->bb_gain[1][1] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL2_TXB_OFFSET, &pg_power, false); + p_power_trim_info->bb_gain[2][1] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM1_TXB_OFFSET, &pg_power, false); + p_power_trim_info->bb_gain[3][1] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM2_TXB_OFFSET, &pg_power, false); + p_power_trim_info->bb_gain[4][1] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GH1_TXB_OFFSET, &pg_power, false); + p_power_trim_info->bb_gain[5][1] = pg_power; + + p_power_trim_info->flag |= KFREE_FLAG_ON_5G; + p_power_trim_info->flag |= KFREE_FLAG_ON; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b power trim flag:0x%02x\n", p_power_trim_info->flag)); + + if (p_power_trim_info->flag & KFREE_FLAG_ON) { + for (i = 0; i < 6; i++) { + for (j = 0; j < 2; j++) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b power_trim_data->bb_gain[%d][%d]=0x%X\n", i, j, p_power_trim_info->bb_gain[i][j])); + } + } +#if 0 + } else + return; +#endif +} + + + +void +phydm_set_pa_bias_to_rf_8822b( + void *p_dm_void, + u8 e_rf_path, + s8 tx_pa_bias +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + tx_pa_bias = tx_pa_bias + (u8)odm_get_rf_reg(p_dm_odm, e_rf_path, 0x51, (BIT(6) | BIT(5) | BIT(4) | BIT(3))); + + if (tx_pa_bias < 0) + tx_pa_bias = 0; + else if (tx_pa_bias > 7) + tx_pa_bias = 7; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b 2g tx pa bias=0x%X rf 0x51=0x%X path=%d\n", tx_pa_bias, + odm_get_rf_reg(p_dm_odm, e_rf_path, 0x51, (BIT(6) | BIT(5) | BIT(4) | BIT(3))), e_rf_path)); + + odm_set_rf_reg(p_dm_odm, e_rf_path, 0xef, BIT(10), 0x1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x33, RFREGOFFSETMASK, 0x0); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9)), tx_pa_bias); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x33, BIT(0), 0x1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9)), tx_pa_bias); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x33, BIT(1), 0x1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9)), tx_pa_bias); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x33, (BIT(1) | BIT(0)), 0x3); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9)), tx_pa_bias); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0xef, BIT(10), 0x0); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b 2g tx pa bias rf_0x3f(0x%X) path=%d\n", + odm_get_rf_reg(p_dm_odm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9))), e_rf_path)); + +} + + + +void +phydm_get_pa_bias_offset_8822b( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + + u8 pg_pa_bias = 0xff, e_rf_path = 0; + s8 tx_pa_bias[2] = {0}; + + odm_efuse_one_byte_read(p_dm_odm, PPG_PA_BIAS_2G_TXA_OFFSET, &pg_pa_bias, false); + + if (pg_pa_bias != 0xff) { + /*paht a*/ + odm_efuse_one_byte_read(p_dm_odm, PPG_PA_BIAS_2G_TXA_OFFSET, &pg_pa_bias, false); + pg_pa_bias = pg_pa_bias & 0xf; + + if ((pg_pa_bias & BIT0) == 0) + tx_pa_bias[0] = (-1 * (pg_pa_bias >> 1)); + else + tx_pa_bias[0] = (pg_pa_bias >> 1); + + /*paht b*/ + odm_efuse_one_byte_read(p_dm_odm, PPG_PA_BIAS_2G_TXB_OFFSET, &pg_pa_bias, false); + pg_pa_bias = pg_pa_bias & 0xf; + + if ((pg_pa_bias & BIT0) == 0) + tx_pa_bias[1] = (-1 * (pg_pa_bias >> 1)); + else + tx_pa_bias[1] = (pg_pa_bias >> 1); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b 2g tx_patha_pa_bias:%d tx_pathb_pa_bias:%d\n", tx_pa_bias[0], tx_pa_bias[1])); + + for (e_rf_path = ODM_RF_PATH_A; e_rf_path < 2; e_rf_path++) + phydm_set_pa_bias_to_rf_8822b(p_dm_odm, e_rf_path, tx_pa_bias[e_rf_path]); + } + else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b 2g tx pa bias no pg\n")); +} + + + +void +phydm_set_kfree_to_rf_8822b( + void *p_dm_void, + u8 e_rf_path, + u8 data +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(0), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(4), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, bMaskLWord, 0x9000); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(5), 1); + + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, + ("[kfree] 8822b 0x55[19:14]=0x%X path=%d\n", + odm_get_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), + e_rf_path + )); +} + + + +void +phydm_clear_kfree_to_rf_8822b( + void *p_dm_void, + u8 e_rf_path, + u8 data +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(0), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(4), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, bMaskLWord, 0x9000); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(5), 1); + + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1)); + + odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(0), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(4), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, bMaskLWord, 0x9000); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(5), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(7), 0); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, + ("[kfree] 8822b clear power trim 0x55[19:14]=0x%X path=%d\n", + odm_get_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), + e_rf_path + )); +} + + + +void +phydm_set_kfree_to_rf( + void *p_dm_void, + u8 e_rf_path, + u8 data +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + phydm_set_kfree_to_rf_8814a(p_dm_odm, e_rf_path, data); + + if ((p_dm_odm->support_ic_type & ODM_RTL8821C) && (*p_dm_odm->p_band_type == ODM_BAND_2_4G)) + phydm_set_kfree_to_rf_8821c(p_dm_odm, e_rf_path, true, data); + else if (p_dm_odm->support_ic_type & ODM_RTL8821C) + phydm_set_kfree_to_rf_8821c(p_dm_odm, e_rf_path, false, data); + + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + phydm_set_kfree_to_rf_8822b(p_dm_odm, e_rf_path, data); +} + + + +void +phydm_clear_kfree_to_rf( + void *p_dm_void, + u8 e_rf_path, + u8 data +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + phydm_clear_kfree_to_rf_8822b(p_dm_odm, e_rf_path, 1); +} + + + + +void +phydm_get_thermal_trim_offset( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + PEFUSE_HAL pEfuseHal = &(p_hal_data->EfuseHal); + u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2]; + + if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] dump efuse fail !!!\n")); +#endif + + if (p_dm_odm->support_ic_type & ODM_RTL8821C) + phydm_get_thermal_trim_offset_8821c(p_dm_void); + else if (p_dm_odm->support_ic_type & ODM_RTL8822B) + phydm_get_thermal_trim_offset_8822b(p_dm_void); +} + + + +void +phydm_get_power_trim_offset( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + PEFUSE_HAL pEfuseHal = &(p_hal_data->EfuseHal); + u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2]; + + if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] dump efuse fail !!!\n")); +#endif + + if (p_dm_odm->support_ic_type & ODM_RTL8821C) + phydm_get_power_trim_offset_8821c(p_dm_void); + else if (p_dm_odm->support_ic_type & ODM_RTL8822B) + phydm_get_power_trim_offset_8822b(p_dm_void); +} + + + +void +phydm_get_pa_bias_offset( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + PEFUSE_HAL pEfuseHal = &(p_hal_data->EfuseHal); + u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2]; + + if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] dump efuse fail !!!\n")); +#endif + + if (p_dm_odm->support_ic_type & ODM_RTL8822B) + phydm_get_pa_bias_offset_8822b(p_dm_void); +} + + + +s8 +phydm_get_thermal_offset( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + + if (p_power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + return p_power_trim_info->thermal; + else + return 0; +} + + + +void +phydm_config_kfree( + void *p_dm_void, + u8 channel_to_sw +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + + u8 rfpath = 0, max_rf_path = 0; + u8 channel_idx = 0, i, j; + + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + max_rf_path = 4; /*0~3*/ + else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B)) + max_rf_path = 2; /*0~1*/ + else if (p_dm_odm->support_ic_type & ODM_RTL8821C) + max_rf_path = 1; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("===>[kfree] phy_ConfigKFree()\n")); + + if (p_rf_calibrate_info->reg_rf_kfree_enable == 2) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == 2, Disable\n")); + return; + } else if (p_rf_calibrate_info->reg_rf_kfree_enable == 1 || p_rf_calibrate_info->reg_rf_kfree_enable == 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == true\n")); + /*Make sure the targetval is defined*/ + if (p_power_trim_info->flag & KFREE_FLAG_ON) { + /*if kfree_table[0] == 0xff, means no Kfree*/ + + for (i = 0; i < BB_GAIN_NUM; i++) { + for (j = 0; j < max_rf_path; j++) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] power_trim_data->bb_gain[%d][%d]=0x%X\n", i, j, p_power_trim_info->bb_gain[i][j])); + } + + if (*p_dm_odm->p_band_type == ODM_BAND_2_4G && p_power_trim_info->flag & KFREE_FLAG_ON_2G) { + + if (channel_to_sw >= 1 && channel_to_sw <= 14) + channel_idx = PHYDM_2G; + + for (rfpath = ODM_RF_PATH_A; rfpath < max_rf_path; rfpath++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phydm_kfree(): channel_to_sw=%d PATH_%d bb_gain:0x%X\n", channel_to_sw, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath])); + phydm_set_kfree_to_rf(p_dm_odm, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath]); + } + + } else if (*p_dm_odm->p_band_type == ODM_BAND_5G && p_power_trim_info->flag & KFREE_FLAG_ON_5G) { + + if (channel_to_sw >= 36 && channel_to_sw <= 48) + channel_idx = PHYDM_5GLB1; + if (channel_to_sw >= 52 && channel_to_sw <= 64) + channel_idx = PHYDM_5GLB2; + if (channel_to_sw >= 100 && channel_to_sw <= 120) + channel_idx = PHYDM_5GMB1; + if (channel_to_sw >= 122 && channel_to_sw <= 144) + channel_idx = PHYDM_5GMB2; + if (channel_to_sw >= 149 && channel_to_sw <= 177) + channel_idx = PHYDM_5GHB; + + for (rfpath = ODM_RF_PATH_A; rfpath < max_rf_path; rfpath++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phydm_kfree(): channel_to_sw=%d PATH_%d bb_gain:0x%X\n", channel_to_sw, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath])); + phydm_set_kfree_to_rf(p_dm_odm, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath]); + } + } + else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] Set default Register\n")); + for (rfpath = ODM_RF_PATH_A; rfpath < max_rf_path; rfpath++) + phydm_clear_kfree_to_rf(p_dm_odm, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath]); + } + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phy_ConfigKFree(): targetval not defined, Don't execute KFree Process.\n")); + return; + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("<===[kfree] phy_ConfigKFree()\n")); +} diff --git a/hal/phydm/halrf/halrf_kfree.h b/hal/phydm/halrf/halrf_kfree.h new file mode 100644 index 0000000..5bdc8a0 --- /dev/null +++ b/hal/phydm/halrf/halrf_kfree.h @@ -0,0 +1,123 @@ + +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMKFREE_H__ +#define __PHYDKFREE_H__ + +#define KFREE_VERSION "1.0" + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP)) + +#define BB_GAIN_NUM 6 +#define KFREE_FLAG_ON BIT(0) +#define KFREE_FLAG_THERMAL_K_ON BIT(1) + +#endif + +#define KFREE_FLAG_ON_2G BIT(2) +#define KFREE_FLAG_ON_5G BIT(3) + +#define PPG_THERMAL_OFFSET_8821C 0x1EF +#define PPG_BB_GAIN_2G_TXAB_OFFSET_8821C 0x1EE +#define PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C 0x1EC +#define PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C 0x1E8 +#define PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C 0x1E4 +#define PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C 0x1E0 +#define PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C 0x1DC + + + +#define PPG_THERMAL_OFFSET 0x3EF +#define PPG_BB_GAIN_2G_TXAB_OFFSET 0x3EE +#define PPG_BB_GAIN_2G_TXCD_OFFSET 0x3ED +#define PPG_BB_GAIN_5GL1_TXA_OFFSET 0x3EC +#define PPG_BB_GAIN_5GL1_TXB_OFFSET 0x3EB +#define PPG_BB_GAIN_5GL1_TXC_OFFSET 0x3EA +#define PPG_BB_GAIN_5GL1_TXD_OFFSET 0x3E9 +#define PPG_BB_GAIN_5GL2_TXA_OFFSET 0x3E8 +#define PPG_BB_GAIN_5GL2_TXB_OFFSET 0x3E7 +#define PPG_BB_GAIN_5GL2_TXC_OFFSET 0x3E6 +#define PPG_BB_GAIN_5GL2_TXD_OFFSET 0x3E5 +#define PPG_BB_GAIN_5GM1_TXA_OFFSET 0x3E4 +#define PPG_BB_GAIN_5GM1_TXB_OFFSET 0x3E3 +#define PPG_BB_GAIN_5GM1_TXC_OFFSET 0x3E2 +#define PPG_BB_GAIN_5GM1_TXD_OFFSET 0x3E1 +#define PPG_BB_GAIN_5GM2_TXA_OFFSET 0x3E0 +#define PPG_BB_GAIN_5GM2_TXB_OFFSET 0x3DF +#define PPG_BB_GAIN_5GM2_TXC_OFFSET 0x3DE +#define PPG_BB_GAIN_5GM2_TXD_OFFSET 0x3DD +#define PPG_BB_GAIN_5GH1_TXA_OFFSET 0x3DC +#define PPG_BB_GAIN_5GH1_TXB_OFFSET 0x3DB +#define PPG_BB_GAIN_5GH1_TXC_OFFSET 0x3DA +#define PPG_BB_GAIN_5GH1_TXD_OFFSET 0x3D9 + +#define PPG_PA_BIAS_2G_TXA_OFFSET 0x3D5 +#define PPG_PA_BIAS_2G_TXB_OFFSET 0x3D6 + + + +struct odm_power_trim_data { + u8 flag; + s8 bb_gain[BB_GAIN_NUM][MAX_RF_PATH]; + s8 thermal; +}; + + + +enum phydm_kfree_channeltosw { + PHYDM_2G = 0, + PHYDM_5GLB1 = 1, + PHYDM_5GLB2 = 2, + PHYDM_5GMB1 = 3, + PHYDM_5GMB2 = 4, + PHYDM_5GHB = 5, +}; + + + +void +phydm_get_thermal_trim_offset( + void *p_dm_void +); + +void +phydm_get_power_trim_offset( + void *p_dm_void +); + +void +phydm_get_pa_bias_offset( + void *p_dm_void +); + +s8 +phydm_get_thermal_offset( + void *p_dm_void +); + +void +phydm_config_kfree( + void *p_dm_void, + u8 channel_to_sw +); + + +#endif diff --git a/hal/phydm/halrf/halrf_powertracking_ap.c b/hal/phydm/halrf/halrf_powertracking_ap.c new file mode 100644 index 0000000..3868182 --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_ap.c @@ -0,0 +1,1166 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if !defined(_OUTSRC_COEXIST) +/* ************************************************************ + * Global var + * ************************************************************ */ + + +u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D] = { + 0x0b40002d, /* 0, -15.0dB */ + 0x0c000030, /* 1, -14.5dB */ + 0x0cc00033, /* 2, -14.0dB */ + 0x0d800036, /* 3, -13.5dB */ + 0x0e400039, /* 4, -13.0dB */ + 0x0f00003c, /* 5, -12.5dB */ + 0x10000040, /* 6, -12.0dB */ + 0x11000044, /* 7, -11.5dB */ + 0x12000048, /* 8, -11.0dB */ + 0x1300004c, /* 9, -10.5dB */ + 0x14400051, /* 10, -10.0dB */ + 0x15800056, /* 11, -9.5dB */ + 0x16c0005b, /* 12, -9.0dB */ + 0x18000060, /* 13, -8.5dB */ + 0x19800066, /* 14, -8.0dB */ + 0x1b00006c, /* 15, -7.5dB */ + 0x1c800072, /* 16, -7.0dB */ + 0x1e400079, /* 17, -6.5dB */ + 0x20000080, /* 18, -6.0dB */ + 0x22000088, /* 19, -5.5dB */ + 0x24000090, /* 20, -5.0dB */ + 0x26000098, /* 21, -4.5dB */ + 0x288000a2, /* 22, -4.0dB */ + 0x2ac000ab, /* 23, -3.5dB */ + 0x2d4000b5, /* 24, -3.0dB */ + 0x300000c0, /* 25, -2.5dB */ + 0x32c000cb, /* 26, -2.0dB */ + 0x35c000d7, /* 27, -1.5dB */ + 0x390000e4, /* 28, -1.0dB */ + 0x3c8000f2, /* 29, -0.5dB */ + 0x40000100, /* 30, +0dB */ + 0x43c0010f, /* 31, +0.5dB */ + 0x47c0011f, /* 32, +1.0dB */ + 0x4c000130, /* 33, +1.5dB */ + 0x50800142, /* 34, +2.0dB */ + 0x55400155, /* 35, +2.5dB */ + 0x5a400169, /* 36, +3.0dB */ + 0x5fc0017f, /* 37, +3.5dB */ + 0x65400195, /* 38, +4.0dB */ + 0x6b8001ae, /* 39, +4.5dB */ + 0x71c001c7, /* 40, +5.0dB */ + 0x788001e2, /* 41, +5.5dB */ + 0x7f8001fe /* 42, +6.0dB */ +}; + +u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */ + {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */ +}; + + +u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ + {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ +}; + +u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D] = { + 0x0b40002d, /* 0, -15.0dB */ + 0x0c000030, /* 1, -14.5dB */ + 0x0cc00033, /* 2, -14.0dB */ + 0x0d800036, /* 3, -13.5dB */ + 0x0e400039, /* 4, -13.0dB */ + 0x0f00003c, /* 5, -12.5dB */ + 0x10000040, /* 6, -12.0dB */ + 0x11000044, /* 7, -11.5dB */ + 0x12000048, /* 8, -11.0dB */ + 0x1300004c, /* 9, -10.5dB */ + 0x14400051, /* 10, -10.0dB */ + 0x15800056, /* 11, -9.5dB */ + 0x16c0005b, /* 12, -9.0dB */ + 0x18000060, /* 13, -8.5dB */ + 0x19800066, /* 14, -8.0dB */ + 0x1b00006c, /* 15, -7.5dB */ + 0x1c800072, /* 16, -7.0dB */ + 0x1e400079, /* 17, -6.5dB */ + 0x20000080, /* 18, -6.0dB */ + 0x22000088, /* 19, -5.5dB */ + 0x24000090, /* 20, -5.0dB */ + 0x26000098, /* 21, -4.5dB */ + 0x288000a2, /* 22, -4.0dB */ + 0x2ac000ab, /* 23, -3.5dB */ + 0x2d4000b5, /* 24, -3.0dB */ + 0x300000c0, /* 25, -2.5dB */ + 0x32c000cb, /* 26, -2.0dB */ + 0x35c000d7, /* 27, -1.5dB */ + 0x390000e4, /* 28, -1.0dB */ + 0x3c8000f2, /* 29, -0.5dB */ + 0x40000100, /* 30, +0dB */ + 0x43c0010f, /* 31, +0.5dB */ + 0x47c0011f, /* 32, +1.0dB */ + 0x4c000130, /* 33, +1.5dB */ + 0x50800142, /* 34, +2.0dB */ + 0x55400155, /* 35, +2.5dB */ + 0x5a400169, /* 36, +3.0dB */ + 0x5fc0017f, /* 37, +3.5dB */ + 0x65400195, /* 38, +4.0dB */ + 0x6b8001ae, /* 39, +4.5dB */ + 0x71c001c7, /* 40, +5.0dB */ + 0x788001e2, /* 41, +5.5dB */ + 0x7f8001fe /* 42, +6.0dB */ +}; + + +u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */ + {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */ +}; + + +u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ + {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ +}; + +u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */ + {0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */ + {0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */ + {0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */ + {0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */ + {0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */ + {0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */ + {0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */ + {0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */ + {0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */ + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */ +}; + + +u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = { + {0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */ + {0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */ + {0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */ + {0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */ + {0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */ + {0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */ + {0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */ + {0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */ + {0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */ + {0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */ + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */ +}; + + +u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + + +#if 0 +u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = { + /* Index0 6 dB */ 0x7fc001ff, + /* Index1 5.7dB */ 0x7b4001ed, + /* Index2 5.4dB */ 0x774001dd, + /* Index3 5.1dB */ 0x734001cd, + /* Index4 4.8dB */ 0x6f4001bd, + /* Index5 4.5dB */ 0x6b8001ae, + /* Index6 4.2dB */ 0x67c0019f, + /* Index7 3.9dB */ 0x64400191, + /* Index8 3.6dB */ 0x60c00183, + /* Index9 3.3dB */ 0x5d800176, + /* Index10 3 dB */ 0x5a80016a, + /* Index11 2.7dB */ 0x5740015d, + /* Index12 2.4dB */ 0x54400151, + /* Index13 2.1dB */ 0x51800146, + /* Index14 1.8dB */ 0x4ec0013b, + /* Index15 1.5dB */ 0x4c000130, + /* Index16 1.2dB */ 0x49800126, + /* Index17 0.9dB */ 0x4700011c, + /* Index18 0.6dB */ 0x44800112, + /* Index19 0.3dB */ 0x42000108, + /* Index20 0 dB */ 0x40000100, /* 20 This is OFDM base index */ + /* Index21 -0.3dB */ 0x3dc000f7, + /* Index22 -0.6dB */ 0x3bc000ef, + /* Index23 -0.9dB */ 0x39c000e7, + /* Index24 -1.2dB */ 0x37c000df, + /* Index25 -1.5dB */ 0x35c000d7, + /* Index26 -1.8dB */ 0x340000d0, + /* Index27 -2.1dB */ 0x324000c9, + /* Index28 -2.4dB */ 0x308000c2, + /* Index29 -2.7dB */ 0x2f0000bc, + /* Index30 -3 dB */ 0x2d4000b5, + /* Index31 -3.3dB */ 0x2bc000af, + /* Index32 -3.6dB */ 0x2a4000a9, + /* Index33 -3.9dB */ 0x28c000a3, + /* Index34 -4.2dB */ 0x2780009e, + /* Index35 -4.5dB */ 0x26000098, + /* Index36 -4.8dB */ 0x24c00093, + /* Index37 -5.1dB */ 0x2380008e, + /* Index38 -5.4dB */ 0x22400089, + /* Index39 -5.7dB */ 0x21400085, + /* Index40 -6 dB */ 0x20000080, + /* Index41 -6.3dB */ 0x1f00007c, + /* Index42 -6.6dB */ 0x1e000078, + /* Index43 -6.9dB */ 0x1d000074, + /* Index44 -7.2dB */ 0x1c000070, + /* Index45 -7.5dB */ 0x1b00006c, + /* Index46 -7.8dB */ 0x1a000068, + /* Index47 -8.1dB */ 0x19400065, + /* Index48 -8.4dB */ 0x18400061, + /* Index49 -8.7dB */ 0x1780005e, + /* Index50 -9 dB */ 0x16c0005b, + /* Index51 -9.3dB */ 0x16000058, + /* Index52 -9.6dB */ 0x15400055, + /* Index53 -9.9dB */ 0x14800052 +}; +u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04}, + /* Index1 -0.3dB */ {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04}, + /* Index2 -0.6dB */ {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04}, + /* Index3 -0.9dB */ {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04}, + /* Index4 -1.2dB */ {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03}, + /* Index5 -1.5dB */ {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03}, + /* Index6 -1.8dB */ {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03}, + /* Index7 -2.1dB */ {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03}, + /* Index8 -2.4dB */ {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03}, + /* Index9 -2.7dB */ {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03}, + /* Index10 -3 dB */ {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03}, + /* Index11 -3.3dB */ {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03}, + /* Index12 -3.6dB */ {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03}, + /* Index13 -3.9dB */ {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03}, + /* Index14 -4.2dB */ {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02}, + /* Index15 -4.5dB */ {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02}, + /* Index16 -4.8dB */ {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02}, + /* Index17 -5.1dB */ {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02}, + /* Index18 -5.4dB */ {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02}, + /* Index19 -5.7dB */ {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02}, + /* Index20 -6.0dB */ {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */ + /* Index21 -6.3dB */ {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02}, + /* Index22 -6.6dB */ {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02}, + /* Index23 -6.9dB */ {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02}, + /* Index24 -7.2dB */ {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02}, + /* Index25 -7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02}, + /* Index26 -7.8dB */ {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02}, + /* Index27 -8.1dB */ {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02}, + /* Index28 -8.4dB */ {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02}, + /* Index29 -8.7dB */ {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01}, + /* Index30 -9.0dB */ {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */ + /* Index31 -9.3dB */ {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01}, + /* Index32 -9.6dB */ {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01}, + /* Index33 -9.9dB */ {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01}, + /* Index34 -10.2dB */ {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01}, + /* Index35 -10.5dB */ {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01}, + /* Index36 -10.8dB */ {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01}, + /* Index37 -11.1dB */ {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01}, + /* Index38 -11.4dB */ {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01}, + /* Index39 -11.7dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01}, + /* Index40 -12 dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01}, + /* Index41 -12.3dB */ {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01}, + /* Index42 -12.6dB */ {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01}, + /* Index43 -12.9dB */ {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01}, + /* Index44 -13.2dB */ {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01}, + /* Index45 -13.5dB */ {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01}, + /* Index46 -13.8dB */ {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, + /* Index47 -14.1dB */ {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01}, + /* Index48 -14.4dB */ {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, + /* Index49 -14.7dB */ {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01}, + /* Index50 -15 dB */ {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01}, + /* Index51 -15.3dB */ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, + /* Index52 -15.6dB */ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, + /* Index53 -15.9dB */ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} +}; +u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00}, + /* Index1 -0.3dB */ {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00}, + /* Index2 -0.6dB */ {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00}, + /* Index3 -0.9dB */ {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00}, + /* Index4 -1.2dB */ {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00}, + /* Index5 -1.5dB */ {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00}, + /* Index6 -1.8dB */ {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00}, + /* Index7 -2.1dB */ {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00}, + /* Index8 -2.4dB */ {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00}, + /* Index9 -2.7dB */ {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00}, + /* Index10 -3 dB */ {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00}, + /* Index11 -3.3dB */ {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00}, + /* Index12 -3.6dB */ {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00}, + /* Index13 -3.9dB */ {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00}, + /* Index14 -4.2dB */ {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00}, + /* Index15 -4.5dB */ {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00}, + /* Index16 -4.8dB */ {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00}, + /* Index17 -5.1dB */ {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00}, + /* Index18 -5.4dB */ {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00}, + /* Index19 -5.7dB */ {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00}, + /* Index20 -6 dB */ {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00}, + /* Index21 -6.3dB */ {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00}, + /* Index22 -6.6dB */ {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00}, + /* Index23 -6.9dB */ {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00}, + /* Index24 -7.2dB */ {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00}, + /* Index25 -7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00}, + /* Index26 -7.8dB */ {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00}, + /* Index27 -8.1dB */ {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00}, + /* Index28 -8.4dB */ {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00}, + /* Index29 -8.7dB */ {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00}, + /* Index30 -9 dB */ {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00}, + /* Index31 -9.3dB */ {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00}, + /* Index32 -9.6dB */ {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00}, + /* Index33 -9.9dB */ {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00}, + /* Index34 -10.2dB */ {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00}, + /* Index35 -10.5dB */ {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00}, + /* Index36 -10.8dB */ {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00}, + /* Index37 -11.1dB */ {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index38 -11.4dB */ {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index39 -11.7dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index40 -12 dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index41 -12.3dB */ {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* Index42 -12.6dB */ {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* Index43 -12.9dB */ {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* Index44 -13.2dB */ {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* Index45 -13.5dB */ {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* Index46 -13.8dB */ {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* Index47 -14.1dB */ {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index48 -14.4dB */ {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index49 -14.7dB */ {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index50 -15 dB */ {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index51 -15.3dB */ {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00}, + /* Index52 -15.6dB */ {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00}, + /* Index53 -15.9dB */ {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00} +}; +#endif +#endif + + +u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3 + , 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9 + }; +u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4 + , 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 + }; + + +#ifdef CONFIG_WLAN_HAL_8192EE +u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = { + /* Index0 6 dB */ 0x7fc001ff, + /* Index1 5.7dB */ 0x7b4001ed, + /* Index2 5.4dB */ 0x774001dd, + /* Index3 5.1dB */ 0x734001cd, + /* Index4 4.8dB */ 0x6f4001bd, + /* Index5 4.5dB */ 0x6b8001ae, + /* Index6 4.2dB */ 0x67c0019f, + /* Index7 3.9dB */ 0x64400191, + /* Index8 3.6dB */ 0x60c00183, + /* Index9 3.3dB */ 0x5d800176, + /* Index10 3 dB */ 0x5a80016a, + /* Index11 2.7dB */ 0x5740015d, + /* Index12 2.4dB */ 0x54400151, + /* Index13 2.1dB */ 0x51800146, + /* Index14 1.8dB */ 0x4ec0013b, + /* Index15 1.5dB */ 0x4c000130, + /* Index16 1.2dB */ 0x49800126, + /* Index17 0.9dB */ 0x4700011c, + /* Index18 0.6dB */ 0x44800112, + /* Index19 0.3dB */ 0x42000108, + /* Index20 0 dB */ 0x40000100, /* 20 This is OFDM base index */ + /* Index21 -0.3dB */ 0x3dc000f7, + /* Index22 -0.6dB */ 0x3bc000ef, + /* Index23 -0.9dB */ 0x39c000e7, + /* Index24 -1.2dB */ 0x37c000df, + /* Index25 -1.5dB */ 0x35c000d7, + /* Index26 -1.8dB */ 0x340000d0, + /* Index27 -2.1dB */ 0x324000c9, + /* Index28 -2.4dB */ 0x308000c2, + /* Index29 -2.7dB */ 0x2f0000bc, + /* Index30 -3 dB */ 0x2d4000b5, + /* Index31 -3.3dB */ 0x2bc000af, + /* Index32 -3.6dB */ 0x2a4000a9, + /* Index33 -3.9dB */ 0x28c000a3, + /* Index34 -4.2dB */ 0x2780009e, + /* Index35 -4.5dB */ 0x26000098, + /* Index36 -4.8dB */ 0x24c00093, + /* Index37 -5.1dB */ 0x2380008e, + /* Index38 -5.4dB */ 0x22400089, + /* Index39 -5.7dB */ 0x21400085, + /* Index40 -6 dB */ 0x20000080, + /* Index41 -6.3dB */ 0x1f00007c, + /* Index42 -6.6dB */ 0x1e000078, + /* Index43 -6.9dB */ 0x1d000074, + /* Index44 -7.2dB */ 0x1c000070, + /* Index45 -7.5dB */ 0x1b00006c, + /* Index46 -7.8dB */ 0x1a000068, + /* Index47 -8.1dB */ 0x19400065, + /* Index48 -8.4dB */ 0x18400061, + /* Index49 -8.7dB */ 0x1780005e, + /* Index50 -9 dB */ 0x16c0005b, + /* Index51 -9.3dB */ 0x16000058, + /* Index52 -9.6dB */ 0x15400055, + /* Index53 -9.9dB */ 0x14800052 +}; +u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04}, + /* Index1 -0.3dB */ {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04}, + /* Index2 -0.6dB */ {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04}, + /* Index3 -0.9dB */ {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04}, + /* Index4 -1.2dB */ {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03}, + /* Index5 -1.5dB */ {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03}, + /* Index6 -1.8dB */ {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03}, + /* Index7 -2.1dB */ {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03}, + /* Index8 -2.4dB */ {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03}, + /* Index9 -2.7dB */ {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03}, + /* Index10 -3 dB */ {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03}, + /* Index11 -3.3dB */ {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03}, + /* Index12 -3.6dB */ {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03}, + /* Index13 -3.9dB */ {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03}, + /* Index14 -4.2dB */ {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02}, + /* Index15 -4.5dB */ {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02}, + /* Index16 -4.8dB */ {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02}, + /* Index17 -5.1dB */ {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02}, + /* Index18 -5.4dB */ {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02}, + /* Index19 -5.7dB */ {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02}, + /* Index20 -6.0dB */ {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */ + /* Index21 -6.3dB */ {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02}, + /* Index22 -6.6dB */ {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02}, + /* Index23 -6.9dB */ {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02}, + /* Index24 -7.2dB */ {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02}, + /* Index25 -7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02}, + /* Index26 -7.8dB */ {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02}, + /* Index27 -8.1dB */ {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02}, + /* Index28 -8.4dB */ {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02}, + /* Index29 -8.7dB */ {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01}, + /* Index30 -9.0dB */ {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */ + /* Index31 -9.3dB */ {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01}, + /* Index32 -9.6dB */ {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01}, + /* Index33 -9.9dB */ {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01}, + /* Index34 -10.2dB */ {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01}, + /* Index35 -10.5dB */ {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01}, + /* Index36 -10.8dB */ {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01}, + /* Index37 -11.1dB */ {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01}, + /* Index38 -11.4dB */ {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01}, + /* Index39 -11.7dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01}, + /* Index40 -12 dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01}, + /* Index41 -12.3dB */ {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01}, + /* Index42 -12.6dB */ {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01}, + /* Index43 -12.9dB */ {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01}, + /* Index44 -13.2dB */ {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01}, + /* Index45 -13.5dB */ {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01}, + /* Index46 -13.8dB */ {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, + /* Index47 -14.1dB */ {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01}, + /* Index48 -14.4dB */ {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, + /* Index49 -14.7dB */ {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01}, + /* Index50 -15 dB */ {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01}, + /* Index51 -15.3dB */ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, + /* Index52 -15.6dB */ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, + /* Index53 -15.9dB */ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} +}; +u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00}, + /* Index1 -0.3dB */ {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00}, + /* Index2 -0.6dB */ {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00}, + /* Index3 -0.9dB */ {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00}, + /* Index4 -1.2dB */ {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00}, + /* Index5 -1.5dB */ {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00}, + /* Index6 -1.8dB */ {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00}, + /* Index7 -2.1dB */ {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00}, + /* Index8 -2.4dB */ {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00}, + /* Index9 -2.7dB */ {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00}, + /* Index10 -3 dB */ {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00}, + /* Index11 -3.3dB */ {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00}, + /* Index12 -3.6dB */ {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00}, + /* Index13 -3.9dB */ {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00}, + /* Index14 -4.2dB */ {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00}, + /* Index15 -4.5dB */ {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00}, + /* Index16 -4.8dB */ {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00}, + /* Index17 -5.1dB */ {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00}, + /* Index18 -5.4dB */ {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00}, + /* Index19 -5.7dB */ {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00}, + /* Index20 -6 dB */ {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00}, + /* Index21 -6.3dB */ {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00}, + /* Index22 -6.6dB */ {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00}, + /* Index23 -6.9dB */ {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00}, + /* Index24 -7.2dB */ {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00}, + /* Index25 -7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00}, + /* Index26 -7.8dB */ {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00}, + /* Index27 -8.1dB */ {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00}, + /* Index28 -8.4dB */ {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00}, + /* Index29 -8.7dB */ {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00}, + /* Index30 -9 dB */ {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00}, + /* Index31 -9.3dB */ {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00}, + /* Index32 -9.6dB */ {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00}, + /* Index33 -9.9dB */ {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00}, + /* Index34 -10.2dB */ {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00}, + /* Index35 -10.5dB */ {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00}, + /* Index36 -10.8dB */ {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00}, + /* Index37 -11.1dB */ {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index38 -11.4dB */ {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index39 -11.7dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index40 -12 dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index41 -12.3dB */ {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* Index42 -12.6dB */ {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* Index43 -12.9dB */ {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* Index44 -13.2dB */ {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* Index45 -13.5dB */ {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* Index46 -13.8dB */ {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* Index47 -14.1dB */ {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index48 -14.4dB */ {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index49 -14.7dB */ {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index50 -15 dB */ {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index51 -15.3dB */ {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00}, + /* Index52 -15.6dB */ {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00}, + /* Index53 -15.9dB */ {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00} +}; +#endif + +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1) +u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = { + 0x081, /* 0, -12.0dB */ + 0x088, /* 1, -11.5dB */ + 0x090, /* 2, -11.0dB */ + 0x099, /* 3, -10.5dB */ + 0x0A2, /* 4, -10.0dB */ + 0x0AC, /* 5, -9.5dB */ + 0x0B6, /* 6, -9.0dB */ + 0x0C0, /* 7, -8.5dB */ + 0x0CC, /* 8, -8.0dB */ + 0x0D8, /* 9, -7.5dB */ + 0x0E5, /* 10, -7.0dB */ + 0x0F2, /* 11, -6.5dB */ + 0x101, /* 12, -6.0dB */ + 0x110, /* 13, -5.5dB */ + 0x120, /* 14, -5.0dB */ + 0x131, /* 15, -4.5dB */ + 0x143, /* 16, -4.0dB */ + 0x156, /* 17, -3.5dB */ + 0x16A, /* 18, -3.0dB */ + 0x180, /* 19, -2.5dB */ + 0x197, /* 20, -2.0dB */ + 0x1AF, /* 21, -1.5dB */ + 0x1C8, /* 22, -1.0dB */ + 0x1E3, /* 23, -0.5dB */ + 0x200, /* 24, +0 dB */ + 0x21E, /* 25, +0.5dB */ + 0x23E, /* 26, +1.0dB */ + 0x261, /* 27, +1.5dB */ + 0x285, /* 28, +2.0dB */ + 0x2AB, /* 29, +2.5dB */ + 0x2D3, /* 30, +3.0dB */ + 0x2FE, /* 31, +3.5dB */ + 0x32B, /* 32, +4.0dB */ + 0x35C, /* 33, +4.5dB */ + 0x38E, /* 34, +5.0dB */ + 0x3C4, /* 35, +5.5dB */ + 0x3FE /* 36, +6.0dB */ +}; +#elif(ODM_IC_11AC_SERIES_SUPPORT) +u32 ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812] = { + 0x3FE, /* 0, (6dB) */ + 0x3C4, /* 1, (5.5dB) */ + 0x38E, /* 2, (5dB) */ + 0x35C, /* 3, (4.5dB) */ + 0x32B, /* 4, (4dB) */ + 0x2FE, /* 5, (3.5dB) */ + 0x2D3, /* 6, (3dB) */ + 0x2AB, /* 7, (2.5dB) */ + 0x285, /* 8, (2dB) */ + 0x261, /* 9, (1.5dB */ + 0x23E, /* 10, (1dB) */ + 0x21E, /* 11, (0.5dB) */ + 0x200, /* 12, (0dB) 8814 int PA 2G default */ + 0x1E3, /* 13, (-0.5dB) */ + 0x1C8, /* 14, (-1dB) */ + 0x1AF, /* 15, (-1.5dB) */ + 0x197, /* 16, (-2dB) */ + 0x180, /* 17, (-2.5dB) */ + 0x16A, /* 18, (-3dB) 8812 / 8814 int PA 5G / 8814 ext PA 2G5G default */ + 0x156, /* 19, (-3.5dB) */ + 0x143, /* 20, (-4dB) 8812 HP default */ + 0x131, /* 21, (-4.5dB) */ + 0x120, /* 22, (-5dB) */ + 0x110, /* 23, (-5.5dB) */ + 0x101, /* 24, (-6dB) */ + 0x0F2, /* 25, (-6.5dB) */ + 0x0E5, /* 26, (-7dB) */ + 0x0D8, /* 27, (-7.5dB) */ + 0x0CC, /* 28, (-8dB) */ + 0x0C0, /* 29, (-8.5dB) */ + 0x0B6, /* 30, (-9dB) */ + 0x0AC, /* 31, (-9.5dB) */ + 0x0A2, /* 32, (-10dB) */ + 0x099, /* 33, (-10.5dB) */ + 0x090, /* 34, (-11dB) */ + 0x088, /* 35, (-11.5dB) */ + 0x081, /* 36, (-12dB) */ + 0x079, /* 37, (-12.5dB) */ + 0x072, /* 38, (-13dB) */ + 0x06c, /* 39, (-13.5dB) */ + 0x066, /* 40, (-14dB) */ + 0x060, /* 41, (-14.5dB) */ + 0x05B /* 42, (-15dB) */ +}; +#endif + +u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = { + 0x0CD, + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; +/* JJ ADD 20161014 */ +u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = { + 0x0CD, + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + + +/* #endif */ +/* 3============================================================ + * 3 Tx Power Tracking + * 3============================================================ */ + +void +odm_txpowertracking_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if (!(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES))) + return; +#endif + + odm_txpowertracking_thermal_meter_init(p_dm_odm); +} + + +u8 +get_swing_index( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0, bb_swing_mask = 0; + u32 bb_swing = 0; + u32 swing_table_size = 0; + u32 *p_swing_table = 0; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + +#if (RTL8197F_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8197F) { + bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D); + p_swing_table = ofdm_swing_table_new; + swing_table_size = OFDM_TABLE_SIZE_92D; + bb_swing_mask = 22; + } +#endif + +#if (RTL8822B_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8822B) { + bb_swing = phy_query_bb_reg(priv, REG_A_TX_SCALE_JAGUAR, 0xFFE00000); + p_swing_table = tx_scaling_table_jaguar; + swing_table_size = TXSCALE_TABLE_SIZE; + bb_swing_mask = 0; + } +#endif + + for (i = 0; i < swing_table_size - 1; i++) { + u32 table_value = p_swing_table[i] >> bb_swing_mask; + + if (bb_swing == table_value) + break; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("bb_swing=0x%x bbswing_index=%d\n", bb_swing, i)); + + + return i; +} + + +void +odm_txpowertracking_thermal_meter_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct rtl8192cd_priv *priv = p_dm_odm->priv; + u8 p; + u8 default_swing_index; +#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) + if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B)) + default_swing_index = get_swing_index(p_dm_odm); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + + p_mgnt_info->is_txpowertracking = true; + p_hal_data->tx_powercount = 0; + p_hal_data->is_txpowertracking_init = false; + + if (*(p_dm_odm->p_mp_mode) == false) + p_hal_data->txpowertrack_control = true; + ODM_RT_TRACE(p_dm_odm, COMP_POWER_TRACKING, DBG_LOUD, ("p_mgnt_info->is_txpowertracking = %d\n", p_mgnt_info->is_txpowertracking)); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#ifdef CONFIG_RTL8188E + { + p_dm_odm->rf_calibrate_info.is_txpowertracking = _TRUE; + p_dm_odm->rf_calibrate_info.tx_powercount = 0; + p_dm_odm->rf_calibrate_info.is_txpowertracking_init = _FALSE; + + if (*(p_dm_odm->p_mp_mode) == false) + p_dm_odm->rf_calibrate_info.txpowertrack_control = _TRUE; + + MSG_8192C("p_dm_odm txpowertrack_control = %d\n", p_dm_odm->rf_calibrate_info.txpowertrack_control); + } +#else + { + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct dm_priv *pdmpriv = &p_hal_data->dmpriv; + + /* if(IS_HARDWARE_TYPE_8192C(p_hal_data)) */ + { + pdmpriv->is_txpowertracking = _TRUE; + pdmpriv->tx_powercount = 0; + pdmpriv->is_txpowertracking_init = _FALSE; + + if (*(p_dm_odm->p_mp_mode) == false) /* for mp driver, turn off txpwrtracking as default */ + pdmpriv->txpowertrack_control = _TRUE; + + } + MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control); + + } +#endif/* endif (CONFIG_RTL8188E==1) */ +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#ifdef RTL8188E_SUPPORT + { + p_dm_odm->rf_calibrate_info.is_txpowertracking = _TRUE; + p_dm_odm->rf_calibrate_info.tx_powercount = 0; + p_dm_odm->rf_calibrate_info.is_txpowertracking_init = _FALSE; + p_dm_odm->rf_calibrate_info.txpowertrack_control = _TRUE; + p_dm_odm->rf_calibrate_info.tm_trigger = 0; + } +#endif +#endif + + p_dm_odm->rf_calibrate_info.txpowertrack_control = true; + p_dm_odm->rf_calibrate_info.delta_power_index = 0; + p_dm_odm->rf_calibrate_info.delta_power_index_last = 0; + p_dm_odm->rf_calibrate_info.power_index_offset = 0; + p_dm_odm->rf_calibrate_info.thermal_value = 0; + p_rf_calibrate_info->default_ofdm_index = 28; + +#if (RTL8197F_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8197F) { + p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index; + p_rf_calibrate_info->default_cck_index = 28; + } +#endif + +#if (RTL8822B_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8822B) { + p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : default_swing_index; + p_rf_calibrate_info->default_cck_index = 20; + } +#endif + + +#if RTL8188E_SUPPORT + p_rf_calibrate_info->default_cck_index = 20; /* -6 dB */ +#elif RTL8192E_SUPPORT + p_rf_calibrate_info->default_cck_index = 8; /* -12 dB */ +#endif + p_rf_calibrate_info->bb_swing_idx_ofdm_base = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index; + p_dm_odm->rf_calibrate_info.CCK_index = p_rf_calibrate_info->default_cck_index; + + for (p = 0; p < MAX_RF_PATH; p++) { + p_dm_odm->rf_calibrate_info.OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->kfree_offset[p] = 0; /* for 8814 kfree*/ + } + p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("p_rf_calibrate_info->default_ofdm_index=%d p_rf_calibrate_info->default_cck_index=%d\n", p_rf_calibrate_info->default_ofdm_index, p_rf_calibrate_info->default_cck_index)); + + +} + + +void +odm_txpowertracking_check( + void *p_dm_void +) +{ + /* */ + /* For AP/ADSL use struct rtl8192cd_priv* */ + /* For CE/NIC use struct _ADAPTER* */ + /* */ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + + + if (!(p_rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + return; + + /* */ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ + /* */ + switch (p_dm_odm->support_platform) { + case ODM_WIN: + odm_txpowertracking_check_mp(p_dm_odm); + break; + + case ODM_CE: + odm_txpowertracking_check_ce(p_dm_odm); + break; + + case ODM_AP: + odm_txpowertracking_check_ap(p_dm_odm); + break; + } + +} + +void +odm_txpowertracking_check_ce( + void *p_dm_void +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + +#if (RTL8188E_SUPPORT == 1) + + /* if(!p_mgnt_info->is_txpowertracking || (!pdmpriv->txpowertrack_control && pdmpriv->is_ap_kdone)) */ + + if (!(p_rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + return; + + if (!p_dm_odm->rf_calibrate_info.tm_trigger) { /* at least delay 1 sec */ + /* p_hal_data->TxPowerCheckCnt++; */ /* cosa add for debug */ + odm_set_rf_reg(p_dm_odm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60); + /* DBG_8192C("Trigger 92C Thermal Meter!!\n"); */ + + p_dm_odm->rf_calibrate_info.tm_trigger = 1; + return; + + } else { + /* DBG_8192C("Schedule TxPowerTracking direct call!!\n"); */ + odm_txpowertracking_callback_thermal_meter_8188e(adapter); + p_dm_odm->rf_calibrate_info.tm_trigger = 0; + } +#endif + +#endif +} + +void +odm_txpowertracking_check_mp( + void *p_dm_void +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + + if (odm_check_power_status(adapter) == false) + return; + + if (!adapter->is_slave_of_dmsp || adapter->dual_mac_smart_concurrent == false) + odm_txpowertracking_thermal_meter_check(adapter); +#endif + +} + + +void +odm_txpowertracking_check_ap( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + struct rtl8192cd_priv *priv = p_dm_odm->priv; + +#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B)) + odm_txpowertracking_callback_thermal_meter(p_dm_odm); + else +#endif + { + } +#endif + +} diff --git a/hal/phydm/halrf/halrf_powertracking_ap.h b/hal/phydm/halrf/halrf_powertracking_ap.h new file mode 100644 index 0000000..e2324d4 --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_ap.h @@ -0,0 +1,355 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define HALRF_POWRTRACKING_VER "1.1" + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #ifdef RTK_AC_SUPPORT + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #else + #define ODM_IC_11AC_SERIES_SUPPORT 0 + #endif +#else + #define ODM_IC_11AC_SERIES_SUPPORT 1 +#endif + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define DELTA_SWINGIDX_SIZE 30 +#define DELTA_SWINTSSI_SIZE 61 +#define BAND_NUM 3 +#define MAX_RF_PATH 4 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 +/* JJ ADD 20161014 */ +#define CCK_TABLE_SIZE_8710B 41 + +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 + +#define IQK_BB_REG_NUM 9 + +#define HP_THERMAL_NUM 8 + +#define AVG_THERMAL_NUM 8 +#define iqk_matrix_reg_num 8 +/* #define IQK_MATRIX_SETTINGS_NUM 1+24+21 */ +#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */ + +#if !defined(_OUTSRC_COEXIST) + #define OFDM_TABLE_SIZE_92D 43 + #define OFDM_TABLE_SIZE 37 + #define CCK_TABLE_SIZE 33 + #define CCK_TABLE_SIZE_88F 21 + + + + /* #define OFDM_TABLE_SIZE_92E 54 */ + /* #define CCK_TABLE_SIZE_92E 54 */ + extern u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D]; + extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8]; + extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8]; + + + extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D]; + extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8]; + extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8]; + extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16]; + extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16]; + extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16]; + +#endif + +#define ODM_OFDM_TABLE_SIZE 37 +#define ODM_CCK_TABLE_SIZE 33 +/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */ +extern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE]; +extern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE]; + +static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +/* extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E]; + * extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8]; + * extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; */ + +#ifdef CONFIG_WLAN_HAL_8192EE + #define OFDM_TABLE_SIZE_92E 54 + #define CCK_TABLE_SIZE_92E 54 + extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E]; + extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8]; + extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; +#endif + +#define OFDM_TABLE_SIZE_8812 43 +#define AVG_THERMAL_NUM_8812 4 + +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1) + extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE]; + #elif(ODM_IC_11AC_SERIES_SUPPORT) + extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812]; +#endif + +extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D]; +/* JJ ADD 20161014 */ +extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B]; + +#define dm_check_txpowertracking odm_txpowertracking_check + +struct _IQK_MATRIX_REGS_SETTING { + boolean is_iqk_done; + s32 value[1][iqk_matrix_reg_num]; +}; + +struct odm_rf_calibration_structure { + /* for tx power tracking */ + + u32 rega24; /* for TempCCK */ + s32 rege94; + s32 rege9c; + s32 regeb4; + s32 regebc; + + /* u8 is_txpowertracking; */ + u8 tx_powercount; + boolean is_txpowertracking_init; + boolean is_txpowertracking; + u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */ + u8 tm_trigger; + u8 internal_pa_5g[2]; /* pathA / pathB */ + + u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */ + u8 thermal_value; + u8 thermal_value_lck; + u8 thermal_value_iqk; + s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */ + u8 thermal_value_dpk; + u8 thermal_value_avg[AVG_THERMAL_NUM]; + u8 thermal_value_avg_index; + u8 thermal_value_rx_gain; + u8 thermal_value_crystal; + u8 thermal_value_dpk_store; + u8 thermal_value_dpk_track; + boolean txpowertracking_in_progress; + boolean is_dpk_enable; + + boolean is_reloadtxpowerindex; + u8 is_rf_pi_enable; + u32 txpowertracking_callback_cnt; /* cosa add for debug */ + + u8 is_cck_in_ch14; + u8 CCK_index; + u8 OFDM_index[MAX_RF_PATH]; + s8 power_index_offset; + s8 delta_power_index; + s8 delta_power_index_last; + boolean is_tx_power_changed; + + u8 thermal_value_hp[HP_THERMAL_NUM]; + u8 thermal_value_hp_index; + struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; + u8 delta_lck; + u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE]; + + u8 bb_swing_idx_ofdm[MAX_RF_PATH]; + u8 bb_swing_idx_ofdm_current; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + u8 bb_swing_idx_ofdm_base[MAX_RF_PATH]; +#else + u8 bb_swing_idx_ofdm_base; +#endif + boolean bb_swing_flag_ofdm; + u8 bb_swing_idx_cck; + u8 bb_swing_idx_cck_current; + u8 bb_swing_idx_cck_base; + u8 default_ofdm_index; + u8 default_cck_index; + boolean bb_swing_flag_cck; + + s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; + s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; + s8 absolute_cck_swing_idx[MAX_RF_PATH]; + s8 remnant_cck_swing_idx; + s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */ + boolean modify_tx_agc_flag_path_a; + boolean modify_tx_agc_flag_path_b; + boolean modify_tx_agc_flag_path_c; + boolean modify_tx_agc_flag_path_d; + boolean modify_tx_agc_flag_path_a_cck; + + s8 kfree_offset[MAX_RF_PATH]; + + /* -------------------------------------------------------------------- */ + + /* for IQK */ + u32 regc04; + u32 reg874; + u32 regc08; + u32 regb68; + u32 regb6c; + u32 reg870; + u32 reg860; + u32 reg864; + + boolean is_iqk_initialized; + boolean is_lck_in_progress; + boolean is_antenna_detected; + boolean is_need_iqk; + boolean is_iqk_in_progress; + boolean is_iqk_pa_off; + u8 delta_iqk; + u32 ADDA_backup[IQK_ADDA_REG_NUM]; + u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; + u32 IQK_BB_backup_recover[9]; + u32 IQK_BB_backup[IQK_BB_REG_NUM]; + u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + u64 iqk_start_time; + u64 iqk_total_progressing_time; + u64 iqk_progressing_time; + u32 lok_result; + u8 iqk_step; + u8 kcount; + u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ + boolean is_mp_mode; + + /* for APK */ + u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */ + u8 is_ap_kdone; + u8 is_apk_thermal_meter_ignore; + u8 is_dp_done; + u8 is_dp_path_aok; + u8 is_dp_path_bok; + + /*Add by Yuchen for Kfree Phydm*/ + u8 reg_rf_kfree_enable; /*for registry*/ + u8 rf_kfree_enable; /*for efuse enable check*/ + u32 tx_lok[2]; +}; + +void +odm_txpowertracking_check_ap( + void *p_dm_void +); + +void +odm_txpowertracking_check( + void *p_dm_void +); + + +void +odm_txpowertracking_thermal_meter_init( + void *p_dm_void +); + +void +odm_txpowertracking_init( + void *p_dm_void +); + +void +odm_txpowertracking_check_mp( + void *p_dm_void +); + + +void +odm_txpowertracking_check_ce( + void *p_dm_void +); + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +void +odm_txpowertracking_callback_thermal_meter92c( + struct _ADAPTER *adapter +); + +void +odm_txpowertracking_callback_rx_gain_thermal_meter92d( + struct _ADAPTER *adapter +); + +void +odm_txpowertracking_callback_thermal_meter92d( + struct _ADAPTER *adapter +); + +void +odm_txpowertracking_direct_call92c( + struct _ADAPTER *adapter +); + +void +odm_txpowertracking_thermal_meter_check( + struct _ADAPTER *adapter +); + +#endif + + + +#endif diff --git a/hal/phydm/halrf/halrf_powertracking_ce.c b/hal/phydm/halrf/halrf_powertracking_ce.c new file mode 100644 index 0000000..5bc1b5f --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_ce.c @@ -0,0 +1,762 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/*============================================================ */ +/* include files */ +/*============================================================ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/* ************************************************************ + * Global var + * ************************************************************ */ + +u32 ofdm_swing_table[OFDM_TABLE_SIZE] = { + 0x7f8001fe, /* 0, +6.0dB */ + 0x788001e2, /* 1, +5.5dB */ + 0x71c001c7, /* 2, +5.0dB*/ + 0x6b8001ae, /* 3, +4.5dB*/ + 0x65400195, /* 4, +4.0dB*/ + 0x5fc0017f, /* 5, +3.5dB*/ + 0x5a400169, /* 6, +3.0dB*/ + 0x55400155, /* 7, +2.5dB*/ + 0x50800142, /* 8, +2.0dB*/ + 0x4c000130, /* 9, +1.5dB*/ + 0x47c0011f, /* 10, +1.0dB*/ + 0x43c0010f, /* 11, +0.5dB*/ + 0x40000100, /* 12, +0dB*/ + 0x3c8000f2, /* 13, -0.5dB*/ + 0x390000e4, /* 14, -1.0dB*/ + 0x35c000d7, /* 15, -1.5dB*/ + 0x32c000cb, /* 16, -2.0dB*/ + 0x300000c0, /* 17, -2.5dB*/ + 0x2d4000b5, /* 18, -3.0dB*/ + 0x2ac000ab, /* 19, -3.5dB*/ + 0x288000a2, /* 20, -4.0dB*/ + 0x26000098, /* 21, -4.5dB*/ + 0x24000090, /* 22, -5.0dB*/ + 0x22000088, /* 23, -5.5dB*/ + 0x20000080, /* 24, -6.0dB*/ + 0x1e400079, /* 25, -6.5dB*/ + 0x1c800072, /* 26, -7.0dB*/ + 0x1b00006c, /* 27. -7.5dB*/ + 0x19800066, /* 28, -8.0dB*/ + 0x18000060, /* 29, -8.5dB*/ + 0x16c0005b, /* 30, -9.0dB*/ + 0x15800056, /* 31, -9.5dB*/ + 0x14400051, /* 32, -10.0dB*/ + 0x1300004c, /* 33, -10.5dB*/ + 0x12000048, /* 34, -11.0dB*/ + 0x11000044, /* 35, -11.5dB*/ + 0x10000040, /* 36, -12.0dB*/ +}; + +u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/ + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/ +}; + + +u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default*/ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/ + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/ +}; + + +u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = { + 0x0b40002d, /* 0, -15.0dB */ + 0x0c000030, /* 1, -14.5dB*/ + 0x0cc00033, /* 2, -14.0dB*/ + 0x0d800036, /* 3, -13.5dB*/ + 0x0e400039, /* 4, -13.0dB */ + 0x0f00003c, /* 5, -12.5dB*/ + 0x10000040, /* 6, -12.0dB*/ + 0x11000044, /* 7, -11.5dB*/ + 0x12000048, /* 8, -11.0dB*/ + 0x1300004c, /* 9, -10.5dB*/ + 0x14400051, /* 10, -10.0dB*/ + 0x15800056, /* 11, -9.5dB*/ + 0x16c0005b, /* 12, -9.0dB*/ + 0x18000060, /* 13, -8.5dB*/ + 0x19800066, /* 14, -8.0dB*/ + 0x1b00006c, /* 15, -7.5dB*/ + 0x1c800072, /* 16, -7.0dB*/ + 0x1e400079, /* 17, -6.5dB*/ + 0x20000080, /* 18, -6.0dB*/ + 0x22000088, /* 19, -5.5dB*/ + 0x24000090, /* 20, -5.0dB*/ + 0x26000098, /* 21, -4.5dB*/ + 0x288000a2, /* 22, -4.0dB*/ + 0x2ac000ab, /* 23, -3.5dB*/ + 0x2d4000b5, /* 24, -3.0dB*/ + 0x300000c0, /* 25, -2.5dB*/ + 0x32c000cb, /* 26, -2.0dB*/ + 0x35c000d7, /* 27, -1.5dB*/ + 0x390000e4, /* 28, -1.0dB*/ + 0x3c8000f2, /* 29, -0.5dB*/ + 0x40000100, /* 30, +0dB*/ + 0x43c0010f, /* 31, +0.5dB*/ + 0x47c0011f, /* 32, +1.0dB*/ + 0x4c000130, /* 33, +1.5dB*/ + 0x50800142, /* 34, +2.0dB*/ + 0x55400155, /* 35, +2.5dB*/ + 0x5a400169, /* 36, +3.0dB*/ + 0x5fc0017f, /* 37, +3.5dB*/ + 0x65400195, /* 38, +4.0dB*/ + 0x6b8001ae, /* 39, +4.5dB*/ + 0x71c001c7, /* 40, +5.0dB*/ + 0x788001e2, /* 41, +5.5dB*/ + 0x7f8001fe /* 42, +6.0dB*/ +}; + + +u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/ + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/ +}; + + +u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ +}; +u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; +/* JJ ADD 20161014 */ +u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + + +u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = { + 0x081, /* 0, -12.0dB*/ + 0x088, /* 1, -11.5dB*/ + 0x090, /* 2, -11.0dB*/ + 0x099, /* 3, -10.5dB*/ + 0x0A2, /* 4, -10.0dB*/ + 0x0AC, /* 5, -9.5dB*/ + 0x0B6, /* 6, -9.0dB*/ + 0x0C0, /*7, -8.5dB*/ + 0x0CC, /* 8, -8.0dB*/ + 0x0D8, /* 9, -7.5dB*/ + 0x0E5, /* 10, -7.0dB*/ + 0x0F2, /* 11, -6.5dB*/ + 0x101, /* 12, -6.0dB*/ + 0x110, /* 13, -5.5dB*/ + 0x120, /* 14, -5.0dB*/ + 0x131, /* 15, -4.5dB*/ + 0x143, /* 16, -4.0dB*/ + 0x156, /* 17, -3.5dB*/ + 0x16A, /* 18, -3.0dB*/ + 0x180, /* 19, -2.5dB*/ + 0x197, /* 20, -2.0dB*/ + 0x1AF, /* 21, -1.5dB*/ + 0x1C8, /* 22, -1.0dB*/ + 0x1E3, /* 23, -0.5dB*/ + 0x200, /* 24, +0 dB*/ + 0x21E, /* 25, +0.5dB*/ + 0x23E, /* 26, +1.0dB*/ + 0x261, /* 27, +1.5dB*/ + 0x285,/* 28, +2.0dB*/ + 0x2AB, /* 29, +2.5dB*/ + 0x2D3, /*30, +3.0dB*/ + 0x2FE, /* 31, +3.5dB*/ + 0x32B, /* 32, +4.0dB*/ + 0x35C, /* 33, +4.5dB*/ + 0x38E, /* 34, +5.0dB*/ + 0x3C4, /* 35, +5.5dB*/ + 0x3FE /* 36, +6.0dB */ +}; + +void +odm_txpowertracking_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if (!(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B))) + return; +#endif + + odm_txpowertracking_thermal_meter_init(p_dm_odm); +} + +u8 +get_swing_index( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); +#endif + u8 i = 0; + u32 bb_swing; + u32 swing_table_size; + u32 *p_swing_table; + + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B + || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B + ) { + bb_swing = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000); + + p_swing_table = ofdm_swing_table_new; + swing_table_size = OFDM_TABLE_SIZE; + } else { +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + if (p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8821) { + bb_swing = phy_get_tx_bb_swing_8812a(adapter, p_hal_data->current_band_type, ODM_RF_PATH_A); + p_swing_table = tx_scaling_table_jaguar; + swing_table_size = TXSCALE_TABLE_SIZE; + } else +#endif + { + bb_swing = 0; + p_swing_table = ofdm_swing_table; + swing_table_size = OFDM_TABLE_SIZE; + } + } + + for (i = 0; i < swing_table_size; ++i) { + u32 table_value = p_swing_table[i]; + + if (table_value >= 0x100000) + table_value >>= 22; + if (bb_swing == table_value) + break; + } + return i; +} + +u8 +get_cck_swing_index( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + u8 i = 0; + u32 bb_cck_swing; + + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B || + p_dm_odm->support_ic_type == ODM_RTL8192E) { + bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22); + + for (i = 0; i < CCK_TABLE_SIZE; i++) { + if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0]) + break; + } + } else if (p_dm_odm->support_ic_type == ODM_RTL8703B) { + bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22); + + for (i = 0; i < CCK_TABLE_SIZE_88F; i++) { + if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0]) + break; + } + } + + return i; +} + + +void +odm_txpowertracking_thermal_meter_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 default_swing_index = get_swing_index(p_dm_odm); + u8 default_cck_swing_index = get_cck_swing_index(p_dm_odm); + u8 p = 0; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + + if (*(p_dm_odm->p_mp_mode) == false) + p_hal_data->txpowertrack_control = true; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#ifdef DM_ODM_CE_MAC80211 + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv); +#else + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); +#endif + + p_rf_calibrate_info->is_txpowertracking = _TRUE; + p_rf_calibrate_info->tx_powercount = 0; + p_rf_calibrate_info->is_txpowertracking_init = _FALSE; + + if (*(p_dm_odm->p_mp_mode) == false) + p_rf_calibrate_info->txpowertrack_control = _TRUE; + else + p_rf_calibrate_info->txpowertrack_control = _FALSE; + + if (*(p_dm_odm->p_mp_mode) == false) + p_rf_calibrate_info->txpowertrack_control = _TRUE; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("p_dm_odm txpowertrack_control = %d\n", p_rf_calibrate_info->txpowertrack_control)); + +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#ifdef RTL8188E_SUPPORT + { + p_rf_calibrate_info->is_txpowertracking = _TRUE; + p_rf_calibrate_info->tx_powercount = 0; + p_rf_calibrate_info->is_txpowertracking_init = _FALSE; + p_rf_calibrate_info->txpowertrack_control = _TRUE; + } +#endif +#endif + + /* p_dm_odm->rf_calibrate_info.txpowertrack_control = true; */ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + p_rf_calibrate_info->thermal_value = rtlefu->eeprom_thermalmeter; + p_rf_calibrate_info->thermal_value_iqk = rtlefu->eeprom_thermalmeter; + p_rf_calibrate_info->thermal_value_lck = rtlefu->eeprom_thermalmeter; +#else + p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter; + p_rf_calibrate_info->thermal_value_iqk = p_hal_data->eeprom_thermal_meter; + p_rf_calibrate_info->thermal_value_lck = p_hal_data->eeprom_thermal_meter; +#endif + + if (p_rf_calibrate_info->default_bb_swing_index_flag != true) { + /*The index of "0 dB" in SwingTable.*/ + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B || + p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8703B) { + p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index; + p_rf_calibrate_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index; + } else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ + p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + p_rf_calibrate_info->default_cck_index = 20; /*CCK:-6dB*/ + } else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ + p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/ + } else if (p_dm_odm->support_ic_type == ODM_RTL8710B) { /* JJ ADD 20161014 */ + p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/ + } else { + p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index; + p_rf_calibrate_info->default_cck_index = 24; + } + p_rf_calibrate_info->default_bb_swing_index_flag = true; + } + + p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index; + p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->default_cck_index; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) { + p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->delta_power_index[p] = 0; + p_rf_calibrate_info->delta_power_index_last[p] = 0; + p_rf_calibrate_info->power_index_offset[p] = 0; + } + p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; + p_rf_calibrate_info->modify_tx_agc_value_cck = 0; + +} + + +void +odm_txpowertracking_check( + void *p_dm_void +) +{ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + at the same time. In the stage2/3, we need to prive universal interface and merge all + HW dynamic mechanism. */ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + switch (p_dm_odm->support_platform) { + case ODM_WIN: + odm_txpowertracking_check_mp(p_dm_odm); + break; + + case ODM_CE: + odm_txpowertracking_check_ce(p_dm_odm); + break; + + case ODM_AP: + odm_txpowertracking_check_ap(p_dm_odm); + break; + + default: + break; + } + +} + +void +odm_txpowertracking_check_ce( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct _ADAPTER *adapter = p_dm_odm->adapter; + + + if (!(p_rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + return; + + if (!p_dm_odm->rf_calibrate_info.tm_trigger) { + + if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8192E(adapter) + || IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8814A(adapter) + || IS_HARDWARE_TYPE_8703B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8822B(adapter) + || IS_HARDWARE_TYPE_8821C(adapter) || (p_dm_odm->support_ic_type == ODM_RTL8710B) + )/* JJ ADD 20161014 */ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03); + else + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60); + + + + p_dm_odm->rf_calibrate_info.tm_trigger = 1; + return; + } else { + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + odm_txpowertracking_callback_thermal_meter(p_dm_odm); +#else + odm_txpowertracking_callback_thermal_meter(adapter); +#endif + p_dm_odm->rf_calibrate_info.tm_trigger = 0; + } + +#endif +} + +void +odm_txpowertracking_check_mp( + void *p_dm_void +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + + if (odm_check_power_status(adapter) == false) { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>odm_check_power_status() return false\n")); + return; + } + + odm_txpowertracking_thermal_meter_check(adapter); +#endif + +} + + +void +odm_txpowertracking_check_ap( + void *p_dm_void +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct rtl8192cd_priv *priv = p_dm_odm->priv; + + return; + +#endif +} diff --git a/hal/phydm/halrf/halrf_powertracking_ce.h b/hal/phydm/halrf/halrf_powertracking_ce.h new file mode 100644 index 0000000..c3d4fe0 --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_ce.h @@ -0,0 +1,347 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define HALRF_POWRTRACKING_VER "1.1" + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define OFDM_TABLE_SIZE 43 +#define CCK_TABLE_SIZE 33 +#define CCK_TABLE_SIZE_88F 21 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 +/* JJ ADD 20161014 */ +#define CCK_TABLE_SIZE_8710B 41 + +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define DELTA_SWINTSSI_SIZE 61 +#define BAND_NUM 4 + +#define AVG_THERMAL_NUM 8 +#define HP_THERMAL_NUM 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 + +#define IQK_BB_REG_NUM 9 + + + +#define iqk_matrix_reg_num 8 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#else +#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */ +#endif + +extern u32 ofdm_swing_table[OFDM_TABLE_SIZE]; +extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8]; + +extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE]; +extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16]; +extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16]; +extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16]; +extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D]; +/* JJ ADD 20161014 */ +extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B]; + +extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE]; + +/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#else +static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; +#endif + +#define dm_check_txpowertracking odm_txpowertracking_check + +struct _IQK_MATRIX_REGS_SETTING { + boolean is_iqk_done; + s32 value[3][iqk_matrix_reg_num]; + boolean is_bw_iqk_result_saved[3]; +}; + +struct odm_rf_calibration_structure { + /* for tx power tracking */ + + u32 rega24; /* for TempCCK */ + s32 rege94; + s32 rege9c; + s32 regeb4; + s32 regebc; + + u8 tx_powercount; + boolean is_txpowertracking_init; + boolean is_txpowertracking; + u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */ + u8 tm_trigger; + u8 internal_pa_5g[2]; /* pathA / pathB */ + + u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */ + u8 thermal_value; + u8 thermal_value_lck; + u8 thermal_value_iqk; + s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */ + u8 thermal_value_dpk; + u8 thermal_value_avg[AVG_THERMAL_NUM]; + u8 thermal_value_avg_index; + u8 thermal_value_rx_gain; + u8 thermal_value_crystal; + u8 thermal_value_dpk_store; + u8 thermal_value_dpk_track; + boolean txpowertracking_in_progress; + + boolean is_reloadtxpowerindex; + u8 is_rf_pi_enable; + u32 txpowertracking_callback_cnt; /* cosa add for debug */ + + + /* ------------------------- Tx power Tracking ------------------------- */ + u8 is_cck_in_ch14; + u8 CCK_index; + u8 OFDM_index[MAX_RF_PATH]; + s8 power_index_offset[MAX_RF_PATH]; + s8 delta_power_index[MAX_RF_PATH]; + s8 delta_power_index_last[MAX_RF_PATH]; + boolean is_tx_power_changed; + s8 xtal_offset; + s8 xtal_offset_last; + + u8 thermal_value_hp[HP_THERMAL_NUM]; + u8 thermal_value_hp_index; + struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; + u8 delta_lck; + s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */ + u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE]; + + u8 bb_swing_idx_ofdm[MAX_RF_PATH]; + u8 bb_swing_idx_ofdm_current; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + u8 bb_swing_idx_ofdm_base[MAX_RF_PATH]; +#else + u8 bb_swing_idx_ofdm_base; +#endif + boolean default_bb_swing_index_flag; + boolean bb_swing_flag_ofdm; + u8 bb_swing_idx_cck; + u8 bb_swing_idx_cck_current; + u8 bb_swing_idx_cck_base; + u8 default_ofdm_index; + u8 default_cck_index; + boolean bb_swing_flag_cck; + + s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; + s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; + s8 absolute_cck_swing_idx[MAX_RF_PATH]; + s8 remnant_cck_swing_idx; + s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */ + boolean modify_tx_agc_flag_path_a; + boolean modify_tx_agc_flag_path_b; + boolean modify_tx_agc_flag_path_c; + boolean modify_tx_agc_flag_path_d; + boolean modify_tx_agc_flag_path_a_cck; + + s8 kfree_offset[MAX_RF_PATH]; + + /* -------------------------------------------------------------------- */ + + /* for IQK */ + u32 regc04; + u32 reg874; + u32 regc08; + u32 regb68; + u32 regb6c; + u32 reg870; + u32 reg860; + u32 reg864; + + boolean is_iqk_initialized; + boolean is_lck_in_progress; + boolean is_antenna_detected; + boolean is_need_iqk; + boolean is_iqk_in_progress; + boolean is_iqk_pa_off; + u8 delta_iqk; + u32 ADDA_backup[IQK_ADDA_REG_NUM]; + u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; + u32 IQK_BB_backup_recover[9]; + u32 IQK_BB_backup[IQK_BB_REG_NUM]; + u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + /* JJ ADD 20161014 */ + u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + u8 iqk_step; + u8 kcount; + u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ + boolean is_mp_mode; + + + + /* IQK time measurement */ + u64 iqk_start_time; + u64 iqk_progressing_time; + u64 iqk_total_progressing_time; + + u32 lok_result; + + /* for APK */ + u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */ + u8 is_ap_kdone; + u8 is_apk_thermal_meter_ignore; + + /* DPK */ + boolean is_dpk_fail; + u8 is_dp_done; + u8 is_dp_path_aok; + u8 is_dp_path_bok; + + u32 tx_lok[2]; + u32 dpk_tx_agc; + s32 dpk_gain; + u32 dpk_thermal[4]; + s8 modify_tx_agc_value_ofdm; + s8 modify_tx_agc_value_cck; + + /*Add by Yuchen for Kfree Phydm*/ + u8 reg_rf_kfree_enable; /*for registry*/ + u8 rf_kfree_enable; /*for efuse enable check*/ + +}; + + +void +odm_txpowertracking_check( + void *p_dm_void +); + + +void +odm_txpowertracking_init( + void *p_dm_void +); + +void +odm_txpowertracking_check_ap( + void *p_dm_void +); + +void +odm_txpowertracking_thermal_meter_init( + void *p_dm_void +); + +void +odm_txpowertracking_init( + void *p_dm_void +); + +void +odm_txpowertracking_check_mp( + void *p_dm_void +); + + +void +odm_txpowertracking_check_ce( + void *p_dm_void +); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +void +odm_txpowertracking_callback_thermal_meter92c( + struct _ADAPTER *adapter +); + +void +odm_txpowertracking_callback_rx_gain_thermal_meter92d( + struct _ADAPTER *adapter +); + +void +odm_txpowertracking_callback_thermal_meter92d( + struct _ADAPTER *adapter +); + +void +odm_txpowertracking_direct_call92c( + struct _ADAPTER *adapter +); + +void +odm_txpowertracking_thermal_meter_check( + struct _ADAPTER *adapter +); + +#endif + +#endif diff --git a/hal/phydm/halrf/halrf_powertracking_win.c b/hal/phydm/halrf/halrf_powertracking_win.c new file mode 100644 index 0000000..ba11f51 --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_win.c @@ -0,0 +1,811 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/*============================================================ */ +/* include files */ +/*============================================================ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/* ************************************************************ + * Global var + * ************************************************************ */ + +u32 ofdm_swing_table[OFDM_TABLE_SIZE] = { + 0x7f8001fe, /* 0, +6.0dB */ + 0x788001e2, /* 1, +5.5dB */ + 0x71c001c7, /* 2, +5.0dB */ + 0x6b8001ae, /* 3, +4.5dB */ + 0x65400195, /* 4, +4.0dB */ + 0x5fc0017f, /* 5, +3.5dB */ + 0x5a400169, /* 6, +3.0dB */ + 0x55400155, /* 7, +2.5dB */ + 0x50800142, /* 8, +2.0dB */ + 0x4c000130, /* 9, +1.5dB */ + 0x47c0011f, /* 10, +1.0dB */ + 0x43c0010f, /* 11, +0.5dB */ + 0x40000100, /* 12, +0dB */ + 0x3c8000f2, /* 13, -0.5dB */ + 0x390000e4, /* 14, -1.0dB */ + 0x35c000d7, /* 15, -1.5dB */ + 0x32c000cb, /* 16, -2.0dB */ + 0x300000c0, /* 17, -2.5dB */ + 0x2d4000b5, /* 18, -3.0dB */ + 0x2ac000ab, /* 19, -3.5dB */ + 0x288000a2, /* 20, -4.0dB */ + 0x26000098, /* 21, -4.5dB */ + 0x24000090, /* 22, -5.0dB */ + 0x22000088, /* 23, -5.5dB */ + 0x20000080, /* 24, -6.0dB */ + 0x1e400079, /* 25, -6.5dB */ + 0x1c800072, /* 26, -7.0dB */ + 0x1b00006c, /* 27. -7.5dB */ + 0x19800066, /* 28, -8.0dB */ + 0x18000060, /* 29, -8.5dB */ + 0x16c0005b, /* 30, -9.0dB */ + 0x15800056, /* 31, -9.5dB */ + 0x14400051, /* 32, -10.0dB */ + 0x1300004c, /* 33, -10.5dB */ + 0x12000048, /* 34, -11.0dB */ + 0x11000044, /* 35, -11.5dB */ + 0x10000040, /* 36, -12.0dB */ +}; + +u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ +}; + + +u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ +}; + + +u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = { + 0x0b40002d, /* 0, -15.0dB */ + 0x0c000030, /* 1, -14.5dB */ + 0x0cc00033, /* 2, -14.0dB */ + 0x0d800036, /* 3, -13.5dB */ + 0x0e400039, /* 4, -13.0dB */ + 0x0f00003c, /* 5, -12.5dB */ + 0x10000040, /* 6, -12.0dB */ + 0x11000044, /* 7, -11.5dB */ + 0x12000048, /* 8, -11.0dB */ + 0x1300004c, /* 9, -10.5dB */ + 0x14400051, /* 10, -10.0dB */ + 0x15800056, /* 11, -9.5dB */ + 0x16c0005b, /* 12, -9.0dB */ + 0x18000060, /* 13, -8.5dB */ + 0x19800066, /* 14, -8.0dB */ + 0x1b00006c, /* 15, -7.5dB */ + 0x1c800072, /* 16, -7.0dB */ + 0x1e400079, /* 17, -6.5dB */ + 0x20000080, /* 18, -6.0dB */ + 0x22000088, /* 19, -5.5dB */ + 0x24000090, /* 20, -5.0dB */ + 0x26000098, /* 21, -4.5dB */ + 0x288000a2, /* 22, -4.0dB */ + 0x2ac000ab, /* 23, -3.5dB */ + 0x2d4000b5, /* 24, -3.0dB */ + 0x300000c0, /* 25, -2.5dB */ + 0x32c000cb, /* 26, -2.0dB */ + 0x35c000d7, /* 27, -1.5dB */ + 0x390000e4, /* 28, -1.0dB */ + 0x3c8000f2, /* 29, -0.5dB */ + 0x40000100, /* 30, +0dB */ + 0x43c0010f, /* 31, +0.5dB */ + 0x47c0011f, /* 32, +1.0dB */ + 0x4c000130, /* 33, +1.5dB */ + 0x50800142, /* 34, +2.0dB */ + 0x55400155, /* 35, +2.5dB */ + 0x5a400169, /* 36, +3.0dB */ + 0x5fc0017f, /* 37, +3.5dB */ + 0x65400195, /* 38, +4.0dB */ + 0x6b8001ae, /* 39, +4.5dB */ + 0x71c001c7, /* 40, +5.0dB */ + 0x788001e2, /* 41, +5.5dB */ + 0x7f8001fe /* 42, +6.0dB */ +}; + + +u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */ +}; + + +u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ +}; +u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = { + 0x0CD, + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; +/* JJ ADD 20161014 */ +u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, /*19*/ + 0x287, /*20*/ + 0x2AE, /*21*/ + 0x2D6, /*22*/ + 0x301, /*23*/ + 0x32F, /*24*/ + 0x35F, /*25*/ + 0x392, /*26*/ + 0x3C9, /*27*/ + 0x402, /*28*/ + 0x43F, /*29*/ + 0x47F, /*30*/ + 0x4C3, /*31*/ + 0x50C, /*32*/ + 0x558, /*33*/ + 0x5A9, /*34*/ + 0x5FF, /*35*/ + 0x65A, /*36*/ + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + + +u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = { + 0x081, /* 0, -12.0dB */ + 0x088, /* 1, -11.5dB */ + 0x090, /* 2, -11.0dB */ + 0x099, /* 3, -10.5dB */ + 0x0A2, /* 4, -10.0dB */ + 0x0AC, /* 5, -9.5dB */ + 0x0B6, /* 6, -9.0dB */ + 0x0C0, /* 7, -8.5dB */ + 0x0CC, /* 8, -8.0dB */ + 0x0D8, /* 9, -7.5dB */ + 0x0E5, /* 10, -7.0dB */ + 0x0F2, /* 11, -6.5dB */ + 0x101, /* 12, -6.0dB */ + 0x110, /* 13, -5.5dB */ + 0x120, /* 14, -5.0dB */ + 0x131, /* 15, -4.5dB */ + 0x143, /* 16, -4.0dB */ + 0x156, /* 17, -3.5dB */ + 0x16A, /* 18, -3.0dB */ + 0x180, /* 19, -2.5dB */ + 0x197, /* 20, -2.0dB */ + 0x1AF, /* 21, -1.5dB */ + 0x1C8, /* 22, -1.0dB */ + 0x1E3, /* 23, -0.5dB */ + 0x200, /* 24, +0 dB */ + 0x21E, /* 25, +0.5dB */ + 0x23E, /* 26, +1.0dB */ + 0x261, /* 27, +1.5dB */ + 0x285, /* 28, +2.0dB */ + 0x2AB, /* 29, +2.5dB */ + 0x2D3, /* 30, +3.0dB */ + 0x2FE, /* 31, +3.5dB */ + 0x32B, /* 32, +4.0dB */ + 0x35C, /* 33, +4.5dB */ + 0x38E, /* 34, +5.0dB */ + 0x3C4, /* 35, +5.5dB */ + 0x3FE /* 36, +6.0dB */ +}; + +void +odm_txpowertracking_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if (!(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B))) + return; +#endif + + odm_txpowertracking_thermal_meter_init(p_dm_odm); +} + +u8 +get_swing_index( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + u8 i = 0; + u32 bb_swing; + u32 swing_table_size; + u32 *p_swing_table; + + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B || + p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B) { + bb_swing = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000); + + p_swing_table = ofdm_swing_table_new; + swing_table_size = OFDM_TABLE_SIZE; + } else { + bb_swing = PHY_GetTxBBSwing_8812A(adapter, p_hal_data->CurrentBandType, ODM_RF_PATH_A); + p_swing_table = tx_scaling_table_jaguar; + swing_table_size = TXSCALE_TABLE_SIZE; + } + + for (i = 0; i < swing_table_size; ++i) { + u32 table_value = p_swing_table[i]; + + if (table_value >= 0x100000) + table_value >>= 22; + if (bb_swing == table_value) + break; + } + return i; +} + +u8 +get_cck_swing_index( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + u8 i = 0; + u32 bb_cck_swing; + + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B || + p_dm_odm->support_ic_type == ODM_RTL8192E) { + bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22); + + for (i = 0; i < CCK_TABLE_SIZE; i++) { + if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0]) + break; + } + } else if (p_dm_odm->support_ic_type == ODM_RTL8703B) { + bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22); + + for (i = 0; i < CCK_TABLE_SIZE_88F; i++) { + if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0]) + break; + } + } + + return i; +} + + +void +odm_txpowertracking_thermal_meter_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 default_swing_index = get_swing_index(p_dm_odm); + u8 default_cck_swing_index = get_cck_swing_index(p_dm_odm); + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + u8 p = 0; + + if (*(p_dm_odm->p_mp_mode) == false) + p_rf_calibrate_info->txpowertrack_control = true; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#ifdef CONFIG_RTL8188E + { + p_rf_calibrate_info->is_txpowertracking = _TRUE; + p_rf_calibrate_info->tx_powercount = 0; + p_rf_calibrate_info->is_txpowertracking_init = _FALSE; + + if (*(p_dm_odm->p_mp_mode) == false) + p_rf_calibrate_info->txpowertrack_control = _TRUE; + + MSG_8192C("p_dm_odm txpowertrack_control = %d\n", p_rf_calibrate_info->txpowertrack_control); + } +#else + { + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct dm_priv *pdmpriv = &p_hal_data->dmpriv; + + pdmpriv->is_txpowertracking = _TRUE; + pdmpriv->tx_powercount = 0; + pdmpriv->is_txpowertracking_init = _FALSE; + + if (*(p_dm_odm->p_mp_mode) == false) + pdmpriv->txpowertrack_control = _TRUE; + + MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control); + + } +#endif +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#ifdef RTL8188E_SUPPORT + { + p_rf_calibrate_info->is_txpowertracking = _TRUE; + p_rf_calibrate_info->tx_powercount = 0; + p_rf_calibrate_info->is_txpowertracking_init = _FALSE; + p_rf_calibrate_info->txpowertrack_control = _TRUE; + } +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if (MP_DRIVER == 1) + p_rf_calibrate_info->txpowertrack_control = false; +#else + p_rf_calibrate_info->txpowertrack_control = true; +#endif +#else + p_rf_calibrate_info->txpowertrack_control = true; +#endif + + p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter; + p_rf_calibrate_info->thermal_value_iqk = p_hal_data->eeprom_thermal_meter; + p_rf_calibrate_info->thermal_value_lck = p_hal_data->eeprom_thermal_meter; + + if (p_rf_calibrate_info->default_bb_swing_index_flag != true) { + /*The index of "0 dB" in SwingTable.*/ + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B || + p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8703B) { + p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index; + p_rf_calibrate_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index; + } else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ + p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + p_rf_calibrate_info->default_cck_index = 20; /*CCK:-6dB*/ + } else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ + p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/ + /* JJ ADD 20161014 */ + } else if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/ + } else { + p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index; + p_rf_calibrate_info->default_cck_index = 24; + } + p_rf_calibrate_info->default_bb_swing_index_flag = true; + } + + p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index; + p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->default_cck_index; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) { + p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->delta_power_index[p] = 0; + p_rf_calibrate_info->delta_power_index_last[p] = 0; + p_rf_calibrate_info->power_index_offset[p] = 0; + p_rf_calibrate_info->kfree_offset[p] = 0; + } + p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; + p_rf_calibrate_info->modify_tx_agc_value_cck = 0; + +} + + +void +odm_txpowertracking_check( + void *p_dm_void +) +{ + +#if 0 + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ +#endif + + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + switch (p_dm_odm->support_platform) { + case ODM_WIN: + odm_txpowertracking_check_mp(p_dm_odm); + break; + + case ODM_CE: + odm_txpowertracking_check_ce(p_dm_odm); + break; + + case ODM_AP: + odm_txpowertracking_check_ap(p_dm_odm); + break; + + default: + break; + } + +} + +void +odm_txpowertracking_check_ce( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct _ADAPTER *adapter = p_dm_odm->adapter; +#if ((RTL8188F_SUPPORT == 1)) + rtl8192c_odm_check_txpowertracking(adapter); +#endif + +#if (RTL8188E_SUPPORT == 1) + + if (!(p_rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + return; + + if (!p_rf_calibrate_info->tm_trigger) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60); + /*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/ + + p_rf_calibrate_info->tm_trigger = 1; + return; + + } else { + /*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/ + odm_txpowertracking_callback_thermal_meter_8188e(adapter); + p_rf_calibrate_info->tm_trigger = 0; + } +#endif +#endif +} + +void +odm_txpowertracking_check_mp( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _ADAPTER *adapter = p_dm_odm->adapter; + + if (*p_dm_odm->p_is_fcs_mode_enable) + return; + + if (odm_check_power_status(adapter) == false) { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>odm_check_power_status() return false\n")); + return; + } + + if (IS_HARDWARE_TYPE_8821B(adapter)) /* TODO: Don't Do PowerTracking*/ + return; + + odm_txpowertracking_thermal_meter_check(adapter); + + +#endif + +} + + +void +odm_txpowertracking_check_ap( + void *p_dm_void +) +{ + return; + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void +odm_txpowertracking_direct_call( + struct _ADAPTER *adapter +) +{ + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + + odm_txpowertracking_callback_thermal_meter(adapter); +} + +void +odm_txpowertracking_thermal_meter_check( + struct _ADAPTER *adapter +) +{ + static u8 tm_trigger = 0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &(pHalData->DM_OutSrc); + struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + + if (!(p_rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, + ("===>odm_txpowertracking_thermal_meter_check(),p_mgnt_info->is_txpowertracking is false, return!!\n")); + return; + } + + if (!tm_trigger) { + if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) || + IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter) + || IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter))/* JJ ADD 20161014 */ + PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03); + else + PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60); + + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n")); + + tm_trigger = 1; + return; + } else { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n")); + odm_txpowertracking_direct_call(adapter); + tm_trigger = 0; + } +} + +#endif diff --git a/hal/phydm/halrf/halrf_powertracking_win.h b/hal/phydm/halrf/halrf_powertracking_win.h new file mode 100644 index 0000000..88356c4 --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_win.h @@ -0,0 +1,310 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define HALRF_POWRTRACKING_VER "1.1" + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define TXSCALE_TABLE_SIZE 37 +#define OFDM_TABLE_SIZE 43 +#define CCK_TABLE_SIZE 33 +#define CCK_TABLE_SIZE_8723D 41 +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define DELTA_SWINTSSI_SIZE 61 +#define BAND_NUM 3 +#define MAX_RF_PATH 4 +#define CCK_TABLE_SIZE_88F 21 +/* JJ ADD 20161014 */ +#define CCK_TABLE_SIZE_8710B 41 + + +#define dm_check_txpowertracking odm_txpowertracking_check + +#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */ +#define AVG_THERMAL_NUM 8 +#define HP_THERMAL_NUM 8 +#define iqk_matrix_reg_num 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 + +#define IQK_BB_REG_NUM 9 + + +extern u32 ofdm_swing_table[OFDM_TABLE_SIZE]; +extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8]; + +extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE]; +extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16]; +extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16]; +extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16]; +extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D]; +/* JJ ADD 20161014 */ +extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B]; + +extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE]; + +/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */ +static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +void +odm_txpowertracking_check( + void *p_dm_void +); + +void +odm_txpowertracking_check_ap( + void *p_dm_void +); + +void +odm_txpowertracking_thermal_meter_init( + void *p_dm_void +); + +void +odm_txpowertracking_init( + void *p_dm_void +); + +void +odm_txpowertracking_check_mp( + void *p_dm_void +); + + +void +odm_txpowertracking_check_ce( + void *p_dm_void +); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + + +void +odm_txpowertracking_thermal_meter_check( + struct _ADAPTER *adapter +); + +#endif + +struct _IQK_MATRIX_REGS_SETTING { + boolean is_iqk_done; + s32 value[3][iqk_matrix_reg_num]; + boolean is_bw_iqk_result_saved[3]; +}; + +struct odm_rf_calibration_structure { + /* for tx power tracking */ + + u32 rega24; /* for TempCCK */ + s32 rege94; + s32 rege9c; + s32 regeb4; + s32 regebc; + /* u8 is_txpowertracking; */ + u8 tx_powercount; + boolean is_txpowertracking_init; + boolean is_txpowertracking; + u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */ + u8 tm_trigger; + u8 internal_pa_5g[2]; /* pathA / pathB */ + + u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */ + u8 thermal_value; + u8 thermal_value_lck; + u8 thermal_value_iqk; + u8 thermal_value_dpk; + s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */ + u8 thermal_value_avg[AVG_THERMAL_NUM]; + u8 thermal_value_avg_index; + u8 thermal_value_rx_gain; + + + boolean is_reloadtxpowerindex; + u8 is_rf_pi_enable; + u32 txpowertracking_callback_cnt; /* cosa add for debug */ + + + /* ------------------------- Tx power Tracking ------------------------- */ + u8 is_cck_in_ch14; + u8 CCK_index; + u8 OFDM_index[MAX_RF_PATH]; + s8 power_index_offset[MAX_RF_PATH]; + s8 delta_power_index[MAX_RF_PATH]; + s8 delta_power_index_last[MAX_RF_PATH]; + boolean is_tx_power_changed; + s8 xtal_offset; + s8 xtal_offset_last; + + u8 thermal_value_hp[HP_THERMAL_NUM]; + u8 thermal_value_hp_index; + struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; + u8 delta_lck; + s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */ + u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE]; + + u8 bb_swing_idx_ofdm[MAX_RF_PATH]; + u8 bb_swing_idx_ofdm_current; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + u8 bb_swing_idx_ofdm_base[MAX_RF_PATH]; +#else + u8 bb_swing_idx_ofdm_base; +#endif + boolean default_bb_swing_index_flag; + boolean bb_swing_flag_ofdm; + u8 bb_swing_idx_cck; + u8 bb_swing_idx_cck_current; + u8 bb_swing_idx_cck_base; + u8 default_ofdm_index; + u8 default_cck_index; + boolean bb_swing_flag_cck; + + s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; + s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; + s8 absolute_cck_swing_idx[MAX_RF_PATH]; + s8 remnant_cck_swing_idx; + s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */ + boolean modify_tx_agc_flag_path_a; + boolean modify_tx_agc_flag_path_b; + boolean modify_tx_agc_flag_path_c; + boolean modify_tx_agc_flag_path_d; + boolean modify_tx_agc_flag_path_a_cck; + + s8 kfree_offset[MAX_RF_PATH]; + + /* -------------------------------------------------------------------- */ + + /* for IQK */ + u32 regc04; + u32 reg874; + u32 regc08; + u32 regb68; + u32 regb6c; + u32 reg870; + u32 reg860; + u32 reg864; + + boolean is_iqk_initialized; + boolean is_lck_in_progress; + boolean is_antenna_detected; + boolean is_need_iqk; + boolean is_iqk_in_progress; + boolean is_iqk_pa_off; + u8 delta_iqk; + u32 ADDA_backup[IQK_ADDA_REG_NUM]; + u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; + u32 IQK_BB_backup_recover[9]; + u32 IQK_BB_backup[IQK_BB_REG_NUM]; + u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + /* JJ ADD 20161014 */ + u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + u64 iqk_start_time; + u64 iqk_total_progressing_time; + u64 iqk_progressing_time; + u32 lok_result; + u8 iqk_step; + u8 kcount; + u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ + boolean is_mp_mode; + + /* for APK */ + u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */ + u8 is_ap_kdone; + u8 is_apk_thermal_meter_ignore; + + /* DPK */ + boolean is_dpk_fail; + u8 is_dp_done; + u8 is_dp_path_aok; + u8 is_dp_path_bok; + + u32 tx_lok[2]; + u32 dpk_tx_agc; + s32 dpk_gain; + u32 dpk_thermal[4]; + + s8 modify_tx_agc_value_ofdm; + s8 modify_tx_agc_value_cck; + + /*Add by Yuchen for Kfree Phydm*/ + u8 reg_rf_kfree_enable; /*for registry*/ + u8 rf_kfree_enable; /*for efuse enable check*/ + + HALMAC_PWR_TRACKING_OPTION HALMAC_PWR_TRACKING_INFO; +}; + + + + +#endif diff --git a/hal/phydm/halrf/rtl8822b/halrf_8822b.c b/hal/phydm/halrf/rtl8822b/halrf_8822b.c new file mode 100644 index 0000000..d22e88c --- /dev/null +++ b/hal/phydm/halrf/rtl8822b/halrf_8822b.c @@ -0,0 +1,590 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#include "../phydm_precomp.h" +#else +#include "../../phydm_precomp.h" +#endif + +#if (RTL8822B_SUPPORT == 1) + +boolean +get_mix_mode_tx_agc_bb_swing_offset_8822b( + void *p_dm_void, + enum pwrtrack_method method, + u8 rf_path, + u8 tx_power_index_offest +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + u8 bb_swing_upper_bound = p_rf_calibrate_info->default_ofdm_index + 10; + u8 bb_swing_lower_bound = 0; + + s8 tx_agc_index = 0; + u8 tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Path_%d p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest=%d\n", + rf_path, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], tx_power_index_offest)); + + if (tx_power_index_offest > 0XF) + tx_power_index_offest = 0XF; + + if (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] >= 0 && p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest) { + tx_agc_index = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]; + tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index; + } else if (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest) { + tx_agc_index = tx_power_index_offest; + p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest; + tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index + p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path]; + + if (tx_bb_swing_index > bb_swing_upper_bound) + tx_bb_swing_index = bb_swing_upper_bound; + } else { + tx_agc_index = 0; + + if (p_rf_calibrate_info->default_ofdm_index > (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] * (-1))) + tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]; + else + tx_bb_swing_index = bb_swing_lower_bound; + + if (tx_bb_swing_index < bb_swing_lower_bound) + tx_bb_swing_index = bb_swing_lower_bound; + } + + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index; + p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("MixMode Offset Path_%d p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]=%d p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]=%d tx_power_index_offest=%d\n", + rf_path, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path], tx_power_index_offest)); + + return true; +} + + +void +odm_tx_pwr_track_set_pwr8822b( + void *p_dm_void, + enum pwrtrack_method method, + u8 rf_path, + u8 channel_mapped_index +) +{ + +#if 0 + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + u8 channel = *p_dm_odm->p_channel; + u8 band_width = p_hal_data->current_channel_bw; + u8 tx_power_index = 0; + u8 tx_rate = 0xFF; + enum rt_status status = RT_STATUS_SUCCESS; + + PHALMAC_PWR_TRACKING_OPTION p_pwr_tracking_opt = &(p_rf_calibrate_info->HALMAC_PWR_TRACKING_INFO); + + if (*(p_dm_odm->p_mp_mode) == true) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx); + + tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx); + + tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index); +#endif +#endif + } else { + u16 rate = *(p_dm_odm->p_forced_data_rate); + + if (!rate) { /*auto rate*/ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (p_dm_odm->number_linked_client != 0) + tx_rate = hw_rate_to_m_rate(p_dm_odm->tx_rate); +#endif + } else /*force rate*/ + tx_rate = (u8) rate; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s tx_rate=0x%X\n", __func__, tx_rate)); + + tx_power_index = phy_get_tx_power_index(adapter, (enum odm_rf_radio_path_e) rf_path, tx_rate, band_width, channel); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("type=%d tx_power_index=%d p_rf_calibrate_info->absolute_ofdm_swing_idx=%d p_rf_calibrate_info->default_ofdm_index=%d rf_path=%d\n", method, tx_power_index, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], p_rf_calibrate_info->default_ofdm_index, rf_path)); + + p_pwr_tracking_opt->type = method; + p_pwr_tracking_opt->bbswing_index = p_rf_calibrate_info->default_ofdm_index; + p_pwr_tracking_opt->pwr_tracking_para[rf_path].enable = 1; + p_pwr_tracking_opt->pwr_tracking_para[rf_path].tx_pwr_index = tx_power_index; + p_pwr_tracking_opt->pwr_tracking_para[rf_path].pwr_tracking_offset_value = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]; + p_pwr_tracking_opt->pwr_tracking_para[rf_path].tssi_value = 0; + + + if (rf_path == (MAX_PATH_NUM_8822B - 1)) { + status = hal_mac_send_power_tracking_info(&GET_HAL_MAC_INFO(adapter), p_pwr_tracking_opt); + + if (status == RT_STATUS_SUCCESS) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("path A 0xC94=0x%X 0xC1C=0x%X\n", + odm_get_bb_reg(p_dm_odm, 0xC94, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), + odm_get_bb_reg(p_dm_odm, 0xC1C, 0xFFE00000) + )); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("path B 0xE94=0x%X 0xE1C=0x%X\n", + odm_get_bb_reg(p_dm_odm, 0xE94, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), + odm_get_bb_reg(p_dm_odm, 0xE1C, 0xFFE00000) + )); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Power Tracking to FW Fail ret code = %d\n", status)); + } + } + +#endif + + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + u8 tx_power_index_offest = 0; + u8 tx_power_index = 0; + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_phy *rtlphy = &(rtlpriv->phy); + u8 channel = rtlphy->current_channel; + u8 band_width = rtlphy->current_chan_bw; +#else + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + u8 channel = *p_dm_odm->p_channel; + u8 band_width = *p_dm_odm->p_band_width; +#endif + u8 tx_rate = 0xFF; + + if (*(p_dm_odm->p_mp_mode) == true) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx); + + tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if (MP_DRIVER == 1) + PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx); + + tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index); +#endif +#endif +#endif + } else { + u16 rate = *(p_dm_odm->p_forced_data_rate); + + if (!rate) { /*auto rate*/ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + tx_rate = p_dm_odm->tx_rate; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (p_dm_odm->number_linked_client != 0) + tx_rate = hw_rate_to_m_rate(p_dm_odm->tx_rate); +#endif + } else /*force rate*/ + tx_rate = (u8) rate; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s tx_rate=0x%X\n", __func__, tx_rate)); + +#endif + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n", p_rf_calibrate_info->default_ofdm_index, p_rf_calibrate_info->default_cck_index)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRF->absolute_ofdm_swing_idx=%d pRF->remnant_ofdm_swing_idx=%d pRF->absolute_cck_swing_idx=%d pRF->remnant_cck_swing_idx=%d rf_path=%d\n", + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path], p_rf_calibrate_info->absolute_cck_swing_idx[rf_path], p_rf_calibrate_info->remnant_cck_swing_idx, rf_path)); + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + tx_power_index = odm_get_tx_power_index(p_dm_odm, (enum odm_rf_radio_path_e) rf_path, tx_rate, (CHANNEL_WIDTH)band_width, channel); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (*(p_dm_odm->p_mp_mode) == true) + tx_power_index = odm_get_tx_power_index(p_dm_odm, (enum odm_rf_radio_path_e) rf_path, tx_rate, (CHANNEL_WIDTH)band_width, channel); + else { + if (p_dm_odm->number_linked_client != 0) + tx_power_index = odm_get_tx_power_index(p_dm_odm, (enum odm_rf_radio_path_e) rf_path, tx_rate, (CHANNEL_WIDTH)band_width, channel); + } +#else + tx_power_index = config_phydm_read_txagc_8822b(p_dm_odm, rf_path, 0x04); /*0x04(TX_AGC_OFDM_6M)*/ +#endif + + if (tx_power_index >= 63) + tx_power_index = 63; + + tx_power_index_offest = 63 - tx_power_index; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("tx_power_index=%d tx_power_index_offest=%d rf_path=%d\n", tx_power_index, tx_power_index_offest, rf_path)); + + if (method == BBSWING) { /*use for mp driver clean power tracking status*/ + switch (rf_path) { + case ODM_RF_PATH_A: + odm_set_bb_reg(p_dm_odm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]); + odm_set_bb_reg(p_dm_odm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]]); + break; + case ODM_RF_PATH_B: + odm_set_bb_reg(p_dm_odm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]); + odm_set_bb_reg(p_dm_odm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]]); + break; + + default: + break; + } + } else if (method == MIX_MODE) { + switch (rf_path) { + case ODM_RF_PATH_A: + get_mix_mode_tx_agc_bb_swing_offset_8822b(p_dm_odm, method, rf_path, tx_power_index_offest); + odm_set_bb_reg(p_dm_odm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]); + odm_set_bb_reg(p_dm_odm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]]); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n", + odm_get_bb_reg(p_dm_odm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))), + odm_get_bb_reg(p_dm_odm, 0xc1c, 0xFFE00000), + p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path], rf_path)); + break; + + case ODM_RF_PATH_B: + get_mix_mode_tx_agc_bb_swing_offset_8822b(p_dm_odm, method, rf_path, tx_power_index_offest); + odm_set_bb_reg(p_dm_odm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]); + odm_set_bb_reg(p_dm_odm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]]); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC(0xE94)=0x%x BBSwing(0xe1c)=0x%x BBSwingIndex=%d rf_path=%d\n", + odm_get_bb_reg(p_dm_odm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))), + odm_get_bb_reg(p_dm_odm, 0xe1c, 0xFFE00000), + p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path], rf_path)); + break; + + default: + break; + } + } +} + + +void +get_delta_swing_table_8822b( + void *p_dm_void, +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + u8 **temperature_up_a, + u8 **temperature_down_a, + u8 **temperature_up_b, + u8 **temperature_down_b, + u8 **temperature_up_cck_a, + u8 **temperature_down_cck_a, + u8 **temperature_up_cck_b, + u8 **temperature_down_cck_b +#else + u8 **temperature_up_a, + u8 **temperature_down_a, + u8 **temperature_up_b, + u8 **temperature_down_b +#endif +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + u8 channel = *(p_dm_odm->p_channel); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_phy *rtlphy = &(rtlpriv->phy); + u8 channel = rtlphy->current_channel; +#else + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + u8 channel = *p_dm_odm->p_channel; +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + *temperature_up_cck_a = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p; + *temperature_down_cck_a = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n; + *temperature_up_cck_b = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p; + *temperature_down_cck_b = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n; +#endif + + *temperature_up_a = p_rf_calibrate_info->delta_swing_table_idx_2ga_p; + *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_2ga_n; + *temperature_up_b = p_rf_calibrate_info->delta_swing_table_idx_2gb_p; + *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_2gb_n; + + if (36 <= channel && channel <= 64) { + *temperature_up_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[0]; + *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[0]; + *temperature_up_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[0]; + *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[0]; + } else if (100 <= channel && channel <= 144) { + *temperature_up_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[1]; + *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[1]; + *temperature_up_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[1]; + *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[1]; + } else if (149 <= channel && channel <= 177) { + *temperature_up_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[2]; + *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[2]; + *temperature_up_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[2]; + *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[2]; + } +} + + +void +_phy_lc_calibrate_8822b( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 lc_cal = 0, cnt = 0,tmp0xc00, tmp0xe00; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK start!!!!!!!\n")); + tmp0xc00 = odm_read_4byte(p_dm_odm, 0xc00); + tmp0xe00 = odm_read_4byte(p_dm_odm, 0xe00); + odm_write_4byte(p_dm_odm, 0xc00, 0x4); + odm_write_4byte(p_dm_odm, 0xe00, 0x4); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, bRFRegOffsetMask, 0x10000); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0, bRFRegOffsetMask, 0x10000); + /*backup RF0x18*/ + lc_cal = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK); + /*disable RTK*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xc4, RFREGOFFSETMASK, 0x01402); + /*Start LCK*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000); + ODM_delay_ms(100); + for (cnt = 0; cnt < 100; cnt++) { + if (odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) + break; + ODM_delay_ms(10); + } + /*Recover channel number*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal); + /*enable RTK*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xc4, RFREGOFFSETMASK, 0x81402); + /**restore*/ + odm_write_4byte(p_dm_odm, 0xc00, tmp0xc00); + odm_write_4byte(p_dm_odm, 0xe00, tmp0xe00); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, bRFRegOffsetMask, 0x3ffff); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0, bRFRegOffsetMask, 0x3ffff); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK end!!!!!!!\n")); +} + +/*LCK VERSION:0x1*/ +void +phy_lc_calibrate_8822b( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + boolean is_start_cont_tx = false, is_single_tone = false, is_carrier_suppression = false; + u64 start_time; + u64 progressing_time; + + struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +#if (MP_DRIVER == 1) + struct _ADAPTER *p_adapter = p_dm_odm->adapter; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT p_mpt_ctx = &(p_adapter->MptCtx); + is_start_cont_tx = p_mpt_ctx->bStartContTx; + is_single_tone = p_mpt_ctx->bSingleTone; + is_carrier_suppression = p_mpt_ctx->bCarrierSuppression; +#else + PMPT_CONTEXT p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx); + is_start_cont_tx = p_mpt_ctx->is_start_cont_tx; + is_single_tone = p_mpt_ctx->is_single_tone; + is_carrier_suppression = p_mpt_ctx->is_carrier_suppression; +#endif +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(p_rf->rf_supportability & HAL_RF_LCK)) + return; +#endif + + if (is_start_cont_tx || is_single_tone || is_carrier_suppression) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]continues TX ing !!! LCK return\n")); + return; + } + + while (*(p_dm_odm->p_is_scan_in_process)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]scan is in process, bypass LCK\n")); + return; + } + + start_time = odm_get_current_time(p_dm_odm); + p_dm_odm->rf_calibrate_info.is_lck_in_progress = true; + _phy_lc_calibrate_8822b(p_dm_odm); + p_dm_odm->rf_calibrate_info.is_lck_in_progress = false; + progressing_time = odm_get_progressing_time(p_dm_odm, start_time); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK progressing_time = %lld\n", progressing_time)); +} + + + +void configure_txpower_track_8822b( + struct _TXPWRTRACK_CFG *p_config +) +{ + p_config->swing_table_size_cck = TXSCALE_TABLE_SIZE; + p_config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE; + p_config->threshold_iqk = IQK_THRESHOLD; + p_config->threshold_dpk = DPK_THRESHOLD; + p_config->average_thermal_num = AVG_THERMAL_NUM_8822B; + p_config->rf_path_count = MAX_PATH_NUM_8822B; + p_config->thermal_reg_addr = RF_T_METER_8822B; + + p_config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8822b; + p_config->do_iqk = do_iqk_8822b; + p_config->phy_lc_calibrate = phy_lc_calibrate_8822b; + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + p_config->get_delta_all_swing_table = get_delta_swing_table_8822b; +#else + p_config->get_delta_swing_table = get_delta_swing_table_8822b; +#endif +} + + +void phy_set_rf_path_switch_8822b( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + struct PHY_DM_STRUCT *p_dm_odm, +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct PHY_DM_STRUCT *p_dm_odm, +#else + struct _ADAPTER *p_adapter, +#endif + boolean is_main +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#elif !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; +#endif +#endif + + /*BY SY Request */ + odm_set_bb_reg(p_dm_odm, 0x4C, (BIT(24) | BIT(23)), 0x2); + + odm_set_bb_reg(p_dm_odm, 0x974, 0xff, 0xff); + + /*odm_set_bb_reg(p_dm_odm, 0x1991, 0x3, 0x0);*/ + odm_set_bb_reg(p_dm_odm, 0x1990, (BIT(9) | BIT(8)), 0x0); + + /*odm_set_bb_reg(p_dm_odm, 0xCBE, 0x8, 0x0);*/ + odm_set_bb_reg(p_dm_odm, 0xCBC, BIT(19), 0x0); + + odm_set_bb_reg(p_dm_odm, 0xCB4, 0xff, 0x77); + + odm_set_bb_reg(p_dm_odm, 0x70, MASKBYTE3, 0x0e); + odm_set_bb_reg(p_dm_odm, 0x1704, MASKDWORD, 0x0000ff00); + odm_set_bb_reg(p_dm_odm, 0x1700, MASKDWORD, 0xc00f0038); + + if (is_main) { + /*odm_set_bb_reg(p_dm_odm, 0xCBD, 0x3, 0x2); WiFi */ + odm_set_bb_reg(p_dm_odm, 0xCBC, (BIT(9) | BIT(8)), 0x2); /*WiFi */ + } else { + /*odm_set_bb_reg(p_dm_odm, 0xCBD, 0x3, 0x1); BT*/ + odm_set_bb_reg(p_dm_odm, 0xCBC, (BIT(9) | BIT(8)), 0x1); /*BT*/ + } +} + +boolean +_phy_query_rf_path_switch_8822b( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + struct PHY_DM_STRUCT *p_dm_odm +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct PHY_DM_STRUCT *p_dm_odm +#else + struct _ADAPTER *p_adapter +#endif +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#elif !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; +#endif +#endif + + if (odm_get_bb_reg(p_dm_odm, 0xCBC, (BIT(9) | BIT(8))) == 0x2) /*WiFi */ + return true; + else + return false; +} + + +boolean phy_query_rf_path_switch_8822b( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + struct PHY_DM_STRUCT *p_dm_odm +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct PHY_DM_STRUCT *p_dm_odm +#else + struct _ADAPTER *p_adapter +#endif +) +{ + +#if DISABLE_BB_RF + return true; +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + return _phy_query_rf_path_switch_8822b(p_dm_odm); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + return _phy_query_rf_path_switch_8822b(p_dm_odm); +#else + return _phy_query_rf_path_switch_8822b(p_adapter); +#endif +} + + +#endif /* (RTL8822B_SUPPORT == 0)*/ diff --git a/hal/phydm/halrf/rtl8822b/halrf_8822b.h b/hal/phydm/halrf/rtl8822b/halrf_8822b.h new file mode 100644 index 0000000..a0fce9d --- /dev/null +++ b/hal/phydm/halrf/rtl8822b/halrf_8822b.h @@ -0,0 +1,80 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8822B_H__ +#define __HAL_PHY_RF_8822B_H__ + +#define AVG_THERMAL_NUM_8822B 4 +#define RF_T_METER_8822B 0x42 + +#define LCK_VERSION "0x2" + + +void configure_txpower_track_8822b( + struct _TXPWRTRACK_CFG *p_config +); + +void +odm_tx_pwr_track_set_pwr8822b( + void *p_dm_void, + enum pwrtrack_method method, + u8 rf_path, + u8 channel_mapped_index +); + +void +get_delta_swing_table_8822b( + void *p_dm_void, +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + u8 **temperature_up_a, + u8 **temperature_down_a, + u8 **temperature_up_b, + u8 **temperature_down_b, + u8 **temperature_up_cck_a, + u8 **temperature_down_cck_a, + u8 **temperature_up_cck_b, + u8 **temperature_down_cck_b +#else + u8 **temperature_up_a, + u8 **temperature_down_a, + u8 **temperature_up_b, + u8 **temperature_down_b +#endif +); + +void +phy_lc_calibrate_8822b( + void *p_dm_void +); + + + +void phy_set_rf_path_switch_8822b( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + struct PHY_DM_STRUCT *p_dm_odm, +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct PHY_DM_STRUCT *p_dm_odm, +#else + struct _ADAPTER *p_adapter, +#endif + boolean is_main +); + +#endif /* #ifndef __HAL_PHY_RF_8822B_H__ */ diff --git a/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c new file mode 100644 index 0000000..8258445 --- /dev/null +++ b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c @@ -0,0 +1,1483 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#include "../phydm_precomp.h" +#else +#include "../../phydm_precomp.h" +#endif + +#if (RTL8822B_SUPPORT == 1) + + +/*---------------------------Define Local Constant---------------------------*/ + +void phydm_set_iqk_cfir(struct PHY_DM_STRUCT *p_dm_odm, struct _IQK_INFORMATION *p_iqk_info, u8 idx, u8 path) +{ + u8 i; + u32 tmp; + + odm_set_bb_reg(p_dm_odm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1); + if (idx == 0) + odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x3); + else + odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x1); + odm_set_bb_reg(p_dm_odm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10); + for (i = 0; i < 8; i++) { + odm_set_bb_reg(p_dm_odm, 0x1bd8, MASKDWORD, 0xe0000001 + (i * 4)); + tmp = odm_get_bb_reg(p_dm_odm, 0x1bfc, MASKDWORD); + p_iqk_info->IQK_CFIR_real[0][path][idx][i] = (tmp & 0x0fff0000) >> 16; + p_iqk_info->IQK_CFIR_imag[0][path][idx][i] = tmp & 0xfff; + } + odm_set_bb_reg(p_dm_odm, 0x1bd8, MASKDWORD, 0x0); + odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x0); +} + +void phydm_get_read_counter(struct PHY_DM_STRUCT *p_dm_odm) +{ + u32 counter = 0x0; + + while (1) { + if ((odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x8, RFREGOFFSETMASK) == 0xabcde) || (counter > 300)) + break; + counter++; + ODM_delay_ms(1); + }; + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x8, RFREGOFFSETMASK, 0x0); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]counter = %d\n", counter)); +} + +/*---------------------------Define Local Constant---------------------------*/ + + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +void do_iqk_8822b( + void *p_dm_void, + u8 delta_thermal_index, + u8 thermal_value, + u8 threshold +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#else + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); +#endif + + odm_reset_iqk_result(p_dm_odm); + + p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value; + + phy_iq_calibrate_8822b(p_dm_odm, true); + +} +#else +/*Originally p_config->do_iqk is hooked phy_iq_calibrate_8822b, but do_iqk_8822b and phy_iq_calibrate_8822b have different arguments*/ +void do_iqk_8822b( + void *p_dm_void, + u8 delta_thermal_index, + u8 thermal_value, + u8 threshold +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + boolean is_recovery = (boolean) delta_thermal_index; + + phy_iq_calibrate_8822b(p_dm_odm, true); +} +#endif + +void +_iqk_rf0xb0_workaround( + struct PHY_DM_STRUCT *p_dm_odm + ) +{ + /*add 0xb8 control for the bad phase noise after switching channel*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)0x0, 0xb8, RFREGOFFSETMASK, 0x00a00); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)0x0, 0xb8, RFREGOFFSETMASK, 0x80a00); +} + +void +_iqk_fill_iqk_report_8822b( + void *p_dm_void, + u8 channel +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u32 tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0; + u8 i; + + for (i = 0; i < SS_8822B; i++) { + tmp1 = tmp1 + ((p_iqk_info->IQK_fail_report[channel][i][TX_IQK] & 0x1) << i); + tmp2 = tmp2 + ((p_iqk_info->IQK_fail_report[channel][i][RX_IQK] & 0x1) << (i + 4)); + tmp3 = tmp3 + ((p_iqk_info->RXIQK_fail_code[channel][i] & 0x3) << (i * 2 + 8)); + } + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); + odm_set_bb_reg(p_dm_odm, 0x1bf0, 0x0000ffff, tmp1 | tmp2 | tmp3); + + for (i = 0; i < 2; i++) + odm_write_4byte(p_dm_odm, 0x1be8 + (i * 4), (p_iqk_info->RXIQK_AGC[channel][(i * 2) + 1] << 16) | p_iqk_info->RXIQK_AGC[channel][i * 2]); +} + + +void +_iqk_iqk_fail_report_8822b( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 tmp1bf0 = 0x0; + u8 i; + + tmp1bf0 = odm_read_4byte(p_dm_odm, 0x1bf0); + + for (i = 0; i < 4; i++) { + if (tmp1bf0 & (0x1 << i)) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] please check S%d TXIQK\n", i)); +#else + panic_printk("[IQK] please check S%d TXIQK\n", i); +#endif + if (tmp1bf0 & (0x1 << (i + 12))) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] please check S%d RXIQK\n", i)); +#else + panic_printk("[IQK] please check S%d RXIQK\n", i); +#endif + + } +} + + +void +_iqk_backup_mac_bb_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 *MAC_backup, + u32 *BB_backup, + u32 *backup_mac_reg, + u32 *backup_bb_reg +) +{ + u32 i; + for (i = 0; i < MAC_REG_NUM_8822B; i++) + MAC_backup[i] = odm_read_4byte(p_dm_odm, backup_mac_reg[i]); + + for (i = 0; i < BB_REG_NUM_8822B; i++) + BB_backup[i] = odm_read_4byte(p_dm_odm, backup_bb_reg[i]); + + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BackupMacBB Success!!!!\n")); */ +} + + +void +_iqk_backup_rf_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 RF_backup[][2], + u32 *backup_rf_reg +) +{ + u32 i; + + for (i = 0; i < RF_REG_NUM_8822B; i++) { + RF_backup[i][ODM_RF_PATH_A] = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK); + RF_backup[i][ODM_RF_PATH_B] = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_B, backup_rf_reg[i], RFREGOFFSETMASK); + } + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BackupRF Success!!!!\n")); */ +} + + +void +_iqk_agc_bnd_int_8822b( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + /*initialize RX AGC bnd, it must do after bbreset*/ + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf80a7008); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8015008); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]init. rx agc bnd\n"));*/ +} + + +void +_iqk_bb_reset_8822b( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + boolean cca_ing = false; + u32 count = 0; + + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000); + /*reset BB report*/ + odm_set_bb_reg(p_dm_odm, 0x8f8, 0x0ff00000, 0x0); + + while (1) { + odm_write_4byte(p_dm_odm, 0x8fc, 0x0); + odm_set_bb_reg(p_dm_odm, 0x198c, 0x7, 0x7); + cca_ing = (boolean) odm_get_bb_reg(p_dm_odm, 0xfa0, BIT(3)); + + if (count > 30) + cca_ing = false; + + if (cca_ing) { + ODM_delay_ms(1); + count++; + } else { + odm_write_1byte(p_dm_odm, 0x808, 0x0); /*RX ant off*/ + odm_set_bb_reg(p_dm_odm, 0xa04, BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x0); /*CCK RX path off*/ + + /*BBreset*/ + odm_set_bb_reg(p_dm_odm, 0x0, BIT(16), 0x0); + odm_set_bb_reg(p_dm_odm, 0x0, BIT(16), 0x1); + + if (odm_get_bb_reg(p_dm_odm, 0x660, BIT(16))) + odm_write_4byte(p_dm_odm, 0x6b4, 0x89000006); + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BBreset!!!!\n"));*/ + break; + } + } +} + +void +_iqk_afe_setting_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + boolean do_iqk +) +{ + if (do_iqk) { + odm_write_4byte(p_dm_odm, 0xc60, 0x50000000); + odm_write_4byte(p_dm_odm, 0xc60, 0x70070040); + odm_write_4byte(p_dm_odm, 0xe60, 0x50000000); + odm_write_4byte(p_dm_odm, 0xe60, 0x70070040); + + odm_write_4byte(p_dm_odm, 0xc58, 0xd8000402); + odm_write_4byte(p_dm_odm, 0xc5c, 0xd1000120); + odm_write_4byte(p_dm_odm, 0xc6c, 0x00000a15); + odm_write_4byte(p_dm_odm, 0xe58, 0xd8000402); + odm_write_4byte(p_dm_odm, 0xe5c, 0xd1000120); + odm_write_4byte(p_dm_odm, 0xe6c, 0x00000a15); + _iqk_bb_reset_8822b(p_dm_odm); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]AFE setting for IQK mode!!!!\n")); */ + } else { + odm_write_4byte(p_dm_odm, 0xc60, 0x50000000); + odm_write_4byte(p_dm_odm, 0xc60, 0x70038040); + odm_write_4byte(p_dm_odm, 0xe60, 0x50000000); + odm_write_4byte(p_dm_odm, 0xe60, 0x70038040); + + odm_write_4byte(p_dm_odm, 0xc58, 0xd8020402); + odm_write_4byte(p_dm_odm, 0xc5c, 0xde000120); + odm_write_4byte(p_dm_odm, 0xc6c, 0x0000122a); + odm_write_4byte(p_dm_odm, 0xe58, 0xd8020402); + odm_write_4byte(p_dm_odm, 0xe5c, 0xde000120); + odm_write_4byte(p_dm_odm, 0xe6c, 0x0000122a); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]AFE setting for Normal mode!!!!\n")); */ + } +} + +void +_iqk_restore_mac_bb_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 *MAC_backup, + u32 *BB_backup, + u32 *backup_mac_reg, + u32 *backup_bb_reg +) +{ + u32 i; + + for (i = 0; i < MAC_REG_NUM_8822B; i++) + odm_write_4byte(p_dm_odm, backup_mac_reg[i], MAC_backup[i]); + for (i = 0; i < BB_REG_NUM_8822B; i++) + odm_write_4byte(p_dm_odm, backup_bb_reg[i], BB_backup[i]); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RestoreMacBB Success!!!!\n")); */ +} + +void +_iqk_restore_rf_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u32 *backup_rf_reg, + u32 RF_backup[][2] +) +{ + u32 i; + + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x0); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, RFREGOFFSETMASK, 0x0); + /*0xdf[4]=0*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, RFREGOFFSETMASK, RF_backup[0][ODM_RF_PATH_A] & (~BIT(4))); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xdf, RFREGOFFSETMASK, RF_backup[0][ODM_RF_PATH_B] & (~BIT(4))); + + for (i = 1; i < RF_REG_NUM_8822B; i++) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][ODM_RF_PATH_A]); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][ODM_RF_PATH_B]); + } + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RestoreRF Success!!!!\n")); */ + +} + + +void +_iqk_backup_iqk_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 step, + u8 path +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u8 i, j, k; + u16 iqk_apply[2] = {0xc94, 0xe94}; + + switch (step) { + case 0: + p_iqk_info->iqk_channel[1] = p_iqk_info->iqk_channel[0]; + for (i = 0; i < 2; i++) { + p_iqk_info->LOK_IDAC[1][i] = p_iqk_info->LOK_IDAC[0][i]; + p_iqk_info->RXIQK_AGC[1][i] = p_iqk_info->RXIQK_AGC[0][i]; + p_iqk_info->bypass_iqk[1][i] = p_iqk_info->bypass_iqk[0][i]; + p_iqk_info->RXIQK_fail_code[1][i] = p_iqk_info->RXIQK_fail_code[0][i]; + for (j = 0; j < 2; j++) { + p_iqk_info->IQK_fail_report[1][i][j] = p_iqk_info->IQK_fail_report[0][i][j]; + for (k = 0; k < 8; k++) { + p_iqk_info->IQK_CFIR_real[1][i][j][k] = p_iqk_info->IQK_CFIR_real[0][i][j][k]; + p_iqk_info->IQK_CFIR_imag[1][i][j][k] = p_iqk_info->IQK_CFIR_imag[0][i][j][k]; + } + } + } + + for (i = 0; i < 4; i++) { + p_iqk_info->RXIQK_fail_code[0][i] = 0x0; + p_iqk_info->RXIQK_AGC[0][i] = 0x0; + for (j = 0; j < 2; j++) { + p_iqk_info->IQK_fail_report[0][i][j] = true; + p_iqk_info->gs_retry_count[0][i][j] = 0x0; + } + for (j = 0; j < 3; j++) + p_iqk_info->retry_count[0][i][j] = 0x0; + } + /*backup channel*/ + p_iqk_info->iqk_channel[0] = p_iqk_info->rf_reg18; + break; + case 1: /*LOK backup*/ + p_iqk_info->LOK_IDAC[0][path] = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x58, RFREGOFFSETMASK); + break; + case 2: /*TXIQK backup*/ + case 3: /*RXIQK backup*/ + phydm_set_iqk_cfir(p_dm_odm, p_iqk_info, (step-2), path); + break; + } +} + +void +_iqk_reload_iqk_setting_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 channel, + u8 reload_idx /*1: reload TX, 2: reload LO, TX, RX*/ +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u8 i, path, idx; + u16 iqk_apply[2] = {0xc94, 0xe94}; + + for (path = 0; path < 2; path++) { + if (reload_idx == 2) { + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xdf, BIT(4), 0x1); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x58, RFREGOFFSETMASK, p_iqk_info->LOK_IDAC[channel][path]); + } + + for (idx = 0; idx < reload_idx; idx++) { + odm_set_bb_reg(p_dm_odm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1); + odm_set_bb_reg(p_dm_odm, 0x1b2c, MASKDWORD, 0x7); + odm_set_bb_reg(p_dm_odm, 0x1b38, MASKDWORD, 0x20000000); + odm_set_bb_reg(p_dm_odm, 0x1b3c, MASKDWORD, 0x20000000); + odm_set_bb_reg(p_dm_odm, 0x1bcc, MASKDWORD, 0x00000000); + if (idx == 0) + odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x3); + else + odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x1); + odm_set_bb_reg(p_dm_odm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10); + for (i = 0; i < 8; i++) { + odm_write_4byte(p_dm_odm, 0x1bd8, ((0xc0000000 >> idx) + 0x3) + (i * 4) + (p_iqk_info->IQK_CFIR_real[channel][path][idx][i] << 9)); + odm_write_4byte(p_dm_odm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (p_iqk_info->IQK_CFIR_imag[channel][path][idx][i] << 9)); + } + if (idx == 0) + odm_set_bb_reg(p_dm_odm, iqk_apply[path], BIT(0), ~(p_iqk_info->IQK_fail_report[channel][path][idx])); + else + odm_set_bb_reg(p_dm_odm, iqk_apply[path], BIT(10), ~(p_iqk_info->IQK_fail_report[channel][path][idx])); + } + odm_set_bb_reg(p_dm_odm, 0x1bd8, MASKDWORD, 0x0); + odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x0); + } +} + +boolean +_iqk_reload_iqk_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + boolean reset +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u8 i; + boolean reload = false; + + if (reset) { + for (i = 0; i < 2; i++) + p_iqk_info->iqk_channel[i] = 0x0; + } else { + p_iqk_info->rf_reg18 = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + + for (i = 0; i < 2; i++) { + if (p_iqk_info->rf_reg18 == p_iqk_info->iqk_channel[i]) { + _iqk_reload_iqk_setting_8822b(p_dm_odm, i, 2); + _iqk_fill_iqk_report_8822b(p_dm_odm, i); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]reload IQK result before!!!!\n")); + reload = true; + } + } + } + /*report*/ + odm_set_bb_reg(p_dm_odm, 0x1bf0, BIT(16), (u8)reload); + return reload; +} + + +void +_iqk_rfe_setting_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + boolean ext_pa_on +) +{ + if (ext_pa_on) { + /*RFE setting*/ + odm_write_4byte(p_dm_odm, 0xcb0, 0x77777777); + odm_write_4byte(p_dm_odm, 0xcb4, 0x00007777); + odm_write_4byte(p_dm_odm, 0xcbc, 0x0000083B); + odm_write_4byte(p_dm_odm, 0xeb0, 0x77777777); + odm_write_4byte(p_dm_odm, 0xeb4, 0x00007777); + odm_write_4byte(p_dm_odm, 0xebc, 0x0000083B); + /*odm_write_4byte(p_dm_odm, 0x1990, 0x00000c30);*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]external PA on!!!!\n")); + } else { + /*RFE setting*/ + odm_write_4byte(p_dm_odm, 0xcb0, 0x77777777); + odm_write_4byte(p_dm_odm, 0xcb4, 0x00007777); + odm_write_4byte(p_dm_odm, 0xcbc, 0x00000100); + odm_write_4byte(p_dm_odm, 0xeb0, 0x77777777); + odm_write_4byte(p_dm_odm, 0xeb4, 0x00007777); + odm_write_4byte(p_dm_odm, 0xebc, 0x00000100); + /*odm_write_4byte(p_dm_odm, 0x1990, 0x00000c30);*/ + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]external PA off!!!!\n"));*/ + } +} + + +void +_iqk_rf_setting_8822b( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u8 path; + u32 tmp; + + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); + odm_write_4byte(p_dm_odm, 0x1bb8, 0x00000000); + + for (path = 0; path < 2; path++) { + /*0xdf:B11 = 1,B4 = 0, B1 = 1*/ + tmp = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xdf, RFREGOFFSETMASK); + tmp = (tmp & (~BIT(4))) | BIT(1) | BIT(11); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xdf, RFREGOFFSETMASK, tmp); + + /*release 0x56 TXBB*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x65, RFREGOFFSETMASK, 0x09000); + + if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x1); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, RFREGOFFSETMASK, 0x00026); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3e, RFREGOFFSETMASK, 0x00037); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3f, RFREGOFFSETMASK, 0xdefce); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x0); + } else { + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x1); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, RFREGOFFSETMASK, 0x00026); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3e, RFREGOFFSETMASK, 0x00037); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3f, RFREGOFFSETMASK, 0x5efce); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x0); + } + } +} + + + +void +_iqk_configure_macbb_8822b( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + /*MACBB register setting*/ + odm_write_1byte(p_dm_odm, 0x522, 0x7f); + odm_set_bb_reg(p_dm_odm, 0x550, BIT(11) | BIT(3), 0x0); + odm_set_bb_reg(p_dm_odm, 0x90c, BIT(15), 0x1); /*0x90c[15]=1: dac_buf reset selection*/ + odm_set_bb_reg(p_dm_odm, 0x9a4, BIT(31), 0x0); /*0x9a4[31]=0: Select da clock*/ + /*0xc94[0]=1, 0xe94[0]=1: Åýtx±qiqk¥´¥X¨Ó*/ + odm_set_bb_reg(p_dm_odm, 0xc94, BIT(0), 0x1); + odm_set_bb_reg(p_dm_odm, 0xe94, BIT(0), 0x1); + odm_set_bb_reg(p_dm_odm, 0xc94, (BIT(11) | BIT(10)), 0x1); + odm_set_bb_reg(p_dm_odm, 0xe94, (BIT(11) | BIT(10)), 0x1); + /* 3-wire off*/ + odm_write_4byte(p_dm_odm, 0xc00, 0x00000004); + odm_write_4byte(p_dm_odm, 0xe00, 0x00000004); + /*disable PMAC*/ + odm_set_bb_reg(p_dm_odm, 0xb00, BIT(8), 0x0); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set MACBB setting for IQK!!!!\n"));*/ + +} + +void +_iqk_lok_setting_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + + u8 path +) +{ + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(p_dm_odm, 0x1bcc, 0x9); + odm_write_1byte(p_dm_odm, 0x1b23, 0x00); + + switch (*p_dm_odm->p_band_type) { + case ODM_BAND_2_4G: + odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x50df2); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xadc00); + /* WE_LUT_TX_LOK*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(4), 0x1); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, BIT(1) | BIT(0), 0x0); + break; + case ODM_BAND_5G: + odm_write_1byte(p_dm_odm, 0x1b2b, 0x80); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x5086c); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xa9c00); + /* WE_LUT_TX_LOK*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(4), 0x1); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, BIT(1) | BIT(0), 0x1); + break; + } + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set LOK setting!!!!\n"));*/ +} + + +void +_iqk_txk_setting_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path +) +{ + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(p_dm_odm, 0x1bcc, 0x9); + odm_write_4byte(p_dm_odm, 0x1b20, 0x01440008); + + if (path == 0x0) + odm_write_4byte(p_dm_odm, 0x1b00, 0xf800000a); + else + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); + odm_write_4byte(p_dm_odm, 0x1bcc, 0x3f); + + switch (*p_dm_odm->p_band_type) { + case ODM_BAND_2_4G: + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x50df2); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xadc00); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + break; + case ODM_BAND_5G: + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x500ef); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xa9c00); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x80); + break; + } + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set TXK setting!!!!\n"));*/ + +} + + +void +_iqk_rxk1_setting_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path +) +{ + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + + switch (*p_dm_odm->p_band_type) { + case ODM_BAND_2_4G: + odm_write_1byte(p_dm_odm, 0x1bcc, 0x9); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + odm_write_4byte(p_dm_odm, 0x1b20, 0x01450008); + odm_write_4byte(p_dm_odm, 0x1b24, 0x01460c88); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x510e0); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xacc00); + break; + case ODM_BAND_5G: + odm_write_1byte(p_dm_odm, 0x1bcc, 0x09); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x80); + odm_write_4byte(p_dm_odm, 0x1b20, 0x00850008); + odm_write_4byte(p_dm_odm, 0x1b24, 0x00460048); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x510e0); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xadc00); + break; + } + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set RXK setting!!!!\n"));*/ + +} + + +void +_iqk_rxk2_setting_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path, + boolean is_gs +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + + switch (*p_dm_odm->p_band_type) { + case ODM_BAND_2_4G: + if (is_gs) + p_iqk_info->tmp1bcc = 0x12; + odm_write_1byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + odm_write_4byte(p_dm_odm, 0x1b20, 0x01450008); + odm_write_4byte(p_dm_odm, 0x1b24, 0x01460848); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x510e0); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xa9c00); + break; + case ODM_BAND_5G: + if (is_gs) { + if (path == ODM_RF_PATH_A) + p_iqk_info->tmp1bcc = 0x12; + else + p_iqk_info->tmp1bcc = 0x09; + } + odm_write_1byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x80); + odm_write_4byte(p_dm_odm, 0x1b20, 0x00850008); + odm_write_4byte(p_dm_odm, 0x1b24, 0x00460848); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x51060); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xa9c00); + break; + } + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set RXK setting!!!!\n"));*/ + +} + + +void +halrf_iqk_set_rf0x8( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path +) +{ + u16 c = 0x0; + + while (c < 30000) { + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, RFREGOFFSETMASK, 0x0); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8, RFREGOFFSETMASK, 0x0); + if (odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8, RFREGOFFSETMASK) == 0x0) + break; + c++; + } +} + +boolean +_iqk_check_cal_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path, + u8 cmd +) +{ + boolean notready = true, fail = true; + u32 delay_count = 0x0; + + while (notready) { + if (odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8, RFREGOFFSETMASK) == 0x12345) { + if (cmd == 0x0)/*LOK*/ + fail = false; + else + fail = (boolean) odm_get_bb_reg(p_dm_odm, 0x1b08, BIT(26)); + notready = false; + } else { + ODM_delay_ms(1); + delay_count++; + } + + if (delay_count >= 50) { + fail = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]IQK timeout!!!\n")); + break; + } + } + halrf_iqk_set_rf0x8(p_dm_odm, path); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]delay count = 0x%x!!!\n", delay_count)); + return fail; +} + + +boolean +_iqk_rx_iqk_gain_search_fail_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path, + u8 step +) +{ + + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + boolean fail = true; + u32 IQK_CMD = 0x0, rf_reg0, tmp, bb_idx; + u8 IQMUX[4] = {0x9, 0x12, 0x1b, 0x24}; + u8 idx; + + for (idx = 0; idx < 4; idx++) + if (p_iqk_info->tmp1bcc == IQMUX[idx]) + break; + + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc); + + if (step == RXIQK1) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d RXIQK GainSearch ============\n", path)); + + if (step == RXIQK1) + IQK_CMD = 0xf8000208 | (1 << (path + 4)); + else + IQK_CMD = 0xf8000308 | (1 << (path + 4)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S%d GS%d_Trigger = 0x%x\n", path, step, IQK_CMD)); + + odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD); + odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD + 0x1); + ODM_delay_ms(GS_delay_8822B); + fail = _iqk_check_cal_8822b(p_dm_odm, path, 0x1); + + if (step == RXIQK2) { + rf_reg0 = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x0, RFREGOFFSETMASK); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]S%d ==> RF0x0 = 0x%x, tmp1bcc = 0x%x, idx = %d, 0x1b3c = 0x%x\n", path, rf_reg0, p_iqk_info->tmp1bcc, idx, odm_read_4byte(p_dm_odm, 0x1b3c))); + tmp = (rf_reg0 & 0x1fe0) >> 5; + p_iqk_info->lna_idx = tmp >> 5; + bb_idx = tmp & 0x1f; +#if 1 + if (bb_idx == 0x1) { + if (p_iqk_info->lna_idx != 0x0) + p_iqk_info->lna_idx--; + else if (idx != 3) + idx++; + else + p_iqk_info->isbnd = true; + fail = true; + } else if (bb_idx == 0xa) { + if (idx != 0) + idx--; + else if (p_iqk_info->lna_idx != 0x7) + p_iqk_info->lna_idx++; + else + p_iqk_info->isbnd = true; + fail = true; + } else + fail = false; + + if (p_iqk_info->isbnd == true) + fail = false; + + p_iqk_info->tmp1bcc = IQMUX[idx]; +#endif + +#if 0 + if (bb_idx == 0x1) { + if (p_iqk_info->lna_idx != 0x0) + p_iqk_info->lna_idx--; + fail = true; + } else if (bb_idx == 0xa) { + if (p_iqk_info->lna_idx != 0x7) + p_iqk_info->lna_idx++; + fail = true; + } else + fail = false; +#endif + if (fail) { + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(p_dm_odm, 0x1b24, (odm_read_4byte(p_dm_odm, 0x1b24) & 0xffffe3ff) | (p_iqk_info->lna_idx << 10)); + } + } + + return fail; +} + +boolean +_lok_one_shot_8822b( + void *p_dm_void, + u8 path +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u8 delay_count = 0; + boolean LOK_notready = false; + u32 LOK_temp = 0; + u32 IQK_CMD = 0x0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]==========S%d LOK ==========\n", path)); + IQK_CMD = 0xf8000008 | (1 << (4 + path)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]LOK_Trigger = 0x%x\n", IQK_CMD)); + odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD); + odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD + 1); + /*LOK: CMD ID = 0 {0xf8000018, 0xf8000028}*/ + /*LOK: CMD ID = 0 {0xf8000019, 0xf8000029}*/ + ODM_delay_ms(LOK_delay_8822B); + LOK_notready = _iqk_check_cal_8822b(p_dm_odm, path, 0x0); + if (!LOK_notready) + _iqk_backup_iqk_8822b(p_dm_odm, 0x1, path); + if (ODM_COMP_CALIBRATION) { + if (!LOK_notready) { + LOK_temp = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x58, RFREGOFFSETMASK); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]0x58 = 0x%x\n", LOK_temp)); + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]==>S%d LOK Fail!!!\n", path)); + } + p_iqk_info->LOK_fail[path] = LOK_notready; + return LOK_notready; +} + + + + +boolean +_iqk_one_shot_8822b( + void *p_dm_void, + u8 path, + u8 idx +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u8 delay_count = 0; + boolean notready = true, fail = true; + u32 IQK_CMD = 0x0; + u16 iqk_apply[2] = {0xc94, 0xe94}; + + if (idx == TXIQK) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBTXIQK ============\n", path)); + else if (idx == RXIQK1) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBRXIQK STEP1============\n", path)); + else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBRXIQK STEP2============\n", path)); + + if (idx == TXIQK) { + IQK_CMD = 0xf8000008 | ((*p_dm_odm->p_band_width + 4) << 8) | (1 << (path + 4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]TXK_Trigger = 0x%x\n", IQK_CMD)); + /*{0xf8000418, 0xf800042a} ==> 20 WBTXK (CMD = 4)*/ + /*{0xf8000518, 0xf800052a} ==> 40 WBTXK (CMD = 5)*/ + /*{0xf8000618, 0xf800062a} ==> 80 WBTXK (CMD = 6)*/ + } else if (idx == RXIQK1) { + if (*p_dm_odm->p_band_width == 2) + IQK_CMD = 0xf8000808 | (1 << (path + 4)); + else + IQK_CMD = 0xf8000708 | (1 << (path + 4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]RXK1_Trigger = 0x%x\n", IQK_CMD)); + /*{0xf8000718, 0xf800072a} ==> 20 WBTXK (CMD = 7)*/ + /*{0xf8000718, 0xf800072a} ==> 40 WBTXK (CMD = 7)*/ + /*{0xf8000818, 0xf800082a} ==> 80 WBTXK (CMD = 8)*/ + } else if (idx == RXIQK2) { + IQK_CMD = 0xf8000008 | ((*p_dm_odm->p_band_width + 9) << 8) | (1 << (path + 4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]RXK2_Trigger = 0x%x\n", IQK_CMD)); + /*{0xf8000918, 0xf800092a} ==> 20 WBRXK (CMD = 9)*/ + /*{0xf8000a18, 0xf8000a2a} ==> 40 WBRXK (CMD = 10)*/ + /*{0xf8000b18, 0xf8000b2a} ==> 80 WBRXK (CMD = 11)*/ + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(p_dm_odm, 0x1b24, (odm_read_4byte(p_dm_odm, 0x1b24) & 0xffffe3ff) | ((p_iqk_info->lna_idx & 0x7) << 10)); + } + odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD); + odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD + 0x1); + ODM_delay_ms(WBIQK_delay_8822B); + fail = _iqk_check_cal_8822b(p_dm_odm, path, 0x1); + + if (p_dm_odm->debug_components && ODM_COMP_CALIBRATION) { + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]S%d ==> 0x1b00 = 0x%x, 0x1b08 = 0x%x\n", path, odm_read_4byte(p_dm_odm, 0x1b00), odm_read_4byte(p_dm_odm, 0x1b08))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]S%d ==> delay_count = 0x%x\n", path, delay_count)); + if (idx != TXIQK) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]S%d ==> RF0x0 = 0x%x, RF0x56 = 0x%x\n", path, odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x0, RFREGOFFSETMASK), + odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK))); + } + + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + + if (idx == TXIQK) { + if (fail) + odm_set_bb_reg(p_dm_odm, iqk_apply[path], BIT(0), 0x0); + else + _iqk_backup_iqk_8822b(p_dm_odm, 0x2, path); + } + + if (idx == RXIQK2) { + p_iqk_info->RXIQK_AGC[0][path] = + (u16)(((odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x0, RFREGOFFSETMASK) >> 5) & 0xff) | + (p_iqk_info->tmp1bcc << 8)); + + odm_write_4byte(p_dm_odm, 0x1b38, 0x20000000); + + if (fail) + odm_set_bb_reg(p_dm_odm, iqk_apply[path], (BIT(11) | BIT(10)), 0x0); + else + _iqk_backup_iqk_8822b(p_dm_odm, 0x3, path); + } + + if (idx == TXIQK) + p_iqk_info->IQK_fail_report[0][path][TXIQK] = fail; + else + p_iqk_info->IQK_fail_report[0][path][RXIQK] = fail; + + return fail; +} + + +boolean +_iqk_rx_iqk_by_path_8822b( + void *p_dm_void, + u8 path +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + boolean KFAIL = true, gonext; + +#if 1 + switch (p_iqk_info->rxiqk_step) { + case 1: /*gain search_RXK1*/ + _iqk_rxk1_setting_8822b(p_dm_odm, path); + gonext = false; + while (1) { + KFAIL = _iqk_rx_iqk_gain_search_fail_8822b(p_dm_odm, path, RXIQK1); + if (KFAIL && (p_iqk_info->gs_retry_count[0][path][RXIQK1] < 2)) + p_iqk_info->gs_retry_count[0][path][RXIQK1]++; + else if (KFAIL) { + p_iqk_info->RXIQK_fail_code[0][path] = 0; + p_iqk_info->rxiqk_step = 5; + gonext = true; + } else { + p_iqk_info->rxiqk_step++; + gonext = true; + } + if (gonext) + break; + } + break; + case 2: /*gain search_RXK2*/ + _iqk_rxk2_setting_8822b(p_dm_odm, path, true); + p_iqk_info->isbnd = false; + while (1) { + KFAIL = _iqk_rx_iqk_gain_search_fail_8822b(p_dm_odm, path, RXIQK2); + if (KFAIL && (p_iqk_info->gs_retry_count[0][path][RXIQK2] < rxiqk_gs_limit)) + p_iqk_info->gs_retry_count[0][path][RXIQK2]++; + else { + p_iqk_info->rxiqk_step++; + break; + } + } + break; + case 3: /*RXK1*/ + _iqk_rxk1_setting_8822b(p_dm_odm, path); + gonext = false; + while (1) { + KFAIL = _iqk_one_shot_8822b(p_dm_odm, path, RXIQK1); + if (KFAIL && (p_iqk_info->retry_count[0][path][RXIQK1] < 2)) + p_iqk_info->retry_count[0][path][RXIQK1]++; + else if (KFAIL) { + p_iqk_info->RXIQK_fail_code[0][path] = 1; + p_iqk_info->rxiqk_step = 5; + gonext = true; + } else { + p_iqk_info->rxiqk_step++; + gonext = true; + } + if (gonext) + break; + } + break; + case 4: /*RXK2*/ + _iqk_rxk2_setting_8822b(p_dm_odm, path, false); + gonext = false; + while (1) { + KFAIL = _iqk_one_shot_8822b(p_dm_odm, path, RXIQK2); + if (KFAIL && (p_iqk_info->retry_count[0][path][RXIQK2] < 2)) + p_iqk_info->retry_count[0][path][RXIQK2]++; + else if (KFAIL) { + p_iqk_info->RXIQK_fail_code[0][path] = 2; + p_iqk_info->rxiqk_step = 5; + gonext = true; + } else { + p_iqk_info->rxiqk_step++; + gonext = true; + } + if (gonext) + break; + } + break; + } + return KFAIL; +#endif +} + + +void +_iqk_iqk_by_path_8822b( + void *p_dm_void, + boolean segment_iqk +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + boolean KFAIL = true; + u8 i, kcount_limit; + + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]iqk_step = 0x%x\n", p_dm_odm->rf_calibrate_info.iqk_step)); */ + + if (*p_dm_odm->p_band_width == 2) + kcount_limit = kcount_limit_80m; + else + kcount_limit = kcount_limit_others; + + while (1) { +#if 1 + switch (p_dm_odm->rf_calibrate_info.iqk_step) { + case 1: /*S0 LOK*/ +#if 1 + _iqk_lok_setting_8822b(p_dm_odm, ODM_RF_PATH_A); + _lok_one_shot_8822b(p_dm_odm, ODM_RF_PATH_A); +#endif + p_dm_odm->rf_calibrate_info.iqk_step++; + break; + case 2: /*S1 LOK*/ +#if 1 + _iqk_lok_setting_8822b(p_dm_odm, ODM_RF_PATH_B); + _lok_one_shot_8822b(p_dm_odm, ODM_RF_PATH_B); +#endif + p_dm_odm->rf_calibrate_info.iqk_step++; + break; + case 3: /*S0 TXIQK*/ +#if 1 + _iqk_txk_setting_8822b(p_dm_odm, ODM_RF_PATH_A); + KFAIL = _iqk_one_shot_8822b(p_dm_odm, ODM_RF_PATH_A, TXIQK); + p_iqk_info->kcount++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S0TXK KFail = 0x%x\n", KFAIL)); + + if (KFAIL && (p_iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK] < 3)) + p_iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK]++; + else +#endif + p_dm_odm->rf_calibrate_info.iqk_step++; + break; + case 4: /*S1 TXIQK*/ +#if 1 + _iqk_txk_setting_8822b(p_dm_odm, ODM_RF_PATH_B); + KFAIL = _iqk_one_shot_8822b(p_dm_odm, ODM_RF_PATH_B, TXIQK); + p_iqk_info->kcount++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S1TXK KFail = 0x%x\n", KFAIL)); + if (KFAIL && p_iqk_info->retry_count[0][ODM_RF_PATH_B][TXIQK] < 3) + p_iqk_info->retry_count[0][ODM_RF_PATH_B][TXIQK]++; + else +#endif + p_dm_odm->rf_calibrate_info.iqk_step++; + break; + case 5: /*S0 RXIQK*/ + while (1) { + KFAIL = _iqk_rx_iqk_by_path_8822b(p_dm_odm, ODM_RF_PATH_A); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S0RXK KFail = 0x%x\n", KFAIL)); + if (p_iqk_info->rxiqk_step == 5) { + p_dm_odm->rf_calibrate_info.iqk_step++; + p_iqk_info->rxiqk_step = 1; + if (KFAIL) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]S0RXK fail code: %d!!!\n", p_iqk_info->RXIQK_fail_code[0][ODM_RF_PATH_A])); + break; + } + } + p_iqk_info->kcount++; + break; + case 6: /*S1 RXIQK*/ + while (1) { + KFAIL = _iqk_rx_iqk_by_path_8822b(p_dm_odm, ODM_RF_PATH_B); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S1RXK KFail = 0x%x\n", KFAIL)); + if (p_iqk_info->rxiqk_step == 5) { + p_dm_odm->rf_calibrate_info.iqk_step++; + p_iqk_info->rxiqk_step = 1; + if (KFAIL) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]S1RXK fail code: %d!!!\n", p_iqk_info->RXIQK_fail_code[0][ODM_RF_PATH_B])); + break; + } + } + p_iqk_info->kcount++; + break; + } + + if (p_dm_odm->rf_calibrate_info.iqk_step == 7) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]==========LOK summary ==========\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]PathA_LOK_notready = %d, PathB_LOK1_notready = %d\n", + p_iqk_info->LOK_fail[ODM_RF_PATH_A], p_iqk_info->LOK_fail[ODM_RF_PATH_B])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]==========IQK summary ==========\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]PathA_TXIQK_fail = %d, PathB_TXIQK_fail = %d\n", + p_iqk_info->IQK_fail_report[0][ODM_RF_PATH_A][TXIQK], p_iqk_info->IQK_fail_report[0][ODM_RF_PATH_B][TXIQK])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]PathA_RXIQK_fail = %d, PathB_RXIQK_fail = %d\n", + p_iqk_info->IQK_fail_report[0][ODM_RF_PATH_A][RXIQK], p_iqk_info->IQK_fail_report[0][ODM_RF_PATH_B][RXIQK])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]PathA_TXIQK_retry = %d, PathB_TXIQK_retry = %d\n", + p_iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK], p_iqk_info->retry_count[0][ODM_RF_PATH_B][TXIQK])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]PathA_RXK1_retry = %d, PathA_RXK2_retry = %d, PathB_RXK1_retry = %d, PathB_RXK2_retry = %d\n", + p_iqk_info->retry_count[0][ODM_RF_PATH_A][RXIQK1], p_iqk_info->retry_count[0][ODM_RF_PATH_A][RXIQK2], + p_iqk_info->retry_count[0][ODM_RF_PATH_B][RXIQK1], p_iqk_info->retry_count[0][ODM_RF_PATH_B][RXIQK2])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]PathA_GS1_retry = %d, PathA_GS2_retry = %d, PathB_GS1_retry = %d, PathB_GS2_retry = %d\n", + p_iqk_info->gs_retry_count[0][ODM_RF_PATH_A][RXIQK1], p_iqk_info->gs_retry_count[0][ODM_RF_PATH_A][RXIQK2], + p_iqk_info->gs_retry_count[0][ODM_RF_PATH_B][RXIQK1], p_iqk_info->gs_retry_count[0][ODM_RF_PATH_B][RXIQK2])); + for (i = 0; i < 2; i++) { + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | i << 1); + odm_write_4byte(p_dm_odm, 0x1b2c, 0x7); + odm_write_4byte(p_dm_odm, 0x1bcc, 0x0); + odm_write_4byte(p_dm_odm, 0x1b38, 0x20000000); + } + break; + } + + if ((segment_iqk == true) && (p_iqk_info->kcount == kcount_limit)) + break; +#endif +} +} + +void +_iqk_start_iqk_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + boolean segment_iqk +) +{ + u32 tmp; + + /*GNT_WL = 1*/ + tmp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK); + tmp = tmp | BIT(5) | BIT(0); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK, tmp); + + tmp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x1, RFREGOFFSETMASK); + tmp = tmp | BIT(5) | BIT(0); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x1, RFREGOFFSETMASK, tmp); + + _iqk_iqk_by_path_8822b(p_dm_odm, segment_iqk); + + +} + +void +_iq_calibrate_8822b_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u8 i, j, k, m; + + if (p_iqk_info->iqk_times == 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]=====>PHY_IQCalibrate_8822B_Init\n")); + + for (i = 0; i < SS_8822B; i++) { + for (j = 0; j < 2; j++) { + p_iqk_info->LOK_fail[i] = true; + p_iqk_info->IQK_fail[j][i] = true; + p_iqk_info->iqc_matrix[j][i] = 0x20000000; + } + } + + for (i = 0; i < 2; i++) { + p_iqk_info->iqk_channel[i] = 0x0; + + for (j = 0; j < SS_8822B; j++) { + p_iqk_info->LOK_IDAC[i][j] = 0x0; + p_iqk_info->RXIQK_AGC[i][j] = 0x0; + p_iqk_info->bypass_iqk[i][j] = 0x0; + + for (k = 0; k < 2; k++) { + p_iqk_info->IQK_fail_report[i][j][k] = true; + for (m = 0; m < 8; m++) { + p_iqk_info->IQK_CFIR_real[i][j][k][m] = 0x0; + p_iqk_info->IQK_CFIR_imag[i][j][k][m] = 0x0; + } + } + + for (k = 0; k < 3; k++) + p_iqk_info->retry_count[i][j][k] = 0x0; + + } + } + } + /*cu_distance (IQK result variation)=111*/ + odm_write_4byte(p_dm_odm, 0x1b10, 0x88011c00); +} + + +void +_phy_iq_calibrate_8822b( + struct PHY_DM_STRUCT *p_dm_odm, + boolean reset +) +{ + + u32 MAC_backup[MAC_REG_NUM_8822B], BB_backup[BB_REG_NUM_8822B], RF_backup[RF_REG_NUM_8822B][SS_8822B]; + u32 backup_mac_reg[MAC_REG_NUM_8822B] = {0x520, 0x550}; + u32 backup_bb_reg[BB_REG_NUM_8822B] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00, 0xeb0, 0xeb4, 0xebc, 0x1990, 0x9a4, 0xa04, 0xb00}; + u32 backup_rf_reg[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1}; + boolean segment_iqk = false, is_mp = false; + + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + + if (*(p_dm_odm->p_mp_mode)) + is_mp = true; + else if (p_dm_odm->is_linked) + segment_iqk = false; + + if (!is_mp) + if (_iqk_reload_iqk_8822b(p_dm_odm, reset)) + return; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]==========IQK strat!!!!!==========\n")); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]p_band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n", (*p_dm_odm->p_band_type == ODM_BAND_5G) ? "5G" : "2G", *p_dm_odm->p_band_width, p_dm_odm->ext_pa, p_dm_odm->ext_pa_5g)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]Interface = %d, cut_version = %x\n", p_dm_odm->support_interface, p_dm_odm->cut_version)); + + p_iqk_info->iqk_times++; + + p_iqk_info->kcount = 0; + p_dm_odm->rf_calibrate_info.iqk_total_progressing_time = 0; + p_dm_odm->rf_calibrate_info.iqk_step = 1; + p_iqk_info->rxiqk_step = 1; + + _iqk_backup_iqk_8822b(p_dm_odm, 0x0, 0x0); + _iqk_backup_mac_bb_8822b(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg); + _iqk_backup_rf_8822b(p_dm_odm, RF_backup, backup_rf_reg); +#if 0 + _iqk_configure_macbb_8822b(p_dm_odm); + _iqk_afe_setting_8822b(p_dm_odm, true); + _iqk_rfe_setting_8822b(p_dm_odm, false); + _iqk_agc_bnd_int_8822b(p_dm_odm); + _iqk_rf_setting_8822b(p_dm_odm); +#endif + + while (1) { + if (!is_mp) + p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm); + + _iqk_configure_macbb_8822b(p_dm_odm); + _iqk_afe_setting_8822b(p_dm_odm, true); + _iqk_rfe_setting_8822b(p_dm_odm, false); + _iqk_agc_bnd_int_8822b(p_dm_odm); + _iqk_rf_setting_8822b(p_dm_odm); + + _iqk_start_iqk_8822b(p_dm_odm, segment_iqk); + + _iqk_afe_setting_8822b(p_dm_odm, false); + _iqk_restore_mac_bb_8822b(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg); + _iqk_restore_rf_8822b(p_dm_odm, backup_rf_reg, RF_backup); + + if (!is_mp) { + p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); + p_dm_odm->rf_calibrate_info.iqk_total_progressing_time += odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]IQK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_progressing_time)); + } + + if (p_dm_odm->rf_calibrate_info.iqk_step == 7) + break; + + p_iqk_info->kcount = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]delay 50ms!!!\n")); + ODM_delay_ms(50); + }; + + if (segment_iqk) + _iqk_reload_iqk_setting_8822b(p_dm_odm, 0x0, 0x1); +#if 0 + _iqk_afe_setting_8822b(p_dm_odm, false); + _iqk_restore_mac_bb_8822b(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg); + _iqk_restore_rf_8822b(p_dm_odm, backup_rf_reg, RF_backup); +#endif + _iqk_fill_iqk_report_8822b(p_dm_odm, 0); + + _iqk_rf0xb0_workaround(p_dm_odm); + + if (!is_mp) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Total IQK progressing_time = %lld ms\n", + p_dm_odm->rf_calibrate_info.iqk_total_progressing_time)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]==========IQK end!!!!!==========\n")); +} + + +void +_phy_iq_calibrate_by_fw_8822b( + void *p_dm_void, + u8 clear +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + enum hal_status status = HAL_STATUS_FAILURE; + u8 segment_iqk = 0x0; + + if (*(p_dm_odm->p_mp_mode)) + clear = 0x1; + else if (p_dm_odm->is_linked) + segment_iqk = 0x0; + + p_iqk_info->iqk_times++; + status = odm_iq_calibrate_by_fw(p_dm_odm, clear, segment_iqk); + + if (status == HAL_STATUS_SUCCESS) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]FWIQK OK!!!\n")); + else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]FWIQK fail!!!\n")); +} + +/*IQK_version:0x29 NCTL:0x8*/ +/*1.reset bb report*/ +/*2.check if rf0x8 is expected*/ +void +phy_iq_calibrate_8822b( + void *p_dm_void, + boolean clear +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#else + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); +#endif + +#if (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT p_mpt_ctx = &(p_adapter->MptCtx); +#else + PMPT_CONTEXT p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(p_rf->rf_supportability & HAL_RF_IQK)) + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if (odm_check_power_status(p_adapter) == false) + return; +#endif + +#if MP_DRIVER == 1 +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (p_mpt_ctx->bSingleTone || p_mpt_ctx->bCarrierSuppression) + return; +#else + if (p_mpt_ctx->is_single_tone || p_mpt_ctx->is_carrier_suppression) + return; +#endif +#endif +#endif + /*p_dm_odm->iqk_fw_offload = 0;*/ + /*FW IQK*/ + if (p_dm_odm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) { + if (!p_dm_odm->rf_calibrate_info.is_iqk_in_progress) { + odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true; + odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + + p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm); + _phy_iq_calibrate_by_fw_8822b(p_dm_odm, clear); + phydm_get_read_counter(p_dm_odm); + p_dm_odm->rf_calibrate_info.iqk_total_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_total_progressing_time)); + + odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); + + } else { + _iq_calibrate_8822b_init(p_dm_void); + if (!p_dm_odm->rf_calibrate_info.is_iqk_in_progress) { + odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true; + odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + + if (*(p_dm_odm->p_mp_mode)) + p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm); +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + _phy_iq_calibrate_8822b(p_dm_odm, clear); + /*DBG_871X("%s,%d, do IQK %u ms\n", __func__, __LINE__, rtw_get_passing_time_ms(time_iqk));*/ +#else + _phy_iq_calibrate_8822b(p_dm_odm, clear); +#endif + if (*(p_dm_odm->p_mp_mode)) { + p_dm_odm->rf_calibrate_info.iqk_total_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_total_progressing_time)); + } + + odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]== Return the IQK CMD, because the IQK in Progress ==\n")); + } +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + _iqk_iqk_fail_report_8822b(p_dm_odm); +#endif +} + +#endif diff --git a/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h new file mode 100644 index 0000000..9f5de92 --- /dev/null +++ b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h @@ -0,0 +1,68 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PHYDM_IQK_8822B_H__ +#define __PHYDM_IQK_8822B_H__ + +#if (RTL8822B_SUPPORT == 1) + +#define IQK_VERSION_8822B "0x28" +/*--------------------------Define Parameters-------------------------------*/ +#define MAC_REG_NUM_8822B 2 +#define BB_REG_NUM_8822B 14 +#define RF_REG_NUM_8822B 5 +#define LOK_delay_8822B 2 +#define GS_delay_8822B 2 +#define WBIQK_delay_8822B 2 + +#define TXIQK 0 +#define RXIQK 1 +#define SS_8822B 2 +/*---------------------------End Define Parameters-------------------------------*/ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +void +do_iqk_8822b( + void *p_dm_void, + u8 delta_thermal_index, + u8 thermal_value, + u8 threshold +); +#else +void +do_iqk_8822b( + void *p_dm_void, + u8 delta_thermal_index, + u8 thermal_value, + u8 threshold +); +#endif + +void +phy_iq_calibrate_8822b( + void *p_dm_void, + boolean clear +); + +#else /* (RTL8822B_SUPPORT == 0)*/ + +#define phy_iq_calibrate_8822b(_pdm_void, clear) + +#endif /* RTL8822B_SUPPORT */ + +#endif /* #ifndef __PHYDM_IQK_8822B_H__*/ diff --git a/hal/phydm/phydm.mk b/hal/phydm/phydm.mk new file mode 100644 index 0000000..499a7b0 --- /dev/null +++ b/hal/phydm/phydm.mk @@ -0,0 +1,157 @@ +EXTRA_CFLAGS += -I$(src)/hal/phydm + +_PHYDM_FILES := hal/phydm/phydm_debug.o \ + hal/phydm/phydm_antdiv.o\ + hal/phydm/phydm_antdect.o\ + hal/phydm/phydm_interface.o\ + hal/phydm/phydm_hwconfig.o\ + hal/phydm/phydm.o\ + hal/phydm/phydm_dig.o\ + hal/phydm/phydm_pathdiv.o\ + hal/phydm/phydm_rainfo.o\ + hal/phydm/phydm_dynamicbbpowersaving.o\ + hal/phydm/phydm_dynamictxpower.o\ + hal/phydm/phydm_adaptivity.o\ + hal/phydm/phydm_cfotracking.o\ + hal/phydm/phydm_noisemonitor.o\ + hal/phydm/phydm_acs.o\ + hal/phydm/phydm_beamforming.o\ + hal/phydm/phydm_dfs.o\ + hal/phydm/txbf/halcomtxbf.o\ + hal/phydm/txbf/haltxbfinterface.o\ + hal/phydm/txbf/phydm_hal_txbf_api.o\ + hal/phydm/phydm_adc_sampling.o\ + hal/phydm/phydm_ccx.o\ + hal/phydm/phydm_psd.o\ + hal/phydm/halrf/halrf.o\ + hal/phydm/halrf/halphyrf_ce.o\ + hal/phydm/halrf/halrf_powertracking_ce.o\ + hal/phydm/halrf/halrf_kfree.o + +ifeq ($(CONFIG_RTL8188E), y) +RTL871X = rtl8188e +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\ + hal/phydm/$(RTL871X)/hal8188erateadaptive.o\ + hal/phydm/$(RTL871X)/phydm_rtl8188e.o +endif + +ifeq ($(CONFIG_RTL8192E), y) +RTL871X = rtl8192e +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\ + hal/phydm/$(RTL871X)/phydm_rtl8192e.o +endif + + +ifeq ($(CONFIG_RTL8812A), y) +RTL871X = rtl8812a +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\ + hal/phydm/$(RTL871X)/phydm_rtl8812a.o\ + hal/phydm/txbf/haltxbfjaguar.o +endif + +ifeq ($(CONFIG_RTL8821A), y) +RTL871X = rtl8821a +_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\ + hal/phydm/rtl8821a/halhwimg8821a_bb.o\ + hal/phydm/rtl8821a/halhwimg8821a_rf.o\ + hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\ + hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\ + hal/phydm/rtl8821a/phydm_regconfig8821a.o\ + hal/phydm/rtl8821a/phydm_rtl8821a.o\ + hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\ + hal/phydm/txbf/haltxbfjaguar.o +endif + + +ifeq ($(CONFIG_RTL8723B), y) +RTL871X = rtl8723b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\ + hal/phydm/$(RTL871X)/phydm_rtl8723b.o +endif + + +ifeq ($(CONFIG_RTL8814A), y) +RTL871X = rtl8814a +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\ + hal/phydm/$(RTL871X)/phydm_rtl8814a.o\ + hal/phydm/txbf/haltxbf8814a.o +endif + + +ifeq ($(CONFIG_RTL8723C), y) +RTL871X = rtl8703b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8703b.o +endif + +ifeq ($(CONFIG_RTL8723D), y) +RTL871X = rtl8723d +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\ + hal/phydm/$(RTL871X)/phydm_rtl8723d.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8723d.o +endif + + +ifeq ($(CONFIG_RTL8188F), y) +RTL871X = rtl8188f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \ + hal/phydm/$(RTL871X)/phydm_rtl8188f.o +endif + +ifeq ($(CONFIG_RTL8822B), y) +RTL871X = rtl8822b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \ + hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \ + hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \ + hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \ + hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \ + hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \ + hal/phydm/$(RTL871X)/phydm_rtl8822b.o + +_PHYDM_FILES += hal/phydm/txbf/haltxbf8822b.o +endif + + +ifeq ($(CONFIG_RTL8821C), y) +RTL871X = rtl8821c +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \ + hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \ + hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \ + hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \ + hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o +endif \ No newline at end of file diff --git a/hal/phydm/phydm_dynamic_rx_path.c b/hal/phydm/phydm_dynamic_rx_path.c new file mode 100644 index 0000000..ed32eed --- /dev/null +++ b/hal/phydm/phydm_dynamic_rx_path.c @@ -0,0 +1,352 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (CONFIG_DYNAMIC_RX_PATH == 1) + +void +phydm_process_phy_status_for_dynamic_rx_path( + void *p_dm_void, + void *p_phy_info_void, + void *p_pkt_info_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; + struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + /*u8 is_cck_rate=0;*/ + + + +} + +void +phydm_drp_get_statistic( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + + odm_false_alarm_counter_statistics(p_dm_odm); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all)); +} + +void +phydm_dynamic_rx_path( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + u8 training_set_timmer_en; + u8 curr_drp_state; + u32 rx_ok_cal; + u32 RSSI = 0; + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + + if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Return Init] Not Support Dynamic RX PAth\n")); + return; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("Current drp_state = ((%d))\n", p_dm_drp_table->drp_state)); + + curr_drp_state = p_dm_drp_table->drp_state; + + if (p_dm_drp_table->drp_state == DRP_INIT_STATE) { + + phydm_drp_get_statistic(p_dm_odm); + + if (false_alm_cnt->cnt_crc32_ok_all > 20) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Stop DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all)); + p_dm_drp_table->drp_state = DRP_INIT_STATE; + training_set_timmer_en = false; + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Start DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all)); + p_dm_drp_table->drp_state = DRP_TRAINING_STATE_0; + p_dm_drp_table->curr_rx_path = PHYDM_AB; + training_set_timmer_en = true; + } + + } else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_0) { + + phydm_drp_get_statistic(p_dm_odm); + + p_dm_drp_table->curr_cca_all_cnt_0 = false_alm_cnt->cnt_cca_all; + p_dm_drp_table->curr_fa_all_cnt_0 = false_alm_cnt->cnt_all; + + p_dm_drp_table->drp_state = DRP_TRAINING_STATE_1; + p_dm_drp_table->curr_rx_path = PHYDM_B; + training_set_timmer_en = true; + + } else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_1) { + + phydm_drp_get_statistic(p_dm_odm); + + p_dm_drp_table->curr_cca_all_cnt_1 = false_alm_cnt->cnt_cca_all; + p_dm_drp_table->curr_fa_all_cnt_1 = false_alm_cnt->cnt_all; + +#if 1 + p_dm_drp_table->drp_state = DRP_DECISION_STATE; +#else + + if (*(p_dm_odm->p_mp_mode)) { + rx_ok_cal = p_dm_odm->phy_dbg_info.num_qry_phy_status_cck + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm; + RSSI = (rx_ok_cal != 0) ? p_dm_odm->rx_pwdb_ave / rx_ok_cal : 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("MP RSSI = ((%d))\n", RSSI)); + } + + if (RSSI > p_dm_drp_table->rssi_threshold) + + p_dm_drp_table->drp_state = DRP_DECISION_STATE; + + else { + + p_dm_drp_table->drp_state = DRP_TRAINING_STATE_2; + p_dm_drp_table->curr_rx_path = PHYDM_A; + training_set_timmer_en = true; + } +#endif + } else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_2) { + + phydm_drp_get_statistic(p_dm_odm); + + p_dm_drp_table->curr_cca_all_cnt_2 = false_alm_cnt->cnt_cca_all; + p_dm_drp_table->curr_fa_all_cnt_2 = false_alm_cnt->cnt_all; + p_dm_drp_table->drp_state = DRP_DECISION_STATE; + } + + if (p_dm_drp_table->drp_state == DRP_DECISION_STATE) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("Current drp_state = ((%d))\n", p_dm_drp_table->drp_state)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[0] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_0, p_dm_drp_table->curr_fa_all_cnt_0)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[1] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_1, p_dm_drp_table->curr_fa_all_cnt_1)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[2] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_2, p_dm_drp_table->curr_fa_all_cnt_2)); + + if (p_dm_drp_table->curr_fa_all_cnt_1 < p_dm_drp_table->curr_fa_all_cnt_0) { + + if ((p_dm_drp_table->curr_fa_all_cnt_0 - p_dm_drp_table->curr_fa_all_cnt_1) > p_dm_drp_table->fa_diff_threshold) + p_dm_drp_table->curr_rx_path = PHYDM_B; + else + p_dm_drp_table->curr_rx_path = PHYDM_AB; + } else + p_dm_drp_table->curr_rx_path = PHYDM_AB; + + phydm_config_ofdm_rx_path(p_dm_odm, p_dm_drp_table->curr_rx_path); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Training Result] curr_rx_path = ((%s%s)),\n", + ((p_dm_drp_table->curr_rx_path & PHYDM_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & PHYDM_B) ? "B" : " "))); + + p_dm_drp_table->drp_state = DRP_INIT_STATE; + training_set_timmer_en = false; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("DRP_state: ((%d)) -> ((%d))\n", curr_drp_state, p_dm_drp_table->drp_state)); + + if (training_set_timmer_en) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Training en] curr_rx_path = ((%s%s)), training_time = ((%d ms))\n", + ((p_dm_drp_table->curr_rx_path & PHYDM_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & PHYDM_B) ? "B" : " "), p_dm_drp_table->training_time)); + + phydm_config_ofdm_rx_path(p_dm_odm, p_dm_drp_table->curr_rx_path); + odm_set_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer), p_dm_drp_table->training_time); /*ms*/ + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("DRP period end\n\n", curr_drp_state, p_dm_drp_table->drp_state)); + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void +phydm_dynamic_rx_path_callback( + struct timer_list *p_timer +) +{ + struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &(p_hal_data->DM_OutSrc); + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +#if USE_WORKITEM + odm_schedule_work_item(&(p_dm_drp_table->phydm_dynamic_rx_path_workitem)); +#else + { + /* dbg_print("phydm_dynamic_rx_path\n"); */ + phydm_dynamic_rx_path(p_dm_odm); + } +#endif +#else + odm_schedule_work_item(&(p_dm_drp_table->phydm_dynamic_rx_path_workitem)); +#endif +} + +void +phydm_dynamic_rx_path_workitem_callback( + void *p_context +) +{ + struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct PHY_DM_STRUCT *p_dm_odm = &(p_hal_data->DM_OutSrc); + + /* dbg_print("phydm_dynamic_rx_path\n"); */ + phydm_dynamic_rx_path(p_dm_odm); +} +#else if (DM_ODM_SUPPORT_TYPE == ODM_CE) + +void +phydm_dynamic_rx_path_callback( + void *function_context +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)function_context; + struct _ADAPTER *padapter = p_dm_odm->adapter; + + if (padapter->net_closed == _TRUE) + return; + +#if 0 /* Can't do I/O in timer callback*/ + odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_DETERMINE); +#else + /*rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter);*/ +#endif +} + +#endif + +void +phydm_dynamic_rx_path_timers( + void *p_dm_void, + u8 state +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + + if (state == INIT_DRP_TIMMER) { + + odm_initialize_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer), + (void *)phydm_dynamic_rx_path_callback, NULL, "phydm_sw_antenna_switch_timer"); + } else if (state == CANCEL_DRP_TIMMER) + + odm_cancel_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer)); + + else if (state == RELEASE_DRP_TIMMER) + + odm_release_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer)); + +} + +void +phydm_dynamic_rx_path_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + boolean ret_value; + + if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Return] Not Support Dynamic RX PAth\n")); + return; + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("phydm_dynamic_rx_path_init\n")); + + p_dm_drp_table->drp_state = DRP_INIT_STATE; + p_dm_drp_table->rssi_threshold = DRP_RSSI_TH; + p_dm_drp_table->fa_count_thresold = 50; + p_dm_drp_table->fa_diff_threshold = 50; + p_dm_drp_table->training_time = 100; /*ms*/ + p_dm_drp_table->drp_skip_counter = 0; + p_dm_drp_table->drp_period = 0; + p_dm_drp_table->drp_init_finished = true; + + ret_value = phydm_api_trx_mode(p_dm_odm, (enum odm_rf_path_e)(ODM_RF_A | ODM_RF_B), (enum odm_rf_path_e)(ODM_RF_A | ODM_RF_B), true); + +} + +void +phydm_drp_debug( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + + switch (dm_value[0]) { + + case DRP_TRAINING_TIME: + p_dm_drp_table->training_time = (u16)dm_value[1]; + break; + case DRP_TRAINING_PERIOD: + p_dm_drp_table->drp_period = (u8)dm_value[1]; + break; + case DRP_RSSI_THRESHOLD: + p_dm_drp_table->rssi_threshold = (u8)dm_value[1]; + break; + case DRP_FA_THRESHOLD: + p_dm_drp_table->fa_count_thresold = dm_value[1]; + break; + case DRP_FA_DIFF_THRESHOLD: + p_dm_drp_table->fa_diff_threshold = dm_value[1]; + break; + default: + PHYDM_SNPRINTF((output + used, out_len - used, "[DRP] unknown command\n")); + break; +} +} + +void +phydm_dynamic_rx_path_caller( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + + if (p_dm_drp_table->drp_skip_counter < p_dm_drp_table->drp_period) + p_dm_drp_table->drp_skip_counter++; + else + p_dm_drp_table->drp_skip_counter = 0; + + if (p_dm_drp_table->drp_skip_counter != 0) + return; + + if (p_dm_drp_table->drp_init_finished != true) + return; + + phydm_dynamic_rx_path(p_dm_odm); + +} +#endif diff --git a/hal/phydm/phydm_dynamic_rx_path.h b/hal/phydm/phydm_dynamic_rx_path.h new file mode 100644 index 0000000..fa9e794 --- /dev/null +++ b/hal/phydm/phydm_dynamic_rx_path.h @@ -0,0 +1,141 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __PHYDMDYMICRXPATH_H__ +#define __PHYDMDYMICRXPATH_H__ + +#define DYNAMIC_RX_PATH_VERSION "1.0" /*2016.07.15 Dino */ + + +#define DRP_RSSI_TH 35 + +#define INIT_DRP_TIMMER 0 +#define CANCEL_DRP_TIMMER 1 +#define RELEASE_DRP_TIMMER 2 + +#if (RTL8822B_SUPPORT == 1) +struct phydm_rtl8822b_struct { + enum odm_rf_path_e path_judge; + u16 path_a_cck_fa; + u16 path_b_cck_fa; + +}; +#endif + +#if (CONFIG_DYNAMIC_RX_PATH == 1) + +enum drp_state_e { + DRP_INIT_STATE = 0, + DRP_TRAINING_STATE_0 = 1, + DRP_TRAINING_STATE_1 = 2, + DRP_TRAINING_STATE_2 = 3, + DRP_DECISION_STATE = 4 +}; + +enum adjustable_value_e { + DRP_TRAINING_TIME = 0, + DRP_TRAINING_PERIOD = 1, + DRP_RSSI_THRESHOLD = 2, + DRP_FA_THRESHOLD = 3, + DRP_FA_DIFF_THRESHOLD = 4 +}; + +struct _DYNAMIC_RX_PATH_ { + u8 curr_rx_path; + u8 drp_state; + u16 training_time; + u8 rssi_threshold; + u32 fa_count_thresold; + u32 fa_diff_threshold; + u32 curr_cca_all_cnt_0; + u32 curr_fa_all_cnt_0; + u32 curr_cca_all_cnt_1; + u32 curr_fa_all_cnt_1; + u32 curr_cca_all_cnt_2; + u32 curr_fa_all_cnt_2; + u8 drp_skip_counter; + u8 drp_period; + u8 drp_init_finished; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if USE_WORKITEM + RT_WORK_ITEM phydm_dynamic_rx_path_workitem; +#endif +#endif + struct timer_list phydm_dynamic_rx_path_timer; + +}; + + + +void +phydm_process_phy_status_for_dynamic_rx_path( + void *p_dm_void, + void *p_phy_info_void, + void *p_pkt_info_void +); + +void +phydm_dynamic_rx_path( + void *p_dm_void +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void +phydm_dynamic_rx_path_callback( + struct timer_list *p_timer +); + +void +phydm_dynamic_rx_path_workitem_callback( + void *p_context +); + +#else if (DM_ODM_SUPPORT_TYPE == ODM_CE) + +void +phydm_dynamic_rx_path_callback( + void *function_context +); + +#endif + +void +phydm_dynamic_rx_path_timers( + void *p_dm_void, + u8 state +); + +void +phydm_dynamic_rx_path_init( + void *p_dm_void +); + +void +phydm_drp_debug( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +void +phydm_dynamic_rx_path_caller( + void *p_dm_void +); + +#endif +#endif diff --git a/hal/phydm/phydm_psd.c b/hal/phydm/phydm_psd.c new file mode 100644 index 0000000..f870621 --- /dev/null +++ b/hal/phydm/phydm_psd.c @@ -0,0 +1,439 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (CONFIG_PSD_TOOL == 1) + +u32 +phydm_get_psd_data( + void *p_dm_void, + u32 psd_tone_idx, + u32 igi + ) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); + u32 psd_report = 0; + + odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, 0x3ff, psd_tone_idx); + + odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, BIT(22), 1); /*PSD trigger start*/ + ODM_delay_us(10); + odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, BIT(22), 0); /*PSD trigger stop*/ + + psd_report = odm_get_bb_reg(p_dm_odm, p_dm_psd_table->psd_report_reg, 0xffff); + psd_report = odm_convert_to_db(psd_report) + igi; + + return psd_report; +} + +u8 +phydm_psd_stop_trx( + void *p_dm_void + ) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 i; + u8 trx_idle_success = false; + u32 dbg_port_value = 0; + + /*[Stop TRX]---------------------------------------------------------------------*/ + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_3, 0x0) == false) /*set debug port to 0x0*/ + return STOP_TRX_FAIL; + + for (i = 0; i<10000; i++) { + dbg_port_value = phydm_get_bb_dbg_port_value(p_dm_odm); + if ((dbg_port_value & (BIT(17) | BIT(3))) == 0) /* PHYTXON && CCA_all */ { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD wait for ((%d)) times\n", i)); + + trx_idle_success = true; + break; + } + } + + if (trx_idle_success) { + + odm_set_bb_reg(p_dm_odm, 0x520, 0xff0000, 0xff); /*pause all TX queue*/ + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0); /*disable CCK block*/ + odm_set_bb_reg(p_dm_odm, 0x838, BIT(1), 1); /*disable OFDM RX CCA*/ + } else { + /*TBD*/ + odm_set_bb_reg(p_dm_odm, 0x800, BIT(24), 0); /* disable whole CCK block */ + odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */ + } + + } else { + return STOP_TRX_FAIL; + } + + phydm_release_bb_dbg_port(p_dm_odm); + + return STOP_TRX_SUCCESS; + +} + +u8 psd_result_cali_tone_8821[7]= {21, 28, 33, 93, 98, 105, 127}; +u8 psd_result_cali_val_8821[7] = {67,69,71,72,71,69,67}; + +void +phydm_psd( + void *p_dm_void, + u32 igi, + u16 start_point, + u16 stop_point + ) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); + u32 i = 0, mod_tone_idx; + u32 t = 0; + u16 fft_max_half_bw; + u32 psd_igi_a_reg; + u32 psd_igi_b_reg; + u16 psd_fc_channel = p_dm_psd_table->psd_fc_channel; + u8 ag_rf_mode_reg = 0; + u8 rf_reg18_9_8 = 0; + u32 psd_result_tmp = 0; + u8 psd_result = 0; + u8 psd_result_cali_tone[7] = {0}; + u8 psd_result_cali_val[7] = {0}; + u8 noise_table_idx = 0; + + if (p_dm_odm->support_ic_type == ODM_RTL8821) { + odm_move_memory(p_dm_odm, psd_result_cali_tone, psd_result_cali_tone_8821, 7); + odm_move_memory(p_dm_odm, psd_result_cali_val, psd_result_cali_val_8821, 7); + } + + p_dm_psd_table->psd_in_progress = 1; + + /*[Stop DIG]*/ + p_dm_odm->support_ability &= ~(ODM_BB_DIG); + p_dm_odm->support_ability &= ~(ODM_BB_FA_CNT); + + + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD Start =>\n")); + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + psd_igi_a_reg = 0xc50; + psd_igi_b_reg = 0xe50; + } else { + psd_igi_a_reg = 0xc50; + psd_igi_b_reg = 0xc58; + } + + /*[back up IGI]*/ + p_dm_psd_table->initial_gain_backup = odm_get_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff); + odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/ + odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/ + ODM_delay_us(10); + + if (phydm_psd_stop_trx(p_dm_odm) == STOP_TRX_FAIL) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("STOP_TRX_FAIL\n")); + return; + } + + /*[Set IGI]*/ + odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, igi); + odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, igi); + + /*[Backup RF Reg]*/ + p_dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + + if (psd_fc_channel > 14) { + + rf_reg18_9_8 = 1; + + if (36 <= psd_fc_channel && psd_fc_channel <= 64) + ag_rf_mode_reg = 0x1; + else if (100 <= psd_fc_channel && psd_fc_channel <= 140) + ag_rf_mode_reg = 0x3; + else if (140 < psd_fc_channel) + ag_rf_mode_reg = 0x5; + } + + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xff, psd_fc_channel); /* Set RF fc*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0x300, rf_reg18_9_8); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xc00, p_dm_psd_table->psd_bw_rf_reg); /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xf0000, ag_rf_mode_reg); /* Set RF ag fc mode*/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("0xc50=((0x%x))\n", odm_get_bb_reg(p_dm_odm, 0xc50, MASKDWORD))); + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("RF0x0=((0x%x))\n", odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, RFREGOFFSETMASK)));*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("RF0x18=((0x%x))\n", odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK))); + + /*[Stop 3-wires]*/ + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, 0xc00, 0xf, 0x4);/* hardware 3-wire off */ + odm_set_bb_reg(p_dm_odm, 0xe00, 0xf, 0x4);/* hardware 3-wire off */ + } else { + odm_set_bb_reg(p_dm_odm, 0x88c, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ + } + ODM_delay_us(10); + + if (stop_point > (p_dm_psd_table->fft_smp_point-1)) + stop_point = (p_dm_psd_table->fft_smp_point-1); + + if (start_point > (p_dm_psd_table->fft_smp_point-1)) + start_point = (p_dm_psd_table->fft_smp_point-1); + + if (start_point > stop_point) + stop_point = start_point; + + + for (i = start_point; i <= stop_point; i++ ) { + + fft_max_half_bw = (p_dm_psd_table->fft_smp_point)>>1; + + if (i < fft_max_half_bw) { + mod_tone_idx = i + fft_max_half_bw; + } else { + mod_tone_idx = i - fft_max_half_bw; + } + + psd_result_tmp = 0; + for (t = 0; t < p_dm_psd_table->sw_avg_time; t++) { + psd_result_tmp += phydm_get_psd_data(p_dm_odm, mod_tone_idx, igi); + /**/ + } + psd_result = (u8)((psd_result_tmp/p_dm_psd_table->sw_avg_time)) - p_dm_psd_table->psd_pwr_common_offset; + + if( p_dm_psd_table->fft_smp_point == 128 && (p_dm_psd_table->noise_k_en)) { + + if (i > psd_result_cali_tone[noise_table_idx]) { + noise_table_idx ++; + } + + if (noise_table_idx > 6) + noise_table_idx = 6; + + if (psd_result >= psd_result_cali_val[noise_table_idx]) + psd_result = psd_result - psd_result_cali_val[noise_table_idx]; + else + psd_result = 0; + + + p_dm_psd_table->psd_result[i] = psd_result; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[%d] N_cali = %d, PSD = %d\n", mod_tone_idx, psd_result_cali_val[noise_table_idx], psd_result)); + + } + + /*[Start 3-wires]*/ + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, 0xc00, 0xf, 0x7);/* hardware 3-wire on */ + odm_set_bb_reg(p_dm_odm, 0xe00, 0xf, 0x7);/* hardware 3-wire on */ + } else { + odm_set_bb_reg(p_dm_odm, 0x88c, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ + } + ODM_delay_us(10); + + /*[Revert Reg]*/ + odm_set_bb_reg(p_dm_odm, 0x520, 0xff0000, 0x0); /*start all TX queue*/ + odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 1); /*enable CCK block*/ + odm_set_bb_reg(p_dm_odm, 0x838, BIT(1), 0); /*enable OFDM RX CCA*/ + + odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, p_dm_psd_table->initial_gain_backup); + odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, p_dm_psd_table->initial_gain_backup); + + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, p_dm_psd_table->rf_0x18_bkp); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD finished\n\n")); + + p_dm_odm->support_ability |= ODM_BB_DIG; + p_dm_odm->support_ability |= ODM_BB_FA_CNT; + p_dm_psd_table->psd_in_progress = 0; + + +} + +void +phydm_psd_para_setting( + void *p_dm_void, + u8 sw_avg_time, + u8 hw_avg_time, + u8 i_q_setting, + u16 fft_smp_point, + u8 ant_sel, + u8 psd_input, + u8 channel, + u8 noise_k_en + ) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); + u8 fft_smp_point_idx = 0; + + p_dm_psd_table->fft_smp_point = fft_smp_point; + + if (sw_avg_time == 0) + sw_avg_time = 1; + + p_dm_psd_table->sw_avg_time = sw_avg_time; + p_dm_psd_table->psd_fc_channel = channel; + p_dm_psd_table->noise_k_en = noise_k_en; + + if (fft_smp_point == 128) + fft_smp_point_idx = 0; + else if (fft_smp_point == 256) + fft_smp_point_idx = 1; + else if (fft_smp_point == 512) + fft_smp_point_idx = 2; + else if (fft_smp_point == 1024) + fft_smp_point_idx = 3; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0x910, BIT(11) | BIT(10), i_q_setting); + odm_set_bb_reg(p_dm_odm, 0x910, BIT(13) | BIT(12), hw_avg_time); + odm_set_bb_reg(p_dm_odm, 0x910, BIT(15) | BIT(14), fft_smp_point_idx); + odm_set_bb_reg(p_dm_odm, 0x910, BIT(17) | BIT(16), ant_sel); + odm_set_bb_reg(p_dm_odm, 0x910, BIT(23), psd_input); + + } else { + + } + + /*bw = (*p_dm_odm->p_band_width); //ODM_BW20M */ + /*channel = *(p_dm_odm->p_channel);*/ + + + + +} + +void +phydm_psd_init( + void *p_dm_void + ) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD para init\n")); + + p_dm_psd_table->psd_in_progress = false; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + p_dm_psd_table->psd_reg = 0x910; + p_dm_psd_table->psd_report_reg = 0xF44; + + if (ODM_IC_11AC_2_SERIES) + p_dm_psd_table->psd_bw_rf_reg = 1; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + else + p_dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + + } else { + + p_dm_psd_table->psd_reg = 0x808; + p_dm_psd_table->psd_report_reg = 0x8B4; + p_dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + } + + if (p_dm_odm->support_ic_type == ODM_RTL8812) + p_dm_psd_table->psd_pwr_common_offset = 0; + else if (p_dm_odm->support_ic_type == ODM_RTL8821) + p_dm_psd_table->psd_pwr_common_offset = 0; + else + p_dm_psd_table->psd_pwr_common_offset = 0; + + phydm_psd_para_setting(p_dm_odm, 1, 2, 3, 128, 0, 0, 7, 0); + /*phydm_psd(p_dm_odm, 0x3c, 0, 127);*/ /* target at -50dBm */ + + +} + +void +phydm_psd_debug( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + if ((strcmp(input[1], help) == 0)) { + PHYDM_SNPRINTF((output + used, out_len - used, "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "{1} {IGI(hex)} {start_point} {stop_point}\n")); + + } else { + + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 0) { + + for (i = 1; i < 10; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + } + + PHYDM_SNPRINTF((output + used, out_len - used, "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n", + var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], (u8)var1[7], (u8)var1[8])); + phydm_psd_para_setting(p_dm_odm, (u8)var1[1], (u8)var1[2], (u8)var1[3], (u16)var1[4], (u8)var1[5], (u8)var1[6], (u8)var1[7], (u8)var1[8]); + + } else if (var1[0] == 1) { + + PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]); + PHYDM_SNPRINTF((output + used, out_len - used, "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n", var1[1], var1[2], var1[3])); + p_dm_odm->debug_components |= ODM_COMP_API; + phydm_psd(p_dm_odm, var1[1], (u16)var1[2], (u16)var1[3]); + p_dm_odm->debug_components &= (~ODM_COMP_API); + } + + } + + + +} + +u8 +phydm_get_psd_result_table( + void *p_dm_void, + int index + ) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); + u8 temp_result = 0; + + if(index<128) + temp_result = p_dm_psd_table->psd_result[index]; + + return temp_result; + +} + +#endif + diff --git a/hal/phydm/phydm_psd.h b/hal/phydm/phydm_psd.h new file mode 100644 index 0000000..80d3617 --- /dev/null +++ b/hal/phydm/phydm_psd.h @@ -0,0 +1,96 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __PHYDMPSD_H__ +#define __PHYDMPSD_H__ + +/*#define PSD_VERSION "1.0"*/ /*2016.09.22 Dino*/ +#define PSD_VERSION "1.1" /*2016.10.07 Dino, Add Option for PSD Tone index Selection */ + +#if (CONFIG_PSD_TOOL == 1) + + +#define STOP_TRX_SUCCESS 1 +#define STOP_TRX_FAIL 0 + + +struct _PHYDM_PSD_ { + + u8 psd_in_progress; + u32 psd_reg; + u32 psd_report_reg; + u8 psd_pwr_common_offset; + u16 sw_avg_time; + u16 fft_smp_point; + u32 initial_gain_backup; + u32 rf_0x18_bkp; + u16 psd_fc_channel; + u32 psd_bw_rf_reg; + u8 psd_result[128]; + u8 noise_k_en; +}; + +u32 +phydm_get_psd_data( + void *p_dm_void, + u32 psd_tone_idx, + u32 igi +); + +void +phydm_psd_debug( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); + +void +phydm_psd( + void *p_dm_void, + u32 igi, + u16 start_point, + u16 stop_point +); + +void +phydm_psd_para_setting( + void *p_dm_void, + u8 sw_avg_time, + u8 hw_avg_time, + u8 i_q_setting, + u16 fft_smp_point, + u8 ant_sel, + u8 psd_input, + u8 channel, + u8 noise_k_en +); + +void +phydm_psd_init( + void *p_dm_void +); + +u8 +phydm_get_psd_result_table( + void *p_dm_void, + int index +); + +#endif +#endif + diff --git a/hal/phydm/rtl8822b/mp_precomp.h b/hal/phydm/rtl8822b/mp_precomp.h new file mode 100644 index 0000000..fa483c6 --- /dev/null +++ b/hal/phydm/rtl8822b/mp_precomp.h @@ -0,0 +1,19 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ diff --git a/hal/phydm/rtl8822b/phydm_rtl8822b_ram.c b/hal/phydm/rtl8822b/phydm_rtl8822b_ram.c new file mode 100644 index 0000000..55c568f --- /dev/null +++ b/hal/phydm/rtl8822b/phydm_rtl8822b_ram.c @@ -0,0 +1,7 @@ +//alex temp disable for merge, 20160328 +//#include "phydm_precomp.h" + +//__iram_odm_func__ void phydm_InitFuncPtrTableRAM8822B(void){ + + +//} \ No newline at end of file diff --git a/hal/phydm/rtl8822b/phydm_rtl8822b_ram.h b/hal/phydm/rtl8822b/phydm_rtl8822b_ram.h new file mode 100644 index 0000000..908a549 --- /dev/null +++ b/hal/phydm/rtl8822b/phydm_rtl8822b_ram.h @@ -0,0 +1,34 @@ +#ifndef __PHYDM_RTL8822B_RAM_H__ +#define __PHYDM_RTL8822B_RAM_H__ + +//============================================================ +//3 +//3 This file defines 8822B RAM code function pointer +//3 +//============================================================ + +//#define phydm_InitFuncPtrTableRAM phydm_InitFuncPtrTableRAM8822B + +//void phydm_InitFuncPtrTableRAM8822B(void); + +#if IS_CUT_TEST(CONFIG_CHIP_SEL) +#define FW_FIFO_Parsing_pu1Byte FW_FIFO_Parsing_pu1Byte_RAM +#define odm_ConvertTo_dB odm_ConvertTo_dB_RAM +#define odm_ConvertTo_linear odm_ConvertTo_linear_RAM +#define odm_QueryRxPwrPercentage odm_QueryRxPwrPercentage_RAM +#define odm_EVMdbToPercentage odm_EVMdbToPercentage_RAM +#define phydm_ResetPhyInfo phydm_ResetPhyInfo_RAM +#define phydm_SetPerPathPhyInfo phydm_SetPerPathPhyInfo_RAM +#define phydm_SetCommonPhyInfo phydm_SetCommonPhyInfo_RAM +#define phydm_GetRxPhyStatusType0 phydm_GetRxPhyStatusType0_RAM +#define phydm_GetRxPhyStatusType1 phydm_GetRxPhyStatusType1_RAM +#define phydm_GetRxPhyStatusType2 phydm_GetRxPhyStatusType2_RAM +#define phydm_GetRxPhyStatusType5 phydm_GetRxPhyStatusType5_RAM +#define phydm_Process_RSSIForDM_Jaguar2 phydm_Process_RSSIForDM_Jaguar2_RAM +#define phydm_RxPhyStatusJaguarSeries2 phydm_RxPhyStatusJaguarSeries2_RAM +#define phystatus_parsing phystatus_parsing_RAM +#elif IS_CUT_B(CONFIG_CHIP_SEL) + +#endif + +#endif //__PHYDM_RTL8821C_RAM_H__ \ No newline at end of file diff --git a/hal/rtl8822b/hal8822b_fw.c b/hal/rtl8822b/hal8822b_fw.c new file mode 100644 index 0000000..f935d13 --- /dev/null +++ b/hal/rtl8822b/hal8822b_fw.c @@ -0,0 +1,35364 @@ +/****************************************************************************** + * + * Copyright(c) 2015 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifdef CONFIG_RTL8822B + +#include "drv_types.h" + +#ifdef LOAD_FW_HEADER_FROM_DRIVER + +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) + +u8 array_mp_8822b_fw_ap[] = { +0x22, 0x88, 0x00, 0x00, 0x0D, 0x00, 0x01, 0x00, +0x67, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x03, 0x0D, 0x0F, 0x28, 0xE1, 0x07, 0x00, 0x00, +0x08, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, +0x00, 0x00, 0x20, 0x80, 0xC8, 0x28, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x48, 0x15, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x10, 0x12, 0x80, 0x00, 0x00, 0x00, 0x80, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 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0xB8, 0x9A, +0x61, 0xF0, 0x00, 0x6C, 0x00, 0xF4, 0x12, 0x6E, +0x00, 0x18, 0x4F, 0x32, 0x4B, 0x99, 0x40, 0xA2, +0x01, 0x72, 0x10, 0x61, 0x54, 0xA1, 0x03, 0x72, +0x02, 0x60, 0x05, 0x72, 0x0B, 0x61, 0x0E, 0x70, +0x05, 0x61, 0x91, 0x67, 0x26, 0x6D, 0x00, 0x18, +0xD8, 0x3E, 0xB6, 0x10, 0x91, 0x67, 0x20, 0x6D, +0x00, 0x18, 0xD8, 0x3E, 0x0F, 0x58, 0xA0, 0xF0, +0x0F, 0x61, 0x68, 0x40, 0xE4, 0x4B, 0xFF, 0x6A, +0x83, 0x67, 0x4C, 0xEC, 0x1D, 0x5C, 0x05, 0x60, +0x5D, 0x67, 0x67, 0x33, 0x6D, 0xE2, 0x58, 0xA3, +0x19, 0x10, 0x68, 0x40, 0xA4, 0x4B, 0x83, 0x67, +0x4C, 0xEC, 0x2D, 0x5C, 0x06, 0x60, 0x67, 0x33, +0x9D, 0x67, 0x6D, 0xE4, 0x20, 0xF0, 0x58, 0xA3, +0x0D, 0x10, 0x67, 0x40, 0x64, 0x4B, 0x4C, 0xEB, +0x1D, 0x5B, 0x80, 0xF0, 0x0B, 0x60, 0x6F, 0xF7, +0x4B, 0x40, 0x47, 0x32, 0x7D, 0x67, 0x49, 0xE3, +0x20, 0xF0, 0x48, 0xA2, 0xFF, 0x72, 0x80, 0xF0, +0x01, 0x60, 0x04, 0xD2, 0x30, 0xF0, 0x20, 0x6A, +0x01, 0xF0, 0xE0, 0x9A, 0x91, 0x67, 0x00, 0x6D, +0xBE, 0x6E, 0x00, 0x18, 0xE2, 0x40, 0x14, 0x94, +0x00, 0x6B, 0x01, 0x4C, 0x01, 0x24, 0x01, 0x6B, +0xFF, 0x6C, 0x4C, 0xEC, 0x6C, 0xEC, 0x90, 0x70, +0x14, 0xD4, 0x11, 0x61, 0x01, 0x6A, 0x04, 0xD2, +0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF5, 0xEC, 0x9A, +0x91, 0x67, 0x00, 0x6D, 0xDF, 0x6E, 0x00, 0x18, +0xE2, 0x40, 0x14, 0x93, 0xFF, 0x6C, 0x4C, 0xEB, +0x8C, 0xEB, 0x14, 0xD3, 0x1C, 0x10, 0x00, 0x6A, +0x04, 0xD2, 0xA2, 0x67, 0x30, 0xF0, 0x20, 0x6A, +0x20, 0xF5, 0x0C, 0x4A, 0xE0, 0x9A, 0x91, 0x67, +0xDF, 0x6E, 0x00, 0x18, 0xE2, 0x40, 0x14, 0x93, +0xFF, 0x6C, 0x91, 0x58, 0x4C, 0xEB, 0x8C, 0xEB, +0x14, 0xD3, 0x07, 0x61, 0x30, 0xF0, 0x20, 0x6A, +0x20, 0xF5, 0x0C, 0x4A, 0x15, 0x93, 0x40, 0x9A, +0x07, 0x10, 0x50, 0x58, 0x07, 0x61, 0x30, 0xF0, +0x20, 0x6A, 0x20, 0xF5, 0x48, 0x9A, 0x15, 0x93, +0x4D, 0xEB, 0x15, 0xD3, 0x30, 0xF0, 0x20, 0x6A, +0x15, 0x94, 0x80, 0xF7, 0x04, 0x4A, 0xE0, 0x9A, +0x04, 0xD4, 0x00, 0x6D, 0x91, 0x67, 0x18, 0x6E, +0x00, 0x18, 0xE2, 0x40, 0x14, 0x90, 0x4C, 0xE8, +0x4A, 0xA1, 0x0F, 0x22, 0x30, 0xF0, 0x20, 0x6A, +0x80, 0xF7, 0x04, 0x4A, 0x15, 0x93, 0xE0, 0x9A, +0x91, 0x67, 0x01, 0x6D, 0x18, 0x6E, 0x04, 0xD3, +0x00, 0x18, 0xE2, 0x40, 0x4C, 0xE8, 0xFF, 0x6A, +0x4C, 0xE8, 0x18, 0x20, 0x30, 0xF0, 0x20, 0x6A, +0x20, 0xF5, 0x10, 0x9A, 0x00, 0x6C, 0xE4, 0x67, +0xB8, 0x6D, 0xD0, 0x67, 0x00, 0x18, 0x27, 0x33, +0xB8, 0x6D, 0xD0, 0x67, 0x01, 0x6F, 0x00, 0x6C, +0x00, 0x18, 0x27, 0x33, 0x91, 0x67, 0x00, 0x18, +0x87, 0x41, 0x91, 0x67, 0x00, 0x18, 0x9B, 0x41, +0x01, 0x6A, 0x01, 0x10, 0x00, 0x6A, 0x1B, 0x97, +0x1A, 0x91, 0x19, 0x90, 0x0E, 0x63, 0x00, 0xEF, +0x00, 0x6A, 0x77, 0x17, 0xFB, 0x63, 0x09, 0x62, +0x08, 0xD1, 0x07, 0xD0, 0xFF, 0x68, 0x0C, 0xED, +0x24, 0x67, 0x0D, 0xD7, 0x04, 0xD5, 0xCC, 0xE8, +0x00, 0x18, 0x03, 0x41, 0x0F, 0x22, 0x04, 0x95, +0x91, 0x67, 0x00, 0x18, 0xEB, 0x43, 0x0A, 0x22, +0x0D, 0x96, 0x91, 0x67, 0xB0, 0x67, 0x00, 0x18, +0x1A, 0x43, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7, +0x62, 0x32, 0x01, 0x10, 0x00, 0x6A, 0x09, 0x97, +0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, +0xA8, 0x6A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +u32 array_length_mp_8822b_fw_wowlan = 73536; + +#endif + +#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */ + +#endif diff --git a/hal/rtl8822b/hal8822b_fw.h b/hal/rtl8822b/hal8822b_fw.h new file mode 100644 index 0000000..31e4c09 --- /dev/null +++ b/hal/rtl8822b/hal8822b_fw.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * + * Copyright(c) 2015 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifdef CONFIG_RTL8822B + +#ifndef _FW_HEADER_8822B_H +#define _FW_HEADER_8822B_H + +#ifdef LOAD_FW_HEADER_FROM_DRIVER +#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) +extern u8 array_mp_8822b_fw_ap[81504]; +extern u32 array_length_mp_8822b_fw_ap; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +extern u8 array_mp_8822b_fw_nic[127496]; +extern u32 array_length_mp_8822b_fw_nic; +extern u8 array_mp_8822b_fw_wowlan[73536]; +extern u32 array_length_mp_8822b_fw_wowlan; +#endif +#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */ + +#endif + +#endif + diff --git a/include/.osdep_service_linux.h.swp b/include/.osdep_service_linux.h.swp new file mode 100644 index 0000000000000000000000000000000000000000..47dcb930ebdb6e18b89712fb4b0f5b80f243ca7c GIT binary patch literal 16384 zcmeI2TWlj&8ONuvKm!!2QV>ucP7`*OxJjINx4T=i4RRbivDUGz@i-T0tE2JEaeS2V z%rKXvfdyW;2?;7LF9jjdA_1yES`d{$NOYx@03q>0d0}6uc%XteUMkp!!vD-Aj_onK zi1LDtm7naK%Xhx-f6n=4=GdL3?dle}ytt&`^`N5MdG+Sr`=?E1|H4T9>q-6fr2K4RAhq-6r2OIJ{kf6)q*%U51*8H}0jYpg zKq?>=kP1izqyka_sen{KD)2v0KsOcTG1xW40RX=LPoMv9yjxLz2(E);un7M0E=Bn{ z_$lCkfZso$D7U~(;DQEN1PkCH@Y*{S);yL1}oqKI1e5He}0>y{0h7TUI5<#&x0?5KIj4lRImsZz~A4B*ul%-ci=_v z6>tbzKm|+S1K>Vz=Pioz4{#g&4167Y4fx<1Xafzbf^*<+XP`g$Ew}-`51s?x2G;=t z4R8q%a0cAQLChb(E%0670u5XMkAWHRA@B%z1#9Au;6?BgU;?pDI^aKf%`l61$!x7! zZ|~CWvf8RP>a^5YFOw_eYFVw9Yia3hVgBNL;fXnN?i?{$m)p#oEj8+u>IPM{9a=9o zt8;Uhz!~Owjz^};w%)NA5#^-Ax{k*Pi;FhY#x;8y@nGZ(OQ?r=~EUle`A3ab&Q~QWcR$UXy$-bz@C~=;hsNOQWqu>1tV{nz~DJ zdErz1`x|m4`pHe+W&u7NEcRB%>$sg+9GdP(IgI23BdgSRjL7z|7@znA)5%mNpRG zhn*NUpN>Bs*l8wWAgy{sqdIf_?zrS zxHOzLcB*Q*R&HT(ceRnA>e!xYalP6&)%j%M>wZ7aok*=gZaS%rr_0s%naBFEPm{Aw zcG6iENheWR)vnU@ttM^Oidvr@56yyq3-hhSgQ#;aeNNW&y!2@ zWGR}0G%1h78+>?En|D&=uCEux@YxOEY|+`v(>aXp-=wML%rPWR`xM<%SoW%HLx{ zcB$@-I3w1wZknFq*xg}+(JDWpJ>51f<_*`yAslg!S1>vBLfVDl%(udlXETcc>DJYv6xkx9?IcaB(G$a_R)N z4?LC(o_z~9zF7Hi%dbvsCTiRAx-L96(bd!plX^We&i492Z zjeO-5lEWV^G`RCMS)g;vUlawEs#eE^g&<**B54*?ty*f=iYmb^W3$mJFOn8x1pAY0 z)Z1i(+04@|(hNHmH%JW|*7li5N5WRIzDIV7s#>gTdn@FK2R$bY2s>nUWPtZwi!+lP z>7J+C!7*{VWUH)}HqpMgR;^XFJrWzzdfX?j=j?lWpWvg3JnHdI7@#+gjrAN?xTOb# z2N=q-a9dA8pLIiPo}eY!scM^zwwA>03Wt595z;x1oT+#StL1b9c*97=32jpk#O#Sc z@DKB%W=OkzUpRUgPcA8lf9@iO?h7NML3G84elp?;Id(!~=r-}#AUY8XGH5=&BjDX* z6eIzZ9QWAc`@LY+m?MRyrAuT1Z_Ag6%5*DW2c+b9uH&7=pyc1k<&(=P;`#rBcuxNu z5YPYV_w#?n^Zu{Fj{yS}@Lup5p83B4o&|?MoCE9t4ZIE;FM(fxXTX=imw>SSSs-6h z0jYpgKq?>=kP1izqyka_sen{KDv+Gw;uJDDAZ}@DyQI-(5#Q6S<1|4Jk|$+K$?UAF z8wbo3rdMzxRLn$F1*sg48WcsW>d)A+u9 +#include + +typedef enum _WIFIONLY_CHIP_INTERFACE { + WIFIONLY_INTF_UNKNOWN = 0, + WIFIONLY_INTF_PCI = 1, + WIFIONLY_INTF_USB = 2, + WIFIONLY_INTF_SDIO = 3, + WIFIONLY_INTF_MAX +} WIFIONLY_CHIP_INTERFACE, *PWIFIONLY_CHIP_INTERFACE; + +typedef enum _WIFIONLY_CUSTOMER_ID { + CUSTOMER_NORMAL = 0, + CUSTOMER_HP_1 = 1 +} WIFIONLY_CUSTOMER_ID, *PWIFIONLY_CUSTOMER_ID; + +struct wifi_only_haldata { + u16 customer_id; + u8 efuse_pg_antnum; + u8 efuse_pg_antpath; + u8 rfe_type; + u8 ant_div_cfg; +}; + +struct wifi_only_cfg { + PVOID Adapter; + struct wifi_only_haldata haldata_info; + WIFIONLY_CHIP_INTERFACE chip_interface; +}; + +void halwifionly_write1byte(PVOID pwifionlyContext, u32 RegAddr, u8 Data); +void halwifionly_write2byte(PVOID pwifionlyContext, u32 RegAddr, u16 Data); +void halwifionly_write4byte(PVOID pwifionlyContext, u32 RegAddr, u32 Data); +u8 halwifionly_read1byte(PVOID pwifionlyContext, u32 RegAddr); +u16 halwifionly_read2byte(PVOID pwifionlyContext, u32 RegAddr); +u32 halwifionly_read4byte(PVOID pwifionlyContext, u32 RegAddr); +void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMask, u8 data); +void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); +void halwifionly_phy_set_bb_reg(PVOID pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data); +void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter); +void hal_btcoex_wifionly_scan_notify(PADAPTER padapter); +void hal_btcoex_wifionly_hw_config(PADAPTER padapter); +void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter); +#endif diff --git a/include/rtl8821c_dm.h b/include/rtl8821c_dm.h new file mode 100644 index 0000000..7d10941 --- /dev/null +++ b/include/rtl8821c_dm.h @@ -0,0 +1,25 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8812C_DM_H__ +#define __RTL8812C_DM_H__ + +void rtl8821c_phy_init_dm_priv(PADAPTER); +void rtl8821c_phy_deinit_dm_priv(PADAPTER); +void rtl8821c_phy_init_haldm(PADAPTER); +void rtl8821c_phy_haldm_watchdog(PADAPTER); +void rtl8821c_phy_haldm_in_lps(PADAPTER); +void rtl8821c_phy_haldm_watchdog_in_lps(PADAPTER); + +#endif diff --git a/include/rtl8821c_spec.h b/include/rtl8821c_spec.h new file mode 100644 index 0000000..44865bf --- /dev/null +++ b/include/rtl8821c_spec.h @@ -0,0 +1,192 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8821C_SPEC_H__ +#define __RTL8821C_SPEC_H__ + +#define EFUSE_MAP_SIZE HALMAC_EFUSE_SIZE_8821C + +/* + * MAC Register definition + */ +#define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8821C /* hal_com.c & phydm */ +#define REG_AFE_PLL_CTRL REG_AFE_CTRL2_8821C /* hal_com.c & phydm */ +#define REG_MAC_PHY_CTRL REG_AFE_CTRL3_8821C /* phydm only */ +#define REG_LEDCFG0 REG_LED_CFG_8821C /* rtw_mp.c */ +#define MSR (REG_CR_8821C + 2) /* rtw_mp.c */ +#define MSR1 REG_CR_EXT_8821C /* rtw_mp.c & hal_com.c */ +#define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ +#define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ +#define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */ +#define REG_TSFTR1 REG_FREERUN_CNT_8821C /* hal_com.c */ +#define REG_RXFLTMAP2 REG_RXFLTMAP_8821C /* rtw_mp.c */ +#define REG_WOWLAN_WAKE_REASON 0x01C7 +#define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8821C + +/* RXERR_RPT, for rtw_mp.c */ +#define RXERR_TYPE_OFDM_PPDU 0 +#define RXERR_TYPE_OFDM_FALSE_ALARM 2 +#define RXERR_TYPE_OFDM_MPDU_OK 0 +#define RXERR_TYPE_OFDM_MPDU_FAIL 1 +#define RXERR_TYPE_CCK_PPDU 3 +#define RXERR_TYPE_CCK_FALSE_ALARM 5 +#define RXERR_TYPE_CCK_MPDU_OK 3 +#define RXERR_TYPE_CCK_MPDU_FAIL 4 +#define RXERR_TYPE_HT_PPDU 8 +#define RXERR_TYPE_HT_FALSE_ALARM 9 +#define RXERR_TYPE_HT_MPDU_TOTAL 6 +#define RXERR_TYPE_HT_MPDU_OK 6 +#define RXERR_TYPE_HT_MPDU_FAIL 7 +#define RXERR_TYPE_RX_FULL_DROP 10 + +#define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8821C +#define RXERR_RPT_RST BIT_RXERR_RPT_RST_8821C +#define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8821C(type) \ + | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8821C : 0)) + +/* + * BB Register definition + */ +#define rPMAC_Reset 0x100 /* hal_mp.c */ + +#define rFPGA0_RFMOD 0x800 +#define rFPGA0_TxInfo 0x804 +#define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */ +#define rFPGA0_TxGainStage 0x80C /* phydm only */ +#define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */ +#define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */ +#define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */ +#define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */ +#define rTxAGC_B_Rate18_06 0x830 +#define rTxAGC_B_Rate54_24 0x834 +#define rTxAGC_B_CCK1_55_Mcs32 0x838 +#define rCCAonSec_Jaguar 0x838 /* hal_mp.c */ +#define rTxAGC_B_Mcs03_Mcs00 0x83C +#define rTxAGC_B_Mcs07_Mcs04 0x848 +#define rTxAGC_B_Mcs11_Mcs08 0x84C +#define rFPGA0_XA_RFInterfaceOE 0x860 +#define rFPGA0_XB_RFInterfaceOE 0x864 +#define rTxAGC_B_Mcs15_Mcs12 0x868 +#define rTxAGC_B_CCK11_A_CCK2_11 0x86C +#define rFPGA0_XAB_RFInterfaceSW 0x870 +#define rFPGA0_XAB_RFParameter 0x878 +#define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */ +#define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */ +#define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8821c_phy.c) */ + +#define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */ +#define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */ + +#define rFPGA1_TxInfo 0x90C /* hal_mp.c */ +#define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */ + +#define rCCK0_System 0xA00 +#define rCCK0_AFESetting 0xA04 + +#define rCCK0_DSPParameter2 0xA1C +#define rCCK0_TxFilter1 0xA20 +#define rCCK0_TxFilter2 0xA24 +#define rCCK0_DebugPort 0xA28 +#define rCCK0_FalseAlarmReport 0xA2C + +#define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */ +#define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */ + +#define rOFDM0_TRxPathEnable 0xC04 +#define rOFDM0_TRMuxPar 0xC08 +#define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */ +#define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */ +#define rOFDM0_ECCAThreshold 0xC4C /* phydm only */ +#define rOFDM0_XAAGCCore1 0xC50 /* phydm only */ +#define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */ +#define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ +#define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ +#define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ +#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ + +#define rOFDM1_LSTF 0xD00 +#define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ +#define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8821c_phy.c) */ +#define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8821c_phy.c) */ +#define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8821c_phy.c) */ +#define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8821c_phy.c) */ + +#define rTxAGC_A_Rate18_06 0xE00 +#define rTxAGC_A_Rate54_24 0xE04 +#define rTxAGC_A_CCK1_Mcs32 0xE08 +#define rTxAGC_A_Mcs03_Mcs00 0xE10 +#define rTxAGC_A_Mcs07_Mcs04 0xE14 +#define rTxAGC_A_Mcs11_Mcs08 0xE18 +#define rTxAGC_A_Mcs15_Mcs12 0xE1C +#define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ +#define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ +#define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ +#define rB_RFE_Pinmux_Jaguar 0xEB0 /* hal_mp.c */ + +/* Page1(0x100) */ +#define bBBResetB 0x100 + +/* Page8(0x800) */ +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 +/* Reg 0x80C rFPGA0_TxGainStage */ +#define bXBTxAGC 0xF00 +#define bXCTxAGC 0xF000 +#define bXDTxAGC 0xF0000 + +/* PageA(0xA00) */ +#define bCCKBBMode 0x3 + +#define bCCKScramble 0x8 +#define bCCKTxRate 0x3000 + +/* General */ +#define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */ +#define bMaskByte1 0xFF00 /* hal_mp.c & phydm */ +#define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */ +#define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */ +#define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */ +#define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */ +#define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */ + +#define bEnable 0x1 /* hal_mp.c, rtw_mp.c */ +#define bDisable 0x0 /* rtw_mp.c */ + +#define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */ + +#define Rx_Smooth_Factor 20 /* phydm only */ + +/* + * RF Register definition + */ +#define RF_AC 0x00 +#define RF_AC_Jaguar 0x00 /* hal_mp.c */ +#define RF_CHNLBW 0x18 /* rtl8821c_phy.c */ +#define RF_0x52 0x52 + +struct hw_port_reg { + u32 net_type; /*reg_offset*/ + u8 net_type_shift; + u32 macaddr; /*reg_offset*/ + u32 bssid; /*reg_offset*/ + u32 bcn_ctl; /*reg_offset*/ + u32 tsf_rst; /*reg_offset*/ + u8 tsf_rst_bit; + u32 bcn_space; /*reg_offset*/ + u8 bcn_space_shift; + u16 bcn_space_mask; + u32 ps_aid; /*reg_offset*/ +}; + +#endif /* __RTL8192E_SPEC_H__ */ diff --git a/include/rtl8821ce_hal.h b/include/rtl8821ce_hal.h new file mode 100644 index 0000000..426002a --- /dev/null +++ b/include/rtl8821ce_hal.h @@ -0,0 +1,23 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTL8821CE_HAL_H_ +#define _RTL8821CE_HAL_H_ + +#include /* PADAPTER */ + +/* rtl8821ce_ops.c */ +void rtl8821ce_set_hal_ops(PADAPTER); + +#endif /* _RTL8821CE_HAL_H_ */ diff --git a/include/rtw_btcoex_wifionly.h b/include/rtw_btcoex_wifionly.h new file mode 100644 index 0000000..5410481 --- /dev/null +++ b/include/rtw_btcoex_wifionly.h @@ -0,0 +1,22 @@ +/****************************************************************************** + * + * Copyright(c) 2013 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_BTCOEX_WIFIONLY_H__ +#define __RTW_BTCOEX_WIFIONLY_H__ + +void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter); +void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter); +void rtw_btcoex_wifionly_hw_config(PADAPTER padapter); +void rtw_btcoex_wifionly_initialize(PADAPTER padapter); +#endif From 3285e7110f754bc95ac8937f8d552359dbbd890b Mon Sep 17 00:00:00 2001 From: Steve Hillier Date: Sun, 6 May 2018 17:51:08 -0700 Subject: [PATCH 08/48] add device (d-link dwa-182 rev d1) --- README.md | 1 + os_dep/linux/usb_intf.c | 1 + 2 files changed, 2 insertions(+) diff --git a/README.md b/README.md index 5c5baf6..135bd08 100644 --- a/README.md +++ b/README.md @@ -7,6 +7,7 @@ Only STA/Monitor Mode is supported, no AP. A few known wireless cards that use this driver include * [Edimax EW-7822ULC](http://us.edimax.com/edimax/merchandise/merchandise_detail/data/edimax/us/wireless_adapters_ac1200_dual-band/ew-7822ulc/) * [ASUS AC-53 NANO](https://www.asus.com/Networking/USB-AC53-Nano/) +* [D-Link DWA-182 (Revision D1 only)](http://ca.dlink.com/products/connect/wireless-ac1200-dual-band-usb-adapter/) > NOTE: At least v4.7 is needed to compile this module diff --git a/os_dep/linux/usb_intf.c b/os_dep/linux/usb_intf.c index e8166a3..b490d27 100644 --- a/os_dep/linux/usb_intf.c +++ b/os_dep/linux/usb_intf.c @@ -239,6 +239,7 @@ static struct usb_device_id rtw_usb_id_tbl[] = { {USB_DEVICE(0x7392, 0xB822), .driver_info = RTL8822B}, /* Edimax - EW-7822ULC */ {USB_DEVICE(0x0b05, 0x184c), .driver_info = RTL8822B}, /* ASUS USB AC53 */ {USB_DEVICE(0x7392, 0xC822), .driver_info = RTL8822B}, /* Edimax - EW-7822UTC */ + {USB_DEVICE(0x2001, 0x331c), .driver_info = RTL8822B}, /* D-Link - DWA-182 Rev D */ {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB82C, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Default ID */ #endif /* CONFIG_RTL8822B */ From 62cb29ad121bca001bbfb2bca01910d912dfad2b Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Sat, 6 Oct 2018 13:12:07 +0200 Subject: [PATCH 09/48] update from version 1.0.0.9 to version 1.0.1.6 --- Makefile | 333 +- README.md | 47 - RTL8822Bfw_NIC.bin | Bin 113632 -> 0 bytes core/efuse/rtw_efuse.c | 290 +- core/rtw_ap.c | 1742 +- core/rtw_beamforming.c | 95 +- core/rtw_bt_mp.c | 2 +- core/rtw_btcoex.c | 40 +- core/rtw_btcoex_wifionly.c | 5 + core/rtw_cmd.c | 583 +- core/rtw_debug.c | 1192 +- core/rtw_ieee80211.c | 382 +- core/rtw_ioctl_set.c | 418 +- core/rtw_mi.c | 401 +- core/rtw_mlme.c | 1449 +- core/rtw_mlme_ext.c | 3220 +- core/rtw_mp.c | 300 +- core/rtw_odm.c | 56 +- core/rtw_p2p.c | 253 +- core/rtw_pwrctrl.c | 225 +- core/rtw_recv.c | 1952 +- core/rtw_rf.c | 556 +- core/rtw_sdio.c | 5 +- core/rtw_security.c | 439 +- core/rtw_sreset.c | 47 +- core/rtw_sta_mgt.c | 317 +- core/rtw_tdls.c | 786 +- core/rtw_vht.c | 450 +- core/rtw_wapi.c | 62 +- core/rtw_wlan_util.c | 755 +- core/rtw_xmit.c | 1222 +- hal/HalPwrSeqCmd.c | 31 +- hal/btc/HalBtc8188c2Ant.c | 1987 - hal/btc/HalBtc8188c2Ant.h | 149 - hal/btc/HalBtc8192d2Ant.c | 1992 - hal/btc/HalBtc8192d2Ant.h | 170 - hal/btc/HalBtc8192e1Ant.c | 3417 - hal/btc/HalBtc8192e1Ant.h | 226 - hal/btc/HalBtc8192e2Ant.c | 3949 - hal/btc/HalBtc8192e2Ant.h | 190 - hal/btc/HalBtc8703b1Ant.c | 4592 -- hal/btc/HalBtc8703b1Ant.h | 348 - hal/btc/HalBtc8723a1Ant.c | 1544 - hal/btc/HalBtc8723a1Ant.h | 171 - hal/btc/HalBtc8723a2Ant.c | 3746 - hal/btc/HalBtc8723a2Ant.h | 184 - hal/btc/HalBtc8723b1Ant.c | 4845 -- hal/btc/HalBtc8723b1Ant.h | 288 - hal/btc/HalBtc8723b2Ant.c | 4920 -- hal/btc/HalBtc8723b2Ant.h | 214 - hal/btc/HalBtc8812a1Ant.c | 3457 - hal/btc/HalBtc8812a1Ant.h | 230 - hal/btc/HalBtc8812a2Ant.c | 4782 -- hal/btc/HalBtc8812a2Ant.h | 202 - hal/btc/HalBtc8821a1Ant.c | 3100 - hal/btc/HalBtc8821a1Ant.h | 197 - hal/btc/HalBtc8821a2Ant.c | 4560 -- hal/btc/HalBtc8821a2Ant.h | 205 - hal/btc/HalBtc8821aCsr2Ant.c | 3997 - hal/btc/HalBtc8821aCsr2Ant.h | 188 - hal/btc/HalBtc8822b1Ant.c | 6006 -- hal/btc/HalBtc8822b1Ant.h | 408 - hal/btc/HalBtcOutSrc.h | 937 - hal/btc/Mp_Precomp.h | 102 - hal/btc/halbtc8192e1ant.c | 3431 - hal/btc/halbtc8192e1ant.h | 240 - hal/btc/halbtc8192e2ant.c | 4391 -- hal/btc/halbtc8192e2ant.h | 225 - hal/btc/halbtc8703b1ant.c | 4307 - hal/btc/halbtc8703b1ant.h | 418 - hal/btc/halbtc8723b1ant.c | 5127 -- hal/btc/halbtc8723b1ant.h | 307 - hal/btc/halbtc8723b2ant.c | 4972 -- hal/btc/halbtc8723b2ant.h | 231 - hal/btc/halbtc8723bwifionly.c | 82 - hal/btc/halbtc8723bwifionly.h | 22 - hal/btc/halbtc8723d1ant.c | 6276 -- hal/btc/halbtc8723d1ant.h | 427 - hal/btc/halbtc8723d2ant.c | 6820 -- hal/btc/halbtc8723d2ant.h | 432 - hal/btc/halbtc8812a1ant.c | 3475 - hal/btc/halbtc8812a1ant.h | 244 - hal/btc/halbtc8812a2ant.c | 5638 -- hal/btc/halbtc8812a2ant.h | 241 - hal/btc/halbtc8821a1ant.c | 3303 - hal/btc/halbtc8821a1ant.h | 228 - hal/btc/halbtc8821a2ant.c | 4651 -- hal/btc/halbtc8821a2ant.h | 225 - hal/btc/halbtc8821c1ant.c | 5357 -- hal/btc/halbtc8821c1ant.h | 497 - hal/btc/halbtc8821c2ant.c | 5965 -- hal/btc/halbtc8821c2ant.h | 504 - hal/btc/halbtc8821cwifionly.c | 200 - hal/btc/halbtc8821cwifionly.h | 84 - hal/btc/halbtc8822b1ant.c | 4188 +- hal/btc/halbtc8822b1ant.h | 73 +- hal/btc/halbtc8822b2ant.c | 2857 +- hal/btc/halbtc8822b2ant.h | 66 +- hal/btc/halbtcoutsrc.h | 135 +- hal/btc/mp_precomp.h | 46 +- hal/hal_btcoex.c | 1399 +- hal/hal_btcoex_wifionly.c | 44 +- hal/hal_com.c | 2530 +- hal/hal_com_c2h.h | 9 + hal/hal_com_phycfg.c | 312 +- hal/hal_dm.c | 922 +- hal/hal_dm.h | 67 + hal/hal_halmac.c | 3383 +- hal/hal_halmac.h | 144 +- hal/hal_hci/hal_usb.c | 2 +- hal/hal_intf.c | 457 +- hal/hal_mcc.c | 1882 +- hal/hal_mp.c | 565 +- hal/hal_phy.c | 36 +- hal/halmac/halmac_2_platform.h | 23 +- .../halmac_8197f/halmac_8197f_cfg.h | 112 - .../halmac_8197f/halmac_8197f_pwr_seq.h | 161 - .../halmac_8197f/halmac_api_8197f.h | 11 - .../halmac_8197f/halmac_api_8197f_pcie.h | 8 - .../halmac_8197f/halmac_api_8197f_sdio.h | 8 - .../halmac_8197f/halmac_api_8197f_usb.h | 8 - .../halmac_8197f/halmac_func_8197f.h | 6 - .../halmac_8821c/halmac_8821c_cfg.h | 119 - .../halmac_8821c/halmac_8821c_pwr_seq.h | 223 - .../halmac_8821c/halmac_api_8821c.h | 23 - .../halmac_8821c/halmac_api_8821c_pcie.h | 13 - .../halmac_8821c/halmac_api_8821c_sdio.h | 20 - .../halmac_8821c/halmac_api_8821c_usb.h | 12 - .../halmac_8821c/halmac_func_8821c.h | 19 - .../halmac_8822b/halmac_8822b_cfg.h | 139 +- .../halmac_8822b/halmac_8822b_phy.c | 73 - .../halmac_8822b/halmac_8822b_pwr_seq.c | 264 - .../halmac_8822b/halmac_8822b_pwr_seq.h | 31 - .../halmac_8822b/halmac_api_8822b.c | 287 - .../halmac_8822b/halmac_api_8822b.h | 44 - .../halmac_8822b/halmac_api_8822b_pcie.c | 265 - .../halmac_8822b/halmac_api_8822b_pcie.h | 54 - .../halmac_8822b/halmac_api_8822b_sdio.c | 156 - .../halmac_8822b/halmac_api_8822b_sdio.h | 48 - .../halmac_8822b/halmac_api_8822b_usb.c | 162 - .../halmac_8822b/halmac_api_8822b_usb.h | 42 - .../halmac_8822b/halmac_func_8822b.c | 333 - .../halmac_8822b/halmac_func_8822b.h | 33 - .../halmac_8822b/halmac_gpio_8822b.c | 830 +- .../halmac_8822b/halmac_gpio_8822b.h | 150 +- hal/halmac/halmac_88xx/halmac_88xx_cfg.h | 179 +- hal/halmac/halmac_88xx/halmac_api_88xx.c | 5802 -- hal/halmac/halmac_88xx/halmac_api_88xx.h | 638 - hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c | 310 - hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h | 84 - hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c | 980 - hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h | 133 - hal/halmac/halmac_88xx/halmac_api_88xx_usb.c | 566 - hal/halmac/halmac_88xx/halmac_api_88xx_usb.h | 98 - hal/halmac/halmac_88xx/halmac_func_88xx.c | 4100 - hal/halmac/halmac_88xx/halmac_func_88xx.h | 523 - hal/halmac/halmac_88xx/halmac_gpio_88xx.c | 320 +- hal/halmac/halmac_88xx/halmac_gpio_88xx.h | 85 +- hal/halmac/halmac_api.c | 668 +- hal/halmac/halmac_api.h | 119 +- hal/halmac/halmac_bit2.h | 60967 ++++++++++---- hal/halmac/halmac_bit_8197f.h | 14201 ++-- hal/halmac/halmac_bit_8814b.h | 27911 +++++-- hal/halmac/halmac_bit_8821c.h | 16836 ++-- hal/halmac/halmac_bit_8822b.h | 14704 +++- hal/halmac/halmac_fw_info.h | 111 +- hal/halmac/halmac_fw_offload_c2h_ap.h | 630 +- hal/halmac/halmac_fw_offload_c2h_nic.h | 461 +- hal/halmac/halmac_fw_offload_h2c_ap.h | 1390 +- hal/halmac/halmac_fw_offload_h2c_nic.h | 974 +- hal/halmac/halmac_gpio_cmd.h | 68 +- hal/halmac/halmac_h2c_extra_info_ap.h | 270 +- hal/halmac/halmac_h2c_extra_info_nic.h | 199 +- hal/halmac/halmac_hw_cfg.h | 33 +- hal/halmac/halmac_intf_phy_cmd.h | 18 +- hal/halmac/halmac_original_c2h_ap.h | 929 +- hal/halmac/halmac_original_c2h_nic.h | 618 +- hal/halmac/halmac_original_h2c_ap.h | 2452 +- hal/halmac/halmac_original_h2c_nic.h | 1663 +- hal/halmac/halmac_pcie_reg.h | 18 +- hal/halmac/halmac_pwr_seq_cmd.h | 118 +- hal/halmac/halmac_reg2.h | 7029 +- hal/halmac/halmac_reg_8197f.h | 7 +- hal/halmac/halmac_reg_8814b.h | 787 +- hal/halmac/halmac_reg_8821c.h | 102 +- hal/halmac/halmac_reg_8822b.h | 28 +- hal/halmac/halmac_rx_bd_ap.h | 40 - hal/halmac/halmac_rx_bd_chip.h | 124 - hal/halmac/halmac_rx_bd_nic.h | 22 +- hal/halmac/halmac_rx_desc_ap.h | 601 +- hal/halmac/halmac_rx_desc_chip.h | 745 +- hal/halmac/halmac_rx_desc_nic.h | 449 +- hal/halmac/halmac_sdio_reg.h | 16 +- hal/halmac/halmac_tx_bd_ap.h | 110 - hal/halmac/halmac_tx_bd_chip.h | 389 - hal/halmac/halmac_tx_bd_nic.h | 91 +- hal/halmac/halmac_tx_desc_ap.h | 2049 +- hal/halmac/halmac_tx_desc_chip.h | 3279 +- hal/halmac/halmac_tx_desc_nic.h | 1033 +- hal/halmac/halmac_type.h | 2630 +- hal/halmac/halmac_usb_reg.h | 6 +- hal/led/hal_usb_led.c | 62 +- hal/phydm/ap_makefile.mk | 15 +- hal/phydm/halphyrf_ap.c | 2790 - hal/phydm/halphyrf_ap.h | 179 - hal/phydm/halphyrf_ce.c | 801 - hal/phydm/halphyrf_ce.h | 118 - hal/phydm/halphyrf_win.c | 780 - hal/phydm/halphyrf_win.h | 120 - hal/phydm/halrf/halphyrf_ap.c | 860 +- hal/phydm/halrf/halphyrf_ap.h | 33 +- hal/phydm/halrf/halphyrf_ce.c | 865 +- hal/phydm/halrf/halphyrf_ce.h | 39 +- hal/phydm/halrf/halphyrf_win.c | 778 +- hal/phydm/halrf/halphyrf_win.h | 63 +- hal/phydm/halrf/halrf.c | 1436 +- hal/phydm/halrf/halrf.h | 390 +- hal/phydm/halrf/halrf_features.h | 17 +- hal/phydm/halrf/halrf_iqk.h | 58 +- hal/phydm/halrf/halrf_kfree.c | 819 +- hal/phydm/halrf/halrf_kfree.h | 49 +- hal/phydm/halrf/halrf_powertracking_ap.c | 204 +- hal/phydm/halrf/halrf_powertracking_ap.h | 46 +- hal/phydm/halrf/halrf_powertracking_ce.c | 243 +- hal/phydm/halrf/halrf_powertracking_ce.h | 53 +- hal/phydm/halrf/halrf_powertracking_win.c | 243 +- hal/phydm/halrf/halrf_powertracking_win.h | 37 +- hal/phydm/halrf/rtl8822b/halrf_8822b.c | 513 +- hal/phydm/halrf/rtl8822b/halrf_8822b.h | 41 +- hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c | 1748 +- hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h | 38 +- hal/phydm/mp_precomp.h | 14 +- hal/phydm/phydm.c | 3737 +- hal/phydm/phydm.h | 1144 +- hal/phydm/phydm.mk | 13 +- hal/phydm/phydm_acs.c | 469 +- hal/phydm/phydm_acs.h | 33 +- hal/phydm/phydm_adaptivity.c | 961 +- hal/phydm/phydm_adaptivity.h | 113 +- hal/phydm/phydm_adc_sampling.c | 417 +- hal/phydm/phydm_adc_sampling.h | 45 +- hal/phydm/phydm_antdect.c | 689 +- hal/phydm/phydm_antdect.h | 26 +- hal/phydm/phydm_antdiv.c | 6120 +- hal/phydm/phydm_antdiv.h | 277 +- hal/phydm/phydm_beamforming.c | 1742 +- hal/phydm/phydm_beamforming.h | 124 +- hal/phydm/phydm_ccx.c | 2177 +- hal/phydm/phydm_ccx.h | 373 +- hal/phydm/phydm_cfotracking.c | 367 +- hal/phydm/phydm_cfotracking.h | 51 +- hal/phydm/phydm_debug.c | 3645 +- hal/phydm/phydm_debug.h | 464 +- hal/phydm/phydm_dfs.c | 682 +- hal/phydm/phydm_dfs.h | 80 +- hal/phydm/phydm_dig.c | 3207 +- hal/phydm/phydm_dig.h | 493 +- hal/phydm/phydm_dynamic_rx_path.c | 194 +- hal/phydm/phydm_dynamic_rx_path.h | 46 +- hal/phydm/phydm_dynamicbbpowersaving.c | 106 - hal/phydm/phydm_dynamicbbpowersaving.h | 52 - hal/phydm/phydm_dynamictxpower.c | 676 +- hal/phydm/phydm_dynamictxpower.h | 59 +- hal/phydm/phydm_edcaturbocheck.c | 763 - hal/phydm/phydm_edcaturbocheck.h | 100 - hal/phydm/phydm_features.h | 245 +- hal/phydm/phydm_hwconfig.c | 3490 +- hal/phydm/phydm_hwconfig.h | 529 +- hal/phydm/phydm_interface.c | 760 +- hal/phydm/phydm_interface.h | 333 +- hal/phydm/phydm_iqk.h | 50 - hal/phydm/phydm_kfree.c | 191 - hal/phydm/phydm_kfree.h | 45 - hal/phydm/phydm_noisemonitor.c | 374 +- hal/phydm/phydm_noisemonitor.h | 47 +- hal/phydm/phydm_pathdiv.c | 677 +- hal/phydm/phydm_pathdiv.h | 110 +- hal/phydm/phydm_powertracking_ap.c | 1216 - hal/phydm/phydm_powertracking_ap.h | 351 - hal/phydm/phydm_powertracking_ce.c | 756 - hal/phydm/phydm_powertracking_ce.h | 334 - hal/phydm/phydm_powertracking_win.c | 788 - hal/phydm/phydm_powertracking_win.h | 299 - hal/phydm/phydm_pre_define.h | 597 +- hal/phydm/phydm_precomp.h | 90 +- hal/phydm/phydm_psd.c | 803 +- hal/phydm/phydm_psd.h | 166 +- hal/phydm/phydm_rainfo.c | 4518 +- hal/phydm/phydm_rainfo.h | 373 +- hal/phydm/phydm_reg.h | 31 +- hal/phydm/phydm_regdefine11ac.h | 23 +- hal/phydm/phydm_regdefine11n.h | 21 +- hal/phydm/phydm_types.h | 63 +- hal/phydm/rtchnlplan.c | 481 - hal/phydm/rtchnlplan.h | 699 - hal/phydm/rtl8822b/halhwimg8822b_bb.c | 5780 +- hal/phydm/rtl8822b/halhwimg8822b_bb.h | 126 +- hal/phydm/rtl8822b/halhwimg8822b_fw.c | 13433 ---- hal/phydm/rtl8822b/halhwimg8822b_fw.h | 61 - hal/phydm/rtl8822b/halhwimg8822b_mac.c | 109 +- hal/phydm/rtl8822b/halhwimg8822b_mac.h | 40 +- hal/phydm/rtl8822b/halhwimg8822b_rf.c | 7965 +- hal/phydm/rtl8822b/halhwimg8822b_rf.h | 178 +- hal/phydm/rtl8822b/halphyrf_8822b.c | 481 - hal/phydm/rtl8822b/halphyrf_8822b.h | 76 - hal/phydm/rtl8822b/mp_precomp.h | 9 +- hal/phydm/rtl8822b/phydm_hal_api8822b.c | 1975 +- hal/phydm/rtl8822b/phydm_hal_api8822b.h | 96 +- hal/phydm/rtl8822b/phydm_iqk_8822b.c | 1244 - hal/phydm/rtl8822b/phydm_iqk_8822b.h | 74 - hal/phydm/rtl8822b/phydm_regconfig8822b.c | 127 +- hal/phydm/rtl8822b/phydm_regconfig8822b.h | 37 +- hal/phydm/rtl8822b/phydm_rtl8822b.c | 529 +- hal/phydm/rtl8822b/phydm_rtl8822b.h | 41 +- hal/phydm/rtl8822b/phydm_rtl8822b_ram.c | 7 - hal/phydm/rtl8822b/phydm_rtl8822b_ram.h | 34 - hal/phydm/rtl8822b/version_rtl8822b.h | 28 +- hal/phydm/txbf/halcomtxbf.c | 332 +- hal/phydm/txbf/halcomtxbf.h | 66 +- hal/phydm/txbf/haltxbf8192e.c | 254 +- hal/phydm/txbf/haltxbf8192e.h | 44 +- hal/phydm/txbf/haltxbf8814a.c | 405 +- hal/phydm/txbf/haltxbf8814a.h | 68 +- hal/phydm/txbf/haltxbf8822b.c | 652 +- hal/phydm/txbf/haltxbf8822b.h | 52 +- hal/phydm/txbf/haltxbfinterface.c | 692 +- hal/phydm/txbf/haltxbfinterface.h | 104 +- hal/phydm/txbf/haltxbfjaguar.c | 326 +- hal/phydm/txbf/haltxbfjaguar.h | 56 +- hal/phydm/txbf/phydm_hal_txbf_api.c | 53 +- hal/phydm/txbf/phydm_hal_txbf_api.h | 31 +- hal/rtl8822b/hal8822b_fw.c | 65863 +++++++++------- hal/rtl8822b/hal8822b_fw.h | 34 +- hal/rtl8822b/rtl8822b.h | 30 +- hal/rtl8822b/rtl8822b_cmd.c | 819 +- hal/rtl8822b/rtl8822b_halinit.c | 17 +- hal/rtl8822b/rtl8822b_mac.c | 121 +- hal/rtl8822b/rtl8822b_ops.c | 1182 +- hal/rtl8822b/rtl8822b_phy.c | 470 +- hal/rtl8822b/usb/rtl8822bu.h | 4 +- hal/rtl8822b/usb/rtl8822bu_halinit.c | 37 +- hal/rtl8822b/usb/rtl8822bu_halmac.c | 64 +- hal/rtl8822b/usb/rtl8822bu_led.c | 64 +- hal/rtl8822b/usb/rtl8822bu_ops.c | 50 +- hal/rtl8822b/usb/rtl8822bu_recv.c | 18 +- hal/rtl8822b/usb/rtl8822bu_xmit.c | 60 +- include/.osdep_service_linux.h.swp | Bin 16384 -> 0 bytes include/Hal8188EPhyCfg.h | 16 +- include/Hal8188FPhyCfg.h | 16 +- include/Hal8192EPhyCfg.h | 14 +- include/Hal8192EPhyReg.h | 2 +- include/Hal8192EPwrSeq.h | 2 +- include/Hal8703BPhyCfg.h | 20 +- include/Hal8723BPhyCfg.h | 16 +- include/Hal8723DPhyCfg.h | 18 +- include/Hal8723DPwrSeq.h | 1 - include/Hal8812PhyCfg.h | 20 +- include/Hal8812PhyReg.h | 2 + include/Hal8812PwrSeq.h | 8 +- include/Hal8814PhyCfg.h | 28 +- include/Hal8814PhyReg.h | 2 + include/HalVerDef.h | 4 - include/autoconf.h | 62 +- include/basic_types.h | 41 +- include/drv_conf.h | 97 +- include/drv_types.h | 209 +- include/drv_types_pci.h | 9 +- include/hal_btcoex.h | 3 + include/hal_btcoex_wifionly.h | 20 +- include/hal_com.h | 103 +- include/hal_com_h2c.h | 102 +- include/hal_com_led.h | 112 +- include/hal_com_phycfg.h | 36 +- include/hal_com_reg.h | 31 +- include/hal_data.h | 103 +- include/hal_ic_cfg.h | 52 +- include/hal_intf.h | 100 +- include/hal_pg.h | 28 +- include/hal_phy.h | 37 +- include/ieee80211.h | 239 +- include/mlme_osdep.h | 5 - include/osdep_service.h | 124 +- include/osdep_service_bsd.h | 1409 +- include/osdep_service_ce.h | 310 +- include/osdep_service_linux.h | 164 +- include/osdep_service_xp.h | 330 +- include/pci_osintf.h | 3 + include/recv_osdep.h | 10 +- include/rtl8188e_cmd.h | 8 - include/rtl8188e_hal.h | 17 +- include/rtl8188e_led.h | 2 + include/rtl8188e_recv.h | 6 +- include/rtl8188e_rf.h | 2 +- include/rtl8188e_spec.h | 2 + include/rtl8188f_cmd.h | 6 - include/rtl8188f_dm.h | 3 - include/rtl8188f_hal.h | 2 +- include/rtl8188f_led.h | 2 + include/rtl8188f_rf.h | 2 +- include/rtl8188f_xmit.h | 3 +- include/rtl8192e_cmd.h | 9 +- include/rtl8192e_dm.h | 2 +- include/rtl8192e_hal.h | 7 +- include/rtl8192e_led.h | 5 +- include/rtl8192e_recv.h | 13 +- include/rtl8192e_rf.h | 4 +- include/rtl8192e_spec.h | 2 +- include/rtl8192e_sreset.h | 2 +- include/rtl8192e_xmit.h | 4 +- include/rtl8703b_cmd.h | 6 - include/rtl8703b_dm.h | 3 - include/rtl8703b_hal.h | 2 +- include/rtl8703b_led.h | 5 +- include/rtl8703b_rf.h | 2 +- include/rtl8703b_xmit.h | 1 + include/rtl8723b_cmd.h | 6 - include/rtl8723b_dm.h | 4 - include/rtl8723b_hal.h | 4 +- include/rtl8723b_led.h | 3 +- include/rtl8723b_rf.h | 2 +- include/rtl8723b_xmit.h | 1 + include/rtl8723d_cmd.h | 28 +- include/rtl8723d_dm.h | 3 - include/rtl8723d_hal.h | 8 +- include/rtl8723d_led.h | 3 +- include/rtl8723d_recv.h | 1 + include/rtl8723d_rf.h | 2 +- include/rtl8723d_spec.h | 6 + include/rtl8723d_xmit.h | 8 +- include/rtl8812a_cmd.h | 9 +- include/rtl8812a_hal.h | 14 +- include/rtl8812a_led.h | 11 +- include/rtl8812a_rf.h | 2 +- include/rtl8812a_spec.h | 11 +- include/rtl8812a_xmit.h | 1 + include/rtl8814a_cmd.h | 3 +- include/rtl8814a_dm.h | 2 +- include/rtl8814a_hal.h | 23 +- include/rtl8814a_led.h | 5 +- include/rtl8814a_recv.h | 2 +- include/rtl8814a_rf.h | 4 +- include/rtl8814a_spec.h | 11 +- include/rtl8814a_sreset.h | 2 +- include/rtl8814a_xmit.h | 6 +- include/rtl8821a_spec.h | 4 +- include/rtl8821c_dm.h | 2 - include/rtl8821c_hal.h | 18 +- include/rtl8821c_spec.h | 17 +- include/rtl8822b_hal.h | 24 +- include/rtl8822be_hal.h | 2 + include/rtw_android.h | 1 + include/rtw_ap.h | 37 +- include/rtw_beamforming.h | 12 +- include/rtw_btcoex.h | 9 + include/rtw_btcoex_wifionly.h | 1 + include/rtw_cmd.h | 68 +- include/rtw_debug.h | 180 +- include/rtw_ht.h | 23 +- include/rtw_ioctl_set.h | 5 +- include/rtw_mcc.h | 65 +- include/rtw_mi.h | 87 +- include/rtw_mlme.h | 338 +- include/rtw_mlme_ext.h | 237 +- include/rtw_mp.h | 59 +- include/rtw_odm.h | 14 +- include/rtw_p2p.h | 1 + include/rtw_pwrctrl.h | 38 +- include/rtw_qos.h | 39 +- include/rtw_recv.h | 179 +- include/rtw_rf.h | 82 +- include/rtw_security.h | 54 +- include/rtw_sreset.h | 15 +- include/rtw_tdls.h | 63 +- include/rtw_version.h | 4 +- include/rtw_vht.h | 43 +- include/rtw_wapi.h | 4 +- include/rtw_xmit.h | 65 +- include/sdio_ops.h | 40 + include/sdio_ops_linux.h | 2 +- include/sta_info.h | 235 +- include/usb_ops.h | 2 +- include/wifi.h | 77 +- include/wlan_bssdef.h | 22 +- os_dep/linux/ioctl_cfg80211.c | 4057 +- os_dep/linux/ioctl_cfg80211.h | 64 +- os_dep/linux/ioctl_linux.c | 1181 +- os_dep/linux/ioctl_mp.c | 197 +- os_dep/linux/mlme_linux.c | 26 +- os_dep/linux/os_intfs.c | 595 +- os_dep/linux/recv_linux.c | 365 +- os_dep/linux/rtw_android.c | 51 +- os_dep/linux/rtw_cfgvendor.c | 346 +- os_dep/linux/rtw_cfgvendor.h | 429 +- os_dep/linux/rtw_proc.c | 1103 +- os_dep/linux/usb_intf.c | 43 +- os_dep/linux/usb_ops_linux.c | 41 +- os_dep/linux/wifi_regd.c | 38 +- os_dep/linux/xmit_linux.c | 16 +- os_dep/osdep_service.c | 537 +- rtl8822b.mk | 58 +- 500 files changed, 231675 insertions(+), 298415 deletions(-) delete mode 100644 README.md delete mode 100644 RTL8822Bfw_NIC.bin delete mode 100644 hal/btc/HalBtc8188c2Ant.c delete mode 100644 hal/btc/HalBtc8188c2Ant.h delete mode 100644 hal/btc/HalBtc8192d2Ant.c delete mode 100644 hal/btc/HalBtc8192d2Ant.h delete mode 100644 hal/btc/HalBtc8192e1Ant.c delete mode 100644 hal/btc/HalBtc8192e1Ant.h delete mode 100644 hal/btc/HalBtc8192e2Ant.c delete mode 100644 hal/btc/HalBtc8192e2Ant.h delete mode 100644 hal/btc/HalBtc8703b1Ant.c delete mode 100644 hal/btc/HalBtc8703b1Ant.h delete mode 100644 hal/btc/HalBtc8723a1Ant.c delete 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########################### CONFIG_MP_INCLUDED = y -CONFIG_POWER_SAVING = y +CONFIG_POWER_SAVING = n CONFIG_USB_AUTOSUSPEND = n CONFIG_HW_PWRP_DETECTION = n CONFIG_WIFI_TEST = n @@ -55,10 +55,11 @@ CONFIG_INTEL_WIDI = n CONFIG_WAPI_SUPPORT = n CONFIG_EFUSE_CONFIG_FILE = y CONFIG_EXT_CLK = n -CONFIG_TRAFFIC_PROTECT = y +CONFIG_TRAFFIC_PROTECT = n CONFIG_LOAD_PHY_PARA_FROM_FILE = y CONFIG_TXPWR_BY_RATE_EN = y CONFIG_TXPWR_LIMIT_EN = n +CONFIG_RTW_CHPLAN = 0xFF CONFIG_RTW_ADAPTIVITY_EN = disable CONFIG_RTW_ADAPTIVITY_MODE = normal CONFIG_SIGNAL_SCALE_MAPPING = n @@ -71,6 +72,10 @@ CONFIG_MCC_MODE = n CONFIG_APPEND_VENDOR_IE_ENABLE = n CONFIG_RTW_NAPI = y CONFIG_RTW_GRO = y +CONFIG_RTW_NETIF_SG = n +CONFIG_RTW_IPCAM_APPLICATION = n +CONFIG_RTW_REPEATER_SON = n +CONFIG_RTW_WIFI_HAL = y ########################## Debug ########################### CONFIG_RTW_DEBUG = n # default log level is _DRV_INFO_ = 4, @@ -78,8 +83,8 @@ CONFIG_RTW_DEBUG = n CONFIG_RTW_LOG_LEVEL = 4 ######################## Wake On Lan ########################## CONFIG_WOWLAN = n +CONFIG_WAKEUP_TYPE = 0x7 #bit2: deauth, bit1: unicast, bit0: magic pkt. CONFIG_GPIO_WAKEUP = n -CONFIG_DEFAULT_PATTERNS_EN = n CONFIG_WAKEUP_GPIO_IDX = default CONFIG_HIGH_ACTIVE = n CONFIG_PNO_SUPPORT = n @@ -142,8 +147,12 @@ CONFIG_PLATFORM_RTK119X = n CONFIG_PLATFORM_RTK129X = n CONFIG_PLATFORM_NOVATEK_NT72668 = n CONFIG_PLATFORM_HISILICON = n +CONFIG_PLATFORM_HISILICON_HI3798 = n CONFIG_PLATFORM_NV_TK1 = n +CONFIG_PLATFORM_NV_TK1_UBUNTU = n CONFIG_PLATFORM_RTL8197D = n +CONFIG_PLATFORM_AML_S905 = n +CONFIG_PLATFORM_ZTE_ZX296716 = n ############################################################### CONFIG_DRVEXT_MODULE = n @@ -180,7 +189,8 @@ _OS_INTFS_FILES := os_dep/osdep_service.o \ os_dep/linux/rtw_cfgvendor.o \ os_dep/linux/wifi_regd.o \ os_dep/linux/rtw_android.o \ - os_dep/linux/rtw_proc.o + os_dep/linux/rtw_proc.o \ + os_dep/linux/rtw_rhashtable.o ifeq ($(CONFIG_MP_INCLUDED), y) _OS_INTFS_FILES += os_dep/linux/ioctl_mp.o @@ -202,11 +212,13 @@ _HAL_INTFS_FILES := hal/hal_intf.o \ hal/hal_com_phycfg.o \ hal/hal_phy.o \ hal/hal_dm.o \ + hal/hal_dm_acs.o \ hal/hal_btcoex_wifionly.o \ hal/hal_btcoex.o \ hal/hal_mp.o \ hal/hal_mcc.o \ hal/hal_hci/hal_$(HCI_NAME).o \ + hal/led/hal_led.o \ hal/led/hal_$(HCI_NAME)_led.o @@ -214,28 +226,7 @@ EXTRA_CFLAGS += -I$(src)/platform _PLATFORM_FILES := platform/platform_ops.o EXTRA_CFLAGS += -I$(src)/hal/btc -_BTC_FILES += hal/btc/halbtc8723bwifionly.o \ - hal/btc/halbtc8822bwifionly.o \ - hal/btc/halbtc8821cwifionly.o -ifeq ($(CONFIG_BT_COEXIST), y) -_BTC_FILES += hal/btc/halbtc8192e1ant.o \ - hal/btc/halbtc8192e2ant.o \ - hal/btc/halbtc8723b1ant.o \ - hal/btc/halbtc8723b2ant.o \ - hal/btc/halbtc8812a1ant.o \ - hal/btc/halbtc8812a2ant.o \ - hal/btc/halbtc8821a1ant.o \ - hal/btc/halbtc8821a2ant.o \ - hal/btc/halbtc8703b1ant.o \ - hal/btc/halbtc8723d1ant.o \ - hal/btc/halbtc8723d2ant.o \ - hal/btc/halbtc8822b1ant.o \ - hal/btc/halbtc8822b2ant.o \ - hal/btc/halbtc8821c1ant.o \ - hal/btc/halbtc8821c2ant.o -endif - -include $(TopDIR)/hal/phydm/phydm.mk + ########### HAL_RTL8188E ################################# ifeq ($(CONFIG_RTL8188E), y) @@ -350,6 +341,11 @@ ifeq ($(CONFIG_SDIO_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_SDIO.o endif +ifeq ($(CONFIG_BT_COEXIST), y) +_BTC_FILES += hal/btc/halbtc8192e1ant.o \ + hal/btc/halbtc8192e2ant.o +endif + endif ########### HAL_RTL8812A_RTL8821A ################################# @@ -446,6 +442,17 @@ _HAL_INTFS_FILES += hal/rtl8812a/hal8821a_fw.o endif +ifeq ($(CONFIG_BT_COEXIST), y) +ifeq ($(CONFIG_RTL8812A), y) +_BTC_FILES += hal/btc/halbtc8812a1ant.o \ + hal/btc/halbtc8812a2ant.o +endif +ifeq ($(CONFIG_RTL8821A), y) +_BTC_FILES += hal/btc/halbtc8821a1ant.o \ + hal/btc/halbtc8821a2ant.o +endif +endif + endif ########### HAL_RTL8723B ################################# @@ -498,6 +505,12 @@ ifeq ($(CONFIG_SDIO_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_SDIO.o endif +_BTC_FILES += hal/btc/halbtc8723bwifionly.o +ifeq ($(CONFIG_BT_COEXIST), y) +_BTC_FILES += hal/btc/halbtc8723b1ant.o \ + hal/btc/halbtc8723b2ant.o +endif + endif ########### HAL_RTL8814A ################################# @@ -608,6 +621,10 @@ ifeq ($(CONFIG_PCI_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_PCIE.o endif +ifeq ($(CONFIG_BT_COEXIST), y) +_BTC_FILES += hal/btc/halbtc8703b1ant.o +endif + endif ########### HAL_RTL8723D ################################# @@ -662,6 +679,11 @@ ifeq ($(CONFIG_PCI_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_PCIE.o endif +ifeq ($(CONFIG_BT_COEXIST), y) +_BTC_FILES += hal/btc/halbtc8723d1ant.o \ + hal/btc/halbtc8723d2ant.o +endif + endif ########### HAL_RTL8188F ################################# @@ -716,14 +738,36 @@ endif ########### HAL_RTL8822B ################################# ifeq ($(CONFIG_RTL8822B), y) -include $(TopDIR)/rtl8822b.mk +RTL871X := rtl8822b +ifeq ($(CONFIG_USB_HCI), y) +ifeq ($(CONFIG_BT_COEXIST), n) +MODULE_NAME = 8812bu +else +MODULE_NAME = 88x2bu +endif +endif +ifeq ($(CONFIG_PCI_HCI), y) +MODULE_NAME = 88x2be +endif +ifeq ($(CONFIG_SDIO_HCI), y) +MODULE_NAME = 88x2bs endif +endif ########### HAL_RTL8821C ################################# ifeq ($(CONFIG_RTL8821C), y) -include $(TopDIR)/rtl8821c.mk +RTL871X := rtl8821c +ifeq ($(CONFIG_USB_HCI), y) +MODULE_NAME = 8821cu +endif +ifeq ($(CONFIG_PCI_HCI), y) +MODULE_NAME = 8821ce +endif +ifeq ($(CONFIG_SDIO_HCI), y) +MODULE_NAME = 8821cs endif +endif ########### AUTO_CFG ################################# ifeq ($(CONFIG_AUTOCFG_CP), y) @@ -818,8 +862,7 @@ endif ifeq ($(CONFIG_LOAD_PHY_PARA_FROM_FILE), y) EXTRA_CFLAGS += -DCONFIG_LOAD_PHY_PARA_FROM_FILE #EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER -#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/lib/firmware/\" -EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"\" +EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/lib/firmware/\" endif ifeq ($(CONFIG_TXPWR_BY_RATE_EN), n) @@ -838,6 +881,10 @@ else ifeq ($(CONFIG_TXPWR_LIMIT_EN), auto) EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=2 endif +ifneq ($(CONFIG_RTW_CHPLAN), 0xFF) +EXTRA_CFLAGS += -DCONFIG_RTW_CHPLAN=$(CONFIG_RTW_CHPLAN) +endif + ifeq ($(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY), y) EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_BY_REGULATORY endif @@ -867,13 +914,10 @@ EXTRA_CFLAGS += -DCONFIG_IEEE80211W endif ifeq ($(CONFIG_WOWLAN), y) -EXTRA_CFLAGS += -DCONFIG_WOWLAN +EXTRA_CFLAGS += -DCONFIG_WOWLAN -DRTW_WAKEUP_EVENT=$(CONFIG_WAKEUP_TYPE) ifeq ($(CONFIG_SDIO_HCI), y) EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER endif -ifeq ($(CONFIG_DEFAULT_PATTERNS_EN), y) -EXTRA_CFLAGS += -DCONFIG_DEFAULT_PATTERNS_EN -endif endif ifeq ($(CONFIG_AP_WOWLAN), y) @@ -940,6 +984,27 @@ ifeq ($(CONFIG_RTW_GRO), y) EXTRA_CFLAGS += -DCONFIG_RTW_GRO endif +ifeq ($(CONFIG_RTW_REPEATER_SON), y) +EXTRA_CFLAGS += -DCONFIG_RTW_REPEATER_SON +endif + +ifeq ($(CONFIG_RTW_IPCAM_APPLICATION), y) +EXTRA_CFLAGS += -DCONFIG_RTW_IPCAM_APPLICATION +ifeq ($(CONFIG_WIFI_MONITOR), n) +EXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR +endif +endif + +ifeq ($(CONFIG_RTW_NETIF_SG), y) +EXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG +endif + +ifeq ($(CONFIG_RTW_WIFI_HAL), y) +#EXTRA_CFLAGS += -DCONFIG_RTW_WIFI_HAL_DEBUG +EXTRA_CFLAGS += -DCONFIG_RTW_WIFI_HAL +EXTRA_CFLAGS += -DCONFIG_RTW_CFGVEDNOR_LLSTATS +endif + ifeq ($(CONFIG_MP_VHT_HW_TX_MODE), y) EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE ifeq ($(CONFIG_PLATFORM_I386_PC), y) @@ -972,14 +1037,34 @@ KVER := $(shell uname -r) KSRC := /lib/modules/$(KVER)/build MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/ INSTALL_PREFIX := +STAGINGMODDIR := /lib/modules/$(KVER)/kernel/drivers/staging endif ifeq ($(CONFIG_PLATFORM_NV_TK1), y) EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1 EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +# default setting for Android 4.1, 4.2 EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_PLATFORM_ANDROID +# Enable this for Android 5.0 +EXTRA_CFLAGS += -DCONFIG_RADIO_WORK +EXTRA_CFLAGS += -DRTW_VENDOR_EXT_SUPPORT +EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC ARCH ?= arm + +CROSS_COMPILE := /mnt/newdisk/android_sdk/nvidia_tk1/android_L/prebuilts/gcc/linux-x86/arm/arm-eabi-4.8/bin/arm-eabi- +KSRC :=/mnt/newdisk/android_sdk/nvidia_tk1/android_L/out/target/product/shieldtablet/obj/KERNEL/ +MODULE_NAME = wlan +endif + +ifeq ($(CONFIG_PLATFORM_NV_TK1_UBUNTU), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1 +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT + +ARCH ?= arm + CROSS_COMPILE ?= KVER := $(shell uname -r) KSRC := /lib/modules/$(KVER)/build @@ -1372,17 +1457,6 @@ KVER:= 2.6.31.6 KSRC:= ../code/linux-2.6.31.6-2020/ endif -#Add setting for MN10300 -ifeq ($(CONFIG_PLATFORM_MN10300), y) -EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MN10300 -ARCH := mn10300 -CROSS_COMPILE := mn10300-linux- -KVER := 2.6.32.2 -KSRC := /home/winuser/work/Plat_sLD2T_V3010/usr/src/linux-2.6.32.2 -INSTALL_PREFIX := -endif - - ifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUNxI @@ -1536,10 +1610,9 @@ endif ifeq ($(CONFIG_PLATFORM_ARM_RTD299X), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -EXTRA_CFLAGS += -DUSB_XMITBUF_ALIGN_SZ=1024 -DUSB_PACKET_OFFSET_SZ=0 EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE -ifeq ($(CONFIG_ANDROID), y) EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +ifeq ($(CONFIG_ANDROID), y) # Enable this for Android 5.0 EXTRA_CFLAGS += -DCONFIG_RADIO_WORK endif @@ -1563,6 +1636,39 @@ ifeq ($(KSRC),) endif endif +ifeq ($(CONFIG_PLATFORM_HISILICON_HI3798), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON +EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON_HI3798 +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +# default setting for Android +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 +EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT +# default setting for Android 5.x and later +#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK + +ifeq ($(CONFIG_SDIO_HCI), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +_PLATFORM_FILES += platform/platform_hisilicon_hi3798_sdio.o +EXTRA_CFLAGS += -DCONFIG_HISI_SDIO_ID=1 +endif + +ARCH ?= arm +CROSS_COMPILE ?= /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/tools/linux/toolchains/arm-histbv310-linux/bin/arm-histbv310-linux- +ifndef KSRC +KSRC := /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/source/kernel/linux-3.18.y +KSRC += O=/HiSTBAndroidV600R003C00SPC021_git_0512/out/target/product/Hi3798MV200/obj/KERNEL_OBJ +endif + +ifeq ($(CONFIG_RTL8822B), y) +ifeq ($(CONFIG_SDIO_HCI), y) +CONFIG_RTL8822BS ?= m +USER_MODULE_NAME := rtl8822bs +endif +endif + +endif + # Platform setting ifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_6820), y) ifeq ($(CONFIG_ANDROID_2X), y) @@ -1653,6 +1759,10 @@ EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION # Enable this for Android 5.0 EXTRA_CFLAGS += -DCONFIG_RADIO_WORK +ifeq ($(CONFIG_RTL8821C)$(CONFIG_SDIO_HCI),yy) +EXTRA_CFLAGS += -DCONFIG_WAKEUP_GPIO_INPUT_MODE +EXTRA_CFLAGS += -DCONFIG_BT_WAKE_HST_OPEN_DRAIN +endif EXTRA_CFLAGS += -Wno-error=date-time # default setting for Android 7.0 ifeq ($(RTK_ANDROID_VERSION), nougat) @@ -1667,10 +1777,11 @@ ARCH := arm64 # ==== Cross compile setting for Android 4.4 SDK ===== #CROSS_COMPILE := arm-linux-gnueabihf- -KVER := 4.1.10 -CROSS_COMPILE := $(CROSS) -KSRC := $(LINUX_KERNEL_PATH) -MODULE_NAME := 8822be +#KVER := 4.1.10 +#CROSS_COMPILE := $(CROSS) +#KSRC := $(LINUX_KERNEL_PATH) +CROSS_COMPILE := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/phoenix/toolchain/asdk64-4.9.4-a53-EL-3.10-g2.19-a64nt-160307/bin/asdk64-linux- +KSRC := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/linux-kernel endif ifeq ($(CONFIG_PLATFORM_NOVATEK_NT72668), y) @@ -1706,12 +1817,67 @@ CROSS_COMPILE:= $(DIR_LINUX)/../toolchain/rsdk-1.5.5-5281-EB-2.6.30-0.9.30.3-110 KSRC := $(DIR_LINUX) endif -# ==== CENTOS ===== -CHECK_KVER := $(subst ., ,$(KVER)) -ifeq ($(findstring el7, $(CHECK_KVER)), el7) -EXTRA_CFLAGS += -DCONFIG_CENTOS_7 +ifeq ($(CONFIG_PLATFORM_AML_S905), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_AML_S905 +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -fno-pic +# default setting for Android +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 +EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT +# default setting for Android 5.x and later +EXTRA_CFLAGS += -DCONFIG_RADIO_WORK + +ifeq ($(CONFIG_SDIO_HCI), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +_PLATFORM_FILES += platform/platform_aml_s905_sdio.o +endif + +ARCH ?= arm64 +CROSS_COMPILE ?= /4.4_S905L_8822bs_compile/gcc-linaro-aarch64-linux-gnu-4.9-2014.09_linux/bin/aarch64-linux-gnu- +ifndef KSRC +KSRC := /4.4_S905L_8822bs_compile/common +# To locate output files in a separate directory. +KSRC += O=/4.4_S905L_8822bs_compile/KERNEL_OBJ +endif + +ifeq ($(CONFIG_RTL8822B), y) +ifeq ($(CONFIG_SDIO_HCI), y) +CONFIG_RTL8822BS ?= m +USER_MODULE_NAME := 8822bs +endif +endif + +endif + +ifeq ($(CONFIG_PLATFORM_ZTE_ZX296716), y) +EXTRA_CFLAGS += -Wno-error=date-time +EXTRA_CFLAGS += -DCONFIG_PLATFORM_ZTE_ZX296716 +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +# default setting for Android +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 +EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT +# default setting for Android 5.x and later +#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK + +ifeq ($(CONFIG_SDIO_HCI), y) +# mark this temporarily +#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +#_PLATFORM_FILES += platform/platform_zte_zx296716_sdio.o +endif + +ARCH ?= arm64 +CROSS_COMPILE ?= +KSRC ?= + +ifeq ($(CONFIG_RTL8822B), y) +ifeq ($(CONFIG_SDIO_HCI), y) +CONFIG_RTL8822BS ?= m +USER_MODULE_NAME := 8822bs +endif +endif + endif -# ============== ifeq ($(CONFIG_MULTIDRV), y) @@ -1737,6 +1903,19 @@ endif ifneq ($(KERNELRELEASE),) +########### this part for *.mk ############################ +include $(src)/hal/phydm/phydm.mk + +########### HAL_RTL8822B ################################# +ifeq ($(CONFIG_RTL8822B), y) +include $(src)/rtl8822b.mk +endif + +########### HAL_RTL8821C ################################# +ifeq ($(CONFIG_RTL8821C), y) +include $(src)/rtl8821c.mk +endif + rtk_core := core/rtw_cmd.o \ core/rtw_security.o \ core/rtw_debug.o \ @@ -1754,8 +1933,12 @@ rtk_core := core/rtw_cmd.o \ core/rtw_recv.o \ core/rtw_sta_mgt.o \ core/rtw_ap.o \ + core/mesh/rtw_mesh.o \ + core/mesh/rtw_mesh_pathtbl.o \ + core/mesh/rtw_mesh_hwmp.o \ core/rtw_xmit.o \ core/rtw_p2p.o \ + core/rtw_rson.o \ core/rtw_tdls.o \ core/rtw_br_ext.o \ core/rtw_iol.o \ @@ -1764,6 +1947,8 @@ rtk_core := core/rtw_cmd.o \ core/rtw_btcoex.o \ core/rtw_beamforming.o \ core/rtw_odm.o \ + core/rtw_rm.o \ + core/rtw_rm_fsm.o \ core/efuse/rtw_efuse.o ifeq ($(CONFIG_SDIO_HCI), y) @@ -1811,6 +1996,40 @@ uninstall: rm -f $(MODDESTDIR)/$(MODULE_NAME).ko /sbin/depmod -a ${KVER} +backup_rtlwifi: + @echo "Making backup rtlwifi drivers" +ifneq (,$(wildcard $(STAGINGMODDIR)/rtl*)) + @tar cPf $(wildcard $(STAGINGMODDIR))/backup_rtlwifi_driver.tar $(wildcard $(STAGINGMODDIR)/rtl*) + @rm -rf $(wildcard $(STAGINGMODDIR)/rtl*) +endif +ifneq (,$(wildcard $(MODDESTDIR)realtek)) + @tar cPf $(MODDESTDIR)backup_rtlwifi_driver.tar $(MODDESTDIR)realtek + @rm -fr $(MODDESTDIR)realtek +endif +ifneq (,$(wildcard $(MODDESTDIR)rtl*)) + @tar cPf $(MODDESTDIR)../backup_rtlwifi_driver.tar $(wildcard $(MODDESTDIR)rtl*) + @rm -fr $(wildcard $(MODDESTDIR)rtl*) +endif + @/sbin/depmod -a ${KVER} + @echo "Please reboot your system" + +restore_rtlwifi: + @echo "Restoring backups" +ifneq (,$(wildcard $(STAGINGMODDIR)/backup_rtlwifi_driver.tar)) + @tar xPf $(STAGINGMODDIR)/backup_rtlwifi_driver.tar + @rm $(STAGINGMODDIR)/backup_rtlwifi_driver.tar +endif +ifneq (,$(wildcard $(MODDESTDIR)backup_rtlwifi_driver.tar)) + @tar xPf $(MODDESTDIR)backup_rtlwifi_driver.tar + @rm $(MODDESTDIR)backup_rtlwifi_driver.tar +endif +ifneq (,$(wildcard $(MODDESTDIR)../backup_rtlwifi_driver.tar)) + @tar xPf $(MODDESTDIR)../backup_rtlwifi_driver.tar + @rm $(MODDESTDIR)../backup_rtlwifi_driver.tar +endif + @/sbin/depmod -a ${KVER} + @echo "Please reboot your system" + config_r: @echo "make config" /bin/bash script/Configure script/config.in @@ -1824,7 +2043,7 @@ clean: cd hal ; rm -fr */*/*.mod.c */*/*.mod */*/*.o */*/.*.cmd */*/*.ko cd hal ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko - cd core/efuse ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko + cd core ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko cd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko cd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko cd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko diff --git a/README.md b/README.md deleted file mode 100644 index 135bd08..0000000 --- a/README.md +++ /dev/null @@ -1,47 +0,0 @@ -**8822BU for Linux** - -Driver for 802.11ac USB Adapter with -RTL8822BU chipset -Only STA/Monitor Mode is supported, no AP. - -A few known wireless cards that use this driver include -* [Edimax EW-7822ULC](http://us.edimax.com/edimax/merchandise/merchandise_detail/data/edimax/us/wireless_adapters_ac1200_dual-band/ew-7822ulc/) -* [ASUS AC-53 NANO](https://www.asus.com/Networking/USB-AC53-Nano/) -* [D-Link DWA-182 (Revision D1 only)](http://ca.dlink.com/products/connect/wireless-ac1200-dual-band-usb-adapter/) - - -> NOTE: At least v4.7 is needed to compile this module -> sorry people with older kernels, the code is removed. -> Upon request I can work towards making it backwards compatible. - -Currently tested on X86_64 and ARM platform(s) **only**, -cross compile possible. - -For compiling type -`make` -in source dir - -To install the firmware files -`sudo make install` - - -To Unload driver you may need to disconnect the device - -If the driver fails building consult your distro how to -install the kernel sources and build an external module. - - -**NOTES** -This driver allows use of wpa_supplicant by using the nl80211 driver -`wpa_supplicant -Dnl80211` - -If installing on Rasberry Pi or other "armv71" devices, edit the Makefile and set `CONFIG_PLATFORM_ARM_RPI = y` and `CONFIG_PLATFORM_I386_PC = n` - -**STATUS** -Driver works fine (some sort of) -Most of the work is done is cleaning the driver and make this mess **readable** for conversion. -Updates for wireless-ext/cfg80211 are not accepted. - - -**BUGS** - diff --git a/RTL8822Bfw_NIC.bin b/RTL8822Bfw_NIC.bin deleted file mode 100644 index ff8a12c76919df9184a70cf86ba312dc5c724382..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 113632 zcmeFaeSB5bnJ>Q2Yfjz|FTw$NIh>$k1jT@guN;y9c|$^oEh=bolDI>10*F{>M}{Lh z9qUj>6I$(|xtE><+Xn2s_IH_k%PkE!V?pm&st%>skpbG#K&K~=Ks#+c_xoLIuf6v< z35YZOeR}`6fpzxU>*ZO`de-wi>shZm^qeOCw%#b8xzh@KA7p8o53gE^-Qo1)5`i3_%cZ%qv-s=tx}5m+xEz{0KPSth`SNnI+?p>p#|wXM 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z^=(3w7Mpr>^jZ4Bpi8a!SD9aKE;9?2u9IgL?ZZD5a`S49nP;J!%gohGHFAcVS*dHU z;g7|?B+W#`Gky~yrRv%+dwOvX@0rhl%{%4GT+w$$;yk%6L>eVR)qzFiT$*(kO?UZ* z%U`a=RkfY2v6-l~b}qT{KHNiBE4jmoV$8)W_FTkUhwq}#yT?L`@^M{Dl)9OZspUz0 z*Q6$M>{k;3JFiN@S_9Sq$Vi;o%Su{+oz5tIVAjs1Zywg;u1iTuv_HQQZFpx~ z`;(Q{AGVN-yy@_nRV*3D+ySNMEywES_T_ru^V#_R%OD_-F%LWVGGneh$>8A3BrWS& zo1E8-xsE|9JSJ6Fbh9T)rG$tBSyvil$`P**vgEvf49MJBXLyRrGs!&V{jKcEEkckQ zify_5>_+$b;6_Lxo|#!Fr}+GBfc!=Y#hoEW3ef#3Z>to%4ND5_YSj9-Ii3qYInW4| zR%{{{xfy)8IcCzHk+dm7wd>=#FBI5v=g!TBn@zsQqYSs&;b`BVUUWeBc$B^Srx$zP zUcxur!Ws3*{2|!0i00=*9xYR0(4=OKxw=(Y|ja$UH=8c+jNfR3*Fv|9VcPEDXo;w znbcANDOEY3nu{ent5O4POU+M!7VQ3YVQP1ujiB5E!_UQw?02S|lrWd8kNmrDwK{ zvFwUMSoo!nx{jt9i}K4#E5$m-ve%}Cb>V@registrypriv.boffefusemask == 0) { + + for (i = 0; i < cnts; i++) { + if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { + if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask.*/ + data[i] = 0xff; + } else { + /*RTW_INFO(" %s , data[%d] = %x\n", __func__, i, data[i]);*/ + if (efuse_IsMasked(padapter, addr + i)) { + data[i] = 0xff; + /*RTW_INFO(" %s ,mask data[%d] = %x\n", __func__, i, data[i]);*/ + } + } + } + + } +} + u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) { u8 ret = _SUCCESS; - u16 mapLen = 0, i = 0; + u16 mapLen = 0; EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); ret = rtw_efuse_map_read(padapter, addr, cnts , data); - if (padapter->registrypriv.boffefusemask == 0) { + rtw_mask_map_read(padapter, addr, cnts , data); - for (i = 0; i < cnts; i++) { - if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { - if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask.*/ - data[i] = 0xff; - } else { - /*RTW_INFO(" %s , data[%d] = %x\n", __func__, i, data[i]);*/ - if (efuse_IsMasked(padapter, addr + i)) { - data[i] = 0xff; - /*RTW_INFO(" %s ,mask data[%d] = %x\n", __func__, i, data[i]);*/ - } - } - } - - } return ret; } @@ -715,6 +723,51 @@ void rtw_efuse_analyze(PADAPTER padapter, u8 Type, u8 Fake) rtw_mfree((u8 *)eFuseWord, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2)); } +VOID efuse_PreUpdateAction( + PADAPTER pAdapter, + pu4Byte BackupRegs) +{ + if (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) { + /* <20131115, Kordan> Turn off Rx to prevent from being busy when writing the EFUSE. (Asked by Chunchu.)*/ + BackupRegs[0] = phy_query_mac_reg(pAdapter, REG_RCR, bMaskDWord); + BackupRegs[1] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord); + BackupRegs[2] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord); +#ifdef CONFIG_RTL8812A + BackupRegs[3] = phy_query_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord); +#endif + PlatformEFIOWrite4Byte(pAdapter, REG_RCR, 0x1); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+1, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+2, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+3, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+4, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+5, 0); +#ifdef CONFIG_RTL8812A + /* <20140410, Kordan> 0x11 = 0x4E, lower down LX_SPS0 voltage. (Asked by Chunchu)*/ + phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskByte1, 0x4E); +#endif + RTW_INFO(" %s , done\n", __func__); + + } +} + + +VOID efuse_PostUpdateAction( + PADAPTER pAdapter, + pu4Byte BackupRegs) +{ + if (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) { + /* <20131115, Kordan> Turn on Rx and restore the registers. (Asked by Chunchu.)*/ + phy_set_mac_reg(pAdapter, REG_RCR, bMaskDWord, BackupRegs[0]); + phy_set_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord, BackupRegs[1]); + phy_set_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord, BackupRegs[2]); +#ifdef CONFIG_RTL8812A + phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord, BackupRegs[3]); +#endif + RTW_INFO(" %s , done\n", __func__); + } +} + #ifdef RTW_HALMAC #include "../../hal/hal_halmac.h" @@ -937,40 +990,52 @@ u8 rtw_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) u8 *efuse = NULL; u32 size, i; int err; + u32 backupRegs[4] = {0}; + u8 status = _SUCCESS; + efuse_PreUpdateAction(adapter, backupRegs); d = adapter_to_dvobj(adapter); err = rtw_halmac_get_logical_efuse_size(d, &size); - if (err) - return _FAIL; - + if (err) { + status = _FAIL; + goto exit; + } /* size error handle */ if ((addr + cnts) > size) { if (addr < size) cnts = size - addr; - else - return _FAIL; + else { + status = _FAIL; + goto exit; + } } if (cnts > 16) efuse = rtw_zmalloc(size); if (efuse) { - err = rtw_halmac_read_logical_efuse_map(d, efuse, size); + err = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0); if (err) { rtw_mfree(efuse, size); - return _FAIL; + status = _FAIL; + goto exit; } _rtw_memcpy(data, efuse + addr, cnts); rtw_mfree(efuse, size); } else { err = rtw_halmac_read_logical_efuse(d, addr, cnts, data); - if (err) - return _FAIL; + if (err) { + status = _FAIL; + goto exit; + } } + status = _SUCCESS; +exit: + efuse_PostUpdateAction(adapter, backupRegs); - return _SUCCESS; + return status; } u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) @@ -981,23 +1046,34 @@ u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) int err; u8 mask_buf[64] = ""; u16 mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(adapter); + u32 backupRegs[4] = {0}; + u8 status = _SUCCESS;; + + efuse_PreUpdateAction(adapter, backupRegs); d = adapter_to_dvobj(adapter); err = rtw_halmac_get_logical_efuse_size(d, &size); - if (err) - return _FAIL; + if (err) { + status = _FAIL; + goto exit; + } - if ((addr + cnts) > size) - return _FAIL; + if ((addr + cnts) > size) { + status = _FAIL; + goto exit; + } efuse = rtw_zmalloc(size); - if (!efuse) - return _FAIL; + if (!efuse) { + status = _FAIL; + goto exit; + } - err = rtw_halmac_read_logical_efuse_map(d, efuse, size); + err = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0); if (err) { rtw_mfree(efuse, size); - return _FAIL; + status = _FAIL; + goto exit; } _rtw_memcpy(efuse + addr, data, cnts); @@ -1022,12 +1098,16 @@ u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) if (err) { rtw_mfree(efuse, size); - return _FAIL; + status = _FAIL; + goto exit; } rtw_mfree(efuse, size); + status = _SUCCESS; +exit : + efuse_PostUpdateAction(adapter, backupRegs); - return _SUCCESS; + return status; } int Efuse_PgPacketRead(PADAPTER adapter, u8 offset, u8 *data, BOOLEAN test) @@ -1517,61 +1597,23 @@ hal_EfusePgPacketWriteData( return _TRUE; } - -#define EFUSE_CTRL 0x30 /* E-Fuse Control. */ - -/* 11/16/2008 MH Read one byte from real Efuse. */ -u8 -efuse_OneByteRead( - IN PADAPTER pAdapter, - IN u16 addr, - IN u8 *data, - IN BOOLEAN bPseudoTest) +u8 efuse_OneByteRead(struct _ADAPTER *a, u16 addr, u8 *data, u8 bPseudoTest) { - u32 tmpidx = 0; - u8 bResult; - u8 readbyte; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - if (IS_HARDWARE_TYPE_8723B(pAdapter) || - (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) || - (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id)) - ) { - /* <20130121, Kordan> For SMIC EFUSE specificatoin. */ - /* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */ - /* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */ - rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) & (~BIT11)); - } + struct dvobj_priv *d; + int err; + u8 ret = _TRUE; - /* -----------------e-fuse reg ctrl --------------------------------- */ - /* address */ - rtw_write8(pAdapter, EFUSE_CTRL + 1, (u8)(addr & 0xff)); - rtw_write8(pAdapter, EFUSE_CTRL + 2, ((u8)((addr >> 8) & 0x03)) | - (rtw_read8(pAdapter, EFUSE_CTRL + 2) & 0xFC)); - - /* rtw_write8(pAdapter, EFUSE_CTRL+3, 0x72); */ /* read cmd */ - /* Write bit 32 0 */ - readbyte = rtw_read8(pAdapter, EFUSE_CTRL + 3); - rtw_write8(pAdapter, EFUSE_CTRL + 3, (readbyte & 0x7f)); - - while (!(0x80 & rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 1000)) { - rtw_mdelay_os(1); - tmpidx++; - } - if (tmpidx < 100) { - *data = rtw_read8(pAdapter, EFUSE_CTRL); - bResult = _TRUE; - } else { - *data = 0xff; - bResult = _FALSE; - RTW_INFO("%s: [ERROR] addr=0x%x bResult=%d time out 1s !!!\n", __FUNCTION__, addr, bResult); - RTW_INFO("%s: [ERROR] EFUSE_CTRL =0x%08x !!!\n", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL)); - } + d = adapter_to_dvobj(a); + err = rtw_halmac_read_physical_efuse(d, addr, 1, data); + if (err) { + RTW_ERR("%s: addr=0x%x FAIL!!!\n", __FUNCTION__, addr); + ret = _FALSE; + } - return bResult; + return ret; + } - static u16 hal_EfuseGetCurrentSize_BT( PADAPTER padapter, @@ -1711,47 +1753,6 @@ u8 EfusePgPacketWrite_BT( #define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ /* ------------------------------------------------------------------------------ */ -VOID efuse_PreUpdateAction( - PADAPTER pAdapter, - pu4Byte BackupRegs) -{ -#if defined(CONFIG_RTL8812A) - if (IS_HARDWARE_TYPE_8812AU(pAdapter)) { - /* <20131115, Kordan> Turn off Rx to prevent from being busy when writing the EFUSE. (Asked by Chunchu.)*/ - BackupRegs[0] = phy_query_mac_reg(pAdapter, REG_RCR, bMaskDWord); - BackupRegs[1] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord); - BackupRegs[2] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord); - BackupRegs[3] = phy_query_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord); - - PlatformEFIOWrite4Byte(pAdapter, REG_RCR, 0x1); - PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0, 0); - PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+1, 0); - PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+2, 0); - PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+3, 0); - PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+4, 0); - PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+5, 0); - - /* <20140410, Kordan> 0x11 = 0x4E, lower down LX_SPS0 voltage. (Asked by Chunchu)*/ - phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskByte1, 0x4E); - } -#endif -} - -VOID efuse_PostUpdateAction( - PADAPTER pAdapter, - pu4Byte BackupRegs) -{ -#if defined(CONFIG_RTL8812A) - if (IS_HARDWARE_TYPE_8812AU(pAdapter)) { - /* <20131115, Kordan> Turn on Rx and restore the registers. (Asked by Chunchu.)*/ - phy_set_mac_reg(pAdapter, REG_RCR, bMaskDWord, BackupRegs[0]); - phy_set_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord, BackupRegs[1]); - phy_set_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord, BackupRegs[2]); - phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord, BackupRegs[3]); - } -#endif -} - BOOLEAN Efuse_Read1ByteFromFakeContent( @@ -1881,7 +1882,7 @@ ReadEFuseByte( u32 value32; u8 readbyte; u16 retry; - /* u32 start=rtw_get_current_time(); */ + /* systime start=rtw_get_current_time(); */ if (bPseudoTest) { Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf); @@ -2304,8 +2305,9 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) return _FAIL; \ } + u8 *efuse = NULL; u8 offset, word_en; - u8 *map; + u8 *map = NULL; u8 newdata[PGPKT_DATA_SIZE]; s32 i, j, idx, chk_total_byte; u8 ret = _SUCCESS; @@ -2324,9 +2326,15 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */ RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */ + efuse = rtw_zmalloc(mapLen); + if (!efuse) + return _FAIL; + map = rtw_zmalloc(mapLen); - if (map == NULL) + if (map == NULL) { + rtw_mfree(efuse, mapLen); return _FAIL; + } _rtw_memset(map, 0xFF, mapLen); @@ -2334,16 +2342,19 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) if (ret == _FAIL) goto exit; + _rtw_memcpy(efuse , map, mapLen); + _rtw_memcpy(efuse + addr, data, cnts); + if (padapter->registrypriv.boffefusemask == 0) { for (i = 0; i < cnts; i++) { if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask. */ - data[i] = map[addr + i]; + efuse[addr + i] = map[addr + i]; } else { if (efuse_IsMasked(padapter, addr + i)) - data[i] = map[addr + i]; + efuse[addr + i] = map[addr + i]; } - RTW_INFO("%s , data[%d] = %x, map[addr+i]= %x\n", __func__, i, data[i], map[addr + i]); + RTW_INFO("%s , data[%d] = %x, map[addr+i]= %x\n", __func__, addr + i, efuse[ addr + i], map[addr + i]); } } /*Efuse_PowerSwitch(padapter, _TRUE, _TRUE);*/ @@ -2356,7 +2367,7 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) word_en = 0xF; j = (addr + idx) & 0x7; for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) { - if (data[idx] != map[addr + idx]) + if (efuse[addr + idx] != map[addr + idx]) word_en &= ~BIT(i >> 1); } @@ -2397,9 +2408,9 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) j = (addr + idx) & 0x7; _rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE); for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) { - if (data[idx] != map[addr + idx]) { + if (efuse[addr + idx] != map[addr + idx]) { word_en &= ~BIT(i >> 1); - newdata[i] = data[idx]; + newdata[i] = efuse[addr + idx]; #ifdef CONFIG_RTL8723B if (addr + idx == 0x8) { if (IS_C_CUT(pHalData->version_id) || IS_B_CUT(pHalData->version_id)) { @@ -2434,6 +2445,7 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) exit: rtw_mfree(map, mapLen); + rtw_mfree(efuse, mapLen); return ret; } @@ -2883,7 +2895,7 @@ void EFUSE_ShadowMapUpdate( } if (pHalData->bautoload_fail_flag == _FALSE) { - err = rtw_halmac_read_logical_efuse_map(adapter_to_dvobj(pAdapter), efuse_map, mapLen); + err = rtw_halmac_read_logical_efuse_map(adapter_to_dvobj(pAdapter), efuse_map, mapLen, NULL, 0); if (err) RTW_ERR("%s: fail to get efuse map!\n", __FUNCTION__); } @@ -2909,6 +2921,8 @@ void EFUSE_ShadowMapUpdate( /* (PVOID)&pHalData->EfuseMap[EFUSE_INIT_MAP][0], mapLen); */ #endif /* !RTW_HALMAC */ + rtw_mask_map_read(pAdapter, 0x00, mapLen, pHalData->efuse_eeprom_data); + rtw_dump_cur_efuse(pAdapter); } /* EFUSE_ShadowMapUpdate */ @@ -3015,7 +3029,7 @@ u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len) return _FALSE; count = rtw_retrieve_from_file(filepatch, ptmpbuf, bufsize); - if (count <= 100) { + if (count <= 90) { rtw_mfree(ptmpbuf, bufsize); RTW_ERR("%s, filepatch %s, size=%d, FAIL!!\n", __FUNCTION__, filepatch, count); return _FALSE; diff --git a/core/rtw_ap.c b/core/rtw_ap.c index 99425b2..b110139 100644 --- a/core/rtw_ap.c +++ b/core/rtw_ap.c @@ -45,6 +45,49 @@ void free_mlme_ap_info(_adapter *padapter) } +/* +* Set TIM IE +* return length of total TIM IE +*/ +u8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period + , const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie) +{ + u8 *p = tim_ie; + u8 i, n1, n2; + u8 bmp_len; + + if (rtw_bmp_not_empty(tim_bmp, tim_bmp_len)) { + /* find the first nonzero octet in tim_bitmap */ + for (i = 0; i < tim_bmp_len; i++) + if (tim_bmp[i]) + break; + n1 = i & 0xFE; + + /* find the last nonzero octet in tim_bitmap, except octet 0 */ + for (i = tim_bmp_len - 1; i > 0; i--) + if (tim_bmp[i]) + break; + n2 = i; + bmp_len = n2 - n1 + 1; + } else { + n1 = n2 = 0; + bmp_len = 1; + } + + *p++ = WLAN_EID_TIM; + *p++ = 2 + 1 + bmp_len; + *p++ = dtim_cnt; + *p++ = dtim_period; + *p++ = (rtw_bmp_is_set(tim_bmp, tim_bmp_len, 0) ? BIT0 : 0) | n1; + _rtw_memcpy(p, tim_bmp + n1, bmp_len); + +#if 0 + RTW_INFO("n1:%u, n2:%u, bmp_offset:%u, bmp_len:%u\n", n1, n2, n1 / 2, bmp_len); + RTW_INFO_DUMP("tim_ie: ", tim_ie + 2, 2 + 1 + bmp_len); +#endif + return 2 + 2 + 1 + bmp_len; +} + static void update_BCNTIM(_adapter *padapter) { struct sta_priv *pstapriv = &padapter->stapriv; @@ -57,15 +100,12 @@ static void update_BCNTIM(_adapter *padapter) /* update TIM IE */ - /* if(pstapriv->tim_bitmap) */ + /* if(rtw_tim_map_anyone_be_set(padapter, pstapriv->tim_bitmap)) */ #endif if (_TRUE) { u8 *p, *dst_ie, *premainder_ie = NULL, *pbackup_remainder_ie = NULL; - u16 tim_bitmap_le; uint offset, tmp_len, tim_ielen, tim_ie_offset, remainder_ielen; - tim_bitmap_le = cpu_to_le16(pstapriv->tim_bitmap); - p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, _TIM_IE_, &tim_ielen, pnetwork_mlmeext->IELength - _FIXED_IE_LENGTH_); if (p != NULL && tim_ielen > 0) { tim_ielen += 2; @@ -112,39 +152,8 @@ static void update_BCNTIM(_adapter *padapter) _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); } - *dst_ie++ = _TIM_IE_; - - if ((pstapriv->tim_bitmap & 0xff00) && (pstapriv->tim_bitmap & 0x00fe)) - tim_ielen = 5; - else - tim_ielen = 4; - - *dst_ie++ = tim_ielen; - - *dst_ie++ = 0;/*DTIM count*/ - *dst_ie++ = 1;/*DTIM period*/ - - if (pstapriv->tim_bitmap & BIT(0))/*for bc/mc frames*/ - *dst_ie++ = BIT(0);/*bitmap ctrl */ - else - *dst_ie++ = 0; - - if (tim_ielen == 4) { - u8 pvb = 0; - - if (pstapriv->tim_bitmap & 0x00fe) - pvb = (u8)tim_bitmap_le; - else if (pstapriv->tim_bitmap & 0xff00) - pvb = (u8)(tim_bitmap_le >> 8); - else - pvb = (u8)tim_bitmap_le; - - *dst_ie++ = pvb; - - } else if (tim_ielen == 5) { - _rtw_memcpy(dst_ie, &tim_bitmap_le, 2); - dst_ie += 2; - } + /* append TIM IE */ + dst_ie += rtw_set_tim_ie(0, 1, pstapriv->tim_bitmap, pstapriv->aid_bmp_len, dst_ie); /*copy remainder IE*/ if (pbackup_remainder_ie) { @@ -269,8 +278,8 @@ u8 chk_sta_is_alive(struct sta_info *psta) u8 ret = _FALSE; #ifdef DBG_EXPIRATION_CHK RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", expire_to:%u, %s%ssq_len:%u\n" - , MAC_ARG(psta->hwaddr) - , psta->rssi_stat.undecorated_smoothed_pwdb + , MAC_ARG(psta->cmn.mac_addr) + , psta->cmn.rssi_stat.rssi /* , STA_RX_PKTS_ARG(psta) */ , STA_RX_PKTS_DIFF_ARG(psta) , psta->expire_to @@ -305,6 +314,18 @@ void expire_timeout_chk(_adapter *padapter) char chk_alive_list[NUM_STA]; int i; +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter) + && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) + ) { + struct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg; + + rtw_mesh_path_expire(padapter); + + if (!mcfg->plink_timeout) + return; + } +#endif #ifdef CONFIG_MCC_MODE /* then driver may check fail due to not recv client's frame under sitesurvey, @@ -333,7 +354,7 @@ void expire_timeout_chk(_adapter *padapter) #ifdef CONFIG_ATMEL_RC_PATCH - if (_TRUE == _rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->hwaddr), ETH_ALEN)) + if (_rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE) continue; if (psta->flag_atmel_rc) continue; @@ -345,7 +366,8 @@ void expire_timeout_chk(_adapter *padapter) pstapriv->auth_list_cnt--; RTW_INFO("auth expire %02X%02X%02X%02X%02X%02X\n", - psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2], psta->hwaddr[3], psta->hwaddr[4], psta->hwaddr[5]); + psta->cmn.mac_addr[0], psta->cmn.mac_addr[1], psta->cmn.mac_addr[2], + psta->cmn.mac_addr[3], psta->cmn.mac_addr[4], psta->cmn.mac_addr[5]); _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); @@ -380,8 +402,8 @@ void expire_timeout_chk(_adapter *padapter) plist = get_next(plist); #ifdef CONFIG_ATMEL_RC_PATCH RTW_INFO("%s:%d psta=%p, %02x,%02x||%02x,%02x \n\n", __func__, __LINE__, - psta, pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->hwaddr[0], psta->hwaddr[5]); - if (_TRUE == _rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->hwaddr), ETH_ALEN)) + psta, pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->cmn.mac_addr[0], psta->cmn.mac_addr[5]); + if (_rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE) continue; if (psta->flag_atmel_rc) continue; @@ -416,7 +438,7 @@ void expire_timeout_chk(_adapter *padapter) RTW_INFO("asoc check by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to - psta->expire_to) * 2); psta->under_exist_checking = 1; /* tear down TX AMPDU */ - send_delba(padapter, 1, psta->hwaddr);/* */ /* originator */ + send_delba(padapter, 1, psta->cmn.mac_addr);/* */ /* originator */ psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ } @@ -468,7 +490,7 @@ void expire_timeout_chk(_adapter *padapter) RTW_INFO("issue addba_req to check if sta alive, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt); - issue_addba_req(padapter, psta->hwaddr, (u8)priority); + issue_addba_req(padapter, psta->cmn.mac_addr, (u8)priority); _set_timer(&psta->addba_retry_timer, ADDBA_TO); @@ -492,38 +514,32 @@ void expire_timeout_chk(_adapter *padapter) psta->expire_to = pstapriv->expire_to; psta->state |= WIFI_STA_ALIVE_CHK_STATE; - /* RTW_INFO("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->hwaddr)); */ + /* RTW_INFO("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->cmn.mac_addr)); */ /* to update bcn with tim_bitmap for this station */ - pstapriv->tim_bitmap |= BIT(psta->aid); + rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid); update_beacon(padapter, _TIM_IE_, NULL, _TRUE); if (!pmlmeext->active_keep_alive_check) continue; } } -#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK - if (pmlmeext->active_keep_alive_check) { + + { int stainfo_offset; stainfo_offset = rtw_stainfo_offset(pstapriv, psta); if (stainfo_offset_valid(stainfo_offset)) chk_alive_list[chk_alive_num++] = stainfo_offset; - continue; } -#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ - rtw_list_delete(&psta->asoc_list); - pstapriv->asoc_list_cnt--; - RTW_INFO("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state); - updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); } else { /* TODO: Aging mechanism to digest frames in sleep_q to avoid running out of xmitframe */ if (psta->sleepq_len > (NR_XMITFRAME / pstapriv->asoc_list_cnt) && padapter->xmitpriv.free_xmitframe_cnt < ((NR_XMITFRAME / pstapriv->asoc_list_cnt) / 2) ) { RTW_INFO("%s sta:"MAC_FMT", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\n", __func__ - , MAC_ARG(psta->hwaddr) + , MAC_ARG(psta->cmn.mac_addr) , psta->sleepq_len, padapter->xmitpriv.free_xmitframe_cnt, pstapriv->asoc_list_cnt); wakeup_sta_to_xmit(padapter, psta); } @@ -532,115 +548,140 @@ void expire_timeout_chk(_adapter *padapter) _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); -#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK if (chk_alive_num) { - u8 backup_ch = 0, backup_bw = 0, backup_offset = 0; - u8 union_ch = 0, union_bw, union_offset; - u8 switch_channel = _TRUE; + u8 union_ch = 0, union_bw = 0, union_offset = 0; + u8 switch_channel_by_drv = _TRUE; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + char del_asoc_list[NUM_STA]; - if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) - || pmlmeext->cur_channel != union_ch) - goto bypass_active_keep_alive; + _rtw_memset(del_asoc_list, NUM_STA, NUM_STA); -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - /* driver doesn't switch channel under MCC */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) - switch_channel = _FALSE; - } -#endif - /* switch to correct channel of current network before issue keep-alive frames */ - if (switch_channel == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { - backup_ch = rtw_get_oper_ch(padapter); - backup_bw = rtw_get_oper_bw(padapter); - backup_offset = rtw_get_oper_choffset(padapter); - set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + if (pmlmeext->active_keep_alive_check) { + #ifdef CONFIG_MCC_MODE + if (MCC_EN(padapter)) { + /* driver doesn't switch channel under MCC */ + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + switch_channel_by_drv = _FALSE; + } + #endif + + if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) + || pmlmeext->cur_channel != union_ch) + switch_channel_by_drv = _FALSE; + + /* switch to correct channel of current network before issue keep-alive frames */ + if (switch_channel_by_drv == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { + backup_ch = rtw_get_oper_ch(padapter); + backup_bw = rtw_get_oper_bw(padapter); + backup_offset = rtw_get_oper_choffset(padapter); + set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + } } + #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ - /* issue null data to check sta alive*/ + /* check loop */ for (i = 0; i < chk_alive_num; i++) { int ret = _FAIL; psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); -#ifdef CONFIG_ATMEL_RC_PATCH - if (_TRUE == _rtw_memcmp(pstapriv->atmel_rc_pattern, psta->hwaddr, ETH_ALEN)) + + #ifdef CONFIG_ATMEL_RC_PATCH + if (_rtw_memcmp(pstapriv->atmel_rc_pattern, psta->cmn.mac_addr, ETH_ALEN) == _TRUE) continue; if (psta->flag_atmel_rc) continue; -#endif + #endif + if (!(psta->state & _FW_LINKED)) continue; - if (psta->state & WIFI_SLEEP_STATE) - ret = issue_nulldata(padapter, psta->hwaddr, 0, 1, 50); - else - ret = issue_nulldata(padapter, psta->hwaddr, 0, 3, 50); + #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + if (pmlmeext->active_keep_alive_check) { + /* issue null data to check sta alive*/ + if (psta->state & WIFI_SLEEP_STATE) + ret = issue_nulldata(padapter, psta->cmn.mac_addr, 0, 1, 50); + else + ret = issue_nulldata(padapter, psta->cmn.mac_addr, 0, 3, 50); - psta->keep_alive_trycnt++; - if (ret == _SUCCESS) { - RTW_INFO("asoc check, sta(" MAC_FMT ") is alive\n", MAC_ARG(psta->hwaddr)); - psta->expire_to = pstapriv->expire_to; - psta->keep_alive_trycnt = 0; - continue; - } else if (psta->keep_alive_trycnt <= 3) { - RTW_INFO("ack check for asoc expire, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt); - psta->expire_to = 1; - continue; + psta->keep_alive_trycnt++; + if (ret == _SUCCESS) { + RTW_INFO("asoc check, sta(" MAC_FMT ") is alive\n", MAC_ARG(psta->cmn.mac_addr)); + psta->expire_to = pstapriv->expire_to; + psta->keep_alive_trycnt = 0; + continue; + } else if (psta->keep_alive_trycnt <= 3) { + RTW_INFO("ack check for asoc expire, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt); + psta->expire_to = 1; + continue; + } } + #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ psta->keep_alive_trycnt = 0; - RTW_INFO("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state); + del_asoc_list[i] = chk_alive_list[i]; _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; - updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); + STA_SET_MESH_PLINK(psta, NULL); } _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - } - /* back to the original operation channel */ - if (switch_channel && backup_ch > 0) - set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw); + /* delete loop */ + for (i = 0; i < chk_alive_num; i++) { + u8 sta_addr[ETH_ALEN]; + + if (del_asoc_list[i] >= NUM_STA) + continue; + + psta = rtw_get_stainfo_by_offset(pstapriv, del_asoc_list[i]); + _rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN); + + RTW_INFO("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->cmn.mac_addr), psta->state); + updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _FALSE); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_mesh_expire_peer(padapter, sta_addr); + #endif + } -bypass_active_keep_alive: - ; + #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + if (pmlmeext->active_keep_alive_check) { + /* back to the original operation channel */ + if (switch_channel_by_drv == _TRUE && backup_ch > 0) + set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw); + } + #endif } -#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); } -void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level, u8 is_update_bw) +void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta) { int i; u8 rf_type; unsigned char sta_band = 0; u64 tx_ra_bitmap = 0; - struct ht_priv *psta_ht = NULL; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; -#ifdef CONFIG_80211N_HT - if (psta) - psta_ht = &psta->htpriv; - else + if (!psta) return; -#endif /* CONFIG_80211N_HT */ if (!(psta->state & _FW_LINKED)) return; - rtw_hal_update_sta_rate_mask(padapter, psta); - tx_ra_bitmap = psta->ra_mask; + rtw_hal_update_sta_ra_info(padapter, psta); + tx_ra_bitmap = psta->cmn.ra_info.ramask; if (pcur_network->Configuration.DSConfig > 14) { if (tx_ra_bitmap & 0xffff000) - sta_band |= WIRELESS_11_5N ; + sta_band |= WIRELESS_11_5N; if (tx_ra_bitmap & 0xff0) sta_band |= WIRELESS_11A; @@ -650,7 +691,6 @@ void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level, u8 is_u if (psta->vhtpriv.vht_option) sta_band = WIRELESS_11_5AC; #endif - } else { if (tx_ra_bitmap & 0xffff000) sta_band |= WIRELESS_11_24N; @@ -663,16 +703,180 @@ void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level, u8 is_u } psta->wireless_mode = sta_band; - psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + rtw_hal_update_sta_wset(padapter, psta); + RTW_INFO("%s=> mac_id:%d , tx_ra_bitmap:0x%016llx, networkType:0x%02x\n", + __FUNCTION__, psta->cmn.mac_id, tx_ra_bitmap, psta->wireless_mode); +} + +#ifdef CONFIG_BMC_TX_RATE_SELECT +u8 rtw_ap_find_mini_tx_rate(_adapter *adapter) +{ + _irqL irqL; + _list *phead, *plist; + u8 miini_tx_rate = ODM_RATEVHTSS4MCS9, sta_tx_rate; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &adapter->stapriv; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); - if (psta->aid < NUM_STA) { - RTW_INFO("%s=> mac_id:%d , raid:%d, tx_ra_bitmap:0x%016llx, networkType:0x%02x\n", - __FUNCTION__, psta->mac_id, psta->raid, tx_ra_bitmap, psta->wireless_mode); + sta_tx_rate = psta->cmn.ra_info.curr_tx_rate & 0x7F; + if (sta_tx_rate < miini_tx_rate) + miini_tx_rate = sta_tx_rate; + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - rtw_update_ramask(padapter, psta, psta->mac_id, rssi_level, is_update_bw); - } else - RTW_INFO("station aid %d exceed the max number\n", psta->aid); + return miini_tx_rate; +} + +u8 rtw_ap_find_bmc_rate(_adapter *adapter, u8 tx_rate) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + u8 tx_ini_rate = ODM_RATE6M; + + switch (tx_rate) { + case ODM_RATEVHTSS3MCS9: + case ODM_RATEVHTSS3MCS8: + case ODM_RATEVHTSS3MCS7: + case ODM_RATEVHTSS3MCS6: + case ODM_RATEVHTSS3MCS5: + case ODM_RATEVHTSS3MCS4: + case ODM_RATEVHTSS3MCS3: + case ODM_RATEVHTSS2MCS9: + case ODM_RATEVHTSS2MCS8: + case ODM_RATEVHTSS2MCS7: + case ODM_RATEVHTSS2MCS6: + case ODM_RATEVHTSS2MCS5: + case ODM_RATEVHTSS2MCS4: + case ODM_RATEVHTSS2MCS3: + case ODM_RATEVHTSS1MCS9: + case ODM_RATEVHTSS1MCS8: + case ODM_RATEVHTSS1MCS7: + case ODM_RATEVHTSS1MCS6: + case ODM_RATEVHTSS1MCS5: + case ODM_RATEVHTSS1MCS4: + case ODM_RATEVHTSS1MCS3: + case ODM_RATEMCS15: + case ODM_RATEMCS14: + case ODM_RATEMCS13: + case ODM_RATEMCS12: + case ODM_RATEMCS11: + case ODM_RATEMCS7: + case ODM_RATEMCS6: + case ODM_RATEMCS5: + case ODM_RATEMCS4: + case ODM_RATEMCS3: + case ODM_RATE54M: + case ODM_RATE48M: + case ODM_RATE36M: + case ODM_RATE24M: + tx_ini_rate = ODM_RATE24M; + break; + case ODM_RATEVHTSS3MCS2: + case ODM_RATEVHTSS3MCS1: + case ODM_RATEVHTSS2MCS2: + case ODM_RATEVHTSS2MCS1: + case ODM_RATEVHTSS1MCS2: + case ODM_RATEVHTSS1MCS1: + case ODM_RATEMCS10: + case ODM_RATEMCS9: + case ODM_RATEMCS2: + case ODM_RATEMCS1: + case ODM_RATE18M: + case ODM_RATE12M: + tx_ini_rate = ODM_RATE12M; + break; + case ODM_RATEVHTSS3MCS0: + case ODM_RATEVHTSS2MCS0: + case ODM_RATEVHTSS1MCS0: + case ODM_RATEMCS8: + case ODM_RATEMCS0: + case ODM_RATE9M: + case ODM_RATE6M: + tx_ini_rate = ODM_RATE6M; + break; + case ODM_RATE11M: + case ODM_RATE5_5M: + case ODM_RATE2M: + case ODM_RATE1M: + tx_ini_rate = ODM_RATE1M; + break; + default: + tx_ini_rate = ODM_RATE6M; + break; + } + + if (hal_data->current_band_type == BAND_ON_5G) + if (tx_ini_rate < ODM_RATE6M) + tx_ini_rate = ODM_RATE6M; + + return tx_ini_rate; +} + +void rtw_update_bmc_sta_tx_rate(_adapter *adapter) +{ + struct sta_info *psta = NULL; + u8 tx_rate; + + psta = rtw_get_bcmc_stainfo(adapter); + if (psta == NULL) { + RTW_ERR(ADPT_FMT "could not get bmc_sta !!\n", ADPT_ARG(adapter)); + return; + } + + if (adapter->bmc_tx_rate != MGN_UNKNOWN) { + psta->init_rate = adapter->bmc_tx_rate; + goto _exit; + } + + if (adapter->stapriv.asoc_sta_count <= 2) + goto _exit; + + tx_rate = rtw_ap_find_mini_tx_rate(adapter); + #ifdef CONFIG_BMC_TX_LOW_RATE + tx_rate = rtw_ap_find_bmc_rate(adapter, tx_rate); + #endif + + psta->init_rate = hw_rate_to_m_rate(tx_rate); + +_exit: + RTW_INFO(ADPT_FMT" BMC Tx rate - %s\n", ADPT_ARG(adapter), MGN_RATE_STR(psta->init_rate)); +} +#endif + +void rtw_init_bmc_sta_tx_rate(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + u8 rate_idx = 0; + u8 brate_table[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, + MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}; + + if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) + return; + + if (padapter->bmc_tx_rate != MGN_UNKNOWN) + psta->init_rate = padapter->bmc_tx_rate; + else { + #ifdef CONFIG_BMC_TX_LOW_RATE + if (IsEnableHWOFDM(pmlmeext->cur_wireless_mode) && (psta->cmn.ra_info.ramask && 0xFF0)) + rate_idx = get_lowest_rate_idx_ex(psta->cmn.ra_info.ramask, 4); /*from basic rate*/ + else + rate_idx = get_lowest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/ + #else + rate_idx = get_highest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/ + #endif + if (rate_idx < 12) + psta->init_rate = brate_table[rate_idx]; + else + psta->init_rate = MGN_1M; + } + RTW_INFO(ADPT_FMT" BMC Init Tx rate - %s\n", ADPT_ARG(padapter), MGN_RATE_STR(psta->init_rate)); } void update_bmc_sta(_adapter *padapter) @@ -685,8 +889,13 @@ void update_bmc_sta(_adapter *padapter) struct sta_info *psta = rtw_get_bcmc_stainfo(padapter); if (psta) { - psta->aid = 0;/* default set to 0 */ - psta->qos_option = 0; + psta->cmn.aid = 0;/* default set to 0 */ +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + psta->qos_option = 1; + else +#endif + psta->qos_option = 0; #ifdef CONFIG_80211N_HT psta->htpriv.ht_option = _FALSE; #endif /* CONFIG_80211N_HT */ @@ -697,7 +906,6 @@ void update_bmc_sta(_adapter *padapter) /* psta->dot118021XPrivacy = _NO_PRIVACY_; */ /* !!! remove it, because it has been set before this. */ - /* prepare for add_RATid */ supportRateNum = rtw_get_rateset_len((u8 *)&pcur_network->SupportedRates); network_type = rtw_check_network_type((u8 *)&pcur_network->SupportedRates, supportRateNum, pcur_network->Configuration.DSConfig); if (IsSupportedTxCCK(network_type)) @@ -711,21 +919,52 @@ void update_bmc_sta(_adapter *padapter) update_sta_basic_rate(psta, network_type); psta->wireless_mode = network_type; - rtw_hal_update_sta_rate_mask(padapter, psta); - - psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + rtw_hal_update_sta_ra_info(padapter, psta); _enter_critical_bh(&psta->lock, &irqL); psta->state = _FW_LINKED; _exit_critical_bh(&psta->lock, &irqL); rtw_sta_media_status_rpt(padapter, psta, 1); - rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); + rtw_init_bmc_sta_tx_rate(padapter, psta); + } else RTW_INFO("add_RATid_bmc_sta error!\n"); } +#if defined(CONFIG_80211N_HT) && defined(CONFIG_BEAMFORMING) +void update_sta_info_apmode_ht_bf_cap(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; + struct ht_priv *phtpriv_sta = &psta->htpriv; + + u8 cur_beamform_cap = 0; + + /*Config Tx beamforming setting*/ + if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP((u8 *)(&phtpriv_sta->ht_cap))) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + /*Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 6); + } + + if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP((u8 *)(&phtpriv_sta->ht_cap))) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + /*Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 4); + } + if (cur_beamform_cap) + RTW_INFO("Client STA(%d) HT Beamforming Cap = 0x%02X\n", psta->cmn.aid, cur_beamform_cap); + + phtpriv_sta->beamform_cap = cur_beamform_cap; + psta->cmn.bf_info.ht_beamform_cap = cur_beamform_cap; + +} +#endif /*CONFIG_80211N_HT && CONFIG_BEAMFORMING*/ + /* notes: * AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode */ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) @@ -738,7 +977,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; struct ht_priv *phtpriv_sta = &psta->htpriv; #endif /* CONFIG_80211N_HT */ - u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0; /* set intf_tag to if1 */ /* psta->intf_tag = 0; */ @@ -746,10 +985,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) /*alloc macid when call rtw_alloc_stainfo(),release macid when call rtw_free_stainfo()*/ - /* ap mode */ - rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); - - if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) + if (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) psta->ieee8021x_blocked = _TRUE; else psta->ieee8021x_blocked = _FALSE; @@ -769,15 +1005,19 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) /* bwmode */ if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) - psta->bw_mode = CHANNEL_WIDTH_40; + psta->cmn.bw_mode = CHANNEL_WIDTH_40; else - psta->bw_mode = CHANNEL_WIDTH_20; + psta->cmn.bw_mode = CHANNEL_WIDTH_20; + + if (phtpriv_sta->op_present + && !GET_HT_OP_ELE_STA_CHL_WIDTH(phtpriv_sta->ht_op)) + psta->cmn.bw_mode = CHANNEL_WIDTH_20; if (psta->ht_40mhz_intolerant) - psta->bw_mode = CHANNEL_WIDTH_20; + psta->cmn.bw_mode = CHANNEL_WIDTH_20; - if (pmlmeext->cur_bwmode < psta->bw_mode) - psta->bw_mode = pmlmeext->cur_bwmode; + if (pmlmeext->cur_bwmode < psta->cmn.bw_mode) + psta->cmn.bw_mode = pmlmeext->cur_bwmode; phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; @@ -788,7 +1028,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) /* check if sta support s Short GI 40M */ if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) { - if (psta->bw_mode == CHANNEL_WIDTH_40) /* according to psta->bw_mode */ + if (psta->cmn.bw_mode == CHANNEL_WIDTH_40) /* according to psta->bw_mode */ phtpriv_sta->sgi_40m = _TRUE; else phtpriv_sta->sgi_40m = _FALSE; @@ -800,52 +1040,36 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) if (TEST_FLAG(phtpriv_ap->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP((u8 *)(&phtpriv_sta->ht_cap))) { SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX)); - RTW_INFO("Enable HT Tx LDPC for STA(%d)\n", psta->aid); + RTW_INFO("Enable HT Tx LDPC for STA(%d)\n", psta->cmn.aid); } /* B7 B8 B9 Config STBC setting */ if (TEST_FLAG(phtpriv_ap->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC((u8 *)(&phtpriv_sta->ht_cap))) { SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX)); - RTW_INFO("Enable HT Tx STBC for STA(%d)\n", psta->aid); + RTW_INFO("Enable HT Tx STBC for STA(%d)\n", psta->cmn.aid); } -#ifdef CONFIG_BEAMFORMING - /*Config Tx beamforming setting*/ - if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && - GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP((u8 *)(&phtpriv_sta->ht_cap))) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); - /*Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ - SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 6); - } - - if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && - GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP((u8 *)(&phtpriv_sta->ht_cap))) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); - /*Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ - SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 4); - } - if (cur_beamform_cap) - RTW_INFO("Client STA(%d) HT Beamforming Cap = 0x%02X\n", psta->aid, cur_beamform_cap); -#endif /*CONFIG_BEAMFORMING*/ + #ifdef CONFIG_BEAMFORMING + update_sta_info_apmode_ht_bf_cap(padapter, psta); + #endif } else { phtpriv_sta->ampdu_enable = _FALSE; phtpriv_sta->sgi_20m = _FALSE; phtpriv_sta->sgi_40m = _FALSE; - psta->bw_mode = CHANNEL_WIDTH_20; + psta->cmn.bw_mode = CHANNEL_WIDTH_20; phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; } phtpriv_sta->ldpc_cap = cur_ldpc_cap; phtpriv_sta->stbc_cap = cur_stbc_cap; - phtpriv_sta->beamform_cap = cur_beamform_cap; /* Rx AMPDU */ - send_delba(padapter, 0, psta->hwaddr);/* recipient */ + send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */ /* TX AMPDU */ - send_delba(padapter, 1, psta->hwaddr);/* */ /* originator */ + send_delba(padapter, 1, psta->cmn.mac_addr);/* */ /* originator */ phtpriv_sta->agg_enable_bitmap = 0x0;/* reset */ phtpriv_sta->candidate_tid_bitmap = 0x0;/* reset */ #endif /* CONFIG_80211N_HT */ @@ -853,7 +1077,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) #ifdef CONFIG_80211AC_VHT update_sta_vht_info_apmode(padapter, psta); #endif - + psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta)); update_ldpc_stbc_cap(psta); /* todo: init other variables */ @@ -864,6 +1088,8 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) /* add ratid */ /* add_RATid(padapter, psta); */ /* move to ap_sta_info_defer_update() */ + /* ap mode */ + rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); _enter_critical_bh(&psta->lock, &irqL); psta->state |= _FW_LINKED; @@ -908,7 +1134,7 @@ static void update_ap_info(_adapter *padapter, struct sta_info *psta) phtpriv_ap->sgi_40m = _FALSE; } - psta->bw_mode = pmlmeext->cur_bwmode; + psta->cmn.bw_mode = pmlmeext->cur_bwmode; phtpriv_ap->ch_offset = pmlmeext->cur_ch_offset; phtpriv_ap->agg_enable_bitmap = 0x0;/* reset */ @@ -1141,13 +1367,13 @@ static void rtw_ap_check_scan(_adapter *padapter) } _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); -#ifdef CONFIG_AUTO_CHNL_SEL_NHM +#ifdef CONFIG_RTW_ACS if (padapter->registrypriv.acs_auto_scan) { do_scan = _TRUE; reason |= RTW_AUTO_SCAN_REASON_ACS; - rtw_acs_start(padapter, _TRUE); + rtw_acs_start(padapter); } -#endif +#endif/*CONFIG_RTW_ACS*/ if (_TRUE == do_scan) { RTW_INFO("%s : drv scans by itself and wait_completed\n", __func__); @@ -1155,10 +1381,11 @@ static void rtw_ap_check_scan(_adapter *padapter) rtw_scan_wait_completed(padapter); } -#ifdef CONFIG_AUTO_CHNL_SEL_NHM +#ifdef CONFIG_RTW_ACS if (padapter->registrypriv.acs_auto_scan) - rtw_acs_start(padapter, _FALSE); + rtw_acs_stop(padapter); #endif + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); phead = get_list_head(queue); @@ -1244,7 +1471,7 @@ void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter) void start_bss_network(_adapter *padapter, struct createbss_parm *parm) { #define DUMP_ADAPTERS_STATUS 0 - + u8 self_action = MLME_ACTION_UNKNOWN; u8 val8; u16 bcn_interval; u32 acparm; @@ -1256,13 +1483,20 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network); struct dvobj_priv *pdvobj = padapter->dvobj; - s16 req_ch = -1, req_bw = -1, req_offset = -1; + s16 req_ch = REQ_CH_NONE, req_bw = REQ_BW_NONE, req_offset = REQ_OFFSET_NONE; bool ch_setting_changed = _FALSE; u8 ch_to_set = 0, bw_to_set, offset_to_set; u8 doiqk = _FALSE; /* use for check ch bw offset can be allowed or not */ u8 chbw_allow = _TRUE; + if (MLME_IS_AP(padapter)) + self_action = MLME_AP_STARTED; + else if (MLME_IS_MESH(padapter)) + self_action = MLME_MESH_STARTED; + else + rtw_warn_on(1); + if (parm->req_ch != 0) { /* bypass other setting, go checking ch, bw, offset */ req_ch = parm->req_ch; @@ -1272,6 +1506,7 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) } else { /* inform this request comes from upper layer */ req_ch = 0; + _rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length); } bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod; @@ -1307,7 +1542,9 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) if (pmlmepriv->cur_network.join_res != _TRUE) { /* setting only at first time */ /* WEP Key will be set before this function, do not clear CAM. */ - if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)) + if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_) + && !MLME_IS_MESH(padapter) /* mesh group key is set before this function */ + ) flush_all_cam_entry(padapter); /* clear CAM */ } @@ -1343,14 +1580,15 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) ch_setting_changed = rtw_ap_chbw_decision(padapter, req_ch, req_bw, req_offset , &ch_to_set, &bw_to_set, &offset_to_set, &chbw_allow); - /* let pnetwork_mlmeext == pnetwork_mlme. */ - _rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length); + /* let pnetwork_mlme == pnetwork_mlmeext */ + _rtw_memcpy(pnetwork, pnetwork_mlmeext, pnetwork_mlmeext->Length); rtw_start_bss_hdl_after_chbw_decided(padapter); #if defined(CONFIG_DFS_MASTER) - rtw_dfs_master_status_apply(padapter, MLME_AP_STARTED); + rtw_dfs_master_status_apply(padapter, self_action); #endif + rtw_hal_rcr_set_chk_bssid(padapter, self_action); #ifdef CONFIG_MCC_MODE if (MCC_EN(padapter)) { @@ -1372,8 +1610,10 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) rtw_hal_mcc_issue_null_data(padapter, chbw_allow, 1); #endif /* CONFIG_MCC_MODE */ - doiqk = _TRUE; - rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + if (!IS_CH_WAITING(adapter_to_rfctl(padapter))) { + doiqk = _TRUE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + } if (ch_to_set != 0) { set_channel_bwmode(padapter, ch_to_set, offset_to_set, bw_to_set); @@ -1388,6 +1628,16 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) rtw_hal_set_mcc_setting_start_bss_network(padapter, chbw_allow); #endif + if (ch_setting_changed == _TRUE + && (MLME_IS_GO(padapter) || MLME_IS_MESH(padapter)) /* pure AP is not needed*/ + ) { + #if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + rtw_cfg80211_ch_switch_notify(padapter + , pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset + , pmlmepriv->htpriv.ht_option); + #endif + } + if (DUMP_ADAPTERS_STATUS) { RTW_INFO(FUNC_ADPT_FMT" done\n", FUNC_ADPT_ARG(padapter)); dump_adapters_status(RTW_DBGDUMP , adapter_to_dvobj(padapter)); @@ -1463,11 +1713,13 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) u16 cap, ht_cap = _FALSE; uint ie_len = 0; int group_cipher, pairwise_cipher; + u8 mfp_opt = MFP_NO; u8 channel, network_type, supportRate[NDIS_802_11_LENGTH_RATES_EX]; int supportRateNum = 0; u8 OUI1[] = {0x00, 0x50, 0xf2, 0x01}; u8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; u8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; + HT_CAP_AMPDU_DENSITY best_ampdu_density; struct registry_priv *pregistrypriv = &padapter->registrypriv; struct security_priv *psecuritypriv = &padapter->securitypriv; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -1493,7 +1745,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) RTW_INFO("%s, len=%d\n", __FUNCTION__, len); - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) return _FAIL; @@ -1507,8 +1759,12 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) _rtw_memcpy(ie, pbuf, pbss_network->IELength); - if (pbss_network->InfrastructureMode != Ndis802_11APMode) + if (pbss_network->InfrastructureMode != Ndis802_11APMode + && pbss_network->InfrastructureMode != Ndis802_11_mesh + ) { + rtw_warn_on(1); return _FAIL; + } rtw_ap_check_scan(padapter); @@ -1540,6 +1796,18 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) #endif } +#ifdef CONFIG_RTW_MESH + /* Mesh ID */ + if (MLME_IS_MESH(padapter)) { + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, WLAN_EID_MESH_ID, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) { + _rtw_memset(&pbss_network->mesh_id, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(pbss_network->mesh_id.Ssid, (p + 2), ie_len); + pbss_network->mesh_id.SsidLength = ie_len; + } + } +#endif + /* chnnel */ channel = 0; pbss_network->Configuration.Length = 0; @@ -1591,7 +1859,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_; p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); if (p && ie_len > 0) { - if (rtw_parse_wpa2_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + if (rtw_parse_wpa2_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) { psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; psecuritypriv->dot8021xalg = 1;/* psk, todo:802.1x */ @@ -1707,9 +1975,26 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) } +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* MFP is mandatory for secure mesh */ + if (padapter->mesh_info.mesh_auth_id) + mfp_opt = MFP_REQUIRED; + } else +#endif + if (mfp_opt == MFP_INVALID) { + RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter)); + return _FAIL; + } + psecuritypriv->mfp_opt = mfp_opt; + /* wmm */ ie_len = 0; pmlmepriv->qospriv.qos_option = 0; +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + pmlmepriv->qospriv.qos_option = 1; +#endif if (pregistrypriv->wmm_enable) { for (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) { p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); @@ -1771,9 +2056,10 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) pht_cap->ampdu_params_info &= ~(IEEE80211_HT_CAP_AMPDU_FACTOR | IEEE80211_HT_CAP_AMPDU_DENSITY); if ((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) || - (psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) - pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (0x07 << 2)); - else + (psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) { + rtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density); + pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2)); + } else pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00); rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); @@ -1849,9 +2135,17 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) /* parsing HT_INFO_IE */ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); - if (p && ie_len > 0) + if (p && ie_len > 0) { pHT_info_ie = p; + if (channel == 0) + pbss_network->Configuration.DSConfig = GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2); + else if (channel != GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2)) { + RTW_INFO(FUNC_ADPT_FMT" ch inconsistent, DSSS:%u, HT primary:%u\n" + , FUNC_ADPT_ARG(padapter), channel, GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2)); + } + } #endif /* CONFIG_80211N_HT */ + switch (network_type) { case WIRELESS_11B: pbss_network->NetworkTypeInUse = Ndis802_11DS; @@ -1900,45 +2194,32 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); if (p && ie_len > 0) vht_cap = _TRUE; - /* Parsing VHT OPERATION IE */ + /* Parsing VHT OPERATION IE */ + pmlmepriv->ori_vht_en = 0; pmlmepriv->vhtpriv.vht_option = _FALSE; /* if channel in 5G band, then add vht ie . */ if ((pbss_network->Configuration.DSConfig > 14) - && (pmlmepriv->htpriv.ht_option == _TRUE) - && REGSTY_IS_11AC_ENABLE(pregistrypriv) - && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) - ) { - if (vht_cap == _TRUE) - pmlmepriv->vhtpriv.vht_option = _TRUE; - else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) { - u8 cap_len, operation_len; - - rtw_vht_use_default_setting(padapter); - - { - /* VHT Operation mode notifiy bit in Extended IE (127) */ - uint len = 0; - - SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1); - pmlmepriv->ext_capab_ie_len = 10; - rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len); - pbss_network->IELength += pmlmepriv->ext_capab_ie_len; - } - - /* VHT Capabilities element */ - cap_len = rtw_build_vht_cap_ie(padapter, pbss_network->IEs + pbss_network->IELength); - pbss_network->IELength += cap_len; - - /* VHT Operation element */ - operation_len = rtw_build_vht_operation_ie(padapter, pbss_network->IEs + pbss_network->IELength, pbss_network->Configuration.DSConfig); - pbss_network->IELength += operation_len; - + && (pmlmepriv->htpriv.ht_option == _TRUE) + && REGSTY_IS_11AC_ENABLE(pregistrypriv) + && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) + ) { + if (vht_cap == _TRUE + && MLME_IS_MESH(padapter) /* allow only mesh temporarily before VHT IE checking is ready */ + ) { + rtw_check_for_vht20(padapter, ie + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_); + pmlmepriv->ori_vht_en = 1; pmlmepriv->vhtpriv.vht_option = _TRUE; + } else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) { + rtw_vht_ies_detach(padapter, pbss_network); + rtw_vht_ies_attach(padapter, pbss_network); } } + + if (pmlmepriv->vhtpriv.vht_option == _FALSE) + rtw_vht_ies_detach(padapter, pbss_network); #endif /* CONFIG_80211AC_VHT */ if(pbss_network->Configuration.DSConfig <= 14 && padapter->registrypriv.wifi_spec == 1) { @@ -1953,7 +2234,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network); rtw_ies_get_chbw(pbss_network->IEs + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_ - , &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset); + , &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset, 1, 1); rtw_warn_on(pmlmepriv->ori_ch == 0); { @@ -1989,14 +2270,24 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) } #if CONFIG_RTW_MACADDR_ACL -void rtw_macaddr_acl_init(_adapter *adapter) +void rtw_macaddr_acl_init(_adapter *adapter, u8 period) { struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; - _queue *acl_node_q = &acl->acl_node_q; + struct wlan_acl_pool *acl; + _queue *acl_node_q; int i; _irqL irqL; + if (period >= RTW_ACL_PERIOD_NUM) { + rtw_warn_on(1); + return; + } + + acl = &stapriv->acl_list[period]; + acl_node_q = &acl->acl_node_q; + + _rtw_spinlock_init(&(acl_node_q->lock)); + _enter_critical_bh(&(acl_node_q->lock), &irqL); _rtw_init_listhead(&(acl_node_q->queue)); acl->num = 0; @@ -2008,15 +2299,23 @@ void rtw_macaddr_acl_init(_adapter *adapter) _exit_critical_bh(&(acl_node_q->lock), &irqL); } -void rtw_macaddr_acl_deinit(_adapter *adapter) +static void _rtw_macaddr_acl_deinit(_adapter *adapter, u8 period, bool clear_only) { struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; - _queue *acl_node_q = &acl->acl_node_q; + struct wlan_acl_pool *acl; + _queue *acl_node_q; _irqL irqL; _list *head, *list; struct rtw_wlan_acl_node *acl_node; + if (period >= RTW_ACL_PERIOD_NUM) { + rtw_warn_on(1); + return; + } + + acl = &stapriv->acl_list[period]; + acl_node_q = &acl->acl_node_q; + _enter_critical_bh(&(acl_node_q->lock), &irqL); head = get_list_head(acl_node_q); list = get_next(head); @@ -2032,24 +2331,42 @@ void rtw_macaddr_acl_deinit(_adapter *adapter) } _exit_critical_bh(&(acl_node_q->lock), &irqL); + if (!clear_only) + _rtw_spinlock_free(&(acl_node_q->lock)); + rtw_warn_on(acl->num); acl->mode = RTW_ACL_MODE_DISABLED; } -void rtw_set_macaddr_acl(_adapter *adapter, int mode) +void rtw_macaddr_acl_deinit(_adapter *adapter, u8 period) +{ + _rtw_macaddr_acl_deinit(adapter, period, 0); +} + +void rtw_macaddr_acl_clear(_adapter *adapter, u8 period) +{ + _rtw_macaddr_acl_deinit(adapter, period, 1); +} + +void rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode) { struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; + struct wlan_acl_pool *acl; + + if (period >= RTW_ACL_PERIOD_NUM) { + rtw_warn_on(1); + return; + } - RTW_INFO(FUNC_ADPT_FMT" mode=%d\n", FUNC_ADPT_ARG(adapter), mode); + acl = &stapriv->acl_list[period]; - acl->mode = mode; + RTW_INFO(FUNC_ADPT_FMT" p=%u, mode=%d\n" + , FUNC_ADPT_ARG(adapter), period, mode); - if (mode == RTW_ACL_MODE_DISABLED) - rtw_macaddr_acl_deinit(adapter); + acl->mode = mode; } -int rtw_acl_add_sta(_adapter *adapter, const u8 *addr) +int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr) { _irqL irqL; _list *list, *head; @@ -2057,8 +2374,17 @@ int rtw_acl_add_sta(_adapter *adapter, const u8 *addr) int i = -1, ret = 0; struct rtw_wlan_acl_node *acl_node; struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; - _queue *acl_node_q = &acl->acl_node_q; + struct wlan_acl_pool *acl; + _queue *acl_node_q; + + if (period >= RTW_ACL_PERIOD_NUM) { + rtw_warn_on(1); + ret = -1; + goto exit; + } + + acl = &stapriv->acl_list[period]; + acl_node_q = &acl->acl_node_q; _enter_critical_bh(&(acl_node_q->lock), &irqL); @@ -2105,26 +2431,34 @@ int rtw_acl_add_sta(_adapter *adapter, const u8 *addr) if (!existed && (i < 0 || i >= NUM_ACL)) ret = -1; - RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" %s (acl_num=%d)\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(addr) + RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n" + , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr) , (existed ? "existed" : ((i < 0 || i >= NUM_ACL) ? "no room" : "added")) , acl->num); - +exit: return ret; } -int rtw_acl_remove_sta(_adapter *adapter, const u8 *addr) +int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr) { _irqL irqL; _list *list, *head; int ret = 0; struct rtw_wlan_acl_node *acl_node; struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; - _queue *acl_node_q = &acl->acl_node_q; + struct wlan_acl_pool *acl; + _queue *acl_node_q; u8 is_baddr = is_broadcast_mac_addr(addr); u8 match = 0; + if (period >= RTW_ACL_PERIOD_NUM) { + rtw_warn_on(1); + goto exit; + } + + acl = &stapriv->acl_list[period]; + acl_node_q = &acl->acl_node_q; + _enter_critical_bh(&(acl_node_q->lock), &irqL); head = get_list_head(acl_node_q); @@ -2146,51 +2480,59 @@ int rtw_acl_remove_sta(_adapter *adapter, const u8 *addr) _exit_critical_bh(&(acl_node_q->lock), &irqL); - RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" %s (acl_num=%d)\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(addr) + RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n" + , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr) , is_baddr ? "clear all" : (match ? "match" : "no found") , acl->num); +exit: return ret; } #endif /* CONFIG_RTW_MACADDR_ACL */ -u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta) +u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk) { - struct cmd_obj *ph2c; - struct set_stakey_parm *psetstakey_para; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_obj *cmd; + struct set_stakey_parm *param; u8 res = _SUCCESS; - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } - psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); - if (psetstakey_para == NULL) { - rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + param = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); + if (param == NULL) { + rtw_mfree((u8 *) cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } - init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); - + init_h2fwcmd_w_parm_no_rsp(cmd, param, _SetStaKey_CMD_); - psetstakey_para->algorithm = (u8)psta->dot118021XPrivacy; + _rtw_memcpy(param->addr, addr, ETH_ALEN); + param->algorithm = alg; + param->keyid = keyid; + _rtw_memcpy(param->key, key, 16); + param->gk = gk; - _rtw_memcpy(psetstakey_para->addr, psta->hwaddr, ETH_ALEN); - - _rtw_memcpy(psetstakey_para->key, &psta->dot118021x_UncstKey, 16); - - - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(cmdpriv, cmd); exit: - return res; +} +u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta) +{ + return rtw_ap_set_sta_key(padapter + , psta->cmn.mac_addr + , psta->dot118021XPrivacy + , psta->dot118021x_UncstKey.skey + , 0 + , 0 + ); } static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set_tx) @@ -2307,7 +2649,7 @@ u8 rtw_ap_bmc_frames_hdl(_adapter *padapter) _enter_critical_bh(&pxmitpriv->lock, &irqL); - if ((pstapriv->tim_bitmap & BIT(0)) && (psta_bmc->sleepq_len > 0)) { + if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) { int tx_counts = 0; _update_beacon(padapter, _TIM_IE_, NULL, _FALSE, "update TIM with TIB=1"); @@ -2352,11 +2694,11 @@ u8 rtw_ap_bmc_frames_hdl(_adapter *padapter) /*RTW_INFO("sleepq_len of bmc_sta = %d\n", psta_bmc->sleepq_len);*/ - if (pstapriv->tim_bitmap & BIT(0)) + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) update_tim = _TRUE; - pstapriv->tim_bitmap &= ~BIT(0); - pstapriv->sta_dz_bitmap &= ~BIT(0); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0); + rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0); if (update_tim == _TRUE) { RTW_INFO("clear TIB\n"); @@ -2389,13 +2731,13 @@ static void associated_stainfo_update(_adapter *padapter, struct sta_info *psta, { struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - RTW_INFO("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->hwaddr), sta_info_type); + RTW_INFO("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->cmn.mac_addr), sta_info_type); if (sta_info_type & STA_INFO_UPDATE_BW) { if ((psta->flags & WLAN_STA_HT) && !psta->ht_20mhz_set) { if (pmlmepriv->sw_to_20mhz) { - psta->bw_mode = CHANNEL_WIDTH_20; + psta->cmn.bw_mode = CHANNEL_WIDTH_20; /*psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;*/ psta->htpriv.sgi_40m = _FALSE; } else { @@ -2450,12 +2792,6 @@ static void update_bcn_ext_capab_ie(_adapter *padapter) } -static void update_bcn_fixed_ie(_adapter *padapter) -{ - RTW_INFO("%s\n", __FUNCTION__); - -} - static void update_bcn_erpinfo_ie(_adapter *padapter) { struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -2691,83 +3027,70 @@ void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *ta { _irqL irqL; struct mlme_priv *pmlmepriv; - struct mlme_ext_priv *pmlmeext; - /* struct mlme_ext_info *pmlmeinfo; */ - - /* RTW_INFO("%s\n", __FUNCTION__); */ + struct mlme_ext_priv *pmlmeext; + bool updated = 1; /* treat as upadated by default */ if (!padapter) return; pmlmepriv = &(padapter->mlmepriv); pmlmeext = &(padapter->mlmeextpriv); - /* pmlmeinfo = &(pmlmeext->mlmext_info); */ - if (_FALSE == pmlmeext->bstart_bss) + if (pmlmeext->bstart_bss == _FALSE) return; _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); switch (ie_id) { - case 0xFF: - - update_bcn_fixed_ie(padapter);/* 8: TimeStamp, 2: Beacon Interval 2:Capability */ - - break; - case _TIM_IE_: - update_BCNTIM(padapter); - break; case _ERPINFO_IE_: - update_bcn_erpinfo_ie(padapter); - break; case _HT_CAPABILITY_IE_: - update_bcn_htcap_ie(padapter); - break; case _RSN_IE_2_: - update_bcn_rsn_ie(padapter); - break; case _HT_ADD_INFO_IE_: - update_bcn_htinfo_ie(padapter); - break; case _EXT_CAP_IE_: - update_bcn_ext_capab_ie(padapter); + break; +#ifdef CONFIG_RTW_MESH + case WLAN_EID_MESH_CONFIG: + updated = rtw_mesh_update_bss_peering_status(padapter, &(pmlmeext->mlmext_info.network)); + updated |= rtw_mesh_update_bss_formation_info(padapter, &(pmlmeext->mlmext_info.network)); + updated |= rtw_mesh_update_bss_forwarding_state(padapter, &(pmlmeext->mlmext_info.network)); break; +#endif case _VENDOR_SPECIFIC_IE_: - update_bcn_vendor_spec_ie(padapter, oui); - break; + case 0xFF: default: break; } - pmlmepriv->update_bcn = _TRUE; + if (updated) + pmlmepriv->update_bcn = _TRUE; _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); #ifndef CONFIG_INTERRUPT_BASED_TXBCN #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - if (tx) { + if (tx && updated) { /* send_beacon(padapter); */ /* send_beacon must execute on TSR level */ if (0) RTW_INFO(FUNC_ADPT_FMT" ie_id:%u - %s\n", FUNC_ADPT_ARG(padapter), ie_id, tag); @@ -2779,7 +3102,6 @@ void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *ta } #endif #endif /* !CONFIG_INTERRUPT_BASED_TXBCN */ - } #ifdef CONFIG_80211N_HT @@ -3016,11 +3338,8 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_no_short_preamble++; if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && - (pmlmepriv->num_sta_no_short_preamble == 1)) { + (pmlmepriv->num_sta_no_short_preamble == 1)) beacon_updated = _TRUE; - update_beacon(padapter, 0xFF, NULL, _TRUE); - } - } } else { if (psta->no_short_preamble_set) { @@ -3029,11 +3348,8 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_no_short_preamble--; if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && - (pmlmepriv->num_sta_no_short_preamble == 0)) { + (pmlmepriv->num_sta_no_short_preamble == 0)) beacon_updated = _TRUE; - update_beacon(padapter, 0xFF, NULL, _TRUE); - } - } } @@ -3054,7 +3370,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) if (pmlmepriv->num_sta_non_erp == 1) { beacon_updated = _TRUE; - update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); + update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE); } } @@ -3066,7 +3382,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) if (pmlmepriv->num_sta_non_erp == 0) { beacon_updated = _TRUE; - update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); + update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE); } } @@ -3091,11 +3407,8 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_no_short_slot_time++; if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && - (pmlmepriv->num_sta_no_short_slot_time == 1)) { + (pmlmepriv->num_sta_no_short_slot_time == 1)) beacon_updated = _TRUE; - update_beacon(padapter, 0xFF, NULL, _TRUE); - } - } } else { if (psta->no_short_slot_time_set) { @@ -3104,20 +3417,17 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_no_short_slot_time--; if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && - (pmlmepriv->num_sta_no_short_slot_time == 0)) { + (pmlmepriv->num_sta_no_short_slot_time == 0)) beacon_updated = _TRUE; - update_beacon(padapter, 0xFF, NULL, _TRUE); - } } } #ifdef CONFIG_80211N_HT - if (psta->flags & WLAN_STA_HT) { u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info); - RTW_INFO("HT: STA " MAC_FMT " HT Capabilities " - "Info: 0x%04x\n", MAC_ARG(psta->hwaddr), ht_capab); + RTW_INFO("HT: STA " MAC_FMT " HT Capabilities Info: 0x%04x\n", + MAC_ARG(psta->cmn.mac_addr), ht_capab); if (psta->no_ht_set) { psta->no_ht_set = 0; @@ -3131,7 +3441,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) } RTW_INFO("%s STA " MAC_FMT " - no " "greenfield, num of non-gf stations %d\n", - __FUNCTION__, MAC_ARG(psta->hwaddr), + __FUNCTION__, MAC_ARG(psta->cmn.mac_addr), pmlmepriv->num_sta_ht_no_gf); } @@ -3142,10 +3452,18 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) } RTW_INFO("%s STA " MAC_FMT " - 20 MHz HT, " "num of 20MHz HT STAs %d\n", - __FUNCTION__, MAC_ARG(psta->hwaddr), + __FUNCTION__, MAC_ARG(psta->cmn.mac_addr), pmlmepriv->num_sta_ht_20mhz); } + if (((ht_capab & RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT) != 0) && + (psta->ht_40mhz_intolerant == 0)) { + psta->ht_40mhz_intolerant = 1; + pmlmepriv->num_sta_40mhz_intolerant++; + RTW_INFO("%s STA " MAC_FMT " - 40MHZ_INTOLERANT, ", + __FUNCTION__, MAC_ARG(psta->cmn.mac_addr)); + } + } else { if (!psta->no_ht_set) { psta->no_ht_set = 1; @@ -3154,19 +3472,32 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) if (pmlmepriv->htpriv.ht_option == _TRUE) { RTW_INFO("%s STA " MAC_FMT " - no HT, num of non-HT stations %d\n", - __FUNCTION__, MAC_ARG(psta->hwaddr), + __FUNCTION__, MAC_ARG(psta->cmn.mac_addr), pmlmepriv->num_sta_no_ht); } } if (rtw_ht_operation_update(padapter) > 0) { update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); - update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); - /*beacon_updated = _TRUE;*/ + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE); + beacon_updated = _TRUE; } - #endif /* CONFIG_80211N_HT */ +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + struct sta_priv *pstapriv = &padapter->stapriv; + + update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE); + if (pstapriv->asoc_list_cnt == 1) + _set_timer(&padapter->mesh_atlm_param_req_timer, 0); + beacon_updated = _TRUE; + } +#endif + + if (beacon_updated) + update_beacon(padapter, 0xFF, NULL, _TRUE); + /* update associcated stations cap. */ associated_clients_update(padapter, beacon_updated, STA_INFO_UPDATE_ALL); @@ -3177,20 +3508,25 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) { u8 beacon_updated = _FALSE; + struct sta_priv *pstapriv = &padapter->stapriv; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); if (!psta) return beacon_updated; + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) { + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); + beacon_updated = _TRUE; + update_beacon(padapter, _TIM_IE_, NULL, _FALSE); + } + if (psta->no_short_preamble_set) { psta->no_short_preamble_set = 0; pmlmepriv->num_sta_no_short_preamble--; if (pmlmeext->cur_wireless_mode > WIRELESS_11B - && pmlmepriv->num_sta_no_short_preamble == 0) { + && pmlmepriv->num_sta_no_short_preamble == 0) beacon_updated = _TRUE; - update_beacon(padapter, 0xFF, NULL, _TRUE); - } } if (psta->nonerp_set) { @@ -3198,7 +3534,7 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_non_erp--; if (pmlmepriv->num_sta_non_erp == 0) { beacon_updated = _TRUE; - update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); + update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE); } } @@ -3206,14 +3542,11 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) psta->no_short_slot_time_set = 0; pmlmepriv->num_sta_no_short_slot_time--; if (pmlmeext->cur_wireless_mode > WIRELESS_11B - && pmlmepriv->num_sta_no_short_slot_time == 0) { + && pmlmepriv->num_sta_no_short_slot_time == 0) beacon_updated = _TRUE; - update_beacon(padapter, 0xFF, NULL, _TRUE); - } } #ifdef CONFIG_80211N_HT - if (psta->no_ht_gf_set) { psta->no_ht_gf_set = 0; pmlmepriv->num_sta_ht_no_gf--; @@ -3229,15 +3562,32 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_ht_20mhz--; } - + if (psta->ht_40mhz_intolerant) { + psta->ht_40mhz_intolerant = 0; + if (pmlmepriv->num_sta_40mhz_intolerant > 0) + pmlmepriv->num_sta_40mhz_intolerant--; + else + rtw_warn_on(1); + } if (rtw_ht_operation_update(padapter) > 0) { update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); - update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE); } - #endif /* CONFIG_80211N_HT */ +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE); + if (pstapriv->asoc_list_cnt == 0) + _cancel_timer_ex(&padapter->mesh_atlm_param_req_timer); + beacon_updated = _TRUE; + } +#endif + + if (beacon_updated == _TRUE) + update_beacon(padapter, 0xFF, NULL, _TRUE); + #if 0 /* update associated stations cap. */ associated_clients_update(padapter, beacon_updated, STA_INFO_UPDATE_ALL); /* move it to avoid deadlock */ @@ -3263,18 +3613,24 @@ u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reaso if (active == _TRUE) { #ifdef CONFIG_80211N_HT /* tear down Rx AMPDU */ - send_delba(padapter, 0, psta->hwaddr);/* recipient */ + send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */ /* tear down TX AMPDU */ - send_delba(padapter, 1, psta->hwaddr);/* */ /* originator */ + send_delba(padapter, 1, psta->cmn.mac_addr);/* */ /* originator */ #endif /* CONFIG_80211N_HT */ - issue_deauth(padapter, psta->hwaddr, reason); + if (!MLME_IS_MESH(padapter)) + issue_deauth(padapter, psta->cmn.mac_addr, reason); } +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_mesh_path_flush_by_nexthop(psta); +#endif + #ifdef CONFIG_BEAMFORMING - beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, psta->hwaddr, ETH_ALEN, 1); + beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, psta->cmn.mac_addr, ETH_ALEN, 1); #endif psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ @@ -3288,22 +3644,21 @@ u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reaso psta->state &= ~_FW_LINKED; _exit_critical_bh(&psta->lock, &irqL); + if (!MLME_IS_MESH(padapter)) { #ifdef CONFIG_IOCTL_CFG80211 - if (1) { -#ifdef COMPAT_KERNEL_RELEASE - rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, reason); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) - rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, reason); -#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */ + #ifdef COMPAT_KERNEL_RELEASE + rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason); + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) + rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason); + #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */ /* will call rtw_cfg80211_indicate_sta_disassoc() in cmd_thread for old API context */ -#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */ - } else -#endif /* CONFIG_IOCTL_CFG80211 */ - { + #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */ +#else rtw_indicate_sta_disassoc_event(padapter, psta); +#endif } - report_del_sta_event(padapter, psta->hwaddr, reason, enqueue, _FALSE); + report_del_sta_event(padapter, psta->cmn.mac_addr, reason, enqueue, _FALSE); beacon_updated = bss_cap_update_on_sta_leave(padapter, psta); @@ -3342,7 +3697,7 @@ int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset) psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); plist = get_next(plist); - issue_action_spct_ch_switch(padapter, psta->hwaddr, new_ch, ch_offset); + issue_action_spct_ch_switch(padapter, psta->cmn.mac_addr, new_ch, ch_offset); psta->expire_to = ((pstapriv->expire_to * 2) > 5) ? 5 : (pstapriv->expire_to * 2); } _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); @@ -3366,7 +3721,7 @@ int rtw_sta_flush(_adapter *padapter, bool enqueue) char flush_list[NUM_STA]; int i; - if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) + if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) return ret; RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev)); @@ -3383,6 +3738,7 @@ int rtw_sta_flush(_adapter *padapter, bool enqueue) rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; + STA_SET_MESH_PLINK(psta, NULL); stainfo_offset = rtw_stainfo_offset(pstapriv, psta); if (stainfo_offset_valid(stainfo_offset)) @@ -3394,11 +3750,20 @@ int rtw_sta_flush(_adapter *padapter, bool enqueue) /* call ap_free_sta() for each sta picked */ for (i = 0; i < flush_num; i++) { + u8 sta_addr[ETH_ALEN]; + psta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]); + _rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN); + ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, enqueue); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_mesh_expire_peer(padapter, sta_addr); + #endif } - issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING); + if (!MLME_IS_MESH(padapter)) + issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING); associated_clients_update(padapter, _TRUE, STA_INFO_UPDATE_ALL); @@ -3454,7 +3819,7 @@ void sta_info_update(_adapter *padapter, struct sta_info *psta) void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta) { if (psta->state & _FW_LINKED) - rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); /* DM_RATR_STA_INIT */ + rtw_hal_update_ra_mask(psta); /* DM_RATR_STA_INIT */ } /* restore hw setting from sw data structures */ void rtw_ap_restore_network(_adapter *padapter) @@ -3471,7 +3836,10 @@ void rtw_ap_restore_network(_adapter *padapter) char chk_alive_list[NUM_STA]; int i; - rtw_setopmode_cmd(padapter, Ndis802_11APMode, _FALSE); + rtw_setopmode_cmd(padapter + , MLME_IS_AP(padapter) ? Ndis802_11APMode : Ndis802_11_mesh + , RTW_CMDF_DIRECTLY + ); set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); @@ -3568,13 +3936,9 @@ void start_ap_mode(_adapter *padapter) psecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID; #endif - for (i = 0 ; i < NUM_STA ; i++) + for (i = 0 ; i < pstapriv->max_aid; i++) pstapriv->sta_aid[i] = NULL; -#if CONFIG_RTW_MACADDR_ACL - rtw_macaddr_acl_init(padapter); -#endif - psta = rtw_get_bcmc_stainfo(padapter); /*_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/ if (psta) @@ -3588,8 +3952,28 @@ void start_ap_mode(_adapter *padapter) } +void rtw_ap_bcmc_sta_flush(_adapter *padapter) +{ +#ifdef CONFIG_CONCURRENT_MODE + int cam_id = -1; + u8 *addr = adapter_mac_addr(padapter); + + cam_id = rtw_iface_bcmc_id_get(padapter); + if (cam_id != INVALID_SEC_MAC_CAM_ID) { + RTW_PRINT("clear group key for "ADPT_FMT" addr:"MAC_FMT", camid:%d\n", + ADPT_ARG(padapter), MAC_ARG(addr), cam_id); + clear_cam_entry(padapter, cam_id); + rtw_camid_free(padapter, cam_id); + rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); /*init default value*/ + } +#else + invalidate_cam_all(padapter); +#endif +} + void stop_ap_mode(_adapter *padapter) { + u8 self_action = MLME_ACTION_UNKNOWN; _irqL irqL; struct sta_info *psta = NULL; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -3598,6 +3982,13 @@ void stop_ap_mode(_adapter *padapter) RTW_INFO("%s -"ADPT_FMT"\n", __func__, ADPT_ARG(padapter)); + if (MLME_IS_AP(padapter)) + self_action = MLME_AP_STOPPED; + else if (MLME_IS_MESH(padapter)) + self_action = MLME_MESH_STOPPED; + else + rtw_warn_on(1); + pmlmepriv->update_bcn = _FALSE; /*pmlmeext->bstart_bss = _FALSE;*/ padapter->netif_up = _FALSE; @@ -3609,25 +4000,29 @@ void stop_ap_mode(_adapter *padapter) padapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled; #ifdef CONFIG_DFS_MASTER - rtw_dfs_master_status_apply(padapter, MLME_AP_STOPPED); + rtw_dfs_master_status_apply(padapter, self_action); #endif /* free scan queue */ rtw_free_network_queue(padapter, _TRUE); #if CONFIG_RTW_MACADDR_ACL - rtw_macaddr_acl_deinit(padapter); + rtw_macaddr_acl_clear(padapter, RTW_ACL_PERIOD_BSS); #endif rtw_sta_flush(padapter, _TRUE); + rtw_ap_bcmc_sta_flush(padapter); /* free_assoc_sta_resources */ rtw_free_all_stainfo(padapter); psta = rtw_get_bcmc_stainfo(padapter); - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - rtw_free_stainfo(padapter, psta); - /*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/ + if (psta) { + rtw_sta_mstatus_disc_rpt(padapter, psta->cmn.mac_id); + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + rtw_free_stainfo(padapter, psta); + /*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/ + } rtw_free_mlme_priv_ie_data(pmlmepriv); @@ -3652,6 +4047,8 @@ void stop_ap_mode(_adapter *padapter) pmlmeext->bstart_bss = _FALSE; + rtw_hal_rcr_set_chk_bssid(padapter, self_action); + #ifdef CONFIG_BT_COEXIST rtw_btcoex_MediaStatusNotify(padapter, 0); /* disconnect */ #endif @@ -3664,10 +4061,32 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, { #define UPDATE_VHT_CAP 1 #define UPDATE_HT_CAP 1 - #ifdef CONFIG_80211AC_VHT + struct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv; +#endif { - struct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv; + u8 *p; + int ie_len; + u8 old_ch = bss->Configuration.DSConfig; + bool change_band = _FALSE; + + if ((ch <= 14 && old_ch >= 36) || (ch >= 36 && old_ch <= 14)) + change_band = _TRUE; + + /* update channel in IE */ + p = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); + if (p && ie_len > 0) + *(p + 2) = ch; + + bss->Configuration.DSConfig = ch; + + /* band is changed, update ERP, support rate, ext support rate IE */ + if (change_band == _TRUE) + change_band_update_ie(adapter, bss, ch); + } + +#ifdef CONFIG_80211AC_VHT + if (vhtpriv->vht_option == _TRUE) { u8 *vht_cap_ie, *vht_op_ie; int vht_cap_ielen, vht_op_ielen; u8 center_freq; @@ -3760,45 +4179,28 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, } } #endif /* CONFIG_80211N_HT */ - - { - u8 *p; - int ie_len; - u8 old_ch = bss->Configuration.DSConfig; - bool change_band = _FALSE; - - if ((ch <= 14 && old_ch >= 36) || (ch >= 36 && old_ch <= 14)) - change_band = _TRUE; - - /* update channel in IE */ - p = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); - if (p && ie_len > 0) - *(p + 2) = ch; - - bss->Configuration.DSConfig = ch; - - /* band is changed, update ERP, support rate, ext support rate IE */ - if (change_band == _TRUE) - change_band_update_ie(adapter, bss, ch); - } - } +/* +* return _TRUE if ch setting differs from mlmeext.network +*/ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offset , u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow) { + RT_CHANNEL_INFO *chset = adapter_to_chset(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + bool ch_avail = _FALSE; u8 cur_ie_ch, cur_ie_bw, cur_ie_offset; u8 dec_ch, dec_bw, dec_offset; u8 u_ch = 0, u_offset, u_bw; bool changed = _FALSE; struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); - WLAN_BSSID_EX *network = &(adapter->mlmepriv.cur_network.network); + WLAN_BSSID_EX *network = &(mlmeext->mlmext_info.network); struct mi_state mstate; bool set_u_ch = _FALSE, set_dec_ch = _FALSE; - rtw_ies_get_chbw(network->IEs + sizeof(NDIS_802_11_FIXED_IEs) - , network->IELength - sizeof(NDIS_802_11_FIXED_IEs) - , &cur_ie_ch, &cur_ie_bw, &cur_ie_offset); + rtw_ies_get_chbw(BSS_EX_TLV_IES(network), BSS_EX_TLV_IES_LEN(network) + , &cur_ie_ch, &cur_ie_bw, &cur_ie_offset, 1, 1); #ifdef CONFIG_MCC_MODE if (MCC_EN(adapter)) { @@ -3826,17 +4228,25 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse } #endif /* CONFIG_MCC_MODE */ - /* use chbw of cur_ie updated with specifying req as temporary decision */ - dec_ch = (req_ch <= 0) ? cur_ie_ch : req_ch; - dec_bw = (req_bw < 0) ? cur_ie_bw : req_bw; - dec_offset = (req_offset < 0) ? cur_ie_offset : req_offset; + if (req_ch == 0) { + /* request comes from upper layer, use cur_ie values */ + dec_ch = cur_ie_ch; + dec_bw = cur_ie_bw; + dec_offset = cur_ie_offset; + } else { + /* use chbw of cur_ie updated with specifying req as temporary decision */ + dec_ch = (req_ch <= REQ_CH_NONE) ? cur_ie_ch : req_ch; + dec_bw = (req_bw <= REQ_BW_NONE) ? cur_ie_bw : req_bw; + dec_offset = (req_offset <= REQ_OFFSET_NONE) ? cur_ie_offset : req_offset; + } rtw_mi_status_no_self(adapter, &mstate); - RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num%u, ap_num:%u\n" - , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate), MSTATE_AP_NUM(&mstate)); + RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num%u, ap_num:%u, mesh_num:%u\n" + , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate) + , MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate)); - if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_AP_NUM(&mstate)) { - /* has linked STA or AP mode, follow */ + if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate)) { + /* has linked STA or AP/Mesh mode */ rtw_warn_on(!rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset)); @@ -3844,12 +4254,13 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse RTW_INFO(FUNC_ADPT_FMT" req: %d,%d,%d\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset); rtw_adjust_chbw(adapter, u_ch, &dec_bw, &dec_offset); + #ifdef CONFIG_MCC_MODE if (MCC_EN(adapter)) { if (!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch, dec_bw, dec_offset)) { - mlmeext->cur_channel = *ch = dec_ch; - mlmeext->cur_bwmode = *bw = dec_bw; - mlmeext->cur_ch_offset = *offset = dec_offset; + mlmeext->cur_channel = *ch = dec_ch = cur_ie_ch; + mlmeext->cur_bwmode = *bw = dec_bw = cur_ie_bw; + mlmeext->cur_ch_offset = *offset = dec_offset = cur_ie_offset; /* channel bw offset can not be allowed, need MCC */ *chbw_allow = _FALSE; RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(adapter) @@ -3860,11 +4271,11 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse *chbw_allow = _TRUE; } #endif /* CONFIG_MCC_MODE */ - rtw_sync_chbw(&dec_ch, &dec_bw, &dec_offset - , &u_ch, &u_bw, &u_offset); - rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) - , dec_ch, dec_bw, dec_offset); + /* follow */ + rtw_chset_sync_chbw(chset + , &dec_ch, &dec_bw, &dec_offset + , &u_ch, &u_bw, &u_offset); set_u_ch = _TRUE; } else if (MSTATE_STA_LG_NUM(&mstate)) { @@ -3879,11 +4290,9 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse if (rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch, dec_bw, dec_offset)) { - rtw_sync_chbw(&dec_ch, &dec_bw, &dec_offset - , &u_ch, &u_bw, &u_offset); - - rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) - , dec_ch, dec_bw, dec_offset); + rtw_chset_sync_chbw(chset + , &dec_ch, &dec_bw, &dec_offset + , &u_ch, &u_bw, &u_offset); set_u_ch = _TRUE; @@ -3903,35 +4312,47 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse goto exit; } #endif /* CONFIG_MCC_MODE */ + /* set this for possible ch change when join down*/ set_fwstate(&adapter->mlmepriv, WIFI_OP_CH_SWITCHING); } } else { - /* single AP mode */ + /* single AP/Mesh mode */ RTW_INFO(FUNC_ADPT_FMT" req: %d,%d,%d\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset); + if (req_ch <= REQ_CH_NONE) /* channel is not specified */ + goto choose_chbw; + + if (rtw_chset_search_ch(chset, dec_ch) < 0) { + RTW_WARN(FUNC_ADPT_FMT" ch:%u doesn't fit in chplan\n", FUNC_ADPT_ARG(adapter), req_ch); + *chbw_allow = _FALSE; + goto exit; + } + /* check temporary decision first */ rtw_adjust_chbw(adapter, dec_ch, &dec_bw, &dec_offset); - if (!rtw_get_offset_by_chbw(dec_ch, dec_bw, &dec_offset)) { - if (req_ch == -1 || req_bw == -1) - goto choose_chbw; + if (!rtw_get_offset_by_chbw(dec_ch, dec_bw, &dec_offset) + && req_bw > REQ_BW_NONE + ) { RTW_WARN(FUNC_ADPT_FMT" req: %u,%u has no valid offset\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw); *chbw_allow = _FALSE; goto exit; } - if (!rtw_chset_is_chbw_valid(adapter_to_chset(adapter), dec_ch, dec_bw, dec_offset)) { - if (req_ch == -1 || req_bw == -1) - goto choose_chbw; - RTW_WARN(FUNC_ADPT_FMT" req: %u,%u,%u doesn't fit in chplan\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw, dec_offset); - *chbw_allow = _FALSE; - goto exit; + while (!rtw_chset_is_chbw_valid(chset, dec_ch, dec_bw, dec_offset) + || (rtw_odm_dfs_domain_unknown(adapter) && rtw_is_dfs_chbw(dec_ch, dec_bw, dec_offset)) + || rtw_chset_is_ch_non_ocp(chset, dec_ch, dec_bw, dec_offset) + ) { + dec_bw--; + if (dec_bw == CHANNEL_WIDTH_20) { + dec_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } } if (rtw_odm_dfs_domain_unknown(adapter) && rtw_is_dfs_chbw(dec_ch, dec_bw, dec_offset)) { - if (req_ch >= 0) - RTW_WARN(FUNC_ADPT_FMT" DFS channel %u,%u,%u can't be used\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw, dec_offset); + RTW_WARN(FUNC_ADPT_FMT" DFS channel %u can't be used\n", FUNC_ADPT_ARG(adapter), dec_ch); if (req_ch > 0) { /* specific channel and not from IE => don't change channel setting */ *chbw_allow = _FALSE; @@ -3940,39 +4361,65 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse goto choose_chbw; } - if (rtw_chset_is_ch_non_ocp(adapter_to_chset(adapter), dec_ch, dec_bw, dec_offset) == _FALSE) + if (rtw_chset_is_ch_non_ocp(chset, dec_ch, dec_bw, dec_offset) == _FALSE) goto update_bss_chbw; + RTW_WARN(FUNC_ADPT_FMT" DFS channel %u under non ocp\n", FUNC_ADPT_ARG(adapter), dec_ch); choose_chbw: - if (req_bw < 0) + req_ch = req_ch >= 0 ? dec_ch : 0; + if (req_bw <= REQ_BW_NONE) req_bw = cur_ie_bw; #if defined(CONFIG_DFS_MASTER) if (!rtw_odm_dfs_domain_unknown(adapter)) { - /* choose 5G DFS channel for debug */ - if (adapter_to_rfctl(adapter)->dbg_dfs_master_choose_dfs_ch_first - && rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_2G | RTW_CHF_NON_DFS) == _TRUE) - RTW_INFO(FUNC_ADPT_FMT" choose 5G DFS channel for debug\n", FUNC_ADPT_ARG(adapter)); - else if (adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags - && rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags) == _TRUE) - RTW_INFO(FUNC_ADPT_FMT" choose with dfs_ch_sel_d_flags:0x%02x for debug\n", FUNC_ADPT_ARG(adapter), adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags); - else if (rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, 0) == _FALSE) { + if (rfctl->dbg_dfs_master_choose_dfs_ch_first) { + ch_avail = rtw_choose_shortest_waiting_ch(adapter, req_ch, req_bw + , &dec_ch, &dec_bw, &dec_offset + , RTW_CHF_2G | RTW_CHF_NON_DFS, mlmeext->cur_channel + , rfctl->ch_sel_same_band_prefer); + if (ch_avail == _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" choose 5G DFS channel for debug\n", FUNC_ADPT_ARG(adapter)); + goto update_bss_chbw; + } + } + + if (rfctl->dfs_ch_sel_d_flags) { + ch_avail = rtw_choose_shortest_waiting_ch(adapter, req_ch, req_bw + , &dec_ch, &dec_bw, &dec_offset + , rfctl->dfs_ch_sel_d_flags, mlmeext->cur_channel + , rfctl->ch_sel_same_band_prefer); + if (ch_avail == _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" choose with dfs_ch_sel_d_flags:0x%02x for debug\n" + , FUNC_ADPT_ARG(adapter), rfctl->dfs_ch_sel_d_flags); + goto update_bss_chbw; + } + } + + ch_avail = rtw_choose_shortest_waiting_ch(adapter, req_ch, req_bw + , &dec_ch, &dec_bw, &dec_offset + , 0, mlmeext->cur_channel + , rfctl->ch_sel_same_band_prefer); + if (ch_avail == _FALSE) { RTW_WARN(FUNC_ADPT_FMT" no available channel\n", FUNC_ADPT_ARG(adapter)); *chbw_allow = _FALSE; goto exit; } + } else #endif /* defined(CONFIG_DFS_MASTER) */ - if (rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_DFS) == _FALSE) { - RTW_WARN(FUNC_ADPT_FMT" no available channel\n", FUNC_ADPT_ARG(adapter)); - *chbw_allow = _FALSE; - goto exit; + { + ch_avail = rtw_choose_shortest_waiting_ch(adapter, req_ch, req_bw + , &dec_ch, &dec_bw, &dec_offset + , RTW_CHF_DFS, MLME_IS_ASOC(adapter) ? mlmeext->cur_channel : cur_ie_ch + , rfctl->ch_sel_same_band_prefer); + if (ch_avail == _FALSE) { + RTW_WARN(FUNC_ADPT_FMT" no available channel\n", FUNC_ADPT_ARG(adapter)); + *chbw_allow = _FALSE; + goto exit; + } } update_bss_chbw: - rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) - , dec_ch, dec_bw, dec_offset); - /* channel bw offset can be allowed for single AP, not need MCC */ *chbw_allow = _TRUE; set_dec_ch = _TRUE; @@ -3983,24 +4430,34 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse set_u_ch = set_dec_ch = _FALSE; } - if (mlmeext->cur_channel != dec_ch - || mlmeext->cur_bwmode != dec_bw - || mlmeext->cur_ch_offset != dec_offset) + /* ch setting differs from mlmeext.network IE */ + if (cur_ie_ch != dec_ch + || cur_ie_bw != dec_bw + || cur_ie_offset != dec_offset) changed = _TRUE; - if (changed == _TRUE && rtw_linked_check(adapter) == _TRUE) { -#ifdef CONFIG_SPCT_CH_SWITCH - if (1) - rtw_ap_inform_ch_switch(adapter, dec_ch, dec_offset); - else -#endif - rtw_sta_flush(adapter, _FALSE); + /* ch setting differs from existing one */ + if (check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) + && (mlmeext->cur_channel != dec_ch + || mlmeext->cur_bwmode != dec_bw + || mlmeext->cur_ch_offset != dec_offset) + ) { + if (rtw_linked_check(adapter) == _TRUE) { + #ifdef CONFIG_SPCT_CH_SWITCH + if (1) + rtw_ap_inform_ch_switch(adapter, dec_ch, dec_offset); + else + #endif + rtw_sta_flush(adapter, _FALSE); + } } mlmeext->cur_channel = dec_ch; mlmeext->cur_bwmode = dec_bw; mlmeext->cur_ch_offset = dec_offset; + rtw_ap_update_bss_chbw(adapter, network, dec_ch, dec_bw, dec_offset); + if (u_ch != 0) RTW_INFO(FUNC_ADPT_FMT" union: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); @@ -4019,8 +4476,38 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse return changed; } -/*#define DBG_SWTIMER_BASED_TXBCN*/ +u8 rtw_ap_sta_linking_state_check(_adapter *adapter) +{ + struct sta_info *psta; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct sta_priv *pstapriv = &adapter->stapriv; + int i; + _list *plist, *phead; + _irqL irqL; + u8 rst = _FALSE; + if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter)) + return _FALSE; + + if (pstapriv->auth_list_cnt !=0) + return _TRUE; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + if (!(psta->state &_FW_LINKED)) { + rst = _TRUE; + break; + } + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + return rst; +} + +/*#define DBG_SWTIMER_BASED_TXBCN*/ #ifdef CONFIG_SWTIMER_BASED_TXBCN void tx_beacon_handlder(struct dvobj_priv *pdvobj) { @@ -4032,6 +4519,7 @@ void tx_beacon_handlder(struct dvobj_priv *pdvobj) u64 time; u32 cur_tick, time_offset; /* unit : usec */ u32 inter_bcn_space_us; /* unit : usec */ + u32 txbcn_timer_ms; /* unit : ms */ int nr_vap, idx, bcn_idx; int i; u8 val8, late = 0; @@ -4131,20 +4619,28 @@ void tx_beacon_handlder(struct dvobj_priv *pdvobj) #ifdef DBG_SWTIMER_BASED_TXBCN RTW_INFO("set sw bcn timer %d us\n", time_offset); #endif - _set_timer(&pdvobj->txbcn_timer, time_offset / NET80211_TU_TO_US); + txbcn_timer_ms = time_offset / NET80211_TU_TO_US; + _set_timer(&pdvobj->txbcn_timer, txbcn_timer_ms); if (padapter) { +#ifdef CONFIG_BCN_RECOVERY + rtw_ap_bcn_recovery(padapter); +#endif /*CONFIG_BCN_RECOVERY*/ + +#ifdef CONFIG_BCN_XMIT_PROTECT + rtw_ap_bcn_queue_empty_check(padapter, txbcn_timer_ms); +#endif /*CONFIG_BCN_XMIT_PROTECT*/ + #ifdef DBG_SWTIMER_BASED_TXBCN RTW_INFO("padapter=%p, PORT=%d\n", padapter, padapter->hw_port); #endif /* bypass TX BCN queue if op ch is switching/waiting */ if (!check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) - #ifdef CONFIG_DFS_MASTER && !IS_CH_WAITING(adapter_to_rfctl(padapter)) - #endif ) { /*update_beacon(padapter, _TIM_IE_, NULL, _FALSE);*/ - issue_beacon(padapter, 0); + /*issue_beacon(padapter, 0);*/ + send_beacon(padapter); } } @@ -4170,50 +4666,318 @@ void tx_beacon_timer_handlder(void *ctx) } #endif -void rtw_ap_acdata_control(_adapter *padapter, u8 power_mode) +void rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap) { - _irqL irqL; - _list *phead, *plist; - struct sta_info *psta = NULL; - struct sta_priv *pstapriv = &padapter->stapriv; - u8 sta_alive_num = 0, i; - char sta_alive_list[NUM_STA]; + sta->capability = RTW_GET_LE16(cap); + if (sta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) + sta->flags |= WLAN_STA_SHORT_PREAMBLE; + else + sta->flags &= ~WLAN_STA_SHORT_PREAMBLE; +} -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter) && rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) - /* driver doesn't access macid sleep reg under MCC */ - return; +u16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len) +{ + u8 rate_set[16]; + u8 rate_num; + int i; + u16 status = _STATS_SUCCESSFUL_; + + rtw_ies_get_supported_rate(tlv_ies, tlv_ies_len, rate_set, &rate_num); + if (rate_num == 0) { + RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" with no supported rate\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + status = _STATS_FAILURE_; + goto exit; + } + + _rtw_memcpy(sta->bssrateset, rate_set, rate_num); + sta->bssratelen = rate_num; + + if (MLME_IS_AP(adapter)) { + /* this function force only CCK rates to be bassic rate... */ + UpdateBrateTblForSoftAP(sta->bssrateset, sta->bssratelen); + } + + /* if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G) */ /* ? */ + sta->flags |= WLAN_STA_NONERP; + for (i = 0; i < sta->bssratelen; i++) { + if ((sta->bssrateset[i] & 0x7f) > 22) { + sta->flags &= ~WLAN_STA_NONERP; + break; + } + } + +exit: + return status; +} + +u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems) +{ + struct security_priv *sec = &adapter->securitypriv; + u8 *wpa_ie; + int wpa_ie_len; + int group_cipher = 0, pairwise_cipher = 0; + u8 mfp_opt = MFP_NO; + u16 status = _STATS_SUCCESSFUL_; + + sta->dot8021xalg = 0; + sta->wpa_psk = 0; + sta->wpa_group_cipher = 0; + sta->wpa2_group_cipher = 0; + sta->wpa_pairwise_cipher = 0; + sta->wpa2_pairwise_cipher = 0; + _rtw_memset(sta->wpa_ie, 0, sizeof(sta->wpa_ie)); + + if ((sec->wpa_psk & BIT(1)) && elems->rsn_ie) { + wpa_ie = elems->rsn_ie; + wpa_ie_len = elems->rsn_ie_len; + + if (rtw_parse_wpa2_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) { + sta->dot8021xalg = 1;/* psk, todo:802.1x */ + sta->wpa_psk |= BIT(1); + + sta->wpa2_group_cipher = group_cipher & sec->wpa2_group_cipher; + sta->wpa2_pairwise_cipher = pairwise_cipher & sec->wpa2_pairwise_cipher; + + if (!sta->wpa2_group_cipher) + status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; + + if (!sta->wpa2_pairwise_cipher) + status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; + } else + status = WLAN_STATUS_INVALID_IE; + + } + else if ((sec->wpa_psk & BIT(0)) && elems->wpa_ie) { + wpa_ie = elems->wpa_ie; + wpa_ie_len = elems->wpa_ie_len; + + if (rtw_parse_wpa_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + sta->dot8021xalg = 1;/* psk, todo:802.1x */ + sta->wpa_psk |= BIT(0); + + sta->wpa_group_cipher = group_cipher & sec->wpa_group_cipher; + sta->wpa_pairwise_cipher = pairwise_cipher & sec->wpa_pairwise_cipher; + + if (!sta->wpa_group_cipher) + status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; + + if (!sta->wpa_pairwise_cipher) + status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; + } else + status = WLAN_STATUS_INVALID_IE; + + } else { + wpa_ie = NULL; + wpa_ie_len = 0; + } + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + /* MFP is mandatory for secure mesh */ + if (adapter->mesh_info.mesh_auth_id) + sta->flags |= WLAN_STA_MFP; + } else #endif + if ((sec->mfp_opt == MFP_REQUIRED && mfp_opt == MFP_NO) || mfp_opt == MFP_INVALID) + status = WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION; + else if (sec->mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL) + sta->flags |= WLAN_STA_MFP; - /*RTW_INFO(FUNC_ADPT_FMT " associated sta num:%d, make macid_%s!!\n", - FUNC_ADPT_ARG(padapter), pstapriv->asoc_list_cnt, power_mode ? "sleep" : "wakeup");*/ + if (status != _STATS_SUCCESSFUL_) + goto exit; - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (!MLME_IS_AP(adapter)) + goto exit; - phead = &pstapriv->asoc_list; - plist = get_next(phead); + sta->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS); + /* if (hapd->conf->wps_state && wpa_ie == NULL) { */ /* todo: to check ap if supporting WPS */ + if (wpa_ie == NULL) { + if (elems->wps_ie) { + RTW_INFO("STA included WPS IE in " + "(Re)Association Request - assume WPS is " + "used\n"); + sta->flags |= WLAN_STA_WPS; + /* wpabuf_free(sta->wps_ie); */ + /* sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, */ + /* elems.wps_ie_len - 4); */ + } else { + RTW_INFO("STA did not include WPA/RSN IE " + "in (Re)Association Request - possible WPS " + "use\n"); + sta->flags |= WLAN_STA_MAYBE_WPS; + } - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - int stainfo_offset; + /* AP support WPA/RSN, and sta is going to do WPS, but AP is not ready */ + /* that the selected registrar of AP is _FLASE */ + if ((sec->wpa_psk > 0) + && (sta->flags & (WLAN_STA_WPS | WLAN_STA_MAYBE_WPS)) + ) { + struct mlme_priv *mlme = &adapter->mlmepriv; - psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); - plist = get_next(plist); + if (mlme->wps_beacon_ie) { + u8 selected_registrar = 0; - stainfo_offset = rtw_stainfo_offset(pstapriv, psta); - if (stainfo_offset_valid(stainfo_offset)) - sta_alive_list[sta_alive_num++] = stainfo_offset; + rtw_get_wps_attr_content(mlme->wps_beacon_ie, mlme->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR, &selected_registrar, NULL); + + if (!selected_registrar) { + RTW_INFO("selected_registrar is _FALSE , or AP is not ready to do WPS\n"); + status = _STATS_UNABLE_HANDLE_STA_; + goto exit; + } + } + } + + } else { + int copy_len; + + if (sec->wpa_psk == 0) { + RTW_INFO("STA " MAC_FMT + ": WPA/RSN IE in association request, but AP don't support WPA/RSN\n", + MAC_ARG(sta->cmn.mac_addr)); + status = WLAN_STATUS_INVALID_IE; + goto exit; + } + + if (elems->wps_ie) { + RTW_INFO("STA included WPS IE in " + "(Re)Association Request - WPS is " + "used\n"); + sta->flags |= WLAN_STA_WPS; + copy_len = 0; + } else + copy_len = ((wpa_ie_len + 2) > sizeof(sta->wpa_ie)) ? (sizeof(sta->wpa_ie)) : (wpa_ie_len + 2); + + if (copy_len > 0) + _rtw_memcpy(sta->wpa_ie, wpa_ie - 2, copy_len); } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - for (i = 0; i < sta_alive_num; i++) { - psta = rtw_get_stainfo_by_offset(pstapriv, sta_alive_list[i]); +exit: + return status; +} + +void rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01}; + u8 *p; - if (psta) { - if (power_mode) - rtw_hal_macid_sleep(padapter, psta->mac_id); - else - rtw_hal_macid_wakeup(padapter, psta->mac_id); + sta->flags &= ~WLAN_STA_WME; + sta->qos_option = 0; + sta->qos_info = 0; + sta->has_legacy_ac = _TRUE; + sta->uapsd_vo = 0; + sta->uapsd_vi = 0; + sta->uapsd_be = 0; + sta->uapsd_bk = 0; + + if (!mlme->qospriv.qos_option) + goto exit; + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + /* QoS is mandatory in mesh */ + sta->flags |= WLAN_STA_WME; + } +#endif + + p = rtw_get_ie_ex(tlv_ies, tlv_ies_len, WLAN_EID_VENDOR_SPECIFIC, WMM_IE, 6, NULL, NULL); + if (!p) + goto exit; + + sta->flags |= WLAN_STA_WME; + sta->qos_option = 1; + sta->qos_info = *(p + 8); + sta->max_sp_len = (sta->qos_info >> 5) & 0x3; + + if ((sta->qos_info & 0xf) != 0xf) + sta->has_legacy_ac = _TRUE; + else + sta->has_legacy_ac = _FALSE; + + if (sta->qos_info & 0xf) { + if (sta->qos_info & BIT(0)) + sta->uapsd_vo = BIT(0) | BIT(1); + else + sta->uapsd_vo = 0; + + if (sta->qos_info & BIT(1)) + sta->uapsd_vi = BIT(0) | BIT(1); + else + sta->uapsd_vi = 0; + + if (sta->qos_info & BIT(2)) + sta->uapsd_bk = BIT(0) | BIT(1); + else + sta->uapsd_bk = 0; + + if (sta->qos_info & BIT(3)) + sta->uapsd_be = BIT(0) | BIT(1); + else + sta->uapsd_be = 0; + } + +exit: + return; +} + +void rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + + sta->flags &= ~WLAN_STA_HT; + +#ifdef CONFIG_80211N_HT + if (mlme->htpriv.ht_option == _FALSE) + goto exit; + + /* save HT capabilities in the sta object */ + _rtw_memset(&sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap)); + if (elems->ht_capabilities && elems->ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) { + sta->flags |= WLAN_STA_HT; + sta->flags |= WLAN_STA_WME; + _rtw_memcpy(&sta->htpriv.ht_cap, elems->ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap)); + + if (elems->ht_operation && elems->ht_operation_len == HT_OP_IE_LEN) { + _rtw_memcpy(sta->htpriv.ht_op, elems->ht_operation, HT_OP_IE_LEN); + sta->htpriv.op_present = 1; } } +exit: +#endif + + return; +} + +void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + + sta->flags &= ~WLAN_STA_VHT; + +#ifdef CONFIG_80211AC_VHT + if (mlme->vhtpriv.vht_option == _FALSE) + goto exit; + + _rtw_memset(&sta->vhtpriv, 0, sizeof(struct vht_priv)); + if (elems->vht_capabilities && elems->vht_capabilities_len == VHT_CAP_IE_LEN) { + sta->flags |= WLAN_STA_VHT; + _rtw_memcpy(sta->vhtpriv.vht_cap, elems->vht_capabilities, VHT_CAP_IE_LEN); + + if (elems->vht_operation && elems->vht_operation_len== VHT_OP_IE_LEN) { + _rtw_memcpy(sta->vhtpriv.vht_op, elems->vht_operation, VHT_OP_IE_LEN); + sta->vhtpriv.op_present = 1; + } + + if (elems->vht_op_mode_notify && elems->vht_op_mode_notify_len == 1) { + _rtw_memcpy(&sta->vhtpriv.vht_op_mode_notify, elems->vht_op_mode_notify, 1); + sta->vhtpriv.notify_present = 1; + } + } +exit: +#endif + + return; } #endif /* CONFIG_AP_MODE */ + diff --git a/core/rtw_beamforming.c b/core/rtw_beamforming.c index 6bd7a30..78a3986 100644 --- a/core/rtw_beamforming.c +++ b/core/rtw_beamforming.c @@ -45,10 +45,10 @@ static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 * * a DLS or TDLS peer STA */ - aid = sta->aid; + aid = sta->cmn.aid; bssid = adapter_mac_addr(adapter); RTW_INFO("%s: AID=0x%x BSSID=" MAC_FMT "\n", - __FUNCTION__, sta->aid, MAC_ARG(bssid)); + __FUNCTION__, sta->cmn.aid, MAC_ARG(bssid)); /* AID[0:8] */ aid &= 0x1FF; @@ -70,7 +70,7 @@ static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 * *g_id = 63; } else { /* Addressed to AP */ - bssid = sta->hwaddr; + bssid = sta->cmn.mac_addr; RTW_INFO("%s: BSSID=" MAC_FMT "\n", __FUNCTION__, MAC_ARG(bssid)); /* BSSID[39:47] */ @@ -162,7 +162,7 @@ static void _get_sta_beamform_cap(PADAPTER adapter, struct sta_info *sta, #endif /* CONFIG_80211AC_VHT */ } -static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, CHANNEL_WIDTH bw) +static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, enum channel_width bw) { /* General */ struct xmit_priv *pxmitpriv; @@ -260,7 +260,7 @@ static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, CHANNEL_WIDTH bw) return _TRUE; } -static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw) +static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, enum channel_width bw) { /* General */ struct xmit_priv *pxmitpriv; @@ -366,7 +366,7 @@ static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, CHANNEL_WIDTH return _TRUE; } -static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, CHANNEL_WIDTH bw) +static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, enum channel_width bw) { /* General */ struct xmit_priv *pxmitpriv; @@ -1008,7 +1008,7 @@ static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter, mlme = &adapter->mlmepriv; info = GET_BEAMFORM_INFO(adapter); - bfer = _bfer_get_entry_by_addr(adapter, sta->hwaddr); + bfer = _bfer_get_entry_by_addr(adapter, sta->cmn.mac_addr); if (!bfer) { bfer = _bfer_get_free_entry(adapter); if (!bfer) @@ -1017,14 +1017,14 @@ static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter, bfer->used = _TRUE; _get_txvector_parameter(adapter, sta, &bfer->g_id, &bfer->p_aid); - _rtw_memcpy(bfer->mac_addr, sta->hwaddr, ETH_ALEN); + _rtw_memcpy(bfer->mac_addr, sta->cmn.mac_addr, ETH_ALEN); bfer->cap = bf_cap; bfer->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT; bfer->NumofSoundingDim = sounding_dim; if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_MU)) { info->beamformer_mu_cnt += 1; - bfer->aid = sta->aid; + bfer->aid = sta->cmn.aid; } else if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) { info->beamformer_su_cnt += 1; @@ -1193,7 +1193,7 @@ static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter, mlme = &adapter->mlmepriv; info = GET_BEAMFORM_INFO(adapter); - bfee = _bfee_get_entry_by_addr(adapter, sta->hwaddr); + bfee = _bfee_get_entry_by_addr(adapter, sta->cmn.mac_addr); if (!bfee) { bfee = _bfee_get_free_entry(adapter); if (!bfee) @@ -1201,15 +1201,15 @@ static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter, } bfee->used = _TRUE; - bfee->aid = sta->aid; - bfee->mac_id = sta->mac_id; - bfee->sound_bw = sta->bw_mode; + bfee->aid = sta->cmn.aid; + bfee->mac_id = sta->cmn.mac_id; + bfee->sound_bw = sta->cmn.bw_mode; _get_txvector_parameter(adapter, sta, &bfee->g_id, &bfee->p_aid); - sta->txbf_gid = bfee->g_id; - sta->txbf_paid = bfee->p_aid; + sta->cmn.bf_info.g_id = bfee->g_id; + sta->cmn.bf_info.p_aid = bfee->p_aid; - _rtw_memcpy(bfee->mac_addr, sta->hwaddr, ETH_ALEN); + _rtw_memcpy(bfee->mac_addr, sta->cmn.mac_addr, ETH_ALEN); bfee->txbf = _FALSE; bfee->sounding = _FALSE; bfee->sound_period = 40; @@ -1380,15 +1380,15 @@ static void _beamforming_enter(PADAPTER adapter, void *p) info = GET_BEAMFORM_INFO(adapter); sta_copy = (struct sta_info *)p; - sta = rtw_get_stainfo(&adapter->stapriv, sta_copy->hwaddr); + sta = rtw_get_stainfo(&adapter->stapriv, sta_copy->cmn.mac_addr); if (!sta) { RTW_ERR("%s: Cann't find STA info for " MAC_FMT "\n", - __FUNCTION__, MAC_ARG(sta_copy->hwaddr)); + __FUNCTION__, MAC_ARG(sta_copy->cmn.mac_addr)); return; } if (sta != sta_copy) { RTW_WARN("%s: Origin sta(fake)=%p realsta=%p for " MAC_FMT "\n", - __FUNCTION__, sta_copy, sta, MAC_ARG(sta_copy->hwaddr)); + __FUNCTION__, sta_copy, sta, MAC_ARG(sta_copy->cmn.mac_addr)); } /* The current setting does not support Beaforming */ @@ -1901,8 +1901,8 @@ u8 rtw_bf_cmd(PADAPTER adapter, s32 type, u8 *pbuf, s32 size, u8 enqueue) void rtw_bf_update_attrib(PADAPTER adapter, struct pkt_attrib *attrib, struct sta_info *sta) { if (sta) { - attrib->txbf_g_id = sta->txbf_gid; - attrib->txbf_p_aid = sta->txbf_paid; + attrib->txbf_g_id = sta->cmn.bf_info.g_id; + attrib->txbf_p_aid = sta->cmn.bf_info.p_aid; } } @@ -1926,7 +1926,8 @@ void rtw_bf_update_traffic(PADAPTER adapter) u16 tp[MAX_BEAMFORMEE_ENTRY_NUM] = {0}; u8 tx_rate[MAX_BEAMFORMEE_ENTRY_NUM] = {0}; u64 tx_bytes, last_bytes; - u32 time, last_timestamp; + u32 time; + systime last_timestamp; u8 set_timer = _FALSE; @@ -1961,7 +1962,7 @@ void rtw_bf_update_traffic(PADAPTER adapter) time = rtw_get_time_interval_ms(last_timestamp, bfee->tx_timestamp); time = (time > 1000) ? time/1000 : 1; tp[i] = toMbps(tx_bytes, time); - tx_rate[i] = rtw_get_current_tx_rate(adapter, bfee->mac_id); + tx_rate[i] = rtw_get_current_tx_rate(adapter, sta); RTW_INFO("%s: BFee idx(%d), MadId(%d), TxTP=%lld bytes (%d Mbps), txrate=%d\n", __FUNCTION__, i, bfee->mac_id, tx_bytes, tp[i], tx_rate[i]); } @@ -2053,7 +2054,7 @@ struct beamforming_entry *beamforming_get_free_entry(struct mlme_priv *pmlmepriv struct beamforming_entry *beamforming_add_entry(PADAPTER adapter, u8 *ra, u16 aid, - u16 mac_id, CHANNEL_WIDTH bw, BEAMFORMING_CAP beamfrom_cap, u8 *idx) + u16 mac_id, enum channel_width bw, BEAMFORMING_CAP beamfrom_cap, u8 *idx) { struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); struct beamforming_entry *pEntry = beamforming_get_free_entry(pmlmepriv, idx); @@ -2115,8 +2116,10 @@ void beamforming_dym_ndpa_rate(PADAPTER adapter) { u16 NDPARate = MGN_6M; PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + s8 min_rssi = 0; - if (pHalData->min_undecorated_pwdb_for_dm > 30) /* link RSSI > 30% */ + min_rssi = rtw_phydm_get_min_rssi(adapter); + if (min_rssi > 30) /* link RSSI > 30% */ NDPARate = MGN_24M; else NDPARate = MGN_6M; @@ -2169,7 +2172,7 @@ void beamforming_dym_period(PADAPTER Adapter) rtw_hal_set_hwreg(Adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&Idx); } -BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx) +BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx) { struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; @@ -2248,7 +2251,7 @@ BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 q } -BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx) +BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx) { struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; @@ -2323,11 +2326,11 @@ BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx return _TRUE; } -BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx) +BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx) { return issue_ht_ndpa_packet(Adapter, ra, bw, qidx); } -BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx) +BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx) { struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; @@ -2421,7 +2424,7 @@ BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDT return _TRUE; } -BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx) +BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx) { struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; @@ -2507,7 +2510,7 @@ BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH b return _TRUE; } -BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx) +BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx) { return issue_vht_ndpa_packet(Adapter, ra, aid, bw, qidx); } @@ -2565,9 +2568,9 @@ u16 beamforming_sounding_time(struct beamforming_info *pBeamInfo, SOUNDING_MODE return sounding_time; } -CHANNEL_WIDTH beamforming_sounding_bw(struct beamforming_info *pBeamInfo, SOUNDING_MODE mode, u8 idx) +enum channel_width beamforming_sounding_bw(struct beamforming_info *pBeamInfo, SOUNDING_MODE mode, u8 idx) { - CHANNEL_WIDTH sounding_bw = CHANNEL_WIDTH_20; + enum channel_width sounding_bw = CHANNEL_WIDTH_20; struct beamforming_entry BeamEntry = pBeamInfo->beamforming_entry[idx]; sounding_bw = BeamEntry.sound_bw; @@ -2704,7 +2707,7 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8 *idx) u8 *ra; u16 aid, mac_id; u8 wireless_mode; - CHANNEL_WIDTH bw = CHANNEL_WIDTH_20; + enum channel_width bw = CHANNEL_WIDTH_20; BEAMFORMING_CAP beamform_cap = BEAMFORMING_CAP_NONE; /* The current setting does not support Beaforming */ @@ -2717,11 +2720,11 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8 *idx) return _FALSE; } - aid = psta->aid; - ra = psta->hwaddr; - mac_id = psta->mac_id; + aid = psta->cmn.aid; + ra = psta->cmn.mac_addr; + mac_id = psta->cmn.mac_id; wireless_mode = psta->wireless_mode; - bw = psta->bw_mode; + bw = psta->cmn.bw_mode; if (is_supported_ht(wireless_mode) || is_supported_vht(wireless_mode)) { /* 3 */ /* HT */ @@ -2773,8 +2776,8 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8 *idx) } pBeamformEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; - psta->txbf_paid = pBeamformEntry->p_aid; - psta->txbf_gid = pBeamformEntry->g_id; + psta->cmn.bf_info.p_aid = pBeamformEntry->p_aid; + psta->cmn.bf_info.g_id = pBeamformEntry->g_id; RTW_INFO("%s Idx %d\n", __FUNCTION__, *idx); } else @@ -2913,7 +2916,7 @@ u32 rtw_beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_ u32 ret = _SUCCESS; #if (BEAMFORMING_SUPPORT == 1) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); ret = beamforming_get_report_frame(pDM_Odm, precv_frame); @@ -2960,7 +2963,7 @@ void rtw_beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_f { #if (BEAMFORMING_SUPPORT == 1) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); beamforming_get_ndpa_frame(pDM_Odm, precv_frame); @@ -3036,13 +3039,13 @@ void rtw_beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_f void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); #if (BEAMFORMING_SUPPORT == 1) /*(BEAMFORMING_SUPPORT == 1)- for PHYDM beamfoming*/ switch (type) { case BEAMFORMING_CTRL_ENTER: { struct sta_info *psta = (PVOID)pbuf; - u16 staIdx = psta->mac_id; + u16 staIdx = psta->cmn.mac_id; beamforming_enter(pDM_Odm, staIdx); break; @@ -3143,8 +3146,8 @@ u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enque void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta) { if (psta) { - pattrib->txbf_g_id = psta->txbf_gid; - pattrib->txbf_p_aid = psta->txbf_paid; + pattrib->txbf_g_id = psta->cmn.bf_info.g_id; + pattrib->txbf_p_aid = psta->cmn.bf_info.p_aid; } } #endif /* !RTW_BEAMFORMING_VERSION_2 */ diff --git a/core/rtw_bt_mp.c b/core/rtw_bt_mp.c index 85516f9..9b4fc24 100644 --- a/core/rtw_bt_mp.c +++ b/core/rtw_bt_mp.c @@ -466,7 +466,7 @@ MPTBT_FwC2hBtMpCtrl( PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)tmpBuf; - if (Adapter->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0) { + if (GET_HAL_DATA(Adapter)->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0) { /* RTW_INFO("Ignore C2H BT MP Info since not in MP mode\n"); */ return; } diff --git a/core/rtw_btcoex.c b/core/rtw_btcoex.c index 730447f..d1d8355 100644 --- a/core/rtw_btcoex.c +++ b/core/rtw_btcoex.c @@ -12,12 +12,10 @@ * more details. * *****************************************************************************/ -#ifdef CONFIG_BT_COEXIST - #include -#include #include - +#ifdef CONFIG_BT_COEXIST +#include void rtw_btcoex_Initialize(PADAPTER padapter) { @@ -29,6 +27,11 @@ void rtw_btcoex_PowerOnSetting(PADAPTER padapter) hal_btcoex_PowerOnSetting(padapter); } +void rtw_btcoex_AntInfoSetting(PADAPTER padapter) +{ + hal_btcoex_AntInfoSetting(padapter); +} + void rtw_btcoex_PowerOffSetting(PADAPTER padapter) { hal_btcoex_PowerOffSetting(padapter); @@ -240,6 +243,16 @@ void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type) hal_btcoex_switchband_notify(under_scan, band_type); } +void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length) +{ + hal_btcoex_WlFwDbgInfoNotify(padapter, tmpBuf, length); +} + +void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id) +{ + hal_btcoex_rx_rate_change_notify(padapter, is_data_frame, rate_id); +} + void rtw_btcoex_SwitchBtTRxMask(PADAPTER padapter) { hal_btcoex_SwitchBtTRxMask(padapter); @@ -1729,3 +1742,22 @@ void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType) } #endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ #endif /* CONFIG_BT_COEXIST */ + +void rtw_btcoex_set_ant_info(PADAPTER padapter) +{ +#ifdef CONFIG_BT_COEXIST + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); + + if (hal->EEPROMBluetoothCoexist == _TRUE) { + u8 bMacPwrCtrlOn = _FALSE; + + rtw_btcoex_AntInfoSetting(padapter); + rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + if (bMacPwrCtrlOn == _TRUE) + rtw_btcoex_PowerOnSetting(padapter); + } + else +#endif + rtw_btcoex_wifionly_AntInfoSetting(padapter); +} + diff --git a/core/rtw_btcoex_wifionly.c b/core/rtw_btcoex_wifionly.c index f7d70aa..e26b3a0 100644 --- a/core/rtw_btcoex_wifionly.c +++ b/core/rtw_btcoex_wifionly.c @@ -35,3 +35,8 @@ void rtw_btcoex_wifionly_initialize(PADAPTER padapter) { hal_btcoex_wifionly_initlizevariables(padapter); } + +void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter) +{ + hal_btcoex_wifionly_AntInfoSetting(padapter); +} diff --git a/core/rtw_cmd.c b/core/rtw_cmd.c index 1486afa..a783412 100644 --- a/core/rtw_cmd.c +++ b/core/rtw_cmd.c @@ -452,7 +452,7 @@ u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) #ifdef CONFIG_CONCURRENT_MODE /* change pcmdpriv to primary's pcmdpriv */ - if (padapter->adapter_type != PRIMARY_ADAPTER) + if (!is_primary_adapter(padapter)) pcmdpriv = &(GET_PRIMARY_ADAPTER(padapter)->cmdpriv); #endif @@ -535,7 +535,7 @@ thread_return rtw_cmd_thread(thread_context context) u8 ret; struct cmd_obj *pcmd; u8 *pcmdbuf, *prspbuf; - u32 cmd_start_time; + systime cmd_start_time; u32 cmd_process_time; u8(*cmd_hdl)(_adapter *padapter, u8 *pbuf); void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd); @@ -842,13 +842,21 @@ u8 rtw_setstandby_cmd(_adapter *padapter, uint action) return ret; } +void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + + _rtw_memset(pparm, 0, sizeof(struct sitesurvey_parm)); + pparm->scan_mode = pmlmepriv->scan_mode; +} + /* rtw_sitesurvey_cmd(~) ### NOTE:#### (!!!!) MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock */ -u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, - struct rtw_ieee80211_channel *ch, int ch_num) +u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm) { u8 res = _FAIL; struct cmd_obj *ph2c; @@ -859,7 +867,6 @@ u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif /* CONFIG_P2P */ - #ifdef CONFIG_LPS if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 1); @@ -880,65 +887,25 @@ u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, return _FAIL; } - rtw_free_network_queue(padapter, _FALSE); + if (pparm) + _rtw_memcpy(psurveyPara, pparm, sizeof(struct sitesurvey_parm)); + else + psurveyPara->scan_mode = pmlmepriv->scan_mode; + rtw_free_network_queue(padapter, _FALSE); init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey)); - /* psurveyPara->bsslimit = 48; */ - psurveyPara->scan_mode = pmlmepriv->scan_mode; - - /* prepare ssid list */ - if (ssid) { - int i; - for (i = 0; i < ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) { - if (ssid[i].SsidLength) { - _rtw_memcpy(&psurveyPara->ssid[i], &ssid[i], sizeof(NDIS_802_11_SSID)); - psurveyPara->ssid_num++; - if (0) - RTW_INFO(FUNC_ADPT_FMT" ssid:(%s, %d)\n", FUNC_ADPT_ARG(padapter), - psurveyPara->ssid[i].Ssid, psurveyPara->ssid[i].SsidLength); - } - } - } - - /* prepare channel list */ - if (ch) { - int i; - for (i = 0; i < ch_num && i < RTW_CHANNEL_SCAN_AMOUNT; i++) { - if (ch[i].hw_value && !(ch[i].flags & RTW_IEEE80211_CHAN_DISABLED)) { - _rtw_memcpy(&psurveyPara->ch[i], &ch[i], sizeof(struct rtw_ieee80211_channel)); - psurveyPara->ch_num++; - if (0) - RTW_INFO(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), - psurveyPara->ch[i].hw_value); - } - } - } - set_fwstate(pmlmepriv, _FW_UNDER_SURVEY); res = rtw_enqueue_cmd(pcmdpriv, ph2c); if (res == _SUCCESS) { + u32 scan_timeout_ms; pmlmepriv->scan_start_time = rtw_get_current_time(); - -#ifdef CONFIG_SCAN_BACKOP - if (rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) { - if (is_supported_5g(padapter->registrypriv.wireless_mode) - && IsSupported24G(padapter->registrypriv.wireless_mode)) /* dual band */ - mlme_set_scan_to_timer(pmlmepriv, CONC_SCANNING_TIMEOUT_DUAL_BAND); - else /* single band */ - mlme_set_scan_to_timer(pmlmepriv, CONC_SCANNING_TIMEOUT_SINGLE_BAND); - } else -#endif /* CONFIG_SCAN_BACKOP */ -#ifdef CONFIG_CHNL_LOAD_MAGT - if (padapter->clm_flag == TRUE) - mlme_set_scan_to_timer(pmlmepriv, CLM_SCANNING_TIMEOUT); - else -#endif - mlme_set_scan_to_timer(pmlmepriv, SCANNING_TIMEOUT); + scan_timeout_ms = rtw_scan_timeout_decision(padapter); + mlme_set_scan_to_timer(pmlmepriv,scan_timeout_ms); rtw_led_control(padapter, LED_CTL_SITE_SURVEY); } else @@ -1324,7 +1291,7 @@ inline u8 rtw_create_ibss_cmd(_adapter *adapter, int flags) { return rtw_createbss_cmd(adapter, flags , 1 - , 0, -1, -1 /* for now, adhoc doesn't support ch,bw,offset request */ + , 0, REQ_BW_NONE, REQ_OFFSET_NONE /* for now, adhoc doesn't support ch,bw,offset request */ ); } @@ -1332,7 +1299,7 @@ inline u8 rtw_startbss_cmd(_adapter *adapter, int flags) { return rtw_createbss_cmd(adapter, flags , 0 - , 0, -1, -1 /* excute entire AP setup cmd */ + , 0, REQ_BW_NONE, REQ_OFFSET_NONE /* excute entire AP setup cmd */ ); } @@ -1344,6 +1311,42 @@ inline u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags, s16 req_ch, s8 r ); } +#ifdef CONFIG_RTW_80211R +static void rtw_ft_validate_akm_type(_adapter *padapter, + struct wlan_network *pnetwork) +{ + struct security_priv *psecuritypriv = &(padapter->securitypriv); + struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); + u32 tmp_len; + u8 *ptmp; + + /*IEEE802.11-2012 Std. Table 8-101¡XAKM suite selectors*/ + if (rtw_ft_valid_akm(padapter, psecuritypriv->rsn_akm_suite_type)) { + ptmp = rtw_get_ie(&pnetwork->network.IEs[12], + _MDIE_, &tmp_len, (pnetwork->network.IELength-12)); + if (ptmp) { + pft_roam->mdid = *(u16 *)(ptmp+2); + pft_roam->ft_cap = *(ptmp+4); + + RTW_INFO("FT: target " MAC_FMT " mdid=(0x%2x), capacity=(0x%2x)\n", + MAC_ARG(pnetwork->network.MacAddress), pft_roam->mdid, pft_roam->ft_cap); + rtw_ft_set_flags(padapter, RTW_FT_PEER_EN); + + if (rtw_ft_otd_roam_en(padapter)) + rtw_ft_set_flags(padapter, RTW_FT_PEER_OTD_EN); + } else { + /* Don't use FT roaming if target AP cannot support FT */ + rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN)); + rtw_ft_reset_status(padapter); + } + } else { + /* It could be a non-FT connection */ + rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN)); + rtw_ft_reset_status(padapter); + } +} +#endif + u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) { u8 *auth, res = _SUCCESS; @@ -1367,9 +1370,6 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); u32 tmp_len; u8 *ptmp = NULL; -#ifdef CONFIG_RTW_80211R - struct _ft_priv *pftpriv = &pmlmepriv->ftpriv; -#endif rtw_led_control(padapter, LED_CTL_START_TO_LINK); @@ -1402,12 +1402,9 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) set_fwstate(pmlmepriv, WIFI_STATION_STATE); break; - case Ndis802_11APMode: - case Ndis802_11AutoUnknown: - case Ndis802_11InfrastructureMax: - case Ndis802_11Monitor: + default: + rtw_warn_on(1); break; - } } @@ -1449,12 +1446,19 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) if (pmlmepriv->assoc_by_bssid == _FALSE) _rtw_memcpy(&pmlmepriv->assoc_bssid[0], &pnetwork->network.MacAddress[0], ETH_ALEN); - psecnetwork->IELength = rtw_restruct_sec_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength); + /* copy fixed ie */ + _rtw_memcpy(psecnetwork->IEs, pnetwork->network.IEs, 12); + psecnetwork->IELength = 12; + + psecnetwork->IELength += rtw_restruct_sec_ie(padapter, psecnetwork->IEs + psecnetwork->IELength); pqospriv->qos_option = 0; if (pregistrypriv->wmm_enable) { +#ifdef CONFIG_WMMPS_STA + rtw_uapsd_use_default_setting(padapter); +#endif /* CONFIG_WMMPS_STA */ tmp_len = rtw_restruct_wmm_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, psecnetwork->IELength); if (psecnetwork->IELength != tmp_len) { @@ -1501,31 +1505,7 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) #endif /* CONFIG_80211N_HT */ #ifdef CONFIG_RTW_80211R - /*IEEE802.11-2012 Std. Table 8-101¡XAKM suite selectors*/ - if ((rtw_chk_ft_flags(padapter, RTW_FT_STA_SUPPORTED)) && - ((psecuritypriv->rsn_akm_suite_type == 3) || (psecuritypriv->rsn_akm_suite_type == 4)) - ) { - ptmp = rtw_get_ie(&pnetwork->network.IEs[12], _MDIE_, &tmp_len, pnetwork->network.IELength-12); - if (ptmp) { - _rtw_memcpy(&pftpriv->mdid, ptmp+2, 2); - pftpriv->ft_cap = *(ptmp+4); - - RTW_INFO("FT: Target AP "MAC_FMT" MDID=(0x%2x), capacity=(0x%2x)\n", MAC_ARG(pnetwork->network.MacAddress), pftpriv->mdid, pftpriv->ft_cap); - rtw_set_ft_flags(padapter, RTW_FT_SUPPORTED); - if ((rtw_chk_ft_flags(padapter, RTW_FT_STA_OVER_DS_SUPPORTED)) && (pftpriv->ft_roam_on_expired == _FALSE) && (pftpriv->ft_cap & 0x01)) - rtw_set_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED); - } else { - /*Don't use FT roaming if Target AP cannot support FT*/ - RTW_INFO("FT: Target AP "MAC_FMT" could not support FT\n", MAC_ARG(pnetwork->network.MacAddress)); - rtw_clr_ft_flags(padapter, RTW_FT_SUPPORTED|RTW_FT_OVER_DS_SUPPORTED); - rtw_reset_ft_status(padapter); - } - } else { - /*It could be a non-FT connection*/ - RTW_INFO("FT: non-FT rtw_joinbss_cmd\n"); - rtw_clr_ft_flags(padapter, RTW_FT_SUPPORTED|RTW_FT_OVER_DS_SUPPORTED); - rtw_reset_ft_status(padapter); - } + rtw_ft_validate_akm_type(padapter, pnetwork); #endif #if 0 @@ -1625,39 +1605,55 @@ u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags) /* for return res; } -u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, bool enqueue) +u8 rtw_setopmode_cmd(_adapter *adapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags) { - struct cmd_obj *ph2c; - struct setopmode_parm *psetop; - - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 res = _SUCCESS; - - psetop = (struct setopmode_parm *)rtw_zmalloc(sizeof(struct setopmode_parm)); + struct cmd_obj *cmdobj; + struct setopmode_parm *parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; - if (psetop == NULL) { + /* prepare cmd parameter */ + parm = (struct setopmode_parm *)rtw_zmalloc(sizeof(*parm)); + if (parm == NULL) { res = _FAIL; goto exit; } - psetop->mode = (u8)networktype; + parm->mode = (u8)networktype; - if (enqueue) { - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { - rtw_mfree((u8 *)psetop, sizeof(*psetop)); + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != setopmode_hdl(adapter, (u8 *)parm)) + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); goto exit; } - init_h2fwcmd_w_parm_no_rsp(ph2c, psetop, _SetOpMode_CMD_); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); - } else { - setopmode_hdl(padapter, (u8 *)psetop); - rtw_mfree((u8 *)psetop, sizeof(*psetop)); - } -exit: + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, _SetOpMode_CMD_); + + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 2000); + } + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + } + } +exit: return res; } @@ -1679,16 +1675,17 @@ u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool goto exit; } - _rtw_memcpy(psetstakey_para->addr, sta->hwaddr, ETH_ALEN); + _rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN); if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) psetstakey_para->algorithm = (unsigned char) psecuritypriv->dot11PrivacyAlgrthm; else GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE); - if (key_type == GROUP_KEY) + if (key_type == GROUP_KEY) { _rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, 16); - else if (key_type == UNICAST_KEY) + psetstakey_para->gk = 1; + } else if (key_type == UNICAST_KEY) _rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, 16); #ifdef CONFIG_TDLS else if (key_type == TDLS_KEY) { @@ -1741,10 +1738,14 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue) s16 cam_id = 0; u8 res = _SUCCESS; + if (!sta) { + RTW_ERR("%s sta == NULL\n", __func__); + goto exit; + } if (!enqueue) { - while ((cam_id = rtw_camid_search(padapter, sta->hwaddr, -1, -1)) >= 0) { - RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(sta->hwaddr), cam_id); + while ((cam_id = rtw_camid_search(padapter, sta->cmn.mac_addr, -1, -1)) >= 0) { + RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(sta->cmn.mac_addr), cam_id); clear_cam_entry(padapter, cam_id); rtw_camid_free(padapter, cam_id); } @@ -1774,7 +1775,7 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue) ph2c->rsp = (u8 *) psetstakey_rsp; ph2c->rspsz = sizeof(struct set_stakey_rsp); - _rtw_memcpy(psetstakey_para->addr, sta->hwaddr, ETH_ALEN); + _rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN); psetstakey_para->algorithm = _NO_PRIVACY_; @@ -2093,12 +2094,12 @@ u8 rtw_dynamic_chk_wk_cmd(_adapter *padapter) } -u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue) +u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags) { struct cmd_obj *pcmdobj; struct set_ch_parm *set_ch_parm; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - + struct submit_ctx sctx; u8 res = _SUCCESS; @@ -2117,7 +2118,13 @@ u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue) set_ch_parm->bw = bw; set_ch_parm->ch_offset = ch_offset; - if (enqueue) { + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != rtw_set_chbw_hdl(padapter, (u8 *)set_ch_parm)) + res = _FAIL; + + rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm)); + } else { /* need enqueue, prepare cmd_obj and enqueue */ pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmdobj == NULL) { @@ -2127,13 +2134,21 @@ u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue) } init_h2fwcmd_w_parm_no_rsp(pcmdobj, set_ch_parm, GEN_CMD_CODE(_SetChannel)); + + if (flags & RTW_CMDF_WAIT_ACK) { + pcmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 10 * 1000); + } + res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); - } else { - /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ - if (H2C_SUCCESS != set_ch_hdl(padapter, (u8 *)set_ch_parm)) - res = _FAIL; - rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm)); + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + pcmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + } } /* do something based on res... */ @@ -2244,7 +2259,7 @@ inline u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_ RTW_PRINT("%s country_code:\"%c%c\" mapping to chplan:0x%02x\n", __func__, country_code[0], country_code[1], ent->chplan); - return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_MAX, ent, swconfig); + return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, ent, swconfig); } u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed) @@ -2670,8 +2685,13 @@ void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter) #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK #ifdef CONFIG_AP_MODE - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { expire_timeout_chk(padapter); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter) && MLME_IS_ASOC(padapter)) + rtw_mesh_peer_status_chk(padapter); + #endif + } #endif #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ dynamic_update_bcn_check(padapter); @@ -2853,7 +2873,7 @@ u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue) void rtw_dm_in_lps_hdl(_adapter *padapter) { - rtw_hal_set_hwreg(padapter, HW_VAR_DM_IN_LPS, NULL); + rtw_hal_set_hwreg(padapter, HW_VAR_DM_IN_LPS_LCLK, NULL); } u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter) @@ -3266,9 +3286,84 @@ inline u8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev { return _p2p_roch_cmd(adapter, cookie, wdev, NULL, 0, 0, flags); } + #endif /* CONFIG_IOCTL_CFG80211 */ #endif /* CONFIG_P2P */ +#ifdef CONFIG_IOCTL_CFG80211 +inline u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + struct mgnt_tx_parm *mgnt_parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + + mgnt_parm = (struct mgnt_tx_parm *)rtw_zmalloc(sizeof(struct mgnt_tx_parm)); + if (mgnt_parm == NULL) { + res = _FAIL; + goto exit; + } + + mgnt_parm->tx_ch = tx_ch; + mgnt_parm->no_cck = no_cck; + mgnt_parm->buf = buf; + mgnt_parm->len = len; + mgnt_parm->wait_ack = wait_ack; + + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != rtw_mgnt_tx_handler(adapter, (u8 *)mgnt_parm)) + res = _FAIL; + rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm)); + res = _FAIL; + goto exit; + } + + parm->ec_id = MGNT_TX_WK_CID; + parm->type = 0; + parm->size = sizeof(*mgnt_parm); + parm->pbuf = (u8 *)mgnt_parm; + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm)); + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 10 * 1000); + } + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status != RTW_SCTX_DONE_SUCCESS) + res = _FAIL; + } + } + +exit: + return res; +} +#endif + u8 rtw_ps_cmd(_adapter *padapter) { struct cmd_obj *ppscmd; @@ -3278,7 +3373,7 @@ u8 rtw_ps_cmd(_adapter *padapter) u8 res = _SUCCESS; #ifdef CONFIG_CONCURRENT_MODE - if (padapter->adapter_type != PRIMARY_ADAPTER) + if (!is_primary_adapter(padapter)) goto exit; #endif @@ -3316,7 +3411,7 @@ static void rtw_chk_hi_queue_hdl(_adapter *padapter) { struct sta_info *psta_bmc; struct sta_priv *pstapriv = &padapter->stapriv; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); u8 empty = _FALSE; psta_bmc = rtw_get_bcmc_stainfo(padapter); @@ -3334,11 +3429,11 @@ static void rtw_chk_hi_queue_hdl(_adapter *padapter) if (empty == _SUCCESS) { bool update_tim = _FALSE; - if (pstapriv->tim_bitmap & BIT(0)) + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) update_tim = _TRUE; - pstapriv->tim_bitmap &= ~BIT(0); - pstapriv->sta_dz_bitmap &= ~BIT(0); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0); + rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0); if (update_tim == _TRUE) _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "bmc sleepq and HIQ empty"); @@ -3387,12 +3482,27 @@ u8 rtw_chk_hi_queue_cmd(_adapter *padapter) #ifdef CONFIG_DFS_MASTER u8 rtw_dfs_master_hdl(_adapter *adapter) { + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); struct mlme_priv *mlme = &adapter->mlmepriv; + int i; if (!rfctl->dfs_master_enabled) goto exit; + for (i = 0; i < dvobj->iface_nums; i++) { + if (!dvobj->padapters[i]) + continue; + if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE) + && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE)) + break; + } + + if (i >= dvobj->iface_nums) + goto cac_status_chk; + else + adapter = dvobj->padapters[i]; + if (rtw_get_on_cur_ch_time(adapter) == 0 || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 300 ) { @@ -3409,61 +3519,66 @@ u8 rtw_dfs_master_hdl(_adapter *adapter) && rtw_odm_radar_detect(adapter) != _TRUE) goto cac_status_chk; - if (rfctl->dbg_dfs_master_fake_radar_detect_cnt != 0) { - RTW_INFO(FUNC_ADPT_FMT" fake radar detect, cnt:%d\n", FUNC_ADPT_ARG(adapter) - , rfctl->dbg_dfs_master_fake_radar_detect_cnt); - rfctl->dbg_dfs_master_fake_radar_detect_cnt--; + if (!rfctl->dbg_dfs_master_fake_radar_detect_cnt + && rfctl->dbg_dfs_master_radar_detect_trigger_non + ) { + /* radar detect debug mode, trigger no mlme flow */ + RTW_INFO(FUNC_ADPT_FMT" radar detected on test mode, trigger no mlme flow\n", FUNC_ADPT_ARG(adapter)); + goto cac_status_chk; } - if (rfctl->dbg_dfs_master_radar_detect_trigger_non) { - /* radar detect debug mode, trigger no mlme flow */ - if (0) - RTW_INFO(FUNC_ADPT_FMT" radar detected, trigger no mlme flow for debug\n", FUNC_ADPT_ARG(adapter)); - } else { - /* TODO: move timer to rfctl */ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - int i; - for (i = 0; i < dvobj->iface_nums; i++) { - if (!dvobj->padapters[i]) - continue; - if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE) - && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE)) - break; - } + if (rfctl->dbg_dfs_master_fake_radar_detect_cnt != 0) { + RTW_INFO(FUNC_ADPT_FMT" fake radar detected, cnt:%d\n", FUNC_ADPT_ARG(adapter) + , rfctl->dbg_dfs_master_fake_radar_detect_cnt); + rfctl->dbg_dfs_master_fake_radar_detect_cnt--; + } else + RTW_INFO(FUNC_ADPT_FMT" radar detected\n", FUNC_ADPT_ARG(adapter)); - if (i >= dvobj->iface_nums) { - /* what? */ - rtw_warn_on(1); - } else { - rtw_chset_update_non_ocp(rfctl->channel_set - , rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset); - rfctl->radar_detected = 1; + rtw_chset_update_non_ocp(rfctl->channel_set + , rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset); + rfctl->radar_detected = 1; - /* trigger channel selection */ - rtw_change_bss_chbw_cmd(dvobj->padapters[i], RTW_CMDF_DIRECTLY, -1, dvobj->padapters[i]->mlmepriv.ori_bw, -1); - } + /* trigger channel selection */ + rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, -1, adapter->mlmepriv.ori_bw, -1); - if (rfctl->dfs_master_enabled) - goto set_timer; - goto exit; - } + if (rfctl->dfs_master_enabled) + goto set_timer; + goto exit; cac_status_chk: - if (!IS_CH_WAITING(rfctl) && !IS_CAC_STOPPED(rfctl)) { + if (!IS_CAC_STOPPED(rfctl) + && ((IS_UNDER_CAC(rfctl) && rfctl->cac_force_stop) + || !IS_CH_WAITING(rfctl) + ) + ) { u8 pause = 0x00; rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause); rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED; if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) { + u8 doiqk = _TRUE; + u8 u_ch, u_bw, u_offset; + + rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk); + + if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) + set_channel_bwmode(adapter, u_ch, u_offset, u_bw); + else + rtw_warn_on(1); + + doiqk = _FALSE; + rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk); + ResumeTxBeacon(adapter); rtw_mi_tx_beacon_hdl(adapter); } } set_timer: + /* TODO: move timer to rfctl */ _set_timer(&mlme->dfs_master_timer, DFS_MASTER_TIMER_MS); exit: @@ -3612,12 +3727,27 @@ void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action) case MLME_STA_CONNECTED: MSTATE_STA_LD_NUM(&mstate)++; break; + case MLME_STA_DISCONNECTED: + break; +#ifdef CONFIG_AP_MODE case MLME_AP_STARTED: MSTATE_AP_NUM(&mstate)++; break; case MLME_AP_STOPPED: - case MLME_STA_DISCONNECTED: + break; +#endif +#ifdef CONFIG_RTW_MESH + case MLME_MESH_STARTED: + MSTATE_MESH_NUM(&mstate)++; + break; + case MLME_MESH_STOPPED: + break; +#endif + case MLME_ACTION_NONE: + /* caller without effect of decision */ + break; default: + rtw_warn_on(1); break; } @@ -3648,8 +3778,8 @@ void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action) goto apply; } - if (MSTATE_AP_NUM(&mstate) == 0) { - /* No working AP mode */ + if (!MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) { + /* No working AP/Mesh mode */ goto apply; } @@ -3660,8 +3790,9 @@ void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action) RTW_INFO(FUNC_ADPT_FMT" needed:%d, self_action:%u\n" , FUNC_ADPT_ARG(adapter), needed, self_action); - RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, %u,%u,%u\n" - , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate), MSTATE_AP_NUM(&mstate) + RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, mesh_num:%u, %u,%u,%u\n" + , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate) + , MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate) , u_ch, u_bw, u_offset); if (needed == _TRUE) @@ -3870,6 +4001,7 @@ u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len) return res; } +#ifdef CONFIG_MP_INCLUDED static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); @@ -3894,7 +4026,9 @@ static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id) ret = H2C_REJECTED; goto exit; } +#ifndef RTW_HALMAC rtw_intf_start(padapter); +#endif /* !RTW_HALMAC */ #ifdef RTW_HALMAC /*for New IC*/ MPT_InitializeAdapter(padapter, 1); #endif /* CONFIG_MP_INCLUDED */ @@ -3929,19 +4063,6 @@ static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id) rtw_write8(padapter, 0x66, 0x27); /*Open BT uart Log*/ rtw_write8(padapter, 0xc50, 0x20); /*for RX init Gain*/ #endif -#ifdef CONFIG_RTL8188F - RTW_INFO("Set reg 0x88c, 0x58, 0x00\n"); - rfreg0 = phy_query_rf_reg(padapter, RF_PATH_A, 0x0, 0x1f); - phy_set_bb_reg(padapter, 0x88c, BIT21|BIT20, 0x3); - phy_set_rf_reg(padapter, RF_PATH_A, 0x58, BIT1, 0x1); - phy_set_rf_reg(padapter, RF_PATH_A, 0x0, 0xF001f, 0x2001f); - rtw_msleep_os(200); - phy_set_rf_reg(padapter, RF_PATH_A, 0x0, 0xF001f, 0x30000 | rfreg0); - phy_set_rf_reg(padapter, RF_PATH_A, 0x58, BIT1, 0x0); - phy_set_bb_reg(padapter, 0x88c, BIT21|BIT20, 0x0); - rtw_msleep_os(1000); -#endif - odm_write_dig(&pHalData->odmpriv, 0x20); } else if (mp_cmd_id == MP_STOP) { @@ -3956,7 +4077,9 @@ static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id) ret = H2C_REJECTED; goto exit; } +#ifndef RTW_HALMAC rtw_intf_start(padapter); +#endif /* !RTW_HALMAC */ } if (padapter->mppriv.mode != MP_OFF) { @@ -4030,6 +4153,7 @@ u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags) exit: return res; } +#endif /*CONFIG_MP_INCLUDED*/ #ifdef CONFIG_RTW_CUSTOMER_STR static s32 rtw_customer_str_cmd_hdl(_adapter *adapter, u8 write, const u8 *cstr) @@ -4514,6 +4638,69 @@ void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm) return; } +#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW) +static s32 rtw_req_per_cmd_hdl(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct macid_bmp req_macid_bmp, *macid_bmp; + u8 i, ret = _FAIL; + + macid_bmp = &macid_ctl->if_g[adapter->iface_id]; + _rtw_memcpy(&req_macid_bmp, macid_bmp, sizeof(struct macid_bmp)); + + /* Clear none mesh's macid */ + for (i = 0; i < macid_ctl->num; i++) { + u8 role; + role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]); + if (role != H2C_MSR_ROLE_MESH) + rtw_macid_map_clr(&req_macid_bmp, i); + } + + /* group_macid: always be 0 in NIC, so only pass macid_bitmap.m0 + * rpt_type: 0 includes all info in 1, use 0 for now + * macid_bitmap: pass m0 only for NIC + */ + ret = rtw_hal_set_req_per_rpt_cmd(adapter, 0, 0, req_macid_bmp.m0); + + return ret; +} + +u8 rtw_req_per_cmd(_adapter *adapter) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + res = _FAIL; + goto exit; + } + + parm->ec_id = REQ_PER_CMD_WK_CID; + parm->type = 0; + parm->size = 0; + parm->pbuf = NULL; + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + +exit: + return res; +} +#endif + u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) { int ret = H2C_SUCCESS; @@ -4633,13 +4820,37 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) rtw_hal_fill_h2c_cmd(padapter, pdrvextra_cmd->pbuf[0], pdrvextra_cmd->size - 1, &pdrvextra_cmd->pbuf[1]); break; case MP_CMD_WK_CID: +#ifdef CONFIG_MP_INCLUDED ret = rtw_mp_cmd_hdl(padapter, pdrvextra_cmd->type); +#endif break; #ifdef CONFIG_RTW_CUSTOMER_STR case CUSTOMER_STR_WK_CID: ret = rtw_customer_str_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); break; #endif + +#ifdef CONFIG_RTW_REPEATER_SON + case RSON_SCAN_WK_CID: + rtw_rson_scan_cmd_hdl(padapter, pdrvextra_cmd->type); + break; +#endif + +#ifdef CONFIG_IOCTL_CFG80211 + case MGNT_TX_WK_CID: + ret = rtw_mgnt_tx_handler(padapter, pdrvextra_cmd->pbuf); + break; +#endif /* CONFIG_IOCTL_CFG80211 */ +#ifdef CONFIG_MCC_MODE + case MCC_SET_DURATION_WK_CID: + ret = rtw_set_mcc_duration_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); + break; +#endif /* CONFIG_MCC_MODE */ +#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW) + case REQ_PER_CMD_WK_CID: + ret = rtw_req_per_cmd_hdl(padapter); + break; +#endif default: break; } @@ -4784,7 +4995,7 @@ void rtw_setstaKey_cmdrsp_callback(_adapter *padapter , struct cmd_obj *pcmd) goto exit; } - /* psta->aid = psta->mac_id = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */ + /* psta->cmn.aid = psta->cmn.mac_id = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */ exit: @@ -4806,7 +5017,7 @@ void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) goto exit; } - psta->aid = psta->mac_id = passocsta_rsp->cam_id; + psta->cmn.aid = psta->cmn.mac_id = passocsta_rsp->cam_id; _enter_critical_bh(&pmlmepriv->lock, &irqL); diff --git a/core/rtw_debug.c b/core/rtw_debug.c index 986f8cc..8b33a5f 100644 --- a/core/rtw_debug.c +++ b/core/rtw_debug.c @@ -42,7 +42,7 @@ const char *rtw_log_level_str[] = { void dump_drv_version(void *sel) { RTW_PRINT_SEL(sel, "%s %s\n", DRV_NAME, DRIVERVERSION); -// RTW_PRINT_SEL(sel, "build time: %s %s\n", __DATE__, __TIME__); //EDX +// RTW_PRINT_SEL(sel, "build time: %s %s\n", __DATE__, __TIME__); //EDX } void dump_drv_cfg(void *sel) @@ -129,6 +129,14 @@ void dump_drv_cfg(void *sel) RTW_PRINT_SEL(sel, "CONFIG_RTW_80211R\n"); #endif +#ifdef CONFIG_RTW_NETIF_SG + RTW_PRINT_SEL(sel, "CONFIG_RTW_NETIF_SG\n"); +#endif + +#ifdef CONFIG_RTW_WIFI_HAL + RTW_PRINT_SEL(sel, "CONFIG_RTW_WIFI_HAL\n"); +#endif + #ifdef CONFIG_USB_HCI #ifdef CONFIG_SUPPORT_USB_INT RTW_PRINT_SEL(sel, "CONFIG_SUPPORT_USB_INT\n"); @@ -168,7 +176,17 @@ void dump_drv_cfg(void *sel) #ifdef CONFIG_PCI_HCI #endif + RTW_PRINT_SEL(sel, "\n=== XMIT-INFO ===\n"); + RTW_PRINT_SEL(sel, "NR_XMITFRAME = %d\n", NR_XMITFRAME); + RTW_PRINT_SEL(sel, "NR_XMITBUFF = %d\n", NR_XMITBUFF); RTW_PRINT_SEL(sel, "MAX_XMITBUF_SZ = %d\n", MAX_XMITBUF_SZ); + RTW_PRINT_SEL(sel, "NR_XMIT_EXTBUFF = %d\n", NR_XMIT_EXTBUFF); + RTW_PRINT_SEL(sel, "MAX_XMIT_EXTBUF_SZ = %d\n", MAX_XMIT_EXTBUF_SZ); + RTW_PRINT_SEL(sel, "MAX_CMDBUF_SZ = %d\n", MAX_CMDBUF_SZ); + + RTW_PRINT_SEL(sel, "\n=== RECV-INFO ===\n"); + RTW_PRINT_SEL(sel, "NR_RECVFRAME = %d\n", NR_RECVFRAME); + RTW_PRINT_SEL(sel, "NR_RECVBUFF = %d\n", NR_RECVBUFF); RTW_PRINT_SEL(sel, "MAX_RECVBUF_SZ = %d\n", MAX_RECVBUF_SZ); } @@ -331,13 +349,13 @@ void rf_reg_dump(void *sel, _adapter *adapter) } } -void rtw_sink_rtp_seq_dbg(_adapter *adapter, _pkt *pkt) +void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos) { struct recv_priv *precvpriv = &(adapter->recvpriv); if (precvpriv->sink_udpport > 0) { - if (*((u16 *)((pkt->data) + 0x24)) == cpu_to_be16(precvpriv->sink_udpport)) { + if (*((u16 *)(ehdr_pos + 0x24)) == cpu_to_be16(precvpriv->sink_udpport)) { precvpriv->pre_rtp_rxseq = precvpriv->cur_rtp_rxseq; - precvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16 *)((pkt->data) + 0x2C))); + precvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16 *)(ehdr_pos + 0x2C))); if (precvpriv->pre_rtp_rxseq + 1 != precvpriv->cur_rtp_rxseq) RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvpriv->pre_rtp_rxseq, precvpriv->cur_rtp_rxseq); } @@ -478,11 +496,12 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) , u_ch, u_bw, u_offset ); - RTW_PRINT_SEL(sel, "%55s %3u,%u,%u\n" + RTW_PRINT_SEL(sel, "%55s %3u,%u,%u offch_state:%d\n" , "oper:" , dvobj->oper_channel , dvobj->oper_bwmode , dvobj->oper_ch_offset + , rfctl->offch_state ); #ifdef CONFIG_DFS_MASTER @@ -506,13 +525,13 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) for (i = 0; i < dvobj->iface_nums; i++) { if (!dvobj->padapters[i]) continue; - if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE) + if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE) && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE)) break; } if (i >= dvobj->iface_nums) { - RTW_PRINT_SEL(sel, "DFS master enable without AP mode???"); + RTW_PRINT_SEL(sel, "DFS master enable without AP/Mesh mode???"); goto end_dfs_master; } @@ -739,12 +758,12 @@ int proc_get_rx_stat(struct seq_file *m, void *v) if (pstats == NULL) continue; - if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(adapter), 6) != _TRUE)) { - RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(psta->hwaddr)); - RTW_PRINT_SEL(m, "data_rx_cnt :\t%llu\n", pstats->rx_data_pkts - pstats->rx_data_last_pkts); - pstats->rx_data_last_pkts = pstats->rx_data_pkts; + if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), 6) != _TRUE)) { + RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); + RTW_PRINT_SEL(m, "data_rx_cnt :\t%llu\n", sta_rx_data_uc_pkts(psta) - pstats->last_rx_data_uc_pkts); + pstats->last_rx_data_uc_pkts = sta_rx_data_uc_pkts(psta); RTW_PRINT_SEL(m, "duplicate_cnt :\t%u\n", pstats->duplicate_cnt); pstats->duplicate_cnt = 0; RTW_PRINT_SEL(m, "rx_per_rate_cnt :\n"); @@ -769,9 +788,12 @@ int proc_get_tx_stat(struct seq_file *m, void *v) _list *plist, *phead; struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct sta_info *psta = NULL, *sta_rec[NUM_STA]; + struct sta_info *psta = NULL; + u8 sta_mac[NUM_STA][ETH_ALEN] = {{0}}; + uint mac_id[NUM_STA]; struct stainfo_stats *pstats = NULL; struct sta_priv *pstapriv = &(adapter->stapriv); + struct sta_priv *pstapriv_primary = &(GET_PRIMARY_ADAPTER(adapter))->stapriv; u32 i, macid_rec_idx = 0; u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; @@ -779,40 +801,54 @@ int proc_get_tx_stat(struct seq_file *m, void *v) _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); for (i = 0; i < NUM_STA; i++) { - sta_rec[i] = NULL; phead = &(pstapriv->sta_hash[i]); plist = get_next(phead); while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); plist = get_next(plist); - if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(adapter), 6) != _TRUE)) { - sta_rec[macid_rec_idx++] = psta; + if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), 6) != _TRUE)) { + _rtw_memcpy(&sta_mac[macid_rec_idx][0], psta->cmn.mac_addr, ETH_ALEN); + mac_id[macid_rec_idx] = psta->cmn.mac_id; + macid_rec_idx++; } } } _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); for (i = 0; i < macid_rec_idx; i++) { - pstats = &(sta_rec[i]->sta_stats); - if (pstats == NULL) - continue; - pstapriv->c2h_sta = sta_rec[i]; - rtw_hal_reqtxrpt(adapter, sta_rec[i]->mac_id); + _rtw_memcpy(pstapriv_primary->c2h_sta_mac, &sta_mac[i][0], ETH_ALEN); + pstapriv_primary->c2h_adapter_id = adapter->iface_id; rtw_sctx_init(&gotc2h, 60); - pstapriv->gotc2h = &gotc2h; + pstapriv_primary->gotc2h = &gotc2h; + rtw_hal_reqtxrpt(adapter, mac_id[i]); if (rtw_sctx_wait(&gotc2h, __func__)) { - RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(sta_rec[i]->hwaddr)); - RTW_PRINT_SEL(m, "data_sent_cnt :\t%u\n", pstats->tx_ok_cnt + pstats->tx_fail_cnt); - RTW_PRINT_SEL(m, "success_cnt :\t%u\n", pstats->tx_ok_cnt); - RTW_PRINT_SEL(m, "failure_cnt :\t%u\n", pstats->tx_fail_cnt); - RTW_PRINT_SEL(m, "retry_cnt :\t%u\n\n", pstats->tx_retry_cnt); + psta = rtw_get_stainfo(pstapriv, &sta_mac[i][0]); + if(psta) { + pstats = &psta->sta_stats; +#ifndef ROKU_PRIVATE + RTW_PRINT_SEL(m, "data_sent_cnt :\t%u\n", pstats->tx_ok_cnt + pstats->tx_fail_cnt); + RTW_PRINT_SEL(m, "success_cnt :\t%u\n", pstats->tx_ok_cnt); + RTW_PRINT_SEL(m, "failure_cnt :\t%u\n", pstats->tx_fail_cnt); + RTW_PRINT_SEL(m, "retry_cnt :\t%u\n\n", pstats->tx_retry_cnt); +#else + RTW_PRINT_SEL(m, "MAC: " MAC_FMT " sent: %u fail: %u retry: %u\n", + MAC_ARG(&sta_mac[i][0]), pstats->tx_ok_cnt, pstats->tx_fail_cnt, pstats->tx_retry_cnt); +#endif /* ROKU_PRIVATE */ + + } else + RTW_PRINT_SEL(m, "STA is gone\n"); } else { + //to avoid c2h modify counters + pstapriv_primary->gotc2h = NULL; + _rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN); + pstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER; RTW_PRINT_SEL(m, "Warming : Query timeout, operation abort!!\n"); - RTW_PRINT_SEL(m, "\n"); - pstapriv->c2h_sta = NULL; break; } + pstapriv_primary->gotc2h = NULL; + _rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN); + pstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER; } return 0; } @@ -1016,7 +1052,7 @@ ssize_t proc_set_ft_flags(struct file *file, const char __user *buffer, size_t c int num = sscanf(tmp, "%hhx", &flags); if (num == 1) - adapter->mlmepriv.ftpriv.ft_flags = flags; + adapter->mlmepriv.ft_roam.ft_flags = flags; } return count; @@ -1028,7 +1064,7 @@ int proc_get_ft_flags(struct seq_file *m, void *v) struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - RTW_PRINT_SEL(m, "0x%02x\n", adapter->mlmepriv.ftpriv.ft_flags); + RTW_PRINT_SEL(m, "0x%02x\n", adapter->mlmepriv.ft_roam.ft_flags); return 0; } @@ -1293,6 +1329,52 @@ ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, s #endif /* CONFIG_SCAN_BACKOP */ +#ifdef CONFIG_RTW_REPEATER_SON +int proc_get_rson_data(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char rson_data_str[256]; + + rtw_rson_get_property_str(padapter, rson_data_str); + RTW_PRINT_SEL(m, "%s\n", rson_data_str); + return 0; +} + +ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + char tmp[64] = {0}; + int num; + u8 field[10], value[64]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + num = sscanf(tmp, "%s %s", field, value); + if (num != 2) { + RTW_INFO("Invalid format : echo > son_data\n"); + return count; + } + RTW_INFO("field=%s value=%s\n", field, value); + num = rtw_rson_set_property(padapter, field, value); + if (num != 1) { + RTW_INFO("Invalid field(%s) or value(%s)\n", field, value); + return count; + } + } + return count; +} +#endif /*CONFIG_RTW_REPEATER_SON*/ + int proc_get_survey_info(struct seq_file *m, void *v) { _irqL irqL; @@ -1310,16 +1392,25 @@ int proc_get_survey_info(struct seq_file *m, void *v) char flag_str[64]; int ielen = 0; u32 wpsielen = 0; +#ifdef CONFIG_RTW_MESH + const char *ssid_title_str = "ssid/mesh_id"; +#else + const char *ssid_title_str = "ssid"; +#endif _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); phead = get_list_head(queue); if (!phead) - return 0; + goto _exit; plist = get_next(phead); if (!plist) - return 0; + goto _exit; - RTW_PRINT_SEL(m, "%5s %-17s %3s %-3s %-4s %-4s %5s %32s %32s\n", "index", "bssid", "ch", "RSSI", "SdBm", "Noise", "age", "flag", "ssid"); +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_show_survey_info(m, plist, phead); +#else + + RTW_PRINT_SEL(m, "%5s %-17s %3s %-3s %-4s %-4s %5s %32s %32s\n", "index", "bssid", "ch", "RSSI", "SdBm", "Noise", "age", "flag", ssid_title_str); while (1) { if (rtw_end_of_queue_search(phead, plist) == _TRUE) break; @@ -1335,8 +1426,9 @@ int proc_get_survey_info(struct seq_file *m, void *v) notify_signal = translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);/* dbm */ } -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &(pnetwork->network.Configuration.DSConfig), &(notify_noise)); +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + if (IS_NM_ENABLE(padapter)) + notify_noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig); #endif ie_wpa = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12); @@ -1350,21 +1442,25 @@ int proc_get_survey_info(struct seq_file *m, void *v) (ie_wpa2) ? "[WPA2]" : "", (!ie_wpa && !ie_wpa && ie_cap & BIT(4)) ? "[WEP]" : "", (ie_wps) ? "[WPS]" : "", - (pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? "[IBSS]" : "", + (pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? "[IBSS]" : + (pnetwork->network.InfrastructureMode == Ndis802_11_mesh) ? "[MESH]" : "", (ie_cap & BIT(0)) ? "[ESS]" : "", (ie_p2p) ? "[P2P]" : ""); RTW_PRINT_SEL(m, "%5d "MAC_FMT" %3d %3d %4d %4d %5d %32s %32s\n", - ++index, - MAC_ARG(pnetwork->network.MacAddress), - pnetwork->network.Configuration.DSConfig, - (int)pnetwork->network.Rssi, - notify_signal, - notify_noise, - rtw_get_passing_time_ms((u32)pnetwork->last_scanned), - flag_str, - pnetwork->network.Ssid.Ssid); + ++index, + MAC_ARG(pnetwork->network.MacAddress), + pnetwork->network.Configuration.DSConfig, + (int)pnetwork->network.Rssi, + notify_signal, + notify_noise, + rtw_get_passing_time_ms(pnetwork->last_scanned), + flag_str, + pnetwork->network.InfrastructureMode == Ndis802_11_mesh ? pnetwork->network.mesh_id.Ssid : pnetwork->network.Ssid.Ssid + ); plist = get_next(plist); } +#endif +_exit: _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); return 0; @@ -1424,7 +1520,7 @@ ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_ goto cancel_ps_deny; } #endif - _status = rtw_set_802_11_bssid_list_scan(padapter, NULL, 0, NULL, 0); + _status = rtw_set_802_11_bssid_list_scan(padapter, NULL); cancel_ps_deny: rtw_ps_deny_cancel(padapter, PS_DENY_SCAN); @@ -1444,17 +1540,16 @@ int proc_get_ap_info(struct seq_file *m, void *v) psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); if (psta) { - int i; - struct recv_reorder_ctrl *preorder_ctrl; - RTW_PRINT_SEL(m, "SSID=%s\n", cur_network->network.Ssid.Ssid); - RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); RTW_PRINT_SEL(m, "cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); RTW_PRINT_SEL(m, "wireless_mode=0x%x, rtsen=%d, cts2slef=%d\n", psta->wireless_mode, psta->rtsen, psta->cts2self); - RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); + RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", + psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id); #ifdef CONFIG_80211N_HT RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); - RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n" + , psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x, beamform_cap=0x%x\n", psta->htpriv.ldpc_cap, psta->htpriv.stbc_cap, psta->htpriv.beamform_cap); @@ -1464,7 +1559,6 @@ int proc_get_ap_info(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap); RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len); #endif - sta_rx_reorder_ctl_dump(m, psta); } else RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); @@ -1476,8 +1570,7 @@ ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct recv_priv *precvpriv = &padapter->recvpriv; char cmd[32] = {0}; u8 cnt = 0; @@ -1490,12 +1583,13 @@ ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t int num = sscanf(cmd, "%hhx", &cnt); if (0 == cnt) { - pdbgpriv->dbg_rx_ampdu_drop_count = 0; - pdbgpriv->dbg_rx_ampdu_forced_indicate_count = 0; - pdbgpriv->dbg_rx_ampdu_loss_count = 0; - pdbgpriv->dbg_rx_dup_mgt_frame_drop_count = 0; - pdbgpriv->dbg_rx_ampdu_window_shift_cnt = 0; - pdbgpriv->dbg_rx_conflic_mac_addr_cnt = 0; + precvpriv->dbg_rx_ampdu_drop_count = 0; + precvpriv->dbg_rx_ampdu_forced_indicate_count = 0; + precvpriv->dbg_rx_ampdu_loss_count = 0; + precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0; + precvpriv->dbg_rx_ampdu_window_shift_cnt = 0; + precvpriv->dbg_rx_conflic_mac_addr_cnt = 0; + precvpriv->dbg_rx_drop_count = 0; } } @@ -1509,9 +1603,15 @@ int proc_get_trx_info(struct seq_file *m, void *v) _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct recv_priv *precvpriv = &padapter->recvpriv; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; struct hw_xmit *phwxmit; + u16 vo_params[4], vi_params[4], be_params[4], bk_params[4]; + + padapter->hal_func.read_wmmedca_reg(padapter, vo_params, vi_params, be_params, bk_params); + + RTW_PRINT_SEL(m, "wmm_edca_vo, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vo_params[0], vo_params[1], vo_params[2], vo_params[3]); + RTW_PRINT_SEL(m, "wmm_edca_vi, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vi_params[0], vi_params[1], vi_params[2], vi_params[3]); + RTW_PRINT_SEL(m, "wmm_edca_be, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", be_params[0], be_params[1], be_params[2], be_params[3]); + RTW_PRINT_SEL(m, "wmm_edca_bk, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", bk_params[0], bk_params[1], bk_params[2], bk_params[3]); dump_os_queue(m, padapter); @@ -1527,65 +1627,32 @@ int proc_get_trx_info(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "%d, hwq.accnt=%d\n", i, phwxmit->accnt); } + rtw_hal_get_hwreg(padapter, HW_VAR_DUMP_MAC_TXFIFO, (u8 *)m); + #ifdef CONFIG_USB_HCI RTW_PRINT_SEL(m, "rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt))); #endif + dump_rx_bh_tk(m, &GET_PRIMARY_ADAPTER(padapter)->recvpriv); + /* Folowing are RX info */ + RTW_PRINT_SEL(m, "RX: Count of Packets dropped by Driver: %llu\n", (unsigned long long)precvpriv->dbg_rx_drop_count); /* Counts of packets whose seq_num is less than preorder_ctrl->indicate_seq, Ex delay, retransmission, redundant packets and so on */ - RTW_PRINT_SEL(m, "Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_ampdu_drop_count); + RTW_PRINT_SEL(m, "Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_drop_count); /* How many times the Rx Reorder Timer is triggered. */ - RTW_PRINT_SEL(m, "Rx: Reorder Time-out Trigger Counts: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_ampdu_forced_indicate_count); + RTW_PRINT_SEL(m, "Rx: Reorder Time-out Trigger Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_forced_indicate_count); /* Total counts of packets loss */ - RTW_PRINT_SEL(m, "Rx: Packet Loss Counts: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_ampdu_loss_count); - RTW_PRINT_SEL(m, "Rx: Duplicate Management Frame Drop Count: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_dup_mgt_frame_drop_count); - RTW_PRINT_SEL(m, "Rx: AMPDU BA window shift Count: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_ampdu_window_shift_cnt); + RTW_PRINT_SEL(m, "Rx: Packet Loss Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_loss_count); + RTW_PRINT_SEL(m, "Rx: Duplicate Management Frame Drop Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_dup_mgt_frame_drop_count); + RTW_PRINT_SEL(m, "Rx: AMPDU BA window shift Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_window_shift_cnt); /*The same mac addr counts*/ - RTW_PRINT_SEL(m, "Rx: Conflict MAC Address Frames Count: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_conflic_mac_addr_cnt); - return 0; -} - -int proc_get_dis_pwt(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u8 dis_pwt = 0; - rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DIS_PWT, &(dis_pwt)); - RTW_PRINT_SEL(m, " Tx Power training mode:%s\n", (dis_pwt == _TRUE) ? "Disable" : "Enable"); + RTW_PRINT_SEL(m, "Rx: Conflict MAC Address Frames Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_conflic_mac_addr_cnt); return 0; } -ssize_t proc_set_dis_pwt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[4] = {0}; - u8 dis_pwt = 0; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx", &dis_pwt); - RTW_INFO("Set Tx Power training mode:%s\n", (dis_pwt == _TRUE) ? "Disable" : "Enable"); - - if (num >= 1) - rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DIS_PWT, &(dis_pwt)); - } - - return count; - -} int proc_get_rate_ctl(struct seq_file *m, void *v) { struct net_device *dev = m->private; - int i; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); u8 data_rate = 0, sgi = 0, data_fb = 0; @@ -1609,6 +1676,7 @@ ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t c { struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); char tmp[32]; u8 fix_rate; u8 data_fb; @@ -1629,6 +1697,11 @@ ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t c u8 fix_rate_ori = adapter->fix_rate; adapter->fix_rate = fix_rate; + if (fix_rate == 0xFF) + hal_data->ForcedDataRate = 0; + else + hal_data->ForcedDataRate = hw_rate_to_m_rate(fix_rate & 0x7F); + if (adapter->fix_bw != 0xFF && fix_rate_ori != fix_rate) rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter)); } @@ -1639,6 +1712,53 @@ ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t c return count; } +#ifdef CONFIG_AP_MODE +int proc_get_bmc_tx_rate(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct sta_info *psta = NULL; + + if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter)) { + RTW_PRINT_SEL(m, "[ERROR] Not in SoftAP/Mesh mode !!\n"); + return 0; + } + + RTW_PRINT_SEL(m, " BMC Tx rate - %s\n", MGN_RATE_STR(adapter->bmc_tx_rate)); + return 0; +} + +ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + char tmp[32]; + u8 bmc_tx_rate; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &bmc_tx_rate); + + if (num >= 1) + /*adapter->bmc_tx_rate = hw_rate_to_m_rate(bmc_tx_rate);*/ + adapter->bmc_tx_rate = bmc_tx_rate; + } + + return count; +} +#endif /*CONFIG_AP_MODE*/ + + int proc_get_tx_power_offset(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -1845,52 +1965,6 @@ ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *bu return count; } -#ifdef CONFIG_DFS_MASTER -int proc_get_dfs_master_test_case(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - - RTW_PRINT_SEL(m, "%-24s %-19s\n", "radar_detect_trigger_non", "choose_dfs_ch_first"); - RTW_PRINT_SEL(m, "%24hhu %19hhu\n" - , rfctl->dbg_dfs_master_radar_detect_trigger_non - , rfctl->dbg_dfs_master_choose_dfs_ch_first - ); - - return 0; -} - -ssize_t proc_set_dfs_master_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - char tmp[32]; - u8 radar_detect_trigger_non; - u8 choose_dfs_ch_first; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hhu %hhu", &radar_detect_trigger_non, &choose_dfs_ch_first); - - if (num >= 1) - rfctl->dbg_dfs_master_radar_detect_trigger_non = radar_detect_trigger_non; - if (num >= 2) - rfctl->dbg_dfs_master_choose_dfs_ch_first = choose_dfs_ch_first; - } - - return count; -} -#endif /* CONFIG_DFS_MASTER */ - static u32 g_wait_hiq_empty_ms = 0; u32 rtw_get_wait_hiq_empty_ms(void) @@ -1919,7 +1993,7 @@ ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, si return count; } -static u32 sta_linking_test_start_time = 0; +static systime sta_linking_test_start_time = 0; static u32 sta_linking_test_wait_ms = 0; static u8 sta_linking_test_force_fail = 0; @@ -1966,7 +2040,7 @@ ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, return count; } -int proc_get_suspend_resume_info(struct seq_file *m, void *v) +int proc_get_ps_dbg_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -2001,9 +2075,39 @@ int proc_get_suspend_resume_info(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "dbg_rpwm_toogle_cnt=%d\n", pdbgpriv->dbg_rpwm_toogle_cnt); RTW_PRINT_SEL(m, "dbg_rpwm_timeout_fail_cnt=%d\n", pdbgpriv->dbg_rpwm_timeout_fail_cnt); RTW_PRINT_SEL(m, "dbg_sreset_cnt=%d\n", pdbgpriv->dbg_sreset_cnt); + RTW_PRINT_SEL(m, "dbg_fw_mem_dl_error_cnt=%d\n", pdbgpriv->dbg_fw_mem_dl_error_cnt); return 0; } +ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter->dvobj; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; + char tmp[32]; + u8 ps_dbg_cmd_id; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &ps_dbg_cmd_id); + + if (ps_dbg_cmd_id == 1) /*Clean all*/ + _rtw_memset(pdbgpriv, 0, sizeof(struct debug_priv)); + + } + + return count; +} + #ifdef CONFIG_DBG_COUNTER @@ -2350,6 +2454,7 @@ int proc_get_rx_signal(struct seq_file *m, void *v) /* RTW_PRINT_SEL(m, "rxpwdb:%d\n", padapter->recvpriv.rxpwdb); */ RTW_PRINT_SEL(m, "signal_strength:%u\n", padapter->recvpriv.signal_strength); RTW_PRINT_SEL(m, "signal_qual:%u\n", padapter->recvpriv.signal_qual); +#ifdef CONFIG_MP_INCLUDED if (padapter->registrypriv.mp_mode == 1) { if (padapter->mppriv.antenna_rx == ANTENNA_A) RTW_PRINT_SEL(m, "Antenna: A\n"); @@ -2369,9 +2474,7 @@ int proc_get_rx_signal(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "Antenna: __\n"); return 0; } - - rtw_get_noise(padapter); - RTW_PRINT_SEL(m, "noise:%d\n", padapter->recvpriv.noise); +#endif #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA rtw_odm_get_perpkt_rssi(m, padapter); rtw_get_raw_rssi_info(m, padapter); @@ -3322,7 +3425,8 @@ int proc_get_all_sta_info(struct seq_file *m, void *v) int i; _list *plist, *phead; - RTW_PRINT_SEL(m, "sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap); + RTW_MAP_DUMP_SEL(m, "sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); + RTW_MAP_DUMP_SEL(m, "tim_bitmap=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); @@ -3335,19 +3439,26 @@ int proc_get_all_sta_info(struct seq_file *m, void *v) plist = get_next(plist); - /* if(extra_arg == psta->aid) */ + /* if(extra_arg == psta->cmn.aid) */ { RTW_PRINT_SEL(m, "==============================\n"); - RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); RTW_PRINT_SEL(m, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); - RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); + RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", + psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id); #ifdef CONFIG_80211N_HT RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); - RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n" + , psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); RTW_PRINT_SEL(m, "tx_amsdu_enable = %d\n", psta->htpriv.tx_amsdu_enable); RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); #endif /* CONFIG_80211N_HT */ +#ifdef CONFIG_80211AC_VHT + RTW_PRINT_SEL(m, "vht_en=%d, vht_sgi_80m=%d\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m); + RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap); + RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len); +#endif RTW_PRINT_SEL(m, "sleepq_len=%d\n", psta->sleepq_len); RTW_PRINT_SEL(m, "sta_xmitpriv.vo_q_qcnt=%d\n", psta->sta_xmitpriv.vo_q.qcnt); RTW_PRINT_SEL(m, "sta_xmitpriv.vi_q_qcnt=%d\n", psta->sta_xmitpriv.vi_q.qcnt); @@ -3367,12 +3478,21 @@ int proc_get_all_sta_info(struct seq_file *m, void *v) #ifdef CONFIG_TDLS RTW_PRINT_SEL(m, "tdls_sta_state=0x%08x\n", psta->tdls_sta_state); RTW_PRINT_SEL(m, "PeerKey_Lifetime=%d\n", psta->TDLS_PeerKey_Lifetime); - RTW_PRINT_SEL(m, "rx_data_pkts=%llu\n", psta->sta_stats.rx_data_pkts); - RTW_PRINT_SEL(m, "rx_bytes=%llu\n", psta->sta_stats.rx_bytes); - RTW_PRINT_SEL(m, "tx_data_pkts=%llu\n", psta->sta_stats.tx_pkts); - RTW_PRINT_SEL(m, "tx_bytes=%llu\n", psta->sta_stats.tx_bytes); #endif /* CONFIG_TDLS */ + RTW_PRINT_SEL(m, "rx_data_uc_pkts=%llu\n", sta_rx_data_uc_pkts(psta)); + RTW_PRINT_SEL(m, "rx_data_mc_pkts=%llu\n", psta->sta_stats.rx_data_mc_pkts); + RTW_PRINT_SEL(m, "rx_data_bc_pkts=%llu\n", psta->sta_stats.rx_data_bc_pkts); + RTW_PRINT_SEL(m, "rx_uc_bytes=%llu\n", sta_rx_uc_bytes(psta)); + RTW_PRINT_SEL(m, "rx_mc_bytes=%llu\n", psta->sta_stats.rx_mc_bytes); + RTW_PRINT_SEL(m, "rx_bc_bytes=%llu\n", psta->sta_stats.rx_bc_bytes); + RTW_PRINT_SEL(m, "rx_avg_tp =%d (Bps)\n", psta->cmn.rx_moving_average_tp); + RTW_PRINT_SEL(m, "tx_data_pkts=%llu\n", psta->sta_stats.tx_pkts); + RTW_PRINT_SEL(m, "tx_bytes=%llu\n", psta->sta_stats.tx_bytes); + RTW_PRINT_SEL(m, "tx_avg_tp =%d (MBps)\n", psta->cmn.tx_moving_average_tp); +#ifdef CONFIG_RTW_80211K + RTW_PRINT_SEL(m, "rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(psta->rm_en_cap)); +#endif dump_st_ctl(m, &psta->st_ctl); if (STA_OP_WFD_MODE(psta)) @@ -3663,8 +3783,21 @@ int proc_get_sreset(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + if (psrtpriv->dbg_sreset_ctrl == _TRUE) { + RTW_PRINT_SEL(m, "self_dect_tx_cnt:%llu\n", psrtpriv->self_dect_tx_cnt); + RTW_PRINT_SEL(m, "self_dect_rx_cnt:%llu\n", psrtpriv->self_dect_rx_cnt); + RTW_PRINT_SEL(m, "self_dect_fw_cnt:%llu\n", psrtpriv->self_dect_fw_cnt); + RTW_PRINT_SEL(m, "tx_dma_status_cnt:%llu\n", psrtpriv->tx_dma_status_cnt); + RTW_PRINT_SEL(m, "rx_dma_status_cnt:%llu\n", psrtpriv->rx_dma_status_cnt); + RTW_PRINT_SEL(m, "self_dect_case:%d\n", psrtpriv->self_dect_case); + RTW_PRINT_SEL(m, "dbg_sreset_cnt:%d\n", pdbgpriv->dbg_sreset_cnt); + } return 0; } @@ -3672,6 +3805,8 @@ ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t cou { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; char tmp[32]; s32 trigger_point; @@ -3689,6 +3824,8 @@ ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t cou if (trigger_point == SRESET_TGP_NULL) rtw_hal_sreset_reset(padapter); + else if (trigger_point == SRESET_TGP_INFO) + psrtpriv->dbg_sreset_ctrl = _TRUE; else sreset_set_trigger_point(padapter, trigger_point); } @@ -3710,6 +3847,7 @@ int proc_get_pci_aspm(struct seq_file *m, void *v) u8 tmp8 = 0; u16 tmp16 = 0; u32 tmp32 = 0; + u8 l1_idle = 0; RTW_PRINT_SEL(m, "***** ASPM Capability *****\n"); @@ -3740,6 +3878,7 @@ int proc_get_pci_aspm(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp8 & BIT4) ? "Enable" : "Disable"); tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f); + l1_idle = tmp8 & 0x38; RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp8&BIT7) ? "Enable" : "Disable"); tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); @@ -3748,6 +3887,10 @@ int proc_get_pci_aspm(struct seq_file *m, void *v) tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718); RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", (tmp8 & BIT5) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "********* MISC **********\n"); + RTW_PRINT_SEL(m, "ASPM L1 Idel Time: 0x%x\n", l1_idle>>3); + RTW_PRINT_SEL(m, "*************************\n"); + return 0; } @@ -3815,11 +3958,12 @@ int proc_get_tx_ring(struct seq_file *m, void *v) for (j = 0; j < pxmitpriv->txringcount[i]; j++) { #ifdef CONFIG_TRX_BD_ARCH struct tx_buf_desc *entry = &tx_ring->buf_desc[j]; + RTW_PRINT_SEL(m, " buf_desc[%03d]: %p\n", j, entry); #else struct tx_desc *entry = &tx_ring->desc[j]; + RTW_PRINT_SEL(m, " desc[%03d]: %p\n", j, entry); #endif - RTW_PRINT_SEL(m, " desc[%03d]: %p\n", j, entry); for (k = 0; k < sizeof(*entry) / 4; k++) { if ((k % 4) == 0) RTW_PRINT_SEL(m, " 0x%03x", k); @@ -3835,52 +3979,198 @@ int proc_get_tx_ring(struct seq_file *m, void *v) return 0; } -#endif -#ifdef CONFIG_WOWLAN -int proc_get_pattern_info(struct seq_file *m, void *v) +#ifdef DBG_TXBD_DESC_DUMP +int proc_get_tx_ring_ext(struct seq_file *m, void *v) { + _irqL irqL; struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct registry_priv *pregistrypriv = &padapter->registrypriv; - u8 pattern_num = 0, val8; - char str_1[128]; - char *p_str; - int i = 0 , j = 0, k = 0; - int len = 0, max_len = 0, total = 0; - - p_str = str_1; - max_len = sizeof(str_1); + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_tx_desc_backup *pbuf; + int i, j, k, idx; - total = pwrpriv->wowlan_pattern_idx; + RTW_PRINT_SEL(m, "<<<< tx ring ext dump settings >>>>\n"); + RTW_PRINT_SEL(m, " - backup frame num: %d\n", TX_BAK_FRMAE_CNT); + RTW_PRINT_SEL(m, " - backup max. desc size: %d bytes\n", TX_BAK_DESC_LEN); + RTW_PRINT_SEL(m, " - backup data size: %d bytes\n\n", TX_BAK_DATA_LEN); - rtw_set_default_pattern(padapter); + if (!pxmitpriv->dump_txbd_desc) { + RTW_PRINT_SEL(m, "Dump function is disabled.\n"); + return 0; + } - /*show pattern*/ - RTW_PRINT_SEL(m, "\n======[Pattern Info.]======\n"); - RTW_PRINT_SEL(m, "pattern number: %d\n", total); - RTW_PRINT_SEL(m, "support default patterns: %c\n", - (pregistrypriv->default_patterns_en) ? 'Y' : 'N'); + _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); + for (i = 0; i < HW_QUEUE_ENTRY; i++) { + struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i]; - for (k = 0; k < total ; k++) { - RTW_PRINT_SEL(m, "\npattern idx: %d\n", k); - RTW_PRINT_SEL(m, "pattern content:\n"); + idx = rtw_get_tx_desc_backup(padapter, i, &pbuf); - p_str = str_1; - max_len = sizeof(str_1); - for (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) { - _rtw_memset(p_str, 0, max_len); - len = 0; - for (j = 0 ; j < 8 ; j++) { - val8 = pwrpriv->patterns[k].content[i * 8 + j]; - len += snprintf(p_str + len, max_len - len, - "%02x ", val8); - } - RTW_PRINT_SEL(m, "%s\n", p_str); + RTW_PRINT_SEL(m, "Tx ring[%d]", i); + switch (i) { + case 0: + RTW_PRINT_SEL(m, " (VO)\n"); + break; + case 1: + RTW_PRINT_SEL(m, " (VI)\n"); + break; + case 2: + RTW_PRINT_SEL(m, " (BE)\n"); + break; + case 3: + RTW_PRINT_SEL(m, " (BK)\n"); + break; + case 4: + RTW_PRINT_SEL(m, " (BCN)\n"); + break; + case 5: + RTW_PRINT_SEL(m, " (MGT)\n"); + break; + case 6: + RTW_PRINT_SEL(m, " (HIGH)\n"); + break; + case 7: + RTW_PRINT_SEL(m, " (TXCMD)\n"); + break; + default: + RTW_PRINT_SEL(m, " (?)\n"); + break; } - RTW_PRINT_SEL(m, "\npattern mask:\n"); - for (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) { + + RTW_PRINT_SEL(m, " Entries: %d\n", TX_BAK_FRMAE_CNT); + RTW_PRINT_SEL(m, " Last idx: %d\n", idx); + + for (j = 0; j < TX_BAK_FRMAE_CNT; j++) { + RTW_PRINT_SEL(m, " desc[%03d]:\n", j); + + for (k = 0; k < (pbuf->tx_desc_size) / 4; k++) { + if ((k % 4) == 0) + RTW_PRINT_SEL(m, " 0x%03x", k); + + RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_desc)[k]); + + if ((k % 4) == 3) + RTW_PRINT_SEL(m, "\n"); + } + +#if 1 /* data dump */ + if (pbuf->tx_desc_size) { + RTW_PRINT_SEL(m, " data[%03d]:\n", j); + + for (k = 0; k < (TX_BAK_DATA_LEN) / 4; k++) { + if ((k % 4) == 0) + RTW_PRINT_SEL(m, " 0x%03x", k); + + RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_data_hdr)[k]); + + if ((k % 4) == 3) + RTW_PRINT_SEL(m, "\n"); + } + RTW_PRINT_SEL(m, "\n"); + } +#endif + + RTW_PRINT_SEL(m, " R/W pointer: %d/%d\n", pbuf->tx_bak_rp, pbuf->tx_bak_wp); + + pbuf = pbuf + 1; + } + RTW_PRINT_SEL(m, "\n"); + } + _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); + + return 0; +} + +ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + _irqL irqL; + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + char tmp[32]; + u32 reset = 0; + u32 dump = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%u %u", &dump, &reset); + + if (num != 2) { + RTW_INFO("invalid parameter!\n"); + return count; + } + + _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); + pxmitpriv->dump_txbd_desc = (BOOLEAN) dump; + + if (reset == 1) + rtw_tx_desc_backup_reset(); + + _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); + + } + + return count; +} + +#endif + +#endif + +#ifdef CONFIG_WOWLAN +int proc_get_pattern_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct registry_priv *pregistrypriv = &padapter->registrypriv; + u8 pattern_num = 0, val8; + char str_1[128]; + char *p_str; + int i = 0 , j = 0, k = 0; + int len = 0, max_len = 0, total = 0; + + p_str = str_1; + max_len = sizeof(str_1); + + total = pwrpriv->wowlan_pattern_idx; + + rtw_set_default_pattern(padapter); + + /*show pattern*/ + RTW_PRINT_SEL(m, "\n======[Pattern Info.]======\n"); + RTW_PRINT_SEL(m, "pattern number: %d\n", total); + RTW_PRINT_SEL(m, "support default patterns: %c\n", + (pwrpriv->default_patterns_en) ? 'Y' : 'N'); + + for (k = 0; k < total ; k++) { + RTW_PRINT_SEL(m, "\npattern idx: %d\n", k); + RTW_PRINT_SEL(m, "pattern content:\n"); + + p_str = str_1; + max_len = sizeof(str_1); + for (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) { + _rtw_memset(p_str, 0, max_len); + len = 0; + for (j = 0 ; j < 8 ; j++) { + val8 = pwrpriv->patterns[k].content[i * 8 + j]; + len += snprintf(p_str + len, max_len - len, + "%02x ", val8); + } + RTW_PRINT_SEL(m, "%s\n", p_str); + } + RTW_PRINT_SEL(m, "\npattern mask:\n"); + for (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) { _rtw_memset(p_str, 0, max_len); len = 0; for (j = 0 ; j < 8 ; j++) { @@ -3898,6 +4188,7 @@ int proc_get_pattern_info(struct seq_file *m, void *v) return 0; } + ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { @@ -3945,6 +4236,62 @@ ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer, return count; } +int proc_get_wakeup_event(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *registry_par = &padapter->registrypriv; + + RTW_PRINT_SEL(m, "wakeup event: %#02x\n", registry_par->wakeup_event); + return 0; +} + +ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + struct registry_priv *registry_par = &padapter->registrypriv; + u32 wakeup_event = 0; + + u8 tmp[8] = {0}; + int ret = 0, num = 0; + u8 index = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) + num = sscanf(tmp, "%u", &wakeup_event); + else + return -EFAULT; + + if (wakeup_event <= 0x07) { + registry_par->wakeup_event = wakeup_event; + + if (wakeup_event & BIT(1)) + pwrctrlpriv->default_patterns_en = _TRUE; + else + pwrctrlpriv->default_patterns_en = _FALSE; + + rtw_wow_pattern_sw_reset(padapter); + + RTW_INFO("%s: wakeup_event: %#2x, default pattern: %d\n", + __func__, registry_par->wakeup_event, + pwrctrlpriv->default_patterns_en); + } else { + return -EINVAL; + } + + return count; +} + int proc_get_wakeup_reason(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -4000,8 +4347,16 @@ ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer, rtw_ps_deny(padapter, PS_DENY_IOCTL); LeaveAllPowerSaveModeDirect(padapter); + + #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE + if (pwrpriv->is_high_active == 0) + rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX); + else + rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0); + #else val8 = (pwrpriv->is_high_active == 0) ? 1 : 0; rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8); + #endif rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); RTW_INFO("set %s %d\n", "gpio_high_active", @@ -4135,9 +4490,130 @@ int proc_get_ps_info(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "=============================\n"); return 0; } + +#ifdef CONFIG_WMMPS_STA +int proc_get_wmmps_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char *uapsd_max_sp_str=""; + + if (pregpriv){ + switch(pregpriv->uapsd_max_sp_len) { + case 0: + uapsd_max_sp_str = "NO_LIMIT"; + break; + case 1: + uapsd_max_sp_str = "TWO_MSDU"; + break; + case 2: + uapsd_max_sp_str = "FOUR_MSDU"; + break; + case 3: + uapsd_max_sp_str = "SIX_MSDU"; + break; + default: + uapsd_max_sp_str = "UNSPECIFIED"; + break; + } + + RTW_PRINT_SEL(m, "====== WMMPS_STA Info:======\n"); + RTW_PRINT_SEL(m, "uapsd_max_sp_len=0x%02x (%s)\n", pregpriv->uapsd_max_sp_len, uapsd_max_sp_str); + RTW_PRINT_SEL(m, "uapsd_ac_enable=0x%02x\n", pregpriv->uapsd_ac_enable); + RTW_PRINT_SEL(m, "BIT0 - AC_VO UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VO) ? "Enabled" : "Disabled"); + RTW_PRINT_SEL(m, "BIT1 - AC_VI UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VI) ? "Enabled" : "Disabled"); + RTW_PRINT_SEL(m, "BIT2 - AC_BK UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BK) ? "Enabled" : "Disabled"); + RTW_PRINT_SEL(m, "BIT3 - AC_BE UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BE) ? "Enabled" : "Disabled"); + RTW_PRINT_SEL(m, "============================\n"); + } + + return 0; +} + +ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u8 uapsd_ac_setting; + u8 uapsd_max_sp_len_setting; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hhx", &uapsd_max_sp_len_setting, &uapsd_ac_setting); + + if (pregpriv) { + if (num >= 1){ + pregpriv->uapsd_max_sp_len = uapsd_max_sp_len_setting; + RTW_INFO("uapsd_max_sp_len = %d\n", pregpriv->uapsd_max_sp_len); + } + + if (num >= 2){ + pregpriv->uapsd_ac_enable = uapsd_ac_setting; + RTW_INFO("uapsd_ac_enable = 0x%02x\n", pregpriv->uapsd_ac_enable); + } + } + } + + return count; +} +#endif /* CONFIG_WMMPS_STA */ #endif /* CONFIG_POWER_SAVING */ #ifdef CONFIG_TDLS +int proc_get_tdls_enable(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + if (pregpriv) + RTW_PRINT_SEL(m, "TDLS is %s !\n", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "enabled" : "disabled"); + + return 0; +} + +ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u32 en_tdls = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &en_tdls); + + if (pregpriv) { + if (en_tdls > 0) + rtw_enable_tdls_func(padapter); + else + rtw_disable_tdls_func(padapter, _TRUE); + } + } + + return count; +} + static int proc_tdls_display_tdls_function_info(struct seq_file *m) { struct net_device *dev = m->private; @@ -4149,6 +4625,8 @@ static int proc_tdls_display_tdls_function_info(struct seq_file *m) int j = 0; RTW_PRINT_SEL(m, "============[TDLS Function Info]============\n"); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Enable", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "_TRUE" : "_FALSE"); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Driver Setup", (ptdlsinfo->driver_setup == _TRUE) ? "_TRUE" : "_FALSE"); RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Prohibited", (ptdlsinfo->ap_prohibited == _TRUE) ? "_TRUE" : "_FALSE"); RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Channel Switch Prohibited", (ptdlsinfo->ch_switch_prohibited == _TRUE) ? "_TRUE" : "_FALSE"); RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Link Established", (ptdlsinfo->link_established == _TRUE) ? "_TRUE" : "_FALSE"); @@ -4212,8 +4690,6 @@ static int proc_tdls_display_tdls_function_info(struct seq_file *m) #endif RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Device Discovered", (ptdlsinfo->dev_discovered == _TRUE) ? "_TRUE" : "_FALSE"); - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Enable", (ptdlsinfo->tdls_enable == _TRUE) ? "_TRUE" : "_FALSE"); - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Driver Setup", (ptdlsinfo->driver_setup == _TRUE) ? "_TRUE" : "_FALSE"); return 0; } @@ -4362,7 +4838,7 @@ static int proc_tdls_display_tdls_sta_info(struct seq_file *m) if (psta->tdls_sta_state != TDLS_STATE_NONE) { /* We got one TDLS sta info to show */ RTW_PRINT_SEL(m, "============[TDLS Peer STA Info: STA %d]============\n", ++NumOfTdlsStaToShow); - RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(psta->hwaddr)); + RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(psta->cmn.mac_addr)); RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS STA State"); SpaceBtwnItemAndValueTmp = 0; FirstMatchFound = _FALSE; @@ -4439,7 +4915,7 @@ static int proc_tdls_display_tdls_sta_info(struct seq_file *m) RTW_PRINT_SEL(m, "\n"); RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode"); - switch (psta->bw_mode) { + switch (psta->cmn.bw_mode) { case CHANNEL_WIDTH_20: RTW_PRINT_SEL(m, "%s\n", "20MHz"); break; @@ -4455,6 +4931,15 @@ static int proc_tdls_display_tdls_sta_info(struct seq_file *m) case CHANNEL_WIDTH_80_80: RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz"); break; + case CHANNEL_WIDTH_5: + RTW_PRINT_SEL(m, "%s\n", "5MHz"); + break; + case CHANNEL_WIDTH_10: + RTW_PRINT_SEL(m, "%s\n", "10MHz"); + break; + default: + RTW_PRINT_SEL(m, "(%d)%s\n", psta->cmn.bw_mode, "invalid"); + break; } RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy"); @@ -4774,11 +5259,11 @@ ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_ } if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) - && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && padapter->securitypriv.binstallBIPkey == _TRUE) { + && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) { RTW_INFO("STA:"MAC_FMT"\n", MAC_ARG(get_my_bssid(&(pmlmeinfo->network)))); /* TX unicast sa_query to AP */ issue_action_SA_Query(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, 0, (u8)key_type); - } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && padapter->securitypriv.binstallBIPkey == _TRUE) { + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) { /* TX unicast sa_query to every client STA */ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); for (index = 0; index < NUM_STA; index++) { @@ -4790,7 +5275,7 @@ ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); plist = get_next(plist); - _rtw_memcpy(&mac_addr[psta->mac_id][0], psta->hwaddr, ETH_ALEN); + _rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN); } } _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); @@ -4878,7 +5363,7 @@ ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); plist = get_next(plist); - _rtw_memcpy(&mac_addr[psta->mac_id][0], psta->hwaddr, ETH_ALEN); + _rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN); } } _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); @@ -5003,18 +5488,12 @@ int proc_get_mcc_policy_table(struct seq_file *m, void *v) return 0; } -ssize_t proc_set_mcc_policy_table(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[255]; - s32 mcc_policy_table_idx; - u32 mcc_duration; - u32 mcc_tsf_sync_offset; - u32 mcc_start_time_offset; - u32 mcc_interval; - s32 mcc_guard_offset0; - s32 mcc_guard_offset1; + u32 en_mcc = 0; if (NULL == buffer) { RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); @@ -5033,53 +5512,35 @@ ssize_t proc_set_mcc_policy_table(struct file *file, const char __user *buffer, } if (buffer && !copy_from_user(tmp, buffer, count)) { - #if 1 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); _adapter *iface = NULL; u8 i = 0; - int num = sscanf(tmp, "%d %u %u %u %u %d %d" - , &mcc_policy_table_idx, &mcc_duration, &mcc_tsf_sync_offset, &mcc_start_time_offset - , &mcc_interval, &mcc_guard_offset0, &mcc_guard_offset1); + int num = sscanf(tmp, "%u", &en_mcc); - if (num < 7) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 7\n", FUNC_ADPT_ARG(padapter)); + if (num < 1) { + RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); return -EINVAL; } -#if 0 - RTW_INFO("mcc_policy_table_idx:%d\n", mcc_policy_table_idx); - RTW_INFO("mcc_duration:%d\n", mcc_duration); - RTW_INFO("mcc_tsf_sync_offset:%d\n", mcc_tsf_sync_offset); - RTW_INFO("mcc_start_time_offset:%d\n", mcc_start_time_offset); - RTW_INFO("mcc_interval:%d\n", mcc_interval); - RTW_INFO("mcc_guard_offset0:%d\n", mcc_guard_offset0); - RTW_INFO("mcc_guard_offset1:%d\n", mcc_guard_offset1); -#endif + + RTW_INFO("%s: en_mcc = %d\n", __func__, en_mcc); + for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if (!iface) continue; - iface->registrypriv.rtw_mcc_policy_table_idx = mcc_policy_table_idx; - iface->registrypriv.rtw_mcc_duration = mcc_duration; - iface->registrypriv.rtw_mcc_tsf_sync_offset = mcc_tsf_sync_offset; - iface->registrypriv.rtw_mcc_start_time_offset = mcc_start_time_offset; - iface->registrypriv.rtw_mcc_interval = mcc_interval; - iface->registrypriv.rtw_mcc_guard_offset0 = mcc_guard_offset0; - iface->registrypriv.rtw_mcc_guard_offset1 = mcc_guard_offset1; + iface->registrypriv.en_mcc = en_mcc; } - - rtw_hal_mcc_update_switch_channel_policy_table(padapter); - #endif } return count; } -ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[255]; - u32 en_mcc = 0; + u32 enable_runtime_duration = 0, mcc_duration = 0; if (NULL == buffer) { RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); @@ -5098,23 +5559,26 @@ ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t } if (buffer && !copy_from_user(tmp, buffer, count)) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - _adapter *iface = NULL; - u8 i = 0; - int num = sscanf(tmp, "%u", &en_mcc); + int num = sscanf(tmp, "%u %u", &enable_runtime_duration, &mcc_duration); if (num < 1) { RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); return -EINVAL; } - RTW_INFO("%s: en_mcc = %d\n", __func__, en_mcc); + if (num > 2) { + RTW_INFO(FUNC_ADPT_FMT ": input parameters > 2\n", FUNC_ADPT_ARG(padapter)); + return -EINVAL; + } - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface) - continue; - iface->registrypriv.en_mcc = en_mcc; + if (num >= 1) { + SET_MCC_RUNTIME_DURATION(padapter, enable_runtime_duration); + RTW_INFO("runtime duration:%s\n", enable_runtime_duration ? "enable":"disable"); + } + + if (num == 2) { + RTW_INFO("mcc duration:%d\n", mcc_duration); + rtw_set_mcc_duration_cmd(padapter, MCC_DURATION_DIRECET, mcc_duration); } } @@ -5479,14 +5943,14 @@ ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_ return count; } -ssize_t proc_set_iqk_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); _adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter); HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); char tmp[32]; - u32 enable = 0; + u32 iqk_offload_enable = 0, ch_switch_offload_enable = 0; if (buffer == NULL) { RTW_INFO("input buffer is NULL!\n"); @@ -5505,23 +5969,26 @@ ssize_t proc_set_iqk_fw_offload(struct file *file, const char __user *buffer, si } if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d", &enable); + int num = sscanf(tmp, "%d %d", &iqk_offload_enable, &ch_switch_offload_enable); - if (num < 1) { + if (num < 2) { RTW_INFO("input parameters < 1\n"); return -EINVAL; } - if (hal->RegIQKFWOffload != enable) { - hal->RegIQKFWOffload = enable; + if (hal->RegIQKFWOffload != iqk_offload_enable) { + hal->RegIQKFWOffload = iqk_offload_enable; rtw_hal_update_iqk_fw_offload_cap(pri_adapter); } + + if (hal->ch_switch_offload != ch_switch_offload_enable) + hal->ch_switch_offload = ch_switch_offload_enable; } return count; } -int proc_get_iqk_fw_offload(struct seq_file *m, void *v) +int proc_get_fw_offload(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); @@ -5529,7 +5996,194 @@ int proc_get_iqk_fw_offload(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "IQK FW offload:%s\n", hal->RegIQKFWOffload?"enable":"disable"); + RTW_PRINT_SEL(m, "Channel switch FW offload:%s\n", hal->ch_switch_offload?"enable":"disable"); return 0; } +#ifdef CONFIG_DBG_RF_CAL +int proc_get_iqk_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + return 0; +} + +ssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 recovery, clear, segment; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d %d %d", &recovery, &clear, &segment); + + rtw_hal_iqk_test(padapter, recovery, clear, segment); + } + + return count; + +} + +int proc_get_lck_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + return 0; +} + +ssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 trigger; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d", &trigger); + + rtw_hal_lck_test(padapter); + } + + return count; +} +#endif /* CONFIG_DBG_RF_CAL */ + #endif /* CONFIG_PROC_DEBUG */ +#define RTW_BUFDUMP_BSIZE 16 +#if 1 +inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring, + bool _idx_show, const u8 *_hexdata, int _hexdatalen) +{ + int __i; + u8 *ptr = (u8 *)_hexdata; + + if (_loglevel <= rtw_drv_log_level) { + if (_titlestring) { + if (sel == RTW_DBGDUMP) + RTW_PRINT(""); + _RTW_PRINT_SEL(sel, "%s", _titlestring); + if (_hexdatalen >= RTW_BUFDUMP_BSIZE) + _RTW_PRINT_SEL(sel, "\n"); + } + + for (__i = 0; __i < _hexdatalen; __i++) { + if (((__i % RTW_BUFDUMP_BSIZE) == 0) && (_hexdatalen >= RTW_BUFDUMP_BSIZE)) { + if (sel == RTW_DBGDUMP) + RTW_PRINT(""); + if (_idx_show) + _RTW_PRINT_SEL(sel, "0x%03X: ", __i); + } + _RTW_PRINT_SEL(sel, "%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); + if ((__i + 1 < _hexdatalen) && ((__i + 1) % RTW_BUFDUMP_BSIZE) == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + _RTW_PRINT_SEL(sel, "\n"); + } +} +#else +inline void _RTW_STR_DUMP_SEL(void *sel, char *str_out) +{ + if (sel == RTW_DBGDUMP) + _dbgdump("%s\n", str_out); + #if defined(_seqdump) + else + _seqdump(sel, "%s\n", str_out); + #endif /*_seqdump*/ +} +inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring, + bool _idx_show, u8 *_hexdata, int _hexdatalen) +{ + int __i, len; + int __j, idx; + int block_num, remain_byte; + char str_out[128] = {'\0'}; + char str_val[32] = {'\0'}; + char *p = NULL; + u8 *ptr = (u8 *)_hexdata; + + if (_loglevel <= rtw_drv_log_level) { + /*dump title*/ + p = &str_out[0]; + if (_titlestring) { + if (sel == RTW_DBGDUMP) { + len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX); + strncpy(p, str_val, len); + p += len; + } + len = snprintf(str_val, sizeof(str_val), "%s", _titlestring); + strncpy(p, str_val, len); + p += len; + } + if (p != &str_out[0]) { + _RTW_STR_DUMP_SEL(sel, str_out); + _rtw_memset(&str_out, '\0', sizeof(str_out)); + } + + /*dump buffer*/ + block_num = _hexdatalen / RTW_BUFDUMP_BSIZE; + remain_byte = _hexdatalen % RTW_BUFDUMP_BSIZE; + for (__i = 0; __i < block_num; __i++) { + p = &str_out[0]; + if (sel == RTW_DBGDUMP) { + len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX); + strncpy(p, str_val, len); + p += len; + } + if (_idx_show) { + len = snprintf(str_val, sizeof(str_val), "0x%03X: ", __i * RTW_BUFDUMP_BSIZE); + strncpy(p, str_val, len); + p += len; + } + for (__j =0; __j < RTW_BUFDUMP_BSIZE; __j++) { + idx = __i * RTW_BUFDUMP_BSIZE + __j; + len = snprintf(str_val, sizeof(str_val), "%02X%s", ptr[idx], (((__j + 1) % 4) == 0) ? " " : " "); + strncpy(p, str_val, len); + p += len; + } + _RTW_STR_DUMP_SEL(sel, str_out); + _rtw_memset(&str_out, '\0', sizeof(str_out)); + } + + p = &str_out[0]; + if ((sel == RTW_DBGDUMP) && remain_byte) { + len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX); + strncpy(p, str_val, len); + p += len; + } + if (_idx_show && remain_byte) { + len = snprintf(str_val, sizeof(str_val), "0x%03X: ", block_num * RTW_BUFDUMP_BSIZE); + strncpy(p, str_val, len); + p += len; + } + for (__i = 0; __i < remain_byte; __i++) { + idx = block_num * RTW_BUFDUMP_BSIZE + __i; + len = snprintf(str_val, sizeof(str_val), "%02X%s", ptr[idx], (((__i + 1) % 4) == 0) ? " " : " "); + strncpy(p, str_val, len); + p += len; + } + _RTW_STR_DUMP_SEL(sel, str_out); + } +} + +#endif diff --git a/core/rtw_ieee80211.c b/core/rtw_ieee80211.c index 2899985..4609336 100644 --- a/core/rtw_ieee80211.c +++ b/core/rtw_ieee80211.c @@ -191,7 +191,7 @@ u8 *rtw_set_ie u8 *pbuf, sint index, uint len, - u8 *source, + const u8 *source, uint *frlen /* frame length */ ) { @@ -202,7 +202,8 @@ u8 *rtw_set_ie if (len > 0) _rtw_memcpy((void *)(pbuf + 2), (void *)source, len); - *frlen = *frlen + (len + 2); + if (frlen) + *frlen = *frlen + (len + 2); return pbuf + len + 2; } @@ -223,9 +224,9 @@ inline u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset) if (ch_offset == SCN) return HAL_PRIME_CHNL_OFFSET_DONT_CARE; else if (ch_offset == SCA) - return HAL_PRIME_CHNL_OFFSET_UPPER; - else if (ch_offset == SCB) return HAL_PRIME_CHNL_OFFSET_LOWER; + else if (ch_offset == SCB) + return HAL_PRIME_CHNL_OFFSET_UPPER; return HAL_PRIME_CHNL_OFFSET_DONT_CARE; } @@ -235,9 +236,9 @@ inline u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset) if (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) return SCN; else if (ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) - return SCB; - else if (ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) return SCA; + else if (ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) + return SCB; return SCN; } @@ -263,10 +264,10 @@ inline u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, /*---------------------------------------------------------------------------- index: the information element id index, limit is the limit for search -----------------------------------------------------------------------------*/ -u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit) +u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit) { sint tmp, i; - u8 *p; + const u8 *p; if (limit < 1) { return NULL; } @@ -277,7 +278,7 @@ u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit) while (1) { if (*p == index) { *len = *(p + 1); - return p; + return (u8 *)p; } else { tmp = *(p + 1); p += (tmp + 2); @@ -301,17 +302,17 @@ u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit) * * Returns: The address of the specific IE found, or NULL */ -u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen) +u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen) { uint cnt; - u8 *target_ie = NULL; + const u8 *target_ie = NULL; if (ielen) *ielen = 0; if (!in_ie || in_len <= 0) - return target_ie; + return (u8 *)target_ie; cnt = 0; @@ -333,7 +334,7 @@ u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, u } - return target_ie; + return (u8 *)target_ie; } /** @@ -674,72 +675,144 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwis } -int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x) +int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info) { - int i, ret = _SUCCESS; - int left, count; - u8 *pos; - u8 SUITE_1X[4] = {0x00, 0x0f, 0xac, 0x01}; + int i; + const u8 *pos = ie; + u16 cnt; - if (rsn_ie_len <= 0) { - /* No RSN IE - fail silently */ - return _FAIL; - } + _rtw_memset(info, 0, sizeof(struct rsne_info)); + if (ie + ie_len < pos + 4) + goto err; - if ((*rsn_ie != _WPA2_IE_ID_) || (*(rsn_ie + 1) != (u8)(rsn_ie_len - 2))) - return _FAIL; + if (*ie != WLAN_EID_RSN || *(ie + 1) != ie_len - 2) + goto err; + pos += 2 + 2; - pos = rsn_ie; + /* Group CS */ + if (ie + ie_len < pos + 4) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + info->gcs = (u8 *)pos; pos += 4; - left = rsn_ie_len - 4; - /* group_cipher */ - if (left >= RSN_SELECTOR_LEN) { + /* Pairwise CS */ + if (ie + ie_len < pos + 2) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + cnt = RTW_GET_LE16(pos); + pos += 2; + if (ie + ie_len < pos + 4 * cnt) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + info->pcs_cnt = cnt; + info->pcs_list = (u8 *)pos; + pos += 4 * cnt; - *group_cipher = rtw_get_wpa2_cipher_suite(pos); + /* AKM */ + if (ie + ie_len < pos + 2) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + cnt = RTW_GET_LE16(pos); + pos += 2; + if (ie + ie_len < pos + 4 * cnt) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + info->akm_cnt = cnt; + info->akm_list = (u8 *)pos; + pos += 4 * cnt; - pos += RSN_SELECTOR_LEN; - left -= RSN_SELECTOR_LEN; + /* RSN cap */ + if (ie + ie_len < pos + 2) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + info->cap = (u8 *)pos; + pos += 2; - } else if (left > 0) { - return _FAIL; + /* PMKID */ + if (ie + ie_len < pos + 2) { + if (ie + ie_len != pos) + goto err; + goto exit; } + cnt = RTW_GET_LE16(pos); + pos += 2; + if (ie + ie_len < pos + 16 * cnt) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + info->pmkid_cnt = cnt; + info->pmkid_list = (u8 *)pos; + pos += 16 * cnt; - /* pairwise_cipher */ - if (left >= 2) { - /* count = le16_to_cpu(*(u16*)pos); */ - count = RTW_GET_LE16(pos); - pos += 2; - left -= 2; + /* Group Mgmt CS */ + if (ie + ie_len < pos + 4) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + info->gmcs = (u8 *)pos; - if (count == 0 || left < count * RSN_SELECTOR_LEN) { - return _FAIL; - } +exit: + return _SUCCESS; - for (i = 0; i < count; i++) { - *pairwise_cipher |= rtw_get_wpa2_cipher_suite(pos); +err: + info->err = 1; + return _FAIL; +} - pos += RSN_SELECTOR_LEN; - left -= RSN_SELECTOR_LEN; - } +int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x, u8 *mfp_opt) +{ + struct rsne_info info; + int i, ret = _SUCCESS; + u8 SUITE_1X[4] = {0x00, 0x0f, 0xac, 0x01}; - } else if (left == 1) { + ret = rtw_rsne_info_parse(rsn_ie, rsn_ie_len, &info); + if (ret != _SUCCESS) + goto exit; - return _FAIL; + if (group_cipher) { + if (info.gcs) + *group_cipher = rtw_get_wpa2_cipher_suite(info.gcs); + else + *group_cipher = 0; + } + + if (pairwise_cipher) { + *pairwise_cipher = 0; + for (i = 0; i < info.pcs_cnt; i++) + *pairwise_cipher |= rtw_get_wpa2_cipher_suite(info.pcs_list + 4 * i); } if (is_8021x) { - if (left >= 6) { - pos += 2; - if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) { - *is_8021x = 1; - } - } + *is_8021x = 0; + /* here only check the first AKM suite */ + if (info.akm_cnt && _rtw_memcmp(SUITE_1X, info.akm_list, 4) == _TRUE) + *is_8021x = 1; } - return ret; + if (mfp_opt) { + *mfp_opt = MFP_NO; + if (info.cap) + *mfp_opt = GET_RSN_CAP_MFP_OPTION(info.cap); + } +exit: + return ret; } /* #ifdef CONFIG_WAPI_SUPPORT */ @@ -848,23 +921,26 @@ u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen) return match; } -u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, u8 frame_type) +u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type) { u8 *wps = NULL; RTW_INFO("[%s] frame_type = %d\n", __FUNCTION__, frame_type); switch (frame_type) { - case 1: - case 3: { + case BSS_TYPE_BCN: + case BSS_TYPE_PROB_RSP: { /* Beacon or Probe Response */ wps = rtw_get_wps_ie(in_ie + _PROBERSP_IE_OFFSET_, in_len - _PROBERSP_IE_OFFSET_, wps_ie, wps_ielen); break; } - case 2: { + case BSS_TYPE_PROB_REQ: { /* Probe Request */ wps = rtw_get_wps_ie(in_ie + _PROBEREQ_IE_OFFSET_ , in_len - _PROBEREQ_IE_OFFSET_ , wps_ie, wps_ielen); break; } + default: + case BSS_TYPE_UNDEF: + break; } return wps; } @@ -878,10 +954,10 @@ u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps * * Returns: The address of the WPS IE found, or NULL */ -u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen) +u8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen) { uint cnt; - u8 *wpsie_ptr = NULL; + const u8 *wpsie_ptr = NULL; u8 eid, wps_oui[4] = {0x00, 0x50, 0xf2, 0x04}; if (wps_ielen) @@ -889,11 +965,11 @@ u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen) if (!in_ie) { rtw_warn_on(1); - return wpsie_ptr; + return (u8 *)wpsie_ptr; } if (in_len <= 0) - return wpsie_ptr; + return (u8 *)wpsie_ptr; cnt = 0; @@ -920,7 +996,7 @@ u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen) } - return wpsie_ptr; + return (u8 *)wpsie_ptr; } /** @@ -1231,6 +1307,28 @@ ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, elems->vht_op_mode_notify = pos; elems->vht_op_mode_notify_len = elen; break; + case _EID_RRM_EN_CAP_IE_: + elems->rm_en_cap = pos; + elems->rm_en_cap_len = elen; + break; +#ifdef CONFIG_RTW_MESH + case WLAN_EID_PREQ: + elems->preq = pos; + elems->preq_len = elen; + break; + case WLAN_EID_PREP: + elems->prep = pos; + elems->prep_len = elen; + break; + case WLAN_EID_PERR: + elems->perr = pos; + elems->perr_len = elen; + break; + case WLAN_EID_RANN: + elems->rann = pos; + elems->rann_len = elen; + break; +#endif default: unknown++; if (!show_errors) @@ -1428,40 +1526,78 @@ void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr) } #ifdef CONFIG_80211N_HT -void dump_ht_cap_ie_content(void *sel, u8 *buf, u32 buf_len) +void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len) { - if (buf_len != 26) { - RTW_PRINT_SEL(sel, "Invalid HT capability IE len:%d != %d\n", buf_len, 26); + if (buf_len != HT_CAP_IE_LEN) { + RTW_PRINT_SEL(sel, "Invalid HT capability IE len:%d != %d\n", buf_len, HT_CAP_IE_LEN); return; } - RTW_PRINT_SEL(sel, "HT Capabilities Info:%02x%02x\n", *(buf), *(buf + 1)); + RTW_PRINT_SEL(sel, "cap_info:%02x%02x:%s\n", *(buf), *(buf + 1) + , GET_HT_CAP_ELE_CHL_WIDTH(buf) ? " 40MHz" : " 20MHz"); RTW_PRINT_SEL(sel, "A-MPDU Parameters:"HT_AMPDU_PARA_FMT"\n" , HT_AMPDU_PARA_ARG(HT_CAP_ELE_AMPDU_PARA(buf))); RTW_PRINT_SEL(sel, "Supported MCS Set:"HT_SUP_MCS_SET_FMT"\n" , HT_SUP_MCS_SET_ARG(HT_CAP_ELE_SUP_MCS_SET(buf))); } -void dump_ht_cap_ie(void *sel, u8 *ie, u32 ie_len) +void dump_ht_cap_ie(void *sel, const u8 *ie, u32 ie_len) { - u8 *pos = (u8 *)ie; + const u8 *pos = ie; u16 id; u16 len; - u8 *ht_cap_ie; + const u8 *ht_cap_ie; sint ht_cap_ielen; - ht_cap_ie = rtw_get_ie(ie, _HT_CAPABILITY_IE_, &ht_cap_ielen, ie_len); + ht_cap_ie = rtw_get_ie(ie, WLAN_EID_HT_CAP, &ht_cap_ielen, ie_len); if (!ie || ht_cap_ie != ie) return; dump_ht_cap_ie_content(sel, ht_cap_ie + 2, ht_cap_ielen); } + +const char *const _ht_sc_offset_str[] = { + "SCN", + "SCA", + "SC-RSVD", + "SCB", +}; + +void dump_ht_op_ie_content(void *sel, const u8 *buf, u32 buf_len) +{ + if (buf_len != HT_OP_IE_LEN) { + RTW_PRINT_SEL(sel, "Invalid HT operation IE len:%d != %d\n", buf_len, HT_OP_IE_LEN); + return; + } + + RTW_PRINT_SEL(sel, "ch:%u%s %s\n" + , GET_HT_OP_ELE_PRI_CHL(buf) + , GET_HT_OP_ELE_STA_CHL_WIDTH(buf) ? "" : " 20MHz only" + , ht_sc_offset_str(GET_HT_OP_ELE_2ND_CHL_OFFSET(buf)) + ); +} + +void dump_ht_op_ie(void *sel, const u8 *ie, u32 ie_len) +{ + const u8 *pos = ie; + u16 id; + u16 len; + + const u8 *ht_op_ie; + sint ht_op_ielen; + + ht_op_ie = rtw_get_ie(ie, WLAN_EID_HT_OPERATION, &ht_op_ielen, ie_len); + if (!ie || ht_op_ie != ie) + return; + + dump_ht_op_ie_content(sel, ht_op_ie + 2, ht_op_ielen); +} #endif /* CONFIG_80211N_HT */ -void dump_ies(void *sel, u8 *buf, u32 buf_len) +void dump_ies(void *sel, const u8 *buf, u32 buf_len) { - u8 *pos = (u8 *)buf; + const u8 *pos = buf; u8 id, len; while (pos - buf + 1 < buf_len) { @@ -1471,6 +1607,11 @@ void dump_ies(void *sel, u8 *buf, u32 buf_len) RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u\n", __FUNCTION__, id, len); #ifdef CONFIG_80211N_HT dump_ht_cap_ie(sel, pos, len + 2); + dump_ht_op_ie(sel, pos, len + 2); +#endif +#ifdef CONFIG_80211AC_VHT + dump_vht_cap_ie(sel, pos, len + 2); + dump_vht_op_ie(sel, pos, len + 2); #endif dump_wps_ie(sel, pos, len + 2); #ifdef CONFIG_P2P @@ -1484,13 +1625,13 @@ void dump_ies(void *sel, u8 *buf, u32 buf_len) } } -void dump_wps_ie(void *sel, u8 *ie, u32 ie_len) +void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len) { - u8 *pos = (u8 *)ie; + const u8 *pos = ie; u16 id; u16 len; - u8 *wps_ie; + const u8 *wps_ie; uint wps_ielen; wps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen); @@ -1516,8 +1657,10 @@ void dump_wps_ie(void *sel, u8 *ie, u32 ie_len) * @ch: pointer of ch, used as output * @bw: pointer of bw, used as output * @offset: pointer of offset, used as output + * @ht: check HT IEs + * @vht: check VHT IEs, if true imply ht is true */ -void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset) +void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht) { u8 *p; int ie_len; @@ -1531,7 +1674,7 @@ void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset) *ch = *(p + 2); #ifdef CONFIG_80211N_HT - { + if (ht || vht) { u8 *ht_cap_ie, *ht_op_ie; int ht_cap_ielen, ht_op_ielen; @@ -1564,44 +1707,29 @@ void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset) } } } - } -#endif /* CONFIG_80211N_HT */ + #ifdef CONFIG_80211AC_VHT - { - u8 *vht_op_ie; - int vht_op_ielen; - - vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len); - if (vht_op_ie && vht_op_ielen) { - /* enable VHT 80 before check enable HT40 or not */ - if (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2) >= 1) { - /* for HT40, enable VHT80 */ - if (*bw == CHANNEL_WIDTH_40) + if (vht) { + u8 *vht_op_ie; + int vht_op_ielen; + + vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len); + if (vht_op_ie && vht_op_ielen) { + if (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2) >= 1) *bw = CHANNEL_WIDTH_80; - /* for HT20, enable VHT20 */ - else if (*bw == CHANNEL_WIDTH_20) { - /* modify VHT OP IE */ - SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0); - /* reset to 0 for VHT20 */ - SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0); - SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0); - } - } else { - /* - VHT OP WIDTH = 0 under HT20/HT40 - if REGSTY_BW_5G(pregistrypriv) < CHANNEL_WIDTH_80 in rtw_build_vht_operation_ie - */ } } +#endif /* CONFIG_80211AC_VHT */ + } -#endif +#endif /* CONFIG_80211N_HT */ } -void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset) +void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht) { rtw_ies_get_chbw(bss->IEs + sizeof(NDIS_802_11_FIXED_IEs) , bss->IELength - sizeof(NDIS_802_11_FIXED_IEs) - , ch, bw, offset); + , ch, bw, offset, ht, vht); if (*ch == 0) *ch = bss->Configuration.DSConfig; @@ -1668,7 +1796,7 @@ void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80) *req_offset = *g_offset; else if (*g_bw == CHANNEL_WIDTH_20) - *req_offset = rtw_get_offset_by_ch(*req_ch); + rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset); if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { RTW_ERR("%s req 80MHz BW without offset, down to 20MHz\n", __func__); @@ -1680,7 +1808,7 @@ void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80) *req_offset = *g_offset; else if (*g_bw == CHANNEL_WIDTH_20) - *req_offset = rtw_get_offset_by_ch(*req_ch); + rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset); if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { RTW_ERR("%s req 40MHz BW without offset, down to 20MHz\n", __func__); @@ -1768,13 +1896,13 @@ int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie) return 0; } -void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len) +void dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len) { - u8 *pos = (u8 *)ie; + const u8 *pos = ie; u8 id; u16 len; - u8 *p2p_ie; + const u8 *p2p_ie; uint p2p_ielen; p2p_ie = rtw_get_p2p_ie(ie, ie_len, NULL, &p2p_ielen); @@ -1802,10 +1930,10 @@ void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len) * * Returns: The address of the P2P IE found, or NULL */ -u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen) +u8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen) { uint cnt; - u8 *p2p_ie_ptr = NULL; + const u8 *p2p_ie_ptr = NULL; u8 eid, p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09}; if (p2p_ielen) @@ -1813,11 +1941,11 @@ u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen) if (!in_ie || in_len < 0) { rtw_warn_on(1); - return p2p_ie_ptr; + return (u8 *)p2p_ie_ptr; } if (in_len <= 0) - return p2p_ie_ptr; + return (u8 *)p2p_ie_ptr; cnt = 0; @@ -1844,7 +1972,7 @@ u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen) } - return p2p_ie_ptr; + return (u8 *)p2p_ie_ptr; } /** @@ -2112,13 +2240,13 @@ void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id) } } -void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len) +void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len) { - u8 *pos = (u8 *)ie; + const u8 *pos = ie; u8 id; u16 len; - u8 *wfd_ie; + const u8 *wfd_ie; uint wfd_ielen; wfd_ie = rtw_get_wfd_ie(ie, ie_len, NULL, &wfd_ielen); @@ -2146,10 +2274,10 @@ void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len) * * Returns: The address of the P2P IE found, or NULL */ -u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen) +u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen) { uint cnt; - u8 *wfd_ie_ptr = NULL; + const u8 *wfd_ie_ptr = NULL; u8 eid, wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A}; if (wfd_ielen) @@ -2157,11 +2285,11 @@ u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen) if (!in_ie || in_len < 0) { rtw_warn_on(1); - return wfd_ie_ptr; + return (u8 *)wfd_ie_ptr; } if (in_len <= 0) - return wfd_ie_ptr; + return (u8 *)wfd_ie_ptr; cnt = 0; @@ -2188,7 +2316,7 @@ u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen) } - return wfd_ie_ptr; + return (u8 *)wfd_ie_ptr; } /** @@ -2503,7 +2631,7 @@ int rtw_get_cipher_info(struct wlan_network *pnetwork) pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12); if (pbuf && (wpa_ielen > 0)) { - if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x)) { + if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x, NULL)) { pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher; pnetwork->BcnInfo.group_cipher = group_cipher; pnetwork->BcnInfo.is_8021x = is8021x; diff --git a/core/rtw_ioctl_set.c b/core/rtw_ioctl_set.c index efd4fcf..e26f74a 100644 --- a/core/rtw_ioctl_set.c +++ b/core/rtw_ioctl_set.c @@ -74,6 +74,7 @@ u8 rtw_do_join(_adapter *padapter) _list *plist, *phead; u8 *pibss = NULL; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sitesurvey_parm parm; _queue *queue = &(pmlmepriv->scanned_queue); u8 ret = _SUCCESS; @@ -91,6 +92,10 @@ u8 rtw_do_join(_adapter *padapter) pmlmepriv->to_join = _TRUE; + rtw_init_sitesurvey_parm(padapter, &parm); + _rtw_memcpy(&parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); + parm.ssid_num = 1; + if (_rtw_queue_empty(queue) == _TRUE) { _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); @@ -102,7 +107,7 @@ u8 rtw_do_join(_adapter *padapter) || rtw_to_roam(padapter) > 0 ) { /* submit site_survey_cmd */ - ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); + ret = rtw_sitesurvey_cmd(padapter, &parm); if (_SUCCESS != ret) { pmlmepriv->to_join = _FALSE; } @@ -156,7 +161,7 @@ u8 rtw_do_join(_adapter *padapter) /* for funk to do roaming */ /* funk will reconnect, but funk will not sitesurvey before reconnect */ if (pmlmepriv->sitesurveyctrl.traffic_busy == _FALSE) - rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); + rtw_sitesurvey_cmd(padapter, &parm); } } @@ -168,7 +173,7 @@ u8 rtw_do_join(_adapter *padapter) || rtw_to_roam(padapter) > 0 ) { /* RTW_INFO("rtw_do_join() when no desired bss in scanning queue\n"); */ - ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); + ret = rtw_sitesurvey_cmd(padapter, &parm); if (_SUCCESS != ret) { pmlmepriv->to_join = _FALSE; } @@ -510,14 +515,15 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, struct wlan_network *cur_network = &pmlmepriv->cur_network; NDIS_802_11_NETWORK_INFRASTRUCTURE *pold_state = &(cur_network->network.InfrastructureMode); u8 ap2sta_mode = _FALSE; - - + u8 ret = _TRUE; if (*pold_state != networktype) { /* RTW_INFO("change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); */ - if (*pold_state == Ndis802_11APMode) { - /* change to other mode from Ndis802_11APMode */ + if (*pold_state == Ndis802_11APMode + || *pold_state == Ndis802_11_mesh + ) { + /* change to other mode from Ndis802_11APMode/Ndis802_11_mesh */ cur_network->join_res = -1; ap2sta_mode = _TRUE; #ifdef CONFIG_NATIVEAP_MLME @@ -565,12 +571,22 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, break; +#ifdef CONFIG_RTW_MESH + case Ndis802_11_mesh: + set_fwstate(pmlmepriv, WIFI_MESH_STATE); + start_ap_mode(padapter); + break; +#endif + case Ndis802_11AutoUnknown: case Ndis802_11InfrastructureMax: break; case Ndis802_11Monitor: set_fwstate(pmlmepriv, WIFI_MONITOR_STATE); break; + default: + ret = _FALSE; + rtw_warn_on(1); } /* SecClearAllKeys(adapter); */ @@ -579,8 +595,7 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, _exit_critical_bh(&pmlmepriv->lock, &irqL); } - - return _TRUE; + return ret; } @@ -609,21 +624,21 @@ u8 rtw_set_802_11_disassociate(_adapter *padapter) } #if 1 -u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num, struct rtw_ieee80211_channel *ch, int ch_num) +u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm) { _irqL irqL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; u8 res = _TRUE; _enter_critical_bh(&pmlmepriv->lock, &irqL); - res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num, ch, ch_num); + res = rtw_sitesurvey_cmd(padapter, pparm); _exit_critical_bh(&pmlmepriv->lock, &irqL); return res; } #else -u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num, struct rtw_ieee80211_channel *ch, int ch_num) +u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm) { _irqL irqL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -655,7 +670,7 @@ u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, i _enter_critical_bh(&pmlmepriv->lock, &irqL); - res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num, NULL, 0, ch, ch_num); + res = rtw_sitesurvey_cmd(padapter, pparm); _exit_critical_bh(&pmlmepriv->lock, &irqL); } @@ -745,374 +760,6 @@ u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep) } -u8 rtw_set_802_11_remove_wep(_adapter *padapter, u32 keyindex) -{ - - u8 ret = _SUCCESS; - - - if (keyindex >= 0x80000000 || padapter == NULL) { - - ret = _FALSE; - goto exit; - - } else { - int res; - struct security_priv *psecuritypriv = &(padapter->securitypriv); - if (keyindex < 4) { - - _rtw_memset(&psecuritypriv->dot11DefKey[keyindex], 0, 16); - - res = rtw_set_key(padapter, psecuritypriv, keyindex, 0, _TRUE); - - psecuritypriv->dot11DefKeylen[keyindex] = 0; - - if (res == _FAIL) - ret = _FAIL; - - } else - ret = _FAIL; - - } - -exit: - - - return ret; - -} - -u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) -{ - - uint encryptionalgo; - u8 *pbssid; - struct sta_info *stainfo; - u8 bgroup = _FALSE; - u8 bgrouptkey = _FALSE;/* can be remove later */ - u8 ret = _SUCCESS; - - - if (((key->KeyIndex & 0x80000000) == 0) && ((key->KeyIndex & 0x40000000) > 0)) { - - /* It is invalid to clear bit 31 and set bit 30. If the miniport driver encounters this combination, */ - /* it must fail the request and return NDIS_STATUS_INVALID_DATA. */ - ret = _FAIL; - goto exit; - } - - if (key->KeyIndex & 0x40000000) { - /* Pairwise key */ - - - pbssid = get_bssid(&padapter->mlmepriv); - stainfo = rtw_get_stainfo(&padapter->stapriv, pbssid); - - if ((stainfo != NULL) && (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)) { - encryptionalgo = stainfo->dot118021XPrivacy; - } else { - encryptionalgo = padapter->securitypriv.dot11PrivacyAlgrthm; - } - - - - - if (key->KeyIndex & 0x000000FF) { - /* The key index is specified in the lower 8 bits by values of zero to 255. */ - /* The key index should be set to zero for a Pairwise key, and the driver should fail with */ - /* NDIS_STATUS_INVALID_DATA if the lower 8 bits is not zero */ - ret = _FAIL; - goto exit; - } - - /* check BSSID */ - if (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _TRUE) { - - ret = _FALSE; - goto exit; - } - - /* Check key length for TKIP. */ - /* if(encryptionAlgorithm == RT_ENC_TKIP_ENCRYPTION && key->KeyLength != 32) */ - if ((encryptionalgo == _TKIP_) && (key->KeyLength != 32)) { - ret = _FAIL; - goto exit; - - } - - /* Check key length for AES. */ - if ((encryptionalgo == _AES_) && (key->KeyLength != 16)) { - /* For our supplicant, EAPPkt9x.vxd, cannot differentiate TKIP and AES case. */ - if (key->KeyLength == 32) - key->KeyLength = 16; - else { - ret = _FAIL; - goto exit; - } - } - - /* Check key length for WEP. For NDTEST, 2005.01.27, by rcnjko. -> modify checking condition*/ - if (((encryptionalgo == _WEP40_) && (key->KeyLength != 5)) || ((encryptionalgo == _WEP104_) && (key->KeyLength != 13))) { - ret = _FAIL; - goto exit; - } - - bgroup = _FALSE; - - /* Check the pairwise key. Added by Annie, 2005-07-06. */ - - } else { - /* Group key - KeyIndex(BIT30==0) */ - - - /* when add wep key through add key and didn't assigned encryption type before */ - if ((padapter->securitypriv.ndisauthtype <= 3) && (padapter->securitypriv.dot118021XGrpPrivacy == 0)) { - - switch (key->KeyLength) { - case 5: - padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_; - break; - case 13: - padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_; - break; - default: - padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_; - break; - } - - encryptionalgo = padapter->securitypriv.dot11PrivacyAlgrthm; - - - } else { - encryptionalgo = padapter->securitypriv.dot118021XGrpPrivacy; - - } - - if ((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE) == _TRUE) && (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _FALSE)) { - ret = _FAIL; - goto exit; - } - - /* Check key length for TKIP */ - if ((encryptionalgo == _TKIP_) && (key->KeyLength != 32)) { - - ret = _FAIL; - goto exit; - - } else if (encryptionalgo == _AES_ && (key->KeyLength != 16 && key->KeyLength != 32)) { - - /* Check key length for AES */ - /* For NDTEST, we allow keylen=32 in this case. 2005.01.27, by rcnjko. */ - ret = _FAIL; - goto exit; - } - - /* Change the key length for EAPPkt9x.vxd. Added by Annie, 2005-11-03. */ - if ((encryptionalgo == _AES_) && (key->KeyLength == 32)) { - key->KeyLength = 16; - } - - if (key->KeyIndex & 0x8000000) /* error ??? 0x8000_0000 */ - bgrouptkey = _TRUE; - - if ((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE) == _TRUE) && (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE)) - bgrouptkey = _TRUE; - - bgroup = _TRUE; - - - } - - /* If WEP encryption algorithm, just call rtw_set_802_11_add_wep(). */ - if ((padapter->securitypriv.dot11AuthAlgrthm != dot11AuthAlgrthm_8021X) && (encryptionalgo == _WEP40_ || encryptionalgo == _WEP104_)) { - u8 ret; - u32 keyindex; - u32 len = FIELD_OFFSET(NDIS_802_11_KEY, KeyMaterial) + key->KeyLength; - NDIS_802_11_WEP *wep = &padapter->securitypriv.ndiswep; - - - wep->Length = len; - keyindex = key->KeyIndex & 0x7fffffff; - wep->KeyIndex = keyindex ; - wep->KeyLength = key->KeyLength; - - - _rtw_memcpy(wep->KeyMaterial, key->KeyMaterial, key->KeyLength); - _rtw_memcpy(&(padapter->securitypriv.dot11DefKey[keyindex].skey[0]), key->KeyMaterial, key->KeyLength); - - padapter->securitypriv.dot11DefKeylen[keyindex] = key->KeyLength; - padapter->securitypriv.dot11PrivacyKeyIndex = keyindex; - - ret = rtw_set_802_11_add_wep(padapter, wep); - - goto exit; - - } - - if (key->KeyIndex & 0x20000000) { - /* SetRSC */ - if (bgroup == _TRUE) { - NDIS_802_11_KEY_RSC keysrc = key->KeyRSC & 0x00FFFFFFFFFFFFULL; - _rtw_memcpy(&padapter->securitypriv.dot11Grprxpn, &keysrc, 8); - } else { - NDIS_802_11_KEY_RSC keysrc = key->KeyRSC & 0x00FFFFFFFFFFFFULL; - _rtw_memcpy(&padapter->securitypriv.dot11Grptxpn, &keysrc, 8); - } - - } - - /* Indicate this key idx is used for TX */ - /* Save the key in KeyMaterial */ - if (bgroup == _TRUE) { /* Group transmit key */ - int res; - - if (bgrouptkey == _TRUE) - padapter->securitypriv.dot118021XGrpKeyid = (u8)key->KeyIndex; - - if ((key->KeyIndex & 0x3) == 0) { - ret = _FAIL; - goto exit; - } - - _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], 0, 16); - _rtw_memset(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16); - _rtw_memset(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16); - - if ((key->KeyIndex & 0x10000000)) { - _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8); - _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8); - - - } else { - _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8); - _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8); - - - } - - /* set group key by index */ - _rtw_memcpy(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial, key->KeyLength); - - key->KeyIndex = key->KeyIndex & 0x03; - - padapter->securitypriv.binstallGrpkey = _TRUE; - - padapter->securitypriv.bcheck_grpkey = _FALSE; - - - res = rtw_set_key(padapter, &padapter->securitypriv, key->KeyIndex, 1, _TRUE); - - if (res == _FAIL) - ret = _FAIL; - - goto exit; - - } else { /* Pairwise Key */ - u8 res; - - pbssid = get_bssid(&padapter->mlmepriv); - stainfo = rtw_get_stainfo(&padapter->stapriv , pbssid); - - if (stainfo != NULL) { - _rtw_memset(&stainfo->dot118021x_UncstKey, 0, 16); /* clear keybuffer */ - - _rtw_memcpy(&stainfo->dot118021x_UncstKey, key->KeyMaterial, 16); - - if (encryptionalgo == _TKIP_) { - padapter->securitypriv.busetkipkey = _FALSE; - - /* if TKIP, save the Receive/Transmit MIC key in KeyMaterial[128-255] */ - if ((key->KeyIndex & 0x10000000)) { - _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 16, 8); - _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 24, 8); - - } else { - _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 24, 8); - _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 16, 8); - - } - - } else if (encryptionalgo == _AES_) { - - } - - - /* Set key to CAM through H2C command */ -#if 0 - if (bgrouptkey) { /* never go to here */ - res = rtw_setstakey_cmd(padapter, stainfo, GROUP_KEY, _TRUE); - } else { - res = rtw_setstakey_cmd(padapter, stainfo, UNICAST_KEY, _TRUE); - } -#else - - res = rtw_setstakey_cmd(padapter, stainfo, UNICAST_KEY, _TRUE); -#endif - - if (res == _FALSE) - ret = _FAIL; - - } - - } - -exit: - - - return ret; -} - -u8 rtw_set_802_11_remove_key(_adapter *padapter, NDIS_802_11_REMOVE_KEY *key) -{ - - uint encryptionalgo; - u8 *pbssid; - struct sta_info *stainfo; - u8 bgroup = (key->KeyIndex & 0x4000000) > 0 ? _FALSE : _TRUE; - u8 keyIndex = (u8)key->KeyIndex & 0x03; - u8 ret = _SUCCESS; - - - if ((key->KeyIndex & 0xbffffffc) > 0) { - ret = _FAIL; - goto exit; - } - - if (bgroup == _TRUE) { - encryptionalgo = padapter->securitypriv.dot118021XGrpPrivacy; - /* clear group key by index */ - /* NdisZeroMemory(Adapter->MgntInfo.SecurityInfo.KeyBuf[keyIndex], MAX_WEP_KEY_LEN); */ - /* Adapter->MgntInfo.SecurityInfo.KeyLen[keyIndex] = 0; */ - - _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[keyIndex], 0, 16); - - /* ! \todo Send a H2C Command to Firmware for removing this Key in CAM Entry. */ - - } else { - - pbssid = get_bssid(&padapter->mlmepriv); - stainfo = rtw_get_stainfo(&padapter->stapriv , pbssid); - if (stainfo != NULL) { - encryptionalgo = stainfo->dot118021XPrivacy; - - /* clear key by BSSID */ - _rtw_memset(&stainfo->dot118021x_UncstKey, 0, 16); - - /* ! \todo Send a H2C Command to Firmware for disable this Key in CAM Entry. */ - - } else { - ret = _FAIL; - goto exit; - } - } - -exit: - - - return _TRUE; - -} - /* * rtw_get_cur_max_rate - * @adapter: pointer to _adapter structure @@ -1146,20 +793,20 @@ u16 rtw_get_cur_max_rate(_adapter *adapter) if (psta == NULL) return 0; - short_GI = query_ra_short_GI(psta, psta->bw_mode); + short_GI = query_ra_short_GI(psta, rtw_get_tx_bw_mode(adapter, psta)); #ifdef CONFIG_80211N_HT if (is_supported_ht(psta->wireless_mode)) { rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); max_rate = rtw_mcs_rate(rf_type - , (psta->bw_mode == CHANNEL_WIDTH_40) ? 1 : 0 + , (psta->cmn.bw_mode == CHANNEL_WIDTH_40) ? 1 : 0 , short_GI , psta->htpriv.ht_cap.supp_mcs_set ); } #ifdef CONFIG_80211AC_VHT else if (is_supported_vht(psta->wireless_mode)) - max_rate = ((rtw_vht_mcs_to_data_rate(psta->bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10; + max_rate = ((rtw_vht_mcs_to_data_rate(psta->cmn.bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10; #endif /* CONFIG_80211AC_VHT */ else #endif /* CONFIG_80211N_HT */ @@ -1222,7 +869,8 @@ int rtw_set_country(_adapter *adapter, const char *country_code) #ifdef CONFIG_RTW_IOCTL_SET_COUNTRY return rtw_set_country_cmd(adapter, RTW_CMDF_WAIT_ACK, country_code, 1); #else - return _FAIL; + RTW_INFO("%s(): not applied\n", __func__); + return _SUCCESS; #endif } diff --git a/core/rtw_mi.c b/core/rtw_mi.c index c4e1487..bef596b 100644 --- a/core/rtw_mi.c +++ b/core/rtw_mi.c @@ -27,6 +27,82 @@ void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw) iface_state->union_offset = offset; } +#ifdef CONFIG_P2P +static u8 _rtw_mi_p2p_listen_scan_chk(_adapter *adapter) +{ + int i; + _adapter *iface; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 p2p_listen_scan_state = _FALSE; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN) || + rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_SCAN)) { + p2p_listen_scan_state = _TRUE; + break; + } + } + return p2p_listen_scan_state; +} +#endif +u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter) +{ + u8 rst = _TRUE; + u8 u_ch, u_bw, u_offset; + u8 o_ch, o_bw, o_offset; + + u_ch = rtw_mi_get_union_chan(adapter); + u_bw = rtw_mi_get_union_bw(adapter); + u_offset = rtw_mi_get_union_offset(adapter); + + o_ch = rtw_get_oper_ch(adapter); + o_bw = rtw_get_oper_bw(adapter); + o_offset = rtw_get_oper_choffset(adapter); + + if ((u_ch != o_ch) || (u_bw != o_bw) || (u_offset != o_offset)) + rst = _FALSE; + + #ifdef DBG_IFACE_STATUS + if (rst == _FALSE) { + RTW_ERR("%s Not stay in union channel\n", __func__); + if (GET_HAL_DATA(adapter)->bScanInProcess == _TRUE) + RTW_ERR("ScanInProcess\n"); + #ifdef CONFIG_P2P + if (_rtw_mi_p2p_listen_scan_chk(adapter)) + RTW_ERR("P2P in listen or scan state\n"); + #endif + RTW_ERR("union ch, bw, offset: %u,%u,%u\n", u_ch, u_bw, u_offset); + RTW_ERR("oper ch, bw, offset: %u,%u,%u\n", o_ch, o_bw, o_offset); + RTW_ERR("=========================\n"); + } + #endif + return rst; +} + +u8 rtw_mi_stayin_union_band_chk(_adapter *adapter) +{ + u8 rst = _TRUE; + u8 u_ch, o_ch; + u8 u_band, o_band; + + u_ch = rtw_mi_get_union_chan(adapter); + o_ch = rtw_get_oper_ch(adapter); + u_band = (u_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G; + o_band = (o_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G; + + if (u_ch != o_ch) + if(u_band != o_band) + rst = _FALSE; + + #ifdef DBG_IFACE_STATUS + if (rst == _FALSE) + RTW_ERR("%s Not stay in union band\n", __func__); + #endif + + return rst; +} + /* Find union about ch, bw, ch_offset of all linked/linking interfaces */ int _rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset, bool include_self) { @@ -105,8 +181,12 @@ inline int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw return _rtw_mi_get_ch_setting_union(adapter, ch, bw, offset, 0); } +#define MI_STATUS_SELF_ONLY 0 +#define MI_STATUS_OTHERS_ONLY 1 +#define MI_STATUS_ALL 2 + /* For now, not return union_ch/bw/offset */ -void _rtw_mi_status(_adapter *adapter, struct mi_state *mstate, bool include_self) +void _rtw_mi_status(_adapter *adapter, struct mi_state *mstate, u8 target_sel) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); _adapter *iface; @@ -117,23 +197,33 @@ void _rtw_mi_status(_adapter *adapter, struct mi_state *mstate, bool include_sel for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; - if (include_self == _FALSE && iface == adapter) + if (target_sel == MI_STATUS_SELF_ONLY && iface != adapter) + continue; + if (target_sel == MI_STATUS_OTHERS_ONLY && iface == adapter) continue; if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) { MSTATE_STA_NUM(mstate)++; - if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) + if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) { MSTATE_STA_LD_NUM(mstate)++; + #ifdef CONFIG_TDLS + if (iface->tdlsinfo.link_established == _TRUE) + MSTATE_TDLS_LD_NUM(mstate)++; + #endif + } if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING) == _TRUE) MSTATE_STA_LG_NUM(mstate)++; - } else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE - && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE - ) { - MSTATE_AP_NUM(mstate)++; - if (iface->stapriv.asoc_sta_count > 2) - MSTATE_AP_LD_NUM(mstate)++; +#ifdef CONFIG_AP_MODE + } else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) { + if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) { + MSTATE_AP_NUM(mstate)++; + if (iface->stapriv.asoc_sta_count > 2) + MSTATE_AP_LD_NUM(mstate)++; + } else + MSTATE_AP_STARTING_NUM(mstate)++; +#endif } else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE @@ -141,11 +231,29 @@ void _rtw_mi_status(_adapter *adapter, struct mi_state *mstate, bool include_sel MSTATE_ADHOC_NUM(mstate)++; if (iface->stapriv.asoc_sta_count > 2) MSTATE_ADHOC_LD_NUM(mstate)++; + +#ifdef CONFIG_RTW_MESH + } else if (check_fwstate(&iface->mlmepriv, WIFI_MESH_STATE) == _TRUE + && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE + ) { + MSTATE_MESH_NUM(mstate)++; + if (iface->stapriv.asoc_sta_count > 2) + MSTATE_MESH_LD_NUM(mstate)++; +#endif + } if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_WPS) == _TRUE) MSTATE_WPS_NUM(mstate)++; + if (check_fwstate(&iface->mlmepriv, WIFI_SITE_MONITOR) == _TRUE) { + MSTATE_SCAN_NUM(mstate)++; + + if (mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_DISABLE + && mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_BACK_OP) + MSTATE_SCAN_ENTER_NUM(mstate)++; + } + #ifdef CONFIG_IOCTL_CFG80211 if (rtw_cfg80211_get_is_mgmt_tx(iface)) MSTATE_MGMT_TX_NUM(mstate)++; @@ -160,32 +268,80 @@ void _rtw_mi_status(_adapter *adapter, struct mi_state *mstate, bool include_sel inline void rtw_mi_status(_adapter *adapter, struct mi_state *mstate) { - return _rtw_mi_status(adapter, mstate, 1); + return _rtw_mi_status(adapter, mstate, MI_STATUS_ALL); } + inline void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate) { - return _rtw_mi_status(adapter, mstate, 0); + return _rtw_mi_status(adapter, mstate, MI_STATUS_OTHERS_ONLY); } + +inline void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate) +{ + return _rtw_mi_status(adapter, mstate, MI_STATUS_SELF_ONLY); +} + +/* For now, not handle union_ch/bw/offset */ +inline void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a) +{ + d->sta_num += a->sta_num; + d->ld_sta_num += a->ld_sta_num; + d->lg_sta_num += a->lg_sta_num; +#ifdef CONFIG_TDLS + d->ld_tdls_num += a->ld_tdls_num; +#endif +#ifdef CONFIG_AP_MODE + d->ap_num += a->ap_num; + d->ld_ap_num += a->ld_ap_num; +#endif + d->adhoc_num += a->adhoc_num; + d->ld_adhoc_num += a->ld_adhoc_num; +#ifdef CONFIG_RTW_MESH + d->mesh_num += a->mesh_num; + d->ld_mesh_num += a->ld_mesh_num; +#endif + d->scan_num += a->scan_num; + d->scan_enter_num += a->scan_enter_num; + d->uwps_num += a->uwps_num; +#ifdef CONFIG_IOCTL_CFG80211 + #ifdef CONFIG_P2P + d->roch_num += a->roch_num; + #endif + d->mgmt_tx_num += a->mgmt_tx_num; +#endif +} + void dump_mi_status(void *sel, struct dvobj_priv *dvobj) { RTW_PRINT_SEL(sel, "== dvobj-iface_state ==\n"); RTW_PRINT_SEL(sel, "sta_num:%d\n", DEV_STA_NUM(dvobj)); RTW_PRINT_SEL(sel, "linking_sta_num:%d\n", DEV_STA_LG_NUM(dvobj)); RTW_PRINT_SEL(sel, "linked_sta_num:%d\n", DEV_STA_LD_NUM(dvobj)); +#ifdef CONFIG_TDLS + RTW_PRINT_SEL(sel, "linked_tdls_num:%d\n", DEV_TDLS_LD_NUM(dvobj)); +#endif +#ifdef CONFIG_AP_MODE RTW_PRINT_SEL(sel, "ap_num:%d\n", DEV_AP_NUM(dvobj)); + RTW_PRINT_SEL(sel, "starting_ap_num:%d\n", DEV_AP_STARTING_NUM(dvobj)); RTW_PRINT_SEL(sel, "linked_ap_num:%d\n", DEV_AP_LD_NUM(dvobj)); +#endif RTW_PRINT_SEL(sel, "adhoc_num:%d\n", DEV_ADHOC_NUM(dvobj)); RTW_PRINT_SEL(sel, "linked_adhoc_num:%d\n", DEV_ADHOC_LD_NUM(dvobj)); +#ifdef CONFIG_RTW_MESH + RTW_PRINT_SEL(sel, "mesh_num:%d\n", DEV_MESH_NUM(dvobj)); + RTW_PRINT_SEL(sel, "linked_mesh_num:%d\n", DEV_MESH_LD_NUM(dvobj)); +#endif #ifdef CONFIG_P2P - RTW_PRINT_SEL(sel, "p2p_device_num:%d\n", rtw_mi_stay_in_p2p_mode(dvobj->padapters[IFACE_ID0])); + RTW_PRINT_SEL(sel, "p2p_device_num:%d\n", rtw_mi_stay_in_p2p_mode(dvobj_get_primary_adapter(dvobj))); #endif + RTW_PRINT_SEL(sel, "scan_num:%d\n", DEV_SCAN_NUM(dvobj)); + RTW_PRINT_SEL(sel, "under_wps_num:%d\n", DEV_WPS_NUM(dvobj)); #if defined(CONFIG_IOCTL_CFG80211) #if defined(CONFIG_P2P) RTW_PRINT_SEL(sel, "roch_num:%d\n", DEV_ROCH_NUM(dvobj)); #endif RTW_PRINT_SEL(sel, "mgmt_tx_num:%d\n", DEV_MGMT_TX_NUM(dvobj)); #endif - RTW_PRINT_SEL(sel, "under_wps_num:%d\n", DEV_WPS_NUM(dvobj)); RTW_PRINT_SEL(sel, "union_ch:%d\n", DEV_U_CH(dvobj)); RTW_PRINT_SEL(sel, "union_bw:%d\n", DEV_U_BW(dvobj)); RTW_PRINT_SEL(sel, "union_offset:%d\n", DEV_U_OFFSET(dvobj)); @@ -209,7 +365,6 @@ inline void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state) _adapter *iface; if (state == WIFI_MONITOR_STATE - || state == WIFI_SITE_MONITOR || state == 0xFFFFFFFF ) return; @@ -247,11 +402,11 @@ u8 rtw_mi_check_status(_adapter *adapter, u8 type) switch (type) { case MI_LINKED: - if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_NUM(iface_state) || MSTATE_ADHOC_NUM(iface_state)) /*check_fwstate(&iface->mlmepriv, _FW_LINKED)*/ + if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_NUM(iface_state) || MSTATE_ADHOC_NUM(iface_state) || MSTATE_MESH_NUM(iface_state)) /*check_fwstate(&iface->mlmepriv, _FW_LINKED)*/ ret = _TRUE; break; case MI_ASSOC: - if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_LD_NUM(iface_state) || MSTATE_ADHOC_LD_NUM(iface_state)) + if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_LD_NUM(iface_state) || MSTATE_ADHOC_LD_NUM(iface_state) || MSTATE_MESH_LD_NUM(iface_state)) ret = _TRUE; break; case MI_UNDER_WPS: @@ -277,6 +432,17 @@ u8 rtw_mi_check_status(_adapter *adapter, u8 type) ret = _TRUE; break; +#ifdef CONFIG_RTW_MESH + case MI_MESH: + if (MSTATE_MESH_NUM(iface_state)) + ret = _TRUE; + break; + case MI_MESH_ASSOC: + if (MSTATE_MESH_LD_NUM(iface_state)) + ret = _TRUE; + break; +#endif + case MI_STA_NOLINK: /* this is misleading, but not used now */ if (MSTATE_STA_NUM(iface_state) && (!(MSTATE_STA_LD_NUM(iface_state) || MSTATE_STA_LG_NUM(iface_state)))) ret = _TRUE; @@ -347,27 +513,54 @@ static u8 _rtw_mi_process_without_schk(_adapter *padapter, bool exclude_self, return ret; } -static u8 _rtw_mi_netif_stop_queue(_adapter *padapter, void *data) +static u8 _rtw_mi_netif_caroff_qstop(_adapter *padapter, void *data) { - bool carrier_off = *(bool *)data; struct net_device *pnetdev = padapter->pnetdev; - if (carrier_off) - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); return _TRUE; } -u8 rtw_mi_netif_stop_queue(_adapter *padapter, bool carrier_off) +u8 rtw_mi_netif_caroff_qstop(_adapter *padapter) { - bool in_data = carrier_off; + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caroff_qstop); +} +u8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caroff_qstop); +} - return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_netif_stop_queue); +static u8 _rtw_mi_netif_caron_qstart(_adapter *padapter, void *data) +{ + struct net_device *pnetdev = padapter->pnetdev; + + rtw_netif_carrier_on(pnetdev); + rtw_netif_start_queue(pnetdev); + return _TRUE; +} +u8 rtw_mi_netif_caron_qstart(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caron_qstart); } -u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter, bool carrier_off) +u8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter) { - bool in_data = carrier_off; + return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caron_qstart); +} - return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_netif_stop_queue); +static u8 _rtw_mi_netif_stop_queue(_adapter *padapter, void *data) +{ + struct net_device *pnetdev = padapter->pnetdev; + + rtw_netif_stop_queue(pnetdev); + return _TRUE; +} +u8 rtw_mi_netif_stop_queue(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_stop_queue); +} +u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_stop_queue); } static u8 _rtw_mi_netif_wake_queue(_adapter *padapter, void *data) @@ -404,6 +597,23 @@ u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter) return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_on); } +static u8 _rtw_mi_netif_carrier_off(_adapter *padapter, void *data) +{ + struct net_device *pnetdev = padapter->pnetdev; + + if (pnetdev) + rtw_netif_carrier_off(pnetdev); + return _TRUE; +} +u8 rtw_mi_netif_carrier_off(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_carrier_off); +} +u8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_off); +} + static u8 _rtw_mi_scan_abort(_adapter *adapter, void *data) { bool bwait = *(bool *)data; @@ -429,32 +639,57 @@ void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait) _rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_scan_abort); } -static u8 _rtw_mi_start_drv_threads(_adapter *adapter, void *data) +static u32 _rtw_mi_start_drv_threads(_adapter *adapter, bool exclude_self) { - rtw_start_drv_threads(adapter); - return _TRUE; + int i; + _adapter *iface = NULL; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u32 _status = _SUCCESS; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + if ((exclude_self) && (iface == adapter)) + continue; + if (rtw_start_drv_threads(iface) == _FAIL) { + _status = _FAIL; + break; + } + } + } + return _status; } -void rtw_mi_start_drv_threads(_adapter *adapter) +u32 rtw_mi_start_drv_threads(_adapter *adapter) { - _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_start_drv_threads); + return _rtw_mi_start_drv_threads(adapter, _FALSE); } -void rtw_mi_buddy_start_drv_threads(_adapter *adapter) +u32 rtw_mi_buddy_start_drv_threads(_adapter *adapter) { - _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_start_drv_threads); + return _rtw_mi_start_drv_threads(adapter, _TRUE); } -static u8 _rtw_mi_stop_drv_threads(_adapter *adapter, void *data) +static void _rtw_mi_stop_drv_threads(_adapter *adapter, bool exclude_self) { - rtw_stop_drv_threads(adapter); - return _TRUE; + int i; + _adapter *iface = NULL; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + if ((exclude_self) && (iface == adapter)) + continue; + rtw_stop_drv_threads(iface); + } + } } void rtw_mi_stop_drv_threads(_adapter *adapter) { - _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_stop_drv_threads); + _rtw_mi_stop_drv_threads(adapter, _FALSE); } void rtw_mi_buddy_stop_drv_threads(_adapter *adapter) { - _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_stop_drv_threads); + _rtw_mi_stop_drv_threads(adapter, _TRUE); } static u8 _rtw_mi_cancel_all_timer(_adapter *adapter, void *data) @@ -563,56 +798,12 @@ void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms) } #endif /*CONFIG_SET_SCAN_DENY_TIMER*/ -struct nulldata_param { - unsigned char *da; - unsigned int power_mode; - int try_cnt; - int wait_ms; -}; - -static u8 _rtw_mi_issue_nulldata(_adapter *padapter, void *data) -{ - struct nulldata_param *pnulldata_param = (struct nulldata_param *)data; - - if (is_client_associated_to_ap(padapter) == _TRUE) { - /* TODO: TDLS peers */ - issue_nulldata(padapter, pnulldata_param->da, pnulldata_param->power_mode, pnulldata_param->try_cnt, pnulldata_param->wait_ms); - return _TRUE; - } - return _FALSE; -} - -u8 rtw_mi_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms) -{ - struct nulldata_param nparam; - - nparam.da = da; - nparam.power_mode = power_mode;/*0 or 1*/ - nparam.try_cnt = try_cnt; - nparam.wait_ms = wait_ms; - - return _rtw_mi_process(padapter, _FALSE, &nparam, _rtw_mi_issue_nulldata); -} -u8 rtw_mi_buddy_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms) -{ - struct nulldata_param nparam; - - nparam.da = da; - nparam.power_mode = power_mode; - nparam.try_cnt = try_cnt; - nparam.wait_ms = wait_ms; - - return _rtw_mi_process(padapter, _TRUE, &nparam, _rtw_mi_issue_nulldata); -} - static u8 _rtw_mi_beacon_update(_adapter *padapter, void *data) { - struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; - - if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE + if (!MLME_IS_STA(padapter) && check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE) { - RTW_INFO(ADPT_FMT"-WIFI_FW_AP_STATE - update_beacon\n", ADPT_ARG(padapter)); - update_beacon(padapter, 0, NULL, _TRUE); + RTW_INFO(ADPT_FMT" - update_beacon\n", ADPT_ARG(padapter)); + update_beacon(padapter, 0xFF, NULL, _TRUE); } return _TRUE; } @@ -631,7 +822,7 @@ static u8 _rtw_mi_hal_dump_macaddr(_adapter *padapter, void *data) { u8 mac_addr[ETH_ALEN] = {0}; - rtw_hal_get_macaddr_port(padapter, mac_addr); + rtw_hal_get_hwreg(padapter, HW_VAR_MAC_ADDR, mac_addr); RTW_INFO(ADPT_FMT"MAC Address ="MAC_FMT"\n", ADPT_ARG(padapter), MAC_ARG(mac_addr)); return _TRUE; } @@ -980,9 +1171,9 @@ u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart) } static u8 _rtw_mi_tx_beacon_hdl(_adapter *adapter, void *data) { - if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE - && check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE - ) { + if ((MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) + && check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE + ) { adapter->mlmepriv.update_bcn = _TRUE; #ifndef CONFIG_INTERRUPT_BASED_TXBCN #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) @@ -1005,7 +1196,7 @@ static u8 _rtw_mi_set_tx_beacon_cmd(_adapter *adapter, void *data) { struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) { if (pmlmepriv->update_bcn == _TRUE) set_tx_beacon_cmd(adapter); } @@ -1191,7 +1382,7 @@ static s32 _rtw_mi_buddy_clone_bcmc_packet(_adapter *adapter, union recv_frame * rtw_dbg_skb_process(adapter, precvframe, pcloneframe); #endif - if (pattrib->physt && pphy_status) + if (pphy_status) rx_query_phy_status(pcloneframe, pphy_status); ret = rtw_recv_entry(pcloneframe); @@ -1213,6 +1404,8 @@ void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvf struct recv_priv *precvpriv = &padapter->recvpriv;/*primary_padapter*/ _queue *pfree_recv_queue = &precvpriv->free_recv_queue; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u8 *fhead = get_recvframe_data(precvframe); + u8 type = GetFrameType(fhead); for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -1220,6 +1413,8 @@ void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvf continue; if (rtw_is_adapter_up(iface) == _FALSE || iface->registered == 0) continue; + if (type == WIFI_DATA_TYPE && !adapter_allow_bmc_data_rx(iface)) + continue; pcloneframe = rtw_alloc_recvframe(pfree_recv_queue); if (pcloneframe) { @@ -1281,27 +1476,3 @@ void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b) #endif } -#ifdef CONFIG_AP_MODE -static u8 _rtw_mi_ap_acdata_control(_adapter *padapter, void *data) -{ - u8 power_mode = *(u8 *)data; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) - rtw_ap_acdata_control(padapter, power_mode); - return _TRUE; -} - -void rtw_mi_ap_acdata_control(_adapter *padapter, u8 power_mode) -{ - u8 in_data = power_mode; - - _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_ap_acdata_control); -} -void rtw_mi_buddy_ap_acdata_control(_adapter *padapter, u8 power_mode) -{ - u8 in_data = power_mode; - - _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_ap_acdata_control); -} -#endif /*CONFIG_AP_MODE*/ diff --git a/core/rtw_mlme.c b/core/rtw_mlme.c index 74363ca..d37dd72 100644 --- a/core/rtw_mlme.c +++ b/core/rtw_mlme.c @@ -127,14 +127,17 @@ sint _rtw_init_mlme_priv(_adapter *padapter) pmlmepriv->roam_rssi_diff_th = RTW_ROAM_RSSI_DIFF_TH; pmlmepriv->roam_scan_int_ms = RTW_ROAM_SCAN_INTERVAL_MS; pmlmepriv->roam_rssi_threshold = RTW_ROAM_RSSI_THRESHOLD; + pmlmepriv->need_to_roam = _FALSE; #endif /* CONFIG_LAYER2_ROAMING */ #ifdef CONFIG_RTW_80211R - memset(&pmlmepriv->ftpriv, 0, sizeof(ft_priv)); - pmlmepriv->ftpriv.ft_flags = 0 - | RTW_FT_STA_SUPPORTED - | RTW_FT_STA_OVER_DS_SUPPORTED - ; + rtw_ft_info_init(&pmlmepriv->ft_roam); +#endif +#ifdef CONFIG_LAYER2_ROAMING +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) + rtw_roam_nb_info_init(padapter); + pmlmepriv->ch_cnt = 0; +#endif #endif rtw_init_mlme_timer(padapter); @@ -458,53 +461,6 @@ void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network * return; } - -/* - return the wlan_network with the matching addr - - Shall be calle under atomic context... to avoid possible racing condition... -*/ -struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr) -{ - - /* _irqL irqL; */ - _list *phead, *plist; - struct wlan_network *pnetwork = NULL; - u8 zero_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; - - - if (_rtw_memcmp(zero_addr, addr, ETH_ALEN)) { - pnetwork = NULL; - goto exit; - } - - /* _enter_critical_bh(&scanned_queue->lock, &irqL); */ - - phead = get_list_head(scanned_queue); - plist = get_next(phead); - - while (plist != phead) { - pnetwork = LIST_CONTAINOR(plist, struct wlan_network , list); - - if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) - break; - - plist = get_next(plist); - } - - if (plist == phead) - pnetwork = NULL; - - /* _exit_critical_bh(&scanned_queue->lock, &irqL); */ - -exit: - - - return pnetwork; - -} - - void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall) { _irqL irqL; @@ -645,14 +601,44 @@ void rtw_free_network_queue(_adapter *dev, u8 isfreeall) _rtw_free_network_queue(dev, isfreeall); } -/* - return the wlan_network with the matching addr +struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr) +{ + _list *phead, *plist; + struct wlan_network *pnetwork = NULL; + u8 zero_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; - Shall be calle under atomic context... to avoid possible racing condition... -*/ -struct wlan_network *rtw_find_network(_queue *scanned_queue, u8 *addr) + if (_rtw_memcmp(zero_addr, addr, ETH_ALEN)) { + pnetwork = NULL; + goto exit; + } + + phead = get_list_head(scanned_queue); + plist = get_next(phead); + + while (plist != phead) { + pnetwork = LIST_CONTAINOR(plist, struct wlan_network , list); + + if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) + break; + + plist = get_next(plist); + } + + if (plist == phead) + pnetwork = NULL; + +exit: + return pnetwork; +} + +struct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr) { - struct wlan_network *pnetwork = _rtw_find_network(scanned_queue, addr); + struct wlan_network *pnetwork; + _irqL irqL; + + _enter_critical_bh(&scanned_queue->lock, &irqL); + pnetwork = _rtw_find_network(scanned_queue, addr); + _exit_critical_bh(&scanned_queue->lock, &irqL); return pnetwork; } @@ -704,15 +690,35 @@ int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature) return _TRUE; #endif - return ((src->Ssid.SsidLength == dst->Ssid.SsidLength) && - /* (src->Configuration.DSConfig == dst->Configuration.DSConfig) && */ - ((_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) && - ((_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) && - ((s_cap & WLAN_CAPABILITY_IBSS) == - (d_cap & WLAN_CAPABILITY_IBSS)) && - ((s_cap & WLAN_CAPABILITY_BSS) == - (d_cap & WLAN_CAPABILITY_BSS))); - + /* Wi-Fi driver doesn't consider the situation of BCN and ProbRsp sent from the same hidden AP, + * it considers these two packets are sent from different AP. + * Therefore, the scan queue may store two scan results of the same hidden AP, likes below. + * + * index bssid ch RSSI SdBm Noise age flag ssid + * 1 00:e0:4c:55:50:01 153 -73 -73 0 7044 [WPS][ESS] RTK5G + * 3 00:e0:4c:55:50:01 153 -73 -73 0 7044 [WPS][ESS] + * + * Original rules will compare Ssid, SsidLength, MacAddress, s_cap, d_cap at the same time. + * Wi-Fi driver will assume that the BCN and ProbRsp sent from the same hidden AP are the same network + * after we add an additional rule to compare SsidLength and Ssid. + * It means the scan queue will not store two scan results of the same hidden AP, it only store ProbRsp. + * For customer request. + */ + + if (((_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) && + ((s_cap & WLAN_CAPABILITY_IBSS) == (d_cap & WLAN_CAPABILITY_IBSS)) && + ((s_cap & WLAN_CAPABILITY_BSS) == (d_cap & WLAN_CAPABILITY_BSS))) { + if ((src->Ssid.SsidLength == dst->Ssid.SsidLength) && + (((_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) || //Case of normal AP + (is_all_null(src->Ssid.Ssid, src->Ssid.SsidLength) == _TRUE || is_all_null(dst->Ssid.Ssid, dst->Ssid.SsidLength) == _TRUE))) //Case of hidden AP + return _TRUE; + else if ((src->Ssid.SsidLength == 0 || dst->Ssid.SsidLength == 0)) //Case of hidden AP + return _TRUE; + else + return _FALSE; + } else { + return _FALSE; + } } struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network) @@ -773,7 +779,7 @@ struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue) pwlan = LIST_CONTAINOR(plist, struct wlan_network, list); if (pwlan->fixed != _TRUE) { - if (oldest == NULL || time_after(oldest->last_scanned, pwlan->last_scanned)) + if (oldest == NULL || rtw_time_after(oldest->last_scanned, pwlan->last_scanned)) oldest = pwlan; } @@ -920,7 +926,7 @@ Caller must hold pmlmepriv->lock first. */ -void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) +bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) { _irqL irqL; _list *plist, *phead; @@ -935,7 +941,7 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) struct wlan_network *oldest = NULL; int target_find = 0; u8 feature = 0; - + bool update_ie = _FALSE; _enter_critical_bh(&queue->lock, &irqL); phead = get_list_head(queue); @@ -977,10 +983,18 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) } #ifdef CONFIG_RSSI_PRIORITY if ((oldest == NULL) || (pnetwork->network.PhyInfo.SignalStrength < oldest->network.PhyInfo.SignalStrength)) - oldest = pnetwork; + #ifdef CONFIG_RTW_MESH + if (!MLME_IS_MESH(adapter) || check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE + || !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network)) + #endif + oldest = pnetwork; #else - if (oldest == NULL || time_after(oldest->last_scanned, pnetwork->last_scanned)) - oldest = pnetwork; + if (oldest == NULL || rtw_time_after(oldest->last_scanned, pnetwork->last_scanned)) + #ifdef CONFIG_RTW_MESH + if (!MLME_IS_MESH(adapter) || check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE + || !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network)) + #endif + oldest = pnetwork; #endif plist = get_next(plist); @@ -995,9 +1009,9 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) /* If there are no more slots, expire the oldest */ /* list_del_init(&oldest->list); */ pnetwork = oldest; - if (pnetwork == NULL) { - goto exit; - } + if (pnetwork == NULL) + goto unlock_scan_queue; + #ifdef CONFIG_RSSI_PRIORITY RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue (rssi:%ld , ss:%d)\n", __func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Rssi, pnetwork->network.PhyInfo.SignalStrength); @@ -1026,10 +1040,8 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) /* Otherwise just pull from the free list */ pnetwork = rtw_alloc_network(pmlmepriv); /* will update scan_time */ - - if (pnetwork == NULL) { - goto exit; - } + if (pnetwork == NULL) + goto unlock_scan_queue; bssid_ex_sz = get_WLAN_BSSID_EX_sz(target); target->Length = bssid_ex_sz; @@ -1052,18 +1064,18 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) * be already expired. In this case we do the same as we found a new * net and call the new_net handler */ - bool update_ie = _TRUE; pnetwork->last_scanned = rtw_get_current_time(); - /* target.Reserved[0]==1, means that scaned network is a bcn frame. */ - if ((pnetwork->network.IELength > target->IELength) && (target->Reserved[0] == 1)) + /* target.Reserved[0]==BSS_TYPE_BCN, means that scanned network is a bcn frame. */ + if ((pnetwork->network.IELength > target->IELength) && (target->Reserved[0] == BSS_TYPE_BCN)) update_ie = _FALSE; - /* probe resp(3) > beacon(1) > probe req(2) */ - if ((target->Reserved[0] != 2) && - (target->Reserved[0] >= pnetwork->network.Reserved[0]) - ) + if (MLME_IS_MESH(adapter) + /* probe resp(3) > beacon(1) > probe req(2) */ + || (target->Reserved[0] != BSS_TYPE_PROB_REQ + && target->Reserved[0] >= pnetwork->network.Reserved[0]) + ) update_ie = _TRUE; else update_ie = _FALSE; @@ -1071,9 +1083,18 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) update_network(&(pnetwork->network), target, adapter, update_ie); } -exit: +unlock_scan_queue: _exit_critical_bh(&queue->lock, &irqL); +#ifdef CONFIG_RTW_MESH + if (pnetwork && MLME_IS_MESH(adapter) + && check_fwstate(pmlmepriv, WIFI_ASOC_STATE) + && !check_fwstate(pmlmepriv, WIFI_SITE_MONITOR) + ) + rtw_chk_candidate_peer_notify(adapter, pnetwork); +#endif + + return update_ie; } void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork); @@ -1081,6 +1102,7 @@ void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) { _irqL irqL; struct mlme_priv *pmlmepriv = &(((_adapter *)adapter)->mlmepriv); + bool update_ie; /* _queue *queue = &(pmlmepriv->scanned_queue); */ @@ -1094,9 +1116,11 @@ void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) rtw_bss_ex_del_wfd_ie(pnetwork); - update_current_network(adapter, pnetwork); + /* Wi-Fi driver will update the current network if the scan result of the connected AP be updated by scan. */ + update_ie = rtw_update_scanned_network(adapter, pnetwork); - rtw_update_scanned_network(adapter, pnetwork); + if (update_ie) + update_current_network(adapter, pnetwork); /* _exit_critical_bh(&queue->lock, &irqL); */ @@ -1215,7 +1239,7 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) _rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8); _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - ibss_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress); + ibss_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress); if (ibss_wlan) { _rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8); _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); @@ -1243,6 +1267,7 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) { _irqL irqL; + struct sitesurvey_parm parm; struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); #ifdef CONFIG_RTW_80211R struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; @@ -1322,8 +1347,13 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(adapter)); if (rtw_to_roam(adapter) != 0) { + + rtw_init_sitesurvey_parm(adapter, &parm); + _rtw_memcpy(&parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); + parm.ssid_num = 1; + if (rtw_dec_to_roam(adapter) == 0 - || _SUCCESS != rtw_sitesurvey_cmd(adapter, &pmlmepriv->assoc_ssid, 1, NULL, 0) + || _SUCCESS != rtw_sitesurvey_cmd(adapter, &parm) ) { rtw_set_to_roam(adapter, 0); #ifdef CONFIG_INTEL_WIDI @@ -1348,12 +1378,8 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) && check_fwstate(pmlmepriv, _FW_LINKED)) { if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) { #ifdef CONFIG_RTW_80211R - if (rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED)) { - start_clnt_ft_action(adapter, (u8 *)pmlmepriv->roam_network->network.MacAddress); - } else { - /*wait a little time to retrieve packets buffered in the current ap while scan*/ - _set_timer(&pmlmeext->ft_roam_timer, 30); - } + rtw_ft_start_roam(adapter, + (u8 *)pmlmepriv->roam_network->network.MacAddress); #else receive_disconnect(adapter, pmlmepriv->cur_network.network.MacAddress , WLAN_REASON_ACTIVE_ROAM, _FALSE); @@ -1397,6 +1423,20 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _FALSE); #endif +#ifdef CONFIG_RTW_MESH + #if CONFIG_RTW_MESH_OFFCH_CAND + if (rtw_mesh_offch_candidate_accepted(adapter)) { + u8 ch; + + ch = rtw_mesh_select_operating_ch(adapter); + if (ch && pmlmepriv->cur_network.network.Configuration.DSConfig != ch) { + /* trigger channel switch with bw specified by upper layer */ + rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ch, adapter->mlmepriv.ori_bw, -1); + issue_probereq_ex(adapter, &pmlmepriv->cur_network.network.mesh_id, NULL, 0, 0, 0, 0); + } + } + #endif +#endif /* CONFIG_RTW_MESH */ } void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf) @@ -1436,13 +1476,17 @@ static void free_scanqueue(struct mlme_priv *pmlmepriv) } -void rtw_reset_rx_info(struct debug_priv *pdbgpriv) +void rtw_reset_rx_info(_adapter *adapter) { - pdbgpriv->dbg_rx_ampdu_drop_count = 0; - pdbgpriv->dbg_rx_ampdu_forced_indicate_count = 0; - pdbgpriv->dbg_rx_ampdu_loss_count = 0; - pdbgpriv->dbg_rx_dup_mgt_frame_drop_count = 0; - pdbgpriv->dbg_rx_ampdu_window_shift_cnt = 0; + struct recv_priv *precvpriv = &adapter->recvpriv; + + precvpriv->dbg_rx_ampdu_drop_count = 0; + precvpriv->dbg_rx_ampdu_forced_indicate_count = 0; + precvpriv->dbg_rx_ampdu_loss_count = 0; + precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0; + precvpriv->dbg_rx_ampdu_window_shift_cnt = 0; + precvpriv->dbg_rx_drop_count = 0; + precvpriv->dbg_rx_conflic_mac_addr_cnt = 0; } /* @@ -1455,8 +1499,6 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) struct mlme_priv *pmlmepriv = &adapter->mlmepriv; struct sta_priv *pstapriv = &adapter->stapriv; struct wlan_network *tgt_network = &pmlmepriv->cur_network; - struct dvobj_priv *psdpriv = adapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; #ifdef CONFIG_TDLS @@ -1464,7 +1506,7 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) #endif /* CONFIG_TDLS */ - RTW_INFO("%s-"ADPT_FMT" tgt_network MacAddress=" MAC_FMT"ssid=%s\n", + RTW_INFO("%s-"ADPT_FMT" tgt_network MacAddress=" MAC_FMT" ssid=%s\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid); if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { @@ -1473,18 +1515,15 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); #ifdef CONFIG_TDLS - if (ptdlsinfo->link_established == _TRUE) { + rtw_free_all_tdls_sta(adapter, _TRUE); + rtw_reset_tdls_info(adapter); + + if (ptdlsinfo->link_established == _TRUE) rtw_tdls_cmd(adapter, NULL, TDLS_RS_RCR); - rtw_reset_tdls_info(adapter); - rtw_free_all_stainfo(adapter); - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - } else #endif /* CONFIG_TDLS */ - { - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - rtw_free_stainfo(adapter, psta); - } + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + rtw_free_stainfo(adapter, psta); /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ } @@ -1536,7 +1575,7 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) adapter->securitypriv.key_mask = 0; - rtw_reset_rx_info(pdbgpriv); + rtw_reset_rx_info(adapter); } @@ -1559,16 +1598,7 @@ void rtw_indicate_connect(_adapter *padapter) rtw_led_control(padapter, LED_CTL_LINK); - -#ifdef CONFIG_DRVEXT_MODULE - if (padapter->drvextpriv.enable_wpa) - indicate_l2_connect(padapter); - else -#endif - { - rtw_os_indicate_connect(padapter); - } - + rtw_os_indicate_connect(padapter); } rtw_set_to_roam(padapter, 0); @@ -1579,7 +1609,7 @@ void rtw_indicate_connect(_adapter *padapter) RTW_INFO("change to widi listen\n"); } #endif /* CONFIG_INTEL_WIDI */ - if (!check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE)) + if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) rtw_mi_set_scan_deny(padapter, 3000); @@ -1628,7 +1658,7 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate #ifdef CONFIG_WAPI_SUPPORT psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) - rtw_wapi_return_one_sta_info(padapter, psta->hwaddr); + rtw_wapi_return_one_sta_info(padapter, psta->cmn.mac_addr); else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) rtw_wapi_return_all_sta_info(padapter); @@ -1689,7 +1719,7 @@ inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted) static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms) { - u32 start; + systime start; u32 pass_ms; struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); @@ -1730,23 +1760,11 @@ static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms) void rtw_scan_wait_completed(_adapter *adapter) { - u32 scan_to; -#ifdef CONFIG_CHNL_LOAD_MAGT - if (adapter->clm_flag == TRUE) - scan_to = CLM_SCANNING_TIMEOUT; - else -#endif - scan_to = SCANNING_TIMEOUT; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct ss_res *ss = &pmlmeext->sitesurvey_res; -#ifdef CONFIG_SCAN_BACKOP - if (is_supported_5g(adapter->registrypriv.wireless_mode) - && IsSupported24G(adapter->registrypriv.wireless_mode)) /*dual band*/ - scan_to = CONC_SCANNING_TIMEOUT_DUAL_BAND; - else /*single band*/ - scan_to = CONC_SCANNING_TIMEOUT_SINGLE_BAND; -#endif /* CONFIG_SCAN_BACKOP */ - - _rtw_wait_scan_done(adapter, _FALSE, scan_to); + _rtw_wait_scan_done(adapter, _FALSE, ss->scan_timeout_ms); } u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms) @@ -1768,10 +1786,59 @@ void rtw_scan_abort(_adapter *adapter) rtw_scan_abort_timeout(adapter, 200); } +static u32 _rtw_wait_join_done(_adapter *adapter, u8 abort, u32 timeout_ms) +{ + systime start; + u32 pass_ms; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + + start = rtw_get_current_time(); + + pmlmeext->join_abort = abort; + if (abort) + set_link_timer(pmlmeext, 1); + + while (rtw_get_passing_time_ms(start) <= timeout_ms + && (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) + #ifdef CONFIG_IOCTL_CFG80211 + || rtw_cfg80211_is_connect_requested(adapter) + #endif + ) + ) { + if (RTW_CANNOT_RUN(adapter)) + break; + + RTW_INFO(FUNC_ADPT_FMT" linking...\n", FUNC_ADPT_ARG(adapter)); + rtw_msleep_os(20); + } + + if (abort) { + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) + #ifdef CONFIG_IOCTL_CFG80211 + || rtw_cfg80211_is_connect_requested(adapter) + #endif + ) { + if (!RTW_CANNOT_RUN(adapter)) + RTW_INFO(FUNC_ADPT_FMT" waiting for join_abort time out!\n", FUNC_ADPT_ARG(adapter)); + } + } + + pmlmeext->join_abort = 0; + pass_ms = rtw_get_passing_time_ms(start); + + return pass_ms; +} + +u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms) +{ + return _rtw_wait_join_done(adapter, _TRUE, timeout_ms); +} + static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork) { int i; - struct sta_info *bmc_sta, *psta = NULL; + struct sta_info *psta = NULL; struct recv_reorder_ctrl *preorder_ctrl; struct sta_priv *pstapriv = &padapter->stapriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; @@ -1783,58 +1850,51 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl if (psta) { /* update ptarget_sta */ RTW_INFO("%s\n", __FUNCTION__); - psta->aid = pnetwork->join_res; - -#if 0 /* alloc macid when call rtw_alloc_stainfo(), and release macid when call rtw_free_stainfo() */ -#ifdef CONFIG_CONCURRENT_MODE - - if (PRIMARY_ADAPTER == padapter->adapter_type) - psta->mac_id = 0; - else - psta->mac_id = 2; -#else - psta->mac_id = 0; -#endif -#endif /* removed */ + psta->cmn.aid = pnetwork->join_res; update_sta_info(padapter, psta); /* update station supportRate */ psta->bssratelen = rtw_get_rateset_len(pnetwork->network.SupportedRates); _rtw_memcpy(psta->bssrateset, pnetwork->network.SupportedRates, psta->bssratelen); - rtw_hal_update_sta_rate_mask(padapter, psta); + rtw_hal_update_sta_ra_info(padapter, psta); psta->wireless_mode = pmlmeext->cur_wireless_mode; - psta->raid = rtw_hal_networktype_to_raid(padapter, psta); - + rtw_hal_update_sta_wset(padapter, psta); /* sta mode */ rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); /* security related */ #ifdef CONFIG_RTW_80211R - if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (psta->ft_pairwise_key_installed == _FALSE)) { + if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) + && (psta->ft_pairwise_key_installed == _FALSE)) { #else if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { #endif + u8 *ie; + sint ie_len; + u8 mfp_opt = MFP_NO; + padapter->securitypriv.binstallGrpkey = _FALSE; padapter->securitypriv.busetkipkey = _FALSE; padapter->securitypriv.bgrpkey_handshake = _FALSE; + ie = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, WLAN_EID_RSN + , &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_)); + if (ie && ie_len > 0 + && rtw_parse_wpa2_ie(ie, ie_len + 2, NULL, NULL, NULL, &mfp_opt) == _SUCCESS + ) { + if (padapter->securitypriv.mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL) + psta->flags |= WLAN_STA_MFP; + } + psta->ieee8021x_blocked = _TRUE; psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; _rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype)); - _rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype)); _rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype)); - - _rtw_memset((u8 *)&psta->dot11txpn, 0, sizeof(union pn48)); - psta->dot11txpn.val = psta->dot11txpn.val + 1; -#ifdef CONFIG_IEEE80211W - _rtw_memset((u8 *)&psta->dot11wtxpn, 0, sizeof(union pn48)); -#endif /* CONFIG_IEEE80211W */ - _rtw_memset((u8 *)&psta->dot11rxpn, 0, sizeof(union pn48)); } /* Commented by Albert 2012/07/21 */ @@ -1846,7 +1906,7 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl } - /* for A-MPDU Rx reordering buffer control for bmc_sta & sta_info */ + /* for A-MPDU Rx reordering buffer control for sta_info */ /* if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff */ /* todo: check if AP can send A-MPDU packets */ for (i = 0; i < 16 ; i++) { @@ -1854,33 +1914,19 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl preorder_ctrl = &psta->recvreorder_ctrl[i]; preorder_ctrl->enable = _FALSE; preorder_ctrl->indicate_seq = 0xffff; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq); -#endif + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%u\n" + , FUNC_ADPT_ARG(padapter), i, preorder_ctrl->indicate_seq); + #endif preorder_ctrl->wend_b = 0xffff; preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */ preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; } + } - - bmc_sta = rtw_get_bcmc_stainfo(padapter); - if (bmc_sta) { - for (i = 0; i < 16 ; i++) { - /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */ - preorder_ctrl = &bmc_sta->recvreorder_ctrl[i]; - preorder_ctrl->enable = _FALSE; - preorder_ctrl->indicate_seq = 0xffff; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq); +#ifdef CONFIG_RTW_80211K + _rtw_memcpy(&psta->rm_en_cap, pnetwork->network.PhyInfo.rm_en_cap, 5); #endif - preorder_ctrl->wend_b = 0xffff; - preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */ - preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; - } - } - } return psta; @@ -2023,9 +2069,9 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) /* s1. find ptarget_wlan */ if (check_fwstate(pmlmepriv, _FW_LINKED)) { if (the_same_macaddr == _TRUE) - ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); + ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); else { - pcur_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); + pcur_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); if (pcur_wlan) pcur_wlan->fixed = _FALSE; @@ -2036,7 +2082,7 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */ } - ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress); + ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress); if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { if (ptarget_wlan) ptarget_wlan->fixed = _TRUE; @@ -2155,21 +2201,21 @@ void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool conn return; } - if (sta->mac_id >= macid_ctl->num) { + if (sta->cmn.mac_id >= macid_ctl->num) { RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n" - , FUNC_ADPT_ARG(adapter), sta->mac_id); + , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id); rtw_warn_on(1); return; } - if (!rtw_macid_is_used(macid_ctl, sta->mac_id)) { + if (!rtw_macid_is_used(macid_ctl, sta->cmn.mac_id)) { RTW_PRINT(FUNC_ADPT_FMT" macid:%u not is used, set connected to 0\n" - , FUNC_ADPT_ARG(adapter), sta->mac_id); + , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id); connected = 0; rtw_warn_on(1); } - if (connected && !rtw_macid_is_bmc(macid_ctl, sta->mac_id)) { + if (connected && !rtw_macid_is_bmc(macid_ctl, sta->cmn.mac_id)) { miracast_enabled = STA_OP_WFD_MODE(sta) != 0 && is_miracast_enabled(adapter); miracast_sink = miracast_enabled && (STA_OP_WFD_MODE(sta) & MIRACAST_SINK); @@ -2178,39 +2224,41 @@ void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool conn role = H2C_MSR_ROLE_TDLS; else #endif - if (MLME_IS_STA(adapter)) { - if (MLME_IS_GC(adapter)) - role = H2C_MSR_ROLE_GO; - else - role = H2C_MSR_ROLE_AP; - } else if (MLME_IS_AP(adapter)) { - if (MLME_IS_GO(adapter)) - role = H2C_MSR_ROLE_GC; - else - role = H2C_MSR_ROLE_STA; - } else if (MLME_IS_ADHOC(adapter) || MLME_IS_ADHOC_MASTER(adapter)) - role = H2C_MSR_ROLE_ADHOC; + if (MLME_IS_STA(adapter)) { + if (MLME_IS_GC(adapter)) + role = H2C_MSR_ROLE_GO; + else + role = H2C_MSR_ROLE_AP; + } else if (MLME_IS_AP(adapter)) { + if (MLME_IS_GO(adapter)) + role = H2C_MSR_ROLE_GC; + else + role = H2C_MSR_ROLE_STA; + } else if (MLME_IS_ADHOC(adapter) || MLME_IS_ADHOC_MASTER(adapter)) + role = H2C_MSR_ROLE_ADHOC; + else if (MLME_IS_MESH(adapter)) + role = H2C_MSR_ROLE_MESH; #ifdef CONFIG_WFD if (role == H2C_MSR_ROLE_GC - || role == H2C_MSR_ROLE_GO - || role == H2C_MSR_ROLE_TDLS - ) { + || role == H2C_MSR_ROLE_GO + || role == H2C_MSR_ROLE_TDLS + ) { if (adapter->wfd_info.rtsp_ctrlport - || adapter->wfd_info.tdls_rtsp_ctrlport - || adapter->wfd_info.peer_rtsp_ctrlport) + || adapter->wfd_info.tdls_rtsp_ctrlport + || adapter->wfd_info.peer_rtsp_ctrlport) rtw_wfd_st_switch(sta, 1); } #endif } rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter - , connected - , miracast_enabled - , miracast_sink - , role - , sta->mac_id - ); + , connected + , miracast_enabled + , miracast_sink + , role + , sta->cmn.mac_id + ); } u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected) @@ -2278,7 +2326,7 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) #endif #if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) { psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr); if (psta) { u8 *passoc_req = NULL; @@ -2286,35 +2334,39 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) rtw_sta_media_status_rpt(adapter, psta, 1); -#ifndef CONFIG_AUTO_AP_MODE +#ifdef CONFIG_MCC_MODE + rtw_hal_mcc_update_macid_bitmap(adapter, psta->cmn.mac_id, _TRUE); +#endif /* CONFIG_MCC_MODE */ +#ifndef CONFIG_AUTO_AP_MODE ap_sta_info_defer_update(adapter, psta); - /* report to upper layer */ - RTW_INFO("indicate_sta_assoc_event to upper layer - hostapd\n"); -#ifdef CONFIG_IOCTL_CFG80211 - _enter_critical_bh(&psta->lock, &irqL); - if (psta->passoc_req && psta->assoc_req_len > 0) { - passoc_req = rtw_zmalloc(psta->assoc_req_len); - if (passoc_req) { - assoc_req_len = psta->assoc_req_len; - _rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len); - - rtw_mfree(psta->passoc_req , psta->assoc_req_len); - psta->passoc_req = NULL; - psta->assoc_req_len = 0; + if (!MLME_IS_MESH(adapter)) { + /* report to upper layer */ + RTW_INFO("indicate_sta_assoc_event to upper layer - hostapd\n"); + #ifdef CONFIG_IOCTL_CFG80211 + _enter_critical_bh(&psta->lock, &irqL); + if (psta->passoc_req && psta->assoc_req_len > 0) { + passoc_req = rtw_zmalloc(psta->assoc_req_len); + if (passoc_req) { + assoc_req_len = psta->assoc_req_len; + _rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len); + + rtw_mfree(psta->passoc_req , psta->assoc_req_len); + psta->passoc_req = NULL; + psta->assoc_req_len = 0; + } } - } - _exit_critical_bh(&psta->lock, &irqL); + _exit_critical_bh(&psta->lock, &irqL); - if (passoc_req && assoc_req_len > 0) { - rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len); - - rtw_mfree(passoc_req, assoc_req_len); + if (passoc_req && assoc_req_len > 0) { + rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len); + rtw_mfree(passoc_req, assoc_req_len); + } + #else /* !CONFIG_IOCTL_CFG80211 */ + rtw_indicate_sta_assoc_event(adapter, psta); + #endif /* !CONFIG_IOCTL_CFG80211 */ } -#else /* !CONFIG_IOCTL_CFG80211 */ - rtw_indicate_sta_assoc_event(adapter, psta); -#endif /* !CONFIG_IOCTL_CFG80211 */ #endif /* !CONFIG_AUTO_AP_MODE */ #ifdef CONFIG_BEAMFORMING @@ -2336,8 +2388,6 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) goto exit; } - rtw_hal_set_odm_var(adapter, HAL_ODM_STA_INFO, psta, _TRUE); - rtw_sta_media_status_rpt(adapter, psta, 1); if (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) @@ -2352,7 +2402,7 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) { if (adapter->stapriv.asoc_sta_count == 2) { _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); + ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); pmlmepriv->cur_network_scanned = ptarget_wlan; if (ptarget_wlan) ptarget_wlan->fixed = _TRUE; @@ -2407,7 +2457,46 @@ void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf) #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_RTW_80211R -void rtw_update_ft_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork) +void rtw_ft_info_init(struct ft_roam_info *pft) +{ + _rtw_memset(pft, 0, sizeof(struct ft_roam_info)); + pft->ft_flags = 0 + | RTW_FT_EN + | RTW_FT_OTD_EN +#ifdef CONFIG_RTW_BTM_ROAM + | RTW_FT_BTM_ROAM +#endif + ; + pft->ft_updated_bcn = _FALSE; +} + +u8 rtw_ft_chk_roaming_candidate( + _adapter *padapter, struct wlan_network *competitor) +{ + u8 *pmdie; + u32 mdie_len = 0; + struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); + + if (!(pmdie = rtw_get_ie(&competitor->network.IEs[12], + _MDIE_, &mdie_len, competitor->network.IELength-12))) + return _FALSE; + + if (!_rtw_memcmp(&pft_roam->mdid, (pmdie+2), 2)) + return _FALSE; + + /*The candidate don't support over-the-DS*/ + if (rtw_ft_valid_otd_candidate(padapter, pmdie)) { + RTW_INFO("FT: ignore the candidate(" + MAC_FMT ") for over-the-DS\n", + MAC_ARG(competitor->network.MacAddress)); + rtw_ft_clr_flags(padapter, RTW_FT_PEER_OTD_EN); + return _FALSE; + } + + return _TRUE; +} + +void rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork) { struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta = NULL; @@ -2424,37 +2513,31 @@ void rtw_update_ft_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork) psta->ieee8021x_blocked = _TRUE; psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; - psta->dot11txpn.val = psta->dot11txpn.val + 1; _rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype)); _rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype)); _rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype)); - _rtw_memset((u8 *)&psta->dot11txpn, 0, sizeof(union pn48)); -#ifdef CONFIG_IEEE80211W - _rtw_memset((u8 *)&psta->dot11wtxpn, 0, sizeof(union pn48)); -#endif - _rtw_memset((u8 *)&psta->dot11rxpn, 0, sizeof(union pn48)); } } void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf) { - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct stassoc_event *pstassoc = (struct stassoc_event *)pbuf; - ft_priv *pftpriv = &pmlmepriv->ftpriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct stassoc_event *pstassoc = (struct stassoc_event *)pbuf; + struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network); struct cfg80211_ft_event_params ft_evt_parms; _irqL irqL; _rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms)); - rtw_update_ft_stainfo(padapter, pnetwork); - ft_evt_parms.ies_len = pftpriv->ft_event.ies_len; + rtw_ft_update_stainfo(padapter, pnetwork); + ft_evt_parms.ies_len = pft_roam->ft_event.ies_len; ft_evt_parms.ies = rtw_zmalloc(ft_evt_parms.ies_len); if (ft_evt_parms.ies) - _rtw_memcpy((void *)ft_evt_parms.ies, pftpriv->ft_event.ies, ft_evt_parms.ies_len); + _rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len); else goto err_2; @@ -2464,17 +2547,14 @@ void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf) else goto err_1; - ft_evt_parms.ric_ies = pftpriv->ft_event.ric_ies; - ft_evt_parms.ric_ies_len = pftpriv->ft_event.ric_ies_len; - - _enter_critical_bh(&pmlmepriv->lock, &irqL); - rtw_set_ft_status(padapter, RTW_FT_AUTHENTICATED_STA); - _exit_critical_bh(&pmlmepriv->lock, &irqL); + ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies; + ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len; + rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL); rtw_cfg80211_ft_event(padapter, &ft_evt_parms); RTW_INFO("%s: to "MAC_FMT"\n", __func__, MAC_ARG(ft_evt_parms.target_ap)); - rtw_mfree((u8 *)pftpriv->ft_event.target_ap, ETH_ALEN); + rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN); err_1: rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len); err_2: @@ -2482,23 +2562,99 @@ void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf) } #endif +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) +void rtw_roam_nb_info_init(_adapter *padapter) +{ + struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); + + _rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt)); + _rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list)); + _rtw_memset(&pnb->roam_target_addr, 0, ETH_ALEN); + pnb->nb_rpt_valid = _FALSE; + pnb->nb_rpt_ch_list_num = 0; + pnb->preference_en = _FALSE; + pnb->nb_rpt_is_same = _TRUE; + pnb->last_nb_rpt_entries = 0; +#ifdef CONFIG_RTW_WNM + rtw_init_timer(&pnb->roam_scan_timer, + padapter, rtw_wnm_roam_scan_hdl, + padapter); +#endif +} + +u8 rtw_roam_nb_scan_list_set( + _adapter *padapter, struct sitesurvey_parm *pparm) +{ + u8 ret = _FALSE; + u32 i; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct roam_nb_info *pnb = &(pmlmepriv->nb_info); + + if (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) + return ret; + + if (!pmlmepriv->need_to_roam) + return ret; + + if ((!pmlmepriv->nb_info.nb_rpt_valid) || (!pnb->nb_rpt_ch_list_num)) + return ret; + + if (!pparm) + return ret; + + rtw_init_sitesurvey_parm(padapter, pparm); + if (rtw_roam_busy_scan(padapter, pnb)) { + pparm->ch_num = 1; + pparm->ch[pmlmepriv->ch_cnt].hw_value = + pnb->nb_rpt_ch_list[pmlmepriv->ch_cnt].hw_value; + pmlmepriv->ch_cnt++; + ret = _TRUE; + if (pmlmepriv->ch_cnt == pnb->nb_rpt_ch_list_num) { + pmlmepriv->nb_info.nb_rpt_valid = _FALSE; + pmlmepriv->ch_cnt = 0; + } + goto set_bssid_list; + } + + pparm->ch_num = (pnb->nb_rpt_ch_list_num > RTW_CHANNEL_SCAN_AMOUNT)? + (RTW_CHANNEL_SCAN_AMOUNT):(pnb->nb_rpt_ch_list_num); + for (i=0; ich_num; i++) { + pparm->ch[i].hw_value = pnb->nb_rpt_ch_list[i].hw_value; + pparm->ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN; + } + + pmlmepriv->nb_info.nb_rpt_valid = _FALSE; + pmlmepriv->ch_cnt = 0; + ret = _TRUE; + +set_bssid_list: + rtw_set_802_11_bssid_list_scan(padapter, pparm); + return ret; +} +#endif + void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id) { struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; - RTW_INFO("%s "ADPT_FMT" - mac_id=%d\n", __func__, ADPT_ARG(adapter), mac_id); - if (mac_id >= 0 && mac_id < macid_ctl->num) { - rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id); - /* - * For safety, prevent from keeping macid sleep. - * If we can sure all power mode enter/leave are paired, - * this check can be removed. - * Lucas@20131113 - */ - /* wakeup macid after disconnect. */ - /*if (MLME_IS_STA(adapter))*/ - rtw_hal_macid_wakeup(adapter, mac_id); + u8 id_is_shared = mac_id == RTW_DEFAULT_MGMT_MACID; /* TODO: real shared macid judgment */ + + RTW_INFO(FUNC_ADPT_FMT" - mac_id=%d%s\n", FUNC_ADPT_ARG(adapter) + , mac_id, id_is_shared ? " shared" : ""); + + if (!id_is_shared) { + rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id); + /* + * For safety, prevent from keeping macid sleep. + * If we can sure all power mode enter/leave are paired, + * this check can be removed. + * Lucas@20131113 + */ + /* wakeup macid after disconnect. */ + /*if (MLME_IS_STA(adapter))*/ + rtw_hal_macid_wakeup(adapter, mac_id); + } } else { RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n" , FUNC_ADPT_ARG(adapter), mac_id); @@ -2514,7 +2670,7 @@ void rtw_sta_mstatus_report(_adapter *adapter) if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); if (psta) - rtw_sta_mstatus_disc_rpt(adapter, psta->mac_id); + rtw_sta_mstatus_disc_rpt(adapter, psta->cmn.mac_id); else { RTW_INFO("%s "ADPT_FMT" - mac_addr: "MAC_FMT" psta == NULL\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress)); rtw_warn_on(1); @@ -2541,6 +2697,10 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) RTW_INFO("%s(mac_id=%d)=" MAC_FMT "\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr)); rtw_sta_mstatus_disc_rpt(adapter, pstadel->mac_id); +#ifdef CONFIG_MCC_MODE + rtw_hal_mcc_update_macid_bitmap(adapter, pstadel->mac_id, _FALSE); +#endif /* CONFIG_MCC_MODE */ + psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr); if (psta == NULL) { @@ -2551,8 +2711,10 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) if (psta) rtw_wfd_st_switch(psta, 0); - /* if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) */ - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + if (MLME_IS_MESH(adapter)) + return; + + if (MLME_IS_AP(adapter)) { #ifdef CONFIG_IOCTL_CFG80211 #ifdef COMPAT_KERNEL_RELEASE @@ -2575,10 +2737,10 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) #ifdef CONFIG_LAYER2_ROAMING #ifdef CONFIG_RTW_80211R - if (reason == WLAN_REASON_EXPIRATION_CHK && rtw_chk_roam_flags(adapter, RTW_ROAM_ON_EXPIRED)) - pmlmepriv->ftpriv.ft_roam_on_expired = _TRUE; + if (rtw_ft_roam_expired(adapter, reason)) + pmlmepriv->ft_roam.ft_roam_on_expired = _TRUE; else - pmlmepriv->ftpriv.ft_roam_on_expired = _FALSE; + pmlmepriv->ft_roam.ft_roam_on_expired = _FALSE; #endif if (adapter->registrypriv.wifi_spec == 1) roam = _FALSE; @@ -2609,7 +2771,7 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); /* remove the network entry in scanned_queue */ - pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); + pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); if ((pwlan) && (!check_fwstate(pmlmepriv, WIFI_UNDER_WPS))) { pwlan->fixed = _FALSE; rtw_free_network_nolock(adapter, pwlan); @@ -2636,8 +2798,8 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) /* rtw_indicate_disconnect(adapter); */ /* removed@20091105 */ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); /* free old ibss network */ - /* pwlan = rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); */ - pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); + /* pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); */ + pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); if (pwlan) { pwlan->fixed = _FALSE; rtw_free_network_nolock(adapter, pwlan); @@ -2748,8 +2910,8 @@ void rtw_join_timeout_handler(void *ctx) #endif /* CONFIG_INTEL_WIDI */ RTW_INFO("%s We've try roaming but fail\n", __FUNCTION__); #ifdef CONFIG_RTW_80211R - rtw_clr_ft_flags(adapter, RTW_FT_SUPPORTED|RTW_FT_OVER_DS_SUPPORTED); - rtw_reset_ft_status(adapter); + rtw_ft_clr_flags(adapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN); + rtw_ft_reset_status(adapter); #endif rtw_indicate_disconnect(adapter, 0, _FALSE); break; @@ -2810,6 +2972,7 @@ void rtw_scan_timeout_handler(void *ctx) void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); struct mlme_priv *mlme = &adapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -2820,15 +2983,29 @@ void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason) rtw_mi_get_ch_setting_union(adapter, &u_ch, NULL, NULL); if (hal_chk_bw_cap(adapter, BW_CAP_40M) - && is_client_associated_to_ap(adapter) == _TRUE - && u_ch >= 1 && u_ch <= 14 - && adapter->registrypriv.wifi_spec - /* TODO: AP Connected is 40MHz capability? */ - ) { + && is_client_associated_to_ap(adapter) == _TRUE + && u_ch >= 1 && u_ch <= 14 + && adapter->registrypriv.wifi_spec + /* TODO: AP Connected is 40MHz capability? */ + ) { interval_ms = rtw_min(interval_ms, 60 * 1000); *reason |= RTW_AUTO_SCAN_REASON_2040_BSS; } +#ifdef CONFIG_RTW_MESH + #if CONFIG_RTW_MESH_OFFCH_CAND + if (adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms + && rtw_mesh_offch_candidate_accepted(adapter) + #ifdef CONFIG_DFS_MASTER + && (!rfctl->radar_detect_ch || (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl))) + #endif + ) { + interval_ms = rtw_min(interval_ms, adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms); + *reason |= RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND; + } + #endif +#endif /* CONFIG_RTW_MESH */ + exit: if (interval_ms == 0xffffffff) interval_ms = 0; @@ -2839,25 +3016,10 @@ void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason) void rtw_drv_scan_by_self(_adapter *padapter, u8 reason) { + struct sitesurvey_parm parm; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct rtw_ieee80211_channel ch_for_2040_bss[14] = { - {1, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {2, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {3, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {4, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {5, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {6, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {7, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {8, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {9, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {10, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {11, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {12, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {13, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {14, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - }; - struct rtw_ieee80211_channel *ch_sel = NULL; - int ch_num = 0; + int i; + if (rtw_is_scan_deny(padapter)) goto exit; @@ -2896,11 +3058,23 @@ void rtw_drv_scan_by_self(_adapter *padapter, u8 reason) /* only for 20/40 BSS */ if (reason == RTW_AUTO_SCAN_REASON_2040_BSS) { - ch_sel = ch_for_2040_bss; - ch_num = 14; + rtw_init_sitesurvey_parm(padapter, &parm); + for (i=0;i<14;i++) { + parm.ch[i].hw_value = i + 1; + parm.ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN; + } + parm.ch_num = 14; + rtw_set_802_11_bssid_list_scan(padapter, &parm); + goto exit; } - rtw_set_802_11_bssid_list_scan(padapter, NULL, 0, ch_sel, ch_num); +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) + if ((reason == RTW_AUTO_SCAN_REASON_ROAM) + && (rtw_roam_nb_scan_list_set(padapter, &parm))) + goto exit; +#endif + + rtw_set_802_11_bssid_list_scan(padapter, NULL); exit: return; } @@ -2972,12 +3146,18 @@ void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter) /* auto site survey */ rtw_auto_scan_handler(adapter); -#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK #ifdef CONFIG_AP_MODE - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (MLME_IS_AP(adapter)|| MLME_IS_MESH(adapter)) { + #ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK expire_timeout_chk(adapter); -#endif -#endif /* !CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ + #endif /* !CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ + + #ifdef CONFIG_BMC_TX_RATE_SELECT + rtw_update_bmc_sta_tx_rate(adapter); + #endif /*CONFIG_BMC_TX_RATE_SELECT*/ + } +#endif /*CONFIG_AP_MODE*/ + #ifdef CONFIG_BR_EXT @@ -3010,6 +3190,61 @@ void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter) } +/*TP_avg(t) = (1/10) * TP_avg(t-1) + (9/10) * TP(t) MBps*/ +static void collect_sta_traffic_statistics(_adapter *adapter) +{ + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + struct sta_info *sta; + u16 curr_tx_mbytes = 0, curr_rx_mbytes = 0; + int i; + + for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { + sta = macid_ctl->sta[i]; + if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) { + if (sta->sta_stats.last_tx_bytes > sta->sta_stats.tx_bytes) + sta->sta_stats.last_tx_bytes = sta->sta_stats.tx_bytes; + if (sta->sta_stats.last_rx_bytes > sta->sta_stats.rx_bytes) + sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes; + if (sta->sta_stats.last_rx_bc_bytes > sta->sta_stats.rx_bc_bytes) + sta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes; + if (sta->sta_stats.last_rx_mc_bytes > sta->sta_stats.rx_mc_bytes) + sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes; + + curr_tx_mbytes = ((sta->sta_stats.tx_bytes - sta->sta_stats.last_tx_bytes) >> 20) / 2; /*MBps*/ + curr_rx_mbytes = ((sta->sta_stats.rx_bytes - sta->sta_stats.last_rx_bytes) >> 20) / 2; /*MBps*/ + sta->sta_stats.tx_tp_mbytes = curr_tx_mbytes; + sta->sta_stats.rx_tp_mbytes = curr_rx_mbytes; + + sta->cmn.tx_moving_average_tp = + (sta->cmn.tx_moving_average_tp / 10) + (curr_tx_mbytes * 9 / 10); + + sta->cmn.rx_moving_average_tp = + (sta->cmn.rx_moving_average_tp / 10) + (curr_rx_mbytes * 9 /10); + + if (adapter->bsta_tp_dump) + dump_sta_traffic(RTW_DBGDUMP, adapter, sta); + + sta->sta_stats.last_tx_bytes = sta->sta_stats.tx_bytes; + sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes; + sta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes; + sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes; + } + } +} + +void rtw_sta_traffic_info(void *sel, _adapter *adapter) +{ + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + struct sta_info *sta; + int i; + + for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { + sta = macid_ctl->sta[i]; + if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) + dump_sta_traffic(sel, adapter, sta); + } +} + /*#define DBG_TRAFFIC_STATISTIC*/ static void collect_traffic_statistics(_adapter *padapter) { @@ -3049,6 +3284,13 @@ static void collect_traffic_statistics(_adapter *padapter) RTW_INFO("cur_tx_tp:%d\n", pdvobjpriv->traffic_stat.cur_tx_tp); RTW_INFO("cur_rx_tp:%d\n", pdvobjpriv->traffic_stat.cur_rx_tp); #endif + +#ifdef CONFIG_RTW_NAPI +#ifdef CONFIG_RTW_NAPI_DYNAMIC + dynamic_napi_th_chk (padapter); +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ +#endif + } void rtw_dynamic_check_timer_handlder(void *ctx) @@ -3073,7 +3315,7 @@ void rtw_dynamic_check_timer_handlder(void *ctx) goto exit; collect_traffic_statistics(adapter); - + collect_sta_traffic_statistics(adapter); rtw_mi_dynamic_check_timer_handlder(adapter); if (!is_drv_in_lps(adapter)) @@ -3126,12 +3368,15 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme { int updated = _FALSE; _adapter *adapter = container_of(mlme, _adapter, mlmepriv); -#ifdef CONFIG_RTW_80211R - ft_priv *pftpriv = &mlme->ftpriv; - u32 mdie_len = 0; - u8 *ptmp = NULL; -#endif + if (rtw_chset_search_ch(adapter_to_chset(adapter), competitor->network.Configuration.DSConfig) < 0) + goto exit; + +#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT)) + if (rtw_rson_isupdate_roamcan(mlme, candidate, competitor)) + goto update; + goto exit; +#endif if (is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE) goto exit; @@ -3145,23 +3390,9 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme #endif #ifdef CONFIG_RTW_80211R - if (rtw_chk_ft_flags(adapter, RTW_FT_SUPPORTED)) { - ptmp = rtw_get_ie(&competitor->network.IEs[12], _MDIE_, &mdie_len, competitor->network.IELength-12); - if (ptmp) { - if (!_rtw_memcmp(&pftpriv->mdid, ptmp+2, 2)) - goto exit; - - /*The candidate don't support over-the-DS*/ - if (rtw_chk_ft_flags(adapter, RTW_FT_STA_OVER_DS_SUPPORTED)) { - if ((rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && !(*(ptmp+4) & 0x01)) || - (!rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && (*(ptmp+4) & 0x01))) { - RTW_INFO("FT: ignore the candidate(" MAC_FMT ") for over-the-DS\n", MAC_ARG(competitor->network.MacAddress)); - rtw_clr_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED); - goto exit; - } - } - } else - goto exit; + if (rtw_ft_chk_flags(adapter, RTW_FT_PEER_EN)) { + if (rtw_ft_chk_roaming_candidate(adapter, competitor) == _FALSE) + goto exit; } #endif @@ -3182,9 +3413,16 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme goto exit; } #if 1 - if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms) + if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms) goto exit; +#if defined(CONFIG_RTW_80211R) && defined(CONFIG_RTW_WNM) + if (rtw_wnm_btm_diff_bss(adapter) && + rtw_wnm_btm_roam_candidate(adapter, competitor)) { + goto update; + } +#endif + if (competitor->network.Rssi - mlme->cur_network_scanned->network.Rssi < mlme->roam_rssi_diff_th) goto exit; @@ -3247,14 +3485,37 @@ int rtw_select_roaming_candidate(struct mlme_priv *mlme) } if (candidate == NULL) { + /* if parent note lost the path to root and there is no other cadidate, report disconnection */ +#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT)) + struct rtw_rson_struct rson_curr; + u8 rson_score; + + rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr); + rson_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi); + if (check_fwstate(mlme, _FW_LINKED) + && ((rson_score == RTW_RSON_SCORE_NOTCNNT) + || (rson_score == RTW_RSON_SCORE_NOTSUP))) + receive_disconnect(adapter, mlme->cur_network_scanned->network.MacAddress + , WLAN_REASON_EXPIRATION_CHK, _FALSE); +#endif RTW_INFO("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__); ret = _FAIL; goto exit; } else { +#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT)) + struct rtw_rson_struct rson_curr; + u8 rson_score; + + rtw_get_rson_struct(&(candidate->network), &rson_curr); + rson_score = rtw_cal_rson_score(&rson_curr, candidate->network.Rssi); + RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u) rson_score:%d\n", __FUNCTION__, + candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress), + candidate->network.Configuration.DSConfig, rson_score); +#else RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__, candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress), candidate->network.Configuration.DSConfig); - +#endif mlme->roam_network = candidate; if (_rtw_memcmp(candidate->network.MacAddress, mlme->roam_tgt_addr, ETH_ALEN) == _TRUE) @@ -3280,6 +3541,27 @@ static int rtw_check_join_candidate(struct mlme_priv *mlme int updated = _FALSE; _adapter *adapter = container_of(mlme, _adapter, mlmepriv); + if (rtw_chset_search_ch(adapter_to_chset(adapter), competitor->network.Configuration.DSConfig) < 0) + goto exit; + +#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT)) + s16 rson_score; + struct rtw_rson_struct rson_data; + + if (rtw_rson_choose(candidate, competitor)) { + *candidate = competitor; + rtw_get_rson_struct(&((*candidate)->network), &rson_data); + rson_score = rtw_cal_rson_score(&rson_data, (*candidate)->network.Rssi); + RTW_INFO("[assoc_ssid:%s] new candidate: %s("MAC_FMT", ch%u) rson_score:%d\n", + mlme->assoc_ssid.Ssid, + (*candidate)->network.Ssid.Ssid, + MAC_ARG((*candidate)->network.MacAddress), + (*candidate)->network.Configuration.DSConfig, + rson_score); + return _TRUE; + } + return _FALSE; +#endif /* check bssid, if needed */ if (mlme->assoc_by_bssid == _TRUE) { @@ -3300,7 +3582,7 @@ static int rtw_check_join_candidate(struct mlme_priv *mlme #ifdef CONFIG_LAYER2_ROAMING if (rtw_to_roam(adapter) > 0) { - if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms + if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms || is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE ) goto exit; @@ -3533,12 +3815,10 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke case _TKIP_: keylen = 16; _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); - psetkeyparm->grpkey = 1; break; case _AES_: keylen = 16; _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); - psetkeyparm->grpkey = 1; break; default: res = _FAIL; @@ -3575,12 +3855,111 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke } +#ifdef CONFIG_WMMPS_STA +/* + * rtw_uapsd_use_default_setting + * This function is used for setting default uapsd max sp length to uapsd_max_sp_len + * in qos_priv data structure from registry. In additional, it will also map default uapsd + * ac to each uapsd TID, delivery-enabled and trigger-enabled of corresponding TID. + * + * Arguments: + * @padapter: _adapter pointer. + * + * Auther: Arvin Liu + * Date: 2017/05/03 + */ +void rtw_uapsd_use_default_setting(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + + if (pregistrypriv->uapsd_ac_enable != 0) { + pqospriv->uapsd_max_sp_len = pregistrypriv->uapsd_max_sp_len; + + CLEAR_FLAGS(pqospriv->uapsd_tid); + CLEAR_FLAGS(pqospriv->uapsd_tid_delivery_enabled); + CLEAR_FLAGS(pqospriv->uapsd_tid_trigger_enabled); + + /* check the uapsd setting of AC_VO from registry then map these setting to each TID if necessary */ + if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VO)) { + SET_FLAG(pqospriv->uapsd_tid, WMM_TID7); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID7); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID7); + SET_FLAG(pqospriv->uapsd_tid, WMM_TID6); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID6); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID6); + } + + /* check the uapsd setting of AC_VI from registry then map these setting to each TID if necessary */ + if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VI)) { + SET_FLAG(pqospriv->uapsd_tid, WMM_TID5); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID5); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID5); + SET_FLAG(pqospriv->uapsd_tid, WMM_TID4); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID4); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID4); + } + + /* check the uapsd setting of AC_BK from registry then map these setting to each TID if necessary */ + if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BK)) { + SET_FLAG(pqospriv->uapsd_tid, WMM_TID2); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID2); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID2); + SET_FLAG(pqospriv->uapsd_tid, WMM_TID1); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID1); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID1); + } + + /* check the uapsd setting of AC_BE from registry then map these setting to each TID if necessary */ + if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BE)) { + SET_FLAG(pqospriv->uapsd_tid, WMM_TID3); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID3); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID3); + SET_FLAG(pqospriv->uapsd_tid, WMM_TID0); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID0); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID0); + } + + RTW_INFO("[WMMPS] UAPSD MAX SP Len = 0x%02x, UAPSD TID enabled = 0x%02x\n", + pqospriv->uapsd_max_sp_len, (u8)pqospriv->uapsd_tid); + } + +} + +/* + * rtw_is_wmmps_mode + * This function is used for checking whether Driver and an AP support uapsd function or not. + * If both of them support uapsd function, it will return true. Otherwise returns false. + * + * Arguments: + * @padapter: _adapter pointer. + * + * Auther: Arvin Liu + * Date: 2017/06/12 + */ +bool rtw_is_wmmps_mode(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + + if ((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT_MASK_TID_TC) != 0)) + return _TRUE; + + return _FALSE; +} +#endif /* CONFIG_WMMPS_STA */ /* adjust IEs for rtw_joinbss_cmd in WMM */ int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len) { +#ifdef CONFIG_WMMPS_STA + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; +#endif /* CONFIG_WMMPS_STA */ unsigned int ielength = 0; unsigned int i, j; + u8 qos_info = 0; i = 12; /* after the fixed IE */ while (i < in_len) { @@ -3603,7 +3982,42 @@ int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, u } out_ie[initial_out_len + 1] = 0x07; out_ie[initial_out_len + 6] = 0x00; - out_ie[initial_out_len + 8] = 0x00; + +#ifdef CONFIG_WMMPS_STA + switch(pqospriv->uapsd_max_sp_len) { + case NO_LIMIT: + /* do nothing */ + break; + case TWO_MSDU: + SET_FLAG(qos_info, BIT5); + break; + case FOUR_MSDU: + SET_FLAG(qos_info, BIT6); + break; + case SIX_MSDU: + SET_FLAG(qos_info, BIT5); + SET_FLAG(qos_info, BIT6); + break; + default: + /* do nothing */ + break; + }; + + /* check TID7 and TID6 for AC_VO to set corresponding Qos_info bit in WMM IE */ + if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID7)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID6))) + SET_FLAG(qos_info, WMM_IE_UAPSD_VO); + /* check TID5 and TID4 for AC_VI to set corresponding Qos_info bit in WMM IE */ + if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID5)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID4))) + SET_FLAG(qos_info, WMM_IE_UAPSD_VI); + /* check TID2 and TID1 for AC_BK to set corresponding Qos_info bit in WMM IE */ + if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID2)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID1))) + SET_FLAG(qos_info, WMM_IE_UAPSD_BK); + /* check TID3 and TID0 for AC_BE to set corresponding Qos_info bit in WMM IE */ + if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID3)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID0))) + SET_FLAG(qos_info, WMM_IE_UAPSD_BE); +#endif /* CONFIG_WMMPS_STA */ + + out_ie[initial_out_len + 8] = qos_info; break; } @@ -3653,84 +4067,74 @@ static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid) } -/* - * Check the RSN IE length - * If the RSN IE length <= 20, the RSN IE didn't include the PMKID information - * 0-11th element in the array are the fixed IE - * 12th element in the array is the IE - * 13th element in the array is the IE length - * */ - -static int rtw_append_pmkid(_adapter *adapter, int iEntry, u8 *ie, uint ie_len) +static int rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent) { struct security_priv *sec = &adapter->securitypriv; + struct rsne_info info; + u8 gm_cs[4]; + int i; - if (ie[13] > 20) { - int i; - u16 pmkid_cnt = RTW_GET_LE16(ie + 14 + 20); - if (pmkid_cnt == 1 && _rtw_memcmp(ie + 14 + 20 + 2, &sec->PMKIDList[iEntry].PMKID, 16)) { - RTW_INFO(FUNC_ADPT_FMT" has carried the same PMKID:"KEY_FMT"\n" - , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[iEntry].PMKID)); - goto exit; - } - - RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n" - , FUNC_ADPT_ARG(adapter), pmkid_cnt); - - for (i = 0; i < pmkid_cnt; i++) - RTW_INFO(" "KEY_FMT"\n", KEY_ARG(ie + 14 + 20 + 2 + i * 16)); + rtw_rsne_info_parse(ie, ie_len, &info); - ie_len -= 2 + pmkid_cnt * 16; - ie[13] = 20; + if (info.err) { + RTW_WARN(FUNC_ADPT_FMT" rtw_rsne_info_parse error\n" + , FUNC_ADPT_ARG(adapter)); + return 0; } - if (ie[13] <= 20) { - /* The RSN IE didn't include the PMK ID, append the PMK information */ - - RTW_INFO(FUNC_ADPT_FMT" append PMKID:"KEY_FMT"\n" - , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[iEntry].PMKID)); - - RTW_PUT_LE16(&ie[ie_len], 1); - ie_len += 2; - - _rtw_memcpy(&ie[ie_len], &sec->PMKIDList[iEntry].PMKID, 16); - ie_len += 16; + if (i_ent < 0 && info.pmkid_cnt == 0) + goto exit; - ie[13] += 18;/* PMKID length = 2+16 */ + if (i_ent >= 0 && info.pmkid_cnt == 1 && _rtw_memcmp(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16)) { + RTW_INFO(FUNC_ADPT_FMT" has carried the same PMKID:"KEY_FMT"\n" + , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[i_ent].PMKID)); + goto exit; } -exit: - return ie_len; -} - -static int rtw_remove_pmkid(_adapter *adapter, u8 *ie, uint ie_len) -{ - struct security_priv *sec = &adapter->securitypriv; - int i; - u16 pmkid_cnt = RTW_GET_LE16(ie + 14 + 20); - - if (ie[13] <= 20) - goto exit; + /* bakcup group mgmt cs */ + if (info.gmcs) + _rtw_memcpy(gm_cs, info.gmcs, 4); - RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n" - , FUNC_ADPT_ARG(adapter), pmkid_cnt); + if (info.pmkid_cnt) { + RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n" + , FUNC_ADPT_ARG(adapter), info.pmkid_cnt); + for (i = 0; i < info.pmkid_cnt; i++) + RTW_INFO(" "KEY_FMT"\n", KEY_ARG(info.pmkid_list + i * 16)); + } - for (i = 0; i < pmkid_cnt; i++) - RTW_INFO(" "KEY_FMT"\n", KEY_ARG(ie + 14 + 20 + 2 + i * 16)); + if (i_ent >= 0) { + RTW_INFO(FUNC_ADPT_FMT" append PMKID:"KEY_FMT"\n" + , FUNC_ADPT_ARG(adapter), KEY_ARG(sec->PMKIDList[i_ent].PMKID)); - ie_len -= 2 + pmkid_cnt * 16; - ie[13] = 20; + info.pmkid_cnt = 1; /* update new pmkid_cnt */ + _rtw_memcpy(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16); + } else + info.pmkid_cnt = 0; /* update new pmkid_cnt */ + + RTW_PUT_LE16(info.pmkid_list - 2, info.pmkid_cnt); + if (info.gmcs) + _rtw_memcpy(info.pmkid_list + 16 * info.pmkid_cnt, gm_cs, 4); + + ie_len = 1 + 1 + 2 + 4 + + 2 + 4 * info.pcs_cnt + + 2 + 4 * info.akm_cnt + + 2 + + 2 + 16 * info.pmkid_cnt + + (info.gmcs ? 4 : 0) + ; + + ie[1] = (u8)(ie_len - 2); exit: return ie_len; } -sint rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len) +sint rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie) { u8 authmode = 0x0, securitytype, match; u8 sec_ie[255], uncst_oui[4], bkup_ie[255]; u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01}; - uint ielength, cnt, remove_cnt; + uint ielength = 0, cnt, remove_cnt; int iEntry; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; @@ -3738,23 +4142,18 @@ sint rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len) uint ndisauthmode = psecuritypriv->ndisauthtype; uint ndissecuritytype = psecuritypriv->ndisencryptstatus; - - - /* copy fixed ie only */ - _rtw_memcpy(out_ie, in_ie, 12); - ielength = 12; if ((ndisauthmode == Ndis802_11AuthModeWPA) || (ndisauthmode == Ndis802_11AuthModeWPAPSK)) authmode = _WPA_IE_ID_; if ((ndisauthmode == Ndis802_11AuthModeWPA2) || (ndisauthmode == Ndis802_11AuthModeWPA2PSK)) authmode = _WPA2_IE_ID_; if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { - _rtw_memcpy(out_ie + ielength, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len); + _rtw_memcpy(out_ie, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len); + ielength = psecuritypriv->wps_ie_len; - ielength += psecuritypriv->wps_ie_len; } else if ((authmode == _WPA_IE_ID_) || (authmode == _WPA2_IE_ID_)) { /* copy RSN or SSN */ - _rtw_memcpy(&out_ie[ielength], &psecuritypriv->supplicant_ie[0], psecuritypriv->supplicant_ie[1] + 2); + _rtw_memcpy(out_ie, psecuritypriv->supplicant_ie, psecuritypriv->supplicant_ie[1] + 2); /* debug for CONFIG_IEEE80211W { int jj; @@ -3763,24 +4162,15 @@ sint rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len) printk(" %02x ", psecuritypriv->supplicant_ie[jj]); printk("\n"); }*/ - ielength += psecuritypriv->supplicant_ie[1] + 2; + ielength = psecuritypriv->supplicant_ie[1] + 2; rtw_report_sec_ie(adapter, authmode, psecuritypriv->supplicant_ie); - -#ifdef CONFIG_DRVEXT_MODULE - drvext_report_sec_ie(&adapter->drvextpriv, authmode, sec_ie); -#endif } - iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid); - if (iEntry < 0) { - if (authmode == _WPA2_IE_ID_) - ielength = rtw_remove_pmkid(adapter, out_ie, ielength); - } else { - if (authmode == _WPA2_IE_ID_) - ielength = rtw_append_pmkid(adapter, iEntry, out_ie, ielength); + if (authmode == WLAN_EID_RSN) { + iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid); + ielength = rtw_rsn_sync_pmkid(adapter, out_ie, ielength, iEntry); } - return ielength; } @@ -3981,15 +4371,23 @@ void rtw_ht_use_default_setting(_adapter *padapter) /* Beamforming setting */ CLEAR_FLAGS(phtpriv->beamform_cap); #ifdef CONFIG_BEAMFORMING - rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer); - rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee); - if (TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) { - SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); - RTW_INFO("[HT] HAL Support Beamformer\n"); - } - if (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) { - SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); - RTW_INFO("[HT] HAL Support Beamformee\n"); +#ifdef RTW_BEAMFORMING_VERSION_2 + /* only enable beamforming in STA client mode */ + if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter) + && !MLME_IS_ADHOC(padapter) + && !MLME_IS_MESH(padapter)) +#endif + { + rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer); + rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee); + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) { + SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + RTW_INFO("[HT] HAL Support Beamformer\n"); + } + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) { + SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + RTW_INFO("[HT] HAL Support Beamformee\n"); + } } #endif /* CONFIG_BEAMFORMING */ } @@ -4017,7 +4415,7 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui HT_CAP_AMPDU_DENSITY best_ampdu_density; unsigned char *p, *pframe; struct rtw_ieee80211_ht_cap ht_capie; - u8 cbw40_enable = 0, rf_type = 0, operation_bw = 0, rf_num = 0, rx_stbc_nss = 0, rx_nss = 0; + u8 cbw40_enable = 0, rf_type = 0, rf_num = 0, rx_stbc_nss = 0, rx_nss = 0; struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct ht_priv *phtpriv = &pmlmepriv->htpriv; @@ -4039,36 +4437,7 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui if (phtpriv->sgi_20m) ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_20; - /* Get HT BW */ - if (in_ie == NULL) { - /* TDLS: TODO 20/40 issue */ - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - operation_bw = padapter->mlmeextpriv.cur_bwmode; - if (operation_bw > CHANNEL_WIDTH_40) - operation_bw = CHANNEL_WIDTH_40; - } else - /* TDLS: TODO 40? */ - operation_bw = CHANNEL_WIDTH_40; - } else { - p = rtw_get_ie(in_ie, _HT_ADD_INFO_IE_, &ielen, in_len); - if (p && (ielen == sizeof(struct ieee80211_ht_addt_info))) { - struct HT_info_element *pht_info = (struct HT_info_element *)(p + 2); - if (pht_info->infos[0] & BIT(2)) { - switch (pht_info->infos[0] & 0x3) { - case 1: - case 3: - operation_bw = CHANNEL_WIDTH_40; - break; - default: - operation_bw = CHANNEL_WIDTH_20; - break; - } - } else - operation_bw = CHANNEL_WIDTH_20; - } - } - - /* to disable 40M Hz support while gd_bw_40MHz_en = 0 */ + /* check if 40MHz is allowed according to hal cap and registry */ if (hal_chk_bw_cap(padapter, BW_CAP_40M)) { if (channel > 14) { if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) @@ -4079,10 +4448,53 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui } } - if ((cbw40_enable == 1) && (operation_bw == CHANNEL_WIDTH_40)) { - ht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH; - if (phtpriv->sgi_40m) - ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_40; + if (cbw40_enable) { + u8 oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + if (in_ie == NULL) { + /* TDLS: TODO 20/40 issue */ + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + oper_bw = padapter->mlmeextpriv.cur_bwmode; + if (oper_bw > CHANNEL_WIDTH_40) + oper_bw = CHANNEL_WIDTH_40; + } else + /* TDLS: TODO 40? */ + oper_bw = CHANNEL_WIDTH_40; + } else { + p = rtw_get_ie(in_ie, WLAN_EID_HT_OPERATION, &ielen, in_len); + if (p && ielen == HT_OP_IE_LEN) { + if (GET_HT_OP_ELE_STA_CHL_WIDTH(p + 2)) { + switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(p + 2)) { + case SCA: + oper_bw = CHANNEL_WIDTH_40; + oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + case SCB: + oper_bw = CHANNEL_WIDTH_40; + oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + } + } + } + } + + /* adjust bw to fit in channel plan setting */ + if (oper_bw == CHANNEL_WIDTH_40 + && oper_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE /* check this because TDLS has no info to set offset */ + && !rtw_chset_is_chbw_valid(adapter_to_chset(padapter), channel, oper_bw, oper_offset) + ) { + oper_bw = CHANNEL_WIDTH_20; + oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + rtw_warn_on(!rtw_chset_is_chbw_valid(adapter_to_chset(padapter), channel, oper_bw, oper_offset)); + } + + if (oper_bw == CHANNEL_WIDTH_40) { + ht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH; + if (phtpriv->sgi_40m) + ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_40; + } + + cbw40_enable = oper_bw == CHANNEL_WIDTH_40 ? 1 : 0; } /* todo: disable SM power save mode */ @@ -4126,7 +4538,7 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui break; case 2: #ifdef CONFIG_DISABLE_MCS13TO15 - if (((cbw40_enable == 1) && (operation_bw == CHANNEL_WIDTH_40)) && (pregistrypriv->wifi_spec != 1)) + if (cbw40_enable && pregistrypriv->wifi_spec != 1) set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R_13TO15_OFF); else #endif @@ -4379,46 +4791,6 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel) /* Config current HT Protection mode. */ /* */ pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; - - - -#if 0 /* move to rtw_update_sta_info_client() */ - /* for A-MPDU Rx reordering buffer control for bmc_sta & sta_info */ - /* if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff */ - /* todo: check if AP can send A-MPDU packets */ - bmc_sta = rtw_get_bcmc_stainfo(padapter); - if (bmc_sta) { - for (i = 0; i < 16 ; i++) { - /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */ - preorder_ctrl = &bmc_sta->recvreorder_ctrl[i]; - preorder_ctrl->enable = _FALSE; - preorder_ctrl->indicate_seq = 0xffff; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq); -#endif - preorder_ctrl->wend_b = 0xffff; - preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */ - } - } - - psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress); - if (psta) { - for (i = 0; i < 16 ; i++) { - /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */ - preorder_ctrl = &psta->recvreorder_ctrl[i]; - preorder_ctrl->enable = _FALSE; - preorder_ctrl->indicate_seq = 0xffff; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq); -#endif - preorder_ctrl->wend_b = 0xffff; - preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */ - } - } -#endif - } #ifdef CONFIG_TDLS @@ -4521,6 +4893,9 @@ void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len) if (pvhtpriv->vht_option) SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(cap_content, 1); #endif /* CONFIG_80211AC_VHT */ +#ifdef CONFIG_RTW_WNM + rtw_wnm_set_ext_cap_btm(cap_content, 1); +#endif /* From 802.11 specification,if a STA does not support any of capabilities defined in the Extended Capabilities element, then the STA is not required to @@ -4590,8 +4965,8 @@ void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) else { RTW_INFO("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__, __LINE__); #ifdef CONFIG_RTW_80211R - rtw_clr_ft_flags(padapter, RTW_FT_SUPPORTED|RTW_FT_OVER_DS_SUPPORTED); - rtw_reset_ft_status(padapter); + rtw_ft_clr_flags(padapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN); + rtw_ft_reset_status(padapter); #endif rtw_indicate_disconnect(padapter, 0, _FALSE); break; @@ -4608,9 +4983,14 @@ bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset) struct registry_priv *regsty = adapter_to_regsty(adapter); u8 allowed_bw; - if (req_ch <= 14) + if (req_ch <= 14) { allowed_bw = REGSTY_BW_2G(regsty); - else + if (MLME_IS_MESH(adapter)) { + /* prevent secondary channel offset mismatch */ + if (req_ch >= 5 && req_ch <= 9) + allowed_bw = CHANNEL_WIDTH_20; + } + } else allowed_bw = REGSTY_BW_5G(regsty); allowed_bw = hal_largest_bw(adapter, allowed_bw); @@ -4630,8 +5010,9 @@ bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset) sint rtw_linked_check(_adapter *padapter) { - if ((check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) || - (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter) + || MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter) + ) { if (padapter->stapriv.asoc_sta_count > 2) return _TRUE; } else { @@ -4641,23 +5022,33 @@ sint rtw_linked_check(_adapter *padapter) } return _FALSE; } +/*#define DBG_ADAPTER_STATE_CHK*/ u8 rtw_is_adapter_up(_adapter *padapter) { if (padapter == NULL) return _FALSE; if (RTW_CANNOT_RUN(padapter)) { - RTW_INFO(FUNC_ADPT_FMT "-(bSurpriseRemoved == _TRUE) || ( bDriverStopped == _TRUE)\n", FUNC_ADPT_ARG(padapter)); + #ifdef DBG_ADAPTER_STATE_CHK + RTW_INFO(FUNC_ADPT_FMT " FALSE -bDriverStopped(%s) bSurpriseRemoved(%s)\n" + , FUNC_ADPT_ARG(padapter) + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False"); + #endif return _FALSE; } if (!rtw_is_hw_init_completed(padapter)) { - /*RTW_INFO(FUNC_ADPT_FMT "-(hw_init_completed == _FALSE)\n", FUNC_ADPT_ARG(padapter));*/ + #ifdef DBG_ADAPTER_STATE_CHK + RTW_INFO(FUNC_ADPT_FMT " FALSE -(hw_init_completed == _FALSE)\n", FUNC_ADPT_ARG(padapter)); + #endif return _FALSE; } if (padapter->bup == _FALSE) { - /*RTW_INFO(FUNC_ADPT_FMT "-(bup == _FALSE)\n", FUNC_ADPT_ARG(padapter));*/ + #ifdef DBG_ADAPTER_STATE_CHK + RTW_INFO(FUNC_ADPT_FMT " FALSE -(bup == _FALSE)\n", FUNC_ADPT_ARG(padapter)); + #endif return _FALSE; } diff --git a/core/rtw_mlme_ext.c b/core/rtw_mlme_ext.c index f7bc092..3bcb3fa 100644 --- a/core/rtw_mlme_ext.c +++ b/core/rtw_mlme_ext.c @@ -73,7 +73,7 @@ struct action_handler OnAction_tbl[] = { {RTW_WLAN_CATEGORY_DLS, "ACTION_DLS", &OnAction_dls}, {RTW_WLAN_CATEGORY_BACK, "ACTION_BACK", &OnAction_back}, {RTW_WLAN_CATEGORY_PUBLIC, "ACTION_PUBLIC", on_action_public}, - {RTW_WLAN_CATEGORY_RADIO_MEASUREMENT, "ACTION_RADIO_MEASUREMENT", &DoReserved}, + {RTW_WLAN_CATEGORY_RADIO_MEAS, "ACTION_RADIO_MEAS", &on_action_rm}, {RTW_WLAN_CATEGORY_FT, "ACTION_FT", &OnAction_ft}, {RTW_WLAN_CATEGORY_HT, "ACTION_HT", &OnAction_ht}, #ifdef CONFIG_IEEE80211W @@ -85,7 +85,10 @@ struct action_handler OnAction_tbl[] = { {RTW_WLAN_CATEGORY_WNM, "ACTION_WNM", &on_action_wnm}, #endif {RTW_WLAN_CATEGORY_UNPROTECTED_WNM, "ACTION_UNPROTECTED_WNM", &DoReserved}, - {RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &DoReserved}, +#ifdef CONFIG_RTW_MESH + {RTW_WLAN_CATEGORY_MESH, "ACTION_MESH", &on_action_mesh}, + {RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &on_action_self_protected}, +#endif {RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm}, {RTW_WLAN_CATEGORY_VHT, "ACTION_VHT", &OnAction_vht}, {RTW_WLAN_CATEGORY_P2P, "ACTION_P2P", &OnAction_p2p}, @@ -140,6 +143,89 @@ static RT_CHANNEL_PLAN legacy_channel_plan[] = { }; #endif +enum rtw_rd_2g { + RTW_RD_2G_NULL = 0, + RTW_RD_2G_WORLD = 1, /* Worldwird 13 */ + RTW_RD_2G_ETSI1 = 2, /* Europe */ + RTW_RD_2G_FCC1 = 3, /* US */ + RTW_RD_2G_MKK1 = 4, /* Japan */ + RTW_RD_2G_ETSI2 = 5, /* France */ + RTW_RD_2G_GLOBAL = 6, /* Global domain */ + RTW_RD_2G_MKK2 = 7, /* Japan */ + RTW_RD_2G_FCC2 = 8, /* US */ + RTW_RD_2G_IC1 = 9, /* Canada */ + RTW_RD_2G_WORLD1 = 10, /* Worldwide 11 */ + + RTW_RD_2G_MAX, +}; + +enum rtw_rd_5g { + RTW_RD_5G_NULL = 0, /* */ + RTW_RD_5G_ETSI1 = 1, /* Europe */ + RTW_RD_5G_ETSI2 = 2, /* Australia, New Zealand */ + RTW_RD_5G_ETSI3 = 3, /* Russia */ + RTW_RD_5G_FCC1 = 4, /* US */ + RTW_RD_5G_FCC2 = 5, /* FCC w/o DFS Channels */ + RTW_RD_5G_FCC3 = 6, /* Bolivia, Chile, El Salvador, Venezuela */ + RTW_RD_5G_FCC4 = 7, /* Venezuela */ + RTW_RD_5G_FCC5 = 8, /* China */ + RTW_RD_5G_FCC6 = 9, /* */ + RTW_RD_5G_FCC7 = 10, /* US(w/o Weather radar) */ + RTW_RD_5G_IC1 = 11, /* Canada(w/o Weather radar) */ + RTW_RD_5G_KCC1 = 12, /* Korea */ + RTW_RD_5G_MKK1 = 13, /* Japan */ + RTW_RD_5G_MKK2 = 14, /* Japan (W52, W53) */ + RTW_RD_5G_MKK3 = 15, /* Japan (W56) */ + RTW_RD_5G_NCC1 = 16, /* Taiwan, (w/o Weather radar) */ + RTW_RD_5G_NCC2 = 17, /* Taiwan, Band2, Band4 */ + RTW_RD_5G_NCC3 = 18, /* Taiwan w/o DFS, Band4 only */ + RTW_RD_5G_ETSI4 = 19, /* Europe w/o DFS, Band1 only */ + RTW_RD_5G_ETSI5 = 20, /* Australia, New Zealand(w/o Weather radar) */ + RTW_RD_5G_FCC8 = 21, /* Latin America */ + RTW_RD_5G_ETSI6 = 22, /* Israel, Bahrain, Egypt, India, China, Malaysia */ + RTW_RD_5G_ETSI7 = 23, /* China */ + RTW_RD_5G_ETSI8 = 24, /* Jordan */ + RTW_RD_5G_ETSI9 = 25, /* Lebanon */ + RTW_RD_5G_ETSI10 = 26, /* Qatar */ + RTW_RD_5G_ETSI11 = 27, /* Russia */ + RTW_RD_5G_NCC4 = 28, /* Taiwan, (w/o Weather radar) */ + RTW_RD_5G_ETSI12 = 29, /* Indonesia */ + RTW_RD_5G_FCC9 = 30, /* (w/o Weather radar) */ + RTW_RD_5G_ETSI13 = 31, /* (w/o Weather radar) */ + RTW_RD_5G_FCC10 = 32, /* Argentina(w/o Weather radar) */ + RTW_RD_5G_MKK4 = 33, /* Japan (W52) */ + RTW_RD_5G_ETSI14 = 34, /* Russia */ + RTW_RD_5G_FCC11 = 35, /* US(include CH144) */ + RTW_RD_5G_ETSI15 = 36, /* Malaysia */ + RTW_RD_5G_MKK5 = 37, /* Japan */ + RTW_RD_5G_ETSI16 = 38, /* Europe */ + RTW_RD_5G_ETSI17 = 39, /* Europe */ + RTW_RD_5G_FCC12 = 40, /* FCC */ + RTW_RD_5G_FCC13 = 41, /* FCC */ + RTW_RD_5G_FCC14 = 42, /* FCC w/o Weather radar(w/o 5600~5650MHz) */ + RTW_RD_5G_FCC15 = 43, /* FCC w/o Band3 */ + RTW_RD_5G_FCC16 = 44, /* FCC w/o Band3 */ + RTW_RD_5G_ETSI18 = 45, /* ETSI w/o DFS Band2&3 */ + RTW_RD_5G_ETSI19 = 46, /* Europe */ + RTW_RD_5G_FCC17 = 47, /* FCC w/o Weather radar(w/o 5600~5650MHz) */ + RTW_RD_5G_ETSI20 = 48, /* Europe */ + RTW_RD_5G_IC2 = 49, /* Canada(w/o Weather radar), include ch144 */ + RTW_RD_5G_ETSI21 = 50, /* Australia, New Zealand(w/o Weather radar) */ + RTW_RD_5G_FCC18 = 51, /* */ + RTW_RD_5G_WORLD = 52, /* Worldwide */ + RTW_RD_5G_CHILE1 = 53, /* Chile */ + RTW_RD_5G_ACMA1 = 54, /* Australia, New Zealand (w/o Weather radar) (w/o Ch120~Ch128) */ + RTW_RD_5G_WORLD1 = 55, /* 5G Worldwide Band1&2 */ + RTW_RD_5G_CHILE2 = 56, /* Chile (Band2,Band3) */ + + /* === Below are driver defined for legacy channel plan compatible, DON'T assign index ==== */ + RTW_RD_5G_OLD_FCC1, + RTW_RD_5G_OLD_NCC1, + RTW_RD_5G_OLD_KCC1, + + RTW_RD_5G_MAX, +}; + static struct ch_list_t RTW_ChannelPlan2G[] = { /* 0, RTW_RD_2G_NULL */ CH_LIST_ENT(0), /* 1, RTW_RD_2G_WORLD */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), @@ -151,6 +237,7 @@ static struct ch_list_t RTW_ChannelPlan2G[] = { /* 7, RTW_RD_2G_MKK2 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), /* 8, RTW_RD_2G_FCC2 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), /* 9, RTW_RD_2G_IC1 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 10, RTW_RD_2G_WORLD1 */ CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11), }; #ifdef CONFIG_IEEE80211_BAND_5GHZ @@ -208,6 +295,10 @@ static struct ch_list_t RTW_ChannelPlan5G[] = { /* 50, RTW_RD_5G_ETSI21 */ CH_LIST_ENT(13, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), /* 51, RTW_RD_5G_FCC18 */ CH_LIST_ENT(8, 100, 104, 108, 112, 116, 132, 136, 140), /* 52, RTW_RD_5G_WORLD */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165), + /* 53, RTW_RD_5G_CHILE1 */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165), + /* 54, RTW_RD_5G_ACMA1 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 55, RTW_RD_5G_WORLD1 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), + /* 56, RTW_RD_5G_CHILE2 */ CH_LIST_ENT(16, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144), /* === Below are driver defined for legacy channel plan compatible, NO static index assigned ==== */ /* RTW_RD_5G_OLD_FCC1 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165), @@ -216,7 +307,7 @@ static struct ch_list_t RTW_ChannelPlan5G[] = { }; #endif /* CONFIG_IEEE80211_BAND_5GHZ */ -static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[] = { +static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[RTW_CHPLAN_MAX] = { /* ===== 0x00 ~ 0x1F, legacy channel plan ===== */ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_KCC1, TXPWR_LMT_FCC), /* 0x00, RTW_CHPLAN_FCC */ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_FCC1, TXPWR_LMT_FCC), /* 0x01, RTW_CHPLAN_IC */ @@ -264,10 +355,10 @@ static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[] = { CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x29, RTW_CHPLAN_WORLD_FCC2 */ CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_NULL, TXPWR_LMT_FCC), /* 0x2A, RTW_CHPLAN_FCC2_NULL */ CHPLAN_ENT(RTW_RD_2G_IC1, RTW_RD_5G_IC2, TXPWR_LMT_IC), /* 0x2B, RTW_CHPLAN_IC1_IC2 */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2C, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2D, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2E, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2F, */ + CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x2C, RTW_CHPLAN_MKK2_NULL */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_CHILE1, TXPWR_LMT_CHILE), /* 0x2D, RTW_CHPLAN_WORLD_CHILE1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD1, RTW_RD_5G_WORLD1, TXPWR_LMT_WW), /* 0x2E, RTW_CHPLAN_WORLD1_WORLD1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_CHILE2, TXPWR_LMT_CHILE), /* 0x2F, RTW_CHPLAN_WORLD_CHILE2 */ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC3, TXPWR_LMT_FCC), /* 0x30, RTW_CHPLAN_WORLD_FCC3 */ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC4, TXPWR_LMT_FCC), /* 0x31, RTW_CHPLAN_WORLD_FCC4 */ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x32, RTW_CHPLAN_WORLD_FCC5 */ @@ -278,10 +369,10 @@ static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[] = { CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK2, TXPWR_LMT_MKK), /* 0x37, RTW_CHPLAN_MKK1_MKK2 */ CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK3, TXPWR_LMT_MKK), /* 0x38, RTW_CHPLAN_MKK1_MKK3 */ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC1, TXPWR_LMT_FCC), /* 0x39, RTW_CHPLAN_FCC1_NCC1 */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3A, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3B, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3C, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3D, */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x3A, RTW_CHPLAN_ETSI1_ETSI1 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ACMA1, TXPWR_LMT_ACMA), /* 0x3B, RTW_CHPLAN_ETSI1_ACMA1 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI6, TXPWR_LMT_ETSI), /* 0x3C, RTW_CHPLAN_ETSI1_ETSI6 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI12, TXPWR_LMT_ETSI), /* 0x3D, RTW_CHPLAN_ETSI1_ETSI12 */ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3E, */ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3F, */ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC), /* 0x40, RTW_CHPLAN_FCC1_NCC2 */ @@ -289,7 +380,7 @@ static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[] = { CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI4, TXPWR_LMT_ETSI), /* 0x42, RTW_CHPLAN_ETSI1_ETSI4 */ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x43, RTW_CHPLAN_FCC1_FCC2 */ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC3, TXPWR_LMT_FCC), /* 0x44, RTW_CHPLAN_FCC1_NCC3 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI5, TXPWR_LMT_ETSI), /* 0x45, RTW_CHPLAN_WORLD_ETSI5 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ACMA1, TXPWR_LMT_ACMA), /* 0x45, RTW_CHPLAN_WORLD_ACMA1 */ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC8, TXPWR_LMT_FCC), /* 0x46, RTW_CHPLAN_FCC1_FCC8 */ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI6, TXPWR_LMT_ETSI), /* 0x47, RTW_CHPLAN_WORLD_ETSI6 */ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI7, TXPWR_LMT_ETSI), /* 0x48, RTW_CHPLAN_WORLD_ETSI7 */ @@ -341,6 +432,7 @@ static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[] = { CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC11, TXPWR_LMT_FCC), /* 0x76, RTW_CHPLAN_FCC2_FCC11 */ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI21, TXPWR_LMT_ETSI), /* 0x77, RTW_CHPLAN_WORLD_ETSI21 */ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC18, TXPWR_LMT_FCC), /* 0x78, RTW_CHPLAN_FCC1_FCC18 */ + CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK1, TXPWR_LMT_MKK), /* 0x79, RTW_CHPLAN_MKK2_MKK1 */ }; static RT_CHANNEL_PLAN_MAP RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE = @@ -388,6 +480,7 @@ inline u8 rtw_rd_5g_band1_passive(u8 rtw_rd_5g) case RTW_RD_5G_ETSI18: case RTW_RD_5G_ETSI19: case RTW_RD_5G_WORLD: + case RTW_RD_5G_WORLD1: passive = 1; }; @@ -659,15 +752,17 @@ void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl) switch (regd) { /* - * To support older chips without IC and KCC regd: - * IC not found, use FCC instead - * KCC not found, use ETSI instead + * To support older chips without new predefined regd: + * - use FCC if IC or CHILE not found + * - use ETSI if KCC or ACMA not found */ case TXPWR_LMT_IC: case TXPWR_LMT_KCC: - if (regd == TXPWR_LMT_IC) + case TXPWR_LMT_ACMA: + case TXPWR_LMT_CHILE: + if (regd == TXPWR_LMT_IC || regd == TXPWR_LMT_CHILE) regd = TXPWR_LMT_FCC; - else if (regd == TXPWR_LMT_KCC) + else if (regd == TXPWR_LMT_KCC || regd == TXPWR_LMT_ACMA) regd = TXPWR_LMT_ETSI; ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd)); if (ent) @@ -696,12 +791,16 @@ void rtw_rfctl_init(_adapter *adapter) rfctl->max_chan_nums = init_channel_set(adapter, rfctl->ChannelPlan, rfctl->channel_set); init_channel_list(adapter, rfctl->channel_set, &rfctl->channel_list); + _rtw_mutex_init(&rfctl->offch_mutex); + #ifdef CONFIG_TXPWR_LIMIT _rtw_mutex_init(&rfctl->txpwr_lmt_mutex); _rtw_init_listhead(&rfctl->reg_exc_list); _rtw_init_listhead(&rfctl->txpwr_lmt_list); #endif + rfctl->ch_sel_same_band_prefer = 1; + #ifdef CONFIG_DFS_MASTER rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED; @@ -713,6 +812,8 @@ void rtw_rfctl_deinit(_adapter *adapter) { struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + _rtw_mutex_free(&rfctl->offch_mutex); + #ifdef CONFIG_TXPWR_LIMIT rtw_regd_exc_list_free(rfctl); rtw_txpwr_lmt_list_free(rfctl); @@ -862,7 +963,7 @@ bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) u32 rtw_chset_get_ch_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) { int ms = 0; - u32 current_time; + systime current_time; u32 hi = 0, lo = 0; int i; @@ -941,7 +1042,6 @@ inline void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms) { struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; u32 non_ocp_ms; u32 cac_ms; u8 in_rd_range = 0; /* if in current radar detection range*/ @@ -1013,10 +1113,42 @@ void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset) if (rfctl->cac_end_time == RTW_CAC_STOPPED) rfctl->cac_end_time++; } + +u32 rtw_force_stop_cac(_adapter *adapter, u32 timeout_ms) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + systime start; + u32 pass_ms; + + start = rtw_get_current_time(); + + rfctl->cac_force_stop = 1; + + while (rtw_get_passing_time_ms(start) <= timeout_ms + && IS_UNDER_CAC(rfctl) + ) { + if (RTW_CANNOT_RUN(adapter)) + break; + rtw_msleep_os(20); + } + + if (IS_UNDER_CAC(rfctl)) { + if (!RTW_CANNOT_RUN(adapter)) + RTW_INFO(FUNC_ADPT_FMT" waiting for cac stop timeout!\n", FUNC_ADPT_ARG(adapter)); + } + + rfctl->cac_force_stop = 0; + + pass_ms = rtw_get_passing_time_ms(start); + + return pass_ms; +} #endif /* CONFIG_DFS_MASTER */ /* choose channel with shortest waiting (non ocp + cac) time */ -bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset, u8 d_flags) +bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 sel_ch, u8 max_bw + , u8 *dec_ch, u8 *dec_bw, u8 *dec_offset + , u8 d_flags, u8 cur_ch, u8 same_band_prefer) { #ifndef DBG_CHOOSE_SHORTEST_WAITING_CH #define DBG_CHOOSE_SHORTEST_WAITING_CH 0 @@ -1035,7 +1167,7 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 } /* full search and narrow bw judegement first to avoid potetial judegement timing issue */ - for (bw = CHANNEL_WIDTH_20; bw <= req_bw; bw++) { + for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) { if (!hal_is_bw_support(adapter, bw)) continue; @@ -1045,6 +1177,8 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 u32 waiting_ms = 0; ch = rfctl->channel_set[i].ChannelNum; + if (sel_ch > 0 && ch != sel_ch) + continue; if ((d_flags & RTW_CHF_2G) && ch <= 14) continue; @@ -1090,8 +1224,13 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 , FUNC_ADPT_ARG(adapter), ch, bw, offset, waiting_ms, non_ocp_ms, cac_ms); if (ch_c == 0 + /* first: smaller wating time */ || min_waiting_ms > waiting_ms - || (min_waiting_ms == waiting_ms && bw > bw_c) /* wider bw first */ + /* then: wider bw */ + || (min_waiting_ms == waiting_ms && bw > bw_c) + /* then: same band if requested */ + || (same_band_prefer && min_waiting_ms == waiting_ms && bw == bw_c + && !rtw_is_same_band(cur_ch, ch_c) && rtw_is_same_band(cur_ch, ch)) ) { ch_c = ch; bw_c = bw; @@ -1102,8 +1241,9 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 } if (ch_c != 0) { - RTW_INFO(FUNC_ADPT_FMT": d_flags:0x%02x %u,%u,%u waiting_ms:%u\n" - , FUNC_ADPT_ARG(adapter), d_flags, ch_c, bw_c, offset_c, min_waiting_ms); + RTW_INFO(FUNC_ADPT_FMT": d_flags:0x%02x cur_ch:%u sb_prefer:%u %u,%u,%u waiting_ms:%u\n" + , FUNC_ADPT_ARG(adapter), d_flags, cur_ch, same_band_prefer + , ch_c, bw_c, offset_c, min_waiting_ms); *dec_ch = ch_c; *dec_bw = bw_c; @@ -1119,7 +1259,7 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 void dump_country_chplan(void *sel, const struct country_chplan *ent) { - _RTW_PRINT_SEL(sel, "\"%c%c\", 0x%02X%s\n" + RTW_PRINT_SEL(sel, "\"%c%c\", 0x%02X%s\n" , ent->alpha2[0], ent->alpha2[1], ent->chplan , COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : "" ); @@ -1131,10 +1271,10 @@ void dump_country_chplan_map(void *sel) u8 code[2]; #if RTW_DEF_MODULE_REGULATORY_CERT - _RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT:0x%x\n", RTW_DEF_MODULE_REGULATORY_CERT); + RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT:0x%x\n", RTW_DEF_MODULE_REGULATORY_CERT); #endif #ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP - _RTW_PRINT_SEL(sel, "CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\n"); + RTW_PRINT_SEL(sel, "CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\n"); #endif for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) { @@ -1150,16 +1290,21 @@ void dump_country_chplan_map(void *sel) void dump_chplan_id_list(void *sel) { + u8 first = 1; int i; for (i = 0; i < RTW_CHPLAN_MAX; i++) { if (!rtw_is_channel_plan_valid(i)) continue; - _RTW_PRINT_SEL(sel, "0x%02X ", i); + if (first) { + RTW_PRINT_SEL(sel, "0x%02X ", i); + first = 0; + } else + _RTW_PRINT_SEL(sel, "0x%02X ", i); } - RTW_PRINT_SEL(sel, "0x7F\n"); + _RTW_PRINT_SEL(sel, "0x7F\n"); } void dump_chplan_test(void *sel) @@ -1237,13 +1382,13 @@ void dump_cur_chset(void *sel, _adapter *adapter) break; if (i < MAX_CHANNEL_NUM) { - _RTW_PRINT_SEL(sel, "excl_chs:"); + RTW_PRINT_SEL(sel, "excl_chs:"); for (i = 0; i < MAX_CHANNEL_NUM; i++) { if (regsty->excl_chs[i] == 0) break; _RTW_PRINT_SEL(sel, "%u ", regsty->excl_chs[i]); } - RTW_PRINT_SEL(sel, "\n"); + _RTW_PRINT_SEL(sel, "\n"); } dump_chset(sel, rfctl->channel_set); @@ -1307,6 +1452,50 @@ u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) return valid; } +/** + * rtw_chset_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset to fit in channel plan + * @ch_set: channel plan to check + * @req_ch: pointer of the request ch, may be modified further + * @req_bw: pointer of the request bw, may be modified further + * @req_offset: pointer of the request offset, may be modified further + * @g_ch: pointer of the ongoing group ch + * @g_bw: pointer of the ongoing group bw, may be modified further + * @g_offset: pointer of the ongoing group offset, may be modified further + */ +void rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset + , u8 *g_ch, u8 *g_bw, u8 *g_offset) +{ + u8 r_ch, r_bw, r_offset; + u8 u_ch, u_bw, u_offset; + u8 cur_bw = *req_bw; + + while (1) { + r_ch = *req_ch; + r_bw = cur_bw; + r_offset = *req_offset; + u_ch = *g_ch; + u_bw = *g_bw; + u_offset = *g_offset; + + rtw_sync_chbw(&r_ch, &r_bw, &r_offset, &u_ch, &u_bw, &u_offset); + + if (rtw_chset_is_chbw_valid(ch_set, r_ch, r_bw, r_offset)) + break; + if (cur_bw == CHANNEL_WIDTH_20) { + rtw_warn_on(1); + break; + } + cur_bw--; + }; + + *req_ch = r_ch; + *req_bw = r_bw; + *req_offset = r_offset; + *g_ch = u_ch; + *g_bw = u_bw; + *g_offset = u_offset; +} + /* * Check the @param ch is fit with setband setting of @param adapter * @adapter: the given adapter @@ -1365,9 +1554,10 @@ Following are the initialization functions for WiFi MLME int init_hw_mlme_ext(_adapter *padapter) { struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + u8 rx_bar_enble = _TRUE; /* set_opmode_cmd(padapter, infra_client_with_mlme); */ /* removed */ - + rtw_hal_set_hwreg(padapter, HW_VAR_ENABLE_RX_BAR, &rx_bar_enble); set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); return _SUCCESS; @@ -1396,9 +1586,7 @@ static void init_mlme_ext_priv_value(_adapter *padapter) pmlmeext->mgnt_seq = 0;/* reset to zero when disconnect at client mode */ #ifdef CONFIG_IEEE80211W pmlmeext->sa_query_seq = 0; - pmlmeext->mgnt_80211w_IPN = 0; - pmlmeext->mgnt_80211w_IPN_rx = 0; -#endif /* CONFIG_IEEE80211W */ +#endif pmlmeext->cur_channel = padapter->registrypriv.channel; pmlmeext->cur_bwmode = CHANNEL_WIDTH_20; pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; @@ -1462,8 +1650,12 @@ void init_mlme_ext_timer(_adapter *padapter) rtw_init_timer(&pmlmeext->survey_timer, padapter, survey_timer_hdl, padapter); rtw_init_timer(&pmlmeext->link_timer, padapter, link_timer_hdl, padapter); #ifdef CONFIG_RTW_80211R - rtw_init_timer(&pmlmeext->ft_link_timer, padapter, ft_link_timer_hdl, padapter); - rtw_init_timer(&pmlmeext->ft_roam_timer, padapter, ft_roam_timer_hdl, padapter); + rtw_init_timer(&pmlmeext->ft_link_timer, padapter, rtw_ft_link_timer_hdl, padapter); + rtw_init_timer(&pmlmeext->ft_roam_timer, padapter, rtw_ft_roam_timer_hdl, padapter); +#endif + +#ifdef CONFIG_RTW_REPEATER_SON + rtw_init_timer(&pmlmeext->rson_scan_timer, padapter, rson_timer_hdl, padapter); #endif } @@ -1565,8 +1757,7 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; u8 *pframe = precv_frame->u.hdr.rx_data; struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(pframe)); - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct recv_priv *precvpriv = &padapter->recvpriv; #if 0 @@ -1614,7 +1805,7 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) if (GetRetry(pframe)) { if (precv_frame->u.hdr.attrib.seq_num == psta->RxMgmtFrameSeqNum) { /* drop the duplicate management frame */ - pdbgpriv->dbg_rx_dup_mgt_frame_drop_count++; + precvpriv->dbg_rx_dup_mgt_frame_drop_count++; RTW_INFO("Drop duplicate management frame with seq_num = %d.\n", precv_frame->u.hdr.attrib.seq_num); return; } @@ -1631,7 +1822,7 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_AP_MODE switch (get_frame_sub_type(pframe)) { case WIFI_AUTH: - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) ptable->func = &OnAuth; else ptable->func = &OnAuthClient; @@ -1639,32 +1830,30 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) case WIFI_ASSOCREQ: case WIFI_REASSOCREQ: _mgt_dispatcher(padapter, ptable, precv_frame); -#ifdef CONFIG_HOSTAPD_MLME - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + #ifdef CONFIG_HOSTAPD_MLME + if (MLME_IS_AP(padapter)) rtw_hostapd_mlme_rx(padapter, precv_frame); -#endif + #endif break; case WIFI_PROBEREQ: - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { -#ifdef CONFIG_HOSTAPD_MLME + _mgt_dispatcher(padapter, ptable, precv_frame); + #ifdef CONFIG_HOSTAPD_MLME + if (MLME_IS_AP(padapter)) rtw_hostapd_mlme_rx(padapter, precv_frame); -#else - _mgt_dispatcher(padapter, ptable, precv_frame); -#endif - } else - _mgt_dispatcher(padapter, ptable, precv_frame); + #endif break; case WIFI_BEACON: _mgt_dispatcher(padapter, ptable, precv_frame); break; case WIFI_ACTION: - /* if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) */ _mgt_dispatcher(padapter, ptable, precv_frame); break; default: _mgt_dispatcher(padapter, ptable, precv_frame); - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + #ifdef CONFIG_HOSTAPD_MLME + if (MLME_IS_AP(padapter)) rtw_hostapd_mlme_rx(padapter, precv_frame); + #endif break; } #else @@ -1806,7 +1995,7 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE && - check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE) == _FALSE) + check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE) return _SUCCESS; @@ -1880,32 +2069,25 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) /* generate pairing ID */ mac_addr = adapter_mac_addr(padapter); - peer_addr = psta->hwaddr; + peer_addr = psta->cmn.mac_addr; psta->pid = (u16)(((mac_addr[4] << 8) + mac_addr[5]) + ((peer_addr[4] << 8) + peer_addr[5])); /* update peer stainfo */ psta->isrc = _TRUE; - /* get a unique AID */ - if (psta->aid > 0) - RTW_INFO("old AID %d\n", psta->aid); + /* AID assignment */ + if (psta->cmn.aid > 0) + RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid); else { - for (psta->aid = 1; psta->aid <= NUM_STA; psta->aid++) - if (pstapriv->sta_aid[psta->aid - 1] == NULL) - break; - - if (psta->aid > pstapriv->max_num_sta) { - psta->aid = 0; - RTW_INFO("no room for more AIDs\n"); + if (!rtw_aid_alloc(padapter, psta)) { + RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter)); return _SUCCESS; - } else { - pstapriv->sta_aid[psta->aid - 1] = psta; - RTW_INFO("allocate new AID = (%d)\n", psta->aid); } + RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid); } psta->qos_option = 1; - psta->bw_mode = CHANNEL_WIDTH_20; + psta->cmn.bw_mode = CHANNEL_WIDTH_20; psta->ieee8021x_blocked = _FALSE; #ifdef CONFIG_80211N_HT psta->htpriv.ht_option = _TRUE; @@ -1925,7 +2107,7 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) psta->state |= _FW_LINKED; _exit_critical_bh(&psta->lock, &irqL); - report_add_sta_event(padapter, psta->hwaddr); + report_add_sta_event(padapter, psta->cmn.mac_addr); } @@ -1960,9 +2142,20 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) goto _issue_probersp; if ((ielen != 0 && _FALSE == _rtw_memcmp((void *)(p + 2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength)) - || (ielen == 0 && pmlmeinfo->hidden_ssid_mode) - ) - return _SUCCESS; + || (ielen == 0 && pmlmeinfo->hidden_ssid_mode)) + goto exit; + + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, WLAN_EID_MESH_ID, (int *)&ielen, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); + + if (!p) + goto exit; + if (ielen != 0 && _rtw_memcmp((void *)(p + 2), (void *)cur->mesh_id.Ssid, cur->mesh_id.SsidLength) == _FALSE) + goto exit; + } + #endif _issue_probersp: if (((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && @@ -1973,6 +2166,7 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) } +exit: return _SUCCESS; } @@ -2029,7 +2223,12 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) #endif - if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) { + if ((mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) + || (MLME_IS_MESH(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) + #ifdef CONFIG_RTW_REPEATER_SON + || (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) + #endif + ) { rtw_mi_report_survey_event(padapter, precv_frame); return _SUCCESS; } @@ -2128,19 +2327,24 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) } #endif - if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) { + if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS) + || (MLME_IS_MESH(padapter) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) + ) { rtw_mi_report_survey_event(padapter, precv_frame); return _SUCCESS; } - +#ifdef CONFIG_RTW_REPEATER_SON + if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) + rtw_mi_report_survey_event(padapter, precv_frame); +#endif rtw_check_legacy_ap(padapter, pframe, len); if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) { if ((pmlmeinfo->state & WIFI_FW_AUTH_NULL) - && rtw_sta_linking_test_wait_done() + && (rtw_sta_linking_test_wait_done() || pmlmeext->join_abort) ) { - if (rtw_sta_linking_test_force_fail()) { + if (rtw_sta_linking_test_force_fail() || pmlmeext->join_abort) { set_link_timer(pmlmeext, 1); return _SUCCESS; } @@ -2219,7 +2423,9 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } #endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */ - +#ifdef CONFIG_RTW_80211R + rtw_ft_update_bcn(padapter, precv_frame); +#endif ret = rtw_check_bcn_info(padapter, pframe, len); if (!ret) { RTW_PRINT("ap has changed, disconnect now\n "); @@ -2233,7 +2439,7 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) update_beacon_info(padapter, pframe, len, psta); } - pmlmepriv->cur_network_scanned->network.Rssi = precv_frame->u.hdr.attrib.phy_info.RecvSignalPower; + pmlmepriv->cur_network_scanned->network.Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power; adaptive_early_32k(pmlmeext, pframe, len); @@ -2253,9 +2459,11 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) #endif #endif /* CONFIG_TDLS */ -#ifdef CONFIG_DFS - process_csa_ie(padapter, pframe, len); /* channel switch announcement */ -#endif /* CONFIG_DFS */ + #ifdef CONFIG_DFS + process_csa_ie(padapter + , pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_ + , len - (WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_)); + #endif #ifdef CONFIG_P2P_PS process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); @@ -2348,6 +2556,29 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) return _FAIL; +#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_RTW_MESH) + if (MLME_IS_MESH(padapter)) { + if (!MLME_IS_ASOC(padapter)) + return _SUCCESS; + + #if CONFIG_RTW_MACADDR_ACL + if (rtw_access_ctrl(padapter, get_addr2_ptr(pframe)) == _FALSE) + return _SUCCESS; + #endif + + if (!rtw_mesh_plink_get(padapter, get_addr2_ptr(pframe))) { + if (adapter_to_rfctl(padapter)->offch_state == OFFCHS_NONE) + issue_probereq(padapter, &padapter->mlmepriv.cur_network.network.mesh_id, get_addr2_ptr(pframe)); + + /* only peer being added (checked by notify conditions) is allowed */ + return _SUCCESS; + } + + rtw_cfg80211_rx_mframe(padapter, precv_frame, NULL); + return _SUCCESS; + } +#endif + RTW_INFO("+OnAuth\n"); sa = get_addr2_ptr(pframe); @@ -2551,7 +2782,7 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) pstat = &stat; _rtw_memset((char *)pstat, '\0', sizeof(stat)); pstat->auth_seq = 2; - _rtw_memcpy(pstat->hwaddr, sa, 6); + _rtw_memcpy(pstat->cmn.mac_addr, sa, 6); #ifdef CONFIG_NATIVEAP_MLME issue_auth(padapter, pstat, (unsigned short)status); @@ -2569,12 +2800,6 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) unsigned int go2asoc = 0; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); -#ifdef CONFIG_RTW_80211R - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - ft_priv *pftpriv = &pmlmepriv->ftpriv; - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta = NULL; -#endif u8 *pframe = precv_frame->u.hdr.rx_data; uint pkt_len = precv_frame->u.hdr.len; @@ -2584,7 +2809,7 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN)) return _SUCCESS; - if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE)) + if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE) || pmlmeext->join_abort) return _SUCCESS; offset = (GetPrivacy(pframe)) ? 4 : 0; @@ -2641,29 +2866,9 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) if (go2asoc) { #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - u8 target_ap_addr[ETH_ALEN] = {0}; - - if ((rtw_chk_ft_status(padapter, RTW_FT_AUTHENTICATED_STA)) || - (rtw_chk_ft_status(padapter, RTW_FT_ASSOCIATING_STA)) || - (rtw_chk_ft_status(padapter, RTW_FT_ASSOCIATED_STA))) { - /*report_ft_reassoc_event already, and waiting for cfg80211_rtw_update_ft_ies*/ - return _SUCCESS; - } - - rtw_buf_update(&pmlmepriv->auth_rsp, &pmlmepriv->auth_rsp_len, pframe, pkt_len); - pftpriv->ft_event.ies = pmlmepriv->auth_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6; - pftpriv->ft_event.ies_len = pmlmepriv->auth_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6; - - /*Not support RIC*/ - pftpriv->ft_event.ric_ies = NULL; - pftpriv->ft_event.ric_ies_len = 0; - _rtw_memcpy(target_ap_addr, pmlmepriv->assoc_bssid, ETH_ALEN); - report_ft_reassoc_event(padapter, target_ap_addr); + if (rtw_ft_update_auth_rsp_ies(padapter, pframe, pkt_len)) return _SUCCESS; - } #endif - RTW_PRINT("auth success, start assoc\n"); start_clnt_assoc(padapter); return _SUCCESS; @@ -2684,15 +2889,11 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) u16 capab_info, listen_interval; struct rtw_ieee802_11_elems elems; struct sta_info *pstat; - unsigned char reassoc, *p, *pos, *wpa_ie; - unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01}; - int i, ie_len, wpa_ie_len, left; - u8 rate_set[16]; - u8 rate_num; + unsigned char reassoc, *p, *pos; + int i, ie_len, left; unsigned short status = _STATS_SUCCESSFUL_; unsigned short frame_type, ie_offset = 0; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct security_priv *psecuritypriv = &padapter->securitypriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *cur = &(pmlmeinfo->network); @@ -2739,15 +2940,6 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) goto asoc_class2_error; } - capab_info = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN); - /* capab_info = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); */ - /* listen_interval = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN+2)); */ - listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN + 2); - - left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset); - pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset); - - RTW_INFO("%s\n", __FUNCTION__); /* check if this stat has been successfully authenticated/assocated */ @@ -2764,7 +2956,6 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) pstat->state |= WIFI_FW_ASSOC_STATE; } - #if 0/* todo:tkip_countermeasures */ if (hapd->tkip_countermeasures) { resp = WLAN_REASON_MICHAEL_MIC_FAILURE; @@ -2772,8 +2963,19 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) } #endif - pstat->capability = capab_info; + /* now parse all ieee802_11 ie to point to elems */ + left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset); + pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset); + if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) { + RTW_INFO("STA " MAC_FMT " sent invalid association request\n", + MAC_ARG(pstat->cmn.mac_addr)); + status = _STATS_FAILURE_; + goto OnAssocReqFail; + } + + rtw_ap_parse_sta_capability(padapter, pstat, pframe + WLAN_HDR_A3_LEN); + listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN + 2); #if 0/* todo: */ /* check listen_interval */ if (listen_interval > hapd->conf->max_listen_interval) { @@ -2788,290 +2990,40 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) pstat->listen_interval = listen_interval; #endif - /* now parse all ieee802_11 ie to point to elems */ - if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed || - !elems.ssid) { - RTW_INFO("STA " MAC_FMT " sent invalid association request\n", - MAC_ARG(pstat->hwaddr)); - status = _STATS_FAILURE_; - goto OnAssocReqFail; - } - - /* now we should check all the fields... */ /* checking SSID */ - p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _SSID_IE_, &ie_len, - pkt_len - WLAN_HDR_A3_LEN - ie_offset); - if (p == NULL) - status = _STATS_FAILURE_; - - if (ie_len == 0) /* broadcast ssid, however it is not allowed in assocreq */ + if (elems.ssid == NULL + || elems.ssid_len == 0 + || elems.ssid_len != cur->Ssid.SsidLength + || _rtw_memcmp(elems.ssid, cur->Ssid.Ssid, cur->Ssid.SsidLength) == _FALSE + ) { status = _STATS_FAILURE_; - else { - /* check if ssid match */ - if (!_rtw_memcmp((void *)(p + 2), cur->Ssid.Ssid, cur->Ssid.SsidLength)) - status = _STATS_FAILURE_; - - if (ie_len != cur->Ssid.SsidLength) - status = _STATS_FAILURE_; - } - - if (_STATS_SUCCESSFUL_ != status) goto OnAssocReqFail; + } - rtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset, rate_set, &rate_num); - if (rate_num == 0) { - RTW_INFO(FUNC_ADPT_FMT" RX assoc-req with no supported rate\n", FUNC_ADPT_ARG(padapter)); - status = _STATS_FAILURE_; + /* (Extended) Supported rates */ + status = rtw_ap_parse_sta_supported_rates(padapter, pstat + , pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset); + if (status != _STATS_SUCCESSFUL_) goto OnAssocReqFail; - } - _rtw_memcpy(pstat->bssrateset, rate_set, rate_num); - pstat->bssratelen = rate_num; - UpdateBrateTblForSoftAP(pstat->bssrateset, pstat->bssratelen); /* check RSN/WPA/WPS */ - pstat->dot8021xalg = 0; - pstat->wpa_psk = 0; - pstat->wpa_group_cipher = 0; - pstat->wpa2_group_cipher = 0; - pstat->wpa_pairwise_cipher = 0; - pstat->wpa2_pairwise_cipher = 0; - _rtw_memset(pstat->wpa_ie, 0, sizeof(pstat->wpa_ie)); - if ((psecuritypriv->wpa_psk & BIT(1)) && elems.rsn_ie) { - - int group_cipher = 0, pairwise_cipher = 0; - - wpa_ie = elems.rsn_ie; - wpa_ie_len = elems.rsn_ie_len; - - if (rtw_parse_wpa2_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { - pstat->dot8021xalg = 1;/* psk, todo:802.1x */ - pstat->wpa_psk |= BIT(1); - - pstat->wpa2_group_cipher = group_cipher & psecuritypriv->wpa2_group_cipher; - pstat->wpa2_pairwise_cipher = pairwise_cipher & psecuritypriv->wpa2_pairwise_cipher; - - if (!pstat->wpa2_group_cipher) - status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; - - if (!pstat->wpa2_pairwise_cipher) - status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; - } else - status = WLAN_STATUS_INVALID_IE; - - } else if ((psecuritypriv->wpa_psk & BIT(0)) && elems.wpa_ie) { - - int group_cipher = 0, pairwise_cipher = 0; - - wpa_ie = elems.wpa_ie; - wpa_ie_len = elems.wpa_ie_len; - - if (rtw_parse_wpa_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { - pstat->dot8021xalg = 1;/* psk, todo:802.1x */ - pstat->wpa_psk |= BIT(0); - - pstat->wpa_group_cipher = group_cipher & psecuritypriv->wpa_group_cipher; - pstat->wpa_pairwise_cipher = pairwise_cipher & psecuritypriv->wpa_pairwise_cipher; - - if (!pstat->wpa_group_cipher) - status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; - - if (!pstat->wpa_pairwise_cipher) - status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; - - } else - status = WLAN_STATUS_INVALID_IE; - - } else { - wpa_ie = NULL; - wpa_ie_len = 0; - } - - if (_STATS_SUCCESSFUL_ != status) + status = rtw_ap_parse_sta_security_ie(padapter, pstat, &elems); + if (status != _STATS_SUCCESSFUL_) goto OnAssocReqFail; - pstat->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS); - /* if (hapd->conf->wps_state && wpa_ie == NULL) { */ /* todo: to check ap if supporting WPS */ - if (wpa_ie == NULL) { - if (elems.wps_ie) { - RTW_INFO("STA included WPS IE in " - "(Re)Association Request - assume WPS is " - "used\n"); - pstat->flags |= WLAN_STA_WPS; - /* wpabuf_free(sta->wps_ie); */ - /* sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, */ - /* elems.wps_ie_len - 4); */ - } else { - RTW_INFO("STA did not include WPA/RSN IE " - "in (Re)Association Request - possible WPS " - "use\n"); - pstat->flags |= WLAN_STA_MAYBE_WPS; - } - - - /* AP support WPA/RSN, and sta is going to do WPS, but AP is not ready */ - /* that the selected registrar of AP is _FLASE */ - if ((psecuritypriv->wpa_psk > 0) - && (pstat->flags & (WLAN_STA_WPS | WLAN_STA_MAYBE_WPS))) { - if (pmlmepriv->wps_beacon_ie) { - u8 selected_registrar = 0; - - rtw_get_wps_attr_content(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR , &selected_registrar, NULL); - - if (!selected_registrar) { - RTW_INFO("selected_registrar is _FALSE , or AP is not ready to do WPS\n"); - - status = _STATS_UNABLE_HANDLE_STA_; - - goto OnAssocReqFail; - } - } - } - - } else { - int copy_len; - - if (psecuritypriv->wpa_psk == 0) { - RTW_INFO("STA " MAC_FMT ": WPA/RSN IE in association " - "request, but AP don't support WPA/RSN\n", MAC_ARG(pstat->hwaddr)); - - status = WLAN_STATUS_INVALID_IE; - - goto OnAssocReqFail; - - } - - if (elems.wps_ie) { - RTW_INFO("STA included WPS IE in " - "(Re)Association Request - WPS is " - "used\n"); - pstat->flags |= WLAN_STA_WPS; - copy_len = 0; - } else - copy_len = ((wpa_ie_len + 2) > sizeof(pstat->wpa_ie)) ? (sizeof(pstat->wpa_ie)) : (wpa_ie_len + 2); - - - if (copy_len > 0) - _rtw_memcpy(pstat->wpa_ie, wpa_ie - 2, copy_len); - - } - - /* check if there is WMM IE & support WWM-PS */ - pstat->flags &= ~WLAN_STA_WME; - pstat->qos_option = 0; - pstat->qos_info = 0; - pstat->has_legacy_ac = _TRUE; - pstat->uapsd_vo = 0; - pstat->uapsd_vi = 0; - pstat->uapsd_be = 0; - pstat->uapsd_bk = 0; - if (pmlmepriv->qospriv.qos_option) { - p = pframe + WLAN_HDR_A3_LEN + ie_offset; - ie_len = 0; - for (;;) { - p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, pkt_len - WLAN_HDR_A3_LEN - ie_offset); - if (p != NULL) { - if (_rtw_memcmp(p + 2, WMM_IE, 6)) { - - pstat->flags |= WLAN_STA_WME; - - pstat->qos_option = 1; - pstat->qos_info = *(p + 8); - - pstat->max_sp_len = (pstat->qos_info >> 5) & 0x3; - - if ((pstat->qos_info & 0xf) != 0xf) - pstat->has_legacy_ac = _TRUE; - else - pstat->has_legacy_ac = _FALSE; - - if (pstat->qos_info & 0xf) { - if (pstat->qos_info & BIT(0)) - pstat->uapsd_vo = BIT(0) | BIT(1); - else - pstat->uapsd_vo = 0; - - if (pstat->qos_info & BIT(1)) - pstat->uapsd_vi = BIT(0) | BIT(1); - else - pstat->uapsd_vi = 0; - - if (pstat->qos_info & BIT(2)) - pstat->uapsd_bk = BIT(0) | BIT(1); - else - pstat->uapsd_bk = 0; - - if (pstat->qos_info & BIT(3)) - pstat->uapsd_be = BIT(0) | BIT(1); - else - pstat->uapsd_be = 0; - - } - - break; - } - } else - break; - p = p + ie_len + 2; - } - } - - -#ifdef CONFIG_80211N_HT - if (pmlmepriv->htpriv.ht_option == _FALSE) - goto bypass_ht_chk; - - /* save HT capabilities in the sta object */ - _rtw_memset(&pstat->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap)); - if (elems.ht_capabilities && elems.ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) { - pstat->flags |= WLAN_STA_HT; - - pstat->flags |= WLAN_STA_WME; - - _rtw_memcpy(&pstat->htpriv.ht_cap, elems.ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap)); - - } else - pstat->flags &= ~WLAN_STA_HT; -bypass_ht_chk: - - if ((pmlmepriv->htpriv.ht_option == _FALSE) && (pstat->flags & WLAN_STA_HT)) { - rtw_warn_on(1); - status = _STATS_FAILURE_; - goto OnAssocReqFail; - } -#endif /* CONFIG_80211N_HT */ - -#ifdef CONFIG_80211AC_VHT - if (pmlmepriv->vhtpriv.vht_option == _FALSE) - goto bypass_vht_chk; - - _rtw_memset(&pstat->vhtpriv, 0, sizeof(struct vht_priv)); - if (elems.vht_capabilities && elems.vht_capabilities_len == 12) { - pstat->flags |= WLAN_STA_VHT; - - _rtw_memcpy(pstat->vhtpriv.vht_cap, elems.vht_capabilities, 12); - - if (elems.vht_op_mode_notify && elems.vht_op_mode_notify_len == 1) - _rtw_memcpy(&pstat->vhtpriv.vht_op_mode_notify, elems.vht_op_mode_notify, 1); - else /* for Frame without Operating Mode notify ie; default: 80M */ - pstat->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80; - } else - pstat->flags &= ~WLAN_STA_VHT; -bypass_vht_chk: + rtw_ap_parse_sta_wmm_ie(padapter, pstat + , pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset); - if ((pmlmepriv->vhtpriv.vht_option == _FALSE) && (pstat->flags & WLAN_STA_VHT)) { - rtw_warn_on(1); - status = _STATS_FAILURE_; - goto OnAssocReqFail; - } -#endif /* CONFIG_80211AC_VHT */ + rtw_ap_parse_sta_ht_ie(padapter, pstat, &elems); + rtw_ap_parse_sta_vht_ie(padapter, pstat, &elems); if (((pstat->flags & WLAN_STA_HT) || (pstat->flags & WLAN_STA_VHT)) && ((pstat->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) || (pstat->wpa_pairwise_cipher & WPA_CIPHER_TKIP))) { - RTW_INFO("(V)HT: " MAC_FMT " tried to use TKIP with (V)HT association\n", MAC_ARG(pstat->hwaddr)); + RTW_INFO("(V)HT: " MAC_FMT " tried to use TKIP with (V)HT association\n", MAC_ARG(pstat->cmn.mac_addr)); pstat->flags &= ~WLAN_STA_HT; pstat->flags &= ~WLAN_STA_VHT; @@ -3080,24 +3032,6 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) */ } - - /* - * if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G) */ /* ? */ - pstat->flags |= WLAN_STA_NONERP; - for (i = 0; i < pstat->bssratelen; i++) { - if ((pstat->bssrateset[i] & 0x7f) > 22) { - pstat->flags &= ~WLAN_STA_NONERP; - break; - } - } - - if (pstat->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) - pstat->flags |= WLAN_STA_SHORT_PREAMBLE; - else - pstat->flags &= ~WLAN_STA_SHORT_PREAMBLE; - - - if (status != _STATS_SUCCESSFUL_) goto OnAssocReqFail; @@ -3121,44 +3055,37 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) pstat->p2p_status_code = p2p_status_code; #endif /* CONFIG_P2P */ +#ifdef CONFIG_RTW_REPEATER_SON + if (rtw_rson_ap_check_sta(padapter, pframe, pkt_len, ie_offset)) + goto OnAssocReqFail; +#endif + /* TODO: identify_proprietary_vendor_ie(); */ /* Realtek proprietary IE */ /* identify if this is Broadcom sta */ /* identify if this is ralink sta */ /* Customer proprietary IE */ +#ifdef CONFIG_RTW_80211K + rtw_ap_parse_sta_rm_en_cap(padapter, pstat, &elems); +#endif - - /* get a unique AID */ - if (pstat->aid > 0) - RTW_INFO(" old AID %d\n", pstat->aid); + /* AID assignment */ + if (pstat->cmn.aid > 0) + RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid); else { - for (pstat->aid = 1; pstat->aid <= NUM_STA; pstat->aid++) { - if (pstapriv->sta_aid[pstat->aid - 1] == NULL) { - if (pstat->aid > pstapriv->max_num_sta) { - pstat->aid = 0; - - RTW_INFO(" no room for more AIDs\n"); - - status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA; - - goto OnAssocReqFail; - - - } else { - pstapriv->sta_aid[pstat->aid - 1] = pstat; - RTW_INFO("allocate new AID = (%d)\n", pstat->aid); - break; - } - } + if (!rtw_aid_alloc(padapter, pstat)) { + RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter)); + status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA; + goto OnAssocReqFail; } + RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid); } - pstat->state &= (~WIFI_FW_ASSOC_STATE); pstat->state |= WIFI_FW_ASSOC_SUCCESS; /* RTW_INFO("==================%s, %d, (%x), bpairwise_key_installed=%d, MAC:"MAC_FMT"\n" - , __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->hwaddr)); */ + , __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->cmn.mac_addr)); */ #ifdef CONFIG_IEEE80211W if (pstat->bpairwise_key_installed != _TRUE) #endif /* CONFIG_IEEE80211W */ @@ -3220,12 +3147,12 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) #endif /* CONFIG_IEEE80211W */ { /* .3-(1) report sta add event */ - report_add_sta_event(padapter, pstat->hwaddr); + report_add_sta_event(padapter, pstat->cmn.mac_addr); } #ifdef CONFIG_IEEE80211W - if (pstat->bpairwise_key_installed == _TRUE && padapter->securitypriv.binstallBIPkey == _TRUE) { - RTW_INFO(MAC_FMT"\n", MAC_ARG(pstat->hwaddr)); - issue_action_SA_Query(padapter, pstat->hwaddr, 0, 0, IEEE80211W_RIGHT_KEY); + if (pstat->bpairwise_key_installed == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) { + RTW_INFO(MAC_FMT"\n", MAC_ARG(pstat->cmn.mac_addr)); + issue_action_SA_Query(padapter, pstat->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY); } #endif /* CONFIG_IEEE80211W */ #endif /* CONFIG_NATIVEAP_MLME */ @@ -3245,7 +3172,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_NATIVEAP_MLME - pstat->aid = 0; + pstat->cmn.aid = 0; if (frame_type == WIFI_ASSOCREQ) issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); else @@ -3259,6 +3186,34 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) } +#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K) +void rtw_roam_nb_discover(_adapter *padapter, u8 bfroce) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + u8 nb_req_issue = _FALSE; + + if (!check_fwstate(pmlmepriv, _FW_LINKED)) + return; + + if (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) + return; + + psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); + if (!psta) + return; + + if (bfroce || (!pmlmepriv->nb_info.nb_rpt_is_same)) + nb_req_issue = _TRUE; + + if (nb_req_issue && (psta->rm_en_cap[0] & RTW_RRM_NB_RPT_EN)) + rm_add_nb_req(padapter, psta); +} +#endif + unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) { uint i; @@ -3279,7 +3234,7 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN)) return _SUCCESS; - if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE))) + if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)) || pmlmeext->join_abort) return _SUCCESS; if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) @@ -3356,6 +3311,12 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) padapter->tdlsinfo.ch_switch_prohibited = _TRUE; break; #endif /* CONFIG_TDLS */ + +#ifdef CONFIG_RTW_80211K + case _EID_RRM_EN_CAP_IE_: + RM_IE_handler(padapter, pIE); + break; +#endif default: break; } @@ -3381,6 +3342,9 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) report_join_res(padapter, res); +#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K) + rtw_roam_nb_discover(padapter, _TRUE); +#endif return _SUCCESS; } @@ -3410,10 +3374,8 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); - rtw_lock_rx_suspend_timeout(8000); - #ifdef CONFIG_AP_MODE - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + if (MLME_IS_AP(padapter)) { _irqL irqL; struct sta_info *psta; struct sta_priv *pstapriv = &padapter->stapriv; @@ -3445,7 +3407,7 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } else #endif - { + if (!MLME_IS_MESH(padapter)) { int ignore_received_deauth = 0; /* Commented by Albert 20130604 */ @@ -3500,10 +3462,8 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); - rtw_lock_rx_suspend_timeout(8000); - #ifdef CONFIG_AP_MODE - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + if (MLME_IS_AP(padapter)) { _irqL irqL; struct sta_info *psta; struct sta_priv *pstapriv = &padapter->stapriv; @@ -3534,7 +3494,7 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } else #endif - { + if (!MLME_IS_MESH(padapter)) { RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n" , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe)); @@ -3570,7 +3530,7 @@ unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, struct ieee80211_info_element *ie; RTW_INFO(FUNC_NDEV_FMT" from "MAC_FMT"\n", - FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->hwaddr)); + FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->cmn.mac_addr)); for_each_ie(ie, ies, ies_len) { if (ie->id == WLAN_EID_CHANNEL_SWITCH) { @@ -3601,7 +3561,7 @@ unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, * 2. things after channel switching */ - ret = rtw_set_ch_cmd(padapter, ch, bwmode, ch_offset, _TRUE); + ret = rtw_set_chbw_cmd(padapter, ch, bwmode, ch_offset, 0); } exit: @@ -3619,8 +3579,6 @@ unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame) u8 category; u8 action; - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev)); - psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); if (!psta) @@ -3631,6 +3589,9 @@ unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame) goto exit; action = frame_body[1]; + + RTW_INFO(FUNC_ADPT_FMT" action:%u\n", FUNC_ADPT_ARG(padapter), action); + switch (action) { case RTW_WLAN_ACTION_SPCT_MSR_REQ: case RTW_WLAN_ACTION_SPCT_MSR_RPRT: @@ -3639,8 +3600,13 @@ unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame) break; case RTW_WLAN_ACTION_SPCT_CHL_SWITCH: #ifdef CONFIG_SPCT_CH_SWITCH - ret = on_action_spct_ch_switch(padapter, psta, &frame_body[2], - frame_len - (frame_body - pframe) - 2); + ret = on_action_spct_ch_switch(padapter, psta + , frame_body + 2, frame_len - (frame_body - pframe) - 2); +#elif defined(CONFIG_DFS) + if (MLME_IS_STA(padapter) && MLME_IS_ASOC(padapter)) { + process_csa_ie(padapter + , frame_body + 2, frame_len - (frame_body - pframe) - 2); + } #endif break; default: @@ -3666,12 +3632,13 @@ unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe) { unsigned int ret = _FAIL; struct sta_info *sta = NULL; - struct sta_priv *stapriv = &adapter->stapriv; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct sta_priv *stapriv = &(adapter->stapriv); u8 *frame = rframe->u.hdr.rx_data; - uint frame_len = rframe->u.hdr.len; + u32 frame_len = rframe->u.hdr.len; u8 *frame_body = (u8 *)(frame + sizeof(struct rtw_ieee80211_hdr_3addr)); - u8 category; - u8 action; + u32 frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; int cnt = 0; char msg[16]; @@ -3686,6 +3653,15 @@ unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe) action = frame_body[1]; switch (action) { +#ifdef CONFIG_RTW_80211R + case RTW_WLAN_ACTION_WNM_BTM_REQ: + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + RTW_INFO("WNM: RTW_WLAN_ACTION_WNM_BTM_REQ recv.\n"); + rtw_wnm_process_btm_req(adapter, frame_body, frame_body_len); + } + ret = _SUCCESS; + break; +#endif default: #ifdef CONFIG_IOCTL_CFG80211 cnt += sprintf((msg + cnt), "ACT_WNM %u", action); @@ -3917,7 +3893,7 @@ u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta) struct mlme_priv *mlme = &adapter->mlmepriv; struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info; s8 nss = -1; - u8 bw = rtw_min(sta->bw_mode, adapter->mlmeextpriv.cur_bwmode); + u8 bw = rtw_min(sta->cmn.bw_mode, adapter->mlmeextpriv.cur_bwmode); #ifdef CONFIG_80211AC_VHT if (is_supported_vht(sta->wireless_mode)) { @@ -3980,7 +3956,7 @@ u16 rtw_rx_ampdu_apply(_adapter *adapter) else size = rtw_rx_ampdu_size(adapter); - if (mlmeext_msr(mlmeext) == WIFI_FW_STATION_STATE) { + if (MLME_IS_STA(adapter)) { sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv)); if (sta) { u8 sta_size = size; @@ -3989,8 +3965,9 @@ u16 rtw_rx_ampdu_apply(_adapter *adapter) sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta)); adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size); } + /* TODO: TDLS peer */ - } else if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE) { + } else if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) { _irqL irqL; _list *phead, *plist; u8 peer_num = 0; @@ -4028,6 +4005,8 @@ u16 rtw_rx_ampdu_apply(_adapter *adapter) } } + /* TODO: ADHOC */ + return adj_cnt; } @@ -4043,6 +4022,7 @@ unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u8 *pframe = precv_frame->u.hdr.rx_data; struct sta_priv *pstapriv = &padapter->stapriv; + struct registry_priv *pregpriv = &padapter->registrypriv; #ifdef CONFIG_80211N_HT @@ -4104,8 +4084,14 @@ unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame) psta->htpriv.agg_enable_bitmap |= 1 << tid; psta->htpriv.candidate_tid_bitmap &= ~BIT(tid); /* amsdu in ampdu */ - if (frame_body[5] & 1) + if (pregpriv->tx_ampdu_amsdu == 0) + psta->htpriv.tx_amsdu_enable = _FALSE; + else if (pregpriv->tx_ampdu_amsdu == 1) psta->htpriv.tx_amsdu_enable = _TRUE; + else { + if (frame_body[5] & 1) + psta->htpriv.tx_amsdu_enable = _TRUE; + } } else psta->htpriv.agg_enable_bitmap &= ~BIT(tid); @@ -6544,7 +6530,7 @@ int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms) { int ret; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); do { ret = _issue_probereq_p2p(adapter, da, wait_ms > 0 ? _TRUE : _FALSE); @@ -7071,6 +7057,249 @@ unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame) return ret; } +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) +static u8 rtw_wnm_nb_elem_parsing( + u8* pdata, u32 data_len, u8 from_btm, + u32 *nb_rpt_num, u8 *nb_rpt_is_same, + struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates) +{ + u8 bfound = _FALSE, ret = _SUCCESS; + u8 *ptr, *pend, *op; + u32 elem_len, subelem_len, op_len; + u32 i, nb_rpt_entries = 0; + struct nb_rpt_hdr *pie; + struct wnm_btm_cant *pcandidate; + + if ((!pdata) || (!pnb)) + return _FAIL; + + if ((from_btm) && (!pcandidates)) + return _FAIL; + + ptr = pdata; + pend = ptr + data_len; + elem_len = data_len; + subelem_len = (u32)*(pdata+1); + + for (i=0; i < RTW_MAX_NB_RPT_NUM; i++) { + if (((ptr + 7) > pend) || (elem_len < subelem_len)) + break; + + if (*ptr != 0x34) { + RTW_ERR("WNM: invalid data(0x%2x)!\n", *ptr); + ret = _FAIL; + break; + } + + pie = (struct nb_rpt_hdr *)ptr; + if (from_btm) { + op = rtw_get_ie((u8 *)(ptr+15), + WNM_BTM_CAND_PREF_SUBEID, + &op_len, (subelem_len - 15)); + } + + ptr = (u8 *)(ptr + subelem_len + 2); + elem_len -= (subelem_len +2); + subelem_len = *(ptr+1); + if (from_btm) { + pcandidate = (pcandidates + i); + _rtw_memcpy(&pcandidate->nb_rpt, pie, sizeof(struct nb_rpt_hdr)); + if (op && (op_len !=0)) { + pcandidate->preference = *(op + 2); + bfound = _TRUE; + } else + pcandidate->preference = 0; + + RTW_DBG("WNM: preference check bssid("MAC_FMT + ") ,bss_info(0x%04X), reg_class(0x%02X), ch(%d)," + " phy_type(0x%02X), preference(0x%02X)\n", + MAC_ARG(pcandidate->nb_rpt.bssid), pcandidate->nb_rpt.bss_info, + pcandidate->nb_rpt.reg_class, pcandidate->nb_rpt.ch_num, + pcandidate->nb_rpt.phy_type, pcandidate->preference); + } else { + if (_rtw_memcmp(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr)) == _FALSE) + *nb_rpt_is_same = _FALSE; + _rtw_memcpy(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr)); + } + nb_rpt_entries++; + } + + if (from_btm) + pnb->preference_en = (bfound)?_TRUE:_FALSE; + + *nb_rpt_num = nb_rpt_entries; + return ret; +} + +/* selection sorting based on preference value + * IN : nb_rpt_entries - candidate num + * IN/OUT : pcandidates - candidate list + * return : TRUE - means pcandidates is updated. + */ +static u8 rtw_wnm_candidates_sorting( + u32 nb_rpt_entries, struct wnm_btm_cant *pcandidates) +{ + u8 updated = _FALSE; + u32 i, j, pos; + struct wnm_btm_cant swap; + struct wnm_btm_cant *pcant_1, *pcant_2; + + if ((!nb_rpt_entries) || (!pcandidates)) + return updated; + + for (i=0; i < (nb_rpt_entries - 1); i++) { + pos = i; + for (j=(i + 1); j < nb_rpt_entries; j++) { + pcant_1 = pcandidates+pos; + pcant_2 = pcandidates+j; + if ((pcant_1->preference) < (pcant_2->preference)) + pos = j; + } + + if (pos != i) { + updated = _TRUE; + _rtw_memcpy(&swap, (pcandidates+i), sizeof(struct wnm_btm_cant)); + _rtw_memcpy((pcandidates+i), (pcandidates+pos), sizeof(struct wnm_btm_cant)); + _rtw_memcpy((pcandidates+pos), &swap, sizeof(struct wnm_btm_cant)); + } + } + return updated; +} + +static void rtw_wnm_nb_info_update( + u32 nb_rpt_entries, u8 from_btm, + struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates, + u8 *nb_rpt_is_same) +{ + u8 is_found; + u32 i, j; + struct wnm_btm_cant *pcand; + + if (!pnb) + return; + + pnb->nb_rpt_ch_list_num = 0; + for (i=0; inb_rpt[i], &pcand->nb_rpt, + sizeof(struct nb_rpt_hdr)) == _FALSE) + *nb_rpt_is_same = _FALSE; + _rtw_memcpy(&pnb->nb_rpt[i], &pcand->nb_rpt, sizeof(struct nb_rpt_hdr)); + } + + RTW_DBG("WNM: bssid(" MAC_FMT + ") , bss_info(0x%04X), reg_class(0x%02X), ch_num(%d), phy_type(0x%02X)\n", + MAC_ARG(pnb->nb_rpt[i].bssid), pnb->nb_rpt[i].bss_info, + pnb->nb_rpt[i].reg_class, pnb->nb_rpt[i].ch_num, + pnb->nb_rpt[i].phy_type); + + if (pnb->nb_rpt[i].ch_num == 0) + continue; + + for (j=0; jnb_rpt[i].ch_num == pnb->nb_rpt_ch_list[j].hw_value) { + is_found = _TRUE; + break; + } + } + + if (!is_found) { + pnb->nb_rpt_ch_list[pnb->nb_rpt_ch_list_num].hw_value = pnb->nb_rpt[i].ch_num; + pnb->nb_rpt_ch_list_num++; + } + } +} + +static void rtw_wnm_btm_candidate_select(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); + struct wlan_network *pnetwork; + u8 bfound = _FALSE; + u32 i; + + for (i = 0; i < pnb->last_nb_rpt_entries; i++) { + pnetwork = rtw_find_network( + &(pmlmepriv->scanned_queue), + pnb->nb_rpt[i].bssid); + + if (pnetwork) { + bfound = _TRUE; + break; + } + } + + if (bfound) { + _rtw_memcpy(pnb->roam_target_addr, pnb->nb_rpt[i].bssid, ETH_ALEN); + RTW_INFO("WNM : select btm entry(%d) - %s("MAC_FMT", ch%u) rssi:%d\n" + , i + , pnetwork->network.Ssid.Ssid + , MAC_ARG(pnetwork->network.MacAddress) + , pnetwork->network.Configuration.DSConfig + , (int)pnetwork->network.Rssi); + } else + _rtw_memset(pnb->roam_target_addr,0, ETH_ALEN); +} + +u32 rtw_wnm_btm_candidates_survey( + _adapter *padapter, u8* pframe, u32 elem_len, u8 from_btm) +{ + struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); + struct wnm_btm_cant *pcandidate_list = NULL; + u8 nb_rpt_is_same = _TRUE; + u32 ret = _FAIL; + u32 nb_rpt_entries = 0; + + if (from_btm) { + u32 mlen = sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM; + pcandidate_list = (struct wnm_btm_cant *)rtw_malloc(mlen); + if (pcandidate_list == NULL) + goto exit; + } + + /*clean the status set last time*/ + _rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list)); + pnb->nb_rpt_valid = _FALSE; + if (!rtw_wnm_nb_elem_parsing( + pframe, elem_len, from_btm, + &nb_rpt_entries, &nb_rpt_is_same, + pnb, pcandidate_list)) + goto exit; + + if (nb_rpt_entries != 0) { + if ((from_btm) && (rtw_wnm_btm_preference_cap(padapter))) + rtw_wnm_candidates_sorting(nb_rpt_entries, pcandidate_list); + + rtw_wnm_nb_info_update( + nb_rpt_entries, from_btm, + pnb, pcandidate_list, &nb_rpt_is_same); + } + + RTW_INFO("nb_rpt_is_same = %d, nb_rpt_entries = %d, last_nb_rpt_entries = %d\n", + nb_rpt_is_same, nb_rpt_entries, pnb->last_nb_rpt_entries); + if ((nb_rpt_is_same == _TRUE) && (nb_rpt_entries == pnb->last_nb_rpt_entries)) + pnb->nb_rpt_is_same = _TRUE; + else { + pnb->nb_rpt_is_same = _FALSE; + pnb->last_nb_rpt_entries = nb_rpt_entries; + } + + if ((from_btm) && (nb_rpt_entries != 0)) + rtw_wnm_btm_candidate_select(padapter); + + pnb->nb_rpt_valid = _TRUE; + ret = _SUCCESS; + +exit: + if (from_btm && pcandidate_list) + rtw_mfree((u8 *)pcandidate_list, sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM); + + return ret; +} +#endif + unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) { #ifdef CONFIG_RTW_80211R @@ -7088,13 +7317,13 @@ unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) struct mlme_ext_info *pmlmeinfo = NULL; struct mlme_priv *pmlmepriv = NULL; struct wlan_network *proam_target = NULL; - ft_priv *pftpriv = NULL; + struct ft_roam_info *pft_roam = NULL; _irqL irqL; - pmlmeext = &padapter->mlmeextpriv; + pmlmeext = &(padapter->mlmeextpriv); pmlmeinfo = &(pmlmeext->mlmext_info); - pmlmepriv = &padapter->mlmepriv; - pftpriv = &pmlmepriv->ftpriv; + pmlmepriv = &(padapter->mlmepriv); + pft_roam = &(pmlmepriv->ft_roam); pframe = precv_frame->u.hdr.rx_data; frame_len = precv_frame->u.hdr.len; pframe_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); @@ -7105,8 +7334,8 @@ unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) action_code = pframe_body[1]; switch (action_code) { - case RTW_WLAN_ACTION_FT_RESPONSE: - RTW_INFO("FT: %s RTW_WLAN_ACTION_FT_RESPONSE\n", __func__); + case RTW_WLAN_ACTION_FT_RSP: + RTW_INFO("FT: RTW_WLAN_ACTION_FT_RSP recv.\n"); if (!_rtw_memcmp(adapter_mac_addr(padapter), &pframe_body[2], ETH_ALEN)) { RTW_ERR("FT: Unmatched STA MAC Address "MAC_FMT"\n", MAC_ARG(&pframe_body[2])); goto exit; @@ -7125,24 +7354,24 @@ unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) pie = rtw_get_ie(pframe_body, _MDIE_, &ft_ie_len, frame_len); if (pie) { - if (!_rtw_memcmp(&pftpriv->mdid, pie+2, 2)) { + if (!_rtw_memcmp(&pft_roam->mdid, pie+2, 2)) { RTW_ERR("FT: Invalid MDID\n"); goto exit; } } - rtw_set_ft_status(padapter, RTW_FT_REQUESTED_STA); + rtw_ft_set_status(padapter, RTW_FT_REQUESTED_STA); _cancel_timer_ex(&pmlmeext->ft_link_timer); /*Disconnect current AP*/ receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress, WLAN_REASON_ACTIVE_ROAM, _FALSE); - pftpriv->ft_action_len = frame_len; - _rtw_memcpy(pftpriv->ft_action, pframe, rtw_min(frame_len, RTW_MAX_FTIE_SZ)); + pft_roam->ft_action_len = frame_len; + _rtw_memcpy(pft_roam->ft_action, pframe, rtw_min(frame_len, RTW_FT_MAX_IE_SZ)); ret = _SUCCESS; break; - case RTW_WLAN_ACTION_FT_REQUEST: - case RTW_WLAN_ACTION_FT_CONFIRM: + case RTW_WLAN_ACTION_FT_REQ: + case RTW_WLAN_ACTION_FT_CONF: case RTW_WLAN_ACTION_FT_ACK: default: RTW_ERR("FT: Unsupported FT Action!\n"); @@ -7156,6 +7385,238 @@ unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) #endif } +#ifdef CONFIG_RTW_WNM +u8 rtw_wmn_btm_rsp_reason_decision(_adapter *padapter, u8* req_mode) +{ + struct recv_priv *precvpriv = &padapter->recvpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 reason = 0; + + if (!rtw_wnm_btm_diff_bss(padapter)) { + /* Reject - No suitable BSS transition candidates */ + reason = 7; + goto candidate_remove; + } + +#ifdef CONFIG_RTW_80211R + if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM)) { + /* Accept */ + reason = 0; + goto under_survey; + } +#endif + + if (((*req_mode) & DISASSOC_IMMINENT) == 0) { + /* Reject - Unspecified reject reason */ + reason = 1; + goto candidate_remove; + } + + if (precvpriv->signal_strength_data.avg_val >= pmlmepriv->roam_rssi_threshold) { + reason = 1; + goto candidate_remove; + } + +under_survey: + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) { + RTW_INFO("%s reject due to _FW_UNDER_SURVEY\n", __func__); + reason = 1; + } + +candidate_remove: + if (reason !=0) + rtw_wnm_reset_btm_candidate(&padapter->mlmepriv.nb_info); + + return reason; +} + +static u32 rtw_wnm_btm_candidates_offset_get(u8* pframe) +{ + u8 *pos = pframe; + u32 offset = 0; + + if (!pframe) + return 0; + + offset += 7; + pos += offset; + + /* BSS Termination Duration check */ + if (wnm_btm_bss_term_inc(pframe)) { + offset += 12; + pos += offset; + } + + /* Session Information URL check*/ + if (wnm_btm_ess_disassoc_im(pframe)) { + /*URL length field + URL variable length*/ + offset = 1 + *(pframe + offset); + pos += offset; + } + + offset = (pos - pframe); + return offset; +} + +static void rtw_wnm_btm_req_hdr_parsing(u8* pframe, struct btm_req_hdr *phdr) +{ + u8 *pos = pframe; + u32 offset = 0; + + if (!pframe || !phdr) + return; + + _rtw_memset(phdr, 0, sizeof(struct btm_req_hdr)); + phdr->req_mode = wnm_btm_req_mode(pframe); + phdr->disassoc_timer = wnm_btm_disassoc_timer(pframe); + phdr->validity_interval = wnm_btm_valid_interval(pframe); + if (wnm_btm_bss_term_inc(pframe)) { + _rtw_memcpy(&phdr->term_duration, + wnm_btm_term_duration_offset(pframe), + sizeof(struct btm_term_duration)); + } + + RTW_DBG("WNM: req_mode(%1x), disassoc_timer(%02x), interval(%x)\n", + phdr->req_mode, phdr->disassoc_timer, phdr->validity_interval); + if (wnm_btm_bss_term_inc(pframe)) + RTW_INFO("WNM: tsf(%llx), duration(%2x)\n", + phdr->term_duration.tsf, phdr->term_duration.duration); +} + +void rtw_wnm_roam_scan_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if (rtw_is_scan_deny(padapter)) + RTW_INFO("WNM: roam scan would abort by scan_deny!\n"); + + pmlmepriv->need_to_roam = _TRUE; + rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM); +} + +static void rtw_wnm_roam_scan(_adapter *padapter) +{ + struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); + + if (rtw_is_scan_deny(padapter)) { + _cancel_timer_ex(&pnb->roam_scan_timer); + _set_timer(&pnb->roam_scan_timer, 1000); + } else + rtw_wnm_roam_scan_hdl((void *)padapter); +} + +void rtw_wnm_process_btm_req(_adapter *padapter, u8* pframe, u32 frame_len) +{ + struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); + struct btm_req_hdr req_hdr; + u8 *ptr, reason; + u32 elem_len, offset; + + rtw_wnm_btm_req_hdr_parsing(pframe, &req_hdr); + offset = rtw_wnm_btm_candidates_offset_get(pframe); + if ((offset == 0) || ((frame_len - offset) <= 15)) + return; + + ptr = (pframe + offset); + elem_len = (frame_len - offset); + rtw_wnm_btm_candidates_survey(padapter, ptr, elem_len, _TRUE); + reason = rtw_wmn_btm_rsp_reason_decision(padapter, &pframe[3]); + rtw_wnm_issue_action(padapter, + RTW_WLAN_ACTION_WNM_BTM_RSP, reason); + + if (reason == 0) + rtw_wnm_roam_scan(padapter); +} + +void rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb) +{ + pnb->preference_en = _FALSE; + _rtw_memset(pnb->roam_target_addr, 0, ETH_ALEN); +} + +void rtw_wnm_reset_btm_state(_adapter *padapter) +{ + struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); + + pnb->last_nb_rpt_entries = 0; + pnb->nb_rpt_is_same = _TRUE; + pnb->nb_rpt_valid = _FALSE; + pnb->nb_rpt_ch_list_num = 0; + rtw_wnm_reset_btm_candidate(pnb); + _rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt)); + _rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list)); +} + +void rtw_wnm_issue_action(_adapter *padapter, u8 action, u8 reason) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct xmit_frame *pmgntframe; + struct rtw_ieee80211_hdr *pwlanhdr; + struct pkt_attrib *pattrib; + u8 category, dialog_token, termination_delay, *pframe; + u16 *fctrl; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + return ; + + pattrib = &(pmgntframe->attrib); + update_mgntframe_attrib(padapter, pattrib); + _rtw_memset(pmgntframe->buf_addr, 0, (WLANHDR_OFFSET + TXDESC_OFFSET)); + + pframe = (u8 *)(pmgntframe->buf_addr + TXDESC_OFFSET); + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + category = RTW_WLAN_CATEGORY_WNM; + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + + switch (action) { + case RTW_WLAN_ACTION_WNM_BTM_QUERY: + pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen)); + RTW_INFO("WNM: RTW_WLAN_ACTION_WNM_BTM_QUERY sent.\n"); + break; + case RTW_WLAN_ACTION_WNM_BTM_RSP: + termination_delay = 0; + pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(termination_delay), &(pattrib->pktlen)); + if (!is_zero_mac_addr(pmlmepriv->nb_info.roam_target_addr)) { + pframe = rtw_set_fixed_ie(pframe, 6, + pmlmepriv->nb_info.roam_target_addr, &(pattrib->pktlen)); + } + RTW_INFO("WNM: RTW_WLAN_ACTION_WNM_BTM_RSP sent. reason = %d\n", reason); + break; + default: + goto exit; + } + + pattrib->last_txcmdsz = pattrib->pktlen; + dump_mgntframe(padapter, pmgntframe); + +exit: + return; +} +#endif + unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame) { u8 *pframe = precv_frame->u.hdr.rx_data; @@ -7241,6 +7702,15 @@ unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame } #endif /* CONFIG_IEEE80211W */ +unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_RTW_80211K + return rm_on_action(padapter, precv_frame); +#else + return _SUCCESS; +#endif /* CONFIG_RTW_80211K */ +} + unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame) { return _SUCCESS; @@ -7460,21 +7930,13 @@ void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib) struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *pbcmc_sta = NULL; psta = rtw_get_stainfo(pstapriv, pattrib->ra); - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); pattrib->hdrlen = 24; pattrib->nr_frags = 1; pattrib->priority = 7; - - if (pbcmc_sta) - pattrib->mac_id = pbcmc_sta->mac_id; - else { - pattrib->mac_id = 0; - RTW_INFO("mgmt use mac_id 0 will affect RA\n"); - } + pattrib->mac_id = RTW_DEFAULT_MGMT_MACID; pattrib->qsel = QSLT_MGNT; pattrib->pktlen = 0; @@ -7526,23 +7988,12 @@ void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib) u8 wireless_mode; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct sta_info *pbcmc_sta = NULL; /* _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); */ - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); - pattrib->hdrlen = 24; pattrib->nr_frags = 1; pattrib->priority = 7; - - if (pbcmc_sta) - pattrib->mac_id = pbcmc_sta->mac_id; - else { - pattrib->mac_id = 1; /* use STA's BCMC sta-info macid */ - - if (MLME_IS_AP(padapter) || MLME_IS_GO(padapter)) - RTW_INFO("%s-"ADPT_FMT" get bcmc sta_info fail,use MACID=1\n", __func__, ADPT_ARG(padapter)); - } + pattrib->mac_id = RTW_DEFAULT_MGMT_MACID; pattrib->qsel = QSLT_MGNT; #ifdef CONFIG_MCC_MODE @@ -7579,24 +8030,26 @@ void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntfr { u8 *pframe; struct pkt_attrib *pattrib = &pmgntframe->attrib; -#ifdef CONFIG_BEAMFORMING +#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) struct sta_info *sta = NULL; -#endif /* CONFIG_BEAMFORMING */ +#endif pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; _rtw_memcpy(pattrib->ra, GetAddr1Ptr(pframe), ETH_ALEN); _rtw_memcpy(pattrib->ta, get_addr2_ptr(pframe), ETH_ALEN); -#ifdef CONFIG_BEAMFORMING +#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) sta = pattrib->psta; if (!sta) { sta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); pattrib->psta = sta; } + #ifdef CONFIG_BEAMFORMING if (sta) update_attrib_txbf_info(padapter, pattrib, sta); -#endif /* CONFIG_BEAMFORMING */ + #endif +#endif /* defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) */ } void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe) @@ -7801,7 +8254,7 @@ void issue_beacon(_adapter *padapter, int timeout_ms) pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { /* RTW_INFO("ie len=%d\n", cur_network->IELength); */ #ifdef CONFIG_P2P /* for P2P : Primary Device Type & Device Name */ @@ -7925,6 +8378,12 @@ void issue_beacon(_adapter *padapter, int timeout_ms) _clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS); } +#ifdef CONFIG_RTW_80211K + pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, + sizeof(padapter->rmpriv.rm_en_cap_def), + padapter->rmpriv.rm_en_cap_def, &pattrib->pktlen); +#endif + #ifdef CONFIG_P2P if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { u32 len; @@ -7953,7 +8412,9 @@ void issue_beacon(_adapter *padapter, int timeout_ms) #endif } #endif /* CONFIG_P2P */ - +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen); +#endif #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_BEACON_VENDOR_IE_BIT); #endif @@ -8175,6 +8636,9 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe pattrib->pktlen += ssid_ielen_diff; } } +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen); +#endif #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_PROBERESP_VENDOR_IE_BIT); #endif @@ -8234,6 +8698,12 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe } +#ifdef CONFIG_RTW_80211K + pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, + sizeof(padapter->rmpriv.rm_en_cap_def), + padapter->rmpriv.rm_en_cap_def, &pattrib->pktlen); +#endif + #ifdef CONFIG_P2P if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) /* IOT issue, When wifi_spec is not set, send probe_resp with P2P IE even if probe_req has no P2P IE */ @@ -8283,7 +8753,7 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe u16 cu_ch = (u16)cur_network->Configuration.DSConfig; RTW_INFO("%s, reply rc(pid=0x%x) device "MAC_FMT" in ch=%d\n", __FUNCTION__, - psta->pid, MAC_ARG(psta->hwaddr), cu_ch); + psta->pid, MAC_ARG(psta->cmn.mac_addr), cu_ch); /* append vendor specific ie */ _rtw_memcpy(RC_INFO, RC_OUI, sizeof(RC_OUI)); @@ -8306,7 +8776,7 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe } -int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps, int wait_ack) +int _issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int wait_ack) { int ret = _FAIL; struct xmit_frame *pmgntframe; @@ -8364,7 +8834,7 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - if (pssid) + if (pssid && !MLME_IS_MESH(padapter)) pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen)); else pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen)); @@ -8380,6 +8850,15 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, if (ch) pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, &ch, &pattrib->pktlen); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + if (pssid) + pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, pssid->Ssid, pssid->SsidLength); + else + pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, NULL, 0); + } +#endif + if (append_wps) { /* add wps_ie for wps2.0 */ if (pmlmepriv->wps_probe_req_ie_len > 0 && pmlmepriv->wps_probe_req_ie) { @@ -8407,7 +8886,7 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, return ret; } -inline void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da) +inline void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da) { _issue_probereq(padapter, pssid, da, 0, 1, _FALSE); } @@ -8417,12 +8896,12 @@ inline void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da) * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX * try_cnt means the maximal TX count to try */ -int issue_probereq_ex(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps, +int issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int try_cnt, int wait_ms) { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; @@ -8475,14 +8954,6 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); -#ifdef CONFIG_RTW_80211R - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - ft_priv *pftpriv = &pmlmepriv->ftpriv; - u8 is_ft_roaming = _FALSE; - u8 is_ft_roaming_with_rsn_ie = _TRUE; - u8 *pie = NULL; - u32 ft_ie_len = 0; -#endif if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) return; @@ -8514,7 +8985,7 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status if (psta) { /* for AP mode */ #ifdef CONFIG_NATIVEAP_MLME - _rtw_memcpy(pwlanhdr->addr1, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); @@ -8552,11 +9023,9 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); #ifdef CONFIG_RTW_80211R - /*For Fast BSS Transition */ - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - is_ft_roaming = _TRUE; - val16 = 2; /* 2: 802.11R FTAA */ - val16 = cpu_to_le16(val16); + if (rtw_ft_roam(padapter)) { + /* 2: 802.11R FTAA */ + val16 = cpu_to_le16(2); } else #endif { @@ -8594,21 +9063,7 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); #ifdef CONFIG_RTW_80211R - if (is_ft_roaming == _TRUE) { - pie = rtw_get_ie(pftpriv->updated_ft_ies, EID_WPA2, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie) - pframe = rtw_set_ie(pframe, EID_WPA2, ft_ie_len, pie+2, &(pattrib->pktlen)); - else - is_ft_roaming_with_rsn_ie = _FALSE; - - pie = rtw_get_ie(pftpriv->updated_ft_ies, _MDIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie) - pframe = rtw_set_ie(pframe, _MDIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); - - pie = rtw_get_ie(pftpriv->updated_ft_ies, _FTIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie && is_ft_roaming_with_rsn_ie) - pframe = rtw_set_ie(pframe, _FTIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); - } + rtw_ft_build_auth_req_ies(padapter, pattrib, &pframe); #endif /* then checking to see if sending challenging text... */ @@ -8684,7 +9139,7 @@ void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *p fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->hwaddr, ETH_ALEN); + _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->cmn.mac_addr, ETH_ALEN); _rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); @@ -8708,7 +9163,7 @@ void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *p ie_status = cpu_to_le16(status); pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&ie_status, &(pattrib->pktlen)); - val = cpu_to_le16(pstat->aid | BIT(14) | BIT(15)); + val = cpu_to_le16(pstat->cmn.aid | BIT(14) | BIT(15)); pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen)); if (pstat->bssratelen <= 8) @@ -8895,11 +9350,6 @@ void _issue_assocreq(_adapter *padapter, u8 is_reassoc) u8 pow_cap_ele[2] = { 0x00 }; u8 sup_ch[30 * 2] = {0x00 }, sup_ch_idx = 0, idx_5g = 2; /* For supported channel */ #endif /* CONFIG_DFS */ -#ifdef CONFIG_RTW_80211R - u8 *pie = NULL; - u32 ft_ie_len = 0; - ft_priv *pftpriv = &pmlmepriv->ftpriv; -#endif if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; @@ -9068,6 +9518,16 @@ void _issue_assocreq(_adapter *padapter, u8 is_reassoc) else RTW_INFO("%s: Connect to AP without 11b and 11g data rate!\n", __FUNCTION__); +#ifdef CONFIG_RTW_80211K + if (pmlmeinfo->network.PhyInfo.rm_en_cap[0] /* RM Enabled Capabilities */ + | pmlmeinfo->network.PhyInfo.rm_en_cap[1] + | pmlmeinfo->network.PhyInfo.rm_en_cap[2] + | pmlmeinfo->network.PhyInfo.rm_en_cap[3] + | pmlmeinfo->network.PhyInfo.rm_en_cap[4]) + pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, 5, + (u8 *)padapter->rmpriv.rm_en_cap_def, &(pattrib->pktlen)); +#endif /* CONFIG_RTW_80211K */ + /* vendor specific IE, such as WPA, WMM, WPS */ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) { pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); @@ -9092,10 +9552,8 @@ void _issue_assocreq(_adapter *padapter, u8 is_reassoc) case EID_WPA2: #ifdef CONFIG_RTW_80211R - if ((is_reassoc == _TRUE) && (rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - pie = rtw_get_ie(pftpriv->updated_ft_ies, EID_WPA2, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie) - pframe = rtw_set_ie(pframe, EID_WPA2, ft_ie_len, pie+2, &(pattrib->pktlen)); + if ((is_reassoc) && (rtw_ft_roam(padapter))) { + rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe); } else #endif pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen)); @@ -9292,31 +9750,14 @@ void _issue_assocreq(_adapter *padapter, u8 is_reassoc) pframe += wfdielen; pattrib->pktlen += wfdielen; #endif +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen); +#endif #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_ASSOCREQ_VENDOR_IE_BIT); #endif #ifdef CONFIG_RTW_80211R - if (rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - u8 mdieval[3] = {0}; - - _rtw_memcpy(mdieval, &(pftpriv->mdid), 2); - mdieval[2] = pftpriv->ft_cap; - pframe = rtw_set_ie(pframe, _MDIE_, 3, mdieval, &(pattrib->pktlen)); - } - - if (is_reassoc == _TRUE) { - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - u8 is_ft_roaming_with_rsn_ie = _TRUE; - - pie = rtw_get_ie(pftpriv->updated_ft_ies, EID_WPA2, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (!pie) - is_ft_roaming_with_rsn_ie = _FALSE; - - pie = rtw_get_ie(pftpriv->updated_ft_ies, _FTIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie && is_ft_roaming_with_rsn_ie) - pframe = rtw_set_ie(pframe, _FTIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); - } - } + rtw_ft_build_assoc_req_ies(padapter, is_reassoc, pattrib, &pframe); #endif pattrib->last_txcmdsz = pattrib->pktlen; @@ -9355,6 +9796,7 @@ static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int p struct xmit_priv *pxmitpriv; struct mlme_ext_priv *pmlmeext; struct mlme_ext_info *pmlmeinfo; + u8 a4_shift; /* RTW_INFO("%s:%d\n", __FUNCTION__, power_mode); */ @@ -9385,24 +9827,38 @@ static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int p fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) + if (MLME_IS_AP(padapter)) SetFrDs(fctrl); - else if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) + else if (MLME_IS_STA(padapter)) SetToDs(fctrl); + else if (MLME_IS_MESH(padapter)) { + SetToDs(fctrl); + SetFrDs(fctrl); + } if (power_mode) SetPwrMgt(fctrl); - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + if (get_tofr_ds(fctrl) == 3) { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN); + a4_shift = ETH_ALEN; + pattrib->hdrlen += ETH_ALEN; + } else { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + a4_shift = 0; + } SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; set_frame_sub_type(pframe, WIFI_DATA_NULL); - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pframe += sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift; + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift; pattrib->last_txcmdsz = pattrib->pktlen; @@ -9418,8 +9874,6 @@ static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int p } /* - * [IMPORTANT] Don't call this function in interrupt context - * * When wait_ms > 0, this function should be called at process context * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX @@ -9430,48 +9884,17 @@ int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mod { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct sta_info *psta; - u8 macid_sleep_reg_access = _TRUE; - -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - /* driver doesn't access macid sleep reg under MCC */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { - macid_sleep_reg_access = _FALSE; - - if (da == NULL) { - RTW_INFO("Warning: Do not tx null data to AP under MCC mode\n"); - rtw_warn_on(1); - } - - } - } -#endif if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; - /* da == NULL, assum it's null data for sta to ap*/ + /* da == NULL, assum it's null data for sta to ap */ if (da == NULL) da = get_my_bssid(&(pmlmeinfo->network)); - psta = rtw_get_stainfo(&padapter->stapriv, da); - if (psta) { - if (macid_sleep_reg_access) { - if (power_mode) - rtw_hal_macid_sleep(padapter, psta->mac_id); - else - rtw_hal_macid_wakeup(padapter, psta->mac_id); - } - } else { - RTW_INFO(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n", - FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode ? "sleep" : "wakeup"); - rtw_warn_on(1); - } - do { ret = _issue_nulldata(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE); @@ -9506,33 +9929,8 @@ int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mod return ret; } -/* - * [IMPORTANT] This function run in interrupt context - * - * The null data packet would be sent without power bit, - * and not guarantee success. - */ -s32 issue_nulldata_in_interrupt(PADAPTER padapter, u8 *da, unsigned int power_mode) -{ - int ret; - struct mlme_ext_priv *pmlmeext; - struct mlme_ext_info *pmlmeinfo; - - - pmlmeext = &padapter->mlmeextpriv; - pmlmeinfo = &pmlmeext->mlmext_info; - - /* da == NULL, assum it's null data for sta to ap*/ - if (da == NULL) - da = get_my_bssid(&(pmlmeinfo->network)); - - ret = _issue_nulldata(padapter, da, power_mode, _FALSE); - - return ret; -} - /* when wait_ack is ture, this function shoule be called at process context */ -static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int wait_ack) +static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int wait_ack) { int ret = _FAIL; struct xmit_frame *pmgntframe; @@ -9543,11 +9941,12 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 a4_shift; if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; - RTW_INFO("%s\n", __FUNCTION__); + /* RTW_INFO("%s\n", __FUNCTION__); */ pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) @@ -9571,14 +9970,35 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) + if (MLME_IS_AP(padapter)) SetFrDs(fctrl); - else if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) + else if (MLME_IS_STA(padapter)) + SetToDs(fctrl); + else if (MLME_IS_MESH(padapter)) { SetToDs(fctrl); + SetFrDs(fctrl); + } + + if (ps) + SetPwrMgt(fctrl); if (pattrib->mdata) SetMData(fctrl); + if (get_tofr_ds(fctrl) == 3) { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN); + a4_shift = ETH_ALEN; + pattrib->hdrlen += ETH_ALEN; + } else { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + a4_shift = 0; + } + qc = (unsigned short *)(pframe + pattrib->hdrlen - 2); SetPriority(qc, tid); @@ -9587,16 +10007,12 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i SetAckpolicy(qc, pattrib->ack_policy); - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); - pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); + pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift; + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift; pattrib->last_txcmdsz = pattrib->pktlen; @@ -9618,11 +10034,11 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i * try_cnt means the maximal TX count to try * da == NULL for station mode */ -int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_cnt, int wait_ms) +int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms) { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -9634,7 +10050,7 @@ int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_c da = get_my_bssid(&(pmlmeinfo->network)); do { - ret = _issue_qos_nulldata(padapter, da, tid, wait_ms > 0 ? _TRUE : _FALSE); + ret = _issue_qos_nulldata(padapter, da, tid, ps, wait_ms > 0 ? _TRUE : _FALSE); i++; @@ -9763,7 +10179,7 @@ int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_c { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; @@ -9933,7 +10349,7 @@ void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned ch pmlmeext->sa_query_seq++; /* send sa query request to AP, AP should reply sa query response in 1 second */ if (pattrib->key_type == IEEE80211W_RIGHT_KEY) { - psta = rtw_get_stainfo(pstapriv, raddr); + psta = rtw_get_stainfo(pstapriv, pwlanhdr->addr1); if (psta != NULL) { /* RTW_INFO("%s, %d, set dot11w_expire_timer\n", __func__, __LINE__); */ _set_timer(&psta->dot11w_expire_timer, 1000); @@ -10086,9 +10502,9 @@ static int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned ch BA_para_set |= (size << 6) & RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK; if (!padapter->registrypriv.wifi_spec) { - if (pregpriv->ampdu_amsdu == 0) /* disabled */ + if (pregpriv->rx_ampdu_amsdu == 0) /* disabled */ BA_para_set &= ~BIT(0); - else if (pregpriv->ampdu_amsdu == 1) /* enabled */ + else if (pregpriv->rx_ampdu_amsdu == 1) /* enabled */ BA_para_set |= BIT(0); } @@ -10183,7 +10599,7 @@ inline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter))) goto exit; @@ -10261,7 +10677,7 @@ int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter))) goto exit; @@ -10301,7 +10717,7 @@ int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 return ret; } -static void issue_action_BSSCoexistPacket(_adapter *padapter) +void issue_action_BSSCoexistPacket(_adapter *padapter) { _irqL irqL; _list *plist, *phead; @@ -10542,7 +10958,7 @@ int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 New { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; @@ -10623,9 +11039,9 @@ static unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct if (rtw_del_rx_ampdu_test_trigger_no_tx_fail()) ret = _FAIL; else if (wait_ack) - ret = issue_del_ba_ex(adapter, sta->hwaddr, tid, 37, initiator, 3, 1); + ret = issue_del_ba_ex(adapter, sta->cmn.mac_addr, tid, 37, initiator, 3, 1); else - issue_del_ba(adapter, sta->hwaddr, tid, 37, initiator); + issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator); if (ret == _FAIL && sta->recvreorder_ctrl[tid].enable == _FALSE) sta->recvreorder_ctrl[tid].ampdu_size = ampdu_size_bak; @@ -10636,7 +11052,7 @@ static unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct if (force || sta->htpriv.agg_enable_bitmap & BIT(tid)) { sta->htpriv.agg_enable_bitmap &= ~BIT(tid); sta->htpriv.candidate_tid_bitmap &= ~BIT(tid); - issue_del_ba(adapter, sta->hwaddr, tid, 37, initiator); + issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator); } #endif } @@ -10697,9 +11113,7 @@ unsigned int send_beacon(_adapter *padapter) #ifdef CONFIG_PCI_HCI /* bypass TX BCN queue because op ch is switching/waiting */ if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) - #ifdef CONFIG_DFS_MASTER || IS_CH_WAITING(adapter_to_rfctl(padapter)) - #endif ) return _SUCCESS; @@ -10722,35 +11136,45 @@ unsigned int send_beacon(_adapter *padapter) #endif #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); /* bypass TX BCN queue because op ch is switching/waiting */ if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) - #ifdef CONFIG_DFS_MASTER || IS_CH_WAITING(adapter_to_rfctl(padapter)) - #endif ) return _SUCCESS; - rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); - rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); - do { - issue_beacon(padapter, 100); - issue++; +#if defined(CONFIG_USB_HCI) +#if defined(CONFIG_RTL8812A) + if (IS_FULL_SPEED_USB(padapter)) { + issue_beacon(padapter, 300); + bxmitok = _TRUE; + } else +#endif +#endif + { + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); + rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); do { - rtw_yield_os(); - rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok)); - poll++; - } while ((poll % 10) != 0 && _FALSE == bxmitok && !RTW_CANNOT_RUN(padapter)); - - } while (_FALSE == bxmitok && issue < 100 && !RTW_CANNOT_RUN(padapter)); + issue_beacon(padapter, 100); + issue++; + do { + rtw_yield_os(); + rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok)); + poll++; + } while ((poll % 10) != 0 && _FALSE == bxmitok && !RTW_CANNOT_RUN(padapter)); + } while (bxmitok == _FALSE && (issue < 100) && !RTW_CANNOT_RUN(padapter)); + } if (RTW_CANNOT_RUN(padapter)) return _FAIL; if (_FALSE == bxmitok) { RTW_INFO("%s fail! %u ms\n", __FUNCTION__, rtw_get_passing_time_ms(start)); + #ifdef CONFIG_BCN_RECOVERY + GET_HAL_DATA(padapter)->issue_bcn_fail++; + #endif /*CONFIG_BCN_RECOVERY*/ return _FAIL; } else { u32 passing_time = rtw_get_passing_time_ms(start); @@ -10796,16 +11220,20 @@ BOOLEAN IsLegal5GChannel( u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid) { int i; - u32 len; + sint len; u8 *p; + u8 rf_path; u16 val16, subtype; u8 *pframe = precv_frame->u.hdr.rx_data; u32 packet_len = precv_frame->u.hdr.len; u8 ie_offset; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr); if (len > MAX_IE_SZ) { @@ -10818,18 +11246,18 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI subtype = get_frame_sub_type(pframe); if (subtype == WIFI_BEACON) { - bssid->Reserved[0] = 1; + bssid->Reserved[0] = BSS_TYPE_BCN; ie_offset = _BEACON_IE_OFFSET_; } else { /* FIXME : more type */ if (subtype == WIFI_PROBERSP) { ie_offset = _PROBERSP_IE_OFFSET_; - bssid->Reserved[0] = 3; + bssid->Reserved[0] = BSS_TYPE_PROB_RSP; } else if (subtype == WIFI_PROBEREQ) { ie_offset = _PROBEREQ_IE_OFFSET_; - bssid->Reserved[0] = 2; + bssid->Reserved[0] = BSS_TYPE_PROB_REQ; } else { - bssid->Reserved[0] = 0; + bssid->Reserved[0] = BSS_TYPE_UNDEF; ie_offset = _FIXED_IE_LENGTH_; } } @@ -10842,9 +11270,19 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI /* get the signal strength */ /* bssid->Rssi = precv_frame->u.hdr.attrib.SignalStrength; */ /* 0-100 index. */ - bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.RecvSignalPower; /* in dBM.raw data */ - bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.SignalQuality;/* in percentage */ - bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.SignalStrength;/* in percentage */ + bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power; /* in dBM.raw data */ + bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.signal_quality;/* in percentage */ + bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.signal_strength;/* in percentage */ + + /* get rx_snr */ + if (precv_frame->u.hdr.attrib.data_rate >= DESC_RATE11M) { + bssid->PhyInfo.is_cck_rate = 0; + for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) + bssid->PhyInfo.rx_snr[rf_path] = + precv_frame->u.hdr.attrib.phy_info.rx_snr[rf_path]; + } else + bssid->PhyInfo.is_cck_rate = 1; + #ifdef CONFIG_ANTENNA_DIVERSITY rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &(bssid->PhyInfo.Optimum_antenna), NULL); #endif @@ -10954,12 +11392,49 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid); - if (val16 & BIT(0)) { + if ((val16 & 0x03) == cap_ESS) { bssid->InfrastructureMode = Ndis802_11Infrastructure; _rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN); - } else { + } else if ((val16 & 0x03) == cap_IBSS){ bssid->InfrastructureMode = Ndis802_11IBSS; _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); + } else if ((val16 & 0x03) == 0x00){ + u8 *mesh_id_ie, *mesh_conf_ie; + sint mesh_id_ie_len, mesh_conf_ie_len; + + mesh_id_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_ID, &mesh_id_ie_len, bssid->IELength - ie_offset); + mesh_conf_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_CONFIG, &mesh_conf_ie_len, bssid->IELength - ie_offset); + if (mesh_id_ie || mesh_conf_ie) { + if (!mesh_id_ie) { + RTW_INFO("cannot find Mesh ID for survey event\n"); + return _FAIL; + } + if (mesh_id_ie_len) { + if (mesh_id_ie_len > NDIS_802_11_LENGTH_SSID) { + RTW_INFO("Mesh ID too long (%d) for survey event\n", mesh_id_ie_len); + return _FAIL; + } + _rtw_memcpy(bssid->mesh_id.Ssid, (mesh_id_ie + 2), mesh_id_ie_len); + bssid->mesh_id.SsidLength = mesh_id_ie_len; + } else + bssid->mesh_id.SsidLength = 0; + + if (!mesh_conf_ie) { + RTW_INFO("cannot find Mesh config for survey event\n"); + return _FAIL; + } + if (mesh_conf_ie_len != 7) { + RTW_INFO("invalid Mesh conf IE len (%d) for survey event\n", mesh_conf_ie_len); + return _FAIL; + } + + bssid->InfrastructureMode = Ndis802_11_mesh; + _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); + } else { + /* default cases */ + bssid->InfrastructureMode = Ndis802_11IBSS; + _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); + } } if (val16 & BIT(4)) @@ -11006,6 +11481,14 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI if (bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter)) bssid->PhyInfo.SignalQuality = 101; +#ifdef CONFIG_RTW_80211K + p = rtw_get_ie(bssid->IEs + ie_offset, _EID_RRM_EN_CAP_IE_, &len, bssid->IELength - ie_offset); + if (p) + _rtw_memcpy(bssid->PhyInfo.rm_en_cap, (p + 2), *(p + 1)); + + /* save freerun counter */ + bssid->PhyInfo.free_cnt = precv_frame->u.hdr.attrib.free_cnt; +#endif return _SUCCESS; } @@ -11057,6 +11540,7 @@ void start_create_ibss(_adapter *padapter) rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); join_type = 0; rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED); report_join_res(padapter, 1); pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; @@ -11133,7 +11617,7 @@ void start_clnt_join(_adapter *padapter) if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE ) { - ie_offset = (scanned->network.Reserved[0] == 2 ? 0 : 12); + ie_offset = (scanned->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); if (rtw_get_p2p_ie(scanned->network.IEs + ie_offset, scanned->network.IELength - ie_offset, NULL, NULL)) has_p2p_ie = _TRUE; break; @@ -11157,23 +11641,8 @@ void start_clnt_join(_adapter *padapter) (REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO * REASSOC_LIMIT) + beacon_timeout); #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - if (rtw_chk_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED)) { - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - ft_priv *pftpriv = &pmlmepriv->ftpriv; - - pmlmeinfo->state = WIFI_FW_AUTH_SUCCESS | WIFI_FW_STATION_STATE; - pftpriv->ft_event.ies = pftpriv->ft_action + sizeof(struct rtw_ieee80211_hdr_3addr) + 16; - pftpriv->ft_event.ies_len = pftpriv->ft_action_len - sizeof(struct rtw_ieee80211_hdr_3addr); - - /*Not support RIC*/ - pftpriv->ft_event.ric_ies = NULL; - pftpriv->ft_event.ric_ies_len = 0; - report_ft_event(padapter); - } else { - pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; - start_clnt_auth(padapter); - } + if (rtw_ft_roam(padapter)) { + rtw_ft_start_clnt_join(padapter); } else #endif { @@ -11182,6 +11651,7 @@ void start_clnt_join(_adapter *padapter) } } else if (caps & cap_IBSS) { /* adhoc client */ Set_MSR(padapter, WIFI_FW_ADHOC_STATE); + rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED); val8 = 0xcf; rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); @@ -11215,8 +11685,8 @@ void start_clnt_auth(_adapter *padapter) pmlmeext->retry = 0; #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - rtw_set_ft_status(padapter, RTW_FT_AUTHENTICATING_STA); + if (rtw_ft_roam(padapter)) { + rtw_ft_set_status(padapter, RTW_FT_AUTHENTICATING_STA); RTW_PRINT("start ft auth\n"); } else #endif @@ -11239,7 +11709,7 @@ void start_clnt_assoc(_adapter *padapter) pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE); #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) + if (rtw_ft_roam(padapter)) issue_reassocreq(padapter); else #endif @@ -11258,6 +11728,9 @@ unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsi RTW_INFO("%s\n", __FUNCTION__); +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_do_disconnect(padapter); +#endif if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { if (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL) @@ -11268,8 +11741,10 @@ unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsi } else RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(padapter)); #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && !rtw_chk_ft_status(padapter, RTW_FT_REQUESTED_STA)) - rtw_reset_ft_status(padapter); + rtw_ft_roam_status_reset(padapter); +#endif +#ifdef CONFIG_RTW_WNM + rtw_wnm_reset_btm_state(padapter); #endif } @@ -11296,7 +11771,7 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) u8 *ie, *p; u32 len; RT_CHANNEL_PLAN chplan_ap; - RT_CHANNEL_INFO chplan_sta[MAX_CHANNEL_NUM]; + RT_CHANNEL_INFO *chplan_sta = NULL; u8 country[4]; u8 fcn; /* first channel number */ u8 noc; /* number of channel */ @@ -11344,7 +11819,11 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) _RTW_INFO("}\n"); #endif - _rtw_memcpy(chplan_sta, rfctl->channel_set, sizeof(chplan_sta)); + chplan_sta = rtw_malloc(sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); + if (!chplan_sta) + goto done_update_chplan_from_ap; + + _rtw_memcpy(chplan_sta, rfctl->channel_set, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); #ifdef CONFIG_RTW_DEBUG i = 0; RTW_INFO("%s: STA channel plan {", __FUNCTION__); @@ -11516,26 +11995,10 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) k++; } #endif - } - - /* If channel is used by AP, set channel scan type to active */ - channel = bssid->Configuration.DSConfig; - chplan_new = rfctl->channel_set; - i = 0; - while (i < MAX_CHANNEL_NUM && chplan_new[i].ChannelNum != 0) { - if (chplan_new[i].ChannelNum == channel) { - if (chplan_new[i].ScanType == SCAN_PASSIVE) { - /* 5G Bnad 2, 3 (DFS) doesn't change to active scan */ - if (rtw_is_dfs_ch(channel)) - break; - chplan_new[i].ScanType = SCAN_ACTIVE; - RTW_INFO("%s: change channel %d scan type from passive to active\n", - __FUNCTION__, channel); - } - break; - } - i++; +done_update_chplan_from_ap: + if (chplan_sta) + rtw_mfree(chplan_sta, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); } } #endif @@ -11604,14 +12067,22 @@ void report_survey_event(_adapter *padapter, union recv_frame *precv_frame) process_80211d(padapter, &psurvey_evt->bss); #endif -#ifdef CONFIG_DFS ch_set_idx = rtw_chset_search_ch(chset, psurvey_evt->bss.Configuration.DSConfig); if (ch_set_idx >= 0) { - if (psurvey_evt->bss.Ssid.SsidLength == 0 - || is_all_null(psurvey_evt->bss.Ssid.Ssid, psurvey_evt->bss.Ssid.SsidLength) == _TRUE) - chset[ch_set_idx].hidden_bss_cnt++; + if (psurvey_evt->bss.InfrastructureMode == Ndis802_11Infrastructure) { + if (chset[ch_set_idx].ScanType == SCAN_PASSIVE + && !rtw_is_dfs_ch(psurvey_evt->bss.Configuration.DSConfig) + ) { + RTW_INFO("%s: change ch:%d to active\n", __func__, psurvey_evt->bss.Configuration.DSConfig); + chset[ch_set_idx].ScanType = SCAN_ACTIVE; + } + #ifdef CONFIG_DFS + if (psurvey_evt->bss.Ssid.SsidLength == 0 + || is_all_null(psurvey_evt->bss.Ssid.Ssid, psurvey_evt->bss.Ssid.SsidLength) == _TRUE) + chset[ch_set_idx].hidden_bss_cnt++; + #endif + } } -#endif rtw_enqueue_cmd(pcmdpriv, pcmd_obj); @@ -11796,7 +12267,7 @@ u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned sh _rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2); psta = rtw_get_stainfo(&padapter->stapriv, MacAddr); if (psta) - mac_id = (int)psta->mac_id; + mac_id = (int)psta->cmn.mac_id; else mac_id = (-1); pdel_sta_evt->mac_id = mac_id; @@ -11932,9 +12403,9 @@ bool rtw_port_switch_chk(_adapter *adapter) } #endif /* CONFIG_WOWLAN */ - /* AP should use port0 for ctl frame's ack */ + /* AP/Mesh should use port0 for ctl frame's ack */ if ((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { - RTW_INFO("%s "ADPT_FMT" is AP/GO\n", __func__, ADPT_ARG(if_port1)); + RTW_INFO("%s "ADPT_FMT" is AP/GO/Mesh\n", __func__, ADPT_ARG(if_port1)); switch_needed = _TRUE; goto exit; } @@ -12010,6 +12481,10 @@ void update_sta_info(_adapter *padapter, struct sta_info *psta) psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap; _rtw_memcpy(&psta->htpriv.ht_cap, &pmlmeinfo->HT_caps, sizeof(struct rtw_ieee80211_ht_cap)); + #ifdef CONFIG_BEAMFORMING + psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap; + psta->cmn.bf_info.ht_beamform_cap = pmlmepriv->htpriv.beamform_cap; + #endif } else #endif /* CONFIG_80211N_HT */ { @@ -12031,7 +12506,7 @@ void update_sta_info(_adapter *padapter, struct sta_info *psta) psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ #endif /* CONFIG_80211N_HT */ - psta->bw_mode = pmlmeext->cur_bwmode; + psta->cmn.bw_mode = pmlmeext->cur_bwmode; /* QoS */ if (pmlmepriv->qospriv.qos_option) @@ -12039,8 +12514,15 @@ void update_sta_info(_adapter *padapter, struct sta_info *psta) #ifdef CONFIG_80211AC_VHT _rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv)); + if (psta->vhtpriv.vht_option) { + psta->cmn.ra_info.is_vht_enable = _TRUE; + #ifdef CONFIG_BEAMFORMING + psta->vhtpriv.beamform_cap = pmlmepriv->vhtpriv.beamform_cap; + psta->cmn.bf_info.vht_beamform_cap = pmlmepriv->vhtpriv.beamform_cap; + #endif /*CONFIG_BEAMFORMING*/ + } #endif /* CONFIG_80211AC_VHT */ - + psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta)); update_ldpc_stbc_cap(psta); _enter_critical_bh(&psta->lock, &irqL); @@ -12055,9 +12537,25 @@ static void rtw_mlmeext_disconnect(_adapter *padapter) struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + u8 self_action = MLME_ACTION_UNKNOWN; u8 state_backup = (pmlmeinfo->state & 0x03); u8 ASIX_ID[] = {0x00, 0x0E, 0xC6}; + if (MLME_IS_AP(padapter)) + self_action = MLME_AP_STOPPED; + else if (MLME_IS_MESH(padapter)) + self_action = MLME_MESH_STOPPED; + else if (MLME_IS_STA(padapter)) + self_action = MLME_STA_DISCONNECTED; + else if (MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter)) + self_action = MLME_ADHOC_STOPPED; + else if (MLME_IS_NULL(padapter)) + self_action = MLME_ACTION_NONE; + else { + RTW_INFO("state:0x%x\n", MLME_STATE(padapter)); + rtw_warn_on(1); + } + /* set_opmode_cmd(padapter, infra_client_with_mlme); */ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0); @@ -12101,10 +12599,7 @@ static void rtw_mlmeext_disconnect(_adapter *padapter) #endif #ifdef CONFIG_DFS_MASTER - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) - rtw_dfs_master_status_apply(padapter, MLME_AP_STOPPED); - else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) - rtw_dfs_master_status_apply(padapter, MLME_STA_DISCONNECTED); + rtw_dfs_master_status_apply(padapter, self_action); #endif { @@ -12132,6 +12627,17 @@ static void rtw_mlmeext_disconnect(_adapter *padapter) padapter->tdlsinfo.ch_switch_prohibited = _FALSE; #endif /* CONFIG_TDLS */ +#ifdef CONFIG_WMMPS_STA + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + /* reset currently related uapsd setting when the connection has broken */ + pmlmepriv->qospriv.uapsd_max_sp_len = 0; + pmlmepriv->qospriv.uapsd_tid = 0; + pmlmepriv->qospriv.uapsd_tid_delivery_enabled = 0; + pmlmepriv->qospriv.uapsd_tid_trigger_enabled = 0; + pmlmepriv->qospriv.uapsd_ap_supported = 0; + } +#endif /* CONFIG_WMMPS_STA */ + } void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) @@ -12192,12 +12698,10 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); if (psta) { /* only for infra. mode */ - /* RTW_INFO("set_sta_rate\n"); */ - psta->wireless_mode = pmlmeext->cur_wireless_mode; #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - rtw_hal_set_default_port_id_cmd(padapter, psta->mac_id); + rtw_hal_set_default_port_id_cmd(padapter, psta->cmn.mac_id); #endif /* set per sta rate after updating HT cap. */ @@ -12207,7 +12711,7 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) /* wakeup macid after join bss successfully to ensure the subsequent data frames can be sent out normally */ - rtw_hal_macid_wakeup(padapter, psta->mac_id); + rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id); } #ifndef CONFIG_IOCTL_CFG80211 @@ -12243,7 +12747,9 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) exit_mlmeext_joinbss_event_callback: rtw_join_done_chk_ch(padapter, join_res); - +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_join_done(padapter); +#endif RTW_INFO("=>%s - End to Connection without 4-way\n", __FUNCTION__); } @@ -12280,11 +12786,11 @@ void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta) /* update adhoc sta_info */ update_sta_info(padapter, psta); - rtw_hal_update_sta_rate_mask(padapter, psta); + rtw_hal_update_sta_ra_info(padapter, psta); /* ToDo: HT for Ad-hoc */ psta->wireless_mode = rtw_check_network_type(psta->bssrateset, psta->bssratelen, pmlmeext->cur_channel); - psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); /* rate radaptive */ Update_RA_Entry(padapter, psta); @@ -12307,50 +12813,10 @@ Following are the functions for the timer handlers *****************************************************************************/ void _linked_info_dump(_adapter *padapter) { - int i; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - HAL_DATA_TYPE *HalData = GET_HAL_DATA(padapter); - int undecorated_smoothed_pwdb = 0; - if (padapter->bLinkInfoDump) { - - RTW_INFO("\n============["ADPT_FMT"] linked status check ===================\n", ADPT_ARG(padapter)); - - if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { - rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &undecorated_smoothed_pwdb); - - RTW_INFO("AP[" MAC_FMT "] - undecorated_smoothed_pwdb:%d\n", - MAC_ARG(padapter->mlmepriv.cur_network.network.MacAddress), undecorated_smoothed_pwdb); - } else if ((pmlmeinfo->state & 0x03) == _HW_STATE_AP_) { - _irqL irqL; - _list *phead, *plist; - - struct sta_info *psta = NULL; - struct sta_priv *pstapriv = &padapter->stapriv; - - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); - phead = &pstapriv->asoc_list; - plist = get_next(phead); - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); - plist = get_next(plist); - - RTW_INFO("STA[" MAC_FMT "]:undecorated_smoothed_pwdb:%d\n", - MAC_ARG(psta->hwaddr), psta->rssi_stat.undecorated_smoothed_pwdb); - } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - - } - - /*============ tx info ============ */ rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, RTW_DBGDUMP); - rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, RTW_DBGDUMP, _FALSE); - } - - } /******************************************************************** @@ -12380,9 +12846,9 @@ void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer) if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) { /* send a DELBA frame to the peer STA with the Reason Code field set to TIMEOUT */ if (!from_timer) - ret = issue_del_ba_ex(padapter, psta->hwaddr, i, 39, 0, 3, 1); + ret = issue_del_ba_ex(padapter, psta->cmn.mac_addr, i, 39, 0, 3, 1); else - issue_del_ba(padapter, psta->hwaddr, i, 39, 0); + issue_del_ba(padapter, psta->cmn.mac_addr, i, 39, 0); psta->recvreorder_ctrl[i].enable = _FALSE; if (ret != _FAIL) psta->recvreorder_ctrl[i].ampdu_size = RX_AMPDU_SIZE_INVALID; @@ -12399,7 +12865,6 @@ void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer) u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta) { u8 ret = _FALSE; - int i = 0; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -12419,7 +12884,7 @@ u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta) ); RTW_INFO(FUNC_ADPT_FMT" tx_pkts:%llu, link_count:%u\n", FUNC_ADPT_ARG(padapter) - , padapter->xmitpriv.tx_pkts + , sta_tx_pkts(psta) , pmlmeinfo->link_count ); #endif @@ -12434,12 +12899,6 @@ u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta) sta_update_last_rx_pkts(psta); - /* - record last rx data packets for every tid. - */ - for (i = 0; i < TID_NUM; i++) - psta->sta_stats.last_rx_data_qos_pkts[i] = psta->sta_stats.rx_data_qos_pkts[i]; - return ret; } @@ -12451,8 +12910,8 @@ u8 chk_adhoc_peer_is_alive(struct sta_info *psta) RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu" /*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/ ", expire_to:%u\n" - , MAC_ARG(psta->hwaddr) - , psta->rssi_stat.undecorated_smoothed_pwdb + , MAC_ARG(psta->cmn.mac_addr) + , psta->cmn.rssi_stat.rssi , STA_RX_PKTS_DIFF_ARG(psta) , psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts , psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts @@ -12523,11 +12982,11 @@ void linked_status_chk_tdls(_adapter *padapter) if (psta->alive_count >= ALIVE_MIN) { if (chk_tdls_peer_sta_is_alive(padapter, psta) == _FALSE) { if (psta->alive_count < ALIVE_MAX) { - _rtw_memcpy(checkalive[num_checkalive].addr, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(checkalive[num_checkalive].addr, psta->cmn.mac_addr, ETH_ALEN); checkalive[num_checkalive].psta = psta; num_checkalive++; } else { - _rtw_memcpy(teardown[num_teardown].addr, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(teardown[num_teardown].addr, psta->cmn.mac_addr, ETH_ALEN); teardown[num_teardown].psta = psta; num_teardown++; } @@ -12597,15 +13056,19 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) int rx_chk_limit; int link_count_limit; -#ifdef CONFIG_LAYER2_ROAMING +#if defined(CONFIG_RTW_REPEATER_SON) + rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_PROCESS); +#elif defined(CONFIG_LAYER2_ROAMING) if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) { RTW_INFO("signal_strength_data.avg_val = %d\n", precvpriv->signal_strength_data.avg_val); if (precvpriv->signal_strength_data.avg_val < pmlmepriv->roam_rssi_threshold) { +#ifdef CONFIG_RTW_80211K + rtw_roam_nb_discover(padapter, _FALSE); +#endif pmlmepriv->need_to_roam = _TRUE; rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM); - } else { + } else pmlmepriv->need_to_roam = _FALSE; - } } #endif #ifdef CONFIG_MCC_MODE @@ -12618,7 +13081,7 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) return; #endif -#if defined(DBG_ROAMING_TEST) +#if defined(DBG_ROAMING_TEST) || defined(CONFIG_RTW_REPEATER_SON) rx_chk_limit = 1; #elif defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER) rx_chk_limit = 4; @@ -12677,44 +13140,50 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) if (chk_ap_is_alive(padapter, psta) == _FALSE) rx_chk = _FAIL; - if (pxmitpriv->last_tx_pkts == pxmitpriv->tx_pkts) + if (sta_last_tx_pkts(psta) == sta_tx_pkts(psta)) tx_chk = _FAIL; #if defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER) if (pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL) - #ifdef CONFIG_MCC_MODE - /* Driver don't know operation channel under MCC*/ - /* So driver don't do KEEP_ALIVE_CHECK */ - && (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) - #endif ) { u8 backup_ch = 0, backup_bw = 0, backup_offset = 0; - u8 union_ch = 0, union_bw, union_offset; - - if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) - || pmlmeext->cur_channel != union_ch) - goto bypass_active_keep_alive; - - /* switch to correct channel of current network before issue keep-alive frames */ - if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { - backup_ch = rtw_get_oper_ch(padapter); - backup_bw = rtw_get_oper_bw(padapter); - backup_offset = rtw_get_oper_choffset(padapter); - set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + u8 union_ch = 0, union_bw = 0, union_offset = 0; + u8 switch_channel_by_drv = _TRUE; + + +#ifdef CONFIG_MCC_MODE + if (MCC_EN(padapter)) { + /* driver doesn't switch channel under MCC */ + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + switch_channel_by_drv = _FALSE; + } +#endif + if (switch_channel_by_drv) { + if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) + || pmlmeext->cur_channel != union_ch) + goto bypass_active_keep_alive; + + /* switch to correct channel of current network before issue keep-alive frames */ + if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { + backup_ch = rtw_get_oper_ch(padapter); + backup_bw = rtw_get_oper_bw(padapter); + backup_offset = rtw_get_oper_choffset(padapter); + set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + } } if (rx_chk != _SUCCESS) - issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->hwaddr, 0, 0, 3, 1); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->cmn.mac_addr, 0, 0, 3, 1); if ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) || rx_chk != _SUCCESS) { - tx_chk = issue_nulldata(padapter, psta->hwaddr, 0, 3, 1); + tx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 0, 3, 1); /* if tx acked and p2p disabled, set rx_chk _SUCCESS to reset retry count */ if (tx_chk == _SUCCESS && !is_p2p_enable) rx_chk = _SUCCESS; } /* back to the original operation channel */ - if (backup_ch > 0) + if (backup_ch > 0 && switch_channel_by_drv) set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw); bypass_active_keep_alive: @@ -12727,9 +13196,9 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) #ifdef DBG_EXPIRATION_CHK RTW_INFO("issue_probereq to trigger probersp, retry=%d\n", pmlmeext->retry); #endif - issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0); - issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0); - issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1)); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1)); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1)); } } @@ -12738,11 +13207,14 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) /* FW tx nulldata under MCC mode, we just check ap is alive */ && (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) #endif /* CONFIG_MCC_MODE */ - ) { -#ifdef DBG_EXPIRATION_CHK + ) { + #ifdef DBG_EXPIRATION_CHK RTW_INFO("%s issue_nulldata(%d)\n", __FUNCTION__, from_timer ? 1 : 0); -#endif - tx_chk = issue_nulldata_in_interrupt(padapter, NULL, from_timer ? 1 : 0); + #endif + if (from_timer) + tx_chk = issue_nulldata(padapter, NULL, 1, 0, 0); + else + tx_chk = issue_nulldata(padapter, NULL, 0, 1, 1); } } @@ -12761,7 +13233,7 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) if (tx_chk == _FAIL) pmlmeinfo->link_count %= (link_count_limit + 1); else { - pxmitpriv->last_tx_pkts = pxmitpriv->tx_pkts; + psta->sta_stats.last_tx_pkts = psta->sta_stats.tx_pkts; pmlmeinfo->link_count = 0; } @@ -12783,7 +13255,7 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); plist = get_next(plist); - if (is_broadcast_mac_addr(psta->hwaddr)) + if (is_broadcast_mac_addr(psta->cmn.mac_addr)) continue; if (chk_adhoc_peer_is_alive(psta) || !psta->expire_to) @@ -12806,8 +13278,8 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) plist = get_next(plist); rtw_list_delete(&psta->list); RTW_INFO(FUNC_ADPT_FMT" ibss expire "MAC_FMT"\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->hwaddr)); - report_del_sta_event(padapter, psta->hwaddr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE); + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + report_del_sta_event(padapter, psta->cmn.mac_addr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE); } } @@ -12846,6 +13318,17 @@ void survey_timer_hdl(void *ctx) return; } +#ifdef CONFIG_RTW_REPEATER_SON +/* 100ms pass, stop rson_scan */ +void rson_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + + rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_DISABLE); +} + +#endif + void link_timer_hdl(void *ctx) { _adapter *padapter = (_adapter *)ctx; @@ -12864,6 +13347,13 @@ void link_timer_hdl(void *ctx) if (rtw_sta_linking_test_force_fail()) RTW_INFO("rtw_sta_linking_test_force_fail\n"); + if (pmlmeext->join_abort && pmlmeinfo->state != WIFI_FW_NULL_STATE) { + RTW_INFO(FUNC_ADPT_FMT" join abort\n", FUNC_ADPT_ARG(padapter)); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + report_join_res(padapter, -4); + goto exit; + } + if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) { RTW_INFO("link_timer_hdl:no beacon while connecting\n"); pmlmeinfo->state = WIFI_FW_NULL_STATE; @@ -12893,7 +13383,7 @@ void link_timer_hdl(void *ctx) if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) { pmlmeinfo->state = WIFI_FW_NULL_STATE; #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + if (rtw_ft_roam(padapter)) { psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); if (psta) rtw_free_stainfo(padapter, psta); @@ -12904,7 +13394,7 @@ void link_timer_hdl(void *ctx) } #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + if (rtw_ft_roam(padapter)) { RTW_INFO("link_timer_hdl: reassoc timeout and try again\n"); issue_reassocreq(padapter); } else @@ -12917,6 +13407,7 @@ void link_timer_hdl(void *ctx) set_link_timer(pmlmeext, REASSOC_TO); } +exit: return; } @@ -12985,7 +13476,7 @@ void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short re psta = rtw_get_stainfo(&padapter->stapriv, MacAddr); if (psta) - mac_id = (int)psta->mac_id; + mac_id = (int)psta->cmn.mac_id; else mac_id = (-1); @@ -13000,12 +13491,11 @@ void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short re void clnt_sa_query_timeout(_adapter *padapter) { + struct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); - rtw_disassoc_cmd(padapter, 0, 0); - rtw_indicate_disconnect(padapter, 0, _FALSE); - rtw_free_assoc_resources(padapter, 1); - - RTW_INFO("SA query timeout client disconnect\n"); + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + receive_disconnect(padapter, get_my_bssid(&(mlmeinfo->network)), WLAN_REASON_SA_QUERY_TIMEOUT, _FALSE); } void sa_query_timer_hdl(void *ctx) @@ -13020,90 +13510,270 @@ void sa_query_timer_hdl(void *ctx) check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) clnt_sa_query_timeout(padapter); else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) - report_sta_timeout_event(padapter, psta->hwaddr, WLAN_REASON_PREV_AUTH_NOT_VALID); + report_sta_timeout_event(padapter, psta->cmn.mac_addr, WLAN_REASON_PREV_AUTH_NOT_VALID); } #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_RTW_80211R -void start_clnt_ft_action(_adapter *padapter, u8 *pTargetAddr) +void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame) { - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + WLAN_BSSID_EX *pbss; - rtw_set_ft_status(padapter, RTW_FT_REQUESTING_STA); - issue_action_ft_request(padapter, pTargetAddr); - _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO); -} + if (rtw_ft_chk_status(padapter,RTW_FT_ASSOCIATED_STA) + && (pmlmepriv->ft_roam.ft_updated_bcn == _FALSE)) { + pbss = (WLAN_BSSID_EX*)rtw_malloc(sizeof(WLAN_BSSID_EX)); + if (pbss) { + if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) { + struct beacon_keys recv_beacon; + + update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE); + rtw_get_bcn_info(&(pmlmepriv->cur_network)); + + /* update bcn keys */ + if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) { + RTW_INFO("%s: beacon keys ready\n", __func__); + _rtw_memcpy(&pmlmepriv->cur_beacon_keys, + &recv_beacon, sizeof(recv_beacon)); + pmlmepriv->new_beacon_cnts = 0; + } else { + RTW_ERR("%s: get beacon keys failed\n", __func__); + _rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon)); + pmlmepriv->new_beacon_cnts = 0; + } + } + rtw_mfree((u8*)pbss, sizeof(WLAN_BSSID_EX)); + } -void ft_link_timer_hdl(void *ctx) -{ - _adapter *padapter = (_adapter *)ctx; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - ft_priv *pftpriv = &pmlmepriv->ftpriv; + /* check the vendor of the assoc AP */ + pmlmeinfo->assoc_AP_vendor = + check_assoc_AP(pframe+sizeof(struct rtw_ieee80211_hdr_3addr), + (len - sizeof(struct rtw_ieee80211_hdr_3addr))); - if (rtw_chk_ft_status(padapter, RTW_FT_REQUESTING_STA)) { - if (pftpriv->ft_req_retry_cnt < FT_ACTION_REQ_LIMIT) { - pftpriv->ft_req_retry_cnt++; - issue_action_ft_request(padapter, (u8 *)pmlmepriv->roam_network->network.MacAddress); - _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO); - } else { - pftpriv->ft_req_retry_cnt = 0; + /* update TSF Value */ + update_TSF(pmlmeext, pframe, len); - if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) - rtw_set_ft_status(padapter, RTW_FT_ASSOCIATED_STA); - else - rtw_reset_ft_status(padapter); - } + /* reset for adaptive_early_32k */ + pmlmeext->adaptive_tsf_done = _FALSE; + pmlmeext->DrvBcnEarly = 0xff; + pmlmeext->DrvBcnTimeOut = 0xff; + pmlmeext->bcn_cnt = 0; + _rtw_memset(pmlmeext->bcn_delay_cnt, 0, sizeof(pmlmeext->bcn_delay_cnt)); + _rtw_memset(pmlmeext->bcn_delay_ratio, 0, sizeof(pmlmeext->bcn_delay_ratio)); + + pmlmepriv->ft_roam.ft_updated_bcn = _TRUE; } } -void ft_roam_timer_hdl(void *ctx) +void rtw_ft_start_clnt_join(_adapter *padapter) { - _adapter *padapter = (_adapter *)ctx; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam); + + if (rtw_ft_otd_roam(padapter)) { + pmlmeinfo->state = WIFI_FW_AUTH_SUCCESS | WIFI_FW_STATION_STATE; + pft_roam->ft_event.ies = + (pft_roam->ft_action + sizeof(struct rtw_ieee80211_hdr_3addr) + 16); + pft_roam->ft_event.ies_len = + (pft_roam->ft_action_len - sizeof(struct rtw_ieee80211_hdr_3addr)); + + /*Not support RIC*/ + pft_roam->ft_event.ric_ies = NULL; + pft_roam->ft_event.ric_ies_len = 0; + rtw_ft_report_evt(padapter); + return; + } - receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress - , WLAN_REASON_ACTIVE_ROAM, _FALSE); + pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; + start_clnt_auth(padapter); } -void issue_action_ft_request(_adapter *padapter, u8 *pTargetAddr) +u8 rtw_ft_update_rsnie( + _adapter *padapter, u8 bwrite, + struct pkt_attrib *pattrib, u8 **pframe) { - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct xmit_frame *pmgntframe = NULL; - struct rtw_ieee80211_hdr *pwlanhdr = NULL; - struct pkt_attrib *pattrib = NULL; - ft_priv *pftpriv = NULL; - u8 *pframe = NULL; - u8 category = RTW_WLAN_CATEGORY_FT; - u8 action = RTW_WLAN_ACTION_FT_REQUEST; - u8 is_ft_roaming_with_rsn_ie = _TRUE; - u8 *pie = NULL; - u16 *fctrl = NULL; - u32 ft_ie_len = 0; + struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); + u8 *pie; + u32 len; - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - return; + pie = rtw_get_ie(pft_roam->updated_ft_ies, EID_WPA2, &len, + pft_roam->updated_ft_ies_len); - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + if (!bwrite) + return (pie)?_SUCCESS:_FAIL; + + if (pie) { + *pframe = rtw_set_ie(((u8 *)*pframe), EID_WPA2, len, + pie+2, &(pattrib->pktlen)); + } else + return _FAIL; - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + return _SUCCESS; +} - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; +static u8 rtw_ft_update_mdie( + _adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe) +{ + struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); + u8 *pie, mdie[3]; + u32 len = 3; + + if (rtw_ft_roam(padapter)) { + if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _MDIE_, + &len, pft_roam->updated_ft_ies_len))) { + pie = (pie + 2); /* ignore md-id & length */ + } else + return _FAIL; + } else { + *((u16 *)&mdie[0]) = pft_roam->mdid; + mdie[2] = pft_roam->ft_cap; + pie = &mdie[0]; + } - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + *pframe = rtw_set_ie(((u8 *)*pframe), _MDIE_, len , pie, &(pattrib->pktlen)); + return _SUCCESS; +} + +static u8 rtw_ft_update_ftie( + _adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe) +{ + struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); + u8 *pie; + u32 len; + + if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _FTIE_, &len, + pft_roam->updated_ft_ies_len)) != NULL) { + *pframe = rtw_set_ie(*pframe, _FTIE_, len , + (pie+2), &(pattrib->pktlen)); + } else + return _FAIL; + + return _SUCCESS; +} + +void rtw_ft_build_auth_req_ies(_adapter *padapter, + struct pkt_attrib *pattrib, u8 **pframe) +{ + u8 ftie_append = _TRUE; + + if (!pattrib || !(*pframe)) + return; + + if (!rtw_ft_roam(padapter)) + return; + + ftie_append = rtw_ft_update_rsnie(padapter, _TRUE, pattrib, pframe); + rtw_ft_update_mdie(padapter, pattrib, pframe); + if (ftie_append) + rtw_ft_update_ftie(padapter, pattrib, pframe); +} + +void rtw_ft_build_assoc_req_ies(_adapter *padapter, + u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe) +{ + if (!pattrib || !(*pframe)) + return; + + if (rtw_ft_chk_flags(padapter, RTW_FT_PEER_EN)) + rtw_ft_update_mdie(padapter, pattrib, pframe); + + if ((!is_reassoc) || (!rtw_ft_roam(padapter))) + return; + + if (rtw_ft_update_rsnie(padapter, _FALSE, pattrib, pframe)) + rtw_ft_update_ftie(padapter, pattrib, pframe); +} + +u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len) +{ + u8 ret = _SUCCESS; + u8 target_ap_addr[ETH_ALEN] = {0}; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam); + + if (!rtw_ft_roam(padapter)) + return _FAIL; + + /*rtw_ft_report_reassoc_evt already, + * and waiting for cfg80211_rtw_update_ft_ies */ + if (rtw_ft_authed_sta(padapter)) + return ret; + + if (!pframe || !len) + return _FAIL; + + rtw_buf_update(&pmlmepriv->auth_rsp, + &pmlmepriv->auth_rsp_len, pframe, len); + pft_roam->ft_event.ies = + (pmlmepriv->auth_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6); + pft_roam->ft_event.ies_len = + (pmlmepriv->auth_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6); + + /*Not support RIC*/ + pft_roam->ft_event.ric_ies = NULL; + pft_roam->ft_event.ric_ies_len = 0; + _rtw_memcpy(target_ap_addr, pmlmepriv->assoc_bssid, ETH_ALEN); + rtw_ft_report_reassoc_evt(padapter, target_ap_addr); + + return ret; +} + +static void rtw_ft_start_clnt_action(_adapter *padapter, u8 *pTargetAddr) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + rtw_ft_set_status(padapter, RTW_FT_REQUESTING_STA); + rtw_ft_issue_action_req(padapter, pTargetAddr); + _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO); +} + +void rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (rtw_ft_otd_roam(padapter)) { + rtw_ft_start_clnt_action(padapter, pTargetAddr); + } else { + /*wait a little time to retrieve packets buffered in the current ap while scan*/ + _set_timer(&pmlmeext->ft_roam_timer, 30); + } +} + +void rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct xmit_frame *pmgntframe; + struct rtw_ieee80211_hdr *pwlanhdr; + struct pkt_attrib *pattrib; + u8 *pframe; + u8 category = RTW_WLAN_CATEGORY_FT; + u8 action = RTW_WLAN_ACTION_FT_REQ; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + pwlanhdr->frame_ctl = 0; + + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; @@ -13123,45 +13793,34 @@ void issue_action_ft_request(_adapter *padapter, u8 *pTargetAddr) pframe += ETH_ALEN; pattrib->pktlen += ETH_ALEN; - pftpriv = &pmlmepriv->ftpriv; - pie = rtw_get_ie(pftpriv->updated_ft_ies, EID_WPA2, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie) - pframe = rtw_set_ie(pframe, EID_WPA2, ft_ie_len, pie+2, &(pattrib->pktlen)); - else - is_ft_roaming_with_rsn_ie = _FALSE; - - pie = rtw_get_ie(pftpriv->updated_ft_ies, _MDIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie) - pframe = rtw_set_ie(pframe, _MDIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); - - pie = rtw_get_ie(pftpriv->updated_ft_ies, _FTIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie && is_ft_roaming_with_rsn_ie) - pframe = rtw_set_ie(pframe, _FTIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); + rtw_ft_update_mdie(padapter, pattrib, &pframe); + if (rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe)) + rtw_ft_update_ftie(padapter, pattrib, &pframe); pattrib->last_txcmdsz = pattrib->pktlen; dump_mgntframe(padapter, pmgntframe); } -void report_ft_event(_adapter *padapter) +void rtw_ft_report_evt(_adapter *padapter) { - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - ft_priv *pftpriv = &pmlmepriv->ftpriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network); struct cfg80211_ft_event_params ft_evt_parms; _irqL irqL; _rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms)); - rtw_update_ft_stainfo(padapter, pnetwork); + rtw_ft_update_stainfo(padapter, pnetwork); if (!pnetwork) goto err_2; - ft_evt_parms.ies_len = pftpriv->ft_event.ies_len; + ft_evt_parms.ies_len = pft_roam->ft_event.ies_len; ft_evt_parms.ies = rtw_zmalloc(ft_evt_parms.ies_len); if (ft_evt_parms.ies) - _rtw_memcpy((void *)ft_evt_parms.ies, pftpriv->ft_event.ies, ft_evt_parms.ies_len); + _rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len); else goto err_2; @@ -13171,31 +13830,28 @@ void report_ft_event(_adapter *padapter) else goto err_1; - ft_evt_parms.ric_ies = pftpriv->ft_event.ric_ies; - ft_evt_parms.ric_ies_len = pftpriv->ft_event.ric_ies_len; - - _enter_critical_bh(&pmlmepriv->lock, &irqL); - rtw_set_ft_status(padapter, RTW_FT_AUTHENTICATED_STA); - _exit_critical_bh(&pmlmepriv->lock, &irqL); + ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies; + ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len; + rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL); rtw_cfg80211_ft_event(padapter, &ft_evt_parms); - RTW_INFO("FT: report_ft_event\n"); - rtw_mfree((u8 *)pftpriv->ft_event.target_ap, ETH_ALEN); + RTW_INFO("FT: rtw_ft_report_evt\n"); + rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN); err_1: rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len); err_2: return; } -void report_ft_reassoc_event(_adapter *padapter, u8 *pMacAddr) +void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr) { - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - struct cmd_obj *pcmd_obj = NULL; - struct stassoc_event *passoc_sta_evt = NULL; - struct C2HEvent_Header *pc2h_evt_hdr = NULL; - u8 *pevtcmd = NULL; - u32 cmdsz = 0; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + struct cmd_obj *pcmd_obj = NULL; + struct stassoc_event *passoc_sta_evt = NULL; + struct C2HEvent_Header *pc2h_evt_hdr = NULL; + u8 *pevtcmd = NULL; + u32 cmdsz = 0; pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmd_obj == NULL) @@ -13224,6 +13880,50 @@ void report_ft_reassoc_event(_adapter *padapter, u8 *pMacAddr) _rtw_memcpy((unsigned char *)(&(passoc_sta_evt->macaddr)), pMacAddr, ETH_ALEN); rtw_enqueue_cmd(pcmdpriv, pcmd_obj); } + +void rtw_ft_link_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam); + + if (rtw_ft_chk_status(padapter, RTW_FT_REQUESTING_STA)) { + if (pft_roam->ft_req_retry_cnt < RTW_FT_ACTION_REQ_LMT) { + pft_roam->ft_req_retry_cnt++; + rtw_ft_issue_action_req(padapter, (u8 *)pmlmepriv->roam_network->network.MacAddress); + _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO); + } else { + pft_roam->ft_req_retry_cnt = 0; + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) + rtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA); + else + rtw_ft_reset_status(padapter); + } + } +} + +void rtw_ft_roam_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress + , WLAN_REASON_ACTIVE_ROAM, _FALSE); +} + +void rtw_ft_roam_status_reset(_adapter *padapter) +{ + struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); + + if ((rtw_to_roam(padapter) > 0) && + (!rtw_ft_chk_status(padapter, RTW_FT_REQUESTED_STA))) { + rtw_ft_reset_status(padapter); + } + + padapter->mlmepriv.ft_roam.ft_updated_bcn = _FALSE; +} #endif u8 NULL_hdl(_adapter *padapter, u8 *pbuf) @@ -13232,13 +13932,47 @@ u8 NULL_hdl(_adapter *padapter, u8 *pbuf) } #ifdef CONFIG_AUTO_AP_MODE +void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos) +{ + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_info *psta = precv_frame->u.hdr.psta; + struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos; + + RTW_INFO("eth rx: got eth_type=0x%x\n", ntohs(ehdr->h_proto)); + + if (psta && psta->isrc && psta->pid > 0) { + u16 rx_pid; + + rx_pid = *(u16 *)(ehdr_pos + ETH_HLEN); + + RTW_INFO("eth rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n", + rx_pid, MAC_ARG(psta->cmn.mac_addr), psta->pid); + + if (rx_pid == psta->pid) { + int i; + u16 len = *(u16 *)(ehdr_pos + ETH_HLEN + 2); + /* u16 ctrl_type = *(u16 *)(ehdr_pos + ETH_HLEN + 4); */ + + /* RTW_INFO("eth, RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type); */ + RTW_INFO("eth, RC: len=0x%x\n", len); + + for (i = 0; i < len; i++) + RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 4 + i)); + /* RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 6 + i)); */ + + RTW_INFO("eth, RC-end\n"); + } + } + +} + void rtw_start_auto_ap(_adapter *adapter) { RTW_INFO("%s\n", __FUNCTION__); rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11APMode); - rtw_setopmode_cmd(adapter, Ndis802_11APMode, _TRUE); + rtw_setopmode_cmd(adapter, Ndis802_11APMode, RTW_CMDF_WAIT_ACK); } static int rtw_auto_ap_start_beacon(_adapter *adapter) @@ -13333,12 +14067,11 @@ u8 setopmode_hdl(_adapter *padapter, u8 *pbuf) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf; - if (psetop->mode == Ndis802_11APMode) { + if (psetop->mode == Ndis802_11APMode + || psetop->mode == Ndis802_11_mesh + ) { pmlmeinfo->state = WIFI_FW_AP_STATE; type = _HW_STATE_AP_; -#ifdef CONFIG_NATIVEAP_MLME - /* start_ap_mode(padapter); */ -#endif } else if (psetop->mode == Ndis802_11Infrastructure) { pmlmeinfo->state &= ~(BIT(0) | BIT(1)); /* clear state */ pmlmeinfo->state |= WIFI_FW_STATION_STATE;/* set to STATION_STATE */ @@ -13376,8 +14109,10 @@ u8 setopmode_hdl(_adapter *padapter, u8 *pbuf) } #ifdef CONFIG_BT_COEXIST - if (psetop->mode == Ndis802_11APMode || - psetop->mode == Ndis802_11Monitor) { + if (psetop->mode == Ndis802_11APMode + || psetop->mode == Ndis802_11_mesh + || psetop->mode == Ndis802_11Monitor + ) { /* Do this after port switch to */ /* prevent from downloading rsvd page to wrong port */ rtw_btcoex_MediaStatusNotify(padapter, 1); /* connect */ @@ -13559,7 +14294,7 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) } rtw_bss_get_chbw(pnetwork - , &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset); + , &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset, 1, 1); rtw_adjust_chbw(padapter, pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset); @@ -13608,6 +14343,8 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress); join_type = 0; rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + if (MLME_IS_STA(padapter)) + rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING); doiqk = _TRUE; rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); @@ -13826,6 +14563,44 @@ u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_nu return ret_num; } +#define SCANNING_TIMEOUT_EX 2000 +u32 rtw_scan_timeout_decision(_adapter *padapter) +{ + u32 back_op_times= 0; + u8 max_chan_num; + u16 scan_ms; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct ss_res *ss = &pmlmeext->sitesurvey_res; + + if (is_supported_5g(padapter->registrypriv.wireless_mode) + && IsSupported24G(padapter->registrypriv.wireless_mode)) + max_chan_num = MAX_CHANNEL_NUM;/* dual band */ + else + max_chan_num = MAX_CHANNEL_NUM_2G;/*single band*/ + + #ifdef CONFIG_SCAN_BACKOP + if (rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) + back_op_times = (max_chan_num / ss->scan_cnt_max) * ss->backop_ms; + #endif + + if (ss->duration) + scan_ms = ss->duration; + else + #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) + if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter)) + scan_ms = rtw_acs_get_adv_st(padapter); + else + #endif /*CONFIG_RTW_ACS*/ + scan_ms = ss->scan_ch_ms; + + ss->scan_timeout_ms = (scan_ms * max_chan_num) + back_op_times + SCANNING_TIMEOUT_EX; + #ifdef DBG_SITESURVEY + RTW_INFO("%s , scan_timeout_ms = %d (ms)\n", __func__, ss->scan_timeout_ms); + #endif /*DBG_SITESURVEY*/ + return ss->scan_timeout_ms; +} + static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out, u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num) { @@ -13921,7 +14696,6 @@ static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm #if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) ss->is_sw_antdiv_bl_scan = 0; #endif - ss->ssid_num = 0; for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { if (parm->ssid[i].SsidLength) { @@ -13942,7 +14716,12 @@ static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm chset[i].hidden_bss_cnt = 0; #endif + ss->bw = parm->bw; + ss->igi = parm->igi; + ss->token = parm->token; + ss->duration = parm->duration; ss->scan_mode = parm->scan_mode; + ss->token = parm->token; } static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *type) @@ -14002,7 +14781,13 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE * if (ss->channel_idx < ss->ch_num) { ch = &ss->ch[ss->channel_idx]; scan_ch = ch->hw_value; - scan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE; + + #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) + if (IS_ACS_ENABLE(padapter) && rtw_is_acs_passiv_scan(padapter)) + scan_type = SCAN_PASSIVE; + else + #endif /*CONFIG_RTW_ACS*/ + scan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE; } } @@ -14103,19 +14888,6 @@ void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType) if (survey_channel != 0) { set_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - if (ACS_ENABLE == GET_ACS_STATE(padapter)) { - ACS_OP acs_op = ACS_RESET; - - rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE); - rtw_set_acs_channel(padapter, survey_channel); -#ifdef DBG_AUTO_CHNL_SEL_NHM - RTW_INFO("[ACS-"ADPT_FMT"]-set ch:%u\n", - ADPT_ARG(padapter), rtw_get_acs_channel(padapter)); -#endif - } -#endif - #ifdef CONFIG_DFS if (ScanType == SCAN_PASSIVE && ss->dfs_ch_ssid_scan) ssid_scan = 1; @@ -14232,65 +15004,102 @@ void survey_done_set_ch_bw(_adapter *padapter) set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); } -#if 1 -/** - * sitesurvey_ps_annc - check and doing ps announcement for all the adapters of given @dvobj - * @padapter - * @ps: power saving or not - * - * Returns: 0: no ps announcement is doing. 1: ps announcement is doing - */ - -u8 sitesurvey_ps_annc(_adapter *padapter, bool ps) -{ - u8 ps_anc = 0; - - #ifdef CONFIG_AP_MODE - /*mac-id sleep or wake-up for AP mode*/ - rtw_mi_ap_acdata_control(padapter, ps); - #endif/*CONFIG_AP_MODE*/ - if (rtw_mi_issue_nulldata(padapter, NULL, ps, 3, 500)) - ps_anc = 1; - return ps_anc; -} -#else /** - * sitesurvey_ps_annc - check and doing ps announcement for all the adapters of given @dvobj - * @dvobj: the dvobj to check + * rtw_ps_annc - check and doing ps announcement for all the adapters + * @adapter: the requesting adapter * @ps: power saving or not * * Returns: 0: no ps announcement is doing. 1: ps announcement is doing */ - -u8 sitesurvey_ps_annc(struct dvobj_priv *dvobj, bool ps) +u8 rtw_ps_annc(_adapter *adapter, bool ps) { - _adapter *adapter; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; int i; u8 ps_anc = 0; for (i = 0; i < dvobj->iface_nums; i++) { - adapter = dvobj->padapters[i]; - if (!adapter) + iface = dvobj->padapters[i]; + if (!iface) continue; - if (ps) { - if (is_client_associated_to_ap(adapter) == _TRUE) { + if (MLME_IS_STA(iface)) { + if (is_client_associated_to_ap(iface) == _TRUE) { /* TODO: TDLS peers */ - issue_nulldata(adapter, NULL, 1, 3, 500); + #ifdef CONFIG_MCC_MODE + /* for two station case */ + if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_NEED_MCC)) { + u8 ch = iface->mlmeextpriv.cur_channel; + u8 offset = iface->mlmeextpriv.cur_ch_offset; + u8 bw = iface->mlmeextpriv.cur_bwmode; + + set_channel_bwmode(iface, ch, offset, bw); + } + #endif /* CONFIG_MCC_MODE */ + issue_nulldata(iface, NULL, ps, 3, 500); ps_anc = 1; } - } else { - if (is_client_associated_to_ap(adapter) == _TRUE) { - /* TODO: TDLS peers */ - issue_nulldata(adapter, NULL, 0, 3, 500); + #ifdef CONFIG_RTW_MESH + } else if (MLME_IS_MESH(iface)) { + if (rtw_mesh_ps_annc(iface, ps)) ps_anc = 1; - } + #endif } } return ps_anc; } + +void rtw_leave_opch(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + +#ifdef CONFIG_MCC_MODE + if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) + return; +#endif + + _enter_critical_mutex(&rfctl->offch_mutex, NULL); + + if (rfctl->offch_state == OFFCHS_NONE) { + /* prepare to leave operating channel */ + rfctl->offch_state = OFFCHS_LEAVING_OP; + + /* clear HW TX queue */ + rtw_hal_set_hwreg(adapter, HW_VAR_CHECK_TXBUF, 0); + + rtw_hal_macid_sleep_all_used(adapter); + + rtw_ps_annc(adapter, 1); + + rfctl->offch_state = OFFCHS_LEAVE_OP; + } + + _exit_critical_mutex(&rfctl->offch_mutex, NULL); +} + +void rtw_back_opch(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + +#ifdef CONFIG_MCC_MODE + if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) + return; #endif + _enter_critical_mutex(&rfctl->offch_mutex, NULL); + + if (rfctl->offch_state != OFFCHS_NONE) { + rfctl->offch_state = OFFCHS_BACKING_OP; + rtw_hal_macid_wakeup_all_used(adapter); + rtw_ps_annc(adapter, 0); + + rfctl->offch_state = OFFCHS_NONE; + rtw_mi_os_xmit_schedule(adapter); + } + + _exit_critical_mutex(&rfctl->offch_mutex, NULL); +} + void sitesurvey_set_igi(_adapter *adapter) { struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; @@ -14304,7 +15113,7 @@ void sitesurvey_set_igi(_adapter *adapter) case SCAN_ENTER: #ifdef CONFIG_P2P #ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(adapter)->p2p_enabled == _TRUE && pwdinfo->driver_interface == DRIVER_CFG80211) + if (pwdinfo->driver_interface == DRIVER_CFG80211 && rtw_cfg80211_is_p2p_scan(adapter)) igi = 0x30; else #endif /* CONFIG_IOCTL_CFG80211 */ @@ -14312,6 +15121,15 @@ void sitesurvey_set_igi(_adapter *adapter) igi = 0x28; else #endif /* CONFIG_P2P */ + + if (ss->igi) + igi = ss->igi; + else + #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) + if (IS_ACS_ENABLE(adapter) && rtw_is_acs_igi_valid(adapter)) + igi = rtw_acs_get_adv_igi(adapter); + else + #endif /*CONFIG_RTW_ACS*/ igi = 0x1e; /* record IGI status */ @@ -14330,11 +15148,11 @@ void sitesurvey_set_igi(_adapter *adapter) #ifdef CONFIG_SCAN_BACKOP case SCAN_BACKING_OP: /* write IGI for op channel when DIG is not enabled */ - odm_write_dig(GET_ODM(adapter), ss->igi_before_scan); + odm_write_dig(adapter_to_phydm(adapter), ss->igi_before_scan); break; case SCAN_LEAVE_OP: /* write IGI for scan when DIG is not enabled */ - odm_write_dig(GET_ODM(adapter), ss->igi_scan); + odm_write_dig(adapter_to_phydm(adapter), ss->igi_scan); break; #endif /* CONFIG_SCAN_BACKOP */ default: @@ -14363,6 +15181,37 @@ void sitesurvey_set_msr(_adapter *adapter, bool enter) } Set_MSR(adapter, network_type); } + +void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + _enter_critical_mutex(&rfctl->offch_mutex, NULL); + + switch (scan_state) { + case SCAN_DISABLE: + case SCAN_BACK_OP: + rfctl->offch_state = OFFCHS_NONE; + break; + case SCAN_START: + case SCAN_LEAVING_OP: + rfctl->offch_state = OFFCHS_LEAVING_OP; + break; + case SCAN_ENTER: + case SCAN_LEAVE_OP: + rfctl->offch_state = OFFCHS_LEAVE_OP; + break; + case SCAN_COMPLETE: + case SCAN_BACKING_OP: + rfctl->offch_state = OFFCHS_BACKING_OP; + break; + default: + break; + } + + _exit_critical_mutex(&rfctl->offch_mutex, NULL); +} + u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) { struct sitesurvey_parm *pparm = (struct sitesurvey_parm *)pbuf; @@ -14371,14 +15220,6 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct ss_res *ss = &pmlmeext->sitesurvey_res; -#ifdef CONFIG_CHNL_LOAD_MAGT - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *p_dm_odm = &pHalData->odmpriv; - u16 *channel_clm = pHalData->clm_result; - int clm_ch_index; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; - struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); -#endif u8 val8; #ifdef CONFIG_P2P @@ -14429,8 +15270,10 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) /* clear HW TX queue before scan */ rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); + rtw_hal_macid_sleep_all_used(padapter); + /* power save state announcement */ - if (sitesurvey_ps_annc(padapter, 1)) { + if (rtw_ps_annc(padapter, 1)) { mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT); mlmeext_set_scan_next_state(pmlmeext, SCAN_ENTER); set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */ @@ -14466,65 +15309,22 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) RT_SCAN_TYPE scan_type; u8 next_state; u32 scan_ms; -#ifdef CONFIG_CHNL_LOAD_MAGT - bool ret; -#endif - -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - if ((ACS_ENABLE == GET_ACS_STATE(padapter)) && (0 != rtw_get_acs_channel(padapter))) { - ACS_OP acs_op = ACS_SELECT; - rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE); - } +#ifdef CONFIG_RTW_ACS + if (IS_ACS_ENABLE(padapter)) + rtw_acs_get_rst(padapter); #endif next_state = sitesurvey_pick_ch_behavior(padapter, &scan_ch, &scan_type); -#ifdef CONFIG_CHNL_LOAD_MAGT - if (padapter->clm_flag == TRUE) { - - if ((next_state == SCAN_COMPLETE) || (ss->channel_idx != 0 && next_state == SCAN_PROCESS)) { - - ret = phydm_check_clm_ready(p_dm_odm); - /*RTW_INFO("DBG_CLM %s ; ss->ch = %u\n", __FUNCTION__,ss->ch[ss->channel_idx-1].hw_value);*/ - if (ret == true) { - ccx_info->echo_CLM_en = false; - phydm_get_clm_result(p_dm_odm); - clm_ch_index = rtw_chset_search_ch(rfctl->channel_set, ss->ch[ss->channel_idx-1].hw_value); - channel_clm[clm_ch_index] = 0; - channel_clm[clm_ch_index] = ccx_info->CLM_result; - RTW_INFO("DBG_CLM %s :clm_index = %d ; ch = %u;CLM_result = %d\n", __FUNCTION__, clm_ch_index, ss->ch[ss->channel_idx-1].hw_value, ccx_info->CLM_result); - } else - RTW_INFO("DBG_CLM %s : CLM is not ready\n", __FUNCTION__); -/* - RTW_INFO("DBG_CLM %s : ready = %d\n", __FUNCTION__, phydm_check_clm_ready(p_dm_odm)); - RTW_INFO("DBG_CLM %s : ODM_REG_CLM_11N reg 890= 0x%x\n", __FUNCTION__, rtw_read32(padapter, ODM_REG_CLM_11N)); - RTW_INFO("DBG_CLM %s : ODM_REG_CCX_PERIOD_11N reg 894= 0x%x\n", __FUNCTION__, rtw_read32(padapter, ODM_REG_CCX_PERIOD_11N)); - RTW_INFO("DBG_CLM %s : ODM_REG_CLM_READY_11N reg 8B4= 0x%x\n", __FUNCTION__, rtw_read32(padapter, ODM_REG_CLM_READY_11N)); - RTW_INFO("DBG_CLM %s : end_time =%d\n", __FUNCTION__, rtw_get_current_time()); - RTW_INFO("DBG_CLM %s : end_time =%d ms\n", __FUNCTION__, rtw_systime_to_ms(rtw_get_current_time())); -*/ - } - } -#endif - if (next_state != SCAN_PROCESS) { -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - if (ACS_ENABLE == GET_ACS_STATE(padapter)) { - rtw_set_acs_channel(padapter, 0); -#ifdef DBG_AUTO_CHNL_SEL_NHM - RTW_INFO("[ACS-"ADPT_FMT"]-set ch:%u\n", ADPT_ARG(padapter), rtw_get_acs_channel(padapter)); -#endif - } -#endif - mlmeext_set_scan_state(pmlmeext, next_state); goto operation_by_state; } /* still SCAN_PROCESS state */ - if (0) -#ifdef CONFIG_P2P + #ifdef DBG_SITESURVEY + #ifdef CONFIG_P2P RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c\n" , FUNC_ADPT_ARG(padapter) , mlmeext_scan_state_str(pmlmeext) @@ -14534,7 +15334,7 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) , scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P' , ss->ssid[0].SsidLength ? 'S' : ' ' ); -#else + #else RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (idx:%d) at %dms, %c%c%c\n" , FUNC_ADPT_ARG(padapter) , mlmeext_scan_state_str(pmlmeext) @@ -14544,8 +15344,8 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) , scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P' , ss->ssid[0].SsidLength ? 'S' : ' ' ); -#endif /* CONFIG_P2P */ - + #endif /* CONFIG_P2P */ + #endif /*DBG_SITESURVEY*/ #ifdef DBG_FIXED_CHAN if (pmlmeext->fixed_chan != 0xff) RTW_INFO(FUNC_ADPT_FMT" fixed_chan:%u\n", pmlmeext->fixed_chan); @@ -14559,7 +15359,12 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) else scan_ms = 40; #else - scan_ms = ss->scan_ch_ms; + #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) + if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter)) + scan_ms = rtw_acs_get_adv_st(padapter); + else + #endif /*CONFIG_RTW_ACS*/ + scan_ms = ss->scan_ch_ms; #endif #if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) @@ -14567,44 +15372,19 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) scan_ms = scan_ms / 2; #endif -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - { - struct noise_info info; - - info.bPauseDIG = _FALSE; - info.IGIValue = 0; - info.max_time = scan_ms / 2; - info.chan = scan_ch; - rtw_hal_set_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &info, _FALSE); +#ifdef CONFIG_RTW_ACS + if (IS_ACS_ENABLE(padapter)) { + if (pparm->token) + rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_IEEE_11K_HIGH); + else + rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_ACS); } #endif -#ifdef CONFIG_CHNL_LOAD_MAGT - - if (padapter->clm_flag == TRUE) { - - scan_ms = ss->scan_ch_ms; - /*beacause scan_ms 200ms ,clm only can test less than 195ms ,otherwise 0x8b4[16] will not be true;difference=5ms*/ - ccx_info->echo_CLM_en = TRUE; - - ccx_info->CLM_period = pHalData->clm_period; /*if CLM_period=0xC350; then 50000*4us=200ms*/ - phydm_clm_setting(p_dm_odm); - phydm_clm_trigger(p_dm_odm); -/* - RTW_INFO("DBG_CLM %s : scan_ms =%u clm_period = 0x%x\n",__FUNCTION__, scan_ms, ccx_info->CLM_period); - RTW_INFO("DBG_CLM %s : current_index = %d;cuurent_ch =%u\n",__FUNCTION__, ss->channel_idx,scan_ch); - RTW_INFO("DBG_CLM %s : start_time =%d\n",__FUNCTION__, rtw_get_current_time()); - RTW_INFO("DBG_CLM %s : start_time =%d ms\n",__FUNCTION__, rtw_systime_to_ms(rtw_get_current_time())); - RTW_INFO(FUNC_ADPT_FMT" %s ch=%u at %dms\n" - , FUNC_ADPT_ARG(padapter) - , mlmeext_scan_state_str(pmlmeext) - ,scan_ch - , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) - ); -*/ - } +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + if (IS_NM_ENABLE(padapter)) + rtw_noise_measure(padapter, scan_ch, _FALSE, 0, scan_ms / 2); #endif - set_survey_timer(pmlmeext, scan_ms); break; } @@ -14624,14 +15404,14 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) rtw_warn_on(1); } - if (0) + #ifdef DBG_SITESURVEY RTW_INFO(FUNC_ADPT_FMT" %s ch:%u, bw:%u, offset:%u at %dms\n" , FUNC_ADPT_ARG(padapter) , mlmeext_scan_state_str(pmlmeext) , back_ch, back_bw, back_ch_offset , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) ); - + #endif /*DBG_SITESURVEY*/ set_channel_bwmode(padapter, back_ch, back_ch_offset, back_bw); sitesurvey_set_msr(padapter, _FALSE); @@ -14641,7 +15421,8 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) { sitesurvey_set_igi(padapter); - sitesurvey_ps_annc(padapter, 0); + rtw_hal_macid_wakeup_all_used(padapter); + rtw_ps_annc(padapter, 0); } mlmeext_set_scan_state(pmlmeext, SCAN_BACK_OP); @@ -14666,15 +15447,16 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) case SCAN_LEAVING_OP: /* - * prepare to leave operating channel - */ + * prepare to leave operating channel + */ /* clear HW TX queue before scan */ rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); + rtw_hal_macid_sleep_all_used(padapter); if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC) - && sitesurvey_ps_annc(padapter, 1) - ) { + && rtw_ps_annc(padapter, 1) + ) { mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT); mlmeext_set_scan_next_state(pmlmeext, SCAN_LEAVE_OP); set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */ @@ -14776,8 +15558,11 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) #ifdef CONFIG_MCC_MODE /* start MCC fail, then tx null data */ if (!rtw_hal_set_mcc_setting_scan_complete(padapter)) -#endif /* CONFIG_MCC_MODE */ - sitesurvey_ps_annc(padapter, 0); +#endif + { + rtw_hal_macid_wakeup_all_used(padapter); + rtw_ps_annc(padapter, 0); + } /* apply rx ampdu setting */ rtw_rx_ampdu_apply(padapter); @@ -14785,10 +15570,25 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE); report_surveydone_event(padapter); +#ifdef CONFIG_RTW_ACS + if (IS_ACS_ENABLE(padapter)) + rtw_acs_select_best_chan(padapter); +#endif +#if defined(CONFIG_BACKGROUND_NOISE_MONITOR) && defined(DBG_NOISE_MONITOR) + if (IS_NM_ENABLE(padapter)) + rtw_noise_info_dump(RTW_DBGDUMP, padapter); +#endif issue_action_BSSCoexistPacket(padapter); issue_action_BSSCoexistPacket(padapter); issue_action_BSSCoexistPacket(padapter); + +#ifdef CONFIG_RTW_80211K + if (ss->token) + rm_post_event(padapter, ss->token, RM_EV_survey_done); +#endif /* CONFIG_RTW_80211K */ + + break; } return H2C_SUCCESS; @@ -14840,23 +15640,26 @@ u8 setkey_hdl(_adapter *padapter, u8 *pbuf) cam_id = rtw_iface_bcmc_id_get(padapter); else #endif - cam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, &used); + cam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, 1, &used); if (cam_id < 0) goto enable_mc; #ifndef CONFIG_CONCURRENT_MODE - if (cam_id >= 0 && cam_id <= 3) + if (cam_id >= 0 && cam_id <= 3) { + /* default key camid */ addr = null_addr; - else + } else #endif { - if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) - /* for AP mode ,we will force sec cam entry_id so hw dont search cam when tx*/ + /* not default key camid */ + if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) { + /* group TX, force sec cam entry_id */ addr = adapter_mac_addr(padapter); - else - /* not default key, searched by A2 */ + } else { + /* group RX, searched by A2 (TA) */ addr = get_bssid(&padapter->mlmepriv); + } } /* cam entry searched is pairwise key */ @@ -14923,6 +15726,7 @@ u8 setkey_hdl(_adapter *padapter, u8 *pbuf) _rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_BMC)) { struct set_stakey_parm sta_pparm; + _rtw_memset(&sta_pparm, 0, sizeof(struct set_stakey_parm)); sta_pparm.algorithm = pparm->algorithm; sta_pparm.keyid = pparm->keyid; _rtw_memcpy(sta_pparm.key, pparm->key, 16); @@ -14950,11 +15754,12 @@ void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta) if ((psecuritypriv->key_mask & BIT(keyid)) && (keyid == psecuritypriv->dot11PrivacyKeyIndex)) { sta_pparm.algorithm = psecuritypriv->dot11PrivacyAlgrthm; sta_pparm.keyid = keyid; + sta_pparm.gk = 0; _rtw_memcpy(sta_pparm.key, &(psecuritypriv->dot11DefKey[keyid].skey[0]), 16); - _rtw_memcpy(sta_pparm.addr, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(sta_pparm.addr, psta->cmn.mac_addr, ETH_ALEN); RTW_PRINT(FUNC_ADPT_FMT"set WEP - PK with "MAC_FMT" keyid:%u\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->hwaddr), keyid); + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr), keyid); set_stakey_hdl(adapter, (u8 *)&sta_pparm); } @@ -14966,7 +15771,6 @@ u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf) u16 ctrl = 0; s16 cam_id = 0; bool used; - u8 kid = 0; u8 ret = H2C_SUCCESS; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -14985,14 +15789,13 @@ u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf) } pmlmeinfo->enc_algo = pparm->algorithm; - if (is_wep_enc(pparm->algorithm)) - kid = pparm->keyid; - cam_id = rtw_camid_alloc(padapter, psta, kid, &used); + + cam_id = rtw_camid_alloc(padapter, psta, pparm->keyid, pparm->gk, &used); if (cam_id < 0) goto exit; - /* cam entry searched is group key */ - if (used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) { + /* cam entry searched is group key when setting pariwise key */ + if (!pparm->gk && used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) { s16 camid_clr; RTW_PRINT(FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u the same key id as group key\n" @@ -15018,9 +15821,12 @@ u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf) rtw_camid_free(padapter, cam_id); } } else { - RTW_PRINT("set pairwise key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n", - cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm)); + RTW_PRINT("set %s key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n" + , pparm->gk ? "group" : "pairwise" + , cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm)); ctrl = BIT(15) | ((pparm->algorithm) << 2) | pparm->keyid; + if (pparm->gk) + ctrl |= BIT(6); write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key); } ret = H2C_SUCCESS_RSP; @@ -15083,13 +15889,17 @@ u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf) /* status = 0 means accept this addba req, so update indicate seq = start_seq under this compile flag */ if (pparm->status == 0) { preorder_ctrl->indicate_seq = pparm->start_seq; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, start_seq: %d\n", __func__, __LINE__, - preorder_ctrl->indicate_seq, pparm->start_seq); -#endif + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_UPDATE indicate_seq:%d, start_seq:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq); + #endif } #else preorder_ctrl->indicate_seq = 0xffff; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d, start_seq:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq); + #endif #endif /* @@ -15256,7 +16066,7 @@ u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf) if (!psta_bmc) return H2C_SUCCESS; - if ((pstapriv->tim_bitmap & BIT(0)) && (psta_bmc->sleepq_len > 0)) { + if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) { #ifndef CONFIG_PCI_HCI rtw_msleep_os(10);/* 10ms, ATIM(HIQ) Windows */ #endif @@ -15338,16 +16148,33 @@ void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch) u8 network_type, rate_len, total_rate_len, remainder_rate_len; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); u8 erpinfo = 0x4; if (ch >= 36) { network_type = WIRELESS_11A; total_rate_len = IEEE80211_NUM_OFDM_RATESLEN; rtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_); + #ifdef CONFIG_80211AC_VHT + /* if channel in 5G band, then add vht ie . */ + if ((pmlmepriv->htpriv.ht_option == _TRUE) + && REGSTY_IS_11AC_ENABLE(&padapter->registrypriv) + && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) + ) { + if (REGSTY_IS_11AC_AUTO(&padapter->registrypriv) + || pmlmepriv->ori_vht_en) + rtw_vht_ies_attach(padapter, pnetwork); + } + #endif } else { network_type = WIRELESS_11BG; total_rate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN; rtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1); + #ifdef CONFIG_80211AC_VHT + rtw_vht_ies_detach(padapter, pnetwork); + #endif } rtw_set_supported_rate(pnetwork->SupportedRates, network_type); @@ -15411,7 +16238,7 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res) if (!iface || iface == adapter) continue; - if (check_fwstate(mlme, WIFI_AP_STATE) + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) && check_fwstate(mlme, WIFI_ASOC_STATE) ) { bool is_grouped = rtw_is_chbw_grouped(u_ch, u_bw, u_offset @@ -15426,7 +16253,8 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res) rtw_adjust_chbw(iface , mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset); - rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset + rtw_chset_sync_chbw(adapter_to_chset(adapter) + , &mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset , &u_ch, &u_bw, &u_offset); rtw_ap_update_bss_chbw(iface, &(mlmeext->mlmext_info.network) @@ -15435,10 +16263,18 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res) _rtw_memcpy(&(mlme->cur_network.network), &(mlmeext->mlmext_info.network), sizeof(WLAN_BSSID_EX)); rtw_start_bss_hdl_after_chbw_decided(iface); + + if (MLME_IS_GO(iface) || MLME_IS_MESH(iface)) { /* pure AP is not needed*/ + #if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + rtw_cfg80211_ch_switch_notify(iface + , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset + , mlme->htpriv.ht_option); + #endif + } } clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); - update_beacon(iface, 0, NULL, _TRUE); + update_beacon(iface, 0xFF, NULL, _TRUE); } } @@ -15454,11 +16290,11 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res) if (!iface || iface == adapter) continue; - if (check_fwstate(mlme, WIFI_AP_STATE) + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) && check_fwstate(mlme, WIFI_ASOC_STATE) ) { clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); - update_beacon(iface, 0, NULL, _TRUE); + update_beacon(iface, 0xFF, NULL, _TRUE); } } #ifdef CONFIG_DFS_MASTER @@ -15516,10 +16352,11 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) dvobj = adapter_to_dvobj(adapter); rtw_mi_status_no_self(adapter, &mstate); - RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, ap_num:%u\n" - , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_AP_NUM(&mstate)); + RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, ap_num:%u, mesh_num:%u\n" + , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate) + , MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate)); - if (!MSTATE_STA_LD_NUM(&mstate) && !MSTATE_AP_NUM(&mstate)) { + if (!MSTATE_STA_LD_NUM(&mstate) && !MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) { /* consider linking STA? */ goto connect_allow_hdl; } @@ -15571,7 +16408,7 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) } #endif /* CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT */ - if (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) >= 2) + if (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) + MSTATE_MESH_LD_NUM(&mstate) >= 2) connect_allow = _FALSE; RTW_INFO(FUNC_ADPT_FMT" connect_allow:%d\n" @@ -15600,7 +16437,7 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) if (!iface || iface == adapter) continue; - if (check_fwstate(mlme, WIFI_AP_STATE) + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) && check_fwstate(mlme, WIFI_ASOC_STATE) ) { #ifdef CONFIG_SPCT_CH_SWITCH @@ -15638,7 +16475,7 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) } -u8 set_ch_hdl(_adapter *padapter, u8 *pbuf) +u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf) { struct set_ch_parm *set_ch_parm; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -15703,7 +16540,7 @@ u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf) ledBlink_param = (struct LedBlink_param *)pbuf; -#ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD +#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD BlinkHandler((PLED_DATA)ledBlink_param->pLed); #endif @@ -15760,12 +16597,14 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) struct sta_info *ptdls_sta = NULL; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct sta_info *ap_sta = rtw_get_stainfo(&padapter->stapriv, get_my_bssid(&(pmlmeinfo->network))); u8 survey_channel, i, min, option; struct tdls_txmgmt txmgmt; u32 setchtime, resp_sleep = 0, wait_time; u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; u8 ret; u8 doiqk; + u64 tx_ra_bitmap = 0; if (!pbuf) return H2C_PARAMETERS_ERROR; @@ -15794,17 +16633,19 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) /* leave ALL PS when TDLS is established */ rtw_pwr_wakeup(padapter); - rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_WRCR, 0); - RTW_INFO("Created Direct Link with "MAC_FMT"\n", MAC_ARG(ptdls_sta->hwaddr)); + rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_LINKED); + RTW_INFO("Created Direct Link with "MAC_FMT"\n", MAC_ARG(ptdls_sta->cmn.mac_addr)); /* Set TDLS sta rate. */ /* Update station supportRate */ - rtw_hal_update_sta_rate_mask(padapter, ptdls_sta); + rtw_hal_update_sta_ra_info(padapter, ptdls_sta); + tx_ra_bitmap = ptdls_sta->cmn.ra_info.ramask; + if (pmlmeext->cur_channel > 14) { - if (ptdls_sta->ra_mask & 0xffff000) + if (tx_ra_bitmap & 0xffff000) sta_band |= WIRELESS_11_5N ; - if (ptdls_sta->ra_mask & 0xff0) + if (tx_ra_bitmap & 0xff0) sta_band |= WIRELESS_11A; /* 5G band */ @@ -15814,21 +16655,22 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) #endif } else { - if (ptdls_sta->ra_mask & 0xffff000) + if (tx_ra_bitmap & 0xffff000) sta_band |= WIRELESS_11_24N; - if (ptdls_sta->ra_mask & 0xff0) + if (tx_ra_bitmap & 0xff0) sta_band |= WIRELESS_11G; - if (ptdls_sta->ra_mask & 0x0f) + if (tx_ra_bitmap & 0x0f) sta_band |= WIRELESS_11B; } ptdls_sta->wireless_mode = sta_band; - ptdls_sta->raid = rtw_hal_networktype_to_raid(padapter, ptdls_sta); - set_sta_rate(padapter, ptdls_sta); - rtw_sta_media_status_rpt(padapter, ptdls_sta, 1); + rtw_hal_update_sta_wset(padapter, ptdls_sta); /* Sta mode */ rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, ptdls_sta, _TRUE); + + set_sta_rate(padapter, ptdls_sta); + rtw_sta_media_status_rpt(padapter, ptdls_sta, 1); break; } case TDLS_ISSUE_PTI: @@ -15840,8 +16682,10 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) case TDLS_CH_SW_RESP: _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); txmgmt.status_code = 0; - _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); + if (ap_sta) + rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id); issue_nulldata(padapter, NULL, 1, 3, 3); RTW_INFO("[TDLS ] issue tdls channel switch response\n"); @@ -15850,12 +16694,12 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) /* If we receive TDLS_CH_SW_REQ at off channel which it's target is AP's channel */ /* then we just switch to AP's channel*/ if (padapter->mlmeextpriv.cur_channel == pchsw_info->off_ch_num) { - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL); break; } if (ret == _SUCCESS) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_OFF_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL); else RTW_INFO("[TDLS] issue_tdls_ch_switch_rsp wait ack fail !!!!!!!!!!\n"); @@ -15873,7 +16717,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) /* switch back to base-chnl */ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START); pchsw_info->ch_sw_state &= ~(TDLS_CH_SWITCH_PREPARE_STATE); @@ -15882,17 +16726,22 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) rtw_tdls_set_ch_sw_oper_control(padapter, _TRUE); break; case TDLS_CH_SW_TO_OFF_CHNL: + if (ap_sta) + rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id); issue_nulldata(padapter, NULL, 1, 3, 3); + if (padapter->registrypriv.wifi_spec == 0) { if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) _set_timer(&ptdls_sta->ch_sw_timer, (u32)(ptdls_sta->ch_switch_timeout) / 1000); + } if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_OFF_CHNL, pchsw_info->off_ch_num, pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20, ptdls_sta->ch_switch_time) == _SUCCESS) { pchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE); if (pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) { - if (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->hwaddr, 0, 1, 3) == _FAIL) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL); + if (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->cmn.mac_addr, 0, 1, + (padapter->registrypriv.wifi_spec == 0) ? 3 : 0) == _FAIL) + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL); } } else { if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) @@ -15913,7 +16762,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) #endif if (option == TDLS_CH_SW_END_TO_BASE_CHNL) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL); break; case TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED: @@ -15925,13 +16774,15 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) /* Send unsolicited channel switch rsp. to peer */ _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); txmgmt.status_code = 0; - _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); issue_tdls_ch_switch_rsp(padapter, &txmgmt, _FALSE); } } if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_BASE_CHNL, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode, ptdls_sta->ch_switch_time) == _SUCCESS) { + if (ap_sta) + rtw_hal_macid_wakeup(padapter, ap_sta->cmn.mac_id); issue_nulldata(padapter, NULL, 0, 3, 3); /* set ch sw monitor timer for responder */ if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) @@ -15941,17 +16792,19 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) break; #endif case TDLS_RS_RCR: - rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_RS_RCR, 0); - RTW_INFO("[TDLS] write REG_RCR, set bit6 on\n"); + rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK); break; case TDLS_TEARDOWN_STA: + case TDLS_TEARDOWN_STA_NO_WAIT: _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - txmgmt.status_code = 0; - _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; + _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); + + issue_tdls_teardown(padapter, &txmgmt, (option == TDLS_TEARDOWN_STA) ? _TRUE : _FALSE); - issue_tdls_teardown(padapter, &txmgmt, _TRUE); break; case TDLS_TEARDOWN_STA_LOCALLY: + case TDLS_TEARDOWN_STA_LOCALLY_POST: #ifdef CONFIG_TDLS_CH_SW if (_rtw_memcmp(TDLSoption->addr, pchsw_info->addr, ETH_ALEN) == _TRUE) { pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE | @@ -15961,8 +16814,15 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) _rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN); } #endif - rtw_sta_media_status_rpt(padapter, ptdls_sta, 0); - free_tdls_sta(padapter, ptdls_sta); + + if (option == TDLS_TEARDOWN_STA_LOCALLY) + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + + rtw_tdls_teardown_post_hdl(padapter, ptdls_sta, _FALSE); + + if (ptdlsinfo->tdls_sctx != NULL) + rtw_sctx_done(&(ptdlsinfo->tdls_sctx)); + break; } diff --git a/core/rtw_mp.c b/core/rtw_mp.c index 9a024bd..ad9755b 100644 --- a/core/rtw_mp.c +++ b/core/rtw_mp.c @@ -120,7 +120,7 @@ static void _init_mp_priv_(struct mp_priv *pmp_priv) pmp_priv->channel = 1; pmp_priv->bandwidth = CHANNEL_WIDTH_20; - pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_LOWER; pmp_priv->rateidx = RATE_1M; pmp_priv->txpoweridx = 0x2A; @@ -159,6 +159,8 @@ static void _init_mp_priv_(struct mp_priv *pmp_priv) pmp_priv->tx.attrib.ht_en = 1; #endif + pmp_priv->mpt_ctx.mpt_rate_index = 1; + } #ifdef PLATFORM_WINDOWS @@ -337,7 +339,6 @@ s32 init_mp_priv(PADAPTER padapter) pmppriv->antenna_rx = ANTENNA_AB; break; case RF_2T2R: - case RF_2T2R_GREEN: pmppriv->antenna_tx = ANTENNA_AB; pmppriv->antenna_rx = ANTENNA_AB; break; @@ -389,6 +390,10 @@ static VOID PHY_SetRFPathSwitch_default( void mpt_InitHWConfig(PADAPTER Adapter) { + PHAL_DATA_TYPE hal; + + hal = GET_HAL_DATA(Adapter); + if (IS_HARDWARE_TYPE_8723B(Adapter)) { /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */ /* TODO: A better solution is configure it according EFUSE during the run-time. */ @@ -421,6 +426,15 @@ void mpt_InitHWConfig(PADAPTER Adapter) else if (IS_HARDWARE_TYPE_8814A(Adapter)) PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000); #endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(Adapter)) { + rtw_write32(Adapter, 0x520, rtw_read32(Adapter, 0x520) | 0x8000); + rtw_write32(Adapter, 0x524, rtw_read32(Adapter, 0x524) & (~0x800)); + } +#endif + + #ifdef CONFIG_RTL8822B else if (IS_HARDWARE_TYPE_8822B(Adapter)) { u32 tmp_reg = 0; @@ -439,112 +453,24 @@ void mpt_InitHWConfig(PADAPTER Adapter) else if (IS_HARDWARE_TYPE_8821C(Adapter)) PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000); #endif /* CONFIG_RTL8821C */ +#ifdef CONFIG_RTL8188F + else if (IS_HARDWARE_TYPE_8188F(Adapter)) { + if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) { + RTW_INFO("%s() Active large power detection\n", __func__); + phy_active_large_power_detection_8188f(&(GET_HAL_DATA(Adapter)->odmpriv)); + } + } +#endif } static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery) { - PHAL_DATA_TYPE pHalData; - u8 b2ant; /* false:1ant, true:2-ant */ - u8 RF_Path; /* 0:S1, 1:S0 */ - - if (IS_HARDWARE_TYPE_8723B(padapter)) { -#ifdef CONFIG_RTL8723B - pHalData = GET_HAL_DATA(padapter); - b2ant = pHalData->EEPROMBluetoothAntNum == Ant_x2 ? _TRUE : _FALSE; - phy_iq_calibrate_8723b(padapter, bReCovery, _FALSE, b2ant, pHalData->ant_path); -#endif - } else if (IS_HARDWARE_TYPE_8188E(padapter)) { -#ifdef CONFIG_RTL8188E - phy_iq_calibrate_8188e(padapter, bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8814A(padapter)) { -#ifdef CONFIG_RTL8814A - phy_iq_calibrate_8814a(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8812(padapter)) { -#ifdef CONFIG_RTL8812A - phy_iq_calibrate_8812a(padapter, bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8821(padapter)) { -#ifdef CONFIG_RTL8821A - phy_iq_calibrate_8821a(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8192E(padapter)) { -#ifdef CONFIG_RTL8192E - phy_iq_calibrate_8192e(padapter, bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8703B(padapter)) { -#ifdef CONFIG_RTL8703B - phy_iq_calibrate_8703b(padapter, bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8188F(padapter)) { -#ifdef CONFIG_RTL8188F - phy_iq_calibrate_8188f(padapter, bReCovery, _FALSE); -#endif - } else if (IS_HARDWARE_TYPE_8822B(padapter)) { -#ifdef CONFIG_RTL8822B - phy_iq_calibrate_8822b(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8723D(padapter)) { -#ifdef CONFIG_RTL8723D - phy_iq_calibrate_8723d(padapter, bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8821C(padapter)) { -#ifdef CONFIG_RTL8821C - phy_iq_calibrate_8821c(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); -#endif - } - + halrf_iqk_trigger(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); } static void PHY_LCCalibrate(PADAPTER padapter) { - if (IS_HARDWARE_TYPE_8723B(padapter)) { -#ifdef CONFIG_RTL8723B - phy_lc_calibrate_8723b(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8188E(padapter)) { -#ifdef CONFIG_RTL8188E - phy_lc_calibrate_8188e(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8814A(padapter)) { -#ifdef CONFIG_RTL8814A - phy_lc_calibrate_8814a(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8812(padapter)) { -#ifdef CONFIG_RTL8812A - phy_lc_calibrate_8812a(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8821(padapter)) { -#ifdef CONFIG_RTL8821A - phy_lc_calibrate_8821a(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8192E(padapter)) { -#ifdef CONFIG_RTL8192E - phy_lc_calibrate_8192e(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8703B(padapter)) { -#ifdef CONFIG_RTL8703B - phy_lc_calibrate_8703b(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8188F(padapter)) { -#ifdef CONFIG_RTL8188F - phy_lc_calibrate_8188f(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8822B(padapter)) { -#ifdef CONFIG_RTL8822B - phy_lc_calibrate_8822b(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8723D(padapter)) { -#ifdef CONFIG_RTL8723D - phy_lc_calibrate_8723d(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8821C(padapter)) { -#ifdef CONFIG_RTL8821C - /*phy_iq_calibrate_8821c(&(GET_HAL_DATA(padapter)->odmpriv));*/ -#endif - } - + halrf_lck_trigger(&(GET_HAL_DATA(padapter)->odmpriv)); } static u8 PHY_QueryRFPathSwitch(PADAPTER padapter) @@ -601,49 +527,88 @@ static u8 PHY_QueryRFPathSwitch(PADAPTER padapter) static void PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) { + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); + struct dm_struct *phydm = &hal->odmpriv; + if (IS_HARDWARE_TYPE_8723B(padapter)) { #ifdef CONFIG_RTL8723B - phy_set_rf_path_switch_8723b(padapter, bMain); + phy_set_rf_path_switch_8723b(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8188E(padapter)) { #ifdef CONFIG_RTL8188E - phy_set_rf_path_switch_8188e(padapter, bMain); + phy_set_rf_path_switch_8188e(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8814A(padapter)) { #ifdef CONFIG_RTL8814A - phy_set_rf_path_switch_8814a(padapter, bMain); + phy_set_rf_path_switch_8814a(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) { #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - phy_set_rf_path_switch_8812a(padapter, bMain); + phy_set_rf_path_switch_8812a(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8192E(padapter)) { #ifdef CONFIG_RTL8192E - phy_set_rf_path_switch_8192e(padapter, bMain); + phy_set_rf_path_switch_8192e(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8703B(padapter)) { #ifdef CONFIG_RTL8703B - phy_set_rf_path_switch_8703b(padapter, bMain); + phy_set_rf_path_switch_8703b(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8188F(padapter)) { #ifdef CONFIG_RTL8188F - phy_set_rf_path_switch_8188f(padapter, bMain); + phy_set_rf_path_switch_8188f(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8822B(padapter)) { #ifdef CONFIG_RTL8822B - phy_set_rf_path_switch_8822b(padapter, bMain); + phy_set_rf_path_switch_8822b(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8723D(padapter)) { #ifdef CONFIG_RTL8723D - phy_set_rf_path_switch_8723d(padapter, bMain); + phy_set_rf_path_switch_8723d(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8821C(padapter)) { #ifdef CONFIG_RTL8821C - phy_set_rf_path_switch_8821c(padapter, bMain); + phy_set_rf_path_switch_8821c(phydm, bMain); #endif } } + +static void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) { + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dm_struct *p_dm = &pHalData->odmpriv; + +#ifdef CONFIG_RTL8821C + if (IS_HARDWARE_TYPE_8821C(padapter)) { + config_phydm_set_ant_path(p_dm, *prf_set_State, p_dm->current_ant_num_8821c); + /* Do IQK when switching to BTG/WLG, requested by RF Binson */ + if (*prf_set_State == SWITCH_TO_BTG || *prf_set_State == SWITCH_TO_WLG) + PHY_IQCalibrate(padapter, FALSE); + } +#endif + +} + + +#ifdef CONFIG_ANTENNA_DIVERSITY +u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 cur_ant, change_ant; + + if (!pHalData->AntDivCfg) + return _FALSE; + /*rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);*/ + change_ant = (bMain == MAIN_ANT) ? MAIN_ANT : AUX_ANT; + + RTW_INFO("%s: config %s\n", __func__, (bMain == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + rtw_antenna_select_cmd(padapter, change_ant, _FALSE); + + return _TRUE; +} +#endif + s32 MPT_InitializeAdapter( IN PADAPTER pAdapter, @@ -678,11 +643,12 @@ MPT_InitializeAdapter( /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/ phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0); PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/ - /*<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten. */ - if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)) - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); - else - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); + + if (pHalData->PackageType == PACKAGE_DEFAULT) + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); + else + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6F10E); + } /*set ant to wifi side in mp mode*/ rtw_write16(pAdapter, 0x870, 0x300); @@ -691,7 +657,7 @@ MPT_InitializeAdapter( pMptCtx->bMptWorkItemInProgress = _FALSE; pMptCtx->CurrMptAct = NULL; - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; /* ------------------------------------------------------------------------- */ /* Don't accept any packets */ rtw_write32(pAdapter, REG_RCR, 0); @@ -817,7 +783,7 @@ static void init_mp_data(PADAPTER padapter) { u8 v8; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; /*disable BCN*/ v8 = rtw_read8(padapter, REG_BCN_CTRL); @@ -830,7 +796,7 @@ static void init_mp_data(PADAPTER padapter) void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; u32 rf_ability; if (bstart == 1) { @@ -849,20 +815,20 @@ void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart) pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE; padapter->mppriv.mp_dm = 0; { - struct _TXPWRTRACK_CFG c; + struct txpwrtrack_cfg c; u1Byte chnl = 0 ; - _rtw_memset(&c, 0, sizeof(struct _TXPWRTRACK_CFG)); + _rtw_memset(&c, 0, sizeof(struct txpwrtrack_cfg)); configure_txpower_track(pDM_Odm, &c); odm_clear_txpowertracking_state(pDM_Odm); if (*c.odm_tx_pwr_track_set_pwr) { if (pDM_Odm->support_ic_type == ODM_RTL8188F) - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, chnl); + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl); else if (pDM_Odm->support_ic_type == ODM_RTL8723D) { - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl); + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl); SetTxPower(padapter); } else { - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl); - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_B, chnl); + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl); + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_B, chnl); } } } @@ -955,7 +921,7 @@ u32 mp_join(PADAPTER padapter, u8 mode) set_fwstate(pmlmepriv, WIFI_STATION_STATE); /* 3 3. join psudo AdHoc */ tgt_network->join_res = 1; - tgt_network->aid = psta->aid = 1; + tgt_network->aid = psta->cmn.aid = 1; _rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length); rtw_update_registrypriv_dev_network(padapter); @@ -976,12 +942,8 @@ u32 mp_join(PADAPTER padapter, u8 mode) /* set msr to WIFI_FW_ADHOC_STATE */ pmlmeinfo->state = WIFI_FW_ADHOC_STATE; Set_MSR(padapter, (pmlmeinfo->state & 0x3)); - rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); - join_type = 0; - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); - - report_join_res(padapter, 1); + rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED); pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; } else { Set_MSR(padapter, WIFI_FW_STATION_STATE); @@ -1045,7 +1007,6 @@ s32 mp_start_test(PADAPTER padapter) pmppriv->antenna_rx = ANTENNA_AB; break; case RF_2T2R: - case RF_2T2R_GREEN: pmppriv->antenna_tx = ANTENNA_AB; pmppriv->antenna_rx = ANTENNA_AB; break; @@ -1253,6 +1214,13 @@ void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain) } +void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate) +{ + + phy_switch_rf_path_set(pAdapter, pstate); + +} + u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter) { return PHY_QueryRFPathSwitch(pAdapter); @@ -1345,6 +1313,48 @@ static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv) } +#ifdef CONFIG_PCIE_HCI +static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib) +{ + u32 prio; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_tx_ring *ring; + + switch (pattrib->qsel) { + case 0: + case 3: + prio = BE_QUEUE_INX; + break; + case 1: + case 2: + prio = BK_QUEUE_INX; + break; + case 4: + case 5: + prio = VI_QUEUE_INX; + break; + case 6: + case 7: + prio = VO_QUEUE_INX; + break; + default: + prio = BE_QUEUE_INX; + break; + } + + ring = &pxmitpriv->tx_ring[prio]; + + /* + * for now we reserve two free descriptor as a safety boundary + * between the tail and the head + */ + if ((ring->entries - ring->qlen) >= 2) + return _TRUE; + else + return _FALSE; +} +#endif + static thread_return mp_xmit_packet_thread(thread_context context) { struct xmit_frame *pxmitframe; @@ -1363,6 +1373,12 @@ static thread_return mp_xmit_packet_thread(thread_context context) RTW_INFO("%s:pkTx Start\n", __func__); while (1) { pxmitframe = alloc_mp_xmitframe(pxmitpriv); +#ifdef CONFIG_PCIE_HCI + if(check_nic_enough_desc(padapter, &pmptx->attrib) == _FALSE) { + rtw_usleep_os(1000); + continue; + } +#endif if (pxmitframe == NULL) { if (pmptx->stop || RTW_CANNOT_RUN(padapter)) @@ -1796,13 +1812,12 @@ void SetPacketTx(PADAPTER padapter) _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); bmcast = IS_MCAST(pattrib->ra); - if (bmcast) { - pattrib->mac_id = 1; + if (bmcast) pattrib->psta = rtw_get_bcmc_stainfo(padapter); - } else { - pattrib->mac_id = 0; + else pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); - } + + pattrib->mac_id = pattrib->psta->cmn.mac_id; pattrib->mbssid = 0; pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen; @@ -1963,6 +1978,7 @@ void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB) MAC_ARG(pmppriv->network_macaddr)); pHalData->ReceiveConfig = 0; pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF; + pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF; #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) write_bbreg(pAdapter, 0x550, BIT3, bEnable); @@ -2065,7 +2081,11 @@ static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point) rtw_mdelay_os(1); psd_val = rtw_read32(pAdapter, psd_regL); +#if defined(CONFIG_RTL8821C) + psd_val = (psd_val & 0x00FFFFFF) / 32; +#else psd_val &= 0x0000FFFF; +#endif return psd_val; } @@ -2726,10 +2746,10 @@ ULONG mpt_ProQueryCalTxPower( , TxPower, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias); pAdapter->mppriv.txpoweridx = (u8)TxPower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)TxPower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)TxPower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)TxPower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)TxPower; + pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)TxPower; + pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)TxPower; + pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)TxPower; + pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)TxPower; hal_mpt_SetTxPower(pAdapter); return TxPower; diff --git a/core/rtw_odm.c b/core/rtw_odm.c index 7cb9d5f..83e6cfc 100644 --- a/core/rtw_odm.c +++ b/core/rtw_odm.c @@ -19,7 +19,7 @@ u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv; + struct dm_struct *podmpriv = &pHalData->odmpriv; u32 result = 0; switch (ops) { @@ -56,8 +56,7 @@ u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability) /* set ODM_CMNINFO_IC_TYPE based on chip_type */ void rtw_odm_init_ic_type(_adapter *adapter) { - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *odm = &hal_data->odmpriv; + struct dm_struct *odm = adapter_to_phydm(adapter); u4Byte ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter)); rtw_warn_on(!ic_type); @@ -65,20 +64,6 @@ void rtw_odm_init_ic_type(_adapter *adapter) odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type); } -inline void rtw_odm_set_force_igi_lb(_adapter *adapter, u8 lb) -{ - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - - hal_data->u1ForcedIgiLb = lb; -} - -inline u8 rtw_odm_get_force_igi_lb(_adapter *adapter) -{ - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - - return hal_data->u1ForcedIgiLb; -} - void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter) { RTW_PRINT_SEL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n"); @@ -90,9 +75,6 @@ void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter) void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter) { struct registry_priv *regsty = &adapter->registrypriv; - struct mlme_priv *mlme = &adapter->mlmepriv; - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *odm = &hal_data->odmpriv; RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_"); @@ -168,8 +150,7 @@ bool rtw_odm_adaptivity_needed(_adapter *adapter) void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *odm = &pHalData->odmpriv; + struct dm_struct *odm = adapter_to_phydm(adapter); rtw_odm_adaptivity_config_msg(sel, adapter); @@ -192,8 +173,7 @@ void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter) void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff, s8 th_l2h_ini_mode2, s8 th_edcca_hl_diff_mode2, u8 edcca_enable) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *odm = &pHalData->odmpriv; + struct dm_struct *odm = adapter_to_phydm(adapter); odm->th_l2h_ini = th_l2h_ini; odm->th_edcca_hl_diff = th_edcca_hl_diff; @@ -204,11 +184,10 @@ void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_h void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter) { - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *odm = &(hal_data->odmpriv); + struct dm_struct *odm = adapter_to_phydm(adapter); - RTW_PRINT_SEL(sel, "rx_rate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n", - HDATA_RATE(odm->rx_rate), odm->RSSI_A, odm->RSSI_B); + RTW_PRINT_SEL(sel, "rx_rate = %s, rssi_a = %d(%%), rssi_b = %d(%%)\n", + HDATA_RATE(odm->rx_rate), odm->rssi_a, odm->rssi_b); } @@ -241,8 +220,7 @@ void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type) inline u8 rtw_odm_get_dfs_domain(_adapter *adapter) { #ifdef CONFIG_DFS_MASTER - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &(hal_data->odmpriv); + struct dm_struct *pDM_Odm = adapter_to_phydm(adapter); return pDM_Odm->dfs_region_domain; #else @@ -262,23 +240,23 @@ inline u8 rtw_odm_dfs_domain_unknown(_adapter *adapter) #ifdef CONFIG_DFS_MASTER inline VOID rtw_odm_radar_detect_reset(_adapter *adapter) { - phydm_radar_detect_reset(GET_ODM(adapter)); + phydm_radar_detect_reset(adapter_to_phydm(adapter)); } inline VOID rtw_odm_radar_detect_disable(_adapter *adapter) { - phydm_radar_detect_disable(GET_ODM(adapter)); + phydm_radar_detect_disable(adapter_to_phydm(adapter)); } /* called after ch, bw is set */ inline VOID rtw_odm_radar_detect_enable(_adapter *adapter) { - phydm_radar_detect_enable(GET_ODM(adapter)); + phydm_radar_detect_enable(adapter_to_phydm(adapter)); } inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter) { - return phydm_radar_detect(GET_ODM(adapter)); + return phydm_radar_detect(adapter_to_phydm(adapter)); } #endif /* CONFIG_DFS_MASTER */ @@ -290,11 +268,11 @@ void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys) #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) _adapter *adapter = rframe->u.hdr.adapter; - struct PHY_DM_STRUCT *phydm = GET_ODM(adapter); + struct dm_struct *phydm = adapter_to_phydm(adapter); struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib; u8 *wlanhdr = get_recvframe_data(rframe); - if (phydm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) { + if (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) { /* * 8723D: * type_0(CCK) @@ -323,7 +301,7 @@ void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys) */ if ((*phys & 0xf) == 0) { - struct _phy_status_rpt_jaguar2_type0 *phys_t0 = (struct _phy_status_rpt_jaguar2_type0 *)phys; + struct phy_status_rpt_jaguar2_type0 *phys_t0 = (struct phy_status_rpt_jaguar2_type0 *)phys; if (DBG_RX_PHYSTATUS_CHINFO) { RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n" @@ -336,7 +314,7 @@ void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys) } } else if ((*phys & 0xf) == 1) { - struct _phy_status_rpt_jaguar2_type1 *phys_t1 = (struct _phy_status_rpt_jaguar2_type1 *)phys; + struct phy_status_rpt_jaguar2_type1 *phys_t1 = (struct phy_status_rpt_jaguar2_type1 *)phys; u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc; u8 pkt_cch = 0; u8 pkt_bw = CHANNEL_WIDTH_20; @@ -457,7 +435,7 @@ void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys) attrib->ch = pkt_cch; } else { - struct _phy_status_rpt_jaguar2_type2 *phys_t2 = (struct _phy_status_rpt_jaguar2_type2 *)phys; + struct phy_status_rpt_jaguar2_type2 *phys_t2 = (struct phy_status_rpt_jaguar2_type2 *)phys; if (DBG_RX_PHYSTATUS_CHINFO) { RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n" diff --git a/core/rtw_p2p.c b/core/rtw_p2p.c index 906a556..964f1c7 100644 --- a/core/rtw_p2p.c +++ b/core/rtw_p2p.c @@ -80,7 +80,7 @@ static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf) pcur += ETH_ALEN; /* P2P interface address */ - _rtw_memcpy(pcur, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(pcur, psta->cmn.mac_addr, ETH_ALEN); pcur += ETH_ALEN; *pcur = psta->dev_cap; @@ -752,6 +752,7 @@ u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunnel _adapter *padapter = pwdinfo->padapter; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + u16 v16 = 0; if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) goto exit; @@ -789,36 +790,43 @@ u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunnel if (is_any_client_associated(pwdinfo->padapter)) { if (pwdinfo->wfd_tdls_enable) { /* TDLS mode + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } else { /* WiFi Direct mode + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } } else { if (pwdinfo->wfd_tdls_enable) { /* available for WFD session + TDLS mode + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } else { /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } } } else { if (pwdinfo->wfd_tdls_enable) { /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } else { - /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } } } else { - if (pwdinfo->wfd_tdls_enable) - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); - else - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); - + if (pwdinfo->wfd_tdls_enable) { + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); + } else { + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); + } } wfdielen += 2; @@ -2462,7 +2470,7 @@ u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint le /* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */ /* issue GO Discoverability Request */ - issue_group_disc_req(pwdinfo, psta->hwaddr); + issue_group_disc_req(pwdinfo, psta->cmn.mac_addr); /* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */ status = P2P_STATUS_SUCCESS; @@ -3065,19 +3073,20 @@ void find_phase_handler(_adapter *padapter) { struct wifidirect_info *pwdinfo = &padapter->wdinfo; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - NDIS_802_11_SSID ssid; + struct sitesurvey_parm parm; _irqL irqL; u8 _status = 0; - _rtw_memset((unsigned char *)&ssid, 0, sizeof(NDIS_802_11_SSID)); - _rtw_memcpy(ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN); - ssid.SsidLength = P2P_WILDCARD_SSID_LEN; + rtw_init_sitesurvey_parm(padapter, &parm); + _rtw_memcpy(&parm.ssid[0].Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN); + parm.ssid[0].SsidLength = P2P_WILDCARD_SSID_LEN; + parm.ssid_num = 1; rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); _enter_critical_bh(&pmlmepriv->lock, &irqL); - _status = rtw_sitesurvey_cmd(padapter, &ssid, 1, NULL, 0); + _status = rtw_sitesurvey_cmd(padapter, &parm); _exit_critical_bh(&pmlmepriv->lock, &irqL); @@ -3102,11 +3111,7 @@ void restore_p2p_state_handler(_adapter *padapter) if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP)) { set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - #ifdef CONFIG_AP_MODE - /*mac-id sleep or wake-up for AP mode*/ - rtw_mi_buddy_ap_acdata_control(padapter, 0); - #endif/*CONFIG_AP_MODE*/ - rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); + rtw_back_opch(padapter); } } #endif @@ -3170,6 +3175,12 @@ void p2p_concurrent_handler(_adapter *padapter) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u8 val8; +#ifdef CONFIG_IOCTL_CFG80211 + if (pwdinfo->driver_interface == DRIVER_CFG80211 + && !rtw_cfg80211_get_is_roch(padapter)) + return; +#endif + if (rtw_mi_check_status(padapter, MI_LINKED)) { u8 union_ch = rtw_mi_get_union_chan(padapter); u8 union_bw = rtw_mi_get_union_bw(padapter); @@ -3178,13 +3189,10 @@ void p2p_concurrent_handler(_adapter *padapter) pwdinfo->operating_channel = union_ch; if (pwdinfo->driver_interface == DRIVER_CFG80211) { - RTW_INFO("%s, switch ch back to union_ch=%d\n", __func__, union_ch); + RTW_INFO("%s, switch ch back to union=%u,%u, %u\n" + , __func__, union_ch, union_bw, union_offset); set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - #ifdef CONFIG_AP_MODE - /*mac-id sleep or wake-up for AP mode*/ - rtw_mi_buddy_ap_acdata_control(padapter, 0); - #endif/*CONFIG_AP_MODE*/ - rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); + rtw_back_opch(padapter); } else if (pwdinfo->driver_interface == DRIVER_WEXT) { if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) { @@ -3194,12 +3202,7 @@ void p2p_concurrent_handler(_adapter *padapter) RTW_INFO("[%s] P2P_STATE_IDLE, ext_listen_period = %d\n", __FUNCTION__, pwdinfo->ext_listen_period); if (union_ch != pwdinfo->listen_channel) { - #ifdef CONFIG_AP_MODE - /*mac-id sleep or wake-up for AP mode*/ - rtw_mi_buddy_ap_acdata_control(padapter, 1); - #endif/*CONFIG_AP_MODE*/ - /* Will switch to listen channel so that need to send the NULL data with PW bit to AP. */ - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); + rtw_leave_opch(padapter); set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); } @@ -3212,6 +3215,7 @@ void p2p_concurrent_handler(_adapter *padapter) /* Todo: To check the value of pwdinfo->ext_listen_period is equal to 0 or not. */ _set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period); } + } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL) || (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _FALSE) || @@ -3231,25 +3235,19 @@ void p2p_concurrent_handler(_adapter *padapter) rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); } rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE); - #ifdef CONFIG_AP_MODE - /*mac-id sleep or wake-up for AP mode*/ - rtw_mi_buddy_ap_acdata_control(padapter, 0); - #endif/*CONFIG_AP_MODE*/ - rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); + rtw_back_opch(padapter); } /* Todo: To check the value of pwdinfo->ext_listen_interval is equal to 0 or not. */ _set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval); + } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) { /* The driver had finished the P2P handshake successfully. */ val8 = 0; rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - #ifdef CONFIG_AP_MODE - /*mac-id sleep or wake-up for AP mode*/ - rtw_mi_buddy_ap_acdata_control(padapter, 0); - #endif/*CONFIG_AP_MODE*/ - rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); + rtw_back_opch(padapter); + } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) { val8 = 1; set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); @@ -3284,10 +3282,133 @@ void p2p_concurrent_handler(_adapter *padapter) #endif #ifdef CONFIG_IOCTL_CFG80211 +u8 roch_stay_in_cur_chan(_adapter *padapter) +{ + int i; + _adapter *iface; + struct mlme_priv *pmlmepriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u8 rst = _FALSE; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + pmlmepriv = &iface->mlmepriv; + + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS) == _TRUE) { + RTW_ERR(ADPT_FMT"- _FW_UNDER_LINKING |WIFI_UNDER_WPS (mlme state:0x%x)\n", + ADPT_ARG(iface), get_fwstate(&iface->mlmepriv)); + rst = _TRUE; + break; + } + #ifdef CONFIG_AP_MODE + if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) { + if (rtw_ap_sta_linking_state_check(iface) == _TRUE) { + RTW_ERR(ADPT_FMT"- SoftAP/Mesh -have sta under linking\n", ADPT_ARG(iface)); + rst = _TRUE; + break; + } + } + #endif + } + } + + return rst; +} + static int ro_ch_handler(_adapter *adapter, u8 *buf) { - /* TODO: move remain on channel logical here */ - return H2C_SUCCESS; + int ret = H2C_SUCCESS; + struct p2p_roch_parm *roch_parm = (struct p2p_roch_parm *)buf; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); + struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &adapter->cfg80211_wdinfo; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + u8 ready_on_channel = _FALSE; + u8 remain_ch; + unsigned int duration; + + _enter_critical_mutex(&pwdev_priv->roch_mutex, NULL); + + if (rtw_cfg80211_get_is_roch(adapter) != _TRUE) + goto exit; + + remain_ch = (u8)ieee80211_frequency_to_channel(roch_parm->ch.center_freq); + duration = roch_parm->duration; + + RTW_INFO(FUNC_ADPT_FMT" ch:%u duration:%d, cookie:0x%llx\n" + , FUNC_ADPT_ARG(adapter), remain_ch, roch_parm->duration, roch_parm->cookie); + + if (roch_parm->wdev && roch_parm->cookie) { + if (pcfg80211_wdinfo->ro_ch_wdev != roch_parm->wdev) { + RTW_WARN(FUNC_ADPT_FMT" ongoing wdev:%p, wdev:%p\n" + , FUNC_ADPT_ARG(adapter), pcfg80211_wdinfo->ro_ch_wdev, roch_parm->wdev); + rtw_warn_on(1); + } + + if (pcfg80211_wdinfo->remain_on_ch_cookie != roch_parm->cookie) { + RTW_WARN(FUNC_ADPT_FMT" ongoing cookie:0x%llx, cookie:0x%llx\n" + , FUNC_ADPT_ARG(adapter), pcfg80211_wdinfo->remain_on_ch_cookie, roch_parm->cookie); + rtw_warn_on(1); + } + } + + if (roch_stay_in_cur_chan(adapter) == _TRUE) { + remain_ch = rtw_mi_get_union_chan(adapter); + RTW_INFO(FUNC_ADPT_FMT" stay in union ch:%d\n", FUNC_ADPT_ARG(adapter), remain_ch); + } + + #ifdef CONFIG_CONCURRENT_MODE + if (rtw_mi_check_status(adapter, MI_LINKED) && (0 != rtw_mi_get_union_chan(adapter))) { + if ((remain_ch != rtw_mi_get_union_chan(adapter)) && !check_fwstate(&adapter->mlmepriv, _FW_LINKED)) { + if (remain_ch != pmlmeext->cur_channel + #ifdef RTW_ROCH_BACK_OP + || ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1 + #endif + ) { + rtw_leave_opch(adapter); + + #ifdef RTW_ROCH_BACK_OP + RTW_INFO("%s, set switch ch timer, duration=%d\n", __func__, duration - pwdinfo->ext_listen_interval); + ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); + _set_timer(&pwdinfo->ap_p2p_switch_timer, duration - pwdinfo->ext_listen_interval); + #endif + } + } + ready_on_channel = _TRUE; + } else + #endif /* CONFIG_CONCURRENT_MODE */ + { + if (remain_ch != rtw_get_oper_ch(adapter)) + ready_on_channel = _TRUE; + } + + if (ready_on_channel == _TRUE) { + #ifndef RTW_SINGLE_WIPHY + if (!check_fwstate(&adapter->mlmepriv, _FW_LINKED)) + #endif + { + #ifdef CONFIG_CONCURRENT_MODE + if (rtw_get_oper_ch(adapter) != remain_ch) + #endif + { + /* if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic) */ + set_channel_bwmode(adapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } + } + } + + #ifdef CONFIG_BT_COEXIST + rtw_btcoex_ScanNotify(adapter, _TRUE); + #endif + + RTW_INFO("%s, set ro ch timer, duration=%d\n", __func__, duration); + _set_timer(&pcfg80211_wdinfo->remain_on_ch_timer, duration); + +exit: + _exit_critical_mutex(&pwdev_priv->roch_mutex, NULL); + + return ret; } static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf) @@ -3319,6 +3440,10 @@ static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf) } } +#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) + _cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer); +#endif + if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) { if (0) RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", @@ -3340,14 +3465,7 @@ static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf) } set_channel_bwmode(padapter, ch, offset, bw); - if (rtw_mi_buddy_check_fwstate(padapter, _FW_LINKED)) { - #ifdef CONFIG_AP_MODE - /*mac-id sleep or wake-up for AP mode*/ - rtw_mi_buddy_ap_acdata_control(padapter, 0); - #endif/*CONFIG_AP_MODE*/ - rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); - } - + rtw_back_opch(padapter); rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); #ifdef CONFIG_DEBUG_CFG80211 @@ -3358,7 +3476,7 @@ static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf) rtw_cfg80211_set_is_roch(padapter, _FALSE); pcfg80211_wdinfo->ro_ch_wdev = NULL; - pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); + rtw_cfg80211_set_last_ro_ch_time(padapter); rtw_cfg80211_remain_on_channel_expired(wdev , pcfg80211_wdinfo->remain_on_ch_cookie @@ -4079,10 +4197,13 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) if (!tx) { #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { + #if defined(CONFIG_P2P_INVITE_IOT) if (op_ch != -1 && rtw_chk_p2pie_op_ch_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) { RTW_INFO(FUNC_ADPT_FMT" op_ch:%u has no intersect with buddy\n", FUNC_ADPT_ARG(padapter), op_ch); rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0); - } else if (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) { + } else + #endif + if (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) { RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter)); rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0); } @@ -4198,24 +4319,23 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) switch (OUI_Subtype) { case P2P_NOTICE_OF_ABSENCE: - RTW_INFO("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", dialogToken); + RTW_INFO("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken); break; case P2P_PRESENCE_REQUEST: - RTW_INFO("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", dialogToken); + RTW_INFO("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken); break; case P2P_PRESENCE_RESPONSE: - RTW_INFO("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", dialogToken); + RTW_INFO("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken); break; case P2P_GO_DISC_REQUEST: - RTW_INFO("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", dialogToken); + RTW_INFO("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken); break; default: - RTW_INFO("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", OUI_Subtype, dialogToken); + RTW_INFO("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", OUI_Subtype, dialogToken); break; } - } else - RTW_INFO("RTW_%s:action frame category=%d\n", (tx == _TRUE) ? "TX" : "RX", category); + } return is_p2p_frame; } @@ -4500,6 +4620,9 @@ void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) break; } +#ifdef CONFIG_MCC_MODE + rtw_hal_mcc_process_noa(padapter); +#endif /* CONFIG_MCC_MODE */ } u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue) diff --git a/core/rtw_pwrctrl.c b/core/rtw_pwrctrl.c index eca0e4a..671fba4 100644 --- a/core/rtw_pwrctrl.c +++ b/core/rtw_pwrctrl.c @@ -85,6 +85,10 @@ void _ips_enter(_adapter *padapter) if (pwrpriv->ips_mode == IPS_LEVEL_2) pwrpriv->bkeepfwalive = _TRUE; +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + pwrpriv->pwr_saving_start_time = rtw_get_current_time(); +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + rtw_ips_pwr_down(padapter); pwrpriv->rf_pwrstate = rf_off; } @@ -120,6 +124,11 @@ int _ips_leave(_adapter *padapter) result = rtw_ips_pwr_up(padapter); if (result == _SUCCESS) pwrpriv->rf_pwrstate = rf_on; + +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time); +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + RTW_PRINT("nolinked power save leave\n"); RTW_INFO("==> ips_leave.....LED(0x%08x)...\n", rtw_read32(padapter, 0x4c)); @@ -183,9 +192,6 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter) struct mlme_priv *pmlmepriv; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo; -#ifdef CONFIG_IOCTL_CFG80211 - struct cfg80211_wifidirect_info *pcfg80211_wdinfo; -#endif #endif bool ret = _FALSE; @@ -195,7 +201,7 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter) goto exit; } - if (adapter_to_pwrctl(adapter)->ips_deny_time >= rtw_get_current_time()) { + if (rtw_time_after(adapter_to_pwrctl(adapter)->ips_deny_time, rtw_get_current_time())) { /* RTW_INFO("%s ips_deny_time\n", __func__); */ goto exit; } @@ -206,24 +212,21 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter) pmlmepriv = &(iface->mlmepriv); #ifdef CONFIG_P2P pwdinfo = &(iface->wdinfo); -#ifdef CONFIG_IOCTL_CFG80211 - pcfg80211_wdinfo = &iface->cfg80211_wdinfo; -#endif #endif if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_SITE_MONITOR) - || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS) - || check_fwstate(pmlmepriv, WIFI_AP_STATE) - || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) -#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) - || rtw_cfg80211_get_is_roch(iface) == _TRUE -#elif defined(CONFIG_P2P) - || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) - || rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) -#endif -#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) - || rtw_get_passing_time_ms(pcfg80211_wdinfo->last_ro_ch_time) < 3000 -#endif - ) + || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS) + || MLME_IS_AP(iface) + || MLME_IS_MESH(iface) + || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) + #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) + || rtw_cfg80211_get_is_roch(iface) == _TRUE + || (rtw_cfg80211_is_ro_ch_once(adapter) + && rtw_cfg80211_get_last_ro_ch_passing_ms(adapter) < 3000) + #elif defined(CONFIG_P2P) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) + #endif + ) goto exit; } @@ -398,7 +401,7 @@ void pwr_state_check_handler(void *ctx) void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets) { #ifdef CONFIG_CHECK_LEAVE_LPS - static u32 start_time = 0; + static systime start_time = 0; static u32 xmit_cnt = 0; u8 bLeaveLPS = _FALSE; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -456,7 +459,7 @@ u8 rtw_cpwm_polling(_adapter *adapter, u8 cpwm_orig) u8 result = _FAIL; u8 cpwm_now; u8 poll_cnt = 0; - u32 start_time; + systime start_time; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); struct debug_priv *pdbgpriv = &(adapter_to_dvobj(adapter)->drv_dbg); @@ -600,7 +603,7 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv) u8 PS_RDY_CHECK(_adapter *padapter) { - u32 curr_time, delta_time; + u32 delta_ms; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); #ifdef CONFIG_P2P @@ -622,26 +625,24 @@ u8 PS_RDY_CHECK(_adapter *padapter) return _FALSE; #endif - curr_time = rtw_get_current_time(); - - delta_time = curr_time - pwrpriv->DelayLPSLastTimeStamp; - - if (delta_time < LPS_DELAY_TIME) + delta_ms = rtw_get_passing_time_ms(pwrpriv->DelayLPSLastTimeStamp); + if (delta_ms < LPS_DELAY_MS) return _FALSE; if (check_fwstate(pmlmepriv, WIFI_SITE_MONITOR) - || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS) - || check_fwstate(pmlmepriv, WIFI_AP_STATE) - || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) -#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) - || rtw_cfg80211_get_is_roch(padapter) == _TRUE -#endif - || rtw_is_scan_deny(padapter) -#ifdef CONFIG_TDLS - /* TDLS link is established. */ - || (padapter->tdlsinfo.link_established == _TRUE) -#endif /* CONFIG_TDLS */ - ) + || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS) + || MLME_IS_AP(padapter) + || MLME_IS_MESH(padapter) + || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) + #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) + || rtw_cfg80211_get_is_roch(padapter) == _TRUE + #endif + || rtw_is_scan_deny(padapter) + #ifdef CONFIG_TDLS + /* TDLS link is established. */ + || (padapter->tdlsinfo.link_established == _TRUE) + #endif /* CONFIG_TDLS */ + ) return _FALSE; if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == _FALSE)) { @@ -662,7 +663,7 @@ void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); int cnt = 0; - u32 start_time; + systime start_time; u8 val8 = 0; u8 cpwm_orig = 0, cpwm_now = 0; u8 parm[H2C_INACTIVE_PS_LEN] = {0}; @@ -704,11 +705,11 @@ void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable) /* H2C done, enter 32k */ if (val8 == 0) { /* ser rpwm to enter 32k */ - val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1); + rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8); RTW_INFO("%s: read rpwm=%02x\n", __FUNCTION__, val8); val8 += 0x80; val8 |= BIT(0); - rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8); + rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8)); RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8); adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80; cnt = val8 = 0; @@ -737,11 +738,10 @@ void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable) rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig); /* ser rpwm */ - val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1); - val8 &= 0x80; + rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8); val8 += 0x80; val8 |= BIT(6); - rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8); + rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8)); RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8); adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80; @@ -779,6 +779,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct registry_priv *pregistrypriv = &padapter->registrypriv; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif /* CONFIG_P2P */ @@ -804,9 +805,12 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode return; #ifndef CONFIG_BT_COEXIST - if ((pwrpriv->smart_ps == smart_ps) && - (pwrpriv->bcn_ant_mode == bcn_ant_mode)) - return; +#ifdef CONFIG_WMMPS_STA + if (!rtw_is_wmmps_mode(padapter)) +#endif /* CONFIG_WMMPS_STA */ + if ((pwrpriv->smart_ps == smart_ps) && + (pwrpriv->bcn_ant_mode == bcn_ant_mode)) + return; #endif /* !CONFIG_BT_COEXIST */ } @@ -863,7 +867,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list); if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) - issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 0, 0, 0); + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0); plist = get_next(plist); } } @@ -876,7 +880,8 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode if (pwrpriv->wowlan_mode == _TRUE || pwrpriv->wowlan_ap_mode == _TRUE || pwrpriv->wowlan_p2p_mode == _TRUE) { - u32 start_time, delay_ms; + systime start_time; + u32 delay_ms; u8 val8; delay_ms = 20; start_time = rtw_get_current_time(); @@ -950,7 +955,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list); if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) - issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 1, 0, 0); + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 0, 0); plist = get_next(plist); } } @@ -969,6 +974,11 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode pwrpriv->pwr_mode = ps_mode; pwrpriv->smart_ps = smart_ps; pwrpriv->bcn_ant_mode = bcn_ant_mode; + +#ifdef CONFIG_WMMPS_STA + pwrpriv->wmm_smart_ps = pregistrypriv->wmm_smart_ps; +#endif /* CONFIG_WMMPS_STA */ + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); #ifdef CONFIG_P2P_PS @@ -1013,7 +1023,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode */ s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms) { - u32 start_time; + systime start_time; u8 bAwake = _FALSE; s32 err = 0; @@ -1093,8 +1103,19 @@ void LPS_Enter(PADAPTER padapter, const char *msg) /* Idle for a while if we connect to AP a while ago. */ if (pwrpriv->LpsIdleCount >= 2) { /* 4 Sec */ if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) { + +#ifdef CONFIG_WMMPS_STA + if (rtw_is_wmmps_mode(padapter)) + msg = "WMMPS_IDLE"; +#endif /* CONFIG_WMMPS_STA */ + sprintf(buf, "WIFI-%s", msg); pwrpriv->bpower_saving = _TRUE; + +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + pwrpriv->pwr_saving_start_time = rtw_get_current_time(); +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + rtw_set_ps_mode(padapter, pwrpriv->power_mgnt, padapter->registrypriv.smart_ps, 0, buf); } } else @@ -1130,9 +1151,19 @@ void LPS_Leave(PADAPTER padapter, const char *msg) if (pwrpriv->bLeisurePs) { if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) { + +#ifdef CONFIG_WMMPS_STA + if (rtw_is_wmmps_mode(padapter)) + msg = "WMMPS_BUSY"; +#endif /* CONFIG_WMMPS_STA */ + sprintf(buf, "WIFI-%s", msg); rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, buf); +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time); +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) LPS_RF_ON_check(padapter, LPS_LEAVE_TIMEOUT_MS); } @@ -1173,7 +1204,7 @@ void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; #ifndef CONFIG_DETECT_CPWM_BY_POLLING u8 cpwm_orig, cpwm_now; - u32 start_time; + systime start_time; #endif /* CONFIG_DETECT_CPWM_BY_POLLING */ @@ -1353,7 +1384,7 @@ void LPS_Leave_check( PADAPTER padapter) { struct pwrctrl_priv *pwrpriv; - u32 start_time; + systime start_time; u8 bReady; @@ -1466,6 +1497,30 @@ static void dma_event_callback(struct work_struct *work) } #ifdef CONFIG_LPS_RPWM_TIMER + +#define DBG_CPWM_CHK_FAIL +#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)) +#define CPU_EXCEPTION_CODE 0xFAFAFAFA +static void rtw_cpwm_chk_fail_debug(_adapter *padapter) +{ + u32 cpu_state; + + cpu_state = rtw_read32(padapter, 0x10FC); + + RTW_INFO("[PS-DBG] Reg_10FC =0x%08x\n", cpu_state); + RTW_INFO("[PS-DBG] Reg_10F8 =0x%08x\n", rtw_read32(padapter, 0x10F8)); + + if (cpu_state == CPU_EXCEPTION_CODE) { + RTW_INFO("[PS-DBG] Reg_48C =0x%08x\n", rtw_read32(padapter, 0x48C)); + RTW_INFO("[PS-DBG] Reg_490 =0x%08x\n", rtw_read32(padapter, 0x490)); + RTW_INFO("[PS-DBG] Reg_494 =0x%08x\n", rtw_read32(padapter, 0x494)); + RTW_INFO("[PS-DBG] Reg_498 =0x%08x\n", rtw_read32(padapter, 0x498)); + RTW_INFO("[PS-DBG] Reg_49C =0x%08x\n", rtw_read32(padapter, 0x49C)); + RTW_INFO("[PS-DBG] Reg_4A0 =0x%08x\n", rtw_read32(padapter, 0x4A0)); + RTW_INFO("[PS-DBG] Reg_1BC =0x%08x\n", rtw_read32(padapter, 0x1BC)); + } +} +#endif static void rpwmtimeout_workitem_callback(struct work_struct *work) { PADAPTER padapter; @@ -1476,7 +1531,6 @@ static void rpwmtimeout_workitem_callback(struct work_struct *work) pwrpriv = container_of(work, struct pwrctrl_priv, rpwmtimeoutwi); dvobj = pwrctl_to_dvobj(pwrpriv); padapter = dvobj_get_primary_adapter(dvobj); - /* RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); */ if (!padapter) return; @@ -1491,6 +1545,11 @@ static void rpwmtimeout_workitem_callback(struct work_struct *work) } _exit_pwrlock(&pwrpriv->lock); +#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)) + RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); + rtw_cpwm_chk_fail_debug(padapter); +#endif + if (rtw_read8(padapter, 0x100) != 0xEA) { #if 1 struct reportpwrstate_parm report; @@ -1971,11 +2030,12 @@ void rtw_unregister_evt_alive(PADAPTER padapter) void rtw_init_pwrctrl_priv(PADAPTER padapter) { struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + struct registry_priv *registry_par = &padapter->registrypriv; u8 val8 = 0; #if defined(CONFIG_CONCURRENT_MODE) - if (padapter->adapter_type != PRIMARY_ADAPTER) + if (!is_primary_adapter(padapter)) return; #endif @@ -1995,11 +2055,14 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode; pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode; + pwrctrlpriv->ips_deny_time = rtw_get_current_time(); pwrctrlpriv->lps_level = padapter->registrypriv.lps_level; pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL; pwrctrlpriv->pwr_state_check_cnts = 0; + #ifdef CONFIG_AUTOSUSPEND pwrctrlpriv->bInternalAutoSuspend = _FALSE; + #endif pwrctrlpriv->bInSuspend = _FALSE; pwrctrlpriv->bkeepfwalive = _FALSE; @@ -2069,14 +2132,28 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) #ifdef CONFIG_GPIO_WAKEUP /*default low active*/ pwrctrlpriv->is_high_active = HIGH_ACTIVE; + + #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE + if (pwrctrlpriv->is_high_active == 0) + rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX); + else + rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0); + #else val8 = (pwrctrlpriv->is_high_active == 0) ? 1 : 0; rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE); rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8); RTW_INFO("%s: set GPIO_%d %d as default.\n", __func__, WAKEUP_GPIO_IDX, val8); + #endif /*CONFIG_WAKEUP_GPIO_INPUT_MODE*/ #endif /* CONFIG_GPIO_WAKEUP */ #ifdef CONFIG_WOWLAN + + if (registry_par->wakeup_event & BIT(1)) + pwrctrlpriv->default_patterns_en = _TRUE; + else + pwrctrlpriv->default_patterns_en = _FALSE; + rtw_wow_pattern_sw_reset(padapter); #ifdef CONFIG_PNO_SUPPORT pwrctrlpriv->pno_inited = _FALSE; @@ -2103,7 +2180,7 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter) struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter); #if defined(CONFIG_CONCURRENT_MODE) - if (adapter->adapter_type != PRIMARY_ADAPTER) + if (!is_primary_adapter(adapter)) return; #endif @@ -2122,6 +2199,14 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter) rtw_hal_set_hwreg(adapter, HW_VAR_LPS_POFF_DEINIT, 0); #endif +#ifdef CONFIG_LPS_LCLK + _cancel_workitem_sync(&pwrctrlpriv->cpwm_event); + _cancel_workitem_sync(&pwrctrlpriv->dma_event); + #ifdef CONFIG_LPS_RPWM_TIMER + _cancel_workitem_sync(&pwrctrlpriv->rpwmtimeoutwi); + #endif +#endif /* CONFIG_LPS_LCLK */ + #ifdef CONFIG_WOWLAN #ifdef CONFIG_PNO_SUPPORT if (pwrctrlpriv->pnlo_info != NULL) @@ -2328,7 +2413,7 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) struct mlme_priv *pmlmepriv; int ret = _SUCCESS; int i; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); /* for LPS */ LeaveAllPowerSaveMode(padapter); @@ -2337,7 +2422,7 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) padapter = GET_PRIMARY_ADAPTER(padapter); pmlmepriv = &padapter->mlmepriv; - if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms)) + if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time)) pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms); @@ -2363,7 +2448,11 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) } #endif - if (pwrpriv->bInternalAutoSuspend == _FALSE && pwrpriv->bInSuspend) { + if (pwrpriv->bInSuspend + #ifdef CONFIG_AUTOSUSPEND + && pwrpriv->bInternalAutoSuspend == _FALSE + #endif + ) { RTW_INFO("%s wait bInSuspend...\n", __func__); while (pwrpriv->bInSuspend && ((rtw_get_passing_time_ms(start) <= 3000 && !rtw_is_do_late_resume(pwrpriv)) @@ -2377,17 +2466,21 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) } /* System suspend is not allowed to wakeup */ - if ((pwrpriv->bInternalAutoSuspend == _FALSE) && (_TRUE == pwrpriv->bInSuspend)) { + if ((_TRUE == pwrpriv->bInSuspend) + #ifdef CONFIG_AUTOSUSPEND + && (pwrpriv->bInternalAutoSuspend == _FALSE) + #endif + ) { ret = _FAIL; goto exit; } - - /* block??? */ +#ifdef CONFIG_AUTOSUSPEND + /* usb autosuspend block??? */ if ((pwrpriv->bInternalAutoSuspend == _TRUE) && (padapter->net_closed == _TRUE)) { ret = _FAIL; goto exit; } - +#endif /* I think this should be check in IPS, LPS, autosuspend functions... */ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { #if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND) @@ -2455,7 +2548,7 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) } exit: - if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms)) + if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time)) pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms); return ret; diff --git a/core/rtw_recv.c b/core/rtw_recv.c index 69c7a3c..4da9bc4 100644 --- a/core/rtw_recv.c +++ b/core/rtw_recv.c @@ -600,11 +600,12 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) } } - if ((prxattrib->encrypt > 0) && ((prxattrib->bdecrypted == 0) || (psecuritypriv->sw_decrypt == _TRUE))) { - -#ifdef CONFIG_CONCURRENT_MODE - if (!IS_MCAST(prxattrib->ra)) /* bc/mc packets use sw decryption for concurrent mode */ -#endif + if (prxattrib->encrypt && !prxattrib->bdecrypted) { + if (GetFrameType(get_recvframe_data(precv_frame)) == WIFI_DATA + #ifdef CONFIG_CONCURRENT_MODE + && !IS_MCAST(prxattrib->ra) /* bc/mc packets may use sw decryption for concurrent mode */ + #endif + ) psecuritypriv->hw_decrypted = _FALSE; #ifdef DBG_RX_SW_DECRYPTOR @@ -685,6 +686,13 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) #endif } + #ifdef CONFIG_RTW_MESH + if (res != _FAIL + && !prxattrib->amsdu + && prxattrib->mesh_ctrl_present) + res = rtw_mesh_rx_validate_mctrl_non_amsdu(padapter, precv_frame); + #endif + if (res == _FAIL) { rtw_free_recvframe(return_packet, &padapter->recvpriv.free_recv_queue); return_packet = NULL; @@ -766,91 +774,145 @@ union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame) } -sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache); -sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache) +sint recv_decache(union recv_frame *precv_frame, u16 *tid_rxseq) { - sint tid = precv_frame->u.hdr.attrib.priority; + struct sta_info *sta = precv_frame->u.hdr.psta; + sint tid = precv_frame->u.hdr.attrib.priority; u16 seq_ctrl = ((precv_frame->u.hdr.attrib.seq_num & 0xffff) << 4) | (precv_frame->u.hdr.attrib.frag_num & 0xf); + if (tid > 15) + return _FAIL; + + if (seq_ctrl == tid_rxseq[tid]) { + /* for non-AMPDU case */ + sta->sta_stats.duplicate_cnt++; - if (tid > 15) { + if (sta->sta_stats.duplicate_cnt % 100 == 0) + RTW_INFO("%s: tid=%u seq=%d frag=%d\n", __func__ + , tid, precv_frame->u.hdr.attrib.seq_num + , precv_frame->u.hdr.attrib.frag_num); return _FAIL; } - if (1) { /* if(bretry) */ - if (seq_ctrl == prxcache->tid_rxseq[tid]) { - /* for non-AMPDU case */ - precv_frame->u.hdr.psta->sta_stats.duplicate_cnt++; + tid_rxseq[tid] = seq_ctrl; - if (precv_frame->u.hdr.psta->sta_stats.duplicate_cnt % 100 == 0) - RTW_INFO("%s: seq=%d\n", __func__, precv_frame->u.hdr.attrib.seq_num); + return _SUCCESS; +} - return _FAIL; +/* VALID_PN_CHK + * Return true when PN is legal, otherwise false. + * Legal PN: + * 1. If old PN is 0, any PN is legal + * 2. PN > old PN + */ +#define PN_LESS_CHK(a, b) (((a-b) & 0x800000000000) != 0) +#define VALID_PN_CHK(new, old) (((old) == 0) || PN_LESS_CHK(old, new)) +#define CCMPH_2_KEYID(ch) (((ch) & 0x00000000c0000000) >> 30) +sint recv_ucast_pn_decache(union recv_frame *precv_frame); +sint recv_ucast_pn_decache(union recv_frame *precv_frame) +{ + _adapter *padapter = precv_frame->u.hdr.adapter; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_info *sta = precv_frame->u.hdr.psta; + struct stainfo_rxcache *prxcache = &sta->sta_recvpriv.rxcache; + u8 *pdata = precv_frame->u.hdr.rx_data; + u32 data_len = precv_frame->u.hdr.len; + sint tid = precv_frame->u.hdr.attrib.priority; + u64 tmp_iv_hdr = 0; + u64 curr_pn = 0, pkt_pn = 0; + + if (tid > 15) + return _FAIL; + + if (pattrib->encrypt == _AES_) { + tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen)); + pkt_pn = CCMPH_2_PN(tmp_iv_hdr); + tmp_iv_hdr = le64_to_cpu(*(u64*)prxcache->iv[tid]); + curr_pn = CCMPH_2_PN(tmp_iv_hdr); + + if (!VALID_PN_CHK(pkt_pn, curr_pn)) { + /* return _FAIL; */ + } else { + prxcache->last_tid = tid; + _rtw_memcpy(prxcache->iv[tid], + (pdata + pattrib->hdrlen), + sizeof(prxcache->iv[tid])); } } - prxcache->tid_rxseq[tid] = seq_ctrl; + return _SUCCESS; +} + +sint recv_bcast_pn_decache(union recv_frame *precv_frame); +sint recv_bcast_pn_decache(union recv_frame *precv_frame) +{ + _adapter *padapter = precv_frame->u.hdr.adapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + u8 *pdata = precv_frame->u.hdr.rx_data; + u32 data_len = precv_frame->u.hdr.len; + u64 tmp_iv_hdr = 0; + u64 curr_pn = 0, pkt_pn = 0; + u8 key_id; + + if ((pattrib->encrypt == _AES_) && + (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) { + + tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen)); + key_id = CCMPH_2_KEYID(tmp_iv_hdr); + pkt_pn = CCMPH_2_PN(tmp_iv_hdr); + + curr_pn = le64_to_cpu(*(u64*)psecuritypriv->iv_seq[key_id]); + curr_pn &= 0x0000ffffffffffff; + + if (!VALID_PN_CHK(pkt_pn, curr_pn)) + return _FAIL; + *(u64*)psecuritypriv->iv_seq[key_id] = cpu_to_le64(pkt_pn); + } return _SUCCESS; - } -void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame); -void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame) +void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta) { #ifdef CONFIG_AP_MODE unsigned char pwrbit; u8 *ptr = precv_frame->u.hdr.rx_data; struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta = NULL; - - psta = rtw_get_stainfo(pstapriv, pattrib->src); pwrbit = GetPwrMgt(ptr); - if (psta) { - if (pwrbit) { - if (!(psta->state & WIFI_SLEEP_STATE)) { - /* psta->state |= WIFI_SLEEP_STATE; */ - /* pstapriv->sta_dz_bitmap |= BIT(psta->aid); */ - - stop_sta_xmit(padapter, psta); - - /* RTW_INFO("to sleep, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); */ - } - } else { - if (psta->state & WIFI_SLEEP_STATE) { - /* psta->state ^= WIFI_SLEEP_STATE; */ - /* pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); */ - - wakeup_sta_to_xmit(padapter, psta); + if (pwrbit) { + if (!(psta->state & WIFI_SLEEP_STATE)) { + /* psta->state |= WIFI_SLEEP_STATE; */ + /* rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */ - /* RTW_INFO("to wakeup, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); */ - } + stop_sta_xmit(padapter, psta); + /* RTW_INFO_DUMP("to sleep, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */ } + } else { + if (psta->state & WIFI_SLEEP_STATE) { + /* psta->state ^= WIFI_SLEEP_STATE; */ + /* rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */ + wakeup_sta_to_xmit(padapter, psta); + /* RTW_INFO_DUMP("to wakeup, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */ + } } - #endif } -void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame); -void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame) +void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta) { #ifdef CONFIG_AP_MODE struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta = NULL; - - psta = rtw_get_stainfo(pstapriv, pattrib->src); - - if (!psta) - return; #ifdef CONFIG_TDLS if (!(psta->tdls_sta_state & TDLS_LINKED_STATE)) { @@ -895,7 +957,7 @@ void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame) xmit_delivery_enabled_frames(padapter, psta); } else { /* issue one qos null frame with More data bit = 0 and the EOSP bit set (=1) */ - issue_qos_nulldata(padapter, psta->hwaddr, (u16)pattrib->priority, 0, 0); + issue_qos_nulldata(padapter, psta->cmn.mac_addr, (u16)pattrib->priority, 0, 0, 0); } } @@ -917,6 +979,9 @@ sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame) u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a }; #endif /* CONFIG_WFD */ struct tdls_info *ptdlsinfo = &(adapter->tdlsinfo); + u8 *ptr = precv_frame->u.hdr.rx_data; + struct sta_priv *pstapriv = &(adapter->stapriv); + struct sta_info *ptdls_sta = NULL; /* point to action field */ paction += pattrib->hdrlen @@ -934,41 +999,54 @@ sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame) return ret; } - if (ptdlsinfo->tdls_enable == _FALSE) { + if (rtw_is_tdls_enabled(adapter) == _FALSE) { RTW_INFO("recv tdls frame, " "but tdls haven't enabled\n"); ret = _FAIL; return ret; } + ptdls_sta = rtw_get_stainfo(pstapriv, get_sa(ptr)); + if (ptdls_sta == NULL) { + switch (*paction) { + case TDLS_SETUP_REQUEST: + case TDLS_DISCOVERY_REQUEST: + break; + default: + RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(get_sa(ptr)), *paction); + ret = _FAIL; + goto exit; + } + } + switch (*paction) { case TDLS_SETUP_REQUEST: - ret = On_TDLS_Setup_Req(adapter, precv_frame); + ret = On_TDLS_Setup_Req(adapter, precv_frame, ptdls_sta); break; case TDLS_SETUP_RESPONSE: - ret = On_TDLS_Setup_Rsp(adapter, precv_frame); + ret = On_TDLS_Setup_Rsp(adapter, precv_frame, ptdls_sta); break; case TDLS_SETUP_CONFIRM: - ret = On_TDLS_Setup_Cfm(adapter, precv_frame); + ret = On_TDLS_Setup_Cfm(adapter, precv_frame, ptdls_sta); break; case TDLS_TEARDOWN: - ret = On_TDLS_Teardown(adapter, precv_frame); + ret = On_TDLS_Teardown(adapter, precv_frame, ptdls_sta); break; case TDLS_DISCOVERY_REQUEST: ret = On_TDLS_Dis_Req(adapter, precv_frame); break; case TDLS_PEER_TRAFFIC_INDICATION: - ret = On_TDLS_Peer_Traffic_Indication(adapter, precv_frame); + ret = On_TDLS_Peer_Traffic_Indication(adapter, precv_frame, ptdls_sta); break; case TDLS_PEER_TRAFFIC_RESPONSE: - ret = On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame); + ret = On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame, ptdls_sta); break; #ifdef CONFIG_TDLS_CH_SW case TDLS_CHANNEL_SWITCH_REQUEST: - ret = On_TDLS_Ch_Switch_Req(adapter, precv_frame); + ret = On_TDLS_Ch_Switch_Req(adapter, precv_frame, ptdls_sta); break; case TDLS_CHANNEL_SWITCH_RESPONSE: - ret = On_TDLS_Ch_Switch_Rsp(adapter, precv_frame); + ret = On_TDLS_Ch_Switch_Rsp(adapter, precv_frame, ptdls_sta); break; #endif #ifdef CONFIG_WFD @@ -1003,7 +1081,6 @@ sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame) } #endif /* CONFIG_TDLS */ -void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta); void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta) { int sz; @@ -1028,26 +1105,29 @@ void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_in psta = prframe->u.hdr.psta; if (psta) { + u8 is_ra_bmc = IS_MCAST(pattrib->ra); + pstats = &psta->sta_stats; + pstats->last_rx_time = rtw_get_current_time(); pstats->rx_data_pkts++; pstats->rx_bytes += sz; + if (is_broadcast_mac_addr(pattrib->ra)) { + pstats->rx_data_bc_pkts++; + pstats->rx_bc_bytes += sz; + } else if (is_ra_bmc) { + pstats->rx_data_mc_pkts++; + pstats->rx_mc_bytes += sz; + } - pstats->rxratecnt[pattrib->data_rate]++; - /*record rx packets for every tid*/ - pstats->rx_data_qos_pkts[pattrib->priority]++; - -#ifdef CONFIG_TDLS - if (psta->tdls_sta_state & TDLS_LINKED_STATE) { - struct sta_info *pap_sta = NULL; - pap_sta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); - if (pap_sta) { - pstats = &pap_sta->sta_stats; - pstats->rx_data_pkts++; - pstats->rx_bytes += sz; - } + if (!is_ra_bmc) { + pstats->rxratecnt[pattrib->data_rate]++; + /*record rx packets for every tid*/ + pstats->rx_data_qos_pkts[pattrib->priority]++; } -#endif /* CONFIG_TDLS */ +#ifdef CONFIG_DYNAMIC_SOML + rtw_dyn_soml_byte_update(padapter, pattrib->data_rate, sz); +#endif } #ifdef CONFIG_CHECK_LEAVE_LPS @@ -1056,11 +1136,6 @@ void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_in } -sint sta2sta_data_frame( - _adapter *adapter, - union recv_frame *precv_frame, - struct sta_info **psta -); sint sta2sta_data_frame( _adapter *adapter, union recv_frame *precv_frame, @@ -1074,7 +1149,7 @@ sint sta2sta_data_frame( struct mlme_priv *pmlmepriv = &adapter->mlmepriv; u8 *mybssid = get_bssid(pmlmepriv); u8 *myhwaddr = adapter_mac_addr(adapter); - u8 *sta_addr = NULL; + u8 *sta_addr = pattrib->ta; sint bmcast = IS_MCAST(pattrib->dst); #ifdef CONFIG_TDLS @@ -1112,14 +1187,12 @@ sint sta2sta_data_frame( goto exit; } - sta_addr = pattrib->src; - } else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { #ifdef CONFIG_TDLS /* direct link data transfer */ if (ptdlsinfo->link_established == _TRUE) { - ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src); + *psta = ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->ta); if (ptdls_sta == NULL) { ret = _FAIL; goto exit; @@ -1154,7 +1227,7 @@ sint sta2sta_data_frame( #endif /* process UAPSD tdls sta */ - process_pwrbit_data(adapter, precv_frame); + process_pwrbit_data(adapter, precv_frame, ptdls_sta); /* if NULL-frame, check pwrbit */ if ((get_frame_sub_type(ptr) & WIFI_DATA_NULL) == WIFI_DATA_NULL) { @@ -1180,14 +1253,11 @@ sint sta2sta_data_frame( } if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) - process_wmmps_data(adapter, precv_frame); + process_wmmps_data(adapter, precv_frame, ptdls_sta); ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE); } - - sta_addr = pattrib->src; - } else #endif /* CONFIG_TDLS */ { @@ -1196,8 +1266,6 @@ sint sta2sta_data_frame( ret = _FAIL; goto exit; } - - sta_addr = pattrib->bssid; } } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { @@ -1213,8 +1281,6 @@ sint sta2sta_data_frame( ret = _FAIL; goto exit; } - - sta_addr = pattrib->src; } } else if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) { @@ -1228,17 +1294,10 @@ sint sta2sta_data_frame( } else ret = _FAIL; - - - if (bmcast) - *psta = rtw_get_bcmc_stainfo(adapter); - else - *psta = rtw_get_stainfo(pstapriv, sta_addr); /* get ap_info */ - #ifdef CONFIG_TDLS - if (ptdls_sta != NULL) - *psta = ptdls_sta; -#endif /* CONFIG_TDLS */ + if (ptdls_sta == NULL) +#endif + *psta = rtw_get_stainfo(pstapriv, sta_addr); if (*psta == NULL) { #ifdef CONFIG_MP_INCLUDED @@ -1256,10 +1315,6 @@ sint sta2sta_data_frame( } -sint ap2sta_data_frame( - _adapter *adapter, - union recv_frame *precv_frame, - struct sta_info **psta); sint ap2sta_data_frame( _adapter *adapter, union recv_frame *precv_frame, @@ -1282,19 +1337,20 @@ sint ap2sta_data_frame( /* filter packets that SA is myself or multicast or broadcast */ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s SA="MAC_FMT", myhwaddr="MAC_FMT"\n", - __FUNCTION__, MAC_ARG(pattrib->src), MAC_ARG(myhwaddr)); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" SA="MAC_FMT", myhwaddr="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->src), MAC_ARG(myhwaddr)); + #endif ret = _FAIL; goto exit; } /* da should be for me */ if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s DA="MAC_FMT"\n", __func__, MAC_ARG(pattrib->dst)); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->dst)); + #endif ret = _FAIL; goto exit; } @@ -1304,10 +1360,10 @@ sint ap2sta_data_frame( if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s BSSID="MAC_FMT", mybssid="MAC_FMT"\n", - __func__, MAC_ARG(pattrib->bssid), MAC_ARG(mybssid)); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" BSSID="MAC_FMT", mybssid="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->bssid), MAC_ARG(mybssid)); + #endif if (!bmcast) { RTW_INFO(ADPT_FMT" -issue_deauth to the nonassociated ap=" MAC_FMT " for the reason(7)\n", ADPT_ARG(adapter), MAC_ARG(pattrib->bssid)); @@ -1318,15 +1374,12 @@ sint ap2sta_data_frame( goto exit; } - if (bmcast) - *psta = rtw_get_bcmc_stainfo(adapter); - else - *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get ap_info */ - + *psta = rtw_get_stainfo(pstapriv, pattrib->ta); if (*psta == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s can't get psta under STATION_MODE ; drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under STATION_MODE ; drop pkt\n" + , FUNC_ADPT_ARG(adapter)); + #endif ret = _FAIL; goto exit; } @@ -1353,9 +1406,10 @@ sint ap2sta_data_frame( *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */ if (*psta == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under WIFI_MP_STATE ; drop pkt\n" + , FUNC_ADPT_ARG(adapter)); + #endif ret = _FAIL; goto exit; } @@ -1367,11 +1421,11 @@ sint ap2sta_data_frame( goto exit; } else { if (_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN) && (!bmcast)) { - *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */ + *psta = rtw_get_stainfo(pstapriv, pattrib->ta); if (*psta == NULL) { /* for AP multicast issue , modify by yiwei */ - static u32 send_issue_deauth_time = 0; + static systime send_issue_deauth_time = 0; /* RTW_INFO("After send deauth , %u ms has elapsed.\n", rtw_get_passing_time_ms(send_issue_deauth_time)); */ @@ -1386,9 +1440,10 @@ sint ap2sta_data_frame( } ret = _FAIL; -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s fw_state:0x%x\n", __FUNCTION__, get_fwstate(pmlmepriv)); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fw_state:0x%x\n" + , FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); + #endif } exit: @@ -1398,10 +1453,6 @@ sint ap2sta_data_frame( } -sint sta2ap_data_frame( - _adapter *adapter, - union recv_frame *precv_frame, - struct sta_info **psta); sint sta2ap_data_frame( _adapter *adapter, union recv_frame *precv_frame, @@ -1422,7 +1473,7 @@ sint sta2ap_data_frame( goto exit; } - *psta = rtw_get_stainfo(pstapriv, pattrib->src); + *psta = rtw_get_stainfo(pstapriv, pattrib->ta); if (*psta == NULL) { #ifdef CONFIG_DFS_MASTER struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); @@ -1443,10 +1494,10 @@ sint sta2ap_data_frame( goto exit; } - process_pwrbit_data(adapter, precv_frame); + process_pwrbit_data(adapter, precv_frame, *psta); if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) - process_wmmps_data(adapter, precv_frame); + process_wmmps_data(adapter, precv_frame, *psta); if (get_frame_sub_type(ptr) & BIT(6)) { /* No data, will not indicate to upper layer, temporily count it here */ @@ -1466,9 +1517,10 @@ sint sta2ap_data_frame( *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */ if (*psta == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under WIFI_MP_STATE ; drop pkt\n" + , FUNC_ADPT_ARG(adapter)); + #endif ret = _FAIL; goto exit; } @@ -1515,6 +1567,7 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) return _FAIL; /* for rx pkt statistics */ + psta->sta_stats.last_rx_time = rtw_get_current_time(); psta->sta_stats.rx_ctrl_pkts++; /* only handle ps-poll */ @@ -1524,7 +1577,7 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) u8 wmmps_ac = 0; aid = GetAid(pframe); - if (psta->aid != aid) + if (psta->cmn.aid != aid) return _FAIL; switch (pattrib->priority) { @@ -1556,7 +1609,7 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) psta->state ^= WIFI_STA_ALIVE_CHK_STATE; } - if ((psta->state & WIFI_SLEEP_STATE) && (pstapriv->sta_dz_bitmap & BIT(psta->aid))) { + if ((psta->state & WIFI_SLEEP_STATE) && (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid))) { _irqL irqL; _list *xmitframe_plist, *xmitframe_phead; struct xmit_frame *pxmitframe = NULL; @@ -1584,7 +1637,8 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) pxmitframe->attrib.triggered = 1; - /* RTW_INFO("handling ps-poll, q_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); */ + /* RTW_INFO("handling ps-poll, q_len=%d\n", psta->sleepq_len); */ + /* RTW_INFO_DUMP("handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ #if 0 _exit_critical_bh(&psta->sleep_q.lock, &irqL); @@ -1595,9 +1649,10 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) rtw_hal_xmitframe_enqueue(padapter, pxmitframe); if (psta->sleepq_len == 0) { - pstapriv->tim_bitmap &= ~BIT(psta->aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); - /* RTW_INFO("after handling ps-poll, tim=%x\n", pstapriv->tim_bitmap); */ + /* RTW_INFO("after handling ps-poll\n"); */ + /* RTW_INFO_DUMP("after handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ /* upate BCN for TIM IE */ /* update_BCNTIM(padapter); */ @@ -1612,18 +1667,18 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) _exit_critical_bh(&pxmitpriv->lock, &irqL); /* RTW_INFO("no buffered packets to xmit\n"); */ - if (pstapriv->tim_bitmap & BIT(psta->aid)) { + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) { if (psta->sleepq_len == 0) { RTW_INFO("no buffered packets to xmit\n"); /* issue nulldata with More data bit = 0 to indicate we have no buffered packets */ - issue_nulldata_in_interrupt(padapter, psta->hwaddr, 0); + issue_nulldata(padapter, psta->cmn.mac_addr, 0, 0, 0); } else { RTW_INFO("error!psta->sleepq_len=%d\n", psta->sleepq_len); psta->sleepq_len = 0; } - pstapriv->tim_bitmap &= ~BIT(psta->aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); /* upate BCN for TIM IE */ /* update_BCNTIM(padapter); */ @@ -1634,55 +1689,282 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) #endif /* CONFIG_AP_MODE */ } else if (get_frame_sub_type(pframe) == WIFI_NDPA) { #ifdef CONFIG_BEAMFORMING - beamforming_get_ndpa_frame(padapter, precv_frame); + rtw_beamforming_get_ndpa_frame(padapter, precv_frame); #endif/*CONFIG_BEAMFORMING*/ + } else if (get_frame_sub_type(pframe) == WIFI_BAR) { + rtw_process_bar_frame(padapter, precv_frame); } return _FAIL; } -union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame); -sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame); -sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) +static sint validate_mgmt_protect(_adapter *adapter, union recv_frame *precv_frame) { - /* struct mlme_priv *pmlmepriv = &adapter->mlmepriv; */ +#define DBG_VALIDATE_MGMT_PROTECT 0 +#define DBG_VALIDATE_MGMT_DEC 0 + struct security_priv *sec = &adapter->securitypriv; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_info *psta = precv_frame->u.hdr.psta; + u8 *ptr; + u8 type; + u8 subtype; + u8 is_bmc; + u8 category = 0xFF; -#if 0 - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { -#ifdef CONFIG_NATIVEAP_MLME - mgt_dispatcher(padapter, precv_frame); -#else - rtw_hostapd_mlme_rx(padapter, precv_frame); +#ifdef CONFIG_IEEE80211W + const u8 *igtk; + u16 igtk_id; + u64* ipn; #endif + + u8 *mgmt_DATA; + u32 data_len = 0; + + sint ret; + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + if (!adapter->mesh_info.mesh_auth_id) + return pattrib->privacy ? _FAIL : _SUCCESS; } else - mgt_dispatcher(padapter, precv_frame); #endif - - precv_frame = recvframe_chk_defrag(padapter, precv_frame); - if (precv_frame == NULL) { + if (SEC_IS_BIP_KEY_INSTALLED(sec) == _FALSE) return _SUCCESS; + + ptr = precv_frame->u.hdr.rx_data; + type = GetFrameType(ptr); + subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */ + is_bmc = IS_MCAST(GetAddr1Ptr(ptr)); + +#if DBG_VALIDATE_MGMT_PROTECT + if (subtype == WIFI_DEAUTH) { + RTW_INFO(FUNC_ADPT_FMT" bmc:%u, deauth, privacy:%u, encrypt:%u, bdecrypted:%u\n" + , FUNC_ADPT_ARG(adapter) + , is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted); + } else if (subtype == WIFI_DISASSOC) { + RTW_INFO(FUNC_ADPT_FMT" bmc:%u, disassoc, privacy:%u, encrypt:%u, bdecrypted:%u\n" + , FUNC_ADPT_ARG(adapter) + , is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted); + } if (subtype == WIFI_ACTION) { + if (pattrib->privacy) { + RTW_INFO(FUNC_ADPT_FMT" bmc:%u, action(?), privacy:%u, encrypt:%u, bdecrypted:%u\n" + , FUNC_ADPT_ARG(adapter) + , is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted); + } else { + RTW_INFO(FUNC_ADPT_FMT" bmc:%u, action(%u), privacy:%u, encrypt:%u, bdecrypted:%u\n" + , FUNC_ADPT_ARG(adapter), is_bmc + , *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr)) + , pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted); + } } +#endif - { - /* for rx pkt statistics */ - struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(precv_frame->u.hdr.rx_data)); - if (psta) { - psta->sta_stats.rx_mgnt_pkts++; - if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_BEACON) - psta->sta_stats.rx_beacon_pkts++; - else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ) - psta->sta_stats.rx_probereq_pkts++; - else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) { - if (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE) - psta->sta_stats.rx_probersp_pkts++; - else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)) - || is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))) - psta->sta_stats.rx_probersp_bm_pkts++; - else - psta->sta_stats.rx_probersp_uo_pkts++; + if (!pattrib->privacy) { + if (!psta || !(psta->flags & WLAN_STA_MFP)) { + /* peer is not MFP capable, no need to check */ + goto exit; + } + + if (subtype == WIFI_ACTION) + category = *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr)); + + if (is_bmc) { + /* broadcast cases */ + if (subtype == WIFI_ACTION) { + if (CATEGORY_IS_GROUP_PRIVACY(category)) { + /* drop broadcast group privacy action frame without encryption */ + #if DBG_VALIDATE_MGMT_PROTECT + RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u) w/o encrypt\n" + , FUNC_ADPT_ARG(adapter), category); + #endif + goto fail; + } + if (CATEGORY_IS_ROBUST(category)) { + /* broadcast robust action frame need BIP check */ + goto bip_verify; + } + } + if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) { + /* broadcast deauth or disassoc frame need BIP check */ + goto bip_verify; + } + goto exit; + + } else { + /* unicast cases */ + #ifdef CONFIG_IEEE80211W + if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) { + if (!MLME_IS_MESH(adapter)) { + unsigned short reason = le16_to_cpu(*(unsigned short *)(ptr + WLAN_HDR_A3_LEN)); + + #if DBG_VALIDATE_MGMT_PROTECT + RTW_INFO(FUNC_ADPT_FMT" unicast %s, reason=%d w/o encrypt\n" + , FUNC_ADPT_ARG(adapter), subtype == WIFI_DEAUTH ? "deauth" : "disassoc", reason); + #endif + if (reason == 6 || reason == 7) { + /* issue sa query request */ + issue_action_SA_Query(adapter, psta->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY); + } + } + goto fail; + } + #endif + + if (subtype == WIFI_ACTION && CATEGORY_IS_ROBUST(category)) { + if (psta->bpairwise_key_installed == _TRUE) { + #if DBG_VALIDATE_MGMT_PROTECT + RTW_INFO(FUNC_ADPT_FMT" unicast robust action(%d) w/o encrypt\n" + , FUNC_ADPT_ARG(adapter), category); + #endif + goto fail; + } } + goto exit; + } + +bip_verify: +#ifdef CONFIG_IEEE80211W + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + if (psta->igtk_bmp) { + igtk = psta->igtk.skey; + igtk_id = psta->igtk_id; + ipn = &psta->igtk_pn.val; + } else { + /* mesh MFP without IGTK */ + goto exit; + } + } else + #endif + { + igtk = sec->dot11wBIPKey[sec->dot11wBIPKeyid].skey; + igtk_id = sec->dot11wBIPKeyid; + ipn = &sec->dot11wBIPrxpn.val; + } + + /* verify BIP MME IE */ + ret = rtw_BIP_verify(adapter + , get_recvframe_data(precv_frame) + , get_recvframe_len(precv_frame) + , igtk, igtk_id, ipn); + if (ret == _FAIL) { + /* RTW_INFO("802.11w BIP verify fail\n"); */ + goto fail; + + } else if (ret == RTW_RX_HANDLED) { + #if DBG_VALIDATE_MGMT_PROTECT + RTW_INFO(FUNC_ADPT_FMT" none protected packet\n", FUNC_ADPT_ARG(adapter)); + #endif + goto fail; + } +#endif /* CONFIG_IEEE80211W */ + goto exit; + } + + /* cases to decrypt mgmt frame */ + pattrib->bdecrypted = 0; + pattrib->encrypt = _AES_; + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* set iv and icv length */ + SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); + + /* actual management data frame body */ + data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; + mgmt_DATA = rtw_zmalloc(data_len); + if (mgmt_DATA == NULL) { + RTW_INFO(FUNC_ADPT_FMT" mgmt allocate fail !!!!!!!!!\n", FUNC_ADPT_ARG(adapter)); + goto fail; + } + +#if DBG_VALIDATE_MGMT_DEC + /* dump the packet content before decrypt */ + { + int pp; + + printk("pattrib->pktlen = %d =>", pattrib->pkt_len); + for (pp = 0; pp < pattrib->pkt_len; pp++) + printk(" %02x ", ptr[pp]); + printk("\n"); + } +#endif + + precv_frame = decryptor(adapter, precv_frame); + /* save actual management data frame body */ + _rtw_memcpy(mgmt_DATA, ptr + pattrib->hdrlen + pattrib->iv_len, data_len); + /* overwrite the iv field */ + _rtw_memcpy(ptr + pattrib->hdrlen, mgmt_DATA, data_len); + /* remove the iv and icv length */ + pattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len; + rtw_mfree(mgmt_DATA, data_len); + +#if DBG_VALIDATE_MGMT_DEC + /* print packet content after decryption */ + { + int pp; + + printk("after decryption pattrib->pktlen = %d @@=>", pattrib->pkt_len); + for (pp = 0; pp < pattrib->pkt_len; pp++) + printk(" %02x ", ptr[pp]); + printk("\n"); + } +#endif + + if (!precv_frame) { + #if DBG_VALIDATE_MGMT_PROTECT + RTW_INFO(FUNC_ADPT_FMT" mgmt descrypt fail !!!!!!!!!\n", FUNC_ADPT_ARG(adapter)); + #endif + goto fail; + } + +exit: + return _SUCCESS; + +fail: + return _FAIL; + +} +#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */ + +union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame); + +sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) +{ + struct sta_info *psta = precv_frame->u.hdr.psta + = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(precv_frame->u.hdr.rx_data)); + +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) + if (validate_mgmt_protect(padapter, precv_frame) == _FAIL) { + DBG_COUNTER(padapter->rx_logs.core_rx_pre_mgmt_err_80211w); + goto exit; + } +#endif + + precv_frame = recvframe_chk_defrag(padapter, precv_frame); + if (precv_frame == NULL) + return _SUCCESS; + + /* for rx pkt statistics */ + if (psta) { + psta->sta_stats.last_rx_time = rtw_get_current_time(); + psta->sta_stats.rx_mgnt_pkts++; + if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_BEACON) + psta->sta_stats.rx_beacon_pkts++; + else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ) + psta->sta_stats.rx_probereq_pkts++; + else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) { + if (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE) + psta->sta_stats.rx_probersp_pkts++; + else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)) + || is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))) + psta->sta_stats.rx_probersp_bm_pkts++; + else + psta->sta_stats.rx_probersp_uo_pkts++; } } @@ -1735,15 +2017,14 @@ sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) #endif mgt_dispatcher(padapter, precv_frame); +exit: return _SUCCESS; } -sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame); sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) { - u8 bretry; - u8 *psa, *pda, *pbssid; + u8 bretry, a4_shift; struct sta_info *psta = NULL; u8 *ptr = precv_frame->u.hdr.rx_data; struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; @@ -1751,114 +2032,139 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) struct security_priv *psecuritypriv = &adapter->securitypriv; sint ret = _SUCCESS; - bretry = GetRetry(ptr); - pda = get_da(ptr); - psa = get_sa(ptr); - pbssid = get_hdr_bssid(ptr); - - if (pbssid == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s pbssid == NULL\n", __func__); -#endif - ret = _FAIL; - goto exit; - } + a4_shift = (pattrib->to_fr_ds == 3) ? ETH_ALEN : 0; - _rtw_memcpy(pattrib->dst, pda, ETH_ALEN); - _rtw_memcpy(pattrib->src, psa, ETH_ALEN); + /* some address fields are different when using AMSDU */ + if (pattrib->qos) + pattrib->amsdu = GetAMsdu(ptr + WLAN_HDR_A3_LEN + a4_shift); + else + pattrib->amsdu = 0; - _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + ret = rtw_mesh_rx_data_validate_hdr(adapter, precv_frame, &psta); + goto pre_validate_status_chk; + } +#endif switch (pattrib->to_fr_ds) { case 0: - _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); - _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); ret = sta2sta_data_frame(adapter, precv_frame, &psta); break; case 1: - _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); - _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN); + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, GetAddr3Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, get_addr2_ptr(ptr), ETH_ALEN); ret = ap2sta_data_frame(adapter, precv_frame, &psta); break; case 2: - _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); - _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); - ret = sta2ap_data_frame(adapter, precv_frame, &psta); - break; - - case 3: _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); - ret = _FAIL; + _rtw_memcpy(pattrib->dst, GetAddr3Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, GetAddr1Ptr(ptr), ETH_ALEN); + ret = sta2ap_data_frame(adapter, precv_frame, &psta); break; + case 3: default: + /* WDS is not supported */ ret = _FAIL; break; - } +pre_validate_status_chk: if (ret == _FAIL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s case:%d, res:%d\n", __FUNCTION__, pattrib->to_fr_ds, ret); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" case:%d, res:%d, ra="MAC_FMT", ta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), pattrib->to_fr_ds, ret, MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr))); + #endif goto exit; } else if (ret == RTW_RX_HANDLED) goto exit; if (psta == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s psta == NULL\n", __func__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" psta == NULL, ra="MAC_FMT", ta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr))); + #endif ret = _FAIL; goto exit; } - /* psta->rssi = prxcmd->rssi; */ - /* psta->signal_quality= prxcmd->sq; */ precv_frame->u.hdr.psta = psta; - - pattrib->amsdu = 0; pattrib->ack_policy = 0; + /* parsing QC field */ if (pattrib->qos == 1) { - pattrib->priority = GetPriority((ptr + 24)); - pattrib->ack_policy = GetAckpolicy((ptr + 24)); - pattrib->amsdu = GetAMsdu((ptr + 24)); - pattrib->hdrlen = pattrib->to_fr_ds == 3 ? 32 : 26; - + pattrib->priority = GetPriority((ptr + WLAN_HDR_A3_LEN + a4_shift)); /* point to Qos field*/ + pattrib->ack_policy = GetAckpolicy((ptr + WLAN_HDR_A3_LEN + a4_shift)); + pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN + a4_shift; if (pattrib->priority != 0 && pattrib->priority != 3) adapter->recvpriv.is_any_non_be_pkts = _TRUE; else adapter->recvpriv.is_any_non_be_pkts = _FALSE; } else { pattrib->priority = 0; - pattrib->hdrlen = pattrib->to_fr_ds == 3 ? 30 : 24; + pattrib->hdrlen = WLAN_HDR_A3_LEN + a4_shift; } if (pattrib->order) /* HT-CTRL 11n */ pattrib->hdrlen += 4; - precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority]; - /* decache, drop duplicate recv packets */ - if (recv_decache(precv_frame, bretry, &psta->sta_recvpriv.rxcache) == _FAIL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s recv_decache return _FAIL\n", __func__); -#endif - ret = _FAIL; - goto exit; + if (!IS_MCAST(pattrib->ra)) { + precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority]; + if (recv_decache(precv_frame, psta->sta_recvpriv.rxcache.tid_rxseq) == _FAIL) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_decache uc return _FAIL for sta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + #endif + ret = _FAIL; + goto exit; + } + if (recv_ucast_pn_decache(precv_frame) == _FAIL) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_ucast_pn_decache return _FAIL for sta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + #endif + ret = _FAIL; + goto exit; + } + } else { + precv_frame->u.hdr.preorder_ctrl = NULL; + if (recv_decache(precv_frame, psta->sta_recvpriv.bmc_tid_rxseq) == _FAIL) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_decache bmc return _FAIL for sta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + #endif + ret = _FAIL; + goto exit; + } + if (recv_bcast_pn_decache(precv_frame) == _FAIL) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_bcast_pn_decache return _FAIL for sta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + #endif + ret = _FAIL; + goto exit; + } } if (pattrib->privacy) { - - #ifdef CONFIG_TDLS if ((psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta->dot118021XPrivacy == _AES_)) pattrib->encrypt = psta->dot118021XPrivacy; @@ -1873,128 +2179,16 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) pattrib->iv_len = pattrib->icv_len = 0; } -exit: - - - return ret; -} - -#ifdef CONFIG_IEEE80211W -static sint validate_80211w_mgmt(_adapter *adapter, union recv_frame *precv_frame) -{ - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - u8 *ptr = precv_frame->u.hdr.rx_data; - struct sta_info *psta; - struct sta_priv *pstapriv = &adapter->stapriv; - u8 type; - u8 subtype; - - type = GetFrameType(ptr); - subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */ - - if (adapter->securitypriv.binstallBIPkey == _TRUE) { - /* unicast management frame decrypt */ - if (pattrib->privacy && !(IS_MCAST(GetAddr1Ptr(ptr))) && - (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || subtype == WIFI_ACTION)) { - u8 *ppp, *mgmt_DATA; - u32 data_len = 0; - ppp = get_addr2_ptr(ptr); - - pattrib->bdecrypted = 0; - pattrib->encrypt = _AES_; - pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); - /* set iv and icv length */ - SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); - _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); - /* actual management data frame body */ - data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; - mgmt_DATA = rtw_zmalloc(data_len); - if (mgmt_DATA == NULL) { - RTW_INFO("%s mgmt allocate fail !!!!!!!!!\n", __FUNCTION__); - goto validate_80211w_fail; - } -#if 0 - /* dump the packet content before decrypt */ - { - int pp; - printk("pattrib->pktlen = %d =>", pattrib->pkt_len); - for (pp = 0; pp < pattrib->pkt_len; pp++) - printk(" %02x ", ptr[pp]); - printk("\n"); - } -#endif - - precv_frame = decryptor(adapter, precv_frame); - /* save actual management data frame body */ - _rtw_memcpy(mgmt_DATA, ptr + pattrib->hdrlen + pattrib->iv_len, data_len); - /* overwrite the iv field */ - _rtw_memcpy(ptr + pattrib->hdrlen, mgmt_DATA, data_len); - /* remove the iv and icv length */ - pattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len; - rtw_mfree(mgmt_DATA, data_len); -#if 0 - /* print packet content after decryption */ - { - int pp; - printk("after decryption pattrib->pktlen = %d @@=>", pattrib->pkt_len); - for (pp = 0; pp < pattrib->pkt_len; pp++) - printk(" %02x ", ptr[pp]); - printk("\n"); - } +#ifdef CONFIG_RTW_MESH + if (!pattrib->amsdu + && pattrib->mesh_ctrl_present + && (!pattrib->encrypt || pattrib->bdecrypted)) + ret = rtw_mesh_rx_validate_mctrl_non_amsdu(adapter, precv_frame); #endif - if (!precv_frame) { - RTW_INFO("%s mgmt descrypt fail !!!!!!!!!\n", __FUNCTION__); - goto validate_80211w_fail; - } - } else if (IS_MCAST(GetAddr1Ptr(ptr)) && - (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC)) { - sint BIP_ret = _SUCCESS; - /* verify BIP MME IE of broadcast/multicast de-auth/disassoc packet */ - BIP_ret = rtw_BIP_verify(adapter, (u8 *)precv_frame); - if (BIP_ret == _FAIL) { - /* RTW_INFO("802.11w BIP verify fail\n"); */ - goto validate_80211w_fail; - } else if (BIP_ret == RTW_RX_HANDLED) { - RTW_INFO("802.11w recv none protected packet\n"); - /* drop pkt, don't issue sa query request */ - /* issue_action_SA_Query(adapter, NULL, 0, 0, 0); */ - goto validate_80211w_fail; - } - } /* 802.11w protect */ - else { - psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(ptr)); - - if (subtype == WIFI_ACTION && psta && psta->bpairwise_key_installed == _TRUE) { - /* according 802.11-2012 standard, these five types are not robust types */ - if (ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_PUBLIC && - ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_HT && - ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_UNPROTECTED_WNM && - ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_SELF_PROTECTED && - ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_P2P) { - RTW_INFO("action frame category=%d should robust\n", ptr[WLAN_HDR_A3_LEN]); - goto validate_80211w_fail; - } - } else if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) { - unsigned short reason; - reason = le16_to_cpu(*(unsigned short *)(ptr + WLAN_HDR_A3_LEN)); - RTW_INFO("802.11w recv none protected packet, reason=%d\n", reason); - if (reason == 6 || reason == 7) { - /* issue sa query request */ - issue_action_SA_Query(adapter, NULL, 0, 0, IEEE80211W_RIGHT_KEY); - } - goto validate_80211w_fail; - } - } - } - return _SUCCESS; - -validate_80211w_fail: - return _FAIL; +exit: + return ret; } -#endif /* CONFIG_IEEE80211W */ static inline void dump_rx_packet(u8 *ptr) { @@ -2019,6 +2213,7 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) sint retval = _SUCCESS; struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct recv_priv *precvpriv = &adapter->recvpriv; u8 *ptr = precv_frame->u.hdr.rx_data; u8 ver = (unsigned char)(*ptr) & 0x3 ; @@ -2106,14 +2301,6 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) switch (type) { case WIFI_MGT_TYPE: /* mgnt */ DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt); -#ifdef CONFIG_IEEE80211W - if (validate_80211w_mgmt(adapter, precv_frame) == _FAIL) { - retval = _FAIL; - DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err_80211w); - break; - } -#endif /* CONFIG_IEEE80211W */ - retval = validate_recv_mgnt_frame(adapter, precv_frame); if (retval == _FAIL) { DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err); @@ -2163,30 +2350,32 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) pattrib->qos = (subtype & BIT(7)) ? 1 : 0; retval = validate_recv_data_frame(adapter, precv_frame); if (retval == _FAIL) { - struct recv_priv *precvpriv = &adapter->recvpriv; - precvpriv->rx_drop++; + precvpriv->dbg_rx_drop_count++; DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_err); } else if (retval == _SUCCESS) { -#ifdef DBG_RX_DUMP_EAP - u8 bDumpRxPkt; - u16 eth_type; - - /* dump eapol */ - rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt)); - /* get ether_type */ - _rtw_memcpy(ð_type, ptr + pattrib->hdrlen + pattrib->iv_len + LLC_HEADER_SIZE, 2); - eth_type = ntohs((unsigned short) eth_type); - if ((bDumpRxPkt == 4) && (eth_type == 0x888e)) - dump_rx_packet(ptr); -#endif + #ifdef DBG_RX_DUMP_EAP + if (!pattrib->encrypt || pattrib->bdecrypted) { + u8 bDumpRxPkt; + u16 eth_type; + + /* dump eapol */ + rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt)); + /* get ether_type */ + _rtw_memcpy(ð_type, ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + LLC_HEADER_SIZE, 2); + eth_type = ntohs((unsigned short) eth_type); + if ((bDumpRxPkt == 4) && (eth_type == 0x888e)) + dump_rx_packet(ptr); + } + #endif } else DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_handled); break; default: DBG_COUNTER(adapter->rx_logs.core_rx_pre_unknown); -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME validate_recv_data_frame fail! type=0x%x\n", type); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fail! type=0x%x\n" + , FUNC_ADPT_ARG(adapter), type); + #endif retval = _FAIL; break; } @@ -2200,8 +2389,6 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) /* remove the wlanhdr and add the eth_hdr */ #if 1 - -sint wlanhdr_to_ethhdr(union recv_frame *precvframe); sint wlanhdr_to_ethhdr(union recv_frame *precvframe) { sint rmv_len; @@ -2221,8 +2408,8 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) if (pattrib->encrypt) recvframe_pull_tail(precvframe, pattrib->icv_len); - psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len); - psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE; + psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib)); + psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + SNAP_SIZE; /* convert hdr + possible LLC headers into Ethernet header */ /* eth_type = (psnap_type[0] << 8) | psnap_type[1]; */ if ((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) && @@ -2237,7 +2424,7 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) bsnaphdr = _FALSE; } - rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0); + rmv_len = pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + (bsnaphdr ? SNAP_SIZE : 0); len = precvframe->u.hdr.len - rmv_len; @@ -2245,37 +2432,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */ pattrib->eth_type = eth_type; -#ifdef CONFIG_AUTO_AP_MODE - if (0x8899 == pattrib->eth_type) { - struct sta_info *psta = precvframe->u.hdr.psta; - - RTW_INFO("wlan rx: got eth_type=0x%x\n", pattrib->eth_type); - - if (psta && psta->isrc && psta->pid > 0) { - u16 rx_pid; - - rx_pid = *(u16 *)(ptr + rmv_len + 2); - - RTW_INFO("wlan rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n", - rx_pid, MAC_ARG(psta->hwaddr), psta->pid); - - if (rx_pid == psta->pid) { - int i; - u16 len = *(u16 *)(ptr + rmv_len + 4); - /* u16 ctrl_type = *(u16*)(ptr+rmv_len+6); */ - - /* RTW_INFO("RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type); */ - RTW_INFO("RC: len=0x%x\n", len); - - for (i = 0; i < len; i++) - RTW_INFO("0x%x\n", *(ptr + rmv_len + 6 + i)); - /* RTW_INFO("0x%x\n", *(ptr+rmv_len+8+i)); */ - - RTW_INFO("RC-end\n"); - } - } - } -#endif /* CONFIG_AUTO_AP_MODE */ if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)) { ptr += rmv_len ; @@ -2307,6 +2463,8 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) len = htons(len); _rtw_memcpy(ptr + 12, &len, 2); } + + rtw_rframe_set_os_pkt(precvframe); } exiting: @@ -2682,8 +2840,144 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec } +static int rtw_recv_indicatepkt_check(union recv_frame *rframe, u8 *ehdr_pos, u32 pkt_len) +{ + _adapter *adapter = rframe->u.hdr.adapter; + struct recv_priv *recvpriv = &adapter->recvpriv; + struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos; + int ret = _FAIL; + +#ifdef CONFIG_WAPI_SUPPORT + if (rtw_wapi_check_for_drop(adapter, rframe, ehdr_pos)) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_wapi_check_for_drop\n" + , FUNC_ADPT_ARG(adapter)); + #endif + goto exit; + } +#endif + + if (rframe->u.hdr.psta) + rtw_st_ctl_rx(rframe->u.hdr.psta, ehdr_pos); + + if (ntohs(ehdr->h_proto) == 0x888e) + RTW_PRINT("recv eapol packet\n"); + + if (recvpriv->sink_udpport > 0) + rtw_sink_rtp_seq_dbg(adapter, ehdr_pos); + +#ifdef DBG_UDP_PKT_LOSE_11AC + #define PAYLOAD_LEN_LOC_OF_IP_HDR 0x10 /*ethernet payload length location of ip header (DA + SA+eth_type+(version&hdr_len)) */ + + if (ntohs(ehdr->h_proto) == ETH_P_ARP) { + /* ARP Payload length will be 42bytes or 42+18(tailer)=60bytes*/ + if (pkt_len != 42 && pkt_len != 60) + RTW_INFO("Error !!%s,ARP Payload length %u not correct\n" , __func__ , pkt_len); + } else if (ntohs(ehdr->h_proto) == ETH_P_IP) { + if (be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR))) != (pkt_len) - ETH_HLEN) { + RTW_INFO("Error !!%s,Payload length not correct\n" , __func__); + RTW_INFO("%s, IP header describe Total length=%u\n" , __func__ , be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR)))); + RTW_INFO("%s, Pkt real length=%u\n" , __func__ , (pkt_len) - ETH_HLEN); + } + } +#endif + +#ifdef CONFIG_AUTO_AP_MODE + if (ntohs(ehdr->h_proto) == 0x8899) + rtw_auto_ap_rx_msg_dump(adapter, rframe, ehdr_pos); +#endif + + ret = _SUCCESS; + +exit: + return ret; +} + +static void recv_free_fwd_resource(_adapter *adapter, struct xmit_frame *fwd_frame, _list *b2u_list) +{ + struct xmit_priv *xmitpriv = &adapter->xmitpriv; + + if (fwd_frame) + rtw_free_xmitframe(xmitpriv, fwd_frame); + +#ifdef CONFIG_RTW_MESH +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (!rtw_is_list_empty(b2u_list)) { + struct xmit_frame *b2uframe; + _list *list; + + list = get_next(b2u_list); + while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) { + b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&b2uframe->list); + rtw_free_xmitframe(xmitpriv, b2uframe); + } + } +#endif +#endif /* CONFIG_RTW_MESH */ +} + +static void recv_fwd_pkt_hdl(_adapter *adapter, _pkt *pkt + , u8 act, struct xmit_frame *fwd_frame, _list *b2u_list) +{ + struct xmit_priv *xmitpriv = &adapter->xmitpriv; + _pkt *fwd_pkt = pkt; + + if (act & RTW_RX_MSDU_ACT_INDICATE) { + fwd_pkt = rtw_os_pkt_copy(pkt); + if (!fwd_pkt) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_pkt_copy fail\n", __func__); + #endif + recv_free_fwd_resource(adapter, fwd_frame, b2u_list); + goto exit; + } + } + +#ifdef CONFIG_RTW_MESH +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (!rtw_is_list_empty(b2u_list)) { + _list *list = get_next(b2u_list); + struct xmit_frame *b2uframe; + + while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) { + b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&b2uframe->list); + + if (!fwd_frame && rtw_is_list_empty(b2u_list)) /* the last fwd_pkt */ + b2uframe->pkt = fwd_pkt; + else + b2uframe->pkt = rtw_os_pkt_copy(fwd_pkt); + if (!b2uframe->pkt) { + rtw_free_xmitframe(xmitpriv, b2uframe); + continue; + } + + rtw_xmit_posthandle(adapter, b2uframe, b2uframe->pkt); + } + } +#endif +#endif /* CONFIG_RTW_MESH */ + + if (fwd_frame) { + fwd_frame->pkt = fwd_pkt; + if (rtw_xmit_posthandle(adapter, fwd_frame, fwd_pkt) < 0) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit_posthandle fail\n", __func__); + #endif + xmitpriv->tx_drop++; + } + } + +exit: + return; +} + int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) { + struct rx_pkt_attrib *rattrib = &prframe->u.hdr.attrib; int a_len, padding_len; u16 nSubframe_Length; u8 nr_subframes, i; @@ -2691,43 +2985,96 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) _pkt *sub_pkt, *subframes[MAX_SUBFRAME_COUNT]; struct recv_priv *precvpriv = &padapter->recvpriv; _queue *pfree_recv_queue = &(precvpriv->free_recv_queue); + const u8 *da, *sa; + int act; + struct xmit_frame *fwd_frame; + _list b2u_list; + u8 mctrl_len = 0; int ret = _SUCCESS; nr_subframes = 0; - recvframe_pull(prframe, prframe->u.hdr.attrib.hdrlen); + recvframe_pull(prframe, rattrib->hdrlen); - if (prframe->u.hdr.attrib.iv_len > 0) - recvframe_pull(prframe, prframe->u.hdr.attrib.iv_len); + if (rattrib->iv_len > 0) + recvframe_pull(prframe, rattrib->iv_len); a_len = prframe->u.hdr.len; - pdata = prframe->u.hdr.rx_data; while (a_len > ETH_HLEN) { - /* Offset 12 denote 2 mac address */ nSubframe_Length = RTW_GET_BE16(pdata + 12); - if (a_len < (ETHERNET_HEADER_SIZE + nSubframe_Length)) { RTW_INFO("nRemain_Length is %d and nSubframe_Length is : %d\n", a_len, nSubframe_Length); break; } - sub_pkt = rtw_os_alloc_msdu_pkt(prframe, nSubframe_Length, pdata); + act = RTW_RX_MSDU_ACT_INDICATE; + fwd_frame = NULL; + + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + u8 *mda = pdata, *msa = pdata + ETH_ALEN; + struct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)(pdata + ETH_HLEN); + int v_ret; + + v_ret = rtw_mesh_rx_data_validate_mctrl(padapter, prframe + , mctrl, mda, msa, &mctrl_len, &da, &sa); + if (v_ret != _SUCCESS) + goto move_to_next; + + act = rtw_mesh_rx_msdu_act_check(prframe + , mda, msa, da, sa, mctrl, &fwd_frame, &b2u_list); + } else + #endif + { + da = pdata; + sa = pdata + ETH_ALEN; + } + + if (!act) + goto move_to_next; + + rtw_led_rx_control(padapter, da); + + sub_pkt = rtw_os_alloc_msdu_pkt(prframe, da, sa + , pdata + ETH_HLEN + mctrl_len, nSubframe_Length - mctrl_len); if (sub_pkt == NULL) { - RTW_INFO("%s(): allocate sub packet fail !!!\n", __FUNCTION__); + if (act & RTW_RX_MSDU_ACT_INDICATE) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__); + #endif + } + if (act & RTW_RX_MSDU_ACT_FORWARD) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__); + #endif + recv_free_fwd_resource(padapter, fwd_frame, &b2u_list); + } break; } + #ifdef CONFIG_RTW_MESH + if (act & RTW_RX_MSDU_ACT_FORWARD) { + recv_fwd_pkt_hdl(padapter, sub_pkt, act, fwd_frame, &b2u_list); + if (!(act & RTW_RX_MSDU_ACT_INDICATE)) + goto move_to_next; + } + #endif + + if (rtw_recv_indicatepkt_check(prframe, rtw_os_pkt_data(sub_pkt), rtw_os_pkt_len(sub_pkt)) == _SUCCESS) + subframes[nr_subframes++] = sub_pkt; + else + rtw_os_pkt_free(sub_pkt); + +move_to_next: /* move the data point to data content */ pdata += ETH_HLEN; a_len -= ETH_HLEN; - subframes[nr_subframes++] = sub_pkt; - if (nr_subframes >= MAX_SUBFRAME_COUNT) { - RTW_INFO("ParseSubframe(): Too many Subframes! Packets dropped!\n"); + RTW_WARN("ParseSubframe(): Too many Subframes! Packets dropped!\n"); break; } @@ -2752,7 +3099,7 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) /* Indicat the packets to upper layer */ if (sub_pkt) - rtw_os_recv_indicate_pkt(padapter, sub_pkt, &prframe->u.hdr.attrib); + rtw_os_recv_indicate_pkt(padapter, sub_pkt, prframe); } prframe->u.hdr.len = 0; @@ -2761,75 +3108,164 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) return ret; } -int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num); -int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num) +static int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe) +{ + struct recv_priv *precvpriv = &padapter->recvpriv; + _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + int ret; + + if (pattrib->amsdu) { + ret = amsdu_to_msdu(padapter, prframe); + if (ret != _SUCCESS) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" amsdu_to_msdu fail\n" + , FUNC_ADPT_ARG(padapter)); + #endif + rtw_free_recvframe(prframe, pfree_recv_queue); + goto exit; + } + } else { + int act = RTW_RX_MSDU_ACT_INDICATE; + struct xmit_frame *fwd_frame = NULL; + _list b2u_list; + + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter) && pattrib->mesh_ctrl_present) { + act = rtw_mesh_rx_msdu_act_check(prframe + , pattrib->mda, pattrib->msa + , pattrib->dst, pattrib->src + , (struct rtw_ieee80211s_hdr *)(get_recvframe_data(prframe) + pattrib->hdrlen + pattrib->iv_len) + , &fwd_frame, &b2u_list); + } + #endif + + if (!act) { + rtw_free_recvframe(prframe, pfree_recv_queue); + ret = _FAIL; + goto exit; + } + + rtw_led_rx_control(padapter, pattrib->dst); + + ret = wlanhdr_to_ethhdr(prframe); + if (ret != _SUCCESS) { + if (act & RTW_RX_MSDU_ACT_INDICATE) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n" + , FUNC_ADPT_ARG(padapter)); + #endif + } + if (act & RTW_RX_MSDU_ACT_FORWARD) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s wlanhdr_to_ethhdr fail\n", __func__); + #endif + recv_free_fwd_resource(padapter, fwd_frame, &b2u_list); + } + rtw_free_recvframe(prframe, pfree_recv_queue); + goto exit; + } + + #ifdef CONFIG_RTW_MESH + if (act & RTW_RX_MSDU_ACT_FORWARD) { + recv_fwd_pkt_hdl(padapter, prframe->u.hdr.pkt, act, fwd_frame, &b2u_list); + if (!(act & RTW_RX_MSDU_ACT_INDICATE)) { + prframe->u.hdr.pkt = NULL; + rtw_free_recvframe(prframe, pfree_recv_queue); + goto exit; + } + } + #endif + + if (!RTW_CANNOT_RUN(padapter)) { + ret = rtw_recv_indicatepkt_check(prframe + , get_recvframe_data(prframe), get_recvframe_len(prframe)); + if (ret != _SUCCESS) { + rtw_free_recvframe(prframe, pfree_recv_queue); + goto exit; + } + + /* indicate this recv_frame */ + ret = rtw_recv_indicatepkt(padapter, prframe); + if (ret != _SUCCESS) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_recv_indicatepkt fail!\n" + , FUNC_ADPT_ARG(padapter)); + #endif + goto exit; + } + } else { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DS:%u SR:%u\n" + , FUNC_ADPT_ARG(padapter) + , rtw_is_drv_stopped(padapter) + , rtw_is_surprise_removed(padapter)); + #endif + ret = _SUCCESS; /* don't count as packet drop */ + rtw_free_recvframe(prframe, pfree_recv_queue); + } + } + +exit: + return ret; +} + +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) +static int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num) { PADAPTER padapter = preorder_ctrl->padapter; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct recv_priv *precvpriv = &padapter->recvpriv; u8 wsize = preorder_ctrl->wsize_b; u16 wend = (preorder_ctrl->indicate_seq + wsize - 1) & 0xFFF; /* % 4096; */ /* Rx Reorder initialize condition. */ if (preorder_ctrl->indicate_seq == 0xFFFF) { preorder_ctrl->indicate_seq = seq_num; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d init IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, seq_num); -#endif - - /* DbgPrint("check_indicate_seq, 1st->indicate_seq=%d\n", precvpriv->indicate_seq); */ + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_INIT indicate_seq:%d, seq_num:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num); + #endif } - /* DbgPrint("enter->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ - /* Drop out the packet which SeqNum is smaller than WinStart */ if (SN_LESS(seq_num, preorder_ctrl->indicate_seq)) { - /* DbgPrint("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ - -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("%s IndicateSeq: %d > NewSeq: %d\n", __FUNCTION__, - preorder_ctrl->indicate_seq, seq_num); -#endif - - + #ifdef DBG_RX_DROP_FRAME + RTW_INFO(FUNC_ADPT_FMT" tid:%u indicate_seq:%d > seq_num:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num); + #endif return _FALSE; } - /* */ - /* Sliding window manipulation. Conditions includes: */ - /* 1. Incoming SeqNum is equal to WinStart =>Window shift 1 */ - /* 2. Incoming SeqNum is larger than the WinEnd => Window shift N */ - /* */ + /* + * Sliding window manipulation. Conditions includes: + * 1. Incoming SeqNum is equal to WinStart =>Window shift 1 + * 2. Incoming SeqNum is larger than the WinEnd => Window shift N + */ if (SN_EQUAL(seq_num, preorder_ctrl->indicate_seq)) { preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num); + #endif -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d SN_EQUAL IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, seq_num); -#endif } else if (SN_LESS(wend, seq_num)) { - /* DbgPrint("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ - /* boundary situation, when seq_num cross 0xFFF */ if (seq_num >= (wsize - 1)) preorder_ctrl->indicate_seq = seq_num + 1 - wsize; else preorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1; - pdbgpriv->dbg_rx_ampdu_window_shift_cnt++; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d SN_LESS(wend, seq_num) IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, seq_num); -#endif - } - /* DbgPrint("exit->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ + precvpriv->dbg_rx_ampdu_window_shift_cnt++; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_LESS(wend, seq_num) indicate_seq:%d, seq_num:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num); + #endif + } return _TRUE; } -int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe); -int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe) +static int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe) { struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; @@ -2881,17 +3317,20 @@ int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union rec } -void recv_indicatepkts_pkt_loss_cnt(struct debug_priv *pdbgpriv, u64 prev_seq, u64 current_seq); -void recv_indicatepkts_pkt_loss_cnt(struct debug_priv *pdbgpriv, u64 prev_seq, u64 current_seq) +static void recv_indicatepkts_pkt_loss_cnt(_adapter *padapter, u64 prev_seq, u64 current_seq) { - if (current_seq < prev_seq) - pdbgpriv->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq); + struct recv_priv *precvpriv = &padapter->recvpriv; - else - pdbgpriv->dbg_rx_ampdu_loss_count += (current_seq - prev_seq); + if (current_seq < prev_seq) { + precvpriv->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq); + precvpriv->rx_drop += (4096 + current_seq - prev_seq); + } else { + precvpriv->dbg_rx_ampdu_loss_count += (current_seq - prev_seq); + precvpriv->rx_drop += (current_seq - prev_seq); + } } -int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced); -int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced) + +static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced) { /* _irqL irql; */ _list *phead, *plist; @@ -2901,8 +3340,6 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre int bPktInBuf = _FALSE; struct recv_priv *precvpriv = &padapter->recvpriv; _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_in_oder); @@ -2922,7 +3359,7 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre /* Handling some condition for forced indicate case. */ if (bforced == _TRUE) { - pdbgpriv->dbg_rx_ampdu_forced_indicate_count++; + precvpriv->dbg_rx_ampdu_forced_indicate_count++; if (rtw_is_list_empty(phead)) { /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ /* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */ @@ -2932,13 +3369,12 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre prframe = LIST_CONTAINOR(plist, union recv_frame, u); pattrib = &prframe->u.hdr.attrib; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, pattrib->seq_num); -#endif - recv_indicatepkts_pkt_loss_cnt(pdbgpriv, preorder_ctrl->indicate_seq, pattrib->seq_num); + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u FORCE indicate_seq:%d, seq_num:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num); + #endif + recv_indicatepkts_pkt_loss_cnt(padapter, preorder_ctrl->indicate_seq, pattrib->seq_num); preorder_ctrl->indicate_seq = pattrib->seq_num; - } /* Prepare indication list and indication. */ @@ -2964,10 +3400,10 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre if (SN_EQUAL(preorder_ctrl->indicate_seq, pattrib->seq_num)) { preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, pattrib->seq_num); -#endif + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num); + #endif } #if 0 @@ -2991,19 +3427,8 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre /* indicate this recv_frame */ /* DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num); */ - if (!pattrib->amsdu) { - /* RTW_INFO("recv_indicatepkts_in_order, amsdu!=1, indicate_seq=%d, seq_num=%d\n", preorder_ctrl->indicate_seq, pattrib->seq_num); */ - - if (!RTW_CANNOT_RUN(padapter)) - rtw_recv_indicatepkt(padapter, prframe);/*indicate this recv_frame*/ - - } else if (pattrib->amsdu == 1) { - if (amsdu_to_msdu(padapter, prframe) != _SUCCESS) - rtw_free_recvframe(prframe, &precvpriv->free_recv_queue); - } else { - /* error condition; */ - } - + if (recv_process_mpdu(padapter, prframe) != _SUCCESS) + precvpriv->dbg_rx_drop_count++; /* Update local variables. */ bPktInBuf = _FALSE; @@ -3039,114 +3464,34 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre } -int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe); -int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) +static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) { _irqL irql; int retval = _SUCCESS; struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; struct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl; - _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - - DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder); - - if (!pattrib->amsdu) { - /* s1. */ - retval = wlanhdr_to_ethhdr(prframe); - if (retval != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__); -#endif - return retval; - } - - /* if ((pattrib->qos!=1) || pattrib->priority!=0 || IS_MCAST(pattrib->ra) */ - /* || (pattrib->eth_type==0x0806) || (pattrib->ack_policy!=0)) */ - if (pattrib->qos != 1) { - if (!RTW_CANNOT_RUN(padapter)) { - - rtw_recv_indicatepkt(padapter, prframe); - return _SUCCESS; - - } - -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s pattrib->qos !=1\n", __FUNCTION__); -#endif - - return _FAIL; - - } - - if (preorder_ctrl->enable == _FALSE) { - /* indicate this recv_frame */ - preorder_ctrl->indicate_seq = pattrib->seq_num; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, pattrib->seq_num); -#endif - - rtw_recv_indicatepkt(padapter, prframe); - - preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) % 4096; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, pattrib->seq_num); -#endif - - return _SUCCESS; - } - -#ifndef CONFIG_RECV_REORDERING_CTRL - /* indicate this recv_frame */ - rtw_recv_indicatepkt(padapter, prframe); - return _SUCCESS; -#endif - - } else if (pattrib->amsdu == 1) { /* temp filter->means didn't support A-MSDUs in a A-MPDU */ - if (preorder_ctrl->enable == _FALSE) { - preorder_ctrl->indicate_seq = pattrib->seq_num; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, pattrib->seq_num); -#endif - - retval = amsdu_to_msdu(padapter, prframe); - - preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) % 4096; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, pattrib->seq_num); -#endif + _queue *ppending_recvframe_queue = preorder_ctrl ? &preorder_ctrl->pending_recvframe_queue : NULL; + struct recv_priv *precvpriv = &padapter->recvpriv; - if (retval != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__); -#endif - } - - return retval; - } - } else { + if (!pattrib->qos || !preorder_ctrl || preorder_ctrl->enable == _FALSE) + goto _success_exit; - } + DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder); _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); - /* s2. check if winstart_b(indicate_seq) needs to been updated */ if (!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) { - pdbgpriv->dbg_rx_ampdu_drop_count++; + precvpriv->dbg_rx_ampdu_drop_count++; /* pHTInfo->RxReorderDropCounter++; */ /* ReturnRFDList(Adapter, pRfd); */ /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ /* return _FAIL; */ -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s check_indicate_seq fail\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" check_indicate_seq fail\n" + , FUNC_ADPT_ARG(padapter)); + #endif #if 0 rtw_recv_indicatepkt(padapter, prframe); @@ -3164,9 +3509,10 @@ int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) /* DbgPrint("recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\n"); */ /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ /* return _FAIL; */ -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s enqueue_reorder_recvframe fail\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" enqueue_reorder_recvframe fail\n" + , FUNC_ADPT_ARG(padapter)); + #endif goto _err_exit; } @@ -3194,6 +3540,7 @@ int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); } + return RTW_RX_HANDLED; _success_exit: @@ -3231,69 +3578,38 @@ void rtw_reordering_ctrl_timeout_handler(void *pcontext) _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); } +#endif /* defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) */ -int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe); -int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe) +static void recv_set_iseq_before_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller) { - int retval = _SUCCESS; - /* struct recv_priv *precvpriv = &padapter->recvpriv; */ - /* struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; */ - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; -#ifdef CONFIG_TDLS - struct sta_info *psta = prframe->u.hdr.psta; -#endif /* CONFIG_TDLS */ - -#ifdef CONFIG_80211N_HT - - struct ht_priv *phtpriv = &pmlmepriv->htpriv; - - DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate); - -#ifdef CONFIG_TDLS - if ((phtpriv->ht_option == _TRUE) || - ((psta->tdls_sta_state & TDLS_LINKED_STATE) && - (psta->htpriv.ht_option == _TRUE) && - (psta->htpriv.ampdu_enable == _TRUE))) /* B/G/N Mode */ -#else - if (phtpriv->ht_option == _TRUE) /* B/G/N Mode */ -#endif /* CONFIG_TDLS */ - { - /* prframe->u.hdr.preorder_ctrl = &precvpriv->recvreorder_ctrl[pattrib->priority]; */ - - if (recv_indicatepkt_reorder(padapter, prframe) != _SUCCESS) { /* including perform A-MPDU Rx Ordering Buffer Control */ -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s recv_indicatepkt_reorder error!\n", __FUNCTION__); -#endif - - if (!RTW_CANNOT_RUN(padapter)) { - retval = _FAIL; - return retval; - } - } - } else /* B/G mode */ -#endif - { - retval = wlanhdr_to_ethhdr(prframe); - if (retval != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__); +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) + struct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl; + + if (reorder_ctrl) { + reorder_ctrl->indicate_seq = seq_num; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ %s("ADPT_FMT")-B tid:%u indicate_seq:%d, seq_num:%d\n" + , caller, ADPT_ARG(reorder_ctrl->padapter) + , reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num); + #endif + } #endif - return retval; - } - - if (!RTW_CANNOT_RUN(padapter)) { - /* indicate this recv_frame */ - rtw_recv_indicatepkt(padapter, prframe); - } else { - - retval = _FAIL; - return retval; - } +} +static void recv_set_iseq_after_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller) +{ +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) + struct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl; + + if (reorder_ctrl) { + reorder_ctrl->indicate_seq = (reorder_ctrl->indicate_seq + 1) % 4096; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ %s("ADPT_FMT")-A tid:%u indicate_seq:%d, seq_num:%d\n" + , caller, ADPT_ARG(reorder_ctrl->padapter) + , reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num); + #endif } - - return retval; - +#endif } #ifdef CONFIG_MP_INCLUDED @@ -3519,9 +3835,10 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) ret = MPwlanhdr_to_ethhdr(rframe); if (ret != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n" + , FUNC_ADPT_ARG(padapter)); + #endif rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ ret = _FAIL; goto exit; @@ -3530,20 +3847,22 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) /* indicate this recv_frame */ ret = rtw_recv_indicatepkt(padapter, rframe); if (ret != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s rtw_recv_indicatepkt fail!\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_recv_indicatepkt fail!\n" + , FUNC_ADPT_ARG(padapter)); + #endif rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ ret = _FAIL; goto exit; } } else { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s ecv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)\n", __func__, - rtw_is_drv_stopped(padapter) ? "True" : "False", - rtw_is_surprise_removed(padapter) ? "True" : "False"); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" + , FUNC_ADPT_ARG(padapter) + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False"); + #endif ret = _FAIL; rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ goto exit; @@ -3727,7 +4046,7 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, /* dBm Antenna Signal */ rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL); - hdr_buf[rt_len] = pattrib->phy_info.RecvSignalPower; + hdr_buf[rt_len] = pattrib->phy_info.recv_signal_power; rt_len += 1; #if 0 @@ -3738,7 +4057,7 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, /* Signal Quality */ rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_LOCK_QUALITY); - hdr_buf[rt_len] = pattrib->phy_info.SignalQuality; + hdr_buf[rt_len] = pattrib->phy_info.signal_quality; rt_len += 1; #endif @@ -3967,30 +4286,24 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) DBG_COUNTER(padapter->rx_logs.core_rx_post); - /* DATA FRAME */ - rtw_led_control(padapter, LED_CTL_RX); - prframe = decryptor(padapter, prframe); if (prframe == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s decryptor: drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" decryptor: drop pkt\n" + , FUNC_ADPT_ARG(padapter)); + #endif ret = _FAIL; DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_err); goto _recv_data_drop; } #ifdef DBG_RX_BMC_FRAME - if (IS_MCAST(pattrib->ra)) { - u8 *pbuf = prframe->u.hdr.rx_data; - u8 *sa_addr = get_sa(pbuf); - - RTW_INFO("%s =>"ADPT_FMT" Rx BC/MC from MAC: "MAC_FMT"\n", __func__, ADPT_ARG(padapter), MAC_ARG(sa_addr)); - } + if (IS_MCAST(pattrib->ra)) + RTW_INFO("%s =>"ADPT_FMT" Rx BC/MC from "MAC_FMT"\n", __func__, ADPT_ARG(padapter), MAC_ARG(pattrib->ta)); #endif #if 0 - if (padapter->adapter_type == PRIMARY_ADAPTER) { + if (is_primary_adapter(padapter)) { RTW_INFO("+++\n"); { int i; @@ -4019,18 +4332,20 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) prframe = recvframe_chk_defrag(padapter, prframe); if (prframe == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s recvframe_chk_defrag: drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recvframe_chk_defrag: drop pkt\n" + , FUNC_ADPT_ARG(padapter)); + #endif DBG_COUNTER(padapter->rx_logs.core_rx_post_defrag_err); goto _recv_data_drop; } prframe = portctrl(padapter, prframe); if (prframe == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s portctrl: drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" portctrl: drop pkt\n" + , FUNC_ADPT_ARG(padapter)); + #endif ret = _FAIL; DBG_COUNTER(padapter->rx_logs.core_rx_post_portctrl_err); goto _recv_data_drop; @@ -4042,75 +4357,30 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) rtw_wapi_update_info(padapter, prframe); #endif -#ifdef CONFIG_80211N_HT - ret = process_recv_indicatepkts(padapter, prframe); - if (ret != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s process_recv_indicatepkts fail!\n", __FUNCTION__); -#endif - rtw_free_recvframe(orig_prframe, pfree_recv_queue);/* free this recv_frame */ - DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_err); +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) + /* including perform A-MPDU Rx Ordering Buffer Control */ + ret = recv_indicatepkt_reorder(padapter, prframe); + if (ret == _FAIL) { + rtw_free_recvframe(orig_prframe, pfree_recv_queue); goto _recv_data_drop; - } -#else /* CONFIG_80211N_HT */ - if (!pattrib->amsdu) { - ret = wlanhdr_to_ethhdr(prframe); - if (ret != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__); -#endif - rtw_free_recvframe(orig_prframe, pfree_recv_queue);/* free this recv_frame */ - goto _recv_data_drop; - } - - if (!RTW_CANNOT_RUN(padapter)) { - /* indicate this recv_frame */ - ret = rtw_recv_indicatepkt(padapter, prframe); - if (ret != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s rtw_recv_indicatepkt fail!\n", __FUNCTION__); -#endif - goto _recv_data_drop; - } - } else { - -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s recv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)\n", __func__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); + } else if (ret == RTW_RX_HANDLED) /* queued OR indicated in order */ + goto _exit_recv_func; #endif - ret = _FAIL; - rtw_free_recvframe(orig_prframe, pfree_recv_queue); /* free this recv_frame */ - } - - } else if (pattrib->amsdu == 1) { - ret = amsdu_to_msdu(padapter, prframe); - if (ret != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__); -#endif - rtw_free_recvframe(orig_prframe, pfree_recv_queue); - goto _recv_data_drop; - } - } else { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s what is this condition??\n", __FUNCTION__); -#endif + recv_set_iseq_before_mpdu_process(prframe, pattrib->seq_num, __func__); + ret = recv_process_mpdu(padapter, prframe); + recv_set_iseq_after_mpdu_process(prframe, pattrib->seq_num, __func__); + if (ret == _FAIL) goto _recv_data_drop; - } -#endif /* CONFIG_80211N_HT */ _exit_recv_func: return ret; _recv_data_drop: - precvpriv->rx_drop++; + precvpriv->dbg_rx_drop_count++; return ret; } - -int recv_func(_adapter *padapter, union recv_frame *rframe); int recv_func(_adapter *padapter, union recv_frame *rframe) { int ret; @@ -4320,7 +4590,7 @@ static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe) struct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data; #endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - /* RTW_INFO("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength); */ + /* RTW_INFO("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->recv_signal_power,pattrib->signal_strength); */ /* if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) */ { #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS @@ -4331,7 +4601,7 @@ static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe) } signal_stat->total_num++; - signal_stat->total_val += pattrib->phy_info.SignalStrength; + signal_stat->total_val += pattrib->phy_info.signal_strength; signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; #else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ @@ -4341,9 +4611,9 @@ static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe) last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index]; padapter->recvpriv.signal_strength_data.total_val -= last_rssi; } - padapter->recvpriv.signal_strength_data.total_val += pattrib->phy_info.SignalStrength; + padapter->recvpriv.signal_strength_data.total_val += pattrib->phy_info.signal_strength; - padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.SignalStrength; + padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.signal_strength; if (padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX) padapter->recvpriv.signal_strength_data.index = 0; @@ -4388,11 +4658,11 @@ static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe) } signal_stat->total_num++; - signal_stat->total_val += pattrib->phy_info.SignalQuality; + signal_stat->total_val += pattrib->phy_info.signal_quality; signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; #else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - if (pattrib->phy_info.SignalQuality != 0) { + if (pattrib->phy_info.signal_quality != 0) { /* */ /* 1. Record the general EVM to the sliding window. */ /* */ @@ -4401,9 +4671,9 @@ static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe) last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index]; padapter->recvpriv.signal_qual_data.total_val -= last_evm; } - padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.SignalQuality; + padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.signal_quality; - padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.SignalQuality; + padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.signal_quality; if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX) padapter->recvpriv.signal_qual_data.index = 0; @@ -4438,41 +4708,30 @@ void rx_query_phy_status( PADAPTER padapter = precvframe->u.hdr.adapter; struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct _odm_phy_status_info_ *pPHYInfo = (struct _odm_phy_status_info_ *)(&pattrib->phy_info); + struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info; u8 *wlanhdr; - struct _odm_per_pkt_info_ pkt_info; - u8 *sa; + struct phydm_perpkt_info_struct pkt_info; + u8 *ta, *ra; + u8 is_ra_bmc; struct sta_priv *pstapriv; struct sta_info *psta = NULL; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct recv_priv *precvpriv = &padapter->recvpriv; /* _irqL irqL; */ pkt_info.is_packet_match_bssid = _FALSE; pkt_info.is_packet_to_self = _FALSE; pkt_info.is_packet_beacon = _FALSE; + pkt_info.ppdu_cnt = pattrib->ppdu_cnt; + pkt_info.station_id = 0xFF; wlanhdr = get_recvframe_data(precvframe); - pkt_info.is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr)) - && (!pattrib->icv_err) && (!pattrib->crc_err) - && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN); - - pkt_info.is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err) - && _rtw_memcmp(get_ra(wlanhdr), adapter_mac_addr(padapter), ETH_ALEN); - - pkt_info.is_packet_to_self = pkt_info.is_packet_match_bssid - && _rtw_memcmp(get_ra(wlanhdr), adapter_mac_addr(padapter), ETH_ALEN); - - pkt_info.is_packet_beacon = pkt_info.is_packet_match_bssid - && (get_frame_sub_type(wlanhdr) == WIFI_BEACON); - - sa = get_ta(wlanhdr); - - pkt_info.station_id = 0xFF; + ta = get_ta(wlanhdr); + ra = get_ra(wlanhdr); + is_ra_bmc = IS_MCAST(ra); - if (_rtw_memcmp(adapter_mac_addr(padapter), sa, ETH_ALEN) == _TRUE) { - static u32 start_time = 0; + if (_rtw_memcmp(adapter_mac_addr(padapter), ta, ETH_ALEN) == _TRUE) { + static systime start_time = 0; #if 0 /*For debug */ if (IsFrameTypeCtrl(wlanhdr)) { @@ -4494,27 +4753,48 @@ void rx_query_phy_status( RTW_PRINT("Warning!!! %s: Confilc mac addr!!\n", __func__); start_time = rtw_get_current_time(); } - pdbgpriv->dbg_rx_conflic_mac_addr_cnt++; + precvpriv->dbg_rx_conflic_mac_addr_cnt++; } else { pstapriv = &padapter->stapriv; - psta = rtw_get_stainfo(pstapriv, sa); + psta = rtw_get_stainfo(pstapriv, ta); if (psta) - pkt_info.station_id = psta->mac_id; + pkt_info.station_id = psta->cmn.mac_id; } + pkt_info.is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr)) + && (!pattrib->icv_err) && (!pattrib->crc_err) + && ((!MLME_IS_MESH(padapter) && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN)) + || (MLME_IS_MESH(padapter) && psta)); + + pkt_info.is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err) + && _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN); + + pkt_info.is_packet_to_self = pkt_info.is_packet_match_bssid + && _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN); + + pkt_info.is_packet_beacon = pkt_info.is_packet_match_bssid + && (get_frame_sub_type(wlanhdr) == WIFI_BEACON); + + if (psta && IsFrameTypeData(wlanhdr)) { + if (is_ra_bmc) + psta->curr_rx_rate_bmc = pattrib->data_rate; + else + psta->curr_rx_rate = pattrib->data_rate; + } pkt_info.data_rate = pattrib->data_rate; - /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ - odm_phy_status_query(&pHalData->odmpriv, pPHYInfo, pphy_status, &pkt_info); - if (psta) - psta->rssi = pattrib->phy_info.RecvSignalPower; - /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ + odm_phy_status_query(&pHalData->odmpriv, p_phy_info, pphy_status, &pkt_info); + + /* If bw is initial value, get from phy status */ + if (pattrib->bw == CHANNEL_WIDTH_MAX) + pattrib->bw = p_phy_info->band_width; { precvframe->u.hdr.psta = NULL; - if ((pkt_info.is_packet_match_bssid - && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)) || (padapter->registrypriv.mp_mode == 1) - ) { + if ((!MLME_IS_MESH(padapter) && pkt_info.is_packet_match_bssid) + || (MLME_IS_MESH(padapter) && psta) + || padapter->registrypriv.mp_mode == 1 + ) { if (psta) { precvframe->u.hdr.psta = psta; rx_process_phy_info(padapter, precvframe); @@ -4554,24 +4834,36 @@ void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index) ATOMIC_SET(&sta->continual_no_rx_packet[tid_index], 0); } +u8 adapter_allow_bmc_data_rx(_adapter *adapter) +{ + if (check_fwstate(&adapter->mlmepriv, WIFI_MONITOR_STATE | WIFI_MP_STATE) == _TRUE) + return 1; + + if (MLME_IS_AP(adapter)) + return 0; + + if (rtw_linked_check(adapter) == _FALSE) + return 0; + + return 1; +} s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status) { s32 ret = _SUCCESS; -#ifdef CONFIG_CONCURRENT_MODE - u8 *pda; u8 *pbuf = precvframe->u.hdr.rx_data; + u8 *pda = get_ra(pbuf); + u8 ra_is_bmc = IS_MCAST(pda); +#ifdef CONFIG_CONCURRENT_MODE _adapter *iface = NULL; _adapter *primary_padapter = precvframe->u.hdr.adapter; -#ifdef CONFIG_MP_INCLUDED + #ifdef CONFIG_MP_INCLUDED if (rtw_mp_mode_check(primary_padapter)) - return ret; -#endif - - pda = get_ra(pbuf); + goto bypass_concurrent_hdl; + #endif - if (IS_MCAST(pda) == _FALSE) { /*unicast packets*/ + if (ra_is_bmc == _FALSE) { /*unicast packets*/ iface = rtw_get_iface_by_macddr(primary_padapter , pda); if (NULL == iface) { RTW_INFO("%s [WARN] Cannot find appropriate adapter - mac_addr : "MAC_FMT"\n", __func__, MAC_ARG(pda)); @@ -4580,8 +4872,22 @@ s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status) precvframe->u.hdr.adapter = iface; } else /* Handle BC/MC Packets */ rtw_mi_buddy_clone_bcmc_packet(primary_padapter, precvframe, pphy_status); -#endif +bypass_concurrent_hdl: +#endif /* CONFIG_CONCURRENT_MODE */ + + /* skip unnecessary bmc data frame for primary adapter */ + if (ra_is_bmc == _TRUE && GetFrameType(pbuf) == WIFI_DATA_TYPE + && !adapter_allow_bmc_data_rx(precvframe->u.hdr.adapter) + ) { + rtw_free_recvframe(precvframe, &precvframe->u.hdr.adapter->recvpriv.free_recv_queue); + goto exit; + } + + if (pphy_status) + rx_query_phy_status(precvframe, pphy_status); + ret = rtw_recv_entry(precvframe); +exit: return ret; } @@ -4638,3 +4944,53 @@ thread_return rtw_recv_thread(thread_context context) } #endif /* CONFIG_RECV_THREAD_MODE */ +#if DBG_RX_BH_TRACKING +void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s) +{ + recv->rx_bh_stage = s; +} + +void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen) +{ + if (recv->rx_bh_cbuf) + recv->rx_bh_lbuf = recv->rx_bh_cbuf; + recv->rx_bh_cbuf = buf; + if (buf) { + recv->rx_bh_cbuf_data = data; + recv->rx_bh_cbuf_dlen = dlen; + recv->rx_bh_buf_dq_cnt++; + } else { + recv->rx_bh_cbuf_data = NULL; + recv->rx_bh_cbuf_dlen = 0; + } +} + +void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos) +{ + if (recv->rx_bh_cbuf) { + recv->rx_bh_cbuf_pos = pos - recv->rx_bh_cbuf_data; + } else { + rtw_warn_on(1); + recv->rx_bh_cbuf_pos = 0; + } +} + +void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame) +{ + recv->rx_bh_cframe = frame; +} + +void dump_rx_bh_tk(void *sel, struct recv_priv *recv) +{ + RTW_PRINT_SEL(sel, "[RXBHTK]s:%u, buf_dqc:%u, lbuf:%p, cbuf:%p, dlen:%u, pos:%u, cframe:%p\n" + , recv->rx_bh_stage + , recv->rx_bh_buf_dq_cnt + , recv->rx_bh_lbuf + , recv->rx_bh_cbuf + , recv->rx_bh_cbuf_dlen + , recv->rx_bh_cbuf_pos + , recv->rx_bh_cframe + ); +} +#endif /* DBG_RX_BH_TRACKING */ + diff --git a/core/rtw_rf.c b/core/rtw_rf.c index 60a714e..1c57c91 100644 --- a/core/rtw_rf.c +++ b/core/rtw_rf.c @@ -509,22 +509,24 @@ bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo) return valid; } -const char *const _ch_width_str[] = { +const char *const _ch_width_str[CHANNEL_WIDTH_MAX] = { "20MHz", "40MHz", "80MHz", "160MHz", "80_80MHz", - "CHANNEL_WIDTH_MAX", + "5MHz", + "10MHz", }; -const u8 _ch_width_to_bw_cap[] = { +const u8 _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] = { BW_CAP_20M, BW_CAP_40M, BW_CAP_80M, BW_CAP_160M, BW_CAP_80_80M, - 0, + BW_CAP_5M, + BW_CAP_10M, }; const char *const _band_str[] = { @@ -542,27 +544,27 @@ const u8 _band_to_band_cap[] = { }; const u8 _rf_type_to_rf_tx_cnt[] = { - 1, - 2, - 2, - 1, - 2, - 2, - 3, - 3, - 4, + 1, /*RF_1T1R*/ + 1, /*RF_1T2R*/ + 2, /*RF_2T2R*/ + 2, /*RF_2T3R*/ + 2, /*RF_2T4R*/ + 3, /*RF_3T3R*/ + 3, /*RF_3T4R*/ + 4, /*RF_4T4R*/ + 1, /*RF_TYPE_MAX*/ }; const u8 _rf_type_to_rf_rx_cnt[] = { - 2, - 4, - 2, - 1, - 2, - 3, - 3, - 4, - 4, + 1, /*RF_1T1R*/ + 2, /*RF_1T2R*/ + 2, /*RF_2T2R*/ + 3, /*RF_2T3R*/ + 4, /*RF_2T4R*/ + 3, /*RF_3T3R*/ + 4, /*RF_3T4R*/ + 4, /*RF_4T4R*/ + 1, /*RF_TYPE_MAX*/ }; #ifdef CONFIG_80211AC_VHT @@ -590,92 +592,97 @@ const u8 _rf_type_to_rf_rx_cnt[] = { #elif RTW_DEF_MODULE_REGULATORY_CERT +/* leave def_module_flags empty, def_module_flags check is done on country_chplan_map */ #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2) /* 2013 certify */ static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0x3FB), /* Canada */ - COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0x3F1), /* Chile */ - COUNTRY_CHPLAN_ENT("CN", 0x51, 1, 0x3FB), /* China */ - COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x3F1), /* Mexico */ - COUNTRY_CHPLAN_ENT("MY", 0x47, 1, 0x3F1), /* Malaysia */ - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0x3FB), /* Ukraine */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0), /* Chile */ + COUNTRY_CHPLAN_ENT("CN", 0x51, 1, 0), /* China */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */ + COUNTRY_CHPLAN_ENT("MY", 0x47, 1, 0), /* Malaysia */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU) /* 2014 certify */ static const struct country_chplan RTL8821AU_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0x3FB), /* Canada */ - COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0x3FB), /* Russia(fac/gost), Kaliningrad */ - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0x3FB), /* Ukraine */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF) /* 2014 certify */ static const struct country_chplan RTL8812AENF_NGFF_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC) /* 2013 certify */ static const struct country_chplan RTL8812AEBT_HMC_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0x3FB), /* Canada */ - COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0x3FB), /* Russia(fac/gost), Kaliningrad */ - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0x3FB), /* Ukraine */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2) /* 2012 certify */ static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0x3FB), /* Canada */ - COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x3F1), /* Mexico */ - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2) /* 2013 certify */ static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0x3FB), /* Canada */ - COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x3F1), /* Mexico */ - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216) /* 2014 certify */ static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0x3FB), /* Canada */ - COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x3F1), /* Mexico */ - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2) /* 2013 certify */ static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0x3FB), /* Canada */ - COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x3F1), /* Mexico */ - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x3FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x3FF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723DE_NGFF1630) /* 2016 certify */ static const struct country_chplan RTL8723DE_NGFF1630_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("CA", 0x2A, 1, 0x3FB), /* Canada */ - COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x3F1), /* Mexico */ + COUNTRY_CHPLAN_ENT("CA", 0x2A, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */ }; #endif #if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8822BE) /* 2016 certify */ static const struct country_chplan RTL8822BE_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0x3F1), /* Chile */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821CE) /* 2016 certify */ +static const struct country_chplan RTL8821CE_country_chplan_exc_map[] = { }; #endif @@ -723,6 +730,9 @@ static const struct country_chplan *rtw_def_module_get_chplan_from_country(const #elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8822BE) hal_map = RTL8822BE_country_chplan_exc_map; hal_map_sz = sizeof(RTL8822BE_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821CE) + hal_map = RTL8821CE_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8821CE_country_chplan_exc_map) / sizeof(struct country_chplan); #endif if (hal_map == NULL || hal_map_sz == 0) @@ -742,235 +752,235 @@ static const struct country_chplan *rtw_def_module_get_chplan_from_country(const static const struct country_chplan country_chplan_map[] = { COUNTRY_CHPLAN_ENT("AD", 0x26, 1, 0x000), /* Andorra */ - COUNTRY_CHPLAN_ENT("AE", 0x26, 1, 0x3FB), /* United Arab Emirates */ + COUNTRY_CHPLAN_ENT("AE", 0x26, 1, 0x7FB), /* United Arab Emirates */ COUNTRY_CHPLAN_ENT("AF", 0x42, 1, 0x000), /* Afghanistan */ COUNTRY_CHPLAN_ENT("AG", 0x26, 1, 0x000), /* Antigua & Barbuda */ COUNTRY_CHPLAN_ENT("AI", 0x26, 1, 0x000), /* Anguilla(UK) */ - COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0x3F1), /* Albania */ - COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0x2B0), /* Armenia */ - COUNTRY_CHPLAN_ENT("AN", 0x26, 1, 0x3F1), /* Netherlands Antilles */ - COUNTRY_CHPLAN_ENT("AO", 0x47, 1, 0x2E0), /* Angola */ + COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0x7F1), /* Albania */ + COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0x6B0), /* Armenia */ + COUNTRY_CHPLAN_ENT("AN", 0x26, 1, 0x7F1), /* Netherlands Antilles */ + COUNTRY_CHPLAN_ENT("AO", 0x47, 1, 0x6E0), /* Angola */ COUNTRY_CHPLAN_ENT("AQ", 0x26, 1, 0x000), /* Antarctica */ - COUNTRY_CHPLAN_ENT("AR", 0x57, 1, 0x3F3), /* Argentina */ + COUNTRY_CHPLAN_ENT("AR", 0x61, 1, 0x7F3), /* Argentina */ COUNTRY_CHPLAN_ENT("AS", 0x34, 1, 0x000), /* American Samoa */ - COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0x3FB), /* Austria */ - COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0x3FB), /* Australia */ + COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0x7FB), /* Austria */ + COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0x7FB), /* Australia */ COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0x0B0), /* Aruba */ - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0x3F1), /* Azerbaijan */ - COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0x3F1), /* Bosnia & Herzegovina */ - COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0x250), /* Barbados */ - COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0x3F1), /* Bangladesh */ - COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0x3FB), /* Belgium */ - COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0x2B0), /* Burkina Faso */ - COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0x3F1), /* Bulgaria */ - COUNTRY_CHPLAN_ENT("BH", 0x47, 1, 0x3F1), /* Bahrain */ - COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0x2B0), /* Burundi */ - COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0x2B0), /* Benin */ - COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0x210), /* Brunei */ - COUNTRY_CHPLAN_ENT("BO", 0x73, 1, 0x3F1), /* Bolivia */ - COUNTRY_CHPLAN_ENT("BR", 0x34, 1, 0x3F1), /* Brazil */ - COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0x220), /* Bahamas */ - COUNTRY_CHPLAN_ENT("BW", 0x26, 1, 0x2F1), /* Botswana */ - COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0x3F1), /* Belarus */ + COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0x7F1), /* Azerbaijan */ + COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0x7F1), /* Bosnia & Herzegovina */ + COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0x650), /* Barbados */ + COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0x7F1), /* Bangladesh */ + COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0x7FB), /* Belgium */ + COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0x6B0), /* Burkina Faso */ + COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0x7F1), /* Bulgaria */ + COUNTRY_CHPLAN_ENT("BH", 0x47, 1, 0x7F1), /* Bahrain */ + COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0x6B0), /* Burundi */ + COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0x6B0), /* Benin */ + COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0x610), /* Brunei */ + COUNTRY_CHPLAN_ENT("BO", 0x73, 1, 0x7F1), /* Bolivia */ + COUNTRY_CHPLAN_ENT("BR", 0x62, 1, 0x7F1), /* Brazil */ + COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0x620), /* Bahamas */ + COUNTRY_CHPLAN_ENT("BW", 0x26, 1, 0x6F1), /* Botswana */ + COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0x7F1), /* Belarus */ COUNTRY_CHPLAN_ENT("BZ", 0x34, 1, 0x000), /* Belize */ - COUNTRY_CHPLAN_ENT("CA", 0x2B, 1, 0x3FB), /* Canada */ + COUNTRY_CHPLAN_ENT("CA", 0x2B, 1, 0x7FB), /* Canada */ COUNTRY_CHPLAN_ENT("CC", 0x26, 1, 0x000), /* Cocos (Keeling) Islands (Australia) */ - COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0x2B0), /* Congo, Republic of the */ - COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0x2B0), /* Central African Republic */ - COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0x2B0), /* Congo, Democratic Republic of the. Zaire */ - COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0x3FB), /* Switzerland */ - COUNTRY_CHPLAN_ENT("CI", 0x26, 1, 0x3F1), /* Cote d'Ivoire */ + COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0x6B0), /* Congo, Republic of the */ + COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0x6B0), /* Central African Republic */ + COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0x6B0), /* Congo, Democratic Republic of the. Zaire */ + COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0x7FB), /* Switzerland */ + COUNTRY_CHPLAN_ENT("CI", 0x26, 1, 0x7F1), /* Cote d'Ivoire */ COUNTRY_CHPLAN_ENT("CK", 0x26, 1, 0x000), /* Cook Islands */ - COUNTRY_CHPLAN_ENT("CL", 0x73, 1, 0x3F1), /* Chile */ - COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0x2B0), /* Cameroon */ - COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0x3FB), /* China */ - COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0x3F1), /* Colombia */ - COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0x3F1), /* Costa Rica */ - COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0x2B0), /* Cape Verde */ + COUNTRY_CHPLAN_ENT("CL", 0x2D, 1, 0x7F1), /* Chile */ + COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0x6B0), /* Cameroon */ + COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0x7FB), /* China */ + COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0x7F1), /* Colombia */ + COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0x7F1), /* Costa Rica */ + COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0x6B0), /* Cape Verde */ COUNTRY_CHPLAN_ENT("CX", 0x45, 1, 0x000), /* Christmas Island (Australia) */ - COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0x3FB), /* Cyprus */ - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0x3FB), /* Czech Republic */ - COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0x3FB), /* Germany */ - COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0x280), /* Djibouti */ - COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0x3FB), /* Denmark */ + COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0x7FB), /* Cyprus */ + COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0x7FB), /* Czech Republic */ + COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0x7FB), /* Germany */ + COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0x680), /* Djibouti */ + COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0x7FB), /* Denmark */ COUNTRY_CHPLAN_ENT("DM", 0x34, 1, 0x000), /* Dominica */ - COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0x3F1), /* Dominican Republic */ - COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0x3F1), /* Algeria */ - COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0x3F1), /* Ecuador */ - COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0x3FB), /* Estonia */ - COUNTRY_CHPLAN_ENT("EG", 0x47, 0, 0x3F1), /* Egypt */ - COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0x280), /* Western Sahara */ + COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0x7F1), /* Dominican Republic */ + COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0x7F1), /* Algeria */ + COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0x7F1), /* Ecuador */ + COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0x7FB), /* Estonia */ + COUNTRY_CHPLAN_ENT("EG", 0x47, 1, 0x7F1), /* Egypt */ + COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0x680), /* Western Sahara */ COUNTRY_CHPLAN_ENT("ER", 0x26, 1, 0x000), /* Eritrea */ - COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0x3FB), /* Spain, Canary Islands, Ceuta, Melilla */ - COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0x0B0), /* Ethiopia */ - COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0x3FB), /* Finland */ - COUNTRY_CHPLAN_ENT("FJ", 0x34, 1, 0x200), /* Fiji */ + COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0x7FB), /* Spain, Canary Islands, Ceuta, Melilla */ + COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0x4B0), /* Ethiopia */ + COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0x7FB), /* Finland */ + COUNTRY_CHPLAN_ENT("FJ", 0x34, 1, 0x600), /* Fiji */ COUNTRY_CHPLAN_ENT("FK", 0x26, 1, 0x000), /* Falkland Islands (Islas Malvinas) (UK) */ COUNTRY_CHPLAN_ENT("FM", 0x34, 1, 0x000), /* Micronesia, Federated States of (USA) */ COUNTRY_CHPLAN_ENT("FO", 0x26, 1, 0x000), /* Faroe Islands (Denmark) */ - COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0x3FB), /* France */ - COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0x2B0), /* Gabon */ - COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0x3FB), /* Great Britain (United Kingdom; England) */ + COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0x7FB), /* France */ + COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0x6B0), /* Gabon */ + COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0x7FB), /* Great Britain (United Kingdom; England) */ COUNTRY_CHPLAN_ENT("GD", 0x34, 1, 0x0B0), /* Grenada */ - COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0x200), /* Georgia */ + COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0x600), /* Georgia */ COUNTRY_CHPLAN_ENT("GF", 0x26, 1, 0x080), /* French Guiana */ COUNTRY_CHPLAN_ENT("GG", 0x26, 1, 0x000), /* Guernsey (UK) */ - COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0x3F1), /* Ghana */ - COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0x200), /* Gibraltar (UK) */ - COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0x200), /* Greenland (Denmark) */ - COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0x2B0), /* Gambia */ - COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0x210), /* Guinea */ - COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0x200), /* Guadeloupe (France) */ - COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0x2B0), /* Equatorial Guinea */ - COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0x3FB), /* Greece */ + COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0x7F1), /* Ghana */ + COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0x600), /* Gibraltar (UK) */ + COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0x600), /* Greenland (Denmark) */ + COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0x6B0), /* Gambia */ + COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0x610), /* Guinea */ + COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0x600), /* Guadeloupe (France) */ + COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0x6B0), /* Equatorial Guinea */ + COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0x7FB), /* Greece */ COUNTRY_CHPLAN_ENT("GS", 0x26, 1, 0x000), /* South Georgia and the Sandwich Islands (UK) */ - COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0x3F1), /* Guatemala */ - COUNTRY_CHPLAN_ENT("GU", 0x34, 1, 0x200), /* Guam (USA) */ - COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0x2B0), /* Guinea-Bissau */ + COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0x7F1), /* Guatemala */ + COUNTRY_CHPLAN_ENT("GU", 0x34, 1, 0x600), /* Guam (USA) */ + COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0x6B0), /* Guinea-Bissau */ COUNTRY_CHPLAN_ENT("GY", 0x44, 1, 0x000), /* Guyana */ - COUNTRY_CHPLAN_ENT("HK", 0x26, 1, 0x3FB), /* Hong Kong */ + COUNTRY_CHPLAN_ENT("HK", 0x26, 1, 0x7FB), /* Hong Kong */ COUNTRY_CHPLAN_ENT("HM", 0x45, 1, 0x000), /* Heard and McDonald Islands (Australia) */ - COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0x3F1), /* Honduras */ - COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0x3F9), /* Croatia */ - COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0x250), /* Haiti */ - COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0x3FB), /* Hungary */ - COUNTRY_CHPLAN_ENT("ID", 0x54, 0, 0x3F3), /* Indonesia */ - COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0x3FB), /* Ireland */ - COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0x3F1), /* Israel */ + COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0x7F1), /* Honduras */ + COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0x7F9), /* Croatia */ + COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0x650), /* Haiti */ + COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0x7FB), /* Hungary */ + COUNTRY_CHPLAN_ENT("ID", 0x3D, 0, 0x7F3), /* Indonesia */ + COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0x7FB), /* Ireland */ + COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0x7F1), /* Israel */ COUNTRY_CHPLAN_ENT("IM", 0x26, 1, 0x000), /* Isle of Man (UK) */ - COUNTRY_CHPLAN_ENT("IN", 0x48, 1, 0x3F1), /* India */ + COUNTRY_CHPLAN_ENT("IN", 0x48, 1, 0x7F1), /* India */ COUNTRY_CHPLAN_ENT("IQ", 0x26, 1, 0x000), /* Iraq */ COUNTRY_CHPLAN_ENT("IR", 0x26, 0, 0x000), /* Iran */ - COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0x3FB), /* Iceland */ - COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0x3FB), /* Italy */ + COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0x7FB), /* Iceland */ + COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0x7FB), /* Italy */ COUNTRY_CHPLAN_ENT("JE", 0x26, 1, 0x000), /* Jersey (UK) */ - COUNTRY_CHPLAN_ENT("JM", 0x51, 1, 0x3F1), /* Jamaica */ - COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0x3FB), /* Jordan */ - COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0x3FF), /* Japan- Telec */ - COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0x3F9), /* Kenya */ - COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0x3F1), /* Kyrgyzstan */ - COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0x3F1), /* Cambodia */ + COUNTRY_CHPLAN_ENT("JM", 0x51, 1, 0x7F1), /* Jamaica */ + COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0x7FB), /* Jordan */ + COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0x7FF), /* Japan- Telec */ + COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0x7F9), /* Kenya */ + COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0x7F1), /* Kyrgyzstan */ + COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0x7F1), /* Cambodia */ COUNTRY_CHPLAN_ENT("KI", 0x26, 1, 0x000), /* Kiribati */ COUNTRY_CHPLAN_ENT("KN", 0x34, 1, 0x000), /* Saint Kitts and Nevis */ - COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0x3FB), /* South Korea */ - COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0x3FB), /* Kuwait */ + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0x7FB), /* South Korea */ + COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0x7FB), /* Kuwait */ COUNTRY_CHPLAN_ENT("KY", 0x34, 1, 0x000), /* Cayman Islands (UK) */ - COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0x300), /* Kazakhstan */ + COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0x700), /* Kazakhstan */ COUNTRY_CHPLAN_ENT("LA", 0x26, 1, 0x000), /* Laos */ - COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0x3F1), /* Lebanon */ + COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0x7F1), /* Lebanon */ COUNTRY_CHPLAN_ENT("LC", 0x34, 1, 0x000), /* Saint Lucia */ - COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0x3FB), /* Liechtenstein */ - COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0x3F1), /* Sri Lanka */ - COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0x2B0), /* Liberia */ - COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0x3F1), /* Lesotho */ - COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0x3FB), /* Lithuania */ - COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0x3FB), /* Luxembourg */ - COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0x3FB), /* Latvia */ + COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0x7FB), /* Liechtenstein */ + COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0x7F1), /* Sri Lanka */ + COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0x6B0), /* Liberia */ + COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0x7F1), /* Lesotho */ + COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0x7FB), /* Lithuania */ + COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0x7FB), /* Luxembourg */ + COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0x7FB), /* Latvia */ COUNTRY_CHPLAN_ENT("LY", 0x26, 1, 0x000), /* Libya */ - COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0x3F1), /* Morocco */ - COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0x3FB), /* Monaco */ - COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0x3F1), /* Moldova */ - COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0x3F1), /* Montenegro */ + COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0x7F1), /* Morocco */ + COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0x7FB), /* Monaco */ + COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0x7F1), /* Moldova */ + COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0x7F1), /* Montenegro */ COUNTRY_CHPLAN_ENT("MF", 0x34, 1, 0x000), /* Saint Martin */ - COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0x220), /* Madagascar */ + COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0x620), /* Madagascar */ COUNTRY_CHPLAN_ENT("MH", 0x34, 1, 0x000), /* Marshall Islands (USA) */ - COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0x3F1), /* Republic of Macedonia (FYROM) */ - COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0x2B0), /* Mali */ + COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0x7F1), /* Republic of Macedonia (FYROM) */ + COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0x6B0), /* Mali */ COUNTRY_CHPLAN_ENT("MM", 0x26, 1, 0x000), /* Burma (Myanmar) */ COUNTRY_CHPLAN_ENT("MN", 0x26, 1, 0x000), /* Mongolia */ - COUNTRY_CHPLAN_ENT("MO", 0x26, 1, 0x200), /* Macau */ + COUNTRY_CHPLAN_ENT("MO", 0x26, 1, 0x600), /* Macau */ COUNTRY_CHPLAN_ENT("MP", 0x34, 1, 0x000), /* Northern Mariana Islands (USA) */ - COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0x240), /* Martinique (France) */ - COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0x2A0), /* Mauritania */ + COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0x640), /* Martinique (France) */ + COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0x6A0), /* Mauritania */ COUNTRY_CHPLAN_ENT("MS", 0x26, 1, 0x000), /* Montserrat (UK) */ - COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0x3FB), /* Malta */ - COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0x2B0), /* Mauritius */ + COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0x7FB), /* Malta */ + COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0x6B0), /* Mauritius */ COUNTRY_CHPLAN_ENT("MV", 0x47, 1, 0x000), /* Maldives */ - COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0x2B0), /* Malawi */ - COUNTRY_CHPLAN_ENT("MX", 0x61, 1, 0x3F1), /* Mexico */ - COUNTRY_CHPLAN_ENT("MY", 0x63, 1, 0x3F1), /* Malaysia */ - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0x3F1), /* Mozambique */ - COUNTRY_CHPLAN_ENT("NA", 0x26, 1, 0x300), /* Namibia */ + COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0x6B0), /* Malawi */ + COUNTRY_CHPLAN_ENT("MX", 0x61, 1, 0x7F1), /* Mexico */ + COUNTRY_CHPLAN_ENT("MY", 0x63, 1, 0x7F1), /* Malaysia */ + COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0x7F1), /* Mozambique */ + COUNTRY_CHPLAN_ENT("NA", 0x26, 1, 0x700), /* Namibia */ COUNTRY_CHPLAN_ENT("NC", 0x26, 1, 0x000), /* New Caledonia */ - COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0x2B0), /* Niger */ + COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0x6B0), /* Niger */ COUNTRY_CHPLAN_ENT("NF", 0x45, 1, 0x000), /* Norfolk Island (Australia) */ - COUNTRY_CHPLAN_ENT("NG", 0x75, 1, 0x3F9), /* Nigeria */ - COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0x3F1), /* Nicaragua */ - COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0x3FB), /* Netherlands */ - COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0x3FB), /* Norway */ - COUNTRY_CHPLAN_ENT("NP", 0x47, 1, 0x2F0), /* Nepal */ + COUNTRY_CHPLAN_ENT("NG", 0x75, 1, 0x7F9), /* Nigeria */ + COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0x7F1), /* Nicaragua */ + COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0x7FB), /* Netherlands */ + COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0x7FB), /* Norway */ + COUNTRY_CHPLAN_ENT("NP", 0x47, 1, 0x6F0), /* Nepal */ COUNTRY_CHPLAN_ENT("NR", 0x26, 1, 0x000), /* Nauru */ COUNTRY_CHPLAN_ENT("NU", 0x45, 1, 0x000), /* Niue */ - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0x3FB), /* New Zealand */ - COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0x3F9), /* Oman */ - COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0x3F1), /* Panama */ - COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0x3F1), /* Peru */ + COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0x7FB), /* New Zealand */ + COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0x7F9), /* Oman */ + COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0x7F1), /* Panama */ + COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0x7F1), /* Peru */ COUNTRY_CHPLAN_ENT("PF", 0x26, 1, 0x000), /* French Polynesia (France) */ - COUNTRY_CHPLAN_ENT("PG", 0x26, 1, 0x3F1), /* Papua New Guinea */ - COUNTRY_CHPLAN_ENT("PH", 0x26, 1, 0x3F1), /* Philippines */ - COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0x3F1), /* Pakistan */ - COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0x3FB), /* Poland */ + COUNTRY_CHPLAN_ENT("PG", 0x26, 1, 0x7F1), /* Papua New Guinea */ + COUNTRY_CHPLAN_ENT("PH", 0x26, 1, 0x7F1), /* Philippines */ + COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0x7F1), /* Pakistan */ + COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0x7FB), /* Poland */ COUNTRY_CHPLAN_ENT("PM", 0x26, 1, 0x000), /* Saint Pierre and Miquelon (France) */ - COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0x3F1), /* Puerto Rico */ - COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0x3FB), /* Portugal */ + COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0x7F1), /* Puerto Rico */ + COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0x7FB), /* Portugal */ COUNTRY_CHPLAN_ENT("PW", 0x34, 1, 0x000), /* Palau */ - COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0x3F1), /* Paraguay */ - COUNTRY_CHPLAN_ENT("QA", 0x51, 1, 0x3F9), /* Qatar */ + COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0x7F1), /* Paraguay */ + COUNTRY_CHPLAN_ENT("QA", 0x51, 1, 0x7F9), /* Qatar */ COUNTRY_CHPLAN_ENT("RE", 0x26, 1, 0x000), /* Reunion (France) */ - COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0x3F1), /* Romania */ - COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0x3F1), /* Serbia, Kosovo */ - COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0x3FB), /* Russia(fac/gost), Kaliningrad */ - COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0x2B0), /* Rwanda */ - COUNTRY_CHPLAN_ENT("SA", 0x26, 1, 0x3FB), /* Saudi Arabia */ + COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0x7F1), /* Romania */ + COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0x7F1), /* Serbia, Kosovo */ + COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0x7FB), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0x0B0), /* Rwanda */ + COUNTRY_CHPLAN_ENT("SA", 0x26, 1, 0x7FB), /* Saudi Arabia */ COUNTRY_CHPLAN_ENT("SB", 0x26, 1, 0x000), /* Solomon Islands */ - COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0x290), /* Seychelles */ - COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0x3FB), /* Sweden */ - COUNTRY_CHPLAN_ENT("SG", 0x26, 1, 0x3FB), /* Singapore */ + COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0x690), /* Seychelles */ + COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0x7FB), /* Sweden */ + COUNTRY_CHPLAN_ENT("SG", 0x26, 1, 0x7FB), /* Singapore */ COUNTRY_CHPLAN_ENT("SH", 0x26, 1, 0x000), /* Saint Helena (UK) */ - COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0x3FB), /* Slovenia */ + COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0x7FB), /* Slovenia */ COUNTRY_CHPLAN_ENT("SJ", 0x26, 1, 0x000), /* Svalbard (Norway) */ - COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0x3FB), /* Slovakia */ - COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0x2B0), /* Sierra Leone */ + COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0x7FB), /* Slovakia */ + COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0x6B0), /* Sierra Leone */ COUNTRY_CHPLAN_ENT("SM", 0x26, 1, 0x000), /* San Marino */ - COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0x3F1), /* Senegal */ + COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0x7F1), /* Senegal */ COUNTRY_CHPLAN_ENT("SO", 0x26, 1, 0x000), /* Somalia */ COUNTRY_CHPLAN_ENT("SR", 0x74, 1, 0x000), /* Suriname */ - COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0x280), /* Sao Tome and Principe */ - COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0x3F1), /* El Salvador */ + COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0x680), /* Sao Tome and Principe */ + COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0x7F1), /* El Salvador */ COUNTRY_CHPLAN_ENT("SX", 0x34, 1, 0x000), /* Sint Marteen */ COUNTRY_CHPLAN_ENT("SZ", 0x26, 1, 0x020), /* Swaziland */ COUNTRY_CHPLAN_ENT("TC", 0x26, 1, 0x000), /* Turks and Caicos Islands (UK) */ - COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0x2B0), /* Chad */ - COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0x280), /* French Southern and Antarctic Lands (FR Southern Territories) */ - COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0x2B0), /* Togo */ - COUNTRY_CHPLAN_ENT("TH", 0x26, 1, 0x3F1), /* Thailand */ - COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0x240), /* Tajikistan */ + COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0x6B0), /* Chad */ + COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0x680), /* French Southern and Antarctic Lands (FR Southern Territories) */ + COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0x6B0), /* Togo */ + COUNTRY_CHPLAN_ENT("TH", 0x26, 1, 0x7F1), /* Thailand */ + COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0x640), /* Tajikistan */ COUNTRY_CHPLAN_ENT("TK", 0x45, 1, 0x000), /* Tokelau */ COUNTRY_CHPLAN_ENT("TM", 0x26, 1, 0x000), /* Turkmenistan */ - COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0x3F1), /* Tunisia */ + COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0x7F1), /* Tunisia */ COUNTRY_CHPLAN_ENT("TO", 0x26, 1, 0x000), /* Tonga */ - COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0x3F1), /* Turkey, Northern Cyprus */ + COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0x7F1), /* Turkey, Northern Cyprus */ COUNTRY_CHPLAN_ENT("TT", 0x42, 1, 0x3F1), /* Trinidad & Tobago */ - COUNTRY_CHPLAN_ENT("TW", 0x76, 1, 0x3FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0x2F0), /* Tanzania */ - COUNTRY_CHPLAN_ENT("UA", 0x36, 1, 0x3FB), /* Ukraine */ - COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0x2F1), /* Uganda */ - COUNTRY_CHPLAN_ENT("US", 0x76, 1, 0x3FF), /* United States of America (USA) */ - COUNTRY_CHPLAN_ENT("UY", 0x30, 1, 0x3F1), /* Uruguay */ - COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0x2F0), /* Uzbekistan */ + COUNTRY_CHPLAN_ENT("TW", 0x76, 1, 0x7FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0x6F0), /* Tanzania */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 1, 0x7FB), /* Ukraine */ + COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0x6F1), /* Uganda */ + COUNTRY_CHPLAN_ENT("US", 0x76, 1, 0x7FF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("UY", 0x30, 1, 0x7F1), /* Uruguay */ + COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0x6F0), /* Uzbekistan */ COUNTRY_CHPLAN_ENT("VA", 0x26, 1, 0x000), /* Holy See (Vatican City) */ COUNTRY_CHPLAN_ENT("VC", 0x34, 1, 0x010), /* Saint Vincent and the Grenadines */ - COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0x3F1), /* Venezuela */ + COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0x7F1), /* Venezuela */ COUNTRY_CHPLAN_ENT("VI", 0x34, 1, 0x000), /* United States Virgin Islands (USA) */ - COUNTRY_CHPLAN_ENT("VN", 0x26, 1, 0x3F1), /* Vietnam */ + COUNTRY_CHPLAN_ENT("VN", 0x26, 1, 0x7F1), /* Vietnam */ COUNTRY_CHPLAN_ENT("VU", 0x26, 1, 0x000), /* Vanuatu */ COUNTRY_CHPLAN_ENT("WF", 0x26, 1, 0x000), /* Wallis and Futuna (France) */ COUNTRY_CHPLAN_ENT("WS", 0x34, 1, 0x000), /* Samoa */ COUNTRY_CHPLAN_ENT("YE", 0x26, 1, 0x040), /* Yemen */ - COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0x280), /* Mayotte (France) */ - COUNTRY_CHPLAN_ENT("ZA", 0x26, 1, 0x3F1), /* South Africa */ - COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0x2B0), /* Zambia */ - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0x3F1), /* Zimbabwe */ + COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0x680), /* Mayotte (France) */ + COUNTRY_CHPLAN_ENT("ZA", 0x26, 1, 0x7F1), /* South Africa */ + COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0x6B0), /* Zambia */ + COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0x7F1), /* Zimbabwe */ }; /* @@ -981,6 +991,9 @@ static const struct country_chplan country_chplan_map[] = { */ const struct country_chplan *rtw_get_chplan_from_country(const char *country_code) { +#if RTW_DEF_MODULE_REGULATORY_CERT + const struct country_chplan *exc_ent = NULL; +#endif const struct country_chplan *ent = NULL; const struct country_chplan *map = NULL; u16 map_sz = 0; @@ -990,16 +1003,13 @@ const struct country_chplan *rtw_get_chplan_from_country(const char *country_cod code[0] = alpha_to_upper(country_code[0]); code[1] = alpha_to_upper(country_code[1]); -#if !defined(CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP) && RTW_DEF_MODULE_REGULATORY_CERT - ent = rtw_def_module_get_chplan_from_country(code); - if (ent != NULL) - goto exit; -#endif - #ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP map = CUSTOMIZED_country_chplan_map; map_sz = sizeof(CUSTOMIZED_country_chplan_map) / sizeof(struct country_chplan); #else + #if RTW_DEF_MODULE_REGULATORY_CERT + exc_ent = rtw_def_module_get_chplan_from_country(code); + #endif map = country_chplan_map; map_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan); #endif @@ -1013,8 +1023,10 @@ const struct country_chplan *rtw_get_chplan_from_country(const char *country_cod exit: #if RTW_DEF_MODULE_REGULATORY_CERT - if (ent && !(COUNTRY_CHPLAN_DEF_MODULE_FALGS(ent) & RTW_DEF_MODULE_REGULATORY_CERT)) - ent = NULL; + if (!ent || !(COUNTRY_CHPLAN_DEF_MODULE_FALGS(ent) & RTW_DEF_MODULE_REGULATORY_CERT)) + exc_ent = ent = NULL; + if (exc_ent) + ent = exc_ent; #endif return ent; @@ -1027,6 +1039,8 @@ const char *const _regd_str[] = { "ETSI", "IC", "KCC", + "ACMA", + "CHILE", "WW", }; @@ -1190,10 +1204,12 @@ void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl) void dump_txpwr_lmt(void *sel, _adapter *adapter) { +#define TMP_STR_LEN 16 struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); _irqL irqL; char fmt[16]; + char tmp_str[TMP_STR_LEN]; s8 *lmt_idx = NULL; int bw, band, ch_num, tlrs, ntx_idx, rs, i, path; u8 ch, n, rfpath_num; @@ -1326,16 +1342,16 @@ void dump_txpwr_lmt(void *sel, _adapter *adapter) cur = get_next(cur); sprintf(fmt, "%%%zus%%s ", strlen(ent->regd_name) < 4 ? 5 - strlen(ent->regd_name) : 1); - _RTW_PRINT_SEL(sel, fmt + snprintf(tmp_str, TMP_STR_LEN, fmt , strcmp(ent->regd_name, rfctl->regd_name) == 0 ? "*" : "" - , ent->regd_name - ); + , ent->regd_name); + _RTW_PRINT_SEL(sel, "%s", tmp_str); } sprintf(fmt, "%%%zus%%s ", strlen(regd_str(TXPWR_LMT_WW)) < 4 ? 5 - strlen(regd_str(TXPWR_LMT_WW)) : 1); - _RTW_PRINT_SEL(sel, fmt + snprintf(tmp_str, TMP_STR_LEN, fmt , strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? "*" : "" - , regd_str(TXPWR_LMT_WW) - ); + , regd_str(TXPWR_LMT_WW)); + _RTW_PRINT_SEL(sel, "%s", tmp_str); /* header for limit offset */ for (path = 0; path < RF_PATH_MAX; path++) { @@ -1380,28 +1396,42 @@ void dump_txpwr_lmt(void *sel, _adapter *adapter) lmt = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw, tlrs, ntx_idx, ch, 0); if (lmt == MAX_POWER_INDEX) { sprintf(fmt, "%%%zus ", strlen(ent->regd_name) >= 5 ? strlen(ent->regd_name) + 1 : 5); - _RTW_PRINT_SEL(sel, fmt, "NA"); + snprintf(tmp_str, TMP_STR_LEN, fmt, "NA"); + _RTW_PRINT_SEL(sel, "%s", tmp_str); } else { - if (lmt % 2) { + if (lmt == -1) { /* -0.5 */ + sprintf(fmt, "%%%zus ", strlen(ent->regd_name) >= 5 ? strlen(ent->regd_name) + 1 : 5); + snprintf(tmp_str, TMP_STR_LEN, fmt, "-0.5"); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } else if (lmt % 2) { /* n.5 */ sprintf(fmt, "%%%zud.5 ", strlen(ent->regd_name) >= 5 ? strlen(ent->regd_name) - 1 : 3); - _RTW_PRINT_SEL(sel, fmt, lmt / 2); - } else { + snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / 2); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } else { /* n */ sprintf(fmt, "%%%zud ", strlen(ent->regd_name) >= 5 ? strlen(ent->regd_name) + 1 : 5); - _RTW_PRINT_SEL(sel, fmt, lmt / 2); + snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / 2); + _RTW_PRINT_SEL(sel, "%s", tmp_str); } } } lmt = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw, tlrs, ntx_idx, ch, 0); if (lmt == MAX_POWER_INDEX) { sprintf(fmt, "%%%zus ", strlen(regd_str(TXPWR_LMT_WW)) >= 5 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 5); - _RTW_PRINT_SEL(sel, fmt, "NA"); + snprintf(tmp_str, TMP_STR_LEN, fmt, "NA"); + _RTW_PRINT_SEL(sel, "%s", tmp_str); } else { - if (lmt % 2) { + if (lmt == -1) { /* -0.5 */ + sprintf(fmt, "%%%zus ", strlen(regd_str(TXPWR_LMT_WW)) >= 5 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 5); + snprintf(tmp_str, TMP_STR_LEN, fmt, "-0.5"); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } else if (lmt % 2) { /* n.5 */ sprintf(fmt, "%%%zud.5 ", strlen(regd_str(TXPWR_LMT_WW)) >= 5 ? strlen(regd_str(TXPWR_LMT_WW)) - 1 : 3); - _RTW_PRINT_SEL(sel, fmt, lmt / 2); - } else { + snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / 2); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } else { /* n */ sprintf(fmt, "%%%zud ", strlen(regd_str(TXPWR_LMT_WW)) >= 5 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 5); - _RTW_PRINT_SEL(sel, fmt, lmt / 2); + snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / 2); + _RTW_PRINT_SEL(sel, "%s", tmp_str); } } @@ -1776,34 +1806,6 @@ void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch) } } -inline u8 rtw_is_5g_band1(u8 ch) -{ - if (ch >= 36 && ch <= 48) - return 1; - return 0; -} - -inline u8 rtw_is_5g_band2(u8 ch) -{ - if (ch >= 52 && ch <= 64) - return 1; - return 0; -} - -inline u8 rtw_is_5g_band3(u8 ch) -{ - if (ch >= 100 && ch <= 144) - return 1; - return 0; -} - -inline u8 rtw_is_5g_band4(u8 ch) -{ - if (ch >= 149 && ch <= 177) - return 1; - return 0; -} - inline u8 rtw_is_dfs_range(u32 hi, u32 lo) { return rtw_is_range_overlap(hi, lo, 5720 + 10, 5260 - 10); @@ -1831,7 +1833,7 @@ u8 rtw_is_dfs_chbw(u8 ch, u8 bw, u8 offset) bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region) { - return (dfs_region == PHYDM_DFS_DOMAIN_ETSI && rtw_is_range_overlap(hi, lo, 5660 + 10, 5600 - 10)) ? _TRUE : _FALSE; + return (dfs_region == PHYDM_DFS_DOMAIN_ETSI && rtw_is_range_overlap(hi, lo, 5650, 5600)) ? _TRUE : _FALSE; } bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region) diff --git a/core/rtw_sdio.c b/core/rtw_sdio.c index bf27f46..e8f49bf 100644 --- a/core/rtw_sdio.c +++ b/core/rtw_sdio.c @@ -123,11 +123,8 @@ u8 rtw_sdio_f0_read(struct dvobj_priv *d, u32 addr, void *buf, size_t len) addr = RTW_SDIO_ADDR_F0_GEN(addr); err = d->intf_ops->read(d, addr, buf, len, 0); - if (err) { - RTW_INFO("%s: [ERROR] Read f0 register FAIL!\n", __FUNCTION__); + if (err) ret = _FAIL; - } - return ret; } diff --git a/core/rtw_security.c b/core/rtw_security.c index 2206428..52d5e3d 100644 --- a/core/rtw_security.c +++ b/core/rtw_security.c @@ -821,7 +821,7 @@ u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe) if (stainfo != NULL) { if (IS_MCAST(prxattrib->ra)) { - static u32 start = 0; + static systime start = 0; static u32 no_gkey_bc_cnt = 0; static u32 no_gkey_mc_cnt = 0; @@ -1185,11 +1185,11 @@ static void construct_mic_iv( mic_iv[1] = mpdu[24] & 0x0f; /* mute bits 7-4 */ if (!qc_exists) mic_iv[1] = 0x00; -#ifdef CONFIG_IEEE80211W +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) /* 802.11w management frame should set management bit(4) */ if (frtype == WIFI_MGT_TYPE) mic_iv[1] |= BIT(4); -#endif /* CONFIG_IEEE80211W */ +#endif for (i = 2; i < 8; i++) mic_iv[i] = mpdu[i + 8]; /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */ #ifdef CONSISTENT_PN_ORDER @@ -1219,12 +1219,12 @@ static void construct_mic_header1( { mic_header1[0] = (u8)((header_length - 2) / 256); mic_header1[1] = (u8)((header_length - 2) % 256); -#ifdef CONFIG_IEEE80211W +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) /* 802.11w management frame don't AND subtype bits 4,5,6 of frame control field */ if (frtype == WIFI_MGT_TYPE) mic_header1[2] = mpdu[0]; else -#endif /* CONFIG_IEEE80211W */ +#endif mic_header1[2] = mpdu[0] & 0xcf; /* Mute CF poll & CF ack bits */ mic_header1[3] = mpdu[1] & 0xc7; /* Mute retry, more data and pwr mgt bits */ @@ -1320,11 +1320,11 @@ static void construct_ctr_preload( ctr_preload[1] = mpdu[30] & 0x0f; /* QoC_Control */ if (qc_exists && !a4_exists) ctr_preload[1] = mpdu[24] & 0x0f; -#ifdef CONFIG_IEEE80211W +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) /* 802.11w management frame should set management bit(4) */ if (frtype == WIFI_MGT_TYPE) ctr_preload[1] |= BIT(4); -#endif /* CONFIG_IEEE80211W */ +#endif for (i = 2; i < 8; i++) ctr_preload[i] = mpdu[i + 8]; /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */ #ifdef CONSISTENT_PN_ORDER @@ -1394,8 +1394,7 @@ static sint aes_cipher(u8 *key, uint hdrlen, ((frtype | frsubtype) == WIFI_DATA_CFPOLL) || ((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) { qc_exists = 1; - if (hdrlen != WLAN_HDR_A3_QOS_LEN) - + if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN) hdrlen += 2; } /* add for CONFIG_IEEE80211W, none 11w also can use */ @@ -1404,8 +1403,7 @@ static sint aes_cipher(u8 *key, uint hdrlen, (frsubtype == 0x09) || (frsubtype == 0x0a) || (frsubtype == 0x0b))) { - if (hdrlen != WLAN_HDR_A3_QOS_LEN) - + if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN) hdrlen += 2; qc_exists = 1; } else @@ -1715,8 +1713,7 @@ static sint aes_decipher(u8 *key, uint hdrlen, ((frtype | frsubtype) == WIFI_DATA_CFPOLL) || ((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) { qc_exists = 1; - if (hdrlen != WLAN_HDR_A3_QOS_LEN) - + if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN) hdrlen += 2; } /* only for data packet . add for CONFIG_IEEE80211W, none 11w also can use */ else if ((frtype == WIFI_DATA) && @@ -1724,8 +1721,7 @@ static sint aes_decipher(u8 *key, uint hdrlen, (frsubtype == 0x09) || (frsubtype == 0x0a) || (frsubtype == 0x0b))) { - if (hdrlen != WLAN_HDR_A3_QOS_LEN) - + if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN) hdrlen += 2; qc_exists = 1; } else @@ -1948,13 +1944,17 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe) if (stainfo != NULL) { if (IS_MCAST(prxattrib->ra)) { - static u32 start = 0; + static systime start = 0; static u32 no_gkey_bc_cnt = 0; static u32 no_gkey_mc_cnt = 0; /* RTW_INFO("rx bc/mc packets, to perform sw rtw_aes_decrypt\n"); */ /* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */ - if (psecuritypriv->binstallGrpkey == _FALSE) { + if ((!MLME_IS_MESH(padapter) && psecuritypriv->binstallGrpkey == _FALSE) + #ifdef CONFIG_RTW_MESH + || !(stainfo->gtk_bmp | BIT(prxattrib->key_index)) + #endif + ) { res = _FAIL; if (start == 0) @@ -1986,12 +1986,20 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe) no_gkey_bc_cnt = 0; no_gkey_mc_cnt = 0; - prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; - if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) { - RTW_DBG("not match packet_index=%d, install_index=%d\n" - , prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid); - res = _FAIL; - goto exit; + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* TODO: multiple GK? */ + prwskey = &stainfo->gtk.skey[0]; + } else + #endif + { + prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; + if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) { + RTW_DBG("not match packet_index=%d, install_index=%d\n" + , prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid); + res = _FAIL; + goto exit; + } } } else prwskey = &stainfo->dot118021x_UncstKey.skey[0]; @@ -2033,94 +2041,96 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe) } #ifdef CONFIG_IEEE80211W -u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe) +u32 rtw_BIP_verify(_adapter *padapter, u8 *whdr_pos, sint flen + , const u8 *key, u16 keyid, u64* ipn) { - struct rx_pkt_attrib *pattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; - u8 *pframe; - u8 *BIP_AAD, *p; + u8 *BIP_AAD, *mme; u32 res = _FAIL; uint len, ori_len; + u16 pkt_keyid = 0; + u64 pkt_ipn = 0; struct rtw_ieee80211_hdr *pwlanhdr; u8 mic[16]; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - ori_len = pattrib->pkt_len - WLAN_HDR_A3_LEN + BIP_AAD_SIZE; - BIP_AAD = rtw_zmalloc(ori_len); + mme = whdr_pos + flen - 18; + if (*mme != _MME_IE_) + return RTW_RX_HANDLED; + + /* copy key index */ + _rtw_memcpy(&pkt_keyid, mme + 2, 2); + pkt_keyid = le16_to_cpu(pkt_keyid); + if (pkt_keyid != keyid) { + RTW_INFO("BIP key index error!\n"); + return _FAIL; + } + + /* save packet number */ + _rtw_memcpy(&pkt_ipn, mme + 4, 6); + pkt_ipn = le64_to_cpu(pkt_ipn); + /* BIP packet number should bigger than previous BIP packet */ + if (pkt_ipn <= *ipn) { /* wrap around? */ + RTW_INFO("replay BIP packet\n"); + return _FAIL; + } + + ori_len = flen - WLAN_HDR_A3_LEN + BIP_AAD_SIZE; + BIP_AAD = rtw_zmalloc(ori_len); if (BIP_AAD == NULL) { RTW_INFO("BIP AAD allocate fail\n"); return _FAIL; } - /* PKT start */ - pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data; + /* mapping to wlan header */ - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + pwlanhdr = (struct rtw_ieee80211_hdr *)whdr_pos; + /* save the frame body + MME */ - _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, pframe + WLAN_HDR_A3_LEN, pattrib->pkt_len - WLAN_HDR_A3_LEN); - /* find MME IE pointer */ - p = rtw_get_ie(BIP_AAD + BIP_AAD_SIZE, _MME_IE_, &len, pattrib->pkt_len - WLAN_HDR_A3_LEN); - /* Baron */ - if (p) { - u16 keyid = 0; - u64 temp_ipn = 0; - /* save packet number */ - _rtw_memcpy(&temp_ipn, p + 4, 6); - temp_ipn = le64_to_cpu(temp_ipn); - /* BIP packet number should bigger than previous BIP packet */ - if (temp_ipn < pmlmeext->mgnt_80211w_IPN_rx) { - RTW_INFO("replay BIP packet\n"); - goto BIP_exit; - } - /* copy key index */ - _rtw_memcpy(&keyid, p + 2, 2); - keyid = le16_to_cpu(keyid); - if (keyid != padapter->securitypriv.dot11wBIPKeyid) { - RTW_INFO("BIP key index error!\n"); - goto BIP_exit; - } - /* clear the MIC field of MME to zero */ - _rtw_memset(p + 2 + len - 8, 0, 8); + _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, whdr_pos + WLAN_HDR_A3_LEN, flen - WLAN_HDR_A3_LEN); + + /* point mme to the copy */ + mme = BIP_AAD + ori_len - 18; - /* conscruct AAD, copy frame control field */ - _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); - ClearRetry(BIP_AAD); - ClearPwrMgt(BIP_AAD); - ClearMData(BIP_AAD); - /* conscruct AAD, copy address 1 to address 3 */ - _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18); + /* clear the MIC field of MME to zero */ + _rtw_memset(mme + 10, 0, 8); - if (omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey - , BIP_AAD, ori_len, mic)) - goto BIP_exit; + /* conscruct AAD, copy frame control field */ + _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); + ClearRetry(BIP_AAD); + ClearPwrMgt(BIP_AAD); + ClearMData(BIP_AAD); + /* conscruct AAD, copy address 1 to address 3 */ + _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18); + + if (omac1_aes_128(key, BIP_AAD, ori_len, mic)) + goto BIP_exit; #if 0 - /* management packet content */ - { - int pp; - RTW_INFO("pkt: "); - for (pp = 0; pp < pattrib->pkt_len; pp++) - printk(" %02x ", pframe[pp]); - RTW_INFO("\n"); - /* BIP AAD + management frame body + MME(MIC is zero) */ - RTW_INFO("AAD+PKT: "); - for (pp = 0; pp < ori_len; pp++) - RTW_INFO(" %02x ", BIP_AAD[pp]); - RTW_INFO("\n"); - /* show the MIC result */ - RTW_INFO("mic: "); - for (pp = 0; pp < 16; pp++) - RTW_INFO(" %02x ", mic[pp]); - RTW_INFO("\n"); - } + /* management packet content */ + { + int pp; + RTW_INFO("pkt: "); + for (pp = 0; pp < flen; pp++) + printk(" %02x ", whdr_pos[pp]); + RTW_INFO("\n"); + /* BIP AAD + management frame body + MME(MIC is zero) */ + RTW_INFO("AAD+PKT: "); + for (pp = 0; pp < ori_len; pp++) + RTW_INFO(" %02x ", BIP_AAD[pp]); + RTW_INFO("\n"); + /* show the MIC result */ + RTW_INFO("mic: "); + for (pp = 0; pp < 16; pp++) + RTW_INFO(" %02x ", mic[pp]); + RTW_INFO("\n"); + } #endif - /* MIC field should be last 8 bytes of packet (packet without FCS) */ - if (_rtw_memcmp(mic, pframe + pattrib->pkt_len - 8, 8)) { - pmlmeext->mgnt_80211w_IPN_rx = temp_ipn; - res = _SUCCESS; - } else - RTW_INFO("BIP MIC error!\n"); + /* MIC field should be last 8 bytes of packet (packet without FCS) */ + if (_rtw_memcmp(mic, whdr_pos + flen - 8, 8)) { + *ipn = pkt_ipn; + res = _SUCCESS; } else - res = RTW_RX_HANDLED; + RTW_INFO("BIP MIC error!\n"); + BIP_exit: rtw_mfree(BIP_AAD, ori_len); @@ -2310,9 +2320,9 @@ static u8 os_strlen(const char *s) return p - s; } -static int os_memcmp(void *s1, void *s2, u8 n) +static int os_memcmp(const void *s1, const void *s2, u8 n) { - unsigned char *p1 = s1, *p2 = s2; + const unsigned char *p1 = s1, *p2 = s2; if (n == 0) return 0; @@ -2718,7 +2728,7 @@ static void rijndaelEncrypt(u32 rk[/*44*/], u8 pt[16], u8 ct[16]) PUTU32(ct + 12, s3); } -static void *aes_encrypt_init(u8 *key, size_t len) +static void *aes_encrypt_init(const u8 *key, size_t len) { u32 *rk; if (len != 16) @@ -2768,12 +2778,12 @@ static void aes_encrypt_deinit(void *ctx) * OMAC1 was standardized with the name CMAC by NIST in a Special Publication * (SP) 800-38B. */ -static int omac1_aes_128_vector(u8 *key, size_t num_elem, - u8 *addr[], size_t *len, u8 *mac) +static int omac1_aes_128_vector(const u8 *key, size_t num_elem, + const u8 *addr[], const size_t *len, u8 *mac) { void *ctx; u8 cbc[AES_BLOCK_SIZE], pad[AES_BLOCK_SIZE]; - u8 *pos, *end; + const u8 *pos, *end; size_t i, e, left, total_len; ctx = aes_encrypt_init(key, 16); @@ -2841,12 +2851,237 @@ static int omac1_aes_128_vector(u8 *key, size_t num_elem, * OMAC1 was standardized with the name CMAC by NIST in a Special Publication * (SP) 800-38B. */ /* modify for CONFIG_IEEE80211W */ -int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac) +int omac1_aes_128(const u8 *key, const u8 *data, size_t data_len, u8 *mac) { return omac1_aes_128_vector(key, 1, &data, &data_len, mac); } #endif /* PLATFORM_FREEBSD Baron */ +#ifdef CONFIG_RTW_MESH_AEK +/* for AES-SIV */ +#define os_memset _rtw_memset +#define os_memcpy _rtw_memcpy +#define os_malloc rtw_malloc +#define bin_clear_free(bin, len) \ + do { \ + if (bin) { \ + os_memset(bin, 0, len); \ + rtw_mfree(bin, len); \ + } \ + } while (0) + +static const u8 zero[AES_BLOCK_SIZE]; + +static void dbl(u8 *pad) +{ + int i, carry; + + carry = pad[0] & 0x80; + for (i = 0; i < AES_BLOCK_SIZE - 1; i++) + pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7); + pad[AES_BLOCK_SIZE - 1] <<= 1; + if (carry) + pad[AES_BLOCK_SIZE - 1] ^= 0x87; +} + +static void xor(u8 *a, const u8 *b) +{ + int i; + + for (i = 0; i < AES_BLOCK_SIZE; i++) + *a++ ^= *b++; +} + +static void xorend(u8 *a, int alen, const u8 *b, int blen) +{ + int i; + + if (alen < blen) + return; + + for (i = 0; i < blen; i++) + a[alen - blen + i] ^= b[i]; +} + +static void pad_block(u8 *pad, const u8 *addr, size_t len) +{ + os_memset(pad, 0, AES_BLOCK_SIZE); + os_memcpy(pad, addr, len); + + if (len < AES_BLOCK_SIZE) + pad[len] = 0x80; +} + +static int aes_s2v(const u8 *key, size_t num_elem, const u8 *addr[], + size_t *len, u8 *mac) +{ + u8 tmp[AES_BLOCK_SIZE], tmp2[AES_BLOCK_SIZE]; + u8 *buf = NULL; + int ret; + size_t i; + + if (!num_elem) { + os_memcpy(tmp, zero, sizeof(zero)); + tmp[AES_BLOCK_SIZE - 1] = 1; + return omac1_aes_128(key, tmp, sizeof(tmp), mac); + } + + ret = omac1_aes_128(key, zero, sizeof(zero), tmp); + if (ret) + return ret; + + for (i = 0; i < num_elem - 1; i++) { + ret = omac1_aes_128(key, addr[i], len[i], tmp2); + if (ret) + return ret; + + dbl(tmp); + xor(tmp, tmp2); + } + if (len[i] >= AES_BLOCK_SIZE) { + buf = os_malloc(len[i]); + if (!buf) + return -ENOMEM; + + os_memcpy(buf, addr[i], len[i]); + xorend(buf, len[i], tmp, AES_BLOCK_SIZE); + ret = omac1_aes_128(key, buf, len[i], mac); + bin_clear_free(buf, len[i]); + return ret; + } + + dbl(tmp); + pad_block(tmp2, addr[i], len[i]); + xor(tmp, tmp2); + + return omac1_aes_128(key, tmp, sizeof(tmp), mac); +} + +/** + * aes_128_ctr_encrypt - AES-128 CTR mode encryption + * @key: Key for encryption (16 bytes) + * @nonce: Nonce for counter mode (16 bytes) + * @data: Data to encrypt in-place + * @data_len: Length of data in bytes + * Returns: 0 on success, -1 on failure + */ +int aes_128_ctr_encrypt(const u8 *key, const u8 *nonce, + u8 *data, size_t data_len) +{ + void *ctx; + size_t j, len, left = data_len; + int i; + u8 *pos = data; + u8 counter[AES_BLOCK_SIZE], buf[AES_BLOCK_SIZE]; + + ctx = aes_encrypt_init(key, 16); + if (ctx == NULL) + return -1; + os_memcpy(counter, nonce, AES_BLOCK_SIZE); + + while (left > 0) { + #if 0 + aes_encrypt(ctx, counter, buf); + #else + aes_128_encrypt(ctx, counter, buf); + #endif + + len = (left < AES_BLOCK_SIZE) ? left : AES_BLOCK_SIZE; + for (j = 0; j < len; j++) + pos[j] ^= buf[j]; + pos += len; + left -= len; + + for (i = AES_BLOCK_SIZE - 1; i >= 0; i--) { + counter[i]++; + if (counter[i]) + break; + } + } + aes_encrypt_deinit(ctx); + return 0; +} + +int aes_siv_encrypt(const u8 *key, const u8 *pw, + size_t pwlen, size_t num_elem, + const u8 *addr[], const size_t *len, u8 *out) +{ + const u8 *_addr[6]; + size_t _len[6]; + const u8 *k1 = key, *k2 = key + 16; + u8 v[AES_BLOCK_SIZE]; + size_t i; + u8 *iv, *crypt_pw; + + if (num_elem > ARRAY_SIZE(_addr) - 1) + return -1; + + for (i = 0; i < num_elem; i++) { + _addr[i] = addr[i]; + _len[i] = len[i]; + } + _addr[num_elem] = pw; + _len[num_elem] = pwlen; + + if (aes_s2v(k1, num_elem + 1, _addr, _len, v)) + return -1; + + iv = out; + crypt_pw = out + AES_BLOCK_SIZE; + + os_memcpy(iv, v, AES_BLOCK_SIZE); + os_memcpy(crypt_pw, pw, pwlen); + + /* zero out 63rd and 31st bits of ctr (from right) */ + v[8] &= 0x7f; + v[12] &= 0x7f; + return aes_128_ctr_encrypt(k2, v, crypt_pw, pwlen); +} + +int aes_siv_decrypt(const u8 *key, const u8 *iv_crypt, size_t iv_c_len, + size_t num_elem, const u8 *addr[], const size_t *len, + u8 *out) +{ + const u8 *_addr[6]; + size_t _len[6]; + const u8 *k1 = key, *k2 = key + 16; + size_t crypt_len; + size_t i; + int ret; + u8 iv[AES_BLOCK_SIZE]; + u8 check[AES_BLOCK_SIZE]; + + if (iv_c_len < AES_BLOCK_SIZE || num_elem > ARRAY_SIZE(_addr) - 1) + return -1; + crypt_len = iv_c_len - AES_BLOCK_SIZE; + + for (i = 0; i < num_elem; i++) { + _addr[i] = addr[i]; + _len[i] = len[i]; + } + _addr[num_elem] = out; + _len[num_elem] = crypt_len; + + os_memcpy(iv, iv_crypt, AES_BLOCK_SIZE); + os_memcpy(out, iv_crypt + AES_BLOCK_SIZE, crypt_len); + + iv[8] &= 0x7f; + iv[12] &= 0x7f; + + ret = aes_128_ctr_encrypt(k2, iv, out, crypt_len); + if (ret) + return ret; + + ret = aes_s2v(k1, num_elem + 1, _addr, _len, check); + if (ret) + return ret; + if (os_memcmp(check, iv_crypt, AES_BLOCK_SIZE) == 0) + return 0; + + return -1; +} +#endif /* CONFIG_RTW_MESH_AEK */ + #ifdef CONFIG_TDLS void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta) { @@ -2883,11 +3118,11 @@ void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta) * added by the KDF anyway.. */ - if (os_memcmp(adapter_mac_addr(padapter), psta->hwaddr, ETH_ALEN) < 0) { + if (os_memcmp(adapter_mac_addr(padapter), psta->cmn.mac_addr, ETH_ALEN) < 0) { _rtw_memcpy(data, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(data + ETH_ALEN, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(data + ETH_ALEN, psta->cmn.mac_addr, ETH_ALEN); } else { - _rtw_memcpy(data, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(data, psta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(data + ETH_ALEN, adapter_mac_addr(padapter), ETH_ALEN); } _rtw_memcpy(data + 2 * ETH_ALEN, get_bssid(pmlmepriv), ETH_ALEN); diff --git a/core/rtw_sreset.c b/core/rtw_sreset.c index 6baacb7..09558ed 100644 --- a/core/rtw_sreset.c +++ b/core/rtw_sreset.c @@ -126,31 +126,18 @@ void sreset_restore_security_station(_adapter *padapter) rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); } -#if 0 - if ((padapter->securitypriv.dot11PrivacyAlgrthm == _WEP40_) || - (padapter->securitypriv.dot11PrivacyAlgrthm == _WEP104_)) { - - for (EntryId = 0; EntryId < 4; EntryId++) { - if (EntryId == psecuritypriv->dot11PrivacyKeyIndex) - rtw_set_key(padapter, &padapter->securitypriv, EntryId, 1, _FALSE); - else - rtw_set_key(padapter, &padapter->securitypriv, EntryId, 0, _FALSE); - } - - } else -#endif - if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || - (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) { - psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv)); - if (psta == NULL) { - /* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */ - } else { - /* pairwise key */ - rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE); - /* group key */ - rtw_set_key(padapter, &padapter->securitypriv, padapter->securitypriv.dot118021XGrpKeyid, 0, _FALSE); - } + if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || + (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) { + psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv)); + if (psta == NULL) { + /* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */ + } else { + /* pairwise key */ + rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE); + /* group key */ + rtw_set_key(padapter, &padapter->securitypriv, padapter->securitypriv.dot118021XGrpKeyid, 0, _FALSE); } + } } void sreset_restore_network_station(_adapter *padapter) @@ -179,7 +166,7 @@ void sreset_restore_network_station(_adapter *padapter) } #endif - rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, _FALSE); + rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY); { u8 threshold; @@ -214,6 +201,7 @@ void sreset_restore_network_station(_adapter *padapter) { u8 join_type = 0; rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING); } Set_MSR(padapter, (pmlmeinfo->state & 0x3)); @@ -235,8 +223,8 @@ void sreset_restore_network_status(_adapter *padapter) if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) { RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); sreset_restore_network_station(padapter); - } else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) { - RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); + } else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { + RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(padapter), MLME_IS_AP(padapter) ? "AP" : "MESH"); rtw_ap_restore_network(padapter); } else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); @@ -306,7 +294,7 @@ void sreset_reset(_adapter *padapter) struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; _irqL irqL; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; @@ -337,5 +325,8 @@ void sreset_reset(_adapter *padapter) RTW_INFO("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start)); pdbgpriv->dbg_sreset_cnt++; + + psrtpriv->self_dect_fw = _FALSE; + psrtpriv->rx_cnt = 0; #endif } diff --git a/core/rtw_sta_mgt.c b/core/rtw_sta_mgt.c index 4bd110a..17c0257 100644 --- a/core/rtw_sta_mgt.c +++ b/core/rtw_sta_mgt.c @@ -128,6 +128,46 @@ inline bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, return ret; } +void rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos) +{ + _adapter *adapter = sta->padapter; + struct ethhdr *etherhdr = (struct ethhdr *)ehdr_pos; + + if (ntohs(etherhdr->h_proto) == ETH_P_IP) { + u8 *ip = ehdr_pos + ETH_HLEN; + + if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */ + && rtw_st_ctl_chk_reg_s_proto(&sta->st_ctl, 0x06) == _TRUE + ) { + u8 *tcp = ip + GET_IPV4_IHL(ip) * 4; + + if (rtw_st_ctl_chk_reg_rule(&sta->st_ctl, adapter, IPV4_DST(ip), TCP_DST(tcp), IPV4_SRC(ip), TCP_SRC(tcp)) == _TRUE) { + if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) { + session_tracker_add_cmd(adapter, sta + , IPV4_DST(ip), TCP_DST(tcp) + , IPV4_SRC(ip), TCP_SRC(tcp)); + if (DBG_SESSION_TRACKER) + RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n" + , FUNC_ADPT_ARG(adapter) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))); + } + if (GET_TCP_FIN(tcp)) { + session_tracker_del_cmd(adapter, sta + , IPV4_DST(ip), TCP_DST(tcp) + , IPV4_SRC(ip), TCP_SRC(tcp)); + if (DBG_SESSION_TRACKER) + RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n" + , FUNC_ADPT_ARG(adapter) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))); + } + } + + } + } +} + #define SESSION_TRACKER_FMT IP_FMT":"PORT_FMT" "IP_FMT":"PORT_FMT" %u %d" #define SESSION_TRACKER_ARG(st) IP_ARG(&(st)->local_naddr), PORT_ARG(&(st)->local_port), IP_ARG(&(st)->remote_naddr), PORT_ARG(&(st)->remote_port), (st)->status, rtw_get_passing_time_ms((st)->set_time) @@ -160,8 +200,6 @@ void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl) void _rtw_init_stainfo(struct sta_info *psta); void _rtw_init_stainfo(struct sta_info *psta) { - - _rtw_memset((u8 *)psta, 0, sizeof(struct sta_info)); _rtw_spinlock_init(&psta->lock); @@ -172,62 +210,36 @@ void _rtw_init_stainfo(struct sta_info *psta) /* _rtw_init_listhead(&psta->wakeup_list); */ _rtw_init_queue(&psta->sleep_q); - psta->sleepq_len = 0; _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); _rtw_init_sta_recv_priv(&psta->sta_recvpriv); #ifdef CONFIG_AP_MODE - _rtw_init_listhead(&psta->asoc_list); - _rtw_init_listhead(&psta->auth_list); - - psta->expire_to = 0; - - psta->flags = 0; - - psta->capability = 0; - psta->bpairwise_key_installed = _FALSE; #ifdef CONFIG_RTW_80211R psta->ft_pairwise_key_installed = _FALSE; #endif - -#ifdef CONFIG_NATIVEAP_MLME - psta->nonerp_set = 0; - psta->no_short_slot_time_set = 0; - psta->no_short_preamble_set = 0; - psta->no_ht_gf_set = 0; - psta->no_ht_set = 0; - psta->ht_20mhz_set = 0; - psta->ht_40mhz_intolerant = 0; -#endif - -#ifdef CONFIG_TX_MCAST2UNI - psta->under_exist_checking = 0; -#endif /* CONFIG_TX_MCAST2UNI */ - - psta->keep_alive_trycnt = 0; - #endif /* CONFIG_AP_MODE */ rtw_st_ctl_init(&psta->st_ctl); - - } u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) { + _adapter *adapter = container_of(pstapriv, _adapter, stapriv); + struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter); struct sta_info *psta; s32 i; + u32 ret = _FAIL; + pstapriv->padapter = adapter; pstapriv->pallocated_stainfo_buf = rtw_zvmalloc(sizeof(struct sta_info) * NUM_STA + 4); - if (!pstapriv->pallocated_stainfo_buf) - return _FAIL; + goto exit; pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 - ((SIZE_PTR)(pstapriv->pallocated_stainfo_buf) & 3); @@ -257,9 +269,19 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) pstapriv->adhoc_expire_to = 4; /* 4 * 2 = 8 sec */ #ifdef CONFIG_AP_MODE - - pstapriv->sta_dz_bitmap = 0; - pstapriv->tim_bitmap = 0; + pstapriv->max_aid = macid_ctl->num; + pstapriv->rr_aid = 0; + pstapriv->started_aid = 1; + pstapriv->sta_aid = rtw_zmalloc(pstapriv->max_aid * sizeof(struct sta_info *)); + if (!pstapriv->sta_aid) + goto exit; + pstapriv->aid_bmp_len = AID_BMP_LEN(pstapriv->max_aid); + pstapriv->sta_dz_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len); + if (!pstapriv->sta_dz_bitmap) + goto exit; + pstapriv->tim_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len); + if (!pstapriv->tim_bitmap) + goto exit; _rtw_init_listhead(&pstapriv->asoc_list); _rtw_init_listhead(&pstapriv->auth_list); @@ -285,15 +307,29 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) #endif #if CONFIG_RTW_MACADDR_ACL - _rtw_init_queue(&(pstapriv->acl_list.acl_node_q)); + for (i = 0; i < RTW_ACL_PERIOD_NUM; i++) + rtw_macaddr_acl_init(adapter, i); #endif #if CONFIG_RTW_PRE_LINK_STA rtw_pre_link_sta_ctl_init(pstapriv); #endif - return _SUCCESS; + ret = _SUCCESS; +exit: + if (ret != _SUCCESS) { + if (pstapriv->pallocated_stainfo_buf) + rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info) * NUM_STA + 4); + #ifdef CONFIG_AP_MODE + if (pstapriv->sta_aid) + rtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *)); + if (pstapriv->sta_dz_bitmap) + rtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); + #endif + } + + return ret; } inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta) @@ -426,7 +462,8 @@ u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) rtw_mfree_sta_priv_lock(pstapriv); #if CONFIG_RTW_MACADDR_ACL - _rtw_deinit_queue(&(pstapriv->acl_list.acl_node_q)); + for (index = 0; index < RTW_ACL_PERIOD_NUM; index++) + rtw_macaddr_acl_deinit(pstapriv->padapter, index); #endif #if CONFIG_RTW_PRE_LINK_STA @@ -435,6 +472,14 @@ u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) if (pstapriv->pallocated_stainfo_buf) rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info) * NUM_STA + 4); + #ifdef CONFIG_AP_MODE + if (pstapriv->sta_aid) + rtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *)); + if (pstapriv->sta_dz_bitmap) + rtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); + if (pstapriv->tim_bitmap) + rtw_mfree(pstapriv->tim_bitmap, pstapriv->aid_bmp_len); + #endif } return _SUCCESS; @@ -445,15 +490,15 @@ static void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl) { _adapter *padapter = preorder_ctrl->padapter; +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) rtw_init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter, rtw_reordering_ctrl_timeout_handler, preorder_ctrl); - +#endif } /* struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) */ -struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) +struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) { _irqL irqL, irqL2; - uint tmp_aid; s32 index; _list *phash_list; struct sta_info *psta; @@ -477,14 +522,11 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) rtw_list_delete(&(psta->list)); /* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */ - - tmp_aid = psta->aid; - _rtw_init_stainfo(psta); psta->padapter = pstapriv->padapter; - _rtw_memcpy(psta->hwaddr, hwaddr, ETH_ALEN); + _rtw_memcpy(psta->cmn.mac_addr, hwaddr, ETH_ALEN); index = wifi_mac_hash(hwaddr); @@ -508,8 +550,11 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) * In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable. * So, we initialize the tid_rxseq variable as the 0xffff. */ - for (i = 0; i < 16; i++) + for (i = 0; i < 16; i++) { _rtw_memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2); + _rtw_memcpy(&psta->sta_recvpriv.bmc_tid_rxseq[i], &wRxSeqInitialValue, 2); + _rtw_memset(&psta->sta_recvpriv.rxcache.iv[i], 0, sizeof(psta->sta_recvpriv.rxcache.iv[i])); + } rtw_init_timer(&psta->addba_retry_timer, psta->padapter, addba_timer_hdl, psta); #ifdef CONFIG_IEEE80211W @@ -522,16 +567,14 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) /* for A-MPDU Rx reordering buffer control */ for (i = 0; i < 16 ; i++) { preorder_ctrl = &psta->recvreorder_ctrl[i]; - preorder_ctrl->padapter = pstapriv->padapter; - + preorder_ctrl->tid = i; preorder_ctrl->enable = _FALSE; - preorder_ctrl->indicate_seq = 0xffff; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq); -#endif + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d\n" + , FUNC_ADPT_ARG(pstapriv->padapter), i, preorder_ctrl->indicate_seq); + #endif preorder_ctrl->wend_b = 0xffff; /* preorder_ctrl->wsize_b = (NR_RECVBUFF-2); */ preorder_ctrl->wsize_b = 64;/* 64; */ @@ -544,14 +587,14 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) /* init for DM */ - psta->rssi_stat.undecorated_smoothed_pwdb = (-1); - psta->rssi_stat.undecorated_smoothed_cck = (-1); + psta->cmn.rssi_stat.rssi = (-1); + psta->cmn.rssi_stat.rssi_cck = (-1); + psta->cmn.rssi_stat.rssi_ofdm = (-1); #ifdef CONFIG_ATMEL_RC_PATCH psta->flag_atmel_rc = 0; #endif /* init for the sequence number of received management frame */ psta->RxMgmtFrameSeqNum = 0xffff; - psta->ra_rpt_linked = _FALSE; rtw_alloc_macid(pstapriv->padapter, psta); @@ -580,13 +623,20 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct sta_priv *pstapriv = &padapter->stapriv; struct hw_xmit *phwxmit; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int pending_qcnt[4]; u8 is_pre_link_sta = _FALSE; if (psta == NULL) goto exit; - is_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->hwaddr); +#ifdef CONFIG_RTW_80211K + rm_post_event(padapter, RM_ID_FOR_ALL(psta->cmn.aid), RM_EV_cancel); +#endif + + is_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr); if (is_pre_link_sta == _FALSE) { _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); @@ -673,7 +723,6 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) #ifdef CONFIG_TDLS psta->tdls_sta_state = TDLS_STATE_NONE; - rtw_free_tdls_timer(psta); #endif /* CONFIG_TDLS */ /* for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer */ @@ -710,7 +759,7 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) } - if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->hwaddr)) && is_pre_link_sta == _FALSE) + if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->cmn.mac_addr)) && is_pre_link_sta == _FALSE) rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE); @@ -749,14 +798,16 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) #ifdef CONFIG_NATIVEAP_MLME - pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); - pstapriv->tim_bitmap &= ~BIT(psta->aid); + if (pmlmeinfo->state == _HW_STATE_AP_) { + rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); - /* rtw_indicate_sta_disassoc_event(padapter, psta); */ + /* rtw_indicate_sta_disassoc_event(padapter, psta); */ - if ((psta->aid > 0) && (pstapriv->sta_aid[psta->aid - 1] == psta)) { - pstapriv->sta_aid[psta->aid - 1] = NULL; - psta->aid = 0; + if ((psta->cmn.aid > 0) && (pstapriv->sta_aid[psta->cmn.aid - 1] == psta)) { + pstapriv->sta_aid[psta->cmn.aid - 1] = NULL; + psta->cmn.aid = 0; + } } #endif /* CONFIG_NATIVEAP_MLME */ @@ -812,7 +863,7 @@ void rtw_free_all_stainfo(_adapter *padapter) plist = get_next(plist); if (pbcmc_stainfo != psta) { - if (rtw_is_pre_link_sta(pstapriv, psta->hwaddr) == _FALSE) + if (rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr) == _FALSE) rtw_list_delete(&psta->hash_list); stainfo_offset = rtw_stainfo_offset(pstapriv, psta); @@ -836,7 +887,7 @@ void rtw_free_all_stainfo(_adapter *padapter) } /* any station allocated can be searched by hash list */ -struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) +struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) { _irqL irqL; @@ -847,7 +898,7 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) u32 index; - u8 *addr; + const u8 *addr; u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; @@ -872,7 +923,7 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); - if ((_rtw_memcmp(psta->hwaddr, addr, ETH_ALEN)) == _TRUE) { + if ((_rtw_memcmp(psta->cmn.mac_addr, addr, ETH_ALEN)) == _TRUE) { /* if found the matched address */ break; } @@ -904,9 +955,10 @@ u32 rtw_init_bcmc_stainfo(_adapter *padapter) goto exit; } #ifdef CONFIG_BEAMFORMING - psta->txbf_gid = 63; - psta->txbf_paid = 0; + psta->cmn.bf_info.g_id = 63; + psta->cmn.bf_info.p_aid = 0; #endif + ptxservq = &(psta->sta_xmitpriv.be_q); /* @@ -934,14 +986,75 @@ struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter) } +#ifdef CONFIG_AP_MODE +u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta) +{ + struct sta_priv *stapriv = &adapter->stapriv; + u16 aid, i, used_cnt = 0; + + for (i = 0; i < stapriv->max_aid; i++) { + aid = ((i + stapriv->started_aid - 1) % stapriv->max_aid) + 1; + if (stapriv->sta_aid[aid - 1] == NULL) + break; + if (++used_cnt >= stapriv->max_num_sta) + break; + } + + /* check for aid limit and assoc limit */ + if (i >= stapriv->max_aid || used_cnt >= stapriv->max_num_sta) + aid = 0; + + sta->cmn.aid = aid; + if (aid) { + stapriv->sta_aid[aid - 1] = sta; + if (stapriv->rr_aid) + stapriv->started_aid = (aid % stapriv->max_aid) + 1; + } + + return aid; +} + +void dump_aid_status(void *sel, _adapter *adapter) +{ + struct sta_priv *stapriv = &adapter->stapriv; + u8 *aid_bmp; + u16 i, used_cnt = 0; + + aid_bmp = rtw_zmalloc(stapriv->aid_bmp_len); + if (!aid_bmp) + return; + + for (i = 1; i <= stapriv->max_aid; i++) { + if (stapriv->sta_aid[i - 1]) { + aid_bmp[i / 8] |= BIT(i % 8); + ++used_cnt; + } + } + + RTW_PRINT_SEL(sel, "used_cnt:%u/%u\n", used_cnt, stapriv->max_aid); + RTW_MAP_DUMP_SEL(sel, "aid_map:", aid_bmp, stapriv->aid_bmp_len); + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "%-2s %-11s\n", "rr", "started_aid"); + RTW_PRINT_SEL(sel, "%2d %11d\n", stapriv->rr_aid, stapriv->started_aid); + + rtw_mfree(aid_bmp, stapriv->aid_bmp_len); +} +#endif /* CONFIG_AP_MODE */ + #if CONFIG_RTW_MACADDR_ACL -const char *const _acl_mode_str[] = { +const char *const _acl_period_str[RTW_ACL_PERIOD_NUM] = { + "DEV", + "BSS", +}; + +const char *const _acl_mode_str[RTW_ACL_MODE_MAX] = { "DISABLED", "ACCEPT_UNLESS_LISTED", "DENY_UNLESS_LISTED", }; -u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr) +u8 _rtw_access_ctrl(_adapter *adapter, u8 period, const u8 *mac_addr) { u8 res = _TRUE; _irqL irqL; @@ -949,8 +1062,20 @@ u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr) struct rtw_wlan_acl_node *acl_node; u8 match = _FALSE; struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; - _queue *acl_node_q = &acl->acl_node_q; + struct wlan_acl_pool *acl; + _queue *acl_node_q; + + if (period >= RTW_ACL_PERIOD_NUM) { + rtw_warn_on(1); + goto exit; + } + + acl = &stapriv->acl_list[period]; + acl_node_q = &acl->acl_node_q; + + if (acl->mode != RTW_ACL_MODE_ACCEPT_UNLESS_LISTED + && acl->mode != RTW_ACL_MODE_DENY_UNLESS_LISTED) + goto exit; _enter_critical_bh(&(acl_node_q->lock), &irqL); head = get_list_head(acl_node_q); @@ -970,26 +1095,42 @@ u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr) if (acl->mode == RTW_ACL_MODE_ACCEPT_UNLESS_LISTED) res = (match == _TRUE) ? _FALSE : _TRUE; - else if (acl->mode == RTW_ACL_MODE_DENY_UNLESS_LISTED) + else /* RTW_ACL_MODE_DENY_UNLESS_LISTED */ res = (match == _TRUE) ? _TRUE : _FALSE; - else - res = _TRUE; +exit: return res; } -void dump_macaddr_acl(void *sel, _adapter *adapter) +u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr) { - struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; int i; - RTW_PRINT_SEL(sel, "mode:%s(%d)\n", acl_mode_str(acl->mode), acl->mode); - RTW_PRINT_SEL(sel, "num:%d/%d\n", acl->num, NUM_ACL); - for (i = 0; i < NUM_ACL; i++) { - if (acl->aclnode[i].valid == _FALSE) - continue; - RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(acl->aclnode[i].addr)); + for (i = 0; i < RTW_ACL_PERIOD_NUM; i++) + if (_rtw_access_ctrl(adapter, i, mac_addr) == _FALSE) + return _FALSE; + + return _TRUE; +} + +void dump_macaddr_acl(void *sel, _adapter *adapter) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct wlan_acl_pool *acl; + int i, j; + + for (j = 0; j < RTW_ACL_PERIOD_NUM; j++) { + RTW_PRINT_SEL(sel, "period:%s(%d)\n", acl_period_str(j), j); + + acl = &stapriv->acl_list[j]; + RTW_PRINT_SEL(sel, "mode:%s(%d)\n", acl_mode_str(acl->mode), acl->mode); + RTW_PRINT_SEL(sel, "num:%d/%d\n", acl->num, NUM_ACL); + for (i = 0; i < NUM_ACL; i++) { + if (acl->aclnode[i].valid == _FALSE) + continue; + RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(acl->aclnode[i].addr)); + } + RTW_PRINT_SEL(sel, "\n"); } } #endif /* CONFIG_RTW_MACADDR_ACL */ diff --git a/core/rtw_tdls.c b/core/rtw_tdls.c index ecf1277..07395fc 100644 --- a/core/rtw_tdls.c +++ b/core/rtw_tdls.c @@ -22,7 +22,12 @@ extern unsigned char MCS_rate_2R[16]; extern unsigned char MCS_rate_1R[16]; -extern void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame); + +inline void rtw_tdls_set_link_established(_adapter *adapter, bool en) +{ + adapter->tdlsinfo.link_established = en; + rtw_mi_update_iface_status(&(adapter->mlmepriv), 0); +} void rtw_reset_tdls_info(_adapter *padapter) { @@ -36,7 +41,7 @@ void rtw_reset_tdls_info(_adapter *padapter) else ptdlsinfo->ch_switch_prohibited = _TRUE; - ptdlsinfo->link_established = _FALSE; + rtw_tdls_set_link_established(padapter, _FALSE); ptdlsinfo->sta_cnt = 0; ptdlsinfo->sta_maximum = _FALSE; @@ -57,6 +62,8 @@ void rtw_reset_tdls_info(_adapter *padapter) #ifdef CONFIG_WFD ptdlsinfo->wfd_info = &padapter->wfd_info; #endif + + ptdlsinfo->tdls_sctx = NULL; } int rtw_init_tdls_info(_adapter *padapter) @@ -66,7 +73,6 @@ int rtw_init_tdls_info(_adapter *padapter) rtw_reset_tdls_info(padapter); - ptdlsinfo->tdls_enable = _TRUE; #ifdef CONFIG_TDLS_DRIVER_SETUP ptdlsinfo->driver_setup = _TRUE; #else @@ -89,6 +95,60 @@ void rtw_free_tdls_info(struct tdls_info *ptdlsinfo) } +void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + _irqL irqL; + _list *plist, *phead; + s32 index; + struct sta_info *psta = NULL; + struct sta_info *ptdls_sta[NUM_STA]; + u8 empty_hwaddr[ETH_ALEN] = { 0x00 }; + + _rtw_memset(ptdls_sta, 0x00, sizeof(ptdls_sta)); + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (index = 0; index < NUM_STA; index++) { + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); + + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + + plist = get_next(plist); + + if (psta->tdls_sta_state != TDLS_STATE_NONE) + ptdls_sta[index] = psta; + } + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (index = 0; index < NUM_STA; index++) { + if (ptdls_sta[index]) { + struct TDLSoption_param tdls_param; + + psta = ptdls_sta[index]; + + RTW_INFO("Do tear down to "MAC_FMT" by enqueue_cmd = %d\n", MAC_ARG(psta->cmn.mac_addr), enqueue_cmd); + + _rtw_memcpy(&(tdls_param.addr), psta->cmn.mac_addr, ETH_ALEN); + tdls_param.option = TDLS_TEARDOWN_STA_NO_WAIT; + tdls_hdl(padapter, (unsigned char *)&(tdls_param)); + + rtw_tdls_teardown_pre_hdl(padapter, psta); + + if (enqueue_cmd == _TRUE) + rtw_tdls_cmd(padapter, psta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + else + { + tdls_param.option = TDLS_TEARDOWN_STA_LOCALLY_POST; + tdls_hdl(padapter, (unsigned char *)&(tdls_param)); + } + } + } +} + int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len) { u8 tdls_prohibited_bit = 0x40; /* bit(38); TDLS_prohibited */ @@ -117,10 +177,86 @@ int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len) return _FALSE; } +u8 rtw_is_tdls_enabled(_adapter *padapter) +{ + return padapter->registrypriv.en_tdls; +} + +void rtw_set_tdls_enable(_adapter *padapter, u8 enable) +{ + padapter->registrypriv.en_tdls = enable; + RTW_INFO("%s: en_tdls = %d\n", __func__, rtw_is_tdls_enabled(padapter)); +} + +void rtw_enable_tdls_func(_adapter *padapter) +{ + if (rtw_is_tdls_enabled(padapter) == _TRUE) + return; + +#if 0 +#ifdef CONFIG_MCC_MODE + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC) == _TRUE) { + RTW_INFO("[TDLS] MCC is running, can't enable TDLS !\n"); + return; + } +#endif +#endif + rtw_set_tdls_enable(padapter, _TRUE); +} + +void rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd) +{ + if (rtw_is_tdls_enabled(padapter) == _FALSE) + return; + + rtw_free_all_tdls_sta(padapter, enqueue_cmd); + rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR); + rtw_reset_tdls_info(padapter); + + rtw_set_tdls_enable(padapter, _FALSE); +} + +u8 rtw_is_tdls_sta_existed(_adapter *padapter) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + int i = 0; + _irqL irqL; + _list *plist, *phead; + u8 ret = _FALSE; + + if (rtw_is_tdls_enabled(padapter) == _FALSE) + return _FALSE; + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + if (psta->tdls_sta_state != TDLS_STATE_NONE) { + ret = _TRUE; + goto Exit; + } + } + } + +Exit: + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + return ret; +} + u8 rtw_tdls_is_setup_allowed(_adapter *padapter) { struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + if (is_client_associated_to_ap(padapter) == _FALSE) + return _FALSE; + if (ptdlsinfo->ap_prohibited == _TRUE) return _FALSE; @@ -142,7 +278,7 @@ u8 rtw_tdls_is_chsw_allowed(_adapter *padapter) } #endif -int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack) +int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ms) { int ret = _FAIL; struct xmit_frame *pmgntframe; @@ -200,8 +336,8 @@ int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsi pattrib->last_txcmdsz = pattrib->pktlen; - if (wait_ack) - ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + if (wait_ms) + ret = dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, wait_ms); else { dump_mgntframe(padapter, pmgntframe); ret = _SUCCESS; @@ -221,7 +357,7 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig { int ret; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -229,9 +365,9 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig psta = rtw_get_stainfo(&padapter->stapriv, da); if (psta) { if (power_mode) - rtw_hal_macid_sleep(padapter, psta->mac_id); + rtw_hal_macid_sleep(padapter, psta->cmn.mac_id); else - rtw_hal_macid_wakeup(padapter, psta->mac_id); + rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id); } else { RTW_INFO(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n", FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode ? "sleep" : "wakeup"); @@ -240,7 +376,7 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig #endif do { - ret = _issue_nulldata_to_TDLS_peer_STA(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE); + ret = _issue_nulldata_to_TDLS_peer_STA(padapter, da, power_mode, wait_ms); i++; @@ -273,37 +409,6 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig return ret; } -void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta) -{ - struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - struct sta_priv *pstapriv = &padapter->stapriv; - _irqL irqL; - - /* free peer sta_info */ - _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); - if (ptdlsinfo->sta_cnt != 0) - ptdlsinfo->sta_cnt--; - _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); - /* -2: AP + BC/MC sta, -4: default key */ - if (ptdlsinfo->sta_cnt < MAX_ALLOWED_TDLS_STA_NUM) { - ptdlsinfo->sta_maximum = _FALSE; - _rtw_memset(&ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record)); - } - - /* clear cam */ - rtw_clearstakey_cmd(padapter, ptdls_sta, _TRUE); - - if (ptdlsinfo->sta_cnt == 0) { - rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR); - ptdlsinfo->link_established = _FALSE; - } else - RTW_INFO("Remain tdls sta:%02x\n", ptdlsinfo->sta_cnt); - - rtw_free_stainfo(padapter, ptdls_sta); - -} - - /* TDLS encryption(if needed) will always be CCMP */ void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta) { @@ -328,8 +433,10 @@ void rtw_tdls_process_ht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 ptdls_sta->flags |= WLAN_STA_WME; _rtw_memcpy(&ptdls_sta->htpriv.ht_cap, data, sizeof(struct rtw_ieee80211_ht_cap)); - } else + } else { ptdls_sta->flags &= ~WLAN_STA_HT; + return; + } if (ptdls_sta->flags & WLAN_STA_HT) { if (padapter->registrypriv.ht_enable == _TRUE) { @@ -361,17 +468,17 @@ void rtw_tdls_process_ht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 ptdls_sta->htpriv.rx_ampdu_min_spacing = max_AMPDU_len | min_MPDU_spacing; /* Check if sta support s Short GI 20M */ - if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20)) + if ((phtpriv->sgi_20m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20))) ptdls_sta->htpriv.sgi_20m = _TRUE; /* Check if sta support s Short GI 40M */ - if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) + if ((phtpriv->sgi_40m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_40))) ptdls_sta->htpriv.sgi_40m = _TRUE; /* Bwmode would still followed AP's setting */ if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) { if (padapter->mlmeextpriv.cur_bwmode >= CHANNEL_WIDTH_40) - ptdls_sta->bw_mode = CHANNEL_WIDTH_40; + ptdls_sta->cmn.bw_mode = CHANNEL_WIDTH_40; ptdls_sta->htpriv.ch_offset = padapter->mlmeextpriv.cur_ch_offset; } @@ -410,6 +517,11 @@ u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattr { rtw_ht_use_default_setting(padapter); + if (padapter->registrypriv.wifi_spec == 1) { + padapter->mlmepriv.htpriv.sgi_20m = _FALSE; + padapter->mlmepriv.htpriv.sgi_40m = _FALSE; + } + rtw_restructure_ht_ie(padapter, NULL, pframe, 0, &(pattrib->pktlen), padapter->mlmeextpriv.cur_channel); return pframe + pattrib->pktlen; @@ -440,8 +552,10 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 #else ptdls_sta->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80; #endif - } else + } else { ptdls_sta->flags &= ~WLAN_STA_VHT; + return; + } if (ptdls_sta->flags & WLAN_STA_VHT) { if (REGSTY_IS_11AC_ENABLE(&padapter->registrypriv) @@ -471,6 +585,7 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 } ptdls_sta->vhtpriv.stbc_cap = cur_stbc_cap; + #ifdef CONFIG_BEAMFORMING /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) && GET_VHT_CAPABILITY_ELE_SU_BFEE(data)) @@ -483,6 +598,7 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 ptdls_sta->vhtpriv.beamform_cap = cur_beamform_cap; if (cur_beamform_cap) RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap); + #endif /*CONFIG_BEAMFORMING*/ /* B23 B24 B25 Maximum A-MPDU Length Exponent */ ptdls_sta->vhtpriv.ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(data); @@ -494,6 +610,56 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 ptdls_sta->vhtpriv.vht_highest_rate = rtw_get_vht_highest_rate(ptdls_sta->vhtpriv.vht_mcs_map); } +void rtw_tdls_process_vht_operation(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct registry_priv *regsty = adapter_to_regsty(padapter); + u8 operation_bw = 0; + + if (GET_VHT_OPERATION_ELE_CHL_WIDTH(data) >= 1) { + + operation_bw = CHANNEL_WIDTH_80; + + if (hal_is_bw_support(padapter, operation_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, operation_bw) + && (operation_bw <= pmlmeext->cur_bwmode)) + ptdls_sta->cmn.bw_mode = operation_bw; + else + ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode; + } else + ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode; +} + +void rtw_tdls_process_vht_op_mode_notify(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct registry_priv *regsty = adapter_to_regsty(padapter); + u8 target_bw; + u8 target_rxss, current_rxss; + + if (pvhtpriv->vht_option == _FALSE) + return; + + target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(data); + target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(data) + 1); + + if (hal_is_bw_support(padapter, target_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw) + && (target_bw <= pmlmeext->cur_bwmode)) + ptdls_sta->cmn.bw_mode = target_bw; + else + ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode; + + current_rxss = rtw_vht_mcsmap_to_nss(ptdls_sta->vhtpriv.vht_mcs_map); + if (target_rxss != current_rxss) { + u8 vht_mcs_map[2] = {}; + + rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, ptdls_sta->vhtpriv.vht_mcs_map); + _rtw_memcpy(ptdls_sta->vhtpriv.vht_mcs_map, vht_mcs_map, 2); + } +} + u8 *rtw_tdls_set_aid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib) { return rtw_set_ie(pframe, EID_AID, 2, (u8 *)&(padapter->mlmepriv.cur_network.aid), &(pattrib->pktlen)); @@ -595,7 +761,9 @@ u8 *rtw_tdls_set_ftie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib _rtw_memcpy(FTIE.Anonce, ANonce, WPA_NONCE_LEN); if (SNonce != NULL) _rtw_memcpy(FTIE.Snonce, SNonce, WPA_NONCE_LEN); - return rtw_set_ie(pframe, _FTIE_ , 82, (u8 *)FTIE.mic_ctrl, &(pattrib->pktlen)); + + return rtw_set_ie(pframe, _FTIE_, TDLS_FTIE_DATA_LEN, + (u8 *)FTIE.data, &(pattrib->pktlen)); } } @@ -714,15 +882,19 @@ u8 *rtw_tdls_set_sup_reg_class(u8 *pframe, struct pkt_attrib *pattrib) return rtw_set_ie(pframe, _SRC_IE_ , sizeof(TDLS_SRC), TDLS_SRC, &(pattrib->pktlen)); } -u8 *rtw_tdls_set_linkid(u8 *pframe, struct pkt_attrib *pattrib, u8 init) +u8 *rtw_tdls_set_linkid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 init) { + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 link_id_addr[18] = {0}; + + _rtw_memcpy(link_id_addr, get_my_bssid(&(pmlmeinfo->network)), 6); + if (init == _TRUE) { - _rtw_memcpy(link_id_addr, pattrib->ra, 6); _rtw_memcpy((link_id_addr + 6), pattrib->src, 6); _rtw_memcpy((link_id_addr + 12), pattrib->dst, 6); } else { - _rtw_memcpy(link_id_addr, pattrib->ra, 6); _rtw_memcpy((link_id_addr + 6), pattrib->dst, 6); _rtw_memcpy((link_id_addr + 12), pattrib->src, 6); } @@ -755,6 +927,20 @@ u8 *rtw_tdls_set_ch_sw(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info * void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable) { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (enable == _TRUE) { +#ifdef CONFIG_TDLS_CH_SW_V2 + pHalData->ch_switch_offload = _TRUE; +#endif + +#ifdef CONFIG_TDLS_CH_SW_BY_DRV + pHalData->ch_switch_offload = _FALSE; +#endif + } + else + pHalData->ch_switch_offload = _FALSE; + if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) != enable) ATOMIC_SET(&padapter->tdlsinfo.chsw_info.chsw_on, enable); @@ -805,10 +991,14 @@ s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_ty ch_sw_time_start = rtw_systime_to_ms(rtw_get_current_time()); - rtw_tdls_chsw_oper_init(padapter, TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT); - /* set mac_id sleep before channel switch */ - rtw_hal_macid_sleep(padapter, ptdls_sta->mac_id); + rtw_hal_macid_sleep(padapter, ptdls_sta->cmn.mac_id); + +#if defined(CONFIG_TDLS_CH_SW_BY_DRV) || defined(CONFIG_TDLS_CH_SW_V2) + set_channel_bwmode(padapter, channel, channel_offset, bwmode); + ret = _SUCCESS; +#else + rtw_tdls_chsw_oper_init(padapter, TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT); /* channel switch IOs offload to FW */ if (rtw_hal_ch_sw_oper_offload(padapter, channel, channel_offset, bwmode) == _SUCCESS) { @@ -844,25 +1034,27 @@ s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_ty if (take_care_iqk == _TRUE) rtw_hal_ch_sw_iqk_info_restore(padapter, CH_SW_USE_CASE_TDLS); - ch_sw_time_spent = rtw_systime_to_ms(rtw_get_current_time()) - ch_sw_time_start; - - if (chnl_type == TDLS_CH_SW_OFF_CHNL) { - if ((u32)ch_switch_time / 1000 > ch_sw_time_spent) - wait_time = (u32)ch_switch_time / 1000 - ch_sw_time_spent; - else - wait_time = 0; - - if (wait_time > 0) - rtw_msleep_os(wait_time); - } - ret = _SUCCESS; } else RTW_INFO("[TDLS] chsw oper wait fail !!\n"); } +#endif + + if (ret == _SUCCESS) { + ch_sw_time_spent = rtw_systime_to_ms(rtw_get_current_time()) - ch_sw_time_start; + if (chnl_type == TDLS_CH_SW_OFF_CHNL) { + if ((u32)ch_switch_time / 1000 > ch_sw_time_spent) + wait_time = (u32)ch_switch_time / 1000 - ch_sw_time_spent; + else + wait_time = 0; + + if (wait_time > 0) + rtw_msleep_os(wait_time); + } + } /* set mac_id wakeup after channel switch */ - rtw_hal_macid_wakeup(padapter, ptdls_sta->mac_id); + rtw_hal_macid_wakeup(padapter, ptdls_sta->cmn.mac_id); return ret; } @@ -1024,27 +1216,24 @@ int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wa RTW_INFO("[TDLS] %s\n", __FUNCTION__); - ptxmgmt->action_code = TDLS_SETUP_REQUEST; if (rtw_tdls_is_setup_allowed(padapter) == _FALSE) goto exit; - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) + if (IS_MCAST(ptxmgmt->peer)) goto exit; - pattrib = &pmgntframe->attrib; - pmgntframe->frame_tag = DATA_FRAMETAG; - pattrib->ether_type = 0x890d; - - _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN); - _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); - _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer); + if (ptdlsinfo->sta_maximum == _TRUE) { + if (ptdls_sta == NULL) + goto exit; + else if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) + goto exit; + } - update_tdls_attrib(padapter, pattrib); + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; - /* init peer sta_info */ - ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer); if (ptdls_sta == NULL) { ptdls_sta = rtw_alloc_stainfo(pstapriv, ptxmgmt->peer); if (ptdls_sta == NULL) { @@ -1053,10 +1242,21 @@ int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wa rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } + ptdlsinfo->sta_cnt++; } - if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) - ptdlsinfo->sta_cnt++; + ptxmgmt->action_code = TDLS_SETUP_REQUEST; + + pattrib = &pmgntframe->attrib; + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + update_tdls_attrib(padapter, pattrib); if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM) ptdlsinfo->sta_maximum = _TRUE; @@ -1088,25 +1288,19 @@ int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wa return ret; } -int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack) +int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta, u8 wait_ack) { struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *ptdls_sta = NULL; _irqL irqL; int ret = _FAIL; RTW_INFO("[TDLS] %s\n", __FUNCTION__); ptxmgmt->action_code = TDLS_TEARDOWN; - ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer); - if (ptdls_sta == NULL) { - RTW_INFO("Np tdls_sta for tearing down\n"); - goto exit; - } pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) @@ -1122,7 +1316,12 @@ int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wai _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN); _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + + if (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) + _rtw_memcpy(pattrib->ra, ptxmgmt->peer, ETH_ALEN); + else + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); update_tdls_attrib(padapter, pattrib); @@ -1145,9 +1344,6 @@ int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wai ret = _SUCCESS; } - if (rtw_tdls_is_driver_setup(padapter)) - rtw_tdls_cmd(padapter, ptxmgmt->peer, TDLS_TEARDOWN_STA_LOCALLY); - exit: return ret; @@ -1155,15 +1351,28 @@ int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wai int issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack) { + struct sta_info *ptdls_sta = NULL; int ret = _FAIL; - ret = _issue_tdls_teardown(padapter, ptxmgmt, wait_ack); + ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), ptxmgmt->peer); + if (ptdls_sta == NULL) { + RTW_INFO("No tdls_sta for tearing down\n"); + goto exit; + } + + ret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack); if ((ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) && (ret == _FAIL)) { /* Change status code and send teardown again via AP */ ptxmgmt->status_code = _RSON_TDLS_TEAR_TOOFAR_; - ret = _issue_tdls_teardown(padapter, ptxmgmt, wait_ack); + ret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack); + } + + if (rtw_tdls_is_driver_setup(padapter)) { + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptxmgmt->peer, TDLS_TEARDOWN_STA_LOCALLY_POST); } +exit: return ret; } @@ -1365,9 +1574,9 @@ int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *ptdls_sta, pmgntframe->frame_tag = DATA_FRAMETAG; pattrib->ether_type = 0x890d; - _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); update_tdls_attrib(padapter, pattrib); @@ -1410,7 +1619,7 @@ int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdl pmgntframe->frame_tag = DATA_FRAMETAG; pattrib->ether_type = 0x890d; - _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); @@ -1463,9 +1672,9 @@ int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta) pmgntframe->frame_tag = DATA_FRAMETAG; pattrib->ether_type = 0x890d; - _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); update_tdls_attrib(padapter, pattrib); @@ -1549,10 +1758,13 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) struct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib); struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo); u8 empty_addr[ETH_ALEN] = { 0x00 }; - int undecorated_smoothed_pwdb; + int rssi = 0; struct tdls_txmgmt txmgmt; int ret = _SUCCESS; + if (psta) + rssi = psta->cmn.rssi_stat.rssi; + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); /* WFDTDLS: for sigma test, not to setup direct link automatically */ ptdlsinfo->dev_discovered = _TRUE; @@ -1568,11 +1780,11 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) if (ptdlsinfo->sta_maximum == _TRUE && ptdls_sta->alive_count >= 1) { if (_rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) { _rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN); - ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.RxPWDBAll; + ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all; } else { - if (ptdlsinfo->ss_record.RxPWDBAll < pattrib->phy_info.RxPWDBAll) { + if (ptdlsinfo->ss_record.RxPWDBAll < pattrib->phy_info.rx_pwdb_all) { _rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN); - ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.RxPWDBAll; + ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all; } } } @@ -1583,7 +1795,7 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) ret = _FAIL; goto exit; } else { - if (pattrib->phy_info.RxPWDBAll > ptdlsinfo->ss_record.RxPWDBAll) { + if (pattrib->phy_info.rx_pwdb_all > ptdlsinfo->ss_record.RxPWDBAll) { _rtw_memcpy(txmgmt.peer, ptdlsinfo->ss_record.macaddr, ETH_ALEN); /* issue_tdls_teardown(padapter, ptdlsinfo->ss_record.macaddr, _FALSE); */ } else { @@ -1593,10 +1805,9 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) } } - rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &undecorated_smoothed_pwdb); - if (pattrib->phy_info.RxPWDBAll + TDLS_SIGNAL_THRESH >= undecorated_smoothed_pwdb) { - RTW_INFO("pattrib->RxPWDBAll=%d, pdmpriv->undecorated_smoothed_pwdb=%d\n", pattrib->phy_info.RxPWDBAll, undecorated_smoothed_pwdb); + if (pattrib->phy_info.rx_pwdb_all + TDLS_SIGNAL_THRESH >= rssi) { + RTW_INFO("pattrib->RxPWDBAll=%d, pdmpriv->undecorated_smoothed_pwdb=%d\n", pattrib->phy_info.rx_pwdb_all, rssi); _rtw_memcpy(txmgmt.peer, psa, ETH_ALEN); issue_tdls_setup_req(padapter, &txmgmt, _FALSE); } @@ -1608,11 +1819,10 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) } -sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) +sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; u8 *psa, *pmyid; - struct sta_info *ptdls_sta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; u8 *ptr = precv_frame->u.hdr.rx_data; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -1637,7 +1847,13 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); psa = get_sa(ptr); - ptdls_sta = rtw_get_stainfo(pstapriv, psa); + + if (ptdlsinfo->sta_maximum == _TRUE) { + if (ptdls_sta == NULL) + goto exit; + else if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) + goto exit; + } pmyid = adapter_mac_addr(padapter); ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN; @@ -1647,11 +1863,15 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) - prx_pkt_attrib->icv_len - LLC_HEADER_SIZE - ETH_TYPE_LEN - - PAYLOAD_TYPE_LEN - - FIXED_IE; + - PAYLOAD_TYPE_LEN; - if (ptdls_sta == NULL) + if (ptdls_sta == NULL) { ptdls_sta = rtw_alloc_stainfo(pstapriv, psa); + if (ptdls_sta == NULL) + goto exit; + + ptdlsinfo->sta_cnt++; + } else { if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) { /* If the direct link is already set up */ @@ -1695,7 +1915,7 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) case _COUNTRY_IE_: break; case _EXT_SUPPORTEDRATES_IE_: - if (supportRateNum <= sizeof(supportRate)) { + if (supportRateNum < sizeof(supportRate)) { _rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length); supportRateNum += pIE->Length; } @@ -1789,8 +2009,6 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) ptdls_sta->bssratelen = supportRateNum; _rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum); - if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) - ptdlsinfo->sta_cnt++; /* -2: AP + BC/MC sta, -4: default key */ if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM) ptdlsinfo->sta_maximum = _TRUE; @@ -1809,8 +2027,10 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) if (txmgmt.status_code == _STATS_SUCCESSFUL_) _set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME); - else - free_tdls_sta(padapter, ptdls_sta); + else { + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + } } exit: @@ -1818,11 +2038,10 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } -int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) +int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct registry_priv *pregistrypriv = &padapter->registrypriv; struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - struct sta_info *ptdls_sta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; u8 *ptr = precv_frame->u.hdr.rx_data; _irqL irqL; @@ -1844,13 +2063,6 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); psa = get_sa(ptr); - ptdls_sta = rtw_get_stainfo(pstapriv, psa); - - if (ptdls_sta == NULL) { - RTW_INFO("[%s] Direct Link Peer = "MAC_FMT" not found\n", __func__, MAC_ARG(psa)); - ret = _FAIL; - goto exit; - } ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN; parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len @@ -1859,14 +2071,14 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) - prx_pkt_attrib->icv_len - LLC_HEADER_SIZE - ETH_TYPE_LEN - - PAYLOAD_TYPE_LEN - - FIXED_IE; + - PAYLOAD_TYPE_LEN; _rtw_memcpy(&status_code, ptr + 2, 2); if (status_code != 0) { RTW_INFO("[TDLS] %s status_code = %d, free_tdls_sta\n", __FUNCTION__, status_code); - free_tdls_sta(padapter, ptdls_sta); + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); ret = _FAIL; goto exit; } @@ -1885,7 +2097,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) case _COUNTRY_IE_: break; case _EXT_SUPPORTEDRATES_IE_: - if (supportRateNum <= sizeof(supportRate)) { + if (supportRateNum < sizeof(supportRate)) { _rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length); supportRateNum += pIE->Length; } @@ -1933,7 +2145,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) rtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length); break; case EID_OpModeNotification: - rtw_process_vht_op_mode_notify(padapter, pIE->data, ptdls_sta); + rtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length); break; #endif case EID_BSSCoexistence: @@ -1957,35 +2169,31 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length); #endif - if (status_code != _STATS_SUCCESSFUL_) - txmgmt.status_code = status_code; - else { - if (prx_pkt_attrib->encrypt) { - if (verify_ccmp == 1) { - txmgmt.status_code = _STATS_SUCCESSFUL_; - if (rtw_tdls_is_driver_setup(padapter) == _TRUE) { - wpa_tdls_generate_tpk(padapter, ptdls_sta); - if (tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL) { - RTW_INFO("[TDLS] %s tdls_verify_mic fail, free_tdls_sta\n", __FUNCTION__); - free_tdls_sta(padapter, ptdls_sta); - ret = _FAIL; - goto exit; - } - ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval; + if (prx_pkt_attrib->encrypt) { + if (verify_ccmp == 1) { + txmgmt.status_code = _STATS_SUCCESSFUL_; + if (rtw_tdls_is_driver_setup(padapter) == _TRUE) { + wpa_tdls_generate_tpk(padapter, ptdls_sta); + if (tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL) { + RTW_INFO("[TDLS] %s tdls_verify_mic fail, free_tdls_sta\n", __FUNCTION__); + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + ret = _FAIL; + goto exit; } - } else - txmgmt.status_code = _STATS_INVALID_RSNIE_; - + ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval; + } } else - txmgmt.status_code = _STATS_SUCCESSFUL_; - } + txmgmt.status_code = _STATS_INVALID_RSNIE_; + } else + txmgmt.status_code = _STATS_SUCCESSFUL_; if (rtw_tdls_is_driver_setup(padapter) == _TRUE) { _rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN); issue_tdls_setup_cfm(padapter, &txmgmt); if (txmgmt.status_code == _STATS_SUCCESSFUL_) { - ptdlsinfo->link_established = _TRUE; + rtw_tdls_set_link_established(padapter, _TRUE); if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) { ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE; @@ -1996,7 +2204,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) if (prx_pkt_attrib->encrypt) rtw_tdls_set_key(padapter, ptdls_sta); - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ESTABLISHED); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED); } } @@ -2009,10 +2217,9 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) } -int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) +int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - struct sta_info *ptdls_sta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; u8 *ptr = precv_frame->u.hdr.rx_data; _irqL irqL; @@ -2027,13 +2234,6 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) int ret = _SUCCESS; psa = get_sa(ptr); - ptdls_sta = rtw_get_stainfo(pstapriv, psa); - - if (ptdls_sta == NULL) { - RTW_INFO("[%s] Direct Link Peer = "MAC_FMT" not found\n", __FUNCTION__, MAC_ARG(psa)); - ret = _FAIL; - goto exit; - } ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN; parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len @@ -2042,14 +2242,14 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) - prx_pkt_attrib->icv_len - LLC_HEADER_SIZE - ETH_TYPE_LEN - - PAYLOAD_TYPE_LEN - - FIXED_IE; + - PAYLOAD_TYPE_LEN; _rtw_memcpy(&status_code, ptr + 2, 2); if (status_code != 0) { RTW_INFO("[%s] status_code = %d\n, free_tdls_sta", __FUNCTION__, status_code); - free_tdls_sta(padapter, ptdls_sta); + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); ret = _FAIL; goto exit; } @@ -2081,9 +2281,10 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) #endif #ifdef CONFIG_80211AC_VHT case EID_VHTOperation: + rtw_tdls_process_vht_operation(padapter, ptdls_sta, pIE->data, pIE->Length); break; case EID_OpModeNotification: - rtw_process_vht_op_mode_notify(padapter, pIE->data, ptdls_sta); + rtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length); break; #endif case _LINK_ID_IE_: @@ -2101,14 +2302,15 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) /* Verify mic in FTIE MIC field */ if (rtw_tdls_is_driver_setup(padapter) && (tdls_verify_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL)) { - free_tdls_sta(padapter, ptdls_sta); + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); ret = _FAIL; goto exit; } } if (rtw_tdls_is_driver_setup(padapter)) { - ptdlsinfo->link_established = _TRUE; + rtw_tdls_set_link_established(padapter, _TRUE); if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) { ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE; @@ -2124,7 +2326,7 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) _set_timer(&ptdls_sta->TPK_timer, ONE_SEC); } - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ESTABLISHED); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED); } exit: @@ -2159,8 +2361,7 @@ int On_TDLS_Dis_Req(_adapter *padapter, union recv_frame *precv_frame) - prx_pkt_attrib->icv_len - LLC_HEADER_SIZE - ETH_TYPE_LEN - - PAYLOAD_TYPE_LEN - - FIXED_IE; + - PAYLOAD_TYPE_LEN; /* Parsing information element */ for (j = FIXED_IE; j < parsing_length;) { @@ -2191,27 +2392,22 @@ int On_TDLS_Dis_Req(_adapter *padapter, union recv_frame *precv_frame) } -int On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame) +int On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { - u8 *psa; u8 *ptr = precv_frame->u.hdr.rx_data; struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *ptdls_sta = NULL; _irqL irqL; u8 reason; reason = *(ptr + prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN + 2); RTW_INFO("[TDLS] %s Reason code(%d)\n", __FUNCTION__, reason); - psa = get_sa(ptr); - - ptdls_sta = rtw_get_stainfo(pstapriv, psa); - if (ptdls_sta != NULL) { - if (rtw_tdls_is_driver_setup(padapter)) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_TEARDOWN_STA_LOCALLY); + if (rtw_tdls_is_driver_setup(padapter)) { + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); } return _SUCCESS; @@ -2232,36 +2428,29 @@ u8 TDLS_check_ch_state(uint state) } #endif -int On_TDLS_Peer_Traffic_Indication(_adapter *padapter, union recv_frame *precv_frame) +int On_TDLS_Peer_Traffic_Indication(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct sta_info *ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->src); u8 *ptr = precv_frame->u.hdr.rx_data; struct tdls_txmgmt txmgmt; ptr += pattrib->hdrlen + pattrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN; _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - if (ptdls_sta != NULL) { txmgmt.dialog_token = *(ptr + 2); issue_tdls_peer_traffic_rsp(padapter, ptdls_sta, &txmgmt); - /* issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 0, 0, 0); */ - } else { - RTW_INFO("from unknown sta:"MAC_FMT"\n", MAC_ARG(pattrib->src)); - return _FAIL; - } + /* issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0); */ return _SUCCESS; } /* We process buffered data for 1. U-APSD, 2. ch. switch, 3. U-APSD + ch. switch here */ -int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame) +int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src); u8 wmmps_ac = 0; /* u8 state=TDLS_check_ch_state(ptdls_sta->tdls_sta_state); */ int i; @@ -2323,20 +2512,17 @@ int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame) } #ifdef CONFIG_TDLS_CH_SW -sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame) +sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; - struct sta_info *ptdls_sta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; u8 *ptr = precv_frame->u.hdr.rx_data; struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; - u8 *psa; sint parsing_length; PNDIS_802_11_VARIABLE_IEs pIE; u8 FIXED_IE = 4; u16 j; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct tdls_txmgmt txmgmt; u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; u16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000; u8 take_care_iqk; @@ -2346,15 +2532,6 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame) return _FAIL; } - _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - psa = get_sa(ptr); - ptdls_sta = rtw_get_stainfo(pstapriv, psa); - - if (ptdls_sta == NULL) { - RTW_INFO("[%s] Direct Link Peer = "MAC_FMT" not found\n", __func__, MAC_ARG(psa)); - return _FAIL; - } - ptdls_sta->ch_switch_time = switch_time; ptdls_sta->ch_switch_timeout = switch_timeout; @@ -2365,8 +2542,7 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame) - prx_pkt_attrib->icv_len - LLC_HEADER_SIZE - ETH_TYPE_LEN - - PAYLOAD_TYPE_LEN - - FIXED_IE; + - PAYLOAD_TYPE_LEN; pchsw_info->off_ch_num = *(ptr + 2); @@ -2421,7 +2597,7 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame) central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset); if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) < 0) { if (!(pchsw_info->ch_sw_state & TDLS_CH_SWITCH_PREPARE_STATE)) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_PREPARE); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE); return _FAIL; } @@ -2431,29 +2607,23 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame) if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) _cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer); - /* Todo: check status */ - txmgmt.status_code = 0; - _rtw_memcpy(txmgmt.peer, psa, ETH_ALEN); - if (_rtw_memcmp(pchsw_info->addr, zaddr, ETH_ALEN) == _TRUE) - _rtw_memcpy(pchsw_info->addr, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(pchsw_info->addr, ptdls_sta->cmn.mac_addr, ETH_ALEN); if (ATOMIC_READ(&pchsw_info->chsw_on) == _FALSE) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START); - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_RESP); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_RESP); return _SUCCESS; } -sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame) +sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; - struct sta_info *ptdls_sta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; u8 *ptr = precv_frame->u.hdr.rx_data; struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; - u8 *psa; sint parsing_length; PNDIS_802_11_VARIABLE_IEs pIE; u8 FIXED_IE = 4; @@ -2466,20 +2636,12 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } - psa = get_sa(ptr); - ptdls_sta = rtw_get_stainfo(pstapriv, psa); - - if (ptdls_sta == NULL) { - RTW_INFO("[%s] Direct Link Peer = "MAC_FMT" not found\n", __func__, MAC_ARG(psa)); - return _FAIL; - } - /* If we receive Unsolicited TDLS Channel Switch Response when channel switch is running, */ /* we will go back to base channel and terminate this channel switch procedure */ if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) { if (pmlmeext->cur_channel != rtw_get_oper_ch(padapter)) { RTW_INFO("[TDLS] Rx unsolicited channel switch response\n"); - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL); goto exit; } } @@ -2491,15 +2653,14 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame) - prx_pkt_attrib->icv_len - LLC_HEADER_SIZE - ETH_TYPE_LEN - - PAYLOAD_TYPE_LEN - - FIXED_IE; + - PAYLOAD_TYPE_LEN; _rtw_memcpy(&status_code, ptr + 2, 2); if (status_code != 0) { RTW_INFO("[TDLS] %s status_code:%d\n", __func__, status_code); pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE); - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END); ret = _FAIL; goto exit; } @@ -2530,7 +2691,7 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame) if ((pmlmeext->cur_channel == rtw_get_oper_ch(padapter)) && (pchsw_info->ch_sw_state & TDLS_WAIT_CH_RSP_STATE)) { if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_OFF_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL); } exit: @@ -2545,6 +2706,7 @@ void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen) struct wifi_display_info *pwfd_info = padapter->tdlsinfo.wfd_info; u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; u32 wfdielen = 0; + u16 v16 = 0; if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) return; @@ -2576,8 +2738,9 @@ void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen) /* Value1: */ /* WFD device information */ /* available for WFD session + Preferred TDLS + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL - | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL + | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, v16); wfdielen += 2; /* Value2: */ @@ -2629,14 +2792,12 @@ void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen) } #endif /* CONFIG_WFD */ -void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_info *ptdls_sta = rtw_get_stainfo((&padapter->stapriv) , pattrib->dst); - int i = 0 ; u32 time; u8 *pframe_head; @@ -2684,7 +2845,7 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib); - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE)) pframe = rtw_tdls_set_qos_cap(pframe, pattrib); @@ -2707,24 +2868,18 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr } -void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_info *ptdls_sta; u8 k; /* for random ANonce */ u8 *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL; u32 time; u8 *pframe_head; - ptdls_sta = rtw_get_stainfo(&(padapter->stapriv) , pattrib->dst); - - if (ptdls_sta == NULL) - RTW_INFO("[%s] %d ptdls_sta is NULL\n", __FUNCTION__, __LINE__); - - if (pattrib->encrypt && ptdls_sta != NULL) { + if (pattrib->encrypt) { for (k = 0; k < 8; k++) { time = rtw_get_current_time(); _rtw_memcpy(&ptdls_sta->ANonce[4 * k], (u8 *)&time, 4); @@ -2781,7 +2936,7 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib); plinkid_ie = pframe; - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); /* Fill FTIE mic */ if (pattrib->encrypt && rtw_tdls_is_driver_setup(padapter) == _TRUE) @@ -2809,14 +2964,13 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr } -void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_info *ptdls_sta = rtw_get_stainfo((&padapter->stapriv) , pattrib->dst); unsigned int ie_len; unsigned char *p; @@ -2859,7 +3013,7 @@ void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitfr /* HT operation; todo */ plinkid_ie = pframe; - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE)) wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic); @@ -2880,10 +3034,9 @@ void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitfr #endif } -void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_info *ptdls_sta = rtw_get_stainfo(&(padapter->stapriv) , pattrib->dst); u8 *pftie = NULL, *pftie_mic = NULL, *plinkid_ie = NULL; pframe = rtw_tdls_set_payload_type(pframe, pattrib); @@ -2903,9 +3056,9 @@ void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitfra plinkid_ie = pframe; if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE)) wpa_tdls_teardown_ftie_mic(ptdls_sta->tpk.kck, plinkid_ie, ptxmgmt->status_code, 1, 4, pftie, pftie_mic); @@ -2919,7 +3072,7 @@ void rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitfram pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt); pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); } @@ -2958,17 +3111,16 @@ void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfram #endif pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib); - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); } -void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct pkt_attrib *pattrib = &pxmitframe->attrib; u8 AC_queue = 0; - struct sta_info *ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst); pframe = rtw_tdls_set_payload_type(pframe, pattrib); pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); @@ -2976,9 +3128,9 @@ void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_ pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); /* PTI control */ /* PU buffer status */ @@ -2994,11 +3146,10 @@ void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_ } -void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_info *ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst); pframe = rtw_tdls_set_payload_type(pframe, pattrib); pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); @@ -3006,18 +3157,17 @@ void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame * pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); } #ifdef CONFIG_TDLS_CH_SW -void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; struct pkt_attrib *pattrib = &pxmitframe->attrib; struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); u16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000; ptdls_sta->ch_switch_time = switch_time; @@ -3041,20 +3191,19 @@ void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxm } if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta); } -void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct pkt_attrib *pattrib = &pxmitframe->attrib; struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); pframe = rtw_tdls_set_payload_type(pframe, pattrib); pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); @@ -3062,9 +3211,9 @@ void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxm pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt); if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta); } @@ -3143,9 +3292,10 @@ void _tdls_tpk_timer_hdl(void *FunctionContext) /* TPK_timer expired in a second */ /* Retry timer should set at least 301 sec. */ if (ptdls_sta->TPK_count >= (ptdls_sta->TDLS_PeerKey_Lifetime - 3)) { - RTW_INFO("[TDLS] %s, Re-Setup TDLS link with "MAC_FMT" since TPK lifetime expires!\n", __FUNCTION__, MAC_ARG(ptdls_sta->hwaddr)); + RTW_INFO("[TDLS] %s, Re-Setup TDLS link with "MAC_FMT" since TPK lifetime expires!\n", + __FUNCTION__, MAC_ARG(ptdls_sta->cmn.mac_addr)); ptdls_sta->TPK_count = 0; - _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); issue_tdls_setup_req(ptdls_sta->padapter, &txmgmt, _FALSE); } @@ -3159,7 +3309,7 @@ void _tdls_ch_switch_timer_hdl(void *FunctionContext) _adapter *padapter = ptdls_sta->padapter; struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL); RTW_INFO("[TDLS] %s, can't get traffic from op_ch:%d\n", __func__, rtw_get_oper_ch(padapter)); } @@ -3191,7 +3341,7 @@ void _tdls_ch_switch_monitor_timer_hdl(void *FunctionContext) _adapter *padapter = ptdls_sta->padapter; struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END); RTW_INFO("[TDLS] %s, does not receive ch sw req\n", __func__); } @@ -3200,37 +3350,41 @@ void _tdls_ch_switch_monitor_timer_hdl(void *FunctionContext) void _tdls_handshake_timer_hdl(void *FunctionContext) { struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; - _adapter *padapter = ptdls_sta->padapter; + _adapter *padapter = NULL; struct tdls_txmgmt txmgmt; _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; if (ptdls_sta != NULL) { + padapter = ptdls_sta->padapter; + RTW_INFO("[TDLS] Handshake time out\n"); if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_TEARDOWN_STA); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA); else - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_TEARDOWN_STA_LOCALLY); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY); } } void _tdls_pti_timer_hdl(void *FunctionContext) { struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; - _adapter *padapter = ptdls_sta->padapter; + _adapter *padapter = NULL; struct tdls_txmgmt txmgmt; _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_; if (ptdls_sta != NULL) { + padapter = ptdls_sta->padapter; + if (ptdls_sta->tdls_sta_state & TDLS_WAIT_PTR_STATE) { RTW_INFO("[TDLS] Doesn't receive PTR from peer dev:"MAC_FMT"; " - "Send TDLS Tear Down\n", MAC_ARG(ptdls_sta->hwaddr)); - issue_tdls_teardown(padapter, &txmgmt, _FALSE); + "Send TDLS Tear Down\n", MAC_ARG(ptdls_sta->cmn.mac_addr)); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA); } } } @@ -3249,7 +3403,7 @@ void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta) rtw_init_timer(&psta->pti_timer, padapter, _tdls_pti_timer_hdl, psta); } -void rtw_free_tdls_timer(struct sta_info *psta) +void rtw_cancel_tdls_timer(struct sta_info *psta) { _cancel_timer_ex(&psta->TPK_timer); #ifdef CONFIG_TDLS_CH_SW @@ -3262,35 +3416,53 @@ void rtw_free_tdls_timer(struct sta_info *psta) _cancel_timer_ex(&psta->pti_timer); } -u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta) +void rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta) { - unsigned char sta_band = 0; - unsigned int tx_ra_bitmap = 0; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct sta_priv *pstapriv = &padapter->stapriv; + _irqL irqL; - rtw_hal_update_sta_rate_mask(padapter, psta); - tx_ra_bitmap = psta->ra_mask; + rtw_cancel_tdls_timer(psta); - if (pcur_network->Configuration.DSConfig > 14) { - if (tx_ra_bitmap & 0xffff000) - sta_band |= WIRELESS_11_5N | WIRELESS_11A; - else - sta_band |= WIRELESS_11A; - } else { - if (tx_ra_bitmap & 0xffff000) - sta_band |= WIRELESS_11_24N | WIRELESS_11G | WIRELESS_11B; - else if (tx_ra_bitmap & 0xff0) - sta_band |= WIRELESS_11G | WIRELESS_11B; - else - sta_band |= WIRELESS_11B; + _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + if (ptdlsinfo->sta_cnt != 0) + ptdlsinfo->sta_cnt--; + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + + if (ptdlsinfo->sta_cnt < MAX_ALLOWED_TDLS_STA_NUM) { + ptdlsinfo->sta_maximum = _FALSE; + _rtw_memset(&ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record)); } - psta->wireless_mode = sta_band; + if (ptdlsinfo->sta_cnt == 0) + rtw_tdls_set_link_established(padapter, _FALSE); + else + RTW_INFO("Remain tdls sta:%02x\n", ptdlsinfo->sta_cnt); +} + +void rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd) +{ + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + + /* Clear cam */ + rtw_clearstakey_cmd(padapter, psta, enqueue_cmd); + + /* Update sta media status */ + if (enqueue_cmd) + rtw_sta_media_status_rpt_cmd(padapter, psta, 0); + else + rtw_sta_media_status_rpt(padapter, psta, 0); + + /* Set RCR if necessary */ + if (ptdlsinfo->sta_cnt == 0) { + if (enqueue_cmd) + rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR); + else + rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK); + } - psta->raid = rtw_hal_networktype_to_raid(padapter, psta); - tx_ra_bitmap |= ((psta->raid << 28) & 0xf0000000); - return tx_ra_bitmap; + /* Free tdls sta info */ + rtw_free_stainfo(padapter, psta); } int rtw_tdls_is_driver_setup(_adapter *padapter) diff --git a/core/rtw_vht.c b/core/rtw_vht.c index bff68c1..dd2e7e5 100644 --- a/core/rtw_vht.c +++ b/core/rtw_vht.c @@ -18,6 +18,101 @@ #include #ifdef CONFIG_80211AC_VHT +const u16 _vht_max_mpdu_len[] = { + 3895, + 7991, + 11454, + 0, +}; + +const u8 _vht_sup_ch_width_set_to_bw_cap[] = { + BW_CAP_80M, + BW_CAP_80M | BW_CAP_160M, + BW_CAP_80M | BW_CAP_160M | BW_CAP_80_80M, + 0, +}; + +const char *const _vht_sup_ch_width_set_str[] = { + "80MHz", + "160MHz", + "160MHz & 80+80MHz", + "BW-RSVD", +}; + +void dump_vht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len) +{ + if (buf_len != VHT_CAP_IE_LEN) { + RTW_PRINT_SEL(sel, "Invalid VHT capability IE len:%d != %d\n", buf_len, VHT_CAP_IE_LEN); + return; + } + + RTW_PRINT_SEL(sel, "cap_info:%02x %02x %02x %02x: MAX_MPDU_LEN:%u %s%s%s%s%s RX-STBC:%u MAX_AMPDU_LEN:%u\n" + , *(buf), *(buf + 1), *(buf + 2), *(buf + 3) + , vht_max_mpdu_len(GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(buf)) + , vht_sup_ch_width_set_str(GET_VHT_CAPABILITY_ELE_CHL_WIDTH(buf)) + , GET_VHT_CAPABILITY_ELE_RX_LDPC(buf) ? " RX-LDPC" : "" + , GET_VHT_CAPABILITY_ELE_SHORT_GI80M(buf) ? " SGI-80" : "" + , GET_VHT_CAPABILITY_ELE_SHORT_GI160M(buf) ? " SGI-160" : "" + , GET_VHT_CAPABILITY_ELE_TX_STBC(buf) ? " TX-STBC" : "" + , GET_VHT_CAPABILITY_ELE_RX_STBC(buf) + , VHT_MAX_AMPDU_LEN(GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(buf)) + ); +} + +void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len) +{ + const u8 *pos = ie; + u16 id; + u16 len; + + const u8 *vht_cap_ie; + sint vht_cap_ielen; + + vht_cap_ie = rtw_get_ie(ie, WLAN_EID_VHT_CAPABILITY, &vht_cap_ielen, ie_len); + if (!ie || vht_cap_ie != ie) + return; + + dump_vht_cap_ie_content(sel, vht_cap_ie + 2, vht_cap_ielen); +} + +const char *const _vht_op_ch_width_str[] = { + "20 or 40MHz", + "80MHz", + "160MHz", + "80+80MHz", + "BW-RSVD", +}; + +void dump_vht_op_ie_content(void *sel, const u8 *buf, u32 buf_len) +{ + if (buf_len != VHT_OP_IE_LEN) { + RTW_PRINT_SEL(sel, "Invalid VHT operation IE len:%d != %d\n", buf_len, VHT_OP_IE_LEN); + return; + } + + RTW_PRINT_SEL(sel, "%s, ch0:%u, ch1:%u\n" + , vht_op_ch_width_str(GET_VHT_OPERATION_ELE_CHL_WIDTH(buf)) + , GET_VHT_OPERATION_ELE_CENTER_FREQ1(buf) + , GET_VHT_OPERATION_ELE_CENTER_FREQ2(buf) + ); +} + +void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len) +{ + const u8 *pos = ie; + u16 id; + u16 len; + + const u8 *vht_op_ie; + sint vht_op_ielen; + + vht_op_ie = rtw_get_ie(ie, WLAN_EID_VHT_OPERATION, &vht_op_ielen, ie_len); + if (!ie || vht_op_ie != ie) + return; + + dump_vht_op_ie_content(sel, vht_op_ie + 2, vht_op_ielen); +} + /* 20/40/80, ShortGI, MCS Rate */ const u16 VHT_MCS_DATA_RATE[3][2][30] = { { { @@ -178,43 +273,53 @@ void rtw_vht_use_default_setting(_adapter *padapter) /* Beamforming setting */ CLEAR_FLAGS(pvhtpriv->beamform_cap); #ifdef CONFIG_BEAMFORMING - rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer); - rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee); - mu_bfer = _FALSE; - mu_bfee = _FALSE; - rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMER, &mu_bfer); - rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMEE, &mu_bfee); - if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) { +#ifdef RTW_BEAMFORMING_VERSION_2 + /* only enable beamforming in STA client mode */ + if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter) + && !MLME_IS_ADHOC(padapter) + && !MLME_IS_MESH(padapter)) +#endif + { + rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, + (u8 *)&bHwSupportBeamformer); + rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, + (u8 *)&bHwSupportBeamformee); + mu_bfer = _FALSE; + mu_bfee = _FALSE; + rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMER, &mu_bfer); + rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMEE, &mu_bfee); + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) { #ifdef CONFIG_CONCURRENT_MODE - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n"); + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2)) + && (_TRUE == mu_bfer)) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE); + RTW_INFO("[VHT] Support MU-MIMO AP\n"); + } + } else + RTW_INFO("[VHT] CONCURRENT not AP ;not allow Support Beamformer\n"); +#else SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); - RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n"); + RTW_INFO("[VHT] Support Beamformer\n"); if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2)) - && (_TRUE == mu_bfer)) { + && (_TRUE == mu_bfer) + && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE); RTW_INFO("[VHT] Support MU-MIMO AP\n"); } - } else - RTW_INFO("[VHT] CONCURRENT not AP ;not allow Support Beamformer\n"); -#else - SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); - RTW_INFO("[VHT] Support Beamformer\n"); - if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2)) - && (_TRUE == mu_bfer) - && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { - SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE); - RTW_INFO("[VHT] Support MU-MIMO AP\n"); - } #endif - } - if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) { - SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); - RTW_INFO("[VHT] Support Beamformee\n"); - if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3)) - && (_TRUE == mu_bfee) - && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) { - SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE); - RTW_INFO("[VHT] Support MU-MIMO STA\n"); + } + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); + RTW_INFO("[VHT] Support Beamformee\n"); + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3)) + && (_TRUE == mu_bfee) + && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE); + RTW_INFO("[VHT] Support MU-MIMO STA\n"); + } } } #endif /* CONFIG_BEAMFORMING */ @@ -261,6 +366,38 @@ u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss) return bitmap; } +#ifdef CONFIG_BEAMFORMING +void update_sta_vht_info_apmode_bf_cap(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv; + struct vht_priv *pvhtpriv_sta = &psta->vhtpriv; + u16 cur_beamform_cap = 0; + + /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */ + if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) && + GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); + /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/ + SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap) << 8); + } + + /* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */ + if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) && + GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/ + SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap) << 12); + } + + if (cur_beamform_cap) + RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->cmn.aid, cur_beamform_cap); + + pvhtpriv_sta->beamform_cap = cur_beamform_cap; + psta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap; +} +#endif + void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta) { struct sta_info *psta = (struct sta_info *)sta; @@ -268,35 +405,52 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta) struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv; struct vht_priv *pvhtpriv_sta = &psta->vhtpriv; - struct ht_priv *phtpriv_sta = &psta->htpriv; - u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, bw_mode = 0; - u16 cur_beamform_cap = 0; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0; + s8 bw_mode = -1; u8 *pcap_mcs; if (pvhtpriv_sta->vht_option == _FALSE) return; - bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify); + if (pvhtpriv_sta->op_present) { + switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(pvhtpriv_sta->vht_op)) { + case 1: /* 80MHz */ + case 2: /* 160MHz */ + case 3: /* 80+80 */ + bw_mode = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */ + break; + } + } + + if (pvhtpriv_sta->notify_present) + bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify); + else if (MLME_IS_AP(padapter)) { + /* for VHT client without Operating Mode Notify IE; minimal 80MHz */ + if (bw_mode < CHANNEL_WIDTH_80) + bw_mode = CHANNEL_WIDTH_80; + } + + if (bw_mode != -1) + psta->cmn.bw_mode = bw_mode; /* update bw_mode only if get value from VHT IEs */ - /* if (bw_mode > psta->bw_mode) */ - psta->bw_mode = bw_mode; + psta->cmn.ra_info.is_vht_enable = _TRUE; /* B4 Rx LDPC */ if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) && GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) { SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX)); - RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->aid, cur_ldpc_cap); + RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->cmn.aid, cur_ldpc_cap); } pvhtpriv_sta->ldpc_cap = cur_ldpc_cap; - if (psta->bw_mode > pmlmeext->cur_bwmode) - psta->bw_mode = pmlmeext->cur_bwmode; + if (psta->cmn.bw_mode > pmlmeext->cur_bwmode) + psta->cmn.bw_mode = pmlmeext->cur_bwmode; - if (psta->bw_mode == CHANNEL_WIDTH_80) { + if (psta->cmn.bw_mode == CHANNEL_WIDTH_80) { /* B5 Short GI for 80 MHz */ pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE; /* RTW_INFO("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m); */ - } else if (psta->bw_mode >= CHANNEL_WIDTH_160) { + } else if (psta->cmn.bw_mode >= CHANNEL_WIDTH_160) { /* B5 Short GI for 80 MHz */ pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE; /* RTW_INFO("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m); */ @@ -306,29 +460,12 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta) if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) && GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) { SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX)); - RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->aid, cur_stbc_cap); + RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->cmn.aid, cur_stbc_cap); } pvhtpriv_sta->stbc_cap = cur_stbc_cap; #ifdef CONFIG_BEAMFORMING - /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */ - if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) && - GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); - /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/ - SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap) << 8); - } - - /* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */ - if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) && - GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); - /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/ - SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap) << 12); - } - pvhtpriv_sta->beamform_cap = cur_beamform_cap; - if (cur_beamform_cap) - RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->aid, cur_beamform_cap); + update_sta_vht_info_apmode_bf_cap(padapter, psta); #endif /* B23 B24 B25 Maximum A-MPDU Length Exponent */ @@ -496,12 +633,12 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta) target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe); target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe) + 1); - if (target_bw != psta->bw_mode) { + if (target_bw != psta->cmn.bw_mode) { if (hal_is_bw_support(padapter, target_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw) ) { update_ra = _TRUE; - psta->bw_mode = target_bw; + psta->cmn.bw_mode = target_bw; } } @@ -514,7 +651,7 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta) rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map); _rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2); - rtw_hal_update_sta_rate_mask(padapter, psta); + rtw_hal_update_sta_ra_info(padapter, psta); } if (update_ra) @@ -651,7 +788,7 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss); RTW_INFO("[VHT] Declare supporting RX STBC = %d\n", rx_stbc_nss); } - + #ifdef CONFIG_BEAMFORMING /* B11 SU Beamformer Capable */ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1); @@ -686,6 +823,7 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) RTW_INFO("[VHT] Declare supporting MU Bfee\n"); } } + #endif/*CONFIG_BEAMFORMING*/ /* B21 VHT TXOP PS */ SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0); @@ -721,61 +859,101 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len) { - u32 ielen = 0, out_len = 0; - u8 cap_len = 0, notify_len = 0, notify_bw = 0, operation_bw = 0, supported_chnl_width = 0; - u8 *p, *pframe; + u32 ielen; + u8 max_bw; + u8 oper_ch, oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + u8 *out_vht_op_ie, *ht_op_ie, *vht_cap_ie, *vht_op_ie; struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; rtw_vht_use_default_setting(padapter); - p = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12); - if (p && ielen > 0) { - supported_chnl_width = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2); + ht_op_ie = rtw_get_ie(in_ie + 12, WLAN_EID_HT_OPERATION, &ielen, in_len - 12); + if (!ht_op_ie || ielen != HT_OP_IE_LEN) + goto exit; + vht_cap_ie = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12); + if (!vht_cap_ie || ielen != VHT_CAP_IE_LEN) + goto exit; + vht_op_ie = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12); + if (!vht_op_ie || ielen != VHT_OP_IE_LEN) + goto exit; - /* VHT Capabilities element */ - cap_len = rtw_build_vht_cap_ie(padapter, out_ie + *pout_len); - *pout_len += cap_len; + /* VHT Capabilities element */ + *pout_len += rtw_build_vht_cap_ie(padapter, out_ie + *pout_len); - /* Get HT BW */ - p = rtw_get_ie(in_ie + 12, _HT_EXTRA_INFO_IE_, &ielen, in_len - 12); - if (p && ielen > 0) { - struct HT_info_element *pht_info = (struct HT_info_element *)(p + 2); - if (pht_info->infos[0] & BIT(2)) - operation_bw = CHANNEL_WIDTH_40; - else - operation_bw = CHANNEL_WIDTH_20; - } - /* VHT Operation element */ - p = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12); - if (p && ielen > 0) { - out_len = *pout_len; - if (GET_VHT_OPERATION_ELE_CHL_WIDTH(p + 2) >= 1) { - if (supported_chnl_width == 2) - operation_bw = CHANNEL_WIDTH_80_80; - else if (supported_chnl_width == 1) - operation_bw = CHANNEL_WIDTH_160; - else - operation_bw = CHANNEL_WIDTH_80; + /* VHT Operation element */ + out_vht_op_ie = out_ie + *pout_len; + rtw_set_ie(out_vht_op_ie, EID_VHTOperation, VHT_OP_IE_LEN, vht_op_ie + 2 , pout_len); + + /* get primary channel from HT_OP_IE */ + oper_ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2); + + /* find the largest bw supported by both registry and hal */ + max_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv)); + + if (max_bw >= CHANNEL_WIDTH_40) { + /* get bw offset form HT_OP_IE */ + if (GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2)) { + switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) { + case SCA: + oper_bw = CHANNEL_WIDTH_40; + oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + case SCB: + oper_bw = CHANNEL_WIDTH_40; + oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; } - pframe = rtw_set_ie(out_ie + out_len, EID_VHTOperation, ielen, p + 2 , pout_len); } - /* find the largest bw supported by both registry and hal */ - notify_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv)); + if (oper_bw == CHANNEL_WIDTH_40) { + switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2)) { + case 1: /* 80MHz */ + case 2: /* 160MHz */ + case 3: /* 80+80 */ + oper_bw = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */ + break; + } + + oper_bw = rtw_min(oper_bw, max_bw); + + /* try downgrage bw to fit in channel plan setting */ + while (!rtw_chset_is_chbw_valid(adapter_to_chset(padapter), oper_ch, oper_bw, oper_offset)) { + oper_bw--; + if (oper_bw == CHANNEL_WIDTH_20) { + oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + } + } + } - if (notify_bw > operation_bw) - notify_bw = operation_bw; + rtw_warn_on(!rtw_chset_is_chbw_valid(adapter_to_chset(padapter), oper_ch, oper_bw, oper_offset)); - /* Operating Mode Notification element */ - notify_len = rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, notify_bw); - *pout_len += notify_len; + /* update VHT_OP_IE */ + if (oper_bw < CHANNEL_WIDTH_80) { + SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0); + } else if (oper_bw == CHANNEL_WIDTH_80) { + u8 cch = rtw_get_center_ch(oper_ch, oper_bw, oper_offset); - pvhtpriv->vht_option = _TRUE; + SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 1); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, cch); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0); + } else { + RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(padapter), oper_bw); + rtw_warn_on(1); } + /* Operating Mode Notification element */ + *pout_len += rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, oper_bw); + + pvhtpriv->vht_option = _TRUE; + +exit: return pvhtpriv->vht_option; } @@ -804,4 +982,72 @@ void VHTOnAssocRsp(_adapter *padapter) rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate)); } +void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 cap_len, operation_len; + uint len = 0; + sint ie_len = 0; + u8 *p = NULL; + + p = rtw_get_ie(pnetwork->IEs + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, + (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) + return; + + rtw_vht_use_default_setting(padapter); + + /* VHT Operation mode notifiy bit in Extended IE (127) */ + SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1); + pmlmepriv->ext_capab_ie_len = 10; + rtw_set_ie(pnetwork->IEs + pnetwork->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len); + pnetwork->IELength += pmlmepriv->ext_capab_ie_len; + + /* VHT Capabilities element */ + cap_len = rtw_build_vht_cap_ie(padapter, pnetwork->IEs + pnetwork->IELength); + pnetwork->IELength += cap_len; + + /* VHT Operation element */ + operation_len = rtw_build_vht_operation_ie(padapter, pnetwork->IEs + pnetwork->IELength, + pnetwork->Configuration.DSConfig); + pnetwork->IELength += operation_len; + + rtw_check_for_vht20(padapter, pnetwork->IEs + _BEACON_IE_OFFSET_, pnetwork->IELength - _BEACON_IE_OFFSET_); + + pmlmepriv->vhtpriv.vht_option = _TRUE; +} + +void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + rtw_remove_bcn_ie(padapter, pnetwork, EID_EXTCapability); + rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTCapability); + rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTOperation); + + pmlmepriv->vhtpriv.vht_option = _FALSE; +} + +void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len) +{ + u8 ht_ch, ht_bw, ht_offset; + u8 vht_ch, vht_bw, vht_offset; + + rtw_ies_get_chbw(ies, ies_len, &ht_ch, &ht_bw, &ht_offset, 1, 0); + rtw_ies_get_chbw(ies, ies_len, &vht_ch, &vht_bw, &vht_offset, 1, 1); + + if (ht_bw == CHANNEL_WIDTH_20 && vht_bw >= CHANNEL_WIDTH_80) { + u8 *vht_op_ie; + int vht_op_ielen; + + RTW_INFO(FUNC_ADPT_FMT" vht80 is not allowed without ht40\n", FUNC_ADPT_ARG(adapter)); + vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len); + if (vht_op_ie && vht_op_ielen) { + RTW_INFO(FUNC_ADPT_FMT" switch to vht20\n", FUNC_ADPT_ARG(adapter)); + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0); + } + } +} #endif /* CONFIG_80211AC_VHT */ diff --git a/core/rtw_wapi.c b/core/rtw_wapi.c index 3143b62..e065b3d 100644 --- a/core/rtw_wapi.c +++ b/core/rtw_wapi.c @@ -452,7 +452,8 @@ add to support WAPI to N-mode *****************************************************************************/ u8 rtw_wapi_check_for_drop( _adapter *padapter, - union recv_frame *precv_frame + union recv_frame *precv_frame, + u8 *ehdr_ops ) { PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); @@ -463,7 +464,7 @@ u8 rtw_wapi_check_for_drop( struct recv_frame_hdr *precv_hdr = &precv_frame->u.hdr; u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - u8 *ptr = precv_frame->u.hdr.rx_data; + u8 *ptr = ehdr_ops; int i; WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__); @@ -1251,4 +1252,61 @@ bool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA) return bDrop; } +void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param) +{ + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; + PRT_WAPI_STA_INFO pWapiSta; + u8 WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; + u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; + u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; + + if (param->u.crypt.set_tx == 1) { + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if (_rtw_memcmp(pWapiSta->PeerMacAddr, param->sta_addr, 6)) { + _rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16); + + pWapiSta->wapiUsk.bSet = true; + _rtw_memcpy(pWapiSta->wapiUsk.dataKey, param->u.crypt.key, 16); + _rtw_memcpy(pWapiSta->wapiUsk.micKey, param->u.crypt.key + 16, 16); + pWapiSta->wapiUsk.keyId = param->u.crypt.idx ; + pWapiSta->wapiUsk.bTxEnable = true; + + _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16); + pWapiSta->wapiUskUpdate.bTxEnable = false; + pWapiSta->wapiUskUpdate.bSet = false; + + if (psecuritypriv->sw_encrypt == false || psecuritypriv->sw_decrypt == false) { + /* set unicast key for ASUE */ + rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false); + } + } + } + } else { + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if (_rtw_memcmp(pWapiSta->PeerMacAddr, get_bssid(pmlmepriv), 6)) { + pWapiSta->wapiMsk.bSet = true; + _rtw_memcpy(pWapiSta->wapiMsk.dataKey, param->u.crypt.key, 16); + _rtw_memcpy(pWapiSta->wapiMsk.micKey, param->u.crypt.key + 16, 16); + pWapiSta->wapiMsk.keyId = param->u.crypt.idx ; + pWapiSta->wapiMsk.bTxEnable = false; + if (!pWapiSta->bSetkeyOk) + pWapiSta->bSetkeyOk = true; + pWapiSta->bAuthenticateInProgress = false; + + _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); + + if (psecuritypriv->sw_decrypt == false) { + /* set rx broadcast key for ASUE */ + rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false); + } + } + } + } +} #endif diff --git a/core/rtw_wlan_util.c b/core/rtw_wlan_util.c index 206bff6..45c273b 100644 --- a/core/rtw_wlan_util.c +++ b/core/rtw_wlan_util.c @@ -72,6 +72,39 @@ static u8 rtw_basic_rate_mix[7] = { IEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK }; +/* test if rate is defined in rtw_basic_rate_cck */ +bool rtw_is_basic_rate_cck(u8 rate) +{ + int i; + + for (i = 0; i < 4; i++) + if ((rtw_basic_rate_cck[i] & 0x7F) == (rate & 0x7F)) + return 1; + return 0; +} + +/* test if rate is defined in rtw_basic_rate_ofdm */ +bool rtw_is_basic_rate_ofdm(u8 rate) +{ + int i; + + for (i = 0; i < 3; i++) + if ((rtw_basic_rate_ofdm[i] & 0x7F) == (rate & 0x7F)) + return 1; + return 0; +} + +/* test if rate is defined in rtw_basic_rate_mix */ +bool rtw_is_basic_rate_mix(u8 rate) +{ + int i; + + for (i = 0; i < 7; i++) + if ((rtw_basic_rate_mix[i] & 0x7F) == (rate & 0x7F)) + return 1; + return 0; +} + int new_bcn_max = 3; int cckrates_included(unsigned char *rate, int ratelen) @@ -101,8 +134,7 @@ int cckratesonly_included(unsigned char *rate, int ratelen) return _TRUE; } -#ifdef CONFIG_GET_RAID_BY_DRV -s8 rtw_get_tx_nss(_adapter *adapter, struct sta_info *psta) +s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta) { struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); u8 rf_type = RF_1T1R, custom_rf_type; @@ -116,154 +148,50 @@ s8 rtw_get_tx_nss(_adapter *adapter, struct sta_info *psta) if (RF_TYPE_VALID(custom_rf_type)) rf_type = custom_rf_type; -#ifdef CONFIG_80211AC_VHT - if (psta->vhtpriv.vht_option) { - nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num); + +#ifdef CONFIG_80211N_HT + #ifdef CONFIG_80211AC_VHT + if (psta->vhtpriv.vht_option) nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map)); - } else -#endif /* CONFIG_80211AC_VHT */ - if (psta->htpriv.ht_option) { - nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + else + #endif /* CONFIG_80211AC_VHT */ + if (psta->htpriv.ht_option) nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set)); - } - +#endif /*CONFIG_80211N_HT*/ RTW_INFO("%s: %d SS\n", __func__, nss); return nss; } -u8 networktype_to_raid(_adapter *adapter, struct sta_info *psta) -{ - unsigned char raid; - switch (psta->wireless_mode) { - case WIRELESS_11B: - raid = RATR_INX_WIRELESS_B; - break; - case WIRELESS_11A: - case WIRELESS_11G: - raid = RATR_INX_WIRELESS_G; - break; - case WIRELESS_11BG: - raid = RATR_INX_WIRELESS_GB; - break; - case WIRELESS_11_24N: - case WIRELESS_11_5N: - raid = RATR_INX_WIRELESS_N; - break; - case WIRELESS_11A_5N: - case WIRELESS_11G_24N: - raid = RATR_INX_WIRELESS_NG; - break; - case WIRELESS_11BG_24N: - raid = RATR_INX_WIRELESS_NGB; - break; - default: - raid = RATR_INX_WIRELESS_GB; - break; - - } - return raid; - -} - -u8 networktype_to_raid_ex(_adapter *adapter, struct sta_info *psta) +s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta) { - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - u8 raid = RATEID_IDX_BGN_40M_1SS, cur_rf_type, rf_type, custom_rf_type; - s8 tx_nss; - - tx_nss = rtw_get_tx_nss(adapter, psta); - - switch (psta->wireless_mode) { - case WIRELESS_11B: - raid = RATEID_IDX_B; - break; - case WIRELESS_11A: - case WIRELESS_11G: - raid = RATEID_IDX_G; - break; - case WIRELESS_11BG: - raid = RATEID_IDX_BG; - break; - case WIRELESS_11_24N: - case WIRELESS_11_5N: - case WIRELESS_11A_5N: - case WIRELESS_11G_24N: - if (tx_nss == 1) - raid = RATEID_IDX_GN_N1SS; - else if (tx_nss == 2) - raid = RATEID_IDX_GN_N2SS; - else if (tx_nss == 3) - raid = RATEID_IDX_BGN_3SS; - else - RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); - break; - case WIRELESS_11B_24N: - case WIRELESS_11BG_24N: - if (psta->bw_mode == CHANNEL_WIDTH_20) { - if (tx_nss == 1) - raid = RATEID_IDX_BGN_20M_1SS_BN; - else if (tx_nss == 2) - raid = RATEID_IDX_BGN_20M_2SS_BN; - else if (tx_nss == 3) - raid = RATEID_IDX_BGN_3SS; - else - RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); - } else { - if (tx_nss == 1) - raid = RATEID_IDX_BGN_40M_1SS; - else if (tx_nss == 2) - raid = RATEID_IDX_BGN_40M_2SS; - else if (tx_nss == 3) - raid = RATEID_IDX_BGN_3SS; - else - RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); - } - break; -#ifdef CONFIG_80211AC_VHT - case WIRELESS_11_5AC: - if (tx_nss == 1) - raid = RATEID_IDX_VHT_1SS; - else if (tx_nss == 2) - raid = RATEID_IDX_VHT_2SS; - else if (tx_nss == 3) - raid = RATEID_IDX_VHT_3SS; - else - RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); - break; - case WIRELESS_11_24AC: - if (psta->bw_mode >= CHANNEL_WIDTH_80) { - if (tx_nss == 1) - raid = RATEID_IDX_VHT_1SS; - else if (tx_nss == 2) - raid = RATEID_IDX_VHT_2SS; - else if (tx_nss == 3) - raid = RATEID_IDX_VHT_3SS; - else - RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); - } else { - if (tx_nss == 1) - raid = RATEID_IDX_MIX1; - else if (tx_nss == 2) - raid = RATEID_IDX_MIX2; - else if (tx_nss == 3) - raid = RATEID_IDX_VHT_3SS; - else - RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); - } - break; -#endif - default: - RTW_INFO("unexpected wireless mode!(psta->wireless_mode=%x)\n", psta->wireless_mode); - break; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 rf_type = RF_1T1R, custom_rf_type; + s8 nss = 1; - } + if (!psta) + return nss; - /* RTW_INFO("psta->wireless_mode=%x, tx_nss=%d\n", psta->wireless_mode, tx_nss); */ + custom_rf_type = adapter->registrypriv.rf_config; + rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + if (RF_TYPE_VALID(custom_rf_type)) + rf_type = custom_rf_type; - return raid; + nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); +#ifdef CONFIG_80211N_HT + #ifdef CONFIG_80211AC_VHT + if (psta->vhtpriv.vht_option) + nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map)); + else + #endif /* CONFIG_80211AC_VHT */ + if (psta->htpriv.ht_option) + nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set)); +#endif /*CONFIG_80211N_HT*/ + RTW_INFO("%s: %d SS\n", __func__, nss); + return nss; } -#endif + u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen) { u8 network_type = 0; @@ -612,53 +540,6 @@ u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset) return valid; } -u8 rtw_get_offset_by_ch(u8 channel) -{ - u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - - if (channel >= 1 && channel <= 4) - offset = HAL_PRIME_CHNL_OFFSET_LOWER; - else if (channel >= 5 && channel <= 14) - offset = HAL_PRIME_CHNL_OFFSET_UPPER; - else { - switch (channel) { - case 36: - case 44: - case 52: - case 60: - case 100: - case 108: - case 116: - case 124: - case 132: - case 149: - case 157: - offset = HAL_PRIME_CHNL_OFFSET_LOWER; - break; - case 40: - case 48: - case 56: - case 64: - case 104: - case 112: - case 120: - case 128: - case 136: - case 153: - case 161: - offset = HAL_PRIME_CHNL_OFFSET_UPPER; - break; - default: - offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - break; - } - - } - - return offset; - -} - u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset) { u8 center_ch = channel; @@ -693,12 +574,12 @@ u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset) return center_ch; } -inline u32 rtw_get_on_oper_ch_time(_adapter *adapter) +inline systime rtw_get_on_oper_ch_time(_adapter *adapter) { return adapter_to_dvobj(adapter)->on_oper_ch_time; } -inline u32 rtw_get_on_cur_ch_time(_adapter *adapter) +inline systime rtw_get_on_cur_ch_time(_adapter *adapter) { if (adapter->mlmeextpriv.cur_channel == adapter_to_dvobj(adapter)->oper_channel) return adapter_to_dvobj(adapter)->on_oper_ch_time; @@ -732,10 +613,8 @@ void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char #ifdef CONFIG_MCC_MODE if (MCC_EN(padapter)) { /* driver doesn't set channel setting reg under MCC */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) RTW_INFO("Warning: Do not set channel setting reg MCC mode\n"); - rtw_warn_on(1); - } } #endif @@ -792,16 +671,6 @@ void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); } -int get_bsstype(unsigned short capability) -{ - if (capability & BIT(0)) - return WIFI_FW_AP_STATE; - else if (capability & BIT(1)) - return WIFI_FW_ADHOC_STATE; - else - return 0; -} - __inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork) { return pnetwork->MacAddress; @@ -852,7 +721,7 @@ int is_IBSS_empty(_adapter *padapter) for (i = 0; i < macid_ctl->num; i++) { if (!rtw_macid_is_used(macid_ctl, i)) continue; - if (rtw_macid_get_if_g(macid_ctl, i) != padapter->iface_id) + if (!rtw_macid_is_iface_specific(macid_ctl, i, padapter)) continue; if (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[i])) continue; @@ -1293,7 +1162,7 @@ s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk) return cam_id; } -s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid) +s16 rtw_get_camid(_adapter *adapter, u8 *addr, s16 kid, u8 gk) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; @@ -1314,7 +1183,7 @@ s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid) /* find cam entry which has the same addr, kid (, gk bit) */ if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC) == _TRUE) - i = _rtw_camid_search(adapter, addr, kid, sta ? _FALSE : _TRUE); + i = _rtw_camid_search(adapter, addr, kid, gk); else i = _rtw_camid_search(adapter, addr, kid, -1); @@ -1334,12 +1203,8 @@ s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid) } if (i == cam_ctl->num) { - if (sta) - RTW_PRINT(FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u no room\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid); - else - RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" id:%u no room\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid); + RTW_PRINT(FUNC_ADPT_FMT" %s key with "MAC_FMT" id:%u no room\n" + , FUNC_ADPT_ARG(adapter), gk ? "group" : "pairwise", MAC_ARG(addr), kid); rtw_warn_on(1); goto _exit; } @@ -1351,7 +1216,7 @@ s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid) return cam_id; } -s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used) +s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool *used) { struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info; struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); @@ -1365,8 +1230,12 @@ s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used) if ((((mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) && !sta) { + /* + * 1. non-STA mode WEP key + * 2. group TX key + */ #ifndef CONFIG_CONCURRENT_MODE - /* AP/Ad-hoc mode group key static alloction to default key by key ID on Non-concurrent*/ + /* static alloction to default key by key ID when concurrent is not defined */ if (kid > 3) { RTW_PRINT(FUNC_ADPT_FMT" group key with invalid key id:%u\n" , FUNC_ADPT_ARG(adapter), kid); @@ -1377,13 +1246,18 @@ s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used) #else u8 *addr = adapter_mac_addr(adapter); - cam_id = rtw_get_camid(adapter, sta, addr, kid); + cam_id = rtw_get_camid(adapter, addr, kid, gk); if (1) RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" assigned cam_id:%u\n" , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), cam_id); #endif } else { - u8 *addr = sta ? sta->hwaddr : NULL; + /* + * 1. STA mode WEP key + * 2. STA mode group RX key + * 3. sta key (pairwise, group RX) + */ + u8 *addr = sta ? sta->cmn.mac_addr : NULL; if (!sta) { if (!(mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) { @@ -1392,7 +1266,7 @@ s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used) } addr = get_bssid(&adapter->mlmepriv);/*A2*/ } - cam_id = rtw_get_camid(adapter, sta, addr, kid); + cam_id = rtw_get_camid(adapter, addr, kid, gk); } @@ -1552,7 +1426,7 @@ void flush_all_cam_entry(_adapter *padapter) } else rtw_clearstakey_cmd(padapter, psta, _FALSE); } - } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + } else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { #if 1 int cam_id = -1; u8 *addr = adapter_mac_addr(padapter); @@ -1670,6 +1544,10 @@ void WMMOnAssocRsp(_adapter *padapter) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct registry_priv *pregpriv = &padapter->registrypriv; +#ifdef CONFIG_WMMPS_STA + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct qos_priv *pqospriv = &pmlmepriv->qospriv; +#endif /* CONFIG_WMMPS_STA */ acm_mask = 0; @@ -1795,10 +1673,14 @@ void WMMOnAssocRsp(_adapter *padapter) pxmitpriv->wmm_para_seq[i] = inx[i]; RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]); } -#ifdef CONFIG_WMMPS - if (pmlmeinfo->WMM_param.QoS_info & BIT(7)) + +#ifdef CONFIG_WMMPS_STA + /* if AP supports UAPSD function, driver must set each uapsd TID to coresponding mac register 0x693 */ + if (pmlmeinfo->WMM_param.QoS_info & AP_SUPPORTED_UAPSD) { + pqospriv->uapsd_ap_supported = 1; rtw_hal_set_hwreg(padapter, HW_VAR_UAPSD_TID, NULL); -#endif + } +#endif /* CONFIG_WMMPS_STA */ } } @@ -1891,10 +1773,10 @@ static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pI if (phtpriv_sta->ht_option) { /* bwmode */ - psta->bw_mode = pmlmeext->cur_bwmode; + psta->cmn.bw_mode = pmlmeext->cur_bwmode; phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; } else { - psta->bw_mode = CHANNEL_WIDTH_20; + psta->cmn.bw_mode = CHANNEL_WIDTH_20; phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; } @@ -2235,21 +2117,29 @@ void update_ldpc_stbc_cap(struct sta_info *psta) #ifdef CONFIG_80211AC_VHT if (psta->vhtpriv.vht_option) { if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_ENABLE_TX)) - psta->ldpc = 1; + psta->cmn.ldpc_en = VHT_LDPC_EN; + else + psta->cmn.ldpc_en = 0; if (TEST_FLAG(psta->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX)) - psta->stbc = 1; + psta->cmn.stbc_en = VHT_STBC_EN; + else + psta->cmn.stbc_en = 0; } else #endif /* CONFIG_80211AC_VHT */ if (psta->htpriv.ht_option) { if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_ENABLE_TX)) - psta->ldpc = 1; + psta->cmn.ldpc_en = HT_LDPC_EN; + else + psta->cmn.ldpc_en = 0; if (TEST_FLAG(psta->htpriv.stbc_cap, STBC_HT_ENABLE_TX)) - psta->stbc = 1; + psta->cmn.stbc_en = HT_STBC_EN; + else + psta->cmn.stbc_en = 0; } else { - psta->ldpc = 0; - psta->stbc = 0; + psta->cmn.ldpc_en = 0; + psta->cmn.stbc_en = 0; } #endif /* CONFIG_80211N_HT */ @@ -2374,7 +2264,7 @@ int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len, recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA2; rtw_parse_wpa2_ie(elems.rsn_ie - 2, elems.rsn_ie_len + 2, &recv_beacon->group_cipher, &recv_beacon->pairwise_cipher, - &recv_beacon->is_8021x); + &recv_beacon->is_8021x, NULL); } /* checking WPA secon */ else if (elems.wpa_ie && elems.wpa_ie_len) { @@ -2649,7 +2539,7 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) pbuf = rtw_get_wpa2_ie(&bssid->IEs[12], &wpa_ielen, bssid->IELength - 12); if (pbuf && (wpa_ielen > 0)) { - rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is_8021x); + rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is_8021x, NULL); } } @@ -2746,20 +2636,17 @@ void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta } #ifdef CONFIG_DFS -void process_csa_ie(_adapter *padapter, u8 *pframe, uint pkt_len) +void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len) { unsigned int i; - unsigned int len; PNDIS_802_11_VARIABLE_IEs pIE; u8 new_ch_no = 0; if (padapter->mlmepriv.handle_dfs == _TRUE) return; - len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN); - - for (i = 0; i < len;) { - pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i); + for (i = 0; i + 1 < ies_len;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(ies + i); switch (pIE->ElementID) { case _CH_SWTICH_ANNOUNCE_: @@ -2985,13 +2872,27 @@ int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bw return _FAIL; } -unsigned char get_highest_rate_idx(u32 mask) +unsigned char get_highest_rate_idx(u64 mask) { int i; unsigned char rate_idx = 0; - for (i = 31; i >= 0; i--) { - if (mask & BIT(i)) { + for (i = 63; i >= 0; i--) { + if ((mask >> i) & 0x01) { + rate_idx = i; + break; + } + } + + return rate_idx; +} +unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit) +{ + int i; + unsigned char rate_idx = 0; + + for (i = start_bit; i < 64; i++) { + if ((mask >> i) & 0x01) { rate_idx = i; break; } @@ -3002,13 +2903,13 @@ unsigned char get_highest_rate_idx(u32 mask) void Update_RA_Entry(_adapter *padapter, struct sta_info *psta) { - rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); + rtw_hal_update_ra_mask(psta); } void set_sta_rate(_adapter *padapter, struct sta_info *psta) { /* rate adaptive */ - rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); + rtw_hal_update_ra_mask(psta); } /* Update RRSR and Rate for USERATE */ @@ -3367,6 +3268,33 @@ void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr) return; } +void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame) +{ + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + struct sta_info *psta = NULL; + struct recv_reorder_ctrl *preorder_ctrl = NULL; + u8 tid = 0; + u16 start_seq=0; + + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (psta == NULL) + goto exit; + + tid = ((cpu_to_le16((*(u16 *)(pframe + 16))) & 0xf000) >> 12); + preorder_ctrl = &psta->recvreorder_ctrl[tid]; + start_seq = ((cpu_to_le16(*(u16 *)(pframe + 18))) >> 4); + preorder_ctrl->indicate_seq = start_seq; + + /* for Debug use */ + if (0) + RTW_INFO(FUNC_ADPT_FMT" tid=%d, start_seq=%d\n", FUNC_ADPT_ARG(padapter), tid, start_seq); + +exit: + return; +} + void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len) { u8 *pIE; @@ -3483,8 +3411,6 @@ void beacon_timing_control(_adapter *padapter) rtw_hal_bcn_related_reg_setting(padapter); } -#define CONFIG_SHARED_BMC_MACID - void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num) { RTW_PRINT_SEL(sel, "0x%08x\n", map->m0); @@ -3544,22 +3470,6 @@ inline void rtw_macid_map_set(struct macid_bmp *map, u8 id) rtw_warn_on(1); } -/*Record bc's mac-id and sec-cam-id*/ -inline void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - - macid_ctl->iface_bmc[padapter->iface_id] = mac_id; -} -inline u8 rtw_iface_bcmc_id_get(_adapter *padapter) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - - return macid_ctl->iface_bmc[padapter->iface_id]; -} - inline void rtw_macid_map_clr(struct macid_bmp *map, u8 id) { if (id < 32) @@ -3590,24 +3500,48 @@ inline bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id) return rtw_macid_is_set(&macid_ctl->bmc, id); } -inline s8 rtw_macid_get_if_g(struct macid_ctl_t *macid_ctl, u8 id) +inline u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id) { int i; + u8 iface_bmp = 0; -#ifdef CONFIG_SHARED_BMC_MACID - if (rtw_macid_is_bmc(macid_ctl, id)) { - for (i = 0; i < CONFIG_IFACE_NUMBER; i++) - if (macid_ctl->iface_bmc[i] == id) - return i; - return -1; + for (i = 0; i < CONFIG_IFACE_NUMBER; i++) { + if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) + iface_bmp |= BIT(i); } -#endif + return iface_bmp; +} + +inline bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id) +{ + int i; + u8 iface_bmp = 0; for (i = 0; i < CONFIG_IFACE_NUMBER; i++) { - if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) - return i; + if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) { + if (iface_bmp) + return 1; + iface_bmp |= BIT(i); + } } - return -1; + + return 0; +} + +inline bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter) +{ + int i; + u8 iface_bmp = 0; + + for (i = 0; i < CONFIG_IFACE_NUMBER; i++) { + if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) { + if (iface_bmp || i != adapter->iface_id) + return 0; + iface_bmp |= BIT(i); + } + } + + return iface_bmp ? 1 : 0; } inline s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id) @@ -3621,6 +3555,22 @@ inline s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id) return -1; } +/*Record bc's mac-id and sec-cam-id*/ +inline void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + + macid_ctl->iface_bmc[padapter->iface_id] = mac_id; +} +inline u8 rtw_iface_bcmc_id_get(_adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + + return macid_ctl->iface_bmc[padapter->iface_id]; +} + void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta) { int i; @@ -3633,51 +3583,31 @@ void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta) u8 last_id = 0; u8 is_bc_sta = _FALSE; - if (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), ETH_ALEN)) { - psta->mac_id = macid_ctl->num; + if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)) { + psta->cmn.mac_id = macid_ctl->num; return; } - if (_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN)) { + if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) { is_bc_sta = _TRUE; rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); /*init default value*/ } -#ifdef CONFIG_SHARED_BMC_MACID if (is_bc_sta -#ifdef CONFIG_CONCURRENT_MODE - && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) || check_fwstate(&padapter->mlmepriv, WIFI_NULL_STATE)) -#endif - ) { - /* use shared broadcast & multicast macid 1 for all ifaces which configure to station mode*/ - _enter_critical_bh(&macid_ctl->lock, &irqL); - rtw_macid_map_set(used_map, 1); - rtw_macid_map_set(&macid_ctl->bmc, 1); - rtw_macid_map_set(&macid_ctl->if_g[padapter->iface_id], 1); - macid_ctl->sta[1] = psta; - /* TODO ch_g? */ - _exit_critical_bh(&macid_ctl->lock, &irqL); - i = 1; + #ifdef CONFIG_CONCURRENT_MODE + && (MLME_IS_STA(padapter) || MLME_IS_NULL(padapter)) + #endif + ) { + /* STA mode have no BMC data TX, shared with this macid */ + /* When non-concurrent, only one BMC data TX is used, shared with this macid */ + /* TODO: When concurrent, non-security BMC data TX may use this, but will not control by specific macid sleep */ + i = RTW_DEFAULT_MGMT_MACID; goto assigned; } -#endif - -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - if (MLME_IS_AP(padapter) || MLME_IS_GO(padapter)) - /* GO/AP assign client macid from 8 */ - last_id = 8; - } -#endif /* CONFIG_MCC_MODE */ _enter_critical_bh(&macid_ctl->lock, &irqL); for (i = last_id; i < macid_ctl->num; i++) { -#ifdef CONFIG_SHARED_BMC_MACID - if (i == 1) - continue; -#endif - #ifdef CONFIG_MCC_MODE /* macid 0/1 reserve for mcc for mgnt queue macid */ if (MCC_EN(padapter)) { @@ -3688,8 +3618,7 @@ void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta) } #endif /* CONFIG_MCC_MODE */ - if (is_bc_sta) {/*for SoftAP's Broadcast sta-info*/ - /*TODO:non-security AP may allociated macid = 1*/ + if (is_bc_sta) { struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); if ((!rtw_macid_is_used(macid_ctl, i)) && (!rtw_sec_camid_is_used(cam_ctl, i))) @@ -3724,18 +3653,18 @@ void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta) _exit_critical_bh(&macid_ctl->lock, &irqL); if (i >= macid_ctl->num) { - psta->mac_id = macid_ctl->num; - RTW_ERR(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" no available macid\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr)); + psta->cmn.mac_id = macid_ctl->num; + RTW_ERR(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" no available macid\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr)); rtw_warn_on(1); goto exit; } else goto assigned; assigned: - psta->mac_id = i; - RTW_INFO(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" macid:%u\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr), psta->mac_id); + psta->cmn.mac_id = i; + RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id); exit: return; @@ -3747,65 +3676,75 @@ void rtw_release_macid(_adapter *padapter, struct sta_info *psta) u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - u8 is_bc_sta = _FALSE; - - if (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), ETH_ALEN)) - return; - - if (_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN)) - is_bc_sta = _TRUE; + u8 ifbmp; + int i; -#ifdef CONFIG_SHARED_BMC_MACID - if (is_bc_sta -#ifdef CONFIG_CONCURRENT_MODE - && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) || check_fwstate(&padapter->mlmepriv, WIFI_NULL_STATE)) -#endif - ) - return; + if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)) + goto exit; - if (psta->mac_id == 1) { - RTW_ERR(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" with macid:%u\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr), psta->mac_id); - if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) || check_fwstate(&padapter->mlmepriv, WIFI_NULL_STATE)) - rtw_warn_on(1); - return; + if (psta->cmn.mac_id >= macid_ctl->num) { + RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not valid\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1 + , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id); + rtw_warn_on(1); + goto exit; } -#endif + + if (psta->cmn.mac_id == RTW_DEFAULT_MGMT_MACID) + goto msg; _enter_critical_bh(&macid_ctl->lock, &irqL); - if (psta->mac_id < macid_ctl->num) { - int i; + if (!rtw_macid_is_used(macid_ctl, psta->cmn.mac_id)) { + RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1 + , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id); + _exit_critical_bh(&macid_ctl->lock, &irqL); + rtw_warn_on(1); + goto exit; + } - if (!rtw_macid_is_used(macid_ctl, psta->mac_id)) { - RTW_ERR(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" macid:%u not used\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr), psta->mac_id); - rtw_warn_on(1); - } + ifbmp = rtw_macid_get_iface_bmp(macid_ctl, psta->cmn.mac_id); + if (!(ifbmp & BIT(padapter->iface_id))) { + RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used by self\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1 + , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id); + _exit_critical_bh(&macid_ctl->lock, &irqL); + rtw_warn_on(1); + goto exit; + } - rtw_macid_map_clr(&macid_ctl->used, psta->mac_id); - rtw_macid_map_clr(&macid_ctl->bmc, psta->mac_id); + if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) { + struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); + u8 id = rtw_iface_bcmc_id_get(padapter); - if (is_bc_sta) { - struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); - u8 id = rtw_iface_bcmc_id_get(padapter); + if ((id != INVALID_SEC_MAC_CAM_ID) && (id < cam_ctl->num)) + rtw_sec_cam_map_clr(&cam_ctl->used, id); - if ((id != INVALID_SEC_MAC_CAM_ID) && (id < cam_ctl->num)) - rtw_sec_cam_map_clr(&cam_ctl->used, id); + rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); + } - rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); - } + rtw_macid_map_clr(&macid_ctl->if_g[padapter->iface_id], psta->cmn.mac_id); - for (i = 0; i < CONFIG_IFACE_NUMBER; i++) - rtw_macid_map_clr(&macid_ctl->if_g[i], psta->mac_id); + ifbmp &= ~BIT(padapter->iface_id); + if (!ifbmp) { /* only used by self */ + rtw_macid_map_clr(&macid_ctl->used, psta->cmn.mac_id); + rtw_macid_map_clr(&macid_ctl->bmc, psta->cmn.mac_id); for (i = 0; i < 2; i++) - rtw_macid_map_clr(&macid_ctl->ch_g[i], psta->mac_id); - macid_ctl->sta[psta->mac_id] = NULL; + rtw_macid_map_clr(&macid_ctl->ch_g[i], psta->cmn.mac_id); + macid_ctl->sta[psta->cmn.mac_id] = NULL; } _exit_critical_bh(&macid_ctl->lock, &irqL); - psta->mac_id = macid_ctl->num; +msg: + RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1 + , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id + ); + +exit: + psta->cmn.mac_id = macid_ctl->num; } /* For 8188E RA */ @@ -3890,8 +3829,31 @@ inline void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u3 RTW_INFO("macid:%u, rate_bmp1:0x%08X\n", id, macid_ctl->rate_bmp1[id]); } +inline void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3) +{ + macid_ctl->reg_sleep_m0 = m0; +#if (MACID_NUM_SW_LIMIT > 32) + macid_ctl->reg_sleep_m1 = m1; +#endif +#if (MACID_NUM_SW_LIMIT > 64) + macid_ctl->reg_sleep_m2 = m2; +#endif +#if (MACID_NUM_SW_LIMIT > 96) + macid_ctl->reg_sleep_m3 = m3; +#endif +} + inline void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl) { + int i; + u8 id = RTW_DEFAULT_MGMT_MACID; + + rtw_macid_map_set(&macid_ctl->used, id); + rtw_macid_map_set(&macid_ctl->bmc, id); + for (i = 0; i < CONFIG_IFACE_NUMBER; i++) + rtw_macid_map_set(&macid_ctl->if_g[i], id); + macid_ctl->sta[id] = NULL; + _rtw_spinlock_init(&macid_ctl->lock); } @@ -3900,6 +3862,87 @@ inline void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl) _rtw_spinlock_free(&macid_ctl->lock); } +inline bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id) +{ + if (id / 8 >= bmp_len) + return 0; + + return bmp[id / 8] & BIT(id % 8); +} + +inline void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id) +{ + if (id / 8 < bmp_len) + bmp[id / 8] |= BIT(id % 8); +} + +inline void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id) +{ + if (id / 8 < bmp_len) + bmp[id / 8] &= ~BIT(id % 8); +} + +inline bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len) +{ + int i; + + for (i = 0; i < bmp_len; i++) { + if (bmp[i]) + return 1; + } + + return 0; +} + +inline bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len) +{ + int i; + + for (i = 0; i < bmp_len; i++) { + if (i == 0) { + if (bmp[i] & 0xFE) + return 1; + } else { + if (bmp[i]) + return 1; + } + } + + return 0; +} + +#ifdef CONFIG_AP_MODE +/* Check the id be set or not in map , if yes , return a none zero value*/ +bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id) +{ + return rtw_bmp_is_set(map, padapter->stapriv.aid_bmp_len, id); +} + +/* Set the id into map array*/ +void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id) +{ + rtw_bmp_set(map, padapter->stapriv.aid_bmp_len, id); +} + +/* Clear the id from map array*/ +void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id) +{ + rtw_bmp_clear(map, padapter->stapriv.aid_bmp_len, id); +} + +/* Check have anyone bit be set , if yes return true*/ +bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map) +{ + return rtw_bmp_not_empty(map, padapter->stapriv.aid_bmp_len); +} + +/* Check have anyone bit be set exclude bit0 , if yes return true*/ +bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map) +{ + return rtw_bmp_not_empty_exclude_bit0(map, padapter->stapriv.aid_bmp_len); +} +#endif /* CONFIG_AP_MODE */ + #if 0 unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame) { @@ -4130,7 +4173,10 @@ void rtw_wow_pattern_sw_reset(_adapter *adapter) int i; struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter); - pwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM; + if (pwrctrlpriv->default_patterns_en == _TRUE) + pwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM; + else + pwrctrlpriv->wowlan_pattern_idx = 0; for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) { _rtw_memset(pwrctrlpriv->patterns[i].content, '\0', sizeof(pwrctrlpriv->patterns[i].content)); @@ -4142,7 +4188,6 @@ void rtw_wow_pattern_sw_reset(_adapter *adapter) u8 rtw_set_default_pattern(_adapter *adapter) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); - struct registry_priv *pregistrypriv = &adapter->registrypriv; struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; u8 index = 0; @@ -4158,7 +4203,7 @@ u8 rtw_set_default_pattern(_adapter *adapter) u8 *target = NULL; - if (pregistrypriv->default_patterns_en == _FALSE) + if (pwrpriv->default_patterns_en == _FALSE) return 0; for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) { @@ -4218,6 +4263,7 @@ u8 rtw_set_default_pattern(_adapter *adapter) IP_OFFSET + RTW_IP_ADDR_LEN; break; +#ifdef CONFIG_IPV6 case 2: if (pwrpriv->wowlan_ns_offload_en == _TRUE) { target = pwrpriv->patterns[index].content; @@ -4241,6 +4287,7 @@ u8 rtw_set_default_pattern(_adapter *adapter) IPv6_OFFSET + RTW_IPv6_ADDR_LEN; } break; +#endif /*CONFIG_IPV6*/ case 3: target = pwrpriv->patterns[index].content; _rtw_memcpy(target, &multicast_addr, @@ -4507,11 +4554,7 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid, source = rtw_zmalloc(2048); if (source != NULL) { - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) - len = kernel_read(fp, source, len, &pos); - #else len = vfs_read(fp, source, len, &pos); - #endif rtw_parse_cipher_list(nlo_info, source); rtw_mfree(source, 2048); } diff --git a/core/rtw_xmit.c b/core/rtw_xmit.c index 0112c37..b480319 100644 --- a/core/rtw_xmit.c +++ b/core/rtw_xmit.c @@ -344,6 +344,9 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxmitpriv->amsdu_debug_timeout = 0; pxmitpriv->amsdu_debug_coalesce_one = 0; pxmitpriv->amsdu_debug_coalesce_two = 0; +#endif +#ifdef DBG_TXBD_DESC_DUMP + pxmitpriv->dump_txbd_desc = 0; #endif rtw_init_xmit_block(padapter); rtw_hal_init_xmit_priv(padapter); @@ -453,7 +456,7 @@ u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta) { u8 bw; - bw = sta->bw_mode; + bw = sta->cmn.bw_mode; if (MLME_STATE(adapter) & WIFI_ASOC_STATE) { if (adapter->mlmeextpriv.cur_channel <= 14) bw = rtw_min(bw, ADAPTER_TX_BW_2G(adapter)); @@ -483,7 +486,7 @@ void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ for (i = 0; i < macid_ctl->num; i++) { if (!rtw_macid_is_used(macid_ctl, i)) continue; - if (rtw_macid_get_if_g(macid_ctl, i) != adapter->iface_id) + if (!rtw_macid_is_iface_specific(macid_ctl, i, adapter)) continue; if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */ @@ -521,7 +524,7 @@ void rtw_get_shared_macid_tx_rate_bmp_by_bw(struct dvobj_priv *dvobj, u8 bw, u16 for (i = 0; i < macid_ctl->num; i++) { if (!rtw_macid_is_used(macid_ctl, i)) continue; - if (rtw_macid_get_if_g(macid_ctl, i) != -1) + if (!rtw_macid_is_iface_shared(macid_ctl, i)) continue; if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */ @@ -877,6 +880,38 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf } +#ifdef CONFIG_WMMPS_STA +/* + * update_attrib_trigger_frame_info + * For Station mode, if a specific TID of driver setting and an AP support uapsd function, the data + * frame with corresponding TID will be a trigger frame when driver is in wmm power saving mode. + * + * Arguments: + * @padapter: _adapter pointer. + * @pattrib: pkt_attrib pointer. + * + * Auther: Arvin Liu + * Date: 2017/06/05 + */ +static void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib) { + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + u8 trigger_frame_en = 0; + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + if ((pwrpriv->pwr_mode == PS_MODE_MIN) || (pwrpriv->pwr_mode == PS_MODE_MAX)) { + if((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT(pattrib->priority)) == _TRUE)) { + trigger_frame_en = 1; + RTW_INFO("[WMMPS]"FUNC_ADPT_FMT": This is a Trigger Frame\n", FUNC_ADPT_ARG(padapter)); + } + } + } + + pattrib->trigger_frame = trigger_frame_en; +} +#endif /* CONFIG_WMMPS_STA */ + static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta) { struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; @@ -893,14 +928,14 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri /* qos_en, ht_en, init rate, ,bw, ch_offset, sgi */ pattrib->qos_en = psta->qos_option; - pattrib->raid = psta->raid; + pattrib->raid = psta->cmn.ra_info.rate_id; bw = rtw_get_tx_bw_mode(padapter, psta); pattrib->bwmode = rtw_min(bw, mlmeext->cur_bwmode); pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode); - pattrib->ldpc = psta->ldpc; - pattrib->stbc = psta->stbc; + pattrib->ldpc = psta->cmn.ldpc_en; + pattrib->stbc = psta->cmn.stbc_en; #ifdef CONFIG_80211N_HT pattrib->ht_en = psta->htpriv.ht_option; @@ -933,7 +968,7 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri if (pattrib->direct_link == _TRUE) { psta = pattrib->ptdls_sta; - pattrib->raid = psta->raid; + pattrib->raid = psta->cmn.ra_info.rate_id; #ifdef CONFIG_80211N_HT pattrib->bwmode = rtw_get_tx_bw_mode(padapter, psta); pattrib->ht_en = psta->htpriv.ht_option; @@ -961,7 +996,7 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib _rtw_memset(pattrib->dot118021x_UncstKey.skey, 0, 16); _rtw_memset(pattrib->dot11tkiptxmickey.skey, 0, 16); - pattrib->mac_id = psta->mac_id; + pattrib->mac_id = psta->cmn.mac_id; if (psta->ieee8021x_blocked == _TRUE) { @@ -1205,7 +1240,7 @@ s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib) goto exit; } - pattrib->mac_id = psta->mac_id; + pattrib->mac_id = psta->cmn.mac_id; pattrib->psta = psta; pattrib->ack_policy = 0; /* get ether_hdr_len */ @@ -1243,13 +1278,14 @@ inline u8 rtw_get_hwseq_no(_adapter *padapter) { u8 hwseq_num = 0; #ifdef CONFIG_CONCURRENT_MODE - if (padapter->adapter_type != PRIMARY_ADAPTER) + if (!is_primary_adapter(padapter)) hwseq_num = 1; /* else */ /* hwseq_num = 2; */ #endif /* CONFIG_CONCURRENT_MODE */ return hwseq_num; } + static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib) { uint i; @@ -1273,11 +1309,12 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr pattrib->ether_type = ntohs(etherhdr.h_proto); + if (MLME_IS_MESH(padapter)) /* address resolve is done for mesh */ + goto get_sta_info; _rtw_memcpy(pattrib->dst, ðerhdr.h_dest, ETH_ALEN); _rtw_memcpy(pattrib->src, ðerhdr.h_source, ETH_ALEN); - if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); @@ -1299,14 +1336,15 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr } else DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_unknown); +get_sta_info: bmcast = IS_MCAST(pattrib->ra); if (bmcast) { psta = rtw_get_bcmc_stainfo(padapter); if (psta == NULL) { /* if we cannot get psta => drop the pkt */ DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta); -#ifdef DBG_TX_DROP_FRAME + #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra)); -#endif + #endif res = _FAIL; goto exit; } @@ -1314,9 +1352,9 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr psta = rtw_get_stainfo(pstapriv, pattrib->ra); if (psta == NULL) { /* if we cannot get psta => drop the pkt */ DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta); -#ifdef DBG_TX_DROP_FRAME + #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra)); -#endif + #endif res = _FAIL; goto exit; } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && !(psta->state & _FW_LINKED)) { @@ -1328,7 +1366,8 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr if (!(psta->state & _FW_LINKED)) { DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link); - RTW_INFO("%s-"ADPT_FMT" psta("MAC_FMT")->state(0x%x) != _FW_LINKED\n", __func__, ADPT_ARG(padapter), MAC_ARG(psta->hwaddr), psta->state); + RTW_INFO("%s-"ADPT_FMT" psta("MAC_FMT")->state(0x%x) != _FW_LINKED\n", + __func__, ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state); res = _FAIL; goto exit; } @@ -1455,9 +1494,19 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr pattrib->subtype = WIFI_DATA_TYPE; pattrib->priority = 0; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { - if (pattrib->qos_en) + if (bmcast) + pattrib->rate = psta->init_rate; + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE + | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) + ) { + if (pattrib->qos_en) { set_qos(&pktfile, pattrib); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_mesh_tx_set_whdr_mctrl_len(pattrib->mesh_frame_mode, pattrib); + #endif + } } else { #ifdef CONFIG_TDLS if (pattrib->direct_link == _TRUE) { @@ -1475,6 +1524,10 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr } } +#ifdef CONFIG_WMMPS_STA + update_attrib_trigger_frame_info(padapter, pattrib); +#endif /* CONFIG_WMMPS_STA */ + /* pattrib->priority = 5; */ /* force to used VI queue, for testing */ pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; rtw_set_tx_chksum_offload(pkt, pattrib); @@ -1736,6 +1789,17 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) if (pattrib->qos_en) qos_option = _TRUE; +#ifdef CONFIG_RTW_MESH + } else if (check_fwstate(pmlmepriv, WIFI_MESH_STATE) == _TRUE) { + rtw_mesh_tx_build_whdr(padapter, pattrib, fctrl, pwlanhdr); + if (pattrib->qos_en) + qos_option = _TRUE; + else { + RTW_WARN("[%s] !qos_en in Mesh\n", __FUNCTION__); + res = _FAIL; + goto exit; + } +#endif } else { res = _FAIL; goto exit; @@ -1759,6 +1823,18 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) if(pattrib->amsdu) SetAMsdu(qc, pattrib->amsdu); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* active: don't care, light sleep: 0, deep sleep: 1*/ + set_mps_lv(qc, 0); //TBD + + /* TBD: temporary set (rspi, eosp) = (0, 1) which means End MPSP */ + set_rspi(qc, 0); + SetEOSP(qc, 1); + + set_mctrl_present(qc, 1); + } +#endif } /* TODO: fill HT Control Field */ @@ -1903,37 +1979,53 @@ s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib) int rtw_build_tdls_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) { + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct sta_info *ptdls_sta = NULL; int res = _SUCCESS; + ptdls_sta = rtw_get_stainfo((&padapter->stapriv), pattrib->dst); + if (ptdls_sta == NULL) { + switch (ptxmgmt->action_code) { + case TDLS_DISCOVERY_REQUEST: + case TUNNELED_PROBE_REQ: + case TUNNELED_PROBE_RSP: + break; + default: + RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(pattrib->dst), ptxmgmt->action_code); + res = _FAIL; + goto exit; + } + } + switch (ptxmgmt->action_code) { case TDLS_SETUP_REQUEST: - rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; case TDLS_SETUP_RESPONSE: - rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; case TDLS_SETUP_CONFIRM: - rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; case TDLS_TEARDOWN: - rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; case TDLS_DISCOVERY_REQUEST: rtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe, ptxmgmt); break; case TDLS_PEER_TRAFFIC_INDICATION: - rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; #ifdef CONFIG_TDLS_CH_SW case TDLS_CHANNEL_SWITCH_REQUEST: - rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; case TDLS_CHANNEL_SWITCH_RESPONSE: - rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; #endif case TDLS_PEER_TRAFFIC_RESPONSE: - rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; #ifdef CONFIG_WFD case TUNNELED_PROBE_REQ: @@ -1948,6 +2040,7 @@ int rtw_build_tdls_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pf break; } +exit: return res; } @@ -2038,7 +2131,7 @@ s32 rtw_make_tdls_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattr pattrib->icv_len = 8; pattrib->bswenc = _FALSE; } - pattrib->mac_id = ptdls_sta->mac_id; + pattrib->mac_id = ptdls_sta->cmn.mac_id; } else { res = _FAIL; goto exit; @@ -2172,12 +2265,14 @@ u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib) { u32 len = 0; - len = pattrib->hdrlen + pattrib->iv_len; /* WLAN Header and IV */ - len += SNAP_SIZE + sizeof(u16); /* LLC */ - len += pattrib->pktlen; - if (pattrib->encrypt == _TKIP_) - len += 8; /* MIC */ - len += ((pattrib->bswenc) ? pattrib->icv_len : 0); /* ICV */ + len = pattrib->hdrlen /* WLAN Header */ + + pattrib->iv_len /* IV */ + + XATTRIB_GET_MCTRL_LEN(pattrib) + + SNAP_SIZE + sizeof(u16) /* LLC */ + + pattrib->pktlen + + (pattrib->encrypt == _TKIP_ ? 8 : 0) /* MIC */ + + (pattrib->bswenc ? pattrib->icv_len : 0) /* ICV */ + ; return len; } @@ -2210,6 +2305,9 @@ s32 check_amsdu(struct xmit_frame *pxmitframe) if (!pattrib->qos_en) ret = _FALSE; + if (IS_AMSDU_AMPDU_NOT_VALID(pattrib)) + ret = _FALSE; + return ret; } @@ -2283,7 +2381,6 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra pattrib->amsdu = 1; if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n")); RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n"); res = _FAIL; goto exit; @@ -2302,9 +2399,8 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra if (pattrib->iv_len) { _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); // queue or new? - RT_TRACE(_module_rtl871x_xmit_c_, _drv_notice_, - ("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n", - padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3))); + RTW_DBG("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n", + padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3)); pframe += pattrib->iv_len; } @@ -2319,16 +2415,28 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra _rtw_open_pktfile(pkt_queue, &pktfile_queue); _rtw_pktfile_read(&pktfile_queue, NULL, pattrib_queue->pkt_hdrlen); - /* 802.3 MAC Header DA(6) SA(6) Len(2)*/ - - _rtw_memcpy(pframe, pattrib_queue->dst, ETH_ALEN); - pframe += ETH_ALEN; - - _rtw_memcpy(pframe, pattrib_queue->src, ETH_ALEN); - pframe += ETH_ALEN; - - len = (u16*) pframe; - pframe += 2; + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* mDA(6), mSA(6), len(2), mctrl */ + _rtw_memcpy(pframe, pattrib_queue->mda, ETH_ALEN); + pframe += ETH_ALEN; + _rtw_memcpy(pframe, pattrib_queue->msa, ETH_ALEN); + pframe += ETH_ALEN; + len = (u16*)pframe; + pframe += 2; + rtw_mesh_tx_build_mctrl(padapter, pattrib_queue, pframe); + pframe += XATTRIB_GET_MCTRL_LEN(pattrib_queue); + } else + #endif + { + /* 802.3 MAC Header DA(6) SA(6) Len(2)*/ + _rtw_memcpy(pframe, pattrib_queue->dst, ETH_ALEN); + pframe += ETH_ALEN; + _rtw_memcpy(pframe, pattrib_queue->src, ETH_ALEN); + pframe += ETH_ALEN; + len = (u16*)pframe; + pframe += 2; + } llc_sz = rtw_put_snap(pframe, pattrib_queue->ether_type); pframe += llc_sz; @@ -2336,17 +2444,17 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra mem_sz = _rtw_pktfile_read(&pktfile_queue, pframe, pattrib_queue->pktlen); pframe += mem_sz; - *len = htons(llc_sz + mem_sz); + *len = htons(XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz); //calc padding - padding = 4 - ((ETH_HLEN + llc_sz + mem_sz) & (4-1)); + padding = 4 - ((ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz) & (4-1)); if(padding == 4) padding = 0; //_rtw_memset(pframe,0xaa, padding); pframe += padding; - pattrib->last_txcmdsz += ETH_HLEN + llc_sz + mem_sz + padding ; + pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz + padding ; } //2nd mpdu @@ -2355,16 +2463,28 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra _rtw_open_pktfile(pkt, &pktfile); _rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen); - /* 802.3 MAC Header DA(6) SA(6) Len(2) */ - - _rtw_memcpy(pframe, pattrib->dst, ETH_ALEN); - pframe += ETH_ALEN; - - _rtw_memcpy(pframe, pattrib->src, ETH_ALEN); - pframe += ETH_ALEN; - - len = (u16*) pframe; - pframe += 2; +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* mDA(6), mSA(6), len(2), mctrl */ + _rtw_memcpy(pframe, pattrib->mda, ETH_ALEN); + pframe += ETH_ALEN; + _rtw_memcpy(pframe, pattrib->msa, ETH_ALEN); + pframe += ETH_ALEN; + len = (u16*)pframe; + pframe += 2; + rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe); + pframe += XATTRIB_GET_MCTRL_LEN(pattrib); + } else +#endif + { + /* 802.3 MAC Header DA(6) SA(6) Len(2) */ + _rtw_memcpy(pframe, pattrib->dst, ETH_ALEN); + pframe += ETH_ALEN; + _rtw_memcpy(pframe, pattrib->src, ETH_ALEN); + pframe += ETH_ALEN; + len = (u16*)pframe; + pframe += 2; + } llc_sz = rtw_put_snap(pframe, pattrib->ether_type); pframe += llc_sz; @@ -2373,14 +2493,14 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra pframe += mem_sz; - *len = htons(llc_sz + mem_sz); + *len = htons(XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz); //the last ampdu has no padding padding = 0; pattrib->nr_frags = 1; - pattrib->last_txcmdsz += ETH_HLEN + llc_sz + mem_sz + padding + + pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz + padding + ((pattrib->bswenc) ? pattrib->icv_len : 0) ; if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { @@ -2389,7 +2509,6 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra } if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n")); RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"); res = _FAIL; goto exit; @@ -2550,6 +2669,14 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm } if (frg_inx == 0) { + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe); + pframe += XATTRIB_GET_MCTRL_LEN(pattrib); + mpdu_len -= XATTRIB_GET_MCTRL_LEN(pattrib); + } + #endif + llc_sz = rtw_put_snap(pframe, pattrib->ether_type); pframe += llc_sz; mpdu_len -= llc_sz; @@ -2577,7 +2704,8 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) { pattrib->nr_frags = frg_inx; - pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + ((pattrib->nr_frags == 1) ? llc_sz : 0) + + pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + + ((pattrib->nr_frags == 1) ? (XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz) : 0) + ((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz; ClearMFrag(mem_start); @@ -2611,15 +2739,23 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm return res; } -#ifdef CONFIG_IEEE80211W -/* broadcast or multicast management pkt use BIP, unicast management pkt use CCMP encryption */ +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) +/* + * CCMP encryption for unicast robust mgmt frame and broadcast group privicy action + * BIP for broadcast robust mgmt frame + */ s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe) { +#define DBG_MGMT_XMIT_COALESEC_DUMP 0 +#define DBG_MGMT_XMIT_BIP_DUMP 0 +#define DBG_MGMT_XMIT_ENC_DUMP 0 + struct pkt_file pktfile; s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz; SIZE_PTR addr; u8 *pframe, *mem_start = NULL, *tmp_buf = NULL; u8 hw_hdr_offset, subtype ; + u8 category = 0xFF; struct sta_info *psta = NULL; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct pkt_attrib *pattrib = &pxmitframe->attrib; @@ -2636,204 +2772,281 @@ s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame _irqL irqL; u32 ori_len; + union pn48 *pn = NULL; + u8 kid; + + if (pxmitframe->buf_addr == NULL) { + RTW_WARN(FUNC_ADPT_FMT" pxmitframe->buf_addr\n" + , FUNC_ADPT_ARG(padapter)); + return _FAIL; + } + mem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */ + + /* check if robust mgmt frame */ + if (subtype != WIFI_DEAUTH && subtype != WIFI_DISASSOC && subtype != WIFI_ACTION) + return _SUCCESS; + if (subtype == WIFI_ACTION) { + category = *(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + if (CATEGORY_IS_NON_ROBUST(category)) + return _SUCCESS; + } + if (!bmcst) { + if (pattrib->psta) + psta = pattrib->psta; + else + pattrib->psta = psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if (psta == NULL) { + RTW_INFO(FUNC_ADPT_FMT" unicast sta == NULL\n", FUNC_ADPT_ARG(padapter)); + return _FAIL; + } + if (!(psta->flags & WLAN_STA_MFP)) { + /* peer is not MFP capable, no need to encrypt */ + return _SUCCESS; + } + if (psta->bpairwise_key_installed != _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" PTK is not installed\n" + , FUNC_ADPT_ARG(padapter)); + return _FAIL; + } + } ori_len = BIP_AAD_SIZE + pattrib->pktlen; tmp_buf = BIP_AAD = rtw_zmalloc(ori_len); - subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */ - if (BIP_AAD == NULL) return _FAIL; _enter_critical_bh(&padapter->security_key_mutex, &irqL); - - /* IGTK key is not install, it may not support 802.11w */ - if (padapter->securitypriv.binstallBIPkey != _TRUE) { - RTW_INFO("no instll BIP key\n"); - goto xmitframe_coalesce_success; - } - /* station mode doesn't need TX BIP, just ready the code */ if (bmcst) { - int frame_body_len; - u8 mic[16]; - - _rtw_memset(MME, 0, _MME_IE_LENGTH_); - - /* other types doesn't need the BIP */ - if (get_frame_sub_type(pframe) != WIFI_DEAUTH && get_frame_sub_type(pframe) != WIFI_DISASSOC) - goto xmitframe_coalesce_fail; + if (subtype == WIFI_ACTION && CATEGORY_IS_GROUP_PRIVACY(category)) { + /* broadcast group privacy action frame */ + #if DBG_MGMT_XMIT_COALESEC_DUMP + RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u)\n" + , FUNC_ADPT_ARG(padapter), category); + #endif - MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - pframe += pattrib->pktlen; - - /* octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 */ - MME[0] = padapter->securitypriv.dot11wBIPKeyid; - /* copy packet number */ - _rtw_memcpy(&MME[2], &pmlmeext->mgnt_80211w_IPN, 6); - /* increase the packet number */ - pmlmeext->mgnt_80211w_IPN++; - - /* add MME IE with MIC all zero, MME string doesn't include element id and length */ - pframe = rtw_set_ie(pframe, _MME_IE_ , 16 , MME, &(pattrib->pktlen)); - pattrib->last_txcmdsz = pattrib->pktlen; - /* total frame length - header length */ - frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr); - - /* conscruct AAD, copy frame control field */ - _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); - ClearRetry(BIP_AAD); - ClearPwrMgt(BIP_AAD); - ClearMData(BIP_AAD); - /* conscruct AAD, copy address 1 to address 3 */ - _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18); - /* copy management fram body */ - _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, MGMT_body, frame_body_len); -#if 0 - /* dump total packet include MME with zero MIC */ - { - int i; - printk("Total packet: "); - for (i = 0; i < BIP_AAD_SIZE + frame_body_len; i++) - printk(" %02x ", BIP_AAD[i]); - printk("\n"); - } -#endif - /* calculate mic */ - if (omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey - , BIP_AAD, BIP_AAD_SIZE + frame_body_len, mic)) - goto xmitframe_coalesce_fail; - -#if 0 - /* dump calculated mic result */ - { - int i; - printk("Calculated mic result: "); - for (i = 0; i < 16; i++) - printk(" %02x ", mic[i]); - printk("\n"); - } -#endif - /* copy right BIP mic value, total is 128bits, we use the 0~63 bits */ - _rtw_memcpy(pframe - 8, mic, 8); - /*/dump all packet after mic ok - { - int pp; - printk("pattrib->pktlen = %d\n", pattrib->pktlen); - for(pp=0;pp< pattrib->pktlen; pp++) - printk(" %02x ", mem_start[pp]); - printk("\n"); - }*/ - } else { /* unicast mgmt frame TX */ - /* start to encrypt mgmt frame */ - if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || - subtype == WIFI_REASSOCREQ || subtype == WIFI_ACTION) { if (pattrib->psta) psta = pattrib->psta; else - psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); - + pattrib->psta = psta = rtw_get_bcmc_stainfo(padapter); if (psta == NULL) { - - RTW_INFO("%s, psta==NUL\n", __func__); + RTW_INFO(FUNC_ADPT_FMT" broadcast sta == NULL\n" + , FUNC_ADPT_ARG(padapter)); goto xmitframe_coalesce_fail; } - - if (pxmitframe->buf_addr == NULL) { - RTW_INFO("%s, pxmitframe->buf_addr\n", __func__); + if (padapter->securitypriv.binstallGrpkey != _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" GTK is not installed\n" + , FUNC_ADPT_ARG(padapter)); goto xmitframe_coalesce_fail; } - /* RTW_INFO("%s, action frame category=%d\n", __func__, pframe[WLAN_HDR_A3_LEN]); */ - /* according 802.11-2012 standard, these five types are not robust types */ - if (subtype == WIFI_ACTION && - (pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_PUBLIC || - pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_HT || - pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_UNPROTECTED_WNM || - pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_SELF_PROTECTED || - pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_P2P)) - goto xmitframe_coalesce_fail; - /* before encrypt dump the management packet content */ - /*{ - int i; - printk("Management pkt: "); - for(i=0; ipktlen; i++) - printk(" %02x ", pframe[i]); - printk("=======\n"); - }*/ - if (pattrib->encrypt > 0) - _rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16); - - /* To use wrong key */ - if (pattrib->key_type == IEEE80211W_WRONG_KEY) { - RTW_INFO("use wrong key\n"); - pattrib->dot118021x_UncstKey.skey[0] = 0xff; + pn = &psta->dot11txpn; + kid = padapter->securitypriv.dot118021XGrpKeyid; + } else { + #ifdef CONFIG_IEEE80211W + /* broadcast robust mgmt frame, using BIP */ + int frame_body_len; + u8 mic[16]; + + /* IGTK key is not install ex: mesh MFP without IGTK */ + if (SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) != _TRUE) + goto xmitframe_coalesce_success; + + #if DBG_MGMT_XMIT_COALESEC_DUMP + if (subtype == WIFI_DEAUTH) + RTW_INFO(FUNC_ADPT_FMT" braodcast deauth\n", FUNC_ADPT_ARG(padapter)); + else if (subtype == WIFI_DISASSOC) + RTW_INFO(FUNC_ADPT_FMT" braodcast disassoc\n", FUNC_ADPT_ARG(padapter)); + else if (subtype == WIFI_ACTION) { + RTW_INFO(FUNC_ADPT_FMT" braodcast action(%u)\n" + , FUNC_ADPT_ARG(padapter), category); } + #endif - /* bakeup original management packet */ - _rtw_memcpy(tmp_buf, pframe, pattrib->pktlen); - /* move to data portion */ - pframe += pattrib->hdrlen; + _rtw_memset(MME, 0, _MME_IE_LENGTH_); - /* 802.11w unicast management packet must be _AES_ */ - pattrib->iv_len = 8; - /* it's MIC of AES */ - pattrib->icv_len = 8; + MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + pframe += pattrib->pktlen; - switch (pattrib->encrypt) { - case _AES_: - /* set AES IV header */ - AES_IV(pattrib->iv, psta->dot11wtxpn, 0); - break; - default: - goto xmitframe_coalesce_fail; - } - /* insert iv header into management frame */ - _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); - pframe += pattrib->iv_len; - /* copy mgmt data portion after CCMP header */ - _rtw_memcpy(pframe, tmp_buf + pattrib->hdrlen, pattrib->pktlen - pattrib->hdrlen); - /* move pframe to end of mgmt pkt */ - pframe += pattrib->pktlen - pattrib->hdrlen; - /* add 8 bytes CCMP IV header to length */ - pattrib->pktlen += pattrib->iv_len; -#if 0 - /* dump management packet include AES IV header */ + /* octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 */ + MME[0] = padapter->securitypriv.dot11wBIPKeyid; + /* increase PN and apply to packet */ + padapter->securitypriv.dot11wBIPtxpn.val++; + RTW_PUT_LE64(&MME[2], padapter->securitypriv.dot11wBIPtxpn.val); + + /* add MME IE with MIC all zero, MME string doesn't include element id and length */ + pframe = rtw_set_ie(pframe, _MME_IE_ , 16 , MME, &(pattrib->pktlen)); + pattrib->last_txcmdsz = pattrib->pktlen; + /* total frame length - header length */ + frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr); + + /* conscruct AAD, copy frame control field */ + _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); + ClearRetry(BIP_AAD); + ClearPwrMgt(BIP_AAD); + ClearMData(BIP_AAD); + /* conscruct AAD, copy address 1 to address 3 */ + _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18); + /* copy management fram body */ + _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, MGMT_body, frame_body_len); + + #if DBG_MGMT_XMIT_BIP_DUMP + /* dump total packet include MME with zero MIC */ { int i; - printk("Management pkt + IV: "); - /* for(i=0; ipktlen; i++) */ - - printk("@@@@@@@@@@@@@\n"); + printk("Total packet: "); + for (i = 0; i < BIP_AAD_SIZE + frame_body_len; i++) + printk(" %02x ", BIP_AAD[i]); + printk("\n"); } -#endif + #endif - if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { - _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); - pframe += pattrib->icv_len; - } - /* add 8 bytes MIC */ - pattrib->pktlen += pattrib->icv_len; - /* set final tx command size */ - pattrib->last_txcmdsz = pattrib->pktlen; + /* calculate mic */ + if (omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey + , BIP_AAD, BIP_AAD_SIZE + frame_body_len, mic)) + goto xmitframe_coalesce_fail; - /* set protected bit must be beofre SW encrypt */ - SetPrivacy(mem_start); -#if 0 - /* dump management packet include AES header */ + #if DBG_MGMT_XMIT_BIP_DUMP + /* dump calculated mic result */ { int i; - printk("prepare to enc Management pkt + IV: "); - for (i = 0; i < pattrib->pktlen; i++) - printk(" %02x ", mem_start[i]); - printk("@@@@@@@@@@@@@\n"); + printk("Calculated mic result: "); + for (i = 0; i < 16; i++) + printk(" %02x ", mic[i]); + printk("\n"); } -#endif - /* software encrypt */ - xmitframe_swencrypt(padapter, pxmitframe); + #endif + + /* copy right BIP mic value, total is 128bits, we use the 0~63 bits */ + _rtw_memcpy(pframe - 8, mic, 8); + + #if DBG_MGMT_XMIT_BIP_DUMP + /*dump all packet after mic ok */ + { + int pp; + printk("pattrib->pktlen = %d\n", pattrib->pktlen); + for(pp=0;pp< pattrib->pktlen; pp++) + printk(" %02x ", mem_start[pp]); + printk("\n"); + } + #endif + + #endif /* CONFIG_IEEE80211W */ + + goto xmitframe_coalesce_success; + } + } + else { + /* unicast robust mgmt frame */ + #if DBG_MGMT_XMIT_COALESEC_DUMP + if (subtype == WIFI_DEAUTH) { + RTW_INFO(FUNC_ADPT_FMT" unicast deauth to "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra)); + } else if (subtype == WIFI_DISASSOC) { + RTW_INFO(FUNC_ADPT_FMT" unicast disassoc to "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra)); + } else if (subtype == WIFI_ACTION) { + RTW_INFO(FUNC_ADPT_FMT" unicast action(%u) to "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), category, MAC_ARG(pattrib->ra)); } + #endif + + _rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16); + + /* To use wrong key */ + if (pattrib->key_type == IEEE80211W_WRONG_KEY) { + RTW_INFO("use wrong key\n"); + pattrib->dot118021x_UncstKey.skey[0] = 0xff; + } + + pn = &psta->dot11txpn; + kid = 0; + } + + #if DBG_MGMT_XMIT_ENC_DUMP + /* before encrypt dump the management packet content */ + { + int i; + printk("Management pkt: "); + for(i=0; ipktlen; i++) + printk(" %02x ", pframe[i]); + printk("=======\n"); + } + #endif + + /* bakeup original management packet */ + _rtw_memcpy(tmp_buf, pframe, pattrib->pktlen); + /* move to data portion */ + pframe += pattrib->hdrlen; + + /* 802.11w encrypted management packet must be _AES_ */ + if (pattrib->key_type != IEEE80211W_NO_KEY) { + pattrib->encrypt = _AES_; + pattrib->bswenc = _TRUE; + } + + pattrib->iv_len = 8; + /* it's MIC of AES */ + pattrib->icv_len = 8; + + switch (pattrib->encrypt) { + case _AES_: + /* set AES IV header */ + AES_IV(pattrib->iv, (*pn), kid); + break; + default: + goto xmitframe_coalesce_fail; + } + + /* insert iv header into management frame */ + _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); + pframe += pattrib->iv_len; + /* copy mgmt data portion after CCMP header */ + _rtw_memcpy(pframe, tmp_buf + pattrib->hdrlen, pattrib->pktlen - pattrib->hdrlen); + /* move pframe to end of mgmt pkt */ + pframe += pattrib->pktlen - pattrib->hdrlen; + /* add 8 bytes CCMP IV header to length */ + pattrib->pktlen += pattrib->iv_len; + + #if DBG_MGMT_XMIT_ENC_DUMP + /* dump management packet include AES IV header */ + { + int i; + printk("Management pkt + IV: "); + /* for(i=0; ipktlen; i++) */ + + printk("@@@@@@@@@@@@@\n"); + } + #endif + + if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { + _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); + pframe += pattrib->icv_len; } + /* add 8 bytes MIC */ + pattrib->pktlen += pattrib->icv_len; + /* set final tx command size */ + pattrib->last_txcmdsz = pattrib->pktlen; + + /* set protected bit must be beofre SW encrypt */ + SetPrivacy(mem_start); + + #if DBG_MGMT_XMIT_ENC_DUMP + /* dump management packet include AES header */ + { + int i; + printk("prepare to enc Management pkt + IV: "); + for (i = 0; i < pattrib->pktlen; i++) + printk(" %02x ", mem_start[i]); + printk("@@@@@@@@@@@@@\n"); + } + #endif + + /* software encrypt */ + xmitframe_swencrypt(padapter, pxmitframe); xmitframe_coalesce_success: _exit_critical_bh(&padapter->security_key_mutex, &irqL); @@ -2846,7 +3059,7 @@ s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame return _FAIL; } -#endif /* CONFIG_IEEE80211W */ +#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */ /* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header * IEEE LLC/SNAP header contains 8 octets @@ -2947,13 +3160,6 @@ void rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, int sz pstats->tx_pkts += pkt_num; pstats->tx_bytes += sz; -#ifdef CONFIG_TDLS - if (pxmitframe->attrib.ptdls_sta != NULL) { - pstats = &(pxmitframe->attrib.ptdls_sta->sta_stats); - pstats->tx_pkts += pkt_num; - pstats->tx_bytes += sz; - } -#endif /* CONFIG_TDLS */ } #ifdef CONFIG_CHECK_LEAVE_LPS @@ -3704,7 +3910,7 @@ __inline static struct tx_servq *rtw_get_sta_pending #ifdef CONFIG_RTL8711 - if (IS_MCAST(psta->hwaddr)) { + if (IS_MCAST(psta->cmn.mac_addr)) { ptxservq = &(psta->sta_xmitpriv.be_q); /* we will use be_q to queue bc/mc frames in BCMC_stainfo */ *ppstapending = &padapter->xmitpriv.bm_pending; } else @@ -4128,11 +4334,6 @@ static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib) qsel = pattrib->priority; -#ifdef CONFIG_CONCURRENT_MODE - /* if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) - * qsel = 7; */ -#endif - #ifdef CONFIG_MCC_MODE if (MCC_EN(padapter)) { /* Under MCC */ @@ -4165,18 +4366,18 @@ static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) { - int ret = 0; - int rtap_len; - int qos_len = 0; - int dot11_hdr_len = 24; - int snap_len = 6; - unsigned char *pdata; u16 frame_ctl; - unsigned char src_mac_addr[6]; - unsigned char dst_mac_addr[6]; - struct rtw_ieee80211_hdr *dot11_hdr; - struct ieee80211_radiotap_header *rtap_hdr; + struct ieee80211_radiotap_header rtap_hdr; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct pkt_file pktfile; + struct rtw_ieee80211_hdr *pwlanhdr; + struct pkt_attrib *pattrib; + struct xmit_frame *pmgntframe; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + unsigned char *pframe; + u8 dummybuf[32]; + int len = skb->len, rtap_len; if (skb) rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize); @@ -4184,11 +4385,12 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) goto fail; - rtap_hdr = (struct ieee80211_radiotap_header *)skb->data; - if (unlikely(rtap_hdr->it_version)) + _rtw_open_pktfile((_pkt *)skb, &pktfile); + _rtw_pktfile_read(&pktfile, (u8 *)(&rtap_hdr), sizeof(struct ieee80211_radiotap_header)); + rtap_len = ieee80211_get_radiotap_len((u8 *)(&rtap_hdr)); + if (unlikely(rtap_hdr.it_version)) goto fail; - rtap_len = ieee80211_get_radiotap_len(skb->data); if (unlikely(skb->len < rtap_len)) goto fail; @@ -4196,106 +4398,116 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) RTW_INFO("radiotap len (should be 14): %d\n", rtap_len); goto fail; } + _rtw_pktfile_read(&pktfile, dummybuf, rtap_len-sizeof(struct ieee80211_radiotap_header)); + len = len - rtap_len; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + rtw_udelay_os(500); + goto fail; + } - /* Skip the ratio tap header */ - skb_pull(skb, rtap_len); + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; +// _rtw_memcpy(pframe, (void *)checking, len); + _rtw_pktfile_read(&pktfile, pframe, len); - dot11_hdr = (struct rtw_ieee80211_hdr *)skb->data; - frame_ctl = le16_to_cpu(dot11_hdr->frame_ctl); - /* Check if the QoS bit is set */ + /* Check DATA/MGNT frames */ + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + frame_ctl = le16_to_cpu(pwlanhdr->frame_ctl); if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) { - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - u8 *buf = skb->data; - u32 len = skb->len; - u8 category, action; - int type = -1; - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) { - rtw_udelay_os(500); - goto fail; - } pattrib = &pmgntframe->attrib; - update_monitor_frame_attrib(padapter, pattrib); - pattrib->retry_ctrl = _FALSE; - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - - _rtw_memcpy(pframe, (void *)buf, len); - - pattrib->pktlen = len; - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - if (is_broadcast_mac_addr(pwlanhdr->addr3) || is_broadcast_mac_addr(pwlanhdr->addr1)) pattrib->rate = MGN_24M; - pmlmeext->mgnt_seq = GetSequence(pwlanhdr); - pattrib->seqnum = pmlmeext->mgnt_seq; - pmlmeext->mgnt_seq++; - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); - } else { - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - u8 *buf = skb->data; - u32 len = skb->len; - u8 category, action; - int type = -1; - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - goto fail; pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); - pattrib->retry_ctrl = _FALSE; - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + } + pattrib->retry_ctrl = _FALSE; + pattrib->pktlen = len; + pmlmeext->mgnt_seq = GetSequence(pwlanhdr); + pattrib->seqnum = pmlmeext->mgnt_seq; + pmlmeext->mgnt_seq++; + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; +fail: + rtw_endofpktfile(&pktfile); + rtw_skb_free(skb); + return 0; +} +#endif - _rtw_memcpy(pframe, (void *)buf, len); +/* + * The main transmit(tx) entry post handle + * + * Return + * 1 enqueue + * 0 success, hardware will handle this xmit frame(packet) + * <0 fail + */ +s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt) +{ +#ifdef CONFIG_AP_MODE + _irqL irqL0; +#endif + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + s32 res; - pattrib->pktlen = len; + res = update_attrib(padapter, pkt, &pxmitframe->attrib); - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; +#ifdef CONFIG_MCC_MODE + /* record data kernel TX to driver to check MCC concurrent TX */ + rtw_hal_mcc_calc_tx_bytes_from_kernel(padapter, pxmitframe->attrib.pktlen); +#endif /* CONFIG_MCC_MODE */ - pmlmeext->mgnt_seq = GetSequence(pwlanhdr); - pattrib->seqnum = pmlmeext->mgnt_seq; - pmlmeext->mgnt_seq++; +#ifdef CONFIG_WAPI_SUPPORT + if (pxmitframe->attrib.ether_type != 0x88B4) { + if (rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) { + WAPI_TRACE(WAPI_RX, "drop for key absend when tx\n"); + res = _FAIL; + } + } +#endif + if (res == _FAIL) { + /*RTW_INFO("%s-"ADPT_FMT" update attrib fail\n", __func__, ADPT_ARG(padapter));*/ +#ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__); +#endif + rtw_free_xmitframe(pxmitpriv, pxmitframe); + return -1; + } + pxmitframe->pkt = pkt; - pattrib->last_txcmdsz = pattrib->pktlen; + rtw_led_tx_control(padapter, pxmitframe->attrib.dst); - dump_mgntframe(padapter, pmgntframe); + do_queue_select(padapter, &pxmitframe->attrib); +#ifdef CONFIG_AP_MODE + _enter_critical_bh(&pxmitpriv->lock, &irqL0); + if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) { + _exit_critical_bh(&pxmitpriv->lock, &irqL0); + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue); + return 1; } + _exit_critical_bh(&pxmitpriv->lock, &irqL0); +#endif -fail: - - rtw_skb_free(skb); + /* pre_xmitframe */ + if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE) + return 1; return 0; } -#endif + /* * The main transmit(tx) entry * @@ -4306,22 +4518,20 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) */ s32 rtw_xmit(_adapter *padapter, _pkt **ppkt) { - static u32 start = 0; + static systime start = 0; static u32 drop_cnt = 0; -#ifdef CONFIG_AP_MODE - _irqL irqL0; -#endif struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct xmit_frame *pxmitframe = NULL; -#ifdef CONFIG_BR_EXT - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - void *br_port = NULL; -#endif /* CONFIG_BR_EXT */ - s32 res; DBG_COUNTER(padapter->tx_logs.core_tx); + if (IS_CH_WAITING(adapter_to_rfctl(padapter))) + return -1; + + if (rtw_linked_check(padapter) == _FALSE) + return -1; + if (start == 0) start = rtw_get_current_time(); @@ -4342,70 +4552,72 @@ s32 rtw_xmit(_adapter *padapter, _pkt **ppkt) } #ifdef CONFIG_BR_EXT + if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) { + void *br_port = NULL; -#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) - br_port = padapter->pnetdev->br_port; -#else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ - rcu_read_lock(); - br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); - rcu_read_unlock(); -#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + br_port = padapter->pnetdev->br_port; + #else + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); + #endif - if (br_port && check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) { - res = rtw_br_client_tx(padapter, ppkt); - if (res == -1) { - rtw_free_xmitframe(pxmitpriv, pxmitframe); - DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx); - return -1; + if (br_port) { + res = rtw_br_client_tx(padapter, ppkt); + if (res == -1) { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx); + return -1; + } } } - #endif /* CONFIG_BR_EXT */ - res = update_attrib(padapter, *ppkt, &pxmitframe->attrib); - -#ifdef CONFIG_MCC_MODE - /* record data kernel TX to driver to check MCC concurrent TX */ - rtw_hal_mcc_calc_tx_bytes_from_kernel(padapter, pxmitframe->attrib.pktlen); -#endif /* CONFIG_MCC_MODE */ +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + _list b2u_list; -#ifdef CONFIG_WAPI_SUPPORT - if (pxmitframe->attrib.ether_type != 0x88B4) { - if (rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) { - WAPI_TRACE(WAPI_RX, "drop for key absend when tx\n"); - res = _FAIL; - } - } -#endif - if (res == _FAIL) { - /*RTW_INFO("%s-"ADPT_FMT" update attrib fail\n", __func__, ADPT_ARG(padapter));*/ -#ifdef DBG_TX_DROP_FRAME - RTW_INFO("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__); -#endif - rtw_free_xmitframe(pxmitpriv, pxmitframe); - return -1; - } - pxmitframe->pkt = *ppkt; + res = rtw_mesh_addr_resolve(padapter, pxmitframe, *ppkt, &b2u_list); + if (res == RTW_RA_RESOLVING) + return 1; + if (res == _FAIL) + return -1; - rtw_led_control(padapter, LED_CTL_TX); + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (!rtw_is_list_empty(&b2u_list)) { + _list *list = get_next(&b2u_list); + struct xmit_frame *b2uframe; + + while ((rtw_end_of_queue_search(&b2u_list, list)) == _FALSE) { + b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&b2uframe->list); + + b2uframe->pkt = rtw_os_pkt_copy(*ppkt); + if (!b2uframe->pkt) { + if (res == RTW_BMC_NO_NEED) + res = _SUCCESS; + rtw_free_xmitframe(pxmitpriv, b2uframe); + continue; + } - do_queue_select(padapter, &pxmitframe->attrib); + rtw_xmit_posthandle(padapter, b2uframe, b2uframe->pkt); + } + } + #endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */ -#ifdef CONFIG_AP_MODE - _enter_critical_bh(&pxmitpriv->lock, &irqL0); - if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) { - _exit_critical_bh(&pxmitpriv->lock, &irqL0); - DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue); - return 1; + if (res == RTW_BMC_NO_NEED) { + rtw_free_xmitframe(&padapter->xmitpriv, pxmitframe); + return 0; + } } - _exit_critical_bh(&pxmitpriv->lock, &irqL0); -#endif +#endif /* CONFIG_RTW_MESH */ - /* pre_xmitframe */ - if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE) - return 1; + pxmitframe->pkt = NULL; /* let rtw_xmit_posthandle not to free pkt inside */ + res = rtw_xmit_posthandle(padapter, pxmitframe, *ppkt); - return 0; + return res; } #ifdef CONFIG_TDLS @@ -4465,7 +4677,7 @@ sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_fra /* Transmit TDLS PTI via AP */ if (ptdls_sta->sleepq_len == 1) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ISSUE_PTI); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ISSUE_PTI); ret = _TRUE; } @@ -4488,32 +4700,31 @@ inline bool xmitframe_hiq_filter(struct xmit_frame *xmitframe) _adapter *adapter = xmitframe->padapter; struct registry_priv *registry = &adapter->registrypriv; - if (rtw_get_intf_type(adapter) != RTW_PCIE) { - - if (adapter->registrypriv.wifi_spec == 1) - allow = _TRUE; - else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) { + if (adapter->registrypriv.wifi_spec == 1) + allow = _TRUE; + else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) { - struct pkt_attrib *attrib = &xmitframe->attrib; + struct pkt_attrib *attrib = &xmitframe->attrib; - if (attrib->ether_type == 0x0806 - || attrib->ether_type == 0x888e + if (attrib->ether_type == 0x0806 + || attrib->ether_type == 0x888e #ifdef CONFIG_WAPI_SUPPORT - || attrib->ether_type == 0x88B4 + || attrib->ether_type == 0x88B4 #endif - || attrib->dhcp_pkt - ) { - if (0) - RTW_INFO(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter) - , attrib->ether_type, attrib->dhcp_pkt ? " DHCP" : ""); - allow = _TRUE; - } - } else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_ALL) + || attrib->dhcp_pkt + ) { + if (0) + RTW_INFO(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter) + , attrib->ether_type, attrib->dhcp_pkt ? " DHCP" : ""); allow = _TRUE; - else if (registry->hiq_filter == RTW_HIQ_FILTER_DENY_ALL) { - } else - rtw_warn_on(1); - } + } + } else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_ALL) + allow = _TRUE; + else if (registry->hiq_filter == RTW_HIQ_FILTER_DENY_ALL) + allow = _FALSE; + else + rtw_warn_on(1); + return allow; } @@ -4535,7 +4746,7 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p ret = xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pxmitframe); #endif /* CONFIG_TDLS */ - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _FALSE) { + if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) { DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_fwstate); return ret; } @@ -4584,7 +4795,7 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p if (bmcst) { _enter_critical_bh(&psta->sleep_q.lock, &irqL); - if (pstapriv->sta_dz_bitmap) { /* if anyone sta is in ps mode */ + if (rtw_tim_map_anyone_be_set(padapter, pstapriv->sta_dz_bitmap)) { /* if anyone sta is in ps mode */ /* pattrib->qsel = QSLT_HIGH; */ /* HIQ */ rtw_list_delete(&pxmitframe->list); @@ -4595,13 +4806,14 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p psta->sleepq_len++; - if (!(pstapriv->tim_bitmap & BIT(0))) + if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0))) update_tim = _TRUE; - pstapriv->tim_bitmap |= BIT(0); - pstapriv->sta_dz_bitmap |= BIT(0); + rtw_tim_map_set(padapter, pstapriv->tim_bitmap, 0); + rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, 0); - /* RTW_INFO("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); */ + /* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */ + /* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ if (update_tim == _TRUE) { if (is_broadcast_mac_addr(pattrib->ra)) _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer BC"); @@ -4615,7 +4827,6 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p ret = _TRUE; DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_mcast); - } _exit_critical_bh(&psta->sleep_q.lock, &irqL); @@ -4630,7 +4841,7 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p if (psta->state & WIFI_SLEEP_STATE) { u8 wmmps_ac = 0; - if (pstapriv->sta_dz_bitmap & BIT(psta->aid)) { + if (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid)) { rtw_list_delete(&pxmitframe->list); /* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */ @@ -4663,12 +4874,13 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p psta->sleepq_ac_len++; if (((psta->has_legacy_ac) && (!wmmps_ac)) || ((!psta->has_legacy_ac) && (wmmps_ac))) { - if (!(pstapriv->tim_bitmap & BIT(psta->aid))) + if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid))) update_tim = _TRUE; - pstapriv->tim_bitmap |= BIT(psta->aid); + rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid); - /* RTW_INFO("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); */ + /* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */ + /* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ if (update_tim == _TRUE) { /* RTW_INFO("sleepq_len==1, update BCNTIM\n"); */ @@ -4755,22 +4967,14 @@ void stop_sta_xmit(_adapter *padapter, struct sta_info *psta) #ifdef CONFIG_TDLS if (!(psta->tdls_sta_state & TDLS_LINKED_STATE)) #endif /* CONFIG_TDLS */ - pstapriv->sta_dz_bitmap |= BIT(psta->aid); - - + rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid); dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); - - dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vi_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); - - dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->be_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); - - dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->bk_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); @@ -4778,12 +4982,16 @@ void stop_sta_xmit(_adapter *padapter, struct sta_info *psta) if (!(psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta_bmc != NULL)) { #endif /* CONFIG_TDLS */ - /* for BC/MC Frames */ pstaxmitpriv = &psta_bmc->sta_xmitpriv; + dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vo_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); + dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vi_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->be_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); - + dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->bk_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); #ifdef CONFIG_TDLS } @@ -4882,14 +5090,15 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) } #endif /* CONFIG_TDLS */ - if (pstapriv->tim_bitmap & BIT(psta->aid)) { - /* RTW_INFO("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); */ + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) { + /* RTW_INFO("wakeup to xmit, qlen==0\n"); */ + /* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ /* upate BCN for TIM IE */ /* update_BCNTIM(padapter); */ update_mask = BIT(0); } - pstapriv->tim_bitmap &= ~BIT(psta->aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); if (psta->state & WIFI_SLEEP_STATE) psta->state ^= WIFI_SLEEP_STATE; @@ -4900,14 +5109,14 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) psta->state ^= WIFI_STA_ALIVE_CHK_STATE; } - pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); + rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid); } /* for BC/MC Frames */ if (!psta_bmc) goto _exit; - if ((pstapriv->sta_dz_bitmap & 0xfffe) == 0x0) { /* no any sta in ps mode */ + if (!(rtw_tim_map_anyone_be_set_exclude_aid0(padapter, pstapriv->sta_dz_bitmap))) { /* no any sta in ps mode */ xmitframe_phead = get_list_head(&psta_bmc->sleep_q); xmitframe_plist = get_next(xmitframe_phead); @@ -4940,14 +5149,15 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) } if (psta_bmc->sleepq_len == 0) { - if (pstapriv->tim_bitmap & BIT(0)) { - /* RTW_INFO("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); */ + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) { + /* RTW_INFO("wakeup to xmit, qlen==0\n"); */ + /* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ /* upate BCN for TIM IE */ /* update_BCNTIM(padapter); */ update_mask |= BIT(1); } - pstapriv->tim_bitmap &= ~BIT(0); - pstapriv->sta_dz_bitmap &= ~BIT(0); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0); + rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0); } } @@ -5036,9 +5246,10 @@ void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta) goto exit; } #endif /* CONFIG_TDLS */ - pstapriv->tim_bitmap &= ~BIT(psta->aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); - /* RTW_INFO("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); */ + /* RTW_INFO("wakeup to xmit, qlen==0\n"); */ + /* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ /* upate BCN for TIM IE */ /* update_BCNTIM(padapter); */ update_beacon(padapter, _TIM_IE_, NULL, _TRUE); @@ -5118,60 +5329,6 @@ struct xmit_buf *dequeue_pending_xmitbuf( return pxmitbuf; } -static struct xmit_buf *dequeue_pending_xmitbuf_under_survey( - struct xmit_priv *pxmitpriv) -{ - _irqL irql; - struct xmit_buf *pxmitbuf; -#ifdef CONFIG_USB_HCI - struct xmit_frame *pxmitframe; -#endif - _queue *pqueue; - - - pxmitbuf = NULL; - pqueue = &pxmitpriv->pending_xmitbuf_queue; - - _enter_critical_bh(&pqueue->lock, &irql); - - if (_rtw_queue_empty(pqueue) == _FALSE) { - _list *plist, *phead; - u8 type = 0; - - phead = get_list_head(pqueue); - plist = phead; - do { - plist = get_next(plist); - if (plist == phead) - break; - - pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); - -#ifdef CONFIG_USB_HCI - pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; - if (pxmitframe) - type = get_frame_sub_type(pxmitbuf->pbuf + TXDESC_SIZE + pxmitframe->pkt_offset * PACKET_OFFSET_SZ); - else - RTW_INFO("%s, !!!ERROR!!! For USB, TODO ITEM\n", __FUNCTION__); -#else - type = get_frame_sub_type(pxmitbuf->pbuf + TXDESC_OFFSET); -#endif - - if ((type == WIFI_PROBEREQ) || - (type == WIFI_DATA_NULL) || - (type == WIFI_QOS_DATA_NULL)) { - rtw_list_delete(&pxmitbuf->list); - break; - } - pxmitbuf = NULL; - } while (1); - } - - _exit_critical_bh(&pqueue->lock, &irql); - - return pxmitbuf; -} - static struct xmit_buf *dequeue_pending_xmitbuf_ext( struct xmit_priv *pxmitpriv) { @@ -5218,13 +5375,9 @@ struct xmit_buf *select_and_dequeue_pending_xmitbuf(_adapter *padapter) if (_TRUE == rtw_is_xmit_blocked(padapter)) return pxmitbuf; - if (rtw_xmit_ac_blocked(padapter) == _TRUE) - pxmitbuf = dequeue_pending_xmitbuf_under_survey(pxmitpriv); - else { - pxmitbuf = dequeue_pending_xmitbuf_ext(pxmitpriv); - if (pxmitbuf == NULL) - pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv); - } + pxmitbuf = dequeue_pending_xmitbuf_ext(pxmitpriv); + if (pxmitbuf == NULL && rtw_xmit_ac_blocked(padapter) != _TRUE) + pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv); return pxmitbuf; } @@ -5335,11 +5488,25 @@ bool rtw_is_xmit_blocked(_adapter *padapter) bool rtw_xmit_ac_blocked(_adapter *adapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); _adapter *iface; struct mlme_ext_priv *mlmeext; struct mlme_ext_info *mlmeextinfo; bool blocked = _FALSE; int i; +#ifdef DBG_CONFIG_ERROR_DETECT +#ifdef DBG_CONFIG_ERROR_RESET +#ifdef CONFIG_USB_HCI + if (rtw_hal_sreset_inprogress(adapter) == _TRUE) { + blocked = _TRUE; + goto exit; + } +#endif/* #ifdef CONFIG_USB_HCI */ +#endif/* #ifdef DBG_CONFIG_ERROR_RESET */ +#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */ + + if (rfctl->offch_state != OFFCHS_NONE) + blocked = _TRUE; for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -5529,6 +5696,55 @@ void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority) } #endif /* CONFIG_TX_AMSDU */ +#ifdef DBG_TXBD_DESC_DUMP +static struct rtw_tx_desc_backup tx_backup[HW_QUEUE_ENTRY][TX_BAK_FRMAE_CNT]; +static u8 backup_idx[HW_QUEUE_ENTRY]; + +void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq) +{ + u16 reg_rp; + u16 reg_wp; + u32 tmp32; + u8 *pxmit_buf; + + if (rtw_get_hw_init_completed(padapter) == _FALSE) + return; + + pxmit_buf = pxmitframe->pxmitbuf->pbuf; + + _rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_desc, pxmit_buf, desc_size); + _rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_data_hdr, pxmit_buf+desc_size, TX_BAK_DATA_LEN); + + tmp32 = rtw_read32(padapter, get_txbd_rw_reg(hwq)); + + tx_backup[hwq][backup_idx[hwq]].tx_bak_rp = (tmp32>>16)&0xfff; + tx_backup[hwq][backup_idx[hwq]].tx_bak_wp = tmp32&0xfff; + + tx_backup[hwq][backup_idx[hwq]].tx_desc_size = desc_size; + + backup_idx[hwq] = (backup_idx[hwq] + 1) % TX_BAK_FRMAE_CNT; +} + +void rtw_tx_desc_backup_reset(void) +{ + int i, j; + + for (i = 0; i < HW_QUEUE_ENTRY; i++) { + for (j = 0; j < TX_BAK_FRMAE_CNT; j++) + _rtw_memset(&tx_backup[i][j], 0, sizeof(struct rtw_tx_desc_backup)); + + backup_idx[i] = 0; + } +} + +u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak) +{ + *pbak = &tx_backup[hwq][0]; + + return backup_idx[hwq]; +} +#endif + void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms) { sctx->timeout_ms = timeout_ms; diff --git a/hal/HalPwrSeqCmd.c b/hal/HalPwrSeqCmd.c index 6a2f9a6..389785c 100644 --- a/hal/HalPwrSeqCmd.c +++ b/hal/HalPwrSeqCmd.c @@ -49,9 +49,11 @@ u8 HalPwrSeqCmdParsing( { WLAN_PWR_CFG PwrCfgCmd = {0}; u8 bPollingBit = _FALSE; + u8 bHWICSupport = _FALSE; u32 AryIdx = 0; u8 value = 0; u32 offset = 0; + u8 flag = 0; u32 pollingCount = 0; /* polling autoload done. */ u32 maxPollingCnt = 5000; @@ -106,6 +108,14 @@ u8 HalPwrSeqCmdParsing( bPollingBit = _FALSE; offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); + + rtw_hal_get_hwreg(padapter, HW_VAR_PWR_CMD, &bHWICSupport); + if (bHWICSupport && offset == 0x06) { + flag = 0; + maxPollingCnt = 100000; + } else + maxPollingCnt = 5000; + #ifdef CONFIG_GSPI_HCI if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) offset = SPI_LOCAL_OFFSET | offset; @@ -126,7 +136,26 @@ u8 HalPwrSeqCmdParsing( if (pollingCount++ > maxPollingCnt) { RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value); - return _FALSE; + + /* For PCIE + USB package poll power bit timeout issue only modify 8821AE and 8723BE */ + if (bHWICSupport && offset == 0x06 && flag == 0) { + + RTW_ERR("[WARNING] PCIE polling(0x%X) timeout(%d), Toggle 0x04[3] and try again.\n", offset, maxPollingCnt); + if (IS_HARDWARE_TYPE_8723DE(padapter)) + PlatformEFIOWrite1Byte(padapter, 0x40, (PlatformEFIORead1Byte(padapter, 0x40)) & (~BIT3)); + + PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) | BIT3); + PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) & ~BIT3); + + if (IS_HARDWARE_TYPE_8723DE(padapter)) + PlatformEFIOWrite1Byte(padapter, 0x40, PlatformEFIORead1Byte(padapter, 0x40)|BIT3); + + /* Retry Polling Process one more time */ + pollingCount = 0; + flag = 1; + } else { + return _FALSE; + } } } while (!bPollingBit); diff --git a/hal/btc/HalBtc8188c2Ant.c b/hal/btc/HalBtc8188c2Ant.c deleted file mode 100644 index 59c2d4c..0000000 --- a/hal/btc/HalBtc8188c2Ant.c +++ /dev/null @@ -1,1987 +0,0 @@ -//============================================================ -// Description: -// -// This file is for 92CE/92CU BT 1 Antenna Co-exist mechanism -// -// By cosa 02/11/2011 -// -//============================================================ - -//============================================================ -// include files -//============================================================ -#include "Mp_Precomp.h" - -#if WPP_SOFTWARE_TRACE -#include "HalBtc8188c2Ant.tmh" -#endif - -#if(BT_30_SUPPORT == 1) -//============================================================ -// Global variables, these are static variables -//============================================================ -static COEX_DM_8188C_2ANT GLCoexDm8188c2Ant; -static PCOEX_DM_8188C_2ANT pCoexDm=&GLCoexDm8188c2Ant; -static COEX_STA_8188C_2ANT GLCoexSta8188c2Ant; -static PCOEX_STA_8188C_2ANT pCoexSta=&GLCoexSta8188c2Ant; - -//============================================================ -// local function start with btdm_ -//============================================================ -u1Byte -halbtc8188c2ant_WifiRssiState( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte index, - IN u1Byte levelNum, - IN u1Byte rssiThresh, - IN u1Byte rssiThresh1 - ) -{ - s4Byte wifiRssi=0; - u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); - - if(levelNum == 2) - { - if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || - (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) - { - if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT)) - { - wifiRssiState = BTC_RSSI_STATE_HIGH; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_LOW; - } - } - else - { - if(wifiRssi < rssiThresh) - { - wifiRssiState = BTC_RSSI_STATE_LOW; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; - } - } - } - else if(levelNum == 3) - { - if(rssiThresh > rssiThresh1) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); - return pCoexSta->preWifiRssiState[index]; - } - - if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || - (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) - { - if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT)) - { - wifiRssiState = BTC_RSSI_STATE_MEDIUM; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_LOW; - } - } - else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || - (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) - { - if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT)) - { - wifiRssiState = BTC_RSSI_STATE_HIGH; - } - else if(wifiRssi < rssiThresh) - { - wifiRssiState = BTC_RSSI_STATE_LOW; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; - } - } - else - { - if(wifiRssi < rssiThresh1) - { - wifiRssiState = BTC_RSSI_STATE_MEDIUM; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; - } - } - } - - pCoexSta->preWifiRssiState[index] = wifiRssiState; - - return wifiRssiState; -} - -u1Byte -halbtc8188c2ant_ActionAlgorithm( - IN PBTC_COEXIST pBtCoexist - ) -{ - PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; - u1Byte algorithm=BT_8188C_2ANT_COEX_ALGO_UNDEFINED; - u1Byte numOfDiffProfile=0; - - if(!pStackInfo->bBtLinkExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No profile exists!!!\n")); - return algorithm; - } - - if(pStackInfo->bScoExist) - numOfDiffProfile++; - if(pStackInfo->bHidExist) - numOfDiffProfile++; - if(pStackInfo->bPanExist) - numOfDiffProfile++; - if(pStackInfo->bA2dpExist) - numOfDiffProfile++; - - if(pStackInfo->bScoExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO algorithm\n")); - algorithm = BT_8188C_2ANT_COEX_ALGO_SCO; - } - else - { - if(numOfDiffProfile == 1) - { - if(pStackInfo->bHidExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n")); - algorithm = BT_8188C_2ANT_COEX_ALGO_HID; - } - else if(pStackInfo->bA2dpExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n")); - algorithm = BT_8188C_2ANT_COEX_ALGO_A2DP; - } - else if(pStackInfo->bPanExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN only\n")); - algorithm = BT_8188C_2ANT_COEX_ALGO_PAN; - } - } - else - { - if( pStackInfo->bHidExist && - pStackInfo->bA2dpExist ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n")); - algorithm = BT_8188C_2ANT_COEX_ALGO_HID_A2DP; - } - else if( pStackInfo->bHidExist && - pStackInfo->bPanExist ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN\n")); - algorithm = BT_8188C_2ANT_COEX_ALGO_HID_PAN; - } - else if( pStackInfo->bPanExist && - pStackInfo->bA2dpExist ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN + A2DP\n")); - algorithm = BT_8188C_2ANT_COEX_ALGO_PAN_A2DP; - } - } - } - return algorithm; -} - -VOID -halbtc8188c2ant_SetFwBalance( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bBalanceOn, - IN u1Byte ms0, - IN u1Byte ms1 - ) -{ - u1Byte H2C_Parameter[3] ={0}; - - if(bBalanceOn) - { - H2C_Parameter[2] = 1; - H2C_Parameter[1] = ms1; - H2C_Parameter[0] = ms0; - } - else - { - H2C_Parameter[2] = 0; - H2C_Parameter[1] = 0; - H2C_Parameter[0] = 0; - } - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Balance=[%s:%dms:%dms], write 0xc=0x%x\n", - bBalanceOn?"ON":"OFF", ms0, ms1, - H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); - - pBtCoexist->fBtcFillH2c(pBtCoexist, 0xc, 3, H2C_Parameter); -} - -VOID -halbtc8188c2ant_Balance( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bBalanceOn, - IN u1Byte ms0, - IN u1Byte ms1 - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Balance %s\n", - (bForceExec? "force to":""), (bBalanceOn? "ON":"OFF"))); - pCoexDm->bCurBalanceOn = bBalanceOn; - - if(!bForceExec) - { - if(pCoexDm->bPreBalanceOn == pCoexDm->bCurBalanceOn) - return; - } - halbtc8188c2ant_SetFwBalance(pBtCoexist, bBalanceOn, ms0, ms1); - - pCoexDm->bPreBalanceOn = pCoexDm->bCurBalanceOn; -} - -VOID -halbtc8188c2ant_SetFwDiminishWifi( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bDacOn, - IN BOOLEAN bInterruptOn, - IN u1Byte fwDacSwingLvl, - IN BOOLEAN bNavOn - ) -{ - u1Byte H2C_Parameter[3] ={0}; - - if((pBtCoexist->stackInfo.minBtRssi <= -5) && (fwDacSwingLvl == 0x20)) - { - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], DiminishWiFi 0x20 original, but set 0x18 for Low RSSI!\n")); - fwDacSwingLvl = 0x18; - } - - H2C_Parameter[2] = 0; - H2C_Parameter[1] = fwDacSwingLvl; - H2C_Parameter[0] = 0; - if(bDacOn) - { - H2C_Parameter[2] |= 0x01; //BIT0 - if(bInterruptOn) - { - H2C_Parameter[2] |= 0x02; //BIT1 - } - } - if(bNavOn) - { - H2C_Parameter[2] |= 0x08; //BIT3 - } - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bDacOn=%s, bInterruptOn=%s, bNavOn=%s, write 0xe=0x%x\n", - (bDacOn?"ON":"OFF"), (bInterruptOn?"ON":"OFF"), (bNavOn?"ON":"OFF"), - (H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2]))); - pBtCoexist->fBtcFillH2c(pBtCoexist, 0xe, 3, H2C_Parameter); -} - -VOID -halbtc8188c2ant_DiminishWifi( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bDacOn, - IN BOOLEAN bInterruptOn, - IN u1Byte fwDacSwingLvl, - IN BOOLEAN bNavOn - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set Diminish Wifi, bDacOn=%s, bInterruptOn=%s, fwDacSwingLvl=%d, bNavOn=%s\n", - (bForceExec? "force to":""), (bDacOn? "ON":"OFF"), (bInterruptOn? "ON":"OFF"), fwDacSwingLvl, (bNavOn? "ON":"OFF"))); - - pCoexDm->bCurDacOn = bDacOn; - pCoexDm->bCurInterruptOn = bInterruptOn; - pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; - pCoexDm->bCurNavOn = bNavOn; - - if(!bForceExec) - { - if( (pCoexDm->bPreDacOn==pCoexDm->bCurDacOn) && - (pCoexDm->bPreInterruptOn==pCoexDm->bCurInterruptOn) && - (pCoexDm->preFwDacSwingLvl==pCoexDm->curFwDacSwingLvl) && - (pCoexDm->bPreNavOn==pCoexDm->bCurNavOn) ) - return; - } - halbtc8188c2ant_SetFwDiminishWifi(pBtCoexist, bDacOn, bInterruptOn, fwDacSwingLvl, bNavOn); - - pCoexDm->bPreDacOn = pCoexDm->bCurDacOn; - pCoexDm->bPreInterruptOn = pCoexDm->bCurInterruptOn; - pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; - pCoexDm->bPreNavOn = pCoexDm->bCurNavOn; -} - -VOID -halbtc8188c2ant_SetSwRfRxLpfCorner( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bRxRfShrinkOn - ) -{ - if(bRxRfShrinkOn) - { - //Shrink RF Rx LPF corner - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xf0, 0xf); - } - else - { - //Resume RF Rx LPF corner - // After initialized, we can use pCoexDm->btRf0x1eBackup - if(pBtCoexist->bInitilized) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xf0, pCoexDm->btRf0x1eBackup); - } - } -} - -VOID -halbtc8188c2ant_RfShrink( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bRxRfShrinkOn - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", - (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); - pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; - - if(!bForceExec) - { - if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) - return; - } - halbtc8188c2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); - - pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; -} - -VOID -halbtc8188c2ant_SetSwPenaltyTxRateAdaptive( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bLowPenaltyRa - ) -{ - u1Byte tmpU1; - - tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd); - if(bLowPenaltyRa) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n")); - tmpU1 &= ~BIT2; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n")); - tmpU1 |= BIT2; - } - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1); -} - -VOID -halbtc8188c2ant_LowPenaltyRa( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bLowPenaltyRa - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", - (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); - pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; - - if(!bForceExec) - { - if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) - return; - } - halbtc8188c2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); - - pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; -} - -VOID -halbtc8188c2ant_SetSwFullTimeDacSwing( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bSwDacSwingOn, - IN u4Byte swDacSwingLvl - ) -{ - u4Byte dacSwingLvl; - - if(bSwDacSwingOn) - { - if((pBtCoexist->stackInfo.minBtRssi <= -5) && (swDacSwingLvl == 0x20)) - { - dacSwingLvl = 0x18; - } - else - { - dacSwingLvl = swDacSwingLvl; - } - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, dacSwingLvl); - } - else - { - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, 0x30); - } -} - -VOID -halbtc8188c2ant_DacSwing( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bDacSwingOn, - IN u4Byte dacSwingLvl - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n", - (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl)); - pCoexDm->bCurDacSwingOn = bDacSwingOn; - pCoexDm->curDacSwingLvl = dacSwingLvl; - - if(!bForceExec) - { - if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && - (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) ) - return; - } - delay_ms(30); - halbtc8188c2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); - - pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; - pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; -} - -VOID -halbtc8188c2ant_SetAdcBackOff( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bAdcBackOff - ) -{ - if(bAdcBackOff) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n")); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a07611); - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n")); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a05611); - } -} - -VOID -halbtc8188c2ant_AdcBackOff( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bAdcBackOff - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n", - (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF"))); - pCoexDm->bCurAdcBackOff = bAdcBackOff; - - if(!bForceExec) - { - if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff) - return; - } - halbtc8188c2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff); - - pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff; -} - -VOID -halbtc8188c2ant_SetAgcTable( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bAgcTableEn - ) -{ - u1Byte rssiAdjustVal=0; - - if(bAgcTableEn) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4e1c0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4d1d0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4c1e0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4b1f0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4a200001); - - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xdc000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x90000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x51000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x12000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x00255); - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x641c0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x631d0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x621e0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x611f0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x60200001); - - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x32000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x71000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xb0000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xfc000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x10255); - } - - // set rssiAdjustVal for wifi module. - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); -} - - -VOID -halbtc8188c2ant_AgcTable( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bAgcTableEn - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n", - (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable"))); - pCoexDm->bCurAgcTableEn = bAgcTableEn; - - if(!bForceExec) - { - if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) - return; - } - halbtc8188c2ant_SetAgcTable(pBtCoexist, bAgcTableEn); - - pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; -} - -VOID -halbtc8188c2ant_SetCoexTable( - IN PBTC_COEXIST pBtCoexist, - IN u4Byte val0x6c4, - IN u4Byte val0x6c8, - IN u4Byte val0x6cc - ) -{ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6cc, val0x6cc); -} - -VOID -halbtc8188c2ant_CoexTable( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN u4Byte val0x6c4, - IN u4Byte val0x6c8, - IN u4Byte val0x6cc - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", - (bForceExec? "force to":""), val0x6c4, val0x6c8, val0x6cc)); - pCoexDm->curVal0x6c4 = val0x6c4; - pCoexDm->curVal0x6c8 = val0x6c8; - pCoexDm->curVal0x6cc = val0x6cc; - - if(!bForceExec) - { - if( (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && - (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && - (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) - return; - } - halbtc8188c2ant_SetCoexTable(pBtCoexist, val0x6c4, val0x6c8, val0x6cc); - - pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; - pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; - pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; -} - -VOID -halbtc8188c2ant_CoexAllOff( - IN PBTC_COEXIST pBtCoexist - ) -{ - // fw mechanism - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); -} -VOID -halbtc8188c2ant_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ) -{ -} - - -VOID -halbtc8188c2ant_MonitorBtState( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN stateChange=FALSE; - u4Byte BT_Polling, Ratio_Act, Ratio_STA; - u4Byte BT_Active, BT_State; - u4Byte regBTActive=0, regBTState=0, regBTPolling=0; - u4Byte btBusyThresh=0; - u4Byte fwVer=0; - static BOOLEAN bBtBusyTraffic=FALSE; - BOOLEAN bRejApAggPkt=FALSE; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FirmwareVersion = 0x%x(%d)\n", fwVer, fwVer)); - if(fwVer < 62) - { - regBTActive = 0x488; - regBTState = 0x48c; - regBTPolling = 0x490; - } - else - { - regBTActive = 0x444; - regBTState = 0x448; - if(fwVer >= 74) - regBTPolling = 0x44c; - else - regBTPolling = 0x700; - } - btBusyThresh = 60; - - BT_Active = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTActive); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Active(0x%x)=0x%x\n", regBTActive, BT_Active)); - BT_Active = BT_Active & 0x00ffffff; - - BT_State = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTState); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_State(0x%x)=0x%x\n", regBTState, BT_State)); - BT_State = BT_State & 0x00ffffff; - - BT_Polling = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTPolling); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Polling(0x%x)=0x%x\n", regBTPolling, BT_Polling)); - - if(BT_Active==0xffffffff && BT_State==0xffffffff && BT_Polling==0xffffffff ) - return; - - // 2011/05/04 MH For Slim combo test meet a problem. Surprise remove and WLAN is running - // DHCP process. At the same time, the register read value might be zero. And cause BSOD 0x7f - // EXCEPTION_DIVIDED_BY_ZERO. In This case, the stack content may always be wrong due to - // HW divide trap. - if (BT_Polling==0) - return; - - Ratio_Act = BT_Active*1000/BT_Polling; - Ratio_STA = BT_State*1000/BT_Polling; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_Act=%d\n", Ratio_Act)); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_STA=%d\n", Ratio_STA)); - - if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - if(Ratio_STA < 60) // BT PAN idle - { - } - else - { - // Check if BT PAN (under BT 2.1) is uplink or downlink - if((Ratio_Act/Ratio_STA) < 2) - { // BT PAN Uplink - pCoexSta->bBtUplink = TRUE; - } - else - { // BT PAN downlink - pCoexSta->bBtUplink = FALSE; - } - } - } - - // Check BT is idle or not - if(!pBtCoexist->stackInfo.bBtLinkExist) - { - pCoexSta->bBtBusy = FALSE; - } - else - { - if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) - { - if(Ratio_Act<20) - { - pCoexSta->bBtBusy = FALSE; - } - else - { - pCoexSta->bBtBusy = TRUE; - } - } - else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - if(Ratio_STA < btBusyThresh) - { - pCoexSta->bBtBusy = FALSE; - } - else - { - pCoexSta->bBtBusy = TRUE; - } - - if( (Ratio_STA < btBusyThresh) || - (Ratio_Act<180 && Ratio_STA<130) ) - { - pCoexSta->bA2dpBusy = FALSE; - } - else - { - pCoexSta->bA2dpBusy = TRUE; - } - } - } - - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &pCoexSta->bBtBusy); - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &pCoexSta->bBtBusy); - - if(bBtBusyTraffic != pCoexSta->bBtBusy) - { // BT idle or BT non-idle - bBtBusyTraffic = pCoexSta->bBtBusy; - stateChange = TRUE; - } - - if(stateChange) - { - if(!pCoexSta->bBtBusy) - { - halbtc8188c2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_CoexAllOff(pBtCoexist); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - } - else - { - halbtc8188c2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); - } - } - - if(stateChange) - { - bRejApAggPkt = pCoexSta->bBtBusy; - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejApAggPkt); - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - } -} - -VOID -halbtc8188c2ant_ActionA2dpBc4( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState; - u4Byte wifiBw, wifiTrafficDir; - - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); - - if(pCoexSta->bBtBusy) - { - if(BTC_WIFI_BW_HT40 == wifiBw) - { - // fw mechanism first - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x20, FALSE); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - } - - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); - } - else - { - wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); - - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x20, FALSE); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - } - - // sw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); - } - else - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); - } - } - } - else - { - halbtc8188c2ant_CoexAllOff(pBtCoexist); - } -} - -VOID -halbtc8188c2ant_ActionA2dpBc8( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState; - u4Byte wifiBw, wifiTrafficDir; - BOOLEAN bWifiBusy=FALSE; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - if(pCoexSta->bA2dpBusy && bWifiBusy) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); - wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); - - // fw mechanism first - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x18); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - - // sw mechanism - if(BTC_WIFI_BW_HT40 == wifiBw) - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - } - else if(pCoexSta->bA2dpBusy) - { - // fw mechanism first - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, TRUE, 0x18, FALSE); - - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8188c2ant_CoexAllOff(pBtCoexist); - } -} - -VOID -halbtc8188c2ant_ActionA2dp( - IN PBTC_COEXIST pBtCoexist - ) -{ - if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) - { - halbtc8188c2ant_ActionA2dpBc4(pBtCoexist); - } - else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - halbtc8188c2ant_ActionA2dpBc8(pBtCoexist); - } -} - -VOID -halbtc8188c2ant_ActionPanBc4( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - if(bBtHsOn) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - } - else - { - if(pCoexSta->bBtBusy && bWifiBusy) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - } - } - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); -} - -VOID -halbtc8188c2ant_ActionPanBc8( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; - u1Byte wifiRssiState; - u4Byte wifiBw, wifiTrafficDir; - s4Byte wifiRssi; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); - - if(bBtHsOn) - { - halbtc8188c2ant_CoexAllOff(pBtCoexist); - } - else - { - wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 3, 25, 50); - - if(pCoexSta->bBtBusy && bWifiBusy) - { - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - // fw mechanism first - if(pCoexSta->bBtUplink) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - } - // sw mechanism - if(BTC_WIFI_BW_HT40 == wifiBw) - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - } - else - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - } - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - if(pCoexSta->bBtUplink) - { - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); - } - } - else if( (wifiRssiState == BTC_RSSI_STATE_MEDIUM) || - (wifiRssiState == BTC_RSSI_STATE_STAY_MEDIUM) ) - { - // fw mechanism first - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20); - - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - if(BTC_WIFI_BW_HT40 == wifiBw) - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON); - else - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - // sw mechanism - if(BTC_WIFI_BW_HT40 == wifiBw) - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - } - else - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - } - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - // fw mechanism first - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20); - - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - if(pCoexSta->bBtUplink) - { - if(BTC_WIFI_BW_HT40 == wifiBw) - { - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON); - } - else - { - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - } - else - { - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - } - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - else if(pCoexSta->bBtBusy && !bWifiBusy && (wifiRssi < 30)) - { - // fw mechanism first - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x0a, 0x20); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8188c2ant_CoexAllOff(pBtCoexist); - } - } -} - -VOID -halbtc8188c2ant_ActionPan( - IN PBTC_COEXIST pBtCoexist - ) -{ - if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) - { - halbtc8188c2ant_ActionPanBc4(pBtCoexist); - } - else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - halbtc8188c2ant_ActionPanBc8(pBtCoexist); - } -} - -VOID -halbtc8188c2ant_ActionHid( - IN PBTC_COEXIST pBtCoexist - ) -{ - u4Byte wifiBw, wifiTrafficDir; - BOOLEAN bWifiBusy=FALSE; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); - if(BTC_WIFI_BW_LEGACY == wifiBw) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - - halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); - } - else if(!bWifiBusy) - { - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - } - else if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - - halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - } - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); -} - - -VOID -halbtc8188c2ant_ActionSco( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState; - u4Byte wifiBw; - - if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) - { - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - - // fw mechanism - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - // fw mechanism first - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); - // fw mechanism first - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - } -} - -VOID -halbtc8188c2ant_ActionHidA2dpBc4( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState; - u4Byte wifiBw, wifiTrafficDir; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); - - if(pCoexSta->bBtBusy) - { - if(BTC_WIFI_BW_HT40 == wifiBw) - { - // fw mechanism first - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x7, 0x20); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x20, FALSE); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - } - - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - else - { - wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); - // fw mechanism first - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x7, 0x20); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x20, FALSE); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - } - - // sw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - else - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - } - } - else - { - halbtc8188c2ant_CoexAllOff(pBtCoexist); - } -} -VOID -halbtc8188c2ant_ActionHidA2dpBc8( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState; - u4Byte wifiBw; - - if(pCoexSta->bBtBusy) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - // fw mechanism first - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - else - { - wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); - // fw mechanism - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - else - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - } - } - else - { - halbtc8188c2ant_CoexAllOff(pBtCoexist); - } -} - -VOID -halbtc8188c2ant_ActionHidA2dp( - IN PBTC_COEXIST pBtCoexist - ) -{ - if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) - { - halbtc8188c2ant_ActionHidA2dpBc4(pBtCoexist); - } - else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - halbtc8188c2ant_ActionHidA2dpBc8(pBtCoexist); - } -} - -VOID -halbtc8188c2ant_ActionHidPanBc4( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; - u4Byte wifiBw, wifiTrafficDir; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - - if(bBtHsOn) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - - halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); - } - else - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); - if(BTC_WIFI_BW_LEGACY == wifiBw) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - - halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); - } - else if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - - halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else if(!bWifiBusy) - { - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - } - } - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); -} -VOID -halbtc8188c2ant_ActionHidPanBc8( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; - u1Byte wifiRssiState; - u4Byte wifiBw, wifiTrafficDir; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - - if(!bBtHsOn) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0); - if((pCoexSta->bBtBusy && bWifiBusy)) - { - // fw mechanism first - if(pCoexSta->bBtUplink) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20); - } - else - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20); - } - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - - // sw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - else - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - else - { - halbtc8188c2ant_CoexAllOff(pBtCoexist); - } - } - else - { - if(BTC_INTF_USB == pBtCoexist->chipInterface) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - - halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - } - else - { - if(pCoexSta->bBtBusy) - { - // fw mechanism - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); - } - else - { - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - } -} - -VOID -halbtc8188c2ant_ActionHidPan( - IN PBTC_COEXIST pBtCoexist - ) -{ - if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) - { - halbtc8188c2ant_ActionHidPanBc4(pBtCoexist); - } - else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - halbtc8188c2ant_ActionHidPanBc8(pBtCoexist); - } -} - -VOID -halbtc8188c2ant_ActionPanA2dpBc4( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; - u1Byte wifiRssiState; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - if(bBtHsOn) - { - if(pCoexSta->bBtBusy) - { - // fw mechanism - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); - } - else - { - halbtc8188c2ant_CoexAllOff(pBtCoexist); - } - } - else - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - if(pCoexSta->bBtBusy && bWifiBusy) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - } - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } -} -VOID -halbtc8188c2ant_ActionPanA2dpBc8( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; - u1Byte wifiRssiState; - u4Byte wifiBw; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - - if(!bBtHsOn) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0); - if((pCoexSta->bBtBusy && bWifiBusy)) - { - // fw mechanism first - if(pCoexSta->bBtUplink) - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20); - } - else - { - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20); - } - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - - // sw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - else - { - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - else - { - halbtc8188c2ant_CoexAllOff(pBtCoexist); - } - } - else - { - if(pCoexSta->bBtBusy) - { - // fw mechanism - halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); - } - else - { - halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } -} - -VOID -halbtc8188c2ant_ActionPanA2dp( - IN PBTC_COEXIST pBtCoexist - ) -{ - if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) - { - halbtc8188c2ant_ActionPanA2dpBc4(pBtCoexist); - } - else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - halbtc8188c2ant_ActionPanA2dpBc8(pBtCoexist); - } -} - -//============================================================ -// extern function start with EXhalbtc8188c2ant_ -//============================================================ -VOID -EXhalbtc8188c2ant_PowerOnSetting( - IN PBTC_COEXIST pBtCoexist - ) -{ -} - -VOID -EXhalbtc8188c2ant_InitHwConfig( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bWifiOnly - ) -{ - u1Byte u1Tmp=0; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n")); - - // backup rf 0x1e value - pCoexDm->btRf0x1eBackup = - pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xf0); - - if( (BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) || - (BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) ) - { - u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd) & BIT0; - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, u1Tmp); - - halbtc8188c2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0xaaaa9aaa, 0xffbd0040, 0x40000010); - } -} - -VOID -EXhalbtc8188c2ant_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ) -{ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); - - halbtc8188c2ant_InitCoexDm(pBtCoexist); -} - -VOID -EXhalbtc8188c2ant_DisplayCoexInfo( - IN PBTC_COEXIST pBtCoexist - ) -{ - PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; - PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; - pu1Byte cliBuf=pBtCoexist->cliBuf; - u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; - u4Byte u4Tmp[4]; - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ - pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); - CL_PRINTF(cliBuf); - - if(pBtCoexist->bManualControl) - { - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!"); - CL_PRINTF(cliBuf); - } - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ - ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); - CL_PRINTF(cliBuf); - - // wifi status - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); - CL_PRINTF(cliBuf); - pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); - CL_PRINTF(cliBuf); - - if(pStackInfo->bProfileNotified) - { - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ - pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist); - CL_PRINTF(cliBuf); - - pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); - } - - // Sw mechanism - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); - CL_PRINTF(cliBuf); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ - pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl); - CL_PRINTF(cliBuf); - - // Fw mechanism - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); - CL_PRINTF(cliBuf); - - // Hw setting - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ - pCoexDm->btRf0x1eBackup); - CL_PRINTF(cliBuf); - - u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \ - u1Tmp[0]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \ - u4Tmp[0]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); - u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); - u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6cc); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x6c4/0x6c8/0x6cc(coexTable)", \ - u4Tmp[0], u4Tmp[1], u4Tmp[2]); - CL_PRINTF(cliBuf); - - pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -VOID -EXhalbtc8188c2ant_IpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_IPS_ENTER == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); - halbtc8188c2ant_CoexAllOff(pBtCoexist); - } - else if(BTC_IPS_LEAVE == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); - //halbtc8188c2ant_InitCoexDm(pBtCoexist); - } -} - -VOID -EXhalbtc8188c2ant_LpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_LPS_ENABLE == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); - halbtc8188c2ant_CoexAllOff(pBtCoexist); - } - else if(BTC_LPS_DISABLE == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); - halbtc8188c2ant_InitCoexDm(pBtCoexist); - } -} - -VOID -EXhalbtc8188c2ant_ScanNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_SCAN_START == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); - } - else if(BTC_SCAN_FINISH == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); - } -} - -VOID -EXhalbtc8188c2ant_ConnectNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_ASSOCIATE_START == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); - } - else if(BTC_ASSOCIATE_FINISH == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); - } -} - -VOID -EXhalbtc8188c2ant_MediaStatusNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_MEDIA_CONNECT == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); - } - -} - -VOID -EXhalbtc8188c2ant_SpecialPacketNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(type == BTC_PACKET_DHCP) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); - } -} - -VOID -EXhalbtc8188c2ant_BtInfoNotify( - IN PBTC_COEXIST pBtCoexist, - IN pu1Byte tmpBuf, - IN u1Byte length - ) -{ -} - -VOID -EXhalbtc8188c2ant_HaltNotify( - IN PBTC_COEXIST pBtCoexist - ) -{ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); - - EXhalbtc8188c2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); -} - -VOID -EXhalbtc8188c2ant_Periodical( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte algorithm; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Periodical!!\n")); - - // NOTE: - // sw mechanism must be done after fw mechanism - // - - if((BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) || - (BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) ) - { - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_GET_BT_RSSI, NULL); - - halbtc8188c2ant_MonitorBtState(pBtCoexist); - algorithm = halbtc8188c2ant_ActionAlgorithm(pBtCoexist); - pCoexDm->curAlgorithm = algorithm; - switch(pCoexDm->curAlgorithm) - { - case BT_8188C_2ANT_COEX_ALGO_SCO: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO\n")); - halbtc8188c2ant_ActionSco(pBtCoexist); - break; - case BT_8188C_2ANT_COEX_ALGO_HID: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID\n")); - halbtc8188c2ant_ActionHid(pBtCoexist); - break; - case BT_8188C_2ANT_COEX_ALGO_A2DP: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP\n")); - halbtc8188c2ant_ActionA2dp(pBtCoexist); - break; - case BT_8188C_2ANT_COEX_ALGO_PAN: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN\n")); - halbtc8188c2ant_ActionPan(pBtCoexist); - break; - case BT_8188C_2ANT_COEX_ALGO_HID_A2DP: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP\n")); - halbtc8188c2ant_ActionHidA2dp(pBtCoexist); - break; - case BT_8188C_2ANT_COEX_ALGO_HID_PAN: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+HID\n")); - halbtc8188c2ant_ActionHidPan(pBtCoexist); - break; - case BT_8188C_2ANT_COEX_ALGO_PAN_A2DP: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP\n")); - halbtc8188c2ant_ActionPanA2dp(pBtCoexist); - break; - default: - break; - } - } -} - - -#endif - diff --git a/hal/btc/HalBtc8188c2Ant.h b/hal/btc/HalBtc8188c2Ant.h deleted file mode 100644 index e4aa715..0000000 --- a/hal/btc/HalBtc8188c2Ant.h +++ /dev/null @@ -1,149 +0,0 @@ -//=========================================== -// The following is for 8188C 2Ant BT Co-exist definition -//=========================================== -#define BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT 6 - -typedef enum _BT_INFO_SRC_8188C_2ANT{ - BT_INFO_SRC_8188C_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8188C_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8188C_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8188C_2ANT_MAX -}BT_INFO_SRC_8188C_2ANT,*PBT_INFO_SRC_8188C_2ANT; - -typedef enum _BT_8188C_2ANT_BT_STATUS{ - BT_8188C_2ANT_BT_STATUS_IDLE = 0x0, - BT_8188C_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8188C_2ANT_BT_STATUS_NON_IDLE = 0x2, - BT_8188C_2ANT_BT_STATUS_MAX -}BT_8188C_2ANT_BT_STATUS,*PBT_8188C_2ANT_BT_STATUS; - -typedef enum _BT_8188C_2ANT_COEX_ALGO{ - BT_8188C_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8188C_2ANT_COEX_ALGO_SCO = 0x1, - BT_8188C_2ANT_COEX_ALGO_HID = 0x2, - BT_8188C_2ANT_COEX_ALGO_A2DP = 0x3, - BT_8188C_2ANT_COEX_ALGO_PAN = 0x4, - BT_8188C_2ANT_COEX_ALGO_HID_A2DP = 0x5, - BT_8188C_2ANT_COEX_ALGO_HID_PAN = 0x6, - BT_8188C_2ANT_COEX_ALGO_PAN_A2DP = 0x7, - BT_8188C_2ANT_COEX_ALGO_MAX -}BT_8188C_2ANT_COEX_ALGO,*PBT_8188C_2ANT_COEX_ALGO; - -typedef struct _COEX_DM_8188C_2ANT{ - // fw mechanism - BOOLEAN bPreBalanceOn; - BOOLEAN bCurBalanceOn; - - // diminishWifi - BOOLEAN bPreDacOn; - BOOLEAN bCurDacOn; - BOOLEAN bPreInterruptOn; - BOOLEAN bCurInterruptOn; - u1Byte preFwDacSwingLvl; - u1Byte curFwDacSwingLvl; - BOOLEAN bPreNavOn; - BOOLEAN bCurNavOn; - - // sw mechanism - BOOLEAN bPreRfRxLpfShrink; - BOOLEAN bCurRfRxLpfShrink; - u4Byte btRf0x1eBackup; - BOOLEAN bPreLowPenaltyRa; - BOOLEAN bCurLowPenaltyRa; - BOOLEAN bPreDacSwingOn; - u4Byte preDacSwingLvl; - BOOLEAN bCurDacSwingOn; - u4Byte curDacSwingLvl; - BOOLEAN bPreAdcBackOff; - BOOLEAN bCurAdcBackOff; - BOOLEAN bPreAgcTableEn; - BOOLEAN bCurAgcTableEn; - //u4Byte preVal0x6c0; - //u4Byte curVal0x6c0; - u4Byte preVal0x6c4; - u4Byte curVal0x6c4; - u4Byte preVal0x6c8; - u4Byte curVal0x6c8; - u4Byte preVal0x6cc; - u4Byte curVal0x6cc; - //BOOLEAN bLimitedDig; - - // algorithm related - u1Byte preAlgorithm; - u1Byte curAlgorithm; - //u1Byte btStatus; - //u1Byte wifiChnlInfo[3]; -} COEX_DM_8188C_2ANT, *PCOEX_DM_8188C_2ANT; - -typedef struct _COEX_STA_8188C_2ANT{ - u1Byte preWifiRssiState[4]; - BOOLEAN bBtBusy; - BOOLEAN bBtUplink; - BOOLEAN bBtDownLink; - BOOLEAN bA2dpBusy; -}COEX_STA_8188C_2ANT, *PCOEX_STA_8188C_2ANT; - -//=========================================== -// The following is interface which will notify coex module. -//=========================================== -VOID -EXhalbtc8188c2ant_PowerOnSetting( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8188c2ant_InitHwConfig( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bWifiOnly - ); -VOID -EXhalbtc8188c2ant_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8188c2ant_IpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8188c2ant_LpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8188c2ant_ScanNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8188c2ant_ConnectNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8188c2ant_MediaStatusNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8188c2ant_SpecialPacketNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8188c2ant_HaltNotify( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8188c2ant_Periodical( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8188c2ant_BtInfoNotify( - IN PBTC_COEXIST pBtCoexist, - IN pu1Byte tmpBuf, - IN u1Byte length - ); -VOID -EXhalbtc8188c2ant_DisplayCoexInfo( - IN PBTC_COEXIST pBtCoexist - ); diff --git a/hal/btc/HalBtc8192d2Ant.c b/hal/btc/HalBtc8192d2Ant.c deleted file mode 100644 index 0cb38ee..0000000 --- a/hal/btc/HalBtc8192d2Ant.c +++ /dev/null @@ -1,1992 +0,0 @@ -//============================================================ -// Description: -// -// This file is for 92D BT 2 Antenna Co-exist mechanism -// -// By cosa 02/11/2011 -// -//============================================================ - -//============================================================ -// include files -//============================================================ -#include "Mp_Precomp.h" - -#if WPP_SOFTWARE_TRACE -#include "HalBtc8192d2Ant.tmh" -#endif - -#if(BT_30_SUPPORT == 1) -//============================================================ -// Global variables, these are static variables -//============================================================ -static COEX_DM_8192D_2ANT GLCoexDm8192d2Ant; -static PCOEX_DM_8192D_2ANT pCoexDm=&GLCoexDm8192d2Ant; -static COEX_STA_8192D_2ANT GLCoexSta8192d2Ant; -static PCOEX_STA_8192D_2ANT pCoexSta=&GLCoexSta8192d2Ant; - -//============================================================ -// local function start with btdm_ -//============================================================ -u1Byte -halbtc8192d2ant_WifiRssiState( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte index, - IN u1Byte levelNum, - IN u1Byte rssiThresh, - IN u1Byte rssiThresh1 - ) -{ - s4Byte wifiRssi=0; - u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); - - if(levelNum == 2) - { - if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || - (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) - { - if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT)) - { - wifiRssiState = BTC_RSSI_STATE_HIGH; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_LOW; - } - } - else - { - if(wifiRssi < rssiThresh) - { - wifiRssiState = BTC_RSSI_STATE_LOW; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; - } - } - } - else if(levelNum == 3) - { - if(rssiThresh > rssiThresh1) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); - return pCoexSta->preWifiRssiState[index]; - } - - if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || - (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) - { - if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT)) - { - wifiRssiState = BTC_RSSI_STATE_MEDIUM; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_LOW; - } - } - else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || - (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) - { - if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT)) - { - wifiRssiState = BTC_RSSI_STATE_HIGH; - } - else if(wifiRssi < rssiThresh) - { - wifiRssiState = BTC_RSSI_STATE_LOW; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; - } - } - else - { - if(wifiRssi < rssiThresh1) - { - wifiRssiState = BTC_RSSI_STATE_MEDIUM; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; - } - } - } - - pCoexSta->preWifiRssiState[index] = wifiRssiState; - - return wifiRssiState; -} - -u1Byte -halbtc8192d2ant_ActionAlgorithm( - IN PBTC_COEXIST pBtCoexist - ) -{ - PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; - BOOLEAN bBtHsOn=FALSE; - u1Byte algorithm=BT_8192D_2ANT_COEX_ALGO_UNDEFINED; - u1Byte numOfDiffProfile=0; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - - if(!pStackInfo->bBtLinkExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No profile exists!!!\n")); - return algorithm; - } - - if(pStackInfo->bScoExist) - numOfDiffProfile++; - if(pStackInfo->bHidExist) - numOfDiffProfile++; - if(pStackInfo->bPanExist) - numOfDiffProfile++; - if(pStackInfo->bA2dpExist) - numOfDiffProfile++; - - if(pStackInfo->bScoExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO algorithm\n")); - algorithm = BT_8192D_2ANT_COEX_ALGO_SCO; - } - else - { - if(numOfDiffProfile == 1) - { - if(pStackInfo->bHidExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n")); - algorithm = BT_8192D_2ANT_COEX_ALGO_HID; - } - else if(pStackInfo->bA2dpExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n")); - algorithm = BT_8192D_2ANT_COEX_ALGO_A2DP; - } - else if(pStackInfo->bPanExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN only\n")); - algorithm = BT_8192D_2ANT_COEX_ALGO_PAN; - } - } - else - { - if( pStackInfo->bHidExist && - pStackInfo->bA2dpExist ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n")); - algorithm = BT_8192D_2ANT_COEX_ALGO_HID_A2DP; - } - else if( pStackInfo->bHidExist && - pStackInfo->bPanExist ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN\n")); - algorithm = BT_8192D_2ANT_COEX_ALGO_HID_PAN; - } - else if( pStackInfo->bPanExist && - pStackInfo->bA2dpExist ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN + A2DP\n")); - algorithm = BT_8192D_2ANT_COEX_ALGO_PAN_A2DP; - } - } - } - return algorithm; -} - -VOID -halbtc8192d2ant_SetFwBalance( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bBalanceOn, - IN u1Byte ms0, - IN u1Byte ms1 - ) -{ - u1Byte H2C_Parameter[3] ={0}; - - if(bBalanceOn) - { - H2C_Parameter[2] = 1; - H2C_Parameter[1] = ms1; - H2C_Parameter[0] = ms0; - } - else - { - H2C_Parameter[2] = 0; - H2C_Parameter[1] = 0; - H2C_Parameter[0] = 0; - } - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Balance=[%s:%dms:%dms], write 0xc=0x%x\n", - bBalanceOn?"ON":"OFF", ms0, ms1, - H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); - - pBtCoexist->fBtcFillH2c(pBtCoexist, 0xc, 3, H2C_Parameter); -} - -VOID -halbtc8192d2ant_Balance( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bBalanceOn, - IN u1Byte ms0, - IN u1Byte ms1 - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Balance %s\n", - (bForceExec? "force to":""), (bBalanceOn? "ON":"OFF"))); - pCoexDm->bCurBalanceOn = bBalanceOn; - - if(!bForceExec) - { - if(pCoexDm->bPreBalanceOn == pCoexDm->bCurBalanceOn) - return; - } - halbtc8192d2ant_SetFwBalance(pBtCoexist, bBalanceOn, ms0, ms1); - - pCoexDm->bPreBalanceOn = pCoexDm->bCurBalanceOn; -} - -VOID -halbtc8192d2ant_SetFwDiminishWifi( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bDacOn, - IN BOOLEAN bInterruptOn, - IN u1Byte fwDacSwingLvl, - IN BOOLEAN bNavOn - ) -{ - u1Byte H2C_Parameter[3] ={0}; - - if((pBtCoexist->stackInfo.minBtRssi <= -5) && (fwDacSwingLvl == 0x20)) - { - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], DiminishWiFi 0x20 original, but set 0x18 for Low RSSI!\n")); - fwDacSwingLvl = 0x18; - } - - H2C_Parameter[2] = 0; - H2C_Parameter[1] = fwDacSwingLvl; - H2C_Parameter[0] = 0; - if(bDacOn) - { - H2C_Parameter[2] |= 0x01; //BIT0 - if(bInterruptOn) - { - H2C_Parameter[2] |= 0x02; //BIT1 - } - } - if(bNavOn) - { - H2C_Parameter[2] |= 0x08; //BIT3 - } - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bDacOn=%s, bInterruptOn=%s, bNavOn=%s, write 0x12=0x%x\n", - (bDacOn?"ON":"OFF"), (bInterruptOn?"ON":"OFF"), (bNavOn?"ON":"OFF"), - (H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2]))); - pBtCoexist->fBtcFillH2c(pBtCoexist, 0x12, 3, H2C_Parameter); -} - - -VOID -halbtc8192d2ant_DiminishWifi( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bDacOn, - IN BOOLEAN bInterruptOn, - IN u1Byte fwDacSwingLvl, - IN BOOLEAN bNavOn - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set Diminish Wifi, bDacOn=%s, bInterruptOn=%s, fwDacSwingLvl=%d, bNavOn=%s\n", - (bForceExec? "force to":""), (bDacOn? "ON":"OFF"), (bInterruptOn? "ON":"OFF"), fwDacSwingLvl, (bNavOn? "ON":"OFF"))); - - pCoexDm->bCurDacOn = bDacOn; - pCoexDm->bCurInterruptOn = bInterruptOn; - pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; - pCoexDm->bCurNavOn = bNavOn; - - if(!bForceExec) - { - if( (pCoexDm->bPreDacOn==pCoexDm->bCurDacOn) && - (pCoexDm->bPreInterruptOn==pCoexDm->bCurInterruptOn) && - (pCoexDm->preFwDacSwingLvl==pCoexDm->curFwDacSwingLvl) && - (pCoexDm->bPreNavOn==pCoexDm->bCurNavOn) ) - return; - } - halbtc8192d2ant_SetFwDiminishWifi(pBtCoexist, bDacOn, bInterruptOn, fwDacSwingLvl, bNavOn); - - pCoexDm->bPreDacOn = pCoexDm->bCurDacOn; - pCoexDm->bPreInterruptOn = pCoexDm->bCurInterruptOn; - pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; - pCoexDm->bPreNavOn = pCoexDm->bCurNavOn; -} - -VOID -halbtc8192d2ant_SetSwRfRxLpfCorner( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bRxRfShrinkOn - ) -{ - if(bRxRfShrinkOn) - { - //Shrink RF Rx LPF corner - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf2ff7); - } - else - { - //Resume RF Rx LPF corner - // After initialized, we can use pCoexDm->btRf0x1eBackup - if(pBtCoexist->bInitilized) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); - } - } -} - - -VOID -halbtc8192d2ant_RfShrink( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bRxRfShrinkOn - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", - (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); - pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; - - if(!bForceExec) - { - if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) - return; - } - halbtc8192d2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); - - pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; -} - -VOID -halbtc8192d2ant_SetSwPenaltyTxRateAdaptive( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bLowPenaltyRa - ) -{ - u1Byte tmpU1; - - tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd); - if(bLowPenaltyRa) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n")); - tmpU1 &= ~BIT2; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n")); - tmpU1 |= BIT2; - } - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1); -} - -VOID -halbtc8192d2ant_LowPenaltyRa( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bLowPenaltyRa - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", - (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); - pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; - - if(!bForceExec) - { - if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) - return; - } - halbtc8192d2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); - - pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; -} - -VOID -halbtc8192d2ant_SetSwFullTimeDacSwing( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bSwDacSwingOn, - IN u4Byte swDacSwingLvl - ) -{ - u4Byte dacSwingLvl; - - if(bSwDacSwingOn) - { - if((pBtCoexist->stackInfo.minBtRssi <= -5) && (swDacSwingLvl == 0x20)) - { - dacSwingLvl = 0x18; - } - else - { - dacSwingLvl = swDacSwingLvl; - } - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, dacSwingLvl); - } - else - { - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, 0x30); - } -} - -VOID -halbtc8192d2ant_DacSwing( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bDacSwingOn, - IN u4Byte dacSwingLvl - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n", - (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl)); - pCoexDm->bCurDacSwingOn = bDacSwingOn; - pCoexDm->curDacSwingLvl = dacSwingLvl; - - if(!bForceExec) - { - if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && - (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) ) - return; - } - delay_ms(30); - halbtc8192d2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); - - pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; - pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; -} - -VOID -halbtc8192d2ant_SetAdcBackOff( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bAdcBackOff - ) -{ - if(bAdcBackOff) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n")); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a07611); - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n")); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a05611); - } -} - -VOID -halbtc8192d2ant_AdcBackOff( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bAdcBackOff - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n", - (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF"))); - pCoexDm->bCurAdcBackOff = bAdcBackOff; - - if(!bForceExec) - { - if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff) - return; - } - halbtc8192d2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff); - - pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff; -} - -VOID -halbtc8192d2ant_SetAgcTable( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bAgcTableEn - ) -{ - u1Byte rssiAdjustVal=0; - - if(bAgcTableEn) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0xa99); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xd4000); - - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b000001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b010001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b020001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b030001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b040001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b050001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b060001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b070001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b080001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b090001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b0A0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b0B0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7a0C0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x790D0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x780E0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x770F0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x76100001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x75110001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x74120001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x73130001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x72140001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x71150001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x70160001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6f170001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6e180001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6d190001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6c1A0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6b1B0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6a1C0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x691D0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4f1E0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4e1F0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4d200001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4c210001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4b220001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4a230001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x49240001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x48250001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x47260001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x46270001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x45280001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x44290001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x432A0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x422B0001); - - rssiAdjustVal = 12; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x30a99); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xdc000); - - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B000001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B010001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B020001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B030001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B040001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B050001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B060001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7A070001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x79080001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x78090001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x770A0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x760B0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x750C0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x740D0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x730E0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x720F0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x71100001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x70110001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6F120001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6E130001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6D140001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6C150001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6B160001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6A170001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x69180001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x68190001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x671A0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x661B0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x651C0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x641D0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x631E0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x621F0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x61200001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x60210001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x49220001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x48230001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x47240001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x46250001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x45260001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x44270001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x43280001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x42290001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x412A0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x402B0001); - } - - // set rssiAdjustVal for wifi module. - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); -} - - - -VOID -halbtc8192d2ant_AgcTable( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bAgcTableEn - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n", - (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable"))); - pCoexDm->bCurAgcTableEn = bAgcTableEn; - - if(!bForceExec) - { - if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) - return; - } - halbtc8192d2ant_SetAgcTable(pBtCoexist, bAgcTableEn); - - pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; -} - -VOID -halbtc8192d2ant_SetCoexTable( - IN PBTC_COEXIST pBtCoexist, - IN u4Byte val0x6c4, - IN u4Byte val0x6c8, - IN u4Byte val0x6cc - ) -{ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6cc, val0x6cc); -} - -VOID -halbtc8192d2ant_CoexTable( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN u4Byte val0x6c4, - IN u4Byte val0x6c8, - IN u4Byte val0x6cc - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", - (bForceExec? "force to":""), val0x6c4, val0x6c8, val0x6cc)); - pCoexDm->curVal0x6c4 = val0x6c4; - pCoexDm->curVal0x6c8 = val0x6c8; - pCoexDm->curVal0x6cc = val0x6cc; - - if(!bForceExec) - { - if( (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && - (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && - (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) - return; - } - halbtc8192d2ant_SetCoexTable(pBtCoexist, val0x6c4, val0x6c8, val0x6cc); - - pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; - pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; - pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; -} - -VOID -halbtc8192d2ant_CoexAllOff( - IN PBTC_COEXIST pBtCoexist - ) -{ - // fw mechanism - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); -} -VOID -halbtc8192d2ant_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ) -{ -} - -VOID -halbtc8192d2ant_MonitorBtEnableDisable( - IN PBTC_COEXIST pBtCoexist, - IN u4Byte btActive - ) -{ - static BOOLEAN bPreBtDisabled=FALSE; - static u4Byte btDisableCnt=0; - BOOLEAN bBtDisabled=FALSE, bForceToRoam=FALSE; - u4Byte u4Tmp=0; - - // This function check if bt is disabled - if(btActive) - { - btDisableCnt = 0; - bBtDisabled = FALSE; - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); - } - else - { - btDisableCnt++; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", - btDisableCnt)); - if(btDisableCnt >= 2) - { - bBtDisabled = TRUE; - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); - } - } - if(bPreBtDisabled != bBtDisabled) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", - (bPreBtDisabled ? "disabled":"enabled"), - (bBtDisabled ? "disabled":"enabled"))); - - bForceToRoam = TRUE; - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_FORCE_TO_ROAM, &bForceToRoam); - - bPreBtDisabled = bBtDisabled; - } -} - -VOID -halbtc8192d2ant_MonitorBtState( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN stateChange=FALSE; - u4Byte BT_Polling, Ratio_Act, Ratio_STA; - u4Byte BT_Active, BT_State; - u4Byte regBTActive=0, regBTState=0, regBTPolling=0; - u4Byte btBusyThresh=0; - u4Byte fwVer=0; - static BOOLEAN bBtBusyTraffic=FALSE; - BOOLEAN bRejApAggPkt=FALSE; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FirmwareVersion = 0x%x(%d)\n", fwVer, fwVer)); - - regBTActive = 0x444; - regBTState = 0x448; - regBTPolling = 0x44c; - - btBusyThresh = 40; - - BT_Active = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTActive); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Active(0x%x)=0x%x\n", regBTActive, BT_Active)); - BT_Active = BT_Active & 0x00ffffff; - - BT_State = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTState); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_State(0x%x)=0x%x\n", regBTState, BT_State)); - BT_State = BT_State & 0x00ffffff; - - BT_Polling = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTPolling); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Polling(0x%x)=0x%x\n", regBTPolling, BT_Polling)); - - if(BT_Active==0xffffffff && BT_State==0xffffffff && BT_Polling==0xffffffff ) - return; - - // 2011/05/04 MH For Slim combo test meet a problem. Surprise remove and WLAN is running - // DHCP process. At the same time, the register read value might be zero. And cause BSOD 0x7f - // EXCEPTION_DIVIDED_BY_ZERO. In This case, the stack content may always be wrong due to - // HW divide trap. - if (BT_Polling==0) - return; - - halbtc8192d2ant_MonitorBtEnableDisable(pBtCoexist, BT_Active); - - Ratio_Act = BT_Active*1000/BT_Polling; - Ratio_STA = BT_State*1000/BT_Polling; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_Act=%d\n", Ratio_Act)); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_STA=%d\n", Ratio_STA)); - - if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - if(Ratio_STA < 60) // BT PAN idle - { - } - else - { - // Check if BT PAN (under BT 2.1) is uplink or downlink - if((Ratio_Act/Ratio_STA) < 2) - { // BT PAN Uplink - pCoexSta->bBtUplink = TRUE; - } - else - { // BT PAN downlink - pCoexSta->bBtUplink = FALSE; - } - } - } - - // Check BT is idle or not - if(!pBtCoexist->stackInfo.bBtLinkExist) - { - pCoexSta->bBtBusy = FALSE; - } - else - { - if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) - { - if(Ratio_Act<20) - { - pCoexSta->bBtBusy = FALSE; - } - else - { - pCoexSta->bBtBusy = TRUE; - } - } - else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - if(Ratio_STA < btBusyThresh) - { - pCoexSta->bBtBusy = FALSE; - } - else - { - pCoexSta->bBtBusy = TRUE; - } - - if( (Ratio_STA < btBusyThresh) || - (Ratio_Act<180 && Ratio_STA<130) ) - { - pCoexSta->bA2dpBusy = FALSE; - } - else - { - pCoexSta->bA2dpBusy = TRUE; - } - } - } - - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &pCoexSta->bBtBusy); - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &pCoexSta->bBtBusy); - - if(bBtBusyTraffic != pCoexSta->bBtBusy) - { // BT idle or BT non-idle - bBtBusyTraffic = pCoexSta->bBtBusy; - stateChange = TRUE; - } - - if(stateChange) - { - if(!pCoexSta->bBtBusy) - { - halbtc8192d2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_CoexAllOff(pBtCoexist); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - } - else - { - halbtc8192d2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); - } - } - - if(stateChange) - { - bRejApAggPkt = pCoexSta->bBtBusy; - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejApAggPkt); - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - } -} - -VOID -halbtc8192d2ant_ActionA2dp( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState, wifiRssiState1=BTC_RSSI_STATE_HIGH; - u4Byte wifiBw, wifiTrafficDir; - BOOLEAN bWifiBusy=FALSE; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); - - wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); - if(pCoexSta->bA2dpBusy && bWifiBusy) - { - if(BTC_WIFI_BW_HT40 == wifiBw) - { - wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); - } - else - { - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 25, 0); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 40, 0); - } - } - - // fw mechanism first - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x18); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - } - else - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - } - - if(BTC_WIFI_BW_HT40 == wifiBw) - { - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - } - else if(pCoexSta->bA2dpBusy) - { - // fw mechanism first - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, TRUE, 0x18, FALSE); - - // sw mechanism - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8192d2ant_CoexAllOff(pBtCoexist); - } -} - -VOID -halbtc8192d2ant_ActionPan( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; - u1Byte wifiRssiState, wifiRssiState1; - u4Byte wifiBw, wifiTrafficDir; - s4Byte wifiRssi; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); - - if(bBtHsOn) - { - halbtc8192d2ant_CoexAllOff(pBtCoexist); - } - else - { - wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 3, 25, 50); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); - } - else - { - wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 25, 0); - } - - if(pCoexSta->bBtBusy && bWifiBusy) - { - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - // fw mechanism first - if(pCoexSta->bBtUplink) - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - } - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - } - else - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - } - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - if(pCoexSta->bBtUplink) - { - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); - } - } - else if( (wifiRssiState == BTC_RSSI_STATE_MEDIUM) || - (wifiRssiState == BTC_RSSI_STATE_STAY_MEDIUM) ) - { - // fw mechanism first - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20); - - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - if(BTC_WIFI_BW_HT40 == wifiBw) - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON); - else - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - } - else - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - } - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - // fw mechanism first - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20); - - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - if(pCoexSta->bBtUplink) - { - if(BTC_WIFI_BW_HT40 == wifiBw) - { - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON); - } - else - { - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - } - else - { - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - } - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - } - else - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - } - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - else if(pCoexSta->bBtBusy && - !bWifiBusy && - (wifiRssi < 30)) - { - // fw mechanism first - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x0a, 0x20); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - // sw mechanism - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8192d2ant_CoexAllOff(pBtCoexist); - } - } -} - - -VOID -halbtc8192d2ant_ActionHid( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; - u4Byte wifiTrafficDir; - BOOLEAN bWifiBusy=FALSE; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 45, 0); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 20, 0); - } - - if(pCoexSta->bBtBusy && bWifiBusy) - { - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - // fw mechanism first - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); - } - else - { - // fw mechanism first - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, TRUE, 0x18, FALSE); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x15); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x30, FALSE); - } - // sw mechanism - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - else - { - halbtc8192d2ant_CoexAllOff(pBtCoexist); - } -} - - - -VOID -halbtc8192d2ant_ActionSco( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState; - u4Byte wifiBw; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); - - if(BTC_WIFI_BW_HT40 == wifiBw) - { - // fw mechanism first - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - // fw mechanism first - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } -} - -VOID -halbtc8192d2ant_ActionHidA2dp( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState, wifiRssiState1; - u4Byte wifiBw; - - if(pCoexSta->bBtBusy) - { - wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 35, 0); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - // fw mechanism first - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - } - else - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - } - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - else - { - wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); - // fw mechanism - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - } - else - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - } - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - else - { - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - } - } - else - { - halbtc8192d2ant_CoexAllOff(pBtCoexist); - } -} - - -VOID -halbtc8192d2ant_ActionHidPanBc4( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; - u4Byte wifiBw, wifiTrafficDir; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - - if(bBtHsOn) - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - - halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); - } - else - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); - if(BTC_WIFI_BW_LEGACY == wifiBw) - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - - halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); - } - else if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - - halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else if(!bWifiBusy) - { - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - } - } - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); -} -VOID -halbtc8192d2ant_ActionHidPanBc8( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; - u1Byte wifiRssiState; - u4Byte wifiBw, wifiTrafficDir; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - - if(!bBtHsOn) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0); - if((pCoexSta->bBtBusy && bWifiBusy)) - { - // fw mechanism first - if(pCoexSta->bBtUplink) - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20); - } - else - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20); - } - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - - // sw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - else - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - else - { - halbtc8192d2ant_CoexAllOff(pBtCoexist); - } - } - else - { - if(BTC_INTF_USB == pBtCoexist->chipInterface) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); - if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - - halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) - { - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); - } - } - else - { - if(pCoexSta->bBtBusy) - { - // fw mechanism - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); - } - else - { - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - } -} - -VOID -halbtc8192d2ant_ActionHidPan( - IN PBTC_COEXIST pBtCoexist - ) -{ - if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) - { - halbtc8192d2ant_ActionHidPanBc4(pBtCoexist); - } - else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - halbtc8192d2ant_ActionHidPanBc8(pBtCoexist); - } -} - -VOID -halbtc8192d2ant_ActionPanA2dpBc4( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; - u1Byte wifiRssiState; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); - if(bBtHsOn) - { - if(pCoexSta->bBtBusy) - { - // fw mechanism - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); - } - else - { - halbtc8192d2ant_CoexAllOff(pBtCoexist); - } - } - else - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - if(pCoexSta->bBtBusy && bWifiBusy) - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - } - else - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); - } - // sw mechanism - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } -} -VOID -halbtc8192d2ant_ActionPanA2dpBc8( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; - u1Byte wifiRssiState; - u4Byte wifiBw; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - - if(!bBtHsOn) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0); - if((pCoexSta->bBtBusy && bWifiBusy)) - { - // fw mechanism first - if(pCoexSta->bBtUplink) - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20); - } - else - { - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20); - } - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); - - // sw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - else - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - else - { - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } - else - { - halbtc8192d2ant_CoexAllOff(pBtCoexist); - } - } - else - { - if(pCoexSta->bBtBusy) - { - // fw mechanism - halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); - halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); - - // sw mechanism - halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); - } - else - { - halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); - } - } -} - -VOID -halbtc8192d2ant_ActionPanA2dp( - IN PBTC_COEXIST pBtCoexist - ) -{ - if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) - { - halbtc8192d2ant_ActionPanA2dpBc4(pBtCoexist); - } - else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - halbtc8192d2ant_ActionPanA2dpBc8(pBtCoexist); - } -} - -BOOLEAN -halbtc8192d2ant_IsBtCoexistEnter( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte macPhyMode; - BOOLEAN bRet=TRUE; - BOOLEAN bWifiUnder5G=FALSE; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_MAC_PHY_MODE, &macPhyMode); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G); - - if(BTC_SMSP != macPhyMode) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Only support single mac single phy!!\n")); - bRet = FALSE; - } - - if(bWifiUnder5G) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under 5G or A band\n")); - halbtc8192d2ant_CoexAllOff(pBtCoexist); - bRet = FALSE; - } - - return bRet; -} - -//============================================================ -// extern function start with EXhalbtc8192d2ant_ -//============================================================ -VOID -EXhalbtc8192d2ant_PowerOnSetting( - IN PBTC_COEXIST pBtCoexist - ) -{ -} - -VOID -EXhalbtc8192d2ant_InitHwConfig( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bWifiOnly - ) -{ - u1Byte u1Tmp=0; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n")); - - // backup rf 0x1e value - pCoexDm->btRf0x1eBackup = - pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); - - if( (BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) || - (BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) ) - { - u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd) & BIT0; - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, u1Tmp); - - halbtc8192d2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0xaaaa9aaa, 0xffbd0040, 0x40000010); - - // switch control, here we set pathA to control - // 0x878[13] = 1, 0:pathB, 1:pathA(default) - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x878, BIT13, 0x1); - - // antsel control, here we use phy0 and enable antsel. - // 0x87c[16:15] = b'11, enable antsel, antsel output pin - // 0x87c[30] = 0, 0: phy0, 1:phy 1 - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x87c, bMaskDWord, 0x1fff8); - - // antsel to Bt or Wifi, it depends Bt on/off. - // 0x860[9:8] = 'b10, b10:Bt On, WL2G off(default), b01:Bt off, WL2G on. - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x860, BIT9|BIT8, 0x2); - - // sw/hw control switch, here we set sw control - // 0x870[9:8] = 'b11 sw control, 'b00 hw control - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x870, BIT9|BIT8, 0x3); - } -} - -VOID -EXhalbtc8192d2ant_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ) -{ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); - - halbtc8192d2ant_InitCoexDm(pBtCoexist); -} - -VOID -EXhalbtc8192d2ant_DisplayCoexInfo( - IN PBTC_COEXIST pBtCoexist - ) -{ - PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; - PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; - pu1Byte cliBuf=pBtCoexist->cliBuf; - u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; - u4Byte u4Tmp[4]; - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ - pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); - CL_PRINTF(cliBuf); - - if(pBtCoexist->bManualControl) - { - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!"); - CL_PRINTF(cliBuf); - } - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ - ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); - CL_PRINTF(cliBuf); - - // wifi status - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); - CL_PRINTF(cliBuf); - pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); - CL_PRINTF(cliBuf); - - if(pStackInfo->bProfileNotified) - { - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ - pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist); - CL_PRINTF(cliBuf); - - pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); - } - - // Sw mechanism - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); - CL_PRINTF(cliBuf); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ - pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl); - CL_PRINTF(cliBuf); - - // Fw mechanism - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); - CL_PRINTF(cliBuf); - - // Hw setting - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ - pCoexDm->btRf0x1eBackup); - CL_PRINTF(cliBuf); - - u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \ - u1Tmp[0]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \ - u4Tmp[0]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); - u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); - u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6cc); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x6c4/0x6c8/0x6cc(coexTable)", \ - u4Tmp[0], u4Tmp[1], u4Tmp[2]); - CL_PRINTF(cliBuf); - - pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -VOID -EXhalbtc8192d2ant_IpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_IPS_ENTER == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); - halbtc8192d2ant_CoexAllOff(pBtCoexist); - } - else if(BTC_IPS_LEAVE == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); - //halbtc8192d2ant_InitCoexDm(pBtCoexist); - } -} - -VOID -EXhalbtc8192d2ant_LpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_LPS_ENABLE == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); - halbtc8192d2ant_CoexAllOff(pBtCoexist); - } - else if(BTC_LPS_DISABLE == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); - halbtc8192d2ant_InitCoexDm(pBtCoexist); - } -} - -VOID -EXhalbtc8192d2ant_ScanNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_SCAN_START == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); - } - else if(BTC_SCAN_FINISH == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); - } -} - -VOID -EXhalbtc8192d2ant_ConnectNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_ASSOCIATE_START == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); - } - else if(BTC_ASSOCIATE_FINISH == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); - } -} - -VOID -EXhalbtc8192d2ant_MediaStatusNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_MEDIA_CONNECT == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); - } -} - -VOID -EXhalbtc8192d2ant_SpecialPacketNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(type == BTC_PACKET_DHCP) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); - } -} - -VOID -EXhalbtc8192d2ant_BtInfoNotify( - IN PBTC_COEXIST pBtCoexist, - IN pu1Byte tmpBuf, - IN u1Byte length - ) -{ -} - -VOID -EXhalbtc8192d2ant_HaltNotify( - IN PBTC_COEXIST pBtCoexist - ) -{ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); - - EXhalbtc8192d2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); -} - -VOID -EXhalbtc8192d2ant_Periodical( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte algorithm; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Periodical!!\n")); - - // NOTE: - // sw mechanism must be done after fw mechanism - // - if(!halbtc8192d2ant_IsBtCoexistEnter(pBtCoexist)) - return; - - if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) - { - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_GET_BT_RSSI, NULL); - - halbtc8192d2ant_MonitorBtState(pBtCoexist); - algorithm = halbtc8192d2ant_ActionAlgorithm(pBtCoexist); - pCoexDm->curAlgorithm = algorithm; - switch(pCoexDm->curAlgorithm) - { - case BT_8192D_2ANT_COEX_ALGO_SCO: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO\n")); - halbtc8192d2ant_ActionSco(pBtCoexist); - break; - case BT_8192D_2ANT_COEX_ALGO_HID: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID\n")); - halbtc8192d2ant_ActionHid(pBtCoexist); - break; - case BT_8192D_2ANT_COEX_ALGO_A2DP: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP\n")); - halbtc8192d2ant_ActionA2dp(pBtCoexist); - break; - case BT_8192D_2ANT_COEX_ALGO_PAN: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN\n")); - halbtc8192d2ant_ActionPan(pBtCoexist); - break; - case BT_8192D_2ANT_COEX_ALGO_HID_A2DP: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP\n")); - halbtc8192d2ant_ActionHidA2dp(pBtCoexist); - break; - case BT_8192D_2ANT_COEX_ALGO_HID_PAN: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+HID\n")); - halbtc8192d2ant_ActionHidPan(pBtCoexist); - break; - case BT_8192D_2ANT_COEX_ALGO_PAN_A2DP: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP\n")); - halbtc8192d2ant_ActionPanA2dp(pBtCoexist); - break; - default: - break; - } - } -} - -#endif - diff --git a/hal/btc/HalBtc8192d2Ant.h b/hal/btc/HalBtc8192d2Ant.h deleted file mode 100644 index f3862b3..0000000 --- a/hal/btc/HalBtc8192d2Ant.h +++ /dev/null @@ -1,170 +0,0 @@ -//=========================================== -// The following is for 8192D 2Ant BT Co-exist definition -//=========================================== -#define BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT 6 - -typedef enum _BT_INFO_SRC_8192D_2ANT{ - BT_INFO_SRC_8192D_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8192D_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8192D_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8192D_2ANT_MAX -}BT_INFO_SRC_8192D_2ANT,*PBT_INFO_SRC_8192D_2ANT; - -typedef enum _BT_8192D_2ANT_BT_STATUS{ - BT_8192D_2ANT_BT_STATUS_IDLE = 0x0, - BT_8192D_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8192D_2ANT_BT_STATUS_NON_IDLE = 0x2, - BT_8192D_2ANT_BT_STATUS_MAX -}BT_8192D_2ANT_BT_STATUS,*PBT_8192D_2ANT_BT_STATUS; - -typedef enum _BT_8192D_2ANT_COEX_ALGO{ - BT_8192D_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8192D_2ANT_COEX_ALGO_SCO = 0x1, - BT_8192D_2ANT_COEX_ALGO_HID = 0x2, - BT_8192D_2ANT_COEX_ALGO_A2DP = 0x3, - BT_8192D_2ANT_COEX_ALGO_PAN = 0x4, - BT_8192D_2ANT_COEX_ALGO_HID_A2DP = 0x5, - BT_8192D_2ANT_COEX_ALGO_HID_PAN = 0x6, - BT_8192D_2ANT_COEX_ALGO_PAN_A2DP = 0x7, - BT_8192D_2ANT_COEX_ALGO_MAX -}BT_8192D_2ANT_COEX_ALGO,*PBT_8192D_2ANT_COEX_ALGO; - -typedef struct _COEX_DM_8192D_2ANT{ - // fw mechanism - BOOLEAN bPreBalanceOn; - BOOLEAN bCurBalanceOn; - - // diminishWifi - BOOLEAN bPreDacOn; - BOOLEAN bCurDacOn; - BOOLEAN bPreInterruptOn; - BOOLEAN bCurInterruptOn; - u1Byte preFwDacSwingLvl; - u1Byte curFwDacSwingLvl; - BOOLEAN bPreNavOn; - BOOLEAN bCurNavOn; - - - - - - //BOOLEAN bPreDecBtPwr; - //BOOLEAN bCurDecBtPwr; - - //u1Byte preFwDacSwingLvl; - //u1Byte curFwDacSwingLvl; - //BOOLEAN bCurIgnoreWlanAct; - //BOOLEAN bPreIgnoreWlanAct; - //u1Byte prePsTdma; - //u1Byte curPsTdma; - //u1Byte psTdmaPara[5]; - //u1Byte psTdmaDuAdjType; - //BOOLEAN bResetTdmaAdjust; - //BOOLEAN bPrePsTdmaOn; - //BOOLEAN bCurPsTdmaOn; - //BOOLEAN bPreBtAutoReport; - //BOOLEAN bCurBtAutoReport; - - // sw mechanism - BOOLEAN bPreRfRxLpfShrink; - BOOLEAN bCurRfRxLpfShrink; - u4Byte btRf0x1eBackup; - BOOLEAN bPreLowPenaltyRa; - BOOLEAN bCurLowPenaltyRa; - BOOLEAN bPreDacSwingOn; - u4Byte preDacSwingLvl; - BOOLEAN bCurDacSwingOn; - u4Byte curDacSwingLvl; - BOOLEAN bPreAdcBackOff; - BOOLEAN bCurAdcBackOff; - BOOLEAN bPreAgcTableEn; - BOOLEAN bCurAgcTableEn; - //u4Byte preVal0x6c0; - //u4Byte curVal0x6c0; - u4Byte preVal0x6c4; - u4Byte curVal0x6c4; - u4Byte preVal0x6c8; - u4Byte curVal0x6c8; - u4Byte preVal0x6cc; - u4Byte curVal0x6cc; - //BOOLEAN bLimitedDig; - - // algorithm related - u1Byte preAlgorithm; - u1Byte curAlgorithm; - //u1Byte btStatus; - //u1Byte wifiChnlInfo[3]; -} COEX_DM_8192D_2ANT, *PCOEX_DM_8192D_2ANT; - -typedef struct _COEX_STA_8192D_2ANT{ - u1Byte preWifiRssiState[4]; - BOOLEAN bBtBusy; - BOOLEAN bBtUplink; - BOOLEAN bBtDownLink; - BOOLEAN bA2dpBusy; -}COEX_STA_8192D_2ANT, *PCOEX_STA_8192D_2ANT; - -//=========================================== -// The following is interface which will notify coex module. -//=========================================== -VOID -EXhalbtc8192d2ant_PowerOnSetting( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8192d2ant_InitHwConfig( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bWifiOnly - ); -VOID -EXhalbtc8192d2ant_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8192d2ant_IpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8192d2ant_LpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8192d2ant_ScanNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8192d2ant_ConnectNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8192d2ant_MediaStatusNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8192d2ant_SpecialPacketNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8192d2ant_HaltNotify( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8192d2ant_Periodical( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8192d2ant_BtInfoNotify( - IN PBTC_COEXIST pBtCoexist, - IN pu1Byte tmpBuf, - IN u1Byte length - ); -VOID -EXhalbtc8192d2ant_DisplayCoexInfo( - IN PBTC_COEXIST pBtCoexist - ); diff --git a/hal/btc/HalBtc8192e1Ant.c b/hal/btc/HalBtc8192e1Ant.c deleted file mode 100644 index 8a4d977..0000000 --- a/hal/btc/HalBtc8192e1Ant.c +++ /dev/null @@ -1,3417 +0,0 @@ -/* ************************************************************ - * Description: - * - * This file is for RTL8192E Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "Mp_Precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8192E_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8192e_1ant glcoex_dm_8192e_1ant; -static struct coex_dm_8192e_1ant *coex_dm = &glcoex_dm_8192e_1ant; -static struct coex_sta_8192e_1ant glcoex_sta_8192e_1ant; -static struct coex_sta_8192e_1ant *coex_sta = &glcoex_sta_8192e_1ant; - -const char *const glbt_info_src_8192e_1ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8192e_1ant = 20140527; -u32 glcoex_ver_8192e_1ant = 0x4f; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8192e1ant_ - * ************************************************************ */ -u8 halbtc8192e1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8192e1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8192e1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8192e1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8192e1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8192e1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8192e1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8192e1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8192e1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8192e1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8192e1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8192e1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8192e1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8192e1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8192e1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -void halbtc8192e1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0; - - /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ - /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ - - if (coex_sta->under_ips) { - coex_sta->high_priority_tx = 65535; - coex_sta->high_priority_rx = 65535; - coex_sta->low_priority_tx = 65535; - coex_sta->low_priority_rx = 65535; - return; - } - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if ((coex_sta->low_priority_tx >= 1050) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", - reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) && - (reg_lp_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8192e1ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; - } - } -} - - -void halbtc8192e1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false; - static u8 cck_lock_counter = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - if (coex_sta->under_ips) { - coex_sta->crc_ok_cck = 0; - coex_sta->crc_ok_11g = 0; - coex_sta->crc_ok_11n = 0; - coex_sta->crc_ok_11n_agg = 0; - - coex_sta->crc_err_cck = 0; - coex_sta->crc_err_11g = 0; - coex_sta->crc_err_11n = 0; - coex_sta->crc_err_11n_agg = 0; - } else { - coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf88); - coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf94); - coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf90); - coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfb8); - - coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf84); - coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf96); - coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf92); - coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfba); - } - - - /* reset counter */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0); - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - if ((coex_dm->bt_status == BT_8192E_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == - BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == - BT_8192E_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + - coex_sta->crc_ok_11n_agg)) { - if (cck_lock_counter < 5) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 5) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - coex_sta->pre_ccklock = coex_sta->cck_lock; - - -} - -boolean halbtc8192e1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - } - - return false; -} - -void halbtc8192e1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8192e1ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8192E_1ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8192e1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8192e1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8192e1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8192e1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8192e1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8192e1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8192e1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8192e1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8192e1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8192e1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** CoexTable(%d) **********\n", type); - BTC_TRACE(trace_buf); - - coex_sta->coex_table_type = type; - - switch (type) { - case 0: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, 0xffffff, 0x3); - break; - case 1: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 2: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 3: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 4: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); - break; - case 5: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaa5a5a5a, 0xffffff, 0x3); - break; - case 6: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 7: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8192e1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8192e1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8192e1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8192e1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8192e1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8192e1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8192e1ant_sw_mechanism(IN struct btc_coexist *btcoexist, - IN boolean low_penalty_ra) -{ - halbtc8192e1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8192e1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - u32 u32tmp = 0; - - if (init_hwcfg) { - btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24); - btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700); - if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); - else - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); - - /* 0x4c[27][24]='00', Set Antenna to BB */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(24); - u32tmp &= ~BIT(27); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } else if (wifi_off) { - if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); - else - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); - - /* 0x4c[27][24]='11', Set Antenna to BT, 0x64[8:7]=0, 0x64[2]=1 */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp |= BIT(24); - u32tmp |= BIT(27); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } - - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); - break; - case BTC_ANT_PATH_BT: - btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20); - break; - default: - case BTC_ANT_PATH_PTA: - btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); - break; - } -} - -void halbtc8192e1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - } - } - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - - -void halbtc8192e1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - u8 rssi_adjust_val = 0; - u8 ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51, - ps_tdma_byte3_val = 0x10; - s8 wifi_duration_adjust = 0x0; - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_sta->scan_ap_num <= 5) - wifi_duration_adjust = 5; - else if (coex_sta->scan_ap_num >= 40) - wifi_duration_adjust = -15; - else if (coex_sta->scan_ap_num >= 20) - wifi_duration_adjust = -10; - - if (!coex_sta->force_lps_on) { /* only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */ - ps_tdma_byte0_val = 0x61; /* no null-pkt */ - ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */ - ps_tdma_byte4_val = 0x10; /* 0x778 = d/1 toggle */ - } - - if ((type == 3) || (type == 13) || (type == 14)) - ps_tdma_byte4_val = ps_tdma_byte4_val & - 0xbf; /* no dynamic slot for multi-profile */ - - if (bt_link_info->slave_role == true) - ps_tdma_byte4_val = ps_tdma_byte4_val | - 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - - if (turn_on) { - switch (type) { - default: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1a, 0x1a, 0x0, ps_tdma_byte4_val); - break; - case 1: - halbtc8192e1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3a + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 2: - halbtc8192e1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x2d + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 3: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1d, 0x1d, 0x0, ps_tdma_byte4_val); - break; - case 4: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x14, 0x0); - break; - case 5: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, - 0x15, 0x3, 0x11, 0x11); - break; - case 6: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x3, 0x11, 0x11); - break; - case 7: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13, - 0xc, 0x5, 0x0, 0x0); - break; - case 8: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 9: - halbtc8192e1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 10: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0xa, 0x0, 0x40); - break; - case 11: - halbtc8192e1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 12: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, - 0x0a, 0x0a, 0x0, 0x50); - break; - case 13: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, - 0x12, 0x12, 0x0, ps_tdma_byte4_val); - break; - case 14: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, - 0x21, 0x3, 0x10, ps_tdma_byte4_val); - break; - case 15: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0x3, 0x8, 0x0); - break; - case 16: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x10, 0x0); - break; - case 18: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 20: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, - 0x3f, 0x03, 0x11, 0x10); - break; - case 21: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x11); - break; - case 22: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x10); - break; - case 23: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x18); - break; - case 24: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x3, 0x31, 0x18); - break; - case 25: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - break; - case 26: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - break; - case 27: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x98); - break; - case 28: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x69, - 0x25, 0x3, 0x31, 0x0); - break; - case 29: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xab, - 0x1a, 0x1a, 0x1, 0x10); - break; - case 30: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, 0x10); - break; - case 31: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1a, 0x1a, 0, 0x58); - break; - case 32: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x3, 0x11, 0x11); - break; - case 33: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xa3, - 0x25, 0x3, 0x30, 0x90); - break; - case 34: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x53, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 35: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x63, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 36: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x12, 0x3, 0x14, 0x50); - break; - case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */ - /* here softap mode screen off will cost 70-80mA for phone */ - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x23, - 0x18, 0x00, 0x10, 0x24); - break; - } - } else { - - /* disable PS tdma */ - switch (type) { - case 8: /* PTA Control */ - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - halbtc8192e1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, false, false); - break; - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - halbtc8192e1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, false, false); - break; - case 9: /* Software control, Antenna at WiFi side */ - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - halbtc8192e1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_WIFI, false, false); - break; - } - } - rssi_adjust_val = 0; - btcoexist->btc_set(btcoexist, - BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", - btcoexist->btc_read_4byte(btcoexist, 0x948), - btcoexist->btc_read_1byte(btcoexist, 0x765), - btcoexist->btc_read_1byte(btcoexist, 0x67)); - BTC_TRACE(trace_buf); - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8192e1ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* sw all off */ - halbtc8192e1ant_sw_mechanism(btcoexist, false); - - /* hw all off */ - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -boolean halbtc8192e1ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (wifi_connected && - (BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (!wifi_connected && - (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (wifi_connected && - (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (!wifi_connected && - (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } - - common = false; - } - - return common; -} - - -void halbtc8192e1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0, bt_info_ext; - boolean wifi_busy = false; - /*static boolean pre_wifi_busy = false;*/ - - if (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status) - wifi_busy = true; - else - wifi_busy = false; - - if ((BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == - wifi_status) || - (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) || - (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT == - wifi_status)) { - if (coex_dm->cur_ps_tdma != 1 && - coex_dm->cur_ps_tdma != 2 && - coex_dm->cur_ps_tdma != 3 && - coex_dm->cur_ps_tdma != 9) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - coex_dm->ps_tdma_du_adj_type = 9; - - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } - return; - } - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* accquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - bt_info_ext = coex_sta->bt_info_ext; - - if ((coex_sta->low_priority_tx) > 1050 || - (coex_sta->low_priority_rx) > 1250) - retry_count++; - - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ - if (wait_count <= 2) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ - if (wait_count == 1) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (result == -1) { - if ((BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 1) || - (coex_dm->cur_ps_tdma == 2))) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } - } else if (result == 1) { - if ((BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 1) || - (coex_dm->cur_ps_tdma == 2))) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = 1; - } - } else { /* no change */ - /* Bryant Modify - if(wifi_busy != pre_wifi_busy) - { - pre_wifi_busy = wifi_busy; - halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma); - } - */ - } - - if (coex_dm->cur_ps_tdma != 1 && - coex_dm->cur_ps_tdma != 2 && - coex_dm->cur_ps_tdma != 9 && - coex_dm->cur_ps_tdma != 11) { - /* recover to previous adjust type */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - } - } -} - -void halbtc8192e1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8192e1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8192e1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8192e1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8192e1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - -void halbtc8192e1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 9); -} - -void halbtc8192e1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - BTC_TRACE(trace_buf); - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 2) { - bt_disabled = true; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - BTC_TRACE(trace_buf); - halbtc8192e1ant_action_wifi_only(btcoexist); - } - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - if (!bt_disabled) { - } else { - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - } - } -} - -/* ********************************************* - * - * Software Coex Mechanism start - * - * ********************************************* */ - -/* SCO only or SCO+PAN(HS) */ - -/* -void halbtc8192e1ant_action_sco(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8192e1ant_action_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8192e1ant_action_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8192e1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8192e1ant_action_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8192e1ant_action_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8192e1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8192e1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8192e1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, true); -} - -void halbtc8192e1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, true); -} - -*/ - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8192e1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8192e1ant_action_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8192e1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, ap_enable = false, wifi_busy = false, - bt_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) { - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - /* SCO/HID/A2DP busy */ - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if ((bt_link_info->pan_exist) || (wifi_busy)) { - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } -} - -void halbtc8192e1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* tdma and coex table */ - - if (bt_link_info->sco_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else { /* HID */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } -} - -void halbtc8192e1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - u8 bt_rssi_state; - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - bt_rssi_state = halbtc8192e1ant_bt_rssi_state(2, 28, 0); - - if ((coex_sta->low_priority_rx >= 1000) && - (coex_sta->low_priority_rx != 65535)) - bt_link_info->slave_role = true; - else - bt_link_info->slave_role = false; - - if (bt_link_info->hid_only) { /* HID */ - halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, - wifi_status); - coex_dm->auto_tdma_adjust = false; - return; - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - halbtc8192e1ant_tdma_duration_adjust_for_acl(btcoexist, - wifi_status); -#if 0 - if (coex_sta->cck_lock) - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - else -#endif - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = true; - } - } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - coex_dm->auto_tdma_adjust = false; - - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && - bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - /* BT no-profile busy (0x9) */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } -} - -void halbtc8192e1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - /* power save state */ - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8192e1ant_action_wifi_not_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* Bryant Add */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8192e1ant_action_wifi_not_connected_asso_auth( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8192e1ant_action_wifi_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* Bryant Add */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8192e1ant_action_wifi_connected_specific_packet( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8192e1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - boolean scan = false, link = false, roam = false; - boolean under_4way = false, ap_enable = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (under_4way) { - halbtc8192e1ant_action_wifi_connected_specific_packet(btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - if (scan) - halbtc8192e1ant_action_wifi_connected_scan(btcoexist); - else - halbtc8192e1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* power save state */ - if (!ap_enable && - BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status && - !btcoexist->bt_link_info.hid_only) { - if (btcoexist->bt_link_info.a2dp_only) { /* A2DP */ - if (!wifi_busy) - halbtc8192e1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - else { /* busy */ - if (coex_sta->scan_ap_num >= - BT_8192E_1ANT_WIFI_NOISY_THRESH) /* no force LPS, no PS-TDMA, use pure TDMA */ - halbtc8192e1ant_power_save_state( - btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8192e1ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - } else if ((coex_sta->pan_exist == false) && - (coex_sta->a2dp_exist == false) && - (coex_sta->hid_exist == false)) - halbtc8192e1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - else - halbtc8192e1ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - } else - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - /* tdma and coex table */ - if (!wifi_busy) { - if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8192e1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - else - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } else { - if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8192e1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - else - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } -} - -void halbtc8192e1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - - algorithm = halbtc8192e1ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - - if (halbtc8192e1ant_is_common_action(btcoexist)) { - - } else { - switch (coex_dm->cur_algorithm) { - case BT_8192E_1ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_sco(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_hid(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_a2dp(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_a2dp_pan_hs(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_pan_edr(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_pan_hs(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_pan_edr_a2dp(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_pan_edr_hid(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_hid_a2dp_pan_edr(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_hid_a2dp(btcoexist); */ - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_coex_all_off(btcoexist); */ - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8192e1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - boolean miracast_plus_bt = false; - u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if ((BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, - 0, 1); - miracast_plus_bt = true; - } else { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, - 0, 0); - miracast_plus_bt = false; - } - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if ((bt_link_info->a2dp_exist) && - (coex_sta->c2h_bt_inquiry_page)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8192e1ant_action_bt_inquiry(btcoexist); - } else - halbtc8192e1ant_action_wifi_multi_port(btcoexist); - - return; - } else { - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); - - if (bt_link_info->sco_exist) - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, - false, true, 0x5); - else - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, - false, true, 0x8); - - halbtc8192e1ant_sw_mechanism(btcoexist, true); - halbtc8192e1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - } else { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x5); - - halbtc8192e1ant_sw_mechanism(btcoexist, false); - halbtc8192e1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8192e1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8192e1ant_action_hs(btcoexist); - return; - } - - - if (!wifi_connected) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is non connected-idle !!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - if (scan) - halbtc8192e1ant_action_wifi_not_connected_scan( - btcoexist); - else - halbtc8192e1ant_action_wifi_not_connected_asso_auth( - btcoexist); - } else - halbtc8192e1ant_action_wifi_not_connected(btcoexist); - } else /* wifi LPS/Busy */ - halbtc8192e1ant_action_wifi_connected(btcoexist); -} - -void halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - - /* sw all off */ - halbtc8192e1ant_sw_mechanism(btcoexist, false); - - /* halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ - halbtc8192e1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - coex_sta->pop_event_cnt = 0; -} - -void halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - u16 u16tmp = 0; - u8 u8tmp = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - /* antenna sw ctrl to bt */ - halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, false); - - halbtc8192e1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - /* antenna switch control parameter */ - btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555); - - /* coex parameters */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* enable PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); - /* enable mailbox interface */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40); - u16tmp |= BIT(9); - btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp); - - /* enable PTA I2C mailbox */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101); - u8tmp |= BIT(4); - btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp); - - /* enable bt clock when wifi is disabled. */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93); - u8tmp |= BIT(0); - btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp); - /* enable bt clock when suspend. */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); - u8tmp |= BIT(0); - btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); -} - - -/* -void halbtc8192e1ant_wifi_off_hw_cfg(IN struct btc_coexist* btcoexist) -{ - - -} -*/ - -/* ************************************************************ - * work around function start with wa_halbtc8192e1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8192e1ant_ - * ************************************************************ */ -void ex_halbtc8192e1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ -#if 0 - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x0; - u16 u16tmp = 0x0; - - btcoexist->stop_coex_dm = true; - - btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20); - - /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - - /* set GRAN_BT = 1 */ - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); - /* set WLAN_ACT = 0 */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - if (btcoexist->chip_interface == BTC_INTF_USB) { - /* fixed at S0 for USB interface */ - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - - u8tmp |= 0x1; /* antenna inverse */ - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - } else { - /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ - if (board_info->single_ant_path == 0) { - /* set to S1 */ - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x280); - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - u8tmp |= 0x1; /* antenna inverse */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - } - - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384, - u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, - u8tmp); - } -#endif -} - -void ex_halbtc8192e1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8192e1ant_init_hw_config(btcoexist, wifi_only); - btcoexist->stop_coex_dm = false; -} - -void ex_halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - - halbtc8192e1ant_init_coex_dm(btcoexist); - - halbtc8192e1ant_query_bt_info(btcoexist); -} - -void ex_halbtc8192e1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u32 u32tmp[4]; - u32 fw_ver = 0, bt_patch_ver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", - "CoexVer/ FwVer/ PatchVer", - glcoex_ver_date_8192e_1ant, glcoex_ver_8192e_1ant, fw_ver, - bt_patch_ver, bt_patch_ver); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", - "SCO/HID/PAN/A2DP", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8192E_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8192e_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - if (!btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - coex_dm->auto_tdma_adjust); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", - "Latest error condition(should be 0)", - coex_dm->error_condition); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", - "IgnWlanAct", - coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - } - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0xc04/ 0xd04/ 0x90c", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", - u8tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x92c/ 0x930", - (u8tmp[0]), u32tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x40/ 0x4f", - u8tmp[0], u8tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", - u32tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(hp rx[31:16]/tx[15:0])", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(lp rx[31:16]/tx[15:0])", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 1) - halbtc8192e1ant_monitor_bt_ctr(btcoexist); -#endif - - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - -void ex_halbtc8192e1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, - true); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; - - halbtc8192e1ant_init_hw_config(btcoexist, false); - halbtc8192e1ant_init_coex_dm(btcoexist); - halbtc8192e1ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8192e1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8192e1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - u8 u8tmpa, u8tmpb; - u32 u32tmp; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_SCAN_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - - halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", - u32tmp, u8tmpa, u8tmpb); - BTC_TRACE(trace_buf); - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - } - - if (coex_sta->bt_disabled) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - halbtc8192e1ant_query_bt_info(btcoexist); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8192e1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8192e1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8192e1ant_action_hs(btcoexist); - return; - } - - if (BTC_SCAN_START == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8192e1ant_action_wifi_not_connected_scan( - btcoexist); - else /* wifi is connected */ - halbtc8192e1ant_action_wifi_connected_scan(btcoexist); - } else if (BTC_SCAN_FINISH == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8192e1ant_action_wifi_not_connected(btcoexist); - else - halbtc8192e1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8192e1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_ASSOCIATE_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - /* coex_dm->arp_cnt = 0; */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8192e1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8192e1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8192e1ant_action_hs(btcoexist); - return; - } - - if (BTC_ASSOCIATE_START == type) - halbtc8192e1ant_action_wifi_not_connected_asso_auth(btcoexist); - else if (BTC_ASSOCIATE_FINISH == type) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (!wifi_connected) /* non-connected scan */ - halbtc8192e1ant_action_wifi_not_connected(btcoexist); - else - halbtc8192e1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8192e1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - boolean wifi_under_b_mode = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x10); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - /* h2c_parameter[0] = 0x1; */ - h2c_parameter[0] = 0x0; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); -} - -void ex_halbtc8192e1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - BTC_PACKET_ARP == type) { - if (BTC_PACKET_ARP == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify\n"); - BTC_TRACE(trace_buf); - - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ARP Packet Count = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - - if (coex_dm->arp_cnt >= - 10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */ - coex_sta->wifi_is_high_pri_task = false; - else - coex_sta->wifi_is_high_pri_task = true; - } else { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify\n"); - BTC_TRACE(trace_buf); - } - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet [Type = %d] notify\n", type); - BTC_TRACE(trace_buf); - } - - coex_sta->specific_pkt_period_cnt = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8192e1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8192e1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8192e1ant_action_hs(btcoexist); - return; - } - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task))) - halbtc8192e1ant_action_wifi_connected_specific_packet(btcoexist); -} - -void ex_halbtc8192e1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean bt_busy = false; - - coex_sta->c2h_bt_info_req_sent = false; - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8192E_1ANT_MAX) - rsp_source = BT_INFO_SRC_8192E_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (BT_INFO_SRC_8192E_1ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_page = true; - else - coex_sta->c2h_bt_page = false; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; - /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */ - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] - & 0x40); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, - &coex_sta->bt_tx_rx_mask); - if (!coex_sta->bt_tx_rx_mask) { - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x3c, 0x15); - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if (coex_sta->bt_info_ext & BIT(1)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8192e1ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8192e1ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if (coex_sta->bt_info_ext & BIT(3)) { - if (!btcoexist->manual_control && - !btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8192e1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - } -#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8192e1ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8192E_1ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8192E_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8192E_1ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8192E_1ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8192E_1ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8192E_1ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - } - - halbtc8192e1ant_update_bt_link_info(btcoexist); - - bt_info = bt_info & - 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ - - if (!(bt_info & BT_INFO_8192E_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8192E_1ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8192E_1ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8192E_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8192E_1ANT_B_ACL_BUSY) { - if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) - coex_dm->auto_tdma_adjust = false; - coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - halbtc8192e1ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8192e1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u32 u32tmp; - u8 u8tmpa, u8tmpb, u8tmpc; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - } else if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, - true); - - halbtc8192e1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - btcoexist->stop_coex_dm = true; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); - u8tmpc = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n", - u32tmp, u8tmpa, u8tmpb, u8tmpc); - BTC_TRACE(trace_buf); - - } -} - -void ex_halbtc8192e1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true); - - halbtc8192e1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8192e1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8192e1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, - true); - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - halbtc8192e1ant_init_hw_config(btcoexist, false); - halbtc8192e1ant_init_coex_dm(btcoexist); - halbtc8192e1ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8192e1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], *****************Coex DM Reset*****************\n"); - BTC_TRACE(trace_buf); - - halbtc8192e1ant_init_hw_config(btcoexist, false); - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); */ - halbtc8192e1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8192e1ant_periodical(IN struct btc_coexist *btcoexist) -{ -#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 0) - halbtc8192e1ant_query_bt_info(btcoexist); - halbtc8192e1ant_monitor_bt_enable_disable(btcoexist); -#else - halbtc8192e1ant_monitor_bt_ctr(btcoexist); - halbtc8192e1ant_monitor_wifi_ctr(btcoexist); - - if (halbtc8192e1ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust) - - halbtc8192e1ant_run_coexist_mechanism(btcoexist); - - coex_sta->specific_pkt_period_cnt++; -#endif -} - - -void ex_halbtc8192e1ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata) -{ - switch (op_code) { - case BTC_DBG_SET_COEX_NORMAL: - btcoexist->manual_control = false; - halbtc8192e1ant_init_coex_dm(btcoexist); - break; - case BTC_DBG_SET_COEX_WIFI_ONLY: - btcoexist->manual_control = true; - halbtc8192e1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 9); - break; - case BTC_DBG_SET_COEX_BT_ONLY: - /* todo */ - break; - default: - break; - } -} - -#endif /* #if (RTL8192E_SUPPORT == 1) */ - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ \ No newline at end of file diff --git a/hal/btc/HalBtc8192e1Ant.h b/hal/btc/HalBtc8192e1Ant.h deleted file mode 100644 index e75127c..0000000 --- a/hal/btc/HalBtc8192e1Ant.h +++ /dev/null @@ -1,226 +0,0 @@ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8192E_SUPPORT == 1) - -/* ******************************************* - * The following is for 8192E 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8192E_1ANT 1 - -#define BT_INFO_8192E_1ANT_B_FTP BIT(7) -#define BT_INFO_8192E_1ANT_B_A2DP BIT(6) -#define BT_INFO_8192E_1ANT_B_HID BIT(5) -#define BT_INFO_8192E_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8192E_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8192E_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8192E_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8192E_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT 2 - -#define BT_8192E_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ - -enum bt_info_src_8192e_1ant { - BT_INFO_SRC_8192E_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8192E_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8192E_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8192E_1ANT_MAX -}; - -enum bt_8192e_1ant_bt_status { - BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8192E_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8192E_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8192E_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8192E_1ANT_BT_STATUS_MAX -}; - -enum bt_8192e_1ant_wifi_status { - BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8192E_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8192e_1ant_coex_algo { - BT_8192E_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8192E_1ANT_COEX_ALGO_SCO = 0x1, - BT_8192E_1ANT_COEX_ALGO_HID = 0x2, - BT_8192E_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8192E_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8192E_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8192E_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8192E_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8192E_1ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8192e_1ant { - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u8 error_condition; -}; - -struct coex_sta_8192e_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - s8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8192E_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8192E_1ANT_MAX]; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - u8 bt_retry_cnt; - u8 bt_info_ext; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_agg; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_agg; - - boolean cck_lock; - boolean pre_ccklock; - u8 coex_table_type; - - boolean force_lps_on; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8192e1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8192e1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8192e1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata); - -#else /* #if (RTL8192E_SUPPORT == 1) */ -#define ex_halbtc8192e1ant_power_on_setting(btcoexist) -#define ex_halbtc8192e1ant_pre_load_firmware(btcoexist) -#define ex_halbtc8192e1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8192e1ant_init_coex_dm(btcoexist) -#define ex_halbtc8192e1ant_ips_notify(btcoexist, type) -#define ex_halbtc8192e1ant_lps_notify(btcoexist, type) -#define ex_halbtc8192e1ant_scan_notify(btcoexist, type) -#define ex_halbtc8192e1ant_connect_notify(btcoexist, type) -#define ex_halbtc8192e1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8192e1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8192e1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8192e1ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8192e1ant_halt_notify(btcoexist) -#define ex_halbtc8192e1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8192e1ant_coex_dm_reset(btcoexist) -#define ex_halbtc8192e1ant_periodical(btcoexist) -#define ex_halbtc8192e1ant_display_coex_info(btcoexist) -#define ex_halbtc8192e1ant_dbg_control(btcoexist, op_code, op_len, pdata) - -#endif - -#endif diff --git a/hal/btc/HalBtc8192e2Ant.c b/hal/btc/HalBtc8192e2Ant.c deleted file mode 100644 index 76e0e93..0000000 --- a/hal/btc/HalBtc8192e2Ant.c +++ /dev/null @@ -1,3949 +0,0 @@ -/* ************************************************************ - * Description: - * - * This file is for RTL8192E Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "Mp_Precomp.h" - - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8192E_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8192e_2ant glcoex_dm_8192e_2ant; -static struct coex_dm_8192e_2ant *coex_dm = &glcoex_dm_8192e_2ant; -static struct coex_sta_8192e_2ant glcoex_sta_8192e_2ant; -static struct coex_sta_8192e_2ant *coex_sta = &glcoex_sta_8192e_2ant; - -const char *const glbt_info_src_8192e_2ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8192e_2ant = 20130912; -u32 glcoex_ver_8192e_2ant = 0x35; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8192e2ant_ - * ************************************************************ */ -u8 halbtc8192e2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8192e2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8192e2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - BTC_TRACE(trace_buf); - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 2) { - bt_disabled = true; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - BTC_TRACE(trace_buf); - } - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - if (!bt_disabled) { - } else { - } - } -} - -u32 halbtc8192e2ant_decide_ra_mask(IN struct btc_coexist *btcoexist, - IN u8 ss_type, IN u32 ra_mask_type) -{ - u32 dis_ra_mask = 0x0; - - switch (ra_mask_type) { - case 0: /* normal mode */ - if (ss_type == 2) - dis_ra_mask = 0x0; /* enable 2ss */ - else - dis_ra_mask = 0xfff00000; /* disable 2ss */ - break; - case 1: /* disable cck 1/2 */ - if (ss_type == 2) - dis_ra_mask = 0x00000003; /* enable 2ss */ - else - dis_ra_mask = 0xfff00003; /* disable 2ss */ - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - if (ss_type == 2) - dis_ra_mask = 0x0001f1f7; /* enable 2ss */ - else - dis_ra_mask = 0xfff1f1f7; /* disable 2ss */ - break; - default: - break; - } - - return dis_ra_mask; -} - -void halbtc8192e2ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8192e2ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8192e2ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8192e2ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8192e2ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - u32 dis_ra_mask = 0x0; - - coex_dm->cur_ra_mask_type = ra_mask_type; - dis_ra_mask = halbtc8192e2ant_decide_ra_mask(btcoexist, - coex_dm->cur_ss_type, ra_mask_type); - halbtc8192e2ant_update_ra_mask(btcoexist, force_exec, dis_ra_mask); - - halbtc8192e2ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8192e2ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8192e2ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8192e2ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8192e2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); -} - -void halbtc8192e2ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -boolean halbtc8192e2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - } - - return false; -} - -void halbtc8192e2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8192e2ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8192E_2ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_SCO_PAN; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - if (stack_info->num_of_hid >= 2) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID*2 + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_HID_A2DP; - } - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_SCO_PAN; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8192e2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - -void halbtc8192e2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN u8 dec_bt_pwr_lvl) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = dec_bt_pwr_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); -} - -void halbtc8192e2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 dec_bt_pwr_lvl) -{ - coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; - - if (!force_exec) { -#if 0 /* work around, avoid h2c command fail. */ - if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) - return; -#endif - } - halbtc8192e2ant_set_fw_dec_bt_pwr(btcoexist, - coex_dm->cur_bt_dec_pwr_lvl); - - coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; -} - -void halbtc8192e2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8192e2ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8192e2ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8192e2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8192e2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - -void halbtc8192e2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist, - IN boolean rx_rf_shrink_on) -{ - if (rx_rf_shrink_on) { - /* Shrink RF Rx LPF corner */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Shrink RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, - 0xffffc); - } else { - /* Resume RF Rx LPF corner */ - /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ - if (btcoexist->initilized) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Resume RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, coex_dm->bt_rf_0x1e_backup); - } - } -} - -void halbtc8192e2ant_rf_shrink(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rx_rf_shrink_on) -{ - coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; - - if (!force_exec) { - if (coex_dm->pre_rf_rx_lpf_shrink == - coex_dm->cur_rf_rx_lpf_shrink) - return; - } - halbtc8192e2ant_set_sw_rf_rx_lpf_corner(btcoexist, - coex_dm->cur_rf_rx_lpf_shrink); - - coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; -} - -void halbtc8192e2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8192e2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8192e2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8192e2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, - IN u32 level) -{ - u8 val = (u8)level; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Write SwDacSwing = 0x%x\n", level); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val); -} - -void halbtc8192e2ant_set_sw_full_time_dac_swing(IN struct btc_coexist - *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) -{ - if (sw_dac_swing_on) - halbtc8192e2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl); - else - halbtc8192e2ant_set_dac_swing_reg(btcoexist, 0x18); -} - - -void halbtc8192e2ant_dac_swing(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) -{ - coex_dm->cur_dac_swing_on = dac_swing_on; - coex_dm->cur_dac_swing_lvl = dac_swing_lvl; - - if (!force_exec) { - if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && - (coex_dm->pre_dac_swing_lvl == - coex_dm->cur_dac_swing_lvl)) - return; - } - delay_ms(30); - halbtc8192e2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, - dac_swing_lvl); - - coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; - coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; -} - -void halbtc8192e2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean adc_back_off) -{ - if (adc_back_off) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x3); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x1); - } -} - -void halbtc8192e2ant_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean adc_back_off) -{ - coex_dm->cur_adc_back_off = adc_back_off; - - if (!force_exec) { - if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) - return; - } - halbtc8192e2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off); - - coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; -} - -void halbtc8192e2ant_set_agc_table(IN struct btc_coexist *btcoexist, - IN boolean agc_table_en) -{ - /* =================BB AGC Gain Table */ - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x0a1A0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x091B0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x081C0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x071D0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x061E0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x051F0001); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001); - } -} - -void halbtc8192e2ant_agc_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean agc_table_en) -{ - coex_dm->cur_agc_table_en = agc_table_en; - - if (!force_exec) { - if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) - return; - } - halbtc8192e2ant_set_agc_table(btcoexist, agc_table_en); - - coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; -} - -void halbtc8192e2ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8192e2ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8192e2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8192e2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - switch (type) { - case 0: - halbtc8192e2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 1: - halbtc8192e2ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 2: - halbtc8192e2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5ffb5ffb, 0xffffff, 0x3); - break; - case 3: - halbtc8192e2ant_coex_table(btcoexist, force_exec, - 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3); - break; - case 4: - halbtc8192e2ant_coex_table(btcoexist, force_exec, - 0xdfffdfff, 0x5ffb5ffb, 0xffffff, 0x3); - break; - - default: - break; - } -} - -void halbtc8192e2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8192e2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8192e2ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8192e2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - - h2c_parameter[0] = byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = byte5; - - coex_dm->ps_tdma_para[0] = byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8192e2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, - IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, - IN boolean limited_dig, IN boolean bt_lna_constrain) -{ - /* - u32 wifi_bw; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if(BTC_WIFI_BW_HT40 != wifi_bw) - { - if (shrink_rx_lpf) - shrink_rx_lpf = false; - } - */ - - halbtc8192e2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); - /* halbtc8192e2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); */ -} - -void halbtc8192e2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, - IN boolean agc_table_shift, IN boolean adc_back_off, - IN boolean sw_dac_swing, IN u32 dac_swing_lvl) -{ - halbtc8192e2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); - /* halbtc8192e2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */ - halbtc8192e2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, - dac_swing_lvl); -} - -void halbtc8192e2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - u32 u32tmp = 0; - - if (init_hwcfg) { - btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24); - btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700); - if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); - else - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); - - /* 0x4c[27][24]='00', Set Antenna to BB */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(24); - u32tmp &= ~BIT(27); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } else if (wifi_off) { - if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); - else - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); - - /* 0x4c[27][24]='11', Set Antenna to BT, 0x64[8:7]=0, 0x64[2]=1 */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp |= BIT(24); - u32tmp |= BIT(27); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } - - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); - break; - case BTC_ANT_PATH_BT: - btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20); - break; - default: - case BTC_ANT_PATH_PTA: - btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); - break; - } -} - -void halbtc8192e2ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - if (turn_on) { - switch (type) { - case 1: - default: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1a, 0x1a, 0xe1, 0x90); - break; - case 2: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x12, 0x12, 0xe1, 0x90); - break; - case 3: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, 0x90); - break; - case 4: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0xf1, 0x90); - break; - case 5: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1a, 0x1a, 0x60, 0x90); - break; - case 6: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x12, 0x12, 0x60, 0x90); - break; - case 7: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0x70, 0x90); - break; - case 8: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xa3, - 0x10, 0x3, 0x70, 0x90); - break; - case 9: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1a, 0x1a, 0xe1, 0x10); - break; - case 10: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x12, 0x12, 0xe1, 0x10); - break; - case 11: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, 0x10); - break; - case 12: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0xf1, 0x10); - break; - case 13: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1a, 0x1a, 0xe0, 0x10); - break; - case 14: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x12, 0x12, 0xe0, 0x10); - break; - case 15: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf0, 0x10); - break; - case 16: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x12, 0x3, 0xf0, 0x10); - break; - case 17: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x03, 0x10, 0x10); - break; - case 18: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x5, 0x5, 0xe1, 0x90); - break; - case 19: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0xe1, 0x90); - break; - case 20: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0x60, 0x90); - break; - case 21: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x03, 0x70, 0x90); - break; - case 71: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1a, 0x1a, 0xe1, 0x90); - break; - } - } else { - /* disable PS tdma */ - switch (type) { - default: - case 0: /* ANT2PTA, 0x778=1 */ - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - halbtc8192e2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, false, false); - break; - case 1: /* ANT2BT, 0x778=3 */ - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x8, 0x0); - delay_ms(5); - halbtc8192e2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, false, false); - break; - - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8192e2ant_set_switch_ss_type(IN struct btc_coexist *btcoexist, - IN u8 ss_type) -{ - u8 mimo_ps = BTC_MIMO_PS_DYNAMIC; - u32 dis_ra_mask = 0x0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], REAL set SS Type = %d\n", ss_type); - BTC_TRACE(trace_buf); - - dis_ra_mask = halbtc8192e2ant_decide_ra_mask(btcoexist, ss_type, - coex_dm->cur_ra_mask_type); - halbtc8192e2ant_update_ra_mask(btcoexist, FORCE_EXEC, dis_ra_mask); - - if (ss_type == 1) { - halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); - /* switch ofdm path */ - btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x11); - btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x1); - btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81111111); - /* switch cck patch */ - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x1); */ - /* btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x81); */ - mimo_ps = BTC_MIMO_PS_STATIC; - } else if (ss_type == 2) { - halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x33); - btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x3); - btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81121313); - /* remove, if 0xe77[2]=0x0 then CCK will fail, advised by Jenyu */ - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x0); */ - /* btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x41); */ - mimo_ps = BTC_MIMO_PS_DYNAMIC; - } - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_SEND_MIMO_PS, - &mimo_ps); /* set rx 1ss or 2ss */ -} - -void halbtc8192e2ant_switch_ss_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 new_ss_type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s Switch SS Type = %d\n", - (force_exec ? "force to" : ""), new_ss_type); - BTC_TRACE(trace_buf); - coex_dm->cur_ss_type = new_ss_type; - - if (!force_exec) { - if (coex_dm->pre_ss_type == coex_dm->cur_ss_type) - return; - } - halbtc8192e2ant_set_switch_ss_type(btcoexist, coex_dm->cur_ss_type); - - coex_dm->pre_ss_type = coex_dm->cur_ss_type; -} - -void halbtc8192e2ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* fw all off */ - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - - halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0); - - halbtc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - halbtc8192e2ant_switch_ss_type(btcoexist, FORCE_EXEC, 2); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - -void halbtc8192e2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - boolean low_pwr_disable = true; - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1); - - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - -boolean halbtc8192e2ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean common = false, wifi_connected = false, wifi_busy = false; - boolean bt_hs_on = false, low_pwr_disable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (bt_link_info->sco_exist || bt_link_info->hid_exist) - halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0); - else - halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - if (!wifi_connected) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non-connected idle!!\n"); - BTC_TRACE(trace_buf); - - if ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || - (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, - 2); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } else { - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, - 1); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - } - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - common = true; - } else { - if (BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, - 2); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else if (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status) { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (bt_hs_on) - return false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, - 2); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - common = false; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - - halbtc8192e2ant_switch_ss_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 21); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, - NORMAL_EXEC, 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, 0); - halbtc8192e2ant_sw_mechanism1(btcoexist, false, - false, false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - common = true; - } - } - } - - return common; -} -void halbtc8192e2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, - IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0; - - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - { - if (sco_hid) { - if (tx_pause) { - if (max_interval == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } else if (max_interval == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (max_interval == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } else { - if (max_interval == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } else if (max_interval == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (max_interval == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } else { - if (tx_pause) { - if (max_interval == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (max_interval == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (max_interval == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } - } else { - if (max_interval == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (max_interval == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (max_interval == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } - } - } - } - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* accquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ - if (wait_count <= 2) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ - if (wait_count == 1) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (max_interval == 1) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 13); - coex_dm->ps_tdma_du_adj_type = 13; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 71); - coex_dm->ps_tdma_du_adj_type = 71; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 71); - coex_dm->ps_tdma_du_adj_type = - 71; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } - } - } - } else if (max_interval == 2) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } - } - } - } else if (max_interval == 3) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } - } - } - - /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ - /* then we have to adjust it back to the previous record one. */ - if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { - boolean scan = false, link = false, roam = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", - coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (!scan && !link && !roam) - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); - BTC_TRACE(trace_buf); - } - } -} - -/* SCO only or SCO+PAN(HS) */ -void halbtc8192e2ant_action_sco(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - u32 wifi_bw; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x6); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x6); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x6); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x6); - } - } -} - -void halbtc8192e2ant_action_sco_pan(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - u32 wifi_bw; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x6); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x6); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x6); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x6); - } - } -} - -void halbtc8192e2ant_action_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8192e2ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - boolean long_dist = false; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW || - bt_rssi_state == BTC_RSSI_STATE_STAY_LOW) && - (wifi_rssi_state == BTC_RSSI_STATE_LOW || - wifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2dp, wifi/bt rssi both LOW!!\n"); - BTC_TRACE(trace_buf); - long_dist = true; - } - if (long_dist) { - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, - 0x4); - } else { - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - } - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (long_dist) - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - else - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - - if (long_dist) { - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17); - coex_dm->auto_tdma_adjust = false; - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - } else { - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, - true, 1); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, - false, 1); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, - false, 1); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - } - } - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8192e2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 2); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false, - 2); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false, - 2); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - } - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - true, 0x6); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - true, 0x6); - } - } -} - -void halbtc8192e2ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); - } - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* PAN(HS) only */ -void halbtc8192e2ant_action_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* PAN(EDR)+A2DP */ -void halbtc8192e2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 3); - } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false, - 3); - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false, - 3); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8192e2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* HID+A2DP+PAN(EDR) */ -void halbtc8192e2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 3); - } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3); - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8192e2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 2); - } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2); - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8192e2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - algorithm = halbtc8192e2ant_action_algorithm(btcoexist); - if (coex_sta->c2h_bt_inquiry_page && - (BT_8192E_2ANT_COEX_ALGO_PANHS != algorithm)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_bt_inquiry(btcoexist); - return; - } - - coex_dm->cur_algorithm = algorithm; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", - coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - - if (halbtc8192e2ant_is_common_action(btcoexist)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant common.\n"); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - } else { - if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", - coex_dm->pre_algorithm, coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - } - switch (coex_dm->cur_algorithm) { - case BT_8192E_2ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_sco(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_SCO_PAN: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO+PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_sco_pan(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_hid(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_a2dp(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_pan_edr(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_pan_hs(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_pan_edr_hid(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_hid_a2dp(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = unknown!!\n"); - BTC_TRACE(trace_buf); - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up) -{ - u16 u16tmp = 0; - u8 u8tmp = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - if (back_up) { - /* backup rf 0x1e value */ - coex_dm->bt_rf_0x1e_backup = - btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff); - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } - - /* antenna sw ctrl to bt */ - halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, false); - - halbtc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - /* antenna switch control parameter */ - btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555); - - /* coex parameters */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* enable PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); - /* enable mailbox interface */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40); - u16tmp |= BIT(9); - btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp); - - /* enable PTA I2C mailbox */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101); - u8tmp |= BIT(4); - btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp); - - /* enable bt clock when wifi is disabled. */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93); - u8tmp |= BIT(0); - btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp); - /* enable bt clock when suspend. */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); - u8tmp |= BIT(0); - btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); -} - -/* ************************************************************ - * work around function start with wa_halbtc8192e2ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8192e2ant_ - * ************************************************************ */ -void ex_halbtc8192e2ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8192e2ant_init_hw_config(btcoexist, true); -} - -void ex_halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - halbtc8192e2ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8192e2ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fw_ver = 0, bt_patch_ver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", - "CoexVer/ FwVer/ PatchVer", - glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant, fw_ver, - bt_patch_ver, bt_patch_ver); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", - "SCO/HID/PAN/A2DP", - stack_info->sco_exist, stack_info->hid_exist, - stack_info->pan_exist, stack_info->a2dp_exist); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8192E_2ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8192e_2ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "SS Type", - coex_dm->cur_ss_type); - CL_PRINTF(cli_buf); - - /* Sw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Sw mechanism]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", - "SM1[ShRf/ LpRA/ LimDig]", - coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, - coex_dm->limited_dig); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", - "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", - coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, - coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); - CL_PRINTF(cli_buf); - - /* Fw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Fw mechanism]============"); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - coex_dm->auto_tdma_adjust); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "DecBtPwr/ IgnWlanAct", - coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", - "RF-A, 0x1e initVal", - coex_dm->bt_rf_0x1e_backup); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "backup ARFR1/ARFR2/RL/AMaxTime", - coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2, - coex_dm->backup_retry_limit, - coex_dm->backup_ampdu_max_time); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0xc04/ 0xd04/ 0x90c", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", - u8tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x92c/ 0x930", - (u8tmp[0]), u32tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x40/ 0x4f", - u8tmp[0], u8tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", - u32tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(hp rx[31:16]/tx[15:0])", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(lp rx[31:16]/tx[15:0])", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 1) - halbtc8192e2ant_monitor_bt_ctr(btcoexist); -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8192e2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - halbtc8192e2ant_coex_all_off(btcoexist); - halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, - true); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; - } -} - -void ex_halbtc8192e2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8192e2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_SCAN_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_SCAN_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8192e2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_ASSOCIATE_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_ASSOCIATE_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8192e2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = 0x1; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); -} - -void ex_halbtc8192e2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (type == BTC_PACKET_DHCP) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], DHCP Packet notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8192e2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean bt_busy = false, limited_dig = false; - boolean wifi_connected = false; - - coex_sta->c2h_bt_info_req_sent = false; - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8192E_2ANT_MAX) - rsp_source = BT_INFO_SRC_8192E_2ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (BT_INFO_SRC_8192E_2ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8192e2ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8192e2ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if ((coex_sta->bt_info_ext & BIT(3))) { - if (!btcoexist->manual_control && - !btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - } - -#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8192e2ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8192E_2ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8192E_2ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8192E_2ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8192E_2ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8192E_2ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - } - - halbtc8192e2ant_update_bt_link_info(btcoexist); - - if (!(bt_info & BT_INFO_8192E_2ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8192E_2ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8192E_2ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8192E_2ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8192E_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8192E_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { - bt_busy = true; - limited_dig = true; - } else { - bt_busy = false; - limited_dig = false; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - coex_dm->limited_dig = limited_dig; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); - - halbtc8192e2ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8192e2ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true); - halbtc8192e2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - ex_halbtc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); -} - -void ex_halbtc8192e2ant_periodical(IN struct btc_coexist *btcoexist) -{ -#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0) - halbtc8192e2ant_query_bt_info(btcoexist); - halbtc8192e2ant_monitor_bt_ctr(btcoexist); - halbtc8192e2ant_monitor_bt_enable_disable(btcoexist); -#else - if (halbtc8192e2ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust) - halbtc8192e2ant_run_coexist_mechanism(btcoexist); -#endif -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ - diff --git a/hal/btc/HalBtc8192e2Ant.h b/hal/btc/HalBtc8192e2Ant.h deleted file mode 100644 index 5a4786a..0000000 --- a/hal/btc/HalBtc8192e2Ant.h +++ /dev/null @@ -1,190 +0,0 @@ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8192E_SUPPORT == 1) -/* ******************************************* - * The following is for 8192E 2Ant BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8192E_2ANT 0 - -#define BT_INFO_8192E_2ANT_B_FTP BIT(7) -#define BT_INFO_8192E_2ANT_B_A2DP BIT(6) -#define BT_INFO_8192E_2ANT_B_HID BIT(5) -#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8192E_2ANT_B_CONNECTION BIT(0) - -#define BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT 2 - -enum bt_info_src_8192e_2ant { - BT_INFO_SRC_8192E_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8192E_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8192E_2ANT_MAX -}; - -enum bt_8192e_2ant_bt_status { - BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8192E_2ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8192E_2ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8192E_2ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8192E_2ANT_BT_STATUS_MAX -}; - -enum bt_8192e_2ant_coex_algo { - BT_8192E_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8192E_2ANT_COEX_ALGO_SCO = 0x1, - BT_8192E_2ANT_COEX_ALGO_SCO_PAN = 0x2, - BT_8192E_2ANT_COEX_ALGO_HID = 0x3, - BT_8192E_2ANT_COEX_ALGO_A2DP = 0x4, - BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS = 0x5, - BT_8192E_2ANT_COEX_ALGO_PANEDR = 0x6, - BT_8192E_2ANT_COEX_ALGO_PANHS = 0x7, - BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8, - BT_8192E_2ANT_COEX_ALGO_PANEDR_HID = 0x9, - BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa, - BT_8192E_2ANT_COEX_ALGO_HID_A2DP = 0xb, - BT_8192E_2ANT_COEX_ALGO_MAX = 0xc -}; - -struct coex_dm_8192e_2ant { - /* fw mechanism */ - u8 pre_bt_dec_pwr_lvl; - u8 cur_bt_dec_pwr_lvl; - u8 pre_fw_dac_swing_lvl; - u8 cur_fw_dac_swing_lvl; - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean reset_tdma_adjust; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - - /* sw mechanism */ - boolean pre_rf_rx_lpf_shrink; - boolean cur_rf_rx_lpf_shrink; - u32 bt_rf_0x1e_backup; - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - boolean pre_dac_swing_on; - u32 pre_dac_swing_lvl; - boolean cur_dac_swing_on; - u32 cur_dac_swing_lvl; - boolean pre_adc_back_off; - boolean cur_adc_back_off; - boolean pre_agc_table_en; - boolean cur_agc_table_en; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u8 pre_ss_type; - u8 cur_ss_type; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 cur_ra_mask_type; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; -}; - -struct coex_sta_8192e_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - u8 bt_rssi; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8192E_2ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8192E_2ANT_MAX]; - boolean c2h_bt_inquiry_page; - u8 bt_retry_cnt; - u8 bt_info_ext; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8192e2ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8192e2ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e2ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e2ant_display_coex_info(IN struct btc_coexist *btcoexist); - -#else /* #if (RTL8192E_SUPPORT == 1) */ -#define ex_halbtc8192e2ant_power_on_setting(btcoexist) -#define ex_halbtc8192e2ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8192e2ant_init_coex_dm(btcoexist) -#define ex_halbtc8192e2ant_ips_notify(btcoexist, type) -#define ex_halbtc8192e2ant_lps_notify(btcoexist, type) -#define ex_halbtc8192e2ant_scan_notify(btcoexist, type) -#define ex_halbtc8192e2ant_connect_notify(btcoexist, type) -#define ex_halbtc8192e2ant_media_status_notify(btcoexist, type) -#define ex_halbtc8192e2ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8192e2ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8192e2ant_halt_notify(btcoexist) -#define ex_halbtc8192e2ant_periodical(btcoexist) -#define ex_halbtc8192e2ant_display_coex_info(btcoexist) - -#endif - -#endif - diff --git a/hal/btc/HalBtc8703b1Ant.c b/hal/btc/HalBtc8703b1Ant.c deleted file mode 100644 index 0225669..0000000 --- a/hal/btc/HalBtc8703b1Ant.c +++ /dev/null @@ -1,4592 +0,0 @@ -/* ************************************************************ - * Description: - * - * This file is for RTL8703B Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "Mp_Precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8703B_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8703b_1ant glcoex_dm_8703b_1ant; -static struct coex_dm_8703b_1ant *coex_dm = &glcoex_dm_8703b_1ant; -static struct coex_sta_8703b_1ant glcoex_sta_8703b_1ant; -static struct coex_sta_8703b_1ant *coex_sta = &glcoex_sta_8703b_1ant; -static struct psdscan_sta_8703b_1ant gl_psd_scan_8703b_1ant; -static struct psdscan_sta_8703b_1ant *psd_scan = &gl_psd_scan_8703b_1ant; - - -const char *const glbt_info_src_8703b_1ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8703b_1ant = 20160218; -u32 glcoex_ver_8703b_1ant = 0x09; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8703b1ant_ - * ************************************************************ */ -u8 halbtc8703b1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8703b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8703b1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8703b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8703b1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8703b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8703b1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8703b1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8703b1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8703b1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8703b1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8703b1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8703b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8703b1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8703b1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -void halbtc8703b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0, cnt_slave = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ - /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", - reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); - - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - if ((coex_sta->low_priority_tx > 1150) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - if ((coex_sta->low_priority_rx >= 1150) && (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) - && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && (coex_sta->bt_link_exist)) { - if (cnt_slave >= 3) { - bt_link_info->slave_role = true; - cnt_slave = 3; - } else - cnt_slave++; - } else { - if (cnt_slave == 0) { - bt_link_info->slave_role = false; - cnt_slave = 0; - } else - cnt_slave--; - - } - - if ((coex_sta->high_priority_tx == 0) && (coex_sta->high_priority_rx == 0) && (coex_sta->low_priority_tx == 0) && - (coex_sta->low_priority_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8703b1ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; - } - } - - -#if 0 - /* Add Hi-Pri Tx/Rx counter to avoid false detection */ - if (((coex_sta->hid_exist) || (coex_sta->sco_exist)) && - (coex_sta->high_priority_tx + coex_sta->high_priority_rx - >= 160) - && (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->bt_hi_pri_link_exist = true; - else - coex_sta->bt_hi_pri_link_exist = false; - - if ((coex_sta->acl_busy) && - (coex_sta->num_of_profile == 0)) { - if (coex_sta->low_priority_tx + - coex_sta->low_priority_rx >= 160) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - coex_sta->wrong_profile_notification++; - } - } -#endif - -} - - -void halbtc8703b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false; - static u8 cck_lock_counter = 0; - u32 total_cnt; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - if (coex_sta->under_ips) { - coex_sta->crc_ok_cck = 0; - coex_sta->crc_ok_11g = 0; - coex_sta->crc_ok_11n = 0; - coex_sta->crc_ok_11n_agg = 0; - - coex_sta->crc_err_cck = 0; - coex_sta->crc_err_11g = 0; - coex_sta->crc_err_11n = 0; - coex_sta->crc_err_11n_agg = 0; - } else { - coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf88); - coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf94); - coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf90); - coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfb8); - - coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf84); - coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf96); - coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf92); - coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfba); - } - - - /* reset counter */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0); - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + - coex_sta->crc_ok_11n_agg; - - if ((coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == - BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == - BT_8703B_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 3) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = true; - - coex_sta->pre_ccklock = coex_sta->cck_lock; - - -} - -boolean halbtc8703b1ant_is_wifibt_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false, pre_bt_off = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (coex_sta->bt_disabled != pre_bt_off) { - pre_bt_off = coex_sta->bt_disabled; - - if (coex_sta->bt_disabled) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - - BTC_TRACE(trace_buf); - return true; - } - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - } - - return false; -} - -void halbtc8703b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->bt_hi_pri_link_exist = coex_sta->bt_hi_pri_link_exist; - bt_link_info->acl_busy = coex_sta->acl_busy; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -void halbtc8703b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = - 0x1; /* enable BT AFH skip WL channel for 8703b because BT Rx LO interference */ - /* h2c_parameter[0] = 0x0; */ - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); - -} - -void halbtc8703b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8703b1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8703b1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8703b1ant_set_fw_low_penalty_ra(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8703b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8703b1ant_set_fw_low_penalty_ra(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8703b1ant_write_score_board( - IN struct btc_coexist *btcoexist, - IN u16 bitpos, - IN BOOLEAN state -) -{ - - static u16 originalval = 0x8002; - - if (state) - originalval = originalval | bitpos; - else - originalval = originalval & (~bitpos); - - - btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); -#if 0 - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "\n [BTCoex], ********** Write Scoreboard = %x**********\n", - originalval); - BTC_TRACE(trace_buf); -#endif - -} - -void halbtc8703b1ant_read_score_board( - IN struct btc_coexist *btcoexist, - IN u16 *score_board_val -) -{ - - *score_board_val = (btcoexist->btc_read_2byte(btcoexist, - 0xaa)) & 0x7fff; -} - -void halbtc8703b1ant_post_activestate_to_bt( - IN struct btc_coexist *btcoexist, - IN boolean wifi_active -) -{ - - if (wifi_active) - halbtc8703b1ant_write_score_board(btcoexist, (u16) BIT(0), TRUE); - else - halbtc8703b1ant_write_score_board(btcoexist, (u16) BIT(0), FALSE); - - /* The BT should set "No Shunt-down" mode if WL = Active for BT Synthesizer on/off interference WL Lo issue at 8703b b-cut. */ - -} - -void halbtc8703b1ant_post_onoffState_to_bt( - IN struct btc_coexist *btcoexist, - IN boolean wifi_on -) -{ - - if (wifi_on) - halbtc8703b1ant_write_score_board(btcoexist, (u16) BIT(1), TRUE); - else - halbtc8703b1ant_write_score_board(btcoexist, (u16) BIT(1), FALSE); - -} - -void halbtc8703b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - u16 u16tmp; - - /* This function check if bt is disabled */ -#if 1 - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - - -#else /* 8703b BT can't show correct on/off status in scoreboard[1] 2015/11/26 */ - - halbtc8703b1ant_read_score_board(btcoexist, &u16tmp); - - bt_active = u16tmp & BIT(1); - - -#endif - - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } else { - - bt_disable_cnt++; - if (bt_disable_cnt >= 2) { - bt_disabled = true; - bt_disable_cnt = 2; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } - - - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - - } -} - -void halbtc8703b1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, - IN boolean isenable) -{ - -#if (BT_8703B_1ANT_ENABLE_GNTBT_TO_GPIO14 == 1) - if (isenable) { - /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); - - /* enable GNT_BT debug to GPIO */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0); - } else { - /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); - - /* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1); - } -#endif -} - -u32 halbtc8703b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, - IN u16 reg_addr) -{ - u32 j = 0; - - - /* wait for ready bit before access 0x7c0 */ - btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr); - - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x7c3)&BIT(5)) == 0) && - (j < BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - return btcoexist->btc_read_4byte(btcoexist, - 0x7c8); /* get read data */ - -} - -void halbtc8703b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist *btcoexist, - IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) -{ - u32 val, i = 0, j = 0, bitpos = 0; - - - if (bit_mask == 0x0) - return; - if (bit_mask == 0xffffffff) { - btcoexist->btc_write_4byte(btcoexist, 0x7c4, - reg_value); /* put write data */ - - /* wait for ready bit before access 0x7c0 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x7c3)&BIT(5)) == 0) && - (j < BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x7c0, - 0xc00F0000 | reg_addr); - } else { - for (i = 0; i <= 31; i++) { - if (((bit_mask >> i) & 0x1) == 0x1) { - bitpos = i; - break; - } - } - - /* read back register value before write */ - val = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - reg_addr); - val = (val & (~bit_mask)) | (reg_value << bitpos); - - btcoexist->btc_write_4byte(btcoexist, 0x7c4, - val); /* put write data */ - - /* wait for ready bit before access 0x7c0 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x7c3)&BIT(5)) == 0) && - (j < BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x7c0, - 0xc00F0000 | reg_addr); - - } - -} - -void halbtc8703b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 val; - - val = (enable) ? 1 : 0; - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, - val); /* 0x38[7] */ - -} - -void halbtc8703b1ant_sw_mechanism(IN struct btc_coexist *btcoexist, - IN boolean low_penalty_ra) -{ - halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8703b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, - IN boolean wifi_control) -{ - u8 val; - - val = (wifi_control) ? 1 : 0; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, - val); /* 0x70[26] */ - -} - -void halbtc8703b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, bit_mask; - - state = state & 0x1; - val = (sw_control) ? ((state << 1) | 0x1) : 0; - - switch (control_block) { - case BT_8703B_1ANT_GNT_BLOCK_RFC_BB: - default: - bit_mask = 0xc000; - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[15:14] */ - bit_mask = 0x0c00; - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[11:10] */ - break; - case BT_8703B_1ANT_GNT_BLOCK_RFC: - bit_mask = 0xc000; - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[15:14] */ - break; - case BT_8703B_1ANT_GNT_BLOCK_BB: - bit_mask = 0x0c00; - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[11:10] */ - break; - - } - -} - -void halbtc8703b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, bit_mask; - - state = state & 0x1; - val = (sw_control) ? ((state << 1) | 0x1) : 0; - - switch (control_block) { - case BT_8703B_1ANT_GNT_BLOCK_RFC_BB: - default: - bit_mask = 0x3000; - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[13:12] */ - bit_mask = 0x0300; - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[9:8] */ - break; - case BT_8703B_1ANT_GNT_BLOCK_RFC: - bit_mask = 0x3000; - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[13:12] */ - break; - case BT_8703B_1ANT_GNT_BLOCK_BB: - bit_mask = 0x0300; - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[9:8] */ - break; - - } - -} - -void halbtc8703b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u16 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8703B_1ANT_CTT_WL_VS_LTE: - reg_addr = 0xa0; - break; - case BT_8703B_1ANT_CTT_BT_VS_LTE: - reg_addr = 0xa4; - break; - } - - if (reg_addr != 0x0000) - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ - - -} - - -void halbtc8703b1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u8 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8703B_1ANT_LBTT_WL_BREAK_LTE: - reg_addr = 0xa8; - break; - case BT_8703B_1ANT_LBTT_BT_BREAK_LTE: - reg_addr = 0xac; - break; - case BT_8703B_1ANT_LBTT_LTE_BREAK_WL: - reg_addr = 0xb0; - break; - case BT_8703B_1ANT_LBTT_LTE_BREAK_BT: - reg_addr = 0xb4; - break; - } - - if (reg_addr != 0x0000) - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ - - -} - -void halbtc8703b1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8703b1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8703b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8703b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - u32 break_table; - u8 select_table; - - coex_sta->coex_table_type = type; - - if (coex_sta->concurrent_rx_mode_on == true) { - break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ - select_table = - 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ - } else { - break_table = 0xffffff; - select_table = 0x3; - } - - switch (type) { - case 0: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, break_table, - select_table); - break; - case 1: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 2: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0xaa5a5a5a, 0xaa5a5a5a, break_table, - select_table); - break; - case 3: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0xaa555555, 0xaa5a5a5a, break_table, - select_table); - break; - case 4: - halbtc8703b1ant_coex_table(btcoexist, - force_exec, 0xaa555555, 0xaa5a5a5a, - break_table, select_table); - break; - case 5: - halbtc8703b1ant_coex_table(btcoexist, - force_exec, 0x5a5a5a5a, 0x5a5a5a5a, - break_table, select_table); - break; - case 6: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaaaaaa, break_table, - select_table); - break; - case 7: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, break_table, - select_table); - break; - case 8: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, break_table, - select_table); - break; - case 9: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, break_table, - select_table); - break; - case 10: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, break_table, - select_table); - break; - case 11: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, break_table, - select_table); - break; - case 12: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, break_table, - select_table); - break; - case 13: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0xaaaaaaaa, break_table, - select_table); - break; - case 14: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5ada5ada, break_table, - select_table); - break; - case 15: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0xaaaaaaaa, break_table, - select_table); - break; - default: - break; - } -} - -void halbtc8703b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8703b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8703b1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8703b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8703b1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8703b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8703b1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - /*halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - /*halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8);*/ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8703b1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - coex_sta->force_lps_on = false; - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - - break; - case BTC_PS_LPS_ON: - coex_sta->force_lps_on = true; - halbtc8703b1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8703b1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - - break; - case BTC_PS_LPS_OFF: - coex_sta->force_lps_on = false; - halbtc8703b1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - - break; - default: - break; - } -} - - - -void halbtc8703b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - - halbtc8703b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - } - } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - - halbtc8703b1ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } else { - halbtc8703b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - } - - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - - -void halbtc8703b1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - u8 rssi_adjust_val = 0; - static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; - static boolean pre_wifi_busy = false; - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (wifi_busy != pre_wifi_busy) { - force_exec = true; - pre_wifi_busy = wifi_busy; - } - - /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist)) - psTdmaByte4Modify = 0x1; - else - psTdmaByte4Modify = 0x0; - - if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { - - force_exec = true; - pre_psTdmaByte4Modify = psTdmaByte4Modify; - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - if (turn_on) { - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - } - - - if (turn_on) { - switch (type) { - default: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x11); - break; - - case 3: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x3a, 0x03, 0x10, 0x10); - break; - case 4: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x21, 0x03, 0x10, 0x10); - break; - case 5: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x03, 0x11, 0x11); - break; - case 6: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x20, 0x03, 0x11, 0x11); - break; - case 7: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify); - break; - case 8: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify); - break; - case 13: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x25, 0x03, 0x10, 0x10 | psTdmaByte4Modify); - break; - case 14: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x15, 0x03, 0x10, 0x10 | psTdmaByte4Modify); - break; - case 15: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x20, 0x03, 0x10, 0x10 | psTdmaByte4Modify); - break; - case 17: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x14 | psTdmaByte4Modify); - break; - case 19: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x03, 0x11, 0x10); - break; - case 20: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); - break; - case 21: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); - break; - case 22: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x25, 0x03, 0x11, 0x10); - break; - case 32: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x11); - break; - case 33: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x10); - break; - - } - } else { - - /* disable PS tdma */ - switch (type) { - case 8: /* PTA Control */ - halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - break; - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - break; - case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */ - halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8703b1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg, - IN boolean wifi_off) -{ - u32 cnt_bt_cal_chk = 0; - boolean is_in_mp_mode = false; - u8 u8tmp = 0; - u32 u32tmp1 = 0, u32tmp2 = 0; - - coex_dm->cur_ant_pos_type = ant_pos_type; - -#if 1 - u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0x54); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Before Ant Setup) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif - - if (init_hwcfg) { - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8703b1ant_ltecoex_set_coex_table(btcoexist, - BT_8703B_1ANT_CTT_WL_VS_LTE, 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8703b1ant_ltecoex_set_coex_table(btcoexist, - BT_8703B_1ANT_CTT_BT_VS_LTE, 0xffff); - - /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ - while (cnt_bt_cal_chk <= 20) { - u8tmp = btcoexist->btc_read_1byte(btcoexist, - 0x49d); - cnt_bt_cal_chk++; - if (u8tmp & BIT(0)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - delay_ms(50); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - break; - } - } - - /* set Path control owner to WL at initial step */ - halbtc8703b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8703B_1ANT_PCO_WLSIDE); - - /* set GNT_BT to SW high */ - halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW low */ - halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_LOW); - - coex_sta->gnt_control_by_PTA = false; - - } else if (wifi_off) { - /* Disable LTE Coex Function in WiFi side */ - halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0); - - /* set Path control owner to BT */ - halbtc8703b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8703B_1ANT_PCO_BTSIDE); - - coex_sta->gnt_control_by_PTA = false; - } else { - - halbtc8703b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8703B_1ANT_PCO_WLSIDE); - - - if (force_exec || - (coex_dm->cur_ant_pos_type != coex_dm->pre_ant_pos_type) || - init_hwcfg || wifi_off) { - /* internal switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - /* set GNT_BT to low */ - halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_LOW); - /* Set GNT_WL to high */ - halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); - - coex_sta->gnt_control_by_PTA = false; - break; - case BTC_ANT_PATH_BT: - /*halbtc8703b1ant_ltecoex_pathcontrol_owner( - btcoexist, BT_8703B_1ANT_PCO_BTSIDE);*/ - /* set GNT_BT to high */ - halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to low */ - halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_LOW); - - coex_sta->gnt_control_by_PTA = false; - break; - default: - case BTC_ANT_PATH_PTA: - /* set GNT_BT to PTA */ - halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8703B_1ANT_SIG_STA_SET_BY_HW); - /* Set GNT_WL to PTA */ - halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8703B_1ANT_SIG_STA_SET_BY_HW); - - coex_sta->gnt_control_by_PTA = true; - break; - } - } - } - -#if 1 - u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - if (init_hwcfg) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ant-Setup Init) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - } else if (wifi_off) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ant-Setup WiFi off) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ant-Setup Run time) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - } -#endif - - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; -} - - -boolean halbtc8703b1ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8703b1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (wifi_connected && - (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8703b1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (!wifi_connected && - (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8703b1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (wifi_connected && - (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8703b1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (!wifi_connected && - (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8703b1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } - - common = false; - } - - return common; -} - -/* ********************************************* - * - * Software Coex Mechanism start - * - * ********************************************* */ - -/* SCO only or SCO+PAN(HS) */ - -/* -void halbtc8703b1ant_action_sco(IN struct btc_coexist* btcoexist) -{ - halbtc8703b1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8703b1ant_action_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8703b1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8703b1ant_action_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8703b1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8703b1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8703b1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8703b1ant_action_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8703b1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8703b1ant_action_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8703b1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8703b1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8703b1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8703b1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8703b1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8703b1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8703b1ant_sw_mechanism(btcoexist, true); -} - -void halbtc8703b1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8703b1ant_sw_mechanism(btcoexist, true); -} - -*/ - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -u8 halbtc8703b1ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8703B_1ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - - - -void halbtc8703b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) -{ - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8703b1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, - false, false); - halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); -} - -void halbtc8703b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8703b1ant_action_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8703b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, ap_enable = false, wifi_busy = false, - bt_busy = false; - boolean wifi_scan = false, wifi_link = false, wifi_roam = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); - - if ((wifi_link) || (wifi_roam) || (coex_sta->wifi_is_high_pri_task)) { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); - - } else if ((wifi_scan) && (coex_sta->bt_create_connection)) { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); - - } else if ((!wifi_connected) && (!wifi_scan)) { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (wifi_scan) { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - } else if (wifi_busy) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 19); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } -} - -void halbtc8703b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* tdma and coex table */ - - if (bt_link_info->sco_exist) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else { /* HID */ - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } -} - -void halbtc8703b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - - if (bt_link_info->hid_only) { /* HID */ - halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist, - wifi_status); - coex_dm->auto_tdma_adjust = false; - return; - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - - if (coex_sta->scan_ap_num >= - BT_8703B_1ANT_WIFI_NOISY_THRESH) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 17); - } else { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 7); - } - - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = true; - } - } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255)) - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 15); - else - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - } else - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = false; - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8); - coex_dm->auto_tdma_adjust = false; - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && - bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - if (BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 4); - else - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = false; - } else { - /* BT no-profile busy (0x9) */ - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } -} - -void halbtc8703b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - - /* tdma and coex table */ - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8703b1ant_action_wifi_not_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if (num_of_wifi_link >= 2) { - halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_action_bt_inquiry(btcoexist); - } else - halbtc8703b1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8703b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8703b1ant_action_hs(btcoexist); - return; - } - - /* tdma and coex table */ - if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8703b1ant_action_wifi_not_connected_asso_auth( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if (num_of_wifi_link >= 2) { - halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_action_bt_inquiry(btcoexist); - } else - halbtc8703b1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8703b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8703b1ant_action_hs(btcoexist); - return; - } - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2); - } -} - -void halbtc8703b1ant_action_wifi_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if (num_of_wifi_link >= 2) { - halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_action_bt_inquiry(btcoexist); - } else - halbtc8703b1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8703b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8703b1ant_action_hs(btcoexist); - return; - } - - /* tdma and coex table */ - if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8703b1ant_action_wifi_connected_specific_packet( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - boolean wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if (num_of_wifi_link >= 2) { - halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_action_bt_inquiry(btcoexist); - } else - halbtc8703b1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8703b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8703b1ant_action_hs(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* no specific packet process for both WiFi and BT very busy */ - if ((wifi_busy) && ((bt_link_info->pan_exist) || - (coex_sta->num_of_profile >= 2))) - return; - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else if (bt_link_info->a2dp_exist) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8703b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - boolean scan = false, link = false, roam = false; - boolean under_4way = false, ap_enable = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (under_4way) { - halbtc8703b1ant_action_wifi_connected_specific_packet(btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - if (scan) - halbtc8703b1ant_action_wifi_connected_scan(btcoexist); - else - halbtc8703b1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - - /* tdma and coex table */ - if (!wifi_busy) { - if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8703b1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else if ((BT_8703B_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8703b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - } - } else { - if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8703b1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else if ((BT_8703B_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else { - /* halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); */ - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8703b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - /* halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); */ - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } -} - -void halbtc8703b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - - algorithm = halbtc8703b1ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - - if (halbtc8703b1ant_is_common_action(btcoexist)) { - - } else { - switch (coex_dm->cur_algorithm) { - case BT_8703B_1ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - /* halbtc8703b1ant_action_sco(btcoexist); */ - break; - case BT_8703B_1ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8703b1ant_action_hid(btcoexist); */ - break; - case BT_8703B_1ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8703b1ant_action_a2dp(btcoexist); */ - break; - case BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - /* halbtc8703b1ant_action_a2dp_pan_hs(btcoexist); */ - break; - case BT_8703B_1ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - /* halbtc8703b1ant_action_pan_edr(btcoexist); */ - break; - case BT_8703B_1ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - /* halbtc8703b1ant_action_pan_hs(btcoexist); */ - break; - case BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8703b1ant_action_pan_edr_a2dp(btcoexist); */ - break; - case BT_8703B_1ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8703b1ant_action_pan_edr_hid(btcoexist); */ - break; - case BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - /* halbtc8703b1ant_action_hid_a2dp_pan_edr(btcoexist); */ - break; - case BT_8703B_1ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8703b1ant_action_hid_a2dp(btcoexist); */ - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8703b1ant_coex_all_off(btcoexist); */ - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8703b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - boolean miracast_plus_bt = false; - u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0, wifi_bw; - u8 iot_peer = BTC_IOT_PEER_UNKNOWN; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_action_bt_whck_test(btcoexist); - return; - } - - if (coex_sta->bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!!\n"); - halbtc8703b1ant_action_wifi_only(btcoexist); - return; - } - - if ((BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) { - halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, - 0, 1); - miracast_plus_bt = true; - } else { - halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - miracast_plus_bt = false; - } - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_action_bt_inquiry(btcoexist); - } else - halbtc8703b1ant_action_wifi_multi_port(btcoexist); - - return; - } else { - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); - - if (BTC_IOT_PEER_CISCO != iot_peer) { - if (bt_link_info->sco_exist) /* if (bt_link_info->bt_hi_pri_link_exist) */ - halbtc8703b1ant_limited_rx(btcoexist, - NORMAL_EXEC, true, false, 0x5); - else - halbtc8703b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, false, 0x5); - } else { - if (bt_link_info->sco_exist) - halbtc8703b1ant_limited_rx(btcoexist, - NORMAL_EXEC, true, false, 0x5); - else { - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8703b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x10); - else - halbtc8703b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x8); - } - } - - halbtc8703b1ant_sw_mechanism(btcoexist, true); - halbtc8703b1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - } else { - halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x5); - - halbtc8703b1ant_sw_mechanism(btcoexist, false); - halbtc8703b1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8703b1ant_action_hs(btcoexist); - return; - } - - - if (!wifi_connected) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is non connected-idle !!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - if (scan) - halbtc8703b1ant_action_wifi_not_connected_scan( - btcoexist); - else - halbtc8703b1ant_action_wifi_not_connected_asso_auth( - btcoexist); - } else - halbtc8703b1ant_action_wifi_not_connected(btcoexist); - } else /* wifi LPS/Busy */ - halbtc8703b1ant_action_wifi_connected(btcoexist); -} - -u32 halbtc8703b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val) -{ - u8 j; - u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0; - u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200, - 174, 151, 132, 115, 100, 86, 74, 62, 51, 42, - 32, 23, 15, 7, 0 - }; - - if (val == 0) - return 0; - - tmp = val; - - while (1) { - if (tmp == 1) - break; - else { - tmp = (tmp >> 1); - shiftcount++; - } - } - - - val_integerd_b = shiftcount + 1; - - tmp2 = 1; - for (j = 1; j <= val_integerd_b; j++) - tmp2 = tmp2 * 2; - - tmp = (val * 100) / tmp2; - tindex = tmp / 5; - - if (tindex > 20) - tindex = 20; - - val_fractiond_b = table_fraction[tindex]; - - result = val_integerd_b * 100 - val_fractiond_b; - - return result; - - -} - -void halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - - /* sw all off */ - halbtc8703b1ant_sw_mechanism(btcoexist, false); - - /* halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ - /* halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */ - - coex_sta->pop_event_cnt = 0; -} - -void halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up, IN boolean wifi_only) -{ - u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0; - - u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70), - u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "\n [BTCoex], ********** 0x70/ 0x38/ 0x54 (Before Init HW config) = 0x%x/ 0x%x/ 0x%x**********\n", - u32tmp0, - u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - - /* BT report packet sample rate */ - btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); - - /* Enable BT counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - - /* Enable PTA (3-wire function form BT side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); - - /* Enable PTA (tx/rx signal form WiFi side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); - - halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, FALSE); - - if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) - halbtc8703b1ant_post_onoffState_to_bt(btcoexist, true); - - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - - /* Antenna config */ - if (wifi_only) { - coex_sta->concurrent_rx_mode_on = false; - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, true, false); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, false, false); - } else { - coex_sta->concurrent_rx_mode_on = true; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); - /* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, true, false); - } - - /* PTA parameter */ - halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70), - u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x70/ 0x38/ 0x54 (After Init HW config) = 0x%x/ 0x%x/ 0x%x**********\n", - u32tmp0, - u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - -} - - - -void halbtc8703b1ant_psd_showdata(IN struct btc_coexist *btcoexist) -{ - u8 *cli_buf = btcoexist->cli_buf; - u32 delta_freq_per_point; - u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n\n============[PSD info] (%d)============\n", - psd_scan->psd_gen_count); - CL_PRINTF(cli_buf); - - if (psd_scan->psd_gen_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n"); - CL_PRINTF(cli_buf); - return; - } - - if (psd_scan->psd_point == 0) - delta_freq_per_point = 0; - else - delta_freq_per_point = psd_scan->psd_band_width / - psd_scan->psd_point; - - /* if (psd_scan->is_psd_show_max_only) */ - if (0) { - psd_rep1 = psd_scan->psd_max_value / 100; - psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100; - - freq = ((psd_scan->real_cent_freq - 20) * 1000000 + - psd_scan->psd_max_value_point * delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq = %d.0%d MHz", - freq1, freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq = %d.%d MHz", - freq1, freq2); - - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - ", Value = %d.0%d dB, (%d)\n", - psd_rep1, psd_rep2, psd_scan->psd_max_value); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - ", Value = %d.%d dB, (%d)\n", - psd_rep1, psd_rep2, psd_scan->psd_max_value); - - CL_PRINTF(cli_buf); - } else { - m = psd_scan->psd_start_point; - n = psd_scan->psd_start_point; - i = 1; - j = 1; - - while (1) { - do { - freq = ((psd_scan->real_cent_freq - 20) * 1000000 + m * - delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (i == 1) { - if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.000", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.0%2d", freq1, - freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.%3d", freq1, - freq2); - } else if ((i % 8 == 0) || - (m == psd_scan->psd_stop_point)) { - if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.000\n", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.0%2d\n", freq1, freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.%3d\n", freq1, freq2); - } else { - if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.000", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.0%2d", freq1, freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.%3d", freq1, freq2); - } - - i++; - m++; - CL_PRINTF(cli_buf); - - } while ((i <= 8) && (m <= psd_scan->psd_stop_point)); - - - do { - psd_rep1 = psd_scan->psd_report_max_hold[n] / 100; - psd_rep2 = psd_scan->psd_report_max_hold[n] - psd_rep1 * - 100; - - if (j == 1) { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Val %7d.0%d", psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Val %7d.%d", psd_rep1, - psd_rep2); - } else if ((j % 8 == 0) || - (n == psd_scan->psd_stop_point)) { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.0%d\n", psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.%d\n", psd_rep1, psd_rep2); - } else { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.0%d", psd_rep1, psd_rep2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.%d", psd_rep1, psd_rep2); - } - - j++; - n++; - CL_PRINTF(cli_buf); - - } while ((j <= 8) && (n <= psd_scan->psd_stop_point)); - - if ((m > psd_scan->psd_stop_point) || - (n > psd_scan->psd_stop_point)) - break; - else { - i = 1; - j = 1; - } - - } - } - - -} - -void halbtc8703b1ant_psd_maxholddata(IN struct btc_coexist *btcoexist, - IN u32 gen_count) -{ - u32 i = 0, i_max = 0, val_max = 0; - - if (gen_count == 1) { - memcpy(psd_scan->psd_report_max_hold, - psd_scan->psd_report, - BT_8703B_1ANT_ANTDET_PSD_POINTS * sizeof(u32)); - - for (i = psd_scan->psd_start_point; - i <= psd_scan->psd_stop_point; i++) { - - } - - psd_scan->psd_max_value_point = 0; - psd_scan->psd_max_value = 0; - - } else { - for (i = psd_scan->psd_start_point; - i <= psd_scan->psd_stop_point; i++) { - if (psd_scan->psd_report[i] > - psd_scan->psd_report_max_hold[i]) - psd_scan->psd_report_max_hold[i] = - psd_scan->psd_report[i]; - - /* search Max Value */ - if (i == psd_scan->psd_start_point) { - i_max = i; - val_max = psd_scan->psd_report_max_hold[i]; - } else { - if (psd_scan->psd_report_max_hold[i] > - val_max) { - i_max = i; - val_max = psd_scan->psd_report_max_hold[i]; - } - } - - - } - - psd_scan->psd_max_value_point = i_max; - psd_scan->psd_max_value = val_max; - - } - - -} - -u32 halbtc8703b1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) -{ - /* reg 0x808[9:0]: FFT data x */ - /* reg 0x808[22]: 0-->1 to get 1 FFT data y */ - /* reg 0x8b4[15:0]: FFT data y report */ - - u32 val = 0, psd_report = 0; - - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - - val &= 0xffbffc00; - val |= point; - - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - val |= 0x00400000; - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - - val = btcoexist->btc_read_4byte(btcoexist, 0x8b4); - - psd_report = val & 0x0000ffff; - - return psd_report; -} - - -boolean halbtc8703b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points, - IN u32 avgnum, IN u32 loopcnt) -{ - u32 i = 0, val = 0, n = 0, k = 0, j, point_index = 0; - u32 points1 = 0, psd_report = 0; - u32 start_p = 0, stop_p = 0, delta_freq_per_point = 156250; - u32 psd_center_freq = 20 * 10 ^ 6; - boolean outloop = false, scan , roam, is_sweep_ok = true; - u8 flag = 0; - u32 tmp = 0, u32tmp1 = 0; - u32 wifi_original_channel = 1; - - psd_scan->is_psd_running = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n"); - BTC_TRACE(trace_buf); - - do { - switch (flag) { - case 0: /* Get PSD parameters */ - default: - - psd_scan->psd_band_width = 40 * 1000000; - psd_scan->psd_point = points; - psd_scan->psd_start_base = points / 2; - psd_scan->psd_avg_num = avgnum; - psd_scan->real_cent_freq = cent_freq; - psd_scan->real_offset = offset; - psd_scan->real_span = span; - - - points1 = psd_scan->psd_point; - delta_freq_per_point = psd_scan->psd_band_width / - psd_scan->psd_point; - - /* PSD point setup */ - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - val &= 0xffff0fff; - - switch (psd_scan->psd_point) { - case 128: - val |= 0x0; - break; - case 256: - default: - val |= 0x00004000; - break; - case 512: - val |= 0x00008000; - break; - case 1024: - val |= 0x0000c000; - break; - } - - switch (psd_scan->psd_avg_num) { - case 1: - val |= 0x0; - break; - case 8: - val |= 0x00001000; - break; - case 16: - val |= 0x00002000; - break; - case 32: - default: - val |= 0x00003000; - break; - } - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - flag = 1; - break; - case 1: /* calculate the PSD point index from freq/offset/span */ - psd_center_freq = psd_scan->psd_band_width / 2 + - offset * (1000000); - - start_p = psd_scan->psd_start_base + (psd_center_freq - - span * (1000000) / 2) / delta_freq_per_point; - psd_scan->psd_start_point = start_p - - psd_scan->psd_start_base; - - stop_p = psd_scan->psd_start_base + (psd_center_freq + - span * (1000000) / 2) / delta_freq_per_point; - psd_scan->psd_stop_point = stop_p - - psd_scan->psd_start_base - 1; - - flag = 2; - break; - case 2: /* set RF channel/BW/Mode */ - - /* set 3-wire off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x88c); - val |= 0x00300000; - btcoexist->btc_write_4byte(btcoexist, 0x88c, val); - - /* CCK off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x800); - val &= 0xfeffffff; - btcoexist->btc_write_4byte(btcoexist, 0x800, val); - - /* Tx-pause on */ - btcoexist->btc_write_1byte(btcoexist, 0x522, 0x6f); - - /* store WiFi original channel */ - wifi_original_channel = btcoexist->btc_get_rf_reg( - btcoexist, BTC_RF_A, 0x18, 0x3ff); - - /* Set RF channel */ - if (cent_freq == 2484) - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, - 0x18, 0x3ff, 0xe); - else - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, - 0x18, 0x3ff, (cent_freq - 2412) / 5 + - 1); /* WiFi TRx Mask on */ - - /* save original RCK value */ - u32tmp1 = btcoexist->btc_get_rf_reg( - btcoexist, BTC_RF_A, 0x1d, 0xfffff); - - /* Enter debug mode */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde, - 0x2, 0x1); - - /* Set RF Rx filter corner */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d, - 0xfffff, 0x2e); - - - /* Set RF mode = Rx, RF Gain = 0x320a0 */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0, - 0xfffff, 0x320a0); - - while (1) { - if (k++ > BT_8703B_1ANT_ANTDET_SWEEPPOINT_DELAY) - break; - } - flag = 3; - break; - case 3: - psd_scan->psd_gen_count = 0; - for (j = 1; j <= loopcnt; j++) { - - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || roam) { - is_sweep_ok = false; - break; - } - memset(psd_scan->psd_report, 0, - psd_scan->psd_point * sizeof(u32)); - start_p = psd_scan->psd_start_point + - psd_scan->psd_start_base; - stop_p = psd_scan->psd_stop_point + - psd_scan->psd_start_base + 1; - - i = start_p; - point_index = 0; - - while (i < stop_p) { - if (i >= points1) - psd_report = - halbtc8703b1ant_psd_getdata( - btcoexist, i - points1); - else - psd_report = - halbtc8703b1ant_psd_getdata( - btcoexist, i); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Point=%d, psd_raw_data = 0x%08x\n", - i, psd_report); - BTC_TRACE(trace_buf); - if (psd_report == 0) - tmp = 0; - else - /* tmp = 20*log10((double)psd_report); */ - /* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */ - tmp = 6 * halbtc8703b1ant_psd_log2base( - btcoexist, psd_report); - - n = i - psd_scan->psd_start_base; - psd_scan->psd_report[n] = tmp; - - - halbtc8703b1ant_psd_maxholddata( - btcoexist, j); - - i++; - - } - - psd_scan->psd_gen_count = j; - } - - flag = 100; - break; - case 99: /* error */ - - outloop = true; - break; - case 100: /* recovery */ - - /* set 3-wire on */ - val = btcoexist->btc_read_4byte(btcoexist, 0x88c); - val &= 0xffcfffff; - btcoexist->btc_write_4byte(btcoexist, 0x88c, val); - - /* CCK on */ - val = btcoexist->btc_read_4byte(btcoexist, 0x800); - val |= 0x01000000; - btcoexist->btc_write_4byte(btcoexist, 0x800, val); - - /* Tx-pause off */ - btcoexist->btc_write_1byte(btcoexist, 0x522, 0x0); - - /* PSD off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - val &= 0xffbfffff; - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - /* restore RF Rx filter corner */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d, - 0xfffff, u32tmp1); - - /* Exit debug mode */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde, - 0x2, 0x0); - - /* restore WiFi original channel */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18, - 0x3ff, wifi_original_channel); - - outloop = true; - break; - - } - - } while (!outloop); - - - - psd_scan->is_psd_running = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n"); - BTC_TRACE(trace_buf); - return is_sweep_ok; - -} - -/* ************************************************************ - * work around function start with wa_halbtc8703b1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8703b1ant_ - * ************************************************************ */ -void ex_halbtc8703b1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x0; - u16 u16tmp = 0x0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Execute 8703b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Ant Det Finish = %s, Ant Det Number = %d\n", - (board_info->btdm_ant_det_finish ? "Yes" : "No"), - board_info->btdm_ant_num_by_ant_det); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = true; - - /* enable BB, REG_SYS_FUNC_EN such that we can write BB/MAC reg correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - - /* set Path control owner to WiFi */ - halbtc8703b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8703B_1ANT_PCO_WLSIDE); - - /* set GNT_BT to high */ - halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to low */ - halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_LOW); - - /* set WLAN_ACT = 0 */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, FALSE); - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - - u8tmp = 0; - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - - if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); - - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x70(MAC)/0x38/0x54 (Power-On) =0x%x/ 0x%x/ 0x%x**********\n", - btcoexist->btc_read_4byte(btcoexist, 0x70), - halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38), - halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54)); - BTC_TRACE(trace_buf); - - -} - -void ex_halbtc8703b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8703b1ant_init_hw_config(btcoexist, true, wifi_only); - btcoexist->stop_coex_dm = false; -} - -void ex_halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8703b1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fa_of_dm, fa_cck; - u32 fw_ver = 0, bt_patch_ver = 0; - static u8 pop_report_in_10s = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - if (psd_scan->ant_det_try_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", - "Ant PG Num/ Mech/ Pos", - board_info->pg_ant_num, board_info->btdm_ant_num, - board_info->btdm_ant_pos); - CL_PRINTF(cli_buf); - } else { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %d (%d/%d/%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos", - board_info->pg_ant_num, board_info->btdm_ant_num_by_ant_det, - board_info->btdm_ant_pos, - psd_scan->ant_det_try_count, psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); - CL_PRINTF(cli_buf); - - if (board_info->btdm_ant_det_finish) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - CL_PRINTF(cli_buf); - } - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", - "BT stack/ hci ext ver", - ((stack_info->profile_notified) ? "Yes" : "No"), - stack_info->hci_version); - CL_PRINTF(cli_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c", - "Version Coex/ Fw/ Patch/ Cut", - glcoex_ver_date_8703b_1ant, glcoex_ver_8703b_1ant, fw_ver, - bt_patch_ver, bt_patch_ver, coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", - "WifibHiPri/ Ccklock/ CckEverLock", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), - (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No")); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") - : ((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); - CL_PRINTF(cli_buf); - - if (pop_report_in_10s >= 5) { - coex_sta->pop_event_cnt = 0; - pop_report_in_10s = 0; - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d / %d / %d / %d / %d", - "SCO/HID/PAN/A2DP/Hi-Pri", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist, - bt_link_info->bt_hi_pri_link_exist); - CL_PRINTF(cli_buf); - - if (stack_info->profile_notified) - btcoexist->btc_disp_dbg_msg(btcoexist, - BTC_DBG_DISP_BT_LINK_INFO); - else { - bt_info_ext = coex_sta->bt_info_ext; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s / %d", - "Role/A2DP Rate/Bitpool", - ((bt_link_info->slave_role) ? "Slave" : "Master"), - (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool); - CL_PRINTF(cli_buf); - } - - - for (i = 0; i < BT_INFO_SRC_8703B_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8703b_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms] (before Manual)============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "SM[LowPenaltyRA]", - coex_dm->cur_low_penalty_ra); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "On" : "Off"), - (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); - - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "WL/BT Coex Table Type", - coex_sta->coex_table_type); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x778/0x6cc/IgnWlanAct", - u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa0); - u32tmp[1] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "LTE Coex Table W_L/B_L", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa8); - u32tmp[1] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xac); - u32tmp[2] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb0); - u32tmp[3] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "LTE Break Table W_L/B_L/L_W/L_B", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, - u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); - CL_PRINTF(cli_buf); - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - - u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s", - "LTE CoexOn/Path Ctrl Owner", - (int)((u32tmp[0] & BIT(7)) >> 7), ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "LTE 3Wire/OPMode/UART/UARTMode", - (int)((u32tmp[0] & BIT(6)) >> 6), (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), - (int)((u32tmp[0] & BIT(3)) >> 3), - (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s", - "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg", - (int)((u32tmp[0] & BIT(12)) >> 12), (int)((u32tmp[0] & BIT(14)) >> 14), - ((u8tmp[0] & BIT(3)) ? "On" : "Off")); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "GNT_WL/GNT_BT/LTE_Busy/UART_Busy", - (int)((u32tmp[0] & BIT(2)) >> 2), (int)((u32tmp[0] & BIT(3)) >> 3), - (int)((u32tmp[0] & BIT(1)) >> 1), (int)(u32tmp[0] & BIT(0))); - CL_PRINTF(cli_buf); - - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x4c6[4]/0x40[5] (WL/BT PTA)", - (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5)); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s", - "0x550(bcn ctrl)/0x522/4-RxAGC", - u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off"); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8); - u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c); - - fa_of_dm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000) - >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) + - ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] & - 0xffff) ; - fa_cck = (u8tmp[0] << 8) + u8tmp[1]; - - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0xc50/OFDM-CCA/OFDM-FA/CCK-FA", - u32tmp[1] & 0xff, u32tmp[0] & 0xffff, fa_of_dm, fa_cck); - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-Agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-Agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); - - halbtc8703b1ant_read_score_board(btcoexist, &u16tmp[0]); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x", - "ScoreBoard[14:0] (from BT)", u16tmp[0]); - CL_PRINTF(cli_buf); - - - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8703b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - coex_sta->under_lps = false; - - /* Write WL "Active" in Score-board for LPS off */ - halbtc8703b1ant_post_activestate_to_bt(btcoexist, false); - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_post_activestate_to_bt(btcoexist, true); - - halbtc8703b1ant_init_hw_config(btcoexist, false, false); - halbtc8703b1ant_init_coex_dm(btcoexist); - halbtc8703b1ant_query_bt_info(btcoexist); - - coex_sta->under_ips = false; - } -} - -void ex_halbtc8703b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - coex_sta->under_ips = false; - - if (coex_sta->force_lps_on == true) { /* LPS No-32K */ - /* Write WL "Active" in Score-board for PS-TDMA */ - halbtc8703b1ant_post_activestate_to_bt(btcoexist, true); - - } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ - /* Write WL "Non-Active" in Score-board for Native-PS */ - halbtc8703b1ant_post_activestate_to_bt(btcoexist, false); - - } - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - - - /* Write WL "Active" in Score-board for LPS off */ - halbtc8703b1ant_post_activestate_to_bt(btcoexist, true); - - } -} - -void ex_halbtc8703b1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - halbtc8703b1ant_query_bt_info(btcoexist); - - if (BTC_SCAN_START == type) { - - coex_sta->wifi_is_high_pri_task = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_post_activestate_to_bt(btcoexist, true); - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); - - /* Force antenna setup for no scan result issue */ - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - - if (!wifi_connected) /* non-connected scan */ - halbtc8703b1ant_action_wifi_not_connected_scan(btcoexist); - else /* wifi is connected */ - halbtc8703b1ant_action_wifi_connected_scan(btcoexist); - - } else { - - coex_sta->wifi_is_high_pri_task = false; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", coex_sta->scan_ap_num); - BTC_TRACE(trace_buf); - - if (!wifi_connected) - halbtc8703b1ant_action_wifi_not_connected(btcoexist); - else - halbtc8703b1ant_action_wifi_connected(btcoexist); - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START Notify() end\n"); - BTC_TRACE(trace_buf); - -} - -void ex_halbtc8703b1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - if (BTC_ASSOCIATE_START == type) { - coex_sta->wifi_is_high_pri_task = true; - halbtc8703b1ant_post_activestate_to_bt(btcoexist, true); - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); - - /* Force antenna setup for no scan result issue */ - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - /* psd_scan->ant_det_is_ant_det_available = TRUE; */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - - halbtc8703b1ant_action_wifi_not_connected_asso_auth(btcoexist); - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - - if (!wifi_connected) /* non-connected scan */ - halbtc8703b1ant_action_wifi_not_connected(btcoexist); - else - halbtc8703b1ant_action_wifi_connected(btcoexist); - } - -} - -void ex_halbtc8703b1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_under_b_mode = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_MEDIA_CONNECT == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_post_activestate_to_bt(btcoexist, true); - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); - - /* Force antenna setup for no scan result issue */ - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - /* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */ - /* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_post_activestate_to_bt(btcoexist, false); - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - - coex_sta->cck_ever_lock = false; - } - - halbtc8703b1ant_update_wifi_channel_info(btcoexist, type); - -} - -void ex_halbtc8703b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean under_4way = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (under_4way) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ---- under_4way!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - } else if (BTC_PACKET_ARP == type) { - - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify -cnt = %d\n", coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", type); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - } - - if (coex_sta->wifi_is_high_pri_task) - halbtc8703b1ant_action_wifi_connected_specific_packet(btcoexist); -} - -void ex_halbtc8703b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean bt_busy = false; - - coex_sta->c2h_bt_info_req_sent = false; - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8703B_1ANT_MAX) - rsp_source = BT_INFO_SRC_8703B_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (BT_INFO_SRC_8703B_1ANT_WIFI_FW != rsp_source) { - - /* if 0xff, it means BT is under WHCK test */ - if (bt_info == 0xff) - coex_sta->bt_whck_test = true; - else - coex_sta->bt_whck_test = false; - - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_page = true; - else - coex_sta->c2h_bt_page = false; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x80) - coex_sta->bt_create_connection = true; - else - coex_sta->bt_create_connection = false; - - /* unit: %, value-100 to translate to unit: dBm */ - coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */ - - if ((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) { - coex_sta->a2dp_bit_pool = - coex_sta->bt_info_c2h[rsp_source][6]; - } else - coex_sta->a2dp_bit_pool = 0; - - if (coex_sta->bt_info_c2h[rsp_source][1] & 0x9) - coex_sta->acl_busy = true; - else - coex_sta->acl_busy = false; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - - if ((!btcoexist->manual_control) && (!btcoexist->stop_coex_dm)) { - - /* Re-Init */ - if (coex_sta->bt_info_ext & BIT(1)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - halbtc8703b1ant_update_wifi_channel_info(btcoexist, - BTC_MEDIA_CONNECT); - else - halbtc8703b1ant_update_wifi_channel_info(btcoexist, - BTC_MEDIA_DISCONNECT); - } - - /* If Ignore_WLanAct && not SetUp_Link */ - if ((coex_sta->bt_info_ext & BIT(3)) && (!(coex_sta->bt_info_ext & BIT(2)))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8703B_1ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - } - - coex_sta->num_of_profile = 0; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8703B_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - - coex_sta->bt_hi_pri_link_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8703B_1ANT_B_FTP) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8703B_1ANT_B_A2DP) { - coex_sta->a2dp_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8703B_1ANT_B_HID) { - coex_sta->hid_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) { - coex_sta->sco_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = false; - - } - - - - halbtc8703b1ant_update_bt_link_info(btcoexist); - - bt_info = bt_info & - 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ - - if (!(bt_info & BT_INFO_8703B_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8703B_1ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8703B_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8703B_1ANT_B_ACL_BUSY) { - if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) - coex_dm->auto_tdma_adjust = false; - coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), No run_coexist_mechanism return for Manual CTRL<===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), No run_coexist_mechanism return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - /* don't run coex mechanism while receve BTInfo if GNT_WL/GNT_BT control by SW */ - if (!coex_sta->gnt_control_by_PTA) - return; - - halbtc8703b1ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8703b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->wl_rf_off_on_event = true; - btcoexist->stop_coex_dm = false; - - halbtc8703b1ant_post_activestate_to_bt(btcoexist, true); - halbtc8703b1ant_post_onoffState_to_bt(btcoexist, true); - - /* halbtc8703b1ant_init_hw_config(btcoexist, false, false); */ - } else if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_post_activestate_to_bt(btcoexist, false); - halbtc8703b1ant_post_onoffState_to_bt(btcoexist, false); - - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - - btcoexist->stop_coex_dm = true; - coex_sta->wl_rf_off_on_event = false; - - } -} - -void ex_halbtc8703b1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_post_activestate_to_bt(btcoexist, false); - halbtc8703b1ant_post_onoffState_to_bt(btcoexist, false); - - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, - false, true); - - ex_halbtc8703b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, FALSE); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8703b1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_post_activestate_to_bt(btcoexist, false); - halbtc8703b1ant_post_onoffState_to_bt(btcoexist, false); - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_post_activestate_to_bt(btcoexist, true); - halbtc8703b1ant_post_onoffState_to_bt(btcoexist, true); - - btcoexist->stop_coex_dm = false; - } -} - -void ex_halbtc8703b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], *****************Coex DM Reset*****************\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_init_hw_config(btcoexist, false, false); - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); */ - halbtc8703b1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8703b1ant_periodical(IN struct btc_coexist *btcoexist) -{ - -#if (BT_AUTO_REPORT_ONLY_8703B_1ANT == 0) - halbtc8703b1ant_query_bt_info(btcoexist); -#endif - - halbtc8703b1ant_monitor_bt_ctr(btcoexist); - halbtc8703b1ant_monitor_wifi_ctr(btcoexist); - - halbtc8703b1ant_monitor_bt_enable_disable(btcoexist); - - /* for 4-way, DHCP, EAPOL packet */ - if (coex_sta->specific_pkt_period_cnt > 0) { - - coex_sta->specific_pkt_period_cnt--; - - if ((coex_sta->specific_pkt_period_cnt == 0) && (coex_sta->wifi_is_high_pri_task)) - coex_sta->wifi_is_high_pri_task = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", (coex_sta->wifi_is_high_pri_task ? "Yes" : "No")); - BTC_TRACE(trace_buf); - - } - - if (halbtc8703b1ant_is_wifibt_status_changed(btcoexist)) - halbtc8703b1ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8703b1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - /* No Antenna Detection required because 8730b is only 1-Ant */ -} - -void ex_halbtc8703b1ant_antenna_isolation(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - - -} - -void ex_halbtc8703b1ant_psd_scan(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - - -} - -void ex_halbtc8703b1ant_display_ant_detection(IN struct btc_coexist *btcoexist) -{ - -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ diff --git a/hal/btc/HalBtc8703b1Ant.h b/hal/btc/HalBtc8703b1Ant.h deleted file mode 100644 index cf167a5..0000000 --- a/hal/btc/HalBtc8703b1Ant.h +++ /dev/null @@ -1,348 +0,0 @@ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8703B_SUPPORT == 1) -/* ******************************************* - * The following is for 8703B 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8703B_1ANT 1 -#define BT_8703B_1ANT_ENABLE_GNTBT_TO_GPIO14 0 - -#define BT_INFO_8703B_1ANT_B_FTP BIT(7) -#define BT_INFO_8703B_1ANT_B_A2DP BIT(6) -#define BT_INFO_8703B_1ANT_B_HID BIT(5) -#define BT_INFO_8703B_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8703B_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8703B_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8703B_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8703B_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8703B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT 2 - -#define BT_8703B_1ANT_WIFI_NOISY_THRESH 50 /* max: 255 */ - -/* for Antenna detection */ -#define BT_8703B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 -#define BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 -#define BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 -#define BT_8703B_1ANT_ANTDET_PSDTHRES_1ANT 35 -#define BT_8703B_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8703B_1ANT_ANTDET_SWEEPPOINT_DELAY 40000 -#define BT_8703B_1ANT_ANTDET_ENABLE 0 -#define BT_8703B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0 - -#define BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 - -enum bt_8703b_1ant_signal_state { - BT_8703B_1ANT_SIG_STA_SET_TO_LOW = 0x0, - BT_8703B_1ANT_SIG_STA_SET_BY_HW = 0x0, - BT_8703B_1ANT_SIG_STA_SET_TO_HIGH = 0x1, - BT_8703B_1ANT_SIG_STA_MAX -}; - -enum bt_8703b_1ant_path_ctrl_owner { - BT_8703B_1ANT_PCO_BTSIDE = 0x0, - BT_8703B_1ANT_PCO_WLSIDE = 0x1, - BT_8703B_1ANT_PCO_MAX -}; - -enum bt_8703b_1ant_gnt_ctrl_type { - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW = 0x1, - BT_8703B_1ANT_GNT_TYPE_MAX -}; - -enum bt_8703b_1ant_gnt_ctrl_block { - BT_8703B_1ANT_GNT_BLOCK_RFC_BB = 0x0, - BT_8703B_1ANT_GNT_BLOCK_RFC = 0x1, - BT_8703B_1ANT_GNT_BLOCK_BB = 0x2, - BT_8703B_1ANT_GNT_BLOCK_MAX -}; - -enum bt_8703b_1ant_lte_coex_table_type { - BT_8703B_1ANT_CTT_WL_VS_LTE = 0x0, - BT_8703B_1ANT_CTT_BT_VS_LTE = 0x1, - BT_8703B_1ANT_CTT_MAX -}; - -enum bt_8703b_1ant_lte_break_table_type { - BT_8703B_1ANT_LBTT_WL_BREAK_LTE = 0x0, - BT_8703B_1ANT_LBTT_BT_BREAK_LTE = 0x1, - BT_8703B_1ANT_LBTT_LTE_BREAK_WL = 0x2, - BT_8703B_1ANT_LBTT_LTE_BREAK_BT = 0x3, - BT_8703B_1ANT_LBTT_MAX -}; - -enum bt_info_src_8703b_1ant { - BT_INFO_SRC_8703B_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8703B_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8703B_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8703B_1ANT_MAX -}; - -enum bt_8703b_1ant_bt_status { - BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8703B_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8703B_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8703B_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8703B_1ANT_BT_STATUS_MAX -}; - -enum bt_8703b_1ant_wifi_status { - BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8703B_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8703b_1ant_coex_algo { - BT_8703B_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8703B_1ANT_COEX_ALGO_SCO = 0x1, - BT_8703B_1ANT_COEX_ALGO_HID = 0x2, - BT_8703B_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8703B_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8703B_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8703B_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8703B_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8703B_1ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8703b_1ant { - /* hw setting */ - u8 pre_ant_pos_type; - u8 cur_ant_pos_type; - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u8 error_condition; -}; - -struct coex_sta_8703b_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - boolean bt_hi_pri_link_exist; - u8 num_of_profile; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - s8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8703B_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8703B_1ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - u8 bt_retry_cnt; - u8 bt_info_ext; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_agg; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_agg; - - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; - u8 coex_table_type; - - boolean force_lps_on; - u32 wrong_profile_notification; - - boolean concurrent_rx_mode_on; - - u16 score_board; - - u8 a2dp_bit_pool; - u8 cut_version; - boolean acl_busy; - boolean wl_rf_off_on_event; - boolean bt_create_connection; - boolean gnt_control_by_PTA; -}; - -#define BT_8703B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ -#define BT_8703B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ -#define BT_8703B_1ANT_ANTDET_BUF_LEN 16 - -struct psdscan_sta_8703b_1ant { - - u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ - u32 ant_det_bt_tx_time; - u32 ant_det_pre_psdscan_peak_val; - boolean ant_det_is_ant_det_available; - u32 ant_det_psd_scan_peak_val; - boolean ant_det_is_btreply_available; - u32 ant_det_psd_scan_peak_freq; - - u8 ant_det_result; - u8 ant_det_peak_val[BT_8703B_1ANT_ANTDET_BUF_LEN]; - u8 ant_det_peak_freq[BT_8703B_1ANT_ANTDET_BUF_LEN]; - u32 ant_det_try_count; - u32 ant_det_fail_count; - u32 ant_det_inteval_count; - u32 ant_det_thres_offset; - - u32 real_cent_freq; - s32 real_offset; - u32 real_span; - - u32 psd_band_width; /* unit: Hz */ - u32 psd_point; /* 128/256/512/1024 */ - u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_start_point; - u32 psd_stop_point; - u32 psd_max_value_point; - u32 psd_max_value; - u32 psd_start_base; - u32 psd_avg_num; /* 1/8/16/32 */ - u32 psd_gen_count; - boolean is_psd_running; - boolean is_psd_show_max_only; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8703b1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8703b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8703b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8703b1ant_antenna_isolation(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); - -void ex_halbtc8703b1ant_psd_scan(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8703b1ant_display_ant_detection(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8703b1ant_power_on_setting(btcoexist) -#define ex_halbtc8703b1ant_pre_load_firmware(btcoexist) -#define ex_halbtc8703b1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8703b1ant_init_coex_dm(btcoexist) -#define ex_halbtc8703b1ant_ips_notify(btcoexist, type) -#define ex_halbtc8703b1ant_lps_notify(btcoexist, type) -#define ex_halbtc8703b1ant_scan_notify(btcoexist, type) -#define ex_halbtc8703b1ant_connect_notify(btcoexist, type) -#define ex_halbtc8703b1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8703b1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8703b1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8703b1ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8703b1ant_halt_notify(btcoexist) -#define ex_halbtc8703b1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8703b1ant_coex_dm_reset(btcoexist) -#define ex_halbtc8703b1ant_periodical(btcoexist) -#define ex_halbtc8703b1ant_display_coex_info(btcoexist) -#define ex_halbtc8703b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8703b1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8703b1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8703b1ant_display_ant_detection(btcoexist) - -#endif - - -#endif diff --git a/hal/btc/HalBtc8723a1Ant.c b/hal/btc/HalBtc8723a1Ant.c deleted file mode 100644 index 5883a37..0000000 --- a/hal/btc/HalBtc8723a1Ant.c +++ /dev/null @@ -1,1544 +0,0 @@ -//============================================================ -// Description: -// -// This file is for RTL8723A Co-exist mechanism -// -// History -// 2012/08/22 Cosa first check in. -// 2012/11/14 Cosa Revise for 8723A 1Ant out sourcing. -// -//============================================================ - -//============================================================ -// include files -//============================================================ -#include "Mp_Precomp.h" - -#if WPP_SOFTWARE_TRACE -#include "HalBtc8723a1Ant.tmh" -#endif - -#if(BT_30_SUPPORT == 1) -//============================================================ -// Global variables, these are static variables -//============================================================ -static COEX_DM_8723A_1ANT GLCoexDm8723a1Ant; -static PCOEX_DM_8723A_1ANT pCoexDm=&GLCoexDm8723a1Ant; -static COEX_STA_8723A_1ANT GLCoexSta8723a1Ant; -static PCOEX_STA_8723A_1ANT pCoexSta=&GLCoexSta8723a1Ant; - -const char *const GLBtInfoSrc8723a1Ant[]={ - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -//============================================================ -// local function proto type if needed -//============================================================ -//============================================================ -// local function start with halbtc8723a1ant_ -//============================================================ -VOID -halbtc8723a1ant_Reg0x550Bit3( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bSet - ) -{ - u1Byte u1tmp=0; - - u1tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x550); - if(bSet) - { - u1tmp |= BIT3; - } - else - { - u1tmp &= ~BIT3; - } - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x550, u1tmp); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set 0x550[3]=%d\n", (bSet? 1:0))); -} - -VOID -halbtc8723a1ant_NotifyFwScan( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte scanType - ) -{ - u1Byte H2C_Parameter[1] ={0}; - - if(BTC_SCAN_START == scanType) - H2C_Parameter[0] = 0x1; - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Notify FW for wifi scan, write 0x3b=0x%x\n", - H2C_Parameter[0])); - - pBtCoexist->fBtcFillH2c(pBtCoexist, 0x3b, 1, H2C_Parameter); -} - -VOID -halbtc8723a1ant_QueryBtInfo( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte H2C_Parameter[1] ={0}; - - pCoexSta->bC2hBtInfoReqSent = TRUE; - - H2C_Parameter[0] |= BIT0; // trigger - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x38=0x%x\n", - H2C_Parameter[0])); - - pBtCoexist->fBtcFillH2c(pBtCoexist, 0x38, 1, H2C_Parameter); -} - -VOID -halbtc8723a1ant_SetSwRfRxLpfCorner( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bRxRfShrinkOn - ) -{ - if(bRxRfShrinkOn) - { - //Shrink RF Rx LPF corner - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf0ff7); - } - else - { - //Resume RF Rx LPF corner - // After initialized, we can use pCoexDm->btRf0x1eBackup - if(pBtCoexist->bInitilized) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); - } - } -} - -VOID -halbtc8723a1ant_RfShrink( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bRxRfShrinkOn - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", - (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); - pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; - - if(!bForceExec) - { - if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) - return; - } - halbtc8723a1ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); - - pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; -} - -VOID -halbtc8723a1ant_SetSwPenaltyTxRateAdaptive( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bLowPenaltyRa - ) -{ - u1Byte tmpU1; - - tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd); - tmpU1 |= BIT0; - if(bLowPenaltyRa) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n")); - tmpU1 &= ~BIT2; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n")); - tmpU1 |= BIT2; - } - - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1); -} - -VOID -halbtc8723a1ant_LowPenaltyRa( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bLowPenaltyRa - ) -{ - return; - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", - (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); - pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; - - if(!bForceExec) - { - if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) - return; - } - halbtc8723a1ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); - - pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; -} - -VOID -halbtc8723a1ant_SetCoexTable( - IN PBTC_COEXIST pBtCoexist, - IN u4Byte val0x6c0, - IN u4Byte val0x6c8, - IN u1Byte val0x6cc - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); -} - -VOID -halbtc8723a1ant_CoexTable( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN u4Byte val0x6c0, - IN u4Byte val0x6c8, - IN u1Byte val0x6cc - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", - (bForceExec? "force to":""), val0x6c0, val0x6c8, val0x6cc)); - pCoexDm->curVal0x6c0 = val0x6c0; - pCoexDm->curVal0x6c8 = val0x6c8; - pCoexDm->curVal0x6cc = val0x6cc; - - if(!bForceExec) - { - if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && - (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && - (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) - return; - } - halbtc8723a1ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c8, val0x6cc); - - pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; - pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; - pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; -} - -VOID -halbtc8723a1ant_SetFwIgnoreWlanAct( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bEnable - ) -{ - u1Byte H2C_Parameter[1] ={0}; - - if(bEnable) - { - H2C_Parameter[0] |= BIT0; // function enable - } - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x25=0x%x\n", - H2C_Parameter[0])); - - pBtCoexist->fBtcFillH2c(pBtCoexist, 0x25, 1, H2C_Parameter); -} - -VOID -halbtc8723a1ant_IgnoreWlanAct( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bEnable - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", - (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); - pCoexDm->bCurIgnoreWlanAct = bEnable; - - if(!bForceExec) - { - if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) - return; - } - halbtc8723a1ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); - - pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; -} - -VOID -halbtc8723a1ant_SetFwPstdma( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type, - IN u1Byte byte1, - IN u1Byte byte2, - IN u1Byte byte3, - IN u1Byte byte4, - IN u1Byte byte5 - ) -{ - u1Byte H2C_Parameter[5] ={0}; - u1Byte realByte1=byte1, realByte5=byte5; - BOOLEAN bApEnable=FALSE; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); - - // byte1[1:0] != 0 means enable pstdma - // for 2Ant bt coexist, if byte1 != 0 means enable pstdma - if(byte1) - { - if(bApEnable) - { - if(type != 5 && type != 12) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW for 1Ant AP mode\n")); - realByte1 &= ~BIT4; - realByte1 |= BIT5; - - realByte5 |= BIT5; - realByte5 &= ~BIT6; - } - } - } - H2C_Parameter[0] = realByte1; - H2C_Parameter[1] = byte2; - H2C_Parameter[2] = byte3; - H2C_Parameter[3] = byte4; - H2C_Parameter[4] = realByte5; - - pCoexDm->psTdmaPara[0] = realByte1; - pCoexDm->psTdmaPara[1] = byte2; - pCoexDm->psTdmaPara[2] = byte3; - pCoexDm->psTdmaPara[3] = byte4; - pCoexDm->psTdmaPara[4] = realByte5; - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x3a(5bytes)=0x%x%08x\n", - H2C_Parameter[0], - H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); - - pBtCoexist->fBtcFillH2c(pBtCoexist, 0x3a, 5, H2C_Parameter); -} - -VOID -halbtc8723a1ant_PsTdma( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bTurnOn, - IN u1Byte type - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn %s PS TDMA, type=%d\n", - (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type)); - pCoexDm->bCurPsTdmaOn = bTurnOn; - pCoexDm->curPsTdma = type; - - if(!bForceExec) - { - if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && - (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) - return; - } - if(pCoexDm->bCurPsTdmaOn) - { - switch(pCoexDm->curPsTdma) - { - case 1: - default: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x1a, 0x1a, 0x0, 0x40); - break; - case 2: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x12, 0x12, 0x0, 0x40); - break; - case 3: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x3f, 0x3, 0x10, 0x40); - break; - case 4: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x15, 0x3, 0x10, 0x0); - break; - case 5: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0xa9, 0x15, 0x3, 0x35, 0xc0); - break; - - case 8: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x25, 0x3, 0x10, 0x0); - break; - case 9: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0xa, 0xa, 0x0, 0x40); - break; - case 10: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0xa, 0xa, 0x0, 0x40); - break; - case 11: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x5, 0x5, 0x0, 0x40); - break; - case 12: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0xa9, 0xa, 0x3, 0x15, 0xc0); - break; - - case 18: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x25, 0x3, 0x10, 0x0); - break; - - case 20: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x2a, 0x2a, 0x0, 0x0); - break; - case 21: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x20, 0x3, 0x10, 0x40); - break; - case 22: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x1a, 0x1a, 0x2, 0x40); - break; - case 23: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x12, 0x12, 0x2, 0x40); - break; - case 24: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0xa, 0xa, 0x2, 0x40); - break; - case 25: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x5, 0x5, 0x2, 0x40); - break; - case 26: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x25, 0x3, 0x10, 0x0); - break; - case 27: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x5, 0x5, 0x2, 0x40); - break; - case 28: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x3, 0x2f, 0x2f, 0x0, 0x0); - break; - - } - } - else - { - // disable PS tdma - switch(pCoexDm->curPsTdma) - { - case 8: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x8, 0x0, 0x0, 0x0, 0x0); - break; - case 0: - default: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x0, 0x0, 0x0, 0x0, 0x0); - pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x860, 0x210); - break; - case 9: - halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x0, 0x0, 0x0, 0x0, 0x0); - pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x860, 0x110); - break; - - } - } - - // update pre state - pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; - pCoexDm->prePsTdma = pCoexDm->curPsTdma; -} - - -VOID -halbtc8723a1ant_CoexAllOff( - IN PBTC_COEXIST pBtCoexist - ) -{ - // fw all off - halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - - // sw all off - halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); - - // hw all off - halbtc8723a1ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); -} - -VOID -halbtc8723a1ant_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ) -{ - // force to reset coex mechanism - halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); -} - -VOID -halbtc8723a1ant_BtEnableAction( - IN PBTC_COEXIST pBtCoexist - ) -{ - halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); -} - -VOID -halbtc8723a1ant_MonitorBtCtr( - IN PBTC_COEXIST pBtCoexist - ) -{ - u4Byte regHPTxRx, regLPTxRx, u4Tmp; - u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; - u1Byte u1Tmp; - - regHPTxRx = 0x770; - regLPTxRx = 0x774; - - u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); - regHPTx = u4Tmp & bMaskLWord; - regHPRx = (u4Tmp & bMaskHWord)>>16; - - u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); - regLPTx = u4Tmp & bMaskLWord; - regLPRx = (u4Tmp & bMaskHWord)>>16; - - pCoexSta->highPriorityTx = regHPTx; - pCoexSta->highPriorityRx = regHPRx; - pCoexSta->lowPriorityTx = regLPTx; - pCoexSta->lowPriorityRx = regLPRx; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx)); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx)); - - // reset counter - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); -} - -VOID -halbtc8723a1ant_MonitorBtEnableDisable( - IN PBTC_COEXIST pBtCoexist - ) -{ - static BOOLEAN bPreBtDisabled=FALSE; - static u4Byte btDisableCnt=0; - BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; - - // This function check if bt is disabled - - if( pCoexSta->highPriorityTx == 0 && - pCoexSta->highPriorityRx == 0 && - pCoexSta->lowPriorityTx == 0 && - pCoexSta->lowPriorityRx == 0) - { - bBtActive = FALSE; - } - if( pCoexSta->highPriorityTx == 0xffff && - pCoexSta->highPriorityRx == 0xffff && - pCoexSta->lowPriorityTx == 0xffff && - pCoexSta->lowPriorityRx == 0xffff) - { - bBtActive = FALSE; - } - if(bBtActive) - { - btDisableCnt = 0; - bBtDisabled = FALSE; - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); - } - else - { - btDisableCnt++; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", - btDisableCnt)); - if(btDisableCnt >= 2) - { - bBtDisabled = TRUE; - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); - } - } - if(bPreBtDisabled != bBtDisabled) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", - (bPreBtDisabled ? "disabled":"enabled"), - (bBtDisabled ? "disabled":"enabled"))); - bPreBtDisabled = bBtDisabled; - if(!bBtDisabled) - { - halbtc8723a1ant_BtEnableAction(pBtCoexist); - } - else - { - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); - } - } -} - -VOID -halbtc8723a1ant_TdmaDurationAdjust( - IN PBTC_COEXIST pBtCoexist - ) -{ - static s4Byte up,dn,m,n,WaitCount; - s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration - u1Byte retryCount=0; - u1Byte btState; - BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; - u4Byte wifiBw; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - btState = pCoexDm->btStatus; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], TdmaDurationAdjust()\n")); - if(pCoexDm->psTdmaGlobalCnt != pCoexDm->psTdmaMonitorCnt) - { - pCoexDm->psTdmaMonitorCnt = 0; - pCoexDm->psTdmaGlobalCnt = 0; - } - if(pCoexDm->psTdmaMonitorCnt == 0) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], first run BT A2DP + WiFi busy state!!\n")); - if(btState == BT_STATE_8723A_1ANT_ACL_ONLY_BUSY) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); - pCoexDm->psTdmaDuAdjType = 1; - } - else - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); - pCoexDm->psTdmaDuAdjType = 22; - } - //============ - up = 0; - dn = 0; - m = 1; - n= 3; - result = 0; - WaitCount = 0; - } - else - { - //accquire the BT TRx retry count from BT_Info byte2 - retryCount = pCoexSta->btRetryCnt; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], retryCount = %d\n", retryCount)); - result = 0; - WaitCount++; - - if(retryCount == 0) // no retry in the last 2-second duration - { - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if(up >= n) // if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration - { - WaitCount = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Increase wifi duration!!\n")); - } - } - else if (retryCount <= 3) // <=3 retry in the last 2-second duration - { - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) // if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration - { - if (WaitCount <= 2) - m++; // ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ - else - m = 1; - - if ( m >= 20) //m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. - m = 20; - - n = 3*m; - up = 0; - dn = 0; - WaitCount = 0; - result = -1; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); - } - } - else //retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration - { - if (WaitCount == 1) - m++; // ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ - else - m = 1; - - if ( m >= 20) //m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. - m = 20; - - n = 3*m; - up = 0; - dn = 0; - WaitCount = 0; - result = -1; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); - } - - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT TxRx counter H+L <= 1200\n")); - if(btState != BT_STATE_8723A_1ANT_ACL_ONLY_BUSY) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], NOT ACL only busy!\n")); - if(BTC_WIFI_BW_HT40 != wifiBw) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 20MHz\n")); - if(result == -1) - { - if(pCoexDm->curPsTdma == 22) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); - pCoexDm->psTdmaDuAdjType = 23; - } - else if(pCoexDm->curPsTdma == 23) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24); - pCoexDm->psTdmaDuAdjType = 24; - } - else if(pCoexDm->curPsTdma == 24) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 25); - pCoexDm->psTdmaDuAdjType = 25; - } - } - else if (result == 1) - { - if(pCoexDm->curPsTdma == 25) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24); - pCoexDm->psTdmaDuAdjType = 24; - } - else if(pCoexDm->curPsTdma == 24) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); - pCoexDm->psTdmaDuAdjType = 23; - } - else if(pCoexDm->curPsTdma == 23) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); - pCoexDm->psTdmaDuAdjType = 22; - } - } - // error handle, if not in the following state, - // set psTdma again. - if( (pCoexDm->psTdmaDuAdjType != 22) && - (pCoexDm->psTdmaDuAdjType != 23) && - (pCoexDm->psTdmaDuAdjType != 24) && - (pCoexDm->psTdmaDuAdjType != 25) ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], duration case out of handle!!\n")); - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); - pCoexDm->psTdmaDuAdjType = 23; - } - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 40MHz\n")); - if(result == -1) - { - if(pCoexDm->curPsTdma == 23) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24); - pCoexDm->psTdmaDuAdjType = 24; - } - else if(pCoexDm->curPsTdma == 24) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 25); - pCoexDm->psTdmaDuAdjType = 25; - } - else if(pCoexDm->curPsTdma == 25) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 27); - pCoexDm->psTdmaDuAdjType = 27; - } - } - else if (result == 1) - { - if(pCoexDm->curPsTdma == 27) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 25); - pCoexDm->psTdmaDuAdjType = 25; - } - else if(pCoexDm->curPsTdma == 25) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24); - pCoexDm->psTdmaDuAdjType = 24; - } - else if(pCoexDm->curPsTdma == 24) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); - pCoexDm->psTdmaDuAdjType = 23; - } - } - // error handle, if not in the following state, - // set psTdma again. - if( (pCoexDm->psTdmaDuAdjType != 23) && - (pCoexDm->psTdmaDuAdjType != 24) && - (pCoexDm->psTdmaDuAdjType != 25) && - (pCoexDm->psTdmaDuAdjType != 27) ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], duration case out of handle!!\n")); - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24); - pCoexDm->psTdmaDuAdjType = 24; - } - } - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ACL only busy\n")); - if (result == -1) - { - if(pCoexDm->curPsTdma == 1) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - pCoexDm->psTdmaDuAdjType = 2; - } - else if(pCoexDm->curPsTdma == 2) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); - pCoexDm->psTdmaDuAdjType = 9; - } - else if(pCoexDm->curPsTdma == 9) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - } - else if (result == 1) - { - if(pCoexDm->curPsTdma == 11) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); - pCoexDm->psTdmaDuAdjType = 9; - } - else if(pCoexDm->curPsTdma == 9) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - pCoexDm->psTdmaDuAdjType = 2; - } - else if(pCoexDm->curPsTdma == 2) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); - pCoexDm->psTdmaDuAdjType = 1; - } - } - - // error handle, if not in the following state, - // set psTdma again. - if( (pCoexDm->psTdmaDuAdjType != 1) && - (pCoexDm->psTdmaDuAdjType != 2) && - (pCoexDm->psTdmaDuAdjType != 9) && - (pCoexDm->psTdmaDuAdjType != 11) ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], duration case out of handle!!\n")); - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - pCoexDm->psTdmaDuAdjType = 2; - } - } - } - } - - // if current PsTdma not match with the recorded one (when scan, dhcp...), - // then we have to adjust it back to the previous record one. - if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n", - pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType)); - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); - - if( !bScan && !bLink && !bRoam) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n")); - } - } - pCoexDm->psTdmaMonitorCnt++; -} - - -VOID -halbtc8723a1ant_CoexForWifiConnect( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bWifiConnected=FALSE, bWifiBusy=FALSE; - u1Byte btState, btInfoOriginal=0; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); - - btState = pCoexDm->btStatus; - btInfoOriginal = pCoexSta->btInfoC2h[BT_INFO_SRC_8723A_1ANT_BT_RSP][0]; - - if(bWifiConnected) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi connected!!\n")); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - - if( !bWifiBusy && - ((BT_STATE_8723A_1ANT_NO_CONNECTION == btState) || - (BT_STATE_8723A_1ANT_CONNECT_IDLE == btState)) ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], [Wifi is idle] or [Bt is non connected idle or Bt is connected idle]!!\n")); - - if(BT_STATE_8723A_1ANT_NO_CONNECTION == btState) - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); - else if(BT_STATE_8723A_1ANT_CONNECT_IDLE == btState) - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, 0xc0); - } - else - { - if( (BT_STATE_8723A_1ANT_SCO_ONLY_BUSY == btState) || - (BT_STATE_8723A_1ANT_ACL_SCO_BUSY == btState) || - (BT_STATE_8723A_1ANT_HID_BUSY == btState) || - (BT_STATE_8723A_1ANT_HID_SCO_BUSY == btState) ) - { - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, 0x60); - } - else - { - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, 0xc0); - } - switch(btState) - { - case BT_STATE_8723A_1ANT_NO_CONNECTION: - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); - break; - case BT_STATE_8723A_1ANT_CONNECT_IDLE: - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); - break; - case BT_STATE_8723A_1ANT_INQ_OR_PAG: - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - break; - case BT_STATE_8723A_1ANT_SCO_ONLY_BUSY: - case BT_STATE_8723A_1ANT_ACL_SCO_BUSY: - case BT_STATE_8723A_1ANT_HID_BUSY: - case BT_STATE_8723A_1ANT_HID_SCO_BUSY: - halbtc8723a1ant_TdmaDurationAdjust(pBtCoexist); - break; - case BT_STATE_8723A_1ANT_ACL_ONLY_BUSY: - if (btInfoOriginal&BT_INFO_8723A_1ANT_B_A2DP) - { - halbtc8723a1ant_TdmaDurationAdjust(pBtCoexist); - } - else if(btInfoOriginal&BT_INFO_8723A_1ANT_B_FTP) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); - } - else if( (btInfoOriginal&BT_INFO_8723A_1ANT_B_A2DP) && - (btInfoOriginal&BT_INFO_8723A_1ANT_B_FTP) ) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - } - else - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); - } - break; - default: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], error!!!, undefined case in halbtc8723a1ant_CoexForWifiConnect()!!\n")); - break; - } - } - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is disconnected!!\n")); - } - - pCoexDm->psTdmaGlobalCnt++; -} - -//============================================================ -// work around function start with wa_halbtc8723a1ant_ -//============================================================ -VOID -wa_halbtc8723a1ant_MonitorC2h( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte tmp1b=0x0; - u4Byte curC2hTotalCnt=0x0; - static u4Byte preC2hTotalCnt=0x0, sameCntPollingTime=0x0; - - curC2hTotalCnt+=pCoexSta->btInfoC2hCnt[BT_INFO_SRC_8723A_1ANT_BT_RSP]; - - if(curC2hTotalCnt == preC2hTotalCnt) - { - sameCntPollingTime++; - } - else - { - preC2hTotalCnt = curC2hTotalCnt; - sameCntPollingTime = 0; - } - - if(sameCntPollingTime >= 2) - { - tmp1b = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x1af); - if(tmp1b != 0x0) - { - pCoexSta->c2hHangDetectCnt++; - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x1af, 0x0); - } - } -} - -//============================================================ -// extern function start with EXhalbtc8723a1ant_ -//============================================================ -VOID -EXhalbtc8723a1ant_InitHwConfig( - IN PBTC_COEXIST pBtCoexist - ) -{ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 1Ant Init HW Config!!\n")); - - // backup rf 0x1e value - pCoexDm->btRf0x1eBackup = - pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); - - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x20); - - // enable counter statistics - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); - - // coex table - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, 0x0); // 1-Ant coex - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, 0xffff); // wifi break table - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, 0x55555555); //coex table - - // antenna switch control parameter - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x858, 0xaaaaaaaa); - - pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x860, 0x210); //set antenna at wifi side if ANTSW is software control - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x870, 0x300); //SPDT(connected with TRSW) control by hardware PTA - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x874, 0x22804000); //ANTSW keep by GNT_BT - - // coexistence parameters - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x1); // enable RTK mode PTA -} - -VOID -EXhalbtc8723a1ant_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ) -{ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); - - halbtc8723a1ant_InitCoexDm(pBtCoexist); -} - -VOID -EXhalbtc8723a1ant_DisplayCoexInfo( - IN PBTC_COEXIST pBtCoexist - ) -{ - PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; - PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; - pu1Byte cliBuf=pBtCoexist->cliBuf; - u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; - u4Byte u4Tmp[4]; - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ - pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); - CL_PRINTF(cliBuf); - - if(pBtCoexist->bManualControl) - { - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!"); - CL_PRINTF(cliBuf); - } - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ - ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ - pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], - pCoexDm->wifiChnlInfo[2]); - CL_PRINTF(cliBuf); - - // wifi status - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); - CL_PRINTF(cliBuf); - pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \ - ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8723A_1ANT_BT_STATUS_IDLE == pCoexDm->btStatus)? "idle":( (BT_8723A_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy"))), - pCoexSta->btRssi, pCoexSta->btRetryCnt); - CL_PRINTF(cliBuf); - - if(pStackInfo->bProfileNotified) - { - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ - pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist); - CL_PRINTF(cliBuf); - - pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); - } - - btInfoExt = pCoexSta->btInfoExt; - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \ - (btInfoExt&BIT0)? "Basic rate":"EDR rate"); - CL_PRINTF(cliBuf); - - for(i=0; ibtInfoC2hCnt[i]) - { - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8723a1Ant[i], \ - pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], - pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], - pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], - pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); - CL_PRINTF(cliBuf); - } - } - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "write 0x1af=0x0 num", \ - pCoexSta->c2hHangDetectCnt); - CL_PRINTF(cliBuf); - - // Sw mechanism - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); - CL_PRINTF(cliBuf); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "SM1[ShRf/ LpRA/ LimDig]", \ - pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->bLimitedDig); - CL_PRINTF(cliBuf); - - // Fw mechanism - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); - CL_PRINTF(cliBuf); - - if(!pBtCoexist->bManualControl) - { - psTdmaCase = pCoexDm->curPsTdma; - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", "PS TDMA", \ - pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], - pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], - pCoexDm->psTdmaPara[4], psTdmaCase); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IgnWlanAct", \ - pCoexDm->bCurIgnoreWlanAct); - CL_PRINTF(cliBuf); - } - - // Hw setting - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ - pCoexDm->btRf0x1eBackup); - CL_PRINTF(cliBuf); - - u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); - u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x783); - u1Tmp[2] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x796); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x778/ 0x783/ 0x796", \ - u1Tmp[0], u1Tmp[1], u1Tmp[2]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x880); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x880", \ - u4Tmp[0]); - CL_PRINTF(cliBuf); - - u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \ - u1Tmp[0]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); - u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ - u4Tmp[0], u1Tmp[0]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x484); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x484(rate adaptive)", \ - u4Tmp[0]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \ - u4Tmp[0]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda0); - u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda4); - u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda8); - u4Tmp[3] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xdac); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0xda0/0xda4/0xda8/0xdac(FA cnt)", \ - u4Tmp[0], u4Tmp[1], u4Tmp[2], u4Tmp[3]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); - u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); - u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); - u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \ - u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770 (hp rx[31:16]/tx[15:0])", \ - pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); - CL_PRINTF(cliBuf); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \ - pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); - CL_PRINTF(cliBuf); - - pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -VOID -EXhalbtc8723a1ant_IpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_IPS_ENTER == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); - halbtc8723a1ant_CoexAllOff(pBtCoexist); - } - else if(BTC_IPS_LEAVE == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); - //halbtc8723a1ant_InitCoexDm(pBtCoexist); - } -} - -VOID -EXhalbtc8723a1ant_LpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_LPS_ENABLE == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); - } - else if(BTC_LPS_DISABLE == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); - } -} - -VOID -EXhalbtc8723a1ant_ScanNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - BOOLEAN bWifiConnected=FALSE; - - halbtc8723a1ant_NotifyFwScan(pBtCoexist, type); - - if(pBtCoexist->btInfo.bBtDisabled) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); - } - else - { - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); - if(BTC_SCAN_START == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); - if(!bWifiConnected) // non-connected scan - { - //set 0x550[3]=1 before PsTdma - halbtc8723a1ant_Reg0x550Bit3(pBtCoexist, TRUE); - } - - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); - } - else if(BTC_SCAN_FINISH == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); - if(!bWifiConnected) // non-connected scan - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - } - else - { - halbtc8723a1ant_CoexForWifiConnect(pBtCoexist); - } - } - } -} - -VOID -EXhalbtc8723a1ant_ConnectNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - BOOLEAN bWifiConnected=FALSE; - - if(pBtCoexist->btInfo.bBtDisabled) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); - } - else - { - if(BTC_ASSOCIATE_START == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); - //set 0x550[3]=1 before PsTdma - halbtc8723a1ant_Reg0x550Bit3(pBtCoexist, TRUE); - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); // extend wifi slot - } - else if(BTC_ASSOCIATE_FINISH == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); - if(!bWifiConnected) // non-connected scan - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - } - else - { - halbtc8723a1ant_CoexForWifiConnect(pBtCoexist); - } - } - } -} - -VOID -EXhalbtc8723a1ant_MediaStatusNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_MEDIA_CONNECT == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); - } -} - -VOID -EXhalbtc8723a1ant_SpecialPacketNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(type == BTC_PACKET_DHCP) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); - if(pBtCoexist->btInfo.bBtDisabled) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); - } - else - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 18); - } - } -} - -VOID -EXhalbtc8723a1ant_BtInfoNotify( - IN PBTC_COEXIST pBtCoexist, - IN pu1Byte tmpBuf, - IN u1Byte length - ) -{ - u1Byte btInfo=0; - u1Byte i, rspSource=0; - BOOLEAN bBtHsOn=FALSE, bBtBusy=FALSE, bForceLps=FALSE; - - pCoexSta->bC2hBtInfoReqSent = FALSE; - - rspSource = BT_INFO_SRC_8723A_1ANT_BT_RSP; - pCoexSta->btInfoC2hCnt[rspSource]++; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); - for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; - if(i == 0) - btInfo = tmpBuf[i]; - if(i == length-1) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); - } - } - - if(BT_INFO_SRC_8723A_1ANT_WIFI_FW != rspSource) - { - pCoexSta->btRetryCnt = - pCoexSta->btInfoC2h[rspSource][1]; - - pCoexSta->btRssi = - pCoexSta->btInfoC2h[rspSource][2]*2+10; - - pCoexSta->btInfoExt = - pCoexSta->btInfoC2h[rspSource][3]; - } - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - // check BIT2 first ==> check if bt is under inquiry or page scan - if(btInfo & BT_INFO_8723A_1ANT_B_INQ_PAGE) - { - pCoexSta->bC2hBtInquiryPage = TRUE; - } - else - { - pCoexSta->bC2hBtInquiryPage = FALSE; - } - btInfo &= ~BIT2; - if(!(btInfo & BIT0)) - { - pCoexDm->btStatus = BT_STATE_8723A_1ANT_NO_CONNECTION; - bForceLps = FALSE; - } - else - { - bForceLps = TRUE; - if(btInfo == 0x1) - { - pCoexDm->btStatus = BT_STATE_8723A_1ANT_CONNECT_IDLE; - } - else if(btInfo == 0x9) - { - pCoexDm->btStatus = BT_STATE_8723A_1ANT_ACL_ONLY_BUSY; - bBtBusy = TRUE; - } - else if(btInfo == 0x13) - { - pCoexDm->btStatus = BT_STATE_8723A_1ANT_SCO_ONLY_BUSY; - bBtBusy = TRUE; - } - else if(btInfo == 0x1b) - { - pCoexDm->btStatus = BT_STATE_8723A_1ANT_ACL_SCO_BUSY; - bBtBusy = TRUE; - } - else if(btInfo == 0x29) - { - pCoexDm->btStatus = BT_STATE_8723A_1ANT_HID_BUSY; - bBtBusy = TRUE; - } - else if(btInfo == 0x3b) - { - pCoexDm->btStatus = BT_STATE_8723A_1ANT_HID_SCO_BUSY; - bBtBusy = TRUE; - } - } - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bBtBusy); - if(bForceLps) - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL); - else - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); - - if( (BT_STATE_8723A_1ANT_NO_CONNECTION == pCoexDm->btStatus) || - (BT_STATE_8723A_1ANT_CONNECT_IDLE == pCoexDm->btStatus) ) - { - if(pCoexSta->bC2hBtInquiryPage) - pCoexDm->btStatus = BT_STATE_8723A_1ANT_INQ_OR_PAG; - } -} - -VOID -EXhalbtc8723a1ant_HaltNotify( - IN PBTC_COEXIST pBtCoexist - ) -{ - halbtc8723a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); - - halbtc8723a1ant_LowPenaltyRa(pBtCoexist, FORCE_EXEC, FALSE); - halbtc8723a1ant_RfShrink(pBtCoexist, FORCE_EXEC, FALSE); - - halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); - EXhalbtc8723a1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); -} - -VOID -EXhalbtc8723a1ant_Periodical( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE, bWifiConnected=FALSE; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 1Ant Periodical!!\n")); - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); - - // work around for c2h hang - wa_halbtc8723a1ant_MonitorC2h(pBtCoexist); - - halbtc8723a1ant_QueryBtInfo(pBtCoexist); - halbtc8723a1ant_MonitorBtCtr(pBtCoexist); - halbtc8723a1ant_MonitorBtEnableDisable(pBtCoexist); - - - if(bScan) - return; - if(bLink) - return; - - if(bWifiConnected) - { - if(pBtCoexist->btInfo.bBtDisabled) - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); - - halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); - } - else - { - halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a1ant_CoexForWifiConnect(pBtCoexist); - } - } - else - { - halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - - halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); - } -} - - -#endif - diff --git a/hal/btc/HalBtc8723a1Ant.h b/hal/btc/HalBtc8723a1Ant.h deleted file mode 100644 index 6d4e1b4..0000000 --- a/hal/btc/HalBtc8723a1Ant.h +++ /dev/null @@ -1,171 +0,0 @@ -//=========================================== -// The following is for 8723A 1Ant BT Co-exist definition -//=========================================== -#define BT_INFO_8723A_1ANT_B_FTP BIT7 -#define BT_INFO_8723A_1ANT_B_A2DP BIT6 -#define BT_INFO_8723A_1ANT_B_HID BIT5 -#define BT_INFO_8723A_1ANT_B_SCO_BUSY BIT4 -#define BT_INFO_8723A_1ANT_B_ACL_BUSY BIT3 -#define BT_INFO_8723A_1ANT_B_INQ_PAGE BIT2 -#define BT_INFO_8723A_1ANT_B_SCO_ESCO BIT1 -#define BT_INFO_8723A_1ANT_B_CONNECTION BIT0 - -typedef enum _BT_STATE_8723A_1ANT{ - BT_STATE_8723A_1ANT_DISABLED = 0, - BT_STATE_8723A_1ANT_NO_CONNECTION = 1, - BT_STATE_8723A_1ANT_CONNECT_IDLE = 2, - BT_STATE_8723A_1ANT_INQ_OR_PAG = 3, - BT_STATE_8723A_1ANT_ACL_ONLY_BUSY = 4, - BT_STATE_8723A_1ANT_SCO_ONLY_BUSY = 5, - BT_STATE_8723A_1ANT_ACL_SCO_BUSY = 6, - BT_STATE_8723A_1ANT_HID_BUSY = 7, - BT_STATE_8723A_1ANT_HID_SCO_BUSY = 8, - BT_STATE_8723A_1ANT_MAX -}BT_STATE_8723A_1ANT, *PBT_STATE_8723A_1ANT; - -#define BTC_RSSI_COEX_THRESH_TOL_8723A_1ANT 2 - -typedef enum _BT_INFO_SRC_8723A_1ANT{ - BT_INFO_SRC_8723A_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8723A_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8723A_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8723A_1ANT_MAX -}BT_INFO_SRC_8723A_1ANT,*PBT_INFO_SRC_8723A_1ANT; - -typedef enum _BT_8723A_1ANT_BT_STATUS{ - BT_8723A_1ANT_BT_STATUS_IDLE = 0x0, - BT_8723A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8723A_1ANT_BT_STATUS_NON_IDLE = 0x2, - BT_8723A_1ANT_BT_STATUS_MAX -}BT_8723A_1ANT_BT_STATUS,*PBT_8723A_1ANT_BT_STATUS; - -typedef enum _BT_8723A_1ANT_COEX_ALGO{ - BT_8723A_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8723A_1ANT_COEX_ALGO_SCO = 0x1, - BT_8723A_1ANT_COEX_ALGO_HID = 0x2, - BT_8723A_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8723A_1ANT_COEX_ALGO_PANEDR = 0x4, - BT_8723A_1ANT_COEX_ALGO_PANHS = 0x5, - BT_8723A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x6, - BT_8723A_1ANT_COEX_ALGO_PANEDR_HID = 0x7, - BT_8723A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8, - BT_8723A_1ANT_COEX_ALGO_HID_A2DP = 0x9, - BT_8723A_1ANT_COEX_ALGO_MAX -}BT_8723A_1ANT_COEX_ALGO,*PBT_8723A_1ANT_COEX_ALGO; - -typedef struct _COEX_DM_8723A_1ANT{ - // fw mechanism - BOOLEAN bCurIgnoreWlanAct; - BOOLEAN bPreIgnoreWlanAct; - u1Byte prePsTdma; - u1Byte curPsTdma; - u1Byte psTdmaPara[5]; - u1Byte psTdmaDuAdjType; - u4Byte psTdmaMonitorCnt; - u4Byte psTdmaGlobalCnt; - BOOLEAN bResetTdmaAdjust; - BOOLEAN bPrePsTdmaOn; - BOOLEAN bCurPsTdmaOn; - - // sw mechanism - BOOLEAN bPreRfRxLpfShrink; - BOOLEAN bCurRfRxLpfShrink; - u4Byte btRf0x1eBackup; - BOOLEAN bPreLowPenaltyRa; - BOOLEAN bCurLowPenaltyRa; - u4Byte preVal0x6c0; - u4Byte curVal0x6c0; - u4Byte preVal0x6c8; - u4Byte curVal0x6c8; - u1Byte preVal0x6cc; - u1Byte curVal0x6cc; - BOOLEAN bLimitedDig; - - // algorithm related - u1Byte preAlgorithm; - u1Byte curAlgorithm; - u1Byte btStatus; - u1Byte wifiChnlInfo[3]; -} COEX_DM_8723A_1ANT, *PCOEX_DM_8723A_1ANT; - -typedef struct _COEX_STA_8723A_1ANT{ - u4Byte highPriorityTx; - u4Byte highPriorityRx; - u4Byte lowPriorityTx; - u4Byte lowPriorityRx; - u1Byte btRssi; - u1Byte preBtRssiState; - u1Byte preBtRssiState1; - u1Byte preWifiRssiState[4]; - BOOLEAN bC2hBtInfoReqSent; - u1Byte btInfoC2h[BT_INFO_SRC_8723A_1ANT_MAX][10]; - u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_1ANT_MAX]; - BOOLEAN bC2hBtInquiryPage; - u1Byte btRetryCnt; - u1Byte btInfoExt; - //BOOLEAN bHoldForStackOperation; - //u1Byte bHoldPeriodCnt; - // this is for c2h hang work-around - u4Byte c2hHangDetectCnt; -}COEX_STA_8723A_1ANT, *PCOEX_STA_8723A_1ANT; - -//=========================================== -// The following is interface which will notify coex module. -//=========================================== -VOID -EXhalbtc8723a1ant_InitHwConfig( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8723a1ant_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8723a1ant_IpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a1ant_LpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a1ant_ScanNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a1ant_ConnectNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a1ant_MediaStatusNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a1ant_SpecialPacketNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a1ant_BtInfoNotify( - IN PBTC_COEXIST pBtCoexist, - IN pu1Byte tmpBuf, - IN u1Byte length - ); -VOID -EXhalbtc8723a1ant_HaltNotify( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8723a1ant_Periodical( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8723a1ant_DisplayCoexInfo( - IN PBTC_COEXIST pBtCoexist - ); - diff --git a/hal/btc/HalBtc8723a2Ant.c b/hal/btc/HalBtc8723a2Ant.c deleted file mode 100644 index 1becd5c..0000000 --- a/hal/btc/HalBtc8723a2Ant.c +++ /dev/null @@ -1,3746 +0,0 @@ -//============================================================ -// Description: -// -// This file is for RTL8723A Co-exist mechanism -// -// History -// 2012/08/22 Cosa first check in. -// 2012/11/14 Cosa Revise for 8723A 2Ant out sourcing. -// -//============================================================ - -//============================================================ -// include files -//============================================================ -#include "Mp_Precomp.h" - -#if WPP_SOFTWARE_TRACE -#include "HalBtc8723a2Ant.tmh" -#endif - -#if(BT_30_SUPPORT == 1) -//============================================================ -// Global variables, these are static variables -//============================================================ -static COEX_DM_8723A_2ANT GLCoexDm8723a2Ant; -static PCOEX_DM_8723A_2ANT pCoexDm=&GLCoexDm8723a2Ant; -static COEX_STA_8723A_2ANT GLCoexSta8723a2Ant; -static PCOEX_STA_8723A_2ANT pCoexSta=&GLCoexSta8723a2Ant; - -const char *const GLBtInfoSrc8723a2Ant[]={ - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -//============================================================ -// local function proto type if needed -//============================================================ -//============================================================ -// local function start with halbtc8723a2ant_ -//============================================================ -BOOLEAN -halbtc8723a2ant_IsWifiIdle( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bWifiConnected=FALSE, bScan=FALSE, bLink=FALSE, bRoam=FALSE; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); - - if(bWifiConnected) - return FALSE; - if(bScan) - return FALSE; - if(bLink) - return FALSE; - if(bRoam) - return FALSE; - - return TRUE; -} - -BOOLEAN -halbtc8723a2ant_IsWifiConnectedIdle( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bWifiConnected=FALSE, bScan=FALSE, bLink=FALSE, bRoam=FALSE, bWifiBusy=FALSE; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); - - if(bScan) - return FALSE; - if(bLink) - return FALSE; - if(bRoam) - return FALSE; - if(bWifiConnected && !bWifiBusy) - return TRUE; - else - return FALSE; -} - -u1Byte -halbtc8723a2ant_BtRssiState( - u1Byte levelNum, - u1Byte rssiThresh, - u1Byte rssiThresh1 - ) -{ - s4Byte btRssi=0; - u1Byte btRssiState=pCoexSta->preBtRssiState; - - btRssi = pCoexSta->btRssi; - - if(levelNum == 2) - { - if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || - (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) - { - if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT)) - { - btRssiState = BTC_RSSI_STATE_HIGH; - } - else - { - btRssiState = BTC_RSSI_STATE_STAY_LOW; - } - } - else - { - if(btRssi < rssiThresh) - { - btRssiState = BTC_RSSI_STATE_LOW; - } - else - { - btRssiState = BTC_RSSI_STATE_STAY_HIGH; - } - } - } - else if(levelNum == 3) - { - if(rssiThresh > rssiThresh1) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); - return pCoexSta->preBtRssiState; - } - - if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || - (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) - { - if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT)) - { - btRssiState = BTC_RSSI_STATE_MEDIUM; - } - else - { - btRssiState = BTC_RSSI_STATE_STAY_LOW; - } - } - else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || - (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) - { - if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT)) - { - btRssiState = BTC_RSSI_STATE_HIGH; - } - else if(btRssi < rssiThresh) - { - btRssiState = BTC_RSSI_STATE_LOW; - } - else - { - btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; - } - } - else - { - if(btRssi < rssiThresh1) - { - btRssiState = BTC_RSSI_STATE_MEDIUM; - } - else - { - btRssiState = BTC_RSSI_STATE_STAY_HIGH; - } - } - } - - pCoexSta->preBtRssiState = btRssiState; - - return btRssiState; -} - -u1Byte -halbtc8723a2ant_WifiRssiState( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte index, - IN u1Byte levelNum, - IN u1Byte rssiThresh, - IN u1Byte rssiThresh1 - ) -{ - s4Byte wifiRssi=0; - u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); - - if(levelNum == 2) - { - if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || - (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) - { - if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT)) - { - wifiRssiState = BTC_RSSI_STATE_HIGH; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_LOW; - } - } - else - { - if(wifiRssi < rssiThresh) - { - wifiRssiState = BTC_RSSI_STATE_LOW; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; - } - } - } - else if(levelNum == 3) - { - if(rssiThresh > rssiThresh1) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); - return pCoexSta->preWifiRssiState[index]; - } - - if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || - (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) - { - if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT)) - { - wifiRssiState = BTC_RSSI_STATE_MEDIUM; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_LOW; - } - } - else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || - (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) - { - if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT)) - { - wifiRssiState = BTC_RSSI_STATE_HIGH; - } - else if(wifiRssi < rssiThresh) - { - wifiRssiState = BTC_RSSI_STATE_LOW; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; - } - } - else - { - if(wifiRssi < rssiThresh1) - { - wifiRssiState = BTC_RSSI_STATE_MEDIUM; - } - else - { - wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; - } - } - } - - pCoexSta->preWifiRssiState[index] = wifiRssiState; - - return wifiRssiState; -} - -VOID -halbtc8723a2ant_IndicateWifiChnlBwInfo( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - u1Byte H2C_Parameter[3] ={0}; - u4Byte wifiBw; - u1Byte wifiCentralChnl; - - // only 2.4G we need to inform bt the chnl mask - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); - if( (BTC_MEDIA_CONNECT == type) && - (wifiCentralChnl <= 14) ) - { - H2C_Parameter[0] = 0x1; - H2C_Parameter[1] = wifiCentralChnl; - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - H2C_Parameter[2] = 0x30; - else - H2C_Parameter[2] = 0x20; - } - - pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; - pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; - pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x19=0x%x\n", - H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); - - pBtCoexist->fBtcFillH2c(pBtCoexist, 0x19, 3, H2C_Parameter); -} - -VOID -halbtc8723a2ant_QueryBtInfo( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte H2C_Parameter[1] ={0}; - - pCoexSta->bC2hBtInfoReqSent = TRUE; - - H2C_Parameter[0] |= BIT0; // trigger - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x38=0x%x\n", - H2C_Parameter[0])); - - pBtCoexist->fBtcFillH2c(pBtCoexist, 0x38, 1, H2C_Parameter); -} -u1Byte -halbtc8723a2ant_ActionAlgorithm( - IN PBTC_COEXIST pBtCoexist - ) -{ - PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; - BOOLEAN bBtHsOn=FALSE, bBtBusy=FALSE, bLimitedDig=FALSE; - u1Byte algorithm=BT_8723A_2ANT_COEX_ALGO_UNDEFINED; - u1Byte numOfDiffProfile=0; - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - - //====================== - // here we get BT status first - //====================== - pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_IDLE; - - if((pStackInfo->bScoExist) ||(bBtHsOn) ||(pStackInfo->bHidExist)) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO or HID or HS exists, set BT non-idle !!!\n")); - pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE; - } - else - { - // A2dp profile - if( (pBtCoexist->stackInfo.numOfLink == 1) && - (pStackInfo->bA2dpExist) ) - { - if( (pCoexSta->lowPriorityTx+ pCoexSta->lowPriorityRx) < 100) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP, low priority tx+rx < 100, set BT connected-idle!!!\n")); - pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP, low priority tx+rx >= 100, set BT non-idle!!!\n")); - pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE; - } - } - // Pan profile - if( (pBtCoexist->stackInfo.numOfLink == 1) && - (pStackInfo->bPanExist) ) - { - if((pCoexSta->lowPriorityTx+ pCoexSta->lowPriorityRx) < 600) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN, low priority tx+rx < 600, set BT connected-idle!!!\n")); - pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE; - } - else - { - if(pCoexSta->lowPriorityTx) - { - if((pCoexSta->lowPriorityRx /pCoexSta->lowPriorityTx)>9 ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN, low priority rx/tx > 9, set BT connected-idle!!!\n")); - pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE; - } - } - } - if(BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN, set BT non-idle!!!\n")); - pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE; - } - } - // Pan+A2dp profile - if( (pBtCoexist->stackInfo.numOfLink == 2) && - (pStackInfo->bA2dpExist) && - (pStackInfo->bPanExist) ) - { - if((pCoexSta->lowPriorityTx+ pCoexSta->lowPriorityRx) < 600) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN+A2DP, low priority tx+rx < 600, set BT connected-idle!!!\n")); - pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE; - } - else - { - if(pCoexSta->lowPriorityTx) - { - if((pCoexSta->lowPriorityRx /pCoexSta->lowPriorityTx)>9 ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN+A2DP, low priority rx/tx > 9, set BT connected-idle!!!\n")); - pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE; - } - } - } - if(BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN+A2DP, set BT non-idle!!!\n")); - pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE; - } - } - } - if(BT_8723A_2ANT_BT_STATUS_IDLE != pCoexDm->btStatus) - { - bBtBusy = TRUE; - bLimitedDig = TRUE; - } - else - { - bBtBusy = FALSE; - bLimitedDig = FALSE; - } - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bLimitedDig); - //====================== - - if(!pStackInfo->bBtLinkExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No profile exists!!!\n")); - return algorithm; - } - - if(pStackInfo->bScoExist) - numOfDiffProfile++; - if(pStackInfo->bHidExist) - numOfDiffProfile++; - if(pStackInfo->bPanExist) - numOfDiffProfile++; - if(pStackInfo->bA2dpExist) - numOfDiffProfile++; - - if(numOfDiffProfile == 1) - { - if(pStackInfo->bScoExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO only\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_SCO; - } - else - { - if(pStackInfo->bHidExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_HID; - } - else if(pStackInfo->bA2dpExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_A2DP; - } - else if(pStackInfo->bPanExist) - { - if(bBtHsOn) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(HS) only\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_PANHS; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(EDR) only\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR; - } - } - } - } - else if(numOfDiffProfile == 2) - { - if(pStackInfo->bScoExist) - { - if(pStackInfo->bHidExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_HID; - } - else if(pStackInfo->bA2dpExist) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP ==> SCO\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_SCO; - } - else if(pStackInfo->bPanExist) - { - if(bBtHsOn) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(HS)\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_SCO; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(EDR)\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } - else - { - if( pStackInfo->bHidExist && - pStackInfo->bA2dpExist ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP; - } - else if( pStackInfo->bHidExist && - pStackInfo->bPanExist ) - { - if(bBtHsOn) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(HS)\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(EDR)\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID; - } - } - else if( pStackInfo->bPanExist && - pStackInfo->bA2dpExist ) - { - if(bBtHsOn) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(HS)\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_A2DP; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(EDR)\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } - else if(numOfDiffProfile == 3) - { - if(pStackInfo->bScoExist) - { - if( pStackInfo->bHidExist && - pStackInfo->bA2dpExist ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP ==> HID\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_HID; - } - else if( pStackInfo->bHidExist && - pStackInfo->bPanExist ) - { - if(bBtHsOn) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(HS)\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(EDR)\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID; - } - } - else if( pStackInfo->bPanExist && - pStackInfo->bA2dpExist ) - { - if(bBtHsOn) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(HS)\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_SCO; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } - else - { - if( pStackInfo->bHidExist && - pStackInfo->bPanExist && - pStackInfo->bA2dpExist ) - { - if(bBtHsOn) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(HS)\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(EDR)\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } - else if(numOfDiffProfile >= 3) - { - if(pStackInfo->bScoExist) - { - if( pStackInfo->bHidExist && - pStackInfo->bPanExist && - pStackInfo->bA2dpExist ) - { - if(bBtHsOn) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n")); - - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); - algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -BOOLEAN -halbtc8723a2ant_NeedToDecBtPwr( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bRet=FALSE; - BOOLEAN bBtHsOn=FALSE, bWifiConnected=FALSE; - s4Byte btHsRssi=0; - u1Byte btRssiState=BTC_RSSI_STATE_HIGH; - - btRssiState = halbtc8723a2ant_BtRssiState(2, 42, 0); - - if(!pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn)) - return FALSE; - if(!pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected)) - return FALSE; - if(!pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_HS_RSSI, &btHsRssi)) - return FALSE; - if(BTC_RSSI_LOW(btRssiState)) - return FALSE; - - if(bWifiConnected) - { - if(bBtHsOn) - { - if(btHsRssi > 37) - { - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Need to decrease bt power for HS mode!!\n")); - bRet = TRUE; - } - } - else - { - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Need to decrease bt power for Wifi is connected!!\n")); - bRet = TRUE; - } - } - - return bRet; -} - -VOID -halbtc8723a2ant_SetFwDacSwingLevel( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte dacSwingLvl - ) -{ - u1Byte H2C_Parameter[1] ={0}; - - // There are several type of dacswing - // 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 - H2C_Parameter[0] = dacSwingLvl; - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Set Dac Swing Level=0x%x\n", dacSwingLvl)); - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x29=0x%x\n", H2C_Parameter[0])); - - pBtCoexist->fBtcFillH2c(pBtCoexist, 0x29, 1, H2C_Parameter); -} - -VOID -halbtc8723a2ant_SetFwDecBtPwr( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bDecBtPwr - ) -{ - u1Byte H2C_Parameter[1] ={0}; - - H2C_Parameter[0] = 0; - - if(bDecBtPwr) - { - H2C_Parameter[0] |= BIT1; - } - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], decrease Bt Power : %s, FW write 0x21=0x%x\n", - (bDecBtPwr? "Yes!!":"No!!"), H2C_Parameter[0])); - - pBtCoexist->fBtcFillH2c(pBtCoexist, 0x21, 1, H2C_Parameter); -} - -VOID -halbtc8723a2ant_DecBtPwr( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bDecBtPwr - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s Dec BT power = %s\n", - (bForceExec? "force to":""), ((bDecBtPwr)? "ON":"OFF"))); - pCoexDm->bCurDecBtPwr = bDecBtPwr; - - if(!bForceExec) - { - if(pCoexDm->bPreDecBtPwr == pCoexDm->bCurDecBtPwr) - return; - } - halbtc8723a2ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->bCurDecBtPwr); - - pCoexDm->bPreDecBtPwr = pCoexDm->bCurDecBtPwr; -} - -VOID -halbtc8723a2ant_FwDacSwingLvl( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN u1Byte fwDacSwingLvl - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set FW Dac Swing level = %d\n", - (bForceExec? "force to":""), fwDacSwingLvl)); - pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; - - if(!bForceExec) - { - if(pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl) - return; - } - - halbtc8723a2ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl); - - pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; -} - -VOID -halbtc8723a2ant_SetSwRfRxLpfCorner( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bRxRfShrinkOn - ) -{ - if(bRxRfShrinkOn) - { - //Shrink RF Rx LPF corner - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf0ff7); - } - else - { - //Resume RF Rx LPF corner - // After initialized, we can use pCoexDm->btRf0x1eBackup - if(pBtCoexist->bInitilized) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); - } - } -} - -VOID -halbtc8723a2ant_RfShrink( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bRxRfShrinkOn - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", - (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); - pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; - - if(!bForceExec) - { - if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) - return; - } - halbtc8723a2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); - - pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; -} - -VOID -halbtc8723a2ant_SetSwPenaltyTxRateAdaptive( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bLowPenaltyRa - ) -{ - u1Byte tmpU1; - - tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd); - tmpU1 |= BIT0; - if(bLowPenaltyRa) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n")); - tmpU1 &= ~BIT2; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n")); - tmpU1 |= BIT2; - } - - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1); -} - -VOID -halbtc8723a2ant_LowPenaltyRa( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bLowPenaltyRa - ) -{ - return; - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", - (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); - pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; - - if(!bForceExec) - { - if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) - return; - } - halbtc8723a2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); - - pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; -} - -VOID -halbtc8723a2ant_SetSwFullTimeDacSwing( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bSwDacSwingOn, - IN u4Byte swDacSwingLvl - ) -{ - if(bSwDacSwingOn) - { - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, swDacSwingLvl); - } - else - { - pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, 0xc0); - } -} - - -VOID -halbtc8723a2ant_DacSwing( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bDacSwingOn, - IN u4Byte dacSwingLvl - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n", - (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl)); - pCoexDm->bCurDacSwingOn = bDacSwingOn; - pCoexDm->curDacSwingLvl = dacSwingLvl; - - if(!bForceExec) - { - if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && - (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) ) - return; - } - delay_ms(30); - halbtc8723a2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); - - pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; - pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; -} - -VOID -halbtc8723a2ant_SetAdcBackOff( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bAdcBackOff - ) -{ - if(bAdcBackOff) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n")); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a07611); - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n")); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a05611); - } -} - -VOID -halbtc8723a2ant_AdcBackOff( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bAdcBackOff - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n", - (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF"))); - pCoexDm->bCurAdcBackOff = bAdcBackOff; - - if(!bForceExec) - { - if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff) - return; - } - halbtc8723a2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff); - - pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff; -} - -VOID -halbtc8723a2ant_SetAgcTable( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bAgcTableEn - ) -{ - u1Byte rssiAdjustVal=0; - - if(bAgcTableEn) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4e1c0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4d1d0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4c1e0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4b1f0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4a200001); - - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xdc000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x90000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x51000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x12000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x00355); - - rssiAdjustVal = 6; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x641c0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x631d0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x621e0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x611f0001); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x60200001); - - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x32000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x71000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xb0000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xfc000); - pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x30355); - } - - // set rssiAdjustVal for wifi module. - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); -} - - -VOID -halbtc8723a2ant_AgcTable( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bAgcTableEn - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n", - (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable"))); - pCoexDm->bCurAgcTableEn = bAgcTableEn; - - if(!bForceExec) - { - if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) - return; - } - halbtc8723a2ant_SetAgcTable(pBtCoexist, bAgcTableEn); - - pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; -} - -VOID -halbtc8723a2ant_SetCoexTable( - IN PBTC_COEXIST pBtCoexist, - IN u4Byte val0x6c0, - IN u4Byte val0x6c8, - IN u1Byte val0x6cc - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); - pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); -} - -VOID -halbtc8723a2ant_CoexTable( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN u4Byte val0x6c0, - IN u4Byte val0x6c8, - IN u1Byte val0x6cc - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", - (bForceExec? "force to":""), val0x6c0, val0x6c8, val0x6cc)); - pCoexDm->curVal0x6c0 = val0x6c0; - pCoexDm->curVal0x6c8 = val0x6c8; - pCoexDm->curVal0x6cc = val0x6cc; - - if(!bForceExec) - { - if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && - (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && - (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) - return; - } - halbtc8723a2ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c8, val0x6cc); - - pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; - pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; - pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; -} - -VOID -halbtc8723a2ant_SetFwIgnoreWlanAct( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bEnable - ) -{ - u1Byte H2C_Parameter[1] ={0}; - - if(bEnable) - { - H2C_Parameter[0] |= BIT0; // function enable - } - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x25=0x%x\n", - H2C_Parameter[0])); - - pBtCoexist->fBtcFillH2c(pBtCoexist, 0x25, 1, H2C_Parameter); -} - -VOID -halbtc8723a2ant_IgnoreWlanAct( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bEnable - ) -{ - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", - (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); - pCoexDm->bCurIgnoreWlanAct = bEnable; - - if(!bForceExec) - { - if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) - return; - } - halbtc8723a2ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); - - pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; -} - -VOID -halbtc8723a2ant_SetFwPstdma( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte byte1, - IN u1Byte byte2, - IN u1Byte byte3, - IN u1Byte byte4, - IN u1Byte byte5 - ) -{ - u1Byte H2C_Parameter[5] ={0}; - - H2C_Parameter[0] = byte1; - H2C_Parameter[1] = byte2; - H2C_Parameter[2] = byte3; - H2C_Parameter[3] = byte4; - H2C_Parameter[4] = byte5; - - pCoexDm->psTdmaPara[0] = byte1; - pCoexDm->psTdmaPara[1] = byte2; - pCoexDm->psTdmaPara[2] = byte3; - pCoexDm->psTdmaPara[3] = byte4; - pCoexDm->psTdmaPara[4] = byte5; - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x3a(5bytes)=0x%x%08x\n", - H2C_Parameter[0], - H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); - - pBtCoexist->fBtcFillH2c(pBtCoexist, 0x3a, 5, H2C_Parameter); -} - -VOID -halbtc8723a2ant_PsTdma( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bForceExec, - IN BOOLEAN bTurnOn, - IN u1Byte type - ) -{ - u4Byte btTxRxCnt=0; - - btTxRxCnt = pCoexSta->highPriorityTx+pCoexSta->highPriorityRx+ - pCoexSta->lowPriorityTx+pCoexSta->lowPriorityRx; - - if(btTxRxCnt > 3000) - { - pCoexDm->bCurPsTdmaOn = TRUE; - pCoexDm->curPsTdma = 8; - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], turn ON PS TDMA, type=%d for BT tx/rx counters=%d(>3000)\n", - pCoexDm->curPsTdma, btTxRxCnt)); - } - else - { - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn %s PS TDMA, type=%d\n", - (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type)); - pCoexDm->bCurPsTdmaOn = bTurnOn; - pCoexDm->curPsTdma = type; - } - - if(!bForceExec) - { - if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && - (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) - return; - } - if(pCoexDm->bCurPsTdmaOn) - { - switch(pCoexDm->curPsTdma) - { - case 1: - default: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x98); - break; - case 2: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x98); - break; - case 3: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x98); - break; - case 4: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x5, 0x5, 0xe1, 0x80); - break; - case 5: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x98); - break; - case 6: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x98); - break; - case 7: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x98); - break; - case 8: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x5, 0x5, 0x60, 0x80); - break; - case 9: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x98); - break; - case 10: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x98); - break; - case 11: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x98); - break; - case 12: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x98); - break; - case 13: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x98); - break; - case 14: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x98); - break; - case 15: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x98); - break; - case 16: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0x60, 0x98); - break; - case 17: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x2f, 0x2f, 0x60, 0x80); - break; - case 18: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x98); - break; - case 19: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0xe1, 0x98); - break; - case 20: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0x60, 0x98); - break; - } - } - else - { - // disable PS tdma - switch(pCoexDm->curPsTdma) - { - case 0: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x8, 0x0); - break; - case 1: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0); - break; - default: - halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x8, 0x0); - break; - } - } - - // update pre state - pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; - pCoexDm->prePsTdma = pCoexDm->curPsTdma; -} - - -VOID -halbtc8723a2ant_CoexAllOff( - IN PBTC_COEXIST pBtCoexist - ) -{ - // fw all off - halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - - // sw all off - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - - // hw all off - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); -} - -VOID -halbtc8723a2ant_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ) -{ - // force to reset coex mechanism - halbtc8723a2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0x55555555, 0xffff, 0x3); - halbtc8723a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); - halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 0x20); - halbtc8723a2ant_DecBtPwr(pBtCoexist, FORCE_EXEC, FALSE); - halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); - - halbtc8723a2ant_AgcTable(pBtCoexist, FORCE_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, FORCE_EXEC, FALSE); - halbtc8723a2ant_LowPenaltyRa(pBtCoexist, FORCE_EXEC, FALSE); - halbtc8723a2ant_RfShrink(pBtCoexist, FORCE_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, FORCE_EXEC, FALSE, 0xc0); -} - -VOID -halbtc8723a2ant_BtInquiryPage( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bLowPwrDisable=TRUE; - - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); - - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); -} - -VOID -halbtc8723a2ant_BtEnableAction( - IN PBTC_COEXIST pBtCoexist - ) -{ - BOOLEAN bWifiConnected=FALSE; - - // Here we need to resend some wifi info to BT - // because bt is reset and loss of the info. - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); - if(bWifiConnected) - { - halbtc8723a2ant_IndicateWifiChnlBwInfo(pBtCoexist, BTC_MEDIA_CONNECT); - } - else - { - halbtc8723a2ant_IndicateWifiChnlBwInfo(pBtCoexist, BTC_MEDIA_DISCONNECT); - } - - halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); -} - -VOID -halbtc8723a2ant_MonitorBtCtr( - IN PBTC_COEXIST pBtCoexist - ) -{ - u4Byte regHPTxRx, regLPTxRx, u4Tmp; - u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; - u1Byte u1Tmp; - - regHPTxRx = 0x770; - regLPTxRx = 0x774; - - u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); - regHPTx = u4Tmp & bMaskLWord; - regHPRx = (u4Tmp & bMaskHWord)>>16; - - u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); - regLPTx = u4Tmp & bMaskLWord; - regLPRx = (u4Tmp & bMaskHWord)>>16; - - pCoexSta->highPriorityTx = regHPTx; - pCoexSta->highPriorityRx = regHPRx; - pCoexSta->lowPriorityTx = regLPTx; - pCoexSta->lowPriorityRx = regLPRx; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx)); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx)); - - // reset counter - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); -} - -VOID -halbtc8723a2ant_MonitorBtEnableDisable( - IN PBTC_COEXIST pBtCoexist - ) -{ - static BOOLEAN bPreBtDisabled=FALSE; - static u4Byte btDisableCnt=0; - BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; - - // This function check if bt is disabled - - if( pCoexSta->highPriorityTx == 0 && - pCoexSta->highPriorityRx == 0 && - pCoexSta->lowPriorityTx == 0 && - pCoexSta->lowPriorityRx == 0) - { - bBtActive = FALSE; - } - if( pCoexSta->highPriorityTx == 0xffff && - pCoexSta->highPriorityRx == 0xffff && - pCoexSta->lowPriorityTx == 0xffff && - pCoexSta->lowPriorityRx == 0xffff) - { - bBtActive = FALSE; - } - if(bBtActive) - { - btDisableCnt = 0; - bBtDisabled = FALSE; - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); - } - else - { - btDisableCnt++; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", - btDisableCnt)); - if(btDisableCnt >= 2) - { - bBtDisabled = TRUE; - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); - } - } - if(bPreBtDisabled != bBtDisabled) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", - (bPreBtDisabled ? "disabled":"enabled"), - (bBtDisabled ? "disabled":"enabled"))); - bPreBtDisabled = bBtDisabled; - if(!bBtDisabled) - { - halbtc8723a2ant_BtEnableAction(pBtCoexist); - } - } -} - -BOOLEAN -halbtc8723a2ant_IsCommonAction( - IN PBTC_COEXIST pBtCoexist - ) -{ - PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; - BOOLEAN bCommon=FALSE, bWifiConnected=FALSE; - BOOLEAN bLowPwrDisable=FALSE; - - if(!pStackInfo->bBtLinkExist) - { - bLowPwrDisable = FALSE; - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); - } - else - { - bLowPwrDisable = TRUE; - pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); - } - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); - - if(halbtc8723a2ant_IsWifiIdle(pBtCoexist) && - BT_8723A_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle + Bt idle!!\n")); - - halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - - bCommon = TRUE; - } - else if(!halbtc8723a2ant_IsWifiIdle(pBtCoexist) && - (BT_8723A_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus) ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-idle + BT idle!!\n")); - - halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); - - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - - bCommon = TRUE; - } - else if(halbtc8723a2ant_IsWifiIdle(pBtCoexist) && - (BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle + Bt connected idle!!\n")); - - halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - - bCommon = TRUE; - } - else if(!halbtc8723a2ant_IsWifiIdle(pBtCoexist) && - (BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-idle + Bt connected idle!!\n")); - - halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - - bCommon = TRUE; - } - else if(halbtc8723a2ant_IsWifiIdle(pBtCoexist) && - (BT_8723A_2ANT_BT_STATUS_NON_IDLE == pCoexDm->btStatus) ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle + BT non-idle!!\n")); - - halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - - bCommon = TRUE; - } - else if(halbtc8723a2ant_IsWifiConnectedIdle(pBtCoexist) && - (BT_8723A_2ANT_BT_STATUS_NON_IDLE == pCoexDm->btStatus) ) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected-idle + BT non-idle!!\n")); - - halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - - bCommon = TRUE; - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-idle + BT non-idle!!\n")); - halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); - - bCommon = FALSE; - } - - return bCommon; -} -VOID -halbtc8723a2ant_TdmaDurationAdjust( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bScoHid, - IN BOOLEAN bTxPause, - IN u1Byte maxInterval - ) -{ - static s4Byte up,dn,m,n,WaitCount; - s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration - u1Byte retryCount=0; - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjust()\n")); - - if(pCoexDm->bResetTdmaAdjust) - { - pCoexDm->bResetTdmaAdjust = FALSE; - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); - { - if(bScoHid) - { - if(bTxPause) - { - if(maxInterval == 1) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); - pCoexDm->psTdmaDuAdjType = 13; - } - else if(maxInterval == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - pCoexDm->psTdmaDuAdjType = 14; - } - else if(maxInterval == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - } - else - { - if(maxInterval == 1) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); - pCoexDm->psTdmaDuAdjType = 9; - } - else if(maxInterval == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - pCoexDm->psTdmaDuAdjType = 10; - } - else if(maxInterval == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - } - } - else - { - if(bTxPause) - { - if(maxInterval == 1) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); - pCoexDm->psTdmaDuAdjType = 5; - } - else if(maxInterval == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - pCoexDm->psTdmaDuAdjType = 6; - } - else if(maxInterval == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - } - else - { - if(maxInterval == 1) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); - pCoexDm->psTdmaDuAdjType = 1; - } - else if(maxInterval == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - pCoexDm->psTdmaDuAdjType = 2; - } - else if(maxInterval == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - } - } - } - //============ - up = 0; - dn = 0; - m = 1; - n= 3; - result = 0; - WaitCount = 0; - } - else - { - //accquire the BT TRx retry count from BT_Info byte2 - retryCount = pCoexSta->btRetryCnt; - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], retryCount = %d\n", retryCount)); - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n", - up, dn, m, n, WaitCount)); - result = 0; - WaitCount++; - - if(retryCount == 0) // no retry in the last 2-second duration - { - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if(up >= n) // if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration - { - WaitCount = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); - } - } - else if (retryCount <= 3) // <=3 retry in the last 2-second duration - { - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) // if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration - { - if (WaitCount <= 2) - m++; // ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ - else - m = 1; - - if ( m >= 20) //m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. - m = 20; - - n = 3*m; - up = 0; - dn = 0; - WaitCount = 0; - result = -1; - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); - } - } - else //retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration - { - if (WaitCount == 1) - m++; // ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ - else - m = 1; - - if ( m >= 20) //m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. - m = 20; - - n = 3*m; - up = 0; - dn = 0; - WaitCount = 0; - result = -1; - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); - } - - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], max Interval = %d\n", maxInterval)); - if(maxInterval == 1) - { - if(bTxPause) - { - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); - - if(pCoexDm->curPsTdma == 1) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); - pCoexDm->psTdmaDuAdjType = 5; - } - else if(pCoexDm->curPsTdma == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - pCoexDm->psTdmaDuAdjType = 6; - } - else if(pCoexDm->curPsTdma == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 4) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); - pCoexDm->psTdmaDuAdjType = 8; - } - if(pCoexDm->curPsTdma == 9) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); - pCoexDm->psTdmaDuAdjType = 13; - } - else if(pCoexDm->curPsTdma == 10) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - pCoexDm->psTdmaDuAdjType = 14; - } - else if(pCoexDm->curPsTdma == 11) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 12) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); - pCoexDm->psTdmaDuAdjType = 16; - } - - if(result == -1) - { - if(pCoexDm->curPsTdma == 5) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - pCoexDm->psTdmaDuAdjType = 6; - } - else if(pCoexDm->curPsTdma == 6) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 7) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); - pCoexDm->psTdmaDuAdjType = 8; - } - else if(pCoexDm->curPsTdma == 13) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - pCoexDm->psTdmaDuAdjType = 14; - } - else if(pCoexDm->curPsTdma == 14) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 15) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); - pCoexDm->psTdmaDuAdjType = 16; - } - } - else if (result == 1) - { - if(pCoexDm->curPsTdma == 8) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 7) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - pCoexDm->psTdmaDuAdjType = 6; - } - else if(pCoexDm->curPsTdma == 6) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); - pCoexDm->psTdmaDuAdjType = 5; - } - else if(pCoexDm->curPsTdma == 16) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 15) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - pCoexDm->psTdmaDuAdjType = 14; - } - else if(pCoexDm->curPsTdma == 14) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); - pCoexDm->psTdmaDuAdjType = 13; - } - } - } - else - { - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); - if(pCoexDm->curPsTdma == 5) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); - pCoexDm->psTdmaDuAdjType = 1; - } - else if(pCoexDm->curPsTdma == 6) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - pCoexDm->psTdmaDuAdjType = 2; - } - else if(pCoexDm->curPsTdma == 7) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 8) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); - pCoexDm->psTdmaDuAdjType = 4; - } - if(pCoexDm->curPsTdma == 13) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); - pCoexDm->psTdmaDuAdjType = 9; - } - else if(pCoexDm->curPsTdma == 14) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - pCoexDm->psTdmaDuAdjType = 10; - } - else if(pCoexDm->curPsTdma == 15) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 16) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); - pCoexDm->psTdmaDuAdjType = 12; - } - - if(result == -1) - { - if(pCoexDm->curPsTdma == 1) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - pCoexDm->psTdmaDuAdjType = 2; - } - else if(pCoexDm->curPsTdma == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); - pCoexDm->psTdmaDuAdjType = 4; - } - else if(pCoexDm->curPsTdma == 9) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - pCoexDm->psTdmaDuAdjType = 10; - } - else if(pCoexDm->curPsTdma == 10) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 11) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); - pCoexDm->psTdmaDuAdjType = 12; - } - } - else if (result == 1) - { - if(pCoexDm->curPsTdma == 4) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - pCoexDm->psTdmaDuAdjType = 2; - } - else if(pCoexDm->curPsTdma == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); - pCoexDm->psTdmaDuAdjType = 1; - } - else if(pCoexDm->curPsTdma == 12) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 11) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - pCoexDm->psTdmaDuAdjType = 10; - } - else if(pCoexDm->curPsTdma == 10) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); - pCoexDm->psTdmaDuAdjType = 9; - } - } - } - } - else if(maxInterval == 2) - { - if(bTxPause) - { - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); - if(pCoexDm->curPsTdma == 1) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - pCoexDm->psTdmaDuAdjType = 6; - } - else if(pCoexDm->curPsTdma == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - pCoexDm->psTdmaDuAdjType = 6; - } - else if(pCoexDm->curPsTdma == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 4) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); - pCoexDm->psTdmaDuAdjType = 8; - } - if(pCoexDm->curPsTdma == 9) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - pCoexDm->psTdmaDuAdjType = 14; - } - else if(pCoexDm->curPsTdma == 10) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - pCoexDm->psTdmaDuAdjType = 14; - } - else if(pCoexDm->curPsTdma == 11) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 12) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); - pCoexDm->psTdmaDuAdjType = 16; - } - if(result == -1) - { - if(pCoexDm->curPsTdma == 5) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - pCoexDm->psTdmaDuAdjType = 6; - } - else if(pCoexDm->curPsTdma == 6) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 7) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); - pCoexDm->psTdmaDuAdjType = 8; - } - else if(pCoexDm->curPsTdma == 13) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - pCoexDm->psTdmaDuAdjType = 14; - } - else if(pCoexDm->curPsTdma == 14) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 15) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); - pCoexDm->psTdmaDuAdjType = 16; - } - } - else if (result == 1) - { - if(pCoexDm->curPsTdma == 8) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 7) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - pCoexDm->psTdmaDuAdjType = 6; - } - else if(pCoexDm->curPsTdma == 6) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - pCoexDm->psTdmaDuAdjType = 6; - } - else if(pCoexDm->curPsTdma == 16) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 15) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - pCoexDm->psTdmaDuAdjType = 14; - } - else if(pCoexDm->curPsTdma == 14) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - pCoexDm->psTdmaDuAdjType = 14; - } - } - } - else - { - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); - if(pCoexDm->curPsTdma == 5) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - pCoexDm->psTdmaDuAdjType = 2; - } - else if(pCoexDm->curPsTdma == 6) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - pCoexDm->psTdmaDuAdjType = 2; - } - else if(pCoexDm->curPsTdma == 7) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 8) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); - pCoexDm->psTdmaDuAdjType = 4; - } - if(pCoexDm->curPsTdma == 13) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - pCoexDm->psTdmaDuAdjType = 10; - } - else if(pCoexDm->curPsTdma == 14) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - pCoexDm->psTdmaDuAdjType = 10; - } - else if(pCoexDm->curPsTdma == 15) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 16) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); - pCoexDm->psTdmaDuAdjType = 12; - } - if(result == -1) - { - if(pCoexDm->curPsTdma == 1) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - pCoexDm->psTdmaDuAdjType = 2; - } - else if(pCoexDm->curPsTdma == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); - pCoexDm->psTdmaDuAdjType = 4; - } - else if(pCoexDm->curPsTdma == 9) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - pCoexDm->psTdmaDuAdjType = 10; - } - else if(pCoexDm->curPsTdma == 10) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 11) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); - pCoexDm->psTdmaDuAdjType = 12; - } - } - else if (result == 1) - { - if(pCoexDm->curPsTdma == 4) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - pCoexDm->psTdmaDuAdjType = 2; - } - else if(pCoexDm->curPsTdma == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - pCoexDm->psTdmaDuAdjType = 2; - } - else if(pCoexDm->curPsTdma == 12) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 11) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - pCoexDm->psTdmaDuAdjType = 10; - } - else if(pCoexDm->curPsTdma == 10) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - pCoexDm->psTdmaDuAdjType = 10; - } - } - } - } - else if(maxInterval == 3) - { - if(bTxPause) - { - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); - if(pCoexDm->curPsTdma == 1) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 4) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); - pCoexDm->psTdmaDuAdjType = 8; - } - if(pCoexDm->curPsTdma == 9) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 10) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 11) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 12) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); - pCoexDm->psTdmaDuAdjType = 16; - } - if(result == -1) - { - if(pCoexDm->curPsTdma == 5) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 6) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 7) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); - pCoexDm->psTdmaDuAdjType = 8; - } - else if(pCoexDm->curPsTdma == 13) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 14) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 15) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); - pCoexDm->psTdmaDuAdjType = 16; - } - } - else if (result == 1) - { - if(pCoexDm->curPsTdma == 8) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 7) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 6) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); - pCoexDm->psTdmaDuAdjType = 7; - } - else if(pCoexDm->curPsTdma == 16) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 15) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - else if(pCoexDm->curPsTdma == 14) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - pCoexDm->psTdmaDuAdjType = 15; - } - } - } - else - { - RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); - if(pCoexDm->curPsTdma == 5) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 6) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 7) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 8) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); - pCoexDm->psTdmaDuAdjType = 4; - } - if(pCoexDm->curPsTdma == 13) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 14) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 15) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 16) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); - pCoexDm->psTdmaDuAdjType = 12; - } - if(result == -1) - { - if(pCoexDm->curPsTdma == 1) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); - pCoexDm->psTdmaDuAdjType = 4; - } - else if(pCoexDm->curPsTdma == 9) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 10) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 11) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); - pCoexDm->psTdmaDuAdjType = 12; - } - } - else if (result == 1) - { - if(pCoexDm->curPsTdma == 4) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 3) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 2) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); - pCoexDm->psTdmaDuAdjType = 3; - } - else if(pCoexDm->curPsTdma == 12) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 11) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - else if(pCoexDm->curPsTdma == 10) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - pCoexDm->psTdmaDuAdjType = 11; - } - } - } - } - } - - // if current PsTdma not match with the recorded one (when scan, dhcp...), - // then we have to adjust it back to the previous record one. - if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType) - { - BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n", - pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType)); - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); - - if( !bScan && !bLink && !bRoam) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n")); - } - } -} - -// SCO only or SCO+PAN(HS) -VOID -halbtc8723a2ant_ActionSco( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState, wifiRssiState1; - u4Byte wifiBw; - - if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); - else - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - } - else - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - } - - // sw mechanism - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); - wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); - } - else - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); - } - - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - } -} - - -VOID -halbtc8723a2ant_ActionHid( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState, wifiRssiState1; - u4Byte wifiBw; - - if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); - else - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); - } - else - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); - } - - // sw mechanism - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); - wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); - } - else - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); - } - - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - } -} - -//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) -VOID -halbtc8723a2ant_ActionA2dp( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState, wifiRssiState1, btInfoExt; - u4Byte wifiBw; - - btInfoExt = pCoexSta->btInfoExt; - - if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); - else - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); - } - else - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1); - } - } - else - { - if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); - } - else - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1); - } - } - - // sw mechanism - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); - wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); - } - else - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1); - } - } - else - { - if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); - } - else - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1); - } - } - - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - } -} - -VOID -halbtc8723a2ant_ActionPanEdr( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState, wifiRssiState1, btInfoExt; - u4Byte wifiBw; - - btInfoExt = pCoexSta->btInfoExt; - - if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); - else - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - } - else - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - } - - // sw mechanism - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); - wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - } - else - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - } - - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - } -} - - -//PAN(HS) only -VOID -halbtc8723a2ant_ActionPanHs( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState; - u4Byte wifiBw; - - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); - } - else - { - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - } - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - - // sw mechanism - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - } - else - { - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); - } - - // sw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - } -} - -//PAN(EDR)+A2DP -VOID -halbtc8723a2ant_ActionPanEdrA2dp( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState, wifiRssiState1, btInfoExt; - u4Byte wifiBw; - - btInfoExt = pCoexSta->btInfoExt; - - if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); - else - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - if(btInfoExt&BIT0) //a2dp basic rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); - } - else //a2dp edr rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - } - } - else - { - if(btInfoExt&BIT0) //a2dp basic rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); - } - else //a2dp edr rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - } - } - - // sw mechanism - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); - wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - if(btInfoExt&BIT0) //a2dp basic rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); - } - else //a2dp edr rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); - } - } - else - { - if(btInfoExt&BIT0) //a2dp basic rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); - } - else //a2dp edr rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); - } - } - - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - } -} - -VOID -halbtc8723a2ant_ActionPanEdrHid( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState, wifiRssiState1; - u4Byte wifiBw; - - if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); - else - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - } - else - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - } - - // sw mechanism - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); - wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - } - else - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - } - - // sw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - } -} - -// HID+A2DP+PAN(EDR) -VOID -halbtc8723a2ant_ActionHidA2dpPanEdr( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState, wifiRssiState1, btInfoExt; - u4Byte wifiBw; - - btInfoExt = pCoexSta->btInfoExt; - - if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); - else - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - if(btInfoExt&BIT0) //a2dp basic rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); - } - else //a2dp edr rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - } - } - else - { - if(btInfoExt&BIT0) //a2dp basic rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); - } - else //a2dp edr rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - } - } - - // sw mechanism - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); - wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - if(btInfoExt&BIT0) //a2dp basic rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); - } - else //a2dp edr rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); - } - } - else - { - if(btInfoExt&BIT0) //a2dp basic rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); - } - else //a2dp edr rate - { - halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); - } - } - - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - } -} - -VOID -halbtc8723a2ant_ActionHidA2dp( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte wifiRssiState, wifiRssiState1, btInfoExt; - u4Byte wifiBw; - - btInfoExt = pCoexSta->btInfoExt; - - if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); - else - halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); - if(BTC_WIFI_BW_HT40 == wifiBw) - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - if(btInfoExt&BIT0) //a2dp basic rate - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); - } - else //a2dp edr rate - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 1); - } - } - else - { - if(btInfoExt&BIT0) //a2dp basic rate - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); - } - else //a2dp edr rate - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 1); - } - } - - // sw mechanism - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); - wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); - - // fw mechanism - if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || - (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) - { - if(btInfoExt&BIT0) //a2dp basic rate - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); - } - else //a2dp edr rate - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 1); - } - } - else - { - if(btInfoExt&BIT0) //a2dp basic rate - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); - } - else //a2dp edr rate - { - halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 1); - } - } - - // sw mechanism - if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || - (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - else - { - halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); - halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); - } - } -} - -VOID -halbtc8723a2ant_RunCoexistMechanism( - IN PBTC_COEXIST pBtCoexist - ) -{ - PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; - u1Byte btInfoOriginal=0, btRetryCnt=0; - u1Byte algorithm=0; - - if(pBtCoexist->bManualControl) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Manual control!!!\n")); - return; - } - - if(pStackInfo->bProfileNotified) - { - if(pCoexSta->bHoldForStackOperation) - { - // if bt inquiry/page/pair, do not execute. - return; - } - - algorithm = halbtc8723a2ant_ActionAlgorithm(pBtCoexist); - if(pCoexSta->bHoldPeriodCnt && (BT_8723A_2ANT_COEX_ALGO_PANHS!=algorithm)) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex],Hold BT inquiry/page scan setting (cnt = %d)!!\n", - pCoexSta->bHoldPeriodCnt)); - if(pCoexSta->bHoldPeriodCnt >= 6) - { - pCoexSta->bHoldPeriodCnt = 0; - // next time the coexist parameters should be reset again. - } - else - pCoexSta->bHoldPeriodCnt++; - return; - } - - pCoexDm->curAlgorithm = algorithm; - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Algorithm = %d \n", pCoexDm->curAlgorithm)); - if(halbtc8723a2ant_IsCommonAction(pBtCoexist)) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant common.\n")); - pCoexDm->bResetTdmaAdjust = TRUE; - } - else - { - if(pCoexDm->curAlgorithm != pCoexDm->preAlgorithm) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], preAlgorithm=%d, curAlgorithm=%d\n", - pCoexDm->preAlgorithm, pCoexDm->curAlgorithm)); - pCoexDm->bResetTdmaAdjust = TRUE; - } - switch(pCoexDm->curAlgorithm) - { - case BT_8723A_2ANT_COEX_ALGO_SCO: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO.\n")); - halbtc8723a2ant_ActionSco(pBtCoexist); - break; - case BT_8723A_2ANT_COEX_ALGO_HID: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID.\n")); - halbtc8723a2ant_ActionHid(pBtCoexist); - break; - case BT_8723A_2ANT_COEX_ALGO_A2DP: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP.\n")); - halbtc8723a2ant_ActionA2dp(pBtCoexist); - break; - case BT_8723A_2ANT_COEX_ALGO_PANEDR: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n")); - halbtc8723a2ant_ActionPanEdr(pBtCoexist); - break; - case BT_8723A_2ANT_COEX_ALGO_PANHS: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HS mode.\n")); - halbtc8723a2ant_ActionPanHs(pBtCoexist); - break; - case BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n")); - halbtc8723a2ant_ActionPanEdrA2dp(pBtCoexist); - break; - case BT_8723A_2ANT_COEX_ALGO_PANEDR_HID: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n")); - halbtc8723a2ant_ActionPanEdrHid(pBtCoexist); - break; - case BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n")); - halbtc8723a2ant_ActionHidA2dpPanEdr(pBtCoexist); - break; - case BT_8723A_2ANT_COEX_ALGO_HID_A2DP: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n")); - halbtc8723a2ant_ActionHidA2dp(pBtCoexist); - break; - default: - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n")); - halbtc8723a2ant_CoexAllOff(pBtCoexist); - break; - } - pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; - } - } -} - -//============================================================ -// work around function start with wa_halbtc8723a2ant_ -//============================================================ -VOID -wa_halbtc8723a2ant_MonitorC2h( - IN PBTC_COEXIST pBtCoexist - ) -{ - u1Byte tmp1b=0x0; - u4Byte curC2hTotalCnt=0x0; - static u4Byte preC2hTotalCnt=0x0, sameCntPollingTime=0x0; - - curC2hTotalCnt+=pCoexSta->btInfoC2hCnt[BT_INFO_SRC_8723A_2ANT_BT_RSP]; - - if(curC2hTotalCnt == preC2hTotalCnt) - { - sameCntPollingTime++; - } - else - { - preC2hTotalCnt = curC2hTotalCnt; - sameCntPollingTime = 0; - } - - if(sameCntPollingTime >= 2) - { - tmp1b = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x1af); - if(tmp1b != 0x0) - { - pCoexSta->c2hHangDetectCnt++; - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x1af, 0x0); - } - } -} - -//============================================================ -// extern function start with EXhalbtc8723a2ant_ -//============================================================ -VOID -EXhalbtc8723a2ant_PowerOnSetting( - IN PBTC_COEXIST pBtCoexist - ) -{ -} - -VOID -EXhalbtc8723a2ant_InitHwConfig( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bWifiOnly - ) -{ - u4Byte u4Tmp=0; - u1Byte u1Tmp=0; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n")); - - // backup rf 0x1e value - pCoexDm->btRf0x1eBackup = - pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); - - // Enable counter statistics - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x3); - pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x20); -} - -VOID -EXhalbtc8723a2ant_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ) -{ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); - - halbtc8723a2ant_InitCoexDm(pBtCoexist); -} - -VOID -EXhalbtc8723a2ant_DisplayCoexInfo( - IN PBTC_COEXIST pBtCoexist - ) -{ - PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; - PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; - pu1Byte cliBuf=pBtCoexist->cliBuf; - u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; - u4Byte u4Tmp[4]; - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ - pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); - CL_PRINTF(cliBuf); - - if(pBtCoexist->bManualControl) - { - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!"); - CL_PRINTF(cliBuf); - } - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ - ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ - pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], - pCoexDm->wifiChnlInfo[2]); - CL_PRINTF(cliBuf); - - // wifi status - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); - CL_PRINTF(cliBuf); - pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \ - ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8723A_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus)? "idle":( (BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy"))), - pCoexSta->btRssi, pCoexSta->btRetryCnt); - CL_PRINTF(cliBuf); - - if(pStackInfo->bProfileNotified) - { - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ - pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist); - CL_PRINTF(cliBuf); - - pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); - } - - btInfoExt = pCoexSta->btInfoExt; - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \ - (btInfoExt&BIT0)? "Basic rate":"EDR rate"); - CL_PRINTF(cliBuf); - - for(i=0; ibtInfoC2hCnt[i]) - { - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8723a2Ant[i], \ - pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], - pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], - pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], - pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); - CL_PRINTF(cliBuf); - } - } - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "write 0x1af=0x0 num", \ - pCoexSta->c2hHangDetectCnt); - CL_PRINTF(cliBuf); - - // Sw mechanism - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); - CL_PRINTF(cliBuf); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "SM1[ShRf/ LpRA/ LimDig]", \ - pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->bLimitedDig); - CL_PRINTF(cliBuf); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ - pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl); - CL_PRINTF(cliBuf); - - // Fw mechanism - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); - CL_PRINTF(cliBuf); - - if(!pBtCoexist->bManualControl) - { - psTdmaCase = pCoexDm->curPsTdma; - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", "PS TDMA", \ - pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], - pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], - pCoexDm->psTdmaPara[4], psTdmaCase); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "DecBtPwr/ IgnWlanAct", \ - pCoexDm->bCurDecBtPwr, pCoexDm->bCurIgnoreWlanAct); - CL_PRINTF(cliBuf); - } - - // Hw setting - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ - pCoexDm->btRf0x1eBackup); - CL_PRINTF(cliBuf); - - u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); - u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x783); - u1Tmp[2] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x796); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x778/ 0x783/ 0x796", \ - u1Tmp[0], u1Tmp[1], u1Tmp[2]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x880); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x880", \ - u4Tmp[0]); - CL_PRINTF(cliBuf); - - u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \ - u1Tmp[0]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); - u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ - u4Tmp[0], u1Tmp[0]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x484); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x484(rate adaptive)", \ - u4Tmp[0]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \ - u4Tmp[0]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda0); - u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda4); - u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda8); - u4Tmp[3] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xdac); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0xda0/0xda4/0xda8/0xdac(FA cnt)", \ - u4Tmp[0], u4Tmp[1], u4Tmp[2], u4Tmp[3]); - CL_PRINTF(cliBuf); - - u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); - u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); - u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); - u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \ - u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]); - CL_PRINTF(cliBuf); - - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770 (hp rx[31:16]/tx[15:0])", \ - pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); - CL_PRINTF(cliBuf); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \ - pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); - CL_PRINTF(cliBuf); - - pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -VOID -EXhalbtc8723a2ant_IpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_IPS_ENTER == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); - halbtc8723a2ant_CoexAllOff(pBtCoexist); - } - else if(BTC_IPS_LEAVE == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); - //halbtc8723a2ant_InitCoexDm(pBtCoexist); - } -} - -VOID -EXhalbtc8723a2ant_LpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_LPS_ENABLE == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); - } - else if(BTC_LPS_DISABLE == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); - } -} - -VOID -EXhalbtc8723a2ant_ScanNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_SCAN_START == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); - } - else if(BTC_SCAN_FINISH == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); - } -} - -VOID -EXhalbtc8723a2ant_ConnectNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_ASSOCIATE_START == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); - } - else if(BTC_ASSOCIATE_FINISH == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); - } -} - -VOID -EXhalbtc8723a2ant_MediaStatusNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_MEDIA_CONNECT == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); - } - - halbtc8723a2ant_IndicateWifiChnlBwInfo(pBtCoexist, type); -} - -VOID -EXhalbtc8723a2ant_SpecialPacketNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(type == BTC_PACKET_DHCP) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); - } -} - -VOID -EXhalbtc8723a2ant_BtInfoNotify( - IN PBTC_COEXIST pBtCoexist, - IN pu1Byte tmpBuf, - IN u1Byte length - ) -{ - u1Byte btInfo=0; - u1Byte i, rspSource=0; - BOOLEAN bBtBusy=FALSE, bLimitedDig=FALSE; - BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; - - pCoexSta->bC2hBtInfoReqSent = FALSE; - - rspSource = BT_INFO_SRC_8723A_2ANT_BT_RSP; - pCoexSta->btInfoC2hCnt[rspSource]++; - - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); - for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; - if(i == 0) - btInfo = tmpBuf[i]; - if(i == length-1) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); - } - else - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); - } - } - - if(BT_INFO_SRC_8723A_2ANT_WIFI_FW != rspSource) - { - pCoexSta->btRetryCnt = - pCoexSta->btInfoC2h[rspSource][1]; - - pCoexSta->btRssi = - pCoexSta->btInfoC2h[rspSource][2]*2+10; - - pCoexSta->btInfoExt = - pCoexSta->btInfoC2h[rspSource][3]; - } - - pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); - // check BIT2 first ==> check if bt is under inquiry or page scan - if(btInfo & BT_INFO_8723A_2ANT_B_INQ_PAGE) - { - pCoexSta->bC2hBtInquiryPage = TRUE; - } - else - { - pCoexSta->bC2hBtInquiryPage = FALSE; - } -} - -VOID -EXhalbtc8723a2ant_StackOperationNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ) -{ - if(BTC_STACK_OP_INQ_PAGE_PAIR_START == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], StackOP Inquiry/page/pair start notify\n")); - pCoexSta->bHoldForStackOperation = TRUE; - pCoexSta->bHoldPeriodCnt = 1; - halbtc8723a2ant_BtInquiryPage(pBtCoexist); - } - else if(BTC_STACK_OP_INQ_PAGE_PAIR_FINISH == type) - { - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], StackOP Inquiry/page/pair finish notify\n")); - pCoexSta->bHoldForStackOperation = FALSE; - } -} - -VOID -EXhalbtc8723a2ant_HaltNotify( - IN PBTC_COEXIST pBtCoexist - ) -{ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); - - halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); - EXhalbtc8723a2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); -} - -VOID -EXhalbtc8723a2ant_Periodical( - IN PBTC_COEXIST pBtCoexist - ) -{ - RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Periodical!!\n")); - - // work around for c2h hang - wa_halbtc8723a2ant_MonitorC2h(pBtCoexist); - - halbtc8723a2ant_QueryBtInfo(pBtCoexist); - halbtc8723a2ant_MonitorBtCtr(pBtCoexist); - halbtc8723a2ant_MonitorBtEnableDisable(pBtCoexist); - - halbtc8723a2ant_RunCoexistMechanism(pBtCoexist); -} - - -#endif - diff --git a/hal/btc/HalBtc8723a2Ant.h b/hal/btc/HalBtc8723a2Ant.h deleted file mode 100644 index d5d5488..0000000 --- a/hal/btc/HalBtc8723a2Ant.h +++ /dev/null @@ -1,184 +0,0 @@ -//=========================================== -// The following is for 8723A 2Ant BT Co-exist definition -//=========================================== -#define BT_INFO_8723A_2ANT_B_FTP BIT7 -#define BT_INFO_8723A_2ANT_B_A2DP BIT6 -#define BT_INFO_8723A_2ANT_B_HID BIT5 -#define BT_INFO_8723A_2ANT_B_SCO_BUSY BIT4 -#define BT_INFO_8723A_2ANT_B_ACL_BUSY BIT3 -#define BT_INFO_8723A_2ANT_B_INQ_PAGE BIT2 -#define BT_INFO_8723A_2ANT_B_SCO_ESCO BIT1 -#define BT_INFO_8723A_2ANT_B_CONNECTION BIT0 - -#define BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT 2 - -typedef enum _BT_INFO_SRC_8723A_2ANT{ - BT_INFO_SRC_8723A_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8723A_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8723A_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8723A_2ANT_MAX -}BT_INFO_SRC_8723A_2ANT,*PBT_INFO_SRC_8723A_2ANT; - -typedef enum _BT_8723A_2ANT_BT_STATUS{ - BT_8723A_2ANT_BT_STATUS_IDLE = 0x0, - BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8723A_2ANT_BT_STATUS_NON_IDLE = 0x2, - BT_8723A_2ANT_BT_STATUS_MAX -}BT_8723A_2ANT_BT_STATUS,*PBT_8723A_2ANT_BT_STATUS; - -typedef enum _BT_8723A_2ANT_COEX_ALGO{ - BT_8723A_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8723A_2ANT_COEX_ALGO_SCO = 0x1, - BT_8723A_2ANT_COEX_ALGO_HID = 0x2, - BT_8723A_2ANT_COEX_ALGO_A2DP = 0x3, - BT_8723A_2ANT_COEX_ALGO_PANEDR = 0x4, - BT_8723A_2ANT_COEX_ALGO_PANHS = 0x5, - BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x6, - BT_8723A_2ANT_COEX_ALGO_PANEDR_HID = 0x7, - BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8, - BT_8723A_2ANT_COEX_ALGO_HID_A2DP = 0x9, - BT_8723A_2ANT_COEX_ALGO_MAX -}BT_8723A_2ANT_COEX_ALGO,*PBT_8723A_2ANT_COEX_ALGO; - -typedef struct _COEX_DM_8723A_2ANT{ - // fw mechanism - BOOLEAN bPreDecBtPwr; - BOOLEAN bCurDecBtPwr; - //BOOLEAN bPreBtLnaConstrain; - //BOOLEAN bCurBtLnaConstrain; - //u1Byte bPreBtPsdMode; - //u1Byte bCurBtPsdMode; - u1Byte preFwDacSwingLvl; - u1Byte curFwDacSwingLvl; - BOOLEAN bCurIgnoreWlanAct; - BOOLEAN bPreIgnoreWlanAct; - u1Byte prePsTdma; - u1Byte curPsTdma; - u1Byte psTdmaPara[5]; - u1Byte psTdmaDuAdjType; - BOOLEAN bResetTdmaAdjust; - BOOLEAN bPrePsTdmaOn; - BOOLEAN bCurPsTdmaOn; - //BOOLEAN bPreBtAutoReport; - //BOOLEAN bCurBtAutoReport; - - // sw mechanism - BOOLEAN bPreRfRxLpfShrink; - BOOLEAN bCurRfRxLpfShrink; - u4Byte btRf0x1eBackup; - BOOLEAN bPreLowPenaltyRa; - BOOLEAN bCurLowPenaltyRa; - BOOLEAN bPreDacSwingOn; - u4Byte preDacSwingLvl; - BOOLEAN bCurDacSwingOn; - u4Byte curDacSwingLvl; - BOOLEAN bPreAdcBackOff; - BOOLEAN bCurAdcBackOff; - BOOLEAN bPreAgcTableEn; - BOOLEAN bCurAgcTableEn; - u4Byte preVal0x6c0; - u4Byte curVal0x6c0; - u4Byte preVal0x6c8; - u4Byte curVal0x6c8; - u1Byte preVal0x6cc; - u1Byte curVal0x6cc; - BOOLEAN bLimitedDig; - - // algorithm related - u1Byte preAlgorithm; - u1Byte curAlgorithm; - u1Byte btStatus; - u1Byte wifiChnlInfo[3]; -} COEX_DM_8723A_2ANT, *PCOEX_DM_8723A_2ANT; - -typedef struct _COEX_STA_8723A_2ANT{ - u4Byte highPriorityTx; - u4Byte highPriorityRx; - u4Byte lowPriorityTx; - u4Byte lowPriorityRx; - u1Byte btRssi; - u1Byte preBtRssiState; - u1Byte preBtRssiState1; - u1Byte preWifiRssiState[4]; - BOOLEAN bC2hBtInfoReqSent; - u1Byte btInfoC2h[BT_INFO_SRC_8723A_2ANT_MAX][10]; - u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_2ANT_MAX]; - BOOLEAN bC2hBtInquiryPage; - u1Byte btRetryCnt; - u1Byte btInfoExt; - BOOLEAN bHoldForStackOperation; - u1Byte bHoldPeriodCnt; - // this is for c2h hang work-around - u4Byte c2hHangDetectCnt; -}COEX_STA_8723A_2ANT, *PCOEX_STA_8723A_2ANT; - -//=========================================== -// The following is interface which will notify coex module. -//=========================================== -VOID -EXhalbtc8723a2ant_PowerOnSetting( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8723a2ant_InitHwConfig( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bWifiOnly - ); -VOID -EXhalbtc8723a2ant_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8723a2ant_IpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a2ant_LpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a2ant_ScanNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a2ant_ConnectNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a2ant_MediaStatusNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a2ant_SpecialPacketNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a2ant_HaltNotify( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8723a2ant_Periodical( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtc8723a2ant_BtInfoNotify( - IN PBTC_COEXIST pBtCoexist, - IN pu1Byte tmpBuf, - IN u1Byte length - ); -VOID -EXhalbtc8723a2ant_StackOperationNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtc8723a2ant_DisplayCoexInfo( - IN PBTC_COEXIST pBtCoexist - ); - diff --git a/hal/btc/HalBtc8723b1Ant.c b/hal/btc/HalBtc8723b1Ant.c deleted file mode 100644 index a15a601..0000000 --- a/hal/btc/HalBtc8723b1Ant.c +++ /dev/null @@ -1,4845 +0,0 @@ -/* ************************************************************ - * Description: - * - * This file is for RTL8723B Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "Mp_Precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8723B_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8723b_1ant glcoex_dm_8723b_1ant; -static struct coex_dm_8723b_1ant *coex_dm = &glcoex_dm_8723b_1ant; -static struct coex_sta_8723b_1ant glcoex_sta_8723b_1ant; -static struct coex_sta_8723b_1ant *coex_sta = &glcoex_sta_8723b_1ant; -static struct psdscan_sta_8723b_1ant gl_psd_scan_8723b_1ant; -static struct psdscan_sta_8723b_1ant *psd_scan = &gl_psd_scan_8723b_1ant; - - -const char *const glbt_info_src_8723b_1ant[]={ - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8723b_1ant = 20151015; -u32 glcoex_ver_8723b_1ant = 0x63; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8723b1ant_ - * ************************************************************ */ - -void halbtc8723b1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if( force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8723b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8723b1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8723b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8723b1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8723b1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8723b1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8723b1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8723b1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8723b1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8723b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8723b1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8723b1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -void halbtc8723b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u32 num_of_bt_counter_chk = 0; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if ((coex_sta->low_priority_tx > 1050) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - /* This part is for wifi FW and driver to update BT's status as disabled. */ - /* The flow is as the following */ - /* 1. disable BT */ - /* 2. if all BT Tx/Rx counter=0, after 6 sec we query bt info */ - /* 3. Because BT will not rsp from mailbox, so wifi fw will know BT is disabled */ - /* 4. FW will rsp c2h for BT that driver will know BT is disabled. */ - if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) && - (reg_lp_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk == 3) - halbtc8723b1ant_query_bt_info(btcoexist); - } else - num_of_bt_counter_chk = 0; -} - - -void halbtc8723b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false; - static u8 cck_lock_counter = 0; - u32 total_cnt; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - if (coex_sta->under_ips) { - coex_sta->crc_ok_cck = 0; - coex_sta->crc_ok_11g = 0; - coex_sta->crc_ok_11n = 0; - coex_sta->crc_ok_11n_agg = 0; - - coex_sta->crc_err_cck = 0; - coex_sta->crc_err_11g = 0; - coex_sta->crc_err_11n = 0; - coex_sta->crc_err_11n_agg = 0; - } else { - coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf88); - coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf94); - coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf90); - coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfb8); - - coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf84); - coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf96); - coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf92); - coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfba); - } - - - /* reset counter */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0); - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + - coex_sta->crc_ok_11n_agg; - - if ( (coex_dm->bt_status == BT_8723B_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == - BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == - BT_8723B_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - -coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 3) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = true; - - coex_sta->pre_ccklock = coex_sta->cck_lock; - - -} - -boolean halbtc8723b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - - - } - - return false; -} - -void halbtc8723b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->bt_hi_pri_link_exist = coex_sta->bt_hi_pri_link_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if( bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist ) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if( !bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist ) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if( !bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist ) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if( !bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist ) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -void halbtc8723b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8723b1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8723b1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8723b1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8723b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8723b1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8723b1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8723b1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8723b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8723b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - -#if BT_8723B_1ANT_ANTDET_ENABLE -#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE - if (board_info->btdm_ant_num_by_ant_det == 2) { - if (type == 3) - type = 14; - else if (type == 4) - type = 13; - else if (type == 5) - type = 8; - } -#endif -#endif - - coex_sta->coex_table_type = type; - - switch (type) { - case 0: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, 0xffffff, 0x3); - break; - case 1: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 2: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 3: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 4: - if ((coex_sta->cck_ever_lock) && - (coex_sta->scan_ap_num <= 5)) - halbtc8723b1ant_coex_table(btcoexist, - force_exec, 0x55555555, 0xaaaa5a5a, - 0xffffff, 0x3); - else - halbtc8723b1ant_coex_table(btcoexist, - force_exec, 0x55555555, 0x5a5a5a5a, - 0xffffff, 0x3); - break; - case 5: - if ((coex_sta->cck_ever_lock) && - (coex_sta->scan_ap_num <= 5)) - halbtc8723b1ant_coex_table(btcoexist, - force_exec, 0x5a5a5a5a, 0x5aaa5a5a, - 0xffffff, 0x3); - else - halbtc8723b1ant_coex_table(btcoexist, - force_exec, 0x5a5a5a5a, 0x5aaa5a5a, - 0xffffff, 0x3); - break; - case 6: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 7: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 8: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 9: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 10: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 11: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 12: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 13: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 14: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); - break; - case 15: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8723b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8723b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8723b1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8723b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8723b1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8723b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8723b1ant_sw_mechanism(IN struct btc_coexist *btcoexist, - IN boolean low_penalty_ra) -{ - halbtc8723b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8723b1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg, - IN boolean wifi_off) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u32 fw_ver = 0, u32tmp = 0, cnt_bt_cal_chk = 0; - boolean pg_ext_switch = false; - boolean use_ext_switch = false; - boolean is_in_mp_mode = false; - u8 h2c_parameter[2] = {0}, u8tmp = 0; - - coex_dm->cur_ant_pos_type = ant_pos_type; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_EXT_SWITCH, &pg_ext_switch); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, - &fw_ver); /* [31:16]=fw ver, [15:0]=fw sub ver */ - - if ((fw_ver > 0 && fw_ver < 0xc0000) || pg_ext_switch) - use_ext_switch = true; - -#if BT_8723B_1ANT_ANTDET_ENABLE -#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE - if (ant_pos_type == BTC_ANT_PATH_PTA) { - if ((board_info->btdm_ant_det_finish) && - (board_info->btdm_ant_num_by_ant_det == 2)) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = BTC_ANT_PATH_WIFI; - else - ant_pos_type = BTC_ANT_PATH_BT; - } - } -#endif -#endif - - if (init_hwcfg) { - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x780); /* WiFi TRx Mask on */ - /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */ - /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); //BT TRx Mask on */ - - if (fw_ver >= 0x180000) { - /* Use H2C to set GNT_BT to HIGH */ - h2c_parameter[0] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, - h2c_parameter); - } else { - /* set grant_bt to high */ - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); - } - /* set wlan_act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x0); /* BT select s0/s1 is controlled by BT */ - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x39, 0x8, 0x1); - btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x944, 0x3, 0x3); - btcoexist->btc_write_1byte(btcoexist, 0x930, 0x77); - } else if (wifi_off) { - if (fw_ver >= 0x180000) { - /* Use H2C to set GNT_BT to HIGH */ - h2c_parameter[0] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, - h2c_parameter); - } else { - /* set grant_bt to high */ - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); - } - /* set wlan_act to always low */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE, - &is_in_mp_mode); - if (!is_in_mp_mode) - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, - 0x20, 0x0); /* BT select s0/s1 is controlled by BT */ - else - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, - 0x20, 0x1); /* BT select s0/s1 is controlled by WiFi */ - - /* 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL BT Vendor 0xac=0xf002 */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp &= ~BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } else { - /* Use H2C to set GNT_BT to LOW */ - if (fw_ver >= 0x180000) { - if (btcoexist->btc_read_1byte(btcoexist, 0x765) != 0) { - h2c_parameter[0] = 0; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, - h2c_parameter); - } - } else { - /* BT calibration check */ - while (cnt_bt_cal_chk <= 20) { - u8tmp = btcoexist->btc_read_1byte(btcoexist, - 0x49d); - cnt_bt_cal_chk++; - if (u8tmp & BIT(0)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - delay_ms(50); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - break; - } - } - - /* set grant_bt to PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x0); - } - - if (btcoexist->btc_read_1byte(btcoexist, 0x76e) != 0xc) { - /* set wlan_act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - } - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x1); /* BT select s0/s1 is controlled by WiFi */ - } - - if (use_ext_switch) { - if (init_hwcfg) { - /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp |= BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - - btcoexist->btc_write_4byte(btcoexist, 0x948, - 0x0); /* fixed internal switch S1->WiFi, S0->BT */ - - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - /* tell firmware "no antenna inverse" */ - h2c_parameter[0] = 0; - h2c_parameter[1] = 1; /* ext switch type */ - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } else { - /* tell firmware "antenna inverse" */ - h2c_parameter[0] = 1; - h2c_parameter[1] = 1; /* ext switch type */ - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } - } - - if (force_exec || - (coex_dm->cur_ant_pos_type != - coex_dm->pre_ant_pos_type)) { - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x92c, 0x3, - 0x1); - else - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x92c, 0x3, - 0x2); - break; - case BTC_ANT_PATH_BT: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x92c, 0x3, - 0x2); - else - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x92c, 0x3, - 0x1); - break; - default: - case BTC_ANT_PATH_PTA: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x92c, 0x3, - 0x1); - else - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x92c, 0x3, - 0x2); - break; - } - } - } else { - if (init_hwcfg) { - /* 0x4c[23]=1, 0x4c[24]=0 Antenna control by 0x64 */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp |= BIT(23); - u32tmp &= ~BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - - /* Fix Ext switch Main->S1, Aux->S0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, - 0x0); - - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - - /* tell firmware "no antenna inverse" */ - h2c_parameter[0] = 0; - h2c_parameter[1] = - 0; /* internal switch type */ - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } else { - - /* tell firmware "antenna inverse" */ - h2c_parameter[0] = 1; - h2c_parameter[1] = - 0; /* internal switch type */ - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } - } - - if (force_exec || - (coex_dm->cur_ant_pos_type != - coex_dm->pre_ant_pos_type)) { - /* internal switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_4byte( - btcoexist, 0x948, 0x0); - else - btcoexist->btc_write_4byte( - btcoexist, 0x948, - 0x280); - break; - case BTC_ANT_PATH_BT: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_4byte( - btcoexist, 0x948, - 0x280); - else - btcoexist->btc_write_4byte( - btcoexist, 0x948, 0x0); - break; - default: - case BTC_ANT_PATH_PTA: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_4byte( - btcoexist, 0x948, - 0x200); - else - btcoexist->btc_write_4byte( - btcoexist, 0x948, 0x80); - break; - } - } - } - - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; -} - -void halbtc8723b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - } - } - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - - -void halbtc8723b1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - u8 rssi_adjust_val = 0; - u8 ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51, - ps_tdma_byte3_val = 0x10; - s8 wifi_duration_adjust = 0x0; - static boolean pre_wifi_busy = false; - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - -#if BT_8723B_1ANT_ANTDET_ENABLE -#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE - if (board_info->btdm_ant_num_by_ant_det == 2) { - if (turn_on) - type = type + - 100; /* for WiFi RSSI low or BT RSSI low */ - else - type = 1; /* always translate to TDMA(off,1) for TDMA-off case */ - } - -#endif -#endif - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (wifi_busy != pre_wifi_busy) { - force_exec = true; - pre_wifi_busy = wifi_busy; - } - - if (!force_exec) { - if( (coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma) ) - return; - } - - if (coex_sta->scan_ap_num <= 5) { - wifi_duration_adjust = 5; - - if (coex_sta->a2dp_bit_pool >= 35) - wifi_duration_adjust = -10; - else if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - } else if (coex_sta->scan_ap_num >= 40) { - wifi_duration_adjust = -15; - - if (coex_sta->a2dp_bit_pool < 35) - wifi_duration_adjust = -5; - else if (coex_sta->a2dp_bit_pool < 45) - wifi_duration_adjust = -10; - } else if (coex_sta->scan_ap_num >= 20) { - wifi_duration_adjust = -10; - - if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - } else { - wifi_duration_adjust = 0; - - if (coex_sta->a2dp_bit_pool >= 35) - wifi_duration_adjust = -10; - else if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - } - - if ((type == 1) || (type == 2) || (type == 9) || (type == 11) || - (type == 101) - || (type == 102) || (type == 109) || (type == 101)) { - if (!coex_sta->force_lps_on) { /* Native power save TDMA, only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */ - ps_tdma_byte0_val = 0x61; /* no null-pkt */ - ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */ - ps_tdma_byte4_val = - 0x10; /* 0x778 = d/1 toggle, no dynamic slot */ - } else { - ps_tdma_byte0_val = 0x51; /* null-pkt */ - ps_tdma_byte3_val = 0x10; /* tx-pause at BT-slot */ - ps_tdma_byte4_val = - 0x50; /* 0x778 = d/1 toggle, dynamic slot */ - } - } else if ((type == 3) || (type == 13) || (type == 14) || - (type == 103) || (type == 113) || (type == 114)) { - ps_tdma_byte0_val = 0x51; /* null-pkt */ - ps_tdma_byte3_val = 0x10; /* tx-pause at BT-slot */ - ps_tdma_byte4_val = - 0x10; /* 0x778 = d/1 toggle, no dynamic slot */ -#if 0 - if (!wifi_busy) - ps_tdma_byte4_val = ps_tdma_byte4_val | - 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ -#endif - } else { /* native power save case */ - ps_tdma_byte0_val = 0x61; /* no null-pkt */ - ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */ - ps_tdma_byte4_val = - 0x11; /* 0x778 = d/1 toggle, no dynamic slot */ - /* psTdmaByte4Va is not defne for 0x778 = d/1, 1/1 case */ - } - - /* if (bt_link_info->slave_role == true) */ - if ((bt_link_info->slave_role == true) && (bt_link_info->a2dp_exist)) - ps_tdma_byte4_val = ps_tdma_byte4_val | - 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - - if (type > 100) { - ps_tdma_byte0_val = ps_tdma_byte0_val | - 0x82; /* set antenna control by SW */ - ps_tdma_byte3_val = ps_tdma_byte3_val | - 0x60; /* set antenna no toggle, control by antenna diversity */ - } - - - if (turn_on) { - switch (type) { - default: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1a, 0x1a, 0x0, ps_tdma_byte4_val); - break; - case 1: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3a + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 2: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x2d + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 3: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x30, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 4: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x14, 0x0); - break; - case 5: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x1f, 0x3, - ps_tdma_byte3_val, 0x11); - break; - case 6: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x20, 0x3, - ps_tdma_byte3_val, 0x11); - break; - case 7: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13, - 0xc, 0x5, 0x0, 0x0); - break; - case 8: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 9: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 10: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0xa, 0x0, 0x40); - break; - case 11: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 12: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, - 0x0a, 0x0a, 0x0, 0x50); - break; - case 13: - if (coex_sta->scan_ap_num <= 3) - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x40, 0x3, - ps_tdma_byte3_val, - ps_tdma_byte4_val); - else - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, - ps_tdma_byte4_val); - break; - case 14: - if (coex_sta->scan_ap_num <= 3) - halbtc8723b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x30, 0x3, 0x10, 0x50); - else - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, - ps_tdma_byte4_val); - break; - case 15: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0x3, 0x8, 0x0); - break; - case 16: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x10, 0x0); - break; - case 18: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 20: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3f, 0x03, - ps_tdma_byte3_val, 0x10); - break; - case 21: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x11); - break; - case 22: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x25, 0x03, - ps_tdma_byte3_val, 0x10); - break; - case 23: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x18); - break; - case 24: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x3, 0x31, 0x18); - break; - case 25: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - break; - case 26: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - break; - case 27: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x98); - break; - case 28: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x69, - 0x25, 0x3, 0x31, 0x0); - break; - case 29: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xab, - 0x1a, 0x1a, 0x1, 0x10); - break; - case 30: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, 0x10); - break; - case 31: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1a, 0x1a, 0, 0x58); - break; - case 32: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x35, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 33: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x35, 0x3, - ps_tdma_byte3_val, 0x10); - break; - case 34: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x53, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 35: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x63, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 36: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x12, 0x3, 0x14, 0x50); - break; - case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */ - /* here softap mode screen off will cost 70-80mA for phone */ - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x23, - 0x18, 0x00, 0x10, 0x24); - break; - - /* for 1-Ant translate to 2-Ant */ - case 101: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3a + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 102: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x2d + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 103: - /* halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, 0x1d, 0x1d, 0x0, ps_tdma_byte4_val); */ - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3a, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 105: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x15, 0x3, - ps_tdma_byte3_val, 0x11); - break; - case 106: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x20, 0x3, - ps_tdma_byte3_val, 0x11); - break; - case 109: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 111: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 113: - /* halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, 0x12, 0x12, 0x0, ps_tdma_byte4_val); */ - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 114: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 120: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3f, 0x03, - ps_tdma_byte3_val, 0x10); - break; - case 122: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x25, 0x03, - ps_tdma_byte3_val, 0x10); - break; - case 132: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x25, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 133: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x25, 0x03, - ps_tdma_byte3_val, 0x11); - break; - - } - } else { - - /* disable PS tdma */ - switch (type) { - case 8: /* PTA Control */ - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - break; - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - break; - case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */ - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - } - } - rssi_adjust_val = 0; - btcoexist->btc_set(btcoexist, - BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", - btcoexist->btc_read_4byte(btcoexist, 0x948), - btcoexist->btc_read_1byte(btcoexist, 0x765), - btcoexist->btc_read_1byte(btcoexist, 0x67)); - BTC_TRACE(trace_buf); - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8723b1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0, bt_info_ext; - boolean wifi_busy = false; - - if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status) - wifi_busy = true; - else - wifi_busy = false; - - if ((BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == - wifi_status) || - (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) || - (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT == - wifi_status)) { - if (coex_dm->cur_ps_tdma != 1 && - coex_dm->cur_ps_tdma != 2 && - coex_dm->cur_ps_tdma != 3 && - coex_dm->cur_ps_tdma != 9) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - coex_dm->ps_tdma_du_adj_type = 9; - - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } - return; - } - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* accquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - bt_info_ext = coex_sta->bt_info_ext; - - if ((coex_sta->low_priority_tx) > 1050 || - (coex_sta->low_priority_rx) > 1250) - retry_count++; - - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ - if (wait_count <= 2) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ - if (wait_count == 1) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (result == -1) { - /* if( (BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 1) ||(coex_dm->cur_ps_tdma == 2)) ) - { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } - else */ if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } - } else if (result == 1) { - /* if( (BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 1) ||(coex_dm->cur_ps_tdma == 2)) ) - { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } - else */ if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = 1; - } - } else { /* no change */ - /* Bryant Modify - if(wifi_busy != pre_wifi_busy) - { - pre_wifi_busy = wifi_busy; - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma); - } - */ - - } - - if (coex_dm->cur_ps_tdma != 1 && - coex_dm->cur_ps_tdma != 2 && - coex_dm->cur_ps_tdma != 9 && - coex_dm->cur_ps_tdma != 11) { - /* recover to previous adjust type */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - } - } -} - -void halbtc8723b1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8723b1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8723b1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8723b1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8723b1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - -void halbtc8723b1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, - false, false); -} - -void halbtc8723b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - } else { - bt_disable_cnt++; - if (bt_disable_cnt >= 2) - bt_disabled = true; - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - - coex_sta->bt_disabled = bt_disabled; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - if (bt_disabled) { - halbtc8723b1ant_action_wifi_only(btcoexist); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - } - } -} - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8723b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) -{ - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8723b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8723b1ant_action_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8723b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, ap_enable = false, wifi_busy = false, - bt_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - if (coex_sta->bt_abnormal_scan) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 33); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } else if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) { - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - /* SCO/HID/A2DP busy */ - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - if (coex_sta->c2h_bt_remote_name_req) - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 33); - else - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if ((bt_link_info->pan_exist) || (wifi_busy)) { - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - if (coex_sta->c2h_bt_remote_name_req) - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 33); - else - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - - } -} - -void halbtc8723b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* tdma and coex table */ - - if (bt_link_info->sco_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else { /* HID */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } -} - -void halbtc8723b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - if ((coex_sta->low_priority_rx >= 950) && (!coex_sta->under_ips)) - bt_link_info->slave_role = true; - else - bt_link_info->slave_role = false; - - if (bt_link_info->hid_only) { /* HID */ - halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, - wifi_status); - coex_dm->auto_tdma_adjust = false; - return; - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - halbtc8723b1ant_tdma_duration_adjust_for_acl(btcoexist, - wifi_status); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = true; - } - } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - coex_dm->auto_tdma_adjust = false; - - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && - bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - /* BT no-profile busy (0x9) */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } -} - -void halbtc8723b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - /* power save state */ - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8723b1ant_action_wifi_not_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* Bryant Add */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8723b1ant_action_wifi_not_connected_asso_auth( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2); - } -} - -void halbtc8723b1ant_action_wifi_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* Bryant Add */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8723b1ant_action_wifi_connected_specific_packet( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* no specific packet process for both WiFi and BT very busy */ - if ((wifi_busy) && ((bt_link_info->pan_exist) || - (coex_sta->num_of_profile >= 2))) - return; - - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else if (bt_link_info->a2dp_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8723b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - boolean scan = false, link = false, roam = false; - boolean under_4way = false, ap_enable = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (under_4way) { - halbtc8723b1ant_action_wifi_connected_specific_packet(btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - if (scan) - halbtc8723b1ant_action_wifi_connected_scan(btcoexist); - else - halbtc8723b1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* power save state */ - if (!ap_enable && - BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status && - !btcoexist->bt_link_info.hid_only) { - if (btcoexist->bt_link_info.a2dp_only) { /* A2DP */ - if (!wifi_busy) - halbtc8723b1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - else { /* busy */ - if (coex_sta->scan_ap_num >= - BT_8723B_1ANT_WIFI_NOISY_THRESH) /* no force LPS, no PS-TDMA, use pure TDMA */ - halbtc8723b1ant_power_save_state( - btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8723b1ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - } else if ((coex_sta->pan_exist == false) && - (coex_sta->a2dp_exist == false) && - (coex_sta->hid_exist == false)) - halbtc8723b1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - else - halbtc8723b1ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - } else - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - /* tdma and coex table */ - if (!wifi_busy) { - if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8723b1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8723b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - /* if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) */ - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - /* else - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); */ - } - } else { - if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8723b1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else { - /* halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8723b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - else - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8723b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - - } - } -} - -void halbtc8723b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false, wifi_busy = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - boolean miracast_plus_bt = false; - u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0, wifi_bw; - u8 iot_peer = BTC_IOT_PEER_UNKNOWN; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b1ant_action_bt_whck_test(btcoexist); - return; - } - - if ((BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - if (bt_link_info->bt_link_exist) { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, - 0, 1); - miracast_plus_bt = true; - } else { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, - 0, 0); - miracast_plus_bt = false; - } - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (((bt_link_info->a2dp_exist) || (wifi_busy)) && - (coex_sta->c2h_bt_inquiry_page)) - halbtc8723b1ant_action_bt_inquiry(btcoexist); - else - halbtc8723b1ant_action_wifi_multi_port(btcoexist); - - return; - } else { - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); - - /* if(BTC_IOT_PEER_CISCO != iot_peer) */ - if ((BTC_IOT_PEER_CISCO != iot_peer) && - (BTC_IOT_PEER_BROADCOM != iot_peer)) { - if (bt_link_info->sco_exist) /* if (bt_link_info->bt_hi_pri_link_exist) */ - /* halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, true, false, 0x5); */ - halbtc8723b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, false, 0x5); - else - halbtc8723b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, false, 0x5); - /* halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8); */ - } else { - if (bt_link_info->sco_exist) - halbtc8723b1ant_limited_rx(btcoexist, - NORMAL_EXEC, true, false, 0x5); - else { - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8723b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x10); - else - halbtc8723b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x8); - } - } - - halbtc8723b1ant_sw_mechanism(btcoexist, true); - } else { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x5); - - halbtc8723b1ant_sw_mechanism(btcoexist, false); - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8723b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723b1ant_action_hs(btcoexist); - return; - } - - - if (!wifi_connected) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is non connected-idle !!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - if (scan) - halbtc8723b1ant_action_wifi_not_connected_scan( - btcoexist); - else - halbtc8723b1ant_action_wifi_not_connected_asso_auth( - btcoexist); - } else - halbtc8723b1ant_action_wifi_not_connected(btcoexist); - } else /* wifi LPS/Busy */ - halbtc8723b1ant_action_wifi_connected(btcoexist); -} - -void halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - - /* sw all off */ - halbtc8723b1ant_sw_mechanism(btcoexist, false); - - /* halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ - /* halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */ - - coex_sta->pop_event_cnt = 0; -} - -void halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up, IN boolean wifi_only) -{ - u32 u32tmp = 0; /* , fw_ver; */ - u8 u8tmpa = 0, u8tmpb = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - psd_scan->ant_det_is_ant_det_available = false; - - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - - /* 0x790[5:0]=0x5 */ - btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); - - /* Enable counter statistics */ - /* btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); //0x76e[3] =1, WLAN_Act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); - - - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1); //BT select s0/s1 is controlled by WiFi */ - - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - - /* Antenna config */ - if (wifi_only) - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, true, false); - else - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, true, false); - - /* PTA parameter */ - halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", - u32tmp, u8tmpa, u8tmpb); - BTC_TRACE(trace_buf); -} - -void halbtc8723b1ant_mechanism_switch(IN struct btc_coexist *btcoexist, - IN boolean bSwitchTo2Antenna) -{ - - if (bSwitchTo2Antenna) { /* 1-Ant -> 2-Ant */ - /* un-lock TRx Mask setup for 8723b f-cut */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, 0x80, 0x1); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, 0x1, 0x1); - /* WiFi TRx Mask on */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - - /* BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 */ - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x2c, - 0x7c45); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x30, - 0x7c45); - - /* BT TRx Mask on */ - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x1); - - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, false); - } else { - /* WiFi TRx Mask on */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x780); - - /* lock TRx Mask setup for 8723b f-cut */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, 0x80, 0x0); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, 0x1, 0x0); - - /* BT TRx Mask on */ - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); - - /* BT TRx Mask ock 0x2c[0], 0x30[0] = 0 */ - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x2c, - 0x7c44); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x30, - 0x7c44); - - - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - } - -} - -u32 halbtc8723b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val) -{ - u8 j; - u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0; - u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200, - 174, 151, 132, 115, 100, 86, 74, 62, 51, 42, - 32, 23, 15, 7, 0 - }; - - if (val == 0) - return 0; - - tmp = val; - - while (1) { - if (tmp == 1) - break; - else { - tmp = (tmp >> 1); - shiftcount++; - } - } - - - val_integerd_b = shiftcount + 1; - - tmp2 = 1; - for (j = 1; j <= val_integerd_b; j++) - tmp2 = tmp2 * 2; - - tmp = (val * 100) / tmp2; - tindex = tmp / 5; - - if (tindex > 20) - tindex = 20; - - val_fractiond_b = table_fraction[tindex]; - - result = val_integerd_b * 100 - val_fractiond_b; - - return result; - - -} - -void halbtc8723b1ant_psd_show_antenna_detect_result(IN struct btc_coexist - *btcoexist) -{ - u8 *cli_buf = btcoexist->cli_buf; - struct btc_board_info *board_info = &btcoexist->board_info; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n============[Antenna Detection info] ============\n"); - CL_PRINTF(cli_buf); - - if (psd_scan->ant_det_result == 1) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)", - "Ant Det Result", "2-Antenna (Bad-Isolation)", - BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); - else if (psd_scan->ant_det_result == 2) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)", - "Ant Det Result", "2-Antenna (Good-Isolation)", - BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset, - BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)", - "Ant Det Result", "1-Antenna", - BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT, - BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset); - - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ", - "Antenna Detection Finish", - (board_info->btdm_ant_det_finish - ? "Yes" : "No")); - CL_PRINTF(cli_buf); - - switch (psd_scan->ant_det_result) { - case 0: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is not available)"); - break; - case 1: /* 2-Ant bad-isolation */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available)"); - break; - case 2: /* 2-Ant good-isolation */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available)"); - break; - case 3: /* 1-Ant */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available)"); - break; - case 4: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(Uncertainty result)"); - break; - case 5: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(Pre-Scan fai)"); - break; - case 6: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(WiFi is Scanning)"); - break; - case 7: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is not idle)"); - break; - case 8: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(Abort by WiFi Scanning)"); - break; - case 9: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(Antenna Init is not ready)"); - break; - case 10: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is Inquiry or page)"); - break; - case 11: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is Disabled)"); - break; - } - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Ant Detect Total Count", psd_scan->ant_det_try_count); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Ant Detect Fail Count", psd_scan->ant_det_fail_count); - CL_PRINTF(cli_buf); - - if ((!board_info->btdm_ant_det_finish) && - (psd_scan->ant_det_result != 5)) - return; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Response", - (psd_scan->ant_det_result ? "ok" : "fail")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ms", "BT Tx Time", - psd_scan->ant_det_bt_tx_time); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "BT Tx Ch", - psd_scan->ant_det_bt_le_channel); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", - "WiFi PSD Cent-Ch/Offset/Span", - psd_scan->real_cent_freq, psd_scan->real_offset, - psd_scan->real_span); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB", - "PSD Pre-Scan Peak Value", - psd_scan->ant_det_pre_psdscan_peak_val / 100); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (<= %d)", - "PSD Pre-Scan result", - (psd_scan->ant_det_result != 5 ? "ok" : "fail"), - BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset); - CL_PRINTF(cli_buf); - - if (psd_scan->ant_det_result == 5) - return; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s dB", - "PSD Scan Peak Value", psd_scan->ant_det_peak_val); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s MHz", - "PSD Scan Peak Freq", psd_scan->ant_det_peak_freq); - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package", - (board_info->tfbga_package) ? "Yes" : "No"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "PSD Threshold Offset", psd_scan->ant_det_thres_offset); - CL_PRINTF(cli_buf); - -} - -void halbtc8723b1ant_psd_showdata(IN struct btc_coexist *btcoexist) -{ - u8 *cli_buf = btcoexist->cli_buf; - u32 delta_freq_per_point; - u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n\n============[PSD info] (%d)============\n", - psd_scan->psd_gen_count); - CL_PRINTF(cli_buf); - - if (psd_scan->psd_gen_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n"); - CL_PRINTF(cli_buf); - return; - } - - if (psd_scan->psd_point == 0) - delta_freq_per_point = 0; - else - delta_freq_per_point = psd_scan->psd_band_width / - psd_scan->psd_point; - - /* if (psd_scan->is_psd_show_max_only) */ - if (0) { - psd_rep1 = psd_scan->psd_max_value / 100; - psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100; - - freq = ((psd_scan->real_cent_freq - 20) * 1000000 + - psd_scan->psd_max_value_point * delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq = %d.0%d MHz", - freq1, freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq = %d.%d MHz", - freq1, freq2); - - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - ", Value = %d.0%d dB, (%d)\n", - psd_rep1, psd_rep2, psd_scan->psd_max_value); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - ", Value = %d.%d dB, (%d)\n", - psd_rep1, psd_rep2, psd_scan->psd_max_value); - - CL_PRINTF(cli_buf); - } else { - m = psd_scan->psd_start_point; - n = psd_scan->psd_start_point; - i = 1; - j = 1; - - while (1) { - do { - freq = ((psd_scan->real_cent_freq - 20) * 1000000 + m * - delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (i == 1) { - if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.000", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.0%2d", freq1, - freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.%3d", freq1, - freq2); - } else if ((i % 8 == 0) || - (m == psd_scan->psd_stop_point)) { - if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.000\n", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.0%2d\n", freq1, freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.%3d\n", freq1, freq2); - } else { - if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.000", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.0%2d", freq1, freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.%3d", freq1, freq2); - } - - i++; - m++; - CL_PRINTF(cli_buf); - - } while ((i <= 8) && (m <= psd_scan->psd_stop_point)); - - - do { - psd_rep1 = psd_scan->psd_report_max_hold[n] / 100; - psd_rep2 = psd_scan->psd_report_max_hold[n] - psd_rep1 * - 100; - - if (j == 1) { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Val %7d.0%d", psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Val %7d.%d", psd_rep1, - psd_rep2); - } else if ((j % 8 == 0) || - (n == psd_scan->psd_stop_point)) { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.0%d\n", psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.%d\n", psd_rep1, psd_rep2); - } else { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.0%d", psd_rep1, psd_rep2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.%d", psd_rep1, psd_rep2); - } - - j++; - n++; - CL_PRINTF(cli_buf); - - } while ((j <= 8) && (n <= psd_scan->psd_stop_point)); - - if ((m > psd_scan->psd_stop_point) || - (n > psd_scan->psd_stop_point)) - break; - else { - i = 1; - j = 1; - } - - } - } - - -} - -void halbtc8723b1ant_psd_max_holddata(IN struct btc_coexist *btcoexist, - IN u32 gen_count) -{ - u32 i = 0, i_max = 0, val_max = 0; - - if (gen_count == 1) { - memcpy(psd_scan->psd_report_max_hold, - psd_scan->psd_report, - BT_8723B_1ANT_ANTDET_PSD_POINTS * sizeof(u32)); - - psd_scan->psd_max_value_point = 0; - psd_scan->psd_max_value = 0; - - } else { - for (i = psd_scan->psd_start_point; - i <= psd_scan->psd_stop_point; i++) { - if (psd_scan->psd_report[i] > - psd_scan->psd_report_max_hold[i]) - psd_scan->psd_report_max_hold[i] = - psd_scan->psd_report[i]; - - /* search Max Value */ - if (i == psd_scan->psd_start_point) { - i_max = i; - val_max = psd_scan->psd_report_max_hold[i]; - } else { - if (psd_scan->psd_report_max_hold[i] > - val_max) { - i_max = i; - val_max = psd_scan->psd_report_max_hold[i]; - } - } - - } - - psd_scan->psd_max_value_point = i_max; - psd_scan->psd_max_value = val_max; - - } - - -} - -u32 halbtc8723b1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) -{ - /* reg 0x808[9:0]: FFT data x */ - /* reg 0x808[22]: 0-->1 to get 1 FFT data y */ - /* reg 0x8b4[15:0]: FFT data y report */ - - u32 val = 0, psd_report = 0; - int k = 0; - - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - - val &= 0xffbffc00; - val |= point; - - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - val |= 0x00400000; - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - while (1) { - if (k++ > BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY) - break; - } - - val = btcoexist->btc_read_4byte(btcoexist, 0x8b4); - - psd_report = val & 0x0000ffff; - - return psd_report; -} - - -boolean halbtc8723b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points, - IN u32 avgnum, IN u32 loopcnt) -{ - u32 i, val, n, k = 0, j, point_index = 0; - u32 points1 = 0, psd_report = 0; - u32 start_p = 0, stop_p = 0, delta_freq_per_point = 156250; - u32 psd_center_freq = 20 * 10 ^ 6; - boolean outloop = false, scan , roam, is_sweep_ok = true; - u8 flag = 0; - u32 tmp; - u32 wifi_original_channel = 1; - - psd_scan->is_psd_running = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n"); - BTC_TRACE(trace_buf); - - do { - switch (flag) { - case 0: /* Get PSD parameters */ - default: - - psd_scan->psd_band_width = 40 * 1000000; - psd_scan->psd_point = points; - psd_scan->psd_start_base = points / 2; - psd_scan->psd_avg_num = avgnum; - psd_scan->real_cent_freq = cent_freq; - psd_scan->real_offset = offset; - psd_scan->real_span = span; - - - points1 = psd_scan->psd_point; - delta_freq_per_point = psd_scan->psd_band_width / - psd_scan->psd_point; - - /* PSD point setup */ - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - val &= 0xffff0fff; - - switch (psd_scan->psd_point) { - case 128: - val |= 0x0; - break; - case 256: - default: - val |= 0x00004000; - break; - case 512: - val |= 0x00008000; - break; - case 1024: - val |= 0x0000c000; - break; - } - - switch (psd_scan->psd_avg_num) { - case 1: - val |= 0x0; - break; - case 8: - val |= 0x00001000; - break; - case 16: - val |= 0x00002000; - break; - case 32: - default: - val |= 0x00003000; - break; - } - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - flag = 1; - break; - case 1: /* calculate the PSD point index from freq/offset/span */ - psd_center_freq = psd_scan->psd_band_width / 2 + - offset * (1000000); - - start_p = psd_scan->psd_start_base + (psd_center_freq - - span * (1000000) / 2) / delta_freq_per_point; - psd_scan->psd_start_point = start_p - - psd_scan->psd_start_base; - - stop_p = psd_scan->psd_start_base + (psd_center_freq + - span * (1000000) / 2) / delta_freq_per_point; - psd_scan->psd_stop_point = stop_p - - psd_scan->psd_start_base - 1; - - flag = 2; - break; - case 2: /* set RF channel/BW/Mode */ - - /* set 3-wire off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x88c); - val |= 0x00300000; - btcoexist->btc_write_4byte(btcoexist, 0x88c, val); - - /* CCK off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x800); - val &= 0xfeffffff; - btcoexist->btc_write_4byte(btcoexist, 0x800, val); - - /* store WiFi original channel */ - wifi_original_channel = btcoexist->btc_get_rf_reg( - btcoexist, BTC_RF_A, 0x18, 0x3ff); - - /* Set RF channel */ - if (cent_freq == 2484) - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, - 0x18, 0x3ff, 0xe); - else - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, - 0x18, 0x3ff, (cent_freq - 2412) / 5 + - 1); /* WiFi TRx Mask on */ - - - /* Set RF Rx filter corner */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, 0x3e4); - - /* Set TRx mask off */ - /* un-lock TRx Mask setup */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, - 0x80, 0x1); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, - 0x1, 0x1); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - - /* Set RF mode = Rx, RF Gain = 0x8a0 */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0, - 0xfffff, 0x308a0); - - while (1) { - if (k++ > BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY) - break; - } - flag = 3; - break; - case 3: - psd_scan->psd_gen_count = 0; - for (j = 1; j <= loopcnt; j++) { - - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || roam) { - is_sweep_ok = false; - break; - } - memset(psd_scan->psd_report, 0, - psd_scan->psd_point * sizeof(u32)); - start_p = psd_scan->psd_start_point + - psd_scan->psd_start_base; - stop_p = psd_scan->psd_stop_point + - psd_scan->psd_start_base + 1; - - i = start_p; - point_index = 0; - - while (i < stop_p) { - if (i >= points1) - psd_report = - halbtc8723b1ant_psd_getdata( - btcoexist, i - points1); - else - psd_report = - halbtc8723b1ant_psd_getdata( - btcoexist, i); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Point=%d, psd_raw_data = 0x%08x\n", - i, psd_report); - BTC_TRACE(trace_buf); - if (psd_report == 0) - tmp = 0; - else - /* tmp = 20*log10((double)psd_report); */ - /* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */ - tmp = 6 * halbtc8723b1ant_psd_log2base( - btcoexist, psd_report); - - n = i - psd_scan->psd_start_base; - psd_scan->psd_report[n] = tmp; - - - halbtc8723b1ant_psd_max_holddata( - btcoexist, j); - - i++; - - } - - psd_scan->psd_gen_count = j; - } - - flag = 100; - break; - case 99: /* error */ - - outloop = true; - break; - case 100: /* recovery */ - - /* set 3-wire on */ - val = btcoexist->btc_read_4byte(btcoexist, 0x88c); - val &= 0xffcfffff; - btcoexist->btc_write_4byte(btcoexist, 0x88c, val); - - /* CCK on */ - val = btcoexist->btc_read_4byte(btcoexist, 0x800); - val |= 0x01000000; - btcoexist->btc_write_4byte(btcoexist, 0x800, val); - - /* PSD off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - val &= 0xffbfffff; - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - /* TRx Mask on */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x780); - - /* lock TRx Mask setup */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, - 0x80, 0x0); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, - 0x1, 0x0); - - /* Set RF Rx filter corner */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, 0x0); - - /* restore WiFi original channel */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18, - 0x3ff, wifi_original_channel); - - outloop = true; - break; - - } - - } while (!outloop); - - - - psd_scan->is_psd_running = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n"); - BTC_TRACE(trace_buf); - return is_sweep_ok; - -} - -void halbtc8723b1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 bt_tx_time, IN u32 bt_le_channel) -{ - u32 i = 0; - u32 wlpsd_cent_freq = 2484, wlpsd_span = 2, wlpsd_sweep_count = 50; - s32 wlpsd_offset = -4; - u8 bt_le_ch[13] = {3,6,8,11,13,16,18,21,23,26,28,31,33}; - - u8 h2c_parameter[3] ={0},u8tmpa,u8tmpb; - - u8 state=0; - boolean outloop = false, bt_resp = false; - u32 freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point, - u32tmp; - struct btc_board_info *board_info = &btcoexist->board_info; - - board_info->btdm_ant_det_finish = false; - memset(psd_scan->ant_det_peak_val, 0, 16*sizeof(u8)); - memset(psd_scan->ant_det_peak_freq, 0, 16*sizeof(u8)); - - if (board_info->tfbga_package) /* for TFBGA */ - psd_scan->ant_det_thres_offset = 5; - else - psd_scan->ant_det_thres_offset = 0; - - do { - switch (state) { - case 0: - if (bt_le_channel == 39) - wlpsd_cent_freq = 2484; - else { - for (i = 1; i <= 13; i++) { - if (bt_le_ch[i - 1] == - bt_le_channel) { - wlpsd_cent_freq = 2412 - + (i - 1) * 5; - break; - } - } - - if (i == 14) { - - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Abort!!, Invalid LE channel = %d\n ", - bt_le_channel); - BTC_TRACE(trace_buf); - outloop = true; - break; - } - } - - wlpsd_sweep_count = bt_tx_time * 238 / - 100; /* bt_tx_time/0.42 */ - wlpsd_sweep_count = wlpsd_sweep_count / 5; - - if (wlpsd_sweep_count % 5 != 0) - wlpsd_sweep_count = (wlpsd_sweep_count / - 5 + 1) * 5; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n", - bt_tx_time, bt_le_channel); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), wlpsd_cent_freq=%d, wlpsd_offset = %d, wlpsd_span = %d, wlpsd_sweep_count = %d\n", - wlpsd_cent_freq, - wlpsd_offset, - wlpsd_span, - wlpsd_sweep_count); - BTC_TRACE(trace_buf); - - state = 1; - break; - case 1: /* stop coex DM & set antenna path */ - /* Stop Coex DM */ - btcoexist->stop_coex_dm = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n"); - BTC_TRACE(trace_buf); - - /* set native power save */ - halbtc8723b1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - - /* Set TDMA off, */ - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, - false, 0); - - /* Set coex table */ - halbtc8723b1ant_coex_table_with_type(btcoexist, - FORCE_EXEC, 0); - - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n"); - BTC_TRACE(trace_buf); - } - - /* Set Antenna path, switch WiFi to un-certain antenna port */ - halbtc8723b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, FORCE_EXEC, false, - false); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n"); - BTC_TRACE(trace_buf); - - /* Set AFH mask on at WiFi channel 2472MHz +/- 10MHz */ - h2c_parameter[0] = 0x1; - h2c_parameter[1] = 0xd; - h2c_parameter[2] = 0x14; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n", - h2c_parameter[1], - h2c_parameter[2]); - BTC_TRACE(trace_buf); - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, - h2c_parameter); - - u32tmp = btcoexist->btc_read_4byte(btcoexist, - 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, - 0x778); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x778=0x%x\n", - u32tmp, u8tmpa, u8tmpb); - BTC_TRACE(trace_buf); - - state = 2; - break; - case 2: /* Pre-sweep background psd */ - if (!halbtc8723b1ant_psd_sweep_point(btcoexist, - wlpsd_cent_freq, wlpsd_offset, wlpsd_span, - BT_8723B_1ANT_ANTDET_PSD_POINTS, - BT_8723B_1ANT_ANTDET_PSD_AVGNUM, 3)) { - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - psd_scan->ant_det_result = 8; - state = 99; - break; - } - - psd_scan->ant_det_pre_psdscan_peak_val = - psd_scan->psd_max_value; - - if (psd_scan->psd_max_value > - (BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset) * 100) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n", - psd_scan->psd_max_value / 100, - BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset); - BTC_TRACE(trace_buf); - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - psd_scan->ant_det_result = 5; - state = 99; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n", - psd_scan->psd_max_value / 100, - BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset); - BTC_TRACE(trace_buf); - state = 3; - } - break; - case 3: - bt_resp = btcoexist->btc_set_bt_ant_detection( - btcoexist, (u8)(bt_tx_time & 0xff), - (u8)(bt_le_channel & 0xff)); - - if (!halbtc8723b1ant_psd_sweep_point(btcoexist, - wlpsd_cent_freq, wlpsd_offset, - wlpsd_span, - BT_8723B_1ANT_ANTDET_PSD_POINTS, - BT_8723B_1ANT_ANTDET_PSD_AVGNUM, - wlpsd_sweep_count)) { - board_info->btdm_ant_det_finish - = false; - board_info->btdm_ant_num_by_ant_det - = 1; - psd_scan->ant_det_result = 8; - state = 99; - break; - } - - psd_scan->ant_det_psd_scan_peak_val = - psd_scan->psd_max_value; - psd_scan->ant_det_psd_scan_peak_freq = - psd_scan->psd_max_value_point; - state = 4; - break; - case 4: - - if (psd_scan->psd_point == 0) - delta_freq_per_point = 0; - else - delta_freq_per_point = - psd_scan->psd_band_width / - psd_scan->psd_point; - - psd_rep1 = psd_scan->psd_max_value / 100; - psd_rep2 = psd_scan->psd_max_value - psd_rep1 * - 100; - - freq = ((psd_scan->real_cent_freq - 20) * - 1000000 + psd_scan->psd_max_value_point - * delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (freq2 < 100) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.0%d MHz", - freq1, freq2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_freq, - BT_8723B_1ANT_ANTDET_BUF_LEN, - "%d.0%d", freq1, freq2); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.%d MHz", - freq1, freq2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_freq, - BT_8723B_1ANT_ANTDET_BUF_LEN, - "%d.%d", freq1, freq2); - } - - if (psd_rep2 < 10) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - ", Value = %d.0%d dB\n", - psd_rep1, psd_rep2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_val, - BT_8723B_1ANT_ANTDET_BUF_LEN, - "%d.0%d", psd_rep1, psd_rep2); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - ", Value = %d.%d dB\n", - psd_rep1, psd_rep2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_val, - BT_8723B_1ANT_ANTDET_BUF_LEN, - "%d.%d", psd_rep1, psd_rep2); - } - - psd_scan->ant_det_is_btreply_available = true; - - if (bt_resp == false) { - psd_scan->ant_det_is_btreply_available = - false; - psd_scan->ant_det_result = 0; - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n "); - BTC_TRACE(trace_buf); - } else if (psd_scan->psd_max_value > - (BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION) - * 100) { - psd_scan->ant_det_result = 1; - board_info->btdm_ant_det_finish = true; - board_info->btdm_ant_num_by_ant_det = 2; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n"); - BTC_TRACE(trace_buf); - } else if (psd_scan->psd_max_value > - (BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset) * 100) { - psd_scan->ant_det_result = 2; - board_info->btdm_ant_det_finish = true; - board_info->btdm_ant_num_by_ant_det = 2; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n"); - BTC_TRACE(trace_buf); - } else if (psd_scan->psd_max_value > - (BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT) * - 100) { - psd_scan->ant_det_result = 3; - board_info->btdm_ant_det_finish = true; - board_info->btdm_ant_num_by_ant_det = 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n"); - BTC_TRACE(trace_buf); - } else { - psd_scan->ant_det_result = 4; - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n"); - BTC_TRACE(trace_buf); - } - - state = 99; - break; - case 99: /* restore setup */ - - /* Set AFH mask off at WiFi channel 2472MHz +/- 10MHz */ - h2c_parameter[0] = 0x0; - h2c_parameter[1] = 0x0; - h2c_parameter[2] = 0x0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n", - h2c_parameter[1], h2c_parameter[2]); - BTC_TRACE(trace_buf); - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, - h2c_parameter); - - /* Set Antenna Path */ - halbtc8723b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, FORCE_EXEC, false, - false); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!"); - BTC_TRACE(trace_buf); - - /* Resume Coex DM */ - btcoexist->stop_coex_dm = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); - BTC_TRACE(trace_buf); - - /* stimulate coex running */ - halbtc8723b1ant_run_coexist_mechanism( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); - BTC_TRACE(trace_buf); - - outloop = true; - break; - } - - } while (!outloop); - - - -} - -void halbtc8723b1ant_psd_antenna_detection_check(IN struct btc_coexist - *btcoexist) -{ - static u32 ant_det_count = 0, ant_det_fail_count = 0; - struct btc_board_info *board_info = &btcoexist->board_info; - - boolean scan, roam; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - - /* psd_scan->ant_det_bt_tx_time = 20; */ - psd_scan->ant_det_bt_tx_time = - BT_8723B_1ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */ - psd_scan->ant_det_bt_le_channel = BT_8723B_1ANT_ANTDET_BTTXCHANNEL; - - ant_det_count++; - - psd_scan->ant_det_try_count = ant_det_count; - - if (scan || roam) { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 6; - } else if (coex_sta->bt_disabled) { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 11; - } else if (coex_sta->num_of_profile >= 1) { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 7; - } else if ( - !psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */ - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 9; - } else if (coex_sta->c2h_bt_inquiry_page) { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 10; - } else - halbtc8723b1ant_psd_antenna_detection(btcoexist, - psd_scan->ant_det_bt_tx_time, - psd_scan->ant_det_bt_le_channel); - - if (!board_info->btdm_ant_det_finish) - ant_det_fail_count++; - - psd_scan->ant_det_fail_count = ant_det_fail_count; - -} - - -/* ************************************************************ - * work around function start with wa_halbtc8723b1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8723b1ant_ - * ************************************************************ */ -void ex_halbtc8723b1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp=0x0; - u16 u16tmp=0x0; - u32 value; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Execute 8723b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Ant Det Finish = %s, Ant Det Number = %d\n", - (board_info->btdm_ant_det_finish ? "Yes" : "No"), - board_info->btdm_ant_num_by_ant_det); - BTC_TRACE(trace_buf); - - - btcoexist->stop_coex_dm = true; - - btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20); - - /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - - /* set GRAN_BT = 1 */ - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); - /* set WLAN_ACT = 0 */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - if(btcoexist->chip_interface == BTC_INTF_USB) { - /* fixed at S0 for USB interface */ - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - - u8tmp |= 0x1; /* antenna inverse */ - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - } else { - /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ - if (board_info->single_ant_path == 0) { - /* set to S1 */ - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x280); - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - value = 1; - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - u8tmp |= 0x1; /* antenna inverse */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - value = 0; - } - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, - &value); - - if(btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384, - u8tmp); - else if(btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, - u8tmp); - } -} - -void ex_halbtc8723b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8723b1ant_init_hw_config(btcoexist, true, wifi_only); - btcoexist->stop_coex_dm = false; -} - -void ex_halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - - halbtc8723b1ant_init_coex_dm(btcoexist); - - halbtc8723b1ant_query_bt_info(btcoexist); -} - -void ex_halbtc8723b1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case=0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fa_ofdm, fa_cck; - u32 fw_ver=0, bt_patch_ver=0; - static u8 pop_report_in_10s = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if(btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if(btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - if (psd_scan->ant_det_try_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", - "Ant PG Num/ Mech/ Pos", - board_info->pg_ant_num, board_info->btdm_ant_num, - board_info->btdm_ant_pos); - CL_PRINTF(cli_buf); - } else { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %d (%d/%d/%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos", - board_info->pg_ant_num, board_info->btdm_ant_num_by_ant_det, - board_info->btdm_ant_pos, - psd_scan->ant_det_try_count, psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); - CL_PRINTF(cli_buf); - - if (board_info->btdm_ant_det_finish) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - CL_PRINTF(cli_buf); - } - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c", - "Version Coex/ Fw/ Patch/ Cut", - glcoex_ver_date_8723b_1ant, glcoex_ver_8723b_1ant, fw_ver, - bt_patch_ver, bt_patch_ver, coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", - "WifibHiPri/ Ccklock/ CckEverLock", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), - (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No")); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Abnormal scan", - (coex_sta->bt_abnormal_scan) ? "Yes" : "No"); - CL_PRINTF(cli_buf); - - pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled)? ("disabled"): (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); - CL_PRINTF(cli_buf); - - if (pop_report_in_10s >= 5) { - coex_sta->pop_event_cnt = 0; - pop_report_in_10s = 0; - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d / %d / %d / %d / %d / %d", - "SCO/HID/PAN/A2DP/NameReq/WHQL", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist, - coex_sta->c2h_bt_remote_name_req, - coex_sta->bt_whck_test); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Role", - (bt_link_info->slave_role) ? "Slave" : "Master"); - CL_PRINTF(cli_buf); - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d", - "A2DP Rate/Bitpool", - (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8723B_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8723b_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - - if(btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms] (before Manual)============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "SM[LowPenaltyRA]", - coex_dm->cur_low_penalty_ra); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - if (board_info->btdm_ant_num_by_ant_det == 2) { - if (coex_dm->cur_ps_tdma_on) - ps_tdma_case = ps_tdma_case + - 100; /* for WiFi RSSI low or BT RSSI low */ - else - ps_tdma_case = - 1; /* always translate to TDMA(off,1) for TDMA-off case */ - } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "On" : "Off"), - (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); - - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Coex Table Type", - coex_sta->coex_table_type); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "IgnWlanAct", - coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - /* - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Latest error condition(should be 0)", - coex_dm->error_condition); - CL_PRINTF(cli_buf); - */ - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "backup ARFR1/ARFR2/RL/AMaxTime", - coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2, - coex_dm->backup_retry_limit, - coex_dm->backup_ampdu_max_time); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x880); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x778/0x6cc/0x880[29:25]", - u8tmp[0], u32tmp[0], (u32tmp[1] & 0x3e000000) >> 25); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x764); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x76e); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x948/ 0x67[5] / 0x764 / 0x76e", - u32tmp[0], ((u8tmp[0] & 0x20) >> 5), (u32tmp[1] & 0xffff), - u8tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x92c); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x930); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x944); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]", - u32tmp[0] & 0x3, u32tmp[1] & 0xff, u32tmp[2] & 0x3); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x39); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x38[11]/0x40/0x4c[24:23]/0x64[0]", - ((u8tmp[0] & 0x8) >> 3), u8tmp[1], - ((u32tmp[0] & 0x01800000) >> 23), u8tmp[2] & 0x1); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xc50(dig)/0x49c(null-drop)", - u32tmp[0] & 0xff, u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8); - u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c); - - fa_ofdm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000) - >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) + - ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] & - 0xffff) ; - fa_cck = (u8tmp[0] << 8) + u8tmp[1]; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "OFDM-CCA/OFDM-FA/CCK-FA", - u32tmp[0] & 0xffff, fa_ofdm, fa_cck); - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-Agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-Agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8723B_1ANT == 1) - /* halbtc8723b1ant_monitor_bt_ctr(btcoexist); */ -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8723b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if(btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723b1ant_init_hw_config(btcoexist, false, false); - halbtc8723b1ant_init_coex_dm(btcoexist); - halbtc8723b1ant_query_bt_info(btcoexist); - - coex_sta->under_ips = false; - } -} - -void ex_halbtc8723b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if(btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8723b1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected=false, bt_hs_on=false; - u32 wifi_link_status=0; - u32 num_of_wifi_link=0; - boolean bt_ctrl_agg_buf_size=false; - u8 agg_buf_size=5; - - u8 u8tmpa, u8tmpb; - u32 u32tmp; - - if(btcoexist->manual_control || - btcoexist->stop_coex_dm ) - return; - - if (BTC_SCAN_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - psd_scan->ant_det_is_ant_det_available = true; - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", - u32tmp, u8tmpa, u8tmpb); - BTC_TRACE(trace_buf); - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - } - - if(coex_sta->bt_disabled) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, -&wifi_connected); - - halbtc8723b1ant_query_bt_info(btcoexist); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status>>16; - if (num_of_wifi_link >= 2) { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8723b1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8723b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723b1ant_action_hs(btcoexist); - return; - } - - if (BTC_SCAN_START == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8723b1ant_action_wifi_not_connected_scan( - btcoexist); - else /* wifi is connected */ - halbtc8723b1ant_action_wifi_connected_scan(btcoexist); - } else if (BTC_SCAN_FINISH == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8723b1ant_action_wifi_not_connected(btcoexist); - else - halbtc8723b1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8723b1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected=false, bt_hs_on=false; - u32 wifi_link_status=0; - u32 num_of_wifi_link=0; - boolean bt_ctrl_agg_buf_size=false; - u8 agg_buf_size=5; - - if(btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled ) - return; - - if (BTC_ASSOCIATE_START == type) { - coex_sta->wifi_is_high_pri_task = true; - psd_scan->ant_det_is_ant_det_available = true; - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - /* coex_dm->arp_cnt = 0; */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8723b1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8723b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723b1ant_action_hs(btcoexist); - return; - } - - if (BTC_ASSOCIATE_START == type) - halbtc8723b1ant_action_wifi_not_connected_asso_auth(btcoexist); - else if (BTC_ASSOCIATE_FINISH == type) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (!wifi_connected) /* non-connected scan */ - halbtc8723b1ant_action_wifi_not_connected(btcoexist); - else - halbtc8723b1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8723b1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] ={0}; - u32 wifi_bw; - u8 wifi_central_chnl; - boolean wifi_under_b_mode = false; - - if(btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled ) - return; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - psd_scan->ant_det_is_ant_det_available = true; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - - coex_sta->cck_ever_lock = false; - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - /* h2c_parameter[0] = 0x1; */ - h2c_parameter[0] = 0x0; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); -} - -void ex_halbtc8723b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean bt_hs_on=false; - u32 wifi_link_status=0; - u32 num_of_wifi_link=0; - boolean bt_ctrl_agg_buf_size=false, under_4way=false; - u8 agg_buf_size=5; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if(btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled ) - return; - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - BTC_PACKET_ARP == type) { - if (BTC_PACKET_ARP == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify\n"); - BTC_TRACE(trace_buf); - - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ARP Packet Count = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - - if ((coex_dm->arp_cnt >= 10) && - (!under_4way)) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */ - coex_sta->wifi_is_high_pri_task = false; - else - coex_sta->wifi_is_high_pri_task = true; - } else { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify\n"); - BTC_TRACE(trace_buf); - } - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet [Type = %d] notify\n", type); - BTC_TRACE(trace_buf); - } - - coex_sta->specific_pkt_period_cnt = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8723b1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8723b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723b1ant_action_hs(btcoexist); - return; - } - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task))) - halbtc8723b1ant_action_wifi_connected_specific_packet(btcoexist); -} - -void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source=0; - boolean wifi_connected=false; - boolean bt_busy=false; - struct btc_board_info *board_info = &btcoexist->board_info; - - coex_sta->c2h_bt_info_req_sent = false; - - rsp_source = tmp_buf[0]&0xf; - if(rsp_source >= BT_INFO_SRC_8723B_1ANT_MAX) - rsp_source = BT_INFO_SRC_8723B_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, -"[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, -length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - /* if 0xff, it means BT is under WHCK test */ - if (bt_info == 0xff) - coex_sta->bt_whck_test = true; - else - coex_sta->bt_whck_test = false; - - if (BT_INFO_SRC_8723B_1ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2]&0xf; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->bt_info_c2h[rsp_source][2]&0x20) - coex_sta->c2h_bt_remote_name_req = true; - else - coex_sta->c2h_bt_remote_name_req = false; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3]*2-90; - /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */ - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - if (coex_sta->bt_info_c2h[rsp_source][1] == 0x49) { - coex_sta->a2dp_bit_pool = - coex_sta->bt_info_c2h[rsp_source][6]; - } else - coex_sta->a2dp_bit_pool = 0; - - coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] - & 0x40); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, - &coex_sta->bt_tx_rx_mask); - -#if BT_8723B_1ANT_ANTDET_ENABLE -#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE - if ((board_info->btdm_ant_det_finish) && - (board_info->btdm_ant_num_by_ant_det == 2)) { - if (coex_sta->bt_tx_rx_mask) { - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x1\n"); - BTC_TRACE(trace_buf); - - /* BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 */ - btcoexist->btc_set_bt_reg(btcoexist, - BTC_BT_REG_RF, 0x2c, 0x7c45); - btcoexist->btc_set_bt_reg(btcoexist, - BTC_BT_REG_RF, 0x30, 0x7c45); - - btcoexist->btc_set_bt_reg(btcoexist, - BTC_BT_REG_RF, 0x3c, 0x1); - } - } else -#endif -#endif - - { - if (!coex_sta->bt_tx_rx_mask) { - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x3c, 0x15); - - /* BT TRx Mask lock 0x2c[0], 0x30[0] = 0 */ - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x2c, 0x7c44); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x30, 0x7c44); - } - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if (coex_sta->bt_info_ext & BIT(1)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8723b1ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8723b1ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if (coex_sta->bt_info_ext & BIT(3)) { - if(!btcoexist->manual_control && - !btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - } -#if(BT_AUTO_REPORT_ONLY_8723B_1ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8723b1ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - coex_sta->num_of_profile = 0; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - - coex_sta->bt_hi_pri_link_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8723B_1ANT_B_FTP) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) { - coex_sta->a2dp_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8723B_1ANT_B_HID) { - coex_sta->hid_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) { - coex_sta->sco_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = false; - - if ((coex_sta->hid_exist == false) && - (coex_sta->c2h_bt_inquiry_page == false) && - (coex_sta->sco_exist == false)) { - if (coex_sta->high_priority_tx + - coex_sta->high_priority_rx >= 160) { - coex_sta->hid_exist = true; - coex_sta->wrong_profile_notification++; - coex_sta->num_of_profile++; - bt_info = bt_info | 0x28; - } - } - - /* Add Hi-Pri Tx/Rx counter to avoid false detection */ - if (((coex_sta->hid_exist) || (coex_sta->sco_exist)) && - (coex_sta->high_priority_tx + - coex_sta->high_priority_rx >= 160) - && (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->bt_hi_pri_link_exist = true; - - if ((bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) && - (coex_sta->num_of_profile == 0)) { - if (coex_sta->low_priority_tx + - coex_sta->low_priority_rx >= 160) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - coex_sta->wrong_profile_notification++; - bt_info = bt_info | 0x88; - } - } - } - - halbtc8723b1ant_update_bt_link_info(btcoexist); - - bt_info = bt_info & - 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ - - if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) - coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - else if (bt_info == - BT_INFO_8723B_1ANT_B_CONNECTION) /* connection exists but no busy */ - coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE; - else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY)) - coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_SCO_BUSY; - else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) { - if(BT_8723B_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) - coex_dm->auto_tdma_adjust = false; - coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_ACL_BUSY; - } else - coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_MAX; - - if( (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status) ) - bt_busy = true; - else - bt_busy = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - halbtc8723b1ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8723b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u32 u32tmp; - u8 u8tmpa,u8tmpb, u8tmpc; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - } else if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, -0x0, 0x0); - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, -FORCE_EXEC, false, true); - - halbtc8723b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - btcoexist->stop_coex_dm = true; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); - u8tmpc = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n", - u32tmp, u8tmpa, u8tmpb, u8tmpc); - BTC_TRACE(trace_buf); - - } -} - -void ex_halbtc8723b1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, - false, true); - - halbtc8723b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8723b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8723b1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - halbtc8723b1ant_init_hw_config(btcoexist, false, false); - halbtc8723b1ant_init_coex_dm(btcoexist); - halbtc8723b1ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8723b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) -{ - - halbtc8723b1ant_init_hw_config(btcoexist, false, false); - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); */ - halbtc8723b1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8723b1ant_periodical(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ==========================Periodical===========================\n"); - BTC_TRACE(trace_buf); - -#if(BT_AUTO_REPORT_ONLY_8723B_1ANT == 0) - halbtc8723b1ant_query_bt_info(btcoexist); - halbtc8723b1ant_monitor_bt_enable_disable(btcoexist); -#else - halbtc8723b1ant_monitor_bt_ctr(btcoexist); - halbtc8723b1ant_monitor_wifi_ctr(btcoexist); -#if BT_8723B_1ANT_ANTDET_ENABLE - halbtc8723b1ant_monitor_bt_enable_disable(btcoexist); -#endif - - if ((coex_sta->high_priority_tx + coex_sta->high_priority_rx < 50) && - (bt_link_info->hid_exist == true)) - bt_link_info->hid_exist = false; - - if( halbtc8723b1ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust ) - halbtc8723b1ant_run_coexist_mechanism(btcoexist); - - coex_sta->specific_pkt_period_cnt++; - - /* sample to set bt to execute Ant detection */ - /* btcoexist->btc_set_bt_ant_detection(btcoexist, 20, 14); - * - if (psd_scan->is_ant_det_enable) - { - if (psd_scan->psd_gen_count > psd_scan->realseconds) - psd_scan->psd_gen_count = 0; - - halbtc8723b1ant_antenna_detection(btcoexist, psd_scan->realcent_freq, psd_scan->realoffset, psd_scan->realspan, psd_scan->realseconds); - psd_scan->psd_gen_total_count +=2; - psd_scan->psd_gen_count += 2; - } - */ -#endif -} - -void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ -#if BT_8723B_1ANT_ANTDET_ENABLE - static u32 ant_det_count = 0, ant_det_fail_count = 0; - struct btc_board_info *board_info = &btcoexist->board_info; - /*boolean scan, roam;*/ - - if (seconds == 0) { - psd_scan->ant_det_try_count = 0; - psd_scan->ant_det_fail_count = 0; - ant_det_count = 0; - ant_det_fail_count = 0; - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - return; - } - - if (!board_info->btdm_ant_det_finish) { - psd_scan->ant_det_inteval_count = - psd_scan->ant_det_inteval_count + 2; - - if (psd_scan->ant_det_inteval_count >= - BT_8723B_1ANT_ANTDET_RETRY_INTERVAL) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b1ant_psd_antenna_detection_check(btcoexist); - - if (board_info->btdm_ant_det_finish) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n"); - BTC_TRACE(trace_buf); -#if 1 - if (board_info->btdm_ant_num_by_ant_det == 2) - halbtc8723b1ant_mechanism_switch( - btcoexist, true); - else - halbtc8723b1ant_mechanism_switch( - btcoexist, false); -#endif - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n"); - BTC_TRACE(trace_buf); - } - psd_scan->ant_det_inteval_count = 0; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n", - psd_scan->ant_det_inteval_count); - BTC_TRACE(trace_buf); - } - - } -#endif - - -/* - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - - psd_scan->ant_det_bt_tx_time = seconds; - psd_scan->ant_det_bt_le_channel = cent_freq; - - if (seconds == 0) - { - psd_scan->ant_det_try_count = 0; - psd_scan->ant_det_fail_count = 0; - ant_det_count = 0; - ant_det_fail_count = 0; - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - return; - } - else - { - ant_det_count++; - - psd_scan->ant_det_try_count = ant_det_count; - - if (scan ||roam) - { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 6; - } - else if (coex_sta->num_of_profile >= 1) - { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 7; - } - else if (!psd_scan->ant_det_is_ant_det_available) - { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 9; - } - else if (coex_sta->c2h_bt_inquiry_page) - { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 10; - } - else - { - - } - - if (!board_info->btdm_ant_det_finish) - ant_det_fail_count++; - - psd_scan->ant_det_fail_count = ant_det_fail_count; - } -*/ -} - - -void ex_halbtc8723b1ant_display_ant_detection(IN struct btc_coexist *btcoexist) -{ -#if BT_8723B_1ANT_ANTDET_ENABLE - struct btc_board_info *board_info = &btcoexist->board_info; - - if (psd_scan->ant_det_try_count != 0) { - halbtc8723b1ant_psd_show_antenna_detect_result(btcoexist); - - if (board_info->btdm_ant_det_finish) - halbtc8723b1ant_psd_showdata(btcoexist); - return; - } -#endif - - /* halbtc8723b1ant_show_psd_data(btcoexist); */ -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ diff --git a/hal/btc/HalBtc8723b1Ant.h b/hal/btc/HalBtc8723b1Ant.h deleted file mode 100644 index b0cd79d..0000000 --- a/hal/btc/HalBtc8723b1Ant.h +++ /dev/null @@ -1,288 +0,0 @@ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8723B_SUPPORT == 1) -/* ******************************************* - * The following is for 8723B 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8723B_1ANT 1 - -#define BT_INFO_8723B_1ANT_B_FTP BIT(7) -#define BT_INFO_8723B_1ANT_B_A2DP BIT(6) -#define BT_INFO_8723B_1ANT_B_HID BIT(5) -#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2 - -#define BT_8723B_1ANT_WIFI_NOISY_THRESH 50 /* 30 //max: 255 */ - -/* for Antenna detection */ -#define BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 -#define BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 -#define BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 -#define BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT 32 -#define BT_8723B_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY 40000 -#define BT_8723B_1ANT_ANTDET_ENABLE 1 -#define BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 1 -#define BT_8723B_1ANT_ANTDET_BTTXTIME 100 -#define BT_8723B_1ANT_ANTDET_BTTXCHANNEL 39 - -enum bt_info_src_8723b_1ant { - BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8723B_1ANT_MAX -}; - -enum bt_8723b_1ant_bt_status { - BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8723B_1ANT_BT_STATUS_MAX -}; - -enum bt_8723b_1ant_wifi_status { - BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8723B_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8723b_1ant_coex_algo { - BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8723B_1ANT_COEX_ALGO_SCO = 0x1, - BT_8723B_1ANT_COEX_ALGO_HID = 0x2, - BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8723B_1ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8723b_1ant { - /* hw setting */ - u8 pre_ant_pos_type; - u8 cur_ant_pos_type; - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u8 error_condition; -}; - -struct coex_sta_8723b_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - boolean bt_hi_pri_link_exist; - u8 num_of_profile; - boolean bt_abnormal_scan; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - s8 bt_rssi; - boolean bt_tx_rx_mask; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8723B_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_1ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_remote_name_req; - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - u8 bt_retry_cnt; - u8 bt_info_ext; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_agg; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_agg; - - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; - u8 coex_table_type; - - boolean force_lps_on; - u32 wrong_profile_notification; - - u8 a2dp_bit_pool; - u8 cut_version; -}; - -#define BT_8723B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ -#define BT_8723B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ -#define BT_8723B_1ANT_ANTDET_BUF_LEN 16 - -struct psdscan_sta_8723b_1ant { - - u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ - u32 ant_det_bt_tx_time; - u32 ant_det_pre_psdscan_peak_val; - boolean ant_det_is_ant_det_available; - u32 ant_det_psd_scan_peak_val; - boolean ant_det_is_btreply_available; - u32 ant_det_psd_scan_peak_freq; - - u8 ant_det_result; - u8 ant_det_peak_val[BT_8723B_1ANT_ANTDET_BUF_LEN]; - u8 ant_det_peak_freq[BT_8723B_1ANT_ANTDET_BUF_LEN]; - u32 ant_det_try_count; - u32 ant_det_fail_count; - u32 ant_det_inteval_count; - u32 ant_det_thres_offset; - - u32 real_cent_freq; - s32 real_offset; - u32 real_span; - - u32 psd_band_width; /* unit: Hz */ - u32 psd_point; /* 128/256/512/1024 */ - u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_start_point; - u32 psd_stop_point; - u32 psd_max_value_point; - u32 psd_max_value; - u32 psd_start_base; - u32 psd_avg_num; /* 1/8/16/32 */ - u32 psd_gen_count; - boolean is_psd_running; - boolean is_psd_show_max_only; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8723b1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8723b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8723b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); - -void ex_halbtc8723b1ant_display_ant_detection(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8723b1ant_power_on_setting(btcoexist) -#define ex_halbtc8723b1ant_pre_load_firmware(btcoexist) -#define ex_halbtc8723b1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8723b1ant_init_coex_dm(btcoexist) -#define ex_halbtc8723b1ant_ips_notify(btcoexist, type) -#define ex_halbtc8723b1ant_lps_notify(btcoexist, type) -#define ex_halbtc8723b1ant_scan_notify(btcoexist, type) -#define ex_halbtc8723b1ant_connect_notify(btcoexist, type) -#define ex_halbtc8723b1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8723b1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8723b1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8723b1ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8723b1ant_halt_notify(btcoexist) -#define ex_halbtc8723b1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8723b1ant_coex_dm_reset(btcoexist) -#define ex_halbtc8723b1ant_periodical(btcoexist) -#define ex_halbtc8723b1ant_display_coex_info(btcoexist) -#define ex_halbtc8723b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8723b1ant_display_ant_detection(btcoexist) - -#endif - -#endif diff --git a/hal/btc/HalBtc8723b2Ant.c b/hal/btc/HalBtc8723b2Ant.c deleted file mode 100644 index 80c1de0..0000000 --- a/hal/btc/HalBtc8723b2Ant.c +++ /dev/null @@ -1,4920 +0,0 @@ -/* ************************************************************ - * Description: - * - * This file is for RTL8723B Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "Mp_Precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8723B_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8723b_2ant glcoex_dm_8723b_2ant; -static struct coex_dm_8723b_2ant *coex_dm = &glcoex_dm_8723b_2ant; -static struct coex_sta_8723b_2ant glcoex_sta_8723b_2ant; -static struct coex_sta_8723b_2ant *coex_sta = &glcoex_sta_8723b_2ant; - -const char *const glbt_info_src_8723b_2ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8723b_2ant = 20151223; -u32 glcoex_ver_8723b_2ant = 0x4a; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8723b2ant_ - * ************************************************************ */ -u8 halbtc8723b2ant_bt_rssi_state(u8 *ppre_bt_rssi_state, u8 level_num, - u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = *ppre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return *ppre_bt_rssi_state; - } - - if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - *ppre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8723b2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh, - IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = *pprewifi_rssi_state; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || - (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return *pprewifi_rssi_state; - } - - if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || - (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - *pprewifi_rssi_state = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8723b2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 2) - bt_disabled = true; - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - - coex_sta->bt_disabled = bt_disabled; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - if (bt_disabled) { - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - } - } -} - - -void halbtc8723b2ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); -} - -void halbtc8723b2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if ((coex_sta->low_priority_tx > 1050) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - if ((coex_sta->low_priority_rx >= 950) && - (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) && - (!coex_sta->under_ips)) - bt_link_info->slave_role = true; - else - bt_link_info->slave_role = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); -} - -void halbtc8723b2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ - - - if (coex_sta->under_ips) { - coex_sta->crc_ok_cck = 0; - coex_sta->crc_ok_11g = 0; - coex_sta->crc_ok_11n = 0; - coex_sta->crc_ok_11n_agg = 0; - - coex_sta->crc_err_cck = 0; - coex_sta->crc_err_11g = 0; - coex_sta->crc_err_11n = 0; - coex_sta->crc_err_11n_agg = 0; - } else { - coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf88); - coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf94); - coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf90); - coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfb8); - - coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf84); - coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf96); - coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf92); - coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfba); - } - - /* reset counter */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0); -} - -void halbtc8723b2ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -boolean halbtc8723b2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) || - (BTC_RSSI_STATE_LOW == wifi_rssi_state)) - return true; - - } - - return false; -} - -void halbtc8723b2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8723b2ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8723B_2ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_HID_A2DP; - } - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8723b2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - -void halbtc8723b2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN u8 dec_bt_pwr_lvl) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = dec_bt_pwr_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); -} - -void halbtc8723b2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 dec_bt_pwr_lvl) -{ - coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; - - if (!force_exec) { - if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) - return; - } - halbtc8723b2ant_set_fw_dec_bt_pwr(btcoexist, - coex_dm->cur_bt_dec_pwr_lvl); - - coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; -} - -void halbtc8723b2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8723b2ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8723b2ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8723b2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8723b2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - -void halbtc8723b2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist, - IN boolean rx_rf_shrink_on) -{ - if (rx_rf_shrink_on) { - /* Shrink RF Rx LPF corner */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Shrink RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, - 0xffffc); - } else { - /* Resume RF Rx LPF corner */ - /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ - if (btcoexist->initilized) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Resume RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, coex_dm->bt_rf_0x1e_backup); - } - } -} - -void halbtc8723b2ant_rf_shrink(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rx_rf_shrink_on) -{ - coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; - - if (!force_exec) { - if (coex_dm->pre_rf_rx_lpf_shrink == - coex_dm->cur_rf_rx_lpf_shrink) - return; - } - halbtc8723b2ant_set_sw_rf_rx_lpf_corner(btcoexist, - coex_dm->cur_rf_rx_lpf_shrink); - - coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; -} - -void halbtc8723b2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf4; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf5; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf6; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8723b2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8723b2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8723b2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, - IN u32 level) -{ - u8 val = (u8)level; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Write SwDacSwing = 0x%x\n", level); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val); -} - -void halbtc8723b2ant_set_sw_full_time_dac_swing(IN struct btc_coexist - *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) -{ - if (sw_dac_swing_on) - halbtc8723b2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl); - else - halbtc8723b2ant_set_dac_swing_reg(btcoexist, 0x18); -} - - -void halbtc8723b2ant_dac_swing(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) -{ - coex_dm->cur_dac_swing_on = dac_swing_on; - coex_dm->cur_dac_swing_lvl = dac_swing_lvl; - - if (!force_exec) { - if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && - (coex_dm->pre_dac_swing_lvl == - coex_dm->cur_dac_swing_lvl)) - return; - } - delay_ms(30); - halbtc8723b2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, - dac_swing_lvl); - - coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; - coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; -} - -void halbtc8723b2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean adc_back_off) -{ - if (adc_back_off) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x3); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x1); - } -} - -void halbtc8723b2ant_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean adc_back_off) -{ - coex_dm->cur_adc_back_off = adc_back_off; - - if (!force_exec) { - if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) - return; - } - halbtc8723b2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off); - - coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; -} - -void halbtc8723b2ant_set_agc_table(IN struct btc_coexist *btcoexist, - IN boolean agc_table_en) -{ - u8 rssi_adjust_val = 0; - - /* =================BB AGC Gain Table */ - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6e1A0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6d1B0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6c1C0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6b1D0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6a1E0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x691F0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x68200001); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa4200001); - } - - - /* =================RF Gain */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x38fff); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x38ffe); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x380c3); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x28ce6); - } - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x1); - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x38fff); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x38ffe); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x380c3); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x28ce6); - } - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x0); - - /* set rssi_adjust_val for wifi module. */ - if (agc_table_en) - rssi_adjust_val = 8; - btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, - &rssi_adjust_val); -} - -void halbtc8723b2ant_agc_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean agc_table_en) -{ - coex_dm->cur_agc_table_en = agc_table_en; - - if (!force_exec) { - if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) - return; - } - halbtc8723b2ant_set_agc_table(btcoexist, agc_table_en); - - coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; -} - -void halbtc8723b2ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8723b2ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8723b2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8723b2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_sta->coex_table_type = type; - - switch (type) { - case 0: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, 0xffffff, 0x3); - break; - case 1: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5afa5afa, 0xffffff, 0x3); - break; - case 2: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3); - break; - case 3: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 4: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0xffffffff, 0xffffffff, 0xffffff, 0x3); - break; - case 5: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3); - break; - case 6: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 7: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 8: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 9: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 10: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 11: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 12: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 13: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 14: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); - break; - case 15: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8723b2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8723b2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8723b2ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8723b2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8723b2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8723b2ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8723b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - - - if ((coex_sta->a2dp_exist) && (coex_sta->hid_exist)) - byte5 = byte5 | 0x1; - - h2c_parameter[0] = byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = byte5; - - coex_dm->ps_tdma_para[0] = byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8723b2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, - IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, - IN boolean limited_dig, IN boolean bt_lna_constrain) -{ - /* - u32 wifi_bw; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if(BTC_WIFI_BW_HT40 != wifi_bw) - { - if (shrink_rx_lpf) - shrink_rx_lpf = false; - } - */ - - /* halbtc8723b2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); */ - halbtc8723b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8723b2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, - IN boolean agc_table_shift, IN boolean adc_back_off, - IN boolean sw_dac_swing, IN u32 dac_swing_lvl) -{ - /* halbtc8723b2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */ - /* halbtc8723b2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */ - /* halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, dac_swing_lvl); */ -} - -void halbtc8723b2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - PADAPTER pAdapter = btcoexist->Adapter; - u32 fw_ver = 0, u32tmp = 0, cnt_bt_cal_chk = 0; - boolean pg_ext_switch = false; - boolean use_ext_switch = false; - u8 h2c_parameter[2] = {0}; - u32 u32tmp_1[4]; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_EXT_SWITCH, &pg_ext_switch); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, - &fw_ver); /* [31:16]=fw ver, [15:0]=fw sub ver */ - - if ((fw_ver > 0 && fw_ver < 0xc0000) || pg_ext_switch) - use_ext_switch = true; - - if (init_hwcfg) { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x39, 0x8, 0x1); - btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x944, 0x3, 0x3); - btcoexist->btc_write_1byte(btcoexist, 0x930, 0x77); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1); - - if (fw_ver >= 0x180000) { - /* Use H2C to set GNT_BT to High to avoid A2DP click */ - h2c_parameter[0] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, - h2c_parameter); - - cnt_bt_cal_chk = 0; - while(1) - { - if( pAdapter->bFWReady == FALSE ) - { - //RT_TRACE(COMP_INIT , DBG_LOUD, ("halbtc8723b2ant_SetAntPath(): we don't need to wait for H2C command completion because of Fw download fail!!!\n")); - break; - } - - if( btcoexist->btc_read_1byte(btcoexist, 0x765) == 0x18 ) - break; - - cnt_bt_cal_chk++; - if( cnt_bt_cal_chk > 20 ) - break; - } - } else - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); - u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); - if( (u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte(btcoexist, 0x948, u32tmp_1[0]); - else - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); /* WiFi TRx Mask off */ - /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */ - /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x01); //BT TRx Mask off */ - - if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { - /* tell firmware "no antenna inverse" */ - h2c_parameter[0] = 0; - } else { - /* tell firmware "antenna inverse" */ - h2c_parameter[0] = 1; - } - - if (use_ext_switch) { - /* ext switch type */ - h2c_parameter[1] = 1; - } else { - /* int switch type */ - h2c_parameter[1] = 0; - } - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, h2c_parameter); - } else { - if (fw_ver >= 0x180000) { - /* Use H2C to set GNT_BT to "Control by PTA"*/ - h2c_parameter[0] = 0; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, - h2c_parameter); - - cnt_bt_cal_chk = 0; - while(1) - { - if( pAdapter->bFWReady == FALSE ) - { - //RT_TRACE(COMP_INIT , DBG_LOUD, ("halbtc8723b2ant_SetAntPath(): we don't need to wait for H2C command completion because of Fw download fail!!!\n")); - break; - } - - if( btcoexist->btc_read_1byte(btcoexist, 0x765) == 0x0 ) - break; - - cnt_bt_cal_chk++; - if( cnt_bt_cal_chk > 20 ) - break; - } - } else - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x0); - } - - /* ext switch setting */ - if (use_ext_switch) { - if (init_hwcfg) { - /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp |= BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } - u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); - if( (u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte(btcoexist, 0x948, u32tmp_1[0]); - else - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - - switch (ant_pos_type) { - case BTC_ANT_WIFI_AT_MAIN: - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0x92c, 0x3, - 0x1); /* ext switch main at wifi */ - break; - case BTC_ANT_WIFI_AT_AUX: - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0x92c, 0x3, - 0x2); /* ext switch aux at wifi */ - break; - } - } else { /* internal switch */ - if (init_hwcfg) { - /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp |= BIT(23); - u32tmp &= ~BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, - 0x0); /* fixed external switch S1->Main, S0->Aux */ - switch (ant_pos_type) { - case BTC_ANT_WIFI_AT_MAIN: - u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); - if( (u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte(btcoexist, 0x948, u32tmp_1[0]); - else - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - break; - case BTC_ANT_WIFI_AT_AUX: - u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); - if( (u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte(btcoexist, 0x948, u32tmp_1[0]); - else - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x280); - break; - } - } -} -#if 0 -boolean halbtc8723b2ant_CoexSwitchThresCheck(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state1, bt_rssi_state; - u32 vendor; - u8 offset = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor); - - /* if (vendor == BTC_VENDOR_LENOVO) */ - /* offset = 20; */ - - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - if (BTC_RSSI_LOW(wifi_rssi_state1) || BTC_RSSI_LOW(bt_rssi_state)) - return true; - - return false; -} -#endif - -void halbtc8723b2ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state1, bt_rssi_state; - s8 wifi_duration_adjust = 0x0; - u8 psTdmaByte4Modify = 0x0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s turn %s PS TDMA, type=%d\n", - (force_exec ? "force to" : ""), (turn_on ? "ON" : "OFF"), type); - BTC_TRACE(trace_buf); - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - if (!(BTC_RSSI_HIGH(wifi_rssi_state1) && - BTC_RSSI_HIGH(bt_rssi_state)) && turn_on) - /* if (halbtc8723b2ant_CoexSwitchThresCheck(btcoexist) && turn_on) */ - { - type = type + 100; /* for WiFi RSSI low or BT RSSI low */ - coex_dm->is_switch_to_1dot5_ant = true; - } else - coex_dm->is_switch_to_1dot5_ant = false; - - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_sta->scan_ap_num <= 5) { - if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - else if (coex_sta->a2dp_bit_pool >= 35) - wifi_duration_adjust = -10; - else - wifi_duration_adjust = 5; - } else if (coex_sta->scan_ap_num <= 20) { - if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - else if (coex_sta->a2dp_bit_pool >= 35) - wifi_duration_adjust = -10; - else - wifi_duration_adjust = 0; - } else if (coex_sta->scan_ap_num <= 40) { - if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - else if (coex_sta->a2dp_bit_pool >= 35) - wifi_duration_adjust = -10; - else - wifi_duration_adjust = -5; - } else { - if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - else if (coex_sta->a2dp_bit_pool >= 35) - wifi_duration_adjust = -10; - else - wifi_duration_adjust = -10; - } - - if ((bt_link_info->slave_role == true) && (bt_link_info->a2dp_exist)) - psTdmaByte4Modify = - 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - - - if (turn_on) { - switch (type) { - case 1: - default: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x03, 0xf1, - 0x90 | psTdmaByte4Modify); - break; - case 2: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d + wifi_duration_adjust, 0x03, 0xf1, - 0x90 | psTdmaByte4Modify); - break; - case 3: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, 0x90 | - psTdmaByte4Modify); - break; - case 4: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x03, 0xf1, 0x90 | - psTdmaByte4Modify); - break; - case 5: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x3, 0x70, - 0x90 | psTdmaByte4Modify); - break; - case 6: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d + wifi_duration_adjust, 0x3, 0x70, - 0x90 | psTdmaByte4Modify); - break; - case 7: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0x70, 0x90 | - psTdmaByte4Modify); - break; - case 8: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xa3, - 0x10, 0x3, 0x70, 0x90 | - psTdmaByte4Modify); - break; - case 9: - /* - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x03, 0xf1, - 0x90 | psTdmaByte4Modify); - */ - /* Bryant Modify for BT no-profile busy case */ - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x03, 0xf1, - 0x91); - - break; - case 10: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d + wifi_duration_adjust, 0x03, 0xf1, - 0x90 | psTdmaByte4Modify); - break; - case 11: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, 0x90 | - psTdmaByte4Modify); - break; - case 12: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0xf1, 0x90 | - psTdmaByte4Modify); - break; - case 13: - /* - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x3, 0x70, - 0x90 | psTdmaByte4Modify); - */ - /* Bryant Modify for BT no-profile busy case */ - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x3, 0x70, - 0x91); - break; - case 14: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d + wifi_duration_adjust, 0x3, 0x70, - 0x90 | psTdmaByte4Modify); - break; - case 15: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0x70, 0x90 | - psTdmaByte4Modify); - break; - case 16: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0x70, 0x90 | - psTdmaByte4Modify); - break; - case 17: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xa3, - 0x2f, 0x2f, 0x60, 0x90); - break; - case 18: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x5, 0x5, 0xe1, 0x90); - break; - case 19: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0xe1, 0x90); - break; - case 20: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0x60, 0x90); - break; - case 21: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x03, 0x70, 0x90); - break; - case 22: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x03, 0xf1, 0x90); - break; - case 23: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x03, 0x71, 0x10); - break; - - case 33: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, 0x91); - - break; - case 71: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x03, 0xf1, - 0x90); - break; - case 101: - case 105: - case 113: - case 171: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x3a + wifi_duration_adjust, 0x03, 0x70, - 0x50 | psTdmaByte4Modify); - break; - case 102: - case 106: - case 110: - case 114: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x2d + wifi_duration_adjust, 0x03, 0x70, - 0x50 | psTdmaByte4Modify); - break; - case 103: - case 107: - case 111: - case 115: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1c, 0x03, 0x70, 0x50 | - psTdmaByte4Modify); - break; - case 104: - case 108: - case 112: - case 116: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x10, 0x03, 0x70, 0x50 | - psTdmaByte4Modify); - break; - case 109: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0xf1, 0x90 | - psTdmaByte4Modify); - break; - /* case 113: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0x70, 0x90 | - psTdmaByte4Modify); - break; */ - case 121: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x03, 0x70, 0x90 | - psTdmaByte4Modify); - break; - case 122: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x03, 0x71, 0x11); - break; - case 123: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x03, 0x71, 0x10); - break; - case 133: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1c, 0x3, 0x70, 0x51); - - break; - } - } else { - /* disable PS tdma */ - switch (type) { - case 0: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - case 1: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - default: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8723b2ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8723b2ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8723b2ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8723b2ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8723b2ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - - -void halbtc8723b2ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* fw all off */ - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8723b2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0); - - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - coex_sta->pop_event_cnt = 0; - -} - -void halbtc8723b2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - boolean wifi_connected = false; - boolean low_pwr_disable = true; - boolean scan = false, link = false, roam = false; - boolean wifi_busy = false; - - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - if (coex_sta->bt_abnormal_scan) { - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 23); - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - } else if (scan || link || roam) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link process + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 7); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - } else if (wifi_connected) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 7); - - if (wifi_busy) - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - else - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi no-link + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - } - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - /* - coex_dm->need_recover0x948 = true; - coex_dm->backup0x948 = btcoexist->btc_read_4byte(btcoexist, 0x948); - - halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_AUX, false, false); - */ -} - - -void halbtc8723b2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist) -{ - u32 u32tmp; - u8 u8tmpa, u8tmpb; - - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 15); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n", - u32tmp, u8tmpa, u8tmpb); - BTC_TRACE(trace_buf); -} - -boolean halbtc8723b2ant_action_wifi_idle_process(IN struct btc_coexist - *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u8 ap_num = 0; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - /* wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES-coex_dm->switch_thres_offset-coex_dm->switch_thres_offset, 0); */ - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); - - /* define the office environment */ - if (BTC_RSSI_HIGH(wifi_rssi_state1) && - (coex_sta->hid_exist == true) && - (coex_sta->a2dp_exist == true)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi idle process for BT HID+A2DP exist!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - return true; - } else { - halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x18); - return false; - } - - -} - - - -boolean halbtc8723b2ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - boolean bt_hs_on = false, low_pwr_disable = false; - boolean asus_8723b = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non-connected idle!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - common = true; - } else { - if (BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, - false, false, 0x8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - halbtc8723b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8723b2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 0xb); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else if (BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status) { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (bt_hs_on) - return false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, - false, false, 0x8); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - halbtc8723b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8723b2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 0xb); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - /* btcoexist->btc_get(btcoexist, - BTC_GET_BL_IS_ASUS_8723B, &asus_8723b); - if (!asus_8723b) - common = false; - else - common = halbtc8723b2ant_action_wifi_idle_process( - btcoexist); */ - common = false; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - /* common = false; */ - common = halbtc8723b2ant_action_wifi_idle_process( - btcoexist); - } - } - } - - return common; -} -void halbtc8723b2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, - IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0; - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - { - if (sco_hid) { - if (tx_pause) { - if (max_interval == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } else if (max_interval == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (max_interval == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } else { - if (max_interval == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } else if (max_interval == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (max_interval == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } else { - if (tx_pause) { - if (max_interval == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (max_interval == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (max_interval == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } - } else { - if (max_interval == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (max_interval == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (max_interval == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } - } - } - } - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* accquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - - if ((coex_sta->low_priority_tx) > 1050 || - (coex_sta->low_priority_rx) > 1250) - retry_count++; - - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) {/* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ - if (wait_count <= 2) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ - if (wait_count == 1) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (max_interval == 1) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 13); - coex_dm->ps_tdma_du_adj_type = 13; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 71); - coex_dm->ps_tdma_du_adj_type = 71; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 71); - coex_dm->ps_tdma_du_adj_type = - 71; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } - } - } - } else if (max_interval == 2) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } - } - } - } else if (max_interval == 3) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } - } - } - - /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ - /* then we have to adjust it back to the previous record one. */ - if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { - boolean scan = false, link = false, roam = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", - coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (!scan && !link && !roam) - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); - BTC_TRACE(trace_buf); - } - } -} - -/* SCO only or SCO+PAN(HS) */ -void halbtc8723b2ant_action_sco(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for SCO quality at 11b/g mode */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else /* for SCO quality & wifi performance balance at 11n mode */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); /* for voice quality */ - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - true, 0x4); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - true, 0x4); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - true, 0x4); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - true, 0x4); - } - } -} - - -void halbtc8723b2ant_action_hid(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - else /* for HID quality & wifi performance balance at 11n mode */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9); - - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - else - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8723b2ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - u8 ap_num = 0; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); - - /* define the office environment */ - if ((ap_num >= 10) && BTC_RSSI_HIGH(wifi_rssi_state1) && - BTC_RSSI_HIGH(bt_rssi_state)) { - /* dbg_print(" AP#>10(%d)\n", ap_num); */ - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - true, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - true, 0x18); - } - return; - - } - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, false, - 1); - else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, true, 1); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8723b2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, true, 2); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8723b2ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 10); - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); - else - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - - -/* PAN(HS) only */ -void halbtc8723b2ant_action_pan_hs(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* PAN(EDR)+A2DP */ -void halbtc8723b2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u8 ap_num = 0; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &ap_num); - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 12); - - if(ap_num < 10) - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 1); - else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 3); - - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - if(ap_num < 10) - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 1); - else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 3); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8723b2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 14); - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (BTC_WIFI_BW_HT40 == wifi_bw) { - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 3); - /* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x780); - } else { - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 6); - /* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - } - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 2); - } else { - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - /* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 2); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* HID+A2DP+PAN(EDR) */ -void halbtc8723b2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 14); - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, - true, 3); - else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, - false, 3); - } else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 3); - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8723b2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - u8 ap_num = 0; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - /* bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0); */ - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 3, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 37); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &ap_num); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x5); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_LEGACY == wifi_bw) { - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - } else { - /* only 802.11N mode we have to dec bt power to 4 degree */ - if (BTC_RSSI_HIGH(bt_rssi_state)) { - /* need to check ap Number of Not */ - if (ap_num < 10) - halbtc8723b2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, 4); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, 2); - } else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - } - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 14); - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - if(BTC_RSSI_HIGH(bt_rssi_state)) { - if(ap_num < 10) - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 1); - else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 3); - } else { - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 18); - btcoexist->btc_write_1byte(btcoexist, 0x456, 0x38); - btcoexist->btc_write_2byte(btcoexist, 0x42a, 0x0808); - btcoexist->btc_write_4byte(btcoexist, 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, 0x434, 0x01010000); - - if(ap_num < 10) - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 1); - else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 3); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8723b2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) -{ - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8723b2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); -} - -void halbtc8723b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - u32 num_of_wifi_link = 0; - u32 wifi_link_status = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean miracast_plus_bt = false; - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_bt_whck_test(btcoexist); - return; - } - - algorithm = halbtc8723b2ant_action_algorithm(btcoexist); - if (coex_sta->c2h_bt_inquiry_page && - (BT_8723B_2ANT_COEX_ALGO_PANHS != algorithm)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_bt_inquiry(btcoexist); - return; - } else { - /* - if(coex_dm->need_recover0x948) - { - coex_dm->need_recover0x948 = false; - btcoexist->btc_write_4byte(btcoexist, 0x948, coex_dm->backup0x948); - } - */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under Link Process !!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_wifi_link_process(btcoexist); - return; - } - - /* for P2P */ - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) - miracast_plus_bt = true; - else - miracast_plus_bt = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8723b2ant_action_wifi_multi_port(btcoexist); - - return; - } else { - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - coex_dm->cur_algorithm = algorithm; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", - coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - - if (halbtc8723b2ant_is_common_action(btcoexist)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant common.\n"); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - } else { - if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", - coex_dm->pre_algorithm, coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - } - switch (coex_dm->cur_algorithm) { - case BT_8723B_2ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_sco(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_hid(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_a2dp(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_pan_edr(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_pan_hs(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_pan_edr_hid(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_hid_a2dp(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_coex_all_off(btcoexist); - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8723b2ant_wifi_off_hw_cfg(IN struct btc_coexist *btcoexist) -{ - boolean is_in_mp_mode = false; - u8 h2c_parameter[2] = {0}; - u32 fw_ver = 0; - - /* set wlan_act to low */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x780); /* WiFi goto standby while GNT_BT 0-->1 */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - if (fw_ver >= 0x180000) { - /* Use H2C to set GNT_BT to HIGH */ - h2c_parameter[0] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, h2c_parameter); - } else - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE, - &is_in_mp_mode); - if (!is_in_mp_mode) - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x0); /* BT select s0/s1 is controlled by BT */ - else - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x1); /* BT select s0/s1 is controlled by WiFi */ -} - -void halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up) -{ - u8 u8tmp = 0; - u32 vendor; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor); - if (vendor == BTC_VENDOR_LENOVO) - coex_dm->switch_thres_offset = 0; - else if (vendor == BTC_VENDOR_ASUS) - coex_dm->switch_thres_offset = 0; - else - coex_dm->switch_thres_offset = 20; - - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - /* backup rf 0x1e value */ - coex_dm->bt_rf_0x1e_backup = - btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff); - - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* Antenna config */ - halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true, - false); - coex_sta->dis_ver_info_cnt = 0; - - /* PTA parameter */ - halbtc8723b2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - /* Enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, - 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); -} - -/* ************************************************************ - * work around function start with wa_halbtc8723b2ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8723b2ant_ - * ************************************************************ */ -void ex_halbtc8723b2ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u16 u16tmp = 0x0; - u32 value = 0; - u32 u32tmp_1[4]; - - btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20); - - /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - DbgPrint("--- TEST 5 ---\n"); - - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - - if (btcoexist->chip_interface == BTC_INTF_USB) { - /* fixed at S0 for USB interface */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - } else { - /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ - if (board_info->single_ant_path == 0) { - /* set to S1 */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - } - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, - &value); - } -} - -void ex_halbtc8723b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - if (btcoexist->chip_interface == BTC_INTF_USB) { - /* fixed at S0 for USB interface */ - u8tmp |= 0x1; /* antenna inverse */ - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - } else { - /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ - if (board_info->single_ant_path == 0) { - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - u8tmp |= 0x1; /* antenna inverse */ - } - - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384, - u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, - u8tmp); - } -} - -void ex_halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8723b2ant_init_hw_config(btcoexist, true); -} - -void ex_halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723b2ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8723b2ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u32 u32tmp[4]; - u32 fa_of_dm, fa_cck; - u32 fw_ver = 0, bt_patch_ver = 0; - static u8 pop_report_in_10s = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c", - "Version Coex/ Fw/ Patch/ Cut", - glcoex_ver_date_8723b_2ant, glcoex_ver_8723b_2ant, fw_ver, - bt_patch_ver, bt_patch_ver, coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Abnormal scan", - (coex_sta->bt_abnormal_scan) ? "Yes" : "No"); - CL_PRINTF(cli_buf); - - pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); - CL_PRINTF(cli_buf); - - if (pop_report_in_10s >= 5) { - coex_sta->pop_event_cnt = 0; - pop_report_in_10s = 0; - } - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d / %d / %d / %d / %d / %d", - "SCO/HID/PAN/A2DP/NameReq/WHQL", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist, - coex_sta->c2h_bt_remote_name_req, - coex_sta->bt_whck_test); - CL_PRINTF(cli_buf); - - { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Role", - (bt_link_info->slave_role) ? "Slave" : "Master"); - CL_PRINTF(cli_buf); - } - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", - "A2DP Rate/Bitpool", - (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8723B_2ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8723b_2ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - /* Sw mechanism */ - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Sw mechanism] (before Manual)============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Sw mechanism]============"); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", - "SM1[ShRf/ LpRA/ LimDig]", - coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, - coex_dm->limited_dig); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", - "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", - coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, - coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); - CL_PRINTF(cli_buf); - - /* Fw mechanism */ - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Fw mechanism] (before Manual) ============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Fw mechanism]============"); - - ps_tdma_case = coex_dm->cur_ps_tdma; - - if (coex_dm->is_switch_to_1dot5_ant) - ps_tdma_case = ps_tdma_case + 100; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "On" : "Off"), - (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Coex Table Type", - coex_sta->coex_table_type); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "DecBtPwr/ IgnWlanAct", - coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", - "RF-A, 0x1e initVal", - coex_dm->bt_rf_0x1e_backup); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x880); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x778/0x880[29:25]", - u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25); - CL_PRINTF(cli_buf); - - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x765); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x948/ 0x67[5] / 0x765", - u32tmp[0], ((u8tmp[0] & 0x20) >> 5), u8tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x92c); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x930); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x944); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]", - u32tmp[0] & 0x3, u32tmp[1] & 0xff, u32tmp[2] & 0x3); - CL_PRINTF(cli_buf); - - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x39); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x38[11]/0x40/0x4c[24:23]/0x64[0]", - ((u8tmp[0] & 0x8) >> 3), u8tmp[1], - ((u32tmp[0] & 0x01800000) >> 23), u8tmp[2] & 0x1); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xc50(dig)/0x49c(null-drop)", - u32tmp[0] & 0xff, u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8); - u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c); - - fa_of_dm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000) - >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) + \ - ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] & - 0xffff) ; - fa_cck = (u8tmp[0] << 8) + u8tmp[1]; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "OFDM-CCA/OFDM-FA/CCK-FA", - u32tmp[0] & 0xffff, fa_of_dm, fa_cck); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-Agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-Agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 1) - /* halbtc8723b2ant_monitor_bt_ctr(btcoexist); */ -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8723b2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - halbtc8723b2ant_wifi_off_hw_cfg(btcoexist); - halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - halbtc8723b2ant_coex_all_off(btcoexist); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; - halbtc8723b2ant_init_hw_config(btcoexist, false); - halbtc8723b2ant_init_coex_dm(btcoexist); - halbtc8723b2ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8723b2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8723b2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u32 u32tmp; - u8 u8tmpa, u8tmpb; - - - - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - if (BTC_SCAN_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, FALSE, FALSE); - } else if (BTC_SCAN_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n", - u32tmp, u8tmpa, u8tmpb); - BTC_TRACE(trace_buf); -} - -void ex_halbtc8723b2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_ASSOCIATE_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, FALSE, FALSE); - } else if (BTC_ASSOCIATE_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8723b2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - u8 ap_num = 0; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, FALSE, FALSE); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = 0x1; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else { - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &ap_num); - if (ap_num < 10) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); -} - -void ex_halbtc8723b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (type == BTC_PACKET_DHCP) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], DHCP Packet notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8723b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean bt_busy = false, limited_dig = false; - boolean wifi_connected = false; - - coex_sta->c2h_bt_info_req_sent = false; - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8723B_2ANT_MAX) - rsp_source = BT_INFO_SRC_8723B_2ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n"); - BTC_TRACE(trace_buf); - return; - } - - /* if 0xff, it means BT is under WHCK test */ - if (bt_info == 0xff) - coex_sta->bt_whck_test = true; - else - coex_sta->bt_whck_test = false; - - if (BT_INFO_SRC_8723B_2ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_remote_name_req = true; - else - coex_sta->c2h_bt_remote_name_req = false; - - if (coex_sta->bt_info_c2h[rsp_source][1] == 0x49) { - coex_sta->a2dp_bit_pool = - coex_sta->bt_info_c2h[rsp_source][6]; - } else - coex_sta->a2dp_bit_pool = 0; - - coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] - & 0x40); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, - &coex_sta->bt_tx_rx_mask); - if (coex_sta->bt_tx_rx_mask) { - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x3c, 0x01); - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8723b2ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8723b2ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if ((coex_sta->bt_info_ext & BIT(3))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, - false); - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - } -#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8723b2ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8723B_2ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8723B_2ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8723B_2ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8723B_2ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8723B_2ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8723B_2ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - - if ((coex_sta->hid_exist == false) && - (coex_sta->c2h_bt_inquiry_page == false) && - (coex_sta->sco_exist == false)) { - if (coex_sta->high_priority_tx + - coex_sta->high_priority_rx >= 160) { - coex_sta->hid_exist = true; - bt_info = bt_info | 0x28; - } - } - } - - halbtc8723b2ant_update_bt_link_info(btcoexist); - - if (!(bt_info & BT_INFO_8723B_2ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8723B_2ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8723B_2ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8723B_2ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8723B_2ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8723B_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8723B_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { - bt_busy = true; - limited_dig = true; - } else { - bt_busy = false; - limited_dig = false; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - coex_dm->limited_dig = limited_dig; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); - - halbtc8723b2ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8723b2ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723b2ant_wifi_off_hw_cfg(btcoexist); - /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */ - /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); //BT goto standby while GNT_BT 1-->0 */ - halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8723b2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); -} - -void ex_halbtc8723b2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_init_hw_config(btcoexist, false); - halbtc8723b2ant_init_coex_dm(btcoexist); - halbtc8723b2ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8723b2ant_periodical(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ==========================Periodical===========================\n"); - BTC_TRACE(trace_buf); - if (coex_sta->dis_ver_info_cnt <= 5) { - coex_sta->dis_ver_info_cnt += 1; - if (coex_sta->dis_ver_info_cnt == 3) { - /* Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set GNT_BT control by PTA\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_set_ant_path(btcoexist, - BTC_ANT_WIFI_AT_MAIN, false, false); - } - } - -#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 0) - halbtc8723b2ant_query_bt_info(btcoexist); - halbtc8723b2ant_monitor_bt_enable_disable(btcoexist); -#else - halbtc8723b2ant_monitor_bt_ctr(btcoexist); - halbtc8723b2ant_monitor_wifi_ctr(btcoexist); - - /* for some BT speaker that Hi-Pri pkt appear begore start play, this will cause HID exist */ - if ((coex_sta->high_priority_tx + coex_sta->high_priority_rx < 50) && - (bt_link_info->hid_exist == true)) - bt_link_info->hid_exist = false; - - if (halbtc8723b2ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust) - halbtc8723b2ant_run_coexist_mechanism(btcoexist); -#endif -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ - diff --git a/hal/btc/HalBtc8723b2Ant.h b/hal/btc/HalBtc8723b2Ant.h deleted file mode 100644 index 4fe39b2..0000000 --- a/hal/btc/HalBtc8723b2Ant.h +++ /dev/null @@ -1,214 +0,0 @@ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8723B_SUPPORT == 1) -/* ******************************************* - * The following is for 8723B 2Ant BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8723B_2ANT 1 - - -#define BT_INFO_8723B_2ANT_B_FTP BIT(7) -#define BT_INFO_8723B_2ANT_B_A2DP BIT(6) -#define BT_INFO_8723B_2ANT_B_HID BIT(5) -#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8723B_2ANT_B_CONNECTION BIT(0) - -#define BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT 2 - - -#define BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 /* WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */ -#define BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES 46 /* BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */ - -enum bt_info_src_8723b_2ant { - BT_INFO_SRC_8723B_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8723B_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8723B_2ANT_MAX -}; - -enum bt_8723b_2ant_bt_status { - BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8723B_2ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8723B_2ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8723B_2ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8723B_2ANT_BT_STATUS_MAX -}; - -enum bt_8723b_2ant_coex_algo { - BT_8723B_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8723B_2ANT_COEX_ALGO_SCO = 0x1, - BT_8723B_2ANT_COEX_ALGO_HID = 0x2, - BT_8723B_2ANT_COEX_ALGO_A2DP = 0x3, - BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8723B_2ANT_COEX_ALGO_PANEDR = 0x5, - BT_8723B_2ANT_COEX_ALGO_PANHS = 0x6, - BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8723B_2ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8723b_2ant { - /* fw mechanism */ - u8 pre_bt_dec_pwr_lvl; - u8 cur_bt_dec_pwr_lvl; - u8 pre_fw_dac_swing_lvl; - u8 cur_fw_dac_swing_lvl; - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean reset_tdma_adjust; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - - /* sw mechanism */ - boolean pre_rf_rx_lpf_shrink; - boolean cur_rf_rx_lpf_shrink; - u32 bt_rf_0x1e_backup; - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - boolean pre_dac_swing_on; - u32 pre_dac_swing_lvl; - boolean cur_dac_swing_on; - u32 cur_dac_swing_lvl; - boolean pre_adc_back_off; - boolean cur_adc_back_off; - boolean pre_agc_table_en; - boolean cur_agc_table_en; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - boolean need_recover0x948; - u32 backup0x948; - - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - boolean is_switch_to_1dot5_ant; - u8 switch_thres_offset; -}; - -struct coex_sta_8723b_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - boolean bt_abnormal_scan; - boolean under_lps; - boolean under_ips; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - u8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8723B_2ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_2ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_remote_name_req; - u8 bt_retry_cnt; - u8 bt_info_ext; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_agg; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_agg; - - u8 coex_table_type; - boolean force_lps_on; - - u8 dis_ver_info_cnt; - - u8 a2dp_bit_pool; - u8 cut_version; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8723b2ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8723b2ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8723b2ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b2ant_display_coex_info(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8723b2ant_power_on_setting(btcoexist) -#define ex_halbtc8723b2ant_pre_load_firmware(btcoexist) -#define ex_halbtc8723b2ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8723b2ant_init_coex_dm(btcoexist) -#define ex_halbtc8723b2ant_ips_notify(btcoexist, type) -#define ex_halbtc8723b2ant_lps_notify(btcoexist, type) -#define ex_halbtc8723b2ant_scan_notify(btcoexist, type) -#define ex_halbtc8723b2ant_connect_notify(btcoexist, type) -#define ex_halbtc8723b2ant_media_status_notify(btcoexist, type) -#define ex_halbtc8723b2ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8723b2ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8723b2ant_halt_notify(btcoexist) -#define ex_halbtc8723b2ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8723b2ant_periodical(btcoexist) -#define ex_halbtc8723b2ant_display_coex_info(btcoexist) - -#endif - -#endif diff --git a/hal/btc/HalBtc8812a1Ant.c b/hal/btc/HalBtc8812a1Ant.c deleted file mode 100644 index e094caa..0000000 --- a/hal/btc/HalBtc8812a1Ant.c +++ /dev/null @@ -1,3457 +0,0 @@ -/* ************************************************************ - * Description: - * - * This file is for RTL8812A Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "Mp_Precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8812A_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8812a_1ant glcoex_dm_8812a_1ant; -static struct coex_dm_8812a_1ant *coex_dm = &glcoex_dm_8812a_1ant; -static struct coex_sta_8812a_1ant glcoex_sta_8812a_1ant; -static struct coex_sta_8812a_1ant *coex_sta = &glcoex_sta_8812a_1ant; - -const char *const glbt_info_src_8812a_1ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8812a_1ant = 20140708; -u32 glcoex_ver_8812a_1ant = 0x52; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8812a1ant_ - * ************************************************************ */ -u8 halbtc8812a1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8812a1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8812a1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -/* to check 0x430/0x434 is correct?? */ -void halbtc8812a1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -/* to check 0x42a ?? */ -void halbtc8812a1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -/* to check 0x456?? */ -void halbtc8812a1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8812a1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8812a1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8812a1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8812a1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8812a1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8812a1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8812a1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8812a1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8812a1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 data_len = 3; - u8 buf[5] = {0}; - - if (!coex_sta->bt_disabled) { - if (!coex_sta->bt_info_query_cnt || - (coex_sta->bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_BT_RSP] - - coex_sta->bt_info_query_cnt) > 2) { - buf[0] = data_len; - buf[1] = 0x1; /* polling enable, 1=enable, 0=disable */ - buf[2] = 0x2; /* polling time in seconds */ - buf[3] = 0x1; /* auto report enable, 1=enable, 0=disable */ - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_INFO, - (void *)&buf[0]); - } - } - coex_sta->bt_info_query_cnt++; -} - -void halbtc8812a1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if ((coex_sta->low_priority_tx > 1150) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", - reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) && - (reg_lp_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8812a1ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; - } - } -} - -/* to check registers */ -void halbtc8812a1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false; - static u8 cck_lock_counter = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - if (coex_sta->under_ips) { - coex_sta->crc_ok_cck = 0; - coex_sta->crc_ok_11g = 0; - coex_sta->crc_ok_11n = 0; - coex_sta->crc_ok_11n_agg = 0; - - coex_sta->crc_err_cck = 0; - coex_sta->crc_err_11g = 0; - coex_sta->crc_err_11n = 0; - coex_sta->crc_err_11n_agg = 0; - } else { - coex_sta->crc_ok_cck = btcoexist->btc_read_2byte(btcoexist, - 0xf04); - coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf14); - coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf10); - coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xf40); - - coex_sta->crc_err_cck = btcoexist->btc_read_2byte(btcoexist, - 0xf06); - coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf16); - coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf12); - coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xf42); - } - - - /* reset counter */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x0); - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - if ((coex_dm->bt_status == BT_8812A_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == - BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == - BT_8812A_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + - coex_sta->crc_ok_11n_agg)) { - if (cck_lock_counter < 5) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 5) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - coex_sta->pre_ccklock = coex_sta->cck_lock; - - -} - -boolean halbtc8812a1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - } - - return false; -} - -void halbtc8812a1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8812a1ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8812A_1ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8812a1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8812a1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8812a1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -/* to check */ -void halbtc8812a1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 tmp_u1; - - tmp_u1 = btcoexist->btc_read_1byte(btcoexist, 0x4fd); - tmp_u1 |= BIT(0); - if (low_penalty_ra) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Tx rate adaptive, set low penalty!!\n"); - BTC_TRACE(trace_buf); - tmp_u1 &= ~BIT(2); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Tx rate adaptive, set normal!!\n"); - BTC_TRACE(trace_buf); - tmp_u1 |= BIT(2); - } - - btcoexist->btc_write_1byte(btcoexist, 0x4fd, tmp_u1); -} - -void halbtc8812a1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8812a1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8812a1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8812a1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8812a1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8812a1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** CoexTable(%d) **********\n", type); - BTC_TRACE(trace_buf); - - coex_sta->coex_table_type = type; - - switch (type) { - case 0: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, 0xffffff, 0x3); - break; - case 1: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 2: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 3: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 4: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); - break; - case 5: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaa5a5a5a, 0xffffff, 0x3); - break; - case 6: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 7: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8812a1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 data_len = 3; - u8 buf[5] = {0}; - - buf[0] = data_len; - buf[1] = 0x1; /* OP_Code */ - buf[2] = 0x1; /* OP_Code_Length */ - if (enable) - buf[3] = 0x1; /* OP_Code_Content */ - else - buf[3] = 0x0; - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); -} - -void halbtc8812a1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8812a1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8812a1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8812a1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8812a1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8812a1ant_sw_mechanism(IN struct btc_coexist *btcoexist, - IN boolean low_penalty_ra) -{ - halbtc8812a1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -/* to check force_exec */ -void halbtc8812a1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg, - IN boolean wifi_off) -{ - u8 u8tmp = 0; - - coex_dm->cur_ant_pos_type = ant_pos_type; - - if (init_hwcfg) { - btcoexist->btc_write_1byte(btcoexist, 0xcb3, 0x77); - btcoexist->btc_write_4byte(btcoexist, 0x900, 0x00000400); - btcoexist->btc_write_1byte(btcoexist, 0x76d, 0x1); - } else if (wifi_off) { - btcoexist->btc_write_1byte(btcoexist, 0xcb3, 0x77); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7); - u8tmp &= ~BIT(3); - u8tmp |= BIT(2); - btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp); - } - - if (force_exec || - (coex_dm->cur_ant_pos_type != coex_dm->pre_ant_pos_type)) { - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - u8tmp = btcoexist->btc_read_1byte(btcoexist, - 0xcb7); - u8tmp |= BIT(3); - u8tmp &= ~BIT(2); - btcoexist->btc_write_1byte(btcoexist, 0xcb7, - u8tmp); - break; - case BTC_ANT_PATH_BT: - u8tmp = btcoexist->btc_read_1byte(btcoexist, - 0xcb7); - u8tmp &= ~BIT(3); - u8tmp |= BIT(2); - btcoexist->btc_write_1byte(btcoexist, 0xcb7, - u8tmp); - break; - default: - case BTC_ANT_PATH_PTA: - u8tmp = btcoexist->btc_read_1byte(btcoexist, - 0xcb7); - u8tmp |= BIT(3); - u8tmp &= ~BIT(2); - btcoexist->btc_write_1byte(btcoexist, 0xcb7, - u8tmp); - break; - } - } - - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; -} - -void halbtc8812a1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - } - } - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - - -void halbtc8812a1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - u8 rssi_adjust_val = 0; - u8 ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51, - ps_tdma_byte3_val = 0x10; - s8 wifi_duration_adjust = 0x0; - static boolean pre_wifi_busy = false; - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (wifi_busy != pre_wifi_busy) { - force_exec = true; - pre_wifi_busy = wifi_busy; - } - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_sta->scan_ap_num <= 5) - wifi_duration_adjust = 2; - else if (coex_sta->scan_ap_num >= 40) - wifi_duration_adjust = -15; - else if (coex_sta->scan_ap_num >= 20) - wifi_duration_adjust = -10; - - if (!coex_sta->force_lps_on) { /* only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */ - ps_tdma_byte0_val = 0x61; /* no null-pkt */ - ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */ - ps_tdma_byte4_val = 0x10; /* 0x778 = d/1 toggle */ - } - - if ((type == 3) || (type == 13) || (type == 14)) { - ps_tdma_byte4_val = ps_tdma_byte4_val & - 0xbf; /* no dynamic slot for multi-profile */ - - if (!wifi_busy) - ps_tdma_byte4_val = ps_tdma_byte4_val | - 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - } - - if (bt_link_info->slave_role == true) - ps_tdma_byte4_val = ps_tdma_byte4_val | - 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - - if (turn_on) { - switch (type) { - default: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1a, 0x1a, 0x0, ps_tdma_byte4_val); - break; - case 1: - halbtc8812a1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3a + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 2: - halbtc8812a1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x2d + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 3: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1d, 0x1d, 0x0, ps_tdma_byte4_val); - break; - case 4: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x14, 0x0); - break; - case 5: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x15, 0x3, 0x11, 0x11); - break; - case 6: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x3, 0x11, 0x11); - break; - case 7: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13, - 0xc, 0x5, 0x0, 0x0); - break; - case 8: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 9: - halbtc8812a1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 10: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0xa, 0x0, 0x40); - break; - case 11: - halbtc8812a1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 12: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x0a, 0x0a, 0x0, 0x50); - break; - case 13: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x12, 0x12, 0x0, ps_tdma_byte4_val); - break; - case 14: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x21, 0x3, 0x10, ps_tdma_byte4_val); - break; - case 15: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0x3, 0x8, 0x0); - break; - case 16: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x10, 0x0); - break; - case 18: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 20: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x3f, 0x03, 0x11, 0x10); - break; - case 21: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x11); - break; - case 22: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x10); - break; - case 23: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x18); - break; - case 24: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x3, 0x31, 0x18); - break; - case 25: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - break; - case 26: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - break; - case 27: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x98); - break; - case 28: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x69, - 0x25, 0x3, 0x31, 0x0); - break; - case 29: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xab, - 0x1a, 0x1a, 0x1, 0x10); - break; - case 30: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, 0x10); - break; - case 31: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1a, 0x1a, 0, 0x58); - break; - case 32: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x3, 0x11, 0x11); - break; - case 33: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xa3, - 0x25, 0x3, 0x30, 0x90); - break; - case 34: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x53, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 35: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x63, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 36: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x12, 0x3, 0x14, 0x50); - break; - case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */ - /* here softap mode screen off will cost 70-80mA for phone */ - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x23, - 0x18, 0x00, 0x10, 0x24); - break; - } - } else { - - /* disable PS tdma */ - switch (type) { - case 8: /* PTA Control */ - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - break; - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - break; - } - } - rssi_adjust_val = 0; - btcoexist->btc_set(btcoexist, - BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val); - - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -boolean halbtc8812a1ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (wifi_connected && - (BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (!wifi_connected && - (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (wifi_connected && - (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (!wifi_connected && - (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } - - common = false; - } - - return common; -} - - -void halbtc8812a1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0, bt_info_ext; - boolean wifi_busy = false; - - if (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status) - wifi_busy = true; - else - wifi_busy = false; - - if ((BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == - wifi_status) || - (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) || - (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT == - wifi_status)) { - if (coex_dm->cur_ps_tdma != 1 && - coex_dm->cur_ps_tdma != 2 && - coex_dm->cur_ps_tdma != 3 && - coex_dm->cur_ps_tdma != 9) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - coex_dm->ps_tdma_du_adj_type = 9; - - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } - return; - } - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* accquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - bt_info_ext = coex_sta->bt_info_ext; - - if ((coex_sta->low_priority_tx) > 1150 || - (coex_sta->low_priority_rx) > 1250) - retry_count++; - - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ - if (wait_count <= 2) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ - if (wait_count == 1) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (result == -1) { - if ((BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 1) || - (coex_dm->cur_ps_tdma == 2))) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } - } else if (result == 1) { - if ((BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 1) || - (coex_dm->cur_ps_tdma == 2))) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = 1; - } - } else { /* no change */ - /* Bryant Modify - if(wifi_busy != pre_wifi_busy) - { - pre_wifi_busy = wifi_busy; - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma); - } - */ - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - if (coex_dm->cur_ps_tdma != 1 && - coex_dm->cur_ps_tdma != 2 && - coex_dm->cur_ps_tdma != 9 && - coex_dm->cur_ps_tdma != 11) { - /* recover to previous adjust type */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - } - } -} - -void halbtc8812a1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8812a1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8812a1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8812a1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8812a1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - -void halbtc8812a1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, - false, false); -} - -void halbtc8812a1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - BTC_TRACE(trace_buf); - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 2) { - bt_disabled = true; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - BTC_TRACE(trace_buf); - halbtc8812a1ant_action_wifi_only(btcoexist); - } - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - if (!bt_disabled) { - } else { - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - } - } -} - -/* ********************************************* - * - * Software Coex Mechanism start - * - * ********************************************* */ - -/* SCO only or SCO+PAN(HS) */ - -/* -void halbtc8812a1ant_action_sco(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8812a1ant_action_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8812a1ant_action_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8812a1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8812a1ant_action_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8812a1ant_action_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8812a1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8812a1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8812a1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, true); -} - -void halbtc8812a1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, true); -} - -*/ - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8812a1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8812a1ant_action_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8812a1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, ap_enable = false, wifi_busy = false, - bt_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) { - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - /* SCO/HID/A2DP busy */ - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if ((bt_link_info->pan_exist) || (wifi_busy)) { - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } -} - -void halbtc8812a1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* tdma and coex table */ - - if (bt_link_info->sco_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else { /* HID */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } -} - -void halbtc8812a1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - u8 bt_rssi_state; - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - bt_rssi_state = halbtc8812a1ant_bt_rssi_state(2, 28, 0); - - if ((coex_sta->low_priority_rx >= 950) && (!coex_sta->under_ips)) - bt_link_info->slave_role = true; - else - bt_link_info->slave_role = false; - - if (bt_link_info->hid_only) { /* HID */ - halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, - wifi_status); - coex_dm->auto_tdma_adjust = false; - return; - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - halbtc8812a1ant_tdma_duration_adjust_for_acl(btcoexist, - wifi_status); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = true; - } - } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - coex_dm->auto_tdma_adjust = false; - - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && - bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - /* BT no-profile busy (0x9) */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } -} - -void halbtc8812a1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - /* power save state */ - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8812a1ant_action_wifi_not_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* Bryant Add */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8812a1ant_action_wifi_not_connected_asso_auth( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2); - } -} - -void halbtc8812a1ant_action_wifi_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* Bryant Add */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8812a1ant_action_wifi_connected_specific_packet( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8812a1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - boolean scan = false, link = false, roam = false; - boolean under_4way = false, ap_enable = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (under_4way) { - halbtc8812a1ant_action_wifi_connected_specific_packet(btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - if (scan) - halbtc8812a1ant_action_wifi_connected_scan(btcoexist); - else - halbtc8812a1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* power save state */ - if (!ap_enable && - BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status && - !btcoexist->bt_link_info.hid_only) { - if (btcoexist->bt_link_info.a2dp_only) { /* A2DP */ - if (!wifi_busy) - halbtc8812a1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - else { /* busy */ - if (coex_sta->scan_ap_num >= - BT_8812A_1ANT_WIFI_NOISY_THRESH) /* no force LPS, no PS-TDMA, use pure TDMA */ - halbtc8812a1ant_power_save_state( - btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8812a1ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - } else if ((coex_sta->pan_exist == false) && - (coex_sta->a2dp_exist == false) && - (coex_sta->hid_exist == false)) - halbtc8812a1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - else - halbtc8812a1ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - } else - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - /* tdma and coex table */ - if (!wifi_busy) { - if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8812a1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8812a1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - else - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } else { - if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8812a1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8812a1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - else - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } -} - -void halbtc8812a1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - - algorithm = halbtc8812a1ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - - if (halbtc8812a1ant_is_common_action(btcoexist)) { - - } else { - switch (coex_dm->cur_algorithm) { - case BT_8812A_1ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_sco(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_hid(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_a2dp(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_a2dp_pan_hs(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_pan_edr(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_pan_hs(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_pan_edr_a2dp(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_pan_edr_hid(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_hid_a2dp_pan_edr(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_hid_a2dp(btcoexist); */ - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_coex_all_off(btcoexist); */ - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8812a1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - boolean miracast_plus_bt = false; - u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0, wifi_bw; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if ((BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, - 0, 1); - miracast_plus_bt = true; - } else { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, - 0, 0); - miracast_plus_bt = false; - } - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if ((bt_link_info->a2dp_exist) && - (coex_sta->c2h_bt_inquiry_page)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8812a1ant_action_bt_inquiry(btcoexist); - } else - halbtc8812a1ant_action_wifi_multi_port(btcoexist); - - return; - } else { - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); - - if (bt_link_info->sco_exist) - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, true, - false, 0x5); - else { - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, - false, true, 0x10); - else - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, - false, true, 0x8); - } - - halbtc8812a1ant_sw_mechanism(btcoexist, true); - halbtc8812a1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - } else { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x5); - - halbtc8812a1ant_sw_mechanism(btcoexist, false); - halbtc8812a1ant_run_sw_coexist_mechanism( - btcoexist); /* //just print debug message */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8812a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8812a1ant_action_hs(btcoexist); - return; - } - - - if (!wifi_connected) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is non connected-idle !!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - if (scan) - halbtc8812a1ant_action_wifi_not_connected_scan( - btcoexist); - else - halbtc8812a1ant_action_wifi_not_connected_asso_auth( - btcoexist); - } else - halbtc8812a1ant_action_wifi_not_connected(btcoexist); - } else /* wifi LPS/Busy */ - halbtc8812a1ant_action_wifi_connected(btcoexist); -} - -void halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - - /* sw all off */ - halbtc8812a1ant_sw_mechanism(btcoexist, false); - - /* halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ - /* halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */ - - coex_sta->pop_event_cnt = 0; -} - -void halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up, IN boolean wifi_only) -{ - u8 u8tmp = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - /* ant sw control to BT */ - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, - true, false); - - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* PTA parameter */ - btcoexist->btc_write_1byte(btcoexist, 0x6cc, 0x0); - btcoexist->btc_write_4byte(btcoexist, 0x6c8, 0xffff); - btcoexist->btc_write_4byte(btcoexist, 0x6c4, 0x55555555); - btcoexist->btc_write_4byte(btcoexist, 0x6c0, 0x55555555); - - /* coex parameters */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - - /* enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* enable PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); - - /* bt clock related */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x4); - u8tmp |= BIT(7); - btcoexist->btc_write_1byte(btcoexist, 0x4, u8tmp); - - /* bt clock related */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); - u8tmp |= BIT(1); - btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); -} - -/* ************************************************************ - * work around function start with wa_halbtc8812a1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8812a1ant_ - * ************************************************************ */ -void ex_halbtc8812a1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8812a1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8812a1ant_init_hw_config(btcoexist, true, wifi_only); - btcoexist->stop_coex_dm = false; -} - -void ex_halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - - halbtc8812a1ant_init_coex_dm(btcoexist); - - halbtc8812a1ant_query_bt_info(btcoexist); -} - -void ex_halbtc8812a1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u32 u32tmp[4]; - u32 fw_ver = 0, bt_patch_ver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", - "CoexVer/ FwVer/ PatchVer", - glcoex_ver_date_8812a_1ant, glcoex_ver_8812a_1ant, fw_ver, - bt_patch_ver, bt_patch_ver); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", - "SCO/HID/PAN/A2DP", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8812A_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8812a_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - if (!btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", - "Latest error condition(should be 0)", - coex_dm->error_condition); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", - "IgnWlanAct", - coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - } - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", - u8tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcb3); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb7); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x900); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0xcb3/0xcb7/0x900", - u8tmp[0], u8tmp[1], u32tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", - u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", - u32tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(hp rx[31:16]/tx[15:0])", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(lp rx[31:16]/tx[15:0])", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); - - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - - -void ex_halbtc8812a1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - - halbtc8812a1ant_init_hw_config(btcoexist, false, false); - halbtc8812a1ant_init_coex_dm(btcoexist); - halbtc8812a1ant_query_bt_info(btcoexist); - - coex_sta->under_ips = false; - } -} - -void ex_halbtc8812a1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8812a1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_SCAN_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - } - - if (coex_sta->bt_disabled) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - halbtc8812a1ant_query_bt_info(btcoexist); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8812a1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8812a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8812a1ant_action_hs(btcoexist); - return; - } - - if (BTC_SCAN_START == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8812a1ant_action_wifi_not_connected_scan( - btcoexist); - else /* wifi is connected */ - halbtc8812a1ant_action_wifi_connected_scan(btcoexist); - } else if (BTC_SCAN_FINISH == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8812a1ant_action_wifi_not_connected(btcoexist); - else - halbtc8812a1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8812a1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_ASSOCIATE_START == type) { - coex_sta->wifi_is_high_pri_task = true; - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - /* coex_dm->arp_cnt = 0; */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8812a1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8812a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8812a1ant_action_hs(btcoexist); - return; - } - - if (BTC_ASSOCIATE_START == type) - halbtc8812a1ant_action_wifi_not_connected_asso_auth(btcoexist); - else if (BTC_ASSOCIATE_FINISH == type) { - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (!wifi_connected) /* non-connected scan */ - halbtc8812a1ant_action_wifi_not_connected(btcoexist); - else - halbtc8812a1ant_action_wifi_connected(btcoexist); - } -} - -/* to check registers... */ -void ex_halbtc8812a1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 data_len = 5; - u8 buf[6] = {0}; - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - boolean wifi_under_b_mode = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); -#if 0 - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x10); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } -#endif - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - /* h2c_parameter[0] = 0x1; */ - h2c_parameter[0] = 0x0; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - buf[0] = data_len; - buf[1] = 0x5; /* OP_Code */ - buf[2] = 0x3; /* OP_Code_Length */ - buf[3] = h2c_parameter[0]; /* OP_Code_Content */ - buf[4] = h2c_parameter[1]; - buf[5] = h2c_parameter[2]; - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); -} - -void ex_halbtc8812a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - BTC_PACKET_ARP == type) { - if (BTC_PACKET_ARP == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify\n"); - BTC_TRACE(trace_buf); - - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ARP Packet Count = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - - if (coex_dm->arp_cnt >= - 10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */ - coex_sta->wifi_is_high_pri_task = false; - else - coex_sta->wifi_is_high_pri_task = true; - } else { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify\n"); - BTC_TRACE(trace_buf); - } - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet [Type = %d] notify\n", type); - BTC_TRACE(trace_buf); - } - - coex_sta->specific_pkt_period_cnt = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8812a1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8812a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8812a1ant_action_hs(btcoexist); - return; - } - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task))) - halbtc8812a1ant_action_wifi_connected_specific_packet(btcoexist); -} - -void ex_halbtc8812a1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean bt_busy = false; - - coex_sta->c2h_bt_info_req_sent = false; - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8812A_1ANT_MAX) - rsp_source = BT_INFO_SRC_8812A_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (BT_INFO_SRC_8812A_1ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_page = true; - else - coex_sta->c2h_bt_page = false; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; - /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */ - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] - & 0x40); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, - &coex_sta->bt_tx_rx_mask); - if (!coex_sta->bt_tx_rx_mask) { - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x3c, 0x15); - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if (coex_sta->bt_info_ext & BIT(1)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8812a1ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8812a1ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if (coex_sta->bt_info_ext & BIT(3)) { - if (!btcoexist->manual_control && - !btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - } -#if (BT_AUTO_REPORT_ONLY_8812A_1ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8812a1ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8812A_1ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8812A_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8812A_1ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8812A_1ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8812A_1ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8812A_1ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - } - - halbtc8812a1ant_update_bt_link_info(btcoexist); - - bt_info = bt_info & - 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ - - if (!(bt_info & BT_INFO_8812A_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8812A_1ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8812A_1ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8812A_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8812A_1ANT_B_ACL_BUSY) { - if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) - coex_dm->auto_tdma_adjust = false; - coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - halbtc8812a1ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8812a1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - } else if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - - halbtc8812a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - btcoexist->stop_coex_dm = true; - } -} - -void ex_halbtc8812a1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, - false, true); - - halbtc8812a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8812a1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8812a1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - halbtc8812a1ant_init_hw_config(btcoexist, false, false); - halbtc8812a1ant_init_coex_dm(btcoexist); - halbtc8812a1ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8812a1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], *****************Coex DM Reset*****************\n"); - BTC_TRACE(trace_buf); - - halbtc8812a1ant_init_hw_config(btcoexist, false, false); - halbtc8812a1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8812a1ant_periodical(IN struct btc_coexist *btcoexist) -{ -#if (BT_AUTO_REPORT_ONLY_8812A_1ANT == 0) - halbtc8812a1ant_query_bt_info(btcoexist); - halbtc8812a1ant_monitor_bt_enable_disable(btcoexist); -#else - halbtc8812a1ant_monitor_bt_ctr(btcoexist); - halbtc8812a1ant_monitor_wifi_ctr(btcoexist); - - if (halbtc8812a1ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust) - halbtc8812a1ant_run_coexist_mechanism(btcoexist); - - coex_sta->specific_pkt_period_cnt++; -#endif -} - -void ex_halbtc8812a1ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata) -{ - switch (op_code) { - case BTC_DBG_SET_COEX_NORMAL: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set CoexMode to Normal\n"); - BTC_TRACE(trace_buf); - btcoexist->manual_control = false; - halbtc8812a1ant_init_coex_dm(btcoexist); - break; - case BTC_DBG_SET_COEX_WIFI_ONLY: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set CoexMode to Wifi Only\n"); - BTC_TRACE(trace_buf); - btcoexist->manual_control = true; - halbtc8812a1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 9); - break; - case BTC_DBG_SET_COEX_BT_ONLY: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set CoexMode to BT only\n"); - BTC_TRACE(trace_buf); - btcoexist->manual_control = true; - halbtc8812a1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - break; - case BTC_DBG_SET_COEX_DEC_BT_PWR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set Dec BT power\n"); - BTC_TRACE(trace_buf); - { - u8 data_len = 4; - u8 buf[6] = {0}; - u8 dec_bt_pwr = 0, pwr_level = 0; - if (op_len == 2) { - dec_bt_pwr = pdata[0]; - pwr_level = pdata[1]; - - buf[0] = data_len; - buf[1] = 0x3; /* OP_Code */ - buf[2] = 0x2; /* OP_Code_Length */ - - buf[3] = dec_bt_pwr; /* OP_Code_Content */ - buf[4] = pwr_level; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set Dec BT power=%d, pwr_level=%d\n", - dec_bt_pwr, pwr_level); - BTC_TRACE(trace_buf); - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); - } - } - break; - - case BTC_DBG_SET_COEX_BT_AFH_MAP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT AFH Map\n"); - BTC_TRACE(trace_buf); - { - u8 data_len = 5; - u8 buf[6] = {0}; - if (op_len == 3) { - buf[0] = data_len; - buf[1] = 0x5; /* OP_Code */ - buf[2] = 0x3; /* OP_Code_Length */ - - buf[3] = pdata[0]; /* OP_Code_Content */ - buf[4] = pdata[1]; - buf[5] = pdata[2]; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT AFH Map = %02x %02x %02x\n", - pdata[0], pdata[1], pdata[2]); - BTC_TRACE(trace_buf); - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); - } - } - break; - - case BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT Ignore Wlan Active\n"); - BTC_TRACE(trace_buf); - { - u8 data_len = 3; - u8 buf[6] = {0}; - if (op_len == 1) { - buf[0] = data_len; - buf[1] = 0x1; /* OP_Code */ - buf[2] = 0x1; /* OP_Code_Length */ - - buf[3] = pdata[0]; /* OP_Code_Content */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT Ignore Wlan Active = 0x%x\n", - pdata[0]); - BTC_TRACE(trace_buf); - - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); - } - } - break; - default: - break; - } -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ \ No newline at end of file diff --git a/hal/btc/HalBtc8812a1Ant.h b/hal/btc/HalBtc8812a1Ant.h deleted file mode 100644 index e786d37..0000000 --- a/hal/btc/HalBtc8812a1Ant.h +++ /dev/null @@ -1,230 +0,0 @@ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8812A_SUPPORT == 1) - -/* ******************************************* - * The following is for 8812A 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8812A_1ANT 1 - -#define BT_INFO_8812A_1ANT_B_FTP BIT(7) -#define BT_INFO_8812A_1ANT_B_A2DP BIT(6) -#define BT_INFO_8812A_1ANT_B_HID BIT(5) -#define BT_INFO_8812A_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8812A_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8812A_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8812A_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8812A_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT 2 - -#define BT_8812A_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ - -enum bt_info_src_8812a_1ant { - BT_INFO_SRC_8812A_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8812A_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8812A_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8812A_1ANT_MAX -}; - -enum bt_8812a_1ant_bt_status { - BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8812A_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8812A_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8812A_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8812A_1ANT_BT_STATUS_MAX -}; - -enum bt_8812a_1ant_wifi_status { - BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8812A_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8812a_1ant_coex_algo { - BT_8812A_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8812A_1ANT_COEX_ALGO_SCO = 0x1, - BT_8812A_1ANT_COEX_ALGO_HID = 0x2, - BT_8812A_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8812A_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8812A_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8812A_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8812A_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8812A_1ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8812a_1ant { - /* hw setting */ - u8 pre_ant_pos_type; - u8 cur_ant_pos_type; - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u8 error_condition; -}; - -struct coex_sta_8812a_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - s8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8812A_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_MAX]; - u32 bt_info_query_cnt; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - u8 bt_retry_cnt; - u8 bt_info_ext; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_agg; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_agg; - - boolean cck_lock; - boolean pre_ccklock; - u8 coex_table_type; - - boolean force_lps_on; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8812a1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8812a1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8812a1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a1ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata); -void ex_halbtc8812a1ant_display_coex_info(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8812a1ant_power_on_setting(btcoexist) -#define ex_halbtc8812a1ant_pre_load_firmware(btcoexist) -#define ex_halbtc8812a1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8812a1ant_init_coex_dm(btcoexist) -#define ex_halbtc8812a1ant_ips_notify(btcoexist, type) -#define ex_halbtc8812a1ant_lps_notify(btcoexist, type) -#define ex_halbtc8812a1ant_scan_notify(btcoexist, type) -#define ex_halbtc8812a1ant_connect_notify(btcoexist, type) -#define ex_halbtc8812a1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8812a1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8812a1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8812a1ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8812a1ant_halt_notify(btcoexist) -#define ex_halbtc8812a1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8812a1ant_coex_dm_reset(btcoexist) -#define ex_halbtc8812a1ant_periodical(btcoexist) -#define ex_halbtc8812a1ant_dbg_control(btcoexist, op_code, op_len, pdata) -#define ex_halbtc8812a1ant_display_coex_info(btcoexist) - -#endif - -#endif diff --git a/hal/btc/HalBtc8812a2Ant.c b/hal/btc/HalBtc8812a2Ant.c deleted file mode 100644 index cd8a547..0000000 --- a/hal/btc/HalBtc8812a2Ant.c +++ /dev/null @@ -1,4782 +0,0 @@ -/* ************************************************************ - * Description: - * - * This file is for RTL8812A Co-exist mechanism - * - * History - * 2012/08/22 Cosa first check in. - * 2012/11/14 Cosa Revise for 8812A 2Ant out sourcing. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "Mp_Precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8812A_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8812a_2ant glcoex_dm_8812a_2ant; -static struct coex_dm_8812a_2ant *coex_dm = &glcoex_dm_8812a_2ant; -static struct coex_sta_8812a_2ant glcoex_sta_8812a_2ant; -static struct coex_sta_8812a_2ant *coex_sta = &glcoex_sta_8812a_2ant; - -const char *const glbt_info_src_8812a_2ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8812a_2ant = 20150724; -u32 glcoex_ver_8812a_2ant = 0x37; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8812a2ant_ - * ************************************************************ */ -u8 halbtc8812a2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8812a2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8812a2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - struct btc_stack_info *stack_info = &btcoexist->stack_info; - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - /* only 8812a need to consider if core stack is installed. */ - if (!stack_info->hci_version) - bt_active = false; - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - BTC_TRACE(trace_buf); - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt is detected as disabled %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 2) { - bt_disabled = true; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - BTC_TRACE(trace_buf); - } - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - if (!bt_disabled) { - } else { - } - } -} - -u32 halbtc8812a2ant_decide_ra_mask(IN struct btc_coexist *btcoexist, - IN u32 ra_mask_type) -{ - u32 dis_ra_mask = 0x0; - - switch (ra_mask_type) { - case 0: /* normal mode */ - dis_ra_mask = 0x0; - break; - case 1: /* disable cck 1/2 */ - dis_ra_mask = 0x00000003; - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - dis_ra_mask = 0x0001f1f7; - break; - default: - break; - } - - return dis_ra_mask; -} - -void halbtc8812a2ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8812a2ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8812a2ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8812a2ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8812a2ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - u32 dis_ra_mask = 0x0; - - coex_dm->cur_ra_mask_type = ra_mask_type; - dis_ra_mask = halbtc8812a2ant_decide_ra_mask(btcoexist, ra_mask_type); - halbtc8812a2ant_update_ra_mask(btcoexist, force_exec, dis_ra_mask); - - halbtc8812a2ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8812a2ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8812a2ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8812a2ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8812a2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); -} - -void halbtc8812a2ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 data_len = 3; - u8 buf[5] = {0}; - - if (!coex_sta->bt_disabled) { - if (!coex_sta->bt_info_query_cnt || - (coex_sta->bt_info_c2h_cnt[BT_INFO_SRC_8812A_2ANT_BT_RSP] - - coex_sta->bt_info_query_cnt) > 2) { - buf[0] = data_len; - buf[1] = 0x1; /* polling enable, 1=enable, 0=disable */ - buf[2] = 0x2; /* polling time in seconds */ - buf[3] = 0x1; /* auto report enable, 1=enable, 0=disable */ - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_INFO, - (void *)&buf[0]); - } - } - coex_sta->bt_info_query_cnt++; -} - -boolean halbtc8812a2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - } - - return false; -} - -void halbtc8812a2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->acl_busy = coex_sta->acl_busy; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8812a2ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8812A_2ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 0) { - if (bt_link_info->acl_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ACL Busy only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR; - } - } else if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_SCO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - if (stack_info->num_of_hid >= 2) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID*2 + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_HID_A2DP; - } - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_SCO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_SCO_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8812a2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - -void halbtc8812a2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN u8 dec_bt_pwr_lvl) -{ - u8 data_len = 4; - u8 buf[6] = {0}; - - buf[0] = data_len; - buf[1] = 0x3; /* OP_Code */ - buf[2] = 0x2; /* OP_Code_Length */ - if (dec_bt_pwr_lvl) - buf[3] = 0x1; /* OP_Code_Content */ - else - buf[3] = 0x0; - buf[4] = dec_bt_pwr_lvl;/* pwr_level */ - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); -} - -void halbtc8812a2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 dec_bt_pwr_lvl) -{ - coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; - - if (!force_exec) { - if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) - return; - } - halbtc8812a2ant_set_fw_dec_bt_pwr(btcoexist, - coex_dm->cur_bt_dec_pwr_lvl); - - coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; -} - -void halbtc8812a2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8812a2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - -void halbtc8812a2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist, - IN boolean rx_rf_shrink_on) -{ - if (rx_rf_shrink_on) { - /* Shrink RF Rx LPF corner */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Shrink RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, - 0xffffc); - } else { - /* Resume RF Rx LPF corner */ - /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ - if (btcoexist->initilized) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Resume RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, coex_dm->bt_rf_0x1e_backup); - } - } -} - -void halbtc8812a2ant_rf_shrink(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rx_rf_shrink_on) -{ - coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; - - if (!force_exec) { - if (coex_dm->pre_rf_rx_lpf_shrink == - coex_dm->cur_rf_rx_lpf_shrink) - return; - } - halbtc8812a2ant_set_sw_rf_rx_lpf_corner(btcoexist, - coex_dm->cur_rf_rx_lpf_shrink); - - coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; -} - -void halbtc8812a2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 tmp_u1; - - tmp_u1 = btcoexist->btc_read_1byte(btcoexist, 0x4fd); - tmp_u1 |= BIT(0); - if (low_penalty_ra) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Tx rate adaptive, set low penalty!!\n"); - BTC_TRACE(trace_buf); - tmp_u1 &= ~BIT(2); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Tx rate adaptive, set normal!!\n"); - BTC_TRACE(trace_buf); - tmp_u1 |= BIT(2); - } - - btcoexist->btc_write_1byte(btcoexist, 0x4fd, tmp_u1); -} - -void halbtc8812a2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - return; - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8812a2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8812a2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, - IN u32 level) -{ - u8 val = (u8)level; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Write SwDacSwing = 0x%x\n", level); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val); -} - -void halbtc8812a2ant_set_sw_full_time_dac_swing(IN struct btc_coexist - *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) -{ - if (sw_dac_swing_on) - halbtc8812a2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl); - else - halbtc8812a2ant_set_dac_swing_reg(btcoexist, 0x18); -} - - -void halbtc8812a2ant_dac_swing(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) -{ - coex_dm->cur_dac_swing_on = dac_swing_on; - coex_dm->cur_dac_swing_lvl = dac_swing_lvl; - - if (!force_exec) { - if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && - (coex_dm->pre_dac_swing_lvl == - coex_dm->cur_dac_swing_lvl)) - return; - } - delay_ms(30); - halbtc8812a2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, - dac_swing_lvl); - - coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; - coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; -} - -void halbtc8812a2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean adc_back_off) -{ - if (adc_back_off) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1); - } -} - -void halbtc8812a2ant_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean adc_back_off) -{ - coex_dm->cur_adc_back_off = adc_back_off; - - if (!force_exec) { - if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) - return; - } - halbtc8812a2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off); - - coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; -} - -void halbtc8812a2ant_set_agc_table(IN struct btc_coexist *btcoexist, - IN boolean agc_table_en) -{ - u8 rssi_adjust_val = 0; - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x28F4B); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x10AB2); - rssi_adjust_val = 8; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x2884B); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x104B2); - } - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); - - /* set rssi_adjust_val for wifi module. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, - &rssi_adjust_val); -} - -void halbtc8812a2ant_agc_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean agc_table_en) -{ - coex_dm->cur_agc_table_en = agc_table_en; - - if (!force_exec) { - if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) - return; - } - halbtc8812a2ant_set_agc_table(btcoexist, agc_table_en); - - coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; -} - -void halbtc8812a2ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8812a2ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8812a2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8812a2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - switch (type) { - case 0: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 1: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 2: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5ffb5ffb, 0xffffff, 0x3); - break; - case 3: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3); - break; - case 4: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0xdfffdfff, 0x5fdb5fdb, 0xffffff, 0x3); - break; - case 5: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0x5ddd5ddd, 0x5fdb5fdb, 0xffffff, 0x3); - break; - - default: - break; - } -} - -void halbtc8812a2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 data_len = 3; - u8 buf[5] = {0}; - - buf[0] = data_len; - buf[1] = 0x1; /* OP_Code */ - buf[2] = 0x1; /* OP_Code_Length */ - if (enable) - buf[3] = 0x1; /* OP_Code_Content */ - else - buf[3] = 0x0; - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); -} - -void halbtc8812a2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8812a2ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8812a2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - } - } - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8812a2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8812a2ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8812a2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8812a2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, - IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, - IN boolean limited_dig, IN boolean bt_lna_constrain) -{ - /* - u32 wifi_bw; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if(BTC_WIFI_BW_HT40 != wifi_bw) - { - if (shrink_rx_lpf) - shrink_rx_lpf = false; - } - */ - - halbtc8812a2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); - /* halbtc8812a2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); */ -} - -void halbtc8812a2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, - IN boolean agc_table_shift, IN boolean adc_back_off, - IN boolean sw_dac_swing, IN u32 dac_swing_lvl) -{ - /* halbtc8812a2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */ - halbtc8812a2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); - halbtc8812a2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, - dac_swing_lvl); -} - -void halbtc8812a2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - u8 u8tmp = 0; - - if (init_hwcfg) { - btcoexist->btc_write_4byte(btcoexist, 0x900, 0x00000400); - btcoexist->btc_write_1byte(btcoexist, 0x76d, 0x1); - } else if (wifi_off) { - - } - - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_WIFI_AT_CPL_MAIN: - break; - case BTC_ANT_WIFI_AT_CPL_AUX: - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7); - u8tmp &= ~BIT(3); - u8tmp |= BIT(2); - btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp); - break; - default: - break; - } -} - -void halbtc8812a2ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - if (turn_on) { - switch (type) { - case 1: - default: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1a, 0x1a, 0xa1, 0x90); - break; - case 2: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x12, 0x12, 0xa1, 0x90); - break; - case 3: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xb1, 0x90); - break; - case 4: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0xb1, 0x90); - break; - case 5: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1a, 0x1a, 0x21, 0x10); - break; - case 6: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x12, 0x12, 0x21, 0x10); - break; - case 7: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0x21, 0x10); - break; - case 8: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0x21, 0x10); - break; - case 9: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1a, 0x1a, 0xa1, 0x10); - break; - case 10: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x12, 0x12, 0xa1, 0x10); - break; - case 11: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xb1, 0x10); - break; - case 12: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0xb1, 0x10); - break; - case 13: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1a, 0x1a, 0x21, 0x10); - break; - case 14: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x12, 0x12, 0x21, 0x10); - break; - case 15: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0x21, 0x10); - break; - case 16: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0x21, 0x10); - break; - case 17: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x3, 0xb1, 0x11); - break; - case 18: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x5, 0x5, 0xe1, 0x90); - break; - case 19: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0xe1, 0x90); - break; - case 20: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0x60, 0x90); - break; - case 21: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x3, 0x70, 0x90); - break; - case 22: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x61, - 0x1a, 0x1a, 0x21, 0x10); - break; - case 23: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x03, 0x31, 0x10); - break; - - case 71: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1a, 0x1a, 0xe1, 0x90); - break; - - /* following cases is for wifi rssi low, started from 81 */ - case 81: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x3a, 0x3, 0x90, 0x50); - break; - case 82: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x2b, 0x3, 0x90, 0x50); - break; - case 83: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x21, 0x3, 0x90, 0x50); - break; - case 84: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x15, 0x3, 0x90, 0x50); - break; - case 85: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1d, 0x1d, 0x80, 0x50); - break; - case 86: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x15, 0x15, 0x80, 0x50); - break; - } - } else { - /* disable PS tdma */ - switch (type) { - case 0: /* ANT2PTA, 0x778=0x1 */ - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - break; - case 1: /* ANT2BT, 0x778=3 */ - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x8, 0x0); - delay_ms(5); - halbtc8812a2ant_set_ant_path(btcoexist, - BTC_ANT_WIFI_AT_CPL_AUX, false, false); - break; - default: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8812a2ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* fw all off */ - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0); - - halbtc8812a2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - -void halbtc8812a2ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8812a2ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN boolean low_pwr_disable, IN u8 lps_val, - IN u8 rpwm_val) -{ - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - break; - case BTC_PS_LPS_ON: - halbtc8812a2ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8812a2ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - break; - default: - break; - } -} - -void halbtc8812a2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true, - 0x0, 0x0); - - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - -boolean halbtc8812a2ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean common = false, wifi_connected = false, wifi_busy = false; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_bt_inquiry(btcoexist); - return true; - } - - if (bt_link_info->sco_exist || bt_link_info->hid_exist) - halbtc8812a2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0); - else - halbtc8812a2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - if (!wifi_connected) { - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - false, 0x0, 0x0); - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non-connected idle!!\n"); - BTC_TRACE(trace_buf); - - if ((BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || - (BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } else { - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - } - - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - common = true; - } else { - if (BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, false, 0x0, 0x0); - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, - false, false, 0x8); - - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else if (BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status) { - if (bt_hs_on) - return false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, true, 0x0, 0x0); - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, - false, false, 0x8); - - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - common = false; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, true, 0x0, 0x0); - - halbtc8812a2ant_limited_rx(btcoexist, - NORMAL_EXEC, false, false, 0x8); - - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 17); - - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, - NORMAL_EXEC, 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, 0); - halbtc8812a2ant_sw_mechanism1(btcoexist, false, - false, false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - common = true; - } - } - } - - return common; -} - -void halbtc8812a2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, - IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0; - - coex_dm->auto_tdma_adjust_low_rssi = false; - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - { - if (sco_hid) { - if (tx_pause) { - if (max_interval == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } else if (max_interval == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (max_interval == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } else { - if (max_interval == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } else if (max_interval == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (max_interval == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } else { - if (tx_pause) { - if (max_interval == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (max_interval == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (max_interval == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } - } else { - if (max_interval == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (max_interval == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (max_interval == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } - } - } - } - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* accquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration */ - if (wait_count <= 2) - m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ - else - m = 1; - - if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration */ - if (wait_count == 1) - m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ - else - m = 1; - - if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (max_interval == 1) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 13); - coex_dm->ps_tdma_du_adj_type = 13; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 71); - coex_dm->ps_tdma_du_adj_type = 71; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 71); - coex_dm->ps_tdma_du_adj_type = - 71; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } - } - } - } else if (max_interval == 2) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } - } - } - } else if (max_interval == 3) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } - } - } - - /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ - /* then we have to adjust it back to the previous record one. */ - if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { - boolean scan = false, link = false, roam = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", - coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (!scan && !link && !roam) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); - BTC_TRACE(trace_buf); - } - } -} - -/* ****************** - * pstdma for wifi rssi low - * ****************** */ -void halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - IN struct btc_coexist *btcoexist/* , */ /* IN u8 wifi_status */) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0, bt_info_ext; - - coex_dm->auto_tdma_adjust = false; - - retry_count = coex_sta->bt_retry_cnt; - bt_info_ext = coex_sta->bt_info_ext; - - if (!coex_dm->auto_tdma_adjust_low_rssi) { - coex_dm->auto_tdma_adjust_low_rssi = true; - - if (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 83); - coex_dm->ps_tdma_du_adj_type = 83; - } else { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 82); - coex_dm->ps_tdma_du_adj_type = 82; - } - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* accquire the BT TRx retry count from BT_Info byte2 - * retry_count = coex_sta->bt_retry_cnt; - * bt_info_ext = coex_sta->bt_info_ext; */ - result = 0; - wait_count++; - - if ((coex_sta->low_priority_tx) > 1150 || - (coex_sta->low_priority_rx) > 1250) - retry_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ - if (wait_count <= 2) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ - if (wait_count == 1) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (result == -1) { - if ((BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 81) || - (coex_dm->cur_ps_tdma == 82))) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 84); - coex_dm->ps_tdma_du_adj_type = 84; - } else if (coex_dm->cur_ps_tdma == 81) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 82); - coex_dm->ps_tdma_du_adj_type = 82; - } else if (coex_dm->cur_ps_tdma == 82) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 83); - coex_dm->ps_tdma_du_adj_type = 83; - } else if (coex_dm->cur_ps_tdma == 83) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 84); - coex_dm->ps_tdma_du_adj_type = 84; - } - } else if (result == 1) { - if ((BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 81) || - (coex_dm->cur_ps_tdma == 82))) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 83); - coex_dm->ps_tdma_du_adj_type = 83; - } else if (coex_dm->cur_ps_tdma == 84) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 83); - coex_dm->ps_tdma_du_adj_type = 83; - } else if (coex_dm->cur_ps_tdma == 83) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 82); - coex_dm->ps_tdma_du_adj_type = 82; - } else if (coex_dm->cur_ps_tdma == 82) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 81); - coex_dm->ps_tdma_du_adj_type = 81; - } - } - - if (coex_dm->cur_ps_tdma != 81 && - coex_dm->cur_ps_tdma != 82 && - coex_dm->cur_ps_tdma != 83 && - coex_dm->cur_ps_tdma != 84) { - /* recover to previous adjust type */ - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - } - } -} - -void halbtc8812a2ant_get_bt_rssi_threshold(IN struct btc_coexist *btcoexist, - IN u8 *pThres0, IN u8 *pThres1) -{ - u8 ant_type; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &ant_type); - - switch (ant_type) { - case BTC_ANT_TYPE_0: - *pThres0 = 100; - *pThres1 = 100; - break; - case BTC_ANT_TYPE_1: - *pThres0 = 34; - *pThres1 = 42; - break; - case BTC_ANT_TYPE_2: - *pThres0 = 34; - *pThres1 = 42; - break; - case BTC_ANT_TYPE_3: - *pThres0 = 34; - *pThres1 = 42; - break; - case BTC_ANT_TYPE_4: - *pThres0 = 34; - *pThres1 = 42; - break; - default: - break; - } -} - - - -void halbtc8812a2ant_action_sco(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true, - 0x0, 0x0); - - /* coex table */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - /* pstdma */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - else - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - true, 0x6); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - true, 0x6); - } - } -} - -void halbtc8812a2ant_action_sco_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true, - 0x0, 0x0); - - /* coex table */ - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - /* pstdma */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - else - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x6); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x6); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x6); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x6); - } - } -} - -void halbtc8812a2ant_action_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true, - 0x0, 0x0); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - else - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, - 0x8); - - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8812a2ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - if ((ap_enable == true) || (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - true, 0x0, 0x0); - else - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, true, - 0x50, 0x4); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, false, - 1); - else - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8812a2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true, - 0x0, 0x0); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, false, - 2); - else - halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, true, 2); - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - true, 0x6); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - true, 0x6); - } - } -} - -void halbtc8812a2ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - if ((ap_enable == true) || (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - true, 0x0, 0x0); - else - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, true, - 0x50, 0x4); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); - else - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85); - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* PAN(HS) only */ -void halbtc8812a2ant_action_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); - - /* power save state */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true, - 0x0, 0x0); - - /* coex table */ - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - /* pstdma */ - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* PAN(EDR)+A2DP */ -void halbtc8812a2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - if ((ap_enable == true) || (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - true, 0x0, 0x0); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - true, 0x0, 0x0); - else - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, true, - 0x50, 0x4); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, false, - 3); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, true, 3); - else { - coex_dm->auto_tdma_adjust = false; - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); - } - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8812a2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - if ((ap_enable == true) || (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - true, 0x0, 0x0); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - true, 0x0, 0x0); - else - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, true, - 0x50, 0x4); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - else - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85); - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, - 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* HID+A2DP+PAN(EDR) */ -void halbtc8812a2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - if ((ap_enable == true) || (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - true, 0x0, 0x0); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - true, 0x0, 0x0); - else - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, true, - 0x50, 0x4); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, false, 3); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 3); - else { - coex_dm->auto_tdma_adjust = false; - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); - } - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, - 0x8); - - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8812a2ant_action_hid_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true, - 0x0, 0x0); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, false, 2); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 2); - else - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 2); - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, - 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8812a2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - if ((ap_enable == true) || (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - true, 0x0, 0x0); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - true, 0x0, 0x0); - else - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, true, - 0x50, 0x4); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, false, 2); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 2); - else { - coex_dm->auto_tdma_adjust = false; - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 82); - } - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, - 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - - -void halbtc8812a2ant_coex_under_5g(IN struct btc_coexist *btcoexist) -{ - halbtc8812a2ant_coex_all_off(btcoexist); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Under 5G, force set BT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true); -} -/* **************************************************** */ -void halbtc8812a2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - boolean wifi_under_5g = false; - u8 algorithm = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_coex_under_5g(btcoexist); - return; - } - - - algorithm = halbtc8812a2ant_action_algorithm(btcoexist); - if (coex_sta->c2h_bt_inquiry_page && - (BT_8812A_2ANT_COEX_ALGO_PANHS != algorithm)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_bt_inquiry(btcoexist); - return; - } - - coex_dm->cur_algorithm = algorithm; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", - coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - - if (halbtc8812a2ant_is_common_action(btcoexist)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant common.\n"); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - } else { - if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", - coex_dm->pre_algorithm, coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - } - switch (coex_dm->cur_algorithm) { - case BT_8812A_2ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_sco(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_SCO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_sco_hid(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_hid(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_a2dp(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_pan_edr(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_pan_hs(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_pan_edr_hid(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_hid_a2dp_pan_hs( - btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_hid_a2dp(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_coex_all_off(btcoexist); - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } - -} - -void halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up) -{ - u8 u8tmp = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - if (back_up) { - /* backup rf 0x1e value */ - coex_dm->bt_rf_0x1e_backup = - btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff); - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } - - /* ant sw control to BT */ - halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, true, - false); - - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* PTA parameter */ - btcoexist->btc_write_1byte(btcoexist, 0x6cc, 0x0); - btcoexist->btc_write_4byte(btcoexist, 0x6c8, 0xffff); - btcoexist->btc_write_4byte(btcoexist, 0x6c4, 0x55555555); - btcoexist->btc_write_4byte(btcoexist, 0x6c0, 0x55555555); - - /* coex parameters */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - - /* enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* enable PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); - - /* bt clock related */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x4); - u8tmp |= BIT(7); - btcoexist->btc_write_1byte(btcoexist, 0x4, u8tmp); - - /* bt clock related */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); - u8tmp |= BIT(1); - btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); -} - -/* ************************************************************ - * work around function start with wa_halbtc8812a2ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8812a2ant_ - * ************************************************************ */ -void ex_halbtc8812a2ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8812a2ant_init_hw_config(btcoexist, true); - btcoexist->stop_coex_dm = false; -} - -void ex_halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - halbtc8812a2ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8812a2ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fw_ver = 0, bt_patch_ver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", - "CoexVer/ FwVer/ PatchVer", - glcoex_ver_date_8812a_2ant, glcoex_ver_8812a_2ant, fw_ver, - bt_patch_ver, bt_patch_ver); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", - "SCO/HID/PAN/A2DP", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8812A_2ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8812a_2ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - /* Sw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Sw mechanism]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", - "SM1[ShRf/ LpRA/ LimDig]", - coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, - coex_dm->limited_dig); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", - "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", - coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, - coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); - CL_PRINTF(cli_buf); - - /* Fw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Fw mechanism]============"); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d/%d)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], - ps_tdma_case, coex_dm->auto_tdma_adjust, - coex_dm->auto_tdma_adjust_low_rssi); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "DecBtPwr/ IgnWlanAct", - coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", - "RF-A, 0x1e initVal", - coex_dm->bt_rf_0x1e_backup); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "backup ARFR1/ARFR2/RL/AMaxTime", - coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2, - coex_dm->backup_retry_limit, - coex_dm->backup_ampdu_max_time); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x ", - "0x778 (W_Act)/ 0x6cc (CoTab Sel)", - u8tmp[0], u8tmp[1]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x8db); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xc5b); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x8db(ADC)/0xc5b[29:25](DAC)", - ((u8tmp[0] & 0x60) >> 5), ((u8tmp[1] & 0x3e) >> 1)); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcb3); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb7); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xcb3/ 0xcb7", - u8tmp[0], u8tmp[1]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x974); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x40/ 0x4c[24:23]/ 0x974", - u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u32tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa0a); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xc50(DIG)/0xa0a(CCK-TH)", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xf48); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xf48/ 0xa5b (FA cnt-- OFDM : CCK)", - u32tmp[0], (u8tmp[0] << 8) + u8tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8812A_2ANT == 1) - halbtc8812a2ant_monitor_bt_ctr(btcoexist); -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8812a2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - halbtc8812a2ant_coex_all_off(btcoexist); - halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, - false, true); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS notify, force set BT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - ex_halbtc8812a2ant_media_status_notify(btcoexist, - BTC_MEDIA_DISCONNECT); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, - &wifi_under_5g); - if (!wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS notify, force set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, - false); - } - } -} - -void ex_halbtc8812a2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8812a2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_SCAN_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_SCAN_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8812a2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_ASSOCIATE_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_ASSOCIATE_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8812a2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 data_len = 5; - u8 buf[6] = {0}; - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = 0x1; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - buf[0] = data_len; - buf[1] = 0x5; /* OP_Code */ - buf[2] = 0x3; /* OP_Code_Length */ - buf[3] = h2c_parameter[0]; /* OP_Code_Content */ - buf[4] = h2c_parameter[1]; - buf[5] = h2c_parameter[2]; - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); -} - -void ex_halbtc8812a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (type == BTC_PACKET_DHCP) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], DHCP Packet notify\n"); - BTC_TRACE(trace_buf); - } - -} - -void ex_halbtc8812a2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean bt_busy = false, limited_dig = false; - boolean wifi_connected = false, wifi_under_5g = false; - - coex_sta->c2h_bt_info_req_sent = false; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8812A_2ANT_MAX) - rsp_source = BT_INFO_SRC_8812A_2ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (BT_INFO_SRC_8812A_2ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8812a2ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8812a2ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if ((coex_sta->bt_info_ext & BIT(3)) && !wifi_under_5g) { - /* BT already ignored WlanAct */ - if (!btcoexist->manual_control && - !btcoexist->stop_coex_dm) { - if (!coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_ignore_wlan_act( - btcoexist, FORCE_EXEC, false); - } - } - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - - if (coex_sta->under_ips) { - /* work around for 8812a combo hw bug => when IPS, wlanAct is always high. */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS, set BT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, true); - } - } - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8812A_2ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8812A_2ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - coex_sta->acl_busy = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8812A_2ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8812A_2ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8812A_2ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8812A_2ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - if (bt_info & BT_INFO_8812A_2ANT_B_ACL_BUSY) - coex_sta->acl_busy = true; - else - coex_sta->acl_busy = false; - - } - - halbtc8812a2ant_update_bt_link_info(btcoexist); - - if (!(bt_info & BT_INFO_8812A_2ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8812A_2ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8812A_2ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8812A_2ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8812A_2ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8812A_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8812A_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { - bt_busy = true; - if (!wifi_under_5g) - limited_dig = true; - } else { - bt_busy = false; - limited_dig = false; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - coex_dm->limited_dig = limited_dig; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); - - halbtc8812a2ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8812a2ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - } - if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - true, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); - /* halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, false, true); */ - halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - btcoexist->stop_coex_dm = true; - - } -} - - -void ex_halbtc8812a2ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, false, - true); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Halt notify, force set BT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - ex_halbtc8812a2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - /* 0x522=0xff, pause tx */ - btcoexist->btc_write_1byte(btcoexist, 0x522, 0xff); - /* 0x40[7:6]=2'b01, modify BT mode. */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0xc0, 0x2); - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8812a2ant_periodical(IN struct btc_coexist *btcoexist) -{ -#if (BT_AUTO_REPORT_ONLY_8812A_2ANT == 0) - halbtc8812a2ant_query_bt_info(btcoexist); - halbtc8812a2ant_monitor_bt_ctr(btcoexist); - halbtc8812a2ant_monitor_bt_enable_disable(btcoexist); -#else - if (halbtc8812a2ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust || - coex_dm->auto_tdma_adjust_low_rssi) - halbtc8812a2ant_run_coexist_mechanism(btcoexist); -#endif -} - -void ex_halbtc8812a2ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata) -{ - switch (op_code) { - case BTC_DBG_SET_COEX_DEC_BT_PWR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set Dec BT power\n"); - BTC_TRACE(trace_buf); - { - u8 data_len = 4; - u8 buf[6] = {0}; - u8 dec_bt_pwr = 0, pwr_level = 0; - if (op_len == 2) { - dec_bt_pwr = pdata[0]; - pwr_level = pdata[1]; - - buf[0] = data_len; - buf[1] = 0x3; /* OP_Code */ - buf[2] = 0x2; /* OP_Code_Length */ - - buf[3] = dec_bt_pwr; /* OP_Code_Content */ - buf[4] = pwr_level; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set Dec BT power=%d, pwr_level=%d\n", - dec_bt_pwr, pwr_level); - BTC_TRACE(trace_buf); - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); - } - } - break; - - case BTC_DBG_SET_COEX_BT_AFH_MAP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT AFH Map\n"); - BTC_TRACE(trace_buf); - { - u8 data_len = 5; - u8 buf[6] = {0}; - if (op_len == 3) { - buf[0] = data_len; - buf[1] = 0x5; /* OP_Code */ - buf[2] = 0x3; /* OP_Code_Length */ - - buf[3] = pdata[0]; /* OP_Code_Content */ - buf[4] = pdata[1]; - buf[5] = pdata[2]; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT AFH Map = %02x %02x %02x\n", - pdata[0], pdata[1], pdata[2]); - BTC_TRACE(trace_buf); - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); - } - } - break; - - case BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT Ignore Wlan Active\n"); - BTC_TRACE(trace_buf); - { - u8 data_len = 3; - u8 buf[6] = {0}; - if (op_len == 1) { - buf[0] = data_len; - buf[1] = 0x1; /* OP_Code */ - buf[2] = 0x1; /* OP_Code_Length */ - - buf[3] = pdata[0]; /* OP_Code_Content */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT Ignore Wlan Active = 0x%x\n", - pdata[0]); - BTC_TRACE(trace_buf); - - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); - } - } - break; - - default: - break; - } -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ \ No newline at end of file diff --git a/hal/btc/HalBtc8812a2Ant.h b/hal/btc/HalBtc8812a2Ant.h deleted file mode 100644 index be08dd3..0000000 --- a/hal/btc/HalBtc8812a2Ant.h +++ /dev/null @@ -1,202 +0,0 @@ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8812A_SUPPORT == 1) - -/* ******************************************* - * The following is for 8812A 2Ant BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8812A_2ANT 0 - -#define BT_INFO_8812A_2ANT_B_FTP BIT(7) -#define BT_INFO_8812A_2ANT_B_A2DP BIT(6) -#define BT_INFO_8812A_2ANT_B_HID BIT(5) -#define BT_INFO_8812A_2ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8812A_2ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8812A_2ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8812A_2ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8812A_2ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT 2 - -enum bt_info_src_8812a_2ant { - BT_INFO_SRC_8812A_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8812A_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8812A_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8812A_2ANT_MAX -}; - -enum bt_8812a_2ant_bt_status { - BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8812A_2ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8812A_2ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8812A_2ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8812A_2ANT_BT_STATUS_MAX -}; - -enum bt_8812a_2ant_coex_algo { - BT_8812A_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8812A_2ANT_COEX_ALGO_SCO = 0x1, - BT_8812A_2ANT_COEX_ALGO_SCO_HID = 0x2, - BT_8812A_2ANT_COEX_ALGO_HID = 0x3, - BT_8812A_2ANT_COEX_ALGO_A2DP = 0x4, - BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS = 0x5, - BT_8812A_2ANT_COEX_ALGO_PANEDR = 0x6, - BT_8812A_2ANT_COEX_ALGO_PANHS = 0x7, - BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8, - BT_8812A_2ANT_COEX_ALGO_PANEDR_HID = 0x9, - BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa, - BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS = 0xb, - BT_8812A_2ANT_COEX_ALGO_HID_A2DP = 0xc, - BT_8812A_2ANT_COEX_ALGO_MAX = 0xd -}; - -struct coex_dm_8812a_2ant { - /* fw mechanism */ - u8 pre_bt_dec_pwr_lvl; - u8 cur_bt_dec_pwr_lvl; - u8 pre_fw_dac_swing_lvl; - u8 cur_fw_dac_swing_lvl; - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean auto_tdma_adjust_low_rssi; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_rf_rx_lpf_shrink; - boolean cur_rf_rx_lpf_shrink; - u32 bt_rf_0x1e_backup; - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - boolean pre_dac_swing_on; - u32 pre_dac_swing_lvl; - boolean cur_dac_swing_on; - u32 cur_dac_swing_lvl; - boolean pre_adc_back_off; - boolean cur_adc_back_off; - boolean pre_agc_table_en; - boolean cur_agc_table_en; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 cur_ra_mask_type; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; -}; - -struct coex_sta_8812a_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - boolean acl_busy; - - boolean under_lps; - boolean under_ips; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - u8 bt_rssi; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8812A_2ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8812A_2ANT_MAX]; - u32 bt_info_query_cnt; - boolean c2h_bt_inquiry_page; - u8 bt_retry_cnt; - u8 bt_info_ext; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8812a2ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8812a2ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); - -void ex_halbtc8812a2ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a2ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a2ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a2ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata); - -#else -#define ex_halbtc8812a2ant_power_on_setting(btcoexist) -#define ex_halbtc8812a2ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8812a2ant_init_coex_dm(btcoexist) -#define ex_halbtc8812a2ant_ips_notify(btcoexist, type) -#define ex_halbtc8812a2ant_lps_notify(btcoexist, type) -#define ex_halbtc8812a2ant_scan_notify(btcoexist, type) -#define ex_halbtc8812a2ant_connect_notify(btcoexist, type) -#define ex_halbtc8812a2ant_media_status_notify(btcoexist, type) -#define ex_halbtc8812a2ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8812a2ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8812a2ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8812a2ant_halt_notify(btcoexist) -#define ex_halbtc8812a2ant_periodical(btcoexist) -#define ex_halbtc8812a2ant_display_coex_info(btcoexist) -#define ex_halbtc8812a2ant_dbg_control(btcoexist, op_code, op_len, pdata) -#endif - -#endif diff --git a/hal/btc/HalBtc8821a1Ant.c b/hal/btc/HalBtc8821a1Ant.c deleted file mode 100644 index 81ddf03..0000000 --- a/hal/btc/HalBtc8821a1Ant.c +++ /dev/null @@ -1,3100 +0,0 @@ -/* ************************************************************ - * Description: - * - * This file is for 8821A_1ANT Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ - * SY modify 2015/04/27 - * ************************************************************ - * include files - * ************************************************************ */ -#include "Mp_Precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821A_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8821a_1ant glcoex_dm_8821a_1ant; -static struct coex_dm_8821a_1ant *coex_dm = &glcoex_dm_8821a_1ant; -static struct coex_sta_8821a_1ant glcoex_sta_8821a_1ant; -static struct coex_sta_8821a_1ant *coex_sta = &glcoex_sta_8821a_1ant; - -const char *const glbt_info_src_8821a_1ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8821a_1ant = 20150615; -u32 glcoex_ver_8821a_1ant = 0x61; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8821a1ant_ - * ************************************************************ */ -u8 halbtc8821a1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8821a1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8821a1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8821a1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8821a1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8821a1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8821a1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8821a1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8821a1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8821a1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8821a1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8821a1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8821a1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - - -/* ture/xxxx/x:1 - * false/false/x: 64 - * false/ture/x:x */ -void halbtc8821a1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8821a1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; -#if 0 - /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ - if (!(btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8)) { - coex_sta->high_priority_tx = 65535; - coex_sta->high_priority_rx = 65535; - coex_sta->low_priority_tx = 65535; - coex_sta->low_priority_rx = 65535; - return; - } -#endif - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); -} - -void halbtc8821a1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -boolean halbtc8821a1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - } - - return false; -} - -void halbtc8821a1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8821a1ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8821A_1ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8821a1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8821a1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8821a1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8821a1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf5; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xa0; /* MCS6 or OFDM48// */ - h2c_parameter[5] = 0xa0; /* MCS5 or OFDM36 // */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8821a1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8821a1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8821a1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8821a1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8821a1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8821a1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** CoexTable(%d) **********\n", type); - BTC_TRACE(trace_buf); - - switch (type) { - case 0: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, 0xffffff, 0x3); - break; - case 1: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 2: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 3: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 4: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 5: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaaaa5a5a, 0xffffff, 0x3); - break; - case 6: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); - break; - case 7: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8821a1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8821a1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8821a1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8821a1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - } - } - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8821a1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8821a1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8821a1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8821a1ant_sw_mechanism(IN struct btc_coexist *btcoexist, - IN boolean low_penalty_ra) -{ - halbtc8821a1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8821a1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u32 u32tmp = 0; - u8 h2c_parameter[2] = {0}; - - if (init_hwcfg) { - /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp |= BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - - /* 0x765 = 0x18 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x3); - - if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { - /* tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ - h2c_parameter[0] = 1; - h2c_parameter[1] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, 0x1); //Main Ant to BT for IPS case 0x4c[23]=1 */ - } else { - /* tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ - h2c_parameter[0] = 0; - h2c_parameter[1] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, 0x0); //Aux Ant to BT for IPS case 0x4c[23]=1 */ - } - } else if (wifi_off) { - /* 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL BT Vendor 0xac=0xf002 */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp &= ~BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - - /* 0x765 = 0x18 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x3); - } else { - /* 0x765 = 0x0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x0); - } - - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77); - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcb7, 0x30, 0x1); - else - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcb7, 0x30, 0x2); - break; - case BTC_ANT_PATH_BT: - btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77); - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcb7, 0x30, 0x2); - else - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcb7, 0x30, 0x1); - break; - default: - case BTC_ANT_PATH_PTA: - btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x66); - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcb7, 0x30, 0x1); - else - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcb7, 0x30, 0x2); - break; - } -} - -void halbtc8821a1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - u8 rssi_adjust_val = 0; - /* u32 fw_ver=0; */ - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - if (turn_on) { - switch (type) { - default: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1a, 0x1a, 0x0, 0x50); - break; - case 1: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x3a, 0x03, 0x10, 0x50); - rssi_adjust_val = 11; - break; - case 2: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x2b, 0x03, 0x10, 0x50); - rssi_adjust_val = 14; - break; - case 3: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1d, 0x1d, 0x0, 0x52); - break; - case 4: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x14, 0x0); - rssi_adjust_val = 17; - break; - case 5: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x15, 0x3, 0x11, 0x10); - break; - case 6: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x3, 0x11, 0x13); - break; - case 7: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13, - 0xc, 0x5, 0x0, 0x0); - break; - case 8: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 9: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x21, 0x3, 0x10, 0x50); - rssi_adjust_val = 18; - break; - case 10: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0xa, 0x0, 0x40); - break; - case 11: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x15, 0x03, 0x10, 0x50); - rssi_adjust_val = 20; - break; - case 12: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x0a, 0x0a, 0x0, 0x50); - break; - case 13: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x12, 0x12, 0x0, 0x50); - break; - case 14: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1e, 0x3, 0x10, 0x14); - break; - case 15: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0x3, 0x8, 0x0); - break; - case 16: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x10, 0x0); - rssi_adjust_val = 18; - break; - case 18: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - rssi_adjust_val = 14; - break; - case 20: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, 0x10); - break; - case 21: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x11); - break; - case 22: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x10); - break; - case 23: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x18); - rssi_adjust_val = 22; - break; - case 24: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x3, 0x31, 0x18); - rssi_adjust_val = 22; - break; - case 25: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - rssi_adjust_val = 22; - break; - case 26: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - rssi_adjust_val = 22; - break; - case 27: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x98); - rssi_adjust_val = 22; - break; - case 28: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x69, - 0x25, 0x3, 0x31, 0x0); - break; - case 29: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xab, - 0x1a, 0x1a, 0x1, 0x10); - break; - case 30: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, 0x10); - break; - case 31: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1a, 0x1a, 0, 0x58); - break; - case 32: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x3, 0x11, 0x11); - break; - case 33: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xa3, - 0x25, 0x3, 0x30, 0x90); - break; - case 34: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x53, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 35: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x63, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 36: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x12, 0x3, 0x14, 0x50); - break; - case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */ - /* here softap mode screen off will cost 70-80mA for phone */ - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x23, - 0x18, 0x00, 0x10, 0x24); - break; - case 41: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x15, 0x3, 0x11, 0x11); - break; - case 42: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x20, 0x3, 0x11, 0x11); - break; - case 43: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, 0x11); - break; - } - } else { - /* disable PS tdma */ - switch (type) { - case 8: /* PTA Control */ - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - halbtc8821a1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, false, false); - break; - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - halbtc8821a1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, false, false); - break; - case 9: /* Software control, Antenna at WiFi side */ - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - halbtc8821a1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_WIFI, false, false); - break; - case 10: /* under 5G */ - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x8, 0x0); - halbtc8821a1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, false, false); - break; - } - } - rssi_adjust_val = 0; - btcoexist->btc_set(btcoexist, - BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val); - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8821a1ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* sw all off */ - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - /* hw all off */ - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -boolean halbtc8821a1ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - common = true; - } else if (wifi_connected && - (BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - common = true; - } else if (!wifi_connected && - (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - common = true; - } else if (wifi_connected && - (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - common = true; - } else if (!wifi_connected && - (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } - - common = false; - } - - return common; -} - -void halbtc8821a1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8821a1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - break; - case BTC_PS_LPS_ON: - halbtc8821a1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8821a1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - break; - case BTC_PS_LPS_OFF: - halbtc8821a1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - break; - default: - break; - } -} - -void halbtc8821a1ant_coex_under_5g(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8821a1ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true); - - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 10); - - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 5); -} - -void halbtc8821a1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 9); -} - -void halbtc8821a1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - BTC_TRACE(trace_buf); - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 2) { - bt_disabled = true; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_wifi_only(btcoexist); - } - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - if (!bt_disabled) { - } else { - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - } - } -} - -/* ********************************************* - * - * Software Coex Mechanism start - * - * ********************************************* */ - -void halbtc8821a1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - /* halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); */ - halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, false, false); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} -/* SCO only or SCO+PAN(HS) */ -void halbtc8821a1ant_action_sco(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, true); -} - -void halbtc8821a1ant_action_hid(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, true); -} - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8821a1ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8821a1ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8821a1ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, false); -} - -/* PAN(HS) only */ -void halbtc8821a1ant_action_pan_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, false); -} - -/* PAN(EDR)+A2DP */ -void halbtc8821a1ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8821a1ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, true); -} - -/* HID+A2DP+PAN(EDR) */ -void halbtc8821a1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, true); -} - -void halbtc8821a1ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, true); -} - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8821a1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8821a1ant_action_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8821a1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, ap_enable = false, wifi_busy = false, - bt_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) { - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } - - /* sy modify */ - else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - /* SCO/HID/A2DP busy */ - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } - - /* sy modify */ - - else if ((bt_link_info->a2dp_exist) && - (bt_link_info->hid_exist)) { - /* A2DP+HID busy */ - halbtc8821a1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } - - - else if ((bt_link_info->pan_exist) || (wifi_busy)) { - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } -} - -void halbtc8821a1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* tdma and coex table */ - - if (bt_link_info->sco_exist) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 41); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } else { /* HID */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 42); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8821a1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - u8 bt_rssi_state; - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - bt_rssi_state = halbtc8821a1ant_bt_rssi_state(2, 28, 0); - - if (bt_link_info->hid_only) { /* HID */ - halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, - wifi_status); - coex_dm->auto_tdma_adjust = false; - return; - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { - /* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); */ - /* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = false; - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - /* halbtc8821a1ant_tdma_duration_adjust_for_acl(btcoexist, wifi_status); */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } else { /* for low BT RSSI */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = false; - } - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - coex_dm->auto_tdma_adjust = false; - } else { /* for low BT RSSI */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - coex_dm->auto_tdma_adjust = false; - } - - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && - bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); - coex_dm->auto_tdma_adjust = false; - } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 43); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = false; - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = false; - } -} - -void halbtc8821a1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - /* power save state */ - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8821a1ant_action_wifi_not_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - /* sy modify */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } else if (bt_link_info->a2dp_exist && bt_link_info->pan_exist) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); */ - /* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); */ - - /* Bryant Add */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8821a1ant_action_wifi_not_connected_asso_auth( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) { - /* sy modify */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - } else if ((bt_link_info->a2dp_exist) || (bt_link_info->pan_exist)) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8821a1ant_action_wifi_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - /* sy modify */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); */ - /* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); */ - - /* Bryant Add */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8821a1ant_action_wifi_connected_specific_packet( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - /* sy modify */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } - - if ((bt_link_info->hid_exist) && (bt_link_info->a2dp_exist)) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } - - - else if (bt_link_info->pan_exist) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8821a1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - boolean scan = false, link = false, roam = false; - boolean under_4way = false, ap_enable = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (under_4way) { - halbtc8821a1ant_action_wifi_connected_specific_packet(btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - if (scan) - halbtc8821a1ant_action_wifi_connected_scan(btcoexist); - else - halbtc8821a1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - /* power save state */ - if (!ap_enable && - BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status && - !btcoexist->bt_link_info.hid_only) { - if (!wifi_busy && btcoexist->bt_link_info.a2dp_only) /* A2DP */ - halbtc8821a1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - else - halbtc8821a1ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - } else - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - /* tdma and coex table */ - if (!wifi_busy) { - if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8821a1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - } - } else { - if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8821a1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - } - } -} - -void halbtc8821a1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - - algorithm = halbtc8821a1ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - - if (halbtc8821a1ant_is_common_action(btcoexist)) { - - } else { - switch (coex_dm->cur_algorithm) { - case BT_8821A_1ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_sco(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_hid(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_a2dp(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_pan_edr(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_pan_hs(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_pan_edr_hid(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_hid_a2dp(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8821a1ant_coex_all_off(btcoexist); */ - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8821a1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean wifi_under_5g = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_bt_whck_test(btcoexist); - return; - } - - if ((BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8821a1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (!bt_link_info->sco_exist && !bt_link_info->hid_exist) - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - else { - if (wifi_connected) { - wifi_rssi_state = halbtc8821a1ant_wifi_rssi_state( - btcoexist, 1, 2, 30, 0); - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - /* halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 1, 1); */ - halbtc8821a1ant_limited_tx(btcoexist, - NORMAL_EXEC, 1, 1, 0, 1); - } else { - /* halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 1, 1); */ - halbtc8821a1ant_limited_tx(btcoexist, - NORMAL_EXEC, 1, 1, 0, 1); - } - } else - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, - 0, 0); - - } - - if (bt_link_info->sco_exist) { - bt_ctrl_agg_buf_size = true; - agg_buf_size = 0x3; - } else if (bt_link_info->hid_exist) { - bt_ctrl_agg_buf_size = true; - agg_buf_size = 0x5; - } else if (bt_link_info->a2dp_exist || bt_link_info->pan_exist) { - bt_ctrl_agg_buf_size = true; - agg_buf_size = 0x8; - } - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - halbtc8821a1ant_run_sw_coexist_mechanism(btcoexist); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8821a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8821a1ant_action_hs(btcoexist); - return; - } - - - if (!wifi_connected) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is non connected-idle !!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - if (scan) - halbtc8821a1ant_action_wifi_not_connected_scan( - btcoexist); - else - halbtc8821a1ant_action_wifi_not_connected_asso_auth( - btcoexist); - } else - halbtc8821a1ant_action_wifi_not_connected(btcoexist); - } else /* wifi LPS/Busy */ - halbtc8821a1ant_action_wifi_connected(btcoexist); -} - -void halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - /* sw all off */ - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - /* halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ - halbtc8821a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); -} - -void halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up, IN boolean wifi_only) -{ - u8 u8tmp = 0; - boolean wifi_under_5g = false; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - if (wifi_only) - return; - - if (back_up) { - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } - - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - /* Antenna config */ - if (wifi_under_5g) - halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, - false); - else - halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, true, - false); - - /* PTA parameter */ - halbtc8821a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - /* Enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, - 0xc); /* 0x76e[3] =1, WLAN_Act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); -} - -/* ************************************************************ - * work around function start with wa_halbtc8821a1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8821a1ant_ - * ************************************************************ */ -void ex_halbtc8821a1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8821a1ant_init_hw_config(btcoexist, true, wifi_only); -} - -void ex_halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - - halbtc8821a1ant_init_coex_dm(btcoexist); - - halbtc8821a1ant_query_bt_info(btcoexist); -} - -void ex_halbtc8821a1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fw_ver = 0, bt_patch_ver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", - "Ant PG Num/ Ant Mech/ Ant Pos:", - board_info->pg_ant_num, board_info->btdm_ant_num, - board_info->btdm_ant_pos); - CL_PRINTF(cli_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)", - "CoexVer/ FwVer/ PatchVer", - glcoex_ver_date_8821a_1ant, glcoex_ver_8821a_1ant, fw_ver, - bt_patch_ver, bt_patch_ver); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", - "SCO/HID/PAN/A2DP", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8821A_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8821a_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - if (!btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "SM[LowPenaltyRA]", - coex_dm->cur_low_penalty_ra); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - coex_dm->auto_tdma_adjust); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", - "IgnWlanAct", - coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", - "Latest error condition(should be 0)", - coex_dm->error_condition); - CL_PRINTF(cli_buf); - } - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "backup ARFR1/ARFR2/RL/AMaxTime", - coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2, - coex_dm->backup_retry_limit, - coex_dm->backup_ampdu_max_time); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc58); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x778/ 0xc58[29:25]", - u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x8db); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8db[6:5]", - ((u8tmp[0] & 0x60) >> 5)); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x975); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0xcb4[29:28]/0xcb4[7:0]/0x974[9:8]", - (u32tmp[0] & 0x30000000) >> 28, u32tmp[0] & 0xff, - u8tmp[0] & 0x3); - CL_PRINTF(cli_buf); - - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x64); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x40/0x4c[24:23]/0x64[0]", - u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u8tmp[1] & 0x1); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", - u32tmp[0] & 0xff); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xf48); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5d); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "OFDM-FA/ CCK-FA", - u32tmp[0], (u8tmp[0] << 8) + u8tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 1) - halbtc8821a1ant_monitor_bt_ctr(btcoexist); -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8821a1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, - &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, - true); - /* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */ - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; - - halbtc8821a1ant_init_hw_config(btcoexist, false, false); - halbtc8821a1ant_init_coex_dm(btcoexist); - halbtc8821a1ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8821a1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8821a1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - if (BTC_SCAN_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - } - - if (coex_sta->bt_disabled) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - halbtc8821a1ant_query_bt_info(btcoexist); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8821a1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8821a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8821a1ant_action_hs(btcoexist); - return; - } - - if (BTC_SCAN_START == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8821a1ant_action_wifi_not_connected_scan( - btcoexist); - else /* wifi is connected */ - halbtc8821a1ant_action_wifi_connected_scan(btcoexist); - } else if (BTC_SCAN_FINISH == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8821a1ant_action_wifi_not_connected(btcoexist); - else - halbtc8821a1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8821a1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - if (BTC_ASSOCIATE_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8821a1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8821a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8821a1ant_action_hs(btcoexist); - return; - } - - if (BTC_ASSOCIATE_START == type) - halbtc8821a1ant_action_wifi_not_connected_asso_auth(btcoexist); - else if (BTC_ASSOCIATE_FINISH == type) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (!wifi_connected) /* non-connected scan */ - halbtc8821a1ant_action_wifi_not_connected(btcoexist); - else - halbtc8821a1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8821a1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - /* h2c_parameter[0] = 0x1; */ - h2c_parameter[0] = 0x0; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); -} - -void ex_halbtc8821a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - BTC_PACKET_ARP == type) { - coex_sta->wifi_is_high_pri_task = true; - - if (BTC_PACKET_ARP == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify\n"); - BTC_TRACE(trace_buf); - } - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet [Type = %d] notify\n", type); - BTC_TRACE(trace_buf); - } - - coex_sta->specific_pkt_period_cnt = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8821a1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8821a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8821a1ant_action_hs(btcoexist); - return; - } - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - BTC_PACKET_ARP == type) { - if (BTC_PACKET_ARP == type) { - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ARP Packet Count = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - if (coex_dm->arp_cnt >= - 10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */ - return; - } - - halbtc8821a1ant_action_wifi_connected_specific_packet(btcoexist); - } -} - -void ex_halbtc8821a1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean bt_busy = false; - boolean wifi_under_5g = false; - - - coex_sta->c2h_bt_info_req_sent = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8821A_1ANT_MAX) - rsp_source = BT_INFO_SRC_8821A_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - /* if 0xff, it means BT is under WHCK test */ - if (bt_info == 0xff) - coex_sta->bt_whck_test = true; - else - coex_sta->bt_whck_test = false; - - if (BT_INFO_SRC_8821A_1ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_page = true; - else - coex_sta->c2h_bt_page = false; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] - & 0x40); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, - &coex_sta->bt_tx_rx_mask); - if (!coex_sta->bt_tx_rx_mask) { - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x3c, 0x15); - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if (coex_sta->bt_info_ext & BIT(1)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8821a1ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8821a1ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if ((coex_sta->bt_info_ext & BIT(3)) && !wifi_under_5g) { - if (!btcoexist->manual_control && - !btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - } -#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8821a1ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8821A_1ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8821A_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8821A_1ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8821A_1ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8821A_1ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8821A_1ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - } - - halbtc8821a1ant_update_bt_link_info(btcoexist); - - bt_info = bt_info & - 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ - - if (!(bt_info & BT_INFO_8821A_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8821A_1ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8821A_1ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8821A_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8821A_1ANT_B_ACL_BUSY) { - if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) - coex_dm->auto_tdma_adjust = false; - coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - halbtc8821a1ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8821a1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - boolean wifi_under_5g = false; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true); - /* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */ - - halbtc8821a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8821a1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8821a1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - boolean wifi_under_5g = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, - true); - /* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */ - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - halbtc8821a1ant_init_hw_config(btcoexist, false, false); - halbtc8821a1ant_init_coex_dm(btcoexist); - halbtc8821a1ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8821a1ant_periodical(IN struct btc_coexist *btcoexist) -{ -#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 0) - halbtc8821a1ant_query_bt_info(btcoexist); - halbtc8821a1ant_monitor_bt_ctr(btcoexist); - halbtc8821a1ant_monitor_bt_enable_disable(btcoexist); -#else - if (halbtc8821a1ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust) { - /* if(coex_sta->specific_pkt_period_cnt > 2) */ - /* { */ - halbtc8821a1ant_run_coexist_mechanism(btcoexist); - /* } */ - } - - coex_sta->specific_pkt_period_cnt++; -#endif -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ - diff --git a/hal/btc/HalBtc8821a1Ant.h b/hal/btc/HalBtc8821a1Ant.h deleted file mode 100644 index 6c9c327..0000000 --- a/hal/btc/HalBtc8821a1Ant.h +++ /dev/null @@ -1,197 +0,0 @@ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821A_SUPPORT == 1) - -/* ******************************************* - * The following is for 8821A 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8821A_1ANT 1 - -#define BT_INFO_8821A_1ANT_B_FTP BIT(7) -#define BT_INFO_8821A_1ANT_B_A2DP BIT(6) -#define BT_INFO_8821A_1ANT_B_HID BIT(5) -#define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8821A_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT 2 - -enum bt_info_src_8821a_1ant { - BT_INFO_SRC_8821A_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8821A_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8821A_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8821A_1ANT_MAX -}; - -enum bt_8821a_1ant_bt_status { - BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8821A_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8821A_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8821A_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8821A_1ANT_BT_STATUS_MAX -}; - -enum bt_8821a_1ant_wifi_status { - BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8821A_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8821a_1ant_coex_algo { - BT_8821A_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8821A_1ANT_COEX_ALGO_SCO = 0x1, - BT_8821A_1ANT_COEX_ALGO_HID = 0x2, - BT_8821A_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8821A_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8821A_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8821A_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8821A_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8821A_1ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8821a_1ant { - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u8 error_condition; -}; - -struct coex_sta_8821a_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - u8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8821A_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8821A_1ANT_MAX]; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - u8 bt_retry_cnt; - u8 bt_info_ext; - boolean - bt_whck_test; /* Add for ASUS WHQL TEST that enable wifi test bt */ -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8821a1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8821a1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8821a1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a1ant_display_coex_info(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8821a1ant_power_on_setting(btcoexist) -#define ex_halbtc8821a1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8821a1ant_init_coex_dm(btcoexist) -#define ex_halbtc8821a1ant_ips_notify(btcoexist, type) -#define ex_halbtc8821a1ant_lps_notify(btcoexist, type) -#define ex_halbtc8821a1ant_scan_notify(btcoexist, type) -#define ex_halbtc8821a1ant_connect_notify(btcoexist, type) -#define ex_halbtc8821a1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8821a1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8821a1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8821a1ant_halt_notify(btcoexist) -#define ex_halbtc8821a1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8821a1ant_periodical(btcoexist) -#define ex_halbtc8821a1ant_display_coex_info(btcoexist) - -#endif - -#endif diff --git a/hal/btc/HalBtc8821a2Ant.c b/hal/btc/HalBtc8821a2Ant.c deleted file mode 100644 index 010a422..0000000 --- a/hal/btc/HalBtc8821a2Ant.c +++ /dev/null @@ -1,4560 +0,0 @@ -/* ************************************************************ - * Description: - * - * This file is for RTL8821A Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "Mp_Precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821A_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8821a_2ant glcoex_dm_8821a_2ant; -static struct coex_dm_8821a_2ant *coex_dm = &glcoex_dm_8821a_2ant; -static struct coex_sta_8821a_2ant glcoex_sta_8821a_2ant; -static struct coex_sta_8821a_2ant *coex_sta = &glcoex_sta_8821a_2ant; - -const char *const glbt_info_src_8821a_2ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8821a_2ant = 20150921; -u32 glcoex_ver_8821a_2ant = 0x58; -/* modify 20140903v43 a2dpandhid tdmaonoff a2dp glitch _ tdma off 778=3(case1)->778=1(case0) - * and to improve tp while a2dphid case23->case25 , case123->case125 for asus spec - * and modify for asus bt WHQL test _ tdma off_ 778=3->1_ - * ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8821a2ant_ - * ************************************************************ */ -u8 halbtc8821a2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8821a2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8821a2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - BTC_TRACE(trace_buf); - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 2) { - bt_disabled = true; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - BTC_TRACE(trace_buf); - } - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - if (!bt_disabled) { - } else { - } - } -} - -void halbtc8821a2ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); -} - -void halbtc8821a2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if ((coex_sta->low_priority_rx >= 950) && - (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) && - (!coex_sta->under_ips)) - bt_link_info->slave_role = true; - else - bt_link_info->slave_role = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); -} - -void halbtc8821a2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ - if (coex_sta->under_ips) { - coex_sta->crc_ok_cck = 0; - coex_sta->crc_ok_11g = 0; - coex_sta->crc_ok_11n = 0; - coex_sta->crc_ok_11n_agg = 0; - - coex_sta->crc_err_cck = 0; - coex_sta->crc_err_11g = 0; - coex_sta->crc_err_11n = 0; - coex_sta->crc_err_11n_agg = 0; - } else { - coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf88); - coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf94); - coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf90); - coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfb8); - - coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf84); - coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf96); - coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf92); - coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfba); - } - - /* reset counter */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0); -} - -void halbtc8821a2ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -boolean halbtc8821a2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 3, - 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - - if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) || - (BTC_RSSI_STATE_LOW == wifi_rssi_state)) - return true; - - } - - return false; -} - -void halbtc8821a2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8821a2ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8821A_2ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_HID_A2DP; - } - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(HS) ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(EDR) ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } - } - } - } - - return algorithm; -} - -void halbtc8821a2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - -void halbtc8821a2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN u8 dec_bt_pwr_lvl) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = dec_bt_pwr_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); -} - -void halbtc8821a2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 dec_bt_pwr_lvl) -{ - coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; - - if (!force_exec) { - if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) - return; - } - halbtc8821a2ant_set_fw_dec_bt_pwr(btcoexist, - coex_dm->cur_bt_dec_pwr_lvl); - - coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; -} - -void halbtc8821a2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8821a2ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8821a2ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8821a2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8821a2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - -void halbtc8821a2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist, - IN boolean rx_rf_shrink_on) -{ - if (rx_rf_shrink_on) { - /* Shrink RF Rx LPF corner */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Shrink RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, - 0xffffc); - } else { - /* Resume RF Rx LPF corner */ - /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ - if (btcoexist->initilized) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Resume RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, coex_dm->bt_rf_0x1e_backup); - } - } -} - -void halbtc8821a2ant_rf_shrink(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rx_rf_shrink_on) -{ - coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; - - if (!force_exec) { - if (coex_dm->pre_rf_rx_lpf_shrink == - coex_dm->cur_rf_rx_lpf_shrink) - return; - } - halbtc8821a2ant_set_sw_rf_rx_lpf_corner(btcoexist, - coex_dm->cur_rf_rx_lpf_shrink); - - coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; -} - -void halbtc8821a2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf5; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xa0; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xa0; /* MCS5 or OFDM36 */ - /* h2c_parameter[3] = 0xf7; //MCS7 or OFDM54 */ - /* h2c_parameter[4] = 0xf8; //MCS6 or OFDM48 */ - /* h2c_parameter[5] = 0xf9; //MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8821a2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8821a2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8821a2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, - IN u32 level) -{ - u8 val = (u8)level; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Write SwDacSwing = 0x%x\n", level); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val); -} - -void halbtc8821a2ant_set_sw_full_time_dac_swing(IN struct btc_coexist - *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) -{ - if (sw_dac_swing_on) - halbtc8821a2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl); - else - halbtc8821a2ant_set_dac_swing_reg(btcoexist, 0x18); -} - - -void halbtc8821a2ant_dac_swing(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) -{ - coex_dm->cur_dac_swing_on = dac_swing_on; - coex_dm->cur_dac_swing_lvl = dac_swing_lvl; - - if (!force_exec) { - if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && - (coex_dm->pre_dac_swing_lvl == - coex_dm->cur_dac_swing_lvl)) - return; - } - delay_ms(30); - halbtc8821a2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, - dac_swing_lvl); - - coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; - coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; -} - -void halbtc8821a2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean adc_back_off) -{ - if (adc_back_off) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1); - } -} - -void halbtc8821a2ant_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean adc_back_off) -{ - coex_dm->cur_adc_back_off = adc_back_off; - - if (!force_exec) { - if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) - return; - } - halbtc8821a2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off); - - coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; -} - -void halbtc8821a2ant_set_agc_table(IN struct btc_coexist *btcoexist, - IN boolean agc_table_en) -{ - u8 rssi_adjust_val = 0; - - /* =================BB AGC Gain Table */ - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6e1A0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6d1B0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6c1C0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6b1D0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6a1E0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x691F0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x68200001); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa4200001); - } - - - /* =================RF Gain */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x38fff); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x38ffe); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x380c3); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x28ce6); - } - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x1); - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x38fff); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x38ffe); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x380c3); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x28ce6); - } - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x0); - - /* set rssi_adjust_val for wifi module. */ - if (agc_table_en) - rssi_adjust_val = 8; - btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, - &rssi_adjust_val); -} - -void halbtc8821a2ant_agc_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean agc_table_en) -{ - coex_dm->cur_agc_table_en = agc_table_en; - - if (!force_exec) { - if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) - return; - } - halbtc8821a2ant_set_agc_table(btcoexist, agc_table_en); - - coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; -} - -void halbtc8821a2ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8821a2ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8821a2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8821a2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_sta->coex_table_type = type; - - switch (type) { - case 0: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, 0xffffff, 0x3); - break; - case 1: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5afa5afa, 0xffffff, 0x3); - break; - case 2: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3); - break; - case 3: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 4: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0xffffffff, 0xffffffff, 0xffffff, 0x3); - break; - case 5: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3); - break; - case 6: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 7: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 8: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 9: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 10: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 11: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 12: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 13: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 14: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); - break; - case 15: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 16: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3); - break; - case 17: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0xfafafafa, 0xfafafafa, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8821a2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8821a2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8821a2ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8821a2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8821a2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8821a2ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8821a2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - - h2c_parameter[0] = byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = byte5; - - coex_dm->ps_tdma_para[0] = byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8821a2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, - IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, - IN boolean limited_dig, IN boolean bt_lna_constrain) -{ - /* - u32 wifi_bw; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if(BTC_WIFI_BW_HT40 != wifi_bw) - { - if (shrink_rx_lpf) - shrink_rx_lpf = false; - } - */ - - /* halbtc8821a2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); */ - halbtc8821a2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8821a2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, - IN boolean agc_table_shift, IN boolean adc_back_off, - IN boolean sw_dac_swing, IN u32 dac_swing_lvl) -{ - /* halbtc8821a2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */ - /* halbtc8821a2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */ - halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, - dac_swing_lvl); -} - -void halbtc8821a2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u32 u32tmp = 0; - u8 h2c_parameter[2] = {0}; - - if (init_hwcfg) { - /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp |= BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - - btcoexist->btc_write_4byte(btcoexist, 0x974, 0x3ff); - /* btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77); */ - - if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { - /* tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ - h2c_parameter[0] = 1; - h2c_parameter[1] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } else { - /* tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ - h2c_parameter[0] = 0; - h2c_parameter[1] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } - } - - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_WIFI_AT_MAIN: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, 0x1); - break; - case BTC_ANT_WIFI_AT_AUX: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, 0x2); - break; - } -} - -void halbtc8821a2ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - u8 wifi_rssi_state1, bt_rssi_state; - - - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - if (!(BTC_RSSI_HIGH(wifi_rssi_state1) && - BTC_RSSI_HIGH(bt_rssi_state)) && turn_on) { - type = type + 100; /* for WiFi RSSI low or BT RSSI low */ - } - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - if (turn_on) { - switch (type) { - case 1: - default: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0xf1, 0x90); - break; - case 2: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d, 0x03, 0xf1, 0x90); - break; - case 3: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, 0x90); - break; - case 4: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x03, 0xf1, 0x90); - break; - case 5: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x3, 0x70, 0x90); - break; - case 6: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d, 0x3, 0x70, 0x90); - break; - case 7: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0x70, 0x90); - break; - case 8: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xa3, - 0x10, 0x3, 0x70, 0x90); - break; - case 9: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0xf1, 0x90); - break; - case 10: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d, 0x03, 0xf1, 0x90); - break; - case 11: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0xa, 0xa, 0xe1, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, 0x90); - break; - case 12: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0xf1, 0x90); - break; - case 13: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x3, 0x70, 0x90); - break; - case 14: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d, 0x3, 0x70, 0x90); - break; - case 15: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0xa, 0xa, 0x60, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0x70, 0x90); - break; - case 16: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, 0x60, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0x70, 0x90); - break; - case 17: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xa3, - 0x2f, 0x2f, 0x60, 0x90); - break; - case 18: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x5, 0x5, 0xe1, 0x90); - break; - case 19: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0xe1, 0x90); - break; - case 20: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0x60, 0x90); - break; - case 21: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x03, 0x70, 0x90); - break; - case 23: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1e, 0x03, 0xf0, 0x14); - break; - case 24: - case 124: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x3c, 0x03, 0x70, 0x50); - break; - /* case25/case125 : for lenovo bt pan tp degrade<30% while wifi downlink */ - case 25: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x14, 0x03, 0xf1, 0x90); - break; - case 26: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x30, 0x03, 0xf1, 0x90); - break; - case 71: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */ - - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0xf1, 0x90); - break; - case 101: - case 105: - case 171: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x3a, 0x03, 0x70, 0x50); - break; - case 102: - case 106: - case 110: - case 114: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x2d, 0x03, 0x70, 0x50); - break; - case 103: - case 107: - case 111: - case 115: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1c, 0x03, 0x70, 0x50); - break; - case 104: - case 108: - case 112: - case 116: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x10, 0x03, 0x70, 0x50); - break; - case 109: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0xf1, 0x90); - break; - case 113: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0x70, 0x90); - break; - case 121: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x03, 0x70, 0x90); - break; - case 22: - case 122: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x03, 0x71, 0x11); - break; - case 123: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1c, 0x03, 0x70, 0x54); - break; - /* case25/case125 : for lenovo bt pan tp degrade<30% while wifi downlink */ - case 125: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x14, 0x03, 0x70, 0x50); - break; - case 126: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x30, 0x03, 0x70, 0x50); - break; - } - } else { - /* disable PS tdma */ - switch (type) { - case 0: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - case 1: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - default: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8821a2ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8821a2ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8821a2ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8821a2ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8821a2ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - - -void halbtc8821a2ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* fw all off */ - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8821a2ant_coex_under_5g(IN struct btc_coexist *btcoexist) -{ - halbtc8821a2ant_coex_all_off(btcoexist); - - halbtc8821a2ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true); -} - -void halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0); - - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - -void halbtc8821a2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - boolean wifi_connected = false; - boolean low_pwr_disable = true; - boolean scan = false, link = false, roam = false; - - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - if (scan || link || roam) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link process + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 15); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - } else if (wifi_connected) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 15); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi no-link + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - } - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - -} - - -void halbtc8821a2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist) -{ - u8 u8tmpa, u8tmpb; - - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 15); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - - - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa, - u8tmpb); - BTC_TRACE(trace_buf); -} - -boolean halbtc8821a2ant_action_wifi_idle_process(IN struct btc_coexist - *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u8 ap_num = 0; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - /* wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); */ - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES - 20, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); - - /* define the office environment */ - if (BTC_RSSI_HIGH(wifi_rssi_state1) && - (coex_sta->hid_exist == true) && - (coex_sta->a2dp_exist == true)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi idle process for BT HID+A2DP exist!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - return true; - } - - /* */ - else if (coex_sta->pan_exist == true) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi idle process for BT PAN exist!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - return true; - } - - else { - halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x18); - return false; - } - - -} - - - -boolean halbtc8821a2ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - boolean bt_hs_on = false, low_pwr_disable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non-connected idle!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - common = true; - } else { - if (BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, - false, false, 0x8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - halbtc8821a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 0xb); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else if (BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status) { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (bt_hs_on) - return false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, - false, false, 0x8); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - halbtc8821a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 0xb); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - common = false; - /* common = halbtc8821a2ant_action_wifi_idle_process(btcoexist); */ - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - /* common = false; */ - common = halbtc8821a2ant_action_wifi_idle_process( - btcoexist); - } - } - } - - return common; -} -void halbtc8821a2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, - IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0; - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - { - if (sco_hid) { - if (tx_pause) { - if (max_interval == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } else if (max_interval == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (max_interval == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } else { - if (max_interval == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } else if (max_interval == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (max_interval == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } else { - if (tx_pause) { - if (max_interval == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (max_interval == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (max_interval == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } - } else { - if (max_interval == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (max_interval == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (max_interval == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } - } - } - } - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* accquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration */ - if (wait_count <= 2) - m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ - else - m = 1; - - if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration */ - if (wait_count == 1) - m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ - else - m = 1; - - if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (max_interval == 1) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 13); - coex_dm->ps_tdma_du_adj_type = 13; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 71); - coex_dm->ps_tdma_du_adj_type = 71; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 71); - coex_dm->ps_tdma_du_adj_type = - 71; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } - } - } - } else if (max_interval == 2) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } - } - } - } else if (max_interval == 3) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } - } - } - - /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ - /* then we have to adjust it back to the previous record one. */ - if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { - boolean scan = false, link = false, roam = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", - coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (!scan && !link && !roam) - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); - BTC_TRACE(trace_buf); - } - } -} - -/* SCO only or SCO+PAN(HS) */ -void halbtc8821a2ant_action_sco(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 wifi_rssi_state, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for SCO quality at 11b/g mode */ - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else { /* for SCO quality & wifi performance balance at 11n mode */ - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8821a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else { - if (bt_link_info->sco_only) - halbtc8821a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 17); - else - halbtc8821a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 12); - } - } - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); /* for voice quality */ - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - true, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - true, 0x18); - } - } -} - - -void halbtc8821a2ant_action_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */ - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - else /* for HID quality & wifi performance balance at 11n mode */ - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 24); - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8821a2ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - u8 ap_num = 0; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); - - /* define the office environment */ - if ((ap_num >= 10) && BTC_RSSI_HIGH(wifi_rssi_state1) && - BTC_RSSI_HIGH(bt_rssi_state)) { - /* dbg_print(" AP#>10(%d)\n", ap_num); */ - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - /* halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } - return; - - } - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, false, 1); */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - } else { - /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 1); */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - } - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8821a2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 2); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8821a2ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 10); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 26); - else - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 26); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - - -/* PAN(HS) only */ -void halbtc8821a2ant_action_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* PAN(EDR)+A2DP */ -void halbtc8821a2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 12); - - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, - true, 3); - else - halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, - false, 3); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 3); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8821a2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 14); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (BTC_WIFI_BW_HT40 == wifi_bw) { - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 3); - /* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x780); - } else { - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 6); - /* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - } - halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, false, 2); - } else { - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - /* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 2); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* HID+A2DP+PAN(EDR) */ -void halbtc8821a2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 14); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, - true, 3); - else - halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, - false, 3); - } else - halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 3); - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8821a2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - u8 ap_num = 0; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - /* bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, 29, 0); */ - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(3, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 37); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x5); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_LEGACY == wifi_bw) { - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - } else { - /* only 802.11N mode we have to dec bt power to 4 degree */ - if (BTC_RSSI_HIGH(bt_rssi_state)) { - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &ap_num); - /* need to check ap Number of Not */ - if (ap_num < 10) - halbtc8821a2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, 4); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, 2); - } else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - } - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 14); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, false, 3); */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - } else { - /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 3); */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8821a2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) -{ - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8821a2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); -} - -void halbtc8821a2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - boolean wifi_under_5g = false; - u8 algorithm = 0; - u32 num_of_wifi_link = 0; - u32 wifi_link_status = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean miracast_plus_bt = false; - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_coex_under_5g(btcoexist); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_bt_whck_test(btcoexist); - return; - } - - algorithm = halbtc8821a2ant_action_algorithm(btcoexist); - if (coex_sta->c2h_bt_inquiry_page && - (BT_8821A_2ANT_COEX_ALGO_PANHS != algorithm)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_bt_inquiry(btcoexist); - return; - } else { - - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under Link Process !!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_wifi_link_process(btcoexist); - return; - } - - /* for P2P */ - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) - miracast_plus_bt = true; - else - miracast_plus_bt = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8821a2ant_action_wifi_multi_port(btcoexist); - - return; - } else { - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - coex_dm->cur_algorithm = algorithm; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", - coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - - if (halbtc8821a2ant_is_common_action(btcoexist)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant common.\n"); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - } else { - if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", - coex_dm->pre_algorithm, coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - } - switch (coex_dm->cur_algorithm) { - case BT_8821A_2ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_sco(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_hid(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_a2dp(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_pan_edr(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_pan_hs(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_pan_edr_hid(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_hid_a2dp(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_coex_all_off(btcoexist); - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8821a2ant_wifi_off_hw_cfg(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[2] = {0}; - u32 fw_ver = 0; - - /* set wlan_act to low */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x780); /* WiFi goto standby while GNT_BT 0-->1 */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - if (fw_ver >= 0x180000) { - /* Use H2C to set GNT_BT to HIGH */ - h2c_parameter[0] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, h2c_parameter); - } else - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); -} - -void halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up) -{ - u8 u8tmp = 0; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - /* backup rf 0x1e value */ - coex_dm->bt_rf_0x1e_backup = - btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff); - - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* Antenna config */ - halbtc8821a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true, - false); - coex_sta->dis_ver_info_cnt = 0; - - /* PTA parameter */ - halbtc8821a2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - /* Enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, - 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); -} - -/* ************************************************************ - * work around function start with wa_halbtc8821a2ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8821a2ant_ - * ************************************************************ */ -void ex_halbtc8821a2ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - -} - -void ex_halbtc8821a2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - if (btcoexist->chip_interface == BTC_INTF_USB) { - /* fixed at S0 for USB interface */ - u8tmp |= 0x1; /* antenna inverse */ - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - } else { - /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ - if (board_info->single_ant_path == 0) { - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - u8tmp |= 0x1; /* antenna inverse */ - } - - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384, - u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, - u8tmp); - } -} - -void ex_halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8821a2ant_init_hw_config(btcoexist, true); -} - -void ex_halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821a2ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8821a2ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u32 u32tmp[4]; - u32 fa_of_dm, fa_cck; - u32 fw_ver = 0, bt_patch_ver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)", - "CoexVer/ FwVer/ PatchVer", - glcoex_ver_date_8821a_2ant, glcoex_ver_8821a_2ant, fw_ver, - bt_patch_ver, bt_patch_ver); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %ddBm/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", - "SCO/HID/PAN/A2DP", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist); - CL_PRINTF(cli_buf); - - { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Role", - (bt_link_info->slave_role) ? "Slave" : "Master"); - CL_PRINTF(cli_buf); - } - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8821A_2ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8821a_2ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - /* Sw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Sw mechanism]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", - "SM1[ShRf/ LpRA/ LimDig]", - coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, - coex_dm->limited_dig); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", - "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", - coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, - coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); - CL_PRINTF(cli_buf); - - /* Fw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Fw mechanism]============"); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - coex_dm->auto_tdma_adjust); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Coex Table Type", - coex_sta->coex_table_type); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "DecBtPwr/ IgnWlanAct", - coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", - "RF-A, 0x1e initVal", - coex_dm->bt_rf_0x1e_backup); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xc5b); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x880); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x778/0x880[29:25]/0xc58[29:25]", - u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25, - ((u8tmp[1] & 0x3e) >> 1)); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x764); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x76e); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x764/ 0x765/ 0x76e", - (u32tmp[0] & 0xff), (u32tmp[0] & 0xff00) >> 8, u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xcb4[7:0](ctrl)/ 0xcb4[29:28](val)", - u32tmp[0] & 0xff, ((u32tmp[0] & 0x30000000) >> 28)); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x974); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x40/ 0x4c[24:23]/ 0x974", - u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u32tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xc50(dig)/0x49c(null-drop)", - u32tmp[0] & 0xff, u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8); - u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c); - - fa_of_dm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000) - >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) + \ - ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] & - 0xffff) ; - fa_cck = (u8tmp[0] << 8) + u8tmp[1]; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "OFDM-CCA/OFDM-FA/CCK-FA", - u32tmp[0] & 0xffff, fa_of_dm, fa_cck); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-Agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-Agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 1) - /* halbtc8821a2ant_monitor_bt_ctr(btcoexist); */ -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8821a2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - halbtc8821a2ant_wifi_off_hw_cfg(btcoexist); - halbtc8821a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - halbtc8821a2ant_coex_all_off(btcoexist); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; - halbtc8821a2ant_init_hw_config(btcoexist, false); - halbtc8821a2ant_init_coex_dm(btcoexist); - halbtc8821a2ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8821a2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8821a2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 u8tmpa, u8tmpb; - - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - if (BTC_SCAN_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_SCAN_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa, - u8tmpb); - BTC_TRACE(trace_buf); -} - -void ex_halbtc8821a2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_ASSOCIATE_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_ASSOCIATE_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8821a2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - u8 ap_num = 0; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = 0x1; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else { - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &ap_num); - if (ap_num < 10) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); -} - -void ex_halbtc8821a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (type == BTC_PACKET_DHCP) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], DHCP Packet notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8821a2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean bt_busy = false, limited_dig = false; - boolean wifi_connected = false, wifi_under_5g = false; - - coex_sta->c2h_bt_info_req_sent = false; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8821A_2ANT_MAX) - rsp_source = BT_INFO_SRC_8821A_2ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n"); - BTC_TRACE(trace_buf); - return; - } - - /* if 0xff, it means BT is under WHCK test */ - if (bt_info == 0xff) - coex_sta->bt_whck_test = true; - else - coex_sta->bt_whck_test = false; - - if (BT_INFO_SRC_8821A_2ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] - & 0x40); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, - &coex_sta->bt_tx_rx_mask); - if (coex_sta->bt_tx_rx_mask) { - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x3c, 0x01); - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - if (wifi_connected) - ex_halbtc8821a2ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8821a2ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - - if (!btcoexist->manual_control && !wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info = 0x%x!!\n", - coex_sta->bt_info_ext); - BTC_TRACE(trace_buf); - if ((coex_sta->bt_info_ext & BIT(3))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3=1, wifi_connected=%d\n", - wifi_connected); - BTC_TRACE(trace_buf); - if (wifi_connected) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_ignore_wlan_act( - btcoexist, FORCE_EXEC, false); - } - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3=0, wifi_connected=%d\n", - wifi_connected); - BTC_TRACE(trace_buf); - /* BT already NOT ignore Wlan active, do nothing here. */ - if (!wifi_connected) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_ignore_wlan_act( - btcoexist, FORCE_EXEC, true); - } - } - } - -#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8821a2ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8821A_2ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8821A_2ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8821A_2ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8821A_2ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8821A_2ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8821A_2ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - - if ((coex_sta->hid_exist == false) && - (coex_sta->c2h_bt_inquiry_page == false) && - (coex_sta->sco_exist == false)) { - if (coex_sta->high_priority_tx + - coex_sta->high_priority_rx >= 160) - coex_sta->hid_exist = true; - } - } - - halbtc8821a2ant_update_bt_link_info(btcoexist); - - if (!(bt_info & BT_INFO_8821A_2ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8821A_2ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8821A_2ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8821A_2ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8821A_2ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8821A_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8821A_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { - bt_busy = true; - limited_dig = true; - } else { - bt_busy = false; - limited_dig = false; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - coex_dm->limited_dig = limited_dig; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); - - halbtc8821a2ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8821a2ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821a2ant_wifi_off_hw_cfg(btcoexist); - /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */ - /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); //BT goto standby while GNT_BT 1-->0 */ - halbtc8821a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8821a2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); -} - -void ex_halbtc8821a2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_init_hw_config(btcoexist, false); - halbtc8821a2ant_init_coex_dm(btcoexist); - halbtc8821a2ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8821a2ant_periodical(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ==========================Periodical===========================\n"); - BTC_TRACE(trace_buf); - - if (coex_sta->dis_ver_info_cnt <= 5) { - coex_sta->dis_ver_info_cnt += 1; - if (coex_sta->dis_ver_info_cnt == 3) { - /* Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set GNT_BT control by PTA\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_set_ant_path(btcoexist, - BTC_ANT_WIFI_AT_MAIN, false, false); - } - } - -#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 0) - halbtc8821a2ant_query_bt_info(btcoexist); - halbtc8821a2ant_monitor_bt_enable_disable(btcoexist); -#else - halbtc8821a2ant_monitor_bt_ctr(btcoexist); - halbtc8821a2ant_monitor_wifi_ctr(btcoexist); - - if (halbtc8821a2ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust) - halbtc8821a2ant_run_coexist_mechanism(btcoexist); -#endif -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ \ No newline at end of file diff --git a/hal/btc/HalBtc8821a2Ant.h b/hal/btc/HalBtc8821a2Ant.h deleted file mode 100644 index 73252dd..0000000 --- a/hal/btc/HalBtc8821a2Ant.h +++ /dev/null @@ -1,205 +0,0 @@ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821A_SUPPORT == 1) - -/* ******************************************* - * The following is for 8821A 2Ant BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8821A_2ANT 1 - - -#define BT_INFO_8821A_2ANT_B_FTP BIT(7) -#define BT_INFO_8821A_2ANT_B_A2DP BIT(6) -#define BT_INFO_8821A_2ANT_B_HID BIT(5) -#define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8821A_2ANT_B_CONNECTION BIT(0) - -#define BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT 2 - - -#define BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 /* WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */ -#define BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES 46 /* BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */ - -enum bt_info_src_8821a_2ant { - BT_INFO_SRC_8821A_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8821A_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8821A_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8821A_2ANT_MAX -}; - -enum bt_8821a_2ant_bt_status { - BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8821A_2ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8821A_2ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8821A_2ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8821A_2ANT_BT_STATUS_MAX -}; - -enum bt_8821a_2ant_coex_algo { - BT_8821A_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8821A_2ANT_COEX_ALGO_SCO = 0x1, - BT_8821A_2ANT_COEX_ALGO_HID = 0x2, - BT_8821A_2ANT_COEX_ALGO_A2DP = 0x3, - BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8821A_2ANT_COEX_ALGO_PANEDR = 0x5, - BT_8821A_2ANT_COEX_ALGO_PANHS = 0x6, - BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8821A_2ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8821A_2ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8821A_2ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8821a_2ant { - /* fw mechanism */ - u8 pre_bt_dec_pwr_lvl; - u8 cur_bt_dec_pwr_lvl; - u8 pre_fw_dac_swing_lvl; - u8 cur_fw_dac_swing_lvl; - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean reset_tdma_adjust; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - - /* sw mechanism */ - boolean pre_rf_rx_lpf_shrink; - boolean cur_rf_rx_lpf_shrink; - u32 bt_rf_0x1e_backup; - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - boolean pre_dac_swing_on; - u32 pre_dac_swing_lvl; - boolean cur_dac_swing_on; - u32 cur_dac_swing_lvl; - boolean pre_adc_back_off; - boolean cur_adc_back_off; - boolean pre_agc_table_en; - boolean cur_agc_table_en; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - boolean need_recover0x948; - u32 backup0x948; - - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; -}; - -struct coex_sta_8821a_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - u8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8821A_2ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8821A_2ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - u8 bt_retry_cnt; - u8 bt_info_ext; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_agg; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_agg; - - u8 coex_table_type; - boolean force_lps_on; - - u8 dis_ver_info_cnt; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8821a2ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a2ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8821a2ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8821a2ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a2ant_display_coex_info(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8821a2ant_power_on_setting(btcoexist) -#define ex_halbtc8821a2ant_pre_load_firmware(btcoexist) -#define ex_halbtc8821a2ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8821a2ant_init_coex_dm(btcoexist) -#define ex_halbtc8821a2ant_ips_notify(btcoexist, type) -#define ex_halbtc8821a2ant_lps_notify(btcoexist, type) -#define ex_halbtc8821a2ant_scan_notify(btcoexist, type) -#define ex_halbtc8821a2ant_connect_notify(btcoexist, type) -#define ex_halbtc8821a2ant_media_status_notify(btcoexist, type) -#define ex_halbtc8821a2ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8821a2ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8821a2ant_halt_notify(btcoexist) -#define ex_halbtc8821a2ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8821a2ant_periodical(btcoexist) -#define ex_halbtc8821a2ant_display_coex_info(btcoexist) -#endif - -#endif diff --git a/hal/btc/HalBtc8821aCsr2Ant.c b/hal/btc/HalBtc8821aCsr2Ant.c deleted file mode 100644 index b69d156..0000000 --- a/hal/btc/HalBtc8821aCsr2Ant.c +++ /dev/null @@ -1,3997 +0,0 @@ -/* ************************************************************ - * Description: - * - * This file is for RTL8821A_CSR_CSR Co-exist mechanism - * - * History - * 2012/08/22 Cosa first check in. - * 2012/11/14 Cosa Revise for 8821A_CSR 2Ant out sourcing. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "Mp_Precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821A_SUPPORT == 1) - -#define _BTCOEX_CSR 1 - -#ifndef rtw_warn_on_8821acsr2ant -#define rtw_warn_on_8821acsr2ant(condition) do {} while (0) -#endif -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8821a_csr_2ant glcoex_dm_8821a_csr_2ant; -static struct coex_dm_8821a_csr_2ant *coex_dm = &glcoex_dm_8821a_csr_2ant; -static struct coex_sta_8821a_csr_2ant glcoex_sta_8821a_csr_2ant; -static struct coex_sta_8821a_csr_2ant *coex_sta = &glcoex_sta_8821a_csr_2ant; - -const char *const glbt_info_src_8821a_csr_2ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8821a_csr_2ant = 20140901; -u32 glcoex_ver_8821a_csr_2ant = 0x51; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8821aCsr2ant_ - * ************************************************************ */ -u8 halbtc8821aCsr2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, - u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8821aCsr2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8821aCsr2ant_monitor_bt_enable_disable(IN struct btc_coexist - *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - BTC_TRACE(trace_buf); - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 2) { - bt_disabled = true; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - BTC_TRACE(trace_buf); - } - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - if (!bt_disabled) { - } else { - } - } -} - -void halbtc8821aCsr2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x5d); -} - -void halbtc8821aCsr2ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8821aCsr2ant_auto_rate_fallback_retry(IN struct btc_coexist - *btcoexist, IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8821aCsr2ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8821aCsr2ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - case 2: - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x17); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8821aCsr2Ant_AmpduMaxNum(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_num_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_num_type != coex_dm->cur_ampdu_num_type)) { - switch (coex_dm->cur_ampdu_num_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x4ca, - coex_dm->backup_ampdu_max_num); - break; - case 1: - btcoexist->btc_write_2byte(btcoexist, 0x4ca, - 0x0808); - break; - case 2: - btcoexist->btc_write_2byte(btcoexist, 0x4ca, - 0x1f1f); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_num_type = coex_dm->cur_ampdu_num_type; - -} - -void halbtc8821aCsr2ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type, IN u8 ampdu_num_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8821aCsr2ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8821aCsr2ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8821aCsr2ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8821aCsr2ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8821aCsr2ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8821aCsr2ant_ampdu_max_time(btcoexist, force_exec, - ampdu_time_type); - halbtc8821aCsr2Ant_AmpduMaxNum(btcoexist, force_exec, ampdu_num_type); -} - - - -void halbtc8821aCsr2ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); -} - -void halbtc8821aCsr2ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - rtw_warn_on_8821acsr2ant(_BTCOEX_CSR); - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -u8 halbtc8821aCsr2ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_stack_info *stack_info = &btcoexist->stack_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - /* sync StackInfo with BT firmware and stack */ - stack_info->hid_exist = coex_sta->hid_exist; - stack_info->bt_link_exist = coex_sta->bt_link_exist; - stack_info->sco_exist = coex_sta->sco_exist; - stack_info->pan_exist = coex_sta->pan_exist; - stack_info->a2dp_exist = coex_sta->a2dp_exist; - - if (!stack_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No profile exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (stack_info->sco_exist) - num_of_diff_profile++; - if (stack_info->hid_exist) - num_of_diff_profile++; - if (stack_info->pan_exist) - num_of_diff_profile++; - if (stack_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (stack_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_SCO; - } else { - if (stack_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_HID; - } else if (stack_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_A2DP; - } else if (stack_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (stack_info->sco_exist) { - if (stack_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; - } else if (stack_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; - } else if (stack_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (stack_info->hid_exist && - stack_info->a2dp_exist) { - if (stack_info->num_of_hid >= 2) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID*2 + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP; - } - } else if (stack_info->hid_exist && - stack_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (stack_info->pan_exist && - stack_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (stack_info->sco_exist) { - if (stack_info->hid_exist && - stack_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; - } else if (stack_info->hid_exist && - stack_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (stack_info->pan_exist && - stack_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (stack_info->hid_exist && - stack_info->pan_exist && - stack_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (stack_info->sco_exist) { - if (stack_info->hid_exist && - stack_info->pan_exist && - stack_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -boolean halbtc8821aCsr2ant_need_to_dec_bt_pwr(IN struct btc_coexist *btcoexist) -{ - boolean ret = false; - boolean bt_hs_on = false, wifi_connected = false; - s32 bt_hs_rssi = 0; - u8 bt_rssi_state; - - if (!btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on)) - return false; - if (!btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected)) - return false; - if (!btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi)) - return false; - - bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0); - - if (wifi_connected) { - if (bt_hs_on) { - if (bt_hs_rssi > 37) - ret = true; - } else { - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - ret = true; - } - } - - return ret; -} - -void halbtc8821aCsr2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - -void halbtc8821aCsr2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean dec_bt_pwr) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (dec_bt_pwr) - h2c_parameter[0] |= BIT(1); - - rtw_warn_on_8821acsr2ant(_BTCOEX_CSR); - btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); -} - -void halbtc8821aCsr2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean dec_bt_pwr) -{ - coex_dm->cur_dec_bt_pwr = dec_bt_pwr; - - if (!force_exec) { - if (coex_dm->pre_dec_bt_pwr == coex_dm->cur_dec_bt_pwr) - return; - } - - /* TODO: may CSR consider to decrease BT power? */ - /* halbtc8821aCsr2ant_set_fw_dec_bt_pwr(btcoexist, coex_dm->cur_dec_bt_pwr); */ - - coex_dm->pre_dec_bt_pwr = coex_dm->cur_dec_bt_pwr; -} - -void halbtc8821aCsr2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - rtw_warn_on_8821acsr2ant(_BTCOEX_CSR); - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8821aCsr2ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - /* halbtc8821aCsr2ant_set_bt_auto_report(btcoexist, coex_dm->cur_bt_auto_report); */ - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8821aCsr2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8821aCsr2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - -void halbtc8821aCsr2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist - *btcoexist, IN boolean rx_rf_shrink_on) -{ - if (rx_rf_shrink_on) { - /* Shrink RF Rx LPF corner */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Shrink RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, - 0xffffc); - } else { - /* Resume RF Rx LPF corner */ - /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ - if (btcoexist->initilized) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Resume RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, coex_dm->bt_rf_0x1e_backup); - } - } -} - -void halbtc8821aCsr2ant_rf_shrink(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rx_rf_shrink_on) -{ - coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; - - if (!force_exec) { - if (coex_dm->pre_rf_rx_lpf_shrink == - coex_dm->cur_rf_rx_lpf_shrink) - return; - } - halbtc8821aCsr2ant_set_sw_rf_rx_lpf_corner(btcoexist, - coex_dm->cur_rf_rx_lpf_shrink); - - coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; -} - -void halbtc8821aCsr2ant_set_sw_penalty_tx_rate_adaptive( - IN struct btc_coexist *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8821aCsr2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8821aCsr2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8821aCsr2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, - IN u32 level) -{ - u8 val = (u8)level; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Write SwDacSwing = 0x%x\n", level); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val); -} - -void halbtc8821aCsr2ant_set_sw_full_time_dac_swing(IN struct btc_coexist - *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) -{ - if (sw_dac_swing_on) - halbtc8821aCsr2ant_set_dac_swing_reg(btcoexist, - sw_dac_swing_lvl); - else - halbtc8821aCsr2ant_set_dac_swing_reg(btcoexist, 0x18); -} - - -void halbtc8821aCsr2ant_dac_swing(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) -{ - coex_dm->cur_dac_swing_on = dac_swing_on; - coex_dm->cur_dac_swing_lvl = dac_swing_lvl; - - if (!force_exec) { - if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && - (coex_dm->pre_dac_swing_lvl == - coex_dm->cur_dac_swing_lvl)) - return; - } - delay_ms(30); - halbtc8821aCsr2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, - dac_swing_lvl); - - coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; - coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; -} - -void halbtc8821aCsr2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean adc_back_off) -{ - if (adc_back_off) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1); - } -} - -void halbtc8821aCsr2ant_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean adc_back_off) -{ - coex_dm->cur_adc_back_off = adc_back_off; - - if (!force_exec) { - if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) - return; - } - halbtc8821aCsr2ant_set_adc_back_off(btcoexist, - coex_dm->cur_adc_back_off); - - coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; -} - -void halbtc8821aCsr2ant_set_agc_table(IN struct btc_coexist *btcoexist, - IN boolean agc_table_en) -{ - u8 rssi_adjust_val = 0; - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x28F4B); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x10AB2); - rssi_adjust_val = 8; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x2884B); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x104B2); - } - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); - - /* set rssi_adjust_val for wifi module. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, - &rssi_adjust_val); -} - -void halbtc8821aCsr2ant_agc_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean agc_table_en) -{ - coex_dm->cur_agc_table_en = agc_table_en; - - if (!force_exec) { - if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) - return; - } - halbtc8821aCsr2ant_set_agc_table(btcoexist, agc_table_en); - - coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; -} - -void halbtc8821aCsr2ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8821aCsr2ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8821aCsr2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, - val0x6c8, val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8821aCsr2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - rtw_warn_on_8821acsr2ant(_BTCOEX_CSR); - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8821aCsr2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - /* halbtc8821aCsr2ant_set_fw_ignore_wlan_act(btcoexist, enable); */ - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8821aCsr2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = byte5; - h2c_parameter[5] = 0x01; - - coex_dm->ps_tdma_para[0] = byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = byte5; - coex_dm->ps_tdma_para[5] = 0x01; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 6, h2c_parameter); -} - -void halbtc8821aCsr2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, - IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, - IN boolean limited_dig, IN boolean bt_lna_constrain) -{ - u32 wifi_bw; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_HT40 != wifi_bw) { /* only shrink RF Rx LPF for HT40 */ - if (shrink_rx_lpf) - shrink_rx_lpf = false; - } - - halbtc8821aCsr2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); - halbtc8821aCsr2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, - low_penalty_ra); - - /* no limited DIG */ - /* halbtc8821aCsr2ant_setBtLnaConstrain(btcoexist, NORMAL_EXEC, bt_lna_constrain); */ -} - -void halbtc8821aCsr2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, - IN boolean agc_table_shift, IN boolean adc_back_off, - IN boolean sw_dac_swing, IN u32 dac_swing_lvl) -{ - /* halbtc8821aCsr2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */ - halbtc8821aCsr2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); - halbtc8821aCsr2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, - dac_swing_lvl); -} - -void halbtc8821aCsr2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u32 u32tmp = 0; - u8 h2c_parameter[2] = {0}; - - if (init_hwcfg) { - /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp |= BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - - btcoexist->btc_write_4byte(btcoexist, 0x974, 0x3ff); - btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77); - - if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { - /* tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ - h2c_parameter[0] = 1; - h2c_parameter[1] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } else { - /* tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ - h2c_parameter[0] = 0; - h2c_parameter[1] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } - } - - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_WIFI_AT_MAIN: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, 0x1); - break; - case BTC_ANT_WIFI_AT_AUX: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, 0x2); - break; - } -} - -void halbtc8821aCsr2ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - if (turn_on) { - switch (type) { - case 1: - default: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x1a, 0x1a, 0xe1, 0x90); - break; - case 2: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x12, 0x12, 0xe1, 0x90); - break; - case 3: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x1c, 0x3, 0xf1, 0x90); - break; - case 4: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x10, 0x03, 0xf1, 0x90); - break; - case 5: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x1a, 0x1a, 0x60, 0x90); - break; - case 6: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x12, 0x12, 0x60, 0x90); - break; - case 7: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x1c, 0x3, 0x70, 0x90); - break; - case 8: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xa3, 0x10, 0x3, 0x70, 0x90); - break; - case 9: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x1a, 0x1a, 0xe1, 0x90); - break; - case 10: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x12, 0x12, 0xe1, 0x90); - break; - case 11: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0xa, 0xa, 0xe1, 0x90); - break; - case 12: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x5, 0x5, 0xe1, 0x90); - break; - case 13: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x1a, 0x1a, 0x60, 0x90); - break; - case 14: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x12, 0x12, 0x60, 0x90); - break; - case 15: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0xa, 0xa, 0x60, 0x90); - break; - case 16: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x5, 0x5, 0x60, 0x90); - break; - case 17: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xa3, 0x2f, 0x2f, 0x60, 0x90); - break; - case 18: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x5, 0x5, 0xe1, 0x90); - break; - case 19: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x25, 0x25, 0xe1, 0x90); - break; - case 20: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x25, 0x25, 0x60, 0x90); - break; - case 21: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x15, 0x03, 0x70, 0x90); - break; - case 22: /* ad2dp master */ - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xeb, 0x11, 0x11, 0x21, 0x10); - break; - case 23: /* a2dp slave */ - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xeb, 0x12, 0x12, 0x20, 0x10); - break; - case 71: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, - 0xe3, 0x1a, 0x1a, 0xe1, 0x90); - break; - } - } else { - /* disable PS tdma */ - switch (type) { - case 0: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - case 1: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - default: - halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8821aCsr2ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* fw all off */ - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - /* sw all off */ - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x55555555, - 0x55555555, 0xffff, 0x3); -} - -void halbtc8821aCsr2ant_coex_under_5g(IN struct btc_coexist *btcoexist) -{ - halbtc8821aCsr2ant_coex_all_off(btcoexist); - - halbtc8821aCsr2ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true); -} - -void halbtc8821aCsr2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - halbtc8821aCsr2ant_coex_table(btcoexist, FORCE_EXEC, 0x55555555, - 0x55555555, 0xffff, 0x3); - - halbtc8821aCsr2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, false); - - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - -void halbtc8821aCsr2ant_bt_inquiry_page(IN struct btc_coexist *btcoexist) -{ - boolean low_pwr_disable = true; - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x55ff55ff, - 0x5afa5afa, 0xffff, 0x3); - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); -} -boolean halbtc8821aCsr2ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - boolean low_pwr_disable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8821A_CSR_2ANT_BT_STATUS_IDLE == coex_dm->bt_status) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi IPS + BT IPS!!\n"); - BTC_TRACE(trace_buf); - - - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, - 0, 0); - halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, 0, 0, 0); - - common = true; - } else if (wifi_connected && - (BT_8821A_CSR_2ANT_BT_STATUS_IDLE == - coex_dm->bt_status)) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Busy + BT IPS!!\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, - false, 1); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi LPS + BT IPS!!\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, - false, 1); - } - - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, - 0, 0); - halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, 0, 0, 0); - - common = true; - } else if (!wifi_connected && - (BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi IPS + BT LPS!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, - 0, 0); - halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, 0, 0, 0); - - common = true; - } else if (wifi_connected && - (BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Busy + BT LPS!!\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, - false, 1); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi LPS + BT LPS!!\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, - false, 1); - } - - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true, true, - true); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, - 0, 0); - halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, 0, 0, 0); - - common = true; - } else if (!wifi_connected && - (BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE == - coex_dm->bt_status)) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi IPS + BT Busy!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); */ - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, - 0, 0); - halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, 0, 0, 0); - - common = true; - } else { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - common = false; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi LPS + BT Busy!!\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 21); - - if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist)) - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, true); - else - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, false); - - common = true; - } - - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true, true, - true); - } - - if (common == true) - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5afa5afa, 0xffff, 0x3); - - return common; -} -void halbtc8821aCsr2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, - IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0; - - if (coex_dm->reset_tdma_adjust) { - coex_dm->reset_tdma_adjust = false; - { - if (sco_hid) { - if (tx_pause) { - if (max_interval == 1) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } else if (max_interval == 2) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (max_interval == 3) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } else { - if (max_interval == 1) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } else if (max_interval == 2) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (max_interval == 3) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } else { - if (tx_pause) { - if (max_interval == 1) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (max_interval == 2) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (max_interval == 3) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } - } else { - if (max_interval == 1) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (max_interval == 2) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (max_interval == 3) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } - } - } - } - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* accquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration */ - if (wait_count <= 2) - m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ - else - m = 1; - - if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration */ - if (wait_count == 1) - m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ - else - m = 1; - - if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (max_interval == 1) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 13); - coex_dm->ps_tdma_du_adj_type = 13; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 71); - coex_dm->ps_tdma_du_adj_type = 71; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 71); - coex_dm->ps_tdma_du_adj_type = - 71; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } - } - } - } else if (max_interval == 2) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } - } - } - } else if (max_interval == 3) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821aCsr2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821aCsr2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } - } - } - - /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ - /* then we have to adjust it back to the previous record one. */ - if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { - boolean scan = false, link = false, roam = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", - coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (!scan && !link && !roam) - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); - BTC_TRACE(trace_buf); - } - } - - /* when halbtc8821aCsr2ant_tdma_duration_adjust() is called, fw dac swing is included in the function. */ - /* if(coex_dm->ps_tdma_du_adj_type == 71) */ - /* halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc); //Skip because A2DP get worse at HT40 */ - /* else */ - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 0x6); -} - -/* SCO only or SCO+PAN(HS) */ -void halbtc8821aCsr2ant_action_sco(IN struct btc_coexist *btcoexist) -{ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x55555555, - 0x55555555, 0xffffff, 0x3); - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - halbtc8821aCsr2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true); - - halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 1, 0, 2, 0); - - if (coex_sta->slave == false) - halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, false, - true, 0x4); - else - halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, false, - true, 0x2); - - /* - wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0); - bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0); - - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4); - - if(halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist)) - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true); - else - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) - { - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x5a5a5a5a, 0x5a5a5a5a, 0xffff, 0x3); - } - else - { - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x5aea5aea, 0x5aea5aea, 0xffff, 0x3); - } - - if(BTC_WIFI_BW_HT40 == wifi_bw) - { - - - - - if( (bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } - else - { - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } - - - if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist,true,true,false,false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist,true,false,false,0x18); - } - else - { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist,true,true,false,false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist,false,false,false,0x18); - } - } - else - { - - - - if( (bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } - else - { - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } - - - if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist,false,true,false,false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist,true,false,false,0x18); - } - else - { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist,false,true,false,false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist,false,false,false,0x18); - } - } - */ -} - - -void halbtc8821aCsr2ant_action_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2, - 15, 0); - bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0); - - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist)) - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true); - else - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); - else /* for HID quality & wifi performance balance at 11n mode */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5aea5aea, 0xffff, 0x3); - - if (BTC_WIFI_BW_HT40 == wifi_bw) { - /* fw mechanism */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - else - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 13); - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } else { - /* fw mechanism */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - else - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 13); - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - true, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - true, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } -} - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8821aCsr2ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8); - - if (coex_sta->slave == false) { - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0xfdfdfdfd, 0xdfdadfda, 0xffffff, 0x3); - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, - 0, 1); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, true, - 0x0c); - } else { - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0xfdfdfdfd, 0xdfdadfda, 0xffffff, 0x3); - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, - 0, 2); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, true, - 0x18); - } - - /* - wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0); - bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0); - - - - - - if(halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist)) - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true); - else - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if(BTC_WIFI_BW_HT40 == wifi_bw) - { - - if( (bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, false, false, 1); - } - else - { - halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, false, true, 1); - } - - - if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist,true,false,false,false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist,true,false,false,0x18); - } - else - { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist,true,false,false,false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist,false,false,false,0x18); - } - } - else - { - - if( (bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, false, false, 1); - } - else - { - halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, false, true, 1); - } - - - if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) ) - { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist,false,false,false,false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist,true,false,false,0x18); - } - else - { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist,false,false,false,false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist,false,false,false,0x18); - } - } - */ -} - -void halbtc8821aCsr2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state, bt_info_ext; - u32 wifi_bw; - - bt_info_ext = coex_sta->bt_info_ext; - wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2, - 15, 0); - bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0); - - /* fw dac swing is called in halbtc8821aCsr2ant_tdma_duration_adjust() */ - /* halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); */ - - - if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist)) - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true); - else - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_HT40 == wifi_bw) { - /* fw mechanism */ - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, - false, true, 2); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, - false, true, 1); - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } else { - /* fw mechanism */ - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, - false, true, 2); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, - false, true, 1); - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } -} - -void halbtc8821aCsr2ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2, - 15, 0); - bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0); - - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist)) - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true); - else - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5aff5aff, 0xffff, 0x3); - else /* for HID quality & wifi performance balance at 11n mode */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5aff5aff, 0xffff, 0x3); - - if (BTC_WIFI_BW_HT40 == wifi_bw) { - /* fw mechanism */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 1); - else - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 5); - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } else { - /* fw mechanism */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 1); - else - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 5); - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } -} - - -/* PAN(HS) only */ -void halbtc8821aCsr2ant_action_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2, - 15, 0); - bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0); - - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_HT40 == wifi_bw) { - /* fw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, - true); - else - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, - false); - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } else { - /* fw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, - true); - else - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, - false); - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, - false, 1); - else - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, - false, 1); - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } -} - -/* PAN(EDR)+A2DP */ -void halbtc8821aCsr2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state, bt_info_ext; - u32 wifi_bw; - - bt_info_ext = coex_sta->bt_info_ext; - wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2, - 15, 0); - bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0); - - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist)) - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true); - else - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5afa5afa, 0xffff, 0x3); - else /* for HID quality & wifi performance balance at 11n mode */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5afa5afa, 0xffff, 0x3); - - if (BTC_WIFI_BW_HT40 == wifi_bw) { - /* fw mechanism */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, false, false, 3); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, false, false, 3); - } else { - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, false, true, 3); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, false, true, 3); - } - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - }; - } else { - /* fw mechanism */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, false, false, 3); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, false, false, 3); - } else { - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, false, true, 3); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, false, true, 3); - } - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - false, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } -} - -void halbtc8821aCsr2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2, - 15, 0); - bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0); - - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist)) - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true); - else - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5a5f5a5f, 0xffff, 0x3); - else /* for HID quality & wifi performance balance at 11n mode */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5a5f5a5f, 0xffff, 0x3); - - if (BTC_WIFI_BW_HT40 == wifi_bw) { - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 3); - /* fw mechanism */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 10); - else - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } else { - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - /* fw mechanism */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 10); - else - halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - true, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - true, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } -} - -/* HID+A2DP+PAN(EDR) */ -void halbtc8821aCsr2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist - *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state, bt_info_ext; - u32 wifi_bw; - - bt_info_ext = coex_sta->bt_info_ext; - wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2, - 15, 0); - bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0); - - halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist)) - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true); - else - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); - else /* for HID quality & wifi performance balance at 11n mode */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); - - if (BTC_WIFI_BW_HT40 == wifi_bw) { - /* fw mechanism */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 3); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 3); - } else { - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 3); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 3); - } - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } else { - /* fw mechanism */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, false, 3); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, false, 3); - } else { - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 3); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 3); - } - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - true, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - true, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } -} - -void halbtc8821aCsr2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state, bt_info_ext; - u32 wifi_bw; - - bt_info_ext = coex_sta->bt_info_ext; - wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2, - 15, 0); - bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0); - - if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist)) - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true); - else - halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) { /* for HID at 11b/g mode */ - /* Allen halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5f5b5f5b, 0xffffff, 0x3); - } else { /* for HID quality & wifi performance balance at 11n mode */ - /* Allen halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); */ - halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, - 0x55ff55ff, 0x5f5b5f5b, 0xffffff, 0x3); - - } - - if (BTC_WIFI_BW_HT40 == wifi_bw) { - /* fw mechanism */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 2); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 2); - } else { - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 2); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 2); - } - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } else { - /* fw mechanism */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (bt_info_ext & BIT(0)) { /* a2dp basic rate */ - /* halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, true, false, 2); */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 2); - - } else { /* a2dp edr rate */ - /* Allen halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, true, false, 2); */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 2); - } - } else { - if (bt_info_ext & BIT(0)) /* a2dp basic rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 2); - else /* a2dp edr rate */ - halbtc8821aCsr2ant_tdma_duration_adjust( - btcoexist, true, true, 2); - } - - /* sw mechanism */ - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - true, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true, - false, false, 0x18); - } else { - halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, - true, false, false); - halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - } - } -} - -void halbtc8821aCsr2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - boolean wifi_under_5g = false; - u8 algorithm = 0; - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Manual control!!!\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_coex_under_5g(btcoexist); - return; - } - - { - algorithm = halbtc8821aCsr2ant_action_algorithm(btcoexist); - if (coex_sta->c2h_bt_inquiry_page && - (BT_8821A_CSR_2ANT_COEX_ALGO_PANHS != algorithm)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_bt_inquiry_page(btcoexist); - return; - } - - coex_dm->cur_algorithm = algorithm; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Algorithm = %d\n", coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - - if (halbtc8821aCsr2ant_is_common_action(btcoexist)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant common.\n"); - BTC_TRACE(trace_buf); - coex_dm->reset_tdma_adjust = true; - } else { - if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", - coex_dm->pre_algorithm, - coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - coex_dm->reset_tdma_adjust = true; - } - switch (coex_dm->cur_algorithm) { - case BT_8821A_CSR_2ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_action_sco( - btcoexist); - break; - case BT_8821A_CSR_2ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_action_hid( - btcoexist); - break; - case BT_8821A_CSR_2ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_action_a2dp( - btcoexist); - break; - case BT_8821A_CSR_2ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_action_a2dp_pan_hs( - btcoexist); - break; - case BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_action_pan_edr( - btcoexist); - break; - case BT_8821A_CSR_2ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_action_pan_hs( - btcoexist); - break; - case BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_action_pan_edr_a2dp( - btcoexist); - break; - case BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_action_pan_edr_hid( - btcoexist); - break; - case BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR - : - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_action_hid_a2dp( - btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_coex_all_off( - btcoexist); - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } - } -} - - - -/* ************************************************************ - * work around function start with wa_halbtc8821aCsr2ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8821aCsr2ant_ - * ************************************************************ */ -void ex_halbtc8821aCsr2ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8821aCsr2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - if (wifi_only) - return; - - /* if(back_up) */ - { - /* backup rf 0x1e value */ - coex_dm->bt_rf_0x1e_backup = btcoexist->btc_get_rf_reg( - btcoexist, BTC_RF_A, 0x1e, 0xfffff); - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - coex_dm->backup_ampdu_max_num = btcoexist->btc_read_2byte( - btcoexist, 0x4ca); - } - -#if 0 /* REMOVE */ - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); -#endif - - /* Antenna config */ - halbtc8821aCsr2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true, - false); - - /* PTA parameter */ - halbtc8821aCsr2ant_coex_table(btcoexist, FORCE_EXEC, 0x55555555, - 0x55555555, 0xffff, 0x3); - - /* Enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, - 0xc); /* 0x76e[3] =1, WLAN_Act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); - -#if 0 /* REMOVE */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); -#endif -} - -void ex_halbtc8821aCsr2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821aCsr2ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8821aCsr2ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u32 u32tmp[4]; - u32 fw_ver = 0, bt_patch_ver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "[Action Manual control]!!"); - CL_PRINTF(cli_buf); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", - "CoexVer/ FwVer/ PatchVer", - glcoex_ver_date_8821a_csr_2ant, glcoex_ver_8821a_csr_2ant, - fw_ver, bt_patch_ver, bt_patch_ver); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") : (( - BT_8821A_CSR_2ANT_BT_STATUS_IDLE == coex_dm->bt_status) - ? "idle" : ((BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE - == coex_dm->bt_status) ? "connected-idle" : "busy"))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - if (stack_info->profile_notified) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", - stack_info->sco_exist, stack_info->hid_exist, - stack_info->pan_exist, stack_info->a2dp_exist); - CL_PRINTF(cli_buf); - - btcoexist->btc_disp_dbg_msg(btcoexist, - BTC_DBG_DISP_BT_LINK_INFO); - } - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8821A_CSR_2ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8821a_csr_2ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - /* Sw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Sw mechanism]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", - "SM1[ShRf/ LpRA/ LimDig]", - coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, - coex_dm->limited_dig); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", - "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", - coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, - coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); - CL_PRINTF(cli_buf); - - /* Fw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Fw mechanism]============"); - CL_PRINTF(cli_buf); - - if (!btcoexist->manual_control) { - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "DecBtPwr/ IgnWlanAct", - coex_dm->cur_dec_bt_pwr, coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - } - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", - "RF-A, 0x1e initVal", - coex_dm->bt_rf_0x1e_backup); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x ", - "0x778 (W_Act)/ 0x6cc (CoTab Sel)", - u8tmp[0], u8tmp[1]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x8db); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xc5b); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x8db(ADC)/0xc5b[29:25](DAC)", - ((u8tmp[0] & 0x60) >> 5), ((u8tmp[1] & 0x3e) >> 1)); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xcb4[7:0](ctrl)/ 0xcb4[29:28](val)", - u32tmp[0] & 0xff, ((u32tmp[0] & 0x30000000) >> 28)); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x974); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x40/ 0x4c[24:23]/ 0x974", - u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u32tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa0a); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xc50(DIG)/0xa0a(CCK-TH)", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xf48); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "OFDM-FA/ CCK-FA", - u32tmp[0], (u8tmp[0] << 8) + u8tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770 (hi-pri Rx/Tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri Rx/Tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); - - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8821aCsr2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - halbtc8821aCsr2ant_coex_all_off(btcoexist); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; - /* halbtc8821aCsr2ant_init_coex_dm(btcoexist); */ - } -} - -void ex_halbtc8821aCsr2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8821aCsr2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_SCAN_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_SCAN_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8821aCsr2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_ASSOCIATE_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_ASSOCIATE_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8821aCsr2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = 0x1; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - -} - -void ex_halbtc8821aCsr2ant_specific_packet_notify(IN struct btc_coexist - *btcoexist, IN u8 type) -{ - if (type == BTC_PACKET_DHCP) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], DHCP Packet notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8821aCsr2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean bt_busy = false, limited_dig = false; - boolean wifi_connected = false, bt_hs_on = false, - wifi_under_5g = false; - - coex_sta->c2h_bt_info_req_sent = false; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8821A_CSR_2ANT_MAX) - rsp_source = BT_INFO_SRC_8821A_CSR_2ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (BT_INFO_SRC_8821A_CSR_2ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - -#if 0 /* REMOVE */ - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if ((coex_sta->bt_info_ext & BIT(1))) { - - if (wifi_connected) - ex_halbtc8821aCsr2ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8821aCsr2ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } -#endif - - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (bt_info == - BT_INFO_8821A_CSR_2ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_sta->bt_link_exist = true; - coex_dm->bt_status = - BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE; - } else if (bt_info & - BT_INFO_8821A_CSR_2ANT_B_CONNECTION) { /* connection exists and some link is busy */ - coex_sta->bt_link_exist = true; - - if (bt_info & BT_INFO_8821A_CSR_2ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - - if (bt_info & BT_INFO_8821A_CSR_2ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - - if (bt_info & BT_INFO_8821A_CSR_2ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - - if (bt_info & BT_INFO_8821A_CSR_2ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - - if (coex_sta->bt_info_ext & 0x80) - coex_sta->slave = true; /* Slave */ - else - coex_sta->slave = false; /* Master */ - - coex_dm->bt_status = - BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE; - } else { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->slave = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - coex_dm->bt_status = BT_8821A_CSR_2ANT_BT_STATUS_IDLE; - } - - if (bt_hs_on) - coex_dm->bt_status = - BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE; - - if (bt_info & BT_INFO_8821A_CSR_2ANT_B_INQ_PAGE) { - coex_sta->c2h_bt_inquiry_page = true; - coex_dm->bt_status = BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE; - } else - coex_sta->c2h_bt_inquiry_page = false; - - - if (BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE == coex_dm->bt_status) - bt_busy = true; - else - bt_busy = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - if (BT_8821A_CSR_2ANT_BT_STATUS_IDLE != coex_dm->bt_status) - limited_dig = true; - else - limited_dig = false; - coex_dm->limited_dig = limited_dig; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); - - halbtc8821aCsr2ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8821aCsr2ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821aCsr2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - ex_halbtc8821aCsr2ant_media_status_notify(btcoexist, - BTC_MEDIA_DISCONNECT); -} - -void ex_halbtc8821aCsr2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - halbtc8821aCsr2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8821aCsr2ant_periodical(IN struct btc_coexist *btcoexist) -{ - halbtc8821aCsr2ant_monitor_bt_ctr(btcoexist); - halbtc8821aCsr2ant_monitor_bt_enable_disable(btcoexist); -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ \ No newline at end of file diff --git a/hal/btc/HalBtc8821aCsr2Ant.h b/hal/btc/HalBtc8821aCsr2Ant.h deleted file mode 100644 index 8d228fb..0000000 --- a/hal/btc/HalBtc8821aCsr2Ant.h +++ /dev/null @@ -1,188 +0,0 @@ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821A_SUPPORT == 1) - -/* ******************************************* - * The following is for 8821A_CSR 2Ant BT Co-exist definition - * ******************************************* */ -#define BT_INFO_8821A_CSR_2ANT_B_FTP BIT(7) -#define BT_INFO_8821A_CSR_2ANT_B_A2DP BIT(6) -#define BT_INFO_8821A_CSR_2ANT_B_HID BIT(5) -#define BT_INFO_8821A_CSR_2ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8821A_CSR_2ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8821A_CSR_2ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8821A_CSR_2ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8821A_CSR_2ANT_B_CONNECTION BIT(0) - -#define BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT 2 - -enum bt_info_src_8821a_csr_2ant { - BT_INFO_SRC_8821A_CSR_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8821A_CSR_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8821A_CSR_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8821A_CSR_2ANT_MAX -}; - -enum bt_8821a_csr_2ant_bt_status { - BT_8821A_CSR_2ANT_BT_STATUS_IDLE = 0x0, - BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE = 0x2, - BT_8821A_CSR_2ANT_BT_STATUS_MAX -}; - -enum bt_8821a_csr_2ant_coex_algo { - BT_8821A_CSR_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8821A_CSR_2ANT_COEX_ALGO_SCO = 0x1, - BT_8821A_CSR_2ANT_COEX_ALGO_HID = 0x2, - BT_8821A_CSR_2ANT_COEX_ALGO_A2DP = 0x3, - BT_8821A_CSR_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR = 0x5, - BT_8821A_CSR_2ANT_COEX_ALGO_PANHS = 0x6, - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8821A_CSR_2ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8821a_csr_2ant { - /* fw mechanism */ - boolean pre_dec_bt_pwr; - boolean cur_dec_bt_pwr; - u8 pre_fw_dac_swing_lvl; - u8 cur_fw_dac_swing_lvl; - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[6]; - u8 ps_tdma_du_adj_type; - boolean reset_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - - /* sw mechanism */ - boolean pre_rf_rx_lpf_shrink; - boolean cur_rf_rx_lpf_shrink; - u32 bt_rf_0x1e_backup; - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - boolean pre_dac_swing_on; - u32 pre_dac_swing_lvl; - boolean cur_dac_swing_on; - u32 cur_dac_swing_lvl; - boolean pre_adc_back_off; - boolean cur_adc_back_off; - boolean pre_agc_table_en; - boolean cur_agc_table_en; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - u32 pre_ra_mask; - u32 cur_ra_mask; - - u8 cur_ampdu_num_type; - u8 pre_ampdu_num_type; - u16 backup_ampdu_max_num; - - u8 cur_ampdu_time_type; - u8 pre_ampdu_time_type; - u8 backup_ampdu_max_time; - - u8 cur_arfr_type; - u8 pre_arfr_type; - u32 backup_arfr_cnt1; - u32 backup_arfr_cnt2; - - u8 cur_retry_limit_type; - u8 pre_retry_limit_type; - u16 backup_retry_limit; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; -}; - -struct coex_sta_8821a_csr_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean slave; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - u8 bt_rssi; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8821A_CSR_2ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8821A_CSR_2ANT_MAX]; - boolean c2h_bt_inquiry_page; - u8 bt_retry_cnt; - u8 bt_info_ext; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8821aCsr2ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8821aCsr2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8821aCsr2ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8821aCsr2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821aCsr2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821aCsr2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821aCsr2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821aCsr2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821aCsr2ant_specific_packet_notify(IN struct btc_coexist - *btcoexist, IN u8 type); -void ex_halbtc8821aCsr2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8821aCsr2ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8821aCsr2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8821aCsr2ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8821aCsr2ant_display_coex_info(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8821aCsr2ant_power_on_setting(btcoexist) -#define ex_halbtc8821aCsr2ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8821aCsr2ant_init_coex_dm(btcoexist) -#define ex_halbtc8821aCsr2ant_ips_notify(btcoexist, type) -#define ex_halbtc8821aCsr2ant_lps_notify(btcoexist, type) -#define ex_halbtc8821aCsr2ant_scan_notify(btcoexist, type) -#define ex_halbtc8821aCsr2ant_connect_notify(btcoexist, type) -#define ex_halbtc8821aCsr2ant_media_status_notify(btcoexist, type) -#define ex_halbtc8821aCsr2ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8821aCsr2ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8821aCsr2ant_halt_notify(btcoexist) -#define ex_halbtc8821aCsr2ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8821aCsr2ant_periodical(btcoexist) -#define ex_halbtc8821aCsr2ant_display_coex_info(btcoexist) -#endif - -#endif diff --git a/hal/btc/HalBtc8822b1Ant.c b/hal/btc/HalBtc8822b1Ant.c deleted file mode 100644 index be0a2ac..0000000 --- a/hal/btc/HalBtc8822b1Ant.c +++ /dev/null @@ -1,6006 +0,0 @@ -/* ************************************************************ - * Description: - * - * This file is for RTL8822B Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "Mp_Precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8822B_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8822b_1ant glcoex_dm_8822b_1ant; -static struct coex_dm_8822b_1ant *coex_dm = &glcoex_dm_8822b_1ant; -static struct coex_sta_8822b_1ant glcoex_sta_8822b_1ant; -static struct coex_sta_8822b_1ant *coex_sta = &glcoex_sta_8822b_1ant; -static struct psdscan_sta_8822b_1ant gl_psd_scan_8822b_1ant; -static struct psdscan_sta_8822b_1ant *psd_scan = &gl_psd_scan_8822b_1ant; -static struct rfe_type_8822b_1ant gl_rfe_type_8822b_1ant; -static struct rfe_type_8822b_1ant *rfe_type = &gl_rfe_type_8822b_1ant; - - - -const char *const glbt_info_src_8822b_1ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8822b_1ant = 20160411; -u32 glcoex_ver_8822b_1ant = 0x14; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8822b1ant_ - * ************************************************************ */ -u8 halbtc8822b1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8822b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8822b1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8822b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8822b1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8822b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8822b1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8822b1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8822b1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8822b1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8822b1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8822b1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8822b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -/* -1: true / don't care / don't care -max: false / false / don't care -7: false / true / 7 -*/ - -void halbtc8822b1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8822b1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -void halbtc8822b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0, cnt_slave = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ - /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ - - if (coex_sta->under_ips) { - /* coex_sta->high_priority_tx = 65535; */ - /* coex_sta->high_priority_rx = 65535; */ - /* coex_sta->low_priority_tx = 65535; */ - /* coex_sta->low_priority_rx = 65535; */ - /* return; */ - } - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", - reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - if ((coex_sta->low_priority_tx > 1150) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - if ((coex_sta->low_priority_rx >= 1150) && (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) - && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && (coex_sta->bt_link_exist) ) { - if (cnt_slave >= 3) { - bt_link_info->slave_role = true; - cnt_slave = 3; - } else { - cnt_slave ++; - } - } else { - if(cnt_slave == 0) { - bt_link_info->slave_role = false; - cnt_slave = 0; - } else{ - cnt_slave--; - } - - } - - if ((coex_sta->high_priority_tx == 0) && (coex_sta->high_priority_rx == 0) && (coex_sta->low_priority_tx == 0) && - (coex_sta->low_priority_rx == 0)) { - num_of_bt_counter_chk++; - - if (num_of_bt_counter_chk >= 3) { - halbtc8822b1ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; - } - } -#if 0 - /* Add Hi-Pri Tx/Rx counter to avoid false detection */ - if (((coex_sta->hid_exist) || (coex_sta->sco_exist)) && - (coex_sta->high_priority_tx + coex_sta->high_priority_rx - >= 160) - && (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->bt_hi_pri_link_exist = true; - else - coex_sta->bt_hi_pri_link_exist = false; - - if ((coex_sta->acl_busy) && - (coex_sta->num_of_profile == 0)) { - if (coex_sta->low_priority_tx + - coex_sta->low_priority_rx >= 160) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - coex_sta->wrong_profile_notification++; - } - } -#endif - -} - - -void halbtc8822b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) - { - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false; - static u8 cck_lock_counter = 0; - u32 total_cnt; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,&wifi_under_b_mode); - - if (coex_sta->under_ips) { - coex_sta->crc_ok_cck = 0; - coex_sta->crc_ok_11g = 0; - coex_sta->crc_ok_11n = 0; - coex_sta->crc_ok_11n_agg = 0; - - coex_sta->crc_err_cck = 0; - coex_sta->crc_err_11g = 0; - coex_sta->crc_err_11n = 0; - coex_sta->crc_err_11n_agg = 0; - } else { - coex_sta->crc_ok_cck = btcoexist->btc_read_2byte(btcoexist, - 0xf04); - coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf14); - coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf10); - coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xf0c); - - coex_sta->crc_err_cck = btcoexist->btc_read_2byte(btcoexist,0xf00) + btcoexist->btc_read_2byte(btcoexist,0xf06); - - coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf16); - coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf12); - coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xf0e); - } - - - /* reset counter */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x0); - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + - coex_sta->crc_ok_11n_agg; - - if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == - BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == - BT_8822B_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 3) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = true; - - coex_sta->pre_ccklock = coex_sta->cck_lock; - - - } - - -boolean halbtc8822b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false, pre_bt_off = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (coex_sta->bt_disabled != pre_bt_off) - { - pre_bt_off = coex_sta->bt_disabled; - - if (coex_sta->bt_disabled) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - - BTC_TRACE(trace_buf); - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - return true; - } - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - } - - return false; -} - -void halbtc8822b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->bt_hi_pri_link_exist = coex_sta->bt_hi_pri_link_exist; - bt_link_info->acl_busy = coex_sta->acl_busy; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -void halbtc8822b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - - h2c_parameter[0] = 0x1; /* enable BT AFH skip WL channel for 8822b because BT Rx LO interference */ - h2c_parameter[1] = wifi_central_chnl; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); - -} - -u8 halbtc8822b1ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8822B_1ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8822B_1ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8822B_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8822B_1ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8822B_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8822B_1ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8822B_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8822B_1ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8822B_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8822B_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8822B_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8822b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8822b1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8822b1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8822b1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8822b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8822b1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8822b1ant_write_score_board( - IN struct btc_coexist *btcoexist, - IN u16 bitpos, - IN BOOLEAN state -) -{ - - static u16 originalval = 0x8002; - - if (state) - originalval = originalval | bitpos; - else - originalval = originalval & (~bitpos); - - btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); -} - -void halbtc8822b1ant_read_score_board( - IN struct btc_coexist *btcoexist, - IN u16 *score_board_val -) -{ - - *score_board_val = (btcoexist->btc_read_2byte(btcoexist, - 0xaa)) & 0x7fff; -} - -void halbtc8822b1ant_post_activestate_to_bt( - IN struct btc_coexist *btcoexist, - IN boolean wifi_active -) -{ - - if (wifi_active) - halbtc8822b1ant_write_score_board(btcoexist, (u16) BIT(0), TRUE); - else - halbtc8822b1ant_write_score_board(btcoexist, (u16) BIT(0), FALSE); -} - - -void halbtc8822b1ant_post_onoffstate_to_bt( - IN struct btc_coexist *btcoexist, - IN boolean wifi_on -) -{ - - if (wifi_on) - halbtc8822b1ant_write_score_board(btcoexist, (u16) BIT(1), TRUE); - else - halbtc8822b1ant_write_score_board(btcoexist, (u16) BIT(1), FALSE); -} - - -void halbtc8822b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - u16 u16tmp; - - /* This function check if bt is disabled */ -#if 1 - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - - -#else - - /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */ - halbtc8822b1ant_read_score_board(btcoexist, &u16tmp); - - bt_active = u16tmp & BIT(1); - - -#endif - - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } else { - - bt_disable_cnt++; - if (bt_disable_cnt >= 2) { - bt_disabled = true; - bt_disable_cnt = 2; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } - - - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - } - -} - - - -void halbtc8822b1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, - boolean isenable) -{ - static u8 bitVal[5] = {0,0,0,0,0}; - static boolean state = false; - - if (state ==isenable) - return; - else - state = isenable; - - if (isenable) { - - /* enable GNT_WL, GNT_BT to GPIO for debug */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); - - /* store original value */ - bitVal[0] = (btcoexist->btc_read_1byte(btcoexist, 0x66) & BIT(4)) >>4; /*0x66[4] */ - bitVal[1] = (btcoexist->btc_read_1byte(btcoexist, 0x67) & BIT(0)); /*0x66[8] */ - bitVal[2] = (btcoexist->btc_read_1byte(btcoexist, 0x42) & BIT(3)) >> 3; /*0x40[19] */ - bitVal[3] = (btcoexist->btc_read_1byte(btcoexist, 0x65) & BIT(7)) >> 7; /*0x64[15] */ - bitVal[4] = (btcoexist->btc_read_1byte(btcoexist, 0x72) & BIT(2)) >> 2; /*0x70[18] */ - - /* switch GPIO Mux */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), 0x0); /*0x66[4] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), 0x0); /*0x66[8] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), 0x0); /*0x40[19] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), 0x0); /*0x64[15] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), 0x0); /*0x70[18] = 0 */ - - - } else { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); - - /* Restore original value */ - /* switch GPIO Mux */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), bitVal[0]); /*0x66[4] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), bitVal[1]); /*0x66[8] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), bitVal[2]); /*0x40[19] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), bitVal[3]); /*0x64[15] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), bitVal[4]); /*0x70[18] = 0 */ - } - -} - - -u32 halbtc8822b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, - IN u16 reg_addr) -{ - u32 j = 0; - - - /* wait for ready bit before access 0x1700 */ - btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr); - - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x1703) & BIT(5)) == 0) && - (j < BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - return btcoexist->btc_read_4byte(btcoexist, - 0x1708); /* get read data */ - -} - -void halbtc8822b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist *btcoexist, - IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) -{ - u32 val, i = 0, j = 0, bitpos = 0; - - - if (bit_mask == 0x0) - return; - if (bit_mask == 0xffffffff) { - btcoexist->btc_write_4byte(btcoexist, 0x1704, - reg_value); /* put write data */ - - /* wait for ready bit before access 0x1700 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x1703) & BIT(5)) == 0) && - (j < BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x1700, - 0xc00F0000 | reg_addr); - } else { - for (i = 0; i <= 31; i++) { - if (((bit_mask >> i) & 0x1) == 0x1) { - bitpos = i; - break; - } - } - - /* read back register value before write */ - val = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - reg_addr); - val = (val & (~bit_mask)) | (reg_value << bitpos); - - /* put write data value */ - btcoexist->btc_write_4byte(btcoexist, 0x1704, - val); /* put write data */ - - /* wait for ready bit before access 0x1700 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x1703) & BIT(5)) == 0) && - (j < BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - /* write data add*/ - - btcoexist->btc_write_4byte(btcoexist, 0x1700, - 0xc00F0000 | reg_addr); - - } - -} - -void halbtc8822b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 val; - - val = (enable) ? 1 : 0; - /* 0x38[7] */ - halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, - val); /* 0x38[7] */ - -} - - -void halbtc8822b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, - IN boolean wifi_control) -{ - u8 val; - - val = (wifi_control) ? 1 : 0; - /* 0x70[26] */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, - val); /* 0x70[26] */ - -} - -void halbtc8822b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, bit_mask; - - state = state & 0x1; - /*LTE indirect 0x38=0xccxx (sw : gnt_wl=1,sw gnt_bt=1) - 0x38=0xddxx (sw : gnt_bt=1 , sw gnt_wl=0) - 0x38=0x55xx(hw pta :gnt_wl /gnt_bt ) */ - val = (sw_control) ? ((state << 1) | 0x1) : 0; - - switch (control_block) { - case BT_8822B_1ANT_GNT_BLOCK_RFC_BB: - default: - bit_mask = 0xc000; - halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[15:14] */ - bit_mask = 0x0c00; - halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[11:10] */ - break; - case BT_8822B_1ANT_GNT_BLOCK_RFC: - bit_mask = 0xc000; - halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[15:14] */ - break; - case BT_8822B_1ANT_GNT_BLOCK_BB: - bit_mask = 0x0c00; - halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[11:10] */ - break; - - } - -} - -void halbtc8822b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, bit_mask; - /*LTE indirect 0x38=0xccxx (sw : gnt_wl=1,sw gnt_bt=1) - 0x38=0xddxx (sw : gnt_bt=1 , sw gnt_wl=0) - 0x38=0x55xx(hw pta :gnt_wl /gnt_bt ) */ - - state = state & 0x1; - val = (sw_control) ? ((state << 1) | 0x1) : 0; - - switch (control_block) { - case BT_8822B_1ANT_GNT_BLOCK_RFC_BB: - default: - bit_mask = 0x3000; - halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[13:12] */ - bit_mask = 0x0300; - halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[9:8] */ - break; - case BT_8822B_1ANT_GNT_BLOCK_RFC: - bit_mask = 0x3000; - halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[13:12] */ - break; - case BT_8822B_1ANT_GNT_BLOCK_BB: - bit_mask = 0x0300; - halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, bit_mask, val); /* 0x38[9:8] */ - break; - - } - -} - -void halbtc8822b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u16 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8822B_1ANT_CTT_WL_VS_LTE: - reg_addr = 0xa0; - break; - case BT_8822B_1ANT_CTT_BT_VS_LTE: - reg_addr = 0xa4; - break; - } - - if (reg_addr != 0x0000) - halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ - - -} - - -void halbtc8822b1ant_ltcoex_set_break_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u8 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8822B_1ANT_LBTT_WL_BREAK_LTE: - reg_addr = 0xa8; - break; - case BT_8822B_1ANT_LBTT_BT_BREAK_LTE: - reg_addr = 0xac; - break; - case BT_8822B_1ANT_LBTT_LTE_BREAK_WL: - reg_addr = 0xb0; - break; - case BT_8822B_1ANT_LBTT_LTE_BREAK_BT: - reg_addr = 0xb4; - break; - } - - if (reg_addr != 0x0000) - halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ - - -} - -void halbtc8822b1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8822b1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8822b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8822b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - u32 break_table; - u8 select_table; - - - - coex_sta->coex_table_type = type; - - if (coex_sta->concurrent_rx_mode_on == true) { - - break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ - select_table = - 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ - } else { - - break_table = 0xffffff; - select_table = 0x3; - } - - switch (type) { - case 0: - halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, break_table, - select_table); - break; - case 1: - halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 2: - halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0xaa5a5a5a, 0xaa5a5a5a, break_table, - select_table); - break; - case 3: - halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaa5a5a5a, break_table, - select_table); - break; - case 4: - halbtc8822b1ant_coex_table(btcoexist, - force_exec, 0xaa555555, 0xaa5a5a5a, - break_table, select_table); - break; - case 5: - halbtc8822b1ant_coex_table(btcoexist, - force_exec, 0x5a5a5a5a, 0x5a5a5a5a, - break_table, select_table); - break; - case 6: - halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaaaaaa, break_table, - select_table); - break; - case 7: - halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, break_table, - select_table); - break; - case 8: - halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0xffffffff, 0xffffffff, break_table, - select_table); - break; - - default: - break; - } -} - -void halbtc8822b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - - - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8822b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - { - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; - return; - } - } - - halbtc8822b1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8822b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8822b1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8822b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8822b1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - - -void halbtc8822b1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - coex_sta->force_lps_on = false; - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - - coex_sta->force_lps_on = true; - halbtc8822b1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8822b1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - - coex_sta->force_lps_on = false; - halbtc8822b1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - - -void halbtc8822b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - BTC_TRACE(trace_buf); - - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - - halbtc8822b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - } - } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - - halbtc8822b1ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } else { - halbtc8822b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - } - - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; - static boolean pre_wifi_busy = false; - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (wifi_busy != pre_wifi_busy) { - force_exec = true; - pre_wifi_busy = wifi_busy; - } - - /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist)) - psTdmaByte4Modify = 0x1; - else - psTdmaByte4Modify = 0x0; - - if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { - - force_exec = true; - pre_psTdmaByte4Modify = psTdmaByte4Modify; - } - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], **********TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], return for no-TDMA case change\n"); - BTC_TRACE(trace_buf); - - return; - } - } - - - if (turn_on) { - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - - switch (type) { - default: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51,0x1a, 0x1a, 0x0, 0x10); - break; - case 1: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x3a,0x03,0x11, 0x10); - break; - case 3: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x3a, 0x03, 0x10, 0x10); - break; - case 4: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x21, 0x03, 0x10, 0x10); - break; - case 5: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x3,0x11, 0x11); - break; - case 7: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify); - break; - case 8: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify); - break; - case 13: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x25, 0x03, 0x10, 0x10 | psTdmaByte4Modify); - break; - case 14: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x15, 0x03, 0x10, 0x10 | psTdmaByte4Modify); - break; - case 15: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x20, 0x03, 0x10, 0x10 | psTdmaByte4Modify); - break; - case 17: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x14 | psTdmaByte4Modify); - break;; - - case 20: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03,0x11, 0x10); - break; - case 22: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x25, 0x03,0x11, 0x10); - break; - case 32: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x3,0x11, 0x11); - break; - case 41:/*HID*/ - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51,0x45, 0x3, 0x11, 0x11); - break; - case 42:/*A2DP*/ - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51,0x1e, 0x3, 0x10, 0x14| psTdmaByte4Modify); - break; - case 43:/*A2DP+HID*/ - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51,0x45, 0x3, 0x10, 0x14); - break; - case 44:/*A2DP+OPP old */ - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51,0x25, 0x3, 0x10, 0x10); - break; - case 45:/*OPP new -> WIFI FW check the ncuu_p ack of AP , if has no null_p ack , wifi fw will extened wifi slot */ - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51,0x3a, 0x3, 0x10, 0x10); - break; - case 46:/*A2DP+OPP new-> WIFI FW check the ncuu_p ack of AP , if has no null_p ack , wifi fw will extened wifi slot*/ - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51,0x1a, 0x3, 0x10, 0x10); - break; - - } - } else { - - switch (type) { - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x0,0x0, 0x0, 0x0, 0x0); - /* - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, FORCE_EXEC, false, - false); */ - break; - case 8: /* PTA Control */ - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x8,0x0, 0x0, 0x0, 0x0); - /* - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, FORCE_EXEC, false, - false); */ - break; - case 9: /* Software control, Antenna at WiFi side */ - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x0,0x0, 0x0, 0x0, 0x0); - /* - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_WIFI, FORCE_EXEC,false,false); */ - break; - case 10: /* under 5G , 0x778=1*/ - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x0,0x0, 0x0, 0x0, 0x0); - - /* - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_WIFI5G, FORCE_EXEC, false, - false); */ - - break; - } - } - - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - - -void halbtc8822b1ant_sw_mechanism(IN struct btc_coexist *btcoexist, - IN boolean low_penalty_ra) -{ - halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8822b1ant_set_rfe_type(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - - - /* the following setup should be got from Efuse in the future */ - rfe_type->rfe_module_type = board_info->rfe_type; - - rfe_type->ext_ant_switch_ctrl_polarity = 0;; - - switch(rfe_type->rfe_module_type) - { - case 0: - default: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; - break; - case 1: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; - break; - case 2: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; - break; - case 3: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; - break; - case 4: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SP3T; /* SP3T */; - break; - } - - -} - - -void halbtc8822b1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - boolean switch_polatiry_inverse = false; - u8 regval_0xcbd = 0, regval_0x64; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - - if (!rfe_type->ext_ant_switch_exist) - return; - - coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; - - if (!force_exec) { - if (coex_dm->pre_ext_ant_switch_status == coex_dm->cur_ext_ant_switch_status) - return; - } - - coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status; - - /* swap control polarity if use different switch control polarity*/ - /* Normal switch polarity for SPDT, 0xcbd[1:0] = 2b'01 => Ant to BTG, 0xcbd[1:0] = 2b'10 => Ant to WLG */ - switch_polatiry_inverse = (rfe_type->ext_ant_switch_ctrl_polarity == 1? ~switch_polatiry_inverse: switch_polatiry_inverse); - - - switch(pos_type) - { - default: - case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT: - case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE: - - break; - case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG: - switch_polatiry_inverse = ~switch_polatiry_inverse; - break; - case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA: - break; - } - - - if (rfe_type->ext_ant_switch_type == BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT) - { - switch(ctrl_type) - { - default: - case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff, 0x77); /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as cotrol pin */ - - regval_0xcbd = (switch_polatiry_inverse == false? 0x1 : 0x2); /* 0xcbd[1:0] = 2b'01 for no switch_polatiry_inverse, ANTSWB =1, ANTSW =0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, regval_0xcbd); - - break; - case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff, 0x66); /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as cotrol pin */ - - regval_0xcbd = (switch_polatiry_inverse == false? 0x2 : 0x1); /* 0xcbd[1:0] = 2b'10 for no switch_polatiry_inverse, ANTSWB =1, ANTSW =0 @ GNT_BT=1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, regval_0xcbd); - - break; - case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff, 0x88); /* */ - - /* no regval_0xcbd setup required, because antenna switch control value by antenna diversity */ - - break; - case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80, 0x1); /* 0x4c[23] = 1 */ - - regval_0x64 = (switch_polatiry_inverse == false? 0x0 : 0x1); /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, regval_0x64); - break; - case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01, 0x0); /* 0x4c[24] = 0 */ - - /* no setup required, because antenna switch control value by BT vendor 0xac[1:0] */ - break; - } - } - - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcbd); - u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ext Ant switch setup) 0xcbd = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x**********\n", - u32tmp1, u32tmp2, u32tmp3); - BTC_TRACE(trace_buf); - - -} - - -void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, - IN u8 phase) - -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - - coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; - - if (!force_exec) { - if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) - return; - } - - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; - -#if 1 - u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0x54); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u32tmp3, u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif - - switch (phase) - { - case BT_8822B_1ANT_PHASE_COEX_INIT: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_COEX_INIT) **********\n" ); - BTC_TRACE(trace_buf); - - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8822b1ant_ltecoex_set_coex_table(btcoexist, - BT_8822B_1ANT_CTT_WL_VS_LTE, 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8822b1ant_ltecoex_set_coex_table(btcoexist, - BT_8822B_1ANT_CTT_BT_VS_LTE, 0xffff); - - /* set GNT_BT to SW high */ - halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); - - /* set GNT_WL to SW low */ - halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_LOW); - - /* set Path control owner to WL at initial step */ - halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8822B_1ANT_PCO_WLSIDE); - - coex_sta->run_time_state = false; - - /* Ext switch buffer mux */ - btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - break; - case BT_8822B_1ANT_PHASE_WLANONLY_INIT: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLANONLY_INIT) **********\n" ); - BTC_TRACE(trace_buf); - - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8822b1ant_ltecoex_set_coex_table(btcoexist, - BT_8822B_1ANT_CTT_WL_VS_LTE, 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8822b1ant_ltecoex_set_coex_table(btcoexist, - BT_8822B_1ANT_CTT_BT_VS_LTE, 0xffff); - - /* set GNT_BT to SW Low */ - halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_LOW); - - /* Set GNT_WL to SW high */ - halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); - - /* set Path control owner to WL at initial step */ - halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8822B_1ANT_PCO_WLSIDE); - - coex_sta->run_time_state = false; - - /* Ext switch buffer mux */ - btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_WIFI; - - break; - case BT_8822B_1ANT_PHASE_WLAN_OFF: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLAN_OFF) **********\n" ); - BTC_TRACE(trace_buf); - - /* Disable LTE Coex Function in WiFi side */ - halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0); - - /* set Path control owner to BT */ - halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8822B_1ANT_PCO_BTSIDE); - - /* Set Ext Ant Switch to BT control at wifi off step */ - halbtc8822b1ant_set_ext_ant_switch(btcoexist, - FORCE_EXEC, - BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT, - BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE); - - coex_sta->run_time_state = false; - - break; - case BT_8822B_1ANT_PHASE_2G_RUNTIME: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_2G_RUNTIME) **********\n" ); - BTC_TRACE(trace_buf); - - /* set GNT_BT to PTA */ - halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_PTA, - BT_8822B_1ANT_SIG_STA_SET_BY_HW); - - /* Set GNT_WL to PTA */ - halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_PTA, - BT_8822B_1ANT_SIG_STA_SET_BY_HW); - - /* set Path control owner to WL at runtime step */ - halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8822B_1ANT_PCO_WLSIDE); - - coex_sta->run_time_state = true; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_PTA; - - break; - case BT_8822B_1ANT_PHASE_5G_RUNTIME: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_5G_RUNTIME) **********\n" ); - BTC_TRACE(trace_buf); - - /* set GNT_BT to SW Hi */ - halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); - - /* Set GNT_WL to SW Hi */ - halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); - - /* set Path control owner to WL at runtime step */ - halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8822B_1ANT_PCO_WLSIDE); - - coex_sta->run_time_state = true; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_WIFI5G; - - break; - case BT_8822B_1ANT_PHASE_BTMPMODE : - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_BTMPMODE) **********\n" ); - BTC_TRACE(trace_buf); - - /* Disable LTE Coex Function in WiFi side */ - halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0); - - /* set GNT_BT to SW Hi */ - halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); - - /* Set GNT_WL to SW Lo */ - halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_LOW); - - /* set Path control owner to WL */ - halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8822B_1ANT_PCO_WLSIDE); - - coex_sta->run_time_state = false; - - /* Set Ext Ant Switch to BT side at BT MP mode */ - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - break; - } - - - if (phase != BT_8822B_1ANT_PHASE_WLAN_OFF) - { - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - halbtc8822b1ant_set_ext_ant_switch( btcoexist, - force_exec, - BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG); - break; - case BTC_ANT_PATH_WIFI5G: - halbtc8822b1ant_set_ext_ant_switch( btcoexist, - force_exec, - BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA); - break; - case BTC_ANT_PATH_BT: - halbtc8822b1ant_set_ext_ant_switch( btcoexist, - force_exec, - BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT); - break; - default: - case BTC_ANT_PATH_PTA: - halbtc8822b1ant_set_ext_ant_switch( btcoexist, - force_exec, - BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA, - BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE); - break; - } - - } -#if 1 - u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u32tmp3, u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - -#endif - -} - - -void halbtc8822b1ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* sw all off */ - halbtc8822b1ant_sw_mechanism(btcoexist, false); - - /* hw all off */ - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} -boolean halbtc8822b1ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (wifi_connected && - (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (!wifi_connected && - (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (wifi_connected && - (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (!wifi_connected && - (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } - - common = false; - } - - return common; -} - -void halbtc8822b1ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], under 5g start \n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 10); - - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 5); - -} - - - -void halbtc8822b1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - boolean wifi_under_5g = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if(wifi_under_5g) - { - halbtc8822b1ant_action_wifi_under5g(btcoexist); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wlan only -- under 5g ) **********\n"); - BTC_TRACE(trace_buf); - return; - } - - halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wlan only -- under 2g ) **********\n"); - BTC_TRACE(trace_buf); - -} - -/* ********************************************* - * - * Software Coex Mechanism start - * - * ********************************************* */ - -/* SCO only or SCO+PAN(HS) */ - -/* -void halbtc8822b1ant_action_sco(IN struct btc_coexist* btcoexist) -{ - halbtc8822b1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8822b1ant_action_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8822b1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8822b1ant_action_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8822b1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8822b1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8822b1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8822b1ant_action_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8822b1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8822b1ant_action_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8822b1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8822b1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8822b1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8822b1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8822b1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8822b1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8822b1ant_sw_mechanism(btcoexist, true); -} - -void halbtc8822b1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8822b1ant_sw_mechanism(btcoexist, true); -} - -*/ - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8822b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],action_bt_whck_test\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8822b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],action_wifi_multi_port\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); -} - -void halbtc8822b1ant_action_hs(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], action_hs\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); -} - -/*"""bt inquiry"""" + wifi any + bt any*/ -void halbtc8822b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, ap_enable = false, wifi_busy = false, - bt_busy = false; - - - boolean wifi_scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (bt inquiry) **********\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** scan = %d, link =%d, roam = %d**********\n", - wifi_scan, link, roam); - BTC_TRACE(trace_buf); - - if ( (link) || (roam) || (coex_sta->wifi_is_high_pri_task)){ - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (bt inquiry wifi connect or scan ) **********\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); - - } else if ((wifi_scan) && (coex_sta->bt_create_connection)) { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); - - } else if ((!wifi_connected) && (!wifi_scan)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (bt inquiry wifi non connect) **********\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist) { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (wifi_scan) { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (wifi_busy) { - - /* for BT inquiry/page fail after S4 resume */ - /* halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); */ - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 1); - }else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (bt inquiry wifi connect) **********\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 1); - } - -/* - if ((wifi_link) || (wifi_roam) || (coex_sta->wifi_is_high_pri_task)) { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); - - } else if ((wifi_scan) && (coex_sta->bt_create_connection)) { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); - - } else if ((!wifi_connected) && (!wifi_scan)) { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (wifi_scan) { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - } else if (wifi_busy) { - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 19); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } -*/ -} - -void halbtc8822b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (bt sco hid only busy) **********\n"); - BTC_TRACE(trace_buf); - - /*SCO + wifi conected idle or busy / 0x778=1@wifi slot*/ - if (bt_link_info->sco_exist) { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - - } else { /* HID + wifi conected idle or busy / 0x778=1@wifi slot */ - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - - } -} - -/*wifi connected + bt acl busy*/ -void halbtc8822b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - - u8 bt_rssi_state; - - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - bt_rssi_state = halbtc8822b1ant_bt_rssi_state(2, 28, 0); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wifi connect acl busy) **********\n"); - BTC_TRACE(trace_buf); - - if (bt_link_info->hid_only) { /* HID + wifi conected idle or busy / 0x778=1@wifi slot */ - halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist, - wifi_status); - return; - } else if (bt_link_info->a2dp_only) { /* A2DP + wifi conected idle or busy */ - if (BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } else { - if (coex_sta->scan_ap_num >= - BT_8822B_1ANT_WIFI_NOISY_THRESH) { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 17); - } else { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 42); - } - - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = true; - } - - /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 44); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 1); - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 42); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 1); - - } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && - bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP)*/ - /* - if (BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 4); - else - */ - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 45); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 1); - } else { - /* BT no-profile busy (0x9) */ - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 1); - } -} - -/*wifi not connected + bt action*/ -void halbtc8822b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wifi not connect) **********\n"); - BTC_TRACE(trace_buf); - - /* tdma and coex table */ - halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -/*""""wl not connected scan"""" + bt action*/ -void halbtc8822b1ant_action_wifi_not_connected_scan(IN struct btc_coexist - *btcoexist) -{ - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wifi non connect scan) **********\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if (num_of_wifi_link >= 2) { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_inquiry(btcoexist); - } else - halbtc8822b1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8822b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8822b1ant_action_hs(btcoexist); - return; - } - - /* tdma and coex table */ - if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } else { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } - } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 5); - } -} - -/*""""wl not connected asso"""" + bt action*/ -void halbtc8822b1ant_action_wifi_not_connected_asso_auth( - IN struct btc_coexist *btcoexist) -{ - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wifi non connect asso_auth) **********\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if (num_of_wifi_link >= 2) { - - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_inquiry(btcoexist); - } else - halbtc8822b1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8822b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8822b1ant_action_hs(btcoexist); - return; - } - - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2); - } -} - -/*""""wl connected scan"""" + bt action*/ -void halbtc8822b1ant_action_wifi_connected_scan(IN struct btc_coexist - *btcoexist) -{ - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wifi connect scan) **********\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if (num_of_wifi_link >= 2) { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_inquiry(btcoexist); - } else - halbtc8822b1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8822b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8822b1ant_action_hs(btcoexist); - return; - } - - /* tdma and coex table */ - if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } else { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } - } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 5); - } -} - -/*""""wl connected specific packet"""" + bt action*/ -void halbtc8822b1ant_action_wifi_connected_specific_packet( - IN struct btc_coexist *btcoexist) -{ - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - boolean wifi_busy = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wifi connect specific packet) **********\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if (num_of_wifi_link >= 2) { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_inquiry(btcoexist); - } else - halbtc8822b1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8822b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8822b1ant_action_hs(btcoexist); - return; - } - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* no specific packet process for both WiFi and BT very busy */ - if ((wifi_busy) && ((bt_link_info->pan_exist) || - (coex_sta->num_of_profile >= 2))) - return; - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else if (bt_link_info->a2dp_exist) { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 1); - } else if (bt_link_info->pan_exist) { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 1); - } else { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 5); - } -} - -/*wifi connected input point : to set different ps and tdma case (+bt different case)*/ -void halbtc8822b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - - boolean wifi_busy = false; - boolean scan = false, link = false, roam = false; - boolean under_4way = false, ap_enable = false, wifi_under_5g=false; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (wifi_under_5g) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 5g<===\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_action_wifi_under5g(btcoexist); - - return; - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 2g<===\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - } - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (under_4way) { - halbtc8822b1ant_action_wifi_connected_specific_packet(btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - if (scan) - halbtc8822b1ant_action_wifi_connected_scan(btcoexist); - else - halbtc8822b1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* tdma and coex table */ - if (!wifi_busy) { - if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8822b1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - /*sy modify case16 -> case17*/ - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - else - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } else { - if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8822b1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8822B_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8822B_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - /*sy modify case16 -> case17*/ - - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - else - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } -} - -void halbtc8822b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - - u8 algorithm = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (runswcoexmech) **********\n"); - BTC_TRACE(trace_buf); - algorithm = halbtc8822b1ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - - if (halbtc8822b1ant_is_common_action(btcoexist)) { - - } else { - switch (coex_dm->cur_algorithm) { - case BT_8822B_1ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - /* halbtc8822b1ant_action_sco(btcoexist); */ - break; - case BT_8822B_1ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8822b1ant_action_hid(btcoexist); */ - break; - case BT_8822B_1ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8822b1ant_action_a2dp(btcoexist); */ - break; - case BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - /* halbtc8822b1ant_action_a2dp_pan_hs(btcoexist); */ - break; - case BT_8822B_1ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - /* halbtc8822b1ant_action_pan_edr(btcoexist); */ - break; - case BT_8822B_1ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - /* halbtc8822b1ant_action_pan_hs(btcoexist); */ - break; - case BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8822b1ant_action_pan_edr_a2dp(btcoexist); */ - break; - case BT_8822B_1ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8822b1ant_action_pan_edr_hid(btcoexist); */ - break; - case BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - /* halbtc8822b1ant_action_hid_a2dp_pan_edr(btcoexist); */ - break; - case BT_8822B_1ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8822b1ant_action_hid_a2dp(btcoexist); */ - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8822b1ant_coex_all_off(btcoexist); */ - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8822b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - boolean miracast_plus_bt = false; - u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0, wifi_bw; - u8 iot_peer = BTC_IOT_PEER_UNKNOWN; - boolean wifi_under_5g = false; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (!coex_sta->run_time_state){ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], return for run_time_state = false !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if(wifi_under_5g) - { - halbtc8822b1ant_action_wifi_under5g(btcoexist); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 5G!!! \n"); - BTC_TRACE(trace_buf); - return; - }else{ - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 2G!!!\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, BT_8822B_1ANT_PHASE_2G_RUNTIME); - } - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_whck_test(btcoexist); - return; - } - - if (coex_sta->bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!!\n"); - halbtc8822b1ant_action_wifi_only(btcoexist); - return; - } - - if ((BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, - 0, 1); - miracast_plus_bt = true; - } else { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - miracast_plus_bt = false; - } - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if ((bt_link_info->a2dp_exist) && - (coex_sta->c2h_bt_inquiry_page)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_inquiry(btcoexist); - } else - halbtc8822b1ant_action_wifi_multi_port(btcoexist); - - return; - } else { - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); - - if (BTC_IOT_PEER_CISCO != iot_peer) { - if (bt_link_info->sco_exist) /* if (bt_link_info->bt_hi_pri_link_exist) */ - halbtc8822b1ant_limited_rx(btcoexist, - NORMAL_EXEC, true, false, 0x5); - else - halbtc8822b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, false, 0x5); - } else { - if (bt_link_info->sco_exist) - halbtc8822b1ant_limited_rx(btcoexist, - NORMAL_EXEC, true, false, 0x5); - else { - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8822b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x10); - else - halbtc8822b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x8); - } - } - - halbtc8822b1ant_sw_mechanism(btcoexist, true); - halbtc8822b1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - } else { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x5); - - halbtc8822b1ant_sw_mechanism(btcoexist, false); - halbtc8822b1ant_run_sw_coexist_mechanism( - btcoexist); /* //just print debug message */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8822b1ant_action_hs(btcoexist); - return; - } - - - if (!wifi_connected) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is non connected-idle !!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - if (scan) - halbtc8822b1ant_action_wifi_not_connected_scan( - btcoexist); - else - halbtc8822b1ant_action_wifi_not_connected_asso_auth( - btcoexist); - } else - halbtc8822b1ant_action_wifi_not_connected(btcoexist); - } else /* wifi LPS/Busy */ - halbtc8822b1ant_action_wifi_connected(btcoexist); -} - -u32 halbtc8822b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val) -{ - u8 j; - u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0; - u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200, - 174, 151, 132, 115, 100, 86, 74, 62, 51, 42, - 32, 23, 15, 7, 0 - }; - - if (val == 0) - return 0; - - tmp = val; - - while (1) { - if (tmp == 1) - break; - else { - tmp = (tmp >> 1); - shiftcount++; - } - } - - - val_integerd_b = shiftcount + 1; - - tmp2 = 1; - for (j = 1; j <= val_integerd_b; j++) - tmp2 = tmp2 * 2; - - tmp = (val * 100) / tmp2; - tindex = tmp / 5; - - if (tindex > 20) - tindex = 20; - - val_fractiond_b = table_fraction[tindex]; - - result = val_integerd_b * 100 - val_fractiond_b; - - return result; - - -} - -void halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - - /* sw all off */ - halbtc8822b1ant_sw_mechanism(btcoexist, false); - - /* halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ - /* halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */ - - coex_sta->pop_event_cnt = 0; -} - -void halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up, IN boolean wifi_only) -{ - - u8 u8tmp = 0; - boolean wifi_under_5g = false; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - - - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u32tmp3, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - - /* Setup RF front end type */ - halbtc8822b1ant_set_rfe_type(btcoexist); - - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - - /* BT report packet sample rate */ - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* Enable BT counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - - /* Enable PTA (3-wire function form BT side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); - - /* Enable PTA (tx/rx signal form WiFi side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); - - /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);*/ - - /* enable GNT_WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0); - - if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) - halbtc8822b1ant_post_onoffstate_to_bt(btcoexist, TRUE); - - /* Antenna config */ - if (wifi_only) { - - coex_sta->concurrent_rx_mode_on = false; - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, BT_8822B_1ANT_PHASE_WLANONLY_INIT); - } else { - - coex_sta->concurrent_rx_mode_on = true; - - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, BT_8822B_1ANT_PHASE_COEX_INIT); - } - - - /* PTA parameter */ - halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, TRUE); - -} - - - -void halbtc8822b1ant_psd_showdata(IN struct btc_coexist *btcoexist) -{ - u8 *cli_buf = btcoexist->cli_buf; - u32 delta_freq_per_point; - u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n\n============[PSD info] (%d)============\n", - psd_scan->psd_gen_count); - CL_PRINTF(cli_buf); - - if (psd_scan->psd_gen_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n"); - CL_PRINTF(cli_buf); - return; - } - - if (psd_scan->psd_point == 0) - delta_freq_per_point = 0; - else - delta_freq_per_point = psd_scan->psd_band_width / - psd_scan->psd_point; - - /* if (psd_scan->is_psd_show_max_only) */ - if (0) { - psd_rep1 = psd_scan->psd_max_value / 100; - psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100; - - freq = ((psd_scan->real_cent_freq - 20) * 1000000 + - psd_scan->psd_max_value_point * delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq = %d.0%d MHz", - freq1, freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq = %d.%d MHz", - freq1, freq2); - - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - ", Value = %d.0%d dB, (%d)\n", - psd_rep1, psd_rep2, psd_scan->psd_max_value); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - ", Value = %d.%d dB, (%d)\n", - psd_rep1, psd_rep2, psd_scan->psd_max_value); - - CL_PRINTF(cli_buf); - } else { - m = psd_scan->psd_start_point; - n = psd_scan->psd_start_point; - i = 1; - j = 1; - - while (1) { - do { - freq = ((psd_scan->real_cent_freq - 20) * 1000000 + m * - delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (i == 1) { - if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.000", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.0%2d", freq1, - freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq%6d.%3d", freq1, - freq2); - } else if ((i % 8 == 0) || - (m == psd_scan->psd_stop_point)) { - if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.000\n", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.0%2d\n", freq1, freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.%3d\n", freq1, freq2); - } else { - if (freq2 == 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.000", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.0%2d", freq1, freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%6d.%3d", freq1, freq2); - } - - i++; - m++; - CL_PRINTF(cli_buf); - - } while ((i <= 8) && (m <= psd_scan->psd_stop_point)); - - - do { - psd_rep1 = psd_scan->psd_report_max_hold[n] / 100; - psd_rep2 = psd_scan->psd_report_max_hold[n] - psd_rep1 * - 100; - - if (j == 1) { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Val %7d.0%d", psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Val %7d.%d", psd_rep1, - psd_rep2); - } else if ((j % 8 == 0) || - (n == psd_scan->psd_stop_point)) { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.0%d\n", psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.%d\n", psd_rep1, psd_rep2); - } else { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.0%d", psd_rep1, psd_rep2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "%7d.%d", psd_rep1, psd_rep2); - } - - j++; - n++; - CL_PRINTF(cli_buf); - - } while ((j <= 8) && (n <= psd_scan->psd_stop_point)); - - if ((m > psd_scan->psd_stop_point) || - (n > psd_scan->psd_stop_point)) - break; - else { - i = 1; - j = 1; - } - - } - } - - -} - -void halbtc8822b1ant_psd_max_holddata(IN struct btc_coexist *btcoexist, - IN u32 gen_count) -{ - u32 i = 0, i_max = 0, val_max = 0; - - if (gen_count == 1) { - memcpy(psd_scan->psd_report_max_hold, - psd_scan->psd_report, - BT_8822B_1ANT_ANTDET_PSD_POINTS * sizeof(u32)); - - for (i = psd_scan->psd_start_point; - i <= psd_scan->psd_stop_point; i++) { - - } - - psd_scan->psd_max_value_point = 0; - psd_scan->psd_max_value = 0; - - } else { - for (i = psd_scan->psd_start_point; - i <= psd_scan->psd_stop_point; i++) { - if (psd_scan->psd_report[i] > - psd_scan->psd_report_max_hold[i]) - psd_scan->psd_report_max_hold[i] = - psd_scan->psd_report[i]; - - /* search Max Value */ - if (i == psd_scan->psd_start_point) { - i_max = i; - val_max = psd_scan->psd_report_max_hold[i]; - } else { - if (psd_scan->psd_report_max_hold[i] > - val_max) { - i_max = i; - val_max = psd_scan->psd_report_max_hold[i]; - } - } - - - - } - - psd_scan->psd_max_value_point = i_max; - psd_scan->psd_max_value = val_max; - - } - - -} - -u32 halbtc8822b1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) -{ - /* reg 0x808[9:0]: FFT data x */ - /* reg 0x808[22]: 0-->1 to get 1 FFT data y */ - /* reg 0x8b4[15:0]: FFT data y report */ - - u32 val = 0, psd_report = 0; - - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - - val &= 0xffbffc00; - val |= point; - - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - val |= 0x00400000; - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - - val = btcoexist->btc_read_4byte(btcoexist, 0x8b4); - - psd_report = val & 0x0000ffff; - - return psd_report; -} - - -void halbtc8822b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points, - IN u32 avgnum) -{ - u32 i, val, n, k = 0; - u32 points1 = 0, psd_report = 0; - u32 start_p = 0, stop_p = 0, delta_freq_per_point = 156250; - u32 psd_center_freq = 20 * 10 ^ 6, freq, freq1, freq2; - boolean outloop = false; - u8 flag = 0; - u32 tmp, psd_rep1, psd_rep2; - u32 wifi_original_channel = 1; - - psd_scan->is_psd_running = true; - - do { - switch (flag) { - case 0: /* Get PSD parameters */ - default: - - psd_scan->psd_band_width = 40 * 1000000; - psd_scan->psd_point = points; - psd_scan->psd_start_base = points / 2; - psd_scan->psd_avg_num = avgnum; - psd_scan->real_cent_freq = cent_freq; - psd_scan->real_offset = offset; - psd_scan->real_span = span; - - - points1 = psd_scan->psd_point; - delta_freq_per_point = psd_scan->psd_band_width / - psd_scan->psd_point; - - /* PSD point setup */ - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - val &= 0xffff0fff; - - switch (psd_scan->psd_point) { - case 128: - val |= 0x0; - break; - case 256: - default: - val |= 0x00004000; - break; - case 512: - val |= 0x00008000; - break; - case 1024: - val |= 0x0000c000; - break; - } - - switch (psd_scan->psd_avg_num) { - case 1: - val |= 0x0; - break; - case 8: - val |= 0x00001000; - break; - case 16: - val |= 0x00002000; - break; - case 32: - default: - val |= 0x00003000; - break; - } - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - flag = 1; - break; - case 1: /* calculate the PSD point index from freq/offset/span */ - psd_center_freq = psd_scan->psd_band_width / 2 + - offset * (1000000); - - start_p = psd_scan->psd_start_base + (psd_center_freq - - span * (1000000) / 2) / delta_freq_per_point; - psd_scan->psd_start_point = start_p - - psd_scan->psd_start_base; - - stop_p = psd_scan->psd_start_base + (psd_center_freq + - span * (1000000) / 2) / delta_freq_per_point; - psd_scan->psd_stop_point = stop_p - - psd_scan->psd_start_base - 1; - - flag = 2; - break; - case 2: /* set RF channel/BW/Mode */ - - /* set 3-wire off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x88c); - val |= 0x00300000; - btcoexist->btc_write_4byte(btcoexist, 0x88c, val); - - /* CCK off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x800); - val &= 0xfeffffff; - btcoexist->btc_write_4byte(btcoexist, 0x800, val); - - /* store WiFi original channel */ - wifi_original_channel = btcoexist->btc_get_rf_reg( - btcoexist, BTC_RF_A, 0x18, 0x3ff); - - /* Set RF channel */ - if (cent_freq == 2484) - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, - 0x18, 0x3ff, 0xe); - else - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, - 0x18, 0x3ff, (cent_freq - 2412) / 5 + - 1); /* WiFi TRx Mask on */ - - /* Set RF mode = Rx, RF Gain = 0x8a0 */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0, - 0xfffff, 0x308a0); - - /* Set RF Rx filter corner */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, 0x3e4); - - /* Set TRx mask off */ - /* un-lock TRx Mask setup */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, - 0x80, 0x1); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, - 0x1, 0x1); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - - flag = 3; - break; - case 3: - memset(psd_scan->psd_report, 0, - psd_scan->psd_point * sizeof(u32)); - start_p = psd_scan->psd_start_point + - psd_scan->psd_start_base; - stop_p = psd_scan->psd_stop_point + - psd_scan->psd_start_base + 1; - - i = start_p; - - while (i < stop_p) { - if (i >= points1) - psd_report = - halbtc8822b1ant_psd_getdata( - btcoexist, i - points1); - else - psd_report = - halbtc8822b1ant_psd_getdata( - btcoexist, i); - - if (psd_report == 0) - tmp = 0; - else - /* tmp = 20*log10((double)psd_report); */ - /* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */ - tmp = 6 * halbtc8822b1ant_psd_log2base( - btcoexist, psd_report); - - n = i - psd_scan->psd_start_base; - psd_scan->psd_report[n] = tmp; - psd_rep1 = psd_scan->psd_report[n] / 100; - psd_rep2 = psd_scan->psd_report[n] - psd_rep1 * - 100; - - freq = ((cent_freq - 20) * 1000000 + n * - delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - i++; - - k = 0; - - /* Add Delay between PSD point */ - while (1) { - if (k++ > 20000) - break; - } - - } - - flag = 100; - break; - case 99: /* error */ - - outloop = true; - break; - case 100: /* recovery */ - - /* set 3-wire on */ - val = btcoexist->btc_read_4byte(btcoexist, 0x88c); - val &= 0xffcfffff; - btcoexist->btc_write_4byte(btcoexist, 0x88c, val); - - /* CCK on */ - val = btcoexist->btc_read_4byte(btcoexist, 0x800); - val |= 0x01000000; - btcoexist->btc_write_4byte(btcoexist, 0x800, val); - - /* PSD off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - val &= 0xffbfffff; - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - /* TRx Mask on */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x780); - - /* lock TRx Mask setup */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, - 0x80, 0x0); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, - 0x1, 0x0); - - /* Set RF Rx filter corner */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, 0x0); - - /* restore WiFi original channel */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18, - 0x3ff, wifi_original_channel); - - outloop = true; - break; - - } - - } while (!outloop); - - - - psd_scan->is_psd_running = false; - - -} - -#if (BTC_COEX_OFFLOAD == 1) -void halbtc8822b1ant_wifi_info_notify(IN struct btc_coexist *btcoexist) -{ - u8 h2c_para[4] = {0}; - u8 opcode_ver = 0; - u8 ap_num = 0; - s32 wifi_rssi = 0; - boolean wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - h2c_para[0] = ap_num; /* AP number */ - h2c_para[1] = (u8)wifi_busy; /* Busy */ - h2c_para[2] = (u8)wifi_rssi; /* RSSI */ - - btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_INFO_NOTIFY, - opcode_ver, &h2c_para[0], 3); -} - -void halbtc8822b1ant_setManual(IN struct btc_coexist *btcoexist, - IN boolean manual) -{ - u8 h2c_para[4] = {0}; - u8 opcode_ver = 0; - u8 set_type = 0; - - if (manual) - set_type = 1; - else - set_type = 0; - - h2c_para[0] = set_type; /* set_type */ - - btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_SET_CONTROL, opcode_ver, - &h2c_para[0], 1); -} - -/* ************************************************************ - * work around function start with wa_halbtc8822b1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8822b1ant_ - * ************************************************************ */ - -void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{} -void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{} -void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{} -void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{} -void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - u8 h2c_para[4] = {0}; - u8 opcode_ver = 0; - u8 ips_notify = 0; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - ips_notify = 1; - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - } - - h2c_para[0] = ips_notify; /* IPS notify */ - h2c_para[1] = 0xff; /* LPS notify */ - h2c_para[2] = 0xff; /* RF state notify */ - h2c_para[3] = 0xff; /* pnp notify */ - - btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_POWER_STATE_NOTIFY, - opcode_ver, &h2c_para[0], 4); -} -void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - u8 h2c_para[4] = {0}; - u8 opcode_ver = 0; - u8 lps_notify = 0; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - lps_notify = 1; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - } - - h2c_para[0] = 0xff; /* IPS notify */ - h2c_para[1] = lps_notify; /* LPS notify */ - h2c_para[2] = 0xff; /* RF state notify */ - h2c_para[3] = 0xff; /* pnp notify */ - - btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_POWER_STATE_NOTIFY, - opcode_ver, &h2c_para[0], 4); -} - -void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_para[4] = {0}; - u8 opcode_ver = 0; - u8 scan_start = 0; - boolean under_4way = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (BTC_SCAN_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - scan_start = 1; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - } - - h2c_para[0] = scan_start; /* scan notify */ - h2c_para[1] = 0xff; /* connect notify */ - h2c_para[2] = 0xff; /* specific packet notify */ - if (under_4way) - h2c_para[3] = 1; /* under 4way progress */ - else - h2c_para[3] = 0; - - btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY, - opcode_ver, &h2c_para[0], 4); -} - -void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_para[4] = {0}; - u8 opcode_ver = 0; - u8 connect_start = 0; - boolean under_4way = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (BTC_ASSOCIATE_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - connect_start = 1; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - } - - h2c_para[0] = 0xff; /* scan notify */ - h2c_para[1] = connect_start; /* connect notify */ - h2c_para[2] = 0xff; /* specific packet notify */ - if (under_4way) - h2c_para[3] = 1; /* under 4way progress */ - else - h2c_para[3] = 0; - - btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY, - opcode_ver, &h2c_para[0], 4); -} - -void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u32 wifi_bw; - u8 wifi_central_chnl; - u8 h2c_para[5] = {0}; - u8 opcode_ver = 0; - u8 port = 0, connected = 0, freq = 0, bandwidth = 0, iot_peer = 0; - boolean wifi_under_5g = false; - - if (BTC_MEDIA_CONNECT == type) - connected = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - bandwidth = (u8)wifi_bw; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) - freq = 1; - else - freq = 0; - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); - - h2c_para[0] = (connected << 4) | - port; /* port need to be implemented in the future (p2p port, ...) */ - h2c_para[1] = (freq << 4) | bandwidth; - h2c_para[2] = wifi_central_chnl; - h2c_para[3] = iot_peer; - btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_STATUS_NOTIFY, - opcode_ver, &h2c_para[0], 4); -} - -void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_para[4] = {0}; - u8 opcode_ver = 0; - u8 connect_start = 0; - boolean under_4way = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - h2c_para[0] = 0xff; /* scan notify */ - h2c_para[1] = 0xff; /* connect notify */ - h2c_para[2] = type; /* specific packet notify */ - if (under_4way) - h2c_para[3] = 1; /* under 4way progress */ - else - h2c_para[3] = 0; - - btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY, - opcode_ver, &h2c_para[0], 4); -} - -void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{} -void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_para[4] = {0}; - u8 opcode_ver = 0; - u8 rfstate_notify = 0; - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - rfstate_notify = 1; - } else if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - } - - h2c_para[0] = 0xff; /* IPS notify */ - h2c_para[1] = 0xff; /* LPS notify */ - h2c_para[2] = rfstate_notify; /* RF state notify */ - h2c_para[3] = 0xff; /* pnp notify */ - - btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_POWER_STATE_NOTIFY, - opcode_ver, &h2c_para[0], 4); -} - -void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist) -{} -void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - u8 h2c_para[4] = {0}; - u8 opcode_ver = 0; - u8 pnp_notify = 0; - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - pnp_notify = 1; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - } - - h2c_para[0] = 0xff; /* IPS notify */ - h2c_para[1] = 0xff; /* LPS notify */ - h2c_para[2] = 0xff; /* RF state notify */ - h2c_para[3] = pnp_notify; /* pnp notify */ - - btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_POWER_STATE_NOTIFY, - opcode_ver, &h2c_para[0], 4); -} - -void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) -{} -void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist) -{ - - halbtc8822b1ant_wifi_info_notify(btcoexist); -} - -void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fa_of_dm, fa_cck; - u32 fw_ver = 0, bt_patch_ver = 0; - static u8 pop_report_in_10s = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - if (psd_scan->ant_det_try_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", - "Ant PG Num/ Mech/ Pos", - board_info->pg_ant_num, board_info->btdm_ant_num, - board_info->btdm_ant_pos); - CL_PRINTF(cli_buf); - } else { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %d (%d/%d/%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos", - board_info->pg_ant_num, board_info->btdm_ant_num_by_ant_det, - board_info->btdm_ant_pos, - psd_scan->ant_det_try_count, psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); - CL_PRINTF(cli_buf); - - if (board_info->btdm_ant_det_finish) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - CL_PRINTF(cli_buf); - } - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)", - "CoexVer/ FwVer/ PatchVer", - glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant, fw_ver, - bt_patch_ver, bt_patch_ver); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", - "WifibHiPri/ Ccklock/ CckEverLock", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), - (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No")); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); - CL_PRINTF(cli_buf); - - if (pop_report_in_10s >= 5) { - coex_sta->pop_event_cnt = 0; - pop_report_in_10s = 0; - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d / %d / %d / %d / %d", - "SCO/HID/PAN/A2DP/Hi-Pri", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist, - bt_link_info->bt_hi_pri_link_exist); - CL_PRINTF(cli_buf); - - { - bt_info_ext = coex_sta->bt_info_ext; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", - "BT Role/A2DP rate", - (bt_link_info->slave_role) ? "Slave" : "Master", - (bt_info_ext & BIT(0)) ? "BR" : "EDR"); - CL_PRINTF(cli_buf); - } - - /*bt info*/ - for (i = 0; i < BT_INFO_SRC_8822B_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8822b_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms] (before Manual)============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "SM[LowPenaltyRA]", - coex_dm->cur_low_penalty_ra); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "On" : "Off"), - (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); - - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "WL/BT Coex Table Type", - coex_sta->coex_table_type); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x778/0x6cc/IgnWlanAct", - u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa0); - u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "LTE Coex Table W_L/B_L", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa8); - u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xac); - u32tmp[2] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb0); - u32tmp[3] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "LTE Break Table W_L/B_L/L_W/L_B", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, - u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); - CL_PRINTF(cli_buf); - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - - u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s", - "LTE CoexOn/Path Ctrl Owner", - (int)((u32tmp[0]&BIT(7)) >> 7), ((u8tmp[0]&BIT(2)) ? "WL" : "BT")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "LTE 3Wire/OPMode/UART/UARTMode", - (int)((u32tmp[0]&BIT(6)) >> 6), (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), - (int)((u32tmp[0]&BIT(3)) >> 3), - (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s", - "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg", - (int)((u32tmp[0]&BIT(12)) >> 12), (int)((u32tmp[0]&BIT(14)) >> 14), - ((u8tmp[0]&BIT(3)) ? "On" : "Off")); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "GNT_WL/GNT_BT/LTE_Busy/UART_Busy", - (int)((u32tmp[0]&BIT(2)) >> 2), (int)((u32tmp[0]&BIT(3)) >> 3), - (int)((u32tmp[0]&BIT(1)) >> 1), (int)(u32tmp[0]&BIT(0))); - CL_PRINTF(cli_buf); - - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x4c6[4]/0x40[5] (WL/BT PTA)", - (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5)); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s", - "0x550(bcn ctrl)/0x522/4-RxAGC", - u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off"); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8); - u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c); - - fa_of_dm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000) - >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) + \ - ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] & - 0xffff) ; - fa_cck = (u8tmp[0] << 8) + u8tmp[1]; - - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0xc50/OFDM-CCA/OFDM-FA/CCK-FA", - u32tmp[1] & 0xff, u32tmp[0] & 0xffff, fa_of_dm, fa_cck); - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-Agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-Agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8822B_1ANT == 1) - /* halbtc8822b1ant_monitor_bt_ctr(btcoexist); */ -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} -void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{} -void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist) -{} -void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata) -{ - switch (op_code) { - case BTC_DBG_SET_COEX_MANUAL_CTRL: { - boolean manual = (boolean)*pdata; - - halbtc8822b1ant_setManual(btcoexist, manual); - } - break; - default: - break; - } -} - -#else -void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x0; - u16 u16tmp = 0x0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Execute 8822b 1-Ant PowerOn Setting!! xxxxxxxxxxxxxxxx\n"); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Ant Det Finish = %s, Ant Det Number = %d\n", - board_info->btdm_ant_det_finish ? "Yes" : "No", - board_info->btdm_ant_num_by_ant_det); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = true; - - /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - - /* set Path control owner to WiFi */ - halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8822B_1ANT_PCO_WLSIDE); - - /* set GNT_BT to high */ - halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to low */ - halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_LOW); - - /* set WLAN_ACT = 0 */ - //btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* SD1 Chunchu red x issue */ - btcoexist->btc_write_1byte(btcoexist, 0xff1a, 0x0); - - halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, TRUE); - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - - u8tmp = 0; - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - - if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); - - BTC_TRACE(trace_buf); - - -} - -void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (ini hw config) **********\n"); - - halbtc8822b1ant_init_hw_config(btcoexist, true, wifi_only); - btcoexist->stop_coex_dm = false; -} - -void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - - halbtc8822b1ant_init_coex_dm(btcoexist); - - halbtc8822b1ant_query_bt_info(btcoexist); -} - -void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fa_of_dm, fa_cck; - u32 fw_ver = 0, bt_patch_ver = 0; - static u8 pop_report_in_10s = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (display coexinfo) **********\n"); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** displaycoexinfostart, 0xcb4/0xcbd = 0x%x/0x%x\n", - btcoexist->btc_read_1byte(btcoexist, 0xcb4), - btcoexist->btc_read_1byte(btcoexist, 0xcbd)); - BTC_TRACE(trace_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - if (psd_scan->ant_det_try_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "Ant PG Num/ Mech/ Pos/ RFE", - board_info->pg_ant_num, board_info->btdm_ant_num, - board_info->btdm_ant_pos, - rfe_type->rfe_module_type); - CL_PRINTF(cli_buf); - } else { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %d/ %d (%d/%d/%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", - board_info->pg_ant_num, board_info->btdm_ant_num_by_ant_det, - board_info->btdm_ant_pos, - rfe_type->rfe_module_type, - psd_scan->ant_det_try_count, psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); - CL_PRINTF(cli_buf); - - if (board_info->btdm_ant_det_finish) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - CL_PRINTF(cli_buf); - } - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c", - "Version Coex/ Fw/ Patch/ Cut", - glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant, fw_ver, - bt_patch_ver, bt_patch_ver, coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", - "WifibHiPri/ Ccklock/ CckEverLock", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), - (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No")); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); - CL_PRINTF(cli_buf); - /*bt rssi */ - /*bt pop_even_cnt : bt retry*/ - - if (pop_report_in_10s >= 5) { - coex_sta->pop_event_cnt = 0; - pop_report_in_10s = 0; - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d / %d / %d / %d / %d", - "SCO/HID/PAN/A2DP/Hi-Pri", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist, - bt_link_info->bt_hi_pri_link_exist); - CL_PRINTF(cli_buf); - - { - bt_info_ext = coex_sta->bt_info_ext; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s / %d/ %x/ %04x", - "Role/A2DP Rate/Bitpool/Feature/Ver", - ((bt_link_info->slave_role) ? "Slave" : "Master"), - (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool, - coex_sta->bt_coex_supported_feature, - coex_sta->bt_coex_supported_version); - CL_PRINTF(cli_buf); - } - - /*bt info*/ - for (i = 0; i < BT_INFO_SRC_8822B_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8822b_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms] (before Manual)============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "SM[LowPenaltyRA]", - coex_dm->cur_low_penalty_ra); - CL_PRINTF(cli_buf); - - /*(ps)tdma*/ - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "On" : "Off"), - (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); - - CL_PRINTF(cli_buf); - - /*coex table type*/ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "WL/BT Coex Table Type", - coex_sta->coex_table_type); - CL_PRINTF(cli_buf); - - /*coex table :0x6c0 0x6c4 , break table: 0x6c8*/ - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - /*PTA : 0x778=1/3/d , WL BA,RTS,CTS :0x6cc H/L pri */ - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x778/0x6cc/IgnWlanAct", - u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - - /*LTE : WL/LTE coex table : 0xa0 */ - - u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa0); - - /*LTE : BT/LTE coex table : 0xa4 */ - u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "LTE Coex Table W_L/B_L", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); - CL_PRINTF(cli_buf); - - /*LTE : WL/LTE break table : 0xa8 */ - u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa8); - /*LTE : WL/LTE break table : 0xac */ - u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xac); - /*LTE : LTE/WL break table : 0xb0 */ - u32tmp[2] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb0); - /*LTE : LTE/BT break table : 0xb4 */ - u32tmp[3] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "LTE Break Table W_L/B_L/L_W/L_B", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, - u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); - CL_PRINTF(cli_buf); - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - /*ANT setting*/ - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb4); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xcbd); - u8tmp[3] = btcoexist->btc_read_1byte(btcoexist, 0x1991); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0xcb4/0xcbd/0x1991", - u8tmp[1], u8tmp[2], u8tmp[3]); - CL_PRINTF(cli_buf); - - /*LTE on/off , Path ctrl owner*/ - /*sy add*/ - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x64); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x73/ 0x4c/ 0x64[0]", u8tmp[0], (u32tmp[0] & ( BIT(24) | BIT(23) )) >> 23, u8tmp[1]&0x1); - CL_PRINTF(cli_buf); - - - u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s", - "LTE CoexOn/Path Ctrl Owner", - (int)((u32tmp[0]&BIT(7)) >> 7), ((u8tmp[0]&BIT(2)) ? "WL" : "BT")); - CL_PRINTF(cli_buf); - - /*LTE mode*/ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "LTE 3Wire/OPMode/UART/UARTMode", - (int)((u32tmp[0]&BIT(6)) >> 6), (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), - (int)((u32tmp[0]&BIT(3)) >> 3), - (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s", - "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg", - (int)((u32tmp[0]&BIT(12)) >> 12), (int)((u32tmp[0]&BIT(14)) >> 14), - ((u8tmp[0]&BIT(3)) ? "On" : "Off")); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "GNT_WL/GNT_BT/LTE_Busy/UART_Busy", - (int)((u32tmp[0]&BIT(2)) >> 2), (int)((u32tmp[0]&BIT(3)) >> 3), - (int)((u32tmp[0]&BIT(1)) >> 1), (int)(u32tmp[0]&BIT(0))); - CL_PRINTF(cli_buf); - - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x4c6[4]/0x40[5] (WL/BT PTA)", - (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5)); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x974); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522/0x974/0xc50", - u32tmp[0], u8tmp[0], u8tmp[1], u8tmp[2]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xf48); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xf4c); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xf08); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5c); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5d); - - fa_of_dm = (u32tmp[0] & 0xffff) + (u32tmp[1] & 0xffff); - - fa_cck = (u8tmp[0] << 8) + u8tmp[1]; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - u32tmp[2] & 0xffff, fa_cck, ((u32tmp[2] & 0xffff0000) >> 16), fa_of_dm); - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11ac", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11ac", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg); - CL_PRINTF(cli_buf); - - /*0x770:bt high pri trx*/ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - /*0x774:bt low pri trx*/ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); - - halbtc8822b1ant_read_score_board(btcoexist, &u16tmp[0]); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x", - "ScoreBoard[14:0] (from BT)", u16tmp[0]); - - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** displaycoexinfo end, 0xcb4/0xcbd = 0x%x/0x%x\n", - btcoexist->btc_read_1byte(btcoexist, 0xcb4), - btcoexist->btc_read_1byte(btcoexist, 0xcbd)); - BTC_TRACE(trace_buf); -} - - -void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - - if (BTC_IPS_ENTER == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, false); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8822B_1ANT_PHASE_WLAN_OFF); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (BTC_IPS_LEAVE == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, true); - - /*leave IPS : run ini hw config (exclude wifi only)*/ - halbtc8822b1ant_init_hw_config(btcoexist, false, false); - /*sw all off*/ - halbtc8822b1ant_init_coex_dm(btcoexist); - /*leave IPS : Query bt info*/ - halbtc8822b1ant_query_bt_info(btcoexist); - - coex_sta->under_ips = false; - } -} - -void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - - if (coex_sta->force_lps_on == true) { /* LPS No-32K */ - /* Write WL "Active" in Score-board for PS-TDMA */ - halbtc8822b1ant_post_activestate_to_bt(btcoexist, true); - - } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ - /* Write WL "Non-Active" in Score-board for Native-PS */ - halbtc8822b1ant_post_activestate_to_bt(btcoexist, false); - - } - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, true); - } -} - - -void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN notify()\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, true); - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_SCAN_START == type) - return; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - - if (BTC_SCAN_START_2G == type) { - coex_sta->wifi_is_high_pri_task = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2g SCAN START notify\n"); - BTC_TRACE(trace_buf); - - - if (!wifi_connected) /* non-connected scan */ - halbtc8822b1ant_action_wifi_not_connected_scan( - btcoexist); - else /* wifi is connected */ - halbtc8822b1ant_action_wifi_connected_scan(btcoexist); - - } else { - coex_sta->wifi_is_high_pri_task = false; - - /*WL scan finish , then get and update sacn ap numbers */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", coex_sta->scan_ap_num); - BTC_TRACE(trace_buf); - - if (!wifi_connected) /* non-connected scan */ - halbtc8822b1ant_action_wifi_not_connected(btcoexist); - else - halbtc8822b1ant_action_wifi_connected(btcoexist); - } - - -} - -void ex_halbtc8822b1ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - - boolean wifi_connected = false; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (switchband_notify) **********\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - - if(type == BTC_SWITCH_TO_5G) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_5G) **********\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_action_wifi_under5g(btcoexist); - return; - } else if (type == BTC_SWITCH_TO_24G_NoForScan) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_2G (no for scan)) **********\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_run_coexist_mechanism(btcoexist); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_2G) **********\n"); - BTC_TRACE(trace_buf); - - ex_halbtc8822b1ant_scan_notify(btcoexist, - BTC_SCAN_START_2G); - } - -} - -void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (connect notify) **********\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, true); - - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - - if ( (BTC_ASSOCIATE_5G_START == type) || (BTC_ASSOCIATE_5G_FINISH== type)) { - - if (BTC_ASSOCIATE_5G_START== type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (5G associate start notify) **********\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_action_wifi_under5g(btcoexist); - - } else if (BTC_ASSOCIATE_5G_FINISH == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (5G associate finish notify) **********\n"); - BTC_TRACE(trace_buf); - - } - - return; - -} - - - if (BTC_ASSOCIATE_START == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2G CONNECT START notify\n"); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - coex_dm->arp_cnt = 0; - - halbtc8822b1ant_action_wifi_not_connected_asso_auth(btcoexist); - - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2G CONNECT Finish notify\n"); - BTC_TRACE(trace_buf); - coex_sta->wifi_is_high_pri_task = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - if (!wifi_connected) /* non-connected scan */ - halbtc8822b1ant_action_wifi_not_connected(btcoexist); - else - halbtc8822b1ant_action_wifi_connected(btcoexist); - } - -} - -void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_under_b_mode = false; - boolean wifi_under_5g = false; - u32 cnt_bt_cal_chk = 0; - boolean is_in_mp_mode = false; - u8 u8tmp = 0; - u32 u32tmp1 = 0, u32tmp2 = 0; - - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if(wifi_under_5g) - { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 5g media notify \n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, true); - - halbtc8822b1ant_action_wifi_under5g(btcoexist); - return; - } - - - - if (BTC_MEDIA_CONNECT == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2g media connect notify"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, true); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (media status notity under b mode) **********\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - /* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */ - /* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (media status notity not under b mode) **********\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2g media disconnect notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, false); - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - - coex_sta->cck_ever_lock = false; - } - - halbtc8822b1ant_update_wifi_channel_info(btcoexist, type); - -} - -void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean under_4way = false, wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if(wifi_under_5g) - { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 5g special packet notify \n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_action_wifi_under5g(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (under_4way) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ---- under_4way!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - } else if (BTC_PACKET_ARP == type) { - - coex_dm->arp_cnt++; - - if (coex_sta->wifi_is_high_pri_task) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify -cnt = %d\n", coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - } - - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", type); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - } - - if (coex_sta->wifi_is_high_pri_task) - halbtc8822b1ant_action_wifi_connected_specific_packet(btcoexist); - -} - -void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean bt_busy = false; - boolean wifi_connected = false; - boolean wifi_under_5g = false; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - coex_sta->c2h_bt_info_req_sent = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (BtInfo Notify) **********\n" ); - BTC_TRACE(trace_buf); - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8822B_1ANT_MAX) - rsp_source = BT_INFO_SRC_8822B_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - - if (BT_INFO_SRC_8822B_1ANT_WIFI_FW != rsp_source) { - - /* if 0xff, it means BT is under WHCK test */ - if (bt_info == 0xff) - coex_sta->bt_whck_test = true; - else - coex_sta->bt_whck_test = false; - - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_page = true; - else - coex_sta->c2h_bt_page = false; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x80) - coex_sta->bt_create_connection = true; - else - coex_sta->bt_create_connection = false; - - /* unit: %, value-100 to translate to unit: dBm */ - coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - /* coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; */ - - if ((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) { - coex_sta->a2dp_bit_pool = - coex_sta->bt_info_c2h[rsp_source][6]; - } else - coex_sta->a2dp_bit_pool = 0; - - if (coex_sta->bt_info_c2h[rsp_source][1] & 0x9) - coex_sta->acl_busy = true; - else - coex_sta->acl_busy = false; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - - if ((!btcoexist->manual_control) && (!btcoexist->stop_coex_dm)) { - - /* Re-Init */ - if (coex_sta->bt_info_ext & BIT(1)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - halbtc8822b1ant_update_wifi_channel_info(btcoexist, - BTC_MEDIA_CONNECT); - else - halbtc8822b1ant_update_wifi_channel_info(btcoexist, - BTC_MEDIA_DISCONNECT); - } - - /* If Ignore_WLanAct && not SetUp_Link */ - if ((coex_sta->bt_info_ext & BIT(3)) && (!(coex_sta->bt_info_ext & BIT(2)))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8822B_1ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - } - - coex_sta->num_of_profile = 0; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - - coex_sta->bt_hi_pri_link_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8822B_1ANT_B_FTP) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8822B_1ANT_B_A2DP) { - coex_sta->a2dp_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8822B_1ANT_B_HID) { - coex_sta->hid_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) { - coex_sta->sco_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = false; - - } - - halbtc8822b1ant_update_bt_link_info(btcoexist); - - bt_info = bt_info & - 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ - - if (!(bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8822B_1ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8822B_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8822B_1ANT_B_ACL_BUSY) { - if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) - coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - halbtc8822b1ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, true); - halbtc8822b1ant_post_onoffstate_to_bt(btcoexist, true); - } else if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8822B_1ANT_PHASE_WLAN_OFF); - - halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - btcoexist->stop_coex_dm = true; - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, false); - halbtc8822b1ant_post_onoffstate_to_bt(btcoexist, false); - - } -} - -void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, false); - halbtc8822b1ant_post_onoffstate_to_bt(btcoexist, false); - - halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8822B_1ANT_PHASE_WLAN_OFF); - - halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8822b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, FALSE); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, false); - halbtc8822b1ant_post_onoffstate_to_bt(btcoexist, false); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8822B_1ANT_PHASE_WLAN_OFF); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 5); - - halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, FALSE); - - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_post_activestate_to_bt(btcoexist, true); - halbtc8822b1ant_post_onoffstate_to_bt(btcoexist, true); - - btcoexist->stop_coex_dm = false; - } -} - -void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], *****************Coex DM Reset*****************\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_init_hw_config(btcoexist, false, false); - halbtc8822b1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist) -{ - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ==========================Periodical===========================\n"); - BTC_TRACE(trace_buf); - -#if (BT_AUTO_REPORT_ONLY_8822B_1ANT == 0) - halbtc8822b1ant_query_bt_info(btcoexist); -#endif - - halbtc8822b1ant_monitor_bt_ctr(btcoexist); - halbtc8822b1ant_monitor_wifi_ctr(btcoexist); - - halbtc8822b1ant_monitor_bt_enable_disable(btcoexist); - - /* for 4-way, DHCP, EAPOL packet */ - if (coex_sta->specific_pkt_period_cnt > 0) { - - coex_sta->specific_pkt_period_cnt--; - - if ((coex_sta->specific_pkt_period_cnt == 0) && (coex_sta->wifi_is_high_pri_task)) - coex_sta->wifi_is_high_pri_task = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", (coex_sta->wifi_is_high_pri_task ? "Yes" : "No")); - BTC_TRACE(trace_buf); - } - - - if (coex_sta->bt_coex_supported_feature == 0) - coex_sta->bt_coex_supported_feature = btcoexist->btc_get_bt_coex_supported_feature(btcoexist); - - if ( (coex_sta->bt_coex_supported_version == 0) && (!coex_sta->bt_disabled) ) - coex_sta->bt_coex_supported_version = btcoexist->btc_get_bt_coex_supported_version(btcoexist); - - if (halbtc8822b1ant_is_wifi_status_changed(btcoexist)) - halbtc8822b1ant_run_coexist_mechanism(btcoexist); - -} - -void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ -} - -void ex_halbtc8822b1ant_antenna_isolation(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - - -} - -void ex_halbtc8822b1ant_psd_scan(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - - -} - -void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist) -{ - -} - -void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata) -{} -#endif /* #if(BTC_COEX_OFFLOAD == 1) */ - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ - diff --git a/hal/btc/HalBtc8822b1Ant.h b/hal/btc/HalBtc8822b1Ant.h deleted file mode 100644 index 4f091f1..0000000 --- a/hal/btc/HalBtc8822b1Ant.h +++ /dev/null @@ -1,408 +0,0 @@ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8822B_SUPPORT == 1) - -/* ******************************************* - * The following is for 8822B 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8822B_1ANT 1 - -#define BT_INFO_8822B_1ANT_B_FTP BIT(7) -#define BT_INFO_8822B_1ANT_B_A2DP BIT(6) -#define BT_INFO_8822B_1ANT_B_HID BIT(5) -#define BT_INFO_8822B_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8822B_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8822B_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8822B_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8822B_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8822B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT 2 - -#define BT_8822B_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ - -/* for Antenna detection */ -#define BT_8822B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 -#define BT_8822B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 -#define BT_8822B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 -#define BT_8822B_1ANT_ANTDET_PSDTHRES_1ANT 35 -#define BT_8822B_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8822B_1ANT_ANTDET_ENABLE 0 -#define BT_8822B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0 - -#define BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 -#define BT_8822B_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ - - -enum bt_8822b_1ant_signal_state { - BT_8822B_1ANT_SIG_STA_SET_TO_LOW = 0x0, - BT_8822B_1ANT_SIG_STA_SET_BY_HW = 0x0, - BT_8822B_1ANT_SIG_STA_SET_TO_HIGH = 0x1, - BT_8822B_1ANT_SIG_STA_MAX -}; - -enum bt_8822b_1ant_path_ctrl_owner { - BT_8822B_1ANT_PCO_BTSIDE = 0x0, - BT_8822B_1ANT_PCO_WLSIDE = 0x1, - BT_8822B_1ANT_PCO_MAX -}; - -enum bt_8822b_1ant_gnt_ctrl_type { - BT_8822B_1ANT_GNT_CTRL_BY_PTA = 0x0, - BT_8822B_1ANT_GNT_CTRL_BY_SW = 0x1, - BT_8822B_1ANT_GNT_CTRL_MAX -}; - -enum bt_8822b_1ant_gnt_ctrl_block { - BT_8822B_1ANT_GNT_BLOCK_RFC_BB = 0x0, - BT_8822B_1ANT_GNT_BLOCK_RFC = 0x1, - BT_8822B_1ANT_GNT_BLOCK_BB = 0x2, - BT_8822B_1ANT_GNT_BLOCK_MAX -}; - -enum bt_8822b_1ant_lte_coex_table_type { - BT_8822B_1ANT_CTT_WL_VS_LTE = 0x0, - BT_8822B_1ANT_CTT_BT_VS_LTE = 0x1, - BT_8822B_1ANT_CTT_MAX -}; - -enum bt_8822b_1ant_lte_break_table_type { - BT_8822B_1ANT_LBTT_WL_BREAK_LTE = 0x0, - BT_8822B_1ANT_LBTT_BT_BREAK_LTE = 0x1, - BT_8822B_1ANT_LBTT_LTE_BREAK_WL = 0x2, - BT_8822B_1ANT_LBTT_LTE_BREAK_BT = 0x3, - BT_8822B_1ANT_LBTT_MAX -}; - -enum bt_info_src_8822b_1ant { - BT_INFO_SRC_8822B_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8822B_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8822B_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8822B_1ANT_MAX -}; - -enum bt_8822b_1ant_bt_status { - BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8822B_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8822B_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8822B_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8822B_1ANT_BT_STATUS_MAX -}; - -enum bt_8822b_1ant_wifi_status { - BT_8822B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8822B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8822B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8822B_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8822b_1ant_coex_algo { - BT_8822B_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8822B_1ANT_COEX_ALGO_SCO = 0x1, - BT_8822B_1ANT_COEX_ALGO_HID = 0x2, - BT_8822B_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8822B_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8822B_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8822B_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8822B_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8822B_1ANT_COEX_ALGO_MAX = 0xb, -}; - -enum bt_8822b_1ant_ext_ant_switch_type { - BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT = 0x0, - BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SP3T = 0x1, - BT_8822B_1ANT_EXT_ANT_SWITCH_MAX -}; - -enum bt_8822b_1ant_ext_ant_switch_ctrl_type { - BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, - BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, - BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, - BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, - BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, - BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_MAX -}; - -enum bt_8822b_1ant_ext_ant_switch_pos_type { - BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT = 0x0, - BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG = 0x1, - BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA = 0x2, - BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE = 0x3, - BT_8822B_1ANT_EXT_ANT_SWITCH_TO_MAX -}; - -enum bt_8822b_1ant_phase{ - BT_8822B_1ANT_PHASE_COEX_INIT = 0x0, - BT_8822B_1ANT_PHASE_WLANONLY_INIT = 0x1, - BT_8822B_1ANT_PHASE_WLAN_OFF = 0x2, - BT_8822B_1ANT_PHASE_2G_RUNTIME = 0x3, - BT_8822B_1ANT_PHASE_5G_RUNTIME = 0x4, - BT_8822B_1ANT_PHASE_BTMPMODE = 0x5, - BT_8822B_1ANT_PHASE_MAX -}; - - -struct coex_dm_8822b_1ant { - /* hw setting */ - u32 pre_ant_pos_type; - u32 cur_ant_pos_type; - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u32 pre_ext_ant_switch_status; - u32 cur_ext_ant_switch_status; - - u8 error_condition; -}; - -struct coex_sta_8822b_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - boolean bt_hi_pri_link_exist; - u8 num_of_profile; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - s8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8822B_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8822B_1ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - u8 bt_retry_cnt; - u8 bt_info_ext; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_agg; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_agg; - - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; - u8 coex_table_type; - - boolean force_lps_on; - u32 wrong_profile_notification; - - boolean concurrent_rx_mode_on; - - u32 special_pkt_period_cnt; - - u16 score_board; - - u8 a2dp_bit_pool; - u8 cut_version; - boolean acl_busy; - boolean wl_rf_off_on_event; - boolean bt_create_connection; - boolean run_time_state; - - u32 bt_coex_supported_feature; - u32 bt_coex_supported_version; -}; - -struct rfe_type_8822b_1ant{ - - u8 rfe_module_type; - boolean ext_ant_switch_exist; - u8 ext_ant_switch_type; - u8 ext_ant_switch_ctrl_polarity; /* iF 0: ANTSW(rfe_sel9)=0, ANTSWB(rfe_sel8)=1 => Ant to BT/5G */ -}; - - -#define BT_8822B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ -#define BT_8822B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ -#define BT_8822B_1ANT_ANTDET_BUF_LEN 16 - -struct psdscan_sta_8822b_1ant { - - u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ - u32 ant_det_bt_tx_time; - u32 ant_det_pre_psdscan_peak_val; - boolean ant_det_is_ant_det_available; - u32 ant_det_psd_scan_peak_val; - boolean ant_det_is_btreply_available; - u32 ant_det_psd_scan_peak_freq; - - u8 ant_det_result; - u8 ant_det_peak_val[BT_8822B_1ANT_ANTDET_BUF_LEN]; - u8 ant_det_peak_freq[BT_8822B_1ANT_ANTDET_BUF_LEN]; - u32 ant_det_try_count; - u32 ant_det_fail_count; - u32 ant_det_inteval_count; - u32 ant_det_thres_offset; - - u32 real_cent_freq; - s32 real_offset; - u32 real_span; - - u32 psd_band_width; /* unit: Hz */ - u32 psd_point; /* 128/256/512/1024 */ - u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_start_point; - u32 psd_stop_point; - u32 psd_max_value_point; - u32 psd_max_value; - u32 psd_start_base; - u32 psd_avg_num; /* 1/8/16/32 */ - u32 psd_gen_count; - boolean is_psd_running; - boolean is_psd_show_max_only; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8822b1ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8822b1ant_ScoreBoardStatusNotify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); -void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8822b1ant_antenna_isolation(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); - -void ex_halbtc8822b1ant_psd_scan(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist); - -void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata); - -#else -#define ex_halbtc8822b1ant_power_on_setting(btcoexist) -#define ex_halbtc8822b1ant_pre_load_firmware(btcoexist) -#define ex_halbtc8822b1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8822b1ant_init_coex_dm(btcoexist) -#define ex_halbtc8822b1ant_ips_notify(btcoexist, type) -#define ex_halbtc8822b1ant_lps_notify(btcoexist, type) -#define ex_halbtc8822b1ant_scan_notify(btcoexist, type) -#define ex_halbtc8822b1ant_switchband_notify(btcoexist, type) -#define ex_halbtc8822b1ant_connect_notify(btcoexist, type) -#define ex_halbtc8822b1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8822b1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8822b1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8822b1ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8822b1ant_halt_notify(btcoexist) -#define ex_halbtc8822b1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8822b1ant_ScoreBoardStatusNotify(btcoexist, tmp_buf, length) -#define ex_halbtc8822b1ant_coex_dm_reset(btcoexist) -#define ex_halbtc8822b1ant_periodical(btcoexist) -#define ex_halbtc8822b1ant_display_coex_info(btcoexist) -#define ex_halbtc8822b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8822b1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8822b1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8822b1ant_display_ant_detection(btcoexist) -#define ex_halbtc8822b1ant_dbg_control(btcoexist, op_code, op_len, pdata) -#endif - -#endif diff --git a/hal/btc/HalBtcOutSrc.h b/hal/btc/HalBtcOutSrc.h deleted file mode 100644 index 8ec3299..0000000 --- a/hal/btc/HalBtcOutSrc.h +++ /dev/null @@ -1,937 +0,0 @@ -#ifndef __HALBTC_OUT_SRC_H__ -#define __HALBTC_OUT_SRC_H__ - - -#define BTC_COEX_OFFLOAD 0 -#define BTC_TMP_BUF_SHORT 20 - -extern u1Byte gl_btc_trace_buf[]; -#define BTC_SPRINTF rsprintf -#define BTC_TRACE(_MSG_) RT_TRACE(COMP_COEX, DBG_LOUD, (_MSG_)) -#define BT_PrintData(adapter, _MSG_, len, data) RTW_DBG_DUMP((_MSG_), data, len) - - -#define NORMAL_EXEC FALSE -#define FORCE_EXEC TRUE - -#define BTC_RF_OFF 0x0 -#define BTC_RF_ON 0x1 - -#define BTC_RF_A 0x0 -#define BTC_RF_B 0x1 -#define BTC_RF_C 0x2 -#define BTC_RF_D 0x3 - -#define BTC_SMSP SINGLEMAC_SINGLEPHY -#define BTC_DMDP DUALMAC_DUALPHY -#define BTC_DMSP DUALMAC_SINGLEPHY -#define BTC_MP_UNKNOWN 0xff - -#define BT_COEX_ANT_TYPE_PG 0 -#define BT_COEX_ANT_TYPE_ANTDIV 1 -#define BT_COEX_ANT_TYPE_DETECTED 2 - -#define BTC_MIMO_PS_STATIC 0 // 1ss -#define BTC_MIMO_PS_DYNAMIC 1 // 2ss - -#define BTC_RATE_DISABLE 0 -#define BTC_RATE_ENABLE 1 - -// single Antenna definition -#define BTC_ANT_PATH_WIFI 0 -#define BTC_ANT_PATH_BT 1 -#define BTC_ANT_PATH_PTA 2 -#define BTC_ANT_PATH_WIFI5G 3 -#define BTC_ANT_PATH_AUTO 4 -// dual Antenna definition -#define BTC_ANT_WIFI_AT_MAIN 0 -#define BTC_ANT_WIFI_AT_AUX 1 -#define BTC_ANT_WIFI_AT_DIVERSITY 2 -// coupler Antenna definition -#define BTC_ANT_WIFI_AT_CPL_MAIN 0 -#define BTC_ANT_WIFI_AT_CPL_AUX 1 - -typedef enum _BTC_POWERSAVE_TYPE{ - BTC_PS_WIFI_NATIVE = 0, // wifi original power save behavior - BTC_PS_LPS_ON = 1, - BTC_PS_LPS_OFF = 2, - BTC_PS_MAX -} BTC_POWERSAVE_TYPE, *PBTC_POWERSAVE_TYPE; - -typedef enum _BTC_BT_REG_TYPE{ - BTC_BT_REG_RF = 0, - BTC_BT_REG_MODEM = 1, - BTC_BT_REG_BLUEWIZE = 2, - BTC_BT_REG_VENDOR = 3, - BTC_BT_REG_LE = 4, - BTC_BT_REG_MAX -} BTC_BT_REG_TYPE, *PBTC_BT_REG_TYPE; - -typedef enum _BTC_CHIP_INTERFACE{ - BTC_INTF_UNKNOWN = 0, - BTC_INTF_PCI = 1, - BTC_INTF_USB = 2, - BTC_INTF_SDIO = 3, - BTC_INTF_MAX -} BTC_CHIP_INTERFACE, *PBTC_CHIP_INTERFACE; - -typedef enum _BTC_CHIP_TYPE{ - BTC_CHIP_UNDEF = 0, - BTC_CHIP_CSR_BC4 = 1, - BTC_CHIP_CSR_BC8 = 2, - BTC_CHIP_RTL8723A = 3, - BTC_CHIP_RTL8821 = 4, - BTC_CHIP_RTL8723B = 5, - BTC_CHIP_MAX -} BTC_CHIP_TYPE, *PBTC_CHIP_TYPE; - -// following is for wifi link status -#define WIFI_STA_CONNECTED BIT0 -#define WIFI_AP_CONNECTED BIT1 -#define WIFI_HS_CONNECTED BIT2 -#define WIFI_P2P_GO_CONNECTED BIT3 -#define WIFI_P2P_GC_CONNECTED BIT4 - -// following is for command line utility -#define CL_SPRINTF rsprintf -#define CL_PRINTF DCMD_Printf - -struct btc_board_info{ - /* The following is some board information */ - u8 bt_chip_type; - u8 pg_ant_num; /* pg ant number */ - u8 btdm_ant_num; /* ant number for btdm */ - u8 btdm_ant_num_by_ant_det; /* ant number for btdm after antenna detection */ - u8 btdm_ant_pos; /* Bryant Add to indicate Antenna Position for (pg_ant_num = 2) && (btdm_ant_num =1) (DPDT+1Ant case) */ - u8 single_ant_path; /* current used for 8723b only, 1=>s0, 0=>s1 */ - boolean tfbga_package; /* for Antenna detect threshold */ - boolean btdm_ant_det_finish; - u8 ant_type; - u8 rfe_type; - u8 ant_div_cfg; -}; - -typedef enum _BTC_DBG_OPCODE{ - BTC_DBG_SET_COEX_NORMAL = 0x0, - BTC_DBG_SET_COEX_WIFI_ONLY = 0x1, - BTC_DBG_SET_COEX_BT_ONLY = 0x2, - BTC_DBG_SET_COEX_DEC_BT_PWR = 0x3, - BTC_DBG_SET_COEX_BT_AFH_MAP = 0x4, - BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT = 0x5, - BTC_DBG_SET_COEX_MANUAL_CTRL = 0x6, - BTC_DBG_MAX -}BTC_DBG_OPCODE,*PBTC_DBG_OPCODE; - -typedef enum _BTC_RSSI_STATE{ - BTC_RSSI_STATE_HIGH = 0x0, - BTC_RSSI_STATE_MEDIUM = 0x1, - BTC_RSSI_STATE_LOW = 0x2, - BTC_RSSI_STATE_STAY_HIGH = 0x3, - BTC_RSSI_STATE_STAY_MEDIUM = 0x4, - BTC_RSSI_STATE_STAY_LOW = 0x5, - BTC_RSSI_MAX -}BTC_RSSI_STATE,*PBTC_RSSI_STATE; -#define BTC_RSSI_HIGH(_rssi_) ((_rssi_==BTC_RSSI_STATE_HIGH||_rssi_==BTC_RSSI_STATE_STAY_HIGH)? TRUE:FALSE) -#define BTC_RSSI_MEDIUM(_rssi_) ((_rssi_==BTC_RSSI_STATE_MEDIUM||_rssi_==BTC_RSSI_STATE_STAY_MEDIUM)? TRUE:FALSE) -#define BTC_RSSI_LOW(_rssi_) ((_rssi_==BTC_RSSI_STATE_LOW||_rssi_==BTC_RSSI_STATE_STAY_LOW)? TRUE:FALSE) - -typedef enum _BTC_WIFI_ROLE{ - BTC_ROLE_STATION = 0x0, - BTC_ROLE_AP = 0x1, - BTC_ROLE_IBSS = 0x2, - BTC_ROLE_HS_MODE = 0x3, - BTC_ROLE_MAX -}BTC_WIFI_ROLE,*PBTC_WIFI_ROLE; - -typedef enum _BTC_WIRELESS_FREQ{ - BTC_FREQ_2_4G = 0x0, - BTC_FREQ_5G = 0x1, - BTC_FREQ_MAX -}BTC_WIRELESS_FREQ,*PBTC_WIRELESS_FREQ; - -typedef enum _BTC_WIFI_BW_MODE{ - BTC_WIFI_BW_LEGACY = 0x0, - BTC_WIFI_BW_HT20 = 0x1, - BTC_WIFI_BW_HT40 = 0x2, - BTC_WIFI_BW_HT80 = 0x3, - BTC_WIFI_BW_HT160 = 0x4, - BTC_WIFI_BW_MAX -}BTC_WIFI_BW_MODE,*PBTC_WIFI_BW_MODE; - -typedef enum _BTC_WIFI_TRAFFIC_DIR{ - BTC_WIFI_TRAFFIC_TX = 0x0, - BTC_WIFI_TRAFFIC_RX = 0x1, - BTC_WIFI_TRAFFIC_MAX -}BTC_WIFI_TRAFFIC_DIR,*PBTC_WIFI_TRAFFIC_DIR; - -typedef enum _BTC_WIFI_PNP{ - BTC_WIFI_PNP_WAKE_UP = 0x0, - BTC_WIFI_PNP_SLEEP = 0x1, - BTC_WIFI_PNP_MAX -}BTC_WIFI_PNP,*PBTC_WIFI_PNP; - -typedef enum _BTC_IOT_PEER -{ - BTC_IOT_PEER_UNKNOWN = 0, - BTC_IOT_PEER_REALTEK = 1, - BTC_IOT_PEER_REALTEK_92SE = 2, - BTC_IOT_PEER_BROADCOM = 3, - BTC_IOT_PEER_RALINK = 4, - BTC_IOT_PEER_ATHEROS = 5, - BTC_IOT_PEER_CISCO = 6, - BTC_IOT_PEER_MERU = 7, - BTC_IOT_PEER_MARVELL = 8, - BTC_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17 - BTC_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP - BTC_IOT_PEER_AIRGO = 11, - BTC_IOT_PEER_INTEL = 12, - BTC_IOT_PEER_RTK_APCLIENT = 13, - BTC_IOT_PEER_REALTEK_81XX = 14, - BTC_IOT_PEER_REALTEK_WOW = 15, - BTC_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16, - BTC_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17, - BTC_IOT_PEER_MAX, -}BTC_IOT_PEER, *PBTC_IOT_PEER; - -//for 8723b-d cut large current issue -typedef enum _BTC_WIFI_COEX_STATE{ - BTC_WIFI_STAT_INIT, - BTC_WIFI_STAT_IQK, - BTC_WIFI_STAT_NORMAL_OFF, - BTC_WIFI_STAT_MP_OFF, - BTC_WIFI_STAT_NORMAL, - BTC_WIFI_STAT_ANT_DIV, - BTC_WIFI_STAT_MAX -}BTC_WIFI_COEX_STATE,*PBTC_WIFI_COEX_STATE; - -typedef enum _BTC_ANT_TYPE{ - BTC_ANT_TYPE_0, - BTC_ANT_TYPE_1, - BTC_ANT_TYPE_2, - BTC_ANT_TYPE_3, - BTC_ANT_TYPE_4, - BTC_ANT_TYPE_MAX -}BTC_ANT_TYPE,*PBTC_ANT_TYPE; - -typedef enum _BTC_VENDOR{ - BTC_VENDOR_LENOVO, - BTC_VENDOR_ASUS, - BTC_VENDOR_OTHER -}BTC_VENDOR,*PBTC_VENDOR; - - -// defined for BFP_BTC_GET -typedef enum _BTC_GET_TYPE{ - // type BOOLEAN - BTC_GET_BL_HS_OPERATION, - BTC_GET_BL_HS_CONNECTING, - BTC_GET_BL_WIFI_CONNECTED, - BTC_GET_BL_WIFI_BUSY, - BTC_GET_BL_WIFI_SCAN, - BTC_GET_BL_WIFI_LINK, - BTC_GET_BL_WIFI_ROAM, - BTC_GET_BL_WIFI_4_WAY_PROGRESS, - BTC_GET_BL_WIFI_UNDER_5G, - BTC_GET_BL_WIFI_AP_MODE_ENABLE, - BTC_GET_BL_WIFI_ENABLE_ENCRYPTION, - BTC_GET_BL_WIFI_UNDER_B_MODE, - BTC_GET_BL_EXT_SWITCH, - BTC_GET_BL_WIFI_IS_IN_MP_MODE, - BTC_GET_BL_IS_ASUS_8723B, - - // type s4Byte - BTC_GET_S4_WIFI_RSSI, - BTC_GET_S4_HS_RSSI, - - // type u4Byte - BTC_GET_U4_WIFI_BW, - BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, - BTC_GET_U4_WIFI_FW_VER, - BTC_GET_U4_WIFI_LINK_STATUS, - BTC_GET_U4_BT_PATCH_VER, - BTC_GET_U4_VENDOR, - BTC_GET_U4_WIFI_IQK_TOTAL, - BTC_GET_U4_WIFI_IQK_OK, - BTC_GET_U4_WIFI_IQK_FAIL, - - // type u1Byte - BTC_GET_U1_WIFI_DOT11_CHNL, - BTC_GET_U1_WIFI_CENTRAL_CHNL, - BTC_GET_U1_WIFI_HS_CHNL, - BTC_GET_U1_WIFI_P2P_CHNL, - BTC_GET_U1_MAC_PHY_MODE, - BTC_GET_U1_AP_NUM, - BTC_GET_U1_ANT_TYPE, - BTC_GET_U1_IOT_PEER, - - //===== for 1Ant ====== - BTC_GET_U1_LPS_MODE, - - BTC_GET_MAX -}BTC_GET_TYPE,*PBTC_GET_TYPE; - -// defined for BFP_BTC_SET -typedef enum _BTC_SET_TYPE{ - // type BOOLEAN - BTC_SET_BL_BT_DISABLE, - BTC_SET_BL_BT_TRAFFIC_BUSY, - BTC_SET_BL_BT_LIMITED_DIG, - BTC_SET_BL_FORCE_TO_ROAM, - BTC_SET_BL_TO_REJ_AP_AGG_PKT, - BTC_SET_BL_BT_CTRL_AGG_SIZE, - BTC_SET_BL_INC_SCAN_DEV_NUM, - BTC_SET_BL_BT_TX_RX_MASK, - BTC_SET_BL_MIRACAST_PLUS_BT, - - // type u1Byte - BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, - BTC_SET_U1_AGG_BUF_SIZE, - - // type trigger some action - BTC_SET_ACT_GET_BT_RSSI, - BTC_SET_ACT_AGGREGATE_CTRL, - BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, - //===== for 1Ant ====== - // type BOOLEAN - - // type u1Byte - BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, - BTC_SET_U1_LPS_VAL, - BTC_SET_U1_RPWM_VAL, - // type trigger some action - BTC_SET_ACT_LEAVE_LPS, - BTC_SET_ACT_ENTER_LPS, - BTC_SET_ACT_NORMAL_LPS, - BTC_SET_ACT_DISABLE_LOW_POWER, - BTC_SET_ACT_UPDATE_RAMASK, - BTC_SET_ACT_SEND_MIMO_PS, - // BT Coex related - BTC_SET_ACT_CTRL_BT_INFO, - BTC_SET_ACT_CTRL_BT_COEX, - BTC_SET_ACT_CTRL_8723B_ANT, - //================= - BTC_SET_MAX -}BTC_SET_TYPE,*PBTC_SET_TYPE; - -typedef enum _BTC_DBG_DISP_TYPE{ - BTC_DBG_DISP_COEX_STATISTICS = 0x0, - BTC_DBG_DISP_BT_LINK_INFO = 0x1, - BTC_DBG_DISP_WIFI_STATUS = 0x2, - BTC_DBG_DISP_MAX -}BTC_DBG_DISP_TYPE,*PBTC_DBG_DISP_TYPE; - -typedef enum _BTC_NOTIFY_TYPE_IPS{ - BTC_IPS_LEAVE = 0x0, - BTC_IPS_ENTER = 0x1, - BTC_IPS_MAX -}BTC_NOTIFY_TYPE_IPS,*PBTC_NOTIFY_TYPE_IPS; -typedef enum _BTC_NOTIFY_TYPE_LPS{ - BTC_LPS_DISABLE = 0x0, - BTC_LPS_ENABLE = 0x1, - BTC_LPS_MAX -}BTC_NOTIFY_TYPE_LPS,*PBTC_NOTIFY_TYPE_LPS; -typedef enum _BTC_NOTIFY_TYPE_SCAN{ - BTC_SCAN_FINISH = 0x0, - BTC_SCAN_START = 0x1, - BTC_SCAN_START_2G = 0x2, - BTC_SCAN_MAX -}BTC_NOTIFY_TYPE_SCAN,*PBTC_NOTIFY_TYPE_SCAN; -typedef enum _BTC_NOTIFY_TYPE_SWITCHBAND{ - BTC_NOT_SWITCH = 0x0, - BTC_SWITCH_TO_24G = 0x1, - BTC_SWITCH_TO_5G = 0x2, - BTC_SWITCH_TO_24G_NoForScan = 0x3, - BTC_SWITCH_MAX -}BTC_NOTIFY_TYPE_SWITCHBAND,*PBTC_NOTIFY_TYPE_SWITCHBAND; -typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE{ - BTC_ASSOCIATE_FINISH = 0x0, - BTC_ASSOCIATE_START = 0x1, - BTC_ASSOCIATE_5G_FINISH = 0x2, - BTC_ASSOCIATE_5G_START = 0x3, - BTC_ASSOCIATE_MAX -}BTC_NOTIFY_TYPE_ASSOCIATE,*PBTC_NOTIFY_TYPE_ASSOCIATE; -typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS{ - BTC_MEDIA_DISCONNECT = 0x0, - BTC_MEDIA_CONNECT = 0x1, - BTC_MEDIA_MAX -}BTC_NOTIFY_TYPE_MEDIA_STATUS,*PBTC_NOTIFY_TYPE_MEDIA_STATUS; -typedef enum _BTC_NOTIFY_TYPE_SPECIFIC_PACKET{ - BTC_PACKET_UNKNOWN = 0x0, - BTC_PACKET_DHCP = 0x1, - BTC_PACKET_ARP = 0x2, - BTC_PACKET_EAPOL = 0x3, - BTC_PACKET_MAX -}BTC_NOTIFY_TYPE_SPECIFIC_PACKET,*PBTC_NOTIFY_TYPE_SPECIFIC_PACKET; -typedef enum _BTC_NOTIFY_TYPE_STACK_OPERATION{ - BTC_STACK_OP_NONE = 0x0, - BTC_STACK_OP_INQ_PAGE_PAIR_START = 0x1, - BTC_STACK_OP_INQ_PAGE_PAIR_FINISH = 0x2, - BTC_STACK_OP_MAX -}BTC_NOTIFY_TYPE_STACK_OPERATION,*PBTC_NOTIFY_TYPE_STACK_OPERATION; - -//Bryant Add -typedef enum _BTC_ANTENNA_POS{ - BTC_ANTENNA_AT_MAIN_PORT = 0x1, - BTC_ANTENNA_AT_AUX_PORT = 0x2, -}BTC_ANTENNA_POS,*PBTC_ANTENNA_POS; - -//Bryant Add -typedef enum _BTC_BT_OFFON{ - BTC_BT_OFF = 0x0, - BTC_BT_ON = 0x1, -}BTC_BTOFFON,*PBTC_BT_OFFON; - -//================================================== -// For following block is for coex offload -//================================================== -typedef struct _COL_H2C{ - u1Byte opcode; - u1Byte opcode_ver:4; - u1Byte req_num:4; - u1Byte buf[1]; -}COL_H2C, *PCOL_H2C; - -#define COL_C2H_ACK_HDR_LEN 3 -typedef struct _COL_C2H_ACK{ - u1Byte status; - u1Byte opcode_ver:4; - u1Byte req_num:4; - u1Byte ret_len; - u1Byte buf[1]; -}COL_C2H_ACK, *PCOL_C2H_ACK; - -#define COL_C2H_IND_HDR_LEN 3 -typedef struct _COL_C2H_IND{ - u1Byte type; - u1Byte version; - u1Byte length; - u1Byte data[1]; -}COL_C2H_IND, *PCOL_C2H_IND; - -//============================================ -// NOTE: for debug message, the following define should match -// the strings in coexH2cResultString. -//============================================ -typedef enum _COL_H2C_STATUS{ - // c2h status - COL_STATUS_C2H_OK = 0x00, // Wifi received H2C request and check content ok. - COL_STATUS_C2H_UNKNOWN = 0x01, // Not handled routine - COL_STATUS_C2H_UNKNOWN_OPCODE = 0x02, // Invalid OP code, It means that wifi firmware received an undefiend OP code. - COL_STATUS_C2H_OPCODE_VER_MISMATCH = 0x03, // Wifi firmware and wifi driver mismatch, need to update wifi driver or wifi or. - COL_STATUS_C2H_PARAMETER_ERROR = 0x04, // Error paraneter.(ex: parameters = NULL but it should have values) - COL_STATUS_C2H_PARAMETER_OUT_OF_RANGE = 0x05, // Wifi firmware needs to check the parameters from H2C request and return the status.(ex: ch = 500, it's wrong) - // other COL status start from here - COL_STATUS_C2H_REQ_NUM_MISMATCH , // c2h req_num mismatch, means this c2h is not we expected. - COL_STATUS_H2C_HALMAC_FAIL , // HALMAC return fail. - COL_STATUS_H2C_TIMTOUT , // not received the c2h response from fw - COL_STATUS_INVALID_C2H_LEN , // invalid coex offload c2h ack length, must >= 3 - COL_STATUS_COEX_DATA_OVERFLOW , // coex returned length over the c2h ack length. - COL_STATUS_MAX -}COL_H2C_STATUS,*PCOL_H2C_STATUS; - -#define COL_MAX_H2C_REQ_NUM 16 - -#define COL_H2C_BUF_LEN 20 -typedef enum _COL_OPCODE{ - COL_OP_WIFI_STATUS_NOTIFY = 0x0, - COL_OP_WIFI_PROGRESS_NOTIFY = 0x1, - COL_OP_WIFI_INFO_NOTIFY = 0x2, - COL_OP_WIFI_POWER_STATE_NOTIFY = 0x3, - COL_OP_SET_CONTROL = 0x4, - COL_OP_GET_CONTROL = 0x5, - COL_OP_WIFI_OPCODE_MAX -}COL_OPCODE,*PCOL_OPCODE; - -typedef enum _COL_IND_TYPE{ - COL_IND_BT_INFO = 0x0, - COL_IND_PSTDMA = 0x1, - COL_IND_LIMITED_TX_RX = 0x2, - COL_IND_COEX_TABLE = 0x3, - COL_IND_REQ = 0x4, - COL_IND_MAX -}COL_IND_TYPE,*PCOL_IND_TYPE; - -typedef struct _COL_SINGLE_H2C_RECORD{ - u1Byte h2c_buf[COL_H2C_BUF_LEN]; // the latest sent h2c buffer - u4Byte h2c_len; - u1Byte c2h_ack_buf[COL_H2C_BUF_LEN]; // the latest received c2h buffer - u4Byte c2h_ack_len; - u4Byte count; // the total number of the sent h2c command - u4Byte status[COL_STATUS_MAX]; // the c2h status for the sent h2c command -} COL_SINGLE_H2C_RECORD, *PCOL_SINGLE_H2C_RECORD; - -typedef struct _COL_SINGLE_C2H_IND_RECORD{ - u1Byte ind_buf[COL_H2C_BUF_LEN]; // the latest received c2h indication buffer - u4Byte ind_len; - u4Byte count; // the total number of the rcvd c2h indication - u4Byte status[COL_STATUS_MAX]; // the c2h indication verified status -} COL_SINGLE_C2H_IND_RECORD, *PCOL_SINGLE_C2H_IND_RECORD; - -typedef struct _BTC_OFFLOAD{ - // H2C command related - u1Byte h2c_req_num; - u4Byte cnt_h2c_sent; - COL_SINGLE_H2C_RECORD h2c_record[COL_OP_WIFI_OPCODE_MAX]; - - // C2H Ack related - u4Byte cnt_c2h_ack; - u4Byte status[COL_STATUS_MAX]; - struct completion c2h_event[COL_MAX_H2C_REQ_NUM]; // for req_num = 1~COL_MAX_H2C_REQ_NUM - u1Byte c2h_ack_buf[COL_MAX_H2C_REQ_NUM][COL_H2C_BUF_LEN]; - u1Byte c2h_ack_len[COL_MAX_H2C_REQ_NUM]; - - // C2H Indication related - u4Byte cnt_c2h_ind; - COL_SINGLE_C2H_IND_RECORD c2h_ind_record[COL_IND_MAX]; - u4Byte c2h_ind_status[COL_STATUS_MAX]; - u1Byte c2h_ind_buf[COL_H2C_BUF_LEN]; - u1Byte c2h_ind_len; -} BTC_OFFLOAD, *PBTC_OFFLOAD; -extern BTC_OFFLOAD gl_coex_offload; -//================================================== - -typedef u1Byte -(*BFP_BTC_R1)( - IN PVOID pBtcContext, - IN u4Byte RegAddr - ); -typedef u2Byte -(*BFP_BTC_R2)( - IN PVOID pBtcContext, - IN u4Byte RegAddr - ); -typedef u4Byte -(*BFP_BTC_R4)( - IN PVOID pBtcContext, - IN u4Byte RegAddr - ); -typedef VOID -(*BFP_BTC_W1)( - IN PVOID pBtcContext, - IN u4Byte RegAddr, - IN u1Byte Data - ); -typedef VOID -(*BFP_BTC_W1_BIT_MASK)( - IN PVOID pBtcContext, - IN u4Byte regAddr, - IN u1Byte bitMask, - IN u1Byte data1b - ); -typedef VOID -(*BFP_BTC_W2)( - IN PVOID pBtcContext, - IN u4Byte RegAddr, - IN u2Byte Data - ); -typedef VOID -(*BFP_BTC_W4)( - IN PVOID pBtcContext, - IN u4Byte RegAddr, - IN u4Byte Data - ); -typedef VOID -(*BFP_BTC_LOCAL_REG_W1)( - IN PVOID pBtcContext, - IN u4Byte RegAddr, - IN u1Byte Data - ); -typedef VOID -(*BFP_BTC_SET_BB_REG)( - IN PVOID pBtcContext, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ); -typedef u4Byte -(*BFP_BTC_GET_BB_REG)( - IN PVOID pBtcContext, - IN u4Byte RegAddr, - IN u4Byte BitMask - ); -typedef VOID -(*BFP_BTC_SET_RF_REG)( - IN PVOID pBtcContext, - IN u1Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask, - IN u4Byte Data - ); -typedef u4Byte -(*BFP_BTC_GET_RF_REG)( - IN PVOID pBtcContext, - IN u1Byte eRFPath, - IN u4Byte RegAddr, - IN u4Byte BitMask - ); -typedef VOID -(*BFP_BTC_FILL_H2C)( - IN PVOID pBtcContext, - IN u1Byte elementId, - IN u4Byte cmdLen, - IN pu1Byte pCmdBuffer - ); - -typedef BOOLEAN -(*BFP_BTC_GET)( - IN PVOID pBtCoexist, - IN u1Byte getType, - OUT PVOID pOutBuf - ); - -typedef BOOLEAN -(*BFP_BTC_SET)( - IN PVOID pBtCoexist, - IN u1Byte setType, - OUT PVOID pInBuf - ); -typedef u2Byte -(*BFP_BTC_SET_BT_REG)( - IN PVOID pBtcContext, - IN u1Byte regType, - IN u4Byte offset, - IN u4Byte value - ); -typedef BOOLEAN -(*BFP_BTC_SET_BT_ANT_DETECTION)( - IN PVOID pBtcContext, - IN u1Byte txTime, - IN u1Byte btChnl - ); -typedef u2Byte -(*BFP_BTC_GET_BT_REG)( - IN PVOID pBtcContext, - IN u1Byte regType, - IN u4Byte offset, - IN pu4Byte data - ); -typedef VOID -(*BFP_BTC_DISP_DBG_MSG)( - IN PVOID pBtCoexist, - IN u1Byte dispType - ); - -typedef COL_H2C_STATUS -(*BFP_BTC_COEX_H2C_PROCESS)( - IN PVOID pBtCoexist, - IN u1Byte opcode, - IN u1Byte opcode_ver, - IN pu1Byte ph2c_par, - IN u1Byte h2c_par_len - ); - -typedef u4Byte -(*BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE)( - IN PVOID pBtcContext - ); - -typedef u4Byte -(*BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION)( - IN PVOID pBtcContext - ); - -typedef u4Byte -(*BFP_BTC_GET_PHYDM_VERSION)( - IN PVOID pBtcContext - ); - -typedef struct _BTC_BT_INFO{ - BOOLEAN bBtDisabled; - u1Byte rssiAdjustForAgcTableOn; - u1Byte rssiAdjustFor1AntCoexType; - BOOLEAN bPreBtCtrlAggBufSize; - BOOLEAN bBtCtrlAggBufSize; - BOOLEAN bPreRejectAggPkt; - BOOLEAN bRejectAggPkt; - BOOLEAN bIncreaseScanDevNum; - BOOLEAN bBtTxRxMask; - u1Byte preAggBufSize; - u1Byte aggBufSize; - BOOLEAN bBtBusy; - BOOLEAN bLimitedDig; - u2Byte btHciVer; - u2Byte btRealFwVer; - u1Byte btFwVer; - u4Byte getBtFwVerCnt; - BOOLEAN bMiracastPlusBt; - - BOOLEAN bBtDisableLowPwr; - - BOOLEAN bBtCtrlLps; - BOOLEAN bBtLpsOn; - BOOLEAN bForceToRoam; // for 1Ant solution - u1Byte lpsVal; - u1Byte rpwmVal; - u4Byte raMask; -} BTC_BT_INFO, *PBTC_BT_INFO; - -struct btc_stack_info { - boolean profile_notified; - u16 hci_version; /* stack hci version */ - u8 num_of_link; - boolean bt_link_exist; - boolean sco_exist; - boolean acl_exist; - boolean a2dp_exist; - boolean hid_exist; - u8 num_of_hid; - boolean pan_exist; - boolean unknown_acl_exist; - s8 min_bt_rssi; -}; - -struct btc_bt_link_info { - boolean bt_link_exist; - boolean bt_hi_pri_link_exist; - boolean sco_exist; - boolean sco_only; - boolean a2dp_exist; - boolean a2dp_only; - boolean hid_exist; - boolean hid_only; - boolean pan_exist; - boolean pan_only; - boolean slave_role; - boolean acl_busy; -}; - -typedef struct _BTC_STATISTICS{ - u4Byte cntBind; - u4Byte cntPowerOn; - u4Byte cntPreLoadFirmware; - u4Byte cntInitHwConfig; - u4Byte cntInitCoexDm; - u4Byte cntIpsNotify; - u4Byte cntLpsNotify; - u4Byte cntScanNotify; - u4Byte cntConnectNotify; - u4Byte cntMediaStatusNotify; - u4Byte cntSpecificPacketNotify; - u4Byte cntBtInfoNotify; - u4Byte cntRfStatusNotify; - u4Byte cntPeriodical; - u4Byte cntCoexDmSwitch; - u4Byte cntStackOperationNotify; - u4Byte cntDbgCtrl; -} BTC_STATISTICS, *PBTC_STATISTICS; - -struct btc_coexist{ - BOOLEAN bBinded; // make sure only one adapter can bind the data context - PVOID Adapter; // default adapter - struct btc_board_info board_info; - BTC_BT_INFO btInfo; // some bt info referenced by non-bt module - struct btc_stack_info stack_info; - struct btc_bt_link_info bt_link_info; - BTC_CHIP_INTERFACE chip_interface; - - BOOLEAN initilized; - BOOLEAN stop_coex_dm; - BOOLEAN manual_control; - BOOLEAN bdontenterLPS; - pu1Byte cli_buf; - BTC_STATISTICS statistics; - u1Byte pwrModeVal[10]; - - // function pointers - // io related - BFP_BTC_R1 btc_read_1byte; - BFP_BTC_W1 btc_write_1byte; - BFP_BTC_W1_BIT_MASK btc_write_1byte_bitmask; - BFP_BTC_R2 btc_read_2byte; - BFP_BTC_W2 btc_write_2byte; - BFP_BTC_R4 btc_read_4byte; - BFP_BTC_W4 btc_write_4byte; - BFP_BTC_LOCAL_REG_W1 btc_write_local_reg_1byte; - // read/write bb related - BFP_BTC_SET_BB_REG btc_set_bb_reg; - BFP_BTC_GET_BB_REG btc_get_bb_reg; - - // read/write rf related - BFP_BTC_SET_RF_REG btc_set_rf_reg; - BFP_BTC_GET_RF_REG btc_get_rf_reg; - - // fill h2c related - BFP_BTC_FILL_H2C btc_fill_h2c; - // other - BFP_BTC_DISP_DBG_MSG btc_disp_dbg_msg; - // normal get/set related - BFP_BTC_GET btc_get; - BFP_BTC_SET btc_set; - - BFP_BTC_GET_BT_REG btc_get_bt_reg; - BFP_BTC_SET_BT_REG btc_set_bt_reg; - - BFP_BTC_SET_BT_ANT_DETECTION btc_set_bt_ant_detection; - - BFP_BTC_COEX_H2C_PROCESS btc_coex_h2c_process; - BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE btc_get_bt_coex_supported_feature; - BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION btc_get_bt_coex_supported_version; - BFP_BTC_GET_PHYDM_VERSION btc_get_bt_phydm_version; -}; -typedef struct btc_coexist *PBTC_COEXIST; - -extern struct btc_coexist GLBtCoexist; - -BOOLEAN -EXhalbtcoutsrc_InitlizeVariables( - IN PVOID Adapter - ); -VOID -EXhalbtcoutsrc_PowerOnSetting( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtcoutsrc_PreLoadFirmware( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtcoutsrc_InitHwConfig( - IN PBTC_COEXIST pBtCoexist, - IN BOOLEAN bWifiOnly - ); -VOID -EXhalbtcoutsrc_InitCoexDm( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtcoutsrc_IpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtcoutsrc_LpsNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtcoutsrc_ScanNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtcoutsrc_ConnectNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte action - ); -VOID -EXhalbtcoutsrc_MediaStatusNotify( - IN PBTC_COEXIST pBtCoexist, - IN RT_MEDIA_STATUS mediaStatus - ); -VOID -EXhalbtcoutsrc_SpecificPacketNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte pktType - ); -VOID -EXhalbtcoutsrc_BtInfoNotify( - IN PBTC_COEXIST pBtCoexist, - IN pu1Byte tmpBuf, - IN u1Byte length - ); -VOID -EXhalbtcoutsrc_RfStatusNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtcoutsrc_StackOperationNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte type - ); -VOID -EXhalbtcoutsrc_HaltNotify( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtcoutsrc_PnpNotify( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte pnpState - ); -VOID -EXhalbtcoutsrc_ScoreBoardStatusNotify( - IN PBTC_COEXIST pBtCoexist, - IN pu1Byte tmpBuf, - IN u1Byte length - ); -VOID -EXhalbtcoutsrc_CoexDmSwitch( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtcoutsrc_Periodical( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtcoutsrc_DbgControl( - IN PBTC_COEXIST pBtCoexist, - IN u1Byte opCode, - IN u1Byte opLen, - IN pu1Byte pData - ); -VOID -EXhalbtcoutsrc_AntennaDetection( - IN PBTC_COEXIST pBtCoexist, - IN u4Byte centFreq, - IN u4Byte offset, - IN u4Byte span, - IN u4Byte seconds - ); -VOID -EXhalbtcoutsrc_StackUpdateProfileInfo( - VOID - ); -VOID -EXhalbtcoutsrc_SetHciVersion( - IN u2Byte hciVersion - ); -VOID -EXhalbtcoutsrc_SetBtPatchVersion( - IN u2Byte btHciVersion, - IN u2Byte btPatchVersion - ); -VOID -EXhalbtcoutsrc_UpdateMinBtRssi( - IN s1Byte btRssi - ); -#if 0 -VOID -EXhalbtcoutsrc_SetBtExist( - IN BOOLEAN bBtExist - ); -#endif -VOID -EXhalbtcoutsrc_SetChipType( - IN u1Byte chipType - ); -VOID -EXhalbtcoutsrc_SetAntNum( - IN u1Byte type, - IN u1Byte antNum - ); -VOID -EXhalbtcoutsrc_SetSingleAntPath( - IN u1Byte singleAntPath - ); -VOID -EXhalbtcoutsrc_DisplayBtCoexInfo( - IN PBTC_COEXIST pBtCoexist - ); -VOID -EXhalbtcoutsrc_DisplayAntDetection( - IN PBTC_COEXIST pBtCoexist - ); - -#define MASKBYTE0 0xff -#define MASKBYTE1 0xff00 -#define MASKBYTE2 0xff0000 -#define MASKBYTE3 0xff000000 -#define MASKHWORD 0xffff0000 -#define MASKLWORD 0x0000ffff -#define MASKDWORD 0xffffffff -#define MASK12BITS 0xfff -#define MASKH4BITS 0xf0000000 -#define MASKOFDM_D 0xffc00000 -#define MASKCCK 0x3f3f3f3f - -#endif diff --git a/hal/btc/Mp_Precomp.h b/hal/btc/Mp_Precomp.h deleted file mode 100644 index d5ebdbf..0000000 --- a/hal/btc/Mp_Precomp.h +++ /dev/null @@ -1,102 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __MP_PRECOMP_H__ -#define __MP_PRECOMP_H__ - -#include -#include - -#define BT_TMP_BUF_SIZE 100 - -#ifdef PLATFORM_LINUX -#define rsprintf snprintf -#elif defined(PLATFORM_WINDOWS) -#define rsprintf sprintf_s -#endif - -#define DCMD_Printf DBG_BT_INFO - -#define delay_ms(ms) rtw_mdelay_os(ms) - -#ifdef bEnable -#undef bEnable -#endif - -#define WPP_SOFTWARE_TRACE 0 - -typedef enum _BTC_MSG_COMP_TYPE{ - COMP_COEX = 0, - COMP_MAX -}BTC_MSG_COMP_TYPE; -extern u4Byte GLBtcDbgType[]; - -#define DBG_OFF 0 -#define DBG_SEC 1 -#define DBG_SERIOUS 2 -#define DBG_WARNING 3 -#define DBG_LOUD 4 -#define DBG_TRACE 5 - -#if DBG -#ifdef RT_TRACE -#undef RT_TRACE -#define RT_TRACE(dbgtype, dbgflag, printstr)\ -do {\ - if (GLBtcDbgType[dbgtype] & BIT(dbgflag))\ - {\ - DbgPrint printstr;\ - }\ -} while (0) -#endif -#else -#define RT_TRACE(dbgtype, dbgflag, printstr) -#endif - -#ifdef CONFIG_BT_COEXIST -#define BT_SUPPORT 1 -#define COEX_SUPPORT 1 -#define HS_SUPPORT 1 -#else -#define BT_SUPPORT 0 -#define COEX_SUPPORT 0 -#define HS_SUPPORT 0 -#endif - -#include "HalBtcOutSrc.h" -#include "HalBtc8188c2Ant.h" -#include "HalBtc8192d2Ant.h" -#include "HalBtc8192e1Ant.h" -#include "HalBtc8192e2Ant.h" -#include "HalBtc8723a1Ant.h" -#include "HalBtc8723a2Ant.h" -#include "HalBtc8723b1Ant.h" -#include "HalBtc8723b2Ant.h" -#include "HalBtc8812a1Ant.h" -#include "HalBtc8812a2Ant.h" -#include "HalBtc8821a1Ant.h" -#include "HalBtc8821a2Ant.h" -#include "HalBtc8821aCsr2Ant.h" -#include "HalBtc8703b1Ant.h" -#include "halbtc8723d1ant.h" -#include "halbtc8723d2ant.h" -#include "HalBtc8822b1Ant.h" - - -#endif // __MP_PRECOMP_H__ diff --git a/hal/btc/halbtc8192e1ant.c b/hal/btc/halbtc8192e1ant.c deleted file mode 100644 index 1c60239..0000000 --- a/hal/btc/halbtc8192e1ant.c +++ /dev/null @@ -1,3431 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for RTL8192E Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8192E_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8192e_1ant glcoex_dm_8192e_1ant; -static struct coex_dm_8192e_1ant *coex_dm = &glcoex_dm_8192e_1ant; -static struct coex_sta_8192e_1ant glcoex_sta_8192e_1ant; -static struct coex_sta_8192e_1ant *coex_sta = &glcoex_sta_8192e_1ant; - -const char *const glbt_info_src_8192e_1ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8192e_1ant = 20140527; -u32 glcoex_ver_8192e_1ant = 0x4f; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8192e1ant_ - * ************************************************************ */ -u8 halbtc8192e1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8192e1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8192e1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8192e1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8192e1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8192e1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8192e1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8192e1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8192e1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8192e1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8192e1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8192e1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8192e1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8192e1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8192e1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -void halbtc8192e1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0; - - /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ - /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ - - if (coex_sta->under_ips) { - coex_sta->high_priority_tx = 65535; - coex_sta->high_priority_rx = 65535; - coex_sta->low_priority_tx = 65535; - coex_sta->low_priority_rx = 65535; - return; - } - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if ((coex_sta->low_priority_tx >= 1050) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", - reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) && - (reg_lp_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8192e1ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; - } - } -} - - -void halbtc8192e1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false; - static u8 cck_lock_counter = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - if (coex_sta->under_ips) { - coex_sta->crc_ok_cck = 0; - coex_sta->crc_ok_11g = 0; - coex_sta->crc_ok_11n = 0; - coex_sta->crc_ok_11n_agg = 0; - - coex_sta->crc_err_cck = 0; - coex_sta->crc_err_11g = 0; - coex_sta->crc_err_11n = 0; - coex_sta->crc_err_11n_agg = 0; - } else { - coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf88); - coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf94); - coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf90); - coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfb8); - - coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist, - 0xf84); - coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf96); - coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf92); - coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xfba); - } - - - /* reset counter */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0); - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - if ((coex_dm->bt_status == BT_8192E_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == - BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == - BT_8192E_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + - coex_sta->crc_ok_11n_agg)) { - if (cck_lock_counter < 5) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 5) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - coex_sta->pre_ccklock = coex_sta->cck_lock; - - -} - -boolean halbtc8192e1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - } - - return false; -} - -void halbtc8192e1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8192e1ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8192E_1ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8192e1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8192e1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8192e1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8192e1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8192e1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8192e1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8192e1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8192e1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8192e1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8192e1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** CoexTable(%d) **********\n", type); - BTC_TRACE(trace_buf); - - coex_sta->coex_table_type = type; - - switch (type) { - case 0: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, 0xffffff, 0x3); - break; - case 1: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 2: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 3: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 4: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); - break; - case 5: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaa5a5a5a, 0xffffff, 0x3); - break; - case 6: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 7: - halbtc8192e1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8192e1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) - h2c_parameter[0] |= BIT(0); /* function enable */ - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8192e1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8192e1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8192e1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8192e1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8192e1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8192e1ant_sw_mechanism(IN struct btc_coexist *btcoexist, - IN boolean low_penalty_ra) -{ - halbtc8192e1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8192e1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - u32 u32tmp = 0; - - if (init_hwcfg) { - btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24); - btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700); - if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); - else - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); - - /* 0x4c[27][24]='00', Set Antenna to BB */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(24); - u32tmp &= ~BIT(27); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } else if (wifi_off) { - if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); - else - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); - - /* 0x4c[27][24]='11', Set Antenna to BT, 0x64[8:7]=0, 0x64[2]=1 */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp |= BIT(24); - u32tmp |= BIT(27); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } - - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); - break; - case BTC_ANT_PATH_BT: - btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20); - break; - default: - case BTC_ANT_PATH_PTA: - btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); - break; - } -} - -void halbtc8192e1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - } - } - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - - -void halbtc8192e1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - u8 rssi_adjust_val = 0; - u8 ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51, - ps_tdma_byte3_val = 0x10; - s8 wifi_duration_adjust = 0x0; - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_sta->scan_ap_num <= 5) - wifi_duration_adjust = 5; - else if (coex_sta->scan_ap_num >= 40) - wifi_duration_adjust = -15; - else if (coex_sta->scan_ap_num >= 20) - wifi_duration_adjust = -10; - - if (!coex_sta->force_lps_on) { /* only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */ - ps_tdma_byte0_val = 0x61; /* no null-pkt */ - ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */ - ps_tdma_byte4_val = 0x10; /* 0x778 = d/1 toggle */ - } - - if ((type == 3) || (type == 13) || (type == 14)) - ps_tdma_byte4_val = ps_tdma_byte4_val & - 0xbf; /* no dynamic slot for multi-profile */ - - if (bt_link_info->slave_role == true) - ps_tdma_byte4_val = ps_tdma_byte4_val | - 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - - if (turn_on) { - switch (type) { - default: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1a, 0x1a, 0x0, ps_tdma_byte4_val); - break; - case 1: - halbtc8192e1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3a + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 2: - halbtc8192e1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x2d + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 3: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1d, 0x1d, 0x0, ps_tdma_byte4_val); - break; - case 4: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x14, 0x0); - break; - case 5: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, - 0x15, 0x3, 0x11, 0x11); - break; - case 6: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x3, 0x11, 0x11); - break; - case 7: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13, - 0xc, 0x5, 0x0, 0x0); - break; - case 8: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 9: - halbtc8192e1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 10: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0xa, 0x0, 0x40); - break; - case 11: - halbtc8192e1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 12: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, - 0x0a, 0x0a, 0x0, 0x50); - break; - case 13: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, - 0x12, 0x12, 0x0, ps_tdma_byte4_val); - break; - case 14: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, - 0x21, 0x3, 0x10, ps_tdma_byte4_val); - break; - case 15: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0x3, 0x8, 0x0); - break; - case 16: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x10, 0x0); - break; - case 18: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 20: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, - 0x3f, 0x03, 0x11, 0x10); - break; - case 21: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x11); - break; - case 22: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x10); - break; - case 23: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x18); - break; - case 24: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x3, 0x31, 0x18); - break; - case 25: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - break; - case 26: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - break; - case 27: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x98); - break; - case 28: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x69, - 0x25, 0x3, 0x31, 0x0); - break; - case 29: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xab, - 0x1a, 0x1a, 0x1, 0x10); - break; - case 30: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, 0x10); - break; - case 31: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1a, 0x1a, 0, 0x58); - break; - case 32: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x3, 0x11, 0x11); - break; - case 33: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xa3, - 0x25, 0x3, 0x30, 0x90); - break; - case 34: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x53, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 35: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x63, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 36: - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x12, 0x3, 0x14, 0x50); - break; - case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */ - /* here softap mode screen off will cost 70-80mA for phone */ - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x23, - 0x18, 0x00, 0x10, 0x24); - break; - } - } else { - - /* disable PS tdma */ - switch (type) { - case 8: /* PTA Control */ - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - halbtc8192e1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, false, false); - break; - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - halbtc8192e1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, false, false); - break; - case 9: /* Software control, Antenna at WiFi side */ - halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - halbtc8192e1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_WIFI, false, false); - break; - } - } - rssi_adjust_val = 0; - btcoexist->btc_set(btcoexist, - BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", - btcoexist->btc_read_4byte(btcoexist, 0x948), - btcoexist->btc_read_1byte(btcoexist, 0x765), - btcoexist->btc_read_1byte(btcoexist, 0x67)); - BTC_TRACE(trace_buf); - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8192e1ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* sw all off */ - halbtc8192e1ant_sw_mechanism(btcoexist, false); - - /* hw all off */ - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -boolean halbtc8192e1ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (wifi_connected && - (BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (!wifi_connected && - (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (wifi_connected && - (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (!wifi_connected && - (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } - - common = false; - } - - return common; -} - - -void halbtc8192e1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0, bt_info_ext; - boolean wifi_busy = false; - /*static boolean pre_wifi_busy = false;*/ - - if (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status) - wifi_busy = true; - else - wifi_busy = false; - - if ((BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == - wifi_status) || - (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) || - (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT == - wifi_status)) { - if (coex_dm->cur_ps_tdma != 1 && - coex_dm->cur_ps_tdma != 2 && - coex_dm->cur_ps_tdma != 3 && - coex_dm->cur_ps_tdma != 9) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - coex_dm->ps_tdma_du_adj_type = 9; - - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } - return; - } - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* acquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - bt_info_ext = coex_sta->bt_info_ext; - - if ((coex_sta->low_priority_tx) > 1050 || - (coex_sta->low_priority_rx) > 1250) - retry_count++; - - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ - if (wait_count <= 2) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ - if (wait_count == 1) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (result == -1) { - if ((BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 1) || - (coex_dm->cur_ps_tdma == 2))) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } - } else if (result == 1) { - if ((BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 1) || - (coex_dm->cur_ps_tdma == 2))) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = 1; - } - } else { /* no change */ - /* Bryant Modify - if(wifi_busy != pre_wifi_busy) - { - pre_wifi_busy = wifi_busy; - halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma); - } - */ - } - - if (coex_dm->cur_ps_tdma != 1 && - coex_dm->cur_ps_tdma != 2 && - coex_dm->cur_ps_tdma != 9 && - coex_dm->cur_ps_tdma != 11) { - /* recover to previous adjust type */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - } - } -} - -void halbtc8192e1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8192e1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8192e1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8192e1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8192e1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - -void halbtc8192e1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 9); -} - -void halbtc8192e1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - BTC_TRACE(trace_buf); - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 2) { - bt_disabled = true; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - BTC_TRACE(trace_buf); - halbtc8192e1ant_action_wifi_only(btcoexist); - } - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - if (!bt_disabled) { - } else { - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - } - } -} - -/* ********************************************* - * - * Software Coex Mechanism start - * - * ********************************************* */ - -/* SCO only or SCO+PAN(HS) */ - -/* -void halbtc8192e1ant_action_sco(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8192e1ant_action_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8192e1ant_action_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8192e1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8192e1ant_action_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8192e1ant_action_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8192e1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8192e1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8192e1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, true); -} - -void halbtc8192e1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8192e1ant_sw_mechanism(btcoexist, true); -} - -*/ - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8192e1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8192e1ant_action_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8192e1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, ap_enable = false, wifi_busy = false, - bt_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) { - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - /* SCO/HID/A2DP busy */ - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if ((bt_link_info->pan_exist) || (wifi_busy)) { - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } -} - -void halbtc8192e1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* tdma and coex table */ - - if (bt_link_info->sco_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else { /* HID */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } -} - -void halbtc8192e1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - u8 bt_rssi_state; - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - bt_rssi_state = halbtc8192e1ant_bt_rssi_state(2, 28, 0); - - if ((coex_sta->low_priority_rx >= 1000) && - (coex_sta->low_priority_rx != 65535)) - bt_link_info->slave_role = true; - else - bt_link_info->slave_role = false; - - if (bt_link_info->hid_only) { /* HID */ - halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, - wifi_status); - coex_dm->auto_tdma_adjust = false; - return; - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - halbtc8192e1ant_tdma_duration_adjust_for_acl(btcoexist, - wifi_status); -#if 0 - if (coex_sta->cck_lock) - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - else -#endif - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = true; - } - } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - coex_dm->auto_tdma_adjust = false; - - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && - bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - /* BT no-profile busy (0x9) */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } -} - -void halbtc8192e1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - /* power save state */ - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8192e1ant_action_wifi_not_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* Bryant Add */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8192e1ant_action_wifi_not_connected_asso_auth( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8192e1ant_action_wifi_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* Bryant Add */ - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8192e1ant_action_wifi_connected_specific_packet( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8192e1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - boolean scan = false, link = false, roam = false; - boolean under_4way = false, ap_enable = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (under_4way) { - halbtc8192e1ant_action_wifi_connected_specific_packet(btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - if (scan) - halbtc8192e1ant_action_wifi_connected_scan(btcoexist); - else - halbtc8192e1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* power save state */ - if (!ap_enable && - BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status && - !btcoexist->bt_link_info.hid_only) { - if (btcoexist->bt_link_info.a2dp_only) { /* A2DP */ - if (!wifi_busy) - halbtc8192e1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - else { /* busy */ - if (coex_sta->scan_ap_num >= - BT_8192E_1ANT_WIFI_NOISY_THRESH) /* no force LPS, no PS-TDMA, use pure TDMA */ - halbtc8192e1ant_power_save_state( - btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8192e1ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - } else if ((coex_sta->pan_exist == false) && - (coex_sta->a2dp_exist == false) && - (coex_sta->hid_exist == false)) - halbtc8192e1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - else - halbtc8192e1ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - } else - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - /* tdma and coex table */ - if (!wifi_busy) { - if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8192e1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - else - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } else { - if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8192e1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else { - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - else - halbtc8192e1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } -} - -void halbtc8192e1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - - algorithm = halbtc8192e1ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - - if (halbtc8192e1ant_is_common_action(btcoexist)) { - - } else { - switch (coex_dm->cur_algorithm) { - case BT_8192E_1ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_sco(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_hid(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_a2dp(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_a2dp_pan_hs(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_pan_edr(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_pan_hs(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_pan_edr_a2dp(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_pan_edr_hid(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_hid_a2dp_pan_edr(btcoexist); */ - break; - case BT_8192E_1ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_action_hid_a2dp(btcoexist); */ - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8192e1ant_coex_all_off(btcoexist); */ - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8192e1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - boolean miracast_plus_bt = false; - u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if ((BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, - 0, 1); - miracast_plus_bt = true; - } else { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, - 0, 0); - miracast_plus_bt = false; - } - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if ((bt_link_info->a2dp_exist) && - (coex_sta->c2h_bt_inquiry_page)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8192e1ant_action_bt_inquiry(btcoexist); - } else - halbtc8192e1ant_action_wifi_multi_port(btcoexist); - - return; - } - - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); - - if (bt_link_info->sco_exist) - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, - false, true, 0x5); - else - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, - false, true, 0x8); - - halbtc8192e1ant_sw_mechanism(btcoexist, true); - halbtc8192e1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - } else { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x5); - - halbtc8192e1ant_sw_mechanism(btcoexist, false); - halbtc8192e1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8192e1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8192e1ant_action_hs(btcoexist); - return; - } - - - if (!wifi_connected) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is non connected-idle !!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - if (scan) - halbtc8192e1ant_action_wifi_not_connected_scan( - btcoexist); - else - halbtc8192e1ant_action_wifi_not_connected_asso_auth( - btcoexist); - } else - halbtc8192e1ant_action_wifi_not_connected(btcoexist); - } else /* wifi LPS/Busy */ - halbtc8192e1ant_action_wifi_connected(btcoexist); -} - -void halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - - /* sw all off */ - halbtc8192e1ant_sw_mechanism(btcoexist, false); - - /* halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ - halbtc8192e1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - coex_sta->pop_event_cnt = 0; -} - -void halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - u16 u16tmp = 0; - u8 u8tmp = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - /* antenna sw ctrl to bt */ - halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, false); - - halbtc8192e1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - /* antenna switch control parameter */ - btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555); - - /* coex parameters */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* enable PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); - /* enable mailbox interface */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40); - u16tmp |= BIT(9); - btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp); - - /* enable PTA I2C mailbox */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101); - u8tmp |= BIT(4); - btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp); - - /* enable bt clock when wifi is disabled. */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93); - u8tmp |= BIT(0); - btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp); - /* enable bt clock when suspend. */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); - u8tmp |= BIT(0); - btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); -} - - -/* -void halbtc8192e1ant_wifi_off_hw_cfg(IN struct btc_coexist* btcoexist) -{ - - -} -*/ - -/* ************************************************************ - * work around function start with wa_halbtc8192e1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8192e1ant_ - * ************************************************************ */ -void ex_halbtc8192e1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ -#if 0 - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x0; - u16 u16tmp = 0x0; - - btcoexist->stop_coex_dm = true; - - btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20); - - /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - - /* set GRAN_BT = 1 */ - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); - /* set WLAN_ACT = 0 */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - if (btcoexist->chip_interface == BTC_INTF_USB) { - /* fixed at S0 for USB interface */ - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - - u8tmp |= 0x1; /* antenna inverse */ - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - } else { - /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ - if (board_info->single_ant_path == 0) { - /* set to S1 */ - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x280); - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - u8tmp |= 0x1; /* antenna inverse */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - } - - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384, - u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, - u8tmp); - } -#endif -} - -void ex_halbtc8192e1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8192e1ant_init_hw_config(btcoexist, wifi_only); - btcoexist->stop_coex_dm = false; -} - -void ex_halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - - halbtc8192e1ant_init_coex_dm(btcoexist); - - halbtc8192e1ant_query_bt_info(btcoexist); -} - -void ex_halbtc8192e1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u32 u32tmp[4]; - u32 fw_ver = 0, bt_patch_ver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", - "CoexVer/ FwVer/ PatchVer", - glcoex_ver_date_8192e_1ant, glcoex_ver_8192e_1ant, fw_ver, - bt_patch_ver, bt_patch_ver); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", - "SCO/HID/PAN/A2DP", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8192E_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8192e_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - if (!btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - coex_dm->auto_tdma_adjust); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", - "Latest error condition(should be 0)", - coex_dm->error_condition); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", - "IgnWlanAct", - coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - } - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0xc04/ 0xd04/ 0x90c", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", - u8tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x92c/ 0x930", - (u8tmp[0]), u32tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x40/ 0x4f", - u8tmp[0], u8tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", - u32tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(hp rx[31:16]/tx[15:0])", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(lp rx[31:16]/tx[15:0])", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 1) - halbtc8192e1ant_monitor_bt_ctr(btcoexist); -#endif - - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - -void ex_halbtc8192e1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, - true); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; - - halbtc8192e1ant_init_hw_config(btcoexist, false); - halbtc8192e1ant_init_coex_dm(btcoexist); - halbtc8192e1ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8192e1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8192e1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - u8 u8tmpa, u8tmpb; - u32 u32tmp; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_SCAN_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - - halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", - u32tmp, u8tmpa, u8tmpb); - BTC_TRACE(trace_buf); - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - } - - if (coex_sta->bt_disabled) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - halbtc8192e1ant_query_bt_info(btcoexist); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8192e1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8192e1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8192e1ant_action_hs(btcoexist); - return; - } - - if (BTC_SCAN_START == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8192e1ant_action_wifi_not_connected_scan( - btcoexist); - else /* wifi is connected */ - halbtc8192e1ant_action_wifi_connected_scan(btcoexist); - } else if (BTC_SCAN_FINISH == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8192e1ant_action_wifi_not_connected(btcoexist); - else - halbtc8192e1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8192e1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_ASSOCIATE_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - /* coex_dm->arp_cnt = 0; */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8192e1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8192e1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8192e1ant_action_hs(btcoexist); - return; - } - - if (BTC_ASSOCIATE_START == type) - halbtc8192e1ant_action_wifi_not_connected_asso_auth(btcoexist); - else if (BTC_ASSOCIATE_FINISH == type) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (!wifi_connected) /* non-connected scan */ - halbtc8192e1ant_action_wifi_not_connected(btcoexist); - else - halbtc8192e1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8192e1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - boolean wifi_under_b_mode = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x10); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - /* h2c_parameter[0] = 0x1; */ - h2c_parameter[0] = 0x0; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); -} - -void ex_halbtc8192e1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - BTC_PACKET_ARP == type) { - if (BTC_PACKET_ARP == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify\n"); - BTC_TRACE(trace_buf); - - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ARP Packet Count = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - - if (coex_dm->arp_cnt >= - 10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */ - coex_sta->wifi_is_high_pri_task = false; - else - coex_sta->wifi_is_high_pri_task = true; - } else { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify\n"); - BTC_TRACE(trace_buf); - } - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet [Type = %d] notify\n", type); - BTC_TRACE(trace_buf); - } - - coex_sta->specific_pkt_period_cnt = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8192e1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8192e1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8192e1ant_action_hs(btcoexist); - return; - } - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task))) - halbtc8192e1ant_action_wifi_connected_specific_packet(btcoexist); -} - -void ex_halbtc8192e1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean bt_busy = false; - - coex_sta->c2h_bt_info_req_sent = false; - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8192E_1ANT_MAX) - rsp_source = BT_INFO_SRC_8192E_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (BT_INFO_SRC_8192E_1ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_page = true; - else - coex_sta->c2h_bt_page = false; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; - /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */ - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] - & 0x40); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, - &coex_sta->bt_tx_rx_mask); - if (!coex_sta->bt_tx_rx_mask) { - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x3c, 0x15); - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if (coex_sta->bt_info_ext & BIT(1)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8192e1ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8192e1ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if (coex_sta->bt_info_ext & BIT(3)) { - if (!btcoexist->manual_control && - !btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8192e1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - } -#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8192e1ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8192E_1ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8192E_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8192E_1ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8192E_1ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8192E_1ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8192E_1ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - } - - halbtc8192e1ant_update_bt_link_info(btcoexist); - - bt_info = bt_info & - 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ - - if (!(bt_info & BT_INFO_8192E_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8192E_1ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8192E_1ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8192E_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8192E_1ANT_B_ACL_BUSY) { - if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) - coex_dm->auto_tdma_adjust = false; - coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - halbtc8192e1ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8192e1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u32 u32tmp; - u8 u8tmpa, u8tmpb, u8tmpc; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - } else if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, - true); - - halbtc8192e1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - btcoexist->stop_coex_dm = true; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); - u8tmpc = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n", - u32tmp, u8tmpa, u8tmpb, u8tmpc); - BTC_TRACE(trace_buf); - - } -} - -void ex_halbtc8192e1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true); - - halbtc8192e1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8192e1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8192e1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, - true); - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - halbtc8192e1ant_init_hw_config(btcoexist, false); - halbtc8192e1ant_init_coex_dm(btcoexist); - halbtc8192e1ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8192e1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], *****************Coex DM Reset*****************\n"); - BTC_TRACE(trace_buf); - - halbtc8192e1ant_init_hw_config(btcoexist, false); - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); */ - halbtc8192e1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8192e1ant_periodical(IN struct btc_coexist *btcoexist) -{ -#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 0) - halbtc8192e1ant_query_bt_info(btcoexist); - halbtc8192e1ant_monitor_bt_enable_disable(btcoexist); -#else - halbtc8192e1ant_monitor_bt_ctr(btcoexist); - halbtc8192e1ant_monitor_wifi_ctr(btcoexist); - - if (halbtc8192e1ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust) - - halbtc8192e1ant_run_coexist_mechanism(btcoexist); - - coex_sta->specific_pkt_period_cnt++; -#endif -} - - -void ex_halbtc8192e1ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata) -{ - switch (op_code) { - case BTC_DBG_SET_COEX_NORMAL: - btcoexist->manual_control = false; - halbtc8192e1ant_init_coex_dm(btcoexist); - break; - case BTC_DBG_SET_COEX_WIFI_ONLY: - btcoexist->manual_control = true; - halbtc8192e1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 9); - break; - case BTC_DBG_SET_COEX_BT_ONLY: - /* todo */ - break; - default: - break; - } -} - -#endif /* #if (RTL8192E_SUPPORT == 1) */ - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ diff --git a/hal/btc/halbtc8192e1ant.h b/hal/btc/halbtc8192e1ant.h deleted file mode 100644 index 10c34c1..0000000 --- a/hal/btc/halbtc8192e1ant.h +++ /dev/null @@ -1,240 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8192E_SUPPORT == 1) - -/* ******************************************* - * The following is for 8192E 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8192E_1ANT 1 - -#define BT_INFO_8192E_1ANT_B_FTP BIT(7) -#define BT_INFO_8192E_1ANT_B_A2DP BIT(6) -#define BT_INFO_8192E_1ANT_B_HID BIT(5) -#define BT_INFO_8192E_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8192E_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8192E_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8192E_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8192E_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT 2 - -#define BT_8192E_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ - -enum bt_info_src_8192e_1ant { - BT_INFO_SRC_8192E_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8192E_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8192E_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8192E_1ANT_MAX -}; - -enum bt_8192e_1ant_bt_status { - BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8192E_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8192E_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8192E_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8192E_1ANT_BT_STATUS_MAX -}; - -enum bt_8192e_1ant_wifi_status { - BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8192E_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8192e_1ant_coex_algo { - BT_8192E_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8192E_1ANT_COEX_ALGO_SCO = 0x1, - BT_8192E_1ANT_COEX_ALGO_HID = 0x2, - BT_8192E_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8192E_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8192E_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8192E_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8192E_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8192E_1ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8192e_1ant { - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u8 error_condition; -}; - -struct coex_sta_8192e_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - s8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8192E_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8192E_1ANT_MAX]; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - u8 bt_retry_cnt; - u8 bt_info_ext; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_agg; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_agg; - - boolean cck_lock; - boolean pre_ccklock; - u8 coex_table_type; - - boolean force_lps_on; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8192e1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8192e1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8192e1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e1ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata); - -#else /* #if (RTL8192E_SUPPORT == 1) */ -#define ex_halbtc8192e1ant_power_on_setting(btcoexist) -#define ex_halbtc8192e1ant_pre_load_firmware(btcoexist) -#define ex_halbtc8192e1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8192e1ant_init_coex_dm(btcoexist) -#define ex_halbtc8192e1ant_ips_notify(btcoexist, type) -#define ex_halbtc8192e1ant_lps_notify(btcoexist, type) -#define ex_halbtc8192e1ant_scan_notify(btcoexist, type) -#define ex_halbtc8192e1ant_connect_notify(btcoexist, type) -#define ex_halbtc8192e1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8192e1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8192e1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8192e1ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8192e1ant_halt_notify(btcoexist) -#define ex_halbtc8192e1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8192e1ant_coex_dm_reset(btcoexist) -#define ex_halbtc8192e1ant_periodical(btcoexist) -#define ex_halbtc8192e1ant_display_coex_info(btcoexist) -#define ex_halbtc8192e1ant_dbg_control(btcoexist, op_code, op_len, pdata) - -#endif - -#endif diff --git a/hal/btc/halbtc8192e2ant.c b/hal/btc/halbtc8192e2ant.c deleted file mode 100644 index 9936a8b..0000000 --- a/hal/btc/halbtc8192e2ant.c +++ /dev/null @@ -1,4391 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for RTL8192E Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8192E_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8192e_2ant glcoex_dm_8192e_2ant; -static struct coex_dm_8192e_2ant *coex_dm = &glcoex_dm_8192e_2ant; -static struct coex_sta_8192e_2ant glcoex_sta_8192e_2ant; -static struct coex_sta_8192e_2ant *coex_sta = &glcoex_sta_8192e_2ant; - -const char *const glbt_info_src_8192e_2ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; -/* ************************************************************ - * BtCoex Version Format: - * 1. date : glcoex_ver_date_XXXXX_1ant - * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant - * 3. BtCoexVersion : glcoex_ver_btdesired_XXXXX_1ant - * 4. others : glcoex_ver_XXXXXX_XXXXX_1ant - * - * Variable should be indicated IC and Antenna numbers !!! - * Please strictly follow this order and naming style !!! - * - * ************************************************************ */ -u32 glcoex_ver_date_8192e_2ant = 20160818; -u32 glcoex_ver_8192e_2ant = 0x44; -u32 glcoex_ver_btdesired_8192e_2ant = 0x44; -/*1. add coex. log for wifi/BT coex. version*/ -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8192e2ant_ - * ************************************************************ */ -u8 halbtc8192e2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8192e2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8192e2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - BTC_TRACE(trace_buf); - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 2) { - bt_disabled = true; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - BTC_TRACE(trace_buf); - } - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - /* if (!bt_disabled) { - } else { - } */ - } -} - -u32 halbtc8192e2ant_decide_ra_mask(IN struct btc_coexist *btcoexist, - IN u8 ss_type, IN u32 ra_mask_type) -{ - u32 dis_ra_mask = 0x0; - - switch (ra_mask_type) { - case 0: /* normal mode */ - if (ss_type == 2) - dis_ra_mask = 0x0; /* enable 2ss */ - else - dis_ra_mask = 0xfff00000; /* disable 2ss */ - break; - case 1: /* disable cck 1/2 */ - if (ss_type == 2) - dis_ra_mask = 0x00000003; /* enable 2ss */ - else - dis_ra_mask = 0xfff00003; /* disable 2ss */ - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - if (ss_type == 2) - dis_ra_mask = 0x0001f1f7; /* enable 2ss */ - else - dis_ra_mask = 0xfff1f1f7; /* disable 2ss */ - break; - default: - break; - } - - return dis_ra_mask; -} - -void halbtc8192e2ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8192e2ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8192e2ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8192e2ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8192e2ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - u32 dis_ra_mask = 0x0; - - coex_dm->cur_ra_mask_type = ra_mask_type; - dis_ra_mask = halbtc8192e2ant_decide_ra_mask(btcoexist, - coex_dm->cur_ss_type, ra_mask_type); - halbtc8192e2ant_update_ra_mask(btcoexist, force_exec, dis_ra_mask); - - halbtc8192e2ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8192e2ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8192e2ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8192e2ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8192e2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); -} - - -void halbtc8192e2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ -#if 1 - - coex_sta->crc_ok_cck = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_VHT); -#endif -} - - - -void halbtc8192e2ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],Query BT info!!!! H2C 0x61 = 0x1\n"); - BTC_TRACE(trace_buf); -} - -boolean halbtc8192e2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, - 2, 34, 0); - - if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) || - (BTC_RSSI_STATE_LOW == wifi_rssi_state)) - return true; - } - - return false; -} - -void halbtc8192e2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8192e2ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8192E_2ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_SCO_PAN; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - if (stack_info->num_of_hid >= 2) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID*2 + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_HID_A2DP; - } - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_SCO_PAN; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8192e2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - -void halbtc8192e2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN u8 dec_bt_pwr_lvl) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = dec_bt_pwr_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); -} - -void halbtc8192e2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 dec_bt_pwr_lvl) -{ - coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; - - if (!force_exec) { -#if 0 /* work around, avoid h2c command fail. */ - if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) - return; -#endif - } - halbtc8192e2ant_set_fw_dec_bt_pwr(btcoexist, - coex_dm->cur_bt_dec_pwr_lvl); - - coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; -} - -void halbtc8192e2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8192e2ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8192e2ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8192e2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8192e2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - -void halbtc8192e2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist, - IN boolean rx_rf_shrink_on) -{ - if (rx_rf_shrink_on) { - /* Shrink RF Rx LPF corner */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Shrink RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, - 0xffffc); - } else { - /* Resume RF Rx LPF corner */ - /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ - if (btcoexist->initilized) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Resume RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, coex_dm->bt_rf_0x1e_backup); - } - } -} - -void halbtc8192e2ant_rf_shrink(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rx_rf_shrink_on) -{ - coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; - - if (!force_exec) { - if (coex_dm->pre_rf_rx_lpf_shrink == - coex_dm->cur_rf_rx_lpf_shrink) - return; - } - halbtc8192e2ant_set_sw_rf_rx_lpf_corner(btcoexist, - coex_dm->cur_rf_rx_lpf_shrink); - - coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; -} - -void halbtc8192e2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8192e2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8192e2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8192e2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, - IN u32 level) -{ - u8 val = (u8)level; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Write SwDacSwing = 0x%x\n", level); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val); -} - -void halbtc8192e2ant_set_sw_full_time_dac_swing(IN struct btc_coexist - *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) -{ - if (sw_dac_swing_on) - halbtc8192e2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl); - else - halbtc8192e2ant_set_dac_swing_reg(btcoexist, 0x18); -} - - -void halbtc8192e2ant_dac_swing(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) -{ - coex_dm->cur_dac_swing_on = dac_swing_on; - coex_dm->cur_dac_swing_lvl = dac_swing_lvl; - - if (!force_exec) { - if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && - (coex_dm->pre_dac_swing_lvl == - coex_dm->cur_dac_swing_lvl)) - return; - } - delay_ms(30); - halbtc8192e2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, - dac_swing_lvl); - - coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; - coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; -} - -void halbtc8192e2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean adc_back_off) -{ - if (adc_back_off) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x3); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x1); - } -} - -void halbtc8192e2ant_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean adc_back_off) -{ - coex_dm->cur_adc_back_off = adc_back_off; - - if (!force_exec) { - if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) - return; - } - halbtc8192e2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off); - - coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; -} - -void halbtc8192e2ant_set_agc_table(IN struct btc_coexist *btcoexist, - IN boolean agc_table_en) -{ - /* =================BB AGC Gain Table */ - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x0a1A0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x091B0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x081C0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x071D0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x061E0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x051F0001); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001); - } -} - -void halbtc8192e2ant_agc_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean agc_table_en) -{ - coex_dm->cur_agc_table_en = agc_table_en; - - if (!force_exec) { - if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) - return; - } - halbtc8192e2ant_set_agc_table(btcoexist, agc_table_en); - - coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; -} - -void halbtc8192e2ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8192e2ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8192e2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8192e2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - switch (type) { - case 0: - halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555, - 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 1: - halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a, - 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 2: - halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55dd55dd, - 0x5ada5ada, 0xffffff, 0x3); - break; - case 3: - halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5fdf5fdf, - 0x5fdb5fdb, 0xffffff, 0x3); - break; - case 4: - halbtc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff, - 0x5ffb5ffb, 0xffffff, 0x3); - break; - case 5: - halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5ddd5ddd, - 0x5fdb5fdb, 0xffffff, 0x3); - break; - case 6: - halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5fff5fff, - 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 7: - if (coex_sta->scan_ap_num <= NOISY_AP_NUM_THRESH_8192E) - halbtc8192e2ant_coex_table(btcoexist, force_exec, - 0xffffffff, 0xfafafafa, 0xffffff, 0x3); - else - halbtc8192e2ant_coex_table(btcoexist, force_exec, - 0xffffffff, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 8: - halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5f5f5f5f, - 0x5a5a5a5a, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8192e2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) - h2c_parameter[0] |= BIT(0); /* function enable */ - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8192e2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8192e2ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8192e2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8192e2ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8192e2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8192e2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - } - } - - h2c_parameter[0] = byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = byte5; - - coex_dm->ps_tdma_para[0] = byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8192e2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, - IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, - IN boolean limited_dig, IN boolean bt_lna_constrain) -{ - /* - u32 wifi_bw; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if(BTC_WIFI_BW_HT40 != wifi_bw) - { - if (shrink_rx_lpf) - shrink_rx_lpf = false; - } - */ - - halbtc8192e2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); - /* halbtc8192e2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); */ -} - -void halbtc8192e2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, - IN boolean agc_table_shift, IN boolean adc_back_off, - IN boolean sw_dac_swing, IN u32 dac_swing_lvl) -{ - halbtc8192e2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); - /* halbtc8192e2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */ - halbtc8192e2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, - dac_swing_lvl); -} - -void halbtc8192e2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - u32 u32tmp = 0; - - if (init_hwcfg) { - btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24); - btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700); - if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); - else - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); - - /* 0x4c[27][24]='00', Set Antenna to BB */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(24); - u32tmp &= ~BIT(27); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } else if (wifi_off) { - if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004); - else - btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004); - - /* 0x4c[27][24]='11', Set Antenna to BT, 0x64[8:7]=0, 0x64[2]=1 */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp |= BIT(24); - u32tmp |= BIT(27); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } - - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); - break; - case BTC_ANT_PATH_BT: - btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20); - break; - default: - case BTC_ANT_PATH_PTA: - btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4); - break; - } -} - -void halbtc8192e2ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - s8 wifi_duration_adjust = 0x0; - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_sta->scan_ap_num >= 40) - wifi_duration_adjust = -15; - else if (coex_sta->scan_ap_num >= 20) - wifi_duration_adjust = -10; - - - if (turn_on) { - switch (type) { - case 1: - default: /*d1,wb*/ - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x3c, - 0x03, 0x11, 0x10); - break; - case 2: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x32, - 0x03, 0x11, 0x10); - break; - case 3: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x28, - 0x03, 0x11, 0x10); - break; - case 4: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1e, - 0x03, 0x11, 0x10); - break; - case 5: /*d1,pb,TXpause*/ - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x3c, - 0x03, 0x90, 0x10); - break; - case 6: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x32, - 0x03, 0x90, 0x10); - break; - case 7: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x28, - 0x03, 0x90, 0x10); - break; - case 8: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x1e, - 0x03, 0x90, 0x10); - break; - case 9: /*d1,bb*/ - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x3c, - 0x03, 0x31, 0x10); - break; - case 10: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x32, - 0x03, 0x31, 0x10); - break; - case 11: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x28, - 0x03, 0x31, 0x10); - break; - case 12: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1e, - 0x03, 0x31, 0x10); - break; - case 13: /*d1,bb,TXpause*/ - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x3c, - 0x03, 0x30, 0x10); - break; - case 14: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x32, - 0x03, 0x30, 0x10); - break; - case 15: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x28, - 0x03, 0x30, 0x10); - break; - case 16: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1e, - 0x03, 0x30, 0x10); - break; - case 17: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x61, 0x20, - 0x03, 0x10, 0x10); - break; - case 18: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, - 0xe1, 0x90); - break; - case 19: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x25, - 0x25, 0xe1, 0x90); - break; - case 20: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x25, - 0x25, 0x60, 0x90); - break; - case 21: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x61, 0x35, - 0x03, 0x11, 0x11); - break; - case 22: /* d1,wb */ - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x14, - 0x03, 0x11, 0x14); - break; - case 23: /* d1,pb,TXpause */ - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x14, - 0x03, 0x90, 0x14); - break; - case 24: /* d1,bb */ - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x14, - 0x03, 0x31, 0x14); - break; - case 25: /* d1,bb,TXpause */ - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x14, - 0x03, 0x30, 0x14); - break; - case 71: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, - 0x1a, 0xe1, 0x90); - break; - /* following cases is for wifi rssi low // bad antenna isolation, started from 81 */ - case 80: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x3c, - 0x3, 0x10, 0x50); - break; - case 81: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, - 0x3a + wifi_duration_adjust, 0x3, 0x10, 0x50); - break; - case 82: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, - 0x30 + wifi_duration_adjust, 0x03, 0x10, 0x50); - break; - case 83: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x21, - 0x03, 0x10, 0x50); - break; - case 84: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x15, - 0x3, 0x10, 0x50); - break; - case 85: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x3a, - 0x03, 0x10, 0x50); - break; - case 86: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x21, - 0x03, 0x10, 0x50); - break; - case 87: - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x14, - 0x03, 0x10, 0x54); - break; - - } - } else { - /* disable PS tdma */ - switch (type) { - default: - case 0: /* ANT2PTA, 0x778=1 */ - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - halbtc8192e2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, false, false); - break; - case 1: /* ANT2BT, 0x778=3 */ - halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x8, 0x0); - delay_ms(5); - halbtc8192e2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, false, false); - break; - - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8192e2ant_set_switch_ss_type(IN struct btc_coexist *btcoexist, - IN u8 ss_type) -{ - u8 mimo_ps = BTC_MIMO_PS_DYNAMIC; - u32 dis_ra_mask = 0x0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], REAL set SS Type = %d\n", ss_type); - BTC_TRACE(trace_buf); - - dis_ra_mask = halbtc8192e2ant_decide_ra_mask(btcoexist, ss_type, - coex_dm->cur_ra_mask_type); - halbtc8192e2ant_update_ra_mask(btcoexist, FORCE_EXEC, dis_ra_mask); - - if (ss_type == 1) { - halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); - /* switch ofdm path */ - btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x11); - btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x1); - btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81111111); - /* switch cck patch */ - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x1); */ - /* btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x81); */ - mimo_ps = BTC_MIMO_PS_STATIC; - } else if (ss_type == 2) { - halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x33); - btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x3); - btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81121313); - /* remove, if 0xe77[2]=0x0 then CCK will fail, advised by Jenyu */ - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x0); */ - /* btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x41); */ - mimo_ps = BTC_MIMO_PS_DYNAMIC; - } - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_SEND_MIMO_PS, - &mimo_ps); /* set rx 1ss or 2ss */ -} - -void halbtc8192e2ant_switch_ss_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 new_ss_type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s Switch SS Type = %d\n", - (force_exec ? "force to" : ""), new_ss_type); - BTC_TRACE(trace_buf); - coex_dm->cur_ss_type = new_ss_type; - - if (!force_exec) { - if (coex_dm->pre_ss_type == coex_dm->cur_ss_type) - return; - } - halbtc8192e2ant_set_switch_ss_type(btcoexist, coex_dm->cur_ss_type); - - coex_dm->pre_ss_type = coex_dm->cur_ss_type; -} - -void halbtc8192e2ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8192e2ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - ps_type = BTC_PS_WIFI_NATIVE; - lps_val = 0x0; - rpwm_val = 0x0; - } - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - break; - case BTC_PS_LPS_ON: - halbtc8192e2ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8192e2ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - break; - default: - break; - } -} - - -void halbtc8192e2ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* fw all off */ - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0); - - halbtc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - halbtc8192e2ant_switch_ss_type(btcoexist, FORCE_EXEC, 2); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - -void halbtc8192e2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - - - /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);*/ - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - -boolean halbtc8192e2ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean common = false, wifi_connected = false, wifi_busy = false; - boolean bt_hs_on = false, low_pwr_disable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (bt_link_info->sco_exist || bt_link_info->hid_exist) - halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0); - else - halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - if (!wifi_connected) { - - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non-connected idle!!\n"); - BTC_TRACE(trace_buf); - - if ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || - (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);*/ - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } else { - /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);*/ - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - } - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - common = true; - } else { - if (BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);*/ - - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else if (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status) { - - if (bt_hs_on) - return false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);*/ - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else { - - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - common = false; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);*/ - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 21); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, - NORMAL_EXEC, 6); - halbtc8192e2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, 0); - halbtc8192e2ant_sw_mechanism1(btcoexist, false, - false, false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - common = true; - } - } - } - - return common; -} -void halbtc8192e2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, - IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0; - - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - { - if (sco_hid) { - if (tx_pause) { - if (max_interval == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } else if (max_interval == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (max_interval == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } else { - if (max_interval == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } else if (max_interval == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (max_interval == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } else { - if (tx_pause) { - if (max_interval == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (max_interval == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (max_interval == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } - } else { - if (max_interval == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (max_interval == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (max_interval == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } - } - } - } - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* acquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ - if (wait_count <= 2) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ - if (wait_count == 1) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (max_interval == 1) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 13); - coex_dm->ps_tdma_du_adj_type = 13; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 1); - coex_dm->ps_tdma_du_adj_type = 1; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 71); - coex_dm->ps_tdma_du_adj_type = - 71; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } - } - } - } else if (max_interval == 2) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } - } - } - } else if (max_interval == 3) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8192e2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8192e2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } - } - } - - /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ - /* then we have to adjust it back to the previous record one. */ - if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", - coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (!scan && !link && !roam) - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); - BTC_TRACE(trace_buf); - } - } -} - -/* ****************** - * pstdma for wifi rssi low - * ****************** */ -void halbtc8192e2ant_tdma_duration_adjust_for_wifi_rssi_low( - IN struct btc_coexist *btcoexist/* , */ /* IN u8 wifi_status */) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0, bt_info_ext; - - coex_dm->auto_tdma_adjust = false; - - retry_count = coex_sta->bt_retry_cnt; - bt_info_ext = coex_sta->bt_info_ext; - - if (!coex_dm->auto_tdma_adjust_low_rssi) { - coex_dm->auto_tdma_adjust_low_rssi = true; - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 81); - coex_dm->ps_tdma_du_adj_type = 81; - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* acquire the BT TRx retry count from BT_Info byte2 - * retry_count = coex_sta->bt_retry_cnt; - * bt_info_ext = coex_sta->bt_info_ext; */ - result = 0; - wait_count++; - - if ((coex_sta->low_priority_tx) > 1050 || - (coex_sta->low_priority_rx) > 1250) - retry_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ - if (wait_count <= 2) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ - if (wait_count == 1) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 80) { - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 81); - coex_dm->ps_tdma_du_adj_type = 81; - } else if (coex_dm->cur_ps_tdma == 81) { - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 82); - coex_dm->ps_tdma_du_adj_type = 82; - } else if (coex_dm->cur_ps_tdma == 82) { - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 83); - coex_dm->ps_tdma_du_adj_type = 83; - } else if (coex_dm->cur_ps_tdma == 83) { - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 84); - coex_dm->ps_tdma_du_adj_type = 84; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 84) { - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 83); - coex_dm->ps_tdma_du_adj_type = 83; - } else if (coex_dm->cur_ps_tdma == 83) { - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 82); - coex_dm->ps_tdma_du_adj_type = 82; - } else if (coex_dm->cur_ps_tdma == 82) { - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 81); - coex_dm->ps_tdma_du_adj_type = 81; - } else if ((coex_dm->cur_ps_tdma == 81) && - (coex_sta->scan_ap_num <= 5)) { - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 81); - coex_dm->ps_tdma_du_adj_type = 81; - } - } - - if (coex_dm->cur_ps_tdma != 80 && - coex_dm->cur_ps_tdma != 81 && - coex_dm->cur_ps_tdma != 82 && - coex_dm->cur_ps_tdma != 83 && - coex_dm->cur_ps_tdma != 84) { - /* recover to previous adjust type */ - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - } - } -} - - -void halbtc8192e2ant_get_bt_rssi_threshold(IN struct btc_coexist *btcoexist, - IN u8 *pThres0, IN u8 *pThres1) -{ - u8 ant_type; - - struct btc_board_info *board_info = &btcoexist->board_info; - - ant_type = board_info->ant_type; - - switch (ant_type) { - case BTC_ANT_TYPE_0: - *pThres0 = 100; - *pThres1 = 100; - break; - case BTC_ANT_TYPE_1: - *pThres0 = 34; - *pThres1 = 42; - break; - case BTC_ANT_TYPE_2: - *pThres0 = 34; - *pThres1 = 42; - break; - case BTC_ANT_TYPE_3: - *pThres0 = 34; - *pThres1 = 42; - break; - case BTC_ANT_TYPE_4: - *pThres0 = 34; - *pThres1 = 42; - break; - default: - break; - } -} - - - - -/* SCO only or SCO+PAN(HS) */ -void halbtc8192e2ant_action_sco(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - else - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - else - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - -void halbtc8192e2ant_action_sco_pan(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - - halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - - if ((BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))) - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - else - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); - else - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); - - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - else - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); -} - - -void halbtc8192e2ant_action_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 anttype = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype); - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - if (anttype == 0) { - /*ANTTYPE = 0 92E 2ant with SPDT*/ - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (anttype == 1) { - /*92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation*/ - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (anttype == 2) { - /*ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation*/ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) { - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - } else { - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - } - } else if (anttype == 3) { - /*ANTTYPE = 3, 92E 3ant with good ant. isolation*/ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) { - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - } else { - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - } - } - - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8192e2ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - boolean long_dist = false; - u8 anttype = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype); - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - if (anttype == 0) { - /*ANTTYPE = 0 92E 2ant with SPDT*/ - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 87); - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } else if (anttype == 1) { - /*92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation*/ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) { - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 25); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } else { - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 87); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } else if (anttype == 2) { - /*ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation*/ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) { - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 5); - } else { - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 87); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } else if (anttype == 3) { - /*ANTTYPE = 3, 92E 3ant with good ant. isolation*/ - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } - - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, true, - 0x06); - else - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); -} - -void halbtc8192e2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 2); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false, - 2); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false, - 2); - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - } - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - true, 0x6); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - true, 0x6); - } - } -} - -void halbtc8192e2ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - /* wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, 0); */ - wifi_rssi_state = BTC_RSSI_STATE_LOW; - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); - else - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85); - - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - else - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); -} - -/* PAN(HS) only */ -void halbtc8192e2ant_action_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - /* halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);*/ - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - if ((bt_rssi_state == BTC_RSSI_STATE_LOW) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* PAN(EDR)+A2DP */ -void halbtc8192e2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - /* wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, 0); */ - wifi_rssi_state = BTC_RSSI_STATE_LOW; - - if ((BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))) - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 4); - else - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); - - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - else - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - -} - -void halbtc8192e2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - - if ((BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))) - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - else - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); - else - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); - - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - else - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - -} - -/* HID+A2DP+PAN(EDR) */ -void halbtc8192e2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - - if ((BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))) - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - else - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 4); - else - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); - - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - else - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); -} - -void halbtc8192e2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0, anttype = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype); - - wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42); - - if (anttype == 0) { - /*92E 2ant with SPDT*/ - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 87); - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - } else if (anttype == 1) { - /*92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation*/ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) { - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 25); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - } else { - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 87); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - } - } else if (anttype == 2) { - /*ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation*/ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) { - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 25); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - } else { - halbtc8192e2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 87); - halbtc8192e2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - } - } else if (anttype == 3) { - /*ANTTYPE = 3, 92E 3ant with good ant. isolation*/ - halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } - - halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false); - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E)) - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, true, - 0x06); - else - halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); -} - -void halbtc8192e2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - algorithm = halbtc8192e2ant_action_algorithm(btcoexist); - if (coex_sta->c2h_bt_inquiry_page && - (BT_8192E_2ANT_COEX_ALGO_PANHS != algorithm)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_bt_inquiry(btcoexist); - return; - } - - coex_dm->cur_algorithm = algorithm; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", - coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - - if (halbtc8192e2ant_is_common_action(btcoexist)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant common.\n"); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - - } else { - if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", - coex_dm->pre_algorithm, coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - - } - switch (coex_dm->cur_algorithm) { - case BT_8192E_2ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_sco(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_SCO_PAN: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO+PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_sco_pan(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_hid(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_a2dp(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_pan_edr(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_pan_hs(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_pan_edr_hid(btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8192E_2ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_action_hid_a2dp(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = unknown!!\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_coex_all_off(btcoexist); - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up) -{ - u16 u16tmp = 0; - u8 u8tmp = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - if (back_up) { - /* backup rf 0x1e value */ - coex_dm->bt_rf_0x1e_backup = - btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff); - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } - - /* antenna sw ctrl to bt */ - halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, false); - - halbtc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - /* antenna switch control parameter */ - /* btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555); */ - - /* coex parameters */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* enable PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); - /* enable mailbox interface */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40); - u16tmp |= BIT(9); - btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp); - - /* enable PTA I2C mailbox */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101); - u8tmp |= BIT(4); - btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp); - - /* enable bt clock when wifi is disabled. */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93); - u8tmp |= BIT(0); - btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp); - /* enable bt clock when suspend. */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); - u8tmp |= BIT(0); - btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); - - /* Give bt_coex_supported_version the default value */ - coex_sta->bt_coex_supported_version = 0; -} - -/* ************************************************************ - * work around function start with wa_halbtc8192e2ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8192e2ant_ - * ************************************************************ */ -void ex_halbtc8192e2ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8192e2ant_init_hw_config(btcoexist, true); -} - -void ex_halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - halbtc8192e2ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8192e2ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; - u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; - u32 phyver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Antenna type:", - board_info->ant_type); - CL_PRINTF(cli_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); - bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", - "CoexVer WL/ BT_Desired/ BT_Report", - glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant, - glcoex_ver_btdesired_8192e_2ant, bt_coex_ver, - (bt_coex_ver == 0xff ? "Unknown" : (bt_coex_ver >= - glcoex_ver_btdesired_8192e_2ant ? "Match" : - "Mis-Match"))); - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ v%d", - "W_FW/ B_FW/ Phy", fw_ver, bt_patch_ver, phyver); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", - "SCO/HID/PAN/A2DP", - stack_info->sco_exist, stack_info->hid_exist, - stack_info->pan_exist, stack_info->a2dp_exist); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8192E_2ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8192e_2ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "SS Type", - coex_dm->cur_ss_type); - CL_PRINTF(cli_buf); - - /* Sw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Sw mechanism]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", - "SM1[ShRf/ LpRA/ LimDig]", - coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, - coex_dm->limited_dig); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", - "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", - coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, - coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); - CL_PRINTF(cli_buf); - - /* Fw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Fw mechanism]============"); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - coex_dm->auto_tdma_adjust); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "DecBtPwr/ IgnWlanAct", - coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", - "RF-A, 0x1e initVal", - coex_dm->bt_rf_0x1e_backup); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "backup ARFR1/ARFR2/RL/AMaxTime", - coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2, - coex_dm->backup_retry_limit, - coex_dm->backup_ampdu_max_time); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0xc04/ 0xd04/ 0x90c", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", - u8tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x92c/ 0x930", - (u8tmp[0]), u32tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x40/ 0x4f", - u8tmp[0], u8tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", - u32tmp[0]); - CL_PRINTF(cli_buf); - - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_CCK); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(hp rx[31:16]/tx[15:0])", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(lp rx[31:16]/tx[15:0])", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 1) - halbtc8192e2ant_monitor_bt_ctr(btcoexist); -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8192e2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, - true); - halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; - halbtc8192e2ant_init_hw_config(btcoexist, false); - halbtc8192e2ant_init_coex_dm(btcoexist); - halbtc8192e2ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8192e2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8192e2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_SCAN_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_SCAN_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - - } -} - -void ex_halbtc8192e2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_ASSOCIATE_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_ASSOCIATE_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8192e2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = 0x1; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); -} - -void ex_halbtc8192e2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (type == BTC_PACKET_DHCP) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], DHCP Packet notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8192e2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean bt_busy = false, limited_dig = false; - boolean wifi_connected = false; - - coex_sta->c2h_bt_info_req_sent = false; - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8192E_2ANT_MAX) - rsp_source = BT_INFO_SRC_8192E_2ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (BT_INFO_SRC_8192E_2ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8192e2ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8192e2ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if ((coex_sta->bt_info_ext & BIT(3))) { - if (!btcoexist->manual_control && - !btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8192e2ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - } - -#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8192e2ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8192E_2ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8192E_2ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8192E_2ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8192E_2ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8192E_2ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - } - - halbtc8192e2ant_update_bt_link_info(btcoexist); - - if (!(bt_info & BT_INFO_8192E_2ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8192E_2ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8192E_2ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8192E_2ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8192E_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8192E_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { - bt_busy = true; - limited_dig = true; - } else { - bt_busy = false; - limited_dig = false; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - coex_dm->limited_dig = limited_dig; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); - - halbtc8192e2ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8192e2ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true); - halbtc8192e2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - ex_halbtc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); -} - -void ex_halbtc8192e2ant_periodical(IN struct btc_coexist *btcoexist) -{ - - if ((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) - coex_sta->bt_coex_supported_version = - btcoexist->btc_get_bt_coex_supported_version(btcoexist); - -#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0) - halbtc8192e2ant_query_bt_info(btcoexist); - halbtc8192e2ant_monitor_bt_ctr(btcoexist); - halbtc8192e2ant_monitor_wifi_ctr(btcoexist); - halbtc8192e2ant_monitor_bt_enable_disable(btcoexist); -#else - halbtc8192e2ant_monitor_wifi_ctr(btcoexist); - - if (halbtc8192e2ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust) - halbtc8192e2ant_run_coexist_mechanism(btcoexist); -#endif -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ - - diff --git a/hal/btc/halbtc8192e2ant.h b/hal/btc/halbtc8192e2ant.h deleted file mode 100644 index b77b3c4..0000000 --- a/hal/btc/halbtc8192e2ant.h +++ /dev/null @@ -1,225 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8192E_SUPPORT == 1) -/* ******************************************* - * The following is for 8192E 2Ant BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8192E_2ANT 0 - -#define BT_INFO_8192E_2ANT_B_FTP BIT(7) -#define BT_INFO_8192E_2ANT_B_A2DP BIT(6) -#define BT_INFO_8192E_2ANT_B_HID BIT(5) -#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8192E_2ANT_B_CONNECTION BIT(0) - -#define BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT 2 -#define NOISY_AP_NUM_THRESH_8192E 10 - -enum bt_info_src_8192e_2ant { - BT_INFO_SRC_8192E_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8192E_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8192E_2ANT_MAX -}; - -enum bt_8192e_2ant_bt_status { - BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8192E_2ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8192E_2ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8192E_2ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8192E_2ANT_BT_STATUS_MAX -}; - -enum bt_8192e_2ant_coex_algo { - BT_8192E_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8192E_2ANT_COEX_ALGO_SCO = 0x1, - BT_8192E_2ANT_COEX_ALGO_SCO_PAN = 0x2, - BT_8192E_2ANT_COEX_ALGO_HID = 0x3, - BT_8192E_2ANT_COEX_ALGO_A2DP = 0x4, - BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS = 0x5, - BT_8192E_2ANT_COEX_ALGO_PANEDR = 0x6, - BT_8192E_2ANT_COEX_ALGO_PANHS = 0x7, - BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8, - BT_8192E_2ANT_COEX_ALGO_PANEDR_HID = 0x9, - BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa, - BT_8192E_2ANT_COEX_ALGO_HID_A2DP = 0xb, - BT_8192E_2ANT_COEX_ALGO_MAX = 0xc -}; - -struct coex_dm_8192e_2ant { - /* fw mechanism */ - u8 pre_bt_dec_pwr_lvl; - u8 cur_bt_dec_pwr_lvl; - u8 pre_fw_dac_swing_lvl; - u8 cur_fw_dac_swing_lvl; - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean reset_tdma_adjust; - boolean auto_tdma_adjust; - boolean auto_tdma_adjust_low_rssi; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - - /* sw mechanism */ - boolean pre_rf_rx_lpf_shrink; - boolean cur_rf_rx_lpf_shrink; - u32 bt_rf_0x1e_backup; - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - boolean pre_dac_swing_on; - u32 pre_dac_swing_lvl; - boolean cur_dac_swing_on; - u32 cur_dac_swing_lvl; - boolean pre_adc_back_off; - boolean cur_adc_back_off; - boolean pre_agc_table_en; - boolean cur_agc_table_en; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u8 pre_ss_type; - u8 cur_ss_type; - - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 cur_ra_mask_type; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; -}; - -struct coex_sta_8192e_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - u8 bt_rssi; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8192E_2ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8192E_2ANT_MAX]; - boolean c2h_bt_inquiry_page; - u8 bt_retry_cnt; - u8 bt_info_ext; - u8 scan_ap_num; - u32 bt_coex_supported_version; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8192e2ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8192e2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8192e2ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e2ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8192e2ant_display_coex_info(IN struct btc_coexist *btcoexist); - -#else /* #if (RTL8192E_SUPPORT == 1) */ -#define ex_halbtc8192e2ant_power_on_setting(btcoexist) -#define ex_halbtc8192e2ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8192e2ant_init_coex_dm(btcoexist) -#define ex_halbtc8192e2ant_ips_notify(btcoexist, type) -#define ex_halbtc8192e2ant_lps_notify(btcoexist, type) -#define ex_halbtc8192e2ant_scan_notify(btcoexist, type) -#define ex_halbtc8192e2ant_connect_notify(btcoexist, type) -#define ex_halbtc8192e2ant_media_status_notify(btcoexist, type) -#define ex_halbtc8192e2ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8192e2ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8192e2ant_halt_notify(btcoexist) -#define ex_halbtc8192e2ant_periodical(btcoexist) -#define ex_halbtc8192e2ant_display_coex_info(btcoexist) - -#endif - -#endif - - diff --git a/hal/btc/halbtc8703b1ant.c b/hal/btc/halbtc8703b1ant.c deleted file mode 100644 index 34f11f1..0000000 --- a/hal/btc/halbtc8703b1ant.c +++ /dev/null @@ -1,4307 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for RTL8703B Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8703B_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8703b_1ant glcoex_dm_8703b_1ant; -static struct coex_dm_8703b_1ant *coex_dm = &glcoex_dm_8703b_1ant; -static struct coex_sta_8703b_1ant glcoex_sta_8703b_1ant; -static struct coex_sta_8703b_1ant *coex_sta = &glcoex_sta_8703b_1ant; -static struct psdscan_sta_8703b_1ant gl_psd_scan_8703b_1ant; -static struct psdscan_sta_8703b_1ant *psd_scan = &gl_psd_scan_8703b_1ant; - - -const char *const glbt_info_src_8703b_1ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; -/* ************************************************************ - * BtCoex Version Format: - * 1. date : glcoex_ver_date_XXXXX_1ant - * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant - * 3. BtCoexVersion : glcoex_ver_btdesired_XXXXX_1ant - * 4. others : glcoex_ver_XXXXXX_XXXXX_1ant - * - * Variable should be indicated IC and Antenna numbers !!! - * Please strictly follow this order and naming style !!! - * - * ************************************************************ */ -u32 glcoex_ver_date_8703b_1ant = 20161027; -u32 glcoex_ver_8703b_1ant = 0x0f; -u32 glcoex_ver_btdesired_8703b_1ant = 0x0d; - - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8703b1ant_ - * ************************************************************ */ -u8 halbtc8703b1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8703b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8703b1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8703b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8703b1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8703b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8703b1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8703b1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8703b1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8703b1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8703b1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8703b1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8703b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8703b1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8703b1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -void halbtc8703b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, - cnt_autoslot_hang = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ - /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - - if (coex_sta->high_priority_rx >= 15) { - if (cnt_overhead < 3) - cnt_overhead++; - - if (cnt_overhead == 3) - coex_sta->is_hiPri_rx_overhead = true; - } else { - if (cnt_overhead > 0) - cnt_overhead--; - - if (cnt_overhead == 0) - coex_sta->is_hiPri_rx_overhead = false; - } - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", - reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); - - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - if ((coex_sta->low_priority_tx > 1150) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - if ((coex_sta->low_priority_rx >= 1150) && - (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) - && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && - (coex_sta->bt_link_exist)) { - if (cnt_slave >= 2) { - bt_link_info->slave_role = true; - cnt_slave = 2; - } else - cnt_slave++; - } else { - if (cnt_slave == 0) { - bt_link_info->slave_role = false; - cnt_slave = 0; - } else - cnt_slave--; - - } - - if (coex_sta->is_tdma_btautoslot) { - if ((coex_sta->low_priority_tx >= 1300) && - (coex_sta->low_priority_rx <= 150)) { - if (cnt_autoslot_hang >= 2) { - coex_sta->is_tdma_btautoslot_hang = true; - cnt_autoslot_hang = 2; - } else - cnt_autoslot_hang++; - } else { - if (cnt_autoslot_hang == 0) { - coex_sta->is_tdma_btautoslot_hang = false; - cnt_autoslot_hang = 0; - } else - cnt_autoslot_hang--; - } - } - - if (!coex_sta->bt_disabled) { - if ((coex_sta->high_priority_tx == 0) && - (coex_sta->high_priority_rx == 0) && - (coex_sta->low_priority_tx == 0) && - (coex_sta->low_priority_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8703b1ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; - } - } - } - -} - - -void halbtc8703b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ -#if 1 - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false, - wifi_scan = false; - boolean bt_idle = false, wl_idle = false; - static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, - wl_noisy_count1 = 3, wl_noisy_count2 = 0; - u32 total_cnt, reg_val1, reg_val2, cck_cnt; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - - coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_VHT); - - cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; - - if (cck_cnt > 250) { - if (wl_noisy_count2 < 3) - wl_noisy_count2++; - - if (wl_noisy_count2 == 3) { - wl_noisy_count0 = 0; - wl_noisy_count1 = 0; - } - } else if (cck_cnt < 50) { - if (wl_noisy_count0 < 3) - wl_noisy_count0++; - - if (wl_noisy_count0 == 3) { - wl_noisy_count1 = 0; - wl_noisy_count2 = 0; - } - } else { - if (wl_noisy_count1 < 3) - wl_noisy_count1++; - - if (wl_noisy_count1 == 3) { - wl_noisy_count0 = 0; - wl_noisy_count2 = 0; - } - } - - if (wl_noisy_count2 == 3) - coex_sta->wl_noisy_level = 2; - else if (wl_noisy_count1 == 3) - coex_sta->wl_noisy_level = 1; - else - coex_sta->wl_noisy_level = 0; - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht; - - if ((coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 3) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = true; - - coex_sta->pre_ccklock = coex_sta->cck_lock; - -#endif -} - - - -boolean halbtc8703b1ant_is_wifibt_status_changed(IN struct btc_coexist - *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false, pre_bt_off = false, pre_bt_slave = false; - static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (coex_sta->bt_disabled != pre_bt_off) { - pre_bt_off = coex_sta->bt_disabled; - - if (coex_sta->bt_disabled) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - - BTC_TRACE(trace_buf); - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - coex_sta->bt_ble_scan_type = 0; - coex_sta->bt_ble_scan_para[0] = 0; - coex_sta->bt_ble_scan_para[1] = 0; - coex_sta->bt_ble_scan_para[2] = 0; - - return true; - } - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { - pre_wl_noisy_level = coex_sta->wl_noisy_level; - return true; - } - } - - if (!coex_sta->bt_disabled) { - if (coex_sta->hid_busy_num != pre_hid_busy_num) { - pre_hid_busy_num = coex_sta->hid_busy_num; - return true; - } - } - - if (bt_link_info->slave_role != pre_bt_slave) { - pre_bt_slave = bt_link_info->slave_role; - return true; - } - - return false; -} - - -void halbtc8703b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - boolean bt_busy = false; - - - coex_sta->num_of_profile = 0; - - /* set link exist status */ - if (!(coex_sta->bt_info & BT_INFO_8703B_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_FTP) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = false; - - if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_A2DP) { - coex_sta->a2dp_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = false; - - if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_HID) { - coex_sta->hid_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = false; - - if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) { - coex_sta->sco_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = false; - - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->acl_busy = coex_sta->acl_busy; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; - - if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_INQ_PAGE) { - coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_INQ_PAGE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); - } else if (!(coex_sta->bt_info & BT_INFO_8703B_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - } else if (coex_sta->bt_info == BT_INFO_8703B_1ANT_B_CONNECTION) { - /* connection exists but no busy */ - coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - } else if (((coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) || - (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_BUSY)) && - (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_ACL_BUSY)) { - coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); - } else if ((coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) || - (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - } else if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - } else { - coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - } - - BTC_TRACE(trace_buf); - - if ((BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); -} - - -void halbtc8703b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = - 0x1; /* enable BT AFH skip WL channel for 8703b because BT Rx LO interference */ - /* h2c_parameter[0] = 0x0; */ - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); - -} - -void halbtc8703b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8703b1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8703b1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8703b1ant_set_fw_low_penalty_ra(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8703b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - - halbtc8703b1ant_set_fw_low_penalty_ra(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8703b1ant_write_score_board( - IN struct btc_coexist *btcoexist, - IN u16 bitpos, - IN boolean state -) -{ - - static u16 originalval = 0x8002; - - if (state) - originalval = originalval | bitpos; - else - originalval = originalval & (~bitpos); - - - btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); -#if 0 - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "\n [BTCoex], ********** Write Scoreboard = %x**********\n", - originalval); - BTC_TRACE(trace_buf); -#endif - -} - -void halbtc8703b1ant_read_score_board( - IN struct btc_coexist *btcoexist, - IN u16 *score_board_val -) -{ - - *score_board_val = (btcoexist->btc_read_2byte(btcoexist, - 0xaa)) & 0x7fff; -} - -void halbtc8703b1ant_post_state_to_bt( - IN struct btc_coexist *btcoexist, - IN u16 type, - IN boolean state -) -{ - halbtc8703b1ant_write_score_board(btcoexist, (u16) type, state); -} - -void halbtc8703b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - u16 u16tmp; - - /* This function check if bt is disabled */ -#if 1 - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - - -#else /* 8703b BT can't show correct on/off status in scoreboard[1] 2015/11/26 */ - - halbtc8703b1ant_read_score_board(btcoexist, &u16tmp); - - bt_active = u16tmp & BIT(1); - - -#endif - - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } else { - - bt_disable_cnt++; - if (bt_disable_cnt >= 2) { - bt_disabled = true; - bt_disable_cnt = 2; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } - - if (bt_disabled) - halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); - else - halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true); - - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - - } -} - - - -void halbtc8703b1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, - IN boolean isenable) -{ - -#if (BT_8703B_1ANT_ENABLE_GNTBT_TO_GPIO14 == 1) - if (isenable) { - /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); - - /* enable GNT_BT debug to GPIO */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0); - } else { - /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); - - /* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1); - } -#endif -} - -u32 halbtc8703b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, - IN u16 reg_addr) -{ - u32 j = 0; - - - /* wait for ready bit before access 0x7c0 */ - btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr); - - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x7c3)&BIT(5)) == 0) && - (j < BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - return btcoexist->btc_read_4byte(btcoexist, - 0x7c8); /* get read data */ - -} - -void halbtc8703b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist - *btcoexist, - IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) -{ - u32 val, i = 0, j = 0, bitpos = 0; - - - if (bit_mask == 0x0) - return; - if (bit_mask == 0xffffffff) { - btcoexist->btc_write_4byte(btcoexist, 0x7c4, - reg_value); /* put write data */ - - /* wait for ready bit before access 0x7c0 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x7c3)&BIT(5)) == 0) && - (j < BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x7c0, - 0xc00F0000 | reg_addr); - } else { - for (i = 0; i <= 31; i++) { - if (((bit_mask >> i) & 0x1) == 0x1) { - bitpos = i; - break; - } - } - - /* read back register value before write */ - val = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - reg_addr); - val = (val & (~bit_mask)) | (reg_value << bitpos); - - btcoexist->btc_write_4byte(btcoexist, 0x7c4, - val); /* put write data */ - - /* wait for ready bit before access 0x7c0 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x7c3)&BIT(5)) == 0) && - (j < BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x7c0, - 0xc00F0000 | reg_addr); - - } - -} - -void halbtc8703b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 val; - - val = (enable) ? 1 : 0; - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, - val); /* 0x38[7] */ - -} - -void halbtc8703b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, - IN boolean wifi_control) -{ - u8 val; - - val = (wifi_control) ? 1 : 0; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, - val); /* 0x70[26] */ - -} - -void halbtc8703b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, val_orig = 0; - - if (!sw_control) - val = 0x0; - else if (state & 0x1) - val = 0x3; - else - val = 0x1; - - val_orig = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - switch (control_block) { - case BT_8703B_1ANT_GNT_BLOCK_RFC_BB: - default: - val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff); - break; - case BT_8703B_1ANT_GNT_BLOCK_RFC: - val = (val << 14) | (val_orig & 0xffff3fff); - break; - case BT_8703B_1ANT_GNT_BLOCK_BB: - val = (val << 10) | (val_orig & 0xfffff3ff); - break; - } - - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); -} - - -void halbtc8703b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, val_orig = 0; - - if (!sw_control) - val = 0x0; - else if (state & 0x1) - val = 0x3; - else - val = 0x1; - - val_orig = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - switch (control_block) { - case BT_8703B_1ANT_GNT_BLOCK_RFC_BB: - default: - val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff); - break; - case BT_8703B_1ANT_GNT_BLOCK_RFC: - val = (val << 12) | (val_orig & 0xffffcfff); - break; - case BT_8703B_1ANT_GNT_BLOCK_BB: - val = (val << 8) | (val_orig & 0xfffffcff); - break; - } - - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); -} - - -void halbtc8703b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u16 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8703B_1ANT_CTT_WL_VS_LTE: - reg_addr = 0xa0; - break; - case BT_8703B_1ANT_CTT_BT_VS_LTE: - reg_addr = 0xa4; - break; - } - - if (reg_addr != 0x0000) - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ - - -} - - -void halbtc8703b1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u8 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8703B_1ANT_LBTT_WL_BREAK_LTE: - reg_addr = 0xa8; - break; - case BT_8703B_1ANT_LBTT_BT_BREAK_LTE: - reg_addr = 0xac; - break; - case BT_8703B_1ANT_LBTT_LTE_BREAK_WL: - reg_addr = 0xb0; - break; - case BT_8703B_1ANT_LBTT_LTE_BREAK_BT: - reg_addr = 0xb4; - break; - } - - if (reg_addr != 0x0000) - halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ - - -} - -void halbtc8703b1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 interval, - IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, - IN u8 val0x6c4_b3) -{ - static u8 pre_h2c_parameter[6] = {0}; - u8 cur_h2c_parameter[6] = {0}; - u8 i, match_cnt = 0; - - cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ - - cur_h2c_parameter[1] = interval; - cur_h2c_parameter[2] = val0x6c4_b0; - cur_h2c_parameter[3] = val0x6c4_b1; - cur_h2c_parameter[4] = val0x6c4_b2; - cur_h2c_parameter[5] = val0x6c4_b3; - - if (!force_exec) { - for (i = 1; i <= 5; i++) { - if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) - break; - - match_cnt++; - } - - if (match_cnt == 5) - return; - } - - for (i = 1; i <= 5; i++) - pre_h2c_parameter[i] = cur_h2c_parameter[i]; - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); -} - - -void halbtc8703b1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8703b1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8703b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8703b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - u32 break_table; - u8 select_table; - - coex_sta->coex_table_type = type; - - if (coex_sta->concurrent_rx_mode_on == true) { - break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ - select_table = - 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ - } else { - break_table = 0xffffff; - select_table = 0x3; - } - - switch (type) { - case 0: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, break_table, - select_table); - break; - case 1: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 2: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0xaa5a5a5a, 0xaa5a5a5a, break_table, - select_table); - break; - case 3: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0xaa555555, 0xaa5a5a5a, break_table, - select_table); - break; - case 4: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 5: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, break_table, - select_table); - break; - case 6: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 7: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, break_table, - select_table); - break; - case 8: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xaaaaaaaa, break_table, - select_table); - break; - case 9: - halbtc8703b1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaaaa5aaa, break_table, - select_table); - break; - default: - break; - } -} - -void halbtc8703b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) - h2c_parameter[0] |= BIT(0);/* function enable */ - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8703b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8703b1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8703b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8703b1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8703b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8703b1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - /*halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - /*halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8);*/ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8703b1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - coex_sta->force_lps_on = false; - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - - break; - case BTC_PS_LPS_ON: - coex_sta->force_lps_on = true; - halbtc8703b1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8703b1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - - break; - case BTC_PS_LPS_OFF: - coex_sta->force_lps_on = false; - halbtc8703b1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - - break; - default: - break; - } -} - - - -void halbtc8703b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - if (byte5 & BIT(2)) - coex_sta->is_tdma_btautoslot = true; - else - coex_sta->is_tdma_btautoslot = false; - - /* release bt-auto slot for auto-slot hang is detected!! */ - if (coex_sta->is_tdma_btautoslot) - if ((coex_sta->is_tdma_btautoslot_hang) || - (bt_link_info->slave_role)) - byte5 = byte5 & 0xfb; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - - halbtc8703b1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - } - } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - - halbtc8703b1ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } else { - halbtc8703b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, - 0x0); - } - - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - - -void halbtc8703b1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - u8 rssi_adjust_val = 0; - static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; - static boolean pre_wifi_busy = false; - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (wifi_busy != pre_wifi_busy) { - force_exec = true; - pre_wifi_busy = wifi_busy; - } - - /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist)) - psTdmaByte4Modify = 0x1; - else - psTdmaByte4Modify = 0x0; - - if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { - - force_exec = true; - pre_psTdmaByte4Modify = psTdmaByte4Modify; - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - if (turn_on) { - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - } - - - if (turn_on) { - switch (type) { - default: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x11); - break; - - case 3: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x3a, 0x03, 0x10, 0x50); - break; - case 4: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x21, 0x03, 0x10, 0x50); - break; - case 5: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x03, 0x11, 0x11); - break; - case 6: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x20, 0x03, 0x11, 0x11); - break; - case 7: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x54 | - psTdmaByte4Modify); - break; - case 8: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x54 | - psTdmaByte4Modify); - break; - case 9: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x55, 0x10, 0x03, 0x10, 0x54 | - psTdmaByte4Modify); - break; - case 10: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); - break; - case 11: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x65, 0x25, 0x03, 0x11, 0x11 | - psTdmaByte4Modify); - break; - case 12: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x55, 0x30, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 13: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x25, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 14: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x15, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 15: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x20, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 16: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x15 | - psTdmaByte4Modify); - break; - case 17: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x14); - break; - case 18: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x30, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 19: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x03, 0x11, 0x10); - break; - case 20: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); - break; - case 21: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); - break; - case 22: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x25, 0x03, 0x11, 0x10); - break; - case 23: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x10); - break; - case 32: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x11); - break; - case 33: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x10); - break; - case 57: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 58: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 67: - halbtc8703b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x10 | - psTdmaByte4Modify); - break; - } - } else { - - /* disable PS tdma */ - switch (type) { - case 8: /* PTA Control */ - halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - break; - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - break; - case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */ - halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8703b1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, - IN u8 phase) -{ - u32 cnt_bt_cal_chk = 0; - boolean is_in_mp_mode = false; - u8 u8tmp = 0; - u32 u32tmp1 = 0, u32tmp2 = 0; - - - u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - /* To avoid indirect access fail */ - if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { - force_exec = true; - coex_sta->gnt_error_cnt++; - } - -#if 1 - u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0x54); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Before Ant Setup) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif - - coex_dm->cur_ant_pos_type = ant_pos_type; - - if (!force_exec) { - if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Skip Antenna Path Setup because no change!!**********\n"); - BTC_TRACE(trace_buf); - return; - } - } - - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; - - switch (phase) { - case BT_8703B_1ANT_PHASE_COEX_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8703b1ant_ltecoex_set_coex_table( - btcoexist, - BT_8703B_1ANT_CTT_WL_VS_LTE, - 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8703b1ant_ltecoex_set_coex_table( - btcoexist, - BT_8703B_1ANT_CTT_BT_VS_LTE, - 0xffff); - - /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ - while (cnt_bt_cal_chk <= 20) { - u8tmp = btcoexist->btc_read_1byte( - btcoexist, - 0x49d); - cnt_bt_cal_chk++; - if (u8tmp & BIT(0)) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - delay_ms(50); - } else { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - break; - } - } - - - /* set Path control owner to WL at initial step */ - halbtc8703b1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8703B_1ANT_PCO_WLSIDE); - - /* set GNT_BT to SW high */ - halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW low */ - halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_LOW); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - coex_sta->run_time_state = false; - break; - case BT_8703B_1ANT_PHASE_WLANONLY_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8703b1ant_ltecoex_set_coex_table( - btcoexist, - BT_8703B_1ANT_CTT_WL_VS_LTE, - 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8703b1ant_ltecoex_set_coex_table( - btcoexist, - BT_8703B_1ANT_CTT_BT_VS_LTE, - 0xffff); - - /* set Path control owner to WL at initial step */ - halbtc8703b1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8703B_1ANT_PCO_WLSIDE); - - /* set GNT_BT to SW low */ - halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_LOW); - /* Set GNT_WL to SW high */ - halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = - BTC_ANT_PATH_WIFI; - - coex_sta->run_time_state = false; - break; - case BT_8703B_1ANT_PHASE_WLAN_OFF: - /* Disable LTE Coex Function in WiFi side */ - halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0); - - /* set Path control owner to BT */ - halbtc8703b1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8703B_1ANT_PCO_BTSIDE); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - coex_sta->run_time_state = false; - break; - case BT_8703B_1ANT_PHASE_2G_RUNTIME: - halbtc8703b1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8703B_1ANT_PCO_WLSIDE); - - /* set GNT_BT to PTA */ - halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8703B_1ANT_SIG_STA_SET_BY_HW); - /* Set GNT_WL to PTA */ - halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8703B_1ANT_SIG_STA_SET_BY_HW); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_PTA; - - coex_sta->run_time_state = true; - break; - case BT_8703B_1ANT_PHASE_BTMPMODE: - halbtc8703b1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8703B_1ANT_PCO_WLSIDE); - - /* set GNT_BT to high */ - halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to low */ - halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_LOW); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - coex_sta->run_time_state = false; - break; - } - - -#if 1 - u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ant-Setup) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", - u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - -#endif -} - - -boolean halbtc8703b1ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - common = true; - } else if (wifi_connected && - (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - common = true; - } else if (!wifi_connected && - (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - common = true; - } else if (wifi_connected && - (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - common = true; - } else if (!wifi_connected && - (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE != - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } - - common = false; - } - - return common; -} - - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -u8 halbtc8703b1ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8703B_1ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8703b1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) -{ - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8703B_1ANT_PHASE_2G_RUNTIME); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8703b1ant_action_bt_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8703b1ant_action_bt_relink(IN struct btc_coexist *btcoexist) -{ - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - coex_sta->bt_relink_downcount = 2; -} - -void halbtc8703b1ant_action_bt_idle(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_busy) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - } else {/* if wl busy */ - - if (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - - if (coex_sta->is_hiPri_rx_overhead) - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - else - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 33); - } else { - - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - } - } -} - -void halbtc8703b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, wifi_busy = false, bt_busy = false; - boolean wifi_scan = false, wifi_link = false, wifi_roam = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); - - if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) - || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - - if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17); - else - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - } else if ((!wifi_connected) && (!wifi_scan)) { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (bt_link_info->pan_exist) { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist) { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - - if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) - || (coex_sta->wifi_is_high_pri_task)) - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - else - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } -} - - -void halbtc8703b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, wifi_busy = false; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - - if (bt_link_info->sco_exist) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else if (coex_sta->hid_busy_num >= 2) {/*for 4/18 hid */ - /* if 11bg mode */ - if (wifi_bw == 0) { - - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8703b1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11); - } else { - - if (wifi_busy) { - - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8703b1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11); - } else { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - } - } - } else { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 6); - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - } -} - - -void halbtc8703b1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8703B_1ANT_PHASE_2G_RUNTIME); - halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); -} - -void halbtc8703b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8703B_1ANT_PHASE_2G_RUNTIME); - - if (!bt_link_info->pan_exist) - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - else - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8703b1ant_action_wifi_linkscan_process(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - if (bt_link_info->pan_exist) { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } -} - -void halbtc8703b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false, wifi_turbo = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - if ((coex_sta->bt_relink_downcount != 0) - && (!bt_link_info->pan_exist) && (wifi_busy)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); - BTC_TRACE(trace_buf); - - /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);*/ - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (!wifi_busy) { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - - if (coex_sta->wl_noisy_level == 2) - halbtc8703b1ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 17); - else - halbtc8703b1ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - - if (wifi_turbo) - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if (((bt_link_info->a2dp_exist) && - (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - - if ((bt_link_info->hid_exist) && (coex_sta->hid_busy_num >= 2)) { - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8703b1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 12); - } else if (wifi_busy) { - if (((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) || - (!coex_sta->is_A2DP_3M)) - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 15); - else if (wifi_turbo) - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 18); - else - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 13); - } else - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - - if (bt_link_info->hid_exist) - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - else if (wifi_turbo) - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) {/* HID+A2DP */ - - if ((wifi_busy) && (coex_sta->hid_busy_num >= 2)) { /*for 4/18 hid */ - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8703b1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - } else { - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 8); - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } - - } else if ((bt_link_info->pan_only) - || (bt_link_info->hid_exist && bt_link_info->pan_exist)) { - /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - - if ((bt_link_info->hid_exist) && (bt_link_info->pan_exist) && - (coex_sta->hid_busy_num >= 2)) { - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); - halbtc8703b1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 12); - } else { - - if (!wifi_busy) - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 4); - else - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 3); - - if (bt_link_info->hid_exist) - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - else if (wifi_turbo) - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else - halbtc8703b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else { - /* BT no-profile busy (0x9) */ - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } -} - -void halbtc8703b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - /* tdma and coex table */ - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8703b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8703B_1ANT_PHASE_2G_RUNTIME); - - if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - - if (bt_link_info->hid_only)/* HID only */ - halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist); - else - halbtc8703b1ant_action_wifi_connected_bt_acl_busy(btcoexist); - - } else if ((BT_8703B_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist); - } else - halbtc8703b1ant_action_bt_idle(btcoexist); -} - - -void halbtc8703b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - - algorithm = halbtc8703b1ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - - if (halbtc8703b1ant_is_common_action(btcoexist)) { - - } else { - switch (coex_dm->cur_algorithm) { - case BT_8703B_1ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8703B_1ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8703B_1ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - break; - case BT_8703B_1ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - break; - case BT_8703B_1ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8703B_1ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8703B_1ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8703b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - boolean miracast_plus_bt = false, wifi_under_5g = false; - u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0, wifi_bw; - u8 iot_peer = BTC_IOT_PEER_UNKNOWN; - boolean scan = false, link = false, roam = false, under_4way = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (!coex_sta->run_time_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], return for run_time_state = false !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->freeze_coexrun_by_btinfo) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_action_bt_whql_test(btcoexist); - return; - } - - if (coex_sta->bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!!\n"); - halbtc8703b1ant_action_wifi_only(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_action_bt_inquiry(btcoexist); - return; - } - - if (coex_sta->is_setupLink) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is re-link !!!\n"); - halbtc8703b1ant_action_bt_relink(btcoexist); - return; - } - - if ((BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) - miracast_plus_bt = true; - else - miracast_plus_bt = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - false, 0x5); - - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", - scan, link, roam, under_4way); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_action_wifi_linkscan_process(btcoexist); - } else - halbtc8703b1ant_action_wifi_multi_port(btcoexist); - - return; - } else { - - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); - - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - - btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); - - if (BTC_IOT_PEER_CISCO == iot_peer) { - - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8703b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x10); - else - halbtc8703b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x8); - } else - halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x5); - } - - halbtc8703b1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is hs\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_action_bt_hs(btcoexist); - return; - } - - if ((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || - (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is idle\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_action_bt_idle(btcoexist); - return; - } - - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", - scan, link, roam, under_4way); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under linkscan process!!\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_action_wifi_linkscan_process(btcoexist); - } else if (wifi_connected) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under connected!!\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_action_wifi_connected(btcoexist); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under not-connected!!\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_action_wifi_not_connected(btcoexist); - } -} - - -void halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - - halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->pop_event_cnt = 0; - coex_sta->cnt_RemoteNameReq = 0; - coex_sta->cnt_ReInit = 0; - coex_sta->cnt_setupLink = 0; - coex_sta->cnt_IgnWlanAct = 0; - coex_sta->cnt_Page = 0; -} - -void halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up, IN boolean wifi_only) -{ - u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0; - u8 i = 0; - - u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70), - u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "\n [BTCoex], ********** 0x70/ 0x38/ 0x54 (Before Init HW config) = 0x%x/ 0x%x/ 0x%x**********\n", - u32tmp0, - u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - coex_sta->bt_ble_scan_type = 0; - coex_sta->bt_ble_scan_para[0] = 0; - coex_sta->bt_ble_scan_para[1] = 0; - coex_sta->bt_ble_scan_para[2] = 0; - coex_sta->gnt_error_cnt = 0; - coex_sta->bt_relink_downcount = 0; - - for (i = 0; i <= 9; i++) - coex_sta->bt_afh_map[i] = 0; - - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - - /* BT report packet sample rate */ - btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); - - /* Enable BT counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - - /* Enable PTA (3-wire function form BT side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); - - /* Enable PTA (tx/rx signal form WiFi side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); - - halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, false); - - if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ONOFF, true); - - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - - /* Antenna config */ - if (wifi_only) { - coex_sta->concurrent_rx_mode_on = false; - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, - BT_8703B_1ANT_PHASE_WLANONLY_INIT); - } else { - coex_sta->concurrent_rx_mode_on = true; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); - /* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8703B_1ANT_PHASE_COEX_INIT); - } - - /* PTA parameter */ - halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70), - u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x70/ 0x38/ 0x54 (After Init HW config) = 0x%x/ 0x%x/ 0x%x**********\n", - u32tmp0, - u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - -} - - - -/* ************************************************************ - * work around function start with wa_halbtc8703b1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8703b1ant_ - * ************************************************************ */ -void ex_halbtc8703b1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x0; - u16 u16tmp = 0x0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Execute 8703b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Ant Det Finish = %s, Ant Det Number = %d\n", - (board_info->btdm_ant_det_finish ? "Yes" : "No"), - board_info->btdm_ant_num_by_ant_det); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = true; - - /* enable BB, REG_SYS_FUNC_EN such that we can write BB/MAC reg correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - - /* set Path control owner to WiFi */ - halbtc8703b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8703B_1ANT_PCO_WLSIDE); - - /* set GNT_BT to high */ - halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to low */ - halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8703B_1ANT_GNT_BLOCK_RFC_BB, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8703B_1ANT_SIG_STA_SET_TO_LOW); - - /* set WLAN_ACT = 0 */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, false); - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - - u8tmp = 0; - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - - if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); - - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x70(MAC)/0x38/0x54 (Power-On) =0x%x/ 0x%x/ 0x%x**********\n", - btcoexist->btc_read_4byte(btcoexist, 0x70), - halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38), - halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54)); - BTC_TRACE(trace_buf); - - -} - -void ex_halbtc8703b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8703b1ant_init_hw_config(btcoexist, true, wifi_only); - btcoexist->stop_coex_dm = false; -} - -void ex_halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8703b1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; - u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; - static u8 pop_report_in_10s = 0; - u32 phyver = 0; - boolean lte_coex_on = false; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - if (psd_scan->ant_det_try_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", - "Ant PG Num/ Mech/ Pos", - board_info->pg_ant_num, board_info->btdm_ant_num, - board_info->btdm_ant_pos); - CL_PRINTF(cli_buf); - } else { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %d (%d/%d/%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos", - board_info->pg_ant_num, - board_info->btdm_ant_num_by_ant_det, - board_info->btdm_ant_pos, - psd_scan->ant_det_try_count, - psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); - CL_PRINTF(cli_buf); - - if (board_info->btdm_ant_det_finish) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - CL_PRINTF(cli_buf); - } - } - - - /*bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;*/ - bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); - - bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", - "CoexVer WL/ BT_Desired/ BT_Report", - glcoex_ver_date_8703b_1ant, glcoex_ver_8703b_1ant, - glcoex_ver_btdesired_8703b_1ant, - bt_coex_ver, - (bt_coex_ver == 0xff ? "Unknown" : - (bt_coex_ver >= glcoex_ver_btdesired_8703b_1ant ? - "Match":"Mis-Match"))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", - "W_FW/ B_FW/ Phy/ Kt", - fw_ver, bt_patch_ver, phyver, - coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", - "WifibHiPri/ Ccklock/ CckEverLock", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), - (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No")); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") - : ((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); - CL_PRINTF(cli_buf); - - if (pop_report_in_10s >= 5) { - coex_sta->pop_event_cnt = 0; - pop_report_in_10s = 0; - } - - if (coex_sta->num_of_profile != 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s%s%s%s%s", - "Profiles", - ((bt_link_info->a2dp_exist) ? "A2DP," : ""), - ((bt_link_info->sco_exist) ? "SCO," : ""), - ((bt_link_info->hid_exist) ? - ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : - "HID(2/18),") : ""), - ((bt_link_info->pan_exist) ? "PAN," : ""), - ((coex_sta->voice_over_HOGP) ? "Voice" : "")); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = None", - "Profiles"); - - CL_PRINTF(cli_buf); - - if (bt_link_info->a2dp_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", - "A2DP Rate/Bitpool/Auto_Slot", - ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), - coex_sta->a2dp_bit_pool, - ((coex_sta->is_autoslot) ? "On" : "Off") - ); - CL_PRINTF(cli_buf); - } - - if (bt_link_info->hid_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "HID PairNum/Forbid_Slot", - coex_sta->hid_pair_cnt, - coex_sta->forbidden_slot - ); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ 0x%x", - "Role/IgnWlanAct/Feature", - ((bt_link_info->slave_role) ? "Slave" : "Master"), - ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), - coex_sta->bt_coex_supported_feature); - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", - "ReInit/ReLink/IgnWlact/Page/NameReq", - coex_sta->cnt_ReInit, - coex_sta->cnt_setupLink, - coex_sta->cnt_IgnWlanAct, - coex_sta->cnt_Page, - coex_sta->cnt_RemoteNameReq - ); - CL_PRINTF(cli_buf); - - halbtc8703b1ant_read_score_board(btcoexist, &u16tmp[0]); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x", - "ScoreBoard[14:0] (from BT)", u16tmp[0]); - CL_PRINTF(cli_buf); - - if (coex_sta->num_of_profile > 0) { - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", - "AFH MAP", - coex_sta->bt_afh_map[0], - coex_sta->bt_afh_map[1], - coex_sta->bt_afh_map[2], - coex_sta->bt_afh_map[3], - coex_sta->bt_afh_map[4], - coex_sta->bt_afh_map[5], - coex_sta->bt_afh_map[6], - coex_sta->bt_afh_map[7], - coex_sta->bt_afh_map[8], - coex_sta->bt_afh_map[9] - ); - CL_PRINTF(cli_buf); - } - - for (i = 0; i < BT_INFO_SRC_8703B_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8703b_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms] (before Manual)============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "SM[LowPenaltyRA]", - coex_dm->cur_low_penalty_ra); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "On" : "Off"), - (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); - - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "WL/BT Coex Table Type", - coex_sta->coex_table_type); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x778/0x6cc/IgnWlanAct", - u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? true : false; - - if (lte_coex_on) { - u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa0); - u32tmp[1] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "LTE Coex Table W_L/B_L", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa8); - u32tmp[1] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xac); - u32tmp[2] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb0); - u32tmp[3] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "LTE Break Table W_L/B_L/L_W/L_B", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, - u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); - CL_PRINTF(cli_buf); - } - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s", - "LTE CoexOn/Path Ctrl Owner", - (int)((u32tmp[0] & BIT(7)) >> 7), - ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); - CL_PRINTF(cli_buf); - - if (lte_coex_on) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "LTE 3Wire/OPMode/UART/UARTMode", - (int)((u32tmp[0] & BIT(6)) >> 6), - (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), - (int)((u32tmp[0] & BIT(3)) >> 3), - (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); - CL_PRINTF(cli_buf); - } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", - "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", - ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), - ((u8tmp[0] & BIT(3)) ? "On" : "Off"), - coex_sta->gnt_error_cnt); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "GNT_WL/GNT_BT/LTE_Busy/UART_Busy", - (int)((u32tmp[0] & BIT(2)) >> 2), - (int)((u32tmp[0] & BIT(3)) >> 3), - (int)((u32tmp[0] & BIT(1)) >> 1), (int)(u32tmp[0] & BIT(0))); - CL_PRINTF(cli_buf); - - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x4c6[4]/0x40[5] (WL/BT PTA)", - (int)((u8tmp[0] & BIT(4)) >> 4), - (int)((u8tmp[1] & BIT(5)) >> 5)); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s", - "0x550(bcn ctrl)/0x522/4-RxAGC", - u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off"); - CL_PRINTF(cli_buf); - - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm); - CL_PRINTF(cli_buf); - -#if 1 - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); - CL_PRINTF(cli_buf); -#endif - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "WlHiPri/ Locking/ Locked/ Noisy", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), - (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No"), - coex_sta->wl_noisy_level); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", - "0x770(Hi-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx, - (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : "")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", - "0x774(Lo-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx, - (bt_link_info->slave_role ? "(Slave!!)" : ( - coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); - CL_PRINTF(cli_buf); - - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8703b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - coex_sta->under_lps = false; - - /* Write WL "Active" in Score-board for LPS off */ - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, false); - - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ONOFF, false); - - halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8703B_1ANT_PHASE_WLAN_OFF); - - halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); - - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ONOFF, true); - - halbtc8703b1ant_init_hw_config(btcoexist, false, false); - halbtc8703b1ant_init_coex_dm(btcoexist); - halbtc8703b1ant_query_bt_info(btcoexist); - - coex_sta->under_ips = false; - } -} - -void ex_halbtc8703b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - coex_sta->under_ips = false; - - if (coex_sta->force_lps_on == true) { /* LPS No-32K */ - /* Write WL "Active" in Score-board for PS-TDMA */ - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); - - } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ - /* Write WL "Non-Active" in Score-board for Native-PS */ - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, false); - } - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - - - /* Write WL "Active" in Score-board for LPS off */ - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); - } -} - -void ex_halbtc8703b1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - halbtc8703b1ant_query_bt_info(btcoexist); - - if (BTC_SCAN_START == type) { - - coex_sta->wifi_is_high_pri_task = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_SCAN, true); - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); - - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); - - /* Force antenna setup for no scan result issue */ - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8703B_1ANT_PHASE_2G_RUNTIME); - - halbtc8703b1ant_run_coexist_mechanism(btcoexist); - - } else { - - coex_sta->wifi_is_high_pri_task = false; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", - coex_sta->scan_ap_num); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_run_coexist_mechanism(btcoexist); - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START Notify() end\n"); - BTC_TRACE(trace_buf); - -} - -void ex_halbtc8703b1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - if (BTC_ASSOCIATE_START == type) { - coex_sta->wifi_is_high_pri_task = true; - - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_SCAN, true); - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); - - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); - - /* Force antenna setup for no scan result issue */ - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8703B_1ANT_PHASE_2G_RUNTIME); - /* psd_scan->ant_det_is_ant_det_available = true; */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - - halbtc8703b1ant_run_coexist_mechanism(btcoexist); - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_run_coexist_mechanism(btcoexist); - } - -} - -void ex_halbtc8703b1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_under_b_mode = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_MEDIA_CONNECT == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); - - /* Force antenna setup for no scan result issue */ - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8703B_1ANT_PHASE_2G_RUNTIME); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - /* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */ - /* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, false); - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - - coex_sta->cck_ever_lock = false; - } - - halbtc8703b1ant_update_wifi_channel_info(btcoexist, type); - -} - -void ex_halbtc8703b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean under_4way = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (under_4way) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ---- under_4way!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - } else if (BTC_PACKET_ARP == type) { - - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify -cnt = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", - type); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - } - - if (coex_sta->wifi_is_high_pri_task) { - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_SCAN, true); - halbtc8703b1ant_run_coexist_mechanism(btcoexist); - } -} - -void ex_halbtc8703b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean wifi_scan = false, wifi_link = false, wifi_roam = false, - wifi_busy = false; - - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8703B_1ANT_MAX) - rsp_source = BT_INFO_SRC_8703B_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; - coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; - coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; - - if (BT_INFO_SRC_8703B_1ANT_WIFI_FW != rsp_source) { - - /* if 0xff, it means BT is under WHCK test */ - coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true : - false); - - coex_sta->bt_create_connection = (( - coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true : - false); - - /* unit: %, value-100 to translate to unit: dBm */ - coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + - 10; - - coex_sta->c2h_bt_remote_name_req = (( - coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true : - false); - - coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & - 0x10) ? true : false); - - coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & - 0x9) ? true : false); - - coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? - true : false); - - coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & - BT_INFO_8703B_1ANT_B_INQ_PAGE) ? true : false); - - coex_sta->a2dp_bit_pool = ((( - coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? - coex_sta->bt_info_c2h[rsp_source][6] : 0); - - coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & - 0xf; - - coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; - - coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; - - coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; - - coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->c2h_bt_remote_name_req) - coex_sta->cnt_RemoteNameReq++; - - if (coex_sta->bt_info_ext & BIT(1)) - coex_sta->cnt_ReInit++; - - if (coex_sta->bt_info_ext & BIT(2)) { - coex_sta->cnt_setupLink++; - coex_sta->is_setupLink = true; - } else - coex_sta->is_setupLink = false; - - if (coex_sta->bt_info_ext & BIT(3)) - coex_sta->cnt_IgnWlanAct++; - - if (coex_sta->bt_create_connection) { - coex_sta->cnt_Page++; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); - - if ((wifi_link) || (wifi_roam) || (wifi_scan) || - (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { - - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_SCAN, true); - - } else { - - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_SCAN, false); - } - } else - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_SCAN, false); - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - - if ((!btcoexist->manual_control) && - (!btcoexist->stop_coex_dm)) { - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* Re-Init */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - if (wifi_connected) - halbtc8703b1ant_update_wifi_channel_info( - btcoexist, BTC_MEDIA_CONNECT); - else - halbtc8703b1ant_update_wifi_channel_info( - btcoexist, - BTC_MEDIA_DISCONNECT); - } - - - /* If Ignore_WLanAct && not SetUp_Link */ - if ((coex_sta->bt_info_ext & BIT(3)) && - (!(coex_sta->bt_info_ext & BIT(2))) && - (!(coex_sta->bt_info_ext & BIT(6)))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } else { - if (coex_sta->bt_info_ext & BIT(2)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ignore Wlan active because Re-link!!\n"); - BTC_TRACE(trace_buf); - } else if (coex_sta->bt_info_ext & BIT(6)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ignore Wlan active because Role-Switch!!\n"); - BTC_TRACE(trace_buf); - } - } - } - - } - if ((coex_sta->bt_info_ext & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); - BTC_TRACE(trace_buf); - coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist); - - if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) - coex_sta->bt_ble_scan_para[0] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x1); - if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) - coex_sta->bt_ble_scan_para[1] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x2); - if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) - coex_sta->bt_ble_scan_para[2] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x4); - } - - halbtc8703b1ant_update_bt_link_info(btcoexist); - - halbtc8703b1ant_run_coexist_mechanism(btcoexist); -} - - -void ex_halbtc8703b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ONOFF, true); - - /* halbtc8703b1ant_init_hw_config(btcoexist, false, false); */ - } else if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, false); - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ONOFF, false); - - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8703B_1ANT_PHASE_WLAN_OFF); - - btcoexist->stop_coex_dm = true; - - } -} - -void ex_halbtc8703b1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, false); - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ONOFF, false); - - halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8703B_1ANT_PHASE_WLAN_OFF); - - ex_halbtc8703b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, false); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8703b1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if ((BTC_WIFI_PNP_SLEEP == pnp_state) || - (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, false); - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ONOFF, false); - - if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { - - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8703B_1ANT_PHASE_2G_RUNTIME); - } else { - - halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8703B_1ANT_PHASE_WLAN_OFF); - } - - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ACTIVE, true); - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_ONOFF, true); - - btcoexist->stop_coex_dm = false; - } -} - -void ex_halbtc8703b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], *****************Coex DM Reset*****************\n"); - BTC_TRACE(trace_buf); - - halbtc8703b1ant_init_hw_config(btcoexist, false, false); - halbtc8703b1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8703b1ant_periodical(IN struct btc_coexist *btcoexist) -{ - u32 bt_patch_ver; - boolean wifi_busy = false; - static u8 cnt = 0; - boolean bt_relink_finish = false; - -#if (BT_AUTO_REPORT_ONLY_8703B_1ANT == 0) - halbtc8703b1ant_query_bt_info(btcoexist); -#endif - - halbtc8703b1ant_monitor_bt_ctr(btcoexist); - halbtc8703b1ant_monitor_wifi_ctr(btcoexist); - - halbtc8703b1ant_monitor_bt_enable_disable(btcoexist); - -# if 1 - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* halbtc8703b1ant_read_score_board(btcoexist, &bt_scoreboard_val); */ - - if (wifi_busy) { - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_UNDERTEST, true); - /* - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_WLBUSY, true); - - if (bt_scoreboard_val & BIT(6)) - halbtc8703b1ant_query_bt_info(btcoexist); */ - } else { - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_UNDERTEST, false); - /* - halbtc8703b1ant_post_state_to_bt(btcoexist, - BT_8703B_1ANT_SCOREBOARD_WLBUSY, - false); */ - } -#endif - - if (coex_sta->bt_relink_downcount != 0) { - coex_sta->bt_relink_downcount--; - - if (coex_sta->bt_relink_downcount == 0) - bt_relink_finish = true; - } - - /* for 4-way, DHCP, EAPOL packet */ - if (coex_sta->specific_pkt_period_cnt > 0) { - - coex_sta->specific_pkt_period_cnt--; - - if ((coex_sta->specific_pkt_period_cnt == 0) && - (coex_sta->wifi_is_high_pri_task)) - coex_sta->wifi_is_high_pri_task = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", - (coex_sta->wifi_is_high_pri_task ? "Yes" : - "No")); - BTC_TRACE(trace_buf); - - } - - if (!coex_sta->bt_disabled) { - if (coex_sta->bt_coex_supported_feature == 0) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, - &coex_sta->bt_coex_supported_feature); - - if ((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, - &coex_sta->bt_coex_supported_version); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; - - if (coex_sta->num_of_profile > 0) { - cnt++; - - if (cnt >= 3) { - btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, - &coex_sta->bt_afh_map[0]); - cnt = 0; - } - } - } - - if (halbtc8703b1ant_is_wifibt_status_changed(btcoexist)) - halbtc8703b1ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8703b1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - /* No Antenna Detection required because 8730b is only 1-Ant */ -} - -void ex_halbtc8703b1ant_antenna_isolation(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - - -} - -void ex_halbtc8703b1ant_psd_scan(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - - -} - -void ex_halbtc8703b1ant_display_ant_detection(IN struct btc_coexist *btcoexist) -{ - -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ - diff --git a/hal/btc/halbtc8703b1ant.h b/hal/btc/halbtc8703b1ant.h deleted file mode 100644 index a2a9711..0000000 --- a/hal/btc/halbtc8703b1ant.h +++ /dev/null @@ -1,418 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8703B_SUPPORT == 1) -/* ******************************************* - * The following is for 8703B 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8703B_1ANT 1 -#define BT_8703B_1ANT_ENABLE_GNTBT_TO_GPIO14 0 - -#define BT_INFO_8703B_1ANT_B_FTP BIT(7) -#define BT_INFO_8703B_1ANT_B_A2DP BIT(6) -#define BT_INFO_8703B_1ANT_B_HID BIT(5) -#define BT_INFO_8703B_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8703B_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8703B_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8703B_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8703B_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8703B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT 2 - -#define BT_8703B_1ANT_WIFI_NOISY_THRESH 50 /* max: 255 */ - -/* for Antenna detection */ -#define BT_8703B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 -#define BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 -#define BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 -#define BT_8703B_1ANT_ANTDET_PSDTHRES_1ANT 35 -#define BT_8703B_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8703B_1ANT_ANTDET_SWEEPPOINT_DELAY 40000 -#define BT_8703B_1ANT_ANTDET_ENABLE 0 -#define BT_8703B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0 - -#define BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 - -enum bt_8703b_1ant_signal_state { - BT_8703B_1ANT_SIG_STA_SET_TO_LOW = 0x0, - BT_8703B_1ANT_SIG_STA_SET_BY_HW = 0x0, - BT_8703B_1ANT_SIG_STA_SET_TO_HIGH = 0x1, - BT_8703B_1ANT_SIG_STA_MAX -}; - -enum bt_8703b_1ant_path_ctrl_owner { - BT_8703B_1ANT_PCO_BTSIDE = 0x0, - BT_8703B_1ANT_PCO_WLSIDE = 0x1, - BT_8703B_1ANT_PCO_MAX -}; - -enum bt_8703b_1ant_gnt_ctrl_type { - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, - BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW = 0x1, - BT_8703B_1ANT_GNT_TYPE_MAX -}; - -enum bt_8703b_1ant_gnt_ctrl_block { - BT_8703B_1ANT_GNT_BLOCK_RFC_BB = 0x0, - BT_8703B_1ANT_GNT_BLOCK_RFC = 0x1, - BT_8703B_1ANT_GNT_BLOCK_BB = 0x2, - BT_8703B_1ANT_GNT_BLOCK_MAX -}; - -enum bt_8703b_1ant_lte_coex_table_type { - BT_8703B_1ANT_CTT_WL_VS_LTE = 0x0, - BT_8703B_1ANT_CTT_BT_VS_LTE = 0x1, - BT_8703B_1ANT_CTT_MAX -}; - -enum bt_8703b_1ant_lte_break_table_type { - BT_8703B_1ANT_LBTT_WL_BREAK_LTE = 0x0, - BT_8703B_1ANT_LBTT_BT_BREAK_LTE = 0x1, - BT_8703B_1ANT_LBTT_LTE_BREAK_WL = 0x2, - BT_8703B_1ANT_LBTT_LTE_BREAK_BT = 0x3, - BT_8703B_1ANT_LBTT_MAX -}; - -enum bt_info_src_8703b_1ant { - BT_INFO_SRC_8703B_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8703B_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8703B_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8703B_1ANT_MAX -}; - -enum bt_8703b_1ant_bt_status { - BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8703B_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8703B_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8703B_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8703B_1ANT_BT_STATUS_MAX -}; - -enum bt_8703b_1ant_wifi_status { - BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8703B_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8703b_1ant_coex_algo { - BT_8703B_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8703B_1ANT_COEX_ALGO_SCO = 0x1, - BT_8703B_1ANT_COEX_ALGO_HID = 0x2, - BT_8703B_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8703B_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8703B_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8703B_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8703B_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8703B_1ANT_COEX_ALGO_MAX = 0xb, -}; - -enum bt_8703b_1ant_phase { - BT_8703B_1ANT_PHASE_COEX_INIT = 0x0, - BT_8703B_1ANT_PHASE_WLANONLY_INIT = 0x1, - BT_8703B_1ANT_PHASE_WLAN_OFF = 0x2, - BT_8703B_1ANT_PHASE_2G_RUNTIME = 0x3, - BT_8703B_1ANT_PHASE_5G_RUNTIME = 0x4, - BT_8703B_1ANT_PHASE_BTMPMODE = 0x5, - BT_8703B_1ANT_PHASE_ANTENNA_DET = 0x6, - BT_8703B_1ANT_PHASE_MAX -}; - -enum bt_8703b_1ant_Scoreboard { - BT_8703B_1ANT_SCOREBOARD_ACTIVE = BIT(0), - BT_8703B_1ANT_SCOREBOARD_ONOFF = BIT(1), - BT_8703B_1ANT_SCOREBOARD_SCAN = BIT(2), - BT_8703B_1ANT_SCOREBOARD_UNDERTEST = BIT(3), - BT_8703B_1ANT_SCOREBOARD_WLBUSY = BIT(6) -}; - - -struct coex_dm_8703b_1ant { - /* hw setting */ - u8 pre_ant_pos_type; - u8 cur_ant_pos_type; - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u8 error_condition; -}; - -struct coex_sta_8703b_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - boolean bt_hi_pri_link_exist; - u8 num_of_profile; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - boolean is_hiPri_rx_overhead; - s8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - u8 bt_info_c2h[BT_INFO_SRC_8703B_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8703B_1ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_remote_name_req; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - u8 bt_retry_cnt; - u8 bt_info_ext; - u8 bt_info_ext2; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; - - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; - u8 coex_table_type; - - boolean force_lps_on; - - boolean concurrent_rx_mode_on; - - u16 score_board; - u8 isolation_btween_wb; /* 0~ 50 */ - - u8 a2dp_bit_pool; - u8 cut_version; - boolean acl_busy; - boolean bt_create_connection; - - u32 bt_coex_supported_feature; - u32 bt_coex_supported_version; - - u8 bt_ble_scan_type; - u32 bt_ble_scan_para[3]; - - boolean run_time_state; - boolean freeze_coexrun_by_btinfo; - - boolean is_A2DP_3M; - boolean voice_over_HOGP; - u8 bt_info; - boolean is_autoslot; - u8 forbidden_slot; - u8 hid_busy_num; - u8 hid_pair_cnt; - - u32 cnt_RemoteNameReq; - u32 cnt_setupLink; - u32 cnt_ReInit; - u32 cnt_IgnWlanAct; - u32 cnt_Page; - - u16 bt_reg_vendor_ac; - u16 bt_reg_vendor_ae; - - boolean is_setupLink; - u8 wl_noisy_level; - u32 gnt_error_cnt; - - u8 bt_afh_map[10]; - u8 bt_relink_downcount; - boolean is_tdma_btautoslot; - boolean is_tdma_btautoslot_hang; -}; - -#define BT_8703B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ -#define BT_8703B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ -#define BT_8703B_1ANT_ANTDET_BUF_LEN 16 - -struct psdscan_sta_8703b_1ant { - - u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ - u32 ant_det_bt_tx_time; - u32 ant_det_pre_psdscan_peak_val; - boolean ant_det_is_ant_det_available; - u32 ant_det_psd_scan_peak_val; - boolean ant_det_is_btreply_available; - u32 ant_det_psd_scan_peak_freq; - - u8 ant_det_result; - u8 ant_det_peak_val[BT_8703B_1ANT_ANTDET_BUF_LEN]; - u8 ant_det_peak_freq[BT_8703B_1ANT_ANTDET_BUF_LEN]; - u32 ant_det_try_count; - u32 ant_det_fail_count; - u32 ant_det_inteval_count; - u32 ant_det_thres_offset; - - u32 real_cent_freq; - s32 real_offset; - u32 real_span; - - u32 psd_band_width; /* unit: Hz */ - u32 psd_point; /* 128/256/512/1024 */ - u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_start_point; - u32 psd_stop_point; - u32 psd_max_value_point; - u32 psd_max_value; - u32 psd_start_base; - u32 psd_avg_num; /* 1/8/16/32 */ - u32 psd_gen_count; - boolean is_psd_running; - boolean is_psd_show_max_only; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8703b1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8703b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8703b1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8703b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8703b1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8703b1ant_antenna_isolation(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); - -void ex_halbtc8703b1ant_psd_scan(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8703b1ant_display_ant_detection(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8703b1ant_power_on_setting(btcoexist) -#define ex_halbtc8703b1ant_pre_load_firmware(btcoexist) -#define ex_halbtc8703b1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8703b1ant_init_coex_dm(btcoexist) -#define ex_halbtc8703b1ant_ips_notify(btcoexist, type) -#define ex_halbtc8703b1ant_lps_notify(btcoexist, type) -#define ex_halbtc8703b1ant_scan_notify(btcoexist, type) -#define ex_halbtc8703b1ant_connect_notify(btcoexist, type) -#define ex_halbtc8703b1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8703b1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8703b1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8703b1ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8703b1ant_halt_notify(btcoexist) -#define ex_halbtc8703b1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8703b1ant_coex_dm_reset(btcoexist) -#define ex_halbtc8703b1ant_periodical(btcoexist) -#define ex_halbtc8703b1ant_display_coex_info(btcoexist) -#define ex_halbtc8703b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8703b1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8703b1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8703b1ant_display_ant_detection(btcoexist) - -#endif - - -#endif - diff --git a/hal/btc/halbtc8723b1ant.c b/hal/btc/halbtc8723b1ant.c deleted file mode 100644 index b5392fb..0000000 --- a/hal/btc/halbtc8723b1ant.c +++ /dev/null @@ -1,5127 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for RTL8723B Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8723B_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8723b_1ant glcoex_dm_8723b_1ant; -static struct coex_dm_8723b_1ant *coex_dm = &glcoex_dm_8723b_1ant; -static struct coex_sta_8723b_1ant glcoex_sta_8723b_1ant; -static struct coex_sta_8723b_1ant *coex_sta = &glcoex_sta_8723b_1ant; -static struct psdscan_sta_8723b_1ant gl_psd_scan_8723b_1ant; -static struct psdscan_sta_8723b_1ant *psd_scan = &gl_psd_scan_8723b_1ant; - - -const char *const glbt_info_src_8723b_1ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8723b_1ant = 20161007; -u32 glcoex_ver_8723b_1ant = 0x69; -u32 glcoex_ver_btdesired_8723b_1ant = 0x69; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8723b1ant_ - * ************************************************************ */ - -void halbtc8723b1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8723b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8723b1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8723b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8723b1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8723b1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8723b1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8723b1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8723b1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8723b1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8723b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8723b1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8723b1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -void halbtc8723b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u32 num_of_bt_counter_chk = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ - /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if ((coex_sta->high_priority_tx + coex_sta->high_priority_rx < 50) && - (bt_link_info->hid_exist == true)) - bt_link_info->hid_exist = false; - - if ((coex_sta->low_priority_tx > 1050) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - if ((coex_sta->low_priority_rx >= 950) && (!coex_sta->under_ips) - && (coex_sta->low_priority_rx >= - coex_sta->low_priority_tx) && - (!coex_sta->c2h_bt_inquiry_page)) - bt_link_info->slave_role = true; - else - bt_link_info->slave_role = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", - reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - /* This part is for wifi FW and driver to update BT's status as disabled. */ - /* The flow is as the following */ - /* 1. disable BT */ - /* 2. if all BT Tx/Rx counter=0, after 6 sec we query bt info */ - /* 3. Because BT will not rsp from mailbox, so wifi fw will know BT is disabled */ - /* 4. FW will rsp c2h for BT that driver will know BT is disabled. */ - if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) && - (reg_lp_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8723b1ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; - } - } - -} - - -void halbtc8723b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false; - static u8 cck_lock_counter = 0; - u32 total_cnt; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - -#if 1 - - coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_VHT); - -#endif - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + - coex_sta->crc_ok_11n_vht; - - if ((coex_dm->bt_status == BT_8723B_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == - BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == - BT_8723B_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 3) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = true; - - coex_sta->pre_ccklock = coex_sta->cck_lock; - - -} - -boolean halbtc8723b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - - - } - - return false; -} - -void halbtc8723b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false, bt_change = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - } else { - bt_disable_cnt++; - if (bt_disable_cnt >= 10) - bt_disabled = true; - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - bt_change = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - - btcoexist->btc_set(btcoexist, - BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE, - &bt_change); - - coex_sta->bt_disabled = bt_disabled; - } else { - btcoexist->btc_set(btcoexist, - BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE, - &bt_change); - } -} - -void halbtc8723b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->bt_hi_pri_link_exist = coex_sta->bt_hi_pri_link_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -void halbtc8723b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8723b1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8723b1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8723b1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8723b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8723b1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8723b1ant_sw_mechanism(IN struct btc_coexist *btcoexist, - IN boolean low_penalty_ra) -{ - halbtc8723b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8723b1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - - - -void halbtc8723b1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8723b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8723b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - -#if BT_8723B_1ANT_ANTDET_ENABLE -#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE - if (board_info->btdm_ant_num_by_ant_det == 2) { - if (type == 3) - type = 14; - else if (type == 4) - type = 13; - else if (type == 5) - type = 8; - } -#endif -#endif - - coex_sta->coex_table_type = type; - - switch (type) { - case 0: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, 0xffffff, 0x3); - break; - case 1: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 2: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 3: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 4: - if ((coex_sta->cck_ever_lock) && - (coex_sta->scan_ap_num <= 5)) - halbtc8723b1ant_coex_table(btcoexist, - force_exec, 0x55555555, 0xaaaa5a5a, - 0xffffff, 0x3); - else - halbtc8723b1ant_coex_table(btcoexist, - force_exec, 0x55555555, 0x5a5a5a5a, - 0xffffff, 0x3); - break; - case 5: - if ((coex_sta->cck_ever_lock) && - (coex_sta->scan_ap_num <= 5)) - halbtc8723b1ant_coex_table(btcoexist, - force_exec, 0x5a5a5a5a, 0x5aaa5a5a, - 0xffffff, 0x3); - else - halbtc8723b1ant_coex_table(btcoexist, - force_exec, 0x5a5a5a5a, 0x5aaa5a5a, - 0xffffff, 0x3); - break; - case 6: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 7: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 8: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 9: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 10: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 11: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 12: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 13: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 14: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); - break; - case 15: - halbtc8723b1ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8723b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) - h2c_parameter[0] |= BIT(0); /* function enable */ - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8723b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8723b1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8723b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8723b1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8723b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8723b1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg, - IN boolean wifi_off) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u32 fw_ver = 0, u32tmp = 0, cnt_bt_cal_chk = 0; - boolean pg_ext_switch = false; - boolean use_ext_switch = false; - boolean is_in_mp_mode = false; - u8 h2c_parameter[2] = {0}, u8tmp = 0; - u32 u32tmp_1[4]; - boolean is_fw_ready; - - coex_dm->cur_ant_pos_type = ant_pos_type; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_EXT_SWITCH, &pg_ext_switch); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, - &fw_ver); /* [31:16]=fw ver, [15:0]=fw sub ver */ - - if ((fw_ver > 0 && fw_ver < 0xc0000) || pg_ext_switch) - use_ext_switch = true; - -#if BT_8723B_1ANT_ANTDET_ENABLE -#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE - if (ant_pos_type == BTC_ANT_PATH_PTA) { - if ((board_info->btdm_ant_det_finish) && - (board_info->btdm_ant_num_by_ant_det == 2)) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = BTC_ANT_PATH_WIFI; - else - ant_pos_type = BTC_ANT_PATH_BT; - } - } -#endif -#endif - - if (init_hwcfg) { - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x780); /* WiFi TRx Mask on */ - /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */ - /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); */ /*BT TRx Mask on */ - - if (fw_ver >= 0x180000) { - /* Use H2C to set GNT_BT to HIGH */ - h2c_parameter[0] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, - h2c_parameter); - - cnt_bt_cal_chk = 0; - while (1) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready); - if (is_fw_ready == false) { - BTC_SPRINTF(trace_buf , BT_TMP_BUF_SIZE, - ("halbtc8723b1ant_set_ant_path(): we don't need to wait for H2C command completion because of Fw download fail!!!\n")); - BTC_TRACE(trace_buf); - break; - } - - if (btcoexist->btc_read_1byte(btcoexist, - 0x765) == 0x18) - break; - - cnt_bt_cal_chk++; - if (cnt_bt_cal_chk > 20) - break; - } - } else { - /* set grant_bt to high */ - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); - } - /* set wlan_act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x0); /* BT select s0/s1 is controlled by BT */ - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x39, 0x8, 0x1); - btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x944, 0x3, 0x3); - btcoexist->btc_write_1byte(btcoexist, 0x930, 0x77); - } else if (wifi_off) { - if (fw_ver >= 0x180000) { - /* Use H2C to set GNT_BT to HIGH */ - h2c_parameter[0] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, - h2c_parameter); - - cnt_bt_cal_chk = 0; - while (1) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready); - if (is_fw_ready == false) { - BTC_SPRINTF(trace_buf , BT_TMP_BUF_SIZE, - ("halbtc8723b1ant_set_ant_path(): we don't need to wait for H2C command completion because of Fw download fail!!!\n")); - BTC_TRACE(trace_buf); - break; - } - - if (btcoexist->btc_read_1byte(btcoexist, - 0x765) == 0x18) - break; - - cnt_bt_cal_chk++; - if (cnt_bt_cal_chk > 20) - break; - } - } else { - /* set grant_bt to high */ - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); - } - /* set wlan_act to always low */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE, - &is_in_mp_mode); - if (!is_in_mp_mode) - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, - 0x20, 0x0); /* BT select s0/s1 is controlled by BT */ - else - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, - 0x20, 0x1); /* BT select s0/s1 is controlled by WiFi */ - - /* 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL BT Vendor 0xac=0xf002 */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp &= ~BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } else { - /* Use H2C to set GNT_BT to LOW */ - if (fw_ver >= 0x180000) { - if (btcoexist->btc_read_1byte(btcoexist, 0x765) != 0) { - h2c_parameter[0] = 0; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, - h2c_parameter); - - cnt_bt_cal_chk = 0; - while (1) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready); - if (is_fw_ready == false) { - BTC_SPRINTF(trace_buf , - BT_TMP_BUF_SIZE, - ("halbtc8723b1ant_set_ant_path(): we don't need to wait for H2C command completion because of Fw download fail!!!\n")); - BTC_TRACE(trace_buf); - break; - } - - if (btcoexist->btc_read_1byte(btcoexist, - 0x765) == 0x0) - break; - - cnt_bt_cal_chk++; - if (cnt_bt_cal_chk > 20) - break; - } - } - } else { - /* BT calibration check */ - while (cnt_bt_cal_chk <= 20) { - u8tmp = btcoexist->btc_read_1byte(btcoexist, - 0x49d); - cnt_bt_cal_chk++; - if (u8tmp & BIT(0)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - delay_ms(50); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - break; - } - } - - /* set grant_bt to PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x0); - } - - if (btcoexist->btc_read_1byte(btcoexist, 0x76e) != 0xc) { - /* set wlan_act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - } - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x1); /* BT select s0/s1 is controlled by WiFi */ - } - - if (use_ext_switch) { - if (init_hwcfg) { - /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp |= BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - - - u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, - 0x948); - if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte(btcoexist, 0x948, - u32tmp_1[0]); - else - btcoexist->btc_write_4byte(btcoexist, 0x948, - 0x0); - - - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - /* tell firmware "no antenna inverse" */ - h2c_parameter[0] = 0; - h2c_parameter[1] = 1; /* ext switch type */ - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } else { - /* tell firmware "antenna inverse" */ - h2c_parameter[0] = 1; - h2c_parameter[1] = 1; /* ext switch type */ - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } - } - - if (force_exec || - (coex_dm->cur_ant_pos_type != - coex_dm->pre_ant_pos_type)) { - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x92c, 0x3, - 0x1); - else - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x92c, 0x3, - 0x2); - break; - case BTC_ANT_PATH_BT: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x92c, 0x3, - 0x2); - else - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x92c, 0x3, - 0x1); - break; - default: - case BTC_ANT_PATH_PTA: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x92c, 0x3, - 0x1); - else - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x92c, 0x3, - 0x2); - break; - } - } - } else { - if (init_hwcfg) { - /* 0x4c[23]=1, 0x4c[24]=0 Antenna control by 0x64 */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp |= BIT(23); - u32tmp &= ~BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - - /* Fix Ext switch Main->S1, Aux->S0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, - 0x0); - - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - - /* tell firmware "no antenna inverse" */ - h2c_parameter[0] = 0; - h2c_parameter[1] = - 0; /* internal switch type */ - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } else { - - /* tell firmware "antenna inverse" */ - h2c_parameter[0] = 1; - h2c_parameter[1] = - 0; /* internal switch type */ - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } - } - - if (force_exec || - (coex_dm->cur_ant_pos_type != - coex_dm->pre_ant_pos_type)) { - /* internal switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - u32tmp_1[0] = btcoexist->btc_read_4byte( - btcoexist, 0x948); - if ((u32tmp_1[0] == 0x40) || - (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte( - btcoexist, 0x948, - u32tmp_1[0]); - else - btcoexist->btc_write_4byte( - btcoexist, 0x948, 0x0); - } else { - u32tmp_1[0] = btcoexist->btc_read_4byte( - btcoexist, 0x948); - if ((u32tmp_1[0] == 0x40) || - (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte( - btcoexist, 0x948, - u32tmp_1[0]); - else - btcoexist->btc_write_4byte( - btcoexist, 0x948, - 0x280); - } - break; - case BTC_ANT_PATH_BT: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - u32tmp_1[0] = btcoexist->btc_read_4byte( - btcoexist, 0x948); - if ((u32tmp_1[0] == 0x40) || - (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte( - btcoexist, 0x948, - u32tmp_1[0]); - else - btcoexist->btc_write_4byte( - btcoexist, 0x948, - 0x280); - } else { - u32tmp_1[0] = btcoexist->btc_read_4byte( - btcoexist, 0x948); - if ((u32tmp_1[0] == 0x40) || - (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte( - btcoexist, 0x948, - u32tmp_1[0]); - else - btcoexist->btc_write_4byte( - btcoexist, 0x948, 0x0); - } - break; - default: - case BTC_ANT_PATH_PTA: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_4byte( - btcoexist, 0x948, - 0x200); - else - btcoexist->btc_write_4byte( - btcoexist, 0x948, 0x80); - break; - } - } - } - - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; -} - -void halbtc8723b1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - /* halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - /* halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - - -void halbtc8723b1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8723b1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8723b1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8723b1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - - -void halbtc8723b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - - halbtc8723b1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - } - } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - halbtc8723b1ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - - } else { - halbtc8723b1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - } - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - - -void halbtc8723b1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - u8 rssi_adjust_val = 0; - u8 ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51, - ps_tdma_byte3_val = 0x10; - s8 wifi_duration_adjust = 0x0; - static boolean pre_wifi_busy = false; - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - -#if BT_8723B_1ANT_ANTDET_ENABLE -#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE - if (board_info->btdm_ant_num_by_ant_det == 2) { - if (turn_on) - type = type + - 100; /* for WiFi RSSI low or BT RSSI low */ - else - type = 1; /* always translate to TDMA(off,1) for TDMA-off case */ - } - -#endif -#endif - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (wifi_busy != pre_wifi_busy) { - force_exec = true; - pre_wifi_busy = wifi_busy; - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_sta->scan_ap_num <= 5) { - wifi_duration_adjust = 5; - - if (coex_sta->a2dp_bit_pool >= 35) - wifi_duration_adjust = -10; - else if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - } else if (coex_sta->scan_ap_num >= 40) { - wifi_duration_adjust = -15; - - if (coex_sta->a2dp_bit_pool < 35) - wifi_duration_adjust = -5; - else if (coex_sta->a2dp_bit_pool < 45) - wifi_duration_adjust = -10; - } else if (coex_sta->scan_ap_num >= 20) { - wifi_duration_adjust = -10; - - if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - } else { - wifi_duration_adjust = 0; - - if (coex_sta->a2dp_bit_pool >= 35) - wifi_duration_adjust = -10; - else if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - } - - if ((type == 1) || (type == 2) || (type == 9) || (type == 11) || - (type == 101) - || (type == 102) || (type == 109) || (type == 101)) { - if (!coex_sta->force_lps_on) { /* Native power save TDMA, only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */ - ps_tdma_byte0_val = 0x61; /* no null-pkt */ - ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */ - ps_tdma_byte4_val = - 0x10; /* 0x778 = d/1 toggle, no dynamic slot */ - } else { - ps_tdma_byte0_val = 0x51; /* null-pkt */ - ps_tdma_byte3_val = 0x10; /* tx-pause at BT-slot */ - ps_tdma_byte4_val = - 0x50; /* 0x778 = d/1 toggle, dynamic slot */ - } - } else if ((type == 3) || (type == 13) || (type == 14) || - (type == 103) || (type == 113) || (type == 114)) { - ps_tdma_byte0_val = 0x51; /* null-pkt */ - ps_tdma_byte3_val = 0x10; /* tx-pause at BT-slot */ - ps_tdma_byte4_val = - 0x10; /* 0x778 = d/1 toggle, no dynamic slot */ -#if 0 - if (!wifi_busy) - ps_tdma_byte4_val = ps_tdma_byte4_val | - 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ -#endif - } else { /* native power save case */ - ps_tdma_byte0_val = 0x61; /* no null-pkt */ - ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */ - ps_tdma_byte4_val = - 0x11; /* 0x778 = d/1 toggle, no dynamic slot */ - /* psTdmaByte4Va is not defne for 0x778 = d/1, 1/1 case */ - } - - /* if (bt_link_info->slave_role == true) */ - if ((bt_link_info->slave_role == true) && (bt_link_info->a2dp_exist)) - ps_tdma_byte4_val = ps_tdma_byte4_val | - 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - - if (type > 100) { - ps_tdma_byte0_val = ps_tdma_byte0_val | - 0x82; /* set antenna control by SW */ - ps_tdma_byte3_val = ps_tdma_byte3_val | - 0x60; /* set antenna no toggle, control by antenna diversity */ - } - - - if (turn_on) { - switch (type) { - default: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1a, 0x1a, 0x0, ps_tdma_byte4_val); - break; - case 1: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3a + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 2: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x2d + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 3: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x30, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 4: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x14, 0x0); - break; - case 5: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x1f, 0x3, - ps_tdma_byte3_val, 0x11); - break; - case 6: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x20, 0x3, - ps_tdma_byte3_val, 0x11); - break; - case 7: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13, - 0xc, 0x5, 0x0, 0x0); - break; - case 8: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 9: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 10: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0xa, 0x0, 0x40); - break; - case 11: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 12: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, - 0x0a, 0x0a, 0x0, 0x50); - break; - case 13: - if (coex_sta->scan_ap_num <= 3) - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x40, 0x3, - ps_tdma_byte3_val, - ps_tdma_byte4_val); - else - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, - ps_tdma_byte4_val); - break; - case 14: - if (coex_sta->scan_ap_num <= 3) - halbtc8723b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x30, 0x3, 0x10, 0x50); - else - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, - ps_tdma_byte4_val); - break; - case 15: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0x3, 0x8, 0x0); - break; - case 16: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x10, 0x0); - break; - case 18: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 20: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3f, 0x03, - ps_tdma_byte3_val, 0x10); - break; - case 21: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x11); - break; - case 22: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x25, 0x03, - ps_tdma_byte3_val, 0x10); - break; - case 23: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x18); - break; - case 24: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x3, 0x31, 0x18); - break; - case 25: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - break; - case 26: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - break; - case 27: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x98); - break; - case 28: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x69, - 0x25, 0x3, 0x31, 0x0); - break; - case 29: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xab, - 0x1a, 0x1a, 0x1, 0x10); - break; - case 30: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, 0x10); - break; - case 31: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1a, 0x1a, 0, 0x58); - break; - case 32: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x35, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 33: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x35, 0x3, - ps_tdma_byte3_val, 0x10); - break; - case 34: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x53, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 35: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x63, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 36: - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x12, 0x3, 0x14, 0x50); - break; - case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */ - /* here softap mode screen off will cost 70-80mA for phone */ - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x23, - 0x18, 0x00, 0x10, 0x24); - break; - - /* for 1-Ant translate to 2-Ant */ - case 101: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3a + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 102: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x2d + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 103: - /* halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, 0x1d, 0x1d, 0x0, ps_tdma_byte4_val); */ - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3a, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 105: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x15, 0x3, - ps_tdma_byte3_val, 0x11); - break; - case 106: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x20, 0x3, - ps_tdma_byte3_val, 0x11); - break; - case 109: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 111: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 113: - /* halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, 0x12, 0x12, 0x0, ps_tdma_byte4_val); */ - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 114: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 120: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3f, 0x03, - ps_tdma_byte3_val, 0x10); - break; - case 122: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x25, 0x03, - ps_tdma_byte3_val, 0x10); - break; - case 132: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x25, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 133: - halbtc8723b1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x25, 0x03, - ps_tdma_byte3_val, 0x11); - break; - - } - } else { - - /* disable PS tdma */ - switch (type) { - case 8: /* PTA Control */ - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - break; - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - break; - case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */ - halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - } - } - rssi_adjust_val = 0; - btcoexist->btc_set(btcoexist, - BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", - btcoexist->btc_read_4byte(btcoexist, 0x948), - btcoexist->btc_read_1byte(btcoexist, 0x765), - btcoexist->btc_read_1byte(btcoexist, 0x67)); - BTC_TRACE(trace_buf); - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8723b1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0, bt_info_ext; - boolean wifi_busy = false; - - if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status) - wifi_busy = true; - else - wifi_busy = false; - - if ((BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == - wifi_status) || - (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) || - (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT == - wifi_status)) { - if (coex_dm->cur_ps_tdma != 1 && - coex_dm->cur_ps_tdma != 2 && - coex_dm->cur_ps_tdma != 3 && - coex_dm->cur_ps_tdma != 9) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - coex_dm->ps_tdma_du_adj_type = 9; - - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } - return; - } - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* acquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - bt_info_ext = coex_sta->bt_info_ext; - - if ((coex_sta->low_priority_tx) > 1050 || - (coex_sta->low_priority_rx) > 1250) - retry_count++; - - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ - if (wait_count <= 2) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ - if (wait_count == 1) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (result == -1) { - /* if( (BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 1) ||(coex_dm->cur_ps_tdma == 2)) ) - { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } - else */ if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } - } else if (result == 1) { - /* if( (BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 1) ||(coex_dm->cur_ps_tdma == 2)) ) - { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } - else */ if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = 1; - } - } else { /* no change */ - /* Bryant Modify - if(wifi_busy != pre_wifi_busy) - { - pre_wifi_busy = wifi_busy; - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma); - } - */ - - } - - if (coex_dm->cur_ps_tdma != 1 && - coex_dm->cur_ps_tdma != 2 && - coex_dm->cur_ps_tdma != 9 && - coex_dm->cur_ps_tdma != 11) { - /* recover to previous adjust type */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - } - } -} - - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8723b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) -{ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - - -void halbtc8723b1ant_action_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8723b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, ap_enable = false, wifi_busy = false, - bt_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - if (coex_sta->bt_abnormal_scan) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 33); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } else if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - /* SCO/HID/A2DP busy */ - - if (coex_sta->c2h_bt_remote_name_req) - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 33); - else - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if ((bt_link_info->pan_exist) || (wifi_busy)) { - - if (coex_sta->c2h_bt_remote_name_req) - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 33); - else - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - - } -} - -void halbtc8723b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* tdma and coex table */ - - if (bt_link_info->sco_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else { /* HID */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } -} - -void halbtc8723b1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, - false, false); -} - -void halbtc8723b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8723b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - if ((coex_sta->low_priority_rx >= 950) && (!coex_sta->under_ips)) - bt_link_info->slave_role = true; - else - bt_link_info->slave_role = false; - - if (bt_link_info->hid_only) { /* HID */ - halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, - wifi_status); - coex_dm->auto_tdma_adjust = false; - return; - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - halbtc8723b1ant_tdma_duration_adjust_for_acl(btcoexist, - wifi_status); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = true; - } - } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - coex_dm->auto_tdma_adjust = false; - - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && - bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - - if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - else - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 3); - - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - /* BT no-profile busy (0x9) */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } -} - -void halbtc8723b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - - /* tdma and coex table */ - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8723b1ant_action_wifi_not_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - /* tdma and coex table */ - if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* Bryant Add */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8723b1ant_action_wifi_not_connected_asso_auth( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2); - } -} - -void halbtc8723b1ant_action_wifi_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - /* tdma and coex table */ - if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* Bryant Add */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8723b1ant_action_wifi_connected_specific_packet( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* no specific packet process for both WiFi and BT very busy */ - if ((wifi_busy) && ((bt_link_info->pan_exist) || - (coex_sta->num_of_profile >= 2))) - return; - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else if (bt_link_info->a2dp_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8723b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - boolean scan = false, link = false, roam = false; - boolean under_4way = false, ap_enable = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (under_4way) { - halbtc8723b1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - if (scan) - halbtc8723b1ant_action_wifi_connected_scan(btcoexist); - else - halbtc8723b1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - - /* tdma and coex table */ - if (!wifi_busy) { - if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8723b1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else { - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8723b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - /* if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) */ - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - /* else - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); */ - } - } else { - if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8723b1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else { - /* halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8723b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - else - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); */ - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8723b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - halbtc8723b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - - } - } -} - -void halbtc8723b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false, wifi_busy = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - boolean miracast_plus_bt = false; - u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0, wifi_bw; - u8 iot_peer = BTC_IOT_PEER_UNKNOWN; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b1ant_action_bt_whck_test(btcoexist); - return; - } - - if ((BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - if (bt_link_info->bt_link_exist) { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, - 0, 1); - miracast_plus_bt = true; - } else { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, - 0, 0); - miracast_plus_bt = false; - } - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if (((bt_link_info->a2dp_exist) || (wifi_busy)) && - (coex_sta->c2h_bt_inquiry_page)) - halbtc8723b1ant_action_bt_inquiry(btcoexist); - else - halbtc8723b1ant_action_wifi_multi_port(btcoexist); - - return; - } - - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); - - /* if(BTC_IOT_PEER_CISCO != iot_peer) */ - if ((BTC_IOT_PEER_CISCO != iot_peer) && - (BTC_IOT_PEER_BROADCOM != iot_peer)) { - if (bt_link_info->sco_exist) /* if (bt_link_info->bt_hi_pri_link_exist) */ - /* halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, true, false, 0x5); */ - halbtc8723b1ant_limited_rx(btcoexist, - NORMAL_EXEC, true, false, 0x5); - else - halbtc8723b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, false, 0x5); - /* halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8); */ - } else { - if (bt_link_info->sco_exist) - halbtc8723b1ant_limited_rx(btcoexist, - NORMAL_EXEC, true, false, 0x5); - else if (bt_link_info->hid_exist) - halbtc8723b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x3); - else { - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8723b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x10); - else - halbtc8723b1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x8); - } - } - - halbtc8723b1ant_sw_mechanism(btcoexist, true); - - /* low pelnaty ra in pcr ra */ - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 35); - - } else { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x5); - - halbtc8723b1ant_sw_mechanism(btcoexist, false); - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8723b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723b1ant_action_hs(btcoexist); - return; - } - - - if (!wifi_connected) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is non connected-idle !!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - if (scan) - halbtc8723b1ant_action_wifi_not_connected_scan( - btcoexist); - else - halbtc8723b1ant_action_wifi_not_connected_asso_auth( - btcoexist); - } else - halbtc8723b1ant_action_wifi_not_connected(btcoexist); - } else /* wifi LPS/Busy */ - halbtc8723b1ant_action_wifi_connected(btcoexist); -} - -void halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - - /* sw all off */ - halbtc8723b1ant_sw_mechanism(btcoexist, false); - - /* halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ - /* halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */ - - coex_sta->pop_event_cnt = 0; -} - -void halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up, IN boolean wifi_only) -{ - u32 u32tmp = 0; /* , fw_ver; */ - u8 u8tmpa = 0, u8tmpb = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - psd_scan->ant_det_is_ant_det_available = false; - - - /* Give bt_coex_supported_version the default value */ - coex_sta->bt_coex_supported_version = 0; - - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - - /* 0x790[5:0]=0x5 */ - btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); - - /* Enable counter statistics */ - /* btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); */ /*0x76e[3] =1, WLAN_Act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); - - - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1); */ /*BT select s0/s1 is controlled by WiFi */ - - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - - /* Antenna config */ - if (wifi_only) - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, true, false); - else - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, true, false); - - /* PTA parameter */ - halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", - u32tmp, u8tmpa, u8tmpb); - BTC_TRACE(trace_buf); - -} - -/* Donot remove optimize off flag, otherwise antenna detection would trigger BT collapsed */ -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -void halbtc8723b1ant_mechanism_switch(IN struct btc_coexist *btcoexist, - IN boolean bSwitchTo2Antenna) -{ - - if (bSwitchTo2Antenna) { - - /* BT TRx mask off */ - btcoexist->btc_set_bt_trx_mask(btcoexist, 0); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT TRx Mask off for mechanism_switch\n"); - - BTC_TRACE(trace_buf); - - } else { - - /* BT TRx mask on */ - btcoexist->btc_set_bt_trx_mask(btcoexist, 1); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT TRx Mask on for mechanism_switch\n"); - - BTC_TRACE(trace_buf); - } - - -#if 0 - if (bSwitchTo2Antenna) { /* 1-Ant -> 2-Ant */ - /* un-lock TRx Mask setup for 8723b f-cut */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, 0x80, 0x1); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, 0x1, 0x1); - /* WiFi TRx Mask on */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - - /* BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 */ - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x2c, - 0x7c45); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x30, - 0x7c45); - - /* BT TRx Mask on */ - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x1); - - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, false); - } else { - /* WiFi TRx Mask on */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x780); - - /* lock TRx Mask setup for 8723b f-cut */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, 0x80, 0x0); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, 0x1, 0x0); - - /* BT TRx Mask on */ - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); - - /* BT TRx Mask ock 0x2c[0], 0x30[0] = 0 */ - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x2c, - 0x7c44); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x30, - 0x7c44); - - - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - } - -#endif -} - -u32 halbtc8723b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val) -{ - u8 j; - u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0; - u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200, - 174, 151, 132, 115, 100, 86, 74, 62, 51, 42, - 32, 23, 15, 7, 0 - }; - - if (val == 0) - return 0; - - tmp = val; - - while (1) { - if (tmp == 1) - break; - - tmp = (tmp >> 1); - shiftcount++; - } - - - val_integerd_b = shiftcount + 1; - - tmp2 = 1; - for (j = 1; j <= val_integerd_b; j++) - tmp2 = tmp2 * 2; - - tmp = (val * 100) / tmp2; - tindex = tmp / 5; - - if (tindex > 20) - tindex = 20; - - val_fractiond_b = table_fraction[tindex]; - - result = val_integerd_b * 100 - val_fractiond_b; - - return result; - - -} - -void halbtc8723b1ant_psd_show_antenna_detect_result(IN struct btc_coexist - *btcoexist) -{ - u8 *cli_buf = btcoexist->cli_buf; - struct btc_board_info *board_info = &btcoexist->board_info; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n============[Antenna Detection info] ============\n"); - CL_PRINTF(cli_buf); - - if (psd_scan->ant_det_result == 1) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)", - "Ant Det Result", "2-Antenna (Bad-Isolation)", - BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); - else if (psd_scan->ant_det_result == 2) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)", - "Ant Det Result", "2-Antenna (Good-Isolation)", - BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset, - BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)", - "Ant Det Result", "1-Antenna", - BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT, - BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset); - - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ", - "Antenna Detection Finish", - (board_info->btdm_ant_det_finish - ? "Yes" : "No")); - CL_PRINTF(cli_buf); - - switch (psd_scan->ant_det_result) { - case 0: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is not available)"); - break; - case 1: /* 2-Ant bad-isolation */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available)"); - break; - case 2: /* 2-Ant good-isolation */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available)"); - break; - case 3: /* 1-Ant */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available)"); - break; - case 4: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(Uncertainty result)"); - break; - case 5: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(Pre-Scan fai)"); - break; - case 6: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(WiFi is Scanning)"); - break; - case 7: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is not idle)"); - break; - case 8: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(Abort by WiFi Scanning)"); - break; - case 9: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(Antenna Init is not ready)"); - break; - case 10: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is Inquiry or page)"); - break; - case 11: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is Disabled)"); - break; - } - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Ant Detect Total Count", psd_scan->ant_det_try_count); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Ant Detect Fail Count", psd_scan->ant_det_fail_count); - CL_PRINTF(cli_buf); - - if ((!board_info->btdm_ant_det_finish) && - (psd_scan->ant_det_result != 5)) - return; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Response", - (psd_scan->ant_det_result ? "ok" : "fail")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ms", "BT Tx Time", - psd_scan->ant_det_bt_tx_time); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "BT Tx Ch", - psd_scan->ant_det_bt_le_channel); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", - "WiFi PSD Cent-Ch/Offset/Span", - psd_scan->real_cent_freq, psd_scan->real_offset, - psd_scan->real_span); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB", - "PSD Pre-Scan Peak Value", - psd_scan->ant_det_pre_psdscan_peak_val / 100); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (<= %d)", - "PSD Pre-Scan result", - (psd_scan->ant_det_result != 5 ? "ok" : "fail"), - BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset); - CL_PRINTF(cli_buf); - - if (psd_scan->ant_det_result == 5) - return; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s dB", - "PSD Scan Peak Value", psd_scan->ant_det_peak_val); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s MHz", - "PSD Scan Peak Freq", psd_scan->ant_det_peak_freq); - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package", - (board_info->tfbga_package) ? "Yes" : "No"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "PSD Threshold Offset", psd_scan->ant_det_thres_offset); - CL_PRINTF(cli_buf); - -} - -void halbtc8723b1ant_psd_showdata(IN struct btc_coexist *btcoexist) -{ - u8 *cli_buf = btcoexist->cli_buf; - u32 delta_freq_per_point; - u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n\n============[PSD info] (%d)============\n", - psd_scan->psd_gen_count); - CL_PRINTF(cli_buf); - - if (psd_scan->psd_gen_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n"); - CL_PRINTF(cli_buf); - return; - } - - if (psd_scan->psd_point == 0) - delta_freq_per_point = 0; - else - delta_freq_per_point = psd_scan->psd_band_width / - psd_scan->psd_point; - - /* if (psd_scan->is_psd_show_max_only) */ - if (0) { - psd_rep1 = psd_scan->psd_max_value / 100; - psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100; - - freq = ((psd_scan->real_cent_freq - 20) * 1000000 + - psd_scan->psd_max_value_point * delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq = %d.0%d MHz", - freq1, freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq = %d.%d MHz", - freq1, freq2); - - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - ", Value = %d.0%d dB, (%d)\n", - psd_rep1, psd_rep2, psd_scan->psd_max_value); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - ", Value = %d.%d dB, (%d)\n", - psd_rep1, psd_rep2, psd_scan->psd_max_value); - - CL_PRINTF(cli_buf); - } else { - m = psd_scan->psd_start_point; - n = psd_scan->psd_start_point; - i = 1; - j = 1; - - while (1) { - do { - freq = ((psd_scan->real_cent_freq - 20) * - 1000000 + m * - delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (i == 1) { - if (freq2 == 0) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Freq%6d.000", - freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Freq%6d.0%2d", - freq1, - freq2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Freq%6d.%3d", - freq1, - freq2); - } else if ((i % 8 == 0) || - (m == psd_scan->psd_stop_point)) { - if (freq2 == 0) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.000\n", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.0%2d\n", freq1, - freq2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.%3d\n", freq1, - freq2); - } else { - if (freq2 == 0) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.000", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.0%2d", freq1, - freq2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.%3d", freq1, - freq2); - } - - i++; - m++; - CL_PRINTF(cli_buf); - - } while ((i <= 8) && (m <= psd_scan->psd_stop_point)); - - - do { - psd_rep1 = psd_scan->psd_report_max_hold[n] / - 100; - psd_rep2 = psd_scan->psd_report_max_hold[n] - - psd_rep1 * - 100; - - if (j == 1) { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Val %7d.0%d", - psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Val %7d.%d", - psd_rep1, - psd_rep2); - } else if ((j % 8 == 0) || - (n == psd_scan->psd_stop_point)) { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%7d.0%d\n", psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%7d.%d\n", psd_rep1, - psd_rep2); - } else { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%7d.0%d", psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%7d.%d", psd_rep1, - psd_rep2); - } - - j++; - n++; - CL_PRINTF(cli_buf); - - } while ((j <= 8) && (n <= psd_scan->psd_stop_point)); - - if ((m > psd_scan->psd_stop_point) || - (n > psd_scan->psd_stop_point)) - break; - - i = 1; - j = 1; - } - } - - -} - -void halbtc8723b1ant_psd_max_holddata(IN struct btc_coexist *btcoexist, - IN u32 gen_count) -{ - u32 i = 0, i_max = 0, val_max = 0; - - if (gen_count == 1) { - memcpy(psd_scan->psd_report_max_hold, - psd_scan->psd_report, - BT_8723B_1ANT_ANTDET_PSD_POINTS * sizeof(u32)); - - psd_scan->psd_max_value_point = 0; - psd_scan->psd_max_value = 0; - - } else { - for (i = psd_scan->psd_start_point; - i <= psd_scan->psd_stop_point; i++) { - if (psd_scan->psd_report[i] > - psd_scan->psd_report_max_hold[i]) - psd_scan->psd_report_max_hold[i] = - psd_scan->psd_report[i]; - - /* search Max Value */ - if (i == psd_scan->psd_start_point) { - i_max = i; - val_max = psd_scan->psd_report_max_hold[i]; - } else { - if (psd_scan->psd_report_max_hold[i] > - val_max) { - i_max = i; - val_max = psd_scan->psd_report_max_hold[i]; - } - } - - } - - psd_scan->psd_max_value_point = i_max; - psd_scan->psd_max_value = val_max; - - } - - -} - -u32 halbtc8723b1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) -{ - /* reg 0x808[9:0]: FFT data x */ - /* reg 0x808[22]: 0-->1 to get 1 FFT data y */ - /* reg 0x8b4[15:0]: FFT data y report */ - - u32 val = 0, psd_report = 0; - int k = 0; - - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - - val &= 0xffbffc00; - val |= point; - - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - val |= 0x00400000; - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - while (1) { - if (k++ > BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY) - break; - } - - val = btcoexist->btc_read_4byte(btcoexist, 0x8b4); - - psd_report = val & 0x0000ffff; - - return psd_report; -} - - -boolean halbtc8723b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points, - IN u32 avgnum, IN u32 loopcnt) -{ - u32 i, val, n, k = 0, j, point_index = 0; - u32 points1 = 0, psd_report = 0; - u32 start_p = 0, stop_p = 0, delta_freq_per_point = 156250; - u32 psd_center_freq = 20 * 10 ^ 6; - boolean outloop = false, scan , roam, is_sweep_ok = true; - u8 flag = 0; - u32 tmp; - u32 wifi_original_channel = 1; - - psd_scan->is_psd_running = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n"); - BTC_TRACE(trace_buf); - - do { - switch (flag) { - case 0: /* Get PSD parameters */ - default: - - psd_scan->psd_band_width = 40 * 1000000; - psd_scan->psd_point = points; - psd_scan->psd_start_base = points / 2; - psd_scan->psd_avg_num = avgnum; - psd_scan->real_cent_freq = cent_freq; - psd_scan->real_offset = offset; - psd_scan->real_span = span; - - - points1 = psd_scan->psd_point; - delta_freq_per_point = psd_scan->psd_band_width / - psd_scan->psd_point; - - /* PSD point setup */ - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - val &= 0xffff0fff; - - switch (psd_scan->psd_point) { - case 128: - val |= 0x0; - break; - case 256: - default: - val |= 0x00004000; - break; - case 512: - val |= 0x00008000; - break; - case 1024: - val |= 0x0000c000; - break; - } - - switch (psd_scan->psd_avg_num) { - case 1: - val |= 0x0; - break; - case 8: - val |= 0x00001000; - break; - case 16: - val |= 0x00002000; - break; - case 32: - default: - val |= 0x00003000; - break; - } - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - flag = 1; - break; - case 1: /* calculate the PSD point index from freq/offset/span */ - psd_center_freq = psd_scan->psd_band_width / 2 + - offset * (1000000); - - start_p = psd_scan->psd_start_base + (psd_center_freq - - span * (1000000) / 2) / delta_freq_per_point; - psd_scan->psd_start_point = start_p - - psd_scan->psd_start_base; - - stop_p = psd_scan->psd_start_base + (psd_center_freq + - span * (1000000) / 2) / delta_freq_per_point; - psd_scan->psd_stop_point = stop_p - - psd_scan->psd_start_base - 1; - - flag = 2; - break; - case 2: /* set RF channel/BW/Mode */ - - /* set 3-wire off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x88c); - val |= 0x00300000; - btcoexist->btc_write_4byte(btcoexist, 0x88c, val); - - /* CCK off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x800); - val &= 0xfeffffff; - btcoexist->btc_write_4byte(btcoexist, 0x800, val); - - /* store WiFi original channel */ - wifi_original_channel = btcoexist->btc_get_rf_reg( - btcoexist, BTC_RF_A, 0x18, 0x3ff); - - /* Set RF channel */ - if (cent_freq == 2484) - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, - 0x18, 0x3ff, 0xe); - else - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, - 0x18, 0x3ff, (cent_freq - 2412) / 5 + - 1); /* WiFi TRx Mask on */ - - - /* Set RF Rx filter corner */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, 0x3e4); - - /* Set TRx mask off */ - /* un-lock TRx Mask setup */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, - 0x80, 0x1); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, - 0x1, 0x1); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - - /* Set RF mode = Rx, RF Gain = 0x8a0 */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0, - 0xfffff, 0x308a0); - - while (1) { - if (k++ > BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY) - break; - } - flag = 3; - break; - case 3: - psd_scan->psd_gen_count = 0; - for (j = 1; j <= loopcnt; j++) { - - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || roam) { - is_sweep_ok = false; - break; - } - memset(psd_scan->psd_report, 0, - psd_scan->psd_point * sizeof(u32)); - start_p = psd_scan->psd_start_point + - psd_scan->psd_start_base; - stop_p = psd_scan->psd_stop_point + - psd_scan->psd_start_base + 1; - - i = start_p; - point_index = 0; - - while (i < stop_p) { - if (i >= points1) - psd_report = - halbtc8723b1ant_psd_getdata( - btcoexist, i - points1); - else - psd_report = - halbtc8723b1ant_psd_getdata( - btcoexist, i); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Point=%d, psd_raw_data = 0x%08x\n", - i, psd_report); - BTC_TRACE(trace_buf); - if (psd_report == 0) - tmp = 0; - else - /* tmp = 20*log10((double)psd_report); */ - /* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */ - tmp = 6 * halbtc8723b1ant_psd_log2base( - btcoexist, psd_report); - - n = i - psd_scan->psd_start_base; - psd_scan->psd_report[n] = tmp; - - - halbtc8723b1ant_psd_max_holddata( - btcoexist, j); - - i++; - - } - - psd_scan->psd_gen_count = j; - } - - flag = 100; - break; - case 99: /* error */ - - outloop = true; - break; - case 100: /* recovery */ - - /* set 3-wire on */ - val = btcoexist->btc_read_4byte(btcoexist, 0x88c); - val &= 0xffcfffff; - btcoexist->btc_write_4byte(btcoexist, 0x88c, val); - - /* CCK on */ - val = btcoexist->btc_read_4byte(btcoexist, 0x800); - val |= 0x01000000; - btcoexist->btc_write_4byte(btcoexist, 0x800, val); - - /* PSD off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - val &= 0xffbfffff; - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - /* TRx Mask on */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x780); - - /* lock TRx Mask setup */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, - 0x80, 0x0); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, - 0x1, 0x0); - - /* Set RF Rx filter corner */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, 0x0); - - /* restore WiFi original channel */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18, - 0x3ff, wifi_original_channel); - - outloop = true; - break; - - } - - } while (!outloop); - - - - psd_scan->is_psd_running = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n"); - BTC_TRACE(trace_buf); - return is_sweep_ok; - -} - -void halbtc8723b1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 bt_tx_time, IN u32 bt_le_channel) -{ - u32 i = 0; - u32 wlpsd_cent_freq = 2484, wlpsd_span = 2, wlpsd_sweep_count = 50; - s32 wlpsd_offset = -4; - u8 bt_le_ch[13] = {3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 33}; - - u8 h2c_parameter[3] = {0}, u8tmpa, u8tmpb; - - u8 state = 0; - boolean outloop = false, bt_resp = false; - u32 freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point, - u32tmp; - struct btc_board_info *board_info = &btcoexist->board_info; - - board_info->btdm_ant_det_finish = false; - memset(psd_scan->ant_det_peak_val, 0, 16 * sizeof(u8)); - memset(psd_scan->ant_det_peak_freq, 0, 16 * sizeof(u8)); - - if (board_info->tfbga_package) /* for TFBGA */ - psd_scan->ant_det_thres_offset = 5; - else - psd_scan->ant_det_thres_offset = 0; - - do { - switch (state) { - case 0: - if (bt_le_channel == 39) - wlpsd_cent_freq = 2484; - else { - for (i = 1; i <= 13; i++) { - if (bt_le_ch[i - 1] == - bt_le_channel) { - wlpsd_cent_freq = 2412 - + (i - 1) * 5; - break; - } - } - - if (i == 14) { - - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Abort!!, Invalid LE channel = %d\n ", - bt_le_channel); - BTC_TRACE(trace_buf); - outloop = true; - break; - } - } - - wlpsd_sweep_count = bt_tx_time * 238 / - 100; /* bt_tx_time/0.42 */ - wlpsd_sweep_count = wlpsd_sweep_count / 5; - - if (wlpsd_sweep_count % 5 != 0) - wlpsd_sweep_count = (wlpsd_sweep_count / - 5 + 1) * 5; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n", - bt_tx_time, bt_le_channel); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), wlpsd_cent_freq=%d, wlpsd_offset = %d, wlpsd_span = %d, wlpsd_sweep_count = %d\n", - wlpsd_cent_freq, - wlpsd_offset, - wlpsd_span, - wlpsd_sweep_count); - BTC_TRACE(trace_buf); - - state = 1; - break; - case 1: /* stop coex DM & set antenna path */ - /* Stop Coex DM */ - - /* - btcoexist->stop_coex_dm = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n"); - BTC_TRACE(trace_buf); */ - - /* Set TDMA off, */ - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, - false, 0); - - /* Set coex table */ - halbtc8723b1ant_coex_table_with_type(btcoexist, - FORCE_EXEC, 0); - - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n"); - BTC_TRACE(trace_buf); - } - - /* Set Antenna path, switch WiFi to un-certain antenna port */ - halbtc8723b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, FORCE_EXEC, false, - false); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n"); - BTC_TRACE(trace_buf); - - /* Set AFH mask on at WiFi channel 2472MHz +/- 10MHz */ - h2c_parameter[0] = 0x1; - h2c_parameter[1] = 0xd; - h2c_parameter[2] = 0x14; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n", - h2c_parameter[1], - h2c_parameter[2]); - BTC_TRACE(trace_buf); - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, - h2c_parameter); - - u32tmp = btcoexist->btc_read_4byte(btcoexist, - 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, - 0x778); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x778=0x%x\n", - u32tmp, u8tmpa, u8tmpb); - BTC_TRACE(trace_buf); - - state = 2; - break; - case 2: /* Pre-sweep background psd */ - if (!halbtc8723b1ant_psd_sweep_point(btcoexist, - wlpsd_cent_freq, wlpsd_offset, wlpsd_span, - BT_8723B_1ANT_ANTDET_PSD_POINTS, - BT_8723B_1ANT_ANTDET_PSD_AVGNUM, 3)) { - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - psd_scan->ant_det_result = 8; - state = 99; - break; - } - - psd_scan->ant_det_pre_psdscan_peak_val = - psd_scan->psd_max_value; - - if (psd_scan->psd_max_value > - (BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset) * 100) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n", - psd_scan->psd_max_value / 100, - BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset); - BTC_TRACE(trace_buf); - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - psd_scan->ant_det_result = 5; - state = 99; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n", - psd_scan->psd_max_value / 100, - BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset); - BTC_TRACE(trace_buf); - state = 3; - } - break; - case 3: - bt_resp = btcoexist->btc_set_bt_ant_detection( - btcoexist, (u8)(bt_tx_time & 0xff), - (u8)(bt_le_channel & 0xff)); - - if (!halbtc8723b1ant_psd_sweep_point(btcoexist, - wlpsd_cent_freq, wlpsd_offset, - wlpsd_span, - BT_8723B_1ANT_ANTDET_PSD_POINTS, - BT_8723B_1ANT_ANTDET_PSD_AVGNUM, - wlpsd_sweep_count)) { - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - psd_scan->ant_det_result = 8; - state = 99; - break; - } - - psd_scan->ant_det_psd_scan_peak_val = - psd_scan->psd_max_value; - psd_scan->ant_det_psd_scan_peak_freq = - psd_scan->psd_max_value_point; - state = 4; - break; - case 4: - - if (psd_scan->psd_point == 0) - delta_freq_per_point = 0; - else - delta_freq_per_point = - psd_scan->psd_band_width / - psd_scan->psd_point; - - psd_rep1 = psd_scan->psd_max_value / 100; - psd_rep2 = psd_scan->psd_max_value - psd_rep1 * - 100; - - freq = ((psd_scan->real_cent_freq - 20) * - 1000000 + psd_scan->psd_max_value_point - * delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (freq2 < 100) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.0%d MHz", - freq1, freq2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_freq, - BT_8723B_1ANT_ANTDET_BUF_LEN, - "%d.0%d", freq1, freq2); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.%d MHz", - freq1, freq2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_freq, - BT_8723B_1ANT_ANTDET_BUF_LEN, - "%d.%d", freq1, freq2); - } - - if (psd_rep2 < 10) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - ", Value = %d.0%d dB\n", - psd_rep1, psd_rep2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_val, - BT_8723B_1ANT_ANTDET_BUF_LEN, - "%d.0%d", psd_rep1, psd_rep2); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - ", Value = %d.%d dB\n", - psd_rep1, psd_rep2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_val, - BT_8723B_1ANT_ANTDET_BUF_LEN, - "%d.%d", psd_rep1, psd_rep2); - } - - psd_scan->ant_det_is_btreply_available = true; - - if (bt_resp == false) { - psd_scan->ant_det_is_btreply_available = - false; - psd_scan->ant_det_result = 0; - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n "); - BTC_TRACE(trace_buf); - } else if (psd_scan->psd_max_value > - (BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION) - * 100) { - psd_scan->ant_det_result = 1; - board_info->btdm_ant_det_finish = true; - board_info->btdm_ant_det_already_init_phydm = - true; - board_info->btdm_ant_num_by_ant_det = 2; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n"); - BTC_TRACE(trace_buf); - } else if (psd_scan->psd_max_value > - (BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset) * 100) { - psd_scan->ant_det_result = 2; - board_info->btdm_ant_det_finish = true; - board_info->btdm_ant_det_already_init_phydm = - true; - board_info->btdm_ant_num_by_ant_det = 2; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n"); - BTC_TRACE(trace_buf); - } else if (psd_scan->psd_max_value > - (BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT) * - 100) { - psd_scan->ant_det_result = 3; - board_info->btdm_ant_det_finish = true; - board_info->btdm_ant_det_already_init_phydm = - true; - board_info->btdm_ant_num_by_ant_det = 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n"); - BTC_TRACE(trace_buf); - } else { - psd_scan->ant_det_result = 4; - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n"); - BTC_TRACE(trace_buf); - } - - state = 99; - break; - case 99: /* restore setup */ - - /* Set AFH mask off at WiFi channel 2472MHz +/- 10MHz */ - h2c_parameter[0] = 0x0; - h2c_parameter[1] = 0x0; - h2c_parameter[2] = 0x0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n", - h2c_parameter[1], h2c_parameter[2]); - BTC_TRACE(trace_buf); - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, - h2c_parameter); - - /* Set Antenna Path */ - halbtc8723b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, FORCE_EXEC, false, - false); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!"); - BTC_TRACE(trace_buf); - - /* Resume Coex DM */ - /* - btcoexist->stop_coex_dm = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); - BTC_TRACE(trace_buf); */ - - /* stimulate coex running */ - /* - halbtc8723b1ant_run_coexist_mechanism( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); - BTC_TRACE(trace_buf); - */ - - outloop = true; - break; - } - - } while (!outloop); - - - -} - -void halbtc8723b1ant_psd_antenna_detection_check(IN struct btc_coexist - *btcoexist) -{ - static u32 ant_det_count = 0, ant_det_fail_count = 0; - struct btc_board_info *board_info = &btcoexist->board_info; - - boolean scan, roam; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - - /* psd_scan->ant_det_bt_tx_time = 20; */ - psd_scan->ant_det_bt_tx_time = - BT_8723B_1ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */ - psd_scan->ant_det_bt_le_channel = BT_8723B_1ANT_ANTDET_BTTXCHANNEL; - - ant_det_count++; - - psd_scan->ant_det_try_count = ant_det_count; - - if (scan || roam) { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 6; - } else if (coex_sta->bt_disabled) { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 11; - } else if (coex_sta->num_of_profile >= 1) { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 7; - } else if ( - !psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */ - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 9; - } else if (coex_sta->c2h_bt_inquiry_page) { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 10; - } else { - btcoexist->stop_coex_dm = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723b1ant_psd_antenna_detection(btcoexist, - psd_scan->ant_det_bt_tx_time, - psd_scan->ant_det_bt_le_channel); - - delay_ms(psd_scan->ant_det_bt_tx_time); - - btcoexist->stop_coex_dm = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); - BTC_TRACE(trace_buf); - - /* stimulate coex running */ - - halbtc8723b1ant_run_coexist_mechanism( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); - BTC_TRACE(trace_buf); - } - - board_info->ant_det_result = psd_scan->ant_det_result; - if (!board_info->btdm_ant_det_finish) - ant_det_fail_count++; - - psd_scan->ant_det_fail_count = ant_det_fail_count; - -} - - -/* ************************************************************ - * work around function start with wa_halbtc8723b1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8723b1ant_ - * ************************************************************ */ -void ex_halbtc8723b1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x0; - u16 u16tmp = 0x0; - u32 value; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Execute 8723b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Ant Det Finish = %s, Ant Det Number = %d\n", - (board_info->btdm_ant_det_finish ? "Yes" : "No"), - board_info->btdm_ant_num_by_ant_det); - BTC_TRACE(trace_buf); - - - btcoexist->stop_coex_dm = true; - - btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20); - - /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - - /* set GRAN_BT = 1 */ - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); - /* set WLAN_ACT = 0 */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - if (btcoexist->chip_interface == BTC_INTF_USB) { - /* fixed at S0 for USB interface */ - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - - u8tmp |= 0x1; /* antenna inverse */ - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - } else { - /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ - if (board_info->single_ant_path == 0) { - /* set to S1 */ - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x280); - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - value = 1; - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - u8tmp |= 0x1; /* antenna inverse */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - value = 0; - } - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, - &value); - - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384, - u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, - u8tmp); - } -} - -void ex_halbtc8723b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8723b1ant_init_hw_config(btcoexist, true, wifi_only); - btcoexist->stop_coex_dm = false; -} - -void ex_halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - - halbtc8723b1ant_init_coex_dm(btcoexist); - - halbtc8723b1ant_query_bt_info(btcoexist); -} - -void ex_halbtc8723b1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; - u32 fw_ver = 0, bt_patch_ver = 0; - u32 bt_coex_ver = 0; - static u8 pop_report_in_10s = 0; - u32 phyver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - if (psd_scan->ant_det_try_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", - "Ant PG Num/ Mech/ Pos", - board_info->pg_ant_num, board_info->btdm_ant_num, - board_info->btdm_ant_pos); - CL_PRINTF(cli_buf); - } else { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %d (%d/%d/%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos", - board_info->pg_ant_num, - board_info->btdm_ant_num_by_ant_det, - board_info->btdm_ant_pos, - psd_scan->ant_det_try_count, - psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); - CL_PRINTF(cli_buf); - - if (board_info->btdm_ant_det_finish) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - CL_PRINTF(cli_buf); - } - } - - if (board_info->ant_det_result_five_complete) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d", - "Ant number by AntDet", - board_info->btdm_ant_num_by_ant_det); - CL_PRINTF(cli_buf); - } - - /* btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); */ - bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); - bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", - "CoexVer WL/ BT_Desired/ BT_Report", - glcoex_ver_date_8723b_1ant, glcoex_ver_8723b_1ant, - glcoex_ver_btdesired_8723b_1ant, - bt_coex_ver, - (bt_coex_ver == 0xff ? "Unknown" : - (bt_coex_ver >= glcoex_ver_btdesired_8723b_1ant ? - "Match" : "Mis-Match"))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", - "W_FW/ B_FW/ Phy/ Kt", - fw_ver, bt_patch_ver, phyver, - coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", - "WifibHiPri/ Ccklock/ CckEverLock", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), - (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No")); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Abnormal scan", - (coex_sta->bt_abnormal_scan) ? "Yes" : "No"); - CL_PRINTF(cli_buf); - - pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); - CL_PRINTF(cli_buf); - - if (pop_report_in_10s >= 5) { - coex_sta->pop_event_cnt = 0; - pop_report_in_10s = 0; - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d / %d / %d / %d / %d / %d", - "SCO/HID/PAN/A2DP/NameReq/WHQL", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist, - coex_sta->c2h_bt_remote_name_req, - coex_sta->bt_whck_test); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Role", - (bt_link_info->slave_role) ? "Slave" : "Master"); - CL_PRINTF(cli_buf); - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d", - "A2DP Rate/Bitpool", - (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8723B_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8723b_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms] (before Manual)============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "SM[LowPenaltyRA]", - coex_dm->cur_low_penalty_ra); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - if (board_info->btdm_ant_num_by_ant_det == 2) { - if (coex_dm->cur_ps_tdma_on) - ps_tdma_case = ps_tdma_case + - 100; /* for WiFi RSSI low or BT RSSI low */ - else - ps_tdma_case = - 1; /* always translate to TDMA(off,1) for TDMA-off case */ - } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "On" : "Off"), - (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); - - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Coex Table Type", - coex_sta->coex_table_type); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "IgnWlanAct", - coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - /* - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Latest error condition(should be 0)", - coex_dm->error_condition); - CL_PRINTF(cli_buf); - */ - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "backup ARFR1/ARFR2/RL/AMaxTime", - coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2, - coex_dm->backup_retry_limit, - coex_dm->backup_ampdu_max_time); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x880); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x778/0x6cc/0x880[29:25]", - u8tmp[0], u32tmp[0], (u32tmp[1] & 0x3e000000) >> 25); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x764); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x76e); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x948/ 0x67[5] / 0x764 / 0x76e", - u32tmp[0], ((u8tmp[0] & 0x20) >> 5), (u32tmp[1] & 0xffff), - u8tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x92c); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x930); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x944); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]", - u32tmp[0] & 0x3, u32tmp[1] & 0xff, u32tmp[2] & 0x3); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x39); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x38[11]/0x40/0x4c[24:23]/0x64[0]", - ((u8tmp[0] & 0x8) >> 3), u8tmp[1], - ((u32tmp[0] & 0x01800000) >> 23), u8tmp[2] & 0x1); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xc50(dig)/0x49c(null-drop)", - u32tmp[0] & 0xff, u8tmp[0]); - CL_PRINTF(cli_buf); - - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_CCK); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8723B_1ANT == 1) - /* halbtc8723b1ant_monitor_bt_ctr(btcoexist); */ -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8723b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723b1ant_init_hw_config(btcoexist, false, false); - halbtc8723b1ant_init_coex_dm(btcoexist); - halbtc8723b1ant_query_bt_info(btcoexist); - - coex_sta->under_ips = false; - } -} - -void ex_halbtc8723b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8723b1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - u8 u8tmpa, u8tmpb; - u32 u32tmp; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_SCAN_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - psd_scan->ant_det_is_ant_det_available = true; - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", - u32tmp, u8tmpa, u8tmpb); - BTC_TRACE(trace_buf); - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - } - - if (coex_sta->bt_disabled) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - halbtc8723b1ant_query_bt_info(btcoexist); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8723b1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8723b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723b1ant_action_hs(btcoexist); - return; - } - - if (BTC_SCAN_START == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8723b1ant_action_wifi_not_connected_scan( - btcoexist); - else /* wifi is connected */ - halbtc8723b1ant_action_wifi_connected_scan(btcoexist); - } else if (BTC_SCAN_FINISH == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8723b1ant_action_wifi_not_connected(btcoexist); - else - halbtc8723b1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8723b1ant_set_antenna_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (type == 2) /* two antenna */ - halbtc8723b1ant_mechanism_switch(btcoexist, true); - else /* one antenna */ - halbtc8723b1ant_mechanism_switch(btcoexist, false); -} - -void ex_halbtc8723b1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_ASSOCIATE_START == type) { - coex_sta->wifi_is_high_pri_task = true; - psd_scan->ant_det_is_ant_det_available = true; - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - /* coex_dm->arp_cnt = 0; */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8723b1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8723b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723b1ant_action_hs(btcoexist); - return; - } - - if (BTC_ASSOCIATE_START == type) - halbtc8723b1ant_action_wifi_not_connected_asso_auth(btcoexist); - else if (BTC_ASSOCIATE_FINISH == type) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (!wifi_connected) /* non-connected scan */ - halbtc8723b1ant_action_wifi_not_connected(btcoexist); - else - halbtc8723b1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8723b1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - boolean wifi_under_b_mode = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - psd_scan->ant_det_is_ant_det_available = true; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - - coex_sta->cck_ever_lock = false; - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - /* h2c_parameter[0] = 0x1; */ - h2c_parameter[0] = 0x0; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); -} - -void ex_halbtc8723b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false, under_4way = false; - u8 agg_buf_size = 5; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - BTC_PACKET_ARP == type) { - if (BTC_PACKET_ARP == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify\n"); - BTC_TRACE(trace_buf); - - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ARP Packet Count = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - - if ((coex_dm->arp_cnt >= 10) && - (!under_4way)) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */ - coex_sta->wifi_is_high_pri_task = false; - else - coex_sta->wifi_is_high_pri_task = true; - } else { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify\n"); - BTC_TRACE(trace_buf); - } - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet [Type = %d] notify\n", type); - BTC_TRACE(trace_buf); - } - - coex_sta->specific_pkt_period_cnt = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8723b1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8723b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8723b1ant_action_hs(btcoexist); - return; - } - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task))) - halbtc8723b1ant_action_wifi_connected_specific_packet( - btcoexist); -} - -/* Donot remove optimize off flag, otherwise antenna detection would trigger BT collapsed */ -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean bt_busy = false; - struct btc_board_info *board_info = &btcoexist->board_info; - - coex_sta->c2h_bt_info_req_sent = false; - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8723B_1ANT_MAX) - rsp_source = BT_INFO_SRC_8723B_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - /* if 0xff, it means BT is under WHCK test */ - if (bt_info == 0xff) - coex_sta->bt_whck_test = true; - else - coex_sta->bt_whck_test = false; - - if (BT_INFO_SRC_8723B_1ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_remote_name_req = true; - else - coex_sta->c2h_bt_remote_name_req = false; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; - /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */ - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - if (coex_sta->bt_info_c2h[rsp_source][1] == 0x49) { - coex_sta->a2dp_bit_pool = - coex_sta->bt_info_c2h[rsp_source][6]; - } else - coex_sta->a2dp_bit_pool = 0; - - coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] - & 0x40); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, - &coex_sta->bt_tx_rx_mask); - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT info Notify() return because stop_coex_dm\n"); - BTC_TRACE(trace_buf); - - return; - } - - -#if BT_8723B_1ANT_ANTDET_ENABLE -#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE - if ((board_info->btdm_ant_det_finish) && - (board_info->btdm_ant_num_by_ant_det == 2)) { - if (coex_sta->bt_tx_rx_mask) { - - /* BT TRx mask off */ - btcoexist->btc_set_bt_trx_mask(btcoexist, 0); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT TRx Mask off for BT Info Notify\n"); - BTC_TRACE(trace_buf); -#if 0 - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x1\n"); - BTC_TRACE(trace_buf); - - /* BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 */ - btcoexist->btc_set_bt_reg(btcoexist, - BTC_BT_REG_RF, 0x2c, 0x7c45); - btcoexist->btc_set_bt_reg(btcoexist, - BTC_BT_REG_RF, 0x30, 0x7c45); - - btcoexist->btc_set_bt_reg(btcoexist, - BTC_BT_REG_RF, 0x3c, 0x1); -#endif - } - } else -#endif -#endif - - { - if (!coex_sta->bt_tx_rx_mask) { - - /* BT TRx mask on */ - btcoexist->btc_set_bt_trx_mask(btcoexist, 1); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT TRx Mask on for BT Info Notify\n"); - BTC_TRACE(trace_buf); -#if 0 - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_bt_reg(btcoexist, - BTC_BT_REG_RF, - 0x3c, 0x15); - - /* BT TRx Mask lock 0x2c[0], 0x30[0] = 0 */ - btcoexist->btc_set_bt_reg(btcoexist, - BTC_BT_REG_RF, - 0x2c, 0x7c44); - btcoexist->btc_set_bt_reg(btcoexist, - BTC_BT_REG_RF, - 0x30, 0x7c44); -#endif - } - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if (coex_sta->bt_info_ext & BIT(1)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8723b1ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8723b1ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if (coex_sta->bt_info_ext & BIT(3)) { - if (!btcoexist->manual_control && - !btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - } -#if (BT_AUTO_REPORT_ONLY_8723B_1ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8723b1ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - coex_sta->num_of_profile = 0; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - - coex_sta->bt_hi_pri_link_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8723B_1ANT_B_FTP) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) { - coex_sta->a2dp_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8723B_1ANT_B_HID) { - coex_sta->hid_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) { - coex_sta->sco_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = false; - - if ((coex_sta->hid_exist == false) && - (coex_sta->c2h_bt_inquiry_page == false) && - (coex_sta->sco_exist == false)) { - if (coex_sta->high_priority_tx + - coex_sta->high_priority_rx >= 160) { - coex_sta->hid_exist = true; - coex_sta->wrong_profile_notification++; - coex_sta->num_of_profile++; - bt_info = bt_info | 0x28; - } - } - - /* Add Hi-Pri Tx/Rx counter to avoid false detection */ - if (((coex_sta->hid_exist) || (coex_sta->sco_exist)) && - (coex_sta->high_priority_tx + - coex_sta->high_priority_rx >= 160) - && (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->bt_hi_pri_link_exist = true; - - if ((bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) && - (coex_sta->num_of_profile == 0)) { - if (coex_sta->low_priority_tx + - coex_sta->low_priority_rx >= 160) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - coex_sta->wrong_profile_notification++; - bt_info = bt_info | 0x88; - } - } - } - - halbtc8723b1ant_update_bt_link_info(btcoexist); - - bt_info = bt_info & - 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ - - if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) - coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - else if (bt_info == - BT_INFO_8723B_1ANT_B_CONNECTION) /* connection exists but no busy */ - coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE; - else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY)) - coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_SCO_BUSY; - else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) { - if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) - coex_dm->auto_tdma_adjust = false; - coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_ACL_BUSY; - } else - coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_MAX; - - if ((BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - halbtc8723b1ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8723b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u32 u32tmp; - u8 u8tmpa, u8tmpb, u8tmpc; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - } else if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - - halbtc8723b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - btcoexist->stop_coex_dm = true; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67); - u8tmpc = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n", - u32tmp, u8tmpa, u8tmpb, u8tmpc); - BTC_TRACE(trace_buf); - - } -} - -void ex_halbtc8723b1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, - false, true); - - halbtc8723b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8723b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8723b1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - halbtc8723b1ant_init_hw_config(btcoexist, false, false); - halbtc8723b1ant_init_coex_dm(btcoexist); - halbtc8723b1ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8723b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) -{ - - halbtc8723b1ant_init_hw_config(btcoexist, false, false); - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); */ - halbtc8723b1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8723b1ant_periodical(IN struct btc_coexist *btcoexist) -{ - u32 bt_patch_ver; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ==========================Periodical===========================\n"); - BTC_TRACE(trace_buf); - -#if (BT_AUTO_REPORT_ONLY_8723B_1ANT == 0) - halbtc8723b1ant_query_bt_info(btcoexist); -#endif - halbtc8723b1ant_monitor_bt_ctr(btcoexist); - halbtc8723b1ant_monitor_wifi_ctr(btcoexist); - - halbtc8723b1ant_monitor_bt_enable_disable(btcoexist); - - - if (halbtc8723b1ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust || - btcoexist->bt_info.bt_enable_disable_change) - halbtc8723b1ant_run_coexist_mechanism(btcoexist); - - if (((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) && (!coex_sta->bt_disabled)) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, &coex_sta->bt_coex_supported_version); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; - coex_sta->specific_pkt_period_cnt++; - - /* sample to set bt to execute Ant detection */ - /* btcoexist->btc_set_bt_ant_detection(btcoexist, 20, 14); - * - if (psd_scan->is_ant_det_enable) - { - if (psd_scan->psd_gen_count > psd_scan->realseconds) - psd_scan->psd_gen_count = 0; - - halbtc8723b1ant_antenna_detection(btcoexist, psd_scan->realcent_freq, psd_scan->realoffset, psd_scan->realspan, psd_scan->realseconds); - psd_scan->psd_gen_total_count +=2; - psd_scan->psd_gen_count += 2; - } - */ -} - -/* Donot remove optimize off flag, otherwise antenna detection would trigger BT collapsed */ -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ -#if BT_8723B_1ANT_ANTDET_ENABLE - static u32 ant_det_count = 0, ant_det_fail_count = 0; - struct btc_board_info *board_info = &btcoexist->board_info; - /*boolean scan, roam;*/ - - if (seconds == 0) { - psd_scan->ant_det_try_count = 0; - psd_scan->ant_det_fail_count = 0; - ant_det_count = 0; - ant_det_fail_count = 0; - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - return; - } - - if (!board_info->btdm_ant_det_finish) { - psd_scan->ant_det_inteval_count = - psd_scan->ant_det_inteval_count + 2; - - if (psd_scan->ant_det_inteval_count >= - BT_8723B_1ANT_ANTDET_RETRY_INTERVAL) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b1ant_psd_antenna_detection_check(btcoexist); - - if (board_info->btdm_ant_det_finish) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n"); - BTC_TRACE(trace_buf); - - -#if 1 - if (board_info->btdm_ant_num_by_ant_det == 2) - halbtc8723b1ant_mechanism_switch( - btcoexist, true); - else - halbtc8723b1ant_mechanism_switch( - btcoexist, false); -#endif - - board_info->btdm_ant_det_complete_fail = false; - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n"); - BTC_TRACE(trace_buf); - - board_info->btdm_ant_det_complete_fail = true; - } - psd_scan->ant_det_inteval_count = 0; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n", - psd_scan->ant_det_inteval_count); - BTC_TRACE(trace_buf); - } - - } -#endif - - - /* - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - - psd_scan->ant_det_bt_tx_time = seconds; - psd_scan->ant_det_bt_le_channel = cent_freq; - - if (seconds == 0) - { - psd_scan->ant_det_try_count = 0; - psd_scan->ant_det_fail_count = 0; - ant_det_count = 0; - ant_det_fail_count = 0; - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - return; - } - else - { - ant_det_count++; - - psd_scan->ant_det_try_count = ant_det_count; - - if (scan ||roam) - { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 6; - } - else if (coex_sta->num_of_profile >= 1) - { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 7; - } - else if (!psd_scan->ant_det_is_ant_det_available) - { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 9; - } - else if (coex_sta->c2h_bt_inquiry_page) - { - board_info->btdm_ant_det_finish = false; - psd_scan->ant_det_result = 10; - } - else - { - - } - - if (!board_info->btdm_ant_det_finish) - ant_det_fail_count++; - - psd_scan->ant_det_fail_count = ant_det_fail_count; - } - */ -} - - -void ex_halbtc8723b1ant_display_ant_detection(IN struct btc_coexist *btcoexist) -{ -#if BT_8723B_1ANT_ANTDET_ENABLE - struct btc_board_info *board_info = &btcoexist->board_info; - - if (psd_scan->ant_det_try_count != 0) { - halbtc8723b1ant_psd_show_antenna_detect_result(btcoexist); - - if (board_info->btdm_ant_det_finish) - halbtc8723b1ant_psd_showdata(btcoexist); - return; - } -#endif - - /* halbtc8723b1ant_show_psd_data(btcoexist); */ -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ - - - diff --git a/hal/btc/halbtc8723b1ant.h b/hal/btc/halbtc8723b1ant.h deleted file mode 100644 index adb29d4..0000000 --- a/hal/btc/halbtc8723b1ant.h +++ /dev/null @@ -1,307 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8723B_SUPPORT == 1) -/* ******************************************* - * The following is for 8723B 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8723B_1ANT 1 - -#define BT_INFO_8723B_1ANT_B_FTP BIT(7) -#define BT_INFO_8723B_1ANT_B_A2DP BIT(6) -#define BT_INFO_8723B_1ANT_B_HID BIT(5) -#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2 - -#define BT_8723B_1ANT_WIFI_NOISY_THRESH 50 /* 30 /max: 255 */ - -/* for Antenna detection */ -#define BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 -#define BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 -#define BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 48 -#define BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT 32 -#define BT_8723B_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY 40000 -#define BT_8723B_1ANT_ANTDET_ENABLE 1 -#define BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 1 -#define BT_8723B_1ANT_ANTDET_BTTXTIME 100 -#define BT_8723B_1ANT_ANTDET_BTTXCHANNEL 39 - -enum bt_info_src_8723b_1ant { - BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8723B_1ANT_MAX -}; - -enum bt_8723b_1ant_bt_status { - BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8723B_1ANT_BT_STATUS_MAX -}; - -enum bt_8723b_1ant_wifi_status { - BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8723B_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8723b_1ant_coex_algo { - BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8723B_1ANT_COEX_ALGO_SCO = 0x1, - BT_8723B_1ANT_COEX_ALGO_HID = 0x2, - BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8723B_1ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8723b_1ant { - /* hw setting */ - u8 pre_ant_pos_type; - u8 cur_ant_pos_type; - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u8 error_condition; -}; - -struct coex_sta_8723b_1ant { - boolean bt_disabled; - boolean bt_enable_disable_change; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - boolean bt_hi_pri_link_exist; - u8 num_of_profile; - boolean bt_abnormal_scan; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - s8 bt_rssi; - boolean bt_tx_rx_mask; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8723B_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_1ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_remote_name_req; - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - u8 bt_retry_cnt; - u8 bt_info_ext; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; - - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; - u8 coex_table_type; - - boolean force_lps_on; - u32 wrong_profile_notification; - u32 bt_coex_supported_version; - u8 a2dp_bit_pool; - u8 cut_version; -}; - -#define BT_8723B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ -#define BT_8723B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ -#define BT_8723B_1ANT_ANTDET_BUF_LEN 16 - -struct psdscan_sta_8723b_1ant { - - u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ - u32 ant_det_bt_tx_time; - u32 ant_det_pre_psdscan_peak_val; - boolean ant_det_is_ant_det_available; - u32 ant_det_psd_scan_peak_val; - boolean ant_det_is_btreply_available; - u32 ant_det_psd_scan_peak_freq; - - u8 ant_det_result; - u8 ant_det_peak_val[BT_8723B_1ANT_ANTDET_BUF_LEN]; - u8 ant_det_peak_freq[BT_8723B_1ANT_ANTDET_BUF_LEN]; - u32 ant_det_try_count; - u32 ant_det_fail_count; - u32 ant_det_inteval_count; - u32 ant_det_thres_offset; - - u32 real_cent_freq; - s32 real_offset; - u32 real_span; - - u32 psd_band_width; /* unit: Hz */ - u32 psd_point; /* 128/256/512/1024 */ - u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_start_point; - u32 psd_stop_point; - u32 psd_max_value_point; - u32 psd_max_value; - u32 psd_start_base; - u32 psd_avg_num; /* 1/8/16/32 */ - u32 psd_gen_count; - boolean is_psd_running; - boolean is_psd_show_max_only; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8723b1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_set_antenna_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8723b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8723b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); - -void ex_halbtc8723b1ant_display_ant_detection(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8723b1ant_power_on_setting(btcoexist) -#define ex_halbtc8723b1ant_pre_load_firmware(btcoexist) -#define ex_halbtc8723b1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8723b1ant_init_coex_dm(btcoexist) -#define ex_halbtc8723b1ant_ips_notify(btcoexist, type) -#define ex_halbtc8723b1ant_lps_notify(btcoexist, type) -#define ex_halbtc8723b1ant_scan_notify(btcoexist, type) -#define ex_halbtc8723b1ant_set_antenna_notify(btcoexist, type) -#define ex_halbtc8723b1ant_connect_notify(btcoexist, type) -#define ex_halbtc8723b1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8723b1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8723b1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8723b1ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8723b1ant_halt_notify(btcoexist) -#define ex_halbtc8723b1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8723b1ant_coex_dm_reset(btcoexist) -#define ex_halbtc8723b1ant_periodical(btcoexist) -#define ex_halbtc8723b1ant_display_coex_info(btcoexist) -#define ex_halbtc8723b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8723b1ant_display_ant_detection(btcoexist) - -#endif - -#endif - diff --git a/hal/btc/halbtc8723b2ant.c b/hal/btc/halbtc8723b2ant.c deleted file mode 100644 index d74f103..0000000 --- a/hal/btc/halbtc8723b2ant.c +++ /dev/null @@ -1,4972 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for RTL8723B Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8723B_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8723b_2ant glcoex_dm_8723b_2ant; -static struct coex_dm_8723b_2ant *coex_dm = &glcoex_dm_8723b_2ant; -static struct coex_sta_8723b_2ant glcoex_sta_8723b_2ant; -static struct coex_sta_8723b_2ant *coex_sta = &glcoex_sta_8723b_2ant; - -const char *const glbt_info_src_8723b_2ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8723b_2ant = 20161007; -u32 glcoex_ver_8723b_2ant = 0x4c; -u32 glcoex_ver_btdesired_8723b_2ant = 0x4c; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8723b2ant_ - * ************************************************************ */ -u8 halbtc8723b2ant_bt_rssi_state(u8 *ppre_bt_rssi_state, u8 level_num, - u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = *ppre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return *ppre_bt_rssi_state; - } - - if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - *ppre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8723b2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh, - IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = *pprewifi_rssi_state; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || - (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return *pprewifi_rssi_state; - } - - if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || - (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - *pprewifi_rssi_state = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8723b2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 10) - bt_disabled = true; - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - - coex_sta->bt_disabled = bt_disabled; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - if (bt_disabled) { - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - } - } -} - - -void halbtc8723b2ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); -} - -void halbtc8723b2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if ((coex_sta->low_priority_tx > 1050) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - if ((coex_sta->low_priority_rx >= 950) && - (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) && - (!coex_sta->under_ips)) - bt_link_info->slave_role = true; - else - bt_link_info->slave_role = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); -} - -void halbtc8723b2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ -#if 1 - - coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_VHT); - -#endif -} - -void halbtc8723b2ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -boolean halbtc8723b2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) || - (BTC_RSSI_STATE_LOW == wifi_rssi_state)) - return true; - - } - - return false; -} - -void halbtc8723b2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8723b2ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8723B_2ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_HID_A2DP; - } - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8723b2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - -void halbtc8723b2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN u8 dec_bt_pwr_lvl) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = dec_bt_pwr_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); -} - -void halbtc8723b2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 dec_bt_pwr_lvl) -{ - coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; - - if (!force_exec) { - if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) - return; - } - halbtc8723b2ant_set_fw_dec_bt_pwr(btcoexist, - coex_dm->cur_bt_dec_pwr_lvl); - - coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; -} - -void halbtc8723b2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8723b2ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8723b2ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8723b2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8723b2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - -void halbtc8723b2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist, - IN boolean rx_rf_shrink_on) -{ - if (rx_rf_shrink_on) { - /* Shrink RF Rx LPF corner */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Shrink RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, - 0xffffc); - } else { - /* Resume RF Rx LPF corner */ - /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ - if (btcoexist->initilized) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Resume RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, coex_dm->bt_rf_0x1e_backup); - } - } -} - -void halbtc8723b2ant_rf_shrink(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rx_rf_shrink_on) -{ - coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; - - if (!force_exec) { - if (coex_dm->pre_rf_rx_lpf_shrink == - coex_dm->cur_rf_rx_lpf_shrink) - return; - } - halbtc8723b2ant_set_sw_rf_rx_lpf_corner(btcoexist, - coex_dm->cur_rf_rx_lpf_shrink); - - coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; -} - -void halbtc8723b2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf4; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf5; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf6; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8723b2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8723b2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8723b2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, - IN u32 level) -{ - u8 val = (u8)level; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Write SwDacSwing = 0x%x\n", level); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val); -} - -void halbtc8723b2ant_set_sw_full_time_dac_swing(IN struct btc_coexist - *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) -{ - if (sw_dac_swing_on) - halbtc8723b2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl); - else - halbtc8723b2ant_set_dac_swing_reg(btcoexist, 0x18); -} - - -void halbtc8723b2ant_dac_swing(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) -{ - coex_dm->cur_dac_swing_on = dac_swing_on; - coex_dm->cur_dac_swing_lvl = dac_swing_lvl; - - if (!force_exec) { - if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && - (coex_dm->pre_dac_swing_lvl == - coex_dm->cur_dac_swing_lvl)) - return; - } - delay_ms(30); - halbtc8723b2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, - dac_swing_lvl); - - coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; - coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; -} - -void halbtc8723b2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean adc_back_off) -{ - if (adc_back_off) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x3); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x1); - } -} - -void halbtc8723b2ant_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean adc_back_off) -{ - coex_dm->cur_adc_back_off = adc_back_off; - - if (!force_exec) { - if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) - return; - } - halbtc8723b2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off); - - coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; -} - -void halbtc8723b2ant_set_agc_table(IN struct btc_coexist *btcoexist, - IN boolean agc_table_en) -{ - u8 rssi_adjust_val = 0; - - /* =================BB AGC Gain Table */ - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6e1A0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6d1B0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6c1C0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6b1D0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6a1E0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x691F0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x68200001); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa4200001); - } - - - /* =================RF Gain */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x38fff); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x38ffe); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x380c3); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x28ce6); - } - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x1); - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x38fff); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x38ffe); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x380c3); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x28ce6); - } - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x0); - - /* set rssi_adjust_val for wifi module. */ - if (agc_table_en) - rssi_adjust_val = 8; - btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, - &rssi_adjust_val); -} - -void halbtc8723b2ant_agc_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean agc_table_en) -{ - coex_dm->cur_agc_table_en = agc_table_en; - - if (!force_exec) { - if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) - return; - } - halbtc8723b2ant_set_agc_table(btcoexist, agc_table_en); - - coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; -} - -void halbtc8723b2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, - IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, - IN boolean limited_dig, IN boolean bt_lna_constrain) -{ - /* - u32 wifi_bw; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if(BTC_WIFI_BW_HT40 != wifi_bw) - { - if (shrink_rx_lpf) - shrink_rx_lpf = false; - } - */ - - /* halbtc8723b2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); */ - halbtc8723b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8723b2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, - IN boolean agc_table_shift, IN boolean adc_back_off, - IN boolean sw_dac_swing, IN u32 dac_swing_lvl) -{ - /* halbtc8723b2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */ - /* halbtc8723b2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */ - /* halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, dac_swing_lvl); */ -} - -void halbtc8723b2ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8723b2ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8723b2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8723b2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_sta->coex_table_type = type; - - switch (type) { - case 0: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, 0xffffff, 0x3); - break; - case 1: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5afa5afa, 0xffffff, 0x3); - break; - case 2: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3); - break; - case 3: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 4: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0xffffffff, 0xffffffff, 0xffffff, 0x3); - break; - case 5: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3); - break; - case 6: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 7: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 8: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 9: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 10: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 11: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 12: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 13: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 14: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); - break; - case 15: - halbtc8723b2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8723b2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) - h2c_parameter[0] |= BIT(0); /* function enable */ - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8723b2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8723b2ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8723b2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8723b2ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8723b2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8723b2ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - u8 h2c_parameter[5] = {0x0, 0, 0, 48, 0}; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - /* halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - /* halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8723b2ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8723b2ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8723b2ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8723b2ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - - -void halbtc8723b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - if ((coex_sta->a2dp_exist) && (coex_sta->hid_exist)) - byte5 = byte5 | 0x1; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - - halbtc8723b2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - } - } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - halbtc8723b2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - - } else { - halbtc8723b2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - } - - h2c_parameter[0] = byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = byte5; - - coex_dm->ps_tdma_para[0] = byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8723b2ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state1, bt_rssi_state; - s8 wifi_duration_adjust = 0x0; - u8 psTdmaByte4Modify = 0x0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s turn %s PS TDMA, type=%d\n", - (force_exec ? "force to" : ""), (turn_on ? "ON" : "OFF"), type); - BTC_TRACE(trace_buf); - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - if (!(BTC_RSSI_HIGH(wifi_rssi_state1) && - BTC_RSSI_HIGH(bt_rssi_state)) && turn_on) - /* if (halbtc8723b2ant_CoexSwitchThresCheck(btcoexist) && turn_on) */ - { - type = type + 100; /* for WiFi RSSI low or BT RSSI low */ - coex_dm->is_switch_to_1dot5_ant = true; - } else - coex_dm->is_switch_to_1dot5_ant = false; - - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_sta->scan_ap_num <= 5) { - if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - else if (coex_sta->a2dp_bit_pool >= 35) - wifi_duration_adjust = -10; - else - wifi_duration_adjust = 5; - } else if (coex_sta->scan_ap_num <= 20) { - if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - else if (coex_sta->a2dp_bit_pool >= 35) - wifi_duration_adjust = -10; - else - wifi_duration_adjust = 0; - } else if (coex_sta->scan_ap_num <= 40) { - if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - else if (coex_sta->a2dp_bit_pool >= 35) - wifi_duration_adjust = -10; - else - wifi_duration_adjust = -5; - } else { - if (coex_sta->a2dp_bit_pool >= 45) - wifi_duration_adjust = -15; - else if (coex_sta->a2dp_bit_pool >= 35) - wifi_duration_adjust = -10; - else - wifi_duration_adjust = -10; - } - - if ((bt_link_info->slave_role == true) && (bt_link_info->a2dp_exist)) - psTdmaByte4Modify = - 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - - - if (turn_on) { - switch (type) { - case 1: - default: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x03, 0xf1, - 0x90 | psTdmaByte4Modify); - break; - case 2: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d + wifi_duration_adjust, 0x03, 0xf1, - 0x90 | psTdmaByte4Modify); - break; - case 3: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, 0x90 | - psTdmaByte4Modify); - break; - case 4: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x03, 0xf1, 0x90 | - psTdmaByte4Modify); - break; - case 5: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x3, 0x70, - 0x90 | psTdmaByte4Modify); - break; - case 6: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d + wifi_duration_adjust, 0x3, 0x70, - 0x90 | psTdmaByte4Modify); - break; - case 7: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0x70, 0x90 | - psTdmaByte4Modify); - break; - case 8: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xa3, - 0x10, 0x3, 0x70, 0x90 | - psTdmaByte4Modify); - break; - case 9: - /* - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x03, 0xf1, - 0x90 | psTdmaByte4Modify); - */ - /* Bryant Modify for BT no-profile busy case */ - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x03, 0xf1, - 0x91); - - break; - case 10: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d + wifi_duration_adjust, 0x03, 0xf1, - 0x90 | psTdmaByte4Modify); - break; - case 11: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, 0x90 | - psTdmaByte4Modify); - break; - case 12: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0xf1, 0x90 | - psTdmaByte4Modify); - break; - case 13: - /* - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x3, 0x70, - 0x90 | psTdmaByte4Modify); - */ - /* Bryant Modify for BT no-profile busy case */ - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x3, 0x70, - 0x91); - break; - case 14: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d + wifi_duration_adjust, 0x3, 0x70, - 0x90 | psTdmaByte4Modify); - break; - case 15: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0x70, 0x90 | - psTdmaByte4Modify); - break; - case 16: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0x70, 0x90 | - psTdmaByte4Modify); - break; - case 17: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xa3, - 0x2f, 0x2f, 0x60, 0x90); - break; - case 18: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x5, 0x5, 0xe1, 0x90); - break; - case 19: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0xe1, 0x90); - break; - case 20: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0x60, 0x90); - break; - case 21: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x03, 0x70, 0x90); - break; - case 22: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x03, 0xf1, 0x90); - break; - case 23: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x03, 0x71, 0x10); - break; - - case 25: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x30, 0x03, 0x71, 0x10); - break; - - case 33: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, 0x91); - - break; - case 71: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c + wifi_duration_adjust, 0x03, 0xf1, - 0x90); - break; - case 101: - case 105: - case 113: - case 171: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x3a + wifi_duration_adjust, 0x03, 0x70, - 0x50 | psTdmaByte4Modify); - break; - case 102: - case 106: - case 110: - case 114: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x2d + wifi_duration_adjust, 0x03, 0x70, - 0x50 | psTdmaByte4Modify); - break; - case 103: - case 107: - case 111: - case 115: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1c, 0x03, 0x70, 0x50 | - psTdmaByte4Modify); - break; - case 104: - case 108: - case 112: - case 116: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x10, 0x03, 0x70, 0x50 | - psTdmaByte4Modify); - break; - case 109: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0xf1, 0x90 | - psTdmaByte4Modify); - break; - /* case 113: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0x70, 0x90 | - psTdmaByte4Modify); - break; */ - case 121: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x03, 0x70, 0x90 | - psTdmaByte4Modify); - break; - case 122: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x03, 0x71, 0x11); - break; - case 123: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x03, 0x71, 0x10); - break; - case 125: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x30, 0x03, 0x70, 0x51); - break; - - case 133: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1c, 0x3, 0x70, 0x51); - - break; - } - } else { - /* disable PS tdma */ - switch (type) { - case 0: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - case 1: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - default: - halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - - -void halbtc8723b2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u32 fw_ver = 0, u32tmp = 0, cnt_bt_cal_chk = 0; - boolean pg_ext_switch = false; - boolean use_ext_switch = false; - u8 h2c_parameter[2] = {0}; - u32 u32tmp_1[4]; - boolean is_fw_ready; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_EXT_SWITCH, &pg_ext_switch); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, - &fw_ver); /* [31:16]=fw ver, [15:0]=fw sub ver */ - - if ((fw_ver > 0 && fw_ver < 0xc0000) || pg_ext_switch) - use_ext_switch = true; - - if (init_hwcfg) { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x39, 0x8, 0x1); - btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x944, 0x3, 0x3); - btcoexist->btc_write_1byte(btcoexist, 0x930, 0x77); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1); - - if (fw_ver >= 0x180000) { - /* Use H2C to set GNT_BT to High to avoid A2DP click */ - h2c_parameter[0] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, - h2c_parameter); - - cnt_bt_cal_chk = 0; - while (1) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready); - if (is_fw_ready == false) - break; - - if (btcoexist->btc_read_1byte(btcoexist, - 0x765) == 0x18) - break; - - cnt_bt_cal_chk++; - if (cnt_bt_cal_chk > 20) - break; - } - } else - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); - u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); - if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte(btcoexist, 0x948, - u32tmp_1[0]); - else - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); /* WiFi TRx Mask off */ - /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */ - /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x01); */ /*BT TRx Mask off */ - - if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { - /* tell firmware "no antenna inverse" */ - h2c_parameter[0] = 0; - } else { - /* tell firmware "antenna inverse" */ - h2c_parameter[0] = 1; - } - - if (use_ext_switch) { - /* ext switch type */ - h2c_parameter[1] = 1; - } else { - /* int switch type */ - h2c_parameter[1] = 0; - } - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, h2c_parameter); - } else { - if (fw_ver >= 0x180000) { - /* Use H2C to set GNT_BT to "Control by PTA"*/ - h2c_parameter[0] = 0; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, - h2c_parameter); - - cnt_bt_cal_chk = 0; - while (1) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready); - if (is_fw_ready == false) - break; - - if (btcoexist->btc_read_1byte(btcoexist, - 0x765) == 0x0) - break; - - cnt_bt_cal_chk++; - if (cnt_bt_cal_chk > 20) - break; - } - } else - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x0); - } - - /* ext switch setting */ - if (use_ext_switch) { - if (init_hwcfg) { - /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp |= BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } - u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); - if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte(btcoexist, 0x948, - u32tmp_1[0]); - else - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - - switch (ant_pos_type) { - case BTC_ANT_WIFI_AT_MAIN: - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0x92c, 0x3, - 0x1); /* ext switch main at wifi */ - break; - case BTC_ANT_WIFI_AT_AUX: - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0x92c, 0x3, - 0x2); /* ext switch aux at wifi */ - break; - } - } else { /* internal switch */ - if (init_hwcfg) { - /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp |= BIT(23); - u32tmp &= ~BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - } - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, - 0x0); /* fixed external switch S1->Main, S0->Aux */ - switch (ant_pos_type) { - case BTC_ANT_WIFI_AT_MAIN: - u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, - 0x948); - if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte(btcoexist, 0x948, - u32tmp_1[0]); - else - btcoexist->btc_write_4byte(btcoexist, 0x948, - 0x0); - break; - case BTC_ANT_WIFI_AT_AUX: - u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, - 0x948); - if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240)) - btcoexist->btc_write_4byte(btcoexist, 0x948, - u32tmp_1[0]); - else - btcoexist->btc_write_4byte(btcoexist, 0x948, - 0x280); - break; - } - } -} -#if 0 -boolean halbtc8723b2ant_CoexSwitchThresCheck(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state1, bt_rssi_state; - u32 vendor; - u8 offset = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor); - - /* if (vendor == BTC_VENDOR_LENOVO) */ - /* offset = 20; */ - - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - if (BTC_RSSI_LOW(wifi_rssi_state1) || BTC_RSSI_LOW(bt_rssi_state)) - return true; - - return false; -} -#endif - - -void halbtc8723b2ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* fw all off */ - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0); - - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - coex_sta->pop_event_cnt = 0; - -} - -void halbtc8723b2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - boolean wifi_connected = false; - boolean low_pwr_disable = true; - boolean scan = false, link = false, roam = false; - boolean wifi_busy = false; - - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - - if (coex_sta->bt_abnormal_scan) { - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 23); - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - } else if (scan || link || roam) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link process + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 7); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - } else if (wifi_connected) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 7); - - if (wifi_busy) - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 3); - else - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi no-link + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - } - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - /* - coex_dm->need_recover0x948 = true; - coex_dm->backup0x948 = btcoexist->btc_read_4byte(btcoexist, 0x948); - - halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_AUX, false, false); - */ -} - - -void halbtc8723b2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist) -{ - u32 u32tmp; - u8 u8tmpa, u8tmpb; - - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 15); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n", - u32tmp, u8tmpa, u8tmpb); - BTC_TRACE(trace_buf); -} - -boolean halbtc8723b2ant_action_wifi_idle_process(IN struct btc_coexist - *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u8 ap_num = 0; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - /* wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES-coex_dm->switch_thres_offset-coex_dm->switch_thres_offset, 0); */ - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); - - /* define the office environment */ - if (BTC_RSSI_HIGH(wifi_rssi_state1) && - (coex_sta->hid_exist == true) && - (coex_sta->a2dp_exist == true)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi idle process for BT HID+A2DP exist!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - return true; - } - - halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x18); - return false; -} - - - -boolean halbtc8723b2ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - boolean bt_hs_on = false, low_pwr_disable = false; - boolean asus_8723b = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non-connected idle!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - common = true; - } else { - if (BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, - false, false, 0x8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - halbtc8723b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 0xb); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, - false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else if (BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status) { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (bt_hs_on) - return false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, - false, false, 0x8); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - halbtc8723b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 0xb); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - /* btcoexist->btc_get(btcoexist, - BTC_GET_BL_IS_ASUS_8723B, &asus_8723b); - if (!asus_8723b) - common = false; - else - common = halbtc8723b2ant_action_wifi_idle_process( - btcoexist); */ - common = false; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - /* common = false; */ - common = halbtc8723b2ant_action_wifi_idle_process( - btcoexist); - } - } - } - - return common; -} -void halbtc8723b2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, - IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0; - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - { - if (sco_hid) { - if (tx_pause) { - if (max_interval == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } else if (max_interval == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (max_interval == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } else { - if (max_interval == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } else if (max_interval == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (max_interval == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } else { - if (tx_pause) { - if (max_interval == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (max_interval == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (max_interval == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } - } else { - if (max_interval == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (max_interval == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (max_interval == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } - } - } - } - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* acquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - - if ((coex_sta->low_priority_tx) > 1050 || - (coex_sta->low_priority_rx) > 1250) - retry_count++; - - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) {/* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ - if (wait_count <= 2) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ - if (wait_count == 1) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (max_interval == 1) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 13); - coex_dm->ps_tdma_du_adj_type = 13; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 71); - coex_dm->ps_tdma_du_adj_type = 71; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 71); - coex_dm->ps_tdma_du_adj_type = - 71; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } - } - } - } else if (max_interval == 2) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } - } - } - } else if (max_interval == 3) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8723b2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8723b2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } - } - } - - /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ - /* then we have to adjust it back to the previous record one. */ - if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", - coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (!scan && !link && !roam) - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); - BTC_TRACE(trace_buf); - } - } -} - -/* SCO only or SCO+PAN(HS) */ -void halbtc8723b2ant_action_sco(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for SCO quality at 11b/g mode */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else /* for SCO quality & wifi performance balance at 11n mode */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); /* for voice quality */ - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - true, 0x4); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - true, 0x4); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - true, 0x4); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - true, 0x4); - } - } -} - - -void halbtc8723b2ant_action_hid(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - u32 wifi_bw; - - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - else /* for HID quality & wifi performance balance at 11n mode */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9); - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - else - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8723b2ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - u8 ap_num = 0; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); - - /* define the office environment */ - if ((ap_num >= 10) && BTC_RSSI_HIGH(wifi_rssi_state1) && - BTC_RSSI_HIGH(bt_rssi_state)) { - /* dbg_print(" AP#>10(%d)\n", ap_num); */ - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - true, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - true, 0x18); - } - return; - - } - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - } - - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, false, - 1); - else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, true, 1); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8723b2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - } - - halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, true, 2); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8723b2ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 10); - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - } - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); - else - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - - -/* PAN(HS) only */ -void halbtc8723b2ant_action_pan_hs(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* PAN(EDR)+A2DP */ -void halbtc8723b2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u8 ap_num = 0; - u32 wifi_bw; - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &ap_num); - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 12); - - if (ap_num < 10) - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, - false, 1); - else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, - false, 3); - - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - if (ap_num < 10) - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, - true, 1); - else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, - true, 3); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8723b2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 14); - } - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (BTC_WIFI_BW_HT40 == wifi_bw) { - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 3); - /* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x780); - } else { - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 6); - /* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - } - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 2); - } else { - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - /* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 2); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* HID+A2DP+PAN(EDR) */ -void halbtc8723b2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 14); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, - true, 3); - else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, - false, 3); - } else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 3); - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8723b2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW, - prewifi_rssi_state1 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - u8 ap_num = 0; - - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 35); - - - wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, 15, 0); - /* bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0); */ - wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state1, 2, - BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 0); - bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 3, - BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES - - coex_dm->switch_thres_offset, 37); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &ap_num); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x5); - - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_LEGACY == wifi_bw) { - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - } else { - /* only 802.11N mode we have to dec bt power to 4 degree */ - if (BTC_RSSI_HIGH(bt_rssi_state)) { - /* need to check ap Number of Not */ - if (ap_num < 10) - halbtc8723b2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, 4); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, 2); - } else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - } - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } else { - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 14); - } - - if (BTC_RSSI_HIGH(bt_rssi_state)) { - if (ap_num < 10) - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, - false, 2); - - else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, - false, 3); - } else { - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 18); - btcoexist->btc_write_1byte(btcoexist, 0x456, 0x38); - btcoexist->btc_write_2byte(btcoexist, 0x42a, 0x0808); - btcoexist->btc_write_4byte(btcoexist, 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, 0x434, 0x01010000); - - if (ap_num < 10) - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, - true, 2); - - else - halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, - true, 3); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8723b2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8723b2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) -{ - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8723b2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); -} - -void halbtc8723b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - u32 num_of_wifi_link = 0; - u32 wifi_link_status = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean miracast_plus_bt = false; - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_bt_whck_test(btcoexist); - return; - } - - algorithm = halbtc8723b2ant_action_algorithm(btcoexist); - if (coex_sta->c2h_bt_inquiry_page && - (BT_8723B_2ANT_COEX_ALGO_PANHS != algorithm)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_bt_inquiry(btcoexist); - return; - } - - /* - if(coex_dm->need_recover0x948) - { - coex_dm->need_recover0x948 = false; - btcoexist->btc_write_4byte(btcoexist, 0x948, coex_dm->backup0x948); - } - */ - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under Link Process !!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_wifi_link_process(btcoexist); - return; - } - - /* for P2P */ - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) - miracast_plus_bt = true; - else - miracast_plus_bt = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8723b2ant_action_wifi_multi_port(btcoexist); - - return; - } - - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - coex_dm->cur_algorithm = algorithm; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", - coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - - if (halbtc8723b2ant_is_common_action(btcoexist)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant common.\n"); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - } else { - if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", - coex_dm->pre_algorithm, coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - } - switch (coex_dm->cur_algorithm) { - case BT_8723B_2ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_sco(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_hid(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_a2dp(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_pan_edr(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_pan_hs(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_pan_edr_hid(btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8723B_2ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_action_hid_a2dp(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_coex_all_off(btcoexist); - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8723b2ant_wifi_off_hw_cfg(IN struct btc_coexist *btcoexist) -{ - boolean is_in_mp_mode = false; - u8 h2c_parameter[2] = {0}; - u32 fw_ver = 0; - - /* set wlan_act to low */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x780); /* WiFi goto standby while GNT_BT 0-->1 */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - if (fw_ver >= 0x180000) { - /* Use H2C to set GNT_BT to HIGH */ - h2c_parameter[0] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, h2c_parameter); - } else - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE, - &is_in_mp_mode); - if (!is_in_mp_mode) - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x0); /* BT select s0/s1 is controlled by BT */ - else - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x1); /* BT select s0/s1 is controlled by WiFi */ -} - -void halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up) -{ - u8 u8tmp = 0; - u32 vendor; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor); - if (vendor == BTC_VENDOR_LENOVO) - coex_dm->switch_thres_offset = 0; - else if (vendor == BTC_VENDOR_ASUS) - coex_dm->switch_thres_offset = 0; - else - coex_dm->switch_thres_offset = 20; - - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - /* backup rf 0x1e value */ - coex_dm->bt_rf_0x1e_backup = - btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff); - - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* Antenna config */ - halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true, - false); - coex_sta->dis_ver_info_cnt = 0; - - /* PTA parameter */ - halbtc8723b2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - /* Enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, - 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); - - /* Give bt_coex_supported_version the default value */ - coex_sta->bt_coex_supported_version = 0; - -} - -/* ************************************************************ - * work around function start with wa_halbtc8723b2ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8723b2ant_ - * ************************************************************ */ -void ex_halbtc8723b2ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u16 u16tmp = 0x0; - u32 value = 0; - u32 u32tmp_1[4]; - - btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20); - - /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - - btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0); - - if (btcoexist->chip_interface == BTC_INTF_USB) { - /* fixed at S0 for USB interface */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - } else { - /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ - if (board_info->single_ant_path == 0) { - /* set to S1 */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - } - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, - &value); - } -} - -void ex_halbtc8723b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - if (btcoexist->chip_interface == BTC_INTF_USB) { - /* fixed at S0 for USB interface */ - u8tmp |= 0x1; /* antenna inverse */ - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - } else { - if (board_info->single_ant_path == 1) { - /* set to S0 */ - u8tmp |= 0x1; /* antenna inverse */ - } - - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384, - u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, - u8tmp); - } -} - -void ex_halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8723b2ant_init_hw_config(btcoexist, true); -} - -void ex_halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723b2ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8723b2ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u32 u32tmp[4]; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; - u32 fw_ver = 0, bt_patch_ver = 0; - u32 bt_coex_ver = 0; - static u8 pop_report_in_10s = 0; - u32 phyver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - - /* btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); */ - bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); - bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", - "CoexVer WL/ BT_Desired/ BT_Report", - glcoex_ver_date_8723b_2ant, glcoex_ver_8723b_2ant, - glcoex_ver_btdesired_8723b_2ant, - bt_coex_ver, - (bt_coex_ver == 0xff ? "Unknown" : - (bt_coex_ver >= glcoex_ver_btdesired_8723b_2ant ? - "Match" : "Mis-Match"))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", - "W_FW/ B_FW/ Phy/ Kt", - fw_ver, bt_patch_ver, phyver, - coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Abnormal scan", - (coex_sta->bt_abnormal_scan) ? "Yes" : "No"); - CL_PRINTF(cli_buf); - - pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); - CL_PRINTF(cli_buf); - - if (pop_report_in_10s >= 5) { - coex_sta->pop_event_cnt = 0; - pop_report_in_10s = 0; - } - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d / %d / %d / %d / %d / %d", - "SCO/HID/PAN/A2DP/NameReq/WHQL", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist, - coex_sta->c2h_bt_remote_name_req, - coex_sta->bt_whck_test); - CL_PRINTF(cli_buf); - - { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Role", - (bt_link_info->slave_role) ? "Slave" : "Master"); - CL_PRINTF(cli_buf); - } - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", - "A2DP Rate/Bitpool", - (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8723B_2ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8723b_2ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - /* Sw mechanism */ - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Sw mechanism] (before Manual)============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Sw mechanism]============"); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", - "SM1[ShRf/ LpRA/ LimDig]", - coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, - coex_dm->limited_dig); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", - "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", - coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, - coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); - CL_PRINTF(cli_buf); - - /* Fw mechanism */ - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Fw mechanism] (before Manual) ============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Fw mechanism]============"); - - ps_tdma_case = coex_dm->cur_ps_tdma; - - if (coex_dm->is_switch_to_1dot5_ant) - ps_tdma_case = ps_tdma_case + 100; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "On" : "Off"), - (coex_dm->auto_tdma_adjust ? "Adj" : "Fix")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Coex Table Type", - coex_sta->coex_table_type); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "DecBtPwr/ IgnWlanAct", - coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", - "RF-A, 0x1e initVal", - coex_dm->bt_rf_0x1e_backup); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x880); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x778/0x880[29:25]", - u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25); - CL_PRINTF(cli_buf); - - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x765); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x948/ 0x67[5] / 0x765", - u32tmp[0], ((u8tmp[0] & 0x20) >> 5), u8tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x92c); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x930); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x944); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]", - u32tmp[0] & 0x3, u32tmp[1] & 0xff, u32tmp[2] & 0x3); - CL_PRINTF(cli_buf); - - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x39); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x38[11]/0x40/0x4c[24:23]/0x64[0]", - ((u8tmp[0] & 0x8) >> 3), u8tmp[1], - ((u32tmp[0] & 0x01800000) >> 23), u8tmp[2] & 0x1); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xc50(dig)/0x49c(null-drop)", - u32tmp[0] & 0xff, u8tmp[0]); - CL_PRINTF(cli_buf); - - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_CCK); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 1) - /* halbtc8723b2ant_monitor_bt_ctr(btcoexist); */ -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8723b2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - halbtc8723b2ant_wifi_off_hw_cfg(btcoexist); - halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - halbtc8723b2ant_coex_all_off(btcoexist); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; - halbtc8723b2ant_init_hw_config(btcoexist, false); - halbtc8723b2ant_init_coex_dm(btcoexist); - halbtc8723b2ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8723b2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8723b2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u32 u32tmp; - u8 u8tmpa, u8tmpb; - - - - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948); - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - if (BTC_SCAN_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, - false, false); - } else if (BTC_SCAN_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n", - u32tmp, u8tmpa, u8tmpb); - BTC_TRACE(trace_buf); -} - -void ex_halbtc8723b2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_ASSOCIATE_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, - false, false); - } else if (BTC_ASSOCIATE_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8723b2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - u8 ap_num = 0; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, - false, false); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = 0x1; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else { - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &ap_num); - if (ap_num < 10) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); -} - -void ex_halbtc8723b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (type == BTC_PACKET_DHCP) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], DHCP Packet notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8723b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean bt_busy = false, limited_dig = false; - boolean wifi_connected = false; - - coex_sta->c2h_bt_info_req_sent = false; - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8723B_2ANT_MAX) - rsp_source = BT_INFO_SRC_8723B_2ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n"); - BTC_TRACE(trace_buf); - return; - } - - /* if 0xff, it means BT is under WHCK test */ - if (bt_info == 0xff) - coex_sta->bt_whck_test = true; - else - coex_sta->bt_whck_test = false; - - if (BT_INFO_SRC_8723B_2ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_remote_name_req = true; - else - coex_sta->c2h_bt_remote_name_req = false; - - if (coex_sta->bt_info_c2h[rsp_source][1] == 0x49) { - coex_sta->a2dp_bit_pool = - coex_sta->bt_info_c2h[rsp_source][6]; - } else - coex_sta->a2dp_bit_pool = 0; - - coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] - & 0x40); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, - &coex_sta->bt_tx_rx_mask); - if (coex_sta->bt_tx_rx_mask) { - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */ - /* BT TRx mask off */ - btcoexist->btc_set_bt_trx_mask(btcoexist, 0); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT TRx Mask off for BT Info Notify\n"); - BTC_TRACE(trace_buf); -#if 0 - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x3c, 0x01); -#endif - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8723b2ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8723b2ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if ((coex_sta->bt_info_ext & BIT(3))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, - false); - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - } -#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8723b2ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8723B_2ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8723B_2ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8723B_2ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8723B_2ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8723B_2ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8723B_2ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - - if ((coex_sta->hid_exist == false) && - (coex_sta->c2h_bt_inquiry_page == false) && - (coex_sta->sco_exist == false)) { - if (coex_sta->high_priority_tx + - coex_sta->high_priority_rx >= 160) { - coex_sta->hid_exist = true; - bt_info = bt_info | 0x28; - } - } - } - - halbtc8723b2ant_update_bt_link_info(btcoexist); - - if (!(bt_info & BT_INFO_8723B_2ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8723B_2ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8723B_2ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8723B_2ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8723B_2ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8723B_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8723B_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { - bt_busy = true; - limited_dig = true; - } else { - bt_busy = false; - limited_dig = false; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - coex_dm->limited_dig = limited_dig; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); - - halbtc8723b2ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8723b2ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723b2ant_wifi_off_hw_cfg(btcoexist); - /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */ - /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); */ /*BT goto standby while GNT_BT 1-->0 */ - halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8723b2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); -} - -void ex_halbtc8723b2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_init_hw_config(btcoexist, false); - halbtc8723b2ant_init_coex_dm(btcoexist); - halbtc8723b2ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8723b2ant_periodical(IN struct btc_coexist *btcoexist) -{ - u32 bt_patch_ver; - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ==========================Periodical===========================\n"); - BTC_TRACE(trace_buf); - if (coex_sta->dis_ver_info_cnt <= 5) { - coex_sta->dis_ver_info_cnt += 1; - if (coex_sta->dis_ver_info_cnt == 3) { - /* Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set GNT_BT control by PTA\n"); - BTC_TRACE(trace_buf); - halbtc8723b2ant_set_ant_path(btcoexist, - BTC_ANT_WIFI_AT_MAIN, false, false); - } - } - - if (((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) && (!coex_sta->bt_disabled)) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, &coex_sta->bt_coex_supported_version); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; - -#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 0) - halbtc8723b2ant_query_bt_info(btcoexist); - halbtc8723b2ant_monitor_bt_enable_disable(btcoexist); -#else - halbtc8723b2ant_monitor_bt_ctr(btcoexist); - halbtc8723b2ant_monitor_wifi_ctr(btcoexist); - - /* for some BT speaker that Hi-Pri pkt appear begore start play, this will cause HID exist */ - if ((coex_sta->high_priority_tx + coex_sta->high_priority_rx < 50) && - (bt_link_info->hid_exist == true)) - bt_link_info->hid_exist = false; - - if (halbtc8723b2ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust) - halbtc8723b2ant_run_coexist_mechanism(btcoexist); -#endif -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ - - diff --git a/hal/btc/halbtc8723b2ant.h b/hal/btc/halbtc8723b2ant.h deleted file mode 100644 index fb6149a..0000000 --- a/hal/btc/halbtc8723b2ant.h +++ /dev/null @@ -1,231 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8723B_SUPPORT == 1) -/* ******************************************* - * The following is for 8723B 2Ant BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8723B_2ANT 1 - - -#define BT_INFO_8723B_2ANT_B_FTP BIT(7) -#define BT_INFO_8723B_2ANT_B_A2DP BIT(6) -#define BT_INFO_8723B_2ANT_B_HID BIT(5) -#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8723B_2ANT_B_CONNECTION BIT(0) - -#define BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT 2 - - -#define BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 /* WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */ -#define BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES 46 /* BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */ - -enum bt_info_src_8723b_2ant { - BT_INFO_SRC_8723B_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8723B_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8723B_2ANT_MAX -}; - -enum bt_8723b_2ant_bt_status { - BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8723B_2ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8723B_2ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8723B_2ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8723B_2ANT_BT_STATUS_MAX -}; - -enum bt_8723b_2ant_coex_algo { - BT_8723B_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8723B_2ANT_COEX_ALGO_SCO = 0x1, - BT_8723B_2ANT_COEX_ALGO_HID = 0x2, - BT_8723B_2ANT_COEX_ALGO_A2DP = 0x3, - BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8723B_2ANT_COEX_ALGO_PANEDR = 0x5, - BT_8723B_2ANT_COEX_ALGO_PANHS = 0x6, - BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8723B_2ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8723B_2ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8723b_2ant { - /* fw mechanism */ - u8 pre_bt_dec_pwr_lvl; - u8 cur_bt_dec_pwr_lvl; - u8 pre_fw_dac_swing_lvl; - u8 cur_fw_dac_swing_lvl; - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean reset_tdma_adjust; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - - /* sw mechanism */ - boolean pre_rf_rx_lpf_shrink; - boolean cur_rf_rx_lpf_shrink; - u32 bt_rf_0x1e_backup; - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - boolean pre_dac_swing_on; - u32 pre_dac_swing_lvl; - boolean cur_dac_swing_on; - u32 cur_dac_swing_lvl; - boolean pre_adc_back_off; - boolean cur_adc_back_off; - boolean pre_agc_table_en; - boolean cur_agc_table_en; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - boolean need_recover0x948; - u32 backup0x948; - - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - boolean is_switch_to_1dot5_ant; - u8 switch_thres_offset; -}; - -struct coex_sta_8723b_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - boolean bt_abnormal_scan; - boolean under_lps; - boolean under_ips; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - u8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8723B_2ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_2ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_remote_name_req; - u8 bt_retry_cnt; - u8 bt_info_ext; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; - - u32 bt_coex_supported_version; - - u8 coex_table_type; - boolean force_lps_on; - - u8 dis_ver_info_cnt; - - u8 a2dp_bit_pool; - u8 cut_version; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8723b2ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8723b2ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8723b2ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8723b2ant_display_coex_info(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8723b2ant_power_on_setting(btcoexist) -#define ex_halbtc8723b2ant_pre_load_firmware(btcoexist) -#define ex_halbtc8723b2ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8723b2ant_init_coex_dm(btcoexist) -#define ex_halbtc8723b2ant_ips_notify(btcoexist, type) -#define ex_halbtc8723b2ant_lps_notify(btcoexist, type) -#define ex_halbtc8723b2ant_scan_notify(btcoexist, type) -#define ex_halbtc8723b2ant_connect_notify(btcoexist, type) -#define ex_halbtc8723b2ant_media_status_notify(btcoexist, type) -#define ex_halbtc8723b2ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8723b2ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8723b2ant_halt_notify(btcoexist) -#define ex_halbtc8723b2ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8723b2ant_periodical(btcoexist) -#define ex_halbtc8723b2ant_display_coex_info(btcoexist) - -#endif - -#endif - diff --git a/hal/btc/halbtc8723bwifionly.c b/hal/btc/halbtc8723bwifionly.c deleted file mode 100644 index d1a8361..0000000 --- a/hal/btc/halbtc8723bwifionly.c +++ /dev/null @@ -1,82 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -#include "mp_precomp.h" - - -VOID -ex_hal8723b_wifi_only_hw_config( - IN struct wifi_only_cfg *pwifionlycfg - ) -{ - struct wifi_only_haldata *pwifionly_haldata = &pwifionlycfg->haldata_info; - - - halwifionly_write1byte(pwifionlycfg, 0x778, 0x3); /* Set pta for wifi first priority, 0x1 need to reference pta table to determine wifi and bt priority */ - halwifionly_bitmaskwrite1byte(pwifionlycfg, 0x40, 0x20, 0x1); - - /* Set Antenna path to Wifi */ - halwifionly_write2byte(pwifionlycfg, 0x0765, 0x8); /* Set pta for wifi first priority, 0x0 need to reference pta table to determine wifi and bt priority */ - halwifionly_write2byte(pwifionlycfg, 0x076e, 0xc); - - halwifionly_write4byte(pwifionlycfg, 0x000006c0, 0xaaaaaaaa); /* pta table, 0xaaaaaaaa means wifi is higher priority than bt */ - halwifionly_write4byte(pwifionlycfg, 0x000006c4, 0xaaaaaaaa); - - halwifionly_bitmaskwrite1byte(pwifionlycfg, 0x67, 0x20, 0x1); /* BT select s0/s1 is controlled by WiFi */ - - /* 0x948 setting */ - if (pwifionlycfg->chip_interface == WIFIONLY_INTF_PCI) { - /* HP Foxconn NGFF at S0 - not sure HP pg correct or not(EEPROMBluetoothSingleAntPath), so here we just write - 0x948=0x280 for HP HW id NIC. */ - if (pwifionly_haldata->customer_id == CUSTOMER_HP_1) { - halwifionly_write4byte(pwifionlycfg, 0x948, 0x280); - halwifionly_phy_set_rf_reg(pwifionlycfg, 0, 0x1, 0xfffff, 0x0); /* WiFi TRx Mask off */ - return; - } - } - - if (pwifionly_haldata->efuse_pg_antnum == 2) { - halwifionly_write4byte(pwifionlycfg, 0x948, 0x0); - } else { - /* 3Attention !!! For 8723BU !!!! - For 8723BU single ant case: jira [USB-1237] - Because of 8723BU S1 has HW problem, we only can use S0 instead. - Whether Efuse 0xc3 [6] is 0 or 1, we should always use S0 and write 0x948 to 80/280 - - -------------------------------------------------- - BT Team : - When in Single Ant case, Reg[0x948] has two case : 0x80 or 0x200 - When in Two Ant case, Reg[0x948] has two case : 0x280 or 0x0 - Efuse 0xc3 [6] Antenna Path - 0xc3 [6] = 0 ==> S1 ==> 0x948 = 0/40/200 - 0xc3 [6] = 1 ==> S0 ==> 0x948 = 80/240/280 */ - - if (pwifionlycfg->chip_interface == WIFIONLY_INTF_USB) - halwifionly_write4byte(pwifionlycfg, 0x948, 0x80); - else { - if (pwifionly_haldata->efuse_pg_antpath == 0) - halwifionly_write4byte(pwifionlycfg, 0x948, 0x0); - else - halwifionly_write4byte(pwifionlycfg, 0x948, 0x280); - } - - } - - - /* after 8723B F-cut, TRx Mask should be set when 0x948=0x0 or 0x280 - PHY_SetRFReg(Adapter, 0, 0x1, 0xfffff, 0x780); WiFi TRx Mask on */ - halwifionly_phy_set_rf_reg(pwifionlycfg, 0, 0x1, 0xfffff, 0x0); /*WiFi TRx Mask off */ - -} diff --git a/hal/btc/halbtc8723bwifionly.h b/hal/btc/halbtc8723bwifionly.h deleted file mode 100644 index 9d38664..0000000 --- a/hal/btc/halbtc8723bwifionly.h +++ /dev/null @@ -1,22 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -#ifndef __INC_HAL8723BWIFIONLYHWCFG_H -#define __INC_HAL8723BWIFIONLYHWCFG_H - -VOID -ex_hal8723b_wifi_only_hw_config( - IN struct wifi_only_cfg *pwifionlycfg - ); -#endif diff --git a/hal/btc/halbtc8723d1ant.c b/hal/btc/halbtc8723d1ant.c deleted file mode 100644 index 5340c1b..0000000 --- a/hal/btc/halbtc8723d1ant.c +++ /dev/null @@ -1,6276 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for RTL8723D Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8723D_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8723d_1ant glcoex_dm_8723d_1ant; -static struct coex_dm_8723d_1ant *coex_dm = &glcoex_dm_8723d_1ant; -static struct coex_sta_8723d_1ant glcoex_sta_8723d_1ant; -static struct coex_sta_8723d_1ant *coex_sta = &glcoex_sta_8723d_1ant; -static struct psdscan_sta_8723d_1ant gl_psd_scan_8723d_1ant; -static struct psdscan_sta_8723d_1ant *psd_scan = &gl_psd_scan_8723d_1ant; - - -const char *const glbt_info_src_8723d_1ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; -/* ************************************************************ - * BtCoex Version Format: - * 1. date : glcoex_ver_date_XXXXX_1ant - * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant - * 3. BtCoexVersion : glcoex_ver_btdesired_XXXXX_1ant - * 4. others : glcoex_ver_XXXXXX_XXXXX_1ant - * - * Variable should be indicated IC and Antenna numbers !!! - * Please strictly follow this order and naming style !!! - * - * ************************************************************ */ -u32 glcoex_ver_date_8723d_1ant = 20161108; -u32 glcoex_ver_8723d_1ant = 0x10; -u32 glcoex_ver_btdesired_8723d_1ant = 0x10; - - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8723d1ant_ - * ************************************************************ */ -u8 halbtc8723d1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8723d1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8723d1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8723d1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8723d1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8723d1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8723d1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8723d1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8723d1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8723d1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8723d1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8723d1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8723d1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8723d1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8723d1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WL query BT info!!\n"); - BTC_TRACE(trace_buf); -} - -void halbtc8723d1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, - cnt_autoslot_hang = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ - /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - - if (coex_sta->high_priority_rx >= 15) { - if (cnt_overhead < 3) - cnt_overhead++; - - if (cnt_overhead == 3) - coex_sta->is_hiPri_rx_overhead = true; - } else { - if (cnt_overhead > 0) - cnt_overhead--; - - if (cnt_overhead == 0) - coex_sta->is_hiPri_rx_overhead = false; - } - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", - reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); - - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - if ((coex_sta->low_priority_tx > 1150) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - if ((coex_sta->low_priority_rx >= 1150) && - (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) - && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && - (coex_sta->bt_link_exist)) { - if (cnt_slave >= 2) { - bt_link_info->slave_role = true; - cnt_slave = 2; - } else - cnt_slave++; - } else { - if (cnt_slave == 0) { - bt_link_info->slave_role = false; - cnt_slave = 0; - } else - cnt_slave--; - - } - - if (coex_sta->is_tdma_btautoslot) { - if ((coex_sta->low_priority_tx >= 1300) && - (coex_sta->low_priority_rx <= 150)) { - if (cnt_autoslot_hang >= 2) { - coex_sta->is_tdma_btautoslot_hang = true; - cnt_autoslot_hang = 2; - } else - cnt_autoslot_hang++; - } else { - if (cnt_autoslot_hang == 0) { - coex_sta->is_tdma_btautoslot_hang = false; - cnt_autoslot_hang = 0; - } else - cnt_autoslot_hang--; - } - } - - if (!coex_sta->bt_disabled) { - - if ((coex_sta->high_priority_tx == 0) && - (coex_sta->high_priority_rx == 0) && - (coex_sta->low_priority_tx == 0) && - (coex_sta->low_priority_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8723d1ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; - } - } - } - -} - -void halbtc8723d1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ -#if 1 - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false, - wifi_scan = false; - boolean bt_idle = false, wl_idle = false; - static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, - wl_noisy_count1 = 3, wl_noisy_count2 = 0; - u32 total_cnt, reg_val1, reg_val2, cck_cnt; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - - coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_VHT); - - cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; - - if (cck_cnt > 250) { - if (wl_noisy_count2 < 3) - wl_noisy_count2++; - - if (wl_noisy_count2 == 3) { - wl_noisy_count0 = 0; - wl_noisy_count1 = 0; - } - } else if (cck_cnt < 50) { - if (wl_noisy_count0 < 3) - wl_noisy_count0++; - - if (wl_noisy_count0 == 3) { - wl_noisy_count1 = 0; - wl_noisy_count2 = 0; - } - } else { - if (wl_noisy_count1 < 3) - wl_noisy_count1++; - - if (wl_noisy_count1 == 3) { - wl_noisy_count0 = 0; - wl_noisy_count2 = 0; - } - } - - if (wl_noisy_count2 == 3) - coex_sta->wl_noisy_level = 2; - else if (wl_noisy_count1 == 3) - coex_sta->wl_noisy_level = 1; - else - coex_sta->wl_noisy_level = 0; - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht; - - if ((coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 3) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = true; - - coex_sta->pre_ccklock = coex_sta->cck_lock; - -#endif -} - -void halbtc8723d1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - boolean bt_busy = false; - - - coex_sta->num_of_profile = 0; - - /* set link exist status */ - if (!(coex_sta->bt_info & BT_INFO_8723D_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_FTP) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = false; - - if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_A2DP) { - coex_sta->a2dp_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = false; - - if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_HID) { - coex_sta->hid_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = false; - - if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) { - coex_sta->sco_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = false; - - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->acl_busy = coex_sta->acl_busy; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; - - if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_INQ_PAGE) { - coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_INQ_PAGE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); - } else if (!(coex_sta->bt_info & BT_INFO_8723D_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - } else if (coex_sta->bt_info == BT_INFO_8723D_1ANT_B_CONNECTION) { - /* connection exists but no busy */ - coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - } else if (((coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) || - (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_BUSY)) && - (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_ACL_BUSY)) { - coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); - } else if ((coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) || - (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - } else if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - } else { - coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - } - - BTC_TRACE(trace_buf); - - if ((BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); -} - - -void halbtc8723d1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = - 0x1; /* enable BT AFH skip WL channel for 8723d because BT Rx LO interference */ - /* h2c_parameter[0] = 0x0; */ - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); - -} - -u8 halbtc8723d1ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8723D_1ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_1ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_1ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_1ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_1ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8723d1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8723d1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8723d1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8723d1ant_set_fw_low_penalty_ra(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ -#if 1 - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -#endif -} - -void halbtc8723d1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ -#if 1 - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - - halbtc8723d1ant_set_fw_low_penalty_ra(btcoexist, - coex_dm->cur_low_penalty_ra); - -#if 0 - if (low_penalty_ra) - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15); - else - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); -#endif - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; - -#endif - -} - -void halbtc8723d1ant_write_score_board( - IN struct btc_coexist *btcoexist, - IN u16 bitpos, - IN boolean state -) -{ - - static u16 originalval = 0x8002; - - if (state) - originalval = originalval | bitpos; - else - originalval = originalval & (~bitpos); - - - btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); - -} - -void halbtc8723d1ant_read_score_board( - IN struct btc_coexist *btcoexist, - IN u16 *score_board_val -) -{ - - *score_board_val = (btcoexist->btc_read_2byte(btcoexist, - 0xaa)) & 0x7fff; -} - -void halbtc8723d1ant_post_state_to_bt( - IN struct btc_coexist *btcoexist, - IN u16 type, - IN boolean state -) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8723d1ant_post_state_to_bt: type = %d, state =%d\n", - type, state); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_write_score_board(btcoexist, (u16) type, state); -} - -boolean halbtc8723d1ant_is_wifibt_status_changed(IN struct btc_coexist - *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false, pre_bt_off = false, pre_bt_slave = false; - static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (coex_sta->bt_disabled != pre_bt_off) { - pre_bt_off = coex_sta->bt_disabled; - - if (coex_sta->bt_disabled) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - - BTC_TRACE(trace_buf); - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - coex_sta->bt_ble_scan_type = 0; - coex_sta->bt_ble_scan_para[0] = 0; - coex_sta->bt_ble_scan_para[1] = 0; - coex_sta->bt_ble_scan_para[2] = 0; - coex_sta->bt_reg_vendor_ac = 0xffff; - coex_sta->bt_reg_vendor_ae = 0xffff; - return true; - } - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - - if (wifi_busy) - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_UNDERTEST, true); - else - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_UNDERTEST, false); - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { - pre_wl_noisy_level = coex_sta->wl_noisy_level; - return true; - } - } - - if (!coex_sta->bt_disabled) { - if (coex_sta->hid_busy_num != pre_hid_busy_num) { - pre_hid_busy_num = coex_sta->hid_busy_num; - return true; - } - } - - if (bt_link_info->slave_role != pre_bt_slave) { - pre_bt_slave = bt_link_info->slave_role; - return true; - } - - return false; -} - -void halbtc8723d1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - u16 u16tmp; - - /* This function check if bt is disabled */ -#if 0 - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - - -#else - - /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */ - halbtc8723d1ant_read_score_board(btcoexist, &u16tmp); - - bt_active = u16tmp & BIT(1); - - -#endif - - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } else { - - bt_disable_cnt++; - if (bt_disable_cnt >= 2) { - bt_disabled = true; - bt_disable_cnt = 2; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } - - if (bt_disabled) - halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); - else - halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true); - - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - } - -} - - - -void halbtc8723d1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, - boolean isenable) -{ -#if BT_8723D_1ANT_COEX_DBG - if (isenable) { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); - - /* enable GNT_BT to GPIO debug */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0); - - /* 0x48[20] = 0 for GPIO14 = GNT_WL*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x0); - /* 0x40[17] = 0 for GPIO14 = GNT_WL*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, 0x02, 0x0); - - /* 0x66[9] = 0 for GPIO15 = GNT_B T*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x02, 0x0); - /* 0x66[7] = 0 - for GPIO15 = GNT_BT*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, 0x80, 0x0); - /* 0x8[8] = 0 for GPIO15 = GNT_BT*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x9, 0x1, 0x0); - - /* BT Vendor Reg 0x76[0] = 0 for GPIO15 = GNT_BT, this is not set here*/ - } else { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); - - /* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1); - - /* 0x48[20] = 0 for GPIO14 = GNT_WL*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x1); - } - -#endif -} - -u32 halbtc8723d1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, - IN u16 reg_addr) -{ - u32 j = 0; - - - /* wait for ready bit before access 0x7c0 */ - btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr); - - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x7c3)&BIT(5)) == 0) && - (j < BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - return btcoexist->btc_read_4byte(btcoexist, - 0x7c8); /* get read data */ - -} - -void halbtc8723d1ant_ltecoex_indirect_write_reg(IN struct btc_coexist - *btcoexist, - IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) -{ - u32 val, i = 0, j = 0, bitpos = 0; - - - if (bit_mask == 0x0) - return; - if (bit_mask == 0xffffffff) { - btcoexist->btc_write_4byte(btcoexist, 0x7c4, - reg_value); /* put write data */ - - /* wait for ready bit before access 0x7c0 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x7c3)&BIT(5)) == 0) && - (j < BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x7c0, - 0xc00F0000 | reg_addr); - } else { - for (i = 0; i <= 31; i++) { - if (((bit_mask >> i) & 0x1) == 0x1) { - bitpos = i; - break; - } - } - - /* read back register value before write */ - val = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - reg_addr); - val = (val & (~bit_mask)) | (reg_value << bitpos); - - btcoexist->btc_write_4byte(btcoexist, 0x7c4, - val); /* put write data */ - - /* wait for ready bit before access 0x7c0 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x7c3)&BIT(5)) == 0) && - (j < BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x7c0, - 0xc00F0000 | reg_addr); - - } - -} - -void halbtc8723d1ant_ltecoex_enable(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 val; - - val = (enable) ? 1 : 0; - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, - val); /* 0x38[7] */ - -} - -void halbtc8723d1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, - IN boolean wifi_control) -{ - u8 val; - - val = (wifi_control) ? 1 : 0; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, - val); /* 0x70[26] */ - -} - -void halbtc8723d1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, val_orig = 0; - - if (!sw_control) - val = 0x0; - else if (state & 0x1) - val = 0x3; - else - val = 0x1; - - val_orig = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - switch (control_block) { - case BT_8723D_1ANT_GNT_BLOCK_RFC_BB: - default: - val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff); - break; - case BT_8723D_1ANT_GNT_BLOCK_RFC: - val = (val << 14) | (val_orig & 0xffff3fff); - break; - case BT_8723D_1ANT_GNT_BLOCK_BB: - val = (val << 10) | (val_orig & 0xfffff3ff); - break; - } - - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); -} - - -void halbtc8723d1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, val_orig = 0; - - if (!sw_control) - val = 0x0; - else if (state & 0x1) - val = 0x3; - else - val = 0x1; - - val_orig = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - switch (control_block) { - case BT_8723D_1ANT_GNT_BLOCK_RFC_BB: - default: - val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff); - break; - case BT_8723D_1ANT_GNT_BLOCK_RFC: - val = (val << 12) | (val_orig & 0xffffcfff); - break; - case BT_8723D_1ANT_GNT_BLOCK_BB: - val = (val << 8) | (val_orig & 0xfffffcff); - break; - } - - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, - 0xffffffff, val); -} - - -void halbtc8723d1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u16 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8723D_1ANT_CTT_WL_VS_LTE: - reg_addr = 0xa0; - break; - case BT_8723D_1ANT_CTT_BT_VS_LTE: - reg_addr = 0xa4; - break; - } - - if (reg_addr != 0x0000) - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ - - -} - - -void halbtc8723d1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u8 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8723D_1ANT_LBTT_WL_BREAK_LTE: - reg_addr = 0xa8; - break; - case BT_8723D_1ANT_LBTT_BT_BREAK_LTE: - reg_addr = 0xac; - break; - case BT_8723D_1ANT_LBTT_LTE_BREAK_WL: - reg_addr = 0xb0; - break; - case BT_8723D_1ANT_LBTT_LTE_BREAK_BT: - reg_addr = 0xb4; - break; - } - - if (reg_addr != 0x0000) - halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ - -} - -void halbtc8723d1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 interval, - IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, - IN u8 val0x6c4_b3) -{ - static u8 pre_h2c_parameter[6] = {0}; - u8 cur_h2c_parameter[6] = {0}; - u8 i, match_cnt = 0; - - cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ - - cur_h2c_parameter[1] = interval; - cur_h2c_parameter[2] = val0x6c4_b0; - cur_h2c_parameter[3] = val0x6c4_b1; - cur_h2c_parameter[4] = val0x6c4_b2; - cur_h2c_parameter[5] = val0x6c4_b3; - - if (!force_exec) { - for (i = 1; i <= 5; i++) { - if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) - break; - - match_cnt++; - } - - if (match_cnt == 5) - return; - } - - for (i = 1; i <= 5; i++) - pre_h2c_parameter[i] = cur_h2c_parameter[i]; - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); -} - - -void halbtc8723d1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8723d1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - - halbtc8723d1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8723d1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - u32 break_table; - u8 select_table; - - coex_sta->coex_table_type = type; - - if (coex_sta->concurrent_rx_mode_on == true) { - break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ - select_table = - 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ - } else { - break_table = 0xffffff; - select_table = 0x3; - } - - switch (type) { - case 0: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, break_table, - select_table); - break; - case 1: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 2: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0xaa5a5a5a, 0xaa5a5a5a, break_table, - select_table); - break; - case 3: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 4: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 5: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, break_table, - select_table); - break; - case 6: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 7: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, break_table, - select_table); - break; - case 8: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xaaaaaaaa, break_table, - select_table); - break; - case 9: - halbtc8723d1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaaaa5aaa, break_table, - select_table); - break; - default: - break; - } -} - -void halbtc8723d1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8723d1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8723d1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8723d1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8723d1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8723d1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8723d1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - /*halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - /*halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8);*/ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8723d1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - coex_sta->force_lps_on = false; - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - - break; - case BTC_PS_LPS_ON: - coex_sta->force_lps_on = true; - halbtc8723d1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8723d1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - - break; - case BTC_PS_LPS_OFF: - coex_sta->force_lps_on = false; - halbtc8723d1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - - break; - default: - break; - } -} - - -void halbtc8723d1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - if (byte5 & BIT(2)) - coex_sta->is_tdma_btautoslot = true; - else - coex_sta->is_tdma_btautoslot = false; - - /* release bt-auto slot for auto-slot hang is detected!! */ - if (coex_sta->is_tdma_btautoslot) - if ((coex_sta->is_tdma_btautoslot_hang) || - (bt_link_info->slave_role)) - byte5 = byte5 & 0xfb; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - - halbtc8723d1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - } - } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - - halbtc8723d1ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } else { - halbtc8723d1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, - 0x0); - } - - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - - -void halbtc8723d1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - struct btc_board_info *board_info = &btcoexist->board_info; - boolean wifi_busy = false; - static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; - static boolean pre_wifi_busy = false; - - -#if BT_8723D_1ANT_ANTDET_ENABLE - - if (board_info->btdm_ant_num_by_ant_det == 2) { -#if 0 - if (turn_on) - type = type + - 100; -#endif - } - -#endif - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (wifi_busy != pre_wifi_busy) { - force_exec = true; - pre_wifi_busy = wifi_busy; - } - - /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist)) - psTdmaByte4Modify = 0x1; - else - psTdmaByte4Modify = 0x0; - - if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { - - force_exec = true; - pre_psTdmaByte4Modify = psTdmaByte4Modify; - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - - if (turn_on) { - switch (type) { - default: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x11); - break; - case 3: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x3a, 0x03, 0x10, 0x50); - break; - case 4: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x21, 0x03, 0x10, 0x50); - break; - case 5: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x03, 0x11, 0x11); - break; - case 6: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x20, 0x03, 0x11, 0x11); - break; - case 7: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x54 | - psTdmaByte4Modify); - break; - case 8: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x54 | - psTdmaByte4Modify); - break; - case 9: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x55, 0x10, 0x03, 0x10, 0x54 | - psTdmaByte4Modify); - break; - case 10: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); - break; - case 11: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x65, 0x25, 0x03, 0x11, 0x11 | - psTdmaByte4Modify); - break; - case 12: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x55, 0x30, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 13: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x25, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 14: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x15, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 15: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x20, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 16: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x15 | - psTdmaByte4Modify); - break; - case 17: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x14); - break; - case 18: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x30, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 19: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x03, 0x11, 0x10); - break; - case 20: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); - break; - case 21: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); - break; - case 22: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x25, 0x03, 0x11, 0x10); - break; - case 23: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x10); - break; - case 27: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x15); - break; - case 32: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x11); - break; - case 33: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x10); - break; - case 57: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 58: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 67: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x10 | - psTdmaByte4Modify); - break; - /* 1-Ant to 2-Ant TDMA case */ - case 103: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x3a, 0x03, 0x70, 0x10); - break; - case 104: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x21, 0x03, 0x70, 0x10); - break; - case 105: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x15, 0x03, 0x71, 0x11); - break; - case 106: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x20, 0x03, 0x71, 0x11); - break; - case 107: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x10, 0x03, 0x70, 0x14 | - psTdmaByte4Modify); - break; - case 108: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x10, 0x03, 0x70, 0x14 | - psTdmaByte4Modify); - break; - case 113: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x25, 0x03, 0x70, 0x10 | - psTdmaByte4Modify); - break; - case 114: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x15, 0x03, 0x70, 0x10 | - psTdmaByte4Modify); - break; - case 115: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x20, 0x03, 0x70, 0x10 | - psTdmaByte4Modify); - break; - case 117: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x10, 0x03, 0x71, 0x14 | - psTdmaByte4Modify); - break; - case 119: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x15, 0x03, 0x71, 0x10); - break; - case 120: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x30, 0x03, 0x71, 0x10); - break; - case 121: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x30, 0x03, 0x71, 0x10); - break; - case 122: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x25, 0x03, 0x71, 0x10); - break; - case 132: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x35, 0x03, 0x71, 0x11); - break; - case 133: - halbtc8723d1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x35, 0x03, 0x71, 0x10); - break; - } - } else { - - /* disable PS tdma */ - switch (type) { - case 8: /* PTA Control */ - halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - break; - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - break; - case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */ - halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - - -void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, - IN u8 phase) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u32 cnt_bt_cal_chk = 0; - boolean is_in_mp_mode = false, is_hw_ant_div_on = false; - u8 u8tmp0 = 0, u8tmp1 = 0; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - u16 u16tmp0, u16tmp1 = 0; - -#if BT_8723D_1ANT_ANTDET_ENABLE - - if (ant_pos_type == BTC_ANT_PATH_PTA) { - if ((board_info->btdm_ant_det_finish) && - (board_info->btdm_ant_num_by_ant_det == 2)) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = BTC_ANT_PATH_WIFI; - else - ant_pos_type = BTC_ANT_PATH_BT; - } - } - -#endif - - u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - /* To avoid indirect access fail */ - if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { - force_exec = true; - coex_sta->gnt_error_cnt++; - } - -#if BT_8723D_1ANT_COEX_DBG - u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa); - u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948); - u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x73); - u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before Set Ant Pat)\n", - u8tmp0, u16tmp1, u8tmp1); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa = 0x%x(Before Set Ant Path)\n", - u32tmp1, u32tmp2, u16tmp0); - BTC_TRACE(trace_buf); -#endif - - coex_dm->cur_ant_pos_type = ant_pos_type; - - if (!force_exec) { - if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Skip Antenna Path Setup because no change!!**********\n"); - BTC_TRACE(trace_buf); - return; - } - } - - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; - - - switch (phase) { - case BT_8723D_1ANT_PHASE_COEX_POWERON: - /* Set Path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, - 0x80, 0x0); - - /* set Path control owner to WL at initial step */ - halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_1ANT_PCO_BTSIDE); - - /* set GNT_BT to SW high */ - halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW low */ - halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - coex_sta->run_time_state = false; - - break; - case BT_8723D_1ANT_PHASE_COEX_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8723d1ant_ltecoex_set_coex_table(btcoexist, - BT_8723D_1ANT_CTT_WL_VS_LTE, 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8723d1ant_ltecoex_set_coex_table(btcoexist, - BT_8723D_1ANT_CTT_BT_VS_LTE, 0xffff); - - /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ - while (cnt_bt_cal_chk <= 20) { - u8tmp0 = btcoexist->btc_read_1byte(btcoexist, - 0x49d); - cnt_bt_cal_chk++; - if (u8tmp0 & BIT(0)) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - delay_ms(50); - } else { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** WL is NOT calibrating (wait cnt=%d)**********\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - break; - } - } - - /* Set Path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, - 0x80, 0x1); - - /* set Path control owner to WL at initial step */ - halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_1ANT_PCO_WLSIDE); - - /* set GNT_BT to SW high */ - halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW low */ - halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - coex_sta->run_time_state = false; - break; - case BT_8723D_1ANT_PHASE_WLANONLY_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8723d1ant_ltecoex_set_coex_table(btcoexist, - BT_8723D_1ANT_CTT_WL_VS_LTE, 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8723d1ant_ltecoex_set_coex_table(btcoexist, - BT_8723D_1ANT_CTT_BT_VS_LTE, 0xffff); - - /* Set Path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, - 0x80, 0x1); - - /* set Path control owner to WL at initial step */ - halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_1ANT_PCO_WLSIDE); - - /* set GNT_BT to SW low */ - halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_LOW); - /* Set GNT_WL to SW high */ - halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_WIFI; - - coex_sta->run_time_state = false; - break; - case BT_8723D_1ANT_PHASE_WLAN_OFF: - /* Disable LTE Coex Function in WiFi side */ - halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0); - - /* Set Path control to BT */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, - 0x80, 0x0); - - /* set Path control owner to BT */ - halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_1ANT_PCO_BTSIDE); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - coex_sta->run_time_state = false; - break; - case BT_8723D_1ANT_PHASE_2G_RUNTIME: - - /* wait for WL/BT IQK finish, keep 0x38 = 0xff00 for WL IQK */ - while (cnt_bt_cal_chk <= 20) { - u8tmp0 = btcoexist->btc_read_1byte(btcoexist, - 0x1e6); - - u8tmp1 = btcoexist->btc_read_1byte(btcoexist, - 0x49d); - - cnt_bt_cal_chk++; - if ((u8tmp0 & BIT(0)) || (u8tmp1 & BIT(0))) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### WL or BT is IQK (wait cnt=%d)\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - delay_ms(50); - } else { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - break; - } - } - - - /* Set Path control to WL */ - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1); */ - - halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_1ANT_PCO_WLSIDE); - - /* set GNT_BT to PTA */ - halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8723D_1ANT_SIG_STA_SET_BY_HW); - /* Set GNT_WL to PTA */ - halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8723D_1ANT_SIG_STA_SET_BY_HW); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_PTA; - - coex_sta->run_time_state = true; - break; - case BT_8723D_1ANT_PHASE_BTMPMODE: - halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_1ANT_PCO_WLSIDE); - - /* Set Path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, - 0x80, 0x1); - - /* set GNT_BT to high */ - halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to low */ - halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_LOW); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - coex_sta->run_time_state = false; - break; - case BT_8723D_1ANT_PHASE_ANTENNA_DET: - halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_1ANT_PCO_WLSIDE); - - /* Set Path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, - 0x80, 0x1); - - /* set GNT_BT to high */ - halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to high */ - halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_1ANT_GNT_BLOCK_RFC_BB, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_1ANT_SIG_STA_SET_TO_HIGH); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - coex_sta->run_time_state = false; - - break; - } - - - is_hw_ant_div_on = board_info->ant_div_cfg; - - if ((is_hw_ant_div_on) && (phase != BT_8723D_1ANT_PHASE_ANTENNA_DET)) - - if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) - /* 0x948 = 0x200, 0x0 while antenna diversity */ - btcoexist->btc_write_2byte(btcoexist, 0x948, 0x100); - else /* 0x948 = 0x80, 0x0 while antenna diversity */ - btcoexist->btc_write_2byte(btcoexist, 0x948, 0x40); - - else if ((is_hw_ant_div_on == false) && - (phase != BT_8723D_1ANT_PHASE_WLAN_OFF)) { /* internal switch setting */ - - switch (ant_pos_type) { - - case BTC_ANT_PATH_WIFI: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - - btcoexist->btc_write_2byte( - btcoexist, 0x948, 0x0); - else - btcoexist->btc_write_2byte( - btcoexist, 0x948, 0x280); - - break; - case BTC_ANT_PATH_BT: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - - btcoexist->btc_write_2byte( - btcoexist, 0x948, 0x280); - else - btcoexist->btc_write_2byte( - btcoexist, 0x948, 0x0); - - break; - default: - case BTC_ANT_PATH_PTA: - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_2byte( - btcoexist, 0x948, - 0x200); - else - btcoexist->btc_write_2byte( - btcoexist, 0x948, 0x80); - break; - } - } - - -#if BT_8723D_1ANT_COEX_DBG - u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa); - u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948); - u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x73); - u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(After Set Ant Pat)\n", - u8tmp0, u16tmp1, u8tmp1); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa = 0x%x(After Set Ant Path)\n", - u32tmp1, u32tmp2, u16tmp0); - BTC_TRACE(trace_buf); -#endif - -} - - -boolean halbtc8723d1ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - common = true; - } else if (wifi_connected && - (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - common = true; - } else if (!wifi_connected && - (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - common = true; - } else if (wifi_connected && - (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - common = true; - } else if (!wifi_connected && - (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE != - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } - - common = false; - } - - return common; -} - - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8723d1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) -{ - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8723d1ant_action_bt_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8723d1ant_action_bt_relink(IN struct btc_coexist *btcoexist) -{ - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - coex_sta->bt_relink_downcount = 2; -} - -void halbtc8723d1ant_action_bt_idle(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_busy) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - } else { - /* if wl busy */ - if (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - } else { - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - } -} - -} - -void halbtc8723d1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, wifi_busy = false, bt_busy = false; - boolean wifi_scan = false, wifi_link = false, wifi_roam = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); - - - if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) - || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - - if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17); - else - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - } else if ((!wifi_connected) && (!wifi_scan)) { - - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (bt_link_info->pan_exist) { - - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); - - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - - if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) - || (coex_sta->wifi_is_high_pri_task)) - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - else - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } -} - - -void halbtc8723d1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, wifi_busy = false; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - - if (bt_link_info->sco_exist) { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 5); - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 5); - } else if (coex_sta->hid_busy_num >= 2) { - /*for 4/18 hid */ - /* if 11bg mode */ - if (wifi_bw == 0) { - - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 11); - } else { - - if (wifi_busy) { - - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 11); - } else { - - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 6); - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - - } - } - } else { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 6); - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - } -} - - -void halbtc8723d1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); -} - -void halbtc8723d1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - - if (!bt_link_info->pan_exist) - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - else - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8723d1ant_action_wifi_linkscan_process(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - if (bt_link_info->pan_exist) { - - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 27); - - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } -} - -void halbtc8723d1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false, wifi_turbo = false; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - if ((coex_sta->bt_relink_downcount != 0) - && (!bt_link_info->pan_exist) && (wifi_busy)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); - BTC_TRACE(trace_buf); - - /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);*/ - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (!wifi_busy) { - /*halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32);*/ - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 27); - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - - if (coex_sta->wl_noisy_level == 2) - halbtc8723d1ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 17); - else - halbtc8723d1ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - - if (wifi_turbo) - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if (((bt_link_info->a2dp_exist) && - (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - - if ((bt_link_info->hid_exist) && (coex_sta->hid_busy_num >= 2)) { - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - if (wifi_bw == 0) /* 11bg mode */ - halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - else - halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 12); - } else if (wifi_busy) { - if (((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) || - (!coex_sta->is_A2DP_3M)) - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 15); - else if (wifi_turbo) - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 18); - else - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 13); - } else - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - - if (bt_link_info->hid_exist) - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - else if (wifi_turbo) - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - - if ((wifi_busy) && (coex_sta->hid_busy_num >= 2)) { /*for 4/18 hid */ - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - if (wifi_bw == 0) /* 11bg mode */ - halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - else - halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - } else { - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 8); - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } - - } else if ((bt_link_info->pan_only) - || (bt_link_info->hid_exist && bt_link_info->pan_exist)) { - /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - - if ((bt_link_info->hid_exist) && (bt_link_info->pan_exist) && - (coex_sta->hid_busy_num >= 2)) { - - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - if (wifi_bw == 0) /* 11bg mode */ - halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - else - halbtc8723d1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 12); - } else { - if (!wifi_busy) - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 4); - else - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 3); - - if (bt_link_info->hid_exist) - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - else if (wifi_turbo) - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else - halbtc8723d1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else { - /* BT no-profile busy (0x9) */ - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } -} - -void halbtc8723d1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - /* tdma and coex table */ - halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - - -void halbtc8723d1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - - if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - - if (bt_link_info->hid_only) /* HID only */ - halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist); - else - halbtc8723d1ant_action_wifi_connected_bt_acl_busy(btcoexist); - - } else if ((BT_8723D_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist); - } else - halbtc8723d1ant_action_bt_idle(btcoexist); -} - - -void halbtc8723d1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - - algorithm = halbtc8723d1ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - - if (halbtc8723d1ant_is_common_action(btcoexist)) { - - } else { - switch (coex_dm->cur_algorithm) { - case BT_8723D_1ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8723D_1ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8723D_1ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - break; - case BT_8723D_1ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - break; - case BT_8723D_1ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8723D_1ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - break; - case BT_8723D_1ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - - -void halbtc8723d1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - boolean miracast_plus_bt = false, wifi_under_5g = false; - u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0, wifi_bw; - u8 iot_peer = BTC_IOT_PEER_UNKNOWN; - boolean scan = false, link = false, roam = false, under_4way = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (!coex_sta->run_time_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], return for run_time_state = false !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->freeze_coexrun_by_btinfo) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8723d1ant_action_bt_whql_test(btcoexist); - return; - } - - if (coex_sta->bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!!\n"); - halbtc8723d1ant_action_wifi_only(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8723d1ant_action_bt_inquiry(btcoexist); - return; - } - - if (coex_sta->is_setupLink) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is re-link !!!\n"); - halbtc8723d1ant_action_bt_relink(btcoexist); - return; - } - - if ((BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) - miracast_plus_bt = true; - else - miracast_plus_bt = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - false, 0x5); - - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", - scan, link, roam, under_4way); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_action_wifi_linkscan_process(btcoexist); - } else - halbtc8723d1ant_action_wifi_multi_port(btcoexist); - - return; - } else { - - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - - btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); - - if (BTC_IOT_PEER_CISCO == iot_peer) { - - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8723d1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x10); - else - halbtc8723d1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x8); - } else - halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x5); - } - - halbtc8723d1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is hs\n"); - BTC_TRACE(trace_buf); - halbtc8723d1ant_action_bt_hs(btcoexist); - return; - } - - if ((BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || - (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is idle\n"); - BTC_TRACE(trace_buf); - halbtc8723d1ant_action_bt_idle(btcoexist); - return; - } - - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", - scan, link, roam, under_4way); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under linkscan process!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_action_wifi_linkscan_process(btcoexist); - } else if (wifi_connected) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under connected!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_action_wifi_connected(btcoexist); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under not-connected!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_action_wifi_not_connected(btcoexist); - } -} - - -void halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->pop_event_cnt = 0; - coex_sta->cnt_RemoteNameReq = 0; - coex_sta->cnt_ReInit = 0; - coex_sta->cnt_setupLink = 0; - coex_sta->cnt_IgnWlanAct = 0; - coex_sta->cnt_Page = 0; - coex_sta->cnt_RoleSwitch = 0; - - halbtc8723d1ant_query_bt_info(btcoexist); -} - -void halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up, IN boolean wifi_only) -{ - u32 u32tmp1 = 0, u32tmp2 = 0; - u16 u16tmp1 = 0; - u8 u8tmp0 = 0, u8tmp1 = 0; - struct btc_board_info *board_info = &btcoexist->board_info; - u8 i = 0; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - -#if BT_8723D_1ANT_COEX_DBG - u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0x54); - u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948); - u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x73); - u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before init_hw_config)\n", - u8tmp0, u16tmp1, u8tmp1); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x (Before init_hw_config)\n", - u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif - - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - coex_sta->bt_ble_scan_type = 0; - coex_sta->bt_ble_scan_para[0] = 0; - coex_sta->bt_ble_scan_para[1] = 0; - coex_sta->bt_ble_scan_para[2] = 0; - coex_sta->bt_reg_vendor_ac = 0xffff; - coex_sta->bt_reg_vendor_ae = 0xffff; - coex_sta->isolation_btween_wb = BT_8723D_1ANT_DEFAULT_ISOLATION; - coex_sta->gnt_error_cnt = 0; - coex_sta->bt_relink_downcount = 0; - - for (i = 0; i <= 9; i++) - coex_sta->bt_afh_map[i] = 0; - - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - - /* BT report packet sample rate */ - btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); - - /* Init 0x778 = 0x1 for 1-Ant */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - - /* Enable PTA (3-wire function form BT side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); - - /* Enable PTA (tx/rx signal form WiFi side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); - - halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, true); - -#if 0 - /* check if WL firmware download ok */ - if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ONOFF, true); -#endif - - /* PTA parameter */ - halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - - halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - psd_scan->ant_det_is_ant_det_available = true; - - /* Antenna config */ - if (wifi_only) { - coex_sta->concurrent_rx_mode_on = false; - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_WLANONLY_INIT); - - btcoexist->stop_coex_dm = true; - } else { - /*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); - - coex_sta->concurrent_rx_mode_on = true; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); - /* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0); - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_COEX_INIT); - - btcoexist->stop_coex_dm = false; - } - - if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Single Antenna, Antenna at Main Port: S1**********\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Single Antenna, Antenna at Aux Port: S0**********\n"); - BTC_TRACE(trace_buf); - } - -} - -u32 halbtc8723d1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val) -{ - u8 j; - u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0; - u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200, - 174, 151, 132, 115, 100, 86, 74, 62, 51, 42, - 32, 23, 15, 7, 0 - }; - - if (val == 0) - return 0; - - tmp = val; - - while (1) { - if (tmp == 1) - break; - else { - tmp = (tmp >> 1); - shiftcount++; - } - } - - - val_integerd_b = shiftcount + 1; - - tmp2 = 1; - for (j = 1; j <= val_integerd_b; j++) - tmp2 = tmp2 * 2; - - tmp = (val * 100) / tmp2; - tindex = tmp / 5; - - if (tindex > 20) - tindex = 20; - - val_fractiond_b = table_fraction[tindex]; - - result = val_integerd_b * 100 - val_fractiond_b; - - return result; - - -} - -void halbtc8723d1ant_psd_show_antenna_detect_result(IN struct btc_coexist - *btcoexist) -{ - u8 *cli_buf = btcoexist->cli_buf; - struct btc_board_info *board_info = &btcoexist->board_info; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n============[Antenna Detection info] ============\n"); - CL_PRINTF(cli_buf); - - if (psd_scan->ant_det_result == 12) { /* Get Ant Det from BT */ - - if (board_info->btdm_ant_num_by_ant_det == 1) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (%d~%d)", - "Ant Det Result", "1-Antenna", - BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT, - BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION); - else { - - if (psd_scan->ant_det_psd_scan_peak_val > - (BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION) - * 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (>%d)", - "Ant Det Result", "2-Antenna (Bad-Isolation)", - BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (%d~%d)", - "Ant Det Result", "2-Antenna (Good-Isolation)", - BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION, - BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); - } - } else if (psd_scan->ant_det_result == 1) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)", - "Ant Det Result", "2-Antenna (Bad-Isolation)", - BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); - else if (psd_scan->ant_det_result == 2) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)", - "Ant Det Result", "2-Antenna (Good-Isolation)", - BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset, - BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)", - "Ant Det Result", "1-Antenna", - BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT, - BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset); - - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ", - "Antenna Detection Finish", - (board_info->btdm_ant_det_finish - ? "Yes" : "No")); - CL_PRINTF(cli_buf); - - switch (psd_scan->ant_det_result) { - case 0: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is not available)"); - break; - case 1: /* 2-Ant bad-isolation */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available)"); - break; - case 2: /* 2-Ant good-isolation */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available)"); - break; - case 3: /* 1-Ant */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available)"); - break; - case 4: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(Uncertainty result)"); - break; - case 5: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(Pre-Scan fai)"); - break; - case 6: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(WiFi is Scanning)"); - break; - case 7: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is not idle)"); - break; - case 8: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(Abort by WiFi Scanning)"); - break; - case 9: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(Antenna Init is not ready)"); - break; - case 10: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is Inquiry or page)"); - break; - case 11: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is Disabled)"); - case 12: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available, result from BT"); - break; - } - CL_PRINTF(cli_buf); - - if (psd_scan->ant_det_result == 12) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB", - "PSD Scan Peak Value", - psd_scan->ant_det_psd_scan_peak_val / 100); - CL_PRINTF(cli_buf); - return; - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Ant Detect Total Count", psd_scan->ant_det_try_count); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Ant Detect Fail Count", psd_scan->ant_det_fail_count); - CL_PRINTF(cli_buf); - - if ((!board_info->btdm_ant_det_finish) && - (psd_scan->ant_det_result != 5)) - return; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Response", - (psd_scan->ant_det_result ? "ok" : "fail")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ms", "BT Tx Time", - psd_scan->ant_det_bt_tx_time); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "BT Tx Ch", - psd_scan->ant_det_bt_le_channel); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", - "WiFi PSD Cent-Ch/Offset/Span", - psd_scan->real_cent_freq, psd_scan->real_offset, - psd_scan->real_span); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB", - "PSD Pre-Scan Peak Value", - psd_scan->ant_det_pre_psdscan_peak_val / 100); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (<= %d)", - "PSD Pre-Scan result", - (psd_scan->ant_det_result != 5 ? "ok" : "fail"), - BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset); - CL_PRINTF(cli_buf); - - if (psd_scan->ant_det_result == 5) - return; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s dB", - "PSD Scan Peak Value", psd_scan->ant_det_peak_val); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s MHz", - "PSD Scan Peak Freq", psd_scan->ant_det_peak_freq); - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package", - (board_info->tfbga_package) ? "Yes" : "No"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "PSD Threshold Offset", psd_scan->ant_det_thres_offset); - CL_PRINTF(cli_buf); - -} - - - -void halbtc8723d1ant_psd_showdata(IN struct btc_coexist *btcoexist) -{ - u8 *cli_buf = btcoexist->cli_buf; - u32 delta_freq_per_point; - u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2; - - if (psd_scan->ant_det_result == 12) - return; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n\n============[PSD info] (%d)============\n", - psd_scan->psd_gen_count); - CL_PRINTF(cli_buf); - - if (psd_scan->psd_gen_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n"); - CL_PRINTF(cli_buf); - return; - } - - if (psd_scan->psd_point == 0) - delta_freq_per_point = 0; - else - delta_freq_per_point = psd_scan->psd_band_width / - psd_scan->psd_point; - - /* if (psd_scan->is_psd_show_max_only) */ - if (0) { - psd_rep1 = psd_scan->psd_max_value / 100; - psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100; - - freq = ((psd_scan->real_cent_freq - 20) * 1000000 + - psd_scan->psd_max_value_point * delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq = %d.0%d MHz", - freq1, freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq = %d.%d MHz", - freq1, freq2); - - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - ", Value = %d.0%d dB, (%d)\n", - psd_rep1, psd_rep2, psd_scan->psd_max_value); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - ", Value = %d.%d dB, (%d)\n", - psd_rep1, psd_rep2, psd_scan->psd_max_value); - - CL_PRINTF(cli_buf); - } else { - m = psd_scan->psd_start_point; - n = psd_scan->psd_start_point; - i = 1; - j = 1; - - while (1) { - do { - freq = ((psd_scan->real_cent_freq - 20) * - 1000000 + m * - delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (i == 1) { - if (freq2 == 0) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Freq%6d.000", - freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Freq%6d.0%2d", - freq1, - freq2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Freq%6d.%3d", - freq1, - freq2); - } else if ((i % 8 == 0) || - (m == psd_scan->psd_stop_point)) { - if (freq2 == 0) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.000\n", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.0%2d\n", freq1, - freq2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.%3d\n", freq1, - freq2); - } else { - if (freq2 == 0) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.000", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.0%2d", freq1, - freq2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.%3d", freq1, - freq2); - } - - i++; - m++; - CL_PRINTF(cli_buf); - - } while ((i <= 8) && (m <= psd_scan->psd_stop_point)); - - - do { - psd_rep1 = psd_scan->psd_report_max_hold[n] / - 100; - psd_rep2 = psd_scan->psd_report_max_hold[n] - - psd_rep1 * - 100; - - if (j == 1) { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Val %7d.0%d", - psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Val %7d.%d", - psd_rep1, - psd_rep2); - } else if ((j % 8 == 0) || - (n == psd_scan->psd_stop_point)) { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%7d.0%d\n", psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%7d.%d\n", psd_rep1, - psd_rep2); - } else { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%7d.0%d", psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%7d.%d", psd_rep1, - psd_rep2); - } - - j++; - n++; - CL_PRINTF(cli_buf); - - } while ((j <= 8) && (n <= psd_scan->psd_stop_point)); - - if ((m > psd_scan->psd_stop_point) || - (n > psd_scan->psd_stop_point)) - break; - else { - i = 1; - j = 1; - } - - } - } - - -} - - -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -void halbtc8723d1ant_psd_maxholddata(IN struct btc_coexist *btcoexist, - IN u32 gen_count) -{ - u32 i = 0; - u32 loop_i_max = 0, loop_val_max = 0; - - if (gen_count == 1) { - memcpy(psd_scan->psd_report_max_hold, - psd_scan->psd_report, - BT_8723D_1ANT_ANTDET_PSD_POINTS * sizeof(u32)); - } - - for (i = psd_scan->psd_start_point; - i <= psd_scan->psd_stop_point; i++) { - - /* update max-hold value at each freq point */ - if (psd_scan->psd_report[i] > psd_scan->psd_report_max_hold[i]) - psd_scan->psd_report_max_hold[i] = - psd_scan->psd_report[i]; - - /* search the max value in this seep */ - if (psd_scan->psd_report[i] > loop_val_max) { - loop_val_max = psd_scan->psd_report[i]; - loop_i_max = i; - } - } - - if (gen_count <= BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT) - psd_scan->psd_loop_max_value[gen_count - 1] = loop_val_max; -} - -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -u32 halbtc8723d1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) -{ - /* reg 0x808[9:0]: FFT data x */ - /* reg 0x808[22]: 0-->1 to get 1 FFT data y */ - /* reg 0x8b4[15:0]: FFT data y report */ - - u32 val = 0, psd_report = 0; - int k = 0; - - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - - val &= 0xffbffc00; - val |= point; - - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - val |= 0x00400000; - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - while (1) { - if (k++ > BT_8723D_1ANT_ANTDET_SWEEPPOINT_DELAY) - break; - } - - val = btcoexist->btc_read_4byte(btcoexist, 0x8b4); - - psd_report = val & 0x0000ffff; - - return psd_report; -} - -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points, - IN u32 avgnum, IN u32 loopcnt) -{ - u32 i = 0, val = 0, n = 0, k = 0, j, point_index = 0; - u32 points1 = 0, psd_report = 0; - u32 start_p = 0, stop_p = 0, delta_freq_per_point = 156250; - u32 psd_center_freq = 20 * 10 ^ 6; - boolean outloop = false, scan , roam, is_sweep_ok = true; - u8 flag = 0; - u32 tmp = 0, u32tmp1 = 0; - u32 wifi_original_channel = 1; - u32 psd_sum = 0, avg_cnt = 0; - u32 i_max = 0, val_max = 0, val_max2 = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n"); - BTC_TRACE(trace_buf); - - do { - switch (flag) { - case 0: /* Get PSD parameters */ - default: - - psd_scan->psd_band_width = 40 * 1000000; - psd_scan->psd_point = points; - psd_scan->psd_start_base = points / 2; - psd_scan->psd_avg_num = avgnum; - psd_scan->real_cent_freq = cent_freq; - psd_scan->real_offset = offset; - psd_scan->real_span = span; - - - points1 = psd_scan->psd_point; - delta_freq_per_point = psd_scan->psd_band_width / - psd_scan->psd_point; - - /* PSD point setup */ - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - val &= 0xffff0fff; - - switch (psd_scan->psd_point) { - case 128: - val |= 0x0; - break; - case 256: - default: - val |= 0x00004000; - break; - case 512: - val |= 0x00008000; - break; - case 1024: - val |= 0x0000c000; - break; - } - - switch (psd_scan->psd_avg_num) { - case 1: - val |= 0x0; - break; - case 8: - val |= 0x00001000; - break; - case 16: - val |= 0x00002000; - break; - case 32: - default: - val |= 0x00003000; - break; - } - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - flag = 1; - break; - case 1: /* calculate the PSD point index from freq/offset/span */ - psd_center_freq = psd_scan->psd_band_width / 2 + - offset * (1000000); - - start_p = psd_scan->psd_start_base + (psd_center_freq - - span * (1000000) / 2) / delta_freq_per_point; - psd_scan->psd_start_point = start_p - - psd_scan->psd_start_base; - - stop_p = psd_scan->psd_start_base + (psd_center_freq + - span * (1000000) / 2) / delta_freq_per_point; - psd_scan->psd_stop_point = stop_p - - psd_scan->psd_start_base - 1; - - flag = 2; - break; - case 2: /* set RF channel/BW/Mode */ - - /* set 3-wire off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x88c); - val |= 0x00300000; - btcoexist->btc_write_4byte(btcoexist, 0x88c, val); - - /* CCK off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x800); - val &= 0xfeffffff; - btcoexist->btc_write_4byte(btcoexist, 0x800, val); - - /* Tx-pause on */ - btcoexist->btc_write_1byte(btcoexist, 0x522, 0x6f); - - /* store WiFi original channel */ - wifi_original_channel = btcoexist->btc_get_rf_reg( - btcoexist, BTC_RF_A, 0x18, 0x3ff); - - /* Set RF channel */ - if (cent_freq == 2484) - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, - 0x18, 0x3ff, 0xe); - else - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, - 0x18, 0x3ff, (cent_freq - 2412) / 5 + - 1); /* WiFi TRx Mask on */ - - /* save original RCK value */ - u32tmp1 = btcoexist->btc_get_rf_reg( - btcoexist, BTC_RF_A, 0x1d, 0xfffff); - - /* Enter debug mode */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde, - 0x2, 0x1); - - /* Set RF Rx filter corner */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d, - 0xfffff, 0x2e); - - - /* Set RF mode = Rx, RF Gain = 0x320a0 */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0, - 0xfffff, 0x320a0); - - while (1) { - if (k++ > BT_8723D_1ANT_ANTDET_SWEEPPOINT_DELAY) - break; - } - flag = 3; - break; - case 3: - psd_scan->psd_gen_count = 0; - for (j = 1; j <= loopcnt; j++) { - - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || roam) { - is_sweep_ok = false; - break; - } - memset(psd_scan->psd_report, 0, - psd_scan->psd_point * sizeof(u32)); - start_p = psd_scan->psd_start_point + - psd_scan->psd_start_base; - stop_p = psd_scan->psd_stop_point + - psd_scan->psd_start_base + 1; - - i = start_p; - point_index = 0; - - while (i < stop_p) { - if (i >= points1) - psd_report = - halbtc8723d1ant_psd_getdata( - btcoexist, i - points1); - else - psd_report = - halbtc8723d1ant_psd_getdata( - btcoexist, i); - - if (psd_report == 0) - tmp = 0; - else - /* tmp = 20*log10((double)psd_report); */ - /* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */ - tmp = 6 * halbtc8723d1ant_psd_log2base( - btcoexist, psd_report); - - n = i - psd_scan->psd_start_base; - psd_scan->psd_report[n] = tmp; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Point=%d, psd_dB_data = %d\n", - i, psd_scan->psd_report[n]); - BTC_TRACE(trace_buf); - - i++; - - } - - halbtc8723d1ant_psd_maxholddata(btcoexist, j); - - psd_scan->psd_gen_count = j; - - /*Accumulate Max PSD value in this loop if the value > threshold */ - if (psd_scan->psd_loop_max_value[j - 1] >= - 4000) { - psd_sum = psd_sum + - psd_scan->psd_loop_max_value[j - - 1]; - avg_cnt++; - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Loop=%d, Max_dB_data = %d\n", - j, psd_scan->psd_loop_max_value[j - - 1]); - BTC_TRACE(trace_buf); - - } - - if (loopcnt == BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT) { - - /* search the Max Value between each-freq-point-max-hold value of all sweep*/ - for (i = 1; - i <= BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT; - i++) { - - if (i == 1) { - i_max = i; - val_max = psd_scan->psd_loop_max_value[i - - 1]; - val_max2 = - psd_scan->psd_loop_max_value[i - - 1]; - } else if ( - psd_scan->psd_loop_max_value[i - - 1] > val_max) { - val_max2 = val_max; - i_max = i; - val_max = psd_scan->psd_loop_max_value[i - - 1]; - } else if ( - psd_scan->psd_loop_max_value[i - - 1] > val_max2) - val_max2 = - psd_scan->psd_loop_max_value[i - - 1]; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "i = %d, val_hold= %d, val_max = %d, val_max2 = %d\n", - i, psd_scan->psd_loop_max_value[i - - 1], - val_max, val_max2); - - BTC_TRACE(trace_buf); - } - - psd_scan->psd_max_value_point = i_max; - psd_scan->psd_max_value = val_max; - psd_scan->psd_max_value2 = val_max2; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "val_max = %d, val_max2 = %d\n", - psd_scan->psd_max_value, - psd_scan->psd_max_value2); - BTC_TRACE(trace_buf); - } - - if (avg_cnt != 0) { - psd_scan->psd_avg_value = (psd_sum / avg_cnt); - if ((psd_sum % avg_cnt) >= (avg_cnt / 2)) - psd_scan->psd_avg_value++; - } else - psd_scan->psd_avg_value = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "AvgLoop=%d, Avg_dB_data = %d\n", - avg_cnt, psd_scan->psd_avg_value); - BTC_TRACE(trace_buf); - - flag = 100; - break; - case 99: /* error */ - - outloop = true; - break; - case 100: /* recovery */ - - /* set 3-wire on */ - val = btcoexist->btc_read_4byte(btcoexist, 0x88c); - val &= 0xffcfffff; - btcoexist->btc_write_4byte(btcoexist, 0x88c, val); - - /* CCK on */ - val = btcoexist->btc_read_4byte(btcoexist, 0x800); - val |= 0x01000000; - btcoexist->btc_write_4byte(btcoexist, 0x800, val); - - /* Tx-pause off */ - btcoexist->btc_write_1byte(btcoexist, 0x522, 0x0); - - /* PSD off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - val &= 0xffbfffff; - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - /* restore RF Rx filter corner */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d, - 0xfffff, u32tmp1); - - /* Exit debug mode */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde, - 0x2, 0x0); - - /* restore WiFi original channel */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18, - 0x3ff, wifi_original_channel); - - outloop = true; - break; - - } - - } while (!outloop); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n"); - BTC_TRACE(trace_buf); - return is_sweep_ok; - -} - -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -boolean halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist - *btcoexist) -{ - u32 i = 0; - u32 wlpsd_cent_freq = 2484, wlpsd_span = 2; - s32 wlpsd_offset = -4; - u32 bt_tx_time, bt_le_channel; - u8 bt_le_ch[13] = {3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 33}; - - u8 h2c_parameter[3] = {0}, u8tmpa, u8tmpb; - - u8 state = 0; - boolean outloop = false, bt_resp = false, ant_det_finish = false; - u32 freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point, - u32tmp, u32tmp0, u32tmp1, u32tmp2 ; - struct btc_board_info *board_info = &btcoexist->board_info; - - memset(psd_scan->ant_det_peak_val, 0, 16 * sizeof(u8)); - memset(psd_scan->ant_det_peak_freq, 0, 16 * sizeof(u8)); - - psd_scan->ant_det_bt_tx_time = - BT_8723D_1ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */ - psd_scan->ant_det_bt_le_channel = BT_8723D_1ANT_ANTDET_BTTXCHANNEL; - - bt_tx_time = psd_scan->ant_det_bt_tx_time; - bt_le_channel = psd_scan->ant_det_bt_le_channel; - - if (board_info->tfbga_package) /* for TFBGA */ - psd_scan->ant_det_thres_offset = 5; - else - psd_scan->ant_det_thres_offset = 0; - - do { - switch (state) { - case 0: - if (bt_le_channel == 39) - wlpsd_cent_freq = 2484; - else { - for (i = 1; i <= 13; i++) { - if (bt_le_ch[i - 1] == - bt_le_channel) { - wlpsd_cent_freq = 2412 - + (i - 1) * 5; - break; - } - } - - if (i == 14) { - - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Abort!!, Invalid LE channel = %d\n ", - bt_le_channel); - BTC_TRACE(trace_buf); - outloop = true; - break; - } - } -#if 0 - wlpsd_sweep_count = bt_tx_time * 238 / - 100; /* bt_tx_time/0.42 */ - wlpsd_sweep_count = wlpsd_sweep_count / 5; - - if (wlpsd_sweep_count % 5 != 0) - wlpsd_sweep_count = (wlpsd_sweep_count / - 5 + 1) * 5; -#endif - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n", - bt_tx_time, bt_le_channel); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), wlpsd_cent_freq=%d, wlpsd_offset = %d, wlpsd_span = %d, wlpsd_sweep_count = %d\n", - wlpsd_cent_freq, - wlpsd_offset, - wlpsd_span, - BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT); - BTC_TRACE(trace_buf); - - state = 1; - break; - case 1: /* stop coex DM & set antenna path */ - /* Stop Coex DM */ - btcoexist->stop_coex_dm = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n"); - BTC_TRACE(trace_buf); - - /* Set TDMA off, */ - halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, - false, 0); - - /* Set coex table */ - halbtc8723d1ant_coex_table_with_type(btcoexist, - FORCE_EXEC, 0); - - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n"); - BTC_TRACE(trace_buf); - } - - /* Set Antenna path, switch WiFi to un-certain antenna port */ - /* Set Antenna Path, both GNT_WL/GNT_BT = 1, and control by SW */ - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_ANTENNA_DET); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n"); - BTC_TRACE(trace_buf); - - /* Set AFH mask on at WiFi channel 2472MHz +/- 10MHz */ - h2c_parameter[0] = 0x1; - h2c_parameter[1] = 0xd; - h2c_parameter[2] = 0x14; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n", - h2c_parameter[1], - h2c_parameter[2]); - BTC_TRACE(trace_buf); - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, - h2c_parameter); - - u32tmp = btcoexist->btc_read_2byte(btcoexist, 0x948); - u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70); - u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg( - btcoexist, 0x38); - u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg( - btcoexist, 0x54); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x948 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (Before Ant Det)\n", - u32tmp, u32tmp0, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - - state = 2; - break; - case 2: /* Pre-sweep background psd */ - if (!halbtc8723d1ant_psd_sweep_point(btcoexist, - wlpsd_cent_freq, wlpsd_offset, wlpsd_span, - BT_8723D_1ANT_ANTDET_PSD_POINTS, - BT_8723D_1ANT_ANTDET_PSD_AVGNUM, 3)) { - ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - psd_scan->ant_det_result = 8; - state = 99; - break; - } - - psd_scan->ant_det_pre_psdscan_peak_val = - psd_scan->psd_max_value; - - if (psd_scan->ant_det_pre_psdscan_peak_val > - (BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset) * 100) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n", - psd_scan->ant_det_pre_psdscan_peak_val / - 100, - BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset); - BTC_TRACE(trace_buf); - ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - psd_scan->ant_det_result = 5; - state = 99; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n", - psd_scan->ant_det_pre_psdscan_peak_val / - 100, - BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset); - BTC_TRACE(trace_buf); - state = 3; - } - break; - case 3: - - bt_resp = btcoexist->btc_set_bt_ant_detection( - btcoexist, (u8)(bt_tx_time & 0xff), - (u8)(bt_le_channel & 0xff)); - - /* Sync WL Rx PSD with BT Tx time because H2C->Mailbox delay */ - delay_ms(20); - - if (!halbtc8723d1ant_psd_sweep_point(btcoexist, - wlpsd_cent_freq, wlpsd_offset, - wlpsd_span, - BT_8723D_1ANT_ANTDET_PSD_POINTS, - BT_8723D_1ANT_ANTDET_PSD_AVGNUM, - BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT)) { - ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - psd_scan->ant_det_result = 8; - state = 99; - break; - } - -#if 1 - psd_scan->ant_det_psd_scan_peak_val = - psd_scan->psd_max_value; -#endif -#if 0 - psd_scan->ant_det_psd_scan_peak_val = - ((psd_scan->psd_max_value - psd_scan->psd_avg_value) < - 800) ? - psd_scan->psd_max_value : (( - psd_scan->psd_max_value - - psd_scan->psd_max_value2 <= 300) ? - psd_scan->psd_avg_value : - psd_scan->psd_max_value2); -#endif - psd_scan->ant_det_psd_scan_peak_freq = - psd_scan->psd_max_value_point; - state = 4; - break; - case 4: - - if (psd_scan->psd_point == 0) - delta_freq_per_point = 0; - else - delta_freq_per_point = - psd_scan->psd_band_width / - psd_scan->psd_point; - - psd_rep1 = psd_scan->ant_det_psd_scan_peak_val / 100; - psd_rep2 = psd_scan->ant_det_psd_scan_peak_val - - psd_rep1 * - 100; - - freq = ((psd_scan->real_cent_freq - 20) * - 1000000 + psd_scan->psd_max_value_point - * delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (freq2 < 100) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.0%d MHz", - freq1, freq2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_freq, - BT_8723D_1ANT_ANTDET_BUF_LEN, - "%d.0%d", freq1, freq2); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.%d MHz", - freq1, freq2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_freq, - BT_8723D_1ANT_ANTDET_BUF_LEN, - "%d.%d", freq1, freq2); - } - - if (psd_rep2 < 10) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - ", Value = %d.0%d dB\n", - psd_rep1, psd_rep2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_val, - BT_8723D_1ANT_ANTDET_BUF_LEN, - "%d.0%d", psd_rep1, psd_rep2); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - ", Value = %d.%d dB\n", - psd_rep1, psd_rep2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_val, - BT_8723D_1ANT_ANTDET_BUF_LEN, - "%d.%d", psd_rep1, psd_rep2); - } - - psd_scan->ant_det_is_btreply_available = true; - - if (bt_resp == false) { - psd_scan->ant_det_is_btreply_available = - false; - psd_scan->ant_det_result = 0; - ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n "); - BTC_TRACE(trace_buf); - } else if (psd_scan->ant_det_psd_scan_peak_val > - (BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION) - * 100) { - psd_scan->ant_det_result = 1; - ant_det_finish = true; - board_info->btdm_ant_num_by_ant_det = 2; - coex_sta->isolation_btween_wb = (u8)(85 - - psd_scan->ant_det_psd_scan_peak_val / - 100) & 0xff; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n"); - BTC_TRACE(trace_buf); - } else if (psd_scan->ant_det_psd_scan_peak_val > - (BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset) * 100) { - psd_scan->ant_det_result = 2; - ant_det_finish = true; - board_info->btdm_ant_num_by_ant_det = 2; - coex_sta->isolation_btween_wb = (u8)(85 - - psd_scan->ant_det_psd_scan_peak_val / - 100) & 0xff; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n"); - BTC_TRACE(trace_buf); - } else if (psd_scan->ant_det_psd_scan_peak_val > - (BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT) * - 100) { - psd_scan->ant_det_result = 3; - ant_det_finish = true; - board_info->btdm_ant_num_by_ant_det = 1; - coex_sta->isolation_btween_wb = (u8)(85 - - psd_scan->ant_det_psd_scan_peak_val / - 100) & 0xff; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n"); - BTC_TRACE(trace_buf); - } else { - psd_scan->ant_det_result = 4; - ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n"); - BTC_TRACE(trace_buf); - } - - state = 99; - break; - case 99: /* restore setup */ - - /* Set AFH mask off at WiFi channel 2472MHz +/- 10MHz */ - h2c_parameter[0] = 0x0; - h2c_parameter[1] = 0x0; - h2c_parameter[2] = 0x0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n", - h2c_parameter[1], h2c_parameter[2]); - BTC_TRACE(trace_buf); - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, - h2c_parameter); - - /* Set Antenna Path, GNT_WL/GNT_BT control by PTA */ - /* Set Antenna path, switch WiFi to certain antenna port */ - halbtc8723d1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); - BTC_TRACE(trace_buf); - - outloop = true; - break; - } - - } while (!outloop); - - return ant_det_finish; - -} - -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -boolean halbtc8723d1ant_psd_antenna_detection_check(IN struct btc_coexist - *btcoexist) -{ - static u32 ant_det_count = 0, ant_det_fail_count = 0; - struct btc_board_info *board_info = &btcoexist->board_info; - - boolean scan, roam, ant_det_finish = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - ant_det_count++; - - psd_scan->ant_det_try_count = ant_det_count; - - if (scan || roam) { - ant_det_finish = false; - psd_scan->ant_det_result = 6; - } else if (coex_sta->bt_disabled) { - ant_det_finish = false; - psd_scan->ant_det_result = 11; - } else if (coex_sta->num_of_profile >= 1) { - ant_det_finish = false; - psd_scan->ant_det_result = 7; - } else if ( - !psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */ - ant_det_finish = false; - psd_scan->ant_det_result = 9; - } else if (coex_sta->c2h_bt_inquiry_page) { - ant_det_finish = false; - psd_scan->ant_det_result = 10; - } else { - - ant_det_finish = halbtc8723d1ant_psd_antenna_detection( - btcoexist); - - delay_ms(psd_scan->ant_det_bt_tx_time); - } - - /* board_info->ant_det_result = psd_scan->ant_det_result; */ - - if (!ant_det_finish) - ant_det_fail_count++; - - psd_scan->ant_det_fail_count = ant_det_fail_count; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), result = %d, fail_count = %d, finish = %s\n", - psd_scan->ant_det_result, - psd_scan->ant_det_fail_count, - ant_det_finish == true ? "Yes" : "No"); - BTC_TRACE(trace_buf); - - return ant_det_finish; - -} - - - -/* ************************************************************ - * work around function start with wa_halbtc8723d1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8723d1ant_ - * ************************************************************ */ -void ex_halbtc8723d1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x0; - u16 u16tmp = 0x0; - u32 value = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Execute 8723d 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Ant Det Finish = %s, Ant Det Number = %d\n", - (board_info->btdm_ant_det_finish ? "Yes" : "No"), - board_info->btdm_ant_num_by_ant_det); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = true; - psd_scan->ant_det_is_ant_det_available = false; - - /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - - /* Set Antenna Path to BT side */ - /* Check efuse 0xc3[6] for Single Antenna Path */ - if (board_info->single_ant_path == 0) { - /* set to S1 */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - u8tmp = 0; - value = 1; - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - u8tmp = 1; - value = 0; - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d **********\n", - board_info->single_ant_path , board_info->btdm_ant_pos); - BTC_TRACE(trace_buf); - - /* Set Antenna Path to BT side */ - halbtc8723d1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_COEX_POWERON); - - /* Write Single Antenna Position to Registry to tell BT for 8723d. This line can be removed - since BT EFuse also add "single antenna position" in EFuse for 8723d*/ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, - &value); - - /* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at power on */ - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); - - /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, true); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n", - halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38)); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0x948 (Power-On) = 0x%x / 0x%x**********\n", - btcoexist->btc_read_4byte(btcoexist, 0x70), - btcoexist->btc_read_2byte(btcoexist, 0x948)); - BTC_TRACE(trace_buf); - -} - -void ex_halbtc8723d1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8723d1ant_init_hw_config(btcoexist, true, wifi_only); -} - -void ex_halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - halbtc8723d1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; - u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; - static u8 pop_report_in_10s = 0; - u32 phyver = 0; - boolean lte_coex_on = false; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - if (psd_scan->ant_det_try_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s", - "Ant PG Num/ Mech/ Pos", - board_info->pg_ant_num, board_info->btdm_ant_num, - (board_info->btdm_ant_pos == 1 ? "S1" : "S0")); - CL_PRINTF(cli_buf); - } else { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %s (%d/%d/%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos", - board_info->pg_ant_num, - board_info->btdm_ant_num_by_ant_det, - (board_info->btdm_ant_pos == 1 ? "S1" : "S0"), - psd_scan->ant_det_try_count, - psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); - CL_PRINTF(cli_buf); - - if (board_info->btdm_ant_det_finish) { - - if (psd_scan->ant_det_result != 12) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d", - "Ant Det PSD Value", - psd_scan->ant_det_psd_scan_peak_val - / 100); - CL_PRINTF(cli_buf); - } - } - - if (board_info->ant_det_result_five_complete) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d", - "AntDet(Registry) Num/PSD Value", - board_info->btdm_ant_num_by_ant_det, - (board_info->antdetval & 0x7f)); - CL_PRINTF(cli_buf); - } - - bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); - - bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", - "CoexVer WL/ BT_Desired/ BT_Report", - glcoex_ver_date_8723d_1ant, glcoex_ver_8723d_1ant, - glcoex_ver_btdesired_8723d_1ant, - bt_coex_ver, - (bt_coex_ver == 0xff ? "Unknown" : - (coex_sta->bt_disabled ? "BT-disable" : - (bt_coex_ver >= glcoex_ver_btdesired_8723d_1ant ? - "Match" : "Mis-Match")))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", - "W_FW/ B_FW/ Phy/ Kt", - fw_ver, bt_patch_ver, phyver, - coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") - : ((BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); - CL_PRINTF(cli_buf); - - if (pop_report_in_10s >= 5) { - coex_sta->pop_event_cnt = 0; - pop_report_in_10s = 0; - } - - if (coex_sta->num_of_profile != 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s%s%s%s%s", - "Profiles", - ((bt_link_info->a2dp_exist) ? "A2DP," : ""), - ((bt_link_info->sco_exist) ? "SCO," : ""), - ((bt_link_info->hid_exist) ? - ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : - "HID(2/18),") : ""), - ((bt_link_info->pan_exist) ? "PAN," : ""), - ((coex_sta->voice_over_HOGP) ? "Voice" : "")); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = None", - "Profiles"); - - CL_PRINTF(cli_buf); - - if (bt_link_info->a2dp_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", - "A2DP Rate/Bitpool/Auto_Slot", - ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), - coex_sta->a2dp_bit_pool, - ((coex_sta->is_autoslot) ? "On" : "Off") - ); - CL_PRINTF(cli_buf); - } - - if (bt_link_info->hid_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "HID PairNum/Forbid_Slot", - coex_sta->hid_pair_cnt, - coex_sta->forbidden_slot - ); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x", - "Role/RoleSwCnt/IgnWlact/Feature", - ((bt_link_info->slave_role) ? "Slave" : "Master"), - coex_sta->cnt_RoleSwitch, - ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), - coex_sta->bt_coex_supported_feature); - CL_PRINTF(cli_buf); - - if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "BLEScan Type/TV/Init/Ble", - coex_sta->bt_ble_scan_type, - (coex_sta->bt_ble_scan_type & 0x1 ? - coex_sta->bt_ble_scan_para[0] : 0x0), - (coex_sta->bt_ble_scan_type & 0x2 ? - coex_sta->bt_ble_scan_para[1] : 0x0), - (coex_sta->bt_ble_scan_type & 0x4 ? - coex_sta->bt_ble_scan_para[2] : 0x0)); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", - "ReInit/ReLink/IgnWlact/Page/NameReq", - coex_sta->cnt_ReInit, - coex_sta->cnt_setupLink, - coex_sta->cnt_IgnWlanAct, - coex_sta->cnt_Page, - coex_sta->cnt_RemoteNameReq - ); - CL_PRINTF(cli_buf); - - halbtc8723d1ant_read_score_board(btcoexist, &u16tmp[0]); - - if ((coex_sta->bt_reg_vendor_ae == 0xffff) || - (coex_sta->bt_reg_vendor_ac == 0xffff)) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", - ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), - coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); - CL_PRINTF(cli_buf); - - if (coex_sta->num_of_profile > 0) { - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", - "AFH MAP", - coex_sta->bt_afh_map[0], - coex_sta->bt_afh_map[1], - coex_sta->bt_afh_map[2], - coex_sta->bt_afh_map[3], - coex_sta->bt_afh_map[4], - coex_sta->bt_afh_map[5], - coex_sta->bt_afh_map[6], - coex_sta->bt_afh_map[7], - coex_sta->bt_afh_map[8], - coex_sta->bt_afh_map[9] - ); - CL_PRINTF(cli_buf); - } - - for (i = 0; i < BT_INFO_SRC_8723D_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)", - glbt_info_src_8723d_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms] (before Manual)============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Mechanisms]============"); - - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s)", - "TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off")); - - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", - "Table/0x6c0/0x6c4/0x6c8", - coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x", - "0x778/0x6cc", - u8tmp[0], u32tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", - "AntDiv/ ForceLPS", - ((board_info->ant_div_cfg) ? "On" : "Off"), - ((coex_sta->force_lps_on) ? "On" : "Off")); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? true : false; - - if (lte_coex_on) { - - u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa0); - u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "LTE Coex Table W_L/B_L", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa8); - u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0xac); - u32tmp[2] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb0); - u32tmp[3] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "LTE Break Table W_L/B_L/L_W/L_B", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, - u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); - CL_PRINTF(cli_buf); - - } - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - /* - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - */ - - u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", - "LTE Coex/Path Owner", - ((lte_coex_on) ? "On" : "Off") , - ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); - CL_PRINTF(cli_buf); - - if (lte_coex_on) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %d/ %d", - "LTE 3Wire/OPMode/UART/UARTMode", - (int)((u32tmp[0] & BIT(6)) >> 6), - (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), - (int)((u32tmp[0] & BIT(3)) >> 3), - (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "LTE_Busy/UART_Busy", - (int)((u32tmp[1] & BIT(1)) >> 1), (int)(u32tmp[1] & BIT(0))); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", - "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", - ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), - ((u8tmp[0] & BIT(3)) ? "On" : "Off"), - coex_sta->gnt_error_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "GNT_WL/GNT_BT", - (int)((u32tmp[1] & BIT(2)) >> 2), - (int)((u32tmp[1] & BIT(3)) >> 3)); - CL_PRINTF(cli_buf); - - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x948); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x948/0x67[7]", - u16tmp[0], (int)((u8tmp[0] & BIT(7)) >> 7)); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x964); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x864); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xab7); - u8tmp[3] = btcoexist->btc_read_1byte(btcoexist, 0xa01); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x964[1]/0x864[0]/0xab7[5]/0xa01[7]", - (int)((u8tmp[0] & BIT(1)) >> 1), (int)((u8tmp[1] & BIT(0))), - (int)((u8tmp[2] & BIT(3)) >> 3), - (int)((u8tmp[3] & BIT(7)) >> 7)); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x45e); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x4c6[4]/0x40[5]/0x45e[3](TxRetry)", - (int)((u8tmp[0] & BIT(4)) >> 4), - (int)((u8tmp[1] & BIT(5)) >> 5), - (int)((u8tmp[2] & BIT(3)) >> 3)); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s", - "0x550/0x522/4-RxAGC", - u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off"); - CL_PRINTF(cli_buf); - - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm); - CL_PRINTF(cli_buf); - -#if 1 - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); - CL_PRINTF(cli_buf); -#endif - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "WlHiPri/ Locking/ Locked/ Noisy", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), - (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No"), - coex_sta->wl_noisy_level); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", - "0x770(Hi-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx, - (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : "")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", - "0x774(Lo-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx, - (bt_link_info->slave_role ? "(Slave!!)" : ( - coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); - CL_PRINTF(cli_buf); - - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8723d1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - - /* Write WL "Active" in Score-board for LPS off */ - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE | - BT_8723D_1ANT_SCOREBOARD_ONOFF | - BT_8723D_1ANT_SCOREBOARD_SCAN | - BT_8723D_1ANT_SCOREBOARD_UNDERTEST, - false); - - halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_WLAN_OFF); - - halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); -#if 0 - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE, true); - - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ONOFF, true); -#endif - - halbtc8723d1ant_init_hw_config(btcoexist, false, false); - halbtc8723d1ant_init_coex_dm(btcoexist);; - - coex_sta->under_ips = false; - } -} - -void ex_halbtc8723d1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - - if (coex_sta->force_lps_on == true) { /* LPS No-32K */ - /* Write WL "Active" in Score-board for PS-TDMA */ - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE, true); - - } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ - /* Write WL "Non-Active" in Score-board for Native-PS */ - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE, false); - - } - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - - /* Write WL "Active" in Score-board for LPS off */ - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE, true); - - } -} - -void ex_halbtc8723d1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - coex_sta->freeze_coexrun_by_btinfo = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - halbtc8723d1ant_query_bt_info(btcoexist); - - if (BTC_SCAN_START == type) { - - if (!wifi_connected) - coex_sta->wifi_is_high_pri_task = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE | - BT_8723D_1ANT_SCOREBOARD_SCAN | - BT_8723D_1ANT_SCOREBOARD_ONOFF, - true); - - /* Force antenna setup for no scan result issue */ - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - - halbtc8723d1ant_run_coexist_mechanism(btcoexist); - - } else { - - coex_sta->wifi_is_high_pri_task = false; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", - coex_sta->scan_ap_num); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_run_coexist_mechanism(btcoexist); - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN Notify() end\n"); - BTC_TRACE(trace_buf); - -} - -void ex_halbtc8723d1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - if (BTC_ASSOCIATE_START == type) { - - coex_sta->wifi_is_high_pri_task = true; - - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE | - BT_8723D_1ANT_SCOREBOARD_SCAN | - BT_8723D_1ANT_SCOREBOARD_ONOFF, - true); - - /* Force antenna setup for no scan result issue */ - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - - coex_dm->arp_cnt = 0; - - halbtc8723d1ant_run_coexist_mechanism(btcoexist); - - /* To keep TDMA case during connect process, - to avoid changed by Btinfo and runcoexmechanism */ - coex_sta->freeze_coexrun_by_btinfo = true; - } else { - - coex_sta->wifi_is_high_pri_task = false; - coex_sta->freeze_coexrun_by_btinfo = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_run_coexist_mechanism(btcoexist); - } - -} - -void ex_halbtc8723d1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_under_b_mode = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_MEDIA_CONNECT == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE | - BT_8723D_1ANT_SCOREBOARD_ONOFF, - true); - - /* Force antenna setup for no scan result issue */ - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - /* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */ - /* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE, false); - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - - coex_sta->cck_ever_lock = false; - } - - halbtc8723d1ant_update_wifi_channel_info(btcoexist, type); - -} - -void ex_halbtc8723d1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean under_4way = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (under_4way) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ---- under_4way!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - } else if (BTC_PACKET_ARP == type) { - - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify -cnt = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", - type); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - } - - if (coex_sta->wifi_is_high_pri_task) { - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_SCAN, true); - halbtc8723d1ant_run_coexist_mechanism(btcoexist); - } -} - -void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean wifi_scan = false, wifi_link = false, wifi_roam = false, - wifi_busy = false; - static boolean is_scoreboard_scan = false; - - if (psd_scan->is_AntDet_running == true) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt_info_notify return for AntDet is running\n"); - BTC_TRACE(trace_buf); - return; - } - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8723D_1ANT_MAX) - rsp_source = BT_INFO_SRC_8723D_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; - coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; - coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; - - if (BT_INFO_SRC_8723D_1ANT_WIFI_FW != rsp_source) { - - /* if 0xff, it means BT is under WHCK test */ - coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true : - false); - - coex_sta->bt_create_connection = (( - coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true : - false); - - /* unit: %, value-100 to translate to unit: dBm */ - coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + - 10; - - coex_sta->c2h_bt_remote_name_req = (( - coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true : - false); - - coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & - 0x10) ? true : false); - - coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & - 0x9) ? true : false); - - coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? - true : false); - - coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & - BT_INFO_8723D_1ANT_B_INQ_PAGE) ? true : false); - - coex_sta->a2dp_bit_pool = ((( - coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? - coex_sta->bt_info_c2h[rsp_source][6] : 0); - - coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & - 0xf; - - coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; - - coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; - - coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; - - coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->c2h_bt_remote_name_req) - coex_sta->cnt_RemoteNameReq++; - - if (coex_sta->bt_info_ext & BIT(1)) - coex_sta->cnt_ReInit++; - - if (coex_sta->bt_info_ext & BIT(2)) { - coex_sta->cnt_setupLink++; - coex_sta->is_setupLink = true; - } else - coex_sta->is_setupLink = false; - - if (coex_sta->bt_info_ext & BIT(3)) - coex_sta->cnt_IgnWlanAct++; - - if (coex_sta->bt_info_ext & BIT(6)) - coex_sta->cnt_RoleSwitch++; - - if (coex_sta->bt_create_connection) { - coex_sta->cnt_Page++; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, - &wifi_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); - - if ((wifi_link) || (wifi_roam) || (wifi_scan) || - (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { - - is_scoreboard_scan = true; - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_SCAN, true); - - } else - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_SCAN, false); - - } else { - if (is_scoreboard_scan) { - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_SCAN, false); - is_scoreboard_scan = false; - } - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - - if ((!btcoexist->manual_control) && - (!btcoexist->stop_coex_dm)) { - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* Re-Init */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - if (wifi_connected) - halbtc8723d1ant_update_wifi_channel_info( - btcoexist, BTC_MEDIA_CONNECT); - else - halbtc8723d1ant_update_wifi_channel_info( - btcoexist, - BTC_MEDIA_DISCONNECT); - } - - - /* If Ignore_WLanAct && not SetUp_Link or Role_Switch */ - if ((coex_sta->bt_info_ext & BIT(3)) && - (!(coex_sta->bt_info_ext & BIT(2))) && - (!(coex_sta->bt_info_ext & BIT(6)))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8723d1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } else { - if (coex_sta->bt_info_ext & BIT(2)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ignore Wlan active because Re-link!!\n"); - BTC_TRACE(trace_buf); - } else if (coex_sta->bt_info_ext & BIT(6)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ignore Wlan active because Role-Switch!!\n"); - BTC_TRACE(trace_buf); - } - } - } - - } - - if ((coex_sta->bt_info_ext & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); - BTC_TRACE(trace_buf); - coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist); - - if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) - coex_sta->bt_ble_scan_para[0] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x1); - if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) - coex_sta->bt_ble_scan_para[1] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x2); - if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) - coex_sta->bt_ble_scan_para[2] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x4); - } - - halbtc8723d1ant_update_bt_link_info(btcoexist); - - halbtc8723d1ant_run_coexist_mechanism(btcoexist); -} - - - -void ex_halbtc8723d1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; -#if 0 - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE, true); - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ONOFF, true); -#endif - - } else if (BTC_RF_OFF == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE | - BT_8723D_1ANT_SCOREBOARD_ONOFF | - BT_8723D_1ANT_SCOREBOARD_SCAN | - BT_8723D_1ANT_SCOREBOARD_UNDERTEST, - false); - - halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_WLAN_OFF); - - btcoexist->stop_coex_dm = true; - } -} - -void ex_halbtc8723d1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE | - BT_8723D_1ANT_SCOREBOARD_ONOFF | - BT_8723D_1ANT_SCOREBOARD_SCAN | - BT_8723D_1ANT_SCOREBOARD_UNDERTEST, - false); - - halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8723D_1ANT_PHASE_WLAN_OFF); - - halbtc8723d1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8723d1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8723d1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if ((BTC_WIFI_PNP_SLEEP == pnp_state) || - (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE | - BT_8723D_1ANT_SCOREBOARD_ONOFF | - BT_8723D_1ANT_SCOREBOARD_SCAN | - BT_8723D_1ANT_SCOREBOARD_UNDERTEST, - false); - - if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { - - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - } else { - - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_WLAN_OFF); - } - - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); -#if 0 - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ACTIVE, true); - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_ONOFF, true); -#endif - btcoexist->stop_coex_dm = false; - } -} - - -void ex_halbtc8723d1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], *****************Coex DM Reset*****************\n"); - BTC_TRACE(trace_buf); - - halbtc8723d1ant_init_hw_config(btcoexist, false, false); - halbtc8723d1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist) -{ - - struct btc_board_info *board_info = &btcoexist->board_info; - boolean wifi_busy = false; - u4Byte value = 0; - u32 bt_patch_ver; - static u8 cnt = 0; - boolean bt_relink_finish = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ************* Periodical *************\n"); - BTC_TRACE(trace_buf); - -#if (BT_AUTO_REPORT_ONLY_8723D_1ANT == 0) - halbtc8723d1ant_query_bt_info(btcoexist); - -#endif - - halbtc8723d1ant_monitor_bt_ctr(btcoexist); - halbtc8723d1ant_monitor_wifi_ctr(btcoexist); - - halbtc8723d1ant_monitor_bt_enable_disable(btcoexist); - -#if 0 - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* halbtc8723d1ant_read_score_board(btcoexist, &bt_scoreboard_val); */ - - if (wifi_busy) { - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_UNDERTEST, true); - /* - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_WLBUSY, true); - - if (bt_scoreboard_val & BIT(6)) - halbtc8723d1ant_query_bt_info(btcoexist); */ - } else { - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_UNDERTEST, false); - /* - halbtc8723d1ant_post_state_to_bt(btcoexist, - BT_8723D_1ANT_SCOREBOARD_WLBUSY, - false); */ - } -#endif - - if (coex_sta->bt_relink_downcount != 0) { - coex_sta->bt_relink_downcount--; - - if (coex_sta->bt_relink_downcount == 0) - bt_relink_finish = true; - } - - /* for 4-way, DHCP, EAPOL packet */ - if (coex_sta->specific_pkt_period_cnt > 0) { - - coex_sta->specific_pkt_period_cnt--; - - if ((coex_sta->specific_pkt_period_cnt == 0) && - (coex_sta->wifi_is_high_pri_task)) - coex_sta->wifi_is_high_pri_task = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", - (coex_sta->wifi_is_high_pri_task ? "Yes" : - "No")); - BTC_TRACE(trace_buf); - - } - - if (!coex_sta->bt_disabled) { - if (coex_sta->bt_coex_supported_feature == 0) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, - &coex_sta->bt_coex_supported_feature); - - if ((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, - &coex_sta->bt_coex_supported_version); - - if (coex_sta->bt_reg_vendor_ac == 0xffff) - coex_sta->bt_reg_vendor_ac = (u16)( - btcoexist->btc_get_bt_reg(btcoexist, 3, - 0xac) & 0xffff); - - if (coex_sta->bt_reg_vendor_ae == 0xffff) - coex_sta->bt_reg_vendor_ae = (u16)( - btcoexist->btc_get_bt_reg(btcoexist, 3, - 0xae) & 0xffff); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, - &bt_patch_ver); - btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; - - if (coex_sta->num_of_profile > 0) { - cnt++; - - if (cnt >= 3) { - btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, - &coex_sta->bt_afh_map[0]); - cnt = 0; - } - } - -#if BT_8723D_1ANT_ANTDET_ENABLE - - if (board_info->btdm_ant_det_finish) { - if ((psd_scan->ant_det_result == 12) && - (psd_scan->ant_det_psd_scan_peak_val == 0) - && (!psd_scan->is_AntDet_running)) { - psd_scan->ant_det_psd_scan_peak_val = - btcoexist->btc_get_ant_det_val_from_bt( - btcoexist) * 100; - - board_info->antdetval = psd_scan->ant_det_psd_scan_peak_val/100; - value = board_info->antdetval; - -#ifdef PLATFORM_WINDOWS - { - PWCHAR registryName; - - registryName = L"antdetval"; - PlatformWriteCommonDwordRegistry(registryName, &value); - } -#endif - } - } - -#endif - } - - if (halbtc8723d1ant_is_wifibt_status_changed(btcoexist)) - halbtc8723d1ant_run_coexist_mechanism(btcoexist); - - -} - -void ex_halbtc8723d1ant_set_antenna_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (type == 2) { /* two antenna */ - board_info->ant_div_cfg = true; - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - } else { /* one antenna */ - halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - } -} - -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - - static u32 ant_det_count = 0, ant_det_fail_count = 0; - struct btc_board_info *board_info = &btcoexist->board_info; - u16 u16tmp; - u8 AntDetval = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Ext Call AntennaDetect()!!\n"); - BTC_TRACE(trace_buf); - -#if BT_8723D_1ANT_ANTDET_ENABLE - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Call AntennaDetect()!!\n"); - BTC_TRACE(trace_buf); - - if (seconds == 0) { - psd_scan->ant_det_try_count = 0; - psd_scan->ant_det_fail_count = 0; - ant_det_count = 0; - ant_det_fail_count = 0; - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - return; - } - - if (!board_info->btdm_ant_det_finish) { - psd_scan->ant_det_inteval_count = - psd_scan->ant_det_inteval_count + 2; - - if (psd_scan->ant_det_inteval_count >= - BT_8723D_2ANT_ANTDET_RETRY_INTERVAL) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n"); - BTC_TRACE(trace_buf); - - psd_scan->is_AntDet_running = true; - - halbtc8723d1ant_read_score_board(btcoexist, &u16tmp); - - if (u16tmp & BIT( - 2)) { /* Antenna detection is already done before last WL power on */ - board_info->btdm_ant_det_finish = true; - psd_scan->ant_det_try_count = 1; - psd_scan->ant_det_fail_count = 0; - board_info->btdm_ant_num_by_ant_det = (u16tmp & - BIT(3)) ? 1 : 2; - psd_scan->ant_det_result = 12; - - psd_scan->ant_det_psd_scan_peak_val = - btcoexist->btc_get_ant_det_val_from_bt( - btcoexist) * 100; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Result from BT (%d-Ant)\n", - board_info->btdm_ant_num_by_ant_det); - BTC_TRACE(trace_buf); - } else - board_info->btdm_ant_det_finish = - halbtc8723d1ant_psd_antenna_detection_check( - btcoexist); - - board_info->ant_det_result = psd_scan->ant_det_result; - btcoexist->bdontenterLPS = false; - - if (board_info->btdm_ant_det_finish) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n"); - BTC_TRACE(trace_buf); - - if (board_info->btdm_ant_num_by_ant_det == 2) { - board_info->ant_div_cfg = true; - halbtc8723d1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_WIFI, FORCE_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - } else - halbtc8723d1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8723D_1ANT_PHASE_2G_RUNTIME); - - /*for 8723d, btc_set_bt_trx_mask is just used to - notify BT stop le tx and Ant Det Result , not set BT RF TRx Mask */ - if (psd_scan->ant_det_result != 12) { - - AntDetval = (u8)( - psd_scan->ant_det_psd_scan_peak_val - / 100) & 0x7f; - - AntDetval = - (board_info->btdm_ant_num_by_ant_det - == 1) ? (AntDetval | 0x80) : - AntDetval; - board_info->antdetval = AntDetval; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxx AntennaDetect(), Ant Count = %d, PSD Val = %d\n", - ((AntDetval & - 0x80) ? 1 - : 2), AntDetval - & 0x7f); - BTC_TRACE(trace_buf); - - if (btcoexist->btc_set_bt_trx_mask( - btcoexist, AntDetval)) - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask ok!\n"); - else - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask fail!\n"); - - BTC_TRACE(trace_buf); - } else - board_info->antdetval = - psd_scan->ant_det_psd_scan_peak_val/100; - - board_info->btdm_ant_det_complete_fail = false; - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n"); - BTC_TRACE(trace_buf); - - board_info->btdm_ant_det_complete_fail = true; - } - - psd_scan->ant_det_inteval_count = 0; - psd_scan->is_AntDet_running = false; - /* stimulate coex running */ - halbtc8723d1ant_run_coexist_mechanism( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n", - psd_scan->ant_det_inteval_count); - BTC_TRACE(trace_buf); - - if (psd_scan->ant_det_inteval_count == 8) - btcoexist->bdontenterLPS = true; - else - btcoexist->bdontenterLPS = false; - } - - } -#endif - - -} - - -void ex_halbtc8723d1ant_display_ant_detection(IN struct btc_coexist *btcoexist) -{ -#if BT_8723D_1ANT_ANTDET_ENABLE - struct btc_board_info *board_info = &btcoexist->board_info; - - if (psd_scan->ant_det_try_count != 0) { - halbtc8723d1ant_psd_show_antenna_detect_result(btcoexist); - - if (board_info->btdm_ant_det_finish) - halbtc8723d1ant_psd_showdata(btcoexist); - } -#endif - -} - -void ex_halbtc8723d1ant_antenna_isolation(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - - -} - -void ex_halbtc8723d1ant_psd_scan(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - - -} - - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ - diff --git a/hal/btc/halbtc8723d1ant.h b/hal/btc/halbtc8723d1ant.h deleted file mode 100644 index a8fb447..0000000 --- a/hal/btc/halbtc8723d1ant.h +++ /dev/null @@ -1,427 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8723D_SUPPORT == 1) - -/* ******************************************* - * The following is for 8723D 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_8723D_1ANT_COEX_DBG 0 -#define BT_AUTO_REPORT_ONLY_8723D_1ANT 1 - -#define BT_INFO_8723D_1ANT_B_FTP BIT(7) -#define BT_INFO_8723D_1ANT_B_A2DP BIT(6) -#define BT_INFO_8723D_1ANT_B_HID BIT(5) -#define BT_INFO_8723D_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8723D_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8723D_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8723D_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8723D_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8723D_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT 2 - -#define BT_8723D_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ -#define BT_8723D_1ANT_DEFAULT_ISOLATION 15 /* unit: dB */ - - -/* for Antenna detection */ -#define BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 -#define BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 -#define BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 -#define BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT 35 -#define BT_8723D_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8723D_1ANT_ANTDET_SWEEPPOINT_DELAY 60000 -#define BT_8723D_1ANT_ANTDET_ENABLE 1 -#define BT_8723D_1ANT_ANTDET_BTTXTIME 100 -#define BT_8723D_1ANT_ANTDET_BTTXCHANNEL 39 -#define BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT 50 - -#define BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 - -enum bt_8723d_1ant_signal_state { - BT_8723D_1ANT_SIG_STA_SET_TO_LOW = 0x0, - BT_8723D_1ANT_SIG_STA_SET_BY_HW = 0x0, - BT_8723D_1ANT_SIG_STA_SET_TO_HIGH = 0x1, - BT_8723D_1ANT_SIG_STA_MAX -}; - -enum bt_8723d_1ant_path_ctrl_owner { - BT_8723D_1ANT_PCO_BTSIDE = 0x0, - BT_8723D_1ANT_PCO_WLSIDE = 0x1, - BT_8723D_1ANT_PCO_MAX -}; - -enum bt_8723d_1ant_gnt_ctrl_type { - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, - BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW = 0x1, - BT_8723D_1ANT_GNT_TYPE_MAX -}; - -enum bt_8723d_1ant_gnt_ctrl_block { - BT_8723D_1ANT_GNT_BLOCK_RFC_BB = 0x0, - BT_8723D_1ANT_GNT_BLOCK_RFC = 0x1, - BT_8723D_1ANT_GNT_BLOCK_BB = 0x2, - BT_8723D_1ANT_GNT_BLOCK_MAX -}; - -enum bt_8723d_1ant_lte_coex_table_type { - BT_8723D_1ANT_CTT_WL_VS_LTE = 0x0, - BT_8723D_1ANT_CTT_BT_VS_LTE = 0x1, - BT_8723D_1ANT_CTT_MAX -}; - -enum bt_8723d_1ant_lte_break_table_type { - BT_8723D_1ANT_LBTT_WL_BREAK_LTE = 0x0, - BT_8723D_1ANT_LBTT_BT_BREAK_LTE = 0x1, - BT_8723D_1ANT_LBTT_LTE_BREAK_WL = 0x2, - BT_8723D_1ANT_LBTT_LTE_BREAK_BT = 0x3, - BT_8723D_1ANT_LBTT_MAX -}; - -enum bt_info_src_8723d_1ant { - BT_INFO_SRC_8723D_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8723D_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8723D_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8723D_1ANT_MAX -}; - -enum bt_8723d_1ant_bt_status { - BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8723D_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8723D_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8723D_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8723D_1ANT_BT_STATUS_MAX -}; - -enum bt_8723d_1ant_wifi_status { - BT_8723D_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8723D_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8723D_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8723D_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8723D_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8723D_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8723d_1ant_coex_algo { - BT_8723D_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8723D_1ANT_COEX_ALGO_SCO = 0x1, - BT_8723D_1ANT_COEX_ALGO_HID = 0x2, - BT_8723D_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8723D_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8723D_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8723D_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8723D_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8723D_1ANT_COEX_ALGO_MAX = 0xb, -}; - -enum bt_8723d_1ant_phase { - BT_8723D_1ANT_PHASE_COEX_INIT = 0x0, - BT_8723D_1ANT_PHASE_WLANONLY_INIT = 0x1, - BT_8723D_1ANT_PHASE_WLAN_OFF = 0x2, - BT_8723D_1ANT_PHASE_2G_RUNTIME = 0x3, - BT_8723D_1ANT_PHASE_5G_RUNTIME = 0x4, - BT_8723D_1ANT_PHASE_BTMPMODE = 0x5, - BT_8723D_1ANT_PHASE_ANTENNA_DET = 0x6, - BT_8723D_1ANT_PHASE_COEX_POWERON = 0x7, - BT_8723D_1ANT_PHASE_MAX -}; - -enum bt_8723d_1ant_Scoreboard { - BT_8723D_1ANT_SCOREBOARD_ACTIVE = BIT(0), - BT_8723D_1ANT_SCOREBOARD_ONOFF = BIT(1), - BT_8723D_1ANT_SCOREBOARD_SCAN = BIT(2), - BT_8723D_1ANT_SCOREBOARD_UNDERTEST = BIT(3), - BT_8723D_1ANT_SCOREBOARD_WLBUSY = BIT(6) -}; - -struct coex_dm_8723d_1ant { - /* hw setting */ - u8 pre_ant_pos_type; - u8 cur_ant_pos_type; - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u8 error_condition; -}; - -struct coex_sta_8723d_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - boolean bt_hi_pri_link_exist; - u8 num_of_profile; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - boolean is_hiPri_rx_overhead; - s8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - u8 bt_info_c2h[BT_INFO_SRC_8723D_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8723D_1ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_remote_name_req; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - u8 bt_retry_cnt; - u8 bt_info_ext; - u8 bt_info_ext2; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; - - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; - u8 coex_table_type; - - boolean force_lps_on; - - boolean concurrent_rx_mode_on; - - u16 score_board; - u8 isolation_btween_wb; /* 0~ 50 */ - - u8 a2dp_bit_pool; - u8 cut_version; - boolean acl_busy; - boolean bt_create_connection; - - u32 bt_coex_supported_feature; - u32 bt_coex_supported_version; - - u8 bt_ble_scan_type; - u32 bt_ble_scan_para[3]; - - boolean run_time_state; - boolean freeze_coexrun_by_btinfo; - - boolean is_A2DP_3M; - boolean voice_over_HOGP; - u8 bt_info; - boolean is_autoslot; - u8 forbidden_slot; - u8 hid_busy_num; - u8 hid_pair_cnt; - - u32 cnt_RemoteNameReq; - u32 cnt_setupLink; - u32 cnt_ReInit; - u32 cnt_IgnWlanAct; - u32 cnt_Page; - u32 cnt_RoleSwitch; - - u16 bt_reg_vendor_ac; - u16 bt_reg_vendor_ae; - - boolean is_setupLink; - u8 wl_noisy_level; - u32 gnt_error_cnt; - - u8 bt_afh_map[10]; - u8 bt_relink_downcount; - boolean is_tdma_btautoslot; - boolean is_tdma_btautoslot_hang; -}; - -#define BT_8723D_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ -#define BT_8723D_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ -#define BT_8723D_1ANT_ANTDET_BUF_LEN 16 - -struct psdscan_sta_8723d_1ant { - - u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ - u32 ant_det_bt_tx_time; - u32 ant_det_pre_psdscan_peak_val; - boolean ant_det_is_ant_det_available; - u32 ant_det_psd_scan_peak_val; - boolean ant_det_is_btreply_available; - u32 ant_det_psd_scan_peak_freq; - - u8 ant_det_result; - u8 ant_det_peak_val[BT_8723D_1ANT_ANTDET_BUF_LEN]; - u8 ant_det_peak_freq[BT_8723D_1ANT_ANTDET_BUF_LEN]; - u32 ant_det_try_count; - u32 ant_det_fail_count; - u32 ant_det_inteval_count; - u32 ant_det_thres_offset; - - u32 real_cent_freq; - s32 real_offset; - u32 real_span; - - u32 psd_band_width; /* unit: Hz */ - u32 psd_point; /* 128/256/512/1024 */ - u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_start_point; - u32 psd_stop_point; - u32 psd_max_value_point; - u32 psd_max_value; - u32 psd_max_value2; - u32 psd_avg_value; /* filter loop_max_value that below BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/ - u32 psd_loop_max_value[BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT]; /*max value in each loop */ - u32 psd_start_base; - u32 psd_avg_num; /* 1/8/16/32 */ - u32 psd_gen_count; - boolean is_AntDet_running; - boolean is_psd_show_max_only; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8723d1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8723d1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8723d1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d1ant_set_antenna_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8723d1ant_antenna_isolation(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); - -void ex_halbtc8723d1ant_psd_scan(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8723d1ant_display_ant_detection(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8723d1ant_power_on_setting(btcoexist) -#define ex_halbtc8723d1ant_pre_load_firmware(btcoexist) -#define ex_halbtc8723d1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8723d1ant_init_coex_dm(btcoexist) -#define ex_halbtc8723d1ant_ips_notify(btcoexist, type) -#define ex_halbtc8723d1ant_lps_notify(btcoexist, type) -#define ex_halbtc8723d1ant_scan_notify(btcoexist, type) -#define ex_halbtc8723d1ant_connect_notify(btcoexist, type) -#define ex_halbtc8723d1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8723d1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8723d1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8723d1ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8723d1ant_halt_notify(btcoexist) -#define ex_halbtc8723d1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8723d1ant_coex_dm_reset(btcoexist) -#define ex_halbtc8723d1ant_periodical(btcoexist) -#define ex_halbtc8723d1ant_display_coex_info(btcoexist) -#define ex_halbtc8723d1ant_set_antenna_notify(btcoexist, type) -#define ex_halbtc8723d1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8723d1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8723d1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8723d1ant_display_ant_detection(btcoexist) -#endif - -#endif - diff --git a/hal/btc/halbtc8723d2ant.c b/hal/btc/halbtc8723d2ant.c deleted file mode 100644 index 318b8ec..0000000 --- a/hal/btc/halbtc8723d2ant.c +++ /dev/null @@ -1,6820 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for RTL8723D Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8723D_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8723d_2ant glcoex_dm_8723d_2ant; -static struct coex_dm_8723d_2ant *coex_dm = &glcoex_dm_8723d_2ant; -static struct coex_sta_8723d_2ant glcoex_sta_8723d_2ant; -static struct coex_sta_8723d_2ant *coex_sta = &glcoex_sta_8723d_2ant; -static struct psdscan_sta_8723d_2ant gl_psd_scan_8723d_2ant; -static struct psdscan_sta_8723d_2ant *psd_scan = &gl_psd_scan_8723d_2ant; - -const char *const glbt_info_src_8723d_2ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; -/* ************************************************************ - * BtCoex Version Format: - * 1. date : glcoex_ver_date_XXXXX_1ant - * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant - * 3. BtCoexVersion : glcoex_ver_btdesired_XXXXX_1ant - * 4. others : glcoex_ver_XXXXXX_XXXXX_1ant - * - * Variable should be indicated IC and Antenna numbers !!! - * Please strictly follow this order and naming style !!! - * - * ************************************************************ */ -u32 glcoex_ver_date_8723d_2ant = 20161108; -u32 glcoex_ver_8723d_2ant = 0x10; -u32 glcoex_ver_btdesired_8723d_2ant = 0x10; - - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8723d2ant_ - * ************************************************************ */ -u8 halbtc8723d2ant_bt_rssi_state(u8 *ppre_bt_rssi_state, u8 level_num, - u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = *ppre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return *ppre_bt_rssi_state; - } - - if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - *ppre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8723d2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh, - IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = *pprewifi_rssi_state; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || - (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return *pprewifi_rssi_state; - } - - if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || - (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - *pprewifi_rssi_state = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8723d2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist, - IN u8 isolation_measuared) -{ - s8 interference_wl_tx = 0, interference_bt_tx = 0; - - - interference_wl_tx = BT_8723D_2ANT_WIFI_MAX_TX_POWER - - isolation_measuared; - interference_bt_tx = BT_8723D_2ANT_BT_MAX_TX_POWER - - isolation_measuared; - - - - coex_sta->wifi_coex_thres = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; - coex_sta->wifi_coex_thres2 = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES2; - - coex_sta->bt_coex_thres = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1; - coex_sta->bt_coex_thres2 = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES2; - - - /* - coex_sta->wifi_coex_thres = interference_wl_tx + BT_8723D_2ANT_WIFI_SIR_THRES1; - coex_sta->wifi_coex_thres2 = interference_wl_tx + BT_8723D_2ANT_WIFI_SIR_THRES2; - - coex_sta->bt_coex_thres = interference_bt_tx + BT_8723D_2ANT_BT_SIR_THRES1; - coex_sta->bt_coex_thres2 = interference_bt_tx + BT_8723D_2ANT_BT_SIR_THRES2; - */ - - - - - - /* - if ( BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - - BT_8723D_2ANT_DEFAULT_ISOLATION) ) - coex_sta->wifi_coex_thres = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; - else - coex_sta->wifi_coex_thres = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 - (isolation_measuared - - BT_8723D_2ANT_DEFAULT_ISOLATION); - - if ( BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - - BT_8723D_2ANT_DEFAULT_ISOLATION) ) - coex_sta->bt_coex_thres = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1; - else - coex_sta->bt_coex_thres = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1 - (isolation_measuared - - BT_8723D_2ANT_DEFAULT_ISOLATION); - - */ -} - - -void halbtc8723d2ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); -} - -void halbtc8723d2ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -void halbtc8723d2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, - cnt_autoslot_hang = 0; - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if (BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - - if (coex_sta->high_priority_rx >= 15) { - if (cnt_overhead < 3) - cnt_overhead++; - - if (cnt_overhead == 3) - coex_sta->is_hiPri_rx_overhead = true; - } else { - if (cnt_overhead > 0) - cnt_overhead--; - - if (cnt_overhead == 0) - coex_sta->is_hiPri_rx_overhead = false; - } - } - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - if ((coex_sta->low_priority_tx > 1050) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - if ((coex_sta->low_priority_rx >= 950) && - (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) - && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && - (coex_sta->bt_link_exist)) { - if (cnt_slave >= 2) { - bt_link_info->slave_role = true; - cnt_slave = 2; - } else - cnt_slave++; - } else { - if (cnt_slave == 0) { - bt_link_info->slave_role = false; - cnt_slave = 0; - } else - cnt_slave--; - - } - - if (coex_sta->is_tdma_btautoslot) { - if ((coex_sta->low_priority_tx >= 1300) && - (coex_sta->low_priority_rx <= 150)) { - if (cnt_autoslot_hang >= 2) { - coex_sta->is_tdma_btautoslot_hang = true; - cnt_autoslot_hang = 2; - } else - cnt_autoslot_hang++; - } else { - if (cnt_autoslot_hang == 0) { - coex_sta->is_tdma_btautoslot_hang = false; - cnt_autoslot_hang = 0; - } else - cnt_autoslot_hang--; - } - } - - if (!coex_sta->bt_disabled) { - - if ((coex_sta->high_priority_tx == 0) && - (coex_sta->high_priority_rx == 0) && - (coex_sta->low_priority_tx == 0) && - (coex_sta->low_priority_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8723d2ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; - } - } - } - -} - -void halbtc8723d2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ -#if 1 - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false, - wifi_scan = false; - boolean bt_idle = false, wl_idle = false; - static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, - wl_noisy_count1 = 3, wl_noisy_count2 = 0; - u32 total_cnt, reg_val1, reg_val2, cck_cnt; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_VHT); - - cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; - - if (cck_cnt > 250) { - if (wl_noisy_count2 < 3) - wl_noisy_count2++; - - if (wl_noisy_count2 == 3) { - wl_noisy_count0 = 0; - wl_noisy_count1 = 0; - } - } else if (cck_cnt < 50) { - if (wl_noisy_count0 < 3) - wl_noisy_count0++; - - if (wl_noisy_count0 == 3) { - wl_noisy_count1 = 0; - wl_noisy_count2 = 0; - } - } else { - if (wl_noisy_count1 < 3) - wl_noisy_count1++; - - if (wl_noisy_count1 == 3) { - wl_noisy_count0 = 0; - wl_noisy_count2 = 0; - } - } - - if (wl_noisy_count2 == 3) - coex_sta->wl_noisy_level = 2; - else if (wl_noisy_count1 == 3) - coex_sta->wl_noisy_level = 1; - else - coex_sta->wl_noisy_level = 0; - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht; - - if ((coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 3) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = true; - - coex_sta->pre_ccklock = coex_sta->cck_lock; - -#endif -} - -void halbtc8723d2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - boolean bt_busy = false; - - - coex_sta->num_of_profile = 0; - - /* set link exist status */ - if (!(coex_sta->bt_info & BT_INFO_8723D_2ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_FTP) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = false; - - if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_A2DP) { - coex_sta->a2dp_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = false; - - if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_HID) { - coex_sta->hid_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = false; - - if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) { - coex_sta->sco_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = false; - - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->acl_busy = coex_sta->acl_busy; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; - - if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_INQ_PAGE) { - coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_INQ_PAGE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); - } else if (!(coex_sta->bt_info & BT_INFO_8723D_2ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - } else if (coex_sta->bt_info == BT_INFO_8723D_2ANT_B_CONNECTION) { - /* connection exists but no busy */ - coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - } else if (((coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) || - (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_BUSY)) && - (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_ACL_BUSY)) { - coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); - } else if ((coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) || - (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - } else if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - } else { - coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - } - - BTC_TRACE(trace_buf); - - if ((BT_8723D_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8723D_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); -} - -void halbtc8723d2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = - 0x1; /* enable BT AFH skip WL channel for 8723d because BT Rx LO interference */ - /* h2c_parameter[0] = 0x0; */ - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); - -} - -void halbtc8723d2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - -void halbtc8723d2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8723d2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - -void halbtc8723d2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN u8 dec_bt_pwr_lvl) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = dec_bt_pwr_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); -} - -void halbtc8723d2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 dec_bt_pwr_lvl) -{ - coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; - - if (!force_exec) { - if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) - return; - } - halbtc8723d2ant_set_fw_dec_bt_pwr(btcoexist, - coex_dm->cur_bt_dec_pwr_lvl); - - coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; -} - -void halbtc8723d2ant_set_fw_low_penalty_ra(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ -#if 1 - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -#endif -} - -void halbtc8723d2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ -#if 1 - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - - halbtc8723d2ant_set_fw_low_penalty_ra(btcoexist, - coex_dm->cur_low_penalty_ra); - -#if 0 - if (low_penalty_ra) - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15); - else - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); -#endif - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; - -#endif -} - -void halbtc8723d2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8723d2ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8723d2ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8723d2ant_write_score_board( - IN struct btc_coexist *btcoexist, - IN u16 bitpos, - IN boolean state -) -{ - - static u16 originalval = 0x8002; - - if (state) - originalval = originalval | bitpos; - else - originalval = originalval & (~bitpos); - - - btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); - -} - -void halbtc8723d2ant_read_score_board( - IN struct btc_coexist *btcoexist, - IN u16 *score_board_val -) -{ - - *score_board_val = (btcoexist->btc_read_2byte(btcoexist, - 0xaa)) & 0x7fff; -} - - -void halbtc8723d2ant_post_state_to_bt( - IN struct btc_coexist *btcoexist, - IN u16 type, - IN boolean state -) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8723d2ant_post_state_to_bt: type = %d, state =%d\n", - type, state); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_write_score_board(btcoexist, (u16) type, state); - -} - -boolean halbtc8723d2ant_is_wifibt_status_changed(IN struct btc_coexist - *btcoexist) -{ - - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false, pre_bt_off = false, pre_bt_slave = false; - static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (coex_sta->bt_disabled != pre_bt_off) { - pre_bt_off = coex_sta->bt_disabled; - - if (coex_sta->bt_disabled) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - - BTC_TRACE(trace_buf); - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - coex_sta->bt_ble_scan_type = 0; - coex_sta->bt_ble_scan_para[0] = 0; - coex_sta->bt_ble_scan_para[1] = 0; - coex_sta->bt_ble_scan_para[2] = 0; - coex_sta->bt_reg_vendor_ac = 0xffff; - coex_sta->bt_reg_vendor_ae = 0xffff; - return true; - } - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - - if (wifi_busy) - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_UNDERTEST, true); - else - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_UNDERTEST, false); - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { - pre_wl_noisy_level = coex_sta->wl_noisy_level; - return true; - } - } - - if (!coex_sta->bt_disabled) { - if (coex_sta->hid_busy_num != pre_hid_busy_num) { - pre_hid_busy_num = coex_sta->hid_busy_num; - return true; - } - } - - if (bt_link_info->slave_role != pre_bt_slave) { - pre_bt_slave = bt_link_info->slave_role; - return true; - } - - return false; -} - -void halbtc8723d2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - u16 u16tmp; - - /* This function check if bt is disabled */ -#if 0 - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - - -#else - - /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */ - halbtc8723d2ant_read_score_board(btcoexist, &u16tmp); - - bt_active = u16tmp & BIT(1); - - -#endif - - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } else { - - bt_disable_cnt++; - if (bt_disable_cnt >= 2) { - bt_disabled = true; - bt_disable_cnt = 2; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } - - if (bt_disabled) - halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); - else - halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true); - - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - } - -} - - - -void halbtc8723d2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, - boolean isenable) -{ -#if BT_8723D_2ANT_COEX_DBG - if (isenable) { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); - - /* enable GNT_BT to GPIO debug */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0); - - /* 0x48[20] = 0 for GPIO14 = GNT_WL*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x0); - /* 0x40[17] = 0 for GPIO14 = GNT_WL*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, 0x02, 0x0); - - /* 0x66[9] = 0 for GPIO15 = GNT_BT*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x02, 0x0); - /* 0x66[7] = 0 - for GPIO15 = GNT_BT*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, 0x80, 0x0); - /* 0x8[8] = 0 for GPIO15 = GNT_BT*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x9, 0x1, 0x0); - - /* BT Vendor Reg 0x76[0] = 0 for GPIO15 = GNT_BT, this is not set here*/ - } else { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); - - /* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1); - - /* 0x48[20] = 0 for GPIO14 = GNT_WL*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x1); - } - -#endif -} - -u32 halbtc8723d2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, - IN u16 reg_addr) -{ - u32 j = 0; - - - /* wait for ready bit before access 0x7c0 */ - btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr); - - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x7c3)&BIT(5)) == 0) && - (j < BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - return btcoexist->btc_read_4byte(btcoexist, - 0x7c8); /* get read data */ - -} - -void halbtc8723d2ant_ltecoex_indirect_write_reg(IN struct btc_coexist - *btcoexist, - IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) -{ - u32 val, i = 0, j = 0, bitpos = 0; - - - if (bit_mask == 0x0) - return; - if (bit_mask == 0xffffffff) { - btcoexist->btc_write_4byte(btcoexist, 0x7c4, - reg_value); /* put write data */ - - /* wait for ready bit before access 0x7c0 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x7c3)&BIT(5)) == 0) && - (j < BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x7c0, - 0xc00F0000 | reg_addr); - } else { - for (i = 0; i <= 31; i++) { - if (((bit_mask >> i) & 0x1) == 0x1) { - bitpos = i; - break; - } - } - - /* read back register value before write */ - val = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - reg_addr); - val = (val & (~bit_mask)) | (reg_value << bitpos); - - btcoexist->btc_write_4byte(btcoexist, 0x7c4, - val); /* put write data */ - - /* wait for ready bit before access 0x7c0 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x7c3)&BIT(5)) == 0) && - (j < BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x7c0, - 0xc00F0000 | reg_addr); - - } - -} - -void halbtc8723d2ant_ltecoex_enable(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 val; - - val = (enable) ? 1 : 0; - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, - val); /* 0x38[7] */ - -} - -void halbtc8723d2ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, - IN boolean wifi_control) -{ - u8 val; - - val = (wifi_control) ? 1 : 0; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, - val); /* 0x70[26] */ - -} - -void halbtc8723d2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, val_orig = 0; - - if (!sw_control) - val = 0x0; - else if (state & 0x1) - val = 0x3; - else - val = 0x1; - - val_orig = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - switch (control_block) { - case BT_8723D_2ANT_GNT_BLOCK_RFC_BB: - default: - val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff); - break; - case BT_8723D_2ANT_GNT_BLOCK_RFC: - val = (val << 14) | (val_orig & 0xffff3fff); - break; - case BT_8723D_2ANT_GNT_BLOCK_BB: - val = (val << 10) | (val_orig & 0xfffff3ff); - break; - } - - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); -} - - -void halbtc8723d2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, val_orig = 0; - - if (!sw_control) - val = 0x0; - else if (state & 0x1) - val = 0x3; - else - val = 0x1; - - val_orig = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - switch (control_block) { - case BT_8723D_2ANT_GNT_BLOCK_RFC_BB: - default: - val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff); - break; - case BT_8723D_2ANT_GNT_BLOCK_RFC: - val = (val << 12) | (val_orig & 0xffffcfff); - break; - case BT_8723D_2ANT_GNT_BLOCK_BB: - val = (val << 8) | (val_orig & 0xfffffcff); - break; - } - - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); -} - -void halbtc8723d2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u16 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8723D_2ANT_CTT_WL_VS_LTE: - reg_addr = 0xa0; - break; - case BT_8723D_2ANT_CTT_BT_VS_LTE: - reg_addr = 0xa4; - break; - } - - if (reg_addr != 0x0000) - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ - - -} - - -void halbtc8723d2ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u8 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8723D_2ANT_LBTT_WL_BREAK_LTE: - reg_addr = 0xa8; - break; - case BT_8723D_2ANT_LBTT_BT_BREAK_LTE: - reg_addr = 0xac; - break; - case BT_8723D_2ANT_LBTT_LTE_BREAK_WL: - reg_addr = 0xb0; - break; - case BT_8723D_2ANT_LBTT_LTE_BREAK_BT: - reg_addr = 0xb4; - break; - } - - if (reg_addr != 0x0000) - halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ - - -} - -void halbtc8723d2ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 interval, - IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, - IN u8 val0x6c4_b3) -{ - static u8 pre_h2c_parameter[6] = {0}; - u8 cur_h2c_parameter[6] = {0}; - u8 i, match_cnt = 0; - - cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ - - cur_h2c_parameter[1] = interval; - cur_h2c_parameter[2] = val0x6c4_b0; - cur_h2c_parameter[3] = val0x6c4_b1; - cur_h2c_parameter[4] = val0x6c4_b2; - cur_h2c_parameter[5] = val0x6c4_b3; - - if (!force_exec) { - for (i = 1; i <= 5; i++) { - if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) - break; - - match_cnt++; - } - - if (match_cnt == 5) - return; - } - - for (i = 1; i <= 5; i++) - pre_h2c_parameter[i] = cur_h2c_parameter[i]; - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); -} - -void halbtc8723d2ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8723d2ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8723d2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8723d2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - u32 break_table; - u8 select_table; - - coex_sta->coex_table_type = type; - - if (coex_sta->concurrent_rx_mode_on == true) { - break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ - select_table = - 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ - } else { - break_table = 0xffffff; - select_table = 0x3; - } - - switch (type) { - case 0: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0xffffffff, 0xffffffff, break_table, select_table); - break; - case 1: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, select_table); - break; - case 2: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table); - break; - case 3: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0xaa555555, 0xaa5a5a5a, break_table, select_table); - break; - case 4: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, select_table); - break; - case 5: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, break_table, select_table); - break; - case 6: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xfafafafa, break_table, select_table); - break; - case 7: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xaa5a5a5a, break_table, select_table); - break; - case 8: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xfafafafa, break_table, select_table); - break; - case 9: - halbtc8723d2ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaaaa5aaa, break_table, select_table); - break; - default: - break; - } -} - -void halbtc8723d2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8723d2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8723d2ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8723d2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8723d2ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8723d2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8723d2ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - u8 h2c_parameter[5] = {0, 0, 0, 0x40, 0}; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - /*halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - /*halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8);*/ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8723d2ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8723d2ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8723d2ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8723d2ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - - - -void halbtc8723d2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - if (byte5 & BIT(2)) - coex_sta->is_tdma_btautoslot = true; - else - coex_sta->is_tdma_btautoslot = false; - - /* release bt-auto slot for auto-slot hang is detected!! */ - if (coex_sta->is_tdma_btautoslot) - if ((coex_sta->is_tdma_btautoslot_hang) || - (bt_link_info->slave_role)) - byte5 = byte5 & 0xfb; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - - halbtc8723d2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - } - } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - - halbtc8723d2ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } else { - halbtc8723d2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, - 0x0); - } - - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8723d2ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - - static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist)) - psTdmaByte4Modify = 0x1; - else - psTdmaByte4Modify = 0x0; - - if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { - - force_exec = true; - pre_psTdmaByte4Modify = psTdmaByte4Modify; - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - - if (turn_on) { - switch (type) { - case 1: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x91, - 0x54 | psTdmaByte4Modify); - break; - case 2: - default: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, - 0x11 | psTdmaByte4Modify); - break; - case 3: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x3a, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); - break; - case 4: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x21, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); - break; - case 5: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); - break; - case 6: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); - break; - case 7: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); - break; - case 8: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x15, 0x03, 0x11, - 0x11); - break; - case 10: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x30, 0x03, 0x11, - 0x10); - break; - case 11: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, - 0x10 | psTdmaByte4Modify); - break; - case 12: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, 0x11); - break; - case 13: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x1c, 0x03, 0x11, - 0x10 | psTdmaByte4Modify); - break; - case 14: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x03, 0x11, - 0x11); - break; - case 15: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x11, - 0x14); - break; - case 16: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x11, - 0x15); - break; - case 21: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x30, 0x03, 0x11, - 0x10); - break; - case 22: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, - 0x10); - break; - case 23: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x11, - 0x10); - break; - case 51: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x91, - 0x10 | psTdmaByte4Modify); - break; - case 101: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, - 0x10, 0x03, 0x10, - 0x54 | psTdmaByte4Modify); - break; - case 102: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, - 0x11 | psTdmaByte4Modify); - break; - case 103: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, - 0x3a, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 104: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, - 0x21, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 105: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, - 0x25, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 106: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, - 0x10, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 107: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, - 0x20, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 108: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 109: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x55, - 0x10, 0x03, 0x10, - 0x54 | psTdmaByte4Modify); - break; - case 110: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x55, - 0x30, 0x03, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 111: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x65, - 0x25, 0x03, 0x11, - 0x11 | psTdmaByte4Modify); - break; - case 151: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51, - 0x10, 0x03, 0x10, - 0x50 | psTdmaByte4Modify); - break; - } - } else { - /* disable PS tdma */ - switch (type) { - case 0: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - case 1: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - default: - halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8723d2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, - IN u8 phase) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u32 u32tmp = 0; - boolean pg_ext_switch = false, is_hw_ant_div_on = false; - u8 h2c_parameter[2] = {0}; - u32 cnt_bt_cal_chk = 0; - u8 u8tmp0 = 0, u8tmp1 = 0; - boolean is_in_mp_mode = false; - u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0; - u16 u16tmp0 = 0, u16tmp1 = 0; - - - u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - /* To avoid indirect access fail */ - if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { - force_exec = true; - coex_sta->gnt_error_cnt++; - } - - -#if BT_8723D_2ANT_COEX_DBG - u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa); - u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948); - u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x73); - u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before Set Ant Pat)\n", - u8tmp0, u16tmp1, u8tmp1); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa = 0x%x (Before Set Ant Path)\n", - u32tmp1, u32tmp2, u16tmp0); - BTC_TRACE(trace_buf); -#endif - - coex_dm->cur_ant_pos_type = ant_pos_type; - - if (!force_exec) { - if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Skip Antenna Path Setup because no change!!**********\n"); - BTC_TRACE(trace_buf); - return; - } - } - - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; - - switch (phase) { - case BT_8723D_2ANT_PHASE_COEX_POWERON: - /* Set Path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, - 0x80, 0x0); - - /* set Path control owner to WL at initial step */ - halbtc8723d2ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_2ANT_PCO_BTSIDE); - - /* set GNT_BT to SW high */ - halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW low */ - halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_WIFI; - - coex_sta->run_time_state = false; - - break; - case BT_8723D_2ANT_PHASE_COEX_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8723d2ant_ltecoex_set_coex_table( - btcoexist, - BT_8723D_2ANT_CTT_WL_VS_LTE, - 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8723d2ant_ltecoex_set_coex_table( - btcoexist, - BT_8723D_2ANT_CTT_BT_VS_LTE, - 0xffff); - - /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ - while (cnt_bt_cal_chk <= 20) { - u8tmp0 = btcoexist->btc_read_1byte( - btcoexist, - 0x49d); - cnt_bt_cal_chk++; - if (u8tmp0 & BIT(0)) { - BTC_SPRINTF( - trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", - cnt_bt_cal_chk); - BTC_TRACE( - trace_buf); - delay_ms(50); - } else { - BTC_SPRINTF( - trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", - cnt_bt_cal_chk); - BTC_TRACE( - trace_buf); - break; - } - } - - - /* Set Path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0x67, 0x80, 0x1); - - /* set Path control owner to WL at initial step */ - halbtc8723d2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8723D_2ANT_PCO_WLSIDE); - - /* set GNT_BT to SW high */ - halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW high */ - halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); - - coex_sta->run_time_state = false; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; - else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; - } - - break; - case BT_8723D_2ANT_PHASE_WLANONLY_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8723d2ant_ltecoex_set_coex_table( - btcoexist, - BT_8723D_2ANT_CTT_WL_VS_LTE, - 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8723d2ant_ltecoex_set_coex_table( - btcoexist, - BT_8723D_2ANT_CTT_BT_VS_LTE, - 0xffff); - - /* Set Path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0x67, 0x80, 0x1); - - /* set Path control owner to WL at initial step */ - halbtc8723d2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8723D_2ANT_PCO_WLSIDE); - - /* set GNT_BT to SW Low */ - halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_2ANT_SIG_STA_SET_TO_LOW); - /* Set GNT_WL to SW high */ - halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); - - coex_sta->run_time_state = false; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; - else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; - } - - break; - case BT_8723D_2ANT_PHASE_WLAN_OFF: - /* Disable LTE Coex Function in WiFi side */ - halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0); - - /* Set Path control to BT */ - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0x67, 0x80, 0x0); - - /* set Path control owner to BT */ - halbtc8723d2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8723D_2ANT_PCO_BTSIDE); - - coex_sta->run_time_state = false; - break; - case BT_8723D_2ANT_PHASE_2G_RUNTIME: - - /* wait for WL/BT IQK finish, keep 0x38 = 0xff00 for WL IQK */ - while (cnt_bt_cal_chk <= 20) { - u8tmp0 = btcoexist->btc_read_1byte( - btcoexist, - 0x1e6); - - u8tmp1 = btcoexist->btc_read_1byte( - btcoexist, - 0x49d); - - cnt_bt_cal_chk++; - if ((u8tmp0 & BIT(0)) || - (u8tmp1 & BIT(0))) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### WL or BT is IQK (wait cnt=%d)\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - delay_ms(50); - } else { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - break; - } - } - - /* Set Path control to WL */ - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);*/ - - /* set Path control owner to WL at runtime step */ - halbtc8723d2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8723D_2ANT_PCO_WLSIDE); - - - halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); - - /* Set GNT_WL to PTA */ - halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8723D_2ANT_SIG_STA_SET_BY_HW); - - coex_sta->run_time_state = true; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; - else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; - } - - break; - case BT_8723D_2ANT_PHASE_BTMPMODE: - /* Disable LTE Coex Function in WiFi side */ - halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0); - - /* Set Path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0x67, 0x80, 0x1); - - /* set Path control owner to WL */ - halbtc8723d2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8723D_2ANT_PCO_WLSIDE); - - /* set GNT_BT to SW Hi */ - halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); - - /* Set GNT_WL to SW Lo */ - halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_2ANT_SIG_STA_SET_TO_LOW); - - coex_sta->run_time_state = false; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; - else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; - } - - break; - case BT_8723D_2ANT_PHASE_ANTENNA_DET: - - /* Set Path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, - 0x80, 0x1); - - /* set Path control owner to WL */ - halbtc8723d2ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8723D_2ANT_PCO_WLSIDE); - - /* Set Antenna Path, both GNT_WL/GNT_BT = 1, and control by SW */ - /* set GNT_BT to SW high */ - halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); - - /* Set GNT_WL to SW high */ - halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8723D_2ANT_GNT_BLOCK_RFC_BB, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8723D_2ANT_SIG_STA_SET_TO_HIGH); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_WIFI_AT_AUX; - - coex_sta->run_time_state = false; - - break; - } - - is_hw_ant_div_on = board_info->ant_div_cfg; - - if ((is_hw_ant_div_on) && (phase != BT_8723D_2ANT_PHASE_ANTENNA_DET)) - btcoexist->btc_write_2byte(btcoexist, 0x948, 0x140); - else if ((is_hw_ant_div_on == false) && - (phase != BT_8723D_2ANT_PHASE_WLAN_OFF)) { - - switch (ant_pos_type) { - case BTC_ANT_WIFI_AT_MAIN: - - btcoexist->btc_write_2byte(btcoexist, - 0x948, 0x0); - break; - case BTC_ANT_WIFI_AT_AUX: - - btcoexist->btc_write_2byte(btcoexist, - 0x948, 0x280); - break; - } - } - - -#if BT_8723D_2ANT_COEX_DBG - u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa); - u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948); - u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x73); - u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(After Set Ant Pat)\n", - u8tmp0, u16tmp1, u8tmp1); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa= 0x%x (After Set Ant Path)\n", - u32tmp1, u32tmp2, u16tmp0); - BTC_TRACE(trace_buf); -#endif - -} - -u8 halbtc8723d2ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8723D_2ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 0) { - - if (bt_link_info->acl_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No-Profile busy\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY; - } - } else if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_2ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_2ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_2ANT_COEX_ALGO_SCO; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP ==> A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_PANEDR; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_HID_A2DP; - } - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_2ANT_COEX_ALGO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP ==> HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8723D_2ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_PANEDR_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } - - return algorithm; -} - - - -void halbtc8723d2ant_action_coex_all_off(IN struct btc_coexist *btcoexist) -{ - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* fw all off */ - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8723d2ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) -{ - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); -} - -void halbtc8723d2ant_action_bt_hs(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false, wifi_turbo = false; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - - wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - - } else { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } - -} - - -void halbtc8723d2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - - boolean wifi_connected = false; - boolean wifi_scan = false, wifi_link = false, wifi_roam = false; - boolean wifi_busy = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); - - if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) - || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 8); - - if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 15); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 11); - } else if ((!wifi_connected) && (!wifi_scan)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi no-link + no-scan + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (bt_link_info->pan_exist) { - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - } else { - - if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) - || (coex_sta->wifi_is_high_pri_task)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - } - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); -} - - -void halbtc8723d2ant_action_bt_relink(IN struct btc_coexist *btcoexist) -{ - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8); - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - coex_sta->bt_relink_downcount = 2; -} - -void halbtc8723d2ant_action_bt_idle(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_busy) { - - halbtc8723d2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - } else { /* if wl busy */ - - if (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - - halbtc8723d2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else { - - halbtc8723d2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 12); - } - } - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - -} - - - -/* SCO only or SCO+PAN(HS) */ -void halbtc8723d2ant_action_sco(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 1); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8); - } - -} - - -void halbtc8723d2ant_action_hid(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; - u32 wifi_bw = 1; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - /*for 4/18 hid */ - if (coex_sta->hid_busy_num >= 2) { - if (wifi_bw == 0) { /* if 11bg mode */ - - halbtc8723d2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 111); - } else { - - if (wifi_busy) { - halbtc8723d2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 111); - } else { - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 3); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - } - } - } else { - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 3); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - } - } - -} - - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false, wifi_turbo = false; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 1); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 16); - } else { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if ((coex_sta->bt_relink_downcount != 0) - && (wifi_busy)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - - } else { - - if (wifi_turbo) - halbtc8723d2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - else - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 7); - - if (wifi_busy) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 101); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 16); - /*halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 102);*/ - } - - } - -} - - -void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false, wifi_turbo = false; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - -#if 0 - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); -#endif - - -#if 1 - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 3); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 4); - } else { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if (wifi_turbo) - halbtc8723d2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - else - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 7); - - if (wifi_busy) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 103); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 104); - - } - -#endif - -} - -void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 1); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 16); - } else { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if ((coex_sta->bt_relink_downcount != 0) - && (wifi_busy)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else if (wifi_busy) { - if (coex_sta->hid_busy_num >= 2) { - halbtc8723d2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - if (wifi_bw == 0) /*11bg mode */ - halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - else - halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 109); - } else { - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 101); - } - } else { - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 1); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 16); - } - - } - -} - - -void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false, wifi_turbo = false; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - - wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 7); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 5); - } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 6); - - } else { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if (wifi_turbo) - halbtc8723d2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - else - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 7); - - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 107); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 105); - } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 106); - - } - -} - - -/* PAN(EDR)+A2DP */ -void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false, wifi_turbo = false; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - - wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) { - - if (((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) || - (!coex_sta->is_A2DP_3M)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 7); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 5); - } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 6); - } else { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if (wifi_turbo) - halbtc8723d2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - else - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 7); - - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 107); - else if (wifi_turbo) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 108); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 105); - } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 106); - - } - -} - - -void halbtc8723d2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 3); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 4); - } else { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if (coex_sta->hid_busy_num >= 2) { - - halbtc8723d2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - if (wifi_bw == 0) /*11bg mode */ - halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - else - halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 110); - } else { - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - - if (wifi_busy) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 103); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 104); - } - - } - -} - - -/* HID+A2DP+PAN(EDR) */ -void halbtc8723d2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) { - - if (((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) || - (!coex_sta->is_A2DP_3M)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 7); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 5); - } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 6); - } else { - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if (coex_sta->hid_busy_num >= 2) { - halbtc8723d2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - if (wifi_bw == 0) /*11bg mode */ - halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - else - halbtc8723d2ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 110); - } else { - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 107); - else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 105); - } else - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 106); - } - } - -} - - -void halbtc8723d2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* hw all off */ - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); -} - -void halbtc8723d2ant_action_wifi_linkscan_process(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - if (bt_link_info->pan_exist) { - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - } else { - - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - } - -} - -void halbtc8723d2ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* fw all off */ - halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8723d2ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - switch (coex_dm->cur_algorithm) { - - case BT_8723D_2ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_sco(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_hid(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_a2dp(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_pan_edr(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_pan_edr_hid(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_hid_a2dp(btcoexist); - break; - case BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_bt_idle(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_coex_all_off(btcoexist); - break; - } - - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - -} - - -void halbtc8723d2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - u32 num_of_wifi_link = 0; - u32 wifi_link_status = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean miracast_plus_bt = false; - boolean scan = false, link = false, roam = false, - under_4way = false, - wifi_connected = false, wifi_under_5g = false, - bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (!coex_sta->run_time_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], return for run_time_state = false !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->freeze_coexrun_by_btinfo) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_bt_whql_test(btcoexist); - return; - } - - if (coex_sta->bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled!!!\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_coex_all_off(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_bt_inquiry(btcoexist); - return; - } - - if (coex_sta->is_setupLink) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is re-link !!!\n"); - halbtc8723d2ant_action_bt_relink(btcoexist); - return; - } - - /* for P2P */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) - miracast_plus_bt = true; - else - miracast_plus_bt = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", - scan, link, roam, under_4way); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_action_wifi_linkscan_process(btcoexist); - } else - halbtc8723d2ant_action_wifi_multi_port(btcoexist); - - return; - } else { - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is hs\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_bt_hs(btcoexist); - return; - } - - if ((BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || - (BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, bt idle!!.\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_action_bt_idle(btcoexist); - return; - } - - algorithm = halbtc8723d2ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", - coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under Link Process !!\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_wifi_linkscan_process(btcoexist); - } else if (wifi_connected) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, wifi connected!!.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_wifi_connected(btcoexist); - - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, wifi not-connected!!.\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_action_wifi_not_connected(btcoexist); - } -} - - -void halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18); - halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); - - coex_sta->pop_event_cnt = 0; - coex_sta->cnt_RemoteNameReq = 0; - coex_sta->cnt_ReInit = 0; - coex_sta->cnt_setupLink = 0; - coex_sta->cnt_IgnWlanAct = 0; - coex_sta->cnt_Page = 0; - - halbtc8723d2ant_query_bt_info(btcoexist); -} - - -void halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - u8 u8tmp0 = 0, u8tmp1 = 0; - u32 vendor; - u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0; - u16 u16tmp1 = 0; - u8 i = 0; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - -#if BT_8723D_2ANT_COEX_DBG - u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0x54); - u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948); - u8tmp1 = btcoexist->btc_read_1byte(btcoexist, 0x73); - u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before init_hw_config)\n", - u8tmp0, u16tmp1, u8tmp1); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], **********0x38= 0x%x, 0x54= 0x%x (Before init_hw_config)\n", - u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif - - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - coex_sta->bt_ble_scan_type = 0; - coex_sta->bt_ble_scan_para[0] = 0; - coex_sta->bt_ble_scan_para[1] = 0; - coex_sta->bt_ble_scan_para[2] = 0; - coex_sta->bt_reg_vendor_ac = 0xffff; - coex_sta->bt_reg_vendor_ae = 0xffff; - coex_sta->gnt_error_cnt = 0; - coex_sta->bt_relink_downcount = 0; - - for (i = 0; i <= 9; i++) - coex_sta->bt_afh_map[i] = 0; - -#if 0 - btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor); - if (vendor == BTC_VENDOR_LENOVO) - coex_dm->switch_thres_offset = 0; - else - coex_dm->switch_thres_offset = 20; -#endif - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - coex_sta->dis_ver_info_cnt = 0; - - /* default isolation = 15dB */ - coex_sta->isolation_btween_wb = BT_8723D_2ANT_DEFAULT_ISOLATION; - halbtc8723d2ant_coex_switch_threshold(btcoexist, - coex_sta->isolation_btween_wb); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - - /* BT report packet sample rate */ - btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); - - /* Init 0x778 = 0x1 for 2-Ant */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - - /* Enable PTA (3-wire function form BT side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); - - /* Enable PTA (tx/rx signal form WiFi side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); - - halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, true); - -#if 0 - /* check if WL firmware download ok */ - if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ONOFF, true); -#endif - - /* Enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, - 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ - - /* WLAN_Tx by GNT_WL 0x950[29] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0); - - halbtc8723d2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - halbtc8723d2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - - psd_scan->ant_det_is_ant_det_available = true; - - if (wifi_only) { - coex_sta->concurrent_rx_mode_on = false; - /* Path config */ - /* Set Antenna Path */ - halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_WLANONLY_INIT); - - btcoexist->stop_coex_dm = true; - } else { - /*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); - - coex_sta->concurrent_rx_mode_on = true; - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */ - - /* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0); - - /* Path config */ - halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_COEX_INIT); - - btcoexist->stop_coex_dm = false; - } - - -} - -u32 halbtc8723d2ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val) -{ - u8 j; - u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0; - u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200, - 174, 151, 132, 115, 100, 86, 74, 62, 51, 42, - 32, 23, 15, 7, 0 - }; - - if (val == 0) - return 0; - - tmp = val; - - while (1) { - if (tmp == 1) - break; - else { - tmp = (tmp >> 1); - shiftcount++; - } - } - - - val_integerd_b = shiftcount + 1; - - tmp2 = 1; - for (j = 1; j <= val_integerd_b; j++) - tmp2 = tmp2 * 2; - - tmp = (val * 100) / tmp2; - tindex = tmp / 5; - - if (tindex > 20) - tindex = 20; - - val_fractiond_b = table_fraction[tindex]; - - result = val_integerd_b * 100 - val_fractiond_b; - - return result; - - -} - -void halbtc8723d2ant_psd_show_antenna_detect_result(IN struct btc_coexist - *btcoexist) -{ - u8 *cli_buf = btcoexist->cli_buf; - struct btc_board_info *board_info = &btcoexist->board_info; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n============[Antenna Detection info] ============\n"); - CL_PRINTF(cli_buf); - - if (psd_scan->ant_det_result == 12) { /* Get Ant Det from BT */ - - if (board_info->btdm_ant_num_by_ant_det == 1) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (%d~%d)", - "Ant Det Result", "1-Antenna", - BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT, - BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION); - else { - - if (psd_scan->ant_det_psd_scan_peak_val > - (BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION) - * 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (>%d)", - "Ant Det Result", "2-Antenna (Bad-Isolation)", - BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (%d~%d)", - "Ant Det Result", "2-Antenna (Good-Isolation)", - BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset, - BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); - } - - } else if (psd_scan->ant_det_result == 1) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)", - "Ant Det Result", "2-Antenna (Bad-Isolation)", - BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); - else if (psd_scan->ant_det_result == 2) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)", - "Ant Det Result", "2-Antenna (Good-Isolation)", - BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset, - BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)", - "Ant Det Result", "1-Antenna", - BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT, - BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset); - - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ", - "Antenna Detection Finish", - (board_info->btdm_ant_det_finish - ? "Yes" : "No")); - CL_PRINTF(cli_buf); - - switch (psd_scan->ant_det_result) { - case 0: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is not available)"); - break; - case 1: /* 2-Ant bad-isolation */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available)"); - break; - case 2: /* 2-Ant good-isolation */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available)"); - break; - case 3: /* 1-Ant */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available)"); - break; - case 4: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(Uncertainty result)"); - break; - case 5: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(Pre-Scan fai)"); - break; - case 6: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(WiFi is Scanning)"); - break; - case 7: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is not idle)"); - break; - case 8: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(Abort by WiFi Scanning)"); - break; - case 9: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(Antenna Init is not ready)"); - break; - case 10: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is Inquiry or page)"); - break; - case 11: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is Disabled)"); - case 12: - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "(BT is available, result from BT"); - break; - } - CL_PRINTF(cli_buf); - - if (psd_scan->ant_det_result == 12) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB", - "PSD Scan Peak Value", - psd_scan->ant_det_psd_scan_peak_val / 100); - CL_PRINTF(cli_buf); - return; - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Ant Detect Total Count", psd_scan->ant_det_try_count); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Ant Detect Fail Count", psd_scan->ant_det_fail_count); - CL_PRINTF(cli_buf); - - if ((!board_info->btdm_ant_det_finish) && - (psd_scan->ant_det_result != 5)) - return; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Response", - (psd_scan->ant_det_result ? "ok" : "fail")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ms", "BT Tx Time", - psd_scan->ant_det_bt_tx_time); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "BT Tx Ch", - psd_scan->ant_det_bt_le_channel); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", - "WiFi PSD Cent-Ch/Offset/Span", - psd_scan->real_cent_freq, psd_scan->real_offset, - psd_scan->real_span); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB", - "PSD Pre-Scan Peak Value", - psd_scan->ant_det_pre_psdscan_peak_val / 100); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (<= %d)", - "PSD Pre-Scan result", - (psd_scan->ant_det_result != 5 ? "ok" : "fail"), - BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset); - CL_PRINTF(cli_buf); - - if (psd_scan->ant_det_result == 5) - return; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s dB", - "PSD Scan Peak Value", psd_scan->ant_det_peak_val); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s MHz", - "PSD Scan Peak Freq", psd_scan->ant_det_peak_freq); - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package", - (board_info->tfbga_package) ? "Yes" : "No"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "PSD Threshold Offset", psd_scan->ant_det_thres_offset); - CL_PRINTF(cli_buf); - -} - -void halbtc8723d2ant_psd_showdata(IN struct btc_coexist *btcoexist) -{ - u8 *cli_buf = btcoexist->cli_buf; - u32 delta_freq_per_point; - u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2; - - if (psd_scan->ant_det_result == 12) - return; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n\n============[PSD info] (%d)============\n", - psd_scan->psd_gen_count); - CL_PRINTF(cli_buf); - - if (psd_scan->psd_gen_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n"); - CL_PRINTF(cli_buf); - return; - } - - if (psd_scan->psd_point == 0) - delta_freq_per_point = 0; - else - delta_freq_per_point = psd_scan->psd_band_width / - psd_scan->psd_point; - - /* if (psd_scan->is_psd_show_max_only) */ - if (0) { - psd_rep1 = psd_scan->psd_max_value / 100; - psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100; - - freq = ((psd_scan->real_cent_freq - 20) * 1000000 + - psd_scan->psd_max_value_point * delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (freq2 < 100) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq = %d.0%d MHz", - freq1, freq2); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n Freq = %d.%d MHz", - freq1, freq2); - - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - ", Value = %d.0%d dB, (%d)\n", - psd_rep1, psd_rep2, psd_scan->psd_max_value); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - ", Value = %d.%d dB, (%d)\n", - psd_rep1, psd_rep2, psd_scan->psd_max_value); - - CL_PRINTF(cli_buf); - } else { - m = psd_scan->psd_start_point; - n = psd_scan->psd_start_point; - i = 1; - j = 1; - - while (1) { - do { - freq = ((psd_scan->real_cent_freq - 20) * - 1000000 + m * - delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (i == 1) { - if (freq2 == 0) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Freq%6d.000", - freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Freq%6d.0%2d", - freq1, - freq2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Freq%6d.%3d", - freq1, - freq2); - } else if ((i % 8 == 0) || - (m == psd_scan->psd_stop_point)) { - if (freq2 == 0) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.000\n", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.0%2d\n", freq1, - freq2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.%3d\n", freq1, - freq2); - } else { - if (freq2 == 0) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.000", freq1); - else if (freq2 < 100) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.0%2d", freq1, - freq2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%6d.%3d", freq1, - freq2); - } - - i++; - m++; - CL_PRINTF(cli_buf); - - } while ((i <= 8) && (m <= psd_scan->psd_stop_point)); - - - do { - psd_rep1 = psd_scan->psd_report_max_hold[n] / - 100; - psd_rep2 = psd_scan->psd_report_max_hold[n] - - psd_rep1 * - 100; - - if (j == 1) { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Val %7d.0%d", - psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "\r\n Val %7d.%d", - psd_rep1, - psd_rep2); - } else if ((j % 8 == 0) || - (n == psd_scan->psd_stop_point)) { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%7d.0%d\n", psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%7d.%d\n", psd_rep1, - psd_rep2); - } else { - if (psd_rep2 < 10) - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%7d.0%d", psd_rep1, - psd_rep2); - else - CL_SPRINTF(cli_buf, - BT_TMP_BUF_SIZE, - "%7d.%d", psd_rep1, - psd_rep2); - } - - j++; - n++; - CL_PRINTF(cli_buf); - - } while ((j <= 8) && (n <= psd_scan->psd_stop_point)); - - if ((m > psd_scan->psd_stop_point) || - (n > psd_scan->psd_stop_point)) - break; - else { - i = 1; - j = 1; - } - - } - } - - -} - -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -void halbtc8723d2ant_psd_maxholddata(IN struct btc_coexist *btcoexist, - IN u32 gen_count) -{ - u32 i = 0; - u32 loop_i_max = 0, loop_val_max = 0; - - if (gen_count == 1) { - memcpy(psd_scan->psd_report_max_hold, - psd_scan->psd_report, - BT_8723D_2ANT_ANTDET_PSD_POINTS * sizeof(u32)); - } - - for (i = psd_scan->psd_start_point; - i <= psd_scan->psd_stop_point; i++) { - - /* update max-hold value at each freq point */ - if (psd_scan->psd_report[i] > psd_scan->psd_report_max_hold[i]) - psd_scan->psd_report_max_hold[i] = - psd_scan->psd_report[i]; - - /* search the max value in this seep */ - if (psd_scan->psd_report[i] > loop_val_max) { - loop_val_max = psd_scan->psd_report[i]; - loop_i_max = i; - } - } - - if (gen_count <= BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT) - psd_scan->psd_loop_max_value[gen_count - 1] = loop_val_max; - -} - - -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -u32 halbtc8723d2ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point) -{ - /* reg 0x808[9:0]: FFT data x */ - /* reg 0x808[22]: 0-->1 to get 1 FFT data y */ - /* reg 0x8b4[15:0]: FFT data y report */ - - u32 val = 0, psd_report = 0; - int k = 0; - - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - - val &= 0xffbffc00; - val |= point; - - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - val |= 0x00400000; - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - while (1) { - if (k++ > BT_8723D_2ANT_ANTDET_SWEEPPOINT_DELAY) - break; - } - - val = btcoexist->btc_read_4byte(btcoexist, 0x8b4); - - psd_report = val & 0x0000ffff; - - return psd_report; -} - -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points, - IN u32 avgnum, IN u32 loopcnt) -{ - u32 i = 0, val = 0, n = 0, k = 0, j, point_index = 0; - u32 points1 = 0, psd_report = 0; - u32 start_p = 0, stop_p = 0, delta_freq_per_point = 156250; - u32 psd_center_freq = 20 * 10 ^ 6; - boolean outloop = false, scan , roam, is_sweep_ok = true; - u8 flag = 0; - u32 tmp = 0, u32tmp1 = 0; - u32 wifi_original_channel = 1; - u32 psd_sum = 0, avg_cnt = 0; - u32 i_max = 0, val_max = 0, val_max2 = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n"); - BTC_TRACE(trace_buf); - - do { - switch (flag) { - case 0: /* Get PSD parameters */ - default: - - psd_scan->psd_band_width = 40 * 1000000; - psd_scan->psd_point = points; - psd_scan->psd_start_base = points / 2; - psd_scan->psd_avg_num = avgnum; - psd_scan->real_cent_freq = cent_freq; - psd_scan->real_offset = offset; - psd_scan->real_span = span; - - - points1 = psd_scan->psd_point; - delta_freq_per_point = psd_scan->psd_band_width / - psd_scan->psd_point; - - /* PSD point setup */ - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - val &= 0xffff0fff; - - switch (psd_scan->psd_point) { - case 128: - val |= 0x0; - break; - case 256: - default: - val |= 0x00004000; - break; - case 512: - val |= 0x00008000; - break; - case 1024: - val |= 0x0000c000; - break; - } - - switch (psd_scan->psd_avg_num) { - case 1: - val |= 0x0; - break; - case 8: - val |= 0x00001000; - break; - case 16: - val |= 0x00002000; - break; - case 32: - default: - val |= 0x00003000; - break; - } - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - flag = 1; - break; - case 1: /* calculate the PSD point index from freq/offset/span */ - psd_center_freq = psd_scan->psd_band_width / 2 + - offset * (1000000); - - start_p = psd_scan->psd_start_base + (psd_center_freq - - span * (1000000) / 2) / delta_freq_per_point; - psd_scan->psd_start_point = start_p - - psd_scan->psd_start_base; - - stop_p = psd_scan->psd_start_base + (psd_center_freq + - span * (1000000) / 2) / delta_freq_per_point; - psd_scan->psd_stop_point = stop_p - - psd_scan->psd_start_base - 1; - - flag = 2; - break; - case 2: /* set RF channel/BW/Mode */ - - /* set 3-wire off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x88c); - val |= 0x00300000; - btcoexist->btc_write_4byte(btcoexist, 0x88c, val); - - /* CCK off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x800); - val &= 0xfeffffff; - btcoexist->btc_write_4byte(btcoexist, 0x800, val); - - /* Tx-pause on */ - btcoexist->btc_write_1byte(btcoexist, 0x522, 0x6f); - - /* store WiFi original channel */ - wifi_original_channel = btcoexist->btc_get_rf_reg( - btcoexist, BTC_RF_A, 0x18, 0x3ff); - - /* Set RF channel */ - if (cent_freq == 2484) - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, - 0x18, 0x3ff, 0xe); - else - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, - 0x18, 0x3ff, (cent_freq - 2412) / 5 + - 1); /* WiFi TRx Mask on */ - - /* save original RCK value */ - u32tmp1 = btcoexist->btc_get_rf_reg( - btcoexist, BTC_RF_A, 0x1d, 0xfffff); - - /* Enter debug mode */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde, - 0x2, 0x1); - - /* Set RF Rx filter corner */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d, - 0xfffff, 0x2e); - - - /* Set RF mode = Rx, RF Gain = 0x320a0 */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0, - 0xfffff, 0x320a0); - - while (1) { - if (k++ > BT_8723D_2ANT_ANTDET_SWEEPPOINT_DELAY) - break; - } - flag = 3; - break; - case 3: - psd_scan->psd_gen_count = 0; - for (j = 1; j <= loopcnt; j++) { - - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || roam) { - is_sweep_ok = false; - break; - } - memset(psd_scan->psd_report, 0, - psd_scan->psd_point * sizeof(u32)); - start_p = psd_scan->psd_start_point + - psd_scan->psd_start_base; - stop_p = psd_scan->psd_stop_point + - psd_scan->psd_start_base + 1; - - i = start_p; - point_index = 0; - - while (i < stop_p) { - if (i >= points1) - psd_report = - halbtc8723d2ant_psd_getdata( - btcoexist, i - points1); - else - psd_report = - halbtc8723d2ant_psd_getdata( - btcoexist, i); - - if (psd_report == 0) - tmp = 0; - else - /* tmp = 20*log10((double)psd_report); */ - /* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */ - tmp = 6 * halbtc8723d2ant_psd_log2base( - btcoexist, psd_report); - - n = i - psd_scan->psd_start_base; - psd_scan->psd_report[n] = tmp; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Point=%d, psd_dB_data = %d\n", - i, psd_scan->psd_report[n]); - BTC_TRACE(trace_buf); - - i++; - - } - - halbtc8723d2ant_psd_maxholddata(btcoexist, j); - - psd_scan->psd_gen_count = j; - - /*Accumulate Max PSD value in this loop if the value > threshold */ - if (psd_scan->psd_loop_max_value[j - 1] >= - 4000) { - psd_sum = psd_sum + - psd_scan->psd_loop_max_value[j - - 1]; - avg_cnt++; - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Loop=%d, Max_dB_data = %d\n", - j, psd_scan->psd_loop_max_value[j - - 1]); - BTC_TRACE(trace_buf); - - } - - if (loopcnt == BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT) { - - /* search the Max Value between each-freq-point-max-hold value of all sweep*/ - for (i = 1; - i <= BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT; - i++) { - - if (i == 1) { - i_max = i; - val_max = psd_scan->psd_loop_max_value[i - - 1]; - val_max2 = - psd_scan->psd_loop_max_value[i - - 1]; - } else if ( - psd_scan->psd_loop_max_value[i - - 1] > val_max) { - val_max2 = val_max; - i_max = i; - val_max = psd_scan->psd_loop_max_value[i - - 1]; - } else if ( - psd_scan->psd_loop_max_value[i - - 1] > val_max2) - val_max2 = - psd_scan->psd_loop_max_value[i - - 1]; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "i = %d, val_hold= %d, val_max = %d, val_max2 = %d\n", - i, psd_scan->psd_loop_max_value[i - - 1], - val_max, val_max2); - - BTC_TRACE(trace_buf); - } - - psd_scan->psd_max_value_point = i_max; - psd_scan->psd_max_value = val_max; - psd_scan->psd_max_value2 = val_max2; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "val_max = %d, val_max2 = %d\n", - psd_scan->psd_max_value, - psd_scan->psd_max_value2); - BTC_TRACE(trace_buf); - } - - if (avg_cnt != 0) { - psd_scan->psd_avg_value = (psd_sum / avg_cnt); - if ((psd_sum % avg_cnt) >= (avg_cnt / 2)) - psd_scan->psd_avg_value++; - } else - psd_scan->psd_avg_value = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "AvgLoop=%d, Avg_dB_data = %d\n", - avg_cnt, psd_scan->psd_avg_value); - BTC_TRACE(trace_buf); - - flag = 100; - break; - case 99: /* error */ - - outloop = true; - break; - case 100: /* recovery */ - - /* set 3-wire on */ - val = btcoexist->btc_read_4byte(btcoexist, 0x88c); - val &= 0xffcfffff; - btcoexist->btc_write_4byte(btcoexist, 0x88c, val); - - /* CCK on */ - val = btcoexist->btc_read_4byte(btcoexist, 0x800); - val |= 0x01000000; - btcoexist->btc_write_4byte(btcoexist, 0x800, val); - - /* Tx-pause off */ - btcoexist->btc_write_1byte(btcoexist, 0x522, 0x0); - - /* PSD off */ - val = btcoexist->btc_read_4byte(btcoexist, 0x808); - val &= 0xffbfffff; - btcoexist->btc_write_4byte(btcoexist, 0x808, val); - - /* restore RF Rx filter corner */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d, - 0xfffff, u32tmp1); - - /* Exit debug mode */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde, - 0x2, 0x0); - - /* restore WiFi original channel */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18, - 0x3ff, wifi_original_channel); - - outloop = true; - break; - - } - - } while (!outloop); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n"); - BTC_TRACE(trace_buf); - return is_sweep_ok; - -} - -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -boolean halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist - *btcoexist) -{ - u32 i = 0; - u32 wlpsd_cent_freq = 2484, wlpsd_span = 2; - s32 wlpsd_offset = -4; - u32 bt_tx_time, bt_le_channel; - u8 bt_le_ch[13] = {3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 33}; - - u8 h2c_parameter[3] = {0}, u8tmpa, u8tmpb; - - u8 state = 0; - boolean outloop = false, bt_resp = false, ant_det_finish = false; - u32 freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point, - u32tmp, u32tmp0, u32tmp1, u32tmp2 ; - struct btc_board_info *board_info = &btcoexist->board_info; - - memset(psd_scan->ant_det_peak_val, 0, 16 * sizeof(u8)); - memset(psd_scan->ant_det_peak_freq, 0, 16 * sizeof(u8)); - - psd_scan->ant_det_bt_tx_time = - BT_8723D_2ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */ - psd_scan->ant_det_bt_le_channel = BT_8723D_2ANT_ANTDET_BTTXCHANNEL; - - bt_tx_time = psd_scan->ant_det_bt_tx_time; - bt_le_channel = psd_scan->ant_det_bt_le_channel; - - if (board_info->tfbga_package) /* for TFBGA */ - psd_scan->ant_det_thres_offset = 5; - else - psd_scan->ant_det_thres_offset = 0; - - do { - switch (state) { - case 0: - if (bt_le_channel == 39) - wlpsd_cent_freq = 2484; - else { - for (i = 1; i <= 13; i++) { - if (bt_le_ch[i - 1] == - bt_le_channel) { - wlpsd_cent_freq = 2412 - + (i - 1) * 5; - break; - } - } - - if (i == 14) { - - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Abort!!, Invalid LE channel = %d\n ", - bt_le_channel); - BTC_TRACE(trace_buf); - outloop = true; - break; - } - } -#if 0 - wlpsd_sweep_count = bt_tx_time * 238 / - 100; /* bt_tx_time/0.42 */ - wlpsd_sweep_count = wlpsd_sweep_count / 5; - - if (wlpsd_sweep_count % 5 != 0) - wlpsd_sweep_count = (wlpsd_sweep_count / - 5 + 1) * 5; -#endif - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n", - bt_tx_time, bt_le_channel); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), wlpsd_cent_freq=%d, wlpsd_offset = %d, wlpsd_span = %d, wlpsd_sweep_count = %d\n", - wlpsd_cent_freq, - wlpsd_offset, - wlpsd_span, - BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT); - BTC_TRACE(trace_buf); - - state = 1; - break; - case 1: /* stop coex DM & set antenna path */ - /* Stop Coex DM */ - btcoexist->stop_coex_dm = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n"); - BTC_TRACE(trace_buf); - - /* Set TDMA off, */ - halbtc8723d2ant_ps_tdma(btcoexist, FORCE_EXEC, - false, 0); - - /* Set coex table */ - halbtc8723d2ant_coex_table_with_type(btcoexist, - FORCE_EXEC, 0); - - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n"); - BTC_TRACE(trace_buf); - } - - /* Set Antenna path, switch WiFi to un-certain antenna port */ - /* Set Antenna Path, both GNT_WL/GNT_BT = 1, and control by SW */ - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_ANTENNA_DET); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n"); - BTC_TRACE(trace_buf); - - /* Set AFH mask on at WiFi channel 2472MHz +/- 10MHz */ - h2c_parameter[0] = 0x1; - h2c_parameter[1] = 0xd; - h2c_parameter[2] = 0x14; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n", - h2c_parameter[1], - h2c_parameter[2]); - BTC_TRACE(trace_buf); - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, - h2c_parameter); - - u32tmp = btcoexist->btc_read_2byte(btcoexist, 0x948); - u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70); - u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg( - btcoexist, 0x38); - u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg( - btcoexist, 0x54); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** 0x948 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (Before Ant Det)\n", - u32tmp, u32tmp0, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - - state = 2; - break; - case 2: /* Pre-sweep background psd */ - if (!halbtc8723d2ant_psd_sweep_point(btcoexist, - wlpsd_cent_freq, wlpsd_offset, wlpsd_span, - BT_8723D_2ANT_ANTDET_PSD_POINTS, - BT_8723D_2ANT_ANTDET_PSD_AVGNUM, 3)) { - ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - psd_scan->ant_det_result = 8; - state = 99; - break; - } - - psd_scan->ant_det_pre_psdscan_peak_val = - psd_scan->psd_max_value; - - if (psd_scan->ant_det_pre_psdscan_peak_val > - (BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset) * 100) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n", - psd_scan->ant_det_pre_psdscan_peak_val / - 100, - BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset); - BTC_TRACE(trace_buf); - ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - psd_scan->ant_det_result = 5; - state = 99; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n", - psd_scan->ant_det_pre_psdscan_peak_val / - 100, - BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND - + psd_scan->ant_det_thres_offset); - BTC_TRACE(trace_buf); - state = 3; - } - break; - case 3: - bt_resp = btcoexist->btc_set_bt_ant_detection( - btcoexist, (u8)(bt_tx_time & 0xff), - (u8)(bt_le_channel & 0xff)); - - /* Sync WL Rx PSD with BT Tx time because H2C->Mailbox delay */ - delay_ms(20); - - if (!halbtc8723d2ant_psd_sweep_point(btcoexist, - wlpsd_cent_freq, wlpsd_offset, - wlpsd_span, - BT_8723D_2ANT_ANTDET_PSD_POINTS, - BT_8723D_2ANT_ANTDET_PSD_AVGNUM, - BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT)) { - ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - psd_scan->ant_det_result = 8; - state = 99; - break; - } - -#if 1 - psd_scan->ant_det_psd_scan_peak_val = - psd_scan->psd_max_value; -#endif -#if 0 - psd_scan->ant_det_psd_scan_peak_val = - ((psd_scan->psd_max_value - psd_scan->psd_avg_value) < - 800) ? - psd_scan->psd_max_value : (( - psd_scan->psd_max_value - - psd_scan->psd_max_value2 <= 300) ? - psd_scan->psd_avg_value : - psd_scan->psd_max_value2); -#endif - psd_scan->ant_det_psd_scan_peak_freq = - psd_scan->psd_max_value_point; - state = 4; - break; - case 4: - - if (psd_scan->psd_point == 0) - delta_freq_per_point = 0; - else - delta_freq_per_point = - psd_scan->psd_band_width / - psd_scan->psd_point; - - psd_rep1 = psd_scan->ant_det_psd_scan_peak_val / 100; - psd_rep2 = psd_scan->ant_det_psd_scan_peak_val - - psd_rep1 * - 100; - - freq = ((psd_scan->real_cent_freq - 20) * - 1000000 + psd_scan->psd_max_value_point - * delta_freq_per_point); - freq1 = freq / 1000000; - freq2 = freq / 1000 - freq1 * 1000; - - if (freq2 < 100) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.0%d MHz", - freq1, freq2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_freq, - BT_8723D_2ANT_ANTDET_BUF_LEN, - "%d.0%d", freq1, freq2); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.%d MHz", - freq1, freq2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_freq, - BT_8723D_2ANT_ANTDET_BUF_LEN, - "%d.%d", freq1, freq2); - } - - if (psd_rep2 < 10) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - ", Value = %d.0%d dB\n", - psd_rep1, psd_rep2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_val, - BT_8723D_2ANT_ANTDET_BUF_LEN, - "%d.0%d", psd_rep1, psd_rep2); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - ", Value = %d.%d dB\n", - psd_rep1, psd_rep2); - BTC_TRACE(trace_buf); - CL_SPRINTF(psd_scan->ant_det_peak_val, - BT_8723D_2ANT_ANTDET_BUF_LEN, - "%d.%d", psd_rep1, psd_rep2); - } - - psd_scan->ant_det_is_btreply_available = true; - - if (bt_resp == false) { - psd_scan->ant_det_is_btreply_available = - false; - psd_scan->ant_det_result = 0; - ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n "); - BTC_TRACE(trace_buf); - } else if (psd_scan->ant_det_psd_scan_peak_val > - (BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION) - * 100) { - psd_scan->ant_det_result = 1; - ant_det_finish = true; - board_info->btdm_ant_num_by_ant_det = 2; - coex_sta->isolation_btween_wb = (u8)(85 - - psd_scan->ant_det_psd_scan_peak_val / - 100) & 0xff; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n"); - BTC_TRACE(trace_buf); - } else if (psd_scan->ant_det_psd_scan_peak_val > - (BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION - + psd_scan->ant_det_thres_offset) * 100) { - psd_scan->ant_det_result = 2; - ant_det_finish = true; - board_info->btdm_ant_num_by_ant_det = 2; - coex_sta->isolation_btween_wb = (u8)(85 - - psd_scan->ant_det_psd_scan_peak_val / - 100) & 0xff; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n"); - BTC_TRACE(trace_buf); - } else if (psd_scan->ant_det_psd_scan_peak_val > - (BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT) * - 100) { - psd_scan->ant_det_result = 3; - ant_det_finish = true; - board_info->btdm_ant_num_by_ant_det = 1; - coex_sta->isolation_btween_wb = (u8)(85 - - psd_scan->ant_det_psd_scan_peak_val / - 100) & 0xff; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n"); - BTC_TRACE(trace_buf); - } else { - psd_scan->ant_det_result = 4; - ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n"); - BTC_TRACE(trace_buf); - } - - state = 99; - break; - case 99: /* restore setup */ - - /* Set AFH mask off at WiFi channel 2472MHz +/- 10MHz */ - h2c_parameter[0] = 0x0; - h2c_parameter[1] = 0x0; - h2c_parameter[2] = 0x0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n", - h2c_parameter[1], h2c_parameter[2]); - BTC_TRACE(trace_buf); - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, - h2c_parameter); - - /* Set Antenna Path, GNT_WL/GNT_BT control by PTA */ - /* Set Antenna path, switch WiFi to certain antenna port */ - halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8723D_2ANT_PHASE_2G_RUNTIME); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!"); - BTC_TRACE(trace_buf); - - outloop = true; - break; - } - - } while (!outloop); - - return ant_det_finish; - -} - -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -boolean halbtc8723d2ant_psd_antenna_detection_check(IN struct btc_coexist - *btcoexist) -{ - static u32 ant_det_count = 0, ant_det_fail_count = 0; - struct btc_board_info *board_info = &btcoexist->board_info; - - boolean scan, roam, ant_det_finish = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - ant_det_count++; - - psd_scan->ant_det_try_count = ant_det_count; - - if (scan || roam) { - ant_det_finish = false; - psd_scan->ant_det_result = 6; - } else if (coex_sta->bt_disabled) { - ant_det_finish = false; - psd_scan->ant_det_result = 11; - } else if (coex_sta->num_of_profile >= 1) { - ant_det_finish = false; - psd_scan->ant_det_result = 7; - } else if ( - !psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */ - ant_det_finish = false; - psd_scan->ant_det_result = 9; - } else if (coex_sta->c2h_bt_inquiry_page) { - ant_det_finish = false; - psd_scan->ant_det_result = 10; - } else { - - ant_det_finish = halbtc8723d2ant_psd_antenna_detection( - btcoexist); - - delay_ms(psd_scan->ant_det_bt_tx_time); - } - - - if (!ant_det_finish) - ant_det_fail_count++; - - psd_scan->ant_det_fail_count = ant_det_fail_count; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), result = %d, fail_count = %d, finish = %s\n", - psd_scan->ant_det_result, - psd_scan->ant_det_fail_count, - ant_det_finish == true ? "Yes" : "No"); - BTC_TRACE(trace_buf); - - return ant_det_finish; - -} - - -/* ************************************************************ - * work around function start with wa_halbtc8723d2ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8723d2ant_ - * ************************************************************ */ -void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x0; - u16 u16tmp = 0x0; - u32 value = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Execute 8723d 2-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Ant Det Finish = %s, Ant Det Number = %d\n", - (board_info->btdm_ant_det_finish ? "Yes" : "No"), - board_info->btdm_ant_num_by_ant_det); - BTC_TRACE(trace_buf); - - - btcoexist->stop_coex_dm = true; - psd_scan->ant_det_is_ant_det_available = false; - - /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - - - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - - /* Set path control to WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1); - btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0); - - /* Check efuse 0xc3[6] for Single Antenna Path */ - if (board_info->single_ant_path == 0) { - /* set to S1 */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - u8tmp = 4; - value = 1; - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - u8tmp = 5; - value = 0; - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d **********\n", - board_info->single_ant_path , board_info->btdm_ant_pos); - BTC_TRACE(trace_buf); - - /* Set Antenna Path to BT side */ - halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_1ANT_PHASE_COEX_POWERON); - - /* Write Single Antenna Position to Registry to tell BT for 872db. This line can be removed - since BT EFuse also add "single antenna position" in EFuse for 8723d*/ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, - &value); - - /* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at power on */ - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); - - /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, true); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n", - halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38)); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0x948 (Power-On) = 0x%x / 0x%x**********\n", - btcoexist->btc_read_4byte(btcoexist, 0x70), - btcoexist->btc_read_2byte(btcoexist, 0x948)); - BTC_TRACE(trace_buf); -} - -void ex_halbtc8723d2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - if (btcoexist->chip_interface == BTC_INTF_USB) { - /* fixed at S0 for USB interface */ - u8tmp |= 0x1; /* antenna inverse */ - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - } else { - /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ - if (board_info->single_ant_path == 0) { - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - u8tmp |= 0x1; /* antenna inverse */ - } - - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, - u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, - u8tmp); - } -} - - -void ex_halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8723d2ant_init_hw_config(btcoexist, wifi_only); -} - -void ex_halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - - halbtc8723d2ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, ps_tdma_case = 0; - u32 u32tmp[4]; - u16 u16tmp[4]; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck, bt_coex_ver = 0; - u32 fw_ver = 0, bt_patch_ver = 0; - static u8 pop_report_in_10s = 0; - u32 phyver = 0; - boolean lte_coex_on = false; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - if (psd_scan->ant_det_try_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s", - "Ant PG Num/ Mech/ Pos", - board_info->pg_ant_num, board_info->btdm_ant_num, - (board_info->btdm_ant_pos == 1 ? "S1" : "S0")); - CL_PRINTF(cli_buf); - } else { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %s (retry=%d/fail=%d/result=%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos", - board_info->pg_ant_num, - board_info->btdm_ant_num_by_ant_det, - (board_info->btdm_ant_pos == 1 ? "S1" : "S0"), - psd_scan->ant_det_try_count, - psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); - CL_PRINTF(cli_buf); - - if (board_info->btdm_ant_det_finish) { - - if (psd_scan->ant_det_result != 12) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d", - "Ant Det PSD Value", - psd_scan->ant_det_psd_scan_peak_val - / 100); - CL_PRINTF(cli_buf); - } - } - - if (board_info->ant_det_result_five_complete) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d", - "AntDet(Registry) Num/PSD Value", - board_info->btdm_ant_num_by_ant_det, - (board_info->antdetval & 0x7f)); - CL_PRINTF(cli_buf); - } - - - bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); - - bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", - "CoexVer WL/ BT_Desired/ BT_Report", - glcoex_ver_date_8723d_2ant, glcoex_ver_8723d_2ant, - glcoex_ver_btdesired_8723d_2ant, - bt_coex_ver, - (bt_coex_ver == 0xff ? "Unknown" : - (coex_sta->bt_disabled ? "BT-disable" : - (bt_coex_ver >= glcoex_ver_btdesired_8723d_2ant ? - "Match" : "Mis-Match")))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", - "W_FW/ B_FW/ Phy/ Kt", - fw_ver, bt_patch_ver, phyver, - coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ", - "Isolation/WL_Thres/BT_Thres", - coex_sta->isolation_btween_wb, - coex_sta->wifi_coex_thres, - coex_sta->bt_coex_thres); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") - : ((BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); - CL_PRINTF(cli_buf); - - if (pop_report_in_10s >= 5) { - coex_sta->pop_event_cnt = 0; - pop_report_in_10s = 0; - } - - - if (coex_sta->num_of_profile != 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s%s%s%s%s", - "Profiles", - ((bt_link_info->a2dp_exist) ? "A2DP," : ""), - ((bt_link_info->sco_exist) ? "SCO," : ""), - ((bt_link_info->hid_exist) ? - ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : - "HID(2/18),") : ""), - ((bt_link_info->pan_exist) ? "PAN," : ""), - ((coex_sta->voice_over_HOGP) ? "Voice" : "")); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = None", - "Profiles"); - - CL_PRINTF(cli_buf); - - - if (bt_link_info->a2dp_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", - "A2DP Rate/Bitpool/Auto_Slot", - ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), - coex_sta->a2dp_bit_pool, - ((coex_sta->is_autoslot) ? "On" : "Off") - ); - CL_PRINTF(cli_buf); - } - - if (bt_link_info->hid_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "HID PairNum/Forbid_Slot", - coex_sta->hid_pair_cnt, - coex_sta->forbidden_slot - ); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ 0x%x/ 0x%x", - "Role/IgnWlanAct/Feature/BLEScan", - ((bt_link_info->slave_role) ? "Slave" : "Master"), - ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), - coex_sta->bt_coex_supported_feature, - coex_sta->bt_ble_scan_type); - CL_PRINTF(cli_buf); - - if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%08x/ 0x%08x/ 0x%08x", - "BLEScan Intv-Win TV/Init/Ble", - (coex_sta->bt_ble_scan_type & 0x1 ? - coex_sta->bt_ble_scan_para[0] : 0x0), - (coex_sta->bt_ble_scan_type & 0x2 ? - coex_sta->bt_ble_scan_para[1] : 0x0), - (coex_sta->bt_ble_scan_type & 0x4 ? - coex_sta->bt_ble_scan_para[2] : 0x0)); - - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", - "ReInit/ReLink/IgnWlact/Page/NameReq", - coex_sta->cnt_ReInit, - coex_sta->cnt_setupLink, - coex_sta->cnt_IgnWlanAct, - coex_sta->cnt_Page, - coex_sta->cnt_RemoteNameReq - ); - CL_PRINTF(cli_buf); - - halbtc8723d2ant_read_score_board(btcoexist, &u16tmp[0]); - - if ((coex_sta->bt_reg_vendor_ae == 0xffff) || - (coex_sta->bt_reg_vendor_ac == 0xffff)) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", - ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), - coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); - CL_PRINTF(cli_buf); - - if (coex_sta->num_of_profile > 0) { - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", - "AFH MAP", - coex_sta->bt_afh_map[0], - coex_sta->bt_afh_map[1], - coex_sta->bt_afh_map[2], - coex_sta->bt_afh_map[3], - coex_sta->bt_afh_map[4], - coex_sta->bt_afh_map[5], - coex_sta->bt_afh_map[6], - coex_sta->bt_afh_map[7], - coex_sta->bt_afh_map[8], - coex_sta->bt_afh_map[9] - ); - CL_PRINTF(cli_buf); - } - - for (i = 0; i < BT_INFO_SRC_8723D_2ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)", - glbt_info_src_8723d_2ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - /* Sw mechanism */ - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanism] (before Manual)============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Mechanism]============"); - - CL_PRINTF(cli_buf); - - - ps_tdma_case = coex_dm->cur_ps_tdma; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, %s)", - "TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"), - (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant")); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", - "Table/0x6c0/0x6c4/0x6c8", - coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x", - "0x778/0x6cc", - u8tmp[0], u32tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", - "AntDiv/ ForceLPS", - ((board_info->ant_div_cfg) ? "On" : "Off"), - ((coex_sta->force_lps_on) ? "On" : "Off")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "WL_DACSwing/ BT_Dec_Pwr", coex_dm->cur_fw_dac_swing_lvl, - coex_dm->cur_bt_dec_pwr_lvl); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? true : false; - - if (lte_coex_on) { - - u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0xa0); - u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0xa4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "LTE Coex Table W_L/B_L", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0xa8); - u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0xac); - u32tmp[2] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0xb0); - u32tmp[3] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, - 0xb4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "LTE Break Table W_L/B_L/L_W/L_B", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, - u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); - CL_PRINTF(cli_buf); - - } - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - /* - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - */ - u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", - "LTE Coex/Path Owner", - ((lte_coex_on) ? "On" : "Off") , - ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); - CL_PRINTF(cli_buf); - - if (lte_coex_on) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %d/ %d", - "LTE 3Wire/OPMode/UART/UARTMode", - (int)((u32tmp[0] & BIT(6)) >> 6), - (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), - (int)((u32tmp[0] & BIT(3)) >> 3), - (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "LTE_Busy/UART_Busy", - (int)((u32tmp[1] & BIT(1)) >> 1), (int)(u32tmp[1] & BIT(0))); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", - "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", - ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), - ((u8tmp[0] & BIT(3)) ? "On" : "Off"), - coex_sta->gnt_error_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "GNT_WL/GNT_BT", - (int)((u32tmp[1] & BIT(2)) >> 2), - (int)((u32tmp[1] & BIT(3)) >> 3)); - CL_PRINTF(cli_buf); - - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x948); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x948/0x67[7]", - u16tmp[0], (int)((u8tmp[0] & BIT(7)) >> 7)); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x964); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x864); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xab7); - u8tmp[3] = btcoexist->btc_read_1byte(btcoexist, 0xa01); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x964[1]/0x864[0]/0xab7[5]/0xa01[7]", - (int)((u8tmp[0] & BIT(1)) >> 1), (int)((u8tmp[1] & BIT(0))), - (int)((u8tmp[2] & BIT(3)) >> 3), - (int)((u8tmp[3] & BIT(7)) >> 7)); - CL_PRINTF(cli_buf); - - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x45e); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x4c6[4]/0x40[5]/0x45e[3](TxRetry)", - (int)((u8tmp[0] & BIT(4)) >> 4), - (int)((u8tmp[1] & BIT(5)) >> 5), - (int)((u8tmp[2] & BIT(3)) >> 3)); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s", - "0x550/0x522/4-RxAGC", - u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off"); - CL_PRINTF(cli_buf); - - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm); - CL_PRINTF(cli_buf); - -#if 1 - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); - CL_PRINTF(cli_buf); -#endif - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "WlHiPri/ Locking/ Locked/ Noisy", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), - (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No"), - coex_sta->wl_noisy_level); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", - "0x770(Hi-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx, - (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : "")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", - "0x774(Lo-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx, - (bt_link_info->slave_role ? "(Slave!!)" : ( - coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); - CL_PRINTF(cli_buf); - - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8723d2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - coex_sta->under_lps = false; - - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE | - BT_8723D_2ANT_SCOREBOARD_ONOFF | - BT_8723D_2ANT_SCOREBOARD_SCAN | - BT_8723D_2ANT_SCOREBOARD_UNDERTEST, - false); - - halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_WLAN_OFF); - - halbtc8723d2ant_action_coex_all_off(btcoexist); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; -#if 0 - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE, true); - - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ONOFF, true); -#endif - halbtc8723d2ant_init_hw_config(btcoexist, false); - halbtc8723d2ant_init_coex_dm(btcoexist); - halbtc8723d2ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8723d2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - coex_sta->under_ips = false; - - if (coex_sta->force_lps_on == true) { /* LPS No-32K */ - /* Write WL "Active" in Score-board for PS-TDMA */ - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE, true); - - } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ - /* Write WL "Non-Active" in Score-board for Native-PS */ - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE, false); - } - - - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE, true); - } -} - -void ex_halbtc8723d2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u32 u32tmp; - u8 u8tmpa, u8tmpb; - boolean wifi_connected = false; - - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* this can't be removed for RF off_on event, or BT would dis-connect */ - halbtc8723d2ant_query_bt_info(btcoexist); - - if (BTC_SCAN_START == type) { - - if (!wifi_connected) - coex_sta->wifi_is_high_pri_task = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE | - BT_8723D_2ANT_SCOREBOARD_SCAN | - BT_8723D_2ANT_SCOREBOARD_ONOFF, - true); - - halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_2G_RUNTIME); - - halbtc8723d2ant_run_coexist_mechanism(btcoexist); - - } else if (BTC_SCAN_FINISH == type) { - - coex_sta->wifi_is_high_pri_task = false; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", - coex_sta->scan_ap_num); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_SCAN, false); - - halbtc8723d2ant_run_coexist_mechanism(btcoexist); - } - -} - -void ex_halbtc8723d2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_ASSOCIATE_START == type) { - - coex_sta->wifi_is_high_pri_task = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE | - BT_8723D_2ANT_SCOREBOARD_SCAN | - BT_8723D_2ANT_SCOREBOARD_ONOFF, - true); - - halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_2G_RUNTIME); - - halbtc8723d2ant_run_coexist_mechanism(btcoexist); - /* To keep TDMA case during connect process, - to avoid changed by Btinfo and runcoexmechanism */ - coex_sta->freeze_coexrun_by_btinfo = true; - - coex_dm->arp_cnt = 0; - - } else if (BTC_ASSOCIATE_FINISH == type) { - - coex_sta->wifi_is_high_pri_task = false; - coex_sta->freeze_coexrun_by_btinfo = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_run_coexist_mechanism(btcoexist); - } -} - -void ex_halbtc8723d2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - u8 ap_num = 0; - boolean wifi_under_b_mode = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_MEDIA_CONNECT == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE | - BT_8723D_2ANT_SCOREBOARD_ONOFF, - true); - - halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_2G_RUNTIME); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE, false); - } - - - halbtc8723d2ant_update_wifi_channel_info(btcoexist, type); -} - -void ex_halbtc8723d2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean under_4way = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (under_4way) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ---- under_4way!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - - } else if (BTC_PACKET_ARP == type) { - - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify -cnt = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", - type); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - } - - if (coex_sta->wifi_is_high_pri_task) { - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE, true); - halbtc8723d2ant_run_coexist_mechanism(btcoexist); - } - -} - -void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean wifi_scan = false, wifi_link = false, wifi_roam = false, - wifi_busy = false; - static boolean is_scoreboard_scan = false; - - if (psd_scan->is_AntDet_running == true) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt_info_notify return for AntDet is running\n"); - BTC_TRACE(trace_buf); - return; - } - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8723D_2ANT_MAX) - rsp_source = BT_INFO_SRC_8723D_2ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; - coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; - coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; - - if (BT_INFO_SRC_8723D_2ANT_WIFI_FW != rsp_source) { - - /* if 0xff, it means BT is under WHCK test */ - coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true : - false); - - coex_sta->bt_create_connection = (( - coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true : - false); - - /* unit: %, value-100 to translate to unit: dBm */ - coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + - 10; - - coex_sta->c2h_bt_remote_name_req = (( - coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true : - false); - - coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & - 0x10) ? true : false); - - coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & - 0x9) ? true : false); - - coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? - true : false); - - coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & - BT_INFO_8723D_2ANT_B_INQ_PAGE) ? true : false); - - coex_sta->a2dp_bit_pool = ((( - coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? - coex_sta->bt_info_c2h[rsp_source][6] : 0); - - coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & - 0xf; - - coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; - - coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; - - coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; - - coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->c2h_bt_remote_name_req) - coex_sta->cnt_RemoteNameReq++; - - if (coex_sta->bt_info_ext & BIT(1)) - coex_sta->cnt_ReInit++; - - if (coex_sta->bt_info_ext & BIT(2)) { - coex_sta->cnt_setupLink++; - coex_sta->is_setupLink = true; - } else - coex_sta->is_setupLink = false; - - if (coex_sta->bt_info_ext & BIT(3)) - coex_sta->cnt_IgnWlanAct++; - - if (coex_sta->bt_create_connection) { - coex_sta->cnt_Page++; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, - &wifi_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); - - if ((wifi_link) || (wifi_roam) || (wifi_scan) || - (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { - - is_scoreboard_scan = true; - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_SCAN, true); - - } else - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_SCAN, false); - - } else { - if (is_scoreboard_scan) { - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_SCAN, false); - is_scoreboard_scan = false; - } - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - - if ((!btcoexist->manual_control) && - (!btcoexist->stop_coex_dm)) { - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* Re-Init */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - if (wifi_connected) - halbtc8723d2ant_update_wifi_channel_info( - btcoexist, BTC_MEDIA_CONNECT); - else - halbtc8723d2ant_update_wifi_channel_info( - btcoexist, - BTC_MEDIA_DISCONNECT); - } - - - /* If Ignore_WLanAct && not SetUp_Link or Role_Switch */ - if ((coex_sta->bt_info_ext & BIT(3)) && - (!(coex_sta->bt_info_ext & BIT(2))) && - (!(coex_sta->bt_info_ext & BIT(6)))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8723d2ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } else { - if (coex_sta->bt_info_ext & BIT(2)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ignore Wlan active because Re-link!!\n"); - BTC_TRACE(trace_buf); - } else if (coex_sta->bt_info_ext & BIT(6)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ignore Wlan active because Role-Switch!!\n"); - BTC_TRACE(trace_buf); - } - } - } - - } - - if ((coex_sta->bt_info_ext & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); - BTC_TRACE(trace_buf); - coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist); - - if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) - coex_sta->bt_ble_scan_para[0] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x1); - if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) - coex_sta->bt_ble_scan_para[1] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x2); - if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) - coex_sta->bt_ble_scan_para[2] = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x4); - } - - halbtc8723d2ant_update_bt_link_info(btcoexist); - - halbtc8723d2ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8723d2ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; -#if 0 - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE, true); - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ONOFF, true); -#endif - } else if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_WLAN_OFF); - - halbtc8723d2ant_action_coex_all_off(btcoexist); - - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE | - BT_8723D_2ANT_SCOREBOARD_ONOFF | - BT_8723D_2ANT_SCOREBOARD_SCAN | - BT_8723D_2ANT_SCOREBOARD_UNDERTEST, - false); - - btcoexist->stop_coex_dm = true; - - } -} - -void ex_halbtc8723d2ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8723d2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_WLAN_OFF); - - ex_halbtc8723d2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE | - BT_8723D_2ANT_SCOREBOARD_ONOFF | - BT_8723D_2ANT_SCOREBOARD_SCAN | - BT_8723D_2ANT_SCOREBOARD_UNDERTEST, - false); -} - -void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if ((BTC_WIFI_PNP_SLEEP == pnp_state) || - (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE | - BT_8723D_2ANT_SCOREBOARD_ONOFF | - BT_8723D_2ANT_SCOREBOARD_SCAN | - BT_8723D_2ANT_SCOREBOARD_UNDERTEST, - false); - - if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { - - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_2G_RUNTIME); - } else { - - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_WLAN_OFF); - } - - - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); -#if 0 - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ACTIVE, true); - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_ONOFF, true); -#endif - } -} - -void ex_halbtc8723d2ant_periodical(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - boolean wifi_busy = false; - u32 bt_patch_ver; - static u8 cnt = 0; - boolean bt_relink_finish = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ************* Periodical *************\n"); - BTC_TRACE(trace_buf); - -#if (BT_AUTO_REPORT_ONLY_8723D_2ANT == 0) - halbtc8723d2ant_query_bt_info(btcoexist); -#endif - - halbtc8723d2ant_monitor_bt_ctr(btcoexist); - halbtc8723d2ant_monitor_wifi_ctr(btcoexist); - halbtc8723d2ant_monitor_bt_enable_disable(btcoexist); - -#if 0 - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* halbtc8723d2ant_read_score_board(btcoexist, &bt_scoreboard_val); */ - - if (wifi_busy) { - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_UNDERTEST, true); - /* - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_WLBUSY, true); - - if (bt_scoreboard_val & BIT(6)) - halbtc8723d2ant_query_bt_info(btcoexist); */ - } else { - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_UNDERTEST, false); - /* - halbtc8723d2ant_post_state_to_bt(btcoexist, - BT_8723D_2ANT_SCOREBOARD_WLBUSY, - false); */ - } -#endif - - if (coex_sta->bt_relink_downcount != 0) { - coex_sta->bt_relink_downcount--; - - if (coex_sta->bt_relink_downcount == 0) - bt_relink_finish = true; - } - - /* for 4-way, DHCP, EAPOL packet */ - if (coex_sta->specific_pkt_period_cnt > 0) { - - coex_sta->specific_pkt_period_cnt--; - - if ((coex_sta->specific_pkt_period_cnt == 0) && - (coex_sta->wifi_is_high_pri_task)) - coex_sta->wifi_is_high_pri_task = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", - (coex_sta->wifi_is_high_pri_task ? "Yes" : - "No")); - BTC_TRACE(trace_buf); - - } - - if (!coex_sta->bt_disabled) { - if (coex_sta->bt_coex_supported_feature == 0) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, - &coex_sta->bt_coex_supported_feature); - - if ((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, - &coex_sta->bt_coex_supported_version); - - if (coex_sta->bt_reg_vendor_ac == 0xffff) - coex_sta->bt_reg_vendor_ac = (u16)( - btcoexist->btc_get_bt_reg(btcoexist, 3, - 0xac) & 0xffff); - - if (coex_sta->bt_reg_vendor_ae == 0xffff) - coex_sta->bt_reg_vendor_ae = (u16)( - btcoexist->btc_get_bt_reg(btcoexist, 3, - 0xae) & 0xffff); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, - &bt_patch_ver); - btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; - - if (coex_sta->num_of_profile > 0) { - cnt++; - - if (cnt >= 3) { - btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, - &coex_sta->bt_afh_map[0]); - cnt = 0; - } - } - -#if BT_8723D_2ANT_ANTDET_ENABLE - - if (board_info->btdm_ant_det_finish) { - if ((psd_scan->ant_det_result == 12) && - (psd_scan->ant_det_psd_scan_peak_val == 0) - && (!psd_scan->is_AntDet_running)) - psd_scan->ant_det_psd_scan_peak_val = - btcoexist->btc_get_ant_det_val_from_bt( - btcoexist) * 100; - } - -#endif - } - - - if (halbtc8723d2ant_is_wifibt_status_changed(btcoexist)) - halbtc8723d2ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8723d2ant_set_antenna_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (type == 2) { /* two antenna */ - board_info->ant_div_cfg = true; - - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_2G_RUNTIME); - - } else { /* one antenna */ - - halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8723D_2ANT_PHASE_2G_RUNTIME); - - } -} - -#ifdef PLATFORM_WINDOWS -#pragma optimize("", off) -#endif -void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - - static u32 ant_det_count = 0, ant_det_fail_count = 0; - struct btc_board_info *board_info = &btcoexist->board_info; - u16 u16tmp; - u8 AntDetval = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Ext Call AntennaDetect()!!\n"); - BTC_TRACE(trace_buf); - -#if BT_8723D_2ANT_ANTDET_ENABLE - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Call AntennaDetect()!!\n"); - BTC_TRACE(trace_buf); - - if (seconds == 0) { - psd_scan->ant_det_try_count = 0; - psd_scan->ant_det_fail_count = 0; - ant_det_count = 0; - ant_det_fail_count = 0; - board_info->btdm_ant_det_finish = false; - board_info->btdm_ant_num_by_ant_det = 1; - return; - } - - if (!board_info->btdm_ant_det_finish) { - psd_scan->ant_det_inteval_count = - psd_scan->ant_det_inteval_count + 2; - - if (psd_scan->ant_det_inteval_count >= - BT_8723D_2ANT_ANTDET_RETRY_INTERVAL) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n"); - BTC_TRACE(trace_buf); - - psd_scan->is_AntDet_running = true; - - halbtc8723d2ant_read_score_board(btcoexist, &u16tmp); - - if (u16tmp & BIT( - 2)) { /* Antenna detection is already done before last WL power on */ - board_info->btdm_ant_det_finish = true; - psd_scan->ant_det_try_count = 1; - psd_scan->ant_det_fail_count = 0; - board_info->btdm_ant_num_by_ant_det = (u16tmp & - BIT(3)) ? 1 : 2; - psd_scan->ant_det_result = 12; - - psd_scan->ant_det_psd_scan_peak_val = - btcoexist->btc_get_ant_det_val_from_bt( - btcoexist) * 100; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Result from BT (%d-Ant)\n", - board_info->btdm_ant_num_by_ant_det); - BTC_TRACE(trace_buf); - } else - board_info->btdm_ant_det_finish = - halbtc8723d2ant_psd_antenna_detection_check( - btcoexist); - - btcoexist->bdontenterLPS = false; - - if (board_info->btdm_ant_det_finish) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n"); - BTC_TRACE(trace_buf); - - /*for 8723d, btc_set_bt_trx_mask is just used to - notify BT stop le tx and Ant Det Result , not set BT RF TRx Mask */ - if (psd_scan->ant_det_result != 12) { - - AntDetval = (u8)( - psd_scan->ant_det_psd_scan_peak_val - / 100) & 0x7f; - - AntDetval = - (board_info->btdm_ant_num_by_ant_det - == 1) ? (AntDetval | 0x80) : - AntDetval; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxx AntennaDetect(), Ant Count = %d, PSD Val = %d\n", - ((AntDetval & - 0x80) ? 1 - : 2), AntDetval - & 0x7f); - BTC_TRACE(trace_buf); - - if (btcoexist->btc_set_bt_trx_mask( - btcoexist, AntDetval)) - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask ok!\n"); - else - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask fail!\n"); - - BTC_TRACE(trace_buf); - } else - board_info->antdetval = - psd_scan->ant_det_psd_scan_peak_val/100; - - board_info->btdm_ant_det_complete_fail = false; - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n"); - BTC_TRACE(trace_buf); - } - - psd_scan->ant_det_inteval_count = 0; - psd_scan->is_AntDet_running = false; - - /* stimulate coex running */ - halbtc8723d2ant_run_coexist_mechanism( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n", - psd_scan->ant_det_inteval_count); - BTC_TRACE(trace_buf); - - if (psd_scan->ant_det_inteval_count == 8) - btcoexist->bdontenterLPS = true; - else - btcoexist->bdontenterLPS = false; - } - - } -#endif - - -} - - -void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist) -{ - -#if BT_8723D_2ANT_ANTDET_ENABLE - struct btc_board_info *board_info = &btcoexist->board_info; - - if (psd_scan->ant_det_try_count != 0) { - halbtc8723d2ant_psd_show_antenna_detect_result(btcoexist); - - if (board_info->btdm_ant_det_finish) - halbtc8723d2ant_psd_showdata(btcoexist); - } -#endif - -} - - -#endif - -#endif /* #if (RTL8723D_SUPPORT == 1) */ - diff --git a/hal/btc/halbtc8723d2ant.h b/hal/btc/halbtc8723d2ant.h deleted file mode 100644 index ca064ec..0000000 --- a/hal/btc/halbtc8723d2ant.h +++ /dev/null @@ -1,432 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8723D_SUPPORT == 1) - -/* ******************************************* - * The following is for 8723D 2Ant BT Co-exist definition - * ******************************************* */ -#define BT_8723D_2ANT_COEX_DBG 0 -#define BT_AUTO_REPORT_ONLY_8723D_2ANT 1 - - -#define BT_INFO_8723D_2ANT_B_FTP BIT(7) -#define BT_INFO_8723D_2ANT_B_A2DP BIT(6) -#define BT_INFO_8723D_2ANT_B_HID BIT(5) -#define BT_INFO_8723D_2ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8723D_2ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8723D_2ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8723D_2ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8723D_2ANT_B_CONNECTION BIT(0) - -#define BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT 2 - - -#define BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 80 /* unit: % WiFi RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation, default = 42 */ -#define BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1 80 /* unit: % BT RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation, default = 46 */ -#define BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 80 /* unit: % WiFi RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation, default = 42 */ -#define BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES2 80 /* unit: % BT RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation, default = 46 */ -#define BT_8723D_2ANT_DEFAULT_ISOLATION 15 /* unit: dB */ -#define BT_8723D_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */ -#define BT_8723D_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */ -#define BT_8723D_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */ -#define BT_8723D_2ANT_WIFI_SIR_THRES2 -30 /* unit: dB */ -#define BT_8723D_2ANT_BT_SIR_THRES1 -15 /* unit: dB */ -#define BT_8723D_2ANT_BT_SIR_THRES2 -30 /* unit: dB */ - - -/* for Antenna detection */ -#define BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND 50 -#define BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 -#define BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 52 -#define BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT 40 -#define BT_8723D_2ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8723D_2ANT_ANTDET_SWEEPPOINT_DELAY 60000 -#define BT_8723D_2ANT_ANTDET_ENABLE 1 -#define BT_8723D_2ANT_ANTDET_BTTXTIME 100 -#define BT_8723D_2ANT_ANTDET_BTTXCHANNEL 39 -#define BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT 50 - - -#define BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 - -enum bt_8723d_2ant_signal_state { - BT_8723D_2ANT_SIG_STA_SET_TO_LOW = 0x0, - BT_8723D_2ANT_SIG_STA_SET_BY_HW = 0x0, - BT_8723D_2ANT_SIG_STA_SET_TO_HIGH = 0x1, - BT_8723D_2ANT_SIG_STA_MAX -}; - -enum bt_8723d_2ant_path_ctrl_owner { - BT_8723D_2ANT_PCO_BTSIDE = 0x0, - BT_8723D_2ANT_PCO_WLSIDE = 0x1, - BT_8723D_2ANT_PCO_MAX -}; - -enum bt_8723d_2ant_gnt_ctrl_type { - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, - BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW = 0x1, - BT_8723D_2ANT_GNT_TYPE_MAX -}; - -enum bt_8723d_2ant_gnt_ctrl_block { - BT_8723D_2ANT_GNT_BLOCK_RFC_BB = 0x0, - BT_8723D_2ANT_GNT_BLOCK_RFC = 0x1, - BT_8723D_2ANT_GNT_BLOCK_BB = 0x2, - BT_8723D_2ANT_GNT_BLOCK_MAX -}; - -enum bt_8723d_2ant_lte_coex_table_type { - BT_8723D_2ANT_CTT_WL_VS_LTE = 0x0, - BT_8723D_2ANT_CTT_BT_VS_LTE = 0x1, - BT_8723D_2ANT_CTT_MAX -}; - -enum bt_8723d_2ant_lte_break_table_type { - BT_8723D_2ANT_LBTT_WL_BREAK_LTE = 0x0, - BT_8723D_2ANT_LBTT_BT_BREAK_LTE = 0x1, - BT_8723D_2ANT_LBTT_LTE_BREAK_WL = 0x2, - BT_8723D_2ANT_LBTT_LTE_BREAK_BT = 0x3, - BT_8723D_2ANT_LBTT_MAX -}; - -enum bt_info_src_8723d_2ant { - BT_INFO_SRC_8723D_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8723D_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8723D_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8723D_2ANT_MAX -}; - -enum bt_8723d_2ant_bt_status { - BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8723D_2ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8723D_2ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8723D_2ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8723D_2ANT_BT_STATUS_MAX -}; - -enum bt_8723d_2ant_coex_algo { - BT_8723D_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8723D_2ANT_COEX_ALGO_SCO = 0x1, - BT_8723D_2ANT_COEX_ALGO_HID = 0x2, - BT_8723D_2ANT_COEX_ALGO_A2DP = 0x3, - BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8723D_2ANT_COEX_ALGO_PANEDR = 0x5, - BT_8723D_2ANT_COEX_ALGO_PANHS = 0x6, - BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8723D_2ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8723D_2ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY = 0xb, - BT_8723D_2ANT_COEX_ALGO_MAX -}; - -enum bt_8723d_2ant_phase { - BT_8723D_2ANT_PHASE_COEX_INIT = 0x0, - BT_8723D_2ANT_PHASE_WLANONLY_INIT = 0x1, - BT_8723D_2ANT_PHASE_WLAN_OFF = 0x2, - BT_8723D_2ANT_PHASE_2G_RUNTIME = 0x3, - BT_8723D_2ANT_PHASE_5G_RUNTIME = 0x4, - BT_8723D_2ANT_PHASE_BTMPMODE = 0x5, - BT_8723D_2ANT_PHASE_ANTENNA_DET = 0x6, - BT_8723D_2ANT_PHASE_COEX_POWERON = 0x7, - BT_8723D_2ANT_PHASE_MAX -}; - -enum bt_8723d_2ant_Scoreboard { - BT_8723D_2ANT_SCOREBOARD_ACTIVE = BIT(0), - BT_8723D_2ANT_SCOREBOARD_ONOFF = BIT(1), - BT_8723D_2ANT_SCOREBOARD_SCAN = BIT(2), - BT_8723D_2ANT_SCOREBOARD_UNDERTEST = BIT(3), - BT_8723D_2ANT_SCOREBOARD_WLBUSY = BIT(6) -}; - - - -struct coex_dm_8723d_2ant { - /* fw mechanism */ - u8 pre_bt_dec_pwr_lvl; - u8 cur_bt_dec_pwr_lvl; - u8 pre_fw_dac_swing_lvl; - u8 cur_fw_dac_swing_lvl; - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean reset_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - - /* sw mechanism */ - boolean pre_rf_rx_lpf_shrink; - boolean cur_rf_rx_lpf_shrink; - u32 bt_rf_0x1e_backup; - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - boolean pre_dac_swing_on; - u32 pre_dac_swing_lvl; - boolean cur_dac_swing_on; - u32 cur_dac_swing_lvl; - boolean pre_adc_back_off; - boolean cur_adc_back_off; - boolean pre_agc_table_en; - boolean cur_agc_table_en; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - boolean need_recover0x948; - u32 backup0x948; - - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - boolean is_switch_to_1dot5_ant; - u8 switch_thres_offset; - u32 arp_cnt; - - u8 pre_ant_pos_type; - u8 cur_ant_pos_type; -}; - -struct coex_sta_8723d_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - boolean is_hiPri_rx_overhead; - u8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - u8 bt_info_c2h[BT_INFO_SRC_8723D_2ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8723D_2ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_remote_name_req; - u8 bt_retry_cnt; - u8 bt_info_ext; - u8 bt_info_ext2; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; - - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; - u8 coex_table_type; - boolean force_lps_on; - - u8 dis_ver_info_cnt; - - u8 a2dp_bit_pool; - u8 cut_version; - - boolean concurrent_rx_mode_on; - - u16 score_board; - u8 isolation_btween_wb; /* 0~ 50 */ - u8 wifi_coex_thres; - u8 bt_coex_thres; - u8 wifi_coex_thres2; - u8 bt_coex_thres2; - - u8 num_of_profile; - boolean acl_busy; - boolean bt_create_connection; - boolean wifi_is_high_pri_task; - u32 specific_pkt_period_cnt; - u32 bt_coex_supported_feature; - u32 bt_coex_supported_version; - - u8 bt_ble_scan_type; - u32 bt_ble_scan_para[3]; - - boolean run_time_state; - boolean freeze_coexrun_by_btinfo; - - boolean is_A2DP_3M; - boolean voice_over_HOGP; - u8 bt_info; - boolean is_autoslot; - u8 forbidden_slot; - u8 hid_busy_num; - u8 hid_pair_cnt; - - u32 cnt_RemoteNameReq; - u32 cnt_setupLink; - u32 cnt_ReInit; - u32 cnt_IgnWlanAct; - u32 cnt_Page; - u32 cnt_RoleSwitch; - - u16 bt_reg_vendor_ac; - u16 bt_reg_vendor_ae; - - boolean is_setupLink; - boolean wl_noisy_level; - u32 gnt_error_cnt; - - u8 bt_afh_map[10]; - u8 bt_relink_downcount; - boolean is_tdma_btautoslot; - boolean is_tdma_btautoslot_hang; -}; - -#define BT_8723D_2ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ -#define BT_8723D_2ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ -#define BT_8723D_2ANT_ANTDET_BUF_LEN 16 - -struct psdscan_sta_8723d_2ant { - - u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ - u32 ant_det_bt_tx_time; - u32 ant_det_pre_psdscan_peak_val; - boolean ant_det_is_ant_det_available; - u32 ant_det_psd_scan_peak_val; - boolean ant_det_is_btreply_available; - u32 ant_det_psd_scan_peak_freq; - - u8 ant_det_result; - u8 ant_det_peak_val[BT_8723D_2ANT_ANTDET_BUF_LEN]; - u8 ant_det_peak_freq[BT_8723D_2ANT_ANTDET_BUF_LEN]; - u32 ant_det_try_count; - u32 ant_det_fail_count; - u32 ant_det_inteval_count; - u32 ant_det_thres_offset; - - u32 real_cent_freq; - s32 real_offset; - u32 real_span; - - u32 psd_band_width; /* unit: Hz */ - u32 psd_point; /* 128/256/512/1024 */ - u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_start_point; - u32 psd_stop_point; - u32 psd_max_value_point; - u32 psd_max_value; - u32 psd_max_value2; - u32 psd_avg_value; /* filter loop_max_value that below BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/ - u32 psd_loop_max_value[BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT]; /*max value in each loop */ - u32 psd_start_base; - u32 psd_avg_num; /* 1/8/16/32 */ - u32 psd_gen_count; - boolean is_AntDet_running; - boolean is_psd_show_max_only; -}; - - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d2ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8723d2ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d2ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8723d2ant_set_antenna_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8723d2ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist); - - -#else -#define ex_halbtc8723d2ant_power_on_setting(btcoexist) -#define ex_halbtc8723d2ant_pre_load_firmware(btcoexist) -#define ex_halbtc8723d2ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8723d2ant_init_coex_dm(btcoexist) -#define ex_halbtc8723d2ant_ips_notify(btcoexist, type) -#define ex_halbtc8723d2ant_lps_notify(btcoexist, type) -#define ex_halbtc8723d2ant_scan_notify(btcoexist, type) -#define ex_halbtc8723d2ant_connect_notify(btcoexist, type) -#define ex_halbtc8723d2ant_media_status_notify(btcoexist, type) -#define ex_halbtc8723d2ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8723d2ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8723d2ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8723d2ant_halt_notify(btcoexist) -#define ex_halbtc8723d2ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8723d2ant_periodical(btcoexist) -#define ex_halbtc8723d2ant_display_coex_info(btcoexist) -#define ex_halbtc8723d2ant_set_antenna_notify(btcoexist, type) -#define ex_halbtc8723d2ant_display_ant_detection(btcoexist) -#define ex_halbtc8723d2ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) -#endif - -#endif - diff --git a/hal/btc/halbtc8812a1ant.c b/hal/btc/halbtc8812a1ant.c deleted file mode 100644 index 0ac288e..0000000 --- a/hal/btc/halbtc8812a1ant.c +++ /dev/null @@ -1,3475 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for RTL8812A Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8812A_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8812a_1ant glcoex_dm_8812a_1ant; -static struct coex_dm_8812a_1ant *coex_dm = &glcoex_dm_8812a_1ant; -static struct coex_sta_8812a_1ant glcoex_sta_8812a_1ant; -static struct coex_sta_8812a_1ant *coex_sta = &glcoex_sta_8812a_1ant; - -const char *const glbt_info_src_8812a_1ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8812a_1ant = 20140708; -u32 glcoex_ver_8812a_1ant = 0x52; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8812a1ant_ - * ************************************************************ */ -u8 halbtc8812a1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8812a1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8812a1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -/* to check 0x430/0x434 is correct?? */ -void halbtc8812a1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -/* to check 0x42a ?? */ -void halbtc8812a1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -/* to check 0x456?? */ -void halbtc8812a1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8812a1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8812a1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8812a1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8812a1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8812a1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8812a1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8812a1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8812a1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8812a1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 data_len = 3; - u8 buf[5] = {0}; - - if (!coex_sta->bt_disabled) { - if (!coex_sta->bt_info_query_cnt || - (coex_sta->bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_BT_RSP] - - coex_sta->bt_info_query_cnt) > 2) { - buf[0] = data_len; - buf[1] = 0x1; /* polling enable, 1=enable, 0=disable */ - buf[2] = 0x2; /* polling time in seconds */ - buf[3] = 0x1; /* auto report enable, 1=enable, 0=disable */ - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_INFO, - (void *)&buf[0]); - } - } - coex_sta->bt_info_query_cnt++; -} - -void halbtc8812a1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if ((coex_sta->low_priority_tx > 1150) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", - reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) && - (reg_lp_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8812a1ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; - } - } -} - -/* to check registers */ -void halbtc8812a1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false; - static u8 cck_lock_counter = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - if (coex_sta->under_ips) { - coex_sta->crc_ok_cck = 0; - coex_sta->crc_ok_11g = 0; - coex_sta->crc_ok_11n = 0; - coex_sta->crc_ok_11n_agg = 0; - - coex_sta->crc_err_cck = 0; - coex_sta->crc_err_11g = 0; - coex_sta->crc_err_11n = 0; - coex_sta->crc_err_11n_agg = 0; - } else { - coex_sta->crc_ok_cck = btcoexist->btc_read_2byte(btcoexist, - 0xf04); - coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf14); - coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf10); - coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xf40); - - coex_sta->crc_err_cck = btcoexist->btc_read_2byte(btcoexist, - 0xf06); - coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist, - 0xf16); - coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist, - 0xf12); - coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist, - 0xf42); - } - - - /* reset counter */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x0); - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - if ((coex_dm->bt_status == BT_8812A_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == - BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == - BT_8812A_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + - coex_sta->crc_ok_11n_agg)) { - if (cck_lock_counter < 5) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 5) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - coex_sta->pre_ccklock = coex_sta->cck_lock; - - -} - -boolean halbtc8812a1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - } - - return false; -} - -void halbtc8812a1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8812a1ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8812A_1ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8812a1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8812a1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8812a1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -/* to check */ -void halbtc8812a1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 tmp_u1; - - tmp_u1 = btcoexist->btc_read_1byte(btcoexist, 0x4fd); - tmp_u1 |= BIT(0); - if (low_penalty_ra) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Tx rate adaptive, set low penalty!!\n"); - BTC_TRACE(trace_buf); - tmp_u1 &= ~BIT(2); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Tx rate adaptive, set normal!!\n"); - BTC_TRACE(trace_buf); - tmp_u1 |= BIT(2); - } - - btcoexist->btc_write_1byte(btcoexist, 0x4fd, tmp_u1); -} - -void halbtc8812a1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8812a1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8812a1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8812a1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8812a1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8812a1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** CoexTable(%d) **********\n", type); - BTC_TRACE(trace_buf); - - coex_sta->coex_table_type = type; - - switch (type) { - case 0: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, 0xffffff, 0x3); - break; - case 1: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 2: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 3: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 4: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); - break; - case 5: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaa5a5a5a, 0xffffff, 0x3); - break; - case 6: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 7: - halbtc8812a1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8812a1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 data_len = 3; - u8 buf[5] = {0}; - - buf[0] = data_len; - buf[1] = 0x1; /* OP_Code */ - buf[2] = 0x1; /* OP_Code_Length */ - if (enable) - buf[3] = 0x1; /* OP_Code_Content */ - else - buf[3] = 0x0; - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); -} - -void halbtc8812a1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8812a1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8812a1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8812a1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8812a1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8812a1ant_sw_mechanism(IN struct btc_coexist *btcoexist, - IN boolean low_penalty_ra) -{ - halbtc8812a1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -/* to check force_exec */ -void halbtc8812a1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg, - IN boolean wifi_off) -{ - u8 u8tmp = 0; - - coex_dm->cur_ant_pos_type = ant_pos_type; - - if (init_hwcfg) { - btcoexist->btc_write_1byte(btcoexist, 0xcb3, 0x77); - btcoexist->btc_write_4byte(btcoexist, 0x900, 0x00000400); - btcoexist->btc_write_1byte(btcoexist, 0x76d, 0x1); - } else if (wifi_off) { - btcoexist->btc_write_1byte(btcoexist, 0xcb3, 0x77); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7); - u8tmp &= ~BIT(3); - u8tmp |= BIT(2); - btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp); - } - - if (force_exec || - (coex_dm->cur_ant_pos_type != coex_dm->pre_ant_pos_type)) { - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - u8tmp = btcoexist->btc_read_1byte(btcoexist, - 0xcb7); - u8tmp |= BIT(3); - u8tmp &= ~BIT(2); - btcoexist->btc_write_1byte(btcoexist, 0xcb7, - u8tmp); - break; - case BTC_ANT_PATH_BT: - u8tmp = btcoexist->btc_read_1byte(btcoexist, - 0xcb7); - u8tmp &= ~BIT(3); - u8tmp |= BIT(2); - btcoexist->btc_write_1byte(btcoexist, 0xcb7, - u8tmp); - break; - default: - case BTC_ANT_PATH_PTA: - u8tmp = btcoexist->btc_read_1byte(btcoexist, - 0xcb7); - u8tmp |= BIT(3); - u8tmp &= ~BIT(2); - btcoexist->btc_write_1byte(btcoexist, 0xcb7, - u8tmp); - break; - } - } - - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; -} - -void halbtc8812a1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - } - } - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - - -void halbtc8812a1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - u8 rssi_adjust_val = 0; - u8 ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51, - ps_tdma_byte3_val = 0x10; - s8 wifi_duration_adjust = 0x0; - static boolean pre_wifi_busy = false; - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (wifi_busy != pre_wifi_busy) { - force_exec = true; - pre_wifi_busy = wifi_busy; - } - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_sta->scan_ap_num <= 5) - wifi_duration_adjust = 2; - else if (coex_sta->scan_ap_num >= 40) - wifi_duration_adjust = -15; - else if (coex_sta->scan_ap_num >= 20) - wifi_duration_adjust = -10; - - if (!coex_sta->force_lps_on) { /* only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */ - ps_tdma_byte0_val = 0x61; /* no null-pkt */ - ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */ - ps_tdma_byte4_val = 0x10; /* 0x778 = d/1 toggle */ - } - - if ((type == 3) || (type == 13) || (type == 14)) { - ps_tdma_byte4_val = ps_tdma_byte4_val & - 0xbf; /* no dynamic slot for multi-profile */ - - if (!wifi_busy) - ps_tdma_byte4_val = ps_tdma_byte4_val | - 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - } - - if (bt_link_info->slave_role == true) - ps_tdma_byte4_val = ps_tdma_byte4_val | - 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - - if (turn_on) { - switch (type) { - default: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1a, 0x1a, 0x0, ps_tdma_byte4_val); - break; - case 1: - halbtc8812a1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x3a + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 2: - halbtc8812a1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x2d + - wifi_duration_adjust, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 3: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1d, 0x1d, 0x0, ps_tdma_byte4_val); - break; - case 4: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x14, 0x0); - break; - case 5: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x15, 0x3, 0x11, 0x11); - break; - case 6: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x3, 0x11, 0x11); - break; - case 7: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13, - 0xc, 0x5, 0x0, 0x0); - break; - case 8: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 9: - halbtc8812a1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x3, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 10: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0xa, 0x0, 0x40); - break; - case 11: - halbtc8812a1ant_set_fw_pstdma(btcoexist, - ps_tdma_byte0_val, 0x21, 0x03, - ps_tdma_byte3_val, ps_tdma_byte4_val); - break; - case 12: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x0a, 0x0a, 0x0, 0x50); - break; - case 13: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x12, 0x12, 0x0, ps_tdma_byte4_val); - break; - case 14: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x21, 0x3, 0x10, ps_tdma_byte4_val); - break; - case 15: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0x3, 0x8, 0x0); - break; - case 16: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x10, 0x0); - break; - case 18: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 20: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x3f, 0x03, 0x11, 0x10); - break; - case 21: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x11); - break; - case 22: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x10); - break; - case 23: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x18); - break; - case 24: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x3, 0x31, 0x18); - break; - case 25: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - break; - case 26: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - break; - case 27: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x98); - break; - case 28: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x69, - 0x25, 0x3, 0x31, 0x0); - break; - case 29: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xab, - 0x1a, 0x1a, 0x1, 0x10); - break; - case 30: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, 0x10); - break; - case 31: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1a, 0x1a, 0, 0x58); - break; - case 32: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x3, 0x11, 0x11); - break; - case 33: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xa3, - 0x25, 0x3, 0x30, 0x90); - break; - case 34: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x53, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 35: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x63, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 36: - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x12, 0x3, 0x14, 0x50); - break; - case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */ - /* here softap mode screen off will cost 70-80mA for phone */ - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x23, - 0x18, 0x00, 0x10, 0x24); - break; - } - } else { - - /* disable PS tdma */ - switch (type) { - case 8: /* PTA Control */ - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - break; - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - break; - } - } - rssi_adjust_val = 0; - btcoexist->btc_set(btcoexist, - BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val); - - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -boolean halbtc8812a1ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (wifi_connected && - (BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (!wifi_connected && - (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (wifi_connected && - (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else if (!wifi_connected && - (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - - /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */ - - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } - - common = false; - } - - return common; -} - - -void halbtc8812a1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0, bt_info_ext; - boolean wifi_busy = false; - - if (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status) - wifi_busy = true; - else - wifi_busy = false; - - if ((BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == - wifi_status) || - (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) || - (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT == - wifi_status)) { - if (coex_dm->cur_ps_tdma != 1 && - coex_dm->cur_ps_tdma != 2 && - coex_dm->cur_ps_tdma != 3 && - coex_dm->cur_ps_tdma != 9) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 9); - coex_dm->ps_tdma_du_adj_type = 9; - - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } - return; - } - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* acquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - bt_info_ext = coex_sta->bt_info_ext; - - if ((coex_sta->low_priority_tx) > 1150 || - (coex_sta->low_priority_rx) > 1250) - retry_count++; - - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */ - if (wait_count <= 2) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */ - if (wait_count == 1) - m++; /* to avoid loop between the two levels */ - else - m = 1; - - if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (result == -1) { - if ((BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 1) || - (coex_dm->cur_ps_tdma == 2))) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } - } else if (result == 1) { - if ((BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 1) || - (coex_dm->cur_ps_tdma == 2))) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = 1; - } - } else { /* no change */ - /* Bryant Modify - if(wifi_busy != pre_wifi_busy) - { - pre_wifi_busy = wifi_busy; - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma); - } - */ - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - if (coex_dm->cur_ps_tdma != 1 && - coex_dm->cur_ps_tdma != 2 && - coex_dm->cur_ps_tdma != 9 && - coex_dm->cur_ps_tdma != 11) { - /* recover to previous adjust type */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - } - } -} - -void halbtc8812a1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8812a1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8812a1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8812a1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8812a1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - -void halbtc8812a1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, - false, false); -} - -void halbtc8812a1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - BTC_TRACE(trace_buf); - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 2) { - bt_disabled = true; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - BTC_TRACE(trace_buf); - halbtc8812a1ant_action_wifi_only(btcoexist); - } - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - if (!bt_disabled) { - } else { - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - } - } -} - -/* ********************************************* - * - * Software Coex Mechanism start - * - * ********************************************* */ - -/* SCO only or SCO+PAN(HS) */ - -/* -void halbtc8812a1ant_action_sco(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8812a1ant_action_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8812a1ant_action_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8812a1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8812a1ant_action_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8812a1ant_action_pan_hs(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, false); -} - - -void halbtc8812a1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8812a1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, true); -} - - -void halbtc8812a1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, true); -} - -void halbtc8812a1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist) -{ - halbtc8812a1ant_sw_mechanism(btcoexist, true); -} - -*/ - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8812a1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8812a1ant_action_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8812a1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, ap_enable = false, wifi_busy = false, - bt_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) { - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - /* SCO/HID/A2DP busy */ - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if ((bt_link_info->pan_exist) || (wifi_busy)) { - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } -} - -void halbtc8812a1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* tdma and coex table */ - - if (bt_link_info->sco_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else { /* HID */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } -} - -void halbtc8812a1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - u8 bt_rssi_state; - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - bt_rssi_state = halbtc8812a1ant_bt_rssi_state(2, 28, 0); - - if ((coex_sta->low_priority_rx >= 950) && (!coex_sta->under_ips)) - bt_link_info->slave_role = true; - else - bt_link_info->slave_role = false; - - if (bt_link_info->hid_only) { /* HID */ - halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, - wifi_status); - coex_dm->auto_tdma_adjust = false; - return; - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - halbtc8812a1ant_tdma_duration_adjust_for_acl(btcoexist, - wifi_status); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = true; - } - } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - coex_dm->auto_tdma_adjust = false; - - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && - bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } else { - /* BT no-profile busy (0x9) */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - coex_dm->auto_tdma_adjust = false; - } -} - -void halbtc8812a1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - /* power save state */ - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, - false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8812a1ant_action_wifi_not_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* Bryant Add */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8812a1ant_action_wifi_not_connected_asso_auth( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - } else { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2); - } -} - -void halbtc8812a1ant_action_wifi_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* Bryant Add */ - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8812a1ant_action_wifi_connected_specific_packet( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->pan_exist) { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - NORMAL_EXEC, false, false); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8812a1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - boolean scan = false, link = false, roam = false; - boolean under_4way = false, ap_enable = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (under_4way) { - halbtc8812a1ant_action_wifi_connected_specific_packet(btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - if (scan) - halbtc8812a1ant_action_wifi_connected_scan(btcoexist); - else - halbtc8812a1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* power save state */ - if (!ap_enable && - BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status && - !btcoexist->bt_link_info.hid_only) { - if (btcoexist->bt_link_info.a2dp_only) { /* A2DP */ - if (!wifi_busy) - halbtc8812a1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - else { /* busy */ - if (coex_sta->scan_ap_num >= - BT_8812A_1ANT_WIFI_NOISY_THRESH) /* no force LPS, no PS-TDMA, use pure TDMA */ - halbtc8812a1ant_power_save_state( - btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8812a1ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - } else if ((coex_sta->pan_exist == false) && - (coex_sta->a2dp_exist == false) && - (coex_sta->hid_exist == false)) - halbtc8812a1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - else - halbtc8812a1ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - } else - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - /* tdma and coex table */ - if (!wifi_busy) { - if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8812a1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8812a1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - else - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } else { - if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8812a1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else { - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8812a1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - else - halbtc8812a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } -} - -void halbtc8812a1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - - algorithm = halbtc8812a1ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - - if (halbtc8812a1ant_is_common_action(btcoexist)) { - - } else { - switch (coex_dm->cur_algorithm) { - case BT_8812A_1ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_sco(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_hid(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_a2dp(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_a2dp_pan_hs(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_pan_edr(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_pan_hs(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_pan_edr_a2dp(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_pan_edr_hid(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_hid_a2dp_pan_edr(btcoexist); */ - break; - case BT_8812A_1ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_action_hid_a2dp(btcoexist); */ - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8812a1ant_coex_all_off(btcoexist); */ - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8812a1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - boolean miracast_plus_bt = false; - u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0, wifi_bw; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if ((BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, - 0, 1); - miracast_plus_bt = true; - } else { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, - 0, 0); - miracast_plus_bt = false; - } - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - if ((bt_link_info->a2dp_exist) && - (coex_sta->c2h_bt_inquiry_page)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8812a1ant_action_bt_inquiry(btcoexist); - } else - halbtc8812a1ant_action_wifi_multi_port(btcoexist); - - return; - } - - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); - - if (bt_link_info->sco_exist) - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, true, - false, 0x5); - else { - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, - false, true, 0x10); - else - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, - false, true, 0x8); - } - - halbtc8812a1ant_sw_mechanism(btcoexist, true); - halbtc8812a1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - } else { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x5); - - halbtc8812a1ant_sw_mechanism(btcoexist, false); - halbtc8812a1ant_run_sw_coexist_mechanism( - btcoexist); /* //just print debug message */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8812a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8812a1ant_action_hs(btcoexist); - return; - } - - - if (!wifi_connected) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is non connected-idle !!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - if (scan) - halbtc8812a1ant_action_wifi_not_connected_scan( - btcoexist); - else - halbtc8812a1ant_action_wifi_not_connected_asso_auth( - btcoexist); - } else - halbtc8812a1ant_action_wifi_not_connected(btcoexist); - } else /* wifi LPS/Busy */ - halbtc8812a1ant_action_wifi_connected(btcoexist); -} - -void halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - - /* sw all off */ - halbtc8812a1ant_sw_mechanism(btcoexist, false); - - /* halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ - /* halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */ - - coex_sta->pop_event_cnt = 0; -} - -void halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up, IN boolean wifi_only) -{ - u8 u8tmp = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - /* ant sw control to BT */ - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, - true, false); - - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* PTA parameter */ - btcoexist->btc_write_1byte(btcoexist, 0x6cc, 0x0); - btcoexist->btc_write_4byte(btcoexist, 0x6c8, 0xffff); - btcoexist->btc_write_4byte(btcoexist, 0x6c4, 0x55555555); - btcoexist->btc_write_4byte(btcoexist, 0x6c0, 0x55555555); - - /* coex parameters */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - - /* enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* enable PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); - - /* bt clock related */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x4); - u8tmp |= BIT(7); - btcoexist->btc_write_1byte(btcoexist, 0x4, u8tmp); - - /* bt clock related */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); - u8tmp |= BIT(1); - btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); -} - -/* ************************************************************ - * work around function start with wa_halbtc8812a1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8812a1ant_ - * ************************************************************ */ -void ex_halbtc8812a1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8812a1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8812a1ant_init_hw_config(btcoexist, true, wifi_only); - btcoexist->stop_coex_dm = false; -} - -void ex_halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - - halbtc8812a1ant_init_coex_dm(btcoexist); - - halbtc8812a1ant_query_bt_info(btcoexist); -} - -void ex_halbtc8812a1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u32 u32tmp[4]; - u32 fw_ver = 0, bt_patch_ver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", - "CoexVer/ FwVer/ PatchVer", - glcoex_ver_date_8812a_1ant, glcoex_ver_8812a_1ant, fw_ver, - bt_patch_ver, bt_patch_ver); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", - "SCO/HID/PAN/A2DP", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8812A_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8812a_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - if (!btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", - "Latest error condition(should be 0)", - coex_dm->error_condition); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", - "IgnWlanAct", - coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - } - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", - u8tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcb3); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb7); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x900); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0xcb3/0xcb7/0x900", - u8tmp[0], u8tmp[1], u32tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", - u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", - u32tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(hp rx[31:16]/tx[15:0])", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(lp rx[31:16]/tx[15:0])", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); - - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - - -void ex_halbtc8812a1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - - halbtc8812a1ant_init_hw_config(btcoexist, false, false); - halbtc8812a1ant_init_coex_dm(btcoexist); - halbtc8812a1ant_query_bt_info(btcoexist); - - coex_sta->under_ips = false; - } -} - -void ex_halbtc8812a1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8812a1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (BTC_SCAN_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - } - - if (coex_sta->bt_disabled) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - halbtc8812a1ant_query_bt_info(btcoexist); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8812a1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8812a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8812a1ant_action_hs(btcoexist); - return; - } - - if (BTC_SCAN_START == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8812a1ant_action_wifi_not_connected_scan( - btcoexist); - else /* wifi is connected */ - halbtc8812a1ant_action_wifi_connected_scan(btcoexist); - } else if (BTC_SCAN_FINISH == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8812a1ant_action_wifi_not_connected(btcoexist); - else - halbtc8812a1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8812a1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_ASSOCIATE_START == type) { - coex_sta->wifi_is_high_pri_task = true; - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - /* coex_dm->arp_cnt = 0; */ - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8812a1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8812a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8812a1ant_action_hs(btcoexist); - return; - } - - if (BTC_ASSOCIATE_START == type) - halbtc8812a1ant_action_wifi_not_connected_asso_auth(btcoexist); - else if (BTC_ASSOCIATE_FINISH == type) { - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (!wifi_connected) /* non-connected scan */ - halbtc8812a1ant_action_wifi_not_connected(btcoexist); - else - halbtc8812a1ant_action_wifi_connected(btcoexist); - } -} - -/* to check registers... */ -void ex_halbtc8812a1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 data_len = 5; - u8 buf[6] = {0}; - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - boolean wifi_under_b_mode = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, - FORCE_EXEC, false, false); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); -#if 0 - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x10); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } -#endif - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - /* h2c_parameter[0] = 0x1; */ - h2c_parameter[0] = 0x0; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - buf[0] = data_len; - buf[1] = 0x5; /* OP_Code */ - buf[2] = 0x3; /* OP_Code_Length */ - buf[3] = h2c_parameter[0]; /* OP_Code_Content */ - buf[4] = h2c_parameter[1]; - buf[5] = h2c_parameter[2]; - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); -} - -void ex_halbtc8812a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - BTC_PACKET_ARP == type) { - if (BTC_PACKET_ARP == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify\n"); - BTC_TRACE(trace_buf); - - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ARP Packet Count = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - - if (coex_dm->arp_cnt >= - 10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */ - coex_sta->wifi_is_high_pri_task = false; - else - coex_sta->wifi_is_high_pri_task = true; - } else { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify\n"); - BTC_TRACE(trace_buf); - } - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet [Type = %d] notify\n", type); - BTC_TRACE(trace_buf); - } - - coex_sta->specific_pkt_period_cnt = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8812a1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8812a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8812a1ant_action_hs(btcoexist); - return; - } - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task))) - halbtc8812a1ant_action_wifi_connected_specific_packet(btcoexist); -} - -void ex_halbtc8812a1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean bt_busy = false; - - coex_sta->c2h_bt_info_req_sent = false; - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8812A_1ANT_MAX) - rsp_source = BT_INFO_SRC_8812A_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (BT_INFO_SRC_8812A_1ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_page = true; - else - coex_sta->c2h_bt_page = false; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; - /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */ - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] - & 0x40); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, - &coex_sta->bt_tx_rx_mask); - if (!coex_sta->bt_tx_rx_mask) { - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x3c, 0x15); - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if (coex_sta->bt_info_ext & BIT(1)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8812a1ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8812a1ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if (coex_sta->bt_info_ext & BIT(3)) { - if (!btcoexist->manual_control && - !btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - } -#if (BT_AUTO_REPORT_ONLY_8812A_1ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8812a1ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8812A_1ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8812A_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8812A_1ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8812A_1ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8812A_1ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8812A_1ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - } - - halbtc8812a1ant_update_bt_link_info(btcoexist); - - bt_info = bt_info & - 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ - - if (!(bt_info & BT_INFO_8812A_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8812A_1ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8812A_1ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8812A_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8812A_1ANT_B_ACL_BUSY) { - if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) - coex_dm->auto_tdma_adjust = false; - coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - halbtc8812a1ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8812a1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - } else if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - - halbtc8812a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - btcoexist->stop_coex_dm = true; - } -} - -void ex_halbtc8812a1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, - false, true); - - halbtc8812a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8812a1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8812a1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, - FORCE_EXEC, false, true); - halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - halbtc8812a1ant_init_hw_config(btcoexist, false, false); - halbtc8812a1ant_init_coex_dm(btcoexist); - halbtc8812a1ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8812a1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], *****************Coex DM Reset*****************\n"); - BTC_TRACE(trace_buf); - - halbtc8812a1ant_init_hw_config(btcoexist, false, false); - halbtc8812a1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8812a1ant_periodical(IN struct btc_coexist *btcoexist) -{ -#if (BT_AUTO_REPORT_ONLY_8812A_1ANT == 0) - halbtc8812a1ant_query_bt_info(btcoexist); - halbtc8812a1ant_monitor_bt_enable_disable(btcoexist); -#else - halbtc8812a1ant_monitor_bt_ctr(btcoexist); - halbtc8812a1ant_monitor_wifi_ctr(btcoexist); - - if (halbtc8812a1ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust) - halbtc8812a1ant_run_coexist_mechanism(btcoexist); - - coex_sta->specific_pkt_period_cnt++; -#endif -} - -void ex_halbtc8812a1ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata) -{ - switch (op_code) { - case BTC_DBG_SET_COEX_NORMAL: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set CoexMode to Normal\n"); - BTC_TRACE(trace_buf); - btcoexist->manual_control = false; - halbtc8812a1ant_init_coex_dm(btcoexist); - break; - case BTC_DBG_SET_COEX_WIFI_ONLY: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set CoexMode to Wifi Only\n"); - BTC_TRACE(trace_buf); - btcoexist->manual_control = true; - halbtc8812a1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 9); - break; - case BTC_DBG_SET_COEX_BT_ONLY: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set CoexMode to BT only\n"); - BTC_TRACE(trace_buf); - btcoexist->manual_control = true; - halbtc8812a1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - break; - case BTC_DBG_SET_COEX_DEC_BT_PWR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set Dec BT power\n"); - BTC_TRACE(trace_buf); - { - u8 data_len = 4; - u8 buf[6] = {0}; - u8 dec_bt_pwr = 0, pwr_level = 0; - - if (op_len == 2) { - dec_bt_pwr = pdata[0]; - pwr_level = pdata[1]; - - buf[0] = data_len; - buf[1] = 0x3; /* OP_Code */ - buf[2] = 0x2; /* OP_Code_Length */ - - buf[3] = dec_bt_pwr; /* OP_Code_Content */ - buf[4] = pwr_level; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set Dec BT power=%d, pwr_level=%d\n", - dec_bt_pwr, pwr_level); - BTC_TRACE(trace_buf); - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); - } - } - break; - - case BTC_DBG_SET_COEX_BT_AFH_MAP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT AFH Map\n"); - BTC_TRACE(trace_buf); - { - u8 data_len = 5; - u8 buf[6] = {0}; - - if (op_len == 3) { - buf[0] = data_len; - buf[1] = 0x5; /* OP_Code */ - buf[2] = 0x3; /* OP_Code_Length */ - - buf[3] = pdata[0]; /* OP_Code_Content */ - buf[4] = pdata[1]; - buf[5] = pdata[2]; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT AFH Map = %02x %02x %02x\n", - pdata[0], pdata[1], pdata[2]); - BTC_TRACE(trace_buf); - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); - } - } - break; - - case BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT Ignore Wlan Active\n"); - BTC_TRACE(trace_buf); - { - u8 data_len = 3; - u8 buf[6] = {0}; - - if (op_len == 1) { - buf[0] = data_len; - buf[1] = 0x1; /* OP_Code */ - buf[2] = 0x1; /* OP_Code_Length */ - - buf[3] = pdata[0]; /* OP_Code_Content */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT Ignore Wlan Active = 0x%x\n", - pdata[0]); - BTC_TRACE(trace_buf); - - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); - } - } - break; - default: - break; - } -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ diff --git a/hal/btc/halbtc8812a1ant.h b/hal/btc/halbtc8812a1ant.h deleted file mode 100644 index 08fbad2..0000000 --- a/hal/btc/halbtc8812a1ant.h +++ /dev/null @@ -1,244 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8812A_SUPPORT == 1) - -/* ******************************************* - * The following is for 8812A 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8812A_1ANT 1 - -#define BT_INFO_8812A_1ANT_B_FTP BIT(7) -#define BT_INFO_8812A_1ANT_B_A2DP BIT(6) -#define BT_INFO_8812A_1ANT_B_HID BIT(5) -#define BT_INFO_8812A_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8812A_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8812A_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8812A_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8812A_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT 2 - -#define BT_8812A_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ - -enum bt_info_src_8812a_1ant { - BT_INFO_SRC_8812A_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8812A_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8812A_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8812A_1ANT_MAX -}; - -enum bt_8812a_1ant_bt_status { - BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8812A_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8812A_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8812A_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8812A_1ANT_BT_STATUS_MAX -}; - -enum bt_8812a_1ant_wifi_status { - BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8812A_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8812a_1ant_coex_algo { - BT_8812A_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8812A_1ANT_COEX_ALGO_SCO = 0x1, - BT_8812A_1ANT_COEX_ALGO_HID = 0x2, - BT_8812A_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8812A_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8812A_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8812A_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8812A_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8812A_1ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8812a_1ant { - /* hw setting */ - u8 pre_ant_pos_type; - u8 cur_ant_pos_type; - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u8 error_condition; -}; - -struct coex_sta_8812a_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - s8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8812A_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_MAX]; - u32 bt_info_query_cnt; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - u8 bt_retry_cnt; - u8 bt_info_ext; - u32 pop_event_cnt; - u8 scan_ap_num; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_agg; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_agg; - - boolean cck_lock; - boolean pre_ccklock; - u8 coex_table_type; - - boolean force_lps_on; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8812a1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8812a1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8812a1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a1ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata); -void ex_halbtc8812a1ant_display_coex_info(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8812a1ant_power_on_setting(btcoexist) -#define ex_halbtc8812a1ant_pre_load_firmware(btcoexist) -#define ex_halbtc8812a1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8812a1ant_init_coex_dm(btcoexist) -#define ex_halbtc8812a1ant_ips_notify(btcoexist, type) -#define ex_halbtc8812a1ant_lps_notify(btcoexist, type) -#define ex_halbtc8812a1ant_scan_notify(btcoexist, type) -#define ex_halbtc8812a1ant_connect_notify(btcoexist, type) -#define ex_halbtc8812a1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8812a1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8812a1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8812a1ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8812a1ant_halt_notify(btcoexist) -#define ex_halbtc8812a1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8812a1ant_coex_dm_reset(btcoexist) -#define ex_halbtc8812a1ant_periodical(btcoexist) -#define ex_halbtc8812a1ant_dbg_control(btcoexist, op_code, op_len, pdata) -#define ex_halbtc8812a1ant_display_coex_info(btcoexist) - -#endif - -#endif diff --git a/hal/btc/halbtc8812a2ant.c b/hal/btc/halbtc8812a2ant.c deleted file mode 100644 index e1e6572..0000000 --- a/hal/btc/halbtc8812a2ant.c +++ /dev/null @@ -1,5638 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for RTL8812A Co-exist mechanism - * - * History - * 2012/08/22 Cosa first check in. - * 2012/11/14 Cosa Revise for 8812A 2Ant out sourcing. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - - -#if (RTL8812A_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8812a_2ant glcoex_dm_8812a_2ant; -static struct coex_dm_8812a_2ant *coex_dm = &glcoex_dm_8812a_2ant; -static struct coex_sta_8812a_2ant glcoex_sta_8812a_2ant; -static struct coex_sta_8812a_2ant *coex_sta = &glcoex_sta_8812a_2ant; - -const char *const glbt_info_src_8812a_2ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; -/* ************************************************************ - * BtCoex Version Format: - * 1. date : glcoex_ver_date_XXXXX_1ant - * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant - * 3. BtCoexVersion : glcoex_ver_btdesired_XXXXX_1ant - * 4. others : glcoex_ver_XXXXXX_XXXXX_1ant - * - * Variable should be indicated IC and Antenna numbers !!! - * Please strictly follow this order and naming style !!! - * - * ************************************************************ */ -u32 glcoex_ver_date_8812a_2ant = 20160818; -u32 glcoex_ver_8812a_2ant = 0x3c; -u32 glcoex_ver_btdesired_8812a_2ant = 0x3c; -/*1. add coex. log for wifi/BT coex. version*/ - -/* ************************************************************ -* local function proto type if needed -* ************************************************************ -* ************************************************************ -* local function start with halbtc8812a2ant_ -* ************************************************************ */ -u8 halbtc8812a2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - - -u8 halbtc8812a2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - - -void halbtc8812a2ant_set_enable_pta(IN struct btc_coexist *btcoexist, - IN boolean enablePTA) -{ - if (enablePTA) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PTA is enable!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PTA is disable!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte(btcoexist, 0x40, 0x00); - - } -} - -void halbtc8812a2ant_enable_pta(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s turn Enable PTA %s\n", - (force_exec ? "force to" : ""), (enable ? "ON" : "OFF")); - BTC_TRACE(trace_buf); - coex_dm->cur_enable_pta = enable; - - if (!force_exec) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_enable_pta = %d, cur_enable_pta = %d!!\n", - coex_dm->pre_enable_pta, coex_dm->cur_enable_pta); - BTC_TRACE(trace_buf); - - if (coex_dm->pre_enable_pta == coex_dm->cur_enable_pta) - return; - } - halbtc8812a2ant_set_enable_pta(btcoexist, enable); - - - coex_dm->pre_enable_pta = coex_dm->cur_enable_pta; -} - -u32 halbtc8812a2ant_decide_ra_mask(IN struct btc_coexist *btcoexist, - IN u32 ra_mask_type) -{ - u32 dis_ra_mask = 0x0; - - switch (ra_mask_type) { - case 0: /* normal mode */ - dis_ra_mask = 0x0; - break; - case 1: /* disable cck 1/2 */ - dis_ra_mask = 0x00000003; - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - dis_ra_mask = 0x0001f1f7; - break; - default: - break; - } - - return dis_ra_mask; -} - -void halbtc8812a2ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8812a2ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8812a2ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8812a2ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8812a2ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - u32 dis_ra_mask = 0x0; - - coex_dm->cur_ra_mask_type = ra_mask_type; - dis_ra_mask = halbtc8812a2ant_decide_ra_mask(btcoexist, ra_mask_type); - halbtc8812a2ant_update_ra_mask(btcoexist, force_exec, dis_ra_mask); - - halbtc8812a2ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8812a2ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8812a2ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8812a2ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8812a2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); -} - - -void halbtc8812a2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ -#if 1 - - coex_sta->crc_ok_cck = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_VHT); -#endif -} - - -void halbtc8812a2ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 data_len = 3; - u8 buf[5] = {0}; - /* 8812a watch btifo to check BT enable/disable - * if(!btcoexist->bt_info.bt_disabled) */ - { - if (!coex_sta->bt_info_query_cnt || - (coex_sta->bt_info_c2h_cnt[BT_INFO_SRC_8812A_2ANT_BT_RSP] - - coex_sta->bt_info_query_cnt) > 2) { - buf[0] = data_len; - buf[1] = 0x1; /* polling enable, 1=enable, 0=disable */ - buf[2] = 0x2; /* polling time in seconds */ - buf[3] = 0x1; /* auto report enable, 1=enable, 0=disable */ - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_INFO, - (void *)&buf[0]); - } - } - coex_sta->bt_info_query_cnt++; -} - -boolean halbtc8812a2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - } - - return false; -} - -void halbtc8812a2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - -#if 1/* (BT_AUTO_REPORT_ONLY_8812A_2ANT == 1) / profile from bt patch */ - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->acl_busy = coex_sta->acl_busy; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } -#else /* profile from bt stack */ - bt_link_info->bt_link_exist = stack_info->bt_link_exist; - bt_link_info->sco_exist = stack_info->sco_exist; - bt_link_info->a2dp_exist = stack_info->a2dp_exist; - bt_link_info->pan_exist = stack_info->pan_exist; - bt_link_info->hid_exist = stack_info->hid_exist; - - /* for win-8 stack HID report error */ - if (!stack_info->hid_exist) - stack_info->hid_exist = - coex_sta->hid_exist; /* sync BTInfo with BT firmware and stack */ - /* when stack HID report error, here we use the info from bt fw. */ - if (!stack_info->bt_link_exist) - stack_info->bt_link_exist = coex_sta->bt_link_exist; -#endif - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8812a2ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8812A_2ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 0) { - if (bt_link_info->acl_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ACL Busy only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR; - } - } else if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_SCO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - if (stack_info->num_of_hid >= 2) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID*2 + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_HID_A2DP; - } - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_SCO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_SCO_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8812a2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set Dac Swing Level=0x%x\n", - dac_swing_lvl); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW write 0x64=0x%x\n", - h2c_parameter[0]); - BTC_TRACE(trace_buf); - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - -void halbtc8812a2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN u8 dec_bt_pwr_lvl) -{ - u8 data_len = 4; - u8 buf[6] = {0}; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], decrease Bt Power level = %d\n", - dec_bt_pwr_lvl); - BTC_TRACE(trace_buf); - - buf[0] = data_len; - buf[1] = 0x3; /* OP_Code */ - buf[2] = 0x2; /* OP_Code_Length */ - if (dec_bt_pwr_lvl) - buf[3] = 0x1; /* OP_Code_Content */ - else - buf[3] = 0x0; - buf[4] = dec_bt_pwr_lvl;/* pwr_level */ - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); -} - -void halbtc8812a2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 dec_bt_pwr_lvl) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s Dec BT power level = %d\n", - (force_exec ? "force to" : ""), dec_bt_pwr_lvl); - BTC_TRACE(trace_buf); - - coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; - - if (!force_exec) { - if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) - return; - } - halbtc8812a2ant_set_fw_dec_bt_pwr(btcoexist, - coex_dm->cur_bt_dec_pwr_lvl); - - coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; -} - -void halbtc8812a2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s set FW Dac Swing level = %d\n", - (force_exec ? "force to" : ""), fw_dac_swing_lvl); - BTC_TRACE(trace_buf); - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8812a2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - -void halbtc8812a2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist, - IN boolean rx_rf_shrink_on) -{ - if (rx_rf_shrink_on) { - /* Shrink RF Rx LPF corner */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Shrink RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, - 0xffffc); - } else { - /* Resume RF Rx LPF corner */ - /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ - if (btcoexist->initilized) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Resume RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, coex_dm->bt_rf_0x1e_backup); - } - } -} - -void halbtc8812a2ant_rf_shrink(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rx_rf_shrink_on) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s turn Rx RF Shrink = %s\n", - (force_exec ? "force to" : ""), - ((rx_rf_shrink_on) ? "ON" : "OFF")); - BTC_TRACE(trace_buf); - coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; - - if (!force_exec) { - if (coex_dm->pre_rf_rx_lpf_shrink == - coex_dm->cur_rf_rx_lpf_shrink) - return; - } - halbtc8812a2ant_set_sw_rf_rx_lpf_corner(btcoexist, - coex_dm->cur_rf_rx_lpf_shrink); - - coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; -} - -void halbtc8812a2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 tmp_u1; - - tmp_u1 = btcoexist->btc_read_1byte(btcoexist, 0x4fd); - tmp_u1 |= BIT(0); - if (low_penalty_ra) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Tx rate adaptive, set low penalty!!\n"); - BTC_TRACE(trace_buf); - tmp_u1 &= ~BIT(2); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Tx rate adaptive, set normal!!\n"); - BTC_TRACE(trace_buf); - tmp_u1 |= BIT(2); - } - - btcoexist->btc_write_1byte(btcoexist, 0x4fd, tmp_u1); -} - -void halbtc8812a2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - return; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s turn LowPenaltyRA = %s\n", - (force_exec ? "force to" : ""), - ((low_penalty_ra) ? "ON" : "OFF")); - BTC_TRACE(trace_buf); - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8812a2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8812a2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, - IN u32 level) -{ - u8 val = (u8)level; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Write SwDacSwing = 0x%x\n", - level); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val); -} - -void halbtc8812a2ant_set_sw_full_time_dac_swing(IN struct btc_coexist - *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) -{ - if (sw_dac_swing_on) - halbtc8812a2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl); - else - halbtc8812a2ant_set_dac_swing_reg(btcoexist, 0x18); -} - - -void halbtc8812a2ant_dac_swing(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s turn DacSwing=%s, dac_swing_lvl=0x%x\n", - (force_exec ? "force to" : ""), ((dac_swing_on) ? "ON" : "OFF"), - dac_swing_lvl); - BTC_TRACE(trace_buf); - coex_dm->cur_dac_swing_on = dac_swing_on; - coex_dm->cur_dac_swing_lvl = dac_swing_lvl; - - if (!force_exec) { - if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && - (coex_dm->pre_dac_swing_lvl == - coex_dm->cur_dac_swing_lvl)) - return; - } - delay_ms(30); - halbtc8812a2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, - dac_swing_lvl); - - coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; - coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; -} - -void halbtc8812a2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean adc_back_off) -{ - if (adc_back_off) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1); - } -} - -void halbtc8812a2ant_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean adc_back_off) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s turn AdcBackOff = %s\n", - (force_exec ? "force to" : ""), - ((adc_back_off) ? "ON" : "OFF")); - BTC_TRACE(trace_buf); - - coex_dm->cur_adc_back_off = adc_back_off; - - if (!force_exec) { - if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) - return; - } - halbtc8812a2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off); - - coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; -} - -void halbtc8812a2ant_set_agc_table(IN struct btc_coexist *btcoexist, - IN boolean agc_table_en) -{ - u8 rssi_adjust_val = 0; - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x28F4B); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x10AB2); - rssi_adjust_val = 8; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x2884B); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x104B2); - } - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); - - /* set rssi_adjust_val for wifi module. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, - &rssi_adjust_val); -} - -void halbtc8812a2ant_agc_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean agc_table_en) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], %s %s Agc Table\n", - (force_exec ? "force to" : ""), - ((agc_table_en) ? "Enable" : "Disable")); - BTC_TRACE(trace_buf); - coex_dm->cur_agc_table_en = agc_table_en; - - if (!force_exec) { - if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) - return; - } - halbtc8812a2ant_set_agc_table(btcoexist, agc_table_en); - - coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; -} - -void halbtc8812a2ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8812a2ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", - (force_exec ? "force to" : ""), val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - BTC_TRACE(trace_buf); - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8812a2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8812a2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - switch (type) { - case 0: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 1: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 2: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5ffb5ffb, 0xffffff, 0x3); - break; - case 3: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3); - break; - case 4: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0xdfffdfff, 0x5fdb5fdb, 0xffffff, 0x3); - break; - case 5: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0x5ddd5ddd, 0x5fdb5fdb, 0xffffff, 0x3); - break; - case 6: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 7: - if (coex_sta->scan_ap_num <= 5) - halbtc8812a2ant_coex_table(btcoexist, - force_exec, 0xffffffff, 0xfafafafa, - 0xffffff, 0x3); - else - halbtc8812a2ant_coex_table(btcoexist, - force_exec, 0xffffffff, 0x5a5a5a5a, - 0xffffff, 0x3); - break; - case 8: - halbtc8812a2ant_coex_table(btcoexist, force_exec, - 0x5f5f5f5f, 0x5a5a5a5a, 0xffffff, 0x3); - break; - - default: - break; - } -} - -void halbtc8812a2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 data_len = 3; - u8 buf[5] = {0}; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s BT Ignore Wlan_Act\n", - (enable ? "Enable" : "Disable")); - BTC_TRACE(trace_buf); - - buf[0] = data_len; - buf[1] = 0x1; /* OP_Code */ - buf[2] = 0x1; /* OP_Code_Length */ - if (enable) - buf[3] = 0x1; /* OP_Code_Content */ - else - buf[3] = 0x0; - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); -} - -void halbtc8812a2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], %s turn Ignore WlanAct %s\n", - (force_exec ? "force to" : ""), (enable ? "ON" : "OFF")); - BTC_TRACE(trace_buf); - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8812a2ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8812a2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - } - } - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PS-TDMA H2C cmd =0x%x%08x\n", - h2c_parameter[0], - h2c_parameter[1] << 24 | h2c_parameter[2] << 16 | - h2c_parameter[3] << 8 | h2c_parameter[4]); - - BTC_TRACE(trace_buf); - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8812a2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8812a2ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8812a2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8812a2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, - IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, - IN boolean limited_dig, IN boolean bt_lna_constrain) -{ - /* - u32 wifi_bw; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if(BTC_WIFI_BW_HT40 != wifi_bw) - { - if (shrink_rx_lpf) - shrink_rx_lpf = false; - } - */ - - halbtc8812a2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); - /* halbtc8812a2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); */ -} - -void halbtc8812a2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, - IN boolean agc_table_shift, IN boolean adc_back_off, - IN boolean sw_dac_swing, IN u32 dac_swing_lvl) -{ - /* halbtc8812a2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */ - halbtc8812a2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); - halbtc8812a2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, - dac_swing_lvl); -} - -void halbtc8812a2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - u8 u8tmp = 0; - - if (init_hwcfg) { - btcoexist->btc_write_4byte(btcoexist, 0x900, 0x00000400); - btcoexist->btc_write_1byte(btcoexist, 0x76d, 0x1); - } else if (wifi_off) { - - } - - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_WIFI_AT_CPL_MAIN: - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7); - u8tmp &= ~BIT(2); - u8tmp |= BIT(3); - btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp); - break; - case BTC_ANT_WIFI_AT_CPL_AUX: - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7); - u8tmp &= ~BIT(3); - u8tmp |= BIT(2); - btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp); - break; - default: - break; - } -} - -void halbtc8812a2ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - s8 wifi_duration_adjust = 0x0; - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - if (!force_exec) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_ps_tdma_on = %d, cur_ps_tdma_on = %d!!\n", - coex_dm->pre_ps_tdma_on, coex_dm->cur_ps_tdma_on); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_ps_tdma = %d, cur_ps_tdma = %d!!\n", - coex_dm->pre_ps_tdma, coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - - if (coex_sta->scan_ap_num >= 40) - wifi_duration_adjust = -15; - else if (coex_sta->scan_ap_num >= 20) - wifi_duration_adjust = -10; - - /* - if (!coex_sta->force_lps_on) - { - ps_tdma_byte0_val = 0x61; - ps_tdma_byte3_val = 0x11; - ps_tdma_byte4_val = 0x10; - } - - - if ( (type == 3) || (type == 13) || (type == 14) ) - { - ps_tdma_byte4_val = ps_tdma_byte4_val & 0xbf; - - if (!wifi_busy) - ps_tdma_byte4_val = ps_tdma_byte4_val | 0x1; - } - - if (bt_link_info->slave_role == true) - ps_tdma_byte4_val = ps_tdma_byte4_val | 0x1; - - */ - if (turn_on) { - switch (type) { - case 1: - default: /* d1,wb */ - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0x11, 0x10); - break; - case 2: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x32, 0x03, 0x11, 0x10); - break; - case 3: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x28, 0x03, 0x11, 0x10); - break; - case 4: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1e, 0x03, 0x11, 0x10); - break; - case 5: /* d1,pb,TXpause */ - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x63, - 0x3c, 0x03, 0x90, 0x10); - break; - case 6: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x63, - 0x32, 0x03, 0x90, 0x10); - break; - case 7: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x63, - 0x28, 0x03, 0x90, 0x10); - break; - case 8: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x63, - 0x1e, 0x03, 0x90, 0x10); - break; - case 9: /* d1,bb */ - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0x31, 0x10); - break; - case 10: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x32, 0x03, 0x31, 0x10); - break; - case 11: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x28, 0x03, 0x31, 0x10); - break; - case 12: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1e, 0x03, 0x31, 0x10); - break; - case 13: /* d1,bb,TXpause */ - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0x30, 0x10); - break; - case 14: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x32, 0x03, 0x30, 0x10); - break; - case 15: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x28, 0x03, 0x30, 0x10); - break; - case 16: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1e, 0x03, 0x30, 0x10); - break; - case 17: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x3, 0x11, 0x11); - break; - case 18: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x5, 0x5, 0xe1, 0x90); - break; - case 19: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0xe1, 0x90); - break; - case 20: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0x60, 0x90); - break; - case 21: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x3, 0x70, 0x90); - break; - case 22: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x61, - 0x1a, 0x1a, 0x21, 0x10); - break; - case 23: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x03, 0x31, 0x10); - break; - - case 71: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1a, 0x1a, 0xe1, 0x90); - break; - - /* following cases is for wifi rssi low, started from 81 */ - case 80: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, - 0x3c, 0x3, 0x90, 0x50); - break; - case 81: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, - 0x3a + wifi_duration_adjust, 0x3, 0x90, - 0x50); - break; - case 82: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, - 0x30 + wifi_duration_adjust, 0x03, 0x90, - 0x50); - break; - case 83: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, - 0x21, 0x03, 0x90, 0x50); - break; - case 84: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, - 0x15, 0x3, 0x90, 0x50); - break; - case 85: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, - 0x1d, 0x1d, 0x80, 0x50); - break; - case 86: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53, - 0x15, 0x15, 0x80, 0x50); - break; - } - } else { - /* disable PS tdma */ - switch (type) { - case 0: /* ANT2PTA, 0x778=0x1 */ - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - break; - case 1: /* ANT2BT, 0x778=3 */ - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x8, 0x0); - delay_ms(5); - halbtc8812a2ant_set_ant_path(btcoexist, - BTC_ANT_WIFI_AT_CPL_AUX, false, false); - break; - case 2: /* ANT2BT, 0x778=3 */ - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x8, 0x0); - delay_ms(5); - halbtc8812a2ant_set_ant_path(btcoexist, - BTC_ANT_WIFI_AT_CPL_MAIN, false, false); - break; - default: - halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - - -void halbtc8812a2ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - - -void halbtc8812a2ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - ps_type = BTC_PS_WIFI_NATIVE; - lps_val = 0x0; - rpwm_val = 0x0; - } - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8812a2ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8812a2ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8812a2ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - -void halbtc8812a2ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* fw all off */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0); - - halbtc8812a2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - -void halbtc8812a2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - struct btc_stack_info *stack_info = &btcoexist->stack_info; - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - /* only 8812a need to consider if core stack is installed. */ - /*if (!stack_info->hci_version)*/ - /*bt_active = false;*/ - - bt_disabled = btcoexist->bt_info.bt_disabled; - - if (coex_sta->pre_bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->pre_bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->pre_bt_disabled = bt_disabled; - - if (bt_disabled) { - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 2); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - } - } -} - - -void halbtc8812a2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - - -boolean halbtc8812a2ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean common = false, wifi_connected = false, wifi_busy = false; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_bt_inquiry(btcoexist); - return true; - } - - if (bt_link_info->sco_exist || bt_link_info->hid_exist) - halbtc8812a2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0); - else - halbtc8812a2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - if (!wifi_connected) { - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non-connected idle!!\n"); - BTC_TRACE(trace_buf); - - if ((BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || - (BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } else { - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - } - - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - common = true; - } else { - if (BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, - false, false, 0x8); - - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else if (BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status) { - if (bt_hs_on) - return false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, - false, false, 0x8); - - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - common = false; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - - halbtc8812a2ant_limited_rx(btcoexist, - NORMAL_EXEC, false, false, 0x8); - - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 17); - - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, - NORMAL_EXEC, 6); - halbtc8812a2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, 0); - halbtc8812a2ant_sw_mechanism1(btcoexist, false, - false, false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, - false, false, 0x18); - common = true; - } - } - } - - return common; -} - -void halbtc8812a2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, - IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], TdmaDurationAdjust()\n"); - BTC_TRACE(trace_buf); - - coex_dm->auto_tdma_adjust_low_rssi = false; - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], first run TdmaDurationAdjust()!!\n"); - BTC_TRACE(trace_buf); - { - if (sco_hid) { - if (tx_pause) { - if (max_interval == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } else if (max_interval == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (max_interval == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } else { - if (max_interval == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } else if (max_interval == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (max_interval == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } else { - if (tx_pause) { - if (max_interval == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (max_interval == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (max_interval == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } - } else { - if (max_interval == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (max_interval == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (max_interval == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } - } - } - } - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* acquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], retry_count = %d\n", - retry_count); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_count=%d\n", - up, dn, m, n, wait_count); - BTC_TRACE(trace_buf); - - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Increase wifi duration!!\n"); - BTC_TRACE(trace_buf); - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration */ - if (wait_count <= 2) - m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ - else - m = 1; - - if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Decrease wifi duration for retry_counter<3!!\n"); - BTC_TRACE(trace_buf); - } - } else { /* retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration */ - if (wait_count == 1) - m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ - else - m = 1; - - if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Decrease wifi duration for retry_counter>3!!\n"); - BTC_TRACE(trace_buf); - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], max Interval = %d\n", - max_interval); - BTC_TRACE(trace_buf); - - if (max_interval == 1) { - if (tx_pause) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], TxPause = 1\n"); - BTC_TRACE(trace_buf); - - if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 13); - coex_dm->ps_tdma_du_adj_type = 13; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } - } - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], TxPause = 0\n"); - BTC_TRACE(trace_buf); - - if (coex_dm->cur_ps_tdma == 5) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 1); - coex_dm->ps_tdma_du_adj_type = 1; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } - } - } - } else if (max_interval == 2) { - if (tx_pause) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], TxPause = 1\n"); - BTC_TRACE(trace_buf); - - if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } - } - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], TxPause = 0\n"); - BTC_TRACE(trace_buf); - - if (coex_dm->cur_ps_tdma == 5) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } - } - } - } else if (max_interval == 3) { - if (tx_pause) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], TxPause = 1\n"); - BTC_TRACE(trace_buf); - - if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], TxPause = 0\n"); - BTC_TRACE(trace_buf); - - if (coex_dm->cur_ps_tdma == 5) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8812a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8812a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } - } - } - - /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ - /* then we have to adjust it back to the previous record one. */ - if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", - coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (!scan && !link && !roam) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); - BTC_TRACE(trace_buf); - } - } -} - -/* ****************** - * pstdma for wifi rssi low - * ****************** */ -void halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - IN struct btc_coexist *btcoexist/* , */ /* IN u8 wifi_status */) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0, bt_info_ext; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low()\n"); - BTC_TRACE(trace_buf); -#if 0 - if ((BT_8812A_2ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == - wifi_status) || - (BT_8812A_2ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) || - (BT_8812A_2ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT == - wifi_status)) { - if (coex_dm->cur_ps_tdma != 81 && - coex_dm->cur_ps_tdma != 82 && - coex_dm->cur_ps_tdma != 83 && - coex_dm->cur_ps_tdma != 84) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 82); - coex_dm->ps_tdma_du_adj_type = 82; - - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } - return; - } -#endif - coex_dm->auto_tdma_adjust = false; - - retry_count = coex_sta->bt_retry_cnt; - bt_info_ext = coex_sta->bt_info_ext; - - if (!coex_dm->auto_tdma_adjust_low_rssi) { - coex_dm->auto_tdma_adjust_low_rssi = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], first run TdmaDurationAdjustForWifiRssiLow()!!\n"); - BTC_TRACE(trace_buf); - - if (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 83); - coex_dm->ps_tdma_du_adj_type = 83; - } else { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 82); - coex_dm->ps_tdma_du_adj_type = 82; - } - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* acquire the BT TRx retry count from BT_Info byte2 - * retry_count = coex_sta->bt_retry_cnt; - * bt_info_ext = coex_sta->bt_info_ext; */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], retry_count = %d\n", - retry_count); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_count=%d\n", - up, dn, m, n, wait_count); - BTC_TRACE(trace_buf); - result = 0; - wait_count++; - - if ((coex_sta->low_priority_tx) > 1050 || - (coex_sta->low_priority_rx) > 1250) - retry_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Increase wifi duration!!\n"); - BTC_TRACE(trace_buf); - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration */ - if (wait_count <= 2) - m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ - else - m = 1; - - if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Decrease wifi duration for retry_counter<3!!\n"); - BTC_TRACE(trace_buf); - } - } else { /* retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration */ - if (wait_count == 1) - m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ - else - m = 1; - - if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Decrease wifi duration for retry_counter>3!!\n"); - BTC_TRACE(trace_buf); - } - - if (result == -1) { - /* - if( (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 81) ||(coex_dm->cur_ps_tdma == 82)) ) - { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 84); - coex_dm->ps_tdma_du_adj_type = 84; - } - */ - if (coex_dm->cur_ps_tdma == 80) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 82); - coex_dm->ps_tdma_du_adj_type = 82; - } else if (coex_dm->cur_ps_tdma == 81) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 82); - coex_dm->ps_tdma_du_adj_type = 82; - } else if (coex_dm->cur_ps_tdma == 82) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 83); - coex_dm->ps_tdma_du_adj_type = 83; - } else if (coex_dm->cur_ps_tdma == 83) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 84); - coex_dm->ps_tdma_du_adj_type = 84; - } - } else if (result == 1) { - /* - if( (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) && - ((coex_dm->cur_ps_tdma == 81) ||(coex_dm->cur_ps_tdma == 82)) ) - { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 83); - coex_dm->ps_tdma_du_adj_type = 83; - } - */ - if (coex_dm->cur_ps_tdma == 84) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 83); - coex_dm->ps_tdma_du_adj_type = 83; - } else if (coex_dm->cur_ps_tdma == 83) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 82); - coex_dm->ps_tdma_du_adj_type = 82; - } else if (coex_dm->cur_ps_tdma == 82) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 81); - coex_dm->ps_tdma_du_adj_type = 81; - } else if ((coex_dm->cur_ps_tdma == 81) && - ((coex_sta->scan_ap_num <= 5))) { - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 81); - coex_dm->ps_tdma_du_adj_type = 81; - } - } - - if (coex_dm->cur_ps_tdma != 80 && - coex_dm->cur_ps_tdma != 81 && - coex_dm->cur_ps_tdma != 82 && - coex_dm->cur_ps_tdma != 83 && - coex_dm->cur_ps_tdma != 84) { - /* recover to previous adjust type */ - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - } - } -} - -void halbtc8812a2ant_get_bt_rssi_threshold(IN struct btc_coexist *btcoexist, - IN u8 *pThres0, IN u8 *pThres1) -{ - u8 ant_type; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &ant_type); - - - switch (ant_type) { - case BTC_ANT_TYPE_0: - *pThres0 = 100; - *pThres1 = 100; - break; - case BTC_ANT_TYPE_1: - *pThres0 = 34; - *pThres1 = 42; - break; - case BTC_ANT_TYPE_2: - *pThres0 = 34; - *pThres1 = 42; - break; - case BTC_ANT_TYPE_3: - *pThres0 = 34; - *pThres1 = 42; - break; - case BTC_ANT_TYPE_4: - *pThres0 = 34; - *pThres1 = 42; - break; - default: - break; - } -} - - - -void halbtc8812a2ant_action_sco(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - - /* halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); */ - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); - - /* power save state */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* coex table */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - /* pstdma */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - else - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - true, 0x6); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - true, 0x6); - } - } -} - -void halbtc8812a2ant_action_sco_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - /* halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); */ - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); - - /* power save state */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* coex table */ - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - /* pstdma */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13); - else - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9); - - /* decrease BT power */ - if (BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x6); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x6); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x6); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x6); - } - } -} - -void halbtc8812a2ant_action_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 anttype = 0; - - - btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype); - - - /* halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); - * bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, bt_thresh1); */ - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); - - - if (anttype == 0) { /* ANTTYPE = 0 92E 2ant with SPDT */ - /* power save state & pstdma & coex table */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (anttype == - 1) { /* 92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation */ - /* power save state & pstdma & coex table */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (anttype == - 2) { /* ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation */ - /* power save state & pstdma & coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & shielding room */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, 9); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - } else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & noisy environment */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, 9); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - } else { /* WIFI RSSI || BT RSSI == low */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, 9); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - } - } else if (anttype == - 3) { /* ANTTYPE = 3, 92E 3ant with good ant. isolation */ - /* power save state & pstdma & coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & shielding room */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 1); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - } else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & noisy environment */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 1); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - } else { /* WIFI RSSI || BT RSSI == low */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 1); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - } - } else { /* ANTTYPE = 4 for test */ - /* power save state & pstdma & coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & shielding room */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & noisy environment */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } else { /* WIFI RSSI || BT RSSI == low */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } - - - /* power save state */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* coex table */ - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - /* decrease BT power */ - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8812a2ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 anttype = 0; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype); - - /* halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); - * bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, bt_thresh1); */ - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); - - /* anttype = 4; */ - - if (anttype == 0) { /* ANTTYPE = 0 92E 2ant with SPDT */ - - if (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A) { - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 0); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) { - /* WIFI RSSI = high & BT RSSI = high & shielding room */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } else { /* WIFI RSSI || BT RSSI == low */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } - - /* power save state & pstdma & coex table - * - if(BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) && (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) - { - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } - else if (BTC_RSSI_HIGH(wifi_rssi_state)&&(!BTC_RSSI_LOW(bt_rssi_state)) && (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) - { - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } - else - { - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } - */ - } else if (anttype == - 1) { /* 92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation */ - /* power save state & pstdma & coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & shielding room */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, - false, 1); /* shielding room */ - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & noisy environment */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 1); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - } else { /* WIFI RSSI || BT RSSI == low */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - - } else if (anttype == - 2) { /* ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation */ - /* power save state & pstdma & coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & shielding room */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, - false, 1); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 5); - } else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & noisy environment */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 1); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - } else { /* WIFI RSSI || BT RSSI == low */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } else if (anttype == - 3) { /* ANTTYPE = 3, 92E 3ant with good ant. isolation */ - /* power save state & pstdma & coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & shielding room */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 1); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - } else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & noisy environment */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 1); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - } else { /* WIFI RSSI || BT RSSI == low */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 1); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - } - } else { /* ANTTYPE = 4 for test */ - /* power save state & pstdma & coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & shielding room */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & noisy environment */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } else { /* WIFI RSSI || BT RSSI == low */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } - - /* decrease BT power */ - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* decrease BT power - * - if(BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if(BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else if (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - */ - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8812a2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - /* halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); */ - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); - - /* power save state */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, false, - 2); - else - halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, true, 2); - - /* decrease BT power */ - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - /* - - if(BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if(BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - */ - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - true, 0x6); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - true, 0x6); - } - } -} - -void halbtc8812a2ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1); - else - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85); - - /* decrease BT power */ - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* PAN(HS) only */ -void halbtc8812a2ant_action_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); - - /* power save state */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* coex table */ - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - /* pstdma */ - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - /* decrease BT power */ - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* - - if(BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if(BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - */ - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* PAN(EDR)+A2DP */ -void halbtc8812a2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, false, - 3); - else { - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); - } - - /* decrease BT power */ - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - - -void halbtc8812a2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - else - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85); - - /* decrease BT power */ - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* - - if(BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if(BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - */ - /* limited Rx */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, - 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* HID+A2DP+PAN(EDR) */ -void halbtc8812a2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, false, 3); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 3); - else { - coex_dm->auto_tdma_adjust = false; - halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86); - } - - /* decrease BT power */ - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - /* - - if(BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if(BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - */ - /* limited Rx */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, - 0x8); - - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8812a2ant_action_hid_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 bt_thresh0 = 0, bt_thresh1 = 0; - - halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, - &bt_thresh1); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, - bt_thresh1); - - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */ - - /* power save state */ - halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - else - halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* pstdma */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, false, 2); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 2); - else - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 2); - - /* decrease BT power */ - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* - - if(BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if(BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - */ - /* limited Rx */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else if (BTC_RSSI_LOW(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state))) - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - else - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, - 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8812a2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH, - bt_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_bw; - u8 anttype = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype); - - - /* halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); - * bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, bt_thresh1); */ - - wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34, - 0); - bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); - - if (anttype == 0) { /* ANTTYPE = 0 92E 2ant with SPDT */ - /* power save state & pstdma & coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, - 83); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - - } else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 0); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - } else { - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, - 83); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - } - } else if (anttype == - 1) { /* 92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation */ - /* power save state & pstdma & coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, - true, 2); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - } else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 0); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - } else { - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, - 83); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - } - } else if (anttype == - 2) { /* ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation */ - /* power save state & pstdma & coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & shielding room */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, - true, 2); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - } else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & noisy environment */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 0); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - } else { /* WIFI RSSI || BT RSSI == low */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, - 83); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - } - } else if (anttype == - 3) { /* ANTTYPE = 3, 92E 3ant with good ant. isolation */ - /* power save state & pstdma & coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & shielding room */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 1); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - } else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & noisy environment */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 1); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - } else { /* WIFI RSSI || BT RSSI == low */ - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 1); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - } - } else { /* ANTTYPE = 4 for test */ - /* power save state & pstdma & coex table */ - if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & shielding room */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } else if (BTC_RSSI_HIGH(wifi_rssi_state) && - (!BTC_RSSI_LOW(bt_rssi_state)) && - (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) { - /* WIFI RSSI = high & BT RSSI = high & noisy environment */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } else { /* WIFI RSSI || BT RSSI == low */ - halbtc8812a2ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low( - btcoexist); - halbtc8812a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 7); - } - } - - /* decrease BT power */ - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* - - if(BTC_RSSI_LOW(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - else if(BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else if (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A) - halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4); - */ - /* limited Rx */ - halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - /* fw dac swing level */ - halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8812a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8812a2ant_coex_under_5g(IN struct btc_coexist *btcoexist) -{ - halbtc8812a2ant_coex_all_off(btcoexist); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Under 5G, force set BT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true); -} -/* **************************************************** */ -void halbtc8812a2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - boolean wifi_under_5g = false; - u8 algorithm = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_coex_under_5g(btcoexist); - return; - } - - - algorithm = halbtc8812a2ant_action_algorithm(btcoexist); - if (coex_sta->c2h_bt_inquiry_page && - (BT_8812A_2ANT_COEX_ALGO_PANHS != algorithm)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_bt_inquiry(btcoexist); - return; - } - - coex_dm->cur_algorithm = algorithm; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", - coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - - if (halbtc8812a2ant_is_common_action(btcoexist)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant common.\n"); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - } else { - if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", - coex_dm->pre_algorithm, coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - coex_dm->auto_tdma_adjust_low_rssi = false; - } - switch (coex_dm->cur_algorithm) { - case BT_8812A_2ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_sco(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_SCO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_sco_hid(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_hid(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_a2dp(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_pan_edr(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_pan_hs(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_pan_edr_hid(btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_hid_a2dp_pan_hs( - btcoexist); - break; - case BT_8812A_2ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_action_hid_a2dp(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_coex_all_off(btcoexist); - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } - -} - -void halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up) -{ - u8 u8tmp = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - if (back_up) { - /* backup rf 0x1e value */ - coex_dm->bt_rf_0x1e_backup = - btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff); - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } - - /* ant sw control to BT */ - halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, true, - false); - - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* PTA parameter */ - btcoexist->btc_write_1byte(btcoexist, 0x6cc, 0x0); - btcoexist->btc_write_4byte(btcoexist, 0x6c8, 0xffff); - btcoexist->btc_write_4byte(btcoexist, 0x6c4, 0x55555555); - btcoexist->btc_write_4byte(btcoexist, 0x6c0, 0x55555555); - - /* coex parameters */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - - /* enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - /* disable PTA to avoid BT insn't on */ - btcoexist->btc_write_1byte(btcoexist, 0x40, 0x00); - - /* bt clock related */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x4); - u8tmp |= BIT(7); - btcoexist->btc_write_1byte(btcoexist, 0x4, u8tmp); - - /* bt clock related */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7); - u8tmp |= BIT(1); - btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp); - - /* Give bt_coex_supported_version the default value */ - coex_sta->bt_coex_supported_version = 0; - -} - -/* ************************************************************ - * work around function start with wa_halbtc8812a2ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8812a2ant_ - * ************************************************************ */ -void ex_halbtc8812a2ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8812a2ant_init_hw_config(btcoexist, true); -} - -void ex_halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - halbtc8812a2ant_init_coex_dm(btcoexist); -} - - -void ex_halbtc8812a2ant_pta_off_on_notify(IN struct btc_coexist *btcoexist, - IN u8 bt_status) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BToff/on notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_BT_OFF == bt_status) { - /* PTA off */ - btcoexist->bt_info.bt_disabled = true; - halbtc8812a2ant_enable_pta(btcoexist, FORCE_EXEC, false); - - } else { - /* PTA on */ - btcoexist->bt_info.bt_disabled = false; - halbtc8812a2ant_enable_pta(btcoexist, FORCE_EXEC, true); - } - -} - - -void ex_halbtc8812a2ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; - u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; - u32 phyver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - -#if 0 - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Antenna type:", - board_info->ant_type); - CL_PRINTF(cli_buf); -#endif - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", - "BT stack/ hci ext ver", - ((stack_info->profile_notified) ? "Yes" : "No"), - stack_info->hci_version); - CL_PRINTF(cli_buf); - - bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); - bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", - "CoexVer WL/ BT_Desired/ BT_Report", - glcoex_ver_date_8812a_2ant, glcoex_ver_8812a_2ant, - glcoex_ver_btdesired_8812a_2ant, bt_coex_ver, - (bt_coex_ver == 0xff ? "Unknown" : (bt_coex_ver >= - glcoex_ver_btdesired_8812a_2ant ? "Match" : - "Mis-Match"))); - CL_PRINTF(cli_buf); - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ v%d", - "W_FW/ B_FW/ Phy", - fw_ver, bt_patch_ver, phyver); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((btcoexist->bt_info.bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", - "SCO/HID/PAN/A2DP", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8812A_2ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8812a_2ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - /* Sw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Sw mechanism]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", - "SM1[ShRf/ LpRA/ LimDig]", - coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, - coex_dm->limited_dig); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", - "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", - coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, - coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Rate Mask", - btcoexist->bt_info.ra_mask); - CL_PRINTF(cli_buf); - - /* Fw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Fw mechanism]============"); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d/%d)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - coex_dm->auto_tdma_adjust, - coex_dm->auto_tdma_adjust_low_rssi); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "DecBtPwr/ IgnWlanAct", - coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", - "RF-A, 0x1e initVal", - coex_dm->bt_rf_0x1e_backup); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "backup ARFR1/ARFR2/RL/AMaxTime", - coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2, - coex_dm->backup_retry_limit, - coex_dm->backup_ampdu_max_time); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x ", - "0x778 (W_Act)/ 0x6cc (CoTab Sel)", - u8tmp[0], u8tmp[1]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x8db); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xc5b); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x8db(ADC)/0xc5b[29:25](DAC)", - ((u8tmp[0] & 0x60) >> 5), ((u8tmp[1] & 0x3e) >> 1)); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcb3); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb7); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xcb3/ 0xcb7", - u8tmp[0], u8tmp[1]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x974); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x40/ 0x4c[24:23]/ 0x974", - u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u32tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa0a); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xc50(DIG)/0xa0a(CCK-TH)", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_CCK); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8812A_2ANT == 1) - halbtc8812a2ant_monitor_bt_ctr(btcoexist); -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8812a2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - boolean wifi_under_5g = false; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - - coex_sta->under_ips = true; - halbtc8812a2ant_coex_all_off(btcoexist); - halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, - false, true); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS notify, force set BT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - - halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - ex_halbtc8812a2ant_media_status_notify(btcoexist, - BTC_MEDIA_DISCONNECT); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - - coex_sta->under_ips = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, - &wifi_under_5g); - if (!wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS notify, force set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - - halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, - false); - } - } -} - -void ex_halbtc8812a2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - - coex_sta->under_lps = false; - } -} - -void ex_halbtc8812a2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_SCAN_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_SCAN_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - } -} - -void ex_halbtc8812a2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_ASSOCIATE_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_ASSOCIATE_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8812a2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 data_len = 5; - u8 buf[6] = {0}; - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - btcoexist->bt_info.bt_disabled) - return; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = 0x1; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - buf[0] = data_len; - buf[1] = 0x5; /* OP_Code */ - buf[2] = 0x3; /* OP_Code_Length */ - buf[3] = h2c_parameter[0]; /* OP_Code_Content */ - buf[4] = h2c_parameter[1]; - buf[5] = h2c_parameter[2]; - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); -} - -void ex_halbtc8812a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (type == BTC_PACKET_DHCP) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], DHCP Packet notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8812a2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean bt_busy = false, limited_dig = false; - boolean wifi_connected = false, wifi_under_5g = false; - - coex_sta->c2h_bt_info_req_sent = false; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8812A_2ANT_MAX) - rsp_source = BT_INFO_SRC_8812A_2ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (BT_INFO_SRC_8812A_2ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8812a2ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8812a2ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if ((coex_sta->bt_info_ext & BIT(3)) && !wifi_under_5g) { - /* BT already ignored WlanAct */ - if (!btcoexist->manual_control && - !btcoexist->stop_coex_dm) { - if (!coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_ignore_wlan_act( - btcoexist, FORCE_EXEC, false); - } - } - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - - if (coex_sta->under_ips) { - /* work around for 8812a combo hw bug => when IPS, wlanAct is always high. */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS, set BT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8812a2ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, true); - } - } - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8812A_2ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8812A_2ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - coex_sta->acl_busy = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8812A_2ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8812A_2ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8812A_2ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8812A_2ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - if (bt_info & BT_INFO_8812A_2ANT_B_ACL_BUSY) - coex_sta->acl_busy = true; - else - coex_sta->acl_busy = false; - - } - - halbtc8812a2ant_update_bt_link_info(btcoexist); - - if (!(bt_info & BT_INFO_8812A_2ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8812A_2ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8812A_2ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8812A_2ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8812A_2ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8812A_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8812A_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { - bt_busy = true; - if (!wifi_under_5g) - limited_dig = true; - } else { - bt_busy = false; - limited_dig = false; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - coex_dm->limited_dig = limited_dig; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); - - halbtc8812a2ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8812a2ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, false, - true); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Halt notify, force set BT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - - halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - ex_halbtc8812a2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - /* 0x522=0xff, pause tx */ - btcoexist->btc_write_1byte(btcoexist, 0x522, 0xff); - /* 0x40[7:6]=2'b01, modify BT mode. */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0xc0, 0x2); - /* PTA off. */ -#ifndef CONFIG_PCI_HCI - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x0); -#endif -} - -void ex_halbtc8812a2ant_periodical(IN struct btc_coexist *btcoexist) -{ - static u8 dis_ver_info_cnt = 0; - u32 fw_ver = 0, bt_patch_ver = 0; - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ==========================Periodical===========================\n"); - BTC_TRACE(trace_buf); - - if (dis_ver_info_cnt <= 5) { - dis_ver_info_cnt += 1; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ****************************************************************\n"); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", - board_info->pg_ant_num, board_info->btdm_ant_num, - board_info->btdm_ant_pos); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT stack/ hci ext ver = %s / %d\n", - ((stack_info->profile_notified) ? "Yes" : "No"), - stack_info->hci_version); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, - &bt_patch_ver); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", - glcoex_ver_date_8812a_2ant, glcoex_ver_8812a_2ant, - fw_ver, bt_patch_ver, bt_patch_ver); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ****************************************************************\n"); - BTC_TRACE(trace_buf); - } - - if ((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) - coex_sta->bt_coex_supported_version = - btcoexist->btc_get_bt_coex_supported_version(btcoexist); - -#if (BT_AUTO_REPORT_ONLY_8812A_2ANT == 0) - halbtc8812a2ant_query_bt_info(btcoexist); - halbtc8812a2ant_monitor_bt_ctr(btcoexist); - halbtc8812a2ant_monitor_wifi_ctr(btcoexist); - halbtc8812a2ant_monitor_bt_enable_disable(btcoexist); -#else - halbtc8812a2ant_monitor_wifi_ctr(btcoexist); - - if (halbtc8812a2ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust || - coex_dm->auto_tdma_adjust_low_rssi) - halbtc8812a2ant_run_coexist_mechanism(btcoexist); -#endif -} - -void ex_halbtc8812a2ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata) -{ - switch (op_code) { - case BTC_DBG_SET_COEX_DEC_BT_PWR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set Dec BT power\n"); - BTC_TRACE(trace_buf); - - { - u8 data_len = 4; - u8 buf[6] = {0}; - u8 dec_bt_pwr = 0, pwr_level = 0; - - if (op_len == 2) { - dec_bt_pwr = pdata[0]; - pwr_level = pdata[1]; - - buf[0] = data_len; - buf[1] = 0x3; /* OP_Code */ - buf[2] = 0x2; /* OP_Code_Length */ - - buf[3] = dec_bt_pwr; /* OP_Code_Content */ - buf[4] = pwr_level; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set Dec BT power=%d, pwr_level=%d\n", - dec_bt_pwr, pwr_level); - BTC_TRACE(trace_buf); - - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); - } - } - break; - - case BTC_DBG_SET_COEX_BT_AFH_MAP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT AFH Map\n"); - BTC_TRACE(trace_buf); - { - u8 data_len = 5; - u8 buf[6] = {0}; - - if (op_len == 3) { - buf[0] = data_len; - buf[1] = 0x5; /* OP_Code */ - buf[2] = 0x3; /* OP_Code_Length */ - - buf[3] = pdata[0]; /* OP_Code_Content */ - buf[4] = pdata[1]; - buf[5] = pdata[2]; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT AFH Map = %02x %02x %02x\n", - pdata[0], pdata[1], pdata[2]); - BTC_TRACE(trace_buf); - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); - } - } - break; - - case BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT Ignore Wlan Active\n"); - BTC_TRACE(trace_buf); - { - u8 data_len = 3; - u8 buf[6] = {0}; - - if (op_len == 1) { - buf[0] = data_len; - buf[1] = 0x1; /* OP_Code */ - buf[2] = 0x1; /* OP_Code_Length */ - - buf[3] = pdata[0]; /* OP_Code_Content */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set BT Ignore Wlan Active = 0x%x\n", - pdata[0]); - BTC_TRACE(trace_buf); - - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_CTRL_BT_COEX, - (void *)&buf[0]); - } - } - break; - - default: - break; - } -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ - diff --git a/hal/btc/halbtc8812a2ant.h b/hal/btc/halbtc8812a2ant.h deleted file mode 100644 index 2b7f4aa..0000000 --- a/hal/btc/halbtc8812a2ant.h +++ /dev/null @@ -1,241 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8812A_SUPPORT == 1) - -/* ******************************************* - * The following is for 8812A 2Ant BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8812A_2ANT 0 - -#define BT_INFO_8812A_2ANT_B_FTP BIT(7) -#define BT_INFO_8812A_2ANT_B_A2DP BIT(6) -#define BT_INFO_8812A_2ANT_B_HID BIT(5) -#define BT_INFO_8812A_2ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8812A_2ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8812A_2ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8812A_2ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8812A_2ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT 2 -#define NOISY_AP_NUM_THRESH_8812A 50 - -enum bt_info_src_8812a_2ant { - BT_INFO_SRC_8812A_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8812A_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8812A_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8812A_2ANT_MAX -}; - -enum bt_8812a_2ant_bt_status { - BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8812A_2ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8812A_2ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8812A_2ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8812A_2ANT_BT_STATUS_MAX -}; - -enum bt_8812a_2ant_coex_algo { - BT_8812A_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8812A_2ANT_COEX_ALGO_SCO = 0x1, - BT_8812A_2ANT_COEX_ALGO_SCO_HID = 0x2, - BT_8812A_2ANT_COEX_ALGO_HID = 0x3, - BT_8812A_2ANT_COEX_ALGO_A2DP = 0x4, - BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS = 0x5, - BT_8812A_2ANT_COEX_ALGO_PANEDR = 0x6, - BT_8812A_2ANT_COEX_ALGO_PANHS = 0x7, - BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8, - BT_8812A_2ANT_COEX_ALGO_PANEDR_HID = 0x9, - BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa, - BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS = 0xb, - BT_8812A_2ANT_COEX_ALGO_HID_A2DP = 0xc, - BT_8812A_2ANT_COEX_ALGO_MAX = 0xd -}; - -struct coex_dm_8812a_2ant { - /* fw mechanism */ - u8 pre_bt_dec_pwr_lvl; - u8 cur_bt_dec_pwr_lvl; - u8 pre_fw_dac_swing_lvl; - u8 cur_fw_dac_swing_lvl; - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean auto_tdma_adjust_low_rssi; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_rf_rx_lpf_shrink; - boolean cur_rf_rx_lpf_shrink; - u32 bt_rf_0x1e_backup; - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - boolean pre_dac_swing_on; - u32 pre_dac_swing_lvl; - boolean cur_dac_swing_on; - u32 cur_dac_swing_lvl; - boolean pre_adc_back_off; - boolean cur_adc_back_off; - boolean pre_agc_table_en; - boolean cur_agc_table_en; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 cur_ra_mask_type; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - - boolean cur_enable_pta; - boolean pre_enable_pta; -}; - -struct coex_sta_8812a_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - boolean acl_busy; - - boolean under_lps; - boolean under_ips; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - u8 bt_rssi; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8812A_2ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8812A_2ANT_MAX]; - u32 bt_info_query_cnt; - boolean c2h_bt_inquiry_page; - u8 bt_retry_cnt; - u8 bt_info_ext; - u8 scan_ap_num; - boolean pre_bt_disabled; - u32 pre_bt_info_c2h_cnt_bt_rsp; - u32 pre_bt_info_c2h_cnt_bt_send; - boolean force_lps_on; - u32 bt_coex_supported_version; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8812a2ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8812a2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8812a2ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); - -void ex_halbtc8812a2ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a2ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a2ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8812a2ant_dbg_control(IN struct btc_coexist *btcoexist, - IN u8 op_code, IN u8 op_len, IN u8 *pdata); -void ex_halbtc8812a2ant_pta_off_on_notify(IN struct btc_coexist *btcoexist, - IN u8 bt_status); - -#else -#define ex_halbtc8812a2ant_power_on_setting(btcoexist) -#define ex_halbtc8812a2ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8812a2ant_init_coex_dm(btcoexist) -#define ex_halbtc8812a2ant_ips_notify(btcoexist, type) -#define ex_halbtc8812a2ant_lps_notify(btcoexist, type) -#define ex_halbtc8812a2ant_scan_notify(btcoexist, type) -#define ex_halbtc8812a2ant_connect_notify(btcoexist, type) -#define ex_halbtc8812a2ant_media_status_notify(btcoexist, type) -#define ex_halbtc8812a2ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8812a2ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8812a2ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8812a2ant_halt_notify(btcoexist) -#define ex_halbtc8812a2ant_periodical(btcoexist) -#define ex_halbtc8812a2ant_display_coex_info(btcoexist) -#define ex_halbtc8812a2ant_dbg_control(btcoexist, op_code, op_len, pdata) -#define ex_halbtc8812a2ant_pta_off_on_notify(btcoexist, bt_status) - -#endif - -#endif - diff --git a/hal/btc/halbtc8821a1ant.c b/hal/btc/halbtc8821a1ant.c deleted file mode 100644 index 5070897..0000000 --- a/hal/btc/halbtc8821a1ant.c +++ /dev/null @@ -1,3303 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for 8821A_1ANT Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ - * SY modify 2015/04/27 - * ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821A_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8821a_1ant glcoex_dm_8821a_1ant; -static struct coex_dm_8821a_1ant *coex_dm = &glcoex_dm_8821a_1ant; -static struct coex_sta_8821a_1ant glcoex_sta_8821a_1ant; -static struct coex_sta_8821a_1ant *coex_sta = &glcoex_sta_8821a_1ant; - -const char *const glbt_info_src_8821a_1ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8821a_1ant = 20160816; -u32 glcoex_ver_8821a_1ant = 0x63; -u32 glcoex_ver_btdesired_8821a_1ant = 0x62; - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8821a1ant_ - * ************************************************************ */ -u8 halbtc8821a1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8821a1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8821a1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8821a1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8821a1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8821a1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8821a1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8821a1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8821a1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8821a1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8821a1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8821a1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8821a1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - - -/* true/xxxx/x:1 - * false/false/x: 64 - * false/true/x:x */ -void halbtc8821a1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8821a1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; -#if 0 - /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ - if (!(btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8)) { - coex_sta->high_priority_tx = 65535; - coex_sta->high_priority_rx = 65535; - coex_sta->low_priority_tx = 65535; - coex_sta->low_priority_rx = 65535; - return; - } -#endif - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); -} - -void halbtc8821a1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ -#if 1 - - coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_VHT); - -#endif -} - - -void halbtc8821a1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -boolean halbtc8821a1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - } - - return false; -} - -void halbtc8821a1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8821a1ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8821A_1ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8821a1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8821a1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8821a1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8821a1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf5; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xa0; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xa0; /* MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8821a1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8821a1ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8821a1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8821a1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8821a1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8821a1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** CoexTable(%d) **********\n", type); - BTC_TRACE(trace_buf); - - switch (type) { - case 0: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, 0xffffff, 0x3); - break; - case 1: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 2: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 3: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 4: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 5: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaaaa5a5a, 0xffffff, 0x3); - break; - case 6: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); - break; - case 7: - halbtc8821a1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8821a1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) - h2c_parameter[0] |= BIT(0); /* function enable */ - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8821a1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8821a1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8821a1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - } - } - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8821a1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8821a1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8821a1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8821a1ant_sw_mechanism(IN struct btc_coexist *btcoexist, - IN boolean low_penalty_ra) -{ - halbtc8821a1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8821a1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u32 u32tmp = 0; - u8 h2c_parameter[2] = {0}; - - if (init_hwcfg) { - /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp |= BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - - /* 0x765 = 0x18 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x3); - - if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { - /* tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ - h2c_parameter[0] = 1; - h2c_parameter[1] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, 0x1); */ /*Main Ant to BT for IPS case 0x4c[23]=1 */ - } else { - /* tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ - h2c_parameter[0] = 0; - h2c_parameter[1] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, 0x0); */ /*Aux Ant to BT for IPS case 0x4c[23]=1 */ - } - } else if (wifi_off) { - /* 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL BT Vendor 0xac=0xf002 */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp &= ~BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - - /* 0x765 = 0x18 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x3); - } else { - /* 0x765 = 0x0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x0); - } - - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77); - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcb7, 0x30, 0x1); - else - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcb7, 0x30, 0x2); - break; - case BTC_ANT_PATH_BT: - btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77); - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcb7, 0x30, 0x2); - else - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcb7, 0x30, 0x1); - break; - default: - case BTC_ANT_PATH_PTA: - btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x66); - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcb7, 0x30, 0x1); - else - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcb7, 0x30, 0x2); - break; - } -} - -void halbtc8821a1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - u8 rssi_adjust_val = 0; - /* u32 fw_ver=0; */ - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - if (turn_on) { - switch (type) { - default: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1a, 0x1a, 0x0, 0x50); - break; - case 1: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x3a, 0x03, 0x10, 0x50); - rssi_adjust_val = 11; - break; - case 2: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x2b, 0x03, 0x10, 0x50); - rssi_adjust_val = 14; - break; - case 3: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1d, 0x1d, 0x0, 0x52); - break; - case 4: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x14, 0x0); - rssi_adjust_val = 17; - break; - case 5: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x15, 0x3, 0x11, 0x10); - break; - case 6: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x3, 0x11, 0x13); - break; - case 7: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13, - 0xc, 0x5, 0x0, 0x0); - break; - case 8: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - break; - case 9: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x21, 0x3, 0x10, 0x50); - rssi_adjust_val = 18; - break; - case 10: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0xa, 0x0, 0x40); - break; - case 11: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x15, 0x03, 0x10, 0x50); - rssi_adjust_val = 20; - break; - case 12: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x0a, 0x0a, 0x0, 0x50); - break; - case 13: - if (coex_sta->scan_ap_num <= 5) - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x40, 0x3, 0x10, 0x50); - else - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x12, 0x12, 0x0, 0x50); - break; - case 14: - if (coex_sta->scan_ap_num <= 5) - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, 0x50); - else - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x1e, 0x3, 0x10, 0x14); - break; - case 15: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13, - 0xa, 0x3, 0x8, 0x0); - break; - case 16: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x15, 0x3, 0x10, 0x0); - rssi_adjust_val = 18; - break; - case 18: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93, - 0x25, 0x3, 0x10, 0x0); - rssi_adjust_val = 14; - break; - case 20: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, 0x10); - break; - case 21: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x11); - break; - case 22: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, 0x10); - break; - case 23: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x18); - rssi_adjust_val = 22; - break; - case 24: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x3, 0x31, 0x18); - rssi_adjust_val = 22; - break; - case 25: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - rssi_adjust_val = 22; - break; - case 26: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0xa, 0x3, 0x31, 0x18); - rssi_adjust_val = 22; - break; - case 27: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x3, 0x31, 0x98); - rssi_adjust_val = 22; - break; - case 28: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x69, - 0x25, 0x3, 0x31, 0x0); - break; - case 29: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xab, - 0x1a, 0x1a, 0x1, 0x10); - break; - case 30: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, 0x10); - break; - case 31: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1a, 0x1a, 0, 0x58); - break; - case 32: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x3, 0x11, 0x11); - break; - case 33: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xa3, - 0x25, 0x3, 0x30, 0x90); - break; - case 34: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x53, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 35: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x63, - 0x1a, 0x1a, 0x0, 0x10); - break; - case 36: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xd3, - 0x12, 0x3, 0x14, 0x50); - break; - case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */ - /* here softap mode screen off will cost 70-80mA for phone */ - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x23, - 0x18, 0x00, 0x10, 0x24); - break; - case 41: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x15, 0x3, 0x11, 0x11); - break; - case 42: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x20, 0x3, 0x11, 0x11); - break; - case 43: - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, 0x11); - break; - } - } else { - /* disable PS tdma */ - switch (type) { - case 8: /* PTA Control */ - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - halbtc8821a1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, false, false); - break; - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - halbtc8821a1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, false, false); - break; - case 9: /* Software control, Antenna at WiFi side */ - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - halbtc8821a1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_WIFI, false, false); - break; - case 10: /* under 5G */ - halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x8, 0x0); - halbtc8821a1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, false, false); - break; - } - } - rssi_adjust_val = 0; - btcoexist->btc_set(btcoexist, - BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val); - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8821a1ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* sw all off */ - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - /* hw all off */ - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -boolean halbtc8821a1ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - common = true; - } else if (wifi_connected && - (BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - common = true; - } else if (!wifi_connected && - (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - common = true; - } else if (wifi_connected && - (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - common = true; - } else if (!wifi_connected && - (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE != - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } - - common = false; - } - - return common; -} - -void halbtc8821a1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8821a1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - break; - case BTC_PS_LPS_ON: - halbtc8821a1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8821a1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - break; - case BTC_PS_LPS_OFF: - halbtc8821a1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - break; - default: - break; - } -} - -void halbtc8821a1ant_coex_under_5g(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8821a1ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true); - - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 10); - - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 5); -} - -void halbtc8821a1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 9); -} - -void halbtc8821a1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - BTC_TRACE(trace_buf); - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 10) { - bt_disabled = true; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_wifi_only(btcoexist); - } - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - if (!bt_disabled) { - } else { - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - } - } -} - -/* ********************************************* - * - * Software Coex Mechanism start - * - * ********************************************* */ - -void halbtc8821a1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - /* halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); */ - halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, false, false); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} -/* SCO only or SCO+PAN(HS) */ -void halbtc8821a1ant_action_sco(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, true); -} - -void halbtc8821a1ant_action_hid(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, true); -} - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8821a1ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8821a1ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8821a1ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, false); -} - -/* PAN(HS) only */ -void halbtc8821a1ant_action_pan_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, false); -} - -/* PAN(EDR)+A2DP */ -void halbtc8821a1ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, false); -} - -void halbtc8821a1ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, true); -} - -/* HID+A2DP+PAN(EDR) */ -void halbtc8821a1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, true); -} - -void halbtc8821a1ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_sw_mechanism(btcoexist, true); -} - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8821a1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8821a1ant_action_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8821a1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, ap_enable = false, wifi_busy = false, - bt_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) { - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } - - /* sy modify */ - else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - /* SCO/HID/A2DP busy */ - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } - - /* sy modify */ - - else if ((bt_link_info->a2dp_exist) && - (bt_link_info->hid_exist)) { - /* A2DP+HID busy */ - halbtc8821a1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } - - - else if ((bt_link_info->pan_exist) || (wifi_busy)) { - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - } -} - -void halbtc8821a1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* tdma and coex table */ - - if (bt_link_info->sco_exist) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 41); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } else { /* HID */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 42); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8821a1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist, IN u8 wifi_status) -{ - u8 bt_rssi_state; - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - bt_rssi_state = halbtc8821a1ant_bt_rssi_state(2, 28, 0); - - if (bt_link_info->hid_only) { /* HID */ - halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, - wifi_status); - coex_dm->auto_tdma_adjust = false; - return; - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) { - /* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); */ - /* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = false; - } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - /* halbtc8821a1ant_tdma_duration_adjust_for_acl(btcoexist, wifi_status); */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } else { /* for low BT RSSI */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = false; - } - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - coex_dm->auto_tdma_adjust = false; - } else { /* for low BT RSSI */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - coex_dm->auto_tdma_adjust = false; - } - - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && - bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); - coex_dm->auto_tdma_adjust = false; - } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 43); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = false; - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - coex_dm->auto_tdma_adjust = false; - } -} - -void halbtc8821a1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - /* power save state */ - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8821a1ant_action_wifi_not_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - /* sy modify */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); */ - /* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); */ - - /* Bryant Add */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8821a1ant_action_wifi_not_connected_asso_auth( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) { - /* sy modify */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - } else if ((bt_link_info->a2dp_exist) || (bt_link_info->pan_exist)) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8821a1ant_action_wifi_connected_scan(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - /* sy modify */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 22); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 20); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN); - } else { - /* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); */ - /* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); */ - - /* Bryant Add */ - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8821a1ant_action_wifi_connected_specific_packet( - IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - /* tdma and coex table */ - /* sy modify */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } - - if ((bt_link_info->hid_exist) && (bt_link_info->a2dp_exist)) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } - - - else if (bt_link_info->pan_exist) { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - } -} - -void halbtc8821a1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - boolean scan = false, link = false, roam = false; - boolean under_4way = false, ap_enable = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - if (under_4way) { - halbtc8821a1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - if (scan) - halbtc8821a1ant_action_wifi_connected_scan(btcoexist); - else - halbtc8821a1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - /* power save state */ - if (!ap_enable && - BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status && - !btcoexist->bt_link_info.hid_only) { - if (!wifi_busy && btcoexist->bt_link_info.a2dp_only) /* A2DP */ - halbtc8821a1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - else - halbtc8821a1ant_power_save_state(btcoexist, - BTC_PS_LPS_ON, 0x50, 0x4); - } else - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - /* tdma and coex table */ - if (!wifi_busy) { - if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8821a1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE); - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - } - } else { - if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8821a1ant_action_wifi_connected_bt_acl_busy( - btcoexist, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY); - } else { - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); - halbtc8821a1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - } - } -} - -void halbtc8821a1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - - algorithm = halbtc8821a1ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - - if (halbtc8821a1ant_is_common_action(btcoexist)) { - - } else { - switch (coex_dm->cur_algorithm) { - case BT_8821A_1ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_sco(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_hid(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_a2dp(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_pan_edr(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_pan_hs(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_pan_edr_hid(btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8821A_1ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_hid_a2dp(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8821a1ant_coex_all_off(btcoexist); */ - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8821a1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean wifi_under_5g = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_action_bt_whck_test(btcoexist); - return; - } - - if ((BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8821a1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (!bt_link_info->sco_exist && !bt_link_info->hid_exist) - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - else { - if (wifi_connected) { - wifi_rssi_state = halbtc8821a1ant_wifi_rssi_state( - btcoexist, 1, 2, 30, 0); - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - /* halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 1, 1); */ - halbtc8821a1ant_limited_tx(btcoexist, - NORMAL_EXEC, 1, 1, 0, 1); - } else { - /* halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 1, 1); */ - halbtc8821a1ant_limited_tx(btcoexist, - NORMAL_EXEC, 1, 1, 0, 1); - } - } else - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, - 0, 0); - - } - - if (bt_link_info->sco_exist) { - bt_ctrl_agg_buf_size = true; - agg_buf_size = 0x3; - } else if (bt_link_info->hid_exist) { - bt_ctrl_agg_buf_size = true; - agg_buf_size = 0x5; - } else if (bt_link_info->a2dp_exist || bt_link_info->pan_exist) { - bt_ctrl_agg_buf_size = true; - agg_buf_size = 0x8; - } - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - - halbtc8821a1ant_run_sw_coexist_mechanism(btcoexist); - - /* low pelnaty ra in pcr ra */ - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8821a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8821a1ant_action_hs(btcoexist); - return; - } - - - if (!wifi_connected) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is non connected-idle !!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - if (scan) - halbtc8821a1ant_action_wifi_not_connected_scan( - btcoexist); - else - halbtc8821a1ant_action_wifi_not_connected_asso_auth( - btcoexist); - } else - halbtc8821a1ant_action_wifi_not_connected(btcoexist); - } else /* wifi LPS/Busy */ - halbtc8821a1ant_action_wifi_connected(btcoexist); -} - -void halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - /* sw all off */ - halbtc8821a1ant_sw_mechanism(btcoexist, false); - - /* halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */ - halbtc8821a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); -} - -void halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up, IN boolean wifi_only) -{ - u8 u8tmp = 0; - boolean wifi_under_5g = false; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - if (wifi_only) - return; - - if (back_up) { - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } - - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - /* Give bt_coex_supported_version the default value */ - coex_sta->bt_coex_supported_version = 0; - - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - /* Antenna config */ - if (wifi_under_5g) - halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, - false); - else - halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, true, - false); - - /* PTA parameter */ - halbtc8821a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - /* Enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, - 0xc); /* 0x76e[3] =1, WLAN_Act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); -} - -/* ************************************************************ - * work around function start with wa_halbtc8821a1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8821a1ant_ - * ************************************************************ */ -void ex_halbtc8821a1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8821a1ant_init_hw_config(btcoexist, true, wifi_only); -} - -void ex_halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; - - halbtc8821a1ant_init_coex_dm(btcoexist); - - halbtc8821a1ant_query_bt_info(btcoexist); -} - -void ex_halbtc8821a1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fw_ver = 0, bt_patch_ver = 0; - u32 bt_coex_ver = 0; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; - u32 phyver = 0; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", - "Ant PG Num/ Ant Mech/ Ant Pos:", - board_info->pg_ant_num, board_info->btdm_ant_num, - board_info->btdm_ant_pos); - CL_PRINTF(cli_buf); - - /* btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); */ - bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); - bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", - "CoexVer WL/ BT_Desired/ BT_Report", - glcoex_ver_date_8821a_1ant, glcoex_ver_8821a_1ant, - glcoex_ver_btdesired_8821a_1ant, - bt_coex_ver, - (bt_coex_ver == 0xff ? "Unknown" : - (bt_coex_ver >= glcoex_ver_btdesired_8821a_1ant ? - "Match" : "Mis-Match"))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", - "W_FW/ B_FW/ Phy/ Kt", - fw_ver, bt_patch_ver, phyver, - coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", - "SCO/HID/PAN/A2DP", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO); - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8821A_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8821a_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - if (!btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "SM[LowPenaltyRA]", - coex_dm->cur_low_penalty_ra); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms]============"); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - coex_dm->auto_tdma_adjust); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", - "IgnWlanAct", - coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", - "Latest error condition(should be 0)", - coex_dm->error_condition); - CL_PRINTF(cli_buf); - } - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "backup ARFR1/ARFR2/RL/AMaxTime", - coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2, - coex_dm->backup_retry_limit, - coex_dm->backup_ampdu_max_time); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434); - u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", - "0x430/0x434/0x42a/0x456", - u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc58); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x778/ 0xc58[29:25]", - u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x8db); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8db[6:5]", - ((u8tmp[0] & 0x60) >> 5)); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x975); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0xcb4[29:28]/0xcb4[7:0]/0x974[9:8]", - (u32tmp[0] & 0x30000000) >> 28, u32tmp[0] & 0xff, - u8tmp[0] & 0x3); - CL_PRINTF(cli_buf); - - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x64); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x40/0x4c[24:23]/0x64[0]", - u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u8tmp[1] & 0x1); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", - u32tmp[0] & 0xff); - CL_PRINTF(cli_buf); - - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_CCK); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); - CL_PRINTF(cli_buf); - - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 1) - halbtc8821a1ant_monitor_bt_ctr(btcoexist); -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8821a1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, - &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, - true); - /* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */ - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; - - halbtc8821a1ant_init_hw_config(btcoexist, false, false); - halbtc8821a1ant_init_coex_dm(btcoexist); - halbtc8821a1ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8821a1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8821a1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - if (BTC_SCAN_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - } - - if (coex_sta->bt_disabled) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - halbtc8821a1ant_query_bt_info(btcoexist); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8821a1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8821a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8821a1ant_action_hs(btcoexist); - return; - } - - if (BTC_SCAN_START == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8821a1ant_action_wifi_not_connected_scan( - btcoexist); - else /* wifi is connected */ - halbtc8821a1ant_action_wifi_connected_scan(btcoexist); - } else if (BTC_SCAN_FINISH == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8821a1ant_action_wifi_not_connected(btcoexist); - else - halbtc8821a1ant_action_wifi_connected(btcoexist); - } -} - -/* copy scan notify content to switch band notify */ -void ex_halbtc8821a1ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - if (BTC_SCAN_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, - 8); /* Force antenna setup for no scan result issue */ - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - } - - if (coex_sta->bt_disabled) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - halbtc8821a1ant_query_bt_info(btcoexist); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8821a1ant_action_wifi_multi_port(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8821a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8821a1ant_action_hs(btcoexist); - return; - } - - if (BTC_SCAN_START == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8821a1ant_action_wifi_not_connected_scan( - btcoexist); - else /* wifi is connected */ - halbtc8821a1ant_action_wifi_connected_scan(btcoexist); - } else if (BTC_SCAN_FINISH == type) { - if (!wifi_connected) /* non-connected scan */ - halbtc8821a1ant_action_wifi_not_connected(btcoexist); - else - halbtc8821a1ant_action_wifi_connected(btcoexist); - } -} -void ex_halbtc8821a1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - if (BTC_ASSOCIATE_START == type) { - coex_sta->wifi_is_high_pri_task = true; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8821a1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8821a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8821a1ant_action_hs(btcoexist); - return; - } - - if (BTC_ASSOCIATE_START == type) - halbtc8821a1ant_action_wifi_not_connected_asso_auth(btcoexist); - else if (BTC_ASSOCIATE_FINISH == type) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (!wifi_connected) /* non-connected scan */ - halbtc8821a1ant_action_wifi_not_connected(btcoexist); - else - halbtc8821a1ant_action_wifi_connected(btcoexist); - } -} - -void ex_halbtc8821a1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - /* h2c_parameter[0] = 0x1; */ - h2c_parameter[0] = 0x0; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); -} - -void ex_halbtc8821a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm || - coex_sta->bt_disabled) - return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - BTC_PACKET_ARP == type) { - coex_sta->wifi_is_high_pri_task = true; - - if (BTC_PACKET_ARP == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify\n"); - BTC_TRACE(trace_buf); - } - } else { - coex_sta->wifi_is_high_pri_task = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet [Type = %d] notify\n", type); - BTC_TRACE(trace_buf); - } - - coex_sta->specific_pkt_period_cnt = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - if (num_of_wifi_link >= 2) { - halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - bt_ctrl_agg_buf_size, agg_buf_size); - halbtc8821a1ant_action_wifi_multi_port(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8821a1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8821a1ant_action_hs(btcoexist); - return; - } - - if (BTC_PACKET_DHCP == type || - BTC_PACKET_EAPOL == type || - BTC_PACKET_ARP == type) { - if (BTC_PACKET_ARP == type) { - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ARP Packet Count = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - if (coex_dm->arp_cnt >= - 10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */ - return; - } - - halbtc8821a1ant_action_wifi_connected_specific_packet( - btcoexist); - } -} - -void ex_halbtc8821a1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean bt_busy = false; - boolean wifi_under_5g = false; - - - coex_sta->c2h_bt_info_req_sent = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8821A_1ANT_MAX) - rsp_source = BT_INFO_SRC_8821A_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - /* if 0xff, it means BT is under WHCK test */ - if (bt_info == 0xff) - coex_sta->bt_whck_test = true; - else - coex_sta->bt_whck_test = false; - - if (BT_INFO_SRC_8821A_1ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20) - coex_sta->c2h_bt_page = true; - else - coex_sta->c2h_bt_page = false; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] - & 0x40); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, - &coex_sta->bt_tx_rx_mask); - if (!coex_sta->bt_tx_rx_mask) { - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x3c, 0x15); - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if (coex_sta->bt_info_ext & BIT(1)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - if (wifi_connected) - ex_halbtc8821a1ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8821a1ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - if ((coex_sta->bt_info_ext & BIT(3)) && !wifi_under_5g) { - if (!btcoexist->manual_control && - !btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } else { - /* BT already NOT ignore Wlan active, do nothing here. */ - } -#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8821a1ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8821A_1ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8821A_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8821A_1ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8821A_1ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8821A_1ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8821A_1ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - } - - halbtc8821a1ant_update_bt_link_info(btcoexist); - - bt_info = bt_info & - 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */ - - if (!(bt_info & BT_INFO_8821A_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8821A_1ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8821A_1ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8821A_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8821A_1ANT_B_ACL_BUSY) { - if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status) - coex_dm->auto_tdma_adjust = false; - coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - halbtc8821a1ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8821a1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - boolean wifi_under_5g = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true); - /* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */ - - halbtc8821a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8821a1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8821a1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - boolean wifi_under_5g = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for 5G <===\n"); - BTC_TRACE(trace_buf); - halbtc8821a1ant_coex_under_5g(btcoexist); - return; - } - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, - true); - /* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */ - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = false; - halbtc8821a1ant_init_hw_config(btcoexist, false, false); - halbtc8821a1ant_init_coex_dm(btcoexist); - halbtc8821a1ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8821a1ant_periodical(IN struct btc_coexist *btcoexist) -{ - - if (((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) && - (!coex_sta->bt_disabled)) - coex_sta->bt_coex_supported_version = - btcoexist->btc_get_bt_coex_supported_version(btcoexist); - -#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 0) - halbtc8821a1ant_query_bt_info(btcoexist); - halbtc8821a1ant_monitor_bt_enable_disable(btcoexist); -#else - halbtc8821a1ant_monitor_bt_ctr(btcoexist); - halbtc8821a1ant_monitor_wifi_ctr(btcoexist); - halbtc8821a1ant_monitor_bt_enable_disable(btcoexist); - if (halbtc8821a1ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust) { - /* if(coex_sta->specific_pkt_period_cnt > 2) */ - /* { */ - halbtc8821a1ant_run_coexist_mechanism(btcoexist); - /* } */ - } - - coex_sta->specific_pkt_period_cnt++; -#endif -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ - - diff --git a/hal/btc/halbtc8821a1ant.h b/hal/btc/halbtc8821a1ant.h deleted file mode 100644 index c9c141c..0000000 --- a/hal/btc/halbtc8821a1ant.h +++ /dev/null @@ -1,228 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821A_SUPPORT == 1) - -/* ******************************************* - * The following is for 8821A 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8821A_1ANT 1 - -#define BT_INFO_8821A_1ANT_B_FTP BIT(7) -#define BT_INFO_8821A_1ANT_B_A2DP BIT(6) -#define BT_INFO_8821A_1ANT_B_HID BIT(5) -#define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8821A_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT 2 - -enum bt_info_src_8821a_1ant { - BT_INFO_SRC_8821A_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8821A_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8821A_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8821A_1ANT_MAX -}; - -enum bt_8821a_1ant_bt_status { - BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8821A_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8821A_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8821A_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8821A_1ANT_BT_STATUS_MAX -}; - -enum bt_8821a_1ant_wifi_status { - BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8821A_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8821a_1ant_coex_algo { - BT_8821A_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8821A_1ANT_COEX_ALGO_SCO = 0x1, - BT_8821A_1ANT_COEX_ALGO_HID = 0x2, - BT_8821A_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8821A_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8821A_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8821A_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8821A_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8821A_1ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8821a_1ant { - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u8 error_condition; -}; - -struct coex_sta_8821a_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; - - u32 bt_coex_supported_version; - u8 cut_version; - u8 bt_rssi; - u8 scan_ap_num; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8821A_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8821A_1ANT_MAX]; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - u8 bt_retry_cnt; - u8 bt_info_ext; - boolean bt_whck_test; /* Add for ASUS WHQL TEST that enable wifi test bt */ -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8821a1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8821a1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8821a1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a1ant_display_coex_info(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8821a1ant_power_on_setting(btcoexist) -#define ex_halbtc8821a1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8821a1ant_init_coex_dm(btcoexist) -#define ex_halbtc8821a1ant_ips_notify(btcoexist, type) -#define ex_halbtc8821a1ant_lps_notify(btcoexist, type) -#define ex_halbtc8821a1ant_scan_notify(btcoexist, type) -#define ex_halbtc8821a1ant_switchband_notify(btcoexist, type) -#define ex_halbtc8821a1ant_connect_notify(btcoexist, type) -#define ex_halbtc8821a1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8821a1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8821a1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8821a1ant_halt_notify(btcoexist) -#define ex_halbtc8821a1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8821a1ant_periodical(btcoexist) -#define ex_halbtc8821a1ant_display_coex_info(btcoexist) - -#endif - -#endif - diff --git a/hal/btc/halbtc8821a2ant.c b/hal/btc/halbtc8821a2ant.c deleted file mode 100644 index 3fcb757..0000000 --- a/hal/btc/halbtc8821a2ant.c +++ /dev/null @@ -1,4651 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for RTL8821A Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821A_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8821a_2ant glcoex_dm_8821a_2ant; -static struct coex_dm_8821a_2ant *coex_dm = &glcoex_dm_8821a_2ant; -static struct coex_sta_8821a_2ant glcoex_sta_8821a_2ant; -static struct coex_sta_8821a_2ant *coex_sta = &glcoex_sta_8821a_2ant; - -const char *const glbt_info_src_8821a_2ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8821a_2ant = 20160816; -u32 glcoex_ver_8821a_2ant = 0x5d; -u32 glcoex_ver_btdesired_8821a_2ant = 0x5c; - -/* modify 20140903v43 a2dpandhid tdmaonoff a2dp glitch _ tdma off 778=3(case1)->778=1(case0) - * and to improve tp while a2dphid case23->case25 , case123->case125 for asus spec - * and modify for asus bt WHQL test _ tdma off_ 778=3->1_ - * ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8821a2ant_ - * ************************************************************ */ -u8 halbtc8821a2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8821a2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8821a2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false; - - /* This function check if bt is disabled */ - - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - BTC_TRACE(trace_buf); - } else { - bt_disable_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt all counters=0, %d times!!\n", - bt_disable_cnt); - BTC_TRACE(trace_buf); - if (bt_disable_cnt >= 10) { - bt_disabled = true; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - BTC_TRACE(trace_buf); - } - } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - /* if (!bt_disabled) { - } else { - } */ - } -} - -void halbtc8821a2ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); -} - -void halbtc8821a2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - if ((coex_sta->low_priority_rx >= 950) && - (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) && - (!coex_sta->under_ips)) - bt_link_info->slave_role = true; - else - bt_link_info->slave_role = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx); - BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", - reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx); - BTC_TRACE(trace_buf); - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); -} - -void halbtc8821a2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ -#if 1 - - coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_VHT); - -#endif -} - -void halbtc8821a2ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - coex_sta->c2h_bt_info_req_sent = true; - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -boolean halbtc8821a2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 3, - 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - - if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) || - (BTC_RSSI_STATE_LOW == wifi_rssi_state)) - return true; - - } - - return false; -} - -void halbtc8821a2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; -} - -u8 halbtc8821a2ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8821A_2ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_HID_A2DP; - } - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(HS) ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(EDR) ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; - } - } - } - } - - return algorithm; -} - -void halbtc8821a2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - -void halbtc8821a2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN u8 dec_bt_pwr_lvl) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = dec_bt_pwr_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); -} - -void halbtc8821a2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 dec_bt_pwr_lvl) -{ - coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; - - if (!force_exec) { - if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) - return; - } - halbtc8821a2ant_set_fw_dec_bt_pwr(btcoexist, - coex_dm->cur_bt_dec_pwr_lvl); - - coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; -} - -void halbtc8821a2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8821a2ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8821a2ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8821a2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8821a2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - -void halbtc8821a2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist, - IN boolean rx_rf_shrink_on) -{ - if (rx_rf_shrink_on) { - /* Shrink RF Rx LPF corner */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Shrink RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, - 0xffffc); - } else { - /* Resume RF Rx LPF corner */ - /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */ - if (btcoexist->initilized) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Resume RF Rx LPF corner!!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, - 0xfffff, coex_dm->bt_rf_0x1e_backup); - } - } -} - -void halbtc8821a2ant_rf_shrink(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rx_rf_shrink_on) -{ - coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on; - - if (!force_exec) { - if (coex_dm->pre_rf_rx_lpf_shrink == - coex_dm->cur_rf_rx_lpf_shrink) - return; - } - halbtc8821a2ant_set_sw_rf_rx_lpf_corner(btcoexist, - coex_dm->cur_rf_rx_lpf_shrink); - - coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink; -} - -void halbtc8821a2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist - *btcoexist, IN boolean low_penalty_ra) -{ - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */ - - if (low_penalty_ra) { - h2c_parameter[1] |= BIT(0); - h2c_parameter[2] = - 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ - h2c_parameter[3] = 0xf3; /* MCS7 or OFDM54 */ - h2c_parameter[4] = 0xa0; /* MCS6 or OFDM48 */ - h2c_parameter[5] = 0xa0; /* MCS5 or OFDM36 */ - /* h2c_parameter[3] = 0xf7; */ /*MCS7 or OFDM54 */ - /* h2c_parameter[4] = 0xf8; */ /*MCS6 or OFDM48 */ - /* h2c_parameter[5] = 0xf9; /MCS5 or OFDM36 */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter); -} - -void halbtc8821a2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra) - return; - } - halbtc8821a2ant_set_sw_penalty_tx_rate_adaptive(btcoexist, - coex_dm->cur_low_penalty_ra); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; -} - -void halbtc8821a2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist, - IN u32 level) -{ - u8 val = (u8)level; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Write SwDacSwing = 0x%x\n", level); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val); -} - -void halbtc8821a2ant_set_sw_full_time_dac_swing(IN struct btc_coexist - *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl) -{ - if (sw_dac_swing_on) - halbtc8821a2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl); - else - halbtc8821a2ant_set_dac_swing_reg(btcoexist, 0x18); -} - - -void halbtc8821a2ant_dac_swing(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl) -{ - coex_dm->cur_dac_swing_on = dac_swing_on; - coex_dm->cur_dac_swing_lvl = dac_swing_lvl; - - if (!force_exec) { - if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) && - (coex_dm->pre_dac_swing_lvl == - coex_dm->cur_dac_swing_lvl)) - return; - } - delay_ms(30); - halbtc8821a2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on, - dac_swing_lvl); - - coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on; - coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl; -} - -void halbtc8821a2ant_set_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean adc_back_off) -{ - if (adc_back_off) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB BackOff Level Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1); - } -} - -void halbtc8821a2ant_adc_back_off(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean adc_back_off) -{ - coex_dm->cur_adc_back_off = adc_back_off; - - if (!force_exec) { - if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off) - return; - } - halbtc8821a2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off); - - coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off; -} - -void halbtc8821a2ant_set_agc_table(IN struct btc_coexist *btcoexist, - IN boolean agc_table_en) -{ - u8 rssi_adjust_val = 0; - - /* =================BB AGC Gain Table */ - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6e1A0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6d1B0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6c1C0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6b1D0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6a1E0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x691F0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x68200001); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001); - btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa4200001); - } - - - /* =================RF Gain */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x38fff); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x38ffe); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x380c3); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, - 0x28ce6); - } - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x1); - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table On!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x38fff); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x38ffe); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Agc Table Off!\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x380c3); - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff, - 0x28ce6); - } - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x0); - - /* set rssi_adjust_val for wifi module. */ - if (agc_table_en) - rssi_adjust_val = 8; - btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, - &rssi_adjust_val); -} - -void halbtc8821a2ant_agc_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean agc_table_en) -{ - coex_dm->cur_agc_table_en = agc_table_en; - - if (!force_exec) { - if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) - return; - } - halbtc8821a2ant_set_agc_table(btcoexist, agc_table_en); - - coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; -} - -void halbtc8821a2ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8821a2ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8821a2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8821a2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_sta->coex_table_type = type; - - switch (type) { - case 0: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, 0xffffff, 0x3); - break; - case 1: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5afa5afa, 0xffffff, 0x3); - break; - case 2: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3); - break; - case 3: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 4: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0xffffffff, 0xffffffff, 0xffffff, 0x3); - break; - case 5: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3); - break; - case 6: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3); - break; - case 7: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 8: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 9: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 10: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 11: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 12: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); - break; - case 13: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 14: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); - break; - case 15: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); - break; - case 16: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3); - break; - case 17: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0xfafafafa, 0xfafafafa, 0xffffff, 0x3); - break; - case 18: - halbtc8821a2ant_coex_table(btcoexist, force_exec, - 0x5555555f, 0x5ada5ada, 0xffffff, 0x3); - break; - default: - break; - } -} - -void halbtc8821a2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) - h2c_parameter[0] |= BIT(0); /* function enable */ - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8821a2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8821a2ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8821a2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8821a2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8821a2ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8821a2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - - h2c_parameter[0] = byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = byte5; - - coex_dm->ps_tdma_para[0] = byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8821a2ant_sw_mechanism1(IN struct btc_coexist *btcoexist, - IN boolean shrink_rx_lpf, IN boolean low_penalty_ra, - IN boolean limited_dig, IN boolean bt_lna_constrain) -{ - /* - u32 wifi_bw; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if(BTC_WIFI_BW_HT40 != wifi_bw) - { - if (shrink_rx_lpf) - shrink_rx_lpf = false; - } - */ - - /* halbtc8821a2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); */ - halbtc8821a2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - -void halbtc8821a2ant_sw_mechanism2(IN struct btc_coexist *btcoexist, - IN boolean agc_table_shift, IN boolean adc_back_off, - IN boolean sw_dac_swing, IN u32 dac_swing_lvl) -{ - /* halbtc8821a2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */ - /* halbtc8821a2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */ - halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, - dac_swing_lvl); -} - -void halbtc8821a2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u32 u32tmp = 0; - u8 h2c_parameter[2] = {0}; - - if (init_hwcfg) { - /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */ - u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp &= ~BIT(23); - u32tmp |= BIT(24); - btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp); - - btcoexist->btc_write_4byte(btcoexist, 0x974, 0x3ff); - /* btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77); */ - - if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) { - /* tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ - h2c_parameter[0] = 1; - h2c_parameter[1] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } else { - /* tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */ - h2c_parameter[0] = 0; - h2c_parameter[1] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, - h2c_parameter); - } - } - - /* ext switch setting */ - switch (ant_pos_type) { - case BTC_ANT_WIFI_AT_MAIN: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, 0x1); - break; - case BTC_ANT_WIFI_AT_AUX: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, 0x2); - break; - } -} - -void halbtc8821a2ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - u8 wifi_rssi_state1, bt_rssi_state; - - - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - if (!(BTC_RSSI_HIGH(wifi_rssi_state1) && - BTC_RSSI_HIGH(bt_rssi_state)) && turn_on) { - type = type + 100; /* for WiFi RSSI low or BT RSSI low */ - } - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) - return; - } - if (turn_on) { - switch (type) { - case 1: - default: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0xf1, 0x90); - break; - case 2: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d, 0x03, 0xf1, 0x90); - break; - case 3: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, 0x90); - break; - case 4: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x03, 0xf1, 0x90); - break; - case 5: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x3, 0x70, 0x90); - break; - case 6: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d, 0x3, 0x70, 0x90); - break; - case 7: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0x70, 0x90); - break; - case 8: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xa3, - 0x10, 0x3, 0x70, 0x90); - break; - case 9: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0xf1, 0x90); - break; - case 10: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d, 0x03, 0xf1, 0x90); - break; - case 11: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0xa, 0xa, 0xe1, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0xf1, 0x90); - break; - case 12: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0xf1, 0x90); - break; - case 13: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x3, 0x70, 0x90); - break; - case 14: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x2d, 0x3, 0x70, 0x90); - break; - case 15: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0xa, 0xa, 0x60, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1c, 0x3, 0x70, 0x90); - break; - case 16: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, 0x60, 0x90); */ - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x10, 0x3, 0x70, 0x90); - break; - case 17: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xa3, - 0x2f, 0x2f, 0x60, 0x90); - break; - case 18: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x5, 0x5, 0xe1, 0x90); - break; - case 19: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0xe1, 0x90); - break; - case 20: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x25, 0x25, 0x60, 0x90); - break; - case 21: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x03, 0x70, 0x90); - break; - case 23: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x1e, 0x03, 0xf0, 0x14); - break; - case 24: - case 124: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x3c, 0x03, 0x70, 0x50); - break; - /* case25/case125 : for lenovo bt pan tp degrade<30% while wifi downlink */ - case 25: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x14, 0x03, 0xf1, 0x90); - break; - case 26: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x30, 0x03, 0xf1, 0x90); - break; - case 27: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x23, 0x03, 0x70, 0x50); - break; - case 28: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1e, 0x03, 0x70, 0x50); - break; - case 71: - /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */ - - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0xf1, 0x90); - break; - case 101: - case 105: - case 171: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x3a, 0x03, 0x70, 0x50); - break; - case 102: - case 106: - case 110: - case 114: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x2d, 0x03, 0x70, 0x50); - break; - case 103: - case 107: - case 111: - case 115: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1c, 0x03, 0x70, 0x50); - break; - case 104: - case 108: - case 112: - case 116: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x10, 0x03, 0x70, 0x50); - break; - case 109: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0xf1, 0x90); - break; - case 113: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x3c, 0x03, 0x70, 0x90); - break; - case 121: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x15, 0x03, 0x70, 0x90); - break; - case 22: - case 122: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, - 0x35, 0x03, 0x71, 0x11); - break; - case 123: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x1c, 0x03, 0x70, 0x54); - break; - /* case25/case125 : for lenovo bt pan tp degrade<30% while wifi downlink */ - case 125: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x14, 0x03, 0x70, 0x50); - break; - case 126: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x30, 0x03, 0x70, 0x50); - break; - case 127: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3, - 0x28, 0x03, 0x70, 0x50); - break; - } - } else { - /* disable PS tdma */ - switch (type) { - case 0: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - case 1: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - default: - halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8821a2ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8821a2ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8821a2ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8821a2ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8821a2ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - - -void halbtc8821a2ant_coex_all_off(IN struct btc_coexist *btcoexist) -{ - /* fw all off */ - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8821a2ant_coex_under_5g(IN struct btc_coexist *btcoexist) -{ - halbtc8821a2ant_coex_all_off(btcoexist); - - halbtc8821a2ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true); -} - -void halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1); - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0); - - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); -} - -void halbtc8821a2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - boolean wifi_connected = false; - boolean low_pwr_disable = true; - boolean scan = false, link = false, roam = false; - - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - if (scan || link || roam) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link process + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 7); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - } else if (wifi_connected) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 7); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi no-link + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - } - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - -} - - -void halbtc8821a2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist) -{ - u8 u8tmpa, u8tmpb; - - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - - - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa, - u8tmpb); - BTC_TRACE(trace_buf); -} - -boolean halbtc8821a2ant_action_wifi_idle_process(IN struct btc_coexist - *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u8 ap_num = 0; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - /* wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); */ - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES - 20, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); - - /* define the office environment */ - if (BTC_RSSI_HIGH(wifi_rssi_state1) && - (coex_sta->hid_exist == true) && - (coex_sta->a2dp_exist == true)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi idle process for BT HID+A2DP exist!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - return true; - } - - /* */ - else if (coex_sta->pan_exist == true) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi idle process for BT PAN exist!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - return true; - } - - else { - halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x18); - return false; - } - - -} - - - -boolean halbtc8821a2ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - boolean bt_hs_on = false, low_pwr_disable = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non-connected idle!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, - false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, - 0x18); - - common = true; - } else { - if (BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, - false, false, 0x8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - halbtc8821a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 0xb); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, - false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else if (BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status) { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (bt_hs_on) - return false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, - false, false, 0x8); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - halbtc8821a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 1); - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 0xb); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - - common = true; - } else { - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - common = false; - /* common = halbtc8821a2ant_action_wifi_idle_process(btcoexist); */ - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - /* common = false; */ - common = halbtc8821a2ant_action_wifi_idle_process( - btcoexist); - } - } - } - - return common; -} -void halbtc8821a2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist, - IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval) -{ - static s32 up, dn, m, n, wait_count; - s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ - u8 retry_count = 0; - - if (!coex_dm->auto_tdma_adjust) { - coex_dm->auto_tdma_adjust = true; - { - if (sco_hid) { - if (tx_pause) { - if (max_interval == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } else if (max_interval == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (max_interval == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } else { - if (max_interval == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } else if (max_interval == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (max_interval == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } else { - if (tx_pause) { - if (max_interval == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (max_interval == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (max_interval == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } - } else { - if (max_interval == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (max_interval == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (max_interval == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } - } - } - } - /* ============ */ - up = 0; - dn = 0; - m = 1; - n = 3; - result = 0; - wait_count = 0; - } else { - /* acquire the BT TRx retry count from BT_Info byte2 */ - retry_count = coex_sta->bt_retry_cnt; - result = 0; - wait_count++; - - if (retry_count == - 0) { /* no retry in the last 2-second duration */ - up++; - dn--; - - if (dn <= 0) - dn = 0; - - if (up >= n) { /* if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration */ - wait_count = 0; - n = 3; - up = 0; - dn = 0; - result = 1; - } - } else if (retry_count <= - 3) { /* <=3 retry in the last 2-second duration */ - up--; - dn++; - - if (up <= 0) - up = 0; - - if (dn == 2) { /* if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration */ - if (wait_count <= 2) - m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ - else - m = 1; - - if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - } else { /* retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration */ - if (wait_count == 1) - m++; /* ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^ */ - else - m = 1; - - if (m >= 20) /* m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */ - m = 20; - - n = 3 * m; - up = 0; - dn = 0; - wait_count = 0; - result = -1; - } - - if (max_interval == 1) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 5); - coex_dm->ps_tdma_du_adj_type = 5; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 13); - coex_dm->ps_tdma_du_adj_type = 13; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 5); - coex_dm->ps_tdma_du_adj_type = - 5; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 13); - coex_dm->ps_tdma_du_adj_type = - 13; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 71); - coex_dm->ps_tdma_du_adj_type = 71; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 9); - coex_dm->ps_tdma_du_adj_type = 9; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - - if (result == -1) { - if (coex_dm->cur_ps_tdma == 71) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 1); - coex_dm->ps_tdma_du_adj_type = - 1; - } else if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 71); - coex_dm->ps_tdma_du_adj_type = - 71; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 9); - coex_dm->ps_tdma_du_adj_type = - 9; - } - } - } - } else if (max_interval == 2) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 6); - coex_dm->ps_tdma_du_adj_type = 6; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - coex_dm->ps_tdma_du_adj_type = 14; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 6); - coex_dm->ps_tdma_du_adj_type = - 6; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 14); - coex_dm->ps_tdma_du_adj_type = - 14; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 2); - coex_dm->ps_tdma_du_adj_type = 2; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 10); - coex_dm->ps_tdma_du_adj_type = 10; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 2); - coex_dm->ps_tdma_du_adj_type = - 2; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 10); - coex_dm->ps_tdma_du_adj_type = - 10; - } - } - } - } else if (max_interval == 3) { - if (tx_pause) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - coex_dm->ps_tdma_du_adj_type = 7; - } else if (coex_dm->cur_ps_tdma == 4) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 8); - coex_dm->ps_tdma_du_adj_type = 8; - } - if (coex_dm->cur_ps_tdma == 9) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 15); - coex_dm->ps_tdma_du_adj_type = 15; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 16); - coex_dm->ps_tdma_du_adj_type = 16; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 8); - coex_dm->ps_tdma_du_adj_type = - 8; - } else if (coex_dm->cur_ps_tdma == 13) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 16); - coex_dm->ps_tdma_du_adj_type = - 16; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 8) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 7); - coex_dm->ps_tdma_du_adj_type = - 7; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 15); - coex_dm->ps_tdma_du_adj_type = - 15; - } - } - } else { - if (coex_dm->cur_ps_tdma == 5) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 6) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 7) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 3); - coex_dm->ps_tdma_du_adj_type = 3; - } else if (coex_dm->cur_ps_tdma == 8) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 4); - coex_dm->ps_tdma_du_adj_type = 4; - } - if (coex_dm->cur_ps_tdma == 13) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 14) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 15) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 11); - coex_dm->ps_tdma_du_adj_type = 11; - } else if (coex_dm->cur_ps_tdma == 16) { - halbtc8821a2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 12); - coex_dm->ps_tdma_du_adj_type = 12; - } - if (result == -1) { - if (coex_dm->cur_ps_tdma == 1) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 4); - coex_dm->ps_tdma_du_adj_type = - 4; - } else if (coex_dm->cur_ps_tdma == 9) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 12); - coex_dm->ps_tdma_du_adj_type = - 12; - } - } else if (result == 1) { - if (coex_dm->cur_ps_tdma == 4) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 3) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 2) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 3); - coex_dm->ps_tdma_du_adj_type = - 3; - } else if (coex_dm->cur_ps_tdma == 12) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 11) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } else if (coex_dm->cur_ps_tdma == 10) { - halbtc8821a2ant_ps_tdma( - btcoexist, NORMAL_EXEC, - true, 11); - coex_dm->ps_tdma_du_adj_type = - 11; - } - } - } - } - } - - /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ - /* then we have to adjust it back to the previous record one. */ - if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) { - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n", - coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (!scan && !link && !roam) - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - coex_dm->ps_tdma_du_adj_type); - else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"); - BTC_TRACE(trace_buf); - } - } -} - -/* SCO only or SCO+PAN(HS) */ -void halbtc8821a2ant_action_sco(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 wifi_rssi_state, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for SCO quality at 11b/g mode */ - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - else { /* for SCO quality & wifi performance balance at 11n mode */ - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8821a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else { - if (bt_link_info->sco_only) - halbtc8821a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 17); - else - halbtc8821a2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 12); - } - } - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 0); /* for voice quality */ - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - true, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - true, 0x18); - } - } -} - - -void halbtc8821a2ant_action_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, bt_rssi_state; - u32 wifi_bw; - - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */ - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - else /* for HID quality & wifi performance balance at 11n mode */ - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 24); - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8821a2ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - u8 ap_num = 0; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num); - - /* define the office environment */ - if ((ap_num >= 10) && BTC_RSSI_HIGH(wifi_rssi_state1) && - BTC_RSSI_HIGH(bt_rssi_state)) { - /* dbg_print(" AP#>10(%d)\n", ap_num); */ - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x8); - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - /* halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - true, 0x6); - } - return; - - } - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, false, 1); */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - } else { - /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 1); */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - } - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8821a2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 2); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8821a2ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 10); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 26); - else - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 26); - - /* sw mechanism */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - - -/* PAN(HS) only */ -void halbtc8821a2ant_action_pan_hs(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* PAN(EDR)+A2DP */ -void halbtc8821a2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - else - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 12); - - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, - true, 3); - else - halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, - false, 3); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 13); - halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 3); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8821a2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 14); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (BTC_WIFI_BW_HT40 == wifi_bw) { - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 3); - /* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x780); - } else { - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, - 6); - /* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, - 0xfffff, 0x0); - } - halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, false, 2); - } else { - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - /* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x0); - halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 2); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -/* HID+A2DP+PAN(EDR) */ -void halbtc8821a2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 14); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, - true, 3); - else - halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, - false, 3); - } else - halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 3); - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8821a2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state; - u32 wifi_bw; - u8 ap_num = 0; - - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); - - wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15, - 0); - /* bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, 29, 0); */ - wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, - BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); - bt_rssi_state = halbtc8821a2ant_bt_rssi_state(3, - BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 37); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); - - halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x6); - - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_LEGACY == wifi_bw) { - if (BTC_RSSI_HIGH(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - } else { - /* only 802.11N mode we have to dec bt power to 4 degree */ - if (BTC_RSSI_HIGH(bt_rssi_state)) { - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &ap_num); - /* need to check ap Number of Not */ - if (ap_num < 10) - halbtc8821a2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, 4); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, - NORMAL_EXEC, 2); - } else if (BTC_RSSI_MEDIUM(bt_rssi_state)) - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - else - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - } - - if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 18); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, 0x0); - } else { - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 18); - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } - - if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) || - (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, false, 3); */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 28); - } else { - /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 3); */ - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 28); - } - - /* sw mechanism */ - if (BTC_WIFI_BW_HT40 == wifi_bw) { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, true, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } else { - if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) || - (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, true, false, - false, 0x18); - } else { - halbtc8821a2ant_sw_mechanism1(btcoexist, false, true, - false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, - false, 0x18); - } - } -} - -void halbtc8821a2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) -{ - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8821a2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); - halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* sw all off */ - halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false); - halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18); - - /* hw all off */ - /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ - halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); -} - -void halbtc8821a2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - boolean wifi_under_5g = false; - u8 algorithm = 0; - u32 num_of_wifi_link = 0; - u32 wifi_link_status = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean miracast_plus_bt = false; - boolean scan = false, link = false, roam = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_coex_under_5g(btcoexist); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_bt_whck_test(btcoexist); - return; - } - - algorithm = halbtc8821a2ant_action_algorithm(btcoexist); - if (coex_sta->c2h_bt_inquiry_page && - (BT_8821A_2ANT_COEX_ALGO_PANHS != algorithm)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_bt_inquiry(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - - if (scan || link || roam) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under Link Process !!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_wifi_link_process(btcoexist); - return; - } - - /* for P2P */ - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) - miracast_plus_bt = true; - else - miracast_plus_bt = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8821a2ant_action_wifi_multi_port(btcoexist); - - return; - } - - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - coex_dm->cur_algorithm = algorithm; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", - coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - - if (halbtc8821a2ant_is_common_action(btcoexist)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant common.\n"); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - } else { - if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n", - coex_dm->pre_algorithm, coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - coex_dm->auto_tdma_adjust = false; - } - switch (coex_dm->cur_algorithm) { - case BT_8821A_2ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_sco(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_hid(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_a2dp(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_pan_edr(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_pan_hs(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_pan_edr_hid(btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8821A_2ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_action_hid_a2dp(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_coex_all_off(btcoexist); - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - -void halbtc8821a2ant_wifi_off_hw_cfg(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[2] = {0}; - u32 fw_ver = 0; - - /* set wlan_act to low */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); - - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, - 0x780); /* WiFi goto standby while GNT_BT 0-->1 */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - if (fw_ver >= 0x180000) { - /* Use H2C to set GNT_BT to HIGH */ - h2c_parameter[0] = 1; - btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, h2c_parameter); - } else - btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18); -} - -void halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up) -{ - u8 u8tmp = 0; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - /* Give bt_coex_supported_version the default value */ - coex_sta->bt_coex_supported_version = 0; - - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - /* backup rf 0x1e value */ - coex_dm->bt_rf_0x1e_backup = - btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff); - - /* 0x790[5:0]=0x5 */ - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790); - u8tmp &= 0xc0; - u8tmp |= 0x5; - btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp); - - /* Antenna config */ - halbtc8821a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true, - false); - coex_sta->dis_ver_info_cnt = 0; - - /* PTA parameter */ - halbtc8821a2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - /* Enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, - 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); -} - -/* ************************************************************ - * work around function start with wa_halbtc8821a2ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8821a2ant_ - * ************************************************************ */ -void ex_halbtc8821a2ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - -} - -void ex_halbtc8821a2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - if (btcoexist->chip_interface == BTC_INTF_USB) { - /* fixed at S0 for USB interface */ - u8tmp |= 0x1; /* antenna inverse */ - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - } else { - /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ - if (board_info->single_ant_path == 0) { - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - u8tmp |= 0x1; /* antenna inverse */ - } - - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384, - u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, - u8tmp); - } -} - -void ex_halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8821a2ant_init_hw_config(btcoexist, true); -} - -void ex_halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821a2ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8821a2ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u32 u32tmp[4]; - u32 fw_ver = 0, bt_patch_ver = 0; - u32 bt_coex_ver = 0; - u32 phyver = 0; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "Ant PG number/ Ant mechanism:", - board_info->pg_ant_num, board_info->btdm_ant_num); - CL_PRINTF(cli_buf); - - /* btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); */ - bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); - bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", - "CoexVer WL/ BT_Desired/ BT_Report", - glcoex_ver_date_8821a_2ant, glcoex_ver_8821a_2ant, - glcoex_ver_btdesired_8821a_2ant, - bt_coex_ver, - (bt_coex_ver == 0xff ? "Unknown" : - (bt_coex_ver >= glcoex_ver_btdesired_8821a_2ant ? - "Match" : "Mis-Match"))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", - "W_FW/ B_FW/ Phy/ Kt", - fw_ver, bt_patch_ver, phyver, - coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "Wifi channel informed to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %ddBm/ %d] ", - "BT [status/ rssi/ retryCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") - : ((BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", - "SCO/HID/PAN/A2DP", - bt_link_info->sco_exist, bt_link_info->hid_exist, - bt_link_info->pan_exist, bt_link_info->a2dp_exist); - CL_PRINTF(cli_buf); - - { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Role", - (bt_link_info->slave_role) ? "Slave" : "Master"); - CL_PRINTF(cli_buf); - } - - bt_info_ext = coex_sta->bt_info_ext; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", - "BT Info A2DP rate", - (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate"); - CL_PRINTF(cli_buf); - - for (i = 0; i < BT_INFO_SRC_8821A_2ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8821a_2ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - /* Sw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Sw mechanism]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", - "SM1[ShRf/ LpRA/ LimDig]", - coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, - coex_dm->limited_dig); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", - "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", - coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, - coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl); - CL_PRINTF(cli_buf); - - /* Fw mechanism */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Fw mechanism]============"); - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", - "PS TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - coex_dm->auto_tdma_adjust); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", - "Coex Table Type", - coex_sta->coex_table_type); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", - "DecBtPwr/ IgnWlanAct", - coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act); - CL_PRINTF(cli_buf); - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", - "RF-A, 0x1e initVal", - coex_dm->bt_rf_0x1e_backup); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xc5b); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x880); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x778/0x880[29:25]/0xc58[29:25]", - u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25, - ((u8tmp[1] & 0x3e) >> 1)); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x764); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x76e); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x764/ 0x765/ 0x76e", - (u32tmp[0] & 0xff), (u32tmp[0] & 0xff00) >> 8, u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xcb4[7:0](ctrl)/ 0xcb4[29:28](val)", - u32tmp[0] & 0xff, ((u32tmp[0] & 0x30000000) >> 28)); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x974); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", - "0x40/ 0x4c[24:23]/ 0x974", - u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u32tmp[1]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0x550(bcn ctrl)/0x522", - u32tmp[0], u8tmp[0]); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "0xc50(dig)/0x49c(null-drop)", - u32tmp[0] & 0xff, u8tmp[0]); - CL_PRINTF(cli_buf); - - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_CCK); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11n-agg", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11n-agg", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", - u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x770(high-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "0x774(low-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx); - CL_PRINTF(cli_buf); -#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 1) - /* halbtc8821a2ant_monitor_bt_ctr(btcoexist); */ -#endif - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8821a2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - halbtc8821a2ant_wifi_off_hw_cfg(btcoexist); - halbtc8821a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - halbtc8821a2ant_coex_all_off(btcoexist); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; - halbtc8821a2ant_init_hw_config(btcoexist, false); - halbtc8821a2ant_init_coex_dm(btcoexist); - halbtc8821a2ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8821a2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - } -} - -void ex_halbtc8821a2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 u8tmpa, u8tmpb; - - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - if (BTC_SCAN_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_SCAN_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa, - u8tmpb); - BTC_TRACE(trace_buf); -} - -/* copy scan notify content to switch band notify */ -void ex_halbtc8821a2ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 u8tmpa, u8tmpb; - - u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765); - u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e); - - if (BTC_SCAN_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_SCAN_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify\n"); - BTC_TRACE(trace_buf); - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa, - u8tmpb); - BTC_TRACE(trace_buf); -} - -void ex_halbtc8821a2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (BTC_ASSOCIATE_START == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify\n"); - BTC_TRACE(trace_buf); - } else if (BTC_ASSOCIATE_FINISH == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8821a2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - u8 ap_num = 0; - - if (BTC_MEDIA_CONNECT == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - } - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = 0x1; - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else { - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &ap_num); - if (ap_num < 10) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); -} - -void ex_halbtc8821a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (type == BTC_PACKET_DHCP) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], DHCP Packet notify\n"); - BTC_TRACE(trace_buf); - } -} - -void ex_halbtc8821a2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 bt_info = 0; - u8 i, rsp_source = 0; - boolean bt_busy = false, limited_dig = false; - boolean wifi_connected = false, wifi_under_5g = false; - - coex_sta->c2h_bt_info_req_sent = false; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8821A_2ANT_MAX) - rsp_source = BT_INFO_SRC_8821A_2ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - if (i == 1) - bt_info = tmp_buf[i]; - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n"); - BTC_TRACE(trace_buf); - return; - } - - /* if 0xff, it means BT is under WHCK test */ - if (bt_info == 0xff) - coex_sta->bt_whck_test = true; - else - coex_sta->bt_whck_test = false; - - if (BT_INFO_SRC_8821A_2ANT_WIFI_FW != rsp_source) { - coex_sta->bt_retry_cnt = /* [3:0] */ - coex_sta->bt_info_c2h[rsp_source][2] & 0xf; - - coex_sta->bt_rssi = - coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - - coex_sta->bt_info_ext = - coex_sta->bt_info_c2h[rsp_source][4]; - - coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2] - & 0x40); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK, - &coex_sta->bt_tx_rx_mask); - if (coex_sta->bt_tx_rx_mask) { - /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, - 0x3c, 0x01); - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - if (wifi_connected) - ex_halbtc8821a2ant_media_status_notify( - btcoexist, BTC_MEDIA_CONNECT); - else - ex_halbtc8821a2ant_media_status_notify( - btcoexist, BTC_MEDIA_DISCONNECT); - } - - - if (!btcoexist->manual_control && !wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info = 0x%x!!\n", - coex_sta->bt_info_ext); - BTC_TRACE(trace_buf); - if ((coex_sta->bt_info_ext & BIT(3))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3=1, wifi_connected=%d\n", - wifi_connected); - BTC_TRACE(trace_buf); - if (wifi_connected) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_ignore_wlan_act( - btcoexist, FORCE_EXEC, false); - } - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3=0, wifi_connected=%d\n", - wifi_connected); - BTC_TRACE(trace_buf); - /* BT already NOT ignore Wlan active, do nothing here. */ - if (!wifi_connected) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_ignore_wlan_act( - btcoexist, FORCE_EXEC, true); - } - } - } - -#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 0) - if ((coex_sta->bt_info_ext & BIT(4))) { - /* BT auto report already enabled, do nothing */ - } else - halbtc8821a2ant_bt_auto_report(btcoexist, FORCE_EXEC, - true); -#endif - } - - /* check BIT2 first ==> check if bt is under inquiry or page scan */ - if (bt_info & BT_INFO_8821A_2ANT_B_INQ_PAGE) - coex_sta->c2h_bt_inquiry_page = true; - else - coex_sta->c2h_bt_inquiry_page = false; - - /* set link exist status */ - if (!(bt_info & BT_INFO_8821A_2ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (bt_info & BT_INFO_8821A_2ANT_B_FTP) - coex_sta->pan_exist = true; - else - coex_sta->pan_exist = false; - if (bt_info & BT_INFO_8821A_2ANT_B_A2DP) - coex_sta->a2dp_exist = true; - else - coex_sta->a2dp_exist = false; - if (bt_info & BT_INFO_8821A_2ANT_B_HID) - coex_sta->hid_exist = true; - else - coex_sta->hid_exist = false; - if (bt_info & BT_INFO_8821A_2ANT_B_SCO_ESCO) - coex_sta->sco_exist = true; - else - coex_sta->sco_exist = false; - - if ((coex_sta->hid_exist == false) && - (coex_sta->c2h_bt_inquiry_page == false) && - (coex_sta->sco_exist == false)) { - if (coex_sta->high_priority_tx + - coex_sta->high_priority_rx >= 160) - coex_sta->hid_exist = true; - } - } - - halbtc8821a2ant_update_bt_link_info(btcoexist); - - if (!(bt_info & BT_INFO_8821A_2ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info == - BT_INFO_8821A_2ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - BTC_TRACE(trace_buf); - } else if ((bt_info & BT_INFO_8821A_2ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8821A_2ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - BTC_TRACE(trace_buf); - } else if (bt_info & BT_INFO_8821A_2ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - BTC_TRACE(trace_buf); - } - - if ((BT_8821A_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8821A_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) { - bt_busy = true; - limited_dig = true; - } else { - bt_busy = false; - limited_dig = false; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - coex_dm->limited_dig = limited_dig; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig); - - halbtc8821a2ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8821a2ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821a2ant_wifi_off_hw_cfg(btcoexist); - /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */ - /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); */ /*BT goto standby while GNT_BT 1-->0 */ - halbtc8821a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8821a2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); -} - -void ex_halbtc8821a2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_WIFI_PNP_SLEEP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_init_hw_config(btcoexist, false); - halbtc8821a2ant_init_coex_dm(btcoexist); - halbtc8821a2ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8821a2ant_periodical(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ==========================Periodical===========================\n"); - BTC_TRACE(trace_buf); - - if (coex_sta->dis_ver_info_cnt <= 5) { - coex_sta->dis_ver_info_cnt += 1; - if (coex_sta->dis_ver_info_cnt == 3) { - /* Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Set GNT_BT control by PTA\n"); - BTC_TRACE(trace_buf); - halbtc8821a2ant_set_ant_path(btcoexist, - BTC_ANT_WIFI_AT_MAIN, false, false); - } - } - - if (((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) && - (!coex_sta->bt_disabled)) - coex_sta->bt_coex_supported_version = - btcoexist->btc_get_bt_coex_supported_version(btcoexist); - - -#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 0) - halbtc8821a2ant_query_bt_info(btcoexist); - halbtc8821a2ant_monitor_bt_enable_disable(btcoexist); -#else - halbtc8821a2ant_monitor_bt_ctr(btcoexist); - halbtc8821a2ant_monitor_wifi_ctr(btcoexist); - halbtc8821a2ant_monitor_bt_enable_disable(btcoexist); - - if (halbtc8821a2ant_is_wifi_status_changed(btcoexist) || - coex_dm->auto_tdma_adjust) - halbtc8821a2ant_run_coexist_mechanism(btcoexist); -#endif -} - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ diff --git a/hal/btc/halbtc8821a2ant.h b/hal/btc/halbtc8821a2ant.h deleted file mode 100644 index d76f566..0000000 --- a/hal/btc/halbtc8821a2ant.h +++ /dev/null @@ -1,225 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821A_SUPPORT == 1) - -/* ******************************************* - * The following is for 8821A 2Ant BT Co-exist definition - * ******************************************* */ -#define BT_AUTO_REPORT_ONLY_8821A_2ANT 1 - - -#define BT_INFO_8821A_2ANT_B_FTP BIT(7) -#define BT_INFO_8821A_2ANT_B_A2DP BIT(6) -#define BT_INFO_8821A_2ANT_B_HID BIT(5) -#define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8821A_2ANT_B_CONNECTION BIT(0) - -#define BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT 2 - - -#define BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 /* WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */ -#define BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES 46 /* BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */ - -enum bt_info_src_8821a_2ant { - BT_INFO_SRC_8821A_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8821A_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8821A_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8821A_2ANT_MAX -}; - -enum bt_8821a_2ant_bt_status { - BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8821A_2ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8821A_2ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8821A_2ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8821A_2ANT_BT_STATUS_MAX -}; - -enum bt_8821a_2ant_coex_algo { - BT_8821A_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8821A_2ANT_COEX_ALGO_SCO = 0x1, - BT_8821A_2ANT_COEX_ALGO_HID = 0x2, - BT_8821A_2ANT_COEX_ALGO_A2DP = 0x3, - BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8821A_2ANT_COEX_ALGO_PANEDR = 0x5, - BT_8821A_2ANT_COEX_ALGO_PANHS = 0x6, - BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8821A_2ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8821A_2ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8821A_2ANT_COEX_ALGO_MAX = 0xb, -}; - -struct coex_dm_8821a_2ant { - /* fw mechanism */ - u8 pre_bt_dec_pwr_lvl; - u8 cur_bt_dec_pwr_lvl; - u8 pre_fw_dac_swing_lvl; - u8 cur_fw_dac_swing_lvl; - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean reset_tdma_adjust; - boolean auto_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - - /* sw mechanism */ - boolean pre_rf_rx_lpf_shrink; - boolean cur_rf_rx_lpf_shrink; - u32 bt_rf_0x1e_backup; - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - boolean pre_dac_swing_on; - u32 pre_dac_swing_lvl; - boolean cur_dac_swing_on; - u32 cur_dac_swing_lvl; - boolean pre_adc_back_off; - boolean cur_adc_back_off; - boolean pre_agc_table_en; - boolean cur_agc_table_en; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - boolean need_recover0x948; - u32 backup0x948; - - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; -}; - -struct coex_sta_8821a_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - u8 bt_rssi; - boolean bt_tx_rx_mask; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - boolean c2h_bt_info_req_sent; - u8 bt_info_c2h[BT_INFO_SRC_8821A_2ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8821A_2ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - u8 bt_retry_cnt; - u8 bt_info_ext; - u8 scan_ap_num; - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; - - u32 bt_coex_supported_version; - u8 cut_version; - u8 coex_table_type; - boolean force_lps_on; - - u8 dis_ver_info_cnt; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8821a2ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a2ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821a2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8821a2ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8821a2ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8821a2ant_display_coex_info(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8821a2ant_power_on_setting(btcoexist) -#define ex_halbtc8821a2ant_pre_load_firmware(btcoexist) -#define ex_halbtc8821a2ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8821a2ant_init_coex_dm(btcoexist) -#define ex_halbtc8821a2ant_ips_notify(btcoexist, type) -#define ex_halbtc8821a2ant_lps_notify(btcoexist, type) -#define ex_halbtc8821a2ant_scan_notify(btcoexist, type) -#define ex_halbtc8821a2ant_switchband_notify(btcoexist, type) -#define ex_halbtc8821a2ant_connect_notify(btcoexist, type) -#define ex_halbtc8821a2ant_media_status_notify(btcoexist, type) -#define ex_halbtc8821a2ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8821a2ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8821a2ant_halt_notify(btcoexist) -#define ex_halbtc8821a2ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8821a2ant_periodical(btcoexist) -#define ex_halbtc8821a2ant_display_coex_info(btcoexist) -#endif - -#endif - diff --git a/hal/btc/halbtc8821c1ant.c b/hal/btc/halbtc8821c1ant.c deleted file mode 100644 index f9f2081..0000000 --- a/hal/btc/halbtc8821c1ant.c +++ /dev/null @@ -1,5357 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for RTL8821C Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821C_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8821c_1ant glcoex_dm_8821c_1ant; -static struct coex_dm_8821c_1ant *coex_dm = &glcoex_dm_8821c_1ant; -static struct coex_sta_8821c_1ant glcoex_sta_8821c_1ant; -static struct coex_sta_8821c_1ant *coex_sta = &glcoex_sta_8821c_1ant; -static struct psdscan_sta_8821c_1ant gl_psd_scan_8821c_1ant; -static struct psdscan_sta_8821c_1ant *psd_scan = &gl_psd_scan_8821c_1ant; -static struct rfe_type_8821c_1ant gl_rfe_type_8821c_1ant; -static struct rfe_type_8821c_1ant *rfe_type = &gl_rfe_type_8821c_1ant; - - -const char *const glbt_info_src_8821c_1ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8821c_1ant = 20161107; -u32 glcoex_ver_8821c_1ant = 0x0a; -u32 glcoex_ver_btdesired_8821c_1ant = 0x0a; - - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8821c1ant_ - * ************************************************************ */ -u8 halbtc8821c1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; - } - - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8821c1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; - } - - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8821c1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -void halbtc8821c1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = false; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8821c1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -void halbtc8821c1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -void halbtc8821c1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8821c1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8821c1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8821c1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8821c1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8821c1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8821c1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - -void halbtc8821c1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - -} - -void halbtc8821c1ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - if (coex_sta->bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No query BT info because BT is disabled!\n"); - BTC_TRACE(trace_buf); - return; - } - - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WL query BT info!!\n"); - BTC_TRACE(trace_buf); -} - -void halbtc8821c1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, - cnt_autoslot_hang = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ - /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", - reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); - - BTC_TRACE(trace_buf); - - if (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - - if (coex_sta->high_priority_rx >= 15) { - if (cnt_overhead < 3) - cnt_overhead++; - - if (cnt_overhead == 3) - coex_sta->is_hiPri_rx_overhead = true; - - } else { - if (cnt_overhead > 0) - cnt_overhead--; - - if (cnt_overhead == 0) - coex_sta->is_hiPri_rx_overhead = false; - } - } - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - if ((coex_sta->low_priority_tx > 1150) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - if ((coex_sta->low_priority_rx >= 1150) && - (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) - && (!coex_sta->under_ips) - && (!coex_sta->c2h_bt_inquiry_page) - && ((bt_link_info->a2dp_exist) || (bt_link_info->pan_exist))) { - if (cnt_slave >= 2) { - bt_link_info->slave_role = true; - cnt_slave = 2; - } else - cnt_slave++; - } else { - if (cnt_slave == 0) { - bt_link_info->slave_role = false; - cnt_slave = 0; - } else - cnt_slave--; - } - - if (coex_sta->is_tdma_btautoslot) { - if ((coex_sta->low_priority_tx >= 1300) && - (coex_sta->low_priority_rx <= 150)) { - if (cnt_autoslot_hang >= 2) { - coex_sta->is_tdma_btautoslot_hang = true; - cnt_autoslot_hang = 2; - } else - cnt_autoslot_hang++; - } else { - if (cnt_autoslot_hang == 0) { - coex_sta->is_tdma_btautoslot_hang = false; - cnt_autoslot_hang = 0; - } else - cnt_autoslot_hang--; - } - } - - if (!coex_sta->bt_disabled) { - - if ((coex_sta->high_priority_tx == 0) && - (coex_sta->high_priority_rx == 0) && - (coex_sta->low_priority_tx == 0) && - (coex_sta->low_priority_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8821c1ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; - } - } - } - -} - - - -void halbtc8821c1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ -#if 1 - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false, - wifi_scan = false; - boolean bt_idle = false, wl_idle = false; - static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, - wl_noisy_count1 = 3, wl_noisy_count2 = 0; - u32 total_cnt, reg_val1, reg_val2, cck_cnt; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - - coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_VHT); - - cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; - - if (cck_cnt > 250) { - if (wl_noisy_count2 < 3) - wl_noisy_count2++; - - if (wl_noisy_count2 == 3) { - wl_noisy_count0 = 0; - wl_noisy_count1 = 0; - } - - } else if (cck_cnt < 50) { - if (wl_noisy_count0 < 3) - wl_noisy_count0++; - - if (wl_noisy_count0 == 3) { - wl_noisy_count1 = 0; - wl_noisy_count2 = 0; - } - - } else { - if (wl_noisy_count1 < 3) - wl_noisy_count1++; - - if (wl_noisy_count1 == 3) { - wl_noisy_count0 = 0; - wl_noisy_count2 = 0; - } - } - - if (wl_noisy_count2 == 3) - coex_sta->wl_noisy_level = 2; - else if (wl_noisy_count1 == 3) - coex_sta->wl_noisy_level = 1; - else - coex_sta->wl_noisy_level = 0; - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht; - - if ((coex_dm->bt_status == BT_8821C_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY) - || - (coex_dm->bt_status == BT_8821C_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 3) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = true; - - coex_sta->pre_ccklock = coex_sta->cck_lock; - -#endif -} - -void halbtc8821c1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - boolean bt_busy = false; - - - coex_sta->num_of_profile = 0; - - /* set link exist status */ - if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_FTP) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = false; - - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_A2DP) { - coex_sta->a2dp_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = false; - - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_HID) { - coex_sta->hid_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = false; - - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) { - coex_sta->sco_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = false; - - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->acl_busy = coex_sta->acl_busy; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; - - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_INQ_PAGE) { - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_INQ_PAGE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); - } else if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - } else if (coex_sta->bt_info == BT_INFO_8821C_1ANT_B_CONNECTION) { - /* connection exists but no busy */ - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - } else if (((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) || - (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_BUSY)) && - (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_ACL_BUSY)) { - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); - } else if ((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) || - (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - } else if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - } else { - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - } - - BTC_TRACE(trace_buf); - - if ((BT_8821C_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); -} - -void halbtc8821c1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = - 0x1; /* enable BT AFH skip WL channel for 8821c because BT Rx LO interference */ - /* h2c_parameter[0] = 0x0; */ - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); - -} - -u8 halbtc8821c1ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8821C_1ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } - - return algorithm; -} - -void halbtc8821c1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8821c1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8821c1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - - -void halbtc8821c1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - -#if 1 - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == - coex_dm->cur_low_penalty_ra) - return; - } - - if (low_penalty_ra) - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15); - else - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; - -#endif - -} - -void halbtc8821c1ant_write_score_board( - IN struct btc_coexist *btcoexist, - IN u16 bitpos, - IN boolean state -) -{ - - static u16 originalval = 0x8002, preval = 0x0; - - if (state) - originalval = originalval | bitpos; - else - originalval = originalval & (~bitpos); - - if (originalval != preval) { - - preval = originalval; - btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c1ant_write_score_board: return for nochange\n"); - BTC_TRACE(trace_buf); - } -} - -void halbtc8821c1ant_read_score_board( - IN struct btc_coexist *btcoexist, - IN u16 *score_board_val -) -{ - - *score_board_val = (btcoexist->btc_read_2byte(btcoexist, - 0xaa)) & 0x7fff; -} - -void halbtc8821c1ant_post_state_to_bt( - IN struct btc_coexist *btcoexist, - IN u16 type, - IN boolean state -) -{ - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c1ant_post_state_to_bt: type = %d, state =%d\n", - type, state); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_write_score_board(btcoexist, (u16) type, state); -} - -boolean halbtc8821c1ant_is_wifibt_status_changed(IN struct btc_coexist - *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false, pre_bt_off = false, - pre_bt_slave = false; - static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (coex_sta->bt_disabled != pre_bt_off) { - pre_bt_off = coex_sta->bt_disabled; - - if (coex_sta->bt_disabled) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - - BTC_TRACE(trace_buf); - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - coex_sta->bt_ble_scan_type = 0; - coex_sta->bt_ble_scan_para[0] = 0; - coex_sta->bt_ble_scan_para[1] = 0; - coex_sta->bt_ble_scan_para[2] = 0; - coex_sta->bt_reg_vendor_ac = 0xffff; - coex_sta->bt_reg_vendor_ae = 0xffff; - return true; - } - - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - - if (wifi_busy) - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, true); - else - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, false); - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { - pre_wl_noisy_level = coex_sta->wl_noisy_level; - return true; - } - } - - if (!coex_sta->bt_disabled) { - if (coex_sta->hid_busy_num != pre_hid_busy_num) { - pre_hid_busy_num = coex_sta->hid_busy_num; - return true; - } - } - - if (bt_link_info->slave_role != pre_bt_slave) { - pre_bt_slave = bt_link_info->slave_role; - return true; - } - - return false; -} - - -void halbtc8821c1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false, wifi_under_5g = false; - u16 u16tmp; - - /* This function check if bt is disabled */ -#if 0 - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - - -#else - - /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */ - halbtc8821c1ant_read_score_board(btcoexist, &u16tmp); - - bt_active = u16tmp & BIT(1); - - -#endif - - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } else { - - bt_disable_cnt++; - if (bt_disable_cnt >= 10) { - bt_disabled = true; - bt_disable_cnt = 10; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if ((wifi_under_5g) || (bt_disabled)) - halbtc8821c1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); - else - halbtc8821c1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true); - - - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - } - -} - -void halbtc8821c1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, - boolean isenable) -{ -#if BT_8821C_1ANT_COEX_DBG - static u8 bitVal[5] = {0, 0, 0, 0, 0}; - static boolean state = false; - /* - if (state ==isenable) - return; - else - state = isenable; - */ - if (isenable) { - - /* enable GNT_WL, GNT_BT to GPIO for debug */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); - - /* store original value */ - bitVal[0] = (btcoexist->btc_read_1byte(btcoexist, - 0x66) & BIT(4)) >> 4; /*0x66[4] */ - bitVal[1] = (btcoexist->btc_read_1byte(btcoexist, - 0x67) & BIT(0)); /*0x66[8] */ - bitVal[2] = (btcoexist->btc_read_1byte(btcoexist, - 0x42) & BIT(3)) >> 3; /*0x40[19] */ - bitVal[3] = (btcoexist->btc_read_1byte(btcoexist, - 0x65) & BIT(7)) >> 7; /*0x64[15] */ - bitVal[4] = (btcoexist->btc_read_1byte(btcoexist, - 0x72) & BIT(2)) >> 2; /*0x70[18] */ - - /* switch GPIO Mux */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), - 0x0); /*0x66[4] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), - 0x0); /*0x66[8] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), - 0x0); /*0x40[19] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), - 0x0); /*0x64[15] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), - 0x0); /*0x70[18] = 0 */ - - - } else { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); - - /* Restore original value */ - /* switch GPIO Mux */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), - bitVal[0]); /*0x66[4] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), - bitVal[1]); /*0x66[8] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), - bitVal[2]); /*0x40[19] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), - bitVal[3]); /*0x64[15] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), - bitVal[4]); /*0x70[18] = 0 */ - } - -#endif -} - -u32 halbtc8821c1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, - IN u16 reg_addr) -{ - u32 j = 0; - - - /* wait for ready bit before access 0x1700 */ - btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr); - - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x1703)&BIT(5)) == 0) && - (j < BT_8821C_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - return btcoexist->btc_read_4byte(btcoexist, - 0x1708); /* get read data */ - -} - -void halbtc8821c1ant_ltecoex_indirect_write_reg(IN struct btc_coexist - *btcoexist, - IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) -{ - u32 val, i = 0, j = 0, bitpos = 0; - - - if (bit_mask == 0x0) - return; - if (bit_mask == 0xffffffff) { - btcoexist->btc_write_4byte(btcoexist, 0x1704, - reg_value); /* put write data */ - - /* wait for ready bit before access 0x1700 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x1703)&BIT(5)) == 0) && - (j < BT_8821C_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x1700, - 0xc00F0000 | reg_addr); - } else { - for (i = 0; i <= 31; i++) { - if (((bit_mask >> i) & 0x1) == 0x1) { - bitpos = i; - break; - } - } - - /* read back register value before write */ - val = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - reg_addr); - val = (val & (~bit_mask)) | (reg_value << bitpos); - - btcoexist->btc_write_4byte(btcoexist, 0x1704, - val); /* put write data */ - - /* wait for ready bit before access 0x1700 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x1703)&BIT(5)) == 0) && - (j < BT_8821C_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x1700, - 0xc00F0000 | reg_addr); - - } - -} - -void halbtc8821c1ant_ltecoex_enable(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 val; - - val = (enable) ? 1 : 0; - halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, - val); /* 0x38[7] */ - -} - -void halbtc8821c1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, - IN boolean wifi_control) -{ - u8 val; - - val = (wifi_control) ? 1 : 0; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, - val); /* 0x70[26] */ - -} - -void halbtc8821c1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, val_orig = 0; - - if (!sw_control) - val = 0x0; - else if (state & 0x1) - val = 0x3; - else - val = 0x1; - - val_orig = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - switch (control_block) { - case BT_8821C_1ANT_GNT_BLOCK_RFC_BB: - default: - val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff); - break; - case BT_8821C_1ANT_GNT_BLOCK_RFC: - val = (val << 14) | (val_orig & 0xffff3fff); - break; - case BT_8821C_1ANT_GNT_BLOCK_BB: - val = (val << 10) | (val_orig & 0xfffff3ff); - break; - } - - halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); -} - -void halbtc8821c1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, val_orig = 0; - - if (!sw_control) - val = 0x0; - else if (state & 0x1) - val = 0x3; - else - val = 0x1; - - val_orig = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - switch (control_block) { - case BT_8821C_1ANT_GNT_BLOCK_RFC_BB: - default: - val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff); - break; - case BT_8821C_1ANT_GNT_BLOCK_RFC: - val = (val << 12) | (val_orig & 0xffffcfff); - break; - case BT_8821C_1ANT_GNT_BLOCK_BB: - val = (val << 8) | (val_orig & 0xfffffcff); - break; - } - - halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); -} - -void halbtc8821c1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u16 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8821C_1ANT_CTT_WL_VS_LTE: - reg_addr = 0xa0; - break; - case BT_8821C_1ANT_CTT_BT_VS_LTE: - reg_addr = 0xa4; - break; - } - - if (reg_addr != 0x0000) - halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ - - -} - - -void halbtc8821c1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u8 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8821C_1ANT_LBTT_WL_BREAK_LTE: - reg_addr = 0xa8; - break; - case BT_8821C_1ANT_LBTT_BT_BREAK_LTE: - reg_addr = 0xac; - break; - case BT_8821C_1ANT_LBTT_LTE_BREAK_WL: - reg_addr = 0xb0; - break; - case BT_8821C_1ANT_LBTT_LTE_BREAK_BT: - reg_addr = 0xb4; - break; - } - - if (reg_addr != 0x0000) - halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ - - -} - -void halbtc8821c1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 interval, - IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, - IN u8 val0x6c4_b3) -{ - static u8 pre_h2c_parameter[6] = {0}; - u8 cur_h2c_parameter[6] = {0}; - u8 i, match_cnt = 0; - - cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ - - cur_h2c_parameter[1] = interval; - cur_h2c_parameter[2] = val0x6c4_b0; - cur_h2c_parameter[3] = val0x6c4_b1; - cur_h2c_parameter[4] = val0x6c4_b2; - cur_h2c_parameter[5] = val0x6c4_b3; - - if (!force_exec) { - for (i = 1; i <= 5; i++) { - if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) - break; - - match_cnt++; - } - - if (match_cnt == 5) - return; - } - - for (i = 1; i <= 5; i++) - pre_h2c_parameter[i] = cur_h2c_parameter[i]; - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); -} - - -void halbtc8821c1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8821c1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - - halbtc8821c1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8821c1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - u32 break_table; - u8 select_table; - - coex_sta->coex_table_type = type; - - if (coex_sta->concurrent_rx_mode_on == true) { - break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ - select_table = - 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ - } else { - break_table = 0xffffff; - select_table = 0x3; - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Table-%d **********\n", - coex_sta->coex_table_type); - BTC_TRACE(trace_buf); - - switch (type) { - case 0: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, break_table, - select_table); - break; - case 1: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 2: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0xaa5a5a5a, 0xaa5a5a5a, break_table, - select_table); - break; - case 3: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 4: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 5: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, break_table, - select_table); - break; - case 6: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0x5a5a5a5a, break_table, - select_table); - break; - case 7: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, break_table, - select_table); - break; - case 8: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xaaaa5aaa, break_table, - select_table); - break; - case 9: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaaaa5aaa, break_table, - select_table); - break; - default: - break; - } -} - -void halbtc8821c1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) - h2c_parameter[0] |= BIT(0); /* function enable */ - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8821c1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8821c1ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8821c1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8821c1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8821c1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8821c1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8);*/ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8821c1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - coex_sta->force_lps_on = false; - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - - break; - case BTC_PS_LPS_ON: - coex_sta->force_lps_on = true; - halbtc8821c1ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8821c1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - - break; - case BTC_PS_LPS_OFF: - coex_sta->force_lps_on = false; - halbtc8821c1ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - - break; - default: - break; - } -} - - -void halbtc8821c1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - if (byte5 & BIT(2)) - coex_sta->is_tdma_btautoslot = true; - else - coex_sta->is_tdma_btautoslot = false; - - /* release bt-auto slot for auto-slot hang is detected!! */ - if (coex_sta->is_tdma_btautoslot) - if ((coex_sta->is_tdma_btautoslot_hang) || - (bt_link_info->slave_role)) - byte5 = byte5 & 0xfb; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for 1Ant AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - - halbtc8821c1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - } - } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - - halbtc8821c1ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } else { - halbtc8821c1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, - 0x0); - } - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - - -void halbtc8821c1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - struct btc_board_info *board_info = &btcoexist->board_info; - boolean wifi_busy = false; - static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; - static boolean pre_wifi_busy = false; - - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (wifi_busy != pre_wifi_busy) { - force_exec = true; - pre_wifi_busy = wifi_busy; - } - - /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - if (bt_link_info->slave_role) - psTdmaByte4Modify = 0x1; - else - psTdmaByte4Modify = 0x0; - - if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { - force_exec = true; - pre_psTdmaByte4Modify = psTdmaByte4Modify; - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n", - (coex_dm->cur_ps_tdma_on ? "on" : "off"), - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - return; - } - } - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - - if (turn_on) { - switch (type) { - default: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x11); - break; - - case 3: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x3a, 0x03, 0x10, 0x50); - break; - case 4: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x21, 0x03, 0x10, 0x50); - break; - case 5: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x03, 0x11, 0x11); - break; - case 6: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x20, 0x03, 0x11, 0x11); - break; - case 7: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x54 | - psTdmaByte4Modify); - break; - case 8: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x54 | - psTdmaByte4Modify); - break; - case 9: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x55, 0x10, 0x03, 0x10, 0x54 | - psTdmaByte4Modify); - break; - case 10: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); - break; - case 11: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x65, 0x25, 0x03, 0x11, 0x11 | - psTdmaByte4Modify); - break; - case 12: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x55, 0x30, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 13: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x25, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 14: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x15, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 15: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x20, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 16: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x15 | - psTdmaByte4Modify); - break; - case 17: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x14 | - psTdmaByte4Modify); - break; - case 18: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x30, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 19: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x03, 0x11, 0x10); - break; - case 20: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); - break; - case 21: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); - break; - case 22: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x25, 0x03, 0x11, 0x10); - break; - case 23: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x10); - break; - case 27: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x15); - break; - case 32: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x11); - break; - case 33: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x10); - break; - case 57: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 58: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 67: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x10 | - psTdmaByte4Modify); - break; - - /* 1-Ant to 2-Ant TDMA case */ - case 103: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x3a, 0x03, 0x70, 0x10); - break; - case 104: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x21, 0x03, 0x70, 0x10); - break; - case 105: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x15, 0x03, 0x71, 0x11); - break; - case 106: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x20, 0x03, 0x71, 0x11); - break; - case 107: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x10, 0x03, 0x70, 0x14 | - psTdmaByte4Modify); - break; - case 108: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x10, 0x03, 0x70, 0x14 | - psTdmaByte4Modify); - break; - case 113: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x25, 0x03, 0x70, 0x10 | - psTdmaByte4Modify); - break; - case 114: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x15, 0x03, 0x70, 0x10 | - psTdmaByte4Modify); - break; - case 115: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x20, 0x03, 0x70, 0x10 | - psTdmaByte4Modify); - break; - case 117: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x10, 0x03, 0x71, 0x14 | - psTdmaByte4Modify); - break; - case 119: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x15, 0x03, 0x71, 0x10); - break; - case 120: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x30, 0x03, 0x71, 0x10); - break; - case 121: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x30, 0x03, 0x71, 0x10); - break; - case 122: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x25, 0x03, 0x71, 0x10); - break; - case 132: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x35, 0x03, 0x71, 0x11); - break; - case 133: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x35, 0x03, 0x71, 0x10); - break; - - } - } else { - - /* disable PS tdma */ - switch (type) { - case 8: /* PTA Control */ - halbtc8821c1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); - break; - case 0: - default: /* Software control, Antenna at BT side */ - halbtc8821c1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); - break; - case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */ - halbtc8821c1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8821c1ant_set_int_block(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 pos_type) -{ -#if 0 - u8 regval_0xcba; - u32 u32tmp1 = 0; - - coex_dm->cur_int_block_status = pos_type; - - if (!force_exec) { - if (coex_dm->pre_int_block_status == - coex_dm->cur_int_block_status) - return; - } - - coex_dm->pre_int_block_status = coex_dm->cur_int_block_status; - - regval_0xcba = btcoexist->btc_read_1byte(btcoexist, 0xcba); - - switch (pos_type) { - - case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG: - regval_0xcba = (regval_0xcba | BIT(0)) & (~(BIT( - 2))); /* 0xcb8[16] = 1, 0xcb8[18] = 0, WL_G select BTG */ - regval_0xcba = regval_0xcba & 0x0f; - - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc1d, 0x0f, 0x5); */ /* Gain Table */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xa9e, 0x0f, 0x2); */ /* CCK Gain Table */ - - break; - case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG: - regval_0xcba = regval_0xcba & (~(BIT(2) | BIT( - 0))); /* 0xcb8[16] = 0, 0xcb8[18] = 0, WL_G select WLAG */ - - /* regval_0xcba = regval_0xcba | BIT(4) | BIT(5) ; */ /* 0xcb8[21:20] = 2b'11, WL_G @ WLAG on */ - /* regval_0xcba = (regval_0xcba | BIT(6)) & (~(BIT(7)) ) ; */ /* 0xcb8[23:22] = 2b'01, WL_A @ WLAG off */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc1d, 0x0f, 0x0); */ /* Gain Table */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xa9e, 0x0f, 0x6); */ /* CCK Gain Table */ - - break; - case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG: - regval_0xcba = regval_0xcba & (~(BIT(2) | BIT( - 0))); /* 0xcb8[16] = 0, 0xcb8[18] = 0, WL_G select WLAG */ - /*regval_0xcba = (regval_0xcba | BIT(4)) & (~(BIT(5))); */ /* 0xcb8[21:20] = 2b'01, WL_G @ WLAG off */ - /*regval_0xcba = regval_0xcba | BIT(6) | BIT(7); */ /* 0xcb8[23:22] = 2b'11, WL_A @ WLAG on */ - - break; - } - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcba, 0xff, - regval_0xcba); - - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Int Block setup) 0xcb8 = 0x%08x **********\n", - u32tmp1); - BTC_TRACE(trace_buf); - -#endif -} - -void halbtc8821c1ant_set_ext_band_switch(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 pos_type) -{ - -#if 0 - boolean switch_polatiry_inverse = false; - u8 regval_0xcb6; - u32 u32tmp1 = 0, u32tmp2 = 0; - - if (!rfe_type->ext_band_switch_exist) - return; - - coex_dm->cur_ext_band_switch_status = pos_type; - - if (!force_exec) { - if (coex_dm->pre_ext_band_switch_status == - coex_dm->cur_ext_band_switch_status) - return; - } - - coex_dm->pre_ext_band_switch_status = - coex_dm->cur_ext_band_switch_status; - - /* swap control polarity if use different switch control polarity*/ - switch_polatiry_inverse = (rfe_type->ext_band_switch_ctrl_polarity == 1 - ? ~switch_polatiry_inverse : switch_polatiry_inverse); - - /*swap control polarity for WL_A, default polarity 0xcb4[21] = 0 && 0xcb4[23] = 1 is for WL_G */ - switch_polatiry_inverse = (pos_type == - BT_8821C_1ANT_EXT_BAND_SWITCH_TO_WLA ? ~switch_polatiry_inverse - : switch_polatiry_inverse); - - regval_0xcb6 = btcoexist->btc_read_1byte(btcoexist, 0xcb6); - - /* for normal switch polrity, 0xcb4[21] =1 && 0xcb4[23] = 0 for WL_A, vice versa */ - regval_0xcb6 = (switch_polatiry_inverse == 1 ? ((regval_0xcb6 & (~(BIT( - 7)))) | BIT(5)) : ((regval_0xcb6 & (~(BIT(5)))) | BIT(7))); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb6, 0xff, - regval_0xcb6); - - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb0); - u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ext Band switch setup) 0xcb0 = 0x%08x, 0xcb4 = 0x%08x**********\n", - u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif - -} - -void halbtc8821c1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - boolean switch_polatiry_inverse = false; - u8 regval_0xcb7 = 0, regval_0x64; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - - if (!rfe_type->ext_ant_switch_exist) - return; - - coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; - - if (!force_exec) { - if (coex_dm->pre_ext_ant_switch_status == - coex_dm->cur_ext_ant_switch_status) - return; - } - - coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status; - - /* swap control polarity if use different switch control polarity*/ - /* Normal switch polarity for DPDT, 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main */ - /* Normal switch polarity for SPDT, 0xcb4[29:28] = 2b'01 => Ant to BTG, 0xcb4[29:28] = 2b'10 => Ant to WLG */ - if (rfe_type->ext_ant_switch_ctrl_polarity) - switch_polatiry_inverse = ~switch_polatiry_inverse; - - /* swap control polarity if 1-Ant at Aux */ - if (rfe_type->ant_at_main_port == false) - switch_polatiry_inverse = ~switch_polatiry_inverse; - - switch (pos_type) { - default: - case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_BT: - case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE: - case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLA: - - break; - case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLG: - if (!rfe_type->wlg_Locate_at_btg) - switch_polatiry_inverse = ~switch_polatiry_inverse; - break; - } - - if (board_info->ant_div_cfg) - ctrl_type = BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; - - - switch (ctrl_type) { - default: - case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x77); /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ - - regval_0xcb7 = (switch_polatiry_inverse == false ? - 0x1 : 0x2); /* 0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, regval_0xcb7); - - break; - case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x66); /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ - - regval_0xcb7 = (switch_polatiry_inverse == false ? - 0x2 : 0x1); /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, regval_0xcb7); - - break; - case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x88); /* */ - - /* no regval_0xcb7 setup required, because antenna switch control value by antenna diversity */ - - break; - case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x1); /* 0x4c[23] = 1 */ - - regval_0x64 = (switch_polatiry_inverse == false ? 0x0 : - 0x1); /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, - regval_0x64); - break; - case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x0); /* 0x4c[24] = 0 */ - - /* no setup required, because antenna switch control value by BT vendor 0xac[1:0] */ - break; - } - - /* PAPE, LNA_ON control by BT while WLAN off for current leakage issue */ - if (ctrl_type == BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT) { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x0); /* PAPE 0x64[29] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, - 0x0); /* LNA_ON 0x64[28] = 0 */ - } else { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x1); /* PAPE 0x64[29] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, - 0x1); /* LNA_ON 0x64[28] = 1 */ - } - -#if BT_8821C_1ANT_COEX_DBG - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (After Ext Ant switch setup) 0xcb4 = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n", - u32tmp1, u32tmp2, u32tmp3); - BTC_TRACE(trace_buf); -#endif - -} - -void halbtc8821c1ant_set_rfe_type(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - - - /* the following setup should be got from Efuse in the future */ - rfe_type->rfe_module_type = board_info->rfe_type & 0x1f; - - rfe_type->ext_ant_switch_ctrl_polarity = 0; - - switch (rfe_type->rfe_module_type) { - case 0: - default: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; /*2-Ant, DPDT, WLG*/ - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = true; - break; - case 1: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, WLG */ - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = true; - break; - case 2: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, BTG */ - rfe_type->wlg_Locate_at_btg = true; - rfe_type->ant_at_main_port = true; - break; - case 3: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, WLG */ - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = false; - break; - case 4: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, BTG */ - rfe_type->wlg_Locate_at_btg = true; - rfe_type->ant_at_main_port = false; - break; - case 5: - rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_NONE; - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = true; - break; - case 6: - rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_NONE; - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = true; - break; - case 7: - rfe_type->ext_ant_switch_exist = true; /*2-Ant, DPDT, BTG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; - rfe_type->wlg_Locate_at_btg = true; - rfe_type->ant_at_main_port = true; - break; - } - -#if 0 - if (rfe_type->wlg_Locate_at_btg) - halbtc8821c1ant_set_int_block(btcoexist, FORCE_EXEC, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); - else - halbtc8821c1ant_set_int_block(btcoexist, FORCE_EXEC, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); -#endif - -} - - -void halbtc8821c1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, - IN u8 phase) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u32 cnt_bt_cal_chk = 0; - boolean is_in_mp_mode = false; - u8 u8tmp = 0; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - u16 u16tmp1 = 0; - - - u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - /* To avoid indirect access fail */ - if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { - force_exec = true; - coex_sta->gnt_error_cnt++; - } - - -#if BT_8821C_1ANT_COEX_DBG - - u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0x54); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],(Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", - u32tmp3, u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif - - coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],(Before Ant Setup) pre_ant_pos_type = 0x%x, cur_ant_pos_type = 0x%x\n", - coex_dm->pre_ant_pos_type, - coex_dm->cur_ant_pos_type); - BTC_TRACE(trace_buf); - - - if (!force_exec) { - if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) - return; - } - - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; - - - switch (phase) { - case BT_8821C_1ANT_PHASE_COEX_POWERON: - - /* set Path control owner to WL at initial step */ - halbtc8821c1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8821C_1ANT_PCO_BTSIDE); - - /* set GNT_BT to SW high */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW high */ - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - coex_sta->run_time_state = false; - - break; - case BT_8821C_1ANT_PHASE_COEX_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c1ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_1ANT_CTT_WL_VS_LTE, - 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c1ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_1ANT_CTT_BT_VS_LTE, - 0xffff); - - /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ - while (cnt_bt_cal_chk <= 20) { - u8tmp = btcoexist->btc_read_1byte( - btcoexist, - 0x49c); - cnt_bt_cal_chk++; - if (u8tmp & BIT(1)) { - BTC_SPRINTF( - trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", - cnt_bt_cal_chk); - BTC_TRACE( - trace_buf); - delay_ms(50); - } else { - BTC_SPRINTF( - trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", - cnt_bt_cal_chk); - BTC_TRACE( - trace_buf); - break; - } - } - - /* set Path control owner to WL at initial step */ - halbtc8821c1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_1ANT_PCO_WLSIDE); - - /* set GNT_BT to SW high */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW low */ - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_LOW); - - coex_sta->run_time_state = false; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - break; - case BT_8821C_1ANT_PHASE_WLANONLY_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c1ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_1ANT_CTT_WL_VS_LTE, - 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c1ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_1ANT_CTT_BT_VS_LTE, - 0xffff); - - /* set Path control owner to WL at initial step */ - halbtc8821c1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_1ANT_PCO_WLSIDE); - - /* set GNT_BT to SW Low */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_LOW); - /* Set GNT_WL to SW high */ - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); - - coex_sta->run_time_state = false; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_WIFI; - - break; - case BT_8821C_1ANT_PHASE_WLAN_OFF: - /* Disable LTE Coex Function in WiFi side */ - halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); - - /* set Path control owner to BT */ - halbtc8821c1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_1ANT_PCO_BTSIDE); - - /* Set Ext Ant Switch to BT control at wifi off step */ - halbtc8821c1ant_set_ext_ant_switch(btcoexist, - FORCE_EXEC, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE); - - coex_sta->run_time_state = false; - break; - case BT_8821C_1ANT_PHASE_2G_RUNTIME: - - while (cnt_bt_cal_chk <= 20) { - /* 0x49c[0]=1 WL IQK, 0x49c[1]=1 BT IQK*/ - u8tmp = btcoexist->btc_read_1byte( - btcoexist, - 0x49c); - - cnt_bt_cal_chk++; - if (u8tmp & BIT(0)) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### WL is IQK (wait cnt=%d)\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - delay_ms(50); - } else if (u8tmp & BIT(1)) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is IQK (wait cnt=%d)\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - delay_ms(50); - } else { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - break; - } - } - - /* set Path control owner to WL at runtime step */ - halbtc8821c1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_1ANT_PCO_WLSIDE); - - /* set GNT_BT to PTA */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_1ANT_SIG_STA_SET_BY_HW); - - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_1ANT_SIG_STA_SET_BY_HW); - - coex_sta->run_time_state = true; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (rfe_type->wlg_Locate_at_btg) - ant_pos_type = - BTC_ANT_PATH_WIFI; - else - ant_pos_type = BTC_ANT_PATH_PTA; - } - - if (rfe_type->wlg_Locate_at_btg) - halbtc8821c1ant_set_int_block(btcoexist, - NORMAL_EXEC, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); - else - halbtc8821c1ant_set_int_block(btcoexist, - NORMAL_EXEC, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); - - break; - case BT_8821C_1ANT_PHASE_5G_RUNTIME: - - /* set Path control owner to WL at runtime step */ - halbtc8821c1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_1ANT_PCO_WLSIDE); - - /* set GNT_BT to SW Hi */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_1ANT_SIG_STA_SET_BY_HW); - - /* Set GNT_WL to SW Hi */ - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); - - coex_sta->run_time_state = true; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - /* if (rfe_type->ext_band_switch_exist) - ant_pos_type = BTC_ANT_PATH_PTA; - else */ - ant_pos_type = - BTC_ANT_PATH_WIFI5G; - } - - halbtc8821c1ant_set_int_block(btcoexist, - NORMAL_EXEC, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG); - - break; - case BT_8821C_1ANT_PHASE_BTMPMODE: - /* Disable LTE Coex Function in WiFi side */ - halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); - - /* set Path control owner to WL */ - halbtc8821c1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_1ANT_PCO_WLSIDE); - - /* set GNT_BT to SW Hi */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); - - /* Set GNT_WL to SW Lo */ - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_LOW); - - coex_sta->run_time_state = false; - - /* Set Ext Ant Switch to BT side at BT MP mode */ - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - break; - case BT_8821C_1ANT_PHASE_ANTENNA_DET: - halbtc8821c1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8821C_1ANT_PCO_WLSIDE); - - /* set GNT_BT to high */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to high */ - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = BTC_ANT_PATH_BT; - - coex_sta->run_time_state = false; - - break; - } - - if (phase != BT_8821C_1ANT_PHASE_WLAN_OFF) { - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - halbtc8821c1ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLG); - break; - case BTC_ANT_PATH_WIFI5G - : - halbtc8821c1ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLA); - break; - case BTC_ANT_PATH_BT: - halbtc8821c1ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_BT); - break; - default: - case BTC_ANT_PATH_PTA: - halbtc8821c1ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE); - break; - } - - } - -#if BT_8821C_1ANT_COEX_DBG - u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],(After Ant-Setup phase---%d) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", - phase, u32tmp3, u8tmp, u32tmp1, u32tmp2); - - BTC_TRACE(trace_buf); -#endif -} - - -boolean halbtc8821c1ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = false, wifi_connected = false, wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - common = true; - } else if (wifi_connected && - (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); - BTC_TRACE(trace_buf); - - common = true; - } else if (!wifi_connected && - (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - - common = true; - } else if (wifi_connected && - (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); - BTC_TRACE(trace_buf); - - common = true; - } else if (!wifi_connected && - (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE != - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - - common = true; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } - - common = false; - } - - return common; -} - - -/* ********************************************* - * - * Software Coex Mechanism start - * - * ********************************************* */ - - - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8821c1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) -{ - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8821c1ant_action_bt_hs(IN struct btc_coexist *btcoexist) -{ - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - -void halbtc8821c1ant_action_bt_relink(IN struct btc_coexist *btcoexist) -{ - /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5); */ - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - coex_sta->bt_relink_downcount = 2; -} - -void halbtc8821c1ant_action_bt_idle(IN struct btc_coexist *btcoexist) -{ - boolean wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_busy) { - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 6); - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - - } else { /* if wl busy */ - - if (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 33); - } else { - - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); - - } - - } - -} - -void halbtc8821c1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, wifi_busy = false, - bt_busy = false; - boolean wifi_scan = false, wifi_link = false, wifi_roam = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); - - - if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) - || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - - if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17); - else - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - } else if ((!wifi_connected) && (!wifi_scan)) { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (bt_link_info->pan_exist) { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - - if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) - || (coex_sta->wifi_is_high_pri_task)) - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - else - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } -} - -void halbtc8821c1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, wifi_busy = false; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - - if (bt_link_info->sco_exist) { - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 5); - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 5); - } else if (coex_sta->hid_busy_num >= 2) { /*for 4/18 hid */ - - /* if 11bg mode */ - if (wifi_bw == 0) { - - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8821c1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 11); - } else { - - if (wifi_busy) { - - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8821c1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 11); - } else { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 6); - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - - } - } - } else { - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 6); - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - } -} - -void halbtc8821c1ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) -{ - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8821C_1ANT_PHASE_5G_RUNTIME); -} - - -void halbtc8821c1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - halbtc8821c1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 7); -} - -void halbtc8821c1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - - if (!bt_link_info->pan_exist) - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - else - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); -} - - -void halbtc8821c1ant_action_wifi_linkscan_process(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - if (bt_link_info->pan_exist) { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 27); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } - -} - -void halbtc8821c1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false, wifi_turbo = false; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - if ((coex_sta->bt_relink_downcount != 0) - && (!bt_link_info->pan_exist) && (wifi_busy)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); - BTC_TRACE(trace_buf); - - /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);*/ - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - } else if (bt_link_info->a2dp_only) { /* A2DP */ - if (!wifi_busy) { - - /* halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 32); */ - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 27); - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - - if (coex_sta->wl_noisy_level == 2) - halbtc8821c1ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 17); - else - halbtc8821c1ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 7); - - if (wifi_turbo) - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else if (((bt_link_info->a2dp_exist) && - (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - - if ((bt_link_info->hid_exist) && - (coex_sta->hid_busy_num >= 2)) { - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8821c1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 12); - } else if (wifi_busy) { - if (((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) || - (!coex_sta->is_A2DP_3M)) - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 15); - else if (wifi_turbo) - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 18); - else - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 13); - } else - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - - if (bt_link_info->hid_exist) - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - else if (wifi_turbo) - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - - if ((wifi_busy) && (coex_sta->hid_busy_num >= 2)) {/*for 4/18 hid */ - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - - if (wifi_bw == 0) /* 11bg mode */ - halbtc8821c1ant_set_wltoggle_coex_table( - btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - else - halbtc8821c1ant_set_wltoggle_coex_table( - btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, - 9); - } else { - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, - 8); - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } - - } else if ((bt_link_info->pan_only) - || (bt_link_info->hid_exist && bt_link_info->pan_exist)) { - /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - - if ((bt_link_info->hid_exist) && (bt_link_info->pan_exist) && - (coex_sta->hid_busy_num >= 2)) { - - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - if (wifi_bw == 0) /* 11bg mode */ - halbtc8821c1ant_set_wltoggle_coex_table( - btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - else - halbtc8821c1ant_set_wltoggle_coex_table( - btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 12); - } else { - - if (!wifi_busy) - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 4); - else - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 3); - - if (bt_link_info->hid_exist) - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - else if (wifi_turbo) - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } - } else { - /* BT no-profile busy (0x9) */ - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } - -} - -void halbtc8821c1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - /* tdma and coex table */ - halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8821c1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = false; - boolean wifi_under_5g = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (wifi_under_5g) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 5G!!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_under5g(btcoexist); - return; - } - - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - - if (BT_8821C_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - - if (bt_link_info->hid_only) /* HID only */ - halbtc8821c1ant_action_bt_sco_hid_only_busy(btcoexist); - else - halbtc8821c1ant_action_wifi_connected_bt_acl_busy( - btcoexist); - - } else if ((BT_8821C_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) - halbtc8821c1ant_action_bt_sco_hid_only_busy(btcoexist); - else - halbtc8821c1ant_action_bt_idle(btcoexist); - -} - -void halbtc8821c1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - - algorithm = halbtc8821c1ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - - if (!halbtc8821c1ant_is_common_action(btcoexist)) { - switch (coex_dm->cur_algorithm) { - case BT_8821C_1ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_sco(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_hid(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_a2dp(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_a2dp_pan_hs(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_pan_edr(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_pan_hs(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_pan_edr_a2dp(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_pan_edr_hid(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_hid_a2dp_pan_edr(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_hid_a2dp(btcoexist); */ - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_coex_all_off(btcoexist); */ - break; - } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - } -} - - -void halbtc8821c1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = false, bt_hs_on = false; - boolean increase_scan_dev_num = false; - boolean bt_ctrl_agg_buf_size = false; - boolean miracast_plus_bt = false, wifi_under_5g = false; - u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0, wifi_bw; - u8 iot_peer = BTC_IOT_PEER_UNKNOWN; - boolean scan = false, link = false, roam = false, under_4way = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (!coex_sta->run_time_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], return for run_time_state = false !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->freeze_coexrun_by_btinfo) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (wifi_under_5g) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 5G!!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_under5g(btcoexist); - return; - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 2G!!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - } - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8821c1ant_action_bt_whql_test(btcoexist); - return; - } - - if (coex_sta->bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!!\n"); - halbtc8821c1ant_action_wifi_only(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8821c1ant_action_bt_inquiry(btcoexist); - return; - } - - if (coex_sta->is_setupLink) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is re-link !!!\n"); - halbtc8821c1ant_action_bt_relink(btcoexist); - return; - } - - if ((BT_8821C_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = true; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) - miracast_plus_bt = true; - else - miracast_plus_bt = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - halbtc8821c1ant_limited_rx(btcoexist, NORMAL_EXEC, false, - false, 0x5); - - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", - scan, link, roam, under_4way); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_linkscan_process(btcoexist); - } else - halbtc8821c1ant_action_wifi_multi_port(btcoexist); - - return; - } else { - - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - - btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); - - if (BTC_IOT_PEER_CISCO == iot_peer) { - - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8821c1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x10); - else - halbtc8821c1ant_limited_rx(btcoexist, - NORMAL_EXEC, false, true, 0x8); - } else - halbtc8821c1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, - 0x5); - } - - halbtc8821c1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is hs\n"); - BTC_TRACE(trace_buf); - halbtc8821c1ant_action_bt_hs(btcoexist); - return; - } - - if ((BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is idle\n"); - BTC_TRACE(trace_buf); - halbtc8821c1ant_action_bt_idle(btcoexist); - return; - } - - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", - scan, link, roam, under_4way); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under linkscan process!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_linkscan_process(btcoexist); - } else if (wifi_connected) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under connected!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_connected(btcoexist); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under not-connected!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_not_connected(btcoexist); - } -} - -void halbtc8821c1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - /* force to reset coex mechanism */ - halbtc8821c1ant_low_penalty_ra(btcoexist, FORCE_EXEC, false); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->pop_event_cnt = 0; - coex_sta->cnt_RemoteNameReq = 0; - coex_sta->cnt_ReInit = 0; - coex_sta->cnt_setupLink = 0; - coex_sta->cnt_IgnWlanAct = 0; - coex_sta->cnt_Page = 0; - coex_sta->cnt_RoleSwitch = 0; - - halbtc8821c1ant_query_bt_info(btcoexist); -} - -void halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up, IN boolean wifi_only) -{ - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - u16 u16tmp1 = 0; - u8 i; - struct btc_board_info *board_info = &btcoexist->board_info; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],(Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", - u32tmp3, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - coex_sta->bt_ble_scan_type = 0; - coex_sta->bt_ble_scan_para[0] = 0; - coex_sta->bt_ble_scan_para[1] = 0; - coex_sta->bt_ble_scan_para[2] = 0; - coex_sta->bt_reg_vendor_ac = 0xffff; - coex_sta->bt_reg_vendor_ae = 0xffff; - coex_sta->isolation_btween_wb = BT_8821C_1ANT_DEFAULT_ISOLATION; - coex_sta->gnt_error_cnt = 0; - coex_sta->bt_relink_downcount = 0; - - for (i = 0; i <= 9; i++) - coex_sta->bt_afh_map[i] = 0; - - /* Setup RF front end type */ - halbtc8821c1ant_set_rfe_type(btcoexist); - - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - - /* BT report packet sample rate */ - btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); - - /* Init 0x778 = 0x1 for 1-Ant */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - - /* Enable PTA (3-wire function form BT side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); - - /* Enable PTA (tx/rx signal form WiFi side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); - - /* set GNT_BT=1 for coex table select both */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1); - - halbtc8821c1ant_enable_gnt_to_gpio(btcoexist, true); - -#if 0 - /* check if WL firmware download ok */ - /*if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)*/ - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ONOFF, true); -#endif - - /* PTA parameter */ - halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); - - halbtc8821c1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - psd_scan->ant_det_is_ant_det_available = true; - - /* Antenna config */ - if (wifi_only) { - coex_sta->concurrent_rx_mode_on = false; - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_WLANONLY_INIT); - - btcoexist->stop_coex_dm = true; - } else { - /*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); - - coex_sta->concurrent_rx_mode_on = true; - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */ - - /* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx, mask Tx only */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0); - - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_COEX_INIT); - - btcoexist->stop_coex_dm = false; - } - - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (After Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", - u32tmp3, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); - -} - - -/* ************************************************************ - * work around function start with wa_halbtc8821c1ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8821c1ant_ - * ************************************************************ */ -void ex_halbtc8821c1ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x0; - u16 u16tmp = 0x0; - u32 value = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Execute 8821c 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Ant Det Finish = %s, Ant Det Number = %d\n", - (board_info->btdm_ant_det_finish ? "Yes" : "No"), - board_info->btdm_ant_num_by_ant_det); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = true; - psd_scan->ant_det_is_ant_det_available = false; - - /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - - /* Set Antenna Path to BT side */ - /* Check efuse 0xc3[6] for Single Antenna Path */ - if (board_info->single_ant_path == 0) { - - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - u8tmp = 1; - } else if (board_info->single_ant_path == 1) { - - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - u8tmp = 0; - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d\n", - board_info->single_ant_path , board_info->btdm_ant_pos); - BTC_TRACE(trace_buf); - - /* Setup RF front end type */ - halbtc8821c1ant_set_rfe_type(btcoexist); - - /* Set Antenna Path to BT side */ - halbtc8821c1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_COEX_POWERON); - - /* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at power on */ - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); - - /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - halbtc8821c1ant_enable_gnt_to_gpio(btcoexist, true); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x\n", - halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38)); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcb4 (Power-On) = 0x%x / 0x%x\n", - btcoexist->btc_read_4byte(btcoexist, 0x70), - btcoexist->btc_read_4byte(btcoexist, 0xcb4)); - BTC_TRACE(trace_buf); - -} - -void ex_halbtc8821c1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ -} - -void ex_halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8821c1ant_init_hw_config(btcoexist, true, wifi_only); -} - -void ex_halbtc8821c1ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - halbtc8821c1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; - u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; - static u8 pop_report_in_10s = 0; - u32 phyver = 0; - boolean lte_coex_on = false; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - if (btcoexist->stop_coex_dm) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - if (psd_scan->ant_det_try_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %s / %d", - "Ant PG Num/ Mech/ Pos/ RFE", - board_info->pg_ant_num, board_info->btdm_ant_num, - (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT - ? "Main" : "Aux"), - rfe_type->rfe_module_type); - CL_PRINTF(cli_buf); - } else { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", - board_info->pg_ant_num, - board_info->btdm_ant_num_by_ant_det, - (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT - ? "Main" : "Aux"), - rfe_type->rfe_module_type, - psd_scan->ant_det_try_count, - psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); - CL_PRINTF(cli_buf); - - if (board_info->btdm_ant_det_finish) { - - if (psd_scan->ant_det_result != 12) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d", - "Ant Det PSD Value", - psd_scan->ant_det_psd_scan_peak_val - / 100); - CL_PRINTF(cli_buf); - } - } - - bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); - - bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", - "CoexVer WL/ BT_Desired/ BT_Report", - glcoex_ver_date_8821c_1ant, glcoex_ver_8821c_1ant, - glcoex_ver_btdesired_8821c_1ant, - bt_coex_ver, - (bt_coex_ver == 0xff ? "Unknown" : - (coex_sta->bt_disabled ? "BT-disable" : - (bt_coex_ver >= glcoex_ver_btdesired_8821c_1ant ? - "Match" : "Mis-Match")))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", - "W_FW/ B_FW/ Phy/ Kt", - fw_ver, bt_patch_ver, phyver, - coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "AFH Map to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") - : ((BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); - CL_PRINTF(cli_buf); - - if (pop_report_in_10s >= 5) { - coex_sta->pop_event_cnt = 0; - pop_report_in_10s = 0; - } - - if (coex_sta->num_of_profile != 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s%s%s%s%s", - "Profiles", - ((bt_link_info->a2dp_exist) ? "A2DP," : ""), - ((bt_link_info->sco_exist) ? "HFP," : ""), - ((bt_link_info->hid_exist) ? - ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : - "HID(2/18),") : ""), - ((bt_link_info->pan_exist) ? "PAN," : ""), - ((coex_sta->voice_over_HOGP) ? "Voice" : "")); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = None", "Profiles"); - - CL_PRINTF(cli_buf); - - if (bt_link_info->a2dp_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", - "A2DP Rate/Bitpool/Auto_Slot", - ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), - coex_sta->a2dp_bit_pool, - ((coex_sta->is_autoslot) ? "On" : "Off") - ); - CL_PRINTF(cli_buf); - } - - if (bt_link_info->hid_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "HID PairNum/Forbid_Slot", - coex_sta->hid_pair_cnt, - coex_sta->forbidden_slot - ); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x", - "Role/RoleSwCnt/IgnWlact/Feature", - ((bt_link_info->slave_role) ? "Slave" : "Master"), - coex_sta->cnt_RoleSwitch, - ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), - coex_sta->bt_coex_supported_feature); - CL_PRINTF(cli_buf); - - if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "BLEScan Type/TV/Init/Ble", - coex_sta->bt_ble_scan_type, - (coex_sta->bt_ble_scan_type & 0x1 ? - coex_sta->bt_ble_scan_para[0] : 0x0), - (coex_sta->bt_ble_scan_type & 0x2 ? - coex_sta->bt_ble_scan_para[1] : 0x0), - (coex_sta->bt_ble_scan_type & 0x4 ? - coex_sta->bt_ble_scan_para[2] : 0x0)); - CL_PRINTF(cli_buf); - } - - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", - "ReInit/ReLink/IgnWlact/Page/NameReq", - coex_sta->cnt_ReInit, - coex_sta->cnt_setupLink, - coex_sta->cnt_IgnWlanAct, - coex_sta->cnt_Page, - coex_sta->cnt_RemoteNameReq - ); - CL_PRINTF(cli_buf); - - halbtc8821c1ant_read_score_board(btcoexist, &u16tmp[0]); - - if ((coex_sta->bt_reg_vendor_ae == 0xffff) || - (coex_sta->bt_reg_vendor_ac == 0xffff)) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", - ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), - coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); - CL_PRINTF(cli_buf); - - if (coex_sta->num_of_profile > 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", - "AFH MAP", - coex_sta->bt_afh_map[0], - coex_sta->bt_afh_map[1], - coex_sta->bt_afh_map[2], - coex_sta->bt_afh_map[3], - coex_sta->bt_afh_map[4], - coex_sta->bt_afh_map[5], - coex_sta->bt_afh_map[6], - coex_sta->bt_afh_map[7], - coex_sta->bt_afh_map[8], - coex_sta->bt_afh_map[9] - ); - CL_PRINTF(cli_buf); - } - - for (i = 0; i < BT_INFO_SRC_8821C_1ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8821c_1ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanisms] (before Manual)============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Mechanisms]============"); - - CL_PRINTF(cli_buf); - - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s)", - "TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off")); - - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", - "Table/0x6c0/0x6c4/0x6c8", - coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x", - "0x778/0x6cc", - u8tmp[0], u32tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", - "AntDiv/ForceLPS/LPRA", - ((board_info->ant_div_cfg) ? "On" : "Off"), - ((coex_sta->force_lps_on) ? "On" : "Off"), - ((coex_dm->cur_low_penalty_ra) ? "On" : "Off")); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? true : false; - - if (lte_coex_on) { - - u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa0); - u32tmp[1] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "LTE Coex Table W_L/B_L", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa8); - u32tmp[1] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0xac); - u32tmp[2] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb0); - u32tmp[3] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb4); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "LTE Break Table W_L/B_L/L_W/L_B", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, - u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); - CL_PRINTF(cli_buf); - } - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp[1] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", - "LTE Coex/Path Owner", - ((lte_coex_on) ? "On" : "Off") , - ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); - CL_PRINTF(cli_buf); - - if (lte_coex_on) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %d/ %d", - "LTE 3Wire/OPMode/UART/UARTMode", - (int)((u32tmp[0] & BIT(6)) >> 6), - (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), - (int)((u32tmp[0] & BIT(3)) >> 3), - (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "LTE_Busy/UART_Busy", - (int)((u32tmp[1] & BIT(1)) >> 1), - (int)(u32tmp[1] & BIT(0))); - CL_PRINTF(cli_buf); - } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", - "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", - ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), - ((u8tmp[0] & BIT(3)) ? "On" : "Off"), - coex_sta->gnt_error_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "GNT_WL/GNT_BT", - (int)((u32tmp[1] & BIT(2)) >> 2), - (int)((u32tmp[1] & BIT(3)) >> 3)); - CL_PRINTF(cli_buf); - - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s", - "0xcb0/0xcb4/0xcb8[23:16]", - u32tmp[0], u32tmp[1], u8tmp[0], - ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "4c[24:23]/64[0]/4c6[4]/40[5]", - (u32tmp[0] & (BIT(24) | BIT(23))) >> 23 , u8tmp[2] & 0x1 , - (int)((u8tmp[0] & BIT(4)) >> 4), - (int)((u8tmp[1] & BIT(5)) >> 5)); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x", - "0x550/0x522/4-RxAGC/0xc50", - u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]); - CL_PRINTF(cli_buf); - - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_CCK); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm); - CL_PRINTF(cli_buf); - - -#if 1 - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11ac", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11ac", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); - CL_PRINTF(cli_buf); -#endif - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "WlHiPri/ Locking/ Locked/ Noisy", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), - (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No"), - coex_sta->wl_noisy_level); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", - "0x770(Hi-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx, - (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : "")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", - "0x774(Lo-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx, - (bt_link_info->slave_role ? "(Slave!!)" : ( - coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); - CL_PRINTF(cli_buf); - - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8821c1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - - /* Write WL "Active" in Score-board for LPS off */ - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, - false); - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_WLAN_OFF); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); -#if 0 - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE, true); - - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ONOFF, true); -#endif - halbtc8821c1ant_init_hw_config(btcoexist, false, false); - halbtc8821c1ant_init_coex_dm(btcoexist); - - coex_sta->under_ips = false; - } -} - -void ex_halbtc8821c1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - - if (coex_sta->force_lps_on == true) { /* LPS No-32K */ - /* Write WL "Active" in Score-board for PS-TDMA */ - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE, true); - - } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ - /* Write WL "Non-Active" in Score-board for Native-PS */ - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE, false); - - } - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - - /* Write WL "Active" in Score-board for LPS off */ - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE, true); - - } -} - -void ex_halbtc8821c1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false; - boolean wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - coex_sta->freeze_coexrun_by_btinfo = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - if (wifi_connected) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** WL connected before SCAN\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** WL is not connected before SCAN\n"); - - BTC_TRACE(trace_buf); - - halbtc8821c1ant_query_bt_info(btcoexist); - - if (BTC_SCAN_START == type) { - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, - &wifi_under_5g); - - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_ONOFF, - true); - - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** SCAN START notify (5g)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_under5g(btcoexist); - return; - } - - coex_sta->wifi_is_high_pri_task = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** SCAN START notify (2g)\n"); - BTC_TRACE(trace_buf); - - /* Force antenna setup for no scan result issue */ - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - - halbtc8821c1ant_run_coexist_mechanism(btcoexist); - - return; - } - - if (BTC_SCAN_START_2G == type) { - - if (!wifi_connected) - coex_sta->wifi_is_high_pri_task = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify (2G)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_ONOFF, - true); - - /* Force antenna setup for no scan result issue */ - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - - halbtc8821c1ant_run_coexist_mechanism(btcoexist); - - } else { - - coex_sta->wifi_is_high_pri_task = false; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", - coex_sta->scan_ap_num); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_run_coexist_mechanism(btcoexist); - } - - -} - -void ex_halbtc8821c1ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - - if (type == BTC_SWITCH_TO_5G) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], switchband_notify --- switch to 5G\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_under5g(btcoexist); - - } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** switchband_notify BTC_SWITCH_TO_2G (no for scan)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_run_coexist_mechanism(btcoexist); - - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], switchband_notify --- switch to 2G\n"); - BTC_TRACE(trace_buf); - - ex_halbtc8821c1ant_scan_notify(btcoexist, - BTC_SCAN_START_2G); - } -} - - -void ex_halbtc8821c1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_ONOFF, - true); - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if ((BTC_ASSOCIATE_5G_START == type) || - (BTC_ASSOCIATE_5G_FINISH == type)) { - - if (BTC_ASSOCIATE_5G_START == type) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], connect_notify --- 5G start\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], connect_notify --- 5G finish\n"); - - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_under5g(btcoexist); - return; - } - - if (BTC_ASSOCIATE_START == type) { - - coex_sta->wifi_is_high_pri_task = true; - - /* Force antenna setup for no scan result issue */ - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify (2G)\n"); - BTC_TRACE(trace_buf); - - coex_dm->arp_cnt = 0; - - halbtc8821c1ant_run_coexist_mechanism(btcoexist); - - /* To keep TDMA case during connect process, - to avoid changed by Btinfo and runcoexmechanism */ - coex_sta->freeze_coexrun_by_btinfo = true; - } else { - - coex_sta->wifi_is_high_pri_task = false; - coex_sta->freeze_coexrun_by_btinfo = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify (2G)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_run_coexist_mechanism(btcoexist); - } - -} - -void ex_halbtc8821c1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_under_b_mode = false, wifi_under_5g = false; - - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (BTC_MEDIA_CONNECT == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF, - true); - - if (wifi_under_5g) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 5G!!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_under5g(btcoexist); - return; - } - - /* Force antenna setup for no scan result issue */ - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - /* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */ - /* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } - - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE, false); - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - - coex_sta->cck_ever_lock = false; - } - - halbtc8821c1ant_update_wifi_channel_info(btcoexist, type); - -} - -void ex_halbtc8821c1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean under_4way = false, wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (wifi_under_5g) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 5G!!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_under5g(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (under_4way) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ---- under_4way!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - } else if (BTC_PACKET_ARP == type) { - - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify -cnt = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", - type); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - } - - if (coex_sta->wifi_is_high_pri_task) { - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_SCAN, true); - halbtc8821c1ant_run_coexist_mechanism(btcoexist); - } - -} - -void ex_halbtc8821c1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean wifi_scan = false, wifi_link = false, wifi_roam = false, - wifi_busy = false; - static boolean is_scoreboard_scan = false; - - if (psd_scan->is_AntDet_running == true) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt_info_notify return for AntDet is running\n"); - BTC_TRACE(trace_buf); - return; - } - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8821C_1ANT_MAX) - rsp_source = BT_INFO_SRC_8821C_1ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; - coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; - coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; - - if (BT_INFO_SRC_8821C_1ANT_WIFI_FW != rsp_source) { - - /* if 0xff, it means BT is under WHCK test */ - coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true : - false); - - coex_sta->bt_create_connection = (( - coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true : - false); - - /* unit: %, value-100 to translate to unit: dBm */ - coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + - 10; - - coex_sta->c2h_bt_remote_name_req = (( - coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true : - false); - - coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & - 0x10) ? true : false); - - coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & - 0x9) ? true : false); - - coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? - true : false); - - coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & - BT_INFO_8821C_1ANT_B_INQ_PAGE) ? true : false); - - coex_sta->a2dp_bit_pool = ((( - coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? - coex_sta->bt_info_c2h[rsp_source][6] : 0); - - coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & - 0xf; - - coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; - - coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; - - coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; - - coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->c2h_bt_remote_name_req) - coex_sta->cnt_RemoteNameReq++; - - if (coex_sta->bt_info_ext & BIT(1)) - coex_sta->cnt_ReInit++; - - if (coex_sta->bt_info_ext & BIT(2)) { - coex_sta->cnt_setupLink++; - coex_sta->is_setupLink = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Re-Link start in BT info!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_sta->is_setupLink = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Re-Link stop in BT info!!\n"); - BTC_TRACE(trace_buf); - } - - if (coex_sta->bt_info_ext & BIT(3)) - coex_sta->cnt_IgnWlanAct++; - - if (coex_sta->bt_info_ext & BIT(6)) - coex_sta->cnt_RoleSwitch++; - - if (coex_sta->bt_create_connection) { - coex_sta->cnt_Page++; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, - &wifi_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); - - if ((wifi_link) || (wifi_roam) || (wifi_scan) || - (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { - - is_scoreboard_scan = true; - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_SCAN, true); - - } else - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_SCAN, false); - - } else { - if (is_scoreboard_scan) { - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_SCAN, false); - is_scoreboard_scan = false; - } - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - - if ((!btcoexist->manual_control) && - (!btcoexist->stop_coex_dm)) { - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* Re-Init */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - if (wifi_connected) - halbtc8821c1ant_update_wifi_channel_info( - btcoexist, BTC_MEDIA_CONNECT); - else - halbtc8821c1ant_update_wifi_channel_info( - btcoexist, - BTC_MEDIA_DISCONNECT); - } - - /* If Ignore_WLanAct && not SetUp_Link */ - if ((coex_sta->bt_info_ext & BIT(3)) && - (!(coex_sta->bt_info_ext & BIT(2)))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8821c1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } - } - - } - - if ((coex_sta->bt_info_ext & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); - BTC_TRACE(trace_buf); - coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( - btcoexist); - - if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) - coex_sta->bt_ble_scan_para[0] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x1); - if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) - coex_sta->bt_ble_scan_para[1] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x2); - if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) - coex_sta->bt_ble_scan_para[2] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x4); - - } - - halbtc8821c1ant_update_bt_link_info(btcoexist); - - halbtc8821c1ant_run_coexist_mechanism(btcoexist); -} - - - -void ex_halbtc8821c1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; -#if 0 - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF, - true); -#endif - } else if (BTC_RF_OFF == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, - false); - - halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_WLAN_OFF); - - btcoexist->stop_coex_dm = true; - } -} - -void ex_halbtc8821c1ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, - false); - - halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_1ANT_PHASE_WLAN_OFF); - - halbtc8821c1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true); - - ex_halbtc8821c1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - btcoexist->stop_coex_dm = true; -} - -void ex_halbtc8821c1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - boolean wifi_under_5g = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if ((BTC_WIFI_PNP_SLEEP == pnp_state) || - (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, - false); - - if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { - - if (wifi_under_5g) - halbtc8821c1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_1ANT_PHASE_5G_RUNTIME); - else - halbtc8821c1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - } else { - - halbtc8821c1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_WLAN_OFF); - } - - btcoexist->stop_coex_dm = true; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); -#if 0 - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF, - true); -#endif - btcoexist->stop_coex_dm = false; - } -} - - -void ex_halbtc8821c1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], *****************Coex DM Reset*****************\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_init_hw_config(btcoexist, false, false); - halbtc8821c1ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8821c1ant_periodical(IN struct btc_coexist *btcoexist) -{ - - struct btc_board_info *board_info = &btcoexist->board_info; - boolean wifi_busy = false; - u16 bt_scoreboard_val = 0; - u32 bt_patch_ver; - static u8 cnt = 0; - boolean bt_relink_finish = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ************* Periodical *************\n"); - BTC_TRACE(trace_buf); - -#if (BT_AUTO_REPORT_ONLY_8821C_1ANT == 0) - halbtc8821c1ant_query_bt_info(btcoexist); - -#endif - - halbtc8821c1ant_monitor_bt_ctr(btcoexist); - halbtc8821c1ant_monitor_wifi_ctr(btcoexist); - - halbtc8821c1ant_monitor_bt_enable_disable(btcoexist); - -#if 0 - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* halbtc8821c1ant_read_score_board(btcoexist, &bt_scoreboard_val); */ - - if (wifi_busy) { - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, true); - /* - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_WLBUSY, true); - - if (bt_scoreboard_val & BIT(6)) - halbtc8821c1ant_query_bt_info(btcoexist); */ - } else { - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, false); - } -#endif - - if (coex_sta->bt_relink_downcount != 0) { - coex_sta->bt_relink_downcount--; - - if (coex_sta->bt_relink_downcount == 0) - bt_relink_finish = true; - } - - /* for 4-way, DHCP, EAPOL packet */ - if (coex_sta->specific_pkt_period_cnt > 0) { - - coex_sta->specific_pkt_period_cnt--; - - if ((coex_sta->specific_pkt_period_cnt == 0) && - (coex_sta->wifi_is_high_pri_task)) - coex_sta->wifi_is_high_pri_task = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ***************** Hi-Pri Task = %s\n", - (coex_sta->wifi_is_high_pri_task ? "Yes" : - "No")); - BTC_TRACE(trace_buf); - - } - - if (!coex_sta->bt_disabled) { - if (coex_sta->bt_coex_supported_feature == 0) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, - &coex_sta->bt_coex_supported_feature); - - if ((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, - &coex_sta->bt_coex_supported_version); - - if (coex_sta->bt_reg_vendor_ac == 0xffff) - coex_sta->bt_reg_vendor_ac = (u16)( - btcoexist->btc_get_bt_reg(btcoexist, 3, - 0xac) & 0xffff); - - if (coex_sta->bt_reg_vendor_ae == 0xffff) - coex_sta->bt_reg_vendor_ae = (u16)( - btcoexist->btc_get_bt_reg(btcoexist, 3, - 0xae) & 0xffff); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, - &bt_patch_ver); - btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; - - if (coex_sta->num_of_profile > 0) { - cnt++; - - if (cnt >= 3) { - btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, - &coex_sta->bt_afh_map[0]); - cnt = 0; - } - } - } - - if (halbtc8821c1ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish)) - halbtc8821c1ant_run_coexist_mechanism(btcoexist); - -} - -/*#pragma optimize( "", off )*/ -void ex_halbtc8821c1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - -} - - -void ex_halbtc8821c1ant_display_ant_detection(IN struct btc_coexist *btcoexist) -{ - -} - -void ex_halbtc8821c1ant_antenna_isolation(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - - -} - -void ex_halbtc8821c1ant_psd_scan(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - - -} - - -#endif - -#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ - - diff --git a/hal/btc/halbtc8821c1ant.h b/hal/btc/halbtc8821c1ant.h deleted file mode 100644 index 25752cd..0000000 --- a/hal/btc/halbtc8821c1ant.h +++ /dev/null @@ -1,497 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821C_SUPPORT == 1) - -/* ******************************************* - * The following is for 8821C 1ANT BT Co-exist definition - * ******************************************* */ -#define BT_8821C_1ANT_COEX_DBG 0 -#define BT_AUTO_REPORT_ONLY_8821C_1ANT 1 - -#define BT_INFO_8821C_1ANT_B_FTP BIT(7) -#define BT_INFO_8821C_1ANT_B_A2DP BIT(6) -#define BT_INFO_8821C_1ANT_B_HID BIT(5) -#define BT_INFO_8821C_1ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8821C_1ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8821C_1ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8821C_1ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8821C_1ANT_B_CONNECTION BIT(0) - -#define BT_INFO_8821C_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? true : false) - -#define BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT 2 - -#define BT_8821C_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ -#define BT_8821C_1ANT_DEFAULT_ISOLATION 15 /* unit: dB */ - - -/* for Antenna detection */ -#define BT_8821C_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 -#define BT_8821C_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 -#define BT_8821C_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 -#define BT_8821C_1ANT_ANTDET_PSDTHRES_1ANT 35 -#define BT_8821C_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8821C_1ANT_ANTDET_SWEEPPOINT_DELAY 60000 -#define BT_8821C_1ANT_ANTDET_ENABLE 0 -#define BT_8821C_1ANT_ANTDET_BTTXTIME 100 -#define BT_8821C_1ANT_ANTDET_BTTXCHANNEL 39 -#define BT_8821C_1ANT_ANTDET_PSD_SWWEEPCOUNT 50 - -#define BT_8821C_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 - -enum bt_8821c_1ant_signal_state { - BT_8821C_1ANT_SIG_STA_SET_TO_LOW = 0x0, - BT_8821C_1ANT_SIG_STA_SET_BY_HW = 0x0, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH = 0x1, - BT_8821C_1ANT_SIG_STA_MAX -}; - -enum bt_8821c_1ant_path_ctrl_owner { - BT_8821C_1ANT_PCO_BTSIDE = 0x0, - BT_8821C_1ANT_PCO_WLSIDE = 0x1, - BT_8821C_1ANT_PCO_MAX -}; - -enum bt_8821c_1ant_gnt_ctrl_type { - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW = 0x1, - BT_8821C_1ANT_GNT_TYPE_MAX -}; - -enum bt_8821c_1ant_gnt_ctrl_block { - BT_8821C_1ANT_GNT_BLOCK_RFC_BB = 0x0, - BT_8821C_1ANT_GNT_BLOCK_RFC = 0x1, - BT_8821C_1ANT_GNT_BLOCK_BB = 0x2, - BT_8821C_1ANT_GNT_BLOCK_MAX -}; - -enum bt_8821c_1ant_lte_coex_table_type { - BT_8821C_1ANT_CTT_WL_VS_LTE = 0x0, - BT_8821C_1ANT_CTT_BT_VS_LTE = 0x1, - BT_8821C_1ANT_CTT_MAX -}; - -enum bt_8821c_1ant_lte_break_table_type { - BT_8821C_1ANT_LBTT_WL_BREAK_LTE = 0x0, - BT_8821C_1ANT_LBTT_BT_BREAK_LTE = 0x1, - BT_8821C_1ANT_LBTT_LTE_BREAK_WL = 0x2, - BT_8821C_1ANT_LBTT_LTE_BREAK_BT = 0x3, - BT_8821C_1ANT_LBTT_MAX -}; - -enum bt_info_src_8821c_1ant { - BT_INFO_SRC_8821C_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8821C_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8821C_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8821C_1ANT_MAX -}; - -enum bt_8821c_1ant_bt_status { - BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8821C_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8821C_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8821C_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8821C_1ANT_BT_STATUS_MAX -}; - -enum bt_8821c_1ant_wifi_status { - BT_8821C_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8821C_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8821C_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8821C_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8821C_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8821C_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8821C_1ANT_WIFI_STATUS_MAX -}; - -enum bt_8821c_1ant_coex_algo { - BT_8821C_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8821C_1ANT_COEX_ALGO_SCO = 0x1, - BT_8821C_1ANT_COEX_ALGO_HID = 0x2, - BT_8821C_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8821C_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8821C_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8821C_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8821C_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8821C_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8821C_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8821C_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8821C_1ANT_COEX_ALGO_MAX = 0xb, -}; - -enum bt_8821c_1ant_ext_ant_switch_type { - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0, - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1, - BT_8821C_1ANT_EXT_ANT_SWITCH_NONE = 0x2, - BT_8821C_1ANT_EXT_ANT_SWITCH_MAX -}; - - -enum bt_8821c_1ant_ext_ant_switch_ctrl_type { - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_MAX -}; - -enum bt_8821c_1ant_ext_ant_switch_pos_type { - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_BT = 0x0, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLG = 0x1, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLA = 0x2, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE = 0x3, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_MAX -}; - -enum bt_8821c_1ant_ext_band_switch_pos_type { - BT_8821C_1ANT_EXT_BAND_SWITCH_TO_WLG = 0x0, - BT_8821C_1ANT_EXT_BAND_SWITCH_TO_WLA = 0x1, - BT_8821C_1ANT_EXT_BAND_SWITCH_TO_MAX -}; - -enum bt_8821c_1ant_int_block { - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_MAX -}; - -enum bt_8821c_1ant_phase { - BT_8821C_1ANT_PHASE_COEX_INIT = 0x0, - BT_8821C_1ANT_PHASE_WLANONLY_INIT = 0x1, - BT_8821C_1ANT_PHASE_WLAN_OFF = 0x2, - BT_8821C_1ANT_PHASE_2G_RUNTIME = 0x3, - BT_8821C_1ANT_PHASE_5G_RUNTIME = 0x4, - BT_8821C_1ANT_PHASE_BTMPMODE = 0x5, - BT_8821C_1ANT_PHASE_ANTENNA_DET = 0x6, - BT_8821C_1ANT_PHASE_COEX_POWERON = 0x7, - BT_8821C_1ANT_PHASE_MAX -}; - -enum bt_8821c_1ant_Scoreboard { - BT_8821C_1ANT_SCOREBOARD_ACTIVE = BIT(0), - BT_8821C_1ANT_SCOREBOARD_ONOFF = BIT(1), - BT_8821C_1ANT_SCOREBOARD_SCAN = BIT(2), - BT_8821C_1ANT_SCOREBOARD_UNDERTEST = BIT(3), - BT_8821C_1ANT_SCOREBOARD_WLBUSY = BIT(6) -}; - -struct coex_dm_8821c_1ant { - /* hw setting */ - u32 pre_ant_pos_type; - u32 cur_ant_pos_type; - /* fw mechanism */ - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - /* sw mechanism */ - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; - u32 arp_cnt; - - u32 pre_ext_ant_switch_status; - u32 cur_ext_ant_switch_status; - - u8 pre_ext_band_switch_status; - u8 cur_ext_band_switch_status; - - u8 pre_int_block_status; - u8 cur_int_block_status; - - u8 error_condition; -}; - -struct coex_sta_8821c_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - u8 num_of_profile; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - boolean is_hiPri_rx_overhead; - s8 bt_rssi; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - u8 bt_info_c2h[BT_INFO_SRC_8821C_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8821C_1ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_remote_name_req; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - - u8 bt_info_ext; - u8 bt_info_ext2; - u32 pop_event_cnt; - u8 scan_ap_num; - u8 bt_retry_cnt; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; - - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; - u8 coex_table_type; - - boolean force_lps_on; - - boolean concurrent_rx_mode_on; - - u16 score_board; - u8 isolation_btween_wb; /* 0~ 50 */ - - u8 a2dp_bit_pool; - u8 cut_version; - boolean acl_busy; - boolean bt_create_connection; - - u32 bt_coex_supported_feature; - u32 bt_coex_supported_version; - - u8 bt_ble_scan_type; - u32 bt_ble_scan_para[3]; - - boolean run_time_state; - boolean freeze_coexrun_by_btinfo; - - boolean is_A2DP_3M; - boolean voice_over_HOGP; - u8 bt_info; - boolean is_autoslot; - u8 forbidden_slot; - u8 hid_busy_num; - u8 hid_pair_cnt; - - u32 cnt_RemoteNameReq; - u32 cnt_setupLink; - u32 cnt_ReInit; - u32 cnt_IgnWlanAct; - u32 cnt_Page; - u32 cnt_RoleSwitch; - - u16 bt_reg_vendor_ac; - u16 bt_reg_vendor_ae; - - boolean is_setupLink; - u8 wl_noisy_level; - u32 gnt_error_cnt; - - u8 bt_afh_map[10]; - u8 bt_relink_downcount; - boolean is_tdma_btautoslot; - boolean is_tdma_btautoslot_hang; -}; - - -#define BT_8821C_1ANT_EXT_BAND_SWITCH_USE_DPDT 0 -#define BT_8821C_1ANT_EXT_BAND_SWITCH_USE_SPDT 1 - - -struct rfe_type_8821c_1ant { - - u8 rfe_module_type; - boolean ext_ant_switch_exist; - u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */ - u8 ext_ant_switch_ctrl_polarity; /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ - - boolean ext_band_switch_exist; - u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */ - u8 ext_band_switch_ctrl_polarity; - - boolean ant_at_main_port; - - boolean wlg_Locate_at_btg; /* If true: WLG at BTG, If false: WLG at WLAG */ - - boolean ext_ant_switch_diversity; /* If diversity on */ -}; - -#define BT_8821C_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ -#define BT_8821C_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ -#define BT_8821C_1ANT_ANTDET_BUF_LEN 16 - -struct psdscan_sta_8821c_1ant { - - u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ - u32 ant_det_bt_tx_time; - u32 ant_det_pre_psdscan_peak_val; - boolean ant_det_is_ant_det_available; - u32 ant_det_psd_scan_peak_val; - boolean ant_det_is_btreply_available; - u32 ant_det_psd_scan_peak_freq; - - u8 ant_det_result; - u8 ant_det_peak_val[BT_8821C_1ANT_ANTDET_BUF_LEN]; - u8 ant_det_peak_freq[BT_8821C_1ANT_ANTDET_BUF_LEN]; - u32 ant_det_try_count; - u32 ant_det_fail_count; - u32 ant_det_inteval_count; - u32 ant_det_thres_offset; - - u32 real_cent_freq; - s32 real_offset; - u32 real_span; - - u32 psd_band_width; /* unit: Hz */ - u32 psd_point; /* 128/256/512/1024 */ - u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_start_point; - u32 psd_stop_point; - u32 psd_max_value_point; - u32 psd_max_value; - u32 psd_max_value2; - u32 psd_avg_value; /* filter loop_max_value that below BT_8821C_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/ - u32 psd_loop_max_value[BT_8821C_1ANT_ANTDET_PSD_SWWEEPCOUNT]; /*max value in each loop */ - u32 psd_start_base; - u32 psd_avg_num; /* 1/8/16/32 */ - u32 psd_gen_count; - boolean is_AntDet_running; - boolean is_psd_show_max_only; -}; - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8821c1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8821c1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8821c1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8821c1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8821c1ant_antenna_isolation(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); - -void ex_halbtc8821c1ant_psd_scan(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8821c1ant_display_ant_detection(IN struct btc_coexist *btcoexist); - -#else -#define ex_halbtc8821c1ant_power_on_setting(btcoexist) -#define ex_halbtc8821c1ant_pre_load_firmware(btcoexist) -#define ex_halbtc8821c1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8821c1ant_init_coex_dm(btcoexist) -#define ex_halbtc8821c1ant_ips_notify(btcoexist, type) -#define ex_halbtc8821c1ant_lps_notify(btcoexist, type) -#define ex_halbtc8821c1ant_scan_notify(btcoexist, type) -#define ex_halbtc8821c1ant_switchband_notify(btcoexist,type) -#define ex_halbtc8821c1ant_connect_notify(btcoexist, type) -#define ex_halbtc8821c1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8821c1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8821c1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8821c1ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8821c1ant_halt_notify(btcoexist) -#define ex_halbtc8821c1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8821c1ant_coex_dm_reset(btcoexist) -#define ex_halbtc8821c1ant_periodical(btcoexist) -#define ex_halbtc8821c1ant_display_coex_info(btcoexist) -#define ex_halbtc8821c1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8821c1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8821c1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8821c1ant_display_ant_detection(btcoexist) -#endif - -#endif - - diff --git a/hal/btc/halbtc8821c2ant.c b/hal/btc/halbtc8821c2ant.c deleted file mode 100644 index aa550b4..0000000 --- a/hal/btc/halbtc8821c2ant.c +++ /dev/null @@ -1,5965 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -/* ************************************************************ - * Description: - * - * This file is for RTL8821C Co-exist mechanism - * - * History - * 2012/11/15 Cosa first check in. - * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821C_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ -static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8821c_2ant glcoex_dm_8821c_2ant; -static struct coex_dm_8821c_2ant *coex_dm = &glcoex_dm_8821c_2ant; -static struct coex_sta_8821c_2ant glcoex_sta_8821c_2ant; -static struct coex_sta_8821c_2ant *coex_sta = &glcoex_sta_8821c_2ant; -static struct psdscan_sta_8821c_2ant gl_psd_scan_8821c_2ant; -static struct psdscan_sta_8821c_2ant *psd_scan = &gl_psd_scan_8821c_2ant; -static struct rfe_type_8821c_2ant gl_rfe_type_8821c_2ant; -static struct rfe_type_8821c_2ant *rfe_type = &gl_rfe_type_8821c_2ant; - -const char *const glbt_info_src_8821c_2ant[] = { - "BT Info[wifi fw]", - "BT Info[bt rsp]", - "BT Info[bt auto report]", -}; - -u32 glcoex_ver_date_8821c_2ant = 20161107; -u32 glcoex_ver_8821c_2ant = 0x0a; -u32 glcoex_ver_btdesired_8821c_2ant = 0x0a; - - -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8821c2ant_ - * ************************************************************ */ -u8 halbtc8821c2ant_bt_rssi_state(u8 *ppre_bt_rssi_state, u8 level_num, - u8 rssi_thresh, u8 rssi_thresh1) -{ - s32 bt_rssi = 0; - u8 bt_rssi_state = *ppre_bt_rssi_state; - - bt_rssi = coex_sta->bt_rssi; - - if (level_num == 2) { - if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); - BTC_TRACE(trace_buf); - return *ppre_bt_rssi_state; - } - - if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (bt_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - if (bt_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) - bt_rssi_state = BTC_RSSI_STATE_HIGH; - else if (bt_rssi < rssi_thresh) - bt_rssi_state = BTC_RSSI_STATE_LOW; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (bt_rssi < rssi_thresh1) - bt_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - *ppre_bt_rssi_state = bt_rssi_state; - - return bt_rssi_state; -} - -u8 halbtc8821c2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh, - IN u8 rssi_thresh1) -{ - s32 wifi_rssi = 0; - u8 wifi_rssi_state = *pprewifi_rssi_state; - - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - - if (level_num == 2) { - if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || - (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else { - if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } else if (level_num == 3) { - if (rssi_thresh > rssi_thresh1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); - BTC_TRACE(trace_buf); - return *pprewifi_rssi_state; - } - - if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || - (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) || - (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) - wifi_rssi_state = BTC_RSSI_STATE_HIGH; - else if (wifi_rssi < rssi_thresh) - wifi_rssi_state = BTC_RSSI_STATE_LOW; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; - } else { - if (wifi_rssi < rssi_thresh1) - wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; - else - wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; - } - } - - *pprewifi_rssi_state = wifi_rssi_state; - - return wifi_rssi_state; -} - -void halbtc8821c2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist, - IN u8 isolation_measuared) -{ - s8 interference_wl_tx = 0, interference_bt_tx = 0; - - - interference_wl_tx = BT_8821C_2ANT_WIFI_MAX_TX_POWER - - isolation_measuared; - interference_bt_tx = BT_8821C_2ANT_BT_MAX_TX_POWER - - isolation_measuared; - - - - coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; - coex_sta->wifi_coex_thres2 = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES2; - - coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1; - coex_sta->bt_coex_thres2 = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES2; - - - /* - coex_sta->wifi_coex_thres = interference_wl_tx + BT_8821C_2ANT_WIFI_SIR_THRES1; - coex_sta->wifi_coex_thres2 = interference_wl_tx + BT_8821C_2ANT_WIFI_SIR_THRES2; - - coex_sta->bt_coex_thres = interference_bt_tx + BT_8821C_2ANT_BT_SIR_THRES1; - coex_sta->bt_coex_thres2 = interference_bt_tx + BT_8821C_2ANT_BT_SIR_THRES2; - */ - - - - - - /* - if ( BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - - BT_8821C_2ANT_DEFAULT_ISOLATION) ) - coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; - else - coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 - (isolation_measuared - - BT_8821C_2ANT_DEFAULT_ISOLATION); - - if ( BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - - BT_8821C_2ANT_DEFAULT_ISOLATION) ) - coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1; - else - coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 - (isolation_measuared - - BT_8821C_2ANT_DEFAULT_ISOLATION); - - */ -} - - -void halbtc8821c2ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) -{ - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); -} - -void halbtc8821c2ant_query_bt_info(IN struct btc_coexist *btcoexist) -{ - u8 h2c_parameter[1] = {0}; - - if (coex_sta->bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No query BT info because BT is disabled!\n"); - BTC_TRACE(trace_buf); - return; - } - - - h2c_parameter[0] |= BIT(0); /* trigger */ - - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); -} - -void halbtc8821c2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) -{ - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, - cnt_autoslot_hang = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - reg_hp_txrx = 0x770; - reg_lp_txrx = 0x774; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); - reg_hp_tx = u32tmp & MASKLWORD; - reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); - reg_lp_tx = u32tmp & MASKLWORD; - reg_lp_rx = (u32tmp & MASKHWORD) >> 16; - - coex_sta->high_priority_tx = reg_hp_tx; - coex_sta->high_priority_rx = reg_hp_rx; - coex_sta->low_priority_tx = reg_lp_tx; - coex_sta->low_priority_rx = reg_lp_rx; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", - reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); - - BTC_TRACE(trace_buf); - - if (BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - - if (coex_sta->high_priority_rx >= 15) { - if (cnt_overhead < 3) - cnt_overhead++; - - if (cnt_overhead == 3) - coex_sta->is_hiPri_rx_overhead = true; - - } else { - if (cnt_overhead > 0) - cnt_overhead--; - - if (cnt_overhead == 0) - coex_sta->is_hiPri_rx_overhead = false; - } - } - - /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); - - if ((coex_sta->low_priority_tx > 1150) && - (!coex_sta->c2h_bt_inquiry_page)) - coex_sta->pop_event_cnt++; - - if ((coex_sta->low_priority_rx >= 1150) && - (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) - && (!coex_sta->under_ips) - && (!coex_sta->c2h_bt_inquiry_page) - && ((bt_link_info->a2dp_exist) || (bt_link_info->pan_exist))) { - if (cnt_slave >= 2) { - bt_link_info->slave_role = true; - cnt_slave = 2; - } else - cnt_slave++; - } else { - if (cnt_slave == 0) { - bt_link_info->slave_role = false; - cnt_slave = 0; - } else - cnt_slave--; - } - - if (coex_sta->is_tdma_btautoslot) { - if ((coex_sta->low_priority_tx >= 1300) && - (coex_sta->low_priority_rx <= 150)) { - if (cnt_autoslot_hang >= 2) { - coex_sta->is_tdma_btautoslot_hang = true; - cnt_autoslot_hang = 2; - } else - cnt_autoslot_hang++; - } else { - if (cnt_autoslot_hang == 0) { - coex_sta->is_tdma_btautoslot_hang = false; - cnt_autoslot_hang = 0; - } else - cnt_autoslot_hang--; - } - } - - if (!coex_sta->bt_disabled) { - - if ((coex_sta->high_priority_tx == 0) && - (coex_sta->high_priority_rx == 0) && - (coex_sta->low_priority_tx == 0) && - (coex_sta->low_priority_rx == 0)) { - num_of_bt_counter_chk++; - if (num_of_bt_counter_chk >= 3) { - halbtc8821c2ant_query_bt_info(btcoexist); - num_of_bt_counter_chk = 0; - } - } - } - -} - - -void halbtc8821c2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ -#if 1 - s32 wifi_rssi = 0; - boolean wifi_busy = false, wifi_under_b_mode = false, - wifi_scan = false; - boolean bt_idle = false, wl_idle = false; - static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, - wl_noisy_count1 = 3, wl_noisy_count2 = 0; - u32 total_cnt, reg_val1, reg_val2, cck_cnt; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - - coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_VHT); - - cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; - - if ((coex_dm->bt_status == - BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE) || - (coex_dm->bt_status == - BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE) || - (coex_sta->bt_disabled)) - bt_idle = true; - - if (cck_cnt > 250) { - if (wl_noisy_count2 < 3) - wl_noisy_count2++; - - if (wl_noisy_count2 == 3) { - wl_noisy_count0 = 0; - wl_noisy_count1 = 0; - } - - } else if (cck_cnt < 50) { - if (wl_noisy_count0 < 3) - wl_noisy_count0++; - - if (wl_noisy_count0 == 3) { - wl_noisy_count1 = 0; - wl_noisy_count2 = 0; - } - - } else { - if (wl_noisy_count1 < 3) - wl_noisy_count1++; - - if (wl_noisy_count1 == 3) { - wl_noisy_count0 = 0; - wl_noisy_count2 = 0; - } - } - - if (wl_noisy_count2 == 3) - coex_sta->wl_noisy_level = 2; - else if (wl_noisy_count1 == 3) - coex_sta->wl_noisy_level = 1; - else - coex_sta->wl_noisy_level = 0; - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g - + coex_sta->crc_ok_11n - + coex_sta->crc_ok_11n_vht; - - if ((coex_dm->bt_status == - BT_8821C_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == - BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == - BT_8821C_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 3) - coex_sta->cck_lock = true; - else - coex_sta->cck_lock = false; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = false; - else - coex_sta->cck_lock = true; - } - - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = true; - - coex_sta->pre_ccklock = coex_sta->cck_lock; - -#endif -} - -void halbtc8821c2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - boolean bt_busy = false; - - coex_sta->num_of_profile = 0; - - /* set link exist status */ - if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = false; - coex_sta->pan_exist = false; - coex_sta->a2dp_exist = false; - coex_sta->hid_exist = false; - coex_sta->sco_exist = false; - } else { /* connection exists */ - coex_sta->bt_link_exist = true; - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_FTP) { - coex_sta->pan_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = false; - - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_A2DP) { - coex_sta->a2dp_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = false; - - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_HID) { - coex_sta->hid_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = false; - - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) { - coex_sta->sco_exist = true; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = false; - - } - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->acl_busy = coex_sta->acl_busy; - - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = true; - bt_link_info->bt_link_exist = true; - } - - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = true; - else - bt_link_info->sco_only = false; - - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = true; - else - bt_link_info->a2dp_only = false; - - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = true; - else - bt_link_info->pan_only = false; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = true; - else - bt_link_info->hid_only = false; - - if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_INQ_PAGE) { - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_INQ_PAGE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); - } else if (!(coex_sta->bt_info & BT_INFO_8821C_2ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - } else if (coex_sta->bt_info == BT_INFO_8821C_2ANT_B_CONNECTION) { - /* connection exists but no busy */ - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - } else if (((coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_ESCO) || - (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_BUSY)) && - (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_ACL_BUSY)) { - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_ACL_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); - } else if ((coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_ESCO) || - (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - } else if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - } else { - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - } - - BTC_TRACE(trace_buf); - - if ((BT_8821C_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8821C_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821C_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = true; - else - bt_busy = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); -} - -void halbtc8821c2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = - 0x1; /* enable BT AFH skip WL channel for 8821c because BT Rx LO interference */ - /* h2c_parameter[0] = 0x0; */ - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); - -} - -void halbtc8821c2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - -void halbtc8821c2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8821c2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - -void halbtc8821c2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN u8 dec_bt_pwr_lvl) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = dec_bt_pwr_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); -} - -void halbtc8821c2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 dec_bt_pwr_lvl) -{ - coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; - - if (!force_exec) { - if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) - return; - } - halbtc8821c2ant_set_fw_dec_bt_pwr(btcoexist, - coex_dm->cur_bt_dec_pwr_lvl); - - coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; -} - - -void halbtc8821c2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ - -#if 1 - coex_dm->cur_low_penalty_ra = low_penalty_ra; - - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == - coex_dm->cur_low_penalty_ra) - return; - } - - if (low_penalty_ra) - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15); - else - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; - -#endif - -} - - -void halbtc8821c2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = 0; - - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); - - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} - -void halbtc8821c2ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; - - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8821c2ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8821c2ant_write_score_board( - IN struct btc_coexist *btcoexist, - IN u16 bitpos, - IN boolean state -) -{ - - static u16 originalval = 0x8002; - - if (state) - originalval = originalval | bitpos; - else - originalval = originalval & (~bitpos); - - - btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); - -} - -void halbtc8821c2ant_read_score_board( - IN struct btc_coexist *btcoexist, - IN u16 *score_board_val -) -{ - - *score_board_val = (btcoexist->btc_read_2byte(btcoexist, - 0xaa)) & 0x7fff; -} - - -void halbtc8821c2ant_post_state_to_bt( - IN struct btc_coexist *btcoexist, - IN u16 type, - IN boolean state -) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c2ant_post_state_to_bt: type = %d, state =%d\n", - type, state); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_write_score_board(btcoexist, (u16) type, state); -} - - -boolean halbtc8821c2ant_is_wifibt_status_changed(IN struct btc_coexist - *btcoexist) -{ - static boolean pre_wifi_busy = false, pre_under_4way = false, - pre_bt_hs_on = false, pre_bt_off = false, - pre_bt_slave = false; - static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0; - boolean wifi_busy = false, under_4way = false, bt_hs_on = false; - boolean wifi_connected = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (coex_sta->bt_disabled != pre_bt_off) { - pre_bt_off = coex_sta->bt_disabled; - - if (coex_sta->bt_disabled) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - - BTC_TRACE(trace_buf); - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - coex_sta->bt_ble_scan_type = 0; - coex_sta->bt_ble_scan_para[0] = 0; - coex_sta->bt_ble_scan_para[1] = 0; - coex_sta->bt_ble_scan_para[2] = 0; - coex_sta->bt_reg_vendor_ac = 0xffff; - coex_sta->bt_reg_vendor_ae = 0xffff; - return true; - } - - - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; - - if (wifi_busy) - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, true); - else - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, false); - return true; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return true; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return true; - } - if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { - pre_wl_noisy_level = coex_sta->wl_noisy_level; - return true; - } - } - - if (!coex_sta->bt_disabled) { - if (coex_sta->hid_busy_num != pre_hid_busy_num) { - pre_hid_busy_num = coex_sta->hid_busy_num; - return true; - } - } - - if (bt_link_info->slave_role != pre_bt_slave) { - pre_bt_slave = bt_link_info->slave_role; - return true; - } - - return false; -} - -void halbtc8821c2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) -{ - static u32 bt_disable_cnt = 0; - boolean bt_active = true, bt_disabled = false, wifi_under_5g = false; - u16 u16tmp; - - /* This function check if bt is disabled */ -#if 0 - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = false; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = false; - - -#else - - /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */ - halbtc8821c2ant_read_score_board(btcoexist, &u16tmp); - - bt_active = u16tmp & BIT(1); - - -#endif - - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } else { - - bt_disable_cnt++; - if (bt_disable_cnt >= 10) { - bt_disabled = true; - bt_disable_cnt = 10; - } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if ((wifi_under_5g) || (bt_disabled)) - halbtc8821c2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); - else - halbtc8821c2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true); - - - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - } - -} - -void halbtc8821c2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, - boolean isenable) -{ -#if BT_8821C_2ANT_COEX_DBG - static u8 bitVal[5] = {0, 0, 0, 0, 0}; - static boolean state = false; - /* - if (state ==isenable) - return; - else - state = isenable; - */ - if (isenable) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], enable_gnt_to_gpio!!\n"); - BTC_TRACE(trace_buf); - - /* enable GNT_WL, GNT_BT to GPIO for debug */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); - - /* store original value */ - bitVal[0] = (btcoexist->btc_read_1byte(btcoexist, - 0x66) & BIT(4)) >> 4; /*0x66[4] */ - bitVal[1] = (btcoexist->btc_read_1byte(btcoexist, - 0x67) & BIT(0)); /*0x66[8] */ - bitVal[2] = (btcoexist->btc_read_1byte(btcoexist, - 0x42) & BIT(3)) >> 3; /*0x40[19] */ - bitVal[3] = (btcoexist->btc_read_1byte(btcoexist, - 0x65) & BIT(7)) >> 7; /*0x64[15] */ - bitVal[4] = (btcoexist->btc_read_1byte(btcoexist, - 0x72) & BIT(2)) >> 2; /*0x70[18] */ - - /* switch GPIO Mux */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), - 0x0); /*0x66[4] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), - 0x0); /*0x66[8] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), - 0x0); /*0x40[19] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), - 0x0); /*0x64[15] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), - 0x0); /*0x70[18] = 0 */ - - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], disable_gnt_to_gpio!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); - - /* Restore original value */ - /* switch GPIO Mux */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), - bitVal[0]); /*0x66[4] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), - bitVal[1]); /*0x66[8] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), - bitVal[2]); /*0x40[19] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), - bitVal[3]); /*0x64[15] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), - bitVal[4]); /*0x70[18] = 0 */ - } - -#endif -} - -u32 halbtc8821c2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, - IN u16 reg_addr) -{ - u32 j = 0; - - - /* wait for ready bit before access 0x1700 */ - btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr); - - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x1703)&BIT(5)) == 0) && - (j < BT_8821C_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - return btcoexist->btc_read_4byte(btcoexist, - 0x1708); /* get read data */ - -} - -void halbtc8821c2ant_ltecoex_indirect_write_reg(IN struct btc_coexist - *btcoexist, - IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) -{ - u32 val, i = 0, j = 0, bitpos = 0; - - - if (bit_mask == 0x0) - return; - if (bit_mask == 0xffffffff) { - btcoexist->btc_write_4byte(btcoexist, 0x1704, - reg_value); /* put write data */ - - /* wait for ready bit before access 0x1700 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x1703)&BIT(5)) == 0) && - (j < BT_8821C_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x1700, - 0xc00F0000 | reg_addr); - } else { - for (i = 0; i <= 31; i++) { - if (((bit_mask >> i) & 0x1) == 0x1) { - bitpos = i; - break; - } - } - - /* read back register value before write */ - val = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - reg_addr); - val = (val & (~bit_mask)) | (reg_value << bitpos); - - btcoexist->btc_write_4byte(btcoexist, 0x1704, - val); /* put write data */ - - /* wait for ready bit before access 0x7c0 */ - do { - j++; - } while (((btcoexist->btc_read_1byte(btcoexist, - 0x1703)&BIT(5)) == 0) && - (j < BT_8821C_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT)); - - - btcoexist->btc_write_4byte(btcoexist, 0x1700, - 0xc00F0000 | reg_addr); - - } - -} - -void halbtc8821c2ant_ltecoex_enable(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 val; - - val = (enable) ? 1 : 0; - halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, - val); /* 0x38[7] */ - -} - -void halbtc8821c2ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, - IN boolean wifi_control) -{ - u8 val; - - val = (wifi_control) ? 1 : 0; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, - val); /* 0x70[26] */ - -} - -void halbtc8821c2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, val_orig = 0; - - if (!sw_control) - val = 0x0; - else if (state & 0x1) - val = 0x3; - else - val = 0x1; - - val_orig = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - switch (control_block) { - case BT_8821C_2ANT_GNT_BLOCK_RFC_BB: - default: - val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff); - break; - case BT_8821C_2ANT_GNT_BLOCK_RFC: - val = (val << 14) | (val_orig & 0xffff3fff); - break; - case BT_8821C_2ANT_GNT_BLOCK_BB: - val = (val << 10) | (val_orig & 0xfffff3ff); - break; - } - - halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); -} - -void halbtc8821c2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) -{ - u32 val = 0, val_orig = 0; - - if (!sw_control) - val = 0x0; - else if (state & 0x1) - val = 0x3; - else - val = 0x1; - - val_orig = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - switch (control_block) { - case BT_8821C_2ANT_GNT_BLOCK_RFC_BB: - default: - val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff); - break; - case BT_8821C_2ANT_GNT_BLOCK_RFC: - val = (val << 12) | (val_orig & 0xffffcfff); - break; - case BT_8821C_2ANT_GNT_BLOCK_BB: - val = (val << 8) | (val_orig & 0xfffffcff); - break; - } - - halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); -} - -void halbtc8821c2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u16 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8821C_2ANT_CTT_WL_VS_LTE: - reg_addr = 0xa0; - break; - case BT_8821C_2ANT_CTT_BT_VS_LTE: - reg_addr = 0xa4; - break; - } - - if (reg_addr != 0x0000) - halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ - - -} - - -void halbtc8821c2ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u8 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8821C_2ANT_LBTT_WL_BREAK_LTE: - reg_addr = 0xa8; - break; - case BT_8821C_2ANT_LBTT_BT_BREAK_LTE: - reg_addr = 0xac; - break; - case BT_8821C_2ANT_LBTT_LTE_BREAK_WL: - reg_addr = 0xb0; - break; - case BT_8821C_2ANT_LBTT_LTE_BREAK_BT: - reg_addr = 0xb4; - break; - } - - if (reg_addr != 0x0000) - halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ - - -} - -void halbtc8821c2ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 interval, - IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, - IN u8 val0x6c4_b3) -{ - static u8 pre_h2c_parameter[6] = {0}; - u8 cur_h2c_parameter[6] = {0}; - u8 i, match_cnt = 0; - - cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ - - cur_h2c_parameter[1] = interval; - cur_h2c_parameter[2] = val0x6c4_b0; - cur_h2c_parameter[3] = val0x6c4_b1; - cur_h2c_parameter[4] = val0x6c4_b2; - cur_h2c_parameter[5] = val0x6c4_b3; - - if (!force_exec) { - for (i = 1; i <= 5; i++) { - if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) - break; - - match_cnt++; - } - - if (match_cnt == 5) - return; - } - - for (i = 1; i <= 5; i++) - pre_h2c_parameter[i] = cur_h2c_parameter[i]; - - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); -} - - - -void halbtc8821c2ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) -{ - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); - - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); - - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} - -void halbtc8821c2ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ - coex_dm->cur_val0x6c0 = val0x6c0; - coex_dm->cur_val0x6c4 = val0x6c4; - coex_dm->cur_val0x6c8 = val0x6c8; - coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8821c2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; -} - -void halbtc8821c2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - u32 break_table; - u8 select_table; - - coex_sta->coex_table_type = type; - - if (coex_sta->concurrent_rx_mode_on == true) { - break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ - select_table = - 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ - } else { - break_table = 0xffffff; - select_table = 0x3; - } - - switch (type) { - case 0: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0xffffffff, 0xffffffff, break_table, select_table); - break; - case 1: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, select_table); - break; - case 2: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table); - break; - case 3: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, select_table); - break; - case 4: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, select_table); - break; - case 5: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, break_table, select_table); - break; - case 6: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xfafafafa, break_table, select_table); - break; - case 7: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xaa5a5a5a, break_table, select_table); - break; - case 8: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xfafafafa, break_table, select_table); - break; - case 9: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaaaa5aaa, break_table, select_table); - break; - default: - break; - } -} - -void halbtc8821c2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) -{ - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} - -void halbtc8821c2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; - - if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) - return; - } - halbtc8821c2ant_set_fw_ignore_wlan_act(btcoexist, enable); - - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} - -void halbtc8821c2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; - - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} - -void halbtc8821c2ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; - - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; - } - halbtc8821c2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; -} - -void halbtc8821c2ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) -{ - u8 lps_mode = 0x0; - u8 h2c_parameter[5] = {0, 0, 0, 0x40, 0}; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); - - if (lps_mode) { /* already under LPS state */ - if (new_ps_state) { - /* keep state under LPS, do nothing. */ - } else { - /* will leave LPS state, turn off psTdma first */ - /*halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } - } else { /* NO PS state */ - if (new_ps_state) { - /* will enter LPS state, turn off psTdma first */ - /*halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, - 8);*/ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); - } else { - /* keep state under NO PS state, do nothing. */ - } - } -} - -void halbtc8821c2ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) -{ - boolean low_pwr_disable = false; - - switch (ps_type) { - case BTC_PS_WIFI_NATIVE: - /* recover to original 32k low power setting */ - low_pwr_disable = false; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - case BTC_PS_LPS_ON: - halbtc8821c2ant_ps_tdma_check_for_power_save_state( - btcoexist, true); - halbtc8821c2ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); - /* when coex force to enter LPS, do not enter 32k low power. */ - low_pwr_disable = true; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - coex_sta->force_lps_on = true; - break; - case BTC_PS_LPS_OFF: - halbtc8821c2ant_ps_tdma_check_for_power_save_state( - btcoexist, false); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - coex_sta->force_lps_on = false; - break; - default: - break; - } -} - - - -void halbtc8821c2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) -{ - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - if (byte5 & BIT(2)) - coex_sta->is_tdma_btautoslot = true; - else - coex_sta->is_tdma_btautoslot = false; - - /* release bt-auto slot for auto-slot hang is detected!! */ - if (coex_sta->is_tdma_btautoslot) - if ((coex_sta->is_tdma_btautoslot_hang) || - (bt_link_info->slave_role)) - byte5 = byte5 & 0xfb; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - - if (ap_enable) { - if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], FW for AP mode\n"); - BTC_TRACE(trace_buf); - real_byte1 &= ~BIT(4); - real_byte1 |= BIT(5); - - real_byte5 |= BIT(5); - real_byte5 &= ~BIT(6); - - halbtc8821c2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, - 0x0); - } - } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - - halbtc8821c2ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); - } else { - halbtc8821c2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, - 0x0); - } - - - h2c_parameter[0] = real_byte1; - h2c_parameter[1] = byte2; - h2c_parameter[2] = byte3; - h2c_parameter[3] = byte4; - h2c_parameter[4] = real_byte5; - - coex_dm->ps_tdma_para[0] = real_byte1; - coex_dm->ps_tdma_para[1] = byte2; - coex_dm->ps_tdma_para[2] = byte3; - coex_dm->ps_tdma_para[3] = byte4; - coex_dm->ps_tdma_para[4] = real_byte5; - - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); -} - -void halbtc8821c2ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) -{ - static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; - - /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - if (bt_link_info->slave_role) - psTdmaByte4Modify = 0x1; - else - psTdmaByte4Modify = 0x0; - - if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { - force_exec = true; - pre_psTdmaByte4Modify = psTdmaByte4Modify; - } - - if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n", - (coex_dm->cur_ps_tdma_on ? "on" : "off"), - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - return; - } - } - - if (coex_dm->cur_ps_tdma_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - } - - - if (turn_on) { - switch (type) { - case 1: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x91, - 0x54 | psTdmaByte4Modify); - break; - case 2: - default: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, - 0x11 | psTdmaByte4Modify); - break; - case 3: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x3a, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); - break; - case 4: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x21, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); - break; - case 5: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); - break; - case 6: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); - break; - case 7: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); - break; - case 8: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x15, 0x03, 0x11, - 0x11); - break; - case 10: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x30, 0x03, 0x11, - 0x10); - break; - case 11: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, - 0x10 | psTdmaByte4Modify); - break; - case 12: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, 0x11); - break; - case 13: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x1c, 0x03, 0x11, - 0x10 | psTdmaByte4Modify); - break; - case 14: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x03, 0x11, - 0x11); - break; - case 15: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x11, - 0x14); - break; - case 16: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x11, - 0x15); - break; - case 21: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x30, 0x03, 0x11, - 0x10); - break; - case 22: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, - 0x10); - break; - case 23: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x11, - 0x10); - break; - case 51: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x91, - 0x10 | psTdmaByte4Modify); - break; - case 101: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x10, 0x03, 0x10, - 0x54 | psTdmaByte4Modify); - break; - case 102: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, - 0x11 | psTdmaByte4Modify); - break; - case 103: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x3a, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 104: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x21, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 105: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x25, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 106: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x10, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 107: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x20, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 108: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 109: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x55, - 0x10, 0x03, 0x10, - 0x54 | psTdmaByte4Modify); - break; - case 110: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x55, - 0x30, 0x03, 0x10, - 0x50 | psTdmaByte4Modify); - break; - case 111: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x65, - 0x25, 0x03, 0x11, - 0x11 | psTdmaByte4Modify); - break; - case 151: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x10, 0x03, 0x10, - 0x50 | psTdmaByte4Modify); - break; - } - } else { - /* disable PS tdma */ - switch (type) { - case 0: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - case 1: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); - break; - default: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); - break; - } - } - - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; -} - -void halbtc8821c2ant_set_int_block(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 pos_type) -{ -#if 0 - u8 regval_0xcba; - u32 u32tmp1 = 0; - - coex_dm->cur_int_block_status = pos_type; - - if (!force_exec) { - if (coex_dm->pre_int_block_status == - coex_dm->cur_int_block_status) - return; - } - - coex_dm->pre_int_block_status = coex_dm->cur_int_block_status; - - regval_0xcba = btcoexist->btc_read_1byte(btcoexist, 0xcba); - - switch (pos_type) { - - case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG: - regval_0xcba = (regval_0xcba | BIT(0)) & (~(BIT( - 2))); /* 0xcb8[16] = 1, 0xcb8[18] = 0, WL_G select BTG */ - regval_0xcba = regval_0xcba & 0x0f; - - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc1d, 0x0f, 0x5); */ /* Gain Table */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xa9e, 0x0f, 0x2); */ /* CCK Gain Table */ - - break; - case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG: - regval_0xcba = regval_0xcba & (~(BIT(2) | BIT( - 0))); /* 0xcb8[16] = 0, 0xcb8[18] = 0, WL_G select WLAG */ - - /* regval_0xcba = regval_0xcba | BIT(4) | BIT(5) ; */ /* 0xcb8[21:20] = 2b'11, WL_G @ WLAG on */ - /* regval_0xcba = (regval_0xcba | BIT(6)) & (~(BIT(7)) ) ; */ /* 0xcb8[23:22] = 2b'01, WL_A @ WLAG off */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc1d, 0x0f, 0x0); */ /* Gain Table */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xa9e, 0x0f, 0x6); */ /* CCK Gain Table */ - - break; - case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG: - regval_0xcba = regval_0xcba & (~(BIT(2) | BIT( - 0))); /* 0xcb8[16] = 0, 0xcb8[18] = 0, WL_G select WLAG */ - /*regval_0xcba = (regval_0xcba | BIT(4)) & (~(BIT(5))); */ /* 0xcb8[21:20] = 2b'01, WL_G @ WLAG off */ - /*regval_0xcba = regval_0xcba | BIT(6) | BIT(7); */ /* 0xcb8[23:22] = 2b'11, WL_A @ WLAG on */ - - break; - } - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcba, 0xff, - regval_0xcba); - - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Int Block setup) 0xcb8 = 0x%08x **********\n", - u32tmp1); - BTC_TRACE(trace_buf); - -#endif -} - -void halbtc8821c2ant_set_ext_band_switch(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 pos_type) -{ - -#if 0 - boolean switch_polatiry_inverse = false; - u8 regval_0xcb6; - u32 u32tmp1 = 0, u32tmp2 = 0; - - if (!rfe_type->ext_band_switch_exist) - return; - - coex_dm->cur_ext_band_switch_status = pos_type; - - if (!force_exec) { - if (coex_dm->pre_ext_band_switch_status == - coex_dm->cur_ext_band_switch_status) - return; - } - - coex_dm->pre_ext_band_switch_status = - coex_dm->cur_ext_band_switch_status; - - /* swap control polarity if use different switch control polarity*/ - switch_polatiry_inverse = (rfe_type->ext_band_switch_ctrl_polarity == 1 - ? ~switch_polatiry_inverse : switch_polatiry_inverse); - - /*swap control polarity for WL_A, default polarity 0xcb4[21] = 0 && 0xcb4[23] = 1 is for WL_G */ - switch_polatiry_inverse = (pos_type == - BT_8821C_2ANT_EXT_BAND_SWITCH_TO_WLA ? ~switch_polatiry_inverse - : switch_polatiry_inverse); - - regval_0xcb6 = btcoexist->btc_read_1byte(btcoexist, 0xcb6); - - /* for normal switch polrity, 0xcb4[21] =1 && 0xcb4[23] = 0 for WL_A, vice versa */ - regval_0xcb6 = (switch_polatiry_inverse == 1 ? ((regval_0xcb6 & (~(BIT( - 7)))) | BIT(5)) : ((regval_0xcb6 & (~(BIT(5)))) | BIT(7))); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb6, 0xff, - regval_0xcb6); - - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb0); - u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ext Band switch setup) 0xcb0 = 0x%08x, 0xcb4 = 0x%08x**********\n", - u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif - -} - -void halbtc8821c2ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - boolean switch_polatiry_inverse = false; - u8 regval_0xcb7 = 0, regval_0x64; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - - if (!rfe_type->ext_ant_switch_exist) - return; - - coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; - - if (!force_exec) { - if (coex_dm->pre_ext_ant_switch_status == - coex_dm->cur_ext_ant_switch_status) - return; - } - - coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status; - - /* swap control polarity if use different switch control polarity*/ - /* Normal switch polarity for DPDT, 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main */ - /* Normal switch polarity for SPDT, 0xcb4[29:28] = 2b'01 => Ant to BTG, 0xcb4[29:28] = 2b'10 => Ant to WLG */ - if (rfe_type->ext_ant_switch_ctrl_polarity) - switch_polatiry_inverse = ~switch_polatiry_inverse; - - /* swap control polarity if 1-Ant at Aux */ - if (rfe_type->ant_at_main_port == false) - switch_polatiry_inverse = ~switch_polatiry_inverse; - - switch (pos_type) { - default: - case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT: - case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE: - case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA: - - break; - case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG: - if (!rfe_type->wlg_Locate_at_btg) - switch_polatiry_inverse = ~switch_polatiry_inverse; - - break; - } - - if (board_info->ant_div_cfg) - ctrl_type = BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; - - - switch (ctrl_type) { - default: - case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x77); /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ - - regval_0xcb7 = (switch_polatiry_inverse == false ? - 0x1 : 0x2); /* 0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, regval_0xcb7); - - break; - case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x66); /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ - - regval_0xcb7 = (switch_polatiry_inverse == false ? - 0x2 : 0x1); /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, regval_0xcb7); - - break; - case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x88); /* */ - - /* no regval_0xcb7 setup required, because antenna switch control value by antenna diversity */ - - break; - case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x1); /* 0x4c[23] = 1 */ - - regval_0x64 = (switch_polatiry_inverse == false ? 0x0 : - 0x1); /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, - regval_0x64); - break; - case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x0); /* 0x4c[24] = 0 */ - - /* no setup required, because antenna switch control value by BT vendor 0x1c[1:0] */ - break; - } - - /* PAPE, LNA_ON control by BT while WLAN off for current leakage issue */ - if (ctrl_type == BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT) { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x0); /* PAPE 0x64[29] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, - 0x0); /* LNA_ON 0x64[28] = 0 */ - } else { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x1); /* PAPE 0x64[29] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, - 0x1); /* LNA_ON 0x64[28] = 1 */ - } - -#if BT_8821C_2ANT_COEX_DBG - - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (After Ext Ant switch setup) 0xcb4 = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n", - u32tmp1, u32tmp2, u32tmp3); - BTC_TRACE(trace_buf); -#endif - -} - -void halbtc8821c2ant_set_rfe_type(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - - - /* the following setup should be got from Efuse in the future */ - rfe_type->rfe_module_type = board_info->rfe_type & 0x1f; - - rfe_type->ext_ant_switch_ctrl_polarity = 0; - - switch (rfe_type->rfe_module_type) { - case 0: - default: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; /*2-Ant, DPDT, WLG*/ - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = true; - break; - case 1: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, WLG */ - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = true; - break; - case 2: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, BTG */ - rfe_type->wlg_Locate_at_btg = true; - rfe_type->ant_at_main_port = true; - break; - case 3: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, WLG */ - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = false; - break; - case 4: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, BTG */ - rfe_type->wlg_Locate_at_btg = true; - rfe_type->ant_at_main_port = false; - break; - case 5: - rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_NONE; - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = true; - break; - case 6: - rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_NONE; - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = true; - break; - case 7: - rfe_type->ext_ant_switch_exist = true; /*2-Ant, DPDT, BTG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; - rfe_type->wlg_Locate_at_btg = true; - rfe_type->ant_at_main_port = true; - break; - } - -#if 0 - if (rfe_type->wlg_Locate_at_btg) - halbtc8821c2ant_set_int_block(btcoexist, FORCE_EXEC, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); - else - halbtc8821c2ant_set_int_block(btcoexist, FORCE_EXEC, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); -#endif - -} - - -void halbtc8821c2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, - IN u8 phase) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u32 cnt_bt_cal_chk = 0; - boolean is_in_mp_mode = false; - u8 u8tmp = 0; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - u16 u16tmp1 = 0; - - u32tmp1 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - /* To avoid indirect access fail */ - if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { - force_exec = true; - coex_sta->gnt_error_cnt++; - } - - -#if BT_8821C_2ANT_COEX_DBG - - u32tmp2 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0x54); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", - u32tmp3, u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif - - coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; - - if (!force_exec) { - if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) - return; - } - - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; - - - switch (phase) { - case BT_8821C_2ANT_PHASE_COEX_POWERON: - - /* set Path control owner to WL at initial step */ - halbtc8821c2ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8821C_2ANT_PCO_BTSIDE); - - /* set GNT_BT to SW high */ - halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW high */ - halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; - else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; - } - - coex_sta->run_time_state = false; - - break; - case BT_8821C_2ANT_PHASE_COEX_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c2ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_2ANT_CTT_WL_VS_LTE, - 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c2ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_2ANT_CTT_BT_VS_LTE, - 0xffff); - - - /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ - while (cnt_bt_cal_chk <= 20) { - u8tmp = btcoexist->btc_read_1byte( - btcoexist, 0x49c); - cnt_bt_cal_chk++; - - if (u8tmp & BIT(1)) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - delay_ms(50); - } else { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - break; - } - } - - /* set Path control owner to WL at initial step */ - halbtc8821c2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_2ANT_PCO_WLSIDE); - - /* set GNT_BT to SW high */ - halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW high */ - halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); - - coex_sta->run_time_state = false; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; - else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; - } - - break; - case BT_8821C_2ANT_PHASE_WLANONLY_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c2ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_2ANT_CTT_WL_VS_LTE, - 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c2ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_2ANT_CTT_BT_VS_LTE, - 0xffff); - - /* set Path control owner to WL at initial step */ - halbtc8821c2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_2ANT_PCO_WLSIDE); - - /* set GNT_BT to SW Low */ - halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_LOW); - /* Set GNT_WL to SW high */ - halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); - - coex_sta->run_time_state = false; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; - else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; - } - - break; - case BT_8821C_2ANT_PHASE_WLAN_OFF: - /* Disable LTE Coex Function in WiFi side */ - halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); - - /* set Path control owner to BT */ - halbtc8821c2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_2ANT_PCO_BTSIDE); - - /* Set Ext Ant Switch to BT control at wifi off step */ - halbtc8821c2ant_set_ext_ant_switch(btcoexist, - FORCE_EXEC, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE); - coex_sta->run_time_state = false; - break; - case BT_8821C_2ANT_PHASE_2G_RUNTIME: - case BT_8821C_2ANT_PHASE_2G_RUNTIME_CONCURRENT: - - while (cnt_bt_cal_chk <= 20) { - /* 0x49c[0]=1 WL IQK, 0x49c[1]=1 BT IQK*/ - u8tmp = btcoexist->btc_read_1byte(btcoexist, - 0x49c); - - cnt_bt_cal_chk++; - if (u8tmp & BIT(0)) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### WL is IQK (wait cnt=%d)\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - delay_ms(50); - } else if (u8tmp & BIT(1)) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is IQK (wait cnt=%d)\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - delay_ms(50); - } else { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", - cnt_bt_cal_chk); - BTC_TRACE(trace_buf); - break; - } - } - - /* set Path control owner to WL at runtime step */ - halbtc8821c2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_2ANT_PCO_WLSIDE); - - if (phase == - BT_8821C_2ANT_PHASE_2G_RUNTIME_CONCURRENT) { - /* set GNT_BT to PTA */ - halbtc8821c2ant_ltecoex_set_gnt_bt( - btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_2ANT_SIG_STA_SET_BY_HW); - - /* Set GNT_WL to SW High */ - halbtc8821c2ant_ltecoex_set_gnt_wl( - btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); - } else { - /* set GNT_BT to PTA */ - halbtc8821c2ant_ltecoex_set_gnt_bt( - btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_2ANT_SIG_STA_SET_BY_HW); - - /* Set GNT_WL to PTA */ - halbtc8821c2ant_ltecoex_set_gnt_wl( - btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_2ANT_SIG_STA_SET_BY_HW); - } - coex_sta->run_time_state = true; - - if (rfe_type->wlg_Locate_at_btg) - halbtc8821c2ant_set_int_block(btcoexist, - NORMAL_EXEC, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); - else - halbtc8821c2ant_set_int_block(btcoexist, - NORMAL_EXEC, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; - else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; - } - - break; - case BT_8821C_2ANT_PHASE_5G_RUNTIME: - - /* set Path control owner to WL at runtime step */ - halbtc8821c2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_2ANT_PCO_WLSIDE); - - /* set GNT_BT to SW Hi */ - halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_2ANT_SIG_STA_SET_BY_HW); - - /* Set GNT_WL to SW Hi */ - halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); - - coex_sta->run_time_state = true; - - halbtc8821c2ant_set_int_block(btcoexist, - NORMAL_EXEC, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG); - - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; - else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; - } - - - break; - case BT_8821C_2ANT_PHASE_BTMPMODE: - /* Disable LTE Coex Function in WiFi side */ - halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); - - /* set Path control owner to WL */ - halbtc8821c2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_2ANT_PCO_WLSIDE); - - /* set GNT_BT to SW Hi */ - halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); - - /* Set GNT_WL to SW Lo */ - halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_LOW); - - coex_sta->run_time_state = false; - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; - else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; - } - - break; - case BT_8821C_2ANT_PHASE_ANTENNA_DET: - halbtc8821c2ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8821C_2ANT_PCO_WLSIDE); - - /* set GNT_BT to high */ - halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to high */ - halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (board_info->btdm_ant_pos == - BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; - else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; - } - - coex_sta->run_time_state = false; - - break; - } - - if (phase != BT_8821C_2ANT_PHASE_WLAN_OFF) { - switch (ant_pos_type) { - default: - case BTC_ANT_WIFI_AT_MAIN - : - halbtc8821c2ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG); - break; - case BTC_ANT_WIFI_AT_AUX - : - halbtc8821c2ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT); - break; - case BTC_ANT_WIFI_AT_DIVERSITY - : - halbtc8821c2ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE); - break; - } - - } - - - -#if BT_8821C_2ANT_COEX_DBG - u32tmp1 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (After Ant-Setup phase---%d) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", - phase, u32tmp3, u8tmp, u32tmp1, u32tmp2); - - BTC_TRACE(trace_buf); -#endif - -} - - -u8 halbtc8821c2ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = false; - u8 algorithm = BT_8821C_2ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; - } - - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; - - if (num_of_diff_profile == 0) { - - if (bt_link_info->acl_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No-Profile busy\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_NOPROFILEBUSY; - } - } else if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_SCO; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP ==> A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_HID_A2DP; - } - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP ==> HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } - - return algorithm; -} - - - -void halbtc8821c2ant_action_coex_all_off(IN struct btc_coexist *btcoexist) -{ - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* fw all off */ - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - -} - -void halbtc8821c2ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) -{ - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); -} - -void halbtc8821c2ant_action_bt_hs(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false, wifi_turbo = false; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - - } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } - -} - - -void halbtc8821c2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) -{ - - boolean wifi_connected = false; - boolean wifi_scan = false, wifi_link = false, wifi_roam = false; - boolean wifi_busy = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); - - if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) - || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 8); - - if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 15); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 11); - } else if ((!wifi_connected) && (!wifi_scan)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi no-link + no-scan + BT Inq/Page!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (bt_link_info->pan_exist) { - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - } else { - - if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) - || (coex_sta->wifi_is_high_pri_task)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - } - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); -} - - -void halbtc8821c2ant_action_bt_relink(IN struct btc_coexist *btcoexist) -{ - /*halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); */ - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - coex_sta->bt_relink_downcount = 2; -} - - -void halbtc8821c2ant_action_bt_idle(IN struct btc_coexist *btcoexist) -{ - - boolean wifi_busy = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_busy) { - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14); - } else { /* if wl busy */ - - if (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else { - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 8); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 12); - } - } - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - -} - - -/* SCO only or SCO+PAN(HS) */ -void halbtc8821c2ant_action_sco(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 1); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8); - } - -} - - -void halbtc8821c2ant_action_hid(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; - u32 wifi_bw = 1; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - /*for 4/18 hid */ - if (coex_sta->hid_busy_num >= 2) { - - if (wifi_bw == 0) { /* if 11bg mode */ - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8821c2ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 111); - } else { - - if (wifi_busy) { - halbtc8821c2ant_coex_table_with_type( - btcoexist, - NORMAL_EXEC, 8); - halbtc8821c2ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 111); - } else { - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 3); - halbtc8821c2ant_ps_tdma(btcoexist, - NORMAL_EXEC, true, 14); - } - } - } else { - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 3); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 14); - } - } - -} - -/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8821c2ant_action_a2dp(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false, wifi_turbo = false; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 1); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 16); - } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if ((coex_sta->bt_relink_downcount != 0) - && (wifi_busy)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - - } else { - - if (wifi_turbo) - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - else - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 7); - - if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 101); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 16); - /* halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 102); */ - } - - } - -} - -void halbtc8821c2ant_action_pan_edr(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false, wifi_turbo = false; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - -#if 0 - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); -#endif - - -#if 1 - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 3); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 4); - } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if (wifi_turbo) - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - else - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 7); - - if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 103); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 104); - - } - -#endif - -} - -void halbtc8821c2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; - u32 wifi_bw = 1; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 1); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 1); - } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if ((coex_sta->bt_relink_downcount != 0) - && (wifi_busy)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else if (wifi_busy) { - if (coex_sta->hid_busy_num >= 2) { - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - - if (wifi_bw == 0) /* 11bg mode */ - halbtc8821c2ant_set_wltoggle_coex_table( - btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - else - halbtc8821c2ant_set_wltoggle_coex_table( - btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 109); - } else { - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 101); - } - } else { - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 1); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 15); - /* halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 102); */ - } - - } - -} - - -void halbtc8821c2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false, wifi_turbo = false; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 7); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 5); - } else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 6); - - } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if (wifi_turbo) - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - else - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 7); - - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 107); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 105); - } else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 106); - - } - -} - - - -/* PAN(EDR)+A2DP */ -void halbtc8821c2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false, wifi_turbo = false; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = true; -#endif - - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) { - - if (((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) || - (!coex_sta->is_A2DP_3M)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 7); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 5); - } else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 6); - } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if (wifi_turbo) - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - else - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 7); - - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 107); - else if (wifi_turbo) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 108); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 105); - } else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 106); - - } - -} - -void halbtc8821c2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 3); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 4); - } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if (coex_sta->hid_busy_num >= 2) { - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - if (wifi_bw == 0) /* 11bg mode */ - halbtc8821c2ant_set_wltoggle_coex_table( - btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - else - halbtc8821c2ant_set_wltoggle_coex_table( - btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 110); - } else { - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - - if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 103); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 104); - } - - } - -} - -/* HID+A2DP+PAN(EDR) */ -void halbtc8821c2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) -{ - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = false; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres , 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2 , 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres , 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(&pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2 , 0); - - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = false; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) { - - if (((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) || - (!coex_sta->is_A2DP_3M)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 7); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 5); - } else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 6); - } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = true; - - if (coex_sta->hid_busy_num >= 2) { - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - - if (wifi_bw == 0) /* 11bg mode */ - halbtc8821c2ant_set_wltoggle_coex_table( - btcoexist, - NORMAL_EXEC, - 0x1, 0xaa, - 0x5a, 0xaa, - 0xaa); - else - halbtc8821c2ant_set_wltoggle_coex_table( - btcoexist, - NORMAL_EXEC, - 0x2, 0xaa, - 0x5a, 0xaa, - 0xaa); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 110); - } else { - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 107); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - true, 105); - } else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, - 106); - } - } - -} - -void halbtc8821c2ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) -{ - - /* fw all off */ - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8821C_2ANT_PHASE_5G_RUNTIME); -} - -void halbtc8821c2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* hw all off */ - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); -} -void halbtc8821c2ant_action_wifi_linkscan_process(IN struct btc_coexist - *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - if (bt_link_info->pan_exist) { - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - } else { - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - } - -} - -void halbtc8821c2ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) -{ - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* fw all off */ - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); -} - -void halbtc8821c2ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - switch (coex_dm->cur_algorithm) { - - case BT_8821C_2ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_sco(btcoexist); - break; - case BT_8821C_2ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID.\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_hid(btcoexist); - break; - case BT_8821C_2ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_a2dp(btcoexist); - break; - case BT_8821C_2ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_a2dp_pan_hs(btcoexist); - break; - case BT_8821C_2ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_pan_edr(btcoexist); - break; - case BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_pan_edr_a2dp(btcoexist); - break; - case BT_8821C_2ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_pan_edr_hid(btcoexist); - break; - case BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_hid_a2dp_pan_edr( - btcoexist); - break; - case BT_8821C_2ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_hid_a2dp(btcoexist); - break; - case BT_8821C_2ANT_COEX_ALGO_NOPROFILEBUSY: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_bt_idle(btcoexist); - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_coex_all_off(btcoexist); - break; - } - - coex_dm->pre_algorithm = coex_dm->cur_algorithm; - -} - - -void halbtc8821c2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; - u32 num_of_wifi_link = 0; - u32 wifi_link_status = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean miracast_plus_bt = false; - boolean scan = false, link = false, roam = false, - under_4way = false, - wifi_connected = false, wifi_under_5g = - false, - bt_hs_on = false; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); - BTC_TRACE(trace_buf); - - if (btcoexist->manual_control) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (btcoexist->stop_coex_dm) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->under_ips) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (!coex_sta->run_time_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], return for run_time_state = false !!!\n"); - BTC_TRACE(trace_buf); - return; - } - - if (coex_sta->freeze_coexrun_by_btinfo) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); - BTC_TRACE(trace_buf); - return; - } - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (wifi_under_5g) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 5G!!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_action_wifi_under5g(btcoexist); - return; - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 2G!!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8821C_2ANT_PHASE_2G_RUNTIME); - } - - - if (coex_sta->bt_whck_test) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_bt_whql_test(btcoexist); - return; - } - - if (coex_sta->bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled!!!\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_coex_all_off(btcoexist); - return; - } - - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_bt_inquiry(btcoexist); - return; - } - - if (coex_sta->is_setupLink) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is re-link !!!\n"); - halbtc8821c2ant_action_bt_relink(btcoexist); - return; - } - - /* for P2P */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); - BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) - miracast_plus_bt = true; - else - miracast_plus_bt = false; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", - scan, link, roam, under_4way); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_action_wifi_linkscan_process(btcoexist); - } else - halbtc8821c2ant_action_wifi_multi_port(btcoexist); - - return; - } else { - miracast_plus_bt = false; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is hs\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_bt_hs(btcoexist); - return; - } - - if ((BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || - (BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, bt idle!!.\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_action_bt_idle(btcoexist); - return; - } - - algorithm = halbtc8821c2ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", - coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under Link Process !!\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_wifi_linkscan_process(btcoexist); - } else if (wifi_connected) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, wifi connected!!.\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_wifi_connected(btcoexist); - - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, wifi not-connected!!.\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_action_wifi_not_connected(btcoexist); - } -} - -void halbtc8821c2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Coex Mechanism Init!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* fw all off */ - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0); - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_sta->pop_event_cnt = 0; - coex_sta->cnt_RemoteNameReq = 0; - coex_sta->cnt_ReInit = 0; - coex_sta->cnt_setupLink = 0; - coex_sta->cnt_IgnWlanAct = 0; - coex_sta->cnt_Page = 0; - coex_sta->cnt_RoleSwitch = 0; - - halbtc8821c2ant_query_bt_info(btcoexist); -} - - -void halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - u8 u8tmp = 0; - u32 vendor; - u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - u8 i; - - - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u32tmp1 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", - u32tmp3, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf);; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - coex_sta->bt_ble_scan_type = 0; - coex_sta->bt_ble_scan_para[0] = 0; - coex_sta->bt_ble_scan_para[1] = 0; - coex_sta->bt_ble_scan_para[2] = 0; - coex_sta->bt_reg_vendor_ac = 0xffff; - coex_sta->bt_reg_vendor_ae = 0xffff; - coex_sta->isolation_btween_wb = BT_8821C_2ANT_DEFAULT_ISOLATION; - coex_sta->gnt_error_cnt = 0; - coex_sta->bt_relink_downcount = 0; - - for (i = 0; i <= 9; i++) - coex_sta->bt_afh_map[i] = 0; - - /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; - - coex_sta->dis_ver_info_cnt = 0; - - halbtc8821c2ant_coex_switch_threshold(btcoexist, - coex_sta->isolation_btween_wb); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - - /* BT report packet sample rate */ - btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); - - /* Init 0x778 = 0x1 for 2-Ant */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); - - /* Enable PTA (3-wire function form BT side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); - - /* Enable PTA (tx/rx signal form WiFi side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); - - /* set GNT_BT=1 for coex table select both */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1); - - halbtc8821c2ant_enable_gnt_to_gpio(btcoexist, true); - -#if 0 - /* check if WL firmware download ok */ - /*if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)*/ - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ONOFF, true); -#endif - - /* Enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, - 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ - - /* WLAN_Tx by GNT_WL 0x950[29] = 0 */ - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0); */ - - halbtc8821c2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0); - - psd_scan->ant_det_is_ant_det_available = true; - - if (wifi_only) { - coex_sta->concurrent_rx_mode_on = false; - /* Path config */ - /* Set Antenna Path */ - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_WLANONLY_INIT); - - btcoexist->stop_coex_dm = true; - } else { - /*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); - - coex_sta->concurrent_rx_mode_on = true; - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */ - - /* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx, mask Tx only */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0); - - /* Set Antenna Path */ - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_COEX_INIT); - - btcoexist->stop_coex_dm = false; - } - - -} - - - -/* ************************************************************ - * work around function start with wa_halbtc8821c2ant_ - * ************************************************************ - * ************************************************************ - * extern function start with ex_halbtc8821c2ant_ - * ************************************************************ */ -void ex_halbtc8821c2ant_power_on_setting(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x0; - u16 u16tmp = 0x0; - u32 value = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Execute 8821c 2-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Ant Det Finish = %s, Ant Det Number = %d\n", - (board_info->btdm_ant_det_finish ? "Yes" : "No"), - board_info->btdm_ant_num_by_ant_det); - BTC_TRACE(trace_buf); - - - btcoexist->stop_coex_dm = true; - psd_scan->ant_det_is_ant_det_available = false; - - /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - - - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - - /* Check efuse 0xc3[6] for Single Antenna Path */ - if (board_info->single_ant_path == 0) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Single Antenna, Antenna at Aux Port\n"); - BTC_TRACE(trace_buf); - - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - - u8tmp = 7; - } else if (board_info->single_ant_path == 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Single Antenna, Antenna at Main Port\n"); - BTC_TRACE(trace_buf); - - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - - u8tmp = 6; - } - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d\n", - board_info->single_ant_path , board_info->btdm_ant_pos); - BTC_TRACE(trace_buf); - - /* Setup RF front end type */ - halbtc8821c2ant_set_rfe_type(btcoexist); - - /* Set Antenna Path to BT side */ - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_2ANT_PHASE_COEX_POWERON); - - /* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at power on */ - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); - - /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - halbtc8821c2ant_enable_gnt_to_gpio(btcoexist, true); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n", - halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38)); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcb4 (Power-On) = 0x%x / 0x%x\n", - btcoexist->btc_read_4byte(btcoexist, 0x70), - btcoexist->btc_read_4byte(btcoexist, 0xcb4)); - BTC_TRACE(trace_buf); - -} - -void ex_halbtc8821c2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ - - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - if (btcoexist->chip_interface == BTC_INTF_USB) { - /* fixed at S0 for USB interface */ - u8tmp |= 0x1; /* antenna inverse */ - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - } else { - /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ - if (board_info->single_ant_path == 0) { - } else if (board_info->single_ant_path == 1) { - /* set to S0 */ - u8tmp |= 0x1; /* antenna inverse */ - } - - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, - u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, - u8tmp); - } -} - - -void ex_halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) -{ - halbtc8821c2ant_init_hw_config(btcoexist, wifi_only); -} - -void ex_halbtc8821c2ant_init_coex_dm(IN struct btc_coexist *btcoexist) -{ - - halbtc8821c2ant_init_coex_dm(btcoexist); -} - -void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, ps_tdma_case = 0; - u32 u32tmp[4]; - u16 u16tmp[4]; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; - u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; - static u8 pop_report_in_10s = 0; - u32 phyver = 0; - boolean lte_coex_on = false; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); - CL_PRINTF(cli_buf); - - if (btcoexist->manual_control) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); - CL_PRINTF(cli_buf); - } - - if (psd_scan->ant_det_try_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %s / %d", - "Ant PG Num/ Mech/ Pos/ RFE", - board_info->pg_ant_num, board_info->btdm_ant_num, - (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT - ? "Main" : "Aux"), - rfe_type->rfe_module_type); - CL_PRINTF(cli_buf); - } else { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", - board_info->pg_ant_num, - board_info->btdm_ant_num_by_ant_det, - (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT - ? "Main" : "Aux"), - rfe_type->rfe_module_type, - psd_scan->ant_det_try_count, - psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); - CL_PRINTF(cli_buf); - - - if (board_info->btdm_ant_det_finish) { - - if (psd_scan->ant_det_result != 12) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d", - "Ant Det PSD Value", - psd_scan->ant_det_psd_scan_peak_val - / 100); - CL_PRINTF(cli_buf); - } - } - - - bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); - - bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", - "CoexVer WL/ BT_Desired/ BT_Report", - glcoex_ver_date_8821c_2ant, glcoex_ver_8821c_2ant, - glcoex_ver_btdesired_8821c_2ant, - bt_coex_ver, - (bt_coex_ver == 0xff ? "Unknown" : - (coex_sta->bt_disabled ? "BT-disable" : - (bt_coex_ver >= glcoex_ver_btdesired_8821c_2ant ? - "Match" : "Mis-Match")))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", - "W_FW/ B_FW/ Phy/ Kt", - fw_ver, bt_patch_ver, phyver, - coex_sta->cut_version + 65); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", - "AFH Map to BT", - coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ", - "Isolation/WL_Thres/BT_Thres", - coex_sta->isolation_btween_wb, - coex_sta->wifi_coex_thres, - coex_sta->bt_coex_thres); - CL_PRINTF(cli_buf); - - /* wifi status */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Wifi Status]============"); - CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[BT Status]============"); - CL_PRINTF(cli_buf); - - pop_report_in_10s++; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") - : ((BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); - CL_PRINTF(cli_buf); - - if (pop_report_in_10s >= 5) { - coex_sta->pop_event_cnt = 0; - pop_report_in_10s = 0; - } - - - if (coex_sta->num_of_profile != 0) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s%s%s%s%s", - "Profiles", - ((bt_link_info->a2dp_exist) ? "A2DP," : ""), - ((bt_link_info->sco_exist) ? "HFP," : ""), - ((bt_link_info->hid_exist) ? - ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : - "HID(2/18),") : ""), - ((bt_link_info->pan_exist) ? "PAN," : ""), - ((coex_sta->voice_over_HOGP) ? "Voice" : "")); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = None", "Profiles"); - - CL_PRINTF(cli_buf); - - - if (bt_link_info->a2dp_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", - "A2DP Rate/Bitpool/Auto_Slot", - ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), - coex_sta->a2dp_bit_pool, - ((coex_sta->is_autoslot) ? "On" : "Off") - ); - CL_PRINTF(cli_buf); - } - - if (bt_link_info->hid_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "HID PairNum/Forbid_Slot", - coex_sta->hid_pair_cnt, - coex_sta->forbidden_slot - ); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x", - "Role/RoleSwCnt/IgnWlact/Feature", - ((bt_link_info->slave_role) ? "Slave" : "Master"), - coex_sta->cnt_RoleSwitch, - ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), - coex_sta->bt_coex_supported_feature); - CL_PRINTF(cli_buf); - - if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "BLEScan Type/TV/Init/Ble", - coex_sta->bt_ble_scan_type, - (coex_sta->bt_ble_scan_type & 0x1 ? - coex_sta->bt_ble_scan_para[0] : 0x0), - (coex_sta->bt_ble_scan_type & 0x2 ? - coex_sta->bt_ble_scan_para[1] : 0x0), - (coex_sta->bt_ble_scan_type & 0x4 ? - coex_sta->bt_ble_scan_para[2] : 0x0)); - CL_PRINTF(cli_buf); - } - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", - "ReInit/ReLink/IgnWlact/Page/NameReq", - coex_sta->cnt_ReInit, - coex_sta->cnt_setupLink, - coex_sta->cnt_IgnWlanAct, - coex_sta->cnt_Page, - coex_sta->cnt_RemoteNameReq - ); - CL_PRINTF(cli_buf); - - halbtc8821c2ant_read_score_board(btcoexist, &u16tmp[0]); - - if ((coex_sta->bt_reg_vendor_ae == 0xffff) || - (coex_sta->bt_reg_vendor_ac == 0xffff)) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", - ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), - coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); - CL_PRINTF(cli_buf); - - if (coex_sta->num_of_profile > 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", - "AFH MAP", - coex_sta->bt_afh_map[0], - coex_sta->bt_afh_map[1], - coex_sta->bt_afh_map[2], - coex_sta->bt_afh_map[3], - coex_sta->bt_afh_map[4], - coex_sta->bt_afh_map[5], - coex_sta->bt_afh_map[6], - coex_sta->bt_afh_map[7], - coex_sta->bt_afh_map[8], - coex_sta->bt_afh_map[9] - ); - CL_PRINTF(cli_buf); - } - - for (i = 0; i < BT_INFO_SRC_8821C_2ANT_MAX; i++) { - if (coex_sta->bt_info_c2h_cnt[i]) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", - glbt_info_src_8821c_2ant[i], - coex_sta->bt_info_c2h[i][0], - coex_sta->bt_info_c2h[i][1], - coex_sta->bt_info_c2h[i][2], - coex_sta->bt_info_c2h[i][3], - coex_sta->bt_info_c2h[i][4], - coex_sta->bt_info_c2h[i][5], - coex_sta->bt_info_c2h[i][6], - coex_sta->bt_info_c2h_cnt[i]); - CL_PRINTF(cli_buf); - } - } - - /* Sw mechanism */ - if (btcoexist->manual_control) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[mechanism] (before Manual)============"); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Mechanism]============"); - - CL_PRINTF(cli_buf); - - - ps_tdma_case = coex_dm->cur_ps_tdma; - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, %s)", - "TDMA", - coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], - coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], - coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"), - (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant")); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", - "Table/0x6c0/0x6c4/0x6c8", - coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); - CL_PRINTF(cli_buf); - - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x", - "0x778/0x6cc", - u8tmp[0], u32tmp[0]); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", - "AntDiv/ForceLPS/LPRA", - ((board_info->ant_div_cfg) ? "On" : "Off"), - ((coex_sta->force_lps_on) ? "On" : "Off"), - ((coex_dm->cur_low_penalty_ra) ? "On" : "Off")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "WL_DACSwing/ BT_Dec_Pwr", coex_dm->cur_fw_dac_swing_lvl, - coex_dm->cur_bt_dec_pwr_lvl); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? true : false; - - if (lte_coex_on) { - - u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0xa0); - u32tmp[1] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0xa4); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "LTE Coex Table W_L/B_L", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); - CL_PRINTF(cli_buf); - - - u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0xa8); - u32tmp[1] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0xac); - u32tmp[2] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0xb0); - u32tmp[3] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0xb4); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "LTE Break Table W_L/B_L/L_W/L_B", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, - u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); - CL_PRINTF(cli_buf); - - } - - /* Hw setting */ - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", - "============[Hw setting]============"); - CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp[1] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", - "LTE Coex/Path Owner", - ((lte_coex_on) ? "On" : "Off") , - ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); - CL_PRINTF(cli_buf); - - if (lte_coex_on) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %d/ %d", - "LTE 3Wire/OPMode/UART/UARTMode", - (int)((u32tmp[0] & BIT(6)) >> 6), - (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), - (int)((u32tmp[0] & BIT(3)) >> 3), - (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "LTE_Busy/UART_Busy", - (int)((u32tmp[1] & BIT(1)) >> 1), - (int)(u32tmp[1] & BIT(0))); - CL_PRINTF(cli_buf); - } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", - "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", - ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), - ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), - ((u8tmp[0] & BIT(3)) ? "On" : "Off"), - coex_sta->gnt_error_cnt); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "GNT_WL/GNT_BT", - (int)((u32tmp[1] & BIT(2)) >> 2), - (int)((u32tmp[1] & BIT(3)) >> 3)); - CL_PRINTF(cli_buf); - - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s", - "0xcb0/0xcb4/0xcb8[23:16]", - u32tmp[0], u32tmp[1], u8tmp[0], - ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "4c[24:23]/64[0]/4c6[4]/40[5]", - (u32tmp[0] & (BIT(24) | BIT(23))) >> 23 , u8tmp[2] & 0x1 , - (int)((u8tmp[0] & BIT(4)) >> 4), - (int)((u8tmp[1] & BIT(5)) >> 5)); - CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x", - "0x550/0x522/4-RxAGC/0xc50", - u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]); - CL_PRINTF(cli_buf); - - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_CCK); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm); - CL_PRINTF(cli_buf); - -#if 1 - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_OK CCK/11g/11n/11ac", - coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", - "CRC_Err CCK/11g/11n/11ac", - coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); - CL_PRINTF(cli_buf); -#endif - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "WlHiPri/ Locking/ Locked/ Noisy", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), - (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No"), - coex_sta->wl_noisy_level); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", - "0x770(Hi-pri rx/tx)", - coex_sta->high_priority_rx, coex_sta->high_priority_tx, - (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : - "")); - CL_PRINTF(cli_buf); - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", - "0x774(Lo-pri rx/tx)", - coex_sta->low_priority_rx, coex_sta->low_priority_tx, - (bt_link_info->slave_role ? "(Slave!!)" : ( - coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); - CL_PRINTF(cli_buf); - - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); -} - - -void ex_halbtc8821c2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_IPS_ENTER == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS ENTER notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = true; - coex_sta->under_lps = false; - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_ONOFF | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, - false); - - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_WLAN_OFF); - - halbtc8821c2ant_action_coex_all_off(btcoexist); - } else if (BTC_IPS_LEAVE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], IPS LEAVE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_ips = false; -#if 0 - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, true); - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ONOFF, true); -#endif - - halbtc8821c2ant_init_hw_config(btcoexist, false); - halbtc8821c2ant_init_coex_dm(btcoexist); - halbtc8821c2ant_query_bt_info(btcoexist); - } -} - -void ex_halbtc8821c2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) -{ - if (btcoexist->manual_control || btcoexist->stop_coex_dm) - return; - - if (BTC_LPS_ENABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = true; - coex_sta->under_ips = false; - - if (coex_sta->force_lps_on == true) { /* LPS No-32K */ - /* Write WL "Active" in Score-board for PS-TDMA */ - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, true); - - } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ - /* Write WL "Non-Active" in Score-board for Native-PS */ - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, false); - } - - - } else if (BTC_LPS_DISABLE == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS DISABLE notify\n"); - BTC_TRACE(trace_buf); - coex_sta->under_lps = false; - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, true); - } -} - -void ex_halbtc8821c2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean wifi_connected = false; - boolean wifi_under_5g = false; - - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN notify()\n"); - BTC_TRACE(trace_buf); - - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* this can't be removed for RF off_on event, or BT would dis-connect */ - halbtc8821c2ant_query_bt_info(btcoexist); - - if (BTC_SCAN_START == type) { - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, - &wifi_under_5g); - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_ONOFF, - true); - - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** SCAN START notify (5g)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_action_wifi_under5g(btcoexist); - return; - } - - coex_sta->wifi_is_high_pri_task = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** SCAN START notify (2g)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_2G_RUNTIME); - - halbtc8821c2ant_run_coexist_mechanism( - btcoexist); - - return; - } - - - if (BTC_SCAN_START_2G == type) { - - if (!wifi_connected) - coex_sta->wifi_is_high_pri_task = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify (2G)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_ONOFF, - true); - - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_2G_RUNTIME); - - halbtc8821c2ant_run_coexist_mechanism(btcoexist); - - } else if (BTC_SCAN_FINISH == type) { - - coex_sta->wifi_is_high_pri_task = false; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", - coex_sta->scan_ap_num); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_run_coexist_mechanism(btcoexist); - } - -} - -void ex_halbtc8821c2ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - - boolean wifi_connected = false, bt_hs_on = false; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = false; - u8 agg_buf_size = 5; - - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - if (type == BTC_SWITCH_TO_5G) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], switchband_notify --- switch to 5G\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_action_wifi_under5g(btcoexist); - - } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** switchband_notify BTC_SWITCH_TO_2G (no for scan)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_run_coexist_mechanism(btcoexist); - - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], switchband_notify --- switch to 2G\n"); - BTC_TRACE(trace_buf); - - ex_halbtc8821c2ant_scan_notify(btcoexist, - BTC_SCAN_START_2G); - } -} - - -void ex_halbtc8821c2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_ONOFF, - true); - - if ((BTC_ASSOCIATE_5G_START == type) || - (BTC_ASSOCIATE_5G_FINISH == type)) { - - if (BTC_ASSOCIATE_5G_START == type) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], connect_notify --- 5G start\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], connect_notify --- 5G finish\n"); - - BTC_TRACE(trace_buf); - - halbtc8821c2ant_action_wifi_under5g(btcoexist); - return; - } - - - if (BTC_ASSOCIATE_START == type) { - - coex_sta->wifi_is_high_pri_task = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT START notify (2G)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_2G_RUNTIME); - - halbtc8821c2ant_run_coexist_mechanism(btcoexist); - - /* To keep TDMA case during connect process, - to avoid changed by Btinfo and runcoexmechanism */ - coex_sta->freeze_coexrun_by_btinfo = true; - - coex_dm->arp_cnt = 0; - - } else if (BTC_ASSOCIATE_FINISH == type) { - - coex_sta->wifi_is_high_pri_task = false; - coex_sta->freeze_coexrun_by_btinfo = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify (2G)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_run_coexist_mechanism(btcoexist); - } -} - -void ex_halbtc8821c2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - u8 ap_num = 0; - boolean wifi_under_b_mode = false, wifi_under_5g = false; - - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (BTC_MEDIA_CONNECT == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_ONOFF, - true); - - if (wifi_under_5g) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 5G!!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_action_wifi_under5g(btcoexist); - return; - } - - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_2G_RUNTIME); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, false); - } - - - halbtc8821c2ant_update_wifi_channel_info(btcoexist, type); -} - -void ex_halbtc8821c2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - boolean under_4way = false, wifi_under_5g = false; - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) - return; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (wifi_under_5g) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 5G!!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_action_wifi_under5g(btcoexist); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (under_4way) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ---- under_4way!!\n"); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - - } else if (BTC_PACKET_ARP == type) { - - coex_dm->arp_cnt++; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet ARP notify -cnt = %d\n", - coex_dm->arp_cnt); - BTC_TRACE(trace_buf); - - } else { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", - type); - BTC_TRACE(trace_buf); - - coex_sta->wifi_is_high_pri_task = true; - coex_sta->specific_pkt_period_cnt = 2; - } - - if (coex_sta->wifi_is_high_pri_task) { - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_SCAN, true); - halbtc8821c2ant_run_coexist_mechanism(btcoexist); - } - -} - -void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) -{ - u8 i, rsp_source = 0; - boolean wifi_connected = false; - boolean wifi_scan = false, wifi_link = false, wifi_roam = false, - wifi_busy = false; - static boolean is_scoreboard_scan = false; - - - rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8821C_2ANT_MAX) - rsp_source = BT_INFO_SRC_8821C_2ANT_WIFI_FW; - coex_sta->bt_info_c2h_cnt[rsp_source]++; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, - length); - BTC_TRACE(trace_buf); - - for (i = 0; i < length; i++) { - coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; - - if (i == length - 1) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", - tmp_buf[i]); - BTC_TRACE(trace_buf); - } - } - - coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; - coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; - coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; - - if (BT_INFO_SRC_8821C_2ANT_WIFI_FW != rsp_source) { - - /* if 0xff, it means BT is under WHCK test */ - coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true : - false); - - coex_sta->bt_create_connection = (( - coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true : - false); - - /* unit: %, value-100 to translate to unit: dBm */ - coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + - 10; - - coex_sta->c2h_bt_remote_name_req = (( - coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true : - false); - - coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & - 0x10) ? true : false); - - coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & - 0x9) ? true : false); - - coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? - true : false); - - coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & - BT_INFO_8821C_2ANT_B_INQ_PAGE) ? true : false); - - coex_sta->a2dp_bit_pool = ((( - coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? - coex_sta->bt_info_c2h[rsp_source][6] : 0); - - coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & - 0xf; - - coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; - - coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; - - coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; - - coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; - - if (coex_sta->bt_retry_cnt >= 1) - coex_sta->pop_event_cnt++; - - if (coex_sta->c2h_bt_remote_name_req) - coex_sta->cnt_RemoteNameReq++; - - if (coex_sta->bt_info_ext & BIT(1)) - coex_sta->cnt_ReInit++; - - - if (coex_sta->bt_info_ext & BIT(2)) { - coex_sta->cnt_setupLink++; - coex_sta->is_setupLink = true; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Re-Link start in BT info!!\n"); - BTC_TRACE(trace_buf); - } else { - coex_sta->is_setupLink = false; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Re-Link stop in BT info!!\n"); - BTC_TRACE(trace_buf); - } - - - if (coex_sta->bt_info_ext & BIT(3)) - coex_sta->cnt_IgnWlanAct++; - - if (coex_sta->bt_info_ext & BIT(6)) - coex_sta->cnt_RoleSwitch++; - - if (coex_sta->bt_create_connection) { - coex_sta->cnt_Page++; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, - &wifi_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); - - if ((wifi_link) || (wifi_roam) || (wifi_scan) || - (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { - - is_scoreboard_scan = true; - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_SCAN, true); - - } else - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_SCAN, false); - - } else { - if (is_scoreboard_scan) { - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_SCAN, false); - is_scoreboard_scan = false; - } - } - - /* Here we need to resend some wifi info to BT */ - /* because bt is reset and loss of the info. */ - - if ((!btcoexist->manual_control) && - (!btcoexist->stop_coex_dm)) { - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* Re-Init */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - if (wifi_connected) - halbtc8821c2ant_update_wifi_channel_info( - btcoexist, BTC_MEDIA_CONNECT); - else - halbtc8821c2ant_update_wifi_channel_info( - btcoexist, - BTC_MEDIA_DISCONNECT); - } - - - /* If Ignore_WLanAct && not SetUp_Link */ - if ((coex_sta->bt_info_ext & BIT(3)) && - (!(coex_sta->bt_info_ext & BIT(2))) && - (!(coex_sta->bt_info_ext & BIT(6)))) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8821c2ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, false); - } else { - if (coex_sta->bt_info_ext & BIT(2)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ignore Wlan active because Re-link!!\n"); - BTC_TRACE(trace_buf); - } else if (coex_sta->bt_info_ext & BIT(6)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ignore Wlan active because Role-Switch!!\n"); - BTC_TRACE(trace_buf); - } - } - } - - } - - if ((coex_sta->bt_info_ext & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); - BTC_TRACE(trace_buf); - coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( - btcoexist); - - if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) - coex_sta->bt_ble_scan_para[0] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x1); - if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) - coex_sta->bt_ble_scan_para[1] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x2); - if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) - coex_sta->bt_ble_scan_para[2] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x4); - } - - halbtc8821c2ant_update_bt_link_info(btcoexist); - - halbtc8821c2ant_run_coexist_mechanism(btcoexist); -} - -void ex_halbtc8821c2ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); - BTC_TRACE(trace_buf); - - if (BTC_RF_ON == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned ON!!\n"); - BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = false; -#if 0 - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, true); - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ONOFF, true); -#endif - } else if (BTC_RF_OFF == type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RF is turned OFF!!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_WLAN_OFF); - - halbtc8821c2ant_action_coex_all_off(btcoexist); - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_ONOFF | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, - false); - - btcoexist->stop_coex_dm = true; - - } -} - -void ex_halbtc8821c2ant_halt_notify(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_2ANT_PHASE_WLAN_OFF); - - ex_halbtc8821c2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_ONOFF | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, - false); -} - -void ex_halbtc8821c2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) -{ - boolean wifi_under_5g = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if ((BTC_WIFI_PNP_SLEEP == pnp_state) || - (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to SLEEP\n"); - BTC_TRACE(trace_buf); - - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ - coex_sta->under_ips = false; - coex_sta->under_lps = false; - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_ONOFF | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, - false); - - if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { - - if (wifi_under_5g) - halbtc8821c2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_2ANT_PHASE_5G_RUNTIME); - else - halbtc8821c2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_2ANT_PHASE_2G_RUNTIME); - } else { - - halbtc8821c2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_WLAN_OFF); - } - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Pnp notify to WAKE UP\n"); - BTC_TRACE(trace_buf); -#if 0 - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, true); - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ONOFF, true); -#endif - } -} - -void ex_halbtc8821c2ant_periodical(IN struct btc_coexist *btcoexist) -{ - struct btc_board_info *board_info = &btcoexist->board_info; - boolean wifi_busy = false; - u32 bt_patch_ver; - static u8 cnt = 0; - boolean bt_relink_finish = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ************* Periodical *************\n"); - BTC_TRACE(trace_buf); - -#if (BT_AUTO_REPORT_ONLY_8821C_2ANT == 0) - halbtc8821c2ant_query_bt_info(btcoexist); -#endif - - halbtc8821c2ant_monitor_bt_ctr(btcoexist); - halbtc8821c2ant_monitor_wifi_ctr(btcoexist); - halbtc8821c2ant_monitor_bt_enable_disable(btcoexist); - -#if 0 - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* halbtc8821c2ant_read_score_board(btcoexist, &bt_scoreboard_val); */ - - if (wifi_busy) { - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, true); - /* - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_WLBUSY, true); - - if (bt_scoreboard_val & BIT(6)) - halbtc8821c2ant_query_bt_info(btcoexist); */ - } else { - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, false); - /* - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_WLBUSY, - false); */ - } -#endif - - if (coex_sta->bt_relink_downcount != 0) { - coex_sta->bt_relink_downcount--; - - if (coex_sta->bt_relink_downcount == 0) - bt_relink_finish = true; - } - - /* for 4-way, DHCP, EAPOL packet */ - if (coex_sta->specific_pkt_period_cnt > 0) { - - coex_sta->specific_pkt_period_cnt--; - - if ((coex_sta->specific_pkt_period_cnt == 0) && - (coex_sta->wifi_is_high_pri_task)) - coex_sta->wifi_is_high_pri_task = false; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ***************** Hi-Pri Task = %s\n", - (coex_sta->wifi_is_high_pri_task ? "Yes" : - "No")); - BTC_TRACE(trace_buf); - - } - - if (!coex_sta->bt_disabled) { - if (coex_sta->bt_coex_supported_feature == 0) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, - &coex_sta->bt_coex_supported_feature); - - if ((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, - &coex_sta->bt_coex_supported_version); - - if (coex_sta->bt_reg_vendor_ac == 0xffff) - coex_sta->bt_reg_vendor_ac = (u16)( - btcoexist->btc_get_bt_reg(btcoexist, 3, - 0xac) & 0xffff); - - if (coex_sta->bt_reg_vendor_ae == 0xffff) - coex_sta->bt_reg_vendor_ae = (u16)( - btcoexist->btc_get_bt_reg(btcoexist, 3, - 0xae) & 0xffff); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, - &bt_patch_ver); - btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; - - if (coex_sta->num_of_profile > 0) { - cnt++; - - if (cnt >= 3) { - btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, - &coex_sta->bt_afh_map[0]); - cnt = 0; - } - } - } - - if (halbtc8821c2ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish)) - halbtc8821c2ant_run_coexist_mechanism(btcoexist); -} - - -/*#pragma optimize( "", off )*/ -void ex_halbtc8821c2ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - -} - - -void ex_halbtc8821c2ant_display_ant_detection(IN struct btc_coexist *btcoexist) -{ - -} - - -#endif - -#endif /* #if (RTL8821C_SUPPORT == 1) */ - - diff --git a/hal/btc/halbtc8821c2ant.h b/hal/btc/halbtc8821c2ant.h deleted file mode 100644 index ae42803..0000000 --- a/hal/btc/halbtc8821c2ant.h +++ /dev/null @@ -1,504 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) - -#if (RTL8821C_SUPPORT == 1) - -/* ******************************************* - * The following is for 8821C 2Ant BT Co-exist definition - * ******************************************* */ -#define BT_8821C_2ANT_COEX_DBG 0 -#define BT_AUTO_REPORT_ONLY_8821C_2ANT 1 - - -#define BT_INFO_8821C_2ANT_B_FTP BIT(7) -#define BT_INFO_8821C_2ANT_B_A2DP BIT(6) -#define BT_INFO_8821C_2ANT_B_HID BIT(5) -#define BT_INFO_8821C_2ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8821C_2ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8821C_2ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8821C_2ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8821C_2ANT_B_CONNECTION BIT(0) - -#define BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT 2 - - -#define BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 80 /* unit: % WiFi RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation, default = 42 */ -#define BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 80 /* unit: % BT RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation, default = 46 */ -#define BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 80 /* unit: % WiFi RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation, default = 42 */ -#define BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES2 80 /* unit: % BT RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation, default = 46 */ -#define BT_8821C_2ANT_DEFAULT_ISOLATION 15 /* unit: dB */ -#define BT_8821C_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */ -#define BT_8821C_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */ -#define BT_8821C_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */ -#define BT_8821C_2ANT_WIFI_SIR_THRES2 -30 /* unit: dB */ -#define BT_8821C_2ANT_BT_SIR_THRES1 -15 /* unit: dB */ -#define BT_8821C_2ANT_BT_SIR_THRES2 -30 /* unit: dB */ - - -/* for Antenna detection */ -#define BT_8821C_2ANT_ANTDET_PSDTHRES_BACKGROUND 50 -#define BT_8821C_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 -#define BT_8821C_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 52 -#define BT_8821C_2ANT_ANTDET_PSDTHRES_1ANT 40 -#define BT_8821C_2ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8821C_2ANT_ANTDET_SWEEPPOINT_DELAY 60000 -#define BT_8821C_2ANT_ANTDET_ENABLE 0 -#define BT_8821C_2ANT_ANTDET_BTTXTIME 100 -#define BT_8821C_2ANT_ANTDET_BTTXCHANNEL 39 -#define BT_8821C_2ANT_ANTDET_PSD_SWWEEPCOUNT 50 - - -#define BT_8821C_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 - -enum bt_8821c_2ant_signal_state { - BT_8821C_2ANT_SIG_STA_SET_TO_LOW = 0x0, - BT_8821C_2ANT_SIG_STA_SET_BY_HW = 0x0, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH = 0x1, - BT_8821C_2ANT_SIG_STA_MAX -}; - -enum bt_8821c_2ant_path_ctrl_owner { - BT_8821C_2ANT_PCO_BTSIDE = 0x0, - BT_8821C_2ANT_PCO_WLSIDE = 0x1, - BT_8821C_2ANT_PCO_MAX -}; - -enum bt_8821c_2ant_gnt_ctrl_type { - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW = 0x1, - BT_8821C_2ANT_GNT_TYPE_MAX -}; - -enum bt_8821c_2ant_gnt_ctrl_block { - BT_8821C_2ANT_GNT_BLOCK_RFC_BB = 0x0, - BT_8821C_2ANT_GNT_BLOCK_RFC = 0x1, - BT_8821C_2ANT_GNT_BLOCK_BB = 0x2, - BT_8821C_2ANT_GNT_BLOCK_MAX -}; - -enum bt_8821c_2ant_lte_coex_table_type { - BT_8821C_2ANT_CTT_WL_VS_LTE = 0x0, - BT_8821C_2ANT_CTT_BT_VS_LTE = 0x1, - BT_8821C_2ANT_CTT_MAX -}; - -enum bt_8821c_2ant_lte_break_table_type { - BT_8821C_2ANT_LBTT_WL_BREAK_LTE = 0x0, - BT_8821C_2ANT_LBTT_BT_BREAK_LTE = 0x1, - BT_8821C_2ANT_LBTT_LTE_BREAK_WL = 0x2, - BT_8821C_2ANT_LBTT_LTE_BREAK_BT = 0x3, - BT_8821C_2ANT_LBTT_MAX -}; - -enum bt_info_src_8821c_2ant { - BT_INFO_SRC_8821C_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8821C_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8821C_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8821C_2ANT_MAX -}; - -enum bt_8821c_2ant_bt_status { - BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8821C_2ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8821C_2ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8821C_2ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8821C_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8821C_2ANT_BT_STATUS_MAX -}; - -enum bt_8821c_2ant_coex_algo { - BT_8821C_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8821C_2ANT_COEX_ALGO_SCO = 0x1, - BT_8821C_2ANT_COEX_ALGO_HID = 0x2, - BT_8821C_2ANT_COEX_ALGO_A2DP = 0x3, - BT_8821C_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8821C_2ANT_COEX_ALGO_PANEDR = 0x5, - BT_8821C_2ANT_COEX_ALGO_PANHS = 0x6, - BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8821C_2ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8821C_2ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8821C_2ANT_COEX_ALGO_NOPROFILEBUSY = 0xb, - BT_8821C_2ANT_COEX_ALGO_MAX -}; - -enum bt_8821c_2ant_ext_ant_switch_type { - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0, - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1, - BT_8821C_2ANT_EXT_ANT_SWITCH_NONE = 0x2, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAX -}; - -enum bt_8821c_2ant_ext_ant_switch_ctrl_type { - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_MAX -}; - -enum bt_8821c_2ant_ext_ant_switch_pos_type { - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT = 0x0, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG = 0x1, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA = 0x2, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE = 0x3, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_MAX -}; - -enum bt_8821c_2ant_ext_band_switch_pos_type { - BT_8821C_2ANT_EXT_BAND_SWITCH_TO_WLG = 0x0, - BT_8821C_2ANT_EXT_BAND_SWITCH_TO_WLA = 0x1, - BT_8821C_2ANT_EXT_BAND_SWITCH_TO_MAX -}; - -enum bt_8821c_2ant_int_block { - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_MAX -}; - -enum bt_8821c_2ant_phase { - BT_8821C_2ANT_PHASE_COEX_INIT = 0x0, - BT_8821C_2ANT_PHASE_WLANONLY_INIT = 0x1, - BT_8821C_2ANT_PHASE_WLAN_OFF = 0x2, - BT_8821C_2ANT_PHASE_2G_RUNTIME = 0x3, - BT_8821C_2ANT_PHASE_5G_RUNTIME = 0x4, - BT_8821C_2ANT_PHASE_BTMPMODE = 0x5, - BT_8821C_2ANT_PHASE_ANTENNA_DET = 0x6, - BT_8821C_2ANT_PHASE_COEX_POWERON = 0x7, - BT_8821C_2ANT_PHASE_2G_RUNTIME_CONCURRENT = 0x8, - BT_8821C_2ANT_PHASE_MAX -}; - -enum bt_8821c_2ant_Scoreboard { - BT_8821C_2ANT_SCOREBOARD_ACTIVE = BIT(0), - BT_8821C_2ANT_SCOREBOARD_ONOFF = BIT(1), - BT_8821C_2ANT_SCOREBOARD_SCAN = BIT(2), - BT_8821C_2ANT_SCOREBOARD_UNDERTEST = BIT(3), - BT_8821C_2ANT_SCOREBOARD_WLBUSY = BIT(6) -}; - - - -struct coex_dm_8821c_2ant { - /* hw setting */ - u32 pre_ant_pos_type; - u32 cur_ant_pos_type; - /* fw mechanism */ - u8 pre_bt_dec_pwr_lvl; - u8 cur_bt_dec_pwr_lvl; - u8 pre_fw_dac_swing_lvl; - u8 cur_fw_dac_swing_lvl; - boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; - u8 cur_ps_tdma; - u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean reset_tdma_adjust; - boolean pre_ps_tdma_on; - boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; - boolean cur_bt_auto_report; - - /* sw mechanism */ - boolean pre_rf_rx_lpf_shrink; - boolean cur_rf_rx_lpf_shrink; - u32 bt_rf_0x1e_backup; - boolean pre_low_penalty_ra; - boolean cur_low_penalty_ra; - boolean pre_dac_swing_on; - u32 pre_dac_swing_lvl; - boolean cur_dac_swing_on; - u32 cur_dac_swing_lvl; - boolean pre_adc_back_off; - boolean cur_adc_back_off; - boolean pre_agc_table_en; - boolean cur_agc_table_en; - u32 pre_val0x6c0; - u32 cur_val0x6c0; - u32 pre_val0x6c4; - u32 cur_val0x6c4; - u32 pre_val0x6c8; - u32 cur_val0x6c8; - u8 pre_val0x6cc; - u8 cur_val0x6cc; - boolean limited_dig; - - /* algorithm related */ - u8 pre_algorithm; - u8 cur_algorithm; - u8 bt_status; - u8 wifi_chnl_info[3]; - - boolean need_recover0x948; - u32 backup0x948; - - u8 pre_lps; - u8 cur_lps; - u8 pre_rpwm; - u8 cur_rpwm; - - boolean is_switch_to_1dot5_ant; - u8 switch_thres_offset; - u32 arp_cnt; - - u32 pre_ext_ant_switch_status; - u32 cur_ext_ant_switch_status; - - u8 pre_ext_band_switch_status; - u8 cur_ext_band_switch_status; - - u8 pre_int_block_status; - u8 cur_int_block_status; -}; - -struct coex_sta_8821c_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - boolean is_hiPri_rx_overhead; - u8 bt_rssi; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - u8 bt_info_c2h[BT_INFO_SRC_8821C_2ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8821C_2ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_remote_name_req; - - u8 bt_info_ext; - u8 bt_info_ext2; - u32 pop_event_cnt; - u8 scan_ap_num; - u8 bt_retry_cnt; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; - - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; - - u8 coex_table_type; - boolean force_lps_on; - - u8 dis_ver_info_cnt; - - u8 a2dp_bit_pool; - u8 cut_version; - - boolean concurrent_rx_mode_on; - - u16 score_board; - u8 isolation_btween_wb; /* 0~ 50 */ - u8 wifi_coex_thres; - u8 bt_coex_thres; - u8 wifi_coex_thres2; - u8 bt_coex_thres2; - - u8 num_of_profile; - boolean acl_busy; - boolean bt_create_connection; - boolean wifi_is_high_pri_task; - u32 specific_pkt_period_cnt; - u32 bt_coex_supported_feature; - u32 bt_coex_supported_version; - - u8 bt_ble_scan_type; - u32 bt_ble_scan_para[3]; - - boolean run_time_state; - boolean freeze_coexrun_by_btinfo; - - boolean is_A2DP_3M; - boolean voice_over_HOGP; - u8 bt_info; - boolean is_autoslot; - u8 forbidden_slot; - u8 hid_busy_num; - u8 hid_pair_cnt; - - u32 cnt_RemoteNameReq; - u32 cnt_setupLink; - u32 cnt_ReInit; - u32 cnt_IgnWlanAct; - u32 cnt_Page; - u32 cnt_RoleSwitch; - - u16 bt_reg_vendor_ac; - u16 bt_reg_vendor_ae; - - boolean is_setupLink; - u8 wl_noisy_level; - u32 gnt_error_cnt; - - u8 bt_afh_map[10]; - u8 bt_relink_downcount; - boolean is_tdma_btautoslot; - boolean is_tdma_btautoslot_hang; -}; - - -#define BT_8821C_2ANT_EXT_BAND_SWITCH_USE_DPDT 0 -#define BT_8821C_2ANT_EXT_BAND_SWITCH_USE_SPDT 1 - - -struct rfe_type_8821c_2ant { - - u8 rfe_module_type; - boolean ext_ant_switch_exist; - u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */ - u8 ext_ant_switch_ctrl_polarity; /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ - - boolean ext_band_switch_exist; - u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */ - u8 ext_band_switch_ctrl_polarity; - - boolean ant_at_main_port; - - boolean wlg_Locate_at_btg; /* If true: WLG at BTG, If false: WLG at WLAG */ - - boolean ext_ant_switch_diversity; /* If diversity on */ -}; - -#define BT_8821C_2ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ -#define BT_8821C_2ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ -#define BT_8821C_2ANT_ANTDET_BUF_LEN 16 - -struct psdscan_sta_8821c_2ant { - - u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ - u32 ant_det_bt_tx_time; - u32 ant_det_pre_psdscan_peak_val; - boolean ant_det_is_ant_det_available; - u32 ant_det_psd_scan_peak_val; - boolean ant_det_is_btreply_available; - u32 ant_det_psd_scan_peak_freq; - - u8 ant_det_result; - u8 ant_det_peak_val[BT_8821C_2ANT_ANTDET_BUF_LEN]; - u8 ant_det_peak_freq[BT_8821C_2ANT_ANTDET_BUF_LEN]; - u32 ant_det_try_count; - u32 ant_det_fail_count; - u32 ant_det_inteval_count; - u32 ant_det_thres_offset; - - u32 real_cent_freq; - s32 real_offset; - u32 real_span; - - u32 psd_band_width; /* unit: Hz */ - u32 psd_point; /* 128/256/512/1024 */ - u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_start_point; - u32 psd_stop_point; - u32 psd_max_value_point; - u32 psd_max_value; - u32 psd_max_value2; - u32 psd_avg_value; /* filter loop_max_value that below BT_8821C_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/ - u32 psd_loop_max_value[BT_8821C_2ANT_ANTDET_PSD_SWWEEPCOUNT]; /*max value in each loop */ - u32 psd_start_base; - u32 psd_avg_num; /* 1/8/16/32 */ - u32 psd_gen_count; - boolean is_AntDet_running; - boolean is_psd_show_max_only; -}; - - -/* ******************************************* - * The following is interface which will notify coex module. - * ******************************************* */ -void ex_halbtc8821c2ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c2ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8821c2ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8821c2ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8821c2ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c2ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8821c2ant_display_ant_detection(IN struct btc_coexist *btcoexist); - - -#else -#define ex_halbtc8821c2ant_power_on_setting(btcoexist) -#define ex_halbtc8821c2ant_pre_load_firmware(btcoexist) -#define ex_halbtc8821c2ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8821c2ant_init_coex_dm(btcoexist) -#define ex_halbtc8821c2ant_ips_notify(btcoexist, type) -#define ex_halbtc8821c2ant_lps_notify(btcoexist, type) -#define ex_halbtc8821c2ant_scan_notify(btcoexist, type) -#define ex_halbtc8821c2ant_switchband_notify(btcoexist,type) -#define ex_halbtc8821c2ant_connect_notify(btcoexist, type) -#define ex_halbtc8821c2ant_media_status_notify(btcoexist, type) -#define ex_halbtc8821c2ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8821c2ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8821c2ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8821c2ant_halt_notify(btcoexist) -#define ex_halbtc8821c2ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8821c2ant_periodical(btcoexist) -#define ex_halbtc8821c2ant_display_coex_info(btcoexist) -#define ex_halbtc8821c2ant_display_ant_detection(btcoexist) -#define ex_halbtc8821c2ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) -#endif - -#endif - - diff --git a/hal/btc/halbtc8821cwifionly.c b/hal/btc/halbtc8821cwifionly.c deleted file mode 100644 index ffa32ed..0000000 --- a/hal/btc/halbtc8821cwifionly.c +++ /dev/null @@ -1,200 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -#include "mp_precomp.h" - -static struct rfe_type_8821c_wifi_only gl_rfe_type_8821c_1ant; -static struct rfe_type_8821c_wifi_only *rfe_type = &gl_rfe_type_8821c_1ant; - - - -VOID hal8821c_wifi_only_switch_antenna( - IN struct wifi_only_cfg *pwifionlycfg, - IN u1Byte is_5g - ) -{ - boolean switch_polatiry_inverse = false; - u8 regval_0xcb7 = 0; - u8 pos_type, ctrl_type; - - if (!rfe_type->ext_ant_switch_exist) - return; - - /* swap control polarity if use different switch control polarity*/ - /* Normal switch polarity for DPDT, 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main */ - /* Normal switch polarity for SPDT, 0xcb4[29:28] = 2b'01 => Ant to BTG, 0xcb4[29:28] = 2b'10 => Ant to WLG */ - if (rfe_type->ext_ant_switch_ctrl_polarity) - switch_polatiry_inverse = !switch_polatiry_inverse; - - /* swap control polarity if 1-Ant at Aux */ - if (rfe_type->ant_at_main_port == false) - switch_polatiry_inverse = !switch_polatiry_inverse; - - if (is_5g) - pos_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLA; - else - pos_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLG; - - switch (pos_type) { - default: - case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLA: - - break; - case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLG: - if (!rfe_type->wlg_Locate_at_btg) - switch_polatiry_inverse = !switch_polatiry_inverse; - break; - } - - if (pwifionlycfg->haldata_info.ant_div_cfg) - ctrl_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; - else - ctrl_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BBSW; - - - switch (ctrl_type) { - default: - case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BBSW: - halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2); - - /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ - halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0x000000ff, 0x77); - - regval_0xcb7 = (switch_polatiry_inverse == false ? 0x1 : 0x2); - - /* 0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ - halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0x30000000, regval_0xcb7); - break; - - case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: - halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2); - - /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ - halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0x000000ff, 0x88); - - /* no regval_0xcb7 setup required, because antenna switch control value by antenna diversity */ - - break; - - } - -} - - -VOID halbtc8821c_wifi_only_set_rfe_type( - IN struct wifi_only_cfg *pwifionlycfg - ) -{ - - /* the following setup should be got from Efuse in the future */ - rfe_type->rfe_module_type = (pwifionlycfg->haldata_info.rfe_type) & 0x1f; - - rfe_type->ext_ant_switch_ctrl_polarity = 0; - - switch (rfe_type->rfe_module_type) { - case 0: - default: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT; /*2-Ant, DPDT, WLG*/ - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = true; - break; - case 1: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, WLG */ - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = true; - break; - case 2: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, BTG */ - rfe_type->wlg_Locate_at_btg = true; - rfe_type->ant_at_main_port = true; - break; - case 3: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, WLG */ - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = false; - break; - case 4: - rfe_type->ext_ant_switch_exist = true; - rfe_type->ext_ant_switch_type = - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, BTG */ - rfe_type->wlg_Locate_at_btg = true; - rfe_type->ant_at_main_port = false; - break; - case 5: - rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_NONE; - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = true; - break; - case 6: - rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_NONE; - rfe_type->wlg_Locate_at_btg = false; - rfe_type->ant_at_main_port = true; - break; - case 7: - rfe_type->ext_ant_switch_exist = true; /*2-Ant, DPDT, BTG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT; - rfe_type->wlg_Locate_at_btg = true; - rfe_type->ant_at_main_port = true; - break; - } - -} - - -VOID -ex_hal8821c_wifi_only_hw_config( - IN struct wifi_only_cfg *pwifionlycfg - ) -{ - halbtc8821c_wifi_only_set_rfe_type(pwifionlycfg); - - /* set gnt_wl, gnt_bt control owner to WL*/ - halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0x400000, 0x1); - - /*gnt_wl=1 , gnt_bt=0*/ - halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700); - halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); -} - -VOID -ex_hal8821c_wifi_only_scannotify( - IN struct wifi_only_cfg *pwifionlycfg, - IN u1Byte is_5g - ) -{ - hal8821c_wifi_only_switch_antenna(pwifionlycfg, is_5g); -} - -VOID -ex_hal8821c_wifi_only_switchbandnotify( - IN struct wifi_only_cfg *pwifionlycfg, - IN u1Byte is_5g - ) -{ - hal8821c_wifi_only_switch_antenna(pwifionlycfg, is_5g); -} - diff --git a/hal/btc/halbtc8821cwifionly.h b/hal/btc/halbtc8821cwifionly.h deleted file mode 100644 index 1949b59..0000000 --- a/hal/btc/halbtc8821cwifionly.h +++ /dev/null @@ -1,84 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ -#ifndef __INC_HAL8821CWIFIONLYHWCFG_H -#define __INC_HAL8821CWIFIONLYHWCFG_H - - -struct rfe_type_8821c_wifi_only { - - u8 rfe_module_type; - boolean ext_ant_switch_exist; - u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */ - u8 ext_ant_switch_ctrl_polarity; /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ - - boolean ant_at_main_port; - - boolean wlg_Locate_at_btg; /* If true: WLG at BTG, If false: WLG at WLAG */ - - boolean ext_ant_switch_diversity; /* If diversity on */ -}; - -enum bt_8821c_wifi_only_ext_ant_switch_type { - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT = 0x0, - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_SPDT = 0x1, - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_NONE = 0x2, - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_MAX -}; - -enum bt_8821c_wifi_only_ext_ant_switch_ctrl_type { - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_MAX -}; - -enum bt_8821c_wifi_only_ext_ant_switch_pos_type { - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_BT = 0x0, - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLG = 0x1, - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLA = 0x2, - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_NOCARE = 0x3, - BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_MAX -}; - - -VOID -hal8821c_wifi_only_switch_antenna( - IN struct wifi_only_cfg *pwifionlycfg, - IN u1Byte is_5g - ); - -VOID -halbtc8821c_wifi_only_set_rfe_type( - IN struct wifi_only_cfg *pwifionlycfg - ); - - -VOID -ex_hal8821c_wifi_only_hw_config( - IN struct wifi_only_cfg *pwifionlycfg - ); -VOID -ex_hal8821c_wifi_only_scannotify( - IN struct wifi_only_cfg *pwifionlycfg, - IN u1Byte is_5g - ); -VOID -ex_hal8821c_wifi_only_switchbandnotify( - IN struct wifi_only_cfg *pwifionlycfg, - IN u1Byte is_5g - ); -#endif diff --git a/hal/btc/halbtc8822b1ant.c b/hal/btc/halbtc8822b1ant.c index 7ec25e2..00f15c4 100644 --- a/hal/btc/halbtc8822b1ant.c +++ b/hal/btc/halbtc8822b1ant.c @@ -1,3 +1,19 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + + /* ************************************************************ * Description: * @@ -15,7 +31,6 @@ #include "mp_precomp.h" - #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) #if (RTL8822B_SUPPORT == 1) @@ -40,9 +55,9 @@ static const char *const glbt_info_src_8822b_1ant[] = { "BT Info[bt auto report]", }; -static u32 glcoex_ver_date_8822b_1ant = 20170518; -static u32 glcoex_ver_8822b_1ant = 0x44; -static u32 glcoex_ver_btdesired_8822b_1ant = 0x42; +u32 glcoex_ver_date_8822b_1ant = 20180427; +u32 glcoex_ver_8822b_1ant = 0x59; +u32 glcoex_ver_btdesired_8822b_1ant = 0x56; /* ************************************************************ @@ -51,20 +66,19 @@ static u32 glcoex_ver_btdesired_8822b_1ant = 0x42; * ************************************************************ * local function start with halbtc8822b1ant_ * ************************************************************ */ -#if 0 static u8 halbtc8822b1ant_bt_rssi_state(IN struct btc_coexist *btcoexist, - u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) + u8 *ppre_bt_rssi_state, u8 level_num, + u8 rssi_thresh, u8 rssi_thresh1) { - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; + s32 bt_rssi = 0; + u8 bt_rssi_state = *ppre_bt_rssi_state; bt_rssi = coex_sta->bt_rssi; if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { + if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { if (bt_rssi >= (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) bt_rssi_state = BTC_RSSI_STATE_HIGH; @@ -79,23 +93,20 @@ u8 halbtc8822b1ant_bt_rssi_state(IN struct btc_coexist *btcoexist, } else if (level_num == 3) { if (rssi_thresh > rssi_thresh1) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Rssi thresh error!!\n"); + "[BTCoex], BT Rssi thresh error!!\n"); BTC_TRACE(trace_buf); - return coex_sta->pre_bt_rssi_state; + return *ppre_bt_rssi_state; } - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { + if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { if (bt_rssi >= (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) bt_rssi_state = BTC_RSSI_STATE_MEDIUM; else bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { + } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { if (bt_rssi >= (rssi_thresh1 + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) bt_rssi_state = BTC_RSSI_STATE_HIGH; @@ -111,26 +122,25 @@ u8 halbtc8822b1ant_bt_rssi_state(IN struct btc_coexist *btcoexist, } } - coex_sta->pre_bt_rssi_state = bt_rssi_state; + *ppre_bt_rssi_state = bt_rssi_state; return bt_rssi_state; } -#endif + static u8 halbtc8822b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) + IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh, + IN u8 rssi_thresh1) { - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; + s32 wifi_rssi = 0; + u8 wifi_rssi_state = *pprewifi_rssi_state; btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { + if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { if (wifi_rssi >= (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) wifi_rssi_state = BTC_RSSI_STATE_HIGH; @@ -145,24 +155,20 @@ u8 halbtc8822b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, } else if (level_num == 3) { if (rssi_thresh > rssi_thresh1) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi RSSI thresh error!!\n"); + "[BTCoex], wifi RSSI thresh error!!\n"); BTC_TRACE(trace_buf); - return coex_sta->pre_wifi_rssi_state[index]; + return *pprewifi_rssi_state; } - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { + if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { if (wifi_rssi >= (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; else wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { + } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { if (wifi_rssi >= (rssi_thresh1 + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT)) wifi_rssi_state = BTC_RSSI_STATE_HIGH; @@ -178,142 +184,11 @@ u8 halbtc8822b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, } } - coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; + *pprewifi_rssi_state = wifi_rssi_state; return wifi_rssi_state; } -static -void halbtc8822b1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) -{ - coex_dm->cur_ra_mask = dis_rate_mask; - - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; -} - -static -void halbtc8822b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - boolean wifi_under_b_mode = FALSE; - - coex_dm->cur_arfr_type = type; - - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } - } - - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -static -void halbtc8822b1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } - - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; -} - -static -void halbtc8822b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } - - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} - -static -void halbtc8822b1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8822b1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8822b1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8822b1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } - - halbtc8822b1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8822b1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8822b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); -} - /* * rx agg size setting : * 1: TRUE / don't care / don't care @@ -346,7 +221,6 @@ void halbtc8822b1ant_limited_rx(IN struct btc_coexist *btcoexist, } -static void halbtc8822b1ant_query_bt_info(IN struct btc_coexist *btcoexist) { u8 h2c_parameter[1] = {0}; @@ -378,20 +252,6 @@ void halbtc8822b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_autoslot_hang = 0; struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; -#if 0 - /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ - if (!(btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8)) -#endif - -#if 0 - if (coex_sta->under_ips) { - /* coex_sta->high_priority_tx = 65535; */ - /* coex_sta->high_priority_rx = 65535; */ - /* coex_sta->low_priority_tx = 65535; */ - /* coex_sta->low_priority_rx = 65535; */ - /* return; */ - } -#endif reg_hp_txrx = 0x770; reg_lp_txrx = 0x774; @@ -448,21 +308,19 @@ void halbtc8822b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) if (cnt_autoslot_hang >= 2) { coex_sta->is_tdma_btautoslot_hang = TRUE; cnt_autoslot_hang = 2; - } else { + } else cnt_autoslot_hang++; - } } else { if (cnt_autoslot_hang == 0) { coex_sta->is_tdma_btautoslot_hang = FALSE; cnt_autoslot_hang = 0; - } else { + } else cnt_autoslot_hang--; - } } } if (bt_link_info->hid_only) { - if (coex_sta->low_priority_rx > 50) + if (coex_sta->low_priority_tx > 50) coex_sta->is_hid_low_pri_tx_overhead = true; else coex_sta->is_hid_low_pri_tx_overhead = false; @@ -484,16 +342,28 @@ void halbtc8822b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) } -static void halbtc8822b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) { -#if 1 s32 wifi_rssi = 0; boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE, wifi_scan = FALSE; + boolean bt_idle = FALSE, wl_idle = FALSE; static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, wl_noisy_count1 = 3, wl_noisy_count2 = 0; - u32 total_cnt, cck_cnt; + u32 total_cnt, reg_val1, reg_val2, cnt_cck; + static u8 cnt = 0, cnt_ccklocking = 0; + u8 h2c_parameter[1] = {0}; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + /* Only enable for windows becaus 8821cu H2C 0x69 unknown fail @ linux */ + if (btcoexist->chip_interface != BTC_INTF_USB) { + /*send h2c to query WL FW dbg info */ + if (((coex_dm->cur_ps_tdma_on) && (coex_sta->force_lps_ctrl)) || + ((coex_sta->acl_busy) && (bt_link_info->a2dp_exist))) { + h2c_parameter[0] = 0x8; + btcoexist->btc_fill_h2c(btcoexist, 0x69, 1, h2c_parameter); + } + } btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); @@ -520,93 +390,62 @@ void halbtc8822b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter( btcoexist, PHYDM_INFO_CRC32_ERROR_VHT); - cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; - - if (cck_cnt > 250) { - if (wl_noisy_count2 < 3) - wl_noisy_count2++; + /* CCK lock identification */ + if (coex_sta->cck_lock) + cnt_ccklocking++; + else if (cnt_ccklocking != 0) + cnt_ccklocking--; - if (wl_noisy_count2 == 3) { - wl_noisy_count0 = 0; - wl_noisy_count1 = 0; - } + if (cnt_ccklocking >= 3) { + cnt_ccklocking = 3; + coex_sta->cck_lock_ever = TRUE; + } - } else if (cck_cnt < 50) { - if (wl_noisy_count0 < 3) - wl_noisy_count0++; + /* WiFi environment noisy identification */ + cnt_cck = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; - if (wl_noisy_count0 == 3) { - wl_noisy_count1 = 0; - wl_noisy_count2 = 0; - } + if ((!wifi_busy) && (!coex_sta->cck_lock)) { + if (cnt_cck > 250) { + if (wl_noisy_count2 < 3) + wl_noisy_count2++; - } else { - if (wl_noisy_count1 < 3) - wl_noisy_count1++; + if (wl_noisy_count2 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count1 = 0; + } - if (wl_noisy_count1 == 3) { - wl_noisy_count0 = 0; - wl_noisy_count2 = 0; - } - } + } else if (cnt_cck < 100) { + if (wl_noisy_count0 < 3) + wl_noisy_count0++; - if (wl_noisy_count2 == 3) - coex_sta->wl_noisy_level = 2; - else if (wl_noisy_count1 == 3) - coex_sta->wl_noisy_level = 1; - else - coex_sta->wl_noisy_level = 0; - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht; - - if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY) - || - (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; + if (wl_noisy_count0 == 3) { + wl_noisy_count1 = 0; + wl_noisy_count2 = 0; } } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } + if (wl_noisy_count1 < 3) + wl_noisy_count1++; - if (!coex_sta->pre_ccklock) { + if (wl_noisy_count1 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count2 = 0; + } + } - if (cck_lock_counter >= 3) - coex_sta->cck_lock = TRUE; - else - coex_sta->cck_lock = FALSE; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = FALSE; + if (wl_noisy_count2 == 3) + coex_sta->wl_noisy_level = 2; + else if (wl_noisy_count1 == 3) + coex_sta->wl_noisy_level = 1; else - coex_sta->cck_lock = TRUE; + coex_sta->wl_noisy_level = 0; } - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = TRUE; - - coex_sta->pre_ccklock = coex_sta->cck_lock; - -#endif } static -boolean halbtc8822b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) +boolean halbtc8822b1ant_is_wifibt_status_changed(IN struct btc_coexist *btcoexist) { static boolean pre_wifi_busy = FALSE, pre_under_4way = FALSE, pre_bt_hs_on = FALSE, pre_rf4ce_enabled = FALSE, pre_bt_off = FALSE, @@ -616,13 +455,26 @@ boolean halbtc8822b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE, rf4ce_enabled = FALSE; boolean wifi_connected = FALSE; struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + static u8 cnt_wifi_busytoidle = 0; + u32 wifi_link_status = 0, num_of_wifi_link = 0; + static u32 pre_num_of_wifi_link = 0; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + + if (wifi_busy) { + coex_sta->gl_wifi_busy = TRUE; + cnt_wifi_busytoidle = 3; + } else { + if ((coex_sta->gl_wifi_busy) && (cnt_wifi_busytoidle > 0)) + cnt_wifi_busytoidle--; + else if (cnt_wifi_busytoidle == 0) + coex_sta->gl_wifi_busy = FALSE; + } if (coex_sta->bt_disabled != pre_bt_off) { pre_bt_off = coex_sta->bt_disabled; @@ -638,11 +490,29 @@ boolean halbtc8822b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) coex_sta->bt_coex_supported_feature = 0; coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + coex_sta->legacy_forbidden_slot = 0; + coex_sta->le_forbidden_slot = 0; + coex_sta->bt_a2dp_vendor_id = 0; + coex_sta->bt_a2dp_device_name = 0; + return TRUE; + } + + num_of_wifi_link = wifi_link_status >> 16; + + if (num_of_wifi_link != pre_num_of_wifi_link) { + pre_num_of_wifi_link = num_of_wifi_link; return TRUE; } + btcoexist->btc_get(btcoexist, BTC_GET_BL_RF4CE_CONNECTED, &rf4ce_enabled); - if (rf4ce_enabled != pre_rf4ce_enabled) { + if (rf4ce_enabled != pre_rf4ce_enabled) { pre_rf4ce_enabled = rf4ce_enabled; if (rf4ce_enabled) @@ -654,7 +524,6 @@ boolean halbtc8822b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) BTC_TRACE(trace_buf); - return TRUE; } @@ -677,7 +546,7 @@ boolean halbtc8822b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) } if (coex_sta->under_lps != pre_wifi_under_lps) { pre_wifi_under_lps = coex_sta->under_lps; - if (coex_sta->under_lps) + if (coex_sta->under_lps == TRUE) return TRUE; } } @@ -709,13 +578,39 @@ boolean halbtc8822b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist) -static void halbtc8822b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) { struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; boolean bt_hs_on = FALSE; boolean bt_busy = FALSE; + u32 val = 0; + static u8 pre_num_of_profile = 0, cur_num_of_profile = 0, cnt = 0; + boolean increase_scan_dev_num = FALSE; + static u8 wd_cnt = 0; + if (++wd_cnt >= 3) + wd_cnt = 0; + + if (coex_sta->is_ble_scan_en && (wd_cnt == 0)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + BTC_TRACE(trace_buf); + coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( + btcoexist); + + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x4); + } coex_sta->num_of_profile = 0; @@ -726,36 +621,37 @@ void halbtc8822b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) coex_sta->a2dp_exist = FALSE; coex_sta->hid_exist = FALSE; coex_sta->sco_exist = FALSE; + coex_sta->msft_mr_exist = FALSE; } else { /* connection exists */ coex_sta->bt_link_exist = TRUE; if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_FTP) { coex_sta->pan_exist = TRUE; coex_sta->num_of_profile++; - } else { + } else coex_sta->pan_exist = FALSE; - } if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_A2DP) { coex_sta->a2dp_exist = TRUE; coex_sta->num_of_profile++; - } else { + } else coex_sta->a2dp_exist = FALSE; - } if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_HID) { coex_sta->hid_exist = TRUE; coex_sta->num_of_profile++; - } else { + } else coex_sta->hid_exist = FALSE; - } if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) { coex_sta->sco_exist = TRUE; coex_sta->num_of_profile++; - } else { + } else coex_sta->sco_exist = FALSE; - } + if ((coex_sta->hid_busy_num == 0) && (coex_sta->hid_pair_cnt > 0)) + coex_sta->msft_mr_exist = true; + else + coex_sta->msft_mr_exist = false; } btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); @@ -819,9 +715,16 @@ void halbtc8822b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); } else if (coex_sta->bt_info == BT_INFO_8822B_1ANT_B_CONNECTION) { /* connection exists but no busy */ + + if (coex_sta->msft_mr_exist) { + coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!\n"); + } else { coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + } } else if (((coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) || (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_BUSY)) && (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_ACL_BUSY)) { @@ -847,12 +750,59 @@ void halbtc8822b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) || (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY) || - (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY)) + (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY)) { bt_busy = TRUE; - else + increase_scan_dev_num = TRUE; + } else { bt_busy = FALSE; + increase_scan_dev_num = FALSE; + } btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, + &increase_scan_dev_num); + + cur_num_of_profile = coex_sta->num_of_profile; + + if (cur_num_of_profile != pre_num_of_profile) + cnt = 2; + + if (bt_link_info->a2dp_exist) { + + if (((coex_sta->bt_a2dp_vendor_id == 0) && + (coex_sta->bt_a2dp_device_name == 0)) || + (cur_num_of_profile != pre_num_of_profile)) { + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_DEVICE_INFO, &val); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), get BT DEVICE_INFO = %x\n", val); + BTC_TRACE(trace_buf); + + coex_sta->bt_a2dp_vendor_id = (u8)(val & 0xff); + coex_sta->bt_a2dp_device_name = (val & 0xffffff00) >> 8; + } + + if (((coex_sta->legacy_forbidden_slot == 0) && + (coex_sta->le_forbidden_slot == 0)) || + (cur_num_of_profile != pre_num_of_profile) || + (cnt > 0)) { + + if (cnt > 0) + cnt--; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL, &val); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), get BT FORBIDDEN_SLOT_VAL = %x\n", val); + BTC_TRACE(trace_buf); + + coex_sta->legacy_forbidden_slot = (u16)(val & 0xffff); + coex_sta->le_forbidden_slot = (u16)((val & 0xffff0000) >> 16); + } + } + + pre_num_of_profile = coex_sta->num_of_profile; } @@ -860,28 +810,46 @@ static void halbtc8822b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, IN u8 type) { - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; + u8 h2c_parameter[3] = {0}, i; + u32 wifi_bw; + u8 wifi_central_chnl = 0; + u8 wifi_5g_chnl[19] = {120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 118, 126, 134, 142, 151, 159, 122, 138, 155}; + u8 bt_skip_cneter_chanl[19] = {2, 8, 17, 26, 34, 42, 51, 62, 71, 77, 2, 12, 29, 46, 66, 76, 10, 37, 68}; + u8 bt_skip_span[19] = {4, 8, 8, 10, 8, 10, 8, 8, 10, 4, 4, 16, 16, 16, 16, 4, 20, 34, 20}; + boolean wifi_under_5g = FALSE; - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - /* enable BT AFH skip WL channel for 8822b - * because BT Rx LO interference - */ - h2c_parameter[0] = 0x1; - h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (type == BTC_MEDIA_CONNECT) { + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + coex_sta->wl_center_channel = wifi_central_chnl; - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; + if (!wifi_under_5g) { + + h2c_parameter[0] = 0x1; + h2c_parameter[1] = wifi_central_chnl; + + if (wifi_bw == BTC_WIFI_BW_HT40) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x30; + } else { /* for 5G */ + + for (i = 0; i <= 18; i++) { + if (wifi_central_chnl == wifi_5g_chnl[i]) + break; + } + + if (i <= 18) { + h2c_parameter[0] = 0x3; + h2c_parameter[1] = bt_skip_cneter_chanl[i]; + h2c_parameter[2] = bt_skip_span[i]; + } + + } } coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; @@ -890,8 +858,14 @@ void halbtc8822b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], para[0:2] = 0x%x 0x%x 0x%x\n", + h2c_parameter[0], h2c_parameter[1], h2c_parameter[2]); + BTC_TRACE(trace_buf); + } + static u8 halbtc8822b1ant_action_algorithm(IN struct btc_coexist *btcoexist) { @@ -1098,52 +1072,6 @@ u8 halbtc8822b1ant_action_algorithm(IN struct btc_coexist *btcoexist) } - - - - - -static -void halbtc8822b1ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - u32 RTL97F_8822B = 0; - - if (RTL97F_8822B) - return; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - - -static -void halbtc8822b1ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - u32 RTL97F_8822B = 0; - - if (RTL97F_8822B) - return; - - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8822b1ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - static void halbtc8822b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN boolean low_penalty_ra) @@ -1158,7 +1086,7 @@ void halbtc8822b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, } if (low_penalty_ra) - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25); + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 10); else btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); @@ -1168,23 +1096,57 @@ void halbtc8822b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, } static -void halbtc8822b1ant_write_score_board( - IN struct btc_coexist *btcoexist, - IN u16 bitpos, - IN boolean state -) +void halbtc8822b1ant_mimo_ps( + IN struct btc_coexist *btcoexist, + IN boolean force_exec, + IN u8 state) { + static u8 pre_state = 0; + + if (!force_exec) { + if (state == pre_state) + return; + } + + pre_state = state; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b1ant_mimo_ps(), state = %d\n", state); + BTC_TRACE(trace_buf); + + btcoexist->btc_set(btcoexist, BTC_SET_MIMO_PS_MODE, &state); +} + + +static +void halbtc8822b1ant_write_score_board( + IN struct btc_coexist *btcoexist, + IN u16 bitpos, + IN boolean state +) +{ + + static u16 originalval = 0x8002, preval = 0x0; - static u16 originalval = 0x8002; - if (state) originalval = originalval | bitpos; else originalval = originalval & (~bitpos); - btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); + coex_sta->score_board_WB = originalval; + + if (originalval != preval) { + + preval = originalval; + btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b1ant_write_score_board: return for nochange\n"); + BTC_TRACE(trace_buf); + } } + static void halbtc8822b1ant_read_score_board( IN struct btc_coexist *btcoexist, @@ -1208,6 +1170,115 @@ void halbtc8822b1ant_post_state_to_bt( } +static +void halbtc8822b1ant_adjust_wl_tx_power(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 fw_dac_swing_lvl) +{ + + coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; + + if (!force_exec) { + if (coex_dm->pre_fw_dac_swing_lvl == + coex_dm->cur_fw_dac_swing_lvl) + return; + } + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0xff, fw_dac_swing_lvl); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe5b, 0xff, fw_dac_swing_lvl); + + coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; +} + +static +void halbtc8822b1ant_adjust_bt_tx_power(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 dec_bt_pwr_lvl) +{ + u8 h2c_parameter[1] = {0}; + + coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; + + if (!force_exec) { + if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) + return; + } + + h2c_parameter[0] = 0 - dec_bt_pwr_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); + + coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; +} + +static +void halbtc8822b1ant_adjust_wl_rx_gain(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean agc_table_en) +{ +u32 rx_gain_value_enable[] = {0xff000003, 0xea240003, 0xe9260003, + 0xe8280003, 0xe72a0003, 0xe62c0003, 0xaf2e0003, 0xae300003, + 0xad320003, 0xac340003, 0xab360003, 0x8d380003, 0x8c3a0003, + 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 0x6c440003, + 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 0x674e0003, + 0x66500003, 0x65520003, 0x64540003, 0x64560003, 0x007e0403}; + +u32 rx_gain_value_disable[] = {0xff000003, 0xeb240003, 0xea260003, + 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 0xe5300003, + 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 0xc43a0003, + 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 0xa5440003, + 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 0x834e0003, + 0x82500003, 0x81520003, 0x80540003, 0x65560003, 0x007e0403}; + + u8 i; + + coex_dm->cur_agc_table_en = agc_table_en; + + if (!force_exec) { + if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) + return; + } + + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table On!\n"); + BTC_TRACE(trace_buf); + + for (i = 0; i <= 100; i++) { + btcoexist->btc_write_4byte(btcoexist, + 0x81c, rx_gain_value_enable[i]); + + if (rx_gain_value_enable[i] == 0x007e0403) + break; + } + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table Off!\n"); + BTC_TRACE(trace_buf); + + for (i = 0; i <= 100; i++) { + btcoexist->btc_write_4byte(btcoexist, + 0x81c, rx_gain_value_disable[i]); + + if (rx_gain_value_disable[i] == 0x007e0403) + break; + } + } + + + coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; +} + +static +void halbtc8822b1ant_adjust_bt_rx_gain(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rx_gain_en) +{ + + /* use scoreboard[4] to notify BT Rx gain table change */ + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_RXGAIN, + rx_gain_en); +} + + static void halbtc8822b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) @@ -1280,6 +1351,15 @@ void halbtc8822b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) (bt_disabled ? "disabled" : "enabled")); BTC_TRACE(trace_buf); coex_sta->bt_disabled = bt_disabled; + + /*for win10 RS3 BT disable->enable trigger wifi scan issue */ + if (!coex_sta->bt_disabled) { + coex_sta->is_bt_reenable = TRUE; + coex_sta->cnt_bt_reenable = 15; + } else { + coex_sta->is_bt_reenable = FALSE; + coex_sta->cnt_bt_reenable = 0; + } } } @@ -1350,24 +1430,22 @@ void halbtc8822b1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, -static u32 halbtc8822b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, IN u16 reg_addr) { - u32 delay_count = 0; + u32 j = 0, delay_count = 0; /* wait for ready bit before access 0x1700 */ while (1) { if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { - delay_ms(50); + delay_ms(10); delay_count++; if (delay_count >= 10) { delay_count = 0; break; } - } else { + } else break; - } } btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr); @@ -1377,12 +1455,11 @@ u32 halbtc8822b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, } -static void halbtc8822b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist *btcoexist, IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) { - u32 val, i = 0, bitpos = 0, delay_count = 0; + u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0; if (bit_mask == 0x0) @@ -1392,15 +1469,14 @@ void halbtc8822b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist /* wait for ready bit before access 0x1700/0x1704 */ while (1) { if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { - delay_ms(50); + delay_ms(10); delay_count++; if (delay_count >= 10) { delay_count = 0; break; } - } else { + } else break; - } } btcoexist->btc_write_4byte(btcoexist, 0x1704, @@ -1424,15 +1500,14 @@ void halbtc8822b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist /* wait for ready bit before access 0x1700/0x1704 */ while (1) { if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { - delay_ms(50); + delay_ms(10); delay_count++; if (delay_count >= 10) { delay_count = 0; break; } - } else { + } else break; - } } btcoexist->btc_write_4byte(btcoexist, 0x1704, @@ -1446,7 +1521,6 @@ void halbtc8822b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist } -static void halbtc8822b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist, IN boolean enable) { @@ -1460,7 +1534,6 @@ void halbtc8822b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist, -static void halbtc8822b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, IN boolean wifi_control) { @@ -1473,7 +1546,6 @@ void halbtc8822b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, } -static void halbtc8822b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, IN u8 control_block, IN boolean sw_control, IN u8 state) { @@ -1512,7 +1584,6 @@ void halbtc8822b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, } -static void halbtc8822b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, IN u8 control_block, IN boolean sw_control, IN u8 state) { @@ -1551,7 +1622,6 @@ void halbtc8822b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, } -static void halbtc8822b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, IN u8 table_type, IN u16 table_content) { @@ -1575,8 +1645,7 @@ void halbtc8822b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, -#if 0 -static + void halbtc8822b1ant_ltcoex_set_break_table(IN struct btc_coexist *btcoexist, IN u8 table_type, IN u8 table_content) { @@ -1603,12 +1672,10 @@ void halbtc8822b1ant_ltcoex_set_break_table(IN struct btc_coexist *btcoexist, } -#endif -static void halbtc8822b1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN u8 interval, IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, @@ -1646,7 +1713,6 @@ void halbtc8822b1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, -static void halbtc8822b1ant_set_coex_table(IN struct btc_coexist *btcoexist, IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) { @@ -1660,7 +1726,6 @@ void halbtc8822b1ant_set_coex_table(IN struct btc_coexist *btcoexist, } -static void halbtc8822b1ant_coex_table(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) @@ -1689,7 +1754,6 @@ void halbtc8822b1ant_coex_table(IN struct btc_coexist *btcoexist, } -static void halbtc8822b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN u8 type) { @@ -1697,14 +1761,14 @@ void halbtc8822b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, u8 select_table; - coex_sta->coex_table_type = type; - if (coex_sta->concurrent_rx_mode_on) { - break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ - select_table = 0x3; /* set Tx response = Hi-Pri - * (ex: Transmitting ACK,BA,CTS) - */ + if (coex_sta->concurrent_rx_mode_on == TRUE) { + /* set WL hi-pri can break BT */ + break_table = 0xf0ffffff; + /* set Tx response = Hi-Pri + (ex: Transmitting ACK,BA,CTS) */ + select_table = 0xb; } else { break_table = 0xffffff; select_table = 0x3; @@ -1713,121 +1777,144 @@ void halbtc8822b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, switch (type) { case 0: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, break_table, - select_table); + 0x55555555, 0x55555555, break_table, + select_table); break; case 1: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, - select_table); + 0x55555555, 0x5a5a5a5a, break_table, + select_table); break; case 2: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0xaa5a5a5a, 0xaa5a5a5a, break_table, - select_table); + 0x65555555, 0xaaaaaaaa, break_table, + select_table); break; case 3: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaa5a5a5a, break_table, - select_table); + 0x65555555, 0x6a5a5a5a, break_table, + select_table); break; case 4: - halbtc8822b1ant_coex_table(btcoexist, - force_exec, 0xaa555555, 0xaa5a5a5a, - break_table, select_table); + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xaa555555, 0xaa5a5a5a, break_table, + select_table); break; case 5: - halbtc8822b1ant_coex_table(btcoexist, - force_exec, 0x5a5a5a5a, 0x5a5a5a5a, - break_table, select_table); + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, break_table, + select_table); break; case 6: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaaaaaa, break_table, - select_table); + 0x55555555, 0xaa5a5a5a, break_table, + select_table); break; case 7: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, break_table, - select_table); + 0x65555555, 0xaaaa5aaa, break_table, + select_table); break; case 8: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0xffffffff, 0xffffffff, break_table, - select_table); + 0xffffffff, 0xffffffff, break_table, + select_table); break; case 9: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x5a5a5555, 0xaaaa5a5a, break_table, - select_table); + 0x65555555, 0xaaaaaaaa, break_table, + select_table); break; case 10: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0xaaaa5aaa, 0xaaaa5aaa, break_table, - select_table); + 0xaa5555aa, 0xaaaaaaaa, break_table, + select_table); break; case 11: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0xaaaaa5aa, 0xaaaaaaaa, break_table, - select_table); + 0xa5a55555, 0xaaaa5a5a, break_table, + select_table); break; case 12: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0xaaaaa5aa, 0xaaaaa5aa, break_table, - select_table); + 0xaaaaa5aa, 0xaaaaa5aa, break_table, + select_table); break; case 13: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaa5a5a, break_table, - select_table); + 0xaa5555aa, 0x6a5a5a5a, break_table, + select_table); break; case 14: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x5a5a555a, 0xaaaa5a5a, break_table, - select_table); + 0xaa5555aa, 0x5a5a5a5a, break_table, + select_table); break; case 15: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaa55aa, break_table, - select_table); + 0x55555555, 0xaaaa55aa, break_table, + select_table); break; case 16: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x5a5a555a, 0x5a5a555a, break_table, - select_table); + 0x5a5a555a, 0x5a5a555a, break_table, + select_table); break; case 17: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0xaaaa55aa, 0xaaaa55aa, break_table, - select_table); + 0xaaaa55aa, 0xaaaa55aa, break_table, + select_table); break; case 18: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5aaa5a5a, break_table, - select_table); + 0x55555555, 0x5aaa5a5a, break_table, + select_table); break; case 19: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xaaaa5aaa, break_table, - select_table); + 0xa5555555, 0xaaaa5aaa, break_table, + select_table); break; case 20: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xaaaa5aaa, break_table, - select_table); + 0x55555555, 0xaaaa5aaa, break_table, + select_table); break; case 21: halbtc8822b1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555a5a, break_table, - select_table); + 0x55555555, 0xaaaa5afa, break_table, + select_table); + break; + case 22: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xaaffffaa, 0xfafafafa, break_table, + select_table); + break; + case 23: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xffff55ff, 0xfafafafa, break_table, + select_table); + break; + case 24: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xfafafafa, break_table, + select_table); + break; + case 25: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xffffffff, 0xaa5a5a5a, break_table, + select_table); break; + case 26: + halbtc8822b1ant_coex_table(btcoexist, force_exec, + 0xffff55ff, 0xaaaaaaaa, break_table, + select_table); default: break; } } -static void halbtc8822b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, IN boolean enable) { @@ -1842,7 +1929,6 @@ void halbtc8822b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, } -static void halbtc8822b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN boolean enable) { @@ -1865,7 +1951,6 @@ void halbtc8822b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, } -static void halbtc8822b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, IN u8 lps_val, IN u8 rpwm_val) { @@ -1877,7 +1962,6 @@ void halbtc8822b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, } -static void halbtc8822b1ant_lps_rpwm(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) { @@ -1897,7 +1981,6 @@ void halbtc8822b1ant_lps_rpwm(IN struct btc_coexist *btcoexist, -static void halbtc8822b1ant_ps_tdma_check_for_power_save_state( IN struct btc_coexist *btcoexist, IN boolean new_ps_state) { @@ -1930,7 +2013,6 @@ void halbtc8822b1ant_ps_tdma_check_for_power_save_state( -static boolean halbtc8822b1ant_power_save_state(IN struct btc_coexist *btcoexist, IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) { @@ -1941,10 +2023,10 @@ boolean halbtc8822b1ant_power_save_state(IN struct btc_coexist *btcoexist, /* recover to original 32k low power setting */ coex_sta->force_lps_ctrl = FALSE; low_pwr_disable = FALSE; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + /* btcoexist->btc_set(btcoexist, + over to original 32k low power setting */ + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_PRE_NORMAL_LPS, NULL); break; case BTC_PS_LPS_ON: @@ -1983,7 +2065,6 @@ boolean halbtc8822b1ant_power_save_state(IN struct btc_coexist *btcoexist, -static void halbtc8822b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) { @@ -1991,6 +2072,7 @@ void halbtc8822b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, u8 real_byte1 = byte1, real_byte5 = byte5; boolean ap_enable = FALSE, result = FALSE; struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 ps_type = BTC_PS_WIFI_NATIVE; if (byte5 & BIT(2)) coex_sta->is_tdma_btautoslot = TRUE; @@ -2018,8 +2100,9 @@ void halbtc8822b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, real_byte5 |= BIT(5); real_byte5 &= ~BIT(6); + ps_type = BTC_PS_WIFI_NATIVE; halbtc8822b1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, + ps_type, 0x0, 0x0); } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { @@ -2027,14 +2110,18 @@ void halbtc8822b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], halbtc8822b1ant_set_fw_pstdma == Force LPS (byte1 = 0x%x)\n", byte1); BTC_TRACE(trace_buf); - if (!halbtc8822b1ant_power_save_state(btcoexist, BTC_PS_LPS_OFF, 0x50, 0x4)) + + ps_type = BTC_PS_LPS_OFF; + if (!halbtc8822b1ant_power_save_state(btcoexist, ps_type, 0x50, 0x4)) result = TRUE; } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], halbtc8822b1ant_set_fw_pstdma == native power save (byte1 = 0x%x)\n", byte1); BTC_TRACE(trace_buf); + + ps_type = BTC_PS_WIFI_NATIVE; halbtc8822b1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, + ps_type, 0x0, 0x0); } @@ -2063,15 +2150,18 @@ void halbtc8822b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, coex_sta->cnt_set_ps_state_fail); BTC_TRACE(trace_buf); } + + if (ps_type == BTC_PS_WIFI_NATIVE) + btcoexist->btc_set(btcoexist, BTC_SET_ACT_POST_NORMAL_LPS, NULL); } -static void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN boolean turn_on, IN u8 type) { struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + struct btc_board_info *board_info = &btcoexist->board_info; boolean wifi_busy = FALSE; static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; static boolean pre_wifi_busy = FALSE; @@ -2155,7 +2245,7 @@ void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist, break; case 6: halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x20, 0x3, 0x11, 0x10); + 0x61, 0x25, 0x3, 0x11, 0x11); break; case 7: halbtc8822b1ant_set_fw_pstdma(btcoexist, @@ -2167,10 +2257,13 @@ void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist, 0x51, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify); break; + case 10: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x07, 0x10, 0x55); + break; case 11: halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x25, 0x03, 0x11, 0x10 | - psTdmaByte4Modify); + 0x61, 0x25, 0x03, 0x11, 0x11); break; case 12: halbtc8822b1ant_set_fw_pstdma(btcoexist, @@ -2179,8 +2272,7 @@ void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist, break; case 13: halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x07, 0x10, 0x54 | - psTdmaByte4Modify); + 0x51, 0x10, 0x07, 0x10, 0x54); break; case 14: halbtc8822b1ant_set_fw_pstdma(btcoexist, @@ -2199,18 +2291,28 @@ void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist, break; case 18: halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); + 0x51, 0x30, 0x03, 0x10, 0x50); break; - case 20: halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x30, 0x03, 0x11, 0x10); break; + case 21: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x61, 0x30, 0x03, 0x11, 0x10); + break; case 22: halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x25, 0x03, 0x11, 0x10); break; + case 25: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x3a, 0x3, 0x11, 0x50); + break; + case 26: + halbtc8822b1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x55); + break; case 27: halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x10, 0x03, 0x11, 0x15); @@ -2223,50 +2325,21 @@ void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist, halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x35, 0x03, 0x11, 0x10); break; - case 41: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x45, 0x3, 0x11, 0x11); - break; - case 42: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x1e, 0x3, 0x10, 0x14 | - psTdmaByte4Modify); - break; - case 43: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x45, 0x3, 0x10, 0x14); - break; - case 44: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x25, 0x3, 0x10, 0x10); - break; - case 45: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x29, 0x3, 0x10, 0x10); - break; - case 46: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x1a, 0x3, 0x10, 0x10); - break; - case 47: - halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x32, 0x3, 0x10, 0x10); - break; - case 48: + case 36: halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x51, 0x29, 0x3, 0x10, 0x10); + 0x61, 0x50, 0x03, 0x11, 0x10); break; - case 49: + case 37: halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x55, 0x10, 0x3, 0x10, 0x54); - break; + 0x61, 0x3c, 0x03, 0x11, 0x10); + break; case 50: halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x51, 0x4a, 0x3, 0x10, 0x10); break; - case 51: + case 105: halbtc8822b1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x3, 0x10, 0x11); + 0x51, 0x3f, 0x3, 0x10, 0x50); break; } @@ -2277,41 +2350,18 @@ void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist, default: /* Software control, Antenna at BT side */ halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x0, 0x0, 0x0, 0x0, 0x0); -#if 0 - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, - FALSE); -#endif break; -#if 0 -/* 08:1ant:PTA Control -0x778=1-ant hw control,40:2ant:sw control-diversity */ -#endif - case 8: + case 8: /* PTA Control */ halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x8, 0x0, 0x0, 0x0, 0x0); -#if 0 - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, - FALSE); -#endif break; case 9: /* Software control, Antenna at WiFi side */ halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x0, 0x0, 0x0, 0x0, 0x0); -#if 0 - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_WIFI, FORCE_EXEC, FALSE, FALSE); -#endif break; case 10: /* under 5G , 0x778=1*/ halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x0, 0x0, 0x0, 0x0, 0x0); - -#if 0 - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_WIFI5G, FORCE_EXEC, FALSE, - FALSE); -#endif break; } } @@ -2325,33 +2375,27 @@ void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist, } - -static -void halbtc8822b1ant_sw_mechanism(IN struct btc_coexist *btcoexist, - IN boolean low_penalty_ra) -{ - halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); -} - /* rf4 type by efuse, and for ant at main aux inverse use, * because is 2x2, and control types are the same, does not need */ -static void halbtc8822b1ant_set_rfe_type(IN struct btc_coexist *btcoexist) { struct btc_board_info *board_info = &btcoexist->board_info; /* Ext switch buffer mux */ - btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); + btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); /* the following setup should be got from Efuse in the future */ rfe_type->rfe_module_type = board_info->rfe_type; rfe_type->ext_ant_switch_ctrl_polarity = 0; + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; +#if 0 switch (rfe_type->rfe_module_type) { case 0: default: @@ -2395,14 +2439,13 @@ void halbtc8822b1ant_set_rfe_type(IN struct btc_coexist *btcoexist) BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT; break; } - +#endif } /*anttenna control by bb mac bt antdiv pta to write 0x4c 0xcb4,0xcbd*/ -static void halbtc8822b1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) { @@ -2430,7 +2473,7 @@ void halbtc8822b1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, /* swap control polarity if use different switch control polarity*/ /* Normal switch polarity for SPDT, - * 0xcbd[1:0] = 2b'01 => Ant to BTG, + * 0xcbd[1:0] = 2b'01 => Ant to BTG, WLA * 0xcbd[1:0] = 2b'10 => Ant to WLG */ switch_polatiry_inverse = (rfe_type->ext_ant_switch_ctrl_polarity == 1 ? @@ -2441,11 +2484,12 @@ void halbtc8822b1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, default: case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT: case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE: + case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA: + case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_S0WLG_S1BT: break; case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG: - break; - case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA: + break; } @@ -2471,10 +2515,14 @@ void halbtc8822b1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, /* 0xcbd[1:0] = 2b'01 for no switch_polatiry_inverse, * ANTSWB =1, ANTSW =0 */ - regval_0xcbd = (!switch_polatiry_inverse ? 0x1 : 0x2); - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0xcbd, 0x3, - regval_0xcbd); + if (pos_type == BT_8822B_1ANT_EXT_ANT_SWITCH_TO_S0WLG_S1BT) + regval_0xcbd = 0x3; + else if (pos_type == BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG) + regval_0xcbd = (!switch_polatiry_inverse ? 0x2 : 0x1); + else + regval_0xcbd = (!switch_polatiry_inverse ? 0x1 : 0x2); + btcoexist->btc_write_1byte_bitmask(btcoexist, + 0xcbd, 0x3, regval_0xcbd); break; case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: @@ -2554,7 +2602,7 @@ void halbtc8822b1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ext Ant switch setup) 0xcbc = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x**********\n", + "[BTCoex], (After Ext Ant switch setup) 0xcbc = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n", u32tmp1, u32tmp2, u32tmp3); BTC_TRACE(trace_buf); @@ -2567,19 +2615,13 @@ void halbtc8822b1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, */ -static void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist, IN u8 ant_pos_type, IN boolean force_exec, IN u8 phase) { -#if BT_8822B_1ANT_COEX_DBG u8 u8tmp = 0; -#endif - u32 u32tmp1 = 0; -#if BT_8822B_1ANT_COEX_DBG - u32 u32tmp2 = 0, u32tmp3 = 0; -#endif + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); @@ -2626,26 +2668,43 @@ void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist, #endif switch (phase) { + case BT_8822B_1ANT_PHASE_COEX_POWERON: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_COEX_POWERON) **********\n"); + BTC_TRACE(trace_buf); + + /* set Path control owner to BT at power-on step */ + halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8822B_1ANT_PCO_BTSIDE); + + /* set GNT_BT to SW high */ + halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW high */ + halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); + + if (ant_pos_type == BTC_ANT_PATH_AUTO) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = FALSE; + break; case BT_8822B_1ANT_PHASE_COEX_INIT: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_COEX_INIT) **********\n"); BTC_TRACE(trace_buf); - /* Disable LTE Coex Function in WiFi side - * (this should be on if LTE coex is required) - */ halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0); - /* GNT_WL_LTE always = 1 - * (this should be config if LTE coex is required) - */ + halbtc8822b1ant_ltecoex_set_coex_table(btcoexist, BT_8822B_1ANT_CTT_WL_VS_LTE, 0xffff); - /* GNT_BT_LTE always = 1 - * (this should be config if LTE coex is required) - */ halbtc8822b1ant_ltecoex_set_coex_table(btcoexist, BT_8822B_1ANT_CTT_BT_VS_LTE, 0xffff); @@ -2668,13 +2727,6 @@ void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist, coex_sta->run_time_state = FALSE; - /* Ext switch buffer mux */ - btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, - 0x3, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, - 0x8, 0x0); - if (BTC_ANT_PATH_AUTO == ant_pos_type) ant_pos_type = BTC_ANT_PATH_BT; @@ -2684,21 +2736,12 @@ void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist, "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLANONLY_INIT) **********\n"); BTC_TRACE(trace_buf); - /* Disable LTE Coex Function in WiFi side - * (this should be on if LTE coex is required) - */ halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0); - /* GNT_WL_LTE always = 1 - * (this should be config if LTE coex is required) - */ halbtc8822b1ant_ltecoex_set_coex_table(btcoexist, BT_8822B_1ANT_CTT_WL_VS_LTE, 0xffff); - /* GNT_BT_LTE always = 1 - * (this should be config if LTE coex is required) - */ halbtc8822b1ant_ltecoex_set_coex_table(btcoexist, BT_8822B_1ANT_CTT_BT_VS_LTE, 0xffff); @@ -2721,13 +2764,6 @@ void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist, coex_sta->run_time_state = FALSE; - /* Ext switch buffer mux */ - btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, - 0x3, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, - 0x8, 0x0); - if (BTC_ANT_PATH_AUTO == ant_pos_type) ant_pos_type = BTC_ANT_PATH_WIFI; @@ -2781,21 +2817,24 @@ void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist, break; case BT_8822B_1ANT_PHASE_5G_RUNTIME: + case BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL: + case BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_BT: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_5G_RUNTIME) **********\n"); + "[BTCoex], ********** (set_ant_path - %d)\n", phase); BTC_TRACE(trace_buf); /* set GNT_BT to SW Hi */ halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); /* Set GNT_WL to SW Hi */ halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_SW, + BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); /* set Path control owner to WL at runtime step */ halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, @@ -2803,9 +2842,12 @@ void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist, coex_sta->run_time_state = TRUE; + if (phase == BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL) + ant_pos_type = BTC_ANT_PATH_WIFI; + else if (phase == BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_BT) + ant_pos_type = BTC_ANT_PATH_BT; if (BTC_ANT_PATH_AUTO == ant_pos_type) - ant_pos_type = - BTC_ANT_PATH_WIFI5G; + ant_pos_type = BTC_ANT_PATH_WIFI5G; break; case BT_8822B_1ANT_PHASE_BTMPMODE: @@ -2838,21 +2880,56 @@ void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist, if (BTC_ANT_PATH_AUTO == ant_pos_type) ant_pos_type = BTC_ANT_PATH_BT; + break; + case BT_8822B_1ANT_PHASE_MCC_DUALBAND_RUNTIME: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (set_ant_path - 1ANT_PHASE_MCC_DUALBAND_RUNTIME)\n"); + BTC_TRACE(trace_buf); + + /* set GNT_BT to PTA */ + halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_PTA, + BT_8822B_1ANT_SIG_STA_SET_BY_HW); + + /* Set GNT_WL to PTA */ + halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8822B_1ANT_GNT_BLOCK_RFC_BB, + BT_8822B_1ANT_GNT_CTRL_BY_PTA, + BT_8822B_1ANT_SIG_STA_SET_BY_HW); + + /* set Path control owner to WL at runtime step */ + halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8822B_1ANT_PCO_WLSIDE); + + coex_sta->run_time_state = TRUE; + + if (ant_pos_type == BTC_ANT_PATH_AUTO) + ant_pos_type = BTC_ANT_PATH_PTA; + break; } - if (phase != BT_8822B_1ANT_PHASE_WLAN_OFF) { + if ((phase != BT_8822B_1ANT_PHASE_WLAN_OFF) && + (phase != BT_8822B_1ANT_PHASE_MCC_DUALBAND_RUNTIME)) { switch (ant_pos_type) { case BTC_ANT_PATH_WIFI: + if (phase == BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL) { + halbtc8822b1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8822B_1ANT_EXT_ANT_SWITCH_TO_S0WLG_S1BT); + } else { halbtc8822b1ant_set_ext_ant_switch( btcoexist, force_exec, BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG); + } break; - case BTC_ANT_PATH_WIFI5G - : + case BTC_ANT_PATH_WIFI5G: halbtc8822b1ant_set_ext_ant_switch( btcoexist, force_exec, @@ -2880,12 +2957,12 @@ void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist, #if BT_8822B_1ANT_COEX_DBG u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcbd); u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", + "[BTCoex], (After Ant Setup) 0xcbd = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", u32tmp3, u8tmp, u32tmp1, u32tmp2); BTC_TRACE(trace_buf); @@ -2893,156 +2970,6 @@ void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist, } - - -static -void halbtc8822b1ant_set_rx_gain(IN struct btc_coexist *btcoexist, - IN boolean agc_table_en) -{ - u8 rssi_adjust_val = 0; - - /* =================BB AGC Gain Table */ - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table On!\n"); - BTC_TRACE(trace_buf); - - - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_2ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - btcoexist->btc_write_1byte(btcoexist, 0xc5b, 0xc8); - btcoexist->btc_write_1byte(btcoexist, 0xe5b, 0xc8); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xff000003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xae2e0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xad300003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xac320003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xab360003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8d380003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8c3a0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8b3c0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8a3e0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6e400003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6d420003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6c440003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6b460003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6a480003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x694a0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x684c0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x674e0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x66500003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x65520003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x64540003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x64560003); - - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x007e0403); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table Off!\n"); - BTC_TRACE(trace_buf); - - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - btcoexist->btc_write_1byte(btcoexist, 0xc5b, 0xd8); - btcoexist->btc_write_1byte(btcoexist, 0xe5b, 0xd8); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xff000003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xe62e0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xe5300003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc8320003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc6360003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc5380003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc43a0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc33c0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc23e0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc1400003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc0420003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa5440003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa4460003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa3480003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa24a0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa14c0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x834e0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x82500003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x81520003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x80540003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x65560003); - - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x007e0403); - } - - -} - - -static -void halbtc8822b1ant_rx_gain(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean agc_table_en) -{ - coex_dm->cur_agc_table_en = agc_table_en; - - if (!force_exec) { - if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) - return; - } - halbtc8822b1ant_set_rx_gain(btcoexist, agc_table_en); - - coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; -} - - -static -void halbtc8822b1ant_action_bt_idle(IN struct btc_coexist *btcoexist) -{ - - boolean wifi_busy = FALSE; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (bt idle) **********\n"); - BTC_TRACE(trace_buf); - - if (!wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (bt idle wl not busy) **********\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - } else { /* if wl busy */ - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - - if (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, - 8); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** else(bt non connect idle wl not busy) **********\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 12); - } - } - -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif -} - - -static boolean halbtc8822b1ant_is_common_action(IN struct btc_coexist *btcoexist) { boolean common = FALSE, wifi_connected = FALSE, wifi_busy = FALSE; @@ -3056,9 +2983,6 @@ boolean halbtc8822b1ant_is_common_action(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); BTC_TRACE(trace_buf); - - /* halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); */ - common = TRUE; } else if (wifi_connected && (coex_dm->bt_status == @@ -3066,9 +2990,6 @@ boolean halbtc8822b1ant_is_common_action(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi connected + BT non connected-idle!!\n"); BTC_TRACE(trace_buf); - - /* halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); */ - common = TRUE; } else if (!wifi_connected && (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == @@ -3076,9 +2997,6 @@ boolean halbtc8822b1ant_is_common_action(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); BTC_TRACE(trace_buf); - - /* halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); */ - common = TRUE; } else if (wifi_connected && (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == @@ -3086,9 +3004,6 @@ boolean halbtc8822b1ant_is_common_action(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi connected + BT connected-idle!!\n"); BTC_TRACE(trace_buf); - - /* halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); */ - common = TRUE; } else if (!wifi_connected && (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE != @@ -3096,9 +3011,6 @@ boolean halbtc8822b1ant_is_common_action(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); BTC_TRACE(trace_buf); - - /* halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); */ - common = TRUE; } else { if (wifi_busy) { @@ -3117,250 +3029,176 @@ boolean halbtc8822b1ant_is_common_action(IN struct btc_coexist *btcoexist) return common; } - -static -void halbtc8822b1ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) +void halbtc8822b1ant_action_wifi_freerun(IN struct btc_coexist *btcoexist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], under 5g start\n"); - BTC_TRACE(trace_buf); - /* for test : s3 bt disappear , fail rate 1/600*/ -#if 0 - halbtc8822b1ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, TRUE); -#endif - /*set sw gnt wl bt high*/ - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0xcbd, 0x3, 1); - halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); #if 0 - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, FALSE, 5); -#endif -} - - - + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; -static -void halbtc8822b1ant_action_wifi_only(IN struct btc_coexist *btcoexist) -{ - boolean wifi_under_5g = FALSE, rf4ce_enabled = FALSE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], under 5g start\n"); + BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - halbtc8822b1ant_action_wifi_under5g(btcoexist); + /* for SUMA fine tune */ + if (bt_link_info->a2dp_only) { + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 2); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wlan only -- under 5g ) **********\n"); - BTC_TRACE(trace_buf); - return; - } + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - if (rf4ce_enabled) { - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x45e, 0x8, 0x1); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_BT); + } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) { + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 10); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, - 50); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - return; + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL); } - halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); - - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wlan only -- under 2g ) **********\n"); - BTC_TRACE(trace_buf); - -} - -static -void halbtc8822b1ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist) -{ - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 5); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); +#endif } -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ - -static -void halbtc8822b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) +void halbtc8822b1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex],action_bt_whck_test\n"); BTC_TRACE(trace_buf); + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, BT_8822B_1ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); } -static -void halbtc8822b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) + +void halbtc8822b1ant_action_bt_hs(IN struct btc_coexist *btcoexist) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],action_wifi_multi_port\n"); + "[BTCoex], action_hs\n"); BTC_TRACE(trace_buf); - /*halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);*/ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 1); - halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - - - -} + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5); -static -void halbtc8822b1ant_action_hs(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], action_hs\n"); - BTC_TRACE(trace_buf); halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, BT_8822B_1ANT_PHASE_2G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5); - - } -static + void halbtc8822b1ant_action_bt_relink(IN struct btc_coexist *btcoexist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], run bt multi link function\n"); - BTC_TRACE(trace_buf); + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - if (coex_sta->is_bt_multi_link) - return; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], run bt_re-link function\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + if (((!coex_sta->is_bt_multi_link) && (!bt_link_info->pan_exist)) || + ((bt_link_info->a2dp_exist) && (bt_link_info->hid_exist))) { + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + } } -#if 0 -static + void halbtc8822b1ant_action_bt_idle(IN struct btc_coexist *btcoexist) { boolean wifi_busy = FALSE; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + if (!wifi_busy) { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 6); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); } else { /* if wl busy */ - - if (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 33); + /* for initiator scan on */ + if ((coex_sta->bt_ble_scan_type & 0x2) && + (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status)) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 36); } else { - - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 32); - + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33); } - } - } -#endif + /*"""bt inquiry"""" + wifi any + bt any*/ -static void halbtc8822b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) { struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = FALSE, ap_enable = FALSE, wifi_busy = FALSE, - bt_busy = FALSE, rf4ce_enabled = FALSE; - - + boolean wifi_connected = FALSE, wifi_busy = FALSE, + bt_busy = FALSE; boolean wifi_scan = FALSE, link = FALSE, roam = FALSE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** (bt inquiry) **********\n"); BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** scan = %d, link =%d, roam = %d**********\n", wifi_scan, link, roam); BTC_TRACE(trace_buf); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - if ((link) || (roam) || (coex_sta->wifi_is_high_pri_task)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (bt inquiry wifi connect or scan ) **********\n"); + "[BTCoex], ********** (bt inquiry wifi connect or scan ) **********\n"); BTC_TRACE(trace_buf); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 1); } else if ((wifi_scan) && (coex_sta->bt_create_connection)) { - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); + + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); } else if ((!wifi_connected) && (!wifi_scan)) { @@ -3368,103 +3206,38 @@ void halbtc8822b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** (bt inquiry wifi non connect) **********\n"); BTC_TRACE(trace_buf); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); - } else if (bt_link_info->a2dp_exist) { - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 23); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); } else if (wifi_scan) { halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20); - - } else if (wifi_busy) { - /* for BT inquiry/page fail after S4 resume */ -#if 0 - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20); -#endif - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 15); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); /*aaaa->55aa for bt connect while wl busy*/ - - if (rf4ce_enabled) { - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x45e, 0x8, 0x1); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, - 50); - } + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 23); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** (bt inquiry wifi connect) **********\n"); BTC_TRACE(trace_buf); - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 4); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); - - } - -#if 0 - if ((wifi_link) || (wifi_roam) || (coex_sta->wifi_is_high_pri_task)) { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); - - } else if ((wifi_scan) && (coex_sta->bt_create_connection)) { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); - - } else if ((!wifi_connected) && (!wifi_scan)) { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - } else if (bt_link_info->a2dp_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 23); halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (wifi_scan) { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - } else if (wifi_busy) { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else { - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 19); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); } -#endif + } -static + void halbtc8822b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist *btcoexist) { @@ -3472,658 +3245,551 @@ void halbtc8822b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist boolean wifi_connected = FALSE, wifi_busy = FALSE; u32 wifi_bw = 1; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + if (!wifi_busy) + wifi_busy = coex_sta->gl_wifi_busy; - - if (bt_link_info->sco_exist) { - /*halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 5); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 5);*/ - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0xcbd, 0x3, 1); - halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); + if (coex_sta->msft_mr_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - } else { + } else if (bt_link_info->sco_exist) { + if (coex_sta->is_bt_multi_link) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 25); + } else { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5); + } + } else if (coex_sta->is_hid_rcu) { + if (coex_sta->voice_over_HOGP) { + if (!wifi_busy) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + else if (coex_sta->bt_coex_supported_feature & BIT(11)) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + + if (wifi_busy) + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 37); + else + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 6); + } else { + if (!wifi_busy) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + else if (coex_sta->bt_coex_supported_feature & BIT(11)) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + if (wifi_busy && coex_sta->wl_noisy_level == 0) + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 36); + else if (wifi_busy) + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 37); + else + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 6); + } + } else { if (coex_sta->is_hid_low_pri_tx_overhead) { - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 18); + if (coex_sta->hid_busy_num < 2) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 18); + } else if (coex_sta->hid_busy_num < 2) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 11); } else if (wifi_bw == 0) { /* if 11bg mode */ - - if (coex_sta->is_bt_multi_link) { - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0xcbd, 0x3, 1); - halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - /*halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 11); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 11);*/ - } else { - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0xcbd, 0x3, 1); - halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - /*halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 11);*/ - } + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 11); } else { - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0xcbd, 0x3, 1); - halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - /*halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 11);*/ + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 11); } } } -static -void halbtc8822b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist) +void halbtc8822b1ant_action_bt_mr(IN struct btc_coexist *btcoexist) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = FALSE, wifi_turbo = FALSE; - u32 wifi_bw = 1; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + "[BTCoex], RunCoexistMechanism(), microsoft MR!!\n"); BTC_TRACE(trace_buf); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = TRUE; - - if ((coex_sta->bt_relink_downcount != 0) - && (!bt_link_info->pan_exist) && (wifi_busy)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); - BTC_TRACE(trace_buf); - - /*halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);*/ - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0xcbd, 0x3, 1); - halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - - } else if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) { - /*halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 12); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6);*/ - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0xcbd, 0x3, 1); - halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - } else if (bt_link_info->a2dp_only) { /* A2DP */ - - /*halbtc8822b1ant_ps_tdma(btcoexist, - NORMAL_EXEC, TRUE, 7); + if (coex_sta->wl_center_channel <= 14) { + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL); - if (wifi_turbo) - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 19); - else - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4);*/ - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0xcbd, 0x3, 1); - halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - } else if (((bt_link_info->a2dp_exist) && - (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { - /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ + halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist); - if (wifi_busy) - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 13); - else - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 14); + /* Enter MIMO Power Save, 0:enable */ + halbtc8822b1ant_mimo_ps(btcoexist, NORMAL_EXEC, 0); + } else { + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); - if (bt_link_info->hid_exist) - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - else if (wifi_turbo) - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 19); - else - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - - if (wifi_bw == 0) {/* if 11bg mode */ - /*halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 21);*/ - /*halbtc8822b1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, 1, 0x55, 0x55, 0x5a, 0x5a);*/ - /*halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, - 49);*/ - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0xcbd, 0x3, 1); - halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - } else { - /*halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 21);*/ - /*halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, - TRUE, 8);*/ - /*halbtc8822b1ant_set_wltoggle_coex_table(btcoexist, - NORMAL_EXEC, 1, 0x55, 0x55, 0x5a, 0x5a);*/ - /*halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, - 49);*/ - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0xcbd, 0x3, 1); - halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - } - /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ + halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist); - } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && bt_link_info->pan_exist)) { + /* No MIMO Power Save, 3:disable */ + halbtc8822b1ant_mimo_ps(btcoexist, NORMAL_EXEC, 3); + } +} - if (!wifi_busy) - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 4); - else - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 3); - if (bt_link_info->hid_exist) - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - else if (wifi_turbo) - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 19); - else - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else { - /* BT no-profile busy (0x9) */ - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33); - } +void halbtc8822b1ant_action_rf4ce(IN struct btc_coexist *btcoexist) +{ + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 50); } -/*wifi not connected + bt action*/ - -static -void halbtc8822b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +void halbtc8822b1ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) { - boolean rf4ce_enabled = FALSE; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wifi not connect) **********\n"); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], under 5g start\n"); BTC_TRACE(trace_buf); - /* tdma and coex table */ - if (rf4ce_enabled) { - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x45e, 0x8, 0x1); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, - 50); - return; - } - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); } -/*""""wl not connected scan"""" + bt action*/ -static -void halbtc8822b1ant_action_wifi_not_connected_scan(IN struct btc_coexist - *btcoexist) +void halbtc8822b1ant_action_wifi_only(IN struct btc_coexist *btcoexist) { + boolean wifi_under_5g = FALSE, rf4ce_enabled = FALSE, + wifi_connected = FALSE; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = FALSE; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = FALSE; - u8 agg_buf_size = 5; + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wifi non connect scan) **********\n"); - BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_BL_RF4CE_CONNECTED, &rf4ce_enabled); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); +#if 0 + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (wlan only -- under 5g ) **********\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_wifi_under5g(btcoexist); + } else +#endif + if ((rf4ce_enabled) && (wifi_connected)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (wlan only -- rf4ce enable ) **********\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_rf4ce(btcoexist); + } else { - num_of_wifi_link = wifi_link_status >> 16; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (wlan only -- under 2g ) **********\n"); + BTC_TRACE(trace_buf); - if (num_of_wifi_link >= 2) { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, - bt_ctrl_agg_buf_size, agg_buf_size); + halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_inquiry(btcoexist); - } else { - halbtc8822b1ant_action_wifi_multi_port(btcoexist); - } - return; + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); } +} - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8822b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8822b1ant_action_hs(btcoexist); - return; - } - /* tdma and coex table */ - if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 32); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 22); - } else { - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 20); - } - } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist); - } else { - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); +void halbtc8822b1ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist) +{ + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 5); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - } + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); } -/*""""wl not connected asso"""" + bt action*/ - -static -void halbtc8822b1ant_action_wifi_not_connected_asso_auth( - IN struct btc_coexist *btcoexist) +void halbtc8822b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist, + IN u8 multi_port_type) { - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = FALSE; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = FALSE; - u8 agg_buf_size = 5; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean miracast_plus_bt = FALSE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wifi non connect asso_auth) **********\n"); + "[BTCoex],action_wifi_multi_port\n"); BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); + if (bt_link_info->bt_link_exist) + miracast_plus_bt = TRUE; + else + miracast_plus_bt = FALSE; - num_of_wifi_link = wifi_link_status >> 16; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); - if (num_of_wifi_link >= 2) { + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, - bt_ctrl_agg_buf_size, - agg_buf_size); + if (multi_port_type == BTC_MULTIPORT_MCC_DUAL_BAND) + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_MCC_DUALBAND_RUNTIME); + else + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_inquiry(btcoexist); + + /* for A2DP + miracast + DL */ + if (multi_port_type == BTC_MULTIPORT_MCC_DUAL_BAND) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 25); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + } else if (multi_port_type == BTC_MULTIPORT_SCC) { + if (bt_link_info->a2dp_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 17); + } else if (bt_link_info->pan_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33); } else { - halbtc8822b1ant_action_wifi_multi_port( - btcoexist); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); } - return; - } + } else { //BTC_MULTIPORT_MCC_DUAL_CHANNEL + if (!bt_link_info->pan_exist) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8822b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8822b1ant_action_hs(btcoexist); - return; + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); } +} +void halbtc8822b1ant_action_wifi_linkscan_process(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) || - (bt_link_info->a2dp_exist)) { - halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); - } else if (bt_link_info->pan_exist) { - halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20); + if (bt_link_info->pan_exist) { - } else { - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + } else if (bt_link_info->a2dp_exist) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 27); + } else { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); } } -/*""""wl connected scan"""" + bt action*/ - -static -void halbtc8822b1ant_action_wifi_connected_scan(IN struct btc_coexist +void halbtc8822b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist *btcoexist) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = FALSE; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = FALSE; - u8 agg_buf_size = 5; + boolean wifi_busy = FALSE, wifi_turbo = FALSE, + wifi_cckdeadlock_ap = FALSE, bt_slave_latency = FALSE, + ap_enable = FALSE; + u32 wifi_bw = 1; + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state; + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2; + u8 iot_peer = BTC_IOT_PEER_UNKNOWN, tb_type; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num); + btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wifi connect scan) **********\n"); + "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); + if (!wifi_busy) + wifi_busy = coex_sta->gl_wifi_busy; - num_of_wifi_link = wifi_link_status >> 16; + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; - if (num_of_wifi_link >= 2) { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, - bt_ctrl_agg_buf_size, agg_buf_size); + if (iot_peer == BTC_IOT_PEER_ATHEROS && coex_sta->cck_lock_ever) + wifi_cckdeadlock_ap = TRUE; - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_inquiry(btcoexist); - } else { - halbtc8822b1ant_action_wifi_multi_port(btcoexist); + if (coex_sta->bt_coex_supported_feature & BIT(11)) + bt_slave_latency = TRUE; + else + bt_slave_latency = FALSE; + + wifi_rssi_state = halbtc8822b1ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + 40, 0); + + wifi_rssi_state2 = halbtc8822b1ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + 42, 0); + + if ((btcoexist->board_info.customerID == RT_CID_LENOVO_CHINA) && + (coex_sta->scan_ap_num <= 10) && + (iot_peer == BTC_IOT_PEER_ATHEROS)) { + + if (((bt_link_info->a2dp_only) && (coex_sta->is_bt_multi_link) && + (coex_sta->hid_pair_cnt == 0)) || + ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist))) { + /* for some case, OPP may disappear during CPT_for_WiFi test */ + /* for CPT_for_WiFi */ + if (BTC_RSSI_LOW(wifi_rssi_state2)) { + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 20); + + if (wifi_busy) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 22); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 105); + } else { + //halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 22); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 23); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 13); + } + } else { /* for CPT_for_BT */ + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 24); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 13); + } + + return; } - return; } - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8822b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8822b1ant_action_hs(btcoexist); - return; - } + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); - /* tdma and coex table */ - if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - if (bt_link_info->a2dp_exist) { - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 32); - } else if (bt_link_info->a2dp_exist && - bt_link_info->pan_exist) { - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 22); + if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) { + if (ap_enable) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + else if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); - } else { - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 20); + if (ap_enable) + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + else + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 12); + } else if (bt_link_info->a2dp_only) { /* A2DP */ + if (wifi_busy && (coex_sta->bt_ble_scan_type & 0x2)) { + if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 10); + else if (coex_sta->wl_noisy_level == 0 && !wifi_cckdeadlock_ap) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + } else if (wifi_busy && !(coex_sta->bt_ble_scan_type & 0x2)) { + if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + } else { /*wifi idle */ + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); } - } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist); - } else { -#if 0 - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); -#endif - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 1); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20); -#if 0 - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 6); -#endif - - } -} -/*""""wl connected specific packet"""" + bt action*/ - -static -void halbtc8822b1ant_action_wifi_connected_specific_packet( - IN struct btc_coexist *btcoexist) -{ - - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = FALSE; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = FALSE; - u8 agg_buf_size = 5; - boolean wifi_busy = FALSE; + if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy) + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 26); + else + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 7); + } else if (((bt_link_info->a2dp_exist) && + (bt_link_info->pan_exist)) || + (bt_link_info->hid_exist && bt_link_info->a2dp_exist && + bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (wifi connect specific packet) **********\n"); - BTC_TRACE(trace_buf); + if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); + else if (bt_link_info->hid_exist) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + else if (wifi_turbo) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 19); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); + if (wifi_busy) + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 13); + else + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 14); + } else if (bt_link_info->hid_exist && coex_sta->is_hid_rcu && + coex_sta->voice_over_HOGP && bt_link_info->a2dp_exist) { + /* RCU voice + A2DP */ + /* Change coex table if slave latency support or not */ + if (wifi_busy && !bt_slave_latency) { + if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 10); + else if (coex_sta->wl_noisy_level == 0 && !wifi_cckdeadlock_ap) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + } else if (wifi_busy && bt_slave_latency) { + if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + } else { /*wifi idle */ + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + } - num_of_wifi_link = wifi_link_status >> 16; + if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy) + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 10); + else + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 13); + } else if (bt_link_info->hid_exist && coex_sta->is_hid_rcu && + bt_link_info->a2dp_exist) { + /* RCU + A2DP */ + /* Change coex table if slave latency support or not */ + if (wifi_busy && !bt_slave_latency) { + if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 10); + else if (coex_sta->wl_noisy_level == 0 && !wifi_cckdeadlock_ap) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + } else if (wifi_busy && bt_slave_latency) { + if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + } else { /*wifi idle */ + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + } - if (num_of_wifi_link >= 2) { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, - bt_ctrl_agg_buf_size, agg_buf_size); + if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy) + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 26); + else + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 7); + } else if (bt_link_info->hid_exist && bt_link_info->a2dp_exist) { + /* HID+A2DP */ + if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) { + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); + } else if (wifi_bw == 0) {/* if 11bg mode */ + if (coex_sta->hid_busy_num < 2) /* for 2/18-4/18 HID lag @ Asus */ + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 21); - if (coex_sta->c2h_bt_inquiry_page) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_inquiry(btcoexist); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 7); } else { - halbtc8822b1ant_action_wifi_multi_port(btcoexist); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 7); } - return; - } + /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ - if (coex_sta->c2h_bt_inquiry_page) { - halbtc8822b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8822b1ant_action_hs(btcoexist); - return; - } + } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && bt_link_info->pan_exist)) { + if ((bt_link_info->pan_only) && + (btcoexist->board_info.customerID == RT_CID_LENOVO_CHINA) && + (wifi_busy) && (BTC_RSSI_HIGH(wifi_rssi_state2))) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 10); - /* no specific packet process for both WiFi and BT very busy */ - if ((wifi_busy) && ((bt_link_info->pan_exist) || - (coex_sta->num_of_profile >= 2))) - return; + } else { - /* tdma and coex table */ - if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) { - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); + if (coex_sta->cck_lock_ever) { + if ((bt_link_info->hid_exist) && (coex_sta->hid_busy_num < 2)) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13); + } else if (bt_link_info->hid_exist) { + if (coex_sta->hid_busy_num < 2) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3); + } else if (wifi_turbo) + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 19); + else + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } else if (bt_link_info->a2dp_exist) { - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 15); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32); - /*for a2dp glitch,change from 1 to 15*/ + if (!wifi_busy) + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 4); + else + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 3); + } + } else { + /* BT no-profile busy (0x9) */ + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33); + } - } else if (bt_link_info->pan_exist) { - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 1); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20); +} - } else { - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 5); +/* wifi connected input point: + * to set different ps and tdma case (+bt different case) + */ - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - } -} +/*wifi not connected + bt action*/ -static -void halbtc8822b1ant_action_a2dpsink(IN struct btc_coexist *btcoexist) +void halbtc8822b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (wifi not connect) **********\n"); + BTC_TRACE(trace_buf); - boolean wifi_busy = FALSE, wifi_turbo = FALSE; + halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0xcbd, 0x3, 1); - halbtc8822b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + /* tdma and coex table */ + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); } -/* wifi connected input point: - * to set different ps and tdma case (+bt different case) - */ - -static + void halbtc8822b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) { - + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; boolean wifi_busy = FALSE, rf4ce_enabled = FALSE; - boolean scan = FALSE, link = FALSE, roam = FALSE; - boolean under_4way = FALSE, ap_enable = FALSE, wifi_under_5g = FALSE; + boolean wifi_under_5g = FALSE; u8 wifi_rssi_state; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], CoexForWifiConnect()===>\n"); BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_BL_RF4CE_CONNECTED, &rf4ce_enabled); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - +#if 0 if (wifi_under_5g) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -4134,7 +3800,7 @@ void halbtc8822b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) return; } - +#endif BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], CoexForWifiConnect(), return for wifi is under 2g<===\n"); BTC_TRACE(trace_buf); @@ -4144,162 +3810,34 @@ void halbtc8822b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) NORMAL_EXEC, BT_8822B_1ANT_PHASE_2G_RUNTIME); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (under_4way) { - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - if (scan || link || roam) { - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - if (scan) - halbtc8822b1ant_action_wifi_connected_scan(btcoexist); - else - halbtc8822b1ant_action_wifi_connected_specific_packet( - btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"); - BTC_TRACE(trace_buf); - return; - } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - /* tdma and coex table */ - if (!wifi_busy) { - if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8822b1ant_action_wifi_connected_bt_acl_busy( - btcoexist); - } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { - halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist); - } else { - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, - 8); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); + if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY)) { - if ((coex_sta->high_priority_tx) + - (coex_sta->high_priority_rx) <= 60) - /*sy modify case16 -> case17*/ - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - else - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } - } else { - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { - halbtc8822b1ant_action_wifi_connected_bt_acl_busy( - btcoexist); - } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) { + if (bt_link_info->hid_only) /* HID only */ halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist); - } else { - if (rf4ce_enabled) { - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x45e, 0x8, 0x1); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, - 50); - return; - } - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, - 8); - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - -#if 0 - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 32); - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, NORMAL_EXEC, BT_8822B_1ANT_PHASE_2G_RUNTIME); -#endif - - + else + halbtc8822b1ant_action_wifi_connected_bt_acl_busy(btcoexist); - wifi_rssi_state = halbtc8822b1ant_wifi_rssi_state( - btcoexist, 1, 2, 25, 0); + } else if (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY) + halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist); + else if (rf4ce_enabled) + halbtc8822b1ant_action_rf4ce(btcoexist); + else + halbtc8822b1ant_action_bt_idle(btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** before **********\n"); - BTC_TRACE(trace_buf); -#if 0 - if ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) && - (coex_sta->scan_ap_num <= 3) && - (wifi_rssi_state == BTC_RSSI_STATE_LOW || - wifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { -#endif - if (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - if (rf4ce_enabled) { - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x45e, 0x8, 0x1); - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, - 50); - return; - } +} - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - } else - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); -#if 0 - else if ((coex_sta->high_priority_tx + - coex_sta->high_priority_rx) <= 60) - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - else - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); -#endif - } - } -} -static void halbtc8822b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) { u8 algorithm = 0; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (run sw coexmech) **********\n"); + "[BTCoex], ********** (run sw coex mech) **********\n"); BTC_TRACE(trace_buf); algorithm = halbtc8822b1ant_action_algorithm(btcoexist); coex_dm->cur_algorithm = algorithm; @@ -4312,103 +3850,56 @@ void halbtc8822b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = SCO.\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8822b1ant_action_sco(btcoexist); -#endif break; case BT_8822B_1ANT_COEX_ALGO_HID: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = HID.\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8822b1ant_action_hid(btcoexist); -#endif break; case BT_8822B_1ANT_COEX_ALGO_A2DP: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = A2DP.\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8822b1ant_action_a2dp(btcoexist); -#endif break; case BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8822b1ant_action_a2dp_pan_hs(btcoexist); -#endif break; case BT_8822B_1ANT_COEX_ALGO_PANEDR: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = PAN(EDR).\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8822b1ant_action_pan_edr(btcoexist); -#endif break; case BT_8822B_1ANT_COEX_ALGO_PANHS: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = HS mode.\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8822b1ant_action_pan_hs(btcoexist); -#endif break; case BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = PAN+A2DP.\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8822b1ant_action_pan_edr_a2dp(btcoexist); -#endif - break; - case BT_8822B_1ANT_COEX_ALGO_A2DPSINK: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP Sink.\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_a2dpsink(btcoexist); break; - case BT_8822B_1ANT_COEX_ALGO_PANEDR_HID: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8822b1ant_action_pan_edr_hid(btcoexist); -#endif break; case BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8822b1ant_action_hid_a2dp_pan_edr(btcoexist); -#endif break; case BT_8822B_1ANT_COEX_ALGO_HID_A2DP: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = HID+A2DP.\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8822b1ant_action_hid_a2dp(btcoexist); -#endif - break; - case BT_8822B_1ANT_COEX_ALGO_NOPROFILEBUSY: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_idle(btcoexist); break; - default: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action algorithm = coexist All Off!!\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8822b1ant_coex_all_off(btcoexist); -#endif break; } coex_dm->pre_algorithm = coex_dm->cur_algorithm; @@ -4421,15 +3912,26 @@ void halbtc8822b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; boolean wifi_connected = FALSE, bt_hs_on = FALSE; - boolean increase_scan_dev_num = FALSE; boolean bt_ctrl_agg_buf_size = FALSE; - boolean miracast_plus_bt = FALSE; - u8 agg_buf_size = 5; + u8 agg_buf_size = 5, mcc_dualband = BTC_MULTIPORT_SCC; u32 wifi_link_status = 0; u32 num_of_wifi_link = 0, wifi_bw; u8 iot_peer = BTC_IOT_PEER_UNKNOWN; boolean wifi_under_5g = FALSE; + boolean scan = FALSE, link = FALSE, roam = FALSE, under_4way = FALSE; + u8 wifi_central_chnl = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + coex_sta->wl_center_channel = wifi_central_chnl; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RunCoexistMechanism()===>\n"); @@ -4451,57 +3953,88 @@ void halbtc8822b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) if (coex_sta->under_ips) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); + "[BTCoex], RunCoexistMechanism(), wifi is under IPS !!!\n"); BTC_TRACE(trace_buf); return; } - if ((coex_sta->under_lps) && - (coex_dm->bt_status != BT_8822B_1ANT_BT_STATUS_ACL_BUSY)) { + if (!coex_sta->run_time_state) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n"); + "[BTCoex], RunCoexistMechanism(), return for run_time_state = FALSE !!!\n"); BTC_TRACE(trace_buf); - halbtc8822b1ant_action_wifi_native_lps(btcoexist); return; } - if (!coex_sta->run_time_state) { + if (coex_sta->freeze_coexrun_by_btinfo) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], return for run_time_state = FALSE !!!\n"); + "[BTCoex], RunCoexistMechanism(), return for freeze_coexrun_by_btinfo\n"); BTC_TRACE(trace_buf); return; } - if (coex_sta->freeze_coexrun_by_btinfo) { + if ((coex_sta->msft_mr_exist) && (wifi_connected)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), microsoft MR!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_action_bt_mr(btcoexist); + return; + } + + /* No MIMO Power Save, 3:disable */ + halbtc8822b1ant_mimo_ps(btcoexist, NORMAL_EXEC, 3); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED, &mcc_dualband); + if (mcc_dualband == BTC_MULTIPORT_MCC_DUAL_BAND) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); + "[BTCoex], RunCoexistMechanism(), mcc dual band!!\n"); BTC_TRACE(trace_buf); + + halbtc8822b1ant_action_wifi_multi_port(btcoexist, BTC_MULTIPORT_MCC_DUAL_BAND); return; } btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { + if ((wifi_under_5g) && + (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G) && + (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G_NOFORSCAN)) { halbtc8822b1ant_action_wifi_under5g(btcoexist); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], WiFi is under 5G!!!\n"); BTC_TRACE(trace_buf); return; + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 2G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); } - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 2G!!!\n"); - BTC_TRACE(trace_buf); +halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_BTCQDDR, + TRUE); - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); + + if ((coex_sta->under_lps) && (!coex_sta->force_lps_ctrl) && + (!coex_sta->acl_busy)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_wifi_native_lps(btcoexist); + return; + } if (coex_sta->bt_whck_test) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BT is under WHCK TEST!!!\n"); BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_whck_test(btcoexist); + halbtc8822b1ant_action_bt_whql_test(btcoexist); return; } @@ -4509,12 +4042,20 @@ void halbtc8822b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BT is disabled !!!\n"); BTC_TRACE(trace_buf); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); halbtc8822b1ant_action_wifi_only(btcoexist); return; } - if (coex_sta->is_setupLink) { + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8822b1ant_action_bt_inquiry(btcoexist); + return; + } + + if ((coex_sta->is_setupLink) && + (coex_sta->bt_relink_downcount != 0)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BT is re-link !!!\n"); BTC_TRACE(trace_buf); @@ -4522,19 +4063,9 @@ void halbtc8822b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) return; } - if ((BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = TRUE; - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; if ((num_of_wifi_link >= 2) || @@ -4543,120 +4074,78 @@ void halbtc8822b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", num_of_wifi_link, wifi_link_status); BTC_TRACE(trace_buf); - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - if (bt_link_info->bt_link_exist) { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, - 0, 1); - miracast_plus_bt = TRUE; - } else { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, - 0, 0); - miracast_plus_bt = FALSE; - } - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, - bt_ctrl_agg_buf_size, agg_buf_size); + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); - if ((bt_link_info->a2dp_exist) && - (coex_sta->c2h_bt_inquiry_page)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); + "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_inquiry(btcoexist); - } else { - halbtc8822b1ant_action_wifi_multi_port(btcoexist); - } + + halbtc8822b1ant_action_wifi_linkscan_process(btcoexist); + } else + halbtc8822b1ant_action_wifi_multi_port(btcoexist, mcc_dualband); return; } - miracast_plus_bt = FALSE; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1); btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); - if (BTC_IOT_PEER_CISCO != iot_peer) { -#if 0 - if (bt_link_info->bt_hi_pri_link_exist) -#endif - if (bt_link_info->sco_exist) + if (iot_peer == BTC_IOT_PEER_CISCO) { + + if (wifi_bw == BTC_WIFI_BW_HT40) halbtc8822b1ant_limited_rx(btcoexist, - NORMAL_EXEC, TRUE, FALSE, 0x5); + NORMAL_EXEC, FALSE, TRUE, 0x10); else halbtc8822b1ant_limited_rx(btcoexist, - NORMAL_EXEC, FALSE, FALSE, 0x5); - } else { - halbtc8822b1ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - if (bt_link_info->sco_exist) - halbtc8822b1ant_limited_rx(btcoexist, - NORMAL_EXEC, TRUE, FALSE, 0x5); - else { - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8822b1ant_limited_rx(btcoexist, - NORMAL_EXEC, FALSE, TRUE, 0x10); - else - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, TRUE, 0x8); - } } - - halbtc8822b1ant_sw_mechanism(btcoexist, TRUE); - halbtc8822b1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - } else { - halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0); - - halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, FALSE, - 0x5); - - halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); - halbtc8822b1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ } - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - if (coex_sta->c2h_bt_inquiry_page) { + /* just print debug message */ + halbtc8822b1ant_run_sw_coexist_mechanism(btcoexist); + + if ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) || + (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is Inquirying\n"); + "############# [BTCoex], BT Is idle\n"); BTC_TRACE(trace_buf); - halbtc8822b1ant_action_bt_inquiry(btcoexist); - return; - } else if (bt_hs_on) { - halbtc8822b1ant_action_hs(btcoexist); + halbtc8822b1ant_action_bt_idle(btcoexist); return; } - - if (!wifi_connected) { - boolean scan = FALSE, link = FALSE, roam = FALSE; + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is non connected-idle !!!\n"); + "[BTCoex], wifi is under linkscan process!!\n"); BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + halbtc8822b1ant_action_wifi_linkscan_process(btcoexist); + } else if (wifi_connected) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under connected!!\n"); + BTC_TRACE(trace_buf); - if (scan) - halbtc8822b1ant_action_wifi_not_connected_scan( - btcoexist); - else if (link || roam) - halbtc8822b1ant_action_wifi_not_connected_asso_auth( - btcoexist); - else - halbtc8822b1ant_action_wifi_not_connected(btcoexist); - } else /* wifi LPS/Busy */ halbtc8822b1ant_action_wifi_connected(btcoexist); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under not-connected!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b1ant_action_wifi_not_connected(btcoexist); + } + } static @@ -4667,14 +4156,18 @@ void halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); /* sw all off */ - halbtc8822b1ant_sw_mechanism(btcoexist, FALSE); - -#if 0 - halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); - halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); -#endif + coex_sta->pop_event_cnt = 0; + coex_sta->cnt_RemoteNameReq = 0; + coex_sta->cnt_ReInit = 0; + coex_sta->cnt_setupLink = 0; + coex_sta->cnt_IgnWlanAct = 0; + coex_sta->cnt_Page = 0; + coex_sta->cnt_RoleSwitch = 0; + coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; coex_sta->pop_event_cnt = 0; + + halbtc8822b1ant_query_bt_info(btcoexist); } static @@ -4683,28 +4176,29 @@ void halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, { u8 u8tmp = 0, i = 0; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 1Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcbc); u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", + "[BTCoex], ********** (Before Init HW config) 0xcbc = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", u32tmp3, u32tmp1, u32tmp2); BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 1Ant Init HW Config!!\n"); - BTC_TRACE(trace_buf); - +#if 0 coex_sta->bt_coex_supported_feature = 0; coex_sta->bt_coex_supported_version = 0; coex_sta->bt_ble_scan_type = 0; coex_sta->bt_ble_scan_para[0] = 0; coex_sta->bt_ble_scan_para[1] = 0; coex_sta->bt_ble_scan_para[2] = 0; +#endif coex_sta->bt_reg_vendor_ac = 0xffff; coex_sta->bt_reg_vendor_ae = 0xffff; coex_sta->isolation_btween_wb = BT_8822B_1ANT_DEFAULT_ISOLATION; @@ -4719,12 +4213,20 @@ void halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, /* Setup RF front end type */ halbtc8822b1ant_set_rfe_type(btcoexist); + if ((rfe_type->rfe_module_type == 2) || + (rfe_type->rfe_module_type == 4)) + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_EXTFEM, TRUE); + else + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_EXTFEM, FALSE); + /* 0xf0[15:12] --> Chip Cut information */ coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, 0xf1) & 0xf0) >> 4; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ + /* enable TBTT nterrupt */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, 0x1); /* BT report packet sample rate */ /* 0x790[5:0]=0x5 */ @@ -4745,18 +4247,17 @@ void halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, /*GNT_BT=1 while select both */ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1); -#if 0 - /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); -#endif - - /* enable GNT_WL */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0); + halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, TRUE); +#if 0 if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) halbtc8822b1ant_post_state_to_bt(btcoexist, BT_8822B_1ANT_SCOREBOARD_ONOFF, TRUE); +#endif + + /* PTA parameter */ + halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); /* Antenna config */ if (coex_sta->is_rf_state_off) { @@ -4777,6 +4278,7 @@ void halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, BTC_ANT_PATH_WIFI, FORCE_EXEC, BT_8822B_1ANT_PHASE_WLANONLY_INIT); + btcoexist->stop_coex_dm = TRUE; } else { coex_sta->concurrent_rx_mode_on = TRUE; @@ -4785,15 +4287,21 @@ void halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, BT_8822B_1ANT_PHASE_COEX_INIT); + btcoexist->stop_coex_dm = FALSE; } - /* PTA parameter */ - halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, TRUE); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcbc); + u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (After Init HW config) 0xcbc = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", + u32tmp3, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); } -#if (BTC_COEX_OFFLOAD == 1) +#if 0 void halbtc8822b1ant_wifi_info_notify(IN struct btc_coexist *btcoexist) { u8 h2c_para[4] = {0}; @@ -5187,11 +4695,14 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], coex_dm->wifi_chnl_info[2]); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", - "WifibHiPri/ Ccklock/ CckEverLock", + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %s/ %d", + "HiPr/ Locking/ warn/ Locked/ Noisy", (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No")); + (coex_sta->cck_lock_warn ? "Yes" : "No"), + (coex_sta->cck_lock_ever ? "Yes" : "No"), + coex_sta->wl_noisy_level); CL_PRINTF(cli_buf); /* wifi status */ @@ -5525,32 +5036,19 @@ void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist) "xxxxxxxxxxxxxxxx Execute 8822b 1-Ant PowerOn Setting!! xxxxxxxxxxxxxxxx\n"); BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Ant Det Finish = %s, Ant Det Number = %d\n", - board_info->btdm_ant_det_finish ? "Yes" : "No", - board_info->btdm_ant_num_by_ant_det); - BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = TRUE; + coex_sta->is_rf_state_off = FALSE; /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); - /* set Path control owner to WiFi */ - halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8822B_1ANT_PCO_WLSIDE); + /* Setup RF front end type */ + halbtc8822b1ant_set_rfe_type(btcoexist); - /* set GNT_BT to high */ - halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to low */ - halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8822B_1ANT_GNT_BLOCK_RFC_BB, - BT_8822B_1ANT_GNT_CTRL_BY_SW, - BT_8822B_1ANT_SIG_STA_SET_TO_LOW); + /* Set Antenna Path to BT side */ + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_COEX_POWERON); /* set WLAN_ACT = 0 */ /* btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); */ @@ -5560,7 +5058,6 @@ void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist) halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, TRUE); - /* */ /* S0 or S1 setting and Local register setting * (By the setting fw can get ant number, S0/S1, ... info) */ @@ -5575,13 +5072,23 @@ void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist) u8tmp = 0; board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - if (btcoexist->chip_interface == BTC_INTF_USB) + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_USB) btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); else if (btcoexist->chip_interface == BTC_INTF_SDIO) btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x\n", + halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38)); BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcbc (Power-On) = 0x%x / 0x%x\n", + btcoexist->btc_read_4byte(btcoexist, 0x70), + btcoexist->btc_read_4byte(btcoexist, 0xcbc)); + BTC_TRACE(trace_buf); } @@ -5613,40 +5120,34 @@ void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist) } -void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) + +void ex_halbtc8822b1ant_display_simple_coex_info(IN struct btc_coexist *btcoexist) { struct btc_board_info *board_info = &btcoexist->board_info; struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; - u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; - static u8 pop_report_in_10s = 0; - u32 phyver = 0; - boolean lte_coex_on = FALSE; - static u8 cnt = 0; + u8 *cli_buf = btcoexist->cli_buf; + u32 bt_patch_ver = 0, bt_coex_ver = 0; + static u8 cnt = 0; CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); + "\r\n _____[BT Coexist info]____"); CL_PRINTF(cli_buf); if (btcoexist->manual_control) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); + "\r\n __[Under Manual Control]_"); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); + "\r\n _________________________"); CL_PRINTF(cli_buf); } if (btcoexist->stop_coex_dm) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); + "\r\n ____[Coex is STOPPED]____"); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); + "\r\n _________________________"); CL_PRINTF(cli_buf); } @@ -5685,6 +5186,7 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) } } + // BT coex. info. if (psd_scan->ant_det_try_count == 0) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s / %d", @@ -5725,6 +5227,130 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) } } + bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant, + glcoex_ver_btdesired_8822b_1ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8822b_1ant ? + "Match" : "Mis-Match")))); + CL_PRINTF(cli_buf); + + // BT Status + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", + "BT status", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE) + ? "connected-idle" : "busy"))))); + CL_PRINTF(cli_buf); + + // HW Settings + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : ( + coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); + CL_PRINTF(cli_buf); + +} + + +void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_stack_info *stack_info = &btcoexist->stack_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u16 u16tmp[4]; + u32 u32tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + static u8 pop_report_in_10s = 0; + u32 phyver = 0; + boolean lte_coex_on = FALSE; + static u8 cnt = 0; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + if (btcoexist->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->bt_coex_supported_feature == 0) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + if (coex_sta->bt_reg_vendor_ac == 0xffff) + coex_sta->bt_reg_vendor_ac = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xac) & 0xffff); + + if (coex_sta->bt_reg_vendor_ae == 0xffff) + coex_sta->bt_reg_vendor_ae = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xae) & 0xffff); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, + &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) { + cnt++; + + if (cnt >= 3) { + btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, + &coex_sta->bt_afh_map[0]); + cnt = 0; + } + } + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s / %d", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, board_info->btdm_ant_num, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type); + CL_PRINTF(cli_buf); + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); @@ -5750,10 +5376,10 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_sta->cut_version + 65); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x (RF-Ch = %d)", "AFH Map to BT", coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); + coex_dm->wifi_chnl_info[2], coex_sta->wl_center_channel); CL_PRINTF(cli_buf); /* wifi status */ @@ -5768,12 +5394,12 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) pop_report_in_10s++; CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", + "\r\n %-35s = %s/ %ddBm/ %d/ %d", + "BT status/ rssi/ retryCnt/ popCnt", ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + coex_sta->c2h_bt_inquiry_page) ? ("inquiry-page") : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : + coex_dm->bt_status) ? "non-connecte-idle" : ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE) ? "connected-idle" : "busy")))), coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, @@ -5787,20 +5413,26 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) if (coex_sta->num_of_profile != 0) CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s%s%s%s%s", - "Profiles", - ((bt_link_info->a2dp_exist) ? - ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," : - "A2DP,") : ""), - ((bt_link_info->sco_exist) ? "HFP," : ""), - ((bt_link_info->hid_exist) ? - ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : - "HID(2/18),") : ""), - ((bt_link_info->pan_exist) ? "PAN," : ""), - ((coex_sta->voice_over_HOGP) ? "Voice" : "")); - else + "\r\n %-35s = %s%s%s%s%s%s (multilink = %d)", + "Profiles", + ((bt_link_info->a2dp_exist) ? + ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," : + "A2DP,") : ""), + ((bt_link_info->sco_exist) ? "HFP," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->is_hid_rcu) ? "HID(RCU)" : + ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : + "HID(2/18),")) : ""), + ((bt_link_info->pan_exist) ? + ((coex_sta->is_bt_opp_exist) ? "OPP," : "PAN,") : ""), + ((coex_sta->voice_over_HOGP) ? "Voice," : ""), + ((coex_sta->msft_mr_exist) ? "MR" : ""), + coex_sta->is_bt_multi_link); + else { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = None", "Profiles"); + "\r\n %-35s = %s", "Profiles", + (coex_sta->msft_mr_exist) ? "MR" : "None"); + } CL_PRINTF(cli_buf); @@ -5812,13 +5444,21 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) ((coex_sta->is_autoslot) ? "On" : "Off") ); CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %d/ %d", + "V_ID/D_name/FBSlot_Legacy/FBSlot_Le", + coex_sta->bt_a2dp_vendor_id, + coex_sta->bt_a2dp_device_name, + coex_sta->legacy_forbidden_slot, + coex_sta->le_forbidden_slot + ); + CL_PRINTF(cli_buf); } if (bt_link_info->hid_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "HID PairNum/Forbid_Slot", - coex_sta->hid_pair_cnt, - coex_sta->forbidden_slot + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "HID PairNum", + coex_sta->hid_pair_cnt ); CL_PRINTF(cli_buf); } @@ -5831,7 +5471,7 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_sta->bt_coex_supported_feature); CL_PRINTF(cli_buf); - if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { + if (coex_sta->is_ble_scan_en) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "BLEScan Type/TV/Init/Ble", @@ -5859,19 +5499,19 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) if ((coex_sta->bt_reg_vendor_ae == 0xffff) || (coex_sta->bt_reg_vendor_ac == 0xffff)) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ 0x%04x", + "0xae[4]/0xac[1:0]/Scoreboard(B->W)", u16tmp[0]); else CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", - (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), + "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x", + "0xae[4]/0xac[1:0]/Scoreboard(B->W)", + ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); CL_PRINTF(cli_buf); if (coex_sta->num_of_profile > 0) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + "\r\n %-35s = %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x", "AFH MAP", coex_sta->bt_afh_map[0], coex_sta->bt_afh_map[1], @@ -5890,7 +5530,7 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) for (i = 0; i < BT_INFO_SRC_8822B_1ANT_MAX; i++) { if (coex_sta->bt_info_c2h_cnt[i]) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)", glbt_info_src_8822b_1ant[i], coex_sta->bt_info_c2h[i][0], coex_sta->bt_info_c2h[i][1], @@ -5937,17 +5577,27 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x", - "0x778/0x6cc", - u8tmp[0], u32tmp[0]); + "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x", + "0x778/0x6cc/Scoreboard(W->B)", + u8tmp[0], u32tmp[0], coex_sta->score_board_WB); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "AntDiv/BtCtrlLPS/LPRA/PsFail", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d/ %d", + "AntDiv/BtCtrlLPS/LPRA/PsFail/g_busy", ((board_info->ant_div_cfg) ? "On" : "Off"), ((coex_sta->force_lps_ctrl) ? "On" : "Off"), ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"), - coex_sta->cnt_set_ps_state_fail); + coex_sta->cnt_set_ps_state_fail, + coex_sta->gl_wifi_busy); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "Null All/Retry/Ack/BT_Empty/BT_Late", + coex_sta->wl_fw_dbg_info[1], + coex_sta->wl_fw_dbg_info[2], + coex_sta->wl_fw_dbg_info[3], + coex_sta->wl_fw_dbg_info[4], + coex_sta->wl_fw_dbg_info[5]); CL_PRINTF(cli_buf); u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); @@ -6014,7 +5664,7 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) CL_PRINTF(cli_buf); } CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s (gnt_err = %d)", "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), @@ -6034,12 +5684,14 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0); u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcbd); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc58); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s", - "0xcb0/0xcb4/0xcb8[23:16]", - u32tmp[0], u32tmp[1], u8tmp[0], - ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); + "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x/ 0x%02x/ 0x%02x %s", + "0xcb0/0xcb4/0xcb8[23:16]/0xcbd/0xc58", + u32tmp[0], u32tmp[1], u8tmp[0], u8tmp[1], u8tmp[2], + ((u8tmp[1] & 0x1) == 0x1 ? "(BT_WL5G)" : "(WL2G)")); CL_PRINTF(cli_buf); u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); @@ -6050,8 +5702,7 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "4c[24:23]/64[0]/4c6[4]/40[5]", - (int)((u32tmp[0] & (BIT(24) | BIT(23))) >> 23), - u8tmp[2] & 0x1, + (u32tmp[0] & (BIT(24) | BIT(23))) >> 23, u8tmp[2] & 0x1, (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5)); CL_PRINTF(cli_buf); @@ -6082,12 +5733,11 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) cca_cck, fa_cck, cca_ofdm, fa_ofdm); CL_PRINTF(cli_buf); - -#if 1 - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d (Rx_rate Data/RTS= %d/%d)", "CRC_OK CCK/11g/11n/11ac", coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht, + coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", @@ -6095,13 +5745,13 @@ void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_sta->crc_err_cck, coex_sta->crc_err_11g, coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); CL_PRINTF(cli_buf); -#endif - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "WlHiPri/ Locking/ Locked/ Noisy", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %s/ %d", + "HiPr/ Locking/ warn/ Locked/ Noisy", (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No"), + (coex_sta->cck_lock_warn ? "Yes" : "No"), + (coex_sta->cck_lock_ever ? "Yes" : "No"), coex_sta->wl_noisy_level); CL_PRINTF(cli_buf); @@ -6136,37 +5786,34 @@ void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) /* Write WL "Active" in Score-board for LPS off */ halbtc8822b1ant_post_state_to_bt(btcoexist, - BT_8822B_1ANT_SCOREBOARD_ACTIVE, FALSE); - - halbtc8822b1ant_post_state_to_bt(btcoexist, - BT_8822B_1ANT_SCOREBOARD_ONOFF, FALSE); - halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + BT_8822B_1ANT_SCOREBOARD_ACTIVE | + BT_8822B_1ANT_SCOREBOARD_ONOFF | + BT_8822B_1ANT_SCOREBOARD_SCAN | + BT_8822B_1ANT_SCOREBOARD_UNDERTEST | + BT_8822B_1ANT_SCOREBOARD_RXGAIN, + FALSE); halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, BT_8822B_1ANT_PHASE_WLAN_OFF); - + halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); } else if (BTC_IPS_LEAVE == type) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], IPS LEAVE notify\n"); BTC_TRACE(trace_buf); halbtc8822b1ant_post_state_to_bt(btcoexist, - BT_8822B_1ANT_SCOREBOARD_ACTIVE, TRUE); - - halbtc8822b1ant_post_state_to_bt(btcoexist, - BT_8822B_1ANT_SCOREBOARD_ONOFF, TRUE); + BT_8822B_1ANT_SCOREBOARD_ACTIVE | + BT_8822B_1ANT_SCOREBOARD_ONOFF, + TRUE); /*leave IPS : run ini hw config (exclude wifi only)*/ halbtc8822b1ant_init_hw_config(btcoexist, FALSE, FALSE); /*sw all off*/ halbtc8822b1ant_init_coex_dm(btcoexist); - /*leave IPS : Query bt info*/ - halbtc8822b1ant_query_bt_info(btcoexist); coex_sta->under_ips = FALSE; } @@ -6185,22 +5832,18 @@ void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) BTC_TRACE(trace_buf); coex_sta->under_lps = TRUE; - if (coex_sta->force_lps_ctrl) { /* LPS No-32K */ + if (coex_sta->force_lps_ctrl == TRUE) { /* LPS No-32K */ /* Write WL "Active" in Score-board for PS-TDMA */ pre_force_lps_on = TRUE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], LPS ENABLE notify-force LPS control\n"); - BTC_TRACE(trace_buf); halbtc8822b1ant_post_state_to_bt(btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE, TRUE); - } else { - /* LPS-32K, need check if this h2c 0x71 can work?? - * (2015/08/28) - */ + } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ /* Write WL "Non-Active" in Score-board for Native-PS */ pre_force_lps_on = FALSE; halbtc8822b1ant_post_state_to_bt(btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE, FALSE); + + halbtc8822b1ant_action_wifi_native_lps(btcoexist); } } else if (BTC_LPS_DISABLE == type) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -6220,171 +5863,132 @@ void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist, IN u8 type) { - boolean wifi_connected = FALSE; + boolean wifi_connected = FALSE; boolean wifi_under_5g = FALSE; if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + btcoexist->stop_coex_dm) return; coex_sta->freeze_coexrun_by_btinfo = FALSE; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); if (wifi_connected) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** WL connected before SCAN\n"); + "[BTCoex], ********** WL connected before SCAN\n"); else BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** WL is not connected before SCAN\n"); BTC_TRACE(trace_buf); - halbtc8822b1ant_query_bt_info(btcoexist); + if ((type == BTC_SCAN_START) || (type == BTC_SCAN_START_2G)) { - /*2.4 g 1*/ - if (BTC_SCAN_START == type) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - /*5 g 1*/ + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE | + BT_8822B_1ANT_SCOREBOARD_SCAN | + BT_8822B_1ANT_SCOREBOARD_ONOFF, + TRUE); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (scan_notify_5g_scan_action 1) **********\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_wifi_under5g(btcoexist); - return; - } + halbtc8822b1ant_query_bt_info(btcoexist); + } - /* 2.4G.2.3*/ - coex_sta->wifi_is_high_pri_task = TRUE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (scan_notify_start action) **********\n"); - BTC_TRACE(trace_buf); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (!wifi_connected) { /* non-connected scan */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** wifi not connected 2g scan action 1 **********\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_wifi_not_connected_scan( - btcoexist); - } else { /* wifi is connected */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** wifi connected 2g scan action 2 **********\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_wifi_connected_scan( - btcoexist); - } + if ((type == BTC_SCAN_START) && (wifi_under_5g)) { - return; - } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify (5G)\n"); + BTC_TRACE(trace_buf); - if (BTC_SCAN_START_2G == type) { - coex_sta->wifi_is_high_pri_task = TRUE; + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_run_coexist_mechanism(btcoexist); + } else if ((type == BTC_SCAN_START_2G) || (type == BTC_SCAN_START)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (scan_notify_2g_sacn_start_for_switch_band_used) **********\n"); + "[BTCoex], SCAN START notify (2G)\n"); BTC_TRACE(trace_buf); - if (!wifi_connected) { /* non-connected scan */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** wifi not connected 2g scan action 3 **********\n"); - BTC_TRACE(trace_buf); + if (!wifi_connected) + coex_sta->wifi_is_high_pri_task = TRUE; - halbtc8822b1ant_action_wifi_not_connected_scan( - btcoexist); - } else { /* wifi is connected */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** wifi connected 2g sacn action 4**********\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_wifi_connected_scan(btcoexist); - } + /* Force antenna setup for no scan result issue */ + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + halbtc8822b1ant_run_coexist_mechanism(btcoexist); } else { - coex_sta->wifi_is_high_pri_task = FALSE; - /* 2.4G 5 WL scan finish, then get and update sacn ap numbers */ - /*5 g 4*/ btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (scan_finish_notify) **********\n"); + "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", + coex_sta->scan_ap_num); BTC_TRACE(trace_buf); - if (!wifi_connected) /* non-connected scan */ - halbtc8822b1ant_action_wifi_not_connected(btcoexist); - else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** scan_finish_notify action wifi connected **********\n"); - BTC_TRACE(trace_buf); - halbtc8822b1ant_action_wifi_connected(btcoexist); - } + coex_sta->wifi_is_high_pri_task = FALSE; + + halbtc8822b1ant_run_coexist_mechanism(btcoexist); } + } + void ex_halbtc8822b1ant_scan_notify_without_bt(IN struct btc_coexist *btcoexist, IN u8 type) { - boolean wifi_under_5g = FALSE; - if (BTC_SCAN_START == type) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (wifi_under_5g) { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, - 0x3, 1); - return; - } + if (BTC_SCAN_START == type) { - /* under 2.4G */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, - 0x3, 2); - return; - } - if (BTC_SCAN_START_2G == type) + if (wifi_under_5g) + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 1); + else /* under 2.4G */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2); + } else if (type == BTC_SCAN_START_2G) btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2); } void ex_halbtc8822b1ant_switchband_notify(IN struct btc_coexist *btcoexist, IN u8 type) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (switchband_notify) **********\n"); - BTC_TRACE(trace_buf); if (btcoexist->manual_control || btcoexist->stop_coex_dm) return; coex_sta->switch_band_notify_to = type; - /*2.4g 4.*//*5 g 2*/ + if (type == BTC_SWITCH_TO_5G) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (switchband_notify 5g action 2) **********\n"); + "[BTCoex], switchband_notify --- BTC_SWITCH_TO_5G\n"); BTC_TRACE(trace_buf); - halbtc8822b1ant_action_wifi_under5g(btcoexist); - return; + halbtc8822b1ant_run_coexist_mechanism(btcoexist); } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_2G (no for scan)) **********\n"); + "[BTCoex], switchband_notify --- BTC_SWITCH_TO_24G_NOFORSCAN\n"); BTC_TRACE(trace_buf); halbtc8822b1ant_run_coexist_mechanism(btcoexist); - /*5 g 3*/ - } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (switchband_notify 2g action 5) **********\n"); + "[BTCoex], switchband_notify --- BTC_SWITCH_TO_2G\n"); BTC_TRACE(trace_buf); - ex_halbtc8822b1ant_scan_notify(btcoexist, - BTC_SCAN_START_2G); + ex_halbtc8822b1ant_scan_notify(btcoexist, BTC_SCAN_START_2G); } + coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; } @@ -6394,189 +5998,145 @@ void ex_halbtc8822b1ant_switchband_notify_without_bt(IN struct btc_coexist *btcoexist, IN u8 type) { - boolean wifi_under_5g = FALSE; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (type == BTC_SWITCH_TO_5G) { - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, - 0x3, 1); - return; - } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { - - if (wifi_under_5g) - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, - 0x3, 1); - - else - btcoexist->btc_write_1byte_bitmask(btcoexist, - 0xcbd, 0x3, 2); - } else { - - ex_halbtc8822b1ant_scan_notify_without_bt(btcoexist, - BTC_SCAN_START_2G); - } + if (type == BTC_SWITCH_TO_5G) + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 1); + else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2); + else + ex_halbtc8822b1ant_scan_notify_without_bt(btcoexist, BTC_SCAN_START_2G); } void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist, IN u8 type) { - boolean wifi_connected = FALSE; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (connect notify) **********\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_post_state_to_bt(btcoexist, - BT_8822B_1ANT_SCOREBOARD_SCAN, TRUE); if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + btcoexist->stop_coex_dm) return; + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_ACTIVE | + BT_8822B_1ANT_SCOREBOARD_SCAN | + BT_8822B_1ANT_SCOREBOARD_ONOFF, + TRUE); - if ((BTC_ASSOCIATE_5G_START == type) || - (BTC_ASSOCIATE_5G_FINISH == type)) { - - if (BTC_ASSOCIATE_5G_START == type) { + if ((type == BTC_ASSOCIATE_5G_START) || + (type == BTC_ASSOCIATE_5G_FINISH)) { + if (type == BTC_ASSOCIATE_5G_START) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (5G associate start notify) **********\n"); - BTC_TRACE(trace_buf); - - halbtc8822b1ant_action_wifi_under5g(btcoexist); - - } else if (BTC_ASSOCIATE_5G_FINISH == type) { - + "[BTCoex], connect_notify --- 5G start\n"); + else BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (5G associate finish notify) **********\n"); - BTC_TRACE(trace_buf); + "[BTCoex], connect_notify --- 5G finish\n"); - } - - return; + BTC_TRACE(trace_buf); - } + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); + halbtc8822b1ant_run_coexist_mechanism(btcoexist); + } else if (type == BTC_ASSOCIATE_START) { - if (BTC_ASSOCIATE_START == type) { + coex_sta->wifi_is_high_pri_task = TRUE; + coex_dm->arp_cnt = 0; + coex_sta->connect_ap_period_cnt = 2; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2G CONNECT START notify\n"); + "[BTCoex], CONNECT START notify (2G)\n"); BTC_TRACE(trace_buf); - coex_sta->wifi_is_high_pri_task = TRUE; - - halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - coex_dm->arp_cnt = 0; + /* Force antenna setup for no scan result issue */ + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); - halbtc8822b1ant_action_wifi_not_connected_asso_auth(btcoexist); + halbtc8822b1ant_run_coexist_mechanism(btcoexist); + /* To keep TDMA case during connect process, + to avoid changed by Btinfo and runcoexmechanism */ coex_sta->freeze_coexrun_by_btinfo = TRUE; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2G CONNECT Finish notify\n"); - BTC_TRACE(trace_buf); coex_sta->wifi_is_high_pri_task = FALSE; coex_sta->freeze_coexrun_by_btinfo = FALSE; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify (2G)\n"); + BTC_TRACE(trace_buf); - if (!wifi_connected) /* non-connected scan */ - halbtc8822b1ant_action_wifi_not_connected(btcoexist); - else - halbtc8822b1ant_action_wifi_connected(btcoexist); + halbtc8822b1ant_run_coexist_mechanism(btcoexist); } } + void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist, IN u8 type) { boolean wifi_under_b_mode = FALSE; boolean wifi_under_5g = FALSE; - if (btcoexist->manual_control || btcoexist->stop_coex_dm) return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - - - if (BTC_MEDIA_CONNECT == type) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2g media connect notify"); - BTC_TRACE(trace_buf); + if (type == BTC_MEDIA_CONNECT) { halbtc8822b1ant_post_state_to_bt(btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE, TRUE); if (wifi_under_5g) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 5g media notify\n"); + "[BTCoex], media_status_notify --- 5G\n"); BTC_TRACE(trace_buf); - halbtc8822b1ant_action_wifi_under5g(btcoexist); - return; - } - /* Force antenna setup for no scan result issue */ - halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); + halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (media status notity under b mode) **********\n"); - BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ + halbtc8822b1ant_run_coexist_mechanism(btcoexist); } else { -#if 0 - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); /*CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); /*CCK Rx */ -#endif + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (media status notity not under b mode) **********\n"); + "[BTCoex], media_status_notify --- 2G\n"); BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); + /* Force antenna setup for no scan result issue */ + halbtc8822b1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], media status notity --- under b mode\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x00); /* CCK Rx */ + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], media status notity --- under b mode\n"); + BTC_TRACE(trace_buf); + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); /* CCK Rx */ + } + + halbtc8822b1ant_run_coexist_mechanism(btcoexist); + } } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], 2g media disconnect notify\n"); + "[BTCoex], media disconnect notify\n"); BTC_TRACE(trace_buf); coex_dm->arp_cnt = 0; @@ -6586,7 +6146,11 @@ void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist, btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ - coex_sta->cck_ever_lock = FALSE; + coex_sta->cck_lock_ever = FALSE; + coex_sta->cck_lock_warn = FALSE; + coex_sta->cck_lock = FALSE; + + halbtc8822b1ant_run_coexist_mechanism(btcoexist); } halbtc8822b1ant_update_wifi_channel_info(btcoexist, type); @@ -6608,7 +6172,7 @@ void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, "[BTCoex], 5g special packet notify\n"); BTC_TRACE(trace_buf); - halbtc8822b1ant_action_wifi_under5g(btcoexist); + halbtc8822b1ant_run_coexist_mechanism(btcoexist); return; } @@ -6645,9 +6209,11 @@ void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, coex_sta->specific_pkt_period_cnt = 2; } - if (coex_sta->wifi_is_high_pri_task) - halbtc8822b1ant_action_wifi_connected_specific_packet( - btcoexist); + if (coex_sta->wifi_is_high_pri_task) { + halbtc8822b1ant_post_state_to_bt(btcoexist, + BT_8822B_1ANT_SCOREBOARD_SCAN, TRUE); + halbtc8822b1ant_run_coexist_mechanism(btcoexist); + } } @@ -6661,13 +6227,6 @@ void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, wifi_busy = FALSE; static boolean is_scoreboard_scan = FALSE; - if (psd_scan->is_AntDet_running) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt_info_notify return for AntDet is running\n"); - BTC_TRACE(trace_buf); - return; - } - rsp_source = tmp_buf[0] & 0xf; if (rsp_source >= BT_INFO_SRC_8822B_1ANT_MAX) rsp_source = BT_INFO_SRC_8822B_1ANT_WIFI_FW; @@ -6678,6 +6237,19 @@ void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, length); BTC_TRACE(trace_buf); + if ((rsp_source == BT_INFO_SRC_8822B_1ANT_BT_RSP) || + (rsp_source == BT_INFO_SRC_8822B_1ANT_BT_ACTIVE_SEND)) { + if (coex_sta->bt_disabled) { + coex_sta->bt_disabled = FALSE; + coex_sta->is_bt_reenable = TRUE; + coex_sta->cnt_bt_reenable = 15; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT enable detected by bt_info\n"); + BTC_TRACE(trace_buf); + } + } + for (i = 0; i < length; i++) { coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; @@ -6720,7 +6292,7 @@ void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, 0x10) ? TRUE : FALSE); coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & - 0x9) ? TRUE : FALSE); + 0x8) ? TRUE : FALSE); coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? TRUE : FALSE); @@ -6745,6 +6317,9 @@ void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; + + coex_sta->is_bt_opp_exist = (coex_sta->bt_info_ext2 & 0x1) ? TRUE : FALSE; + if (coex_sta->bt_retry_cnt >= 1) coex_sta->pop_event_cnt++; @@ -6757,16 +6332,14 @@ void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, if (coex_sta->bt_info_ext & BIT(2)) { coex_sta->cnt_setupLink++; coex_sta->is_setupLink = TRUE; + + if (coex_sta->is_bt_reenable) + coex_sta->bt_relink_downcount = 8; + else coex_sta->bt_relink_downcount = 2; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Re-Link start in BT info!!\n"); BTC_TRACE(trace_buf); - } else { - coex_sta->is_setupLink = FALSE; - coex_sta->bt_relink_downcount = 0; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Re-Link stop in BT info!!\n"); - BTC_TRACE(trace_buf); } if (coex_sta->bt_info_ext & BIT(3)) @@ -6780,12 +6353,20 @@ void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, else coex_sta->is_bt_multi_link = FALSE; + if (coex_sta->bt_info_ext & BIT(0)) + coex_sta->is_hid_rcu = TRUE; + else + coex_sta->is_hid_rcu = FALSE; + + if (coex_sta->bt_info_ext & BIT(5)) + coex_sta->is_ble_scan_en = TRUE; + else + coex_sta->is_ble_scan_en = FALSE; + if (coex_sta->bt_create_connection) { coex_sta->cnt_Page++; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, - &wifi_busy); - + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); @@ -6846,35 +6427,108 @@ void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, } - if ((coex_sta->bt_info_ext & BIT(5))) { + halbtc8822b1ant_update_bt_link_info(btcoexist); + + halbtc8822b1ant_run_coexist_mechanism(btcoexist); +} + + +void ex_halbtc8822b1ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 i = 0; + static u8 tmp_buf_pre[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi Fw Dbg info = %d %d %d %d %d %d (len = %d)\n", + tmp_buf[0], tmp_buf[1], + tmp_buf[2], tmp_buf[3], + tmp_buf[4], tmp_buf[5], length); + BTC_TRACE(trace_buf); + + if (tmp_buf[0] == 0x8) { + for (i = 1; i <= 5; i++) { + coex_sta->wl_fw_dbg_info[i] = + (tmp_buf[i] >= tmp_buf_pre[i]) ? + (tmp_buf[i] - tmp_buf_pre[i]) : + (255 - tmp_buf_pre[i] + tmp_buf[i]); + + tmp_buf_pre[i] = tmp_buf[i]; + } + } +} + + +void ex_halbtc8822b1ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist, + IN BOOLEAN is_data_frame, IN u8 btc_rate_id) +{ + BOOLEAN wifi_connected = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + if (is_data_frame) { + coex_sta->wl_rx_rate = btc_rate_id; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + "[BTCoex], rx_rate_change_notify data rate id = %d, RTS_Rate = %d\n", + coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate); BTC_TRACE(trace_buf); - coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( - btcoexist); - - if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) - coex_sta->bt_ble_scan_para[0] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x1); - if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) - coex_sta->bt_ble_scan_para[1] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x2); - if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) - coex_sta->bt_ble_scan_para[2] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x4); + } else { + coex_sta->wl_rts_rx_rate = btc_rate_id; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], rts_rate_change_notify RTS rate id = %d, RTS_Rate = %d\n", + coex_sta->wl_rts_rx_rate, coex_sta->wl_rts_rx_rate); + BTC_TRACE(trace_buf); } + if ((wifi_connected) && + ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY))) { - halbtc8822b1ant_update_bt_link_info(btcoexist); + if ((coex_sta->wl_rx_rate == BTC_CCK_5_5) || + (coex_sta->wl_rx_rate == BTC_OFDM_6) || + (coex_sta->wl_rx_rate == BTC_MCS_0)) { + + coex_sta->cck_lock_warn = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], cck lock warning...\n"); + BTC_TRACE(trace_buf); + } else if ((coex_sta->wl_rx_rate == BTC_CCK_1) || + (coex_sta->wl_rx_rate == BTC_CCK_2) || + (coex_sta->wl_rts_rx_rate == BTC_CCK_1) || + (coex_sta->wl_rts_rx_rate == BTC_CCK_2)) { + + coex_sta->cck_lock = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], cck locking...\n"); + BTC_TRACE(trace_buf); + } else { + coex_sta->cck_lock_warn = FALSE; + coex_sta->cck_lock = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], cck unlock...\n"); + BTC_TRACE(trace_buf); + } + } else { + if ((coex_dm->bt_status == + BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE) || + (coex_dm->bt_status == + BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE)) { + coex_sta->cck_lock_warn = FALSE; + coex_sta->cck_lock = FALSE; + } + } - halbtc8822b1ant_run_coexist_mechanism(btcoexist); } + void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, IN u8 type) { @@ -6886,11 +6540,7 @@ void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, "[BTCoex], RF is turned ON!!\n"); BTC_TRACE(trace_buf); btcoexist->stop_coex_dm = FALSE; - - halbtc8822b1ant_post_state_to_bt(btcoexist, - BT_8822B_1ANT_SCOREBOARD_ACTIVE, TRUE); - halbtc8822b1ant_post_state_to_bt(btcoexist, - BT_8822B_1ANT_SCOREBOARD_ONOFF, TRUE); + coex_sta->is_rf_state_off = FALSE; } else if (BTC_RF_OFF == type) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -6898,9 +6548,12 @@ void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, BTC_TRACE(trace_buf); halbtc8822b1ant_post_state_to_bt(btcoexist, - BT_8822B_1ANT_SCOREBOARD_ACTIVE, FALSE); - halbtc8822b1ant_post_state_to_bt(btcoexist, - BT_8822B_1ANT_SCOREBOARD_ONOFF, FALSE); + BT_8822B_1ANT_SCOREBOARD_ACTIVE | + BT_8822B_1ANT_SCOREBOARD_ONOFF | + BT_8822B_1ANT_SCOREBOARD_SCAN | + BT_8822B_1ANT_SCOREBOARD_UNDERTEST, + FALSE); + halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); halbtc8822b1ant_set_ant_path(btcoexist, @@ -6912,6 +6565,7 @@ void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, TRUE); btcoexist->stop_coex_dm = TRUE; + coex_sta->is_rf_state_off = TRUE; } } @@ -6922,21 +6576,24 @@ void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist) BTC_TRACE(trace_buf); halbtc8822b1ant_post_state_to_bt(btcoexist, - BT_8822B_1ANT_SCOREBOARD_ACTIVE, FALSE); - halbtc8822b1ant_post_state_to_bt(btcoexist, - BT_8822B_1ANT_SCOREBOARD_ONOFF, FALSE); - - halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); + BT_8822B_1ANT_SCOREBOARD_ACTIVE | + BT_8822B_1ANT_SCOREBOARD_ONOFF | + BT_8822B_1ANT_SCOREBOARD_SCAN | + BT_8822B_1ANT_SCOREBOARD_UNDERTEST | + BT_8822B_1ANT_SCOREBOARD_RXGAIN, + FALSE); halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8822B_1ANT_PHASE_WLAN_OFF); - /* for test : s3 bt disppear , fail rate 1/600*/ + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_WLAN_OFF); halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, TRUE); ex_halbtc8822b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + + halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); + btcoexist->stop_coex_dm = TRUE; } @@ -6961,25 +6618,26 @@ void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE | BT_8822B_1ANT_SCOREBOARD_ONOFF | BT_8822B_1ANT_SCOREBOARD_SCAN | - BT_8822B_1ANT_SCOREBOARD_UNDERTEST, + BT_8822B_1ANT_SCOREBOARD_UNDERTEST | + BT_8822B_1ANT_SCOREBOARD_RXGAIN, FALSE); if (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) { if (wifi_under_5g) halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_5G_RUNTIME); + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_5G_RUNTIME); else halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_1ANT_PHASE_2G_RUNTIME); + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_1ANT_PHASE_2G_RUNTIME); } else { halbtc8822b1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8822B_1ANT_PHASE_WLAN_OFF); + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_1ANT_PHASE_WLAN_OFF); } btcoexist->stop_coex_dm = TRUE; @@ -6994,7 +6652,6 @@ void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist, BT_8822B_1ANT_SCOREBOARD_ONOFF, TRUE); #endif - btcoexist->stop_coex_dm = FALSE; } } @@ -7010,6 +6667,10 @@ void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist) { + + boolean wifi_busy = FALSE; + u16 bt_scoreboard_val = 0; + u32 bt_patch_ver; boolean bt_relink_finish = FALSE; #if 0 @@ -7022,10 +6683,6 @@ void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist) #if (BT_AUTO_REPORT_ONLY_8822B_1ANT == 0) halbtc8822b1ant_query_bt_info(btcoexist); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ==========================Periodical-auto report only===========================\n"); - BTC_TRACE(trace_buf); - #endif halbtc8822b1ant_monitor_bt_ctr(btcoexist); @@ -7033,23 +6690,6 @@ void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist) halbtc8822b1ant_monitor_bt_enable_disable(btcoexist); -#if 0 - /*RF4CE for arris , rf4ce always on*/ - btcoexist->btc_get(btcoexist, BTC_GET_BL_RF4CE_CONNECTED, &rf4ce_connected); - if (rf4ce_connected){ - btcoexist->btc_write_1byte_bitmask( - btcoexist, 0x45e, 0x8, 0x1); - - halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, - 50); - - halbtc8822b1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - return; - } -#endif - if (coex_sta->bt_relink_downcount != 0) { coex_sta->bt_relink_downcount--; @@ -7075,7 +6715,22 @@ void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist) BTC_TRACE(trace_buf); } - if (halbtc8822b1ant_is_wifi_status_changed(btcoexist) || (bt_relink_finish) + /*for A2DP glitch during connecting AP*/ + if (coex_sta->connect_ap_period_cnt > 0) + coex_sta->connect_ap_period_cnt--; + + if (coex_sta->cnt_bt_reenable > 0) { + coex_sta->cnt_bt_reenable--; + if (coex_sta->cnt_bt_reenable == 0) { + coex_sta->is_bt_reenable = false; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT renable 30s finish!!\n"); + BTC_TRACE(trace_buf); + } + } + + if (halbtc8822b1ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish) || (coex_sta->is_set_ps_state_fail)) halbtc8822b1ant_run_coexist_mechanism(btcoexist); } @@ -7118,11 +6773,8 @@ void ex_halbtc8822b1ant_switch_band_without_bt(IN struct btc_coexist *btcoexist, { /* ant switch WL2G or WL5G*/ if (wifi_only_5g) - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 1); - else - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2); } diff --git a/hal/btc/halbtc8822b1ant.h b/hal/btc/halbtc8822b1ant.h index 0ba1193..2ec4f7c 100644 --- a/hal/btc/halbtc8822b1ant.h +++ b/hal/btc/halbtc8822b1ant.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) @@ -143,6 +157,7 @@ enum bt_8822b_1ant_ext_ant_switch_pos_type { BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG = 0x1, BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA = 0x2, BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE = 0x3, + BT_8822B_1ANT_EXT_ANT_SWITCH_TO_S0WLG_S1BT = 0x4, BT_8822B_1ANT_EXT_ANT_SWITCH_TO_MAX }; @@ -153,16 +168,24 @@ enum bt_8822b_1ant_phase { BT_8822B_1ANT_PHASE_2G_RUNTIME = 0x3, BT_8822B_1ANT_PHASE_5G_RUNTIME = 0x4, BT_8822B_1ANT_PHASE_BTMPMODE = 0x5, + BT_8822B_1ANT_PHASE_COEX_POWERON = 0x6, + BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL = 0x7, + BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_BT = 0x8, + BT_8822B_1ANT_PHASE_MCC_DUALBAND_RUNTIME = 0x9, + BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_S0WLS1BT = 0xa, BT_8822B_1ANT_PHASE_MAX }; /*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/ enum bt_8822b_1ant_Scoreboard { - BT_8822B_1ANT_SCOREBOARD_ACTIVE = BIT(0), - BT_8822B_1ANT_SCOREBOARD_ONOFF = BIT(1), - BT_8822B_1ANT_SCOREBOARD_SCAN = BIT(2), - BT_8822B_1ANT_SCOREBOARD_UNDERTEST = BIT(3), - BT_8822B_1ANT_SCOREBOARD_WLBUSY = BIT(6) + BT_8822B_1ANT_SCOREBOARD_ACTIVE = BIT(0), + BT_8822B_1ANT_SCOREBOARD_ONOFF = BIT(1), + BT_8822B_1ANT_SCOREBOARD_SCAN = BIT(2), + BT_8822B_1ANT_SCOREBOARD_UNDERTEST = BIT(3), + BT_8822B_1ANT_SCOREBOARD_RXGAIN = BIT(4), + BT_8822B_1ANT_SCOREBOARD_WLBUSY = BIT(6), + BT_8822B_1ANT_SCOREBOARD_EXTFEM = BIT(8), + BT_8822B_1ANT_SCOREBOARD_BTCQDDR = BIT(10) }; struct coex_dm_8822b_1ant { @@ -185,6 +208,8 @@ struct coex_dm_8822b_1ant { u8 cur_lps; u8 pre_rpwm; u8 cur_rpwm; + u8 pre_bt_dec_pwr_lvl; + u8 cur_bt_dec_pwr_lvl; u8 pre_fw_dac_swing_lvl; u8 cur_fw_dac_swing_lvl; @@ -237,6 +262,7 @@ struct coex_sta_8822b_1ant { boolean a2dp_exist; boolean hid_exist; boolean pan_exist; + boolean msft_mr_exist; u8 num_of_profile; boolean under_lps; @@ -274,9 +300,10 @@ struct coex_sta_8822b_1ant { u32 crc_err_11n; u32 crc_err_11n_vht; - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; + boolean cck_lock; + boolean cck_lock_ever; + boolean cck_lock_warn; + u8 coex_table_type; boolean force_lps_ctrl; @@ -332,10 +359,30 @@ struct coex_sta_8822b_1ant { boolean is_hid_low_pri_tx_overhead; boolean is_bt_multi_link; boolean is_bt_a2dp_sink; - boolean rf4ce_enabled; boolean is_set_ps_state_fail; u8 cnt_set_ps_state_fail; + + u8 wl_fw_dbg_info[10]; + u8 wl_rx_rate; + u8 wl_rts_rx_rate; + u8 wl_center_channel; + + u16 score_board_WB; + boolean is_hid_rcu; + u16 legacy_forbidden_slot; + u16 le_forbidden_slot; + u8 bt_a2dp_vendor_id; + u32 bt_a2dp_device_name; + boolean is_ble_scan_en; + + boolean is_bt_opp_exist; + boolean gl_wifi_busy; + + boolean is_mimo_ps; + u8 connect_ap_period_cnt; + boolean is_bt_reenable; + u8 cnt_bt_reenable; }; struct rfe_type_8822b_1ant { @@ -419,6 +466,10 @@ void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, IN u8 type); void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist, IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8822b1ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8822b1ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist, + IN BOOLEAN is_data_frame, IN u8 btc_rate_id); void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist, IN u8 type); void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist); @@ -428,6 +479,8 @@ void ex_halbtc8822b1ant_ScoreBoardStatusNotify(IN struct btc_coexist *btcoexist, IN u8 *tmp_buf, IN u8 length); void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b1ant_display_simple_coex_info(IN struct btc_coexist *btcoexist); + void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist); void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist, IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); @@ -456,6 +509,8 @@ void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist, #define ex_halbtc8822b1ant_media_status_notify(btcoexist, type) #define ex_halbtc8822b1ant_specific_packet_notify(btcoexist, type) #define ex_halbtc8822b1ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8822b1ant_wl_fwdbginfo_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8822b1ant_rx_rate_change_notify(btcoexist, is_data_frame, btc_rate_id) #define ex_halbtc8822b1ant_rf_status_notify(btcoexist, type) #define ex_halbtc8822b1ant_halt_notify(btcoexist) #define ex_halbtc8822b1ant_pnp_notify(btcoexist, pnp_state) diff --git a/hal/btc/halbtc8822b2ant.c b/hal/btc/halbtc8822b2ant.c index 4dc1bb4..6fdf427 100644 --- a/hal/btc/halbtc8822b2ant.c +++ b/hal/btc/halbtc8822b2ant.c @@ -1,3 +1,19 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + + /* ************************************************************ * Description: * @@ -35,9 +51,9 @@ static const char *const glbt_info_src_8822b_2ant[] = { "BT Info[bt auto report]", }; -static u32 glcoex_ver_date_8822b_2ant = 20170518; -static u32 glcoex_ver_8822b_2ant = 0x44; -static u32 glcoex_ver_btdesired_8822b_2ant = 0x42; +u32 glcoex_ver_date_8822b_2ant = 20180427; +u32 glcoex_ver_8822b_2ant = 0x59; +u32 glcoex_ver_btdesired_8822b_2ant = 0x56; /* ************************************************************ @@ -182,14 +198,22 @@ void halbtc8822b2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist, interference_bt_tx = BT_8822B_2ANT_BT_MAX_TX_POWER - isolation_measuared; + /* coex_sta->isolation_btween_wb default = 25dB, should be from config file */ + if (coex_sta->isolation_btween_wb > 20) { + coex_sta->wifi_coex_thres = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; + coex_sta->wifi_coex_thres2 = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2; - coex_sta->wifi_coex_thres = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; - coex_sta->wifi_coex_thres2 = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2; + coex_sta->bt_coex_thres = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1; + coex_sta->bt_coex_thres2 = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2; + } else { - coex_sta->bt_coex_thres = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1; - coex_sta->bt_coex_thres2 = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2; + coex_sta->wifi_coex_thres = 90; + coex_sta->wifi_coex_thres2 = 90; + coex_sta->bt_coex_thres = 90; + coex_sta->bt_coex_thres2 = 90; + } #if 0 coex_sta->wifi_coex_thres = interference_wl_tx + BT_8822B_2ANT_WIFI_SIR_THRES1; @@ -200,9 +224,6 @@ void halbtc8822b2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist, #endif - - - #if 0 if (BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - BT_8822B_2ANT_DEFAULT_ISOLATION)) @@ -321,7 +342,7 @@ void halbtc8822b2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) } if (bt_link_info->hid_only) { - if (coex_sta->low_priority_rx > 50) + if (coex_sta->low_priority_tx > 50) coex_sta->is_hid_low_pri_tx_overhead = true; else coex_sta->is_hid_low_pri_tx_overhead = false; @@ -343,83 +364,101 @@ void halbtc8822b2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) static void halbtc8822b2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) { -#if 1 - s32 wifi_rssi = 0; - boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE, - wifi_scan = FALSE; - boolean bt_idle = FALSE; - static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, - wl_noisy_count1 = 3, wl_noisy_count2 = 0; - u32 total_cnt, cck_cnt; - u32 cnt_crcok = 0, cnt_crcerr = 0; - static u8 cnt = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - - coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_VHT); + s32 wifi_rssi = 0; + boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE, + wifi_scan = FALSE; + boolean bt_idle = FALSE; + static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, + wl_noisy_count1 = 3, wl_noisy_count2 = 0; + u32 total_cnt, cnt_cck; + u32 cnt_crcok = 0, cnt_crcerr = 0; + static u8 cnt = 0, cnt_ccklocking = 0; + u8 h2c_parameter[1] = {0}; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - cnt_crcok = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g - + coex_sta->crc_ok_11n - + coex_sta->crc_ok_11n_vht; + /* Only enable for windows becaus 8821cu H2C 0x69 unknown fail @ linux */ + if (btcoexist->chip_interface != BTC_INTF_USB) { + /*send h2c to query WL FW dbg info */ + if (((coex_dm->cur_ps_tdma_on) && (coex_sta->force_lps_ctrl)) || + ((coex_sta->acl_busy) && (bt_link_info->a2dp_exist))) { + h2c_parameter[0] = 0x8; + btcoexist->btc_fill_h2c(btcoexist, 0x69, 1, h2c_parameter); + } + } - cnt_crcerr = coex_sta->crc_err_cck + coex_sta->crc_err_11g - + coex_sta->crc_err_11n - + coex_sta->crc_err_11n_vht; + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); - if ((wifi_busy) && (cnt_crcerr != 0)) { + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - coex_sta->now_crc_ratio = cnt_crcok/cnt_crcerr; + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_VHT); - if (cnt == 0) - coex_sta->acc_crc_ratio = coex_sta->now_crc_ratio; - else - coex_sta->acc_crc_ratio = (coex_sta->acc_crc_ratio * 7 + - coex_sta->now_crc_ratio * 3)/10; + cnt_crcok = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + + coex_sta->crc_ok_11n_vht; - if (cnt >= 10) - cnt = 0; - else - cnt++; - } + cnt_crcerr = coex_sta->crc_err_cck + coex_sta->crc_err_11g + + coex_sta->crc_err_11n + + coex_sta->crc_err_11n_vht; - cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; + if ((wifi_busy) && (cnt_crcerr != 0)) { - if ((coex_dm->bt_status == - BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE) || - (coex_dm->bt_status == - BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE) || - (coex_sta->bt_disabled)) - bt_idle = TRUE; + coex_sta->now_crc_ratio = cnt_crcok/cnt_crcerr; + + if (cnt == 0) + coex_sta->acc_crc_ratio = coex_sta->now_crc_ratio; + else + coex_sta->acc_crc_ratio = (coex_sta->acc_crc_ratio * 7 + + coex_sta->now_crc_ratio * 3)/10; + + if (cnt >= 10) + cnt = 0; + else + cnt++; + } + + + /* CCK lock identification */ + if (coex_sta->cck_lock) + cnt_ccklocking++; + else if (cnt_ccklocking != 0) + cnt_ccklocking--; + + if (cnt_ccklocking >= 3) { + cnt_ccklocking = 3; + coex_sta->cck_lock_ever = TRUE; + } + + /* WiFi environment noisy identification */ + cnt_cck = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; - if (cck_cnt > 250) { + if ((!wifi_busy) && (!coex_sta->cck_lock)) { + if (cnt_cck > 250) { if (wl_noisy_count2 < 3) wl_noisy_count2++; @@ -428,7 +467,7 @@ void halbtc8822b2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) wl_noisy_count1 = 0; } - } else if (cck_cnt < 50) { + } else if (cnt_cck < 100) { if (wl_noisy_count0 < 3) wl_noisy_count0++; @@ -453,53 +492,7 @@ void halbtc8822b2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) coex_sta->wl_noisy_level = 1; else coex_sta->wl_noisy_level = 0; - - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = cnt_crcok; - - if ((coex_dm->bt_status == - BT_8822B_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == - BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == - BT_8822B_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - - if (!coex_sta->pre_ccklock) { - - if (cck_lock_counter >= 3) - coex_sta->cck_lock = TRUE; - else - coex_sta->cck_lock = FALSE; - } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = FALSE; - else - coex_sta->cck_lock = TRUE; - } - - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = TRUE; - - coex_sta->pre_ccklock = coex_sta->cck_lock; - -#endif + } } @@ -515,13 +508,26 @@ boolean halbtc8822b2ant_is_wifibt_status_changed(IN struct btc_coexist boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE; boolean wifi_connected = FALSE; struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + static u8 cnt_wifi_busytoidle = 0; + u32 wifi_link_status = 0, num_of_wifi_link = 0; + static u32 pre_num_of_wifi_link = 0; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + + if (wifi_busy) { + coex_sta->gl_wifi_busy = TRUE; + cnt_wifi_busytoidle = 6; + } else { + if ((coex_sta->gl_wifi_busy) && (cnt_wifi_busytoidle > 0)) + cnt_wifi_busytoidle--; + else if (cnt_wifi_busytoidle == 0) + coex_sta->gl_wifi_busy = FALSE; + } if (coex_sta->bt_disabled != pre_bt_off) { pre_bt_off = coex_sta->bt_disabled; @@ -543,9 +549,19 @@ boolean halbtc8822b2ant_is_wifibt_status_changed(IN struct btc_coexist coex_sta->bt_ble_scan_para[2] = 0; coex_sta->bt_reg_vendor_ac = 0xffff; coex_sta->bt_reg_vendor_ae = 0xffff; + coex_sta->legacy_forbidden_slot = 0; + coex_sta->le_forbidden_slot = 0; + coex_sta->bt_a2dp_vendor_id = 0; + coex_sta->bt_a2dp_device_name = 0; return TRUE; } + num_of_wifi_link = wifi_link_status >> 16; + + if (num_of_wifi_link != pre_num_of_wifi_link) { + pre_num_of_wifi_link = num_of_wifi_link; + return TRUE; + } if (wifi_connected) { if (wifi_busy != pre_wifi_busy) { @@ -604,6 +620,33 @@ void halbtc8822b2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; boolean bt_hs_on = FALSE; boolean bt_busy = FALSE; + u32 val = 0; + static u8 pre_num_of_profile = 0, cur_num_of_profile = 0, cnt = 0; + static u8 wd_cnt = 0; + + if (++wd_cnt >= 3) + wd_cnt = 0; + + if (coex_sta->is_ble_scan_en && (wd_cnt == 0)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + BTC_TRACE(trace_buf); + coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( + btcoexist); + + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x4); + } coex_sta->num_of_profile = 0; @@ -734,130 +777,119 @@ void halbtc8822b2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) BTC_TRACE(trace_buf); - if ((BT_8822B_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8822B_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + if ((coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_SCO_BUSY) || + (coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY)) bt_busy = TRUE; else bt_busy = FALSE; btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); -} + cur_num_of_profile = coex_sta->num_of_profile; -static -void halbtc8822b2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - u32 RTL97F_8822B = 0; + if (cur_num_of_profile != pre_num_of_profile) + cnt = 2; - if (RTL97F_8822B) - return; + if (bt_link_info->a2dp_exist) { - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - /* enable BT AFH skip WL channel for 8822b - * because BT Rx LO interference - */ - h2c_parameter[0] = 0x1; -#if 0 - h2c_parameter[0] = 0x0; -#endif - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } + if (((coex_sta->bt_a2dp_vendor_id == 0) && + (coex_sta->bt_a2dp_device_name == 0)) || + (cur_num_of_profile != pre_num_of_profile)) { - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_DEVICE_INFO, &val); - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), get BT DEVICE_INFO = %x\n", val); + BTC_TRACE(trace_buf); -} + coex_sta->bt_a2dp_vendor_id = (u8)(val & 0xff); + coex_sta->bt_a2dp_device_name = (val & 0xffffff00) >> 8; + } + if (((coex_sta->legacy_forbidden_slot == 0) && + (coex_sta->le_forbidden_slot == 0)) || + (cur_num_of_profile != pre_num_of_profile) || + (cnt > 0)) { -static -void halbtc8822b2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - u32 RTL97F_8822B = 0; + if (cnt > 0) + cnt--; - if (RTL97F_8822B) - return; + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL, &val); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), get BT FORBIDDEN_SLOT_VAL = %x\n", val); + BTC_TRACE(trace_buf); - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; + coex_sta->legacy_forbidden_slot = (u16)(val & 0xffff); + coex_sta->le_forbidden_slot = (u16)((val & 0xffff0000) >> 16); + } + } - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); + pre_num_of_profile = coex_sta->num_of_profile; } static -void halbtc8822b2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) +void halbtc8822b2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, + IN u8 type) { - u32 RTL97F_8822B = 0; + u8 h2c_parameter[3] = {0}, i; + u32 wifi_bw; + u8 wifi_central_chnl = 0; + u8 wifi_5g_chnl[19] = {120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 118, 126, 134, 142, 151, 159, 122, 138, 155}; + u8 bt_skip_cneter_chanl[19] = {2, 8, 17, 26, 34, 42, 51, 62, 71, 77, 2, 12, 29, 46, 66, 76, 10, 37, 68}; + u8 bt_skip_span[19] = {4, 8, 8, 10, 8, 10, 8, 8, 10, 4, 4, 16, 16, 16, 16, 4, 20, 34, 20}; + boolean wifi_under_5g = FALSE; - if (RTL97F_8822B) - return; - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } + if (type == BTC_MEDIA_CONNECT) { + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + coex_sta->wl_center_channel = wifi_central_chnl; - halbtc8822b2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); + if (!wifi_under_5g) { - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} + h2c_parameter[0] = 0x1; + h2c_parameter[1] = wifi_central_chnl; -static -void halbtc8822b2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN u8 dec_bt_pwr_lvl) -{ - u32 RTL97F_8822B = 0; - u8 h2c_parameter[1] = {0}; + if (wifi_bw == BTC_WIFI_BW_HT40) + h2c_parameter[2] = 0x36; + else + h2c_parameter[2] = 0x30; + } else { /* for 5G */ - if (RTL97F_8822B) - return; + for (i = 0; i <= 18; i++) { + if (wifi_central_chnl == wifi_5g_chnl[i]) + break; + } - h2c_parameter[0] = dec_bt_pwr_lvl; + if (i <= 18) { + h2c_parameter[0] = 0x3; + h2c_parameter[1] = bt_skip_cneter_chanl[i]; + h2c_parameter[2] = bt_skip_span[i]; + } - btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); -} + } + } -static -void halbtc8822b2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 dec_bt_pwr_lvl) -{ - coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - if (!force_exec) { - if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) - return; - } - halbtc8822b2ant_set_fw_dec_bt_pwr(btcoexist, - coex_dm->cur_bt_dec_pwr_lvl); + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], para[0:2] = 0x%x 0x%x 0x%x\n", + h2c_parameter[0], h2c_parameter[1], h2c_parameter[2]); + BTC_TRACE(trace_buf); - coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; } + static void halbtc8822b2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN boolean low_penalty_ra) @@ -873,7 +905,7 @@ void halbtc8822b2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, } if (low_penalty_ra) - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 50); + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 10); else btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); @@ -891,18 +923,27 @@ void halbtc8822b2ant_write_score_board( ) { - static u16 originalval = 0x8002; + static u16 originalval = 0x8002, preval = 0x0; if (state) originalval = originalval | bitpos; else originalval = originalval & (~bitpos); + coex_sta->score_board_WB = originalval; - btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); + if (originalval != preval) { + preval = originalval; + btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8822b2ant_write_score_board: return for nochange\n"); + BTC_TRACE(trace_buf); + } } + static void halbtc8822b2ant_read_score_board( IN struct btc_coexist *btcoexist, @@ -926,71 +967,241 @@ void halbtc8822b2ant_post_state_to_bt( } +static +void halbtc8822b2ant_adjust_wl_tx_power(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 fw_dac_swing_lvl) +{ + + coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; + + if (!force_exec) { + if (coex_dm->pre_fw_dac_swing_lvl == + coex_dm->cur_fw_dac_swing_lvl) + return; + } + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0xff, fw_dac_swing_lvl); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe5b, 0xff, fw_dac_swing_lvl); + coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; +} static -void halbtc8822b2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +void halbtc8822b2ant_adjust_bt_tx_power(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 dec_bt_pwr_lvl) { - static u32 bt_disable_cnt = 0; - boolean bt_active = TRUE, bt_disabled = FALSE, wifi_under_5g = FALSE; - u16 u16tmp; + u8 h2c_parameter[1] = {0}; - /* This function check if bt is disabled */ -#if 0 - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = FALSE; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = FALSE; + coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; + if (!force_exec) { + if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) + return; + } -#else + //h2c_parameter[0] = 0 - dec_bt_pwr_lvl; + h2c_parameter[0] = dec_bt_pwr_lvl; - /* Read BT on/off status from scoreboard[1], - * enable this only if BT patch support this feature - */ - halbtc8822b2ant_read_score_board(btcoexist, &u16tmp); - bt_active = u16tmp & BIT(1); + btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); + coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; +} -#endif +static +void halbtc8822b2ant_adjust_wl_rx_gain(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean agc_table_en) +{ - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = FALSE; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } else { + /*20171116*/ + + u32 rx_gain_value_enable[] = {0xff000003, + 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, 0xbf050003, + 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, 0xb81c0003, + 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, 0xb3260003, + 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, 0xae300003, + 0xad320003, 0xac340003, 0xab360003, 0x8d380003, 0x8c3a0003, + 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 0x6c440003, + 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 0x674e0003, + 0x66500003, 0x65520003, 0x64540003, 0x64560003, 0x007e0403}; + + u32 rx_gain_value_disable[] = {0xff000003, + 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, 0xf80a0003, + 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, 0xef1c0003, + 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, 0xea260003, + 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 0xe5300003, + 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 0xc43a0003, + 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 0xa5440003, + 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 0x834e0003, + 0x82500003, 0x81520003, 0x80540003, 0x65560003, 0x007e0403}; - bt_disable_cnt++; - if (bt_disable_cnt >= 10) { - bt_disabled = TRUE; - bt_disable_cnt = 10; - } - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } +#if 0 + /*20170110*/ - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + u32 rx_gain_value_enable[] = {0xff000003, + 0xb6200003, 0xb5220003, 0xb4240003, 0xb3260003, + 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, 0xae300003, + 0xad320003, 0xac340003, 0xab360003, 0x8d380003, 0x8c3a0003, + 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 0x6c440003, + 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 0x674e0003, + 0x66500003, 0x65520003, 0x64540003, 0x64560003, 0x007e0403}; - if ((wifi_under_5g) || (bt_disabled)) - halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); - else - halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE); + /*20170110*/ - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); + u32 rx_gain_value_disable[] = {0xff000003, 0xeb240003, 0xea260003, + 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 0xe5300003, + 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 0xc43a0003, + 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 0xa5440003, + 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 0x834e0003, + 0x82500003, 0x81520003, 0x80540003, 0x65560003, 0x007e0403}; +#endif + u8 i; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], *************wl rx gain*************\n"); + BTC_TRACE(trace_buf); + + coex_dm->cur_agc_table_en = agc_table_en; + + if (!force_exec) { + if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) + return; + } + + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table On!\n"); + BTC_TRACE(trace_buf); + + for (i = 0; i <= 100; i++) { + btcoexist->btc_write_4byte(btcoexist, + 0x81c, rx_gain_value_enable[i]); + + if (rx_gain_value_enable[i] == 0x007e0403) + break; + } + + /* set Rx filter corner RCK offset */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde, 0x2, 0x1); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d, 0x3f, 0x3f); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_B, 0xde, 0x2, 0x1); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_B, 0x1d, 0x3f, 0x3f); + /* ADC clock 80M */ + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8ad, 0x3, 0x3); */ + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table Off!\n"); + BTC_TRACE(trace_buf); + + for (i = 0; i <= 100; i++) { + btcoexist->btc_write_4byte(btcoexist, + 0x81c, rx_gain_value_disable[i]); + + if (rx_gain_value_disable[i] == 0x007e0403) + break; + } + + /* set Rx filter corner RCK offset */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d, 0x3f, 0x4); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde, 0x2, 0x0); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_B, 0x1d, 0x3f, 0x4); + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_B, 0xde, 0x2, 0x0); + /* ADC clock 160M */ + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8ad, 0x3, 0x0); */ + } + + + coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; +} + +static +void halbtc8822b2ant_adjust_bt_rx_gain(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rx_gain_en) +{ + u8 lna_constrain_level = 0; + + /* use scoreboard[4] to notify BT Rx gain table change */ + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_RXGAIN, + rx_gain_en); + + if (rx_gain_en) + lna_constrain_level = 1; + else + lna_constrain_level = 7; + + btcoexist->btc_set(btcoexist, + BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL, + &lna_constrain_level); +} + + +static +void halbtc8822b2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = TRUE, bt_disabled = FALSE, wifi_under_5g = FALSE; + u16 u16tmp; + + /* This function check if bt is disabled */ +#if 0 + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) + bt_active = FALSE; + if (coex_sta->high_priority_tx == 0xffff && + coex_sta->high_priority_rx == 0xffff && + coex_sta->low_priority_tx == 0xffff && + coex_sta->low_priority_rx == 0xffff) + bt_active = FALSE; + + +#else + + /* Read BT on/off status from scoreboard[1], + * enable this only if BT patch support this feature + */ + halbtc8822b2ant_read_score_board(btcoexist, &u16tmp); + + bt_active = u16tmp & BIT(1); + + +#endif + + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = FALSE; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } else { + + bt_disable_cnt++; + if (bt_disable_cnt >= 10) { + bt_disabled = TRUE; + bt_disable_cnt = 10; + } + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((wifi_under_5g) || (bt_disabled)) + halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); + else + halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE); + + + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); BTC_TRACE(trace_buf); coex_sta->bt_disabled = bt_disabled; } @@ -1079,7 +1290,7 @@ u32 halbtc8822b2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, while (1) { if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { - delay_ms(50); + delay_ms(10); delay_count++; if (delay_count >= 10) { delay_count = 0; @@ -1113,7 +1324,7 @@ void halbtc8822b2ant_ltecoex_indirect_write_reg(IN struct btc_coexist /* wait for ready bit before access 0x1700/0x1704 */ while (1) { if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { - delay_ms(50); + delay_ms(10); delay_count++; if (delay_count >= 10) { delay_count = 0; @@ -1145,7 +1356,7 @@ void halbtc8822b2ant_ltecoex_indirect_write_reg(IN struct btc_coexist /* wait for ready bit before access 0x1700/0x1704 */ while (1) { if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { - delay_ms(50); + delay_ms(10); delay_count++; if (delay_count >= 10) { delay_count = 0; @@ -1409,7 +1620,7 @@ void halbtc8822b2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, break; case 8: halbtc8822b2ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xfafafafa, break_table, select_table); + 0xffff55ff, 0xfafafafa, break_table, select_table); break; case 9: halbtc8822b2ant_coex_table(btcoexist, force_exec, @@ -1419,6 +1630,22 @@ void halbtc8822b2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, halbtc8822b2ant_coex_table(btcoexist, force_exec, 0x55555555, 0x5a5a555a, break_table, select_table); break; + case 11: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0xaaffffaa, 0xfafafafa, break_table, select_table); + break; + case 12: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0xffff55ff, 0x5afa5afa, break_table, select_table); + break; + case 13: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0xffffffff, 0xfafafafa, break_table, select_table); + break; + case 14: + halbtc8822b2ant_coex_table(btcoexist, force_exec, + 0xffff55ff, 0xaaaaaaaa, break_table, select_table); + break; default: break; } @@ -1542,10 +1769,10 @@ boolean halbtc8822b2ant_power_save_state(IN struct btc_coexist *btcoexist, BTC_TRACE(trace_buf); low_pwr_disable = FALSE; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + /* btcoexist->btc_set(btcoexist, + over to original 32k low power setting */ + + btcoexist->btc_set(btcoexist, BTC_SET_ACT_PRE_NORMAL_LPS, NULL); break; case BTC_PS_LPS_ON: @@ -1596,6 +1823,7 @@ void halbtc8822b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, u8 real_byte1 = byte1, real_byte5 = byte5; boolean ap_enable = FALSE, result = FALSE; struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 ps_type = BTC_PS_WIFI_NATIVE; if (byte5 & BIT(2)) coex_sta->is_tdma_btautoslot = TRUE; @@ -1622,8 +1850,9 @@ void halbtc8822b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, real_byte5 |= BIT(5); real_byte5 &= ~BIT(6); + ps_type = BTC_PS_WIFI_NATIVE; halbtc8822b2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); + ps_type, 0x0, 0x0); } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], halbtc8822b2ant_set_fw_pstdma == Force LPS (byte1 = 0x%x)\n", byte1); @@ -1634,7 +1863,8 @@ void halbtc8822b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, btcoexist, BTC_PS_LPS_ON, 0x50, 0x4); #endif - if (!halbtc8822b2ant_power_save_state(btcoexist, BTC_PS_LPS_OFF, 0x50, 0x4)) + ps_type = BTC_PS_LPS_OFF; + if (!halbtc8822b2ant_power_save_state(btcoexist, ps_type, 0x50, 0x4)) result = TRUE; } else { @@ -1642,9 +1872,8 @@ void halbtc8822b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, "[BTCoex], halbtc8822b2ant_set_fw_pstdma == Native LPS (byte1 = 0x%x)\n", byte1); BTC_TRACE(trace_buf); - halbtc8822b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, - 0x0); + ps_type = BTC_PS_WIFI_NATIVE; + halbtc8822b2ant_power_save_state(btcoexist, ps_type, 0x0, 0x0); } @@ -1672,6 +1901,9 @@ void halbtc8822b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, coex_sta->cnt_set_ps_state_fail); BTC_TRACE(trace_buf); } + + if (ps_type == BTC_PS_WIFI_NATIVE) + btcoexist->btc_set(btcoexist, BTC_SET_ACT_POST_NORMAL_LPS, NULL); } @@ -1813,8 +2045,13 @@ void halbtc8822b2ant_ps_tdma(IN struct btc_coexist *btcoexist, break; case 23: halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x11, - 0x10); + 0x10, 0x03, 0x11, + 0x10); + break; + case 25: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51, + 0x3a, 0x3, 0x11, + 0x50); break; case 51: halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, @@ -1876,6 +2113,16 @@ void halbtc8822b2ant_ps_tdma(IN struct btc_coexist *btcoexist, 0x25, 0x03, 0x11, 0x11 | psTdmaByte4Modify); break; + case 113: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x48, 0x03, 0x11, + 0x10); + break; + case 119: + halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x14 | psTdmaByte4Modify); + break; case 151: halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51, 0x10, 0x03, 0x10, @@ -1885,9 +2132,6 @@ void halbtc8822b2ant_ps_tdma(IN struct btc_coexist *btcoexist, } else { /* disable PS tdma */ switch (type) { -#if 0 -/* 08:1ant:PTA Control -0x778=1-ant hw control,40:2ant:sw control-diversity */ -#endif case 0: halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x0, @@ -1912,14 +2156,10 @@ static void halbtc8822b2ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) { -#if 0 - struct btc_board_info *board_info = &btcoexist->board_info; -#endif + boolean switch_polatiry_inverse = FALSE; u8 regval_0xcbc = 0, regval_0x64; -#if BT_8822B_2ANT_COEX_DBG u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; -#endif if (!rfe_type->ext_ant_switch_exist) return; @@ -1933,30 +2173,12 @@ void halbtc8822b2ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, } coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status; -#if 0 - switch (pos_type) { - default: - case BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT: - case BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE: - break; - case BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG: - break; - case BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA: - break; - } -#endif - -#if 0 - if (board_info->ant_div_cfg) - ctrl_type = BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; -#endif /* Ext switch buffer mux */ btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); - switch (ctrl_type) { default: case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW: @@ -1969,7 +2191,7 @@ void halbtc8822b2ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, 0xff, 0x77); btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, - 0x03, 01); + 0x03, 0x1); break; case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: @@ -2034,18 +2256,17 @@ void halbtc8822b2ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, #if BT_8822B_2ANT_COEX_DBG - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcbc); u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c); u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (After Ext Ant switch setup) 0xcb4 = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n", + "[BTCoex], (After Ext Ant switch setup) 0xcbc = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n", u32tmp1, u32tmp2, u32tmp3); BTC_TRACE(trace_buf); #endif - } /* rf4 type by efuse, and for ant at main aux inverse use, @@ -2084,9 +2305,11 @@ void halbtc8822b2ant_set_rfe_type(IN struct btc_coexist *btcoexist) /* the following setup should be got from Efuse in the future */ rfe_type->rfe_module_type = board_info->rfe_type; - rfe_type->ext_ant_switch_ctrl_polarity = 0; + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT; +#if 0 switch (rfe_type->rfe_module_type) { case 0: default: @@ -2120,9 +2343,10 @@ void halbtc8822b2ant_set_rfe_type(IN struct btc_coexist *btcoexist) break; case 7: rfe_type->ext_ant_switch_exist = TRUE; -rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT; + rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT; break; } +#endif #if 0 @@ -2144,13 +2368,10 @@ void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist, IN u8 ant_pos_type, IN boolean force_exec, IN u8 phase) { -#if BT_8822B_2ANT_COEX_DBG + u8 u8tmp = 0; -#endif u32 u32tmp1 = 0; -#if BT_8822B_2ANT_COEX_DBG u32 u32tmp2 = 0, u32tmp3 = 0; -#endif u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); @@ -2161,14 +2382,7 @@ void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist, coex_sta->gnt_error_cnt++; } - /* Ext switch buffer mux */ - btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ + coex_sta->is_2g_freerun = ((phase == BT_8822B_2ANT_PHASE_2G_FREERUN) ? TRUE : FALSE); coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; @@ -2194,6 +2408,8 @@ void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist, BTC_TRACE(trace_buf); #endif + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff, 0x77); + switch (phase) { case BT_8822B_2ANT_PHASE_COEX_POWERON: @@ -2214,12 +2430,19 @@ void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist, coex_sta->run_time_state = FALSE; + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 2); + break; case BT_8822B_2ANT_PHASE_COEX_INIT: + /* Ext switch buffer mux */ + btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0); btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80, 0x0); /* 0x4c[23] = 0 */ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01, 0x1); /* 0x4c[24] = 1 */ + /* Disable LTE Coex Function in WiFi side * (this should be on if LTE coex is required) */ @@ -2257,6 +2480,8 @@ void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist, BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 2); + coex_sta->run_time_state = FALSE; break; @@ -2298,15 +2523,12 @@ void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist, BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); - coex_sta->run_time_state = FALSE; + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 2); + coex_sta->run_time_state = FALSE; break; case BT_8822B_2ANT_PHASE_WLAN_OFF: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x0); /* 0x4c[24] = 0 */ /* Disable LTE Coex Function in WiFi side */ halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0); @@ -2315,34 +2537,27 @@ void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist, btcoexist, BT_8822B_2ANT_PCO_BTSIDE); - /* Set Ext Ant Switch to BT control at wifi off step */ - halbtc8822b2ant_set_ext_ant_switch(btcoexist, - FORCE_EXEC, - BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT, - BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 1); + coex_sta->run_time_state = FALSE; break; case BT_8822B_2ANT_PHASE_2G_RUNTIME: - case BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT: + case BT_8822B_2ANT_PHASE_2G_FREERUN: /* set Path control owner to WL at runtime step */ halbtc8822b2ant_ltecoex_pathcontrol_owner( btcoexist, BT_8822B_2ANT_PCO_WLSIDE); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x66); + if (phase == - BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT) { - /* set GNT_BT to PTA */ - halbtc8822b2ant_ltecoex_set_gnt_bt( - btcoexist, + BT_8822B_2ANT_PHASE_2G_FREERUN) { + /* set GNT_BT to SW Hi */ + halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB, - BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8822B_2ANT_SIG_STA_SET_BY_HW); - - /* Set GNT_WL to SW High */ - halbtc8822b2ant_ltecoex_set_gnt_wl( - btcoexist, + BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW Hi */ + halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB, BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); @@ -2362,11 +2577,13 @@ void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist, BT_8822B_2ANT_SIG_STA_SET_BY_HW); } - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + coex_sta->run_time_state = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ************* under2g 0xcbd setting =2 *************\n"); BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 02); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 2); break; case BT_8822B_2ANT_PHASE_5G_RUNTIME: @@ -2386,14 +2603,14 @@ void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB, BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, BT_8822B_2ANT_SIG_STA_SET_TO_HIGH); + coex_sta->run_time_state = TRUE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ************* under5g 0xcbd setting =1 *************\n"); BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, - 0x03, 01); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 1); break; case BT_8822B_2ANT_PHASE_BTMPMODE: @@ -2417,6 +2634,8 @@ void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist, BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW, BT_8822B_2ANT_SIG_STA_SET_TO_LOW); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 1); + coex_sta->run_time_state = FALSE; break; } @@ -2436,105 +2655,6 @@ void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist, } -static -void halbtc8822b2ant_set_rx_gain(IN struct btc_coexist *btcoexist, - IN boolean agc_table_en) -{ - u8 rssi_adjust_val = 0; - - /* =================BB AGC Gain Table */ - if (agc_table_en) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table On!\n"); - BTC_TRACE(trace_buf); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - btcoexist->btc_write_1byte(btcoexist, 0xc5b, 0xc8); - btcoexist->btc_write_1byte(btcoexist, 0xe5b, 0xc8); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xff000003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xae2e0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xad300003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xac320003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xab360003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8d380003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8c3a0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8b3c0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x8a3e0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6e400003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6d420003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6c440003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6b460003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x6a480003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x694a0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x684c0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x674e0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x66500003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x65520003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x64540003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x64560003); - - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x007e0403); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BB Agc Table Off!\n"); - BTC_TRACE(trace_buf); - coex_dm->is_switch_to_1dot5_ant = TRUE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - btcoexist->btc_write_1byte(btcoexist, 0xc5b, 0xd8); - btcoexist->btc_write_1byte(btcoexist, 0xe5b, 0xd8); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xff000003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xe62e0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xe5300003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc8320003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc6360003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc5380003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc43a0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc33c0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc23e0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc1400003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xc0420003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa5440003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa4460003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa3480003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa24a0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0xa14c0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x834e0003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x82500003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x81520003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x80540003); - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x65560003); - - btcoexist->btc_write_4byte(btcoexist, 0x81c, 0x007e0403); - } - -} - - -static -void halbtc8822b2ant_rx_gain(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean agc_table_en) -{ - coex_dm->cur_agc_table_en = agc_table_en; - - if (!force_exec) { - if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en) - return; - } - halbtc8822b2ant_set_rx_gain(btcoexist, agc_table_en); - - coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en; -} - - static u8 halbtc8822b2ant_action_algorithm(IN struct btc_coexist *btcoexist) { @@ -2757,62 +2877,190 @@ u8 halbtc8822b2ant_action_algorithm(IN struct btc_coexist *btcoexist) return algorithm; } - static -void halbtc8822b2ant_action_coex_all_off(IN struct btc_coexist *btcoexist) +void halbtc8822b2ant_action_wifi_freerun(IN struct btc_coexist *btcoexist) { + boolean wifi_busy = FALSE; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 bt_rssi_state; - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ************* freerunXXXX*************\n"); + BTC_TRACE(trace_buf); -#if 0 - /*halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);*/ -#endif + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, 55, 0); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + if (!wifi_busy) + wifi_busy = coex_sta->gl_wifi_busy; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - /* fw all off */ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_2G_FREERUN); -} + halbtc8822b2ant_update_wifi_channel_info(btcoexist, BTC_MEDIA_CONNECT); -static -void halbtc8822b2ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) -{ + halbtc8822b2ant_post_state_to_bt(btcoexist, BT_8822B_2ANT_SCOREBOARD_BTCQDDR, TRUE); + + /*avoid tdma off to write 0xc5b ,0xe5b */ + if (wifi_busy) { + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, FORCE_EXEC, TRUE); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + + if (BTC_RSSI_HIGH(bt_rssi_state)) + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, FORCE_EXEC, 0xeb); + else + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, FORCE_EXEC, 0xf3); + + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd4); + } else { + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, FORCE_EXEC, TRUE); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, TRUE); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, FORCE_EXEC, 0x0); + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + } +} + + + +static +void halbtc8822b2ant_action_coex_all_off(IN struct btc_coexist *btcoexist) +{ + + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); +} + +static +void halbtc8822b2ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) +{ + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); - /* fw all off */ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ************* under5g *************\n"); - BTC_TRACE(trace_buf); - halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_2ANT_PHASE_5G_RUNTIME); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ +} + +static +void halbtc8822b2ant_action_bt_hs(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + +#if 1 + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; #endif + + wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8822b2ant_action_wifi_freerun(btcoexist); + } else { + + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } + } static -void halbtc8822b2ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist) +void halbtc8822b2ant_action_bt_relink(IN struct btc_coexist *btcoexist) { -#if 0 - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); -#endif - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + if (((!coex_sta->is_bt_multi_link) && (!bt_link_info->pan_exist)) || + ((bt_link_info->a2dp_exist) && (bt_link_info->hid_exist))) { + + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } } +static +void halbtc8822b2ant_action_bt_idle(IN struct btc_coexist *btcoexist) +{ + + boolean wifi_busy = FALSE; + + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_busy) { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 14); + } else { /* if wl busy */ + if ((coex_sta->bt_ble_scan_type & 0x2) && + (BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status)) {/* for A2DP + RCU off (initiator scan on) */ + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 12); + } else { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 12); + } + } +} static void halbtc8822b2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) @@ -2825,14 +3073,17 @@ void halbtc8822b2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { @@ -2840,15 +3091,12 @@ void halbtc8822b2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 8); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 15); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 15); else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 11); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 11); } else if ((!wifi_connected) && (!wifi_scan)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -2865,137 +3113,24 @@ void halbtc8822b2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) } else if (bt_link_info->a2dp_exist) { -#if 0 - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16); - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); -#endif halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 10); halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8); } else { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task)) halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); else halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 23); - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - } - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif -} - -static -void halbtc8822b2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd4); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - if (bt_link_info->pan_exist) { - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); - - } else if (bt_link_info->a2dp_exist) { - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16); - - } else { - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); - } } -static -void halbtc8822b2ant_action_wifi_nonconnected(IN struct btc_coexist *btcoexist) -{ - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -#if 0 - /*halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);*/ -#endif - - /* fw all off */ - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif -} - -static -void halbtc8822b2ant_action_bt_relink(IN struct btc_coexist *btcoexist) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], run bt multi link function\n"); - BTC_TRACE(trace_buf); - - if (coex_sta->is_bt_multi_link) - return; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], run bt re-link function\n"); - BTC_TRACE(trace_buf); - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - -} - -static -void halbtc8822b2ant_action_bt_idle(IN struct btc_coexist *btcoexist) -{ - - boolean wifi_busy = FALSE; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_busy) { - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 14); - } else { /* if wl busy */ - - if (BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, - 0); - } else { - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 8); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 12); - } - } - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif -} /* SCO only or SCO+PAN(HS) */ static @@ -3036,33 +3171,27 @@ void halbtc8822b2ant_action_sco(IN struct btc_coexist *btcoexist) if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - /*halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);*/ - halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_2ANT_PHASE_5G_RUNTIME); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b2ant_action_wifi_freerun(btcoexist); } else { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); coex_dm->is_switch_to_1dot5_ant = FALSE; - if (coex_sta->is_eSCO_mode) - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - else /* 2-Ant free run if SCO mode */ - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + if (coex_sta->is_bt_multi_link) { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 25); + } else { + if (coex_sta->is_eSCO_mode) + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + else /* 2-Ant free run if SCO mode */ + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8); + } } } @@ -3105,43 +3234,35 @@ void halbtc8822b2ant_action_hid(IN struct btc_coexist *btcoexist) if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - /*halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);*/ - halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_2ANT_PHASE_5G_RUNTIME); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8822b2ant_action_wifi_freerun(btcoexist); } else { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); coex_dm->is_switch_to_1dot5_ant = FALSE; if (coex_sta->is_hid_low_pri_tx_overhead) { - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 108); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 108); + } else if (coex_sta->is_hid_rcu) { + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 12); + + if (wifi_busy) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 113); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 111); } else if (wifi_bw == 0) { /* if 11bg mode */ - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 111); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 111); } else { - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 111); } @@ -3161,13 +3282,13 @@ void halbtc8822b2ant_action_a2dpsink(IN struct btc_coexist *btcoexist) static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; u8 wifi_rssi_state2, bt_rssi_state2; boolean wifi_busy = FALSE, wifi_turbo = FALSE; -#if 0 - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); -#endif + boolean ap_enable = FALSE; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", coex_sta->scan_ap_num, coex_sta->wl_noisy_level); @@ -3195,43 +3316,15 @@ void halbtc8822b2ant_action_a2dpsink(IN struct btc_coexist *btcoexist) coex_sta->bt_coex_thres2, 0); - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - /*halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);*/ - halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_2ANT_PHASE_5G_RUNTIME); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + if (BTC_RSSI_HIGH(wifi_rssi_state) ||ap_enable) { - if (wifi_busy) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 1); - else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 16); + halbtc8822b2ant_action_wifi_freerun(btcoexist); } else { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); coex_dm->is_switch_to_1dot5_ant = TRUE; @@ -3242,17 +3335,15 @@ void halbtc8822b2ant_action_a2dpsink(IN struct btc_coexist *btcoexist) "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); } else { halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 105); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 105); } } - } /* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ @@ -3277,7 +3368,6 @@ void halbtc8822b2ant_action_a2dp(IN struct btc_coexist *btcoexist) coex_sta->scan_ap_num, coex_sta->wl_noisy_level); BTC_TRACE(trace_buf); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) wifi_turbo = TRUE; @@ -3288,7 +3378,7 @@ void halbtc8822b2ant_action_a2dp(IN struct btc_coexist *btcoexist) wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); + 45, 0); bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, &pre_bt_rssi_state, 2, @@ -3298,43 +3388,15 @@ void halbtc8822b2ant_action_a2dp(IN struct btc_coexist *btcoexist) &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0); - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - /*halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);*/ - halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_2ANT_PHASE_5G_RUNTIME); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + if (BTC_RSSI_HIGH(wifi_rssi_state)) { - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 1); - else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 16); + halbtc8822b2ant_action_wifi_freerun(btcoexist); } else { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); coex_dm->is_switch_to_1dot5_ant = TRUE; @@ -3345,30 +3407,19 @@ void halbtc8822b2ant_action_a2dp(IN struct btc_coexist *btcoexist) "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); } else { - if (wifi_turbo) - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 10); - else - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 10); -#if 0 -halbtc8822b2ant_coex_table_with_type(btcoexist, -NORMAL_EXEC, -7); -#endif + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 109); + if (BTC_RSSI_HIGH(wifi_rssi_state2)) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 119); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 109); } - } - } @@ -3414,66 +3465,28 @@ void halbtc8822b2ant_action_pan_edr(IN struct btc_coexist *btcoexist) &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0); -#if 0 - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); -#endif - -#if 1 if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 3); - else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 4); + halbtc8822b2ant_action_wifi_freerun(btcoexist); } else { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); coex_dm->is_switch_to_1dot5_ant = TRUE; - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); if (wifi_busy) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 103); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 103); else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 104); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 104); } -#endif - } static @@ -3501,7 +3514,7 @@ void halbtc8822b2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); + 45, 0); bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, &pre_bt_rssi_state, 2, @@ -3512,42 +3525,15 @@ void halbtc8822b2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) coex_sta->bt_coex_thres2, 0); - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - /*halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = FALSE; + if (BTC_RSSI_HIGH(wifi_rssi_state)) { - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);*/ - halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_2ANT_PHASE_5G_RUNTIME); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 1); - else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 16); + halbtc8822b2ant_action_wifi_freerun(btcoexist); } else { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); coex_dm->is_switch_to_1dot5_ant = TRUE; @@ -3561,10 +3547,13 @@ void halbtc8822b2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); } else { - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 109); + + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 12); + + if (BTC_RSSI_HIGH(wifi_rssi_state2)) + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 119); + else + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 109); } } @@ -3617,64 +3606,30 @@ void halbtc8822b2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);*/ - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) { - - if ((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 7); - else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 5); - } else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 6); - + halbtc8822b2ant_action_wifi_freerun(btcoexist); } else { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); coex_dm->is_switch_to_1dot5_ant = TRUE; if (wifi_turbo) - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6); else - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 7); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); if (wifi_busy) { if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255)) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 107); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 107); else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 105); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 105); } else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 106); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 106); } @@ -3727,52 +3682,21 @@ void halbtc8822b2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) { - - if (((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) || - (!coex_sta->is_A2DP_3M)) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 7); - else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 5); - } else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 6); - } else { + halbtc8822b2ant_action_wifi_freerun(btcoexist); + } else { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); coex_dm->is_switch_to_1dot5_ant = TRUE; - halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 8); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); if (wifi_busy) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 107); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 107); else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 106); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 106); } } @@ -3816,44 +3740,22 @@ void halbtc8822b2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 3); - else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 4); + halbtc8822b2ant_action_wifi_freerun(btcoexist); } else { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); coex_dm->is_switch_to_1dot5_ant = TRUE; - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 12); if (wifi_busy) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 103); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 103); else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 104); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 104); } } @@ -3898,52 +3800,19 @@ void halbtc8822b2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - - if (wifi_busy) { - - if (((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) || - (!coex_sta->is_A2DP_3M)) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 7); - else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 5); - } else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 6); - } else { + halbtc8822b2ant_action_wifi_freerun(btcoexist); + } else { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); coex_dm->is_switch_to_1dot5_ant = TRUE; if (coex_sta->hid_busy_num >= 2) { halbtc8822b2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); + NORMAL_EXEC, 12); if (wifi_bw == 0) { halbtc8822b2ant_set_wltoggle_coex_table( @@ -3961,8 +3830,7 @@ void halbtc8822b2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) 0x5a, 0xaa, 0xaa); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 110); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 110); } else { halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); @@ -3970,146 +3838,119 @@ void halbtc8822b2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255)) - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 107); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 107); else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 105); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 105); } else - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 106); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 106); } } } static -void halbtc8822b2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist) -{ - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif - - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -#if 0 - /*halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);*/ -#endif - - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); -} - -static -void halbtc8822b2ant_action_bt_hs(IN struct btc_coexist *btcoexist) +void halbtc8822b2ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) { - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = FALSE, wifi_turbo = FALSE; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); + /* fw all off */ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + "[BTCoex], ************* under5g *************\n"); BTC_TRACE(trace_buf); -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = TRUE; -#endif - + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); - wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres, 0); - - wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); - - bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres, 0); - - bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2, 0); + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8822B_2ANT_PHASE_5G_RUNTIME); - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif +} - coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +static +void halbtc8822b2ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist) +{ + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif +} - coex_dm->is_switch_to_1dot5_ant = FALSE; +static +void halbtc8822b2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + if (bt_link_info->pan_exist) { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); - } else { + } else if (bt_link_info->a2dp_exist) { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16); - coex_dm->is_switch_to_1dot5_ant = TRUE; + } else { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); } } static -void halbtc8822b2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +void halbtc8822b2ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) { - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif + halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0); + halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE); + halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE); - /* hw all off */ - /*halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);*/ - halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8822B_2ANT_PHASE_5G_RUNTIME); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, TRUE); halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); +} -#if 0 - /*halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);*/ -#endif - /*halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);*/ +static +void halbtc8822b2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist, + IN u8 multi_port_type) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean miracast_plus_bt = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],action_wifi_multi_port\n"); + BTC_TRACE(trace_buf); + + if (bt_link_info->bt_link_exist) + miracast_plus_bt = TRUE; + else + miracast_plus_bt = FALSE; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + if (multi_port_type == BTC_MULTIPORT_MCC_DUAL_BAND) { + halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13); + halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else { + halbtc8822b2ant_action_wifi_freerun(btcoexist); + } } static @@ -4188,7 +4029,6 @@ void halbtc8822b2ant_action_wifi_connected(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); halbtc8822b2ant_action_coex_all_off(btcoexist); break; } @@ -4200,16 +4040,14 @@ void halbtc8822b2ant_action_wifi_connected(IN struct btc_coexist *btcoexist) static void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) { - u8 algorithm = 0; + u8 algorithm = 0, mcc_dualband = BTC_MULTIPORT_SCC; u32 num_of_wifi_link = 0; u32 wifi_link_status = 0; struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean miracast_plus_bt = FALSE; - boolean scan = FALSE, link = FALSE, roam = FALSE, - under_4way = FALSE, - wifi_connected = FALSE, wifi_under_5g = - FALSE, - bt_hs_on = FALSE; + boolean scan = FALSE, link = FALSE, roam = FALSE, + under_4way = FALSE, wifi_connected = FALSE, + wifi_under_5g = FALSE, bt_hs_on = FALSE; + u8 wifi_central_chnl = 0; btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); @@ -4217,6 +4055,10 @@ void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way); + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + coex_sta->wl_center_channel = wifi_central_chnl; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RunCoexistMechanism()===>\n"); BTC_TRACE(trace_buf); @@ -4242,31 +4084,33 @@ void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) return; } - if ((coex_sta->under_lps) && - (coex_dm->bt_status != BT_8822B_2ANT_BT_STATUS_ACL_BUSY)) { + if (!coex_sta->run_time_state) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n"); + "[BTCoex], return for run_time_state = FALSE !!!\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_action_wifi_native_lps(btcoexist); return; } - if (!coex_sta->run_time_state) { + if (coex_sta->freeze_coexrun_by_btinfo) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], return for run_time_state = FALSE !!!\n"); + "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); BTC_TRACE(trace_buf); return; } - if (coex_sta->freeze_coexrun_by_btinfo) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED, &mcc_dualband); + if (mcc_dualband == BTC_MULTIPORT_MCC_DUAL_BAND) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); + "[BTCoex], RunCoexistMechanism(), mcc dual band!!\n"); BTC_TRACE(trace_buf); + + halbtc8822b2ant_action_wifi_multi_port(btcoexist, BTC_MULTIPORT_MCC_DUAL_BAND); return; } btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if ((wifi_under_5g) && (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G) && (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G_NOFORSCAN)) { @@ -4274,25 +4118,37 @@ void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], WiFi is under 5G!!!\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); halbtc8822b2ant_action_wifi_under5g(btcoexist); return; - } + } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 2G!!!\n"); - BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 2G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME); + } - halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8822B_2ANT_PHASE_2G_RUNTIME); +halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_BTCQDDR, + TRUE); + if ((coex_sta->under_lps) && (!coex_sta->force_lps_ctrl) && + (!coex_sta->acl_busy)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n"); + BTC_TRACE(trace_buf); + halbtc8822b2ant_action_wifi_native_lps(btcoexist); + return; + } if (coex_sta->bt_whck_test) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BT is under WHCK TEST!!!\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_action_bt_whck_test(btcoexist); + halbtc8822b2ant_action_bt_whql_test(btcoexist); return; } @@ -4300,7 +4156,6 @@ void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BT is disabled!!!\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); halbtc8822b2ant_action_coex_all_off(btcoexist); return; } @@ -4309,16 +4164,14 @@ void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BT is under inquiry/page scan !!\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); halbtc8822b2ant_action_bt_inquiry(btcoexist); return; } - if (coex_sta->is_setupLink) { + if ((coex_sta->is_setupLink) && (!coex_sta->is_2g_freerun)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BT is re-link !!!\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); halbtc8822b2ant_action_bt_relink(btcoexist); return; } @@ -4335,14 +4188,6 @@ void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) num_of_wifi_link, wifi_link_status); BTC_TRACE(trace_buf); - if (bt_link_info->bt_link_exist) - miracast_plus_bt = TRUE; - else - miracast_plus_bt = FALSE; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - if (scan || link || roam || under_4way) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", @@ -4355,33 +4200,16 @@ void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) halbtc8822b2ant_action_wifi_link_process(btcoexist); } else { - halbtc8822b2ant_action_wifi_multi_port(btcoexist); + halbtc8822b2ant_action_wifi_multi_port(btcoexist, mcc_dualband); } return; } - miracast_plus_bt = FALSE; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is hs\n"); - BTC_TRACE(trace_buf); - halbtc8822b2ant_action_bt_hs(btcoexist); - return; - } - if ((BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == coex_dm->bt_status) || (BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) { - halbtc8822b2ant_rx_gain(btcoexist, NORMAL_EXEC, FALSE); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action 2-Ant, bt idle!!.\n"); @@ -4397,8 +4225,7 @@ void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) coex_dm->cur_algorithm); BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); if (scan || link || roam || under_4way) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -4417,7 +4244,7 @@ void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action 2-Ant, wifi not-connected!!.\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_action_wifi_nonconnected(btcoexist); + halbtc8822b2ant_action_wifi_not_connected(btcoexist); } } @@ -4430,20 +4257,6 @@ void halbtc8822b2ant_init_coex_dm(IN struct btc_coexist *btcoexist) halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); - halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); -#if 0 - /*halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);*/ -#endif - - /* fw all off */ - halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - - halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); -#if 0 - /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/ -#endif - coex_sta->pop_event_cnt = 0; coex_sta->cnt_RemoteNameReq = 0; coex_sta->cnt_ReInit = 0; @@ -4519,11 +4332,19 @@ void halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist, coex_sta->dis_ver_info_cnt = 0; + if ((rfe_type->rfe_module_type == 2) || + (rfe_type->rfe_module_type == 4)) + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_EXTFEM, TRUE); + else + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_EXTFEM, FALSE); + halbtc8822b2ant_coex_switch_threshold(btcoexist, coex_sta->isolation_btween_wb); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ + /* enable TBTT nterrupt */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, 0x1); /* BT report packet sample rate */ btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); @@ -4544,27 +4365,13 @@ void halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist, btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1); - /* check if WL firmware download ok */ -#if 0 - if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6) -#endif - halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ONOFF, TRUE); - - /* Enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, - 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ - -#if 0 - /* WLAN_Tx by GNT_WL 0x950[29] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0); -#endif + /* Enable counter statistics */ /* 0x76e[3] =1, WLAN_Act control by PTA */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); halbtc8822b2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 5); halbtc8822b2ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); - psd_scan->ant_det_is_ant_det_available = TRUE; if (coex_sta->is_rf_state_off) { @@ -4593,13 +4400,7 @@ void halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist, btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); coex_sta->concurrent_rx_mode_on = TRUE; -#if 0 - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); -#endif - /* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 for - * con-current Rx, mask Tx only - */ btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0); /* Set Antenna Path */ @@ -4637,6 +4438,7 @@ void ex_halbtc8822b2ant_power_on_setting(IN struct btc_coexist *btcoexist) btcoexist->stop_coex_dm = TRUE; + coex_sta->is_rf_state_off = FALSE; psd_scan->ant_det_is_ant_det_available = FALSE; /* enable BB, REG_SYS_FUNC_EN such that we can write BB Reg correctly */ @@ -4704,9 +4506,9 @@ void ex_halbtc8822b2ant_power_on_setting(IN struct btc_coexist *btcoexist) BTC_TRACE(trace_buf); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcb4 (Power-On) = 0x%x / 0x%x\n", + "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcbc (Power-On) = 0x%x / 0x%x\n", btcoexist->btc_read_4byte(btcoexist, 0x70), - btcoexist->btc_read_4byte(btcoexist, 0xcb4)); + btcoexist->btc_read_4byte(btcoexist, 0xcbc)); BTC_TRACE(trace_buf); } @@ -4757,9 +4559,151 @@ void ex_halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist, void ex_halbtc8822b2ant_init_coex_dm(IN struct btc_coexist *btcoexist) { - halbtc8822b2ant_init_coex_dm(btcoexist); + halbtc8822b2ant_init_coex_dm(btcoexist); +} + + +void ex_halbtc8822b2ant_display_simple_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + u8 *cli_buf = btcoexist->cli_buf; + u32 bt_patch_ver = 0, bt_coex_ver = 0; + static u8 cnt = 0; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n _____[BT Coexist info]____"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n __[Under Manual Control]_"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n _________________________"); + CL_PRINTF(cli_buf); + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->bt_coex_supported_feature == 0) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + if (coex_sta->bt_reg_vendor_ac == 0xffff) + coex_sta->bt_reg_vendor_ac = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xac) & 0xffff); + + if (coex_sta->bt_reg_vendor_ae == 0xffff) + coex_sta->bt_reg_vendor_ae = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xae) & 0xffff); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, + &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) { + cnt++; + + if (cnt >= 3) { + btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, + &coex_sta->bt_afh_map[0]); + cnt = 0; + } + } + } + + // BT coex. info. + if (psd_scan->ant_det_try_count == 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s / %d", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, board_info->btdm_ant_num, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type); + CL_PRINTF(cli_buf); + } else { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", + "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", + board_info->pg_ant_num, + board_info->btdm_ant_num_by_ant_det, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type, + psd_scan->ant_det_try_count, + psd_scan->ant_det_fail_count, + psd_scan->ant_det_result); + CL_PRINTF(cli_buf); + + + if (board_info->btdm_ant_det_finish) { + + if (psd_scan->ant_det_result != 12) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", + "Ant Det PSD Value", + psd_scan->ant_det_peak_val); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d", + "Ant Det PSD Value", + psd_scan->ant_det_psd_scan_peak_val + / 100); + CL_PRINTF(cli_buf); + } + } + + bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8822b_2ant, glcoex_ver_8822b_2ant, + glcoex_ver_btdesired_8822b_2ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8822b_2ant ? + "Match" : "Mis-Match")))); + CL_PRINTF(cli_buf); + + // BT status + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", + "BT status", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + : ((BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE) + ? "connected-idle" : "busy"))))); + CL_PRINTF(cli_buf); + + // HW Settings + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : ( + coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); + CL_PRINTF(cli_buf); + } + void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) { struct btc_board_info *board_info = &btcoexist->board_info; @@ -4792,7 +4736,7 @@ void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) if (!coex_sta->bt_disabled) { if (coex_sta->bt_coex_supported_feature == 0) btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, - &coex_sta->bt_coex_supported_feature); + &coex_sta->bt_coex_supported_feature); if ((coex_sta->bt_coex_supported_version == 0) || (coex_sta->bt_coex_supported_version == 0xffff)) @@ -4824,47 +4768,14 @@ void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) } } - if (psd_scan->ant_det_try_count == 0) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %s / %d", - "Ant PG Num/ Mech/ Pos/ RFE", - board_info->pg_ant_num, board_info->btdm_ant_num, - (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT - ? "Main" : "Aux"), - rfe_type->rfe_module_type); - CL_PRINTF(cli_buf); - } else { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", - board_info->pg_ant_num, - board_info->btdm_ant_num_by_ant_det, - (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT - ? "Main" : "Aux"), - rfe_type->rfe_module_type, - psd_scan->ant_det_try_count, - psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); - CL_PRINTF(cli_buf); - - - if (board_info->btdm_ant_det_finish) { - - if (psd_scan->ant_det_result != 12) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d", - "Ant Det PSD Value", - psd_scan->ant_det_psd_scan_peak_val - / 100); - CL_PRINTF(cli_buf); - } - } - + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s / %d", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, board_info->btdm_ant_num, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type); + CL_PRINTF(cli_buf); bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); @@ -4891,10 +4802,10 @@ void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_sta->cut_version + 65); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x (RF-Ch = %d)", "AFH Map to BT", coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); + coex_dm->wifi_chnl_info[2], coex_sta->wl_center_channel); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ", @@ -4916,12 +4827,12 @@ void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) pop_report_in_10s++; CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", + "\r\n %-35s = %s/ %ddBm/ %d/ %d", + "BT status/ rssi/ retryCnt/ popCnt", ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + coex_sta->c2h_bt_inquiry_page) ? ("inquiry-page") : ((BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : + coex_dm->bt_status) ? "non-connected-idle" : ((coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE) ? "connected-idle" : "busy")))), coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, @@ -4936,17 +4847,20 @@ void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) if (coex_sta->num_of_profile != 0) CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s%s%s%s%s", - "Profiles", - ((bt_link_info->a2dp_exist) ? - ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," : - "A2DP,") : ""), - ((bt_link_info->sco_exist) ? "HFP," : ""), - ((bt_link_info->hid_exist) ? - ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : - "HID(2/18),") : ""), - ((bt_link_info->pan_exist) ? "PAN," : ""), - ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + "\r\n %-35s = %s%s%s%s%s (multilink = %d)", + "Profiles", + ((bt_link_info->a2dp_exist) ? + ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," : + "A2DP,") : ""), + ((bt_link_info->sco_exist) ? "HFP," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->is_hid_rcu) ? "HID(RCU)" : + ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : + "HID(2/18),")) : ""), + ((bt_link_info->pan_exist) ? + ((coex_sta->is_bt_opp_exist) ? "OPP," : "PAN,") : ""), + ((coex_sta->voice_over_HOGP) ? "Voice" : ""), + coex_sta->is_bt_multi_link); else CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = None", "Profiles"); @@ -4962,13 +4876,21 @@ void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) ((coex_sta->is_autoslot) ? "On" : "Off") ); CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %d/ %d", + "V_ID/D_name/FBSlot_Legacy/FBSlot_Le", + coex_sta->bt_a2dp_vendor_id, + coex_sta->bt_a2dp_device_name, + coex_sta->legacy_forbidden_slot, + coex_sta->le_forbidden_slot + ); + CL_PRINTF(cli_buf); } if (bt_link_info->hid_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "HID PairNum/Forbid_Slot", - coex_sta->hid_pair_cnt, - coex_sta->forbidden_slot + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "HID PairNum", + coex_sta->hid_pair_cnt ); CL_PRINTF(cli_buf); } @@ -4981,7 +4903,7 @@ void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_sta->bt_coex_supported_feature); CL_PRINTF(cli_buf); - if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { + if (coex_sta->is_ble_scan_en) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "BLEScan Type/TV/Init/Ble", @@ -5009,19 +4931,19 @@ void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) if ((coex_sta->bt_reg_vendor_ae == 0xffff) || (coex_sta->bt_reg_vendor_ac == 0xffff)) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ 0x%04x", + "0xae[4]/0xac[1:0]/Scoreboard(B->W)", u16tmp[0]); else CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", + "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x", + "0xae[4]/0xac[1:0]/Scoreboard(B->W)", (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); CL_PRINTF(cli_buf); if (coex_sta->num_of_profile > 0) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + "\r\n %-35s = %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x", "AFH MAP", coex_sta->bt_afh_map[0], coex_sta->bt_afh_map[1], @@ -5089,21 +5011,31 @@ void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x", - "0x778/0x6cc", - u8tmp[0], u32tmp[0]); + "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x", + "0x778/0x6cc/Scoreboard(W->B)", + u8tmp[0], u32tmp[0], coex_sta->score_board_WB); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "AntDiv/BtCtrlLPS/LPRA/PsFail", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d/ %d", + "AntDiv/BtCtrlLPS/LPRA/PsFail/g_busy", ((board_info->ant_div_cfg) ? "On" : "Off"), ((coex_sta->force_lps_ctrl) ? "On" : "Off"), ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"), - coex_sta->cnt_set_ps_state_fail); + coex_sta->cnt_set_ps_state_fail, + coex_sta->gl_wifi_busy); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "Null All/Retry/Ack/BT_Empty/BT_Late", + coex_sta->wl_fw_dbg_info[1], + coex_sta->wl_fw_dbg_info[2], + coex_sta->wl_fw_dbg_info[3], + coex_sta->wl_fw_dbg_info[4], + coex_sta->wl_fw_dbg_info[5]); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "WL_DACSwing/ BT_Dec_Pwr", coex_dm->cur_fw_dac_swing_lvl, + "WL_Pwr/ BT_Pwr", coex_dm->cur_fw_dac_swing_lvl, coex_dm->cur_bt_dec_pwr_lvl); CL_PRINTF(cli_buf); @@ -5171,7 +5103,7 @@ void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) CL_PRINTF(cli_buf); } CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s (gnt_err = %d)", "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), @@ -5188,15 +5120,17 @@ void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) CL_PRINTF(cli_buf); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcbc); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0); u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcbd); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc58); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s", - "0xcbc/0xcb4/0xcb8[23:16]", - u32tmp[0], u32tmp[1], u8tmp[0], - ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); + "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x/ 0x%02x 0x%02x %s", + "0xcb0/0xcb4/0xcb8[23:16]/0xcbd/0xc58", + u32tmp[0], u32tmp[1], u8tmp[0], u8tmp[1], u8tmp[2], + ((u8tmp[1] & 0x1) == 0x1 ? "(BT_WL5G)" : "(WL2G)")); CL_PRINTF(cli_buf); u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); @@ -5232,36 +5166,31 @@ void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist) cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK); - ratio_ofdm = (fa_ofdm == 0) ? 1000 : (cca_ofdm/fa_ofdm); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x (%d)", + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm, - ratio_ofdm); + cca_cck, fa_cck, cca_ofdm, fa_ofdm); CL_PRINTF(cli_buf); -#if 1 - - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d (Rx_rate Data/RTS= %d/%d)", "CRC_OK CCK/11g/11n/11ac", coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, - coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht, + coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d (%d, %d)", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_Err CCK/11g/11n/11ac", coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht, - coex_sta->now_crc_ratio, coex_sta->acc_crc_ratio); + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); CL_PRINTF(cli_buf); -#endif - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "WlHiPri/ Locking/ Locked/ Noisy", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %s/ %d", + "HiPr/ Locking/ warn/ Locked/ Noisy", (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No"), + (coex_sta->cck_lock_warn ? "Yes" : "No"), + (coex_sta->cck_lock_ever ? "Yes" : "No"), coex_sta->wl_noisy_level); CL_PRINTF(cli_buf); @@ -5294,10 +5223,12 @@ void ex_halbtc8822b2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) coex_sta->under_lps = FALSE; halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE); - - halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ONOFF, FALSE); + BT_8822B_2ANT_SCOREBOARD_ACTIVE | + BT_8822B_2ANT_SCOREBOARD_ONOFF | + BT_8822B_2ANT_SCOREBOARD_SCAN | + BT_8822B_2ANT_SCOREBOARD_UNDERTEST | + BT_8822B_2ANT_SCOREBOARD_RXGAIN, + FALSE); halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, @@ -5310,10 +5241,6 @@ void ex_halbtc8822b2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) BTC_TRACE(trace_buf); coex_sta->under_ips = FALSE; - halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); - halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ONOFF, TRUE); halbtc8822b2ant_init_hw_config(btcoexist, FALSE); halbtc8822b2ant_init_coex_dm(btcoexist); halbtc8822b2ant_query_bt_info(btcoexist); @@ -5340,16 +5267,14 @@ void ex_halbtc8822b2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) /* Write WL "Active" in Score-board for PS-TDMA */ pre_force_lps_on = TRUE; halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); + BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); } else { - /* LPS-32K, need check if this h2c 0x71 can work?? - * (2015/08/28) - */ /* Write WL "Non-Active" in Score-board for Native-PS */ pre_force_lps_on = FALSE; halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE); + BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE); + halbtc8822b2ant_action_wifi_native_lps(btcoexist); } } else if (BTC_LPS_DISABLE == type) { @@ -5369,94 +5294,77 @@ void ex_halbtc8822b2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) void ex_halbtc8822b2ant_scan_notify(IN struct btc_coexist *btcoexist, IN u8 type) { - boolean wifi_connected = FALSE; + boolean wifi_connected = FALSE; boolean wifi_under_5g = FALSE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN notify()\n"); + "[BTCoex], SCAN notify()\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + btcoexist->stop_coex_dm) return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* this can't be removed for RF off_on event, or BT would dis-connect */ - halbtc8822b2ant_query_bt_info(btcoexist); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); - if (BTC_SCAN_START == type) { + /* this can't be removed for RF off_on event, or BT would dis-connect */ + if ((type == BTC_SCAN_START) || (type == BTC_SCAN_START_2G)) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, - &wifi_under_5g); + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE | + BT_8822B_2ANT_SCOREBOARD_SCAN | + BT_8822B_2ANT_SCOREBOARD_ONOFF, + TRUE); - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** SCAN START notify (5g)\n"); - BTC_TRACE(trace_buf); + halbtc8822b2ant_query_bt_info(btcoexist); + } - halbtc8822b2ant_action_wifi_under5g(btcoexist); - return; - } + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - coex_sta->wifi_is_high_pri_task = TRUE; + if ((type == BTC_SCAN_START) && (wifi_under_5g)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** SCAN START notify (2g)\n"); + "[BTCoex], SCAN START notify (5G)\n"); BTC_TRACE(trace_buf); + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_5G_RUNTIME); - halbtc8822b2ant_run_coexist_mechanism( - btcoexist); - - return; - } - - - if (BTC_SCAN_START_2G == type) { - - if (!wifi_connected) - coex_sta->wifi_is_high_pri_task = TRUE; + halbtc8822b2ant_run_coexist_mechanism(btcoexist); + } else if ((type == BTC_SCAN_START_2G) || (type == BTC_SCAN_START)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify (2G)\n"); + "[BTCoex], SCAN START notify (2G)\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_SCAN, TRUE); - halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); + if (!wifi_connected) + coex_sta->wifi_is_high_pri_task = TRUE; halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8822B_2ANT_PHASE_2G_RUNTIME); + FORCE_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME); halbtc8822b2ant_run_coexist_mechanism(btcoexist); } else if (BTC_SCAN_FINISH == type) { - coex_sta->wifi_is_high_pri_task = FALSE; - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", - coex_sta->scan_ap_num); + "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", + coex_sta->scan_ap_num); BTC_TRACE(trace_buf); - halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_SCAN, FALSE); + coex_sta->wifi_is_high_pri_task = FALSE; halbtc8822b2ant_run_coexist_mechanism(btcoexist); } } + void ex_halbtc8822b2ant_switchband_notify(IN struct btc_coexist *btcoexist, IN u8 type) { @@ -5471,11 +5379,11 @@ void ex_halbtc8822b2ant_switchband_notify(IN struct btc_coexist *btcoexist, "[BTCoex], switchband_notify --- switch to 5G\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_action_wifi_under5g(btcoexist); + halbtc8822b2ant_run_coexist_mechanism(btcoexist); } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** switchband_notify BTC_SWITCH_TO_2G (no for scan)\n"); + "[BTCoex], ********** switchband_notify --- BTC_SWITCH_TO_2G (no for scan)\n"); BTC_TRACE(trace_buf); halbtc8822b2ant_run_coexist_mechanism(btcoexist); @@ -5497,12 +5405,16 @@ void ex_halbtc8822b2ant_connect_notify(IN struct btc_coexist *btcoexist, IN u8 type) { - halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); if (btcoexist->manual_control || btcoexist->stop_coex_dm) return; + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_ACTIVE | + BT_8822B_2ANT_SCOREBOARD_SCAN | + BT_8822B_2ANT_SCOREBOARD_ONOFF, + TRUE); + if ((BTC_ASSOCIATE_5G_START == type) || (BTC_ASSOCIATE_5G_FINISH == type)) { @@ -5515,12 +5427,12 @@ void ex_halbtc8822b2ant_connect_notify(IN struct btc_coexist *btcoexist, BTC_TRACE(trace_buf); - halbtc8822b2ant_action_wifi_under5g(btcoexist); - return; - } - + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_5G_RUNTIME); - if (BTC_ASSOCIATE_START == type) { + halbtc8822b2ant_run_coexist_mechanism(btcoexist); + } else if (type == BTC_ASSOCIATE_START) { coex_sta->wifi_is_high_pri_task = TRUE; @@ -5532,7 +5444,7 @@ void ex_halbtc8822b2ant_connect_notify(IN struct btc_coexist *btcoexist, FORCE_EXEC, BT_8822B_2ANT_PHASE_2G_RUNTIME); - halbtc8822b2ant_action_wifi_link_process(btcoexist); + halbtc8822b2ant_run_coexist_mechanism(btcoexist); /* To keep TDMA case during connect process, * to avoid changed by Btinfo and runcoexmechanism @@ -5547,7 +5459,7 @@ void ex_halbtc8822b2ant_connect_notify(IN struct btc_coexist *btcoexist, coex_sta->freeze_coexrun_by_btinfo = FALSE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify (2G)\n"); + "[BTCoex], CONNECT FINISH notify (2G)\n"); BTC_TRACE(trace_buf); halbtc8822b2ant_run_coexist_mechanism(btcoexist); @@ -5566,7 +5478,7 @@ void ex_halbtc8822b2ant_media_status_notify(IN struct btc_coexist *btcoexist, btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - if (BTC_MEDIA_CONNECT == type) { + if (type == BTC_MEDIA_CONNECT) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], MEDIA connect notify\n"); @@ -5581,31 +5493,32 @@ void ex_halbtc8822b2ant_media_status_notify(IN struct btc_coexist *btcoexist, "[BTCoex], WiFi is under 5G!!!\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_action_wifi_under5g(btcoexist); - return; - } + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_5G_RUNTIME); - halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8822B_2ANT_PHASE_2G_RUNTIME); + halbtc8822b2ant_run_coexist_mechanism(btcoexist); + } else { + + halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8822B_2ANT_PHASE_2G_RUNTIME); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x00); /* CCK Rx */ + } else { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); /* CCK Rx */ + } + halbtc8822b2ant_run_coexist_mechanism(btcoexist); + } } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], MEDIA disconnect notify\n"); @@ -5616,6 +5529,12 @@ void ex_halbtc8822b2ant_media_status_notify(IN struct btc_coexist *btcoexist, halbtc8822b2ant_post_state_to_bt(btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE); + + coex_sta->cck_lock_ever = FALSE; + coex_sta->cck_lock_warn = FALSE; + coex_sta->cck_lock = FALSE; + + halbtc8822b2ant_run_coexist_mechanism(btcoexist); } @@ -5639,7 +5558,7 @@ void ex_halbtc8822b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, "[BTCoex], WiFi is under 5G!!!\n"); BTC_TRACE(trace_buf); - halbtc8822b2ant_action_wifi_under5g(btcoexist); + halbtc8822b2ant_run_coexist_mechanism(btcoexist); return; } @@ -5674,8 +5593,11 @@ void ex_halbtc8822b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, coex_sta->specific_pkt_period_cnt = 2; } - if (coex_sta->wifi_is_high_pri_task) + if (coex_sta->wifi_is_high_pri_task) { + halbtc8822b2ant_post_state_to_bt(btcoexist, + BT_8822B_2ANT_SCOREBOARD_SCAN, TRUE); halbtc8822b2ant_run_coexist_mechanism(btcoexist); + } } @@ -5740,7 +5662,7 @@ void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, 0x10) ? TRUE : FALSE); coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & - 0x9) ? TRUE : FALSE); + 0x8) ? TRUE : FALSE); coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? TRUE : FALSE); @@ -5766,6 +5688,8 @@ void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; + coex_sta->is_bt_opp_exist = (coex_sta->bt_info_ext2 & 0x1) ? TRUE : FALSE; + if (coex_sta->bt_retry_cnt >= 1) coex_sta->pop_event_cnt++; @@ -5782,15 +5706,8 @@ void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Re-Link start in BT info!!\n"); BTC_TRACE(trace_buf); - } else { - coex_sta->is_setupLink = FALSE; - coex_sta->bt_relink_downcount = 0; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Re-Link stop in BT info!!\n"); - BTC_TRACE(trace_buf); } - if (coex_sta->bt_info_ext & BIT(3)) coex_sta->cnt_IgnWlanAct++; @@ -5802,6 +5719,16 @@ void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, else coex_sta->is_bt_multi_link = FALSE; + if (coex_sta->bt_info_ext & BIT(0)) + coex_sta->is_hid_rcu = TRUE; + else + coex_sta->is_hid_rcu = FALSE; + + if (coex_sta->bt_info_ext & BIT(5)) + coex_sta->is_ble_scan_en = TRUE; + else + coex_sta->is_ble_scan_en = FALSE; + if (coex_sta->bt_create_connection) { coex_sta->cnt_Page++; @@ -5880,30 +5807,103 @@ void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, } - if ((coex_sta->bt_info_ext & BIT(5))) { + halbtc8822b2ant_update_bt_link_info(btcoexist); + + halbtc8822b2ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8822b2ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 i = 0; + static u8 tmp_buf_pre[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi Fw Dbg info = %d %d %d %d %d %d (len = %d)\n", + tmp_buf[0], tmp_buf[1], + tmp_buf[2], tmp_buf[3], + tmp_buf[4], tmp_buf[5], length); + BTC_TRACE(trace_buf); + + if (tmp_buf[0] == 0x8) { + for (i = 1; i <= 5; i++) { + coex_sta->wl_fw_dbg_info[i] = + (tmp_buf[i] >= tmp_buf_pre[i]) ? + (tmp_buf[i] - tmp_buf_pre[i]) : + (255 - tmp_buf_pre[i] + tmp_buf[i]); + + tmp_buf_pre[i] = tmp_buf[i]; + } + } +} + + +void ex_halbtc8822b2ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist, + IN BOOLEAN is_data_frame, IN u8 btc_rate_id) +{ + BOOLEAN wifi_connected = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + if (is_data_frame) { + coex_sta->wl_rx_rate = btc_rate_id; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + "[BTCoex], rx_rate_change_notify data rate id = %d, RTS_Rate = %d\n", + coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate); BTC_TRACE(trace_buf); - coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( - btcoexist); + } else { + coex_sta->wl_rts_rx_rate = btc_rate_id; - if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) - coex_sta->bt_ble_scan_para[0] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x1); - if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) - coex_sta->bt_ble_scan_para[1] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x2); - if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) - coex_sta->bt_ble_scan_para[2] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x4); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], rts_rate_change_notify RTS rate id = %d, RTS_Rate = %d\n", + coex_sta->wl_rts_rx_rate, coex_sta->wl_rts_rx_rate); + BTC_TRACE(trace_buf); } - halbtc8822b2ant_update_bt_link_info(btcoexist); + if ((wifi_connected) && + ((coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY) || + (coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_SCO_BUSY))) { + + if ((coex_sta->wl_rx_rate == BTC_CCK_5_5) || + (coex_sta->wl_rx_rate == BTC_OFDM_6) || + (coex_sta->wl_rx_rate == BTC_MCS_0)) { + + coex_sta->cck_lock_warn = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], cck lock warning...\n"); + BTC_TRACE(trace_buf); + } else if ((coex_sta->wl_rx_rate == BTC_CCK_1) || + (coex_sta->wl_rx_rate == BTC_CCK_2) || + (coex_sta->wl_rts_rx_rate == BTC_CCK_1) || + (coex_sta->wl_rts_rx_rate == BTC_CCK_2)) { + + coex_sta->cck_lock = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], cck locking...\n"); + BTC_TRACE(trace_buf); + } else { + coex_sta->cck_lock_warn = FALSE; + coex_sta->cck_lock = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], cck unlock...\n"); + BTC_TRACE(trace_buf); + } + } else { + if ((coex_dm->bt_status == + BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE) || + (coex_dm->bt_status == + BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE)) { + coex_sta->cck_lock_warn = FALSE; + coex_sta->cck_lock = FALSE; + } + } - halbtc8822b2ant_run_coexist_mechanism(btcoexist); } @@ -5941,7 +5941,8 @@ void ex_halbtc8822b2ant_rf_status_notify(IN struct btc_coexist *btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE | BT_8822B_2ANT_SCOREBOARD_ONOFF | BT_8822B_2ANT_SCOREBOARD_SCAN | - BT_8822B_2ANT_SCOREBOARD_UNDERTEST, + BT_8822B_2ANT_SCOREBOARD_UNDERTEST | + BT_8822B_2ANT_SCOREBOARD_RXGAIN, FALSE); btcoexist->stop_coex_dm = TRUE; @@ -5960,9 +5961,14 @@ void ex_halbtc8822b2ant_halt_notify(IN struct btc_coexist *btcoexist) ex_halbtc8822b2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE); - halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ONOFF, FALSE); + BT_8822B_2ANT_SCOREBOARD_ACTIVE | + BT_8822B_2ANT_SCOREBOARD_ONOFF | + BT_8822B_2ANT_SCOREBOARD_SCAN | + BT_8822B_2ANT_SCOREBOARD_UNDERTEST | + BT_8822B_2ANT_SCOREBOARD_RXGAIN, + FALSE); + + btcoexist->stop_coex_dm = TRUE; } void ex_halbtc8822b2ant_pnp_notify(IN struct btc_coexist *btcoexist, @@ -5992,10 +5998,12 @@ void ex_halbtc8822b2ant_pnp_notify(IN struct btc_coexist *btcoexist, coex_sta->under_lps = FALSE; halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE); - halbtc8822b2ant_post_state_to_bt(btcoexist, - BT_8822B_2ANT_SCOREBOARD_ONOFF, FALSE); - + BT_8822B_2ANT_SCOREBOARD_ACTIVE | + BT_8822B_2ANT_SCOREBOARD_ONOFF | + BT_8822B_2ANT_SCOREBOARD_SCAN | + BT_8822B_2ANT_SCOREBOARD_UNDERTEST | + BT_8822B_2ANT_SCOREBOARD_RXGAIN, + FALSE); if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { @@ -6010,18 +6018,21 @@ void ex_halbtc8822b2ant_pnp_notify(IN struct btc_coexist *btcoexist, } else { halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8822B_2ANT_PHASE_WLAN_OFF); + FORCE_EXEC, + BT_8822B_2ANT_PHASE_WLAN_OFF); } + + btcoexist->stop_coex_dm = TRUE; } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify to WAKE UP\n"); BTC_TRACE(trace_buf); - +#if 0 halbtc8822b2ant_post_state_to_bt(btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE); halbtc8822b2ant_post_state_to_bt(btcoexist, BT_8822B_2ANT_SCOREBOARD_ONOFF, TRUE); +#endif } } @@ -6043,7 +6054,7 @@ void ex_halbtc8822b2ant_periodical(IN struct btc_coexist *btcoexist) halbtc8822b2ant_monitor_wifi_ctr(btcoexist); halbtc8822b2ant_monitor_bt_enable_disable(btcoexist); -#if 1 +#if 0 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); halbtc8822b2ant_read_score_board(btcoexist, &bt_scoreboard_val); diff --git a/hal/btc/halbtc8822b2ant.h b/hal/btc/halbtc8822b2ant.h index 5338473..acbb959 100644 --- a/hal/btc/halbtc8822b2ant.h +++ b/hal/btc/halbtc8822b2ant.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) @@ -27,20 +41,21 @@ /* unit: % WiFi RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation. * (default = 42) */ -#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 10 +#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 25 /* unit: % BT RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation. * (default = 46) */ -#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 10 +#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 22 /* unit: % WiFi RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation. * (default = 42) */ -#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 10 +#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 25 /* unit: % BT RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation. * (default = 46) */ -#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2 10 -#define BT_8822B_2ANT_DEFAULT_ISOLATION 15 /* unit: dB */ +#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2 22 + +#define BT_8822B_2ANT_DEFAULT_ISOLATION 25 /* unit: dB */ #define BT_8822B_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */ #define BT_8822B_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */ #define BT_8822B_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */ @@ -185,6 +200,7 @@ enum bt_8822b_2ant_phase { BT_8822B_2ANT_PHASE_ANTENNA_DET = 0x6, BT_8822B_2ANT_PHASE_COEX_POWERON = 0x7, BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT = 0x8, + BT_8822B_2ANT_PHASE_2G_FREERUN = 0x9, BT_8822B_2ANT_PHASE_MAX }; @@ -195,7 +211,10 @@ enum bt_8822b_2ant_Scoreboard { BT_8822B_2ANT_SCOREBOARD_ONOFF = BIT(1), BT_8822B_2ANT_SCOREBOARD_SCAN = BIT(2), BT_8822B_2ANT_SCOREBOARD_UNDERTEST = BIT(3), - BT_8822B_2ANT_SCOREBOARD_WLBUSY = BIT(6) + BT_8822B_2ANT_SCOREBOARD_RXGAIN = BIT(4), + BT_8822B_2ANT_SCOREBOARD_WLBUSY = BIT(6), + BT_8822B_2ANT_SCOREBOARD_EXTFEM = BIT(8), + BT_8822B_2ANT_SCOREBOARD_BTCQDDR = BIT(10) }; @@ -319,12 +338,12 @@ struct coex_sta_8822b_2ant { u32 acc_crc_ratio; u32 now_crc_ratio; - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; + boolean cck_lock; + boolean cck_lock_ever; + boolean cck_lock_warn; u8 coex_table_type; - boolean force_lps_ctrl; + boolean force_lps_ctrl; u8 dis_ver_info_cnt; @@ -391,6 +410,24 @@ struct coex_sta_8822b_2ant { boolean is_set_ps_state_fail; u8 cnt_set_ps_state_fail; + + u8 wl_fw_dbg_info[10]; + u8 wl_rx_rate; + u8 wl_rts_rx_rate; + u8 wl_center_channel; + + boolean is_2g_freerun; + + u16 score_board_WB; + boolean is_hid_rcu; + u16 legacy_forbidden_slot; + u16 le_forbidden_slot; + u8 bt_a2dp_vendor_id; + u32 bt_a2dp_device_name; + boolean is_ble_scan_en; + + boolean is_bt_opp_exist; + boolean gl_wifi_busy; }; @@ -489,12 +526,18 @@ void ex_halbtc8822b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, IN u8 type); void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist, IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8822b2ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8822b2ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist, + IN BOOLEAN is_data_frame, IN u8 btc_rate_id); void ex_halbtc8822b2ant_rf_status_notify(IN struct btc_coexist *btcoexist, IN u8 type); void ex_halbtc8822b2ant_halt_notify(IN struct btc_coexist *btcoexist); void ex_halbtc8822b2ant_pnp_notify(IN struct btc_coexist *btcoexist, IN u8 pnp_state); void ex_halbtc8822b2ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8822b2ant_display_simple_coex_info(IN struct btc_coexist *btcoexist); + void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist); void ex_halbtc8822b2ant_antenna_detection(IN struct btc_coexist *btcoexist, IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); @@ -514,6 +557,8 @@ void ex_halbtc8822b2ant_display_ant_detection(IN struct btc_coexist *btcoexist); #define ex_halbtc8822b2ant_media_status_notify(btcoexist, type) #define ex_halbtc8822b2ant_specific_packet_notify(btcoexist, type) #define ex_halbtc8822b2ant_bt_info_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8822b2ant_wl_fwdbginfo_notify(btcoexist, tmp_buf, length) +#define ex_halbtc8822b2ant_rx_rate_change_notify(btcoexist, is_data_frame, btc_rate_id) #define ex_halbtc8822b2ant_rf_status_notify(btcoexist, type) #define ex_halbtc8822b2ant_halt_notify(btcoexist) #define ex_halbtc8822b2ant_pnp_notify(btcoexist, pnp_state) @@ -521,6 +566,7 @@ void ex_halbtc8822b2ant_display_ant_detection(IN struct btc_coexist *btcoexist); #define ex_halbtc8822b2ant_display_coex_info(btcoexist) #define ex_halbtc8822b2ant_display_ant_detection(btcoexist) #define ex_halbtc8822b2ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8822b2ant_display_simple_coex_info(btcoexist) #endif #endif diff --git a/hal/btc/halbtcoutsrc.h b/hal/btc/halbtcoutsrc.h index 2005e1e..fefcf34 100644 --- a/hal/btc/halbtcoutsrc.h +++ b/hal/btc/halbtcoutsrc.h @@ -15,6 +15,106 @@ #ifndef __HALBTC_OUT_SRC_H__ #define __HALBTC_OUT_SRC_H__ +enum { + BTC_CCK_1, + BTC_CCK_2, + BTC_CCK_5_5, + BTC_CCK_11, + BTC_OFDM_6, + BTC_OFDM_9, + BTC_OFDM_12, + BTC_OFDM_18, + BTC_OFDM_24, + BTC_OFDM_36, + BTC_OFDM_48, + BTC_OFDM_54, + BTC_MCS_0, + BTC_MCS_1, + BTC_MCS_2, + BTC_MCS_3, + BTC_MCS_4, + BTC_MCS_5, + BTC_MCS_6, + BTC_MCS_7, + BTC_MCS_8, + BTC_MCS_9, + BTC_MCS_10, + BTC_MCS_11, + BTC_MCS_12, + BTC_MCS_13, + BTC_MCS_14, + BTC_MCS_15, + BTC_MCS_16, + BTC_MCS_17, + BTC_MCS_18, + BTC_MCS_19, + BTC_MCS_20, + BTC_MCS_21, + BTC_MCS_22, + BTC_MCS_23, + BTC_MCS_24, + BTC_MCS_25, + BTC_MCS_26, + BTC_MCS_27, + BTC_MCS_28, + BTC_MCS_29, + BTC_MCS_30, + BTC_MCS_31, + BTC_VHT_1SS_MCS_0, + BTC_VHT_1SS_MCS_1, + BTC_VHT_1SS_MCS_2, + BTC_VHT_1SS_MCS_3, + BTC_VHT_1SS_MCS_4, + BTC_VHT_1SS_MCS_5, + BTC_VHT_1SS_MCS_6, + BTC_VHT_1SS_MCS_7, + BTC_VHT_1SS_MCS_8, + BTC_VHT_1SS_MCS_9, + BTC_VHT_2SS_MCS_0, + BTC_VHT_2SS_MCS_1, + BTC_VHT_2SS_MCS_2, + BTC_VHT_2SS_MCS_3, + BTC_VHT_2SS_MCS_4, + BTC_VHT_2SS_MCS_5, + BTC_VHT_2SS_MCS_6, + BTC_VHT_2SS_MCS_7, + BTC_VHT_2SS_MCS_8, + BTC_VHT_2SS_MCS_9, + BTC_VHT_3SS_MCS_0, + BTC_VHT_3SS_MCS_1, + BTC_VHT_3SS_MCS_2, + BTC_VHT_3SS_MCS_3, + BTC_VHT_3SS_MCS_4, + BTC_VHT_3SS_MCS_5, + BTC_VHT_3SS_MCS_6, + BTC_VHT_3SS_MCS_7, + BTC_VHT_3SS_MCS_8, + BTC_VHT_3SS_MCS_9, + BTC_VHT_4SS_MCS_0, + BTC_VHT_4SS_MCS_1, + BTC_VHT_4SS_MCS_2, + BTC_VHT_4SS_MCS_3, + BTC_VHT_4SS_MCS_4, + BTC_VHT_4SS_MCS_5, + BTC_VHT_4SS_MCS_6, + BTC_VHT_4SS_MCS_7, + BTC_VHT_4SS_MCS_8, + BTC_VHT_4SS_MCS_9, + BTC_MCS_32, + BTC_UNKNOWN, + BTC_PKT_MGNT, + BTC_PKT_CTRL, + BTC_PKT_UNKNOWN, + BTC_PKT_NOT_FOR_ME, + BTC_RATE_MAX +}; + +enum { + BTC_MULTIPORT_SCC, + BTC_MULTIPORT_MCC_DUAL_CHANNEL, + BTC_MULTIPORT_MCC_DUAL_BAND, + BTC_MULTIPORT_MAX +}; #define BTC_COEX_OFFLOAD 0 #define BTC_TMP_BUF_SHORT 20 @@ -133,6 +233,7 @@ struct btc_board_info { u8 ant_det_result; boolean ant_det_result_five_complete; u32 antdetval; + u8 customerID; }; typedef enum _BTC_DBG_OPCODE { @@ -251,6 +352,7 @@ typedef enum _BTC_GET_TYPE { BTC_GET_BL_HS_CONNECTING, BTC_GET_BL_WIFI_FW_READY, BTC_GET_BL_WIFI_CONNECTED, + BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED, BTC_GET_BL_WIFI_BUSY, BTC_GET_BL_WIFI_SCAN, BTC_GET_BL_WIFI_LINK, @@ -278,6 +380,8 @@ typedef enum _BTC_GET_TYPE { BTC_GET_U4_VENDOR, BTC_GET_U4_SUPPORTED_VERSION, BTC_GET_U4_SUPPORTED_FEATURE, + BTC_GET_U4_BT_DEVICE_INFO, + BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL, BTC_GET_U4_WIFI_IQK_TOTAL, BTC_GET_U4_WIFI_IQK_OK, BTC_GET_U4_WIFI_IQK_FAIL, @@ -292,6 +396,9 @@ typedef enum _BTC_GET_TYPE { BTC_GET_U1_ANT_TYPE, BTC_GET_U1_IOT_PEER, + /* type u2Byte */ + BTC_GET_U2_BEACON_PERIOD, + /*===== for 1Ant ======*/ BTC_GET_U1_LPS_MODE, @@ -311,6 +418,7 @@ typedef enum _BTC_SET_TYPE { BTC_SET_BL_INC_SCAN_DEV_NUM, BTC_SET_BL_BT_TX_RX_MASK, BTC_SET_BL_MIRACAST_PLUS_BT, + BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL, /* type u1Byte */ BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, @@ -320,6 +428,9 @@ typedef enum _BTC_SET_TYPE { BTC_SET_ACT_GET_BT_RSSI, BTC_SET_ACT_AGGREGATE_CTRL, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, + + // for mimo ps mode setting + BTC_SET_MIMO_PS_MODE, /*===== for 1Ant ======*/ /* type BOOLEAN */ @@ -583,7 +694,7 @@ typedef u4Byte typedef VOID (*BFP_BTC_SET_RF_REG)( IN PVOID pBtcContext, - IN u1Byte eRFPath, + IN enum rf_path eRFPath, IN u4Byte RegAddr, IN u4Byte BitMask, IN u4Byte Data @@ -591,7 +702,7 @@ typedef VOID typedef u4Byte (*BFP_BTC_GET_RF_REG)( IN PVOID pBtcContext, - IN u1Byte eRFPath, + IN enum rf_path eRFPath, IN u4Byte RegAddr, IN u4Byte BitMask ); @@ -685,6 +796,12 @@ typedef u4Byte IN u1Byte info_type ); +typedef VOID +(*BTC_PHYDM_MODIFY_ANTDIV_HWSW)( + IN PVOID pDM_Odm, + IN u1Byte type + ); + typedef u1Byte (*BFP_BTC_GET_ANT_DET_VAL_FROM_BT)( @@ -795,6 +912,7 @@ struct btc_statistics { u32 cnt_coex_dm_switch; u32 cnt_stack_operation_notify; u32 cnt_dbg_ctrl; + u32 cnt_rate_id_notify; }; struct btc_coexist { @@ -857,6 +975,7 @@ struct btc_coexist { BFP_BTC_GET_PHYDM_VERSION btc_get_bt_phydm_version; BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD btc_phydm_modify_RA_PCR_threshold; BTC_PHYDM_CMNINFOQUERY btc_phydm_query_PHY_counter; + BTC_PHYDM_MODIFY_ANTDIV_HWSW btc_phydm_modify_ANTDIV_HwSw; BFP_BTC_GET_ANT_DET_VAL_FROM_BT btc_get_ant_det_val_from_bt; BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT btc_get_ble_scan_type_from_bt; BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT btc_get_ble_scan_para_from_bt; @@ -934,6 +1053,18 @@ EXhalbtcoutsrc_RfStatusNotify( IN u1Byte type ); VOID +EXhalbtcoutsrc_WlFwDbgInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtcoutsrc_rx_rate_change_notify( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN is_data_frame, + IN u1Byte btc_rate_id + ); +VOID EXhalbtcoutsrc_StackOperationNotify( IN PBTC_COEXIST pBtCoexist, IN u1Byte type diff --git a/hal/btc/mp_precomp.h b/hal/btc/mp_precomp.h index b7402aa..2c333c2 100644 --- a/hal/btc/mp_precomp.h +++ b/hal/btc/mp_precomp.h @@ -60,26 +60,68 @@ extern u4Byte GLBtcDbgType[]; #endif #include "halbtcoutsrc.h" + +/* for wifi only mode */ +#include "hal_btcoex_wifionly.h" + +#ifdef CONFIG_BT_COEXIST + +#ifdef CONFIG_RTL8192E #include "halbtc8192e1ant.h" #include "halbtc8192e2ant.h" +#endif + +#ifdef CONFIG_RTL8723B +#include "halbtc8723bwifionly.h" #include "halbtc8723b1ant.h" #include "halbtc8723b2ant.h" +#endif + +#ifdef CONFIG_RTL8812A #include "halbtc8812a1ant.h" #include "halbtc8812a2ant.h" +#endif + +#ifdef CONFIG_RTL8821A #include "halbtc8821a1ant.h" #include "halbtc8821a2ant.h" +#endif + +#ifdef CONFIG_RTL8703B #include "halbtc8703b1ant.h" +#endif + +#ifdef CONFIG_RTL8723D #include "halbtc8723d1ant.h" #include "halbtc8723d2ant.h" +#endif + +#ifdef CONFIG_RTL8822B +#include "halbtc8822bwifionly.h" #include "halbtc8822b1ant.h" #include "halbtc8822b2ant.h" +#endif + +#ifdef CONFIG_RTL8821C +#include "halbtc8821cwifionly.h" #include "halbtc8821c1ant.h" #include "halbtc8821c2ant.h" +#endif -/* for wifi only mode */ -#include "hal_btcoex_wifionly.h" +#else /* CONFIG_BT_COEXIST */ + +#ifdef CONFIG_RTL8723B #include "halbtc8723bwifionly.h" +#endif + +#ifdef CONFIG_RTL8822B #include "halbtc8822bwifionly.h" +#endif + +#ifdef CONFIG_RTL8821C #include "halbtc8821cwifionly.h" +#endif + +#endif /* CONFIG_BT_COEXIST */ #endif /* __MP_PRECOMP_H__ */ diff --git a/hal/hal_btcoex.c b/hal/hal_btcoex.c index 05ab197..9e63f2c 100644 --- a/hal/hal_btcoex.c +++ b/hal/hal_btcoex.c @@ -174,8 +174,11 @@ typedef enum _bt_op_code { BT_OP_GET_BT_COEX_SUPPORTED_FEATURE = 0x2a, BT_OP_GET_BT_COEX_SUPPORTED_VERSION = 0x2b, BT_OP_GET_BT_ANT_DET_VAL = 0x2c, - BT_OP_GET_BT_BLE_SCAN_PARA = 0x2d, - BT_OP_GET_BT_BLE_SCAN_TYPE = 0x2e, + BT_OP_GET_BT_BLE_SCAN_TYPE = 0x2d, + BT_OP_GET_BT_BLE_SCAN_PARA = 0x2e, + BT_OP_GET_BT_DEVICE_INFO = 0x30, + BT_OP_GET_BT_FORBIDDEN_SLOT_VAL = 0x31, + BT_OP_SET_BT_LANCONSTRAIN_LEVEL = 0x32, BT_OP_MAX } BT_OP_CODE; @@ -381,7 +384,7 @@ void halbtcoutsrc_LeaveLowPower(PBTC_COEXIST pBtCoexist) PHAL_DATA_TYPE pHalData; struct pwrctrl_priv *pwrctrl; s32 ready; - u32 stime; + systime stime; s32 utime; u32 timeout; /* unit: ms */ @@ -512,9 +515,30 @@ u8 halbtcoutsrc_is_fw_ready(PBTC_COEXIST pBtCoexist) return GET_HAL_DATA(padapter)->bFWReady; } +u8 halbtcoutsrc_IsDualBandConnected(PADAPTER padapter) +{ + u8 ret = BTC_MULTIPORT_SCC; + +#ifdef CONFIG_MCC_MODE + if (MCC_EN(padapter) && (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))) { + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + u8 band0 = mccobjpriv->iface[0]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G; + u8 band1 = mccobjpriv->iface[1]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G; + + if (band0 != band1) + ret = BTC_MULTIPORT_MCC_DUAL_BAND; + else + ret = BTC_MULTIPORT_MCC_DUAL_CHANNEL; + } +#endif + + return ret; +} + u8 halbtcoutsrc_IsWifiBusy(PADAPTER padapter) { - if (rtw_mi_check_status(padapter, MI_AP_MODE)) + if (rtw_mi_check_status(padapter, MI_AP_ASSOC)) return _TRUE; if (rtw_mi_busy_traffic_check(padapter, _FALSE)) return _TRUE; @@ -593,8 +617,8 @@ u32 halbtcoutsrc_GetWifiLinkStatus(PBTC_COEXIST pBtCoexist) static void _btmpoper_timer_hdl(void *p) { - if (GLBtcBtMpRptWait) { - GLBtcBtMpRptWait = 0; + if (GLBtcBtMpRptWait == _TRUE) { + GLBtcBtMpRptWait = _FALSE; _rtw_up_sema(&GLBtcBtMpRptSema); } } @@ -627,9 +651,9 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm if (cmd && size) _rtw_memcpy(buf + 2, cmd, size); - GLBtcBtMpRptWait = 1; - GLBtcBtMpRptWiFiOK = 0; - GLBtcBtMpRptBTOK = 0; + GLBtcBtMpRptWait = _TRUE; + GLBtcBtMpRptWiFiOK = _FALSE; + GLBtcBtMpRptBTOK = _FALSE; GLBtcBtMpRptStatus = 0; padapter = pBtCoexist->Adapter; _set_timer(&GLBtcBtMpOperTimer, BTC_MPOPER_TIMEOUT); @@ -640,18 +664,19 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm } _rtw_down_sema(&GLBtcBtMpRptSema); - /* GLBtcBtMpRptWait should be 0 here*/ + /* GLBtcBtMpRptWait should be _FALSE here*/ - if (!GLBtcBtMpRptWiFiOK) { + if (GLBtcBtMpRptWiFiOK == _FALSE) { RTW_ERR("%s: Didn't get H2C Rsp Event!\n", __FUNCTION__); ret = BT_STATUS_H2C_TIMTOUT; goto exit; } - if (!GLBtcBtMpRptBTOK) { + if (GLBtcBtMpRptBTOK == _FALSE) { RTW_DBG("%s: Didn't get BT response!\n", __FUNCTION__); ret = BT_STATUS_H2C_BT_NO_RSP; goto exit; } + if (seq != GLBtcBtMpRptSeq) { RTW_ERR("%s: Sequence number not match!(%d!=%d)!\n", __FUNCTION__, seq, GLBtcBtMpRptSeq); @@ -722,14 +747,7 @@ u32 halbtcoutsrc_GetBtPatchVer(PBTC_COEXIST pBtCoexist) s32 halbtcoutsrc_GetWifiRssi(PADAPTER padapter) { - PHAL_DATA_TYPE pHalData; - s32 undecorated_smoothed_pwdb = 0; - - pHalData = GET_HAL_DATA(padapter); - - undecorated_smoothed_pwdb = pHalData->entry_min_undecorated_smoothed_pwdb; - - return undecorated_smoothed_pwdb; + return rtw_phydm_get_min_rssi(padapter); } u32 halbtcoutsrc_GetBtCoexSupportedFeature(void *pBtcContext) @@ -794,6 +812,68 @@ u32 halbtcoutsrc_GetBtCoexSupportedVersion(void *pBtcContext) return data; } +u32 halbtcoutsrc_GetBtDeviceInfo(void *pBtcContext) +{ + PBTC_COEXIST pBtCoexist; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + u32 btDeviceInfo = 0; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_GET_BT_DEVICE_INFO; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + btDeviceInfo = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp); + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return btDeviceInfo; +} + +u32 halbtcoutsrc_GetBtForbiddenSlotVal(void *pBtcContext) +{ + PBTC_COEXIST pBtCoexist; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + u32 btForbiddenSlotVal = 0; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_GET_BT_FORBIDDEN_SLOT_VAL; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + btForbiddenSlotVal = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp); + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return btForbiddenSlotVal; +} + static u8 halbtcoutsrc_GetWifiScanAPNum(PADAPTER padapter) { struct mlme_priv *pmlmepriv; @@ -825,6 +905,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) s32 *pS4Tmp; u32 *pU4Tmp; u8 *pU1Tmp; + u16 *pU2Tmp; u8 ret; @@ -841,6 +922,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) pS4Tmp = (s32 *)pOutBuf; pU4Tmp = (u32 *)pOutBuf; pU1Tmp = (u8 *)pOutBuf; + pU2Tmp = (u16*)pOutBuf; ret = _TRUE; switch (getType) { @@ -862,6 +944,10 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) *pu8 = (rtw_mi_check_status(padapter, MI_LINKED)) ? _TRUE : _FALSE; break; + case BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED: + *pu8 = halbtcoutsrc_IsDualBandConnected(padapter); + break; + case BTC_GET_BL_WIFI_BUSY: *pu8 = halbtcoutsrc_IsWifiBusy(padapter); break; @@ -889,7 +975,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) break; case BTC_GET_BL_WIFI_UNDER_5G: - *pu8 = (pHalData->current_band_type == 1) ? _TRUE : _FALSE; + *pu8 = (pHalData->current_band_type == BAND_ON_5G) ? _TRUE : _FALSE; break; case BTC_GET_BL_WIFI_AP_MODE_ENABLE: @@ -1003,6 +1089,14 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) *pU4Tmp = halbtcoutsrc_GetBtCoexSupportedFeature(pBtCoexist); break; + case BTC_GET_U4_BT_DEVICE_INFO: + *pU4Tmp = halbtcoutsrc_GetBtDeviceInfo(pBtCoexist); + break; + + case BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL: + *pU4Tmp = halbtcoutsrc_GetBtForbiddenSlotVal(pBtCoexist); + break; + case BTC_GET_U4_WIFI_IQK_TOTAL: *pU4Tmp = pHalData->odmpriv.n_iqk_cnt; break; @@ -1083,6 +1177,10 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) *pU1Tmp = padapter->dvobj->pwrctl_priv.pwr_mode; break; + case BTC_GET_U2_BEACON_PERIOD: + *pU2Tmp = mlmeext->mlmext_info.bcn_interval; + break; + default: ret = _FALSE; break; @@ -1091,6 +1189,30 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) return ret; } +u16 halbtcoutsrc_LnaConstrainLvl(void *pBtcContext, u8 *lna_constrain_level) +{ + PBTC_COEXIST pBtCoexist; + u16 ret = BT_STATUS_BT_OP_SUCCESS; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + _irqL irqL; + u8 op_code; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + ret = _btmpoper_cmd(pBtCoexist, BT_OP_SET_BT_LANCONSTRAIN_LEVEL, 0, lna_constrain_level, 1); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + } else { + ret = BT_STATUS_NOT_IMPLEMENT; + RTW_INFO("%s halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == FALSE\n", __func__); + } + + return ret; +} + u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) { PBTC_COEXIST pBtCoexist; @@ -1218,6 +1340,7 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) break; case BTC_SET_ACT_UPDATE_RAMASK: + /* pBtCoexist->bt_info.ra_mask = *pU4Tmp; if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) { @@ -1226,8 +1349,9 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) cur_network = &padapter->mlmeextpriv.mlmext_info.network; psta = rtw_get_stainfo(&padapter->stapriv, cur_network->MacAddress); - rtw_hal_update_ra_mask(psta, psta->rssi_level, _FALSE); + rtw_hal_update_ra_mask(psta); } + */ break; case BTC_SET_ACT_SEND_MIMO_PS: { @@ -1289,6 +1413,9 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) ret = _FALSE; #endif break; + case BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL: + halbtcoutsrc_LnaConstrainLvl(pBtCoexist, pu8); + break; /* ===================== */ default: ret = _FALSE; @@ -1540,18 +1667,20 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist) BOOLEAN bBtHsOn = _FALSE, bLowPower = _FALSE; u8 wifiChnl = 0, wifiP2PChnl = 0, nScanAPNum = 0, FwPSState; u32 iqk_cnt_total = 0, iqk_cnt_ok = 0, iqk_cnt_fail = 0; + u16 wifiBcnInterval = 0; wifiLinkStatus = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "STA/vWifi/HS/p2pGo/p2pGc", \ + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d (mcc+2band = %d)", "STA/vWifi/HS/p2pGo/p2pGc", ((wifiLinkStatus & WIFI_STA_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_AP_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_HS_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) ? 1 : 0), - ((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0)); + ((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0), + halbtcoutsrc_IsDualBandConnected(padapter) ? 1 : 0); CL_PRINTF(cliBuf); pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Link/ Roam/ Scan", \ + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Link/ Roam/ Scan", bLink, bRoam, bScan); CL_PRINTF(cliBuf); @@ -1570,10 +1699,11 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist) pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_DOT11_CHNL, &wifiChnl); + pBtCoexist->btc_get(pBtCoexist, BTC_GET_U2_BEACON_PERIOD, &wifiBcnInterval); if ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) || (wifiLinkStatus & WIFI_P2P_GC_CONNECTED)) pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_P2P_CHNL, &wifiP2PChnl); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dBm/ %d/ %d", "RSSI/ STA_Chnl/ P2P_Chnl", \ - wifiRssi -100, wifiChnl, wifiP2PChnl); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dBm/ %d/ %d/ %d", "RSSI/ STA_Chnl/ P2P_Chnl/ BI", + wifiRssi-100, wifiChnl, wifiP2PChnl, wifiBcnInterval); CL_PRINTF(cliBuf); pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifiFreq); @@ -1582,7 +1712,7 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist) pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_AP_NUM, &nScanAPNum); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s/ %d ", "Band/ BW/ Traffic/ APCnt", \ + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s/ %d ", "Band/ BW/ Traffic/ APCnt", GLBtcWifiFreqString[wifiFreq], ((bWifiUnderBMode) ? "11b" : GLBtcWifiBwString[wifiBw]), ((!bWifiBusy) ? "idle" : ((BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) ? "uplink" : "downlink")), nScanAPNum); @@ -1595,7 +1725,7 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist) ((halbtcoutsrc_Under32K(pBtCoexist) == _TRUE) ? ", 32k" : "")); CL_PRINTF(cliBuf); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)", "Power mode cmd(lps/rpwm)", \ + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)", "Power mode cmd(lps/rpwm)", pBtCoexist->pwrModeVal[0], pBtCoexist->pwrModeVal[1], pBtCoexist->pwrModeVal[2], pBtCoexist->pwrModeVal[3], pBtCoexist->pwrModeVal[4], pBtCoexist->pwrModeVal[5], @@ -1764,7 +1894,7 @@ u32 halbtcoutsrc_GetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask) return phy_query_bb_reg(padapter, RegAddr, BitMask); } -void halbtcoutsrc_SetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +void halbtcoutsrc_SetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data) { PBTC_COEXIST pBtCoexist; PADAPTER padapter; @@ -1776,7 +1906,7 @@ void halbtcoutsrc_SetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMa phy_set_rf_reg(padapter, eRFPath, RegAddr, BitMask, Data); } -u32 halbtcoutsrc_GetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask) +u32 halbtcoutsrc_GetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask) { PBTC_COEXIST pBtCoexist; PADAPTER padapter; @@ -2109,11 +2239,12 @@ u32 halbtcoutsrc_GetBleScanParaFromBt(void *pBtcContext, u8 scanType) u8 op_code; u8 status; + buf[0] = scanType; _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); op_code = BT_OP_GET_BT_BLE_SCAN_PARA; - status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 1); if (status == BT_STATUS_BT_OP_SUCCESS) data = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp); else @@ -2219,6 +2350,11 @@ u32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext) #endif } +void halbtcoutsrc_phydm_modify_AntDiv_HwSw(void *pBtcContext, u8 is_hw) +{ + /* empty function since we don't need it */ +} + void halbtcoutsrc_phydm_modify_RA_PCR_threshold(void *pBtcContext, u8 RA_offset_direction, u8 RA_threshold_offset) { struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext; @@ -2235,7 +2371,7 @@ u32 halbtcoutsrc_phydm_query_PHY_counter(void *pBtcContext, u8 info_type) /* switch to #if 0 in case the phydm version does not provide the function */ #if 1 - return phydm_cmn_info_query((struct PHY_DM_STRUCT *)pBtCoexist->odm_priv, (enum phydm_info_query_e)info_type); + return phydm_cmn_info_query((struct dm_struct *)pBtCoexist->odm_priv, (enum phydm_info_query)info_type); #else return 0; #endif @@ -2362,7 +2498,6 @@ void BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length) u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter) { PBTC_COEXIST pBtCoexist = &GLBtCoexist; - u8 antNum = 1, chipType = 0, singleAntPath = 0; HAL_DATA_TYPE *pHalData = GET_HAL_DATA((PADAPTER)padapter); if (pBtCoexist->bBinded) @@ -2383,6 +2518,14 @@ u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter) pBtCoexist->bt_info.increase_scan_dev_num = _FALSE; pBtCoexist->bt_info.miracast_plus_bt = _FALSE; + return _TRUE; +} + +void EXhalbtcoutsrc_AntInfoSetting(void *padapter) +{ + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + u8 antNum = 1, singleAntPath = 0; + antNum = rtw_btcoex_get_pg_ant_num((PADAPTER)padapter); EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_PG, antNum); @@ -2391,6 +2534,8 @@ u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter) EXhalbtcoutsrc_SetSingleAntPath(singleAntPath); } + pBtCoexist->board_info.customerID = RT_CID_DEFAULT; + /* set default antenna position to main port */ pBtCoexist->board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; @@ -2403,7 +2548,6 @@ u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter) pBtCoexist->board_info.ant_div_cfg = rtw_btcoex_get_ant_div_cfg((PADAPTER)padapter); - return _TRUE; } u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter) @@ -2462,6 +2606,7 @@ u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter) pBtCoexist->btc_get_bt_phydm_version = halbtcoutsrc_GetPhydmVersion; pBtCoexist->btc_phydm_modify_RA_PCR_threshold = halbtcoutsrc_phydm_modify_RA_PCR_threshold; pBtCoexist->btc_phydm_query_PHY_counter = halbtcoutsrc_phydm_query_PHY_counter; + pBtCoexist->btc_phydm_modify_ANTDIV_HwSw = halbtcoutsrc_phydm_modify_AntDiv_HwSw; pBtCoexist->cli_buf = &GLBtcDbgBuf[0]; @@ -2484,9 +2629,9 @@ u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter) GLBtcBtMpRptStatus = 0; _rtw_memset(GLBtcBtMpRptRsp, 0, C2H_MAX_SIZE); GLBtcBtMpRptRspSize = 0; - GLBtcBtMpRptWait = 0; - GLBtcBtMpRptWiFiOK = 0; - GLBtcBtMpRptBTOK = 0; + GLBtcBtMpRptWait = _FALSE; + GLBtcBtMpRptWiFiOK = _FALSE; + GLBtcBtMpRptBTOK = _FALSE; return _TRUE; } @@ -2500,34 +2645,57 @@ void EXhalbtcoutsrc_PowerOnSetting(PBTC_COEXIST pBtCoexist) pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter); - /* Power on setting function is only added in 8723B currently */ if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723B if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_power_on_setting(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_power_on_setting(pBtCoexist); +#endif } - if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8703b1ant_power_on_setting(pBtCoexist); + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_power_on_setting(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_power_on_setting(pBtCoexist); } +#endif + +#ifdef CONFIG_RTL8821A + else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821a1ant_power_on_setting(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821a2ant_power_on_setting(pBtCoexist); + } +#endif - if ((IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) { +#ifdef CONFIG_RTL8822B + else if ((IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_power_on_setting(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_power_on_setting(pBtCoexist); } +#endif - if ((IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) { +#ifdef CONFIG_RTL8821C + else if ((IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_power_on_setting(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_power_on_setting(pBtCoexist); } +#endif } void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist) @@ -2538,25 +2706,31 @@ void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist) pBtCoexist->statistics.cnt_pre_load_firmware++; if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723B if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_pre_load_firmware(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_pre_load_firmware(pBtCoexist); +#endif } - if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_pre_load_firmware(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_pre_load_firmware(pBtCoexist); } +#endif - if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_pre_load_firmware(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_pre_load_firmware(pBtCoexist); } +#endif } void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly) @@ -2567,39 +2741,59 @@ void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly) pBtCoexist->statistics.cnt_init_hw_config++; if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_init_hw_config(pBtCoexist, bWifiOnly); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_init_hw_config(pBtCoexist, bWifiOnly); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_init_hw_config(pBtCoexist, bWifiOnly); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_init_hw_config(pBtCoexist, bWifiOnly); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_init_hw_config(pBtCoexist, bWifiOnly); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_init_hw_config(pBtCoexist, bWifiOnly); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_init_hw_config(pBtCoexist, bWifiOnly); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 2) @@ -2608,7 +2802,11 @@ void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly) rtw_hal_set_default_port_id_cmd(pBtCoexist->Adapter, 0); rtw_hal_set_wifi_port_id_cmd(pBtCoexist->Adapter); #endif - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) @@ -2618,6 +2816,7 @@ void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly) rtw_hal_set_wifi_port_id_cmd(pBtCoexist->Adapter); #endif } +#endif } void EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist) @@ -2628,49 +2827,74 @@ void EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist) pBtCoexist->statistics.cnt_init_coex_dm++; if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_init_coex_dm(pBtCoexist); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_init_coex_dm(pBtCoexist); } +#endif pBtCoexist->initilized = _TRUE; } @@ -2698,50 +2922,74 @@ void EXhalbtcoutsrc_ips_notify(PBTC_COEXIST pBtCoexist, u8 type) * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_ips_notify(pBtCoexist, ipsType); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_ips_notify(pBtCoexist, ipsType); } - +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } @@ -2766,49 +3014,74 @@ void EXhalbtcoutsrc_lps_notify(PBTC_COEXIST pBtCoexist, u8 type) } if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_lps_notify(pBtCoexist, lpsType); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_lps_notify(pBtCoexist, lpsType); } +#endif } void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type) @@ -2833,49 +3106,74 @@ void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type) * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_scan_notify(pBtCoexist, scanType); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_scan_notify(pBtCoexist, scanType); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } @@ -2910,68 +3208,85 @@ void EXhalbtcoutsrc_SetAntennaPathNotify(PBTC_COEXIST pBtCoexist, u8 type) #endif } -void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 action) +void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 assoType) { - u8 assoType; - if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; pBtCoexist->statistics.cnt_connect_notify++; if (pBtCoexist->manual_control) return; - - if (action) - assoType = BTC_ASSOCIATE_START; - else - assoType = BTC_ASSOCIATE_FINISH; - + /* All notify is called in cmd thread, don't need to leave low power again * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_connect_notify(pBtCoexist, assoType); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_connect_notify(pBtCoexist, assoType); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } @@ -2994,51 +3309,75 @@ void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS /* All notify is called in cmd thread, don't need to leave low power again * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_media_status_notify(pBtCoexist, mStatus); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_media_status_notify(pBtCoexist, mStatus); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } @@ -3066,51 +3405,75 @@ void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType) /* All notify is called in cmd thread, don't need to leave low power again * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_specific_packet_notify(pBtCoexist, packetType); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_specific_packet_notify(pBtCoexist, packetType); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } @@ -3124,55 +3487,143 @@ void EXhalbtcoutsrc_bt_info_notify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 lengt /* All notify is called in cmd thread, don't need to leave low power again * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_bt_info_notify(pBtCoexist, tmpBuf, length); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_bt_info_notify(pBtCoexist, tmpBuf, length); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } +void EXhalbtcoutsrc_WlFwDbgInfoNotify(PBTC_COEXIST pBtCoexist, u8* tmpBuf, u8 length) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8703B + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8703b1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length); +#endif + } + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8723d1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8723d2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length); + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length); + } +#endif +} + +void EXhalbtcoutsrc_rx_rate_change_notify(PBTC_COEXIST pBtCoexist, u8 is_data_frame, u8 btc_rate_id) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cnt_rate_id_notify++; + + if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8703B + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8703b1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id); +#endif + } + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8723d1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8723d2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id); + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id); + } +#endif +} + VOID EXhalbtcoutsrc_RfStatusNotify( IN PBTC_COEXIST pBtCoexist, @@ -3183,29 +3634,44 @@ EXhalbtcoutsrc_RfStatusNotify( return; pBtCoexist->statistics.cnt_rf_status_notify++; - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { + if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723B if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_rf_status_notify(pBtCoexist, type); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_rf_status_notify(pBtCoexist, type); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_rf_status_notify(pBtCoexist, type); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_rf_status_notify(pBtCoexist, type); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_rf_status_notify(pBtCoexist, type); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_rf_status_notify(pBtCoexist, type); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_rf_status_notify(pBtCoexist, type); } +#endif } void EXhalbtcoutsrc_StackOperationNotify(PBTC_COEXIST pBtCoexist, u8 type) @@ -3240,49 +3706,74 @@ void EXhalbtcoutsrc_halt_notify(PBTC_COEXIST pBtCoexist) return; if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_halt_notify(pBtCoexist); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_halt_notify(pBtCoexist); } +#endif } void EXhalbtcoutsrc_SwitchBtTRxMask(PBTC_COEXIST pBtCoexist) @@ -3305,47 +3796,71 @@ void EXhalbtcoutsrc_pnp_notify(PBTC_COEXIST pBtCoexist, u8 pnpState) /* currently only 1ant we have to do the notification, */ /* once pnp is notified to sleep state, we have to leave LPS that we can sleep normally. */ /* */ - if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723B if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_pnp_notify(pBtCoexist, pnpState); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_pnp_notify(pBtCoexist, pnpState); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_pnp_notify(pBtCoexist, pnpState); - else + } #endif + +#ifdef CONFIG_RTL8821A + else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_pnp_notify(pBtCoexist, pnpState); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_pnp_notify(pBtCoexist, pnpState); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_pnp_notify(pBtCoexist, pnpState); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_pnp_notify(pBtCoexist, pnpState); } +#endif } void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist) @@ -3357,6 +3872,7 @@ void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist) halbtcoutsrc_LeaveLowPower(pBtCoexist); if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723B if (pBtCoexist->board_info.btdm_ant_num == 1) { pBtCoexist->stop_coex_dm = TRUE; ex_halbtc8723b1ant_coex_dm_reset(pBtCoexist); @@ -3365,7 +3881,11 @@ void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist) ex_halbtc8723b2ant_init_coex_dm(pBtCoexist); pBtCoexist->stop_coex_dm = FALSE; } - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) { pBtCoexist->stop_coex_dm = TRUE; ex_halbtc8723d1ant_coex_dm_reset(pBtCoexist); @@ -3375,6 +3895,7 @@ void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist) pBtCoexist->stop_coex_dm = FALSE; } } +#endif halbtcoutsrc_NormalLowPower(pBtCoexist); } @@ -3388,53 +3909,77 @@ void EXhalbtcoutsrc_periodical(PBTC_COEXIST pBtCoexist) /* Periodical should be called in cmd thread, */ /* don't need to leave low power again * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_periodical(pBtCoexist); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) { if (!halbtcoutsrc_UnderIps(pBtCoexist)) ex_halbtc8821a1ant_periodical(pBtCoexist); } - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_periodical(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_periodical(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_periodical(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_periodical(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_periodical(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_periodical(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_periodical(pBtCoexist); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } @@ -3449,18 +3994,27 @@ void EXhalbtcoutsrc_dbg_control(PBTC_COEXIST pBtCoexist, u8 opCode, u8 opLen, u8 /* This function doesn't be called yet, */ /* default no need to leave low power to avoid deadlock * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ - if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8192E if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_dbg_control(pBtCoexist, opCode, opLen, pData); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_dbg_control(pBtCoexist, opCode, opLen, pData); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_dbg_control(pBtCoexist, opCode, opLen, pData); - } else if(IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) if(pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_dbg_control(pBtCoexist, opCode, opLen, pData); +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } @@ -3650,49 +4204,74 @@ void EXhalbtcoutsrc_DisplayBtCoexInfo(PBTC_COEXIST pBtCoexist) halbtcoutsrc_EnterPwrLock(pBtCoexist); if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_display_coex_info(pBtCoexist); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_display_coex_info(pBtCoexist); } +#endif halbtcoutsrc_ExitPwrLock(pBtCoexist); @@ -3707,24 +4286,32 @@ void EXhalbtcoutsrc_DisplayAntDetection(PBTC_COEXIST pBtCoexist) halbtcoutsrc_LeaveLowPower(pBtCoexist); if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723B if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_display_ant_detection(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_display_ant_detection(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_display_ant_detection(pBtCoexist); } +#endif halbtcoutsrc_NormalLowPower(pBtCoexist); } void ex_halbtcoutsrc_pta_off_on_notify(PBTC_COEXIST pBtCoexist, u8 bBTON) { +#ifdef CONFIG_RTL8812A if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_pta_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF); } +#endif } void EXhalbtcoutsrc_set_rfe_type(u8 type) @@ -3756,20 +4343,297 @@ void EXhalbtcoutsrc_switchband_notify(struct btc_coexist *pBtCoexist, u8 type) /* halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if(IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8822B if(pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_switchband_notify(pBtCoexist, type); else if(pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_switchband_notify(pBtCoexist, type); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_switchband_notify(pBtCoexist, type); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_switchband_notify(pBtCoexist, type); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } +u8 EXhalbtcoutsrc_rate_id_to_btc_rate_id(u8 rate_id) +{ + u8 btc_rate_id = BTC_UNKNOWN; + + switch (rate_id) { + /* CCK rates */ + case DESC_RATE1M: + btc_rate_id = BTC_CCK_1; + break; + case DESC_RATE2M: + btc_rate_id = BTC_CCK_2; + break; + case DESC_RATE5_5M: + btc_rate_id = BTC_CCK_5_5; + break; + case DESC_RATE11M: + btc_rate_id = BTC_CCK_11; + break; + + /* OFDM rates */ + case DESC_RATE6M: + btc_rate_id = BTC_OFDM_6; + break; + case DESC_RATE9M: + btc_rate_id = BTC_OFDM_9; + break; + case DESC_RATE12M: + btc_rate_id = BTC_OFDM_12; + break; + case DESC_RATE18M: + btc_rate_id = BTC_OFDM_18; + break; + case DESC_RATE24M: + btc_rate_id = BTC_OFDM_24; + break; + case DESC_RATE36M: + btc_rate_id = BTC_OFDM_36; + break; + case DESC_RATE48M: + btc_rate_id = BTC_OFDM_48; + break; + case DESC_RATE54M: + btc_rate_id = BTC_OFDM_54; + break; + + /* MCS rates */ + case DESC_RATEMCS0: + btc_rate_id = BTC_MCS_0; + break; + case DESC_RATEMCS1: + btc_rate_id = BTC_MCS_1; + break; + case DESC_RATEMCS2: + btc_rate_id = BTC_MCS_2; + break; + case DESC_RATEMCS3: + btc_rate_id = BTC_MCS_3; + break; + case DESC_RATEMCS4: + btc_rate_id = BTC_MCS_4; + break; + case DESC_RATEMCS5: + btc_rate_id = BTC_MCS_5; + break; + case DESC_RATEMCS6: + btc_rate_id = BTC_MCS_6; + break; + case DESC_RATEMCS7: + btc_rate_id = BTC_MCS_7; + break; + case DESC_RATEMCS8: + btc_rate_id = BTC_MCS_8; + break; + case DESC_RATEMCS9: + btc_rate_id = BTC_MCS_9; + break; + case DESC_RATEMCS10: + btc_rate_id = BTC_MCS_10; + break; + case DESC_RATEMCS11: + btc_rate_id = BTC_MCS_11; + break; + case DESC_RATEMCS12: + btc_rate_id = BTC_MCS_12; + break; + case DESC_RATEMCS13: + btc_rate_id = BTC_MCS_13; + break; + case DESC_RATEMCS14: + btc_rate_id = BTC_MCS_14; + break; + case DESC_RATEMCS15: + btc_rate_id = BTC_MCS_15; + break; + case DESC_RATEMCS16: + btc_rate_id = BTC_MCS_16; + break; + case DESC_RATEMCS17: + btc_rate_id = BTC_MCS_17; + break; + case DESC_RATEMCS18: + btc_rate_id = BTC_MCS_18; + break; + case DESC_RATEMCS19: + btc_rate_id = BTC_MCS_19; + break; + case DESC_RATEMCS20: + btc_rate_id = BTC_MCS_20; + break; + case DESC_RATEMCS21: + btc_rate_id = BTC_MCS_21; + break; + case DESC_RATEMCS22: + btc_rate_id = BTC_MCS_22; + break; + case DESC_RATEMCS23: + btc_rate_id = BTC_MCS_23; + break; + case DESC_RATEMCS24: + btc_rate_id = BTC_MCS_24; + break; + case DESC_RATEMCS25: + btc_rate_id = BTC_MCS_25; + break; + case DESC_RATEMCS26: + btc_rate_id = BTC_MCS_26; + break; + case DESC_RATEMCS27: + btc_rate_id = BTC_MCS_27; + break; + case DESC_RATEMCS28: + btc_rate_id = BTC_MCS_28; + break; + case DESC_RATEMCS29: + btc_rate_id = BTC_MCS_29; + break; + case DESC_RATEMCS30: + btc_rate_id = BTC_MCS_30; + break; + case DESC_RATEMCS31: + btc_rate_id = BTC_MCS_31; + break; + + case DESC_RATEVHTSS1MCS0: + btc_rate_id = BTC_VHT_1SS_MCS_0; + break; + case DESC_RATEVHTSS1MCS1: + btc_rate_id = BTC_VHT_1SS_MCS_1; + break; + case DESC_RATEVHTSS1MCS2: + btc_rate_id = BTC_VHT_1SS_MCS_2; + break; + case DESC_RATEVHTSS1MCS3: + btc_rate_id = BTC_VHT_1SS_MCS_3; + break; + case DESC_RATEVHTSS1MCS4: + btc_rate_id = BTC_VHT_1SS_MCS_4; + break; + case DESC_RATEVHTSS1MCS5: + btc_rate_id = BTC_VHT_1SS_MCS_5; + break; + case DESC_RATEVHTSS1MCS6: + btc_rate_id = BTC_VHT_1SS_MCS_6; + break; + case DESC_RATEVHTSS1MCS7: + btc_rate_id = BTC_VHT_1SS_MCS_7; + break; + case DESC_RATEVHTSS1MCS8: + btc_rate_id = BTC_VHT_1SS_MCS_8; + break; + case DESC_RATEVHTSS1MCS9: + btc_rate_id = BTC_VHT_1SS_MCS_9; + break; + + case DESC_RATEVHTSS2MCS0: + btc_rate_id = BTC_VHT_2SS_MCS_0; + break; + case DESC_RATEVHTSS2MCS1: + btc_rate_id = BTC_VHT_2SS_MCS_1; + break; + case DESC_RATEVHTSS2MCS2: + btc_rate_id = BTC_VHT_2SS_MCS_2; + break; + case DESC_RATEVHTSS2MCS3: + btc_rate_id = BTC_VHT_2SS_MCS_3; + break; + case DESC_RATEVHTSS2MCS4: + btc_rate_id = BTC_VHT_2SS_MCS_4; + break; + case DESC_RATEVHTSS2MCS5: + btc_rate_id = BTC_VHT_2SS_MCS_5; + break; + case DESC_RATEVHTSS2MCS6: + btc_rate_id = BTC_VHT_2SS_MCS_6; + break; + case DESC_RATEVHTSS2MCS7: + btc_rate_id = BTC_VHT_2SS_MCS_7; + break; + case DESC_RATEVHTSS2MCS8: + btc_rate_id = BTC_VHT_2SS_MCS_8; + break; + case DESC_RATEVHTSS2MCS9: + btc_rate_id = BTC_VHT_2SS_MCS_9; + break; + + case DESC_RATEVHTSS3MCS0: + btc_rate_id = BTC_VHT_3SS_MCS_0; + break; + case DESC_RATEVHTSS3MCS1: + btc_rate_id = BTC_VHT_3SS_MCS_1; + break; + case DESC_RATEVHTSS3MCS2: + btc_rate_id = BTC_VHT_3SS_MCS_2; + break; + case DESC_RATEVHTSS3MCS3: + btc_rate_id = BTC_VHT_3SS_MCS_3; + break; + case DESC_RATEVHTSS3MCS4: + btc_rate_id = BTC_VHT_3SS_MCS_4; + break; + case DESC_RATEVHTSS3MCS5: + btc_rate_id = BTC_VHT_3SS_MCS_5; + break; + case DESC_RATEVHTSS3MCS6: + btc_rate_id = BTC_VHT_3SS_MCS_6; + break; + case DESC_RATEVHTSS3MCS7: + btc_rate_id = BTC_VHT_3SS_MCS_7; + break; + case DESC_RATEVHTSS3MCS8: + btc_rate_id = BTC_VHT_3SS_MCS_8; + break; + case DESC_RATEVHTSS3MCS9: + btc_rate_id = BTC_VHT_3SS_MCS_9; + break; + + case DESC_RATEVHTSS4MCS0: + btc_rate_id = BTC_VHT_4SS_MCS_0; + break; + case DESC_RATEVHTSS4MCS1: + btc_rate_id = BTC_VHT_4SS_MCS_1; + break; + case DESC_RATEVHTSS4MCS2: + btc_rate_id = BTC_VHT_4SS_MCS_2; + break; + case DESC_RATEVHTSS4MCS3: + btc_rate_id = BTC_VHT_4SS_MCS_3; + break; + case DESC_RATEVHTSS4MCS4: + btc_rate_id = BTC_VHT_4SS_MCS_4; + break; + case DESC_RATEVHTSS4MCS5: + btc_rate_id = BTC_VHT_4SS_MCS_5; + break; + case DESC_RATEVHTSS4MCS6: + btc_rate_id = BTC_VHT_4SS_MCS_6; + break; + case DESC_RATEVHTSS4MCS7: + btc_rate_id = BTC_VHT_4SS_MCS_7; + break; + case DESC_RATEVHTSS4MCS8: + btc_rate_id = BTC_VHT_4SS_MCS_8; + break; + case DESC_RATEVHTSS4MCS9: + btc_rate_id = BTC_VHT_4SS_MCS_9; + break; + } + + return btc_rate_id; +} + static void halbt_init_hw_config92C(PADAPTER padapter) { PHAL_DATA_TYPE pHalData; @@ -3883,10 +4747,6 @@ u8 hal_btcoex_Initialize(PADAPTER padapter) _rtw_memset(&GLBtCoexist, 0, sizeof(GLBtCoexist)); - hal_btcoex_SetBTCoexist(padapter, rtw_btcoex_get_bt_coexist(padapter)); - hal_btcoex_SetChipType(padapter, rtw_btcoex_get_chip_type(padapter)); - hal_btcoex_SetPgAntNum(padapter, rtw_btcoex_get_pg_ant_num(padapter)); - ret = EXhalbtcoutsrc_InitlizeVariables((void *)padapter); return ret; @@ -3897,6 +4757,15 @@ void hal_btcoex_PowerOnSetting(PADAPTER padapter) EXhalbtcoutsrc_PowerOnSetting(&GLBtCoexist); } +void hal_btcoex_AntInfoSetting(PADAPTER padapter) +{ + hal_btcoex_SetBTCoexist(padapter, rtw_btcoex_get_bt_coexist(padapter)); + hal_btcoex_SetChipType(padapter, rtw_btcoex_get_chip_type(padapter)); + hal_btcoex_SetPgAntNum(padapter, rtw_btcoex_get_pg_ant_num(padapter)); + + EXhalbtcoutsrc_AntInfoSetting(padapter); +} + void hal_btcoex_PowerOffSetting(PADAPTER padapter) { /* Clear the WiFi on/off bit in scoreboard reg. if necessary */ @@ -3936,7 +4805,25 @@ void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type) void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action) { - EXhalbtcoutsrc_connect_notify(&GLBtCoexist, action); + u8 assoType = 0; + u8 is_5g_band = _FALSE; + + is_5g_band = (padapter->mlmeextpriv.cur_channel > 14) ? _TRUE : _FALSE; + + if (action == _TRUE) { + if (is_5g_band == _TRUE) + assoType = BTC_ASSOCIATE_5G_START; + else + assoType = BTC_ASSOCIATE_START; + } + else { + if (is_5g_band == _TRUE) + assoType = BTC_ASSOCIATE_5G_FINISH; + else + assoType = BTC_ASSOCIATE_FINISH; + } + + EXhalbtcoutsrc_connect_notify(&GLBtCoexist, assoType); } void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus) @@ -3967,7 +4854,7 @@ void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) u8 extid, status, len, seq; - if (!GLBtcBtMpRptWait) + if (GLBtcBtMpRptWait == _FALSE) return; if ((length < 3) || (!tmpBuf)) @@ -3977,28 +4864,32 @@ void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) /* not response from BT FW then exit*/ switch (extid) { case C2H_WIFI_FW_ACTIVE_RSP: - GLBtcBtMpRptWiFiOK = 1; - return; + GLBtcBtMpRptWiFiOK = _TRUE; + break; case C2H_TRIG_BY_BT_FW: - _cancel_timer_ex(&GLBtcBtMpOperTimer); - GLBtcBtMpRptWait = 0; - GLBtcBtMpRptBTOK = 1; + GLBtcBtMpRptBTOK = _TRUE; + + status = tmpBuf[1] & 0xF; + len = length - 3; + seq = tmpBuf[2] >> 4; + + GLBtcBtMpRptSeq = seq; + GLBtcBtMpRptStatus = status; + _rtw_memcpy(GLBtcBtMpRptRsp, tmpBuf + 3, len); + GLBtcBtMpRptRspSize = len; + break; default: return; } - status = tmpBuf[1] & 0xF; - len = length - 3; - seq = tmpBuf[2] >> 4; - - GLBtcBtMpRptSeq = seq; - GLBtcBtMpRptStatus = status; - _rtw_memcpy(GLBtcBtMpRptRsp, tmpBuf + 3, len); - GLBtcBtMpRptRspSize = len; - _rtw_up_sema(&GLBtcBtMpRptSema); + if ((GLBtcBtMpRptWiFiOK == _TRUE) && (GLBtcBtMpRptBTOK == _TRUE)) { + GLBtcBtMpRptWait = _FALSE; + _cancel_timer_ex(&GLBtcBtMpOperTimer); + _rtw_up_sema(&GLBtcBtMpRptSema); + } } void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state) @@ -4565,4 +5456,14 @@ void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type) break; } } + +void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length) +{ + EXhalbtcoutsrc_WlFwDbgInfoNotify(&GLBtCoexist, tmpBuf, length); +} + +void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id) +{ + EXhalbtcoutsrc_rx_rate_change_notify(&GLBtCoexist, is_data_frame, EXhalbtcoutsrc_rate_id_to_btc_rate_id(rate_id)); +} #endif /* CONFIG_BT_COEXIST */ diff --git a/hal/hal_btcoex_wifionly.c b/hal/hal_btcoex_wifionly.c index 1abfeb0..8201513 100644 --- a/hal/hal_btcoex_wifionly.c +++ b/hal/hal_btcoex_wifionly.c @@ -12,9 +12,12 @@ * more details. * *****************************************************************************/ -#include "btc/mp_precomp.h" #include +#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1) + +#include "btc/mp_precomp.h" + struct wifi_only_cfg GLBtCoexistWifiOnly; void halwifionly_write1byte(PVOID pwifionlyContext, u32 RegAddr, u8 Data) @@ -85,7 +88,7 @@ void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMa rtw_write8(Adapter, regAddr, data); } -void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data) { struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; PADAPTER Adapter = pwifionlycfg->Adapter; @@ -109,10 +112,16 @@ void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter) if (pHalData->current_band_type == BAND_ON_5G) is_5g = _TRUE; - if (IS_HARDWARE_TYPE_8822B(padapter)) + if (IS_HARDWARE_TYPE_8822B(padapter)) { +#ifdef CONFIG_RTL8822B ex_hal8822b_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g); +#endif + } + +#ifdef CONFIG_RTL8821C else if (IS_HARDWARE_TYPE_8821C(padapter)) ex_hal8821c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g); +#endif } void hal_btcoex_wifionly_scan_notify(PADAPTER padapter) @@ -123,22 +132,37 @@ void hal_btcoex_wifionly_scan_notify(PADAPTER padapter) if (pHalData->current_band_type == BAND_ON_5G) is_5g = _TRUE; - if (IS_HARDWARE_TYPE_8822B(padapter)) + if (IS_HARDWARE_TYPE_8822B(padapter)) { +#ifdef CONFIG_RTL8822B ex_hal8822b_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g); +#endif + } + +#ifdef CONFIG_RTL8821C else if (IS_HARDWARE_TYPE_8821C(padapter)) ex_hal8821c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g); +#endif } void hal_btcoex_wifionly_hw_config(PADAPTER padapter) { struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly; - if (IS_HARDWARE_TYPE_8723B(padapter)) + if (IS_HARDWARE_TYPE_8723B(padapter)) { +#ifdef CONFIG_RTL8723B ex_hal8723b_wifi_only_hw_config(pwifionlycfg); +#endif + } + +#ifdef CONFIG_RTL8822B else if (IS_HARDWARE_TYPE_8822B(padapter)) ex_hal8822b_wifi_only_hw_config(pwifionlycfg); +#endif + +#ifdef CONFIG_RTL8821C else if (IS_HARDWARE_TYPE_8821C(padapter)) ex_hal8821c_wifi_only_hw_config(pwifionlycfg); +#endif } void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter) @@ -162,9 +186,19 @@ void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter) #endif pwifionly_haldata->customer_id = CUSTOMER_NORMAL; +} + +void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter) +{ + struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly; + struct wifi_only_haldata *pwifionly_haldata = &pwifionlycfg->haldata_info; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + pwifionly_haldata->efuse_pg_antnum = pHalData->EEPROMBluetoothAntNum; pwifionly_haldata->efuse_pg_antpath = pHalData->ant_path; pwifionly_haldata->rfe_type = pHalData->rfe_type; pwifionly_haldata->ant_div_cfg = pHalData->AntDivCfg; } +#endif + diff --git a/hal/hal_com.c b/hal/hal_com.c index faf9617..c3376b0 100644 --- a/hal/hal_com.c +++ b/hal/hal_com.c @@ -47,7 +47,7 @@ void rtw_hal_move_sta_gk_to_dk(_adapter *adapter) int cam_id, index = 0; u8 *addr = NULL; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (!MLME_IS_STA(adapter)) return; addr = get_bssid(pmlmepriv); @@ -300,7 +300,7 @@ void hal_com_config_channel_plan( /* cancel hw_alpha2 because chplan is specified by sw_chplan*/ country_ent = NULL; chplan = sw_chplan; - } else if (sw_chplan != RTW_CHPLAN_MAX) + } else if (sw_chplan != RTW_CHPLAN_UNSPECIFIED) RTW_PRINT("%s unsupported sw_chplan:0x%02X\n", __func__, sw_chplan); done: @@ -1129,7 +1129,7 @@ void rtw_hal_dump_macaddr(void *sel, _adapter *adapter) for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if (iface) { - rtw_hal_get_macaddr_port(iface, mac_addr); + rtw_hal_get_hwreg(iface, HW_VAR_MAC_ADDR, mac_addr); RTW_PRINT_SEL(sel, ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", ADPT_ARG(iface), iface->hw_port, MAC_ARG(mac_addr)); } @@ -1137,12 +1137,58 @@ void rtw_hal_dump_macaddr(void *sel, _adapter *adapter) #endif } -void rtw_restore_mac_addr(_adapter *adapter) +#ifdef RTW_HALMAC +void rtw_hal_hw_port_enable(_adapter *adapter) +{ +#if 1 + u8 port_enable = _TRUE; + + rtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable); +#else + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rtw_halmac_bcn_ctrl bcn_ctrl; + + _rtw_memset(&bcn_ctrl, 0, sizeof(struct rtw_halmac_bcn_ctrl)); + bcn_ctrl.enable_bcn = 1; + bcn_ctrl.rx_bssid_fit = 1; + bcn_ctrl.rxbcn_rpt = 1; + + /*rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, + struct rtw_halmac_bcn_ctrl *bcn_ctrl)*/ + if (rtw_halmac_set_bcn_ctrl(dvobj, get_hw_port(adapter), &bcn_ctrl) == -1) { + RTW_ERR(ADPT_FMT" - hw port(%d) enable fail!!\n", ADPT_ARG(adapter), get_hw_port(adapter)); + rtw_warn_on(1); + } +#endif +} +void rtw_hal_hw_port_disable(_adapter *adapter) +{ + u8 port_enable = _FALSE; + + rtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable); +} + +void rtw_restore_hw_port_cfg(_adapter *adapter) { #ifdef CONFIG_MI_WITH_MBSSID_CAM + +#else + int i; _adapter *iface; struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) + rtw_hal_hw_port_enable(iface); + } +#endif +} +#endif + +void rtw_restore_mac_addr(_adapter *adapter) +{ +#ifdef CONFIG_MI_WITH_MBSSID_CAM rtw_mbid_cam_restore(adapter); #else int i; @@ -1152,7 +1198,7 @@ void rtw_restore_mac_addr(_adapter *adapter) for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if (iface) - rtw_hal_set_macaddr_port(iface, adapter_mac_addr(iface)); + rtw_hal_set_hwreg(iface, HW_VAR_MAC_ADDR, adapter_mac_addr(iface)); } #endif if (1) @@ -1166,13 +1212,8 @@ void rtw_init_hal_com_default_value(PADAPTER Adapter) pHalData->AntDetection = 1; pHalData->antenna_test = _FALSE; - pHalData->u1ForcedIgiLb = regsty->force_igi_lb; pHalData->RegIQKFWOffload = regsty->iqk_fw_offload; - -#ifdef CONFIG_CHNL_LOAD_MAGT - if (!pHalData->clm_period) - pHalData->clm_period = (SURVEY_TO - 5)*1000/4; /* CLM_period ; 4us per unit */ -#endif + pHalData->ch_switch_offload = regsty->ch_switch_offload; } #ifdef CONFIG_FW_C2H_REG @@ -1214,7 +1255,7 @@ s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf) for (i = 0; i < C2H_PLEN_88XX(buf); i++) *(C2H_PAYLOAD_88XX(buf) + i) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i); - RTW_DBG_DUMP("payload:\n", C2H_PAYLOAD_88XX(buf), C2H_PLEN_88XX(buf)); + RTW_DBG_DUMP("payload: ", C2H_PAYLOAD_88XX(buf), C2H_PLEN_88XX(buf)); ret = _SUCCESS; @@ -1461,6 +1502,19 @@ int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len) RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i)); } + #ifdef CONFIG_RTL8188F + if (IS_8188F(hal_data->version_id)) { + #define GET_C2H_MAC_HIDDEN_RPT_IRV(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 4) + u8 irv = GET_C2H_MAC_HIDDEN_RPT_IRV(data); + + if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) + RTW_PRINT("irv:0x%x\n", irv); + + if(irv != 0xf) + hal_data->version_id.CUTVersion = irv; + } + #endif + ret = _SUCCESS; exit: @@ -1473,7 +1527,7 @@ int hal_read_mac_hidden_rpt(_adapter *adapter) int ret = _FAIL; int ret_fwdl; u8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN] = {0}; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); u32 cnt = 0; u32 timeout_ms = 800; u32 min_cnt = 10; @@ -1784,22 +1838,191 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs) } #endif /* CONFIG_RTW_CUSTOMER_STR */ -u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta) +#ifdef RTW_PER_CMD_SUPPORT_FW +#define H2C_REQ_PER_RPT_LEN 5 +#define SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) +#define SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd + 1, 0, 32, __Value) + +u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid, + u8 rpt_type, u32 macid_bitmap) +{ + u8 ret = _FAIL; + u8 cmd_buf[H2C_REQ_PER_RPT_LEN] = {0}; + + SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(cmd_buf, group_macid); + SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(cmd_buf, rpt_type); + SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(cmd_buf, macid_bitmap); + + ret = rtw_hal_fill_h2c_cmd(adapter, + H2C_REQ_PER_RPT, + H2C_REQ_PER_RPT_LEN, + cmd_buf); + return ret; +} + +#define GET_C2H_PER_RATE_RPT_TYPE0_MACID0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE0_PER0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE0_RATE0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE0_BW0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2) +#define GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(_data) LE_BITS_TO_2BYTE(((u8 *)(_data)) + 4, 0, 16) +#define GET_C2H_PER_RATE_RPT_TYPE0_MACID1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE0_PER1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE0_RATE1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE0_BW1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 2) +#define GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(_data) LE_BITS_TO_2BYTE(((u8 *)(_data)) + 10, 0, 16) + +#define GET_C2H_PER_RATE_RPT_TYPE1_MACID0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_PER0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_RATE0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_BW0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2) +#define GET_C2H_PER_RATE_RPT_TYPE1_MACID1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_PER1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_RATE1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_BW1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 2) +#define GET_C2H_PER_RATE_RPT_TYPE1_MACID2(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_PER2(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_RATE2(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 10, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_BW2(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 11, 0, 2) + +static void per_rate_rpt_update(_adapter *adapter, u8 mac_id, + u8 per, u8 rate, + u8 bw, u8 total_pkt) +{ +#ifdef CONFIG_RTW_MESH + rtw_ieee80211s_update_metric(adapter, mac_id, + per, rate, + bw, total_pkt); +#endif +} + +int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len) +{ + /* Now only consider type0, since it covers all params in type1 + * type0: mac_id, per, rate, bw, total_pkt + * type1: mac_id, per, rate, bw + */ + u8 mac_id[2] = {0}, per[2] = {0}, rate[2] = {0}, bw[2] = {0}; + u16 total_pkt[2] = {0}; + int ret = _FAIL, i, macid_cnt = 0; + + /* type0: + * 1 macid includes 6 bytes info + 1 byte 0xff + * 2 macid includes 2*6 bytes info + */ + if (!(len == 7 || len == 12)) { + RTW_WARN("%s len(%u) != 7 or 12\n", __FUNCTION__, len); + goto exit; + } + + macid_cnt++; + mac_id[0] = GET_C2H_PER_RATE_RPT_TYPE0_MACID0(data); + per[0] = GET_C2H_PER_RATE_RPT_TYPE0_PER0(data); + rate[0] = GET_C2H_PER_RATE_RPT_TYPE0_RATE0(data); + bw[0] = GET_C2H_PER_RATE_RPT_TYPE0_BW0(data); + total_pkt[0] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(data); + + mac_id[1] = GET_C2H_PER_RATE_RPT_TYPE0_MACID1(data); + /* 0xff means no report anymore */ + if (mac_id[1] == 0xff) + goto update_per; + if (len != 12) { + RTW_WARN("%s incorrect format\n", __FUNCTION__); + goto exit; + } + macid_cnt++; + per[1] = GET_C2H_PER_RATE_RPT_TYPE0_PER1(data); + rate[1] = GET_C2H_PER_RATE_RPT_TYPE0_RATE1(data); + bw[1] = GET_C2H_PER_RATE_RPT_TYPE0_BW1(data); + total_pkt[1] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(data); + +update_per: + for (i = 0; i < macid_cnt; i++) { + RTW_DBG("[%s] type0 rpt[%d]: macid = %u, per = %u, " + "rate = %u, bw = %u, total_pkt = %u\n", + __FUNCTION__, i, mac_id[i], per[i], + rate[i], bw[i], total_pkt[i]); + per_rate_rpt_update(adapter, mac_id[i], + per[i], rate[i], + bw[i], total_pkt[i]); + } + ret = _SUCCESS; +exit: + return ret; +} +#endif /* RTW_PER_CMD_SUPPORT_FW */ + +void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta) +{ + u8 w_set = 0; + + if (psta->wireless_mode & WIRELESS_11B) + w_set |= WIRELESS_CCK; + + if ((psta->wireless_mode & WIRELESS_11G) || (psta->wireless_mode & WIRELESS_11A)) + w_set |= WIRELESS_OFDM; + + if (psta->wireless_mode & WIRELESS_11_24N) + w_set |= WIRELESS_HT; + + if ((psta->wireless_mode & WIRELESS_11AC) || (psta->wireless_mode & WIRELESS_11_5N)) + w_set |= WIRELESS_VHT; + + psta->cmn.support_wireless_set = w_set; +} + +void rtw_hal_update_sta_mimo_type(_adapter *adapter, struct sta_info *psta) { -#ifdef CONFIG_GET_RAID_BY_DRV /*Just for 8188E now*/ - if (IS_NEW_GENERATION_IC(adapter)) - return networktype_to_raid_ex(adapter, psta); + s8 tx_nss, rx_nss; + + tx_nss = rtw_get_sta_tx_nss(adapter, psta); + rx_nss = rtw_get_sta_rx_nss(adapter, psta); + if ((tx_nss == 1) && (rx_nss == 1)) + psta->cmn.mimo_type = RF_1T1R; + else if ((tx_nss == 1) && (rx_nss == 2)) + psta->cmn.mimo_type = RF_1T2R; + else if ((tx_nss == 2) && (rx_nss == 2)) + psta->cmn.mimo_type = RF_2T2R; + else if ((tx_nss == 2) && (rx_nss == 3)) + psta->cmn.mimo_type = RF_2T3R; + else if ((tx_nss == 2) && (rx_nss == 4)) + psta->cmn.mimo_type = RF_2T4R; + else if ((tx_nss == 3) && (rx_nss == 3)) + psta->cmn.mimo_type = RF_3T3R; + else if ((tx_nss == 3) && (rx_nss == 4)) + psta->cmn.mimo_type = RF_3T4R; + else if ((tx_nss == 4) && (rx_nss == 4)) + psta->cmn.mimo_type = RF_4T4R; else - return networktype_to_raid(adapter, psta); -#else - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - u8 bw; + rtw_warn_on(1); - bw = rtw_get_tx_bw_mode(adapter, psta); + RTW_INFO("STA - MAC_ID:%d, Tx - %d SS, Rx - %d SS\n", + psta->cmn.mac_id, tx_nss, rx_nss); +} - return phydm_rate_id_mapping(&pHalData->odmpriv, psta->wireless_mode, pHalData->rf_type, bw); +void rtw_hal_update_sta_smps_cap(_adapter *adapter, struct sta_info *psta) +{ + /*Spatial Multiplexing Power Save*/ +#if 0 + if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + #ifdef CONFIG_80211N_HT + if (psta->htpriv.ht_option) { + if (psta->htpriv.smps_cap == 0) + psta->cmn.sm_ps = SM_PS_STATIC; + else if (psta->htpriv.smps_cap == 1) + psta->cmn.sm_ps = SM_PS_DYNAMIC; + else + psta->cmn.sm_ps = SM_PS_DISABLE; + } + #endif /* CONFIG_80211N_HT */ + } else #endif + psta->cmn.sm_ps = SM_PS_DISABLE; + + RTW_INFO("STA - MAC_ID:%d, SM_PS %d\n", + psta->cmn.mac_id, psta->cmn.sm_ps); } + u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type) { @@ -1819,13 +2042,11 @@ void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta) { struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); u8 i, rf_type, tx_nss; - u64 tx_ra_bitmap; + u64 tx_ra_bitmap = 0; if (psta == NULL) return; - tx_ra_bitmap = 0; - /* b/g mode ra_bitmap */ for (i = 0; i < sizeof(psta->bssrateset); i++) { if (psta->bssrateset[i]) @@ -1856,10 +2077,17 @@ void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta) tx_ra_bitmap |= (rtw_ht_mcs_set_to_bitmap(psta->htpriv.ht_cap.supp_mcs_set, tx_nss) << 12); } #endif /* CONFIG_80211N_HT */ - psta->ra_mask = tx_ra_bitmap; + psta->cmn.ra_info.ramask = tx_ra_bitmap; psta->init_rate = get_highest_rate_idx(tx_ra_bitmap) & 0x3f; } +void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta) +{ + rtw_hal_update_sta_mimo_type(padapter, psta); + rtw_hal_update_sta_smps_cap(padapter, psta); + rtw_hal_update_sta_rate_mask(padapter, psta); +} + #ifndef SEC_CAM_ACCESS_TIMEOUT_MS #define SEC_CAM_ACCESS_TIMEOUT_MS 200 #endif @@ -1873,7 +2101,7 @@ u32 rtw_sec_read_cam(_adapter *adapter, u8 addr) _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex; u32 rdata; u32 cnt = 0; - u32 start = 0, end = 0; + systime start = 0, end = 0; u8 timeout = 0; u8 sr = 0; @@ -1915,7 +2143,7 @@ void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata) { _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex; u32 cnt = 0; - u32 start = 0, end = 0; + systime start = 0, end = 0; u8 timeout = 0; u8 sr = 0; @@ -2334,10 +2562,12 @@ int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name, _adapter *adapter) iface = dvobj->padapters[iface_id]; if (iface) { - if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) + if (MLME_IS_STA(iface)) RTW_PRINT_SEL(sel, "ROLE:%s\n", "STA"); - else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE) + else if (MLME_IS_AP(iface)) RTW_PRINT_SEL(sel, "ROLE:%s\n", "AP"); + else if (MLME_IS_MESH(iface)) + RTW_PRINT_SEL(sel, "ROLE:%s\n", "MESH"); else RTW_PRINT_SEL(sel, "ROLE:%s\n", "NONE"); } @@ -2422,10 +2652,10 @@ static void enable_mbssid_cam(_adapter *adapter) { u8 max_cam_id = rtw_get_max_mbid_cam_id(adapter); /*enable MBSSID*/ - rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR) | RCR_ENMBID); + rtw_hal_rcr_add(adapter, RCR_ENMBID); if (max_cam_id != INVALID_CAM_ID) { rtw_write8(adapter, REG_MBID_NUM, - ((rtw_read8(adapter, REG_MBID_NUM) & 0xF8) | (max_cam_id & 0x07))); + ((rtw_read8(adapter, REG_MBID_NUM) & 0xF8) | ((max_cam_id -1) & 0x07))); } } void rtw_mbid_cam_restore(_adapter *adapter) @@ -2510,10 +2740,19 @@ void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr) write_mbssid_cam(adapter, entry_id, mac_addr); } +#ifdef CONFIG_SWTIMER_BASED_TXBCN +u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval) +{ + if (adapter_to_dvobj(adapter)->inter_bcn_space != bcn_interval) + return adapter_to_dvobj(adapter)->inter_bcn_space; + else + return bcn_interval; +} +#endif/*CONFIG_SWTIMER_BASED_TXBCN*/ #endif/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/ -void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val) +static void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val) { u8 idx = 0; u32 reg_macid = 0; @@ -2524,6 +2763,9 @@ void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val) RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", __func__, ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(val)); +#ifdef RTW_HALMAC + rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), adapter->hw_port, val); +#else /* !RTW_HALMAC */ switch (adapter->hw_port) { case HW_PORT0: default: @@ -2547,8 +2789,10 @@ void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val) for (idx = 0; idx < 6; idx++) rtw_write8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx), val[idx]); +#endif /* !RTW_HALMAC */ } -void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr) + +static void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr) { u8 idx = 0; u32 reg_macid = 0; @@ -2557,6 +2801,9 @@ void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr) return; _rtw_memset(mac_addr, 0, ETH_ALEN); +#ifdef RTW_HALMAC + rtw_halmac_get_mac_address(adapter_to_dvobj(adapter), adapter->hw_port, mac_addr); +#else /* !RTW_HALMAC */ switch (adapter->hw_port) { case HW_PORT0: default: @@ -2580,13 +2827,17 @@ void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr) for (idx = 0; idx < 6; idx++) mac_addr[idx] = rtw_read8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx)); +#endif /* !RTW_HALMAC */ RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", __func__, ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(mac_addr)); } -void rtw_hal_set_bssid(_adapter *adapter, u8 *val) +static void rtw_hal_set_bssid(_adapter *adapter, u8 *val) { +#ifdef RTW_HALMAC + rtw_halmac_set_bssid(adapter_to_dvobj(adapter), adapter->hw_port, val); +#else /* !RTW_HALMAC */ u8 idx = 0; u32 reg_bssid = 0; @@ -2613,12 +2864,180 @@ void rtw_hal_set_bssid(_adapter *adapter, u8 *val) for (idx = 0 ; idx < 6; idx++) rtw_write8(adapter, (reg_bssid + idx), val[idx]); +#endif /* !RTW_HALMAC */ RTW_INFO("%s "ADPT_FMT"- hw port -%d BSSID: "MAC_FMT"\n", __func__, ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(val)); } -void rtw_hal_get_msr(_adapter *adapter, u8 *net_type) +static inline u8 hw_var_rcr_config(_adapter *adapter, u32 rcr) +{ + int err; + + err = rtw_write32(adapter, REG_RCR, rcr); + if (err == _SUCCESS) + GET_HAL_DATA(adapter)->ReceiveConfig = rcr; + return err; +} + +static inline u8 hw_var_rcr_get(_adapter *adapter, u32 *rcr) +{ + u32 v32; + + v32 = rtw_read32(adapter, REG_RCR); + if (rcr) + *rcr = v32; + GET_HAL_DATA(adapter)->ReceiveConfig = v32; + return _SUCCESS; +} + +/* only check SW RCR variable */ +inline u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit) +{ + PHAL_DATA_TYPE hal; + u32 rcr; + + hal = GET_HAL_DATA(adapter); + + rcr = hal->ReceiveConfig; + if ((rcr & check_bit) == check_bit) + return 1; + + return 0; +} + +inline u8 rtw_hal_rcr_add(_adapter *adapter, u32 add) +{ + PHAL_DATA_TYPE hal; + u32 rcr; + u8 ret = _SUCCESS; + + hal = GET_HAL_DATA(adapter); + + rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr); + rcr |= add; + if (rcr != hal->ReceiveConfig) + ret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr); + + return ret; +} + +inline u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear) +{ + PHAL_DATA_TYPE hal; + u32 rcr; + u8 ret = _SUCCESS; + + hal = GET_HAL_DATA(adapter); + + rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr); + rcr &= ~clear; + if (rcr != hal->ReceiveConfig) + ret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr); + + return ret; +} + +void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u32 rcr, rcr_new; + struct mi_state mstate, mstate_s; + + rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr); + rcr_new = rcr; + +#ifdef CONFIG_MI_WITH_MBSSID_CAM + rcr_new &= ~(RCR_CBSSID_BCN | RCR_CBSSID_DATA); +#else + rtw_mi_status_no_self(adapter, &mstate); + rtw_mi_status_no_others(adapter, &mstate_s); + + /* only adjust parameters interested */ + switch (self_action) { + case MLME_SCAN_ENTER: + mstate_s.scan_num = 1; + mstate_s.scan_enter_num = 1; + break; + case MLME_SCAN_DONE: + mstate_s.scan_enter_num = 0; + break; +#ifdef CONFIG_TDLS + case MLME_TDLS_LINKED: + mstate_s.ld_tdls_num = 1; + break; + case MLME_TDLS_NOLINK: + mstate_s.ld_tdls_num = 0; + break; +#endif +#ifdef CONFIG_AP_MODE + case MLME_AP_STARTED: + mstate_s.ap_num = 1; + break; + case MLME_AP_STOPPED: + mstate_s.ap_num = 0; + mstate_s.ld_ap_num = 0; + break; +#endif +#ifdef CONFIG_RTW_MESH + case MLME_MESH_STARTED: + mstate_s.mesh_num = 1; + break; + case MLME_MESH_STOPPED: + mstate_s.mesh_num = 0; + mstate_s.ld_mesh_num = 0; + break; +#endif + case MLME_ACTION_NONE: + case MLME_STA_CONNECTING: + case MLME_ADHOC_STARTED: + /* caller without effect of decision */ + break; + default: + rtw_warn_on(1); + }; + + rtw_mi_status_merge(&mstate, &mstate_s); + + if (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate) || MSTATE_TDLS_LD_NUM(&mstate) + #ifdef CONFIG_FIND_BEST_CHANNEL + || MSTATE_SCAN_ENTER_NUM(&mstate) + #endif + || hal_data->in_cta_test + ) + rcr_new &= ~RCR_CBSSID_DATA; + else + rcr_new |= RCR_CBSSID_DATA; + + if ((MSTATE_AP_NUM(&mstate) && adapter->registrypriv.wifi_spec) /* for 11n Logo 4.2.31/4.2.32 */ + || MSTATE_MESH_NUM(&mstate) + || MSTATE_SCAN_ENTER_NUM(&mstate) + || hal_data->in_cta_test + ) + rcr_new &= ~RCR_CBSSID_BCN; + else + rcr_new |= RCR_CBSSID_BCN; +#endif /* CONFIG_MI_WITH_MBSSID_CAM */ + + if (rcr != rcr_new) + rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_new); +} + +static void hw_var_set_rcr_am(_adapter *adapter, u8 enable) +{ + u32 rcr = RCR_AM; + + if (enable) + rtw_hal_rcr_add(adapter, rcr); + else + rtw_hal_rcr_clear(adapter, rcr); +} + +static void rtw_hal_get_msr(_adapter *adapter, u8 *net_type) { +#ifdef RTW_HALMAC + rtw_halmac_get_network_type(adapter_to_dvobj(adapter), + adapter->hw_port, net_type); +#else /* !RTW_HALMAC */ switch (adapter->hw_port) { case HW_PORT0: /*REG_CR - BIT[17:16]-Network Type for port 1*/ @@ -2648,20 +3067,35 @@ void rtw_hal_get_msr(_adapter *adapter, u8 *net_type) rtw_warn_on(1); break; } +#endif /* !RTW_HALMAC */ } -void rtw_hal_set_msr(_adapter *adapter, u8 net_type) +#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) /*For 2 hw ports - 88E/92E/8812/8821/8723B*/ +static u8 rtw_hal_net_type_decision(_adapter *adapter, u8 net_type) +{ + if ((adapter->hw_port == HW_PORT0) && (rtw_get_mbid_cam_entry_num(adapter))) { + if (net_type != _HW_STATE_NOLINK_) + return _HW_STATE_AP_; + } + return net_type; +} +#endif +static void rtw_hal_set_msr(_adapter *adapter, u8 net_type) { +#ifdef RTW_HALMAC + #if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) + net_type = rtw_hal_net_type_decision(adapter, net_type); + #endif + rtw_halmac_set_network_type(adapter_to_dvobj(adapter), + adapter->hw_port, net_type); +#else /* !RTW_HALMAC */ u8 val8 = 0; switch (adapter->hw_port) { case HW_PORT0: -#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) /*For 2 hw ports - 88E/92E/8812/8821/8723B*/ - if (rtw_get_mbid_cam_entry_num(adapter)) { - if (net_type != _HW_STATE_NOLINK_) - net_type = _HW_STATE_AP_; - } -#endif + #if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) + net_type = rtw_hal_net_type_decision(adapter, net_type); + #endif /*REG_CR - BIT[17:16]-Network Type for port 0*/ val8 = rtw_read8(adapter, MSR) & 0x0C; val8 |= net_type; @@ -2699,6 +3133,17 @@ void rtw_hal_set_msr(_adapter *adapter, u8 net_type) rtw_warn_on(1); break; } +#endif /* !RTW_HALMAC */ +} + +static void hw_var_set_bcn_interval(struct _ADAPTER *a, u16 interval) +{ +#ifdef RTW_HALMAC + rtw_halmac_set_bcn_interval(adapter_to_dvobj(a), a->hw_port, interval); +#else /* !RTW_HALMAC */ + RTW_ERR(FUNC_ADPT_FMT ": Not implemented yet!!\n", FUNC_ADPT_ARG(a)); + rtw_warn_on(1); +#endif /* !RTW_HALMAC */ } void hw_var_port_switch(_adapter *adapter) @@ -2917,6 +3362,7 @@ const char *const _h2c_msr_role_str[] = { "GO", "TDLS", "ADHOC", + "MESH", "INVALID", }; @@ -2951,7 +3397,7 @@ s32 rtw_set_default_port_id(_adapter *adapter) if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv)); if (psta) - ret = rtw_hal_set_default_port_id_cmd(adapter, psta->mac_id); + ret = rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id); } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { } else { @@ -2992,13 +3438,13 @@ void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state) u8 i; _rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA)); - _rtw_memcpy((&p2p_ps_para), &hal->p2p_ps_offload, sizeof(hal->p2p_ps_offload)); + _rtw_memcpy((&p2p_ps_para) , &hal->p2p_ps_offload , sizeof(hal->p2p_ps_offload)); (&p2p_ps_para)->p2p_port_id = adapter->hw_port; (&p2p_ps_para)->p2p_group = 0; psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); if (psta) { - (&p2p_ps_para)->p2p_macid = psta->mac_id; + (&p2p_ps_para)->p2p_macid = psta->cmn.mac_id; } else { if (p2p_ps_state != P2P_PS_DISABLE) { RTW_ERR("%s , psta was NULL\n", __func__); @@ -3010,7 +3456,7 @@ void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state) switch (p2p_ps_state) { case P2P_PS_DISABLE: RTW_INFO("P2P_PS_DISABLE\n"); - _rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA)); + _rtw_memset(&p2p_ps_para , 0, sizeof(HAL_P2P_PS_PARA)); break; case P2P_PS_ENABLE: @@ -3050,7 +3496,7 @@ void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state) /*RTW_INFO("%s , noa_duration_para = %d , noa_interval_para = %d , noa_start_time_para = %d , noa_count_para = %d\n" , __func__ , (&p2p_ps_para)->noa_duration_para , (&p2p_ps_para)->noa_interval_para , (&p2p_ps_para)->noa_start_time_para , (&p2p_ps_para)->noa_count_para);*/ - status = rtw_halmac_p2pps(adapter_to_dvobj(adapter), (&p2p_ps_para)); + status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para)); if (status == -1) RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__); } @@ -3091,11 +3537,11 @@ void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state) } if (p2p_ps_state != P2P_PS_ENABLE || (&p2p_ps_para)->noa_en == 0) { - status = rtw_halmac_p2pps(adapter_to_dvobj(adapter), (&p2p_ps_para)); + status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para)); if (status == -1) RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__); } - _rtw_memcpy(&hal->p2p_ps_offload, (&p2p_ps_para), sizeof(hal->p2p_ps_offload)); + _rtw_memcpy(&hal->p2p_ps_offload , (&p2p_ps_para) , sizeof(hal->p2p_ps_offload)); } #endif /* RTW_HALMAC */ @@ -3236,7 +3682,12 @@ void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable) * TODO: GPIO_8 multi function? */ - if (index == 13 || index == 14) + if ((index == 13 || index == 14) + #if defined(CONFIG_RTL8821A) && defined(CONFIG_SDIO_HCI) + /* 8821A's LED2 circuit(used by HW_LED strategy) needs enable WL GPIO control of GPIO[14:13], can't disable */ + && (!IS_HW_LED_STRATEGY(rtw_led_get_strategy(padapter)) || enable) + #endif + ) rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable)); } @@ -3292,6 +3743,41 @@ void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval) __FUNCTION__, index, outputval); } } +void rtw_hal_set_input_gpio(_adapter *padapter, u8 index) +{ + if (index <= 7) { + /* config GPIO mode */ + rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3, + rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index)); + + /* config GPIO Sel */ + /* 0: input */ + /* 1: output */ + rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2, + rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) & ~BIT(index)); + + } else if (index <= 15) { + /* 88C Series: */ + /* index: 11~8 transform to 3~0 */ + /* 8723 Series: */ + /* index: 12~8 transform to 4~0 */ + + index -= 8; + + /* config GPIO mode */ + rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3, + rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index)); + + /* config GPIO Sel */ + /* 0: input */ + /* 1: output */ + rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2, + rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) & ~BIT(index)); + } else + RTW_INFO("%s: invalid GPIO%d\n", __func__, index); + +} + #endif void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) @@ -3357,6 +3843,26 @@ void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc #endif /* CONFIG_WOWLAN */ } +#ifdef DBG_FW_DEBUG_MSG_PKT +void rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) +{ + struct hal_ops *pHalFunc = &padapter->hal_func; + u8 u1H2C_fw_dbg_msg_pkt_parm[H2C_FW_DBG_MSG_PKT_LEN] = {0}; + u8 ret = 0; + + + RTW_INFO("RsvdPageLoc: loc_fw_dbg_msg_pkt =%d\n", rsvdpageloc->loc_fw_dbg_msg_pkt); + + SET_H2CCMD_FW_DBG_MSG_PKT_EN(u1H2C_fw_dbg_msg_pkt_parm, 1); + SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(u1H2C_fw_dbg_msg_pkt_parm, rsvdpageloc->loc_fw_dbg_msg_pkt); + ret = rtw_hal_fill_h2c_cmd(padapter, + H2C_FW_DBG_MSG_PKT, + H2C_FW_DBG_MSG_PKT_LEN, + u1H2C_fw_dbg_msg_pkt_parm); + +} +#endif /*DBG_FW_DEBUG_MSG_PKT*/ + /*#define DBG_GET_RSVD_PAGE*/ int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size) @@ -3385,7 +3891,7 @@ int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, #else txbndy = rtw_read8(adapter, REG_TDECTRL + 1); - offset = (txbndy + page_offset) << 4; + offset = (txbndy + page_offset) * page_size / 8; count = (buffer_size / 8) + 1; rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x69); @@ -3421,7 +3927,7 @@ void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_nu if (page_num == 0) return; - RTW_PRINT_SEL(sel, "======= RSVG PAGE DUMP =======\n"); + RTW_PRINT_SEL(sel, "======= RSVD PAGE DUMP =======\n"); RTW_PRINT_SEL(sel, "page_offset:%d, page_num:%d\n", page_offset, page_num); rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); @@ -3431,7 +3937,7 @@ void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_nu if (buffer) { rtw_hal_get_rsvd_page(adapter, page_offset, page_num, buffer, buf_size); - _RTW_DUMP_SEL(sel, buffer, buf_size); + RTW_DUMP_SEL(sel, buffer, buf_size); rtw_vmfree(buffer, buf_size); } else RTW_PRINT_SEL(sel, "ERROR - rsvd_buf mem allocate failed\n"); @@ -3468,7 +3974,7 @@ void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), fifo_sel, fifo_addr, buff_size, buffer); if (buffer) { - _RTW_DUMP_SEL(sel, buffer, fifo_size); + RTW_DUMP_SEL(sel, buffer, fifo_size); rtw_vmfree(buffer, buff_size); } @@ -3556,12 +4062,12 @@ static u8 rtw_hal_pause_rx_dma(_adapter *adapter) } while (trycnt--); if (trycnt < 0) { - tmp = rtw_read16(adapter, REG_RXPKT_NUM + 3); + tmp = rtw_read16(adapter, REG_RXPKT_NUM + 2); RTW_PRINT("Stop RX DMA failed......\n"); - RTW_PRINT("%s, RXPKT_NUM: 0x%04x\n", - __func__, tmp); - tmp = rtw_read16(adapter, REG_RXPKT_NUM + 2); + RTW_PRINT("%s, RXPKT_NUM: 0x%02x\n", + __func__, ((tmp & 0xFF00) >> 8)); + if (tmp & BIT(3)) RTW_PRINT("%s, RX DMA has req\n", __func__); @@ -3650,12 +4156,12 @@ static u8 rtw_hal_check_wow_ctrl(_adapter *adapter, u8 chk_type) RTW_PRINT("%s REG_FE1IMR (reg120): 0x%x, REG_RXPKT_NUM(reg284): 0x%x\n", __func__, fe1_imr, rxpkt_num); while (((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN)) && trycnt > 1) { + rtw_msleep_os(20); fe1_imr = rtw_read32(adapter, REG_FE1IMR); rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM); RTW_PRINT("Loop index: %d :0x%x, 0x%x\n", trycnt, fe1_imr, rxpkt_num); trycnt--; - rtw_msleep_os(20); } if ((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN)) @@ -3744,7 +4250,7 @@ static void rtw_hal_fw_sync_cam_id(_adapter *adapter) int cam_id, index = 0; u8 *addr = NULL; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (!MLME_IS_STA(adapter)) return; addr = get_bssid(pmlmepriv); @@ -3770,90 +4276,24 @@ static void rtw_hal_fw_sync_cam_id(_adapter *adapter) rtw_write8(adapter, REG_SECCFG, 0xcc); } -static void rtw_dump_aoac_rpt(_adapter *adapter) +static void rtw_hal_update_gtk_offload_info(_adapter *adapter) { struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct security_priv *psecuritypriv = &adapter->securitypriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + u8 get_key[16]; + u8 gtk_id = 0, offset = 0, i = 0, sz = 0; + u64 replay_count = 0, tmp_iv_hdr = 0, pkt_pn = 0; - RTW_INFO_DUMP("[AOAC-RPT] IV -", paoac_rpt->iv, 8); - RTW_INFO_DUMP("[AOAC-RPT] Replay counter of EAPOL key - ", - paoac_rpt->replay_counter_eapol_key, 8); - RTW_INFO_DUMP("[AOAC-RPT] Group key - ", paoac_rpt->group_key, 32); - RTW_INFO("[AOAC-RPT] Key Index - %d\n", paoac_rpt->key_index); - RTW_INFO("[AOAC-RPT] Security Type - %d\n", paoac_rpt->security_type); -} - -static void rtw_hal_get_aoac_rpt(_adapter *adapter) -{ - struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); - struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; - u32 page_offset = 0, page_number = 0; - u32 page_size = 0, buf_size = 0; - u8 *buffer = NULL; - u8 i = 0, tmp = 0; - int ret = -1; - - /* read aoac report from rsvd page */ - page_offset = pwrctl->wowlan_aoac_rpt_loc; - page_number = 1; - - rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); - buf_size = page_size * page_number; - - buffer = rtw_zvmalloc(buf_size); - - if (NULL == buffer) { - RTW_ERR("%s buffer allocate failed size(%d)\n", - __func__, buf_size); - return; - } - - RTW_INFO("Get AOAC Report from rsvd page_offset:%d\n", page_offset); - - ret = rtw_hal_get_rsvd_page(adapter, page_offset, - page_number, buffer, buf_size); - - if (ret == _FALSE) { - RTW_ERR("%s get aoac report failed\n", __func__); - rtw_warn_on(1); - goto _exit; - } - - _rtw_memset(paoac_rpt, 0, sizeof(struct aoac_report)); - _rtw_memcpy(paoac_rpt, buffer, sizeof(struct aoac_report)); - - for (i = 0 ; i < 4 ; i++) { - tmp = paoac_rpt->replay_counter_eapol_key[i]; - paoac_rpt->replay_counter_eapol_key[i] = - paoac_rpt->replay_counter_eapol_key[7 - i]; - paoac_rpt->replay_counter_eapol_key[7 - i] = tmp; - } - - /* rtw_dump_aoac_rpt(adapter); */ - -_exit: - if (buffer) - rtw_vmfree(buffer, buf_size); -} - -static void rtw_hal_update_gtk_offload_info(_adapter *adapter) -{ - struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); - struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct security_priv *psecuritypriv = &adapter->securitypriv; - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; - _irqL irqL; - u8 get_key[16]; - u8 gtk_id = 0, offset = 0; - u64 replay_count = 0; - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) - return; - - _rtw_memset(get_key, 0, sizeof(get_key)); - _rtw_memcpy(&replay_count, + if (!MLME_IS_STA(adapter)) + return; + + _rtw_memset(get_key, 0, sizeof(get_key)); + _rtw_memcpy(&replay_count, paoac_rpt->replay_counter_eapol_key, 8); /*read gtk key index*/ @@ -3900,11 +4340,21 @@ static void rtw_hal_update_gtk_offload_info(_adapter *adapter) &(paoac_rpt->group_key[offset]), RTW_TKIP_MIC_LEN); } - RTW_PRINT("GTK (%d) "KEY_FMT"\n", gtk_id, KEY_ARG(psecuritypriv->dot118021XGrpKey[gtk_id].skey)); } + /* Update broadcast RX IV */ + if (psecuritypriv->dot118021XGrpPrivacy == _AES_) { + sz = sizeof(psecuritypriv->iv_seq[0]); + for (i = 0 ; i < 4 ; i++) { + _rtw_memcpy(&tmp_iv_hdr, paoac_rpt->rxgtk_iv[i], sz); + tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr); + pkt_pn = CCMPH_2_PN(tmp_iv_hdr); + _rtw_memcpy(psecuritypriv->iv_seq[i], &pkt_pn, sz); + } + } + rtw_clean_dk_section(adapter); rtw_write8(adapter, REG_SECCFG, 0x0c); @@ -3915,6 +4365,82 @@ static void rtw_hal_update_gtk_offload_info(_adapter *adapter) dump_sec_cam_cache(RTW_DBGDUMP, adapter); #endif } +#endif /*CONFIG_GTK_OL*/ + +static void rtw_dump_aoac_rpt(_adapter *adapter) +{ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; + int i = 0; + + RTW_INFO_DUMP("[AOAC-RPT] IV -", paoac_rpt->iv, 8); + RTW_INFO_DUMP("[AOAC-RPT] Replay counter of EAPOL key - ", + paoac_rpt->replay_counter_eapol_key, 8); + RTW_INFO_DUMP("[AOAC-RPT] Group key - ", paoac_rpt->group_key, 32); + RTW_INFO("[AOAC-RPT] Key Index - %d\n", paoac_rpt->key_index); + RTW_INFO("[AOAC-RPT] Security Type - %d\n", paoac_rpt->security_type); + RTW_INFO("[AOAC-RPT] wow_pattern_idx - %d\n", + paoac_rpt->wow_pattern_idx); + RTW_INFO("[AOAC-RPT] version_info - %d\n", paoac_rpt->version_info); + RTW_INFO_DUMP("[AOAC-RPT] RX PTK IV-", paoac_rpt->rxptk_iv, 8); + RTW_INFO_DUMP("[AOAC-RPT] RX GTK[0] IV-", paoac_rpt->rxgtk_iv[0], 8); + RTW_INFO_DUMP("[AOAC-RPT] RX GTK[1] IV-", paoac_rpt->rxgtk_iv[1], 8); + RTW_INFO_DUMP("[AOAC-RPT] RX GTK[2] IV-", paoac_rpt->rxgtk_iv[2], 8); + RTW_INFO_DUMP("[AOAC-RPT] RX GTK[3] IV-", paoac_rpt->rxgtk_iv[3], 8); +} + +static void rtw_hal_get_aoac_rpt(_adapter *adapter) +{ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; + u32 page_offset = 0, page_number = 0; + u32 page_size = 0, buf_size = 0; + u8 *buffer = NULL; + u8 i = 0, tmp = 0; + int ret = -1; + + /* read aoac report from rsvd page */ + page_offset = pwrctl->wowlan_aoac_rpt_loc; + page_number = 1; + + rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); + buf_size = page_size * page_number; + + buffer = rtw_zvmalloc(buf_size); + + if (buffer == NULL) { + RTW_ERR("%s buffer allocate failed size(%d)\n", + __func__, buf_size); + return; + } + + RTW_INFO("Get AOAC Report from rsvd page_offset:%d\n", page_offset); + + ret = rtw_hal_get_rsvd_page(adapter, page_offset, + page_number, buffer, buf_size); + + if (ret == _FALSE) { + RTW_ERR("%s get aoac report failed\n", __func__); + rtw_warn_on(1); + goto _exit; + } + + _rtw_memset(paoac_rpt, 0, sizeof(struct aoac_report)); + _rtw_memcpy(paoac_rpt, buffer, sizeof(struct aoac_report)); + + for (i = 0 ; i < 4 ; i++) { + tmp = paoac_rpt->replay_counter_eapol_key[i]; + paoac_rpt->replay_counter_eapol_key[i] = + paoac_rpt->replay_counter_eapol_key[7 - i]; + paoac_rpt->replay_counter_eapol_key[7 - i] = tmp; + } + + rtw_dump_aoac_rpt(adapter); + +_exit: + if (buffer) + rtw_vmfree(buffer, buf_size); +} static void rtw_hal_update_tx_iv(_adapter *adapter) { @@ -3961,10 +4487,18 @@ static void rtw_hal_update_tx_iv(_adapter *adapter) static void rtw_hal_update_sw_security_info(_adapter *adapter) { + struct security_priv *psecpriv = &adapter->securitypriv; + u8 sz = sizeof (psecpriv->iv_seq); + rtw_hal_update_tx_iv(adapter); - rtw_hal_update_gtk_offload_info(adapter); +#ifdef CONFIG_GTK_OL + if (psecpriv->binstallKCK_KEK == _TRUE && + psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) + rtw_hal_update_gtk_offload_info(adapter); +#else + _rtw_memset(psecpriv->iv_seq, 0, sz); +#endif } -#endif /*CONFIG_GTK_OL*/ static u8 rtw_hal_set_keep_alive_cmd(_adapter *adapter, u8 enable, u8 pkt_type) { @@ -3996,7 +4530,7 @@ static u8 rtw_hal_set_disconnect_decision_cmd(_adapter *adapter, u8 enable) { struct hal_ops *pHalFunc = &adapter->hal_func; u8 u1H2CDisconDecisionParm[H2C_DISCON_DECISION_LEN] = {0}; - u8 adopt = 1, check_period = 10, trypkt_num = 0; + u8 adopt = 1, check_period = 30, trypkt_num = 5; u8 ret = _FAIL; SET_H2CCMD_DISCONDECISION_PARM_ENABLE(u1H2CDisconDecisionParm, enable); @@ -4019,18 +4553,22 @@ static u8 rtw_hal_set_disconnect_decision_cmd(_adapter *adapter, u8 enable) static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_unit) { + struct registry_priv *registry_par = &adapter->registrypriv; struct security_priv *psecpriv = &adapter->securitypriv; struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter); struct hal_ops *pHalFunc = &adapter->hal_func; u8 u1H2CWoWlanCtrlParm[H2C_WOWLAN_LEN] = {0}; - u8 discont_wake = 1, gpionum = 0, gpio_dur = 0; + u8 discont_wake = 0, gpionum = 0, gpio_dur = 0; u8 hw_unicast = 0, gpio_pulse_cnt = 0, gpio_pulse_en = 0; u8 sdio_wakeup_enable = 1; u8 gpio_high_active = 0; u8 magic_pkt = 0; u8 gpio_unit = 0; /*0: 64ns, 1: 8ms*/ u8 ret = _FAIL; +#ifdef CONFIG_DIS_UPHY + u8 dis_uphy = 0, dis_uphy_unit = 0, dis_uphy_time = 0; +#endif /* CONFIG_DIS_UPHY */ #ifdef CONFIG_GPIO_WAKEUP gpio_high_active = ppwrpriv->is_high_active; @@ -4038,15 +4576,17 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un sdio_wakeup_enable = 0; #endif /* CONFIG_GPIO_WAKEUP */ - if (!ppwrpriv->wowlan_pno_enable) + if (!ppwrpriv->wowlan_pno_enable && + registry_par->wakeup_event & BIT(0)) magic_pkt = enable; -#ifndef CONFIG_DEFAULT_PATTERNS_EN - if (psecpriv->dot11PrivacyAlgrthm == _WEP40_ || psecpriv->dot11PrivacyAlgrthm == _WEP104_) - hw_unicast = 1; - else - hw_unicast = 0; -#endif + if ((registry_par->wakeup_event & BIT(1)) && + (psecpriv->dot11PrivacyAlgrthm == _WEP40_ || + psecpriv->dot11PrivacyAlgrthm == _WEP104_)) + hw_unicast = 1; + + if (registry_par->wakeup_event & BIT(2)) + discont_wake = enable; RTW_INFO("%s(): enable=%d change_unit=%d\n", __func__, enable, change_unit); @@ -4091,6 +4631,26 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(u1H2CWoWlanCtrlParm, gpio_pulse_en); SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(u1H2CWoWlanCtrlParm, gpio_pulse_cnt); +#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE + if (enable) + SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1); +#endif + +#ifdef CONFIG_DIS_UPHY + if (enable) { + dis_uphy = 1; + /* time unit: 0 -> ms, 1 -> 256 ms*/ + dis_uphy_unit = 1; + dis_uphy_time = 0x4; + } + + SET_H2CCMD_WOWLAN_DIS_UPHY(u1H2CWoWlanCtrlParm, dis_uphy); + SET_H2CCMD_WOWLAN_HOST_2_DEV(u1H2CWoWlanCtrlParm, 1); + SET_H2CCMD_WOWLAN_DIS_UPHY_UNIT(u1H2CWoWlanCtrlParm, dis_uphy_unit); + SET_H2CCMD_WOWLAN_DIS_UPHY_TIME(u1H2CWoWlanCtrlParm, dis_uphy_time); +#endif /* CONFIG_DIS_UPHY */ + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_WOWLAN, H2C_WOWLAN_LEN, @@ -4126,23 +4686,22 @@ static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable) } #endif /* CONFIG_GTK_OL */ +#ifdef CONFIG_IPV6 if (ppwrpriv->wowlan_ns_offload_en == _TRUE) { RTW_INFO("enable NS offload\n"); SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN( u1H2CRemoteWakeCtrlParm, enable); } - if (pregistrypriv->default_patterns_en == _FALSE) { - SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN( - u1H2CRemoteWakeCtrlParm, enable); - /* - * filter NetBios name service pkt to avoid being waked-up - * by this kind of unicast pkt this exceptional modification - * is used for match competitor's behavior - */ - SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN( - u1H2CRemoteWakeCtrlParm, enable); - } + /* + * filter NetBios name service pkt to avoid being waked-up + * by this kind of unicast pkt this exceptional modification + * is used for match competitor's behavior + */ + + SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN( + u1H2CRemoteWakeCtrlParm, enable); +#endif /*CONFIG_IPV6*/ if ((psecuritypriv->dot11PrivacyAlgrthm == _AES_) || (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) || @@ -4256,6 +4815,7 @@ void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable) struct security_priv *psecpriv = &padapter->securitypriv; struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct registry_priv *pregistry = &padapter->registrypriv; struct sta_info *psta = NULL; u16 media_status_rpt; u8 pkt_type = 0; @@ -4271,7 +4831,9 @@ void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable) psecpriv->dot11PrivacyAlgrthm); if (!(ppwrpriv->wowlan_pno_enable)) { - rtw_hal_set_disconnect_decision_cmd(padapter, enable); + if (pregistry->wakeup_event & BIT(2)) + rtw_hal_set_disconnect_decision_cmd(padapter, + enable); #ifdef CONFIG_ARP_KEEP_ALIVE if ((psecpriv->dot11PrivacyAlgrthm == _WEP40_) || (psecpriv->dot11PrivacyAlgrthm == _WEP104_)) @@ -4543,11 +5105,18 @@ static void rtw_hal_ap_wow_disable(_adapter *padapter) rtw_hal_fw_dl(padapter, _FALSE); #ifdef CONFIG_GPIO_WAKEUP + #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE + if (pwrctl->is_high_active == 0) + rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX); + else + rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0); + #else val8 = (pwrctl->is_high_active == 0) ? 1 : 0; RTW_PRINT("Set Wake GPIO to default(%d).\n", val8); rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8); rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _FALSE); + #endif/*CONFIG_WAKEUP_GPIO_INPUT_MODE*/ #endif media_status_rpt = RT_MEDIA_CONNECT; @@ -6024,7 +6593,7 @@ u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter) } #endif /* CONFIG_P2P_WOWLAN */ -static void rtw_hal_construct_beacon(_adapter *padapter, +void rtw_hal_construct_beacon(_adapter *padapter, u8 *pframe, u32 *pLength) { struct rtw_ieee80211_hdr *pwlanhdr; @@ -6153,6 +6722,44 @@ static void rtw_hal_construct_PSPoll(_adapter *padapter, *pLength = 16; } + +#ifdef DBG_FW_DEBUG_MSG_PKT +void rtw_hal_construct_fw_dbg_msg_pkt( + PADAPTER padapter, + u8 *pframe, + u32 *plength) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 pktlen; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + + /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, 0); + + set_frame_sub_type(pframe, WIFI_DATA); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + *plength = pktlen; +} +#endif /*DBG_FW_DEBUG_MSG_PKT*/ + void rtw_hal_construct_NullFunctionData( PADAPTER padapter, u8 *pframe, @@ -6170,7 +6777,7 @@ void rtw_hal_construct_NullFunctionData( struct wlan_network *cur_network = &pmlmepriv->cur_network; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - + u8 bssid[ETH_ALEN]; /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */ @@ -6181,6 +6788,11 @@ void rtw_hal_construct_NullFunctionData( if (bForcePowerSave) SetPwrMgt(fctrl); + if (NULL == StaAddr) { + _rtw_memcpy(bssid, adapter_mac_addr(padapter), ETH_ALEN); + StaAddr = bssid; + } + switch (cur_network->network.InfrastructureMode) { case Ndis802_11Infrastructure: SetToDs(fctrl); @@ -6203,6 +6815,7 @@ void rtw_hal_construct_NullFunctionData( } SetSeqNum(pwlanhdr, 0); + set_duration(pwlanhdr, 0); if (bQoS == _TRUE) { struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; @@ -6441,6 +7054,7 @@ static void rtw_hal_construct_ARPRsp( } } +#ifdef CONFIG_IPV6 /* * Description: Neighbor Discovery Offload. */ @@ -6618,6 +7232,7 @@ static void rtw_hal_construct_ndp_info(_adapter *padapter, _rtw_memcpy(pndp_info, &ndp_info, len); } +#endif /* CONFIG_IPV6 */ #ifdef CONFIG_PNO_SUPPORT static void rtw_hal_construct_ProbeReq(_adapter *padapter, u8 *pframe, @@ -6907,6 +7522,84 @@ static void rtw_hal_construct_GTKRsp( } #endif /* CONFIG_GTK_OL */ +#define PN_2_CCMPH(ch,key_id) ((ch) & 0x000000000000ffff) \ + | (((ch) & 0x0000ffffffff0000) << 16) \ + | (((key_id) << 30)) \ + | BIT(29) +static void rtw_hal_construct_remote_control_info(_adapter *adapter, + u8 *pframe, u32 *pLength) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct sta_priv *pstapriv = &adapter->stapriv; + struct security_priv *psecuritypriv = &adapter->securitypriv; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct sta_info *psta; + struct stainfo_rxcache *prxcache; + u8 cur_dot11rxiv[8], id = 0, tid_id = 0, i = 0; + size_t sz = 0, total = 0; + u64 ccmp_hdr = 0, tmp_key = 0; + + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + + if (psta == NULL) { + rtw_warn_on(1); + return; + } + + prxcache = &psta->sta_recvpriv.rxcache; + sz = sizeof(cur_dot11rxiv); + + /* 3 SEC IV * 1 page */ + rtw_get_sec_iv(adapter, cur_dot11rxiv, + get_my_bssid(&pmlmeinfo->network)); + + _rtw_memcpy(pframe, cur_dot11rxiv, sz); + *pLength += sz; + pframe += sz; + + _rtw_memset(&cur_dot11rxiv, 0, sz); + + if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) { + id = psecuritypriv->dot118021XGrpKeyid; + tid_id = prxcache->last_tid; + REMOTE_INFO_CTRL_SET_VALD_EN(cur_dot11rxiv, 0xdd); + REMOTE_INFO_CTRL_SET_PTK_EN(cur_dot11rxiv, 1); + REMOTE_INFO_CTRL_SET_GTK_EN(cur_dot11rxiv, 1); + REMOTE_INFO_CTRL_SET_GTK_IDX(cur_dot11rxiv, id); + _rtw_memcpy(pframe, cur_dot11rxiv, sz); + *pLength += sz; + pframe += sz; + + _rtw_memcpy(pframe, prxcache->iv[tid_id], sz); + *pLength += sz; + pframe += sz; + + total = sizeof(psecuritypriv->iv_seq); + total /= sizeof(psecuritypriv->iv_seq[0]); + + for (i = 0 ; i < total ; i ++) { + ccmp_hdr = + le64_to_cpu(*(u64*)psecuritypriv->iv_seq[i]); + _rtw_memset(&cur_dot11rxiv, 0, sz); + if (ccmp_hdr != 0) { + tmp_key = i; + ccmp_hdr = PN_2_CCMPH(ccmp_hdr, tmp_key); + *(u64*)cur_dot11rxiv = cpu_to_le64(ccmp_hdr); + _rtw_memcpy(pframe, cur_dot11rxiv, sz); + } + *pLength += sz; + pframe += sz; + } + } +} + +/*#define DBG_RSVD_PAGE_CFG*/ +#ifdef DBG_RSVD_PAGE_CFG +#define RSVD_PAGE_CFG(ops, v1, v2, v3) \ + RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n", \ + ops, v1, v2, v3) +#endif void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len, RSVDPAGE_LOC *rsvd_page_loc) @@ -6917,9 +7610,8 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, struct mlme_ext_priv *pmlmeext; struct mlme_ext_info *pmlmeinfo; u32 ARPLength = 0, GTKLength = 0, PNOLength = 0, ScanInfoLength = 0; - u32 SSIDLegnth = 0, ProbeReqLength = 0, ns_len = 0; + u32 SSIDLegnth = 0, ProbeReqLength = 0, ns_len = 0, rc_len = 0; u8 CurtPktPageNum = 0; - u8 cur_dot11txpn[8]; #ifdef CONFIG_GTK_OL struct sta_priv *pstapriv = &adapter->stapriv; @@ -6955,7 +7647,11 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-ARPRsp", CurtPktPageNum, *page_num, 0); + #endif +#ifdef CONFIG_IPV6 /* 2 NS offload and NDP Info*/ if (pwrctl->wowlan_ns_offload_en == _TRUE) { rsvd_page_loc->LocNbrAdv = *page_num; @@ -6970,6 +7666,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, page_size); *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-NbrAdv", CurtPktPageNum, *page_num, 0); + #endif rsvd_page_loc->LocNDPInfo = *page_num; RTW_INFO("LocNDPInfo: %d\n", @@ -6982,23 +7681,24 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, (u8)PageNum(tx_desc + ns_len, page_size); *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); - } - - /* 3 SEC IV * 1 page */ - rtw_get_sec_iv(adapter, cur_dot11txpn, - get_my_bssid(&pmlmeinfo->network)); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-NDPInfo", CurtPktPageNum, *page_num, 0); + #endif + } +#endif /*CONFIG_IPV6*/ + /* 3 Remote Control Info. * 1 page */ rsvd_page_loc->LocRemoteCtrlInfo = *page_num; - RTW_INFO("LocRemoteCtrlInfo: %d\n", rsvd_page_loc->LocRemoteCtrlInfo); - - _rtw_memcpy(pframe + index - tx_desc, cur_dot11txpn, _AES_IV_LEN_); - - CurtPktPageNum = (u8)PageNum(_AES_IV_LEN_, page_size); - + rtw_hal_construct_remote_control_info(adapter, + &pframe[index - tx_desc], + &rc_len); + CurtPktPageNum = (u8)PageNum(rc_len, page_size); *page_num += CurtPktPageNum; - - *total_pkt_len = index + _AES_IV_LEN_; + *total_pkt_len = index + rc_len; + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-RCI", CurtPktPageNum, *page_num, *total_pkt_len); + #endif #ifdef CONFIG_GTK_OL index += (CurtPktPageNum * page_size); @@ -7018,19 +7718,34 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, rsvd_page_loc->LocGTKInfo = *page_num; RTW_INFO("LocGTKInfo: %d\n", rsvd_page_loc->LocGTKInfo); - _rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN); - _rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN, - kek, RTW_KEK_LEN); - GTKLength = tx_desc + RTW_KCK_LEN + RTW_KEK_LEN; + if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8812(adapter)) { + struct security_priv *psecpriv = NULL; + + psecpriv = &adapter->securitypriv; + _rtw_memcpy(pframe + index - tx_desc, + &psecpriv->dot11PrivacyAlgrthm, 1); + _rtw_memcpy(pframe + index - tx_desc + 1, + &psecpriv->dot118021XGrpPrivacy, 1); + _rtw_memcpy(pframe + index - tx_desc + 2, + kck, RTW_KCK_LEN); + _rtw_memcpy(pframe + index - tx_desc + 2 + RTW_KCK_LEN, + kek, RTW_KEK_LEN); + CurtPktPageNum = (u8)PageNum(tx_desc + 2 + RTW_KCK_LEN + RTW_KEK_LEN, page_size); + } else { + + _rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN); + _rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN, + kek, RTW_KEK_LEN); + GTKLength = tx_desc + RTW_KCK_LEN + RTW_KEK_LEN; - if (psta != NULL && - psecuritypriv->dot118021XGrpPrivacy == _TKIP_) { - _rtw_memcpy(pframe + index - tx_desc + 56, - &psta->dot11tkiptxmickey, RTW_TKIP_MIC_LEN); - GTKLength += RTW_TKIP_MIC_LEN; + if (psta != NULL && + psecuritypriv->dot118021XGrpPrivacy == _TKIP_) { + _rtw_memcpy(pframe + index - tx_desc + 56, + &psta->dot11tkiptxmickey, RTW_TKIP_MIC_LEN); + GTKLength += RTW_TKIP_MIC_LEN; + } + CurtPktPageNum = (u8)PageNum(GTKLength, page_size); } - - CurtPktPageNum = (u8)PageNum(GTKLength, page_size); #if 0 { int i; @@ -7051,6 +7766,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-GTKInfo", CurtPktPageNum, *page_num, 0); + #endif /* 3 GTK Response */ rsvd_page_loc->LocGTKRsp = *page_num; @@ -7081,6 +7799,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-GTKRsp", CurtPktPageNum, *page_num, 0); + #endif /* below page is empty for GTK extension memory */ /* 3(11) GTK EXT MEM */ @@ -7094,6 +7815,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; /* extension memory for FW */ *total_pkt_len = index + (page_size * CurtPktPageNum); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-GTKEXTMEM", CurtPktPageNum, *page_num, *total_pkt_len); + #endif #endif /* CONFIG_GTK_OL */ index += (CurtPktPageNum * page_size); @@ -7103,6 +7827,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, RTW_INFO("LocAOACReport: %d\n", rsvd_page_loc->LocAOACReport); *page_num += 1; *total_pkt_len = index + (page_size * 1); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-AOAC", 1, *page_num, *total_pkt_len); + #endif } else { #ifdef CONFIG_PNO_SUPPORT if (pwrctl->wowlan_in_resume == _FALSE && @@ -7130,6 +7857,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-ProbeReq", CurtPktPageNum, *page_num, 0); + #endif /* Hidden SSID Probe Request */ ssid_num = pwrctl->pnlo_info->hidden_ssid_num; @@ -7154,6 +7884,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-ProbeReq", CurtPktPageNum, *page_num, 0); + #endif } /* PNO INFO Page */ @@ -7166,6 +7899,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, CurtPktPageNum = (u8)PageNum(PNOLength, page_size); *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-PNOInfo", CurtPktPageNum, *page_num, 0); + #endif /* Scan Info Page */ rsvd_page_loc->LocScanInfo = *page_num; @@ -7178,6 +7914,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; *total_pkt_len = index + ScanInfoLength; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-ScanInfo", CurtPktPageNum, *page_num, *total_pkt_len); + #endif } #endif /* CONFIG_PNO_SUPPORT */ } @@ -7186,10 +7925,25 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, static void rtw_hal_gate_bb(_adapter *adapter, bool stop) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); - u8 val8 = 0; + u8 i = 0, val8 = 0, empty = _FAIL; u16 val16 = 0; if (stop) { + /* checking TX queue status */ + for (i = 0 ; i < 5 ; i++) { + rtw_hal_get_hwreg(adapter, HW_VAR_CHK_MGQ_CPU_EMPTY, &empty); + if (empty) { + break; + } else { + RTW_WARN("%s: MGQ_CPU is busy(%d)!\n", + __func__, i); + rtw_mdelay_os(10); + } + } + + if (val8 == 5) + RTW_ERR("%s: Polling MGQ_CPU empty fail!\n", __func__); + /* Pause TX*/ pwrpriv->wowlan_txpause_status = rtw_read8(adapter, REG_TXPAUSE); rtw_write8(adapter, REG_TXPAUSE, 0xff); @@ -7726,7 +8480,7 @@ static u32 _rtw_wow_pattern_read_cam(_adapter *adapter, u8 addr) u32 rdata = 0; u32 cnt = 0; - u32 start = 0; + systime start = 0; u8 timeout = 0; u8 rst = _FALSE; @@ -7796,7 +8550,7 @@ static void _rtw_wow_pattern_write_cam(_adapter *adapter, u8 addr, u32 wdata) struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex; u32 cnt = 0; - u32 start = 0, end = 0; + systime start = 0, end = 0; u8 timeout = 0; /*RTW_INFO("%s ==> addr:0x%02x , wdata:0x%08x\n", __func__, addr, wdata);*/ @@ -7865,7 +8619,7 @@ static u8 _rtw_wow_pattern_clean_cam(_adapter *adapter) struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex; u32 cnt = 0; - u32 start = 0; + systime start = 0; u8 timeout = 0; u8 rst = _FAIL; @@ -8029,7 +8783,7 @@ static void rtw_hal_wow_enable(_adapter *adapter) if (psta != NULL) { #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - rtw_hal_set_default_port_id_cmd(adapter, psta->mac_id); + rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id); #endif rtw_sta_media_status_rpt(adapter, psta, 1); @@ -8194,26 +8948,31 @@ static void rtw_hal_wow_disable(_adapter *adapter) rtw_hal_enable_tx_report(adapter); #endif -#ifdef CONFIG_GTK_OL - if (((pwrctl->wowlan_wake_reason != RX_DISASSOC) || + if ((pwrctl->wowlan_wake_reason != RX_DISASSOC) || (pwrctl->wowlan_wake_reason != RX_DEAUTH) || - (pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT)) && - psecuritypriv->binstallKCK_KEK == _TRUE) { + (pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT)) { rtw_hal_get_aoac_rpt(adapter); rtw_hal_update_sw_security_info(adapter); } -#endif /*CONFIG_GTK_OL*/ rtw_hal_fw_dl(adapter, _FALSE); #ifdef CONFIG_GPIO_WAKEUP + +#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE + if (pwrctl->is_high_active == 0) + rtw_hal_set_input_gpio(adapter, WAKEUP_GPIO_IDX); + else + rtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, 0); +#else val8 = (pwrctl->is_high_active == 0) ? 1 : 0; RTW_PRINT("Set Wake GPIO to default(%d).\n", val8); - rtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, val8); + rtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, val8); rtw_hal_switch_gpio_wl_ctrl(adapter, WAKEUP_GPIO_IDX, _FALSE); #endif +#endif if ((pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT) && (pwrctl->wowlan_wake_reason != RX_PAIRWISEKEY) && (pwrctl->wowlan_wake_reason != RX_DISASSOC) && @@ -8225,7 +8984,7 @@ static void rtw_hal_wow_disable(_adapter *adapter) if (psta != NULL) { #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - rtw_hal_set_default_port_id_cmd(adapter, psta->mac_id); + rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id); #endif rtw_sta_media_status_rpt(adapter, psta, 1); } @@ -8259,6 +9018,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-P2P-Beacon", CurtPktPageNum, *page_num, 0); + #endif /* P2P Probe rsp */ rsvd_page_loc->LocP2PProbeRsp = *page_num; @@ -8275,6 +9037,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-P2P-ProbeRsp", CurtPktPageNum, *page_num, 0); + #endif /* P2P nego rsp */ rsvd_page_loc->LocNegoRsp = *page_num; @@ -8291,6 +9056,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-P2P-NegoRsp", CurtPktPageNum, *page_num, 0); + #endif /* P2P invite rsp */ rsvd_page_loc->LocInviteRsp = *page_num; @@ -8307,6 +9075,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-P2P-InviteRsp", CurtPktPageNum, *page_num, 0); + #endif /* P2P provision discovery rsp */ rsvd_page_loc->LocPDRsp = *page_num; @@ -8324,6 +9095,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; *total_pkt_len = index + P2PPDRspLength; + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-P2P-PDR", CurtPktPageNum, *page_num, *total_pkt_len); + #endif index += (CurtPktPageNum * page_size); @@ -8351,6 +9125,7 @@ static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter) #endif u8 *psec_cam_id = lps_pg_info + 8; u8 sec_cam_num = 0; + u8 drv_rsvdpage_num = 0; if (!psta) { RTW_ERR("%s [ERROR] sta is NULL\n", __func__); @@ -8359,8 +9134,8 @@ static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter) } /*Byte 0 - used macid*/ - LPSPG_RSVD_PAGE_SET_MACID(lps_pg_info, psta->mac_id); - RTW_INFO("[LPSPG-INFO] mac_id:%d\n", psta->mac_id); + LPSPG_RSVD_PAGE_SET_MACID(lps_pg_info, psta->cmn.mac_id); + RTW_INFO("[LPSPG-INFO] mac_id:%d\n", psta->cmn.mac_id); #ifdef CONFIG_MBSSID_CAM /*Byte 1 - used BSSID CAM entry*/ @@ -8380,8 +9155,8 @@ static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter) #endif #ifdef CONFIG_BEAMFORMING /*&& MU BF*/ /*Btye 3 - Max MU rate table Group ID*/ - LPSPG_RSVD_PAGE_SET_MU_RAID_GID(lps_pg_info, _value); - RTW_INFO("[LPSPG-INFO] Max MU rate table Group ID :%d\n", _value); + LPSPG_RSVD_PAGE_SET_MU_RAID_GID(lps_pg_info, 0); + RTW_INFO("[LPSPG-INFO] Max MU rate table Group ID :%d\n", 0); #endif /*Btye 8 ~15 - used Security CAM entry */ @@ -8393,8 +9168,12 @@ static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter) RTW_INFO("[LPSPG-INFO] Security CAM entry number :%d\n", sec_cam_num); /*Btye 5 - Txbuf used page number for fw offload*/ - LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(lps_pg_info, phal_data->drv_rsvd_page_number); - RTW_INFO("[LPSPG-INFO] DRV's rsvd page numbers :%d\n", phal_data->drv_rsvd_page_number); + if (pwrpriv->wowlan_mode == _TRUE || pwrpriv->wowlan_ap_mode == _TRUE) + drv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE); + else + drv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE); + LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(lps_pg_info, drv_rsvdpage_num); + RTW_INFO("[LPSPG-INFO] DRV's rsvd page numbers :%d\n", drv_rsvdpage_num); #ifdef DBG_LPSPG_SEC_DUMP { @@ -8495,7 +9274,23 @@ u8 rtw_hal_set_lps_pg_info(_adapter *adapter) return ret; } -void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id) +void rtw_hal_lps_pg_rssi_lv_decide(_adapter *adapter, struct sta_info *sta) +{ +#if 0 + if (sta->cmn.ra_info.rssi_level >= 4) + sta->lps_pg_rssi_lv = 3; /*RSSI High - 1SS_VHT_MCS7*/ + else if (sta->cmn.ra_info.rssi_level >= 2) + sta->lps_pg_rssi_lv = 2; /*RSSI Middle - 1SS_VHT_MCS3*/ + else + sta->lps_pg_rssi_lv = 1; /*RSSI Lower - Lowest_rate*/ +#else + sta->lps_pg_rssi_lv = 0; +#endif + RTW_INFO("%s mac-id:%d, rssi:%d, rssi_level:%d, lps_pg_rssi_lv:%d\n", + __func__, sta->cmn.mac_id, sta->cmn.rssi_stat.rssi, sta->cmn.ra_info.rssi_level, sta->lps_pg_rssi_lv); +} + +void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id) { switch (hdl_id) { case LPS_PG_INFO_CFG: @@ -8516,14 +9311,15 @@ void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id) { struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; struct sta_info *sta; - PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); int i; for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { sta = macid_ctl->sta[i]; - if (sta && !is_broadcast_mac_addr(sta->hwaddr)) - /*rtw_dm_ra_mask_hdl(adapter, sta);*/ - rtw_dm_ra_mask_wk_cmd(adapter, (u8 *)sta); + if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) { + rtw_hal_lps_pg_rssi_lv_decide(adapter, sta); + set_sta_rate(adapter, sta); + sta->lps_pg_rssi_lv = 0; + } } } break; @@ -8544,7 +9340,12 @@ void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id) * so we need to set the packet length to total lengh. * TRUE: At the second time, we should send the first packet (default:beacon) * to Hw again and set the lengh in descriptor to the real beacon lengh. + * page_num - The amount of reserved page which driver need. + * If this is not NULL, this function doesn't real download reserved + * page, but just count the number of reserved page. + * * 2009.10.15 by tynli. + * 2017.06.20 modified by Lucas. * * Page Size = 128: 8188e, 8723a/b, 8192c/d, * Page Size = 256: 8192e, 8821a @@ -8552,10 +9353,10 @@ void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id) */ /*#define DBG_DUMP_SET_RSVD_PAGE*/ -void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) +static void _rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished, u8 *page_num) { PHAL_DATA_TYPE pHalData; - struct xmit_frame *pcmdframe; + struct xmit_frame *pcmdframe = NULL; struct pkt_attrib *pattrib; struct xmit_priv *pxmitpriv; struct mlme_ext_priv *pmlmeext; @@ -8573,6 +9374,10 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) u32 TotalPacketLen = 0, MaxRsvdPageBufSize = 0, PageSize = 0; RSVDPAGE_LOC RsvdPageLoc; +#ifdef DBG_FW_DEBUG_MSG_PKT + u32 fw_dbg_msg_pkt_len = 0; +#endif /*DBG_FW_DEBUG_MSG_PKT*/ + #ifdef DBG_CONFIG_ERROR_DETECT struct sreset_priv *psrtpriv; #endif /* DBG_CONFIG_ERROR_DETECT */ @@ -8597,30 +9402,39 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) return; } - if (pwrctl->wowlan_mode == _TRUE || pwrctl->wowlan_ap_mode == _TRUE) - RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE); - else - RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE); - - RTW_INFO("%s PageSize: %d, RsvdPageNUm: %d\n", __func__, PageSize, RsvdPageNum); + /* Prepare ReservedPagePacket */ + if (page_num) { + ReservedPagePacket = rtw_zmalloc(MAX_CMDBUF_SZ); + if (!ReservedPagePacket) { + RTW_WARN("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); + *page_num = 0xFF; + return; + } + } else { + if (pwrctl->wowlan_mode == _TRUE || pwrctl->wowlan_ap_mode == _TRUE) + RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE); + else + RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE); - MaxRsvdPageBufSize = RsvdPageNum * PageSize; + RTW_INFO("%s PageSize: %d, RsvdPageNUm: %d\n", __func__, PageSize, RsvdPageNum); - if (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) { - RTW_INFO("%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)", - __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ); - rtw_warn_on(1); - return; - } + MaxRsvdPageBufSize = RsvdPageNum * PageSize; + if (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) { + RTW_ERR("%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)", + __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ); + rtw_warn_on(1); + return; + } - pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv); + pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv); + if (pcmdframe == NULL) { + RTW_ERR("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); + return; + } - if (pcmdframe == NULL) { - RTW_INFO("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); - return; + ReservedPagePacket = pcmdframe->buf_addr; } - ReservedPagePacket = pcmdframe->buf_addr; _rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC)); /* beacon * 1 pages */ @@ -8638,6 +9452,10 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) BufIndex += (CurtPktPageNum * PageSize); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("Beacon", CurtPktPageNum, TotalPageNum, TotalPacketLen); + #endif + if (pwrctl->wowlan_ap_mode == _TRUE) { /* (4) probe response*/ RsvdPageLoc.LocProbeRsp = TotalPageNum; @@ -8653,6 +9471,9 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) TotalPageNum += CurtPktPageNum; TotalPacketLen = BufIndex + ProbeRspLength; BufIndex += (CurtPktPageNum * PageSize); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("ProbeRsp", CurtPktPageNum, TotalPageNum, TotalPacketLen); + #endif goto download_page; } @@ -8670,6 +9491,9 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) TotalPageNum += CurtPktPageNum; BufIndex += (CurtPktPageNum * PageSize); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("PSPoll", CurtPktPageNum, TotalPageNum, TotalPacketLen); + #endif #ifdef CONFIG_BT_COEXIST if (pwrctl->wowlan_mode == _FALSE || @@ -8694,20 +9518,24 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) TotalPageNum += CurtPktPageNum; BufIndex += (CurtPktPageNum * PageSize); + + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("BTQosNull", CurtPktPageNum, TotalPageNum, TotalPacketLen); + #endif } #endif /* CONFIG_BT_COEXIT */ #ifdef CONFIG_MCC_MODE if (MCC_EN(adapter)) { dl_mcc_page = rtw_hal_dl_mcc_fw_rsvd_page(adapter, ReservedPagePacket, - &BufIndex, TxDescLen, PageSize, - &TotalPageNum, &TotalPacketLen, &RsvdPageLoc); - } else + &BufIndex, TxDescLen, PageSize, &TotalPageNum, &RsvdPageLoc, page_num); + } else { dl_mcc_page = _FAIL; + } - if (dl_mcc_page == _FAIL) { + if (dl_mcc_page == _FAIL) #endif /* CONFIG_MCC_MODE */ - + { /* null data * 1 page */ RsvdPageLoc.LocNullData = TotalPageNum; RTW_INFO("LocNullData: %d\n", RsvdPageLoc.LocNullData); @@ -8726,9 +9554,10 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) TotalPageNum += CurtPktPageNum; BufIndex += (CurtPktPageNum * PageSize); -#ifdef CONFIG_MCC_MODE + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("NullData", CurtPktPageNum, TotalPageNum, TotalPacketLen); + #endif } -#endif /* CONFIG_MCC_MODE */ if (pwrctl->wowlan_mode == _FALSE || pwrctl->wowlan_in_resume == _TRUE) { @@ -8750,9 +9579,34 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) TotalPageNum += CurtPktPageNum; BufIndex += (CurtPktPageNum * PageSize); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("QosNull", CurtPktPageNum, TotalPageNum, TotalPacketLen); + #endif } - TotalPacketLen = BufIndex + QosNullLength; + TotalPacketLen = BufIndex; + +#ifdef DBG_FW_DEBUG_MSG_PKT + RsvdPageLoc.loc_fw_dbg_msg_pkt = TotalPageNum; + RTW_INFO("loc_fw_dbg_msg_pkt: %d\n", RsvdPageLoc.loc_fw_dbg_msg_pkt); + rtw_hal_construct_fw_dbg_msg_pkt( + adapter, + &ReservedPagePacket[BufIndex], + &fw_dbg_msg_pkt_len); + + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex - TxDescLen], + fw_dbg_msg_pkt_len, _FALSE, _FALSE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + fw_dbg_msg_pkt_len, PageSize); + + TotalPageNum += CurtPktPageNum; + + TotalPacketLen = BufIndex + fw_dbg_msg_pkt_len; + BufIndex += (CurtPktPageNum * PageSize); + + +#endif /*DBG_FW_DEBUG_MSG_PKT*/ #ifdef CONFIG_WOWLAN if (pwrctl->wowlan_mode == _TRUE && @@ -8775,26 +9629,48 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) /* must reserved last 1 x page for LPS PG Info*/ pwrctl->lpspg_rsvd_page_locate = TotalPageNum; pwrctl->blpspg_info_up = _TRUE; + if (page_num) + TotalPageNum += LPS_PG_INFO_RSVD_PAGE_NUM; + + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("LPS_PG", LPS_PG_INFO_RSVD_PAGE_NUM, + (page_num) ? TotalPageNum : (TotalPageNum + LPS_PG_INFO_RSVD_PAGE_NUM), + TotalPacketLen); + #endif + #endif + /*Note: BufIndex already add a TxDescOffset offset in first Beacon page + * The "TotalPacketLen" is calculate by BufIndex. + * We need to decrease TxDescOffset before doing length check. by yiwei + */ + TotalPacketLen = TotalPacketLen - TxDescOffset; + download_page: + if (page_num) { + *page_num = TotalPageNum; + rtw_mfree(ReservedPagePacket, MAX_CMDBUF_SZ); + ReservedPagePacket = NULL; + return; + } + /* RTW_INFO("%s BufIndex(%d), TxDescLen(%d), PageSize(%d)\n",__func__, BufIndex, TxDescLen, PageSize);*/ RTW_INFO("%s PageNum(%d), pktlen(%d)\n", __func__, TotalPageNum, TotalPacketLen); #ifdef CONFIG_LPS_PG - if ((TotalPacketLen + (LPS_PG_INFO_RSVD_PAGE_NUM * PageSize)) > MaxRsvdPageBufSize) { + if ((TotalPageNum + LPS_PG_INFO_RSVD_PAGE_NUM) > RsvdPageNum) { pwrctl->lpspg_rsvd_page_locate = 0; pwrctl->blpspg_info_up = _FALSE; - RTW_ERR("%s rsvd page size is not enough!!TotalPacketLen+LPS_PG_INFO_LEN %d, MaxRsvdPageBufSize %d\n", - __func__, (TotalPacketLen + (LPS_PG_INFO_RSVD_PAGE_NUM * PageSize)), MaxRsvdPageBufSize); + RTW_ERR("%s [LPS_PG] rsvd page %d is not enough! need %d pages\n", + __func__, RsvdPageNum, (TotalPageNum + LPS_PG_INFO_RSVD_PAGE_NUM)); rtw_warn_on(1); } #endif if (TotalPacketLen > MaxRsvdPageBufSize) { - RTW_ERR("%s(ERROR): rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n", + RTW_ERR("%s : rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n", __FUNCTION__, TotalPacketLen, MaxRsvdPageBufSize); rtw_warn_on(1); goto error; @@ -8803,8 +9679,8 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) pattrib = &pcmdframe->attrib; update_mgntframe_attrib(adapter, pattrib); pattrib->qsel = QSLT_BEACON; - pattrib->pktlen = TotalPacketLen - TxDescOffset; - pattrib->last_txcmdsz = TotalPacketLen - TxDescOffset; + pattrib->pktlen = TotalPacketLen; + pattrib->last_txcmdsz = TotalPacketLen; #ifdef CONFIG_PCI_HCI dump_mgntframe(adapter, pcmdframe); #else @@ -8821,6 +9697,9 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) #endif if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { rtw_hal_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc); +#ifdef DBG_FW_DEBUG_MSG_PKT + rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(adapter, &RsvdPageLoc); +#endif /*DBG_FW_DEBUG_MSG_PKT*/ #ifdef CONFIG_WOWLAN if (pwrctl->wowlan_mode == _TRUE && pwrctl->wowlan_in_resume == _FALSE) @@ -8841,14 +9720,205 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) &RsvdPageLoc, 1); #endif /* CONFIG_PNO_SUPPORT */ } + #ifdef CONFIG_P2P_WOWLAN if (_TRUE == pwrctl->wowlan_p2p_mode) rtw_hal_set_FwP2PRsvdPage_cmd(adapter, &RsvdPageLoc); #endif /* CONFIG_P2P_WOWLAN */ + return; error: rtw_free_xmitframe(pxmitpriv, pcmdframe); } + +void rtw_hal_set_fw_rsvd_page(struct _ADAPTER *adapter, bool finished) +{ + _rtw_hal_set_fw_rsvd_page(adapter, finished, NULL); +} + +/** + * rtw_hal_get_rsvd_page_num() - Get needed reserved page number + * @adapter: struct _ADAPTER* + * + * Caculate needed reserved page number. + * In different state would get different number, for example normal mode and + * WOW mode would need different reserved page size. + * + * Return the number of reserved page which driver need. + */ +u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter) +{ + u8 num = 0; + + + _rtw_hal_set_fw_rsvd_page(adapter, _FALSE, &num); + + return num; +} + +static void hw_var_set_mlme_sitesurvey(_adapter *adapter, u8 variable, u8 *val) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u16 value_rxfltmap2; + int i; + _adapter *iface; + +#ifdef DBG_IFACE_STATUS + DBG_IFACE_STATUS_DUMP(adapter); +#endif + +#ifdef CONFIG_FIND_BEST_CHANNEL + /* Receive all data frames */ + value_rxfltmap2 = 0xFFFF; +#else + /* not to receive data frame */ + value_rxfltmap2 = 0; +#endif + + if (*((u8 *)val)) { /* under sitesurvey */ + /* + * 1. configure REG_RXFLTMAP2 + * 2. disable TSF update & buddy TSF update to avoid updating wrong TSF due to clear RCR_CBSSID_BCN + * 3. config RCR to receive different BSSID BCN or probe rsp + */ + rtw_write16(adapter, REG_RXFLTMAP2, value_rxfltmap2); + +#ifdef CONFIG_MI_WITH_MBSSID_CAM + /*do nothing~~*/ +#else + + /* disable update TSF */ + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + + if (rtw_linked_check(iface) + && !MLME_IS_AP(iface) && !MLME_IS_MESH(iface) + ) { + if (iface->hw_port == HW_PORT1) + rtw_write8(iface, REG_BCN_CTRL_1, rtw_read8(iface, REG_BCN_CTRL_1) | DIS_TSF_UDT); + else + rtw_write8(iface, REG_BCN_CTRL, rtw_read8(iface, REG_BCN_CTRL) | DIS_TSF_UDT); + + iface->mlmeextpriv.en_hw_update_tsf = _FALSE; + } + } +#endif /* CONFIG_MI_WITH_MBSSID_CAM */ + + rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_ENTER); + + /* Save orignal RRSR setting. needed? */ + hal_data->RegRRSR = rtw_read16(adapter, REG_RRSR); + + #if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)) + if (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) { + /* set 718[1:0]=2'b00 to avoid BF scan hang */ + hal_data->backup_snd_ptcl_ctrl = rtw_read8(adapter, REG_SND_PTCL_CTRL_8812A); + rtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, (hal_data->backup_snd_ptcl_ctrl & 0xfc)); + } + #endif + + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) + StopTxBeacon(adapter); + } else { /* sitesurvey done */ + /* + * 1. enable rx data frame + * 2. config RCR not to receive different BSSID BCN or probe rsp + * 3. doesn't enable TSF update & buddy TSF right now to avoid HW conflict + * so, we enable TSF update when rx first BCN after sitesurvey done + */ + if (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE)) { + /* enable to rx data frame */ + rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF); + } + + rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_DONE); + +#ifdef CONFIG_MI_WITH_MBSSID_CAM + /*if ((rtw_mi_get_assoced_sta_num(adapter) == 1) && (!rtw_mi_check_status(adapter, MI_AP_MODE))) + rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)&(~DIS_TSF_UDT));*/ +#else + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + if (rtw_linked_check(iface) + && !MLME_IS_AP(iface) && !MLME_IS_MESH(iface) + ) { + /* enable HW TSF update when recive beacon*/ + /*if (iface->hw_port == HW_PORT1) + rtw_write8(iface, REG_BCN_CTRL_1, rtw_read8(iface, REG_BCN_CTRL_1)&(~(DIS_TSF_UDT))); + else + rtw_write8(iface, REG_BCN_CTRL, rtw_read8(iface, REG_BCN_CTRL)&(~(DIS_TSF_UDT))); + */ + iface->mlmeextpriv.en_hw_update_tsf = _TRUE; + } + } +#endif /* CONFIG_MI_WITH_MBSSID_CAM */ + + /* Restore orignal RRSR setting. needed? */ + rtw_write16(adapter, REG_RRSR, hal_data->RegRRSR); + + #if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)) + if (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) { + /* Restore orignal 0x718 setting*/ + rtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, hal_data->backup_snd_ptcl_ctrl); + } + #endif + + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) { + ResumeTxBeacon(adapter); + rtw_mi_tx_beacon_hdl(adapter); + } + } +} + +#ifdef CONFIG_TSF_RESET_OFFLOAD +static int rtw_hal_h2c_reset_tsf(_adapter *adapter, u8 reset_port) +{ + u8 buf[2]; + int ret; + + if (reset_port == HW_PORT0) { + buf[0] = 0x1; + buf[1] = 0; + } else { + buf[0] = 0x0; + buf[1] = 0x1; + } + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_RESET_TSF, 2, buf); + + return ret; +} + +int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port) +{ + u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0; + u32 reg_reset_tsf_cnt = (reset_port == HW_PORT0) ? + REG_FW_RESET_TSF_CNT_0 : REG_FW_RESET_TSF_CNT_1; + int ret; + + /* site survey will cause reset tsf fail */ + rtw_mi_buddy_scan_abort(adapter, _FALSE); + reset_cnt_after = reset_cnt_before = rtw_read8(adapter, reg_reset_tsf_cnt); + ret = rtw_hal_h2c_reset_tsf(adapter, reset_port); + if (ret != _SUCCESS) + return ret; + + while ((reset_cnt_after == reset_cnt_before) && (loop_cnt < 10)) { + rtw_msleep_os(100); + loop_cnt++; + reset_cnt_after = rtw_read8(adapter, reg_reset_tsf_cnt); + } + + return (loop_cnt >= 10) ? _FAIL : _SUCCESS; +} +#endif /* CONFIG_TSF_RESET_OFFLOAD */ + static void rtw_hal_set_hw_update_tsf(PADAPTER padapter) { struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; @@ -8863,13 +9933,14 @@ static void rtw_hal_set_hw_update_tsf(PADAPTER padapter) if (!pmlmeext->en_hw_update_tsf) return; - /* check REG_RCR bit is set */ - if (!(rtw_read32(padapter, REG_RCR) & RCR_CBSSID_BCN)) + /* check RCR */ + if (!rtw_hal_rcr_check(padapter, RCR_CBSSID_BCN)) return; - /* enable hw update tsf function for non-AP */ - if (rtw_linked_check(padapter) && - check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) { + /* enable hw update tsf function for non-AP and non-Mesh */ + if (rtw_linked_check(padapter) + && !MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter) + ) { #ifdef CONFIG_CONCURRENT_MODE if (padapter->hw_port == HW_PORT1) rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) & (~DIS_TSF_UDT)); @@ -8880,6 +9951,60 @@ static void rtw_hal_set_hw_update_tsf(PADAPTER padapter) pmlmeext->en_hw_update_tsf = _FALSE; } +static void hw_var_set_correct_tsf(_adapter *adapter) +{ +#ifdef CONFIG_MI_WITH_MBSSID_CAM + /*do nothing*/ +#else + u64 tsf; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); + + tsf = mlmeext->TSFValue - rtw_modular64(mlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024)) - 1024; /*us*/ + + if ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE + || (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) + StopTxBeacon(adapter); + + rtw_hal_correct_tsf(adapter, adapter->hw_port, tsf); + +#ifdef CONFIG_CONCURRENT_MODE + /* Update buddy port's TSF if it is SoftAP/Mesh for beacon TX issue! */ + if ((mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE + && (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) + ) { + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + int i; + _adapter *iface; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + if (iface == adapter) + continue; + + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) + && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE + ) { + rtw_hal_correct_tsf(iface, iface->hw_port, tsf); + #ifdef CONFIG_TSF_RESET_OFFLOAD + if (rtw_hal_reset_tsf(iface, iface->hw_port) == _FAIL) + RTW_INFO("%s-[ERROR] "ADPT_FMT" Reset port%d TSF fail\n" + , __func__, ADPT_ARG(iface), iface->hw_port); + #endif /* CONFIG_TSF_RESET_OFFLOAD*/ + } + } + } +#endif /* CONFIG_CONCURRENT_MODE */ + + if ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE + || (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) + ResumeTxBeacon(adapter); + +#endif /*CONFIG_MI_WITH_MBSSID_CAM*/ +} + #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode) @@ -8908,12 +10033,17 @@ s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset #endif #endif -#ifdef CONFIG_WMMPS +#ifdef CONFIG_WMMPS_STA void rtw_hal_update_uapsd_tid(_adapter *adapter) { - rtw_write8(adapter, REG_WMMPS_UAPSD_TID, 0xFF); + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + + /* write complement of pqospriv->uapsd_tid to mac register 0x693 because + it's designed for "0" represents "enable" and "1" represents "disable" */ + rtw_write8(adapter, REG_WMMPS_UAPSD_TID, (u8)(~pqospriv->uapsd_tid)); } -#endif +#endif /* CONFIG_WMMPS_STA */ #if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) /* For multi-port support, driver needs to inform the port ID to FW for btc operations */ @@ -8927,9 +10057,10 @@ s32 rtw_hal_set_wifi_port_id_cmd(_adapter *adapter) } #endif -void SetHwReg(_adapter *adapter, u8 variable, u8 *val) +u8 SetHwReg(_adapter *adapter, u8 variable, u8 *val) { HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 ret = _SUCCESS; switch (variable) { case HW_VAR_MEDIA_STATUS: { @@ -8948,6 +10079,18 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) case HW_VAR_BSSID: rtw_hal_set_bssid(adapter, val); break; + case HW_VAR_RCR: + ret = hw_var_rcr_config(adapter, *((u32 *)val)); + break; + case HW_VAR_ON_RCR_AM: + hw_var_set_rcr_am(adapter, 1); + break; + case HW_VAR_OFF_RCR_AM: + hw_var_set_rcr_am(adapter, 0); + break; + case HW_VAR_BEACON_INTERVAL: + hw_var_set_bcn_interval(adapter, *(u16 *)val); + break; #ifdef CONFIG_MBSSID_CAM case HW_VAR_MBSSID_CAM_WRITE: { u32 cmd = 0; @@ -8970,14 +10113,9 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) break; case HW_VAR_RCR_MBSSID_EN: if (*((u8 *)val)) - rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR) | RCR_ENMBID); - else { - u32 val32; - - val32 = rtw_read32(adapter, REG_RCR); - val32 &= ~(RCR_ENMBID); - rtw_write32(adapter, REG_RCR, val32); - } + rtw_hal_rcr_add(adapter, RCR_ENMBID); + else + rtw_hal_rcr_clear(adapter, RCR_ENMBID); break; #endif case HW_VAR_PORT_SWITCH: @@ -9078,40 +10216,79 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) break; #endif /*defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)*/ + case HW_VAR_MLME_SITESURVEY: + hw_var_set_mlme_sitesurvey(adapter, variable, val); + #ifdef CONFIG_BT_COEXIST + if (hal_data->EEPROMBluetoothCoexist == 1) + rtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE); + #endif + break; + case HW_VAR_EN_HW_UPDATE_TSF: rtw_hal_set_hw_update_tsf(adapter); break; + case HW_VAR_CORRECT_TSF: + hw_var_set_correct_tsf(adapter); + break; + case HW_VAR_APFM_ON_MAC: hal_data->bMacPwrCtrlOn = *val; RTW_INFO("%s: bMacPwrCtrlOn=%d\n", __func__, hal_data->bMacPwrCtrlOn); break; -#ifdef CONFIG_WMMPS +#ifdef CONFIG_WMMPS_STA case HW_VAR_UAPSD_TID: rtw_hal_update_uapsd_tid(adapter); break; -#endif +#endif /* CONFIG_WMMPS_STA */ #ifdef CONFIG_LPS_PG case HW_VAR_LPS_PG_HANDLE: rtw_hal_lps_pg_handler(adapter, *val); break; #endif +#ifdef CONFIG_LPS_LCLK_WD_TIMER + case HW_VAR_DM_IN_LPS_LCLK: + rtw_phydm_wd_lps_lclk_hdl(adapter); + break; +#endif + case HW_VAR_ENABLE_RX_BAR: + if (*val == _TRUE) { + /* enable RX BAR */ + u16 val16 = rtw_read16(adapter, REG_RXFLTMAP1); + val16 |= BIT(8); + rtw_write16(adapter, REG_RXFLTMAP1, val16); + } else { + /* disable RX BAR */ + u16 val16 = rtw_read16(adapter, REG_RXFLTMAP1); + + val16 &= (~BIT(8)); + rtw_write16(adapter, REG_RXFLTMAP1, val16); + } + RTW_INFO("[HW_VAR_ENABLE_RX_BAR] 0x%02X=0x%02X\n", + REG_RXFLTMAP1, rtw_read16(adapter, REG_RXFLTMAP1)); + break; default: if (0) RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n", FUNC_ADPT_ARG(adapter), variable); + ret = _FAIL; break; } + return ret; } void GetHwReg(_adapter *adapter, u8 variable, u8 *val) { HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u64 val64; switch (variable) { + case HW_VAR_MAC_ADDR: + rtw_hal_get_macaddr_port(adapter, val); + break; case HW_VAR_BASIC_RATE: *((u16 *)val) = hal_data->BasicRateSet; break; @@ -9133,6 +10310,41 @@ void GetHwReg(_adapter *adapter, u8 variable, u8 *val) case HW_VAR_APFM_ON_MAC: *val = hal_data->bMacPwrCtrlOn; break; + case HW_VAR_RCR: + hw_var_rcr_get(adapter, (u32 *)val); + break; + case HW_VAR_FWLPS_RF_ON: + /* When we halt NIC, we should check if FW LPS is leave. */ + if (rtw_is_surprise_removed(adapter) + || (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off) + ) { + /* + * If it is in HW/SW Radio OFF or IPS state, + * we do not check Fw LPS Leave, + * because Fw is unload. + */ + *val = _TRUE; + } else { + u32 rcr = 0; + + rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr); + if (rcr & (RCR_UC_MD_EN | RCR_BC_MD_EN | RCR_TIM_PARSER_EN)) + *val = _FALSE; + else + *val = _TRUE; + } + break; + + case HW_VAR_TSF: + /* read and save HIGH 32bits TSF value */ + val64 = rtw_read32(adapter, REG_TSFTR+4); + val64 = val64 << 32; + + /* read and save LOW 32bits TSF value */ + val64 |= rtw_read32(adapter, REG_TSFTR); + *((u64*)val) = val64; + break; + default: if (0) RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n", @@ -9142,6 +10354,27 @@ void GetHwReg(_adapter *adapter, u8 variable, u8 *val) } +static u32 _get_page_size(struct _ADAPTER *a) +{ +#ifdef RTW_HALMAC + struct dvobj_priv *d; + u32 size = 0; + int err = 0; + + + d = adapter_to_dvobj(a); + + err = rtw_halmac_get_page_size(d, &size); + if (!err) + return size; + + RTW_WARN(FUNC_ADPT_FMT ": Fail to get Page size!!(err=%d)\n", + FUNC_ADPT_ARG(a), err); +#endif /* RTW_HALMAC */ + + return PAGE_SIZE_128; +} + u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) { @@ -9159,9 +10392,6 @@ SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) case HAL_DEF_ANT_DETECT: hal_data->AntDetection = *((u8 *)value); break; - case HAL_DEF_DBG_DIS_PWT: - hal_data->bDisableTXPowerTraining = *((u8 *)value); - break; default: RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable); bResult = _FAIL; @@ -9216,6 +10446,35 @@ u8 rtw_hal_query_txbfee_rf_num(_adapter *adapter) return 1; } +#ifdef RTW_BEAMFORMING_VERSION_2 +void rtw_hal_beamforming_config_csirate(PADAPTER adapter) +{ + struct dm_struct *p_dm_odm; + struct beamforming_info *bf_info; + u8 fix_rate_enable = 0; + u8 new_csi_rate_idx; + + /* Acting as BFee */ + if (IS_BEAMFORMEE(adapter)) { + #if 0 + /* Do not enable now because it will affect MU performance and CTS/BA rate. 2016.07.19. by tynli. [PCIE-1660] */ + if (IS_HARDWARE_TYPE_8821C(Adapter)) + FixRateEnable = 1; /* Support after 8821C */ + #endif + + p_dm_odm = adapter_to_phydm(adapter); + bf_info = GET_BEAMFORM_INFO(adapter); + + rtw_halmac_bf_cfg_csi_rate(adapter_to_dvobj(adapter), + p_dm_odm->rssi_min, + bf_info->cur_csi_rpt_rate, + fix_rate_enable, &new_csi_rate_idx); + + if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) + bf_info->cur_csi_rpt_rate = new_csi_rate_idx; + } +} +#endif #endif u8 @@ -9234,7 +10493,7 @@ GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) pstapriv = &adapter->stapriv; psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress); if (psta) - *((int *)value) = psta->rssi_stat.undecorated_smoothed_pwdb; + *((int *)value) = psta->cmn.rssi_stat.rssi; } break; case HAL_DEF_DBG_DUMP_RXPKT: @@ -9246,14 +10505,8 @@ GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) case HAL_DEF_ANT_DETECT: *((u8 *)value) = hal_data->AntDetection; break; - case HAL_DEF_MACID_SLEEP: - *(u8 *)value = _FALSE; - break; case HAL_DEF_TX_PAGE_SIZE: - *((u32 *)value) = PAGE_SIZE_128; - break; - case HAL_DEF_DBG_DIS_PWT: - *(u8 *)value = hal_data->bDisableTXPowerTraining; + *((u32 *)value) = _get_page_size(adapter); break; case HAL_DEF_EXPLICIT_BEAMFORMER: case HAL_DEF_EXPLICIT_BEAMFORMEE: @@ -9278,222 +10531,6 @@ GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) return bResult; } -void SetHalODMVar( - PADAPTER Adapter, - HAL_ODM_VARIABLE eVariable, - PVOID pValue1, - BOOLEAN bSet) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv; - /* _irqL irqL; */ - switch (eVariable) { - case HAL_ODM_STA_INFO: { - struct sta_info *psta = (struct sta_info *)pValue1; - if (bSet) { - RTW_INFO("### Set STA_(%d) info ###\n", psta->mac_id); - odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta); - } else { - RTW_INFO("### Clean STA_(%d) info ###\n", psta->mac_id); - /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ - psta->rssi_level = 0; - odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL); - - /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ - } - } - break; - case HAL_ODM_P2P_STATE: - odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet); - break; - case HAL_ODM_WIFI_DISPLAY_STATE: - odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet); - break; - case HAL_ODM_REGULATION: - /* used to auto enable/disable adaptivity by SD7 */ - odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_2G, 0); - odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_5G, 0); - break; -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - case HAL_ODM_NOISE_MONITOR: { - struct noise_info *pinfo = (struct noise_info *)pValue1; - -#ifdef DBG_NOISE_MONITOR - RTW_INFO("### Noise monitor chan(%d)-bPauseDIG:%d,IGIValue:0x%02x,max_time:%d (ms) ###\n", - pinfo->chan, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time); -#endif - - pHalData->noise[pinfo->chan] = odm_inband_noise_monitor(podmpriv, pinfo->is_pause_dig, pinfo->igi_value, pinfo->max_time); - RTW_INFO("chan_%d, noise = %d (dBm)\n", pinfo->chan, pHalData->noise[pinfo->chan]); -#ifdef DBG_NOISE_MONITOR - RTW_INFO("noise_a = %d, noise_b = %d noise_all:%d\n", - podmpriv->noise_level.noise[ODM_RF_PATH_A], - podmpriv->noise_level.noise[ODM_RF_PATH_B], - podmpriv->noise_level.noise_all); -#endif - } - break; -#endif/*#ifdef CONFIG_BACKGROUND_NOISE_MONITOR*/ - - case HAL_ODM_INITIAL_GAIN: { - u8 rx_gain = *((u8 *)(pValue1)); - /*printk("rx_gain:%x\n",rx_gain);*/ - if (rx_gain == 0xff) {/*restore rx gain*/ - /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/ - odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain); - } else { - /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/ - /*odm_write_dig(podmpriv,rx_gain);*/ - odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain); - } - } - break; - case HAL_ODM_FA_CNT_DUMP: - if (*((u8 *)pValue1)) - podmpriv->debug_components |= (ODM_COMP_DIG | ODM_COMP_FA_CNT); - else - podmpriv->debug_components &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT); - break; - case HAL_ODM_DBG_FLAG: - odm_cmn_info_update(podmpriv, ODM_CMNINFO_DBG_COMP, *((u8Byte *)pValue1)); - break; - case HAL_ODM_DBG_LEVEL: - odm_cmn_info_update(podmpriv, ODM_CMNINFO_DBG_LEVEL, *((u4Byte *)pValue1)); - break; - case HAL_ODM_RX_INFO_DUMP: { - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(podmpriv , PHYDM_FALSEALMCNT); - struct _dynamic_initial_gain_threshold_ *pDM_DigTable = &podmpriv->dm_dig_table; - void *sel; - - sel = pValue1; - - _RTW_PRINT_SEL(sel , "============ Rx Info dump ===================\n"); - _RTW_PRINT_SEL(sel , "is_linked = %d, rssi_min = %d(%%), current_igi = 0x%x\n", podmpriv->is_linked, podmpriv->rssi_min, pDM_DigTable->cur_ig_value); - _RTW_PRINT_SEL(sel , "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n", false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all); - - if (podmpriv->is_linked) { - _RTW_PRINT_SEL(sel , "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate)); - _RTW_PRINT_SEL(sel , " RSSI_A = %d(%%), RSSI_B = %d(%%)\n", podmpriv->RSSI_A, podmpriv->RSSI_B); -#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA - rtw_dump_raw_rssi_info(Adapter, sel); -#endif - } - } - break; - case HAL_ODM_RX_Dframe_INFO: { - void *sel; - - sel = pValue1; - - /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/ -#ifdef DBG_RX_DFRAME_RAW_DATA - rtw_dump_rx_dframe_info(Adapter, sel); -#endif - } - break; - -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - case HAL_ODM_AUTO_CHNL_SEL: { - ACS_OP acs_op = *(ACS_OP *)pValue1; - - if (ACS_INIT == acs_op) { -#ifdef DBG_AUTO_CHNL_SEL_NHM - RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_INIT\n", ADPT_ARG(Adapter)); -#endif - odm_AutoChannelSelectInit(podmpriv); - } else if (ACS_RESET == acs_op) { - /* Reset statistics for auto channel selection mechanism.*/ -#ifdef DBG_AUTO_CHNL_SEL_NHM - RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_RESET\n", ADPT_ARG(Adapter)); -#endif - odm_auto_channel_select_reset(podmpriv); - - } else if (ACS_SELECT == acs_op) { - /* Collect NHM measurement result after current channel */ -#ifdef DBG_AUTO_CHNL_SEL_NHM - RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_SELECT, CH(%d)\n", ADPT_ARG(Adapter), rtw_get_acs_channel(Adapter)); -#endif - odm_AutoChannelSelect(podmpriv, rtw_get_acs_channel(Adapter)); - } else - RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: Unexpected OP\n", ADPT_ARG(Adapter)); - - } - break; -#endif -#ifdef CONFIG_ANTENNA_DIVERSITY - case HAL_ODM_ANTDIV_SELECT: { - u8 antenna = (*(u8 *)pValue1); - - /*switch antenna*/ - odm_update_rx_idle_ant(&pHalData->odmpriv, antenna); - /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/ - - } - break; -#endif - - default: - break; - } -} - -void GetHalODMVar( - PADAPTER Adapter, - HAL_ODM_VARIABLE eVariable, - PVOID pValue1, - PVOID pValue2) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv; - - switch (eVariable) { -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - case HAL_ODM_NOISE_MONITOR: { - u8 chan = *(u8 *)pValue1; - *(s16 *)pValue2 = pHalData->noise[chan]; -#ifdef DBG_NOISE_MONITOR - RTW_INFO("### Noise monitor chan(%d)-noise:%d (dBm) ###\n", - chan, pHalData->noise[chan]); -#endif - } - break; -#endif/*#ifdef CONFIG_BACKGROUND_NOISE_MONITOR*/ - case HAL_ODM_DBG_FLAG: - *((u8Byte *)pValue1) = podmpriv->debug_components; - break; - case HAL_ODM_DBG_LEVEL: - *((u4Byte *)pValue1) = podmpriv->debug_level; - break; - -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - case HAL_ODM_AUTO_CHNL_SEL: { -#ifdef DBG_AUTO_CHNL_SEL_NHM - RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: GET_BEST_CHAN\n", ADPT_ARG(Adapter)); -#endif - /* Retrieve better channel from NHM mechanism */ - if (IsSupported24G(Adapter->registrypriv.wireless_mode)) - *((u8 *)(pValue1)) = odm_get_auto_channel_select_result(podmpriv, BAND_ON_2_4G); - if (is_supported_5g(Adapter->registrypriv.wireless_mode)) - *((u8 *)(pValue2)) = odm_get_auto_channel_select_result(podmpriv, BAND_ON_5G); - } - break; -#endif -#ifdef CONFIG_ANTENNA_DIVERSITY - case HAL_ODM_ANTDIV_SELECT: { - struct _FAST_ANTENNA_TRAINNING_ *pDM_FatTable = &podmpriv->dm_fat_table; - *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant; - } - break; -#endif - case HAL_ODM_INITIAL_GAIN: { - struct _dynamic_initial_gain_threshold_ *pDM_DigTable = &podmpriv->dm_dig_table; - *((u8 *)pValue1) = pDM_DigTable->cur_ig_value; - } - break; - default: - break; - } -} BOOLEAN eqNByte( @@ -9842,6 +10879,10 @@ void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel) #ifdef DBG_RX_DFRAME_RAW_DATA void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel) { +#define DBG_RX_DFRAME_RAW_DATA_UC 0 +#define DBG_RX_DFRAME_RAW_DATA_BMC 1 +#define DBG_RX_DFRAME_RAW_DATA_TYPES 2 + _irqL irqL; u8 isCCKrate, rf_path; struct recv_priv *precvpriv = &(padapter->recvpriv); @@ -9849,9 +10890,8 @@ void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel) struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta; struct sta_recv_dframe_info *psta_dframe_info; - int i; + int i, j; _list *plist, *phead; - char *BW; u8 bc_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; u8 null_addr[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; @@ -9869,53 +10909,38 @@ void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel) plist = get_next(plist); if (psta) { - psta_dframe_info = &psta->sta_dframe_info; - if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), 6) != _TRUE)) { - - - isCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE; - - switch (psta_dframe_info->sta_bw_mode) { - - case CHANNEL_WIDTH_20: - BW = "20M"; - break; - - case CHANNEL_WIDTH_40: - BW = "40M"; - break; - - case CHANNEL_WIDTH_80: - BW = "80M"; - break; - - case CHANNEL_WIDTH_160: - BW = "160M"; - break; - - default: - BW = ""; - break; - } + if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), 6) != _TRUE)) { RTW_PRINT_SEL(sel, "==============================\n"); - _RTW_PRINT_SEL(sel, "macaddr =" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); - _RTW_PRINT_SEL(sel, "BW=%s, sgi =%d\n", BW, psta_dframe_info->sta_sgi); - _RTW_PRINT_SEL(sel, "Rx_Data_Rate = %s\n", HDATA_RATE(psta_dframe_info->sta_data_rate)); - - for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) { - - if (!isCCKrate) { - - _RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)", rf_path, psta_dframe_info->sta_RxPwr[rf_path]); - _RTW_PRINT_SEL(sel , ",rx_ofdm_snr:%d(dB)\n", psta_dframe_info->sta_ofdm_snr[rf_path]); - - } else - - _RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)\n", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100); + RTW_PRINT_SEL(sel, "macaddr =" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); + + for (j = 0; j < DBG_RX_DFRAME_RAW_DATA_TYPES; j++) { + if (j == DBG_RX_DFRAME_RAW_DATA_UC) { + psta_dframe_info = &psta->sta_dframe_info; + RTW_PRINT_SEL(sel, "\n"); + RTW_PRINT_SEL(sel, "Unicast:\n"); + } else if (j == DBG_RX_DFRAME_RAW_DATA_BMC) { + psta_dframe_info = &psta->sta_dframe_info_bmc; + RTW_PRINT_SEL(sel, "\n"); + RTW_PRINT_SEL(sel, "Broadcast/Multicast:\n"); + } + + isCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE; + + RTW_PRINT_SEL(sel, "BW=%s, sgi =%d\n", ch_width_str(psta_dframe_info->sta_bw_mode), psta_dframe_info->sta_sgi); + RTW_PRINT_SEL(sel, "Rx_Data_Rate = %s\n", HDATA_RATE(psta_dframe_info->sta_data_rate)); + + for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) { + if (!isCCKrate) { + RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)", rf_path, psta_dframe_info->sta_RxPwr[rf_path]); + _RTW_PRINT_SEL(sel , ",rx_ofdm_snr:%d(dB)\n", psta_dframe_info->sta_ofdm_snr[rf_path]); + } else + RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)\n", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100); + } } + } } } @@ -9936,7 +10961,7 @@ void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; struct sta_info *psta = prframe->u.hdr.psta; - struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)(&pattrib->phy_info); + struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info; struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info; psample_pkt_rssi->data_rate = pattrib->data_rate; ptr = prframe->u.hdr.rx_data; @@ -9963,9 +10988,13 @@ void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe) /*RTW_INFO("=>%s WIFI_DATA_TYPE or WIFI_QOS_DATA_TYPE\n", __FUNCTION__);*/ if (psta) { - psta_dframe_info = &psta->sta_dframe_info; - /*RTW_INFO("=>%s psta->hwaddr="MAC_FMT" !\n", __FUNCTION__, MAC_ARG(psta->hwaddr));*/ - if ((_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN) != _TRUE) || (padapter->registrypriv.mp_mode == 1)) { + if (IS_MCAST(get_ra(get_recvframe_data(prframe)))) + psta_dframe_info = &psta->sta_dframe_info_bmc; + else + psta_dframe_info = &psta->sta_dframe_info; + /*RTW_INFO("=>%s psta->cmn.mac_addr="MAC_FMT" !\n", + __FUNCTION__, MAC_ARG(psta->cmn.mac_addr));*/ + if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) || (padapter->registrypriv.mp_mode == 1)) { psta_dframe_info->sta_data_rate = pattrib->data_rate; psta_dframe_info->sta_sgi = pattrib->sgi; psta_dframe_info->sta_bw_mode = pattrib->bw; @@ -9986,61 +11015,6 @@ void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe) } - -int check_phy_efuse_tx_power_info_valid(PADAPTER padapter) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - u8 *pContent = pHalData->efuse_eeprom_data; - int index = 0; - u16 tx_index_offset = 0x0000; - - switch (rtw_get_chip_type(padapter)) { - case RTL8723B: - tx_index_offset = EEPROM_TX_PWR_INX_8723B; - break; - case RTL8703B: - tx_index_offset = EEPROM_TX_PWR_INX_8703B; - break; - case RTL8723D: - tx_index_offset = EEPROM_TX_PWR_INX_8723D; - break; - case RTL8188E: - tx_index_offset = EEPROM_TX_PWR_INX_88E; - break; - case RTL8188F: - tx_index_offset = EEPROM_TX_PWR_INX_8188F; - break; - case RTL8192E: - tx_index_offset = EEPROM_TX_PWR_INX_8192E; - break; - case RTL8821: - tx_index_offset = EEPROM_TX_PWR_INX_8821; - break; - case RTL8812: - tx_index_offset = EEPROM_TX_PWR_INX_8812; - break; - case RTL8814A: - tx_index_offset = EEPROM_TX_PWR_INX_8814; - break; - case RTL8822B: - tx_index_offset = EEPROM_TX_PWR_INX_8822B; - break; - case RTL8821C: - tx_index_offset = EEPROM_TX_PWR_INX_8821C; - break; - default: - tx_index_offset = 0x0010; - break; - } - - /* TODO: chacking length by ICs */ - for (index = 0 ; index < 11 ; index++) { - if (pContent[tx_index_offset + index] == 0xFF) - return _FALSE; - } - return _TRUE; -} - int hal_efuse_macaddr_offset(_adapter *adapter) { u8 interface_type = 0; @@ -10192,22 +11166,11 @@ void rtw_dump_cur_efuse(PADAPTER padapter) return; } +#ifdef CONFIG_RTW_DEBUG if (hal_data->efuse_file_status == EFUSE_FILE_LOADED) - RTW_INFO("EFUSE FILE\n"); + RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "EFUSE FILE", hal_data->efuse_eeprom_data, mapsize); else - RTW_INFO("HW EFUSE\n"); - -#ifdef CONFIG_RTW_DEBUG - for (i = 0; i < mapsize; i++) { - if (i % 16 == 0) - RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i); - - _RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s" - , hal_data->efuse_eeprom_data[i] - , ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? " " : " ") - ); - } - _RTW_PRINT_SEL(RTW_DBGDUMP, "\n"); + RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "HW EFUSE", hal_data->efuse_eeprom_data, mapsize); #endif } @@ -10260,6 +11223,9 @@ int hal_config_macaddr(_adapter *adapter, bool autoload_fail) int addr_offset = hal_efuse_macaddr_offset(adapter); u8 *hw_addr = NULL; int ret = _SUCCESS; +#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI) + u8 ft_mac_addr[ETH_ALEN] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff}; /* FT USB2 for 8822B */ +#endif if (autoload_fail) goto bypass_hw_pg; @@ -10279,6 +11245,11 @@ int hal_config_macaddr(_adapter *adapter, bool autoload_fail) hw_addr = addr; } +#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI) + if (_rtw_memcmp(hw_addr, ft_mac_addr, ETH_ALEN)) + hw_addr[0] = 0xff; +#endif + /* check hw pg data */ if (hw_addr && rtw_check_invalid_mac_address(hw_addr, _TRUE) == _FALSE) { _rtw_memcpy(hal_data->EEPROMMACAddr, hw_addr, ETH_ALEN); @@ -10334,18 +11305,18 @@ void rtw_bb_rf_gain_offset(_adapter *padapter) } #if defined(CONFIG_RTL8723B) - if (value & BIT4 || (registry_par->RegPwrTrimEnable == 1)) { + if (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) { RTW_INFO("Offset RF Gain.\n"); RTW_INFO("Offset RF Gain. pHalData->EEPROMRFGainVal=0x%x\n", pHalData->EEPROMRFGainVal); if (pHalData->EEPROMRFGainVal != 0xff) { - if (pHalData->ant_path == ODM_RF_PATH_A) + if (pHalData->ant_path == RF_PATH_A) GainValue = (pHalData->EEPROMRFGainVal & 0x0f); else GainValue = (pHalData->EEPROMRFGainVal & 0xf0) >> 4; - RTW_INFO("Ant PATH_%d GainValue Offset = 0x%x\n", (pHalData->ant_path == ODM_RF_PATH_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B), GainValue); + RTW_INFO("Ant PATH_%d GainValue Offset = 0x%x\n", (pHalData->ant_path == RF_PATH_A) ? (RF_PATH_A) : (RF_PATH_B), GainValue); for (i = 0; i < ArrayLen; i += 2) { /* RTW_INFO("ArrayLen in =%d ,Array 1 =0x%x ,Array2 =0x%x\n",i,Array[i],Array[i]+1); */ @@ -10373,7 +11344,7 @@ void rtw_bb_rf_gain_offset(_adapter *padapter) RTW_INFO("Using the default RF gain.\n"); #elif defined(CONFIG_RTL8188E) - if (value & BIT4 || (registry_par->RegPwrTrimEnable == 1)) { + if (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) { RTW_INFO("8188ES Offset RF Gain.\n"); RTW_INFO("8188ES Offset RF Gain. EEPROMRFGainVal=0x%x\n", pHalData->EEPROMRFGainVal); @@ -10540,7 +11511,7 @@ void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer) return; #ifdef RTW_HALMAC - if (IS_HARDWARE_TYPE_8822BU(padapter)) + if (IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8821CU(padapter)) rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, NULL); #else /* !RTW_HALMAC */ if (IS_HARDWARE_TYPE_8821U(padapter)) { /* || IS_HARDWARE_TYPE_8192EU(padapter)) */ @@ -10590,7 +11561,7 @@ inline u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qse struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); u8 chk_rst = _SUCCESS; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) return chk_rst; /* if((pre_qsel == 0xFF)||(next_qsel== 0xFF)) */ @@ -10655,7 +11626,9 @@ u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num) { u8 value = 0; u8 direction = 0; - u32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2; + u32 gpio_pin_input_val = REG_GPIO_PIN_CTRL; + u32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1; + u32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2; u8 gpio_num_to_set = gpio_num; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); @@ -10668,18 +11641,20 @@ u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num) LeaveAllPowerSaveModeDirect(adapter); if (gpio_num > 7) { - gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2; + gpio_pin_input_val = REG_GPIO_PIN_CTRL_2; + gpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1; + gpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2; gpio_num_to_set = gpio_num - 8; } /* Read GPIO Direction */ - direction = (rtw_read8(adapter, gpio_ctrl_reg_to_set) & BIT(gpio_num_to_set)) >> gpio_num; + direction = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set; /* According the direction to read register value */ if (direction) - value = (rtw_read8(adapter, gpio_ctrl_reg_to_set) & BIT(gpio_num_to_set)) >> gpio_num; + value = (rtw_read8(adapter, gpio_pin_output_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set; else - value = (rtw_read8(adapter, gpio_ctrl_reg_to_set) & BIT(gpio_num_to_set)) >> gpio_num; + value = (rtw_read8(adapter, gpio_pin_input_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set; rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); RTW_INFO("%s direction=%d value=%d\n", __FUNCTION__, direction, value); @@ -10691,7 +11666,8 @@ int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh) { u8 direction = 0; u8 res = -1; - u32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2; + u32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1; + u32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2; u8 gpio_num_to_set = gpio_num; if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL) @@ -10702,19 +11678,20 @@ int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh) LeaveAllPowerSaveModeDirect(adapter); if (gpio_num > 7) { - gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2; + gpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1; + gpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2; gpio_num_to_set = gpio_num - 8; } /* Read GPIO direction */ - direction = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num; + direction = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set; /* If GPIO is output direction, setting value. */ if (direction) { if (isHigh) - rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) | BIT(gpio_num_to_set)); + rtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) | BIT(gpio_num_to_set)); else - rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) & ~BIT(gpio_num_to_set)); + rtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) & ~BIT(gpio_num_to_set)); RTW_INFO("%s Set gpio %x[%d]=%d\n", __FUNCTION__, REG_GPIO_PIN_CTRL + 1, gpio_num, isHigh); res = 0; @@ -11111,61 +12088,39 @@ void rtw_dump_rx_counters(_adapter *padapter) } } #endif -void rtw_get_noise(_adapter *padapter) +u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta) { -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct noise_info info; - if (rtw_linked_check(padapter)) { - info.bPauseDIG = _TRUE; - info.IGIValue = 0x1e; - info.max_time = 100;/* ms */ - info.chan = pmlmeext->cur_channel ;/* rtw_get_oper_ch(padapter); */ - rtw_ps_deny(padapter, PS_DENY_IOCTL); - LeaveAllPowerSaveModeDirect(padapter); - - rtw_hal_set_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &info, _FALSE); - /* odm_inband_noise_monitor(podmpriv,_TRUE,0x20,100); */ - rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); - rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &(info.chan), &(padapter->recvpriv.noise)); -#ifdef DBG_NOISE_MONITOR - RTW_INFO("chan:%d,noise_level:%d\n", info.chan, padapter->recvpriv.noise); -#endif - } -#endif - -} -u8 rtw_get_current_tx_sgi(_adapter *padapter, u8 macid) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct _rate_adaptive_table_ *pRA_Table = &pDM_Odm->dm_ra_table; u8 curr_tx_sgi = 0; + struct ra_sta_info *ra_info; -#if defined(CONFIG_RTL8188E) - curr_tx_sgi = odm_ra_get_decision_rate_8188e(pDM_Odm, macid); -#else - curr_tx_sgi = ((pRA_Table->link_tx_rate[macid]) & 0x80) >> 7; -#endif + if (!psta) + return curr_tx_sgi; - return curr_tx_sgi; + if (padapter->fix_rate == 0xff) { + ra_info = &psta->cmn.ra_info; + curr_tx_sgi = ((ra_info->curr_tx_rate) & 0x80) >> 7; + } else { + curr_tx_sgi = ((padapter->fix_rate) & 0x80) >> 7; + } + return curr_tx_sgi; } -u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid) +u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct _rate_adaptive_table_ *pRA_Table = &pDM_Odm->dm_ra_table; u8 rate_id = 0; + struct ra_sta_info *ra_info; -#if (RATE_ADAPTIVE_SUPPORT == 1) - rate_id = odm_ra_get_decision_rate_8188e(pDM_Odm, macid); -#else - rate_id = (pRA_Table->link_tx_rate[macid]) & 0x7f; -#endif + if (!psta) + return rate_id; - return rate_id; + if (padapter->fix_rate == 0xff) { + ra_info = &psta->cmn.ra_info; + rate_id = ra_info->curr_tx_rate & 0x7f; + } else { + rate_id = padapter->fix_rate & 0x7f; + } + return rate_id; } void update_IOT_info(_adapter *padapter) @@ -11194,30 +12149,6 @@ void update_IOT_info(_adapter *padapter) } } -#ifdef CONFIG_AUTO_CHNL_SEL_NHM -void rtw_acs_start(_adapter *padapter, bool bStart) -{ - if (_TRUE == bStart) { - ACS_OP acs_op = ACS_INIT; - - rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE); - rtw_set_acs_channel(padapter, 0); - SET_ACS_STATE(padapter, ACS_ENABLE); - } else { - SET_ACS_STATE(padapter, ACS_DISABLE); -#ifdef DBG_AUTO_CHNL_SEL_NHM - if (1) { - u8 best_24g_ch = 0; - u8 best_5g_ch = 0; - - rtw_hal_get_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &(best_24g_ch), &(best_5g_ch)); - RTW_INFO("[ACS-"ADPT_FMT"] Best 2.4G CH:%u\n", ADPT_ARG(padapter), best_24g_ch); - RTW_INFO("[ACS-"ADPT_FMT"] Best 5G CH:%u\n", ADPT_ARG(padapter), best_5g_ch); - } -#endif - } -} -#endif /* TODO: merge with phydm, see odm_SetCrystalCap() */ void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap) @@ -11414,6 +12345,8 @@ void dump_hal_spec(void *sel, _adapter *adapter) _RTW_PRINT_SEL(sel, "%s ", _wl_func_str[i]); } _RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "pg_txpwr_saddr:0x%X\n", hal_spec->pg_txpwr_saddr); } inline bool hal_chk_band_cap(_adapter *adapter, u8 cap) @@ -11480,9 +12413,9 @@ inline bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode) /* * hal_largest_bw - starting from in_bw, get largest bw supported by HAL * @adapter: -* @in_bw: starting bw, value of CHANNEL_WIDTH +* @in_bw: starting bw, value of enum channel_width * -* Returns: value of CHANNEL_WIDTH +* Returns: value of enum channel_width */ u8 hal_largest_bw(_adapter *adapter, u8 in_bw) { @@ -11523,38 +12456,36 @@ void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf) void ResumeTxBeacon(_adapter *padapter) { - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - - - /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ - /* which should be read from register to a global variable. */ - +#ifdef CONFIG_MI_WITH_MBSSID_CAM +#else rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) | BIT(6)); - /*TBTT hold time :4ms 0x540[19:8]*/ - rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, - TBTT_PROBIHIT_HOLD_TIME & 0xFF); +#ifdef RTW_HALMAC + /* Add this for driver using HALMAC because driver doesn't have setup time init by self */ + /* TBTT setup time */ + rtw_write8(padapter, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME); +#endif + + /* TBTT hold time: 0x540[19:8] */ + rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME & 0xFF); rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, - (rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROBIHIT_HOLD_TIME >> 8)); + (rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME >> 8)); +#endif } void StopTxBeacon(_adapter *padapter) { - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - - - /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ - /* which should be read from register to a global variable. */ - +#ifdef CONFIG_MI_WITH_MBSSID_CAM +#else rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) & (~BIT6)); - rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64); + /* TBTT hold time: 0x540[19:8] */ + rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF); rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, - (rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0)); - - /*CheckFwRsvdPageContent(padapter);*/ /* 2010.06.23. Added by tynli. */ + (rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8)); +#endif } #ifdef CONFIG_MI_WITH_MBSSID_CAM /*HW port0 - MBSS*/ @@ -11562,7 +12493,7 @@ void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode) { RTW_INFO("%s()-"ADPT_FMT" mode = %d\n", __func__, ADPT_ARG(Adapter), mode); - rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) & (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN))); + rtw_hal_rcr_set_chk_bssid(Adapter, MLME_ACTION_NONE); /* disable Port0 TSF update*/ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) | DIS_TSF_UDT); @@ -11571,7 +12502,7 @@ void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode) Set_MSR(Adapter, mode); if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) { - if (!rtw_mi_check_status(Adapter, MI_AP_MODE)) + if (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter)) StopTxBeacon(Adapter); rtw_write8(Adapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM);/*disable atim wnd*/ @@ -11591,9 +12522,9 @@ void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode) rtw_write8(Adapter, REG_BCNDMATIM, 0x02); /* 2ms */ /*rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);*/ - rtw_write8(Adapter, REG_ATIMWND, 0x0a); /* 10ms */ + rtw_write8(Adapter, REG_ATIMWND, 0x0c); /* 12ms */ rtw_write16(Adapter, REG_BCNTCFG, 0x00); - rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04); + rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */ /*reset TSF*/ @@ -11602,6 +12533,9 @@ void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode) /*enable BCN0 Function for if1*/ /*don't enable update TSF0 for if1 (due to TSF update when beacon,probe rsp are received)*/ rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB)); + #ifdef CONFIG_BCN_XMIT_PROTECT + rtw_write8(Adapter, REG_CCK_CHECK, rtw_read8(Adapter, REG_CCK_CHECK) | BIT_EN_BCN_PKT_REL); + #endif if (IS_HARDWARE_TYPE_8821(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter))/* select BCN on port 0 for DualBeacon*/ rtw_write8(Adapter, REG_CCK_CHECK, rtw_read8(Adapter, REG_CCK_CHECK) & (~BIT_BCN_PORT_SEL)); @@ -11749,18 +12683,146 @@ void rtw_dump_phy_cap(void *sel, _adapter *adapter) #endif } -void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter) +inline s16 translate_dbm_to_percentage(s16 signal) +{ + if ((signal <= -100) || (signal >= 20)) + return 0; + else if (signal >= 0) + return 100; + else + return 100 + signal; +} + +#ifdef CONFIG_SWTIMER_BASED_TXBCN +#ifdef CONFIG_BCN_RECOVERY +#define REG_CPU_MGQ_INFO 0x041C +#define BIT_BCN_POLL BIT(28) +u8 rtw_ap_bcn_recovery(_adapter *padapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + + if (hal_data->issue_bcn_fail >= 2) { + RTW_ERR("%s ISSUE BCN Fail\n", __func__); + rtw_write8(padapter, REG_CPU_MGQ_INFO + 3, 0x10); + hal_data->issue_bcn_fail = 0; + } + return _SUCCESS; +} +#endif /*CONFIG_BCN_RECOVERY*/ + +#ifdef CONFIG_BCN_XMIT_PROTECT +u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms) +{ + u32 start_time = rtw_get_current_time(); + u8 bcn_queue_empty = _FALSE; + + do { + if (rtw_read16(padapter, REG_TXPKT_EMPTY) & BIT(11)) { + bcn_queue_empty = _TRUE; + break; + } + } while (rtw_get_passing_time_ms(start_time) <= (txbcn_timer_ms + 10)); + + if (bcn_queue_empty == _FALSE) + RTW_ERR("%s BCN queue not empty\n", __func__); + + return bcn_queue_empty; +} +#endif /*CONFIG_BCN_XMIT_PROTECT*/ +#endif /*CONFIG_SWTIMER_BASED_TXBCN*/ + +static void _rf_type_to_ant_path(enum rf_type rf, enum bb_path *tx, + enum bb_path *rx) { + if (tx) { + switch (rf) { + case RF_1T1R: + case RF_1T2R: + *tx = BB_PATH_A; + break; + case RF_2T2R: + case RF_2T3R: + case RF_2T4R: + *tx = BB_PATH_AB; + break; + case RF_3T3R: + case RF_3T4R: + *tx = BB_PATH_ABC; + break; + case RF_4T4R: + default: + *tx = BB_PATH_ABCD; + break; + } + } + + if (rx) { + switch (rf) { + case RF_1T1R: + *rx = BB_PATH_A; + break; + case RF_1T2R: + case RF_2T2R: + *rx = BB_PATH_AB; + break; + case RF_2T3R: + case RF_3T3R: + *rx = BB_PATH_ABC; + break; + case RF_2T4R: + case RF_3T4R: + case RF_4T4R: + default: + *rx = BB_PATH_ABCD; + break; + } + } +} + +/** + * rtw_hal_get_rf_path() - Get RF path related information + * @d: struct dvobj_priv* + * @type: RF type, nTnR + * @tx: Tx path + * @rx: Rx path + * + * Get RF type, TX path and RX path information. + */ +void rtw_hal_get_rf_path(struct dvobj_priv *d, enum rf_type *type, + enum bb_path *tx, enum bb_path *rx) +{ + struct _ADAPTER *a; + u8 val8 = RF_1T1R; + enum rf_type rf; + + + a = dvobj_get_primary_adapter(d); + + rtw_hal_get_hwreg(a, HW_VAR_RF_TYPE, &val8); + rf = (enum rf_type)val8; + if (type) + *type = rf; + + if (tx || rx) + _rf_type_to_ant_path(rf, tx, rx); +} + +#ifdef RTW_CHANNEL_SWITCH_OFFLOAD +void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw) +{ + u8 h2c[H2C_SINGLE_CHANNELSWITCH_V2_LEN] = {0}; PHAL_DATA_TYPE hal; - struct PHY_DM_STRUCT *p_dm_odm; + struct submit_ctx *chsw_sctx; hal = GET_HAL_DATA(adapter); - p_dm_odm = &hal->odmpriv; + chsw_sctx = &hal->chsw_sctx; - if (hal->RegIQKFWOffload) - rtw_sctx_init(&hal->iqk_sctx, 0); + SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(h2c, central_ch); + SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(h2c, pri_ch_idx); + SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(h2c, bw); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_IQKFWOFFLOAD, hal->RegIQKFWOffload); - RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload?"enable":"disable"); + rtw_sctx_init(chsw_sctx, 10); + rtw_hal_fill_h2c_cmd(adapter, H2C_SINGLE_CHANNELSWITCH_V2, H2C_SINGLE_CHANNELSWITCH_V2_LEN, h2c); + rtw_sctx_wait(chsw_sctx, __func__); } - +#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ diff --git a/hal/hal_com_c2h.h b/hal/hal_com_c2h.h index d6cca9a..1efabc9 100644 --- a/hal/hal_com_c2h.h +++ b/hal/hal_com_c2h.h @@ -70,6 +70,10 @@ typedef enum _C2H_EVT { C2H_DEFEATURE_DBG = 0x22, C2H_CUSTOMER_STR_RPT = 0x24, C2H_CUSTOMER_STR_RPT_2 = 0x25, + C2H_WLAN_INFO = 0x27, +#ifdef RTW_PER_CMD_SUPPORT_FW + C2H_PER_RATE_RPT = 0x2c, +#endif C2H_DEFEATURE_RSVD = 0xFD, C2H_EXTEND = 0xff, } C2H_EVT; @@ -111,4 +115,9 @@ int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len); int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len); #endif /* CONFIG_RTW_CUSTOMER_STR */ +#ifdef RTW_PER_CMD_SUPPORT_FW +/* C2H_PER_RATE_RPT, 0x2c */ +int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len); +#endif + #endif /* __COMMON_C2H_H__ */ diff --git a/hal/hal_com_phycfg.c b/hal/hal_com_phycfg.c index 3f3c491..04df339 100644 --- a/hal/hal_com_phycfg.c +++ b/hal/hal_com_phycfg.c @@ -17,6 +17,12 @@ #include #include +#define PG_TXPWR_1PATH_BYTE_NUM_2G 18 +#define PG_TXPWR_BASE_BYTE_NUM_2G 11 + +#define PG_TXPWR_1PATH_BYTE_NUM_5G 24 +#define PG_TXPWR_BASE_BYTE_NUM_5G 14 + #define PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) (((_pg_v) & 0xf0) >> 4) #define PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) ((_pg_v) & 0x0f) #define PG_TXPWR_MSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_MSB_DIFF_S4BIT(_pg_v)) @@ -575,8 +581,6 @@ u16 hal_load_pg_txpwr_info_path_2g( const struct map_t *txpwr_map, u16 pg_offset) { -#define PG_TXPWR_1PATH_BYTE_NUM_2G 18 - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); u16 offset = pg_offset; u8 group, tx_idx; @@ -705,8 +709,6 @@ u16 hal_load_pg_txpwr_info_path_5g( const struct map_t *txpwr_map, u16 pg_offset) { -#define PG_TXPWR_1PATH_BYTE_NUM_5G 24 - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); u16 offset = pg_offset; u8 group, tx_idx; @@ -878,7 +880,7 @@ void hal_load_pg_txpwr_info( hal_init_pg_txpwr_info_5g(adapter, pwr_info_5g); select_src: - pg_offset = 0x10; + pg_offset = hal_spec->pg_txpwr_saddr; switch (txpwr_src) { case PG_TXPWR_SRC_PG_DATA: @@ -927,6 +929,79 @@ void hal_load_pg_txpwr_info( return; } +#ifdef CONFIG_EFUSE_CONFIG_FILE + +#define EFUSE_POWER_INDEX_INVALID 0xFF + +static u8 _check_phy_efuse_tx_power_info_valid(u8 *pg_data, int base_len, u16 pg_offset) +{ + int ff_cnt = 0; + int i; + + for (i = 0; i < base_len; i++) { + if (*(pg_data + pg_offset + i) == 0xFF) + ff_cnt++; + } + + if (ff_cnt == 0) + return _TRUE; + else if (ff_cnt == base_len) + return _FALSE; + else + return EFUSE_POWER_INDEX_INVALID; +} + +int check_phy_efuse_tx_power_info_valid(_adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 *pg_data = hal_data->efuse_eeprom_data; + u16 pg_offset = hal_spec->pg_txpwr_saddr; + u8 path; + u8 valid_2g_path_bmp = 0; +#ifdef CONFIG_IEEE80211_BAND_5GHZ + u8 valid_5g_path_bmp = 0; +#endif + int result = _FALSE; + + for (path = 0; path < MAX_RF_PATH; path++) { + u8 ret = _FALSE; + + if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) + break; + + if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) { + ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_2G, pg_offset); + if (ret == _TRUE) + valid_2g_path_bmp |= BIT(path); + else if (ret == EFUSE_POWER_INDEX_INVALID) + return _FALSE; + } + pg_offset += PG_TXPWR_1PATH_BYTE_NUM_2G; + + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) { + ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_5G, pg_offset); + if (ret == _TRUE) + valid_5g_path_bmp |= BIT(path); + else if (ret == EFUSE_POWER_INDEX_INVALID) + return _FALSE; + } + #endif + pg_offset += PG_TXPWR_1PATH_BYTE_NUM_5G; + } + + if ((hal_chk_band_cap(adapter, BAND_CAP_2G) && valid_2g_path_bmp) + #ifdef CONFIG_IEEE80211_BAND_5GHZ + || (hal_chk_band_cap(adapter, BAND_CAP_5G) && valid_5g_path_bmp) + #endif + ) + return _TRUE; + + return _FALSE; +} +#endif /* CONFIG_EFUSE_CONFIG_FILE */ + void hal_load_txpwr_info( _adapter *adapter, TxPowerInfo24G *pwr_info_2g, @@ -1510,7 +1585,7 @@ PHY_GetRateValuesOfTxPowerByRate( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; u8 index = 0, i = 0; switch (RegAddr) { @@ -1909,7 +1984,7 @@ PHY_StoreTxPowerByRateNew( return; } - if (RfPath > ODM_RF_PATH_D) { + if (RfPath > RF_PATH_D) { RTW_PRINT("Invalid RfPath %d\n", RfPath); return; } @@ -1947,7 +2022,7 @@ phy_store_tx_power_by_rate( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; if (pDM_Odm->phy_reg_pg_version > 0) PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, RegAddr, BitMask, Data); @@ -1980,7 +2055,7 @@ phy_ConvertTxPowerByRateInDbmToRelativeValues( /* RTW_INFO("===>PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */ for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) { - for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) { + for (path = RF_PATH_A; path <= RF_PATH_D; ++path) { /* CCK */ if (band == BAND_ON_2_4G) { base = PHY_GetTxPowerByRateBase(pAdapter, band, path, CCK); @@ -2063,7 +2138,7 @@ PHY_TxPowerByRateConfiguration( VOID phy_set_tx_power_index_by_rate_section( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Channel, IN u8 RateSection ) @@ -2115,16 +2190,16 @@ phy_GetChnlIndex( u8 PHY_GetTxPowerIndexBase( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, u8 ntx_idx, - IN CHANNEL_WIDTH BandWidth, + IN enum channel_width BandWidth, IN u8 Channel, OUT PBOOLEAN bIn24G ) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; u8 i = 0; /* default set to 1S */ u8 txPower = 0; u8 chnlIdx = (Channel - 1); @@ -2293,12 +2368,12 @@ PHY_GetTxPowerIndexBase( s8 PHY_GetTxPowerTrackingOffset( PADAPTER pAdapter, - u8 RFPath, + enum rf_path RFPath, u8 Rate ) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; s8 offset = 0; if (pDM_Odm->rf_calibrate_info.txpowertrack_control == _FALSE) @@ -2588,7 +2663,7 @@ s8 _PHY_GetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ) { @@ -2600,7 +2675,7 @@ _PHY_GetTxPowerByRate( RTW_INFO("Invalid band %d in %s\n", Band, __func__); goto exit; } - if (RFPath > ODM_RF_PATH_D) { + if (RFPath > RF_PATH_D) { RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __func__); goto exit; } @@ -2620,7 +2695,7 @@ s8 PHY_GetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ) { @@ -2634,7 +2709,7 @@ VOID PHY_SetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, IN s8 Value ) @@ -2646,7 +2721,7 @@ PHY_SetTxPowerByRate( RTW_INFO("Invalid band %d in %s\n", Band, __FUNCTION__); return; } - if (RFPath > ODM_RF_PATH_D) { + if (RFPath > RF_PATH_D) { RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __FUNCTION__); return; } @@ -2700,8 +2775,8 @@ phy_set_tx_power_level_by_path( VOID PHY_SetTxPowerIndexByRateArray( IN PADAPTER pAdapter, - IN u8 RFPath, - IN CHANNEL_WIDTH BandWidth, + IN enum rf_path RFPath, + IN enum channel_width BandWidth, IN u8 Channel, IN u8 *Rates, IN u8 RateArraySize @@ -2759,12 +2834,15 @@ phy_GetChannelIndexOfTxPowerLimit( return channelIndex; } -/* return txpwr limit absolute value */ +/* +* return txpwr limit absolute value +* MAX_POWER_INDEX is returned when NO limit +*/ s8 phy_get_txpwr_lmt_abs( IN PADAPTER Adapter, IN const char *regd_name, IN BAND_TYPE Band, - IN CHANNEL_WIDTH bw, + IN enum channel_width bw, u8 tlrs, u8 ntx_idx, u8 cch, @@ -2820,31 +2898,41 @@ s8 phy_get_txpwr_lmt_abs( goto release_lock; if (Band == BAND_ON_2_4G) { - if (is_ww_regd) { - lmt = MAX_POWER_INDEX; - head = &rfctl->txpwr_lmt_list; - cur = get_next(head); - while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { - ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); - cur = get_next(cur); - lmt = rtw_min(lmt, ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]); - } - } else + if (!is_ww_regd) { lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]; + if (lmt != -MAX_POWER_INDEX) + goto release_lock; + } + + /* search for min value for WW regd or WW limit */ + lmt = MAX_POWER_INDEX; + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + if (ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] != -MAX_POWER_INDEX) + lmt = rtw_min(lmt, ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]); + } } #ifdef CONFIG_IEEE80211_BAND_5GHZ else if (Band == BAND_ON_5G) { - if (is_ww_regd) { - lmt = MAX_POWER_INDEX; - head = &rfctl->txpwr_lmt_list; - cur = get_next(head); - while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { - ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); - cur = get_next(cur); - lmt = rtw_min(lmt, ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]); - } - } else + if (!is_ww_regd) { lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]; + if (lmt != -MAX_POWER_INDEX) + goto release_lock; + } + + /* search for min value for WW regd or WW limit */ + lmt = MAX_POWER_INDEX; + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + if (ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] != -MAX_POWER_INDEX) + lmt = rtw_min(lmt, ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]); + } } #endif @@ -2856,10 +2944,13 @@ s8 phy_get_txpwr_lmt_abs( return lmt; } -/* return txpwr limit diff value */ +/* +* return txpwr limit diff value +* MAX_POWER_INDEX is returned when NO limit +*/ inline s8 phy_get_txpwr_lmt(_adapter *adapter , const char *regd_name - , BAND_TYPE band, CHANNEL_WIDTH bw + , BAND_TYPE band, enum channel_width bw , u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock ) { @@ -2898,7 +2989,7 @@ inline s8 phy_get_txpwr_lmt(_adapter *adapter s8 PHY_GetTxPowerLimit(_adapter *adapter , const char *regd_name - , BAND_TYPE band, CHANNEL_WIDTH bw + , BAND_TYPE band, enum channel_width bw , u8 rfpath, u8 rate, u8 ntx_idx, u8 cch) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); @@ -2914,10 +3005,11 @@ PHY_GetTxPowerLimit(_adapter *adapter u8 final_bw = bw, final_cch = cch; _irqL irqL; +#ifdef CONFIG_MP_INCLUDED /* MP mode channel don't use secondary channel */ if (rtw_mp_mode_check(adapter) == _TRUE) no_sc = _TRUE; - +#endif if (IS_CCK_RATE(rate)) { tlrs = TXPWR_LMT_RS_CCK; rs = CCK; @@ -3367,6 +3459,35 @@ static void phy_txpwr_lmt_post_hdl(_adapter *adapter) _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); } + +BOOLEAN +GetS1ByteIntegerFromStringInDecimal( + IN char *str, + IN OUT s8 *val +) +{ + u8 negative = 0; + u16 i = 0; + + *val = 0; + + while (str[i] != '\0') { + if (i == 0 && (str[i] == '+' || str[i] == '-')) { + if (str[i] == '-') + negative = 1; + } else if (str[i] >= '0' && str[i] <= '9') { + *val *= 10; + *val += (str[i] - '0'); + } else + return _FALSE; + ++i; + } + + if (negative) + *val = -*val; + + return _TRUE; +} #endif /* CONFIG_TXPWR_LIMIT */ /* @@ -3374,7 +3495,7 @@ static void phy_txpwr_lmt_post_hdl(_adapter *adapter) */ VOID phy_set_tx_power_limit( - IN struct PHY_DM_STRUCT *pDM_Odm, + IN struct dm_struct *pDM_Odm, IN u8 *Regulation, IN u8 *Band, IN u8 *Bandwidth, @@ -3395,14 +3516,18 @@ phy_set_tx_power_limit( RTW_INFO("Index of power limit table [regulation %s][band %s][bw %s][rate section %s][ntx %s][chnl %s][val %s]\n" , Regulation, Band, Bandwidth, RateSection, ntx, Channel, PowerLimit); - if (GetU1ByteIntegerFromStringInDecimal((s8 *)Channel, &channel) == _FALSE - || GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit) == _FALSE + if (GetU1ByteIntegerFromStringInDecimal((char *)Channel, &channel) == _FALSE + || GetS1ByteIntegerFromStringInDecimal((char *)PowerLimit, &powerLimit) == _FALSE ) { RTW_PRINT("Illegal index of power limit table [ch %s][val %s]\n", Channel, PowerLimit); return; } + if (powerLimit < -MAX_POWER_INDEX || powerLimit > MAX_POWER_INDEX) + RTW_PRINT("Illegal power limit value [ch %s][val %s]\n", Channel, PowerLimit); + powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit; + powerLimit = powerLimit < -MAX_POWER_INDEX ? -MAX_POWER_INDEX + 1 : powerLimit; if (eqNByte(RateSection, (u8 *)("CCK"), 3)) tlrs = TXPWR_LMT_RS_CCK; @@ -3482,9 +3607,9 @@ phy_set_tx_power_limit( u8 phy_get_tx_power_index( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, + IN enum channel_width BandWidth, IN u8 Channel ) { @@ -3495,7 +3620,7 @@ VOID PHY_SetTxPowerIndex( IN PADAPTER pAdapter, IN u32 PowerIndex, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ) { @@ -3698,7 +3823,7 @@ int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file) #endif #ifdef CONFIG_EMBEDDED_FWIMG - if (HAL_STATUS_SUCCESS == odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, (enum odm_rf_radio_path_e)0)) { + if (odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, RF_PATH_A) == HAL_STATUS_SUCCESS) { RTW_INFO("default power limit loaded\n"); hal_data->txpwr_limit_from_file = 0; goto post_hdl; @@ -4510,7 +4635,7 @@ int PHY_ConfigRFWithParaFile( IN PADAPTER Adapter, IN char *pFileName, - IN u8 eRFPath + IN enum rf_path eRFPath ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); @@ -4525,11 +4650,11 @@ PHY_ConfigRFWithParaFile( return rtStatus; switch (eRFPath) { - case ODM_RF_PATH_A: + case RF_PATH_A: pBuf = pHalData->rf_radio_a; pBufLen = &pHalData->rf_radio_a_len; break; - case ODM_RF_PATH_B: + case RF_PATH_B: pBuf = pHalData->rf_radio_b; pBufLen = &pHalData->rf_radio_b_len; break; @@ -4552,12 +4677,15 @@ PHY_ConfigRFWithParaFile( *pBufLen = rlen; switch (eRFPath) { - case ODM_RF_PATH_A: + case RF_PATH_A: pHalData->rf_radio_a = pBuf; break; - case ODM_RF_PATH_B: + case RF_PATH_B: pHalData->rf_radio_b = pBuf; break; + default: + RTW_INFO("Unknown RF path!! %d\r\n", eRFPath); + break; } } else RTW_INFO("%s(): eRFPath=%d alloc fail !\n", __FUNCTION__, eRFPath); @@ -4655,8 +4783,8 @@ initDeltaSwingIndexTables( } } while (0)\ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; + struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); u32 j = 0; char *token; char delim[] = ","; @@ -4724,8 +4852,8 @@ PHY_ConfigRFWithTxPwrTrackParaFile( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; + struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); int rlen = 0, rtStatus = _FAIL; char *szLine, *ptmp; u32 i = 0, j = 0; @@ -4943,10 +5071,10 @@ phy_ParsePowerLimitTableFile( int rtStatus = _FAIL; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); u8 loadingStage = LD_STAGE_EXC_MAPPING; u32 i = 0, forCnt = 0; - u8 limitValue = 0, fraction = 0; + u8 limitValue = 0, fraction = 0, negative = 0; char *szLine, *ptmp; char band[10], bandwidth[10], rateSection[10], ntx[10], colNumBuf[10]; char **regulation = NULL; @@ -5146,9 +5274,25 @@ phy_ParsePowerLimitTableFile( /* load the power limit value */ cnt = 0; fraction = 0; + negative = 0; _rtw_memset((PVOID) powerLimit, 0, 10); - while ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.') { - if (szLine[i] == '.') { + + while ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.' + || szLine[i] == '+' || szLine[i] == '-' + ) { + /* try to get valid decimal number */ + if (szLine[i] == '+' || szLine[i] == '-') { + if (cnt != 0) { + RTW_ERR("Wrong position for sign '%c'\n", szLine[i]); + goto exit; + } + if (szLine[i] == '-') { + negative = 1; + ++i; + continue; + } + + } else if (szLine[i] == '.') { if ((szLine[i + 1] >= '0' && szLine[i + 1] <= '9')) { fraction = szLine[i + 1]; i += 2; @@ -5166,17 +5310,41 @@ phy_ParsePowerLimitTableFile( } if (powerLimit[0] == '\0') { - powerLimit[0] = '6'; - powerLimit[1] = '3'; - i += 2; + if (szLine[i] == 'W' && szLine[i + 1] == 'W') { + /* + * case "WW" assign special value -63 + * means to get minimal limit in other regulations at same channel + */ + powerLimit[0] = '-'; + powerLimit[1] = '6'; + powerLimit[2] = '3'; + i += 2; + } else if (szLine[i] == 'N' && szLine[i + 1] == 'A') { + /* + * case "NA" assign special value 63 + * means no limitation + */ + powerLimit[0] = '6'; + powerLimit[1] = '3'; + i += 2; + } else { + RTW_ERR("Wrong limit expression \"%c%c\"(%d, %d)\n" + , szLine[i], szLine[i + 1], szLine[i], szLine[i + 1]); + goto exit; + } } else { + /* transform dicimal value to power index */ if (!GetU1ByteIntegerFromStringInDecimal(powerLimit, &limitValue)) { - RTW_ERR("Limit \"%s\" is not unsigned decimal\n", powerLimit); + RTW_ERR("Limit \"%s\" is not valid decimal\n", powerLimit); goto exit; } limitValue *= 2; cnt = 0; + + if (negative) + powerLimit[cnt++] = '-'; + if (fraction == '5') ++limitValue; diff --git a/hal/hal_dm.c b/hal/hal_dm.c index 021231b..9102ca5 100644 --- a/hal/hal_dm.c +++ b/hal/hal_dm.c @@ -17,9 +17,9 @@ #include /* A mapping from HalData to ODM. */ -enum odm_board_type_e boardType(u8 InterfaceSel) +enum odm_board_type boardType(u8 InterfaceSel) { - enum odm_board_type_e board = ODM_BOARD_DEFAULT; + enum odm_board_type board = ODM_BOARD_DEFAULT; #ifdef CONFIG_PCI_HCI INTERFACE_SELECT_PCIE pcie = (INTERFACE_SELECT_PCIE)InterfaceSel; @@ -65,13 +65,130 @@ enum odm_board_type_e boardType(u8 InterfaceSel) return board; } +void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + + if (hal->RegIQKFWOffload) { + rtw_sctx_init(&hal->iqk_sctx, 0); + phydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD); + } else + phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD); + + RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable"); +} + +#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)) +void rtw_phydm_iqk_trigger(_adapter *adapter) +{ + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + u8 clear = _TRUE; + u8 segment = _FALSE; + u8 rfk_forbidden = _FALSE; + + /*segment = _rtw_phydm_iqk_segment_chk(adapter);*/ + halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden); + halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); + halrf_segment_iqk_trigger(p_dm_odm, clear, segment); +} +#endif + +void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment) +{ + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + +#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)) + halrf_segment_iqk_trigger(p_dm_odm, clear, segment); +#else + halrf_iqk_trigger(p_dm_odm, recovery); +#endif +} +void rtw_phydm_lck_trigger(_adapter *adapter) +{ + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + + halrf_lck_trigger(p_dm_odm); +} +#ifdef CONFIG_DBG_RF_CAL +void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment) +{ + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + + rtw_ps_deny(adapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(adapter); + + rtw_phydm_ability_backup(adapter); + rtw_phydm_func_disable_all(adapter); + + halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK); + + rtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment); + rtw_phydm_ability_restore(adapter); + + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); +} + +void rtw_hal_lck_test(_adapter *adapter) +{ + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + + rtw_ps_deny(adapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(adapter); + + rtw_phydm_ability_backup(adapter); + rtw_phydm_func_disable_all(adapter); + + halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK); + + rtw_phydm_lck_trigger(adapter); + + rtw_phydm_ability_restore(adapter); + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); +} +#endif + +#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT +void rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter) +{ + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + + if (adapter->registrypriv.fw_param_init) + phydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD); + else + phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD); + + RTW_INFO("Init-Parameter FW offload:%s\n", adapter->registrypriv.fw_param_init ? "enable" : "disable"); +} +#endif + +void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask) +{ + struct dm_struct *p_dm = (struct dm_struct *)p_dm_void; + _adapter *adapter = p_dm->adapter; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + + rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode); + rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable); + rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask); + rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32); + + rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter)); +} + +void rtw_phydm_ops_func_init(struct dm_struct *p_phydm) +{ + struct ra_table *p_ra_t = &p_phydm->dm_ra_table; + + p_ra_t->record_ra_info = record_ra_info; +} + void Init_ODM_ComInfo(_adapter *adapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); int i; @@ -79,6 +196,9 @@ void Init_ODM_ComInfo(_adapter *adapter) pDM_Odm->adapter = adapter; + /*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/ + pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/ + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PLATFORM, ODM_CE); rtw_odm_init_ic_type(adapter); @@ -94,28 +214,10 @@ void Init_ODM_ComInfo(_adapter *adapter) odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec); - - if (pHalData->rf_type == RF_1T1R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T1R); - else if (pHalData->rf_type == RF_1T2R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T2R); - else if (pHalData->rf_type == RF_2T2R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R); - else if (pHalData->rf_type == RF_2T2R_GREEN) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R_GREEN); - else if (pHalData->rf_type == RF_2T3R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T3R); - else if (pHalData->rf_type == RF_2T4R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T4R); - else if (pHalData->rf_type == RF_3T3R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T3R); - else if (pHalData->rf_type == RF_3T4R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T4R); - else if (pHalData->rf_type == RF_4T4R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_4T4R); - else - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_XTXR); - +#ifdef CONFIG_ADVANCE_OTA + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota); +#endif + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type); { /* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */ @@ -164,8 +266,6 @@ void Init_ODM_ComInfo(_adapter *adapter) odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable); odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable); - /*Antenna diversity relative parameters*/ - odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg)); odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType); odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant); odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch); @@ -176,51 +276,74 @@ void Init_ODM_ComInfo(_adapter *adapter) /*Add by YuChen for adaptivity init*/ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en)); - odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode)); phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE); phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DCBACKOFF, adapter->registrypriv.adaptivity_dc_backoff); phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, (adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE); phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini); phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff); + /*halrf info init*/ + halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter); + if (rtw_odm_adaptivity_needed(adapter) == _TRUE) rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter); #ifdef CONFIG_IQK_PA_OFF odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1); #endif - /* odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKFWOFFLOAD, pHalData->RegIQKFWOffload); */ rtw_hal_update_iqk_fw_offload_cap(adapter); + #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT + rtw_hal_update_param_init_fw_offload_cap(adapter); + #endif /* Pointer reference */ + /*Antenna diversity relative parameters*/ + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode)); + + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes)); - odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_WM_MODE, &(pmlmeext->cur_wireless_mode)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate)); - odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed)); - odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb)); - odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pmlmepriv->bScanInProcess)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving)); /*Add by Yuchen for phydm beamforming*/ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test)); +#ifdef CONFIG_RTL8723B + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path); +#endif /*CONFIG_RTL8723B*/ #ifdef CONFIG_USB_HCI odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed)); #endif + +#ifdef CONFIG_DYNAMIC_SOML + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en)); +#endif + + /*halrf info hook*/ +#ifdef CONFIG_MP_INCLUDED + halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx)); + halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone)); + halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression)); + halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index)); +#endif/*CONFIG_MP_INCLUDED*/ for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) odm_cmn_info_ptr_array_hook(pDM_Odm, ODM_CMNINFO_STA_STATUS, i, NULL); phydm_init_debug_setting(pDM_Odm); - + rtw_phydm_ops_func_init(pDM_Odm); /* TODO */ /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */ /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */ @@ -362,15 +485,19 @@ void rtw_hal_turbo_edca(_adapter *adapter) } if (interface_type == RTW_PCIE && - (ic_type == RTL8822B)) { - EDCA_BE_DL = 0xa630; + ((ic_type == RTL8822B) + || (ic_type == RTL8814A))) { + EDCA_BE_UL = 0x6ea42b; + EDCA_BE_DL = 0x6ea42b; } if (traffic_index == DOWN_LINK) edca_param = EDCA_BE_DL; else edca_param = EDCA_BE_UL; - +#ifdef CONFIG_RTW_CUSTOMIZE_BEEDCA + edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA; +#endif rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param)); RTW_DBG("Turbo EDCA =0x%x\n", edca_param); @@ -393,4 +520,721 @@ void rtw_hal_turbo_edca(_adapter *adapter) } +s8 rtw_phydm_get_min_rssi(_adapter *adapter) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + s8 rssi_min = 0; + + rssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_RSSI_MIN); + return rssi_min; +} + +u8 rtw_phydm_get_cur_igi(_adapter *adapter) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + u8 cur_igi = 0; + + cur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CURR_IGI); + return cur_igi; +} + +u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + + if (cnt == FA_OFDM) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_OFDM); + else if (cnt == FA_CCK) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_CCK); + else if (cnt == FA_TOTAL) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_TOTAL); + else if (cnt == CCA_OFDM) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_OFDM); + else if (cnt == CCA_CCK) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_CCK); + else if (cnt == CCA_ALL) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_ALL); + else if (cnt == CRC32_OK_VHT) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_VHT); + else if (cnt == CRC32_OK_HT) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_HT); + else if (cnt == CRC32_OK_LEGACY) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_LEGACY); + else if (cnt == CRC32_OK_CCK) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_CCK); + else if (cnt == CRC32_ERROR_VHT) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_VHT); + else if (cnt == CRC32_ERROR_HT) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_HT); + else if (cnt == CRC32_ERROR_LEGACY) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_LEGACY); + else if (cnt == CRC32_ERROR_CCK) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_CCK); + else + return 0; +} + +u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter) +{ + u8 rts = _FALSE; + struct dm_struct *podmpriv = adapter_to_phydm(adapter); + + odm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK); + if (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) { + RTW_ERR("IQK InProgress\n"); + rts = _TRUE; + } + odm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK); + + return rts; +} + +void SetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + BOOLEAN bSet) +{ + struct dm_struct *podmpriv = adapter_to_phydm(Adapter); + /* _irqL irqL; */ + switch (eVariable) { + case HAL_ODM_STA_INFO: { + struct sta_info *psta = (struct sta_info *)pValue1; + + if (bSet) { + RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id); + odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->cmn.mac_id, psta); + psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE; + phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn)); + } else { + RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id); + /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ + psta->cmn.dm_ctrl = 0; + odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->cmn.mac_id, NULL); + phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL); + + /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ + } + } + break; + case HAL_ODM_P2P_STATE: + odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet); + break; + case HAL_ODM_WIFI_DISPLAY_STATE: + odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet); + break; + case HAL_ODM_REGULATION: + /* used to auto enable/disable adaptivity by SD7 */ + odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_2G, 0); + odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_5G, 0); + break; + case HAL_ODM_INITIAL_GAIN: { + u8 rx_gain = *((u8 *)(pValue1)); + /*printk("rx_gain:%x\n",rx_gain);*/ + if (rx_gain == 0xff) {/*restore rx gain*/ + /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/ + odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain); + } else { + /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/ + /*odm_write_dig(podmpriv,rx_gain);*/ + odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain); + } + } + break; + case HAL_ODM_RX_INFO_DUMP: { + u8 cur_igi = 0; + s8 rssi_min; + void *sel; + + sel = pValue1; + cur_igi = rtw_phydm_get_cur_igi(Adapter); + rssi_min = rtw_phydm_get_min_rssi(Adapter); + + _RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n"); + _RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%), current_igi = 0x%x\n", podmpriv->is_linked, rssi_min, cur_igi); + _RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n", + rtw_phydm_get_phy_cnt(Adapter, FA_CCK), + rtw_phydm_get_phy_cnt(Adapter, FA_OFDM), + rtw_phydm_get_phy_cnt(Adapter, FA_TOTAL)); + + if (podmpriv->is_linked) { + _RTW_PRINT_SEL(sel, "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate)); + if (IS_HARDWARE_TYPE_8814A(Adapter)) + _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%), rssi_c = %d(%%), rssi_d = %d(%%)\n", + podmpriv->rssi_a, podmpriv->rssi_b, podmpriv->rssi_c, podmpriv->rssi_d); + else + _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%)\n", podmpriv->rssi_a, podmpriv->rssi_b); +#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA + rtw_dump_raw_rssi_info(Adapter, sel); +#endif + } + } + break; + case HAL_ODM_RX_Dframe_INFO: { + void *sel; + + sel = pValue1; + + /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/ +#ifdef DBG_RX_DFRAME_RAW_DATA + rtw_dump_rx_dframe_info(Adapter, sel); +#endif + } + break; + +#ifdef CONFIG_ANTENNA_DIVERSITY + case HAL_ODM_ANTDIV_SELECT: { + u8 antenna = (*(u8 *)pValue1); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + /*switch antenna*/ + odm_update_rx_idle_ant(&pHalData->odmpriv, antenna); + /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/ + + } + break; +#endif + + default: + break; + } +} + +void GetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + PVOID pValue2) +{ + struct dm_struct *podmpriv = adapter_to_phydm(Adapter); + + switch (eVariable) { +#ifdef CONFIG_ANTENNA_DIVERSITY + case HAL_ODM_ANTDIV_SELECT: { + struct phydm_fat_struct *pDM_FatTable = &podmpriv->dm_fat_table; + *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant; + } + break; +#endif + case HAL_ODM_INITIAL_GAIN: + *((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter); + break; + default: + break; + } +} + +#ifdef RTW_HALMAC +#include "../hal_halmac.h" +#endif + +enum hal_status +rtw_phydm_fw_iqk( + struct dm_struct *p_dm_odm, + u8 clear, + u8 segment +) +{ + #ifdef RTW_HALMAC + struct _ADAPTER *adapter = p_dm_odm->adapter; + + if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0) + return HAL_STATUS_SUCCESS; + #endif + return HAL_STATUS_FAILURE; +} + +enum hal_status +rtw_phydm_cfg_phy_para( + struct dm_struct *p_dm_odm, + enum phydm_halmac_param config_type, + u32 offset, + u32 data, + u32 mask, + enum rf_path e_rf_path, + u32 delay_time) +{ + #ifdef RTW_HALMAC + struct _ADAPTER *adapter = p_dm_odm->adapter; + struct rtw_phy_parameter para; + + switch (config_type) { + case PHYDM_HALMAC_CMD_MAC_W8: + para.cmd = 0; /* MAC register */ + para.data.mac.offset = offset; + para.data.mac.value = data; + para.data.mac.msk = mask; + para.data.mac.msk_en = (mask) ? 1 : 0; + para.data.mac.size = 1; + break; + case PHYDM_HALMAC_CMD_MAC_W16: + para.cmd = 0; /* MAC register */ + para.data.mac.offset = offset; + para.data.mac.value = data; + para.data.mac.msk = mask; + para.data.mac.msk_en = (mask) ? 1 : 0; + para.data.mac.size = 2; + break; + case PHYDM_HALMAC_CMD_MAC_W32: + para.cmd = 0; /* MAC register */ + para.data.mac.offset = offset; + para.data.mac.value = data; + para.data.mac.msk = mask; + para.data.mac.msk_en = (mask) ? 1 : 0; + para.data.mac.size = 4; + break; + case PHYDM_HALMAC_CMD_BB_W8: + para.cmd = 1; /* BB register */ + para.data.bb.offset = offset; + para.data.bb.value = data; + para.data.bb.msk = mask; + para.data.bb.msk_en = (mask) ? 1 : 0; + para.data.bb.size = 1; + break; + case PHYDM_HALMAC_CMD_BB_W16: + para.cmd = 1; /* BB register */ + para.data.bb.offset = offset; + para.data.bb.value = data; + para.data.bb.msk = mask; + para.data.bb.msk_en = (mask) ? 1 : 0; + para.data.bb.size = 2; + break; + case PHYDM_HALMAC_CMD_BB_W32: + para.cmd = 1; /* BB register */ + para.data.bb.offset = offset; + para.data.bb.value = data; + para.data.bb.msk = mask; + para.data.bb.msk_en = (mask) ? 1 : 0; + para.data.bb.size = 4; + break; + case PHYDM_HALMAC_CMD_RF_W: + para.cmd = 2; /* RF register */ + para.data.rf.offset = offset; + para.data.rf.value = data; + para.data.rf.msk = mask; + para.data.rf.msk_en = (mask) ? 1 : 0; + if (e_rf_path == RF_PATH_A) + para.data.rf.path = 0; + else if (e_rf_path == RF_PATH_B) + para.data.rf.path = 1; + else if (e_rf_path == RF_PATH_C) + para.data.rf.path = 2; + else if (e_rf_path == RF_PATH_D) + para.data.rf.path = 3; + else + para.data.rf.path = 0; + break; + case PHYDM_HALMAC_CMD_DELAY_US: + para.cmd = 3; /* Delay */ + para.data.delay.unit = 0; /* microsecond */ + para.data.delay.value = delay_time; + break; + case PHYDM_HALMAC_CMD_DELAY_MS: + para.cmd = 3; /* Delay */ + para.data.delay.unit = 1; /* millisecond */ + para.data.delay.value = delay_time; + break; + case PHYDM_HALMAC_CMD_END: + para.cmd = 0xFF; /* End command */ + break; + default: + return HAL_STATUS_FAILURE; + } + + if (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), ¶)) + return HAL_STATUS_FAILURE; + #endif /*RTW_HALMAC*/ + return HAL_STATUS_SUCCESS; +} + + +#ifdef CONFIG_LPS_LCLK_WD_TIMER +void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + struct dm_struct *podmpriv = &(pHalData->odmpriv); + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *psta = NULL; + u8 rssi_min = 0; + u32 rssi_rpt = 0; + bool is_linked = _FALSE; + + if (!rtw_is_hw_init_completed(adapter)) + return; + + if (rtw_mi_check_status(adapter, MI_ASSOC)) + is_linked = _TRUE; + + if (is_linked == _FALSE) + return; + + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + if (psta == NULL) + return; + + odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked); + + phydm_watchdog_lps_32k(&pHalData->odmpriv); +} + +void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *psta = NULL; + u8 cur_igi = 0; + s8 min_rssi = 0; + + if (!rtw_is_hw_init_completed(adapter)) + return; + + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + if (psta == NULL) + return; + + cur_igi = rtw_phydm_get_cur_igi(adapter); + min_rssi = rtw_phydm_get_min_rssi(adapter); + if (min_rssi <= 0) + min_rssi = psta->cmn.rssi_stat.rssi; + /*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__, ADPT_ARG(adapter), cur_igi, min_rssi);*/ + + if (min_rssi <= 0) + return; + + if ((cur_igi > min_rssi + 5) || + (cur_igi < min_rssi - 5)) { +#ifdef CONFIG_LPS + rtw_dm_in_lps_wk_cmd(adapter); +#endif + } +} +#endif /*CONFIG_LPS_LCLK_WD_TIMER*/ + +void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta) +{ + struct ra_sta_info *ra_info; + u8 curr_sgi = _FALSE; + + if (!psta) + return; + RTW_PRINT_SEL(sel, "====== mac_id : %d ======\n", psta->cmn.mac_id); + + ra_info = &psta->cmn.ra_info; + curr_sgi = (ra_info->curr_tx_rate & 0x80) ? _TRUE : _FALSE; + RTW_PRINT_SEL(sel, "tx_rate : %s(%s) rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\n" + , HDATA_RATE((ra_info->curr_tx_rate & 0x7F)), (curr_sgi) ? "S" : "L" + , HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi + ); + + if (0) { + RTW_PRINT_SEL(sel, "tx_bytes:%llu(%llu - %llu)\n" + , psta->sta_stats.tx_bytes - psta->sta_stats.last_tx_bytes + , psta->sta_stats.tx_bytes, psta->sta_stats.last_tx_bytes + ); + RTW_PRINT_SEL(sel, "rx_uc_bytes:%llu(%llu - %llu)\n" + , sta_rx_uc_bytes(psta) - sta_last_rx_uc_bytes(psta) + , sta_rx_uc_bytes(psta), sta_last_rx_uc_bytes(psta) + ); + RTW_PRINT_SEL(sel, "rx_mc_bytes:%llu(%llu - %llu)\n" + , psta->sta_stats.rx_mc_bytes - psta->sta_stats.last_rx_mc_bytes + , psta->sta_stats.rx_mc_bytes, psta->sta_stats.last_rx_mc_bytes + ); + RTW_PRINT_SEL(sel, "rx_bc_bytes:%llu(%llu - %llu)\n" + , psta->sta_stats.rx_bc_bytes - psta->sta_stats.last_rx_bc_bytes + , psta->sta_stats.rx_bc_bytes, psta->sta_stats.last_rx_bc_bytes + ); + } + + RTW_PRINT_SEL(sel, "TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n", + (psta->sta_stats.tx_tp_mbytes << 3), (psta->sta_stats.rx_tp_mbytes << 3), + (psta->sta_stats.tx_tp_mbytes + psta->sta_stats.rx_tp_mbytes) << 3); + + RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n", + (psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3), + (psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3); + +} + +void dump_sta_info(void *sel, struct sta_info *psta) +{ + struct ra_sta_info *ra_info; + u8 curr_tx_sgi = _FALSE; + u8 curr_tx_rate = 0; + + if (!psta) + return; + + ra_info = &psta->cmn.ra_info; + + RTW_PRINT_SEL(sel, "============ STA [" MAC_FMT "] ===================\n", + MAC_ARG(psta->cmn.mac_addr)); + RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id); + RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode); + RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type); + RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n", + ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode)); + RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id); + RTW_PRINT_SEL(sel, "rssi : %d (%%), rssi_level : %d\n", psta->cmn.rssi_stat.rssi, ra_info->rssi_level); + RTW_PRINT_SEL(sel, "is_support_sgi : %s, is_vht_enable : %s\n", + (ra_info->is_support_sgi) ? "Y" : "N", (ra_info->is_vht_enable) ? "Y" : "N"); + RTW_PRINT_SEL(sel, "disable_ra : %s, disable_pt : %s\n", + (ra_info->disable_ra) ? "Y" : "N", (ra_info->disable_pt) ? "Y" : "N"); + RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N"); + RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/ + + curr_tx_sgi = (ra_info->curr_tx_rate & 0x80) ? _TRUE : _FALSE; + curr_tx_rate = ra_info->curr_tx_rate & 0x7F; + RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n", + HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L"); + RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw)); + RTW_PRINT_SEL(sel, "curr_retry_ratio : %d\n", ra_info->curr_retry_ratio); + RTW_PRINT_SEL(sel, "ra_mask : 0x%016llx\n\n", ra_info->ramask); +} + +void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + if (psta == NULL) { + RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(adapter)); + rtw_warn_on(1); + return; + } + + phydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi); + dump_sta_info(RTW_DBGDUMP, psta); +} + +static void init_phydm_info(_adapter *adapter) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + struct dm_struct *phydm = &(hal_data->odmpriv); + + halrf_cmn_info_init(phydm, HALRF_CMNINFO_FW_VER, + ((hal_data->firmware_version << 16) | hal_data->firmware_sub_version)); + + #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) + /*PHYDM API - thermal trim*/ + phydm_get_thermal_trim_offset(phydm); + /*PHYDM API - power trim*/ + phydm_get_power_trim_offset(phydm); + #endif +} +void rtw_phydm_init(_adapter *adapter) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + struct dm_struct *phydm = &(hal_data->odmpriv); + + init_phydm_info(adapter); + odm_dm_init(phydm); +} + +#ifdef CONFIG_LPS_PG +static void _lps_pg_state_update(_adapter *adapter) +{ + u8 is_in_lpspg = _FALSE; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *psta = NULL; + + if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2)) + is_in_lpspg = _TRUE; + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + + if (psta) + psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE; +} +#endif + +/*#define DBG_PHYDM_STATE_CHK*/ + + +static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter) +{ + u8 rst = _FALSE; + + if (rtw_mi_stayin_union_ch_chk(adapter)) + rst = _TRUE; + + #ifdef CONFIG_MCC_MODE + /*not in MCC State*/ + if (MCC_EN(adapter)) + if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) + rst = _TRUE; + #endif + + #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) + + #endif + + return rst; +} +#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)) +static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter) +{ + u8 rst = _FALSE; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + +#if 0 + if (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2) + rst = _TRUE; +#else + rst = _TRUE; +#endif + return rst; +} +#endif + +/*check the tx low rate while unlinked to any AP;for pwr tracking */ +static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter) +{ + int i; + _adapter *iface; + u8 if_tx_rate = 0xFF; + u8 tx_rate = 0xFF; + struct mlme_ext_priv *pmlmeext = NULL; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + pmlmeext = &(iface->mlmeextpriv); + if ((iface) && rtw_is_adapter_up(iface)) { +#ifdef CONFIG_P2P + if (!rtw_p2p_chk_role(&(iface)->wdinfo, P2P_ROLE_DISABLE)) + if_tx_rate = IEEE80211_OFDM_RATE_6MB; + else +#endif + if_tx_rate = pmlmeext->tx_rate; + if(if_tx_rate < tx_rate) + tx_rate = if_tx_rate; + + RTW_DBG("%s i=%d tx_rate =0x%x\n", __func__, i, if_tx_rate); + } + } + RTW_DBG("%s tx_low_rate (unlinked to any AP)=0x%x\n", __func__, tx_rate); + return tx_rate; +} + +#ifdef CONFIG_DYNAMIC_SOML +void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + + phydm_soml_bytes_acq(phydm, data_rate, size); +} + +void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl, + u8 period, u8 delay) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + + phydm_adaptive_soml_para_set(phydm, train_num, intvl, period, delay); + RTW_INFO("%s.\n", __func__); +} + +void rtw_dyn_soml_config(_adapter *adapter) +{ + RTW_INFO("%s.\n", __func__); + + if (adapter->registrypriv.dyn_soml_en == 1) { + /* Must after phydm_adaptive_soml_init() */ + rtw_hal_set_hwreg(adapter , HW_VAR_SET_SOML_PARAM , NULL); + RTW_INFO("dyn_soml_en = 1\n"); + } else { + if (adapter->registrypriv.dyn_soml_en == 2) { + rtw_dyn_soml_para_set(adapter, + adapter->registrypriv.dyn_soml_train_num, + adapter->registrypriv.dyn_soml_interval, + adapter->registrypriv.dyn_soml_period, + adapter->registrypriv.dyn_soml_delay); + RTW_INFO("dyn_soml_en = 2\n"); + RTW_INFO("dyn_soml_en, param = %d, %d, %d, %d\n", + adapter->registrypriv.dyn_soml_train_num, + adapter->registrypriv.dyn_soml_interval, + adapter->registrypriv.dyn_soml_period, + adapter->registrypriv.dyn_soml_delay); + } else if (adapter->registrypriv.dyn_soml_en == 0) { + RTW_INFO("dyn_soml_en = 0\n"); + } else + RTW_ERR("%s, wrong setting: dyn_soml_en = %d\n", __func__, + adapter->registrypriv.dyn_soml_en); + } +} +#endif + +void rtw_phydm_watchdog(_adapter *adapter) +{ + u8 bLinked = _FALSE; + u8 bsta_state = _FALSE; + u8 bBtDisabled = _TRUE; + u8 rfk_forbidden = _TRUE; + u8 segment_iqk = _TRUE; + u8 tx_unlinked_low_rate = 0xFF; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + + if (!rtw_is_hw_init_completed(adapter)) { + RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__); + return; + } + if (rtw_mi_check_fwstate(adapter, _FW_UNDER_SURVEY)) + pHalData->bScanInProcess = _TRUE; + else + pHalData->bScanInProcess = _FALSE; + + if (rtw_mi_check_status(adapter, MI_ASSOC)) { + bLinked = _TRUE; + if (rtw_mi_check_status(adapter, MI_STA_LINKED)) + bsta_state = _TRUE; + } + + odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked); + odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state); + +#ifdef CONFIG_BT_COEXIST + bBtDisabled = rtw_btcoex_IsBtDisabled(adapter); +#endif /* CONFIG_BT_COEXIST */ + odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, + (bBtDisabled == _TRUE) ? _FALSE : _TRUE); +#ifdef CONFIG_LPS_PG + _lps_pg_state_update(adapter); +#endif + + if (bLinked == _TRUE) { + rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter) == _TRUE) ? _FALSE : _TRUE; + halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden); + + #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)) + segment_iqk = _rtw_phydm_iqk_segment_chk(adapter); + halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk); + #endif + } else { + tx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter); + halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate); + } +#ifdef DBG_PHYDM_STATE_CHK + RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n", + __func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N"); +#endif + + /*if (!rtw_mi_stayin_union_band_chk(adapter)) { + #ifdef DBG_PHYDM_STATE_CHK + RTW_ERR("Not stay in union band, skip phydm\n"); + #endif + goto _exit; + }*/ + if (pwrctl->bpower_saving) + phydm_watchdog_lps(&pHalData->odmpriv); + else + phydm_watchdog(&pHalData->odmpriv); + + #ifdef CONFIG_RTW_ACS + rtw_acs_update_current_info(adapter); + #endif + +_exit: + return; +} diff --git a/hal/hal_dm.h b/hal/hal_dm.h index a25d3a7..299a060 100644 --- a/hal/hal_dm.h +++ b/hal/hal_dm.h @@ -15,7 +15,74 @@ #ifndef __HAL_DM_H__ #define __HAL_DM_H__ +#define adapter_to_phydm(adapter) (&(GET_HAL_DATA(adapter)->odmpriv)) + void Init_ODM_ComInfo(_adapter *adapter); +void rtw_phydm_init(_adapter *adapter); + void rtw_hal_turbo_edca(_adapter *adapter); +u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter); + +void GetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + PVOID pValue2); +void SetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + BOOLEAN bSet); + +void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta); + +#ifdef CONFIG_DYNAMIC_SOML +void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size); +void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl, + u8 period, u8 delay); +void rtw_dyn_soml_config(_adapter *adapter); +#endif +void rtw_phydm_watchdog(_adapter *adapter); + +void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter); +void dump_sta_info(void *sel, struct sta_info *psta); +void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta); + +#ifdef CONFIG_DBG_RF_CAL +void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment); +void rtw_hal_lck_test(_adapter *adapter); +#endif + +s8 rtw_phydm_get_min_rssi(_adapter *adapter); +u8 rtw_phydm_get_cur_igi(_adapter *adapter); + + +#ifdef CONFIG_LPS_LCLK_WD_TIMER +extern void phydm_rssi_monitor_check(void *p_dm_void); + +void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter); +void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter); +#endif + +enum phy_cnt { + FA_OFDM, + FA_CCK, + FA_TOTAL, + CCA_OFDM, + CCA_CCK, + CCA_ALL, + CRC32_OK_VHT, + CRC32_OK_HT, + CRC32_OK_LEGACY, + CRC32_OK_CCK, + CRC32_ERROR_VHT, + CRC32_ERROR_HT, + CRC32_ERROR_LEGACY, + CRC32_ERROR_CCK, +}; +u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt); +#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)) +void rtw_phydm_iqk_trigger(_adapter *adapter); +#endif #endif /* __HAL_DM_H__ */ diff --git a/hal/hal_halmac.c b/hal/hal_halmac.c index a5d2df4..046d15c 100644 --- a/hal/hal_halmac.c +++ b/hal/hal_halmac.c @@ -16,13 +16,13 @@ #include /* PADAPTER, struct dvobj_priv, SDIO_ERR_VAL8 and etc. */ #include /* efuse, PHAL_DATA_TYPE and etc. */ -#include "halmac/halmac_api.h" /* HALMAC_FW_SIZE_MAX_88XX and etc. */ #include "hal_halmac.h" /* dvobj_to_halmac() and ect. */ #define DEFAULT_INDICATOR_TIMELMT 1000 /* ms */ -#define FIRMWARE_MAX_SIZE HALMAC_FW_SIZE_MAX_88XX #define MSG_PREFIX "[HALMAC]" +#define RTW_HALMAC_DLFW_MEM_NO_STOP_TX + /* * Driver API for HALMAC operations */ @@ -39,14 +39,19 @@ static u8 _halmac_mac_reg_page0_chk(const char *func, struct dvobj_priv *dvobj, if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) return _TRUE; + if (pwrpriv->lps_level == LPS_NORMAL) + return _TRUE; + if (pwrpriv->rpwm >= PS_STATE_S2) return _TRUE; if (offset & (WLAN_IOREG_DEVICE_ID << 13)) { /*WLAN_IOREG_OFFSET*/ mac_reg_offset = offset & HALMAC_WLAN_MAC_REG_MSK; if (mac_reg_offset < 0x100) { - RTW_ERR(FUNC_ADPT_FMT "access MAC REG -0x%04x in PS-mode:0x%02x\n", - FUNC_ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mac_reg_offset, pwrpriv->pwr_mode); + RTW_ERR(FUNC_ADPT_FMT + "access MAC REG -0x%04x in PS-mode:0x%02x (rpwm:0x%02x, lps_level:0x%02x)\n", + FUNC_ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mac_reg_offset, + pwrpriv->pwr_mode, pwrpriv->rpwm, pwrpriv->lps_level); rtw_warn_on(1); return _FALSE; } @@ -176,7 +181,6 @@ static u32 _halmac_sdio_reg_read_32(void *p, u32 offset) static u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data) { struct dvobj_priv *d = (struct dvobj_priv *)p; - PSDIO_DATA psdio = &d->intf_data; u8 *pbuf; u8 ret; u8 rst = _FALSE; @@ -184,8 +188,7 @@ static u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data) sdio_read_size = RND4(size); - if (sdio_read_size > psdio->block_transfer_len) - sdio_read_size = _RND(sdio_read_size, psdio->block_transfer_len); + sdio_read_size = rtw_sdio_cmd53_align_size(d, sdio_read_size); pbuf = rtw_zmalloc(sdio_read_size); if ((!pbuf) || (!data)) @@ -270,6 +273,22 @@ static void _halmac_sdio_reg_write_32(void *p, u32 offset, u32 val) rtw_mfree(pbuf, 4); } +static u8 _halmac_sdio_read_cia(void *p, u32 offset) +{ + struct dvobj_priv *d; + u8 data = 0; + u8 ret; + + + d = (struct dvobj_priv *)p; + + ret = rtw_sdio_f0_read(d, offset, &data, 1); + if (ret == _FAIL) + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); + + return data; +} + #else /* !CONFIG_SDIO_HCI */ static u8 _halmac_reg_read_8(void *p, u32 offset) @@ -379,7 +398,13 @@ static u8 _halmac_memset(void *p, void *addr, u8 value, u32 size) static void _halmac_udelay(void *p, u32 us) { - rtw_udelay_os(us); + /* Most hardware polling wait time < 50us) */ + if (us <= 50) + rtw_udelay_os(us); + else if (us <= 1000) + rtw_usleep_os(us); + else + rtw_msleep_os(RTW_DIV_ROUND_UP(us, 1000)); } static u8 _halmac_mutex_init(void *p, HALMAC_MUTEX *pMutex) @@ -466,14 +491,15 @@ const char *const RTW_HALMAC_FEATURE_NAME[] = { "HALMAC_FEATURE_IQK", "HALMAC_FEATURE_POWER_TRACKING", "HALMAC_FEATURE_PSD", + "HALMAC_FEATURE_FW_SNDING", "HALMAC_FEATURE_ALL" }; -static inline u8 is_valid_id_status(HALMAC_FEATURE_ID id, HALMAC_CMD_PROCESS_STATUS status) +static inline u8 is_valid_id_status(enum halmac_feature_id id, enum halmac_cmd_process_status status) { switch (id) { case HALMAC_FEATURE_CFG_PARA: - RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + RTW_DBG("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); break; case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE: RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); @@ -508,6 +534,9 @@ static inline u8 is_valid_id_status(HALMAC_FEATURE_ID id, HALMAC_CMD_PROCESS_STA case HALMAC_FEATURE_PSD: RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); break; + case HALMAC_FEATURE_FW_SNDING: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + break; case HALMAC_FEATURE_ALL: RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); break; @@ -519,7 +548,7 @@ static inline u8 is_valid_id_status(HALMAC_FEATURE_ID id, HALMAC_CMD_PROCESS_STA return _TRUE; } -static int init_halmac_event_with_waittime(struct dvobj_priv *d, HALMAC_FEATURE_ID id, u8 *buf, u32 size, u32 time) +static int init_halmac_event_with_waittime(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size, u32 time) { struct submit_ctx *sctx; @@ -545,12 +574,12 @@ static int init_halmac_event_with_waittime(struct dvobj_priv *d, HALMAC_FEATURE_ return 0; } -static inline int init_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id, u8 *buf, u32 size) +static inline int init_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size) { return init_halmac_event_with_waittime(d, id, buf, size, DEFAULT_INDICATOR_TIMELMT); } -static void free_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) +static void free_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id) { struct submit_ctx *sctx; @@ -563,10 +592,10 @@ static void free_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) rtw_mfree((u8 *)sctx, sizeof(*sctx)); } -static int wait_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) +static int wait_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; struct submit_ctx *sctx; int ret; @@ -594,7 +623,7 @@ static int wait_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) * Return: * Always return _TRUE, HALMAC don't care the return value. */ -static u8 _halmac_event_indication(void *p, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS process_status, u8 *buf, u32 size) +static u8 _halmac_event_indication(void *p, enum halmac_feature_id feature_id, enum halmac_cmd_process_status process_status, u8 *buf, u32 size) { struct dvobj_priv *d; PADAPTER adapter; @@ -646,7 +675,7 @@ static u8 _halmac_event_indication(void *p, HALMAC_FEATURE_ID feature_id, HALMAC return _TRUE; } -HALMAC_PLATFORM_API rtw_halmac_platform_api = { +struct halmac_platform_api rtw_halmac_platform_api = { /* R/W register */ #ifdef CONFIG_SDIO_HCI .SDIO_CMD52_READ = _halmac_sdio_cmd52_read, @@ -658,7 +687,7 @@ HALMAC_PLATFORM_API rtw_halmac_platform_api = { .SDIO_CMD53_WRITE_8 = _halmac_sdio_reg_write_8, .SDIO_CMD53_WRITE_16 = _halmac_sdio_reg_write_16, .SDIO_CMD53_WRITE_32 = _halmac_sdio_reg_write_32, - + .SDIO_CMD52_CIA_READ = _halmac_sdio_read_cia, #endif /* CONFIG_SDIO_HCI */ #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCIE_HCI) .REG_READ_8 = _halmac_reg_read_8, @@ -697,8 +726,8 @@ HALMAC_PLATFORM_API rtw_halmac_platform_api = { u8 rtw_halmac_read8(struct intf_hdl *pintfhdl, u32 addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; /* WARNING: pintf_dev should not be null! */ @@ -710,8 +739,8 @@ u8 rtw_halmac_read8(struct intf_hdl *pintfhdl, u32 addr) u16 rtw_halmac_read16(struct intf_hdl *pintfhdl, u32 addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; /* WARNING: pintf_dev should not be null! */ @@ -723,8 +752,8 @@ u16 rtw_halmac_read16(struct intf_hdl *pintfhdl, u32 addr) u32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; /* WARNING: pintf_dev should not be null! */ @@ -734,29 +763,119 @@ u32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr) return api->halmac_reg_read_32(mac, addr); } +static void _read_register(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf) +{ +#if 1 + struct _ADAPTER *a; + u32 i, n; + u16 val16; + u32 val32; + + + a = dvobj_get_primary_adapter(d); + + i = addr & 0x3; + /* Handle address not start from 4 bytes alignment case */ + if (i) { + val32 = cpu_to_le32(rtw_read32(a, addr & ~0x3)); + n = 4 - i; + _rtw_memcpy(buf, ((u8 *)&val32) + i, n); + i = n; + cnt -= n; + } + + while (cnt) { + if (cnt >= 4) + n = 4; + else if (cnt >= 2) + n = 2; + else + n = 1; + cnt -= n; + + switch (n) { + case 1: + buf[i] = rtw_read8(a, addr+i); + i++; + break; + case 2: + val16 = cpu_to_le16(rtw_read16(a, addr+i)); + _rtw_memcpy(&buf[i], &val16, 2); + i += 2; + break; + case 4: + val32 = cpu_to_le32(rtw_read32(a, addr+i)); + _rtw_memcpy(&buf[i], &val32, 4); + i += 4; + break; + } + } +#else + struct _ADAPTER *a; + u32 i; + + + a = dvobj_get_primary_adapter(d); + for (i = 0; i < cnt; i++) + buf[i] = rtw_read8(a, addr + i); +#endif +} + +#ifdef CONFIG_SDIO_HCI +static int _sdio_read_local(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + + + if (buf == NULL) + return -1; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_reg_sdio_cmd53_read_n(mac, addr, cnt, buf); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: addr=0x%08x cnt=%d err=%d\n", + __FUNCTION__, addr, cnt, status); + return -1; + } + + return 0; +} +#endif /* CONFIG_SDIO_HCI */ + void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem) { -#if defined(CONFIG_SDIO_HCI) - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct dvobj_priv *d; + if (pmem == NULL) { RTW_ERR("pmem is NULL\n"); return; } - /* WARNING: pintf_dev should not be null! */ - mac = dvobj_to_halmac(pintfhdl->pintf_dev); - api = HALMAC_GET_API(mac); - api->halmac_reg_sdio_cmd53_read_n(mac, addr, cnt, pmem); -#endif + d = pintfhdl->pintf_dev; + +#ifdef CONFIG_SDIO_HCI + if (addr & 0xFFFF0000) { + int err = 0; + + err = _sdio_read_local(d, addr, cnt, pmem); + if (!err) + return; + } +#endif /* CONFIG_SDIO_HCI */ + + _read_register(d, addr, cnt, pmem); } #ifdef CONFIG_SDIO_INDIRECT_ACCESS u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; /* WARNING: pintf_dev should not be null! */ mac = dvobj_to_halmac(pintfhdl->pintf_dev); @@ -768,8 +887,8 @@ u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr) u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; u16 val16 = 0; /* WARNING: pintf_dev should not be null! */ @@ -782,8 +901,8 @@ u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr) u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; /* WARNING: pintf_dev should not be null! */ @@ -792,13 +911,13 @@ u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr) return api->halmac_reg_read_indirect_32(mac, addr); } -#endif +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ int rtw_halmac_write8(struct intf_hdl *pintfhdl, u32 addr, u8 value) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; /* WARNING: pintf_dev should not be null! */ @@ -815,9 +934,9 @@ int rtw_halmac_write8(struct intf_hdl *pintfhdl, u32 addr, u8 value) int rtw_halmac_write16(struct intf_hdl *pintfhdl, u32 addr, u16 value) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; /* WARNING: pintf_dev should not be null! */ @@ -834,9 +953,9 @@ int rtw_halmac_write16(struct intf_hdl *pintfhdl, u32 addr, u16 value) int rtw_halmac_write32(struct intf_hdl *pintfhdl, u32 addr, u32 value) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; /* WARNING: pintf_dev should not be null! */ @@ -851,6 +970,50 @@ int rtw_halmac_write32(struct intf_hdl *pintfhdl, u32 addr, u32 value) return -1; } +static int init_write_rsvd_page_size(struct dvobj_priv *d) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + u32 size = 0; + struct halmac_ofld_func_info ofld_info; + enum halmac_ret_status status; + int err = 0; + + +#ifdef CONFIG_USB_HCI + /* for USB do not exceed MAX_CMDBUF_SZ */ + size = 0x1000; +#elif defined(CONFIG_PCIE_HCI) + size = MAX_CMDBUF_SZ - TXDESC_OFFSET; +#elif defined(CONFIG_SDIO_HCI) + size = 0x7000; /* 28KB */ +#endif + + /* If size==0, use HALMAC default setting and don't call any function */ + if (!size) + return 0; + + err = rtw_halmac_set_max_dl_fw_size(d, size); + if (err) { + RTW_ERR("%s: Fail to set max download fw size!\n", __FUNCTION__); + return -1; + } + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + _rtw_memset(&ofld_info, 0, sizeof(ofld_info)); + ofld_info.halmac_malloc_max_sz = 0xFFFFFFFF; + ofld_info.rsvd_pg_drv_buf_max_sz = size; + status = api->halmac_ofld_func_cfg(mac, &ofld_info); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: Fail to config offload parameters!\n", __FUNCTION__); + return -1; + } + + return 0; +} + static int init_priv(struct halmacpriv *priv) { struct halmac_indicator *indicator; @@ -903,10 +1066,10 @@ static void deinit_priv(struct halmacpriv *priv) } #ifdef CONFIG_SDIO_HCI -static enum _HALMAC_SDIO_SPEC_VER _sdio_ver_drv2halmac(struct dvobj_priv *d) +static enum halmac_sdio_spec_ver _sdio_ver_drv2halmac(struct dvobj_priv *d) { bool v3; - enum _HALMAC_SDIO_SPEC_VER ver; + enum halmac_sdio_spec_ver ver; v3 = rtw_is_sdio30(dvobj_get_primary_adapter(d)); @@ -919,39 +1082,41 @@ static enum _HALMAC_SDIO_SPEC_VER _sdio_ver_drv2halmac(struct dvobj_priv *d) } #endif /* CONFIG_SDIO_HCI */ -void rtw_dump_halmac_info(void *sel) +void rtw_halmac_get_version(char *str, u32 len) { - HALMAC_RET_STATUS status; - HALMAC_VER halmac_version; + enum halmac_ret_status status; + struct halmac_ver ver; - status = halmac_get_version(&halmac_version); + + status = halmac_get_version(&ver); if (status != HALMAC_RET_SUCCESS) return; - RTW_PRINT_SEL(sel, "HALMAC VER -%x.%x.%x\n", halmac_version.major_ver, halmac_version.prototype_ver, halmac_version.minor_ver); + rtw_sprintf(str, len, "V%d_%02d_%02d", + ver.major_ver, ver.prototype_ver, ver.minor_ver); } -int rtw_halmac_init_adapter(struct dvobj_priv *d, PHALMAC_PLATFORM_API pf_api) +int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api) { - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_INTERFACE intf; - HALMAC_RET_STATUS status; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_interface intf; + enum halmac_ret_status status; int err = 0; #ifdef CONFIG_SDIO_HCI - HALMAC_SDIO_HW_INFO info; + struct halmac_sdio_hw_info info; #endif /* CONFIG_SDIO_HCI */ halmac = dvobj_to_halmac(d); if (halmac) { - err = 0; - goto out; + RTW_WARN("%s: initialize already completed!\n", __FUNCTION__); + goto error; } err = init_priv(&d->hmpriv); if (err) - goto out; + goto error; #ifdef CONFIG_SDIO_HCI intf = HALMAC_INTERFACE_SDIO; @@ -967,7 +1132,9 @@ int rtw_halmac_init_adapter(struct dvobj_priv *d, PHALMAC_PLATFORM_API pf_api) if (HALMAC_RET_SUCCESS != status) { RTW_ERR("%s: halmac_init_adapter fail!(status=%d)\n", __FUNCTION__, status); err = -1; - goto out; + if (halmac) + goto deinit; + goto free; } dvobj_set_halmac(d, halmac); @@ -976,183 +1143,1283 @@ int rtw_halmac_init_adapter(struct dvobj_priv *d, PHALMAC_PLATFORM_API pf_api) if (status != HALMAC_RET_SUCCESS) { RTW_ERR("%s: halmac_interface_integration_tuning fail!(status=%d)\n", __FUNCTION__, status); err = -1; - goto out; + goto deinit; } status = api->halmac_phy_cfg(halmac, HALMAC_INTF_PHY_PLATFORM_ALL); if (status != HALMAC_RET_SUCCESS) { RTW_ERR("%s: halmac_phy_cfg fail!(status=%d)\n", __FUNCTION__, status); err = -1; - goto out; + goto deinit; } + init_write_rsvd_page_size(d); + #ifdef CONFIG_SDIO_HCI + _rtw_memset(&info, 0, sizeof(info)); info.spec_ver = _sdio_ver_drv2halmac(d); - /* clock unit is MHz */ + /* Convert clock speed unit to MHz from Hz */ info.clock_speed = RTW_DIV_ROUND_UP(rtw_sdio_get_clock(d), 1000000); - RTW_DBG("%s: SDIO clock=%uMHz ver=%u\n", __FUNCTION__, info.clock_speed, info.spec_ver+2); + info.block_size = rtw_sdio_get_block_size(d); + RTW_DBG("%s: SDIO ver=%u clock=%uMHz blk_size=%u bytes\n", + __FUNCTION__, info.spec_ver+2, info.clock_speed, + info.block_size); status = api->halmac_sdio_hw_info(halmac, &info); if (status != HALMAC_RET_SUCCESS) { - RTW_ERR("%s: halmac_sdio_hw_info fail!(status=%d)\n", __FUNCTION__, status); + RTW_ERR("%s: halmac_sdio_hw_info fail!(status=%d)\n", + __FUNCTION__, status); err = -1; - goto out; + goto deinit; } #endif /* CONFIG_SDIO_HCI */ -out: - if (err) - rtw_halmac_deinit_adapter(d); + return 0; + +deinit: + status = halmac_deinit_adapter(halmac); + dvobj_set_halmac(d, NULL); + if (status != HALMAC_RET_SUCCESS) + RTW_ERR("%s: halmac_deinit_adapter fail!(status=%d)\n", + __FUNCTION__, status); + +free: + deinit_priv(&d->hmpriv); +error: return err; } int rtw_halmac_deinit_adapter(struct dvobj_priv *d) { - PHALMAC_ADAPTER halmac; - HALMAC_RET_STATUS status; + struct halmac_adapter *halmac; + enum halmac_ret_status status; int err = 0; halmac = dvobj_to_halmac(d); - if (!halmac) { - err = 0; - goto out; + if (halmac) { + status = halmac_deinit_adapter(halmac); + dvobj_set_halmac(d, NULL); + if (status != HALMAC_RET_SUCCESS) + err = -1; } deinit_priv(&d->hmpriv); - status = halmac_deinit_adapter(halmac); - dvobj_set_halmac(d, NULL); - if (status != HALMAC_RET_SUCCESS) { - err = -1; - goto out; - } - -out: return err; } -/* - * Description: - * Power on device hardware. - * [Notice!] If device's power state is on before, - * it would be power off first and turn on power again. - * - * Return: - * 0 power on success - * -1 power on fail - * -2 power state unchange - */ -int rtw_halmac_poweron(struct dvobj_priv *d) +static inline enum halmac_portid _hw_port_drv2halmac(enum _hw_port hwport) { - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - int err = -1; + enum halmac_portid port = HALMAC_PORTID_NUM; - halmac = dvobj_to_halmac(d); - if (!halmac) - goto out; + switch (hwport) { + case HW_PORT0: + port = HALMAC_PORTID0; + break; + case HW_PORT1: + port = HALMAC_PORTID1; + break; + case HW_PORT2: + port = HALMAC_PORTID2; + break; + case HW_PORT3: + port = HALMAC_PORTID3; + break; + case HW_PORT4: + port = HALMAC_PORTID4; + break; + default: + break; + } - api = HALMAC_GET_API(halmac); + return port; +} - status = api->halmac_pre_init_system_cfg(halmac); - if (status != HALMAC_RET_SUCCESS) - goto out; +static enum halmac_network_type_select _network_type_drv2halmac(u8 type) +{ + enum halmac_network_type_select network = HALMAC_NETWORK_UNDEFINE; -#ifdef CONFIG_SDIO_HCI - status = api->halmac_sdio_cmd53_4byte(halmac, HALMAC_SDIO_CMD53_4BYTE_MODE_RW); - if (status != HALMAC_RET_SUCCESS) - goto out; -#endif /* CONFIG_SDIO_HCI */ - status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON); - if (HALMAC_RET_PWR_UNCHANGE == status) { - /* - * Work around for warm reboot but device not power off, - * but it would also fall into this case when auto power on is enabled. - */ - api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF); - status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON); - RTW_WARN("%s: Power state abnormal, try to recover...%s\n", - __FUNCTION__, (HALMAC_RET_SUCCESS == status)?"OK":"FAIL!"); + switch (type) { + case _HW_STATE_NOLINK_: + case _HW_STATE_MONITOR_: + network = HALMAC_NETWORK_NO_LINK; + break; + + case _HW_STATE_ADHOC_: + network = HALMAC_NETWORK_ADHOC; + break; + + case _HW_STATE_STATION_: + network = HALMAC_NETWORK_INFRASTRUCTURE; + break; + + case _HW_STATE_AP_: + network = HALMAC_NETWORK_AP; + break; } - if (HALMAC_RET_SUCCESS != status) { - if (HALMAC_RET_PWR_UNCHANGE == status) - err = -2; - goto out; + + return network; +} + +static u8 _network_type_halmac2drv(enum halmac_network_type_select network) +{ + u8 type = _HW_STATE_NOLINK_; + + + switch (network) { + case HALMAC_NETWORK_NO_LINK: + case HALMAC_NETWORK_UNDEFINE: + type = _HW_STATE_NOLINK_; + break; + + case HALMAC_NETWORK_ADHOC: + type = _HW_STATE_ADHOC_; + break; + + case HALMAC_NETWORK_INFRASTRUCTURE: + type = _HW_STATE_STATION_; + break; + + case HALMAC_NETWORK_AP: + type = _HW_STATE_AP_; + break; } - status = api->halmac_init_system_cfg(halmac); - if (status != HALMAC_RET_SUCCESS) - goto out; + return type; +} - err = 0; -out: - return err; +static void _beacon_ctrl_halmac2drv(struct halmac_bcn_ctrl *ctrl, + struct rtw_halmac_bcn_ctrl *drv_ctrl) +{ + drv_ctrl->rx_bssid_fit = ctrl->dis_rx_bssid_fit ? 0 : 1; + drv_ctrl->txbcn_rpt = ctrl->en_txbcn_rpt ? 1 : 0; + drv_ctrl->tsf_update = ctrl->dis_tsf_udt ? 0 : 1; + drv_ctrl->enable_bcn = ctrl->en_bcn ? 1 : 0; + drv_ctrl->rxbcn_rpt = ctrl->en_rxbcn_rpt ? 1 : 0; + drv_ctrl->p2p_ctwin = ctrl->en_p2p_ctwin ? 1 : 0; + drv_ctrl->p2p_bcn_area = ctrl->en_p2p_bcn_area ? 1 : 0; } -/* - * Description: - * Power off device hardware. - * - * Return: - * 0 Power off success - * -1 Power off fail - */ -int rtw_halmac_poweroff(struct dvobj_priv *d) +static void _beacon_ctrl_drv2halmac(struct rtw_halmac_bcn_ctrl *drv_ctrl, + struct halmac_bcn_ctrl *ctrl) { - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - int err = -1; + ctrl->dis_rx_bssid_fit = drv_ctrl->rx_bssid_fit ? 0 : 1; + ctrl->en_txbcn_rpt = drv_ctrl->txbcn_rpt ? 1 : 0; + ctrl->dis_tsf_udt = drv_ctrl->tsf_update ? 0 : 1; + ctrl->en_bcn = drv_ctrl->enable_bcn ? 1 : 0; + ctrl->en_rxbcn_rpt = drv_ctrl->rxbcn_rpt ? 1 : 0; + ctrl->en_p2p_ctwin = drv_ctrl->p2p_ctwin ? 1 : 0; + ctrl->en_p2p_bcn_area = drv_ctrl->p2p_bcn_area ? 1 : 0; +} +int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; - halmac = dvobj_to_halmac(d); - if (!halmac) - goto out; - api = HALMAC_GET_API(halmac); + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); - status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF); - if ((HALMAC_RET_SUCCESS != status) - && (HALMAC_RET_PWR_UNCHANGE != status)) - goto out; + status = api->halmac_get_hw_value(mac, hw_id, pvalue); + if (HALMAC_RET_SUCCESS != status) + return -1; - err = 0; -out: - return err; + return 0; } -/* - * Note: - * When this function return, the register REG_RCR may be changed. +/** + * rtw_halmac_get_tx_fifo_size() - TX FIFO size + * @d: struct dvobj_priv* + * @size: TX FIFO size, unit is byte. + * + * Get TX FIFO size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. */ -int rtw_halmac_config_rx_info(struct dvobj_priv *d, HALMAC_DRV_INFO info) +int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size) { - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - int err = -1; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; halmac = dvobj_to_halmac(d); api = HALMAC_GET_API(halmac); - status = api->halmac_cfg_drv_info(halmac, info); + status = api->halmac_get_hw_value(halmac, HALMAC_HW_TXFIFO_SIZE, &val); if (status != HALMAC_RET_SUCCESS) - goto out; + return -1; - err = 0; -out: - return err; + *size = val; + + return 0; } -#ifdef CONFIG_SUPPORT_TRX_SHARED -static inline HALMAC_RX_FIFO_EXPANDING_MODE _trx_share_mode_drv2halmac(u8 trx_share_mode) -{ - if (0 == trx_share_mode) +/** + * rtw_halmac_get_rx_fifo_size() - RX FIFO size + * @d: struct dvobj_priv* + * @size: RX FIFO size, unit is byte + * + * Get RX FIFO size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_RXFIFO_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/** + * rtw_halmac_get_rsvd_drv_pg_bndy() - Reserve page boundary of driver + * @d: struct dvobj_priv* + * @size: Page size, unit is byte + * + * Get reserve page boundary of driver from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u16 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *bndy = val; + + return 0; +} + +/** + * rtw_halmac_get_page_size() - Page size + * @d: struct dvobj_priv* + * @size: Page size, unit is byte + * + * Get TX/RX page size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_PAGE_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/** + * rtw_halmac_get_tx_agg_align_size() - TX aggregation align size + * @d: struct dvobj_priv* + * @size: TX aggregation align size, unit is byte + * + * Get TX aggregation align size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u16 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_AGG_ALIGN_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/** + * rtw_halmac_get_rx_agg_align_size() - RX aggregation align size + * @d: struct dvobj_priv* + * @size: RX aggregation align size, unit is byte + * + * Get RX aggregation align size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u8 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_AGG_ALIGN_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/* + * Description: + * Get RX driver info size. RX driver info is a small memory space between + * scriptor and RX payload. + * + * +-------------------------+ + * | RX descriptor | + * | usually 24 bytes | + * +-------------------------+ + * | RX driver info | + * | depends on driver cfg | + * +-------------------------+ + * | RX paylad | + * | | + * +-------------------------+ + * + * Parameter: + * d pointer to struct dvobj_priv of driver + * sz rx driver info size in bytes. + * + * Rteurn: + * 0 Success + * other Fail + */ +int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *d, u8 *sz) +{ + enum halmac_ret_status status; + struct halmac_adapter *halmac = dvobj_to_halmac(d); + struct halmac_api *api = HALMAC_GET_API(halmac); + u8 dw = 0; + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_DRV_INFO_SIZE, &dw); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *sz = dw * 8; + return 0; +} + +/** + * rtw_halmac_get_tx_desc_size() - TX descriptor size + * @d: struct dvobj_priv* + * @size: TX descriptor size, unit is byte. + * + * Get TX descriptor size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_DESC_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/** + * rtw_halmac_get_rx_desc_size() - RX descriptor size + * @d: struct dvobj_priv* + * @size: RX descriptor size, unit is byte. + * + * Get RX descriptor size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_DESC_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + + +/** + * rtw_halmac_get_fw_max_size() - Firmware MAX size + * @d: struct dvobj_priv* + * @size: MAX Firmware size, unit is byte. + * + * Get Firmware MAX size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +static int rtw_halmac_get_fw_max_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_FW_MAX_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/** + * rtw_halmac_get_ori_h2c_size() - Original H2C MAX size + * @d: struct dvobj_priv* + * @size: H2C MAX size, unit is byte. + * + * Get original H2C MAX size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_ORI_H2C_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size) +{ + enum halmac_ret_status status; + struct halmac_adapter *halmac; + struct halmac_api *api; + u8 val; + + + if (!size) + return -1; + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_OQT_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + return 0; +} + +int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num) +{ + enum halmac_ret_status status; + struct halmac_adapter *halmac; + struct halmac_api *api; + u8 val; + + + if (!num) + return -1; + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_QUEUE_NUM, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *num = val; + return 0; +} + +/** + * rtw_halmac_get_mac_address() - Get MAC address of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @addr: buffer for storing MAC address + * + * Get MAC address of specific port from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + union halmac_wlan_addr hwa; + enum halmac_ret_status status; + int err = -1; + + + if (!addr) + goto out; + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + _rtw_memset(&hwa, 0, sizeof(hwa)); + + status = api->halmac_get_mac_addr(halmac, port, &hwa); + if (status != HALMAC_RET_SUCCESS) + goto out; + + _rtw_memcpy(addr, hwa.addr, 6); + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_get_network_type() - Get network type of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @type: buffer to put network type (_HW_STATE_*) + * + * Get network type of specific port from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type) +{ +#if 0 + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + enum halmac_network_type_select network; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + network = HALMAC_NETWORK_UNDEFINE; + + status = api->halmac_get_net_type(halmac, port, &network); + if (status != HALMAC_RET_SUCCESS) + goto out; + + *type = _network_type_halmac2drv(network); + + err = 0; +out: + return err; +#else + struct _ADAPTER *a; + enum halmac_portid port; + enum halmac_network_type_select network; + u32 val; + int err = -1; + + + a = dvobj_get_primary_adapter(d); + port = _hw_port_drv2halmac(hwport); + network = HALMAC_NETWORK_UNDEFINE; + + switch (port) { + case HALMAC_PORTID0: + val = rtw_read32(a, REG_CR); + network = BIT_GET_NETYPE0(val); + break; + + case HALMAC_PORTID1: + val = rtw_read32(a, REG_CR); + network = BIT_GET_NETYPE1(val); + break; + + case HALMAC_PORTID2: + val = rtw_read32(a, REG_CR_EXT); + network = BIT_GET_NETYPE2(val); + break; + + case HALMAC_PORTID3: + val = rtw_read32(a, REG_CR_EXT); + network = BIT_GET_NETYPE3(val); + break; + + case HALMAC_PORTID4: + val = rtw_read32(a, REG_CR_EXT); + network = BIT_GET_NETYPE4(val); + break; + + default: + goto out; + } + + *type = _network_type_halmac2drv(network); + + err = 0; +out: + return err; +#endif +} + +/** + * rtw_halmac_get_bcn_ctrl() - Get beacon control setting of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @bcn_ctrl: setting of beacon control + * + * Get beacon control setting of specific port from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, + struct rtw_halmac_bcn_ctrl *bcn_ctrl) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + struct halmac_bcn_ctrl ctrl; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + _rtw_memset(&ctrl, 0, sizeof(ctrl)); + + status = api->halmac_rw_bcn_ctrl(halmac, port, 0, &ctrl); + if (status != HALMAC_RET_SUCCESS) + goto out; + _beacon_ctrl_halmac2drv(&ctrl, bcn_ctrl); + + err = 0; +out: + return err; +} + +/* + * Note: + * When this function return, the register REG_RCR may be changed. + */ +int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_cfg_drv_info(halmac, info); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_max_dl_fw_size() - Set the MAX download firmware size + * @d: struct dvobj_priv* + * @size: the max download firmware size in one I/O + * + * Set the max download firmware size in one I/O. + * Please also consider the max size of the callback function "SEND_RSVD_PAGE" + * could accept, because download firmware would call "SEND_RSVD_PAGE" to send + * firmware to IC. + * + * If the value of "size" is not even, it would be rounded down to nearest + * even, and 0 and 1 are both invalid value. + * + * Return 0 for setting OK, otherwise fail. + */ +int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + + + if (!size || (size == 1)) + return -1; + + mac = dvobj_to_halmac(d); + if (!mac) { + RTW_ERR("%s: HALMAC is not ready!!\n", __FUNCTION__); + return -1; + } + api = HALMAC_GET_API(mac); + + size &= ~1; /* round down to even */ + status = api->halmac_cfg_max_dl_size(mac, size); + if (status != HALMAC_RET_SUCCESS) { + RTW_WARN("%s: Fail to cfg_max_dl_size(%d), err=%d!!\n", + __FUNCTION__, size, status); + return -1; + } + + return 0; +} + +/** + * rtw_halmac_set_mac_address() - Set mac address of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @addr: mac address + * + * Set self mac address of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + union halmac_wlan_addr hwa; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + port = _hw_port_drv2halmac(hwport); + _rtw_memset(&hwa, 0, sizeof(hwa)); + _rtw_memcpy(hwa.addr, addr, 6); + + status = api->halmac_cfg_mac_addr(halmac, port, &hwa); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_bssid() - Set BSSID of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @addr: BSSID, mac address of AP + * + * Set BSSID of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + union halmac_wlan_addr hwa; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + + _rtw_memset(&hwa, 0, sizeof(hwa)); + _rtw_memcpy(hwa.addr, addr, 6); + status = api->halmac_cfg_bssid(halmac, port, &hwa); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_tx_address() - Set transmitter address of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @addr: transmitter address + * + * Set transmitter address of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + union halmac_wlan_addr hwa; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + _rtw_memset(&hwa, 0, sizeof(hwa)); + _rtw_memcpy(hwa.addr, addr, 6); + + status = api->halmac_cfg_transmitter_addr(halmac, port, &hwa); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_network_type() - Set network type of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @type: network type (_HW_STATE_*) + * + * Set network type of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + enum halmac_network_type_select network; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + network = _network_type_drv2halmac(type); + + status = api->halmac_cfg_net_type(halmac, port, network); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_reset_tsf() - Reset TSF timer of specific port + * @d: struct dvobj_priv* + * @hwport: port + * + * Notice HALMAC to reset timing synchronization function(TSF) timer of + * specific port. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + + status = api->halmac_cfg_tsf_rst(halmac, port); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_bcn_interval() - Set beacon interval of each port + * @d: struct dvobj_priv* + * @hwport: port + * @space: beacon interval, unit is ms + * + * Set beacon interval of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, + u32 interval) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + + status = api->halmac_cfg_bcn_space(halmac, port, interval); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_bcn_ctrl() - Set beacon control setting of each port + * @d: struct dvobj_priv* + * @hwport: port + * @bcn_ctrl: setting of beacon control + * + * Set beacon control setting of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, + struct rtw_halmac_bcn_ctrl *bcn_ctrl) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + struct halmac_bcn_ctrl ctrl; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + _rtw_memset(&ctrl, 0, sizeof(ctrl)); + _beacon_ctrl_drv2halmac(bcn_ctrl, &ctrl); + + status = api->halmac_rw_bcn_ctrl(halmac, port, 1, &ctrl); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_aid() - Set association identifier(AID) of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @aid: Association identifier + * + * Set association identifier(AID) of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + +#if 0 + status = api->halmac_cfg_aid(halmac, port, aid); + if (status != HALMAC_RET_SUCCESS) + goto out; +#else +{ + struct _ADAPTER *a; + u32 addr; + u16 val; + + a = dvobj_get_primary_adapter(d); + + switch (port) { + case 0: + addr = REG_BCN_PSR_RPT; + val = rtw_read16(a, addr); + val = BIT_SET_PS_AID_0(val, aid); + rtw_write16(a, addr, val); + break; + + case 1: + addr = REG_BCN_PSR_RPT1; + val = rtw_read16(a, addr); + val = BIT_SET_PS_AID_1(val, aid); + rtw_write16(a, addr, val); + break; + + case 2: + addr = REG_BCN_PSR_RPT2; + val = rtw_read16(a, addr); + val = BIT_SET_PS_AID_2(val, aid); + rtw_write16(a, addr, val); + break; + + case 3: + addr = REG_BCN_PSR_RPT3; + val = rtw_read16(a, addr); + val = BIT_SET_PS_AID_3(val, aid); + rtw_write16(a, addr, val); + break; + + case 4: + addr = REG_BCN_PSR_RPT4; + val = rtw_read16(a, addr); + val = BIT_SET_PS_AID_4(val, aid); + rtw_write16(a, addr, val); + break; + + default: + goto out; + } +} +#endif + + err = 0; +out: + return err; +} + +int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw); + if (HALMAC_RET_SUCCESS != status) + return -1; + + return 0; +} + +/** + * rtw_halmac_set_edca() - config edca parameter + * @d: struct dvobj_priv* + * @queue: XMIT_[VO/VI/BE/BK]_QUEUE + * @aifs: Arbitration inter-frame space(AIFS) + * @cw: Contention window(CW) + * @txop: MAX Transmit Opportunity(TXOP) + * + * Return: 0 if process OK, otherwise -1. + */ +int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_acq_id ac; + struct halmac_edca_para edca; + enum halmac_ret_status status; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + switch (queue) { + case XMIT_VO_QUEUE: + ac = HALMAC_ACQ_ID_VO; + break; + case XMIT_VI_QUEUE: + ac = HALMAC_ACQ_ID_VI; + break; + case XMIT_BE_QUEUE: + ac = HALMAC_ACQ_ID_BE; + break; + case XMIT_BK_QUEUE: + ac = HALMAC_ACQ_ID_BK; + break; + default: + return -1; + } + + edca.aifs = aifs; + edca.cw = cw; + edca.txop_limit = txop; + + status = api->halmac_cfg_edca_para(mac, ac, &edca); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +/* + * Description: + * Power on device hardware. + * [Notice!] If device's power state is on before, + * it would be power off first and turn on power again. + * + * Return: + * 0 power on success + * -1 power on fail + * -2 power state unchange + */ +int rtw_halmac_poweron(struct dvobj_priv *d) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + if (!halmac) + goto out; + + api = HALMAC_GET_API(halmac); + + status = api->halmac_pre_init_system_cfg(halmac); + if (status != HALMAC_RET_SUCCESS) + goto out; + +#ifdef CONFIG_SDIO_HCI + status = api->halmac_sdio_cmd53_4byte(halmac, HALMAC_SDIO_CMD53_4BYTE_MODE_RW); + if (status != HALMAC_RET_SUCCESS) + goto out; +#endif /* CONFIG_SDIO_HCI */ + + status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON); + if (HALMAC_RET_PWR_UNCHANGE == status) { + /* + * Work around for warm reboot but device not power off, + * but it would also fall into this case when auto power on is enabled. + */ + api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF); + status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON); + RTW_WARN("%s: Power state abnormal, try to recover...%s\n", + __FUNCTION__, (HALMAC_RET_SUCCESS == status)?"OK":"FAIL!"); + } + if (HALMAC_RET_SUCCESS != status) { + if (HALMAC_RET_PWR_UNCHANGE == status) + err = -2; + goto out; + } + + status = api->halmac_init_system_cfg(halmac); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/* + * Description: + * Power off device hardware. + * + * Return: + * 0 Power off success + * -1 Power off fail + */ +int rtw_halmac_poweroff(struct dvobj_priv *d) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + if (!halmac) + goto out; + + api = HALMAC_GET_API(halmac); + + status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF); + if ((HALMAC_RET_SUCCESS != status) + && (HALMAC_RET_PWR_UNCHANGE != status)) + goto out; + + err = 0; +out: + return err; +} + +#ifdef CONFIG_SUPPORT_TRX_SHARED +static inline enum halmac_rx_fifo_expanding_mode _trx_share_mode_drv2halmac(u8 trx_share_mode) +{ + if (0 == trx_share_mode) return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE; else if (1 == trx_share_mode) return HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK; @@ -1163,16 +2430,18 @@ static inline HALMAC_RX_FIFO_EXPANDING_MODE _trx_share_mode_drv2halmac(u8 trx_sh else return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE; } -static HALMAC_RX_FIFO_EXPANDING_MODE _rtw_get_trx_share_mode(_adapter *adapter) + +static enum halmac_rx_fifo_expanding_mode _rtw_get_trx_share_mode(struct _ADAPTER *adapter) { - struct registry_priv *registry_par = &adapter->registrypriv; + struct registry_priv *registry_par = &adapter->registrypriv; return _trx_share_mode_drv2halmac(registry_par->trx_share_mode); } -void dump_trx_share_mode(void *sel, _adapter *adapter) + +void dump_trx_share_mode(void *sel, struct _ADAPTER *adapter) { struct registry_priv *registry_par = &adapter->registrypriv; - u8 mode = _trx_share_mode_drv2halmac(registry_par->trx_share_mode); + u8 mode = _trx_share_mode_drv2halmac(registry_par->trx_share_mode); if (HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK == mode) RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_1"); @@ -1185,21 +2454,62 @@ void dump_trx_share_mode(void *sel, _adapter *adapter) } #endif -static u8 _get_drv_rsvd_page(HALMAC_DRV_RSVD_PG_NUM rsvd_page_number) +static enum halmac_drv_rsvd_pg_num _rsvd_page_num_drv2halmac(u8 num) +{ + if (num <= 8) + return HALMAC_RSVD_PG_NUM8; + if (num <= 16) + return HALMAC_RSVD_PG_NUM16; + if (num <= 24) + return HALMAC_RSVD_PG_NUM24; + if (num <= 32) + return HALMAC_RSVD_PG_NUM32; + if (num <= 64) + return HALMAC_RSVD_PG_NUM64; + + if (num > 128) + RTW_WARN("%s: Fail to allocate RSVD page(%d)!!" + " The MAX RSVD page number is 128...\n", + __FUNCTION__, num); + + return HALMAC_RSVD_PG_NUM128; +} + +static u8 _rsvd_page_num_halmac2drv(enum halmac_drv_rsvd_pg_num rsvd_page_number) { - if (HALMAC_RSVD_PG_NUM16 == rsvd_page_number) - return 16; - else if (HALMAC_RSVD_PG_NUM24 == rsvd_page_number) - return 24; - else if (HALMAC_RSVD_PG_NUM32 == rsvd_page_number) - return 32; + u8 num = 0; - RTW_ERR("%s unknown HALMAC_RSVD_PG type :%d\n", __func__, rsvd_page_number); - rtw_warn_on(1); - return 0; + + switch (rsvd_page_number) { + case HALMAC_RSVD_PG_NUM8: + num = 8; + break; + + case HALMAC_RSVD_PG_NUM16: + num = 16; + break; + + case HALMAC_RSVD_PG_NUM24: + num = 24; + break; + + case HALMAC_RSVD_PG_NUM32: + num = 32; + break; + + case HALMAC_RSVD_PG_NUM64: + num = 64; + break; + + case HALMAC_RSVD_PG_NUM128: + num = 128; + break; + } + + return num; } -static HALMAC_TRX_MODE _choose_trx_mode(struct dvobj_priv *d) +static enum halmac_trx_mode _choose_trx_mode(struct dvobj_priv *d) { PADAPTER p; @@ -1217,30 +2527,27 @@ static HALMAC_TRX_MODE _choose_trx_mode(struct dvobj_priv *d) return HALMAC_TRX_MODE_NORMAL; } -static inline HALMAC_RF_TYPE _rf_type_drv2halmac(RT_RF_TYPE_DEF_E rf_drv) +static inline enum halmac_rf_type _rf_type_drv2halmac(enum rf_type rf_drv) { - HALMAC_RF_TYPE rf_mac; + enum halmac_rf_type rf_mac; switch (rf_drv) { + case RF_1T1R: + rf_mac = HALMAC_RF_1T1R; + break; case RF_1T2R: rf_mac = HALMAC_RF_1T2R; break; - case RF_2T4R: - rf_mac = HALMAC_RF_2T4R; - break; case RF_2T2R: rf_mac = HALMAC_RF_2T2R; break; - case RF_1T1R: - rf_mac = HALMAC_RF_1T1R; - break; - case RF_2T2R_GREEN: - rf_mac = HALMAC_RF_2T2R_GREEN; - break; case RF_2T3R: rf_mac = HALMAC_RF_2T3R; break; + case RF_2T4R: + rf_mac = HALMAC_RF_2T4R; + break; case RF_3T3R: rf_mac = HALMAC_RF_3T3R; break; @@ -1251,22 +2558,120 @@ static inline HALMAC_RF_TYPE _rf_type_drv2halmac(RT_RF_TYPE_DEF_E rf_drv) rf_mac = HALMAC_RF_4T4R; break; default: - rf_mac = (HALMAC_RF_TYPE)rf_drv; + rf_mac = HALMAC_RF_MAX_TYPE; + RTW_ERR("%s: Invalid RF type(0x%x)!\n", __FUNCTION__, rf_drv); break; } return rf_mac; } +static inline enum rf_type _rf_type_halmac2drv(enum halmac_rf_type rf_mac) +{ + enum rf_type rf_drv; + + + switch (rf_mac) { + case HALMAC_RF_1T2R: + rf_drv = RF_1T2R; + break; + case HALMAC_RF_2T4R: + rf_drv = RF_2T4R; + break; + case HALMAC_RF_2T2R: + case HALMAC_RF_2T2R_GREEN: + rf_drv = RF_2T2R; + break; + case HALMAC_RF_2T3R: + rf_drv = RF_2T3R; + break; + case HALMAC_RF_1T1R: + rf_drv = RF_1T1R; + break; + case HALMAC_RF_3T3R: + rf_drv = RF_3T3R; + break; + case HALMAC_RF_3T4R: + rf_drv = RF_3T4R; + break; + case HALMAC_RF_4T4R: + rf_drv = RF_4T4R; + break; + default: + rf_drv = RF_TYPE_MAX; + RTW_ERR("%s: Invalid RF type(0x%x)!\n", __FUNCTION__, rf_mac); + break; + } + + return rf_drv; +} + +static enum odm_cut_version _cut_version_drv2phydm( + enum tag_HAL_Cut_Version_Definition cut_drv) +{ + enum odm_cut_version cut_phydm = ODM_CUT_A; + u32 diff; + + + if (cut_drv > K_CUT_VERSION) + RTW_WARN("%s: unknown cut_ver=%d !!\n", __FUNCTION__, cut_drv); + + diff = cut_drv - A_CUT_VERSION; + cut_phydm += diff; + + return cut_phydm; +} + +static int _send_general_info_by_reg(struct dvobj_priv *d, + struct halmac_general_info *info) +{ + struct _ADAPTER *a; + struct hal_com_data *hal; + enum tag_HAL_Cut_Version_Definition cut_drv; + enum rf_type rftype; + enum odm_cut_version cut_phydm; + u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; + + + a = dvobj_get_primary_adapter(d); + hal = GET_HAL_DATA(a); + rftype = _rf_type_halmac2drv(info->rf_type); + cut_drv = GET_CVID_CUT_VERSION(hal->version_id); + cut_phydm = _cut_version_drv2phydm(cut_drv); + +#define CLASS_GENERAL_INFO_REG 0x02 +#define CMD_ID_GENERAL_INFO_REG 0x0C +#define GENERAL_INFO_REG_SET_CMD_ID(buf, v) SET_BITS_TO_LE_4BYTE(buf, 0, 5, v) +#define GENERAL_INFO_REG_SET_CLASS(buf, v) SET_BITS_TO_LE_4BYTE(buf, 5, 3, v) +#define GENERAL_INFO_REG_SET_RFE_TYPE(buf, v) SET_BITS_TO_LE_4BYTE(buf, 8, 8, v) +#define GENERAL_INFO_REG_SET_RF_TYPE(buf, v) SET_BITS_TO_LE_4BYTE(buf, 16, 8, v) +#define GENERAL_INFO_REG_SET_CUT_VERSION(buf, v) SET_BITS_TO_LE_4BYTE(buf, 24, 8, v) +#define GENERAL_INFO_REG_SET_RX_ANT_STATUS(buf, v) SET_BITS_TO_LE_1BYTE(buf+4, 0, 4, v) +#define GENERAL_INFO_REG_SET_TX_ANT_STATUS(buf, v) SET_BITS_TO_LE_1BYTE(buf+4, 4, 4, v) + + GENERAL_INFO_REG_SET_CMD_ID(h2c, CMD_ID_GENERAL_INFO_REG); + GENERAL_INFO_REG_SET_CLASS(h2c, CLASS_GENERAL_INFO_REG); + GENERAL_INFO_REG_SET_RFE_TYPE(h2c, info->rfe_type); + GENERAL_INFO_REG_SET_RF_TYPE(h2c, rftype); + GENERAL_INFO_REG_SET_CUT_VERSION(h2c, cut_phydm); + GENERAL_INFO_REG_SET_RX_ANT_STATUS(h2c, info->rx_ant_status); + GENERAL_INFO_REG_SET_TX_ANT_STATUS(h2c, info->tx_ant_status); + + return rtw_halmac_send_h2c(d, h2c); +} + static int _send_general_info(struct dvobj_priv *d) { - PADAPTER adapter; - PHAL_DATA_TYPE hal; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_GENERAL_INFO info; - HALMAC_RET_STATUS status; - u8 val8; + struct _ADAPTER *adapter; + struct hal_com_data *hal; + struct halmac_adapter *halmac; + struct halmac_api *api; + struct halmac_general_info info; + enum halmac_ret_status status; + enum rf_type rf = RF_1T1R; + enum bb_path txpath = BB_PATH_A; + enum bb_path rxpath = BB_PATH_A; + int err; adapter = dvobj_get_primary_adapter(d); @@ -1278,8 +2683,10 @@ static int _send_general_info(struct dvobj_priv *d) _rtw_memset(&info, 0, sizeof(info)); info.rfe_type = (u8)hal->rfe_type; - rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &val8); - info.rf_type = _rf_type_drv2halmac(val8); + rtw_hal_get_rf_path(d, &rf, &txpath, &rxpath); + info.rf_type = _rf_type_drv2halmac(rf); + info.tx_ant_status = (u8)txpath; + info.rx_ant_status = (u8)rxpath; status = api->halmac_send_general_info(halmac, &info); switch (status) { @@ -1293,9 +2700,232 @@ static int _send_general_info(struct dvobj_priv *d) return -1; } + err = _send_general_info_by_reg(d, &info); + if (err) { + RTW_ERR("%s: Fail to send general info by register!\n", + __FUNCTION__); + return -1; + } + + return 0; +} + +static int _cfg_drv_rsvd_pg_num(struct dvobj_priv *d) +{ + struct _ADAPTER *a; + struct hal_com_data *hal; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_drv_rsvd_pg_num rsvd_page_number; + enum halmac_ret_status status; + u8 drv_rsvd_num; + + + a = dvobj_get_primary_adapter(d); + hal = GET_HAL_DATA(a); + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + drv_rsvd_num = rtw_hal_get_rsvd_page_num(a); + rsvd_page_number = _rsvd_page_num_drv2halmac(drv_rsvd_num); + status = api->halmac_cfg_drv_rsvd_pg_num(halmac, rsvd_page_number); + if (status != HALMAC_RET_SUCCESS) + return -1; + hal->drv_rsvd_page_number = _rsvd_page_num_halmac2drv(rsvd_page_number); + + if (drv_rsvd_num != hal->drv_rsvd_page_number) + RTW_INFO("%s: request %d pages, but allocate %d pages\n", + __FUNCTION__, drv_rsvd_num, hal->drv_rsvd_page_number); + return 0; } +static void _debug_dlfw_fail(struct dvobj_priv *d) +{ + struct _ADAPTER *a; + u32 addr; + u32 v32, i, n; + u8 data[0x100] = {0}; + + + a = dvobj_get_primary_adapter(d); + + /* read 0x80[15:0], 0x10F8[31:0] once */ + addr = 0x80; + v32 = rtw_read16(a, addr); + RTW_PRINT("%s: 0x%X = 0x%04x\n", __FUNCTION__, addr, v32); + + addr = 0x10F8; + v32 = rtw_read32(a, addr); + RTW_PRINT("%s: 0x%X = 0x%08x\n", __FUNCTION__, addr, v32); + + /* read 0x10FC[31:0], 5 times */ + addr = 0x10FC; + n = 5; + for (i = 0; i < n; i++) { + v32 = rtw_read32(a, addr); + RTW_PRINT("%s: 0x%X = 0x%08x (%u/%u)\n", + __FUNCTION__, addr, v32, i, n); + } + + /* + * write 0x3A[7:0]=0x28 and 0xF6[7:0]=0x01 + * and then read 0xC0[31:0] 5 times + */ + addr = 0x3A; + v32 = 0x28; + rtw_write8(a, addr, (u8)v32); + v32 = rtw_read8(a, addr); + RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v32); + + addr = 0xF6; + v32 = 0x1; + rtw_write8(a, addr, (u8)v32); + v32 = rtw_read8(a, addr); + RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v32); + + addr = 0xC0; + n = 5; + for (i = 0; i < n; i++) { + v32 = rtw_read32(a, addr); + RTW_PRINT("%s: 0x%X = 0x%08x (%u/%u)\n", + __FUNCTION__, addr, v32, i, n); + } + + /* 0x00~0xFF, 0x1000~0x10FF */ + addr = 0; + n = 0x100; + for (i = 0; i < n; i+=4) + *(u32*)&data[i] = cpu_to_le32(rtw_read32(a, addr+i)); + for (i = 0; i < n; i++) { + if (i % 16 == 0) + RTW_PRINT("0x%04x\t", addr+i); + _RTW_PRINT("0x%02x", data[i]); + if (i % 16 == 15) + _RTW_PRINT("\n"); + else + _RTW_PRINT(" "); + } + + addr = 0x1000; + n = 0x100; + for (i = 0; i < n; i+=4) + *(u32*)&data[i] = cpu_to_le32(rtw_read32(a, addr+i)); + for (i = 0; i < n; i++) { + if (i % 16 == 0) + RTW_PRINT("0x%04x\t", addr+i); + _RTW_PRINT("0x%02x", data[i]); + if (i % 16 == 15) + _RTW_PRINT("\n"); + else + _RTW_PRINT(" "); + } + + /* read 0x80 after 10 secs */ + rtw_msleep_os(10000); + addr = 0x80; + v32 = rtw_read16(a, addr); + RTW_PRINT("%s: 0x%X = 0x%04x (after 10 secs)\n", + __FUNCTION__, addr, v32); +} + +static enum halmac_ret_status _enter_cpu_sleep_mode(struct dvobj_priv *d) +{ + struct hal_com_data *hal; + struct halmac_adapter *mac; + struct halmac_api *api; + + + hal = GET_HAL_DATA(dvobj_get_primary_adapter(d)); + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + +#ifdef CONFIG_RTL8822B + /* Support after firmware version 21 */ + if (hal->firmware_version < 21) + return HALMAC_RET_NOT_SUPPORT; +#elif defined(CONFIG_RTL8821C) + /* Support after firmware version 13.6 or 16 */ + if (hal->firmware_version == 13) { + if (hal->firmware_sub_version < 6) + return HALMAC_RET_NOT_SUPPORT; + } else if (hal->firmware_version < 16) { + return HALMAC_RET_NOT_SUPPORT; + } +#endif + + return api->halmac_enter_cpu_sleep_mode(mac); +} + +/* + * _cpu_sleep() - Let IC CPU enter sleep mode + * @d: struct dvobj_priv* + * @timeout: time limit of wait, unit is ms + * 0 for no limit + * + * Rteurn 0 for CPU in sleep mode, otherwise fail to enter sleep mode. + * Error codes definition are as follow: + * -1 HALMAC enter sleep return fail + * -2 HALMAC get CPU mode return fail + * -110 timeout + */ +static int _cpu_sleep(struct dvobj_priv *d, u32 timeout) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_wlcpu_mode mode = HALMAC_WLCPU_UNDEFINE; + systime start_t; + s32 period = 0; + u32 cnt = 0; + int err = 0; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + start_t = rtw_get_current_time(); + + status = _enter_cpu_sleep_mode(d); + if (status != HALMAC_RET_SUCCESS) { + if (status != HALMAC_RET_NOT_SUPPORT) + err = -1; + goto exit; + } + + do { + cnt++; + + mode = HALMAC_WLCPU_UNDEFINE; + status = api->halmac_get_cpu_mode(mac, &mode); + + period = rtw_get_passing_time_ms(start_t); + + if (status != HALMAC_RET_SUCCESS) { + err = -2; + break; + } + if (mode == HALMAC_WLCPU_SLEEP) + break; + if (period > timeout) { + err = -110; + break; + } + + rtw_msleep_os(1); + } while (1); + +exit: + if (err) + RTW_ERR("%s: Fail to enter sleep mode! (%d, %d)\n", + __FUNCTION__, status, mode); + + RTW_INFO("%s: Cost %dms to polling %u times. (err=%d)\n", + __FUNCTION__, period, cnt, err); + + return err; +} + /* * Description: * Downlaod Firmware Flow @@ -1314,17 +2944,17 @@ static int _send_general_info(struct dvobj_priv *d) */ static int download_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize, u8 re_dl) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - int err = 0; PHAL_DATA_TYPE hal; - HALMAC_FW_VERSION fw_vesion; + struct halmac_adapter *mac; + struct halmac_api *api; + struct halmac_fw_version fw_vesion; + enum halmac_ret_status status; + int err = 0; + hal = GET_HAL_DATA(dvobj_get_primary_adapter(d)); mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - hal = GET_HAL_DATA(dvobj_get_primary_adapter(d)); if ((!fw) || (!fwsize)) return -1; @@ -1333,71 +2963,100 @@ static int download_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize, u8 re_dl) /* ToDo */ /* 2. Driver Check Tx FIFO is empty */ - /* ToDo */ + err = rtw_halmac_txfifo_wait_empty(d, 2000); /* wait 2s */ + if (err) { + err = -1; + goto resume_tx; + } /* 3. Config MAX download size */ -#ifdef CONFIG_USB_HCI - /* for USB do not exceed MAX_CMDBUF_SZ */ - api->halmac_cfg_max_dl_size(mac, 0x1000); -#elif defined CONFIG_PCIE_HCI - /* required a even length from u32 */ - api->halmac_cfg_max_dl_size(mac, (MAX_CMDBUF_SZ - TXDESC_OFFSET) & 0xFFFFFFFE); -#endif + /* + * Already done in rtw_halmac_init_adapter() or + * somewhere calling rtw_halmac_set_max_dl_fw_size(). + */ + + if (re_dl) { + /* 4. Enter IC CPU sleep mode */ + err = _cpu_sleep(d, 2000); + if (err) { + RTW_ERR("%s: IC CPU fail to enter sleep mode!(%d)\n", + __FUNCTION__, err); + /* skip this error */ + err = 0; + } + } - /* 4. Download Firmware */ + /* 5. Download Firmware */ status = api->halmac_download_firmware(mac, fw, fwsize); - if (HALMAC_RET_SUCCESS != status) - return -1; + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: download firmware FAIL! status=0x%02x\n", + __FUNCTION__, status); + _debug_dlfw_fail(d); + err = -1; + goto resume_tx; + } + + /* 5.1. (Driver) Reset driver variables if needed */ + hal->LastHMEBoxNum = 0; + + /* 5.2. (Driver) Get FW version */ + status = api->halmac_get_fw_version(mac, &fw_vesion); + if (status == HALMAC_RET_SUCCESS) { + hal->firmware_version = fw_vesion.version; + hal->firmware_sub_version = fw_vesion.sub_version; + hal->firmware_size = fwsize; + } - /* 5. Driver resume TX if needed */ +resume_tx: + /* 6. Driver resume TX if needed */ /* ToDo */ + if (err) + goto exit; + if (re_dl) { - HALMAC_TRX_MODE mode; + enum halmac_trx_mode mode; + + /* 7. Change reserved page size */ + err = _cfg_drv_rsvd_pg_num(d); + if (err) + return -1; - /* 6. Init TRX Configuration */ + /* 8. Init TRX Configuration */ mode = _choose_trx_mode(d); status = api->halmac_init_trx_cfg(mac, mode); if (HALMAC_RET_SUCCESS != status) return -1; - /* 7. Config RX Aggregation */ + /* 9. Config RX Aggregation */ err = rtw_halmac_rx_agg_switch(d, _TRUE); if (err) return -1; - /* 8. Send General Info */ + /* 10. Send General Info */ err = _send_general_info(d); if (err) - return -1; - } - - /* 9. Reset driver variables if needed */ - hal->LastHMEBoxNum = 0; - - /* 10. Get FW version */ - status = api->halmac_get_fw_version(mac, &fw_vesion); - if (status == HALMAC_RET_SUCCESS) { - hal->firmware_version = fw_vesion.version; - hal->firmware_sub_version = fw_vesion.sub_version; - hal->firmware_size = fwsize; + return -1; } +exit: return err; } -static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d) +static int init_mac_flow(struct dvobj_priv *d) { PADAPTER p; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_WLAN_ADDR hwa; - HALMAC_TRX_MODE trx_mode; - HALMAC_RET_STATUS status; + struct hal_com_data *hal; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_drv_rsvd_pg_num rsvd_page_number; + union halmac_wlan_addr hwa; + enum halmac_trx_mode trx_mode; + enum halmac_ret_status status; + u8 drv_rsvd_num; u8 nettype; - int err; - PHAL_DATA_TYPE hal; - HALMAC_DRV_RSVD_PG_NUM rsvd_page_number = HALMAC_RSVD_PG_NUM16;/*HALMAC_RSVD_PG_NUM24/HALMAC_RSVD_PG_NUM32*/ + int err, err_ret = -1; + p = dvobj_get_primary_adapter(d); hal = GET_HAL_DATA(p); @@ -1405,18 +3064,21 @@ static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d) api = HALMAC_GET_API(halmac); #ifdef CONFIG_SUPPORT_TRX_SHARED - status = api->halmac_cfg_rx_fifo_expanding_mode(halmac, _rtw_get_trx_share_mode(p)); + status = api->halmac_cfg_rxff_expand_mode(halmac, + _rtw_get_trx_share_mode(p)); if (status != HALMAC_RET_SUCCESS) goto out; #endif -#ifdef CONFIG_PNO_SUPPORT - rsvd_page_number = HALMAC_RSVD_PG_NUM32; -#endif - status = api->halmac_cfg_drv_rsvd_pg_num(halmac, rsvd_page_number); +#if 0 /* It is not necessary to call this in normal driver */ + status = api->halmac_cfg_la_mode(halmac, HALMAC_LA_MODE_DISABLE); if (status != HALMAC_RET_SUCCESS) goto out; - hal->drv_rsvd_page_number = _get_drv_rsvd_page(rsvd_page_number); +#endif + + err = _cfg_drv_rsvd_pg_num(d); + if (err) + goto out; #ifdef CONFIG_USB_HCI status = api->halmac_set_bulkout_num(halmac, d->RtNumOutPipes); @@ -1445,8 +3107,29 @@ static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d) if (status != HALMAC_RET_SUCCESS) goto out; + err_ret = 0; out: - return status; + return err_ret; +} + +static int _drv_enable_trx(struct dvobj_priv *d) +{ + struct _ADAPTER *adapter; + u32 status; + + + adapter = dvobj_get_primary_adapter(d); + if (adapter->bup == _FALSE) { + status = rtw_start_drv_threads(adapter); + if (status == _FAIL) { + RTW_ERR("%s: Start threads Failed!\n", __FUNCTION__); + return -1; + } + } + + rtw_intf_start(adapter); + + return 0; } /* @@ -1459,10 +3142,10 @@ static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d) static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize) { PADAPTER adapter; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - u32 ok = _TRUE; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 ok; u8 fw_ok = _FALSE; int err, err_ret = -1; @@ -1495,8 +3178,13 @@ static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize) } /* InitMACFlow */ - status = init_mac_flow(d); - if (status != HALMAC_RET_SUCCESS) + err = init_mac_flow(d); + if (err) + goto out; + + /* Driver insert flow: Enable TR/RX */ + err = _drv_enable_trx(d); + if (err) goto out; /* halmac_send_general_info */ @@ -1565,11 +3253,16 @@ int rtw_halmac_init_hal_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize) int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath) { u8 *fw = NULL; - u32 fwmaxsize, size = 0; + u32 fwmaxsize = 0, size = 0; int err = 0; - fwmaxsize = FIRMWARE_MAX_SIZE; + err = rtw_halmac_get_fw_max_size(d, &fwmaxsize); + if (err) { + RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err); + return -1; + } + fw = rtw_zmalloc(fwmaxsize); if (!fw) return -1; @@ -1584,7 +3277,7 @@ int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath) exit: rtw_mfree(fw, fwmaxsize); - fw = NULL; + /*fw = NULL;*/ return err; } @@ -1592,9 +3285,9 @@ int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath) int rtw_halmac_deinit_hal(struct dvobj_priv *d) { PADAPTER adapter; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; int err = -1; @@ -1617,9 +3310,9 @@ int rtw_halmac_deinit_hal(struct dvobj_priv *d) int rtw_halmac_self_verify(struct dvobj_priv *d) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; int err = -1; @@ -1639,41 +3332,121 @@ int rtw_halmac_self_verify(struct dvobj_priv *d) return err; } -u8 rtw_halmac_txfifo_is_empty(struct dvobj_priv *d) +static u8 rtw_halmac_txfifo_is_empty(struct dvobj_priv *d) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - u8 rst = _TRUE; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 chk_num = 10; + u8 rst = _FALSE; + mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - if (HALMAC_RET_TXFIFO_NO_EMPTY == api->halmac_txfifo_is_empty(mac, 10)) - rst = _FALSE; + + status = api->halmac_txfifo_is_empty(mac, chk_num); + if (status == HALMAC_RET_SUCCESS) + rst = _TRUE; return rst; } -static HALMAC_DLFW_MEM _get_halmac_fw_mem(enum fw_mem mem) +/** + * rtw_halmac_txfifo_wait_empty() - Wait TX FIFO to be emtpy + * @d: struct dvobj_priv* + * @timeout: time limit of wait, unit is ms + * 0 for no limit + * + * Wait TX FIFO to be emtpy. + * + * Rteurn 0 for TX FIFO is empty, otherwise not empty. + */ +int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout) { - if (FW_EMEM == mem) - return HALMAC_DLFW_MEM_EMEM; - else if (FW_IMEM == mem) - return HALMAC_DLFW_MEM_UNDEFINE; - else if (FW_DMEM == mem) - return HALMAC_DLFW_MEM_UNDEFINE; - else - return HALMAC_DLFW_MEM_UNDEFINE; + struct _ADAPTER *a; + u8 empty = _FALSE; + u32 cnt = 0; + systime start_time = 0; + u32 pass_time; /* ms */ + + + a = dvobj_get_primary_adapter(d); + start_time = rtw_get_current_time(); + + do { + cnt++; + empty = rtw_halmac_txfifo_is_empty(d); + if (empty == _TRUE) + break; + + if (timeout) { + pass_time = rtw_get_passing_time_ms(start_time); + if (pass_time > timeout) + break; + } + if (RTW_CANNOT_IO(a)) { + RTW_WARN("%s: Interrupted by I/O forbiden!\n", __FUNCTION__); + break; + } + + rtw_msleep_os(2); + } while (1); + + if (empty == _FALSE) { +#ifdef CONFIG_RTW_DEBUG + u16 dbg_reg[] = {0x210, 0x230, 0x234, 0x238, 0x23C, 0x240, + 0x41A, 0x10FC, 0x10F8, 0x11F4, 0x11F8}; + u8 i; + u32 val; + + if (!RTW_CANNOT_IO(a)) { + for (i = 0; i < ARRAY_SIZE(dbg_reg); i++) { + val = rtw_read32(a, dbg_reg[i]); + RTW_ERR("REG_%X:0x%08x\n", dbg_reg[i], val); + } + } +#endif /* CONFIG_RTW_DEBUG */ + + RTW_ERR("%s: Fail to wait txfifo empty!(cnt=%d)\n", + __FUNCTION__, cnt); + return -1; + } + + return 0; +} + +static enum halmac_dlfw_mem _fw_mem_drv2halmac(enum fw_mem mem, u8 tx_stop) +{ + enum halmac_dlfw_mem mem_halmac = HALMAC_DLFW_MEM_UNDEFINE; + + + switch (mem) { + case FW_EMEM: + if (tx_stop == _FALSE) + mem_halmac = HALMAC_DLFW_MEM_EMEM_RSVD_PG; + else + mem_halmac = HALMAC_DLFW_MEM_EMEM; + break; + + case FW_IMEM: + case FW_DMEM: + mem_halmac = HALMAC_DLFW_MEM_UNDEFINE; + break; + } + + return mem_halmac; } -#define DBG_DL_FW_MEM int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_dlfw_mem dlfw_mem; + u8 tx_stop = _FALSE; + u32 chk_timeout = 2000; /* unit: ms */ int err = 0; - u8 chk_cnt = 0; - bool txfifo_empty = _FALSE; + mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); @@ -1681,46 +3454,37 @@ int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem me if ((!fw) || (!fwsize)) return -1; +#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX /* 1. Driver Stop Tx */ /* ToDo */ /* 2. Driver Check Tx FIFO is empty */ - do { - txfifo_empty = rtw_halmac_txfifo_is_empty(d); - chk_cnt++; - #ifdef DBG_DL_FW_MEM - RTW_INFO("polling txfifo empty chk_cnt:%d\n", chk_cnt); - #endif - rtw_msleep_os(2); - } while ((!txfifo_empty) && (chk_cnt < 100)); - - if (_FALSE == txfifo_empty) { - #ifdef DBG_DL_FW_MEM - { - PADAPTER adapter = dvobj_get_primary_adapter(d); - - RTW_ERR("%s => polling txfifo empty failed\n", __func__); - RTW_ERR("REG_210:0x%08x\n", rtw_read32(adapter, 0x210)); - RTW_ERR("REG_230:0x%08x\n", rtw_read32(adapter, 0x230)); - RTW_ERR("REG_234:0x%08x\n", rtw_read32(adapter, 0x234)); - RTW_ERR("REG_238:0x%08x\n", rtw_read32(adapter, 0x238)); - RTW_ERR("REG_23C:0x%08x\n", rtw_read32(adapter, 0x23C)); - RTW_ERR("REG_240:0x%08x\n", rtw_read32(adapter, 0x240)); - } - #endif - return -1; - } + err = rtw_halmac_txfifo_wait_empty(d, chk_timeout); + if (err) + tx_stop = _FALSE; + else + tx_stop = _TRUE; +#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */ /* 3. Download Firmware MEM */ - status = api->halmac_free_download_firmware(mac, _get_halmac_fw_mem(mem), fw, fwsize); - if (HALMAC_RET_SUCCESS != status) { - #ifdef DBG_DL_FW_MEM - RTW_ERR("%s => halmac_free_download_firmware failed\n", __func__); - #endif - return -1; + dlfw_mem = _fw_mem_drv2halmac(mem, tx_stop); + if (dlfw_mem == HALMAC_DLFW_MEM_UNDEFINE) { + err = -1; + goto resume_tx; + } + status = api->halmac_free_download_firmware(mac, dlfw_mem, fw, fwsize); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: halmac_free_download_firmware fail(err=0x%x)\n", + __FUNCTION__, status); + err = -1; + goto resume_tx; } + +resume_tx: +#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX /* 4. Driver resume TX if needed */ /* ToDo */ +#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */ return err; } @@ -1728,10 +3492,16 @@ int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem me int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem) { u8 *fw = NULL; - u32 fwmaxsize, size = 0; + u32 fwmaxsize = 0, size = 0; int err = 0; - fwmaxsize = FIRMWARE_MAX_SIZE; + + err = rtw_halmac_get_fw_max_size(d, &fwmaxsize); + if (err) { + RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err); + return -1; + } + fw = rtw_zmalloc(fwmaxsize); if (!fw) return -1; @@ -1743,7 +3513,7 @@ int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem err = -1; rtw_mfree(fw, fwmaxsize); - fw = NULL; + /*fw = NULL;*/ return err; } @@ -1756,8 +3526,8 @@ int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize) { PADAPTER adapter; - HALMAC_RET_STATUS status; - u32 ok = _TRUE; + enum halmac_ret_status status; + u32 ok; int err, err_ret = -1; @@ -1782,8 +3552,8 @@ int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize) goto out; } - status = init_mac_flow(d); - if (status != HALMAC_RET_SUCCESS) + err = init_mac_flow(d); + if (err) goto out; err = _send_general_info(d); @@ -1799,11 +3569,16 @@ int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize) int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath) { u8 *fw = NULL; - u32 fwmaxsize, size = 0; + u32 fwmaxsize = 0, size = 0; int err = 0; - fwmaxsize = FIRMWARE_MAX_SIZE; + err = rtw_halmac_get_fw_max_size(d, &fwmaxsize); + if (err) { + RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err); + return -1; + } + fw = rtw_zmalloc(fwmaxsize); if (!fw) return -1; @@ -1815,7 +3590,7 @@ int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath) err = -1; rtw_mfree(fw, fwmaxsize); - fw = NULL; + /*fw = NULL;*/ return err; } @@ -1834,9 +3609,9 @@ int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath) int rtw_halmac_phy_power_switch(struct dvobj_priv *d, u8 enable) { PADAPTER adapter; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; adapter = dvobj_get_primary_adapter(d); @@ -1879,6 +3654,10 @@ static u8 _is_fw_read_cmd_down(PADAPTER adapter, u8 msgbox_num) * * Send H2C to firmware by message box register(0x1D0~0x1D3 & 0x1F0~0x1F3). * + * Assume firmware be ready to accept H2C here, please check + * (hal->bFWReady == _TRUE) before call this function or make sure firmware is + * ready. + * * Return: 0 if process OK, otherwise fail to send this H2C. */ int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c) @@ -1892,10 +3671,6 @@ int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c) u32 h2c_cmd_ex = 0; int err = -1; - if (hal->bFWReady == _FALSE) { - RTW_WARN("%s: return H2C cmd because fw is not ready\n", __FUNCTION__); - return err; - } if (!h2c) { RTW_WARN("%s: pbuf is NULL\n", __FUNCTION__); @@ -1914,6 +3689,10 @@ int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c) if (!_is_fw_read_cmd_down(adapter, h2c_box_num)) { RTW_WARN(" fw read cmd failed...\n"); +#ifdef DBG_CONFIG_ERROR_DETECT + hal->srestpriv.self_dect_fw = _TRUE; + hal->srestpriv.self_dect_fw_cnt++; +#endif /* DBG_CONFIG_ERROR_DETECT */ goto exit; } @@ -1958,9 +3737,9 @@ int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c) */ int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; mac = dvobj_to_halmac(d); @@ -1975,9 +3754,9 @@ int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size) int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 val; @@ -1994,9 +3773,9 @@ int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size) int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 val; @@ -2013,10 +3792,10 @@ int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size) int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - HALMAC_FEATURE_ID id; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_feature_id id; int ret; @@ -2043,9 +3822,9 @@ int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) int rtw_halmac_read_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u8 v; u32 i; u8 *efuse = NULL; @@ -2086,9 +3865,9 @@ int rtw_halmac_read_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 i; @@ -2109,9 +3888,9 @@ int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *d, u32 *size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 val; @@ -2126,12 +3905,12 @@ int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *d, u32 *size) return 0; } -int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) +int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - HALMAC_FEATURE_ID id; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_feature_id id; int ret; @@ -2153,23 +3932,36 @@ int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) if (ret) return -1; + if (maskmap && masksize) { + struct halmac_pg_efuse_info pginfo; + + pginfo.efuse_map = map; + pginfo.efuse_map_size = size; + pginfo.efuse_mask = maskmap; + pginfo.efuse_mask_size = masksize; + + status = api->halmac_mask_logical_efuse(mac, &pginfo); + if (status != HALMAC_RET_SUCCESS) + RTW_WARN("%s: mask logical efuse FAIL!\n", __FUNCTION__); + } + return 0; } int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_PG_EFUSE_INFO pginfo; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + struct halmac_pg_efuse_info pginfo; + enum halmac_ret_status status; mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - pginfo.pEfuse_map = map; + pginfo.efuse_map = map; pginfo.efuse_map_size = size; - pginfo.pEfuse_mask = maskmap; + pginfo.efuse_mask = maskmap; pginfo.efuse_mask_size = masksize; status = api->halmac_pg_efuse_by_map(mac, &pginfo, HALMAC_EFUSE_R_AUTO); @@ -2181,9 +3973,9 @@ int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, int rtw_halmac_read_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u8 v; u32 i; @@ -2203,9 +3995,9 @@ int rtw_halmac_read_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 int rtw_halmac_write_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 i; @@ -2223,214 +4015,51 @@ int rtw_halmac_write_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 i; u8 bank = 1; - mac = dvobj_to_halmac(d); - api = HALMAC_GET_API(mac); - - for (i = 0; i < cnt; i++) { - status = api->halmac_write_efuse_bt(mac, offset + i, data[i], bank); - if (HALMAC_RET_SUCCESS != status) { - printk("%s: halmac_write_efuse_bt status = %d\n", __FUNCTION__, status); - return -1; - } - } - printk("%s: halmac_write_efuse_bt status = HALMAC_RET_SUCCESS %d\n", __FUNCTION__, status); - return 0; -} - - -int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) -{ - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - HALMAC_FEATURE_ID id; - int ret; - int bank = 1; - - mac = dvobj_to_halmac(d); - api = HALMAC_GET_API(mac); - - status = api->halmac_dump_efuse_map_bt(mac, bank, size, map); - if (HALMAC_RET_SUCCESS != status) { - printk("%s: halmac_dump_efuse_map_bt fail!\n", __FUNCTION__); - return -1; - } - - printk("%s: OK!\n", __FUNCTION__); - - return 0; -} - -static inline u8 _hw_port_drv2halmac(enum _hw_port hwport) -{ - u8 port = 0; - - - switch (hwport) { - case HW_PORT0: - port = 0; - break; - case HW_PORT1: - port = 1; - break; - case HW_PORT2: - port = 2; - break; - case HW_PORT3: - port = 3; - break; - case HW_PORT4: - port = 4; - break; - default: - port = hwport; - break; - } - - return port; -} - -int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) -{ - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - u8 port; - HALMAC_WLAN_ADDR hwa; - HALMAC_RET_STATUS status; - int err = -1; - - - halmac = dvobj_to_halmac(d); - api = HALMAC_GET_API(halmac); - - port = _hw_port_drv2halmac(hwport); - _rtw_memset(&hwa, 0, sizeof(hwa)); - _rtw_memcpy(hwa.Address, addr, 6); - - status = api->halmac_cfg_mac_addr(halmac, port, &hwa); - if (status != HALMAC_RET_SUCCESS) - goto out; - - err = 0; -out: - return err; -} - -int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) -{ - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - u8 port; - HALMAC_WLAN_ADDR hwa; - HALMAC_RET_STATUS status; - int err = -1; - - halmac = dvobj_to_halmac(d); - api = HALMAC_GET_API(halmac); - port = _hw_port_drv2halmac(hwport); - - _rtw_memset(&hwa, 0, sizeof(HALMAC_WLAN_ADDR)); - _rtw_memcpy(hwa.Address, addr, 6); - status = api->halmac_cfg_bssid(halmac, port, &hwa); - if (status != HALMAC_RET_SUCCESS) - goto out; - - err = 0; -out: - return err; -} - -int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw) -{ - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - - - mac = dvobj_to_halmac(d); - api = HALMAC_GET_API(mac); - - status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw); - if (HALMAC_RET_SUCCESS != status) - return -1; - - return 0; -} - -/** - * rtw_halmac_set_edca() - config edca parameter - * @d: struct dvobj_priv* - * @queue: XMIT_[VO/VI/BE/BK]_QUEUE - * @aifs: Arbitration inter-frame space(AIFS) - * @cw: Contention window(CW) - * @txop: MAX Transmit Opportunity(TXOP) - * - * Return: 0 if process OK, otherwise -1. - */ -int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop) -{ - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_ACQ_ID ac; - HALMAC_EDCA_PARA edca; - HALMAC_RET_STATUS status; - mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - switch (queue) { - case XMIT_VO_QUEUE: - ac = HALMAC_ACQ_ID_VO; - break; - case XMIT_VI_QUEUE: - ac = HALMAC_ACQ_ID_VI; - break; - case XMIT_BE_QUEUE: - ac = HALMAC_ACQ_ID_BE; - break; - case XMIT_BK_QUEUE: - ac = HALMAC_ACQ_ID_BK; - break; - default: - return -1; - } - - edca.aifs = aifs; - edca.cw = cw; - edca.txop_limit = txop; - - status = api->halmac_cfg_edca_para(mac, ac, &edca); - if (status != HALMAC_RET_SUCCESS) - return -1; - + for (i = 0; i < cnt; i++) { + status = api->halmac_write_efuse_bt(mac, offset + i, data[i], bank); + if (HALMAC_RET_SUCCESS != status) { + printk("%s: halmac_write_efuse_bt status = %d\n", __FUNCTION__, status); + return -1; + } + } + printk("%s: halmac_write_efuse_bt status = HALMAC_RET_SUCCESS %d\n", __FUNCTION__, status); return 0; } -int rtw_halmac_get_hw_value(struct dvobj_priv *d, HALMAC_HW_ID hw_id, VOID *pvalue) + +int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + int bank = 1; mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - status = api->halmac_get_hw_value(mac, hw_id, pvalue); - if (HALMAC_RET_SUCCESS != status) + status = api->halmac_dump_efuse_map_bt(mac, bank, size, map); + if (HALMAC_RET_SUCCESS != status) { + printk("%s: halmac_dump_efuse_map_bt fail!\n", __FUNCTION__); return -1; + } + + printk("%s: OK!\n", __FUNCTION__); return 0; } -static enum _HAL_FIFO_SEL _fifo_sel_drv2halmac(u8 fifo_sel) +static enum hal_fifo_sel _fifo_sel_drv2halmac(u8 fifo_sel) { switch (fifo_sel) { case 0: @@ -2453,15 +4082,15 @@ static enum _HAL_FIFO_SEL _fifo_sel_drv2halmac(u8 fifo_sel) /*#define CONFIG_HALMAC_FIFO_DUMP*/ int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum hal_fifo_sel halmac_fifo_sel; + enum halmac_ret_status status; u8 *pfifo_map = NULL; u32 fifo_size = 0; s8 ret = 0;/* 0:success, -1:error */ u8 mem_created = _FALSE; - HAL_FIFO_SEL halmac_fifo_sel; mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); @@ -2509,15 +4138,36 @@ int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, return ret; } +/* + * rtw_halmac_rx_agg_switch() - Switch RX aggregation function and setting + * @d struct dvobj_priv * + * @enable 0/1 for disable/enable RX aggregation function + * + * This function could help to on/off bus RX aggregation function, and is only + * useful for SDIO and USB interface. Although only "enable" flag is brough in, + * some setting would be taken from other places, and they are from: + * [DMA aggregation] + * struct hal_com_data.rxagg_dma_size + * struct hal_com_data.rxagg_dma_timeout + * [USB aggregation] (only use for USB interface) + * struct hal_com_data.rxagg_usb_size + * struct hal_com_data.rxagg_usb_timeout + * If above values of size and timeout are both 0 means driver would not + * control the threshold setting and leave it to HALMAC handle. + * + * From HALMAC V1_04_04, driver force the size threshold be hard limit, and the + * rx size can not exceed the setting. + * + * Return 0 for success, otherwise fail. + */ int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable) { - PADAPTER adapter; - PHAL_DATA_TYPE hal; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RXAGG_CFG rxaggcfg; - HALMAC_RET_STATUS status; - int err = -1; + struct _ADAPTER *adapter; + struct hal_com_data *hal; + struct halmac_adapter *halmac; + struct halmac_api *api; + struct halmac_rxagg_cfg rxaggcfg; + enum halmac_ret_status status; adapter = dvobj_get_primary_adapter(d); @@ -2525,12 +4175,29 @@ int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable) halmac = dvobj_to_halmac(d); api = HALMAC_GET_API(halmac); _rtw_memset((void *)&rxaggcfg, 0, sizeof(rxaggcfg)); - + rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE; + /* + * Always enable size limit to avoid rx size exceed + * driver defined size. + */ + rxaggcfg.threshold.size_limit_en = 1; + +#ifdef RTW_RX_AGGREGATION if (_TRUE == enable) { #ifdef CONFIG_SDIO_HCI rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA; rxaggcfg.threshold.drv_define = 0; -#elif defined(CONFIG_USB_HCI) && defined(CONFIG_USB_RX_AGGREGATION) + if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) { + rxaggcfg.threshold.drv_define = 1; + rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout; + rxaggcfg.threshold.size = hal->rxagg_dma_size; + RTW_INFO("%s: RX aggregation threshold: " + "timeout=%u size=%u\n", + __FUNCTION__, + hal->rxagg_dma_timeout, + hal->rxagg_dma_size); + } +#elif defined(CONFIG_USB_HCI) switch (hal->rxagg_mode) { case RX_AGG_DISABLE: rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE; @@ -2556,119 +4223,21 @@ int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable) break; } #endif /* CONFIG_USB_HCI */ - } else - rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE; + } +#endif /* RTW_RX_AGGREGATION */ status = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg); - if (status != HALMAC_RET_SUCCESS) - goto out; - - err = 0; -out: - return err; -} - -/* - * Description: - * Get RX driver info size. RX driver info is a small memory space between - * scriptor and RX payload. - * - * +-------------------------+ - * | RX descriptor | - * | usually 24 bytes | - * +-------------------------+ - * | RX driver info | - * | depends on driver cfg | - * +-------------------------+ - * | RX paylad | - * | | - * +-------------------------+ - * - * Parameter: - * d pointer to struct dvobj_priv of driver - * sz rx driver info size in bytes. - * - * Rteurn: - * 0 Success - * other Fail - */ -int rtw_halmac_get_drv_info_sz(struct dvobj_priv *d, u8 *sz) -{ - HALMAC_RET_STATUS status; - PHALMAC_ADAPTER halmac = dvobj_to_halmac(d); - PHALMAC_API api = HALMAC_GET_API(halmac); - u8 dw = 0; - - status = api->halmac_get_hw_value(halmac, HALMAC_HW_DRV_INFO_SIZE, &dw); - if (status != HALMAC_RET_SUCCESS) - return -1; - - *sz = dw * 8; - return 0; -} - -int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg) -{ - HALMAC_RET_STATUS status; - PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj); - PHALMAC_API api = HALMAC_GET_API(halmac); - - status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, drv_pg); - if (status != HALMAC_RET_SUCCESS) - return -1; - - return 0; -} - -int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size) -{ - enum _HALMAC_RET_STATUS status; - struct _HALMAC_ADAPTER *halmac; - struct _HALMAC_API *api; - u8 val; - - - if (!size) - return -1; - - halmac = dvobj_to_halmac(d); - api = HALMAC_GET_API(halmac); - - status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_OQT_SIZE, &val); - if (status != HALMAC_RET_SUCCESS) - return -1; - - *size = val; - return 0; -} - -int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num) -{ - enum _HALMAC_RET_STATUS status; - struct _HALMAC_ADAPTER *halmac; - struct _HALMAC_API *api; - u8 val; - - - if (!num) - return -1; - - halmac = dvobj_to_halmac(d); - api = HALMAC_GET_API(halmac); - - status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_QUEUE_NUM, &val); if (status != HALMAC_RET_SUCCESS) return -1; - *num = val; return 0; } int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size) { - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj); - PHALMAC_API api = HALMAC_GET_API(halmac); + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_adapter *halmac = dvobj_to_halmac(dvobj); + struct halmac_api *api = HALMAC_GET_API(halmac); status = api->halmac_dl_drv_rsvd_page(halmac, pg_offset, pbuf, size); if (status != HALMAC_RET_SUCCESS) @@ -2688,9 +4257,9 @@ int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pb */ int rtw_halmac_fill_hal_spec(struct dvobj_priv *dvobj, struct hal_spec_t *spec) { - HALMAC_RET_STATUS status; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; + enum halmac_ret_status status; + struct halmac_adapter *halmac; + struct halmac_api *api; u8 cam = 0; /* Security Cam Entry Number */ @@ -2708,12 +4277,12 @@ int rtw_halmac_fill_hal_spec(struct dvobj_priv *dvobj, struct hal_spec_t *spec) return 0; } -int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para) +int rtw_halmac_p2pps(struct dvobj_priv *dvobj, struct hal_p2p_ps_para *pp2p_ps_para) { - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj); - PHALMAC_API api = HALMAC_GET_API(halmac); - HALMAC_P2PPS halmac_p2p_ps; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_adapter *halmac = dvobj_to_halmac(dvobj); + struct halmac_api *api = HALMAC_GET_API(halmac); + struct halmac_p2pps halmac_p2p_ps; (&halmac_p2p_ps)->offload_en = pp2p_ps_para->offload_en; (&halmac_p2p_ps)->role = pp2p_ps_para->role; @@ -2751,11 +4320,11 @@ int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para) */ int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - HALMAC_FEATURE_ID id; - HALMAC_IQK_PARA para; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_feature_id id; + struct halmac_iqk_para para; int ret; u8 retry = 3; u8 delay = 1; /* ms */ @@ -2794,6 +4363,279 @@ int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment) return 0; } +static inline u32 _phy_parameter_val_drv2halmac(u32 val, u8 msk_en, u32 msk) +{ + if (!msk_en) + return val; + + return (val << bitshift(msk)); +} + +static int _phy_parameter_drv2halmac(struct rtw_phy_parameter *para, struct halmac_phy_parameter_info *info) +{ + if (!para || !info) + return -1; + + _rtw_memset(info, 0, sizeof(*info)); + + switch (para->cmd) { + case 0: + /* MAC register */ + switch (para->data.mac.size) { + case 1: + info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W8; + break; + case 2: + info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W16; + break; + default: + info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W32; + break; + } + info->content.MAC_REG_W.value = _phy_parameter_val_drv2halmac( + para->data.mac.value, + para->data.mac.msk_en, + para->data.mac.msk); + info->content.MAC_REG_W.msk = para->data.mac.msk; + info->content.MAC_REG_W.offset = para->data.mac.offset; + info->content.MAC_REG_W.msk_en = para->data.mac.msk_en; + break; + + case 1: + /* BB register */ + switch (para->data.bb.size) { + case 1: + info->cmd_id = HALMAC_PARAMETER_CMD_BB_W8; + break; + case 2: + info->cmd_id = HALMAC_PARAMETER_CMD_BB_W16; + break; + default: + info->cmd_id = HALMAC_PARAMETER_CMD_BB_W32; + break; + } + info->content.BB_REG_W.value = _phy_parameter_val_drv2halmac( + para->data.bb.value, + para->data.bb.msk_en, + para->data.bb.msk); + info->content.BB_REG_W.msk = para->data.bb.msk; + info->content.BB_REG_W.offset = para->data.bb.offset; + info->content.BB_REG_W.msk_en = para->data.bb.msk_en; + break; + + case 2: + /* RF register */ + info->cmd_id = HALMAC_PARAMETER_CMD_RF_W; + info->content.RF_REG_W.value = _phy_parameter_val_drv2halmac( + para->data.rf.value, + para->data.rf.msk_en, + para->data.rf.msk); + info->content.RF_REG_W.msk = para->data.rf.msk; + info->content.RF_REG_W.offset = para->data.rf.offset; + info->content.RF_REG_W.msk_en = para->data.rf.msk_en; + info->content.RF_REG_W.rf_path = para->data.rf.path; + break; + + case 3: + /* Delay register */ + if (para->data.delay.unit == 0) + info->cmd_id = HALMAC_PARAMETER_CMD_DELAY_US; + else + info->cmd_id = HALMAC_PARAMETER_CMD_DELAY_MS; + info->content.DELAY_TIME.delay_time = para->data.delay.value; + break; + + case 0xFF: + /* Latest(End) command */ + info->cmd_id = HALMAC_PARAMETER_CMD_END; + break; + + default: + return -1; + } + + return 0; +} + +/** + * rtw_halmac_cfg_phy_para() - Register(Phy parameter) configuration + * @d: struct dvobj_priv* + * @para: phy parameter + * + * Configure registers by firmware using H2C/C2H mechanism. + * The latest command should be para->cmd==0xFF(End command) to finish all + * processes. + * + * Return: 0 for OK, otherwise fail. + */ +int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_feature_id id; + struct halmac_phy_parameter_info info; + u8 full_fifo; + int err, ret; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + id = HALMAC_FEATURE_CFG_PARA; + full_fifo = 1; /* ToDo: How to deciede? */ + ret = 0; + + err = _phy_parameter_drv2halmac(para, &info); + if (err) + return -1; + + err = init_halmac_event(d, id, NULL, 0); + if (err) + return -1; + + status = api->halmac_cfg_parameter(mac, &info, full_fifo); + if (info.cmd_id == HALMAC_PARAMETER_CMD_END) { + if (status == HALMAC_RET_SUCCESS) { + err = wait_halmac_event(d, id); + if (err) + ret = -1; + } else { + free_halmac_event(d, id); + ret = -1; + RTW_ERR("%s: Fail to send END of cfg parameter, status is 0x%x!\n", __FUNCTION__, status); + } + } else { + if (status == HALMAC_RET_PARA_SENDING) { + err = wait_halmac_event(d, id); + if (err) + ret = -1; + } else { + free_halmac_event(d, id); + if (status != HALMAC_RET_SUCCESS) { + ret = -1; + RTW_ERR("%s: Fail to cfg parameter, status is 0x%x!\n", __FUNCTION__, status); + } + } + } + + return ret; +} + +static enum halmac_wlled_mode _led_mode_drv2halmac(u8 drv_mode) +{ + enum halmac_wlled_mode halmac_mode; + + + switch (drv_mode) { + case 1: + halmac_mode = HALMAC_WLLED_MODE_TX; + break; + case 2: + halmac_mode = HALMAC_WLLED_MODE_RX; + break; + case 3: + halmac_mode = HALMAC_WLLED_MODE_SW_CTRL; + break; + case 0: + default: + halmac_mode = HALMAC_WLLED_MODE_TRX; + break; + } + + return halmac_mode; +} + +/** + * rtw_halmac_led_cfg() - Configure Hardware LED Mode + * @d: struct dvobj_priv* + * @enable: enable or disable LED function + * 0: disable + * 1: enable + * @mode: WLan LED mode (valid when enable==1) + * 0: Blink when TX(transmit packet) and RX(receive packet) + * 1: Blink when TX only + * 2: Blink when RX only + * 3: Software control + * + * Configure hardware WLan LED mode. + * If want to change LED mode after enabled, need to disable LED first and + * enable again to set new mode. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_wlled_mode led_mode; + enum halmac_ret_status status; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + if (enable) { + status = api->halmac_pinmux_set_func(halmac, + HALMAC_GPIO_FUNC_WL_LED); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: pinmux set fail!(0x%x)\n", + __FUNCTION__, status); + return -1; + } + + led_mode = _led_mode_drv2halmac(mode); + status = api->halmac_pinmux_wl_led_mode(halmac, led_mode); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: mode set fail!(0x%x)\n", + __FUNCTION__, status); + return -1; + } + } else { + /* Change LED to software control and turn off */ + api->halmac_pinmux_wl_led_mode(halmac, + HALMAC_WLLED_MODE_SW_CTRL); + api->halmac_pinmux_wl_led_sw_ctrl(halmac, 0); + + status = api->halmac_pinmux_free_func(halmac, + HALMAC_GPIO_FUNC_WL_LED); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: pinmux free fail!(0x%x)\n", + __FUNCTION__, status); + return -1; + } + } + + return 0; +} + +/** + * rtw_halmac_led_switch() - Turn Hardware LED on/off + * @d: struct dvobj_priv* + * @on: LED light or not + * 0: Off + * 1: On(Light) + * + * Turn Hardware WLan LED On/Off. + * Before use this function, user should call rtw_halmac_led_ctrl() to switch + * mode to "software control(3)" first, otherwise control would fail. + * The interval between on and off must be longer than 1 ms, or the LED would + * keep light or dark only. + * Ex. Turn off LED at first, turn on after 0.5ms and turn off again after + * 0.5ms. The LED during this flow will only keep dark, and miss the turn on + * operation between two turn off operations. + */ +void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + api->halmac_pinmux_wl_led_sw_ctrl(halmac, on); +} + #ifdef CONFIG_SDIO_HCI /* @@ -2811,12 +4653,12 @@ int rtw_halmac_query_tx_page_num(struct dvobj_priv *d) { PADAPTER adapter; struct halmacpriv *hmpriv; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RQPN_MAP rqpn; - HALMAC_DMA_MAPPING dmaqueue; - HALMAC_TXFF_ALLOCATION fifosize; - HALMAC_RET_STATUS status; + struct halmac_adapter *halmac; + struct halmac_api *api; + struct halmac_rqpn_map rqpn; + enum halmac_dma_mapping dmaqueue; + struct halmac_txff_allocation fifosize; + enum halmac_ret_status status; u8 i; @@ -2915,9 +4757,9 @@ int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *d, u8 queue, u32 *page) */ u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *d, u8 *desc, u32 size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 addr; @@ -2933,9 +4775,9 @@ u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *d, u8 *desc, u32 size) int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *d, u8 *buf, u32 size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; mac = dvobj_to_halmac(d); @@ -2964,9 +4806,9 @@ u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *d, u8 *seq) #ifdef CONFIG_USB_HCI u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *d, u8 *buf, u32 size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u8 bulkout_id; @@ -2980,9 +4822,38 @@ u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *d, u8 *buf, u32 size) return bulkout_id; } -static inline HALMAC_USB_MODE _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode) +/** + * rtw_halmac_usb_get_txagg_desc_num() - MAX descriptor number in one bulk for TX + * @d: struct dvobj_priv* + * @size: TX FIFO size, unit is byte. + * + * Get MAX descriptor number in one bulk out from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u8 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_USB_TXAGG_DESC_NUM, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *num = val; + + return 0; +} + +static inline enum halmac_usb_mode _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode) { - HALMAC_USB_MODE halmac_usb_mode = HALMAC_USB_MODE_U2; + enum halmac_usb_mode halmac_usb_mode = HALMAC_USB_MODE_U2; switch (usb_mode) { case RTW_USB_SPEED_2: @@ -3001,11 +4872,11 @@ static inline HALMAC_USB_MODE _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode) u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; PADAPTER adapter; - HALMAC_USB_MODE halmac_usb_mode; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_usb_mode halmac_usb_mode; adapter = dvobj_get_primary_adapter(d); mac = dvobj_to_halmac(d); @@ -3023,22 +4894,23 @@ u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode) #ifdef CONFIG_BEAMFORMING #ifdef RTW_BEAMFORMING_VERSION_2 int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para, - u16 my_aid, HALMAC_CSI_SEG_LEN sel, u8 *addr) + u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - HALMAC_MU_BFER_INIT_PARA param; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + struct halmac_mu_bfer_init_para param; + mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - memset(¶m, 0, sizeof(param)); + _rtw_memset(¶m, 0, sizeof(param)); param.paid = paid; param.csi_para = csi_para; param.my_aid = my_aid; param.csi_length_sel = sel; - memcpy(param.bfer_address.Address, addr, 6); + _rtw_memcpy(param.bfer_address.addr, addr, 6); status = api->halmac_mu_bfer_entry_init(mac, ¶m); if (status != HALMAC_RET_SUCCESS) @@ -3049,9 +4921,10 @@ int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para, int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); @@ -3065,11 +4938,12 @@ int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d) int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, - HALMAC_SND_ROLE role, HALMAC_DATA_RATE rate) + enum halmac_snd_role role, enum halmac_data_rate rate) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); @@ -3082,11 +4956,12 @@ int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, } int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, - HALMAC_SND_ROLE role) + enum halmac_snd_role role) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); @@ -3102,9 +4977,10 @@ int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate, u8 fixrate_en, u8 *new_rate) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); @@ -3117,32 +4993,33 @@ int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, return 0; } -int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, HALMAC_SND_ROLE role, +int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role, u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en, u32 *given_gid_tab, u32 *given_user_pos) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - HALMAC_CFG_MUMIMO_PARA param; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + struct halmac_cfg_mumimo_para param; + mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - memset(¶m, 0, sizeof(param)); + _rtw_memset(¶m, 0, sizeof(param)); param.role = role; param.grouping_bitmap = grouping_bitmap; param.mu_tx_en = mu_tx_en; if (sounding_sts) - memcpy(param.sounding_sts, sounding_sts, 6); + _rtw_memcpy(param.sounding_sts, sounding_sts, 6); if (given_gid_tab) - memcpy(param.given_gid_tab, given_gid_tab, 8); + _rtw_memcpy(param.given_gid_tab, given_gid_tab, 8); if (given_user_pos) - memcpy(param.given_user_pos, given_user_pos, 16); + _rtw_memcpy(param.given_user_pos, given_user_pos, 16); status = api->halmac_cfg_mumimo(mac, ¶m); if (status != HALMAC_RET_SUCCESS) diff --git a/hal/hal_halmac.h b/hal/hal_halmac.h index 5b006f7..4555b18 100644 --- a/hal/hal_halmac.h +++ b/hal/hal_halmac.h @@ -17,14 +17,14 @@ #include /* adapter_to_dvobj(), struct intf_hdl and etc. */ #include /* struct hal_spec_t */ -#include "halmac/halmac_api.h" /* PHALMAC_ADAPTER and etc. */ +#include "halmac/halmac_api.h" /* struct halmac_adapter* and etc. */ /* HALMAC Definition for Driver */ -#define RTW_HALMAC_H2C_MAX_SIZE HALMAC_H2C_CMD_ORIGINAL_SIZE_88XX +#define RTW_HALMAC_H2C_MAX_SIZE 8 #define RTW_HALMAC_BA_SSN_RPT_SIZE 4 #define dvobj_set_halmac(d, mac) ((d)->halmac = (mac)) -#define dvobj_to_halmac(d) ((PHALMAC_ADAPTER)((d)->halmac)) +#define dvobj_to_halmac(d) ((struct halmac_adapter *)((d)->halmac)) #define adapter_to_halmac(p) dvobj_to_halmac(adapter_to_dvobj(p)) /* for H2C cmd */ @@ -37,7 +37,67 @@ typedef enum _RTW_HALMAC_MODE { RTW_HALMAC_MODE_WIFI_TEST, } RTW_HALMAC_MODE; -extern HALMAC_PLATFORM_API rtw_halmac_platform_api; +union rtw_phy_para_data { + struct _mac { + u32 value; /* value to be set in bit mask(msk) */ + u32 msk; /* bit mask */ + u16 offset; /* address */ + u8 msk_en; /* 0/1 for msk invalid/valid */ + u8 size; /* Unit is bytes, and value should be 1/2/4 */ + } mac; + struct _bb { + u32 value; + u32 msk; + u16 offset; + u8 msk_en; + u8 size; + } bb; + struct _rf { + u32 value; + u32 msk; + u8 offset; + u8 msk_en; + /* + * 0: path A + * 1: path B + * 2: path C + * 3: path D + */ + u8 path; + } rf; + struct _delay { + /* + * 0: microsecond (us) + * 1: millisecond (ms) + */ + u8 unit; + u16 value; + } delay; +}; + +struct rtw_phy_parameter { + /* + * 0: MAC register + * 1: BB register + * 2: RF register + * 3: Delay + * 0xFF: Latest(End) command + */ + u8 cmd; + union rtw_phy_para_data data; +}; + +struct rtw_halmac_bcn_ctrl { + u8 rx_bssid_fit:1; /* 0:HW handle beacon, 1:ignore */ + u8 txbcn_rpt:1; /* Enable TXBCN report in ad hoc and AP mode */ + u8 tsf_update:1; /* Update TSF when beacon or probe response */ + u8 enable_bcn:1; /* Enable beacon related functions */ + u8 rxbcn_rpt:1; /* Enable RXBCNOK report */ + u8 p2p_ctwin:1; /* Enable P2P CTN WINDOWS function */ + u8 p2p_bcn_area:1; /* Enable P2P BCN area on function */ +}; + +extern struct halmac_platform_api rtw_halmac_platform_api; /* HALMAC API for Driver(HAL) */ u8 rtw_halmac_read8(struct intf_hdl *, u32 addr); @@ -48,15 +108,52 @@ void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem) u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr); u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr); u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr); -#endif +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ int rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value); int rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value); int rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value); -void rtw_dump_halmac_info(void *sel); +/* Software Information */ +void rtw_halmac_get_version(char *str, u32 len); -int rtw_halmac_init_adapter(struct dvobj_priv *, PHALMAC_PLATFORM_API); +/* Software Initialization */ +int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api); int rtw_halmac_deinit_adapter(struct dvobj_priv *); + +/* Get operations */ +int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue); +int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size); +int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size); +int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy); +int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size); +int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size); +int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size); +int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *, u8 *sz); +int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size); +int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size); +int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size); +int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size); +int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num); +int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); +int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type); +int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl); +/*int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason);*/ + +/* Set operations */ +int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info); +int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size); +int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); +int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); +int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); +int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type); +int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport); +int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, u32 space); +int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl); +int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid); +int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw); +int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop); + +/* Functions */ int rtw_halmac_poweron(struct dvobj_priv *); int rtw_halmac_poweroff(struct dvobj_priv *); int rtw_halmac_init_hal(struct dvobj_priv *); @@ -64,6 +161,7 @@ int rtw_halmac_init_hal_fw(struct dvobj_priv *, u8 *fw, u32 fwsize); int rtw_halmac_init_hal_fw_file(struct dvobj_priv *, u8 *fwpath); int rtw_halmac_deinit_hal(struct dvobj_priv *); int rtw_halmac_self_verify(struct dvobj_priv *); +int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout); int rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize); int rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath); int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem); @@ -71,14 +169,15 @@ int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem int rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable); int rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c); int rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size); -int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size); +/* eFuse */ +int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size); int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size); int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); int rtw_halmac_read_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); int rtw_halmac_write_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *, u32 *size); -int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); +int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize); int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize); int rtw_halmac_read_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); @@ -86,27 +185,17 @@ int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); -int rtw_halmac_config_rx_info(struct dvobj_priv *, HALMAC_DRV_INFO); -int rtw_halmac_set_mac_address(struct dvobj_priv *, enum _hw_port, u8 *addr); -int rtw_halmac_set_bssid(struct dvobj_priv *, enum _hw_port hwport, u8 *addr); - -int rtw_halmac_set_bandwidth(struct dvobj_priv *, u8 channel, u8 pri_ch_idx, u8 bw); -int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop); - int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer); int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable); -int rtw_halmac_get_hw_value(struct dvobj_priv *, HALMAC_HW_ID hw_id, VOID *pvalue); -int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason); -int rtw_halmac_get_drv_info_sz(struct dvobj_priv *, u8 *sz); -int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg); -int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size); -int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num); /* Specific function APIs*/ int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size); int rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *); int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para); int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment); +int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para); +int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode); +void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on); #ifdef CONFIG_SDIO_HCI int rtw_halmac_query_tx_page_num(struct dvobj_priv *); @@ -118,6 +207,7 @@ u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *, u8 *seq); #ifdef CONFIG_USB_HCI u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *, u8 *buf, u32 size); +int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num); u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode); #endif /* CONFIG_USB_HCI */ @@ -128,17 +218,17 @@ void dump_trx_share_mode(void *sel, _adapter *adapter); #ifdef CONFIG_BEAMFORMING #ifdef RTW_BEAMFORMING_VERSION_2 int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para, - u16 my_aid, HALMAC_CSI_SEG_LEN sel, u8 *addr); + u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr); int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d); -int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, HALMAC_SND_ROLE role, - HALMAC_DATA_RATE rate); -int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, HALMAC_SND_ROLE role); +int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, enum halmac_snd_role role, + enum halmac_data_rate rate); +int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, enum halmac_snd_role role); int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate, u8 fixrate_en, u8 *new_rate); -int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, HALMAC_SND_ROLE role, +int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role, u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en, u32 *given_gid_tab, u32 *given_user_pos); #define rtw_halmac_bf_cfg_mu_bfee(d, gid_tab, user_pos) \ diff --git a/hal/hal_hci/hal_usb.c b/hal/hal_hci/hal_usb.c index 50b3d57..e47135b 100644 --- a/hal/hal_hci/hal_usb.c +++ b/hal/hal_hci/hal_usb.c @@ -213,7 +213,7 @@ void usb_free_recv_priv(_adapter *padapter, u16 ini_in_buf_sz) IF_DEQUEUE(&precvpriv->rx_indicate_queue, m); if (m == NULL) break; - m_freem(m); + rtw_os_pkt_free(m); } mtx_destroy(&precvpriv->rx_indicate_queue.ifq_mtx); #endif /* CONFIG_RX_INDICATE_QUEUE */ diff --git a/hal/hal_intf.c b/hal/hal_intf.c index 3956950..351e923 100644 --- a/hal/hal_intf.c +++ b/hal/hal_intf.c @@ -51,7 +51,7 @@ u8 rtw_hal_read_chip_info(_adapter *padapter) { u8 rtn = _SUCCESS; u8 hci_type = rtw_get_intf_type(padapter); - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); /* before access eFuse, make sure card enable has been called */ if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI) @@ -149,26 +149,49 @@ void rtw_hal_dm_deinit(_adapter *padapter) _rtw_spinlock_free(&pHalData->IQKSpinLock); } } -void rtw_hal_sw_led_init(_adapter *padapter) + +#ifdef CONFIG_RTW_SW_LED +void rtw_hal_sw_led_init(_adapter *padapter) { - if (padapter->hal_func.InitSwLeds) + struct led_priv *ledpriv = adapter_to_led(padapter); + + if (ledpriv->bRegUseLed == _FALSE) + return; + + if (!is_primary_adapter(padapter)) + return; + + if (padapter->hal_func.InitSwLeds) { padapter->hal_func.InitSwLeds(padapter); + rtw_led_set_ctl_en_mask_primary(padapter); + rtw_led_set_iface_en(padapter, 1); + } } void rtw_hal_sw_led_deinit(_adapter *padapter) { + struct led_priv *ledpriv = adapter_to_led(padapter); + + if (ledpriv->bRegUseLed == _FALSE) + return; + + if (!is_primary_adapter(padapter)) + return; + if (padapter->hal_func.DeInitSwLeds) padapter->hal_func.DeInitSwLeds(padapter); } +#endif u32 rtw_hal_power_on(_adapter *padapter) { u32 ret = 0; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); ret = padapter->hal_func.hal_power_on(padapter); #ifdef CONFIG_BT_COEXIST - if (ret == _SUCCESS) + if ((ret == _SUCCESS) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) rtw_btcoex_PowerOnSetting(padapter); #endif @@ -200,27 +223,34 @@ void rtw_hal_init_opmode(_adapter *padapter) networkType = Ndis802_11IBSS; else if (fw_state & WIFI_STATION_STATE) networkType = Ndis802_11Infrastructure; +#ifdef CONFIG_AP_MODE else if (fw_state & WIFI_AP_STATE) networkType = Ndis802_11APMode; +#endif +#ifdef CONFIG_RTW_MESH + else if (fw_state & WIFI_MESH_STATE) + networkType = Ndis802_11_mesh; +#endif else return; - rtw_setopmode_cmd(padapter, networkType, _FALSE); + rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY); } uint rtw_hal_init(_adapter *padapter) { uint status = _SUCCESS; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); int i; status = padapter->hal_func.hal_init(padapter); if (status == _SUCCESS) { - pHalData->hw_init_completed = _TRUE; + rtw_set_hw_init_completed(padapter, _TRUE); rtw_restore_mac_addr(padapter); - + #ifdef RTW_HALMAC + rtw_restore_hw_port_cfg(padapter); + #endif if (padapter->registrypriv.notch_filter == 1) rtw_hal_notch_filter(padapter, 1); @@ -237,9 +267,15 @@ uint rtw_hal_init(_adapter *padapter) rtw_bb_rf_gain_offset(padapter); #endif /*CONFIG_RF_POWER_TRIM*/ +#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) +#ifdef CONFIG_DYNAMIC_SOML + rtw_dyn_soml_config(padapter); +#endif +#endif + } else { - pHalData->hw_init_completed = _FALSE; - RTW_INFO("rtw_hal_init: hal_init fail\n"); + rtw_set_hw_init_completed(padapter, _FALSE); + RTW_ERR("%s: fail\n", __func__); } @@ -251,14 +287,13 @@ uint rtw_hal_deinit(_adapter *padapter) { uint status = _SUCCESS; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); int i; status = padapter->hal_func.hal_deinit(padapter); if (status == _SUCCESS) { rtw_led_control(padapter, LED_CTL_POWER_OFF); - pHalData->hw_init_completed = _FALSE; + rtw_set_hw_init_completed(padapter, _FALSE); } else RTW_INFO("\n rtw_hal_deinit: hal_init fail\n"); @@ -266,9 +301,9 @@ uint rtw_hal_deinit(_adapter *padapter) return status; } -void rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val) +u8 rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val) { - padapter->hal_func.set_hw_reg_handler(padapter, variable, val); + return padapter->hal_func.set_hw_reg_handler(padapter, variable, val); } void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val) @@ -330,12 +365,18 @@ s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan) #ifdef RTW_HALMAC s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem) { - u32 dlfw_start_time = rtw_get_current_time(); + systime dlfw_start_time = rtw_get_current_time(); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; s32 rst = _FALSE; rst = padapter->hal_func.fw_mem_dl(padapter, mem); RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(dlfw_start_time)); + if (rst == _FALSE) + pdbgpriv->dbg_fw_mem_dl_error_cnt++; + if (1) + RTW_INFO("%s dbg_fw_mem_dl_error_cnt:%d\n", __func__, pdbgpriv->dbg_fw_mem_dl_error_cnt); return rst; } #endif @@ -449,38 +490,18 @@ s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe) s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe) { s32 ret = _FAIL; - u8 *pframe, subtype; - struct rtw_ieee80211_hdr *pwlanhdr; - struct sta_info *psta; - struct sta_priv *pstapriv = &padapter->stapriv; update_mgntframe_attrib_addr(padapter, pmgntframe); - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */ - - /* pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; */ - /* _rtw_memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN); */ - -#ifdef CONFIG_IEEE80211W - if (padapter->securitypriv.binstallBIPkey == _TRUE && (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || - subtype == WIFI_ACTION)) { - if (IS_MCAST(pmgntframe->attrib.ra) && pmgntframe->attrib.key_type != IEEE80211W_NO_KEY) { - pmgntframe->attrib.encrypt = _BIP_; - /* pmgntframe->attrib.bswenc = _TRUE; */ - } else if (pmgntframe->attrib.key_type != IEEE80211W_NO_KEY) { - psta = rtw_get_stainfo(pstapriv, pmgntframe->attrib.ra); - if (psta && psta->bpairwise_key_installed == _TRUE) { - pmgntframe->attrib.encrypt = _AES_; - pmgntframe->attrib.bswenc = _TRUE; - } else { - RTW_INFO("%s, %d, bpairwise_key_installed is FALSE\n", __func__, __LINE__); - goto no_mgmt_coalesce; - } - } - RTW_INFO("encrypt=%d, bswenc=%d\n", pmgntframe->attrib.encrypt, pmgntframe->attrib.bswenc); + +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) + if ((!MLME_IS_MESH(padapter) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) + #ifdef CONFIG_RTW_MESH + || (MLME_IS_MESH(padapter) && padapter->mesh_info.mesh_auth_id) + #endif + ) rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe); - } -#endif /* CONFIG_IEEE80211W */ +#endif + no_mgmt_coalesce: ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe); return ret; @@ -504,97 +525,44 @@ void rtw_hal_free_recv_priv(_adapter *padapter) padapter->hal_func.free_recv_priv(padapter); } -void rtw_update_ramask(_adapter *padapter, struct sta_info *psta, u32 mac_id, u8 rssi_level, u8 is_update_bw) +void rtw_sta_ra_registed(_adapter *padapter, struct sta_info *psta) { - struct macid_cfg h2c_macid_cfg; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); - u8 disable_cck_rate = FALSE, MimoPs_enable = FALSE; - u32 ratr_bitmap_msb = 0, ratr_bitmap_lsb = 0; - u64 mask = 0, rate_bitmap = 0; - u8 bw, short_gi; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); if (psta == NULL) { - RTW_ERR(FUNC_ADPT_FMT" macid:%u, sta is NULL\n", FUNC_ADPT_ARG(padapter), mac_id); + RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(padapter)); rtw_warn_on(1); return; } - _rtw_memset(&h2c_macid_cfg, 0, sizeof(struct macid_cfg)); - - bw = rtw_get_tx_bw_mode(padapter, psta); - short_gi = query_ra_short_GI(psta, bw); - ratr_bitmap_msb = (u32)(psta->ra_mask >> 32); - ratr_bitmap_lsb = (u32)(psta->ra_mask); - - phydm_update_hal_ra_mask(&hal_data->odmpriv, psta->wireless_mode, hal_data->rf_type, bw, MimoPs_enable, disable_cck_rate, &ratr_bitmap_msb, &ratr_bitmap_lsb, rssi_level); - mask = (((u64)ratr_bitmap_msb) << 32) | ((u64)ratr_bitmap_lsb); - - -#ifdef CONFIG_BT_COEXIST - if (hal_data->EEPROMBluetoothCoexist == 1) { - rate_bitmap = rtw_btcoex_GetRaMask(padapter); - mask &= ~rate_bitmap; - } -#endif /* CONFIG_BT_COEXIST */ - -#ifdef CONFIG_CMCC_TEST -#ifdef CONFIG_BT_COEXIST - if (pmlmeext->cur_wireless_mode & WIRELESS_11G) { - if (mac_id == 0) { - RTW_INFO("CMCC_BT update raid entry, mask=0x%x\n", mask); - /*mask &=0xffffffc0; //disable CCK & <12M OFDM rate for 11G mode for CMCC */ - mask &= 0xffffff00; /*disable CCK & <24M OFDM rate for 11G mode for CMCC */ - RTW_INFO("CMCC_BT update raid entry, mask=0x%x\n", mask); +#ifdef CONFIG_AP_MODE + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { + if (psta->cmn.aid > padapter->stapriv.max_aid) { + RTW_ERR("station aid %d exceed the max number\n", psta->cmn.aid); + rtw_warn_on(1); + return; } + rtw_ap_update_sta_ra_info(padapter, psta); } -#endif #endif + psta->cmn.ra_info.ra_bw_mode = rtw_get_tx_bw_mode(padapter, psta); /*set correct initial date rate for each mac_id */ - hal_data->INIDATA_RATE[mac_id] = psta->init_rate; - - - RTW_INFO("%s => mac_id:%d, networkType:0x%02x, mask:0x%016llx\n\t ==> rssi_level:%d, rate_bitmap:0x%016llx, shortGIrate=%d\n\t ==> bw:%d, ignore_bw:0x%d\n", - __func__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap, short_gi, bw, (!is_update_bw)); - - rtw_macid_ctl_set_bw(macid_ctl, mac_id, bw); - rtw_macid_ctl_set_vht_en(macid_ctl, mac_id, is_supported_vht(psta->wireless_mode)); - rtw_macid_ctl_set_rate_bmp0(macid_ctl, mac_id, mask); - rtw_macid_ctl_set_rate_bmp1(macid_ctl, mac_id, mask >> 32); - rtw_update_tx_rate_bmp(adapter_to_dvobj(padapter)); + hal_data->INIDATA_RATE[psta->cmn.mac_id] = psta->init_rate; - h2c_macid_cfg.mac_id = mac_id; - h2c_macid_cfg.rate_id = psta->raid; - h2c_macid_cfg.bandwidth = bw; - h2c_macid_cfg.ignore_bw = (!is_update_bw); - h2c_macid_cfg.short_gi = short_gi; - h2c_macid_cfg.ra_mask = mask; - - padapter->hal_func.update_ra_mask_handler(padapter, psta, &h2c_macid_cfg); + rtw_phydm_ra_registed(padapter, psta); } -void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level, u8 is_update_bw) +void rtw_hal_update_ra_mask(struct sta_info *psta) { _adapter *padapter; - struct mlme_priv *pmlmepriv; if (!psta) return; padapter = psta->padapter; - - pmlmepriv = &(padapter->mlmepriv); - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) - add_RATid(padapter, psta, rssi_level, is_update_bw); - else { - psta->raid = rtw_hal_networktype_to_raid(padapter, psta); - rtw_update_ramask(padapter, psta, psta->mac_id, rssi_level, is_update_bw); - } + rtw_sta_ra_registed(padapter, psta); } /* Start specifical interface thread */ @@ -631,7 +599,7 @@ void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data) padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data); } -u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask) +u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask) { u32 data = 0; @@ -647,7 +615,7 @@ u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask return data; } -void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data) { if (padapter->hal_func.write_rfreg) { @@ -680,22 +648,22 @@ void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf) } #endif -void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80) +void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0; u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0; u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0; u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0; - odm_acquire_spin_lock(pDM_Odm, RT_IQK_SPINLOCK); - if (pDM_Odm->rf_calibrate_info.is_iqk_in_progress == _TRUE) + if (rtw_phydm_is_iqk_in_progress(padapter)) RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__); - odm_release_spin_lock(pDM_Odm, RT_IQK_SPINLOCK); +#ifdef CONFIG_MP_INCLUDED /* MP mode channel don't use secondary channel */ - if (rtw_mp_mode_check(padapter) == _FALSE) { + if (rtw_mp_mode_check(padapter) == _FALSE) +#endif + { #if 0 if (cch_160 != 0) cch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80); @@ -732,15 +700,13 @@ void rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel) void rtw_hal_dm_watchdog(_adapter *padapter) { -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) - return; - } -#endif /* CONFIG_MCC_MODE */ + rtw_hal_turbo_edca(padapter); padapter->hal_func.hal_dm_watchdog(padapter); +#ifdef CONFIG_PCI_DYNAMIC_ASPM + rtw_pci_aspm_config_dynamic_l1_ilde_time(padapter); +#endif } #ifdef CONFIG_LPS_LCLK_WD_TIMER @@ -753,11 +719,10 @@ void rtw_hal_dm_watchdog_in_lps(_adapter *padapter) #endif #endif - if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE) { - padapter->hal_func.hal_dm_watchdog_in_lps(padapter);/* this function caller is in interrupt context */ - } + if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE) + rtw_phydm_watchdog_in_lps_lclk(padapter);/* this function caller is in interrupt context */ } -#endif +#endif /*CONFIG_LPS_LCLK_WD_TIMER*/ void rtw_hal_bcn_related_reg_setting(_adapter *padapter) { @@ -903,8 +868,6 @@ bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 * #endif s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) { - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *odm = &hal_data->odmpriv; u8 sub_id = 0; s32 ret = _SUCCESS; @@ -924,7 +887,10 @@ s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) rtw_btcoex_BtMpRptNotify(adapter, plen, payload); break; case C2H_MAILBOX_STATUS: - RTW_INFO_DUMP("C2H_MAILBOX_STATUS: ", payload, plen); + RTW_DBG_DUMP("C2H_MAILBOX_STATUS: ", payload, plen); + break; + case C2H_WLAN_INFO: + rtw_btcoex_WlFwDbgInfoNotify(adapter, payload, plen); break; #endif /* CONFIG_BT_COEXIST */ @@ -968,13 +934,17 @@ s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) c2h_customer_str_rpt_2_hdl(adapter, payload, plen); break; #endif - +#ifdef RTW_PER_CMD_SUPPORT_FW + case C2H_PER_RATE_RPT: + c2h_per_rate_rpt_hdl(adapter, payload, plen); + break; +#endif case C2H_EXTEND: sub_id = payload[0]; /* no handle, goto default */ default: - if (phydm_c2H_content_parsing(odm, id, plen, payload) != TRUE) + if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE) ret = _FAIL; break; } @@ -1025,50 +995,156 @@ s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter) return GET_HAL_DATA(padapter)->bDisableSWChannelPlan; } -s32 rtw_hal_macid_sleep(PADAPTER padapter, u8 macid) +static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - u8 support; - - support = _FALSE; - rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support); - if (_FALSE == support) - return _FAIL; + struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter); + u16 reg_sleep; + u8 bit_shift; + u32 val32; + s32 ret = _FAIL; if (macid >= macid_ctl->num) { - RTW_ERR(FUNC_ADPT_FMT": Invalid macid(%u)\n", - FUNC_ADPT_ARG(padapter), macid); - return _FAIL; + RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n" + , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid); + goto exit; + } + + if (macid < 32) { + reg_sleep = macid_ctl->reg_sleep_m0; + bit_shift = macid; + #if (MACID_NUM_SW_LIMIT > 32) + } else if (macid < 64) { + reg_sleep = macid_ctl->reg_sleep_m1; + bit_shift = macid - 32; + #endif + #if (MACID_NUM_SW_LIMIT > 64) + } else if (macid < 96) { + reg_sleep = macid_ctl->reg_sleep_m2; + bit_shift = macid - 64; + #endif + #if (MACID_NUM_SW_LIMIT > 96) + } else if (macid < 128) { + reg_sleep = macid_ctl->reg_sleep_m3; + bit_shift = macid - 96; + #endif + } else { + rtw_warn_on(1); + goto exit; } - rtw_hal_set_hwreg(padapter, HW_VAR_MACID_SLEEP, &macid); + if (!reg_sleep) { + rtw_warn_on(1); + goto exit; + } - return _SUCCESS; + val32 = rtw_read32(adapter, reg_sleep); + RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n" + , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" + , macid, reg_sleep, val32); + + ret = _SUCCESS; + + if (sleep) { + if (val32 & BIT(bit_shift)) + goto exit; + val32 |= BIT(bit_shift); + } else { + if (!(val32 & BIT(bit_shift))) + goto exit; + val32 &= ~BIT(bit_shift); + } + + rtw_write32(adapter, reg_sleep, val32); + +exit: + return ret; } -s32 rtw_hal_macid_wakeup(PADAPTER padapter, u8 macid) +inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - u8 support; + return _rtw_hal_macid_sleep(adapter, macid, 1); +} - support = _FALSE; - rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support); - if (_FALSE == support) - return _FAIL; +inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid) +{ + return _rtw_hal_macid_sleep(adapter, macid, 0); +} - if (macid >= macid_ctl->num) { - RTW_ERR(FUNC_ADPT_FMT": Invalid macid(%u)\n", - FUNC_ADPT_ARG(padapter), macid); - return _FAIL; - } +static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep) +{ + struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter); + u16 reg_sleep; + u32 *m = &bmp->m0; + u8 mid = 0; + u32 val32; - rtw_hal_set_hwreg(padapter, HW_VAR_MACID_WAKEUP, &macid); + do { + if (*m == 0) + goto move_next; + + if (mid == 0) + reg_sleep = macid_ctl->reg_sleep_m0; + #if (MACID_NUM_SW_LIMIT > 32) + else if (mid == 1) + reg_sleep = macid_ctl->reg_sleep_m1; + #endif + #if (MACID_NUM_SW_LIMIT > 64) + else if (mid == 2) + reg_sleep = macid_ctl->reg_sleep_m2; + #endif + #if (MACID_NUM_SW_LIMIT > 96) + else if (mid == 3) + reg_sleep = macid_ctl->reg_sleep_m3; + #endif + else { + rtw_warn_on(1); + break; + } + + if (!reg_sleep) { + rtw_warn_on(1); + break; + } + + val32 = rtw_read32(adapter, reg_sleep); + RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n" + , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" + , mid, *m, reg_sleep, val32); + + if (sleep) { + if ((val32 & *m) == *m) + goto move_next; + val32 |= *m; + } else { + if ((val32 & *m) == 0) + goto move_next; + val32 &= ~(*m); + } + + rtw_write32(adapter, reg_sleep, val32); + +move_next: + m++; + mid++; + } while (mid * 32 < MACID_NUM_SW_LIMIT); return _SUCCESS; } +inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter) +{ + struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter); + + return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 1); +} + +inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter) +{ + struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter); + + return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 0); +} + s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) { _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter); @@ -1087,9 +1163,21 @@ void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen, padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame); } + u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan) { - return adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan); + u8 num = 0; + + + if (adapter->hal_func.hal_get_tx_buff_rsvd_page_num) { + num = adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan); + } else { +#ifdef RTW_HALMAC + num = GET_HAL_DATA(adapter)->drv_rsvd_page_number; +#endif /* RTW_HALMAC */ + } + + return num; } #ifdef CONFIG_GPIO_API @@ -1122,12 +1210,12 @@ void rtw_hal_fw_correct_bcn(_adapter *padapter) padapter->hal_func.fw_correct_bcn(padapter); } -void rtw_hal_set_tx_power_index(PADAPTER padapter, u32 powerindex, u8 rfpath, u8 rate) +void rtw_hal_set_tx_power_index(PADAPTER padapter, u32 powerindex, enum rf_path rfpath, u8 rate) { return padapter->hal_func.set_tx_power_index_handler(padapter, powerindex, rfpath, rate); } -u8 rtw_hal_get_tx_power_index(PADAPTER padapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic) +u8 rtw_hal_get_tx_power_index(PADAPTER padapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic) { return padapter->hal_func.get_tx_power_index_handler(padapter, rfpath, rate, bandwidth, channel, tic); } @@ -1160,6 +1248,21 @@ u8 rtw_hal_init_phy(PADAPTER adapter) } #endif /* RTW_HALMAC */ +#ifdef CONFIG_RFKILL_POLL +bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid) +{ + bool ret; + + if (adapter->hal_func.hal_radio_onoff_check) + ret = adapter->hal_func.hal_radio_onoff_check(adapter, valid); + else { + *valid = 0; + ret = _FALSE; + } + return ret; +} +#endif + #define rtw_hal_error_msg(ops_fun) \ RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun) @@ -1309,12 +1412,6 @@ u8 rtw_hal_ops_check(_adapter *padapter) rtw_hal_error_msg("hal_dm_watchdog"); ret = _FAIL; } -#ifdef CONFIG_LPS_LCLK_WD_TIMER - if (NULL == padapter->hal_func.hal_dm_watchdog_in_lps) { - rtw_hal_error_msg("hal_dm_watchdog_in_lps"); - ret = _FAIL; - } -#endif /*** xxx section ***/ if (NULL == padapter->hal_func.set_chnl_bw_handler) { @@ -1346,10 +1443,6 @@ u8 rtw_hal_ops_check(_adapter *padapter) rtw_hal_error_msg("SetHalODMVarHandler"); ret = _FAIL; } - if (NULL == padapter->hal_func.update_ra_mask_handler) { - rtw_hal_error_msg("update_ra_mask_handler"); - ret = _FAIL; - } if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) { rtw_hal_error_msg("SetBeaconRelatedRegistersHandler"); @@ -1379,10 +1472,13 @@ u8 rtw_hal_ops_check(_adapter *padapter) ret = _FAIL; } #endif + +#ifndef RTW_HALMAC if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) { rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num"); ret = _FAIL; } +#endif /* !RTW_HALMAC */ #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) @@ -1466,6 +1562,13 @@ u8 rtw_hal_ops_check(_adapter *padapter) ret = _FAIL; } #endif /* RTW_HALMAC */ + +#ifdef CONFIG_RFKILL_POLL + if (padapter->hal_func.hal_radio_onoff_check == NULL) { + rtw_hal_error_msg("hal_radio_onoff_check"); + ret = _FAIL; + } +#endif #endif return ret; } diff --git a/hal/hal_mcc.c b/hal/hal_mcc.c index 606d02a..27138c7 100644 --- a/hal/hal_mcc.c +++ b/hal/hal_mcc.c @@ -20,21 +20,25 @@ #include /* HAL_DATA */ #include /* power control */ -#define MCC_DURATION_IDX 0 +/* use for AP/GO + STA/GC case */ +#define MCC_DURATION_IDX 0 /* druration for station side */ #define MCC_TSF_SYNC_OFFSET_IDX 1 #define MCC_START_TIME_OFFSET_IDX 2 #define MCC_INTERVAL_IDX 3 #define MCC_GUARD_OFFSET0_IDX 4 #define MCC_GUARD_OFFSET1_IDX 5 +#define MCC_STOP_THRESHOLD 6 #define TU 1024 /* 1 TU equals 1024 microseconds */ -/* port 1 druration, TSF sync offset, start time offset, interval (unit:TU (1024 microseconds))*/ -u8 mcc_switch_channel_policy_table[][6]={ - {35, 50, 30, 100, 0, 0}, - {19, 50, 40, 100, 2, 2}, - {25, 50, 30, 100, 5, 5}, +/* druration, TSF sync offset, start time offset, interval (unit:TU (1024 microseconds))*/ +u8 mcc_switch_channel_policy_table[][7]={ + {20, 50, 40, 100, 0, 0, 30}, + {80, 50, 10, 100, 0, 0, 30}, + {36, 50, 32, 100, 0, 0, 30}, + {30, 50, 35, 100, 0, 0, 30}, }; -const int mcc_max_policy_num = sizeof(mcc_switch_channel_policy_table) /sizeof(u8) /6; +const int mcc_max_policy_num = sizeof(mcc_switch_channel_policy_table) /sizeof(u8) /7; +struct mi_state mcc_mstate; static void dump_iqk_val_table(PADAPTER padapter) { @@ -45,6 +49,9 @@ static void dump_iqk_val_table(PADAPTER padapter) u8 backup_chan_idx = 0; u8 backup_reg_idx = 0; +#ifdef CONFIG_MCC_MODE_V2 +#else + RTW_INFO("=============dump IQK backup table================\n"); for (backup_chan_idx = 0; backup_chan_idx < MAX_IQK_INFO_BACKUP_CHNL_NUM; backup_chan_idx++) { for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx++) { @@ -60,6 +67,8 @@ static void dump_iqk_val_table(PADAPTER padapter) } } RTW_INFO("=============================================\n"); + +#endif } static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_len) @@ -72,14 +81,14 @@ static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_le u8 noa_desc_num = 1; u8 opp_ps = 0; /* Disable OppPS */ u8 noa_count = 255; - u32 noa_duration = 0x20; - u32 noa_interval = 0x64; + u32 noa_duration; + u32 noa_interval; u8 noa_index = 0; u8 mcc_policy_idx = 0; mcc_policy_idx = pmccobjpriv->policy_index; - noa_duration = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX]; - noa_interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX]; + noa_duration = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX] * TU; + noa_interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX] * TU; /* P2P OUI(4 bytes) */ _rtw_memcpy(p2p_noa_attr_ie, P2P_OUI, 4); @@ -90,7 +99,7 @@ static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_le p2p_noa_attr_len = p2p_noa_attr_len + 1; /* attrute length(2 bytes) length = noa_desc_num*13 + 2 */ - RTW_PUT_LE16(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_desc_num*13 + 2)); + RTW_PUT_LE16(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_desc_num * 13 + 2)); p2p_noa_attr_len = p2p_noa_attr_len + 2; /* Index (1 byte) */ @@ -106,11 +115,11 @@ static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_le p2p_noa_attr_len = p2p_noa_attr_len + 1; /* NoA Duration (4 bytes) unit: microseconds */ - RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_duration * TU)); + RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_duration); p2p_noa_attr_len = p2p_noa_attr_len + 4; /* NoA Interval (4 bytes) unit: microseconds */ - RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_interval * TU)); + RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_interval); p2p_noa_attr_len = p2p_noa_attr_len + 4; /* NoA Start Time (4 bytes) unit: microseconds */ @@ -135,6 +144,7 @@ static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_le static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter) { struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); u8 *pos = NULL; @@ -142,14 +152,22 @@ static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter) if (pmccadapriv->p2p_go_noa_ie_len == 0) rtw_hal_mcc_build_p2p_noa_attr(padapter, pmccadapriv->p2p_go_noa_ie, &pmccadapriv->p2p_go_noa_ie_len); else { - /* has noa attribut, modify it */ + /* has noa attribut, modify it */ + u32 noa_duration = 0; + /* update index */ pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 15; /* 0~255 */ (*pos) = ((*pos) + 1) % 256; - if (1) + if (0) RTW_INFO("indxe:%d\n", (*pos)); + + /* update duration */ + noa_duration = mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX] * TU; + pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 12; + RTW_PUT_LE32(pos, noa_duration); + /* update start time */ pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 4; RTW_PUT_LE32(pos, pmccadapriv->noa_start_time); @@ -163,16 +181,8 @@ static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter) } if (0) { - u8 i = 0; RTW_INFO("p2p_go_noa_ie_len:%d\n", pmccadapriv->p2p_go_noa_ie_len); - - for (i = 0;i < pmccadapriv->p2p_go_noa_ie_len; i++) { - if ((i+1)%8 != 0) - printk("0x%02x ", pmccadapriv->p2p_go_noa_ie[i]); - else - printk("0x%02x\n", pmccadapriv->p2p_go_noa_ie[i]); - } - printk("\n"); + RTW_INFO_DUMP("\n", pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len); } update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE); } @@ -241,101 +251,74 @@ void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status) pmccobjpriv->mcc_status &= (~mcc_status); } -void rtw_hal_mcc_update_switch_channel_policy_table(PADAPTER padapter) +static void rtw_hal_mcc_update_policy_table(PADAPTER adapter) { - struct registry_priv *registry_par = &padapter->registrypriv; - u8 idx = 0; - - if (registry_par->rtw_mcc_policy_table_idx < 0) - return; - - if (registry_par->rtw_mcc_policy_table_idx >= mcc_max_policy_num) { - RTW_INFO("[MCC] mcc_policy_table_idx error, do not update policy table\n"); - return; - } - - idx = registry_par->rtw_mcc_policy_table_idx; - - if (registry_par->rtw_mcc_duration > 0) - mcc_switch_channel_policy_table[idx][MCC_DURATION_IDX] = registry_par->rtw_mcc_duration; - - if (registry_par->rtw_mcc_tsf_sync_offset > 0) - mcc_switch_channel_policy_table[idx][MCC_TSF_SYNC_OFFSET_IDX] = registry_par->rtw_mcc_tsf_sync_offset; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + u8 mcc_duration = mccobjpriv->duration; + s8 mcc_policy_idx = mccobjpriv->policy_index; + u8 interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX]; + u8 new_mcc_duration_time = 0; + u8 new_starttime_offset = 0; - if (registry_par->rtw_mcc_start_time_offset > 0) - mcc_switch_channel_policy_table[idx][MCC_START_TIME_OFFSET_IDX] = registry_par->rtw_mcc_start_time_offset; + /* convert % to ms */ + new_mcc_duration_time = mcc_duration * interval / 100; - if (registry_par->rtw_mcc_interval > 0) - mcc_switch_channel_policy_table[idx][MCC_INTERVAL_IDX] = registry_par->rtw_mcc_interval; + /* start time offset = (interval - duration time)/2 */ + new_starttime_offset = (interval - new_mcc_duration_time) >> 1; - if (registry_par->rtw_mcc_guard_offset0 >= 0) - mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET0_IDX] = registry_par->rtw_mcc_guard_offset0; + /* update modified parameters */ + mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX] + = new_mcc_duration_time; - if (registry_par->rtw_mcc_guard_offset1 >= 0) - mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET1_IDX] = registry_par->rtw_mcc_guard_offset1; + mcc_switch_channel_policy_table[mcc_policy_idx][MCC_START_TIME_OFFSET_IDX] + = new_starttime_offset; + } static void rtw_hal_config_mcc_switch_channel_setting(PADAPTER padapter) { - struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); struct registry_priv *registry_par = &padapter->registrypriv; - u8 interval = pmlmepriv->cur_network.network.Configuration.BeaconPeriod; - u8 i = 0; + u8 mcc_duration = 0; s8 mcc_policy_idx = 0; - rtw_hal_mcc_update_switch_channel_policy_table(padapter); mcc_policy_idx = registry_par->rtw_mcc_policy_table_idx; + mcc_duration = mccobjpriv->duration; if (mcc_policy_idx < 0 || mcc_policy_idx >= mcc_max_policy_num) { - pmccobjpriv->policy_index = 0; - RTW_INFO("[MCC] can't find table(%d,%d,%d), use default policy(%d)\n" - , pmccobjpriv->duration, interval, mcc_policy_idx, pmccobjpriv->policy_index); + mccobjpriv->policy_index = 0; + RTW_INFO("[MCC] can't find table(%d), use default policy(%d)\n", + mcc_policy_idx, mccobjpriv->policy_index); } else - pmccobjpriv->policy_index = mcc_policy_idx; + mccobjpriv->policy_index = mcc_policy_idx; + + /* convert % to time */ + if (mcc_duration != 0) + rtw_hal_mcc_update_policy_table(padapter); RTW_INFO("[MCC] policy(%d): %d,%d,%d,%d,%d,%d\n" - , pmccobjpriv->policy_index - , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX] - , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_TSF_SYNC_OFFSET_IDX] - , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_START_TIME_OFFSET_IDX] - , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX] - , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX] - , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]); + , mccobjpriv->policy_index + , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX] + , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_TSF_SYNC_OFFSET_IDX] + , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_START_TIME_OFFSET_IDX] + , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_INTERVAL_IDX] + , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX] + , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]); } -static void rtw_hal_config_mcc_role_setting(PADAPTER padapter) +static void rtw_hal_mcc_assign_tx_threshold(PADAPTER padapter) { - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv); - struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct wlan_network *cur_network = &(pmlmepriv->cur_network); - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta = NULL; struct registry_priv *preg = &padapter->registrypriv; - u8 policy_index = 0; - u8 mcc_duration = 0; - u8 mcc_interval = 0; - - policy_index = pmccobjpriv->policy_index; - mcc_duration = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX] - - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX] - - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]; - mcc_interval = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX]; + struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - /* GO/AP is 1nd order GC/STA is 2nd order */ switch (pmccadapriv->role) { case MCC_ROLE_STA: case MCC_ROLE_GC: - pmccadapriv->order = 1; - pmccadapriv->mcc_duration = mcc_duration; - switch (pmlmeext->cur_bwmode) { case CHANNEL_WIDTH_20: /* @@ -359,26 +342,9 @@ static void rtw_hal_config_mcc_role_setting(PADAPTER padapter) , FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode); break; } - - /* assign used mac to avoid affecting RA */ - pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID; - - psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); - if (psta) { - /* combine AP/GO macid and mgmt queue macid to bitmap */ - pmccadapriv->mcc_macid_bitmap = BIT(psta->mac_id) | BIT(pmccadapriv->mgmt_queue_macid); - } else { - RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter)); - rtw_warn_on(1); - } break; case MCC_ROLE_AP: case MCC_ROLE_GO: - pmccadapriv->order = 0; - /* total druation value equals interval */ - pmccadapriv->mcc_duration = mcc_interval - mcc_duration; - pmccadapriv->p2p_go_noa_ie_len = 0; /* not NoA attribute at init time */ - switch (pmlmeext->cur_bwmode) { case CHANNEL_WIDTH_20: pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration; @@ -395,31 +361,149 @@ static void rtw_hal_config_mcc_role_setting(PADAPTER padapter) , FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode); break; } + break; + } +} + +static void rtw_hal_config_mcc_role_setting(PADAPTER padapter, u8 order) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv); + struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; + struct registry_priv *preg = &padapter->registrypriv; + _irqL irqL; + _list *phead =NULL, *plist = NULL; + u8 policy_index = 0; + u8 mcc_duration = 0; + u8 mcc_interval = 0; + policy_index = pmccobjpriv->policy_index; + mcc_duration = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX] + - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX] + - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]; + mcc_interval = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX]; - psta = rtw_get_bcmc_stainfo(padapter); + if (MSTATE_AP_STARTING_NUM(&mcc_mstate) == 0 + && MSTATE_AP_NUM(&mcc_mstate) == 0) { + pmccadapriv->order = order; - if (psta != NULL) - pmccadapriv->mgmt_queue_macid = psta->mac_id; - else { + if (pmccadapriv->order == 0) { + /* setting is smiliar to GO/AP */ + /* pmccadapriv->mcc_duration = mcc_interval - mcc_duration;*/ pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID; - RTW_INFO(FUNC_ADPT_FMT":bcmc station is NULL, use macid %d\n" - , FUNC_ADPT_ARG(padapter), pmccadapriv->mgmt_queue_macid); + } else if (pmccadapriv->order == 1) { + /* pmccadapriv->mcc_duration = mcc_duration; */ + pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID; + } else { + RTW_INFO("[MCC] not support >= 3 interface\n"); + rtw_warn_on(1); } - /* combine client macid and mgmt queue macid to bitmap */ - pmccadapriv->mcc_macid_bitmap = (0xff << 8) | BIT(pmccadapriv->mgmt_queue_macid); - break; - default: - RTW_INFO("Unknown role\n"); - rtw_warn_on(1); - break; + rtw_hal_mcc_assign_tx_threshold(padapter); + + psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if (psta) { + /* combine AP/GO macid and mgmt queue macid to bitmap */ + pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid); + } else { + RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter)); + rtw_warn_on(1); + } + } else { + /* GO/AP is 1nd order GC/STA is 2nd order */ + switch (pmccadapriv->role) { + case MCC_ROLE_STA: + case MCC_ROLE_GC: + pmccadapriv->order = 1; + pmccadapriv->mcc_duration = mcc_duration; + + rtw_hal_mcc_assign_tx_threshold(padapter); + /* assign used mac to avoid affecting RA */ + pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID; + + psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if (psta) { + /* combine AP/GO macid and mgmt queue macid to bitmap */ + pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid); + } else { + RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter)); + rtw_warn_on(1); + } + break; + case MCC_ROLE_AP: + case MCC_ROLE_GO: + pmccadapriv->order = 0; + /* total druation value equals interval */ + pmccadapriv->mcc_duration = mcc_interval - mcc_duration; + pmccadapriv->p2p_go_noa_ie_len = 0; /* not NoA attribute at init time */ + + rtw_hal_mcc_assign_tx_threshold(padapter); + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + pmccadapriv->mcc_macid_bitmap = 0; + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + pmccadapriv->mcc_macid_bitmap |= BIT(psta->cmn.mac_id); + } + + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + psta = rtw_get_bcmc_stainfo(padapter); + + if (psta != NULL) + pmccadapriv->mgmt_queue_macid = psta->cmn.mac_id; + else { + pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID; + RTW_INFO(FUNC_ADPT_FMT":bcmc station is NULL, use macid %d\n" + , FUNC_ADPT_ARG(padapter), pmccadapriv->mgmt_queue_macid); + } + + /* combine client macid and mgmt queue macid to bitmap */ + pmccadapriv->mcc_macid_bitmap |= BIT(pmccadapriv->mgmt_queue_macid); + break; + default: + RTW_INFO("Unknown role\n"); + rtw_warn_on(1); + break; + } + + } + + /* setting Null data parameters */ + if (pmccadapriv->role == MCC_ROLE_STA) { + pmccadapriv->null_early = 3; + pmccadapriv->null_rty_num= 5; + } else if (pmccadapriv->role == MCC_ROLE_GC) { + pmccadapriv->null_early = 2; + pmccadapriv->null_rty_num= 5; + } else { + pmccadapriv->null_early = 0; + pmccadapriv->null_rty_num= 0; } + RTW_INFO("********* "FUNC_ADPT_FMT" *********\n", FUNC_ADPT_ARG(padapter)); + RTW_INFO("order:%d\n", pmccadapriv->order); + RTW_INFO("role:%d\n", pmccadapriv->role); + RTW_INFO("mcc duration:%d\n", pmccadapriv->mcc_duration); + RTW_INFO("null_early:%d\n", pmccadapriv->null_early); + RTW_INFO("null_rty_num:%d\n", pmccadapriv->null_rty_num); + RTW_INFO("mgmt queue macid:%d\n", pmccadapriv->mgmt_queue_macid); + RTW_INFO("bitmap:0x%02x\n", pmccadapriv->mcc_macid_bitmap); + RTW_INFO("target tx bytes:%d\n", pmccadapriv->mcc_target_tx_bytes_to_port); + RTW_INFO("**********************************\n"); + pmccobjpriv->iface[pmccadapriv->order] = padapter; - RTW_INFO(FUNC_ADPT_FMT": order:%d, role:%d, mcc duration:%d, target tx bytes:%d, mgmt queue macid:%d, bitmap:0x%02x\n" - , FUNC_ADPT_ARG(padapter), pmccadapriv->order, pmccadapriv->role, pmccadapriv->mcc_duration - , pmccadapriv->mcc_target_tx_bytes_to_port, pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap); + } static void rtw_hal_clear_mcc_macid(PADAPTER padapter) @@ -441,6 +525,370 @@ static void rtw_hal_clear_mcc_macid(PADAPTER padapter) break; } } + +static void rtw_hal_mcc_rqt_tsf(PADAPTER padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + u8 cmd[H2C_MCC_RQT_TSF_LEN] = {0}; + + rtw_sctx_init(&pmccobjpriv->mcc_tsf_req_sctx, MCC_EXPIRE_TIME); + + SET_H2CCMD_MCC_RQT_TSFX(cmd, pmccobjpriv->iface[0]->hw_port); + SET_H2CCMD_MCC_RQT_TSFY(cmd, pmccobjpriv->iface[1]->hw_port); + + rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_RQT_TSF, H2C_MCC_RQT_TSF_LEN, cmd); + + if (!rtw_sctx_wait(&pmccobjpriv->mcc_tsf_req_sctx, __func__)) + RTW_INFO(FUNC_ADPT_FMT": wait for mcc tsf req C2H time out\n", FUNC_ADPT_ARG(padapter)); + +} + +static u8 rtw_hal_mcc_check_start_time_is_valid(PADAPTER padapter, u8 case_num, + u32 tsfdiff, s8 *upper_bound_0, s8 *lower_bound_0, s8 *upper_bound_1, s8 *lower_bound_1) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + u8 duration_0 = 0, duration_1 = 0; + s8 final_upper_bound = 0, final_lower_bound = 0; + u8 intersection = _FALSE; + u8 min_start_time = 5; + u8 max_start_time = 95; + + duration_0 = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration; + duration_1 = mccobjpriv->iface[1]->mcc_adapterpriv.mcc_duration; + + switch(case_num) { + case 1: + *upper_bound_0 = tsfdiff; + *lower_bound_0 = tsfdiff - duration_1; + *upper_bound_1 = 150 - duration_1; + *lower_bound_1= 0; + break; + case 2: + *upper_bound_0 = tsfdiff + 100; + *lower_bound_0 = tsfdiff + 100 - duration_1; + *upper_bound_1 = 150 - duration_1; + *lower_bound_1= 0; + break; + case 3: + *upper_bound_0 = tsfdiff + 50; + *lower_bound_0 = tsfdiff + 50 - duration_1; + *upper_bound_1 = 150 - duration_1; + *lower_bound_1= 0; + break; + case 4: + *upper_bound_0 = tsfdiff; + *lower_bound_0 = tsfdiff - duration_1; + *upper_bound_1 = 150 - duration_1; + *lower_bound_1= 0; + break; + case 5: + *upper_bound_0 = 200 - tsfdiff; + *lower_bound_0 = 200 - tsfdiff - duration_1; + *upper_bound_1 = 150 - duration_1; + *lower_bound_1= 0; + break; + case 6: + *upper_bound_0 = tsfdiff - 50; + *lower_bound_0 = tsfdiff - 50 - duration_1; + *upper_bound_1 = 150 - duration_1; + *lower_bound_1= 0; + break; + default: + RTW_ERR("[MCC] %s: error case number(%d\n)", __func__, case_num); + } + + + /* check Intersection or not */ + if ((*lower_bound_1 >= *upper_bound_0) || + (*lower_bound_0 >= *upper_bound_1)) + intersection = _FALSE; + else + intersection = _TRUE; + + if (intersection) { + if (*upper_bound_0 > *upper_bound_1) + final_upper_bound = *upper_bound_1; + else + final_upper_bound = *upper_bound_0; + + if (*lower_bound_0 > *lower_bound_1) + final_lower_bound = *lower_bound_0; + else + final_lower_bound = *lower_bound_1; + + mccobjpriv->start_time = (final_lower_bound + final_upper_bound) / 2; + + /* check start time less than 5ms, request by Pablo@SD1 */ + if (mccobjpriv->start_time <= min_start_time) { + mccobjpriv->start_time = 6; + if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) { + intersection = _FALSE; + goto exit; + } + } + + /* check start time less than 95ms */ + if (mccobjpriv->start_time >= max_start_time) { + mccobjpriv->start_time = 90; + if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) { + intersection = _FALSE; + goto exit; + } + } + } + +exit: + return intersection; +} + +static void rtw_hal_mcc_decide_duration(PADAPTER padapter) +{ + struct registry_priv *registry_par = &padapter->registrypriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + struct mcc_adapter_priv *mccadapriv = NULL, *mccadapriv_order0 = NULL, *mccadapriv_order1 = NULL; + _adapter *iface = NULL, *iface_order0 = NULL, *iface_order1 = NULL; + u8 duration = 0, i = 0, duration_time; + u8 mcc_interval = 150; + + iface_order0 = mccobjpriv->iface[0]; + iface_order1 = mccobjpriv->iface[1]; + mccadapriv_order0 = &iface_order0->mcc_adapterpriv; + mccadapriv_order1 = &iface_order1->mcc_adapterpriv; + + if (mccobjpriv->duration == 0) { + /* default */ + duration = 30;/*(%)*/ + RTW_INFO("%s: mccobjpriv->duration=0, use default value(%d)\n", + __FUNCTION__, duration); + } else { + duration = mccobjpriv->duration;/*(%)*/ + RTW_INFO("%s: mccobjpriv->duration=%d\n", + __FUNCTION__, duration); + } + + mccobjpriv->interval = mcc_interval; + mccobjpriv->mcc_stop_threshold = 2000 * 4 / 300 - 6; + /* convert % to ms, for primary adapter */ + duration_time = mccobjpriv->interval * duration / 100; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + + if (!iface) + continue; + + mccadapriv = &iface->mcc_adapterpriv; + + if (is_primary_adapter(iface)) + mccadapriv->mcc_duration = duration_time; + else + mccadapriv->mcc_duration = mccobjpriv->interval - duration_time; + } + + RTW_INFO("[MCC]" FUNC_ADPT_FMT " order 0 duration=%d\n", FUNC_ADPT_ARG(iface_order0), mccadapriv_order0->mcc_duration); + RTW_INFO("[MCC]" FUNC_ADPT_FMT " order 1 duration=%d\n", FUNC_ADPT_ARG(iface_order1), mccadapriv_order1->mcc_duration); +} + +static u8 rtw_hal_mcc_update_timing_parameters(PADAPTER padapter, u8 force_update) +{ + u8 need_update = _FALSE; + + /* for STA+STA, modify policy table */ + if (MSTATE_AP_STARTING_NUM(&mcc_mstate) == 0 + && MSTATE_AP_NUM(&mcc_mstate) == 0) { + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + struct mcc_adapter_priv *pmccadapriv = NULL; + _adapter *iface = NULL; + u64 tsf0 = 0, tsf1 = 0; + u32 beaconperiod_0 = 0, beaconperiod_1 = 0, tsfdiff = 0; + s8 upper_bound_0 = 0, lower_bound_0 = 0; + s8 upper_bound_1 = 0, lower_bound_1 = 0; + u8 valid = _FALSE; + u8 case_num = 1; + u8 i = 0; + + /* query TSF */ + rtw_hal_mcc_rqt_tsf(padapter); + + /* selecet policy table according TSF diff */ + tsf0 = pmccobjpriv->iface[0]->mcc_adapterpriv.tsf; + beaconperiod_0 = pmccobjpriv->iface[0]->mlmepriv.cur_network.network.Configuration.BeaconPeriod; + tsf0 = rtw_modular64(tsf0, (beaconperiod_0 * TU)); + + tsf1 = pmccobjpriv->iface[1]->mcc_adapterpriv.tsf; + beaconperiod_1 = pmccobjpriv->iface[1]->mlmepriv.cur_network.network.Configuration.BeaconPeriod; + tsf1 = rtw_modular64(tsf1, (beaconperiod_1 * TU)); + + if (tsf0 > tsf1) + tsfdiff = tsf0- tsf1; + else + tsfdiff = (tsf0 + beaconperiod_0 * TU) - tsf1; + + /* convert to ms */ + tsfdiff = (tsfdiff / TU); + + /* force update*/ + if (force_update) { + RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n", + pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf); + RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1); + RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n", + __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD); + pmccobjpriv->last_tsfdiff = tsfdiff; + need_update = _TRUE; + } else { + if (pmccobjpriv->last_tsfdiff > tsfdiff) { + /* last tsfdiff - current tsfdiff > THRESHOLD, update parameters */ + if (pmccobjpriv->last_tsfdiff > (tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) { + RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n", + pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf); + RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1); + RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n", + __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD); + + pmccobjpriv->last_tsfdiff = tsfdiff; + need_update = _TRUE; + } else { + need_update = _FALSE; + } + } else if (tsfdiff > pmccobjpriv->last_tsfdiff){ + /* current tsfdiff - last tsfdiff > THRESHOLD, update parameters */ + if (tsfdiff > (pmccobjpriv->last_tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) { + RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n", + pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf); + RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1); + RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n", + __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD); + + pmccobjpriv->last_tsfdiff = tsfdiff; + need_update = _TRUE; + } else { + need_update = _FALSE; + } + } else { + need_update = _FALSE; + } + } + + if (need_update == _FALSE) + goto exit; + + rtw_hal_mcc_decide_duration(padapter); + + if (tsfdiff <= 50) { + + /* RX TBTT 0 */ + case_num = 1; + valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff, + &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1); + + if (valid) + goto valid_result; + + /* RX TBTT 1 */ + case_num = 2; + valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff, + &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1); + + if (valid) + goto valid_result; + + /* RX TBTT 2 */ + case_num = 3; + valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff, + &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1); + + if (valid) + goto valid_result; + + if (valid == _FALSE) { + RTW_INFO("[MCC] do not find fit start time\n"); + RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n", + tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval); + + } + + } else { + + /* RX TBTT 0 */ + case_num = 4; + valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff, + &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1); + + if (valid) + goto valid_result; + + + /* RX TBTT 1 */ + case_num = 5; + valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff, + &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1); + + if (valid) + goto valid_result; + + + /* RX TBTT 2 */ + case_num = 6; + valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff, + &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1); + + if (valid) + goto valid_result; + + if (valid == _FALSE) { + RTW_INFO("[MCC] do not find fit start time\n"); + RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n", + tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval); + } + } + + + + valid_result: + RTW_INFO("********************\n"); + RTW_INFO("%s: case_num:%d, start time:%d\n", + __func__, case_num, pmccobjpriv->start_time); + RTW_INFO("%s: upper_bound_0:%d, lower_bound_0:%d\n", + __func__, upper_bound_0, lower_bound_0); + RTW_INFO("%s: upper_bound_1:%d, lower_bound_1:%d\n", + __func__, upper_bound_1, lower_bound_1); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface == NULL) + continue; + + pmccadapriv = &iface->mcc_adapterpriv; +#if 0 + if (pmccadapriv->order == 0) { + pmccadapriv->mcc_duration = mcc_duration; + } else if (pmccadapriv->order == 1) { + pmccadapriv->mcc_duration = mcc_interval - mcc_duration; + } else { + RTW_INFO("[MCC] not support >= 3 interface\n"); + rtw_warn_on(1); + } +#endif + RTW_INFO("********************\n"); + RTW_INFO(FUNC_ADPT_FMT": order:%d, role:%d\n", + FUNC_ADPT_ARG(iface), pmccadapriv->order, pmccadapriv->role); + RTW_INFO(FUNC_ADPT_FMT": mcc duration:%d, target tx bytes:%d\n", + FUNC_ADPT_ARG(iface), pmccadapriv->mcc_duration, pmccadapriv->mcc_target_tx_bytes_to_port); + RTW_INFO(FUNC_ADPT_FMT": mgmt queue macid:%d, bitmap:0x%02x\n", + FUNC_ADPT_ARG(iface), pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap); + RTW_INFO("********************\n"); + } + + } +exit: + return need_update; +} + static u8 rtw_hal_decide_mcc_role(PADAPTER padapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); @@ -449,6 +897,7 @@ static u8 rtw_hal_decide_mcc_role(PADAPTER padapter) struct wifidirect_info *pwdinfo = NULL; struct mlme_priv *pmlmepriv = NULL; u8 ret = _SUCCESS, i = 0; + u8 order = 1; for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -477,18 +926,22 @@ static u8 rtw_hal_decide_mcc_role(PADAPTER padapter) goto exit; } - if (ret == _SUCCESS) - rtw_hal_config_mcc_role_setting(iface); + if (ret == _SUCCESS) { + if (padapter == iface) { + /* current adapter is order 0 */ + rtw_hal_config_mcc_role_setting(iface, 0); + } else { + rtw_hal_config_mcc_role_setting(iface, order); + order ++; + } + } } + rtw_hal_mcc_update_timing_parameters(padapter, _TRUE); exit: return ret; } -static void rtw_hal_init_mcc_parameter(PADAPTER padapter) -{ -} - static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength) { u8 broadcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; @@ -510,9 +963,69 @@ static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength) *pLength = 22; } +/* avoid wrong information for power limit */ +void rtw_hal_mcc_upadate_chnl_bw(_adapter *padapter, u8 ch, u8 ch_offset, u8 bw, u8 print) +{ + + u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); + u8 cch_160, cch_80, cch_40, cch_20; + + center_ch = rtw_get_center_ch(ch, bw, ch_offset); + + if (bw == CHANNEL_WIDTH_80) { + if (center_ch > ch) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER; + else if (center_ch < ch) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER; + else + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + + /* set Channel */ + /* saved channel/bw info */ + rtw_set_oper_ch(padapter, ch); + rtw_set_oper_bw(padapter, bw); + rtw_set_oper_choffset(padapter, ch_offset); + + cch_80 = bw == CHANNEL_WIDTH_80 ? center_ch : 0; + cch_40 = bw == CHANNEL_WIDTH_40 ? center_ch : 0; + cch_20 = bw == CHANNEL_WIDTH_20 ? center_ch : 0; + + if (cch_80 != 0) + cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, chnl_offset80); + if (cch_40 != 0) + cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, ch_offset); + + + hal->cch_80 = cch_80; + hal->cch_40 = cch_40; + hal->cch_20 = cch_20; + hal->current_channel = center_ch; + hal->CurrentCenterFrequencyIndex1 = center_ch; + hal->current_channel_bw = bw; + hal->nCur40MhzPrimeSC = ch_offset; + hal->nCur80MhzPrimeSC = chnl_offset80; + hal->current_band_type = ch > 14 ? BAND_ON_5G:BAND_ON_2_4G; + + if (print) { + RTW_INFO(FUNC_ADPT_FMT" cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u), band:%s\n" + , FUNC_ADPT_ARG(padapter), center_ch, ch_width_str(bw) + , ch_offset, chnl_offset80 + , hal->cch_80, hal->cch_40, hal->cch_20 + , band_str(hal->current_band_type)); + } +} + +#ifdef DBG_RSVD_PAGE_CFG +#define RSVD_PAGE_CFG(ops, v1, v2, v3) \ + RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n", \ + ops, v1, v2, v3) +#endif + u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, - u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len, - RSVDPAGE_LOC *rsvd_page_loc) + u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num) { u32 len = 0; _adapter *iface = NULL; @@ -520,8 +1033,21 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); struct mlme_ext_info *pmlmeinfo = NULL; struct mlme_ext_priv *pmlmeext = NULL; - u8 ret = _SUCCESS, i = 0, order = 0, CurtPktPageNum = 0; + struct hal_com_data *hal = GET_HAL_DATA(adapter); + u8 ret = _SUCCESS, i = 0, j =0, order = 0, CurtPktPageNum = 0; u8 bssid[ETH_ALEN] = {0}; + u8 *start = NULL; + u8 path = RF_PATH_A; + + if (page_num) { +#ifdef CONFIG_MCC_MODE_V2 + if (!hal->RegIQKFWOffload) + RTW_WARN("[MCC] must enable FW IQK for New IC\n"); +#endif /* CONFIG_MCC_MODE_V2 */ + /* Null data(interface number) + power index(interface number) + 1 */ + *total_page_num += (2 * dvobj->iface_nums + 3); + goto exit; + } /* check proccess mcc start setting */ if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) { @@ -535,7 +1061,7 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, continue; order = iface->mcc_adapterpriv.order; - dvobj->mcc_objpriv.mcc_loc_rsvd_paga[order] = *page_num; + dvobj->mcc_objpriv.mcc_loc_rsvd_paga[order] = *total_page_num; switch (iface->mcc_adapterpriv.role) { case MCC_ROLE_STA: @@ -548,15 +1074,18 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, pmlmeinfo = &pmlmeext->mlmext_info; _rtw_memcpy(bssid, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + rtw_hal_construct_NullFunctionData(iface , &pframe[*index], &len, bssid, _FALSE, 0, 0, _FALSE); rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc], len, _FALSE, _FALSE, _FALSE); CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size); - *page_num += CurtPktPageNum; + *total_page_num += CurtPktPageNum; *index += (CurtPktPageNum * page_size); - *total_pkt_len = *index + len; + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("LocNull", CurtPktPageNum, *total_page_num, *index); + #endif break; case MCC_ROLE_AP: /* Bulid CTS */ @@ -569,15 +1098,311 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, len, _FALSE, _FALSE, _FALSE); CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size); - *page_num += CurtPktPageNum; + *total_page_num += CurtPktPageNum; *index += (CurtPktPageNum * page_size); - *total_pkt_len = *index + len; + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("LocCTS", CurtPktPageNum, *total_page_num, *index); + #endif break; case MCC_ROLE_GO: /* To DO */ break; } } + + for (i = 0; i < MAX_MCC_NUM; i++) { + u8 center_ch = 0, ch = 0, bw = 0, bw_offset = 0; + u8 power_index = 0; + u8 rate_array_sz = 0; + u8 *rates = NULL; + u8 rate = 0; + u8 shift = 0; + u32 power_index_4bytes = 0; + u8 total_rate = 0; + u8 *total_rate_offset = NULL; + + iface = pmccobjpriv->iface[i]; + pmlmeext = &iface->mlmeextpriv; + ch = pmlmeext->cur_channel; + bw = pmlmeext->cur_bwmode; + bw_offset = pmlmeext->cur_ch_offset; + center_ch = rtw_get_center_ch(ch, bw, bw_offset); + rtw_hal_mcc_upadate_chnl_bw(iface, ch, bw_offset, bw, _TRUE); + + start = &pframe[*index - tx_desc]; + _rtw_memset(start, 0, page_size); + pmccobjpriv->mcc_pwr_idx_rsvd_page[i] = *total_page_num; + RTW_INFO(ADPT_FMT" order:%d, pwr_idx_rsvd_page location[%d]: %d\n", + ADPT_ARG(iface), iface->mcc_adapterpriv.order, + i, pmccobjpriv->mcc_pwr_idx_rsvd_page[i]); + + total_rate_offset = start; + + for (path = RF_PATH_A; path < hal->NumTotalRFPath; ++path) { + total_rate = 0; + /* PATH A for 0~63 byte, PATH B for 64~127 byte*/ + if (path == RF_PATH_A) + start = total_rate_offset + 1; + else if (path == RF_PATH_B) + start = total_rate_offset + 64; + else { + RTW_INFO("[MCC] %s: unknow RF PATH(%d)\n", __func__, path); + break; + } + + /* CCK */ + if (ch <= 14) { + rate_array_sz = rates_by_sections[CCK].rate_num; + rates = rates_by_sections[CCK].rates; + for (j = 0; j < rate_array_sz; ++j) { + power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL); + rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]); + + shift = rate % 4; + if (shift == 0) { + *start = rate; + start++; + total_rate++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + #endif + } + + *start = power_index; + start++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + + + shift = rate % 4; + power_index_4bytes |= ((power_index & 0xff) << (shift * 8)); + if (shift == 3) { + rate = rate - 3; + RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate); + power_index_4bytes = 0; + total_rate++; + } + #endif + + } + } + + /* OFDM */ + rate_array_sz = rates_by_sections[OFDM].rate_num; + rates = rates_by_sections[OFDM].rates; + for (j = 0; j < rate_array_sz; ++j) { + power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL); + rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]); + + shift = rate % 4; + if (shift == 0) { + *start = rate; + start++; + total_rate++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + #endif + + } + + *start = power_index; + start++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + + shift = rate % 4; + power_index_4bytes |= ((power_index & 0xff) << (shift * 8)); + if (shift == 3) { + rate = rate - 3; + RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate); + power_index_4bytes = 0; + total_rate++; + } + #endif + } + + /* HT_MCS0_MCS7 */ + rate_array_sz = rates_by_sections[HT_MCS0_MCS7].rate_num; + rates = rates_by_sections[HT_MCS0_MCS7].rates; + for (j = 0; j < rate_array_sz; ++j) { + power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL); + rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]); + + shift = rate % 4; + if (shift == 0) { + *start = rate; + start++; + total_rate++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + #endif + + } + + *start = power_index; + start++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + + shift = rate % 4; + power_index_4bytes |= ((power_index & 0xff) << (shift * 8)); + if (shift == 3) { + rate = rate - 3; + RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate); + power_index_4bytes = 0; + total_rate++; + } + #endif + } + + /* HT_MCS8_MCS15 */ + rate_array_sz = rates_by_sections[HT_MCS8_MCS15].rate_num; + rates = rates_by_sections[HT_MCS8_MCS15].rates; + for (j = 0; j < rate_array_sz; ++j) { + power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL); + rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]); + + shift = rate % 4; + if (shift == 0) { + *start = rate; + start++; + total_rate++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + #endif + } + + *start = power_index; + start++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + + shift = rate % 4; + power_index_4bytes |= ((power_index & 0xff) << (shift * 8)); + if (shift == 3) { + rate = rate - 3; + RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate); + power_index_4bytes = 0; + total_rate++; + } + #endif + } + + /* VHT_1SSMCS0_1SSMCS9 */ + rate_array_sz = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rate_num; + rates = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rates; + for (j = 0; j < rate_array_sz; ++j) { + power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL); + rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]); + + shift = rate % 4; + if (shift == 0) { + *start = rate; + start++; + total_rate++; + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:0x%02x\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + #endif + } + *start = power_index; + start++; + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + + shift = rate % 4; + power_index_4bytes |= ((power_index & 0xff) << (shift * 8)); + if (shift == 3) { + rate = rate - 3; + RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate); + power_index_4bytes = 0; + total_rate++; + } + #endif + } + + /* VHT_2SSMCS0_2SSMCS9 */ + rate_array_sz = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rate_num; + rates = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rates; + for (j = 0; j < rate_array_sz; ++j) { + power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL); + rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]); + + shift = rate % 4; + if (shift == 0) { + *start = rate; + start++; + total_rate++; + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + #endif + } + *start = power_index; + start++; + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + + shift = rate % 4; + power_index_4bytes |= ((power_index & 0xff) << (shift * 8)); + if (shift == 3) { + rate = rate - 3; + RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate); + power_index_4bytes = 0; + total_rate++; + } + #endif + } + + } + /* total rate store in offset 0 */ + *total_rate_offset = total_rate; + +#ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("total_rate=%d\n", total_rate); + RTW_INFO(" ======================="ADPT_FMT"===========================\n", ADPT_ARG(iface)); + RTW_INFO_DUMP("\n", total_rate_offset, 128); + RTW_INFO(" ==================================================\n"); +#endif + + CurtPktPageNum = 1; + *total_page_num += CurtPktPageNum; + *index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("mcc_pwr_idx_rsvd_page", CurtPktPageNum, *total_page_num, *index); + #endif + } + exit: return ret; } @@ -614,23 +1439,17 @@ static void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter) { u8 cmd[H2C_MCC_LOCATION_LEN] = {0}, i = 0, order = 0; _adapter *iface = NULL; + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(cmd, _TRUE); + SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(cmd, hal->NumTotalRFPath); + for (order = 0; order < MAX_MCC_NUM; order++) { + iface = pmccobjpriv->iface[i]; - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (iface == NULL) - continue; - - order = iface->mcc_adapterpriv.order; - if (order >= H2C_MCC_LOCATION_LEN) { - RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n" - , FUNC_ADPT_ARG(padapter), order); - continue; - } - - SET_H2CCMD_MCC_RSVDPAGE_LOC((cmd + order), (pmccobjpriv->mcc_loc_rsvd_paga[order])); + SET_H2CCMD_MCC_RSVDPAGE_LOC((cmd + order), pmccobjpriv->mcc_loc_rsvd_paga[order]); + SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC ((cmd + order), pmccobjpriv->mcc_pwr_idx_rsvd_page[order]); } #ifdef CONFIG_MCC_MODE_DEBUG @@ -645,44 +1464,68 @@ static void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter) rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_LOCATION, H2C_MCC_LOCATION_LEN, cmd); } -static void rtw_hal_set_mcc_noa_cmd(PADAPTER padapter) +static void rtw_hal_set_mcc_time_setting_cmd(PADAPTER padapter) { struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); - u8 cmd[H2C_MCC_NOA_PARAM_LEN] = {0}; - u8 policy_idx = pmccobjpriv->policy_index; - u8 noa_fw_eable = 1; - u8 noa_tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX]; - u8 noa_start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX]; - u8 noa_interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX]; - u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX]; - u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX]; + u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0}; + u8 fw_eable = 1; u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME; - u8 i = 0; + - /* FW set NOA enable */ - SET_H2CCMD_MCC_NOA_FW_EN(cmd, noa_fw_eable); - /* TSF Sync offset */ - SET_H2CCMD_MCC_NOA_TSF_SYNC_OFFSET(cmd, noa_tsf_sync_offset); - /* NoA start time offset */ - SET_H2CCMD_MCC_NOA_START_TIME(cmd, (noa_start_time_offset + guard_offset0)); - /* NoA interval */ - SET_H2CCMD_MCC_NOA_INTERVAL(cmd, noa_interval); - /* Early time to inform driver by C2H before switch channel */ - SET_H2CCMD_MCC_EARLY_TIME(cmd, swchannel_early_time); + if (MSTATE_AP_STARTING_NUM(&mcc_mstate) == 0 + && MSTATE_AP_NUM(&mcc_mstate) == 0) + /* For STA+GC/STA+STA, TSF of GC/STA does not need to sync from TSF of other STA/GC */ + fw_eable = 0; + else + /* Only for STA+GO/STA+AP, TSF of AP/GO need to sync from TSF of STA */ + fw_eable = 1; + + if (fw_eable == 1) { + u8 policy_idx = pmccobjpriv->policy_index; + u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX]; + u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX]; + u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX]; + u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX]; + u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX]; + /* FW set enable */ + SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, fw_eable); + /* TSF Sync offset */ + SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset); + /* start time offset */ + SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0)); + /* interval */ + SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval); + /* Early time to inform driver by C2H before switch channel */ + SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time); + /* Port0 sync from Port1, not support multi-port */ + SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, HW_PORT1); + SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, HW_PORT0); + } else { + /* start time offset */ + SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, pmccobjpriv->start_time); + /* interval */ + SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, pmccobjpriv->interval); + /* Early time to inform driver by C2H before switch channel */ + SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time); + } #ifdef CONFIG_MCC_MODE_DEBUG - RTW_INFO("=========================\n"); - RTW_INFO("NoA:\n"); - for (i = 0; i < H2C_MCC_NOA_PARAM_LEN; i++) - pr_dbg("0x%x ", cmd[i]); - pr_dbg("\n"); - RTW_INFO("=========================\n"); + { + u8 i = 0; + + RTW_INFO("=========================\n"); + RTW_INFO("NoA:\n"); + for (i = 0; i < H2C_MCC_TIME_SETTING_LEN; i++) + pr_dbg("0x%x ", cmd[i]); + pr_dbg("\n"); + RTW_INFO("=========================\n"); + } #endif /* CONFIG_MCC_MODE_DEBUG */ - rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_NOA_PARAM, H2C_MCC_NOA_PARAM_LEN, cmd); + rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd); } static void rtw_hal_set_mcc_IQK_offload_cmd(PADAPTER padapter) @@ -773,36 +1616,181 @@ static void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter) u8 cmd[H2C_MCC_MACID_BITMAP_LEN] = {0}, i = 0, order = 0; u16 bitmap = 0; - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (iface == NULL) - continue; + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface == NULL) + continue; + + pmccadapriv = &iface->mcc_adapterpriv; + order = pmccadapriv->order; + bitmap = pmccadapriv->mcc_macid_bitmap; + + if (order >= (H2C_MCC_MACID_BITMAP_LEN/2)) { + RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n" + , FUNC_ADPT_ARG(padapter), order); + continue; + } + SET_H2CCMD_MCC_MACID_BITMAP_L((cmd + order * 2), (u8)(bitmap & 0xff)); + SET_H2CCMD_MCC_MACID_BITMAP_H((cmd + order * 2), (u8)((bitmap >> 8) & 0xff)); + } + +#ifdef CONFIG_MCC_MODE_DEBUG + RTW_INFO("=========================\n"); + RTW_INFO("MACID BITMAP: "); + for (i = 0; i < H2C_MCC_MACID_BITMAP_LEN; i++) + printk("0x%x ", cmd[i]); + printk("\n"); + RTW_INFO("=========================\n"); +#endif /* CONFIG_MCC_MODE_DEBUG */ + rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_MACID_BITMAP, H2C_MCC_MACID_BITMAP_LEN, cmd); +} + +#ifdef CONFIG_MCC_MODE_V2 +static u8 get_pri_ch_idx_by_adapter(u8 center_ch, u8 channel, u8 bw, u8 ch_offset40) +{ + u8 pri_ch_idx = 0, chnl_offset80 = 0; + + if (bw == CHANNEL_WIDTH_80) { + if (center_ch > channel) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER; + else if (center_ch < channel) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER; + else + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + + if (bw == CHANNEL_WIDTH_80) { + /* primary channel is at lower subband of 80MHz & 40MHz */ + if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER)) + pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ; + /* primary channel is at lower subband of 80MHz & upper subband of 40MHz */ + else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER)) + pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ; + /* primary channel is at upper subband of 80MHz & lower subband of 40MHz */ + else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER)) + pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ; + /* primary channel is at upper subband of 80MHz & upper subband of 40MHz */ + else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER)) + pri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ; + else { + if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER) + pri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ; + else if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER) + pri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ; + else + RTW_INFO("SCMapping: DONOT CARE Mode Setting\n"); + } + } else if (bw == CHANNEL_WIDTH_40) { + /* primary channel is at upper subband of 40MHz */ + if (ch_offset40== HAL_PRIME_CHNL_OFFSET_UPPER) + pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ; + /* primary channel is at lower subband of 40MHz */ + else if (ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) + pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ; + else + RTW_INFO("SCMapping: DONOT CARE Mode Setting\n"); + } + + return pri_ch_idx; +} + +static void rtw_hal_set_mcc_ctrl_cmd_v2(PADAPTER padapter, u8 stop) +{ + u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0; + u8 order = 0, totalnum = 0; + u8 center_ch = 0, pri_ch_idx = 0, bw = 0; + u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0; + u8 dis_sw_retry = 0, null_early_time=2, tsfx = 0, update_parm = 0; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + struct mlme_ext_priv *pmlmeext = NULL; + struct mlme_ext_info *pmlmeinfo = NULL; + _adapter *iface = NULL; + + RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = pmccobjpriv->iface[i]; + if (iface == NULL) + continue; + + if (stop) { + if (iface != padapter) + continue; + } + + + order = iface->mcc_adapterpriv.order; + if (!stop) + totalnum = dvobj->iface_nums; + else + totalnum = 0xff; /* 0xff means stop */ + + pmlmeext = &iface->mlmeextpriv; + center_ch = rtw_get_center_ch(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); + pri_ch_idx = get_pri_ch_idx_by_adapter(center_ch, pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); + bw = pmlmeext->cur_bwmode; + duration = iface->mcc_adapterpriv.mcc_duration; + role = iface->mcc_adapterpriv.role; - pmccadapriv = &iface->mcc_adapterpriv; - order = pmccadapriv->order; - bitmap = pmccadapriv->mcc_macid_bitmap; + incurch = _FALSE; + dis_sw_retry = _TRUE; - if (order >= (H2C_MCC_MACID_BITMAP_LEN/2)) { - RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n" - , FUNC_ADPT_ARG(padapter), order); - continue; + /* STA/GC TX NULL data to inform AP/GC for ps mode */ + switch (role) { + case MCC_ROLE_GO: + case MCC_ROLE_AP: + distxnull = MCC_DISABLE_TX_NULL; + break; + case MCC_ROLE_GC: + set_channel_bwmode(iface, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + distxnull = MCC_ENABLE_TX_NULL; + break; + case MCC_ROLE_STA: + distxnull = MCC_ENABLE_TX_NULL; + break; } - SET_H2CCMD_MCC_MACID_BITMAP_L((cmd + order * 2), (u8)(bitmap & 0xff)); - SET_H2CCMD_MCC_MACID_BITMAP_H((cmd + order * 2), (u8)((bitmap >> 8) & 0xff)); - } + + null_early_time = iface->mcc_adapterpriv.null_early; + + c2hrpt = MCC_C2H_REPORT_ALL_STATUS; + tsfx = iface->hw_port; + update_parm = 0; + + SET_H2CCMD_MCC_CTRL_V2_ORDER(cmd, order); + SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(cmd, totalnum); + SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(cmd, center_ch); + SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(cmd, pri_ch_idx); + SET_H2CCMD_MCC_CTRL_V2_BW(cmd, bw); + SET_H2CCMD_MCC_CTRL_V2_DURATION(cmd, duration); + SET_H2CCMD_MCC_CTRL_V2_ROLE(cmd, role); + SET_H2CCMD_MCC_CTRL_V2_INCURCH(cmd, incurch); + SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(cmd, dis_sw_retry); + SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(cmd, distxnull); + SET_H2CCMD_MCC_CTRL_V2_C2HRPT(cmd, c2hrpt); + SET_H2CCMD_MCC_CTRL_V2_TSFX(cmd, tsfx); + SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(cmd, null_early_time); + SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(cmd, update_parm); #ifdef CONFIG_MCC_MODE_DEBUG - RTW_INFO("=========================\n"); - RTW_INFO("MACID BITMAP: "); - for (i = 0; i < H2C_MCC_MACID_BITMAP_LEN; i++) - pr_dbg("0x%x ", cmd[i]); - pr_dbg("\n"); - RTW_INFO("=========================\n"); + RTW_INFO("=========================\n"); + RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface)); + RTW_INFO("cmd[0]:0x%02x\n", cmd[0]); + RTW_INFO("cmd[1]:0x%02x\n", cmd[1]); + RTW_INFO("cmd[2]:0x%02x\n", cmd[2]); + RTW_INFO("cmd[3]:0x%02x\n", cmd[3]); + RTW_INFO("cmd[4]:0x%02x\n", cmd[4]); + RTW_INFO("cmd[5]:0x%02x\n", cmd[5]); + RTW_INFO("cmd[6]:0x%02x\n", cmd[6]); + RTW_INFO("=========================\n"); #endif /* CONFIG_MCC_MODE_DEBUG */ - rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_MACID_BITMAP, H2C_MCC_MACID_BITMAP_LEN, cmd); + + rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL_V2, H2C_MCC_CTRL_LEN, cmd); + } } -static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop) +#else +static void rtw_hal_set_mcc_ctrl_cmd_v1(PADAPTER padapter, u8 stop) { u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0; u8 order = 0, totalnum = 0, chidx = 0, bw = 0, bw40sc = 0, bw80sc = 0; @@ -906,10 +1894,22 @@ static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop) rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL, H2C_MCC_CTRL_LEN, cmd); } } +#endif + +static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop) +{ + #ifdef CONFIG_MCC_MODE_V2 + /* new cmd 0x17 */ + rtw_hal_set_mcc_ctrl_cmd_v2(padapter, stop); + #else + /* old cmd 0x18 */ + rtw_hal_set_mcc_ctrl_cmd_v1(padapter, stop); + #endif +} static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status) { - u8 ret = _SUCCESS; + u8 ret = _SUCCESS, enable_tsf_auto_sync = _FALSE; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); @@ -925,6 +1925,9 @@ static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status) goto exit; } + /* update mi_state to decide STA+STA or AP+STA */ + rtw_mi_status(padapter, &mcc_mstate); + /* configure mcc switch channel setting */ rtw_hal_config_mcc_switch_channel_setting(padapter); @@ -943,15 +1946,20 @@ static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status) rtw_hal_set_mcc_rsvdpage_cmd(padapter); } - /* configure NoA setting */ - rtw_hal_set_mcc_noa_cmd(padapter); + /* configure time setting */ + rtw_hal_set_mcc_time_setting_cmd(padapter); +#ifndef CONFIG_MCC_MODE_V2 /* IQK value offload */ rtw_hal_set_mcc_IQK_offload_cmd(padapter); +#endif /* set mac id to fw */ rtw_hal_set_mcc_macid_cmd(padapter); + /* disable tsf auto sync */ + rtw_hal_set_hwreg(padapter, HW_VAR_TSF_AUTO_SYNC, &enable_tsf_auto_sync); + /* set mcc parameter */ rtw_hal_set_mcc_ctrl_cmd(padapter, _FALSE); @@ -1010,8 +2018,12 @@ static void rtw_hal_mcc_status_hdl(PADAPTER padapter, u8 status) static void rtw_hal_mcc_stop_posthdl(PADAPTER padapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); _adapter *iface = NULL; + PHAL_DATA_TYPE hal; + struct dm_struct *p_dm_odm; u8 i = 0; + u8 enable_rx_bar = _FALSE; for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -1025,14 +2037,38 @@ static void rtw_hal_mcc_stop_posthdl(PADAPTER padapter) if (iface->mcc_adapterpriv.role == MCC_ROLE_GO) rtw_hal_mcc_remove_go_p2p_ie(iface); + +#ifdef CONFIG_TDLS + if (MLME_IS_STA(iface)) { + if (iface->mcc_adapterpriv.backup_tdls_en) { + rtw_enable_tdls_func(iface); + RTW_INFO("%s: Disable MCC, Enable TDLS\n", __func__); + iface->mcc_adapterpriv.backup_tdls_en = _FALSE; + } + } +#endif /* CONFIG_TDLS */ } + + hal = GET_HAL_DATA(padapter); + p_dm_odm = &hal->odmpriv; + phydm_dm_early_init(p_dm_odm); + + /* force switch channel */ + hal->current_channel = 0; + hal->current_channel_bw = CHANNEL_WIDTH_MAX; } static void rtw_hal_mcc_start_posthdl(PADAPTER padapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); _adapter *iface = NULL; + PHAL_DATA_TYPE hal; + struct dm_struct *p_dm_odm; + struct _hal_rf_ *p_rf; + u32 support_ability = 0; u8 i = 0; + u8 enable_rx_bar = _TRUE; for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -1041,7 +2077,23 @@ static void rtw_hal_mcc_start_posthdl(PADAPTER padapter) iface->mcc_adapterpriv.mcc_tx_bytes_from_kernel = 0; iface->mcc_adapterpriv.mcc_last_tx_bytes_from_kernel = 0; iface->mcc_adapterpriv.mcc_tx_bytes_to_port = 0; + +#ifdef CONFIG_TDLS + if (MLME_IS_STA(iface)) { + if (rtw_is_tdls_enabled(iface)) { + iface->mcc_adapterpriv.backup_tdls_en = _TRUE; + rtw_disable_tdls_func(iface, _TRUE); + RTW_INFO("%s: Enable MCC, Disable TDLS\n", __func__); + } + } +#endif /* CONFIG_TDLS */ } + + hal = GET_HAL_DATA(padapter); + p_dm_odm = &hal->odmpriv; + p_rf = &(p_dm_odm->rf_table); + mccobjpriv->backup_phydm_ability = p_rf->rf_supportability; + p_rf->rf_supportability = p_rf->rf_supportability & (~HAL_RF_TX_PWR_TRACK) & (~HAL_RF_IQK); } /* @@ -1075,6 +2127,7 @@ static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status) if (ret == _SUCCESS) { RTW_INFO(FUNC_ADPT_FMT": mcc start sucecssfully\n", FUNC_ADPT_ARG(padapter)); + rtw_hal_mcc_status_hdl(padapter, status); rtw_hal_mcc_start_posthdl(padapter); } } else { @@ -1090,13 +2143,12 @@ static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status) RTW_INFO(FUNC_ADPT_FMT": wait for mcc stop C2H time out\n", FUNC_ADPT_ARG(padapter)); else { ret = _SUCCESS; + rtw_hal_mcc_status_hdl(padapter, status); rtw_hal_mcc_stop_posthdl(padapter); } } exit: - - rtw_hal_mcc_status_hdl(padapter, status); /* clear mcc status */ rtw_hal_clear_mcc_status(padapter , MCC_STATUS_PROCESS_MCC_START_SETTING | MCC_STATUS_PROCESS_MCC_STOP_SETTING); @@ -1152,6 +2204,12 @@ static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter) } } + if (cur_iface == NULL || next_iface == NULL) { + RTW_ERR("cur_iface=%p,next_iface=%p\n", cur_iface, next_iface); + rtw_warn_on(1); + return; + } + /* check other interface tx busy traffic or not under every 2 switch channel notify(Mbits/100ms) */ if (cnt == 2) { cur_mccadapriv->mcc_tp = (cur_mccadapriv->mcc_tx_bytes_from_kernel @@ -1255,6 +2313,31 @@ static void rtw_hal_mcc_update_noa_start_time_hdl(PADAPTER padapter, u8 buflen, } +static void rtw_hal_mcc_rpt_tsf_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); + struct submit_ctx *mcc_tsf_req_sctx = &pmccobjpriv->mcc_tsf_req_sctx; + struct mcc_adapter_priv *pmccadapriv = NULL; + u8 iface_num = pdvobjpriv->iface_nums; + static u8 order = 0; + + pmccadapriv = &pmccobjpriv->iface[order]->mcc_adapterpriv; + pmccadapriv->tsf = RTW_GET_LE64(tmpBuf + 2); + + + if (0) { + RTW_INFO("TSF(order:%d):%llu\n", pmccadapriv->order, pmccadapriv->tsf); + } + + if (pmccadapriv->order == (iface_num - 1)) { + rtw_sctx_done(&mcc_tsf_req_sctx); + order = 0; + } else + order ++; + +} + /** * rtw_hal_mcc_c2h_handler - mcc c2h handler */ @@ -1264,6 +2347,8 @@ void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf) struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; struct submit_ctx *mcc_sctx = &pmccobjpriv->mcc_sctx; + _adapter *cur_adapter = NULL; + u8 cur_ch = 0, cur_bw = 0, cur_ch_offset = 0; _irqL irqL; /* RTW_INFO("[length]=%d, [C2H data]="MAC_FMT"\n", buflen, MAC_ARG(tmpBuf)); */ @@ -1274,19 +2359,32 @@ void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf) } pmccobjpriv->mcc_c2h_status = tmpBuf[0]; + pmccobjpriv->current_order = tmpBuf[1]; + cur_adapter = pmccobjpriv->iface[pmccobjpriv->current_order]; + cur_ch = cur_adapter->mlmeextpriv.cur_channel; + cur_bw = cur_adapter->mlmeextpriv.cur_bwmode; + cur_ch_offset = cur_adapter->mlmeextpriv.cur_ch_offset; + rtw_set_oper_ch(cur_adapter, cur_ch); + rtw_set_oper_bw(cur_adapter, cur_bw); + rtw_set_oper_choffset(cur_adapter, cur_ch_offset); + + if (0) + RTW_INFO("%d,order:%d,TSF:0x%llx\n", tmpBuf[0], tmpBuf[1], RTW_GET_LE64(tmpBuf + 2)); + switch (pmccobjpriv->mcc_c2h_status) { case MCC_RPT_SUCCESS: - pdvobjpriv->oper_channel = tmpBuf[1]; _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL); pmccobjpriv->cur_mcc_success_cnt++; + rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _FALSE); _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL); break; case MCC_RPT_TXNULL_FAIL: RTW_INFO("[MCC] TXNULL FAIL\n"); break; case MCC_RPT_STOPMCC: - RTW_INFO("[MCC] MCC stop (time:%d)\n", rtw_get_current_time()); + RTW_INFO("[MCC] MCC stop\n"); pmccobjpriv->mcc_c2h_status = MCC_RPT_STOPMCC; + rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _TRUE); rtw_sctx_done(&mcc_sctx); break; case MCC_RPT_READY: @@ -1303,18 +2401,103 @@ void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf) rtw_sctx_done(&mcc_sctx); break; case MCC_RPT_SWICH_CHANNEL_NOTIFY: - pdvobjpriv->oper_channel = tmpBuf[1]; rtw_hal_mcc_sw_ch_fw_notify_hdl(padapter); break; case MCC_RPT_UPDATE_NOA_START_TIME: rtw_hal_mcc_update_noa_start_time_hdl(padapter, buflen, tmpBuf); break; + case MCC_RPT_TSF: + _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL); + rtw_hal_mcc_rpt_tsf_hdl(padapter, buflen, tmpBuf); + _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL); + break; default: /* RTW_INFO("[MCC] Other MCC status(%d)\n", pmccobjpriv->mcc_c2h_status); */ break; } } +void rtw_hal_mcc_update_parameter(PADAPTER padapter, u8 force_update) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0}; + u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME; + + rtw_mi_status(padapter, &mcc_mstate); + + if (MSTATE_AP_NUM(&mcc_mstate) == 0) { + u8 need_update = _FALSE; + u8 start_time_offset = 0, interval = 0, duration = 0; + + need_update = rtw_hal_mcc_update_timing_parameters(padapter, force_update); + + if (need_update == _FALSE) + return; + + start_time_offset = pmccobjpriv->start_time; + interval = pmccobjpriv->interval; + duration = pmccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration; + + SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, start_time_offset); + SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval); + SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time); + SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE); + SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, duration); + } else { + u8 policy_idx = pmccobjpriv->policy_index; + u8 duration = mcc_switch_channel_policy_table[policy_idx][MCC_DURATION_IDX]; + u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX]; + u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX]; + u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX]; + u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX]; + u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX]; + u8 order0_duration = 0; + u8 i = 0; + + RTW_INFO("%s: policy_idx=%d\n", __func__, policy_idx); + + /* GO/AP is order 0, GC/STA is order 1 */ + order0_duration = pmccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration = interval - duration; + pmccobjpriv->iface[1]->mcc_adapterpriv.mcc_duration = duration; + + /* update IE */ + for (i = 0; i < dvobj->iface_nums; i++) { + PADAPTER iface = NULL; + struct mcc_adapter_priv *mccadapriv = NULL; + + iface = dvobj->padapters[i]; + if (iface == NULL) + continue; + + mccadapriv = &iface->mcc_adapterpriv; + if (mccadapriv == NULL) + continue; + + if (mccadapriv->role == MCC_ROLE_GO) + rtw_hal_mcc_update_go_p2p_ie(iface); + } + + /* update H2C cmd */ + /* FW set enable */ + SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, _TRUE); + /* TSF Sync offset */ + SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset); + /* start time offset */ + SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0)); + /* interval */ + SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval); + /* Early time to inform driver by C2H before switch channel */ + SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time); + /* Port0 sync from Port1, not support multi-port */ + SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, HW_PORT1); + SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, HW_PORT0); + SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE); + SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, order0_duration); + } + + rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd); +} /** * rtw_hal_mcc_sw_status_check - check mcc swich channel status @@ -1325,7 +2508,11 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter) struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - u8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL; + _adapter *iface = NULL; + u8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL, threshold = 0; + u8 policy_idx = pmccobjpriv->policy_index; + u8 noa_enable = _FALSE; + u8 i = 0; _irqL irqL; /* #define MCC_RESTART 1 */ @@ -1333,10 +2520,26 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter) if (!MCC_EN(padapter)) return; + rtw_mi_status(padapter, &mcc_mstate); + _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { + /* check noa enable or not */ + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) { + noa_enable = _TRUE; + break; + } + } + + if (!noa_enable && MSTATE_AP_NUM(&mcc_mstate) == 0) + rtw_hal_mcc_update_parameter(padapter, _FALSE); + + threshold = pmccobjpriv->mcc_stop_threshold; + if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) { rtw_warn_on(1); RTW_INFO("PS mode is not active under mcc, force exit ps mode\n"); @@ -1353,7 +2556,7 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter) else diff_cnt = cur_cnt - prev_cnt; - if (diff_cnt < 30) { + if (diff_cnt < threshold) { pmccobjpriv->mcc_tolerance_time--; RTW_INFO("%s: diff_cnt:%d, tolerance_time:%d\n", __func__, diff_cnt, pmccobjpriv->mcc_tolerance_time); @@ -1427,6 +2630,12 @@ u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset) break; case MCC_ROLE_STA: case MCC_ROLE_GC: + if (dvobj->padapters[i] != padapter) { + *ch = pmlmeext->cur_channel; + *bw = pmlmeext->cur_bwmode; + *offset = pmlmeext->cur_ch_offset; + need_ch_setting_union = _FALSE; + } break; default: RTW_INFO("unknown role\n"); @@ -1479,13 +2688,14 @@ inline void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len) struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { pmccadapriv->mcc_tx_bytes_to_port += len; if (0) RTW_INFO("%s(order:%d): mcc tx bytes to port:%d, mcc target tx bytes to port:%d\n" , __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_to_port , pmccadapriv->mcc_target_tx_bytes_to_port); } + } } /** @@ -1512,6 +2722,37 @@ inline u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter) return _FALSE; } +static void rtw_hal_mcc_assign_scan_flag(PADAPTER padapter, u8 scan_done) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + _adapter *iface = NULL; + struct mlme_ext_priv *pmlmeext = NULL; + u8 i = 0, flags; + + if (!MCC_EN(padapter)) + return; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + pmlmeext = &iface->mlmeextpriv; + if (is_client_associated_to_ap(iface)) { + flags = mlmeext_scan_backop_flags_sta(pmlmeext); + if (scan_done) { + if (mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) { + flags &= ~SS_BACKOP_EN; + mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags); + } + } else { + if (!mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) { + flags |= SS_BACKOP_EN; + mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags); + } + } + + } + } +} + /** * rtw_hal_set_mcc_setting_scan_start - setting mcc under scan start * @padapter: the adapter to be setted @@ -1528,8 +2769,7 @@ u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter) if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) { if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_SCAN_START); - /* issue null data to all station connected to AP before scan */ - rtw_hal_mcc_issue_null_data(padapter, 0, 1); + rtw_hal_mcc_assign_scan_flag(padapter, 0); } } _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); @@ -1552,9 +2792,10 @@ u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter) _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) - ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_SCAN_DONE); - + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) { + rtw_hal_mcc_assign_scan_flag(padapter, 1); + ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_SCAN_DONE); + } _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); } @@ -1651,9 +2892,9 @@ u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter) _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT); _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); - } } } + } return ret; } @@ -1676,12 +2917,15 @@ u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw if (chbw_allow == _FALSE) { struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + /* issue null data to other interface connected to AP */ + rtw_hal_mcc_issue_null_data(padapter, chbw_allow, _TRUE); + *ch = pmlmeext->cur_channel; *bw = pmlmeext->cur_bwmode; *offset = pmlmeext->cur_ch_offset; RTW_INFO(FUNC_ADPT_FMT" en_mcc:%d(%d,%d,%d,)\n" - , FUNC_ADPT_ARG(padapter), padapter->registrypriv.en_mcc + , FUNC_ADPT_ARG(padapter), MCC_EN(padapter) , *ch, *bw, *offset); ret = _SUCCESS; } @@ -1716,9 +2960,13 @@ void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj) u8 i = 0; /* regpriv is common for all adapter */ - adapter = dvobj->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(dvobj); RTW_PRINT_SEL(sel, "**********************************************\n"); + RTW_PRINT_SEL(sel, "en_mcc:%d\n", MCC_EN(adapter)); + RTW_PRINT_SEL(sel, "primary adapter("ADPT_FMT") duration:%d%c\n", + ADPT_ARG(dvobj_get_primary_adapter(dvobj)), pmccobjpriv->duration, 37); + RTW_PRINT_SEL(sel, "runtime duration:%s\n", pmccobjpriv->enable_runtime_duration ? "enable":"disable"); for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if (!iface) @@ -1727,6 +2975,8 @@ void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj) regpriv = &iface->registrypriv; pmccadapriv = &iface->mcc_adapterpriv; if (pmccadapriv) { + u8 p2p_ps_mode = iface->wdinfo.p2p_ps_mode; + RTW_PRINT_SEL(sel, "adapter mcc info:\n"); RTW_PRINT_SEL(sel, "ifname:%s\n", ADPT_ARG(iface)); RTW_PRINT_SEL(sel, "order:%d\n", pmccadapriv->order); @@ -1734,9 +2984,9 @@ void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj) RTW_PRINT_SEL(sel, "target tx bytes:%d\n", pmccadapriv->mcc_target_tx_bytes_to_port); RTW_PRINT_SEL(sel, "current TP:%d\n", pmccadapriv->mcc_tp); RTW_PRINT_SEL(sel, "mgmt queue macid:%d\n", pmccadapriv->mgmt_queue_macid); - RTW_PRINT_SEL(sel, "macid bitmap:0x%02x\n\n", pmccadapriv->mcc_macid_bitmap); + RTW_PRINT_SEL(sel, "macid bitmap:0x%02x\n", pmccadapriv->mcc_macid_bitmap); + RTW_PRINT_SEL(sel, "P2P NoA:%s\n\n", p2p_ps_mode == P2P_PS_NOA ? "enable":"disable"); RTW_PRINT_SEL(sel, "registry data:\n"); - RTW_PRINT_SEL(sel, "en_mcc:%d\n", regpriv->en_mcc); RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_ap_bw20_target_tx_tp); RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", regpriv->rtw_mcc_ap_bw40_target_tx_tp); RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_ap_bw80_target_tx_tp); @@ -1807,7 +3057,7 @@ void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); _adapter *iface = NULL; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); u8 i = 0; if (!MCC_EN(padapter)) @@ -1824,11 +3074,22 @@ void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode) /* issue null data to inform ap station will leave */ if (is_client_associated_to_ap(iface)) { struct mlme_ext_priv *mlmeext = &iface->mlmeextpriv; + struct mlme_ext_info *mlmeextinfo = &mlmeext->mlmext_info; u8 ch = mlmeext->cur_channel; u8 bw = mlmeext->cur_bwmode; u8 offset = mlmeext->cur_ch_offset; + struct sta_info *sta = rtw_get_stainfo(&iface->stapriv, get_my_bssid(&(mlmeextinfo->network))); + + if (!sta) + continue; + + set_channel_bwmode(iface, ch, offset, bw); + + if (ps_mode) + rtw_hal_macid_sleep(iface, sta->cmn.mac_id); + else + rtw_hal_macid_wakeup(iface, sta->cmn.mac_id); - set_channel_bwmode(iface, ch, bw, offset); issue_nulldata(iface, NULL, ps_mode, 3, 50); } } @@ -1870,4 +3131,179 @@ void rtw_hal_dump_mcc_policy_table(void *sel) } } +void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add) +{ + struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + + if (!MCC_EN(padapter)) + return; + + if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + return; + + if (pmccadapriv->role == MCC_ROLE_GC || pmccadapriv->role == MCC_ROLE_STA) + return; + + if (mac_id < 0) { + RTW_WARN("%s: mac_id < 0(%d)\n", __func__, mac_id); + return; + } + + RTW_INFO(ADPT_FMT" %s macid=%d, ori mcc_macid_bitmap=0x%08x\n" + , ADPT_ARG(padapter), add ? "add" : "clear" + , mac_id, pmccadapriv->mcc_macid_bitmap); + + if (add) + pmccadapriv->mcc_macid_bitmap |= BIT(mac_id); + else + pmccadapriv->mcc_macid_bitmap &= ~(BIT(mac_id)); + + rtw_hal_set_mcc_macid_cmd(padapter); +} + +void rtw_hal_mcc_process_noa(PADAPTER padapter) +{ + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + + if (!MCC_EN(padapter)) + return; + + if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + return; + + if (!MLME_IS_GC(padapter)) + return; + + switch(pwdinfo->p2p_ps_mode) { + case P2P_PS_NONE: + RTW_INFO("[MCC] Disable NoA under MCC\n"); + rtw_hal_mcc_update_parameter(padapter, _TRUE); + break; + case P2P_PS_NOA: + RTW_INFO("[MCC] Enable NoA under MCC\n"); + break; + default: + break; + + } +} + +void rtw_hal_mcc_parameter_init(PADAPTER padapter) +{ + if (!padapter->registrypriv.en_mcc) + return; + + if (is_primary_adapter(padapter)) { + SET_MCC_EN_FLAG(padapter, padapter->registrypriv.en_mcc); + SET_MCC_DURATION(padapter, padapter->registrypriv.rtw_mcc_duration); + SET_MCC_RUNTIME_DURATION(padapter, padapter->registrypriv.rtw_mcc_enable_runtime_duration); + } +} + + +u8 rtw_set_mcc_duration_hdl(PADAPTER adapter, u8 type, const u8 *val) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + _adapter *iface = NULL; + u8 duration = 50; + u8 ret = _SUCCESS, noa_enable = _FALSE, i = 0; + + if (!mccobjpriv->enable_runtime_duration) + goto exit; + +#ifdef CONFIG_P2P_PS + /* check noa enable or not */ + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) { + noa_enable = _TRUE; + break; + } + } +#endif /* CONFIG_P2P_PS */ + + + + if (type == MCC_DURATION_MAPPING) { + switch (*val) { + /* 0 = fair scheduling */ + case 0: + mccobjpriv->duration= 40; + mccobjpriv->policy_index = 2; + mccobjpriv->mchan_sched_mode = MCC_FAIR_SCHEDULE; + break; + /* 1 = favor STA */ + case 1: + mccobjpriv->duration= 70; + mccobjpriv->policy_index = 1; + mccobjpriv->mchan_sched_mode = MCC_FAVOE_STA; + break; + /* 2 = favor P2P*/ + case 2: + default: + mccobjpriv->duration= 30; + mccobjpriv->policy_index = 0; + mccobjpriv->mchan_sched_mode = MCC_FAVOE_P2P; + break; + } + } else { + mccobjpriv->duration = *val; + rtw_hal_mcc_update_policy_table(adapter); + } + + /* only update sw parameter under MCC + it will be force update during */ + if (noa_enable) + goto exit; + + if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) + rtw_hal_mcc_update_parameter(adapter, _TRUE); +exit: + return ret; +} + +u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + u8 *mcc_duration = NULL; + u8 res = _FAIL; + + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmdobj == NULL) + goto exit; + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + goto exit; + } + + mcc_duration = rtw_zmalloc(sizeof(u8)); + if (mcc_duration == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = MCC_SET_DURATION_WK_CID; + pdrvextra_cmd_parm->type = type; + pdrvextra_cmd_parm->size = 1; + pdrvextra_cmd_parm->pbuf = mcc_duration; + + _rtw_memcpy(mcc_duration, &val, 1); + + init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + +exit: + return res; +} + #endif /* CONFIG_MCC_MODE */ diff --git a/hal/hal_mp.c b/hal/hal_mp.c index 1cc498a..8616dcb 100644 --- a/hal/hal_mp.c +++ b/hal/hal_mp.c @@ -78,34 +78,34 @@ void hal_mpt_SwitchRfSetting(PADAPTER pAdapter) /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/ if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) && (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) { - pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0); - pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0); + pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0); + pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0); if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); } else { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD); + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD); } } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/ if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ } else { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ } } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A); + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B); } } s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); if (!netif_running(padapter->pnetdev)) { @@ -126,7 +126,7 @@ s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable) void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control; @@ -308,9 +308,9 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) void hal_mpt_SetChannel(PADAPTER pAdapter) { - u8 eRFPath; + enum rf_path eRFPath; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); struct mp_priv *pmp = &pAdapter->mppriv; u8 channel = pmp->channel; u8 bandwidth = pmp->bandwidth; @@ -319,7 +319,14 @@ void hal_mpt_SetChannel(PADAPTER pAdapter) pHalData->bSwChnl = _TRUE; pHalData->bSetChnlBW = _TRUE; - rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); + + if (bandwidth > 0) { + if ((channel >= 3 && channel <= 11) || (channel >= 42 && channel <= 171)) + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, pmp->prime_channel_offset); + else + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); + } else + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14); @@ -339,7 +346,14 @@ void hal_mpt_SetBandwidth(PADAPTER pAdapter) pHalData->bSwChnl = _TRUE; pHalData->bSetChnlBW = _TRUE; - rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); + + if (bandwidth > 0) { + if ((channel >= 3 && channel <= 11) || (channel >= 42 && channel <= 171)) + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, pmp->prime_channel_offset); + else + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); + } else + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); hal_mpt_SwitchRfSetting(pAdapter); } @@ -351,16 +365,16 @@ void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower) u4Byte TxAGC = 0, pwr = 0; u1Byte rf; - pwr = pTxPower[ODM_RF_PATH_A]; + pwr = pTxPower[RF_PATH_A]; if (pwr < 0x3f) { TxAGC = (pwr << 16) | (pwr << 8) | (pwr); - phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]); + phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]); phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); } - pwr = pTxPower[ODM_RF_PATH_B]; + pwr = pTxPower[RF_PATH_B]; if (pwr < 0x3f) { TxAGC = (pwr << 16) | (pwr << 8) | (pwr); - phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]); + phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]); phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC); } } @@ -412,12 +426,12 @@ mpt_SetTxPower( HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); u1Byte path = 0 , i = 0, MaxRate = MGN_6M; - u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_B; + u1Byte StartPath = RF_PATH_A, EndPath = RF_PATH_B; if (IS_HARDWARE_TYPE_8814A(pAdapter)) - EndPath = ODM_RF_PATH_D; + EndPath = RF_PATH_D; else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) - EndPath = ODM_RF_PATH_A; + EndPath = RF_PATH_A; switch (Rate) { case MPT_CCK: { @@ -501,15 +515,15 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; - if (pHalData->rf_chip < RF_TYPE_MAX) { + if (pHalData->rf_chip < RF_CHIP_MAX) { if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) { - u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B); + u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (RF_PATH_A) : (RF_PATH_B); RTW_INFO("===> MPT_ProSetTxPower: Old\n"); @@ -525,7 +539,7 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter) } } else - RTW_INFO("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip); + RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip); odm_clear_txpowertracking_state(pDM_Odm); } @@ -544,24 +558,24 @@ void hal_mpt_SetDataRate(PADAPTER pAdapter) #ifdef CONFIG_RTL8723B if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) { if (IS_CCK_RATE(DataRate)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6); + if (pMptCtx->mpt_rf_path == RF_PATH_A) + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6); else - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6); } else { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE); + if (pMptCtx->mpt_rf_path == RF_PATH_A) + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE); else - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE); } } if ((IS_HARDWARE_TYPE_8723BS(pAdapter) && ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE); + if (pMptCtx->mpt_rf_path == RF_PATH_A) + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE); else - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE); } #endif } @@ -574,15 +588,15 @@ VOID mpt_ToggleIG_8814A(PADAPTER pAdapter) u1Byte Path = 0; u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0; - for (Path; Path <= ODM_RF_PATH_D; Path++) { + for (Path; Path <= RF_PATH_D; Path++) { switch (Path) { - case ODM_RF_PATH_B: + case RF_PATH_B: IGReg = rB_IGI_Jaguar; break; - case ODM_RF_PATH_C: + case RF_PATH_C: IGReg = rC_IGI_Jaguar2; break; - case ODM_RF_PATH_D: + case RF_PATH_D: IGReg = rD_IGI_Jaguar2; break; default: @@ -612,52 +626,29 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) u32 ulAntennaRx = pHalData->AntennaRxPath; u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate); - if ((NssforRate == RF_2TX) || ((NssforRate == RF_1TX) && IS_HT_RATE(ForcedDataRate)) || ((NssforRate == RF_1TX) && IS_VHT_RATE(ForcedDataRate))) { - RTW_INFO("===> SetAntenna 2T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); - - switch (ulAntennaTx) { - case ANTENNA_BC: - pMptCtx->mpt_rf_path = ODM_RF_PATH_BC; - /*pHalData->ValidTxPath = 0x06; linux no use */ - phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x106); /*/ 0x940[15:4]=12'b0000_0100_0011*/ - break; - - case ANTENNA_CD: - pMptCtx->mpt_rf_path = ODM_RF_PATH_CD; - /*pHalData->ValidTxPath = 0x0C;*/ - phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x40c); /*/ 0x940[15:4]=12'b0000_0100_0011*/ - break; - case ANTENNA_AB: - default: - pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; - /*pHalData->ValidTxPath = 0x03;*/ - phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x043); /*/ 0x940[15:4]=12'b0000_0100_0011*/ - break; - } - - } else if (NssforRate == RF_3TX) { - RTW_INFO("===> SetAntenna 3T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); + if (NssforRate == RF_3TX) { + RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); switch (ulAntennaTx) { case ANTENNA_BCD: - pMptCtx->mpt_rf_path = ODM_RF_PATH_BCD; + pMptCtx->mpt_rf_path = RF_PATH_BCD; /*pHalData->ValidTxPath = 0x0e;*/ phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/ break; case ANTENNA_ABC: default: - pMptCtx->mpt_rf_path = ODM_RF_PATH_ABC; + pMptCtx->mpt_rf_path = RF_PATH_ABC; /*pHalData->ValidTxPath = 0x0d;*/ phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/ break; } } else { /*/if(NssforRate == RF_1TX)*/ - RTW_INFO("===> SetAntenna 1T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); + RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); switch (ulAntennaTx) { case ANTENNA_BCD: - pMptCtx->mpt_rf_path = ODM_RF_PATH_BCD; + pMptCtx->mpt_rf_path = RF_PATH_BCD; /*pHalData->ValidTxPath = 0x0e;*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7); phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe); @@ -665,14 +656,14 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) break; case ANTENNA_BC: - pMptCtx->mpt_rf_path = ODM_RF_PATH_BC; + pMptCtx->mpt_rf_path = RF_PATH_BC; /*pHalData->ValidTxPath = 0x06;*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6); phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6); phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6); break; case ANTENNA_B: - pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = RF_PATH_B; /*pHalData->ValidTxPath = 0x02;*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/ @@ -680,7 +671,7 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) break; case ANTENNA_C: - pMptCtx->mpt_rf_path = ODM_RF_PATH_C; + pMptCtx->mpt_rf_path = RF_PATH_C; /*pHalData->ValidTxPath = 0x04;*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/ @@ -688,7 +679,7 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) break; case ANTENNA_D: - pMptCtx->mpt_rf_path = ODM_RF_PATH_D; + pMptCtx->mpt_rf_path = RF_PATH_D; /*pHalData->ValidTxPath = 0x08;*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/ @@ -697,7 +688,7 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_A: default: - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; /*pHalData->ValidTxPath = 0x01;*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/ @@ -709,14 +700,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) switch (ulAntennaRx) { case ANTENNA_A: /*pHalData->ValidRxPath = 0x01;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); @@ -724,14 +717,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_B: /*pHalData->ValidRxPath = 0x02;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); @@ -739,14 +734,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_C: /*pHalData->ValidRxPath = 0x04;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); @@ -754,14 +751,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_D: /*pHalData->ValidRxPath = 0x08;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); @@ -769,14 +768,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_BC: /*pHalData->ValidRxPath = 0x06;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); @@ -784,14 +785,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_CD: /*pHalData->ValidRxPath = 0x0C;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); @@ -799,14 +802,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_BCD: /*pHalData->ValidRxPath = 0x0e;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8); @@ -814,14 +819,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_ABCD: /*pHalData->ValidRxPath = 0x0f;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8); @@ -845,7 +852,7 @@ mpt_SetSingleTone_8814A( { PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); - u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_A; + u1Byte StartPath = RF_PATH_A, EndPath = RF_PATH_A; static u4Byte regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0; if (bSingleTone) { @@ -855,29 +862,29 @@ mpt_SetSingleTone_8814A( regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/ switch (pMptCtx->mpt_rf_path) { - case ODM_RF_PATH_A: - case ODM_RF_PATH_B: - case ODM_RF_PATH_C: - case ODM_RF_PATH_D: + case RF_PATH_A: + case RF_PATH_B: + case RF_PATH_C: + case RF_PATH_D: StartPath = pMptCtx->mpt_rf_path; EndPath = pMptCtx->mpt_rf_path; break; - case ODM_RF_PATH_AB: - EndPath = ODM_RF_PATH_B; + case RF_PATH_AB: + EndPath = RF_PATH_B; break; - case ODM_RF_PATH_BC: - StartPath = ODM_RF_PATH_B; - EndPath = ODM_RF_PATH_C; + case RF_PATH_BC: + StartPath = RF_PATH_B; + EndPath = RF_PATH_C; break; - case ODM_RF_PATH_ABC: - EndPath = ODM_RF_PATH_C; + case RF_PATH_ABC: + EndPath = RF_PATH_C; break; - case ODM_RF_PATH_BCD: - StartPath = ODM_RF_PATH_B; - EndPath = ODM_RF_PATH_D; + case RF_PATH_BCD: + StartPath = RF_PATH_B; + EndPath = RF_PATH_D; break; - case ODM_RF_PATH_ABCD: - EndPath = ODM_RF_PATH_D; + case RF_PATH_ABCD: + EndPath = RF_PATH_D; break; } @@ -901,29 +908,29 @@ mpt_SetSingleTone_8814A( phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/ } else { switch (pMptCtx->mpt_rf_path) { - case ODM_RF_PATH_A: - case ODM_RF_PATH_B: - case ODM_RF_PATH_C: - case ODM_RF_PATH_D: + case RF_PATH_A: + case RF_PATH_B: + case RF_PATH_C: + case RF_PATH_D: StartPath = pMptCtx->mpt_rf_path; EndPath = pMptCtx->mpt_rf_path; break; - case ODM_RF_PATH_AB: - EndPath = ODM_RF_PATH_B; + case RF_PATH_AB: + EndPath = RF_PATH_B; break; - case ODM_RF_PATH_BC: - StartPath = ODM_RF_PATH_B; - EndPath = ODM_RF_PATH_C; + case RF_PATH_BC: + StartPath = RF_PATH_B; + EndPath = RF_PATH_C; break; - case ODM_RF_PATH_ABC: - EndPath = ODM_RF_PATH_C; + case RF_PATH_ABC: + EndPath = RF_PATH_C; break; - case ODM_RF_PATH_BCD: - StartPath = ODM_RF_PATH_B; - EndPath = ODM_RF_PATH_D; + case RF_PATH_BCD: + StartPath = RF_PATH_B; + EndPath = RF_PATH_D; break; - case ODM_RF_PATH_ABCD: - EndPath = ODM_RF_PATH_D; + case RF_PATH_ABCD: + EndPath = RF_PATH_D; break; } for (StartPath; StartPath <= EndPath; StartPath++) @@ -959,25 +966,25 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) switch (ulAntennaTx) { case ANTENNA_A: - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111); if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0); break; case ANTENNA_B: - pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = RF_PATH_B; phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222); if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1); break; case ANTENNA_AB: - pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; + pMptCtx->mpt_rf_path = RF_PATH_AB; phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333); if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0); break; default: - pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; + pMptCtx->mpt_rf_path = RF_PATH_AB; RTW_INFO("Unknown Tx antenna.\n"); break; } @@ -986,9 +993,9 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) u32 reg0xC50 = 0; case ANTENNA_A: phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3); /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/ reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0); @@ -1012,9 +1019,9 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) break; case ANTENNA_B: phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3); + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3); /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/ reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0); @@ -1038,7 +1045,7 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) break; case ANTENNA_AB: phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); /* set PWED_TH for BB Yn user guide R29 */ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04); @@ -1047,6 +1054,18 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) RTW_INFO("Unknown Rx antenna.\n"); break; } + + if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) { + if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) { + /* WiFi */ + phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2); + phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3); + } else { + /* BT */ + phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1); + phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3); + } + } } #endif @@ -1056,13 +1075,13 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter) HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); u32 ulAntennaTx, ulAntennaRx; PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; + struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); ulAntennaTx = pHalData->antenna_tx_path; ulAntennaRx = pHalData->AntennaRxPath; - if (pHalData->rf_chip >= RF_TYPE_MAX) { + if (pHalData->rf_chip >= RF_CHIP_MAX) { RTW_INFO("This RF chip ID is not supported\n"); return; } @@ -1070,19 +1089,13 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter) switch (pAdapter->mppriv.antenna_tx) { u8 p = 0, i = 0; case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/ - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0); phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/ - /*/<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/ - if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)) - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); - else - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); - for (i = 0; i < 3; ++i) { - u4Byte offset = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_A][i][0]; - u4Byte data = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_A][i][1]; + u4Byte offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0]; + u4Byte data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1]; if (offset != 0) { phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); @@ -1090,8 +1103,8 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter) } } for (i = 0; i < 2; ++i) { - u4Byte offset = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_A][i][0]; - u4Byte data = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_A][i][1]; + u4Byte offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0]; + u4Byte data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1]; if (offset != 0) { phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); @@ -1104,29 +1117,24 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter) u4Byte offset; u4Byte data; - pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = RF_PATH_B; phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5); phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/ - /* <20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/ - if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)) - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); - else - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); for (i = 0; i < 3; ++i) { /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/ - offset = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_A][i][0]; - data = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_B][i][1]; - if (pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_B][i][0] != 0) { + offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0]; + data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1]; + if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) { phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); } } /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/ for (i = 0; i < 2; ++i) { - offset = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_A][i][0]; - data = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_B][i][1]; - if (pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_B][i][0] != 0) { + offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0]; + data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1]; + if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) { phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); } @@ -1146,13 +1154,13 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter) HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); u4Byte ulAntennaTx, ulAntennaRx; PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; + struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); ulAntennaTx = pHalData->antenna_tx_path; ulAntennaRx = pHalData->AntennaRxPath; - if (pHalData->rf_chip >= RF_TYPE_MAX) { + if (pHalData->rf_chip >= RF_CHIP_MAX) { RTW_INFO("This RF chip ID is not supported\n"); return; } @@ -1161,7 +1169,7 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter) u1Byte p = 0, i = 0; case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */ - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0); phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/ @@ -1187,7 +1195,7 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter) } break; case ANTENNA_B: { /* Actually path S0 (BT)*/ - pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = RF_PATH_B; phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5); phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */ @@ -1226,13 +1234,13 @@ void mpt_SetRFPath_8723D(PADAPTER pAdapter) u1Byte p = 0, i = 0; u4Byte ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0; PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; + struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); ulAntennaTx = pHalData->antenna_tx_path; ulAntennaRx = pHalData->AntennaRxPath; - if (pHalData->rf_chip >= RF_TYPE_MAX) { + if (pHalData->rf_chip >= RF_CHIP_MAX) { RTW_INFO("This RF chip ID is not supported\n"); return; } @@ -1240,13 +1248,13 @@ void mpt_SetRFPath_8723D(PADAPTER pAdapter) switch (pAdapter->mppriv.antenna_tx) { /* Actually path S1 (Wi-Fi) */ case ANTENNA_A: { - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0); } break; /* Actually path S0 (BT) */ case ANTENNA_B: { - pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = RF_PATH_B; phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA); } @@ -1305,7 +1313,7 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter) phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0); } } - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; break; case ANTENNA_B: p_ofdm_tx->r_tx_antenna = 0x2; @@ -1332,7 +1340,7 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter) phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); } } - pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = RF_PATH_B; break; case ANTENNA_AB:/*/ For 8192S*/ p_ofdm_tx->r_tx_antenna = 0x3; @@ -1359,7 +1367,7 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter) phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); } } - pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; + pMptCtx->mpt_rf_path = RF_PATH_AB; break; default: break; @@ -1504,7 +1512,7 @@ s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther) void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03); } @@ -1512,13 +1520,12 @@ void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter) u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter) { - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(pAdapter); - struct PHY_DM_STRUCT *p_dm_odm = &hal_data->odmpriv; + struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter); u32 ThermalValue = 0; s32 thermal_value_temp = 0; s8 thermal_offset = 0; - ThermalValue = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/ + ThermalValue = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/ thermal_offset = phydm_get_thermal_offset(p_dm_odm); thermal_value_temp = ThermalValue + thermal_offset; @@ -1599,23 +1606,24 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; u4Byte ulAntennaTx = pHalData->antenna_tx_path; static u4Byte regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0; u8 rfPath; switch (ulAntennaTx) { case ANTENNA_B: - rfPath = ODM_RF_PATH_B; + rfPath = RF_PATH_B; break; case ANTENNA_C: - rfPath = ODM_RF_PATH_C; + rfPath = RF_PATH_C; break; case ANTENNA_D: - rfPath = ODM_RF_PATH_D; + rfPath = RF_PATH_D; break; case ANTENNA_A: default: - rfPath = ODM_RF_PATH_A; + rfPath = RF_PATH_A; break; } @@ -1625,7 +1633,7 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/ if (IS_HARDWARE_TYPE_8188E(pAdapter)) { regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0); phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0); } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/ @@ -1634,18 +1642,18 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/ + if (pMptCtx->mpt_rf_path == RF_PATH_A) { + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/ } else { /*/ S0/S1 both use PATH A to configure*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/ } } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */ + if (pMptCtx->mpt_rf_path == RF_PATH_A) { + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */ + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */ } } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { /*Set BB REG 88C: Prevent SingleTone Fail*/ @@ -1654,20 +1662,20 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + if (pMptCtx->mpt_rf_path == RF_PATH_A) { phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x1); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1); } else {/* S0/S1 both use PATH A to configure */ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x1); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1); } - } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) { -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) - u1Byte p = ODM_RF_PATH_A; + } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) { +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) + u1Byte p = RF_PATH_A; - regRF = phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask); + regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask); regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord); regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord); regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord); @@ -1675,8 +1683,8 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/ - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_AB) { - for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) { + if (pMptCtx->mpt_rf_path == RF_PATH_AB) { + for (p = RF_PATH_A; p <= RF_PATH_B; ++p) { phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ @@ -1684,26 +1692,49 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) } else { phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ - phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ +#ifdef CONFIG_RTL8821C + if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG) + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */ + else +#endif + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ } - - phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ - phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ - - if (pHalData->external_pa_5g) { - phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/ - phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/ - } else if (pHalData->ExternalPA_2G) { - phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/ - phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/ + if (IS_HARDWARE_TYPE_8822B(pAdapter)) { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xCB0=0x77777777*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xEB0=0x77777777*/ + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xCB4[15:0] = 0x7777*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xEB4[15:0] = 0x7777*/ + phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/ + phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/ + } else if (IS_HARDWARE_TYPE_8821C(pAdapter)) { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707); /* 0xCB0[[15:12, 7:4] = 0x707*/ + + if (pHalData->external_pa_5g) + { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/ + } + else if (pHalData->ExternalPA_2G) + { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/ + } + } else { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ + + if (pHalData->external_pa_5g) { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/ + } else if (pHalData->ExternalPA_2G) { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/ + } } #endif } -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821C) - else if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) +#if defined(CONFIG_RTL8814A) + else if (IS_HARDWARE_TYPE_8814A(pAdapter)) mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE); #endif - else /*/ Turn On SingleTone and turn off the other test modes.*/ phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone); @@ -1713,7 +1744,7 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) } else {/*/ Stop Single Ton e.*/ if (IS_HARDWARE_TYPE_8188E(pAdapter)) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF); + phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF); phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1); phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1); } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { @@ -1722,18 +1753,18 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) /*/ RESTORE MAC REG 88C: Enable RF Functions*/ phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0); } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/ + if (pMptCtx->mpt_rf_path == RF_PATH_A) { + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/ } else { /*/ S0/S1 both use PATH A to configure*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/ } } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */ + if (pMptCtx->mpt_rf_path == RF_PATH_A) { + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */ + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */ } } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/ @@ -1741,28 +1772,33 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) /*Set BB REG 88C: Prevent SingleTone Fail*/ phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc); } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + if (pMptCtx->mpt_rf_path == RF_PATH_A) { phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x0); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0); } else { /* S0/S1 both use PATH A to configure */ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x0); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0); } - } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) { -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) - u1Byte p = ODM_RF_PATH_A; + } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) { +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) + u1Byte p = RF_PATH_A; phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/ - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_AB) { - for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) { + if (pMptCtx->mpt_rf_path == RF_PATH_AB) { + for (p = RF_PATH_A; p <= RF_PATH_B; ++p) { phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF); phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/ } } else { + p = pMptCtx->mpt_rf_path; phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF); + + if (IS_HARDWARE_TYPE_8821C(pAdapter)) + phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */ + phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/ } @@ -1770,10 +1806,16 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1); phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2); phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3); + + if (IS_HARDWARE_TYPE_8822B(pAdapter)) { + RTW_INFO("Restore RFE control Pin cbc\n"); + phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0); + phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0); + } #endif } -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) - else if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) +#if defined(CONFIG_RTL8814A) + else if (IS_HARDWARE_TYPE_8814A(pAdapter)) mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE); else/*/ Turn off all test modes.*/ @@ -2002,12 +2044,10 @@ static VOID mpt_StartOfdmContTx( void mpt_ProSetPMacTx(PADAPTER Adapter) { PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); + struct mp_priv *pmppriv = &Adapter->mppriv; RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo; u32 u4bTmp; - dbg_print("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound); - dbg_print("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount, - PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern); #if 0 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3); PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6); @@ -2019,8 +2059,15 @@ void mpt_ProSetPMacTx(PADAPTER Adapter) PRINT_DATA("Src Address", Adapter->mac_addr, 6); PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, 6); #endif + if (Adapter->mppriv.pktInterval != 0) + PMacTxInfo.PacketPeriod = Adapter->mppriv.pktInterval; + + RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound); + RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount, + PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern); if (PMacTxInfo.bEnPMacTx == FALSE) { + pmppriv->mode = MP_ON; if (PMacTxInfo.Mode == CONTINUOUS_TX) { phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/ if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) @@ -2048,6 +2095,7 @@ void mpt_ProSetPMacTx(PADAPTER Adapter) } if (PMacTxInfo.Mode == CONTINUOUS_TX) { + pmppriv->mode = MP_CONTINUOUS_TX; PMacTxInfo.PacketCount = 1; if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) @@ -2055,6 +2103,7 @@ void mpt_ProSetPMacTx(PADAPTER Adapter) else mpt_StartOfdmContTx(Adapter); } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) { + pmppriv->mode = MP_SINGLE_TONE_TX; /* Continuous TX -> HW TX -> RF Setting */ PMacTxInfo.PacketCount = 1; @@ -2063,6 +2112,7 @@ void mpt_ProSetPMacTx(PADAPTER Adapter) else mpt_StartOfdmContTx(Adapter); } else if (PMacTxInfo.Mode == PACKETS_TX) { + pmppriv->mode = MP_PACKET_TX; if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0) PMacTxInfo.PacketCount = 0xffff; } @@ -2169,7 +2219,7 @@ void mpt_ProSetPMacTx(PADAPTER Adapter) u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8); phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp); - if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) { + if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) { u4Byte offset = 0xb44; if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE)) @@ -2199,8 +2249,7 @@ void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart) { u8 Rate; - RT_TRACE(_module_mp_, _drv_info_, - ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx)); + RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx); Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx); pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart; diff --git a/hal/hal_phy.c b/hal/hal_phy.c index 88c1b1c..1504a73 100644 --- a/hal/hal_phy.c +++ b/hal/hal_phy.c @@ -16,12 +16,6 @@ #include -/* ******************************************************************************** - * Constant. - * ******************************************************************************** - * 2008/11/20 MH For Debug only, RF */ -static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; - /** * Function: PHY_CalculateBitShift * @@ -49,6 +43,13 @@ PHY_CalculateBitShift( } +#ifdef CONFIG_RF_SHADOW_RW +/* ******************************************************************************** + * Constant. + * ******************************************************************************** + * 2008/11/20 MH For Debug only, RF */ +static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; + /* * ==> RF shadow Operation API Code Section!!! * @@ -80,7 +81,7 @@ PHY_CalculateBitShift( u32 PHY_RFShadowRead( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset) { return RF_Shadow[eRFPath][Offset].Value; @@ -91,7 +92,7 @@ PHY_RFShadowRead( VOID PHY_RFShadowWrite( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset, IN u32 Data) { @@ -104,7 +105,7 @@ PHY_RFShadowWrite( BOOLEAN PHY_RFShadowCompare( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset) { u32 reg; @@ -125,7 +126,7 @@ PHY_RFShadowCompare( VOID PHY_RFShadowRecorver( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset) { /* Check if the address is error */ @@ -144,7 +145,7 @@ VOID PHY_RFShadowCompareAll( IN PADAPTER Adapter) { - u8 eRFPath = 0 ; + enum rf_path eRFPath = RF_PATH_A; u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter); for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) { @@ -159,7 +160,7 @@ VOID PHY_RFShadowRecorverAll( IN PADAPTER Adapter) { - u8 eRFPath = 0; + enum rf_path eRFPath = RF_PATH_A; u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter); for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) { @@ -173,7 +174,7 @@ PHY_RFShadowRecorverAll( VOID PHY_RFShadowCompareFlagSet( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset, IN u8 Type) { @@ -186,7 +187,7 @@ PHY_RFShadowCompareFlagSet( VOID PHY_RFShadowRecorverFlagSet( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset, IN u8 Type) { @@ -200,7 +201,7 @@ VOID PHY_RFShadowCompareFlagSetAll( IN PADAPTER Adapter) { - u8 eRFPath = 0; + enum rf_path eRFPath = RF_PATH_A; u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter); for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) { @@ -220,7 +221,7 @@ VOID PHY_RFShadowRecorverFlagSetAll( IN PADAPTER Adapter) { - u8 eRFPath = 0; + enum rf_path eRFPath = RF_PATH_A; u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter); for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) { @@ -239,7 +240,7 @@ VOID PHY_RFShadowRefresh( IN PADAPTER Adapter) { - u8 eRFPath = 0; + enum rf_path eRFPath = RF_PATH_A; u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter); for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) { @@ -253,3 +254,4 @@ PHY_RFShadowRefresh( } } /* PHY_RFShadowRead */ +#endif /*CONFIG_RF_SHADOW_RW*/ diff --git a/hal/halmac/halmac_2_platform.h b/hal/halmac/halmac_2_platform.h index c6352de..44fd9a1 100644 --- a/hal/halmac/halmac_2_platform.h +++ b/hal/halmac/halmac_2_platform.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -35,14 +35,6 @@ #define HALMAC_INLINE inline -typedef u8 *pu8; -typedef u16 *pu16; -typedef u32 *pu32; -typedef s8 *ps8; -typedef s16 *ps16; -typedef s32 *ps32; - - #define HALMAC_PLATFORM_LITTLE_ENDIAN 1 #define HALMAC_PLATFORM_BIG_ENDIAN 0 @@ -66,9 +58,20 @@ typedef s32 *ps32; /*[Driver] config if enable the dbg msg or notl*/ #define HALMAC_DBG_MSG_ENABLE 1 +#define HALMAC_MSG_LEVEL_TRACE 3 +#define HALMAC_MSG_LEVEL_WARNING 2 +#define HALMAC_MSG_LEVEL_ERR 1 +#define HALMAC_MSG_LEVEL_NO_LOG 0 +/*[Driver] config halmac msg level + * Use HALMAC_MSG_LEVEL_XXXX + */ +#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE + /*[Driver] define the Rx FIFO expanding mode packet size unit for 8821C and 8822B */ /*Should be 8 Byte alignment*/ -#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 48 /*Bytes*/ +#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 80 /*Bytes*/ + +#define HALMAC_USE_TYPEDEF 0 /*[Driver] provide the type mutex*/ /* Mutex type */ diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_8197f_cfg.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_8197f_cfg.h deleted file mode 100644 index 4386ec8..0000000 --- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_8197f_cfg.h +++ /dev/null @@ -1,112 +0,0 @@ -#ifndef _HALMAC_8197F_CFG_H_ -#define _HALMAC_8197F_CFG_H_ - -#include "halmac_8197f_pwr_seq.h" -#include "halmac_api_8197f.h" -#include "halmac_api_8197f_usb.h" -#include "halmac_api_8197f_sdio.h" -#include "halmac_api_8197f_pcie.h" - -#if HALMAC_PLATFORM_TESTPROGRAM -#include "halmisc_api_8197f.h" -#include "halmisc_api_8197f_usb.h" -#include "halmisc_api_8197f_sdio.h" -#include "halmisc_api_8197f_pcie.h" -#endif - -#define HALMAC_TX_FIFO_SIZE_8197F 262144 /* 64k */ -#define HALMAC_RX_FIFO_SIZE_8197F 32768 /* 32k */ -#define HALMAC_TX_PAGE_SIZE_8197F 128 /* PageSize 128Byte */ -#define HALMAC_SECURITY_CAM_ENTRY_NUM_8197F 64 /* CAM Entry Size */ -#define HALMAC_TX_DESC_SIZE_8197F 48 -#define HALMAC_RX_DESC_SIZE_8197F 24 - -/* H2C/C2hH*/ -#define HALMAC_H2C_CMD_SIZE_8197F 32 - -/* Efuse size */ -#define HALMAC_EFUSE_SIZE_8197F 512/* 0x2000 */ -#define HALMAC_EEPROM_SIZE_8197F 0x300 -#define HALMAC_BT_EFUSE_SIZE_8197F 128 - -/* Rx aggregation parameters */ -typedef enum _HALMAC_NORMAL_RXAGG_TH_TO_8197F { - HALMAC_NORMAL_RXAGG_THRESHOLD_8197F = 0xFF, - HALMAC_NORMAL_RXAGG_TIMEOUT_8197F = 0x01, -} HALMAC_NORMAL_RXAGG_TH_TO_8197F; - -typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO_8197F { - HALMAC_LOOPBACK_RXAGG_THRESHOLD_8197F = 0xFF, - HALMAC_LOOPBACK_RXAGG_TIMEOUT_8197F = 0x01, -} HALMAC_LOOPBACK_RXAGG_TH_TO_8197F; - -/* FIFO size & packet size */ -#define HALMAC_BASIC_RXFF_SIZE_8197F 24576 /* 24K */ -#define HALMAC_WOWLAN_PATTERN_SIZE_8197F 256 - -/* Normal mode */ -typedef enum _HALMAC_NORMAL_PAGE_NUM_8197F { - HALMAC_NORMAL_PAGE_NUM_HPQ_8197F = 0x4C, - HALMAC_NORMAL_PAGE_NUM_NPQ_8197F = 0x4C, - HALMAC_NORMAL_PAGE_NUM_LPQ_8197F = 0x4C, - HALMAC_NORMAL_PAGE_NUM_EXPQ_8197F = 0x4A, - HALMAC_NORMAL_PAGE_NUM_PUBQ_8197F = 0x6C0, - HALMAC_NORMAL_TX_PAGE_BOUNDARY_8197F = 2032, -} HALMAC_NORMAL_PAGE_NUM_8197F; - -/* Loop back mode */ -typedef enum _HALMAC_LOOBACK_PAGE_NUM_8197F { - HALMAC_LOOPBACK_PAGE_NUM_HPQ_8197F = 0x4C, - HALMAC_LOOPBACK_PAGE_NUM_LPQ_8197F = 0x4C, - HALMAC_LOOPBACK_PAGE_NUM_NPQ_8197F = 0x4C, - HALMAC_LOOPBACK_PAGE_NUM_EXPQ_8197F = 0x4A, - HALMAC_LOOPBACK_PAGE_NUM_PUBQ_8197F = 0x2C0, - HALMAC_LOOPBACK_TX_PAGE_BOUNDARY_8197F = 1008, - HALMAC_LOOPBACK_LB_BUF_PAGE_NUM_8197F = 0x600, -} HALMAC_LOOBACK_PAGE_NUM_8197F; - - -/* Normal mode */ -typedef enum _HALMAC_NORMAL_PAGE_NUM_2BULKOUT_8197F { - HALMAC_NORMAL_PAGE_NUM_HPQ_2BULKOUT_8197F = 0x4C, - HALMAC_NORMAL_PAGE_NUM_NPQ_2BULKOUT_8197F = 0x4C, - HALMAC_NORMAL_PAGE_NUM_LPQ_2BULKOUT_8197F = 0x00, - HALMAC_NORMAL_PAGE_NUM_EXPQ_2BULKOUT_8197F = 0x00, - HALMAC_NORMAL_PAGE_NUM_PUBQ_2BULKOUT_8197F = 0x756, - HALMAC_NORMAL_TX_PAGE_BOUNDARY_2BULKOUT_8197F = 2032, -} HALMAC_NORMAL_PAGE_NUM_2BULKOUT_8197F; - -/* Loop back mode */ -typedef enum _HALMAC_LOOBACK_PAGE_NUM_2BULKOUT_8197F { - HALMAC_LOOPBACK_PAGE_NUM_HPQ_2BULKOUT_8197F = 0x4C, - HALMAC_LOOPBACK_PAGE_NUM_NPQ_2BULKOUT_8197F = 0x4C, - HALMAC_LOOPBACK_PAGE_NUM_LPQ_2BULKOUT_8197F = 0x00, - HALMAC_LOOPBACK_PAGE_NUM_EXPQ_2BULKOUT_8197F = 0x00, - HALMAC_LOOPBACK_PAGE_NUM_PUBQ_2BULKOUT_8197F = 0x356, - HALMAC_LOOPBACK_TX_PAGE_BOUNDARY_2BULKOUT_8197F = 1008, - HALMAC_LOOPBACK_LB_BUF_PAGE_NUM_2BULKOUT_8197F = 0x600, -} HALMAC_LOOBACK_PAGE_NUM_2BULKOUT_8197F; - -/* Normal mode */ -typedef enum _HALMAC_NORMAL_PAGE_NUM_3BULKOUT_8197F { - HALMAC_NORMAL_PAGE_NUM_HPQ_3BULKOUT_8197F = 0x4C, - HALMAC_NORMAL_PAGE_NUM_NPQ_3BULKOUT_8197F = 0x4C, - HALMAC_NORMAL_PAGE_NUM_LPQ_3BULKOUT_8197F = 0x4C, - HALMAC_NORMAL_PAGE_NUM_EXPQ_3BULKOUT_8197F = 0x00, - HALMAC_NORMAL_PAGE_NUM_PUBQ_3BULKOUT_8197F = 0x70A, - HALMAC_NORMAL_TX_PAGE_BOUNDARY_3BULKOUT_8197F = 2032, -} HALMAC_NORMAL_PAGE_NUM_3BULKOUT_8197F; - -/* Loop back mode */ -typedef enum _HALMAC_LOOBACK_PAGE_NUM_3BULKOUT_8197F { - HALMAC_LOOPBACK_PAGE_NUM_HPQ_3BULKOUT_8197F = 0x4C, - HALMAC_LOOPBACK_PAGE_NUM_NPQ_3BULKOUT_8197F = 0x4C, - HALMAC_LOOPBACK_PAGE_NUM_LPQ_3BULKOUT_8197F = 0x4C, - HALMAC_LOOPBACK_PAGE_NUM_EXPQ_3BULKOUT_8197F = 0x00, - HALMAC_LOOPBACK_PAGE_NUM_PUBQ_3BULKOUT_8197F = 0x30A, - HALMAC_LOOPBACK_TX_PAGE_BOUNDARY_3BULKOUT_8197F = 1008, - HALMAC_LOOPBACK_LB_BUF_PAGE_NUM_3BULKOUT_8197F = 0x600, -} HALMAC_LOOBACK_PAGE_NUM_3BULKOUT_8197F; - - -#endif diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_8197f_pwr_seq.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_8197f_pwr_seq.h deleted file mode 100644 index a4bb2ec..0000000 --- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_8197f_pwr_seq.h +++ /dev/null @@ -1,161 +0,0 @@ -#ifndef HALMAC_POWER_SEQUENCE_8197F -#define HALMAC_POWER_SEQUENCE_8197F - -#include "../../halmac_pwr_seq_cmd.h" - -/* - * There are 6 HW Power States: - * 0: POFF--Power Off - * 1: PDN--Power Down - * 2: CARDEMU--Card Emulation - * 3: ACT--Active Mode - * 4: LPS--Low Power State - * 5: SUS--Suspend - * - * The transition from different states are defined below - * TRANS_CARDEMU_TO_ACT - * TRANS_ACT_TO_CARDEMU - * TRANS_CARDEMU_TO_SUS - * TRANS_SUS_TO_CARDEMU - * TRANS_CARDEMU_TO_PDN - * TRANS_ACT_TO_LPS - * TRANS_LPS_TO_ACT - * - * TRANS_END - */ - -#define HALMAC_8197f_TRANS_CARDEMU_TO_ACT_STEPS 15 -#define HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define HALMAC_8197f_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define HALMAC_8197f_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define HALMAC_8197f_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define HALMAC_8197f_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define HALMAC_8197f_TRANS_ACT_TO_LPS_STEPS 20 -#define HALMAC_8197f_TRANS_LPS_TO_ACT_STEPS 15 -#define HALMAC_8197f_TRANS_END_STEPS 1 - - -#define RTL8197f_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0 }, /* disable SW LPS 0x04[10]=0*/ \ - { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /* wait till 0x04[17] = 1 power ready*/ \ - { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* release WLON reset 0x04[16]=1*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /* disable HWPDN 0x04[15]=0*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0 }, /* disable WL suspend*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* polling until return 0*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(0), 0 }, /**/ \ - { 0x0026, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /*MAC CLK = 40M*/ \ - { 0x0073, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /**/ - -#define RTL8197f_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0x1F[7:0] = 0 turn off RF*/ \ - { 0x004E, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ - -#define RTL8197f_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3)) }, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4) }, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*Set SDIO suspend local register*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait power state to suspend*/ - -#define RTL8197f_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*Set SDIO suspend local register*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /*wait power state to suspend*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0 }, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8197f_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07=0x20 , SOP option to disable BG/MB*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*0x04[10] = 1, enable SW LPS*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*Set SDIO suspend local register*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait power state to suspend*/ - -#define RTL8197f_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*Set SDIO suspend local register*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /*wait power state to suspend*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0 }, /*0x04[12:11] = 2b'01enable WL suspend*/ \ - { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*PCIe DMA start*/ - - -#define RTL8197f_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* 0x04[16] = 0*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /* 0x04[15] = 1*/ - -#define RTL8197f_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 },/* 0x04[15] = 0*/ - -#define RTL8197f_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, BIT(0) | BIT(1) }, /*set RPWM IMR*/ \ - { 0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable 32K CLK*/ \ - /*{0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK,HALMAC_PWR_BASEADDR_MAC,HALMAC_PWR_CMD_WRITE, 0xff, 0x42}, *//* LPS Option WL partial ON*/ \ - { 0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xff, 0x40 }, /* LPS Option WL partial ON disable*/ \ - { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*Tx Pause*/ \ - { 0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*CCK and OFDM are disabled,and clock are gated*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US }, /*Delay 1us*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Whole BB is reset*/ \ - { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F }, /*Reset MAC TRX*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*check if removed later*/ \ - { 0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*Respond TxOK to scheduler*/ \ - { 0x0029, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(6) | BIT(7), 0x00 }, /*gated BB clock*/ \ - { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* switch TSF clock to 32K*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable WL_LPS_EN*/ - - -#define RTL8197f_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - /*{0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK,HALMAC_PWR_BASEADDR_SDIO,HALMAC_PWR_CMD_WRITE, 0xFF, 0x84}, *//*SDIO RPWM*/ \ - { 0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*SDIO RPWM*/ \ - { 0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /*SDIO RPWM*/ \ - { 0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84 }, /*USB RPWM*/ \ - { 0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84 }, /*PCIe RPWM*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS }, /*Delay*/ \ - { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /*. 0x08[4] = 0 switch TSF to 40M*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS }, /*Delay*/ \ - { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), 0 }, /*Polling 0x109[7]=0 TSF in 40M*/ \ - { 0x0029, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(6) | BIT(7), BIT(6) | BIT(7) }, /*. 0x29[7:6] = 2b'00 enable BB clock*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /*. 0x101[1] = 1*/ \ - { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0) }, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \ - { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*. 0x522 = 0*/ \ - { 0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*clear RPWM INT*/ - -#define RTL8197f_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0 }, - - -extern HALMAC_WLAN_PWR_CFG halmac_8197f_power_on_flow[HALMAC_8197f_TRANS_CARDEMU_TO_ACT_STEPS + HALMAC_8197f_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8197f_radio_off_flow[HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8197f_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8197f_card_disable_flow[HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8197f_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8197f_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8197f_card_enable_flow[HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8197f_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8197f_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8197f_suspend_flow[HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8197f_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8197f_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8197f_resume_flow[HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8197f_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8197f_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8197f_hwpdn_flow[HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8197f_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8197f_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8197f_enter_lps_flow[HALMAC_8197f_TRANS_ACT_TO_LPS_STEPS + HALMAC_8197f_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8197f_leave_lps_flow[HALMAC_8197f_TRANS_LPS_TO_ACT_STEPS + HALMAC_8197f_TRANS_END_STEPS]; - -#endif diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f.h deleted file mode 100644 index 5c61b41..0000000 --- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _HALMAC_API_8197F_H_ -#define _HALMAC_API_8197F_H_ - -#include "../../halmac_2_platform.h" -#include "../../halmac_type.h" - -HALMAC_RET_STATUS -halmac_mount_api_8197f( - IN PHALMAC_ADAPTER pHalmac_adapter -); -#endif/* _HALMAC_API_8197F_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_pcie.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_pcie.h deleted file mode 100644 index 1e546a6..0000000 --- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_pcie.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _HALMAC_API_8197F_PCIE_H_ -#define _HALMAC_API_8197F_PCIE_H_ - -#include "../../halmac_2_platform.h" -#include "../../halmac_type.h" - - -#endif/* _HALMAC_API_8197F_PCIE_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_sdio.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_sdio.h deleted file mode 100644 index c6e59c3..0000000 --- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_sdio.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _HALMAC_API_8197F_SDIO_H_ -#define _HALMAC_API_8197F_SDIO_H_ - -#include "../../halmac_2_platform.h" -#include "../../halmac_type.h" - - -#endif/* _HALMAC_API_8197F_SDIO_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_usb.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_usb.h deleted file mode 100644 index 4bf5779..0000000 --- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_usb.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _HALMAC_API_8197F_USB_H_ -#define _HALMAC_API_8197F_USB_H_ - -#include "../../halmac_2_platform.h" -#include "../../halmac_type.h" - - -#endif/* _HALMAC_API_8197F_USB_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_func_8197f.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_func_8197f.h deleted file mode 100644 index 1432b41..0000000 --- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_func_8197f.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _HALMAC_FUNC_8197F_H_ -#define _HALMAC_FUNC_8197F_H_ - -#include "../../halmac_type.h" - -#endif /* _HALMAC_FUNC_8197F_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h deleted file mode 100644 index 1bd24c0..0000000 --- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h +++ /dev/null @@ -1,119 +0,0 @@ -#ifndef _HALMAC_8821C_CFG_H_ -#define _HALMAC_8821C_CFG_H_ - -#include "halmac_8821c_pwr_seq.h" -#include "halmac_api_8821c.h" -#include "halmac_api_8821c_usb.h" -#include "halmac_api_8821c_pcie.h" -#include "halmac_api_8821c_sdio.h" -#include "../../halmac_bit2.h" -#include "../../halmac_reg2.h" -#include "../../halmac_api.h" - -#if HALMAC_PLATFORM_TESTPROGRAM -#include "halmisc_api_8821c.h" -#include "halmisc_api_8821c_usb.h" -#include "halmisc_api_8821c_sdio.h" -#include "halmisc_api_8821c_pcie.h" -#endif - -#define HALMAC_TX_FIFO_SIZE_8821C 65536 /* 64k */ -#define HALMAC_TX_FIFO_SIZE_LA_8821C 32768 /* 32k */ -#define HALMAC_RX_FIFO_SIZE_8821C 16384 /* 16k */ -#define HALMAC_TX_PAGE_SIZE_8821C 128 /* PageSize 128Byte */ -#define HALMAC_TX_PAGE_SIZE_2_POWER_8821C 7 /* 128 = 2^7 */ -#define HALMAC_SECURITY_CAM_ENTRY_NUM_8821C 64 /* CAM Entry Size */ -#define HALMAC_TX_DESC_SIZE_8821C 48 -#define HALMAC_RX_DESC_SIZE_8821C 24 -#define HALMAC_WOWLAN_PATTERN_SIZE_8821C 256 - -#define HALMAC_EFUSE_SIZE_8821C 512 /* 0x2000 */ -#define HALMAC_EEPROM_SIZE_8821C 0x200 -#define HALMAC_BT_EFUSE_SIZE_8821C 128 - -#define HALMAC_CR_TRX_ENABLE_8821C (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \ - BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \ - BIT_MACTXEN | BIT_MACRXEN) - -#define HALMAC_BLK_DESC_NUM_8821C 0x3 /* Only for USB */ - -typedef enum _HALMAC_NORMAL_RXAGG_TH_TO_8821C { - HALMAC_NORMAL_RXAGG_THRESHOLD_8821C = 0xFF, - HALMAC_NORMAL_RXAGG_TIMEOUT_8821C = 0x01, -} HALMAC_NORMAL_RXAGG_TH_TO_8821C; - -typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO_8821C { - HALMAC_LOOPBACK_RXAGG_THRESHOLD_8821C = 0xFF, - HALMAC_LOOPBACK_RXAGG_TIMEOUT_8821C = 0x01, -} HALMAC_LOOPBACK_RXAGG_TH_TO_8821C; - -#define HALMAC_RSVD_DRV_PGNUM_8821C 16 /*2048*/ -#define HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8821C 32 /*4096*/ -#define HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C 8 /*1024*/ -#define HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8821C 0 /*0*/ -#define HALMAC_RSVD_FW_TXBUFF_PGNUM_8821C 4 /*512*/ - -/* - * Normal mode - */ -#define HALMAC_NORMAL_HPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_NORMAL_NPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_NORMAL_LPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_NORMAL_EXPQ_PGNUM_8821C 14 /**/ -#define HALMAC_NORMAL_GAP_PGNUM_8821C 1 /*128*/ - -/* - * Loopback mode - */ -#define HALMAC_LB_HPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_LB_NPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_LB_LPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_LB_EXPQ_PGNUM_8821C 14 /**/ -#define HALMAC_LB_GAP_PGNUM_8821C 256 /**/ - -/* - * Normal mode - 2Bulkout - */ -#define HALMAC_NORMAL_2BULKOUT_HPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_NORMAL_2BULKOUT_NPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_NORMAL_2BULKOUT_LPQ_PGNUM_8821C 0 /*0*/ -#define HALMAC_NORMAL_2BULKOUT_EXPQ_PGNUM_8821C 0 /*0*/ -#define HALMAC_NORMAL_2BULKOUT_GAP_PGNUM_8821C 1 /*128*/ - -/* - * Loopback mode - 2Bulkout - */ -#define HALMAC_LB_2BULKOUT_HPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_LB_2BULKOUT_NPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_LB_2BULKOUT_LPQ_PGNUM_8821C 0 /*0*/ -#define HALMAC_LB_2BULKOUT_EXPQ_PGNUM_8821C 0 /*0*/ -#define HALMAC_LB_2BULKOUT_GAP_PGNUM_8821C 256 /**/ - -/* - * Normal mode - 3BULKOUT - */ -#define HALMAC_NORMAL_3BULKOUT_HPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_NORMAL_3BULKOUT_NPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_NORMAL_3BULKOUT_LPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_NORMAL_3BULKOUT_EXPQ_PGNUM_8821C 0 /*0*/ -#define HALMAC_NORMAL_3BULKOUT_GAP_PGNUM_8821C 1 /*128*/ - -/* - * Loopback mode - 3BULKOUT - */ -#define HALMAC_LB_3BULKOUT_HPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_LB_3BULKOUT_NPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_LB_3BULKOUT_LPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_LB_3BULKOUT_EXPQ_PGNUM_8821C 0 /*0*/ -#define HALMAC_LB_3BULKOUT_GAP_PGNUM_8821C 256 /**/ - -/* - * WMM mode - */ -#define HALMAC_WMM_HPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_WMM_NPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_WMM_LPQ_PGNUM_8821C 16 /*2048*/ -#define HALMAC_WMM_EXPQ_PGNUM_8821C 14 /**/ -#define HALMAC_WMM_GAP_PGNUM_8821C 1 /*128*/ - -#endif diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h deleted file mode 100644 index c813530..0000000 --- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h +++ /dev/null @@ -1,223 +0,0 @@ -#ifndef HALMAC_POWER_SEQUENCE_8821C -#define HALMAC_POWER_SEQUENCE_8821C - -#include "../../halmac_pwr_seq_cmd.h" - -/* - * There are 6 HW Power States: - * 0: POFF--Power Off - * 1: PDN--Power Down - * 2: CARDEMU--Card Emulation - * 3: ACT--Active Mode - * 4: LPS--Low Power State - * 5: SUS--Suspend - * - * The transition from different states are defined below - * TRANS_CARDEMU_TO_ACT - * TRANS_ACT_TO_CARDEMU - * TRANS_CARDEMU_TO_SUS - * TRANS_SUS_TO_CARDEMU - * TRANS_CARDEMU_TO_PDN - * TRANS_ACT_TO_LPS - * TRANS_LPS_TO_ACT - * - * TRANS_END - */ - -#define HALMAC_8821c_TRANS_CARDEMU_TO_ACT_STEPS 25 -#define HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define HALMAC_8821c_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define HALMAC_8821c_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define HALMAC_8821c_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define HALMAC_8821c_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define HALMAC_8821c_TRANS_ACT_TO_LPS_STEPS 25 -#define HALMAC_8821c_TRANS_ACT_TO_DEEP_LPS_STEPS 25 -#define HALMAC_8821c_TRANS_LPS_TO_ACT_STEPS 20 -#define HALMAC_8821c_TRANS_END_STEPS 1 - - -#define HALMAC_RTL8821c_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ - { 0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ - { 0x0001, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWRSEQ_DELAY_MS }, /*Delay 1ms*/ \ - { 0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0 }, /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \ - { 0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* Disable USB suspend */ \ - { 0x0004, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /* enabled usb resume */ \ - { 0x0004, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0 }, /* disable usb resume */ \ - { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /* wait till 0x04[17] = 1 power ready*/ \ - { 0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* Enable USB suspend */ \ - { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* release WLON reset 0x04[16]=1*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /* disable HWPDN 0x04[15]=0*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0 }, /* disable WL suspend*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* polling until return 0*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(0), 0 }, /**/ \ - { 0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /*Enable XTAL_CLK*/ \ - { 0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*0x67[5]=1 , BIT_PAPE_WLBT_SEL*/ \ - -#define HALMAC_RTL8821c_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0x1F[7:0] = 0 turn off RF*/ \ - { 0x0049, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Enable rising edge triggering interrupt*/ \ - { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* release WLON reset 0x04[16]=1*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /* Whole BB is reset */ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - { 0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0 }, /* XTAL_CLK gated*/ \ - { 0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ - -#define HALMAC_RTL8821c_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3)) }, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4) }, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*Set SDIO suspend local register*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait power state to suspend*/ - -#define HALMAC_RTL8821c_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0 }, /*clear suspend enable and power down enable*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*Set SDIO suspend local register*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /*wait power state to suspend*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0 }, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define HALMAC_RTL8821c_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07=0x20 , SOP option to disable BG/MB*/ \ - { 0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /*0x67[5]=0 , BIT_PAPE_WLBT_SEL*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*0x04[10] = 1, enable SW LPS*/ \ - { 0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*Set SDIO suspend local register*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait power state to suspend*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*0x90[1]=0 , disable 32k clock*/ \ - { 0x0044, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ \ - { 0x0040, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x90 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ \ - { 0x0041, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x00 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ \ - { 0x0042, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x04 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ - -#define HALMAC_RTL8821c_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0 }, /*clear suspend enable and power down enable*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*Set SDIO suspend local register*/ \ - { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /*wait power state to suspend*/ \ - { 0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0 }, /*0x04[12:11] = 2b'01enable WL suspend*/ \ - { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*PCIe DMA start*/ - - -#define HALMAC_RTL8821c_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ - { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* 0x04[16] = 0*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /* 0x04[15] = 1*/ - -#define HALMAC_RTL8821c_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 },/* 0x04[15] = 0*/ - -#define HALMAC_RTL8821c_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*Enable 32k calibration and thermal meter*/ \ - { 0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /*Register write data of 32K calibration*/ \ - { 0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*Enable 32k calibration reg write*/ \ - { 0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1) }, /*set RPWM IMR*/ \ - { 0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable 32K CLK*/ \ - { 0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x42 }, /* LPS Option MAC OFF enable*/ \ - { 0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /* LPS Option Enable memory to deep sleep mode*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /* enable reg use 32K CLK*/ \ - { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*PCIe DMA stop*/ \ - { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*Tx Pause*/ \ - { 0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*CCK and OFDM are disabled,and clock are gated*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US }, /*Delay 1us*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Whole BB is reset*/ \ - { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F }, /*Reset MAC TRX*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*check if removed later*/ \ - { 0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*Respond TxOK to scheduler*/ \ - { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* switch TSF clock to 32K*/ \ - { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7) }, /*Polling 0x109[7]=0 TSF in 40M*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable WL_LPS_EN*/ - -#define HALMAC_RTL8821c_TRANS_ACT_TO_DEEP_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*Enable 32k calibration and thermal meter*/ \ - { 0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /*Register write data of 32K calibration*/ \ - { 0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*Enable 32k calibration reg write*/ \ - { 0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1) }, /*set RPWM IMR*/ \ - { 0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable 32K CLK*/ \ - { 0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x40 }, /* LPS Option MAC OFF enable*/ \ - { 0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /* LPS Option Enable memory to deep sleep mode*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /* enable reg use 32K CLK*/ \ - { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*PCIe DMA stop*/ \ - { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*Tx Pause*/ \ - { 0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*CCK and OFDM are disabled,and clock are gated*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US }, /*Delay 1us*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Whole BB is reset*/ \ - { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F }, /*Reset MAC TRX*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*check if removed later*/ \ - { 0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*Respond TxOK to scheduler*/ \ - { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* switch TSF clock to 32K*/ \ - { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7) }, /*Polling 0x109[7]=1 TSF in 32K*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable WL_LPS_EN*/ - -#define HALMAC_RTL8821c_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*SDIO RPWM*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS }, /*Delay*/ \ - { 0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /*SDIO RPWM*/ \ - { 0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84 }, /*USB RPWM*/ \ - { 0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84 }, /*PCIe RPWM*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS }, /*Delay*/ \ - { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /*. 0x08[4] = 0 switch TSF to 40M*/ \ - { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), 0 }, /*Polling 0x109[7]=0 TSF in 40M*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /*. 0x101[1] = 1*/ \ - { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \ - { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0) }, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \ - { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*. 0x522 = 0*/ \ - { 0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x03 }, /*clear RPWM INT*/ \ - { 0x0124, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \ - { 0x0125, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \ - { 0x0126, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \ - { 0x0127, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \ - { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /* disable reg use 32K CLK*/ \ - { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0 }, /*disable 32k calibration and thermal meter*/ - -#define HALMAC_RTL8821c_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - { 0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0 }, /* */ - - -extern HALMAC_WLAN_PWR_CFG halmac_8821c_power_on_flow[HALMAC_8821c_TRANS_CARDEMU_TO_ACT_STEPS + HALMAC_8821c_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8821c_radio_off_flow[HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8821c_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8821c_card_disable_flow[HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8821c_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8821c_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8821c_card_enable_flow[HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8821c_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8821c_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8821c_suspend_flow[HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8821c_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8821c_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8821c_resume_flow[HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8821c_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8821c_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8821c_hwpdn_flow[HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8821c_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8821c_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8821c_enter_lps_flow[HALMAC_8821c_TRANS_ACT_TO_LPS_STEPS + HALMAC_8821c_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8821c_enter_deep_lps_flow[HALMAC_8821c_TRANS_ACT_TO_DEEP_LPS_STEPS + HALMAC_8821c_TRANS_END_STEPS]; -extern HALMAC_WLAN_PWR_CFG halmac_8821c_leave_lps_flow[HALMAC_8821c_TRANS_LPS_TO_ACT_STEPS + HALMAC_8821c_TRANS_END_STEPS]; - -#endif diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h deleted file mode 100644 index c244cd3..0000000 --- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef _HALMAC_API_8821C_H_ -#define _HALMAC_API_8821C_H_ - -#include "../../halmac_2_platform.h" -#include "../../halmac_type.h" - -HALMAC_RET_STATUS -halmac_mount_api_8821c( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_init_trx_cfg_8821C( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode -); - -HALMAC_RET_STATUS -halmac_init_h2c_8821c( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -#endif/* _HALMAC_API_8821C_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h deleted file mode 100644 index 0100303..0000000 --- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _HALMAC_API_8821C_PCIE_H_ -#define _HALMAC_API_8821C_PCIE_H_ - -#include "../../halmac_2_platform.h" -#include "../../halmac_type.h" - -HALMAC_RET_STATUS -halmac_mac_power_switch_8821c_pcie( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_MAC_POWER halmac_power -); - -#endif/* _HALMAC_API_8821C_PCIE_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h deleted file mode 100644 index baa7f47..0000000 --- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef _HALMAC_API_8821C_SDIO_H_ -#define _HALMAC_API_8821C_SDIO_H_ - -#include "../../halmac_2_platform.h" -#include "../../halmac_type.h" - -HALMAC_RET_STATUS -halmac_mac_power_switch_8821c_sdio( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_MAC_POWER halmac_power -); - -HALMAC_RET_STATUS -halmac_tx_allowed_sdio_8821c( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHalmac_buf, - IN u32 halmac_size -); - -#endif/* _HALMAC_API_8821C_SDIO_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h deleted file mode 100644 index ea1be95..0000000 --- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _HALMAC_API_8821C_USB_H_ -#define _HALMAC_API_8821C_USB_H_ - -#include "../../halmac_2_platform.h" -#include "../../halmac_type.h" - -HALMAC_RET_STATUS -halmac_mac_power_switch_8821c_usb( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_MAC_POWER halmac_power -); -#endif/* _HALMAC_API_8821C_USB_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h deleted file mode 100644 index 3c0364c..0000000 --- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _HALMAC_FUNC_8821C_H_ -#define _HALMAC_FUNC_8821C_H_ - -#include "../../halmac_type.h" - -HALMAC_RET_STATUS -halmac_txdma_queue_mapping_8821c( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode -); - - -HALMAC_RET_STATUS -halmac_priority_queue_config_8821c( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode -); - -#endif /* _HALMAC_FUNC_8821C_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h index e2a9c96..b88755a 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,99 +16,58 @@ #ifndef _HALMAC_8822B_CFG_H_ #define _HALMAC_8822B_CFG_H_ -#include "halmac_8822b_pwr_seq.h" -#include "halmac_api_8822b.h" -#include "halmac_api_8822b_usb.h" -#include "halmac_api_8822b_sdio.h" -#include "halmac_api_8822b_pcie.h" -#include "../../halmac_bit2.h" -#include "../../halmac_reg2.h" -#include "../../halmac_api.h" +#include "../../halmac_hw_cfg.h" +#include "../halmac_88xx_cfg.h" -#if HALMAC_PLATFORM_TESTPROGRAM -#include "halmisc_api_8822b.h" -#include "halmisc_api_8822b_usb.h" -#include "halmisc_api_8822b_sdio.h" -#include "halmisc_api_8822b_pcie.h" -#endif - -#define HALMAC_TX_FIFO_SIZE_8822B 262144 /* 256k */ -#define HALMAC_TX_FIFO_SIZE_LA_8822B (HALMAC_TX_FIFO_SIZE_8822B >> 1) /* 128k */ -#define HALMAC_RX_FIFO_SIZE_8822B 24576 /* 24k */ -#define HALMAC_TX_PAGE_SIZE_8822B 128 /* PageSize 128Byte */ -#define HALMAC_TX_ALIGN_SIZE_8822B 8 -#define HALMAC_TX_PAGE_SIZE_2_POWER_8822B 7 /* 128 = 2^7 */ -#define HALMAC_SECURITY_CAM_ENTRY_NUM_8822B 64 /* CAM Entry Size */ -#define HALMAC_TX_AGG_ALIGNMENT_SIZE_8822B 8 -#define HALMAC_TX_DESC_SIZE_8822B 48 -#define HALMAC_RX_DESC_SIZE_8822B 24 -#define HALMAC_C2H_PKT_BUF_8822B 256 -#define HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B 80 /*8*10 Bytes*/ -#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B 80 /* should be 8 Byte alignment*/ - -#define HALMAC_RX_FIFO_EXPANDING_UNIT_8822B (HALMAC_RX_DESC_SIZE_8822B + HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE) /* should be 8 Byte alignment*/ -#define HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8822B (HALMAC_RX_DESC_SIZE_8822B + HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B) /* should be 8 Byte alignment*/ - -#define HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B 196608 /* 192k */ -#define HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B ((((HALMAC_RX_FIFO_EXPANDING_UNIT_8822B << 8) - 1) >> 10) << 10) /* < 46k*/ -#define HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_MAX_8822B ((((HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8822B << 8) - 1) >> 10) << 10) /* 45k < 64K*/ -#define HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_2_BLOCK_8822B 131072 /* 128k */ -#define HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_2_BLOCK_8822B 155648 /* 152k */ -#define HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_3_BLOCK_8822B 65536 /* 64k */ -#define HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_3_BLOCK_8822B 221184 /* 216k */ - -/* -* TXFIFO LAYOUT -* HIGH_QUEUE -* NORMAL_QUEUE -* LOW_QUEUE -* EXTRA_QUEUE -* PUBLIC_QUEUE -- decided after all other queue are defined -* GAP_QUEUE -- Used to separate AC queue and Rsvd page -* -* RSVD_DRIVER -- Driver used rsvd page area -* RSVD_H2C_EXTRAINFO -- Extra Information for h2c -* RSVD_H2C_QUEUE -- h2c queue in rsvd page -* RSVD_CPU_INSTRUCTION -- extend fw code -* RSVD_FW_TXBUFF -- fw used this area to send packet -* -* Symbol : HALMAC_MODE_QUEUE_UNIT_CHIP, ex: HALMAC_LB_2BULKOUT_FWCMD_PGNUM_8822B -*/ -#define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_8822B 16384 /*16K, only used in init case*/ +#if HALMAC_8822B_SUPPORT -#define HALMAC_RSVD_DRV_PGNUM_8822B 16 /*2048*/ -#define HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B 32 /*4096*/ -#define HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B 8 /*1024*/ -#define HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B 0 /*0*/ -#define HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B 4 /*512*/ +#define TX_FIFO_SIZE_8822B 262144 +#define RX_FIFO_SIZE_8822B 24576 +#define TRX_SHARE_SIZE_8822B 65536 +#define RX_DESC_DUMMY_SIZE_8822B 72 /* 8 * 9 Bytes */ +#define RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B 80 /* 8 Byte alignment*/ -#define HALMAC_EFUSE_SIZE_8822B 1024 /* 0x400 */ -#define HALMAC_BT_EFUSE_SIZE_8822B 128 /* 0x80 */ -#define HALMAC_EEPROM_SIZE_8822B 0x300 -#define HALMAC_CR_TRX_ENABLE_8822B (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \ - BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \ - BIT_MACTXEN | BIT_MACRXEN) - -#define HALMAC_BLK_DESC_NUM_8822B 0x3 /* Only for USB */ - -/* AMPDU max time (unit : 32us) */ -#define HALMAC_AMPDU_MAX_TIME_8822B 0x70 - -/* Protect mode control */ -#define HALMAC_PROT_RTS_LEN_TH_8822B 0xFF -#define HALMAC_PROT_RTS_TX_TIME_TH_8822B 0x08 -#define HALMAC_PROT_MAX_AGG_PKT_LIMIT_8822B 0x20 -#define HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8822B 0x20 - -/* Fast EDCA setting */ -#define HALMAC_FAST_EDCA_VO_TH_8822B 0x06 -#define HALMAC_FAST_EDCA_VI_TH_8822B 0x06 -#define HALMAC_FAST_EDCA_BE_TH_8822B 0x06 -#define HALMAC_FAST_EDCA_BK_TH_8822B 0x06 +/* should be 8 Byte alignment*/ +#if (HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE <= \ + RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B) +#define RX_FIFO_EXPANDING_UNIT_8822B (RX_DESC_SIZE_88XX + \ + RX_DESC_DUMMY_SIZE_8822B + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE) +#else +#define RX_FIFO_EXPANDING_UNIT_8822B (RX_DESC_SIZE_88XX + \ + RX_DESC_DUMMY_SIZE_8822B + RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B) +#endif -/* BAR setting */ -#define HALMAC_BAR_RETRY_LIMIT_8822B 0x01 -#define HALMAC_RA_TRY_RATE_AGG_LIMIT_8822B 0x08 +#define TX_FIFO_SIZE_LA_8822B (TX_FIFO_SIZE_8822B >> 1) +#define TX_FIFO_SIZE_RX_EXPAND_1BLK_8822B \ + (TX_FIFO_SIZE_8822B - TRX_SHARE_SIZE_8822B) +#define RX_FIFO_SIZE_RX_EXPAND_1BLK_8822B \ + ((((RX_FIFO_EXPANDING_UNIT_8822B << 8) - 1) >> 10) << 10) +#define TX_FIFO_SIZE_RX_EXPAND_2BLK_8822B \ + (TX_FIFO_SIZE_8822B - (2 * TRX_SHARE_SIZE_8822B)) +#define RX_FIFO_SIZE_RX_EXPAND_2BLK_8822B \ + (RX_FIFO_SIZE_8822B + (2 * TRX_SHARE_SIZE_8822B)) +#define TX_FIFO_SIZE_RX_EXPAND_3BLK_8822B \ + (TX_FIFO_SIZE_8822B - (3 * TRX_SHARE_SIZE_8822B)) +#define RX_FIFO_SIZE_RX_EXPAND_3BLK_8822B \ + (RX_FIFO_SIZE_8822B + (3 * TRX_SHARE_SIZE_8822B)) + +#define EFUSE_SIZE_8822B 1024 +#define EEPROM_SIZE_8822B 768 +#define BT_EFUSE_SIZE_8822B 128 + +#define SEC_CAM_NUM_8822B 64 + +#define OQT_ENTRY_AC_8822B 32 +#define OQT_ENTRY_NOAC_8822B 32 +#define MACID_MAX_8822B 128 + +#define WLAN_FW_IRAM_MAX_SIZE_8822B 196608 +#define WLAN_FW_DRAM_MAX_SIZE_8822B 49152 +#define WLAN_FW_ERAM_MAX_SIZE_8822B 0 +#define WLAN_FW_MAX_SIZE_8822B (WLAN_FW_IRAM_MAX_SIZE_8822B + \ + WLAN_FW_DRAM_MAX_SIZE_8822B + WLAN_FW_ERAM_MAX_SIZE_8822B) + +#endif /* HALMAC_8822B_SUPPORT*/ #endif diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.c deleted file mode 100644 index 5ccbac7..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.c +++ /dev/null @@ -1,73 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#include "../halmac_88xx_cfg.h" -#include "halmac_8822b_cfg.h" - -/** - * ============ip sel item list============ - * HALMAC_IP_SEL_INTF_PHY - * USB2 : usb2 phy, 1byte value - * USB3 : usb3 phy, 2byte value - * PCIE1 : pcie gen1 mdio, 2byte value - * PCIE2 : pcie gen2 mdio, 2byte value - * HALMAC_IP_SEL_MAC - * USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value - * HALMAC_IP_SEL_PCIE_DBI - * USB2 USB3 : none - * PCIE1, PCIE2 : pcie dbi, 1byte value - */ - -HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_USB2_PHY[] = { - /* {offset, value, ip sel, cut mask, platform mask} */ - {0xFFFF, 0x00, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL}, -}; - -HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_USB3_PHY[] = { - /* {offset, value, ip sel, cut mask, platform mask} */ - {0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_D, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL}, -}; - -HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_PCIE_PHY_GEN1[] = { - /* {offset, value, ip sel, cut mask, platform mask} */ - {0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0002, 0x60C6, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0008, 0x3596, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0009, 0x321C, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x000A, 0x9623, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0020, 0x94FF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0021, 0xFFCF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0026, 0xC006, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0029, 0xFF0E, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x002A, 0x1840, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL}, -}; - -HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_PCIE_PHY_GEN2[] = { - /* {offset, value, ip sel, cut mask, platform mask} */ - {0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0002, 0x60C6, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0008, 0x3597, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0009, 0x321C, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x000A, 0x9623, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0020, 0x94FF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0021, 0xFFCF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0026, 0xC006, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x0029, 0xFF0E, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0x002A, 0x3040, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, HALMAC_INTF_PHY_PLATFORM_ALL}, - {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL}, -}; - diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c deleted file mode 100644 index 79e2a5a..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c +++ /dev/null @@ -1,264 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#include "../halmac_88xx_cfg.h" -#include "halmac_8822b_cfg.h" - -HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT[] = { - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ - {0x0012, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*SWR OCP = SWR OCP = 010 1382.40*/ - {0x0012, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*SWR OCP = 010 1382.40 */ - {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ - {0x0001, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWRSEQ_DELAY_MS}, /*Delay 1ms*/ - {0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ - {0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* Disable USB suspend */ - {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, /* wait till 0x04[17] = 1 power ready*/ - {0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /* Enable USB suspend */ - {0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*0xFF1A = 0 to release resume signals*/ - {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* release WLON reset 0x04[16]=1*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0}, /* disable HWPDN 0x04[15]=0*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, /* disable WL suspend*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* polling until return 0*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(0), 0}, - {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, /*Enable XTAL_CLK*/ - {0x10A8, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0},/*NFC pad enabled*/ - {0x10A9, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xef},/*NFC pad enabled*/ - {0x10AA, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x0c},/*NFC pad enabled*/ - {0x0068, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO pad power down disabled*/ - {0x0029, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xF9}, /*PLL seting*/ - {0x0024, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /*CH13»P5G³¡¤ÀCH TX EVMªº§ïµ½*/ - {0x0074, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*PCIE WAKE# enabled*/ - {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, -}; - -HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU[] = { - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ - {0x0003, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /*0x02[10] = 0 Disable MCU Core*/ - {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0}, /*LPS option 0x93[3]=0 , SWR PFM*/ - {0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ - {0x00EF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*0xEF[7:0] = 0 turn off RF*/ - {0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x30}, /*0xFF1A = 0x30 to block resume signals*/ - {0x0049, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*Enable rising edge triggering interrupt*/ - {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* release WLON reset 0x04[16]=1*/ - {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /* Whole BB is reset */ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ - {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0}, /* XTAL_CLK gated*/ - {0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ - {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, -}; - -HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS[] = { - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/ - {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ - {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ - {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ - {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, -}; - -HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU[] = { - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ - {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ - {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, -}; - -HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS[] = { - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*suspend enable and power down enable*/ - {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ - {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0}, /*0x67[5]=0 , BIT_PAPE_WLBT_SEL*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/ - {0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ - {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /* 0: BT PAPE control ; 1: WL BB LNAON control*/ - {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /* 0: BT GPIO[11:10] control ; 1: WL BB LNAON control*/ - {0x004F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* 0: BT Control*/ - {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /* turn off BT_3DD_SYNC_B and BT_GPIO[18] */ - {0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6) }, /* GPIO[6] : Output mode*/ - {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0 }, /* turn off BT_GPIO[16] */ - {0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /* GPIO[7] : Output mode*/ - {0x0062, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* GPIO[12] : Output mode */ - {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ - {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ - {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*0x90[1]=0 , disable 32k clock*/ - {0x0044, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*0x90[1]=0 , disable 32k clock by indirect access*/ - {0x0040, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x90}, /*0x90[1]=0 , disable 32k clock by indirect access*/ - {0x0041, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x00}, /*0x90[1]=0 , disable 32k clock by indirect access*/ - {0x0042, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x04}, /*0x90[1]=0 , disable 32k clock by indirect access*/ - {0x0081, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0}, /*0x80[15]clean fw init ready bit*/ - {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, -}; - -HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU[] = { - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ - {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ - {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/ - {0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, /*clear suspend enable and power down enable*/ - {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, - {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, -}; - -HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_CARDEMU_TO_PDN[] = { - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ - {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ - {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /* 0x04[16] = 0*/ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /* 0x04[15] = 1*/ - {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, -}; - -HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_PDN_TO_CARDEMU[] = { - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ - {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0}, - {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, -}; - -HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_ACT_TO_LPS[] = { - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ - {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/ - {0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, /*Register write data of 32K calibration*/ - {0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/ - {0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/ - {0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable 32K CLK*/ - {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x42}, /* LPS Option MAC OFF enable*/ - {0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /* LPS Option Enable memory to deep sleep mode*/ - {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, /* enable reg use 32K CLK*/ - {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*PCIe DMA stop*/ - {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*Tx Pause*/ - {0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ - {0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ - {0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ - {0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ - {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/ - {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/ - {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*Whole BB is reset*/ - {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F}, /*Reset MAC TRX*/ - {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*check if removed later*/ - {0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/ - {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /* switch TSF clock to 32K*/ - {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)}, /*Polling 0x109[7]=0 TSF in 40M*/ - {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable WL_LPS_EN*/ - {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, -}; - -HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS[] = { - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ - {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/ - {0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, /*Register write data of 32K calibration*/ - {0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/ - {0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/ - {0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable 32K CLK*/ - {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x40}, /* LPS Option MAC OFF enable*/ - {0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /* LPS Option Enable memory to deep sleep mode*/ - {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, /* enable reg use 32K CLK*/ - {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*PCIe DMA stop*/ - {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*Tx Pause*/ - {0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ - {0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ - {0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ - {0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ - {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/ - {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/ - {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*Whole BB is reset*/ - {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F}, /*Reset MAC TRX*/ - {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*check if removed later*/ - {0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/ - {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /* switch TSF clock to 32K*/ - {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)}, /*Polling 0x109[7]=1 TSF in 32K*/ - {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable WL_LPS_EN*/ - {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, -}; - -HALMAC_WLAN_PWR_CFG HALMAC_RTL8822B_TRANS_LPS_TO_ACT[] = { - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ - {0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*SDIO RPWM*/ - {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/ - {0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), 0}, /*SDIO RPWM*/ - {0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ - {0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ - {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/ - {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0}, /* switch TSF to 40M*/ - {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/ - {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, - {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*nable WMAC TRX*/ - {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, /*nable BB macro*/ - {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, - {0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x03}, /*clear RPWM INT*/ - {0x0124, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/ - {0x0125, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/ - {0x0126, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/ - {0x0127, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/ - {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /* disable reg use 32K CLK*/ - {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /*disable 32k calibration and thermal meter*/ - {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, -}; - -/* Card Enable Array */ -PHALMAC_WLAN_PWR_CFG halmac_8822b_card_enable_flow[] = { - HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU, - HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT, - NULL -}; - -/* Card Disable Array */ -PHALMAC_WLAN_PWR_CFG halmac_8822b_card_disable_flow[] = { - HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU, - HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS, - NULL -}; - -/* Suspend Array */ -PHALMAC_WLAN_PWR_CFG halmac_8822b_suspend_flow[] = { - HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU, - HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS, - NULL -}; - -/* Resume Array */ -PHALMAC_WLAN_PWR_CFG halmac_8822b_resume_flow[] = { - HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU, - HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT, - NULL -}; - -/* HWPDN Array - HW behavior */ -PHALMAC_WLAN_PWR_CFG halmac_8822b_hwpdn_flow[] = { - NULL -}; - -/* Enter LPS - FW behavior */ -PHALMAC_WLAN_PWR_CFG halmac_8822b_enter_lps_flow[] = { - HALMAC_RTL8822B_TRANS_ACT_TO_LPS, - NULL -}; - -/* Enter Deep LPS - FW behavior */ -PHALMAC_WLAN_PWR_CFG halmac_8822b_enter_deep_lps_flow[] = { - HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS, - NULL -}; - -/* Leave LPS -FW behavior */ -PHALMAC_WLAN_PWR_CFG halmac_8822b_leave_lps_flow[] = { - HALMAC_RTL8822B_TRANS_LPS_TO_ACT, - NULL -}; diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h deleted file mode 100644 index 0b8e246..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h +++ /dev/null @@ -1,31 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef HALMAC_POWER_SEQUENCE_8822B -#define HALMAC_POWER_SEQUENCE_8822B - -#include "../../halmac_pwr_seq_cmd.h" - -#define HALMAC_8822B_PWR_SEQ_VER "V21" -extern PHALMAC_WLAN_PWR_CFG halmac_8822b_card_disable_flow[]; -extern PHALMAC_WLAN_PWR_CFG halmac_8822b_card_enable_flow[]; -extern PHALMAC_WLAN_PWR_CFG halmac_8822b_suspend_flow[]; -extern PHALMAC_WLAN_PWR_CFG halmac_8822b_resume_flow[]; -extern PHALMAC_WLAN_PWR_CFG halmac_8822b_hwpdn_flow[]; -extern PHALMAC_WLAN_PWR_CFG halmac_8822b_enter_lps_flow[]; -extern PHALMAC_WLAN_PWR_CFG halmac_8822b_enter_deep_lps_flow[]; -extern PHALMAC_WLAN_PWR_CFG halmac_8822b_leave_lps_flow[]; - -#endif diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.c deleted file mode 100644 index 7dcca57..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.c +++ /dev/null @@ -1,287 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#include "halmac_8822b_cfg.h" -#include "halmac_func_8822b.h" -#include "../halmac_func_88xx.h" -#include "halmac_gpio_8822b.h" - -/** - * halmac_mount_api_8822b() - attach functions to function pointer - * @pHalmac_adapter - * - * SD1 internal use - * - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ -HALMAC_RET_STATUS -halmac_mount_api_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8822B; - pHalmac_adapter->hw_config_info.efuse_size = HALMAC_EFUSE_SIZE_8822B; - pHalmac_adapter->hw_config_info.eeprom_size = HALMAC_EEPROM_SIZE_8822B; - pHalmac_adapter->hw_config_info.bt_efuse_size = HALMAC_BT_EFUSE_SIZE_8822B; - pHalmac_adapter->hw_config_info.cam_entry_num = HALMAC_SECURITY_CAM_ENTRY_NUM_8822B; - pHalmac_adapter->hw_config_info.txdesc_size = HALMAC_TX_DESC_SIZE_8822B; - pHalmac_adapter->hw_config_info.rxdesc_size = HALMAC_RX_DESC_SIZE_8822B; - pHalmac_adapter->hw_config_info.tx_fifo_size = HALMAC_TX_FIFO_SIZE_8822B; - pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_8822B; - pHalmac_adapter->hw_config_info.page_size = HALMAC_TX_PAGE_SIZE_8822B; - pHalmac_adapter->hw_config_info.tx_align_size = HALMAC_TX_ALIGN_SIZE_8822B; - pHalmac_adapter->hw_config_info.page_size_2_power = HALMAC_TX_PAGE_SIZE_2_POWER_8822B; - - pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = HALMAC_RSVD_DRV_PGNUM_8822B; - -#if HALMAC_8822B_SUPPORT - pHalmac_api->halmac_init_trx_cfg = halmac_init_trx_cfg_8822b; - pHalmac_api->halmac_init_protocol_cfg = halmac_init_protocol_cfg_8822b; - pHalmac_api->halmac_init_h2c = halmac_init_h2c_8822b; - pHalmac_api->halmac_pinmux_get_func = halmac_pinmux_get_func_8822b; - pHalmac_api->halmac_pinmux_set_func = halmac_pinmux_set_func_8822b; - pHalmac_api->halmac_pinmux_free_func = halmac_pinmux_free_func_8822b; - - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { - pHalmac_api->halmac_tx_allowed_sdio = halmac_tx_allowed_sdio_88xx; - pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_sdio_not_support_88xx; - pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8822b_sdio; - pHalmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_sdio; - pHalmac_api->halmac_interface_integration_tuning = halmac_interface_integration_tuning_8822b_sdio; - } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) { - pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8822b_usb; - pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_usb_not_support_88xx; - pHalmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_usb; - pHalmac_api->halmac_interface_integration_tuning = halmac_interface_integration_tuning_8822b_usb; - } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) { - pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8822b_pcie; - pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_pcie_not_support_88xx; - pHalmac_api->halmac_pcie_switch = halmac_pcie_switch_8822b; - pHalmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_pcie; - pHalmac_api->halmac_interface_integration_tuning = halmac_interface_integration_tuning_8822b_pcie; - } else { - pHalmac_api->halmac_pcie_switch = halmac_pcie_switch_8822b_nc; - } -#endif - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_init_trx_cfg_8822b() - config trx dma register - * @pHalmac_adapter : the adapter of halmac - * @halmac_trx_mode : trx mode selection - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_init_trx_cfg_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode -) -{ - u8 value8; - u32 value32; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - pHalmac_adapter->trx_mode = halmac_trx_mode; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_trx_cfg ==========>halmac_trx_mode = %d\n", halmac_trx_mode); - - status = halmac_txdma_queue_mapping_8822b(pHalmac_adapter, halmac_trx_mode); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_txdma_queue_mapping fail!\n"); - return status; - } - - value8 = 0; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); - value8 = HALMAC_CR_TRX_ENABLE_8822B; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31)); - - status = halmac_priority_queue_config_8822b(pHalmac_adapter, halmac_trx_mode); - if (pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode != HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_DRVINFO_SZ, HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B >> 3); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_txdma_queue_mapping fail!\n"); - return status; - } - - /* Config H2C packet buffer */ - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_HEAD); - value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_HEAD, value32); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_READ_ADDR); - value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_READ_ADDR, value32); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_TAIL); - value32 = (value32 & 0xFFFC0000) | ((pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B) + (HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B << HALMAC_TX_PAGE_SIZE_2_POWER_8822B)); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_TAIL, value32); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO); - value8 = (u8)((value8 & 0xFC) | 0x01); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO); - value8 = (u8)((value8 & 0xFB) | 0x04); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1); - value8 = (u8)((value8 & 0x7f) | 0x80); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8); - - pHalmac_adapter->h2c_buff_size = HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B << HALMAC_TX_PAGE_SIZE_2_POWER_8822B; - halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter); - - if (pHalmac_adapter->h2c_buff_size != pHalmac_adapter->h2c_buf_free_space) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "get h2c free space error!\n"); - return HALMAC_RET_GET_H2C_SPACE_ERR; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_trx_cfg <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_init_protocol_cfg_8822b() - config protocol register - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_init_protocol_cfg_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u32 value32; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_init_protocol_cfg_8822b ==========>\n"); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AMPDU_MAX_TIME_V1, HALMAC_AMPDU_MAX_TIME_8822B); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); - - value32 = HALMAC_PROT_RTS_LEN_TH_8822B | (HALMAC_PROT_RTS_TX_TIME_TH_8822B << 8) | - (HALMAC_PROT_MAX_AGG_PKT_LIMIT_8822B << 16) | (HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8822B << 24); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PROT_MODE_CTRL, value32); - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BAR_MODE_CTRL + 2, HALMAC_BAR_RETRY_LIMIT_8822B | HALMAC_RA_TRY_RATE_AGG_LIMIT_8822B << 8); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_VOVI_SETTING, HALMAC_FAST_EDCA_VO_TH_8822B); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_VOVI_SETTING + 2, HALMAC_FAST_EDCA_VI_TH_8822B); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_BEBK_SETTING, HALMAC_FAST_EDCA_BE_TH_8822B); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_BEBK_SETTING + 2, HALMAC_FAST_EDCA_BK_TH_8822B); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_init_protocol_cfg_8822b <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_init_h2c_8822b() - config h2c packet buffer - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_init_h2c_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u8 value8; - u32 value32; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - value8 = 0; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); - value8 = HALMAC_CR_TRX_ENABLE_8822B; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_HEAD); - value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_HEAD, value32); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_READ_ADDR); - value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_READ_ADDR, value32); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_TAIL); - value32 = (value32 & 0xFFFC0000) | ((pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B) + (HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B << HALMAC_TX_PAGE_SIZE_2_POWER_8822B)); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_TAIL, value32); - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO); - value8 = (u8)((value8 & 0xFC) | 0x01); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO); - value8 = (u8)((value8 & 0xFB) | 0x04); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1); - value8 = (u8)((value8 & 0x7f) | 0x80); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8); - - pHalmac_adapter->h2c_buff_size = HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B << HALMAC_TX_PAGE_SIZE_2_POWER_8822B; - halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter); - - if (pHalmac_adapter->h2c_buff_size != pHalmac_adapter->h2c_buf_free_space) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "get h2c free space error!\n"); - return HALMAC_RET_GET_H2C_SPACE_ERR; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "h2c free space : %d\n", pHalmac_adapter->h2c_buf_free_space); - - return HALMAC_RET_SUCCESS; -} diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.h deleted file mode 100644 index 846a0d3..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.h +++ /dev/null @@ -1,44 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_API_8822B_H_ -#define _HALMAC_API_8822B_H_ - -#include "../../halmac_2_platform.h" -#include "../../halmac_type.h" - -HALMAC_RET_STATUS -halmac_mount_api_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_init_trx_cfg_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode -); - -HALMAC_RET_STATUS -halmac_init_protocol_cfg_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_init_h2c_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter -); - - -#endif/* _HALMAC_API_8822B_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c deleted file mode 100644 index 471d452..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c +++ /dev/null @@ -1,265 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#include "../halmac_88xx_cfg.h" -#include "../halmac_api_88xx_pcie.h" -#include "halmac_8822b_cfg.h" - -/** - * halmac_mac_power_switch_8822b_pcie() - switch mac power - * @pHalmac_adapter : the adapter of halmac - * @halmac_power : power state - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_mac_power_switch_8822b_pcie( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_MAC_POWER halmac_power -) -{ - u8 interface_mask; - u8 value8; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_mac_power_switch_88xx_pcie halmac_power = %x ==========>\n", halmac_power); - interface_mask = HALMAC_PWR_INTF_PCI_MSK; - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR); - if (value8 == 0xEA) - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; - else - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; - - /* Check if power switch is needed */ - if (halmac_power == HALMAC_MAC_POWER_ON && pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "[WARN]halmac_mac_power_switch power state unchange!\n"); - return HALMAC_RET_PWR_UNCHANGE; - } - - if (halmac_power == HALMAC_MAC_POWER_OFF) { - if (halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, - interface_mask, halmac_8822b_card_disable_flow) != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Handle power off cmd error\n"); - return HALMAC_RET_POWER_OFF_FAIL; - } - - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE; - pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; - halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter); - } else { - if (halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, - interface_mask, halmac_8822b_card_enable_flow) != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Handle power on cmd error\n"); - return HALMAC_RET_POWER_ON_FAIL; - } - - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_mac_power_switch_88xx_pcie <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_pcie_switch_8822b() - pcie gen1/gen2 switch - * @pHalmac_adapter : the adapter of halmac - * @pcie_cfg : gen1/gen2 selection - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_pcie_switch_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_PCIE_CFG pcie_cfg -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - u8 current_link_speed = 0; - u32 count = 0; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_pcie_switch_8822b ==========>\n"); - - /** - * Link Control 2 Register[3:0] Target Link Speed - * Defined encodings are: - * 0001b Target Link 2.5 GT/s - * 0010b Target Link 5.0 GT/s - * 0100b Target Link 8.0 GT/s - */ - - if (pcie_cfg == HALMAC_PCIE_GEN1) { - /* cfg 0xA0[3:0]=4'b0001 */ - halmac_dbi_write8_88xx(pHalmac_adapter, LINK_CTRL2_REG_OFFSET, (halmac_dbi_read8_88xx(pHalmac_adapter, LINK_CTRL2_REG_OFFSET) & 0xF0) | BIT(0)); - - /* cfg 0x80C[17]=1 //PCIe DesignWave */ - halmac_dbi_write32_88xx(pHalmac_adapter, GEN2_CTRL_OFFSET, halmac_dbi_read32_88xx(pHalmac_adapter, GEN2_CTRL_OFFSET) | BIT(17)); - - /* check link speed if GEN1 */ - /* cfg 0x82[3:0]=4'b0001 */ - current_link_speed = halmac_dbi_read8_88xx(pHalmac_adapter, LINK_STATUS_REG_OFFSET) & 0x0F; - count = 2000; - - while ((current_link_speed != HALMAC_PCIE_GEN1_SPEED_88XX) && (count != 0)) { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); - current_link_speed = halmac_dbi_read8_88xx(pHalmac_adapter, LINK_STATUS_REG_OFFSET) & 0x0F; - count--; - } - - if (current_link_speed != HALMAC_PCIE_GEN1_SPEED_88XX) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Speed change to GEN1 fail !\n"); - return HALMAC_RET_FAIL; - } - - } else if (pcie_cfg == HALMAC_PCIE_GEN2) { - /* cfg 0xA0[3:0]=4'b0010 */ - halmac_dbi_write8_88xx(pHalmac_adapter, LINK_CTRL2_REG_OFFSET, (halmac_dbi_read8_88xx(pHalmac_adapter, LINK_CTRL2_REG_OFFSET) & 0xF0) | BIT(1)); - - /* cfg 0x80C[17]=1 //PCIe DesignWave */ - halmac_dbi_write32_88xx(pHalmac_adapter, GEN2_CTRL_OFFSET, halmac_dbi_read32_88xx(pHalmac_adapter, GEN2_CTRL_OFFSET) | BIT(17)); - - /* check link speed if GEN2 */ - /* cfg 0x82[3:0]=4'b0010 */ - current_link_speed = halmac_dbi_read8_88xx(pHalmac_adapter, LINK_STATUS_REG_OFFSET) & 0x0F; - count = 2000; - - while ((current_link_speed != HALMAC_PCIE_GEN2_SPEED_88XX) && (count != 0)) { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); - current_link_speed = halmac_dbi_read8_88xx(pHalmac_adapter, LINK_STATUS_REG_OFFSET) & 0x0F; - count--; - } - - if (current_link_speed != HALMAC_PCIE_GEN2_SPEED_88XX) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Speed change to GEN1 fail !\n"); - return HALMAC_RET_FAIL; - } - - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Error Speed !\n"); - return HALMAC_RET_FAIL; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_pcie_switch_8822b <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_pcie_switch_8822b_nc( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_PCIE_CFG pcie_cfg -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_pcie_switch_8822b_nc ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_pcie_switch_8822b_nc <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_phy_cfg_8822b_pcie() - phy config - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_phy_cfg_8822b_pcie( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_INTF_PHY_PLATFORM platform -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_phy_cfg ==========>\n"); - - status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8822B_PCIE_PHY_GEN1, platform, HAL_INTF_PHY_PCIE_GEN1); - - if (status != HALMAC_RET_SUCCESS) - return status; - - status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8822B_PCIE_PHY_GEN2, platform, HAL_INTF_PHY_PCIE_GEN2); - - if (status != HALMAC_RET_SUCCESS) - return status; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_phy_cfg <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_interface_integration_tuning_8822b_pcie() - pcie interface fine tuning - * @pHalmac_adapter : the adapter of halmac - * Author : Rick Liu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_interface_integration_tuning_8822b_pcie( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - return HALMAC_RET_SUCCESS; -} diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h deleted file mode 100644 index 2371c19..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h +++ /dev/null @@ -1,54 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_API_8822B_PCIE_H_ -#define _HALMAC_API_8822B_PCIE_H_ - -#include "../../halmac_2_platform.h" -#include "../../halmac_type.h" - -extern HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_PCIE_PHY_GEN1[]; -extern HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_PCIE_PHY_GEN2[]; - -HALMAC_RET_STATUS -halmac_mac_power_switch_8822b_pcie( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_MAC_POWER halmac_power -); - -HALMAC_RET_STATUS -halmac_pcie_switch_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_PCIE_CFG pcie_cfg -); - -HALMAC_RET_STATUS -halmac_pcie_switch_8822b_nc( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_PCIE_CFG pcie_cfg -); - -HALMAC_RET_STATUS -halmac_phy_cfg_8822b_pcie( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_INTF_PHY_PLATFORM platform -); - -HALMAC_RET_STATUS -halmac_interface_integration_tuning_8822b_pcie( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -#endif/* _HALMAC_API_8822B_PCIE_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c deleted file mode 100644 index 50d1407..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c +++ /dev/null @@ -1,156 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#include "halmac_8822b_cfg.h" - -/** - * halmac_mac_power_switch_8822b_sdio() - switch mac power - * @pHalmac_adapter : the adapter of halmac - * @halmac_power : power state - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_mac_power_switch_8822b_sdio( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_MAC_POWER halmac_power -) -{ - u8 interface_mask; - u8 value8; - u8 rpwm; - u32 imr_backup; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_mac_power_switch_88xx_sdio==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_power = %x ==========>\n", halmac_power); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]8822B pwr seq ver = %s\n", HALMAC_8822B_PWR_SEQ_VER); - - interface_mask = HALMAC_PWR_INTF_SDIO_MSK; - - pHalmac_adapter->rpwm_record = HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HRPWM1); - - /* Check FW still exist or not */ - if (HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) == 0xC078) { - /* Leave 32K */ - rpwm = (u8)((pHalmac_adapter->rpwm_record ^ BIT(7)) & 0x80); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HRPWM1, rpwm); - } - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR); - if (value8 == 0xEA) - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; - else - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; - - /*Check if power switch is needed*/ - if (halmac_power == HALMAC_MAC_POWER_ON && pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "[WARN]halmac_mac_power_switch power state unchange!\n"); - return HALMAC_RET_PWR_UNCHANGE; - } - - imr_backup = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_HIMR); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_HIMR, 0); - - if (halmac_power == HALMAC_MAC_POWER_OFF) { - if (halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, - interface_mask, halmac_8822b_card_disable_flow) != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Handle power off cmd error\n"); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_HIMR, imr_backup); - return HALMAC_RET_POWER_OFF_FAIL; - } - - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE; - pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; - halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter); - } else { - if (halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, - interface_mask, halmac_8822b_card_enable_flow) != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Handle power on cmd error\n"); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_HIMR, imr_backup); - return HALMAC_RET_POWER_ON_FAIL; - } - - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT; - } - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_HIMR, imr_backup); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_mac_power_switch_88xx_sdio <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_phy_cfg_8822b_sdio() - phy config - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_phy_cfg_8822b_sdio( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_INTF_PHY_PLATFORM platform -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "sdio no phy\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_interface_integration_tuning_8822b_sdio() - sdio interface fine tuning - * @pHalmac_adapter : the adapter of halmac - * Author : Ivan - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_interface_integration_tuning_8822b_sdio( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - return HALMAC_RET_SUCCESS; -} \ No newline at end of file diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h deleted file mode 100644 index 36b70ac..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h +++ /dev/null @@ -1,48 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_API_8822B_SDIO_H_ -#define _HALMAC_API_8822B_SDIO_H_ - -#include "../../halmac_2_platform.h" -#include "../../halmac_type.h" - -HALMAC_RET_STATUS -halmac_mac_power_switch_8822b_sdio( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_MAC_POWER halmac_power -); - -#if 0 -HALMAC_RET_STATUS -halmac_tx_allowed_sdio_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHalmac_buf, - IN u32 halmac_size -); -#endif - -HALMAC_RET_STATUS -halmac_phy_cfg_8822b_sdio( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_INTF_PHY_PLATFORM platform -); - -HALMAC_RET_STATUS -halmac_interface_integration_tuning_8822b_sdio( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -#endif/* _HALMAC_API_8822B_SDIO_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c deleted file mode 100644 index f7956f4..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c +++ /dev/null @@ -1,162 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#include "../halmac_88xx_cfg.h" -#include "halmac_8822b_cfg.h" - -/** - * halmac_mac_power_switch_8822b_usb() - switch mac power - * @pHalmac_adapter : the adapter of halmac - * @halmac_power : power state - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_mac_power_switch_8822b_usb( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_MAC_POWER halmac_power -) -{ - u8 interface_mask; - u8 value8; - u8 rpwm; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_mac_power_switch_88xx_usb halmac_power = %x ==========>\n", halmac_power); - - interface_mask = HALMAC_PWR_INTF_USB_MSK; - - pHalmac_adapter->rpwm_record = HALMAC_REG_READ_8(pHalmac_adapter, 0xFE58); - - /* Check FW still exist or not */ - if (HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) == 0xC078) { - /* Leave 32K */ - rpwm = (u8)((pHalmac_adapter->rpwm_record ^ BIT(7)) & 0x80); - HALMAC_REG_WRITE_8(pHalmac_adapter, 0xFE58, rpwm); - } - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR); - if (value8 == 0xEA) { - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; - } else { - if (BIT(0) == (HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_STATUS1 + 1) & BIT(0))) - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; - else - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; - } - - /*Check if power switch is needed*/ - if (halmac_power == HALMAC_MAC_POWER_ON && pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "halmac_mac_power_switch power state unchange!\n"); - return HALMAC_RET_PWR_UNCHANGE; - } - - if (halmac_power == HALMAC_MAC_POWER_OFF) { - if (halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, - interface_mask, halmac_8822b_card_disable_flow) != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power off cmd error\n"); - return HALMAC_RET_POWER_OFF_FAIL; - } - - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE; - pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; - halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter); - } else { - if (halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, - interface_mask, halmac_8822b_card_enable_flow) != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power on cmd error\n"); - return HALMAC_RET_POWER_ON_FAIL; - } - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_STATUS1 + 1, HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_STATUS1 + 1) & ~(BIT(0))); - - pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; - pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_mac_power_switch_88xx_usb <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_phy_cfg_8822b_usb() - phy config - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_phy_cfg_8822b_usb( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_INTF_PHY_PLATFORM platform -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg ==========>\n"); - - status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8822B_USB2_PHY, platform, HAL_INTF_PHY_USB2); - - if (status != HALMAC_RET_SUCCESS) - return status; - - status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8822B_USB3_PHY, platform, HAL_INTF_PHY_USB3); - - if (status != HALMAC_RET_SUCCESS) - return status; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_interface_integration_tuning_8822b_usb() - usb interface fine tuning - * @pHalmac_adapter : the adapter of halmac - * Author : Ivan - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_interface_integration_tuning_8822b_usb( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - return HALMAC_RET_SUCCESS; -} diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h deleted file mode 100644 index fdae4e2..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h +++ /dev/null @@ -1,42 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_API_8822B_USB_H_ -#define _HALMAC_API_8822B_USB_H_ - -extern HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_USB2_PHY[]; -extern HALMAC_INTF_PHY_PARA HALMAC_RTL8822B_USB3_PHY[]; - -#include "../../halmac_2_platform.h" -#include "../../halmac_type.h" - -HALMAC_RET_STATUS -halmac_mac_power_switch_8822b_usb( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_MAC_POWER halmac_power -); - -HALMAC_RET_STATUS -halmac_phy_cfg_8822b_usb( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_INTF_PHY_PLATFORM platform -); - -HALMAC_RET_STATUS -halmac_interface_integration_tuning_8822b_usb( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -#endif/* _HALMAC_API_8822B_USB_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.c deleted file mode 100644 index 8b80fc3..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.c +++ /dev/null @@ -1,333 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#include "halmac_8822b_cfg.h" -#if HALMAC_PLATFORM_WINDOWS -/*SDIO RQPN Mapping for Windows, extra queue is not implemented in Driver code*/ -HALMAC_RQPN HALMAC_RQPN_SDIO_8822B[] = { - /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ - {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, -}; -#else -/*SDIO RQPN Mapping*/ -HALMAC_RQPN HALMAC_RQPN_SDIO_8822B[] = { - /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ - {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, -}; -#endif - -/*PCIE RQPN Mapping*/ -HALMAC_RQPN HALMAC_RQPN_PCIE_8822B[] = { - /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ - {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, -}; - -/*USB 2 Bulkout RQPN Mapping*/ -HALMAC_RQPN HALMAC_RQPN_2BULKOUT_8822B[] = { - /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ - {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, -}; - -/*USB 3 Bulkout RQPN Mapping*/ -HALMAC_RQPN HALMAC_RQPN_3BULKOUT_8822B[] = { - /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ - {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, -}; - -/*USB 4 Bulkout RQPN Mapping*/ -HALMAC_RQPN HALMAC_RQPN_4BULKOUT_8822B[] = { - /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ - {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, - {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, -}; - -#if HALMAC_PLATFORM_WINDOWS -/*SDIO Page Number*/ -HALMAC_PG_NUM HALMAC_PG_NUM_SDIO_8822B[] = { - /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ - {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1}, - {HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 0, 1}, - {HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1}, - {HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1}, - {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 640}, - {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 640}, -}; -#else -/*SDIO Page Number*/ -HALMAC_PG_NUM HALMAC_PG_NUM_SDIO_8822B[] = { - /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ - {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1}, - {HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 32, 1}, - {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1}, - {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1}, - {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640}, - {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640}, -}; -#endif - -/*PCIE Page Number*/ -HALMAC_PG_NUM HALMAC_PG_NUM_PCIE_8822B[] = { - /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ - {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1}, - {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1}, - {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1}, - {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1}, - {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640}, - {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640}, -}; - -/*USB 2 Bulkout Page Number*/ -HALMAC_PG_NUM HALMAC_PG_NUM_2BULKOUT_8822B[] = { - /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ - {HALMAC_TRX_MODE_NORMAL, 64, 64, 0, 0, 1}, - {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 0, 0, 1}, - {HALMAC_TRX_MODE_WMM, 64, 64, 0, 0, 1}, - {HALMAC_TRX_MODE_P2P, 64, 64, 0, 0, 1}, - {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1024}, - {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1024}, -}; - -/*USB 3 Bulkout Page Number*/ -HALMAC_PG_NUM HALMAC_PG_NUM_3BULKOUT_8822B[] = { - /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ - {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1}, - {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 0, 1}, - {HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1}, - {HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1}, - {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1024}, - {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1024}, -}; - -/*USB 4 Bulkout Page Number*/ -HALMAC_PG_NUM HALMAC_PG_NUM_4BULKOUT_8822B[] = { - /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ - {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1}, - {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1}, - {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1}, - {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1}, - {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640}, - {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640}, -}; - -HALMAC_RET_STATUS -halmac_txdma_queue_mapping_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode -) -{ - u16 value16; - VOID *pDriver_adapter = NULL; - PHALMAC_RQPN pCurr_rqpn_Sel = NULL; - HALMAC_RET_STATUS status; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { - pCurr_rqpn_Sel = HALMAC_RQPN_SDIO_8822B; - } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) { - pCurr_rqpn_Sel = HALMAC_RQPN_PCIE_8822B; - } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) { - if (pHalmac_adapter->halmac_bulkout_num == 2) { - pCurr_rqpn_Sel = HALMAC_RQPN_2BULKOUT_8822B; - } else if (pHalmac_adapter->halmac_bulkout_num == 3) { - pCurr_rqpn_Sel = HALMAC_RQPN_3BULKOUT_8822B; - } else if (pHalmac_adapter->halmac_bulkout_num == 4) { - pCurr_rqpn_Sel = HALMAC_RQPN_4BULKOUT_8822B; - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]interface not support\n"); - return HALMAC_RET_NOT_SUPPORT; - } - } else { - return HALMAC_RET_NOT_SUPPORT; - } - - status = halmac_rqpn_parser_88xx(pHalmac_adapter, halmac_trx_mode, pCurr_rqpn_Sel); - if (status != HALMAC_RET_SUCCESS) - return status; - - value16 = 0; - value16 |= BIT_TXDMA_HIQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]); - value16 |= BIT_TXDMA_MGQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]); - value16 |= BIT_TXDMA_BKQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]); - value16 |= BIT_TXDMA_BEQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]); - value16 |= BIT_TXDMA_VIQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]); - value16 |= BIT_TXDMA_VOQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXDMA_PQ_MAP, value16); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_priority_queue_config_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode -) -{ - u8 transfer_mode = 0; - u8 value8; - u32 counter; - HALMAC_RET_STATUS status; - PHALMAC_PG_NUM pCurr_pg_num = NULL; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (pHalmac_adapter->txff_allocation.la_mode == HALMAC_LA_MODE_DISABLE) { - if (pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode == HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) { - pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_8822B >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B; - } else if (pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode == HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK) { - pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B; - pHalmac_adapter->hw_config_info.tx_fifo_size = HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B; - if (HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B <= HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_MAX_8822B) - pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B; - else - pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_MAX_8822B; - } else { - pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_8822B >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]rx_fifo_expanding_mode = %d not support\n", pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode); - } - } else { - pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_LA_8822B >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B; - } - pHalmac_adapter->txff_allocation.rsvd_pg_num = (pHalmac_adapter->txff_allocation.rsvd_drv_pg_num + - HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B + - HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B + - HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B + - HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B); - if (pHalmac_adapter->txff_allocation.rsvd_pg_num > pHalmac_adapter->txff_allocation.tx_fifo_pg_num) - return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL; - - pHalmac_adapter->txff_allocation.ac_q_pg_num = pHalmac_adapter->txff_allocation.tx_fifo_pg_num - pHalmac_adapter->txff_allocation.rsvd_pg_num; - pHalmac_adapter->txff_allocation.rsvd_pg_bndy = pHalmac_adapter->txff_allocation.tx_fifo_pg_num - pHalmac_adapter->txff_allocation.rsvd_pg_num; - pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy = pHalmac_adapter->txff_allocation.tx_fifo_pg_num - HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B; - pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy - HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B; - pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy - HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B; - pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy - HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B; - pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_drv_pg_num; - - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { - pCurr_pg_num = HALMAC_PG_NUM_SDIO_8822B; - } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) { - pCurr_pg_num = HALMAC_PG_NUM_PCIE_8822B; - } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) { - if (pHalmac_adapter->halmac_bulkout_num == 2) { - pCurr_pg_num = HALMAC_PG_NUM_2BULKOUT_8822B; - } else if (pHalmac_adapter->halmac_bulkout_num == 3) { - pCurr_pg_num = HALMAC_PG_NUM_3BULKOUT_8822B; - } else if (pHalmac_adapter->halmac_bulkout_num == 4) { - pCurr_pg_num = HALMAC_PG_NUM_4BULKOUT_8822B; - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]interface not support\n"); - return HALMAC_RET_NOT_SUPPORT; - } - } else { - return HALMAC_RET_NOT_SUPPORT; - } - - status = halmac_pg_num_parser_88xx(pHalmac_adapter, halmac_trx_mode, pCurr_pg_num); - if (status != HALMAC_RET_SUCCESS) - return status; - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, pHalmac_adapter->txff_allocation.high_queue_pg_num); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_2, pHalmac_adapter->txff_allocation.low_queue_pg_num); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_3, pHalmac_adapter->txff_allocation.normal_queue_pg_num); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_4, pHalmac_adapter->txff_allocation.extra_queue_pg_num); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_5, pHalmac_adapter->txff_allocation.pub_queue_pg_num); - - pHalmac_adapter->sdio_free_space.high_queue_number = pHalmac_adapter->txff_allocation.high_queue_pg_num; - pHalmac_adapter->sdio_free_space.normal_queue_number = pHalmac_adapter->txff_allocation.normal_queue_pg_num; - pHalmac_adapter->sdio_free_space.low_queue_number = pHalmac_adapter->txff_allocation.low_queue_pg_num; - pHalmac_adapter->sdio_free_space.public_queue_number = pHalmac_adapter->txff_allocation.pub_queue_pg_num; - pHalmac_adapter->sdio_free_space.extra_queue_number = pHalmac_adapter->txff_allocation.extra_queue_pg_num; - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31)); - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BCNQ_BDNY_V1, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCNQ_PGBNDY_V1)); - - /*20170223 Soar*/ - /*SDIO sometimes use two CMD52 to do HALMAC_REG_WRITE_16 and may cause a mismatch between HW status and Reg value.*/ - /*A patch is to write it again*/ - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BCNQ_BDNY_V1, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCNQ_PGBNDY_V1)); - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BCNQ1_BDNY_V1, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCNQ_PGBNDY_V1)); - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RXFF_BNDY, pHalmac_adapter->hw_config_info.rx_fifo_size - HALMAC_C2H_PKT_BUF_8822B - 1); - - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) { - value8 = (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) & ~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM)); - value8 = (u8)(value8 | (HALMAC_BLK_DESC_NUM_8822B << BIT_SHIFT_BLK_DESC_NUM)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1, value8); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1 + 3, HALMAC_BLK_DESC_NUM_8822B); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1, HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1) | BIT(1)); - } - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) | BIT_AUTO_INIT_LLT_V1)); - counter = 1000; - while (HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) & BIT_AUTO_INIT_LLT_V1) { - counter--; - if (counter == 0) - return HALMAC_RET_INIT_LLT_FAIL; - } - - if (halmac_trx_mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) { - transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY; - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_WMAC_LBK_BUF_HD_V1, (u16)pHalmac_adapter->txff_allocation.rsvd_pg_bndy); - } else if (halmac_trx_mode == HALMAC_TRX_MODE_LOOPBACK) { - transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT; - } else { - transfer_mode = HALMAC_TRNSFER_NORMAL; - } - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 3, (u8)transfer_mode); - - return HALMAC_RET_SUCCESS; -} diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.h deleted file mode 100644 index be7906e..0000000 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.h +++ /dev/null @@ -1,33 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_FUNC_8822B_H_ -#define _HALMAC_FUNC_8822B_H_ - -#include "../../halmac_type.h" - -HALMAC_RET_STATUS -halmac_txdma_queue_mapping_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode -); - -HALMAC_RET_STATUS -halmac_priority_queue_config_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode -); - -#endif /* _HALMAC_FUNC_8822B_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c index d336323..13f3554 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -18,198 +18,485 @@ #if HALMAC_8822B_SUPPORT -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO0_8822B[] = { - HALMAC_GPIO0_BT_GPIO0_8822B, - HALMAC_GPIO0_BT_ACT_8822B, - HALMAC_GPIO0_WL_ACT_8822B, - HALMAC_GPIO0_WLMAC_DBG_GPIO0_8822B, - HALMAC_GPIO0_WLPHY_DBG_GPIO0_8822B, - HALMAC_GPIO0_BT_DBG_GPIO0_8822B, - HALMAC_GPIO0_SW_IO_8822B +/* GPIO0 definition */ +#define GPIO0_BT_GPIO0_8822B \ + {HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(2), BIT(2)} +#define GPIO0_BT_ACT_8822B \ + {HALMAC_BT_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \ + 0x41, BIT(1), 0} +#define GPIO0_WL_ACT_8822B \ + {HALMAC_WL_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \ + 0x41, BIT(2), BIT(2)} +#define GPIO0_WLMAC_DBG_GPIO0_8822B \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO0_WLPHY_DBG_GPIO0_8822B \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO0_BT_DBG_GPIO0_8822B \ + {HALMAC_BT_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO0_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO1 definition */ +#define GPIO1_BT_GPIO1_8822B \ + {HALMAC_BT_GPIO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(2), BIT(2)} +#define GPIO1_BT_3DD_SYNC_A_8822B \ + {HALMAC_BT_3DDLS_A, HALMAC_GPIO1, HALMAC_GPIO_IN, \ + 0x66, BIT(2), BIT(2)} +#define GPIO1_WL_CK_8822B \ + {HALMAC_BT_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \ + 0x41, BIT(1), 0} +#define GPIO1_BT_CK_8822B \ + {HALMAC_WL_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \ + 0x41, BIT(2), BIT(2)} +#define GPIO1_WLMAC_DBG_GPIO1_8822B \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO1_WLPHY_DBG_GPIO1_8822B \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO1_BT_DBG_GPIO1_8822B \ + {HALMAC_BT_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO1_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO2 definition */ +#define GPIO2_BT_GPIO2_8822B \ + {HALMAC_BT_GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(2), BIT(2)} +#define GPIO2_WL_STATE_8822B \ + {HALMAC_BT_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \ + 0x41, BIT(1), 0} +#define GPIO2_BT_STATE_8822B \ + {HALMAC_WL_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \ + 0x41, BIT(2), BIT(2)} +#define GPIO2_WLMAC_DBG_GPIO2_8822B \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO2_WLPHY_DBG_GPIO2_8822B \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO2_BT_DBG_GPIO2_8822B \ + {HALMAC_BT_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO2_RFE_CTRL_5_8822B \ + {HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(2), BIT(2)} +#define GPIO2_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO3 definition */ +#define GPIO3_BT_GPIO3_8822B \ + {HALMAC_BT_GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(2), BIT(2)} +#define GPIO3_WL_PRI_8822B \ + {HALMAC_BT_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \ + 0x41, BIT(1), 0} +#define GPIO3_BT_PRI_8822B \ + {HALMAC_WL_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \ + 0x41, BIT(2), BIT(2)} +#define GPIO3_WLMAC_DBG_GPIO3_8822B \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO3_WLPHY_DBG_GPIO3_8822B \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO3_BT_DBG_GPIO3_8822B \ + {HALMAC_BT_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO3_RFE_CTRL_4_8822B \ + {HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(2), BIT(2)} +#define GPIO3_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO4 definition */ +#define GPIO4_BT_SPI_D0_8822B \ + {HALMAC_BT_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(4), BIT(4)} +#define GPIO4_WL_SPI_D0_8822B \ + {HALMAC_WL_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \ + 0x42, BIT(3), BIT(3)} +#define GPIO4_SDIO_INT_8822B \ + {HALMAC_SDIO_INT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \ + 0x72, BIT(2), BIT(2)} +#define GPIO4_JTAG_TRST_8822B \ + {HALMAC_JTAG, HALMAC_GPIO4, HALMAC_GPIO_IN, \ + 0x67, BIT(0), BIT(0)} +#define GPIO4_DBG_GNT_WL_8822B \ + {HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \ + 0x73, BIT(3), BIT(3)} +#define GPIO4_WLMAC_DBG_GPIO4_8822B \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO4_WLPHY_DBG_GPIO4_8822B \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO4_BT_DBG_GPIO4_8822B \ + {HALMAC_BT_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO4_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO5 definition */ +#define GPIO5_BT_SPI_D1_8822B \ + {HALMAC_BT_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(4), BIT(4)} +#define GPIO5_WL_SPI_D1_8822B \ + {HALMAC_WL_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \ + 0x42, BIT(3), BIT(3)} +#define GPIO5_JTAG_TDI_8822B \ + {HALMAC_JTAG, HALMAC_GPIO5, HALMAC_GPIO_IN, \ + 0x67, BIT(0), BIT(0)} +#define GPIO5_DBG_GNT_BT_8822B \ + {HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO5, HALMAC_GPIO_OUT, \ + 0x73, BIT(3), BIT(3)} +#define GPIO5_WLMAC_DBG_GPIO5_8822B \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO5_WLPHY_DBG_GPIO5_8822B \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO5_BT_DBG_GPIO5_8822B \ + {HALMAC_BT_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO5_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO6 definition */ +#define GPIO6_BT_SPI_D2_8822B \ + {HALMAC_BT_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(4), BIT(4)} +#define GPIO6_WL_SPI_D2_8822B \ + {HALMAC_WL_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \ + 0x42, BIT(3), BIT(3)} +#define GPIO6_EEDO_8822B \ + {HALMAC_EEPROM, HALMAC_GPIO6, HALMAC_GPIO_IN, \ + 0x40, BIT(4), BIT(4)} +#define GPIO6_JTAG_TDO_8822B \ + {HALMAC_JTAG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \ + 0x67, BIT(0), BIT(0)} +#define GPIO6_BT_3DD_SYNC_B_8822B \ + {HALMAC_BT_3DDLS_B, HALMAC_GPIO6, HALMAC_GPIO_IN, \ + 0x67, BIT(1), BIT(1)} +#define GPIO6_BT_GPIO18_8822B \ + {HALMAC_BT_GPIO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \ + 0x67, BIT(1), BIT(1)} +#define GPIO6_SIN_8822B \ + {HALMAC_WL_UART, HALMAC_GPIO6, HALMAC_GPIO_IN, \ + 0x41, BIT(0), BIT(0)} +#define GPIO6_WLMAC_DBG_GPIO6_8822B \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO6_WLPHY_DBG_GPIO6_8822B \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO6_BT_DBG_GPIO6_8822B \ + {HALMAC_BT_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO6_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO7 definition */ +#define GPIO7_BT_SPI_D3_8822B \ + {HALMAC_BT_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(4), BIT(4)} +#define GPIO7_WL_SPI_D3_8822B \ + {HALMAC_WL_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \ + 0x42, BIT(3), BIT(3)} +#define GPIO7_EEDI_8822B \ + {HALMAC_EEPROM, HALMAC_GPIO7, HALMAC_GPIO_OUT, \ + 0x40, BIT(4), BIT(4)} +#define GPIO7_JTAG_TMS_8822B \ + {HALMAC_JTAG, HALMAC_GPIO7, HALMAC_GPIO_IN, \ + 0x67, BIT(0), BIT(0)} +#define GPIO7_BT_GPIO16_8822B \ + {HALMAC_BT_GPIO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \ + 0x67, BIT(2), BIT(2)} +#define GPIO7_SOUT_8822B \ + {HALMAC_WL_UART, HALMAC_GPIO7, HALMAC_GPIO_OUT, \ + 0x41, BIT(0), BIT(0)} +#define GPIO7_WLMAC_DBG_GPIO7_8822B \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO7_WLPHY_DBG_GPIO7_8822B \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO7_BT_DBG_GPIO7_8822B \ + {HALMAC_BT_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO7_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO8 definition */ +#define GPIO8_WL_EXT_WOL_8822B \ + {HALMAC_WL_HW_EXTWOL, HALMAC_GPIO8, HALMAC_GPIO_IN, \ + 0x4a, BIT(0) | BIT(1), BIT(0) | BIT(1)} +#define GPIO8_WL_LED_8822B \ + {HALMAC_WL_LED, HALMAC_GPIO8, HALMAC_GPIO_OUT, \ + 0x4e, BIT(5), BIT(5)} +#define GPIO8_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO8, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO9 definition */ +#define GPIO9_DIS_WL_N_8822B \ + {HALMAC_WL_HWPDN, HALMAC_GPIO9, HALMAC_GPIO_IN, \ + 0x68, BIT(3) | BIT(0), BIT(3) | BIT(0)} +#define GPIO9_WL_EXT_WOL_8822B \ + {HALMAC_WL_HW_EXTWOL, HALMAC_GPIO9, HALMAC_GPIO_IN, \ + 0x4a, BIT(0) | BIT(1), BIT(0)} +#define GPIO9_USCTS0_8822B \ + {HALMAC_UART0, HALMAC_GPIO9, HALMAC_GPIO_IN, \ + 0x66, BIT(6), BIT(6)} +#define GPIO9_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO9, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO10 definition */ +#define GPIO10_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO10, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO11 definition */ +#define GPIO11_DIS_BT_N_8822B \ + {HALMAC_BT_HWPDN, HALMAC_GPIO11, HALMAC_GPIO_IN, \ + 0x6a, BIT(0), BIT(0)} +#define GPIO11_USOUT0_8822B \ + {HALMAC_UART0, HALMAC_GPIO11, HALMAC_GPIO_OUT, \ + 0x66, BIT(6), BIT(6)} +#define GPIO11_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO11, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO12 definition */ +#define GPIO12_USIN0_8822B \ + {HALMAC_UART0, HALMAC_GPIO12, HALMAC_GPIO_IN, \ + 0x66, BIT(6), BIT(6)} +#define GPIO12_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO12, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO13 definition */ +#define GPIO13_BT_WAKE_8822B \ + {HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO13, HALMAC_GPIO_IN, \ + 0x4e, BIT(6), BIT(6)} +#define GPIO13_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO14 definition */ +#define GPIO14_UART_WAKE_8822B \ + {HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO14, HALMAC_GPIO_OUT, \ + 0x4e, BIT(6), BIT(6)} +#define GPIO14_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO14, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO15 definition */ +#define GPIO15_EXT_XTAL_8822B \ + {HALMAC_EXT_XTAL, HALMAC_GPIO15, HALMAC_GPIO_OUT, \ + 0x66, BIT(7), BIT(7)} +#define GPIO15_SW_IO_8822B \ + {HALMAC_SW_IO, HALMAC_GPIO15, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO0_8822B[] = { + GPIO0_BT_GPIO0_8822B, + GPIO0_BT_ACT_8822B, + GPIO0_WL_ACT_8822B, + GPIO0_WLMAC_DBG_GPIO0_8822B, + GPIO0_WLPHY_DBG_GPIO0_8822B, + GPIO0_BT_DBG_GPIO0_8822B, + GPIO0_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO1_8822B[] = { - HALMAC_GPIO1_BT_GPIO1_8822B, - HALMAC_GPIO1_BT_3DD_SYNC_A_8822B, - HALMAC_GPIO1_WL_CK_8822B, - HALMAC_GPIO1_BT_CK_8822B, - HALMAC_GPIO1_WLMAC_DBG_GPIO1_8822B, - HALMAC_GPIO1_WLPHY_DBG_GPIO1_8822B, - HALMAC_GPIO1_BT_DBG_GPIO1_8822B, - HALMAC_GPIO1_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO1_8822B[] = { + GPIO1_BT_GPIO1_8822B, + GPIO1_BT_3DD_SYNC_A_8822B, + GPIO1_WL_CK_8822B, + GPIO1_BT_CK_8822B, + GPIO1_WLMAC_DBG_GPIO1_8822B, + GPIO1_WLPHY_DBG_GPIO1_8822B, + GPIO1_BT_DBG_GPIO1_8822B, + GPIO1_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO2_8822B[] = { - HALMAC_GPIO2_BT_GPIO2_8822B, - HALMAC_GPIO2_WL_STATE_8822B, - HALMAC_GPIO2_BT_STATE_8822B, - HALMAC_GPIO2_WLMAC_DBG_GPIO2_8822B, - HALMAC_GPIO2_WLPHY_DBG_GPIO2_8822B, - HALMAC_GPIO2_BT_DBG_GPIO2_8822B, - HALMAC_GPIO2_RFE_CTRL_5_8822B, - HALMAC_GPIO2_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO2_8822B[] = { + GPIO2_BT_GPIO2_8822B, + GPIO2_WL_STATE_8822B, + GPIO2_BT_STATE_8822B, + GPIO2_WLMAC_DBG_GPIO2_8822B, + GPIO2_WLPHY_DBG_GPIO2_8822B, + GPIO2_BT_DBG_GPIO2_8822B, + GPIO2_RFE_CTRL_5_8822B, + GPIO2_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO3_8822B[] = { - HALMAC_GPIO3_BT_GPIO3_8822B, - HALMAC_GPIO3_WL_PRI_8822B, - HALMAC_GPIO3_BT_PRI_8822B, - HALMAC_GPIO3_WLMAC_DBG_GPIO3_8822B, - HALMAC_GPIO3_WLPHY_DBG_GPIO3_8822B, - HALMAC_GPIO3_BT_DBG_GPIO3_8822B, - HALMAC_GPIO3_RFE_CTRL_4_8822B, - HALMAC_GPIO3_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO3_8822B[] = { + GPIO3_BT_GPIO3_8822B, + GPIO3_WL_PRI_8822B, + GPIO3_BT_PRI_8822B, + GPIO3_WLMAC_DBG_GPIO3_8822B, + GPIO3_WLPHY_DBG_GPIO3_8822B, + GPIO3_BT_DBG_GPIO3_8822B, + GPIO3_RFE_CTRL_4_8822B, + GPIO3_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO4_8822B[] = { - HALMAC_GPIO4_BT_SPI_D0_8822B, - HALMAC_GPIO4_WL_SPI_D0_8822B, - HALMAC_GPIO4_SDIO_INT_8822B, - HALMAC_GPIO4_JTAG_TRST_8822B, - HALMAC_GPIO4_DBG_GNT_WL_8822B, - HALMAC_GPIO4_WLMAC_DBG_GPIO4_8822B, - HALMAC_GPIO4_WLPHY_DBG_GPIO4_8822B, - HALMAC_GPIO4_BT_DBG_GPIO4_8822B, - HALMAC_GPIO4_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO4_8822B[] = { + GPIO4_BT_SPI_D0_8822B, + GPIO4_WL_SPI_D0_8822B, + GPIO4_SDIO_INT_8822B, + GPIO4_JTAG_TRST_8822B, + GPIO4_DBG_GNT_WL_8822B, + GPIO4_WLMAC_DBG_GPIO4_8822B, + GPIO4_WLPHY_DBG_GPIO4_8822B, + GPIO4_BT_DBG_GPIO4_8822B, + GPIO4_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO5_8822B[] = { - HALMAC_GPIO5_BT_SPI_D1_8822B, - HALMAC_GPIO5_WL_SPI_D1_8822B, - HALMAC_GPIO5_JTAG_TDI_8822B, - HALMAC_GPIO5_DBG_GNT_BT, - HALMAC_GPIO5_WLMAC_DBG_GPIO5_8822B, - HALMAC_GPIO5_WLPHY_DBG_GPIO5_8822B, - HALMAC_GPIO5_BT_DBG_GPIO5_8822B, - HALMAC_GPIO5_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO5_8822B[] = { + GPIO5_BT_SPI_D1_8822B, + GPIO5_WL_SPI_D1_8822B, + GPIO5_JTAG_TDI_8822B, + GPIO5_DBG_GNT_BT_8822B, + GPIO5_WLMAC_DBG_GPIO5_8822B, + GPIO5_WLPHY_DBG_GPIO5_8822B, + GPIO5_BT_DBG_GPIO5_8822B, + GPIO5_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO6_8822B[] = { - HALMAC_GPIO6_BT_SPI_D2_8822B, - HALMAC_GPIO6_WL_SPI_D2_8822B, - HALMAC_GPIO6_EEDO_8822B, - HALMAC_GPIO6_JTAG_TDO_8822B, - HALMAC_GPIO6_BT_3DD_SYNC_B_8822B, - HALMAC_GPIO6_BT_GPIO18_8822B, - HALMAC_GPIO6_SIN_8822B, - HALMAC_GPIO6_WLMAC_DBG_GPIO6_8822B, - HALMAC_GPIO6_WLPHY_DBG_GPIO6_8822B, - HALMAC_GPIO6_BT_DBG_GPIO6_8822B, - HALMAC_GPIO6_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO6_8822B[] = { + GPIO6_BT_SPI_D2_8822B, + GPIO6_WL_SPI_D2_8822B, + GPIO6_EEDO_8822B, + GPIO6_JTAG_TDO_8822B, + GPIO6_BT_3DD_SYNC_B_8822B, + GPIO6_BT_GPIO18_8822B, + GPIO6_SIN_8822B, + GPIO6_WLMAC_DBG_GPIO6_8822B, + GPIO6_WLPHY_DBG_GPIO6_8822B, + GPIO6_BT_DBG_GPIO6_8822B, + GPIO6_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO7_8822B[] = { - HALMAC_GPIO7_BT_SPI_D3_8822B, - HALMAC_GPIO7_WL_SPI_D3_8822B, - HALMAC_GPIO7_EEDI_8822B, - HALMAC_GPIO7_JTAG_TMS_8822B, - HALMAC_GPIO7_BT_GPIO16_8822B, - HALMAC_GPIO7_SOUT_8822B, - HALMAC_GPIO7_WLMAC_DBG_GPIO7_8822B, - HALMAC_GPIO7_WLPHY_DBG_GPIO7_8822B, - HALMAC_GPIO7_BT_DBG_GPIO7_8822B, - HALMAC_GPIO7_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO7_8822B[] = { + GPIO7_BT_SPI_D3_8822B, + GPIO7_WL_SPI_D3_8822B, + GPIO7_EEDI_8822B, + GPIO7_JTAG_TMS_8822B, + GPIO7_BT_GPIO16_8822B, + GPIO7_SOUT_8822B, + GPIO7_WLMAC_DBG_GPIO7_8822B, + GPIO7_WLPHY_DBG_GPIO7_8822B, + GPIO7_BT_DBG_GPIO7_8822B, + GPIO7_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO8_8822B[] = { - HALMAC_GPIO8_WL_EXT_WOL_8822B, - HALMAC_GPIO8_WL_LED, - HALMAC_GPIO8_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO8_8822B[] = { + GPIO8_WL_EXT_WOL_8822B, + GPIO8_WL_LED_8822B, + GPIO8_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO9_8822B[] = { - HALMAC_GPIO9_DIS_WL_N_8822B, - HALMAC_GPIO9_WL_EXT_WOL_8822B, - HALMAC_GPIO9_USCTS0_8822B, - HALMAC_GPIO9_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO9_8822B[] = { + GPIO9_DIS_WL_N_8822B, + GPIO9_WL_EXT_WOL_8822B, + GPIO9_USCTS0_8822B, + GPIO9_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO10_8822B[] = { - HALMAC_GPIO10_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO10_8822B[] = { + GPIO10_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO11_8822B[] = { - HALMAC_GPIO11_DIS_BT_N_8822B, - HALMAC_GPIO11_USOUT0_8822B, - HALMAC_GPIO11_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO11_8822B[] = { + GPIO11_DIS_BT_N_8822B, + GPIO11_USOUT0_8822B, + GPIO11_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO12_8822B[] = { - HALMAC_GPIO12_USIN0_8822B, - HALMAC_GPIO12_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO12_8822B[] = { + GPIO12_USIN0_8822B, + GPIO12_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO13_8822B[] = { - HALMAC_GPIO13_BT_WAKE_8822B, - HALMAC_GPIO13_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO13_8822B[] = { + GPIO13_BT_WAKE_8822B, + GPIO13_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO14_8822B[] = { - HALMAC_GPIO14_UART_WAKE_8822B, - HALMAC_GPIO14_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO14_8822B[] = { + GPIO14_UART_WAKE_8822B, + GPIO14_SW_IO_8822B }; -const HALMAC_GPIO_PIMUX_LIST PIMUX_LIST_GPIO15_8822B[] = { - HALMAC_GPIO15_EXT_XTAL_8822B, - HALMAC_GPIO15_SW_IO_8822B +const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO15_8822B[] = { + GPIO15_EXT_XTAL_8822B, + GPIO15_SW_IO_8822B }; -static HALMAC_RET_STATUS -halmac_get_pinmux_list_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_GPIO_FUNC gpio_func, - OUT const HALMAC_GPIO_PIMUX_LIST **ppPinmux_list, - OUT u32 *pList_size, - OUT u32 *pGpio_id -); - -static HALMAC_RET_STATUS -halmac_chk_pinmux_valid_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_GPIO_FUNC gpio_func -); +static enum halmac_ret_status +get_pinmux_list_8822b(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, + const struct halmac_gpio_pimux_list **list, + u32 *list_size, u32 *gpio_id); + +static enum halmac_ret_status +chk_pinmux_valid_8822b(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func); /** - * halmac_pinmux_get_func_8822b() -get current gpio status - * @pHalmac_adapter : the adapter of halmac + * pinmux_get_func_8822b() -get current gpio status + * @adapter : the adapter of halmac * @gpio_func : gpio function - * @pEnable : function is enable(1) or disable(0) + * @enable : function is enable(1) or disable(0) * Author : Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_pinmux_get_func_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_GPIO_FUNC gpio_func, - OUT u8 *pEnable -) +enum halmac_ret_status +pinmux_get_func_8822b(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, u8 *enable) { u32 list_size; - u32 curr_func; + u32 cur_func; u32 gpio_id; - HALMAC_RET_STATUS status; - const HALMAC_GPIO_PIMUX_LIST *pPinmux_list = NULL; - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; + enum halmac_ret_status status; + const struct halmac_gpio_pimux_list *list = NULL; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_get_func_8822b ==========>\n"); + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); - status = halmac_get_pinmux_list_8822b(pHalmac_adapter, gpio_func, &pPinmux_list, &list_size, &gpio_id); + status = get_pinmux_list_8822b(adapter, gpio_func, &list, &list_size, + &gpio_id); if (status != HALMAC_RET_SUCCESS) return status; - status = halmac_pinmux_parser_88xx(pHalmac_adapter, pPinmux_list, list_size, gpio_id, &curr_func); + status = pinmux_parser_88xx(adapter, list, list_size, gpio_id, + &cur_func); if (status != HALMAC_RET_SUCCESS) return status; switch (gpio_func) { case HALMAC_GPIO_FUNC_WL_LED: - *pEnable = (curr_func == HALMAC_WL_LED) ? 1 : 0; + *enable = (cur_func == HALMAC_WL_LED) ? 1 : 0; break; case HALMAC_GPIO_FUNC_SDIO_INT: - *pEnable = (curr_func == HALMAC_SDIO_INT) ? 1 : 0; + *enable = (cur_func == HALMAC_SDIO_INT) ? 1 : 0; break; case HALMAC_GPIO_FUNC_SW_IO_0: case HALMAC_GPIO_FUNC_SW_IO_1: @@ -227,239 +514,228 @@ halmac_pinmux_get_func_8822b( case HALMAC_GPIO_FUNC_SW_IO_13: case HALMAC_GPIO_FUNC_SW_IO_14: case HALMAC_GPIO_FUNC_SW_IO_15: - *pEnable = (curr_func == HALMAC_SW_IO) ? 1 : 0; + *enable = (cur_func == HALMAC_SW_IO) ? 1 : 0; break; default: - *pEnable = 0; + *enable = 0; return HALMAC_RET_GET_PINMUX_ERR; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_get_func_8822b <==========\n"); + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); return HALMAC_RET_SUCCESS; } /** - * halmac_pinmux_set_func_8822b() -set gpio function - * @pHalmac_adapter : the adapter of halmac + * pinmux_set_func_8822b() -set gpio function + * @adapter : the adapter of halmac * @gpio_func : gpio function * Author : Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_pinmux_set_func_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_GPIO_FUNC gpio_func -) +enum halmac_ret_status +pinmux_set_func_8822b(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func) { u32 list_size; u32 gpio_id; - HALMAC_RET_STATUS status; - const HALMAC_GPIO_PIMUX_LIST *pPinmux_list = NULL; - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; + enum halmac_ret_status status; + const struct halmac_gpio_pimux_list *list = NULL; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_set_func_8822b ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]func name : %d\n", gpio_func); + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]func name : %d\n", gpio_func); - status = halmac_chk_pinmux_valid_8822b(pHalmac_adapter, gpio_func); + status = chk_pinmux_valid_8822b(adapter, gpio_func); if (status != HALMAC_RET_SUCCESS) return status; - status = halmac_get_pinmux_list_8822b(pHalmac_adapter, gpio_func, &pPinmux_list, &list_size, &gpio_id); + status = get_pinmux_list_8822b(adapter, gpio_func, &list, &list_size, + &gpio_id); if (status != HALMAC_RET_SUCCESS) return status; - status = halmac_pinmux_switch_88xx(pHalmac_adapter, pPinmux_list, list_size, gpio_id, gpio_func); + status = pinmux_switch_88xx(adapter, list, list_size, gpio_id, + gpio_func); if (status != HALMAC_RET_SUCCESS) return status; - status = halmac_pinmux_record_88xx(pHalmac_adapter, gpio_func, 1); + status = pinmux_record_88xx(adapter, gpio_func, 1); if (status != HALMAC_RET_SUCCESS) return status; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_set_func_8822b <==========\n"); + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); return HALMAC_RET_SUCCESS; } /** - * halmac_pinmux_free_func_8822b() -free locked gpio function - * @pHalmac_adapter : the adapter of halmac + * pinmux_free_func_8822b() -free locked gpio function + * @adapter : the adapter of halmac * @gpio_func : gpio function * Author : Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_pinmux_free_func_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_GPIO_FUNC gpio_func -) +enum halmac_ret_status +pinmux_free_func_8822b(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func) { - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - VOID *pDriver_adapter = NULL; + struct halmac_pinmux_info *info = &adapter->pinmux_info; - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_free_func_8822b ==========>\n"); + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); switch (gpio_func) { case HALMAC_GPIO_FUNC_SW_IO_0: - pHalmac_adapter->pinmux_info.sw_io_0 = 0; + info->sw_io_0 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_1: - pHalmac_adapter->pinmux_info.sw_io_1 = 0; + info->sw_io_1 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_2: - pHalmac_adapter->pinmux_info.sw_io_2 = 0; + info->sw_io_2 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_3: - pHalmac_adapter->pinmux_info.sw_io_3 = 0; + info->sw_io_3 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_4: case HALMAC_GPIO_FUNC_SDIO_INT: - pHalmac_adapter->pinmux_info.sw_io_4 = 0; - pHalmac_adapter->pinmux_info.sdio_int = 0; + info->sw_io_4 = 0; + info->sdio_int = 0; break; case HALMAC_GPIO_FUNC_SW_IO_5: - pHalmac_adapter->pinmux_info.sw_io_5 = 0; + info->sw_io_5 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_6: - pHalmac_adapter->pinmux_info.sw_io_6 = 0; + info->sw_io_6 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_7: - pHalmac_adapter->pinmux_info.sw_io_7 = 0; + info->sw_io_7 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_8: case HALMAC_GPIO_FUNC_WL_LED: - pHalmac_adapter->pinmux_info.sw_io_8 = 0; - pHalmac_adapter->pinmux_info.wl_led = 0; + info->sw_io_8 = 0; + info->wl_led = 0; break; case HALMAC_GPIO_FUNC_SW_IO_9: - pHalmac_adapter->pinmux_info.sw_io_9 = 0; + info->sw_io_9 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_10: - pHalmac_adapter->pinmux_info.sw_io_10 = 0; + info->sw_io_10 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_11: - pHalmac_adapter->pinmux_info.sw_io_11 = 0; + info->sw_io_11 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_12: - pHalmac_adapter->pinmux_info.sw_io_12 = 0; + info->sw_io_12 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_13: - pHalmac_adapter->pinmux_info.sw_io_13 = 0; + info->sw_io_13 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_14: - pHalmac_adapter->pinmux_info.sw_io_14 = 0; + info->sw_io_14 = 0; break; case HALMAC_GPIO_FUNC_SW_IO_15: - pHalmac_adapter->pinmux_info.sw_io_15 = 0; + info->sw_io_15 = 0; break; default: return HALMAC_RET_SWITCH_CASE_ERROR; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]func : %X\n", gpio_func); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_free_func_8822b <==========\n"); + PLTFM_MSG_TRACE("[TRACE]func : %X\n", gpio_func); + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); return HALMAC_RET_SUCCESS; } -static HALMAC_RET_STATUS -halmac_get_pinmux_list_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_GPIO_FUNC gpio_func, - OUT const HALMAC_GPIO_PIMUX_LIST **ppPinmux_list, - OUT u32 *pList_size, - OUT u32 *pGpio_id -) +static enum halmac_ret_status +get_pinmux_list_8822b(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, + const struct halmac_gpio_pimux_list **list, + u32 *list_size, u32 *gpio_id) { switch (gpio_func) { case HALMAC_GPIO_FUNC_SW_IO_0: - *ppPinmux_list = PIMUX_LIST_GPIO0_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO0_8822B); - *pGpio_id = HALMAC_GPIO0; + *list = PIMUX_LIST_GPIO0_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO0_8822B); + *gpio_id = HALMAC_GPIO0; break; case HALMAC_GPIO_FUNC_SW_IO_1: - *ppPinmux_list = PIMUX_LIST_GPIO1_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO1_8822B); - *pGpio_id = HALMAC_GPIO1; + *list = PIMUX_LIST_GPIO1_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO1_8822B); + *gpio_id = HALMAC_GPIO1; break; case HALMAC_GPIO_FUNC_SW_IO_2: - *ppPinmux_list = PIMUX_LIST_GPIO2_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO2_8822B); - *pGpio_id = HALMAC_GPIO2; + *list = PIMUX_LIST_GPIO2_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO2_8822B); + *gpio_id = HALMAC_GPIO2; break; case HALMAC_GPIO_FUNC_SW_IO_3: - *ppPinmux_list = PIMUX_LIST_GPIO3_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO3_8822B); - *pGpio_id = HALMAC_GPIO3; + *list = PIMUX_LIST_GPIO3_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO3_8822B); + *gpio_id = HALMAC_GPIO3; break; case HALMAC_GPIO_FUNC_SW_IO_4: case HALMAC_GPIO_FUNC_SDIO_INT: - *ppPinmux_list = PIMUX_LIST_GPIO4_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO4_8822B); - *pGpio_id = HALMAC_GPIO4; + *list = PIMUX_LIST_GPIO4_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO4_8822B); + *gpio_id = HALMAC_GPIO4; break; case HALMAC_GPIO_FUNC_SW_IO_5: - *ppPinmux_list = PIMUX_LIST_GPIO5_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO5_8822B); - *pGpio_id = HALMAC_GPIO5; + *list = PIMUX_LIST_GPIO5_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO5_8822B); + *gpio_id = HALMAC_GPIO5; break; case HALMAC_GPIO_FUNC_SW_IO_6: - *ppPinmux_list = PIMUX_LIST_GPIO6_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO6_8822B); - *pGpio_id = HALMAC_GPIO6; + *list = PIMUX_LIST_GPIO6_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO6_8822B); + *gpio_id = HALMAC_GPIO6; break; case HALMAC_GPIO_FUNC_SW_IO_7: - *ppPinmux_list = PIMUX_LIST_GPIO7_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO7_8822B); - *pGpio_id = HALMAC_GPIO7; + *list = PIMUX_LIST_GPIO7_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO7_8822B); + *gpio_id = HALMAC_GPIO7; break; case HALMAC_GPIO_FUNC_SW_IO_8: case HALMAC_GPIO_FUNC_WL_LED: - *ppPinmux_list = PIMUX_LIST_GPIO8_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO8_8822B); - *pGpio_id = HALMAC_GPIO8; + *list = PIMUX_LIST_GPIO8_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO8_8822B); + *gpio_id = HALMAC_GPIO8; break; case HALMAC_GPIO_FUNC_SW_IO_9: - *ppPinmux_list = PIMUX_LIST_GPIO9_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO9_8822B); - *pGpio_id = HALMAC_GPIO9; + *list = PIMUX_LIST_GPIO9_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO9_8822B); + *gpio_id = HALMAC_GPIO9; break; case HALMAC_GPIO_FUNC_SW_IO_10: - *ppPinmux_list = PIMUX_LIST_GPIO10_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO10_8822B); - *pGpio_id = HALMAC_GPIO10; + *list = PIMUX_LIST_GPIO10_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO10_8822B); + *gpio_id = HALMAC_GPIO10; break; case HALMAC_GPIO_FUNC_SW_IO_11: - *ppPinmux_list = PIMUX_LIST_GPIO11_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO11_8822B); - *pGpio_id = HALMAC_GPIO11; + *list = PIMUX_LIST_GPIO11_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO11_8822B); + *gpio_id = HALMAC_GPIO11; break; case HALMAC_GPIO_FUNC_SW_IO_12: - *ppPinmux_list = PIMUX_LIST_GPIO12_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO12_8822B); - *pGpio_id = HALMAC_GPIO12; + *list = PIMUX_LIST_GPIO12_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO12_8822B); + *gpio_id = HALMAC_GPIO12; break; case HALMAC_GPIO_FUNC_SW_IO_13: - *ppPinmux_list = PIMUX_LIST_GPIO13_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO13_8822B); - *pGpio_id = HALMAC_GPIO13; + *list = PIMUX_LIST_GPIO13_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO13_8822B); + *gpio_id = HALMAC_GPIO13; break; case HALMAC_GPIO_FUNC_SW_IO_14: - *ppPinmux_list = PIMUX_LIST_GPIO14_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO14_8822B); - *pGpio_id = HALMAC_GPIO14; + *list = PIMUX_LIST_GPIO14_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO14_8822B); + *gpio_id = HALMAC_GPIO14; break; case HALMAC_GPIO_FUNC_SW_IO_15: - *ppPinmux_list = PIMUX_LIST_GPIO15_8822B; - *pList_size = ARRAY_SIZE(PIMUX_LIST_GPIO15_8822B); - *pGpio_id = HALMAC_GPIO15; + *list = PIMUX_LIST_GPIO15_8822B; + *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO15_8822B); + *gpio_id = HALMAC_GPIO15; break; default: return HALMAC_RET_SWITCH_CASE_ERROR; @@ -468,90 +744,86 @@ halmac_get_pinmux_list_8822b( return HALMAC_RET_SUCCESS; } -static HALMAC_RET_STATUS -halmac_chk_pinmux_valid_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_GPIO_FUNC gpio_func -) +static enum halmac_ret_status +chk_pinmux_valid_8822b(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func) { - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; + struct halmac_pinmux_info *info = &adapter->pinmux_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; switch (gpio_func) { case HALMAC_GPIO_FUNC_SW_IO_0: - if (pHalmac_adapter->pinmux_info.sw_io_0 == 1) + if (info->sw_io_0 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_1: - if (pHalmac_adapter->pinmux_info.sw_io_1 == 1) + if (info->sw_io_1 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_2: - if (pHalmac_adapter->pinmux_info.sw_io_2 == 1) + if (info->sw_io_2 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_3: - if (pHalmac_adapter->pinmux_info.sw_io_3 == 1) + if (info->sw_io_3 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_4: case HALMAC_GPIO_FUNC_SDIO_INT: - if ((pHalmac_adapter->pinmux_info.sw_io_4 == 1) || (pHalmac_adapter->pinmux_info.sdio_int == 1)) + if (info->sw_io_4 == 1 || info->sdio_int == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_5: - if (pHalmac_adapter->pinmux_info.sw_io_5 == 1) + if (info->sw_io_5 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_6: - if (pHalmac_adapter->pinmux_info.sw_io_6 == 1) + if (info->sw_io_6 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_7: - if (pHalmac_adapter->pinmux_info.sw_io_7 == 1) + if (info->sw_io_7 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_8: case HALMAC_GPIO_FUNC_WL_LED: - if ((pHalmac_adapter->pinmux_info.sw_io_8 == 1) || (pHalmac_adapter->pinmux_info.wl_led == 1)) + if (info->sw_io_8 == 1 || info->wl_led == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_9: - if (pHalmac_adapter->pinmux_info.sw_io_9 == 1) + if (info->sw_io_9 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_10: - if (pHalmac_adapter->pinmux_info.sw_io_10 == 1) + if (info->sw_io_10 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_11: - if (pHalmac_adapter->pinmux_info.sw_io_11 == 1) + if (info->sw_io_11 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_12: - if (pHalmac_adapter->pinmux_info.sw_io_12 == 1) + if (info->sw_io_12 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_13: - if (pHalmac_adapter->pinmux_info.sw_io_13 == 1) + if (info->sw_io_13 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_14: - if (pHalmac_adapter->pinmux_info.sw_io_14 == 1) + if (info->sw_io_14 == 1) status = HALMAC_RET_PINMUX_USED; break; case HALMAC_GPIO_FUNC_SW_IO_15: - if (pHalmac_adapter->pinmux_info.sw_io_15 == 1) + if (info->sw_io_15 == 1) status = HALMAC_RET_PINMUX_USED; break; default: return HALMAC_RET_SWITCH_CASE_ERROR; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]chk_pinmux_valid func : %X status : %X\n", - gpio_func, status); + PLTFM_MSG_TRACE("[TRACE]chk_pinmux_valid func : %X status : %X\n", + gpio_func, status); return status; } diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h index 2bbf97e..6fa0bfa 100644 --- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -21,147 +21,17 @@ #if HALMAC_8822B_SUPPORT -/* P_LED0 definition */ -#define HALMAC_GPIO0_BT_GPIO0_8822B {HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, 0x66, BIT(2), BIT(2)} +enum halmac_ret_status +pinmux_get_func_8822b(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, u8 *enable); -/* GPIO0 definition */ -#define HALMAC_GPIO0_BT_GPIO0_8822B {HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, 0x66, BIT(2), BIT(2)} -#define HALMAC_GPIO0_BT_ACT_8822B {HALMAC_BT_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, 0x41, BIT(1), 0} -#define HALMAC_GPIO0_WL_ACT_8822B {HALMAC_WL_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, 0x41, BIT(2), BIT(2)} -#define HALMAC_GPIO0_WLMAC_DBG_GPIO0_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} -#define HALMAC_GPIO0_WLPHY_DBG_GPIO0_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} -#define HALMAC_GPIO0_BT_DBG_GPIO0_8822B {HALMAC_BT_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} -#define HALMAC_GPIO0_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} +enum halmac_ret_status +pinmux_set_func_8822b(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func); -/* GPIO1 definition */ -#define HALMAC_GPIO1_BT_GPIO1_8822B {HALMAC_BT_GPIO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, 0x66, BIT(2), BIT(2)} -#define HALMAC_GPIO1_BT_3DD_SYNC_A_8822B {HALMAC_BT_3DDLS_A, HALMAC_GPIO1, HALMAC_GPIO_IN, 0x66, BIT(2), BIT(2)} -#define HALMAC_GPIO1_WL_CK_8822B {HALMAC_BT_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, 0x41, BIT(1), 0} -#define HALMAC_GPIO1_BT_CK_8822B {HALMAC_WL_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, 0x41, BIT(2), BIT(2)} -#define HALMAC_GPIO1_WLMAC_DBG_GPIO1_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} -#define HALMAC_GPIO1_WLPHY_DBG_GPIO1_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} -#define HALMAC_GPIO1_BT_DBG_GPIO1_8822B {HALMAC_BT_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} -#define HALMAC_GPIO1_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO2 definition */ -#define HALMAC_GPIO2_BT_GPIO2_8822B {HALMAC_BT_GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, 0x66, BIT(2), BIT(2)} -#define HALMAC_GPIO2_WL_STATE_8822B {HALMAC_BT_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, 0x41, BIT(1), 0} -#define HALMAC_GPIO2_BT_STATE_8822B {HALMAC_WL_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, 0x41, BIT(2), BIT(2)} -#define HALMAC_GPIO2_WLMAC_DBG_GPIO2_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} -#define HALMAC_GPIO2_WLPHY_DBG_GPIO2_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} -#define HALMAC_GPIO2_BT_DBG_GPIO2_8822B {HALMAC_BT_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} -#define HALMAC_GPIO2_RFE_CTRL_5_8822B {HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, 0x40, BIT(2), BIT(2)} -#define HALMAC_GPIO2_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO3 definition */ -#define HALMAC_GPIO3_BT_GPIO3_8822B {HALMAC_BT_GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, 0x66, BIT(2), BIT(2)} -#define HALMAC_GPIO3_WL_PRI_8822B {HALMAC_BT_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, 0x41, BIT(1), 0} -#define HALMAC_GPIO3_BT_PRI_8822B {HALMAC_WL_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, 0x41, BIT(2), BIT(2)} -#define HALMAC_GPIO3_WLMAC_DBG_GPIO3_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} -#define HALMAC_GPIO3_WLPHY_DBG_GPIO3_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} -#define HALMAC_GPIO3_BT_DBG_GPIO3_8822B {HALMAC_BT_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} -#define HALMAC_GPIO3_RFE_CTRL_4_8822B {HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, 0x40, BIT(2), BIT(2)} -#define HALMAC_GPIO3_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO4 definition */ -#define HALMAC_GPIO4_BT_SPI_D0_8822B {HALMAC_BT_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, 0x66, BIT(4), BIT(4)} -#define HALMAC_GPIO4_WL_SPI_D0_8822B {HALMAC_WL_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, 0x42, BIT(3), BIT(3)} -#define HALMAC_GPIO4_SDIO_INT_8822B {HALMAC_SDIO_INT, HALMAC_GPIO4, HALMAC_GPIO_OUT, 0x72, BIT(2), BIT(2)} -#define HALMAC_GPIO4_JTAG_TRST_8822B {HALMAC_JTAG, HALMAC_GPIO4, HALMAC_GPIO_IN, 0x67, BIT(0), BIT(0)} -#define HALMAC_GPIO4_DBG_GNT_WL_8822B {HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO4, HALMAC_GPIO_OUT, 0x73, BIT(3), BIT(3)} -#define HALMAC_GPIO4_WLMAC_DBG_GPIO4_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} -#define HALMAC_GPIO4_WLPHY_DBG_GPIO4_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} -#define HALMAC_GPIO4_BT_DBG_GPIO4_8822B {HALMAC_BT_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} -#define HALMAC_GPIO4_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO5 definition */ -#define HALMAC_GPIO5_BT_SPI_D1_8822B {HALMAC_BT_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, 0x66, BIT(4), BIT(4)} -#define HALMAC_GPIO5_WL_SPI_D1_8822B {HALMAC_WL_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, 0x42, BIT(3), BIT(3)} -#define HALMAC_GPIO5_JTAG_TDI_8822B {HALMAC_JTAG, HALMAC_GPIO5, HALMAC_GPIO_IN, 0x67, BIT(0), BIT(0)} -#define HALMAC_GPIO5_DBG_GNT_BT {HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO5, HALMAC_GPIO_OUT, 0x73, BIT(3), BIT(3)} -#define HALMAC_GPIO5_WLMAC_DBG_GPIO5_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} -#define HALMAC_GPIO5_WLPHY_DBG_GPIO5_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} -#define HALMAC_GPIO5_BT_DBG_GPIO5_8822B {HALMAC_BT_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} -#define HALMAC_GPIO5_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO6 definition */ -#define HALMAC_GPIO6_BT_SPI_D2_8822B {HALMAC_BT_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, 0x66, BIT(4), BIT(4)} -#define HALMAC_GPIO6_WL_SPI_D2_8822B {HALMAC_WL_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, 0x42, BIT(3), BIT(3)} -#define HALMAC_GPIO6_EEDO_8822B {HALMAC_EEPROM, HALMAC_GPIO6, HALMAC_GPIO_IN, 0x40, BIT(4), BIT(4)} -#define HALMAC_GPIO6_JTAG_TDO_8822B {HALMAC_JTAG, HALMAC_GPIO6, HALMAC_GPIO_OUT, 0x67, BIT(0), BIT(0)} -#define HALMAC_GPIO6_BT_3DD_SYNC_B_8822B {HALMAC_BT_3DDLS_B, HALMAC_GPIO6, HALMAC_GPIO_IN, 0x67, BIT(1), BIT(1)} -#define HALMAC_GPIO6_BT_GPIO18_8822B {HALMAC_BT_GPIO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, 0x67, BIT(1), BIT(1)} -#define HALMAC_GPIO6_SIN_8822B {HALMAC_WL_UART, HALMAC_GPIO6, HALMAC_GPIO_IN, 0x41, BIT(0), BIT(0)} -#define HALMAC_GPIO6_WLMAC_DBG_GPIO6_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} -#define HALMAC_GPIO6_WLPHY_DBG_GPIO6_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} -#define HALMAC_GPIO6_BT_DBG_GPIO6_8822B {HALMAC_BT_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} -#define HALMAC_GPIO6_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO7 definition */ -#define HALMAC_GPIO7_BT_SPI_D3_8822B {HALMAC_BT_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, 0x66, BIT(4), BIT(4)} -#define HALMAC_GPIO7_WL_SPI_D3_8822B {HALMAC_WL_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, 0x42, BIT(3), BIT(3)} -#define HALMAC_GPIO7_EEDI_8822B {HALMAC_EEPROM, HALMAC_GPIO7, HALMAC_GPIO_OUT, 0x40, BIT(4), BIT(4)} -#define HALMAC_GPIO7_JTAG_TMS_8822B {HALMAC_JTAG, HALMAC_GPIO7, HALMAC_GPIO_IN, 0x67, BIT(0), BIT(0)} -#define HALMAC_GPIO7_BT_GPIO16_8822B {HALMAC_BT_GPIO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, 0x67, BIT(2), BIT(2)} -#define HALMAC_GPIO7_SOUT_8822B {HALMAC_WL_UART, HALMAC_GPIO7, HALMAC_GPIO_OUT, 0x41, BIT(0), BIT(0)} -#define HALMAC_GPIO7_WLMAC_DBG_GPIO7_8822B {HALMAC_WLMAC_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0)} -#define HALMAC_GPIO7_WLPHY_DBG_GPIO7_8822B {HALMAC_WLPHY_DBG, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), BIT(1)} -#define HALMAC_GPIO7_BT_DBG_GPIO7_8822B {HALMAC_BT_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} -#define HALMAC_GPIO7_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO8 definition */ -#define HALMAC_GPIO8_WL_EXT_WOL_8822B {HALMAC_WL_HW_EXTWOL, HALMAC_GPIO8, HALMAC_GPIO_IN, 0x4a, BIT(0) | BIT(1), BIT(0) | BIT(1)} -#define HALMAC_GPIO8_WL_LED {HALMAC_WL_LED, HALMAC_GPIO8, HALMAC_GPIO_OUT, 0x4e, BIT(5), BIT(5)} -#define HALMAC_GPIO8_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO8, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO9 definition */ -#define HALMAC_GPIO9_DIS_WL_N_8822B {HALMAC_WL_HWPDN, HALMAC_GPIO9, HALMAC_GPIO_IN, 0x68, BIT(3) | BIT(0), BIT(3) | BIT(0)} -#define HALMAC_GPIO9_WL_EXT_WOL_8822B {HALMAC_WL_HW_EXTWOL, HALMAC_GPIO9, HALMAC_GPIO_IN, 0x4a, BIT(0) | BIT(1), BIT(0)} -#define HALMAC_GPIO9_USCTS0_8822B {HALMAC_UART0, HALMAC_GPIO9, HALMAC_GPIO_IN, 0x66, BIT(6), BIT(6)} -#define HALMAC_GPIO9_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO9, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO10 definition */ -#define HALMAC_GPIO10_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO10, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO11 definition */ -#define HALMAC_GPIO11_DIS_BT_N_8822B {HALMAC_BT_HWPDN, HALMAC_GPIO11, HALMAC_GPIO_IN, 0x6a, BIT(0), BIT(0)} -#define HALMAC_GPIO11_USOUT0_8822B {HALMAC_UART0, HALMAC_GPIO11, HALMAC_GPIO_OUT, 0x66, BIT(6), BIT(6)} -#define HALMAC_GPIO11_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO11, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO12 definition */ -#define HALMAC_GPIO12_USIN0_8822B {HALMAC_UART0, HALMAC_GPIO12, HALMAC_GPIO_IN, 0x66, BIT(6), BIT(6)} -#define HALMAC_GPIO12_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO12, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO13 definition */ -#define HALMAC_GPIO13_BT_WAKE_8822B {HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO13, HALMAC_GPIO_IN, 0x4e, BIT(6), BIT(6)} -#define HALMAC_GPIO13_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO14 definition */ -#define HALMAC_GPIO14_UART_WAKE_8822B {HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO14, HALMAC_GPIO_OUT, 0x4e, BIT(6), BIT(6)} -#define HALMAC_GPIO14_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO14, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -/* GPIO15 definition */ -#define HALMAC_GPIO15_EXT_XTAL_8822B {HALMAC_EXT_XTAL, HALMAC_GPIO15, HALMAC_GPIO_OUT, 0x66, BIT(7), BIT(7)} -#define HALMAC_GPIO15_SW_IO_8822B {HALMAC_SW_IO, HALMAC_GPIO15, HALMAC_GPIO_IN_OUT, 0x40, BIT(1) | BIT(0), 0} - -HALMAC_RET_STATUS -halmac_pinmux_get_func_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_GPIO_FUNC gpio_func, - OUT u8 *pEnable -); - -HALMAC_RET_STATUS -halmac_pinmux_set_func_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_GPIO_FUNC gpio_func -); - -HALMAC_RET_STATUS -halmac_pinmux_free_func_8822b( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_GPIO_FUNC gpio_func -); +enum halmac_ret_status +pinmux_free_func_8822b(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func); #endif /* HALMAC_8822B_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_88xx_cfg.h b/hal/halmac/halmac_88xx/halmac_88xx_cfg.h index b40ff3a..bad894c 100644 --- a/hal/halmac/halmac_88xx/halmac_88xx_cfg.h +++ b/hal/halmac/halmac_88xx/halmac_88xx_cfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,174 +16,29 @@ #ifndef _HALMAC_88XX_CFG_H_ #define _HALMAC_88XX_CFG_H_ -#include "../halmac_2_platform.h" -#include "../halmac_type.h" -#include "../halmac_hw_cfg.h" #include "../halmac_api.h" -#include "../halmac_bit2.h" -#include "../halmac_reg2.h" -#include "../halmac_pwr_seq_cmd.h" -#include "halmac_func_88xx.h" -#include "halmac_api_88xx.h" -#include "halmac_api_88xx_usb.h" -#include "halmac_api_88xx_pcie.h" -#include "halmac_api_88xx_sdio.h" -#if HALMAC_PLATFORM_TESTPROGRAM -#include "halmisc_api_88xx.h" -#include "halmisc_api_88xx_usb.h" -#include "halmisc_api_88xx_pcie.h" -#include "halmisc_api_88xx_sdio.h" -#endif - -#define HALMAC_SVN_VER_88XX "13359M" - -#define HALMAC_MAJOR_VER_88XX 0x0001 /* major version, ver_1 for async_api */ -#define HALMAC_PROTOTYPE_VER_88XX 0x0003 /* For halmac_api num change or prototype change, increment prototype version */ -#define HALMAC_MINOR_VER_88XX 0x0009 /* else increment minor version */ -#define HALMAC_PATCH_VER_88XX 0x0000 /* patch version */ - -#define HALMAC_C2H_DATA_OFFSET_88XX 10 -#define HALMAC_RX_AGG_ALIGNMENT_SIZE_88XX 8 -#define HALMAC_TX_AGG_ALIGNMENT_SIZE_88XX 8 -#define HALMAC_TX_AGG_BUFF_SIZE_88XX 32768 -#define HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX 80 /*8*10 Bytes*/ -#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_88XX 80 /* should be 8 Byte alignment*/ -#define HALMAC_TX_PAGE_SIZE_88XX 128 /* PageSize 128Byte */ -#define HALMAC_TX_PAGE_SIZE_2_POWER_88XX 7 /* 128 = 2^7 */ -#define HALMAC_RX_BUF_FW_88XX 12288 /* 12K */ +#if HALMAC_88XX_SUPPORT -#define HALMAC_EXTRA_INFO_BUFF_SIZE_88XX 4096 /*4K*/ -#define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX 16384 /*16K*/ -#define HALMAC_FW_OFFLOAD_CMD_SIZE_88XX 12 /*Fw config parameter cmd size, each 12 byte*/ +#define TX_PAGE_SIZE_88XX 128 +#define TX_PAGE_SIZE_SHIFT_88XX 7 /* 128 = 2^7 */ +#define TX_ALIGN_SIZE_88XX 8 +#define SDIO_TX_MAX_SIZE_88XX 31744 +#define RX_BUF_FW_88XX 12288 -#define HALMAC_H2C_CMD_ORIGINAL_SIZE_88XX 8 -#define HALMAC_H2C_CMD_SIZE_UNIT_88XX 32 /* Only support 32 byte packet now */ +#define TX_DESC_SIZE_88XX 48 +#define RX_DESC_SIZE_88XX 24 -#define HALMAC_NLO_INFO_SIZE_88XX 1024 - -/* Download FW */ -#define HALMAC_FW_SIZE_MAX_88XX 0x40000 -#define HALMAC_FWHDR_SIZE_88XX 64 -#define HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX 8 -#define HALMAC_FW_MAX_DL_SIZE_88XX 0x2000 /* need power of 2 */ -/* Max dlfw size can not over 31K, because SDIO HW restriction */ -#define HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX 0x7C00 - -#define DLFW_RESTORE_REG_NUM_88XX 9 -#define ID_INFORM_DLEMEM_RDY 0x80 - -/* FW header information */ -#define HALMAC_FWHDR_OFFSET_VERSION_88XX 4 -#define HALMAC_FWHDR_OFFSET_SUBVERSION_88XX 6 -#define HALMAC_FWHDR_OFFSET_SUBINDEX_88XX 7 -#define HALMAC_FWHDR_OFFSET_MONTH_88XX 16 -#define HALMAC_FWHDR_OFFSET_DATE_88XX 17 -#define HALMAC_FWHDR_OFFSET_HOUR_88XX 18 -#define HALMAC_FWHDR_OFFSET_MIN_88XX 19 -#define HALMAC_FWHDR_OFFSET_YEAR_88XX 20 -#define HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX 24 -#define HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX 28 -#define HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX 32 -#define HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX 36 -#define HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX 48 -#define HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX 52 -#define HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX 56 -#define HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX 60 +#define H2C_PKT_SIZE_88XX 32 /* Only support 32 byte packet now */ +#define H2C_PKT_HDR_SIZE_88XX 8 +#define C2H_DATA_OFFSET_88XX 10 +#define C2H_PKT_BUF_88XX 256 /* HW memory address */ -#define HALMAC_OCPBASE_TXBUF_88XX 0x18780000 -#define HALMAC_OCPBASE_DMEM_88XX 0x00200000 -#define HALMAC_OCPBASE_IMEM_88XX 0x00000000 - -/* define the SDIO Bus CLK threshold, for avoiding CMD53 fails that result from SDIO CLK sync to ana_clk fail */ -#define HALMAC_SDIO_CLK_THRESHOLD_88XX 150 /* 150MHz */ -#define HALMAC_SDIO_CLOCK_SPEED_MAX_88XX 208 /* 208MHz */ - -/* MAC clock */ -#define HALMAC_MAC_CLOCK_88XX 80 /* 80M */ - -/* H2C/C2H*/ -#define HALMAC_H2C_CMD_SIZE_88XX 32 -#define HALMAC_H2C_CMD_HDR_SIZE_88XX 8 - -#define HALMAC_PROTECTED_EFUSE_SIZE_88XX 0x60 - -/* Function enable */ -#define HALMAC_FUNCTION_ENABLE_88XX 0xDC - -/* FIFO size & packet size */ -/* #define HALMAC_WOWLAN_PATTERN_SIZE 256 */ - -/* CFEND rate */ -#define HALMAC_BASIC_CFEND_RATE_88XX 0x5 -#define HALMAC_STBC_CFEND_RATE_88XX 0xF - -/* Response rate */ -#define HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX 0xFFFFF -#define HALMAC_RESPONSE_RATE_88XX HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX - -/* Spec SIFS */ -#define HALMAC_SIFS_CCK_PTCL_88XX 16 -#define HALMAC_SIFS_OFDM_PTCL_88XX 16 - -/* Retry limit */ -#define HALMAC_LONG_RETRY_LIMIT_88XX 8 -#define HALMAC_SHORT_RETRY_LIMIT_88XX 7 - -/* Slot, SIFS, PIFS time */ -#define HALMAC_SLOT_TIME_88XX 0x05 -#define HALMAC_PIFS_TIME_88XX 0x19 -#define HALMAC_SIFS_CCK_CTX_88XX 0xA -#define HALMAC_SIFS_OFDM_CTX_88XX 0xA -#define HALMAC_SIFS_CCK_TRX_88XX 0x10 -#define HALMAC_SIFS_OFDM_TRX_88XX 0x10 - -/* TXOP limit */ -#define HALMAC_VO_TXOP_LIMIT_88XX 0x186 -#define HALMAC_VI_TXOP_LIMIT_88XX 0x3BC - -/* NAV */ -#define HALMAC_RDG_NAV_88XX 0x05 -#define HALMAC_TXOP_NAV_88XX 0x1B - -/* TSF */ -#define HALMAC_CCK_RX_TSF_88XX 0x30 -#define HALMAC_OFDM_RX_TSF_88XX 0x30 - -/* Send beacon related */ -#define HALMAC_TBTT_PROHIBIT_88XX 0x04 -#define HALMAC_TBTT_HOLD_TIME_88XX 0x064 -#define HALMAC_DRIVER_EARLY_INT_88XX 0x04 -#define HALMAC_BEACON_DMA_TIM_88XX 0x02 - -/* RX filter */ -#define HALMAC_RX_FILTER0_RECIVE_ALL_88XX 0xFFFFFFF -#define HALMAC_RX_FILTER0_88XX HALMAC_RX_FILTER0_RECIVE_ALL_88XX -#define HALMAC_RX_FILTER_RECIVE_ALL_88XX 0xFFFF -#define HALMAC_RX_FILTER_88XX HALMAC_RX_FILTER_RECIVE_ALL_88XX - -/* RCR */ -#define HALMAC_RCR_CONFIG_88XX 0xE400631E - -/* Security config */ -#define HALMAC_SECURITY_CONFIG_88XX 0x01CC - -/* CCK rate ACK timeout */ -#define HALMAC_ACK_TO_CCK_88XX 0x40 - -/* RX pkt max size */ -#define HALMAC_RXPKT_MAX_SIZE 12288 /* 12K */ -#define HALMAC_RXPKT_MAX_SIZE_BASE512 (HALMAC_RXPKT_MAX_SIZE >> 9) - -/* OQT entry */ -#define HALMAC_OQT_ENTRY_AC_88XX 32 -#define HALMAC_OQT_ENTRY_NOAC_88XX 32 - -/* MACID number */ -#define HALMAC_MACID_MAX_88XX 127 +#define OCPBASE_TXBUF_88XX 0x18780000 +#define OCPBASE_DMEM_88XX 0x00200000 +#define OCPBASE_EMEM_88XX 0x00100000 -#define HALMAC_PCIE_GEN1_SPEED_88XX 0x01 -#define HALMAC_PCIE_GEN2_SPEED_88XX 0x02 +#endif /* HALMAC_88XX_SUPPORT */ #endif diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx.c b/hal/halmac/halmac_88xx/halmac_api_88xx.c deleted file mode 100644 index c4360b9..0000000 --- a/hal/halmac/halmac_88xx/halmac_api_88xx.c +++ /dev/null @@ -1,5802 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#include "halmac_88xx_cfg.h" -#include "halmac_gpio_88xx.h" - -/** - * halmac_init_adapter_para_88xx() - int halmac adapter - * @pHalmac_adapter - * - * SD1 internal use - * - * Author : KaiYuan Chang/Ivan Lin - * Return : VOID - */ -VOID -halmac_init_adapter_para_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - pHalmac_adapter->pHalAdapter_backup = pHalmac_adapter; - pHalmac_adapter->pHalEfuse_map = (u8 *)NULL; - pHalmac_adapter->hal_efuse_map_valid = _FALSE; - pHalmac_adapter->efuse_end = 0; - pHalmac_adapter->pHal_mac_addr[0].Address_L_H.Address_Low = 0; - pHalmac_adapter->pHal_mac_addr[0].Address_L_H.Address_High = 0; - pHalmac_adapter->pHal_mac_addr[1].Address_L_H.Address_Low = 0; - pHalmac_adapter->pHal_mac_addr[1].Address_L_H.Address_High = 0; - pHalmac_adapter->pHal_bss_addr[0].Address_L_H.Address_Low = 0; - pHalmac_adapter->pHal_bss_addr[0].Address_L_H.Address_High = 0; - pHalmac_adapter->pHal_bss_addr[1].Address_L_H.Address_Low = 0; - pHalmac_adapter->pHal_bss_addr[1].Address_L_H.Address_High = 0; - - pHalmac_adapter->low_clk = _FALSE; - pHalmac_adapter->max_download_size = HALMAC_FW_MAX_DL_SIZE_88XX; - - pHalmac_adapter->config_para_info.pCfg_para_buf = NULL; - pHalmac_adapter->config_para_info.pPara_buf_w = NULL; - pHalmac_adapter->config_para_info.para_num = 0; - pHalmac_adapter->config_para_info.full_fifo_mode = _FALSE; - pHalmac_adapter->config_para_info.para_buf_size = 0; - pHalmac_adapter->config_para_info.avai_para_buf_size = 0; - pHalmac_adapter->config_para_info.offset_accumulation = 0; - pHalmac_adapter->config_para_info.value_accumulation = 0; - pHalmac_adapter->config_para_info.datapack_segment = 0; - - pHalmac_adapter->ch_sw_info.ch_info_buf = NULL; - pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL; - pHalmac_adapter->ch_sw_info.extra_info_en = 0; - pHalmac_adapter->ch_sw_info.buf_size = 0; - pHalmac_adapter->ch_sw_info.avai_buf_size = 0; - pHalmac_adapter->ch_sw_info.total_size = 0; - pHalmac_adapter->ch_sw_info.ch_num = 0; - - pHalmac_adapter->drv_info_size = 0; - - pHalmac_adapter->txff_allocation.tx_fifo_pg_num = 0; - pHalmac_adapter->txff_allocation.ac_q_pg_num = 0; - pHalmac_adapter->txff_allocation.rsvd_pg_bndy = 0; - pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy = 0; - pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy = 0; - pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy = 0; - pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy = 0; - pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy = 0; - pHalmac_adapter->txff_allocation.pub_queue_pg_num = 0; - pHalmac_adapter->txff_allocation.high_queue_pg_num = 0; - pHalmac_adapter->txff_allocation.low_queue_pg_num = 0; - pHalmac_adapter->txff_allocation.normal_queue_pg_num = 0; - pHalmac_adapter->txff_allocation.extra_queue_pg_num = 0; - - pHalmac_adapter->txff_allocation.la_mode = HALMAC_LA_MODE_DISABLE; - pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode = HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE; - - pHalmac_adapter->hw_config_info.ac_oqt_size = HALMAC_OQT_ENTRY_AC_88XX; - pHalmac_adapter->hw_config_info.non_ac_oqt_size = HALMAC_OQT_ENTRY_NOAC_88XX; - pHalmac_adapter->hw_config_info.ac_queue_num = 8; - - pHalmac_adapter->sdio_cmd53_4byte = HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE; - pHalmac_adapter->sdio_hw_info.io_hi_speed_flag = 0; - pHalmac_adapter->sdio_hw_info.spec_ver = HALMAC_SDIO_SPEC_VER_2_00; - pHalmac_adapter->sdio_hw_info.clock_speed = 50; - - pHalmac_adapter->pinmux_info.wl_led = 0; - pHalmac_adapter->pinmux_info.sdio_int = 0; - pHalmac_adapter->pinmux_info.sw_io_0 = 0; - pHalmac_adapter->pinmux_info.sw_io_1 = 0; - pHalmac_adapter->pinmux_info.sw_io_2 = 0; - pHalmac_adapter->pinmux_info.sw_io_3 = 0; - pHalmac_adapter->pinmux_info.sw_io_4 = 0; - pHalmac_adapter->pinmux_info.sw_io_5 = 0; - pHalmac_adapter->pinmux_info.sw_io_6 = 0; - pHalmac_adapter->pinmux_info.sw_io_7 = 0; - pHalmac_adapter->pinmux_info.sw_io_8 = 0; - pHalmac_adapter->pinmux_info.sw_io_9 = 0; - pHalmac_adapter->pinmux_info.sw_io_10 = 0; - pHalmac_adapter->pinmux_info.sw_io_11 = 0; - pHalmac_adapter->pinmux_info.sw_io_12 = 0; - pHalmac_adapter->pinmux_info.sw_io_13 = 0; - pHalmac_adapter->pinmux_info.sw_io_14 = 0; - pHalmac_adapter->pinmux_info.sw_io_15 = 0; - - halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter); - halmac_init_state_machine_88xx(pHalmac_adapter); -} - -/** - * halmac_init_adapter_dynamic_para_88xx() - int halmac adapter - * @pHalmac_adapter - * - * SD1 internal use - * - * Author : KaiYuan Chang/Ivan Lin - * Return : VOID - */ -VOID -halmac_init_adapter_dynamic_para_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - pHalmac_adapter->h2c_packet_seq = 0; - pHalmac_adapter->h2c_buf_free_space = 0; - pHalmac_adapter->gen_info_valid = _FALSE; -} - -/** - * halmac_init_state_machine_88xx() - init halmac software state machine - * @pHalmac_adapter - * - * SD1 internal use. - * - * Author : KaiYuan Chang/Ivan Lin - * Return : VOID - */ -VOID -halmac_init_state_machine_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - PHALMAC_STATE pState = &pHalmac_adapter->halmac_state; - - halmac_init_offload_feature_state_machine_88xx(pHalmac_adapter); - - pState->api_state = HALMAC_API_STATE_INIT; - - pState->dlfw_state = HALMAC_DLFW_NONE; - pState->mac_power = HALMAC_MAC_POWER_OFF; - pState->ps_state = HALMAC_PS_STATE_UNDEFINE; - pState->gpio_cfg_state = HALMAC_GPIO_CFG_STATE_IDLE; -} - -/** - * halmac_mount_api_88xx() - attach functions to function pointer - * @pHalmac_adapter - * - * SD1 internal use - * - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ -HALMAC_RET_STATUS -halmac_mount_api_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - PHALMAC_API pHalmac_api = (PHALMAC_API)NULL; - - pHalmac_adapter->pHalmac_api = (PHALMAC_API)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(HALMAC_API)); - if (pHalmac_adapter->pHalmac_api == NULL) - return HALMAC_RET_MALLOC_FAIL; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, HALMAC_SVN_VER_88XX"\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MAJOR_VER_88XX = %x\n", HALMAC_MAJOR_VER_88XX); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PROTOTYPE_88XX = %x\n", HALMAC_PROTOTYPE_VER_88XX); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MINOR_VER_88XX = %x\n", HALMAC_MINOR_VER_88XX); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PATCH_VER_88XX = %x\n", HALMAC_PATCH_VER_88XX); - - /* Mount function pointer */ - pHalmac_api->halmac_download_firmware = halmac_download_firmware_88xx; - pHalmac_api->halmac_free_download_firmware = halmac_free_download_firmware_88xx; - pHalmac_api->halmac_get_fw_version = halmac_get_fw_version_88xx; - pHalmac_api->halmac_cfg_mac_addr = halmac_cfg_mac_addr_88xx; - pHalmac_api->halmac_cfg_bssid = halmac_cfg_bssid_88xx; - pHalmac_api->halmac_cfg_multicast_addr = halmac_cfg_multicast_addr_88xx; - pHalmac_api->halmac_pre_init_system_cfg = halmac_pre_init_system_cfg_88xx; - pHalmac_api->halmac_init_system_cfg = halmac_init_system_cfg_88xx; - pHalmac_api->halmac_init_edca_cfg = halmac_init_edca_cfg_88xx; - pHalmac_api->halmac_cfg_operation_mode = halmac_cfg_operation_mode_88xx; - pHalmac_api->halmac_cfg_ch_bw = halmac_cfg_ch_bw_88xx; - pHalmac_api->halmac_cfg_bw = halmac_cfg_bw_88xx; - pHalmac_api->halmac_init_wmac_cfg = halmac_init_wmac_cfg_88xx; - pHalmac_api->halmac_init_mac_cfg = halmac_init_mac_cfg_88xx; - pHalmac_api->halmac_init_sdio_cfg = halmac_init_sdio_cfg_88xx; - pHalmac_api->halmac_init_usb_cfg = halmac_init_usb_cfg_88xx; - pHalmac_api->halmac_init_pcie_cfg = halmac_init_pcie_cfg_88xx; - pHalmac_api->halmac_deinit_sdio_cfg = halmac_deinit_sdio_cfg_88xx; - pHalmac_api->halmac_deinit_usb_cfg = halmac_deinit_usb_cfg_88xx; - pHalmac_api->halmac_deinit_pcie_cfg = halmac_deinit_pcie_cfg_88xx; - pHalmac_api->halmac_dump_efuse_map = halmac_dump_efuse_map_88xx; - pHalmac_api->halmac_dump_efuse_map_bt = halmac_dump_efuse_map_bt_88xx; - pHalmac_api->halmac_write_efuse_bt = halmac_write_efuse_bt_88xx; - pHalmac_api->halmac_read_efuse_bt = halmac_read_efuse_bt_88xx; - pHalmac_api->halmac_cfg_efuse_auto_check = halmac_cfg_efuse_auto_check_88xx; - pHalmac_api->halmac_dump_logical_efuse_map = halmac_dump_logical_efuse_map_88xx; - pHalmac_api->halmac_pg_efuse_by_map = halmac_pg_efuse_by_map_88xx; - pHalmac_api->halmac_get_efuse_size = halmac_get_efuse_size_88xx; - pHalmac_api->halmac_get_efuse_available_size = halmac_get_efuse_available_size_88xx; - pHalmac_api->halmac_get_c2h_info = halmac_get_c2h_info_88xx; - - pHalmac_api->halmac_get_logical_efuse_size = halmac_get_logical_efuse_size_88xx; - - pHalmac_api->halmac_write_logical_efuse = halmac_write_logical_efuse_88xx; - pHalmac_api->halmac_read_logical_efuse = halmac_read_logical_efuse_88xx; - - pHalmac_api->halmac_h2c_lb = halmac_h2c_lb_88xx; - pHalmac_api->halmac_debug = halmac_debug_88xx; - pHalmac_api->halmac_cfg_parameter = halmac_cfg_parameter_88xx; - pHalmac_api->halmac_update_datapack = halmac_update_datapack_88xx; - pHalmac_api->halmac_run_datapack = halmac_run_datapack_88xx; - pHalmac_api->halmac_cfg_drv_info = halmac_cfg_drv_info_88xx; - pHalmac_api->halmac_send_bt_coex = halmac_send_bt_coex_88xx; - pHalmac_api->halmac_verify_platform_api = halmac_verify_platform_api_88xx; - pHalmac_api->halmac_update_packet = halmac_update_packet_88xx; - pHalmac_api->halmac_bcn_ie_filter = halmac_bcn_ie_filter_88xx; - pHalmac_api->halmac_cfg_txbf = halmac_cfg_txbf_88xx; - pHalmac_api->halmac_cfg_mumimo = halmac_cfg_mumimo_88xx; - pHalmac_api->halmac_cfg_sounding = halmac_cfg_sounding_88xx; - pHalmac_api->halmac_del_sounding = halmac_del_sounding_88xx; - pHalmac_api->halmac_su_bfer_entry_init = halmac_su_bfer_entry_init_88xx; - pHalmac_api->halmac_su_bfee_entry_init = halmac_su_bfee_entry_init_88xx; - pHalmac_api->halmac_mu_bfer_entry_init = halmac_mu_bfer_entry_init_88xx; - pHalmac_api->halmac_mu_bfee_entry_init = halmac_mu_bfee_entry_init_88xx; - pHalmac_api->halmac_su_bfer_entry_del = halmac_su_bfer_entry_del_88xx; - pHalmac_api->halmac_su_bfee_entry_del = halmac_su_bfee_entry_del_88xx; - pHalmac_api->halmac_mu_bfer_entry_del = halmac_mu_bfer_entry_del_88xx; - pHalmac_api->halmac_mu_bfee_entry_del = halmac_mu_bfee_entry_del_88xx; - - pHalmac_api->halmac_add_ch_info = halmac_add_ch_info_88xx; - pHalmac_api->halmac_add_extra_ch_info = halmac_add_extra_ch_info_88xx; - pHalmac_api->halmac_ctrl_ch_switch = halmac_ctrl_ch_switch_88xx; - pHalmac_api->halmac_p2pps = halmac_p2pps_88xx; - pHalmac_api->halmac_clear_ch_info = halmac_clear_ch_info_88xx; - pHalmac_api->halmac_send_general_info = halmac_send_general_info_88xx; - - pHalmac_api->halmac_start_iqk = halmac_start_iqk_88xx; - pHalmac_api->halmac_ctrl_pwr_tracking = halmac_ctrl_pwr_tracking_88xx; - pHalmac_api->halmac_psd = halmac_psd_88xx; - pHalmac_api->halmac_cfg_la_mode = halmac_cfg_la_mode_88xx; - pHalmac_api->halmac_cfg_rx_fifo_expanding_mode = halmac_cfg_rx_fifo_expanding_mode_88xx; - - pHalmac_api->halmac_config_security = halmac_config_security_88xx; - pHalmac_api->halmac_get_used_cam_entry_num = halmac_get_used_cam_entry_num_88xx; - pHalmac_api->halmac_read_cam_entry = halmac_read_cam_entry_88xx; - pHalmac_api->halmac_write_cam = halmac_write_cam_88xx; - pHalmac_api->halmac_clear_cam_entry = halmac_clear_cam_entry_88xx; - - pHalmac_api->halmac_get_hw_value = halmac_get_hw_value_88xx; - pHalmac_api->halmac_set_hw_value = halmac_set_hw_value_88xx; - - pHalmac_api->halmac_cfg_drv_rsvd_pg_num = halmac_cfg_drv_rsvd_pg_num_88xx; - pHalmac_api->halmac_get_chip_version = halmac_get_chip_version_88xx; - - pHalmac_api->halmac_query_status = halmac_query_status_88xx; - pHalmac_api->halmac_reset_feature = halmac_reset_feature_88xx; - pHalmac_api->halmac_check_fw_status = halmac_check_fw_status_88xx; - pHalmac_api->halmac_dump_fw_dmem = halmac_dump_fw_dmem_88xx; - pHalmac_api->halmac_cfg_max_dl_size = halmac_cfg_max_dl_size_88xx; - - pHalmac_api->halmac_dump_fifo = halmac_dump_fifo_88xx; - pHalmac_api->halmac_get_fifo_size = halmac_get_fifo_size_88xx; - - pHalmac_api->halmac_chk_txdesc = halmac_chk_txdesc_88xx; - pHalmac_api->halmac_dl_drv_rsvd_page = halmac_dl_drv_rsvd_page_88xx; - pHalmac_api->halmac_cfg_csi_rate = halmac_cfg_csi_rate_88xx; - - pHalmac_api->halmac_sdio_cmd53_4byte = halmac_sdio_cmd53_4byte_88xx; - pHalmac_api->halmac_sdio_hw_info = halmac_sdio_hw_info_88xx; - pHalmac_api->halmac_txfifo_is_empty = halmac_txfifo_is_empty_88xx; - pHalmac_api->halmac_download_flash = halmac_download_flash_88xx; - pHalmac_api->halmac_read_flash = halmac_read_flash_88xx; - pHalmac_api->halmac_erase_flash = halmac_erase_flash_88xx; - pHalmac_api->halmac_check_flash = halmac_check_flash_88xx; - pHalmac_api->halmac_cfg_edca_para = halmac_cfg_edca_para_88xx; - pHalmac_api->halmac_pinmux_wl_led_mode = halmac_pinmux_wl_led_mode_88xx; - pHalmac_api->halmac_pinmux_wl_led_sw_ctrl = halmac_pinmux_wl_led_sw_ctrl_88xx; - pHalmac_api->halmac_pinmux_sdio_int_polarity = halmac_pinmux_sdio_int_polarity_88xx; - pHalmac_api->halmac_pinmux_gpio_mode = halmac_pinmux_gpio_mode_88xx; - pHalmac_api->halmac_pinmux_gpio_output = halmac_pinmux_gpio_output_88xx; - pHalmac_api->halmac_pinmux_pin_status = halmac_pinmux_pin_status_88xx; - - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { - pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_sdio; - pHalmac_api->halmac_init_interface_cfg = halmac_init_sdio_cfg_88xx; - pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_sdio_cfg_88xx; - pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_sdio_88xx; - pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_sdio_88xx; - pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_sdio_88xx; - pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_sdio_88xx; - pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_sdio_88xx; - pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_sdio_88xx; - pHalmac_api->halmac_reg_read_indirect_32 = halmac_reg_read_indirect_32_sdio_88xx; - pHalmac_api->halmac_reg_sdio_cmd53_read_n = halmac_reg_read_nbyte_sdio_88xx; - } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) { - pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_usb; - pHalmac_api->halmac_init_interface_cfg = halmac_init_usb_cfg_88xx; - pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_usb_cfg_88xx; - pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_usb_88xx; - pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_usb_88xx; - pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_usb_88xx; - pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_usb_88xx; - pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_usb_88xx; - pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_usb_88xx; - } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) { - pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_pcie; - pHalmac_api->halmac_init_interface_cfg = halmac_init_pcie_cfg_88xx; - pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_pcie_cfg_88xx; - pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_pcie_88xx; - pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_pcie_88xx; - pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_pcie_88xx; - pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_pcie_88xx; - pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_pcie_88xx; - pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_pcie_88xx; - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Set halmac io function Error!!\n"); - } - - pHalmac_api->halmac_set_bulkout_num = halmac_set_bulkout_num_88xx; - pHalmac_api->halmac_get_sdio_tx_addr = halmac_get_sdio_tx_addr_88xx; - pHalmac_api->halmac_get_usb_bulkout_id = halmac_get_usb_bulkout_id_88xx; - pHalmac_api->halmac_timer_2s = halmac_timer_2s_88xx; - pHalmac_api->halmac_fill_txdesc_checksum = halmac_fill_txdesc_check_sum_88xx; - - - if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8822B) { -#if HALMAC_8822B_SUPPORT - /*mount 8822b function and data*/ - halmac_mount_api_8822b(pHalmac_adapter); -#endif - - } else if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) { -#if HALMAC_8821C_SUPPORT - /*mount 8822b function and data*/ - halmac_mount_api_8821c(pHalmac_adapter); -#endif - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Chip ID undefine!!\n"); - return HALMAC_RET_CHIP_NOT_SUPPORT; - } -#if HALMAC_PLATFORM_TESTPROGRAM - pHalmac_api->halmac_write_efuse = halmac_write_efuse_88xx; - pHalmac_api->halmac_read_efuse = halmac_read_efuse_88xx; - pHalmac_api->halmac_switch_efuse_bank = halmac_switch_efuse_bank_88xx; - - pHalmac_api->halmac_gen_txdesc = halmac_gen_tx_desc_88xx; - pHalmac_api->halmac_txdesc_parser = halmac_tx_desc_parser_88xx; - pHalmac_api->halmac_rxdesc_parser = halmac_rx_desc_parser_88xx; - pHalmac_api->halmac_get_txdesc_size = halmac_get_txdesc_size_88xx; - pHalmac_api->halmac_send_packet = halmac_send_packet_88xx; - pHalmac_api->halmac_parse_packet = halmac_parse_packet_88xx; - - pHalmac_api->halmac_get_pcie_packet = halmac_get_pcie_packet_88xx; - pHalmac_api->halmac_gen_txagg_desc = halmac_gen_txagg_desc_88xx; - - pHalmac_api->halmac_bb_reg_read = halmac_bb_reg_read_88xx; - pHalmac_api->halmac_bb_reg_write = halmac_bb_reg_write_88xx; - - pHalmac_api->halmac_rf_reg_read = halmac_rf_ac_reg_read_88xx; - pHalmac_api->halmac_rf_reg_write = halmac_rf_ac_reg_write_88xx; - pHalmac_api->halmac_init_antenna_selection = halmac_init_antenna_selection_88xx; - pHalmac_api->halmac_bb_preconfig = halmac_bb_preconfig_88xx; - pHalmac_api->halmac_init_crystal_capacity = halmac_init_crystal_capacity_88xx; - pHalmac_api->halmac_trx_antenna_setting = halmac_trx_antenna_setting_88xx; - - pHalmac_api->halmac_himr_setting_sdio = halmac_himr_setting_88xx_sdio; - - pHalmac_api->halmac_send_beacon = halmac_send_beacon_88xx; - pHalmac_api->halmac_stop_beacon = halmac_stop_beacon_88xx; - pHalmac_api->halmac_check_trx_status = halmac_check_trx_status_88xx; - pHalmac_api->halmac_set_agg_num = halmac_set_agg_num_88xx; - pHalmac_api->halmac_get_management_txdesc = halmac_get_management_txdesc_88xx; - pHalmac_api->halmac_send_control = halmac_send_control_88xx; - pHalmac_api->halmac_send_hiqueue = halmac_send_hiqueue_88xx; - - pHalmac_api->halmac_timer_10ms = halmac_timer_10ms_88xx; - - pHalmac_api->halmac_download_firmware_fpag = halmac_download_firmware_fpga_88xx; - pHalmac_api->halmac_download_rom_fpga = halmac_download_rom_fpga_88xx; - pHalmac_api->halmac_send_nlo = halmac_send_nlo_88xx; - - pHalmac_api->halmac_dump_cam_table = halmac_dump_cam_table_88xx; - pHalmac_api->halmac_load_cam_table = halmac_load_cam_table_88xx; - - pHalmac_api->halmac_get_chip_type = halmac_get_chip_type_88xx; - - pHalmac_api->halmac_get_rx_agg_num = halmac_get_rx_agg_num_88xx; - pHalmac_api->halmac_check_rx_scsi_resp = halmac_check_rx_scsi_resp_88xx_usb; - - pHalmac_api->halmac_get_hcpwm = halmac_get_hcpwm_88xx; - pHalmac_api->halmac_get_hcpwm2 = halmac_get_hcpwm2_88xx; - pHalmac_api->halmac_set_hrpwm = halmac_set_hrpwm_88xx; - pHalmac_api->halmac_set_hrpwm2 = halmac_set_hrpwm2_88xx; - pHalmac_api->halmac_coex_cfg = halmac_coex_cfg_88xx; -#if HALMAC_8822B_SUPPORT - if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8822B) - pHalmac_api->halmac_run_pwrseq = halmac_run_pwrseq_8822b; -#endif -#if HALMAC_8821C_SUPPORT - if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) - pHalmac_api->halmac_run_pwrseq = halmac_run_pwrseq_8821c; -#endif - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { - pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_sdio_88xx; - pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_sdio_88xx; - pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_sdio_88xx; - pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_sdio_88xx; - pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_sdio_88xx; - pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_sdio_88xx; - } -#endif - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_download_firmware_88xx() - download Firmware - * @pHalmac_adapter : the adapter of halmac - * @pHamacl_fw : firmware bin - * @halmac_fw_size : firmware size - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_download_firmware_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHamacl_fw, - IN u32 halmac_fw_size -) -{ - u8 value8; - u8 *pFile_ptr; - u16 value16; - u32 restore_index = 0; - u16 halmac_h2c_ver = 0, fw_h2c_ver = 0; - u32 iram_pkt_size, dmem_pkt_size, eram_pkt_size = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RESTORE_INFO restore_info[DLFW_RESTORE_REG_NUM_88XX]; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx ==========>\n"); - - if (halmac_fw_size > HALMAC_FW_SIZE_MAX_88XX || halmac_fw_size < HALMAC_FWHDR_SIZE_88XX) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "FW size error!\n"); - return HALMAC_RET_FW_SIZE_ERR; - } - - fw_h2c_ver = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX))); - halmac_h2c_ver = H2C_FORMAT_VERSION; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac h2c/c2h format = %x, fw h2c/c2h format = %x!!\n", halmac_h2c_ver, fw_h2c_ver); - if (fw_h2c_ver != halmac_h2c_ver) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "[WARN]H2C/C2H version between HALMAC and FW is compatible!!\n"); - - pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1); - value8 = (u8)(value8 & ~(BIT(2))); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, value8); /* Disable CPU reset */ - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RSV_CTRL + 1); - value8 = (u8)(value8 & ~(BIT(0))); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RSV_CTRL + 1, value8); - - restore_info[restore_index].length = 1; - restore_info[restore_index].mac_register = REG_TXDMA_PQ_MAP + 1; - restore_info[restore_index].value = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP + 1); - restore_index++; - value8 = HALMAC_DMA_MAPPING_HIGH << 6; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP + 1, value8); /* set HIQ to hi priority */ - - /* DLFW only use HIQ, map HIQ to hi priority */ - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - restore_info[restore_index].length = 1; - restore_info[restore_index].mac_register = REG_CR; - restore_info[restore_index].value = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR); - restore_index++; - restore_info[restore_index].length = 4; - restore_info[restore_index].mac_register = REG_H2CQ_CSR; - restore_info[restore_index].value = BIT(31); - restore_index++; - value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31)); - - /* Config hi priority queue and public priority queue page number (only for DLFW) */ - restore_info[restore_index].length = 2; - restore_info[restore_index].mac_register = REG_FIFOPAGE_INFO_1; - restore_info[restore_index].value = HALMAC_REG_READ_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1); - restore_index++; - restore_info[restore_index].length = 4; - restore_info[restore_index].mac_register = REG_RQPN_CTRL_2; - restore_info[restore_index].value = HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31); - restore_index++; - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, 0x200); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, restore_info[restore_index - 1].value); - - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) - HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG); - - halmac_update_fw_info_88xx(pHalmac_adapter, pHamacl_fw, halmac_fw_size); - - dmem_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX)); - iram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX)); - if (0 != ((*(pHamacl_fw + HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX)) & BIT(4))) - eram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX)); - - dmem_pkt_size = rtk_le32_to_cpu(dmem_pkt_size); - iram_pkt_size = rtk_le32_to_cpu(iram_pkt_size); - eram_pkt_size = rtk_le32_to_cpu(eram_pkt_size); - - dmem_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; - iram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; - if (eram_pkt_size != 0) - eram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; - - if (halmac_fw_size != (HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size + eram_pkt_size)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "FW size mismatch the real fw size!\n"); - goto DLFW_FAIL; - } - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 1); - restore_info[restore_index].length = 1; - restore_info[restore_index].mac_register = REG_CR + 1; - restore_info[restore_index].value = value8; - restore_index++; - value8 = (u8)(value8 | BIT(0)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, value8); /* Enable SW TX beacon */ - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL); - restore_info[restore_index].length = 1; - restore_info[restore_index].mac_register = REG_BCN_CTRL; - restore_info[restore_index].value = value8; - restore_index++; - value8 = (u8)((value8 & (~BIT(3))) | BIT(4)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, value8); /* Disable beacon related functions */ - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2); - restore_info[restore_index].length = 1; - restore_info[restore_index].mac_register = REG_FWHW_TXQ_CTRL + 2; - restore_info[restore_index].value = value8; - restore_index++; - value8 = (u8)(value8 & ~(BIT(6))); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8); /* Disable ptcl tx bcnq */ - - restore_info[restore_index].length = 2; - restore_info[restore_index].mac_register = REG_FIFOPAGE_CTRL_2; - restore_info[restore_index].value = HALMAC_REG_READ_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2) | BIT(15); - restore_index++; - value16 = 0x8000; - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, value16); /* Set beacon header to 0 */ - - value16 = (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) & 0x3800); - value16 |= BIT(0); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MCUFW_CTRL, value16); /* MCU/FW setting */ - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2); - value8 &= ~(BIT(0)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2, value8); - value8 |= BIT(0); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2, value8); - - pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX; - if (halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, - rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX))) & ~(BIT(31)), dmem_pkt_size) != HALMAC_RET_SUCCESS) - goto DLFW_END; - - pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size; - if (halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, - rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX))) & ~(BIT(31)), iram_pkt_size) != HALMAC_RET_SUCCESS) - goto DLFW_END; - - if (eram_pkt_size != 0) { - pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size; - if (halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, - rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX))) & ~(BIT(31)), eram_pkt_size) != HALMAC_RET_SUCCESS) - goto DLFW_END; - } - - halmac_init_offload_feature_state_machine_88xx(pHalmac_adapter); -DLFW_END: - - halmac_restore_mac_register_88xx(pHalmac_adapter, restore_info, DLFW_RESTORE_REG_NUM_88XX); - - if (halmac_dlfw_end_flow_88xx(pHalmac_adapter) != HALMAC_RET_SUCCESS) - goto DLFW_FAIL; - - pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_DONE; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; - -DLFW_FAIL: - - /* Disable FWDL_EN */ - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & ~(BIT(0)))); - - return HALMAC_RET_DLFW_FAIL; -} - -/** - * halmac_free_download_firmware_88xx() - download specific memory firmware - * @pHalmac_adapter - * @dlfw_mem : memory selection - * @pHamacl_fw : firmware bin - * @halmac_fw_size : firmware size - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - */ -HALMAC_RET_STATUS -halmac_free_download_firmware_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DLFW_MEM dlfw_mem, - IN u8 *pHamacl_fw, - IN u32 halmac_fw_size -) -{ - u8 tx_pause_backup; - u8 *pFile_ptr; - u16 bcn_head_backup; - u32 iram_pkt_size, dmem_pkt_size, eram_pkt_size = 0; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_DLFW_FAIL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_free_download_firmware_88xx ==========>\n"); - - if (halmac_fw_size > HALMAC_FW_SIZE_MAX_88XX || halmac_fw_size < HALMAC_FWHDR_SIZE_88XX) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]FW size error!\n"); - return HALMAC_RET_FW_SIZE_ERR; - } - - dmem_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX)); - iram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX)); - if (0 != ((*(pHamacl_fw + HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX)) & BIT(4))) - eram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX)); - - dmem_pkt_size = rtk_le32_to_cpu(dmem_pkt_size); - iram_pkt_size = rtk_le32_to_cpu(iram_pkt_size); - eram_pkt_size = rtk_le32_to_cpu(eram_pkt_size); - - dmem_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; - iram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; - if (eram_pkt_size != 0) - eram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; - - if (halmac_fw_size != (HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size + eram_pkt_size)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]FW size mismatch the real fw size!\n"); - return HALMAC_RET_DLFW_FAIL; - } - - tx_pause_backup = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPAUSE); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXPAUSE, tx_pause_backup | BIT(7)); - - bcn_head_backup = HALMAC_REG_READ_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2) | BIT(15); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0x8000); - - if (eram_pkt_size != 0) { - pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size; - status = halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, - rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX))) & ~(BIT(31)), eram_pkt_size); - if (status != HALMAC_RET_SUCCESS) - goto DL_FREE_FW_END; - } - - status = halmac_free_dl_fw_end_flow_88xx(pHalmac_adapter); - -DL_FREE_FW_END: - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXPAUSE, tx_pause_backup); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, bcn_head_backup); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_free_download_firmware_88xx <==========\n"); - - return status; -} - -/** - * halmac_get_fw_version_88xx() - get FW version - * @pHalmac_adapter : the adapter of halmac - * @pFw_version : fw version info - * Author : Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_get_fw_version_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT PHALMAC_FW_VERSION pFw_version -) -{ - PHALMAC_FW_VERSION pFw_info = &pHalmac_adapter->fw_version; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (pFw_version == NULL) - return HALMAC_RET_NULL_POINTER; - - if (pHalmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) - return HALMAC_RET_NO_DLFW; - - pFw_version->version = pFw_info->version; - pFw_version->sub_version = pFw_info->sub_version; - pFw_version->sub_index = pFw_info->sub_index; - pFw_version->h2c_version = pFw_info->h2c_version; - pFw_version->build_time.month = pFw_info->build_time.month; - pFw_version->build_time.date = pFw_info->build_time.date; - pFw_version->build_time.hour = pFw_info->build_time.hour; - pFw_version->build_time.min = pFw_info->build_time.min; - pFw_version->build_time.year = pFw_info->build_time.year; - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_mac_addr_88xx() - config mac address - * @pHalmac_adapter : the adapter of halmac - * @halmac_port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 - * @pHal_address : mac address - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_mac_addr_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 halmac_port, - IN PHALMAC_WLAN_ADDR pHal_address -) -{ - u16 mac_address_H; - u32 mac_address_L; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_mac_addr_88xx ==========>\n"); - - if (halmac_port >= HALMAC_PORTIDMAX) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]port index > 5\n"); - return HALMAC_RET_PORT_NOT_SUPPORT; - } - - mac_address_L = pHal_address->Address_L_H.Address_Low; - mac_address_H = pHal_address->Address_L_H.Address_High; - - mac_address_L = rtk_le32_to_cpu(mac_address_L); - mac_address_H = rtk_le16_to_cpu(mac_address_H); - - pHalmac_adapter->pHal_mac_addr[halmac_port].Address_L_H.Address_Low = mac_address_L; - pHalmac_adapter->pHal_mac_addr[halmac_port].Address_L_H.Address_High = mac_address_H; - - switch (halmac_port) { - case HALMAC_PORTID0: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID, mac_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID + 4, mac_address_H); - break; - - case HALMAC_PORTID1: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID1, mac_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID1 + 4, mac_address_H); - break; - - case HALMAC_PORTID2: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID2, mac_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID2 + 4, mac_address_H); - break; - - case HALMAC_PORTID3: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID3, mac_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID3 + 4, mac_address_H); - break; - - case HALMAC_PORTID4: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID4, mac_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID4 + 4, mac_address_H); - break; - - default: - break; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_mac_addr_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_bssid_88xx() - config BSSID - * @pHalmac_adapter : the adapter of halmac - * @halmac_port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 - * @pHal_address : bssid - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_bssid_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 halmac_port, - IN PHALMAC_WLAN_ADDR pHal_address -) -{ - u16 bssid_address_H; - u32 bssid_address_L; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_bssid_88xx ==========>\n"); - - if (halmac_port >= HALMAC_PORTIDMAX) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]port index > 5\n"); - return HALMAC_RET_PORT_NOT_SUPPORT; - } - - bssid_address_L = pHal_address->Address_L_H.Address_Low; - bssid_address_H = pHal_address->Address_L_H.Address_High; - - bssid_address_L = rtk_le32_to_cpu(bssid_address_L); - bssid_address_H = rtk_le16_to_cpu(bssid_address_H); - - pHalmac_adapter->pHal_bss_addr[halmac_port].Address_L_H.Address_Low = bssid_address_L; - pHalmac_adapter->pHal_bss_addr[halmac_port].Address_L_H.Address_High = bssid_address_H; - - switch (halmac_port) { - case HALMAC_PORTID0: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID, bssid_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID + 4, bssid_address_H); - break; - - case HALMAC_PORTID1: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID1, bssid_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID1 + 4, bssid_address_H); - break; - - case HALMAC_PORTID2: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID2, bssid_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID2 + 4, bssid_address_H); - break; - - case HALMAC_PORTID3: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID3, bssid_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID3 + 4, bssid_address_H); - break; - - case HALMAC_PORTID4: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID4, bssid_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID4 + 4, bssid_address_H); - break; - - default: - break; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_bssid_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_multicast_addr_88xx() - config multicast address - * @pHalmac_adapter : the adapter of halmac - * @pHal_address : multicast address - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_multicast_addr_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_WLAN_ADDR pHal_address -) -{ - u16 address_H; - u32 address_L; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_multicast_addr_88xx ==========>\n"); - - address_L = pHal_address->Address_L_H.Address_Low; - address_H = pHal_address->Address_L_H.Address_High; - - address_L = rtk_le32_to_cpu(address_L); - address_H = rtk_le16_to_cpu(address_H); - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MAR, address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MAR + 4, address_H); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_multicast_addr_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_pre_init_system_cfg_88xx() - pre-init system config - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_pre_init_system_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u32 value32, counter; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - u8 enable_bb; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pre_init_system_cfg ==========>\n"); - - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL) & ~(BIT(0))); - counter = 10000; - while (!(HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL) & 0x02)) { - counter--; - if (counter == 0) - return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL; - } - - if (pHalmac_adapter->sdio_hw_info.spec_ver == HALMAC_SDIO_SPEC_VER_3_00) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_HCI_OPT_CTRL + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_HCI_OPT_CTRL + 2) | BIT(2)); - else - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_HCI_OPT_CTRL + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_HCI_OPT_CTRL + 2) & ~(BIT(2))); - } else if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) { - if (HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2 + 3) == 0x20) /* usb3.0 */ - HALMAC_REG_WRITE_8(pHalmac_adapter, 0xFE5B, HALMAC_REG_READ_8(pHalmac_adapter, 0xFE5B) | BIT(4)); - } - - /* Config PIN Mux */ - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL1); - value32 = value32 & (~(BIT(28) | BIT(29))); - value32 = value32 | BIT(28) | BIT(29); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL1, value32); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_LED_CFG); - value32 = value32 & (~(BIT(25) | BIT(26))); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_LED_CFG, value32); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_GPIO_MUXCFG); - value32 = value32 & (~(BIT(2))); - value32 = value32 | BIT(2); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_GPIO_MUXCFG, value32); - - enable_bb = _FALSE; - halmac_set_hw_value_88xx(pHalmac_adapter, HALMAC_HW_EN_BB_RF, &enable_bb); - - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pre_init_system_cfg <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_init_system_cfg_88xx() - init system config - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_init_system_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - u32 temp = 0; - - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_system_cfg ==========>\n"); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, HALMAC_FUNCTION_ENABLE_88XX); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SYS_SDIO_CTRL, (u32)(HALMAC_REG_READ_32(pHalmac_adapter, REG_SYS_SDIO_CTRL) | BIT_LTE_MUX_CTRL_PATH)); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CPU_DMEM_CON, (u32)(HALMAC_REG_READ_32(pHalmac_adapter, REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST)); - - /*disable boot-from-flash for driver's DL FW*/ - temp = HALMAC_REG_READ_32(pHalmac_adapter, REG_MCUFW_CTRL); - if (temp & BIT_BOOT_FSPI_EN) { - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MCUFW_CTRL, temp & (~BIT_BOOT_FSPI_EN)); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_GPIO_MUXCFG, HALMAC_REG_READ_32(pHalmac_adapter, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN)); - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_system_cfg <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_init_edca_cfg_88xx() - init EDCA config - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_init_edca_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u32 value32; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_edca_cfg_88xx ==========>\n"); - - /* Clear TX pause */ - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXPAUSE, 0x0000); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SLOT, HALMAC_SLOT_TIME_88XX); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PIFS, HALMAC_PIFS_TIME_88XX); - value32 = HALMAC_SIFS_CCK_CTX_88XX | (HALMAC_SIFS_OFDM_CTX_88XX << BIT_SHIFT_SIFS_OFDM_CTX) | - (HALMAC_SIFS_CCK_TRX_88XX << BIT_SHIFT_SIFS_CCK_TRX) | (HALMAC_SIFS_OFDM_TRX_88XX << BIT_SHIFT_SIFS_OFDM_TRX); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SIFS, value32); - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EDCA_VO_PARAM, HALMAC_REG_READ_32(pHalmac_adapter, REG_EDCA_VO_PARAM) & 0xFFFF); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_EDCA_VO_PARAM + 2, HALMAC_VO_TXOP_LIMIT_88XX); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_EDCA_VI_PARAM + 2, HALMAC_VI_TXOP_LIMIT_88XX); - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RD_NAV_NXT, HALMAC_RDG_NAV_88XX | (HALMAC_TXOP_NAV_88XX << 16)); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXTSF_OFFSET_CCK, HALMAC_CCK_RX_TSF_88XX | (HALMAC_OFDM_RX_TSF_88XX) << 8); - - /* Set beacon cotnrol - enable TSF and other related functions */ - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL) | BIT_EN_BCN_FUNCTION)); - - /* Set send beacon related registers */ - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TBTT_PROHIBIT, HALMAC_TBTT_PROHIBIT_88XX | (HALMAC_TBTT_HOLD_TIME_88XX << BIT_SHIFT_TBTT_HOLD_TIME_AP)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DRVERLYINT, HALMAC_DRIVER_EARLY_INT_88XX); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCNDMATIM, HALMAC_BEACON_DMA_TIM_88XX); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_edca_cfg_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_init_wmac_cfg_88xx() - init wmac config - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_init_wmac_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_wmac_cfg_88xx ==========>\n"); - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RXFLTMAP0, HALMAC_RX_FILTER0_88XX); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXFLTMAP, HALMAC_RX_FILTER_88XX); - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RCR, HALMAC_RCR_CONFIG_88XX); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_PKT_LIMIT, HALMAC_RXPKT_MAX_SIZE_BASE512); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_TCR + 1) | 0x30)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 2, 0x30); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 1, 0x00); - -#if HALMAC_8821C_SUPPORT - if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_ACKTO_CCK, HALMAC_ACK_TO_CCK_88XX); -#endif - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 8, 0x30810041); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4, 0x50802098); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_wmac_cfg_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_init_mac_cfg_88xx() - config page1~page7 register - * @pHalmac_adapter : the adapter of halmac - * @mode : trx mode - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_init_mac_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE mode -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_mac_cfg_88xx ==========>mode = %d\n", mode); - - status = pHalmac_api->halmac_init_trx_cfg(pHalmac_adapter, mode); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg errorr = %x\n", status); - return status; - } -#if 1 - status = pHalmac_api->halmac_init_protocol_cfg(pHalmac_adapter); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_protocol_cfg_88xx error = %x\n", status); - return status; - } - - status = halmac_init_edca_cfg_88xx(pHalmac_adapter); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_edca_cfg_88xx error = %x\n", status); - return status; - } - - status = halmac_init_wmac_cfg_88xx(pHalmac_adapter); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_wmac_cfg_88xx error = %x\n", status); - return status; - } -#endif - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_mac_cfg_88xx <==========\n"); - - return status; -} - -/** - * halmac_cfg_operation_mode_88xx() - config operation mode - * @pHalmac_adapter : the adapter of halmac - * @wireless_mode : 802.11 standard(b/g/n/ac¡K) - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_operation_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_WIRELESS_MODE wireless_mode -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_operation_mode_88xx ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]wireless_mode = %d\n", wireless_mode); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_operation_mode_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_ch_bw_88xx() - config channel & bandwidth - * @pHalmac_adapter : the adapter of halmac - * @channel : WLAN channel, support 2.4G & 5G - * @pri_ch_idx : primary channel index, idx1, idx2, idx3, idx4 - * @bw : band width, 20, 40, 80, 160, 5 ,10 - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_ch_bw_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 channel, - IN HALMAC_PRI_CH_IDX pri_ch_idx, - IN HALMAC_BW bw -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_ch_bw_88xx ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]ch = %d, idx=%d, bw=%d\n", channel, pri_ch_idx, bw); - - halmac_cfg_pri_ch_idx_88xx(pHalmac_adapter, pri_ch_idx); - - halmac_cfg_bw_88xx(pHalmac_adapter, bw); - - halmac_cfg_ch_88xx(pHalmac_adapter, channel); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_bw_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_cfg_ch_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 channel -) -{ - u8 value8; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_ch_88xx ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]ch = %d\n", channel); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CCK_CHECK); - value8 = value8 & (~(BIT(7))); - - if (channel > 35) - value8 = value8 | BIT(7); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CCK_CHECK, value8); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_cfg_pri_ch_idx_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_PRI_CH_IDX pri_ch_idx -) -{ - u8 txsc_40 = 0, txsc_20 = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_pri_ch_idx_88xx ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]idx=%d\n", pri_ch_idx); - - txsc_20 = pri_ch_idx; - if ((txsc_20 == HALMAC_CH_IDX_1) || (txsc_20 == HALMAC_CH_IDX_3)) - txsc_40 = 9; - else - txsc_40 = 10; - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DATA_SC, BIT_TXSC_20M(txsc_20) | BIT_TXSC_40M(txsc_40)); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_pri_ch_idx_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_bw_88xx() - config bandwidth - * @pHalmac_adapter : the adapter of halmac - * @bw : band width, 20, 40, 80, 160, 5 ,10 - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_bw_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_BW bw -) -{ - u32 value32; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_bw_88xx ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]bw=%d\n", bw); - - /* RF Mode */ - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WMAC_TRXPTCL_CTL); - value32 = value32 & (~(BIT(7) | BIT(8))); - - switch (bw) { - case HALMAC_BW_80: - value32 = value32 | BIT(7); - break; - case HALMAC_BW_40: - value32 = value32 | BIT(8); - break; - case HALMAC_BW_20: - case HALMAC_BW_10: - case HALMAC_BW_5: - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_bw_88xx switch case not support\n"); - break; - } - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_TRXPTCL_CTL, value32); - - /* MAC CLK */ - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_AFE_CTRL1); - value32 = (value32 & (~(BIT(20) | BIT(21)))) | (HALMAC_MAC_CLOCK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_AFE_CTRL1, value32); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_USTIME_TSF, HALMAC_MAC_CLOCK_88XX); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_USTIME_EDCA, HALMAC_MAC_CLOCK_88XX); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_bw_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_dump_efuse_map_88xx() - dump "physical" efuse map - * @pHalmac_adapter : the adapter of halmac - * @cfg : dump efuse method - * Author : Ivan Lin/KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_dump_efuse_map_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_EFUSE_READ_CFG cfg -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_88xx ==========>cfg=%d\n", cfg); - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(dump efuse)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); - return HALMAC_RET_ERROR_STATE; - } - - if (pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_WARN, "[WARN]Dump efuse in suspend mode\n"); - - *pProcess_status = HALMAC_CMD_PROCESS_IDLE; - pHalmac_adapter->event_trigger.physical_efuse_map = 1; - - status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); - return status; - } - - status = halmac_dump_efuse_88xx(pHalmac_adapter, cfg); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_efuse error = %x\n", status); - return status; - } - - if (pHalmac_adapter->hal_efuse_map_valid == _TRUE) { - *pProcess_status = HALMAC_CMD_PROCESS_DONE; - - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, *pProcess_status, - pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size); - pHalmac_adapter->event_trigger.physical_efuse_map = 0; - } - - if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_dump_efuse_map_bt_88xx() - dump "BT physical" efuse map - * @pHalmac_adapter : the adapter of halmac - * @halmac_efuse_bank : bt efuse bank - * @bt_efuse_map_size : bt efuse map size. get from halmac_get_efuse_size API - * @pBT_efuse_map : bt efuse map - * Author : Soar / Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_dump_efuse_map_bt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_EFUSE_BANK halmac_efuse_bank, - IN u32 bt_efuse_map_size, - OUT u8 *pBT_efuse_map -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_bt_88xx ==========>\n"); - - if (pHalmac_adapter->hw_config_info.bt_efuse_size != bt_efuse_map_size) - return HALMAC_RET_EFUSE_SIZE_INCORRECT; - - if ((halmac_efuse_bank >= HALMAC_EFUSE_BANK_MAX) || (halmac_efuse_bank == HALMAC_EFUSE_BANK_WIFI)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Undefined BT bank\n"); - return HALMAC_RET_EFUSE_BANK_INCORRECT; - } - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(dump efuse)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); - return HALMAC_RET_ERROR_STATE; - } - - status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, halmac_efuse_bank); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); - return status; - } - - status = halmac_read_hw_efuse_88xx(pHalmac_adapter, 0, bt_efuse_map_size, pBT_efuse_map); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_hw_efuse_88xx error = %x\n", status); - return status; - } - - if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_bt_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_write_efuse_bt_88xx() - write "BT physical" efuse offset - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : offset - * @halmac_value : Write value - * @pBT_efuse_map : bt efuse map - * Author : Soar - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_write_efuse_bt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u8 halmac_value, - IN HALMAC_EFUSE_BANK halmac_efuse_bank -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_efuse_bt_88xx ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "offset : %X value : %X Bank : %X\n", halmac_offset, halmac_value, halmac_efuse_bank); - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); - return HALMAC_RET_ERROR_STATE; - } - - if (halmac_offset >= pHalmac_adapter->hw_config_info.efuse_size) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n"); - return HALMAC_RET_EFUSE_SIZE_INCORRECT; - } - - if ((halmac_efuse_bank > HALMAC_EFUSE_BANK_MAX) || (halmac_efuse_bank == HALMAC_EFUSE_BANK_WIFI)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Undefined BT bank\n"); - return HALMAC_RET_EFUSE_BANK_INCORRECT; - } - - status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, halmac_efuse_bank); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); - return status; - } - - status = halmac_func_write_efuse_88xx(pHalmac_adapter, halmac_offset, halmac_value); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_write_efuse error = %x\n", status); - return status; - } - - if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_efuse_bt_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_read_efuse_bt_88xx() - read "BT physical" efuse offset - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : offset - * @pValue : 1 byte efuse value - * @HALMAC_EFUSE_BANK : efuse bank - * Author : Soar - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_read_efuse_bt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - OUT u8 *pValue, - IN HALMAC_EFUSE_BANK halmac_efuse_bank -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_efuse_bt_88xx ==========>\n"); - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); - return HALMAC_RET_ERROR_STATE; - } - - if (halmac_offset >= pHalmac_adapter->hw_config_info.efuse_size) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n"); - return HALMAC_RET_EFUSE_SIZE_INCORRECT; - } - - if ((halmac_efuse_bank > HALMAC_EFUSE_BANK_MAX) || (halmac_efuse_bank == HALMAC_EFUSE_BANK_WIFI)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Undefined BT bank\n"); - return HALMAC_RET_EFUSE_BANK_INCORRECT; - } - - status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, halmac_efuse_bank); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); - return status; - } - - status = halmac_func_read_efuse_88xx(pHalmac_adapter, halmac_offset, 1, pValue); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_read_efuse error = %x\n", status); - return status; - } - - if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_efuse_bt_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_efuse_auto_check_88xx() - check efuse after writing it - * @pHalmac_adapter : the adapter of halmac - * @enable : 1, enable efuse auto check. others, disable - * Author : Soar - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_efuse_auto_check_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_efuse_auto_check_88xx ==========> function enable = %d\n", enable); - - pHalmac_adapter->efuse_auto_check_en = enable; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_efuse_auto_check_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_get_efuse_available_size_88xx() - get efuse available size - * @pHalmac_adapter : the adapter of halmac - * @halmac_size : physical efuse available size - * Author : Soar - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_get_efuse_available_size_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u32 *halmac_size -) -{ - HALMAC_RET_STATUS status; - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_available_size_88xx ==========>\n"); - - status = halmac_dump_logical_efuse_map_88xx(pHalmac_adapter, HALMAC_EFUSE_R_DRV); - - if (status != HALMAC_RET_SUCCESS) - return status; - - *halmac_size = pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - pHalmac_adapter->efuse_end; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_available_size_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_get_efuse_size_88xx() - get "physical" efuse size - * @pHalmac_adapter : the adapter of halmac - * @halmac_size : physical efuse size - * Author : Ivan Lin/KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_get_efuse_size_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u32 *halmac_size -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_size_88xx ==========>\n"); - - *halmac_size = pHalmac_adapter->hw_config_info.efuse_size; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_size_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_get_logical_efuse_size_88xx() - get "logical" efuse size - * @pHalmac_adapter : the adapter of halmac - * @halmac_size : logical efuse size - * Author : Ivan Lin/KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_get_logical_efuse_size_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u32 *halmac_size -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_logical_efuse_size_88xx ==========>\n"); - - *halmac_size = pHalmac_adapter->hw_config_info.eeprom_size; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_logical_efuse_size_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_dump_logical_efuse_map_88xx() - dump "logical" efuse map - * @pHalmac_adapter : the adapter of halmac - * @cfg : dump efuse method - * Author : Soar - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_dump_logical_efuse_map_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_EFUSE_READ_CFG cfg -) -{ - u8 *pEeprom_map = NULL; - u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_logical_efuse_map_88xx ==========>cfg = %d\n", cfg); - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); - return HALMAC_RET_ERROR_STATE; - } - - if (pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_WARN, "[WARN]Dump logical efuse in suspend mode\n"); - - *pProcess_status = HALMAC_CMD_PROCESS_IDLE; - pHalmac_adapter->event_trigger.logical_efuse_map = 1; - - status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); - return status; - } - - status = halmac_dump_efuse_88xx(pHalmac_adapter, cfg); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_eeprom_parser_88xx error = %x\n", status); - return status; - } - - if (pHalmac_adapter->hal_efuse_map_valid == _TRUE) { - *pProcess_status = HALMAC_CMD_PROCESS_DONE; - - pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); - if (pEeprom_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); - - if (halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map) != HALMAC_RET_SUCCESS) { - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - return HALMAC_RET_EEPROM_PARSING_FAIL; - } - - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, *pProcess_status, pEeprom_map, eeprom_size); - pHalmac_adapter->event_trigger.logical_efuse_map = 0; - - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - } - - if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_logical_efuse_map_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_read_logical_efuse_88xx() - read logical efuse map 1 byte - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : offset - * @pValue : 1 byte efuse value - * Author : Soar - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_read_logical_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - OUT u8 *pValue -) -{ - u8 *pEeprom_map = NULL; - u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_logical_efuse_88xx ==========>\n"); - - if (halmac_offset >= eeprom_size) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n"); - return HALMAC_RET_EFUSE_SIZE_INCORRECT; - } - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); - return HALMAC_RET_BUSY_STATE; - } - if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); - return HALMAC_RET_ERROR_STATE; - } - - status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); - return status; - } - - pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); - if (pEeprom_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); - - status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_logical_efuse_map error = %x\n", status); - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - return status; - } - - *pValue = *(pEeprom_map + halmac_offset); - - if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) { - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - return HALMAC_RET_ERROR_STATE; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_logical_efuse_88xx <==========\n"); - - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_write_logical_efuse_88xx() - write "logical" efuse offset - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : offset - * @halmac_value : value - * Author : Soar - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_write_logical_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u8 halmac_value -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_logical_efuse_88xx ==========>\n"); - - if (halmac_offset >= pHalmac_adapter->hw_config_info.eeprom_size) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n"); - return HALMAC_RET_EFUSE_SIZE_INCORRECT; - } - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); - return HALMAC_RET_ERROR_STATE; - } - - status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); - return status; - } - - status = halmac_func_write_logical_efuse_88xx(pHalmac_adapter, halmac_offset, halmac_value); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_write_logical_efuse error = %x\n", status); - return status; - } - - if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_logical_efuse_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_pg_efuse_by_map_88xx() - pg logical efuse by map - * @pHalmac_adapter : the adapter of halmac - * @pPg_efuse_info : efuse map information - * @cfg : dump efuse method - * Author : Soar - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_pg_efuse_by_map_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, - IN HALMAC_EFUSE_READ_CFG cfg -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_pg_efuse_by_map_88xx ==========>\n"); - - if (pPg_efuse_info->efuse_map_size != pHalmac_adapter->hw_config_info.eeprom_size) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map_size is incorrect, should be %d bytes\n", pHalmac_adapter->hw_config_info.eeprom_size); - return HALMAC_RET_EFUSE_SIZE_INCORRECT; - } - - if ((pPg_efuse_info->efuse_map_size & 0xF) > 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map_size should be multiple of 16\n"); - return HALMAC_RET_EFUSE_SIZE_INCORRECT; - } - - if (pPg_efuse_info->efuse_mask_size != pPg_efuse_info->efuse_map_size >> 4) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_mask_size is incorrect, should be %d bytes\n", pPg_efuse_info->efuse_map_size >> 4); - return HALMAC_RET_EFUSE_SIZE_INCORRECT; - } - - if (pPg_efuse_info->pEfuse_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map is NULL\n"); - return HALMAC_RET_NULL_POINTER; - } - - if (pPg_efuse_info->pEfuse_mask == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_mask is NULL\n"); - return HALMAC_RET_NULL_POINTER; - } - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - if (halmac_query_efuse_curr_state_88xx(pHalmac_adapter) != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); - return HALMAC_RET_ERROR_STATE; - } - - status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); - return status; - } - - status = halmac_func_pg_efuse_by_map_88xx(pHalmac_adapter, pPg_efuse_info, cfg); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_pg_efuse_by_map error = %x\n", status); - return status; - } - - if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_pg_efuse_by_map_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_get_c2h_info_88xx() - process halmac C2H packet - * @pHalmac_adapter : the adapter of halmac - * @halmac_buf : RX Packet pointer - * @halmac_size : RX Packet size - * Author : KaiYuan Chang/Ivan Lin - * - * Used to process c2h packet info from RX path. After receiving the packet, - * user need to call this api and pass the packet pointer. - * - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_get_c2h_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *halmac_buf, - IN u32 halmac_size -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_c2h_info_88xx ==========>\n"); */ - - /* Check if it is C2H packet */ - if (GET_RX_DESC_C2H(halmac_buf) == _TRUE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H packet, start parsing!\n"); - - status = halmac_parse_c2h_packet_88xx(pHalmac_adapter, halmac_buf, halmac_size); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_parse_c2h_packet_88xx error = %x\n", status); - return status; - } - } - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_c2h_info_88xx <==========\n"); */ - - return HALMAC_RET_SUCCESS; -} - -/** - * (debug API)halmac_h2c_lb_88xx() - send h2c loopback packet - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_h2c_lb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_h2c_lb_88xx ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_h2c_lb_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_debug_88xx() - dump information for debugging - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_debug_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u8 temp8 = 0; - u32 i = 0, temp32 = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug_88xx ==========>\n"); - - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { - /* Dump CCCR, it needs new platform api */ - - /*Dump SDIO Local Register, use CMD52*/ - for (i = 0x10250000; i < 0x102500ff; i++) { - temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: sdio[%x]=%x\n", i, temp8); - } - - /*Dump MAC Register*/ - for (i = 0x0000; i < 0x17ff; i++) { - temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8); - } - - /*Check RX Fifo status*/ - i = REG_RXFF_PTR_V1; - temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8); - i = REG_RXFF_WTR_V1; - temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8); - i = REG_RXFF_PTR_V1; - temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8); - i = REG_RXFF_WTR_V1; - temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8); - } else { - /*Dump MAC Register*/ - for (i = 0x0000; i < 0x17fc; i += 4) { - temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32); - } - - /*Check RX Fifo status*/ - i = REG_RXFF_PTR_V1; - temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32); - i = REG_RXFF_WTR_V1; - temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32); - i = REG_RXFF_PTR_V1; - temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32); - i = REG_RXFF_WTR_V1; - temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32); - } - - /* TODO: Add check register code, including MAC CLK, CPU CLK */ - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_parameter_88xx() - config parameter by FW - * @pHalmac_adapter : the adapter of halmac - * @para_info : cmd id, content - * @full_fifo : parameter information - * - * If msk_en = _TRUE, the format of array is {reg_info, mask, value}. - * If msk_en =_FAUSE, the format of array is {reg_info, value} - * The format of reg_info is - * reg_info[31]=rf_reg, 0: MAC_BB reg, 1: RF reg - * reg_info[27:24]=rf_path, 0: path_A, 1: path_B - * if rf_reg=0(MAC_BB reg), rf_path is meaningless. - * ref_info[15:0]=offset - * - * Example: msk_en = _FALSE - * {0x8100000a, 0x00001122} - * =>Set RF register, path_B, offset 0xA to 0x00001122 - * {0x00000824, 0x11224433} - * =>Set MAC_BB register, offset 0x800 to 0x11224433 - * - * Note : full fifo mode only for init flow - * - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_parameter_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PHY_PARAMETER_INFO para_info, - IN u8 full_fifo -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.cfg_para_state_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - if (pHalmac_adapter->fw_version.h2c_version < 4) - return HALMAC_RET_FW_NO_SUPPORT; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_parameter_88xx ==========>\n"); */ - - if (pHalmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_cfg_parameter_88xx Fail due to DLFW NONE!!\n"); - return HALMAC_RET_DLFW_FAIL; - } - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(cfg para)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - if ((halmac_query_cfg_para_curr_state_88xx(pHalmac_adapter) != HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) && - (halmac_query_cfg_para_curr_state_88xx(pHalmac_adapter) != HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(cfg para)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - *pProcess_status = HALMAC_CMD_PROCESS_IDLE; - - ret_status = halmac_send_h2c_phy_parameter_88xx(pHalmac_adapter, para_info, full_fifo); - - if (ret_status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_phy_parameter_88xx Fail!! = %x\n", ret_status); - return ret_status; - } - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_parameter_88xx <==========\n"); */ - - return ret_status; -} - -/** - * halmac_update_packet_88xx() - send specific packet to FW - * @pHalmac_adapter : the adapter of halmac - * @pkt_id : packet id, to know the purpose of this packet - * @pkt : packet - * @pkt_size : packet size - * - * Note : TX_DESC is not included in the pkt - * - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_update_packet_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_PACKET_ID pkt_id, - IN u8 *pkt, - IN u32 pkt_size -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.update_packet_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - if (pHalmac_adapter->fw_version.h2c_version < 4) - return HALMAC_RET_FW_NO_SUPPORT; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_packet_88xx ==========>\n"); - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(update_packet)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - *pProcess_status = HALMAC_CMD_PROCESS_SENDING; - - status = halmac_send_h2c_update_packet_88xx(pHalmac_adapter, pkt_id, pkt, pkt_size); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_packet_88xx packet = %x, fail = %x!!\n", pkt_id, status); - return status; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_packet_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_bcn_ie_filter_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_BCN_IE_INFO pBcn_ie_info -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - if (pHalmac_adapter->fw_version.h2c_version < 4) - return HALMAC_RET_FW_NO_SUPPORT; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_bcn_ie_filter_88xx ==========>\n"); - - status = halmac_send_h2c_update_bcn_parse_info_88xx(pHalmac_adapter, pBcn_ie_info); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_bcn_parse_info_88xx fail = %x\n", status); - return status; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_bcn_ie_filter_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_update_datapack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DATA_TYPE halmac_data_type, - IN PHALMAC_PHY_PARAMETER_INFO para_info -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - if (pHalmac_adapter->fw_version.h2c_version < 4) - return HALMAC_RET_FW_NO_SUPPORT; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_update_datapack_88xx ==========>\n"); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_update_datapack_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_run_datapack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DATA_TYPE halmac_data_type -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - if (pHalmac_adapter->fw_version.h2c_version < 4) - return HALMAC_RET_FW_NO_SUPPORT; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_run_datapack_88xx ==========>\n"); - - ret_status = halmac_send_h2c_run_datapack_88xx(pHalmac_adapter, halmac_data_type); - - if (ret_status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_run_datapack_88xx Fail, datatype = %x, status = %x!!\n", halmac_data_type, ret_status); - return ret_status; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_datapack_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_drv_info_88xx() - config driver info - * @pHalmac_adapter : the adapter of halmac - * @halmac_drv_info : driver information selection - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_drv_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DRV_INFO halmac_drv_info -) -{ - u8 drv_info_size = 0; - u8 phy_status_en = 0; - u8 sniffer_en = 0; - u8 plcp_hdr_en = 0; - u32 value32; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_drv_info_88xx ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_drv_info = %d\n", halmac_drv_info); - - switch (halmac_drv_info) { - case HALMAC_DRV_INFO_NONE: - drv_info_size = 0; - phy_status_en = 0; - sniffer_en = 0; - plcp_hdr_en = 0; - break; - case HALMAC_DRV_INFO_PHY_STATUS: - drv_info_size = 4; - phy_status_en = 1; - sniffer_en = 0; - plcp_hdr_en = 0; - break; - case HALMAC_DRV_INFO_PHY_SNIFFER: - drv_info_size = 5; /* phy status 4byte, sniffer info 1byte */ - phy_status_en = 1; - sniffer_en = 1; - plcp_hdr_en = 0; - break; - case HALMAC_DRV_INFO_PHY_PLCP: - drv_info_size = 6; /* phy status 4byte, plcp header 2byte */ - phy_status_en = 1; - sniffer_en = 0; - plcp_hdr_en = 1; - break; - default: - status = HALMAC_RET_SW_CASE_NOT_SUPPORT; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_drv_info_88xx error = %x\n", status); - return status; - } - - if (pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode != HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) - drv_info_size = HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX >> 3; - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_DRVINFO_SZ, drv_info_size); - - pHalmac_adapter->drv_info_size = drv_info_size; - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_RCR); - value32 = (value32 & (~BIT_APP_PHYSTS)); - if (phy_status_en == 1) - value32 = value32 | BIT_APP_PHYSTS; - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RCR, value32); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4); - value32 = (value32 & (~(BIT(8) | BIT(9)))); - if (sniffer_en == 1) - value32 = value32 | BIT(9); - if (plcp_hdr_en == 1) - value32 = value32 | BIT(8); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4, value32); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_info_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_send_bt_coex_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pBt_buf, - IN u32 bt_size, - IN u8 ack -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_88xx ==========>\n"); - - ret_status = halmac_send_bt_coex_cmd_88xx(pHalmac_adapter, pBt_buf, bt_size, ack); - - if (ret_status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_bt_coex_cmd_88xx Fail = %x!!\n", ret_status); - return ret_status; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * (debug API)halmac_verify_platform_api_88xx() - verify platform api - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_verify_platform_api_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_verify_platform_api_88xx ==========>\n"); - - ret_status = halmac_verify_io_88xx(pHalmac_adapter); - - if (ret_status != HALMAC_RET_SUCCESS) - return ret_status; - - if (pHalmac_adapter->txff_allocation.la_mode != HALMAC_LA_MODE_FULL) - ret_status = halmac_verify_send_rsvd_page_88xx(pHalmac_adapter); - - if (ret_status != HALMAC_RET_SUCCESS) - return ret_status; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_verify_platform_api_88xx <==========\n"); - - return ret_status; -} - -HALMAC_RET_STATUS -halmac_send_original_h2c_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *original_h2c, - IN u16 *seq, - IN u8 ack -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c_88xx ==========>\n"); - - status = halmac_func_send_original_h2c_88xx(pHalmac_adapter, original_h2c, seq, ack); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_original_h2c FAIL = %x!!\n", status); - return status; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_timer_2s_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_timer_2s_88xx ==========>\n"); - - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_timer_2s_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_fill_txdesc_check_sum_88xx() - fill in tx desc check sum - * @pHalmac_adapter : the adapter of halmac - * @pCur_desc : tx desc packet - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_fill_txdesc_check_sum_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - INOUT u8 *pCur_desc -) -{ - u16 chk_result = 0; - u16 *pData = (u16 *)NULL; - u32 i; - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - if (pCur_desc == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_fill_txdesc_check_sum_88xx NULL PTR"); - return HALMAC_RET_NULL_POINTER; - } - - SET_TX_DESC_TXDESC_CHECKSUM(pCur_desc, 0x0000); - - pData = (u16 *)(pCur_desc); - - /* HW clculates only 32byte */ - for (i = 0; i < 8; i++) - chk_result ^= (*(pData + 2 * i) ^ *(pData + (2 * i + 1))); - - /* *(pData + 2 * i) & *(pData + (2 * i + 1) have endain issue*/ - /* Process eniadn issue after checksum calculation */ - chk_result = rtk_le16_to_cpu(chk_result); - - SET_TX_DESC_TXDESC_CHECKSUM(pCur_desc, chk_result); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_dump_fifo_88xx() - dump fifo data - * @pHalmac_adapter : the adapter of halmac - * @halmac_fifo_sel : FIFO selection - * @halmac_start_addr : start address of selected FIFO - * @halmac_fifo_dump_size : dump size of selected FIFO - * @pFifo_map : FIFO data - * - * Note : before dump fifo, user need to call halmac_get_fifo_size to - * get fifo size. Then input this size to halmac_dump_fifo. - * - * Author : Ivan Lin/KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_dump_fifo_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HAL_FIFO_SEL halmac_fifo_sel, - IN u32 halmac_start_addr, - IN u32 halmac_fifo_dump_size, - OUT u8 *pFifo_map -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_fifo_88xx ==========>\n"); - - if (halmac_fifo_sel == HAL_FIFO_SEL_TX && (halmac_start_addr + halmac_fifo_dump_size) > pHalmac_adapter->hw_config_info.tx_fifo_size) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TX fifo dump size is too large\n"); - return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; - } - - if (halmac_fifo_sel == HAL_FIFO_SEL_RX && (halmac_start_addr + halmac_fifo_dump_size) > pHalmac_adapter->hw_config_info.rx_fifo_size) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "RX fifo dump size is too large\n"); - return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; - } - - if ((halmac_fifo_dump_size & (4 - 1)) != 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_fifo_dump_size shall 4byte align\n"); - return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; - } - - if (pFifo_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "pFifo_map address is NULL\n"); - return HALMAC_RET_NULL_POINTER; - } - - status = halmac_buffer_read_88xx(pHalmac_adapter, halmac_start_addr, halmac_fifo_dump_size, halmac_fifo_sel, pFifo_map); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buffer_read_88xx error = %x\n", status); - return status; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_fifo_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_get_fifo_size_88xx() - get fifo size - * @pHalmac_adapter : the adapter of halmac - * @halmac_fifo_sel : FIFO selection - * Author : Ivan Lin/KaiYuan Chang - * Return : u32 - * More details of status code can be found in prototype document - */ -u32 -halmac_get_fifo_size_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HAL_FIFO_SEL halmac_fifo_sel -) -{ - u32 fifo_size = 0; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fifo_sel == HAL_FIFO_SEL_TX) - fifo_size = pHalmac_adapter->hw_config_info.tx_fifo_size; - else if (halmac_fifo_sel == HAL_FIFO_SEL_RX) - fifo_size = pHalmac_adapter->hw_config_info.rx_fifo_size; - else if (halmac_fifo_sel == HAL_FIFO_SEL_RSVD_PAGE) - fifo_size = ((pHalmac_adapter->hw_config_info.tx_fifo_size >> HALMAC_TX_PAGE_SIZE_2_POWER_88XX) - - pHalmac_adapter->txff_allocation.rsvd_pg_bndy) << HALMAC_TX_PAGE_SIZE_2_POWER_88XX; - else if (halmac_fifo_sel == HAL_FIFO_SEL_REPORT) - fifo_size = 65536; - else if (halmac_fifo_sel == HAL_FIFO_SEL_LLT) - fifo_size = 65536; - else if (halmac_fifo_sel == HAL_FIFO_SEL_RXBUF_FW) - fifo_size = HALMAC_RX_BUF_FW_88XX; - - return fifo_size; -} - -/** - * halmac_cfg_txbf_88xx() - enable/disable specific user's txbf - * @pHalmac_adapter : the adapter of halmac - * @userid : su bfee userid = 0 or 1 to apply TXBF - * @bw : the sounding bandwidth - * @txbf_en : 0: disable TXBF, 1: enable TXBF - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_txbf_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 userid, - IN HALMAC_BW bw, - IN u8 txbf_en -) -{ - u16 temp42C = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (txbf_en) { - switch (bw) { - case HALMAC_BW_80: - temp42C |= BIT_R_TXBF0_80M; - case HALMAC_BW_40: - temp42C |= BIT_R_TXBF0_40M; - case HALMAC_BW_20: - temp42C |= BIT_R_TXBF0_20M; - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_txbf_88xx invalid TXBF BW setting 0x%x of userid %d\n", bw, userid); - return HALMAC_RET_INVALID_SOUNDING_SETTING; - } - } - - switch (userid) { - case 0: - temp42C |= HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, temp42C); - break; - case 1: - temp42C |= HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, temp42C); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_txbf_88xx invalid userid %d\n", userid); - return HALMAC_RET_INVALID_SOUNDING_SETTING; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_txbf_88xx, txbf_en = %x <==========\n", txbf_en); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_mumimo_88xx() -config mumimo - * @pHalmac_adapter : the adapter of halmac - * @pCfgmu : parameters to configure MU PPDU Tx/Rx - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_mumimo_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_CFG_MUMIMO_PARA pCfgmu -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - u8 i, idx, id0, id1, gid, mu_tab_sel; - u8 mu_tab_valid = 0; - u32 gid_valid[6] = {0}; - u8 temp14C0 = 0; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (pCfgmu->role == HAL_BFEE) { - /*config MU BFEE*/ - temp14C0 = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~BIT_MASK_R_MU_TABLE_VALID; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, (temp14C0 | BIT(0) | BIT(1)) & ~(BIT(7))); /*enable MU table 0 and 1, disable MU TX*/ - - /*config GID valid table and user position table*/ - mu_tab_sel = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL + 1) & ~(BIT(0) | BIT(1) | BIT(2)); - for (i = 0; i < 2; i++) { - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL + 1, mu_tab_sel | i); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, pCfgmu->given_gid_tab[i]); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO, pCfgmu->given_user_pos[i * 2]); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO + 4, pCfgmu->given_user_pos[i * 2 + 1]); - } - } else { - /*config MU BFER*/ - if (pCfgmu->mu_tx_en == _FALSE) { - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(7))); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_mumimo_88xx disable mu tx <==========\n"); - return HALMAC_RET_SUCCESS; - } - - /*Transform BB grouping bitmap[14:0] to MAC GID_valid table*/ - for (idx = 0; idx < 15; idx++) { - if (idx < 5) { - /*grouping_bitmap bit0~4, MU_STA0 with MUSTA1~5*/ - id0 = 0; - id1 = (u8)(idx + 1); - } else if (idx < 9) { - /*grouping_bitmap bit5~8, MU_STA1 with MUSTA2~5*/ - id0 = 1; - id1 = (u8)(idx - 3); - } else if (idx < 12) { - /*grouping_bitmap bit9~11, MU_STA2 with MUSTA3~5*/ - id0 = 2; - id1 = (u8)(idx - 6); - } else if (idx < 14) { - /*grouping_bitmap bit12~13, MU_STA3 with MUSTA4~5*/ - id0 = 3; - id1 = (u8)(idx - 8); - } else { - /*grouping_bitmap bit14, MU_STA4 with MUSTA5*/ - id0 = 4; - id1 = (u8)(idx - 9); - } - if (pCfgmu->grouping_bitmap & BIT(idx)) { - /*Pair 1*/ - gid = (idx << 1) + 1; - gid_valid[id0] |= (BIT(gid)); - gid_valid[id1] |= (BIT(gid)); - /*Pair 2*/ - gid += 1; - gid_valid[id0] |= (BIT(gid)); - gid_valid[id1] |= (BIT(gid)); - } else { - /*Pair 1*/ - gid = (idx << 1) + 1; - gid_valid[id0] &= ~(BIT(gid)); - gid_valid[id1] &= ~(BIT(gid)); - /*Pair 2*/ - gid += 1; - gid_valid[id0] &= ~(BIT(gid)); - gid_valid[id1] &= ~(BIT(gid)); - } - } - - /*set MU STA GID valid TABLE*/ - mu_tab_sel = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL + 1) & ~(BIT(0) | BIT(1) | BIT(2)); - for (idx = 0; idx < 6; idx++) { - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL + 1, idx | mu_tab_sel); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, gid_valid[idx]); - } - - /*To validate the sounding successful MU STA and enable MU TX*/ - for (i = 0; i < 6; i++) { - if (pCfgmu->sounding_sts[i] == _TRUE) - mu_tab_valid |= BIT(i); - } - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, mu_tab_valid | BIT(7)); - } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_mumimo_88xx <==========\n"); - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_sounding_88xx() - configure general sounding - * @pHalmac_adapter : the adapter of halmac - * @role : driver's role, BFer or BFee - * @datarate : set ndpa tx rate if driver is BFer, or set csi response rate if driver is BFee - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_sounding_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_SND_ROLE role, - IN HALMAC_DATA_RATE datarate -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - switch (role) { - case HAL_BFER: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TXBF_CTRL, HALMAC_REG_READ_32(pHalmac_adapter, REG_TXBF_CTRL) | BIT_R_ENABLE_NDPA - | BIT_USE_NDPA_PARAMETER | BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_NDPA_RATE, datarate); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_NDPA_OPT_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_NDPA_OPT_CTRL) & (~(BIT(0) | BIT(1)))); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 1, 0x2 | BIT(7)); /*service file length 2 bytes; fix non-STA1 csi start offset */ - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 2, 0x2); - break; - case HAL_BFEE: - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL, 0xDB); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 3, 0x24); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BBPSF_CTRL + 3, HALMAC_OFDM54 | BIT(6)); //use ndpa rx rate to decide csi rate - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, HALMAC_REG_READ_16(pHalmac_adapter, REG_RRSR) | BIT(datarate)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXFLTMAP1, HALMAC_REG_READ_8(pHalmac_adapter, REG_RXFLTMAP1) & (~(BIT(4)))); /*RXFF do not accept BF Rpt Poll, avoid CSI crc error*/ - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXFLTMAP4, HALMAC_REG_READ_8(pHalmac_adapter, REG_RXFLTMAP4) & (~(BIT(4)))); /*FWFF do not accept BF Rpt Poll, avoid CSI crc error*/ - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_sounding_88xx invalid role\n"); - return HALMAC_RET_INVALID_SOUNDING_SETTING; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_sounding_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_del_sounding_88xx() - reset general sounding - * @pHalmac_adapter : the adapter of halmac - * @role : driver's role, BFer or BFee - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_del_sounding_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_SND_ROLE role -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - switch (role) { - case HAL_BFER: - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXBF_CTRL + 3, 0); - break; - case HAL_BFEE: - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL, 0); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_del_sounding_88xx invalid role\n"); - return HALMAC_RET_INVALID_SOUNDING_SETTING; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_del_sounding_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_su_bfee_entry_init_88xx() - config SU beamformee's registers - * @pHalmac_adapter : the adapter of halmac - * @userid : SU bfee userid = 0 or 1 to be added - * @paid : partial AID of this bfee - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_su_bfee_entry_init_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 userid, - IN u16 paid -) -{ - u16 temp42C = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - switch (userid) { - case 0: - temp42C = HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, temp42C | paid); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL, paid); - break; - case 1: - temp42C = HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, temp42C | paid); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 2, paid | BIT(9)); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfee_entry_init_88xx invalid userid %d\n", userid); - return HALMAC_RET_INVALID_SOUNDING_SETTING; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfee_entry_init_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_su_bfee_entry_init_88xx() - config SU beamformer's registers - * @pHalmac_adapter : the adapter of halmac - * @pSu_bfer_init : parameters to configure SU BFER entry - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_su_bfer_entry_init_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init -) -{ - u16 mac_address_H; - u32 mac_address_L; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - /* mac_address_L = bfer_address.Address_L_H.Address_Low; */ - /* mac_address_H = bfer_address.Address_L_H.Address_High; */ - - mac_address_L = rtk_le32_to_cpu(pSu_bfer_init->bfer_address.Address_L_H.Address_Low); - mac_address_H = rtk_le16_to_cpu(pSu_bfer_init->bfer_address.Address_L_H.Address_High); - - switch (pSu_bfer_init->userid) { - case 0: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, mac_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, mac_address_H); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 6, pSu_bfer_init->paid); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TX_CSI_RPT_PARAM_BW20, pSu_bfer_init->csi_para); - break; - case 1: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO, mac_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO + 4, mac_address_H); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO + 6, pSu_bfer_init->paid); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TX_CSI_RPT_PARAM_BW20 + 2, pSu_bfer_init->csi_para); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfer_entry_init_88xx invalid userid %d\n", pSu_bfer_init->userid); - return HALMAC_RET_INVALID_SOUNDING_SETTING; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfer_entry_init_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_mu_bfee_entry_init_88xx() - config MU beamformee's registers - * @pHalmac_adapter : the adapter of halmac - * @pMu_bfee_init : parameters to configure MU BFEE entry - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_mu_bfee_entry_init_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init -) -{ - u16 temp168X = 0, temp14C0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - temp168X |= pMu_bfee_init->paid | BIT(9); - HALMAC_REG_WRITE_16(pHalmac_adapter, (0x1680 + pMu_bfee_init->userid * 2), temp168X); - - temp14C0 = HALMAC_REG_READ_16(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(8) | BIT(9) | BIT(10)); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MU_TX_CTL, temp14C0 | ((pMu_bfee_init->userid - 2) << 8)); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, 0); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO, pMu_bfee_init->user_position_l); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO + 4, pMu_bfee_init->user_position_h); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfee_entry_init_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_mu_bfer_entry_init_88xx() - config MU beamformer's registers - * @pHalmac_adapter : the adapter of halmac - * @pMu_bfer_init : parameters to configure MU BFER entry - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_mu_bfer_entry_init_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init -) -{ - u16 temp1680 = 0; - u16 mac_address_H; - u32 mac_address_L; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - /* mac_address_L = pHalmac_adapter->snd_info.bfer_address.Address_L_H.Address_Low; */ - /* mac_address_H = pHalmac_adapter->snd_info.bfer_address.Address_L_H.Address_High; */ - - mac_address_L = rtk_le32_to_cpu(pMu_bfer_init->bfer_address.Address_L_H.Address_Low); - mac_address_H = rtk_le16_to_cpu(pMu_bfer_init->bfer_address.Address_L_H.Address_High); - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, mac_address_L); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, mac_address_H); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 6, pMu_bfer_init->paid); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TX_CSI_RPT_PARAM_BW20, pMu_bfer_init->csi_para); - - temp1680 = HALMAC_REG_READ_16(pHalmac_adapter, 0x1680) & 0xC000; - temp1680 |= pMu_bfer_init->my_aid | (pMu_bfer_init->csi_length_sel << 12); - HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680, temp1680); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfer_entry_init_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_su_bfee_entry_del_88xx() - reset SU beamformee's registers - * @pHalmac_adapter : the adapter of halmac - * @userid : the SU BFee userid to be deleted - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_su_bfee_entry_del_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 userid -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - switch (userid) { - case 0: - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & - ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M)); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL, 0); - break; - case 1: - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & - ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M)); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 2, 0); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfee_entry_del_88xx invalid userid %d\n", userid); - return HALMAC_RET_INVALID_SOUNDING_SETTING; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfee_entry_del_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_su_bfee_entry_del_88xx() - reset SU beamformer's registers - * @pHalmac_adapter : the adapter of halmac - * @userid : the SU BFer userid to be deleted - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_su_bfer_entry_del_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 userid -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - switch (userid) { - case 0: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, 0); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, 0); - break; - case 1: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO, 0); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO + 4, 0); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfer_entry_del_88xx invalid userid %d\n", userid); - return HALMAC_RET_INVALID_SOUNDING_SETTING; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfer_entry_del_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_mu_bfee_entry_del_88xx() - reset MU beamformee's registers - * @pHalmac_adapter : the adapter of halmac - * @userid : the MU STA userid to be deleted - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_mu_bfee_entry_del_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 userid -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680 + userid * 2, 0); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(userid - 2))); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfee_entry_del_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_mu_bfer_entry_del_88xx() -reset MU beamformer's registers - * @pHalmac_adapter : the adapter of halmac - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_mu_bfer_entry_del_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, 0); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, 0); - HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680, 0); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, 0); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfer_entry_del_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_add_ch_info_88xx() -add channel information - * @pHalmac_adapter : the adapter of halmac - * @pCh_info : channel information - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_add_ch_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_CH_INFO pCh_info -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_CS_INFO pCh_sw_info; - HALMAC_SCAN_CMD_CONSTRUCT_STATE state_scan; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pCh_sw_info = &pHalmac_adapter->ch_sw_info; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_add_ch_info_88xx ==========>\n"); - - if (pHalmac_adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_add_ch_info_88xx: gen_info is not send to FW!!!!\n"); - return HALMAC_RET_GEN_INFO_NOT_SENT; - } - - state_scan = halmac_query_scan_curr_state_88xx(pHalmac_adapter); - if ((state_scan != HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) && (state_scan != HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "[WARN]Scan machine fail(add ch info)...\n"); - return HALMAC_RET_ERROR_STATE; - } - - if (pCh_sw_info->ch_info_buf == NULL) { - pCh_sw_info->ch_info_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, HALMAC_EXTRA_INFO_BUFF_SIZE_88XX); - if (pCh_sw_info->ch_info_buf == NULL) - return HALMAC_RET_NULL_POINTER; - pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf; - pCh_sw_info->buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX; - pCh_sw_info->avai_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX; - pCh_sw_info->total_size = 0; - pCh_sw_info->extra_info_en = 0; - pCh_sw_info->ch_num = 0; - } - - if (pCh_sw_info->extra_info_en == 1) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_add_ch_info_88xx: construct sequence wrong!!\n"); - return HALMAC_RET_CH_SW_SEQ_WRONG; - } - - if (pCh_sw_info->avai_buf_size < 4) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_add_ch_info_88xx: no available buffer!!\n"); - return HALMAC_RET_CH_SW_NO_BUF; - } - - if (halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - CHANNEL_INFO_SET_CHANNEL(pCh_sw_info->ch_info_buf_w, pCh_info->channel); - CHANNEL_INFO_SET_PRI_CH_IDX(pCh_sw_info->ch_info_buf_w, pCh_info->pri_ch_idx); - CHANNEL_INFO_SET_BANDWIDTH(pCh_sw_info->ch_info_buf_w, pCh_info->bw); - CHANNEL_INFO_SET_TIMEOUT(pCh_sw_info->ch_info_buf_w, pCh_info->timeout); - CHANNEL_INFO_SET_ACTION_ID(pCh_sw_info->ch_info_buf_w, pCh_info->action_id); - CHANNEL_INFO_SET_CH_EXTRA_INFO(pCh_sw_info->ch_info_buf_w, pCh_info->extra_info); - - pCh_sw_info->avai_buf_size = pCh_sw_info->avai_buf_size - 4; - pCh_sw_info->total_size = pCh_sw_info->total_size + 4; - pCh_sw_info->ch_num++; - pCh_sw_info->extra_info_en = pCh_info->extra_info; - pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf_w + 4; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_add_ch_info_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_add_extra_ch_info_88xx() -add extra channel information - * @pHalmac_adapter : the adapter of halmac - * @pCh_extra_info : extra channel information - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_add_extra_ch_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_CH_EXTRA_INFO pCh_extra_info -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_CS_INFO pCh_sw_info; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pCh_sw_info = &pHalmac_adapter->ch_sw_info; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_extra_ch_info_88xx ==========>\n"); - - if (pCh_sw_info->ch_info_buf == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: NULL==pCh_sw_info->ch_info_buf!!\n"); - return HALMAC_RET_CH_SW_SEQ_WRONG; - } - - if (pCh_sw_info->extra_info_en == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: construct sequence wrong!!\n"); - return HALMAC_RET_CH_SW_SEQ_WRONG; - } - - if (pCh_sw_info->avai_buf_size < (u32)(pCh_extra_info->extra_info_size + 2)) {/* 2:ch_extra_info_id, ch_extra_info, ch_extra_info_size are totally 2Byte */ - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: no available buffer!!\n"); - return HALMAC_RET_CH_SW_NO_BUF; - } - - if (halmac_query_scan_curr_state_88xx(pHalmac_adapter) != HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Scan machine fail(add extra ch info)...\n"); - return HALMAC_RET_ERROR_STATE; - } - - if (halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_action_id); - CH_EXTRA_INFO_SET_CH_EXTRA_INFO(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_info); - CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_info_size); - PLATFORM_RTL_MEMCPY(pDriver_adapter, pCh_sw_info->ch_info_buf_w + 2, pCh_extra_info->extra_info_data, pCh_extra_info->extra_info_size); - - pCh_sw_info->avai_buf_size = pCh_sw_info->avai_buf_size - (2 + pCh_extra_info->extra_info_size); - pCh_sw_info->total_size = pCh_sw_info->total_size + (2 + pCh_extra_info->extra_info_size); - pCh_sw_info->extra_info_en = pCh_extra_info->extra_info; - pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf_w + (2 + pCh_extra_info->extra_info_size); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_extra_ch_info_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_ctrl_ch_switch_88xx() -send channel switch cmd - * @pHalmac_adapter : the adapter of halmac - * @pCs_option : channel switch config - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_ctrl_ch_switch_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_CH_SWITCH_OPTION pCs_option -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_SCAN_CMD_CONSTRUCT_STATE state_scan; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.scan_state_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - if (pHalmac_adapter->fw_version.h2c_version < 4) - return HALMAC_RET_FW_NO_SUPPORT; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx pCs_option->switch_en = %d==========>\n", pCs_option->switch_en); - - if (pCs_option->switch_en == _FALSE) - *pProcess_status = HALMAC_CMD_PROCESS_IDLE; - - if ((*pProcess_status == HALMAC_CMD_PROCESS_SENDING) || (*pProcess_status == HALMAC_CMD_PROCESS_RCVD)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(ctrl ch switch)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - state_scan = halmac_query_scan_curr_state_88xx(pHalmac_adapter); - if (pCs_option->switch_en == _TRUE) { - if (state_scan != HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx(on) invalid in state %x\n", state_scan); - return HALMAC_RET_ERROR_STATE; - } - } else { - if (state_scan != HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx(off) invalid in state %x\n", state_scan); - return HALMAC_RET_ERROR_STATE; - } - } - - status = halmac_func_ctrl_ch_switch_88xx(pHalmac_adapter, pCs_option); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_ctrl_ch_switch FAIL = %x!!\n", status); - return status; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_clear_ch_info_88xx() -clear channel information - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_clear_ch_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_clear_ch_info_88xx ==========>\n"); - - if (halmac_query_scan_curr_state_88xx(pHalmac_adapter) == HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Scan machine fail(clear ch info)...\n"); - return HALMAC_RET_ERROR_STATE; - } - - if (halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.buf_size); - pHalmac_adapter->ch_sw_info.ch_info_buf = NULL; - pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL; - pHalmac_adapter->ch_sw_info.extra_info_en = 0; - pHalmac_adapter->ch_sw_info.buf_size = 0; - pHalmac_adapter->ch_sw_info.avai_buf_size = 0; - pHalmac_adapter->ch_sw_info.total_size = 0; - pHalmac_adapter->ch_sw_info.ch_num = 0; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_clear_ch_info_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_p2pps_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_P2PPS pP2PPS -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - if (pHalmac_adapter->fw_version.h2c_version < 6) - return HALMAC_RET_FW_NO_SUPPORT; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - status = halmac_func_p2pps_88xx(pHalmac_adapter, pP2PPS); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_p2pps FAIL = %x!!\n", status); - return status; - } - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_func_p2pps_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_P2PPS pP2PPS -) -{ - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u16 h2c_seq_mum = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_p2pps !!\n"); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - P2PPS_SET_OFFLOAD_EN(pH2c_buff, pP2PPS->offload_en); - P2PPS_SET_ROLE(pH2c_buff, pP2PPS->role); - P2PPS_SET_CTWINDOW_EN(pH2c_buff, pP2PPS->ctwindow_en); - P2PPS_SET_NOA_EN(pH2c_buff, pP2PPS->noa_en); - P2PPS_SET_NOA_SEL(pH2c_buff, pP2PPS->noa_sel); - P2PPS_SET_ALLSTASLEEP(pH2c_buff, pP2PPS->all_sta_sleep); - P2PPS_SET_DISCOVERY(pH2c_buff, pP2PPS->discovery); - P2PPS_SET_P2P_PORT_ID(pH2c_buff, pP2PPS->p2p_port_id); - P2PPS_SET_P2P_GROUP(pH2c_buff, pP2PPS->p2p_group); - P2PPS_SET_P2P_MACID(pH2c_buff, pP2PPS->p2p_macid); - - P2PPS_SET_CTWINDOW_LENGTH(pH2c_buff, pP2PPS->ctwindow_length); - - P2PPS_SET_NOA_DURATION_PARA(pH2c_buff, pP2PPS->noa_duration_para); - P2PPS_SET_NOA_INTERVAL_PARA(pH2c_buff, pP2PPS->noa_interval_para); - P2PPS_SET_NOA_START_TIME_PARA(pH2c_buff, pP2PPS->noa_start_time_para); - P2PPS_SET_NOA_COUNT_PARA(pH2c_buff, pP2PPS->noa_count_para); - - h2c_header_info.sub_cmd_id = SUB_CMD_ID_P2PPS; - h2c_header_info.content_size = 24; - h2c_header_info.ack = _FALSE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _FALSE); - - if (status != HALMAC_RET_SUCCESS) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_send_h2c_p2pps_88xx Fail = %x!!\n", status); - - return status; -} - -/** - * halmac_send_general_info_88xx() -send general information to FW - * @pHalmac_adapter : the adapter of halmac - * @pGeneral_info : general information - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_send_general_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_GENERAL_INFO pGeneral_info -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - if (pHalmac_adapter->fw_version.h2c_version < 4) - return HALMAC_RET_FW_NO_SUPPORT; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info_88xx ==========>\n"); - - if (pHalmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_general_info_88xx Fail due to DLFW NONE!!\n"); - return HALMAC_RET_DLFW_FAIL; - } - - status = halmac_func_send_general_info_88xx(pHalmac_adapter, pGeneral_info); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_send_general_info error = %x\n", status); - return status; - } - - if (pHalmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_DONE) - pHalmac_adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT; - - pHalmac_adapter->gen_info_valid = _TRUE; - PLATFORM_RTL_MEMCPY(pDriver_adapter, &pHalmac_adapter->general_info, pGeneral_info, sizeof(HALMAC_GENERAL_INFO)); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_start_iqk_88xx() -trigger FW IQK - * @pHalmac_adapter : the adapter of halmac - * @pIqk_para : IQK parameter - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_start_iqk_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_IQK_PARA pIqk_para -) -{ - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u16 h2c_seq_num = 0; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.iqk_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx ==========>\n"); - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(iqk)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - *pProcess_status = HALMAC_CMD_PROCESS_SENDING; - - IQK_SET_CLEAR(pH2c_buff, pIqk_para->clear); - IQK_SET_SEGMENT_IQK(pH2c_buff, pIqk_para->segment_iqk); - - h2c_header_info.sub_cmd_id = SUB_CMD_ID_IQK; - h2c_header_info.content_size = 1; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_num); - - pHalmac_adapter->halmac_state.iqk_set.seq_num = h2c_seq_num; - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); - halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_IQK); - return status; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_ctrl_pwr_tracking_88xx() -trigger FW power tracking - * @pHalmac_adapter : the adapter of halmac - * @pPwr_tracking_opt : power tracking option - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_ctrl_pwr_tracking_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt -) -{ - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u16 h2c_seq_mum = 0; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.power_tracking_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx ==========>\n"); - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(pwr tracking)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - *pProcess_status = HALMAC_CMD_PROCESS_SENDING; - - POWER_TRACKING_SET_TYPE(pH2c_buff, pPwr_tracking_opt->type); - POWER_TRACKING_SET_BBSWING_INDEX(pH2c_buff, pPwr_tracking_opt->bbswing_index); - POWER_TRACKING_SET_ENABLE_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].enable); - POWER_TRACKING_SET_TX_PWR_INDEX_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].tx_pwr_index); - POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].pwr_tracking_offset_value); - POWER_TRACKING_SET_TSSI_VALUE_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].tssi_value); - POWER_TRACKING_SET_ENABLE_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].enable); - POWER_TRACKING_SET_TX_PWR_INDEX_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].tx_pwr_index); - POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].pwr_tracking_offset_value); - POWER_TRACKING_SET_TSSI_VALUE_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].tssi_value); - POWER_TRACKING_SET_ENABLE_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].enable); - POWER_TRACKING_SET_TX_PWR_INDEX_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].tx_pwr_index); - POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].pwr_tracking_offset_value); - POWER_TRACKING_SET_TSSI_VALUE_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].tssi_value); - POWER_TRACKING_SET_ENABLE_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].enable); - POWER_TRACKING_SET_TX_PWR_INDEX_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].tx_pwr_index); - POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].pwr_tracking_offset_value); - POWER_TRACKING_SET_TSSI_VALUE_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].tssi_value); - - h2c_header_info.sub_cmd_id = SUB_CMD_ID_POWER_TRACKING; - h2c_header_info.content_size = 20; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - - pHalmac_adapter->halmac_state.power_tracking_set.seq_num = h2c_seq_mum; - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); - halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_POWER_TRACKING); - return status; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_query_status_88xx() -query the offload feature status - * @pHalmac_adapter : the adapter of halmac - * @feature_id : feature_id - * @pProcess_status : feature_status - * @data : data buffer - * @size : data size - * - * Note : - * If user wants to know the data size, use can allocate zero - * size buffer first. If this size less than the data size, halmac - * will return HALMAC_RET_BUFFER_TOO_SMALL. User need to - * re-allocate data buffer with correct data size. - * - * Author : Ivan Lin/KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_query_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_FEATURE_ID feature_id, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_query_status_88xx ==========>\n"); */ - - if (pProcess_status == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "null pointer!!\n"); - return HALMAC_RET_NULL_POINTER; - } - - switch (feature_id) { - case HALMAC_FEATURE_CFG_PARA: - status = halmac_query_cfg_para_status_88xx(pHalmac_adapter, pProcess_status, data, size); - break; - case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE: - status = halmac_query_dump_physical_efuse_status_88xx(pHalmac_adapter, pProcess_status, data, size); - break; - case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE: - status = halmac_query_dump_logical_efuse_status_88xx(pHalmac_adapter, pProcess_status, data, size); - break; - case HALMAC_FEATURE_CHANNEL_SWITCH: - status = halmac_query_channel_switch_status_88xx(pHalmac_adapter, pProcess_status, data, size); - break; - case HALMAC_FEATURE_UPDATE_PACKET: - status = halmac_query_update_packet_status_88xx(pHalmac_adapter, pProcess_status, data, size); - break; - case HALMAC_FEATURE_IQK: - status = halmac_query_iqk_status_88xx(pHalmac_adapter, pProcess_status, data, size); - break; - case HALMAC_FEATURE_POWER_TRACKING: - status = halmac_query_power_tracking_status_88xx(pHalmac_adapter, pProcess_status, data, size); - break; - case HALMAC_FEATURE_PSD: - status = halmac_query_psd_status_88xx(pHalmac_adapter, pProcess_status, data, size); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_query_status_88xx invalid feature id %d\n", feature_id); - return HALMAC_RET_INVALID_FEATURE_ID; - } - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_query_status_88xx <==========\n"); */ - - return status; -} - -/** - * halmac_reset_feature_88xx() -reset async api cmd status - * @pHalmac_adapter : the adapter of halmac - * @feature_id : feature_id - * Author : Ivan Lin/KaiYuan Chang - * Return : HALMAC_RET_STATUS. - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_reset_feature_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_FEATURE_ID feature_id -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_STATE pState = &pHalmac_adapter->halmac_state; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_reset_feature_88xx ==========>\n"); - - switch (feature_id) { - case HALMAC_FEATURE_CFG_PARA: - pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE; - break; - case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE: - case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE: - pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE; - break; - case HALMAC_FEATURE_CHANNEL_SWITCH: - pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE; - break; - case HALMAC_FEATURE_UPDATE_PACKET: - pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE; - break; - case HALMAC_FEATURE_IQK: - pState->iqk_set.process_status = HALMAC_CMD_PROCESS_IDLE; - break; - case HALMAC_FEATURE_POWER_TRACKING: - pState->power_tracking_set.process_status = HALMAC_CMD_PROCESS_IDLE; - break; - case HALMAC_FEATURE_PSD: - pState->psd_set.process_status = HALMAC_CMD_PROCESS_IDLE; - break; - case HALMAC_FEATURE_ALL: - pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE; - pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE; - pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE; - pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->iqk_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->power_tracking_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->psd_set.process_status = HALMAC_CMD_PROCESS_IDLE; - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "[ERR]halmac_reset_feature_88xx invalid feature id %d\n", feature_id); - return HALMAC_RET_INVALID_FEATURE_ID; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_reset_feature_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_check_fw_status_88xx() -check fw status - * @pHalmac_adapter : the adapter of halmac - * @fw_status : fw status - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_check_fw_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u8 *fw_status -) -{ - u32 value32 = 0, value32_backup = 0, i = 0; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_check_fw_status_88xx ==========>\n"); - - value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG6); - - if (value32 != 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_check_fw_status REG_FW_DBG6 !=0\n"); - *fw_status = _FALSE; - return status; - } - - value32_backup = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG7); - - for (i = 0; i <= 10; i++) { - value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG7); - if (value32_backup != value32) - break; - - if (i == 10) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_check_fw_status Polling FW PC fail\n"); - *fw_status = _FALSE; - return status; - } - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_check_fw_status_88xx <==========\n"); - - return status; -} - -HALMAC_RET_STATUS -halmac_dump_fw_dmem_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - INOUT u8 *dmem, - INOUT u32 *size -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_dump_fw_dmem_88xx ==========>\n"); - - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_dump_fw_dmem_88xx <==========\n"); - - return status; -} - -/** - * halmac_cfg_max_dl_size_88xx() - config max download FW size - * @pHalmac_adapter : the adapter of halmac - * @size : max download fw size - * - * Halmac uses this setting to set max packet size for - * download FW. - * If user has not called this API, halmac use default - * setting for download FW - * Note1 : size need multiple of 2 - * Note2 : max size is 31K - * - * Author : Ivan Lin/KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_max_dl_size_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 size -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "halmac_cfg_max_dl_size_88xx ==========>\n"); - - if (size > HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "size > HALMAC_FW_CFG_MAX_DL_SIZE_MAX!\n"); - return HALMAC_RET_CFG_DLFW_SIZE_FAIL; - } - - if (0 != (size & (2 - 1))) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "size is not power of 2!\n"); - return HALMAC_RET_CFG_DLFW_SIZE_FAIL; - } - - pHalmac_adapter->max_download_size = size; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "Cfg max size is : %X\n", size); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "halmac_cfg_max_dl_size_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_psd_88xx() - trigger fw psd - * @pHalmac_adapter : the adapter of halmac - * @start_psd : start PSD - * @end_psd : end PSD - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_psd_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u16 start_psd, - IN u16 end_psd -) -{ - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u16 h2c_seq_mum = 0; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.psd_set.process_status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (halmac_fw_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_NO_DLFW; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_psd_88xx ==========>\n"); - - if (*pProcess_status == HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(psd)...\n"); - return HALMAC_RET_BUSY_STATE; - } - - if (pHalmac_adapter->halmac_state.psd_set.pData != NULL) { - PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->halmac_state.psd_set.pData, pHalmac_adapter->halmac_state.psd_set.data_size); - pHalmac_adapter->halmac_state.psd_set.pData = (u8 *)NULL; - } - - pHalmac_adapter->halmac_state.psd_set.data_size = 0; - pHalmac_adapter->halmac_state.psd_set.segment_size = 0; - - *pProcess_status = HALMAC_CMD_PROCESS_SENDING; - - PSD_SET_START_PSD(pH2c_buff, start_psd); - PSD_SET_END_PSD(pH2c_buff, end_psd); - - h2c_header_info.sub_cmd_id = SUB_CMD_ID_PSD; - h2c_header_info.content_size = 4; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); - halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_PSD); - return status; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_psd_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_la_mode_88xx() - config la mode - * @pHalmac_adapter : the adapter of halmac - * @la_mode : - * disable : no TXFF space reserved for LA debug - * partial : partial TXFF space is reserved for LA debug - * full : all TXFF space is reserved for LA debug - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_la_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_LA_MODE la_mode -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_la_mode_88xx ==========>la_mode = %d\n", la_mode); - - pHalmac_adapter->txff_allocation.la_mode = la_mode; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_la_mode_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_rx_fifo_expanding_mode_88xx() - rx fifo expanding - * @pHalmac_adapter : the adapter of halmac - * @la_mode : - * disable : normal mode - * 1 block : Rx FIFO + 1 FIFO block; Tx fifo - 1 FIFO block - * 2 block : Rx FIFO + 2 FIFO block; Tx fifo - 2 FIFO block - * 3 block : Rx FIFO + 3 FIFO block; Tx fifo - 3 FIFO block - * Author : Soar - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_rx_fifo_expanding_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_rx_fifo_expanding_mode_88xx ==========>rx_fifo_expanding_mode = %d\n", rx_fifo_expanding_mode); - - pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode = rx_fifo_expanding_mode; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_rx_fifo_expanding_mode_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_config_security_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_SECURITY_SETTING pSec_setting -) -{ - PHALMAC_API pHalmac_api; - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_config_security_88xx ==========>\n"); - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_CR, (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_CR) | BIT_MAC_SEC_EN)); - - if (pSec_setting->tx_encryption == 1) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) | BIT(2)); - else - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) & ~(BIT(2))); - - if (pSec_setting->rx_decryption == 1) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) | BIT(3)); - else - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) & ~(BIT(3))); - - if (pSec_setting->bip_enable == 1) { - if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8822B) - return HALMAC_RET_BIP_NO_SUPPORT; -#if HALMAC_8821C_SUPPORT - if (pSec_setting->tx_encryption == 1) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) | (BIT(3) | BIT(5))); - else - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) & ~(BIT(3) | BIT(5))); - - if (pSec_setting->rx_decryption == 1) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) | (BIT(4) | BIT(6))); - else - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) & ~(BIT(4) | BIT(6))); -#endif - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_config_security_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -u8 -halmac_get_used_cam_entry_num_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HAL_SECURITY_TYPE sec_type -) -{ - u8 entry_num; - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_get_used_cam_entry_num_88xx ==========>\n"); - - switch (sec_type) { - case HAL_SECURITY_TYPE_WEP40: - case HAL_SECURITY_TYPE_WEP104: - case HAL_SECURITY_TYPE_TKIP: - case HAL_SECURITY_TYPE_AES128: - case HAL_SECURITY_TYPE_GCMP128: - case HAL_SECURITY_TYPE_GCMSMS4: - case HAL_SECURITY_TYPE_BIP: - entry_num = 1; - break; - case HAL_SECURITY_TYPE_WAPI: - case HAL_SECURITY_TYPE_AES256: - case HAL_SECURITY_TYPE_GCMP256: - entry_num = 2; - break; - default: - entry_num = 0; - break; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_get_used_cam_entry_num_88xx <==========\n"); - - return entry_num; -} - -HALMAC_RET_STATUS -halmac_write_cam_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 entry_index, - IN PHALMAC_CAM_ENTRY_INFO pCam_entry_info -) -{ - u32 i; - u32 command = 0x80010000; - PHALMAC_API pHalmac_api; - VOID *pDriver_adapter = NULL; - PHALMAC_CAM_ENTRY_FORMAT pCam_entry_format = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_write_cam_88xx ==========>\n"); - - if (entry_index >= pHalmac_adapter->hw_config_info.cam_entry_num) - return HALMAC_RET_ENTRY_INDEX_ERROR; - - if (pCam_entry_info->key_id > 3) - return HALMAC_RET_FAIL; - - pCam_entry_format = (PHALMAC_CAM_ENTRY_FORMAT)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(*pCam_entry_format)); - if (pCam_entry_format == NULL) - return HALMAC_RET_NULL_POINTER; - PLATFORM_RTL_MEMSET(pDriver_adapter, pCam_entry_format, 0x00, sizeof(*pCam_entry_format)); - - pCam_entry_format->key_id = pCam_entry_info->key_id; - pCam_entry_format->valid = pCam_entry_info->valid; - PLATFORM_RTL_MEMCPY(pDriver_adapter, pCam_entry_format->mac_address, pCam_entry_info->mac_address, 6); - PLATFORM_RTL_MEMCPY(pDriver_adapter, pCam_entry_format->key, pCam_entry_info->key, 16); - - switch (pCam_entry_info->security_type) { - case HAL_SECURITY_TYPE_NONE: - pCam_entry_format->type = 0; - break; - case HAL_SECURITY_TYPE_WEP40: - pCam_entry_format->type = 1; - break; - case HAL_SECURITY_TYPE_WEP104: - pCam_entry_format->type = 5; - break; - case HAL_SECURITY_TYPE_TKIP: - pCam_entry_format->type = 2; - break; - case HAL_SECURITY_TYPE_AES128: - pCam_entry_format->type = 4; - break; - case HAL_SECURITY_TYPE_WAPI: - pCam_entry_format->type = 6; - break; - case HAL_SECURITY_TYPE_AES256: - pCam_entry_format->type = 4; - pCam_entry_format->ext_sectype = 1; - break; - case HAL_SECURITY_TYPE_GCMP128: - pCam_entry_format->type = 7; - break; - case HAL_SECURITY_TYPE_GCMP256: - case HAL_SECURITY_TYPE_GCMSMS4: - pCam_entry_format->type = 7; - pCam_entry_format->ext_sectype = 1; - break; - case HAL_SECURITY_TYPE_BIP: - pCam_entry_format->type = (pCam_entry_info->unicast == 1) ? 4 : 0; - pCam_entry_format->mgnt = 1; - pCam_entry_format->grp = (pCam_entry_info->unicast == 1) ? 0 : 1; - break; - default: - PLATFORM_RTL_FREE(pDriver_adapter, pCam_entry_format, sizeof(*pCam_entry_format)); - return HALMAC_RET_FAIL; - } - - - for (i = 0; i < 8; i++) { - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMWRITE, *((u32 *)pCam_entry_format + i)); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | ((entry_index << 3) + i)); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]1 - CAM entry format : %X\n", *((u32 *)pCam_entry_format + i)); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]1 - REG_CAMCMD : %X\n", command | ((entry_index << 3) + i)); - } - - if (HAL_SECURITY_TYPE_WAPI == pCam_entry_info->security_type || HAL_SECURITY_TYPE_AES256 == pCam_entry_info->security_type || - HAL_SECURITY_TYPE_GCMP256 == pCam_entry_info->security_type || HAL_SECURITY_TYPE_GCMSMS4 == pCam_entry_info->security_type) { - pCam_entry_format->mic = 1; - PLATFORM_RTL_MEMCPY(pDriver_adapter, pCam_entry_format->key, pCam_entry_info->key_ext, 16); - - for (i = 0; i < 8; i++) { - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMWRITE, *((u32 *)pCam_entry_format + i)); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | (((entry_index + 1) << 3) + i)); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]2 - CAM entry format : %X\n", *((u32 *)pCam_entry_format + i)); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]2 - REG_CAMCMD : %X\n", command | (((entry_index + 1) << 3) + i)); - } - } - - PLATFORM_RTL_FREE(pDriver_adapter, pCam_entry_format, sizeof(*pCam_entry_format)); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_write_cam_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_read_cam_entry_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 entry_index, - OUT PHALMAC_CAM_ENTRY_FORMAT pContent -) -{ - u32 i; - u32 command = 0x80000000; - PHALMAC_API pHalmac_api; - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_read_cam_entry_88xx ==========>\n"); - - if (entry_index >= pHalmac_adapter->hw_config_info.cam_entry_num) - return HALMAC_RET_ENTRY_INDEX_ERROR; - - for (i = 0; i < 8; i++) { - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | ((entry_index << 3) + i)); - *((u32 *)pContent + i) = HALMAC_REG_READ_32(pHalmac_adapter, REG_CAMREAD); - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_read_cam_entry_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_clear_cam_entry_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 entry_index -) -{ - u32 i; - u32 command = 0x80010000; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - PHALMAC_CAM_ENTRY_FORMAT pCam_entry_format; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_clear_security_cam_88xx ==========>\n"); - - if (entry_index >= pHalmac_adapter->hw_config_info.cam_entry_num) - return HALMAC_RET_ENTRY_INDEX_ERROR; - - pCam_entry_format = (PHALMAC_CAM_ENTRY_FORMAT)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(*pCam_entry_format)); - if (pCam_entry_format == NULL) - return HALMAC_RET_NULL_POINTER; - PLATFORM_RTL_MEMSET(pDriver_adapter, pCam_entry_format, 0x00, sizeof(*pCam_entry_format)); - - for (i = 0; i < 8; i++) { - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMWRITE, *((u32 *)pCam_entry_format + i)); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | ((entry_index << 3) + i)); - } - - PLATFORM_RTL_FREE(pDriver_adapter, pCam_entry_format, sizeof(*pCam_entry_format)); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_clear_security_cam_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_get_hw_value_88xx() -get hw config value - * @pHalmac_adapter : the adapter of halmac - * @hw_id : hw id for driver to query - * @pvalue : hw value, reference table to get data type - * Author : KaiYuan Chang / Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_get_hw_value_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_HW_ID hw_id, - OUT VOID *pvalue -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_hw_value_88xx ==========>\n"); - - if (pvalue == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_get_hw_value_88xx (NULL ==pvalue)==========>\n"); - return HALMAC_RET_NULL_POINTER; - } - - switch (hw_id) { - case HALMAC_HW_RQPN_MAPPING: - ((PHALMAC_RQPN_MAP)pvalue)->dma_map_vo = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]; - ((PHALMAC_RQPN_MAP)pvalue)->dma_map_vi = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]; - ((PHALMAC_RQPN_MAP)pvalue)->dma_map_be = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]; - ((PHALMAC_RQPN_MAP)pvalue)->dma_map_bk = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]; - ((PHALMAC_RQPN_MAP)pvalue)->dma_map_mg = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]; - ((PHALMAC_RQPN_MAP)pvalue)->dma_map_hi = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]; - break; - case HALMAC_HW_EFUSE_SIZE: - *(u32 *)pvalue = pHalmac_adapter->hw_config_info.efuse_size; - break; - case HALMAC_HW_EEPROM_SIZE: - *(u32 *)pvalue = pHalmac_adapter->hw_config_info.eeprom_size; - break; - case HALMAC_HW_BT_BANK_EFUSE_SIZE: - *(u32 *)pvalue = pHalmac_adapter->hw_config_info.bt_efuse_size; - break; - case HALMAC_HW_BT_BANK1_EFUSE_SIZE: - case HALMAC_HW_BT_BANK2_EFUSE_SIZE: - *(u32 *)pvalue = 0; - break; - case HALMAC_HW_TXFIFO_SIZE: - *(u32 *)pvalue = pHalmac_adapter->hw_config_info.tx_fifo_size; - break; - case HALMAC_HW_RSVD_PG_BNDY: - *(u16 *)pvalue = pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy; - break; - case HALMAC_HW_CAM_ENTRY_NUM: - *(u8 *)pvalue = pHalmac_adapter->hw_config_info.cam_entry_num; - break; - case HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE: /*Remove later*/ - status = halmac_dump_logical_efuse_map_88xx(pHalmac_adapter, HALMAC_EFUSE_R_DRV); - if (status != HALMAC_RET_SUCCESS) - return status; - *(u32 *)pvalue = pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - pHalmac_adapter->efuse_end; - break; - case HALMAC_HW_IC_VERSION: - *(u8 *)pvalue = pHalmac_adapter->chip_version; - break; - case HALMAC_HW_PAGE_SIZE: - *(u32 *)pvalue = pHalmac_adapter->hw_config_info.page_size; - break; - case HALMAC_HW_TX_AGG_ALIGN_SIZE: - *(u16 *)pvalue = pHalmac_adapter->hw_config_info.tx_align_size; - break; - case HALMAC_HW_RX_AGG_ALIGN_SIZE: - *(u8 *)pvalue = 8; - break; - case HALMAC_HW_DRV_INFO_SIZE: - *(u8 *)pvalue = pHalmac_adapter->drv_info_size; - break; - case HALMAC_HW_TXFF_ALLOCATION: - PLATFORM_RTL_MEMCPY(pDriver_adapter, pvalue, &pHalmac_adapter->txff_allocation, sizeof(HALMAC_TXFF_ALLOCATION)); - break; - case HALMAC_HW_TX_DESC_SIZE: - *(u32 *)pvalue = pHalmac_adapter->hw_config_info.txdesc_size; - break; - case HALMAC_HW_RX_DESC_SIZE: - *(u32 *)pvalue = pHalmac_adapter->hw_config_info.rxdesc_size; - break; - case HALMAC_HW_AC_OQT_SIZE: - *(u8 *)pvalue = pHalmac_adapter->hw_config_info.ac_oqt_size; - break; - case HALMAC_HW_NON_AC_OQT_SIZE: - *(u8 *)pvalue = pHalmac_adapter->hw_config_info.non_ac_oqt_size; - break; - case HALMAC_HW_AC_QUEUE_NUM: - *(u8 *)pvalue = pHalmac_adapter->hw_config_info.ac_queue_num; - break; - default: - return HALMAC_RET_PARA_NOT_SUPPORT; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_hw_value_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_set_hw_value_88xx() -set hw config value - * @pHalmac_adapter : the adapter of halmac - * @hw_id : hw id for driver to config - * @pvalue : hw value, reference table to get data type - * Author : KaiYuan Chang / Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_set_hw_value_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_HW_ID hw_id, - IN VOID *pvalue -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_hw_value_88xx ==========>\n"); - - if (pvalue == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_set_hw_value_88xx (NULL == pvalue)==========>\n"); - return HALMAC_RET_NULL_POINTER; - } - - switch (hw_id) { - case HALMAC_HW_USB_MODE: - status = halmac_set_usb_mode_88xx(pHalmac_adapter, *(HALMAC_USB_MODE *)pvalue); - if (status != HALMAC_RET_SUCCESS) - return status; - break; - case HALMAC_HW_SEQ_EN: - /*if (_TRUE == hw_seq_en) { - } else { - }*/ - break; - case HALMAC_HW_BANDWIDTH: - halmac_cfg_bw_88xx(pHalmac_adapter, *(HALMAC_BW *)pvalue); - break; - case HALMAC_HW_CHANNEL: - halmac_cfg_ch_88xx(pHalmac_adapter, *(u8 *)pvalue); - break; - case HALMAC_HW_PRI_CHANNEL_IDX: - halmac_cfg_pri_ch_idx_88xx(pHalmac_adapter, *(HALMAC_PRI_CH_IDX *)pvalue); - break; - case HALMAC_HW_EN_BB_RF: - halmac_enable_bb_rf_88xx(pHalmac_adapter, *(u8 *)pvalue); - break; - case HALMAC_HW_SDIO_TX_PAGE_THRESHOLD: - halmac_config_sdio_tx_page_threshold_88xx(pHalmac_adapter, (PHALMAC_TX_PAGE_THRESHOLD_INFO)pvalue); - break; - case HALMAC_HW_AMPDU_CONFIG: - halmac_config_ampdu_88xx(pHalmac_adapter, (PHALMAC_AMPDU_CONFIG)pvalue); - break; - case HALMAC_HW_RX_SHIFT: - halmac_rx_shift_88xx(pHalmac_adapter, *(u8 *)pvalue); - break; - default: - return HALMAC_RET_PARA_NOT_SUPPORT; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_hw_value_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_drv_rsvd_pg_num_88xx() -config reserved page number for driver - * @pHalmac_adapter : the adapter of halmac - * @pg_num : page number - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_drv_rsvd_pg_num_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DRV_RSVD_PG_NUM pg_num -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_drv_rsvd_pg_num_88xx ==========>\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]pg_num = %d\n", pg_num); - - switch (pg_num) { - case HALMAC_RSVD_PG_NUM16: - pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 16; - break; - case HALMAC_RSVD_PG_NUM24: - pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 24; - break; - case HALMAC_RSVD_PG_NUM32: - pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 32; - break; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_rsvd_pg_num_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_get_chip_version_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_VER pVersion -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_chip_version_88xx ==========>\n"); - pVersion->major_ver = (u8)HALMAC_MAJOR_VER_88XX; - pVersion->prototype_ver = (u8)HALMAC_PROTOTYPE_VER_88XX; - pVersion->minor_ver = (u8)HALMAC_MINOR_VER_88XX; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_chip_version_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_chk_txdesc_88xx() -check if the tx packet format is incorrect - * @pHalmac_adapter : the adapter of halmac - * @halmac_buf : tx Packet buffer, tx desc is included - * @halmac_size : tx packet size - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_chk_txdesc_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHalmac_buf, - IN u32 halmac_size -) -{ - u32 mac_clk = 0; - PHALMAC_API pHalmac_api; - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_chk_txdesc_88xx ==========>\n"); - - if (GET_TX_DESC_BMC(pHalmac_buf) == _TRUE) - if (GET_TX_DESC_AGG_EN(pHalmac_buf) == _TRUE) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]TxDesc: Agg should not be set when BMC\n"); - - if (halmac_size < (GET_TX_DESC_TXPKTSIZE(pHalmac_buf) + GET_TX_DESC_OFFSET(pHalmac_buf))) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]TxDesc: PktSize too small\n"); - - if (GET_TX_DESC_AMSDU_PAD_EN(pHalmac_buf) != 0) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]TxDesc: Do not set AMSDU_PAD_EN\n"); - - switch (BIT_GET_MAC_CLK_SEL(HALMAC_REG_READ_32(pHalmac_adapter, REG_AFE_CTRL1))) { - case 0x0: - mac_clk = 80; - break; - case 0x1: - mac_clk = 40; - break; - case 0x2: - mac_clk = 20; - break; - case 0x3: - mac_clk = 10; - break; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ALWAYS, "MAC clock : 0x%XM\n", mac_clk); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ALWAYS, "TX mac agg enable : 0x%X\n", GET_TX_DESC_AGG_EN(pHalmac_buf)); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ALWAYS, "TX mac agg num : 0x%X\n", GET_TX_DESC_MAX_AGG_NUM(pHalmac_buf)); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_chk_txdesc_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_dl_drv_rsvd_page_88xx() - download packet to rsvd page - * @pHalmac_adapter : the adapter of halmac - * @pg_offset : page offset of driver's rsvd page - * @halmac_buf : data to be downloaded, tx_desc is not included - * @halmac_size : data size to be downloaded - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_dl_drv_rsvd_page_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 pg_offset, - IN u8 *pHalmac_buf, - IN u32 halmac_size -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RET_STATUS ret_status; - u16 drv_pg_bndy = 0; - u32 dl_pg_num = 0; - - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dl_drv_rsvd_page_88xx ==========>\n"); - - /*check boundary and size valid*/ - dl_pg_num = halmac_size / pHalmac_adapter->hw_config_info.page_size + ((halmac_size & (pHalmac_adapter->hw_config_info.page_size - 1)) ? 1 : 0); - if (pg_offset + dl_pg_num > pHalmac_adapter->txff_allocation.rsvd_drv_pg_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERROR] driver download offset or size error ==========>\n"); - return HALMAC_RET_DRV_DL_ERR; - } - - /*update to target download boundary*/ - drv_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy + pg_offset; - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(drv_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - - ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pHalmac_buf, halmac_size); - - /*restore to original bundary*/ - if (ret_status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", ret_status); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - return ret_status; - } - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dl_drv_rsvd_page_88xx < ==========\n"); - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_csi_rate_88xx() - config CSI frame Tx rate - * @pHalmac_adapter : the adapter of halmac - * @rssi : rssi in decimal value - * @current_rate : current CSI frame rate - * @fixrate_en : enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate - * @new_rate : API returns the final CSI frame rate - * Author : chunchu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_csi_rate_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 rssi, - IN u8 current_rate, - IN u8 fixrate_en, - OUT u8 *new_rate -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - u32 temp_csi_setting; - u16 current_rrsr; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_csi_rate_88xx ==========>\n"); - -#if HALMAC_8821C_SUPPORT - if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) { - if (fixrate_en) { - temp_csi_setting = HALMAC_REG_READ_32(pHalmac_adapter, REG_BBPSF_CTRL) & ~(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BBPSF_CTRL, temp_csi_setting | BIT_CSI_FORCE_RATE_EN | BIT_CSI_RSC(1) | BIT_WMAC_CSI_RATE(HALMAC_VHT_NSS1_MCS3)); - *new_rate = HALMAC_VHT_NSS1_MCS3; - return HALMAC_RET_SUCCESS; - } - } - temp_csi_setting = HALMAC_REG_READ_32(pHalmac_adapter, REG_BBPSF_CTRL) & ~(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE) & ~BIT_CSI_FORCE_RATE_EN; -#else - temp_csi_setting = HALMAC_REG_READ_32(pHalmac_adapter, REG_BBPSF_CTRL) & ~(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE); -#endif - - current_rrsr = HALMAC_REG_READ_16(pHalmac_adapter, REG_RRSR); - - if (rssi >= 40) { - if (current_rate != HALMAC_OFDM54) { - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, current_rrsr | BIT(HALMAC_OFDM54)); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BBPSF_CTRL, temp_csi_setting | BIT_WMAC_CSI_RATE(HALMAC_OFDM54)); - } - *new_rate = HALMAC_OFDM54; - return HALMAC_RET_SUCCESS; - } - - if (current_rate != HALMAC_OFDM24) { - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, current_rrsr & ~(BIT(HALMAC_OFDM54))); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BBPSF_CTRL, temp_csi_setting | BIT_WMAC_CSI_RATE(HALMAC_OFDM24)); - } - *new_rate = HALMAC_OFDM24; - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_txfifo_is_empty_88xx() -check if txfifo is empty - * @pHalmac_adapter : the adapter of halmac - * Author : Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_txfifo_is_empty_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 chk_num -) -{ - u32 counter; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_txfifo_is_empty_88xx ==========>\n"); - - counter = (chk_num <= 10) ? 10 : chk_num; - do { - if (HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPKT_EMPTY) != 0xFF) - return HALMAC_RET_TXFIFO_NO_EMPTY; - - if ((HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPKT_EMPTY + 1) & 0x07) != 0x07) - return HALMAC_RET_TXFIFO_NO_EMPTY; - counter--; - - } while (counter != 0); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_txfifo_is_empty_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_download_flash_88xx() -download firmware to flash - * @pHalmac_adapter : the adapter of halmac - * @pHalmac_fw : pointer to fw - * @halmac_fw_size : fw size - * @rom_address : flash start address where fw should be download - * Author : Pablo Chiu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_download_flash_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHalmac_fw, - IN u32 halmac_fw_size, - IN u32 rom_address -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RET_STATUS status; - HALMAC_H2C_HEADER_INFO h2c_header_info; - u8 value8; - u8 restore[3]; - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0}; - u16 h2c_seq_mum = 0; - u32 send_pkt_size, mem_offset; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_flash_88xx ==========>\n"); - - pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; - - value8 = HALMAC_DMA_MAPPING_HIGH << 6; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP + 1, value8); - - /* DLFW only use HIQ, map HIQ to hi priority */ - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31)); - - /* Config hi priority queue and public priority queue page number (only for DLFW) */ - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, 0x200); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31)); - - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { - HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_TX_CTRL, 0x00000000); - } - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 1); - restore[0] = value8; - value8 = (u8)(value8 | BIT(0)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, value8); - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL); - restore[1] = value8; - value8 = (u8)((value8 & (~(BIT(3)))) | BIT(4)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, value8); - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2); - restore[2] = value8; - value8 = (u8)(value8 & ~(BIT(6))); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8); - - /* Set beacon header to 0 */ - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0x8000); - - /* Download FW to Flash flow */ - mem_offset = 0; - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - - while (halmac_fw_size != 0) { - if (halmac_fw_size >= (HALMAC_EXTRA_INFO_BUFF_SIZE_88XX - 48)) - send_pkt_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX - 48; - else - send_pkt_size = halmac_fw_size; - - status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pHalmac_fw + mem_offset, send_pkt_size); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", status); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - goto DLFW_FAIL; - } else { - /* Construct H2C Content */ - DOWNLOAD_FLASH_SET_SPI_CMD(pH2c_buff, 0x02); - DOWNLOAD_FLASH_SET_LOCATION(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy); - DOWNLOAD_FLASH_SET_SIZE(pH2c_buff, send_pkt_size); - DOWNLOAD_FLASH_SET_START_ADDR(pH2c_buff, rom_address); - - /* Fill in H2C Header */ - h2c_header_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH; - h2c_header_info.content_size = 20; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - - /* Send H2C Cmd Packet */ - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n"); - goto DLFW_FAIL; - } - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I); - value8 |= BIT(0); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUTST_I, value8); - } - - rom_address += send_pkt_size; - mem_offset += send_pkt_size; - halmac_fw_size -= send_pkt_size; - - while (((HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I)) & BIT(0)) != 0) - PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000); - - if (((HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I)) & BIT(0)) != 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "download flash fail!!\n"); - goto DLFW_FAIL; - } - } - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, restore[2]); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, restore[1]); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, restore[0]); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_flash_88xx <==========\n"); - return HALMAC_RET_SUCCESS; - -DLFW_FAIL: - - return HALMAC_RET_DLFW_FAIL; -} - -/** - * halmac_read_flash_88xx() -read data from flash - * @pHalmac_adapter : the adapter of halmac - * @addr : flash start address where fw should be read - * Author : Pablo Chiu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_read_flash_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - u32 addr -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RET_STATUS status; - HALMAC_H2C_HEADER_INFO h2c_header_info; - u8 value8; - u8 restore[3]; - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0}; - u16 h2c_seq_mum = 0; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_flash_88xx ==========>\n"); - - pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; - - value8 = HALMAC_DMA_MAPPING_HIGH << 6; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP + 1, value8); - - /* DLFW only use HIQ, map HIQ to hi priority */ - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; - value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31)); - - /* Config hi priority queue and public priority queue page number (only for DLFW) */ - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, 0x200); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31)); - - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { - HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_TX_CTRL, 0x00000000); - } - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 1); - restore[0] = value8; - value8 = (u8)(value8 | BIT(0)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, value8); - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL); - restore[1] = value8; - value8 = (u8)((value8 & (~(BIT(3)))) | BIT(4)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, value8); - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2); - restore[2] = value8; - value8 = (u8)(value8 & ~(BIT(6))); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8); - - /* Set beacon header to 0 */ - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0x8000); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I); - value8 |= BIT(0); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUTST_I, value8); - - /* Construct H2C Content */ - DOWNLOAD_FLASH_SET_SPI_CMD(pH2c_buff, 0x03); - DOWNLOAD_FLASH_SET_LOCATION(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy); - DOWNLOAD_FLASH_SET_SIZE(pH2c_buff, 4096); - DOWNLOAD_FLASH_SET_START_ADDR(pH2c_buff, addr); - - /* Fill in H2C Header */ - h2c_header_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH; - h2c_header_info.content_size = 16; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - - /* Send H2C Cmd Packet */ - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n"); - goto DLFW_FAIL; - } - - while (((HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I)) & BIT(0)) != 0) - PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000); - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, restore[2]); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, restore[1]); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, restore[0]); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_flash_88xx <==========\n"); - return HALMAC_RET_SUCCESS; - -DLFW_FAIL: - - return HALMAC_RET_FAIL; -} - -/** - * halmac_erase_flash_88xx() -erase flash data - * @pHalmac_adapter : the adapter of halmac - * @erase_cmd : erase command - * @addr : flash start address where fw should be erased - * Author : Pablo Chiu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_erase_flash_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - u8 erase_cmd, - u32 addr -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status; - HALMAC_H2C_HEADER_INFO h2c_header_info; - PHALMAC_API pHalmac_api; - u8 value8; - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0}; - u16 h2c_seq_mum = 0; - u32 timeout; - - /* Construct H2C Content */ - DOWNLOAD_FLASH_SET_SPI_CMD(pH2c_buff, erase_cmd); - DOWNLOAD_FLASH_SET_LOCATION(pH2c_buff, 0); - DOWNLOAD_FLASH_SET_START_ADDR(pH2c_buff, addr); - DOWNLOAD_FLASH_SET_SIZE(pH2c_buff, 0); - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I); - value8 |= BIT(0); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUTST_I, value8); - - /* Fill in H2C Header */ - h2c_header_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH; - h2c_header_info.content_size = 16; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - - /* Send H2C Cmd Packet */ - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - - if (status != HALMAC_RET_SUCCESS) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n"); - - timeout = 5000; - while ((((HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUTST_I)) & BIT(0)) != 0) && (timeout != 0)) { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000); - timeout--; - } - - if (timeout == 0) - return HALMAC_RET_FAIL; - else - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_check_flash_88xx() -check flash data - * @pHalmac_adapter : the adapter of halmac - * @pHalmac_fw : pointer to fw - * @halmac_fw_size : fw size - * @addr : flash start address where fw should be checked - * Author : Pablo Chiu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_check_flash_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHalmac_fw, - IN u32 halmac_fw_size, - IN u32 addr -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - u8 value8; - u16 value16, residue; - u32 send_pkt_size, start_page, counter; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - while (halmac_fw_size != 0) { - start_page = ((pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy << 7) >> 12) + 0x780; - residue = (pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy << 7) & (4096 - 1); - - if (halmac_fw_size >= HALMAC_EXTRA_INFO_BUFF_SIZE_88XX) - send_pkt_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX; - else - send_pkt_size = halmac_fw_size; - - halmac_read_flash_88xx(pHalmac_adapter, addr); - - value16 = HALMAC_REG_READ_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL); - counter = 0; - while (counter < send_pkt_size) { - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL, (u16)(start_page | (value16 & 0xF000))); - for (value16 = 0x8000 + residue; value16 <= 0x8FFF; value16++) { - value8 = HALMAC_REG_READ_8(pHalmac_adapter, value16); - - if (*pHalmac_fw != value8) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "check flash fail!!\n"); - goto DLFW_FAIL; - } - pHalmac_fw++; - - counter++; - if (counter == send_pkt_size) - break; - } - residue = 0; - start_page++; - } - addr += send_pkt_size; - halmac_fw_size -= send_pkt_size; - } - - return HALMAC_RET_SUCCESS; - -DLFW_FAIL: - - return HALMAC_RET_FAIL; -} - - -/** - * halmac_cfg_edca_para_88xx() - config edca parameter - * @pHalmac_adapter : the adapter of halmac - * @acq_id : VO/VI/BE/BK - * @pEdca_para : aifs, cw, txop limit - * Author : Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_edca_para_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_ACQ_ID acq_id, - IN PHALMAC_EDCA_PARA pEdca_para -) -{ - u32 offset, value32; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_edca_88xx ==========>\n"); - - switch (acq_id) { - case HALMAC_ACQ_ID_VO: - offset = REG_EDCA_VO_PARAM; - break; - case HALMAC_ACQ_ID_VI: - offset = REG_EDCA_VI_PARAM; - break; - case HALMAC_ACQ_ID_BE: - offset = REG_EDCA_BE_PARAM; - break; - case HALMAC_ACQ_ID_BK: - offset = REG_EDCA_BK_PARAM; - break; - default: - return HALMAC_RET_SWITCH_CASE_ERROR; - } - - value32 = (pEdca_para->aifs & 0xFF) | ((pEdca_para->cw & 0xFF) << 8) | ((pEdca_para->txop_limit & 0x7FF) << 16); - - HALMAC_REG_WRITE_32(pHalmac_adapter, offset, value32); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_edca_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx.h b/hal/halmac/halmac_88xx/halmac_api_88xx.h deleted file mode 100644 index 74a747f..0000000 --- a/hal/halmac/halmac_88xx/halmac_api_88xx.h +++ /dev/null @@ -1,638 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_API_88XX_H_ -#define _HALMAC_API_88XX_H_ - -#include "../halmac_2_platform.h" -#include "../halmac_type.h" - -VOID -halmac_init_state_machine_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -VOID -halmac_init_adapter_para_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -VOID -halmac_init_adapter_dynamic_para_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_mount_api_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_download_firmware_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHamacl_fw, - IN u32 halmac_fw_size -); - -HALMAC_RET_STATUS -halmac_free_download_firmware_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DLFW_MEM dlfw_mem, - IN u8 *pHamacl_fw, - IN u32 halmac_fw_size -); - -HALMAC_RET_STATUS -halmac_get_fw_version_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT PHALMAC_FW_VERSION pFw_version -); - -HALMAC_RET_STATUS -halmac_cfg_mac_addr_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 halmac_port, - IN PHALMAC_WLAN_ADDR pHal_address -); - -HALMAC_RET_STATUS -halmac_cfg_bssid_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 halmac_port, - IN PHALMAC_WLAN_ADDR pHal_address -); - -HALMAC_RET_STATUS -halmac_cfg_multicast_addr_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_WLAN_ADDR pHal_address -); - -HALMAC_RET_STATUS -halmac_pre_init_system_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_init_system_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_cfg_rx_aggregation_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_RXAGG_CFG halmac_rxagg_cfg -); - -HALMAC_RET_STATUS -halmac_init_edca_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_cfg_operation_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_WIRELESS_MODE wireless_mode -); - -HALMAC_RET_STATUS -halmac_cfg_ch_bw_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 channel, - IN HALMAC_PRI_CH_IDX pri_ch_idx, - IN HALMAC_BW bw -); - -HALMAC_RET_STATUS -halmac_cfg_ch_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 channel -); - -HALMAC_RET_STATUS -halmac_cfg_pri_ch_idx_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_PRI_CH_IDX pri_ch_idx -); - -HALMAC_RET_STATUS -halmac_cfg_bw_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_BW bw -); - -HALMAC_RET_STATUS -halmac_init_wmac_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_init_mac_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE mode -); - -HALMAC_RET_STATUS -halmac_dump_efuse_map_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_EFUSE_READ_CFG cfg -); - -HALMAC_RET_STATUS -halmac_dump_efuse_map_bt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_EFUSE_BANK halmac_efuse_bank, - IN u32 bt_efuse_map_size, - OUT u8 *pBT_efuse_map -); - -HALMAC_RET_STATUS -halmac_write_efuse_bt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u8 halmac_value, - IN HALMAC_EFUSE_BANK halmac_efuse_bank -); - -HALMAC_RET_STATUS -halmac_read_efuse_bt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - OUT u8 *pValue, - IN HALMAC_EFUSE_BANK halmac_efuse_bank -); - -HALMAC_RET_STATUS -halmac_cfg_efuse_auto_check_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable -); - -HALMAC_RET_STATUS -halmac_pg_efuse_by_map_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, - IN HALMAC_EFUSE_READ_CFG cfg -); - -HALMAC_RET_STATUS -halmac_get_efuse_size_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u32 *halmac_size -); - -HALMAC_RET_STATUS -halmac_get_efuse_available_size_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u32 *halmac_size -); - -HALMAC_RET_STATUS -halmac_get_c2h_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *halmac_buf, - IN u32 halmac_size -); - -HALMAC_RET_STATUS -halmac_get_logical_efuse_size_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u32 *halmac_size -); - -HALMAC_RET_STATUS -halmac_dump_logical_efuse_map_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_EFUSE_READ_CFG cfg -); - -HALMAC_RET_STATUS -halmac_write_logical_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u8 halmac_value -); - -HALMAC_RET_STATUS -halmac_read_logical_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - OUT u8 *pValue -); - -HALMAC_RET_STATUS -halmac_h2c_lb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_debug_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_cfg_parameter_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PHY_PARAMETER_INFO para_info, - IN u8 full_fifo -); - -HALMAC_RET_STATUS -halmac_update_packet_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_PACKET_ID pkt_id, - IN u8 *pkt, - IN u32 pkt_size -); - -HALMAC_RET_STATUS -halmac_bcn_ie_filter_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_BCN_IE_INFO pBcn_ie_info -); - -HALMAC_RET_STATUS -halmac_send_original_h2c_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *original_h2c, - IN u16 *seq, - IN u8 ack -); - -HALMAC_RET_STATUS -halmac_update_datapack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DATA_TYPE halmac_data_type, - IN PHALMAC_PHY_PARAMETER_INFO para_info -); - -HALMAC_RET_STATUS -halmac_run_datapack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DATA_TYPE halmac_data_type -); - -HALMAC_RET_STATUS -halmac_cfg_drv_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DRV_INFO halmac_drv_info -); - -HALMAC_RET_STATUS -halmac_send_bt_coex_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pBt_buf, - IN u32 bt_size, - IN u8 ack -); - -HALMAC_RET_STATUS -halmac_verify_platform_api_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_timer_2s_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_fill_txdesc_check_sum_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *cur_desc -); - -HALMAC_RET_STATUS -halmac_dump_fifo_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HAL_FIFO_SEL halmac_fifo_sel, - IN u32 halmac_start_addr, - IN u32 halmac_fifo_dump_size, - OUT u8 *pFifo_map -); - -u32 -halmac_get_fifo_size_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HAL_FIFO_SEL halmac_fifo_sel -); - -HALMAC_RET_STATUS -halmac_cfg_txbf_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 userid, - IN HALMAC_BW bw, - IN u8 txbf_en -); - -HALMAC_RET_STATUS -halmac_cfg_mumimo_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_CFG_MUMIMO_PARA pCfgmu -); - -HALMAC_RET_STATUS -halmac_cfg_sounding_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_SND_ROLE role, - IN HALMAC_DATA_RATE datarate -); - -HALMAC_RET_STATUS -halmac_del_sounding_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_SND_ROLE role -); - -HALMAC_RET_STATUS -halmac_su_bfee_entry_init_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 userid, - IN u16 paid -); - -HALMAC_RET_STATUS -halmac_su_bfer_entry_init_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init -); - -HALMAC_RET_STATUS -halmac_mu_bfee_entry_init_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init -); - -HALMAC_RET_STATUS -halmac_mu_bfer_entry_init_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init -); - -HALMAC_RET_STATUS -halmac_su_bfee_entry_del_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 userid -); - -HALMAC_RET_STATUS -halmac_su_bfer_entry_del_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 userid -); - -HALMAC_RET_STATUS -halmac_mu_bfee_entry_del_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 userid -); - -HALMAC_RET_STATUS -halmac_mu_bfer_entry_del_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_add_ch_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_CH_INFO pCh_info -); - -HALMAC_RET_STATUS -halmac_add_extra_ch_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_CH_EXTRA_INFO pCh_extra_info -); - -HALMAC_RET_STATUS -halmac_ctrl_ch_switch_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_CH_SWITCH_OPTION pCs_option -); - -HALMAC_RET_STATUS -halmac_p2pps_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_P2PPS pP2PPS -); - -static HALMAC_RET_STATUS -halmac_func_p2pps_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_P2PPS pP2PPS -); - -HALMAC_RET_STATUS -halmac_clear_ch_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_send_general_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_GENERAL_INFO pGeneral_info -); - -HALMAC_RET_STATUS -halmac_start_iqk_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_IQK_PARA pIqk_para -); - -HALMAC_RET_STATUS -halmac_ctrl_pwr_tracking_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt -); - -HALMAC_RET_STATUS -halmac_query_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_FEATURE_ID feature_id, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -); - -HALMAC_RET_STATUS -halmac_reset_feature_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_FEATURE_ID feature_id -); - -HALMAC_RET_STATUS -halmac_check_fw_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u8 *fw_status -); - -HALMAC_RET_STATUS -halmac_dump_fw_dmem_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - INOUT u8 *dmem, - INOUT u32 *size -); - -HALMAC_RET_STATUS -halmac_cfg_max_dl_size_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 size -); - - -HALMAC_RET_STATUS -halmac_psd_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u16 start_psd, - IN u16 end_psd -); - -HALMAC_RET_STATUS -halmac_cfg_la_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_LA_MODE la_mode -); - -HALMAC_RET_STATUS -halmac_cfg_rx_fifo_expanding_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode -); - -HALMAC_RET_STATUS -halmac_config_security_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_SECURITY_SETTING pSec_setting -); - -u8 -halmac_get_used_cam_entry_num_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HAL_SECURITY_TYPE sec_type -); - -HALMAC_RET_STATUS -halmac_write_cam_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 entry_index, - IN PHALMAC_CAM_ENTRY_INFO pCam_entry_info -); - -HALMAC_RET_STATUS -halmac_read_cam_entry_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 entry_index, - OUT PHALMAC_CAM_ENTRY_FORMAT pContent -); - -HALMAC_RET_STATUS -halmac_clear_cam_entry_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 entry_index -); - -HALMAC_RET_STATUS -halmac_get_hw_value_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_HW_ID hw_id, - OUT VOID *pvalue -); - -HALMAC_RET_STATUS -halmac_set_hw_value_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_HW_ID hw_id, - IN VOID *pvalue -); - -HALMAC_RET_STATUS -halmac_cfg_drv_rsvd_pg_num_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DRV_RSVD_PG_NUM pg_num -); - -HALMAC_RET_STATUS -halmac_get_chip_version_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_VER pVersion -); - -HALMAC_RET_STATUS -halmac_chk_txdesc_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHalmac_buf, - IN u32 halmac_size -); - -HALMAC_RET_STATUS -halmac_dl_drv_rsvd_page_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 pg_offset, - IN u8 *pHalmac_buf, - IN u32 halmac_size -); - -HALMAC_RET_STATUS -halmac_cfg_csi_rate_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 rssi, - IN u8 current_rate, - IN u8 fixrate_en, - OUT u8 *new_rate -); - -HALMAC_RET_STATUS -halmac_txfifo_is_empty_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 chk_num -); - -HALMAC_RET_STATUS -halmac_download_flash_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHalmac_fw, - IN u32 halmac_fw_size, - IN u32 rom_address -); - -HALMAC_RET_STATUS -halmac_read_flash_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - u32 addr -); - -HALMAC_RET_STATUS -halmac_erase_flash_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - u8 erase_cmd, - u32 addr -); - -HALMAC_RET_STATUS -halmac_check_flash_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHalmac_fw, - IN u32 halmac_fw_size, - IN u32 addr -); - -HALMAC_RET_STATUS -halmac_cfg_edca_para_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_ACQ_ID acq_id, - IN PHALMAC_EDCA_PARA pEdca_para -); - -#endif/* _HALMAC_API_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c b/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c deleted file mode 100644 index c08801b..0000000 --- a/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c +++ /dev/null @@ -1,310 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#include "halmac_88xx_cfg.h" - -/** - * halmac_init_pcie_cfg_88xx() - init PCIe - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_init_pcie_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_pcie_cfg_88xx ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_pcie_cfg_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_deinit_pcie_cfg_88xx() - deinit PCIE - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_deinit_pcie_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_pcie_cfg_88xx ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_pcie_cfg_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_rx_aggregation_88xx_pcie() - config rx aggregation - * @pHalmac_adapter : the adapter of halmac - * @halmac_rx_agg_mode - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_rx_aggregation_88xx_pcie( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_pcie ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_pcie <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_reg_read_8_pcie_88xx() - read 1byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -u8 -halmac_reg_read_8_pcie_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - return PLATFORM_REG_READ_8(pDriver_adapter, halmac_offset); -} - -/** - * halmac_reg_write_8_pcie_88xx() - write 1byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * @halmac_data : register value - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_reg_write_8_pcie_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u8 halmac_data -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_REG_WRITE_8(pDriver_adapter, halmac_offset, halmac_data); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_reg_read_16_pcie_88xx() - read 2byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -u16 -halmac_reg_read_16_pcie_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - return PLATFORM_REG_READ_16(pDriver_adapter, halmac_offset); -} - -/** - * halmac_reg_write_16_pcie_88xx() - write 2byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * @halmac_data : register value - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_reg_write_16_pcie_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u16 halmac_data -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_REG_WRITE_16(pDriver_adapter, halmac_offset, halmac_data); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_reg_read_32_pcie_88xx() - read 4byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -u32 -halmac_reg_read_32_pcie_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - return PLATFORM_REG_READ_32(pDriver_adapter, halmac_offset); -} - -/** - * halmac_reg_write_32_pcie_88xx() - write 4byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * @halmac_data : register value - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_reg_write_32_pcie_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u32 halmac_data -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_REG_WRITE_32(pDriver_adapter, halmac_offset, halmac_data); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_tx_agg_align_pcie_88xx() -config sdio bus tx agg alignment - * @pHalmac_adapter : the adapter of halmac - * @enable : function enable(1)/disable(0) - * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11) - * Author : Soar Tu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_tx_agg_align_pcie_not_support_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable, - IN u16 align_size -) -{ - return HALMAC_RET_NOT_SUPPORT; -} diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h b/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h deleted file mode 100644 index 0e471b1..0000000 --- a/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h +++ /dev/null @@ -1,84 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_API_88XX_PCIE_H_ -#define _HALMAC_API_88XX_PCIE_H_ - -#include "../halmac_2_platform.h" -#include "../halmac_type.h" - -HALMAC_RET_STATUS -halmac_init_pcie_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_deinit_pcie_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_cfg_rx_aggregation_88xx_pcie( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg -); - -u8 -halmac_reg_read_8_pcie_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -); - -HALMAC_RET_STATUS -halmac_reg_write_8_pcie_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u8 halmac_data -); - -u16 -halmac_reg_read_16_pcie_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -); - -HALMAC_RET_STATUS -halmac_reg_write_16_pcie_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u16 halmac_data -); - -u32 -halmac_reg_read_32_pcie_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -); - -HALMAC_RET_STATUS -halmac_reg_write_32_pcie_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u32 halmac_data -); - -HALMAC_RET_STATUS -halmac_cfg_tx_agg_align_pcie_not_support_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable, - IN u16 align_size -); - -#endif/* _HALMAC_API_88XX_PCIE_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c b/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c deleted file mode 100644 index 3d4e6c1..0000000 --- a/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c +++ /dev/null @@ -1,980 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#include "halmac_88xx_cfg.h" - -/** - * halmac_init_sdio_cfg_88xx() - init SDIO - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_init_sdio_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u32 value32; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (pHalmac_adapter->halmac_interface != HALMAC_INTERFACE_SDIO) - return HALMAC_RET_WRONG_INTF; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_init_sdio_cfg_88xx ==========>\n"); - - HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_TX_CTRL); - value32 &= 0x0000FFFF; - value32 &= ~(BIT_CMD_ERR_STOP_INT_EN | BIT_EN_MASK_TIMER | BIT_EN_RXDMA_MASK_INT); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_TX_CTRL, value32); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_init_sdio_cfg_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_deinit_sdio_cfg_88xx() - deinit SDIO - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_deinit_sdio_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_sdio_cfg_88xx ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_sdio_cfg_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_rx_aggregation_88xx_sdio() - config rx aggregation - * @pHalmac_adapter : the adapter of halmac - * @halmac_rx_agg_mode - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_rx_aggregation_88xx_sdio( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg -) -{ - u8 value8; - u8 size = 0, timeout = 0, agg_enable = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_sdio ==========>\n"); - - agg_enable = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP); - - switch (phalmac_rxagg_cfg->mode) { - case HALMAC_RX_AGG_MODE_NONE: - agg_enable &= ~(BIT_RXDMA_AGG_EN); - break; - case HALMAC_RX_AGG_MODE_DMA: - case HALMAC_RX_AGG_MODE_USB: - agg_enable |= BIT_RXDMA_AGG_EN; - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_rx_aggregation_88xx_usb switch case not support\n"); - agg_enable &= ~BIT_RXDMA_AGG_EN; - break; - } - - if (phalmac_rxagg_cfg->threshold.drv_define == _FALSE) { - size = 0xFF; - timeout = 0x01; - } else { - size = phalmac_rxagg_cfg->threshold.size; - timeout = phalmac_rxagg_cfg->threshold.timeout; - } - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP, agg_enable); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXDMA_AGG_PG_TH, (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1))); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RXDMA_MODE); - if (0 != (agg_enable & BIT_RXDMA_AGG_EN)) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXDMA_MODE, value8 | BIT_DMA_MODE); - else - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXDMA_MODE, value8 & ~(BIT_DMA_MODE)); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_sdio <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_reg_read_8_sdio_88xx() - read 1byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -u8 -halmac_reg_read_8_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -) -{ - u8 value8; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (0 == (halmac_offset & 0xFFFF0000)) - halmac_offset |= WLAN_IOREG_OFFSET; - - status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_8_sdio_88xx error = %x\n", status); - return status; - } - - value8 = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset); - - return value8; -} - -/** - * halmac_reg_write_8_sdio_88xx() - write 1byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * @halmac_data : register value - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_reg_write_8_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u8 halmac_data -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (0 == (halmac_offset & 0xFFFF0000)) - halmac_offset |= WLAN_IOREG_OFFSET; - - status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_8_sdio_88xx error = %x\n", status); - return status; - } - - PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, halmac_data); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_reg_read_16_sdio_88xx() - read 2byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -u16 -halmac_reg_read_16_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - u32 halmac_offset_old = 0; - - union { - u16 word; - u8 byte[2]; - } value16 = { 0x0000 }; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - halmac_offset_old = halmac_offset; - - if (0 == (halmac_offset & 0xFFFF0000)) - halmac_offset |= WLAN_IOREG_OFFSET; - - status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_16_sdio_88xx error = %x\n", status); - return status; - } - - if ((pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) || ((halmac_offset & (2 - 1)) != 0) || - (pHalmac_adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW) || (pHalmac_adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_R)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]use cmd52, offset = %x\n", halmac_offset); - value16.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset); - value16.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1); - value16.word = rtk_le16_to_cpu(value16.word); - } else { - if (pHalmac_adapter->sdio_hw_info.io_hi_speed_flag != 0) { - if ((halmac_offset_old & 0xffffef00) == 0x00000000) { - value16.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset); - value16.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1); - value16.word = rtk_le16_to_cpu(value16.word); - } else { - value16.word = PLATFORM_SDIO_CMD53_READ_16(pDriver_adapter, halmac_offset); - } - } else { - value16.word = PLATFORM_SDIO_CMD53_READ_16(pDriver_adapter, halmac_offset); - } - } - - return value16.word; -} - -/** - * halmac_reg_write_16_sdio_88xx() - write 2byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * @halmac_data : register value - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_reg_write_16_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u16 halmac_data -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - if (0 == (halmac_offset & 0xFFFF0000)) - halmac_offset |= WLAN_IOREG_OFFSET; - - status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_16_sdio_88xx error = %x\n", status); - return status; - } - - if ((pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) || ((halmac_offset & (2 - 1)) != 0) || - (pHalmac_adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW) || (pHalmac_adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_W)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]use cmd52, offset = %x\n", halmac_offset); - PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, (u8)(halmac_data & 0xFF)); - PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 1, (u8)((halmac_data & 0xFF00) >> 8)); - } else { - PLATFORM_SDIO_CMD53_WRITE_16(pDriver_adapter, halmac_offset, halmac_data); - } - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_reg_read_32_sdio_88xx() - read 4byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -u32 -halmac_reg_read_32_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - u32 halmac_offset_old = 0; - - union { - u32 dword; - u8 byte[4]; - } value32 = { 0x00000000 }; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - halmac_offset_old = halmac_offset; - - if (0 == (halmac_offset & 0xFFFF0000)) - halmac_offset |= WLAN_IOREG_OFFSET; - - status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_32_sdio_88xx error = %x\n", status); - return status; - } - - if (pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF || (halmac_offset & (4 - 1)) != 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_WARN, "[WARN]use cmd52, offset = %x\n", halmac_offset); - value32.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset); - value32.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1); - value32.byte[2] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 2); - value32.byte[3] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 3); - value32.dword = rtk_le32_to_cpu(value32.dword); - } else { - if (pHalmac_adapter->sdio_hw_info.io_hi_speed_flag != 0) { - if ((halmac_offset_old & 0xffffef00) == 0x00000000) { - value32.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset); - value32.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1); - value32.byte[2] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 2); - value32.byte[3] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 3); - value32.dword = rtk_le32_to_cpu(value32.dword); - } else { - value32.dword = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset); - } - } else { - value32.dword = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset); - } - } - - return value32.dword; -} - -/** - * halmac_reg_write_32_sdio_88xx() - write 4byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * @halmac_data : register value - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_reg_write_32_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u32 halmac_data -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - if ((halmac_offset & 0xFFFF0000) == 0) - halmac_offset |= WLAN_IOREG_OFFSET; - - status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_32_sdio_88xx error = %x\n", status); - return status; - } - - if (pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF || (halmac_offset & (4 - 1)) != 0) { - PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, (u8)(halmac_data & 0xFF)); - PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 1, (u8)((halmac_data & 0xFF00) >> 8)); - PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 2, (u8)((halmac_data & 0xFF0000) >> 16)); - PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 3, (u8)((halmac_data & 0xFF000000) >> 24)); - } else { - PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, halmac_offset, halmac_data); - } - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_reg_read_nbyte_sdio_88xx() - read n byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * @halmac_size : register value size - * @halmac_data : register value - * Author : Soar - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -u8 -halmac_reg_read_nbyte_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u32 halmac_size, - OUT u8 *halmac_data -) -{ - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - if (0 == (halmac_offset & 0xFFFF0000)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_offset error = 0x%x\n", halmac_offset); - return HALMAC_RET_FAIL; - } - - status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_nbyte_sdio_88xx error = %x\n", status); - return status; - } - - if (pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_state error = 0x%x\n", pHalmac_adapter->halmac_state.mac_power); - return HALMAC_RET_FAIL; - } - - PLATFORM_SDIO_CMD53_READ_N(pDriver_adapter, halmac_offset, halmac_size, halmac_data); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_get_sdio_tx_addr_sdio_88xx() - get CMD53 addr for the TX packet - * @pHalmac_adapter : the adapter of halmac - * @halmac_buf : tx packet, include txdesc - * @halmac_size : tx packet size - * @pcmd53_addr : cmd53 addr value - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_get_sdio_tx_addr_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *halmac_buf, - IN u32 halmac_size, - OUT u32 *pcmd53_addr -) -{ - u32 four_byte_len; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_QUEUE_SELECT queue_sel; - HALMAC_DMA_MAPPING dma_mapping; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_sdio_tx_addr_88xx ==========>\n"); - - if (halmac_buf == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buf is NULL!!\n"); - return HALMAC_RET_DATA_BUF_NULL; - } - - if (halmac_size == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_size is 0!!\n"); - return HALMAC_RET_DATA_SIZE_INCORRECT; - } - - queue_sel = (HALMAC_QUEUE_SELECT)GET_TX_DESC_QSEL(halmac_buf); - - switch (queue_sel) { - case HALMAC_QUEUE_SELECT_VO: - case HALMAC_QUEUE_SELECT_VO_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]; - break; - case HALMAC_QUEUE_SELECT_VI: - case HALMAC_QUEUE_SELECT_VI_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]; - break; - case HALMAC_QUEUE_SELECT_BE: - case HALMAC_QUEUE_SELECT_BE_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]; - break; - case HALMAC_QUEUE_SELECT_BK: - case HALMAC_QUEUE_SELECT_BK_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]; - break; - case HALMAC_QUEUE_SELECT_MGNT: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]; - break; - case HALMAC_QUEUE_SELECT_HIGH: - case HALMAC_QUEUE_SELECT_BCN: - case HALMAC_QUEUE_SELECT_CMD: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]; - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Qsel is out of range\n"); - return HALMAC_RET_QSEL_INCORRECT; - } - - four_byte_len = (halmac_size >> 2) + ((halmac_size & (4 - 1)) ? 1 : 0); - - switch (dma_mapping) { - case HALMAC_DMA_MAPPING_HIGH: - *pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_HIGH; - break; - case HALMAC_DMA_MAPPING_NORMAL: - *pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL; - break; - case HALMAC_DMA_MAPPING_LOW: - *pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_LOW; - break; - case HALMAC_DMA_MAPPING_EXTRA: - *pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA; - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "DmaMapping is out of range\n"); - return HALMAC_RET_DMA_MAP_INCORRECT; - } - - *pcmd53_addr = (*pcmd53_addr << 13) | (four_byte_len & HALMAC_SDIO_4BYTE_LEN_MASK); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_sdio_tx_addr_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_tx_agg_align_sdio_88xx() -config sdio bus tx agg alignment - * @pHalmac_adapter : the adapter of halmac - * @enable : function enable(1)/disable(0) - * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11) - * Author : Soar Tu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_tx_agg_align_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable, - IN u16 align_size -) -{ - PHALMAC_API pHalmac_api; - VOID *pDriver_adapter = NULL; - u8 i, align_size_ok = 0; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_88xx ==========>\n"); - - if ((align_size & 0xF000) != 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Align size is out of range\n"); - return HALMAC_RET_FAIL; - } - - for (i = 3; i <= 11; i++) { - if (align_size == 1 << i) { - align_size_ok = 1; - break; - } - } - if (align_size_ok == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Align size is not 2^3 ~ 2^11\n"); - return HALMAC_RET_FAIL; - } - - /*Keep sdio tx agg alignment size for driver query*/ - pHalmac_adapter->hw_config_info.tx_align_size = align_size; - - if (enable) - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RQPN_CTRL_2, 0x8000 | align_size); - else - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RQPN_CTRL_2, align_size); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_cfg_tx_agg_align_sdio_not_support_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable, - IN u16 align_size -) -{ - PHALMAC_API pHalmac_api; - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_not_support_88xx ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_not_support_88xx not support\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_not_support_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_tx_allowed_sdio_88xx() - check tx status - * @pHalmac_adapter : the adapter of halmac - * @pHalmac_buf : tx packet, include txdesc - * @halmac_size : tx packet size, include txdesc - * Author : Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_tx_allowed_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHalmac_buf, - IN u32 halmac_size -) -{ - u8 *pCurr_packet; - u16 *pCurr_free_space; - u32 i, counter; - u32 tx_agg_num, packet_size = 0; - u32 tx_required_page_num, total_required_page_num = 0; - u8 macid_group[HALMAC_MACID_MAX_88XX + 1] = {0}, qsel; - u8 macid, macid_counter = 0; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - VOID *pDriver_adapter = NULL; - HALMAC_DMA_MAPPING dma_mapping; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_tx_allowed_sdio_88xx ==========>\n"); - - tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(pHalmac_buf); - pCurr_packet = pHalmac_buf; - - tx_agg_num = (tx_agg_num == 0) ? 1 : tx_agg_num; - - qsel = (u8)GET_TX_DESC_QSEL(pCurr_packet); - switch ((HALMAC_QUEUE_SELECT)qsel) { - case HALMAC_QUEUE_SELECT_VO: - case HALMAC_QUEUE_SELECT_VO_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]; - break; - case HALMAC_QUEUE_SELECT_VI: - case HALMAC_QUEUE_SELECT_VI_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]; - break; - case HALMAC_QUEUE_SELECT_BE: - case HALMAC_QUEUE_SELECT_BE_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]; - break; - case HALMAC_QUEUE_SELECT_BK: - case HALMAC_QUEUE_SELECT_BK_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]; - break; - case HALMAC_QUEUE_SELECT_MGNT: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]; - break; - case HALMAC_QUEUE_SELECT_HIGH: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]; - break; - case HALMAC_QUEUE_SELECT_BCN: - case HALMAC_QUEUE_SELECT_CMD: - return HALMAC_RET_SUCCESS; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "Qsel is out of range\n"); - return HALMAC_RET_QSEL_INCORRECT; - } - - switch (dma_mapping) { - case HALMAC_DMA_MAPPING_HIGH: - pCurr_free_space = &pHalmac_adapter->sdio_free_space.high_queue_number; - break; - case HALMAC_DMA_MAPPING_NORMAL: - pCurr_free_space = &pHalmac_adapter->sdio_free_space.normal_queue_number; - break; - case HALMAC_DMA_MAPPING_LOW: - pCurr_free_space = &pHalmac_adapter->sdio_free_space.low_queue_number; - break; - case HALMAC_DMA_MAPPING_EXTRA: - pCurr_free_space = &pHalmac_adapter->sdio_free_space.extra_queue_number; - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "DmaMapping is out of range\n"); - return HALMAC_RET_DMA_MAP_INCORRECT; - } - - for (i = 0; i < tx_agg_num; i++) { - /*MACID parser*/ - macid = (u8)GET_TX_DESC_MACID(pCurr_packet); - if (macid_group[macid] == 0) { - macid_group[macid] = 1; - macid_counter++; - } - /*QSEL parser*/ - if (qsel != GET_TX_DESC_QSEL(pCurr_packet)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "Multi-Qsel in a bus agg is not allowed, qsel = %d, %d\n", qsel, GET_TX_DESC_QSEL(pCurr_packet)); - return HALMAC_RET_QSEL_INCORRECT; - } - /*Page number parser*/ - packet_size = GET_TX_DESC_TXPKTSIZE(pCurr_packet) + GET_TX_DESC_OFFSET(pCurr_packet) + (GET_TX_DESC_PKT_OFFSET(pCurr_packet) << 3); - tx_required_page_num = (packet_size >> pHalmac_adapter->hw_config_info.page_size_2_power) + ((packet_size & (pHalmac_adapter->hw_config_info.page_size - 1)) ? 1 : 0); - total_required_page_num += tx_required_page_num; - - packet_size = HALMAC_ALIGN(packet_size, 8); - - pCurr_packet += packet_size; - } - - counter = 10; - do { - if ((u32)(*pCurr_free_space + pHalmac_adapter->sdio_free_space.public_queue_number) > total_required_page_num) { - status = halmac_check_oqt_88xx(pHalmac_adapter, tx_agg_num, pHalmac_buf, macid_counter); - - if (status != HALMAC_RET_SUCCESS) - return status; - - if (*pCurr_free_space >= total_required_page_num) { - *pCurr_free_space -= (u16)total_required_page_num; - } else { - pHalmac_adapter->sdio_free_space.public_queue_number -= (u16)(total_required_page_num - *pCurr_free_space); - *pCurr_free_space = 0; - } - - break; - } - - halmac_update_sdio_free_page_88xx(pHalmac_adapter); - - counter--; - if (counter == 0) - return HALMAC_RET_FREE_SPACE_NOT_ENOUGH; - } while (1); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_tx_allowed_sdio_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_reg_read_indirect_32_sdio_88xx() - read MAC reg by SDIO reg - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * Author : Soar - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -u32 -halmac_reg_read_indirect_32_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -) -{ - u8 rtemp; - u32 counter = 1000; - VOID *pDriver_adapter = NULL; - - union { - u32 dword; - u8 byte[4]; - } value32 = { 0x00000000 }; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | (REG_SDIO_INDIRECT_REG_CFG & HALMAC_SDIO_LOCAL_MSK), halmac_offset | BIT(19) | BIT(17)); - - do { - rtemp = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | ((REG_SDIO_INDIRECT_REG_CFG + 2) & HALMAC_SDIO_LOCAL_MSK)); - counter--; - } while (((rtemp & BIT(4)) != 0) && (counter > 0)); - - value32.dword = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | (REG_SDIO_INDIRECT_REG_DATA & HALMAC_SDIO_LOCAL_MSK)); - - return value32.dword; -} - - -/** - * halmac_sdio_cmd53_4byte_88xx() - cmd53 only for 4byte len register IO - * @pHalmac_adapter : the adapter of halmac - * @enable : 1->CMD53 only use in 4byte reg, 0 : No limitation - * Author : Ivan Lin/KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_sdio_cmd53_4byte_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_SDIO_CMD53_4BYTE_MODE cmd53_4byte_mode -) -{ - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (pHalmac_adapter->halmac_interface != HALMAC_INTERFACE_SDIO) - return HALMAC_RET_WRONG_INTF; - - pHalmac_adapter->sdio_cmd53_4byte = cmd53_4byte_mode; - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_sdio_hw_info_88xx() - info sdio hw info - * @pHalmac_adapter : the adapter of halmac - * @HALMAC_SDIO_CMD53_4BYTE_MODE : - * clock_speed : sdio bus clock. Unit -> MHz - * spec_ver : sdio spec version - * Author : Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_sdio_hw_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_SDIO_HW_INFO pSdio_hw_info -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_sdio_hw_info_88xx ==========>\n"); - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - if (pHalmac_adapter->halmac_interface != HALMAC_INTERFACE_SDIO) - return HALMAC_RET_WRONG_INTF; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]SDIO hw clock : %d, spec : %d\n", pSdio_hw_info->clock_speed, pSdio_hw_info->spec_ver); - - if (pSdio_hw_info->clock_speed > HALMAC_SDIO_CLOCK_SPEED_MAX_88XX) - return HALMAC_RET_SDIO_CLOCK_ERR; - - if (pSdio_hw_info->clock_speed > HALMAC_SDIO_CLK_THRESHOLD_88XX) - pHalmac_adapter->sdio_hw_info.io_hi_speed_flag = 1; - - pHalmac_adapter->sdio_hw_info.clock_speed = pSdio_hw_info->clock_speed; - pHalmac_adapter->sdio_hw_info.spec_ver = pSdio_hw_info->spec_ver; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_sdio_hw_info_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h b/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h deleted file mode 100644 index 06885a8..0000000 --- a/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h +++ /dev/null @@ -1,133 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_API_88XX_SDIO_H_ -#define _HALMAC_API_88XX_SDIO_H_ - -#include "../halmac_2_platform.h" -#include "../halmac_type.h" - -HALMAC_RET_STATUS -halmac_init_sdio_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_deinit_sdio_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_cfg_rx_aggregation_88xx_sdio( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg -); - -u8 -halmac_reg_read_8_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -); - -HALMAC_RET_STATUS -halmac_reg_write_8_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u8 halmac_data -); - -u16 -halmac_reg_read_16_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -); - -HALMAC_RET_STATUS -halmac_reg_write_16_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u16 halmac_data -); - -u32 -halmac_reg_read_32_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -); - -HALMAC_RET_STATUS -halmac_reg_write_32_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u32 halmac_data -); - -HALMAC_RET_STATUS -halmac_get_sdio_tx_addr_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *halmac_buf, - IN u32 halmac_size, - OUT u32 *pcmd53_addr -); - -HALMAC_RET_STATUS -halmac_cfg_tx_agg_align_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable, - IN u16 align_size -); - -HALMAC_RET_STATUS -halmac_cfg_tx_agg_align_sdio_not_support_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable, - IN u16 align_size -); - -HALMAC_RET_STATUS -halmac_tx_allowed_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHalmac_buf, - IN u32 halmac_size -); - -u32 -halmac_reg_read_indirect_32_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -); - - -HALMAC_RET_STATUS -halmac_sdio_cmd53_4byte_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_SDIO_CMD53_4BYTE_MODE cmd53_4byte_mode -); - -u8 -halmac_reg_read_nbyte_sdio_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u32 halmac_size, - OUT u8 *halmac_data -); - -HALMAC_RET_STATUS -halmac_sdio_hw_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_SDIO_HW_INFO pSdio_hw_info -); - -#endif/* _HALMAC_API_88XX_SDIO_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c b/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c deleted file mode 100644 index 5b70718..0000000 --- a/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c +++ /dev/null @@ -1,566 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#include "halmac_88xx_cfg.h" - -/** - * halmac_init_usb_cfg_88xx() - init USB - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_init_usb_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - u8 value8 = 0; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_usb_cfg_88xx ==========>\n"); - - value8 |= (BIT_DMA_MODE | (0x3 << BIT_SHIFT_BURST_CNT)); /* burst number = 4 */ - - if (PLATFORM_REG_READ_8(pDriver_adapter, REG_SYS_CFG2 + 3) == 0x20) { /* usb3.0 */ - value8 |= (HALMAC_USB_BURST_SIZE_3_0 << BIT_SHIFT_BURST_SIZE); - } else { - if ((PLATFORM_REG_READ_8(pDriver_adapter, REG_USB_USBSTAT) & 0x3) == 0x1) /* usb2.0 */ - value8 |= HALMAC_USB_BURST_SIZE_2_0_HSPEED << BIT_SHIFT_BURST_SIZE; - else /* usb1.1 */ - value8 |= HALMAC_USB_BURST_SIZE_2_0_FSPEED << BIT_SHIFT_BURST_SIZE; - } - - PLATFORM_REG_WRITE_8(pDriver_adapter, REG_RXDMA_MODE, value8); - PLATFORM_REG_WRITE_16(pDriver_adapter, REG_TXDMA_OFFSET_CHK, PLATFORM_REG_READ_16(pDriver_adapter, REG_TXDMA_OFFSET_CHK) | BIT_DROP_DATA_EN); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_usb_cfg_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_deinit_usb_cfg_88xx() - deinit USB - * @pHalmac_adapter : the adapter of halmac - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_deinit_usb_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_usb_cfg_88xx ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_usb_cfg_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_rx_aggregation_88xx_usb() - config rx aggregation - * @pHalmac_adapter : the adapter of halmac - * @halmac_rx_agg_mode - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_rx_aggregation_88xx_usb( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg -) -{ - u8 dma_usb_agg; - u8 size = 0, timeout = 0, agg_enable = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_usb ==========>\n"); - - dma_usb_agg = HALMAC_REG_READ_8(pHalmac_adapter, REG_RXDMA_AGG_PG_TH + 3); - agg_enable = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP); - - switch (phalmac_rxagg_cfg->mode) { - case HALMAC_RX_AGG_MODE_NONE: - agg_enable &= ~BIT_RXDMA_AGG_EN; - break; - case HALMAC_RX_AGG_MODE_DMA: - agg_enable |= BIT_RXDMA_AGG_EN; - dma_usb_agg |= BIT(7); - break; - - case HALMAC_RX_AGG_MODE_USB: - agg_enable |= BIT_RXDMA_AGG_EN; - dma_usb_agg &= ~BIT(7); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_rx_aggregation_88xx_usb switch case not support\n"); - agg_enable &= ~BIT_RXDMA_AGG_EN; - break; - } - - if (phalmac_rxagg_cfg->threshold.drv_define == _FALSE) { - if (PLATFORM_REG_READ_8(pDriver_adapter, REG_SYS_CFG2 + 3) == 0x20) { - /* usb3.0 */ - size = 0x5; - timeout = 0xA; - } else { - /* usb2.0 */ - size = 0x5; - timeout = 0x20; - } - } else { - size = phalmac_rxagg_cfg->threshold.size; - timeout = phalmac_rxagg_cfg->threshold.timeout; - } - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP, agg_enable); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXDMA_AGG_PG_TH + 3, dma_usb_agg); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXDMA_AGG_PG_TH, (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1))); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_usb <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_reg_read_8_usb_88xx() - read 1byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -u8 -halmac_reg_read_8_usb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -) -{ - u8 value8; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_8_usb_88xx ==========>\n"); */ - - value8 = PLATFORM_REG_READ_8(pDriver_adapter, halmac_offset); - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_8_usb_88xx <==========\n"); */ - - return value8; -} - -/** - * halmac_reg_write_8_usb_88xx() - write 1byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * @halmac_data : register value - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_reg_write_8_usb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u8 halmac_data -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_8_usb_88xx ==========>\n"); */ - - PLATFORM_REG_WRITE_8(pDriver_adapter, halmac_offset, halmac_data); - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_8_usb_88xx <==========\n"); */ - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_reg_read_16_usb_88xx() - read 2byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -u16 -halmac_reg_read_16_usb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - union { - u16 word; - u8 byte[2]; - } value16 = { 0x0000 }; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_16_usb_88xx ==========>\n"); */ - - value16.word = PLATFORM_REG_READ_16(pDriver_adapter, halmac_offset); - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_16_usb_88xx <==========\n"); */ - - return value16.word; -} - -/** - * halmac_reg_write_16_usb_88xx() - write 2byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * @halmac_data : register value - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_reg_write_16_usb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u16 halmac_data -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_16_usb_88xx ==========>\n"); */ - - PLATFORM_REG_WRITE_16(pDriver_adapter, halmac_offset, halmac_data); - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_16_usb_88xx <==========\n"); */ - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_reg_read_32_usb_88xx() - read 4byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -u32 -halmac_reg_read_32_usb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - union { - u32 dword; - u8 byte[4]; - } value32 = { 0x00000000 }; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_32_usb_88xx ==========>\n"); */ - - value32.dword = PLATFORM_REG_READ_32(pDriver_adapter, halmac_offset); - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_32_usb_88xx <==========\n"); */ - - return value32.dword; -} - -/** - * halmac_reg_write_32_usb_88xx() - write 4byte register - * @pHalmac_adapter : the adapter of halmac - * @halmac_offset : register offset - * @halmac_data : register value - * Author : KaiYuan Chang/Ivan Lin - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_reg_write_32_usb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u32 halmac_data -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_32_usb_88xx ==========>\n"); */ - - PLATFORM_REG_WRITE_32(pDriver_adapter, halmac_offset, halmac_data); - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_32_usb_88xx <==========\n"); */ - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_set_bulkout_num_usb_88xx() - inform bulk-out num - * @pHalmac_adapter : the adapter of halmac - * @bulkout_num : usb bulk-out number - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_set_bulkout_num_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 bulkout_num -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE,"halmac_set_bulkout_num_88xx ==========>\n"); */ - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE,"bulkout_num = %d\n", bulkout_num); */ - - pHalmac_adapter->halmac_bulkout_num = bulkout_num; - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE,"halmac_set_bulkout_num_88xx <==========\n"); */ - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_get_usb_bulkout_id_usb_88xx() - get bulk out id for the TX packet - * @pHalmac_adapter : the adapter of halmac - * @halmac_buf : tx packet, include txdesc - * @halmac_size : tx packet size - * @bulkout_id : usb bulk-out id - * Author : KaiYuan Chang - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_get_usb_bulkout_id_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *halmac_buf, - IN u32 halmac_size, - OUT u8 *bulkout_id -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_QUEUE_SELECT queue_sel; - HALMAC_DMA_MAPPING dma_mapping; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_usb_bulkout_id_88xx ==========>\n"); - - if (halmac_buf == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buf is NULL!!\n"); - return HALMAC_RET_DATA_BUF_NULL; - } - - if (halmac_size == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_size is 0!!\n"); - return HALMAC_RET_DATA_SIZE_INCORRECT; - } - - queue_sel = (HALMAC_QUEUE_SELECT)GET_TX_DESC_QSEL(halmac_buf); - - switch (queue_sel) { - case HALMAC_QUEUE_SELECT_VO: - case HALMAC_QUEUE_SELECT_VO_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]; - break; - case HALMAC_QUEUE_SELECT_VI: - case HALMAC_QUEUE_SELECT_VI_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]; - break; - case HALMAC_QUEUE_SELECT_BE: - case HALMAC_QUEUE_SELECT_BE_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]; - break; - case HALMAC_QUEUE_SELECT_BK: - case HALMAC_QUEUE_SELECT_BK_V2: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]; - break; - case HALMAC_QUEUE_SELECT_MGNT: - dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]; - break; - case HALMAC_QUEUE_SELECT_HIGH: - case HALMAC_QUEUE_SELECT_BCN: - case HALMAC_QUEUE_SELECT_CMD: - dma_mapping = HALMAC_DMA_MAPPING_HIGH; - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Qsel is out of range\n"); - return HALMAC_RET_QSEL_INCORRECT; - } - - switch (dma_mapping) { - case HALMAC_DMA_MAPPING_HIGH: - *bulkout_id = 0; - break; - case HALMAC_DMA_MAPPING_NORMAL: - *bulkout_id = 1; - break; - case HALMAC_DMA_MAPPING_LOW: - *bulkout_id = 2; - break; - case HALMAC_DMA_MAPPING_EXTRA: - *bulkout_id = 3; - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "DmaMapping is out of range\n"); - return HALMAC_RET_DMA_MAP_INCORRECT; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_usb_bulkout_id_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -/** - * halmac_cfg_tx_agg_align_usb_88xx() -config sdio bus tx agg alignment - * @pHalmac_adapter : the adapter of halmac - * @enable : function enable(1)/disable(0) - * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11) - * Author : Soar Tu - * Return : HALMAC_RET_STATUS - * More details of status code can be found in prototype document - */ -HALMAC_RET_STATUS -halmac_cfg_tx_agg_align_usb_not_support_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable, - IN u16 align_size -) -{ - PHALMAC_API pHalmac_api; - VOID *pDriver_adapter = NULL; - - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; - - if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_API_INVALID; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_usb_not_support_88xx ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_usb_not_support_88xx not support\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_usb_not_support_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h b/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h deleted file mode 100644 index 36702c4..0000000 --- a/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h +++ /dev/null @@ -1,98 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_API_88XX_USB_H_ -#define _HALMAC_API_88XX_USB_H_ - -#include "../halmac_2_platform.h" -#include "../halmac_type.h" - -HALMAC_RET_STATUS -halmac_init_usb_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_deinit_usb_cfg_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_cfg_rx_aggregation_88xx_usb( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg -); - -u8 -halmac_reg_read_8_usb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -); - -HALMAC_RET_STATUS -halmac_reg_write_8_usb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u8 halmac_data -); - -u16 -halmac_reg_read_16_usb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -); - -HALMAC_RET_STATUS -halmac_reg_write_16_usb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u16 halmac_data -); - -u32 -halmac_reg_read_32_usb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset -); - -HALMAC_RET_STATUS -halmac_reg_write_32_usb_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 halmac_offset, - IN u32 halmac_data -); - -HALMAC_RET_STATUS -halmac_set_bulkout_num_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 bulkout_num -); - -HALMAC_RET_STATUS -halmac_get_usb_bulkout_id_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *halmac_buf, - IN u32 halmac_size, - OUT u8 *bulkout_id -); - -HALMAC_RET_STATUS -halmac_cfg_tx_agg_align_usb_not_support_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable, - IN u16 align_size -); - -#endif/* _HALMAC_API_88XX_USB_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_func_88xx.c b/hal/halmac/halmac_88xx/halmac_func_88xx.c deleted file mode 100644 index 55a6b07..0000000 --- a/hal/halmac/halmac_88xx/halmac_func_88xx.c +++ /dev/null @@ -1,4100 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#include "halmac_88xx_cfg.h" - -static HALMAC_RET_STATUS -halmac_dump_efuse_fw_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -static HALMAC_RET_STATUS -halmac_dump_efuse_drv_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -static HALMAC_RET_STATUS -halmac_update_eeprom_mask_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - INOUT PHALMAC_PG_EFUSE_INFO pPg_efuse_info, - OUT u8 *pEeprom_mask_updated -); - -static HALMAC_RET_STATUS -halmac_check_efuse_enough_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, - IN u8 *pEeprom_mask_updated -); - -static HALMAC_RET_STATUS -halmac_program_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, - IN u8 *pEeprom_mask_updated -); - -static HALMAC_RET_STATUS -halmac_pwr_sub_seq_parer_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 cut, - IN u8 fab, - IN u8 intf, - IN PHALMAC_WLAN_PWR_CFG pPwr_sub_seq_cfg -); - -static HALMAC_RET_STATUS -halmac_parse_c2h_debug_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - -static HALMAC_RET_STATUS -halmac_parse_scan_status_rpt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - -static HALMAC_RET_STATUS -halmac_parse_psd_data_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - -static HALMAC_RET_STATUS -halmac_parse_efuse_data_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - -static HALMAC_RET_STATUS -halmac_enqueue_para_buff_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PHY_PARAMETER_INFO para_info, - IN u8 *pCurr_buff_wptr, - OUT u8 *pEnd_cmd -); - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_phy_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_cfg_para_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - -static HALMAC_RET_STATUS -halmac_gen_cfg_para_h2c_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pH2c_buff -); - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_update_packet_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_update_datapack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_run_datapack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_channel_switch_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_iqk_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_power_tracking_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -); - -VOID -halmac_init_offload_feature_state_machine_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - PHALMAC_STATE pState = &pHalmac_adapter->halmac_state; - - pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE; - pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->efuse_state_set.seq_num = pHalmac_adapter->h2c_packet_seq; - - pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE; - pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->cfg_para_state_set.seq_num = pHalmac_adapter->h2c_packet_seq; - - pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE; - pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->scan_state_set.seq_num = pHalmac_adapter->h2c_packet_seq; - - pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->update_packet_set.seq_num = pHalmac_adapter->h2c_packet_seq; - - pState->iqk_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->iqk_set.seq_num = pHalmac_adapter->h2c_packet_seq; - - pState->power_tracking_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->power_tracking_set.seq_num = pHalmac_adapter->h2c_packet_seq; - - pState->psd_set.process_status = HALMAC_CMD_PROCESS_IDLE; - pState->psd_set.seq_num = pHalmac_adapter->h2c_packet_seq; - pState->psd_set.data_size = 0; - pState->psd_set.segment_size = 0; - pState->psd_set.pData = NULL; -} - -HALMAC_RET_STATUS -halmac_dump_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_EFUSE_READ_CFG cfg -) -{ - u32 chk_h2c_init; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.efuse_state_set.process_status; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - *pProcess_status = HALMAC_CMD_PROCESS_SENDING; - - if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - if (cfg == HALMAC_EFUSE_R_AUTO) { - chk_h2c_init = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_PKT_READADDR); - if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state || 0 == chk_h2c_init) - status = halmac_dump_efuse_drv_88xx(pHalmac_adapter); - else - status = halmac_dump_efuse_fw_88xx(pHalmac_adapter); - } else if (cfg == HALMAC_EFUSE_R_FW) { - status = halmac_dump_efuse_fw_88xx(pHalmac_adapter); - } else { - status = halmac_dump_efuse_drv_88xx(pHalmac_adapter); - } - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_efuse error = %x\n", status); - return status; - } - - return status; -} - -HALMAC_RET_STATUS -halmac_func_read_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 offset, - IN u32 size, - OUT u8 *pEfuse_map -) -{ - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - if (pEfuse_map == NULL) { - PLATFORM_MSG_PRINT(pHalmac_adapter->pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Malloc for dump efuse map error\n"); - return HALMAC_RET_NULL_POINTER; - } - - if (pHalmac_adapter->hal_efuse_map_valid == _TRUE) - PLATFORM_RTL_MEMCPY(pDriver_adapter, pEfuse_map, pHalmac_adapter->pHalEfuse_map + offset, size); - else - if (halmac_read_hw_efuse_88xx(pHalmac_adapter, offset, size, pEfuse_map) != HALMAC_RET_SUCCESS) - return HALMAC_RET_EFUSE_R_FAIL; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_read_hw_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 offset, - IN u32 size, - OUT u8 *pEfuse_map -) -{ - u8 value8; - u32 value32; - u32 address; - u32 tmp32, counter; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - /* Read efuse no need 2.5V LDO */ - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3); - if (value8 & BIT(7)) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(value8 & ~(BIT(7)))); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL); - - for (address = offset; address < offset + size; address++) { - value32 = value32 & ~((BIT_MASK_EF_DATA) | (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)); - value32 = value32 | ((address & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EFUSE_CTRL, value32 & (~BIT_EF_FLAG)); - - counter = 1000000; - do { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 1); - tmp32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL); - counter--; - if (counter == 0) { - PLATFORM_MSG_PRINT(pHalmac_adapter->pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "HALMAC_RET_EFUSE_R_FAIL\n"); - return HALMAC_RET_EFUSE_R_FAIL; - } - } while ((tmp32 & BIT_EF_FLAG) == 0); - - *(pEfuse_map + address - offset) = (u8)(tmp32 & BIT_MASK_EF_DATA); - } - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_dump_efuse_drv_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u8 *pEfuse_map = NULL; - u32 efuse_size; - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - efuse_size = pHalmac_adapter->hw_config_info.efuse_size; - - if (pHalmac_adapter->pHalEfuse_map == NULL) { - pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); - if (pHalmac_adapter->pHalEfuse_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate efuse map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - } - - if (pHalmac_adapter->hal_efuse_map_valid == _FALSE) { - pEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); - if (pEfuse_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local efuse map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - - if (halmac_read_hw_efuse_88xx(pHalmac_adapter, 0, efuse_size, pEfuse_map) != HALMAC_RET_SUCCESS) { - PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); - return HALMAC_RET_EFUSE_R_FAIL; - } - - PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pEfuse_map, efuse_size); - pHalmac_adapter->hal_efuse_map_valid = _TRUE; - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - - PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); - } - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_dump_efuse_fw_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; - u16 h2c_seq_mum = 0; - VOID *pDriver_adapter = NULL; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - h2c_header_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE; - h2c_header_info.content_size = 0; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - pHalmac_adapter->halmac_state.efuse_state_set.seq_num = h2c_seq_mum; - - if (pHalmac_adapter->pHalEfuse_map == NULL) { - pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pHalmac_adapter->hw_config_info.efuse_size); - if (pHalmac_adapter->pHalEfuse_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac allocate efuse map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - } - - if (pHalmac_adapter->hal_efuse_map_valid == _FALSE) { - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_read_efuse_fw Fail = %x!!\n", status); - halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE); - return status; - } - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_func_write_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 offset, - IN u8 value -) -{ - const u8 wite_protect_code = 0x69; - u32 value32, tmp32, counter; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - u8 value_read = 0; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - pHalmac_adapter->hal_efuse_map_valid = _FALSE; - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PMC_DBG_CTRL2 + 3, wite_protect_code); - - /* Enable 2.5V LDO */ - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3) | BIT(7))); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL); - value32 = value32 & ~((BIT_MASK_EF_DATA) | (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)); - value32 = value32 | ((offset & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) | (value & BIT_MASK_EF_DATA); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EFUSE_CTRL, value32 | BIT_EF_FLAG); - - counter = 1000000; - do { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 1); - tmp32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL); - counter--; - if (counter == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_write_efuse Fail !!\n"); - return HALMAC_RET_EFUSE_W_FAIL; - } - } while ((tmp32 & BIT_EF_FLAG) == BIT_EF_FLAG); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PMC_DBG_CTRL2 + 3, 0x00); - - /* Disable 2.5V LDO */ - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3) & ~(BIT(7)))); - - if (pHalmac_adapter->efuse_auto_check_en == 1) { - if (halmac_read_hw_efuse_88xx(pHalmac_adapter, offset, 1, &value_read) != HALMAC_RET_SUCCESS) - return HALMAC_RET_EFUSE_R_FAIL; - if (value_read != value) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_write_efuse Fail: result 0x%X != write value 0x%X !!\n", value_read, value); - return HALMAC_RET_EFUSE_W_FAIL; - } - } - - return HALMAC_RET_SUCCESS; -} - - -HALMAC_RET_STATUS -halmac_func_switch_efuse_bank_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_EFUSE_BANK efuse_bank -) -{ - u8 reg_value; - PHALMAC_API pHalmac_api; - - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_BUSY) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - reg_value = HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1); - - if (efuse_bank == (reg_value & (BIT(0) | BIT(1)))) - return HALMAC_RET_SUCCESS; - - reg_value &= ~(BIT(0) | BIT(1)); - reg_value |= efuse_bank; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1, reg_value); - - if ((HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1) & (BIT(0) | BIT(1))) != efuse_bank) - return HALMAC_RET_SWITCH_EFUSE_BANK_FAIL; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_eeprom_parser_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pPhysical_efuse_map, - OUT u8 *pLogical_efuse_map -) -{ - u8 j; - u8 value8; - u8 block_index; - u8 valid_word_enable, word_enable; - u8 efuse_read_header, efuse_read_header2 = 0; - u32 eeprom_index; - u32 efuse_index = 0; - u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_RTL_MEMSET(pDriver_adapter, pLogical_efuse_map, 0xFF, eeprom_size); - - do { - value8 = *(pPhysical_efuse_map + efuse_index); - efuse_read_header = value8; - - if ((efuse_read_header & 0x1f) == 0x0f) { - efuse_index++; - value8 = *(pPhysical_efuse_map + efuse_index); - efuse_read_header2 = value8; - block_index = ((efuse_read_header2 & 0xF0) >> 1) | ((efuse_read_header >> 5) & 0x07); - word_enable = efuse_read_header2 & 0x0F; - } else { - block_index = (efuse_read_header & 0xF0) >> 4; - word_enable = efuse_read_header & 0x0F; - } - - if (efuse_read_header == 0xff) - break; - - efuse_index++; - - if (efuse_index >= pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - 1) - return HALMAC_RET_EEPROM_PARSING_FAIL; - - for (j = 0; j < 4; j++) { - valid_word_enable = (u8)((~(word_enable >> j)) & BIT(0)); - if (valid_word_enable == 1) { - eeprom_index = (block_index << 3) + (j << 1); - - if ((eeprom_index + 1) > eeprom_size) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM addr exceeds eeprom_size:0x%X, at eFuse 0x%X\n", eeprom_size, efuse_index - 1); - if ((efuse_read_header & 0x1f) == 0x0f) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM header: 0x%X, 0x%X,\n", efuse_read_header, efuse_read_header2); - else - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM header: 0x%X,\n", efuse_read_header); - - return HALMAC_RET_EEPROM_PARSING_FAIL; - } - - value8 = *(pPhysical_efuse_map + efuse_index); - *(pLogical_efuse_map + eeprom_index) = value8; - - eeprom_index++; - efuse_index++; - - if (efuse_index > pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - 1) - return HALMAC_RET_EEPROM_PARSING_FAIL; - - value8 = *(pPhysical_efuse_map + efuse_index); - *(pLogical_efuse_map + eeprom_index) = value8; - - efuse_index++; - - if (efuse_index > pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX) - return HALMAC_RET_EEPROM_PARSING_FAIL; - } - } - } while (1); - - pHalmac_adapter->efuse_end = efuse_index; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_read_logical_efuse_map_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pMap -) -{ - u8 *pEfuse_map = NULL; - u32 efuse_size; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - efuse_size = pHalmac_adapter->hw_config_info.efuse_size; - - if (pHalmac_adapter->hal_efuse_map_valid == _FALSE) { - pEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); - if (pEfuse_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local efuse map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - - status = halmac_func_read_efuse_88xx(pHalmac_adapter, 0, efuse_size, pEfuse_map); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_read_efuse error = %x\n", status); - PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); - return status; - } - - if (pHalmac_adapter->pHalEfuse_map == NULL) { - pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); - if (pHalmac_adapter->pHalEfuse_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate efuse map Fail!!\n"); - PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); - return HALMAC_RET_MALLOC_FAIL; - } - } - - PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pEfuse_map, efuse_size); - pHalmac_adapter->hal_efuse_map_valid = _TRUE; - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - - PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); - } - - if (halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pMap) != HALMAC_RET_SUCCESS) - return HALMAC_RET_EEPROM_PARSING_FAIL; - - return status; -} - -HALMAC_RET_STATUS -halmac_func_write_logical_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 offset, - IN u8 value -) -{ - u8 pg_efuse_byte1, pg_efuse_byte2; - u8 pg_block, pg_block_index; - u8 pg_efuse_header, pg_efuse_header2; - u8 *pEeprom_map = NULL; - u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; - u32 efuse_end, pg_efuse_num; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); - if (pEeprom_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); - - status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_read_logical_efuse_map_88xx error = %x\n", status); - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - return status; - } - - if (*(pEeprom_map + offset) != value) { - efuse_end = pHalmac_adapter->efuse_end; - pg_block = (u8)(offset >> 3); - pg_block_index = (u8)((offset & (8 - 1)) >> 1); - - if (offset > 0x7f) { - pg_efuse_header = (((pg_block & 0x07) << 5) & 0xE0) | 0x0F; - pg_efuse_header2 = (u8)(((pg_block & 0x78) << 1) + ((0x1 << pg_block_index) ^ 0x0F)); - } else { - pg_efuse_header = (u8)((pg_block << 4) + ((0x01 << pg_block_index) ^ 0x0F)); - } - - if ((offset & 1) == 0) { - pg_efuse_byte1 = value; - pg_efuse_byte2 = *(pEeprom_map + offset + 1); - } else { - pg_efuse_byte1 = *(pEeprom_map + offset - 1); - pg_efuse_byte2 = value; - } - - if (offset > 0x7f) { - pg_efuse_num = 4; - if (pHalmac_adapter->hw_config_info.efuse_size <= (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX + pHalmac_adapter->efuse_end)) { - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - return HALMAC_RET_EFUSE_NOT_ENOUGH; - } - halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); - halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_header2); - halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 2, pg_efuse_byte1); - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 3, pg_efuse_byte2); - } else { - pg_efuse_num = 3; - if (pHalmac_adapter->hw_config_info.efuse_size <= (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX + pHalmac_adapter->efuse_end)) { - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - return HALMAC_RET_EFUSE_NOT_ENOUGH; - } - halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); - halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_byte1); - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 2, pg_efuse_byte2); - } - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_write_logical_efuse error = %x\n", status); - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - return status; - } - } - - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_func_pg_efuse_by_map_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, - IN HALMAC_EFUSE_READ_CFG cfg -) -{ - u8 *pEeprom_mask_updated = NULL; - u32 eeprom_mask_size = pHalmac_adapter->hw_config_info.eeprom_size >> 4; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pEeprom_mask_updated = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_mask_size); - if (pEeprom_mask_updated == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_mask_updated, 0x00, eeprom_mask_size); - - status = halmac_update_eeprom_mask_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_update_eeprom_mask_88xx error = %x\n", status); - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size); - return status; - } - - status = halmac_check_efuse_enough_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_check_efuse_enough_88xx error = %x\n", status); - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size); - return status; - } - - status = halmac_program_efuse_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_program_efuse_88xx error = %x\n", status); - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size); - return status; - } - - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size); - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_update_eeprom_mask_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - INOUT PHALMAC_PG_EFUSE_INFO pPg_efuse_info, - OUT u8 *pEeprom_mask_updated -) -{ - u8 *pEeprom_map = NULL; - u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; - u8 *pEeprom_map_pg, *pEeprom_mask; - u16 i, j; - u16 map_byte_offset, mask_byte_offset; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); - if (pEeprom_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); - - PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_mask_updated, 0x00, pPg_efuse_info->efuse_mask_size); - - status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - return status; - } - - pEeprom_map_pg = pPg_efuse_info->pEfuse_map; - pEeprom_mask = pPg_efuse_info->pEfuse_mask; - - - for (i = 0; i < pPg_efuse_info->efuse_mask_size; i++) - *(pEeprom_mask_updated + i) = *(pEeprom_mask + i); - - for (i = 0; i < pPg_efuse_info->efuse_map_size; i = i + 16) { - for (j = 0; j < 16; j = j + 2) { - map_byte_offset = i + j; - mask_byte_offset = i >> 4; - if (*(pEeprom_map_pg + map_byte_offset) == *(pEeprom_map + map_byte_offset)) { - if (*(pEeprom_map_pg + map_byte_offset + 1) == *(pEeprom_map + map_byte_offset + 1)) { - switch (j) { - case 0: - *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(4) ^ 0xFF); - break; - case 2: - *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(5) ^ 0xFF); - break; - case 4: - *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(6) ^ 0xFF); - break; - case 6: - *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(7) ^ 0xFF); - break; - case 8: - *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(0) ^ 0xFF); - break; - case 10: - *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(1) ^ 0xFF); - break; - case 12: - *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(2) ^ 0xFF); - break; - case 14: - *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(3) ^ 0xFF); - break; - default: - break; - } - } - } - } - } - - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - - return status; -} - -static HALMAC_RET_STATUS -halmac_check_efuse_enough_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, - IN u8 *pEeprom_mask_updated -) -{ - u8 pre_word_enb, word_enb; - u8 pg_efuse_header, pg_efuse_header2; - u8 pg_block; - u16 i, j; - u32 efuse_end; - u32 tmp_eeprom_offset, pg_efuse_num = 0; - - efuse_end = pHalmac_adapter->efuse_end; - - for (i = 0; i < pPg_efuse_info->efuse_map_size; i = i + 8) { - tmp_eeprom_offset = i; - - if ((tmp_eeprom_offset & 7) > 0) { - pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) & 0x0F); - word_enb = pre_word_enb ^ 0x0F; - } else { - pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) >> 4); - word_enb = pre_word_enb ^ 0x0F; - } - - pg_block = (u8)(tmp_eeprom_offset >> 3); - - if (pre_word_enb > 0) { - if (tmp_eeprom_offset > 0x7f) { - pg_efuse_header = (((pg_block & 0x07) << 5) & 0xE0) | 0x0F; - pg_efuse_header2 = (u8)(((pg_block & 0x78) << 1) + word_enb); - } else { - pg_efuse_header = (u8)((pg_block << 4) + word_enb); - } - - if (tmp_eeprom_offset > 0x7f) { - pg_efuse_num++; - pg_efuse_num++; - efuse_end = efuse_end + 2; - for (j = 0; j < 4; j++) { - if (((pre_word_enb >> j) & 0x1) > 0) { - pg_efuse_num++; - pg_efuse_num++; - efuse_end = efuse_end + 2; - } - } - } else { - pg_efuse_num++; - efuse_end = efuse_end + 1; - for (j = 0; j < 4; j++) { - if (((pre_word_enb >> j) & 0x1) > 0) { - pg_efuse_num++; - pg_efuse_num++; - efuse_end = efuse_end + 2; - } - } - } - } - } - - if (pHalmac_adapter->hw_config_info.efuse_size <= (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX + pHalmac_adapter->efuse_end)) - return HALMAC_RET_EFUSE_NOT_ENOUGH; - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_program_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, - IN u8 *pEeprom_mask_updated -) -{ - u8 pre_word_enb, word_enb; - u8 pg_efuse_header, pg_efuse_header2; - u8 pg_block; - u16 i, j; - u32 efuse_end; - u32 tmp_eeprom_offset; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - efuse_end = pHalmac_adapter->efuse_end; - - for (i = 0; i < pPg_efuse_info->efuse_map_size; i = i + 8) { - tmp_eeprom_offset = i; - - if (((tmp_eeprom_offset >> 3) & 1) > 0) { - pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) & 0x0F); - word_enb = pre_word_enb ^ 0x0F; - } else { - pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) >> 4); - word_enb = pre_word_enb ^ 0x0F; - } - - pg_block = (u8)(tmp_eeprom_offset >> 3); - - if (pre_word_enb > 0) { - if (tmp_eeprom_offset > 0x7f) { - pg_efuse_header = (((pg_block & 0x07) << 5) & 0xE0) | 0x0F; - pg_efuse_header2 = (u8)(((pg_block & 0x78) << 1) + word_enb); - } else { - pg_efuse_header = (u8)((pg_block << 4) + word_enb); - } - - if (tmp_eeprom_offset > 0x7f) { - halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_header2); - efuse_end = efuse_end + 2; - for (j = 0; j < 4; j++) { - if (((pre_word_enb >> j) & 0x1) > 0) { - halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1))); - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1) + 1)); - efuse_end = efuse_end + 2; - } - } - } else { - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); - efuse_end = efuse_end + 1; - for (j = 0; j < 4; j++) { - if (((pre_word_enb >> j) & 0x1) > 0) { - halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1))); - status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1) + 1)); - efuse_end = efuse_end + 2; - } - } - } - } - } - - return status; -} - -HALMAC_RET_STATUS -halmac_update_fw_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHamacl_fw, - IN u32 halmac_fw_size -) -{ - PHALMAC_FW_VERSION pFw_info = &pHalmac_adapter->fw_version; - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - pFw_info->version = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_VERSION_88XX))); - pFw_info->sub_version = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_SUBVERSION_88XX); - pFw_info->sub_index = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_SUBINDEX_88XX); - pFw_info->h2c_version = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX))); - pFw_info->build_time.month = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_MONTH_88XX); - pFw_info->build_time.date = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_DATE_88XX); - pFw_info->build_time.hour = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_HOUR_88XX); - pFw_info->build_time.min = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_MIN_88XX); - pFw_info->build_time.year = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_YEAR_88XX))); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "[TRACE]FW version : %X\n", pFw_info->version); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "[TRACE]FW sub version : %X\n", pFw_info->sub_version); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "[TRACE]FW sub index : %X\n", pFw_info->sub_index); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "[TRACE]FW build time : %d/%d/%d %d:%d\n", - pFw_info->build_time.year, pFw_info->build_time.month, - pFw_info->build_time.date, pFw_info->build_time.hour, - pFw_info->build_time.min); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_dlfw_to_mem_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pRam_code, - IN u32 dest, - IN u32 code_size -) -{ - u8 *pCode_ptr; - u8 first_part; - u32 mem_offset; - u32 pkt_size_tmp, send_pkt_size; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - pCode_ptr = pRam_code; - mem_offset = 0; - first_part = 1; - pkt_size_tmp = code_size; - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0CTRL, HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) | BIT_DDMACH0_RESET_CHKSUM_STS); - - while (pkt_size_tmp != 0) { - if (pkt_size_tmp >= pHalmac_adapter->max_download_size) - send_pkt_size = pHalmac_adapter->max_download_size; - else - send_pkt_size = pkt_size_tmp; - - if (halmac_send_fwpkt_88xx(pHalmac_adapter, pCode_ptr + mem_offset, send_pkt_size) != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_send_fwpkt_88xx fail!!"); - return HALMAC_RET_DLFW_FAIL; - } - - if (halmac_iddma_dlfw_88xx(pHalmac_adapter, HALMAC_OCPBASE_TXBUF_88XX + pHalmac_adapter->hw_config_info.txdesc_size, - dest + mem_offset, send_pkt_size, first_part) != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx fail!!"); - return HALMAC_RET_DLFW_FAIL; - } - - first_part = 0; - mem_offset += send_pkt_size; - pkt_size_tmp -= send_pkt_size; - } - - if (halmac_check_fw_chksum_88xx(pHalmac_adapter, dest) != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pHalmac_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_check_fw_chksum_88xx fail!!"); - return HALMAC_RET_DLFW_FAIL; - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_send_fwpkt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pRam_code, - IN u32 code_size -) -{ - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - if (halmac_download_rsvd_page_88xx(pHalmac_adapter, pRam_code, code_size) != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "PLATFORM_SEND_RSVD_PAGE 0 error!!\n"); - return HALMAC_RET_DL_RSVD_PAGE_FAIL; - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_iddma_dlfw_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 source, - IN u32 dest, - IN u32 length, - IN u8 first -) -{ - u32 counter; - u32 ch0_control = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN); - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - counter = HALMC_DDMA_POLLING_COUNT; - while (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { - counter--; - if (counter == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx error-1!!\n"); - return HALMAC_RET_DDMA_FAIL; - } - } - - ch0_control |= (length & BIT_MASK_DDMACH0_DLEN); - if (first == 0) - ch0_control |= BIT_DDMACH0_CHKSUM_CONT; - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0SA, source); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0DA, dest); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0CTRL, ch0_control); - - counter = HALMC_DDMA_POLLING_COUNT; - while (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { - counter--; - if (counter == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx error-2!!\n"); - return HALMAC_RET_DDMA_FAIL; - } - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_check_fw_chksum_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 memory_address -) -{ - u8 mcu_fw_ctrl; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - mcu_fw_ctrl = HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL); - - if (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) { - if (memory_address < HALMAC_OCPBASE_DMEM_88XX) { - mcu_fw_ctrl |= BIT_IMEM_DW_OK; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl & ~(BIT_IMEM_CHKSUM_OK))); - } else { - mcu_fw_ctrl |= BIT_DMEM_DW_OK; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl & ~(BIT_DMEM_CHKSUM_OK))); - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_check_fw_chksum_88xx error!!\n"); - - return HALMAC_RET_FW_CHECKSUM_FAIL; - } - - if (memory_address < HALMAC_OCPBASE_DMEM_88XX) { - mcu_fw_ctrl |= BIT_IMEM_DW_OK; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl | BIT_IMEM_CHKSUM_OK)); - } else { - mcu_fw_ctrl |= BIT_DMEM_DW_OK; - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl | BIT_DMEM_CHKSUM_OK)); - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_dlfw_end_flow_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u8 value8; - u32 counter; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TXDMA_STATUS, BIT(2)); - - /* Check IMEM & DMEM checksum is OK or not */ - if (0x50 == (HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & 0x50)) - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MCUFW_CTRL, (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) | BIT_FW_DW_RDY)); - else - return HALMAC_RET_DLFW_FAIL; - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & ~(BIT(0)))); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RSV_CTRL + 1); - value8 = (u8)(value8 | BIT(0)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RSV_CTRL + 1, value8); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1); - value8 = (u8)(value8 | BIT(2)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, value8); /* Release MCU reset */ - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Download Finish, Reset CPU\n"); - - counter = 10000; - while (HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) != 0xC078) { - if (counter == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Check 0x80 = 0xC078 fail\n"); - if (0xFAAAAA00 == (HALMAC_REG_READ_32(pHalmac_adapter, REG_FW_DBG7) & 0xFFFFFF00)) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Key fail\n"); - return HALMAC_RET_DLFW_FAIL; - } - counter--; - PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Check 0x80 = 0xC078 counter = %d\n", counter); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_free_dl_fw_end_flow_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u32 counter; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - counter = 100; - while (HALMAC_REG_READ_8(pHalmac_adapter, REG_HMETFR + 3) != 0) { - counter--; - if (counter == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]0x1CF != 0\n"); - return HALMAC_RET_DLFW_FAIL; - } - PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); - } - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_HMETFR + 3, ID_INFORM_DLEMEM_RDY); - - counter = 10000; - while (HALMAC_REG_READ_8(pHalmac_adapter, REG_C2HEVT_3 + 3) != ID_INFORM_DLEMEM_RDY) { - counter--; - if (counter == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]0x1AF != 0x80\n"); - return HALMAC_RET_DLFW_FAIL; - } - PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); - } - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_C2HEVT_3 + 3, 0); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_pwr_seq_parser_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 cut, - IN u8 fab, - IN u8 intf, - IN PHALMAC_WLAN_PWR_CFG *ppPwr_seq_cfg -) -{ - u32 seq_idx = 0; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - PHALMAC_WLAN_PWR_CFG pSeq_cmd; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - do { - pSeq_cmd = ppPwr_seq_cfg[seq_idx]; - - if (pSeq_cmd == NULL) - break; - - status = halmac_pwr_sub_seq_parer_88xx(pHalmac_adapter, cut, fab, intf, pSeq_cmd); - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[Err]pwr sub seq parser fail, status = 0x%X!\n", status); - return status; - } - - seq_idx++; - } while (1); - - return status; -} - -static HALMAC_RET_STATUS -halmac_pwr_sub_seq_parer_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 cut, - IN u8 fab, - IN u8 intf, - IN PHALMAC_WLAN_PWR_CFG pPwr_sub_seq_cfg -) -{ - u8 value, flag; - u8 polling_bit; - u32 offset; - u32 polling_count; - static u32 poll_to_static; - VOID *pDriver_adapter = NULL; - PHALMAC_WLAN_PWR_CFG pSub_seq_cmd; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - pSub_seq_cmd = pPwr_sub_seq_cfg; - - do { - if ((pSub_seq_cmd->interface_msk & intf) && (pSub_seq_cmd->fab_msk & fab) && (pSub_seq_cmd->cut_msk & cut)) { - switch (pSub_seq_cmd->cmd) { - case HALMAC_PWR_CMD_WRITE: - if (pSub_seq_cmd->base == HALMAC_PWR_BASEADDR_SDIO) - offset = pSub_seq_cmd->offset | SDIO_LOCAL_OFFSET; - else - offset = pSub_seq_cmd->offset; - - value = HALMAC_REG_READ_8(pHalmac_adapter, offset); - value = (u8)(value & (u8)(~(pSub_seq_cmd->msk))); - value = (u8)(value | (u8)(pSub_seq_cmd->value & pSub_seq_cmd->msk)); - - HALMAC_REG_WRITE_8(pHalmac_adapter, offset, value); - break; - case HALMAC_PWR_CMD_POLLING: - polling_bit = 0; - polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT; - flag = 0; - - - if (pSub_seq_cmd->base == HALMAC_PWR_BASEADDR_SDIO) - offset = pSub_seq_cmd->offset | SDIO_LOCAL_OFFSET; - else - offset = pSub_seq_cmd->offset; - - do { - polling_count--; - value = HALMAC_REG_READ_8(pHalmac_adapter, offset); - value = (u8)(value & pSub_seq_cmd->msk); - - if (value == (pSub_seq_cmd->value & pSub_seq_cmd->msk)) { - polling_bit = 1; - } else { - if (polling_count == 0) { - if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface && 0 == flag) { - /* For PCIE + USB package poll power bit timeout issue */ - poll_to_static++; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "[WARN]PCIE polling timeout : %d!!\n", poll_to_static); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_PW_CTRL) | BIT(3)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_PW_CTRL) & ~BIT(3)); - polling_bit = 0; - polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT; - flag = 1; - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd polling timeout!!\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd offset : %X!!\n", pSub_seq_cmd->offset); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd value : %X!!\n", pSub_seq_cmd->value); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd msk : %X!!\n", pSub_seq_cmd->msk); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Read offset = %X value = %X!!\n", offset, value); - return HALMAC_RET_PWRSEQ_POLLING_FAIL; - } - } else { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); - } - } - } while (!polling_bit); - break; - case HALMAC_PWR_CMD_DELAY: - if (pSub_seq_cmd->value == HALMAC_PWRSEQ_DELAY_US) - PLATFORM_RTL_DELAY_US(pDriver_adapter, pSub_seq_cmd->offset); - else - PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000 * pSub_seq_cmd->offset); - break; - case HALMAC_PWR_CMD_READ: - break; - case HALMAC_PWR_CMD_END: - return HALMAC_RET_SUCCESS; - default: - return HALMAC_RET_PWRSEQ_CMD_INCORRECT; - } - } - pSub_seq_cmd++; - } while (1); - - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_get_h2c_buff_free_space_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u32 hw_wptr, fw_rptr; - PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - hw_wptr = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_WR_ADDR; - fw_rptr = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_PKT_READADDR) & BIT_MASK_H2C_READ_ADDR; - - if (hw_wptr >= fw_rptr) - pHalmac_adapter->h2c_buf_free_space = pHalmac_adapter->h2c_buff_size - (hw_wptr - fw_rptr); - else - pHalmac_adapter->h2c_buf_free_space = fw_rptr - hw_wptr; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_send_h2c_pkt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHal_h2c_cmd, - IN u32 size, - IN u8 ack -) -{ - u32 counter = 100; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - while (pHalmac_adapter->h2c_buf_free_space <= HALMAC_H2C_CMD_SIZE_UNIT_88XX) { - halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter); - counter--; - if (counter == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "h2c free space is not enough!!\n"); - return HALMAC_RET_H2C_SPACE_FULL; - } - } - - /* Send TxDesc + H2C_CMD */ - if (PLATFORM_SEND_H2C_PKT(pDriver_adapter, pHal_h2c_cmd, size) == _FALSE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Send H2C_CMD pkt error!!\n"); - return HALMAC_RET_SEND_H2C_FAIL; - } - - pHalmac_adapter->h2c_buf_free_space -= HALMAC_H2C_CMD_SIZE_UNIT_88XX; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "H2C free space : %d\n", pHalmac_adapter->h2c_buf_free_space); - - return status; -} - -HALMAC_RET_STATUS -halmac_download_rsvd_page_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHal_buf, - IN u32 size -) -{ - u8 restore[3]; - u8 value8; - u32 counter; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (size == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Rsvd page packet size is zero!!\n"); - return HALMAC_RET_ZERO_LEN_RSVD_PACKET; - } - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1); - value8 = (u8)(value8 | BIT(7)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1, value8); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 1); - restore[0] = value8; - value8 = (u8)(value8 | BIT(0)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, value8); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL); - restore[1] = value8; - value8 = (u8)((value8 & ~(BIT(3))) | BIT(4)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, value8); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2); - restore[2] = value8; - value8 = (u8)(value8 & ~(BIT(6))); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8); - - if (PLATFORM_SEND_RSVD_PAGE(pDriver_adapter, pHal_buf, size) == _FALSE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "PLATFORM_SEND_RSVD_PAGE 1 error!!\n"); - status = HALMAC_RET_DL_RSVD_PAGE_FAIL; - } - - /* Check Bcn_Valid_Bit */ - counter = 1000; - while (!(HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1) & BIT(7))) { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); - counter--; - if (counter == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Polling Bcn_Valid_Fail error!!\n"); - status = HALMAC_RET_POLLING_BCN_VALID_FAIL; - break; - } - } - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1, (value8 | BIT(7))); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, restore[2]); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, restore[1]); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, restore[0]); - - return status; -} - -HALMAC_RET_STATUS -halmac_set_h2c_header_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u8 *pHal_h2c_hdr, - IN u16 *seq, - IN u8 ack -) -{ - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_h2c_header_88xx!!\n"); - - H2C_CMD_HEADER_SET_CATEGORY(pHal_h2c_hdr, 0x00); - H2C_CMD_HEADER_SET_TOTAL_LEN(pHal_h2c_hdr, 16); - - PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->h2c_seq_mutex); - H2C_CMD_HEADER_SET_SEQ_NUM(pHal_h2c_hdr, pHalmac_adapter->h2c_packet_seq); - *seq = pHalmac_adapter->h2c_packet_seq; - pHalmac_adapter->h2c_packet_seq++; - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->h2c_seq_mutex); - - if (ack == _TRUE) - H2C_CMD_HEADER_SET_ACK(pHal_h2c_hdr, _TRUE); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_set_fw_offload_h2c_header_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u8 *pHal_h2c_hdr, - IN PHALMAC_H2C_HEADER_INFO pH2c_header_info, - OUT u16 *pSeq_num -) -{ - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_fw_offload_h2c_header_88xx!!\n"); - - FW_OFFLOAD_H2C_SET_TOTAL_LEN(pHal_h2c_hdr, 8 + pH2c_header_info->content_size); - FW_OFFLOAD_H2C_SET_SUB_CMD_ID(pHal_h2c_hdr, pH2c_header_info->sub_cmd_id); - - FW_OFFLOAD_H2C_SET_CATEGORY(pHal_h2c_hdr, 0x01); - FW_OFFLOAD_H2C_SET_CMD_ID(pHal_h2c_hdr, 0xFF); - - PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->h2c_seq_mutex); - FW_OFFLOAD_H2C_SET_SEQ_NUM(pHal_h2c_hdr, pHalmac_adapter->h2c_packet_seq); - *pSeq_num = pHalmac_adapter->h2c_packet_seq; - pHalmac_adapter->h2c_packet_seq++; - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->h2c_seq_mutex); - - if (pH2c_header_info->ack == _TRUE) - FW_OFFLOAD_H2C_SET_ACK(pHal_h2c_hdr, _TRUE); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_func_send_original_h2c_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *original_h2c, - IN u16 *seq, - IN u8 ack -) -{ - u8 H2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u8 *pH2c_header, *pH2c_cmd; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c ==========>\n"); - - pH2c_header = H2c_buff; - pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX; - PLATFORM_RTL_MEMCPY(pDriver_adapter, pH2c_cmd, original_h2c, 8); /* Original H2C 8 byte */ - - halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, seq, ack); - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, H2c_buff, HALMAC_H2C_CMD_SIZE_88XX, ack); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_original_h2c Fail = %x!!\n", status); - return status; - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_send_h2c_update_packet_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_PACKET_ID pkt_id, - IN u8 *pkt, - IN u32 pkt_size -) -{ - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u16 h2c_seq_mum = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - - ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pkt, pkt_size); - - if (ret_status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", ret_status); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - return ret_status; - } - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - - UPDATE_PACKET_SET_SIZE(pH2c_buff, pkt_size + pHalmac_adapter->hw_config_info.txdesc_size); - UPDATE_PACKET_SET_PACKET_ID(pH2c_buff, pkt_id); - UPDATE_PACKET_SET_PACKET_LOC(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy); - - h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PACKET; - h2c_header_info.content_size = 8; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - pHalmac_adapter->halmac_state.update_packet_set.seq_num = h2c_seq_mum; - - ret_status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - - if (ret_status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_packet_88xx Fail = %x!!\n", ret_status); - halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_UPDATE_PACKET); - return ret_status; - } - - return ret_status; -} - -HALMAC_RET_STATUS -halmac_send_h2c_phy_parameter_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PHY_PARAMETER_INFO para_info, - IN u8 full_fifo -) -{ - u8 drv_trigger_send = _FALSE; - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u16 h2c_seq_mum = 0; - u32 info_size = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - PHALMAC_CONFIG_PARA_INFO pConfig_para_info; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - pConfig_para_info = &pHalmac_adapter->config_para_info; - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_phy_parameter_88xx!!\n"); */ - - if (pConfig_para_info->pCfg_para_buf == NULL) { - if (full_fifo == _TRUE) - pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX; - else - pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX; - - pConfig_para_info->pCfg_para_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pConfig_para_info->para_buf_size); - - if (pConfig_para_info->pCfg_para_buf != NULL) { - PLATFORM_RTL_MEMSET(pDriver_adapter, pConfig_para_info->pCfg_para_buf, 0x00, pConfig_para_info->para_buf_size); - pConfig_para_info->full_fifo_mode = full_fifo; - pConfig_para_info->pPara_buf_w = pConfig_para_info->pCfg_para_buf; - pConfig_para_info->para_num = 0; - pConfig_para_info->avai_para_buf_size = pConfig_para_info->para_buf_size; - pConfig_para_info->value_accumulation = 0; - pConfig_para_info->offset_accumulation = 0; - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Allocate pCfg_para_buf fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - } - - if (halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - halmac_enqueue_para_buff_88xx(pHalmac_adapter, para_info, pConfig_para_info->pPara_buf_w, &drv_trigger_send); - - if (para_info->cmd_id != HALMAC_PARAMETER_CMD_END) { - pConfig_para_info->para_num++; - pConfig_para_info->pPara_buf_w += HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; - pConfig_para_info->avai_para_buf_size = pConfig_para_info->avai_para_buf_size - HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; - } - - if (((pConfig_para_info->avai_para_buf_size - pHalmac_adapter->hw_config_info.txdesc_size) > HALMAC_FW_OFFLOAD_CMD_SIZE_88XX) && - (drv_trigger_send == _FALSE)) { - return HALMAC_RET_SUCCESS; - } - - if (pConfig_para_info->para_num == 0) { - PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size); - pConfig_para_info->pCfg_para_buf = NULL; - pConfig_para_info->pPara_buf_w = NULL; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "no cfg parameter element!!\n"); - - if (halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - return HALMAC_RET_SUCCESS; - } - - if (halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_SENDING; - - if (pConfig_para_info->full_fifo_mode == _TRUE) - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0); - else - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - - info_size = pConfig_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; - - status = halmac_download_rsvd_page_88xx(pHalmac_adapter, (u8 *)pConfig_para_info->pCfg_para_buf, info_size); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail!!\n"); - } else { - halmac_gen_cfg_para_h2c_88xx(pHalmac_adapter, pH2c_buff); - - h2c_header_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAMETER; - h2c_header_info.content_size = 4; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - - pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num = h2c_seq_mum; - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n"); - halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_CFG_PARA); - } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "config parameter time = %d\n", HALMAC_REG_READ_32(pHalmac_adapter, REG_FW_DBG6)); - } - - PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size); - pConfig_para_info->pCfg_para_buf = NULL; - pConfig_para_info->pPara_buf_w = NULL; - - /* Restore bcn head */ - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - - if (halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - if (drv_trigger_send == _FALSE) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Buffer full trigger sending H2C!!\n"); - return HALMAC_RET_PARA_SENDING; - } - - return status; -} - -static HALMAC_RET_STATUS -halmac_enqueue_para_buff_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PHY_PARAMETER_INFO para_info, - IN u8 *pCurr_buff_wptr, - OUT u8 *pEnd_cmd -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_CONFIG_PARA_INFO pConfig_para_info = &pHalmac_adapter->config_para_info; - - *pEnd_cmd = _FALSE; - - PHY_PARAMETER_INFO_SET_LENGTH(pCurr_buff_wptr, HALMAC_FW_OFFLOAD_CMD_SIZE_88XX); - PHY_PARAMETER_INFO_SET_IO_CMD(pCurr_buff_wptr, para_info->cmd_id); - - switch (para_info->cmd_id) { - case HALMAC_PARAMETER_CMD_BB_W8: - case HALMAC_PARAMETER_CMD_BB_W16: - case HALMAC_PARAMETER_CMD_BB_W32: - case HALMAC_PARAMETER_CMD_MAC_W8: - case HALMAC_PARAMETER_CMD_MAC_W16: - case HALMAC_PARAMETER_CMD_MAC_W32: - PHY_PARAMETER_INFO_SET_IO_ADDR(pCurr_buff_wptr, para_info->content.MAC_REG_W.offset); - PHY_PARAMETER_INFO_SET_DATA(pCurr_buff_wptr, para_info->content.MAC_REG_W.value); - PHY_PARAMETER_INFO_SET_MASK(pCurr_buff_wptr, para_info->content.MAC_REG_W.msk); - PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buff_wptr, para_info->content.MAC_REG_W.msk_en); - pConfig_para_info->value_accumulation += para_info->content.MAC_REG_W.value; - pConfig_para_info->offset_accumulation += para_info->content.MAC_REG_W.offset; - break; - case HALMAC_PARAMETER_CMD_RF_W: - PHY_PARAMETER_INFO_SET_RF_ADDR(pCurr_buff_wptr, para_info->content.RF_REG_W.offset); /*In rf register, the address is only 1 byte*/ - PHY_PARAMETER_INFO_SET_RF_PATH(pCurr_buff_wptr, para_info->content.RF_REG_W.rf_path); - PHY_PARAMETER_INFO_SET_DATA(pCurr_buff_wptr, para_info->content.RF_REG_W.value); - PHY_PARAMETER_INFO_SET_MASK(pCurr_buff_wptr, para_info->content.RF_REG_W.msk); - PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buff_wptr, para_info->content.RF_REG_W.msk_en); - pConfig_para_info->value_accumulation += para_info->content.RF_REG_W.value; - pConfig_para_info->offset_accumulation += (para_info->content.RF_REG_W.offset + (para_info->content.RF_REG_W.rf_path << 8)); - break; - case HALMAC_PARAMETER_CMD_DELAY_US: - case HALMAC_PARAMETER_CMD_DELAY_MS: - PHY_PARAMETER_INFO_SET_DELAY_VALUE(pCurr_buff_wptr, para_info->content.DELAY_TIME.delay_time); - break; - case HALMAC_PARAMETER_CMD_END: - *pEnd_cmd = _TRUE; - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, " halmac_send_h2c_phy_parameter_88xx illegal cmd_id!!\n"); - break; - } - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_gen_cfg_para_h2c_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pH2c_buff -) -{ - PHALMAC_CONFIG_PARA_INFO pConfig_para_info = &pHalmac_adapter->config_para_info; - - CFG_PARAMETER_SET_NUM(pH2c_buff, pConfig_para_info->para_num); - - if (pConfig_para_info->full_fifo_mode == _TRUE) { - CFG_PARAMETER_SET_INIT_CASE(pH2c_buff, 0x1); - CFG_PARAMETER_SET_PHY_PARAMETER_LOC(pH2c_buff, 0); - } else { - CFG_PARAMETER_SET_INIT_CASE(pH2c_buff, 0x0); - CFG_PARAMETER_SET_PHY_PARAMETER_LOC(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy); - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_send_h2c_run_datapack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DATA_TYPE halmac_data_type -) -{ - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u16 h2c_seq_mum = 0; - VOID *pDriver_adapter = NULL; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_run_datapack_88xx!!\n"); - - RUN_DATAPACK_SET_DATAPACK_ID(pH2c_buff, halmac_data_type); - - h2c_header_info.sub_cmd_id = SUB_CMD_ID_RUN_DATAPACK; - h2c_header_info.content_size = 4; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); - return status; - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_send_bt_coex_cmd_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pBt_buf, - IN u32 bt_size, - IN u8 ack -) -{ - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u16 h2c_seq_mum = 0; - VOID *pDriver_adapter = NULL; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_cmd_88xx!!\n"); - - PLATFORM_RTL_MEMCPY(pDriver_adapter, pH2c_buff + 8, pBt_buf, bt_size); - - h2c_header_info.sub_cmd_id = SUB_CMD_ID_BT_COEX; - h2c_header_info.content_size = (u16)bt_size; - h2c_header_info.ack = ack; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, ack); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); - return status; - } - - return HALMAC_RET_SUCCESS; -} - - -HALMAC_RET_STATUS -halmac_func_ctrl_ch_switch_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_CH_SWITCH_OPTION pCs_option -) -{ - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u16 h2c_seq_mum = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - HALMAC_CMD_PROCESS_STATUS *pProcess_status = &pHalmac_adapter->halmac_state.scan_state_set.process_status; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch!!\n"); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - *pProcess_status = HALMAC_CMD_PROCESS_SENDING; - - if (pCs_option->switch_en != 0) { - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - - status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.total_size); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", status); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - return status; - } - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); - } - - CHANNEL_SWITCH_SET_SWITCH_START(pH2c_buff, pCs_option->switch_en); - CHANNEL_SWITCH_SET_CHANNEL_NUM(pH2c_buff, pHalmac_adapter->ch_sw_info.ch_num); - CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy); - CHANNEL_SWITCH_SET_DEST_CH_EN(pH2c_buff, pCs_option->dest_ch_en); - CHANNEL_SWITCH_SET_DEST_CH(pH2c_buff, pCs_option->dest_ch); - CHANNEL_SWITCH_SET_PRI_CH_IDX(pH2c_buff, pCs_option->dest_pri_ch_idx); - CHANNEL_SWITCH_SET_ABSOLUTE_TIME(pH2c_buff, pCs_option->absolute_time_en); - CHANNEL_SWITCH_SET_TSF_LOW(pH2c_buff, pCs_option->tsf_low); - CHANNEL_SWITCH_SET_PERIODIC_OPTION(pH2c_buff, pCs_option->periodic_option); - CHANNEL_SWITCH_SET_NORMAL_CYCLE(pH2c_buff, pCs_option->normal_cycle); - CHANNEL_SWITCH_SET_NORMAL_PERIOD(pH2c_buff, pCs_option->normal_period); - CHANNEL_SWITCH_SET_SLOW_PERIOD(pH2c_buff, pCs_option->phase_2_period); - CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(pH2c_buff, pHalmac_adapter->ch_sw_info.total_size); - - h2c_header_info.sub_cmd_id = SUB_CMD_ID_CHANNEL_SWITCH; - h2c_header_info.content_size = 20; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - pHalmac_adapter->halmac_state.scan_state_set.seq_num = h2c_seq_mum; - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); - halmac_reset_feature_88xx(pHalmac_adapter, HALMAC_FEATURE_CHANNEL_SWITCH); - } - PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.buf_size); - pHalmac_adapter->ch_sw_info.ch_info_buf = NULL; - pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL; - pHalmac_adapter->ch_sw_info.extra_info_en = 0; - pHalmac_adapter->ch_sw_info.buf_size = 0; - pHalmac_adapter->ch_sw_info.avai_buf_size = 0; - pHalmac_adapter->ch_sw_info.total_size = 0; - pHalmac_adapter->ch_sw_info.ch_num = 0; - - if (halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_IDLE) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ERROR_STATE; - - return status; -} - -HALMAC_RET_STATUS -halmac_func_send_general_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_GENERAL_INFO pGeneral_info -) -{ - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u16 h2c_seq_mum = 0; - VOID *pDriver_adapter = NULL; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info!!\n"); - - GENERAL_INFO_SET_REF_TYPE(pH2c_buff, pGeneral_info->rfe_type); - GENERAL_INFO_SET_RF_TYPE(pH2c_buff, pGeneral_info->rf_type); - GENERAL_INFO_SET_FW_TX_BOUNDARY(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy); - - h2c_header_info.sub_cmd_id = SUB_CMD_ID_GENERAL_INFO; - h2c_header_info.content_size = 4; - h2c_header_info.ack = _FALSE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - - if (status != HALMAC_RET_SUCCESS) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); - - return status; -} - -HALMAC_RET_STATUS -halmac_send_h2c_update_bcn_parse_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_BCN_IE_INFO pBcn_ie_info -) -{ - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u16 h2c_seq_mum = 0; - VOID *pDriver_adapter = NULL; - HALMAC_H2C_HEADER_INFO h2c_header_info; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_update_bcn_parse_info_88xx!!\n"); - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(pH2c_buff, pBcn_ie_info->func_en); - UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(pH2c_buff, pBcn_ie_info->size_th); - UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(pH2c_buff, pBcn_ie_info->timeout); - - UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[0])); - UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[1])); - UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[2])); - UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[3])); - UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[4])); - - h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO; - h2c_header_info.content_size = 24; - h2c_header_info.ack = _TRUE; - halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail =%x !!\n", status); - return status; - } - - return status; -} - -HALMAC_RET_STATUS -halmac_send_h2c_ps_tuning_para_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; - u8 *pH2c_header, *pH2c_cmd; - u16 seq = 0; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_ps_tuning_para_88xx!!\n"); - - pH2c_header = pH2c_buff; - pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX; - - halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, &seq, _FALSE); - - status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _FALSE); - - if (status != HALMAC_RET_SUCCESS) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); - return status; - } - - return status; -} - -HALMAC_RET_STATUS -halmac_parse_c2h_packet_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *halmac_buf, - IN u32 halmac_size -) -{ - u8 c2h_cmd, c2h_sub_cmd_id; - u8 *pC2h_buf = halmac_buf + pHalmac_adapter->hw_config_info.rxdesc_size; - u32 c2h_size = halmac_size - pHalmac_adapter->hw_config_info.rxdesc_size; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_parse_c2h_packet_88xx!!\n"); */ - - c2h_cmd = (u8)C2H_HDR_GET_CMD_ID(pC2h_buf); - - /* FW offload C2H cmd is 0xFF */ - if (c2h_cmd != 0xFF) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H_PKT not for FwOffloadC2HFormat!!\n"); - return HALMAC_RET_C2H_NOT_HANDLED; - } - - /* Get C2H sub cmd ID */ - c2h_sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(pC2h_buf); - - switch (c2h_sub_cmd_id) { - case C2H_SUB_CMD_ID_C2H_DBG: - status = halmac_parse_c2h_debug_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - case C2H_SUB_CMD_ID_H2C_ACK_HDR: - status = halmac_parse_h2c_ack_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - case C2H_SUB_CMD_ID_BT_COEX_INFO: - status = HALMAC_RET_C2H_NOT_HANDLED; - break; - case C2H_SUB_CMD_ID_SCAN_STATUS_RPT: - status = halmac_parse_scan_status_rpt_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - case C2H_SUB_CMD_ID_PSD_DATA: - status = halmac_parse_psd_data_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - - case C2H_SUB_CMD_ID_EFUSE_DATA: - status = halmac_parse_efuse_data_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "c2h_sub_cmd_id switch case out of boundary!!\n"); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "[ERR]c2h pkt : %.8X %.8X!!\n", *(u32 *)pC2h_buf, *(u32 *)(pC2h_buf + 4)); - status = HALMAC_RET_C2H_NOT_HANDLED; - break; - } - - return status; -} - -static HALMAC_RET_STATUS -halmac_parse_c2h_debug_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - VOID *pDriver_adapter = NULL; - u8 *pC2h_buf_local = (u8 *)NULL; - u32 c2h_size_local = 0; - u8 dbg_content_length = 0; - u8 dbg_seq_num = 0; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pC2h_buf_local = pC2h_buf; - c2h_size_local = c2h_size; - - dbg_content_length = (u8)C2H_HDR_GET_LEN((u8 *)pC2h_buf_local); - - if (dbg_content_length > C2H_DBG_CONTENT_MAX_LENGTH) - return HALMAC_RET_SUCCESS; - - *(pC2h_buf_local + C2H_DBG_HEADER_LENGTH + dbg_content_length - 2) = '\n'; - dbg_seq_num = (u8)(*(pC2h_buf_local + C2H_DBG_HEADER_LENGTH)); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[RTKFW, SEQ=%d]: %s", dbg_seq_num, (char *)(pC2h_buf_local + C2H_DBG_HEADER_LENGTH + 1)); - - return HALMAC_RET_SUCCESS; -} - - -static HALMAC_RET_STATUS -halmac_parse_scan_status_rpt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - u8 h2c_return_code; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status; - - h2c_return_code = (u8)SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(pC2h_buf); - process_status = (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) ? HALMAC_CMD_PROCESS_DONE : HALMAC_CMD_PROCESS_ERROR; - - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, NULL, 0); - - pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]scan status : %X\n", process_status); - - return HALMAC_RET_SUCCESS; -} - - -static HALMAC_RET_STATUS -halmac_parse_psd_data_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - u8 segment_id = 0, segment_size = 0, h2c_seq = 0; - u16 total_size; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status; - PHALMAC_PSD_STATE_SET pPsd_set = &pHalmac_adapter->halmac_state.psd_set; - - h2c_seq = (u8)PSD_DATA_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pPsd_set->seq_num, h2c_seq); - if (h2c_seq != pPsd_set->seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pPsd_set->seq_num, h2c_seq); - return HALMAC_RET_SUCCESS; - } - - if (pPsd_set->process_status != HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); - return HALMAC_RET_SUCCESS; - } - - total_size = (u16)PSD_DATA_GET_TOTAL_SIZE(pC2h_buf); - segment_id = (u8)PSD_DATA_GET_SEGMENT_ID(pC2h_buf); - segment_size = (u8)PSD_DATA_GET_SEGMENT_SIZE(pC2h_buf); - pPsd_set->data_size = total_size; - - if (pPsd_set->pData == NULL) - pPsd_set->pData = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pPsd_set->data_size); - - if (segment_id == 0) - pPsd_set->segment_size = segment_size; - - PLATFORM_RTL_MEMCPY(pDriver_adapter, pPsd_set->pData + segment_id * pPsd_set->segment_size, pC2h_buf + HALMAC_C2H_DATA_OFFSET_88XX, segment_size); - - if (PSD_DATA_GET_END_SEGMENT(pC2h_buf) == _FALSE) - return HALMAC_RET_SUCCESS; - - process_status = HALMAC_CMD_PROCESS_DONE; - pPsd_set->process_status = process_status; - - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_PSD, process_status, pPsd_set->pData, pPsd_set->data_size); - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_parse_efuse_data_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - u8 segment_id = 0, segment_size = 0, h2c_seq = 0; - u8 *pEeprom_map = NULL; - u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; - u8 h2c_return_code = 0; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status; - - h2c_seq = (u8)EFUSE_DATA_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); - if (h2c_seq != pHalmac_adapter->halmac_state.efuse_state_set.seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); - return HALMAC_RET_SUCCESS; - } - - if (pHalmac_adapter->halmac_state.efuse_state_set.process_status != HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); - return HALMAC_RET_SUCCESS; - } - - segment_id = (u8)EFUSE_DATA_GET_SEGMENT_ID(pC2h_buf); - segment_size = (u8)EFUSE_DATA_GET_SEGMENT_SIZE(pC2h_buf); - if (segment_id == 0) - pHalmac_adapter->efuse_segment_size = segment_size; - - pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); - if (pEeprom_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); - - PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map + segment_id * pHalmac_adapter->efuse_segment_size, - pC2h_buf + HALMAC_C2H_DATA_OFFSET_88XX, segment_size); - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - - if (EFUSE_DATA_GET_END_SEGMENT(pC2h_buf) == _FALSE) { - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - return HALMAC_RET_SUCCESS; - } - - h2c_return_code = pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code; - - if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) { - process_status = HALMAC_CMD_PROCESS_DONE; - pHalmac_adapter->halmac_state.efuse_state_set.process_status = process_status; - - PLATFORM_MUTEX_LOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - pHalmac_adapter->hal_efuse_map_valid = _TRUE; - PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - - if (pHalmac_adapter->event_trigger.physical_efuse_map == 1) { - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, process_status, pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size); - pHalmac_adapter->event_trigger.physical_efuse_map = 0; - } - - if (pHalmac_adapter->event_trigger.logical_efuse_map == 1) { - if (halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map) != HALMAC_RET_SUCCESS) { - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - return HALMAC_RET_EEPROM_PARSING_FAIL; - } - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, process_status, pEeprom_map, eeprom_size); - pHalmac_adapter->event_trigger.logical_efuse_map = 0; - } - } else { - process_status = HALMAC_CMD_PROCESS_ERROR; - pHalmac_adapter->halmac_state.efuse_state_set.process_status = process_status; - - if (pHalmac_adapter->event_trigger.physical_efuse_map == 1) { - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, process_status, &pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code, 1); - pHalmac_adapter->event_trigger.physical_efuse_map = 0; - } - - if (pHalmac_adapter->event_trigger.logical_efuse_map == 1) { - if (halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map) != HALMAC_RET_SUCCESS) { - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - return HALMAC_RET_EEPROM_PARSING_FAIL; - } - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, process_status, &pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code, 1); - pHalmac_adapter->event_trigger.logical_efuse_map = 0; - } - } - - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - u8 h2c_cmd_id, h2c_sub_cmd_id; - u8 h2c_return_code; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Ack for C2H!!\n"); - - h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); - if (HALMAC_H2C_RETURN_SUCCESS != (HALMAC_H2C_RETURN_CODE)h2c_return_code) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H_PKT Status Error!! Status = %d\n", h2c_return_code); - - h2c_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(pC2h_buf); - - if (h2c_cmd_id != 0xFF) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "original h2c ack is not handled!!\n"); - status = HALMAC_RET_C2H_NOT_HANDLED; - } else { - h2c_sub_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(pC2h_buf); - - switch (h2c_sub_cmd_id) { - case H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK: - status = halmac_parse_h2c_ack_phy_efuse_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - case H2C_SUB_CMD_ID_CFG_PARAMETER_ACK: - status = halmac_parse_h2c_ack_cfg_para_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - case H2C_SUB_CMD_ID_UPDATE_PACKET_ACK: - status = halmac_parse_h2c_ack_update_packet_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - case H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK: - status = halmac_parse_h2c_ack_update_datapack_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - case H2C_SUB_CMD_ID_RUN_DATAPACK_ACK: - status = halmac_parse_h2c_ack_run_datapack_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - case H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK: - status = halmac_parse_h2c_ack_channel_switch_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - case H2C_SUB_CMD_ID_IQK_ACK: - status = halmac_parse_h2c_ack_iqk_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - case H2C_SUB_CMD_ID_POWER_TRACKING_ACK: - status = halmac_parse_h2c_ack_power_tracking_88xx(pHalmac_adapter, pC2h_buf, c2h_size); - break; - case H2C_SUB_CMD_ID_PSD_ACK: - break; - default: - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "h2c_sub_cmd_id switch case out of boundary!!\n"); - status = HALMAC_RET_C2H_NOT_HANDLED; - break; - } - } - - return status; -} - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_phy_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - u8 h2c_seq = 0; - u8 h2c_return_code; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); - if (h2c_seq != pHalmac_adapter->halmac_state.efuse_state_set.seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); - return HALMAC_RET_SUCCESS; - } - - if (pHalmac_adapter->halmac_state.efuse_state_set.process_status != HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); - return HALMAC_RET_SUCCESS; - } - - h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); - pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code = h2c_return_code; - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_cfg_para_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - u8 h2c_seq = 0; - u8 h2c_return_code; - u32 offset_accu = 0, value_accu = 0; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; - - h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num, h2c_seq); - if (h2c_seq != pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num, h2c_seq); - return HALMAC_RET_SUCCESS; - } - - if (pHalmac_adapter->halmac_state.cfg_para_state_set.process_status != HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n"); - return HALMAC_RET_SUCCESS; - } - - h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); - pHalmac_adapter->halmac_state.cfg_para_state_set.fw_return_code = h2c_return_code; - offset_accu = CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(pC2h_buf); - value_accu = CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(pC2h_buf); - - if ((offset_accu != pHalmac_adapter->config_para_info.offset_accumulation) || (value_accu != pHalmac_adapter->config_para_info.value_accumulation)) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[C2H]offset_accu : %x, value_accu : %x!!\n", offset_accu, value_accu); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[Adapter]offset_accu : %x, value_accu : %x!!\n", pHalmac_adapter->config_para_info.offset_accumulation, pHalmac_adapter->config_para_info.value_accumulation); - process_status = HALMAC_CMD_PROCESS_ERROR; - } - - if (((HALMAC_H2C_RETURN_CODE)h2c_return_code == HALMAC_H2C_RETURN_SUCCESS) && (process_status != HALMAC_CMD_PROCESS_ERROR)) { - process_status = HALMAC_CMD_PROCESS_DONE; - pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CFG_PARA, process_status, NULL, 0); - } else { - process_status = HALMAC_CMD_PROCESS_ERROR; - pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CFG_PARA, process_status, &pHalmac_adapter->halmac_state.cfg_para_state_set.fw_return_code, 1); - } - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_update_packet_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - u8 h2c_seq = 0; - u8 h2c_return_code; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status; - - h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.update_packet_set.seq_num, h2c_seq); - if (h2c_seq != pHalmac_adapter->halmac_state.update_packet_set.seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.update_packet_set.seq_num, h2c_seq); - return HALMAC_RET_SUCCESS; - } - - if (pHalmac_adapter->halmac_state.update_packet_set.process_status != HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); - return HALMAC_RET_SUCCESS; - } - - h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); - pHalmac_adapter->halmac_state.update_packet_set.fw_return_code = h2c_return_code; - - if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) { - process_status = HALMAC_CMD_PROCESS_DONE; - pHalmac_adapter->halmac_state.update_packet_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_PACKET, process_status, NULL, 0); - } else { - process_status = HALMAC_CMD_PROCESS_ERROR; - pHalmac_adapter->halmac_state.update_packet_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_PACKET, process_status, &pHalmac_adapter->halmac_state.update_packet_set.fw_return_code, 1); - } - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_update_datapack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; - - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_DATAPACK, process_status, NULL, 0); - - return HALMAC_RET_SUCCESS; -} - - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_run_datapack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; - - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_RUN_DATAPACK, process_status, NULL, 0); - - return HALMAC_RET_SUCCESS; -} - - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_channel_switch_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - u8 h2c_seq = 0; - u8 h2c_return_code; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status; - - h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.scan_state_set.seq_num, h2c_seq); - if (h2c_seq != pHalmac_adapter->halmac_state.scan_state_set.seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.scan_state_set.seq_num, h2c_seq); - return HALMAC_RET_SUCCESS; - } - - if (pHalmac_adapter->halmac_state.scan_state_set.process_status != HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); - return HALMAC_RET_SUCCESS; - } - - h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); - pHalmac_adapter->halmac_state.scan_state_set.fw_return_code = h2c_return_code; - - if ((HALMAC_H2C_RETURN_CODE)h2c_return_code == HALMAC_H2C_RETURN_SUCCESS) { - process_status = HALMAC_CMD_PROCESS_RCVD; - pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, NULL, 0); - } else { - process_status = HALMAC_CMD_PROCESS_ERROR; - pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, &pHalmac_adapter->halmac_state.scan_state_set.fw_return_code, 1); - } - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_iqk_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - u8 h2c_seq = 0; - u8 h2c_return_code; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status; - - h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq); - if (h2c_seq != pHalmac_adapter->halmac_state.iqk_set.seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq); - return HALMAC_RET_SUCCESS; - } - - if (pHalmac_adapter->halmac_state.iqk_set.process_status != HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); - return HALMAC_RET_SUCCESS; - } - - h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); - pHalmac_adapter->halmac_state.iqk_set.fw_return_code = h2c_return_code; - - if ((HALMAC_H2C_RETURN_CODE)h2c_return_code == HALMAC_H2C_RETURN_SUCCESS) { - process_status = HALMAC_CMD_PROCESS_DONE; - pHalmac_adapter->halmac_state.iqk_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_IQK, process_status, NULL, 0); - } else { - process_status = HALMAC_CMD_PROCESS_ERROR; - pHalmac_adapter->halmac_state.iqk_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_IQK, process_status, &pHalmac_adapter->halmac_state.iqk_set.fw_return_code, 1); - } - - return HALMAC_RET_SUCCESS; -} - -static HALMAC_RET_STATUS -halmac_parse_h2c_ack_power_tracking_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pC2h_buf, - IN u32 c2h_size -) -{ - u8 h2c_seq = 0; - u8 h2c_return_code; - VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; - HALMAC_CMD_PROCESS_STATUS process_status; - - h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.power_tracking_set.seq_num, h2c_seq); - if (h2c_seq != pHalmac_adapter->halmac_state.power_tracking_set.seq_num) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.power_tracking_set.seq_num, h2c_seq); - return HALMAC_RET_SUCCESS; - } - - if (pHalmac_adapter->halmac_state.power_tracking_set.process_status != HALMAC_CMD_PROCESS_SENDING) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); - return HALMAC_RET_SUCCESS; - } - - h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); - pHalmac_adapter->halmac_state.power_tracking_set.fw_return_code = h2c_return_code; - - if ((HALMAC_H2C_RETURN_CODE)h2c_return_code == HALMAC_H2C_RETURN_SUCCESS) { - process_status = HALMAC_CMD_PROCESS_DONE; - pHalmac_adapter->halmac_state.power_tracking_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_POWER_TRACKING, process_status, NULL, 0); - } else { - process_status = HALMAC_CMD_PROCESS_ERROR; - pHalmac_adapter->halmac_state.power_tracking_set.process_status = process_status; - PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_POWER_TRACKING, process_status, &pHalmac_adapter->halmac_state.power_tracking_set.fw_return_code, 1); - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_convert_to_sdio_bus_offset_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - INOUT u32 *halmac_offset -) -{ - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - switch ((*halmac_offset) & 0xFFFF0000) { - case WLAN_IOREG_OFFSET: - *halmac_offset = (HALMAC_SDIO_CMD_ADDR_MAC_REG << 13) | (*halmac_offset & HALMAC_WLAN_MAC_REG_MSK); - break; - case SDIO_LOCAL_OFFSET: - *halmac_offset = (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | (*halmac_offset & HALMAC_SDIO_LOCAL_MSK); - break; - default: - *halmac_offset = 0xFFFFFFFF; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Unknown base address!!\n"); - return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL; - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_update_sdio_free_page_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u32 free_page = 0, free_page2 = 0, free_page3 = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - PHALMAC_SDIO_FREE_SPACE pSdio_free_space; - u8 data[12] = {0}; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_sdio_free_page_88xx ==========>\n"); - - pSdio_free_space = &pHalmac_adapter->sdio_free_space; - - HALMAC_REG_SDIO_CMD53_READ_N(pHalmac_adapter, REG_SDIO_FREE_TXPG, 12, data); - - free_page = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24); - free_page2 = data[4] | (data[5] << 8) | (data[6] << 16) | (data[7] << 24); - free_page3 = data[8] | (data[9] << 8) | (data[10] << 16) | (data[11] << 24); - - pSdio_free_space->high_queue_number = (u16)BIT_GET_HIQ_FREEPG_V1(free_page); - pSdio_free_space->normal_queue_number = (u16)BIT_GET_MID_FREEPG_V1(free_page); - pSdio_free_space->low_queue_number = (u16)BIT_GET_LOW_FREEPG_V1(free_page2); - pSdio_free_space->public_queue_number = (u16)BIT_GET_PUB_FREEPG_V1(free_page2); - pSdio_free_space->extra_queue_number = (u16)BIT_GET_EXQ_FREEPG_V1(free_page3); - pSdio_free_space->ac_oqt_number = (u8)BIT_GET_AC_OQT_FREEPG_V1(free_page3); - pSdio_free_space->non_ac_oqt_number = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(free_page3); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_sdio_free_page_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_update_oqt_free_space_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - PHALMAC_SDIO_FREE_SPACE pSdio_free_space; - u8 value; - u32 oqt_free_page; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_update_oqt_free_space_88xx ==========>\n"); - - pSdio_free_space = &pHalmac_adapter->sdio_free_space; - - oqt_free_page = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_OQT_FREE_TXPG_V1); - pSdio_free_space->ac_oqt_number = (u8)BIT_GET_AC_OQT_FREEPG_V1(oqt_free_page); - pSdio_free_space->non_ac_oqt_number = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(oqt_free_page); - pSdio_free_space->ac_empty = 0; - if (pSdio_free_space->ac_oqt_number == HALMAC_OQT_ENTRY_AC_88XX) { - value = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPKT_EMPTY); - while (value > 0) { - value = value & (value - 1); - pSdio_free_space->ac_empty++; - }; - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "pSdio_free_space->ac_oqt_number %d != %d\n", - pSdio_free_space->ac_oqt_number, HALMAC_OQT_ENTRY_AC_88XX); - } - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_update_oqt_free_space_88xx <==========\n"); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_EFUSE_CMD_CONSTRUCT_STATE -halmac_query_efuse_curr_state_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - return pHalmac_adapter->halmac_state.efuse_state_set.efuse_cmd_construct_state; -} - -HALMAC_RET_STATUS -halmac_transition_efuse_state_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_EFUSE_CMD_CONSTRUCT_STATE dest_state -) -{ - PHALMAC_EFUSE_STATE_SET pEfuse_state = &pHalmac_adapter->halmac_state.efuse_state_set; - - if ((pEfuse_state->efuse_cmd_construct_state != HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) - && (pEfuse_state->efuse_cmd_construct_state != HALMAC_EFUSE_CMD_CONSTRUCT_BUSY) - && (pEfuse_state->efuse_cmd_construct_state != HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT)) - return HALMAC_RET_ERROR_STATE; - - if (pEfuse_state->efuse_cmd_construct_state == dest_state) - return HALMAC_RET_ERROR_STATE; - - if (dest_state == HALMAC_EFUSE_CMD_CONSTRUCT_BUSY) { - if (pEfuse_state->efuse_cmd_construct_state == HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT) - return HALMAC_RET_ERROR_STATE; - } else if (dest_state == HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT) { - if (pEfuse_state->efuse_cmd_construct_state == HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) - return HALMAC_RET_ERROR_STATE; - } - - pEfuse_state->efuse_cmd_construct_state = dest_state; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE -halmac_query_cfg_para_curr_state_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - return pHalmac_adapter->halmac_state.cfg_para_state_set.cfg_para_cmd_construct_state; -} - -HALMAC_RET_STATUS -halmac_transition_cfg_para_state_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE dest_state -) -{ - PHALMAC_CFG_PARA_STATE_SET pCfg_para = &pHalmac_adapter->halmac_state.cfg_para_state_set; - - if ((pCfg_para->cfg_para_cmd_construct_state != HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) && - (pCfg_para->cfg_para_cmd_construct_state != HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING) && - (pCfg_para->cfg_para_cmd_construct_state != HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT)) - return HALMAC_RET_ERROR_STATE; - - if (dest_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) { - if (pCfg_para->cfg_para_cmd_construct_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING) - return HALMAC_RET_ERROR_STATE; - } else if (dest_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING) { - if (pCfg_para->cfg_para_cmd_construct_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT) - return HALMAC_RET_ERROR_STATE; - } else if (dest_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT) { - if ((pCfg_para->cfg_para_cmd_construct_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) - || (pCfg_para->cfg_para_cmd_construct_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT)) - return HALMAC_RET_ERROR_STATE; - } - - pCfg_para->cfg_para_cmd_construct_state = dest_state; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_SCAN_CMD_CONSTRUCT_STATE -halmac_query_scan_curr_state_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - return pHalmac_adapter->halmac_state.scan_state_set.scan_cmd_construct_state; -} - -HALMAC_RET_STATUS -halmac_transition_scan_state_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_SCAN_CMD_CONSTRUCT_STATE dest_state -) -{ - PHALMAC_SCAN_STATE_SET pScan = &pHalmac_adapter->halmac_state.scan_state_set; - - if (pScan->scan_cmd_construct_state > HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) - return HALMAC_RET_ERROR_STATE; - - if (dest_state == HALMAC_SCAN_CMD_CONSTRUCT_IDLE) { - if ((pScan->scan_cmd_construct_state == HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) || - (pScan->scan_cmd_construct_state == HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING)) - return HALMAC_RET_ERROR_STATE; - } else if (dest_state == HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) { - if (pScan->scan_cmd_construct_state == HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) - return HALMAC_RET_ERROR_STATE; - } else if (dest_state == HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) { - if ((pScan->scan_cmd_construct_state == HALMAC_SCAN_CMD_CONSTRUCT_IDLE) || - (pScan->scan_cmd_construct_state == HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT)) - return HALMAC_RET_ERROR_STATE; - } else if (dest_state == HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) { - if ((pScan->scan_cmd_construct_state != HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) && - (pScan->scan_cmd_construct_state != HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED)) - return HALMAC_RET_ERROR_STATE; - } - - pScan->scan_cmd_construct_state = dest_state; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_query_cfg_para_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -) -{ - PHALMAC_CFG_PARA_STATE_SET pCfg_para_state_set = &pHalmac_adapter->halmac_state.cfg_para_state_set; - - *pProcess_status = pCfg_para_state_set->process_status; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_query_dump_physical_efuse_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_EFUSE_STATE_SET pEfuse_state_set = &pHalmac_adapter->halmac_state.efuse_state_set; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - *pProcess_status = pEfuse_state_set->process_status; - - if (data == NULL) - return HALMAC_RET_NULL_POINTER; - - if (size == NULL) - return HALMAC_RET_NULL_POINTER; - - if (*pProcess_status == HALMAC_CMD_PROCESS_DONE) { - if (*size < pHalmac_adapter->hw_config_info.efuse_size) { - *size = pHalmac_adapter->hw_config_info.efuse_size; - return HALMAC_RET_BUFFER_TOO_SMALL; - } - - *size = pHalmac_adapter->hw_config_info.efuse_size; - PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pHalmac_adapter->pHalEfuse_map, *size); - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_query_dump_logical_efuse_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -) -{ - u8 *pEeprom_map = NULL; - u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; - VOID *pDriver_adapter = NULL; - PHALMAC_EFUSE_STATE_SET pEfuse_state_set = &pHalmac_adapter->halmac_state.efuse_state_set; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - *pProcess_status = pEfuse_state_set->process_status; - - if (data == NULL) - return HALMAC_RET_NULL_POINTER; - - if (size == NULL) - return HALMAC_RET_NULL_POINTER; - - if (*pProcess_status == HALMAC_CMD_PROCESS_DONE) { - if (*size < eeprom_size) { - *size = eeprom_size; - return HALMAC_RET_BUFFER_TOO_SMALL; - } - - *size = eeprom_size; - - pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); - if (pEeprom_map == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); - - if (halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map) != HALMAC_RET_SUCCESS) { - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - return HALMAC_RET_EEPROM_PARSING_FAIL; - } - - PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pEeprom_map, *size); - - PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_query_channel_switch_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -) -{ - PHALMAC_SCAN_STATE_SET pScan_state_set = &pHalmac_adapter->halmac_state.scan_state_set; - - *pProcess_status = pScan_state_set->process_status; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_query_update_packet_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -) -{ - PHALMAC_UPDATE_PACKET_STATE_SET pUpdate_packet_set = &pHalmac_adapter->halmac_state.update_packet_set; - - *pProcess_status = pUpdate_packet_set->process_status; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_query_iqk_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -) -{ - PHALMAC_IQK_STATE_SET pIqk_set = &pHalmac_adapter->halmac_state.iqk_set; - - *pProcess_status = pIqk_set->process_status; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_query_power_tracking_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -) -{ - PHALMAC_POWER_TRACKING_STATE_SET pPower_tracking_state_set = &pHalmac_adapter->halmac_state.power_tracking_set; - - *pProcess_status = pPower_tracking_state_set->process_status; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_query_psd_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_PSD_STATE_SET pPsd_set = &pHalmac_adapter->halmac_state.psd_set; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - *pProcess_status = pPsd_set->process_status; - - if (data == NULL) - return HALMAC_RET_NULL_POINTER; - - if (size == NULL) - return HALMAC_RET_NULL_POINTER; - - if (*pProcess_status == HALMAC_CMD_PROCESS_DONE) { - if (*size < pPsd_set->data_size) { - *size = pPsd_set->data_size; - return HALMAC_RET_BUFFER_TOO_SMALL; - } - - *size = pPsd_set->data_size; - PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pPsd_set->pData, *size); - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_verify_io_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u8 value8, wvalue8; - u32 value32, value32_2, wvalue32; - u32 halmac_offset; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { - halmac_offset = REG_PAGE5_DUMMY; - if (0 == (halmac_offset & 0xFFFF0000)) - halmac_offset |= WLAN_IOREG_OFFSET; - - ret_status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset); - - /* Verify CMD52 R/W */ - wvalue8 = 0xab; - PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, wvalue8); - - value8 = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset); - - if (value8 != wvalue8) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd52 r/w fail write = %X read = %X\n", wvalue8, value8); - ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "cmd52 r/w ok\n"); - } - - /* Verify CMD53 R/W */ - PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, 0xaa); - PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 1, 0xbb); - PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 2, 0xcc); - PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 3, 0xdd); - - value32 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset); - - if (value32 != 0xddccbbaa) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd53 r fail : read = %X\n"); - ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "cmd53 r ok\n"); - } - - wvalue32 = 0x11223344; - PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, halmac_offset, wvalue32); - - value32 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset); - - if (value32 != wvalue32) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd53 w fail\n"); - ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "cmd53 w ok\n"); - } - - value32 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset + 2); /* value32 should be 0x33441122 */ - - wvalue32 = 0x11225566; - PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, halmac_offset, wvalue32); - - value32_2 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset + 2); /* value32 should be 0x55661122 */ - if (value32_2 == value32) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd52 is used for HAL_SDIO_CMD53_READ_32\n"); - ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "cmd53 is correctly used\n"); - } - } else { - wvalue32 = 0x77665511; - PLATFORM_REG_WRITE_32(pDriver_adapter, REG_PAGE5_DUMMY, wvalue32); - - value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_PAGE5_DUMMY); - if (value32 != wvalue32) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "reg rw\n"); - ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "reg rw ok\n"); - } - } - - return ret_status; -} - -HALMAC_RET_STATUS -halmac_verify_send_rsvd_page_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -) -{ - u8 *rsvd_buf = NULL; - u8 *rsvd_page = NULL; - u32 i; - u32 h2c_pkt_verify_size = 64, h2c_pkt_verify_payload = 0xab; - VOID *pDriver_adapter = NULL; - HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - rsvd_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, h2c_pkt_verify_size); - - if (rsvd_buf == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]rsvd buffer malloc fail!!\n"); - return HALMAC_RET_MALLOC_FAIL; - } - - PLATFORM_RTL_MEMSET(pDriver_adapter, rsvd_buf, (u8)h2c_pkt_verify_payload, h2c_pkt_verify_size); - - ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, rsvd_buf, h2c_pkt_verify_size); - - if (ret_status != HALMAC_RET_SUCCESS) { - PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size); - return ret_status; - } - - rsvd_page = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); - - if (rsvd_page == NULL) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]rsvd page malloc fail!!\n"); - PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size); - return HALMAC_RET_MALLOC_FAIL; - } - - PLATFORM_RTL_MEMSET(pDriver_adapter, rsvd_page, 0x00, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); - - ret_status = halmac_dump_fifo_88xx(pHalmac_adapter, HAL_FIFO_SEL_RSVD_PAGE, 0, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size, rsvd_page); - - if (ret_status != HALMAC_RET_SUCCESS) { - PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size); - PLATFORM_RTL_FREE(pDriver_adapter, rsvd_page, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); - return ret_status; - } - - for (i = 0; i < h2c_pkt_verify_size; i++) { - if (*(rsvd_buf + i) != *(rsvd_page + (i + pHalmac_adapter->hw_config_info.txdesc_size))) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]Compare RSVD page Fail\n"); - ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; - } - } - - PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size); - PLATFORM_RTL_FREE(pDriver_adapter, rsvd_page, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); - - return ret_status; -} - -VOID -halmac_power_save_cb_88xx( - IN VOID *CbData -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_ADAPTER pHalmac_adapter = (PHALMAC_ADAPTER)NULL; - - pHalmac_adapter = (PHALMAC_ADAPTER)CbData; - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_power_save_cb_88xx\n"); -} - -HALMAC_RET_STATUS -halmac_buffer_read_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 offset, - IN u32 size, - IN HAL_FIFO_SEL halmac_fifo_sel, - OUT u8 *pFifo_map -) -{ - u32 start_page, value_read; - u32 i, counter = 0, residue; - PHALMAC_API pHalmac_api; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (halmac_fifo_sel == HAL_FIFO_SEL_RSVD_PAGE) - offset = offset + (pHalmac_adapter->txff_allocation.rsvd_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_88XX); - - start_page = offset >> 12; - residue = offset & (4096 - 1); - - if ((halmac_fifo_sel == HAL_FIFO_SEL_TX) || (halmac_fifo_sel == HAL_FIFO_SEL_RSVD_PAGE)) - start_page += 0x780; - else if (halmac_fifo_sel == HAL_FIFO_SEL_RX) - start_page += 0x700; - else if (halmac_fifo_sel == HAL_FIFO_SEL_REPORT) - start_page += 0x660; - else if (halmac_fifo_sel == HAL_FIFO_SEL_LLT) - start_page += 0x650; - else if (halmac_fifo_sel == HAL_FIFO_SEL_RXBUF_FW) - start_page += 0x680; - else - return HALMAC_RET_NOT_SUPPORT; - - value_read = HALMAC_REG_READ_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL); - - do { - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL, (u16)(start_page | (value_read & 0xF000))); - - for (i = 0x8000 + residue; i <= 0x8FFF; i += 4) { - *(u32 *)(pFifo_map + counter) = HALMAC_REG_READ_32(pHalmac_adapter, i); - *(u32 *)(pFifo_map + counter) = rtk_le32_to_cpu(*(u32 *)(pFifo_map + counter)); - counter += 4; - if (size == counter) - goto HALMAC_BUF_READ_OK; - } - - residue = 0; - start_page++; - } while (1); - -HALMAC_BUF_READ_OK: - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL, (u16)value_read); - - return HALMAC_RET_SUCCESS; -} - -VOID -halmac_restore_mac_register_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_RESTORE_INFO pRestore_info, - IN u32 restore_num -) -{ - u8 value_length; - u32 i; - u32 mac_register; - u32 mac_value; - PHALMAC_API pHalmac_api; - PHALMAC_RESTORE_INFO pCurr_restore_info = pRestore_info; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - for (i = 0; i < restore_num; i++) { - mac_register = pCurr_restore_info->mac_register; - mac_value = pCurr_restore_info->value; - value_length = pCurr_restore_info->length; - - if (value_length == 1) - HALMAC_REG_WRITE_8(pHalmac_adapter, mac_register, (u8)mac_value); - else if (value_length == 2) - HALMAC_REG_WRITE_16(pHalmac_adapter, mac_register, (u16)mac_value); - else if (value_length == 4) - HALMAC_REG_WRITE_32(pHalmac_adapter, mac_register, mac_value); - - pCurr_restore_info++; - } -} - -HALMAC_RET_STATUS -halmac_set_usb_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_USB_MODE usb_mode -) -{ - u32 usb_temp; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - HALMAC_USB_MODE current_usb_mode; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - current_usb_mode = (HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2 + 3) == 0x20) ? HALMAC_USB_MODE_U3 : HALMAC_USB_MODE_U2; - - /*check if HW supports usb2_usb3 swtich*/ - usb_temp = HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL2); - if (_FALSE == (BIT_GET_USB23_SW_MODE_V1(usb_temp) | (usb_temp & BIT_USB3_USB2_TRANSITION))) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "HALMAC_HW_USB_MODE usb mode HW unsupport\n"); - return HALMAC_RET_USB2_3_SWITCH_UNSUPPORT; - } - - if (usb_mode == current_usb_mode) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "HALMAC_HW_USB_MODE usb mode unchange\n"); - return HALMAC_RET_USB_MODE_UNCHANGE; - } - - usb_temp &= ~(BIT_USB23_SW_MODE_V1(0x3)); - - if (usb_mode == HALMAC_USB_MODE_U2) { - /* usb3 to usb2 */ - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U2) | BIT_RSM_EN_V1); - } else { - /* usb2 to usb3 */ - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U3) | BIT_RSM_EN_V1); - } - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PAD_CTRL2 + 1, 4); /* set counter down timer 4x64 ms */ - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_16(pHalmac_adapter, REG_SYS_PW_CTRL) | BIT_APFM_OFFMAC); - PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL2) | BIT_NO_PDN_CHIPOFF_V1); - - return HALMAC_RET_SUCCESS; -} - -VOID -halmac_enable_bb_rf_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable -) -{ - u8 value8; - u32 value32; - PHALMAC_API pHalmac_api; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (enable == 1) { - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN); - value8 = value8 | BIT(0) | BIT(1); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN, value8); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RF_CTRL); - value8 = value8 | BIT(0) | BIT(1) | BIT(2); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RF_CTRL, value8); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WLRF1); - value32 = value32 | BIT(24) | BIT(25) | BIT(26); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WLRF1, value32); - } else { - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN); - value8 = value8 & (~(BIT(0) | BIT(1))); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN, value8); - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RF_CTRL); - value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2))); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RF_CTRL, value8); - - value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WLRF1); - value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26))); - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WLRF1, value32); - } -} - -VOID -halmac_config_sdio_tx_page_threshold_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_TX_PAGE_THRESHOLD_INFO pThreshold_info -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - u32 threshold = pThreshold_info->threshold; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_config_sdio_tx_page_threshold_88xx ==========>\n"); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]queue %d, threshold 0x%X\n", pThreshold_info->dma_queue_sel, threshold); - - if (pThreshold_info->enable == 1) { - threshold = BIT(31) | threshold; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]enable\n"); - } else { - threshold = ~(BIT(31)) & threshold; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]disable\n"); - } - - switch (pThreshold_info->dma_queue_sel) { - case HALMAC_MAP2_HQ: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT1, threshold); - break; - case HALMAC_MAP2_NQ: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT2, threshold); - break; - case HALMAC_MAP2_LQ: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT3, threshold); - break; - case HALMAC_MAP2_EXQ: - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT4, threshold); - break; - default: - break; - } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_config_sdio_tx_page_threshold_88xx <==========\n"); -} - -VOID -halmac_config_ampdu_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_AMPDU_CONFIG pAmpdu_config -) -{ - PHALMAC_API pHalmac_api; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PROT_MODE_CTRL + 2, pAmpdu_config->max_agg_num); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PROT_MODE_CTRL + 3, pAmpdu_config->max_agg_num); -} - -VOID -halmac_rx_shift_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable -) -{ - PHALMAC_API pHalmac_api; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (enable == 1) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP, HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP) | BIT(1)); - else - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP, HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP) & ~(BIT(1))); -} - -HALMAC_RET_STATUS -halmac_check_oqt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 tx_agg_num, - IN u8 *pHalmac_buf, - IN u8 macid_counter -) -{ - u32 counter = 10; - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - /*S0, S1 are not allowed to use, 0x4E4[0] should be 0. Soar 20160323*/ - /*no need to check non_ac_oqt_number. HI and MGQ blocked will cause protocal issue before H_OQT being full*/ - switch ((HALMAC_QUEUE_SELECT)GET_TX_DESC_QSEL(pHalmac_buf)) { - case HALMAC_QUEUE_SELECT_VO: - case HALMAC_QUEUE_SELECT_VO_V2: - case HALMAC_QUEUE_SELECT_VI: - case HALMAC_QUEUE_SELECT_VI_V2: - case HALMAC_QUEUE_SELECT_BE: - case HALMAC_QUEUE_SELECT_BE_V2: - case HALMAC_QUEUE_SELECT_BK: - case HALMAC_QUEUE_SELECT_BK_V2: - if (tx_agg_num > HALMAC_OQT_ENTRY_AC_88XX) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_WARN, "tx_agg_num %d > HALMAC_OQT_ENTRY_AC_88XX %d\n", tx_agg_num, HALMAC_OQT_ENTRY_AC_88XX); - counter = 10; - do { - if (pHalmac_adapter->sdio_free_space.ac_empty >= macid_counter) { - pHalmac_adapter->sdio_free_space.ac_empty -= macid_counter; - break; - } - - if (pHalmac_adapter->sdio_free_space.ac_oqt_number >= tx_agg_num) { - pHalmac_adapter->sdio_free_space.ac_empty = 0; - pHalmac_adapter->sdio_free_space.ac_oqt_number -= (u8)tx_agg_num; - break; - } - - halmac_update_oqt_free_space_88xx(pHalmac_adapter); - - counter--; - if (counter == 0) - return HALMAC_RET_OQT_NOT_ENOUGH; - } while (1); - break; - case HALMAC_QUEUE_SELECT_MGNT: - case HALMAC_QUEUE_SELECT_HIGH: - if (tx_agg_num > HALMAC_OQT_ENTRY_NOAC_88XX) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_WARN, "tx_agg_num %d > HALMAC_OQT_ENTRY_NOAC_88XX %d\n", tx_agg_num, HALMAC_OQT_ENTRY_NOAC_88XX); - counter = 10; - do { - if (pHalmac_adapter->sdio_free_space.non_ac_oqt_number >= tx_agg_num) { - pHalmac_adapter->sdio_free_space.non_ac_oqt_number -= (u8)tx_agg_num; - break; - } - - halmac_update_oqt_free_space_88xx(pHalmac_adapter); - - counter--; - if (counter == 0) - return HALMAC_RET_OQT_NOT_ENOUGH; - } while (1); - break; - default: - break; - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_rqpn_parser_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode, - IN PHALMAC_RQPN pRqpn_table -) -{ - u8 search_flag; - u32 i; - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - search_flag = 0; - for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) { - if (halmac_trx_mode == pRqpn_table[i].mode) { - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = pRqpn_table[i].dma_map_vo; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = pRqpn_table[i].dma_map_vi; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = pRqpn_table[i].dma_map_be; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = pRqpn_table[i].dma_map_bk; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = pRqpn_table[i].dma_map_mg; - pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = pRqpn_table[i].dma_map_hi; - search_flag = 1; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_rqpn_parser_88xx done\n"); - break; - } - } - - if (search_flag == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_RET_TRX_MODE_NOT_SUPPORT 1 switch case not support\n"); - return HALMAC_RET_TRX_MODE_NOT_SUPPORT; - } - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_pg_num_parser_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode, - IN PHALMAC_PG_NUM pPg_num_table -) -{ - u8 search_flag; - u16 HPQ_num = 0, LPQ_Nnum = 0, NPQ_num = 0, GAPQ_num = 0; - u16 EXPQ_num = 0, PUBQ_num = 0; - u32 i = 0; - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - search_flag = 0; - for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) { - if (halmac_trx_mode == pPg_num_table[i].mode) { - HPQ_num = pPg_num_table[i].hq_num; - LPQ_Nnum = pPg_num_table[i].lq_num; - NPQ_num = pPg_num_table[i].nq_num; - EXPQ_num = pPg_num_table[i].exq_num; - GAPQ_num = pPg_num_table[i].gap_num; - PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num; - search_flag = 1; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pg_num_parser_88xx done\n"); - break; - } - } - - if (search_flag == 0) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_RET_TRX_MODE_NOT_SUPPORT 1 switch case not support\n"); - return HALMAC_RET_TRX_MODE_NOT_SUPPORT; - } - - if (pHalmac_adapter->txff_allocation.ac_q_pg_num < HPQ_num + LPQ_Nnum + NPQ_num + EXPQ_num + GAPQ_num) - return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL; - - pHalmac_adapter->txff_allocation.high_queue_pg_num = HPQ_num; - pHalmac_adapter->txff_allocation.low_queue_pg_num = LPQ_Nnum; - pHalmac_adapter->txff_allocation.normal_queue_pg_num = NPQ_num; - pHalmac_adapter->txff_allocation.extra_queue_pg_num = EXPQ_num; - pHalmac_adapter->txff_allocation.pub_queue_pg_num = PUBQ_num; - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_parse_intf_phy_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_INTF_PHY_PARA pIntf_phy_para, - IN HALMAC_INTF_PHY_PLATFORM platform, - IN HAL_INTF_PHY intf_phy -) -{ - u16 value; - u16 curr_cut; - u16 offset; - u16 ip_sel; - PHALMAC_INTF_PHY_PARA pCurr_phy_para; - PHALMAC_API pHalmac_api; - VOID *pDriver_adapter = NULL; - u8 result = HALMAC_RET_SUCCESS; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - switch (pHalmac_adapter->chip_version) { - case HALMAC_CHIP_VER_A_CUT: - curr_cut = (u16)HALMAC_INTF_PHY_CUT_A; - break; - case HALMAC_CHIP_VER_B_CUT: - curr_cut = (u16)HALMAC_INTF_PHY_CUT_B; - break; - case HALMAC_CHIP_VER_C_CUT: - curr_cut = (u16)HALMAC_INTF_PHY_CUT_C; - break; - case HALMAC_CHIP_VER_D_CUT: - curr_cut = (u16)HALMAC_INTF_PHY_CUT_D; - break; - case HALMAC_CHIP_VER_E_CUT: - curr_cut = (u16)HALMAC_INTF_PHY_CUT_E; - break; - case HALMAC_CHIP_VER_F_CUT: - curr_cut = (u16)HALMAC_INTF_PHY_CUT_F; - break; - case HALMAC_CHIP_VER_TEST: - curr_cut = (u16)HALMAC_INTF_PHY_CUT_TESTCHIP; - break; - default: - return HALMAC_RET_FAIL; - } - - pCurr_phy_para = pIntf_phy_para; - - do { - if ((pCurr_phy_para->cut & curr_cut) && (pCurr_phy_para->plaform & (u16)platform)) { - offset = pCurr_phy_para->offset; - value = pCurr_phy_para->value; - ip_sel = pCurr_phy_para->ip_sel; - - if (offset == 0xFFFF) - break; - - if (ip_sel == HALMAC_IP_SEL_MAC) { - HALMAC_REG_WRITE_8(pHalmac_adapter, (u32)offset, (u8)value); - } else if (intf_phy == HAL_INTF_PHY_USB2) { - result = halmac_usbphy_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_USB2); - - if (result != HALMAC_RET_SUCCESS) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Write USB2PHY fail!\n"); - - } else if (intf_phy == HAL_INTF_PHY_USB3) { - result = halmac_usbphy_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_USB3); - - if (result != HALMAC_RET_SUCCESS) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Write USB3PHY fail!\n"); - - } else if (intf_phy == HAL_INTF_PHY_PCIE_GEN1) { - if (ip_sel == HALMAC_IP_SEL_INTF_PHY) - result = halmac_mdio_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_PCIE_GEN1); - else - result = halmac_dbi_write8_88xx(pHalmac_adapter, offset, (u8)value); - - if (result != HALMAC_RET_SUCCESS) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "[ERR]MDIO write GEN1 fail!\n"); - - } else if (intf_phy == HAL_INTF_PHY_PCIE_GEN2) { - if (ip_sel == HALMAC_IP_SEL_INTF_PHY) - result = halmac_mdio_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_PCIE_GEN2); - else - result = halmac_dbi_write8_88xx(pHalmac_adapter, offset, (u8)value); - - if (result != HALMAC_RET_SUCCESS) - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "[ERR]MDIO write GEN2 fail!\n"); - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]Parse intf phy cfg error!\n"); - } - } - pCurr_phy_para++; - } while (1); - - return HALMAC_RET_SUCCESS; -} - -HALMAC_RET_STATUS -halmac_dbi_write32_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u16 addr, - IN u32 data -) -{ - u8 tmp_u1b = 0; - u32 count = 0; - u16 write_addr = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DBI_WDATA_V1, data); - - write_addr = ((addr & 0x0ffc) | (0x000F << 12)); - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, write_addr); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "[TRACE]WriteAddr = %x\n", write_addr); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x01); - tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); - - count = 20; - while (tmp_u1b && (count != 0)) { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); - tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); - count--; - } - - if (tmp_u1b) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "[ERR]DBI write fail!\n"); - return HALMAC_RET_FAIL; - } - - return HALMAC_RET_SUCCESS; -} - -u32 -halmac_dbi_read32_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u16 addr -) -{ - u16 read_addr = addr & 0x0ffc; - u8 tmp_u1b = 0; - u32 count = 0; - u32 ret = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, read_addr); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x2); - tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); - - count = 20; - while (tmp_u1b && (count != 0)) { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); - tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); - count--; - } - - if (tmp_u1b) { - ret = 0xFFFF; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "[ERR]DBI read fail!\n"); - } else { - ret = HALMAC_REG_READ_32(pHalmac_adapter, REG_DBI_RDATA_V1); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "[TRACE]Read Value = %x\n", ret); - } - - return ret; -} - -HALMAC_RET_STATUS -halmac_dbi_write8_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u16 addr, - IN u8 data -) -{ - u8 tmp_u1b = 0; - u32 count = 0; - u16 write_addr = 0; - u16 remainder = addr & (4 - 1); - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_WDATA_V1 + remainder, data); - - write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12))); - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, write_addr); - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "[TRACE]WriteAddr = %x\n", write_addr); - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x01); - - tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); - - count = 20; - while (tmp_u1b && (count != 0)) { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); - tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); - count--; - } - - if (tmp_u1b) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "[ERR]DBI write fail!\n"); - return HALMAC_RET_FAIL; - } - - return HALMAC_RET_SUCCESS; -} - -u8 -halmac_dbi_read8_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u16 addr -) -{ - u16 read_addr = addr & 0x0ffc; - u8 tmp_u1b = 0; - u32 count = 0; - u8 ret = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, read_addr); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x2); - - tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); - - count = 20; - while (tmp_u1b && (count != 0)) { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); - tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); - count--; - } - - if (tmp_u1b) { - ret = 0xFF; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "[ERR]DBI read fail!\n"); - } else { - ret = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_RDATA_V1 + (addr & (4 - 1))); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "[TRACE]Read Value = %x\n", ret); - } - - return ret; -} - -HALMAC_RET_STATUS -halmac_mdio_write_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 addr, - IN u16 data, - IN u8 speed -) -{ - u8 tmp_u1b = 0; - u32 count = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - u8 real_addr = 0; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MDIO_V1, data); - - real_addr = (addr & 0x1F); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, real_addr); - - if (speed == HAL_INTF_PHY_PCIE_GEN1) { - if (addr < 0x20) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x00); - else - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x01); - } else if (speed == HAL_INTF_PHY_PCIE_GEN2) { - if (addr < 0x20) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x02); - else - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x03); - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "Error Speed !\n"); - } - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) | BIT_MDIO_WFLAG_V1); - - tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1; - count = 20; - - while (tmp_u1b && (count != 0)) { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); - tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1; - count--; - } - - if (tmp_u1b) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "MDIO write fail!\n"); - return HALMAC_RET_FAIL; - } - - return HALMAC_RET_SUCCESS; -} - -u16 -halmac_mdio_read_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 addr, - IN u8 speed - -) -{ - u16 ret = 0; - u8 tmp_u1b = 0; - u32 count = 0; - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - u8 real_addr = 0; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - real_addr = (addr & 0x1F); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, real_addr); - - if (speed == HAL_INTF_PHY_PCIE_GEN1) { - if (addr < 0x20) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x00); - else - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x01); - } else if (speed == HAL_INTF_PHY_PCIE_GEN2) { - if (addr < 0x20) - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x02); - else - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x03); - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "Error Speed !\n"); - } - - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) | BIT_MDIO_RFLAG_V1); - - tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1; - count = 20; - - while (tmp_u1b && (count != 0)) { - PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); - tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1; - count--; - } - - if (tmp_u1b) { - ret = 0xFFFF; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "MDIO read fail!\n"); - } else { - ret = HALMAC_REG_READ_16(pHalmac_adapter, REG_MDIO_V1 + 2); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_TRACE, "Read Value = %x\n", ret); - } - - return ret; -} - -HALMAC_RET_STATUS -halmac_usbphy_write_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 addr, - IN u16 data, - IN u8 speed -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (speed == HAL_INTF_PHY_USB3) { - HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0d, (u8)data); - HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0e, (u8)(data >> 8)); - HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0c, addr | BIT(7)); - } else if (speed == HAL_INTF_PHY_USB2) { - HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe41, (u8)data); - HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe40, addr); - HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe42, 0x81); - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Error USB Speed !\n"); - return HALMAC_RET_NOT_SUPPORT; - } - - return HALMAC_RET_SUCCESS; -} - -u16 -halmac_usbphy_read_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 addr, - IN u8 speed -) -{ - VOID *pDriver_adapter = NULL; - PHALMAC_API pHalmac_api; - u16 value = 0; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - if (speed == HAL_INTF_PHY_USB3) { - HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0c, addr | BIT(6)); - value = (u16)(HALMAC_REG_READ_32(pHalmac_adapter, 0xff0c) >> 8); - } else if (speed == HAL_INTF_PHY_USB2) { - if ((addr >= 0xE0) && (addr <= 0xFF)) - addr -= 0x20; - if ((addr >= 0xC0) && (addr <= 0xDF)) { - HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe40, addr); - HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe42, 0x81); - value = HALMAC_REG_READ_8(pHalmac_adapter, 0xfe43); - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Error USB2PHY offset!\n"); - return HALMAC_RET_NOT_SUPPORT; - } - } else { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Error USB Speed !\n"); - return HALMAC_RET_NOT_SUPPORT; - } - - return value; -} - diff --git a/hal/halmac/halmac_88xx/halmac_func_88xx.h b/hal/halmac/halmac_88xx/halmac_func_88xx.h deleted file mode 100644 index 51bf8c0..0000000 --- a/hal/halmac/halmac_88xx/halmac_func_88xx.h +++ /dev/null @@ -1,523 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_FUNC_88XX_H_ -#define _HALMAC_FUNC_88XX_H_ - -#include "../halmac_type.h" - -VOID -halmac_init_offload_feature_state_machine_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_send_h2c_pkt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHal_buff, - IN u32 size, - IN u8 ack -); - -HALMAC_RET_STATUS -halmac_download_rsvd_page_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHal_buf, - IN u32 size -); - -HALMAC_RET_STATUS -halmac_set_h2c_header_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u8 *pHal_h2c_hdr, - IN u16 *seq, - IN u8 ack -); - -HALMAC_RET_STATUS -halmac_set_fw_offload_h2c_header_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT u8 *pHal_h2c_hdr, - IN PHALMAC_H2C_HEADER_INFO pH2c_header_info, - OUT u16 *pSeq_num -); - -HALMAC_RET_STATUS -halmac_dump_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_EFUSE_READ_CFG cfg -); - -HALMAC_RET_STATUS -halmac_func_read_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 offset, - IN u32 size, - OUT u8 *pEfuse_map -); - -HALMAC_RET_STATUS -halmac_func_write_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 offset, - IN u8 value -); - -HALMAC_RET_STATUS -halmac_func_switch_efuse_bank_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_EFUSE_BANK efuse_bank -); - -HALMAC_RET_STATUS -halmac_read_logical_efuse_map_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pMap -); - -HALMAC_RET_STATUS -halmac_func_write_logical_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 offset, - IN u8 value -); - -HALMAC_RET_STATUS -halmac_func_pg_efuse_by_map_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, - IN HALMAC_EFUSE_READ_CFG cfg -); - -HALMAC_RET_STATUS -halmac_eeprom_parser_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pPhysical_efuse_map, - OUT u8 *pLogical_efuse_map -); - -HALMAC_RET_STATUS -halmac_read_hw_efuse_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 offset, - IN u32 size, - OUT u8 *pEfuse_map -); - -HALMAC_RET_STATUS -halmac_update_fw_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pHamacl_fw, - IN u32 halmac_fw_size -); - -HALMAC_RET_STATUS -halmac_dlfw_to_mem_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pRam_code, - IN u32 dest, - IN u32 code_size -); - -HALMAC_RET_STATUS -halmac_send_fwpkt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pRam_code, - IN u32 code_size -); - -HALMAC_RET_STATUS -halmac_iddma_dlfw_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 source, - IN u32 dest, - IN u32 length, - IN u8 first -); - -HALMAC_RET_STATUS -halmac_check_fw_chksum_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 memory_address -); - -HALMAC_RET_STATUS -halmac_dlfw_end_flow_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_free_dl_fw_end_flow_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_pwr_seq_parser_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 cut, - IN u8 fab, - IN u8 intf, - IN PHALMAC_WLAN_PWR_CFG *ppPwr_seq_cfg - -); - -HALMAC_RET_STATUS -halmac_get_h2c_buff_free_space_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_func_send_original_h2c_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *original_h2c, - IN u16 *seq, - IN u8 ack -); - -HALMAC_RET_STATUS -halmac_send_h2c_update_datapack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DATA_TYPE halmac_data_type, - IN PHALMAC_PHY_PARAMETER_INFO para_info -); - -HALMAC_RET_STATUS -halmac_send_h2c_run_datapack_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_DATA_TYPE halmac_data_type -); - -HALMAC_RET_STATUS -halmac_send_bt_coex_cmd_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *pBt_buf, - IN u32 bt_size, - IN u8 ack -); - -HALMAC_RET_STATUS -halmac_func_ctrl_ch_switch_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_CH_SWITCH_OPTION pCs_option -); - -HALMAC_RET_STATUS -halmac_func_send_general_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_GENERAL_INFO pGeneral_info -); - -HALMAC_RET_STATUS -halmac_send_h2c_ps_tuning_para_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_parse_c2h_packet_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 *halmac_buf, - IN u32 halmac_size -); - -HALMAC_RET_STATUS -halmac_send_h2c_update_packet_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_PACKET_ID pkt_id, - IN u8 *pkt, - IN u32 pkt_size -); - -HALMAC_RET_STATUS -halmac_send_h2c_phy_parameter_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_PHY_PARAMETER_INFO para_info, - IN u8 full_fifo -); - -HALMAC_RET_STATUS -halmac_dump_physical_efuse_fw_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 offset, - IN u32 Size, - OUT u8 *pEfuse_map -); - -HALMAC_RET_STATUS -halmac_send_h2c_update_bcn_parse_info_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_BCN_IE_INFO pBcn_ie_info -); - -HALMAC_RET_STATUS -halmac_convert_to_sdio_bus_offset_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - INOUT u32 *halmac_offset -); - -HALMAC_RET_STATUS -halmac_update_sdio_free_page_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_update_oqt_free_space_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_EFUSE_CMD_CONSTRUCT_STATE -halmac_query_efuse_curr_state_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_transition_efuse_state_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_EFUSE_CMD_CONSTRUCT_STATE dest_state -); - -HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE -halmac_query_cfg_para_curr_state_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_transition_cfg_para_state_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE dest_state -); - -HALMAC_SCAN_CMD_CONSTRUCT_STATE -halmac_query_scan_curr_state_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_transition_scan_state_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_SCAN_CMD_CONSTRUCT_STATE dest_state -); - -HALMAC_RET_STATUS -halmac_query_cfg_para_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -); - -HALMAC_RET_STATUS -halmac_query_dump_physical_efuse_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -); - -HALMAC_RET_STATUS -halmac_query_dump_logical_efuse_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -); - -HALMAC_RET_STATUS -halmac_query_channel_switch_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -); - -HALMAC_RET_STATUS -halmac_query_update_packet_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -); - -HALMAC_RET_STATUS -halmac_query_iqk_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -); - -HALMAC_RET_STATUS -halmac_query_power_tracking_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -); - -HALMAC_RET_STATUS -halmac_query_psd_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, - INOUT u8 *data, - INOUT u32 *size -); - -HALMAC_RET_STATUS -halmac_verify_io_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_verify_send_rsvd_page_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -VOID -halmac_power_save_cb_88xx( - IN VOID *CbData -); - -HALMAC_RET_STATUS -halmac_buffer_read_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 offset, - IN u32 size, - IN HAL_FIFO_SEL halmac_fifo_sel, - OUT u8 *pFifo_map -); - -VOID -halmac_restore_mac_register_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_RESTORE_INFO pRestore_info, - IN u32 restore_num -); - -HALMAC_RET_STATUS -halmac_set_usb_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_USB_MODE usb_mode -); - -VOID -halmac_enable_bb_rf_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable -); - -VOID -halmac_config_sdio_tx_page_threshold_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_TX_PAGE_THRESHOLD_INFO pThreshold_info -); - -HALMAC_RET_STATUS -halmac_rqpn_parser_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode, - IN PHALMAC_RQPN pPwr_seq_cfg -); - -HALMAC_RET_STATUS -halmac_check_oqt_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u32 tx_agg_num, - IN u8 *pHalmac_buf, - IN u8 macid_counter -); - -HALMAC_RET_STATUS -halmac_pg_num_parser_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_TRX_MODE halmac_trx_mode, - IN PHALMAC_PG_NUM pPg_num_table -); - -HALMAC_RET_STATUS -halmac_parse_intf_phy_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_INTF_PHY_PARA pIntf_phy_para, - IN HALMAC_INTF_PHY_PLATFORM platform, - IN HAL_INTF_PHY intf_phy -); - -HALMAC_RET_STATUS -halmac_dbi_write32_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u16 addr, - IN u32 data -); - -u32 -halmac_dbi_read32_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u16 addr -); - -HALMAC_RET_STATUS -halmac_dbi_write8_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u16 addr, - IN u8 data -); - -u8 -halmac_dbi_read8_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u16 addr -); - -u16 -halmac_mdio_read_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 addr, - IN u8 speed - -); - -HALMAC_RET_STATUS -halmac_mdio_write_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 addr, - IN u16 data, - IN u8 speed -); - -VOID -halmac_config_ampdu_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN PHALMAC_AMPDU_CONFIG pAmpdu_config -); - -VOID -halmac_rx_shift_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 enable -); - -HALMAC_RET_STATUS -halmac_usbphy_write_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 addr, - IN u16 data, - IN u8 speed -); - -u16 -halmac_usbphy_read_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 addr, - IN u8 speed -); -#endif /* _HALMAC_FUNC_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_gpio_88xx.c b/hal/halmac/halmac_88xx/halmac_gpio_88xx.c index 436220c..5ed94e3 100644 --- a/hal/halmac/halmac_88xx/halmac_gpio_88xx.c +++ b/hal/halmac/halmac_88xx/halmac_gpio_88xx.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,35 +15,31 @@ #include "halmac_gpio_88xx.h" +#if HALMAC_88XX_SUPPORT + /** - * halmac_pinmux_wl_led_mode_88xx() -control wlan led gpio function - * @pHalmac_adapter : the adapter of halmac - * @wlled_mode : wlan led mode + * pinmux_wl_led_mode_88xx() -control wlan led gpio function + * @adapter : the adapter of halmac + * @mode : wlan led mode * Author : Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_pinmux_wl_led_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_WLLED_MODE wlled_mode -) +enum halmac_ret_status +pinmux_wl_led_mode_88xx(struct halmac_adapter *adapter, + enum halmac_wlled_mode mode) { u8 value8; - PHALMAC_API pHalmac_api; - VOID *pDriver_adapter = NULL; - - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_wl_led_mode_88xx ==========>\n"); + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_LED_CFG + 2); + value8 = HALMAC_REG_R8(REG_LED_CFG + 2); value8 &= ~(BIT(6)); value8 |= BIT(3); value8 &= ~(BIT(0) | BIT(1) | BIT(2)); - switch (wlled_mode) { + switch (mode) { case HALMAC_WLLED_MODE_TRX: value8 |= 2; break; @@ -60,85 +56,69 @@ halmac_pinmux_wl_led_mode_88xx( return HALMAC_RET_SWITCH_CASE_ERROR; } - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LED_CFG + 2, value8); + HALMAC_REG_W8(REG_LED_CFG + 2, value8); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_pinmux_wl_led_mode_88xx <==========\n"); + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); return HALMAC_RET_SUCCESS; } /** - * halmac_pinmux_wl_led_sw_ctrl_88xx() -control wlan led on/off - * @pHalmac_adapter : the adapter of halmac - * @led_on : on(1), off(0) + * pinmux_wl_led_sw_ctrl_88xx() -control wlan led on/off + * @adapter : the adapter of halmac + * @on : on(1), off(0) * Author : Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -VOID -halmac_pinmux_wl_led_sw_ctrl_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 led_on -) +void +pinmux_wl_led_sw_ctrl_88xx(struct halmac_adapter *adapter, u8 on) { u8 value8; - PHALMAC_API pHalmac_api; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_LED_CFG + 2); - value8 = (led_on == 0) ? value8 | BIT(3) : value8 & ~(BIT(3)); + value8 = HALMAC_REG_R8(REG_LED_CFG + 2); + value8 = (on == 0) ? value8 | BIT(3) : value8 & ~(BIT(3)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LED_CFG + 2, value8); + HALMAC_REG_W8(REG_LED_CFG + 2, value8); } /** - * halmac_pinmux_sdio_int_polarity_88xx() -control sdio int polarity - * @pHalmac_adapter : the adapter of halmac + * pinmux_sdio_int_polarity_88xx() -control sdio int polarity + * @adapter : the adapter of halmac * @low_active : low active(1), high active(0) * Author : Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -VOID -halmac_pinmux_sdio_int_polarity_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 low_active -) +void +pinmux_sdio_int_polarity_88xx(struct halmac_adapter *adapter, u8 low_active) { u8 value8; - PHALMAC_API pHalmac_api; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_SDIO_CTRL + 2); + value8 = HALMAC_REG_R8(REG_SYS_SDIO_CTRL + 2); value8 = (low_active == 0) ? value8 | BIT(3) : value8 & ~(BIT(3)); - HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_SDIO_CTRL + 2, value8); + HALMAC_REG_W8(REG_SYS_SDIO_CTRL + 2, value8); } /** - * halmac_pinmux_gpio_mode_88xx() -control gpio io mode - * @pHalmac_adapter : the adapter of halmac + * pinmux_gpio_mode_88xx() -control gpio io mode + * @adapter : the adapter of halmac * @gpio_id : gpio0~15(0~15) * @output : output(1), input(0) * Author : Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_pinmux_gpio_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 gpio_id, - IN u8 output -) +enum halmac_ret_status +pinmux_gpio_mode_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 output) { u16 value16; u8 in_out; u32 offset; - PHALMAC_API pHalmac_api; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; if (gpio_id <= 7) offset = REG_GPIO_PIN_CTRL + 2; @@ -150,36 +130,30 @@ halmac_pinmux_gpio_mode_88xx( in_out = (output == 0) ? 0 : 1; gpio_id &= (8 - 1); - value16 = HALMAC_REG_READ_16(pHalmac_adapter, offset); + value16 = HALMAC_REG_R16(offset); value16 &= ~((1 << gpio_id) | (1 << gpio_id << 8)); value16 |= (in_out << gpio_id); - HALMAC_REG_WRITE_16(pHalmac_adapter, offset, value16); + HALMAC_REG_W16(offset, value16); return HALMAC_RET_SUCCESS; } /** - * halmac_pinmux_gpio_output_88xx() -control gpio output high/low - * @pHalmac_adapter : the adapter of halmac + * pinmux_gpio_output_88xx() -control gpio output high/low + * @adapter : the adapter of halmac * @gpio_id : gpio0~15(0~15) * @high : high(1), low(0) * Author : Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_pinmux_gpio_output_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 gpio_id, - IN u8 high -) +enum halmac_ret_status +pinmux_gpio_output_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 high) { u8 value8; u8 hi_low; u32 offset; - PHALMAC_API pHalmac_api; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; if (gpio_id <= 7) offset = REG_GPIO_PIN_CTRL + 1; @@ -191,35 +165,29 @@ halmac_pinmux_gpio_output_88xx( hi_low = (high == 0) ? 0 : 1; gpio_id &= (8 - 1); - value8 = HALMAC_REG_READ_8(pHalmac_adapter, offset); + value8 = HALMAC_REG_R8(offset); value8 &= ~(1 << gpio_id); value8 |= (hi_low << gpio_id); - HALMAC_REG_WRITE_8(pHalmac_adapter, offset, value8); + HALMAC_REG_W8(offset, value8); return HALMAC_RET_SUCCESS; } /** * halmac_pinmux_status_88xx() -get current gpio status(high/low) - * @pHalmac_adapter : the adapter of halmac + * @adapter : the adapter of halmac * @pin_id : 0~15(0~15) * @phigh : high(1), low(0) * Author : Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_pinmux_pin_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 pin_id, - OUT u8 *pHigh -) +enum halmac_ret_status +pinmux_pin_status_88xx(struct halmac_adapter *adapter, u8 pin_id, u8 *high) { u8 value8; u32 offset; - PHALMAC_API pHalmac_api; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; if (pin_id <= 7) offset = REG_GPIO_PIN_CTRL; @@ -230,84 +198,72 @@ halmac_pinmux_pin_status_88xx( pin_id &= (8 - 1); - value8 = HALMAC_REG_READ_8(pHalmac_adapter, offset); - *pHigh = (value8 & (1 << pin_id)) >> pin_id; + value8 = HALMAC_REG_R8(offset); + *high = (value8 & (1 << pin_id)) >> pin_id; return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS -halmac_pinmux_parser_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN const HALMAC_GPIO_PIMUX_LIST *pPinmux_list, - IN u32 list_size, - IN u32 gpio_id, - OUT u32 *pCur_func -) +enum halmac_ret_status +pinmux_parser_88xx(struct halmac_adapter *adapter, + const struct halmac_gpio_pimux_list *list, u32 size, + u32 gpio_id, u32 *cur_func) { - u8 value8; u32 i; - const HALMAC_GPIO_PIMUX_LIST *pCurr_func; - HALMAC_GPIO_CFG_STATE *pGpio_state = &pHalmac_adapter->halmac_state.gpio_cfg_state; - PHALMAC_API pHalmac_api; - VOID *pDriver_adapter = NULL; + u8 value8; + const struct halmac_gpio_pimux_list *cur_list = list; + enum halmac_gpio_cfg_state *state; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - pCurr_func = pPinmux_list; + state = &adapter->halmac_state.gpio_cfg_state; - if (*pGpio_state == HALMAC_GPIO_CFG_STATE_BUSY) + if (*state == HALMAC_GPIO_CFG_STATE_BUSY) return HALMAC_RET_BUSY_STATE; - *pGpio_state = HALMAC_GPIO_CFG_STATE_BUSY; + *state = HALMAC_GPIO_CFG_STATE_BUSY; - for (i = 0; i < list_size; i++) { - if (gpio_id != pCurr_func->id) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]offset : %X, value : %X, func : %X\n", - pCurr_func->offset, pCurr_func->value, pCurr_func->func); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]id1 : %X, id2 : %X\n", gpio_id, pCurr_func->id); - *pGpio_state = HALMAC_GPIO_CFG_STATE_IDLE; + for (i = 0; i < size; i++) { + if (gpio_id != cur_list->id) { + PLTFM_MSG_ERR("[ERR]offset:%X, value:%X, func:%X\n", + cur_list->offset, cur_list->value, + cur_list->func); + PLTFM_MSG_ERR("[ERR]id1 : %X, id2 : %X\n", + gpio_id, cur_list->id); + *state = HALMAC_GPIO_CFG_STATE_IDLE; return HALMAC_RET_GET_PINMUX_ERR; } - value8 = HALMAC_REG_READ_8(pHalmac_adapter, pCurr_func->offset); - value8 &= pCurr_func->msk; - if (value8 == pCurr_func->value) { - *pCur_func = pCurr_func->func; + value8 = HALMAC_REG_R8(cur_list->offset); + value8 &= cur_list->msk; + if (value8 == cur_list->value) { + *cur_func = cur_list->func; break; } - pCurr_func++; + cur_list++; } - *pGpio_state = HALMAC_GPIO_CFG_STATE_IDLE; + *state = HALMAC_GPIO_CFG_STATE_IDLE; - if (i == list_size) + if (i == size) return HALMAC_RET_GET_PINMUX_ERR; return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS -halmac_pinmux_switch_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN const HALMAC_GPIO_PIMUX_LIST *pPinmux_list, - IN u32 list_size, - IN u32 gpio_id, - IN HALMAC_GPIO_FUNC gpio_func -) +enum halmac_ret_status +pinmux_switch_88xx(struct halmac_adapter *adapter, + const struct halmac_gpio_pimux_list *list, u32 size, + u32 gpio_id, enum halmac_gpio_func gpio_func) { u32 i; u8 value8; u16 switch_func; - const HALMAC_GPIO_PIMUX_LIST *pCurr_func; - HALMAC_GPIO_CFG_STATE *pGpio_state = &pHalmac_adapter->halmac_state.gpio_cfg_state; - PHALMAC_API pHalmac_api; - VOID *pDriver_adapter = NULL; + const struct halmac_gpio_pimux_list *cur_list = list; + enum halmac_gpio_cfg_state *state; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - pCurr_func = pPinmux_list; + state = &adapter->halmac_state.gpio_cfg_state; - if (*pGpio_state == HALMAC_GPIO_CFG_STATE_BUSY) + if (*state == HALMAC_GPIO_CFG_STATE_BUSY) return HALMAC_RET_BUSY_STATE; switch (gpio_func) { @@ -339,110 +295,110 @@ halmac_pinmux_switch_88xx( return HALMAC_RET_SWITCH_CASE_ERROR; } - for (i = 0; i < list_size; i++) { - if (gpio_id != pCurr_func->id) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]offset : %X, value : %X, func : %X\n", - pCurr_func->offset, pCurr_func->value, pCurr_func->func); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]id1 : %X, id2 : %X\n", gpio_id, pCurr_func->id); + for (i = 0; i < size; i++) { + if (gpio_id != cur_list->id) { + PLTFM_MSG_ERR("[ERR]offset:%X, value:%X, func:%X\n", + cur_list->offset, cur_list->value, + cur_list->func); + PLTFM_MSG_ERR("[ERR]id1 : %X, id2 : %X\n", + gpio_id, cur_list->id); return HALMAC_RET_GET_PINMUX_ERR; } - if (switch_func == pCurr_func->func) + if (switch_func == cur_list->func) break; - pCurr_func++; + cur_list++; } - if (i == list_size) { - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]gpio func error : %X %X\n", gpio_id, pCurr_func->id); + if (i == size) { + PLTFM_MSG_ERR("[ERR]gpio func error:%X %X\n", + gpio_id, cur_list->id); return HALMAC_RET_GET_PINMUX_ERR; } - *pGpio_state = HALMAC_GPIO_CFG_STATE_BUSY; + *state = HALMAC_GPIO_CFG_STATE_BUSY; - pCurr_func = pPinmux_list; - for (i = 0; i < list_size; i++) { - value8 = HALMAC_REG_READ_8(pHalmac_adapter, pCurr_func->offset); - value8 &= ~(pCurr_func->msk); + cur_list = list; + for (i = 0; i < size; i++) { + value8 = HALMAC_REG_R8(cur_list->offset); + value8 &= ~(cur_list->msk); - if (switch_func == pCurr_func->func) { - value8 |= (pCurr_func->value & pCurr_func->msk); - HALMAC_REG_WRITE_8(pHalmac_adapter, pCurr_func->offset, value8); + if (switch_func == cur_list->func) { + value8 |= (cur_list->value & cur_list->msk); + HALMAC_REG_W8(cur_list->offset, value8); break; } - value8 |= (~pCurr_func->value & pCurr_func->msk); - HALMAC_REG_WRITE_8(pHalmac_adapter, pCurr_func->offset, value8); + value8 |= (~cur_list->value & cur_list->msk); + HALMAC_REG_W8(cur_list->offset, value8); - pCurr_func++; + cur_list++; } - *pGpio_state = HALMAC_GPIO_CFG_STATE_IDLE; + *state = HALMAC_GPIO_CFG_STATE_IDLE; return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS -halmac_pinmux_record_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_GPIO_FUNC gpio_func, - IN u8 val -) +enum halmac_ret_status +pinmux_record_88xx(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, u8 val) { switch (gpio_func) { case HALMAC_GPIO_FUNC_WL_LED: - pHalmac_adapter->pinmux_info.wl_led = val; + adapter->pinmux_info.wl_led = val; break; case HALMAC_GPIO_FUNC_SDIO_INT: - pHalmac_adapter->pinmux_info.sdio_int = val; + adapter->pinmux_info.sdio_int = val; break; case HALMAC_GPIO_FUNC_SW_IO_0: - pHalmac_adapter->pinmux_info.sw_io_0 = val; + adapter->pinmux_info.sw_io_0 = val; break; case HALMAC_GPIO_FUNC_SW_IO_1: - pHalmac_adapter->pinmux_info.sw_io_1 = val; + adapter->pinmux_info.sw_io_1 = val; break; case HALMAC_GPIO_FUNC_SW_IO_2: - pHalmac_adapter->pinmux_info.sw_io_2 = val; + adapter->pinmux_info.sw_io_2 = val; break; case HALMAC_GPIO_FUNC_SW_IO_3: - pHalmac_adapter->pinmux_info.sw_io_3 = val; + adapter->pinmux_info.sw_io_3 = val; break; case HALMAC_GPIO_FUNC_SW_IO_4: - pHalmac_adapter->pinmux_info.sw_io_4 = val; + adapter->pinmux_info.sw_io_4 = val; break; case HALMAC_GPIO_FUNC_SW_IO_5: - pHalmac_adapter->pinmux_info.sw_io_5 = val; + adapter->pinmux_info.sw_io_5 = val; break; case HALMAC_GPIO_FUNC_SW_IO_6: - pHalmac_adapter->pinmux_info.sw_io_6 = val; + adapter->pinmux_info.sw_io_6 = val; break; case HALMAC_GPIO_FUNC_SW_IO_7: - pHalmac_adapter->pinmux_info.sw_io_7 = val; + adapter->pinmux_info.sw_io_7 = val; break; case HALMAC_GPIO_FUNC_SW_IO_8: - pHalmac_adapter->pinmux_info.sw_io_8 = val; + adapter->pinmux_info.sw_io_8 = val; break; case HALMAC_GPIO_FUNC_SW_IO_9: - pHalmac_adapter->pinmux_info.sw_io_9 = val; + adapter->pinmux_info.sw_io_9 = val; break; case HALMAC_GPIO_FUNC_SW_IO_10: - pHalmac_adapter->pinmux_info.sw_io_10 = val; + adapter->pinmux_info.sw_io_10 = val; break; case HALMAC_GPIO_FUNC_SW_IO_11: - pHalmac_adapter->pinmux_info.sw_io_11 = val; + adapter->pinmux_info.sw_io_11 = val; break; case HALMAC_GPIO_FUNC_SW_IO_12: - pHalmac_adapter->pinmux_info.sw_io_12 = val; + adapter->pinmux_info.sw_io_12 = val; break; case HALMAC_GPIO_FUNC_SW_IO_13: - pHalmac_adapter->pinmux_info.sw_io_13 = val; + adapter->pinmux_info.sw_io_13 = val; break; case HALMAC_GPIO_FUNC_SW_IO_14: - pHalmac_adapter->pinmux_info.sw_io_14 = val; + adapter->pinmux_info.sw_io_14 = val; break; case HALMAC_GPIO_FUNC_SW_IO_15: - pHalmac_adapter->pinmux_info.sw_io_15 = val; + adapter->pinmux_info.sw_io_15 = val; break; default: return HALMAC_RET_GET_PINMUX_ERR; @@ -451,3 +407,5 @@ halmac_pinmux_record_88xx( return HALMAC_RET_SUCCESS; } +#endif /* HALMAC_88XX_SUPPORT */ + diff --git a/hal/halmac/halmac_88xx/halmac_gpio_88xx.h b/hal/halmac/halmac_88xx/halmac_gpio_88xx.h index c2f31b0..63ffac4 100644 --- a/hal/halmac/halmac_88xx/halmac_gpio_88xx.h +++ b/hal/halmac/halmac_88xx/halmac_gpio_88xx.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -19,68 +19,41 @@ #include "../halmac_api.h" #include "../halmac_gpio_cmd.h" -HALMAC_RET_STATUS -halmac_pinmux_wl_led_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_WLLED_MODE wlled_mode -); +#if HALMAC_88XX_SUPPORT -VOID -halmac_pinmux_wl_led_sw_ctrl_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 led_on -); +enum halmac_ret_status +pinmux_wl_led_mode_88xx(struct halmac_adapter *adapter, + enum halmac_wlled_mode mode); -VOID -halmac_pinmux_sdio_int_polarity_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 low_active -); +void +pinmux_wl_led_sw_ctrl_88xx(struct halmac_adapter *adapter, u8 on); -HALMAC_RET_STATUS -halmac_pinmux_gpio_mode_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 gpio_id, - IN u8 output -); +void +pinmux_sdio_int_polarity_88xx(struct halmac_adapter *adapter, u8 low_active); -HALMAC_RET_STATUS -halmac_pinmux_gpio_output_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 gpio_id, - IN u8 high -); +enum halmac_ret_status +pinmux_gpio_mode_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 output); -HALMAC_RET_STATUS -halmac_pinmux_pin_status_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN u8 pin_id, - OUT u8 *pHigh -); +enum halmac_ret_status +pinmux_gpio_output_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 high); -HALMAC_RET_STATUS -halmac_pinmux_parser_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN const HALMAC_GPIO_PIMUX_LIST *pPinmux_list, - IN u32 list_size, - IN u32 gpio_id, - OUT u32 *pCur_func -); +enum halmac_ret_status +pinmux_pin_status_88xx(struct halmac_adapter *adapter, u8 pin_id, u8 *high); -HALMAC_RET_STATUS -halmac_pinmux_switch_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN const HALMAC_GPIO_PIMUX_LIST *pPinmux_list, - IN u32 list_size, - IN u32 gpio_id, - IN HALMAC_GPIO_FUNC gpio_func -); +enum halmac_ret_status +pinmux_parser_88xx(struct halmac_adapter *adapter, + const struct halmac_gpio_pimux_list *list, u32 size, + u32 gpio_id, u32 *cur_func); -HALMAC_RET_STATUS -halmac_pinmux_record_88xx( - IN PHALMAC_ADAPTER pHalmac_adapter, - IN HALMAC_GPIO_FUNC gpio_func, - IN u8 val -); +enum halmac_ret_status +pinmux_switch_88xx(struct halmac_adapter *adapter, + const struct halmac_gpio_pimux_list *list, u32 size, + u32 gpio_id, enum halmac_gpio_func gpio_func); + +enum halmac_ret_status +pinmux_record_88xx(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, u8 val); + +#endif /* HALMAC_88XX_SUPPORT */ #endif/* _HALMAC_GPIO_88XX_H_ */ diff --git a/hal/halmac/halmac_api.c b/hal/halmac/halmac_api.c index ac367d2..6bf40b8 100644 --- a/hal/halmac/halmac_api.c +++ b/hal/halmac/halmac_api.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -13,366 +13,425 @@ * ******************************************************************************/ -#include "halmac_2_platform.h" #include "halmac_type.h" -#if HALMAC_PLATFORM_WINDOWS == 1 +#include "halmac_api.h" + +#if (HALMAC_PLATFORM_WINDOWS) + #if HALMAC_8822B_SUPPORT -#include "halmac_88xx/halmac_api_win8822b.h" -#include "halmac_88xx/halmac_win8822b_cfg.h" +#include "halmac_88xx/halmac_init_win8822b.h" #endif + #if HALMAC_8821C_SUPPORT -#include "halmac_88xx/halmac_api_win8821c.h" -#include "halmac_88xx/halmac_win8821c_cfg.h" +#include "halmac_88xx/halmac_init_win8821c.h" #endif -#else -#include "halmac_88xx/halmac_api_88xx.h" -#include "halmac_88xx/halmac_88xx_cfg.h" +#if HALMAC_8814B_SUPPORT +#include "halmac_88xx_v1/halmac_init_win8814b_v1.h" #endif -#if HALMAC_8822B_SUPPORT -#include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h" +#if HALMAC_8822C_SUPPORT +#include "halmac_88xx/halmac_init_win8822c.h" #endif -#if HALMAC_8821C_SUPPORT -#include "halmac_88xx/halmac_8821c/halmac_8821c_cfg.h" + +#else + +#if HALMAC_88XX_SUPPORT +#include "halmac_88xx/halmac_init_88xx.h" +#endif +#if HALMAC_88XX_V1_SUPPORT +#include "halmac_88xx_v1/halmac_init_88xx_v1.h" +#endif + #endif +/* Remove halmac_*/ +enum chip_id_hw_def { + CHIP_ID_HW_DEF_8723A = 0x01, + CHIP_ID_HW_DEF_8188E = 0x02, + CHIP_ID_HW_DEF_8881A = 0x03, + CHIP_ID_HW_DEF_8812A = 0x04, + CHIP_ID_HW_DEF_8821A = 0x05, + CHIP_ID_HW_DEF_8723B = 0x06, + CHIP_ID_HW_DEF_8192E = 0x07, + CHIP_ID_HW_DEF_8814A = 0x08, + CHIP_ID_HW_DEF_8821C = 0x09, + CHIP_ID_HW_DEF_8822B = 0x0A, + CHIP_ID_HW_DEF_8703B = 0x0B, + CHIP_ID_HW_DEF_8188F = 0x0C, + CHIP_ID_HW_DEF_8192F = 0x0D, + CHIP_ID_HW_DEF_8197F = 0x0E, + CHIP_ID_HW_DEF_8723D = 0x0F, + CHIP_ID_HW_DEF_8814B = 0x11, + CHIP_ID_HW_DEF_8822C = 0x13, + CHIP_ID_HW_DEF_UNDEFINE = 0x7F, + CHIP_ID_HW_DEF_PS = 0xEA, +}; + +static enum halmac_ret_status +chk_pltfm_api(void *drv_adapter, enum halmac_interface intf, + struct halmac_platform_api *pltfm_api); + +static enum halmac_ret_status +get_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api, + enum halmac_interface intf, struct halmac_adapter *adapter); -static HALMAC_RET_STATUS -halmac_check_platform_api( - IN VOID *pDriver_adapter, - IN HALMAC_INTERFACE halmac_interface, - IN PHALMAC_PLATFORM_API pHalmac_platform_api -); - -static HALMAC_RET_STATUS -halmac_get_chip_info( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN HALMAC_INTERFACE halmac_interface, - IN PHALMAC_ADAPTER pHalmac_adapter -); +static u8 +pltfm_reg_r8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api, + u32 offset); + +static enum halmac_ret_status +pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api, + u32 offset, u8 data); static u8 -platform_reg_read_8_sdio( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN u32 offset -); - -static HALMAC_RET_STATUS -plarform_reg_write_8_sdio( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN u32 offset, - IN u8 data -); - -static HALMAC_RET_STATUS -halmac_convert_to_sdio_bus_offset( - INOUT u32 *halmac_offset -); +pltfm_reg_r_indir_sdio(VOID *drv_adapter, struct halmac_platform_api *pltfm_api, + u32 offset); + +static enum halmac_ret_status +cnv_to_sdio_bus_offset(u32 *offset); /** * halmac_init_adapter() - init halmac_adapter - * @pDriver_adapter : the adapter of caller - * @pHalmac_platform_api : the platform APIs which is used in halmac APIs - * @halmac_interface : bus interface - * @ppHalmac_adapter : the adapter of halmac - * @ppHalmac_api : the function pointer of APIs, caller shall call APIs by function pointer + * @drv_adapter : the adapter of caller + * @pltfm_api : the platform APIs which is used in halmac + * @intf : bus interface + * @halmac_adapter : the adapter of halmac + * @halmac_api : the function pointer of APIs * Author : KaiYuan Chang / Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_init_adapter( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN HALMAC_INTERFACE halmac_interface, - OUT PHALMAC_ADAPTER *ppHalmac_adapter, - OUT PHALMAC_API *ppHalmac_api -) +enum halmac_ret_status +halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api, + enum halmac_interface intf, + struct halmac_adapter **halmac_adapter, + struct halmac_api **halmac_api) { - PHALMAC_ADAPTER pHalmac_adapter = (PHALMAC_ADAPTER)NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - u8 *pBuf = NULL; + struct halmac_adapter *adapter = NULL; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + u8 *buf = NULL; -#if HALMAC_PLATFORM_WINDOWS == 1 - u8 chip_id = 0; -#endif union { - u32 i; - u8 x[4]; + u32 i; + u8 x[4]; } ENDIAN_CHECK = { 0x01000000 }; - status = halmac_check_platform_api(pDriver_adapter, halmac_interface, pHalmac_platform_api); + status = chk_pltfm_api(drv_adapter, intf, pltfm_api); if (status != HALMAC_RET_SUCCESS) return status; - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, HALMAC_SVN_VER "\n"); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MAJOR_VER = %x\n", HALMAC_MAJOR_VER); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PROTOTYPE_VER = %x\n", HALMAC_PROTOTYPE_VER); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MINOR_VER = %x\n", HALMAC_MINOR_VER); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PATCH_VER = %x\n", HALMAC_PATCH_VER); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_adapter_88xx ==========>\n"); + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, + HALMAC_SVN_VER "\n" + "HALMAC_MAJOR_VER = %x\n" + "HALMAC_PROTOTYPE_VER = %x\n" + "HALMAC_MINOR_VER = %x\n" + "HALMAC_PATCH_VER = %x\n", + HALMAC_MAJOR_VER, HALMAC_PROTOTYPE_VER, + HALMAC_MINOR_VER, HALMAC_PATCH_VER); - /* Check endian setting - Little endian : 1, Big endian : 0*/ if (ENDIAN_CHECK.x[0] == HALMAC_SYSTEM_ENDIAN) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Endian setting Err!!\n"); + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, + "[ERR]Endian setting err!!\n"); return HALMAC_RET_ENDIAN_ERR; } - pBuf = (u8 *)pHalmac_platform_api->RTL_MALLOC(pDriver_adapter, sizeof(HALMAC_ADAPTER)); + buf = (u8 *)pltfm_api->RTL_MALLOC(drv_adapter, sizeof(*adapter)); - if (pBuf == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Malloc HAL Adapter Err!!\n"); + if (!buf) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, + "[ERR]Malloc HAL adapter err!!\n"); return HALMAC_RET_MALLOC_FAIL; } - pHalmac_platform_api->RTL_MEMSET(pDriver_adapter, pBuf, 0x00, sizeof(HALMAC_ADAPTER)); - pHalmac_adapter = (PHALMAC_ADAPTER)pBuf; + pltfm_api->RTL_MEMSET(drv_adapter, buf, 0x00, sizeof(*adapter)); + adapter = (struct halmac_adapter *)buf; - /* return halmac adapter address to caller */ - *ppHalmac_adapter = pHalmac_adapter; + *halmac_adapter = adapter; - /* Record caller info */ - pHalmac_adapter->pHalmac_platform_api = pHalmac_platform_api; - pHalmac_adapter->pDriver_adapter = pDriver_adapter; - halmac_interface = (halmac_interface == HALMAC_INTERFACE_AXI) ? HALMAC_INTERFACE_PCIE : halmac_interface; - pHalmac_adapter->halmac_interface = halmac_interface; + adapter->pltfm_api = pltfm_api; + adapter->drv_adapter = drv_adapter; + intf = (intf == HALMAC_INTERFACE_AXI) ? HALMAC_INTERFACE_PCIE : intf; + adapter->intf = intf; - PLATFORM_MUTEX_INIT(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - PLATFORM_MUTEX_INIT(pDriver_adapter, &pHalmac_adapter->h2c_seq_mutex); - - /*Get Chip*/ - if (halmac_get_chip_info(pDriver_adapter, pHalmac_platform_api, halmac_interface, pHalmac_adapter) != HALMAC_RET_SUCCESS) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_RET_CHIP_NOT_SUPPORT\n"); + if (get_chip_info(drv_adapter, pltfm_api, intf, adapter) + != HALMAC_RET_SUCCESS) { + PLTFM_FREE(*halmac_adapter, sizeof(**halmac_adapter)); + *halmac_adapter = NULL; return HALMAC_RET_CHIP_NOT_SUPPORT; } - /* Assign function pointer to halmac API */ -#if HALMAC_PLATFORM_WINDOWS == 0 - halmac_init_adapter_para_88xx(pHalmac_adapter); - status = halmac_mount_api_88xx(pHalmac_adapter); + PLTFM_MUTEX_INIT(&adapter->efuse_mutex); + PLTFM_MUTEX_INIT(&adapter->h2c_seq_mutex); + PLTFM_MUTEX_INIT(&adapter->sdio_indir_mutex); + +#if (HALMAC_PLATFORM_WINDOWS == 0) + +#if HALMAC_88XX_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8822B || + adapter->chip_id == HALMAC_CHIP_ID_8821C || + adapter->chip_id == HALMAC_CHIP_ID_8822C) { + init_adapter_param_88xx(adapter); + status = mount_api_88xx(adapter); + } +#endif + +#if HALMAC_88XX_V1_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8814B) { + init_adapter_param_88xx_v1(adapter); + status = mount_api_88xx_v1(adapter); + } +#endif + #else #if HALMAC_8822B_SUPPORT - if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8822B) { - halmac_init_adapter_para_win8822b(pHalmac_adapter); - status = halmac_mount_api_win8822b(pHalmac_adapter); + if (adapter->chip_id == HALMAC_CHIP_ID_8822B) { + init_adapter_param_win8822b(adapter); + status = mount_api_win8822b(adapter); } #endif + #if HALMAC_8821C_SUPPORT - if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) { - halmac_init_adapter_para_win8821c(pHalmac_adapter); - status = halmac_mount_api_win8821c(pHalmac_adapter); + if (adapter->chip_id == HALMAC_CHIP_ID_8821C) { + init_adapter_param_win8821c(adapter); + status = mount_api_win8821c(adapter); } #endif +#if HALMAC_8814B_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8814B) { + init_adapter_param_win8814b_v1(adapter); + status = mount_api_win8814b_v1(adapter); + } #endif - /* Return halmac API function pointer */ - *ppHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; +#if HALMAC_8822C_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8822C) { + init_adapter_param_win8822c(adapter); + status = mount_api_win8822c(adapter); + } +#endif + +#endif + *halmac_api = (struct halmac_api *)adapter->halmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_adapter_88xx <==========\n"); + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); return status; } /** * halmac_halt_api() - stop halmac_api action - * @pHalmac_adapter : the adapter of halmac + * @adapter : the adapter of halmac * Author : Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_halt_api( - IN PHALMAC_ADAPTER pHalmac_adapter -) +enum halmac_ret_status +halmac_halt_api(struct halmac_adapter *adapter) { - VOID *pDriver_adapter = NULL; - PHALMAC_PLATFORM_API pHalmac_platform_api = (PHALMAC_PLATFORM_API)NULL; + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; + adapter->halmac_state.api_state = HALMAC_API_STATE_HALT; - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_platform_api = pHalmac_adapter->pHalmac_platform_api; + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_halt_api ==========>\n"); - pHalmac_adapter->halmac_state.api_state = HALMAC_API_STATE_HALT; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_halt_api ==========>\n"); return HALMAC_RET_SUCCESS; } /** * halmac_deinit_adapter() - deinit halmac adapter - * @pHalmac_adapter : the adapter of halmac + * @adapter : the adapter of halmac * Author : KaiYuan Chang / Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_deinit_adapter( - IN PHALMAC_ADAPTER pHalmac_adapter -) +enum halmac_ret_status +halmac_deinit_adapter(struct halmac_adapter *adapter) { - VOID *pDriver_adapter = NULL; + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); - if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS) - return HALMAC_RET_ADAPTER_INVALID; + PLTFM_MUTEX_DEINIT(&adapter->efuse_mutex); + PLTFM_MUTEX_DEINIT(&adapter->h2c_seq_mutex); + PLTFM_MUTEX_DEINIT(&adapter->sdio_indir_mutex); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_deinit_adapter_88xx ==========>\n"); - - PLATFORM_MUTEX_DEINIT(pDriver_adapter, &pHalmac_adapter->EfuseMutex); - PLATFORM_MUTEX_DEINIT(pDriver_adapter, &pHalmac_adapter->h2c_seq_mutex); + if (adapter->efuse_map) { + PLTFM_FREE(adapter->efuse_map, adapter->hw_cfg_info.efuse_size); + adapter->efuse_map = (u8 *)NULL; + } - if (pHalmac_adapter->pHalEfuse_map != NULL) { - PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size); - pHalmac_adapter->pHalEfuse_map = (u8 *)NULL; + if (adapter->sdio_fs.macid_map) { + PLTFM_FREE(adapter->sdio_fs.macid_map, + adapter->sdio_fs.macid_map_size); + adapter->sdio_fs.macid_map = (u8 *)NULL; } - if (pHalmac_adapter->halmac_state.psd_set.pData != NULL) { - PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->halmac_state.psd_set.pData, pHalmac_adapter->halmac_state.psd_set.data_size); - pHalmac_adapter->halmac_state.psd_set.pData = (u8 *)NULL; + if (adapter->halmac_state.psd_state.data) { + PLTFM_FREE(adapter->halmac_state.psd_state.data, + adapter->halmac_state.psd_state.data_size); + adapter->halmac_state.psd_state.data = (u8 *)NULL; } - if (pHalmac_adapter->pHalmac_api != NULL) { - PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->pHalmac_api, sizeof(HALMAC_API)); - pHalmac_adapter->pHalmac_api = NULL; + if (adapter->halmac_api) { + PLTFM_FREE(adapter->halmac_api, sizeof(struct halmac_api)); + adapter->halmac_api = NULL; } - pHalmac_adapter->pHalAdapter_backup = NULL; - PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter, sizeof(HALMAC_ADAPTER)); + PLTFM_FREE(adapter, sizeof(*adapter)); return HALMAC_RET_SUCCESS; } -static HALMAC_RET_STATUS -halmac_check_platform_api( - IN VOID *pDriver_adapter, - IN HALMAC_INTERFACE halmac_interface, - IN PHALMAC_PLATFORM_API pHalmac_platform_api -) +static enum halmac_ret_status +chk_pltfm_api(void *drv_adapter, enum halmac_interface intf, + struct halmac_platform_api *pltfm_api) { - if (pHalmac_platform_api == NULL) + if (!pltfm_api) return HALMAC_RET_PLATFORM_API_NULL; - if (pHalmac_platform_api->MSG_PRINT == NULL) + if (!pltfm_api->MSG_PRINT) return HALMAC_RET_PLATFORM_API_NULL; - if (halmac_interface == HALMAC_INTERFACE_SDIO) { - if (pHalmac_platform_api->SDIO_CMD52_READ == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD52_READ)\n"); + if (intf == HALMAC_INTERFACE_SDIO) { + if (!pltfm_api->SDIO_CMD52_READ) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-r\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (!pltfm_api->SDIO_CMD53_READ_8) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-r8\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->SDIO_CMD53_READ_8 == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_8)\n"); + if (!pltfm_api->SDIO_CMD53_READ_16) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-r16\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->SDIO_CMD53_READ_16 == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_16)\n"); + if (!pltfm_api->SDIO_CMD53_READ_32) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-r32\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->SDIO_CMD53_READ_32 == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_32)\n"); + if (!pltfm_api->SDIO_CMD53_READ_N) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-rn\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->SDIO_CMD53_READ_N == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_N)\n"); + if (!pltfm_api->SDIO_CMD52_WRITE) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-w\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->SDIO_CMD52_WRITE == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD52_WRITE)\n"); + if (!pltfm_api->SDIO_CMD53_WRITE_8) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-w8\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->SDIO_CMD53_WRITE_8 == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_8)\n"); + if (!pltfm_api->SDIO_CMD53_WRITE_16) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-w16\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->SDIO_CMD53_WRITE_16 == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_16)\n"); + if (!pltfm_api->SDIO_CMD53_WRITE_32) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-w32\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->SDIO_CMD53_WRITE_32 == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_32)\n"); + if (!pltfm_api->SDIO_CMD52_CIA_READ) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-cia\n"); return HALMAC_RET_PLATFORM_API_NULL; } } - if ((halmac_interface == HALMAC_INTERFACE_USB) || (halmac_interface == HALMAC_INTERFACE_PCIE)) { - if (pHalmac_platform_api->REG_READ_8 == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_8)\n"); + if (intf == HALMAC_INTERFACE_USB || intf == HALMAC_INTERFACE_PCIE) { + if (!pltfm_api->REG_READ_8) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]reg-r8\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->REG_READ_16 == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_16)\n"); + if (!pltfm_api->REG_READ_16) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]reg-r16\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->REG_READ_32 == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_32)\n"); + if (!pltfm_api->REG_READ_32) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]reg-r32\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->REG_WRITE_8 == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_8)\n"); + if (!pltfm_api->REG_WRITE_8) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]reg-w8\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->REG_WRITE_16 == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_16)\n"); + if (!pltfm_api->REG_WRITE_16) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]reg-w16\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->REG_WRITE_32 == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_32)\n"); + if (!pltfm_api->REG_WRITE_32) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]reg-w32\n"); return HALMAC_RET_PLATFORM_API_NULL; } } - if (pHalmac_platform_api->RTL_FREE == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_FREE)\n"); + if (!pltfm_api->RTL_FREE) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mem-free\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->RTL_MALLOC == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MALLOC)\n"); + if (!pltfm_api->RTL_MALLOC) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mem-malloc\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->RTL_MEMCPY == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MEMCPY)\n"); + if (!pltfm_api->RTL_MEMCPY) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mem-cpy\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->RTL_MEMSET == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MEMSET)\n"); + if (!pltfm_api->RTL_MEMSET) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mem-set\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->RTL_DELAY_US == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_DELAY_US)\n"); + if (!pltfm_api->RTL_DELAY_US) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]time-delay\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->MUTEX_INIT == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_INIT)\n"); + if (!pltfm_api->MUTEX_INIT) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mutex-init\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->MUTEX_DEINIT == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_DEINIT)\n"); + if (!pltfm_api->MUTEX_DEINIT) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mutex-deinit\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->MUTEX_LOCK == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_LOCK)\n"); + if (!pltfm_api->MUTEX_LOCK) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mutex-lock\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->MUTEX_UNLOCK == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_UNLOCK)\n"); + if (!pltfm_api->MUTEX_UNLOCK) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mutex-unlock\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (pHalmac_platform_api->EVENT_INDICATION == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->EVENT_INDICATION)\n"); + if (!pltfm_api->EVENT_INDICATION) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]event-indication\n"); return HALMAC_RET_PLATFORM_API_NULL; } - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_check_platform_api ==========>\n"); - return HALMAC_RET_SUCCESS; } @@ -380,13 +439,11 @@ halmac_check_platform_api( * halmac_get_version() - get HALMAC version * @version : return version of major, prototype and minor information * Author : KaiYuan Chang / Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_get_version( - OUT HALMAC_VER *version -) +enum halmac_ret_status +halmac_get_version(struct halmac_ver *version) { version->major_ver = (u8)HALMAC_MAJOR_VER; version->prototype_ver = (u8)HALMAC_PROTOTYPE_VER; @@ -395,53 +452,53 @@ halmac_get_version( return HALMAC_RET_SUCCESS; } -static HALMAC_RET_STATUS -halmac_get_chip_info( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN HALMAC_INTERFACE halmac_interface, - IN PHALMAC_ADAPTER pHalmac_adapter -) +static enum halmac_ret_status +get_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api, + enum halmac_interface intf, struct halmac_adapter *adapter) { - PHALMAC_API pHalmac_api = (PHALMAC_API)NULL; - u8 chip_id, chip_version; - u32 polling_count; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - /* Get Chip_id and Chip_version */ - if (pHalmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) { - plarform_reg_write_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SDIO_HSUS_CTRL, platform_reg_read_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SDIO_HSUS_CTRL) & ~(BIT(0))); - - polling_count = 10000; - while (!(platform_reg_read_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SDIO_HSUS_CTRL) & 0x02)) { - polling_count--; - if (polling_count == 0) + u8 chip_id; + u8 chip_ver; + u32 cnt; + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + pltfm_reg_w8_sdio(drv_adapter, pltfm_api, REG_SDIO_HSUS_CTRL, + pltfm_reg_r8_sdio(drv_adapter, pltfm_api, + REG_SDIO_HSUS_CTRL) & + ~(BIT(0))); + + cnt = 10000; + while (!(pltfm_reg_r8_sdio(drv_adapter, pltfm_api, + REG_SDIO_HSUS_CTRL) & BIT(1))) { + cnt--; + if (cnt == 0) return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL; } - chip_id = platform_reg_read_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SYS_CFG2); - chip_version = platform_reg_read_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SYS_CFG1 + 1) >> 4; + chip_id = pltfm_reg_r_indir_sdio(drv_adapter, pltfm_api, + REG_SYS_CFG2); + chip_ver = pltfm_reg_r_indir_sdio(drv_adapter, pltfm_api, + REG_SYS_CFG1 + 1) >> 4; } else { - chip_id = pHalmac_platform_api->REG_READ_8(pDriver_adapter, REG_SYS_CFG2); - chip_version = pHalmac_platform_api->REG_READ_8(pDriver_adapter, REG_SYS_CFG1 + 1) >> 4; + chip_id = pltfm_api->REG_READ_8(drv_adapter, REG_SYS_CFG2); + chip_ver = pltfm_api->REG_READ_8(drv_adapter, + REG_SYS_CFG1 + 1) >> 4; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]Chip id : 0x%X\n", chip_id); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]Chip version : 0x%X\n", chip_version); - - pHalmac_adapter->chip_version = (HALMAC_CHIP_VER)chip_version; - - if (chip_id == HALMAC_CHIP_ID_HW_DEF_8822B) { - pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8822B; - } else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8821C) { - pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8821C; - } else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8814B) { - pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8814B; - } else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8197F) { - pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8197F; + adapter->chip_ver = (enum halmac_chip_ver)chip_ver; + + if (chip_id == CHIP_ID_HW_DEF_8822B) { + adapter->chip_id = HALMAC_CHIP_ID_8822B; + } else if (chip_id == CHIP_ID_HW_DEF_8821C) { + adapter->chip_id = HALMAC_CHIP_ID_8821C; + } else if (chip_id == CHIP_ID_HW_DEF_8814B) { + adapter->chip_id = HALMAC_CHIP_ID_8814B; + } else if (chip_id == CHIP_ID_HW_DEF_8197F) { + adapter->chip_id = HALMAC_CHIP_ID_8197F; + } else if (chip_id == CHIP_ID_HW_DEF_8822C) { + adapter->chip_id = HALMAC_CHIP_ID_8822C; } else { - pHalmac_adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE; + adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE; + PLTFM_MSG_ERR("[ERR]Chip id is undefined\n"); return HALMAC_RET_CHIP_NOT_SUPPORT; } @@ -449,72 +506,97 @@ halmac_get_chip_info( } static u8 -platform_reg_read_8_sdio( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN u32 offset -) +pltfm_reg_r8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api, + u32 offset) { u8 value8; - u32 halmac_offset = offset; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; - if (0 == (halmac_offset & 0xFFFF0000)) - halmac_offset |= WLAN_IOREG_OFFSET; + if (0 == (offset & 0xFFFF0000)) + offset |= WLAN_IOREG_OFFSET; - status = halmac_convert_to_sdio_bus_offset(&halmac_offset); - if (status != HALMAC_RET_SUCCESS) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "platform_reg_read_8_sdio error = %x\n", status); + status = cnv_to_sdio_bus_offset(&offset); + if (status != HALMAC_RET_SUCCESS) return status; - } - value8 = pHalmac_platform_api->SDIO_CMD52_READ(pDriver_adapter, halmac_offset); + value8 = pltfm_api->SDIO_CMD52_READ(drv_adapter, offset); return value8; } -static HALMAC_RET_STATUS -plarform_reg_write_8_sdio( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN u32 offset, - IN u8 data -) +static enum halmac_ret_status +pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api, + u32 offset, u8 data) { - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - u32 halmac_offset = offset; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; - if (0 == (halmac_offset & 0xFFFF0000)) - halmac_offset |= WLAN_IOREG_OFFSET; + if (0 == (offset & 0xFFFF0000)) + offset |= WLAN_IOREG_OFFSET; - status = halmac_convert_to_sdio_bus_offset(&halmac_offset); + status = cnv_to_sdio_bus_offset(&offset); - if (status != HALMAC_RET_SUCCESS) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_8_sdio_88xx error = %x\n", status); + if (status != HALMAC_RET_SUCCESS) return status; - } - pHalmac_platform_api->SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, data); + + pltfm_api->SDIO_CMD52_WRITE(drv_adapter, offset, data); return HALMAC_RET_SUCCESS; } +static u8 +pltfm_reg_r_indir_sdio(VOID *drv_adapter, struct halmac_platform_api *pltfm_api, + u32 offset) +{ + u8 value8, tmp, cnt = 50; + u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG; + u32 reg_data = REG_SDIO_INDIRECT_REG_DATA; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + status = cnv_to_sdio_bus_offset(®_cfg); + if (status != HALMAC_RET_SUCCESS) + return status; + status = cnv_to_sdio_bus_offset(®_data); + if (status != HALMAC_RET_SUCCESS) + return status; + + pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg, (u8)offset); + pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg + 1, + (u8)(offset >> 8)); + pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg + 2, + (u8)(BIT(3) | BIT(4))); -static HALMAC_RET_STATUS -halmac_convert_to_sdio_bus_offset( - INOUT u32 *halmac_offset -) + do { + tmp = pltfm_api->SDIO_CMD52_READ(drv_adapter, reg_cfg + 2); + cnt--; + } while (((tmp & BIT(4)) == 0) && (cnt > 0)); + + if (((cnt & BIT(4)) == 0) && cnt == 0) + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio indir read\n"); + + value8 = pltfm_api->SDIO_CMD52_READ(drv_adapter, reg_data); + + return value8; +} + +/*Note: copy from cnv_to_sdio_bus_offset_88xx*/ +static enum halmac_ret_status +cnv_to_sdio_bus_offset(u32 *offset) { - switch ((*halmac_offset) & 0xFFFF0000) { + switch ((*offset) & 0xFFFF0000) { case WLAN_IOREG_OFFSET: - *halmac_offset = (HALMAC_SDIO_CMD_ADDR_MAC_REG << 13) | (*halmac_offset & HALMAC_WLAN_MAC_REG_MSK); + *offset &= HALMAC_WLAN_MAC_REG_MSK; + *offset |= HALMAC_SDIO_CMD_ADDR_MAC_REG << 13; break; case SDIO_LOCAL_OFFSET: - *halmac_offset = (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | (*halmac_offset & HALMAC_SDIO_LOCAL_MSK); + *offset &= HALMAC_SDIO_LOCAL_MSK; + *offset |= HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13; break; default: - *halmac_offset = 0xFFFFFFFF; + *offset = 0xFFFFFFFF; return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL; } return HALMAC_RET_SUCCESS; } + diff --git a/hal/halmac/halmac_api.h b/hal/halmac/halmac_api.h index 8a1f35e..219bf60 100644 --- a/hal/halmac/halmac_api.h +++ b/hal/halmac/halmac_api.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,26 +16,64 @@ #ifndef _HALMAC_API_H_ #define _HALMAC_API_H_ -#define HALMAC_SVN_VER "13348M" +#define HALMAC_SVN_VER "11692M" -#define HALMAC_MAJOR_VER 0x0001 /* major version, ver_1 for async_api */ -#define HALMAC_PROTOTYPE_VER 0x0003 /* For halmac_api num change or prototype change, increment prototype version */ -#define HALMAC_MINOR_VER 0x0009 /* else increment minor version */ -#define HALMAC_PATCH_VER 0x0000 /* patch version */ +#define HALMAC_MAJOR_VER 0x0001 +#define HALMAC_PROTOTYPE_VER 0x0004 +#define HALMAC_MINOR_VER 0x0008 +#define HALMAC_PATCH_VER 0x0003 + +#define HALMAC_88XX_SUPPORT (HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define HALMAC_88XX_V1_SUPPORT HALMAC_8814B_SUPPORT #include "halmac_2_platform.h" -#include "halmac_hw_cfg.h" #include "halmac_type.h" - +#include "halmac_hw_cfg.h" #include "halmac_usb_reg.h" #include "halmac_sdio_reg.h" #include "halmac_pcie_reg.h" - #include "halmac_bit2.h" #include "halmac_reg2.h" +#if HALMAC_PLATFORM_TESTPROGRAM +#include "halmac_type_testprogram.h" +#endif + +#ifndef HALMAC_USE_TYPEDEF +#define HALMAC_USE_TYPEDEF 1 +#endif + +#if HALMAC_USE_TYPEDEF +#include "halmac_typedef.h" +#endif + +#if HALMAC_8822B_SUPPORT +#include "halmac_reg_8822b.h" +#include "halmac_bit_8822b.h" +#endif + +#if HALMAC_8821C_SUPPORT +#include "halmac_reg_8821c.h" +#include "halmac_bit_8821c.h" +#endif + +#if HALMAC_8814B_SUPPORT +#include "halmac_reg_8814b.h" +#include "halmac_bit_8814b.h" +#endif + +#if HALMAC_8822C_SUPPORT +#include "halmac_reg_8822c.h" +#include "halmac_bit_8822c.h" +#endif + #if (HALMAC_PLATFORM_WINDOWS || HALMAC_PLATFORM_LINUX) #include "halmac_tx_desc_nic.h" +#include "halmac_tx_desc_buffer_nic.h" +#include "halmac_tx_desc_ie_nic.h" #include "halmac_rx_desc_nic.h" #include "halmac_tx_bd_nic.h" #include "halmac_rx_bd_nic.h" @@ -49,8 +87,8 @@ #if (HALMAC_PLATFORM_AP) #include "halmac_rx_desc_ap.h" #include "halmac_tx_desc_ap.h" -#include "halmac_rx_bd_ap.h" -#include "halmac_tx_bd_ap.h" +#include "halmac_tx_desc_buffer_ap.h" +#include "halmac_tx_desc_ie_ap.h" #include "halmac_fw_offload_c2h_ap.h" #include "halmac_fw_offload_h2c_ap.h" #include "halmac_h2c_extra_info_ap.h" @@ -60,55 +98,22 @@ #include "halmac_tx_desc_chip.h" #include "halmac_rx_desc_chip.h" -#include "halmac_tx_bd_chip.h" -#include "halmac_rx_bd_chip.h" -#if HALMAC_PLATFORM_WINDOWS == 1 - -#if HALMAC_8822B_SUPPORT -#include "halmac_88xx/halmac_win8822b_cfg.h" -#endif -#if HALMAC_8821C_SUPPORT -#include "halmac_88xx/halmac_win8821c_cfg.h" -#endif +#include "halmac_tx_desc_buffer_chip.h" +#include "halmac_tx_desc_ie_chip.h" -#else -#include "halmac_88xx/halmac_88xx_cfg.h" -#endif +enum halmac_ret_status +halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api, + enum halmac_interface intf, + struct halmac_adapter **halmac_adapter, + struct halmac_api **halmac_api); -#if HALMAC_8822B_SUPPORT -#include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h" -#include "halmac_reg_8822b.h" -#include "halmac_bit_8822b.h" -#endif +enum halmac_ret_status +halmac_deinit_adapter(struct halmac_adapter *adapter); -#if HALMAC_8821C_SUPPORT -#include "halmac_88xx/halmac_8821c/halmac_8821c_cfg.h" -#include "halmac_reg_8821c.h" -#include "halmac_bit_8821c.h" -#endif +enum halmac_ret_status +halmac_halt_api(struct halmac_adapter *adapter); -HALMAC_RET_STATUS -halmac_init_adapter( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN HALMAC_INTERFACE halmac_interface, - OUT PHALMAC_ADAPTER *ppHalmac_adapter, - OUT PHALMAC_API *ppHalmac_api -); - -HALMAC_RET_STATUS -halmac_deinit_adapter( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_halt_api( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_get_version( - OUT HALMAC_VER *version -); +enum halmac_ret_status +halmac_get_version(struct halmac_ver *version); #endif diff --git a/hal/halmac/halmac_bit2.h b/hal/halmac/halmac_bit2.h index cda17c6..d54ba86 100644 --- a/hal/halmac/halmac_bit2.h +++ b/hal/halmac/halmac_bit2.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,34880 +16,63915 @@ #ifndef __RTL_WLAN_BITDEF_H__ #define __RTL_WLAN_BITDEF_H__ -/*-------------------------Modification Log----------------------------------- - Base on MAC_Register.doc SVN391 --------------------------Modification Log-----------------------------------*/ - -/*--------------------------Include File--------------------------------------*/ #include "halmac_hw_cfg.h" -/*--------------------------Include File--------------------------------------*/ -/* 3 ============Programming guide Start===================== */ -/* - 1. For all bit define, it should be prefixed by "BIT_" - 2. For all bit mask, it should be prefixed by "BIT_MASK_" - 3. For all bit shift, it should be prefixed by "BIT_SHIFT_" - 4. For other case, prefix is not needed +#define CPU_OPT_WIDTH 0x1F -Example: -#define BIT_SHIFT_MAX_TXDMA 16 -#define BIT_MASK_MAX_TXDMA 0x7 -#define BIT_MAX_TXDMA(x) (((x) & BIT_MASK_MAX_TXDMA)<> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA) +#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME BIT(31) -*/ -/* 3 ============Programming guide End===================== */ +#define BIT_SHIFT_GTAB_ID 28 +#define BIT_MASK_GTAB_ID 0x7 +#define BIT_GTAB_ID(x) (((x) & BIT_MASK_GTAB_ID) << BIT_SHIFT_GTAB_ID) +#define BITS_GTAB_ID (BIT_MASK_GTAB_ID << BIT_SHIFT_GTAB_ID) +#define BIT_CLEAR_GTAB_ID(x) ((x) & (~BITS_GTAB_ID)) +#define BIT_GET_GTAB_ID(x) (((x) >> BIT_SHIFT_GTAB_ID) & BIT_MASK_GTAB_ID) +#define BIT_SET_GTAB_ID(x, v) (BIT_CLEAR_GTAB_ID(x) | BIT_GTAB_ID(v)) -#define CPU_OPT_WIDTH 0x1F +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_MULRW BIT(27) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_CPRST BIT(23) + +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WATCH_DOG_RECORD_V1 10 -#define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff -#define BIT_WATCH_DOG_RECORD_V1(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1) -#define BIT_GET_WATCH_DOG_RECORD_V1(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1) +#define BIT_SHIFT_COUNTER_BASE 16 +#define BIT_MASK_COUNTER_BASE 0x1fff +#define BIT_COUNTER_BASE(x) \ + (((x) & BIT_MASK_COUNTER_BASE) << BIT_SHIFT_COUNTER_BASE) +#define BITS_COUNTER_BASE (BIT_MASK_COUNTER_BASE << BIT_SHIFT_COUNTER_BASE) +#define BIT_CLEAR_COUNTER_BASE(x) ((x) & (~BITS_COUNTER_BASE)) +#define BIT_GET_COUNTER_BASE(x) \ + (((x) >> BIT_SHIFT_COUNTER_BASE) & BIT_MASK_COUNTER_BASE) +#define BIT_SET_COUNTER_BASE(x, v) \ + (BIT_CLEAR_COUNTER_BASE(x) | BIT_COUNTER_BASE(v)) -#define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9) +#define BIT_SHIFT_AGG_VALUE2 16 +#define BIT_MASK_AGG_VALUE2 0x7f +#define BIT_AGG_VALUE2(x) (((x) & BIT_MASK_AGG_VALUE2) << BIT_SHIFT_AGG_VALUE2) +#define BITS_AGG_VALUE2 (BIT_MASK_AGG_VALUE2 << BIT_SHIFT_AGG_VALUE2) +#define BIT_CLEAR_AGG_VALUE2(x) ((x) & (~BITS_AGG_VALUE2)) +#define BIT_GET_AGG_VALUE2(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE2) & BIT_MASK_AGG_VALUE2) +#define BIT_SET_AGG_VALUE2(x, v) (BIT_CLEAR_AGG_VALUE2(x) | BIT_AGG_VALUE2(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1 BIT(15) -#define BIT_EN_WATCH_DOG_V1 BIT(8) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define BIT_SHIFT_XTAL_DRV_RF1 13 +#define BIT_MASK_XTAL_DRV_RF1 0x3 +#define BIT_XTAL_DRV_RF1(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1) +#define BITS_XTAL_DRV_RF1 (BIT_MASK_XTAL_DRV_RF1 << BIT_SHIFT_XTAL_DRV_RF1) +#define BIT_CLEAR_XTAL_DRV_RF1(x) ((x) & (~BITS_XTAL_DRV_RF1)) +#define BIT_GET_XTAL_DRV_RF1(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1) +#define BIT_SET_XTAL_DRV_RF1(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF1(x) | BIT_XTAL_DRV_RF1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +#define BIT_ATIMEND BIT(12) -#define BIT_AFE_MBIAS BIT(1) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define BIT_SHIFT_GTAB_ID_V1 12 +#define BIT_MASK_GTAB_ID_V1 0x7 +#define BIT_GTAB_ID_V1(x) (((x) & BIT_MASK_GTAB_ID_V1) << BIT_SHIFT_GTAB_ID_V1) +#define BITS_GTAB_ID_V1 (BIT_MASK_GTAB_ID_V1 << BIT_SHIFT_GTAB_ID_V1) +#define BIT_CLEAR_GTAB_ID_V1(x) ((x) & (~BITS_GTAB_ID_V1)) +#define BIT_GET_GTAB_ID_V1(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1) & BIT_MASK_GTAB_ID_V1) +#define BIT_SET_GTAB_ID_V1(x, v) (BIT_CLEAR_GTAB_ID_V1(x) | BIT_GTAB_ID_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define BIT_SHIFT_WATCH_DOG_RECORD_V1 10 +#define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff +#define BIT_WATCH_DOG_RECORD_V1(x) \ + (((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1) +#define BITS_WATCH_DOG_RECORD_V1 \ + (BIT_MASK_WATCH_DOG_RECORD_V1 << BIT_SHIFT_WATCH_DOG_RECORD_V1) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1(x) ((x) & (~BITS_WATCH_DOG_RECORD_V1)) +#define BIT_GET_WATCH_DOG_RECORD_V1(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1) +#define BIT_SET_WATCH_DOG_RECORD_V1(x, v) \ + (BIT_CLEAR_WATCH_DOG_RECORD_V1(x) | BIT_WATCH_DOG_RECORD_V1(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_ISO_MD2PP BIT(0) +#define BIT_R_8051_SPD BIT(9) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_EN_RTS_REQ BIT(9) +#endif -#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0 -#define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) -#define BIT_GET_R_WMAC_IPV6_MYIPAD(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_EN_EDCA_REQ BIT(8) +#define BIT_SHIFT_AGG_VALUE1 8 +#define BIT_MASK_AGG_VALUE1 0x7f +#define BIT_AGG_VALUE1(x) (((x) & BIT_MASK_AGG_VALUE1) << BIT_SHIFT_AGG_VALUE1) +#define BITS_AGG_VALUE1 (BIT_MASK_AGG_VALUE1 << BIT_SHIFT_AGG_VALUE1) +#define BIT_CLEAR_AGG_VALUE1(x) ((x) & (~BITS_AGG_VALUE1)) +#define BIT_GET_AGG_VALUE1(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE1) & BIT_MASK_AGG_VALUE1) +#define BIT_SET_AGG_VALUE1(x, v) (BIT_CLEAR_AGG_VALUE1(x) | BIT_AGG_VALUE1(v)) -/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_EN_WATCH_DOG_V1 BIT(8) -#define BIT_SHIFT_SDIO_INT_TIMEOUT 16 -#define BIT_MASK_SDIO_INT_TIMEOUT 0xffff -#define BIT_SDIO_INT_TIMEOUT(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT) -#define BIT_GET_SDIO_INT_TIMEOUT(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +#define BIT_DIS_TXDMA_PRE BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_RAM_DL_SEL BIT(7) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_PWC_EV12V BIT(15) +#define BIT_EN_PTCL_REQ BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#define BIT_DIS_RXDMA_PRE BIT(6) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_PWC_EBCOEB BIT(15) +#define BIT_WINTINI_RDY BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_EN_SCH_REQ BIT(6) +#endif -/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#if (HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_IO_ERR_STATUS BIT(15) +#define BIT_CLR_HGQ_REQ_BLOCK BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_TXFLAG_EXIT_L1_EN BIT(2) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8881A_SUPPORT) -#define BIT_PWC_EV25V BIT(14) +#define BIT_AFE_MBIAS BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_MCUFWDL_EN BIT(0) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_PA33V_EN BIT(13) -#define BIT_PA12V_EN BIT(12) +#define BIT_SHIFT_AGG_VALUE0 0 +#define BIT_MASK_AGG_VALUE0 0x7f +#define BIT_AGG_VALUE0(x) (((x) & BIT_MASK_AGG_VALUE0) << BIT_SHIFT_AGG_VALUE0) +#define BITS_AGG_VALUE0 (BIT_MASK_AGG_VALUE0 << BIT_SHIFT_AGG_VALUE0) +#define BIT_CLEAR_AGG_VALUE0(x) ((x) & (~BITS_AGG_VALUE0)) +#define BIT_GET_AGG_VALUE0(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE0) & BIT_MASK_AGG_VALUE0) +#define BIT_SET_AGG_VALUE0(x, v) (BIT_CLEAR_AGG_VALUE0(x) | BIT_AGG_VALUE0(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#define BIT_SHIFT_MDIO_REG_ADDR 0 +#define BIT_MASK_MDIO_REG_ADDR 0x1f +#define BIT_MDIO_REG_ADDR(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR) << BIT_SHIFT_MDIO_REG_ADDR) +#define BITS_MDIO_REG_ADDR (BIT_MASK_MDIO_REG_ADDR << BIT_SHIFT_MDIO_REG_ADDR) +#define BIT_CLEAR_MDIO_REG_ADDR(x) ((x) & (~BITS_MDIO_REG_ADDR)) +#define BIT_GET_MDIO_REG_ADDR(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR) & BIT_MASK_MDIO_REG_ADDR) +#define BIT_SET_MDIO_REG_ADDR(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR(x) | BIT_MDIO_REG_ADDR(v)) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_PC_A15V BIT(12) +#define BIT_ISO_MD2PP BIT(0) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ + +#define BIT_SHIFT_SDIO_INT_TIMEOUT 16 +#define BIT_MASK_SDIO_INT_TIMEOUT 0xffff +#define BIT_SDIO_INT_TIMEOUT(x) \ + (((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT) +#define BITS_SDIO_INT_TIMEOUT \ + (BIT_MASK_SDIO_INT_TIMEOUT << BIT_SHIFT_SDIO_INT_TIMEOUT) +#define BIT_CLEAR_SDIO_INT_TIMEOUT(x) ((x) & (~BITS_SDIO_INT_TIMEOUT)) +#define BIT_GET_SDIO_INT_TIMEOUT(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT) +#define BIT_SET_SDIO_INT_TIMEOUT(x, v) \ + (BIT_CLEAR_SDIO_INT_TIMEOUT(x) | BIT_SDIO_INT_TIMEOUT(v)) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_UA33V_EN BIT(11) -#define BIT_UA12V_EN BIT(10) +#define BIT_PWC_EV12V BIT(15) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_AFE_OUTPUT_SIGNAL BIT(10) +#define BIT_PWC_EBCOEB BIT(15) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ + +#define BIT_IO_ERR_STATUS BIT(15) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_RFDIO BIT(9) +#define BIT_PWC_EV25V BIT(14) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#define BIT_CMD53_W_MIX BIT(14) -/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_REPLY_ERRCRC_IN_DATA BIT(9) +#define BIT_PA33V_EN BIT(13) #endif +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ + +#define BIT_CMD53_TX_FORMAT BIT(13) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_EB2CORE BIT(8) +#define BIT_PA12V_EN BIT(12) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_PC_A15V BIT(12) + +#endif + +#if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_EN_CMD53_OVERLAP BIT(8) +#define BIT_CMD53_R_TIMEOUT_MASK BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ + +#define BIT_UA33V_EN BIT(11) +#define BIT_UA12V_EN BIT(10) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_DIOE BIT(7) +#define BIT_ISO_AFE_OUTPUT_SIGNAL BIT(10) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#define BIT_SHIFT_CMD53_R_TIMEOUT_UNIT 10 +#define BIT_MASK_CMD53_R_TIMEOUT_UNIT 0x3 +#define BIT_CMD53_R_TIMEOUT_UNIT(x) \ + (((x) & BIT_MASK_CMD53_R_TIMEOUT_UNIT) \ + << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) +#define BITS_CMD53_R_TIMEOUT_UNIT \ + (BIT_MASK_CMD53_R_TIMEOUT_UNIT << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) +#define BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) ((x) & (~BITS_CMD53_R_TIMEOUT_UNIT)) +#define BIT_GET_CMD53_R_TIMEOUT_UNIT(x) \ + (((x) >> BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) & \ + BIT_MASK_CMD53_R_TIMEOUT_UNIT) +#define BIT_SET_CMD53_R_TIMEOUT_UNIT(x, v) \ + (BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) | BIT_CMD53_R_TIMEOUT_UNIT(v)) -/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#endif -#define BIT_REPLY_ERR_IN_R5 BIT(7) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ + +#define BIT_ISO_RFDIO BIT(9) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ + +#define BIT_REPLY_ERRCRC_IN_DATA BIT(9) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_DIOP BIT(6) +#define BIT_ISO_EB2CORE BIT(8) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#define BIT_EN_CMD53_OVERLAP BIT(8) -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#endif -#define BIT_ISO_WLPON2PP BIT(6) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_ISO_DIOE BIT(7) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_R18A_EN BIT(6) +#define BIT_REPLY_ERR_IN_R5 BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ + +#define BIT_ISO_DIOP BIT(6) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_IP2MAC_WA2PP BIT(5) +#define BIT_ISO_WLPON2PP BIT(6) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ + +#define BIT_R18A_EN BIT(6) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_INIT_CMD_EN BIT(5) +#define BIT_ISO_IP2MAC_WA2PP BIT(5) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ + +#define BIT_SDIO_CMD_FORCE_VLD BIT(5) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_PD2CORE BIT(4) +#define BIT_ISO_PD2CORE BIT(4) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ + +#define BIT_INIT_CMD_EN BIT(4) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_PA2PCIE BIT(3) +#define BIT_ISO_PA2PCIE BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_EN_32K_TRANS BIT(3) +#define BIT_EN_32K_TRANS BIT(3) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#define BIT_RXINT_READ_MASK_DIS BIT(3) -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#endif -#define BIT_ISO_UD2CORE BIT(2) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_ISO_UD2CORE BIT(2) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_EN_RXDMA_MASK_INT BIT(2) +#define BIT_EN_RXDMA_MASK_INT BIT(2) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_HD2CORE BIT(2) +#define BIT_ISO_HD2CORE BIT(2) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_UA2USB BIT(1) +#define BIT_ISO_UA2USB BIT(1) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_EN_MASK_TIMER BIT(1) +#define BIT_EN_MASK_TIMER BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_WD2PP BIT(0) +#define BIT_ISO_WD2PP BIT(0) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_CMD_ERR_STOP_INT_EN BIT(0) +#define BIT_CMD_ERR_STOP_INT_EN BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ -#define BIT_FEN_MREGEN BIT(15) -#define BIT_FEN_HWPDN BIT(14) +#define BIT_FEN_MREGEN BIT(15) +#define BIT_FEN_HWPDN BIT(14) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ -#define BIT_EN_25_1 BIT(13) +#define BIT_EN_25_1 BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ -#define BIT_FEN_ELDR BIT(12) -#define BIT_FEN_DCORE BIT(11) -#define BIT_FEN_CPUEN BIT(10) -#define BIT_FEN_DIOE BIT(9) -#define BIT_FEN_PCIED BIT(8) -#define BIT_FEN_PPLL BIT(7) -#define BIT_FEN_PCIEA BIT(6) -#define BIT_FEN_DIO_PCIE BIT(5) -#define BIT_FEN_USBD BIT(4) -#define BIT_FEN_UPLL BIT(3) -#define BIT_FEN_USBA BIT(2) +#define BIT_FEN_ELDR BIT(12) +#define BIT_FEN_DCORE BIT(11) +#define BIT_FEN_CPUEN BIT(10) +#define BIT_FEN_DIOE BIT(9) +#define BIT_FEN_PCIED BIT(8) +#define BIT_FEN_PPLL BIT(7) +#define BIT_FEN_PCIEA BIT(6) +#define BIT_FEN_DIO_PCIE BIT(5) +#define BIT_FEN_USBD BIT(4) +#define BIT_FEN_UPLL BIT(3) +#define BIT_FEN_USBA BIT(2) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ -#define BIT_FEN_BB_GLB_RSTN BIT(1) -#define BIT_FEN_BBRSTB BIT(0) +#define BIT_FEN_BB_GLB_RSTN BIT(1) +#define BIT_FEN_BBRSTB BIT(0) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SOP_EABM BIT(31) +#define BIT_SOP_EABM BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SKP_ALD BIT(31) +#define BIT_SKP_ALD BIT(31) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SOP_ACKF BIT(30) -#define BIT_SOP_ERCK BIT(29) +#define BIT_SOP_ACKF BIT(30) +#define BIT_SOP_ERCK BIT(29) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SOP_ESWR BIT(28) +#define BIT_SOP_ESWR BIT(28) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SOP_AFEP BIT(28) +#define BIT_SOP_AFEP BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SOP_PWMM BIT(27) +#define BIT_SOP_PWMM BIT(27) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SOP_EPWM BIT(27) +#define BIT_SOP_EPWM BIT(27) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SOP_EECK BIT(26) +#define BIT_SOP_EECK BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_ROP_ENXT BIT(25) +#define BIT_ROP_ENXT BIT(25) #endif +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ + +#define BIT_SOP_ANA_CLK_DIVISION_2 BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SOP_EXTL BIT(24) +#define BIT_SOP_EXTL BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_CHIPOFF_EN BIT(23) +#define BIT_CHIPOFF_EN BIT(23) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SYM_OP_RING_12M BIT(22) +#define BIT_SYM_OP_RING_12M BIT(22) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_DIS_USB3_SUS_ALD BIT(22) +#define BIT_DIS_USB3_SUS_ALD BIT(22) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_ROP_SWPR BIT(21) +#define BIT_ROP_SWPR BIT(21) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_DIS_HW_LPLDM BIT(20) +#define BIT_DIS_HW_LPLDM BIT(20) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SOP_ALD BIT(20) +#define BIT_SOP_ALD BIT(20) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_OPT_SWRST_WLMCU BIT(19) -#define BIT_RDY_SYSPWR BIT(17) +#define BIT_OPT_SWRST_WLMCU BIT(19) +#define BIT_RDY_SYSPWR BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_EN_WLON BIT(16) +#define BIT_EN_WLON BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_APDM_HPDN BIT(15) +#define BIT_APDM_HPDN BIT(15) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_HSUS BIT(14) -#define BIT_PDN_SEL BIT(13) +#define BIT_HSUS BIT(14) +#define BIT_PDN_SEL BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_AFSM_PCIE_SUS_EN BIT(12) +#define BIT_AFSM_PCIE_SUS_EN BIT(12) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_AFSM_WLSUS_EN BIT(11) +#define BIT_AFSM_WLSUS_EN BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_APFM_SWLPS BIT(10) +#define BIT_APFM_SWLPS BIT(10) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_APFM_SWLPS_EN BIT(10) +#define BIT_APFM_SWLPS_EN BIT(10) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_APFM_OFFMAC BIT(9) -#define BIT_APFN_ONMAC BIT(8) +#define BIT_APFM_OFFMAC BIT(9) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_CHIP_PDN_EN BIT(7) +#define BIT_HW_AUTO_CTRL_EXT_SWR BIT(9) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_BT_SUSEN BIT(7) +#define BIT_APFN_ONMAC BIT(8) #endif +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ + +#define BIT_USE_INTERNAL_SWR_AND_LDO BIT(8) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_RDY_MACDIS BIT(6) +#define BIT_CHIP_PDN_EN BIT(7) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_PD_RF BIT(5) +#define BIT_BT_SUSEN BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_RING_CLK_12M_EN BIT(4) +#define BIT_RDY_MACDIS BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_ENPDN BIT(4) +#define BIT_PD_RF BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_PFM_WOWL BIT(3) +#define BIT_RING_CLK_12M_EN BIT(4) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SW_WAKE BIT(3) +#define BIT_ENPDN BIT(4) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_CMD11_VOL_SWITCH (Offset 0x10250004) */ - -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ - -#define BIT_PFM_LDKP BIT(2) +#define BIT_SHIFT_CMD11_SEQ_END_DELAY 4 +#define BIT_MASK_CMD11_SEQ_END_DELAY 0xf +#define BIT_CMD11_SEQ_END_DELAY(x) \ + (((x) & BIT_MASK_CMD11_SEQ_END_DELAY) << BIT_SHIFT_CMD11_SEQ_END_DELAY) +#define BITS_CMD11_SEQ_END_DELAY \ + (BIT_MASK_CMD11_SEQ_END_DELAY << BIT_SHIFT_CMD11_SEQ_END_DELAY) +#define BIT_CLEAR_CMD11_SEQ_END_DELAY(x) ((x) & (~BITS_CMD11_SEQ_END_DELAY)) +#define BIT_GET_CMD11_SEQ_END_DELAY(x) \ + (((x) >> BIT_SHIFT_CMD11_SEQ_END_DELAY) & BIT_MASK_CMD11_SEQ_END_DELAY) +#define BIT_SET_CMD11_SEQ_END_DELAY(x, v) \ + (BIT_CLEAR_CMD11_SEQ_END_DELAY(x) | BIT_CMD11_SEQ_END_DELAY(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_WL_HCI_ALD BIT(1) +#define BIT_PFM_WOWL BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_PFM_ALDN BIT(1) +#define BIT_SW_WAKE BIT(3) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_PFM_LDALL BIT(0) +#define BIT_PFM_LDKP BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_LDO_DUMMY BIT(15) +#define BIT_WL_HCI_ALD BIT(1) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ - -#define BIT_ANA_CLK_EN BIT(15) +#define BIT_PFM_ALDN BIT(1) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_ANA_CLK_DIVISION_2 BIT(1) -#define BIT_CPU_CLK_EN BIT(14) +#define BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL 1 +#define BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL 0x7 +#define BIT_CMD11_SEQ_SAMPLE_INTERVAL(x) \ + (((x) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL) \ + << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) +#define BITS_CMD11_SEQ_SAMPLE_INTERVAL \ + (BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL \ + << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) +#define BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x) \ + ((x) & (~BITS_CMD11_SEQ_SAMPLE_INTERVAL)) +#define BIT_GET_CMD11_SEQ_SAMPLE_INTERVAL(x) \ + (((x) >> BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) & \ + BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL) +#define BIT_SET_CMD11_SEQ_SAMPLE_INTERVAL(x, v) \ + (BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x) | \ + BIT_CMD11_SEQ_SAMPLE_INTERVAL(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_PFM_LDALL BIT(0) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_SDIO_CMD11_VOL_SWITCH (Offset 0x10250004) */ + +#define BIT_CMD11_SEQ_EN BIT(0) + +/* 2 REG_SDIO_DRIVING (Offset 0x10250006) */ + +#define BIT_SHIFT_SDIO_DRV_TYPE_D 12 +#define BIT_MASK_SDIO_DRV_TYPE_D 0xf +#define BIT_SDIO_DRV_TYPE_D(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_D) << BIT_SHIFT_SDIO_DRV_TYPE_D) +#define BITS_SDIO_DRV_TYPE_D \ + (BIT_MASK_SDIO_DRV_TYPE_D << BIT_SHIFT_SDIO_DRV_TYPE_D) +#define BIT_CLEAR_SDIO_DRV_TYPE_D(x) ((x) & (~BITS_SDIO_DRV_TYPE_D)) +#define BIT_GET_SDIO_DRV_TYPE_D(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_D) & BIT_MASK_SDIO_DRV_TYPE_D) +#define BIT_SET_SDIO_DRV_TYPE_D(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_D(x) | BIT_SDIO_DRV_TYPE_D(v)) + +#define BIT_SHIFT_SDIO_DRV_TYPE_C 8 +#define BIT_MASK_SDIO_DRV_TYPE_C 0xf +#define BIT_SDIO_DRV_TYPE_C(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_C) << BIT_SHIFT_SDIO_DRV_TYPE_C) +#define BITS_SDIO_DRV_TYPE_C \ + (BIT_MASK_SDIO_DRV_TYPE_C << BIT_SHIFT_SDIO_DRV_TYPE_C) +#define BIT_CLEAR_SDIO_DRV_TYPE_C(x) ((x) & (~BITS_SDIO_DRV_TYPE_C)) +#define BIT_GET_SDIO_DRV_TYPE_C(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_C) & BIT_MASK_SDIO_DRV_TYPE_C) +#define BIT_SET_SDIO_DRV_TYPE_C(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_C(x) | BIT_SDIO_DRV_TYPE_C(v)) + +#define BIT_SHIFT_SDIO_DRV_TYPE_B 4 +#define BIT_MASK_SDIO_DRV_TYPE_B 0xf +#define BIT_SDIO_DRV_TYPE_B(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_B) << BIT_SHIFT_SDIO_DRV_TYPE_B) +#define BITS_SDIO_DRV_TYPE_B \ + (BIT_MASK_SDIO_DRV_TYPE_B << BIT_SHIFT_SDIO_DRV_TYPE_B) +#define BIT_CLEAR_SDIO_DRV_TYPE_B(x) ((x) & (~BITS_SDIO_DRV_TYPE_B)) +#define BIT_GET_SDIO_DRV_TYPE_B(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_B) & BIT_MASK_SDIO_DRV_TYPE_B) +#define BIT_SET_SDIO_DRV_TYPE_B(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_B(x) | BIT_SDIO_DRV_TYPE_B(v)) + +#define BIT_SHIFT_SDIO_DRV_TYPE_A 0 +#define BIT_MASK_SDIO_DRV_TYPE_A 0xf +#define BIT_SDIO_DRV_TYPE_A(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_A) << BIT_SHIFT_SDIO_DRV_TYPE_A) +#define BITS_SDIO_DRV_TYPE_A \ + (BIT_MASK_SDIO_DRV_TYPE_A << BIT_SHIFT_SDIO_DRV_TYPE_A) +#define BIT_CLEAR_SDIO_DRV_TYPE_A(x) ((x) & (~BITS_SDIO_DRV_TYPE_A)) +#define BIT_GET_SDIO_DRV_TYPE_A(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_A) & BIT_MASK_SDIO_DRV_TYPE_A) +#define BIT_SET_SDIO_DRV_TYPE_A(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_A(x) | BIT_SDIO_DRV_TYPE_A(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_SYMREG_CLK_EN BIT(13) +#define BIT_CPHY_LDO_CL_EN BIT(19) +#define BIT_CPHY_LDO_OK BIT(18) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_RING_CLK_EN BIT(13) +#define BIT_LDO_DUMMY BIT(15) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_HCI_CLK_EN BIT(12) +#define BIT_ANA_CLK_EN BIT(15) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_SYS_CLK_EN BIT(12) +#define BIT_DATA_CPU_CLK_EN BIT(15) +#define BIT_DATA_CPU_PWC BIT(15) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_MAC_CLK_EN BIT(11) -#define BIT_SEC_CLK_EN BIT(10) +#define BIT_CPU_CLK_EN BIT(14) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_PHY_SSC_RSTB BIT(9) -#define BIT_EXT_32K_EN BIT(8) +#define BIT_SYMREG_CLK_EN BIT(13) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_EXT32K_EN BIT(8) +#define BIT_RING_CLK_EN BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_WL_CLK_TEST BIT(7) -#define BIT_OP_SPS_PWM_EN BIT(6) +#define BIT_HCI_CLK_EN BIT(12) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_SYS_CLK_EN BIT(12) -#define BIT_SHIFT_MAC_CLK_SEL_V1 6 -#define BIT_MASK_MAC_CLK_SEL_V1 0x3 -#define BIT_MAC_CLK_SEL_V1(x) (((x) & BIT_MASK_MAC_CLK_SEL_V1) << BIT_SHIFT_MAC_CLK_SEL_V1) -#define BIT_GET_MAC_CLK_SEL_V1(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_V1) & BIT_MASK_MAC_CLK_SEL_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_MAC_CLK_EN BIT(11) +#define BIT_SEC_CLK_EN BIT(10) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_LOADER_CLK_EN BIT(5) -#define BIT_MACSLP BIT(4) -#define BIT_WAKEPAD_EN BIT(3) -#define BIT_ROMD16V_EN BIT(2) +#define BIT_CTRL_SPS_PWM_FREQ BIT(10) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_CKANA8M_EN BIT(1) +#define BIT_PHY_SSC_RSTB BIT(9) +#define BIT_EXT_32K_EN BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_CKANA12M_EN BIT(1) +#define BIT_EXT32K_EN BIT(8) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_ANA8M_EN BIT(1) +#define BIT_DISABLE_OPEN_SPS_LDO BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_CNTD16V_EN BIT(0) +#define BIT_WL_CLK_TEST BIT(7) +#define BIT_OP_SPS_PWM_EN BIT(6) -/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_VPDIDX 8 -#define BIT_MASK_VPDIDX 0xff -#define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX) -#define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_SHIFT_MAC_CLK_SEL_V1 6 +#define BIT_MASK_MAC_CLK_SEL_V1 0x3 +#define BIT_MAC_CLK_SEL_V1(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL_V1) << BIT_SHIFT_MAC_CLK_SEL_V1) +#define BITS_MAC_CLK_SEL_V1 \ + (BIT_MASK_MAC_CLK_SEL_V1 << BIT_SHIFT_MAC_CLK_SEL_V1) +#define BIT_CLEAR_MAC_CLK_SEL_V1(x) ((x) & (~BITS_MAC_CLK_SEL_V1)) +#define BIT_GET_MAC_CLK_SEL_V1(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL_V1) & BIT_MASK_MAC_CLK_SEL_V1) +#define BIT_SET_MAC_CLK_SEL_V1(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL_V1(x) | BIT_MAC_CLK_SEL_V1(v)) -#define BIT_SHIFT_EEM1_0 6 -#define BIT_MASK_EEM1_0 0x3 -#define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0) -#define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0) +#endif -#define BIT_AUTOLOAD_SUS BIT(5) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_LOADER_CLK_EN BIT(5) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_EERPOMSEL BIT(4) +#define BIT_POW_PC_LDO3 BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_MACSLP BIT(4) -/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +#endif -#define BIT_EEPROMSEL BIT(4) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_POW_PC_LDO2 BIT(4) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_EECS_V1 BIT(3) -#define BIT_EESK_V1 BIT(2) -#define BIT_EEDI_V1 BIT(1) -#define BIT_EEDO_V1 BIT(0) +#define BIT_WAKEPAD_EN BIT(3) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_ENB_LDO_DIODE_L BIT(3) +#define BIT_POW_PC_LDO1 BIT(3) -/* 2 REG_EE_VPD (Offset 0x000C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VPD_DATA 0 -#define BIT_MASK_VPD_DATA 0xffffffffL -#define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA) -#define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_ROMD16V_EN BIT(2) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_AFE_BGEN_PCIE_OP BIT(2) +#define BIT_POW_PC_LDO0 BIT(2) -/* 2 REG_EE_VPD (Offset 0x000C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VDP_DATA 0 -#define BIT_MASK_VDP_DATA 0xffffffffL -#define BIT_VDP_DATA(x) (((x) & BIT_MASK_VDP_DATA) << BIT_SHIFT_VDP_DATA) -#define BIT_GET_VDP_DATA(x) (((x) >> BIT_SHIFT_VDP_DATA) & BIT_MASK_VDP_DATA) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_CKANA8M_EN BIT(1) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_CKANA12M_EN BIT(1) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif -#define BIT_SW18_C2_BIT0 BIT(31) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_ANA8M_EN BIT(1) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_C2_L_BIT0 BIT(31) +#define BIT_CNTD16V_EN BIT(0) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_POW_POWER_CUT BIT(0) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R1_L1_V1 30 -#define BIT_MASK_R1_L1_V1 0x3 -#define BIT_R1_L1_V1(x) (((x) & BIT_MASK_R1_L1_V1) << BIT_SHIFT_R1_L1_V1) -#define BIT_GET_R1_L1_V1(x) (((x) >> BIT_SHIFT_R1_L1_V1) & BIT_MASK_R1_L1_V1) +/* 2 REG_SDIO_MONITOR (Offset 0x10250008) */ +#define BIT_SHIFT_SDIO_INT_START 0 +#define BIT_MASK_SDIO_INT_START 0xffffffffL +#define BIT_SDIO_INT_START(x) \ + (((x) & BIT_MASK_SDIO_INT_START) << BIT_SHIFT_SDIO_INT_START) +#define BITS_SDIO_INT_START \ + (BIT_MASK_SDIO_INT_START << BIT_SHIFT_SDIO_INT_START) +#define BIT_CLEAR_SDIO_INT_START(x) ((x) & (~BITS_SDIO_INT_START)) +#define BIT_GET_SDIO_INT_START(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_START) & BIT_MASK_SDIO_INT_START) +#define BIT_SET_SDIO_INT_START(x, v) \ + (BIT_CLEAR_SDIO_INT_START(x) | BIT_SDIO_INT_START(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +#define BIT_SHIFT_VPDIDX 8 +#define BIT_MASK_VPDIDX 0xff +#define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX) +#define BITS_VPDIDX (BIT_MASK_VPDIDX << BIT_SHIFT_VPDIDX) +#define BIT_CLEAR_VPDIDX(x) ((x) & (~BITS_VPDIDX)) +#define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX) +#define BIT_SET_VPDIDX(x, v) (BIT_CLEAR_VPDIDX(x) | BIT_VPDIDX(v)) -#define BIT_SHIFT_SW18_C1 29 -#define BIT_MASK_SW18_C1 0x3 -#define BIT_SW18_C1(x) (((x) & BIT_MASK_SW18_C1) << BIT_SHIFT_SW18_C1) -#define BIT_GET_SW18_C1(x) (((x) >> BIT_SHIFT_SW18_C1) & BIT_MASK_SW18_C1) +#define BIT_SHIFT_EEM1_0 6 +#define BIT_MASK_EEM1_0 0x3 +#define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0) +#define BITS_EEM1_0 (BIT_MASK_EEM1_0 << BIT_SHIFT_EEM1_0) +#define BIT_CLEAR_EEM1_0(x) ((x) & (~BITS_EEM1_0)) +#define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0) +#define BIT_SET_EEM1_0(x, v) (BIT_CLEAR_EEM1_0(x) | BIT_EEM1_0(v)) +#define BIT_AUTOLOAD_SUS BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +#define BIT_EERPOMSEL BIT(4) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_C1_L 29 -#define BIT_MASK_C1_L 0x3 -#define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L) -#define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L) +/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +#define BIT_EEPROMSEL BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_EECS_V1 BIT(3) +#define BIT_EESK_V1 BIT(2) +#define BIT_EEDI_V1 BIT(1) +#define BIT_EEDO_V1 BIT(0) +#endif -#define BIT_SHIFT_C3_L1_V1 28 -#define BIT_MASK_C3_L1_V1 0x3 -#define BIT_C3_L1_V1(x) (((x) & BIT_MASK_C3_L1_V1) << BIT_SHIFT_C3_L1_V1) -#define BIT_GET_C3_L1_V1(x) (((x) >> BIT_SHIFT_C3_L1_V1) & BIT_MASK_C3_L1_V1) +#if (HALMAC_8822C_SUPPORT) +/* 2 REG_SDIO_MONITOR_2 (Offset 0x1025000C) */ -#define BIT_SHIFT_C2_L1_V1 26 -#define BIT_MASK_C2_L1_V1 0x3 -#define BIT_C2_L1_V1(x) (((x) & BIT_MASK_C2_L1_V1) << BIT_SHIFT_C2_L1_V1) -#define BIT_GET_C2_L1_V1(x) (((x) >> BIT_SHIFT_C2_L1_V1) & BIT_MASK_C2_L1_V1) +#define BIT_CMD53_WT_EN BIT(23) +#define BIT_SHIFT_SDIO_CLK_MONITOR 21 +#define BIT_MASK_SDIO_CLK_MONITOR 0x3 +#define BIT_SDIO_CLK_MONITOR(x) \ + (((x) & BIT_MASK_SDIO_CLK_MONITOR) << BIT_SHIFT_SDIO_CLK_MONITOR) +#define BITS_SDIO_CLK_MONITOR \ + (BIT_MASK_SDIO_CLK_MONITOR << BIT_SHIFT_SDIO_CLK_MONITOR) +#define BIT_CLEAR_SDIO_CLK_MONITOR(x) ((x) & (~BITS_SDIO_CLK_MONITOR)) +#define BIT_GET_SDIO_CLK_MONITOR(x) \ + (((x) >> BIT_SHIFT_SDIO_CLK_MONITOR) & BIT_MASK_SDIO_CLK_MONITOR) +#define BIT_SET_SDIO_CLK_MONITOR(x, v) \ + (BIT_CLEAR_SDIO_CLK_MONITOR(x) | BIT_SDIO_CLK_MONITOR(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_EE_VPD (Offset 0x000C) */ +#define BIT_SHIFT_VPD_DATA 0 +#define BIT_MASK_VPD_DATA 0xffffffffL +#define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA) +#define BITS_VPD_DATA (BIT_MASK_VPD_DATA << BIT_SHIFT_VPD_DATA) +#define BIT_CLEAR_VPD_DATA(x) ((x) & (~BITS_VPD_DATA)) +#define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA) +#define BIT_SET_VPD_DATA(x, v) (BIT_CLEAR_VPD_DATA(x) | BIT_VPD_DATA(v)) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_REG_FREQ_L 25 -#define BIT_MASK_REG_FREQ_L 0x7 -#define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L) -#define BIT_GET_REG_FREQ_L(x) (((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L) +/* 2 REG_EE_VPD (Offset 0x000C) */ -#define BIT_REG_EN_DUTY BIT(24) +#define BIT_SHIFT_VDP_DATA 0 +#define BIT_MASK_VDP_DATA 0xffffffffL +#define BIT_VDP_DATA(x) (((x) & BIT_MASK_VDP_DATA) << BIT_SHIFT_VDP_DATA) +#define BITS_VDP_DATA (BIT_MASK_VDP_DATA << BIT_SHIFT_VDP_DATA) +#define BIT_CLEAR_VDP_DATA(x) ((x) & (~BITS_VDP_DATA)) +#define BIT_GET_VDP_DATA(x) (((x) >> BIT_SHIFT_VDP_DATA) & BIT_MASK_VDP_DATA) +#define BIT_SET_VDP_DATA(x, v) (BIT_CLEAR_VDP_DATA(x) | BIT_VDP_DATA(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDIO_MONITOR_2 (Offset 0x1025000C) */ +#define BIT_SHIFT_SDIO_CLK_CNT 0 +#define BIT_MASK_SDIO_CLK_CNT 0x1fffff +#define BIT_SDIO_CLK_CNT(x) \ + (((x) & BIT_MASK_SDIO_CLK_CNT) << BIT_SHIFT_SDIO_CLK_CNT) +#define BITS_SDIO_CLK_CNT (BIT_MASK_SDIO_CLK_CNT << BIT_SHIFT_SDIO_CLK_CNT) +#define BIT_CLEAR_SDIO_CLK_CNT(x) ((x) & (~BITS_SDIO_CLK_CNT)) +#define BIT_GET_SDIO_CLK_CNT(x) \ + (((x) >> BIT_SHIFT_SDIO_CLK_CNT) & BIT_MASK_SDIO_CLK_CNT) +#define BIT_SET_SDIO_CLK_CNT(x, v) \ + (BIT_CLEAR_SDIO_CLK_CNT(x) | BIT_SDIO_CLK_CNT(v)) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_C1_L1_V1 24 -#define BIT_MASK_C1_L1_V1 0x3 -#define BIT_C1_L1_V1(x) (((x) & BIT_MASK_C1_L1_V1) << BIT_SHIFT_C1_L1_V1) -#define BIT_GET_C1_L1_V1(x) (((x) >> BIT_SHIFT_C1_L1_V1) & BIT_MASK_C1_L1_V1) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_REG_TYPE_L_V3 BIT(23) +#define BIT_SW18_C2_BIT0 BIT(31) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ - -#define BIT_SHIFT_REG_MODE 22 -#define BIT_MASK_REG_MODE 0x3 -#define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE) -#define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE) - +#define BIT_C2_L_BIT0 BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_FPWM_L1_V1 BIT(22) +#define BIT_SHIFT_R1_L1_V1 30 +#define BIT_MASK_R1_L1_V1 0x3 +#define BIT_R1_L1_V1(x) (((x) & BIT_MASK_R1_L1_V1) << BIT_SHIFT_R1_L1_V1) +#define BITS_R1_L1_V1 (BIT_MASK_R1_L1_V1 << BIT_SHIFT_R1_L1_V1) +#define BIT_CLEAR_R1_L1_V1(x) ((x) & (~BITS_R1_L1_V1)) +#define BIT_GET_R1_L1_V1(x) (((x) >> BIT_SHIFT_R1_L1_V1) & BIT_MASK_R1_L1_V1) +#define BIT_SET_R1_L1_V1(x, v) (BIT_CLEAR_R1_L1_V1(x) | BIT_R1_L1_V1(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_REG_EN_SP BIT(21) -#define BIT_REG_AUTO_L BIT(20) +#define BIT_SHIFT_SW18_C1 29 +#define BIT_MASK_SW18_C1 0x3 +#define BIT_SW18_C1(x) (((x) & BIT_MASK_SW18_C1) << BIT_SHIFT_SW18_C1) +#define BITS_SW18_C1 (BIT_MASK_SW18_C1 << BIT_SHIFT_SW18_C1) +#define BIT_CLEAR_SW18_C1(x) ((x) & (~BITS_SW18_C1)) +#define BIT_GET_SW18_C1(x) (((x) >> BIT_SHIFT_SW18_C1) & BIT_MASK_SW18_C1) +#define BIT_SET_SW18_C1(x, v) (BIT_CLEAR_SW18_C1(x) | BIT_SW18_C1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_SW18_SELD_BIT0 BIT(19) +#define BIT_SHIFT_C1_L 29 +#define BIT_MASK_C1_L 0x3 +#define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L) +#define BITS_C1_L (BIT_MASK_C1_L << BIT_SHIFT_C1_L) +#define BIT_CLEAR_C1_L(x) ((x) & (~BITS_C1_L)) +#define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L) +#define BIT_SET_C1_L(x, v) (BIT_CLEAR_C1_L(x) | BIT_C1_L(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_C3_L1_V1 28 +#define BIT_MASK_C3_L1_V1 0x3 +#define BIT_C3_L1_V1(x) (((x) & BIT_MASK_C3_L1_V1) << BIT_SHIFT_C3_L1_V1) +#define BITS_C3_L1_V1 (BIT_MASK_C3_L1_V1 << BIT_SHIFT_C3_L1_V1) +#define BIT_CLEAR_C3_L1_V1(x) ((x) & (~BITS_C3_L1_V1)) +#define BIT_GET_C3_L1_V1(x) (((x) >> BIT_SHIFT_C3_L1_V1) & BIT_MASK_C3_L1_V1) +#define BIT_SET_C3_L1_V1(x, v) (BIT_CLEAR_C3_L1_V1(x) | BIT_C3_L1_V1(v)) -#define BIT_SHIFT_V15ADJ_L1 19 -#define BIT_MASK_V15ADJ_L1 0x7 -#define BIT_V15ADJ_L1(x) (((x) & BIT_MASK_V15ADJ_L1) << BIT_SHIFT_V15ADJ_L1) -#define BIT_GET_V15ADJ_L1(x) (((x) >> BIT_SHIFT_V15ADJ_L1) & BIT_MASK_V15ADJ_L1) - +#define BIT_SHIFT_C2_L1_V1 26 +#define BIT_MASK_C2_L1_V1 0x3 +#define BIT_C2_L1_V1(x) (((x) & BIT_MASK_C2_L1_V1) << BIT_SHIFT_C2_L1_V1) +#define BITS_C2_L1_V1 (BIT_MASK_C2_L1_V1 << BIT_SHIFT_C2_L1_V1) +#define BIT_CLEAR_C2_L1_V1(x) ((x) & (~BITS_C2_L1_V1)) +#define BIT_GET_C2_L1_V1(x) (((x) >> BIT_SHIFT_C2_L1_V1) & BIT_MASK_C2_L1_V1) +#define BIT_SET_C2_L1_V1(x, v) (BIT_CLEAR_C2_L1_V1(x) | BIT_C2_L1_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_SW18_POWOCP BIT(18) +#define BIT_SHIFT_REG_FREQ_L 25 +#define BIT_MASK_REG_FREQ_L 0x7 +#define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L) +#define BITS_REG_FREQ_L (BIT_MASK_REG_FREQ_L << BIT_SHIFT_REG_FREQ_L) +#define BIT_CLEAR_REG_FREQ_L(x) ((x) & (~BITS_REG_FREQ_L)) +#define BIT_GET_REG_FREQ_L(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L) +#define BIT_SET_REG_FREQ_L(x, v) (BIT_CLEAR_REG_FREQ_L(x) | BIT_REG_FREQ_L(v)) -#endif +#define BIT_REG_EN_DUTY BIT(24) +#endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_C1_L1_V1 24 +#define BIT_MASK_C1_L1_V1 0x3 +#define BIT_C1_L1_V1(x) (((x) & BIT_MASK_C1_L1_V1) << BIT_SHIFT_C1_L1_V1) +#define BITS_C1_L1_V1 (BIT_MASK_C1_L1_V1 << BIT_SHIFT_C1_L1_V1) +#define BIT_CLEAR_C1_L1_V1(x) ((x) & (~BITS_C1_L1_V1)) +#define BIT_GET_C1_L1_V1(x) (((x) >> BIT_SHIFT_C1_L1_V1) & BIT_MASK_C1_L1_V1) +#define BIT_SET_C1_L1_V1(x, v) (BIT_CLEAR_C1_L1_V1(x) | BIT_C1_L1_V1(v)) -#define BIT_SHIFT_IN_L1 16 -#define BIT_MASK_IN_L1 0x7 -#define BIT_IN_L1(x) (((x) & BIT_MASK_IN_L1) << BIT_SHIFT_IN_L1) -#define BIT_GET_IN_L1(x) (((x) >> BIT_SHIFT_IN_L1) & BIT_MASK_IN_L1) - +#define BIT_REG_TYPE_L_V3 BIT(23) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_REG_MODE 22 +#define BIT_MASK_REG_MODE 0x3 +#define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE) +#define BITS_REG_MODE (BIT_MASK_REG_MODE << BIT_SHIFT_REG_MODE) +#define BIT_CLEAR_REG_MODE(x) ((x) & (~BITS_REG_MODE)) +#define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE) +#define BIT_SET_REG_MODE(x, v) (BIT_CLEAR_REG_MODE(x) | BIT_REG_MODE(v)) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_SW18_OCP 15 -#define BIT_MASK_SW18_OCP 0x7 -#define BIT_SW18_OCP(x) (((x) & BIT_MASK_SW18_OCP) << BIT_SHIFT_SW18_OCP) -#define BIT_GET_SW18_OCP(x) (((x) >> BIT_SHIFT_SW18_OCP) & BIT_MASK_SW18_OCP) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_FPWM_L1_V1 BIT(22) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_REG_EN_SP BIT(21) +#define BIT_REG_AUTO_L BIT(20) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_OCP_L1 15 -#define BIT_MASK_OCP_L1 0x7 -#define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1) -#define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SW18_SELD_BIT0 BIT(19) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_V15ADJ_L1 19 +#define BIT_MASK_V15ADJ_L1 0x7 +#define BIT_V15ADJ_L1(x) (((x) & BIT_MASK_V15ADJ_L1) << BIT_SHIFT_V15ADJ_L1) +#define BITS_V15ADJ_L1 (BIT_MASK_V15ADJ_L1 << BIT_SHIFT_V15ADJ_L1) +#define BIT_CLEAR_V15ADJ_L1(x) ((x) & (~BITS_V15ADJ_L1)) +#define BIT_GET_V15ADJ_L1(x) (((x) >> BIT_SHIFT_V15ADJ_L1) & BIT_MASK_V15ADJ_L1) +#define BIT_SET_V15ADJ_L1(x, v) (BIT_CLEAR_V15ADJ_L1(x) | BIT_V15ADJ_L1(v)) -#define BIT_SHIFT_STD_L1 14 -#define BIT_MASK_STD_L1 0x3 -#define BIT_STD_L1(x) (((x) & BIT_MASK_STD_L1) << BIT_SHIFT_STD_L1) -#define BIT_GET_STD_L1(x) (((x) >> BIT_SHIFT_STD_L1) & BIT_MASK_STD_L1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SW18_POWOCP BIT(18) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_IN_L1 16 +#define BIT_MASK_IN_L1 0x7 +#define BIT_IN_L1(x) (((x) & BIT_MASK_IN_L1) << BIT_SHIFT_IN_L1) +#define BITS_IN_L1 (BIT_MASK_IN_L1 << BIT_SHIFT_IN_L1) +#define BIT_CLEAR_IN_L1(x) ((x) & (~BITS_IN_L1)) +#define BIT_GET_IN_L1(x) (((x) >> BIT_SHIFT_IN_L1) & BIT_MASK_IN_L1) +#define BIT_SET_IN_L1(x, v) (BIT_CLEAR_IN_L1(x) | BIT_IN_L1(v)) -#define BIT_SHIFT_CF_L_BIT0_TO_1 13 -#define BIT_MASK_CF_L_BIT0_TO_1 0x3 -#define BIT_CF_L_BIT0_TO_1(x) (((x) & BIT_MASK_CF_L_BIT0_TO_1) << BIT_SHIFT_CF_L_BIT0_TO_1) -#define BIT_GET_CF_L_BIT0_TO_1(x) (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1) & BIT_MASK_CF_L_BIT0_TO_1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_SW18_OCP 15 +#define BIT_MASK_SW18_OCP 0x7 +#define BIT_SW18_OCP(x) (((x) & BIT_MASK_SW18_OCP) << BIT_SHIFT_SW18_OCP) +#define BITS_SW18_OCP (BIT_MASK_SW18_OCP << BIT_SHIFT_SW18_OCP) +#define BIT_CLEAR_SW18_OCP(x) ((x) & (~BITS_SW18_OCP)) +#define BIT_GET_SW18_OCP(x) (((x) >> BIT_SHIFT_SW18_OCP) & BIT_MASK_SW18_OCP) +#define BIT_SET_SW18_OCP(x, v) (BIT_CLEAR_SW18_OCP(x) | BIT_SW18_OCP(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_OCP_L1 15 +#define BIT_MASK_OCP_L1 0x7 +#define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1) +#define BITS_OCP_L1 (BIT_MASK_OCP_L1 << BIT_SHIFT_OCP_L1) +#define BIT_CLEAR_OCP_L1(x) ((x) & (~BITS_OCP_L1)) +#define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1) +#define BIT_SET_OCP_L1(x, v) (BIT_CLEAR_OCP_L1(x) | BIT_OCP_L1(v)) -#define BIT_SHIFT_CF_L 13 -#define BIT_MASK_CF_L 0x3 -#define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L) -#define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_STD_L1 14 +#define BIT_MASK_STD_L1 0x3 +#define BIT_STD_L1(x) (((x) & BIT_MASK_STD_L1) << BIT_SHIFT_STD_L1) +#define BITS_STD_L1 (BIT_MASK_STD_L1 << BIT_SHIFT_STD_L1) +#define BIT_CLEAR_STD_L1(x) ((x) & (~BITS_STD_L1)) +#define BIT_GET_STD_L1(x) (((x) >> BIT_SHIFT_STD_L1) & BIT_MASK_STD_L1) +#define BIT_SET_STD_L1(x, v) (BIT_CLEAR_STD_L1(x) | BIT_STD_L1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_SW18_FPWM BIT(11) +#define BIT_SHIFT_CF_L_BIT0_TO_1 13 +#define BIT_MASK_CF_L_BIT0_TO_1 0x3 +#define BIT_CF_L_BIT0_TO_1(x) \ + (((x) & BIT_MASK_CF_L_BIT0_TO_1) << BIT_SHIFT_CF_L_BIT0_TO_1) +#define BITS_CF_L_BIT0_TO_1 \ + (BIT_MASK_CF_L_BIT0_TO_1 << BIT_SHIFT_CF_L_BIT0_TO_1) +#define BIT_CLEAR_CF_L_BIT0_TO_1(x) ((x) & (~BITS_CF_L_BIT0_TO_1)) +#define BIT_GET_CF_L_BIT0_TO_1(x) \ + (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1) & BIT_MASK_CF_L_BIT0_TO_1) +#define BIT_SET_CF_L_BIT0_TO_1(x, v) \ + (BIT_CLEAR_CF_L_BIT0_TO_1(x) | BIT_CF_L_BIT0_TO_1(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_CF_L 13 +#define BIT_MASK_CF_L 0x3 +#define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L) +#define BITS_CF_L (BIT_MASK_CF_L << BIT_SHIFT_CF_L) +#define BIT_CLEAR_CF_L(x) ((x) & (~BITS_CF_L)) +#define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L) +#define BIT_SET_CF_L(x, v) (BIT_CLEAR_CF_L(x) | BIT_CF_L(v)) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VOL_L1 10 -#define BIT_MASK_VOL_L1 0xf -#define BIT_VOL_L1(x) (((x) & BIT_MASK_VOL_L1) << BIT_SHIFT_VOL_L1) -#define BIT_GET_VOL_L1(x) (((x) >> BIT_SHIFT_VOL_L1) & BIT_MASK_VOL_L1) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SW18_FPWM BIT(11) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ + +#define BIT_SHIFT_VOL_L1 10 +#define BIT_MASK_VOL_L1 0xf +#define BIT_VOL_L1(x) (((x) & BIT_MASK_VOL_L1) << BIT_SHIFT_VOL_L1) +#define BITS_VOL_L1 (BIT_MASK_VOL_L1 << BIT_SHIFT_VOL_L1) +#define BIT_CLEAR_VOL_L1(x) ((x) & (~BITS_VOL_L1)) +#define BIT_GET_VOL_L1(x) (((x) >> BIT_SHIFT_VOL_L1) & BIT_MASK_VOL_L1) +#define BIT_SET_VOL_L1(x, v) (BIT_CLEAR_VOL_L1(x) | BIT_VOL_L1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_SW18_SWEN BIT(9) -#define BIT_SW18_LDEN BIT(8) -#define BIT_MAC_ID_EN BIT(7) +#define BIT_SW18_SWEN BIT(9) +#define BIT_SW18_LDEN BIT(8) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_MAC_ID_EN BIT(7) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_WL_CTRL_XTAL_CADJ BIT(6) +#define BIT_WL_CTRL_XTAL_CADJ BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_LDO11_EN BIT(6) -#define BIT_AFE_P3_PC BIT(5) -#define BIT_AFE_P2_PC BIT(4) -#define BIT_AFE_P1_PC BIT(3) -#define BIT_AFE_P0_PC BIT(2) +#define BIT_LDO11_EN BIT(6) +#define BIT_AFE_P3_PC BIT(5) +#define BIT_AFE_P2_PC BIT(4) +#define BIT_AFE_P1_PC BIT(3) +#define BIT_AFE_P0_PC BIT(2) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_AFE_BGEN BIT(0) +#define BIT_AFE_BGEN BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_POW_ZCD_L BIT(31) +#define BIT_POW_ZCD_L BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_IO_READY_SIGNAL_ERR_MSK BIT(31) +#define BIT_IO_READY_SIGNAL_ERR_MSK BIT(31) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_CRCERR_MSK BIT(31) +#define BIT_SDIO_CRCERR_MSK BIT(31) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_ENABLE_ZCDOUT_L BIT(30) +#define BIT_ENABLE_ZCDOUT_L BIT(30) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_TX_CRC__MSK BIT(30) +#define BIT_SDIO_TX_CRC__MSK BIT(30) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SDIO_HSISR3_IND_MSK BIT(30) + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_AUTOZCD_L BIT(30) -#define BIT_SDIO_HSISR3_IND_MSK BIT(30) -#define BIT_SDIO_HSISR2_IND_MSK BIT(29) +#define BIT_AUTOZCD_L BIT(30) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SDIO_HSISR2_IND_MSK BIT(29) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_REG_DELAY 28 -#define BIT_MASK_REG_DELAY 0x3 -#define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY) -#define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY) +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_REG_DELAY 28 +#define BIT_MASK_REG_DELAY 0x3 +#define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY) +#define BITS_REG_DELAY (BIT_MASK_REG_DELAY << BIT_SHIFT_REG_DELAY) +#define BIT_CLEAR_REG_DELAY(x) ((x) & (~BITS_REG_DELAY)) +#define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY) +#define BIT_SET_REG_DELAY(x, v) (BIT_CLEAR_REG_DELAY(x) | BIT_REG_DELAY(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_HEISR_IND_MSK BIT(28) +#define BIT_SDIO_HEISR_IND_MSK BIT(28) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_CTWEND_MSK BIT(27) -#define BIT_SDIO_ATIMEND_E_MSK BIT(26) +#define BIT_SDIO_CTWEND_MSK BIT(27) +#define BIT_SDIO_ATIMEND_E_MSK BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_ATIMEND_MSK BIT(25) +#define BIT_SDIO_ATIMEND_MSK BIT(25) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIIO_ATIMEND_MSK BIT(25) +#define BIT_SDIIO_ATIMEND_MSK BIT(25) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_SW18_V15ADJ 24 -#define BIT_MASK_SW18_V15ADJ 0x7 -#define BIT_SW18_V15ADJ(x) (((x) & BIT_MASK_SW18_V15ADJ) << BIT_SHIFT_SW18_V15ADJ) -#define BIT_GET_SW18_V15ADJ(x) (((x) >> BIT_SHIFT_SW18_V15ADJ) & BIT_MASK_SW18_V15ADJ) - +#define BIT_SHIFT_SW18_V15ADJ 24 +#define BIT_MASK_SW18_V15ADJ 0x7 +#define BIT_SW18_V15ADJ(x) \ + (((x) & BIT_MASK_SW18_V15ADJ) << BIT_SHIFT_SW18_V15ADJ) +#define BITS_SW18_V15ADJ (BIT_MASK_SW18_V15ADJ << BIT_SHIFT_SW18_V15ADJ) +#define BIT_CLEAR_SW18_V15ADJ(x) ((x) & (~BITS_SW18_V15ADJ)) +#define BIT_GET_SW18_V15ADJ(x) \ + (((x) >> BIT_SHIFT_SW18_V15ADJ) & BIT_MASK_SW18_V15ADJ) +#define BIT_SET_SW18_V15ADJ(x, v) \ + (BIT_CLEAR_SW18_V15ADJ(x) | BIT_SW18_V15ADJ(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_OCPINT_MSK BIT(24) +#define BIT_SDIO_OCPINT_MSK BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_OCPSL BIT(24) +#define BIT_OCPSL BIT(24) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_V15ADJ_L1_V1 24 -#define BIT_MASK_V15ADJ_L1_V1 0x7 -#define BIT_V15ADJ_L1_V1(x) (((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1) -#define BIT_GET_V15ADJ_L1_V1(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1) - +#define BIT_SHIFT_V15ADJ_L1_V1 24 +#define BIT_MASK_V15ADJ_L1_V1 0x7 +#define BIT_V15ADJ_L1_V1(x) \ + (((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1) +#define BITS_V15ADJ_L1_V1 (BIT_MASK_V15ADJ_L1_V1 << BIT_SHIFT_V15ADJ_L1_V1) +#define BIT_CLEAR_V15ADJ_L1_V1(x) ((x) & (~BITS_V15ADJ_L1_V1)) +#define BIT_GET_V15ADJ_L1_V1(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1) +#define BIT_SET_V15ADJ_L1_V1(x, v) \ + (BIT_CLEAR_V15ADJ_L1_V1(x) | BIT_V15ADJ_L1_V1(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_PSTIMEOUT_MSK BIT(23) +#define BIT_SDIO_PSTIMEOUT_MSK BIT(23) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_REG_LDOF_L_V1 BIT(23) +#define BIT_REG_LDOF_L_V1 BIT(23) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_GTINT4_MSK BIT(22) +#define BIT_SDIO_GTINT4_MSK BIT(22) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_PARSW_DUMMY BIT(22) +#define BIT_PARSW_DUMMY BIT(22) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_GTINT3_MSK BIT(21) +#define BIT_SDIO_GTINT3_MSK BIT(21) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_CLAMP_MAX_DUTY BIT(21) +#define BIT_CLAMP_MAX_DUTY BIT(21) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_SW18_VOL 20 -#define BIT_MASK_SW18_VOL 0xf -#define BIT_SW18_VOL(x) (((x) & BIT_MASK_SW18_VOL) << BIT_SHIFT_SW18_VOL) -#define BIT_GET_SW18_VOL(x) (((x) >> BIT_SHIFT_SW18_VOL) & BIT_MASK_SW18_VOL) - +#define BIT_SHIFT_SW18_VOL 20 +#define BIT_MASK_SW18_VOL 0xf +#define BIT_SW18_VOL(x) (((x) & BIT_MASK_SW18_VOL) << BIT_SHIFT_SW18_VOL) +#define BITS_SW18_VOL (BIT_MASK_SW18_VOL << BIT_SHIFT_SW18_VOL) +#define BIT_CLEAR_SW18_VOL(x) ((x) & (~BITS_SW18_VOL)) +#define BIT_GET_SW18_VOL(x) (((x) >> BIT_SHIFT_SW18_VOL) & BIT_MASK_SW18_VOL) +#define BIT_SET_SW18_VOL(x, v) (BIT_CLEAR_SW18_VOL(x) | BIT_SW18_VOL(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_HSISR_IND_MSK BIT(20) +#define BIT_SDIO_HSISR_IND_MSK BIT(20) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_VOL_L1_V1 20 -#define BIT_MASK_VOL_L1_V1 0xf -#define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1) -#define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1) - +#define BIT_SHIFT_VOL_L1_V1 20 +#define BIT_MASK_VOL_L1_V1 0xf +#define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1) +#define BITS_VOL_L1_V1 (BIT_MASK_VOL_L1_V1 << BIT_SHIFT_VOL_L1_V1) +#define BIT_CLEAR_VOL_L1_V1(x) ((x) & (~BITS_VOL_L1_V1)) +#define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1) +#define BIT_SET_VOL_L1_V1(x, v) (BIT_CLEAR_VOL_L1_V1(x) | BIT_VOL_L1_V1(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_CPWM2_MSK BIT(19) +#define BIT_SDIO_CPWM2_MSK BIT(19) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_TBOX_L1_V1 19 -#define BIT_MASK_TBOX_L1_V1 0x3 -#define BIT_TBOX_L1_V1(x) (((x) & BIT_MASK_TBOX_L1_V1) << BIT_SHIFT_TBOX_L1_V1) -#define BIT_GET_TBOX_L1_V1(x) (((x) >> BIT_SHIFT_TBOX_L1_V1) & BIT_MASK_TBOX_L1_V1) - +#define BIT_SHIFT_TBOX_L1_V1 19 +#define BIT_MASK_TBOX_L1_V1 0x3 +#define BIT_TBOX_L1_V1(x) (((x) & BIT_MASK_TBOX_L1_V1) << BIT_SHIFT_TBOX_L1_V1) +#define BITS_TBOX_L1_V1 (BIT_MASK_TBOX_L1_V1 << BIT_SHIFT_TBOX_L1_V1) +#define BIT_CLEAR_TBOX_L1_V1(x) ((x) & (~BITS_TBOX_L1_V1)) +#define BIT_GET_TBOX_L1_V1(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_V1) & BIT_MASK_TBOX_L1_V1) +#define BIT_SET_TBOX_L1_V1(x, v) (BIT_CLEAR_TBOX_L1_V1(x) | BIT_TBOX_L1_V1(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_CPWM1_MSK BIT(18) +#define BIT_SDIO_CPWM1_MSK BIT(18) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_SW18_IN 17 -#define BIT_MASK_SW18_IN 0x7 -#define BIT_SW18_IN(x) (((x) & BIT_MASK_SW18_IN) << BIT_SHIFT_SW18_IN) -#define BIT_GET_SW18_IN(x) (((x) >> BIT_SHIFT_SW18_IN) & BIT_MASK_SW18_IN) - +#define BIT_SHIFT_SW18_IN 17 +#define BIT_MASK_SW18_IN 0x7 +#define BIT_SW18_IN(x) (((x) & BIT_MASK_SW18_IN) << BIT_SHIFT_SW18_IN) +#define BITS_SW18_IN (BIT_MASK_SW18_IN << BIT_SHIFT_SW18_IN) +#define BIT_CLEAR_SW18_IN(x) ((x) & (~BITS_SW18_IN)) +#define BIT_GET_SW18_IN(x) (((x) >> BIT_SHIFT_SW18_IN) & BIT_MASK_SW18_IN) +#define BIT_SET_SW18_IN(x, v) (BIT_CLEAR_SW18_IN(x) | BIT_SW18_IN(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_C2HCMD_INT_MSK BIT(17) +#define BIT_SDIO_C2HCMD_INT_MSK BIT(17) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_REG_DELAY_V3 17 -#define BIT_MASK_REG_DELAY_V3 0x3 -#define BIT_REG_DELAY_V3(x) (((x) & BIT_MASK_REG_DELAY_V3) << BIT_SHIFT_REG_DELAY_V3) -#define BIT_GET_REG_DELAY_V3(x) (((x) >> BIT_SHIFT_REG_DELAY_V3) & BIT_MASK_REG_DELAY_V3) - +#define BIT_SHIFT_REG_DELAY_V3 17 +#define BIT_MASK_REG_DELAY_V3 0x3 +#define BIT_REG_DELAY_V3(x) \ + (((x) & BIT_MASK_REG_DELAY_V3) << BIT_SHIFT_REG_DELAY_V3) +#define BITS_REG_DELAY_V3 (BIT_MASK_REG_DELAY_V3 << BIT_SHIFT_REG_DELAY_V3) +#define BIT_CLEAR_REG_DELAY_V3(x) ((x) & (~BITS_REG_DELAY_V3)) +#define BIT_GET_REG_DELAY_V3(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_V3) & BIT_MASK_REG_DELAY_V3) +#define BIT_SET_REG_DELAY_V3(x, v) \ + (BIT_CLEAR_REG_DELAY_V3(x) | BIT_REG_DELAY_V3(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_IN_L1_V1 17 -#define BIT_MASK_IN_L1_V1 0x7 -#define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1) -#define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1) - +#define BIT_SHIFT_IN_L1_V1 17 +#define BIT_MASK_IN_L1_V1 0x7 +#define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1) +#define BITS_IN_L1_V1 (BIT_MASK_IN_L1_V1 << BIT_SHIFT_IN_L1_V1) +#define BIT_CLEAR_IN_L1_V1(x) ((x) & (~BITS_IN_L1_V1)) +#define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1) +#define BIT_SET_IN_L1_V1(x, v) (BIT_CLEAR_IN_L1_V1(x) | BIT_IN_L1_V1(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_BCNERLY_INT_MSK BIT(16) +#define BIT_SDIO_BCNERLY_INT_MSK BIT(16) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_REG_CLAMP_D_L_V2 BIT(16) +#define BIT_REG_CLAMP_D_L_V2 BIT(16) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_SW18_TBOX 15 -#define BIT_MASK_SW18_TBOX 0x3 -#define BIT_SW18_TBOX(x) (((x) & BIT_MASK_SW18_TBOX) << BIT_SHIFT_SW18_TBOX) -#define BIT_GET_SW18_TBOX(x) (((x) >> BIT_SHIFT_SW18_TBOX) & BIT_MASK_SW18_TBOX) - +#define BIT_SHIFT_SW18_TBOX 15 +#define BIT_MASK_SW18_TBOX 0x3 +#define BIT_SW18_TBOX(x) (((x) & BIT_MASK_SW18_TBOX) << BIT_SHIFT_SW18_TBOX) +#define BITS_SW18_TBOX (BIT_MASK_SW18_TBOX << BIT_SHIFT_SW18_TBOX) +#define BIT_CLEAR_SW18_TBOX(x) ((x) & (~BITS_SW18_TBOX)) +#define BIT_GET_SW18_TBOX(x) (((x) >> BIT_SHIFT_SW18_TBOX) & BIT_MASK_SW18_TBOX) +#define BIT_SET_SW18_TBOX(x, v) (BIT_CLEAR_SW18_TBOX(x) | BIT_SW18_TBOX(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_REG_BYPASS_L_V3 BIT(15) +#define BIT_REG_BYPASS_L_V3 BIT(15) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_TBOX_L1 15 -#define BIT_MASK_TBOX_L1 0x3 -#define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1) -#define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1) - +#define BIT_SHIFT_TBOX_L1 15 +#define BIT_MASK_TBOX_L1 0x3 +#define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1) +#define BITS_TBOX_L1 (BIT_MASK_TBOX_L1 << BIT_SHIFT_TBOX_L1) +#define BIT_CLEAR_TBOX_L1(x) ((x) & (~BITS_TBOX_L1)) +#define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1) +#define BIT_SET_TBOX_L1(x, v) (BIT_CLEAR_TBOX_L1(x) | BIT_TBOX_L1(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_ENABLE_ZCDOUT_L_V3 BIT(14) +#define BIT_ENABLE_ZCDOUT_L_V3 BIT(14) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_SW18_SEL BIT(13) +#define BIT_SW18_SEL BIT(13) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_POW_ZCD_L_V3 BIT(13) -#define BIT_AREN_L1_V1 BIT(12) +#define BIT_POW_ZCD_L_V3 BIT(13) +#define BIT_AREN_L1_V1 BIT(12) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_SW18_STD 11 +#define BIT_MASK_SW18_STD 0x3 +#define BIT_SW18_STD(x) (((x) & BIT_MASK_SW18_STD) << BIT_SHIFT_SW18_STD) +#define BITS_SW18_STD (BIT_MASK_SW18_STD << BIT_SHIFT_SW18_STD) +#define BIT_CLEAR_SW18_STD(x) ((x) & (~BITS_SW18_STD)) +#define BIT_GET_SW18_STD(x) (((x) >> BIT_SHIFT_SW18_STD) & BIT_MASK_SW18_STD) +#define BIT_SET_SW18_STD(x, v) (BIT_CLEAR_SW18_STD(x) | BIT_SW18_STD(v)) -#define BIT_SHIFT_SW18_STD 11 -#define BIT_MASK_SW18_STD 0x3 -#define BIT_SW18_STD(x) (((x) & BIT_MASK_SW18_STD) << BIT_SHIFT_SW18_STD) -#define BIT_GET_SW18_STD(x) (((x) >> BIT_SHIFT_SW18_STD) & BIT_MASK_SW18_STD) - - -#endif - - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_SW18_SD BIT(10) +#define BIT_SW18_SD BIT(10) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_SW18_AREN BIT(9) +#define BIT_SW18_AREN BIT(9) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_OCP_V3 9 +#define BIT_MASK_OCP_V3 0x7 +#define BIT_OCP_V3(x) (((x) & BIT_MASK_OCP_V3) << BIT_SHIFT_OCP_V3) +#define BITS_OCP_V3 (BIT_MASK_OCP_V3 << BIT_SHIFT_OCP_V3) +#define BIT_CLEAR_OCP_V3(x) ((x) & (~BITS_OCP_V3)) +#define BIT_GET_OCP_V3(x) (((x) >> BIT_SHIFT_OCP_V3) & BIT_MASK_OCP_V3) +#define BIT_SET_OCP_V3(x, v) (BIT_CLEAR_OCP_V3(x) | BIT_OCP_V3(v)) -#define BIT_SHIFT_OCP_V3 9 -#define BIT_MASK_OCP_V3 0x7 -#define BIT_OCP_V3(x) (((x) & BIT_MASK_OCP_V3) << BIT_SHIFT_OCP_V3) -#define BIT_GET_OCP_V3(x) (((x) >> BIT_SHIFT_OCP_V3) & BIT_MASK_OCP_V3) - -#define BIT_POWOCP_V3 BIT(8) +#define BIT_POWOCP_V3 BIT(8) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_SW18_R3 7 -#define BIT_MASK_SW18_R3 0x3 -#define BIT_SW18_R3(x) (((x) & BIT_MASK_SW18_R3) << BIT_SHIFT_SW18_R3) -#define BIT_GET_SW18_R3(x) (((x) >> BIT_SHIFT_SW18_R3) & BIT_MASK_SW18_R3) - +#define BIT_SHIFT_SW18_R3 7 +#define BIT_MASK_SW18_R3 0x3 +#define BIT_SW18_R3(x) (((x) & BIT_MASK_SW18_R3) << BIT_SHIFT_SW18_R3) +#define BITS_SW18_R3 (BIT_MASK_SW18_R3 << BIT_SHIFT_SW18_R3) +#define BIT_CLEAR_SW18_R3(x) ((x) & (~BITS_SW18_R3)) +#define BIT_GET_SW18_R3(x) (((x) >> BIT_SHIFT_SW18_R3) & BIT_MASK_SW18_R3) +#define BIT_SET_SW18_R3(x, v) (BIT_CLEAR_SW18_R3(x) | BIT_SW18_R3(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_TXBCNERR_MSK BIT(7) +#define BIT_SDIO_TXBCNERR_MSK BIT(7) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_R3_L 7 -#define BIT_MASK_R3_L 0x3 -#define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L) -#define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L) - +#define BIT_SHIFT_R3_L 7 +#define BIT_MASK_R3_L 0x3 +#define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L) +#define BITS_R3_L (BIT_MASK_R3_L << BIT_SHIFT_R3_L) +#define BIT_CLEAR_R3_L(x) ((x) & (~BITS_R3_L)) +#define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L) +#define BIT_SET_R3_L(x, v) (BIT_CLEAR_R3_L(x) | BIT_R3_L(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_TXBCNOK_MSK BIT(6) +#define BIT_SDIO_TXBCNOK_MSK BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_CF_L_V3 6 -#define BIT_MASK_CF_L_V3 0x3 -#define BIT_CF_L_V3(x) (((x) & BIT_MASK_CF_L_V3) << BIT_SHIFT_CF_L_V3) -#define BIT_GET_CF_L_V3(x) (((x) >> BIT_SHIFT_CF_L_V3) & BIT_MASK_CF_L_V3) - +#define BIT_SHIFT_CF_L_V3 6 +#define BIT_MASK_CF_L_V3 0x3 +#define BIT_CF_L_V3(x) (((x) & BIT_MASK_CF_L_V3) << BIT_SHIFT_CF_L_V3) +#define BITS_CF_L_V3 (BIT_MASK_CF_L_V3 << BIT_SHIFT_CF_L_V3) +#define BIT_CLEAR_CF_L_V3(x) ((x) & (~BITS_CF_L_V3)) +#define BIT_GET_CF_L_V3(x) (((x) >> BIT_SHIFT_CF_L_V3) & BIT_MASK_CF_L_V3) +#define BIT_SET_CF_L_V3(x, v) (BIT_CLEAR_CF_L_V3(x) | BIT_CF_L_V3(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_SW18_R2 5 -#define BIT_MASK_SW18_R2 0x3 -#define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2) -#define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2) - +#define BIT_SHIFT_SW18_R2 5 +#define BIT_MASK_SW18_R2 0x3 +#define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2) +#define BITS_SW18_R2 (BIT_MASK_SW18_R2 << BIT_SHIFT_SW18_R2) +#define BIT_CLEAR_SW18_R2(x) ((x) & (~BITS_SW18_R2)) +#define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2) +#define BIT_SET_SW18_R2(x, v) (BIT_CLEAR_SW18_R2(x) | BIT_SW18_R2(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_RXFOVW_MSK BIT(5) -#define BIT_SDIO_TXFOVW_MSK BIT(4) +#define BIT_SDIO_RXFOVW_MSK BIT(5) +#define BIT_SDIO_TXFOVW_MSK BIT(4) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_CFC_L_BIT0_TO_1_V1 4 -#define BIT_MASK_CFC_L_BIT0_TO_1_V1 0x3 -#define BIT_CFC_L_BIT0_TO_1_V1(x) (((x) & BIT_MASK_CFC_L_BIT0_TO_1_V1) << BIT_SHIFT_CFC_L_BIT0_TO_1_V1) -#define BIT_GET_CFC_L_BIT0_TO_1_V1(x) (((x) >> BIT_SHIFT_CFC_L_BIT0_TO_1_V1) & BIT_MASK_CFC_L_BIT0_TO_1_V1) - +#define BIT_SHIFT_CFC_L_BIT0_TO_1_V1 4 +#define BIT_MASK_CFC_L_BIT0_TO_1_V1 0x3 +#define BIT_CFC_L_BIT0_TO_1_V1(x) \ + (((x) & BIT_MASK_CFC_L_BIT0_TO_1_V1) << BIT_SHIFT_CFC_L_BIT0_TO_1_V1) +#define BITS_CFC_L_BIT0_TO_1_V1 \ + (BIT_MASK_CFC_L_BIT0_TO_1_V1 << BIT_SHIFT_CFC_L_BIT0_TO_1_V1) +#define BIT_CLEAR_CFC_L_BIT0_TO_1_V1(x) ((x) & (~BITS_CFC_L_BIT0_TO_1_V1)) +#define BIT_GET_CFC_L_BIT0_TO_1_V1(x) \ + (((x) >> BIT_SHIFT_CFC_L_BIT0_TO_1_V1) & BIT_MASK_CFC_L_BIT0_TO_1_V1) +#define BIT_SET_CFC_L_BIT0_TO_1_V1(x, v) \ + (BIT_CLEAR_CFC_L_BIT0_TO_1_V1(x) | BIT_CFC_L_BIT0_TO_1_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_SW18_R1 3 -#define BIT_MASK_SW18_R1 0x3 -#define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1) -#define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1) - +#define BIT_SHIFT_SW18_R1 3 +#define BIT_MASK_SW18_R1 0x3 +#define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1) +#define BITS_SW18_R1 (BIT_MASK_SW18_R1 << BIT_SHIFT_SW18_R1) +#define BIT_CLEAR_SW18_R1(x) ((x) & (~BITS_SW18_R1)) +#define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1) +#define BIT_SET_SW18_R1(x, v) (BIT_CLEAR_SW18_R1(x) | BIT_SW18_R1(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_RXERR_MSK BIT(3) -#define BIT_SDIO_TXERR_MSK BIT(2) +#define BIT_SDIO_RXERR_MSK BIT(3) +#define BIT_SDIO_TXERR_MSK BIT(2) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_R3_L1_V1 2 -#define BIT_MASK_R3_L1_V1 0x3 -#define BIT_R3_L1_V1(x) (((x) & BIT_MASK_R3_L1_V1) << BIT_SHIFT_R3_L1_V1) -#define BIT_GET_R3_L1_V1(x) (((x) >> BIT_SHIFT_R3_L1_V1) & BIT_MASK_R3_L1_V1) - +#define BIT_SHIFT_R3_L1_V1 2 +#define BIT_MASK_R3_L1_V1 0x3 +#define BIT_R3_L1_V1(x) (((x) & BIT_MASK_R3_L1_V1) << BIT_SHIFT_R3_L1_V1) +#define BITS_R3_L1_V1 (BIT_MASK_R3_L1_V1 << BIT_SHIFT_R3_L1_V1) +#define BIT_CLEAR_R3_L1_V1(x) ((x) & (~BITS_R3_L1_V1)) +#define BIT_GET_R3_L1_V1(x) (((x) >> BIT_SHIFT_R3_L1_V1) & BIT_MASK_R3_L1_V1) +#define BIT_SET_R3_L1_V1(x, v) (BIT_CLEAR_R3_L1_V1(x) | BIT_R3_L1_V1(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_SW18_C3 1 -#define BIT_MASK_SW18_C3 0x3 -#define BIT_SW18_C3(x) (((x) & BIT_MASK_SW18_C3) << BIT_SHIFT_SW18_C3) -#define BIT_GET_SW18_C3(x) (((x) >> BIT_SHIFT_SW18_C3) & BIT_MASK_SW18_C3) - +#define BIT_SHIFT_SW18_C3 1 +#define BIT_MASK_SW18_C3 0x3 +#define BIT_SW18_C3(x) (((x) & BIT_MASK_SW18_C3) << BIT_SHIFT_SW18_C3) +#define BITS_SW18_C3 (BIT_MASK_SW18_C3 << BIT_SHIFT_SW18_C3) +#define BIT_CLEAR_SW18_C3(x) ((x) & (~BITS_SW18_C3)) +#define BIT_GET_SW18_C3(x) (((x) >> BIT_SHIFT_SW18_C3) & BIT_MASK_SW18_C3) +#define BIT_SET_SW18_C3(x, v) (BIT_CLEAR_SW18_C3(x) | BIT_SW18_C3(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_AVAL_MSK BIT(1) +#define BIT_SDIO_AVAL_MSK BIT(1) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_C3_L_C3 1 -#define BIT_MASK_C3_L_C3 0x3 -#define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3) -#define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3) - +#define BIT_SHIFT_C3_L_C3 1 +#define BIT_MASK_C3_L_C3 0x3 +#define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3) +#define BITS_C3_L_C3 (BIT_MASK_C3_L_C3 << BIT_SHIFT_C3_L_C3) +#define BIT_CLEAR_C3_L_C3(x) ((x) & (~BITS_C3_L_C3)) +#define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3) +#define BIT_SET_C3_L_C3(x, v) (BIT_CLEAR_C3_L_C3(x) | BIT_C3_L_C3(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_SW18_C2_BIT1 BIT(0) +#define BIT_SW18_C2_BIT1 BIT(0) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_RX_REQUEST_MSK BIT(0) +#define BIT_RX_REQUEST_MSK BIT(0) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_R2_L1_V1 0 -#define BIT_MASK_R2_L1_V1 0x3 -#define BIT_R2_L1_V1(x) (((x) & BIT_MASK_R2_L1_V1) << BIT_SHIFT_R2_L1_V1) -#define BIT_GET_R2_L1_V1(x) (((x) >> BIT_SHIFT_R2_L1_V1) & BIT_MASK_R2_L1_V1) - +#define BIT_SHIFT_R2_L1_V1 0 +#define BIT_MASK_R2_L1_V1 0x3 +#define BIT_R2_L1_V1(x) (((x) & BIT_MASK_R2_L1_V1) << BIT_SHIFT_R2_L1_V1) +#define BITS_R2_L1_V1 (BIT_MASK_R2_L1_V1 << BIT_SHIFT_R2_L1_V1) +#define BIT_CLEAR_R2_L1_V1(x) ((x) & (~BITS_R2_L1_V1)) +#define BIT_GET_R2_L1_V1(x) (((x) >> BIT_SHIFT_R2_L1_V1) & BIT_MASK_R2_L1_V1) +#define BIT_SET_R2_L1_V1(x, v) (BIT_CLEAR_R2_L1_V1(x) | BIT_R2_L1_V1(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_C2_L_BIT1 BIT(0) +#define BIT_C2_L_BIT1 BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ -#define BIT_SPS18_OCP_DIS BIT(31) +#define BIT_SPS18_OCP_DIS BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_IO_READY_SIGNAL_ERR BIT(31) +#define BIT_IO_READY_SIGNAL_ERR BIT(31) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_SDIO_CRCERR BIT(31) +#define BIT_SDIO_CRCERR BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_TX_CRC BIT(30) +#define BIT_TX_CRC BIT(30) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_SDIO_HSISR3_IND BIT(30) -#define BIT_SDIO_HSISR2_IND BIT(29) -#define BIT_SDIO_HEISR_IND BIT(28) +#define BIT_SDIO_HSISR3_IND BIT(30) +#define BIT_SDIO_HSISR2_IND BIT(29) +#define BIT_SDIO_HEISR_IND BIT(28) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_SDIO_CTWEND BIT(27) -#define BIT_SDIO_ATIMEND_E BIT(26) -#define BIT_SDIO_ATIMEND BIT(25) -#define BIT_SDIO_OCPINT BIT(24) -#define BIT_SDIO_PSTIMEOUT BIT(23) -#define BIT_SDIO_GTINT4 BIT(22) -#define BIT_SDIO_GTINT3 BIT(21) -#define BIT_SDIO_HSISR_IND BIT(20) -#define BIT_SDIO_CPWM2 BIT(19) -#define BIT_SDIO_CPWM1 BIT(18) -#define BIT_SDIO_C2HCMD_INT BIT(17) +#define BIT_SDIO_CTWEND BIT(27) +#define BIT_SDIO_ATIMEND_E BIT(26) +#define BIT_SDIO_ATIMEND BIT(25) +#define BIT_SDIO_OCPINT BIT(24) +#define BIT_SDIO_PSTIMEOUT BIT(23) +#define BIT_SDIO_GTINT4 BIT(22) +#define BIT_SDIO_GTINT3 BIT(21) +#define BIT_SDIO_HSISR_IND BIT(20) +#define BIT_SDIO_CPWM2 BIT(19) +#define BIT_SDIO_CPWM1 BIT(18) +#define BIT_SDIO_C2HCMD_INT BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ - -#define BIT_SHIFT_SPS18_OCP_TH 16 -#define BIT_MASK_SPS18_OCP_TH 0x7fff -#define BIT_SPS18_OCP_TH(x) (((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH) -#define BIT_GET_SPS18_OCP_TH(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH) - +#define BIT_SHIFT_SPS18_OCP_TH 16 +#define BIT_MASK_SPS18_OCP_TH 0x7fff +#define BIT_SPS18_OCP_TH(x) \ + (((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH) +#define BITS_SPS18_OCP_TH (BIT_MASK_SPS18_OCP_TH << BIT_SHIFT_SPS18_OCP_TH) +#define BIT_CLEAR_SPS18_OCP_TH(x) ((x) & (~BITS_SPS18_OCP_TH)) +#define BIT_GET_SPS18_OCP_TH(x) \ + (((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH) +#define BIT_SET_SPS18_OCP_TH(x, v) \ + (BIT_CLEAR_SPS18_OCP_TH(x) | BIT_SPS18_OCP_TH(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_SDIO_BCNERLY_INT BIT(16) -#define BIT_SDIO_TXBCNERR BIT(7) -#define BIT_SDIO_TXBCNOK BIT(6) -#define BIT_SDIO_RXFOVW BIT(5) -#define BIT_SDIO_TXFOVW BIT(4) -#define BIT_SDIO_RXERR BIT(3) -#define BIT_SDIO_TXERR BIT(2) -#define BIT_SDIO_AVAL BIT(1) +#define BIT_SDIO_BCNERLY_INT BIT(16) +#define BIT_SDIO_TXBCNERR BIT(7) +#define BIT_SDIO_TXBCNOK BIT(6) +#define BIT_SDIO_RXFOVW BIT(5) +#define BIT_SDIO_TXFOVW BIT(4) +#define BIT_SDIO_RXERR BIT(3) +#define BIT_SDIO_TXERR BIT(2) +#define BIT_SDIO_AVAL BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ - -#define BIT_SHIFT_OCP_WINDOW 0 -#define BIT_MASK_OCP_WINDOW 0xffff -#define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW) -#define BIT_GET_OCP_WINDOW(x) (((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW) - +#define BIT_SHIFT_OCP_WINDOW 0 +#define BIT_MASK_OCP_WINDOW 0xffff +#define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW) +#define BITS_OCP_WINDOW (BIT_MASK_OCP_WINDOW << BIT_SHIFT_OCP_WINDOW) +#define BIT_CLEAR_OCP_WINDOW(x) ((x) & (~BITS_OCP_WINDOW)) +#define BIT_GET_OCP_WINDOW(x) \ + (((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW) +#define BIT_SET_OCP_WINDOW(x, v) (BIT_CLEAR_OCP_WINDOW(x) | BIT_OCP_WINDOW(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_RX_REQUEST BIT(0) +#define BIT_RX_REQUEST BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_HREG_DBG BIT(23) +#define BIT_HREG_DBG BIT(23) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ +#define BIT_SHIFT_HREG_DBG_V1 12 +#define BIT_MASK_HREG_DBG_V1 0xfff +#define BIT_HREG_DBG_V1(x) \ + (((x) & BIT_MASK_HREG_DBG_V1) << BIT_SHIFT_HREG_DBG_V1) +#define BITS_HREG_DBG_V1 (BIT_MASK_HREG_DBG_V1 << BIT_SHIFT_HREG_DBG_V1) +#define BIT_CLEAR_HREG_DBG_V1(x) ((x) & (~BITS_HREG_DBG_V1)) +#define BIT_GET_HREG_DBG_V1(x) \ + (((x) >> BIT_SHIFT_HREG_DBG_V1) & BIT_MASK_HREG_DBG_V1) +#define BIT_SET_HREG_DBG_V1(x, v) \ + (BIT_CLEAR_HREG_DBG_V1(x) | BIT_HREG_DBG_V1(v)) -#define BIT_SHIFT_HREG_DBG_V1 12 -#define BIT_MASK_HREG_DBG_V1 0xfff -#define BIT_HREG_DBG_V1(x) (((x) & BIT_MASK_HREG_DBG_V1) << BIT_SHIFT_HREG_DBG_V1) -#define BIT_GET_HREG_DBG_V1(x) (((x) >> BIT_SHIFT_HREG_DBG_V1) & BIT_MASK_HREG_DBG_V1) +#endif -#define BIT_MCU_RST BIT(11) -#define BIT_WLOCK_90 BIT(10) -#define BIT_WLOCK_70 BIT(9) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_RSV_CTRL (Offset 0x001C) */ +#define BIT_MCU_RST BIT(11) +#define BIT_WLOCK_90 BIT(10) +#define BIT_WLOCK_70 BIT(9) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_WLMCUIOIF BIT(8) +#define BIT_WLMCUIOIF BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_WLOCK_78 BIT(8) +#define BIT_WLOCK_78 BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_LOCK_ALL_EN BIT(7) +#define BIT_LOCK_ALL_EN BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_R_DIS_PRST BIT(6) +#define BIT_R_DIS_PRST BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_R_DIS_PRST_1 BIT(6) +#define BIT_R_DIS_PRST_1 BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_WLOCK_1C_B6 BIT(5) +#define BIT_WLOCK_1C_B6 BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_R_DIS_PRST_0 BIT(5) +#define BIT_R_DIS_PRST_0 BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_WLOCK_40 BIT(4) -#define BIT_WLOCK_08 BIT(3) -#define BIT_WLOCK_04 BIT(2) -#define BIT_WLOCK_00 BIT(1) -#define BIT_WLOCK_ALL BIT(0) +#define BIT_WLOCK_40 BIT(4) +#define BIT_WLOCK_08 BIT(3) +#define BIT_WLOCK_04 BIT(2) +#define BIT_WLOCK_00 BIT(1) +#define BIT_WLOCK_ALL BIT(0) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_RX_REQ_LEN (Offset 0x1025001C) */ - -#define BIT_SHIFT_RX_REQ_LEN_V1 0 -#define BIT_MASK_RX_REQ_LEN_V1 0x3ffff -#define BIT_RX_REQ_LEN_V1(x) (((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1) -#define BIT_GET_RX_REQ_LEN_V1(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1) - +#define BIT_SHIFT_RX_REQ_LEN_V1 0 +#define BIT_MASK_RX_REQ_LEN_V1 0x3ffff +#define BIT_RX_REQ_LEN_V1(x) \ + (((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1) +#define BITS_RX_REQ_LEN_V1 (BIT_MASK_RX_REQ_LEN_V1 << BIT_SHIFT_RX_REQ_LEN_V1) +#define BIT_CLEAR_RX_REQ_LEN_V1(x) ((x) & (~BITS_RX_REQ_LEN_V1)) +#define BIT_GET_RX_REQ_LEN_V1(x) \ + (((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1) +#define BIT_SET_RX_REQ_LEN_V1(x, v) \ + (BIT_CLEAR_RX_REQ_LEN_V1(x) | BIT_RX_REQ_LEN_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RF_CTRL (Offset 0x001F) */ -#define BIT_RF_SDMRSTB BIT(2) +#define BIT_RF_SDMRSTB BIT(2) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RF0_CTRL (Offset 0x001F) */ -#define BIT_RF0_SDMRSTB BIT(2) +#define BIT_RF0_SDMRSTB BIT(2) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RF_CTRL (Offset 0x001F) */ -#define BIT_RF_RSTB BIT(1) +#define BIT_RF_RSTB BIT(1) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RF0_CTRL (Offset 0x001F) */ -#define BIT_RF0_RSTB BIT(1) +#define BIT_RF0_RSTB BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RF_CTRL (Offset 0x001F) */ -#define BIT_RF_EN BIT(0) +#define BIT_RF_EN BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RF0_CTRL (Offset 0x001F) */ -#define BIT_RF0_EN BIT(0) +#define BIT_RF0_EN BIT(0) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_FREE_TXPG_SEQ_V1 (Offset 0x1025001F) */ - -#define BIT_SHIFT_FREE_TXPG_SEQ 0 -#define BIT_MASK_FREE_TXPG_SEQ 0xff -#define BIT_FREE_TXPG_SEQ(x) (((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ) -#define BIT_GET_FREE_TXPG_SEQ(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ) - +#define BIT_SHIFT_FREE_TXPG_SEQ 0 +#define BIT_MASK_FREE_TXPG_SEQ 0xff +#define BIT_FREE_TXPG_SEQ(x) \ + (((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ) +#define BITS_FREE_TXPG_SEQ (BIT_MASK_FREE_TXPG_SEQ << BIT_SHIFT_FREE_TXPG_SEQ) +#define BIT_CLEAR_FREE_TXPG_SEQ(x) ((x) & (~BITS_FREE_TXPG_SEQ)) +#define BIT_GET_FREE_TXPG_SEQ(x) \ + (((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ) +#define BIT_SET_FREE_TXPG_SEQ(x, v) \ + (BIT_CLEAR_FREE_TXPG_SEQ(x) | BIT_FREE_TXPG_SEQ(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_LPLDH12_RSV1 BIT(31) -#define BIT_LPLDH12_RSV0 BIT(30) +#define BIT_LPLDH12_RSV1 BIT(31) +#define BIT_LPLDH12_RSV0 BIT(30) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_SHIFT_LPLDH12_RSV 29 +#define BIT_MASK_LPLDH12_RSV 0x7 +#define BIT_LPLDH12_RSV(x) \ + (((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV) +#define BITS_LPLDH12_RSV (BIT_MASK_LPLDH12_RSV << BIT_SHIFT_LPLDH12_RSV) +#define BIT_CLEAR_LPLDH12_RSV(x) ((x) & (~BITS_LPLDH12_RSV)) +#define BIT_GET_LPLDH12_RSV(x) \ + (((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV) +#define BIT_SET_LPLDH12_RSV(x, v) \ + (BIT_CLEAR_LPLDH12_RSV(x) | BIT_LPLDH12_RSV(v)) -/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_SHIFT_LPLDH12_RSV 29 -#define BIT_MASK_LPLDH12_RSV 0x7 -#define BIT_LPLDH12_RSV(x) (((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV) -#define BIT_GET_LPLDH12_RSV(x) (((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV) +#define BIT_LPLDH12_SLP BIT(28) +#define BIT_SHIFT_LPLDH12_VADJ 24 +#define BIT_MASK_LPLDH12_VADJ 0xf +#define BIT_LPLDH12_VADJ(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ) +#define BITS_LPLDH12_VADJ (BIT_MASK_LPLDH12_VADJ << BIT_SHIFT_LPLDH12_VADJ) +#define BIT_CLEAR_LPLDH12_VADJ(x) ((x) & (~BITS_LPLDH12_VADJ)) +#define BIT_GET_LPLDH12_VADJ(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ) +#define BIT_SET_LPLDH12_VADJ(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ(x) | BIT_LPLDH12_VADJ(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_PCIE_CALIB_EN BIT(17) -/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#endif -#define BIT_LPLDH12_SLP BIT(28) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LPLDH12_VADJ 24 -#define BIT_MASK_LPLDH12_VADJ 0xf -#define BIT_LPLDH12_VADJ(x) (((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ) -#define BIT_GET_LPLDH12_VADJ(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_LDH12_EN BIT(16) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ +#define BIT_SHIFT_MID_FREEPG_V1 16 +#define BIT_MASK_MID_FREEPG_V1 0xfff +#define BIT_MID_FREEPG_V1(x) \ + (((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1) +#define BITS_MID_FREEPG_V1 (BIT_MASK_MID_FREEPG_V1 << BIT_SHIFT_MID_FREEPG_V1) +#define BIT_CLEAR_MID_FREEPG_V1(x) ((x) & (~BITS_MID_FREEPG_V1)) +#define BIT_GET_MID_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1) +#define BIT_SET_MID_FREEPG_V1(x, v) \ + (BIT_CLEAR_MID_FREEPG_V1(x) | BIT_MID_FREEPG_V1(v)) -/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#endif -#define BIT_PCIE_CALIB_EN BIT(17) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_WLBBOFF_BIG_PWC_EN BIT(14) +#define BIT_WLBBOFF_SMALL_PWC_EN BIT(13) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_LDH12_EN BIT(16) +#define BIT_POW_REGU_P3 BIT(12) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_WLMACOFF_BIG_PWC_EN BIT(12) -/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_MID_FREEPG_V1 16 -#define BIT_MASK_MID_FREEPG_V1 0xfff -#define BIT_MID_FREEPG_V1(x) (((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1) -#define BIT_GET_MID_FREEPG_V1(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_POW_REGU_P2 BIT(11) #endif - #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_WLBBOFF_BIG_PWC_EN BIT(14) -#define BIT_WLBBOFF_SMALL_PWC_EN BIT(13) -#define BIT_WLMACOFF_BIG_PWC_EN BIT(12) -#define BIT_WLPON_PWC_EN BIT(11) +#define BIT_WLPON_PWC_EN BIT(11) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_POW_REGU_P1 BIT(10) +#define BIT_POW_REGU_P1 BIT(10) #endif +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ + +#define BIT_R_SYM_WLBBOFF1_P4_EN BIT(9) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_LDOV12W_EN BIT(8) +#define BIT_LDOV12W_EN BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_SHIFT_ANAPAR_RFC2 8 +#define BIT_MASK_ANAPAR_RFC2 0xff +#define BIT_ANAPAR_RFC2(x) \ + (((x) & BIT_MASK_ANAPAR_RFC2) << BIT_SHIFT_ANAPAR_RFC2) +#define BITS_ANAPAR_RFC2 (BIT_MASK_ANAPAR_RFC2 << BIT_SHIFT_ANAPAR_RFC2) +#define BIT_CLEAR_ANAPAR_RFC2(x) ((x) & (~BITS_ANAPAR_RFC2)) +#define BIT_GET_ANAPAR_RFC2(x) \ + (((x) >> BIT_SHIFT_ANAPAR_RFC2) & BIT_MASK_ANAPAR_RFC2) +#define BIT_SET_ANAPAR_RFC2(x, v) \ + (BIT_CLEAR_ANAPAR_RFC2(x) | BIT_ANAPAR_RFC2(v)) -#define BIT_SHIFT_ANAPAR_RFC2 8 -#define BIT_MASK_ANAPAR_RFC2 0xff -#define BIT_ANAPAR_RFC2(x) (((x) & BIT_MASK_ANAPAR_RFC2) << BIT_SHIFT_ANAPAR_RFC2) -#define BIT_GET_ANAPAR_RFC2(x) (((x) >> BIT_SHIFT_ANAPAR_RFC2) & BIT_MASK_ANAPAR_RFC2) +#endif +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_WLBBOFF1_P3_EN BIT(8) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_EX_XTAL_DRV_DIGI BIT(7) -#define BIT_EX_XTAL_DRV_USB BIT(6) -#define BIT_EX_XTAL_DRV_AFE BIT(5) +#define BIT_EX_XTAL_DRV_DIGI BIT(7) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_WLBBOFF1_P2_EN BIT(7) -/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_LDA12_VOADJ 4 -#define BIT_MASK_LDA12_VOADJ 0xf -#define BIT_LDA12_VOADJ(x) (((x) & BIT_MASK_LDA12_VOADJ) << BIT_SHIFT_LDA12_VOADJ) -#define BIT_GET_LDA12_VOADJ(x) (((x) >> BIT_SHIFT_LDA12_VOADJ) & BIT_MASK_LDA12_VOADJ) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_EX_XTAL_DRV_USB BIT(6) #endif +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ + +#define BIT_R_SYM_WLBBOFF1_P1_EN BIT(6) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_EX_XTAL_DRV_RF2 BIT(4) +#define BIT_EX_XTAL_DRV_AFE BIT(5) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_REG_VOS BIT(3) +#define BIT_SHIFT_LDA12_VOADJ 4 +#define BIT_MASK_LDA12_VOADJ 0xf +#define BIT_LDA12_VOADJ(x) \ + (((x) & BIT_MASK_LDA12_VOADJ) << BIT_SHIFT_LDA12_VOADJ) +#define BITS_LDA12_VOADJ (BIT_MASK_LDA12_VOADJ << BIT_SHIFT_LDA12_VOADJ) +#define BIT_CLEAR_LDA12_VOADJ(x) ((x) & (~BITS_LDA12_VOADJ)) +#define BIT_GET_LDA12_VOADJ(x) \ + (((x) >> BIT_SHIFT_LDA12_VOADJ) & BIT_MASK_LDA12_VOADJ) +#define BIT_SET_LDA12_VOADJ(x, v) \ + (BIT_CLEAR_LDA12_VOADJ(x) | BIT_LDA12_VOADJ(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ + +#define BIT_EX_XTAL_DRV_RF2 BIT(4) + +#endif +#if (HALMAC_8822C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_EX_XTAL_DRV_RF1 BIT(3) -#define BIT_POW_REGU_P0 BIT(2) +#define BIT_R_SYM_WLBBOFF_P4_EN BIT(4) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_LDA12_EN BIT(0) +#define BIT_REG_VOS BIT(3) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_POW_PLL_LDO BIT(0) +#define BIT_EX_XTAL_DRV_RF1 BIT(3) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_WLBBOFF_P3_EN BIT(3) -/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_HIQ_FREEPG_V1 0 -#define BIT_MASK_HIQ_FREEPG_V1 0xfff -#define BIT_HIQ_FREEPG_V1(x) (((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1) -#define BIT_GET_HIQ_FREEPG_V1(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_POW_REGU_P0 BIT(2) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_WLBBOFF_P2_EN BIT(2) +#define BIT_R_SYM_WLBBOFF_P1_EN BIT(1) -/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_ANAPAR_RFC1 0 -#define BIT_MASK_ANAPAR_RFC1 0xff -#define BIT_ANAPAR_RFC1(x) (((x) & BIT_MASK_ANAPAR_RFC1) << BIT_SHIFT_ANAPAR_RFC1) -#define BIT_GET_ANAPAR_RFC1(x) (((x) >> BIT_SHIFT_ANAPAR_RFC1) & BIT_MASK_ANAPAR_RFC1) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_LDA12_EN BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_POW_PLL_LDO BIT(0) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif -#define BIT_AGPIO_GPE BIT(31) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ +#define BIT_SHIFT_HIQ_FREEPG_V1 0 +#define BIT_MASK_HIQ_FREEPG_V1 0xfff +#define BIT_HIQ_FREEPG_V1(x) \ + (((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1) +#define BITS_HIQ_FREEPG_V1 (BIT_MASK_HIQ_FREEPG_V1 << BIT_SHIFT_HIQ_FREEPG_V1) +#define BIT_CLEAR_HIQ_FREEPG_V1(x) ((x) & (~BITS_HIQ_FREEPG_V1)) +#define BIT_GET_HIQ_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1) +#define BIT_SET_HIQ_FREEPG_V1(x, v) \ + (BIT_CLEAR_HIQ_FREEPG_V1(x) | BIT_HIQ_FREEPG_V1(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_XQSEL_V3 BIT(31) +#define BIT_SHIFT_ANAPAR_RFC1 0 +#define BIT_MASK_ANAPAR_RFC1 0xff +#define BIT_ANAPAR_RFC1(x) \ + (((x) & BIT_MASK_ANAPAR_RFC1) << BIT_SHIFT_ANAPAR_RFC1) +#define BITS_ANAPAR_RFC1 (BIT_MASK_ANAPAR_RFC1 << BIT_SHIFT_ANAPAR_RFC1) +#define BIT_CLEAR_ANAPAR_RFC1(x) ((x) & (~BITS_ANAPAR_RFC1)) +#define BIT_GET_ANAPAR_RFC1(x) \ + (((x) >> BIT_SHIFT_ANAPAR_RFC1) & BIT_MASK_ANAPAR_RFC1) +#define BIT_SET_ANAPAR_RFC1(x, v) \ + (BIT_CLEAR_ANAPAR_RFC1(x) | BIT_ANAPAR_RFC1(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_WLBBOFF_EN BIT(0) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_REG_CC 30 -#define BIT_MASK_REG_CC 0x3 -#define BIT_REG_CC(x) (((x) & BIT_MASK_REG_CC) << BIT_SHIFT_REG_CC) -#define BIT_GET_REG_CC(x) (((x) >> BIT_SHIFT_REG_CC) & BIT_MASK_REG_CC) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_AGPIO_GPE BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_CKDELAY_AFE_V1 BIT(30) +#define BIT_XQSEL_V3 BIT(31) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_CKDLY_DIG BIT(28) -#define BIT_CKDLY_USB BIT(27) +#define BIT_SHIFT_REG_CC 30 +#define BIT_MASK_REG_CC 0x3 +#define BIT_REG_CC(x) (((x) & BIT_MASK_REG_CC) << BIT_SHIFT_REG_CC) +#define BITS_REG_CC (BIT_MASK_REG_CC << BIT_SHIFT_REG_CC) +#define BIT_CLEAR_REG_CC(x) ((x) & (~BITS_REG_CC)) +#define BIT_GET_REG_CC(x) (((x) >> BIT_SHIFT_REG_CC) & BIT_MASK_REG_CC) +#define BIT_SET_REG_CC(x, v) (BIT_CLEAR_REG_CC(x) | BIT_REG_CC(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_CKDELAY_AFE_V1 BIT(30) -#define BIT_SHIFT_XTAL_GPIO_V1 27 -#define BIT_MASK_XTAL_GPIO_V1 0x7 -#define BIT_XTAL_GPIO_V1(x) (((x) & BIT_MASK_XTAL_GPIO_V1) << BIT_SHIFT_XTAL_GPIO_V1) -#define BIT_GET_XTAL_GPIO_V1(x) (((x) >> BIT_SHIFT_XTAL_GPIO_V1) & BIT_MASK_XTAL_GPIO_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_CKDLY_DIG BIT(28) +#define BIT_CKDLY_USB BIT(27) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_CKDLY_AFE BIT(26) +#define BIT_SHIFT_XTAL_GPIO_V1 27 +#define BIT_MASK_XTAL_GPIO_V1 0x7 +#define BIT_XTAL_GPIO_V1(x) \ + (((x) & BIT_MASK_XTAL_GPIO_V1) << BIT_SHIFT_XTAL_GPIO_V1) +#define BITS_XTAL_GPIO_V1 (BIT_MASK_XTAL_GPIO_V1 << BIT_SHIFT_XTAL_GPIO_V1) +#define BIT_CLEAR_XTAL_GPIO_V1(x) ((x) & (~BITS_XTAL_GPIO_V1)) +#define BIT_GET_XTAL_GPIO_V1(x) \ + (((x) >> BIT_SHIFT_XTAL_GPIO_V1) & BIT_MASK_XTAL_GPIO_V1) +#define BIT_SET_XTAL_GPIO_V1(x, v) \ + (BIT_CLEAR_XTAL_GPIO_V1(x) | BIT_XTAL_GPIO_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_CKDLY_AFE BIT(26) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_XTAL_CAP_XI 25 -#define BIT_MASK_XTAL_CAP_XI 0x3f -#define BIT_XTAL_CAP_XI(x) (((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI) -#define BIT_GET_XTAL_CAP_XI(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_CAP_XI 25 +#define BIT_MASK_XTAL_CAP_XI 0x3f +#define BIT_XTAL_CAP_XI(x) \ + (((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI) +#define BITS_XTAL_CAP_XI (BIT_MASK_XTAL_CAP_XI << BIT_SHIFT_XTAL_CAP_XI) +#define BIT_CLEAR_XTAL_CAP_XI(x) ((x) & (~BITS_XTAL_CAP_XI)) +#define BIT_GET_XTAL_CAP_XI(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI) +#define BIT_SET_XTAL_CAP_XI(x, v) \ + (BIT_CLEAR_XTAL_CAP_XI(x) | BIT_XTAL_CAP_XI(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_DIG_DRV_1_TO_0 25 +#define BIT_MASK_XTAL_DIG_DRV_1_TO_0 0x3 +#define BIT_XTAL_DIG_DRV_1_TO_0(x) \ + (((x) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) +#define BITS_XTAL_DIG_DRV_1_TO_0 \ + (BIT_MASK_XTAL_DIG_DRV_1_TO_0 << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) +#define BIT_CLEAR_XTAL_DIG_DRV_1_TO_0(x) ((x) & (~BITS_XTAL_DIG_DRV_1_TO_0)) +#define BIT_GET_XTAL_DIG_DRV_1_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) +#define BIT_SET_XTAL_DIG_DRV_1_TO_0(x, v) \ + (BIT_CLEAR_XTAL_DIG_DRV_1_TO_0(x) | BIT_XTAL_DIG_DRV_1_TO_0(v)) -#define BIT_SHIFT_XTAL_DIG_DRV_1_TO_0 25 -#define BIT_MASK_XTAL_DIG_DRV_1_TO_0 0x3 -#define BIT_XTAL_DIG_DRV_1_TO_0(x) (((x) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) -#define BIT_GET_XTAL_DIG_DRV_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) - -#define BIT_XTAL_GDIG BIT(24) +#define BIT_XTAL_GDIG BIT(24) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_GPIO 23 -#define BIT_MASK_XTAL_GPIO 0x7 -#define BIT_XTAL_GPIO(x) (((x) & BIT_MASK_XTAL_GPIO) << BIT_SHIFT_XTAL_GPIO) -#define BIT_GET_XTAL_GPIO(x) (((x) >> BIT_SHIFT_XTAL_GPIO) & BIT_MASK_XTAL_GPIO) - +#define BIT_SHIFT_XTAL_GPIO 23 +#define BIT_MASK_XTAL_GPIO 0x7 +#define BIT_XTAL_GPIO(x) (((x) & BIT_MASK_XTAL_GPIO) << BIT_SHIFT_XTAL_GPIO) +#define BITS_XTAL_GPIO (BIT_MASK_XTAL_GPIO << BIT_SHIFT_XTAL_GPIO) +#define BIT_CLEAR_XTAL_GPIO(x) ((x) & (~BITS_XTAL_GPIO)) +#define BIT_GET_XTAL_GPIO(x) (((x) >> BIT_SHIFT_XTAL_GPIO) & BIT_MASK_XTAL_GPIO) +#define BIT_SET_XTAL_GPIO(x, v) (BIT_CLEAR_XTAL_GPIO(x) | BIT_XTAL_GPIO(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_DRV_DIGI 23 +#define BIT_MASK_XTAL_DRV_DIGI 0x3 +#define BIT_XTAL_DRV_DIGI(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI) +#define BITS_XTAL_DRV_DIGI (BIT_MASK_XTAL_DRV_DIGI << BIT_SHIFT_XTAL_DRV_DIGI) +#define BIT_CLEAR_XTAL_DRV_DIGI(x) ((x) & (~BITS_XTAL_DRV_DIGI)) +#define BIT_GET_XTAL_DRV_DIGI(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI) +#define BIT_SET_XTAL_DRV_DIGI(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI(x) | BIT_XTAL_DRV_DIGI(v)) -#define BIT_SHIFT_XTAL_DRV_DIGI 23 -#define BIT_MASK_XTAL_DRV_DIGI 0x3 -#define BIT_XTAL_DRV_DIGI(x) (((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI) -#define BIT_GET_XTAL_DRV_DIGI(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI) - -#define BIT_XTAL_DRV_USB_BIT1 BIT(22) +#define BIT_XTAL_DRV_USB_BIT1 BIT(22) #endif - -#if (HALMAC_8814A_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0 22 -#define BIT_MASK_XTAL_RDRV_RF2_1_TO_0 0x3 -#define BIT_XTAL_RDRV_RF2_1_TO_0(x) (((x) & BIT_MASK_XTAL_RDRV_RF2_1_TO_0) << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) -#define BIT_GET_XTAL_RDRV_RF2_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) & BIT_MASK_XTAL_RDRV_RF2_1_TO_0) - +#define BIT_XTAL_DRV_RF_LATCH_V2 BIT(22) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8814A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GMN_4 BIT(21) +#define BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0 22 +#define BIT_MASK_XTAL_RDRV_RF2_1_TO_0 0x3 +#define BIT_XTAL_RDRV_RF2_1_TO_0(x) \ + (((x) & BIT_MASK_XTAL_RDRV_RF2_1_TO_0) \ + << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) +#define BITS_XTAL_RDRV_RF2_1_TO_0 \ + (BIT_MASK_XTAL_RDRV_RF2_1_TO_0 << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) +#define BIT_CLEAR_XTAL_RDRV_RF2_1_TO_0(x) ((x) & (~BITS_XTAL_RDRV_RF2_1_TO_0)) +#define BIT_GET_XTAL_RDRV_RF2_1_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) & \ + BIT_MASK_XTAL_RDRV_RF2_1_TO_0) +#define BIT_SET_XTAL_RDRV_RF2_1_TO_0(x, v) \ + (BIT_CLEAR_XTAL_RDRV_RF2_1_TO_0(x) | BIT_XTAL_RDRV_RF2_1_TO_0(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_XTAL_GMN_4 BIT(21) -#define BIT_SHIFT_MAC_CLK_SEL 20 -#define BIT_MASK_MAC_CLK_SEL 0x3 -#define BIT_MAC_CLK_SEL(x) (((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL) -#define BIT_GET_MAC_CLK_SEL(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_MAC_CLK_SEL 20 +#define BIT_MASK_MAC_CLK_SEL 0x3 +#define BIT_MAC_CLK_SEL(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL) +#define BITS_MAC_CLK_SEL (BIT_MASK_MAC_CLK_SEL << BIT_SHIFT_MAC_CLK_SEL) +#define BIT_CLEAR_MAC_CLK_SEL(x) ((x) & (~BITS_MAC_CLK_SEL)) +#define BIT_GET_MAC_CLK_SEL(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL) +#define BIT_SET_MAC_CLK_SEL(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL(x) | BIT_MAC_CLK_SEL(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_DRV_USB_BIT0 BIT(19) +#define BIT_XTAL_DRV_USB_BIT0 BIT(19) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_RDRV_1_TO_0 19 -#define BIT_MASK_XTAL_RDRV_1_TO_0 0x3 -#define BIT_XTAL_RDRV_1_TO_0(x) (((x) & BIT_MASK_XTAL_RDRV_1_TO_0) << BIT_SHIFT_XTAL_RDRV_1_TO_0) -#define BIT_GET_XTAL_RDRV_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_RDRV_1_TO_0) & BIT_MASK_XTAL_RDRV_1_TO_0) - +#define BIT_SHIFT_XTAL_RDRV_1_TO_0 19 +#define BIT_MASK_XTAL_RDRV_1_TO_0 0x3 +#define BIT_XTAL_RDRV_1_TO_0(x) \ + (((x) & BIT_MASK_XTAL_RDRV_1_TO_0) << BIT_SHIFT_XTAL_RDRV_1_TO_0) +#define BITS_XTAL_RDRV_1_TO_0 \ + (BIT_MASK_XTAL_RDRV_1_TO_0 << BIT_SHIFT_XTAL_RDRV_1_TO_0) +#define BIT_CLEAR_XTAL_RDRV_1_TO_0(x) ((x) & (~BITS_XTAL_RDRV_1_TO_0)) +#define BIT_GET_XTAL_RDRV_1_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_RDRV_1_TO_0) & BIT_MASK_XTAL_RDRV_1_TO_0) +#define BIT_SET_XTAL_RDRV_1_TO_0(x, v) \ + (BIT_CLEAR_XTAL_RDRV_1_TO_0(x) | BIT_XTAL_RDRV_1_TO_0(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_DIG_DRV 18 -#define BIT_MASK_XTAL_DIG_DRV 0x3 -#define BIT_XTAL_DIG_DRV(x) (((x) & BIT_MASK_XTAL_DIG_DRV) << BIT_SHIFT_XTAL_DIG_DRV) -#define BIT_GET_XTAL_DIG_DRV(x) (((x) >> BIT_SHIFT_XTAL_DIG_DRV) & BIT_MASK_XTAL_DIG_DRV) - +#define BIT_SHIFT_XTAL_DIG_DRV 18 +#define BIT_MASK_XTAL_DIG_DRV 0x3 +#define BIT_XTAL_DIG_DRV(x) \ + (((x) & BIT_MASK_XTAL_DIG_DRV) << BIT_SHIFT_XTAL_DIG_DRV) +#define BITS_XTAL_DIG_DRV (BIT_MASK_XTAL_DIG_DRV << BIT_SHIFT_XTAL_DIG_DRV) +#define BIT_CLEAR_XTAL_DIG_DRV(x) ((x) & (~BITS_XTAL_DIG_DRV)) +#define BIT_GET_XTAL_DIG_DRV(x) \ + (((x) >> BIT_SHIFT_XTAL_DIG_DRV) & BIT_MASK_XTAL_DIG_DRV) +#define BIT_SET_XTAL_DIG_DRV(x, v) \ + (BIT_CLEAR_XTAL_DIG_DRV(x) | BIT_XTAL_DIG_DRV(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GMP_4 BIT(18) +#define BIT_XTAL_GMP_4 BIT(18) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GATE_DIG BIT(17) +#define BIT_XTAL_GATE_DIG BIT(17) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_DRV_AFE 17 -#define BIT_MASK_XTAL_DRV_AFE 0x3 -#define BIT_XTAL_DRV_AFE(x) (((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE) -#define BIT_GET_XTAL_DRV_AFE(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE) - +#define BIT_SHIFT_XTAL_DRV_AFE 17 +#define BIT_MASK_XTAL_DRV_AFE 0x3 +#define BIT_XTAL_DRV_AFE(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE) +#define BITS_XTAL_DRV_AFE (BIT_MASK_XTAL_DRV_AFE << BIT_SHIFT_XTAL_DRV_AFE) +#define BIT_CLEAR_XTAL_DRV_AFE(x) ((x) & (~BITS_XTAL_DRV_AFE)) +#define BIT_GET_XTAL_DRV_AFE(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE) +#define BIT_SET_XTAL_DRV_AFE(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE(x) | BIT_XTAL_DRV_AFE(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ - -#define BIT_SHIFT_PUB_FREEPG_V1 16 -#define BIT_MASK_PUB_FREEPG_V1 0xfff -#define BIT_PUB_FREEPG_V1(x) (((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1) -#define BIT_GET_PUB_FREEPG_V1(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1) - +#define BIT_SHIFT_PUB_FREEPG_V1 16 +#define BIT_MASK_PUB_FREEPG_V1 0xfff +#define BIT_PUB_FREEPG_V1(x) \ + (((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1) +#define BITS_PUB_FREEPG_V1 (BIT_MASK_PUB_FREEPG_V1 << BIT_SHIFT_PUB_FREEPG_V1) +#define BIT_CLEAR_PUB_FREEPG_V1(x) ((x) & (~BITS_PUB_FREEPG_V1)) +#define BIT_GET_PUB_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1) +#define BIT_SET_PUB_FREEPG_V1(x, v) \ + (BIT_CLEAR_PUB_FREEPG_V1(x) | BIT_PUB_FREEPG_V1(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_ADRV_1_TO_0 16 -#define BIT_MASK_XTAL_ADRV_1_TO_0 0x3 -#define BIT_XTAL_ADRV_1_TO_0(x) (((x) & BIT_MASK_XTAL_ADRV_1_TO_0) << BIT_SHIFT_XTAL_ADRV_1_TO_0) -#define BIT_GET_XTAL_ADRV_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_ADRV_1_TO_0) & BIT_MASK_XTAL_ADRV_1_TO_0) - +#define BIT_SHIFT_XTAL_ADRV_1_TO_0 16 +#define BIT_MASK_XTAL_ADRV_1_TO_0 0x3 +#define BIT_XTAL_ADRV_1_TO_0(x) \ + (((x) & BIT_MASK_XTAL_ADRV_1_TO_0) << BIT_SHIFT_XTAL_ADRV_1_TO_0) +#define BITS_XTAL_ADRV_1_TO_0 \ + (BIT_MASK_XTAL_ADRV_1_TO_0 << BIT_SHIFT_XTAL_ADRV_1_TO_0) +#define BIT_CLEAR_XTAL_ADRV_1_TO_0(x) ((x) & (~BITS_XTAL_ADRV_1_TO_0)) +#define BIT_GET_XTAL_ADRV_1_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_ADRV_1_TO_0) & BIT_MASK_XTAL_ADRV_1_TO_0) +#define BIT_SET_XTAL_ADRV_1_TO_0(x, v) \ + (BIT_CLEAR_XTAL_ADRV_1_TO_0(x) | BIT_XTAL_ADRV_1_TO_0(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_RF_DRV 15 -#define BIT_MASK_XTAL_RF_DRV 0x3 -#define BIT_XTAL_RF_DRV(x) (((x) & BIT_MASK_XTAL_RF_DRV) << BIT_SHIFT_XTAL_RF_DRV) -#define BIT_GET_XTAL_RF_DRV(x) (((x) >> BIT_SHIFT_XTAL_RF_DRV) & BIT_MASK_XTAL_RF_DRV) - +#define BIT_SHIFT_XTAL_RF_DRV 15 +#define BIT_MASK_XTAL_RF_DRV 0x3 +#define BIT_XTAL_RF_DRV(x) \ + (((x) & BIT_MASK_XTAL_RF_DRV) << BIT_SHIFT_XTAL_RF_DRV) +#define BITS_XTAL_RF_DRV (BIT_MASK_XTAL_RF_DRV << BIT_SHIFT_XTAL_RF_DRV) +#define BIT_CLEAR_XTAL_RF_DRV(x) ((x) & (~BITS_XTAL_RF_DRV)) +#define BIT_GET_XTAL_RF_DRV(x) \ + (((x) >> BIT_SHIFT_XTAL_RF_DRV) & BIT_MASK_XTAL_RF_DRV) +#define BIT_SET_XTAL_RF_DRV(x, v) \ + (BIT_CLEAR_XTAL_RF_DRV(x) | BIT_XTAL_RF_DRV(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_DRV_RF2 15 -#define BIT_MASK_XTAL_DRV_RF2 0x3 -#define BIT_XTAL_DRV_RF2(x) (((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2) -#define BIT_GET_XTAL_DRV_RF2(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2) - +#define BIT_SHIFT_XTAL_DRV_RF2 15 +#define BIT_MASK_XTAL_DRV_RF2 0x3 +#define BIT_XTAL_DRV_RF2(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2) +#define BITS_XTAL_DRV_RF2 (BIT_MASK_XTAL_DRV_RF2 << BIT_SHIFT_XTAL_DRV_RF2) +#define BIT_CLEAR_XTAL_DRV_RF2(x) ((x) & (~BITS_XTAL_DRV_RF2)) +#define BIT_GET_XTAL_DRV_RF2(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2) +#define BIT_SET_XTAL_DRV_RF2(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2(x) | BIT_XTAL_DRV_RF2(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GAFE BIT(15) +#define BIT_XTAL_GAFE BIT(15) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_XTAL_RF_GATE BIT(14) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_DRV_RF1 13 -#define BIT_MASK_XTAL_DRV_RF1 0x3 -#define BIT_XTAL_DRV_RF1(x) (((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1) -#define BIT_GET_XTAL_DRV_RF1(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1) - +#define BIT_XTAL_RF_GATE BIT(14) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_DDRV_1_TO_0 13 -#define BIT_MASK_XTAL_DDRV_1_TO_0 0x3 -#define BIT_XTAL_DDRV_1_TO_0(x) (((x) & BIT_MASK_XTAL_DDRV_1_TO_0) << BIT_SHIFT_XTAL_DDRV_1_TO_0) -#define BIT_GET_XTAL_DDRV_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_DDRV_1_TO_0) & BIT_MASK_XTAL_DDRV_1_TO_0) - +#define BIT_SHIFT_XTAL_DDRV_1_TO_0 13 +#define BIT_MASK_XTAL_DDRV_1_TO_0 0x3 +#define BIT_XTAL_DDRV_1_TO_0(x) \ + (((x) & BIT_MASK_XTAL_DDRV_1_TO_0) << BIT_SHIFT_XTAL_DDRV_1_TO_0) +#define BITS_XTAL_DDRV_1_TO_0 \ + (BIT_MASK_XTAL_DDRV_1_TO_0 << BIT_SHIFT_XTAL_DDRV_1_TO_0) +#define BIT_CLEAR_XTAL_DDRV_1_TO_0(x) ((x) & (~BITS_XTAL_DDRV_1_TO_0)) +#define BIT_GET_XTAL_DDRV_1_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_DDRV_1_TO_0) & BIT_MASK_XTAL_DDRV_1_TO_0) +#define BIT_SET_XTAL_DDRV_1_TO_0(x, v) \ + (BIT_CLEAR_XTAL_DDRV_1_TO_0(x) | BIT_XTAL_DDRV_1_TO_0(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_AFE_DRV 12 -#define BIT_MASK_XTAL_AFE_DRV 0x3 -#define BIT_XTAL_AFE_DRV(x) (((x) & BIT_MASK_XTAL_AFE_DRV) << BIT_SHIFT_XTAL_AFE_DRV) -#define BIT_GET_XTAL_AFE_DRV(x) (((x) >> BIT_SHIFT_XTAL_AFE_DRV) & BIT_MASK_XTAL_AFE_DRV) - +#define BIT_SHIFT_XTAL_AFE_DRV 12 +#define BIT_MASK_XTAL_AFE_DRV 0x3 +#define BIT_XTAL_AFE_DRV(x) \ + (((x) & BIT_MASK_XTAL_AFE_DRV) << BIT_SHIFT_XTAL_AFE_DRV) +#define BITS_XTAL_AFE_DRV (BIT_MASK_XTAL_AFE_DRV << BIT_SHIFT_XTAL_AFE_DRV) +#define BIT_CLEAR_XTAL_AFE_DRV(x) ((x) & (~BITS_XTAL_AFE_DRV)) +#define BIT_GET_XTAL_AFE_DRV(x) \ + (((x) >> BIT_SHIFT_XTAL_AFE_DRV) & BIT_MASK_XTAL_AFE_DRV) +#define BIT_SET_XTAL_AFE_DRV(x, v) \ + (BIT_CLEAR_XTAL_AFE_DRV(x) | BIT_XTAL_AFE_DRV(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_DELAY_DIGI BIT(12) +#define BIT_XTAL_DELAY_DIGI BIT(12) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GUSB BIT(12) +#define BIT_XTAL_GUSB BIT(12) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GATE_AFE BIT(11) +#define BIT_XTAL_GATE_AFE BIT(11) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_DELAY_USB BIT(11) -#define BIT_XTAL_DELAY_AFE BIT(10) +#define BIT_XTAL_DELAY_USB BIT(11) +#define BIT_XTAL_DELAY_AFE BIT(10) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_USB_DRV 9 -#define BIT_MASK_XTAL_USB_DRV 0x3 -#define BIT_XTAL_USB_DRV(x) (((x) & BIT_MASK_XTAL_USB_DRV) << BIT_SHIFT_XTAL_USB_DRV) -#define BIT_GET_XTAL_USB_DRV(x) (((x) >> BIT_SHIFT_XTAL_USB_DRV) & BIT_MASK_XTAL_USB_DRV) - +#define BIT_SHIFT_XTAL_USB_DRV 9 +#define BIT_MASK_XTAL_USB_DRV 0x3 +#define BIT_XTAL_USB_DRV(x) \ + (((x) & BIT_MASK_XTAL_USB_DRV) << BIT_SHIFT_XTAL_USB_DRV) +#define BITS_XTAL_USB_DRV (BIT_MASK_XTAL_USB_DRV << BIT_SHIFT_XTAL_USB_DRV) +#define BIT_CLEAR_XTAL_USB_DRV(x) ((x) & (~BITS_XTAL_USB_DRV)) +#define BIT_GET_XTAL_USB_DRV(x) \ + (((x) >> BIT_SHIFT_XTAL_USB_DRV) & BIT_MASK_XTAL_USB_DRV) +#define BIT_SET_XTAL_USB_DRV(x, v) \ + (BIT_CLEAR_XTAL_USB_DRV(x) | BIT_XTAL_USB_DRV(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_LP_V1 BIT(9) +#define BIT_XTAL_LP_V1 BIT(9) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GATE_USB BIT(8) +#define BIT_XTAL_GATE_USB BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GM_SEP_V1 BIT(8) +#define BIT_XTAL_GM_SEP_V1 BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_GMN_3_TO_0 8 -#define BIT_MASK_XTAL_GMN_3_TO_0 0xf -#define BIT_XTAL_GMN_3_TO_0(x) (((x) & BIT_MASK_XTAL_GMN_3_TO_0) << BIT_SHIFT_XTAL_GMN_3_TO_0) -#define BIT_GET_XTAL_GMN_3_TO_0(x) (((x) >> BIT_SHIFT_XTAL_GMN_3_TO_0) & BIT_MASK_XTAL_GMN_3_TO_0) - +#define BIT_SHIFT_XTAL_GMN_3_TO_0 8 +#define BIT_MASK_XTAL_GMN_3_TO_0 0xf +#define BIT_XTAL_GMN_3_TO_0(x) \ + (((x) & BIT_MASK_XTAL_GMN_3_TO_0) << BIT_SHIFT_XTAL_GMN_3_TO_0) +#define BITS_XTAL_GMN_3_TO_0 \ + (BIT_MASK_XTAL_GMN_3_TO_0 << BIT_SHIFT_XTAL_GMN_3_TO_0) +#define BIT_CLEAR_XTAL_GMN_3_TO_0(x) ((x) & (~BITS_XTAL_GMN_3_TO_0)) +#define BIT_GET_XTAL_GMN_3_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_3_TO_0) & BIT_MASK_XTAL_GMN_3_TO_0) +#define BIT_SET_XTAL_GMN_3_TO_0(x, v) \ + (BIT_CLEAR_XTAL_GMN_3_TO_0(x) | BIT_XTAL_GMN_3_TO_0(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_LDO_VREF_V1 BIT(7) +#define BIT_XTAL_LDO_VREF_V1 BIT(7) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_LDO_VREF 7 -#define BIT_MASK_XTAL_LDO_VREF 0x7 -#define BIT_XTAL_LDO_VREF(x) (((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF) -#define BIT_GET_XTAL_LDO_VREF(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF) - +#define BIT_SHIFT_XTAL_LDO_VREF 7 +#define BIT_MASK_XTAL_LDO_VREF 0x7 +#define BIT_XTAL_LDO_VREF(x) \ + (((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF) +#define BITS_XTAL_LDO_VREF (BIT_MASK_XTAL_LDO_VREF << BIT_SHIFT_XTAL_LDO_VREF) +#define BIT_CLEAR_XTAL_LDO_VREF(x) ((x) & (~BITS_XTAL_LDO_VREF)) +#define BIT_GET_XTAL_LDO_VREF(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF) +#define BIT_SET_XTAL_LDO_VREF(x, v) \ + (BIT_CLEAR_XTAL_LDO_VREF(x) | BIT_XTAL_LDO_VREF(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_XQSEL_RF BIT(6) -#define BIT_XTAL_XQSEL BIT(5) +#define BIT_XTAL_XQSEL_RF BIT(6) +#define BIT_XTAL_XQSEL BIT(5) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_GMP 4 -#define BIT_MASK_XTAL_GMP 0xf -#define BIT_XTAL_GMP(x) (((x) & BIT_MASK_XTAL_GMP) << BIT_SHIFT_XTAL_GMP) -#define BIT_GET_XTAL_GMP(x) (((x) >> BIT_SHIFT_XTAL_GMP) & BIT_MASK_XTAL_GMP) - +#define BIT_SHIFT_XTAL_GMP 4 +#define BIT_MASK_XTAL_GMP 0xf +#define BIT_XTAL_GMP(x) (((x) & BIT_MASK_XTAL_GMP) << BIT_SHIFT_XTAL_GMP) +#define BITS_XTAL_GMP (BIT_MASK_XTAL_GMP << BIT_SHIFT_XTAL_GMP) +#define BIT_CLEAR_XTAL_GMP(x) ((x) & (~BITS_XTAL_GMP)) +#define BIT_GET_XTAL_GMP(x) (((x) >> BIT_SHIFT_XTAL_GMP) & BIT_MASK_XTAL_GMP) +#define BIT_SET_XTAL_GMP(x, v) (BIT_CLEAR_XTAL_GMP(x) | BIT_XTAL_GMP(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_GMP_3_TO_0 4 -#define BIT_MASK_XTAL_GMP_3_TO_0 0xf -#define BIT_XTAL_GMP_3_TO_0(x) (((x) & BIT_MASK_XTAL_GMP_3_TO_0) << BIT_SHIFT_XTAL_GMP_3_TO_0) -#define BIT_GET_XTAL_GMP_3_TO_0(x) (((x) >> BIT_SHIFT_XTAL_GMP_3_TO_0) & BIT_MASK_XTAL_GMP_3_TO_0) - +#define BIT_SHIFT_XTAL_GMP_3_TO_0 4 +#define BIT_MASK_XTAL_GMP_3_TO_0 0xf +#define BIT_XTAL_GMP_3_TO_0(x) \ + (((x) & BIT_MASK_XTAL_GMP_3_TO_0) << BIT_SHIFT_XTAL_GMP_3_TO_0) +#define BITS_XTAL_GMP_3_TO_0 \ + (BIT_MASK_XTAL_GMP_3_TO_0 << BIT_SHIFT_XTAL_GMP_3_TO_0) +#define BIT_CLEAR_XTAL_GMP_3_TO_0(x) ((x) & (~BITS_XTAL_GMP_3_TO_0)) +#define BIT_GET_XTAL_GMP_3_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_3_TO_0) & BIT_MASK_XTAL_GMP_3_TO_0) +#define BIT_SET_XTAL_GMP_3_TO_0(x, v) \ + (BIT_CLEAR_XTAL_GMP_3_TO_0(x) | BIT_XTAL_GMP_3_TO_0(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_GMN_V1 3 -#define BIT_MASK_XTAL_GMN_V1 0x3 -#define BIT_XTAL_GMN_V1(x) (((x) & BIT_MASK_XTAL_GMN_V1) << BIT_SHIFT_XTAL_GMN_V1) -#define BIT_GET_XTAL_GMN_V1(x) (((x) >> BIT_SHIFT_XTAL_GMN_V1) & BIT_MASK_XTAL_GMN_V1) - +#define BIT_SHIFT_XTAL_GMN_V1 3 +#define BIT_MASK_XTAL_GMN_V1 0x3 +#define BIT_XTAL_GMN_V1(x) \ + (((x) & BIT_MASK_XTAL_GMN_V1) << BIT_SHIFT_XTAL_GMN_V1) +#define BITS_XTAL_GMN_V1 (BIT_MASK_XTAL_GMN_V1 << BIT_SHIFT_XTAL_GMN_V1) +#define BIT_CLEAR_XTAL_GMN_V1(x) ((x) & (~BITS_XTAL_GMN_V1)) +#define BIT_GET_XTAL_GMN_V1(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V1) & BIT_MASK_XTAL_GMN_V1) +#define BIT_SET_XTAL_GMN_V1(x, v) \ + (BIT_CLEAR_XTAL_GMN_V1(x) | BIT_XTAL_GMN_V1(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_GMN_V2 3 -#define BIT_MASK_XTAL_GMN_V2 0x3 -#define BIT_XTAL_GMN_V2(x) (((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2) -#define BIT_GET_XTAL_GMN_V2(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2) - +#define BIT_SHIFT_XTAL_GMN_V2 3 +#define BIT_MASK_XTAL_GMN_V2 0x3 +#define BIT_XTAL_GMN_V2(x) \ + (((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2) +#define BITS_XTAL_GMN_V2 (BIT_MASK_XTAL_GMN_V2 << BIT_SHIFT_XTAL_GMN_V2) +#define BIT_CLEAR_XTAL_GMN_V2(x) ((x) & (~BITS_XTAL_GMN_V2)) +#define BIT_GET_XTAL_GMN_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2) +#define BIT_SET_XTAL_GMN_V2(x, v) \ + (BIT_CLEAR_XTAL_GMN_V2(x) | BIT_XTAL_GMN_V2(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_LDO_VCM 2 -#define BIT_MASK_XTAL_LDO_VCM 0x3 -#define BIT_XTAL_LDO_VCM(x) (((x) & BIT_MASK_XTAL_LDO_VCM) << BIT_SHIFT_XTAL_LDO_VCM) -#define BIT_GET_XTAL_LDO_VCM(x) (((x) >> BIT_SHIFT_XTAL_LDO_VCM) & BIT_MASK_XTAL_LDO_VCM) - +#define BIT_SHIFT_XTAL_LDO_VCM 2 +#define BIT_MASK_XTAL_LDO_VCM 0x3 +#define BIT_XTAL_LDO_VCM(x) \ + (((x) & BIT_MASK_XTAL_LDO_VCM) << BIT_SHIFT_XTAL_LDO_VCM) +#define BITS_XTAL_LDO_VCM (BIT_MASK_XTAL_LDO_VCM << BIT_SHIFT_XTAL_LDO_VCM) +#define BIT_CLEAR_XTAL_LDO_VCM(x) ((x) & (~BITS_XTAL_LDO_VCM)) +#define BIT_GET_XTAL_LDO_VCM(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_VCM) & BIT_MASK_XTAL_LDO_VCM) +#define BIT_SET_XTAL_LDO_VCM(x, v) \ + (BIT_CLEAR_XTAL_LDO_VCM(x) | BIT_XTAL_LDO_VCM(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_DRV_LDO_VCM_1_TO_0 2 -#define BIT_MASK_DRV_LDO_VCM_1_TO_0 0x3 -#define BIT_DRV_LDO_VCM_1_TO_0(x) (((x) & BIT_MASK_DRV_LDO_VCM_1_TO_0) << BIT_SHIFT_DRV_LDO_VCM_1_TO_0) -#define BIT_GET_DRV_LDO_VCM_1_TO_0(x) (((x) >> BIT_SHIFT_DRV_LDO_VCM_1_TO_0) & BIT_MASK_DRV_LDO_VCM_1_TO_0) - +#define BIT_SHIFT_DRV_LDO_VCM_1_TO_0 2 +#define BIT_MASK_DRV_LDO_VCM_1_TO_0 0x3 +#define BIT_DRV_LDO_VCM_1_TO_0(x) \ + (((x) & BIT_MASK_DRV_LDO_VCM_1_TO_0) << BIT_SHIFT_DRV_LDO_VCM_1_TO_0) +#define BITS_DRV_LDO_VCM_1_TO_0 \ + (BIT_MASK_DRV_LDO_VCM_1_TO_0 << BIT_SHIFT_DRV_LDO_VCM_1_TO_0) +#define BIT_CLEAR_DRV_LDO_VCM_1_TO_0(x) ((x) & (~BITS_DRV_LDO_VCM_1_TO_0)) +#define BIT_GET_DRV_LDO_VCM_1_TO_0(x) \ + (((x) >> BIT_SHIFT_DRV_LDO_VCM_1_TO_0) & BIT_MASK_DRV_LDO_VCM_1_TO_0) +#define BIT_SET_DRV_LDO_VCM_1_TO_0(x, v) \ + (BIT_CLEAR_DRV_LDO_VCM_1_TO_0(x) | BIT_DRV_LDO_VCM_1_TO_0(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_DUMMY BIT(1) +#define BIT_XTAL_DUMMY BIT(1) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_GMP_V1 1 -#define BIT_MASK_XTAL_GMP_V1 0x3 -#define BIT_XTAL_GMP_V1(x) (((x) & BIT_MASK_XTAL_GMP_V1) << BIT_SHIFT_XTAL_GMP_V1) -#define BIT_GET_XTAL_GMP_V1(x) (((x) >> BIT_SHIFT_XTAL_GMP_V1) & BIT_MASK_XTAL_GMP_V1) - +#define BIT_SHIFT_XTAL_GMP_V1 1 +#define BIT_MASK_XTAL_GMP_V1 0x3 +#define BIT_XTAL_GMP_V1(x) \ + (((x) & BIT_MASK_XTAL_GMP_V1) << BIT_SHIFT_XTAL_GMP_V1) +#define BITS_XTAL_GMP_V1 (BIT_MASK_XTAL_GMP_V1 << BIT_SHIFT_XTAL_GMP_V1) +#define BIT_CLEAR_XTAL_GMP_V1(x) ((x) & (~BITS_XTAL_GMP_V1)) +#define BIT_GET_XTAL_GMP_V1(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V1) & BIT_MASK_XTAL_GMP_V1) +#define BIT_SET_XTAL_GMP_V1(x, v) \ + (BIT_CLEAR_XTAL_GMP_V1(x) | BIT_XTAL_GMP_V1(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XQSEL_RF_INITIAL_V1 BIT(1) +#define BIT_XQSEL_RF_INITIAL_V1 BIT(1) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_GMP_V2 1 -#define BIT_MASK_XTAL_GMP_V2 0x3 -#define BIT_XTAL_GMP_V2(x) (((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2) -#define BIT_GET_XTAL_GMP_V2(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2) - +#define BIT_SHIFT_XTAL_GMP_V2 1 +#define BIT_MASK_XTAL_GMP_V2 0x3 +#define BIT_XTAL_GMP_V2(x) \ + (((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2) +#define BITS_XTAL_GMP_V2 (BIT_MASK_XTAL_GMP_V2 << BIT_SHIFT_XTAL_GMP_V2) +#define BIT_CLEAR_XTAL_GMP_V2(x) ((x) & (~BITS_XTAL_GMP_V2)) +#define BIT_GET_XTAL_GMP_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2) +#define BIT_SET_XTAL_GMP_V2(x, v) \ + (BIT_CLEAR_XTAL_GMP_V2(x) | BIT_XTAL_GMP_V2(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_EN BIT(0) +#define BIT_XTAL_EN BIT(0) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ - -#define BIT_SHIFT_LOW_FREEPG_V1 0 -#define BIT_MASK_LOW_FREEPG_V1 0xfff -#define BIT_LOW_FREEPG_V1(x) (((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1) -#define BIT_GET_LOW_FREEPG_V1(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1) - +#define BIT_SHIFT_LOW_FREEPG_V1 0 +#define BIT_MASK_LOW_FREEPG_V1 0xfff +#define BIT_LOW_FREEPG_V1(x) \ + (((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1) +#define BITS_LOW_FREEPG_V1 (BIT_MASK_LOW_FREEPG_V1 << BIT_SHIFT_LOW_FREEPG_V1) +#define BIT_CLEAR_LOW_FREEPG_V1(x) ((x) & (~BITS_LOW_FREEPG_V1)) +#define BIT_GET_LOW_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1) +#define BIT_SET_LOW_FREEPG_V1(x, v) \ + (BIT_CLEAR_LOW_FREEPG_V1(x) | BIT_LOW_FREEPG_V1(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_SHIFT_REG_C3_V4 30 +#define BIT_MASK_REG_C3_V4 0x3 +#define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4) +#define BITS_REG_C3_V4 (BIT_MASK_REG_C3_V4 << BIT_SHIFT_REG_C3_V4) +#define BIT_CLEAR_REG_C3_V4(x) ((x) & (~BITS_REG_C3_V4)) +#define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4) +#define BIT_SET_REG_C3_V4(x, v) (BIT_CLEAR_REG_C3_V4(x) | BIT_REG_C3_V4(v)) -#define BIT_SHIFT_REG_C3_V4 30 -#define BIT_MASK_REG_C3_V4 0x3 -#define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4) -#define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4) - -#define BIT_REG_CP_BIT1 BIT(29) +#define BIT_REG_CP_BIT1 BIT(29) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_XTAL_GMN 28 -#define BIT_MASK_XTAL_GMN 0xf -#define BIT_XTAL_GMN(x) (((x) & BIT_MASK_XTAL_GMN) << BIT_SHIFT_XTAL_GMN) -#define BIT_GET_XTAL_GMN(x) (((x) >> BIT_SHIFT_XTAL_GMN) & BIT_MASK_XTAL_GMN) - +#define BIT_SHIFT_XTAL_GMN 28 +#define BIT_MASK_XTAL_GMN 0xf +#define BIT_XTAL_GMN(x) (((x) & BIT_MASK_XTAL_GMN) << BIT_SHIFT_XTAL_GMN) +#define BITS_XTAL_GMN (BIT_MASK_XTAL_GMN << BIT_SHIFT_XTAL_GMN) +#define BIT_CLEAR_XTAL_GMN(x) ((x) & (~BITS_XTAL_GMN)) +#define BIT_GET_XTAL_GMN(x) (((x) >> BIT_SHIFT_XTAL_GMN) & BIT_MASK_XTAL_GMN) +#define BIT_SET_XTAL_GMN(x, v) (BIT_CLEAR_XTAL_GMN(x) | BIT_XTAL_GMN(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_SHIFT_IOOFFSET_3_TO_0 28 +#define BIT_MASK_IOOFFSET_3_TO_0 0xf +#define BIT_IOOFFSET_3_TO_0(x) \ + (((x) & BIT_MASK_IOOFFSET_3_TO_0) << BIT_SHIFT_IOOFFSET_3_TO_0) +#define BITS_IOOFFSET_3_TO_0 \ + (BIT_MASK_IOOFFSET_3_TO_0 << BIT_SHIFT_IOOFFSET_3_TO_0) +#define BIT_CLEAR_IOOFFSET_3_TO_0(x) ((x) & (~BITS_IOOFFSET_3_TO_0)) +#define BIT_GET_IOOFFSET_3_TO_0(x) \ + (((x) >> BIT_SHIFT_IOOFFSET_3_TO_0) & BIT_MASK_IOOFFSET_3_TO_0) +#define BIT_SET_IOOFFSET_3_TO_0(x, v) \ + (BIT_CLEAR_IOOFFSET_3_TO_0(x) | BIT_IOOFFSET_3_TO_0(v)) -#define BIT_SHIFT_IOOFFSET_3_TO_0 28 -#define BIT_MASK_IOOFFSET_3_TO_0 0xf -#define BIT_IOOFFSET_3_TO_0(x) (((x) & BIT_MASK_IOOFFSET_3_TO_0) << BIT_SHIFT_IOOFFSET_3_TO_0) -#define BIT_GET_IOOFFSET_3_TO_0(x) (((x) >> BIT_SHIFT_IOOFFSET_3_TO_0) & BIT_MASK_IOOFFSET_3_TO_0) - -#define BIT_REG_FREF_SEL_BIT3_V1 BIT(27) +#define BIT_REG_FREF_SEL_BIT3_V1 BIT(27) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_REG_VO_AD 26 -#define BIT_MASK_REG_VO_AD 0x3 -#define BIT_REG_VO_AD(x) (((x) & BIT_MASK_REG_VO_AD) << BIT_SHIFT_REG_VO_AD) -#define BIT_GET_REG_VO_AD(x) (((x) >> BIT_SHIFT_REG_VO_AD) & BIT_MASK_REG_VO_AD) - +#define BIT_SHIFT_REG_VO_AD 26 +#define BIT_MASK_REG_VO_AD 0x3 +#define BIT_REG_VO_AD(x) (((x) & BIT_MASK_REG_VO_AD) << BIT_SHIFT_REG_VO_AD) +#define BITS_REG_VO_AD (BIT_MASK_REG_VO_AD << BIT_SHIFT_REG_VO_AD) +#define BIT_CLEAR_REG_VO_AD(x) ((x) & (~BITS_REG_VO_AD)) +#define BIT_GET_REG_VO_AD(x) (((x) >> BIT_SHIFT_REG_VO_AD) & BIT_MASK_REG_VO_AD) +#define BIT_SET_REG_VO_AD(x, v) (BIT_CLEAR_REG_VO_AD(x) | BIT_REG_VO_AD(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_RS_SET_V2 26 -#define BIT_MASK_RS_SET_V2 0x7 -#define BIT_RS_SET_V2(x) (((x) & BIT_MASK_RS_SET_V2) << BIT_SHIFT_RS_SET_V2) -#define BIT_GET_RS_SET_V2(x) (((x) >> BIT_SHIFT_RS_SET_V2) & BIT_MASK_RS_SET_V2) - +#define BIT_SHIFT_RS_SET_V2 26 +#define BIT_MASK_RS_SET_V2 0x7 +#define BIT_RS_SET_V2(x) (((x) & BIT_MASK_RS_SET_V2) << BIT_SHIFT_RS_SET_V2) +#define BITS_RS_SET_V2 (BIT_MASK_RS_SET_V2 << BIT_SHIFT_RS_SET_V2) +#define BIT_CLEAR_RS_SET_V2(x) ((x) & (~BITS_RS_SET_V2)) +#define BIT_GET_RS_SET_V2(x) (((x) >> BIT_SHIFT_RS_SET_V2) & BIT_MASK_RS_SET_V2) +#define BIT_SET_RS_SET_V2(x, v) (BIT_CLEAR_RS_SET_V2(x) | BIT_RS_SET_V2(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_REG_RS_V4 26 -#define BIT_MASK_REG_RS_V4 0x7 -#define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4) -#define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4) - +#define BIT_SHIFT_REG_RS_V4 26 +#define BIT_MASK_REG_RS_V4 0x7 +#define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4) +#define BITS_REG_RS_V4 (BIT_MASK_REG_RS_V4 << BIT_SHIFT_REG_RS_V4) +#define BIT_CLEAR_REG_RS_V4(x) ((x) & (~BITS_REG_RS_V4)) +#define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4) +#define BIT_SET_REG_RS_V4(x, v) (BIT_CLEAR_REG_RS_V4(x) | BIT_REG_RS_V4(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_V12ADJ_V1 25 -#define BIT_MASK_V12ADJ_V1 0x3 -#define BIT_V12ADJ_V1(x) (((x) & BIT_MASK_V12ADJ_V1) << BIT_SHIFT_V12ADJ_V1) -#define BIT_GET_V12ADJ_V1(x) (((x) >> BIT_SHIFT_V12ADJ_V1) & BIT_MASK_V12ADJ_V1) - +#define BIT_SHIFT_V12ADJ_V1 25 +#define BIT_MASK_V12ADJ_V1 0x3 +#define BIT_V12ADJ_V1(x) (((x) & BIT_MASK_V12ADJ_V1) << BIT_SHIFT_V12ADJ_V1) +#define BITS_V12ADJ_V1 (BIT_MASK_V12ADJ_V1 << BIT_SHIFT_V12ADJ_V1) +#define BIT_CLEAR_V12ADJ_V1(x) ((x) & (~BITS_V12ADJ_V1)) +#define BIT_GET_V12ADJ_V1(x) (((x) >> BIT_SHIFT_V12ADJ_V1) & BIT_MASK_V12ADJ_V1) +#define BIT_SET_V12ADJ_V1(x, v) (BIT_CLEAR_V12ADJ_V1(x) | BIT_V12ADJ_V1(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ - -#define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24 -#define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff -#define BIT_NOAC_OQT_FREEPG_V1(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1) -#define BIT_GET_NOAC_OQT_FREEPG_V1(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1) - +#define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24 +#define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff +#define BIT_NOAC_OQT_FREEPG_V1(x) \ + (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1) +#define BITS_NOAC_OQT_FREEPG_V1 \ + (BIT_MASK_NOAC_OQT_FREEPG_V1 << BIT_SHIFT_NOAC_OQT_FREEPG_V1) +#define BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) ((x) & (~BITS_NOAC_OQT_FREEPG_V1)) +#define BIT_GET_NOAC_OQT_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1) +#define BIT_SET_NOAC_OQT_FREEPG_V1(x, v) \ + (BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) | BIT_NOAC_OQT_FREEPG_V1(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_PS_EN BIT(24) +#define BIT_PS_EN BIT(24) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_REG__CS 24 -#define BIT_MASK_REG__CS 0x3 -#define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS) -#define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS) - +#define BIT_SHIFT_REG__CS 24 +#define BIT_MASK_REG__CS 0x3 +#define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS) +#define BITS_REG__CS (BIT_MASK_REG__CS << BIT_SHIFT_REG__CS) +#define BIT_CLEAR_REG__CS(x) ((x) & (~BITS_REG__CS)) +#define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS) +#define BIT_SET_REG__CS(x, v) (BIT_CLEAR_REG__CS(x) | BIT_REG__CS(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_EN_CK320M_V1 BIT(23) -#define BIT_AGPIO BIT(22) -#define BIT_REG_EDGE_SEL_V1 BIT(21) +#define BIT_EN_CK320M_V1 BIT(23) +#define BIT_AGPIO BIT(22) +#define BIT_REG_EDGE_SEL_V1 BIT(21) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_REG_CP_OFFSET 21 -#define BIT_MASK_REG_CP_OFFSET 0x7 -#define BIT_REG_CP_OFFSET(x) (((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET) -#define BIT_GET_REG_CP_OFFSET(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET) - +#define BIT_SHIFT_REG_CP_OFFSET 21 +#define BIT_MASK_REG_CP_OFFSET 0x7 +#define BIT_REG_CP_OFFSET(x) \ + (((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET) +#define BITS_REG_CP_OFFSET (BIT_MASK_REG_CP_OFFSET << BIT_SHIFT_REG_CP_OFFSET) +#define BIT_CLEAR_REG_CP_OFFSET(x) ((x) & (~BITS_REG_CP_OFFSET)) +#define BIT_GET_REG_CP_OFFSET(x) \ + (((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET) +#define BIT_SET_REG_CP_OFFSET(x, v) \ + (BIT_CLEAR_REG_CP_OFFSET(x) | BIT_REG_CP_OFFSET(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_VCO_BIAS_0 BIT(20) +#define BIT_REG_VCO_BIAS_0 BIT(20) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_CP_BIAS_V2 18 -#define BIT_MASK_CP_BIAS_V2 0x7 -#define BIT_CP_BIAS_V2(x) (((x) & BIT_MASK_CP_BIAS_V2) << BIT_SHIFT_CP_BIAS_V2) -#define BIT_GET_CP_BIAS_V2(x) (((x) >> BIT_SHIFT_CP_BIAS_V2) & BIT_MASK_CP_BIAS_V2) - +#define BIT_SHIFT_CP_BIAS_V2 18 +#define BIT_MASK_CP_BIAS_V2 0x7 +#define BIT_CP_BIAS_V2(x) (((x) & BIT_MASK_CP_BIAS_V2) << BIT_SHIFT_CP_BIAS_V2) +#define BITS_CP_BIAS_V2 (BIT_MASK_CP_BIAS_V2 << BIT_SHIFT_CP_BIAS_V2) +#define BIT_CLEAR_CP_BIAS_V2(x) ((x) & (~BITS_CP_BIAS_V2)) +#define BIT_GET_CP_BIAS_V2(x) \ + (((x) >> BIT_SHIFT_CP_BIAS_V2) & BIT_MASK_CP_BIAS_V2) +#define BIT_SET_CP_BIAS_V2(x, v) (BIT_CLEAR_CP_BIAS_V2(x) | BIT_CP_BIAS_V2(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_CP_BIAS 18 -#define BIT_MASK_CP_BIAS 0x7 -#define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS) -#define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS) - +#define BIT_SHIFT_CP_BIAS 18 +#define BIT_MASK_CP_BIAS 0x7 +#define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS) +#define BITS_CP_BIAS (BIT_MASK_CP_BIAS << BIT_SHIFT_CP_BIAS) +#define BIT_CLEAR_CP_BIAS(x) ((x) & (~BITS_CP_BIAS)) +#define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS) +#define BIT_SET_CP_BIAS(x, v) (BIT_CLEAR_CP_BIAS(x) | BIT_CP_BIAS(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1 17 -#define BIT_MASK_REG_PLLBIAS_2_TO_0_V1 0x7 -#define BIT_REG_PLLBIAS_2_TO_0_V1(x) (((x) & BIT_MASK_REG_PLLBIAS_2_TO_0_V1) << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) -#define BIT_GET_REG_PLLBIAS_2_TO_0_V1(x) (((x) >> BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) & BIT_MASK_REG_PLLBIAS_2_TO_0_V1) - +#define BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1 17 +#define BIT_MASK_REG_PLLBIAS_2_TO_0_V1 0x7 +#define BIT_REG_PLLBIAS_2_TO_0_V1(x) \ + (((x) & BIT_MASK_REG_PLLBIAS_2_TO_0_V1) \ + << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) +#define BITS_REG_PLLBIAS_2_TO_0_V1 \ + (BIT_MASK_REG_PLLBIAS_2_TO_0_V1 << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) +#define BIT_CLEAR_REG_PLLBIAS_2_TO_0_V1(x) ((x) & (~BITS_REG_PLLBIAS_2_TO_0_V1)) +#define BIT_GET_REG_PLLBIAS_2_TO_0_V1(x) \ + (((x) >> BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) & \ + BIT_MASK_REG_PLLBIAS_2_TO_0_V1) +#define BIT_SET_REG_PLLBIAS_2_TO_0_V1(x, v) \ + (BIT_CLEAR_REG_PLLBIAS_2_TO_0_V1(x) | BIT_REG_PLLBIAS_2_TO_0_V1(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_IDOUBLE_V2 BIT(17) +#define BIT_REG_IDOUBLE_V2 BIT(17) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_FREF_SEL BIT(16) +#define BIT_FREF_SEL BIT(16) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_IDOUBLE_V1 BIT(16) - -#define BIT_SHIFT_AC_OQT__FREEPG_V1 16 -#define BIT_MASK_AC_OQT__FREEPG_V1 0xff -#define BIT_AC_OQT__FREEPG_V1(x) (((x) & BIT_MASK_AC_OQT__FREEPG_V1) << BIT_SHIFT_AC_OQT__FREEPG_V1) -#define BIT_GET_AC_OQT__FREEPG_V1(x) (((x) >> BIT_SHIFT_AC_OQT__FREEPG_V1) & BIT_MASK_AC_OQT__FREEPG_V1) +#define BIT_REG_IDOUBLE_V1 BIT(16) +#define BIT_SHIFT_AC_OQT__FREEPG_V1 16 +#define BIT_MASK_AC_OQT__FREEPG_V1 0xff +#define BIT_AC_OQT__FREEPG_V1(x) \ + (((x) & BIT_MASK_AC_OQT__FREEPG_V1) << BIT_SHIFT_AC_OQT__FREEPG_V1) +#define BITS_AC_OQT__FREEPG_V1 \ + (BIT_MASK_AC_OQT__FREEPG_V1 << BIT_SHIFT_AC_OQT__FREEPG_V1) +#define BIT_CLEAR_AC_OQT__FREEPG_V1(x) ((x) & (~BITS_AC_OQT__FREEPG_V1)) +#define BIT_GET_AC_OQT__FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_AC_OQT__FREEPG_V1) & BIT_MASK_AC_OQT__FREEPG_V1) +#define BIT_SET_AC_OQT__FREEPG_V1(x, v) \ + (BIT_CLEAR_AC_OQT__FREEPG_V1(x) | BIT_AC_OQT__FREEPG_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ +#define BIT_SHIFT_AC_OQT_FREEPG_V1 16 +#define BIT_MASK_AC_OQT_FREEPG_V1 0xff +#define BIT_AC_OQT_FREEPG_V1(x) \ + (((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1) +#define BITS_AC_OQT_FREEPG_V1 \ + (BIT_MASK_AC_OQT_FREEPG_V1 << BIT_SHIFT_AC_OQT_FREEPG_V1) +#define BIT_CLEAR_AC_OQT_FREEPG_V1(x) ((x) & (~BITS_AC_OQT_FREEPG_V1)) +#define BIT_GET_AC_OQT_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1) +#define BIT_SET_AC_OQT_FREEPG_V1(x, v) \ + (BIT_CLEAR_AC_OQT_FREEPG_V1(x) | BIT_AC_OQT_FREEPG_V1(v)) -/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#endif -#define BIT_EN_SYN BIT(16) +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_AC_OQT_FREEPG_V1 16 -#define BIT_MASK_AC_OQT_FREEPG_V1 0xff -#define BIT_AC_OQT_FREEPG_V1(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1) -#define BIT_GET_AC_OQT_FREEPG_V1(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1) +/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_EN_SYN BIT(16) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_KVCO_V1 BIT(15) +#define BIT_REG_KVCO_V1 BIT(15) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_APLL_320_GATEB BIT(14) +#define BIT_APLL_320_GATEB BIT(14) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_MCCO_V2 14 -#define BIT_MASK_MCCO_V2 0x3 -#define BIT_MCCO_V2(x) (((x) & BIT_MASK_MCCO_V2) << BIT_SHIFT_MCCO_V2) -#define BIT_GET_MCCO_V2(x) (((x) >> BIT_SHIFT_MCCO_V2) & BIT_MASK_MCCO_V2) - +#define BIT_SHIFT_MCCO_V2 14 +#define BIT_MASK_MCCO_V2 0x3 +#define BIT_MCCO_V2(x) (((x) & BIT_MASK_MCCO_V2) << BIT_SHIFT_MCCO_V2) +#define BITS_MCCO_V2 (BIT_MASK_MCCO_V2 << BIT_SHIFT_MCCO_V2) +#define BIT_CLEAR_MCCO_V2(x) ((x) & (~BITS_MCCO_V2)) +#define BIT_GET_MCCO_V2(x) (((x) >> BIT_SHIFT_MCCO_V2) & BIT_MASK_MCCO_V2) +#define BIT_SET_MCCO_V2(x, v) (BIT_CLEAR_MCCO_V2(x) | BIT_MCCO_V2(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_VCO_BIAS_1_V1 BIT(14) +#define BIT_REG_VCO_BIAS_1_V1 BIT(14) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_MCCO 14 -#define BIT_MASK_MCCO 0x3 -#define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO) -#define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO) - +#define BIT_SHIFT_MCCO 14 +#define BIT_MASK_MCCO 0x3 +#define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO) +#define BITS_MCCO (BIT_MASK_MCCO << BIT_SHIFT_MCCO) +#define BIT_CLEAR_MCCO(x) ((x) & (~BITS_MCCO)) +#define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO) +#define BIT_SET_MCCO(x, v) (BIT_CLEAR_MCCO(x) | BIT_MCCO(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_DOGB_V1 BIT(13) +#define BIT_REG_DOGB_V1 BIT(13) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_CK320_EN 12 -#define BIT_MASK_CK320_EN 0x3 -#define BIT_CK320_EN(x) (((x) & BIT_MASK_CK320_EN) << BIT_SHIFT_CK320_EN) -#define BIT_GET_CK320_EN(x) (((x) >> BIT_SHIFT_CK320_EN) & BIT_MASK_CK320_EN) - +#define BIT_SHIFT_CK320_EN 12 +#define BIT_MASK_CK320_EN 0x3 +#define BIT_CK320_EN(x) (((x) & BIT_MASK_CK320_EN) << BIT_SHIFT_CK320_EN) +#define BITS_CK320_EN (BIT_MASK_CK320_EN << BIT_SHIFT_CK320_EN) +#define BIT_CLEAR_CK320_EN(x) ((x) & (~BITS_CK320_EN)) +#define BIT_GET_CK320_EN(x) (((x) >> BIT_SHIFT_CK320_EN) & BIT_MASK_CK320_EN) +#define BIT_SET_CK320_EN(x, v) (BIT_CLEAR_CK320_EN(x) | BIT_CK320_EN(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_SHIFT_REG_LDO_SEL 12 +#define BIT_MASK_REG_LDO_SEL 0x3 +#define BIT_REG_LDO_SEL(x) \ + (((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL) +#define BITS_REG_LDO_SEL (BIT_MASK_REG_LDO_SEL << BIT_SHIFT_REG_LDO_SEL) +#define BIT_CLEAR_REG_LDO_SEL(x) ((x) & (~BITS_REG_LDO_SEL)) +#define BIT_GET_REG_LDO_SEL(x) \ + (((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL) +#define BIT_SET_REG_LDO_SEL(x, v) \ + (BIT_CLEAR_REG_LDO_SEL(x) | BIT_REG_LDO_SEL(v)) -#define BIT_SHIFT_REG_LDO_SEL 12 -#define BIT_MASK_REG_LDO_SEL 0x3 -#define BIT_REG_LDO_SEL(x) (((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL) -#define BIT_GET_REG_LDO_SEL(x) (((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL) - -#define BIT_REG_KVCO_V2 BIT(10) +#define BIT_REG_KVCO_V2 BIT(10) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_AGPIO_GPO BIT(9) +#define BIT_AGPIO_GPO BIT(9) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_SHIFT_APLL_BIAS 8 +#define BIT_MASK_APLL_BIAS 0x7 +#define BIT_APLL_BIAS(x) (((x) & BIT_MASK_APLL_BIAS) << BIT_SHIFT_APLL_BIAS) +#define BITS_APLL_BIAS (BIT_MASK_APLL_BIAS << BIT_SHIFT_APLL_BIAS) +#define BIT_CLEAR_APLL_BIAS(x) ((x) & (~BITS_APLL_BIAS)) +#define BIT_GET_APLL_BIAS(x) (((x) >> BIT_SHIFT_APLL_BIAS) & BIT_MASK_APLL_BIAS) +#define BIT_SET_APLL_BIAS(x, v) (BIT_CLEAR_APLL_BIAS(x) | BIT_APLL_BIAS(v)) -#define BIT_SHIFT_APLL_BIAS 8 -#define BIT_MASK_APLL_BIAS 0x7 -#define BIT_APLL_BIAS(x) (((x) & BIT_MASK_APLL_BIAS) << BIT_SHIFT_APLL_BIAS) -#define BIT_GET_APLL_BIAS(x) (((x) >> BIT_SHIFT_APLL_BIAS) & BIT_MASK_APLL_BIAS) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_SHIFT_AGPIO_DRV 7 +#define BIT_MASK_AGPIO_DRV 0x3 +#define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV) +#define BITS_AGPIO_DRV (BIT_MASK_AGPIO_DRV << BIT_SHIFT_AGPIO_DRV) +#define BIT_CLEAR_AGPIO_DRV(x) ((x) & (~BITS_AGPIO_DRV)) +#define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV) +#define BIT_SET_AGPIO_DRV(x, v) (BIT_CLEAR_AGPIO_DRV(x) | BIT_AGPIO_DRV(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_AGPIO_DRV 7 -#define BIT_MASK_AGPIO_DRV 0x3 -#define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV) -#define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV) - +#define BIT_SHIFT_REG_V15_3_TO_0_V1 7 +#define BIT_MASK_REG_V15_3_TO_0_V1 0xf +#define BIT_REG_V15_3_TO_0_V1(x) \ + (((x) & BIT_MASK_REG_V15_3_TO_0_V1) << BIT_SHIFT_REG_V15_3_TO_0_V1) +#define BITS_REG_V15_3_TO_0_V1 \ + (BIT_MASK_REG_V15_3_TO_0_V1 << BIT_SHIFT_REG_V15_3_TO_0_V1) +#define BIT_CLEAR_REG_V15_3_TO_0_V1(x) ((x) & (~BITS_REG_V15_3_TO_0_V1)) +#define BIT_GET_REG_V15_3_TO_0_V1(x) \ + (((x) >> BIT_SHIFT_REG_V15_3_TO_0_V1) & BIT_MASK_REG_V15_3_TO_0_V1) +#define BIT_SET_REG_V15_3_TO_0_V1(x, v) \ + (BIT_CLEAR_REG_V15_3_TO_0_V1(x) | BIT_REG_V15_3_TO_0_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_APLL_KVCO BIT(6) -/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_REG_V15_3_TO_0_V1 7 -#define BIT_MASK_REG_V15_3_TO_0_V1 0xf -#define BIT_REG_V15_3_TO_0_V1(x) (((x) & BIT_MASK_REG_V15_3_TO_0_V1) << BIT_SHIFT_REG_V15_3_TO_0_V1) -#define BIT_GET_REG_V15_3_TO_0_V1(x) (((x) >> BIT_SHIFT_REG_V15_3_TO_0_V1) & BIT_MASK_REG_V15_3_TO_0_V1) +/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_REG_SEL_LDO_PC BIT(6) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_APLL_KVCO BIT(6) +#define BIT_APLL_WDOGB BIT(4) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_SEL_LDO_PC BIT(6) +#define BIT_SHIFT_REG_CC_1_TO_0_V1 4 +#define BIT_MASK_REG_CC_1_TO_0_V1 0x3 +#define BIT_REG_CC_1_TO_0_V1(x) \ + (((x) & BIT_MASK_REG_CC_1_TO_0_V1) << BIT_SHIFT_REG_CC_1_TO_0_V1) +#define BITS_REG_CC_1_TO_0_V1 \ + (BIT_MASK_REG_CC_1_TO_0_V1 << BIT_SHIFT_REG_CC_1_TO_0_V1) +#define BIT_CLEAR_REG_CC_1_TO_0_V1(x) ((x) & (~BITS_REG_CC_1_TO_0_V1)) +#define BIT_GET_REG_CC_1_TO_0_V1(x) \ + (((x) >> BIT_SHIFT_REG_CC_1_TO_0_V1) & BIT_MASK_REG_CC_1_TO_0_V1) +#define BIT_SET_REG_CC_1_TO_0_V1(x, v) \ + (BIT_CLEAR_REG_CC_1_TO_0_V1(x) | BIT_REG_CC_1_TO_0_V1(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_APLL_WDOGB BIT(4) +#define BIT_APLL_EDGE_SEL BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_REG_CC_1_TO_0_V1 4 -#define BIT_MASK_REG_CC_1_TO_0_V1 0x3 -#define BIT_REG_CC_1_TO_0_V1(x) (((x) & BIT_MASK_REG_CC_1_TO_0_V1) << BIT_SHIFT_REG_CC_1_TO_0_V1) -#define BIT_GET_REG_CC_1_TO_0_V1(x) (((x) >> BIT_SHIFT_REG_CC_1_TO_0_V1) & BIT_MASK_REG_CC_1_TO_0_V1) - +#define BIT_CKDELAY_USB_V1 BIT(3) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_APLL_EDGE_SEL BIT(3) +#define BIT_APLL_FREF_SEL_BIT0 BIT(2) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_CKDELAY_USB_V1 BIT(3) +#define BIT_CKDELAY_DIG_V1 BIT(2) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ANAPARSW_POW_MAC (Offset 0x0028) */ +#define BIT_POW_LDO15 BIT(2) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_APLL_FREF_SEL_BIT0 BIT(2) +#define BIT_SHIFT_XTAL_CAP_XO 1 +#define BIT_MASK_XTAL_CAP_XO 0x3f +#define BIT_XTAL_CAP_XO(x) \ + (((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO) +#define BITS_XTAL_CAP_XO (BIT_MASK_XTAL_CAP_XO << BIT_SHIFT_XTAL_CAP_XO) +#define BIT_CLEAR_XTAL_CAP_XO(x) ((x) & (~BITS_XTAL_CAP_XO)) +#define BIT_GET_XTAL_CAP_XO(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO) +#define BIT_SET_XTAL_CAP_XO(x, v) \ + (BIT_CLEAR_XTAL_CAP_XO(x) | BIT_XTAL_CAP_XO(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_CKDELAY_DIG_V1 BIT(2) +#define BIT_MPLL_EN BIT(1) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_POW_MAC (Offset 0x0028) */ +#define BIT_POW_SW BIT(1) -/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_XTAL_CAP_XO 1 -#define BIT_MASK_XTAL_CAP_XO 0x3f -#define BIT_XTAL_CAP_XO(x) (((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO) -#define BIT_GET_XTAL_CAP_XO(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO) +/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_APLL_EN BIT(0) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_MPLL_EN BIT(1) +#define BIT_POW_PLL BIT(0) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_SHIFT_EXQ__FREEPG_V1 0 +#define BIT_MASK_EXQ__FREEPG_V1 0xfff +#define BIT_EXQ__FREEPG_V1(x) \ + (((x) & BIT_MASK_EXQ__FREEPG_V1) << BIT_SHIFT_EXQ__FREEPG_V1) +#define BITS_EXQ__FREEPG_V1 \ + (BIT_MASK_EXQ__FREEPG_V1 << BIT_SHIFT_EXQ__FREEPG_V1) +#define BIT_CLEAR_EXQ__FREEPG_V1(x) ((x) & (~BITS_EXQ__FREEPG_V1)) +#define BIT_GET_EXQ__FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_EXQ__FREEPG_V1) & BIT_MASK_EXQ__FREEPG_V1) +#define BIT_SET_EXQ__FREEPG_V1(x, v) \ + (BIT_CLEAR_EXQ__FREEPG_V1(x) | BIT_EXQ__FREEPG_V1(v)) +#endif -/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_APLL_EN BIT(0) +/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ + +#define BIT_SHIFT_EXQ_FREEPG_V1 0 +#define BIT_MASK_EXQ_FREEPG_V1 0xfff +#define BIT_EXQ_FREEPG_V1(x) \ + (((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1) +#define BITS_EXQ_FREEPG_V1 (BIT_MASK_EXQ_FREEPG_V1 << BIT_SHIFT_EXQ_FREEPG_V1) +#define BIT_CLEAR_EXQ_FREEPG_V1(x) ((x) & (~BITS_EXQ_FREEPG_V1)) +#define BIT_GET_EXQ_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1) +#define BIT_SET_EXQ_FREEPG_V1(x, v) \ + (BIT_CLEAR_EXQ_FREEPG_V1(x) | BIT_EXQ_FREEPG_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_POW_MAC (Offset 0x0028) */ +#define BIT_POW_LDO14 BIT(0) -/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +/* 2 REG_ANAPARLDO_POW_MAC (Offset 0x0029) */ -#define BIT_POW_PLL BIT(0) +#define BIT_LDOE25_POW_L BIT(0) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_ANAPAR_POW_MAC (Offset 0x002A) */ +#define BIT_REG_STANDBY_L BIT(19) +#define BIT_PD_REGU_L BIT(18) +#define BIT_EN_PC_BT_L BIT(17) -/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ +#define BIT_SHIFT_REG_LDOADJ_L 13 +#define BIT_MASK_REG_LDOADJ_L 0xf +#define BIT_REG_LDOADJ_L(x) \ + (((x) & BIT_MASK_REG_LDOADJ_L) << BIT_SHIFT_REG_LDOADJ_L) +#define BITS_REG_LDOADJ_L (BIT_MASK_REG_LDOADJ_L << BIT_SHIFT_REG_LDOADJ_L) +#define BIT_CLEAR_REG_LDOADJ_L(x) ((x) & (~BITS_REG_LDOADJ_L)) +#define BIT_GET_REG_LDOADJ_L(x) \ + (((x) >> BIT_SHIFT_REG_LDOADJ_L) & BIT_MASK_REG_LDOADJ_L) +#define BIT_SET_REG_LDOADJ_L(x, v) \ + (BIT_CLEAR_REG_LDOADJ_L(x) | BIT_REG_LDOADJ_L(v)) +#define BIT_CK12M_EN BIT(11) +#define BIT_CK12M_SEL BIT(10) +#define BIT_EN_25_L BIT(9) +#define BIT_EN_SLEEP BIT(8) +#define BIT_DUMMY_V4 BIT(7) +#define BIT_DUMMY_V3 BIT(6) +#define BIT_DUMMY_V2 BIT(5) +#define BIT_DUMMY_V1 BIT(4) -#define BIT_SHIFT_EXQ__FREEPG_V1 0 -#define BIT_MASK_EXQ__FREEPG_V1 0xfff -#define BIT_EXQ__FREEPG_V1(x) (((x) & BIT_MASK_EXQ__FREEPG_V1) << BIT_SHIFT_EXQ__FREEPG_V1) -#define BIT_GET_EXQ__FREEPG_V1(x) (((x) >> BIT_SHIFT_EXQ__FREEPG_V1) & BIT_MASK_EXQ__FREEPG_V1) +#define BIT_SHIFT_LDOH12_V12ADJ_L 4 +#define BIT_MASK_LDOH12_V12ADJ_L 0xf +#define BIT_LDOH12_V12ADJ_L(x) \ + (((x) & BIT_MASK_LDOH12_V12ADJ_L) << BIT_SHIFT_LDOH12_V12ADJ_L) +#define BITS_LDOH12_V12ADJ_L \ + (BIT_MASK_LDOH12_V12ADJ_L << BIT_SHIFT_LDOH12_V12ADJ_L) +#define BIT_CLEAR_LDOH12_V12ADJ_L(x) ((x) & (~BITS_LDOH12_V12ADJ_L)) +#define BIT_GET_LDOH12_V12ADJ_L(x) \ + (((x) >> BIT_SHIFT_LDOH12_V12ADJ_L) & BIT_MASK_LDOH12_V12ADJ_L) +#define BIT_SET_LDOH12_V12ADJ_L(x, v) \ + (BIT_CLEAR_LDOH12_V12ADJ_L(x) | BIT_LDOH12_V12ADJ_L(v)) +#define BIT_POW_PC_LDO_PORT1 BIT(3) +#define BIT_POW_PC_LDO_PORT0 BIT(2) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_POW_MAC (Offset 0x002A) */ +#define BIT_POW_PLL_V1 BIT(1) -/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_EXQ_FREEPG_V1 0 -#define BIT_MASK_EXQ_FREEPG_V1 0xfff -#define BIT_EXQ_FREEPG_V1(x) (((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1) -#define BIT_GET_EXQ_FREEPG_V1(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1) +/* 2 REG_ANAPAR_POW_MAC (Offset 0x002A) */ +#define BIT_POW_POWER_CUT_POW_LDO BIT(0) + +#define BIT_SHIFT_LDOE25_V12ADJ_L_V1 0 +#define BIT_MASK_LDOE25_V12ADJ_L_V1 0xf +#define BIT_LDOE25_V12ADJ_L_V1(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L_V1) << BIT_SHIFT_LDOE25_V12ADJ_L_V1) +#define BITS_LDOE25_V12ADJ_L_V1 \ + (BIT_MASK_LDOE25_V12ADJ_L_V1 << BIT_SHIFT_LDOE25_V12ADJ_L_V1) +#define BIT_CLEAR_LDOE25_V12ADJ_L_V1(x) ((x) & (~BITS_LDOE25_V12ADJ_L_V1)) +#define BIT_GET_LDOE25_V12ADJ_L_V1(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_V1) & BIT_MASK_LDOE25_V12ADJ_L_V1) +#define BIT_SET_LDOE25_V12ADJ_L_V1(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L_V1(x) | BIT_LDOE25_V12ADJ_L_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ANAPAR_POW_XTAL (Offset 0x002B) */ +#define BIT_PSTIMER_2 BIT(31) +#define BIT_PSTIMER_1 BIT(30) +#define BIT_PSTIMER_0 BIT(29) +#define BIT_TXDMA_START_INT BIT(23) +#define BIT_TXDMA_STOP_INT BIT(22) +#define BIT_HISR7_IND BIT(21) +#define BIT_HISR6_IND BIT(19) +#define BIT_HISR5_IND BIT(18) +#define BIT_HISR4_IND BIT(17) +#define BIT_HISR3_IND BIT(14) +#define BIT_HISR2_IND BIT(13) +#define BIT_POW_XTAL BIT(1) +#define BIT_POW_BG BIT(0) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_XTAL_RF2_DRV 30 -#define BIT_MASK_XTAL_RF2_DRV 0x3 -#define BIT_XTAL_RF2_DRV(x) (((x) & BIT_MASK_XTAL_RF2_DRV) << BIT_SHIFT_XTAL_RF2_DRV) -#define BIT_GET_XTAL_RF2_DRV(x) (((x) >> BIT_SHIFT_XTAL_RF2_DRV) & BIT_MASK_XTAL_RF2_DRV) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_XTAL_RF2_DRV 30 +#define BIT_MASK_XTAL_RF2_DRV 0x3 +#define BIT_XTAL_RF2_DRV(x) \ + (((x) & BIT_MASK_XTAL_RF2_DRV) << BIT_SHIFT_XTAL_RF2_DRV) +#define BITS_XTAL_RF2_DRV (BIT_MASK_XTAL_RF2_DRV << BIT_SHIFT_XTAL_RF2_DRV) +#define BIT_CLEAR_XTAL_RF2_DRV(x) ((x) & (~BITS_XTAL_RF2_DRV)) +#define BIT_GET_XTAL_RF2_DRV(x) \ + (((x) >> BIT_SHIFT_XTAL_RF2_DRV) & BIT_MASK_XTAL_RF2_DRV) +#define BIT_SET_XTAL_RF2_DRV(x, v) \ + (BIT_CLEAR_XTAL_RF2_DRV(x) | BIT_XTAL_RF2_DRV(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_REG_REF_SEL_V3 BIT(30) +#define BIT_REG_REF_SEL_V3 BIT(30) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_XTAL_GMN_BIT4 BIT(29) -#define BIT_XTAL_GMP_BIT4 BIT(28) +#define BIT_XTAL_GMN_BIT4 BIT(29) +#define BIT_XTAL_GMP_BIT4 BIT(28) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_XQSEL BIT(27) +#define BIT_XQSEL BIT(27) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_REG_FREF_SEL_2_TO_0 27 -#define BIT_MASK_REG_FREF_SEL_2_TO_0 0x7 -#define BIT_REG_FREF_SEL_2_TO_0(x) (((x) & BIT_MASK_REG_FREF_SEL_2_TO_0) << BIT_SHIFT_REG_FREF_SEL_2_TO_0) -#define BIT_GET_REG_FREF_SEL_2_TO_0(x) (((x) >> BIT_SHIFT_REG_FREF_SEL_2_TO_0) & BIT_MASK_REG_FREF_SEL_2_TO_0) - +#define BIT_SHIFT_REG_FREF_SEL_2_TO_0 27 +#define BIT_MASK_REG_FREF_SEL_2_TO_0 0x7 +#define BIT_REG_FREF_SEL_2_TO_0(x) \ + (((x) & BIT_MASK_REG_FREF_SEL_2_TO_0) << BIT_SHIFT_REG_FREF_SEL_2_TO_0) +#define BITS_REG_FREF_SEL_2_TO_0 \ + (BIT_MASK_REG_FREF_SEL_2_TO_0 << BIT_SHIFT_REG_FREF_SEL_2_TO_0) +#define BIT_CLEAR_REG_FREF_SEL_2_TO_0(x) ((x) & (~BITS_REG_FREF_SEL_2_TO_0)) +#define BIT_GET_REG_FREF_SEL_2_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_FREF_SEL_2_TO_0) & BIT_MASK_REG_FREF_SEL_2_TO_0) +#define BIT_SET_REG_FREF_SEL_2_TO_0(x, v) \ + (BIT_CLEAR_REG_FREF_SEL_2_TO_0(x) | BIT_REG_FREF_SEL_2_TO_0(v)) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_XQSEL_BIT0 BIT(27) +#define BIT_XQSEL_BIT0 BIT(27) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_APLL_DUMMY BIT(26) +#define BIT_APLL_DUMMY BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1 21 -#define BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 0x3f -#define BIT_XTAL_CADJ_XOUT_5_TO_0_V1(x) (((x) & BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1) << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) -#define BIT_GET_XTAL_CADJ_XOUT_5_TO_0_V1(x) (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) & BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1) - +#define BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1 21 +#define BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 0x3f +#define BIT_XTAL_CADJ_XOUT_5_TO_0_V1(x) \ + (((x) & BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1) \ + << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) +#define BITS_XTAL_CADJ_XOUT_5_TO_0_V1 \ + (BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 \ + << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) +#define BIT_CLEAR_XTAL_CADJ_XOUT_5_TO_0_V1(x) \ + ((x) & (~BITS_XTAL_CADJ_XOUT_5_TO_0_V1)) +#define BIT_GET_XTAL_CADJ_XOUT_5_TO_0_V1(x) \ + (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) & \ + BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1) +#define BIT_SET_XTAL_CADJ_XOUT_5_TO_0_V1(x, v) \ + (BIT_CLEAR_XTAL_CADJ_XOUT_5_TO_0_V1(x) | \ + BIT_XTAL_CADJ_XOUT_5_TO_0_V1(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_XTAL_CADJ_XOUT 18 -#define BIT_MASK_XTAL_CADJ_XOUT 0x3f -#define BIT_XTAL_CADJ_XOUT(x) (((x) & BIT_MASK_XTAL_CADJ_XOUT) << BIT_SHIFT_XTAL_CADJ_XOUT) -#define BIT_GET_XTAL_CADJ_XOUT(x) (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT) & BIT_MASK_XTAL_CADJ_XOUT) - +#define BIT_SHIFT_XTAL_CADJ_XOUT 18 +#define BIT_MASK_XTAL_CADJ_XOUT 0x3f +#define BIT_XTAL_CADJ_XOUT(x) \ + (((x) & BIT_MASK_XTAL_CADJ_XOUT) << BIT_SHIFT_XTAL_CADJ_XOUT) +#define BITS_XTAL_CADJ_XOUT \ + (BIT_MASK_XTAL_CADJ_XOUT << BIT_SHIFT_XTAL_CADJ_XOUT) +#define BIT_CLEAR_XTAL_CADJ_XOUT(x) ((x) & (~BITS_XTAL_CADJ_XOUT)) +#define BIT_GET_XTAL_CADJ_XOUT(x) \ + (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT) & BIT_MASK_XTAL_CADJ_XOUT) +#define BIT_SET_XTAL_CADJ_XOUT(x, v) \ + (BIT_CLEAR_XTAL_CADJ_XOUT(x) | BIT_XTAL_CADJ_XOUT(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_XTAL_CADJ_XIN_V2 15 -#define BIT_MASK_XTAL_CADJ_XIN_V2 0x3f -#define BIT_XTAL_CADJ_XIN_V2(x) (((x) & BIT_MASK_XTAL_CADJ_XIN_V2) << BIT_SHIFT_XTAL_CADJ_XIN_V2) -#define BIT_GET_XTAL_CADJ_XIN_V2(x) (((x) >> BIT_SHIFT_XTAL_CADJ_XIN_V2) & BIT_MASK_XTAL_CADJ_XIN_V2) - +#define BIT_SHIFT_XTAL_CADJ_XIN_V2 15 +#define BIT_MASK_XTAL_CADJ_XIN_V2 0x3f +#define BIT_XTAL_CADJ_XIN_V2(x) \ + (((x) & BIT_MASK_XTAL_CADJ_XIN_V2) << BIT_SHIFT_XTAL_CADJ_XIN_V2) +#define BITS_XTAL_CADJ_XIN_V2 \ + (BIT_MASK_XTAL_CADJ_XIN_V2 << BIT_SHIFT_XTAL_CADJ_XIN_V2) +#define BIT_CLEAR_XTAL_CADJ_XIN_V2(x) ((x) & (~BITS_XTAL_CADJ_XIN_V2)) +#define BIT_GET_XTAL_CADJ_XIN_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_CADJ_XIN_V2) & BIT_MASK_XTAL_CADJ_XIN_V2) +#define BIT_SET_XTAL_CADJ_XIN_V2(x, v) \ + (BIT_CLEAR_XTAL_CADJ_XIN_V2(x) | BIT_XTAL_CADJ_XIN_V2(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_XTAL_CADJ_XIN 12 -#define BIT_MASK_XTAL_CADJ_XIN 0x3f -#define BIT_XTAL_CADJ_XIN(x) (((x) & BIT_MASK_XTAL_CADJ_XIN) << BIT_SHIFT_XTAL_CADJ_XIN) -#define BIT_GET_XTAL_CADJ_XIN(x) (((x) >> BIT_SHIFT_XTAL_CADJ_XIN) & BIT_MASK_XTAL_CADJ_XIN) - +#define BIT_SHIFT_XTAL_CADJ_XIN 12 +#define BIT_MASK_XTAL_CADJ_XIN 0x3f +#define BIT_XTAL_CADJ_XIN(x) \ + (((x) & BIT_MASK_XTAL_CADJ_XIN) << BIT_SHIFT_XTAL_CADJ_XIN) +#define BITS_XTAL_CADJ_XIN (BIT_MASK_XTAL_CADJ_XIN << BIT_SHIFT_XTAL_CADJ_XIN) +#define BIT_CLEAR_XTAL_CADJ_XIN(x) ((x) & (~BITS_XTAL_CADJ_XIN)) +#define BIT_GET_XTAL_CADJ_XIN(x) \ + (((x) >> BIT_SHIFT_XTAL_CADJ_XIN) & BIT_MASK_XTAL_CADJ_XIN) +#define BIT_SET_XTAL_CADJ_XIN(x, v) \ + (BIT_CLEAR_XTAL_CADJ_XIN(x) | BIT_XTAL_CADJ_XIN(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_REG_RS_V3 12 -#define BIT_MASK_REG_RS_V3 0x7 -#define BIT_REG_RS_V3(x) (((x) & BIT_MASK_REG_RS_V3) << BIT_SHIFT_REG_RS_V3) -#define BIT_GET_REG_RS_V3(x) (((x) >> BIT_SHIFT_REG_RS_V3) & BIT_MASK_REG_RS_V3) - +#define BIT_SHIFT_REG_RS_V3 12 +#define BIT_MASK_REG_RS_V3 0x7 +#define BIT_REG_RS_V3(x) (((x) & BIT_MASK_REG_RS_V3) << BIT_SHIFT_REG_RS_V3) +#define BITS_REG_RS_V3 (BIT_MASK_REG_RS_V3 << BIT_SHIFT_REG_RS_V3) +#define BIT_CLEAR_REG_RS_V3(x) ((x) & (~BITS_REG_RS_V3)) +#define BIT_GET_REG_RS_V3(x) (((x) >> BIT_SHIFT_REG_RS_V3) & BIT_MASK_REG_RS_V3) +#define BIT_SET_REG_RS_V3(x, v) (BIT_CLEAR_REG_RS_V3(x) | BIT_REG_RS_V3(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_BCNQ_EMPTY BIT(11) +#define BIT_SDIO_HQQ_EMPTY BIT(10) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_REG_RS 9 -#define BIT_MASK_REG_RS 0x7 -#define BIT_REG_RS(x) (((x) & BIT_MASK_REG_RS) << BIT_SHIFT_REG_RS) -#define BIT_GET_REG_RS(x) (((x) >> BIT_SHIFT_REG_RS) & BIT_MASK_REG_RS) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_REG_RS 9 +#define BIT_MASK_REG_RS 0x7 +#define BIT_REG_RS(x) (((x) & BIT_MASK_REG_RS) << BIT_SHIFT_REG_RS) +#define BITS_REG_RS (BIT_MASK_REG_RS << BIT_SHIFT_REG_RS) +#define BIT_CLEAR_REG_RS(x) ((x) & (~BITS_REG_RS)) +#define BIT_GET_REG_RS(x) (((x) >> BIT_SHIFT_REG_RS) & BIT_MASK_REG_RS) +#define BIT_SET_REG_RS(x, v) (BIT_CLEAR_REG_RS(x) | BIT_REG_RS(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_REG_R3_V3 9 -#define BIT_MASK_REG_R3_V3 0x7 -#define BIT_REG_R3_V3(x) (((x) & BIT_MASK_REG_R3_V3) << BIT_SHIFT_REG_R3_V3) -#define BIT_GET_REG_R3_V3(x) (((x) >> BIT_SHIFT_REG_R3_V3) & BIT_MASK_REG_R3_V3) - +#define BIT_SHIFT_REG_R3_V3 9 +#define BIT_MASK_REG_R3_V3 0x7 +#define BIT_REG_R3_V3(x) (((x) & BIT_MASK_REG_R3_V3) << BIT_SHIFT_REG_R3_V3) +#define BITS_REG_R3_V3 (BIT_MASK_REG_R3_V3 << BIT_SHIFT_REG_R3_V3) +#define BIT_CLEAR_REG_R3_V3(x) ((x) & (~BITS_REG_R3_V3)) +#define BIT_GET_REG_R3_V3(x) (((x) >> BIT_SHIFT_REG_R3_V3) & BIT_MASK_REG_R3_V3) +#define BIT_SET_REG_R3_V3(x, v) (BIT_CLEAR_REG_R3_V3(x) | BIT_REG_R3_V3(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_MQQ_EMPTY BIT(9) +#define BIT_SDIO_MGQ_CPU_EMPTY BIT(8) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_PS_V2 7 -#define BIT_MASK_PS_V2 0x7 -#define BIT_PS_V2(x) (((x) & BIT_MASK_PS_V2) << BIT_SHIFT_PS_V2) -#define BIT_GET_PS_V2(x) (((x) >> BIT_SHIFT_PS_V2) & BIT_MASK_PS_V2) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_PS_V2 7 +#define BIT_MASK_PS_V2 0x7 +#define BIT_PS_V2(x) (((x) & BIT_MASK_PS_V2) << BIT_SHIFT_PS_V2) +#define BITS_PS_V2 (BIT_MASK_PS_V2 << BIT_SHIFT_PS_V2) +#define BIT_CLEAR_PS_V2(x) ((x) & (~BITS_PS_V2)) +#define BIT_GET_PS_V2(x) (((x) >> BIT_SHIFT_PS_V2) & BIT_MASK_PS_V2) +#define BIT_SET_PS_V2(x, v) (BIT_CLEAR_PS_V2(x) | BIT_PS_V2(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_REG_CS_V3 7 -#define BIT_MASK_REG_CS_V3 0x3 -#define BIT_REG_CS_V3(x) (((x) & BIT_MASK_REG_CS_V3) << BIT_SHIFT_REG_CS_V3) -#define BIT_GET_REG_CS_V3(x) (((x) >> BIT_SHIFT_REG_CS_V3) & BIT_MASK_REG_CS_V3) - +#define BIT_SHIFT_REG_CS_V3 7 +#define BIT_MASK_REG_CS_V3 0x3 +#define BIT_REG_CS_V3(x) (((x) & BIT_MASK_REG_CS_V3) << BIT_SHIFT_REG_CS_V3) +#define BITS_REG_CS_V3 (BIT_MASK_REG_CS_V3 << BIT_SHIFT_REG_CS_V3) +#define BIT_CLEAR_REG_CS_V3(x) ((x) & (~BITS_REG_CS_V3)) +#define BIT_GET_REG_CS_V3(x) (((x) >> BIT_SHIFT_REG_CS_V3) & BIT_MASK_REG_CS_V3) +#define BIT_SET_REG_CS_V3(x, v) (BIT_CLEAR_REG_CS_V3(x) | BIT_REG_CS_V3(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_PS 7 +#define BIT_MASK_PS 0x7 +#define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS) +#define BITS_PS (BIT_MASK_PS << BIT_SHIFT_PS) +#define BIT_CLEAR_PS(x) ((x) & (~BITS_PS)) +#define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS) +#define BIT_SET_PS(x, v) (BIT_CLEAR_PS(x) | BIT_PS(v)) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PS 7 -#define BIT_MASK_PS 0x7 -#define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS) -#define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC7Q_EMPTY BIT(7) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_REG_R3 6 -#define BIT_MASK_REG_R3 0x7 -#define BIT_REG_R3(x) (((x) & BIT_MASK_REG_R3) << BIT_SHIFT_REG_R3) -#define BIT_GET_REG_R3(x) (((x) >> BIT_SHIFT_REG_R3) & BIT_MASK_REG_R3) - +#define BIT_SHIFT_REG_R3 6 +#define BIT_MASK_REG_R3 0x7 +#define BIT_REG_R3(x) (((x) & BIT_MASK_REG_R3) << BIT_SHIFT_REG_R3) +#define BITS_REG_R3 (BIT_MASK_REG_R3 << BIT_SHIFT_REG_R3) +#define BIT_CLEAR_REG_R3(x) ((x) & (~BITS_REG_R3)) +#define BIT_GET_REG_R3(x) (((x) >> BIT_SHIFT_REG_R3) & BIT_MASK_REG_R3) +#define BIT_SET_REG_R3(x, v) (BIT_CLEAR_REG_R3(x) | BIT_REG_R3(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_PSEN BIT(6) -#define BIT_DOGENB BIT(5) +#define BIT_PSEN BIT(6) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC6Q_EMPTY BIT(6) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_REG_CP_V3 5 -#define BIT_MASK_REG_CP_V3 0x3 -#define BIT_REG_CP_V3(x) (((x) & BIT_MASK_REG_CP_V3) << BIT_SHIFT_REG_CP_V3) -#define BIT_GET_REG_CP_V3(x) (((x) >> BIT_SHIFT_REG_CP_V3) & BIT_MASK_REG_CP_V3) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_DOGENB BIT(5) #endif +#if (HALMAC_8814A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_REG_CP_V3 5 +#define BIT_MASK_REG_CP_V3 0x3 +#define BIT_REG_CP_V3(x) (((x) & BIT_MASK_REG_CP_V3) << BIT_SHIFT_REG_CP_V3) +#define BITS_REG_CP_V3 (BIT_MASK_REG_CP_V3 << BIT_SHIFT_REG_CP_V3) +#define BIT_CLEAR_REG_CP_V3(x) ((x) & (~BITS_REG_CP_V3)) +#define BIT_GET_REG_CP_V3(x) (((x) >> BIT_SHIFT_REG_CP_V3) & BIT_MASK_REG_CP_V3) +#define BIT_SET_REG_CP_V3(x, v) (BIT_CLEAR_REG_CP_V3(x) | BIT_REG_CP_V3(v)) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_REG_CS 4 -#define BIT_MASK_REG_CS 0x3 -#define BIT_REG_CS(x) (((x) & BIT_MASK_REG_CS) << BIT_SHIFT_REG_CS) -#define BIT_GET_REG_CS(x) (((x) >> BIT_SHIFT_REG_CS) & BIT_MASK_REG_CS) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC5Q_EMPTY BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ + +#define BIT_SHIFT_REG_CS 4 +#define BIT_MASK_REG_CS 0x3 +#define BIT_REG_CS(x) (((x) & BIT_MASK_REG_CS) << BIT_SHIFT_REG_CS) +#define BITS_REG_CS (BIT_MASK_REG_CS << BIT_SHIFT_REG_CS) +#define BIT_CLEAR_REG_CS(x) ((x) & (~BITS_REG_CS)) +#define BIT_GET_REG_CS(x) (((x) >> BIT_SHIFT_REG_CS) & BIT_MASK_REG_CS) +#define BIT_SET_REG_CS(x, v) (BIT_CLEAR_REG_CS(x) | BIT_REG_CS(v)) +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_REG_MBIAS BIT(4) +#define BIT_REG_MBIAS BIT(4) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC4Q_EMPTY BIT(4) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8814A_SUPPORT) -#define BIT_SHIFT_REG_C3_V3 3 -#define BIT_MASK_REG_C3_V3 0x3 -#define BIT_REG_C3_V3(x) (((x) & BIT_MASK_REG_C3_V3) << BIT_SHIFT_REG_C3_V3) -#define BIT_GET_REG_C3_V3(x) (((x) >> BIT_SHIFT_REG_C3_V3) & BIT_MASK_REG_C3_V3) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_REG_C3_V3 3 +#define BIT_MASK_REG_C3_V3 0x3 +#define BIT_REG_C3_V3(x) (((x) & BIT_MASK_REG_C3_V3) << BIT_SHIFT_REG_C3_V3) +#define BITS_REG_C3_V3 (BIT_MASK_REG_C3_V3 << BIT_SHIFT_REG_C3_V3) +#define BIT_CLEAR_REG_C3_V3(x) ((x) & (~BITS_REG_C3_V3)) +#define BIT_GET_REG_C3_V3(x) (((x) >> BIT_SHIFT_REG_C3_V3) & BIT_MASK_REG_C3_V3) +#define BIT_SET_REG_C3_V3(x, v) (BIT_CLEAR_REG_C3_V3(x) | BIT_REG_C3_V3(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC3Q_EMPTY BIT(3) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_REG_CP 2 -#define BIT_MASK_REG_CP 0x3 -#define BIT_REG_CP(x) (((x) & BIT_MASK_REG_CP) << BIT_SHIFT_REG_CP) -#define BIT_GET_REG_CP(x) (((x) >> BIT_SHIFT_REG_CP) & BIT_MASK_REG_CP) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_REG_CP 2 +#define BIT_MASK_REG_CP 0x3 +#define BIT_REG_CP(x) (((x) & BIT_MASK_REG_CP) << BIT_SHIFT_REG_CP) +#define BITS_REG_CP (BIT_MASK_REG_CP << BIT_SHIFT_REG_CP) +#define BIT_CLEAR_REG_CP(x) ((x) & (~BITS_REG_CP)) +#define BIT_GET_REG_CP(x) (((x) >> BIT_SHIFT_REG_CP) & BIT_MASK_REG_CP) +#define BIT_SET_REG_CP(x, v) (BIT_CLEAR_REG_CP(x) | BIT_REG_CP(v)) #endif - #if (HALMAC_8814A_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_REG_320_SEL_V3 BIT(2) +#define BIT_REG_320_SEL_V3 BIT(2) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ + +#define BIT_SDIO_AC2Q_EMPTY BIT(2) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_EN_SYN_V1 BIT(1) +#define BIT_EN_SYN_V1 BIT(1) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_REG_R3_V4 1 +#define BIT_MASK_REG_R3_V4 0x7 +#define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4) +#define BITS_REG_R3_V4 (BIT_MASK_REG_R3_V4 << BIT_SHIFT_REG_R3_V4) +#define BIT_CLEAR_REG_R3_V4(x) ((x) & (~BITS_REG_R3_V4)) +#define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4) +#define BIT_SET_REG_R3_V4(x, v) (BIT_CLEAR_REG_R3_V4(x) | BIT_REG_R3_V4(v)) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_REG_R3_V4 1 -#define BIT_MASK_REG_R3_V4 0x7 -#define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4) -#define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC1Q_EMPTY BIT(1) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_REG_C3 0 -#define BIT_MASK_REG_C3 0x3 -#define BIT_REG_C3(x) (((x) & BIT_MASK_REG_C3) << BIT_SHIFT_REG_C3) -#define BIT_GET_REG_C3(x) (((x) >> BIT_SHIFT_REG_C3) & BIT_MASK_REG_C3) - +#define BIT_SHIFT_REG_C3 0 +#define BIT_MASK_REG_C3 0x3 +#define BIT_REG_C3(x) (((x) & BIT_MASK_REG_C3) << BIT_SHIFT_REG_C3) +#define BITS_REG_C3 (BIT_MASK_REG_C3 << BIT_SHIFT_REG_C3) +#define BIT_CLEAR_REG_C3(x) ((x) & (~BITS_REG_C3)) +#define BIT_GET_REG_C3(x) (((x) >> BIT_SHIFT_REG_C3) & BIT_MASK_REG_C3) +#define BIT_SET_REG_C3(x, v) (BIT_CLEAR_REG_C3(x) | BIT_REG_C3(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_IOOFFSET_BIT4 BIT(0) +#define BIT_IOOFFSET_BIT4 BIT(0) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_REG_CP_BIT0 BIT(0) +#define BIT_REG_CP_BIT0 BIT(0) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC0Q_EMPTY BIT(0) -/* 2 REG_EFUSE_CTRL (Offset 0x0030) */ - -#define BIT_EF_FLAG BIT(31) +#endif -#define BIT_SHIFT_EF_PGPD 28 -#define BIT_MASK_EF_PGPD 0x7 -#define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD) -#define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) +/* 2 REG_EFUSE_CTRL (Offset 0x0030) */ -#define BIT_SHIFT_EF_RDT 24 -#define BIT_MASK_EF_RDT 0xf -#define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT) -#define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT) +#define BIT_EF_FLAG BIT(31) +#define BIT_SHIFT_EF_PGPD 28 +#define BIT_MASK_EF_PGPD 0x7 +#define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD) +#define BITS_EF_PGPD (BIT_MASK_EF_PGPD << BIT_SHIFT_EF_PGPD) +#define BIT_CLEAR_EF_PGPD(x) ((x) & (~BITS_EF_PGPD)) +#define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD) +#define BIT_SET_EF_PGPD(x, v) (BIT_CLEAR_EF_PGPD(x) | BIT_EF_PGPD(v)) -#define BIT_SHIFT_EF_PGTS 20 -#define BIT_MASK_EF_PGTS 0xf -#define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS) -#define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS) +#define BIT_SHIFT_EF_RDT 24 +#define BIT_MASK_EF_RDT 0xf +#define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT) +#define BITS_EF_RDT (BIT_MASK_EF_RDT << BIT_SHIFT_EF_RDT) +#define BIT_CLEAR_EF_RDT(x) ((x) & (~BITS_EF_RDT)) +#define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT) +#define BIT_SET_EF_RDT(x, v) (BIT_CLEAR_EF_RDT(x) | BIT_EF_RDT(v)) +#define BIT_SHIFT_EF_PGTS 20 +#define BIT_MASK_EF_PGTS 0xf +#define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS) +#define BITS_EF_PGTS (BIT_MASK_EF_PGTS << BIT_SHIFT_EF_PGTS) +#define BIT_CLEAR_EF_PGTS(x) ((x) & (~BITS_EF_PGTS)) +#define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS) +#define BIT_SET_EF_PGTS(x, v) (BIT_CLEAR_EF_PGTS(x) | BIT_EF_PGTS(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ -#define BIT_EF_PDWN BIT(19) +#define BIT_EF_PDWN BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ -#define BIT_EF_ALDEN BIT(18) +#define BIT_EF_ALDEN BIT(18) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ - -#define BIT_SHIFT_HTSFR1 16 -#define BIT_MASK_HTSFR1 0xffff -#define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1) -#define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1) - +#define BIT_SHIFT_HTSFR1 16 +#define BIT_MASK_HTSFR1 0xffff +#define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1) +#define BITS_HTSFR1 (BIT_MASK_HTSFR1 << BIT_SHIFT_HTSFR1) +#define BIT_CLEAR_HTSFR1(x) ((x) & (~BITS_HTSFR1)) +#define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1) +#define BIT_SET_HTSFR1(x, v) (BIT_CLEAR_HTSFR1(x) | BIT_HTSFR1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ +#define BIT_SHIFT_EF_ADDR 8 +#define BIT_MASK_EF_ADDR 0x3ff +#define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) +#define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR) +#define BIT_CLEAR_EF_ADDR(x) ((x) & (~BITS_EF_ADDR)) +#define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR) +#define BIT_SET_EF_ADDR(x, v) (BIT_CLEAR_EF_ADDR(x) | BIT_EF_ADDR(v)) -#define BIT_SHIFT_EF_ADDR 8 -#define BIT_MASK_EF_ADDR 0x3ff -#define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) -#define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR) - - -#define BIT_SHIFT_EF_DATA 0 -#define BIT_MASK_EF_DATA 0xff -#define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA) -#define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA) - +#define BIT_SHIFT_EF_DATA 0 +#define BIT_MASK_EF_DATA 0xff +#define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA) +#define BITS_EF_DATA (BIT_MASK_EF_DATA << BIT_SHIFT_EF_DATA) +#define BIT_CLEAR_EF_DATA(x) ((x) & (~BITS_EF_DATA)) +#define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA) +#define BIT_SET_EF_DATA(x, v) (BIT_CLEAR_EF_DATA(x) | BIT_EF_DATA(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ - -#define BIT_SHIFT_HTSFR0 0 -#define BIT_MASK_HTSFR0 0xffff -#define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0) -#define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0) - +#define BIT_SHIFT_HTSFR0 0 +#define BIT_MASK_HTSFR0 0xffff +#define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0) +#define BITS_HTSFR0 (BIT_MASK_HTSFR0 << BIT_SHIFT_HTSFR0) +#define BIT_CLEAR_HTSFR0(x) ((x) & (~BITS_HTSFR0)) +#define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0) +#define BIT_SET_HTSFR0(x, v) (BIT_CLEAR_HTSFR0(x) | BIT_HTSFR0(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_LDOE25_EN BIT(31) +#define BIT_LDOE25_EN BIT(31) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ +#define BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2 28 +#define BIT_MASK_LDOE25_VADJ_BIT0_TO_2 0x7 +#define BIT_LDOE25_VADJ_BIT0_TO_2(x) \ + (((x) & BIT_MASK_LDOE25_VADJ_BIT0_TO_2) \ + << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) +#define BITS_LDOE25_VADJ_BIT0_TO_2 \ + (BIT_MASK_LDOE25_VADJ_BIT0_TO_2 << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) +#define BIT_CLEAR_LDOE25_VADJ_BIT0_TO_2(x) ((x) & (~BITS_LDOE25_VADJ_BIT0_TO_2)) +#define BIT_GET_LDOE25_VADJ_BIT0_TO_2(x) \ + (((x) >> BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) & \ + BIT_MASK_LDOE25_VADJ_BIT0_TO_2) +#define BIT_SET_LDOE25_VADJ_BIT0_TO_2(x, v) \ + (BIT_CLEAR_LDOE25_VADJ_BIT0_TO_2(x) | BIT_LDOE25_VADJ_BIT0_TO_2(v)) -#define BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2 28 -#define BIT_MASK_LDOE25_VADJ_BIT0_TO_2 0x7 -#define BIT_LDOE25_VADJ_BIT0_TO_2(x) (((x) & BIT_MASK_LDOE25_VADJ_BIT0_TO_2) << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) -#define BIT_GET_LDOE25_VADJ_BIT0_TO_2(x) (((x) >> BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) & BIT_MASK_LDOE25_VADJ_BIT0_TO_2) - -#define BIT_LDOE25_VADJ_BIT3 BIT(27) +#define BIT_LDOE25_VADJ_BIT3 BIT(27) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ - -#define BIT_SHIFT_LDOE25_V12ADJ_L 27 -#define BIT_MASK_LDOE25_V12ADJ_L 0xf -#define BIT_LDOE25_V12ADJ_L(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L) -#define BIT_GET_LDOE25_V12ADJ_L(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L) - +#define BIT_SHIFT_LDOE25_V12ADJ_L 27 +#define BIT_MASK_LDOE25_V12ADJ_L 0xf +#define BIT_LDOE25_V12ADJ_L(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L) +#define BITS_LDOE25_V12ADJ_L \ + (BIT_MASK_LDOE25_V12ADJ_L << BIT_SHIFT_LDOE25_V12ADJ_L) +#define BIT_CLEAR_LDOE25_V12ADJ_L(x) ((x) & (~BITS_LDOE25_V12ADJ_L)) +#define BIT_GET_LDOE25_V12ADJ_L(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L) +#define BIT_SET_LDOE25_V12ADJ_L(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L(x) | BIT_LDOE25_V12ADJ_L(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ - -#define BIT_SHIFT_LDOE25_VADJ_3_TO_0 27 -#define BIT_MASK_LDOE25_VADJ_3_TO_0 0xf -#define BIT_LDOE25_VADJ_3_TO_0(x) (((x) & BIT_MASK_LDOE25_VADJ_3_TO_0) << BIT_SHIFT_LDOE25_VADJ_3_TO_0) -#define BIT_GET_LDOE25_VADJ_3_TO_0(x) (((x) >> BIT_SHIFT_LDOE25_VADJ_3_TO_0) & BIT_MASK_LDOE25_VADJ_3_TO_0) - +#define BIT_SHIFT_LDOE25_VADJ_3_TO_0 27 +#define BIT_MASK_LDOE25_VADJ_3_TO_0 0xf +#define BIT_LDOE25_VADJ_3_TO_0(x) \ + (((x) & BIT_MASK_LDOE25_VADJ_3_TO_0) << BIT_SHIFT_LDOE25_VADJ_3_TO_0) +#define BITS_LDOE25_VADJ_3_TO_0 \ + (BIT_MASK_LDOE25_VADJ_3_TO_0 << BIT_SHIFT_LDOE25_VADJ_3_TO_0) +#define BIT_CLEAR_LDOE25_VADJ_3_TO_0(x) ((x) & (~BITS_LDOE25_VADJ_3_TO_0)) +#define BIT_GET_LDOE25_VADJ_3_TO_0(x) \ + (((x) >> BIT_SHIFT_LDOE25_VADJ_3_TO_0) & BIT_MASK_LDOE25_VADJ_3_TO_0) +#define BIT_SET_LDOE25_VADJ_3_TO_0(x, v) \ + (BIT_CLEAR_LDOE25_VADJ_3_TO_0(x) | BIT_LDOE25_VADJ_3_TO_0(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_EFCRES_SEL BIT(26) +#define BIT_EFCRES_SEL BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_EF_CSER BIT(26) +#define BIT_EF_CSER BIT(26) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_EF_CRES_SEL BIT(26) +#define BIT_EF_CRES_SEL BIT(26) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ - -#define BIT_SHIFT_EF_SCAN_START 16 -#define BIT_MASK_EF_SCAN_START 0x1ff -#define BIT_EF_SCAN_START(x) (((x) & BIT_MASK_EF_SCAN_START) << BIT_SHIFT_EF_SCAN_START) -#define BIT_GET_EF_SCAN_START(x) (((x) >> BIT_SHIFT_EF_SCAN_START) & BIT_MASK_EF_SCAN_START) - +#define BIT_SHIFT_EF_SCAN_START 16 +#define BIT_MASK_EF_SCAN_START 0x1ff +#define BIT_EF_SCAN_START(x) \ + (((x) & BIT_MASK_EF_SCAN_START) << BIT_SHIFT_EF_SCAN_START) +#define BITS_EF_SCAN_START (BIT_MASK_EF_SCAN_START << BIT_SHIFT_EF_SCAN_START) +#define BIT_CLEAR_EF_SCAN_START(x) ((x) & (~BITS_EF_SCAN_START)) +#define BIT_GET_EF_SCAN_START(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START) & BIT_MASK_EF_SCAN_START) +#define BIT_SET_EF_SCAN_START(x, v) \ + (BIT_CLEAR_EF_SCAN_START(x) | BIT_EF_SCAN_START(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ - -#define BIT_SHIFT_EF_SCAN_START_V1 16 -#define BIT_MASK_EF_SCAN_START_V1 0x3ff -#define BIT_EF_SCAN_START_V1(x) (((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1) -#define BIT_GET_EF_SCAN_START_V1(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1) - +#define BIT_SHIFT_EF_SCAN_START_V1 16 +#define BIT_MASK_EF_SCAN_START_V1 0x3ff +#define BIT_EF_SCAN_START_V1(x) \ + (((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1) +#define BITS_EF_SCAN_START_V1 \ + (BIT_MASK_EF_SCAN_START_V1 << BIT_SHIFT_EF_SCAN_START_V1) +#define BIT_CLEAR_EF_SCAN_START_V1(x) ((x) & (~BITS_EF_SCAN_START_V1)) +#define BIT_GET_EF_SCAN_START_V1(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1) +#define BIT_SET_EF_SCAN_START_V1(x, v) \ + (BIT_CLEAR_EF_SCAN_START_V1(x) | BIT_EF_SCAN_START_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ - -#define BIT_SHIFT_EF_SCAN_END 12 -#define BIT_MASK_EF_SCAN_END 0xf -#define BIT_EF_SCAN_END(x) (((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END) -#define BIT_GET_EF_SCAN_END(x) (((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END) - +#define BIT_SHIFT_EF_SCAN_END 12 +#define BIT_MASK_EF_SCAN_END 0xf +#define BIT_EF_SCAN_END(x) \ + (((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END) +#define BITS_EF_SCAN_END (BIT_MASK_EF_SCAN_END << BIT_SHIFT_EF_SCAN_END) +#define BIT_CLEAR_EF_SCAN_END(x) ((x) & (~BITS_EF_SCAN_END)) +#define BIT_GET_EF_SCAN_END(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END) +#define BIT_SET_EF_SCAN_END(x, v) \ + (BIT_CLEAR_EF_SCAN_END(x) | BIT_EF_SCAN_END(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_EF_FORCE_PGMEN BIT(11) +#define BIT_EF_FORCE_PGMEN BIT(11) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_SCAN_EN BIT(11) +#define BIT_SCAN_EN BIT(11) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_EF_PD_DIS BIT(11) +#define BIT_EF_PD_DIS BIT(11) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_SW_PG_EN BIT(10) +#define BIT_SW_PG_EN BIT(10) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ - -#define BIT_SHIFT_EF_CELL_SEL 8 -#define BIT_MASK_EF_CELL_SEL 0x3 -#define BIT_EF_CELL_SEL(x) (((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL) -#define BIT_GET_EF_CELL_SEL(x) (((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL) - +#define BIT_SHIFT_EF_CELL_SEL 8 +#define BIT_MASK_EF_CELL_SEL 0x3 +#define BIT_EF_CELL_SEL(x) \ + (((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL) +#define BITS_EF_CELL_SEL (BIT_MASK_EF_CELL_SEL << BIT_SHIFT_EF_CELL_SEL) +#define BIT_CLEAR_EF_CELL_SEL(x) ((x) & (~BITS_EF_CELL_SEL)) +#define BIT_GET_EF_CELL_SEL(x) \ + (((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL) +#define BIT_SET_EF_CELL_SEL(x, v) \ + (BIT_CLEAR_EF_CELL_SEL(x) | BIT_EF_CELL_SEL(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_EF_TRPT BIT(7) - -#define BIT_SHIFT_EF_TTHD 0 -#define BIT_MASK_EF_TTHD 0x7f -#define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD) -#define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD) +#define BIT_EF_TRPT BIT(7) +#define BIT_SHIFT_EF_TTHD 0 +#define BIT_MASK_EF_TTHD 0x7f +#define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD) +#define BITS_EF_TTHD (BIT_MASK_EF_TTHD << BIT_SHIFT_EF_TTHD) +#define BIT_CLEAR_EF_TTHD(x) ((x) & (~BITS_EF_TTHD)) +#define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD) +#define BIT_SET_EF_TTHD(x, v) (BIT_CLEAR_EF_TTHD(x) | BIT_EF_TTHD(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ + +#define BIT_SHIFT_AFE_USB_CURRENT_SEL 26 +#define BIT_MASK_AFE_USB_CURRENT_SEL 0x7 +#define BIT_AFE_USB_CURRENT_SEL(x) \ + (((x) & BIT_MASK_AFE_USB_CURRENT_SEL) << BIT_SHIFT_AFE_USB_CURRENT_SEL) +#define BITS_AFE_USB_CURRENT_SEL \ + (BIT_MASK_AFE_USB_CURRENT_SEL << BIT_SHIFT_AFE_USB_CURRENT_SEL) +#define BIT_CLEAR_AFE_USB_CURRENT_SEL(x) ((x) & (~BITS_AFE_USB_CURRENT_SEL)) +#define BIT_GET_AFE_USB_CURRENT_SEL(x) \ + (((x) >> BIT_SHIFT_AFE_USB_CURRENT_SEL) & BIT_MASK_AFE_USB_CURRENT_SEL) +#define BIT_SET_AFE_USB_CURRENT_SEL(x, v) \ + (BIT_CLEAR_AFE_USB_CURRENT_SEL(x) | BIT_AFE_USB_CURRENT_SEL(v)) + +#define BIT_SHIFT_AFE_USB_PATH_SEL 24 +#define BIT_MASK_AFE_USB_PATH_SEL 0x3 +#define BIT_AFE_USB_PATH_SEL(x) \ + (((x) & BIT_MASK_AFE_USB_PATH_SEL) << BIT_SHIFT_AFE_USB_PATH_SEL) +#define BITS_AFE_USB_PATH_SEL \ + (BIT_MASK_AFE_USB_PATH_SEL << BIT_SHIFT_AFE_USB_PATH_SEL) +#define BIT_CLEAR_AFE_USB_PATH_SEL(x) ((x) & (~BITS_AFE_USB_PATH_SEL)) +#define BIT_GET_AFE_USB_PATH_SEL(x) \ + (((x) >> BIT_SHIFT_AFE_USB_PATH_SEL) & BIT_MASK_AFE_USB_PATH_SEL) +#define BIT_SET_AFE_USB_PATH_SEL(x, v) \ + (BIT_CLEAR_AFE_USB_PATH_SEL(x) | BIT_AFE_USB_PATH_SEL(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_DBG_SEL_V1 16 +#define BIT_MASK_DBG_SEL_V1 0xff +#define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1) +#define BITS_DBG_SEL_V1 (BIT_MASK_DBG_SEL_V1 << BIT_SHIFT_DBG_SEL_V1) +#define BIT_CLEAR_DBG_SEL_V1(x) ((x) & (~BITS_DBG_SEL_V1)) +#define BIT_GET_DBG_SEL_V1(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1) +#define BIT_SET_DBG_SEL_V1(x, v) (BIT_CLEAR_DBG_SEL_V1(x) | BIT_DBG_SEL_V1(v)) -#define BIT_SHIFT_AFE_USB_CURRENT_SEL 26 -#define BIT_MASK_AFE_USB_CURRENT_SEL 0x7 -#define BIT_AFE_USB_CURRENT_SEL(x) (((x) & BIT_MASK_AFE_USB_CURRENT_SEL) << BIT_SHIFT_AFE_USB_CURRENT_SEL) -#define BIT_GET_AFE_USB_CURRENT_SEL(x) (((x) >> BIT_SHIFT_AFE_USB_CURRENT_SEL) & BIT_MASK_AFE_USB_CURRENT_SEL) +#endif +#if (HALMAC_8192E_SUPPORT) -#define BIT_SHIFT_AFE_USB_PATH_SEL 24 -#define BIT_MASK_AFE_USB_PATH_SEL 0x3 -#define BIT_AFE_USB_PATH_SEL(x) (((x) & BIT_MASK_AFE_USB_PATH_SEL) << BIT_SHIFT_AFE_USB_PATH_SEL) -#define BIT_GET_AFE_USB_PATH_SEL(x) (((x) >> BIT_SHIFT_AFE_USB_PATH_SEL) & BIT_MASK_AFE_USB_PATH_SEL) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_CLK_REQ_INPUT BIT(15) +#define BIT_USB_XTAL_CLK_SEL BIT(14) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_DBG_SEL_BYTE 14 +#define BIT_MASK_DBG_SEL_BYTE 0x3 +#define BIT_DBG_SEL_BYTE(x) \ + (((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE) +#define BITS_DBG_SEL_BYTE (BIT_MASK_DBG_SEL_BYTE << BIT_SHIFT_DBG_SEL_BYTE) +#define BIT_CLEAR_DBG_SEL_BYTE(x) ((x) & (~BITS_DBG_SEL_BYTE)) +#define BIT_GET_DBG_SEL_BYTE(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE) +#define BIT_SET_DBG_SEL_BYTE(x, v) \ + (BIT_CLEAR_DBG_SEL_BYTE(x) | BIT_DBG_SEL_BYTE(v)) -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_DBG_SEL_V1 16 -#define BIT_MASK_DBG_SEL_V1 0xff -#define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1) -#define BIT_GET_DBG_SEL_V1(x) (((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_USB_REG_XTAL_SEL BIT(14) +#define BIT_SYSON_BTIO1POW_PAD_E2 BIT(13) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_CLK_REQ_INPUT BIT(15) -#define BIT_USB_XTAL_CLK_SEL BIT(14) +#define BIT_SHIFT_SYSON_SPS0_STD_L1 12 +#define BIT_MASK_SYSON_SPS0_STD_L1 0x3 +#define BIT_SYSON_SPS0_STD_L1(x) \ + (((x) & BIT_MASK_SYSON_SPS0_STD_L1) << BIT_SHIFT_SYSON_SPS0_STD_L1) +#define BITS_SYSON_SPS0_STD_L1 \ + (BIT_MASK_SYSON_SPS0_STD_L1 << BIT_SHIFT_SYSON_SPS0_STD_L1) +#define BIT_CLEAR_SYSON_SPS0_STD_L1(x) ((x) & (~BITS_SYSON_SPS0_STD_L1)) +#define BIT_GET_SYSON_SPS0_STD_L1(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0_STD_L1) & BIT_MASK_SYSON_SPS0_STD_L1) +#define BIT_SET_SYSON_SPS0_STD_L1(x, v) \ + (BIT_CLEAR_SYSON_SPS0_STD_L1(x) | BIT_SYSON_SPS0_STD_L1(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ - -#define BIT_SHIFT_DBG_SEL_BYTE 14 -#define BIT_MASK_DBG_SEL_BYTE 0x3 -#define BIT_DBG_SEL_BYTE(x) (((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE) -#define BIT_GET_DBG_SEL_BYTE(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE) - +#define BIT_SHIFT_STD_L1_V1 12 +#define BIT_MASK_STD_L1_V1 0x3 +#define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1) +#define BITS_STD_L1_V1 (BIT_MASK_STD_L1_V1 << BIT_SHIFT_STD_L1_V1) +#define BIT_CLEAR_STD_L1_V1(x) ((x) & (~BITS_STD_L1_V1)) +#define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1) +#define BIT_SET_STD_L1_V1(x, v) (BIT_CLEAR_STD_L1_V1(x) | BIT_STD_L1_V1(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_USB_REG_XTAL_SEL BIT(14) -#define BIT_SYSON_BTIO1POW_PAD_E2 BIT(13) +#define BIT_SYSON_BTIOPOW_PAD_E2 BIT(12) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ - -#define BIT_SHIFT_SYSON_SPS0_STD_L1 12 -#define BIT_MASK_SYSON_SPS0_STD_L1 0x3 -#define BIT_SYSON_SPS0_STD_L1(x) (((x) & BIT_MASK_SYSON_SPS0_STD_L1) << BIT_SHIFT_SYSON_SPS0_STD_L1) -#define BIT_GET_SYSON_SPS0_STD_L1(x) (((x) >> BIT_SHIFT_SYSON_SPS0_STD_L1) & BIT_MASK_SYSON_SPS0_STD_L1) - +#define BIT_SHIFT_SYSON_LDOA12V_WT 12 +#define BIT_MASK_SYSON_LDOA12V_WT 0x3 +#define BIT_SYSON_LDOA12V_WT(x) \ + (((x) & BIT_MASK_SYSON_LDOA12V_WT) << BIT_SHIFT_SYSON_LDOA12V_WT) +#define BITS_SYSON_LDOA12V_WT \ + (BIT_MASK_SYSON_LDOA12V_WT << BIT_SHIFT_SYSON_LDOA12V_WT) +#define BIT_CLEAR_SYSON_LDOA12V_WT(x) ((x) & (~BITS_SYSON_LDOA12V_WT)) +#define BIT_GET_SYSON_LDOA12V_WT(x) \ + (((x) >> BIT_SHIFT_SYSON_LDOA12V_WT) & BIT_MASK_SYSON_LDOA12V_WT) +#define BIT_SET_SYSON_LDOA12V_WT(x, v) \ + (BIT_CLEAR_SYSON_LDOA12V_WT(x) | BIT_SYSON_LDOA12V_WT(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ - -#define BIT_SHIFT_STD_L1_V1 12 -#define BIT_MASK_STD_L1_V1 0x3 -#define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1) -#define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1) - +#define BIT_SYSON_DBG_PAD_E2 BIT(11) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_BTIOPOW_PAD_E2 BIT(12) +#define BIT_SYSON_SDIOPOW_PAD_E2 BIT(11) #endif - -#if (HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ - -#define BIT_SHIFT_SYSON_LDOA12V_WT 12 -#define BIT_MASK_SYSON_LDOA12V_WT 0x3 -#define BIT_SYSON_LDOA12V_WT(x) (((x) & BIT_MASK_SYSON_LDOA12V_WT) << BIT_SHIFT_SYSON_LDOA12V_WT) -#define BIT_GET_SYSON_LDOA12V_WT(x) (((x) >> BIT_SHIFT_SYSON_LDOA12V_WT) & BIT_MASK_SYSON_LDOA12V_WT) - +#define BIT_SYSON_LED_PAD_E2 BIT(10) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_DBG_PAD_E2 BIT(11) +#define BIT_SYSON_GPEE_PAD_E2 BIT(9) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_SDIOPOW_PAD_E2 BIT(11) +#define BIT_SYSON_GPEE_PAD_E2_V33 BIT(9) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ + +#define BIT_SYSON_PCI_PAD_E2 BIT(8) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_SHIFT_MATCH_CNT 8 +#define BIT_MASK_MATCH_CNT 0xff +#define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT) +#define BITS_MATCH_CNT (BIT_MASK_MATCH_CNT << BIT_SHIFT_MATCH_CNT) +#define BIT_CLEAR_MATCH_CNT(x) ((x) & (~BITS_MATCH_CNT)) +#define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT) +#define BIT_SET_MATCH_CNT(x, v) (BIT_CLEAR_MATCH_CNT(x) | BIT_MATCH_CNT(v)) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_LED_PAD_E2 BIT(10) +#define BIT_AUTO_SW_LDO_VOL_EN BIT(7) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */ + +#define BIT_TOGGLE BIT(7) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_GPEE_PAD_E2 BIT(9) +#define BIT_AUTO_SW_LDO_VOL_EN_V1 BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_GPEE_PAD_E2_V33 BIT(9) +#define BIT_ADJ_LDO_VOLT BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_PCI_PAD_E2 BIT(8) +#define BIT_SHIFT_SYSON_LDOHCI12_WT 6 +#define BIT_MASK_SYSON_LDOHCI12_WT 0x3 +#define BIT_SYSON_LDOHCI12_WT(x) \ + (((x) & BIT_MASK_SYSON_LDOHCI12_WT) << BIT_SHIFT_SYSON_LDOHCI12_WT) +#define BITS_SYSON_LDOHCI12_WT \ + (BIT_MASK_SYSON_LDOHCI12_WT << BIT_SHIFT_SYSON_LDOHCI12_WT) +#define BIT_CLEAR_SYSON_LDOHCI12_WT(x) ((x) & (~BITS_SYSON_LDOHCI12_WT)) +#define BIT_GET_SYSON_LDOHCI12_WT(x) \ + (((x) >> BIT_SHIFT_SYSON_LDOHCI12_WT) & BIT_MASK_SYSON_LDOHCI12_WT) +#define BIT_SET_SYSON_LDOHCI12_WT(x, v) \ + (BIT_CLEAR_SYSON_LDOHCI12_WT(x) | BIT_SYSON_LDOHCI12_WT(v)) -#define BIT_SHIFT_MATCH_CNT 8 -#define BIT_MASK_MATCH_CNT 0xff -#define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT) -#define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_SYSON_SPS0WWV_WT 4 +#define BIT_MASK_SYSON_SPS0WWV_WT 0x3 +#define BIT_SYSON_SPS0WWV_WT(x) \ + (((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT) +#define BITS_SYSON_SPS0WWV_WT \ + (BIT_MASK_SYSON_SPS0WWV_WT << BIT_SHIFT_SYSON_SPS0WWV_WT) +#define BIT_CLEAR_SYSON_SPS0WWV_WT(x) ((x) & (~BITS_SYSON_SPS0WWV_WT)) +#define BIT_GET_SYSON_SPS0WWV_WT(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT) +#define BIT_SET_SYSON_SPS0WWV_WT(x, v) \ + (BIT_CLEAR_SYSON_SPS0WWV_WT(x) | BIT_SYSON_SPS0WWV_WT(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_AUTO_SW_LDO_VOL_EN BIT(7) +#define BIT_SHIFT_SYSON_SPS0SPS_WT 4 +#define BIT_MASK_SYSON_SPS0SPS_WT 0x3 +#define BIT_SYSON_SPS0SPS_WT(x) \ + (((x) & BIT_MASK_SYSON_SPS0SPS_WT) << BIT_SHIFT_SYSON_SPS0SPS_WT) +#define BITS_SYSON_SPS0SPS_WT \ + (BIT_MASK_SYSON_SPS0SPS_WT << BIT_SHIFT_SYSON_SPS0SPS_WT) +#define BIT_CLEAR_SYSON_SPS0SPS_WT(x) ((x) & (~BITS_SYSON_SPS0SPS_WT)) +#define BIT_GET_SYSON_SPS0SPS_WT(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0SPS_WT) & BIT_MASK_SYSON_SPS0SPS_WT) +#define BIT_SET_SYSON_SPS0SPS_WT(x, v) \ + (BIT_CLEAR_SYSON_SPS0SPS_WT(x) | BIT_SYSON_SPS0SPS_WT(v)) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_AUTO_SW_LDO_VOL_EN_V1 BIT(6) +#define BIT_SHIFT_SYSON_SPS0LDO_WT 2 +#define BIT_MASK_SYSON_SPS0LDO_WT 0x3 +#define BIT_SYSON_SPS0LDO_WT(x) \ + (((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT) +#define BITS_SYSON_SPS0LDO_WT \ + (BIT_MASK_SYSON_SPS0LDO_WT << BIT_SHIFT_SYSON_SPS0LDO_WT) +#define BIT_CLEAR_SYSON_SPS0LDO_WT(x) ((x) & (~BITS_SYSON_SPS0LDO_WT)) +#define BIT_GET_SYSON_SPS0LDO_WT(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT) +#define BIT_SET_SYSON_SPS0LDO_WT(x, v) \ + (BIT_CLEAR_SYSON_SPS0LDO_WT(x) | BIT_SYSON_SPS0LDO_WT(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_ADJ_LDO_VOLT BIT(6) +#define BIT_SHIFT_SYSON_SPS11VLDO_WT 2 +#define BIT_MASK_SYSON_SPS11VLDO_WT 0x3 +#define BIT_SYSON_SPS11VLDO_WT(x) \ + (((x) & BIT_MASK_SYSON_SPS11VLDO_WT) << BIT_SHIFT_SYSON_SPS11VLDO_WT) +#define BITS_SYSON_SPS11VLDO_WT \ + (BIT_MASK_SYSON_SPS11VLDO_WT << BIT_SHIFT_SYSON_SPS11VLDO_WT) +#define BIT_CLEAR_SYSON_SPS11VLDO_WT(x) ((x) & (~BITS_SYSON_SPS11VLDO_WT)) +#define BIT_GET_SYSON_SPS11VLDO_WT(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS11VLDO_WT) & BIT_MASK_SYSON_SPS11VLDO_WT) +#define BIT_SET_SYSON_SPS11VLDO_WT(x, v) \ + (BIT_CLEAR_SYSON_SPS11VLDO_WT(x) | BIT_SYSON_SPS11VLDO_WT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_SYSON_RCLK_SCALE 0 +#define BIT_MASK_SYSON_RCLK_SCALE 0x3 +#define BIT_SYSON_RCLK_SCALE(x) \ + (((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE) +#define BITS_SYSON_RCLK_SCALE \ + (BIT_MASK_SYSON_RCLK_SCALE << BIT_SHIFT_SYSON_RCLK_SCALE) +#define BIT_CLEAR_SYSON_RCLK_SCALE(x) ((x) & (~BITS_SYSON_RCLK_SCALE)) +#define BIT_GET_SYSON_RCLK_SCALE(x) \ + (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE) +#define BIT_SET_SYSON_RCLK_SCALE(x, v) \ + (BIT_CLEAR_SYSON_RCLK_SCALE(x) | BIT_SYSON_RCLK_SCALE(v)) -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SYSON_LDOHCI12_WT 6 -#define BIT_MASK_SYSON_LDOHCI12_WT 0x3 -#define BIT_SYSON_LDOHCI12_WT(x) (((x) & BIT_MASK_SYSON_LDOHCI12_WT) << BIT_SHIFT_SYSON_LDOHCI12_WT) -#define BIT_GET_SYSON_LDOHCI12_WT(x) (((x) >> BIT_SHIFT_SYSON_LDOHCI12_WT) & BIT_MASK_SYSON_LDOHCI12_WT) +/* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */ +#define BIT_CUR_PS BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_CAL_TIMER (Offset 0x003C) */ -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_SHIFT_CAL_SCAL 0 +#define BIT_MASK_CAL_SCAL 0xff +#define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL) +#define BITS_CAL_SCAL (BIT_MASK_CAL_SCAL << BIT_SHIFT_CAL_SCAL) +#define BIT_CLEAR_CAL_SCAL(x) ((x) & (~BITS_CAL_SCAL)) +#define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL) +#define BIT_SET_CAL_SCAL(x, v) (BIT_CLEAR_CAL_SCAL(x) | BIT_CAL_SCAL(v)) +/* 2 REG_ACLK_MON (Offset 0x003E) */ -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_RCLK_MON 5 +#define BIT_MASK_RCLK_MON 0x7ff +#define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON) +#define BITS_RCLK_MON (BIT_MASK_RCLK_MON << BIT_SHIFT_RCLK_MON) +#define BIT_CLEAR_RCLK_MON(x) ((x) & (~BITS_RCLK_MON)) +#define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON) +#define BIT_SET_RCLK_MON(x, v) (BIT_CLEAR_RCLK_MON(x) | BIT_RCLK_MON(v)) +#define BIT_CAL_EN BIT(4) -#define BIT_SHIFT_SYSON_SPS0WWV_WT 4 -#define BIT_MASK_SYSON_SPS0WWV_WT 0x3 -#define BIT_SYSON_SPS0WWV_WT(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT) -#define BIT_GET_SYSON_SPS0WWV_WT(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT) +#define BIT_SHIFT_DPSTU 2 +#define BIT_MASK_DPSTU 0x3 +#define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU) +#define BITS_DPSTU (BIT_MASK_DPSTU << BIT_SHIFT_DPSTU) +#define BIT_CLEAR_DPSTU(x) ((x) & (~BITS_DPSTU)) +#define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU) +#define BIT_SET_DPSTU(x, v) (BIT_CLEAR_DPSTU(x) | BIT_DPSTU(v)) +#define BIT_SUS_16X BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_ACLK_MON (Offset 0x003E) */ +#define BIT_RSM_EN BIT(0) -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SYSON_SPS0SPS_WT 4 -#define BIT_MASK_SYSON_SPS0SPS_WT 0x3 -#define BIT_SYSON_SPS0SPS_WT(x) (((x) & BIT_MASK_SYSON_SPS0SPS_WT) << BIT_SHIFT_SYSON_SPS0SPS_WT) -#define BIT_GET_SYSON_SPS0SPS_WT(x) (((x) >> BIT_SHIFT_SYSON_SPS0SPS_WT) & BIT_MASK_SYSON_SPS0SPS_WT) +/* 2 REG_GPIO_MUXCFG_2 (Offset 0x003F) */ +#define BIT_SOUT_GPIO8 BIT(7) +#define BIT_SOUT_GPIO5 BIT(6) +#define BIT_RFE_CTRL_5_GPIO14_V1 BIT(5) +#define BIT_RFE_CTRL_10_GPIO13_V1 BIT(4) +#define BIT_RFE_CTRL_11_GPIO4_V1 BIT(3) +#define BIT_RFE_CTRL_5_GPIO14 BIT(2) +#define BIT_RFE_CTRL_10_GPIO13 BIT(1) +#define BIT_RFE_CTRL_11_GPIO4 BIT(0) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_PAD_D_PAPE_2G_E BIT(31) -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SYSON_SPS0LDO_WT 2 -#define BIT_MASK_SYSON_SPS0LDO_WT 0x3 -#define BIT_SYSON_SPS0LDO_WT(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT) -#define BIT_GET_SYSON_SPS0LDO_WT(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_RFE_CTRL_3_GPIO12 BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_PAD_D_PAPE_5G_E BIT(30) +#endif + +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SYSON_SPS11VLDO_WT 2 -#define BIT_MASK_SYSON_SPS11VLDO_WT 0x3 -#define BIT_SYSON_SPS11VLDO_WT(x) (((x) & BIT_MASK_SYSON_SPS11VLDO_WT) << BIT_SHIFT_SYSON_SPS11VLDO_WT) -#define BIT_GET_SYSON_SPS11VLDO_WT(x) (((x) >> BIT_SHIFT_SYSON_SPS11VLDO_WT) & BIT_MASK_SYSON_SPS11VLDO_WT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_BT_RFE_CTRL_5_GPIO12 BIT(30) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_PAD_D_TRSW_E BIT(29) -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SYSON_RCLK_SCALE 0 -#define BIT_MASK_SYSON_RCLK_SCALE 0x3 -#define BIT_SYSON_RCLK_SCALE(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE) -#define BIT_GET_SYSON_RCLK_SCALE(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_S0_TRSW_GPIO12 BIT(29) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_SIC_LOWEST_PRIORITY BIT(28) -/* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */ +#endif -#define BIT_SYS_CLK BIT(0) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_PAD_D_TRSWB_E BIT(28) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_CAL_TIMER (Offset 0x003C) */ +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_RFE_CTRL_9_GPIO13 BIT(28) -#define BIT_SHIFT_CAL_SCAL 0 -#define BIT_MASK_CAL_SCAL 0xff -#define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL) -#define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_ACLK_MON (Offset 0x003E) */ +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_PAD_D_PAPE_2G_O BIT(27) -#define BIT_SHIFT_RCLK_MON 5 -#define BIT_MASK_RCLK_MON 0x7ff -#define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON) -#define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON) +#endif -#define BIT_CAL_EN BIT(4) +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DPSTU 2 -#define BIT_MASK_DPSTU 0x3 -#define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU) -#define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_SUS_16X BIT(1) +#define BIT_RFE_CTRL_9_GPIO12 BIT(27) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_PAD_D_PAPE_5G_O BIT(26) -/* 2 REG_ACLK_MON (Offset 0x003E) */ +#endif -#define BIT_RSM_EN BIT(0) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_RFE_CTRL_8_GPIO4 BIT(26) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_PAD_D_PAPE_2G_E BIT(31) -#define BIT_PAD_D_PAPE_5G_E BIT(30) -#define BIT_PAD_D_TRSW_E BIT(29) +#define BIT_PAD_D_TRSW_O BIT(25) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ + +#define BIT_BT_RFE_CTRL_1_GPIO13 BIT(25) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_SIC_LOWEST_PRIORITY BIT(28) +#define BIT_SHIFT_PIN_USECASE 24 +#define BIT_MASK_PIN_USECASE 0xf +#define BIT_PIN_USECASE(x) \ + (((x) & BIT_MASK_PIN_USECASE) << BIT_SHIFT_PIN_USECASE) +#define BITS_PIN_USECASE (BIT_MASK_PIN_USECASE << BIT_SHIFT_PIN_USECASE) +#define BIT_CLEAR_PIN_USECASE(x) ((x) & (~BITS_PIN_USECASE)) +#define BIT_GET_PIN_USECASE(x) \ + (((x) >> BIT_SHIFT_PIN_USECASE) & BIT_MASK_PIN_USECASE) +#define BIT_SET_PIN_USECASE(x, v) \ + (BIT_CLEAR_PIN_USECASE(x) | BIT_PIN_USECASE(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_PAD_D_TRSWB_E BIT(28) -#define BIT_PAD_D_PAPE_2G_O BIT(27) -#define BIT_PAD_D_PAPE_5G_O BIT(26) -#define BIT_PAD_D_TRSW_O BIT(25) +#define BIT_PAD_D_TRSWB_O BIT(24) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_EN_DATACPU_GPIO2 BIT(24) -/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PIN_USECASE 24 -#define BIT_MASK_PIN_USECASE 0xf -#define BIT_PIN_USECASE(x) (((x) & BIT_MASK_PIN_USECASE) << BIT_SHIFT_PIN_USECASE) -#define BIT_GET_PIN_USECASE(x) (((x) >> BIT_SHIFT_PIN_USECASE) & BIT_MASK_PIN_USECASE) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_BT_RFE_CTRL_1_GPIO12 BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_PAD_D_TRSWB_O BIT(24) -#define BIT_EN_A_ANTSEL BIT(23) -#define BIT_EN_A_ANTSELB BIT(22) -#define BIT_EN_D_PAPE_2G BIT(21) +#define BIT_EN_A_ANTSEL BIT(23) #endif +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ + +#define BIT_EN_DATACPU_GPIO BIT(23) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_INDIRECT_REG_RDY BIT(20) +#define BIT_BT_RFE_CTRL_0_GPIO4 BIT(23) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_EN_D_PAPE_5G BIT(20) +#define BIT_EN_A_ANTSELB BIT(22) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_FSPI_EN BIT(19) +#define BIT_EN_DATACPU_UART BIT(22) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_ANTSW_GPIO13 BIT(22) -/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#endif -#define BIT_INDIRECT_REG_R BIT(19) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_EN_D_PAPE_2G BIT(21) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_WL_RTS_EXT_32K_SEL BIT(18) +#define BIT_DATACPU_FSPI_EN BIT(21) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_ANTSW_GPIO12 BIT(21) -/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#endif -#define BIT_INDIRECT_REG_W BIT(18) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#define BIT_INDIRECT_REG_RDY BIT(20) -#if (HALMAC_8192E_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_CKOUT33_EN BIT(17) +#define BIT_EN_D_PAPE_5G BIT(20) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_XTAL_OUT_EN BIT(17) +#define BIT_EN_GPIO8_UART_OUT BIT(20) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_WLGP_SPI_EN BIT(16) +#define BIT_ANTSWB_GPIO4 BIT(20) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_FSPI_EN BIT(19) -/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_INDIRECT_REG_SIZE 16 -#define BIT_MASK_INDIRECT_REG_SIZE 0x3 -#define BIT_INDIRECT_REG_SIZE(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE) -#define BIT_GET_INDIRECT_REG_SIZE(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE) +/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#define BIT_INDIRECT_REG_R BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_SIC_LBK BIT(15) -#define BIT_ENHTP BIT(14) +#define BIT_WL_RTS_EXT_32K_SEL BIT(18) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ + +#define BIT_INDIRECT_REG_W BIT(18) + +#endif +#if (HALMAC_8192E_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_WLPHY_DBG_EN BIT(13) +#define BIT_CKOUT33_EN BIT(17) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_SIC_23 BIT(13) +#define BIT_XTAL_OUT_EN BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_ENSIC BIT(12) -#define BIT_SIC_SWRST BIT(11) +#define BIT_WLBT_DPDT_SEL_EN BIT(17) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_PO_WIFI_PTA_PINS BIT(10) +#define BIT_WLGP_SPI_EN BIT(16) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#define BIT_SHIFT_INDIRECT_REG_SIZE 16 +#define BIT_MASK_INDIRECT_REG_SIZE 0x3 +#define BIT_INDIRECT_REG_SIZE(x) \ + (((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE) +#define BITS_INDIRECT_REG_SIZE \ + (BIT_MASK_INDIRECT_REG_SIZE << BIT_SHIFT_INDIRECT_REG_SIZE) +#define BIT_CLEAR_INDIRECT_REG_SIZE(x) ((x) & (~BITS_INDIRECT_REG_SIZE)) +#define BIT_GET_INDIRECT_REG_SIZE(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE) +#define BIT_SET_INDIRECT_REG_SIZE(x, v) \ + (BIT_CLEAR_INDIRECT_REG_SIZE(x) | BIT_INDIRECT_REG_SIZE(v)) -/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#endif -#define BIT_ENPMAC BIT(10) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_WLBT_LNAON_SEL_EN BIT(16) -#if (HALMAC_8192E_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_ENBTCMD BIT(9) +#define BIT_SIC_LBK BIT(15) +#define BIT_ENHTP BIT(14) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_BTCOEX_MBOX_EN BIT(9) +#define BIT_WLPHY_DBG_EN BIT(13) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_BTCMD_OUT_EN BIT(9) +#define BIT_SIC_23 BIT(13) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_PO_BT_PTA_PINS BIT(9) +#define BIT_BT_AOD_GPIO3 BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_ENUART BIT(8) - -#define BIT_SHIFT_BTMODE 6 -#define BIT_MASK_BTMODE 0x3 -#define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE) -#define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE) - -#define BIT_ENBT BIT(5) -#define BIT_EROM_EN BIT(4) +#define BIT_ENSIC BIT(12) +#define BIT_SIC_SWRST BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_WLRFE_6_7_EN BIT(3) +#define BIT_PO_WIFI_PTA_PINS BIT(10) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_EN_D_TRSW BIT(3) +#define BIT_ENPMAC BIT(10) #endif +#if (HALMAC_8192E_SUPPORT) + +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ + +#define BIT_ENBTCMD BIT(9) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_WLRFE_4_5_EN BIT(2) +#define BIT_BTCOEX_MBOX_EN BIT(9) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_EN_D_TRSWB BIT(2) +#define BIT_BTCMD_OUT_EN BIT(9) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ + +#define BIT_PO_BT_PTA_PINS BIT(9) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_ENUART BIT(8) -#define BIT_SHIFT_GPIOSEL 0 -#define BIT_MASK_GPIOSEL 0x3 -#define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL) -#define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL) +#define BIT_SHIFT_BTMODE 6 +#define BIT_MASK_BTMODE 0x3 +#define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE) +#define BITS_BTMODE (BIT_MASK_BTMODE << BIT_SHIFT_BTMODE) +#define BIT_CLEAR_BTMODE(x) ((x) & (~BITS_BTMODE)) +#define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE) +#define BIT_SET_BTMODE(x, v) (BIT_CLEAR_BTMODE(x) | BIT_BTMODE(v)) +#define BIT_ENBT BIT(5) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_GEN1GEN2_SWITCH BIT(5) -/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_INDIRECT_REG_ADDR 0 -#define BIT_MASK_INDIRECT_REG_ADDR 0xffff -#define BIT_INDIRECT_REG_ADDR(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR) -#define BIT_GET_INDIRECT_REG_ADDR(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_EROM_EN BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */ +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_WLRFE_6_7_EN BIT(3) -#define BIT_SHIFT_GPIO_MOD_7_TO_0 24 -#define BIT_MASK_GPIO_MOD_7_TO_0 0xff -#define BIT_GPIO_MOD_7_TO_0(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0) -#define BIT_GET_GPIO_MOD_7_TO_0(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16 -#define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff -#define BIT_GPIO_IO_SEL_7_TO_0(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0) -#define BIT_GET_GPIO_IO_SEL_7_TO_0(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_EN_D_TRSW BIT(3) -#define BIT_SHIFT_GPIO_OUT_7_TO_0 8 -#define BIT_MASK_GPIO_OUT_7_TO_0 0xff -#define BIT_GPIO_OUT_7_TO_0(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0) -#define BIT_GET_GPIO_OUT_7_TO_0(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_GPIO_IN_7_TO_0 0 -#define BIT_MASK_GPIO_IN_7_TO_0 0xff -#define BIT_GPIO_IN_7_TO_0(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0) -#define BIT_GET_GPIO_IN_7_TO_0(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_WLRFE_4_5_EN BIT(2) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_EN_D_TRSWB BIT(2) -/* 2 REG_SDIO_INDIRECT_REG_DATA (Offset 0x10250044) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_INDIRECT_REG_DATA 0 -#define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL -#define BIT_INDIRECT_REG_DATA(x) (((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA) -#define BIT_GET_INDIRECT_REG_DATA(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_SHIFT_GPIOSEL 0 +#define BIT_MASK_GPIOSEL 0x3 +#define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL) +#define BITS_GPIOSEL (BIT_MASK_GPIOSEL << BIT_SHIFT_GPIOSEL) +#define BIT_CLEAR_GPIOSEL(x) ((x) & (~BITS_GPIOSEL)) +#define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL) +#define BIT_SET_GPIOSEL(x, v) (BIT_CLEAR_GPIOSEL(x) | BIT_GPIOSEL(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#define BIT_SHIFT_INDIRECT_REG_ADDR 0 +#define BIT_MASK_INDIRECT_REG_ADDR 0xffff +#define BIT_INDIRECT_REG_ADDR(x) \ + (((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR) +#define BITS_INDIRECT_REG_ADDR \ + (BIT_MASK_INDIRECT_REG_ADDR << BIT_SHIFT_INDIRECT_REG_ADDR) +#define BIT_CLEAR_INDIRECT_REG_ADDR(x) ((x) & (~BITS_INDIRECT_REG_ADDR)) +#define BIT_GET_INDIRECT_REG_ADDR(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR) +#define BIT_SET_INDIRECT_REG_ADDR(x, v) \ + (BIT_CLEAR_INDIRECT_REG_ADDR(x) | BIT_INDIRECT_REG_ADDR(v)) -/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MUXDBG_SEL 30 -#define BIT_MASK_MUXDBG_SEL 0x3 -#define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL) -#define BIT_GET_MUXDBG_SEL(x) (((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL) +/* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */ +#define BIT_SHIFT_GPIO_MOD_7_TO_0 24 +#define BIT_MASK_GPIO_MOD_7_TO_0 0xff +#define BIT_GPIO_MOD_7_TO_0(x) \ + (((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0) +#define BITS_GPIO_MOD_7_TO_0 \ + (BIT_MASK_GPIO_MOD_7_TO_0 << BIT_SHIFT_GPIO_MOD_7_TO_0) +#define BIT_CLEAR_GPIO_MOD_7_TO_0(x) ((x) & (~BITS_GPIO_MOD_7_TO_0)) +#define BIT_GET_GPIO_MOD_7_TO_0(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0) +#define BIT_SET_GPIO_MOD_7_TO_0(x, v) \ + (BIT_CLEAR_GPIO_MOD_7_TO_0(x) | BIT_GPIO_MOD_7_TO_0(v)) + +#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16 +#define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff +#define BIT_GPIO_IO_SEL_7_TO_0(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0) +#define BITS_GPIO_IO_SEL_7_TO_0 \ + (BIT_MASK_GPIO_IO_SEL_7_TO_0 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) ((x) & (~BITS_GPIO_IO_SEL_7_TO_0)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0) +#define BIT_SET_GPIO_IO_SEL_7_TO_0(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) | BIT_GPIO_IO_SEL_7_TO_0(v)) + +#define BIT_SHIFT_GPIO_OUT_7_TO_0 8 +#define BIT_MASK_GPIO_OUT_7_TO_0 0xff +#define BIT_GPIO_OUT_7_TO_0(x) \ + (((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0) +#define BITS_GPIO_OUT_7_TO_0 \ + (BIT_MASK_GPIO_OUT_7_TO_0 << BIT_SHIFT_GPIO_OUT_7_TO_0) +#define BIT_CLEAR_GPIO_OUT_7_TO_0(x) ((x) & (~BITS_GPIO_OUT_7_TO_0)) +#define BIT_GET_GPIO_OUT_7_TO_0(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0) +#define BIT_SET_GPIO_OUT_7_TO_0(x, v) \ + (BIT_CLEAR_GPIO_OUT_7_TO_0(x) | BIT_GPIO_OUT_7_TO_0(v)) + +#define BIT_SHIFT_GPIO_IN_7_TO_0 0 +#define BIT_MASK_GPIO_IN_7_TO_0 0xff +#define BIT_GPIO_IN_7_TO_0(x) \ + (((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0) +#define BITS_GPIO_IN_7_TO_0 \ + (BIT_MASK_GPIO_IN_7_TO_0 << BIT_SHIFT_GPIO_IN_7_TO_0) +#define BIT_CLEAR_GPIO_IN_7_TO_0(x) ((x) & (~BITS_GPIO_IN_7_TO_0)) +#define BIT_GET_GPIO_IN_7_TO_0(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0) +#define BIT_SET_GPIO_IN_7_TO_0(x, v) \ + (BIT_CLEAR_GPIO_IN_7_TO_0(x) | BIT_GPIO_IN_7_TO_0(v)) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_INDIRECT_REG_DATA (Offset 0x10250044) */ +#define BIT_SHIFT_INDIRECT_REG_DATA 0 +#define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL +#define BIT_INDIRECT_REG_DATA(x) \ + (((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA) +#define BITS_INDIRECT_REG_DATA \ + (BIT_MASK_INDIRECT_REG_DATA << BIT_SHIFT_INDIRECT_REG_DATA) +#define BIT_CLEAR_INDIRECT_REG_DATA(x) ((x) & (~BITS_INDIRECT_REG_DATA)) +#define BIT_GET_INDIRECT_REG_DATA(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA) +#define BIT_SET_INDIRECT_REG_DATA(x, v) \ + (BIT_CLEAR_INDIRECT_REG_DATA(x) | BIT_INDIRECT_REG_DATA(v)) -#if (HALMAC_8192E_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ +#define BIT_SHIFT_MUXDBG_SEL 30 +#define BIT_MASK_MUXDBG_SEL 0x3 +#define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL) +#define BITS_MUXDBG_SEL (BIT_MASK_MUXDBG_SEL << BIT_SHIFT_MUXDBG_SEL) +#define BIT_CLEAR_MUXDBG_SEL(x) ((x) & (~BITS_MUXDBG_SEL)) +#define BIT_GET_MUXDBG_SEL(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL) +#define BIT_SET_MUXDBG_SEL(x, v) (BIT_CLEAR_MUXDBG_SEL(x) | BIT_MUXDBG_SEL(v)) -#define BIT_SHIFT_MUXDBG_SEL2 28 -#define BIT_MASK_MUXDBG_SEL2 0x3 -#define BIT_MUXDBG_SEL2(x) (((x) & BIT_MASK_MUXDBG_SEL2) << BIT_SHIFT_MUXDBG_SEL2) -#define BIT_GET_MUXDBG_SEL2(x) (((x) >> BIT_SHIFT_MUXDBG_SEL2) & BIT_MASK_MUXDBG_SEL2) +#endif +#if (HALMAC_8192E_SUPPORT) -#endif +/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#define BIT_SHIFT_MUXDBG_SEL2 28 +#define BIT_MASK_MUXDBG_SEL2 0x3 +#define BIT_MUXDBG_SEL2(x) \ + (((x) & BIT_MASK_MUXDBG_SEL2) << BIT_SHIFT_MUXDBG_SEL2) +#define BITS_MUXDBG_SEL2 (BIT_MASK_MUXDBG_SEL2 << BIT_SHIFT_MUXDBG_SEL2) +#define BIT_CLEAR_MUXDBG_SEL2(x) ((x) & (~BITS_MUXDBG_SEL2)) +#define BIT_GET_MUXDBG_SEL2(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL2) & BIT_MASK_MUXDBG_SEL2) +#define BIT_SET_MUXDBG_SEL2(x, v) \ + (BIT_CLEAR_MUXDBG_SEL2(x) | BIT_MUXDBG_SEL2(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ -#define BIT_GPIO_EXT_EN BIT(20) +#define BIT_GPIO_EXT_EN BIT(20) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_GPIO_INTM (Offset 0x0048) */ -#define BIT_EXTWOL1_SEL BIT(19) -#define BIT_EXTWOL1_EN BIT(18) +#define BIT_EXTWOL1_SEL BIT(19) +#define BIT_EXTWOL1_EN BIT(18) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_GPIO_INTM (Offset 0x0048) */ -#define BIT_EXTWOL0_SEL BIT(17) +#define BIT_EXTWOL0_SEL BIT(17) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ -#define BIT_EXTWOL_SEL BIT(17) +#define BIT_EXTWOL_SEL BIT(17) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_GPIO_INTM (Offset 0x0048) */ -#define BIT_EXTWOL0_EN BIT(16) +#define BIT_EXTWOL0_EN BIT(16) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ -#define BIT_EXTWOL_EN BIT(16) +#define BIT_EXTWOL_EN BIT(16) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GPIO_INTM (Offset 0x0048) */ - -#define BIT_SHIFT_GPIO_EXT_WOL_V1 16 -#define BIT_MASK_GPIO_EXT_WOL_V1 0xf -#define BIT_GPIO_EXT_WOL_V1(x) (((x) & BIT_MASK_GPIO_EXT_WOL_V1) << BIT_SHIFT_GPIO_EXT_WOL_V1) -#define BIT_GET_GPIO_EXT_WOL_V1(x) (((x) >> BIT_SHIFT_GPIO_EXT_WOL_V1) & BIT_MASK_GPIO_EXT_WOL_V1) - +#define BIT_SHIFT_GPIO_EXT_WOL_V1 16 +#define BIT_MASK_GPIO_EXT_WOL_V1 0xf +#define BIT_GPIO_EXT_WOL_V1(x) \ + (((x) & BIT_MASK_GPIO_EXT_WOL_V1) << BIT_SHIFT_GPIO_EXT_WOL_V1) +#define BITS_GPIO_EXT_WOL_V1 \ + (BIT_MASK_GPIO_EXT_WOL_V1 << BIT_SHIFT_GPIO_EXT_WOL_V1) +#define BIT_CLEAR_GPIO_EXT_WOL_V1(x) ((x) & (~BITS_GPIO_EXT_WOL_V1)) +#define BIT_GET_GPIO_EXT_WOL_V1(x) \ + (((x) >> BIT_SHIFT_GPIO_EXT_WOL_V1) & BIT_MASK_GPIO_EXT_WOL_V1) +#define BIT_SET_GPIO_EXT_WOL_V1(x, v) \ + (BIT_CLEAR_GPIO_EXT_WOL_V1(x) | BIT_GPIO_EXT_WOL_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ -#define BIT_GPIOF_INT_MD BIT(15) -#define BIT_GPIOE_INT_MD BIT(14) -#define BIT_GPIOD_INT_MD BIT(13) -#define BIT_GPIOC_INT_MD BIT(12) -#define BIT_GPIOB_INT_MD BIT(11) -#define BIT_GPIOA_INT_MD BIT(10) -#define BIT_GPIO9_INT_MD BIT(9) -#define BIT_GPIO8_INT_MD BIT(8) -#define BIT_GPIO7_INT_MD BIT(7) -#define BIT_GPIO6_INT_MD BIT(6) -#define BIT_GPIO5_INT_MD BIT(5) -#define BIT_GPIO4_INT_MD BIT(4) -#define BIT_GPIO3_INT_MD BIT(3) -#define BIT_GPIO2_INT_MD BIT(2) -#define BIT_GPIO1_INT_MD BIT(1) -#define BIT_GPIO0_INT_MD BIT(0) +#define BIT_GPIOF_INT_MD BIT(15) +#define BIT_GPIOE_INT_MD BIT(14) +#define BIT_GPIOD_INT_MD BIT(13) +#define BIT_GPIOC_INT_MD BIT(12) +#define BIT_GPIOB_INT_MD BIT(11) +#define BIT_GPIOA_INT_MD BIT(10) +#define BIT_GPIO9_INT_MD BIT(9) +#define BIT_GPIO8_INT_MD BIT(8) +#define BIT_GPIO7_INT_MD BIT(7) +#define BIT_GPIO6_INT_MD BIT(6) +#define BIT_GPIO5_INT_MD BIT(5) +#define BIT_GPIO4_INT_MD BIT(4) +#define BIT_GPIO3_INT_MD BIT(3) +#define BIT_GPIO2_INT_MD BIT(2) +#define BIT_GPIO1_INT_MD BIT(1) +#define BIT_GPIO0_INT_MD BIT(0) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_PAD_ANTSEL_I BIT(31) +#define BIT_PAD_ANTSEL_I BIT(31) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_MAILBOX_1WIRE_GPIO_CFG BIT(31) +#endif + +#if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_ANT_SEL7_EN BIT(30) +#define BIT_ANT_SEL7_EN BIT(30) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_PAD_ANTSELB_I BIT(30) +#define BIT_PAD_ANTSELB_I BIT(30) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_ANT_SEL46_EN BIT(29) +#define BIT_BT_RF_GPIO_CFG BIT(30) #endif +#if (HALMAC_8192E_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_ANT_SEL46_EN BIT(29) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_PAD_D_PAPE_2G_I BIT(29) +#define BIT_PAD_D_PAPE_2G_I BIT(29) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_BT_SDIO_INT_GPIO_CFG BIT(29) + +#endif +#if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_ANT_SEL3_EN BIT(28) +#define BIT_ANT_SEL3_EN BIT(28) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_PAD_D_PAPE_5G_I BIT(28) +#define BIT_PAD_D_PAPE_5G_I BIT(28) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_MAILBOX_3WIRE_GPIO_CFG BIT(28) + +#endif +#if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_TRSW_SEL_EN BIT(27) +#define BIT_TRSW_SEL_EN BIT(27) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_PAD_D_TRSW_I BIT(27) +#define BIT_PAD_D_TRSW_I BIT(27) #endif - #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_GPIO3_WL_CTRL_EN BIT(27) +#define BIT_GPIO3_WL_CTRL_EN BIT(27) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_PAPE1_SEL_EN BIT(26) +#define BIT_WLBT_PAPE_SEL_EN BIT(27) #endif +#if (HALMAC_8192E_SUPPORT) + +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_PAPE1_SEL_EN BIT(26) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_LNAON_SEL_EN BIT(26) +#define BIT_LNAON_SEL_EN BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_PAD_D_TRSWB_I BIT(26) +#define BIT_PAD_D_TRSWB_I BIT(26) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_PAPE0_SEL_EN BIT(25) +#define BIT_PAPE0_SEL_EN BIT(25) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_PAPE_SEL_EN BIT(25) +#define BIT_PAPE_SEL_EN BIT(25) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_DWH_EN BIT(25) +#define BIT_DWH_EN BIT(25) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_ANTSEL2_EN BIT(24) +#define BIT_ANTSEL2_EN BIT(24) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_DPDT_WLBT_SEL BIT(24) +#define BIT_DPDT_WLBT_SEL BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_DHW_EN BIT(24) +#define BIT_DHW_EN BIT(24) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_RFE_ANT_EXT_SEL BIT(24) +#define BIT_RFE_ANT_EXT_SEL BIT(24) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_ANTSEL_EN BIT(23) +#define BIT_ANTSEL_EN BIT(23) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_DPDT_SEL_EN BIT(23) +#define BIT_DPDT_SEL_EN BIT(23) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_GPIO13_14_WL_CTRL_EN BIT(22) +#define BIT_GPIO13_14_WL_CTRL_EN BIT(22) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_LED2DIS_V1 BIT(22) +#define BIT_LED2DIS_V1 BIT(22) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_TRXIQ_DBG_EN BIT(22) +#define BIT_TRXIQ_DBG_EN BIT(22) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_LED2DIS BIT(21) +#define BIT_LED2DIS BIT(21) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_LED2EN BIT(21) +#define BIT_LED2EN BIT(21) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_LED2PL BIT(20) -#define BIT_LED2SV BIT(19) +#define BIT_LED2PL BIT(20) +#define BIT_LED2SV BIT(19) -#define BIT_SHIFT_LED2CM 16 -#define BIT_MASK_LED2CM 0x7 -#define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM) -#define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM) +#define BIT_SHIFT_LED2CM 16 +#define BIT_MASK_LED2CM 0x7 +#define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM) +#define BITS_LED2CM (BIT_MASK_LED2CM << BIT_SHIFT_LED2CM) +#define BIT_CLEAR_LED2CM(x) ((x) & (~BITS_LED2CM)) +#define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM) +#define BIT_SET_LED2CM(x, v) (BIT_CLEAR_LED2CM(x) | BIT_LED2CM(v)) -#define BIT_LED1DIS BIT(15) -#define BIT_LED1PL BIT(12) -#define BIT_LED1SV BIT(11) +#define BIT_LED1DIS BIT(15) +#define BIT_LED1PL BIT(12) +#define BIT_LED1SV BIT(11) -#define BIT_SHIFT_LED1CM 8 -#define BIT_MASK_LED1CM 0x7 -#define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM) -#define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM) +#define BIT_SHIFT_LED1CM 8 +#define BIT_MASK_LED1CM 0x7 +#define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM) +#define BITS_LED1CM (BIT_MASK_LED1CM << BIT_SHIFT_LED1CM) +#define BIT_CLEAR_LED1CM(x) ((x) & (~BITS_LED1CM)) +#define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM) +#define BIT_SET_LED1CM(x, v) (BIT_CLEAR_LED1CM(x) | BIT_LED1CM(v)) -#define BIT_LED0DIS BIT(7) +#define BIT_LED0DIS BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ - -#define BIT_SHIFT_AFE_LDO_SWR_CHECK 5 -#define BIT_MASK_AFE_LDO_SWR_CHECK 0x3 -#define BIT_AFE_LDO_SWR_CHECK(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK) -#define BIT_GET_AFE_LDO_SWR_CHECK(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK) - +#define BIT_SHIFT_AFE_LDO_SWR_CHECK 5 +#define BIT_MASK_AFE_LDO_SWR_CHECK 0x3 +#define BIT_AFE_LDO_SWR_CHECK(x) \ + (((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK) +#define BITS_AFE_LDO_SWR_CHECK \ + (BIT_MASK_AFE_LDO_SWR_CHECK << BIT_SHIFT_AFE_LDO_SWR_CHECK) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK(x) ((x) & (~BITS_AFE_LDO_SWR_CHECK)) +#define BIT_GET_AFE_LDO_SWR_CHECK(x) \ + (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK) +#define BIT_SET_AFE_LDO_SWR_CHECK(x, v) \ + (BIT_CLEAR_AFE_LDO_SWR_CHECK(x) | BIT_AFE_LDO_SWR_CHECK(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_LED0PL BIT(4) -#define BIT_LED0SV BIT(3) - -#define BIT_SHIFT_LED0CM 0 -#define BIT_MASK_LED0CM 0x7 -#define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM) -#define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM) +#define BIT_LED0PL BIT(4) +#define BIT_LED0SV BIT(3) +#define BIT_SHIFT_LED0CM 0 +#define BIT_MASK_LED0CM 0x7 +#define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM) +#define BITS_LED0CM (BIT_MASK_LED0CM << BIT_SHIFT_LED0CM) +#define BIT_CLEAR_LED0CM(x) ((x) & (~BITS_LED0CM)) +#define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM) +#define BIT_SET_LED0CM(x, v) (BIT_CLEAR_LED0CM(x) | BIT_LED0CM(v)) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_PDNINT_EN BIT(31) +#define BIT_FS_PDNINT_EN BIT(31) #endif - #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_NFC_INT_PAD_EN BIT(30) +#define BIT_NFC_INT_PAD_EN BIT(30) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_SPS_OCP_INT_EN BIT(29) +#define BIT_FS_SPS_OCP_INT_EN BIT(29) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_SW_SPS_OCP_INT_EN BIT(29) +#define BIT_SW_SPS_OCP_INT_EN BIT(29) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_PWMERR_INT_EN BIT(28) +#define BIT_FS_PWMERR_INT_EN BIT(28) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_PWM_HW_ERR_EN BIT(28) +#define BIT_FS_PWM_HW_ERR_EN BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOF_INT_EN BIT(27) -#define BIT_FS_GPIOE_INT_EN BIT(26) -#define BIT_FS_GPIOD_INT_EN BIT(25) -#define BIT_FS_GPIOC_INT_EN BIT(24) +#define BIT_FS_GPIOF_INT_EN BIT(27) +#define BIT_FS_GPIOE_INT_EN BIT(26) +#define BIT_FS_GPIOD_INT_EN BIT(25) +#define BIT_FS_GPIOC_INT_EN BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_ACT2RECOVERY_INT_EN BIT(24) +#define BIT_ACT2RECOVERY_INT_EN BIT(24) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOB_INT_EN BIT(23) +#define BIT_FS_GPIOB_INT_EN BIT(23) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_PCIE_GEN12_SWITH_EN BIT(23) +#define BIT_PCIE_GEN12_SWITCH_EN BIT(23) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOA_INT_EN BIT(22) +#define BIT_FS_GPIOA_INT_EN BIT(22) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_HCI_SUS_EN_V1 BIT(22) +#define BIT_FS_HCI_SUS_EN_V1 BIT(22) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO9_INT_EN BIT(21) +#define BIT_FS_GPIO9_INT_EN BIT(21) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_HCI_RES_EN_V1 BIT(21) +#define BIT_FS_HCI_RES_EN_V1 BIT(21) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO8_INT_EN BIT(20) +#define BIT_FS_GPIO8_INT_EN BIT(20) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_HCI_RESET_EN_V1 BIT(20) +#define BIT_FS_HCI_RESET_EN_V1 BIT(20) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO7_INT_EN BIT(19) +#define BIT_FS_GPIO7_INT_EN BIT(19) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_32K_LEAVE_SETTING_EN BIT(19) +#define BIT_FS_32K_LEAVE_SETTING_EN BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO6_INT_EN BIT(18) +#define BIT_FS_GPIO6_INT_EN BIT(18) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_32K_ENTER_SETTING_EN BIT(18) +#define BIT_FS_32K_ENTER_SETTING_EN BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO5_INT_EN BIT(17) +#define BIT_FS_GPIO5_INT_EN BIT(17) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_SIE_LPM_RSM_EN_V1 BIT(17) +#define BIT_FS_SIE_LPM_RSM_EN_V1 BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO4_INT_EN BIT(16) +#define BIT_FS_GPIO4_INT_EN BIT(16) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_SIE_LPM_ACT_EN_V1 BIT(16) +#define BIT_FS_SIE_LPM_ACT_EN_V1 BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO3_INT_EN BIT(15) +#define BIT_FS_GPIO3_INT_EN BIT(15) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOF_INT_EN_V1 BIT(15) +#define BIT_FS_GPIOF_INT_EN_V1 BIT(15) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO2_INT_EN BIT(14) +#define BIT_FS_GPIO2_INT_EN BIT(14) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOE_INT_EN_V1 BIT(14) +#define BIT_FS_GPIOE_INT_EN_V1 BIT(14) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO1_INT_EN BIT(13) +#define BIT_FS_GPIO1_INT_EN BIT(13) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOD_INT_EN_V1 BIT(13) +#define BIT_FS_GPIOD_INT_EN_V1 BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO0_INT_EN BIT(12) +#define BIT_FS_GPIO0_INT_EN BIT(12) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOC_INT_EN_V1 BIT(12) +#define BIT_FS_GPIOC_INT_EN_V1 BIT(12) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_HCI_SUS_EN BIT(11) +#define BIT_FS_HCI_SUS_EN BIT(11) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOB_INT_EN_V1 BIT(11) +#define BIT_FS_GPIOB_INT_EN_V1 BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_HCI_RES_EN BIT(10) +#define BIT_FS_HCI_RES_EN BIT(10) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOA_INT_EN_V1 BIT(10) +#define BIT_FS_GPIOA_INT_EN_V1 BIT(10) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_HCI_RESET_EN BIT(9) +#define BIT_FS_HCI_RESET_EN BIT(9) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO9_INT_EN_V1 BIT(9) +#define BIT_FS_GPIO9_INT_EN_V1 BIT(9) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_AXI_EXCEPT_FINT_EN BIT(8) +#define BIT_AXI_EXCEPT_FINT_EN BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO8_INT_EN_V1 BIT(8) +#define BIT_FS_GPIO8_INT_EN_V1 BIT(8) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_USB_SCSI_CMD_EN BIT(8) +#define BIT_USB_SCSI_CMD_EN BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7) +#define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO7_INT_EN_V1 BIT(7) +#define BIT_FS_GPIO7_INT_EN_V1 BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6) +#define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO6_INT_EN_V1 BIT(6) +#define BIT_FS_GPIO6_INT_EN_V1 BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_TRPC_TO_INT_EN BIT(5) +#define BIT_FS_TRPC_TO_INT_EN BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -/* 2 REG_FSIMR (Offset 0x0050) */ - -#define BIT_FS_GPIO5_INT_EN_V1 BIT(5) - -#endif - - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_GEN1GEN2_SWITCH BIT(5) +#define BIT_FS_GPIO5_INT_EN_V1 BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_RPC_O_T_INT_EN BIT(4) +#define BIT_FS_RPC_O_T_INT_EN BIT(4) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO4_INT_EN_V1 BIT(4) +#define BIT_FS_GPIO4_INT_EN_V1 BIT(4) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_HCI_TXDMA_REQ_HIMR BIT(4) +#define BIT_HCI_TXDMA_REQ_HIMR BIT(4) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3) +#define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO3_INT_EN_V1 BIT(3) +#define BIT_FS_GPIO3_INT_EN_V1 BIT(3) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_32K_ENTER_SETTING_MAK BIT(2) +#define BIT_FS_32K_ENTER_SETTING_MAK BIT(2) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO2_INT_EN_V1 BIT(2) +#define BIT_FS_GPIO2_INT_EN_V1 BIT(2) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_USB_LPMRSM_MSK BIT(1) +#define BIT_FS_USB_LPMRSM_MSK BIT(1) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO1_INT_EN_V1 BIT(1) +#define BIT_FS_GPIO1_INT_EN_V1 BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_USB_LPMINT_MSK BIT(0) +#define BIT_FS_USB_LPMINT_MSK BIT(0) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO0_INT_EN_V1 BIT(0) +#define BIT_FS_GPIO0_INT_EN_V1 BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_PDNINT BIT(31) +#define BIT_FS_PDNINT BIT(31) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_SPS_OCP_INT BIT(29) +#define BIT_FS_SPS_OCP_INT BIT(29) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_SW_SPS_OCP_INT BIT(29) +#define BIT_SW_SPS_OCP_INT BIT(29) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_PWMERR_INT BIT(28) +#define BIT_FS_PWMERR_INT BIT(28) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_PWM_HW_ERR BIT(28) +#define BIT_FS_PWM_HW_ERR BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOF_INT BIT(27) -#define BIT_FS_GPIOE_INT BIT(26) -#define BIT_FS_GPIOD_INT BIT(25) -#define BIT_FS_GPIOC_INT BIT(24) +#define BIT_FS_GPIOF_INT BIT(27) +#define BIT_FS_GPIOE_INT BIT(26) +#define BIT_FS_GPIOD_INT BIT(25) +#define BIT_FS_GPIOC_INT BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_ACT2RECOVERY_INT BIT(24) +#define BIT_ACT2RECOVERY_INT BIT(24) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOB_INT BIT(23) +#define BIT_FS_GPIOB_INT BIT(23) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_PCIE_GEN12_SWITH BIT(23) +#define BIT_PCIE_GEN12_SWITCH BIT(23) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOA_INT BIT(22) +#define BIT_FS_GPIOA_INT BIT(22) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_HCI_SUS_V1 BIT(22) +#define BIT_FS_HCI_SUS_V1 BIT(22) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO9_INT BIT(21) +#define BIT_FS_GPIO9_INT BIT(21) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_HCI_RES_V1 BIT(21) +#define BIT_FS_HCI_RES_V1 BIT(21) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO8_INT BIT(20) +#define BIT_FS_GPIO8_INT BIT(20) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_HCI_RESET_V1 BIT(20) +#define BIT_FS_HCI_RESET_V1 BIT(20) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO7_INT BIT(19) +#define BIT_FS_GPIO7_INT BIT(19) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_32K_LEAVE_SETTING BIT(19) +#define BIT_FS_32K_LEAVE_SETTING BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO6_INT BIT(18) +#define BIT_FS_GPIO6_INT BIT(18) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_32K_ENTER_SETTING BIT(18) +#define BIT_FS_32K_ENTER_SETTING BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO5_INT BIT(17) +#define BIT_FS_GPIO5_INT BIT(17) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_SIE_LPM_RSM_V1 BIT(17) +#define BIT_FS_SIE_LPM_RSM_V1 BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO4_INT BIT(16) +#define BIT_FS_GPIO4_INT BIT(16) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_SIE_LPM_ACT_V1 BIT(16) +#define BIT_FS_SIE_LPM_ACT_V1 BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO3_INT BIT(15) +#define BIT_FS_GPIO3_INT BIT(15) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOF_INT_V1 BIT(15) +#define BIT_FS_GPIOF_INT_V1 BIT(15) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO2_INT BIT(14) +#define BIT_FS_GPIO2_INT BIT(14) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOE_INT_V1 BIT(14) +#define BIT_FS_GPIOE_INT_V1 BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FSISR (Offset 0x0054) */ - -/* 2 REG_FSISR (Offset 0x0054) */ - -#define BIT_FS_GPIO1_INT BIT(13) +#define BIT_FS_GPIO1_INT BIT(13) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOD_INT_V1 BIT(13) +#define BIT_FS_GPIOD_INT_V1 BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO0_INT BIT(12) +#define BIT_FS_GPIO0_INT BIT(12) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOC_INT_V1 BIT(12) +#define BIT_FS_GPIOC_INT_V1 BIT(12) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_HCI_SUS_INT BIT(11) +#define BIT_FS_HCI_SUS_INT BIT(11) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOB_INT_V1 BIT(11) +#define BIT_FS_GPIOB_INT_V1 BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_HCI_RES_INT BIT(10) +#define BIT_FS_HCI_RES_INT BIT(10) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -/* 2 REG_FSISR (Offset 0x0054) */ - -#define BIT_FS_GPIOA_INT_V1 BIT(10) - -#endif - - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_HCI_RESET_INT BIT(9) +#define BIT_FS_GPIOA_INT_V1 BIT(10) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_R_8051_SPD BIT(9) +#define BIT_FS_HCI_RESET_INT BIT(9) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO9_INT_V1 BIT(9) +#define BIT_FS_GPIO9_INT_V1 BIT(9) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_AXI_EXCEPT_FINT BIT(8) +#define BIT_AXI_EXCEPT_FINT BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -/* 2 REG_FSISR (Offset 0x0054) */ - -#define BIT_FS_GPIO8_INT_V1 BIT(8) - -#endif - - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_USB_SCSI_CMD_INT BIT(8) +#define BIT_FS_GPIO8_INT_V1 BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_RAM_DL_SEL BIT(7) +#define BIT_USB_SCSI_CMD_INT BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_BTON_STS_UPDATE_INT BIT(7) +#define BIT_FS_BTON_STS_UPDATE_INT BIT(7) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -/* 2 REG_FSISR (Offset 0x0054) */ - -#define BIT_FS_GPIO7_INT_V1 BIT(7) - -#endif - - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_WINTINI_RDY BIT(6) +#define BIT_FS_GPIO7_INT_V1 BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_ACT2RECOVERY_INT_V1 BIT(6) +#define BIT_ACT2RECOVERY_INT_V1 BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO6_INT_V1 BIT(6) +#define BIT_FS_GPIO6_INT_V1 BIT(6) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_ACT2RECOVERY BIT(6) +#define BIT_ACT2RECOVERY BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_TRPC_TO_INT_INT BIT(5) +#define BIT_FS_TRPC_TO_INT_INT BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO5_INT_V1 BIT(5) +#define BIT_FS_GPIO5_INT_V1 BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_RPC_O_T_INT_INT BIT(4) +#define BIT_FS_RPC_O_T_INT_INT BIT(4) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO4_INT_V1 BIT(4) +#define BIT_FS_GPIO4_INT_V1 BIT(4) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_HCI_TXDMA_REQ_HISR BIT(4) +#define BIT_HCI_TXDMA_REQ_HISR BIT(4) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_32K_LEAVE_SETTING_INT BIT(3) +#define BIT_FS_32K_LEAVE_SETTING_INT BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO3_INT_V1 BIT(3) +#define BIT_FS_GPIO3_INT_V1 BIT(3) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_32K_ENTER_SETTING_INT BIT(2) +#define BIT_FS_32K_ENTER_SETTING_INT BIT(2) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO2_INT_V1 BIT(2) +#define BIT_FS_GPIO2_INT_V1 BIT(2) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_USB_LPMRSM_INT BIT(1) +#define BIT_FS_USB_LPMRSM_INT BIT(1) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO1_INT_V1 BIT(1) +#define BIT_FS_GPIO1_INT_V1 BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_USB_LPMINT_INT BIT(0) +#define BIT_FS_USB_LPMINT_INT BIT(0) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO0_INT_V1 BIT(0) +#define BIT_FS_GPIO0_INT_V1 BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_GPIOF_INT_EN BIT(31) -#define BIT_GPIOE_INT_EN BIT(30) -#define BIT_GPIOD_INT_EN BIT(29) -#define BIT_GPIOC_INT_EN BIT(28) -#define BIT_GPIOB_INT_EN BIT(27) -#define BIT_GPIOA_INT_EN BIT(26) -#define BIT_GPIO9_INT_EN BIT(25) -#define BIT_GPIO8_INT_EN BIT(24) -#define BIT_GPIO7_INT_EN BIT(23) -#define BIT_GPIO6_INT_EN BIT(22) -#define BIT_GPIO5_INT_EN BIT(21) -#define BIT_GPIO4_INT_EN BIT(20) -#define BIT_GPIO3_INT_EN BIT(19) +#define BIT_GPIOF_INT_EN BIT(31) +#define BIT_GPIOE_INT_EN BIT(30) +#define BIT_GPIOD_INT_EN BIT(29) +#define BIT_GPIOC_INT_EN BIT(28) +#define BIT_GPIOB_INT_EN BIT(27) +#define BIT_GPIOA_INT_EN BIT(26) +#define BIT_GPIO9_INT_EN BIT(25) +#define BIT_GPIO8_INT_EN BIT(24) +#define BIT_GPIO7_INT_EN BIT(23) +#define BIT_GPIO6_INT_EN BIT(22) +#define BIT_GPIO5_INT_EN BIT(21) +#define BIT_GPIO4_INT_EN BIT(20) +#define BIT_GPIO3_INT_EN BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_GPIO2_INT_EN BIT(18) +#define BIT_GPIO2_INT_EN BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_GPIO1_INT_EN BIT(17) -#define BIT_GPIO0_INT_EN BIT(16) +#define BIT_GPIO2_INT_EN_V1 BIT(18) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_GPIO2_INT_EN_V1 BIT(16) +#define BIT_GPIO1_INT_EN BIT(17) +#define BIT_GPIO0_INT_EN BIT(16) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_AXI_EXCEPT_HINT_EN BIT(9) -#define BIT_PDNINT_EN_V2 BIT(8) +#define BIT_AXI_EXCEPT_HINT_EN BIT(9) +#define BIT_PDNINT_EN_V2 BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_PDNINT_EN BIT(7) +#define BIT_PDNINT_EN BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_PDNINT_EN_V1 BIT(7) +#define BIT_PDNINT_EN_V1 BIT(7) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_PDN_INT_EN BIT(7) +#define BIT_PDN_INT_EN BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_RON_INT_EN BIT(6) +#define BIT_RON_INT_EN BIT(6) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_RON_INT_EN_V1 BIT(6) +#define BIT_RON_INT_EN_V1 BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_SPS_OCP_INT_EN BIT(5) +#define BIT_SPS_OCP_INT_EN BIT(5) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_SPS_OCP_INT_EN_V1 BIT(5) +#define BIT_SPS_OCP_INT_EN_V1 BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_GPIO15_0_INT_EN BIT(0) +#define BIT_GPIO15_0_INT_EN BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_GPIO15_0_INT_EN_V1 BIT(0) +#define BIT_GPIO15_0_INT_EN_V1 BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_GPIOF_INT BIT(31) -#define BIT_GPIOE_INT BIT(30) -#define BIT_GPIOD_INT BIT(29) -#define BIT_GPIOC_INT BIT(28) -#define BIT_GPIOB_INT BIT(27) -#define BIT_GPIOA_INT BIT(26) -#define BIT_GPIO9_INT BIT(25) -#define BIT_GPIO8_INT BIT(24) -#define BIT_GPIO7_INT BIT(23) +#define BIT_GPIOF_INT BIT(31) +#define BIT_GPIOE_INT BIT(30) +#define BIT_GPIOD_INT BIT(29) +#define BIT_GPIOC_INT BIT(28) +#define BIT_GPIOB_INT BIT(27) +#define BIT_GPIOA_INT BIT(26) +#define BIT_GPIO9_INT BIT(25) +#define BIT_GPIO8_INT BIT(24) +#define BIT_GPIO7_INT BIT(23) +#define BIT_GPIO6_INT BIT(22) +#define BIT_GPIO5_INT BIT(21) +#define BIT_GPIO4_INT BIT(20) +#define BIT_GPIO3_INT BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_CPRST BIT(23) +#define BIT_GPIO2_INT BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_GPIO6_INT BIT(22) -#define BIT_GPIO5_INT BIT(21) -#define BIT_GPIO4_INT BIT(20) -#define BIT_GPIO3_INT BIT(19) +#define BIT_GPIO2_INT_V1 BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_GPIO2_INT BIT(18) +#define BIT_GPIO1_INT BIT(17) +#define BIT_GPIO0_INT BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_GPIO1_INT BIT(17) -#define BIT_GPIO0_INT BIT(16) +#define BIT_AXI_EXCEPT_HINT BIT(8) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_GPIO2_INT_V1 BIT(16) +#define BIT_PDNINT BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ +#define BIT_PDNINT_V1 BIT(7) -#define BIT_SHIFT_NPQ_AVAL_PG 8 -#define BIT_MASK_NPQ_AVAL_PG 0xff -#define BIT_NPQ_AVAL_PG(x) (((x) & BIT_MASK_NPQ_AVAL_PG) << BIT_SHIFT_NPQ_AVAL_PG) -#define BIT_GET_NPQ_AVAL_PG(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG) & BIT_MASK_NPQ_AVAL_PG) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_HSISR (Offset 0x005C) */ +#define BIT_PDN_INT BIT(7) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_AXI_EXCEPT_HINT BIT(8) +#define BIT_RON_INT BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_PDNINT BIT(7) +#define BIT_RON_INT_V1 BIT(6) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_PDNINT_V1 BIT(7) +#define BIT_SPS_OCP_INT BIT(5) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_PDN_INT BIT(7) +#define BIT_SPS_OCP_INT_V1 BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_RON_INT BIT(6) +#define BIT_GPIO15_0_INT BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_RON_INT_V1 BIT(6) +#define BIT_GPIO15_0_INT_V1 BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */ +#define BIT_SHIFT_GPIO_MOD_15_TO_8 24 +#define BIT_MASK_GPIO_MOD_15_TO_8 0xff +#define BIT_GPIO_MOD_15_TO_8(x) \ + (((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8) +#define BITS_GPIO_MOD_15_TO_8 \ + (BIT_MASK_GPIO_MOD_15_TO_8 << BIT_SHIFT_GPIO_MOD_15_TO_8) +#define BIT_CLEAR_GPIO_MOD_15_TO_8(x) ((x) & (~BITS_GPIO_MOD_15_TO_8)) +#define BIT_GET_GPIO_MOD_15_TO_8(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8) +#define BIT_SET_GPIO_MOD_15_TO_8(x, v) \ + (BIT_CLEAR_GPIO_MOD_15_TO_8(x) | BIT_GPIO_MOD_15_TO_8(v)) + +#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16 +#define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff +#define BIT_GPIO_IO_SEL_15_TO_8(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8) +#define BITS_GPIO_IO_SEL_15_TO_8 \ + (BIT_MASK_GPIO_IO_SEL_15_TO_8 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) ((x) & (~BITS_GPIO_IO_SEL_15_TO_8)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8) +#define BIT_SET_GPIO_IO_SEL_15_TO_8(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) | BIT_GPIO_IO_SEL_15_TO_8(v)) + +#define BIT_SHIFT_GPIO_OUT_15_TO_8 8 +#define BIT_MASK_GPIO_OUT_15_TO_8 0xff +#define BIT_GPIO_OUT_15_TO_8(x) \ + (((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8) +#define BITS_GPIO_OUT_15_TO_8 \ + (BIT_MASK_GPIO_OUT_15_TO_8 << BIT_SHIFT_GPIO_OUT_15_TO_8) +#define BIT_CLEAR_GPIO_OUT_15_TO_8(x) ((x) & (~BITS_GPIO_OUT_15_TO_8)) +#define BIT_GET_GPIO_OUT_15_TO_8(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8) +#define BIT_SET_GPIO_OUT_15_TO_8(x, v) \ + (BIT_CLEAR_GPIO_OUT_15_TO_8(x) | BIT_GPIO_OUT_15_TO_8(v)) + +#define BIT_SHIFT_GPIO_IN_15_TO_8 0 +#define BIT_MASK_GPIO_IN_15_TO_8 0xff +#define BIT_GPIO_IN_15_TO_8(x) \ + (((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8) +#define BITS_GPIO_IN_15_TO_8 \ + (BIT_MASK_GPIO_IN_15_TO_8 << BIT_SHIFT_GPIO_IN_15_TO_8) +#define BIT_CLEAR_GPIO_IN_15_TO_8(x) ((x) & (~BITS_GPIO_IN_15_TO_8)) +#define BIT_GET_GPIO_IN_15_TO_8(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8) +#define BIT_SET_GPIO_IN_15_TO_8(x, v) \ + (BIT_CLEAR_GPIO_IN_15_TO_8(x) | BIT_GPIO_IN_15_TO_8(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_HSISR (Offset 0x005C) */ +/* 2 REG_SDIO_H2C (Offset 0x10250060) */ -#define BIT_SPS_OCP_INT BIT(5) +#define BIT_SHIFT_SDIO_H2C_MSG 0 +#define BIT_MASK_SDIO_H2C_MSG 0xffffffffL +#define BIT_SDIO_H2C_MSG(x) \ + (((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG) +#define BITS_SDIO_H2C_MSG (BIT_MASK_SDIO_H2C_MSG << BIT_SHIFT_SDIO_H2C_MSG) +#define BIT_CLEAR_SDIO_H2C_MSG(x) ((x) & (~BITS_SDIO_H2C_MSG)) +#define BIT_GET_SDIO_H2C_MSG(x) \ + (((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG) +#define BIT_SET_SDIO_H2C_MSG(x, v) \ + (BIT_CLEAR_SDIO_H2C_MSG(x) | BIT_SDIO_H2C_MSG(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_DATA_CPU_JTAG BIT(30) -/* 2 REG_HSISR (Offset 0x005C) */ +#endif -#define BIT_SPS_OCP_INT_V1 BIT(5) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_PAPE_WLBT_SEL BIT(29) +#define BIT_LNAON_WLBT_SEL BIT(28) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_HSISR (Offset 0x005C) */ +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_GPIO15_0_INT BIT(0) -#define BIT_MCUFWDL_EN BIT(0) +#define BIT_BDEN BIT(28) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_BT_BQB_GPIO_SEL BIT(27) -/* 2 REG_HSISR (Offset 0x005C) */ +#endif -#define BIT_GPIO15_0_INT_V1 BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_BTGP_GPG3_FEN BIT(26) +#define BIT_BTGP_GPG2_FEN BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */ +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_BTGP_JTAG_EN BIT(24) -#define BIT_SHIFT_GPIO_MOD_15_TO_8 24 -#define BIT_MASK_GPIO_MOD_15_TO_8 0xff -#define BIT_GPIO_MOD_15_TO_8(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8) -#define BIT_GET_GPIO_MOD_15_TO_8(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16 -#define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff -#define BIT_GPIO_IO_SEL_15_TO_8(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8) -#define BIT_GET_GPIO_IO_SEL_15_TO_8(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_BB2PP_ISO BIT(24) -#define BIT_SHIFT_GPIO_OUT_15_TO_8 8 -#define BIT_MASK_GPIO_OUT_15_TO_8 0xff -#define BIT_GPIO_OUT_15_TO_8(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8) -#define BIT_GET_GPIO_OUT_15_TO_8(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_GPIO_IN_15_TO_8 0 -#define BIT_MASK_GPIO_IN_15_TO_8 0xff -#define BIT_GPIO_IN_15_TO_8(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8) -#define BIT_GET_GPIO_IN_15_TO_8(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_XTAL_CLK_EXTARNAL_EN BIT(23) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_BTBRI_UART_EN BIT(22) -/* 2 REG_SDIO_H2C (Offset 0x10250060) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SDIO_H2C_MSG 0 -#define BIT_MASK_SDIO_H2C_MSG 0xffffffffL -#define BIT_SDIO_H2C_MSG(x) (((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG) -#define BIT_GET_SDIO_H2C_MSG(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_BTGP_UART0_EN BIT(22) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAPE_WLBT_SEL BIT(29) -#define BIT_LNAON_WLBT_SEL BIT(28) +#define BIT_BTGP_UART1_EN BIT(21) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BDEN BIT(28) +#define BIT_BTCOEX_PU BIT(21) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_GPG3_FEN BIT(26) -#define BIT_BTGP_GPG2_FEN BIT(25) +#define BIT_BTGP_SPI_EN BIT(20) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_JTAG_EN BIT(24) +#define BIT_EEPROM_SEL_PD BIT(20) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BB2PP_ISO BIT(24) +#define BIT_BTGP_GPIO_E2 BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_XTAL_CLK_EXTARNAL_EN BIT(23) +#define BIT_TST_MOD_PD BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTBRI_UART_EN BIT(22) +#define BIT_BTGP_GPIO_EN BIT(18) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_UART0_EN BIT(22) +#define BIT_BOOT_FLUSH_PD BIT(18) +#define BIT_USB_XTAL_SEL1_PD BIT(17) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_UART1_EN BIT(21) +#define BIT_SHIFT_BTGP_GPIO_SL 16 +#define BIT_MASK_BTGP_GPIO_SL 0x3 +#define BIT_BTGP_GPIO_SL(x) \ + (((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL) +#define BITS_BTGP_GPIO_SL (BIT_MASK_BTGP_GPIO_SL << BIT_SHIFT_BTGP_GPIO_SL) +#define BIT_CLEAR_BTGP_GPIO_SL(x) ((x) & (~BITS_BTGP_GPIO_SL)) +#define BIT_GET_BTGP_GPIO_SL(x) \ + (((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL) +#define BIT_SET_BTGP_GPIO_SL(x, v) \ + (BIT_CLEAR_BTGP_GPIO_SL(x) | BIT_BTGP_GPIO_SL(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTCOEX_PU BIT(21) +#define BIT_USB_XTAL_SEL0_PD BIT(16) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_SPI_EN BIT(20) +#define BIT_HST_WKE_DEV_SL BIT(15) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_EEPROM_SEL_PD BIT(20) +#define BIT_BTSUSB_PL BIT(15) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_GPIO_E2 BIT(19) +#define BIT_WL_JTAG BIT(15) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_TST_MOD_PD BIT(19) +#define BIT_PAD_SDIO_SR BIT(14) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_GPIO_EN BIT(18) +#define BIT_GPIO14_OUTPUT_PL BIT(13) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BOOT_FLUSH_PD BIT(18) -#define BIT_USB_XTAL_SEL1_PD BIT(17) +#define BIT_SW_DEVWHOST_POLARITY BIT(13) #endif +#if (HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_GPIO15_OUTPUT_PL BIT(13) -/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BTGP_GPIO_SL 16 -#define BIT_MASK_BTGP_GPIO_SL 0x3 -#define BIT_BTGP_GPIO_SL(x) (((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL) -#define BIT_GET_BTGP_GPIO_SL(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_HOST_WAKE_PAD_PULL_EN BIT(12) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_USB_XTAL_SEL0_PD BIT(16) +#define BIT_HOST_WAKE_DEV_PLL_EN BIT(12) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_HST_WKE_DEV_SL BIT(15) +#define BIT_HOST_WAKE_PAD_SL BIT(11) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTSUSB_PL BIT(15) +#define BIT_HOST_WAKE_DEV_POLARITY BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_SDIO_SR BIT(14) +#define BIT_PAD_TRSW_SR BIT(10) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_GPIO14_OUTPUT_PL BIT(13) +#define BIT_PAD_LNAON_SR BIT(10) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_DEVWHOST_POLARITY BIT(13) +#define BIT_PAD_TRSW_E2 BIT(9) #endif - -#if (HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_GPIO15_OUTPUT_PL BIT(13) +#define BIT_PAD_LNAON_E2 BIT(9) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_HOST_WAKE_PAD_PULL_EN BIT(12) +#define BIT_A_ANTSEL_SR BIT(9) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_HOST_WAKE_DEV_PLL_EN BIT(12) +#define BIT_SW_TRSW_P_SEL_DATA BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_HOST_WAKE_PAD_SL BIT(11) +#define BIT_SW_LNAON_G_SEL_DATA BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_HOST_WAKE_DEV_POLARITY BIT(11) +#define BIT_A_ANTSEL_E2 BIT(8) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_TRSW_SR BIT(10) +#define BIT_SW_TRSW_N_SEL_DATA BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_LNAON_SR BIT(10) +#define BIT_SW_LNAON_A_SEL_DATA BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_TRSW_E2 BIT(9) +#define BIT_D_PAPE_2G_SR BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_LNAON_E2 BIT(9) +#define BIT_PAD_PAPE_SR BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ - -#define BIT_A_ANTSEL_SR BIT(9) - -#endif - - -#if (HALMAC_8192E_SUPPORT) - - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_TRSW_P_SEL_DATA BIT(8) +#define BIT_D_PAPE_5G_SR BIT(6) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_LNAON_G_SEL_DATA BIT(8) +#define BIT_PAD_PAPE_E2 BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_A_ANTSEL_E2 BIT(8) +#define BIT_D_TRSW_SR BIT(5) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_TRSW_N_SEL_DATA BIT(7) +#define BIT_SW_PAPE_1_SEL_DATA BIT(4) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_LNAON_A_SEL_DATA BIT(7) +#define BIT_SW_PAPE_G_SEL_DATA BIT(4) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_PAPE_2G_SR BIT(7) +#define BIT_D_TRSWB_SR BIT(4) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ - -#define BIT_PAD_PAPE_SR BIT(6) - -#endif - - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_PAPE_5G_SR BIT(6) +#define BIT_SW_PAPE_0_SEL_DATA BIT(3) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_PAPE_E2 BIT(5) +#define BIT_SW_PAPE_A_SEL_DATA BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_TRSW_SR BIT(5) +#define BIT_D_PAPE_2G_E2 BIT(3) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_PAPE_1_SEL_DATA BIT(4) +#define BIT_SW_ANTSEL_2_SEL_DATA BIT(2) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_PAPE_G_SEL_DATA BIT(4) +#define BIT_PAD_DPDT_SR BIT(2) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_TRSWB_SR BIT(4) +#define BIT_D_PAPE_5G_E2 BIT(2) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_PAPE_0_SEL_DATA BIT(3) +#define BIT_SW_ANTSEL_N_SEL_DATA BIT(1) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_PAPE_A_SEL_DATA BIT(3) +#define BIT_PAD_DPDT_PAD_E2 BIT(1) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ - -#define BIT_D_PAPE_2G_E2 BIT(3) - -#endif - - -#if (HALMAC_8192E_SUPPORT) - - -/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ - -#define BIT_SW_ANTSEL_2_SEL_DATA BIT(2) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_DPDT_SR BIT(2) +#define BIT_D_TRSW_E2 BIT(1) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_PAPE_5G_E2 BIT(2) +#define BIT_PAD_DPDT_E2 BIT(1) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_ANTSEL_N_SEL_DATA BIT(1) +#define BIT_SW_ANTSEL_P_SEL_DATA BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_DPDT_PAD_E2 BIT(1) +#define BIT_SW_DPDT_SEL_DATA BIT(0) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_TRSW_E2 BIT(1) +#define BIT_D_TRSWB_E2 BIT(0) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - - -/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +/* 2 REG_SDIO_C2H (Offset 0x10250064) */ -#define BIT_PAD_DPDT_E2 BIT(1) +#define BIT_SHIFT_SDIO_C2H_MSG 0 +#define BIT_MASK_SDIO_C2H_MSG 0xffffffffL +#define BIT_SDIO_C2H_MSG(x) \ + (((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG) +#define BITS_SDIO_C2H_MSG (BIT_MASK_SDIO_C2H_MSG << BIT_SHIFT_SDIO_C2H_MSG) +#define BIT_CLEAR_SDIO_C2H_MSG(x) ((x) & (~BITS_SDIO_C2H_MSG)) +#define BIT_GET_SDIO_C2H_MSG(x) \ + (((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG) +#define BIT_SET_SDIO_C2H_MSG(x, v) \ + (BIT_CLEAR_SDIO_C2H_MSG(x) | BIT_SDIO_C2H_MSG(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT) - - -/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_SW_ANTSEL_P_SEL_DATA BIT(0) +#define BIT_ISO_BD2PP BIT(31) +#define BIT_LDOV12B_EN BIT(30) +#define BIT_CKEN_BTGPS BIT(29) +#define BIT_FEN_BTGPS BIT(28) +#define BIT_BTCPU_BOOTSEL BIT(27) +#define BIT_SPI_SPEEDUP BIT(26) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_SW_DPDT_SEL_DATA BIT(0) +#define BIT_BT_SUS BIT(25) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_D_TRSWB_E2 BIT(0) +#define BIT_BT_LDO_MODE BIT(25) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ +#define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24) +#define BIT_CLKREQ_PAD_TYPE_SEL BIT(23) -/* 2 REG_SDIO_C2H (Offset 0x10250064) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SDIO_C2H_MSG 0 -#define BIT_MASK_SDIO_C2H_MSG 0xffffffffL -#define BIT_SDIO_C2H_MSG(x) (((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG) -#define BIT_GET_SDIO_C2H_MSG(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG) +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ +#define BIT_CKSL_BZSLP BIT(23) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_ISO_BD2PP BIT(31) -#define BIT_LDOV12B_EN BIT(30) -#define BIT_CKEN_BTGPS BIT(29) -#define BIT_FEN_BTGPS BIT(28) +#define BIT_EN_CPL_TIMEOUT_PS BIT(22) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_MULRW BIT(27) +#define BIT_BT_WAKE_HST_EN BIT(22) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BTCPU_BOOTSEL BIT(27) -#define BIT_SPI_SPEEDUP BIT(26) +#define BIT_ISO_BTPON2PP BIT(22) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24) -#define BIT_CLKREQ_PAD_TYPE_SEL BIT(23) +#define BIT_REG_TXDMA_FAIL_PS BIT(21) #endif - -#if (HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_CKSL_BZSLP BIT(23) +#define BIT_WAKE_BT_EN BIT(21) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_EN_CPL_TIMEOUT_PS BIT(22) +#define BIT_BTCOEX_CMD BIT(21) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_WAKE_HST_EN BIT(22) +#define BIT_EN_BT BIT(20) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_ISO_BTPON2PP BIT(22) +#define BIT_BT_UART_INTF BIT(20) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_REG_TXDMA_FAIL_PS BIT(21) +#define BIT_EN_HWENTR_L1 BIT(19) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WAKE_BT_EN BIT(21) -#define BIT_EN_BT BIT(20) +#define BIT_BT_SUSN_EN BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_EN_HWENTR_L1 BIT(19) +#define BIT_BT_HWROF_EN BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_SUSN_EN BIT(19) +#define BIT_S3_RF_HW_EN BIT(19) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_HWROF_EN BIT(19) +#define BIT_EN_ADV_CLKGATE BIT(18) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_S3_RF_HW_EN BIT(19) +#define BIT_BT_FUNC_EN BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_EN_ADV_CLKGATE BIT(18) +#define BIT_S2_RF_HW_EN BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_FUNC_EN BIT(18) +#define BIT_BT_HWPDN_SL BIT(17) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_S2_RF_HW_EN BIT(18) +#define BIT_S1_RF_HW_EN BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_HWPDN_SL BIT(17) +#define BIT_BT_DISN_EN BIT(16) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_S1_RF_HW_EN BIT(17) +#define BIT_S0_RF_HW_EN BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_DISN_EN BIT(16) +#define BIT_BT_PDN_PULL_EN BIT(15) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_S0_RF_HW_EN BIT(16) +#define BIT_WL_PDN_PULL_EN BIT(14) +#define BIT_EXTERNAL_REQUEST_PL BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_PDN_PULL_EN BIT(15) +#define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WL_PDN_PULL_EN BIT(14) -#define BIT_EXTERNAL_REQUEST_PL BIT(13) +#define BIT_ISO_BA2PP BIT(11) +#define BIT_BT_AFE_LDO_EN BIT(10) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12) +#define BIT_PDN_PIN_SEL BIT(10) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_ISO_BA2PP BIT(11) -#define BIT_BT_AFE_LDO_EN BIT(10) +#define BIT_GPIO11_PULL_LOW_EN BIT(9) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_PDN_PIN_SEL BIT(10) +#define BIT_BT_AFE_PLL_EN BIT(9) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_GPIO11_PULL_LOW_EN BIT(9) +#define BIT_GPIO4_PULL_LOW_EN BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_AFE_PLL_EN BIT(9) +#define BIT_BT_DIG_CLK_EN BIT(8) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_GPIO4_PULL_LOW_EN BIT(8) +#define BIT_BT_WAKE_HST_SL BIT(7) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ + +#define BIT_ASSERT_SPS_EN BIT(7) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_DIG_CLK_EN BIT(8) +#define BIT_UART_BRIDGE BIT(7) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_WAKE_HST_SL BIT(7) +#define BIT_WAKE_BT_SL BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_ASSERT_SPS_EN BIT(7) +#define BIT_MASK_CHIPEN BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WAKE_BT_SL BIT(6) +#define BIT_OSC32K_CTRL_SEL BIT(6) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_MASK_CHIPEN BIT(6) +#define BIT_WLAN_32K_SEL BIT(6) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WL_DRV_EXIST_IDX BIT(5) +#define BIT_WL_DRV_EXIST_IDX BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_ASSERT_RF_EN BIT(5) +#define BIT_ASSERT_RF_EN BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_DOP_EHPAD BIT(4) +#define BIT_DOP_EHPAD BIT(4) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BIT_DOP_EHPAD BIT(4) +#define BIT_BIT_DOP_EHPAD BIT(4) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WL_HWROF_EN BIT(3) +#define BIT_WL_HWROF_EN BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_SDIO_PAD_SHUTDOWNB BIT(3) +#define BIT_SDIO_PAD_SHUTDOWNB BIT(3) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WL_FUNC_EN BIT(2) +#define BIT_WL_FUNC_EN BIT(2) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_SDIO_CLK_SMT BIT(2) +#define BIT_SDIO_CLK_SMT BIT(2) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WL_HWPDN_SL BIT(1) -#define BIT_WL_HWPDN_EN BIT(0) +#define BIT_WL_HWPDN_SL BIT(1) +#define BIT_WL_HWPDN_EN BIT(0) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SDM_DEBUG (Offset 0x006C) */ - -#define BIT_SHIFT_F0N 23 -#define BIT_MASK_F0N 0x7 -#define BIT_F0N(x) (((x) & BIT_MASK_F0N) << BIT_SHIFT_F0N) -#define BIT_GET_F0N(x) (((x) >> BIT_SHIFT_F0N) & BIT_MASK_F0N) - +#define BIT_SHIFT_F0N 23 +#define BIT_MASK_F0N 0x7 +#define BIT_F0N(x) (((x) & BIT_MASK_F0N) << BIT_SHIFT_F0N) +#define BITS_F0N (BIT_MASK_F0N << BIT_SHIFT_F0N) +#define BIT_CLEAR_F0N(x) ((x) & (~BITS_F0N)) +#define BIT_GET_F0N(x) (((x) >> BIT_SHIFT_F0N) & BIT_MASK_F0N) +#define BIT_SET_F0N(x, v) (BIT_CLEAR_F0N(x) | BIT_F0N(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#define BIT_BT_WAKE_DEV_EN_V1 BIT(19) +#define BIT_BT_WAKE_HST_EN_V1 BIT(18) +#define BIT_BT_WAKE_HST_PL_V1 BIT(17) -/* 2 REG_GSSR (Offset 0x006C) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_GPIO_15_TO_0_VAL 16 -#define BIT_MASK_GPIO_15_TO_0_VAL 0xffff -#define BIT_GPIO_15_TO_0_VAL(x) (((x) & BIT_MASK_GPIO_15_TO_0_VAL) << BIT_SHIFT_GPIO_15_TO_0_VAL) -#define BIT_GET_GPIO_15_TO_0_VAL(x) (((x) >> BIT_SHIFT_GPIO_15_TO_0_VAL) & BIT_MASK_GPIO_15_TO_0_VAL) +/* 2 REG_GSSR (Offset 0x006C) */ +#define BIT_SHIFT_GPIO_15_TO_0_VAL 16 +#define BIT_MASK_GPIO_15_TO_0_VAL 0xffff +#define BIT_GPIO_15_TO_0_VAL(x) \ + (((x) & BIT_MASK_GPIO_15_TO_0_VAL) << BIT_SHIFT_GPIO_15_TO_0_VAL) +#define BITS_GPIO_15_TO_0_VAL \ + (BIT_MASK_GPIO_15_TO_0_VAL << BIT_SHIFT_GPIO_15_TO_0_VAL) +#define BIT_CLEAR_GPIO_15_TO_0_VAL(x) ((x) & (~BITS_GPIO_15_TO_0_VAL)) +#define BIT_GET_GPIO_15_TO_0_VAL(x) \ + (((x) >> BIT_SHIFT_GPIO_15_TO_0_VAL) & BIT_MASK_GPIO_15_TO_0_VAL) +#define BIT_SET_GPIO_15_TO_0_VAL(x, v) \ + (BIT_CLEAR_GPIO_15_TO_0_VAL(x) | BIT_GPIO_15_TO_0_VAL(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#define BIT_BT_CLKREQ_EN_V1 BIT(16) -/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_F0F 10 -#define BIT_MASK_F0F 0x1fff -#define BIT_F0F(x) (((x) & BIT_MASK_F0F) << BIT_SHIFT_F0F) -#define BIT_GET_F0F(x) (((x) >> BIT_SHIFT_F0F) & BIT_MASK_F0F) +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#define BIT_SHIFT_F0F 10 +#define BIT_MASK_F0F 0x1fff +#define BIT_F0F(x) (((x) & BIT_MASK_F0F) << BIT_SHIFT_F0F) +#define BITS_F0F (BIT_MASK_F0F << BIT_SHIFT_F0F) +#define BIT_CLEAR_F0F(x) ((x) & (~BITS_F0F)) +#define BIT_GET_F0F(x) (((x) >> BIT_SHIFT_F0F) & BIT_MASK_F0F) +#define BIT_SET_F0F(x, v) (BIT_CLEAR_F0F(x) | BIT_F0F(v)) -#define BIT_SHIFT_DIVN 4 -#define BIT_MASK_DIVN 0x3f -#define BIT_DIVN(x) (((x) & BIT_MASK_DIVN) << BIT_SHIFT_DIVN) -#define BIT_GET_DIVN(x) (((x) >> BIT_SHIFT_DIVN) & BIT_MASK_DIVN) +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM 0 -#define BIT_MASK_BB_DBG_SEL_AFE_SDM 0xf -#define BIT_BB_DBG_SEL_AFE_SDM(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM) -#define BIT_GET_BB_DBG_SEL_AFE_SDM(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM) & BIT_MASK_BB_DBG_SEL_AFE_SDM) +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#define BIT_GPIO_IE_V18 BIT(10) +#define BIT_PCIE_IE_V18 BIT(9) +#define BIT_UART_IE_V18 BIT(8) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_DIVN 4 +#define BIT_MASK_DIVN 0x3f +#define BIT_DIVN(x) (((x) & BIT_MASK_DIVN) << BIT_SHIFT_DIVN) +#define BITS_DIVN (BIT_MASK_DIVN << BIT_SHIFT_DIVN) +#define BIT_CLEAR_DIVN(x) ((x) & (~BITS_DIVN)) +#define BIT_GET_DIVN(x) (((x) >> BIT_SHIFT_DIVN) & BIT_MASK_DIVN) +#define BIT_SET_DIVN(x, v) (BIT_CLEAR_DIVN(x) | BIT_DIVN(v)) +#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM 0 +#define BIT_MASK_BB_DBG_SEL_AFE_SDM 0xf +#define BIT_BB_DBG_SEL_AFE_SDM(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM) +#define BITS_BB_DBG_SEL_AFE_SDM \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM << BIT_SHIFT_BB_DBG_SEL_AFE_SDM) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM) & BIT_MASK_BB_DBG_SEL_AFE_SDM) +#define BIT_SET_BB_DBG_SEL_AFE_SDM(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) | BIT_BB_DBG_SEL_AFE_SDM(v)) -/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WLCLK_PHASE 0 -#define BIT_MASK_WLCLK_PHASE 0x1f -#define BIT_WLCLK_PHASE(x) (((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE) -#define BIT_GET_WLCLK_PHASE(x) (((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE) +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#define BIT_SHIFT_WLCLK_PHASE 0 +#define BIT_MASK_WLCLK_PHASE 0x1f +#define BIT_WLCLK_PHASE(x) \ + (((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE) +#define BITS_WLCLK_PHASE (BIT_MASK_WLCLK_PHASE << BIT_SHIFT_WLCLK_PHASE) +#define BIT_CLEAR_WLCLK_PHASE(x) ((x) & (~BITS_WLCLK_PHASE)) +#define BIT_GET_WLCLK_PHASE(x) \ + (((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE) +#define BIT_SET_WLCLK_PHASE(x, v) \ + (BIT_CLEAR_WLCLK_PHASE(x) | BIT_WLCLK_PHASE(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GSSR (Offset 0x006C) */ +#define BIT_SHIFT_GPIO_15_TO_0_EN 0 +#define BIT_MASK_GPIO_15_TO_0_EN 0xffff +#define BIT_GPIO_15_TO_0_EN(x) \ + (((x) & BIT_MASK_GPIO_15_TO_0_EN) << BIT_SHIFT_GPIO_15_TO_0_EN) +#define BITS_GPIO_15_TO_0_EN \ + (BIT_MASK_GPIO_15_TO_0_EN << BIT_SHIFT_GPIO_15_TO_0_EN) +#define BIT_CLEAR_GPIO_15_TO_0_EN(x) ((x) & (~BITS_GPIO_15_TO_0_EN)) +#define BIT_GET_GPIO_15_TO_0_EN(x) \ + (((x) >> BIT_SHIFT_GPIO_15_TO_0_EN) & BIT_MASK_GPIO_15_TO_0_EN) +#define BIT_SET_GPIO_15_TO_0_EN(x, v) \ + (BIT_CLEAR_GPIO_15_TO_0_EN(x) | BIT_GPIO_15_TO_0_EN(v)) -#define BIT_SHIFT_GPIO_15_TO_0_EN 0 -#define BIT_MASK_GPIO_15_TO_0_EN 0xffff -#define BIT_GPIO_15_TO_0_EN(x) (((x) & BIT_MASK_GPIO_15_TO_0_EN) << BIT_SHIFT_GPIO_15_TO_0_EN) -#define BIT_GET_GPIO_15_TO_0_EN(x) (((x) >> BIT_SHIFT_GPIO_15_TO_0_EN) & BIT_MASK_GPIO_15_TO_0_EN) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_BBRSTB_STANDBY_V1 BIT(28) -/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_BBRSTB_STANDBY_V1 BIT(28) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ + +#define BIT_DBG_GNT_WL_BT BIT(27) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SYS_CLKR (Offset 0x0070) */ + +#define BIT_AFE_PORT3_ISO BIT(27) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_DBG_GNT_WL_BT BIT(27) +#define BIT_LTE_MUX_CTRL_PATH BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_AFE_PORT3_ISO BIT(27) +#define BIT_AFE_PORT2_ISO BIT(26) +#define BIT_AFE_PORT1_ISO BIT(25) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_LTE_MUX_CTRL_PATH BIT(26) +#define BIT_LTE_COEX_UART BIT(25) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_AFE_PORT2_ISO BIT(26) -#define BIT_AFE_PORT1_ISO BIT(25) +#define BIT_AFE_PORT0_ISO BIT(24) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_LTE_COEX_UART BIT(25) +#define BIT_3W_LTE_WL_GPIO BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_AFE_PORT0_ISO BIT(24) +#define BIT_USB_PWR_OFF_SEL BIT(23) +#define BIT_USB_HOST_PWR_OFF_EN_V1 BIT(22) +#define BIT_SYM_LPS_BLOCK_EN_V1 BIT(21) +#define BIT_USB_LPM_ACT_EN_V1 BIT(20) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_SDIO_INT_POLARITY BIT(19) +#define BIT_SDIO_INT BIT(18) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_3W_LTE_WL_GPIO BIT(24) +#define BIT_SDIO_OFF_EN BIT(17) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_USB_PWR_OFF_SEL BIT(23) -#define BIT_USB_HOST_PWR_OFF_EN_V1 BIT(22) -#define BIT_SYM_LPS_BLOCK_EN_V1 BIT(21) -#define BIT_USB_LPM_ACT_EN_V1 BIT(20) +#define BIT_SDIO_OFF_EN_V1 BIT(17) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_SDIO_INT_POLARITY BIT(19) -#define BIT_SDIO_INT BIT(18) +#define BIT_SDIO_ON_EN BIT(16) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SYS_CLKR (Offset 0x0070) */ + +#define BIT_SDIO_ON_EN_V1 BIT(16) +#define BIT_DIS_U3MB_INU2 BIT(13) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_SDIO_OFF_EN BIT(17) +#define BIT_PCIE_FORCE_PWR_NGAT BIT(13) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_SDIO_OFF_EN_V1 BIT(17) +#define BIT_USB3_MDIO_EN BIT(12) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_PCIE_CALIB_EN_V1 BIT(12) -/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_SDIO_ON_EN BIT(16) +#define BIT_USB3_BG_EN BIT(11) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ + +#define BIT_PAGE3_AUXCLK_GATE BIT(11) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_SDIO_ON_EN_V1 BIT(16) -#define BIT_DIS_U3MB_INU2 BIT(13) -#define BIT_USB3_MDIO_EN BIT(12) -#define BIT_USB3_BG_EN BIT(11) -#define BIT_USB3_MB_EN BIT(10) +#define BIT_USB3_MB_EN BIT(10) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10) +#define BIT_PCIE_WAIT_TIME BIT(9) -/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10) -#define BIT_PCIE_WAIT_TIME BIT(9) +#define BIT_SHIFT_USB3_CK_MD 8 +#define BIT_MASK_USB3_CK_MD 0x3 +#define BIT_USB3_CK_MD(x) (((x) & BIT_MASK_USB3_CK_MD) << BIT_SHIFT_USB3_CK_MD) +#define BITS_USB3_CK_MD (BIT_MASK_USB3_CK_MD << BIT_SHIFT_USB3_CK_MD) +#define BIT_CLEAR_USB3_CK_MD(x) ((x) & (~BITS_USB3_CK_MD)) +#define BIT_GET_USB3_CK_MD(x) \ + (((x) >> BIT_SHIFT_USB3_CK_MD) & BIT_MASK_USB3_CK_MD) +#define BIT_SET_USB3_CK_MD(x, v) (BIT_CLEAR_USB3_CK_MD(x) | BIT_USB3_CK_MD(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ + +#define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8) + +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_USB3_CKBUF BIT(7) +#define BIT_USB3_IBX_EN BIT(6) + +#endif + +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_USB3_CK_MD 8 -#define BIT_MASK_USB3_CK_MD 0x3 -#define BIT_USB3_CK_MD(x) (((x) & BIT_MASK_USB3_CK_MD) << BIT_SHIFT_USB3_CK_MD) -#define BIT_GET_USB3_CK_MD(x) (((x) >> BIT_SHIFT_USB3_CK_MD) & BIT_MASK_USB3_CK_MD) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_BT_CLKREQ_EN BIT(6) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_U3_MB_MASK BIT(5) + +#endif + +#if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8) +#define BIT_BT_CTRL_USB_PWR_BACKDOOR BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_USB3_CKBUF BIT(7) -#define BIT_USB3_IBX_EN BIT(6) -#define BIT_U3_MB_MASK BIT(5) -#define BIT_U3_BG_MASK BIT(4) -#define BIT_DIS_USB3_MB_POLLING BIT(3) -#define BIT_PDN_MASK BIT(2) -#define BIT_NO_PDN_CHIPOFF BIT(1) +#define BIT_U3_BG_MASK BIT(4) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ + +#define BIT_SHIFT_USB_CKREF_CML_R 4 +#define BIT_MASK_USB_CKREF_CML_R 0x3 +#define BIT_USB_CKREF_CML_R(x) \ + (((x) & BIT_MASK_USB_CKREF_CML_R) << BIT_SHIFT_USB_CKREF_CML_R) +#define BITS_USB_CKREF_CML_R \ + (BIT_MASK_USB_CKREF_CML_R << BIT_SHIFT_USB_CKREF_CML_R) +#define BIT_CLEAR_USB_CKREF_CML_R(x) ((x) & (~BITS_USB_CKREF_CML_R)) +#define BIT_GET_USB_CKREF_CML_R(x) \ + (((x) >> BIT_SHIFT_USB_CKREF_CML_R) & BIT_MASK_USB_CKREF_CML_R) +#define BIT_SET_USB_CKREF_CML_R(x, v) \ + (BIT_CLEAR_USB_CKREF_CML_R(x) | BIT_USB_CKREF_CML_R(v)) +#endif + +#if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_RES_USB_MASS_STORAGE_DESC BIT(1) +#define BIT_USB_D_STATE_HOLD BIT(4) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_PDN_HCOUNT BIT(0) +#define BIT_DIS_USB3_MB_POLLING BIT(3) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - +#if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_USB_WAIT_TIME BIT(0) +#define BIT_REG_FORCE_DP BIT(3) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_PDN_MASK BIT(2) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TSFT_SEL 29 -#define BIT_MASK_TSFT_SEL 0x7 -#define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL) -#define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_SHIFT_USB_CKREF_D2S_I 2 +#define BIT_MASK_USB_CKREF_D2S_I 0x3 +#define BIT_USB_CKREF_D2S_I(x) \ + (((x) & BIT_MASK_USB_CKREF_D2S_I) << BIT_SHIFT_USB_CKREF_D2S_I) +#define BITS_USB_CKREF_D2S_I \ + (BIT_MASK_USB_CKREF_D2S_I << BIT_SHIFT_USB_CKREF_D2S_I) +#define BIT_CLEAR_USB_CKREF_D2S_I(x) ((x) & (~BITS_USB_CKREF_D2S_I)) +#define BIT_GET_USB_CKREF_D2S_I(x) \ + (((x) >> BIT_SHIFT_USB_CKREF_D2S_I) & BIT_MASK_USB_CKREF_D2S_I) +#define BIT_SET_USB_CKREF_D2S_I(x, v) \ + (BIT_CLEAR_USB_CKREF_D2S_I(x) | BIT_USB_CKREF_D2S_I(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_REG_DP_MODE BIT(2) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_XTAL_SEL_0_V1 28 -#define BIT_MASK_XTAL_SEL_0_V1 0xf -#define BIT_XTAL_SEL_0_V1(x) (((x) & BIT_MASK_XTAL_SEL_0_V1) << BIT_SHIFT_XTAL_SEL_0_V1) -#define BIT_GET_XTAL_SEL_0_V1(x) (((x) >> BIT_SHIFT_XTAL_SEL_0_V1) & BIT_MASK_XTAL_SEL_0_V1) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_ISO_RFC2RF_3 BIT(27) -#define BIT_ISO_RFC2RF_2 BIT(26) +#define BIT_NO_PDN_CHIPOFF BIT(1) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_RES_USB_MASS_STORAGE_DESC BIT(1) +#endif -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ + +#define BIT_PDN_HCOUNT BIT(0) -#define BIT_SHIFT_RPWM 24 -#define BIT_MASK_RPWM 0xff -#define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM) -#define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM) +#endif -#define BIT_ROM_DLEN BIT(19) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_ROM_PGE 16 -#define BIT_MASK_ROM_PGE 0x7 -#define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE) -#define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_USB_WAIT_TIME BIT(0) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ + +#define BIT_SHIFT_SI_AUTHORIZATION 0 +#define BIT_MASK_SI_AUTHORIZATION 0xff +#define BIT_SI_AUTHORIZATION(x) \ + (((x) & BIT_MASK_SI_AUTHORIZATION) << BIT_SHIFT_SI_AUTHORIZATION) +#define BITS_SI_AUTHORIZATION \ + (BIT_MASK_SI_AUTHORIZATION << BIT_SHIFT_SI_AUTHORIZATION) +#define BIT_CLEAR_SI_AUTHORIZATION(x) ((x) & (~BITS_SI_AUTHORIZATION)) +#define BIT_GET_SI_AUTHORIZATION(x) \ + (((x) >> BIT_SHIFT_SI_AUTHORIZATION) & BIT_MASK_SI_AUTHORIZATION) +#define BIT_SET_SI_AUTHORIZATION(x, v) \ + (BIT_CLEAR_SI_AUTHORIZATION(x) | BIT_SI_AUTHORIZATION(v)) +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_R_FORCE_CLK_U3 BIT(13) +#define BIT_SHIFT_TSFT_SEL 29 +#define BIT_MASK_TSFT_SEL 0x7 +#define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL) +#define BITS_TSFT_SEL (BIT_MASK_TSFT_SEL << BIT_SHIFT_TSFT_SEL) +#define BIT_CLEAR_TSFT_SEL(x) ((x) & (~BITS_TSFT_SEL)) +#define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL) +#define BIT_SET_TSFT_SEL(x, v) (BIT_CLEAR_TSFT_SEL(x) | BIT_TSFT_SEL(v)) #endif +#if (HALMAC_8814AMP_SUPPORT) + +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ + +#define BIT_SHIFT_XTAL_SEL_0_V1 28 +#define BIT_MASK_XTAL_SEL_0_V1 0xf +#define BIT_XTAL_SEL_0_V1(x) \ + (((x) & BIT_MASK_XTAL_SEL_0_V1) << BIT_SHIFT_XTAL_SEL_0_V1) +#define BITS_XTAL_SEL_0_V1 (BIT_MASK_XTAL_SEL_0_V1 << BIT_SHIFT_XTAL_SEL_0_V1) +#define BIT_CLEAR_XTAL_SEL_0_V1(x) ((x) & (~BITS_XTAL_SEL_0_V1)) +#define BIT_GET_XTAL_SEL_0_V1(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_0_V1) & BIT_MASK_XTAL_SEL_0_V1) +#define BIT_SET_XTAL_SEL_0_V1(x, v) \ + (BIT_CLEAR_XTAL_SEL_0_V1(x) | BIT_XTAL_SEL_0_V1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_USB_HOST_PWR_OFF_EN BIT(12) +#define BIT_TSFT_BAND_SEL BIT(28) #endif +#if (HALMAC_8814AMP_SUPPORT) + +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ + +#define BIT_ISO_RFC2RF_3 BIT(27) +#define BIT_ISO_RFC2RF_2 BIT(26) -#if (HALMAC_8814A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_R_USB2_AUTOLOAD BIT(12) +#define BIT_SHIFT_RPWM 24 +#define BIT_MASK_RPWM 0xff +#define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM) +#define BITS_RPWM (BIT_MASK_RPWM << BIT_SHIFT_RPWM) +#define BIT_CLEAR_RPWM(x) ((x) & (~BITS_RPWM)) +#define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM) +#define BIT_SET_RPWM(x, v) (BIT_CLEAR_RPWM(x) | BIT_RPWM(v)) + +#define BIT_ROM_DLEN BIT(19) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ + +#define BIT_SDIO_PAD_E5 BIT(18) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_SYM_LPS_BLOCK_EN BIT(11) +#define BIT_SHIFT_ROM_PGE 16 +#define BIT_MASK_ROM_PGE 0x7 +#define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE) +#define BITS_ROM_PGE (BIT_MASK_ROM_PGE << BIT_SHIFT_ROM_PGE) +#define BIT_CLEAR_ROM_PGE(x) ((x) & (~BITS_ROM_PGE)) +#define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE) +#define BIT_SET_ROM_PGE(x, v) (BIT_CLEAR_ROM_PGE(x) | BIT_ROM_PGE(v)) #endif - #if (HALMAC_8814A_SUPPORT) - /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_FORCE_U2CK BIT(11) +#define BIT_R_FORCE_CLK_U3 BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ + +#define BIT_USB_HOST_PWR_OFF_EN BIT(12) + +#endif +#if (HALMAC_8814A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_USB_LPM_ACT_EN BIT(10) +#define BIT_R_USB2_AUTOLOAD BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ + +#define BIT_SYM_LPS_BLOCK_EN BIT(11) +#endif + +#if (HALMAC_8814A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_FORCE_CLK BIT(10) +#define BIT_FORCE_U2CK BIT(11) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ + +#define BIT_USB_LPM_ACT_EN BIT(10) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_USB_LPM_NY BIT(9) +#define BIT_FORCE_CLK BIT(10) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ + +#define BIT_USB_LPM_NY BIT(9) + +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_U2_FORCE BIT(9) +#define BIT_U2_FORCE BIT(9) #endif +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ + +#define BIT_IBX_EN_VALUE BIT(9) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_USB_SUS_DIS BIT(8) +#define BIT_USB_SUS_DIS BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_U3_FORCE BIT(8) +#define BIT_U3_FORCE BIT(8) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_IB_EN_VALUE BIT(8) +#define BIT_EN_LW_PWR BIT(6) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SDIO_PAD_E 5 -#define BIT_MASK_SDIO_PAD_E 0x7 -#define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E) -#define BIT_GET_SDIO_PAD_E(x) (((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_SHIFT_SDIO_PAD_E 5 +#define BIT_MASK_SDIO_PAD_E 0x7 +#define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E) +#define BITS_SDIO_PAD_E (BIT_MASK_SDIO_PAD_E << BIT_SHIFT_SDIO_PAD_E) +#define BIT_CLEAR_SDIO_PAD_E(x) ((x) & (~BITS_SDIO_PAD_E)) +#define BIT_GET_SDIO_PAD_E(x) \ + (((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E) +#define BIT_SET_SDIO_PAD_E(x, v) (BIT_CLEAR_SDIO_PAD_E(x) | BIT_SDIO_PAD_E(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ + +#define BIT_EN_REGU BIT(5) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_USB_LPPLL_EN BIT(4) +#define BIT_USB_LPPLL_EN BIT(4) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_SDIO_H3L1 BIT(4) +#define BIT_SDIO_H3L1 BIT(4) #endif +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ + +#define BIT_FORCED_IB_EN BIT(4) +#define BIT_EN_PC BIT(4) +#define BIT_USB1_1_USB2_0_DECISION BIT(3) +#define BIT_EN_REGBG BIT(3) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_ROP_SW15 BIT(2) +#define BIT_ROP_SW15 BIT(2) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_SHIFT_USB23_SW_MODE 2 +#define BIT_MASK_USB23_SW_MODE 0x3 +#define BIT_USB23_SW_MODE(x) \ + (((x) & BIT_MASK_USB23_SW_MODE) << BIT_SHIFT_USB23_SW_MODE) +#define BITS_USB23_SW_MODE (BIT_MASK_USB23_SW_MODE << BIT_SHIFT_USB23_SW_MODE) +#define BIT_CLEAR_USB23_SW_MODE(x) ((x) & (~BITS_USB23_SW_MODE)) +#define BIT_GET_USB23_SW_MODE(x) \ + (((x) >> BIT_SHIFT_USB23_SW_MODE) & BIT_MASK_USB23_SW_MODE) +#define BIT_SET_USB23_SW_MODE(x, v) \ + (BIT_CLEAR_USB23_SW_MODE(x) | BIT_USB23_SW_MODE(v)) -#define BIT_SHIFT_USB23_SW_MODE 2 -#define BIT_MASK_USB23_SW_MODE 0x3 -#define BIT_USB23_SW_MODE(x) (((x) & BIT_MASK_USB23_SW_MODE) << BIT_SHIFT_USB23_SW_MODE) -#define BIT_GET_USB23_SW_MODE(x) (((x) >> BIT_SHIFT_USB23_SW_MODE) & BIT_MASK_USB23_SW_MODE) +#endif +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_REG_BG_LPF BIT(2) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_PCI_CKRDY_OPT BIT(1) +#define BIT_PCI_CKRDY_OPT BIT(1) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_PCLK_VLD_SEL BIT(1) +#define BIT_PCLK_VLD_SEL BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ + +#define BIT_PCI_VAUX_EN BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_PCI_VAUX_EN BIT(0) +#define BIT_VAUX_EN BIT(0) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_SHIFT_REG_BG 0 +#define BIT_MASK_REG_BG 0x3 +#define BIT_REG_BG(x) (((x) & BIT_MASK_REG_BG) << BIT_SHIFT_REG_BG) +#define BITS_REG_BG (BIT_MASK_REG_BG << BIT_SHIFT_REG_BG) +#define BIT_CLEAR_REG_BG(x) ((x) & (~BITS_REG_BG)) +#define BIT_GET_REG_BG(x) (((x) >> BIT_SHIFT_REG_BG) & BIT_MASK_REG_BG) +#define BIT_SET_REG_BG(x, v) (BIT_CLEAR_REG_BG(x) | BIT_REG_BG(v)) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_SHIFT_REG_VADJ 0 +#define BIT_MASK_REG_VADJ 0xf +#define BIT_REG_VADJ(x) (((x) & BIT_MASK_REG_VADJ) << BIT_SHIFT_REG_VADJ) +#define BITS_REG_VADJ (BIT_MASK_REG_VADJ << BIT_SHIFT_REG_VADJ) +#define BIT_CLEAR_REG_VADJ(x) ((x) & (~BITS_REG_VADJ)) +#define BIT_GET_REG_VADJ(x) (((x) >> BIT_SHIFT_REG_VADJ) & BIT_MASK_REG_VADJ) +#define BIT_SET_REG_VADJ(x, v) (BIT_CLEAR_REG_VADJ(x) | BIT_REG_VADJ(v)) + +#endif -#define BIT_VAUX_EN BIT(0) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ -#define BIT_SDM_ORDER BIT(30) -#define BIT_XTAL_DRV_RF_LATCH_V1 BIT(29) -#define BIT_XTAL_VDD_SEL_V1 BIT(28) +#define BIT_SDM_ORDER BIT(30) +#define BIT_XTAL_DRV_RF_LATCH_V1 BIT(29) +#define BIT_XTAL_VDD_SEL_V1 BIT(28) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_XTAL_DRV_RF_LATCH BIT(27) +#define BIT_XTAL_DRV_RF_LATCH BIT(27) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ -#define BIT_XQSEL_RF_AWAKE_V1 BIT(27) +#define BIT_XQSEL_RF_AWAKE_V1 BIT(27) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_XTAL_VDD_SEL BIT(26) +#define BIT_XTAL_VDD_SEL BIT(26) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_RF1_SDMRSTB BIT(26) +#define BIT_RF1_SDMRSTB BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ -#define BIT_GATED_XTAL_OK0_V1 BIT(26) +#define BIT_GATED_XTAL_OK0_V1 BIT(26) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_XQSEL_RF BIT(25) +#define BIT_XQSEL_RF BIT(25) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_RF1_RSTB BIT(25) +#define BIT_RF1_RSTB BIT(25) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_XQSEL_RF_AWAKE BIT(25) +#define BIT_XQSEL_RF_AWAKE BIT(25) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_XQSEL_RF_INITIAL BIT(24) +#define BIT_XQSEL_RF_INITIAL BIT(24) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_RF1_EN BIT(24) +#define BIT_RF1_EN BIT(24) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_XQSEL_BIT1 BIT(24) +#define BIT_XQSEL_BIT1 BIT(24) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_REG_VREF_SEL BIT(23) +#define BIT_REG_VREF_SEL BIT(23) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_DITHER_SDM_BIT3 BIT(23) -/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_F0N_2_TO_0 23 -#define BIT_MASK_F0N_2_TO_0 0x7 -#define BIT_F0N_2_TO_0(x) (((x) & BIT_MASK_F0N_2_TO_0) << BIT_SHIFT_F0N_2_TO_0) -#define BIT_GET_F0N_2_TO_0(x) (((x) >> BIT_SHIFT_F0N_2_TO_0) & BIT_MASK_F0N_2_TO_0) +/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#define BIT_SHIFT_F0N_2_TO_0 23 +#define BIT_MASK_F0N_2_TO_0 0x7 +#define BIT_F0N_2_TO_0(x) (((x) & BIT_MASK_F0N_2_TO_0) << BIT_SHIFT_F0N_2_TO_0) +#define BITS_F0N_2_TO_0 (BIT_MASK_F0N_2_TO_0 << BIT_SHIFT_F0N_2_TO_0) +#define BIT_CLEAR_F0N_2_TO_0(x) ((x) & (~BITS_F0N_2_TO_0)) +#define BIT_GET_F0N_2_TO_0(x) \ + (((x) >> BIT_SHIFT_F0N_2_TO_0) & BIT_MASK_F0N_2_TO_0) +#define BIT_SET_F0N_2_TO_0(x, v) (BIT_CLEAR_F0N_2_TO_0(x) | BIT_F0N_2_TO_0(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_REG_LPFEN BIT(22) -#define BIT_REG_KVCO BIT(21) -#define BIT_XTAL_DRV_AGPIO_BIT1 BIT(20) +#define BIT_REG_LPFEN BIT(22) +#define BIT_REG_KVCO BIT(21) +#define BIT_XTAL_DRV_AGPIO_BIT1 BIT(20) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ - -#define BIT_SHIFT_XTAL_LDO 20 -#define BIT_MASK_XTAL_LDO 0x7 -#define BIT_XTAL_LDO(x) (((x) & BIT_MASK_XTAL_LDO) << BIT_SHIFT_XTAL_LDO) -#define BIT_GET_XTAL_LDO(x) (((x) >> BIT_SHIFT_XTAL_LDO) & BIT_MASK_XTAL_LDO) - +#define BIT_SHIFT_XTAL_LDO 20 +#define BIT_MASK_XTAL_LDO 0x7 +#define BIT_XTAL_LDO(x) (((x) & BIT_MASK_XTAL_LDO) << BIT_SHIFT_XTAL_LDO) +#define BITS_XTAL_LDO (BIT_MASK_XTAL_LDO << BIT_SHIFT_XTAL_LDO) +#define BIT_CLEAR_XTAL_LDO(x) ((x) & (~BITS_XTAL_LDO)) +#define BIT_GET_XTAL_LDO(x) (((x) >> BIT_SHIFT_XTAL_LDO) & BIT_MASK_XTAL_LDO) +#define BIT_SET_XTAL_LDO(x, v) (BIT_CLEAR_XTAL_LDO(x) | BIT_XTAL_LDO(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_XTAL_DRV_AGPIO_BIT0 BIT(19) +#define BIT_XTAL_DRV_AGPIO_BIT0 BIT(19) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_XTAL_GRF2 BIT(18) -#define BIT_REG_REF_SEL BIT(17) -#define BIT_REG_320_SEL BIT(16) +#define BIT_XTAL_GRF2 BIT(18) +#define BIT_REG_REF_SEL BIT(17) +#define BIT_REG_320_SEL BIT(16) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_ADC_CK_SYNC_EN BIT(16) +#define BIT_ADC_CK_SYNC_EN BIT(16) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_EN_SYM BIT(15) - -#define BIT_SHIFT_IOFFSET 10 -#define BIT_MASK_IOFFSET 0x1f -#define BIT_IOFFSET(x) (((x) & BIT_MASK_IOFFSET) << BIT_SHIFT_IOFFSET) -#define BIT_GET_IOFFSET(x) (((x) >> BIT_SHIFT_IOFFSET) & BIT_MASK_IOFFSET) +#define BIT_EN_SYM BIT(15) +#define BIT_SHIFT_IOFFSET 10 +#define BIT_MASK_IOFFSET 0x1f +#define BIT_IOFFSET(x) (((x) & BIT_MASK_IOFFSET) << BIT_SHIFT_IOFFSET) +#define BITS_IOFFSET (BIT_MASK_IOFFSET << BIT_SHIFT_IOFFSET) +#define BIT_CLEAR_IOFFSET(x) ((x) & (~BITS_IOFFSET)) +#define BIT_GET_IOFFSET(x) (((x) >> BIT_SHIFT_IOFFSET) & BIT_MASK_IOFFSET) +#define BIT_SET_IOFFSET(x, v) (BIT_CLEAR_IOFFSET(x) | BIT_IOFFSET(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_RF2_SDMRSTB BIT(10) -/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_F0F_12_TO_0 10 -#define BIT_MASK_F0F_12_TO_0 0x1fff -#define BIT_F0F_12_TO_0(x) (((x) & BIT_MASK_F0F_12_TO_0) << BIT_SHIFT_F0F_12_TO_0) -#define BIT_GET_F0F_12_TO_0(x) (((x) >> BIT_SHIFT_F0F_12_TO_0) & BIT_MASK_F0F_12_TO_0) +/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#define BIT_SHIFT_F0F_12_TO_0 10 +#define BIT_MASK_F0F_12_TO_0 0x1fff +#define BIT_F0F_12_TO_0(x) \ + (((x) & BIT_MASK_F0F_12_TO_0) << BIT_SHIFT_F0F_12_TO_0) +#define BITS_F0F_12_TO_0 (BIT_MASK_F0F_12_TO_0 << BIT_SHIFT_F0F_12_TO_0) +#define BIT_CLEAR_F0F_12_TO_0(x) ((x) & (~BITS_F0F_12_TO_0)) +#define BIT_GET_F0F_12_TO_0(x) \ + (((x) >> BIT_SHIFT_F0F_12_TO_0) & BIT_MASK_F0F_12_TO_0) +#define BIT_SET_F0F_12_TO_0(x, v) \ + (BIT_CLEAR_F0F_12_TO_0(x) | BIT_F0F_12_TO_0(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_RF2_RSTB BIT(9) -#define BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1 8 -#define BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 0x3 -#define BIT_APLL_FREF_SEL_BIT_2_TO_1(x) (((x) & BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1) << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) -#define BIT_GET_APLL_FREF_SEL_BIT_2_TO_1(x) (((x) >> BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) & BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1) +#endif -#define BIT_APLL_FREF_SEL_BIT3 BIT(7) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_APLL_LDO_V12ADJ 5 -#define BIT_MASK_APLL_LDO_V12ADJ 0x3 -#define BIT_APLL_LDO_V12ADJ(x) (((x) & BIT_MASK_APLL_LDO_V12ADJ) << BIT_SHIFT_APLL_LDO_V12ADJ) -#define BIT_GET_APLL_LDO_V12ADJ(x) (((x) >> BIT_SHIFT_APLL_LDO_V12ADJ) & BIT_MASK_APLL_LDO_V12ADJ) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_APLL_160_GATEB BIT(4) +#define BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1 8 +#define BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 0x3 +#define BIT_APLL_FREF_SEL_BIT_2_TO_1(x) \ + (((x) & BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1) \ + << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) +#define BITS_APLL_FREF_SEL_BIT_2_TO_1 \ + (BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 \ + << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) +#define BIT_CLEAR_APLL_FREF_SEL_BIT_2_TO_1(x) \ + ((x) & (~BITS_APLL_FREF_SEL_BIT_2_TO_1)) +#define BIT_GET_APLL_FREF_SEL_BIT_2_TO_1(x) \ + (((x) >> BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) & \ + BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1) +#define BIT_SET_APLL_FREF_SEL_BIT_2_TO_1(x, v) \ + (BIT_CLEAR_APLL_FREF_SEL_BIT_2_TO_1(x) | \ + BIT_APLL_FREF_SEL_BIT_2_TO_1(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ - - -#define BIT_SHIFT_DIVN_5_TO_0 4 -#define BIT_MASK_DIVN_5_TO_0 0x3f -#define BIT_DIVN_5_TO_0(x) (((x) & BIT_MASK_DIVN_5_TO_0) << BIT_SHIFT_DIVN_5_TO_0) -#define BIT_GET_DIVN_5_TO_0(x) (((x) >> BIT_SHIFT_DIVN_5_TO_0) & BIT_MASK_DIVN_5_TO_0) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_RF2_EN BIT(8) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_AFE_DUMMY BIT(3) -#define BIT_REG_IDOUBLE BIT(2) -#define BIT_REG_VCO_BIAS_BIT0 BIT(1) -#define BIT_REG_VCO_BIAS_BIT1 BIT(0) +#define BIT_APLL_FREF_SEL_BIT3 BIT(7) -#endif +#define BIT_SHIFT_APLL_LDO_V12ADJ 5 +#define BIT_MASK_APLL_LDO_V12ADJ 0x3 +#define BIT_APLL_LDO_V12ADJ(x) \ + (((x) & BIT_MASK_APLL_LDO_V12ADJ) << BIT_SHIFT_APLL_LDO_V12ADJ) +#define BITS_APLL_LDO_V12ADJ \ + (BIT_MASK_APLL_LDO_V12ADJ << BIT_SHIFT_APLL_LDO_V12ADJ) +#define BIT_CLEAR_APLL_LDO_V12ADJ(x) ((x) & (~BITS_APLL_LDO_V12ADJ)) +#define BIT_GET_APLL_LDO_V12ADJ(x) \ + (((x) >> BIT_SHIFT_APLL_LDO_V12ADJ) & BIT_MASK_APLL_LDO_V12ADJ) +#define BIT_SET_APLL_LDO_V12ADJ(x, v) \ + (BIT_CLEAR_APLL_LDO_V12ADJ(x) | BIT_APLL_LDO_V12ADJ(v)) +#define BIT_APLL_160_GATEB BIT(4) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#define BIT_SHIFT_DIVN_5_TO_0 4 +#define BIT_MASK_DIVN_5_TO_0 0x3f +#define BIT_DIVN_5_TO_0(x) \ + (((x) & BIT_MASK_DIVN_5_TO_0) << BIT_SHIFT_DIVN_5_TO_0) +#define BITS_DIVN_5_TO_0 (BIT_MASK_DIVN_5_TO_0 << BIT_SHIFT_DIVN_5_TO_0) +#define BIT_CLEAR_DIVN_5_TO_0(x) ((x) & (~BITS_DIVN_5_TO_0)) +#define BIT_GET_DIVN_5_TO_0(x) \ + (((x) >> BIT_SHIFT_DIVN_5_TO_0) & BIT_MASK_DIVN_5_TO_0) +#define BIT_SET_DIVN_5_TO_0(x, v) \ + (BIT_CLEAR_DIVN_5_TO_0(x) | BIT_DIVN_5_TO_0(v)) -#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0 0 -#define BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 0xf -#define BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_3_TO_0(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) & BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_REF_FREF_EDGE BIT(29) -#define BIT_REG_VREF_SEL_V1 BIT(28) +#define BIT_AFE_DUMMY BIT(3) +#define BIT_REG_IDOUBLE BIT(2) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_ZCD_HW_AUTO_EN BIT(27) -#define BIT_ZCD_REGSEL BIT(26) +#define BIT_RF3_SDMRSTB BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_REG_VCO_BIAS_BIT0 BIT(1) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_REG_CP_OFFSET_4_TO_0 23 -#define BIT_MASK_REG_CP_OFFSET_4_TO_0 0x1f -#define BIT_REG_CP_OFFSET_4_TO_0(x) (((x) & BIT_MASK_REG_CP_OFFSET_4_TO_0) << BIT_SHIFT_REG_CP_OFFSET_4_TO_0) -#define BIT_GET_REG_CP_OFFSET_4_TO_0(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_4_TO_0) & BIT_MASK_REG_CP_OFFSET_4_TO_0) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_RF3_RSTB BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_REG_VCO_BIAS_BIT1 BIT(0) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_AUTO_ZCD_IN_CODE 21 -#define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f -#define BIT_AUTO_ZCD_IN_CODE(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE) -#define BIT_GET_AUTO_ZCD_IN_CODE(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_RF3_EN BIT(0) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ - - -#define BIT_SHIFT_REG_RS_SET_2_TO_0 20 -#define BIT_MASK_REG_RS_SET_2_TO_0 0x7 -#define BIT_REG_RS_SET_2_TO_0(x) (((x) & BIT_MASK_REG_RS_SET_2_TO_0) << BIT_SHIFT_REG_RS_SET_2_TO_0) -#define BIT_GET_REG_RS_SET_2_TO_0(x) (((x) >> BIT_SHIFT_REG_RS_SET_2_TO_0) & BIT_MASK_REG_RS_SET_2_TO_0) - +#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0 0 +#define BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 0xf +#define BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0) \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) +#define BITS_BB_DBG_SEL_AFE_SDM_3_TO_0 \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_3_TO_0(x) \ + ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_3_TO_0)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_3_TO_0(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) & \ + BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_3_TO_0(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_3_TO_0(x) | \ + BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(v)) -#define BIT_SHIFT_REG_CS_SET_1_TO_0 18 -#define BIT_MASK_REG_CS_SET_1_TO_0 0x3 -#define BIT_REG_CS_SET_1_TO_0(x) (((x) & BIT_MASK_REG_CS_SET_1_TO_0) << BIT_SHIFT_REG_CS_SET_1_TO_0) -#define BIT_GET_REG_CS_SET_1_TO_0(x) (((x) >> BIT_SHIFT_REG_CS_SET_1_TO_0) & BIT_MASK_REG_CS_SET_1_TO_0) +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_REG_CP_SET_1_TO_0 16 -#define BIT_MASK_REG_CP_SET_1_TO_0 0x3 -#define BIT_REG_CP_SET_1_TO_0(x) (((x) & BIT_MASK_REG_CP_SET_1_TO_0) << BIT_SHIFT_REG_CP_SET_1_TO_0) -#define BIT_GET_REG_CP_SET_1_TO_0(x) (((x) >> BIT_SHIFT_REG_CP_SET_1_TO_0) & BIT_MASK_REG_CP_SET_1_TO_0) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_EXT_SWR_CTRL_EN BIT(31) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_REF_FREF_EDGE BIT(29) +#define BIT_REG_VREF_SEL_V1 BIT(28) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_ZCD_CODE_IN_L 16 -#define BIT_MASK_ZCD_CODE_IN_L 0x1f -#define BIT_ZCD_CODE_IN_L(x) (((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L) -#define BIT_GET_ZCD_CODE_IN_L(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_ZCD_HW_AUTO_EN BIT(27) +#define BIT_ZCD_REGSEL BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_LPFEN BIT(15) +#define BIT_SHIFT_REG_CP_OFFSET_4_TO_0 23 +#define BIT_MASK_REG_CP_OFFSET_4_TO_0 0x1f +#define BIT_REG_CP_OFFSET_4_TO_0(x) \ + (((x) & BIT_MASK_REG_CP_OFFSET_4_TO_0) \ + << BIT_SHIFT_REG_CP_OFFSET_4_TO_0) +#define BITS_REG_CP_OFFSET_4_TO_0 \ + (BIT_MASK_REG_CP_OFFSET_4_TO_0 << BIT_SHIFT_REG_CP_OFFSET_4_TO_0) +#define BIT_CLEAR_REG_CP_OFFSET_4_TO_0(x) ((x) & (~BITS_REG_CP_OFFSET_4_TO_0)) +#define BIT_GET_REG_CP_OFFSET_4_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_CP_OFFSET_4_TO_0) & \ + BIT_MASK_REG_CP_OFFSET_4_TO_0) +#define BIT_SET_REG_CP_OFFSET_4_TO_0(x, v) \ + (BIT_CLEAR_REG_CP_OFFSET_4_TO_0(x) | BIT_REG_CP_OFFSET_4_TO_0(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ + +#define BIT_SHIFT_AUTO_ZCD_IN_CODE 21 +#define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f +#define BIT_AUTO_ZCD_IN_CODE(x) \ + (((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE) +#define BITS_AUTO_ZCD_IN_CODE \ + (BIT_MASK_AUTO_ZCD_IN_CODE << BIT_SHIFT_AUTO_ZCD_IN_CODE) +#define BIT_CLEAR_AUTO_ZCD_IN_CODE(x) ((x) & (~BITS_AUTO_ZCD_IN_CODE)) +#define BIT_GET_AUTO_ZCD_IN_CODE(x) \ + (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE) +#define BIT_SET_AUTO_ZCD_IN_CODE(x, v) \ + (BIT_CLEAR_AUTO_ZCD_IN_CODE(x) | BIT_AUTO_ZCD_IN_CODE(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_REG_RS_SET_2_TO_0 20 +#define BIT_MASK_REG_RS_SET_2_TO_0 0x7 +#define BIT_REG_RS_SET_2_TO_0(x) \ + (((x) & BIT_MASK_REG_RS_SET_2_TO_0) << BIT_SHIFT_REG_RS_SET_2_TO_0) +#define BITS_REG_RS_SET_2_TO_0 \ + (BIT_MASK_REG_RS_SET_2_TO_0 << BIT_SHIFT_REG_RS_SET_2_TO_0) +#define BIT_CLEAR_REG_RS_SET_2_TO_0(x) ((x) & (~BITS_REG_RS_SET_2_TO_0)) +#define BIT_GET_REG_RS_SET_2_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_RS_SET_2_TO_0) & BIT_MASK_REG_RS_SET_2_TO_0) +#define BIT_SET_REG_RS_SET_2_TO_0(x, v) \ + (BIT_CLEAR_REG_RS_SET_2_TO_0(x) | BIT_REG_RS_SET_2_TO_0(v)) + +#define BIT_SHIFT_REG_CS_SET_1_TO_0 18 +#define BIT_MASK_REG_CS_SET_1_TO_0 0x3 +#define BIT_REG_CS_SET_1_TO_0(x) \ + (((x) & BIT_MASK_REG_CS_SET_1_TO_0) << BIT_SHIFT_REG_CS_SET_1_TO_0) +#define BITS_REG_CS_SET_1_TO_0 \ + (BIT_MASK_REG_CS_SET_1_TO_0 << BIT_SHIFT_REG_CS_SET_1_TO_0) +#define BIT_CLEAR_REG_CS_SET_1_TO_0(x) ((x) & (~BITS_REG_CS_SET_1_TO_0)) +#define BIT_GET_REG_CS_SET_1_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_CS_SET_1_TO_0) & BIT_MASK_REG_CS_SET_1_TO_0) +#define BIT_SET_REG_CS_SET_1_TO_0(x, v) \ + (BIT_CLEAR_REG_CS_SET_1_TO_0(x) | BIT_REG_CS_SET_1_TO_0(v)) + +#define BIT_SHIFT_REG_CP_SET_1_TO_0 16 +#define BIT_MASK_REG_CP_SET_1_TO_0 0x3 +#define BIT_REG_CP_SET_1_TO_0(x) \ + (((x) & BIT_MASK_REG_CP_SET_1_TO_0) << BIT_SHIFT_REG_CP_SET_1_TO_0) +#define BITS_REG_CP_SET_1_TO_0 \ + (BIT_MASK_REG_CP_SET_1_TO_0 << BIT_SHIFT_REG_CP_SET_1_TO_0) +#define BIT_CLEAR_REG_CP_SET_1_TO_0(x) ((x) & (~BITS_REG_CP_SET_1_TO_0)) +#define BIT_GET_REG_CP_SET_1_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_CP_SET_1_TO_0) & BIT_MASK_REG_CP_SET_1_TO_0) +#define BIT_SET_REG_CP_SET_1_TO_0(x, v) \ + (BIT_CLEAR_REG_CP_SET_1_TO_0(x) | BIT_REG_CP_SET_1_TO_0(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LDO_HV5_DUMMY 14 -#define BIT_MASK_LDO_HV5_DUMMY 0x3 -#define BIT_LDO_HV5_DUMMY(x) (((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY) -#define BIT_GET_LDO_HV5_DUMMY(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_ZCD_CODE_IN_L 16 +#define BIT_MASK_ZCD_CODE_IN_L 0x1f +#define BIT_ZCD_CODE_IN_L(x) \ + (((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L) +#define BITS_ZCD_CODE_IN_L (BIT_MASK_ZCD_CODE_IN_L << BIT_SHIFT_ZCD_CODE_IN_L) +#define BIT_CLEAR_ZCD_CODE_IN_L(x) ((x) & (~BITS_ZCD_CODE_IN_L)) +#define BIT_GET_ZCD_CODE_IN_L(x) \ + (((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L) +#define BIT_SET_ZCD_CODE_IN_L(x, v) \ + (BIT_CLEAR_ZCD_CODE_IN_L(x) | BIT_ZCD_CODE_IN_L(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_DOGENB BIT(14) -#define BIT_REG_TEST_EN BIT(13) +#define BIT_LPFEN BIT(15) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_LDO_HV5_DUMMY 14 +#define BIT_MASK_LDO_HV5_DUMMY 0x3 +#define BIT_LDO_HV5_DUMMY(x) \ + (((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY) +#define BITS_LDO_HV5_DUMMY (BIT_MASK_LDO_HV5_DUMMY << BIT_SHIFT_LDO_HV5_DUMMY) +#define BIT_CLEAR_LDO_HV5_DUMMY(x) ((x) & (~BITS_LDO_HV5_DUMMY)) +#define BIT_GET_LDO_HV5_DUMMY(x) \ + (((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY) +#define BIT_SET_LDO_HV5_DUMMY(x, v) \ + (BIT_CLEAR_LDO_HV5_DUMMY(x) | BIT_LDO_HV5_DUMMY(v)) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_REG_VTUNE33 12 -#define BIT_MASK_REG_VTUNE33 0x3 -#define BIT_REG_VTUNE33(x) (((x) & BIT_MASK_REG_VTUNE33) << BIT_SHIFT_REG_VTUNE33) -#define BIT_GET_REG_VTUNE33(x) (((x) >> BIT_SHIFT_REG_VTUNE33) & BIT_MASK_REG_VTUNE33) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_REG_DOGENB BIT(14) +#define BIT_REG_TEST_EN BIT(13) #endif +#if (HALMAC_8192E_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_REG_VTUNE33 12 +#define BIT_MASK_REG_VTUNE33 0x3 +#define BIT_REG_VTUNE33(x) \ + (((x) & BIT_MASK_REG_VTUNE33) << BIT_SHIFT_REG_VTUNE33) +#define BITS_REG_VTUNE33 (BIT_MASK_REG_VTUNE33 << BIT_SHIFT_REG_VTUNE33) +#define BIT_CLEAR_REG_VTUNE33(x) ((x) & (~BITS_REG_VTUNE33)) +#define BIT_GET_REG_VTUNE33(x) \ + (((x) >> BIT_SHIFT_REG_VTUNE33) & BIT_MASK_REG_VTUNE33) +#define BIT_SET_REG_VTUNE33(x, v) \ + (BIT_CLEAR_REG_VTUNE33(x) | BIT_REG_VTUNE33(v)) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12 -#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3 -#define BIT_REG_VTUNE33_BIT0_TO_BIT1(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) -#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12 +#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3 +#define BIT_REG_VTUNE33_BIT0_TO_BIT1(x) \ + (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) \ + << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) +#define BITS_REG_VTUNE33_BIT0_TO_BIT1 \ + (BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 \ + << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) +#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1(x) \ + ((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1)) +#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x) \ + (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) & \ + BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) +#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1(x, v) \ + (BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1(x) | \ + BIT_REG_VTUNE33_BIT0_TO_BIT1(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ - -#define BIT_SHIFT_REG_STANDBY33 10 -#define BIT_MASK_REG_STANDBY33 0x3 -#define BIT_REG_STANDBY33(x) (((x) & BIT_MASK_REG_STANDBY33) << BIT_SHIFT_REG_STANDBY33) -#define BIT_GET_REG_STANDBY33(x) (((x) >> BIT_SHIFT_REG_STANDBY33) & BIT_MASK_REG_STANDBY33) - +#define BIT_SHIFT_REG_STANDBY33 10 +#define BIT_MASK_REG_STANDBY33 0x3 +#define BIT_REG_STANDBY33(x) \ + (((x) & BIT_MASK_REG_STANDBY33) << BIT_SHIFT_REG_STANDBY33) +#define BITS_REG_STANDBY33 (BIT_MASK_REG_STANDBY33 << BIT_SHIFT_REG_STANDBY33) +#define BIT_CLEAR_REG_STANDBY33(x) ((x) & (~BITS_REG_STANDBY33)) +#define BIT_GET_REG_STANDBY33(x) \ + (((x) >> BIT_SHIFT_REG_STANDBY33) & BIT_MASK_REG_STANDBY33) +#define BIT_SET_REG_STANDBY33(x, v) \ + (BIT_CLEAR_REG_STANDBY33(x) | BIT_REG_STANDBY33(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ - -#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10 -#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3 -#define BIT_REG_STANDBY33_BIT0_TO_BIT1(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) -#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) - +#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10 +#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3 +#define BIT_REG_STANDBY33_BIT0_TO_BIT1(x) \ + (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) \ + << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) +#define BITS_REG_STANDBY33_BIT0_TO_BIT1 \ + (BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 \ + << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) +#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1(x) \ + ((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1)) +#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x) \ + (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) & \ + BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) +#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1(x, v) \ + (BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1(x) | \ + BIT_REG_STANDBY33_BIT0_TO_BIT1(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ - -#define BIT_SHIFT_REG_LOAD33 8 -#define BIT_MASK_REG_LOAD33 0x3 -#define BIT_REG_LOAD33(x) (((x) & BIT_MASK_REG_LOAD33) << BIT_SHIFT_REG_LOAD33) -#define BIT_GET_REG_LOAD33(x) (((x) >> BIT_SHIFT_REG_LOAD33) & BIT_MASK_REG_LOAD33) - +#define BIT_SHIFT_REG_LOAD33 8 +#define BIT_MASK_REG_LOAD33 0x3 +#define BIT_REG_LOAD33(x) (((x) & BIT_MASK_REG_LOAD33) << BIT_SHIFT_REG_LOAD33) +#define BITS_REG_LOAD33 (BIT_MASK_REG_LOAD33 << BIT_SHIFT_REG_LOAD33) +#define BIT_CLEAR_REG_LOAD33(x) ((x) & (~BITS_REG_LOAD33)) +#define BIT_GET_REG_LOAD33(x) \ + (((x) >> BIT_SHIFT_REG_LOAD33) & BIT_MASK_REG_LOAD33) +#define BIT_SET_REG_LOAD33(x, v) (BIT_CLEAR_REG_LOAD33(x) | BIT_REG_LOAD33(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ - -#define BIT_SHIFT_REG_DIV_SEL 8 -#define BIT_MASK_REG_DIV_SEL 0x1f -#define BIT_REG_DIV_SEL(x) (((x) & BIT_MASK_REG_DIV_SEL) << BIT_SHIFT_REG_DIV_SEL) -#define BIT_GET_REG_DIV_SEL(x) (((x) >> BIT_SHIFT_REG_DIV_SEL) & BIT_MASK_REG_DIV_SEL) - +#define BIT_SHIFT_REG_DIV_SEL 8 +#define BIT_MASK_REG_DIV_SEL 0x1f +#define BIT_REG_DIV_SEL(x) \ + (((x) & BIT_MASK_REG_DIV_SEL) << BIT_SHIFT_REG_DIV_SEL) +#define BITS_REG_DIV_SEL (BIT_MASK_REG_DIV_SEL << BIT_SHIFT_REG_DIV_SEL) +#define BIT_CLEAR_REG_DIV_SEL(x) ((x) & (~BITS_REG_DIV_SEL)) +#define BIT_GET_REG_DIV_SEL(x) \ + (((x) >> BIT_SHIFT_REG_DIV_SEL) & BIT_MASK_REG_DIV_SEL) +#define BIT_SET_REG_DIV_SEL(x, v) \ + (BIT_CLEAR_REG_DIV_SEL(x) | BIT_REG_DIV_SEL(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ - -#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8 -#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3 -#define BIT_REG_LOAD33_BIT0_TO_BIT1(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) -#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) - +#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8 +#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3 +#define BIT_REG_LOAD33_BIT0_TO_BIT1(x) \ + (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) \ + << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) +#define BITS_REG_LOAD33_BIT0_TO_BIT1 \ + (BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) +#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1(x) \ + ((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1)) +#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x) \ + (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) & \ + BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) +#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1(x, v) \ + (BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1(x) | BIT_REG_LOAD33_BIT0_TO_BIT1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_BYPASS_L BIT(7) +#define BIT_REG_BYPASS_L BIT(7) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_EN_CK200M BIT(7) +#define BIT_EN_CK200M BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_LDOF_L BIT(6) +#define BIT_REG_LDOF_L BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_OCPS_L BIT(5) +#define BIT_REG_OCPS_L BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ - -#define BIT_SHIFT_REG_KVCO_200M_1_TO_0 5 -#define BIT_MASK_REG_KVCO_200M_1_TO_0 0x3 -#define BIT_REG_KVCO_200M_1_TO_0(x) (((x) & BIT_MASK_REG_KVCO_200M_1_TO_0) << BIT_SHIFT_REG_KVCO_200M_1_TO_0) -#define BIT_GET_REG_KVCO_200M_1_TO_0(x) (((x) >> BIT_SHIFT_REG_KVCO_200M_1_TO_0) & BIT_MASK_REG_KVCO_200M_1_TO_0) - +#define BIT_SHIFT_REG_KVCO_200M_1_TO_0 5 +#define BIT_MASK_REG_KVCO_200M_1_TO_0 0x3 +#define BIT_REG_KVCO_200M_1_TO_0(x) \ + (((x) & BIT_MASK_REG_KVCO_200M_1_TO_0) \ + << BIT_SHIFT_REG_KVCO_200M_1_TO_0) +#define BITS_REG_KVCO_200M_1_TO_0 \ + (BIT_MASK_REG_KVCO_200M_1_TO_0 << BIT_SHIFT_REG_KVCO_200M_1_TO_0) +#define BIT_CLEAR_REG_KVCO_200M_1_TO_0(x) ((x) & (~BITS_REG_KVCO_200M_1_TO_0)) +#define BIT_GET_REG_KVCO_200M_1_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_KVCO_200M_1_TO_0) & \ + BIT_MASK_REG_KVCO_200M_1_TO_0) +#define BIT_SET_REG_KVCO_200M_1_TO_0(x, v) \ + (BIT_CLEAR_REG_KVCO_200M_1_TO_0(x) | BIT_REG_KVCO_200M_1_TO_0(v)) #endif - #if (HALMAC_8822B_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_TYPE_L_V1 BIT(5) +#define BIT_REG_TYPE_L_V1 BIT(5) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_ARENB_L BIT(3) +#define BIT_ARENB_L BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ - -#define BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0 2 -#define BIT_MASK_REG_CP_BIAS_200M_2_TO_0 0x7 -#define BIT_REG_CP_BIAS_200M_2_TO_0(x) (((x) & BIT_MASK_REG_CP_BIAS_200M_2_TO_0) << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) -#define BIT_GET_REG_CP_BIAS_200M_2_TO_0(x) (((x) >> BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) & BIT_MASK_REG_CP_BIAS_200M_2_TO_0) - +#define BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0 2 +#define BIT_MASK_REG_CP_BIAS_200M_2_TO_0 0x7 +#define BIT_REG_CP_BIAS_200M_2_TO_0(x) \ + (((x) & BIT_MASK_REG_CP_BIAS_200M_2_TO_0) \ + << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) +#define BITS_REG_CP_BIAS_200M_2_TO_0 \ + (BIT_MASK_REG_CP_BIAS_200M_2_TO_0 << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) +#define BIT_CLEAR_REG_CP_BIAS_200M_2_TO_0(x) \ + ((x) & (~BITS_REG_CP_BIAS_200M_2_TO_0)) +#define BIT_GET_REG_CP_BIAS_200M_2_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) & \ + BIT_MASK_REG_CP_BIAS_200M_2_TO_0) +#define BIT_SET_REG_CP_BIAS_200M_2_TO_0(x, v) \ + (BIT_CLEAR_REG_CP_BIAS_200M_2_TO_0(x) | BIT_REG_CP_BIAS_200M_2_TO_0(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ - -#define BIT_SHIFT_CFC_L_BIT_1_TO_0 1 -#define BIT_MASK_CFC_L_BIT_1_TO_0 0x3 -#define BIT_CFC_L_BIT_1_TO_0(x) (((x) & BIT_MASK_CFC_L_BIT_1_TO_0) << BIT_SHIFT_CFC_L_BIT_1_TO_0) -#define BIT_GET_CFC_L_BIT_1_TO_0(x) (((x) >> BIT_SHIFT_CFC_L_BIT_1_TO_0) & BIT_MASK_CFC_L_BIT_1_TO_0) - +#define BIT_SHIFT_CFC_L_BIT_1_TO_0 1 +#define BIT_MASK_CFC_L_BIT_1_TO_0 0x3 +#define BIT_CFC_L_BIT_1_TO_0(x) \ + (((x) & BIT_MASK_CFC_L_BIT_1_TO_0) << BIT_SHIFT_CFC_L_BIT_1_TO_0) +#define BITS_CFC_L_BIT_1_TO_0 \ + (BIT_MASK_CFC_L_BIT_1_TO_0 << BIT_SHIFT_CFC_L_BIT_1_TO_0) +#define BIT_CLEAR_CFC_L_BIT_1_TO_0(x) ((x) & (~BITS_CFC_L_BIT_1_TO_0)) +#define BIT_GET_CFC_L_BIT_1_TO_0(x) \ + (((x) >> BIT_SHIFT_CFC_L_BIT_1_TO_0) & BIT_MASK_CFC_L_BIT_1_TO_0) +#define BIT_SET_CFC_L_BIT_1_TO_0(x, v) \ + (BIT_CLEAR_CFC_L_BIT_1_TO_0(x) | BIT_CFC_L_BIT_1_TO_0(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ - -#define BIT_SHIFT_CFC_L 1 -#define BIT_MASK_CFC_L 0x3 -#define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L) -#define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L) - +#define BIT_SHIFT_CFC_L 1 +#define BIT_MASK_CFC_L 0x3 +#define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L) +#define BITS_CFC_L (BIT_MASK_CFC_L << BIT_SHIFT_CFC_L) +#define BIT_CLEAR_CFC_L(x) ((x) & (~BITS_CFC_L)) +#define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L) +#define BIT_SET_CFC_L(x, v) (BIT_CLEAR_CFC_L(x) | BIT_CFC_L(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_TYPE_L BIT(0) +#define BIT_REG_TYPE_L BIT(0) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_XCK_OUT_EN BIT(0) +#define BIT_XCK_OUT_EN BIT(0) #endif - #if (HALMAC_8822B_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_OCPS_L_V1 BIT(0) +#define BIT_REG_OCPS_L_V1 BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_ANA_PORT_EN BIT(22) -#define BIT_MAC_PORT_EN BIT(21) -#define BIT_BOOT_FSPI_EN BIT(20) -#define BIT_FW_INIT_RDY BIT(15) -#define BIT_FW_DW_RDY BIT(14) +#define BIT_ANA_PORT_EN BIT(22) +#define BIT_MAC_PORT_EN BIT(21) +#define BIT_BOOT_FSPI_EN BIT(20) +#define BIT_FW_INIT_RDY BIT(15) +#define BIT_FW_DW_RDY BIT(14) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_FWDL_RSVDPAGE_RDY BIT(12) +#define BIT_FWDL_RSVDPAGE_RDY BIT(12) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ - -#define BIT_SHIFT_CPU_CLK_SEL 12 -#define BIT_MASK_CPU_CLK_SEL 0x3 -#define BIT_CPU_CLK_SEL(x) (((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL) -#define BIT_GET_CPU_CLK_SEL(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL) - +#define BIT_SHIFT_CPU_CLK_SEL 12 +#define BIT_MASK_CPU_CLK_SEL 0x3 +#define BIT_CPU_CLK_SEL(x) \ + (((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL) +#define BITS_CPU_CLK_SEL (BIT_MASK_CPU_CLK_SEL << BIT_SHIFT_CPU_CLK_SEL) +#define BIT_CLEAR_CPU_CLK_SEL(x) ((x) & (~BITS_CPU_CLK_SEL)) +#define BIT_GET_CPU_CLK_SEL(x) \ + (((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL) +#define BIT_SET_CPU_CLK_SEL(x, v) \ + (BIT_CLEAR_CPU_CLK_SEL(x) | BIT_CPU_CLK_SEL(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_R_8051_ROMDLFW_EN BIT(11) +#define BIT_R_8051_ROMDLFW_EN BIT(11) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_CCLK_CHG_MASK BIT(11) +#define BIT_CCLK_CHG_MASK BIT(11) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_R_8051_INIT_RDY BIT(10) +#define BIT_R_8051_INIT_RDY BIT(10) #endif - #if (HALMAC_8197F_SUPPORT) - /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_FW_INIT_RDY_V1 BIT(10) +#define BIT_FW_INIT_RDY_V1 BIT(10) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_EMEM_TXBUF_CHKSUM_OK BIT(10) +#define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10) +#define BIT_EMEM_TXBUF_CHKSUM_OK BIT(10) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_EMEM_TXBUF_DW_RDY BIT(9) +#define BIT_EMEM_TXBUF_DW_RDY BIT(9) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_R_8051_GAT BIT(8) +#define BIT_R_8051_GAT BIT(8) #endif - #if (HALMAC_8197F_SUPPORT) - /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_MCU_CLK_EN BIT(8) +#define BIT_MCU_CLK_EN BIT(8) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_EMEM_CHKSUM_OK BIT(8) -#define BIT_EMEM_DW_OK BIT(7) -#define BIT_TOGGLING BIT(7) -#define BIT_DMEM_CHKSUM_OK BIT(6) -#define BIT_ACK BIT(6) +#define BIT_EMEM_CHKSUM_OK BIT(8) +#define BIT_EMEM_DW_OK BIT(7) +#define BIT_DMEM_CHKSUM_OK BIT(6) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */ +#define BIT_ACK BIT(6) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_RFINI_RDY BIT(5) +#define BIT_RFINI_RDY BIT(5) #endif - #if (HALMAC_8197F_SUPPORT) - /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_RF_INIT_RDY BIT(5) +#define BIT_RF_INIT_RDY BIT(5) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_DMEM_DW_OK BIT(5) +#define BIT_DMEM_DW_OK BIT(5) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_BBINI_RDY BIT(4) +#define BIT_BBINI_RDY BIT(4) #endif - #if (HALMAC_8197F_SUPPORT) - /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_BB_INIT_RDY BIT(4) +#define BIT_BB_INIT_RDY BIT(4) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_IMEM_CHKSUM_OK BIT(4) +#define BIT_IMEM_CHKSUM_OK BIT(4) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_MACINI_RDY BIT(3) +#define BIT_MACINI_RDY BIT(3) #endif - #if (HALMAC_8197F_SUPPORT) - /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_MAC_INIT_RDY BIT(3) +#define BIT_MAC_INIT_RDY BIT(3) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_IMEM_DW_OK BIT(3) +#define BIT_IMEM_DW_OK BIT(3) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_FWDL_CHK_RPT BIT(2) +#define BIT_FWDL_CHK_RPT BIT(2) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2) +#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_MCUFWDL_RDY BIT(1) +#define BIT_MCUFWDL_RDY BIT(1) #endif - #if (HALMAC_8197F_SUPPORT) - /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_MCU_FWDL_RDY BIT(1) +#define BIT_MCU_FWDL_RDY BIT(1) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1) +#define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1) #endif - #if (HALMAC_8197F_SUPPORT) - /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_MCU_FWDL_EN BIT(0) +#define BIT_MCU_FWDL_EN BIT(0) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */ -#define BIT_32K_PERMISSION BIT(0) +#define BIT_REQ_PS BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MCU_TST_CFG (Offset 0x0084) */ - -#define BIT_SHIFT_LBKTST 0 -#define BIT_MASK_LBKTST 0xffff -#define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST) -#define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST) - +#define BIT_SHIFT_LBKTST 0 +#define BIT_MASK_LBKTST 0xffff +#define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST) +#define BITS_LBKTST (BIT_MASK_LBKTST << BIT_SHIFT_LBKTST) +#define BIT_CLEAR_LBKTST(x) ((x) & (~BITS_LBKTST)) +#define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST) +#define BIT_SET_LBKTST(x, v) (BIT_CLEAR_LBKTST(x) | BIT_LBKTST(v)) #endif +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MCU_TST_CFG (Offset 0x0084) */ +#define BIT_SHIFT_C2H_MSG 0 +#define BIT_MASK_C2H_MSG 0xffff +#define BIT_C2H_MSG(x) (((x) & BIT_MASK_C2H_MSG) << BIT_SHIFT_C2H_MSG) +#define BITS_C2H_MSG (BIT_MASK_C2H_MSG << BIT_SHIFT_C2H_MSG) +#define BIT_CLEAR_C2H_MSG(x) ((x) & (~BITS_C2H_MSG)) +#define BIT_GET_C2H_MSG(x) (((x) >> BIT_SHIFT_C2H_MSG) & BIT_MASK_C2H_MSG) +#define BIT_SET_C2H_MSG(x, v) (BIT_CLEAR_C2H_MSG(x) | BIT_C2H_MSG(v)) -/* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */ +#endif -#define BIT_PAD_CLK_XHGE_EN BIT(3) -#define BIT_INTER_CLK_EN BIT(2) -#define BIT_EN_RPT_TXCRC BIT(1) -#define BIT_DIS_RXDMA_STS BIT(0) +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ +/* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */ -#define BIT_INTR_CTRL BIT(4) -#define BIT_SDIO_VOLTAGE BIT(3) -#define BIT_BYPASS_INIT BIT(2) +#define BIT_INT_MASK_DIS BIT(4) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */ +#define BIT_PAD_CLK_XHGE_EN BIT(3) +#define BIT_INTER_CLK_EN BIT(2) +#define BIT_EN_RPT_TXCRC BIT(1) +#define BIT_DIS_RXDMA_STS BIT(0) /* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ -#define BIT_HCI_RESUME_RDY BIT(1) -#define BIT_HCI_SUS_REQ BIT(0) +#define BIT_INTR_CTRL BIT(4) +#define BIT_SDIO_VOLTAGE BIT(3) +#define BIT_BYPASS_INIT BIT(2) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_HMEBOX_E0_E1 (Offset 0x0088) */ - - -#define BIT_SHIFT_HOST_MSG_E1 16 -#define BIT_MASK_HOST_MSG_E1 0xffff -#define BIT_HOST_MSG_E1(x) (((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1) -#define BIT_GET_HOST_MSG_E1(x) (((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1) - - -#define BIT_SHIFT_HOST_MSG_E0 0 -#define BIT_MASK_HOST_MSG_E0 0xffff -#define BIT_HOST_MSG_E0(x) (((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0) -#define BIT_GET_HOST_MSG_E0(x) (((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0) +/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ +#define BIT_HCI_RESUME_RDY BIT(1) +#define BIT_HCI_SUS_REQ BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HMEBOX_E0_E1 (Offset 0x0088) */ +#define BIT_SHIFT_HOST_MSG_E1 16 +#define BIT_MASK_HOST_MSG_E1 0xffff +#define BIT_HOST_MSG_E1(x) \ + (((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1) +#define BITS_HOST_MSG_E1 (BIT_MASK_HOST_MSG_E1 << BIT_SHIFT_HOST_MSG_E1) +#define BIT_CLEAR_HOST_MSG_E1(x) ((x) & (~BITS_HOST_MSG_E1)) +#define BIT_GET_HOST_MSG_E1(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1) +#define BIT_SET_HOST_MSG_E1(x, v) \ + (BIT_CLEAR_HOST_MSG_E1(x) | BIT_HOST_MSG_E1(v)) + +#define BIT_SHIFT_HOST_MSG_E0 0 +#define BIT_MASK_HOST_MSG_E0 0xffff +#define BIT_HOST_MSG_E0(x) \ + (((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0) +#define BITS_HOST_MSG_E0 (BIT_MASK_HOST_MSG_E0 << BIT_SHIFT_HOST_MSG_E0) +#define BIT_CLEAR_HOST_MSG_E0(x) ((x) & (~BITS_HOST_MSG_E0)) +#define BIT_GET_HOST_MSG_E0(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0) +#define BIT_SET_HOST_MSG_E0(x, v) \ + (BIT_CLEAR_HOST_MSG_E0(x) | BIT_HOST_MSG_E0(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_RESPONSE_TIMER (Offset 0x10250088) */ - -#define BIT_SHIFT_CMDIN_2RESP_TIMER 0 -#define BIT_MASK_CMDIN_2RESP_TIMER 0xffff -#define BIT_CMDIN_2RESP_TIMER(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER) -#define BIT_GET_CMDIN_2RESP_TIMER(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER) - +#define BIT_SHIFT_CMDIN_2RESP_TIMER 0 +#define BIT_MASK_CMDIN_2RESP_TIMER 0xffff +#define BIT_CMDIN_2RESP_TIMER(x) \ + (((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER) +#define BITS_CMDIN_2RESP_TIMER \ + (BIT_MASK_CMDIN_2RESP_TIMER << BIT_SHIFT_CMDIN_2RESP_TIMER) +#define BIT_CLEAR_CMDIN_2RESP_TIMER(x) ((x) & (~BITS_CMDIN_2RESP_TIMER)) +#define BIT_GET_CMDIN_2RESP_TIMER(x) \ + (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER) +#define BIT_SET_CMDIN_2RESP_TIMER(x, v) \ + (BIT_CLEAR_CMDIN_2RESP_TIMER(x) | BIT_CMDIN_2RESP_TIMER(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ +#define BIT_SHIFT_SDIO_CMD_CRC 1 +#define BIT_MASK_SDIO_CMD_CRC 0x7f +#define BIT_SDIO_CMD_CRC(x) \ + (((x) & BIT_MASK_SDIO_CMD_CRC) << BIT_SHIFT_SDIO_CMD_CRC) +#define BITS_SDIO_CMD_CRC (BIT_MASK_SDIO_CMD_CRC << BIT_SHIFT_SDIO_CMD_CRC) +#define BIT_CLEAR_SDIO_CMD_CRC(x) ((x) & (~BITS_SDIO_CMD_CRC)) +#define BIT_GET_SDIO_CMD_CRC(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_CRC) & BIT_MASK_SDIO_CMD_CRC) +#define BIT_SET_SDIO_CMD_CRC(x, v) \ + (BIT_CLEAR_SDIO_CMD_CRC(x) | BIT_SDIO_CMD_CRC(v)) -#define BIT_SHIFT_SDIO_CMD_CRC 1 -#define BIT_MASK_SDIO_CMD_CRC 0x7f -#define BIT_SDIO_CMD_CRC(x) (((x) & BIT_MASK_SDIO_CMD_CRC) << BIT_SHIFT_SDIO_CMD_CRC) -#define BIT_GET_SDIO_CMD_CRC(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC) & BIT_MASK_SDIO_CMD_CRC) - -#define BIT_SDIO_CMD_E_BIT BIT(0) +#define BIT_SDIO_CMD_E_BIT BIT(0) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ - -#define BIT_SHIFT_SDIO_CMD_CRC_V1 0 -#define BIT_MASK_SDIO_CMD_CRC_V1 0xff -#define BIT_SDIO_CMD_CRC_V1(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1) -#define BIT_GET_SDIO_CMD_CRC_V1(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1) - +#define BIT_SHIFT_SDIO_CMD_CRC_V1 0 +#define BIT_MASK_SDIO_CMD_CRC_V1 0xff +#define BIT_SDIO_CMD_CRC_V1(x) \ + (((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1) +#define BITS_SDIO_CMD_CRC_V1 \ + (BIT_MASK_SDIO_CMD_CRC_V1 << BIT_SHIFT_SDIO_CMD_CRC_V1) +#define BIT_CLEAR_SDIO_CMD_CRC_V1(x) ((x) & (~BITS_SDIO_CMD_CRC_V1)) +#define BIT_GET_SDIO_CMD_CRC_V1(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1) +#define BIT_SET_SDIO_CMD_CRC_V1(x, v) \ + (BIT_CLEAR_SDIO_CMD_CRC_V1(x) | BIT_SDIO_CMD_CRC_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HMEBOX_E2_E3 (Offset 0x008C) */ +#define BIT_SHIFT_HOST_MSG_E3 16 +#define BIT_MASK_HOST_MSG_E3 0xffff +#define BIT_HOST_MSG_E3(x) \ + (((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3) +#define BITS_HOST_MSG_E3 (BIT_MASK_HOST_MSG_E3 << BIT_SHIFT_HOST_MSG_E3) +#define BIT_CLEAR_HOST_MSG_E3(x) ((x) & (~BITS_HOST_MSG_E3)) +#define BIT_GET_HOST_MSG_E3(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3) +#define BIT_SET_HOST_MSG_E3(x, v) \ + (BIT_CLEAR_HOST_MSG_E3(x) | BIT_HOST_MSG_E3(v)) + +#define BIT_SHIFT_HOST_MSG_E2 0 +#define BIT_MASK_HOST_MSG_E2 0xffff +#define BIT_HOST_MSG_E2(x) \ + (((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2) +#define BITS_HOST_MSG_E2 (BIT_MASK_HOST_MSG_E2 << BIT_SHIFT_HOST_MSG_E2) +#define BIT_CLEAR_HOST_MSG_E2(x) ((x) & (~BITS_HOST_MSG_E2)) +#define BIT_GET_HOST_MSG_E2(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2) +#define BIT_SET_HOST_MSG_E2(x, v) \ + (BIT_CLEAR_HOST_MSG_E2(x) | BIT_HOST_MSG_E2(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HOST_MSG_E3 16 -#define BIT_MASK_HOST_MSG_E3 0xffff -#define BIT_HOST_MSG_E3(x) (((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3) -#define BIT_GET_HOST_MSG_E3(x) (((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3) - - -#define BIT_SHIFT_HOST_MSG_E2 0 -#define BIT_MASK_HOST_MSG_E2 0xffff -#define BIT_HOST_MSG_E2(x) (((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2) -#define BIT_GET_HOST_MSG_E2(x) (((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_WLLPSOP_EABM BIT(31) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_EABM BIT(31) +#define BIT_WLLPSOP_ACKF BIT(30) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_ACKF BIT(30) +#define BIT_TXFIFO_TH_INT BIT(30) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_DLDM BIT(29) +#define BIT_WLLPSOP_DLDM BIT(29) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_AFEP BIT(29) +#define BIT_WLLPSOP_AFEP BIT(29) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_ESWR BIT(28) +#define BIT_WLLPSOP_ESWR BIT(28) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_LPS_DIS_SW BIT(28) +#define BIT_LPS_DIS_SW BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_PWMM BIT(27) -#define BIT_WLLPSOP_EECK BIT(26) +#define BIT_WLLPSOP_PWMM BIT(27) +#define BIT_WLLPSOP_EECK BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_ELDO BIT(25) +#define BIT_WLLPSOP_ELDO BIT(25) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_WLMACOFF BIT(25) +#define BIT_WLLPSOP_WLMACOFF BIT(25) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_EXTAL BIT(24) +#define BIT_WLLPSOP_EXTAL BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_LPS_BB_REG_EN BIT(23) +#define BIT_LPS_BB_REG_EN BIT(23) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WL_SYNPON_VOLTSPDN BIT(23) +#define BIT_WL_SYNPON_VOLTSPDN BIT(23) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_LPS_BB_PWR_EN BIT(22) +#define BIT_LPS_BB_PWR_EN BIT(22) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_WLBBOFF BIT(22) +#define BIT_WLLPSOP_WLBBOFF BIT(22) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_LPS_BB_GLB_EN BIT(21) +#define BIT_LPS_BB_GLB_EN BIT(21) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_WLMEM_DS BIT(21) +#define BIT_WLLPSOP_WLMEM_DS BIT(21) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_SUS_DIS_SW BIT(15) -#define BIT_SUS_SKP_PAGE0_ALD BIT(14) -#define BIT_SUS_LDO_SLEEP BIT(13) -#define BIT_PFM_EN_ZCD BIT(12) +#define BIT_WLLPSOP_LDO_WAIT_TIME BIT(20) +#define BIT_WLLPSOP_ANA_CLK_DIVISION_2 BIT(19) +#define BIT_AFE_BCN BIT(18) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_SUS_DIS_SW BIT(15) +#define BIT_SUS_SKP_PAGE0_ALD BIT(14) +#define BIT_SUS_LDO_SLEEP BIT(13) +#define BIT_PFM_EN_ZCD BIT(12) -/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12 -#define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf -#define BIT_LPLDH12_VADJ_STEP_DN(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN) -#define BIT_GET_LPLDH12_VADJ_STEP_DN(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) & BIT_MASK_LPLDH12_VADJ_STEP_DN) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12 +#define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf +#define BIT_LPLDH12_VADJ_STEP_DN(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN) \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN) +#define BITS_LPLDH12_VADJ_STEP_DN \ + (BIT_MASK_LPLDH12_VADJ_STEP_DN << BIT_SHIFT_LPLDH12_VADJ_STEP_DN) +#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN(x) ((x) & (~BITS_LPLDH12_VADJ_STEP_DN)) +#define BIT_GET_LPLDH12_VADJ_STEP_DN(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) & \ + BIT_MASK_LPLDH12_VADJ_STEP_DN) +#define BIT_SET_LPLDH12_VADJ_STEP_DN(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_STEP_DN(x) | BIT_LPLDH12_VADJ_STEP_DN(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_KEEP_RFC_EN BIT(11) -#define BIT_MACON_NO_RFCISO_RELEASE BIT(10) -#define BIT_MACON_NO_AFEPORT_PWR BIT(9) -#define BIT_MACON_NO_CPU_EN BIT(8) +#define BIT_KEEP_RFC_EN BIT(11) +#define BIT_MACON_NO_RFCISO_RELEASE BIT(10) +#define BIT_MACON_NO_AFEPORT_PWR BIT(9) +#define BIT_MACON_NO_CPU_EN BIT(8) #endif - #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_SHIFT_V15ADJ_L1_STEP_DN 8 +#define BIT_MASK_V15ADJ_L1_STEP_DN 0x7 +#define BIT_V15ADJ_L1_STEP_DN(x) \ + (((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN) +#define BITS_V15ADJ_L1_STEP_DN \ + (BIT_MASK_V15ADJ_L1_STEP_DN << BIT_SHIFT_V15ADJ_L1_STEP_DN) +#define BIT_CLEAR_V15ADJ_L1_STEP_DN(x) ((x) & (~BITS_V15ADJ_L1_STEP_DN)) +#define BIT_GET_V15ADJ_L1_STEP_DN(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN) +#define BIT_SET_V15ADJ_L1_STEP_DN(x, v) \ + (BIT_CLEAR_V15ADJ_L1_STEP_DN(x) | BIT_V15ADJ_L1_STEP_DN(v)) + +#endif -#define BIT_SHIFT_V15ADJ_L1_STEP_DN 8 -#define BIT_MASK_V15ADJ_L1_STEP_DN 0x7 -#define BIT_V15ADJ_L1_STEP_DN(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN) -#define BIT_GET_V15ADJ_L1_STEP_DN(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN) +#if (HALMAC_8822C_SUPPORT) -#define BIT_REGU_32K_CLK_EN BIT(1) -#define BIT_DRV_WLAN_INT_CLR BIT(1) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#endif +#define BIT_SHIFT_V15ADJ_L1_STEP_DN_V1 8 +#define BIT_MASK_V15ADJ_L1_STEP_DN_V1 0xf +#define BIT_V15ADJ_L1_STEP_DN_V1(x) \ + (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_V1) \ + << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1) +#define BITS_V15ADJ_L1_STEP_DN_V1 \ + (BIT_MASK_V15ADJ_L1_STEP_DN_V1 << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1) +#define BIT_CLEAR_V15ADJ_L1_STEP_DN_V1(x) ((x) & (~BITS_V15ADJ_L1_STEP_DN_V1)) +#define BIT_GET_V15ADJ_L1_STEP_DN_V1(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_V1) & \ + BIT_MASK_V15ADJ_L1_STEP_DN_V1) +#define BIT_SET_V15ADJ_L1_STEP_DN_V1(x, v) \ + (BIT_CLEAR_V15ADJ_L1_STEP_DN_V1(x) | BIT_V15ADJ_L1_STEP_DN_V1(v)) +#define BIT_FORCE_LEAVE_LPS BIT(3) +#define BIT_SW_AFE_MODE BIT(2) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WL_LPS_EN BIT(0) +#define BIT_REGU_32K_CLK_EN BIT(1) +#define BIT_DRV_WLAN_INT_CLR BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_WL_LPS_EN BIT(0) -/* 2 REG_SDIO_HSISR (Offset 0x10250090) */ +#endif -#define BIT_DRV_WLAN_INT BIT(0) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_SDIO_HSIMR (Offset 0x10250091) */ +/* 2 REG_SDIO_HSISR (Offset 0x10250090) */ -#define BIT_HISR_MASK BIT(0) +#define BIT_DRV_WLAN_INT BIT(0) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SDIO_HSIMR (Offset 0x10250091) */ +#define BIT_HISR_MASK BIT(0) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#endif -#define BIT_BB_DBG_SEL_AFE_SDM_V3 BIT(31) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_BB_DBG_SEL_AFE_SDM_V3 BIT(31) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ -#define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31) +#define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ -#define BIT_ORDER_SDM BIT(30) -#define BIT_RFE_SEL_SDM BIT(29) - -#define BIT_SHIFT_REF_SEL 25 -#define BIT_MASK_REF_SEL 0xf -#define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL) -#define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL) +#define BIT_ORDER_SDM BIT(30) +#define BIT_RFE_SEL_SDM BIT(29) +#define BIT_SHIFT_REF_SEL 25 +#define BIT_MASK_REF_SEL 0xf +#define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL) +#define BITS_REF_SEL (BIT_MASK_REF_SEL << BIT_SHIFT_REF_SEL) +#define BIT_CLEAR_REF_SEL(x) ((x) & (~BITS_REF_SEL)) +#define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL) +#define BIT_SET_REF_SEL(x, v) (BIT_CLEAR_REF_SEL(x) | BIT_REF_SEL(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ - -#define BIT_SHIFT_F0F_SDM_V2 12 -#define BIT_MASK_F0F_SDM_V2 0x1fff -#define BIT_F0F_SDM_V2(x) (((x) & BIT_MASK_F0F_SDM_V2) << BIT_SHIFT_F0F_SDM_V2) -#define BIT_GET_F0F_SDM_V2(x) (((x) >> BIT_SHIFT_F0F_SDM_V2) & BIT_MASK_F0F_SDM_V2) - +#define BIT_SHIFT_F0F_SDM_V2 12 +#define BIT_MASK_F0F_SDM_V2 0x1fff +#define BIT_F0F_SDM_V2(x) (((x) & BIT_MASK_F0F_SDM_V2) << BIT_SHIFT_F0F_SDM_V2) +#define BITS_F0F_SDM_V2 (BIT_MASK_F0F_SDM_V2 << BIT_SHIFT_F0F_SDM_V2) +#define BIT_CLEAR_F0F_SDM_V2(x) ((x) & (~BITS_F0F_SDM_V2)) +#define BIT_GET_F0F_SDM_V2(x) \ + (((x) >> BIT_SHIFT_F0F_SDM_V2) & BIT_MASK_F0F_SDM_V2) +#define BIT_SET_F0F_SDM_V2(x, v) (BIT_CLEAR_F0F_SDM_V2(x) | BIT_F0F_SDM_V2(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_F0F_SDM 12 +#define BIT_MASK_F0F_SDM 0x1fff +#define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM) +#define BITS_F0F_SDM (BIT_MASK_F0F_SDM << BIT_SHIFT_F0F_SDM) +#define BIT_CLEAR_F0F_SDM(x) ((x) & (~BITS_F0F_SDM)) +#define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM) +#define BIT_SET_F0F_SDM(x, v) (BIT_CLEAR_F0F_SDM(x) | BIT_F0F_SDM(v)) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_F0F_SDM 12 -#define BIT_MASK_F0F_SDM 0x1fff -#define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM) -#define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_F0N_SDM_V2 9 +#define BIT_MASK_F0N_SDM_V2 0x7 +#define BIT_F0N_SDM_V2(x) (((x) & BIT_MASK_F0N_SDM_V2) << BIT_SHIFT_F0N_SDM_V2) +#define BITS_F0N_SDM_V2 (BIT_MASK_F0N_SDM_V2 << BIT_SHIFT_F0N_SDM_V2) +#define BIT_CLEAR_F0N_SDM_V2(x) ((x) & (~BITS_F0N_SDM_V2)) +#define BIT_GET_F0N_SDM_V2(x) \ + (((x) >> BIT_SHIFT_F0N_SDM_V2) & BIT_MASK_F0N_SDM_V2) +#define BIT_SET_F0N_SDM_V2(x, v) (BIT_CLEAR_F0N_SDM_V2(x) | BIT_F0N_SDM_V2(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_F0N_SDM 9 +#define BIT_MASK_F0N_SDM 0x7 +#define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM) +#define BITS_F0N_SDM (BIT_MASK_F0N_SDM << BIT_SHIFT_F0N_SDM) +#define BIT_CLEAR_F0N_SDM(x) ((x) & (~BITS_F0N_SDM)) +#define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM) +#define BIT_SET_F0N_SDM(x, v) (BIT_CLEAR_F0N_SDM(x) | BIT_F0N_SDM(v)) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_F0N_SDM_V2 9 -#define BIT_MASK_F0N_SDM_V2 0x7 -#define BIT_F0N_SDM_V2(x) (((x) & BIT_MASK_F0N_SDM_V2) << BIT_SHIFT_F0N_SDM_V2) -#define BIT_GET_F0N_SDM_V2(x) (((x) >> BIT_SHIFT_F0N_SDM_V2) & BIT_MASK_F0N_SDM_V2) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_DIVN_SDM_V2 3 +#define BIT_MASK_DIVN_SDM_V2 0x3f +#define BIT_DIVN_SDM_V2(x) \ + (((x) & BIT_MASK_DIVN_SDM_V2) << BIT_SHIFT_DIVN_SDM_V2) +#define BITS_DIVN_SDM_V2 (BIT_MASK_DIVN_SDM_V2 << BIT_SHIFT_DIVN_SDM_V2) +#define BIT_CLEAR_DIVN_SDM_V2(x) ((x) & (~BITS_DIVN_SDM_V2)) +#define BIT_GET_DIVN_SDM_V2(x) \ + (((x) >> BIT_SHIFT_DIVN_SDM_V2) & BIT_MASK_DIVN_SDM_V2) +#define BIT_SET_DIVN_SDM_V2(x, v) \ + (BIT_CLEAR_DIVN_SDM_V2(x) | BIT_DIVN_SDM_V2(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_DIVN_SDM 3 +#define BIT_MASK_DIVN_SDM 0x3f +#define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM) +#define BITS_DIVN_SDM (BIT_MASK_DIVN_SDM << BIT_SHIFT_DIVN_SDM) +#define BIT_CLEAR_DIVN_SDM(x) ((x) & (~BITS_DIVN_SDM)) +#define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM) +#define BIT_SET_DIVN_SDM(x, v) (BIT_CLEAR_DIVN_SDM(x) | BIT_DIVN_SDM(v)) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_F0N_SDM 9 -#define BIT_MASK_F0N_SDM 0x7 -#define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM) -#define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_DITHER_SDM_V2 0 +#define BIT_MASK_DITHER_SDM_V2 0x7 +#define BIT_DITHER_SDM_V2(x) \ + (((x) & BIT_MASK_DITHER_SDM_V2) << BIT_SHIFT_DITHER_SDM_V2) +#define BITS_DITHER_SDM_V2 (BIT_MASK_DITHER_SDM_V2 << BIT_SHIFT_DITHER_SDM_V2) +#define BIT_CLEAR_DITHER_SDM_V2(x) ((x) & (~BITS_DITHER_SDM_V2)) +#define BIT_GET_DITHER_SDM_V2(x) \ + (((x) >> BIT_SHIFT_DITHER_SDM_V2) & BIT_MASK_DITHER_SDM_V2) +#define BIT_SET_DITHER_SDM_V2(x, v) \ + (BIT_CLEAR_DITHER_SDM_V2(x) | BIT_DITHER_SDM_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_GPIO_DEBOUNCE_CTRL (Offset 0x0098) */ -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_WLGP_DBC1EN BIT(15) +#define BIT_SHIFT_WLGP_DBC1 8 +#define BIT_MASK_WLGP_DBC1 0xf +#define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1) +#define BITS_WLGP_DBC1 (BIT_MASK_WLGP_DBC1 << BIT_SHIFT_WLGP_DBC1) +#define BIT_CLEAR_WLGP_DBC1(x) ((x) & (~BITS_WLGP_DBC1)) +#define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1) +#define BIT_SET_WLGP_DBC1(x, v) (BIT_CLEAR_WLGP_DBC1(x) | BIT_WLGP_DBC1(v)) -#define BIT_SHIFT_DIVN_SDM_V2 3 -#define BIT_MASK_DIVN_SDM_V2 0x3f -#define BIT_DIVN_SDM_V2(x) (((x) & BIT_MASK_DIVN_SDM_V2) << BIT_SHIFT_DIVN_SDM_V2) -#define BIT_GET_DIVN_SDM_V2(x) (((x) >> BIT_SHIFT_DIVN_SDM_V2) & BIT_MASK_DIVN_SDM_V2) +#define BIT_WLGP_DBC0EN BIT(7) +#define BIT_SHIFT_WLGP_DBC0 0 +#define BIT_MASK_WLGP_DBC0 0xf +#define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0) +#define BITS_WLGP_DBC0 (BIT_MASK_WLGP_DBC0 << BIT_SHIFT_WLGP_DBC0) +#define BIT_CLEAR_WLGP_DBC0(x) ((x) & (~BITS_WLGP_DBC0)) +#define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0) +#define BIT_SET_WLGP_DBC0(x, v) (BIT_CLEAR_WLGP_DBC0(x) | BIT_WLGP_DBC0(v)) -#endif +/* 2 REG_RPWM2 (Offset 0x009C) */ +#define BIT_SHIFT_RPWM2 16 +#define BIT_MASK_RPWM2 0xffff +#define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2) +#define BITS_RPWM2 (BIT_MASK_RPWM2 << BIT_SHIFT_RPWM2) +#define BIT_CLEAR_RPWM2(x) ((x) & (~BITS_RPWM2)) +#define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2) +#define BIT_SET_RPWM2(x, v) (BIT_CLEAR_RPWM2(x) | BIT_RPWM2(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +/* 2 REG_SYSON_FSM_MON (Offset 0x00A0) */ +#define BIT_SHIFT_FSM_MON_SEL 24 +#define BIT_MASK_FSM_MON_SEL 0x7 +#define BIT_FSM_MON_SEL(x) \ + (((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL) +#define BITS_FSM_MON_SEL (BIT_MASK_FSM_MON_SEL << BIT_SHIFT_FSM_MON_SEL) +#define BIT_CLEAR_FSM_MON_SEL(x) ((x) & (~BITS_FSM_MON_SEL)) +#define BIT_GET_FSM_MON_SEL(x) \ + (((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL) +#define BIT_SET_FSM_MON_SEL(x, v) \ + (BIT_CLEAR_FSM_MON_SEL(x) | BIT_FSM_MON_SEL(v)) -#define BIT_SHIFT_DIVN_SDM 3 -#define BIT_MASK_DIVN_SDM 0x3f -#define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM) -#define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM) +#define BIT_DOP_ELDO BIT(23) +#define BIT_FSM_MON_UPD BIT(15) +#define BIT_SHIFT_FSM_PAR 0 +#define BIT_MASK_FSM_PAR 0x7fff +#define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR) +#define BITS_FSM_PAR (BIT_MASK_FSM_PAR << BIT_SHIFT_FSM_PAR) +#define BIT_CLEAR_FSM_PAR(x) ((x) & (~BITS_FSM_PAR)) +#define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR) +#define BIT_SET_FSM_PAR(x, v) (BIT_CLEAR_FSM_PAR(x) | BIT_FSM_PAR(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ +#define BIT_SHIFT_TSFT_SEL_V1 0 +#define BIT_MASK_TSFT_SEL_V1 0x7 +#define BIT_TSFT_SEL_V1(x) \ + (((x) & BIT_MASK_TSFT_SEL_V1) << BIT_SHIFT_TSFT_SEL_V1) +#define BITS_TSFT_SEL_V1 (BIT_MASK_TSFT_SEL_V1 << BIT_SHIFT_TSFT_SEL_V1) +#define BIT_CLEAR_TSFT_SEL_V1(x) ((x) & (~BITS_TSFT_SEL_V1)) +#define BIT_GET_TSFT_SEL_V1(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_V1) & BIT_MASK_TSFT_SEL_V1) +#define BIT_SET_TSFT_SEL_V1(x, v) \ + (BIT_CLEAR_TSFT_SEL_V1(x) | BIT_TSFT_SEL_V1(v)) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_DITHER_SDM_V2 0 -#define BIT_MASK_DITHER_SDM_V2 0x7 -#define BIT_DITHER_SDM_V2(x) (((x) & BIT_MASK_DITHER_SDM_V2) << BIT_SHIFT_DITHER_SDM_V2) -#define BIT_GET_DITHER_SDM_V2(x) (((x) >> BIT_SHIFT_DITHER_SDM_V2) & BIT_MASK_DITHER_SDM_V2) +/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ +#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0 +#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7 +#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) +#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1 \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ + ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) & \ + BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1(x) | \ + BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ +#define BIT_BT_INT_EN BIT(31) -/* 2 REG_GPIO_DEBOUNCE_CTRL (Offset 0x0098) */ +#define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16 +#define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff +#define BIT_RD_WR_WIFI_BT_INFO(x) \ + (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO) +#define BITS_RD_WR_WIFI_BT_INFO \ + (BIT_MASK_RD_WR_WIFI_BT_INFO << BIT_SHIFT_RD_WR_WIFI_BT_INFO) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) ((x) & (~BITS_RD_WR_WIFI_BT_INFO)) +#define BIT_GET_RD_WR_WIFI_BT_INFO(x) \ + (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO) +#define BIT_SET_RD_WR_WIFI_BT_INFO(x, v) \ + (BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) | BIT_RD_WR_WIFI_BT_INFO(v)) + +#endif -#define BIT_WLGP_DBC1EN BIT(15) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WLGP_DBC1 8 -#define BIT_MASK_WLGP_DBC1 0xf -#define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1) -#define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1) +/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ -#define BIT_WLGP_DBC0EN BIT(7) +#define BIT_PMC_WR_OVF BIT(8) -#define BIT_SHIFT_WLGP_DBC0 0 -#define BIT_MASK_WLGP_DBC0 0xf -#define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0) -#define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0) +#define BIT_SHIFT_WLPMC_ERRINT 0 +#define BIT_MASK_WLPMC_ERRINT 0xff +#define BIT_WLPMC_ERRINT(x) \ + (((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT) +#define BITS_WLPMC_ERRINT (BIT_MASK_WLPMC_ERRINT << BIT_SHIFT_WLPMC_ERRINT) +#define BIT_CLEAR_WLPMC_ERRINT(x) ((x) & (~BITS_WLPMC_ERRINT)) +#define BIT_GET_WLPMC_ERRINT(x) \ + (((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT) +#define BIT_SET_WLPMC_ERRINT(x, v) \ + (BIT_CLEAR_WLPMC_ERRINT(x) | BIT_WLPMC_ERRINT(v)) +#endif -/* 2 REG_RPWM2 (Offset 0x009C) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ -#define BIT_SHIFT_RPWM2 16 -#define BIT_MASK_RPWM2 0xffff -#define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2) -#define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2) +#define BIT_SHIFT_SEL_V 30 +#define BIT_MASK_SEL_V 0x3 +#define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V) +#define BITS_SEL_V (BIT_MASK_SEL_V << BIT_SHIFT_SEL_V) +#define BIT_CLEAR_SEL_V(x) ((x) & (~BITS_SEL_V)) +#define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V) +#define BIT_SET_SEL_V(x, v) (BIT_CLEAR_SEL_V(x) | BIT_SEL_V(v)) +#define BIT_SEL_LDO_PC BIT(29) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#define BIT_SHIFT_CK_MON_SEL_V2 26 +#define BIT_MASK_CK_MON_SEL_V2 0x7 +#define BIT_CK_MON_SEL_V2(x) \ + (((x) & BIT_MASK_CK_MON_SEL_V2) << BIT_SHIFT_CK_MON_SEL_V2) +#define BITS_CK_MON_SEL_V2 (BIT_MASK_CK_MON_SEL_V2 << BIT_SHIFT_CK_MON_SEL_V2) +#define BIT_CLEAR_CK_MON_SEL_V2(x) ((x) & (~BITS_CK_MON_SEL_V2)) +#define BIT_GET_CK_MON_SEL_V2(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL_V2) & BIT_MASK_CK_MON_SEL_V2) +#define BIT_SET_CK_MON_SEL_V2(x, v) \ + (BIT_CLEAR_CK_MON_SEL_V2(x) | BIT_CK_MON_SEL_V2(v)) -/* 2 REG_SYSON_FSM_MON (Offset 0x00A0) */ +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ + +#define BIT_SHIFT_CK_MON_SEL 26 +#define BIT_MASK_CK_MON_SEL 0x7 +#define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL) +#define BITS_CK_MON_SEL (BIT_MASK_CK_MON_SEL << BIT_SHIFT_CK_MON_SEL) +#define BIT_CLEAR_CK_MON_SEL(x) ((x) & (~BITS_CK_MON_SEL)) +#define BIT_GET_CK_MON_SEL(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL) +#define BIT_SET_CK_MON_SEL(x, v) (BIT_CLEAR_CK_MON_SEL(x) | BIT_CK_MON_SEL(v)) -#define BIT_SHIFT_FSM_MON_SEL 24 -#define BIT_MASK_FSM_MON_SEL 0x7 -#define BIT_FSM_MON_SEL(x) (((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL) -#define BIT_GET_FSM_MON_SEL(x) (((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL) +#endif -#define BIT_DOP_ELDO BIT(23) -#define BIT_FSM_MON_UPD BIT(15) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_FSM_PAR 0 -#define BIT_MASK_FSM_PAR 0x7fff -#define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR) -#define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR) +/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#define BIT_CK_MON_EN BIT(25) +#define BIT_FREF_EDGE BIT(24) +#define BIT_CK320M_EN BIT(23) +#define BIT_CK_5M_EN BIT(22) +#define BIT_TESTEN BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31) -/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TSFT_SEL_V1 0 -#define BIT_MASK_TSFT_SEL_V1 0x7 -#define BIT_TSFT_SEL_V1(x) (((x) & BIT_MASK_TSFT_SEL_V1) << BIT_SHIFT_TSFT_SEL_V1) -#define BIT_GET_TSFT_SEL_V1(x) (((x) >> BIT_SHIFT_TSFT_SEL_V1) & BIT_MASK_TSFT_SEL_V1) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_PSTIMER_2_MSK BIT(31) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30) -/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0 -#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7 -#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_PSTIMER_1_MSK BIT(30) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_PSTIMEOUT_MSK BIT(29) -/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ +#endif -#define BIT_BT_INT_EN BIT(31) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16 -#define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff -#define BIT_RD_WR_WIFI_BT_INFO(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO) -#define BIT_GET_RD_WR_WIFI_BT_INFO(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_PSTIMER_0_MSK BIT(29) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_GTINT4_MSK BIT(28) +#define BIT_GTINT4 BIT(28) +#define BIT_GTINT3_MSK BIT(27) +#define BIT_GTINT3 BIT(27) +#define BIT_TXBCN0ERR_MSK BIT(26) +#define BIT_TXBCN0ERR BIT(26) +#define BIT_TXBCN0OK_MSK BIT(25) +#define BIT_TXBCN0OK BIT(25) +#define BIT_TSF_BIT32_TOGGLE_MSK BIT(24) +#define BIT_TSF_BIT32_TOGGLE BIT(24) -/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ +#endif -#define BIT_PMC_WR_OVF BIT(8) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_WLPMC_ERRINT 0 -#define BIT_MASK_WLPMC_ERRINT 0xff -#define BIT_WLPMC_ERRINT(x) (((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT) -#define BIT_GET_WLPMC_ERRINT(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_TXDMA_START_INT_MSK BIT(23) +#define BIT_TXDMA_STOP_INT_MSK BIT(22) +#define BIT_HISR7_IND_MSK BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_BCNDMAINT0_MSK BIT(20) +#define BIT_BCNDMAINT0 BIT(20) -/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_SEL_V 30 -#define BIT_MASK_SEL_V 0x3 -#define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V) -#define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR6_IND_MSK BIT(19) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR5_MSK BIT(18) -/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#endif -#define BIT_TXFIFO_TH_INT BIT(30) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR5_IND_MSK BIT(18) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +/* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_SEL_LDO_PC BIT(29) +#define BIT_HISR4_MSK BIT(17) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR4_IND_MSK BIT(17) -/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CK_MON_SEL_V2 26 -#define BIT_MASK_CK_MON_SEL_V2 0x7 -#define BIT_CK_MON_SEL_V2(x) (((x) & BIT_MASK_CK_MON_SEL_V2) << BIT_SHIFT_CK_MON_SEL_V2) -#define BIT_GET_CK_MON_SEL_V2(x) (((x) >> BIT_SHIFT_CK_MON_SEL_V2) & BIT_MASK_CK_MON_SEL_V2) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_BCNDERR0_MSK BIT(16) +#define BIT_BCNDERR0 BIT(16) +#define BIT_HSISR_IND_ON_INT_MSK BIT(15) +#define BIT_HSISR_IND_ON_INT BIT(15) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_BCNDMAINT_E_MSK BIT(14) -/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_CK_MON_SEL 26 -#define BIT_MASK_CK_MON_SEL 0x7 -#define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL) -#define BIT_GET_CK_MON_SEL(x) (((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR3_IND_INT_MSK BIT(14) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR3_IND_MSK BIT(14) -/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#endif -#define BIT_CK_MON_EN BIT(25) -#define BIT_FREF_EDGE BIT(24) -#define BIT_CK320M_EN BIT(23) -#define BIT_CK_5M_EN BIT(22) -#define BIT_TESTEN BIT(21) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR2_IND_INT_MSK BIT(13) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31) -#define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30) -#define BIT_PSTIMEOUT_MSK BIT(29) -#define BIT_GTINT4_MSK BIT(28) -#define BIT_GTINT3_MSK BIT(27) -#define BIT_TXBCN0ERR_MSK BIT(26) -#define BIT_TXBCN0OK_MSK BIT(25) -#define BIT_TSF_BIT32_TOGGLE_MSK BIT(24) -#define BIT_BCNDMAINT0_MSK BIT(20) -#define BIT_BCNDERR0_MSK BIT(16) -#define BIT_HSISR_IND_ON_INT_MSK BIT(15) +#define BIT_HISR2_IND_MSK BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_HIMR0 (Offset 0x00B0) */ + +#define BIT_CTWEND_MSK BIT(12) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_BCNDMAINT_E_MSK BIT(14) +#define BIT_HISR1_IND_MSK BIT(11) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_HISR3_IND_INT_MSK BIT(14) -#define BIT_HISR2_IND_INT_MSK BIT(13) +#define BIT_HISR1_IND_INT_MSK BIT(11) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_HIMR0 (Offset 0x00B0) */ + +#define BIT_C2HCMD_MSK BIT(10) +#define BIT_C2HCMD BIT(10) +#define BIT_CPWM2_MSK BIT(9) +#define BIT_CPWM2 BIT(9) +#define BIT_CPWM_MSK BIT(8) +#define BIT_CPWM BIT(8) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_CTWEND_MSK BIT(12) -#define BIT_HISR1_IND_MSK BIT(11) +#define BIT_HIGHDOK_MSK BIT(7) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ + +#define BIT_TXDMAOK_CHANNEL15_MSK BIT(7) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_HISR1_IND_INT_MSK BIT(11) +#define BIT_MGTDOK_MSK BIT(6) #endif +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR0 (Offset 0x00B0) */ + +#define BIT_TXDMAOK_CHANNEL14_MSK BIT(6) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_C2HCMD_MSK BIT(10) -#define BIT_CPWM2_MSK BIT(9) -#define BIT_CPWM_MSK BIT(8) -#define BIT_HIGHDOK_MSK BIT(7) -#define BIT_MGTDOK_MSK BIT(6) -#define BIT_BKDOK_MSK BIT(5) -#define BIT_BEDOK_MSK BIT(4) -#define BIT_VIDOK_MSK BIT(3) -#define BIT_VODOK_MSK BIT(2) -#define BIT_RDU_MSK BIT(1) -#define BIT_RXOK_MSK BIT(0) +#define BIT_BKDOK_MSK BIT(5) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_TXDMAOK_CHANNEL3_MSK BIT(5) -/* 2 REG_HISR0 (Offset 0x00B4) */ +#endif -#define BIT_PSTIMEOUT2 BIT(31) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_BEDOK_MSK BIT(4) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_HISR0 (Offset 0x00B4) */ +/* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_TIMEOUT_INTERRUPT2 BIT(31) +#define BIT_TXDMAOK_CHANNEL2_MSK BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_VIDOK_MSK BIT(3) -/* 2 REG_HISR0 (Offset 0x00B4) */ +#endif -#define BIT_PSTIMEOUT1 BIT(30) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_TXDMAOK_CHANNEL1_MSK BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_HISR0 (Offset 0x00B4) */ +/* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_TIMEOUT_INTERRUTP1 BIT(30) +#define BIT_VODOK_MSK BIT(2) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_TXDMAOK_CHANNEL0_MSK BIT(2) -/* 2 REG_HISR0 (Offset 0x00B4) */ +#endif -#define BIT_PSTIMEOUT BIT(29) -#define BIT_GTINT4 BIT(28) -#define BIT_GTINT3 BIT(27) -#define BIT_TXBCN0ERR BIT(26) -#define BIT_TXBCN0OK BIT(25) -#define BIT_TSF_BIT32_TOGGLE BIT(24) -#define BIT_BCNDMAINT0 BIT(20) -#define BIT_BCNDERR0 BIT(16) -#define BIT_HSISR_IND_ON_INT BIT(15) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_RDU_MSK BIT(1) +#define BIT_RDU BIT(1) +#define BIT_RXOK_MSK BIT(0) +#define BIT_RXOK BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ -#define BIT_BCNDMAINT_E BIT(14) +#define BIT_PSTIMEOUT2 BIT(31) +#define BIT_PSTIMEOUT1 BIT(30) +#define BIT_PSTIMEOUT BIT(29) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ -#define BIT_HISR3_IND_INT BIT(14) -#define BIT_HISR2_IND_INT BIT(13) +#define BIT_HISR5_IND_INT BIT(18) +#define BIT_HISR4_IND_INT BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ -#define BIT_CTWEND BIT(12) +#define BIT_BCNDMAINT_E BIT(14) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ -#define BIT_HISR1_IND_INT BIT(11) -#define BIT_C2HCMD BIT(10) -#define BIT_CPWM2 BIT(9) -#define BIT_CPWM BIT(8) -#define BIT_HIGHDOK BIT(7) -#define BIT_MGTDOK BIT(6) -#define BIT_BKDOK BIT(5) -#define BIT_BEDOK BIT(4) -#define BIT_VIDOK BIT(3) -#define BIT_VODOK BIT(2) -#define BIT_RDU BIT(1) -#define BIT_RXOK BIT(0) +#define BIT_HISR3_IND_INT BIT(14) +#define BIT_HISR2_IND_INT BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HISR0 (Offset 0x00B4) */ +#define BIT_CTWEND BIT(12) -/* 2 REG_HIMR1 (Offset 0x00B8) */ +#endif -#define BIT_BTON_STS_UPDATE_MSK BIT(29) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HISR0 (Offset 0x00B4) */ +#define BIT_HISR1_IND_INT BIT(11) +#define BIT_HIGHDOK BIT(7) +#define BIT_MGTDOK BIT(6) +#define BIT_BKDOK BIT(5) +#define BIT_BEDOK BIT(4) +#define BIT_VIDOK BIT(3) +#define BIT_VODOK BIT(2) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BTON_STS_UPDATE_MASK BIT(29) +#define BIT_PRETXERR_HANDLE_MSK BIT(31) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_MCU_ERR_MASK BIT(28) +#define BIT_PRE_TX_ERR_INT_MSK BIT(31) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT7_MSK BIT(27) +#define BIT_BTON_STS_UPDATE_INT BIT(29) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT7__MSK BIT(27) +#define BIT_BTON_STS_UPDATE_MSK BIT(29) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT6_MSK BIT(26) +#define BIT_BTON_STS_UPDATE_MASK BIT(29) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT6__MSK BIT(26) +#define BIT_MCU_ERR_MASK BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT5_MSK BIT(25) +#define BIT_BCNDMAINT7 BIT(27) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT5__MSK BIT(25) +#define BIT_BCNDMAINT7_MSK BIT(27) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT4_MSK BIT(24) +#define BIT_BCNDMAINT7__MSK BIT(27) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT4__MSK BIT(24) +#define BIT_BCNDMAINT6 BIT(26) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT3_MSK BIT(23) -#define BIT_BCNDMAINT2_MSK BIT(22) -#define BIT_BCNDMAINT1_MSK BIT(21) -#define BIT_BCNDERR7_MSK BIT(20) -#define BIT_BCNDERR6_MSK BIT(19) -#define BIT_BCNDERR5_MSK BIT(18) -#define BIT_BCNDERR4_MSK BIT(17) -#define BIT_BCNDERR3_MSK BIT(16) -#define BIT_BCNDERR2_MSK BIT(15) -#define BIT_BCNDERR1_MSK BIT(14) +#define BIT_BCNDMAINT6_MSK BIT(26) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_ATIMEND_E_MSK BIT(13) +#define BIT_BCNDMAINT6__MSK BIT(26) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_ATIMEND_MSK BIT(12) +#define BIT_BCNDMAINT5 BIT(25) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_ATIMEND__MSK BIT(12) +#define BIT_BCNDMAINT5_MSK BIT(25) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_BCNDMAINT5__MSK BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_TXERR_MSK BIT(11) -#define BIT_RXERR_MSK BIT(10) -#define BIT_TXFOVW_MSK BIT(9) -#define BIT_FOVW_MSK BIT(8) +#define BIT_BCNDMAINT4 BIT(24) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_BCNDMAINT4_MSK BIT(24) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_LD_B12V_EN_V1 BIT(7) +#define BIT_BCNDMAINT4__MSK BIT(24) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_BCNDMAINT3_MSK BIT(23) +#define BIT_BCNDMAINT3 BIT(23) +#define BIT_BCNDMAINT2_MSK BIT(22) +#define BIT_BCNDMAINT2 BIT(22) +#define BIT_BCNDMAINT1_MSK BIT(21) +#define BIT_BCNDMAINT1 BIT(21) +#define BIT_BCNDERR7_MSK BIT(20) +#define BIT_BCNDERR7 BIT(20) +#define BIT_BCNDERR6_MSK BIT(19) +#define BIT_BCNDERR6 BIT(19) +#define BIT_BCNDERR5_MSK BIT(18) +#define BIT_BCNDERR5 BIT(18) +#define BIT_BCNDERR4_MSK BIT(17) +#define BIT_BCNDERR4 BIT(17) +#define BIT_BCNDERR3_MSK BIT(16) +#define BIT_BCNDERR3 BIT(16) +#define BIT_BCNDERR2_MSK BIT(15) +#define BIT_BCNDERR2 BIT(15) +#define BIT_BCNDERR1_MSK BIT(14) +#define BIT_BCNDERR1 BIT(14) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_CPU_MGQ_TXDONE_MSK BIT(5) -#define BIT_PS_TIMER_C_MSK BIT(4) -#define BIT_PS_TIMER_B_MSK BIT(3) -#define BIT_PS_TIMER_A_MSK BIT(2) -#define BIT_CPUMGQ_TX_TIMER_MSK BIT(1) +#define BIT_ATIMEND_E_MSK BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_ATIMEND_MSK BIT(12) -/* 2 REG_HISR1 (Offset 0x00BC) */ +#endif -#define BIT_BTON_STS_UPDATE_INT BIT(29) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_ATIMEND__MSK BIT(12) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8822B_SUPPORT) -/* 2 REG_HISR1 (Offset 0x00BC) */ +/* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_MCU_ERR BIT(28) +#define BIT_ATIMEND_E_V1_MSK BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_TXERR_MSK BIT(11) +#define BIT_TXERR_INT BIT(11) +#define BIT_RXERR_MSK BIT(10) +#define BIT_RXERR_INT BIT(10) +#define BIT_TXFOVW_MSK BIT(9) +#define BIT_TXFOVW BIT(9) +#define BIT_FOVW_MSK BIT(8) +#define BIT_FOVW BIT(8) -/* 2 REG_HISR1 (Offset 0x00BC) */ +#endif -#define BIT_BCNDMAINT7 BIT(27) -#define BIT_BCNDMAINT6 BIT(26) -#define BIT_BCNDMAINT5 BIT(25) -#define BIT_BCNDMAINT4 BIT(24) -#define BIT_BCNDMAINT3 BIT(23) -#define BIT_BCNDMAINT2 BIT(22) -#define BIT_BCNDMAINT1 BIT(21) -#define BIT_BCNDERR7 BIT(20) -#define BIT_BCNDERR6 BIT(19) -#define BIT_BCNDERR5 BIT(18) -#define BIT_BCNDERR4 BIT(17) -#define BIT_BCNDERR3 BIT(16) -#define BIT_BCNDERR2 BIT(15) -#define BIT_BCNDERR1 BIT(14) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_LD_B12V_EN_V1 BIT(7) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_HISR1 (Offset 0x00BC) */ +/* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_ATIMEND_E BIT(13) +#define BIT_CPU_MGQ_EARLY_INT_MSK BIT(6) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_CPU_MGQ_TXDONE_MSK BIT(5) +#define BIT_CPU_MGQ_TXDONE BIT(5) -/* 2 REG_HISR1 (Offset 0x00BC) */ +#endif -#define BIT_ATIMEND BIT(12) -#define BIT_TXERR_INT BIT(11) -#define BIT_RXERR_INT BIT(10) -#define BIT_TXFOVW BIT(9) -#define BIT_FOVW BIT(8) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_PSTIMER_5_MSK BIT(4) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_HISR1 (Offset 0x00BC) */ +/* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_CPU_MGQ_TXDONE BIT(5) -#define BIT_PS_TIMER_C BIT(4) -#define BIT_PS_TIMER_B BIT(3) -#define BIT_PS_TIMER_A BIT(2) -#define BIT_CPUMGQ_TX_TIMER BIT(1) +#define BIT_PS_TIMER_C_MSK BIT(4) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_PSTIMER_4_MSK BIT(3) -/* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_HR_FF_OVF BIT(6) -#define BIT_HR_FF_UDN BIT(5) -#define BIT_TXDMA_BUSY_ERR BIT(4) -#define BIT_TXDMA_VLD_ERR BIT(3) -#define BIT_QSEL_UNKNOWN_ERR BIT(2) -#define BIT_QSEL_MIS_ERR BIT(1) +#define BIT_PS_TIMER_B_MSK BIT(3) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_PSTIMER_3_MSK BIT(2) -/* 2 REG_DBG_PORT_SEL (Offset 0x00C0) */ +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DEBUG_ST 0 -#define BIT_MASK_DEBUG_ST 0xffffffffL -#define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST) -#define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST) +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_PS_TIMER_A_MSK BIT(2) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_CPUMGQ_TX_TIMER_MSK BIT(1) +#define BIT_CPUMGQ_TX_TIMER BIT(1) -/* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ +#endif -#define BIT_SDIO_OVERRD_ERR BIT(0) +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_SDIO_CMD_ERRCNT (Offset 0x102500C1) */ +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_BB_STOPRX_INT_MSK BIT(0) -#define BIT_SHIFT_CMD_CRC_ERR_CNT 0 -#define BIT_MASK_CMD_CRC_ERR_CNT 0xff -#define BIT_CMD_CRC_ERR_CNT(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT) -#define BIT_GET_CMD_CRC_ERR_CNT(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_SDIO_DATA_ERRCNT (Offset 0x102500C2) */ +/* 2 REG_HISR1 (Offset 0x00BC) */ +#define BIT_PRETXERR_HANDLE_INT BIT(31) -#define BIT_SHIFT_DATA_CRC_ERR_CNT 0 -#define BIT_MASK_DATA_CRC_ERR_CNT 0xff -#define BIT_DATA_CRC_ERR_CNT(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT) -#define BIT_GET_DATA_CRC_ERR_CNT(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HISR1 (Offset 0x00BC) */ +#define BIT_MCU_ERR BIT(28) +#define BIT_ATIMEND_E BIT(13) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8822B_SUPPORT) -/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ +/* 2 REG_HISR1 (Offset 0x00BC) */ -#define BIT_MAC_SOP BIT(25) -#define BIT_LDO11_ST_EXT BIT(24) -#define BIT_ANTSELB_S2 BIT(23) -#define BIT_ANTSELB_S1 BIT(22) -#define BIT_ANTSEL_S3 BIT(21) -#define BIT_ANTSEL_S2 BIT(20) +#define BIT_ATIMEND_E_V1_INT BIT(12) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HISR1 (Offset 0x00BC) */ +#define BIT_PS_TIMER_C BIT(4) +#define BIT_PS_TIMER_B BIT(3) +#define BIT_PS_TIMER_A BIT(2) -/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ +#endif -#define BIT_USB3_USB2_TRANSITION BIT(20) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ +#define BIT_HR_FF_OVF BIT(6) +#define BIT_HR_FF_UDN BIT(5) +#define BIT_TXDMA_BUSY_ERR BIT(4) +#define BIT_TXDMA_VLD_ERR BIT(3) +#define BIT_QSEL_UNKNOWN_ERR BIT(2) +#define BIT_QSEL_MIS_ERR BIT(1) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ +/* 2 REG_DBG_PORT_SEL (Offset 0x00C0) */ -#define BIT_ANTSEL_S1 BIT(19) -#define BIT_FCSN_PU BIT(18) +#define BIT_SHIFT_DEBUG_ST 0 +#define BIT_MASK_DEBUG_ST 0xffffffffL +#define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST) +#define BITS_DEBUG_ST (BIT_MASK_DEBUG_ST << BIT_SHIFT_DEBUG_ST) +#define BIT_CLEAR_DEBUG_ST(x) ((x) & (~BITS_DEBUG_ST)) +#define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST) +#define BIT_SET_DEBUG_ST(x, v) (BIT_CLEAR_DEBUG_ST(x) | BIT_DEBUG_ST(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ +#define BIT_SDIO_OVERRD_ERR BIT(0) -/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ +#define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0 +#define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7 +#define BIT_SDIO_DATA_REPLY_TIME(x) \ + (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME) \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME) +#define BITS_SDIO_DATA_REPLY_TIME \ + (BIT_MASK_SDIO_DATA_REPLY_TIME << BIT_SHIFT_SDIO_DATA_REPLY_TIME) +#define BIT_CLEAR_SDIO_DATA_REPLY_TIME(x) ((x) & (~BITS_SDIO_DATA_REPLY_TIME)) +#define BIT_GET_SDIO_DATA_REPLY_TIME(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) & \ + BIT_MASK_SDIO_DATA_REPLY_TIME) +#define BIT_SET_SDIO_DATA_REPLY_TIME(x, v) \ + (BIT_CLEAR_SDIO_DATA_REPLY_TIME(x) | BIT_SDIO_DATA_REPLY_TIME(v)) + +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_USB23_SW_MODE_V1 18 -#define BIT_MASK_USB23_SW_MODE_V1 0x3 -#define BIT_USB23_SW_MODE_V1(x) (((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1) -#define BIT_GET_USB23_SW_MODE_V1(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1) +/* 2 REG_SDIO_DIOERR_RPT (Offset 0x102500C0) */ +#define BIT_SDIO_PAGE_ERR BIT(0) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDIO_CMD_ERRCNT (Offset 0x102500C2) */ +#define BIT_SHIFT_CMD_CRC_ERR_CNT 0 +#define BIT_MASK_CMD_CRC_ERR_CNT 0xff +#define BIT_CMD_CRC_ERR_CNT(x) \ + (((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT) +#define BITS_CMD_CRC_ERR_CNT \ + (BIT_MASK_CMD_CRC_ERR_CNT << BIT_SHIFT_CMD_CRC_ERR_CNT) +#define BIT_CLEAR_CMD_CRC_ERR_CNT(x) ((x) & (~BITS_CMD_CRC_ERR_CNT)) +#define BIT_GET_CMD_CRC_ERR_CNT(x) \ + (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT) +#define BIT_SET_CMD_CRC_ERR_CNT(x, v) \ + (BIT_CLEAR_CMD_CRC_ERR_CNT(x) | BIT_CMD_CRC_ERR_CNT(v)) -/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ +/* 2 REG_SDIO_DATA_ERRCNT (Offset 0x102500C3) */ -#define BIT_KEEP_PAD BIT(17) +#define BIT_SHIFT_DATA_CRC_ERR_CNT 0 +#define BIT_MASK_DATA_CRC_ERR_CNT 0xff +#define BIT_DATA_CRC_ERR_CNT(x) \ + (((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT) +#define BITS_DATA_CRC_ERR_CNT \ + (BIT_MASK_DATA_CRC_ERR_CNT << BIT_SHIFT_DATA_CRC_ERR_CNT) +#define BIT_CLEAR_DATA_CRC_ERR_CNT(x) ((x) & (~BITS_DATA_CRC_ERR_CNT)) +#define BIT_GET_DATA_CRC_ERR_CNT(x) \ + (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT) +#define BIT_SET_DATA_CRC_ERR_CNT(x, v) \ + (BIT_CLEAR_DATA_CRC_ERR_CNT(x) | BIT_DATA_CRC_ERR_CNT(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ + +#define BIT_MAC_SOP BIT(25) +#define BIT_LDO11_ST_EXT BIT(24) +#define BIT_ANTSELB_S2 BIT(23) +#define BIT_ANTSELB_S1 BIT(22) +#define BIT_ANTSEL_S3 BIT(21) +#define BIT_ANTSEL_S2 BIT(20) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_NO_PDN_CHIPOFF_V1 BIT(17) +#define BIT_USB3_USB2_TRANSITION BIT(20) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_PAD_ALD_SKP BIT(16) +#define BIT_ANTSEL_S1 BIT(19) +#define BIT_FCSN_PU BIT(18) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_RSM_EN_V1 BIT(16) +#define BIT_SHIFT_USB23_SW_MODE_V1 18 +#define BIT_MASK_USB23_SW_MODE_V1 0x3 +#define BIT_USB23_SW_MODE_V1(x) \ + (((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1) +#define BITS_USB23_SW_MODE_V1 \ + (BIT_MASK_USB23_SW_MODE_V1 << BIT_SHIFT_USB23_SW_MODE_V1) +#define BIT_CLEAR_USB23_SW_MODE_V1(x) ((x) & (~BITS_USB23_SW_MODE_V1)) +#define BIT_GET_USB23_SW_MODE_V1(x) \ + (((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1) +#define BIT_SET_USB23_SW_MODE_V1(x, v) \ + (BIT_CLEAR_USB23_SW_MODE_V1(x) | BIT_USB23_SW_MODE_V1(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_PAD_A_ANTSEL_E BIT(11) -#define BIT_PAD_A_ANTSELB_E BIT(10) -#define BIT_PAD_A_ANTSEL_O BIT(9) -#define BIT_PAD_A_ANTSELB_O BIT(8) +#define BIT_KEEP_PAD BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_LD_B12V_EN BIT(7) +#define BIT_NO_PDN_CHIPOFF_V1 BIT(17) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_B15V_EN BIT(7) +#define BIT_PAD_ALD_SKP BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EESK_IOSEL BIT(6) +#define BIT_RSM_EN_V1 BIT(16) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EECS_IOSEL_V1 BIT(6) +#define BIT_PAD_A_ANTSEL_E BIT(11) +#define BIT_PAD_A_ANTSELB_E BIT(10) +#define BIT_PAD_A_ANTSEL_O BIT(9) +#define BIT_PAD_A_ANTSELB_O BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EESK_DATA_O BIT(5) +#define BIT_LD_B12V_EN BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EECS_DATA_O_V1 BIT(5) +#define BIT_B15V_EN BIT(7) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EESK_DATA_I BIT(4) +#define BIT_EESK_IOSEL BIT(6) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EECS_DATA_I_V1 BIT(4) +#define BIT_EECS_IOSEL_V1 BIT(6) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EECS_IOSEL BIT(2) +#define BIT_EESK_DATA_O BIT(5) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EESK_IOSEL_V1 BIT(2) +#define BIT_EECS_DATA_O_V1 BIT(5) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EECS_DATA_O BIT(1) +#define BIT_EESK_DATA_I BIT(4) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EESK_DATA_O_V1 BIT(1) +#define BIT_EECS_DATA_I_V1 BIT(4) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EECS_DATA_I BIT(0) +#define BIT_EECS_IOSEL BIT(2) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EESK_DATA_I_V1 BIT(0) +#define BIT_EESK_IOSEL_V1 BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ +#define BIT_EECS_DATA_O BIT(1) -/* 2 REG_SDIO_CMD_ERR_CONTENT (Offset 0x102500C4) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0 -#define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL -#define BIT_SDIO_CMD_ERR_CONTENT(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT) -#define BIT_GET_SDIO_CMD_ERR_CONTENT(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) & BIT_MASK_SDIO_CMD_ERR_CONTENT) +/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ +#define BIT_EESK_DATA_O_V1 BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_MEM_RMC (Offset 0x00C8) */ +/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_MEM_RMV_SIGN BIT(31) -#define BIT_MEM_RMV_2PRF1 BIT(29) -#define BIT_MEM_RMV_2PRF0 BIT(28) -#define BIT_MEM_RMV_1PRF1 BIT(27) -#define BIT_MEM_RMV_1PRF0 BIT(26) -#define BIT_MEM_RMV_1PSR BIT(25) -#define BIT_MEM_RMV_ROM BIT(24) +#define BIT_EECS_DATA_I BIT(0) -#define BIT_SHIFT_MEM_RME_WL_V2 4 -#define BIT_MASK_MEM_RME_WL_V2 0x3f -#define BIT_MEM_RME_WL_V2(x) (((x) & BIT_MASK_MEM_RME_WL_V2) << BIT_SHIFT_MEM_RME_WL_V2) -#define BIT_GET_MEM_RME_WL_V2(x) (((x) >> BIT_SHIFT_MEM_RME_WL_V2) & BIT_MASK_MEM_RME_WL_V2) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MEM_RME_HCI_V2 0 -#define BIT_MASK_MEM_RME_HCI_V2 0x1f -#define BIT_MEM_RME_HCI_V2(x) (((x) & BIT_MASK_MEM_RME_HCI_V2) << BIT_SHIFT_MEM_RME_HCI_V2) -#define BIT_GET_MEM_RME_HCI_V2(x) (((x) >> BIT_SHIFT_MEM_RME_HCI_V2) & BIT_MASK_MEM_RME_HCI_V2) +/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ +#define BIT_EESK_DATA_I_V1 BIT(0) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_CMD_ERR_CONTENT (Offset 0x102500C4) */ +#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0 +#define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL +#define BIT_SDIO_CMD_ERR_CONTENT(x) \ + (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT) \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT) +#define BITS_SDIO_CMD_ERR_CONTENT \ + (BIT_MASK_SDIO_CMD_ERR_CONTENT << BIT_SHIFT_SDIO_CMD_ERR_CONTENT) +#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) ((x) & (~BITS_SDIO_CMD_ERR_CONTENT)) +#define BIT_GET_SDIO_CMD_ERR_CONTENT(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) & \ + BIT_MASK_SDIO_CMD_ERR_CONTENT) +#define BIT_SET_SDIO_CMD_ERR_CONTENT(x, v) \ + (BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) | BIT_SDIO_CMD_ERR_CONTENT(v)) -/* 2 REG_SDIO_CRC_ERR_IDX (Offset 0x102500C9) */ +#endif -#define BIT_D3_CRC_ERR BIT(4) -#define BIT_D2_CRC_ERR BIT(3) -#define BIT_D1_CRC_ERR BIT(2) -#define BIT_D0_CRC_ERR BIT(1) -#define BIT_CMD_CRC_ERR BIT(0) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_SDIO_DATA_CRC (Offset 0x102500CA) */ +/* 2 REG_MEM_RMC (Offset 0x00C8) */ +#define BIT_MEM_RMV_SIGN BIT(31) +#define BIT_MEM_RMV_2PRF1 BIT(29) +#define BIT_MEM_RMV_2PRF0 BIT(28) +#define BIT_MEM_RMV_1PRF1 BIT(27) +#define BIT_MEM_RMV_1PRF0 BIT(26) +#define BIT_MEM_RMV_1PSR BIT(25) +#define BIT_MEM_RMV_ROM BIT(24) + +#define BIT_SHIFT_MEM_RME_WL_V2 4 +#define BIT_MASK_MEM_RME_WL_V2 0x3f +#define BIT_MEM_RME_WL_V2(x) \ + (((x) & BIT_MASK_MEM_RME_WL_V2) << BIT_SHIFT_MEM_RME_WL_V2) +#define BITS_MEM_RME_WL_V2 (BIT_MASK_MEM_RME_WL_V2 << BIT_SHIFT_MEM_RME_WL_V2) +#define BIT_CLEAR_MEM_RME_WL_V2(x) ((x) & (~BITS_MEM_RME_WL_V2)) +#define BIT_GET_MEM_RME_WL_V2(x) \ + (((x) >> BIT_SHIFT_MEM_RME_WL_V2) & BIT_MASK_MEM_RME_WL_V2) +#define BIT_SET_MEM_RME_WL_V2(x, v) \ + (BIT_CLEAR_MEM_RME_WL_V2(x) | BIT_MEM_RME_WL_V2(v)) + +#define BIT_SHIFT_MEM_RME_HCI_V2 0 +#define BIT_MASK_MEM_RME_HCI_V2 0x1f +#define BIT_MEM_RME_HCI_V2(x) \ + (((x) & BIT_MASK_MEM_RME_HCI_V2) << BIT_SHIFT_MEM_RME_HCI_V2) +#define BITS_MEM_RME_HCI_V2 \ + (BIT_MASK_MEM_RME_HCI_V2 << BIT_SHIFT_MEM_RME_HCI_V2) +#define BIT_CLEAR_MEM_RME_HCI_V2(x) ((x) & (~BITS_MEM_RME_HCI_V2)) +#define BIT_GET_MEM_RME_HCI_V2(x) \ + (((x) >> BIT_SHIFT_MEM_RME_HCI_V2) & BIT_MASK_MEM_RME_HCI_V2) +#define BIT_SET_MEM_RME_HCI_V2(x, v) \ + (BIT_CLEAR_MEM_RME_HCI_V2(x) | BIT_MEM_RME_HCI_V2(v)) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SDIO_DATA_CRC 0 -#define BIT_MASK_SDIO_DATA_CRC 0xff -#define BIT_SDIO_DATA_CRC(x) (((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC) -#define BIT_GET_SDIO_DATA_CRC(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC) +/* 2 REG_SDIO_CRC_ERR_IDX (Offset 0x102500C9) */ +#define BIT_D3_CRC_ERR BIT(4) +#define BIT_D2_CRC_ERR BIT(3) +#define BIT_D1_CRC_ERR BIT(2) +#define BIT_D0_CRC_ERR BIT(1) +#define BIT_CMD_CRC_ERR BIT(0) -/* 2 REG_SDIO_DATA_REPLY_TIME (Offset 0x102500CB) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0 -#define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7 -#define BIT_SDIO_DATA_REPLY_TIME(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME) << BIT_SHIFT_SDIO_DATA_REPLY_TIME) -#define BIT_GET_SDIO_DATA_REPLY_TIME(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) & BIT_MASK_SDIO_DATA_REPLY_TIME) +/* 2 REG_SDIO_DATA_CRC (Offset 0x102500CA) */ +#define BIT_SHIFT_SDIO_DATA_CRC 0 +#define BIT_MASK_SDIO_DATA_CRC 0xffff +#define BIT_SDIO_DATA_CRC(x) \ + (((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC) +#define BITS_SDIO_DATA_CRC (BIT_MASK_SDIO_DATA_CRC << BIT_SHIFT_SDIO_DATA_CRC) +#define BIT_CLEAR_SDIO_DATA_CRC(x) ((x) & (~BITS_SDIO_DATA_CRC)) +#define BIT_GET_SDIO_DATA_CRC(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC) +#define BIT_SET_SDIO_DATA_CRC(x, v) \ + (BIT_CLEAR_SDIO_DATA_CRC(x) | BIT_SDIO_DATA_CRC(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ - -#define BIT_SHIFT_EFUSE_BURN_GNT 24 -#define BIT_MASK_EFUSE_BURN_GNT 0xff -#define BIT_EFUSE_BURN_GNT(x) (((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT) -#define BIT_GET_EFUSE_BURN_GNT(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT) - +#define BIT_SHIFT_EFUSE_BURN_GNT 24 +#define BIT_MASK_EFUSE_BURN_GNT 0xff +#define BIT_EFUSE_BURN_GNT(x) \ + (((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT) +#define BITS_EFUSE_BURN_GNT \ + (BIT_MASK_EFUSE_BURN_GNT << BIT_SHIFT_EFUSE_BURN_GNT) +#define BIT_CLEAR_EFUSE_BURN_GNT(x) ((x) & (~BITS_EFUSE_BURN_GNT)) +#define BIT_GET_EFUSE_BURN_GNT(x) \ + (((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT) +#define BIT_SET_EFUSE_BURN_GNT(x, v) \ + (BIT_CLEAR_EFUSE_BURN_GNT(x) | BIT_EFUSE_BURN_GNT(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#define BIT_SHIFT_EFUSE_PG_PWD 24 +#define BIT_MASK_EFUSE_PG_PWD 0xff +#define BIT_EFUSE_PG_PWD(x) \ + (((x) & BIT_MASK_EFUSE_PG_PWD) << BIT_SHIFT_EFUSE_PG_PWD) +#define BITS_EFUSE_PG_PWD (BIT_MASK_EFUSE_PG_PWD << BIT_SHIFT_EFUSE_PG_PWD) +#define BIT_CLEAR_EFUSE_PG_PWD(x) ((x) & (~BITS_EFUSE_PG_PWD)) +#define BIT_GET_EFUSE_PG_PWD(x) \ + (((x) >> BIT_SHIFT_EFUSE_PG_PWD) & BIT_MASK_EFUSE_PG_PWD) +#define BIT_SET_EFUSE_PG_PWD(x, v) \ + (BIT_CLEAR_EFUSE_PG_PWD(x) | BIT_EFUSE_PG_PWD(v)) -#define BIT_SHIFT_EFUSE_PG_PWD 24 -#define BIT_MASK_EFUSE_PG_PWD 0xff -#define BIT_EFUSE_PG_PWD(x) (((x) & BIT_MASK_EFUSE_PG_PWD) << BIT_SHIFT_EFUSE_PG_PWD) -#define BIT_GET_EFUSE_PG_PWD(x) (((x) >> BIT_SHIFT_EFUSE_PG_PWD) & BIT_MASK_EFUSE_PG_PWD) - -#define BIT_DBG_READ_EN BIT(16) +#define BIT_DBG_READ_EN BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ -#define BIT_STOP_WL_PMC BIT(9) -#define BIT_STOP_SYM_PMC BIT(8) +#define BIT_STOP_WL_PMC BIT(9) +#define BIT_STOP_SYM_PMC BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#define BIT_SHIFT_EDATA1_V1 8 +#define BIT_MASK_EDATA1_V1 0xff +#define BIT_EDATA1_V1(x) (((x) & BIT_MASK_EDATA1_V1) << BIT_SHIFT_EDATA1_V1) +#define BITS_EDATA1_V1 (BIT_MASK_EDATA1_V1 << BIT_SHIFT_EDATA1_V1) +#define BIT_CLEAR_EDATA1_V1(x) ((x) & (~BITS_EDATA1_V1)) +#define BIT_GET_EDATA1_V1(x) (((x) >> BIT_SHIFT_EDATA1_V1) & BIT_MASK_EDATA1_V1) +#define BIT_SET_EDATA1_V1(x, v) (BIT_CLEAR_EDATA1_V1(x) | BIT_EDATA1_V1(v)) -#define BIT_SHIFT_EDATA1_V1 8 -#define BIT_MASK_EDATA1_V1 0xff -#define BIT_EDATA1_V1(x) (((x) & BIT_MASK_EDATA1_V1) << BIT_SHIFT_EDATA1_V1) -#define BIT_GET_EDATA1_V1(x) (((x) >> BIT_SHIFT_EDATA1_V1) & BIT_MASK_EDATA1_V1) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#define BIT_BT_ACCESS_WL_PAGE0 BIT(6) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ -#define BIT_BT_ACCESS_WL_PAGE0 BIT(6) +#define BIT_REG_RST_WLPMC BIT(5) +#define BIT_REG_RST_PD12N BIT(4) +#define BIT_SYSON_DIS_WLREG_WRMSK BIT(3) +#define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TRANS_FIFO_STATUS (Offset 0x102500CC) */ +#define BIT_TRANS_FIFO_UNDERFLOW BIT(1) -/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#endif -#define BIT_REG_RST_WLPMC BIT(5) -#define BIT_REG_RST_PD12N BIT(4) -#define BIT_SYSON_DIS_WLREG_WRMSK BIT(3) -#define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SYSON_REG_ARB 0 -#define BIT_MASK_SYSON_REG_ARB 0x3 -#define BIT_SYSON_REG_ARB(x) (((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB) -#define BIT_GET_SYSON_REG_ARB(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB) +/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#define BIT_SHIFT_SYSON_REG_ARB 0 +#define BIT_MASK_SYSON_REG_ARB 0x3 +#define BIT_SYSON_REG_ARB(x) \ + (((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB) +#define BITS_SYSON_REG_ARB (BIT_MASK_SYSON_REG_ARB << BIT_SHIFT_SYSON_REG_ARB) +#define BIT_CLEAR_SYSON_REG_ARB(x) ((x) & (~BITS_SYSON_REG_ARB)) +#define BIT_GET_SYSON_REG_ARB(x) \ + (((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB) +#define BIT_SET_SYSON_REG_ARB(x, v) \ + (BIT_CLEAR_SYSON_REG_ARB(x) | BIT_SYSON_REG_ARB(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#define BIT_SHIFT_EDATA0_V1 0 +#define BIT_MASK_EDATA0_V1 0xff +#define BIT_EDATA0_V1(x) (((x) & BIT_MASK_EDATA0_V1) << BIT_SHIFT_EDATA0_V1) +#define BITS_EDATA0_V1 (BIT_MASK_EDATA0_V1 << BIT_SHIFT_EDATA0_V1) +#define BIT_CLEAR_EDATA0_V1(x) ((x) & (~BITS_EDATA0_V1)) +#define BIT_GET_EDATA0_V1(x) (((x) >> BIT_SHIFT_EDATA0_V1) & BIT_MASK_EDATA0_V1) +#define BIT_SET_EDATA0_V1(x, v) (BIT_CLEAR_EDATA0_V1(x) | BIT_EDATA0_V1(v)) -#define BIT_SHIFT_EDATA0_V1 0 -#define BIT_MASK_EDATA0_V1 0xff -#define BIT_EDATA0_V1(x) (((x) & BIT_MASK_EDATA0_V1) << BIT_SHIFT_EDATA0_V1) -#define BIT_GET_EDATA0_V1(x) (((x) >> BIT_SHIFT_EDATA0_V1) & BIT_MASK_EDATA0_V1) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_BIST_CTRL (Offset 0x00D0) */ +/* 2 REG_SDIO_TRANS_FIFO_STATUS (Offset 0x102500CC) */ -#define BIT_SCAN_PLL_BYPASS BIT(30) -#define BIT_DRF_BIST_FAIL_V1 BIT(28) +#define BIT_TRANS_FIFO_OVERFLOW BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_USB_DIS BIT(27) +#define BIT_LD_RQPN BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_DRF_BIST_READY_V1 BIT(27) +#define BIT_SCAN_PLL_BYPASS BIT(30) +#define BIT_DRF_BIST_FAIL_V1 BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_PCI_DIS BIT(26) +#define BIT_BIST_USB_DIS BIT(27) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_FAIL_V1 BIT(26) +#define BIT_DRF_BIST_READY_V1 BIT(27) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_BT_DIS BIT(25) +#define BIT_BIST_PCI_DIS BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_READY_V1 BIT(25) +#define BIT_BIST_FAIL_V1 BIT(26) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_WL_DIS BIT(24) +#define BIT_BIST_BT_DIS BIT(25) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_START_PAUSE_V1 BIT(24) +#define BIT_BIST_READY_V1 BIT(25) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ - -#define BIT_SHIFT_BIST_RPT_SEL 16 -#define BIT_MASK_BIST_RPT_SEL 0xf -#define BIT_BIST_RPT_SEL(x) (((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL) -#define BIT_GET_BIST_RPT_SEL(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL) - +#define BIT_BIST_WL_DIS BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_BIST_CTRL (Offset 0x00D0) */ - -#define BIT_SHIFT_MBIST_RSTNI 8 -#define BIT_MASK_MBIST_RSTNI 0x3ff -#define BIT_MBIST_RSTNI(x) (((x) & BIT_MASK_MBIST_RSTNI) << BIT_SHIFT_MBIST_RSTNI) -#define BIT_GET_MBIST_RSTNI(x) (((x) >> BIT_SHIFT_MBIST_RSTNI) & BIT_MASK_MBIST_RSTNI) - -#define BIT_BIST_RESUME_PS_V1 BIT(5) +#define BIT_BIST_START_PAUSE_V1 BIT(24) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_RESUME_PS BIT(4) +#define BIT_SHIFT_BIST_RPT_SEL 16 +#define BIT_MASK_BIST_RPT_SEL 0xf +#define BIT_BIST_RPT_SEL(x) \ + (((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL) +#define BITS_BIST_RPT_SEL (BIT_MASK_BIST_RPT_SEL << BIT_SHIFT_BIST_RPT_SEL) +#define BIT_CLEAR_BIST_RPT_SEL(x) ((x) & (~BITS_BIST_RPT_SEL)) +#define BIT_GET_BIST_RPT_SEL(x) \ + (((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL) +#define BIT_SET_BIST_RPT_SEL(x, v) \ + (BIT_CLEAR_BIST_RPT_SEL(x) | BIT_BIST_RPT_SEL(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_RESUME_V1 BIT(4) - -#endif +#define BIT_SHIFT_MBIST_RSTNI 8 +#define BIT_MASK_MBIST_RSTNI 0x3ff +#define BIT_MBIST_RSTNI(x) \ + (((x) & BIT_MASK_MBIST_RSTNI) << BIT_SHIFT_MBIST_RSTNI) +#define BITS_MBIST_RSTNI (BIT_MASK_MBIST_RSTNI << BIT_SHIFT_MBIST_RSTNI) +#define BIT_CLEAR_MBIST_RSTNI(x) ((x) & (~BITS_MBIST_RSTNI)) +#define BIT_GET_MBIST_RSTNI(x) \ + (((x) >> BIT_SHIFT_MBIST_RSTNI) & BIT_MASK_MBIST_RSTNI) +#define BIT_SET_MBIST_RSTNI(x, v) \ + (BIT_CLEAR_MBIST_RSTNI(x) | BIT_MBIST_RSTNI(v)) +#define BIT_BIST_RESUME_PS_V1 BIT(5) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_RESUME BIT(3) -#define BIT_BIST_NORMAL BIT(2) +#define BIT_BIST_RESUME_PS BIT(4) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_BIST_CTRL (Offset 0x00D0) */ +#define BIT_BIST_RESUME_V1 BIT(4) -#define BIT_SHIFT_BIST_MODE 2 -#define BIT_MASK_BIST_MODE 0x3 -#define BIT_BIST_MODE(x) (((x) & BIT_MASK_BIST_MODE) << BIT_SHIFT_BIST_MODE) -#define BIT_GET_BIST_MODE(x) (((x) >> BIT_SHIFT_BIST_MODE) & BIT_MASK_BIST_MODE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_BIST_CTRL (Offset 0x00D0) */ +#define BIT_BIST_RESUME BIT(3) +#define BIT_BIST_NORMAL BIT(2) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_RSTN BIT(1) -#define BIT_BIST_CLK_EN BIT(0) +#define BIT_SHIFT_BIST_MODE 2 +#define BIT_MASK_BIST_MODE 0x3 +#define BIT_BIST_MODE(x) (((x) & BIT_MASK_BIST_MODE) << BIT_SHIFT_BIST_MODE) +#define BITS_BIST_MODE (BIT_MASK_BIST_MODE << BIT_SHIFT_BIST_MODE) +#define BIT_CLEAR_BIST_MODE(x) ((x) & (~BITS_BIST_MODE)) +#define BIT_GET_BIST_MODE(x) (((x) >> BIT_SHIFT_BIST_MODE) & BIT_MASK_BIST_MODE) +#define BIT_SET_BIST_MODE(x, v) (BIT_CLEAR_BIST_MODE(x) | BIT_BIST_MODE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BIST_CTRL (Offset 0x00D0) */ +#define BIT_BIST_RSTN BIT(1) +#define BIT_BIST_CLK_EN BIT(0) -/* 2 REG_BIST_RPT (Offset 0x00D4) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MBIST_REPORT 0 -#define BIT_MASK_MBIST_REPORT 0xffffffffL -#define BIT_MBIST_REPORT(x) (((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT) -#define BIT_GET_MBIST_REPORT(x) (((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT) +/* 2 REG_BIST_RPT (Offset 0x00D4) */ +#define BIT_SHIFT_MBIST_REPORT 0 +#define BIT_MASK_MBIST_REPORT 0xffffffffL +#define BIT_MBIST_REPORT(x) \ + (((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT) +#define BITS_MBIST_REPORT (BIT_MASK_MBIST_REPORT << BIT_SHIFT_MBIST_REPORT) +#define BIT_CLEAR_MBIST_REPORT(x) ((x) & (~BITS_MBIST_REPORT)) +#define BIT_GET_MBIST_REPORT(x) \ + (((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT) +#define BIT_SET_MBIST_REPORT(x, v) \ + (BIT_CLEAR_MBIST_REPORT(x) | BIT_MBIST_REPORT(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_MEM_CTRL (Offset 0x00D8) */ -#define BIT_RMV_SIGN BIT(31) +#define BIT_RMV_SIGN BIT(31) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ -#define BIT_UMEM_RME BIT(31) +#define BIT_UMEM_RME BIT(31) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_MEM_CTRL (Offset 0x00D8) */ -#define BIT_RMV_2PRF1 BIT(29) -#define BIT_RMV_2PRF0 BIT(28) +#define BIT_RMV_2PRF1 BIT(29) +#define BIT_RMV_2PRF0 BIT(28) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ - -#define BIT_SHIFT_BT_SPRAM 28 -#define BIT_MASK_BT_SPRAM 0x3 -#define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM) -#define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM) - +#define BIT_SHIFT_BT_SPRAM 28 +#define BIT_MASK_BT_SPRAM 0x3 +#define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM) +#define BITS_BT_SPRAM (BIT_MASK_BT_SPRAM << BIT_SHIFT_BT_SPRAM) +#define BIT_CLEAR_BT_SPRAM(x) ((x) & (~BITS_BT_SPRAM)) +#define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM) +#define BIT_SET_BT_SPRAM(x, v) (BIT_CLEAR_BT_SPRAM(x) | BIT_BT_SPRAM(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_MEM_CTRL (Offset 0x00D8) */ -#define BIT_RMV_1PRF1 BIT(27) -#define BIT_RMV_1PRF0 BIT(26) -#define BIT_RMV_1PSR BIT(25) -#define BIT_RMV_ROM BIT(24) +#define BIT_RMV_1PRF1 BIT(27) +#define BIT_RMV_1PRF0 BIT(26) +#define BIT_RMV_1PSR BIT(25) +#define BIT_RMV_ROM BIT(24) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#define BIT_SHIFT_BT_ROM 24 +#define BIT_MASK_BT_ROM 0xf +#define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM) +#define BITS_BT_ROM (BIT_MASK_BT_ROM << BIT_SHIFT_BT_ROM) +#define BIT_CLEAR_BT_ROM(x) ((x) & (~BITS_BT_ROM)) +#define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM) +#define BIT_SET_BT_ROM(x, v) (BIT_CLEAR_BT_ROM(x) | BIT_BT_ROM(v)) -#define BIT_SHIFT_BT_ROM 24 -#define BIT_MASK_BT_ROM 0xf -#define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM) -#define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM) - - -#define BIT_SHIFT_PCI_DPRAM 10 -#define BIT_MASK_PCI_DPRAM 0x3 -#define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM) -#define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM) - +#define BIT_SHIFT_PCI_DPRAM 10 +#define BIT_MASK_PCI_DPRAM 0x3 +#define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM) +#define BITS_PCI_DPRAM (BIT_MASK_PCI_DPRAM << BIT_SHIFT_PCI_DPRAM) +#define BIT_CLEAR_PCI_DPRAM(x) ((x) & (~BITS_PCI_DPRAM)) +#define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM) +#define BIT_SET_PCI_DPRAM(x, v) (BIT_CLEAR_PCI_DPRAM(x) | BIT_PCI_DPRAM(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_MEM_CTRL (Offset 0x00D8) */ - -#define BIT_SHIFT_MEM_RME_BT 8 -#define BIT_MASK_MEM_RME_BT 0xf -#define BIT_MEM_RME_BT(x) (((x) & BIT_MASK_MEM_RME_BT) << BIT_SHIFT_MEM_RME_BT) -#define BIT_GET_MEM_RME_BT(x) (((x) >> BIT_SHIFT_MEM_RME_BT) & BIT_MASK_MEM_RME_BT) - +#define BIT_SHIFT_MEM_RME_BT 8 +#define BIT_MASK_MEM_RME_BT 0xf +#define BIT_MEM_RME_BT(x) (((x) & BIT_MASK_MEM_RME_BT) << BIT_SHIFT_MEM_RME_BT) +#define BITS_MEM_RME_BT (BIT_MASK_MEM_RME_BT << BIT_SHIFT_MEM_RME_BT) +#define BIT_CLEAR_MEM_RME_BT(x) ((x) & (~BITS_MEM_RME_BT)) +#define BIT_GET_MEM_RME_BT(x) \ + (((x) >> BIT_SHIFT_MEM_RME_BT) & BIT_MASK_MEM_RME_BT) +#define BIT_SET_MEM_RME_BT(x, v) (BIT_CLEAR_MEM_RME_BT(x) | BIT_MEM_RME_BT(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#define BIT_SHIFT_PCI_SPRAM 8 +#define BIT_MASK_PCI_SPRAM 0x3 +#define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM) +#define BITS_PCI_SPRAM (BIT_MASK_PCI_SPRAM << BIT_SHIFT_PCI_SPRAM) +#define BIT_CLEAR_PCI_SPRAM(x) ((x) & (~BITS_PCI_SPRAM)) +#define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM) +#define BIT_SET_PCI_SPRAM(x, v) (BIT_CLEAR_PCI_SPRAM(x) | BIT_PCI_SPRAM(v)) -#define BIT_SHIFT_PCI_SPRAM 8 -#define BIT_MASK_PCI_SPRAM 0x3 -#define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM) -#define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM) - - -#define BIT_SHIFT_USB_SPRAM 6 -#define BIT_MASK_USB_SPRAM 0x3 -#define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM) -#define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM) - +#define BIT_SHIFT_USB_SPRAM 6 +#define BIT_MASK_USB_SPRAM 0x3 +#define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM) +#define BITS_USB_SPRAM (BIT_MASK_USB_SPRAM << BIT_SHIFT_USB_SPRAM) +#define BIT_CLEAR_USB_SPRAM(x) ((x) & (~BITS_USB_SPRAM)) +#define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM) +#define BIT_SET_USB_SPRAM(x, v) (BIT_CLEAR_USB_SPRAM(x) | BIT_USB_SPRAM(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_MEM_CTRL (Offset 0x00D8) */ - -#define BIT_SHIFT_MEM_RME_WL 4 -#define BIT_MASK_MEM_RME_WL 0xf -#define BIT_MEM_RME_WL(x) (((x) & BIT_MASK_MEM_RME_WL) << BIT_SHIFT_MEM_RME_WL) -#define BIT_GET_MEM_RME_WL(x) (((x) >> BIT_SHIFT_MEM_RME_WL) & BIT_MASK_MEM_RME_WL) - +#define BIT_SHIFT_MEM_RME_WL 4 +#define BIT_MASK_MEM_RME_WL 0xf +#define BIT_MEM_RME_WL(x) (((x) & BIT_MASK_MEM_RME_WL) << BIT_SHIFT_MEM_RME_WL) +#define BITS_MEM_RME_WL (BIT_MASK_MEM_RME_WL << BIT_SHIFT_MEM_RME_WL) +#define BIT_CLEAR_MEM_RME_WL(x) ((x) & (~BITS_MEM_RME_WL)) +#define BIT_GET_MEM_RME_WL(x) \ + (((x) >> BIT_SHIFT_MEM_RME_WL) & BIT_MASK_MEM_RME_WL) +#define BIT_SET_MEM_RME_WL(x, v) (BIT_CLEAR_MEM_RME_WL(x) | BIT_MEM_RME_WL(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ - -#define BIT_SHIFT_USB_SPRF 4 -#define BIT_MASK_USB_SPRF 0x3 -#define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF) -#define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF) - +#define BIT_SHIFT_USB_SPRF 4 +#define BIT_MASK_USB_SPRF 0x3 +#define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF) +#define BITS_USB_SPRF (BIT_MASK_USB_SPRF << BIT_SHIFT_USB_SPRF) +#define BIT_CLEAR_USB_SPRF(x) ((x) & (~BITS_USB_SPRF)) +#define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF) +#define BIT_SET_USB_SPRF(x, v) (BIT_CLEAR_USB_SPRF(x) | BIT_USB_SPRF(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_MEM_CTRL (Offset 0x00D8) */ - -#define BIT_SHIFT_MEM_RME_HCI 0 -#define BIT_MASK_MEM_RME_HCI 0xf -#define BIT_MEM_RME_HCI(x) (((x) & BIT_MASK_MEM_RME_HCI) << BIT_SHIFT_MEM_RME_HCI) -#define BIT_GET_MEM_RME_HCI(x) (((x) >> BIT_SHIFT_MEM_RME_HCI) & BIT_MASK_MEM_RME_HCI) - +#define BIT_SHIFT_MEM_RME_HCI 0 +#define BIT_MASK_MEM_RME_HCI 0xf +#define BIT_MEM_RME_HCI(x) \ + (((x) & BIT_MASK_MEM_RME_HCI) << BIT_SHIFT_MEM_RME_HCI) +#define BITS_MEM_RME_HCI (BIT_MASK_MEM_RME_HCI << BIT_SHIFT_MEM_RME_HCI) +#define BIT_CLEAR_MEM_RME_HCI(x) ((x) & (~BITS_MEM_RME_HCI)) +#define BIT_GET_MEM_RME_HCI(x) \ + (((x) >> BIT_SHIFT_MEM_RME_HCI) & BIT_MASK_MEM_RME_HCI) +#define BIT_SET_MEM_RME_HCI(x, v) \ + (BIT_CLEAR_MEM_RME_HCI(x) | BIT_MEM_RME_HCI(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ - -#define BIT_SHIFT_MCU_ROM 0 -#define BIT_MASK_MCU_ROM 0xf -#define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM) -#define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM) - +#define BIT_SHIFT_MCU_ROM 0 +#define BIT_MASK_MCU_ROM 0xf +#define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM) +#define BITS_MCU_ROM (BIT_MASK_MCU_ROM << BIT_SHIFT_MCU_ROM) +#define BIT_CLEAR_MCU_ROM(x) ((x) & (~BITS_MCU_ROM)) +#define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM) +#define BIT_SET_MCU_ROM(x, v) (BIT_CLEAR_MCU_ROM(x) | BIT_MCU_ROM(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#define BIT_SHIFT_BIST_ROM 0 +#define BIT_MASK_BIST_ROM 0xffffffffL +#define BIT_BIST_ROM(x) (((x) & BIT_MASK_BIST_ROM) << BIT_SHIFT_BIST_ROM) +#define BITS_BIST_ROM (BIT_MASK_BIST_ROM << BIT_SHIFT_BIST_ROM) +#define BIT_CLEAR_BIST_ROM(x) ((x) & (~BITS_BIST_ROM)) +#define BIT_GET_BIST_ROM(x) (((x) >> BIT_SHIFT_BIST_ROM) & BIT_MASK_BIST_ROM) +#define BIT_SET_BIST_ROM(x, v) (BIT_CLEAR_BIST_ROM(x) | BIT_BIST_ROM(v)) -#define BIT_SHIFT_BIST_ROM 0 -#define BIT_MASK_BIST_ROM 0xffffffffL -#define BIT_BIST_ROM(x) (((x) & BIT_MASK_BIST_ROM) << BIT_SHIFT_BIST_ROM) -#define BIT_GET_BIST_ROM(x) (((x) >> BIT_SHIFT_BIST_ROM) & BIT_MASK_BIST_ROM) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4 26 +#define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 0x7 +#define BIT_BB_DBG_SEL_AFE_SDM_V4(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4) \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) +#define BITS_BB_DBG_SEL_AFE_SDM_V4 \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) & \ + BIT_MASK_BB_DBG_SEL_AFE_SDM_V4) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4(x) | BIT_BB_DBG_SEL_AFE_SDM_V4(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#define BIT_SYN_AGPIO BIT(20) -#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4 26 -#define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 0x7 -#define BIT_BB_DBG_SEL_AFE_SDM_V4(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4) +#endif +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_SYN_RFC_CTRL (Offset 0x00DC) */ +#define BIT_SHIFT_SYN_RF1_CTRL 8 +#define BIT_MASK_SYN_RF1_CTRL 0xff +#define BIT_SYN_RF1_CTRL(x) \ + (((x) & BIT_MASK_SYN_RF1_CTRL) << BIT_SHIFT_SYN_RF1_CTRL) +#define BITS_SYN_RF1_CTRL (BIT_MASK_SYN_RF1_CTRL << BIT_SHIFT_SYN_RF1_CTRL) +#define BIT_CLEAR_SYN_RF1_CTRL(x) ((x) & (~BITS_SYN_RF1_CTRL)) +#define BIT_GET_SYN_RF1_CTRL(x) \ + (((x) >> BIT_SHIFT_SYN_RF1_CTRL) & BIT_MASK_SYN_RF1_CTRL) +#define BIT_SET_SYN_RF1_CTRL(x, v) \ + (BIT_CLEAR_SYN_RF1_CTRL(x) | BIT_SYN_RF1_CTRL(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ -#define BIT_SYN_AGPIO BIT(20) +#define BIT_XTAL_LP BIT(4) +#define BIT_XTAL_GM_SEP BIT(3) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ -#define BIT_XTAL_LP BIT(4) -#define BIT_XTAL_GM_SEP BIT(3) +#define BIT_SHIFT_XTAL_SEL_TOK_V2 0 +#define BIT_MASK_XTAL_SEL_TOK_V2 0x7 +#define BIT_XTAL_SEL_TOK_V2(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_V2) << BIT_SHIFT_XTAL_SEL_TOK_V2) +#define BITS_XTAL_SEL_TOK_V2 \ + (BIT_MASK_XTAL_SEL_TOK_V2 << BIT_SHIFT_XTAL_SEL_TOK_V2) +#define BIT_CLEAR_XTAL_SEL_TOK_V2(x) ((x) & (~BITS_XTAL_SEL_TOK_V2)) +#define BIT_GET_XTAL_SEL_TOK_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2) & BIT_MASK_XTAL_SEL_TOK_V2) +#define BIT_SET_XTAL_SEL_TOK_V2(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_V2(x) | BIT_XTAL_SEL_TOK_V2(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_WLAN_DBG (Offset 0x00DC) */ +#define BIT_SHIFT_WLAN_DBG 0 +#define BIT_MASK_WLAN_DBG 0xffffffffL +#define BIT_WLAN_DBG(x) (((x) & BIT_MASK_WLAN_DBG) << BIT_SHIFT_WLAN_DBG) +#define BITS_WLAN_DBG (BIT_MASK_WLAN_DBG << BIT_SHIFT_WLAN_DBG) +#define BIT_CLEAR_WLAN_DBG(x) ((x) & (~BITS_WLAN_DBG)) +#define BIT_GET_WLAN_DBG(x) (((x) >> BIT_SHIFT_WLAN_DBG) & BIT_MASK_WLAN_DBG) +#define BIT_SET_WLAN_DBG(x, v) (BIT_CLEAR_WLAN_DBG(x) | BIT_WLAN_DBG(v)) -/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_XTAL_SEL_TOK_V2 0 -#define BIT_MASK_XTAL_SEL_TOK_V2 0x7 -#define BIT_XTAL_SEL_TOK_V2(x) (((x) & BIT_MASK_XTAL_SEL_TOK_V2) << BIT_SHIFT_XTAL_SEL_TOK_V2) -#define BIT_GET_XTAL_SEL_TOK_V2(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2) & BIT_MASK_XTAL_SEL_TOK_V2) +/* 2 REG_SYN_RFC_CTRL (Offset 0x00DC) */ +#define BIT_SHIFT_SYN_RF0_CTRL 0 +#define BIT_MASK_SYN_RF0_CTRL 0xff +#define BIT_SYN_RF0_CTRL(x) \ + (((x) & BIT_MASK_SYN_RF0_CTRL) << BIT_SHIFT_SYN_RF0_CTRL) +#define BITS_SYN_RF0_CTRL (BIT_MASK_SYN_RF0_CTRL << BIT_SHIFT_SYN_RF0_CTRL) +#define BIT_CLEAR_SYN_RF0_CTRL(x) ((x) & (~BITS_SYN_RF0_CTRL)) +#define BIT_GET_SYN_RF0_CTRL(x) \ + (((x) >> BIT_SHIFT_SYN_RF0_CTRL) & BIT_MASK_SYN_RF0_CTRL) +#define BIT_SET_SYN_RF0_CTRL(x, v) \ + (BIT_CLEAR_SYN_RF0_CTRL(x) | BIT_SYN_RF0_CTRL(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#define BIT_SHIFT_XTAL_SEL_TOK 0 +#define BIT_MASK_XTAL_SEL_TOK 0x7 +#define BIT_XTAL_SEL_TOK(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK) +#define BITS_XTAL_SEL_TOK (BIT_MASK_XTAL_SEL_TOK << BIT_SHIFT_XTAL_SEL_TOK) +#define BIT_CLEAR_XTAL_SEL_TOK(x) ((x) & (~BITS_XTAL_SEL_TOK)) +#define BIT_GET_XTAL_SEL_TOK(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK) +#define BIT_SET_XTAL_SEL_TOK(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK(x) | BIT_XTAL_SEL_TOK(v)) -/* 2 REG_WLAN_DBG (Offset 0x00DC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WLAN_DBG 0 -#define BIT_MASK_WLAN_DBG 0xffffffffL -#define BIT_WLAN_DBG(x) (((x) & BIT_MASK_WLAN_DBG) << BIT_SHIFT_WLAN_DBG) -#define BIT_GET_WLAN_DBG(x) (((x) >> BIT_SHIFT_WLAN_DBG) & BIT_MASK_WLAN_DBG) +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#define BIT_RD_SEL BIT(31) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#define BIT_CPU_REG_SEL BIT(31) +#define BIT_USB3_REG_SEL BIT(30) -/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_XTAL_SEL_TOK 0 -#define BIT_MASK_XTAL_SEL_TOK 0x7 -#define BIT_XTAL_SEL_TOK(x) (((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK) -#define BIT_GET_XTAL_SEL_TOK(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK) +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#define BIT_USB_SIE_INTF_WE_V1 BIT(30) +#define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29) +#define BIT_USB_SIE_SELECT BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ -#define BIT_RD_SEL BIT(31) - -#endif +#define BIT_USB_SIE_INTF_WE BIT(25) +#define BIT_USB_SIE_INTF_BYIOREG BIT(24) +#define BIT_SHIFT_USB_SIE_INTF_ADDR 16 +#define BIT_MASK_USB_SIE_INTF_ADDR 0xff +#define BIT_USB_SIE_INTF_ADDR(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_ADDR) << BIT_SHIFT_USB_SIE_INTF_ADDR) +#define BITS_USB_SIE_INTF_ADDR \ + (BIT_MASK_USB_SIE_INTF_ADDR << BIT_SHIFT_USB_SIE_INTF_ADDR) +#define BIT_CLEAR_USB_SIE_INTF_ADDR(x) ((x) & (~BITS_USB_SIE_INTF_ADDR)) +#define BIT_GET_USB_SIE_INTF_ADDR(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR) & BIT_MASK_USB_SIE_INTF_ADDR) +#define BIT_SET_USB_SIE_INTF_ADDR(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_ADDR(x) | BIT_USB_SIE_INTF_ADDR(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ -#define BIT_CPU_REG_SEL BIT(31) -#define BIT_USB3_REG_SEL BIT(30) +#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16 +#define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff +#define BIT_USB_SIE_INTF_ADDR_V1(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1) \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1) +#define BITS_USB_SIE_INTF_ADDR_V1 \ + (BIT_MASK_USB_SIE_INTF_ADDR_V1 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1) +#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1(x) ((x) & (~BITS_USB_SIE_INTF_ADDR_V1)) +#define BIT_GET_USB_SIE_INTF_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) & \ + BIT_MASK_USB_SIE_INTF_ADDR_V1) +#define BIT_SET_USB_SIE_INTF_ADDR_V1(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_ADDR_V1(x) | BIT_USB_SIE_INTF_ADDR_V1(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ -#define BIT_USB_SIE_INTF_WE_V1 BIT(30) -#define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29) -#define BIT_USB_SIE_SELECT BIT(28) +#define BIT_SHIFT_USB_SIE_INTF_RD 8 +#define BIT_MASK_USB_SIE_INTF_RD 0xff +#define BIT_USB_SIE_INTF_RD(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD) +#define BITS_USB_SIE_INTF_RD \ + (BIT_MASK_USB_SIE_INTF_RD << BIT_SHIFT_USB_SIE_INTF_RD) +#define BIT_CLEAR_USB_SIE_INTF_RD(x) ((x) & (~BITS_USB_SIE_INTF_RD)) +#define BIT_GET_USB_SIE_INTF_RD(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD) +#define BIT_SET_USB_SIE_INTF_RD(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_RD(x) | BIT_USB_SIE_INTF_RD(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ -#define BIT_USB_SIE_INTF_WE BIT(25) -#define BIT_USB_SIE_INTF_BYIOREG BIT(24) - -#define BIT_SHIFT_USB_SIE_INTF_ADDR 16 -#define BIT_MASK_USB_SIE_INTF_ADDR 0xff -#define BIT_USB_SIE_INTF_ADDR(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR) << BIT_SHIFT_USB_SIE_INTF_ADDR) -#define BIT_GET_USB_SIE_INTF_ADDR(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR) & BIT_MASK_USB_SIE_INTF_ADDR) - +#define BIT_SHIFT_NPQ_AVAL_PG 8 +#define BIT_MASK_NPQ_AVAL_PG 0xff +#define BIT_NPQ_AVAL_PG(x) \ + (((x) & BIT_MASK_NPQ_AVAL_PG) << BIT_SHIFT_NPQ_AVAL_PG) +#define BITS_NPQ_AVAL_PG (BIT_MASK_NPQ_AVAL_PG << BIT_SHIFT_NPQ_AVAL_PG) +#define BIT_CLEAR_NPQ_AVAL_PG(x) ((x) & (~BITS_NPQ_AVAL_PG)) +#define BIT_GET_NPQ_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_NPQ_AVAL_PG) & BIT_MASK_NPQ_AVAL_PG) +#define BIT_SET_NPQ_AVAL_PG(x, v) \ + (BIT_CLEAR_NPQ_AVAL_PG(x) | BIT_NPQ_AVAL_PG(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#define BIT_SHIFT_USB_SIE_INTF_WD 0 +#define BIT_MASK_USB_SIE_INTF_WD 0xff +#define BIT_USB_SIE_INTF_WD(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD) +#define BITS_USB_SIE_INTF_WD \ + (BIT_MASK_USB_SIE_INTF_WD << BIT_SHIFT_USB_SIE_INTF_WD) +#define BIT_CLEAR_USB_SIE_INTF_WD(x) ((x) & (~BITS_USB_SIE_INTF_WD)) +#define BIT_GET_USB_SIE_INTF_WD(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD) +#define BIT_SET_USB_SIE_INTF_WD(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_WD(x) | BIT_USB_SIE_INTF_WD(v)) -/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16 -#define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff -#define BIT_USB_SIE_INTF_ADDR_V1(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1) -#define BIT_GET_USB_SIE_INTF_ADDR_V1(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) & BIT_MASK_USB_SIE_INTF_ADDR_V1) +/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ +#define BIT_PCIE_MIO_EXIT_L1 BIT(19) +#define BIT_PCIE_MIO_EXT BIT(18) +#define BIT_PCIE_MIO_ACK BIT(17) +#define BIT_PCIE_MIO_IOREG BIT(16) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ +#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE 16 +#define BIT_MASK_PCIE_MIO_ADDR_PAGE 0x3 +#define BIT_PCIE_MIO_ADDR_PAGE(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE) << BIT_SHIFT_PCIE_MIO_ADDR_PAGE) +#define BITS_PCIE_MIO_ADDR_PAGE \ + (BIT_MASK_PCIE_MIO_ADDR_PAGE << BIT_SHIFT_PCIE_MIO_ADDR_PAGE) +#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE(x) ((x) & (~BITS_PCIE_MIO_ADDR_PAGE)) +#define BIT_GET_PCIE_MIO_ADDR_PAGE(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE) & BIT_MASK_PCIE_MIO_ADDR_PAGE) +#define BIT_SET_PCIE_MIO_ADDR_PAGE(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_PAGE(x) | BIT_PCIE_MIO_ADDR_PAGE(v)) -/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_USB_SIE_INTF_RD 8 -#define BIT_MASK_USB_SIE_INTF_RD 0xff -#define BIT_USB_SIE_INTF_RD(x) (((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD) -#define BIT_GET_USB_SIE_INTF_RD(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD) +/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ +#define BIT_PCIE_MIO_BYIOREG BIT(13) +#define BIT_PCIE_MIO_RE BIT(12) + +#define BIT_SHIFT_PCIE_MIO_WE 8 +#define BIT_MASK_PCIE_MIO_WE 0xf +#define BIT_PCIE_MIO_WE(x) \ + (((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE) +#define BITS_PCIE_MIO_WE (BIT_MASK_PCIE_MIO_WE << BIT_SHIFT_PCIE_MIO_WE) +#define BIT_CLEAR_PCIE_MIO_WE(x) ((x) & (~BITS_PCIE_MIO_WE)) +#define BIT_GET_PCIE_MIO_WE(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE) +#define BIT_SET_PCIE_MIO_WE(x, v) \ + (BIT_CLEAR_PCIE_MIO_WE(x) | BIT_PCIE_MIO_WE(v)) + +#define BIT_SHIFT_PCIE_MIO_ADDR 0 +#define BIT_MASK_PCIE_MIO_ADDR 0xff +#define BIT_PCIE_MIO_ADDR(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR) +#define BITS_PCIE_MIO_ADDR (BIT_MASK_PCIE_MIO_ADDR << BIT_SHIFT_PCIE_MIO_ADDR) +#define BIT_CLEAR_PCIE_MIO_ADDR(x) ((x) & (~BITS_PCIE_MIO_ADDR)) +#define BIT_GET_PCIE_MIO_ADDR(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR) +#define BIT_SET_PCIE_MIO_ADDR(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR(x) | BIT_PCIE_MIO_ADDR(v)) -#define BIT_SHIFT_USB_SIE_INTF_WD 0 -#define BIT_MASK_USB_SIE_INTF_WD 0xff -#define BIT_USB_SIE_INTF_WD(x) (((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD) -#define BIT_GET_USB_SIE_INTF_WD(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD) +/* 2 REG_PCIE_MIO_INTD (Offset 0x00E8) */ +#define BIT_SHIFT_PCIE_MIO_DATA 0 +#define BIT_MASK_PCIE_MIO_DATA 0xffffffffL +#define BIT_PCIE_MIO_DATA(x) \ + (((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA) +#define BITS_PCIE_MIO_DATA (BIT_MASK_PCIE_MIO_DATA << BIT_SHIFT_PCIE_MIO_DATA) +#define BIT_CLEAR_PCIE_MIO_DATA(x) ((x) & (~BITS_PCIE_MIO_DATA)) +#define BIT_GET_PCIE_MIO_DATA(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA) +#define BIT_SET_PCIE_MIO_DATA(x, v) \ + (BIT_CLEAR_PCIE_MIO_DATA(x) | BIT_PCIE_MIO_DATA(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HPON_FSM (Offset 0x00EC) */ -/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ +#define BIT_SUSPEND_V1 BIT(31) +#define BIT_FSM_RESUME_V1 BIT(30) +#define BIT_HOST_RESUME_SYNC_V1 BIT(29) +#define BIT_CHIP_PDNB_V1 BIT(28) -#define BIT_PCIE_MIO_EXIT_L1 BIT(19) -#define BIT_PCIE_MIO_EXT BIT(18) -#define BIT_PCIE_MIO_ACK BIT(17) -#define BIT_PCIE_MIO_IOREG BIT(16) +#define BIT_SHIFT_FSM_SUSPEND_V1 25 +#define BIT_MASK_FSM_SUSPEND_V1 0x7 +#define BIT_FSM_SUSPEND_V1(x) \ + (((x) & BIT_MASK_FSM_SUSPEND_V1) << BIT_SHIFT_FSM_SUSPEND_V1) +#define BITS_FSM_SUSPEND_V1 \ + (BIT_MASK_FSM_SUSPEND_V1 << BIT_SHIFT_FSM_SUSPEND_V1) +#define BIT_CLEAR_FSM_SUSPEND_V1(x) ((x) & (~BITS_FSM_SUSPEND_V1)) +#define BIT_GET_FSM_SUSPEND_V1(x) \ + (((x) >> BIT_SHIFT_FSM_SUSPEND_V1) & BIT_MASK_FSM_SUSPEND_V1) +#define BIT_SET_FSM_SUSPEND_V1(x, v) \ + (BIT_CLEAR_FSM_SUSPEND_V1(x) | BIT_FSM_SUSPEND_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ +/* 2 REG_WLRF1 (Offset 0x00EC) */ -#define BIT_PCIE_MIO_BYIOREG BIT(13) -#define BIT_PCIE_MIO_RE BIT(12) +#define BIT_SHIFT_XTAL_SEL 25 +#define BIT_MASK_XTAL_SEL 0x3 +#define BIT_XTAL_SEL(x) (((x) & BIT_MASK_XTAL_SEL) << BIT_SHIFT_XTAL_SEL) +#define BITS_XTAL_SEL (BIT_MASK_XTAL_SEL << BIT_SHIFT_XTAL_SEL) +#define BIT_CLEAR_XTAL_SEL(x) ((x) & (~BITS_XTAL_SEL)) +#define BIT_GET_XTAL_SEL(x) (((x) >> BIT_SHIFT_XTAL_SEL) & BIT_MASK_XTAL_SEL) +#define BIT_SET_XTAL_SEL(x, v) (BIT_CLEAR_XTAL_SEL(x) | BIT_XTAL_SEL(v)) -#define BIT_SHIFT_PCIE_MIO_WE 8 -#define BIT_MASK_PCIE_MIO_WE 0xf -#define BIT_PCIE_MIO_WE(x) (((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE) -#define BIT_GET_PCIE_MIO_WE(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_PCIE_MIO_ADDR 0 -#define BIT_MASK_PCIE_MIO_ADDR 0xff -#define BIT_PCIE_MIO_ADDR(x) (((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR) -#define BIT_GET_PCIE_MIO_ADDR(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR) +/* 2 REG_HPON_FSM (Offset 0x00EC) */ +#define BIT_PMC_ALD_V1 BIT(24) -/* 2 REG_PCIE_MIO_INTD (Offset 0x00E8) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PCIE_MIO_DATA 0 -#define BIT_MASK_PCIE_MIO_DATA 0xffffffffL -#define BIT_PCIE_MIO_DATA(x) (((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA) -#define BIT_GET_PCIE_MIO_DATA(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA) +/* 2 REG_WLRF1 (Offset 0x00EC) */ +#define BIT_SHIFT_WLRF1_CTRL 24 +#define BIT_MASK_WLRF1_CTRL 0xff +#define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL) +#define BITS_WLRF1_CTRL (BIT_MASK_WLRF1_CTRL << BIT_SHIFT_WLRF1_CTRL) +#define BIT_CLEAR_WLRF1_CTRL(x) ((x) & (~BITS_WLRF1_CTRL)) +#define BIT_GET_WLRF1_CTRL(x) \ + (((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL) +#define BIT_SET_WLRF1_CTRL(x, v) (BIT_CLEAR_WLRF1_CTRL(x) | BIT_WLRF1_CTRL(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_HPON_FSM (Offset 0x00EC) */ -#define BIT_SUSPEND_V1 BIT(31) -#define BIT_FSM_RESUME_V1 BIT(30) -#define BIT_HOST_RESUME_SYNC_V1 BIT(29) -#define BIT_CHIP_PDNB_V1 BIT(28) - -#define BIT_SHIFT_FSM_SUSPEND_V1 25 -#define BIT_MASK_FSM_SUSPEND_V1 0x7 -#define BIT_FSM_SUSPEND_V1(x) (((x) & BIT_MASK_FSM_SUSPEND_V1) << BIT_SHIFT_FSM_SUSPEND_V1) -#define BIT_GET_FSM_SUSPEND_V1(x) (((x) >> BIT_SHIFT_FSM_SUSPEND_V1) & BIT_MASK_FSM_SUSPEND_V1) +#define BIT_SHIFT_HCI_SEL_1 22 +#define BIT_MASK_HCI_SEL_1 0x3 +#define BIT_HCI_SEL_1(x) (((x) & BIT_MASK_HCI_SEL_1) << BIT_SHIFT_HCI_SEL_1) +#define BITS_HCI_SEL_1 (BIT_MASK_HCI_SEL_1 << BIT_SHIFT_HCI_SEL_1) +#define BIT_CLEAR_HCI_SEL_1(x) ((x) & (~BITS_HCI_SEL_1)) +#define BIT_GET_HCI_SEL_1(x) (((x) >> BIT_SHIFT_HCI_SEL_1) & BIT_MASK_HCI_SEL_1) +#define BIT_SET_HCI_SEL_1(x, v) (BIT_CLEAR_HCI_SEL_1(x) | BIT_HCI_SEL_1(v)) -#define BIT_PMC_ALD_V1 BIT(24) +#define BIT_LOAD_DONE_V1 BIT(21) +#define BIT_CNT_MATCH BIT(20) +#define BIT_TIMEUP_V1 BIT(19) +#define BIT_SPS_12V_VLD BIT(18) +#define BIT_PCIERST_V1 BIT(17) +#define BIT_HOST_CLK_VLD BIT(16) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_WLRF1 (Offset 0x00EC) */ - -#define BIT_SHIFT_WLRF1_CTRL 24 -#define BIT_MASK_WLRF1_CTRL 0xff -#define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL) -#define BIT_GET_WLRF1_CTRL(x) (((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL) - +#define BIT_SHIFT_WLRF2_CTRL 16 +#define BIT_MASK_WLRF2_CTRL 0xff +#define BIT_WLRF2_CTRL(x) (((x) & BIT_MASK_WLRF2_CTRL) << BIT_SHIFT_WLRF2_CTRL) +#define BITS_WLRF2_CTRL (BIT_MASK_WLRF2_CTRL << BIT_SHIFT_WLRF2_CTRL) +#define BIT_CLEAR_WLRF2_CTRL(x) ((x) & (~BITS_WLRF2_CTRL)) +#define BIT_GET_WLRF2_CTRL(x) \ + (((x) >> BIT_SHIFT_WLRF2_CTRL) & BIT_MASK_WLRF2_CTRL) +#define BIT_SET_WLRF2_CTRL(x, v) (BIT_CLEAR_WLRF2_CTRL(x) | BIT_WLRF2_CTRL(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_HPON_FSM (Offset 0x00EC) */ +#define BIT_PMC_WR_V1 BIT(15) +#define BIT_PMC_DATA_V1 BIT(14) -#define BIT_SHIFT_HCI_SEL_1 22 -#define BIT_MASK_HCI_SEL_1 0x3 -#define BIT_HCI_SEL_1(x) (((x) & BIT_MASK_HCI_SEL_1) << BIT_SHIFT_HCI_SEL_1) -#define BIT_GET_HCI_SEL_1(x) (((x) >> BIT_SHIFT_HCI_SEL_1) & BIT_MASK_HCI_SEL_1) - -#define BIT_LOAD_DONE_V1 BIT(21) -#define BIT_CNT_MATCH BIT(20) -#define BIT_TIMEUP_V1 BIT(19) -#define BIT_SPS_12V_VLD BIT(18) -#define BIT_PCIERST_V1 BIT(17) -#define BIT_HOST_CLK_VLD BIT(16) -#define BIT_PMC_WR_V1 BIT(15) -#define BIT_PMC_DATA_V1 BIT(14) +#define BIT_SHIFT_PMC_ADDR_V1 8 +#define BIT_MASK_PMC_ADDR_V1 0x3f +#define BIT_PMC_ADDR_V1(x) \ + (((x) & BIT_MASK_PMC_ADDR_V1) << BIT_SHIFT_PMC_ADDR_V1) +#define BITS_PMC_ADDR_V1 (BIT_MASK_PMC_ADDR_V1 << BIT_SHIFT_PMC_ADDR_V1) +#define BIT_CLEAR_PMC_ADDR_V1(x) ((x) & (~BITS_PMC_ADDR_V1)) +#define BIT_GET_PMC_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_PMC_ADDR_V1) & BIT_MASK_PMC_ADDR_V1) +#define BIT_SET_PMC_ADDR_V1(x, v) \ + (BIT_CLEAR_PMC_ADDR_V1(x) | BIT_PMC_ADDR_V1(v)) -#define BIT_SHIFT_PMC_ADDR_V1 8 -#define BIT_MASK_PMC_ADDR_V1 0x3f -#define BIT_PMC_ADDR_V1(x) (((x) & BIT_MASK_PMC_ADDR_V1) << BIT_SHIFT_PMC_ADDR_V1) -#define BIT_GET_PMC_ADDR_V1(x) (((x) >> BIT_SHIFT_PMC_ADDR_V1) & BIT_MASK_PMC_ADDR_V1) +#endif -#define BIT_PMC_COUNT_EN_V1 BIT(7) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_FSM_STATE_V1 0 -#define BIT_MASK_FSM_STATE_V1 0x7f -#define BIT_FSM_STATE_V1(x) (((x) & BIT_MASK_FSM_STATE_V1) << BIT_SHIFT_FSM_STATE_V1) -#define BIT_GET_FSM_STATE_V1(x) (((x) >> BIT_SHIFT_FSM_STATE_V1) & BIT_MASK_FSM_STATE_V1) +/* 2 REG_WLRF1 (Offset 0x00EC) */ +#define BIT_SHIFT_WLRF3_CTRL 8 +#define BIT_MASK_WLRF3_CTRL 0xff +#define BIT_WLRF3_CTRL(x) (((x) & BIT_MASK_WLRF3_CTRL) << BIT_SHIFT_WLRF3_CTRL) +#define BITS_WLRF3_CTRL (BIT_MASK_WLRF3_CTRL << BIT_SHIFT_WLRF3_CTRL) +#define BIT_CLEAR_WLRF3_CTRL(x) ((x) & (~BITS_WLRF3_CTRL)) +#define BIT_GET_WLRF3_CTRL(x) \ + (((x) >> BIT_SHIFT_WLRF3_CTRL) & BIT_MASK_WLRF3_CTRL) +#define BIT_SET_WLRF3_CTRL(x, v) (BIT_CLEAR_WLRF3_CTRL(x) | BIT_WLRF3_CTRL(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_HPON_FSM (Offset 0x00EC) */ -/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_PMC_COUNT_EN_V1 BIT(7) +#define BIT_SHIFT_FSM_STATE_V1 0 +#define BIT_MASK_FSM_STATE_V1 0x7f +#define BIT_FSM_STATE_V1(x) \ + (((x) & BIT_MASK_FSM_STATE_V1) << BIT_SHIFT_FSM_STATE_V1) +#define BITS_FSM_STATE_V1 (BIT_MASK_FSM_STATE_V1 << BIT_SHIFT_FSM_STATE_V1) +#define BIT_CLEAR_FSM_STATE_V1(x) ((x) & (~BITS_FSM_STATE_V1)) +#define BIT_GET_FSM_STATE_V1(x) \ + (((x) >> BIT_SHIFT_FSM_STATE_V1) & BIT_MASK_FSM_STATE_V1) +#define BIT_SET_FSM_STATE_V1(x, v) \ + (BIT_CLEAR_FSM_STATE_V1(x) | BIT_FSM_STATE_V1(v)) -#define BIT_SHIFT_TRP_ICFG 28 -#define BIT_MASK_TRP_ICFG 0xf -#define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG) -#define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_SHIFT_TRP_ICFG 28 +#define BIT_MASK_TRP_ICFG 0xf +#define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG) +#define BITS_TRP_ICFG (BIT_MASK_TRP_ICFG << BIT_SHIFT_TRP_ICFG) +#define BIT_CLEAR_TRP_ICFG(x) ((x) & (~BITS_TRP_ICFG)) +#define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG) +#define BIT_SET_TRP_ICFG(x, v) (BIT_CLEAR_TRP_ICFG(x) | BIT_TRP_ICFG(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_RF_TYPE_ID BIT(27) -#define BIT_BD_HCI_SEL BIT(26) +#define BIT_RF_TYPE_ID BIT(27) +#define BIT_BD_HCI_SEL BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ - -#define BIT_SHIFT_BD_HCI_SEL 26 -#define BIT_MASK_BD_HCI_SEL 0x3 -#define BIT_BD_HCI_SEL(x) (((x) & BIT_MASK_BD_HCI_SEL) << BIT_SHIFT_BD_HCI_SEL) -#define BIT_GET_BD_HCI_SEL(x) (((x) >> BIT_SHIFT_BD_HCI_SEL) & BIT_MASK_BD_HCI_SEL) - +#define BIT_SHIFT_BD_HCI_SEL_V1 26 +#define BIT_MASK_BD_HCI_SEL_V1 0x3 +#define BIT_BD_HCI_SEL_V1(x) \ + (((x) & BIT_MASK_BD_HCI_SEL_V1) << BIT_SHIFT_BD_HCI_SEL_V1) +#define BITS_BD_HCI_SEL_V1 (BIT_MASK_BD_HCI_SEL_V1 << BIT_SHIFT_BD_HCI_SEL_V1) +#define BIT_CLEAR_BD_HCI_SEL_V1(x) ((x) & (~BITS_BD_HCI_SEL_V1)) +#define BIT_GET_BD_HCI_SEL_V1(x) \ + (((x) >> BIT_SHIFT_BD_HCI_SEL_V1) & BIT_MASK_BD_HCI_SEL_V1) +#define BIT_SET_BD_HCI_SEL_V1(x, v) \ + (BIT_CLEAR_BD_HCI_SEL_V1(x) | BIT_BD_HCI_SEL_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_BD_PKG_SEL BIT(25) +#define BIT_BD_PKG_SEL BIT(25) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_SPSLDO_SEL BIT(24) +#define BIT_SPSLDO_SEL BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_LDO_SPS_SEL BIT(24) +#define BIT_LDO_SPS_SEL BIT(24) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_RTL_ID BIT(23) -#define BIT_PAD_HWPD_IDN BIT(22) +#define BIT_INTERNAL_EXTERNAL_SWR BIT(24) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_TESTMODE BIT(20) +#define BIT_RTL_ID BIT(23) +#define BIT_PAD_HWPD_IDN BIT(22) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ - -#define BIT_SHIFT_PSC_TESTCFG 20 -#define BIT_MASK_PSC_TESTCFG 0x3 -#define BIT_PSC_TESTCFG(x) (((x) & BIT_MASK_PSC_TESTCFG) << BIT_SHIFT_PSC_TESTCFG) -#define BIT_GET_PSC_TESTCFG(x) (((x) >> BIT_SHIFT_PSC_TESTCFG) & BIT_MASK_PSC_TESTCFG) - +#define BIT_TESTMODE BIT(20) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_SHIFT_PSC_TESTCFG 20 +#define BIT_MASK_PSC_TESTCFG 0x3 +#define BIT_PSC_TESTCFG(x) \ + (((x) & BIT_MASK_PSC_TESTCFG) << BIT_SHIFT_PSC_TESTCFG) +#define BITS_PSC_TESTCFG (BIT_MASK_PSC_TESTCFG << BIT_SHIFT_PSC_TESTCFG) +#define BIT_CLEAR_PSC_TESTCFG(x) ((x) & (~BITS_PSC_TESTCFG)) +#define BIT_GET_PSC_TESTCFG(x) \ + (((x) >> BIT_SHIFT_PSC_TESTCFG) & BIT_MASK_PSC_TESTCFG) +#define BIT_SET_PSC_TESTCFG(x, v) \ + (BIT_CLEAR_PSC_TESTCFG(x) | BIT_PSC_TESTCFG(v)) -/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VENDOR_ID 16 -#define BIT_MASK_VENDOR_ID 0xf -#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) -#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_SHIFT_VENDOR_ID 16 +#define BIT_MASK_VENDOR_ID 0xf +#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) +#define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID) +#define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID)) +#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) +#define BIT_SET_VENDOR_ID(x, v) (BIT_CLEAR_VENDOR_ID(x) | BIT_VENDOR_ID(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ - -#define BIT_SHIFT_CHIP_VER_V2 16 -#define BIT_MASK_CHIP_VER_V2 0xf -#define BIT_CHIP_VER_V2(x) (((x) & BIT_MASK_CHIP_VER_V2) << BIT_SHIFT_CHIP_VER_V2) -#define BIT_GET_CHIP_VER_V2(x) (((x) >> BIT_SHIFT_CHIP_VER_V2) & BIT_MASK_CHIP_VER_V2) - +#define BIT_SHIFT_CHIP_VER_V2 16 +#define BIT_MASK_CHIP_VER_V2 0xf +#define BIT_CHIP_VER_V2(x) \ + (((x) & BIT_MASK_CHIP_VER_V2) << BIT_SHIFT_CHIP_VER_V2) +#define BITS_CHIP_VER_V2 (BIT_MASK_CHIP_VER_V2 << BIT_SHIFT_CHIP_VER_V2) +#define BIT_CLEAR_CHIP_VER_V2(x) ((x) & (~BITS_CHIP_VER_V2)) +#define BIT_GET_CHIP_VER_V2(x) \ + (((x) >> BIT_SHIFT_CHIP_VER_V2) & BIT_MASK_CHIP_VER_V2) +#define BIT_SET_CHIP_VER_V2(x, v) \ + (BIT_CLEAR_CHIP_VER_V2(x) | BIT_CHIP_VER_V2(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ - -#define BIT_SHIFT_CHIP_VER 12 -#define BIT_MASK_CHIP_VER 0xf -#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) -#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) - +#define BIT_SHIFT_CHIP_VER 12 +#define BIT_MASK_CHIP_VER 0xf +#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) +#define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER) +#define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER)) +#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) +#define BIT_SET_CHIP_VER(x, v) (BIT_CLEAR_CHIP_VER(x) | BIT_CHIP_VER(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_IC_MACPHY_MODE BIT(11) +#define BIT_IC_MACPHY_MODE BIT(11) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_BD_MAC3 BIT(11) +#define BIT_BD_MAC3 BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_BD_MAC1 BIT(10) -#define BIT_BD_MAC2 BIT(9) -#define BIT_SIC_IDLE BIT(8) -#define BIT_SW_OFFLOAD_EN BIT(7) +#define BIT_BD_MAC1 BIT(10) +#define BIT_BD_MAC2 BIT(9) +#define BIT_SIC_IDLE BIT(8) +#define BIT_SW_OFFLOAD_EN BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_OCP_SHUTDN BIT(6) +#define BIT_OCP_SHUTDN BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_OCP_SHUTDN_1 BIT(6) +#define BIT_OCP_SHUTDN_1 BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_V15_VLD BIT(5) +#define BIT_V15_VLD BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_V12_VLD BIT(5) +#define BIT_V12_VLD BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_PCIRSTB BIT(4) +#define BIT_PCIRSTB BIT(4) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_PCLK_VLD BIT(3) +#define BIT_PCLK_VLD BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_PCLK_VLD_1 BIT(3) +#define BIT_PCLK_VLD_1 BIT(3) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_UCLK_VLD BIT(2) +#define BIT_UCLK_VLD BIT(2) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_ACLK_VLD BIT(1) +#define BIT_ACLK_VLD BIT(1) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_M200CLK_VLD_V1 BIT(1) +#define BIT_M200CLK_VLD_V1 BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_XCLK_VLD BIT(0) +#define BIT_XCLK_VLD BIT(0) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ - -#define BIT_SHIFT_RF_RL_ID 28 -#define BIT_MASK_RF_RL_ID 0xf -#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID) -#define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID) - +#define BIT_SHIFT_RF_RL_ID 28 +#define BIT_MASK_RF_RL_ID 0xf +#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID) +#define BITS_RF_RL_ID (BIT_MASK_RF_RL_ID << BIT_SHIFT_RF_RL_ID) +#define BIT_CLEAR_RF_RL_ID(x) ((x) & (~BITS_RF_RL_ID)) +#define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID) +#define BIT_SET_RF_RL_ID(x, v) (BIT_CLEAR_RF_RL_ID(x) | BIT_RF_RL_ID(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_U3_CLK_VLD BIT(27) -#define BIT_PRST_VLD_V1 BIT(26) -#define BIT_PDN BIT(25) -#define BIT_OCP_SHUTDN_V1 BIT(24) -#define BIT_PCLK_VLD_V1 BIT(23) -#define BIT_U2_CLK_VLD BIT(22) -#define BIT_PLL_CLK_VLD BIT(21) -#define BIT_XCK_VLD BIT(20) +#define BIT_U3_CLK_VLD BIT(27) +#define BIT_PRST_VLD_V1 BIT(26) +#define BIT_PDN BIT(25) +#define BIT_OCP_SHUTDN_V1 BIT(24) +#define BIT_PCLK_VLD_V1 BIT(23) +#define BIT_U2_CLK_VLD BIT(22) +#define BIT_PLL_CLK_VLD BIT(21) +#define BIT_XCK_VLD BIT(20) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_HPHY_ICFG BIT(19) +#define BIT_HPHY_ICFG BIT(19) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_CK200M_VLD BIT(19) -#define BIT_BTEN_TRAP BIT(18) -#define BIT_PKG_EN_V1 BIT(17) +#define BIT_CK200M_VLD BIT(19) +#define BIT_BTEN_TRAP BIT(18) +#define BIT_PKG_EN_V1 BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ - -#define BIT_SHIFT_SEL_0XC0 16 -#define BIT_MASK_SEL_0XC0 0x3 -#define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0) -#define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0) - +#define BIT_SHIFT_SEL_0XC0 16 +#define BIT_MASK_SEL_0XC0 0x3 +#define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0) +#define BITS_SEL_0XC0 (BIT_MASK_SEL_0XC0 << BIT_SHIFT_SEL_0XC0) +#define BIT_CLEAR_SEL_0XC0(x) ((x) & (~BITS_SEL_0XC0)) +#define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0) +#define BIT_SET_SEL_0XC0(x, v) (BIT_CLEAR_SEL_0XC0(x) | BIT_SEL_0XC0(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_TRAP_LDO_SPS_V1 BIT(16) -#define BIT_MACRDY BIT(15) -#define BIT_12V_VLD BIT(14) -#define BIT_U3PHY_RST BIT(13) -#define BIT_USB2_SEL_V1 BIT(12) +#define BIT_TRAP_LDO_SPS_V1 BIT(16) +#define BIT_MACRDY BIT(15) +#define BIT_12V_VLD BIT(14) +#define BIT_U3PHY_RST BIT(13) +#define BIT_USB2_SEL_V1 BIT(12) #endif - -#if (HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_HCI_SEL_V4 12 +#define BIT_MASK_HCI_SEL_V4 0x3 +#define BIT_HCI_SEL_V4(x) (((x) & BIT_MASK_HCI_SEL_V4) << BIT_SHIFT_HCI_SEL_V4) +#define BITS_HCI_SEL_V4 (BIT_MASK_HCI_SEL_V4 << BIT_SHIFT_HCI_SEL_V4) +#define BIT_CLEAR_HCI_SEL_V4(x) ((x) & (~BITS_HCI_SEL_V4)) +#define BIT_GET_HCI_SEL_V4(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V4) & BIT_MASK_HCI_SEL_V4) +#define BIT_SET_HCI_SEL_V4(x, v) (BIT_CLEAR_HCI_SEL_V4(x) | BIT_HCI_SEL_V4(v)) -#define BIT_SHIFT_HCI_SEL_V3 12 -#define BIT_MASK_HCI_SEL_V3 0x7 -#define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3) -#define BIT_GET_HCI_SEL_V3(x) (((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3) +#endif +#if (HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_HCI_SEL_V3 12 +#define BIT_MASK_HCI_SEL_V3 0x7 +#define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3) +#define BITS_HCI_SEL_V3 (BIT_MASK_HCI_SEL_V3 << BIT_SHIFT_HCI_SEL_V3) +#define BIT_CLEAR_HCI_SEL_V3(x) ((x) & (~BITS_HCI_SEL_V3)) +#define BIT_GET_HCI_SEL_V3(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3) +#define BIT_SET_HCI_SEL_V3(x, v) (BIT_CLEAR_HCI_SEL_V3(x) | BIT_HCI_SEL_V3(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_USB_OPERATION_MODE BIT(10) -#define BIT_BT_PDN BIT(9) -#define BIT_AUTO_WLPON BIT(8) +#define BIT_USB_OPERATION_MODE BIT(10) +#define BIT_BT_PDN BIT(9) +#define BIT_AUTO_WLPON BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ - -#define BIT_SHIFT_TRAP_ICFG 8 -#define BIT_MASK_TRAP_ICFG 0xf -#define BIT_TRAP_ICFG(x) (((x) & BIT_MASK_TRAP_ICFG) << BIT_SHIFT_TRAP_ICFG) -#define BIT_GET_TRAP_ICFG(x) (((x) >> BIT_SHIFT_TRAP_ICFG) & BIT_MASK_TRAP_ICFG) - +#define BIT_SHIFT_TRAP_ICFG 8 +#define BIT_MASK_TRAP_ICFG 0xf +#define BIT_TRAP_ICFG(x) (((x) & BIT_MASK_TRAP_ICFG) << BIT_SHIFT_TRAP_ICFG) +#define BITS_TRAP_ICFG (BIT_MASK_TRAP_ICFG << BIT_SHIFT_TRAP_ICFG) +#define BIT_CLEAR_TRAP_ICFG(x) ((x) & (~BITS_TRAP_ICFG)) +#define BIT_GET_TRAP_ICFG(x) (((x) >> BIT_SHIFT_TRAP_ICFG) & BIT_MASK_TRAP_ICFG) +#define BIT_SET_TRAP_ICFG(x, v) (BIT_CLEAR_TRAP_ICFG(x) | BIT_TRAP_ICFG(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_WL_MODE BIT(7) +#define BIT_WL_MODE BIT(7) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_WLAN_ID BIT(7) +#define BIT_WLAN_ID BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_PKG_SEL_HCI BIT(6) +#define BIT_PKG_SEL_HCI BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_ALDN BIT(6) -#define BIT_BTCOEX_CMDEN BIT(5) +#define BIT_ALDN BIT(6) +#define BIT_BTCOEX_CMDEN BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_HCI_SEL 4 +#define BIT_MASK_HCI_SEL 0x3 +#define BIT_HCI_SEL(x) (((x) & BIT_MASK_HCI_SEL) << BIT_SHIFT_HCI_SEL) +#define BITS_HCI_SEL (BIT_MASK_HCI_SEL << BIT_SHIFT_HCI_SEL) +#define BIT_CLEAR_HCI_SEL(x) ((x) & (~BITS_HCI_SEL)) +#define BIT_GET_HCI_SEL(x) (((x) >> BIT_SHIFT_HCI_SEL) & BIT_MASK_HCI_SEL) +#define BIT_SET_HCI_SEL(x, v) (BIT_CLEAR_HCI_SEL(x) | BIT_HCI_SEL(v)) -#define BIT_SHIFT_HCI_SEL 4 -#define BIT_MASK_HCI_SEL 0x3 -#define BIT_HCI_SEL(x) (((x) & BIT_MASK_HCI_SEL) << BIT_SHIFT_HCI_SEL) -#define BIT_GET_HCI_SEL(x) (((x) >> BIT_SHIFT_HCI_SEL) & BIT_MASK_HCI_SEL) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_BT_EN BIT(4) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_BT_EN BIT(4) +#define BIT_SHIFT_PAD_HCI_SEL_V2 3 +#define BIT_MASK_PAD_HCI_SEL_V2 0x3 +#define BIT_PAD_HCI_SEL_V2(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_V2) << BIT_SHIFT_PAD_HCI_SEL_V2) +#define BITS_PAD_HCI_SEL_V2 \ + (BIT_MASK_PAD_HCI_SEL_V2 << BIT_SHIFT_PAD_HCI_SEL_V2) +#define BIT_CLEAR_PAD_HCI_SEL_V2(x) ((x) & (~BITS_PAD_HCI_SEL_V2)) +#define BIT_GET_PAD_HCI_SEL_V2(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2) & BIT_MASK_PAD_HCI_SEL_V2) +#define BIT_SET_PAD_HCI_SEL_V2(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_V2(x) | BIT_PAD_HCI_SEL_V2(v)) #endif - #if (HALMAC_8822B_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_PAD_HCI_SEL_V1 3 +#define BIT_MASK_PAD_HCI_SEL_V1 0x7 +#define BIT_PAD_HCI_SEL_V1(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1) +#define BITS_PAD_HCI_SEL_V1 \ + (BIT_MASK_PAD_HCI_SEL_V1 << BIT_SHIFT_PAD_HCI_SEL_V1) +#define BIT_CLEAR_PAD_HCI_SEL_V1(x) ((x) & (~BITS_PAD_HCI_SEL_V1)) +#define BIT_GET_PAD_HCI_SEL_V1(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1) +#define BIT_SET_PAD_HCI_SEL_V1(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_V1(x) | BIT_PAD_HCI_SEL_V1(v)) -#define BIT_SHIFT_PAD_HCI_SEL_V1 3 -#define BIT_MASK_PAD_HCI_SEL_V1 0x7 -#define BIT_PAD_HCI_SEL_V1(x) (((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1) -#define BIT_GET_PAD_HCI_SEL_V1(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_PAD_HCI_SEL 2 +#define BIT_MASK_PAD_HCI_SEL 0x3 +#define BIT_PAD_HCI_SEL(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL) << BIT_SHIFT_PAD_HCI_SEL) +#define BITS_PAD_HCI_SEL (BIT_MASK_PAD_HCI_SEL << BIT_SHIFT_PAD_HCI_SEL) +#define BIT_CLEAR_PAD_HCI_SEL(x) ((x) & (~BITS_PAD_HCI_SEL)) +#define BIT_GET_PAD_HCI_SEL(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL) & BIT_MASK_PAD_HCI_SEL) +#define BIT_SET_PAD_HCI_SEL(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL(x) | BIT_PAD_HCI_SEL(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_HCI_SEL_V2 2 +#define BIT_MASK_HCI_SEL_V2 0x3 +#define BIT_HCI_SEL_V2(x) (((x) & BIT_MASK_HCI_SEL_V2) << BIT_SHIFT_HCI_SEL_V2) +#define BITS_HCI_SEL_V2 (BIT_MASK_HCI_SEL_V2 << BIT_SHIFT_HCI_SEL_V2) +#define BIT_CLEAR_HCI_SEL_V2(x) ((x) & (~BITS_HCI_SEL_V2)) +#define BIT_GET_HCI_SEL_V2(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V2) & BIT_MASK_HCI_SEL_V2) +#define BIT_SET_HCI_SEL_V2(x, v) (BIT_CLEAR_HCI_SEL_V2(x) | BIT_HCI_SEL_V2(v)) -#define BIT_SHIFT_PAD_HCI_SEL 2 -#define BIT_MASK_PAD_HCI_SEL 0x3 -#define BIT_PAD_HCI_SEL(x) (((x) & BIT_MASK_PAD_HCI_SEL) << BIT_SHIFT_PAD_HCI_SEL) -#define BIT_GET_PAD_HCI_SEL(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL) & BIT_MASK_PAD_HCI_SEL) - +#define BIT_TST_MOD_SEL BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_EFS_HCI_SEL 0 +#define BIT_MASK_EFS_HCI_SEL 0x3 +#define BIT_EFS_HCI_SEL(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL) << BIT_SHIFT_EFS_HCI_SEL) +#define BITS_EFS_HCI_SEL (BIT_MASK_EFS_HCI_SEL << BIT_SHIFT_EFS_HCI_SEL) +#define BIT_CLEAR_EFS_HCI_SEL(x) ((x) & (~BITS_EFS_HCI_SEL)) +#define BIT_GET_EFS_HCI_SEL(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL) & BIT_MASK_EFS_HCI_SEL) +#define BIT_SET_EFS_HCI_SEL(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL(x) | BIT_EFS_HCI_SEL(v)) -/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_HCI_SEL_V2 2 -#define BIT_MASK_HCI_SEL_V2 0x3 -#define BIT_HCI_SEL_V2(x) (((x) & BIT_MASK_HCI_SEL_V2) << BIT_SHIFT_HCI_SEL_V2) -#define BIT_GET_HCI_SEL_V2(x) (((x) >> BIT_SHIFT_HCI_SEL_V2) & BIT_MASK_HCI_SEL_V2) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_TST_MOD_SEL BIT(1) +#define BIT_PAD_HWPDB BIT(0) #endif +#if (HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_EFS_HCI_SEL_V1 0 +#define BIT_MASK_EFS_HCI_SEL_V1 0x7 +#define BIT_EFS_HCI_SEL_V1(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1) +#define BITS_EFS_HCI_SEL_V1 \ + (BIT_MASK_EFS_HCI_SEL_V1 << BIT_SHIFT_EFS_HCI_SEL_V1) +#define BIT_CLEAR_EFS_HCI_SEL_V1(x) ((x) & (~BITS_EFS_HCI_SEL_V1)) +#define BIT_GET_EFS_HCI_SEL_V1(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1) +#define BIT_SET_EFS_HCI_SEL_V1(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL_V1(x) | BIT_EFS_HCI_SEL_V1(v)) -/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_EFS_HCI_SEL 0 -#define BIT_MASK_EFS_HCI_SEL 0x3 -#define BIT_EFS_HCI_SEL(x) (((x) & BIT_MASK_EFS_HCI_SEL) << BIT_SHIFT_EFS_HCI_SEL) -#define BIT_GET_EFS_HCI_SEL(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL) & BIT_MASK_EFS_HCI_SEL) +/* 2 REG_SYS_STATUS2 (Offset 0x00F8) */ +#define BIT_HIOE_ON_TIMEOUT BIT(23) +#define BIT_SIC_ON_TIMEOUT BIT(22) +#define BIT_CPU_ON_TIMEOUT BIT(21) +#define BIT_HCI_ON_TIMEOUT BIT(20) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_STATUS2 (Offset 0x00F8) */ +#define BIT_SIO_ALDN BIT(19) +#define BIT_USB_ALDN BIT(18) +#define BIT_PCI_ALDN BIT(17) +#define BIT_SYS_ALDN BIT(16) -/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_EPVID1 8 +#define BIT_MASK_EPVID1 0xff +#define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1) +#define BITS_EPVID1 (BIT_MASK_EPVID1 << BIT_SHIFT_EPVID1) +#define BIT_CLEAR_EPVID1(x) ((x) & (~BITS_EPVID1)) +#define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1) +#define BIT_SET_EPVID1(x, v) (BIT_CLEAR_EPVID1(x) | BIT_EPVID1(v)) -#define BIT_PAD_HWPDB BIT(0) +#define BIT_SHIFT_EPVID0 0 +#define BIT_MASK_EPVID0 0xff +#define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0) +#define BITS_EPVID0 (BIT_MASK_EPVID0 << BIT_SHIFT_EPVID0) +#define BIT_CLEAR_EPVID0(x) ((x) & (~BITS_EPVID0)) +#define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0) +#define BIT_SET_EPVID0(x, v) (BIT_CLEAR_EPVID0(x) | BIT_EPVID0(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_USB2_SEL_1 BIT(31) -/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_EFS_HCI_SEL_V1 0 -#define BIT_MASK_EFS_HCI_SEL_V1 0x7 -#define BIT_EFS_HCI_SEL_V1(x) (((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1) -#define BIT_GET_EFS_HCI_SEL_V1(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_USB2_SEL BIT(31) +#define BIT_FEN_WLMAC_OFF BIT(31) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_SYS_STATUS2 (Offset 0x00F8) */ +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ -#define BIT_SIO_ALDN BIT(19) -#define BIT_USB_ALDN BIT(18) -#define BIT_PCI_ALDN BIT(17) -#define BIT_SYS_ALDN BIT(16) +#define BIT_USB3PHY_RST BIT(30) -#define BIT_SHIFT_EPVID1 8 -#define BIT_MASK_EPVID1 0xff -#define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1) -#define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_EPVID0 0 -#define BIT_MASK_EPVID0 0xff -#define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0) -#define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_U3PHY_RST_V1 BIT(30) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ -#define BIT_USB2_SEL_1 BIT(31) -#define BIT_USB3PHY_RST BIT(30) -#define BIT_U3_TERM_DET BIT(29) -#define BIT_USB23_DBG_SEL BIT(24) +#define BIT_U3_TERM_DET BIT(29) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ -#define BIT_HCI_SEL_EMBEDED BIT(8) +#define BIT_U3_TERM_DETECT BIT(29) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_USB23_DBG_SEL BIT(24) -/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HW_ID 0 -#define BIT_MASK_HW_ID 0xff -#define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID) -#define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_HCI_SEL_EMBEDDED BIT(8) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_ISO_BB2PP BIT(7) +#define BIT_ISO_DENG2PP BIT(6) -/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CHIPID 0 -#define BIT_MASK_CHIPID 0xff -#define BIT_CHIPID(x) (((x) & BIT_MASK_CHIPID) << BIT_SHIFT_CHIPID) -#define BIT_GET_CHIPID(x) (((x) >> BIT_SHIFT_CHIPID) & BIT_MASK_CHIPID) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_SHIFT_HW_ID 0 +#define BIT_MASK_HW_ID 0xff +#define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID) +#define BITS_HW_ID (BIT_MASK_HW_ID << BIT_SHIFT_HW_ID) +#define BIT_CLEAR_HW_ID(x) ((x) & (~BITS_HW_ID)) +#define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID) +#define BIT_SET_HW_ID(x, v) (BIT_CLEAR_HW_ID(x) | BIT_HW_ID(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_SHIFT_CHIPID 0 +#define BIT_MASK_CHIPID 0xff +#define BIT_CHIPID(x) (((x) & BIT_MASK_CHIPID) << BIT_SHIFT_CHIPID) +#define BITS_CHIPID (BIT_MASK_CHIPID << BIT_SHIFT_CHIPID) +#define BIT_CLEAR_CHIPID(x) ((x) & (~BITS_CHIPID)) +#define BIT_GET_CHIPID(x) (((x) >> BIT_SHIFT_CHIPID) & BIT_MASK_CHIPID) +#define BIT_SET_CHIPID(x, v) (BIT_CLEAR_CHIPID(x) | BIT_CHIPID(v)) -/* 2 REG_CR (Offset 0x0100) */ +#endif -#define BIT_MACIO_TIMEOUT_EN BIT(29) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_MACIO_TIMEOUT_EN BIT(29) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ +#define BIT_SHIFT_LBMODE 24 +#define BIT_MASK_LBMODE 0x1f +#define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE) +#define BITS_LBMODE (BIT_MASK_LBMODE << BIT_SHIFT_LBMODE) +#define BIT_CLEAR_LBMODE(x) ((x) & (~BITS_LBMODE)) +#define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE) +#define BIT_SET_LBMODE(x, v) (BIT_CLEAR_LBMODE(x) | BIT_LBMODE(v)) -#define BIT_SHIFT_LBMODE 24 -#define BIT_MASK_LBMODE 0x1f -#define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE) -#define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE) +#define BIT_SHIFT_NETYPE1 18 +#define BIT_MASK_NETYPE1 0x3 +#define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1) +#define BITS_NETYPE1 (BIT_MASK_NETYPE1 << BIT_SHIFT_NETYPE1) +#define BIT_CLEAR_NETYPE1(x) ((x) & (~BITS_NETYPE1)) +#define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1) +#define BIT_SET_NETYPE1(x, v) (BIT_CLEAR_NETYPE1(x) | BIT_NETYPE1(v)) +#define BIT_SHIFT_NETYPE0 16 +#define BIT_MASK_NETYPE0 0x3 +#define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0) +#define BITS_NETYPE0 (BIT_MASK_NETYPE0 << BIT_SHIFT_NETYPE0) +#define BIT_CLEAR_NETYPE0(x) ((x) & (~BITS_NETYPE0)) +#define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0) +#define BIT_SET_NETYPE0(x, v) (BIT_CLEAR_NETYPE0(x) | BIT_NETYPE0(v)) -#define BIT_SHIFT_NETYPE1 18 -#define BIT_MASK_NETYPE1 0x3 -#define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1) -#define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_NETYPE0 16 -#define BIT_MASK_NETYPE0 0x3 -#define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0) -#define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0) +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_STAT_FUNC_RST BIT(13) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ -#define BIT_STAT_FUNC_RST BIT(13) +#define BIT_COUNTER_STS_EN BIT(13) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_CR (Offset 0x0100) */ -#define BIT_PTA_I2C_MBOX_EN BIT(12) +#define BIT_PTA_I2C_MBOX_EN BIT(12) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ -#define BIT_I2C_MAILBOX_EN BIT(12) -#define BIT_SHCUT_EN BIT(11) +#define BIT_I2C_MAILBOX_EN BIT(12) +#define BIT_SHCUT_EN BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ -#define BIT_32K_CAL_TMR_EN BIT(10) -#define BIT_MAC_SEC_EN BIT(9) -#define BIT_ENSWBCN BIT(8) -#define BIT_MACRXEN BIT(7) -#define BIT_MACTXEN BIT(6) -#define BIT_SCHEDULE_EN BIT(5) -#define BIT_PROTOCOL_EN BIT(4) -#define BIT_RXDMA_EN BIT(3) -#define BIT_TXDMA_EN BIT(2) -#define BIT_HCI_RXDMA_EN BIT(1) -#define BIT_HCI_TXDMA_EN BIT(0) +#define BIT_32K_CAL_TMR_EN BIT(10) +#define BIT_MAC_SEC_EN BIT(9) +#define BIT_ENSWBCN BIT(8) +#define BIT_MACRXEN BIT(7) +#define BIT_MACTXEN BIT(6) +#define BIT_SCHEDULE_EN BIT(5) +#define BIT_PROTOCOL_EN BIT(4) +#define BIT_RXDMA_EN BIT(3) +#define BIT_TXDMA_EN BIT(2) +#define BIT_HCI_RXDMA_EN BIT(1) +#define BIT_HCI_TXDMA_EN BIT(0) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PG_SIZE (Offset 0x0104) */ +#define BIT_SHIFT_DBG_FIFO_SEL 16 +#define BIT_MASK_DBG_FIFO_SEL 0xff +#define BIT_DBG_FIFO_SEL(x) \ + (((x) & BIT_MASK_DBG_FIFO_SEL) << BIT_SHIFT_DBG_FIFO_SEL) +#define BITS_DBG_FIFO_SEL (BIT_MASK_DBG_FIFO_SEL << BIT_SHIFT_DBG_FIFO_SEL) +#define BIT_CLEAR_DBG_FIFO_SEL(x) ((x) & (~BITS_DBG_FIFO_SEL)) +#define BIT_GET_DBG_FIFO_SEL(x) \ + (((x) >> BIT_SHIFT_DBG_FIFO_SEL) & BIT_MASK_DBG_FIFO_SEL) +#define BIT_SET_DBG_FIFO_SEL(x, v) \ + (BIT_CLEAR_DBG_FIFO_SEL(x) | BIT_DBG_FIFO_SEL(v)) -/* 2 REG_PKT_BUFF_ACCESS_CTRL (Offset 0x0106) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0 -#define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff -#define BIT_PKT_BUFF_ACCESS_CTRL(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) -#define BIT_GET_PKT_BUFF_ACCESS_CTRL(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) +/* 2 REG_PKT_BUFF_ACCESS_CTRL (Offset 0x0106) */ +#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0 +#define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff +#define BIT_PKT_BUFF_ACCESS_CTRL(x) \ + (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) +#define BITS_PKT_BUFF_ACCESS_CTRL \ + (BIT_MASK_PKT_BUFF_ACCESS_CTRL << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) +#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL)) +#define BIT_GET_PKT_BUFF_ACCESS_CTRL(x) \ + (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) & \ + BIT_MASK_PKT_BUFF_ACCESS_CTRL) +#define BIT_SET_PKT_BUFF_ACCESS_CTRL(x, v) \ + (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) | BIT_PKT_BUFF_ACCESS_CTRL(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ -#define BIT_TSF_CLK_IDX BIT(15) +#define BIT_TSF_CLK_IDX BIT(15) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ -#define BIT_TSF_CLK_STABLE BIT(15) +#define BIT_TSF_CLK_STABLE BIT(15) -#define BIT_SHIFT_I2C_M_BUS_GNT_FW 4 -#define BIT_MASK_I2C_M_BUS_GNT_FW 0x7 -#define BIT_I2C_M_BUS_GNT_FW(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW) -#define BIT_GET_I2C_M_BUS_GNT_FW(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW) +#define BIT_SHIFT_I2C_M_BUS_GNT_FW 4 +#define BIT_MASK_I2C_M_BUS_GNT_FW 0x7 +#define BIT_I2C_M_BUS_GNT_FW(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW) +#define BITS_I2C_M_BUS_GNT_FW \ + (BIT_MASK_I2C_M_BUS_GNT_FW << BIT_SHIFT_I2C_M_BUS_GNT_FW) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW(x) ((x) & (~BITS_I2C_M_BUS_GNT_FW)) +#define BIT_GET_I2C_M_BUS_GNT_FW(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW) +#define BIT_SET_I2C_M_BUS_GNT_FW(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT_FW(x) | BIT_I2C_M_BUS_GNT_FW(v)) -#define BIT_I2C_M_GNT_FW BIT(3) +#define BIT_I2C_M_GNT_FW BIT(3) -#define BIT_SHIFT_I2C_M_SPEED 1 -#define BIT_MASK_I2C_M_SPEED 0x3 -#define BIT_I2C_M_SPEED(x) (((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED) -#define BIT_GET_I2C_M_SPEED(x) (((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED) +#define BIT_SHIFT_I2C_M_SPEED 1 +#define BIT_MASK_I2C_M_SPEED 0x3 +#define BIT_I2C_M_SPEED(x) \ + (((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED) +#define BITS_I2C_M_SPEED (BIT_MASK_I2C_M_SPEED << BIT_SHIFT_I2C_M_SPEED) +#define BIT_CLEAR_I2C_M_SPEED(x) ((x) & (~BITS_I2C_M_SPEED)) +#define BIT_GET_I2C_M_SPEED(x) \ + (((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED) +#define BIT_SET_I2C_M_SPEED(x, v) \ + (BIT_CLEAR_I2C_M_SPEED(x) | BIT_I2C_M_SPEED(v)) -#define BIT_I2C_M_UNLOCK BIT(0) +#define BIT_I2C_M_UNLOCK BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ - -#define BIT_SHIFT_TXDMA_CMQ_MAP 16 -#define BIT_MASK_TXDMA_CMQ_MAP 0x3 -#define BIT_TXDMA_CMQ_MAP(x) (((x) & BIT_MASK_TXDMA_CMQ_MAP) << BIT_SHIFT_TXDMA_CMQ_MAP) -#define BIT_GET_TXDMA_CMQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_CMQ_MAP) & BIT_MASK_TXDMA_CMQ_MAP) - +#define BIT_CSI_BW_EN BIT(31) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_HIQ_MAP_V1 19 +#define BIT_MASK_TXDMA_HIQ_MAP_V1 0x7 +#define BIT_TXDMA_HIQ_MAP_V1(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP_V1) << BIT_SHIFT_TXDMA_HIQ_MAP_V1) +#define BITS_TXDMA_HIQ_MAP_V1 \ + (BIT_MASK_TXDMA_HIQ_MAP_V1 << BIT_SHIFT_TXDMA_HIQ_MAP_V1) +#define BIT_CLEAR_TXDMA_HIQ_MAP_V1(x) ((x) & (~BITS_TXDMA_HIQ_MAP_V1)) +#define BIT_GET_TXDMA_HIQ_MAP_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_V1) & BIT_MASK_TXDMA_HIQ_MAP_V1) +#define BIT_SET_TXDMA_HIQ_MAP_V1(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP_V1(x) | BIT_TXDMA_HIQ_MAP_V1(v)) -#define BIT_SHIFT_TXDMA_HIQ_MAP 14 -#define BIT_MASK_TXDMA_HIQ_MAP 0x3 -#define BIT_TXDMA_HIQ_MAP(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) -#define BIT_GET_TXDMA_HIQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TXDMA_MGQ_MAP 12 -#define BIT_MASK_TXDMA_MGQ_MAP 0x3 -#define BIT_TXDMA_MGQ_MAP(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) -#define BIT_GET_TXDMA_MGQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_CMQ_MAP 16 +#define BIT_MASK_TXDMA_CMQ_MAP 0x3 +#define BIT_TXDMA_CMQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_CMQ_MAP) << BIT_SHIFT_TXDMA_CMQ_MAP) +#define BITS_TXDMA_CMQ_MAP (BIT_MASK_TXDMA_CMQ_MAP << BIT_SHIFT_TXDMA_CMQ_MAP) +#define BIT_CLEAR_TXDMA_CMQ_MAP(x) ((x) & (~BITS_TXDMA_CMQ_MAP)) +#define BIT_GET_TXDMA_CMQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_CMQ_MAP) & BIT_MASK_TXDMA_CMQ_MAP) +#define BIT_SET_TXDMA_CMQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_CMQ_MAP(x) | BIT_TXDMA_CMQ_MAP(v)) -#define BIT_SHIFT_TXDMA_BKQ_MAP 10 -#define BIT_MASK_TXDMA_BKQ_MAP 0x3 -#define BIT_TXDMA_BKQ_MAP(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) -#define BIT_GET_TXDMA_BKQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_TXDMA_BEQ_MAP 8 -#define BIT_MASK_TXDMA_BEQ_MAP 0x3 -#define BIT_TXDMA_BEQ_MAP(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) -#define BIT_GET_TXDMA_BEQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_MGQ_MAP_V1 16 +#define BIT_MASK_TXDMA_MGQ_MAP_V1 0x7 +#define BIT_TXDMA_MGQ_MAP_V1(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP_V1) << BIT_SHIFT_TXDMA_MGQ_MAP_V1) +#define BITS_TXDMA_MGQ_MAP_V1 \ + (BIT_MASK_TXDMA_MGQ_MAP_V1 << BIT_SHIFT_TXDMA_MGQ_MAP_V1) +#define BIT_CLEAR_TXDMA_MGQ_MAP_V1(x) ((x) & (~BITS_TXDMA_MGQ_MAP_V1)) +#define BIT_GET_TXDMA_MGQ_MAP_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_V1) & BIT_MASK_TXDMA_MGQ_MAP_V1) +#define BIT_SET_TXDMA_MGQ_MAP_V1(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP_V1(x) | BIT_TXDMA_MGQ_MAP_V1(v)) -#define BIT_SHIFT_TXDMA_VIQ_MAP 6 -#define BIT_MASK_TXDMA_VIQ_MAP 0x3 -#define BIT_TXDMA_VIQ_MAP(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) -#define BIT_GET_TXDMA_VIQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TXDMA_VOQ_MAP 4 -#define BIT_MASK_TXDMA_VOQ_MAP 0x3 -#define BIT_TXDMA_VOQ_MAP(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) -#define BIT_GET_TXDMA_VOQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ -#define BIT_RXDMA_AGG_EN BIT(2) -#define BIT_RXSHFT_EN BIT(1) -#define BIT_RXDMA_ARBBW_EN BIT(0) +#define BIT_SHIFT_TXDMA_H2C_MAP 16 +#define BIT_MASK_TXDMA_H2C_MAP 0x3 +#define BIT_TXDMA_H2C_MAP(x) \ + (((x) & BIT_MASK_TXDMA_H2C_MAP) << BIT_SHIFT_TXDMA_H2C_MAP) +#define BITS_TXDMA_H2C_MAP (BIT_MASK_TXDMA_H2C_MAP << BIT_SHIFT_TXDMA_H2C_MAP) +#define BIT_CLEAR_TXDMA_H2C_MAP(x) ((x) & (~BITS_TXDMA_H2C_MAP)) +#define BIT_GET_TXDMA_H2C_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_H2C_MAP) & BIT_MASK_TXDMA_H2C_MAP) +#define BIT_SET_TXDMA_H2C_MAP(x, v) \ + (BIT_CLEAR_TXDMA_H2C_MAP(x) | BIT_TXDMA_H2C_MAP(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_HIQ_MAP 14 +#define BIT_MASK_TXDMA_HIQ_MAP 0x3 +#define BIT_TXDMA_HIQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) +#define BITS_TXDMA_HIQ_MAP (BIT_MASK_TXDMA_HIQ_MAP << BIT_SHIFT_TXDMA_HIQ_MAP) +#define BIT_CLEAR_TXDMA_HIQ_MAP(x) ((x) & (~BITS_TXDMA_HIQ_MAP)) +#define BIT_GET_TXDMA_HIQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP) +#define BIT_SET_TXDMA_HIQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP(x) | BIT_TXDMA_HIQ_MAP(v)) -/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RXFFOVFL_RSV_V1 28 -#define BIT_MASK_RXFFOVFL_RSV_V1 0xf -#define BIT_RXFFOVFL_RSV_V1(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V1) << BIT_SHIFT_RXFFOVFL_RSV_V1) -#define BIT_GET_RXFFOVFL_RSV_V1(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V1) & BIT_MASK_RXFFOVFL_RSV_V1) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_BKQ_MAP_V1 13 +#define BIT_MASK_TXDMA_BKQ_MAP_V1 0x7 +#define BIT_TXDMA_BKQ_MAP_V1(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP_V1) << BIT_SHIFT_TXDMA_BKQ_MAP_V1) +#define BITS_TXDMA_BKQ_MAP_V1 \ + (BIT_MASK_TXDMA_BKQ_MAP_V1 << BIT_SHIFT_TXDMA_BKQ_MAP_V1) +#define BIT_CLEAR_TXDMA_BKQ_MAP_V1(x) ((x) & (~BITS_TXDMA_BKQ_MAP_V1)) +#define BIT_GET_TXDMA_BKQ_MAP_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_V1) & BIT_MASK_TXDMA_BKQ_MAP_V1) +#define BIT_SET_TXDMA_BKQ_MAP_V1(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP_V1(x) | BIT_TXDMA_BKQ_MAP_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ -/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_TXDMA_MGQ_MAP 12 +#define BIT_MASK_TXDMA_MGQ_MAP 0x3 +#define BIT_TXDMA_MGQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) +#define BITS_TXDMA_MGQ_MAP (BIT_MASK_TXDMA_MGQ_MAP << BIT_SHIFT_TXDMA_MGQ_MAP) +#define BIT_CLEAR_TXDMA_MGQ_MAP(x) ((x) & (~BITS_TXDMA_MGQ_MAP)) +#define BIT_GET_TXDMA_MGQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP) +#define BIT_SET_TXDMA_MGQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP(x) | BIT_TXDMA_MGQ_MAP(v)) +#define BIT_SHIFT_TXDMA_BKQ_MAP 10 +#define BIT_MASK_TXDMA_BKQ_MAP 0x3 +#define BIT_TXDMA_BKQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) +#define BITS_TXDMA_BKQ_MAP (BIT_MASK_TXDMA_BKQ_MAP << BIT_SHIFT_TXDMA_BKQ_MAP) +#define BIT_CLEAR_TXDMA_BKQ_MAP(x) ((x) & (~BITS_TXDMA_BKQ_MAP)) +#define BIT_GET_TXDMA_BKQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP) +#define BIT_SET_TXDMA_BKQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP(x) | BIT_TXDMA_BKQ_MAP(v)) -#define BIT_SHIFT_RXFF0_BNDY 16 -#define BIT_MASK_RXFF0_BNDY 0xffff -#define BIT_RXFF0_BNDY(x) (((x) & BIT_MASK_RXFF0_BNDY) << BIT_SHIFT_RXFF0_BNDY) -#define BIT_GET_RXFF0_BNDY(x) (((x) >> BIT_SHIFT_RXFF0_BNDY) & BIT_MASK_RXFF0_BNDY) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RXFFOVFL_RSV 8 -#define BIT_MASK_RXFFOVFL_RSV 0xf -#define BIT_RXFFOVFL_RSV(x) (((x) & BIT_MASK_RXFFOVFL_RSV) << BIT_SHIFT_RXFFOVFL_RSV) -#define BIT_GET_RXFFOVFL_RSV(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV) & BIT_MASK_RXFFOVFL_RSV) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_BEQ_MAP_V1 10 +#define BIT_MASK_TXDMA_BEQ_MAP_V1 0x7 +#define BIT_TXDMA_BEQ_MAP_V1(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP_V1) << BIT_SHIFT_TXDMA_BEQ_MAP_V1) +#define BITS_TXDMA_BEQ_MAP_V1 \ + (BIT_MASK_TXDMA_BEQ_MAP_V1 << BIT_SHIFT_TXDMA_BEQ_MAP_V1) +#define BIT_CLEAR_TXDMA_BEQ_MAP_V1(x) ((x) & (~BITS_TXDMA_BEQ_MAP_V1)) +#define BIT_GET_TXDMA_BEQ_MAP_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_V1) & BIT_MASK_TXDMA_BEQ_MAP_V1) +#define BIT_SET_TXDMA_BEQ_MAP_V1(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP_V1(x) | BIT_TXDMA_BEQ_MAP_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_BEQ_MAP 8 +#define BIT_MASK_TXDMA_BEQ_MAP 0x3 +#define BIT_TXDMA_BEQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) +#define BITS_TXDMA_BEQ_MAP (BIT_MASK_TXDMA_BEQ_MAP << BIT_SHIFT_TXDMA_BEQ_MAP) +#define BIT_CLEAR_TXDMA_BEQ_MAP(x) ((x) & (~BITS_TXDMA_BEQ_MAP)) +#define BIT_GET_TXDMA_BEQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP) +#define BIT_SET_TXDMA_BEQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP(x) | BIT_TXDMA_BEQ_MAP(v)) -/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RXFFOVFL_RSV_V2 8 -#define BIT_MASK_RXFFOVFL_RSV_V2 0xf -#define BIT_RXFFOVFL_RSV_V2(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2) -#define BIT_GET_RXFFOVFL_RSV_V2(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2) & BIT_MASK_RXFFOVFL_RSV_V2) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_VIQ_MAP_V1 7 +#define BIT_MASK_TXDMA_VIQ_MAP_V1 0x7 +#define BIT_TXDMA_VIQ_MAP_V1(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP_V1) << BIT_SHIFT_TXDMA_VIQ_MAP_V1) +#define BITS_TXDMA_VIQ_MAP_V1 \ + (BIT_MASK_TXDMA_VIQ_MAP_V1 << BIT_SHIFT_TXDMA_VIQ_MAP_V1) +#define BIT_CLEAR_TXDMA_VIQ_MAP_V1(x) ((x) & (~BITS_TXDMA_VIQ_MAP_V1)) +#define BIT_GET_TXDMA_VIQ_MAP_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_V1) & BIT_MASK_TXDMA_VIQ_MAP_V1) +#define BIT_SET_TXDMA_VIQ_MAP_V1(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP_V1(x) | BIT_TXDMA_VIQ_MAP_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_VIQ_MAP 6 +#define BIT_MASK_TXDMA_VIQ_MAP 0x3 +#define BIT_TXDMA_VIQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) +#define BITS_TXDMA_VIQ_MAP (BIT_MASK_TXDMA_VIQ_MAP << BIT_SHIFT_TXDMA_VIQ_MAP) +#define BIT_CLEAR_TXDMA_VIQ_MAP(x) ((x) & (~BITS_TXDMA_VIQ_MAP)) +#define BIT_GET_TXDMA_VIQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP) +#define BIT_SET_TXDMA_VIQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP(x) | BIT_TXDMA_VIQ_MAP(v)) -/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_TXDMA_VOQ_MAP 4 +#define BIT_MASK_TXDMA_VOQ_MAP 0x3 +#define BIT_TXDMA_VOQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) +#define BITS_TXDMA_VOQ_MAP (BIT_MASK_TXDMA_VOQ_MAP << BIT_SHIFT_TXDMA_VOQ_MAP) +#define BIT_CLEAR_TXDMA_VOQ_MAP(x) ((x) & (~BITS_TXDMA_VOQ_MAP)) +#define BIT_GET_TXDMA_VOQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP) +#define BIT_SET_TXDMA_VOQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP(x) | BIT_TXDMA_VOQ_MAP(v)) + +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RXFF0_BNDY_V1 8 -#define BIT_MASK_RXFF0_BNDY_V1 0x3ffff -#define BIT_RXFF0_BNDY_V1(x) (((x) & BIT_MASK_RXFF0_BNDY_V1) << BIT_SHIFT_RXFF0_BNDY_V1) -#define BIT_GET_RXFF0_BNDY_V1(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V1) & BIT_MASK_RXFF0_BNDY_V1) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_VOQ_MAP_V1 4 +#define BIT_MASK_TXDMA_VOQ_MAP_V1 0x7 +#define BIT_TXDMA_VOQ_MAP_V1(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP_V1) << BIT_SHIFT_TXDMA_VOQ_MAP_V1) +#define BITS_TXDMA_VOQ_MAP_V1 \ + (BIT_MASK_TXDMA_VOQ_MAP_V1 << BIT_SHIFT_TXDMA_VOQ_MAP_V1) +#define BIT_CLEAR_TXDMA_VOQ_MAP_V1(x) ((x) & (~BITS_TXDMA_VOQ_MAP_V1)) +#define BIT_GET_TXDMA_VOQ_MAP_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_V1) & BIT_MASK_TXDMA_VOQ_MAP_V1) +#define BIT_SET_TXDMA_VOQ_MAP_V1(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP_V1(x) | BIT_TXDMA_VOQ_MAP_V1(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_TXDMA_BW_EN BIT(3) -/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TXPKTBUF_PGBNDY 0 -#define BIT_MASK_TXPKTBUF_PGBNDY 0xff -#define BIT_TXPKTBUF_PGBNDY(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY) << BIT_SHIFT_TXPKTBUF_PGBNDY) -#define BIT_GET_TXPKTBUF_PGBNDY(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY) & BIT_MASK_TXPKTBUF_PGBNDY) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_RXDMA_AGG_EN BIT(2) +#define BIT_RXSHFT_EN BIT(1) +#define BIT_RXDMA_ARBBW_EN BIT(0) #endif +#if (HALMAC_8814A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_RXFFOVFL_RSV_V1 28 +#define BIT_MASK_RXFFOVFL_RSV_V1 0xf +#define BIT_RXFFOVFL_RSV_V1(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V1) << BIT_SHIFT_RXFFOVFL_RSV_V1) +#define BITS_RXFFOVFL_RSV_V1 \ + (BIT_MASK_RXFFOVFL_RSV_V1 << BIT_SHIFT_RXFFOVFL_RSV_V1) +#define BIT_CLEAR_RXFFOVFL_RSV_V1(x) ((x) & (~BITS_RXFFOVFL_RSV_V1)) +#define BIT_GET_RXFFOVFL_RSV_V1(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V1) & BIT_MASK_RXFFOVFL_RSV_V1) +#define BIT_SET_RXFFOVFL_RSV_V1(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V1(x) | BIT_RXFFOVFL_RSV_V1(v)) -/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RXFF0_BNDY_V2 0 -#define BIT_MASK_RXFF0_BNDY_V2 0x3ffff -#define BIT_RXFF0_BNDY_V2(x) (((x) & BIT_MASK_RXFF0_BNDY_V2) << BIT_SHIFT_RXFF0_BNDY_V2) -#define BIT_GET_RXFF0_BNDY_V2(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2) & BIT_MASK_RXFF0_BNDY_V2) +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_RXFF0_BNDY 16 +#define BIT_MASK_RXFF0_BNDY 0xffff +#define BIT_RXFF0_BNDY(x) (((x) & BIT_MASK_RXFF0_BNDY) << BIT_SHIFT_RXFF0_BNDY) +#define BITS_RXFF0_BNDY (BIT_MASK_RXFF0_BNDY << BIT_SHIFT_RXFF0_BNDY) +#define BIT_CLEAR_RXFF0_BNDY(x) ((x) & (~BITS_RXFF0_BNDY)) +#define BIT_GET_RXFF0_BNDY(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY) & BIT_MASK_RXFF0_BNDY) +#define BIT_SET_RXFF0_BNDY(x, v) (BIT_CLEAR_RXFF0_BNDY(x) | BIT_RXFF0_BNDY(v)) -#define BIT_SHIFT_RXFF0_RDPTR_V2 0 -#define BIT_MASK_RXFF0_RDPTR_V2 0x3ffff -#define BIT_RXFF0_RDPTR_V2(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2) << BIT_SHIFT_RXFF0_RDPTR_V2) -#define BIT_GET_RXFF0_RDPTR_V2(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2) & BIT_MASK_RXFF0_RDPTR_V2) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXFF0_WTPTR_V2 0 -#define BIT_MASK_RXFF0_WTPTR_V2 0x3ffff -#define BIT_RXFF0_WTPTR_V2(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2) << BIT_SHIFT_RXFF0_WTPTR_V2) -#define BIT_GET_RXFF0_WTPTR_V2(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2) & BIT_MASK_RXFF0_WTPTR_V2) +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_FWFFOVFL_RSV 16 +#define BIT_MASK_FWFFOVFL_RSV 0xf +#define BIT_FWFFOVFL_RSV(x) \ + (((x) & BIT_MASK_FWFFOVFL_RSV) << BIT_SHIFT_FWFFOVFL_RSV) +#define BITS_FWFFOVFL_RSV (BIT_MASK_FWFFOVFL_RSV << BIT_SHIFT_FWFFOVFL_RSV) +#define BIT_CLEAR_FWFFOVFL_RSV(x) ((x) & (~BITS_FWFFOVFL_RSV)) +#define BIT_GET_FWFFOVFL_RSV(x) \ + (((x) >> BIT_SHIFT_FWFFOVFL_RSV) & BIT_MASK_FWFFOVFL_RSV) +#define BIT_SET_FWFFOVFL_RSV(x, v) \ + (BIT_CLEAR_FWFFOVFL_RSV(x) | BIT_FWFFOVFL_RSV(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_RXFFOVFL_RSV 8 +#define BIT_MASK_RXFFOVFL_RSV 0xf +#define BIT_RXFFOVFL_RSV(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV) << BIT_SHIFT_RXFFOVFL_RSV) +#define BITS_RXFFOVFL_RSV (BIT_MASK_RXFFOVFL_RSV << BIT_SHIFT_RXFFOVFL_RSV) +#define BIT_CLEAR_RXFFOVFL_RSV(x) ((x) & (~BITS_RXFFOVFL_RSV)) +#define BIT_GET_RXFFOVFL_RSV(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV) & BIT_MASK_RXFFOVFL_RSV) +#define BIT_SET_RXFFOVFL_RSV(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV(x) | BIT_RXFFOVFL_RSV(v)) -/* 2 REG_FF_STATUS (Offset 0x0118) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXFF0_RDPTR_V1 13 -#define BIT_MASK_RXFF0_RDPTR_V1 0x3ffff -#define BIT_RXFF0_RDPTR_V1(x) (((x) & BIT_MASK_RXFF0_RDPTR_V1) << BIT_SHIFT_RXFF0_RDPTR_V1) -#define BIT_GET_RXFF0_RDPTR_V1(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V1) & BIT_MASK_RXFF0_RDPTR_V1) +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_RXFFOVFL_RSV_V2 8 +#define BIT_MASK_RXFFOVFL_RSV_V2 0xf +#define BIT_RXFFOVFL_RSV_V2(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2) +#define BITS_RXFFOVFL_RSV_V2 \ + (BIT_MASK_RXFFOVFL_RSV_V2 << BIT_SHIFT_RXFFOVFL_RSV_V2) +#define BIT_CLEAR_RXFFOVFL_RSV_V2(x) ((x) & (~BITS_RXFFOVFL_RSV_V2)) +#define BIT_GET_RXFFOVFL_RSV_V2(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2) & BIT_MASK_RXFFOVFL_RSV_V2) +#define BIT_SET_RXFFOVFL_RSV_V2(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V2(x) | BIT_RXFFOVFL_RSV_V2(v)) #endif +#if (HALMAC_8814A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_RXFF0_BNDY_V1 8 +#define BIT_MASK_RXFF0_BNDY_V1 0x3ffff +#define BIT_RXFF0_BNDY_V1(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V1) << BIT_SHIFT_RXFF0_BNDY_V1) +#define BITS_RXFF0_BNDY_V1 (BIT_MASK_RXFF0_BNDY_V1 << BIT_SHIFT_RXFF0_BNDY_V1) +#define BIT_CLEAR_RXFF0_BNDY_V1(x) ((x) & (~BITS_RXFF0_BNDY_V1)) +#define BIT_GET_RXFF0_BNDY_V1(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V1) & BIT_MASK_RXFF0_BNDY_V1) +#define BIT_SET_RXFF0_BNDY_V1(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V1(x) | BIT_RXFF0_BNDY_V1(v)) -/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_I2C_M_STATUS 8 -#define BIT_MASK_I2C_M_STATUS 0xf -#define BIT_I2C_M_STATUS(x) (((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS) -#define BIT_GET_I2C_M_STATUS(x) (((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS) +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_TXPKTBUF_PGBNDY 0 +#define BIT_MASK_TXPKTBUF_PGBNDY 0xff +#define BIT_TXPKTBUF_PGBNDY(x) \ + (((x) & BIT_MASK_TXPKTBUF_PGBNDY) << BIT_SHIFT_TXPKTBUF_PGBNDY) +#define BITS_TXPKTBUF_PGBNDY \ + (BIT_MASK_TXPKTBUF_PGBNDY << BIT_SHIFT_TXPKTBUF_PGBNDY) +#define BIT_CLEAR_TXPKTBUF_PGBNDY(x) ((x) & (~BITS_TXPKTBUF_PGBNDY)) +#define BIT_GET_TXPKTBUF_PGBNDY(x) \ + (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY) & BIT_MASK_TXPKTBUF_PGBNDY) +#define BIT_SET_TXPKTBUF_PGBNDY(x, v) \ + (BIT_CLEAR_TXPKTBUF_PGBNDY(x) | BIT_TXPKTBUF_PGBNDY(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_RXFF0_BNDY_V2 0 +#define BIT_MASK_RXFF0_BNDY_V2 0x3ffff +#define BIT_RXFF0_BNDY_V2(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V2) << BIT_SHIFT_RXFF0_BNDY_V2) +#define BITS_RXFF0_BNDY_V2 (BIT_MASK_RXFF0_BNDY_V2 << BIT_SHIFT_RXFF0_BNDY_V2) +#define BIT_CLEAR_RXFF0_BNDY_V2(x) ((x) & (~BITS_RXFF0_BNDY_V2)) +#define BIT_GET_RXFF0_BNDY_V2(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V2) & BIT_MASK_RXFF0_BNDY_V2) +#define BIT_SET_RXFF0_BNDY_V2(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V2(x) | BIT_RXFF0_BNDY_V2(v)) + +#define BIT_SHIFT_RXFF0_RDPTR_V2 0 +#define BIT_MASK_RXFF0_RDPTR_V2 0x3ffff +#define BIT_RXFF0_RDPTR_V2(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V2) << BIT_SHIFT_RXFF0_RDPTR_V2) +#define BITS_RXFF0_RDPTR_V2 \ + (BIT_MASK_RXFF0_RDPTR_V2 << BIT_SHIFT_RXFF0_RDPTR_V2) +#define BIT_CLEAR_RXFF0_RDPTR_V2(x) ((x) & (~BITS_RXFF0_RDPTR_V2)) +#define BIT_GET_RXFF0_RDPTR_V2(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2) & BIT_MASK_RXFF0_RDPTR_V2) +#define BIT_SET_RXFF0_RDPTR_V2(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V2(x) | BIT_RXFF0_RDPTR_V2(v)) + +#define BIT_SHIFT_RXFF0_WTPTR_V2 0 +#define BIT_MASK_RXFF0_WTPTR_V2 0x3ffff +#define BIT_RXFF0_WTPTR_V2(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V2) << BIT_SHIFT_RXFF0_WTPTR_V2) +#define BITS_RXFF0_WTPTR_V2 \ + (BIT_MASK_RXFF0_WTPTR_V2 << BIT_SHIFT_RXFF0_WTPTR_V2) +#define BIT_CLEAR_RXFF0_WTPTR_V2(x) ((x) & (~BITS_RXFF0_WTPTR_V2)) +#define BIT_GET_RXFF0_WTPTR_V2(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2) & BIT_MASK_RXFF0_WTPTR_V2) +#define BIT_SET_RXFF0_WTPTR_V2(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V2(x) | BIT_RXFF0_WTPTR_V2(v)) -#define BIT_SHIFT_I2C_M_BUS_GNT 4 -#define BIT_MASK_I2C_M_BUS_GNT 0x7 -#define BIT_I2C_M_BUS_GNT(x) (((x) & BIT_MASK_I2C_M_BUS_GNT) << BIT_SHIFT_I2C_M_BUS_GNT) -#define BIT_GET_I2C_M_BUS_GNT(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT) & BIT_MASK_I2C_M_BUS_GNT) +#endif -#define BIT_I2C_GNT_FW BIT(3) +#if (HALMAC_8814A_SUPPORT) -#define BIT_SHIFT_I2C_DATA_RATE 1 -#define BIT_MASK_I2C_DATA_RATE 0x3 -#define BIT_I2C_DATA_RATE(x) (((x) & BIT_MASK_I2C_DATA_RATE) << BIT_SHIFT_I2C_DATA_RATE) -#define BIT_GET_I2C_DATA_RATE(x) (((x) >> BIT_SHIFT_I2C_DATA_RATE) & BIT_MASK_I2C_DATA_RATE) +/* 2 REG_FF_STATUS (Offset 0x0118) */ -#define BIT_I2C_SW_CONTROL_UNLOCK BIT(0) +#define BIT_SHIFT_RXFF0_RDPTR_V1 13 +#define BIT_MASK_RXFF0_RDPTR_V1 0x3ffff +#define BIT_RXFF0_RDPTR_V1(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V1) << BIT_SHIFT_RXFF0_RDPTR_V1) +#define BITS_RXFF0_RDPTR_V1 \ + (BIT_MASK_RXFF0_RDPTR_V1 << BIT_SHIFT_RXFF0_RDPTR_V1) +#define BIT_CLEAR_RXFF0_RDPTR_V1(x) ((x) & (~BITS_RXFF0_RDPTR_V1)) +#define BIT_GET_RXFF0_RDPTR_V1(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V1) & BIT_MASK_RXFF0_RDPTR_V1) +#define BIT_SET_RXFF0_RDPTR_V1(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V1(x) | BIT_RXFF0_RDPTR_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ +#define BIT_SHIFT_I2C_M_STATUS 8 +#define BIT_MASK_I2C_M_STATUS 0xf +#define BIT_I2C_M_STATUS(x) \ + (((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS) +#define BITS_I2C_M_STATUS (BIT_MASK_I2C_M_STATUS << BIT_SHIFT_I2C_M_STATUS) +#define BIT_CLEAR_I2C_M_STATUS(x) ((x) & (~BITS_I2C_M_STATUS)) +#define BIT_GET_I2C_M_STATUS(x) \ + (((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS) +#define BIT_SET_I2C_M_STATUS(x, v) \ + (BIT_CLEAR_I2C_M_STATUS(x) | BIT_I2C_M_STATUS(v)) -/* 2 REG_FF_STATUS (Offset 0x0118) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RXFF0_WTPTR_V1 0 -#define BIT_MASK_RXFF0_WTPTR_V1 0x3ffff -#define BIT_RXFF0_WTPTR_V1(x) (((x) & BIT_MASK_RXFF0_WTPTR_V1) << BIT_SHIFT_RXFF0_WTPTR_V1) -#define BIT_GET_RXFF0_WTPTR_V1(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V1) & BIT_MASK_RXFF0_WTPTR_V1) +/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ +#define BIT_SHIFT_I2C_M_BUS_GNT 4 +#define BIT_MASK_I2C_M_BUS_GNT 0x7 +#define BIT_I2C_M_BUS_GNT(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT) << BIT_SHIFT_I2C_M_BUS_GNT) +#define BITS_I2C_M_BUS_GNT (BIT_MASK_I2C_M_BUS_GNT << BIT_SHIFT_I2C_M_BUS_GNT) +#define BIT_CLEAR_I2C_M_BUS_GNT(x) ((x) & (~BITS_I2C_M_BUS_GNT)) +#define BIT_GET_I2C_M_BUS_GNT(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT) & BIT_MASK_I2C_M_BUS_GNT) +#define BIT_SET_I2C_M_BUS_GNT(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT(x) | BIT_I2C_M_BUS_GNT(v)) -#endif +#define BIT_I2C_GNT_FW BIT(3) +#define BIT_SHIFT_I2C_DATA_RATE 1 +#define BIT_MASK_I2C_DATA_RATE 0x3 +#define BIT_I2C_DATA_RATE(x) \ + (((x) & BIT_MASK_I2C_DATA_RATE) << BIT_SHIFT_I2C_DATA_RATE) +#define BITS_I2C_DATA_RATE (BIT_MASK_I2C_DATA_RATE << BIT_SHIFT_I2C_DATA_RATE) +#define BIT_CLEAR_I2C_DATA_RATE(x) ((x) & (~BITS_I2C_DATA_RATE)) +#define BIT_GET_I2C_DATA_RATE(x) \ + (((x) >> BIT_SHIFT_I2C_DATA_RATE) & BIT_MASK_I2C_DATA_RATE) +#define BIT_SET_I2C_DATA_RATE(x, v) \ + (BIT_CLEAR_I2C_DATA_RATE(x) | BIT_I2C_DATA_RATE(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_I2C_SW_CONTROL_UNLOCK BIT(0) +#endif -/* 2 REG_RXFF_PTR (Offset 0x011C) */ +#if (HALMAC_8814A_SUPPORT) +/* 2 REG_FF_STATUS (Offset 0x0118) */ -#define BIT_SHIFT_RXFF0_RDPTR 16 -#define BIT_MASK_RXFF0_RDPTR 0xffff -#define BIT_RXFF0_RDPTR(x) (((x) & BIT_MASK_RXFF0_RDPTR) << BIT_SHIFT_RXFF0_RDPTR) -#define BIT_GET_RXFF0_RDPTR(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR) & BIT_MASK_RXFF0_RDPTR) +#define BIT_SHIFT_RXFF0_WTPTR_V1 0 +#define BIT_MASK_RXFF0_WTPTR_V1 0x3ffff +#define BIT_RXFF0_WTPTR_V1(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V1) << BIT_SHIFT_RXFF0_WTPTR_V1) +#define BITS_RXFF0_WTPTR_V1 \ + (BIT_MASK_RXFF0_WTPTR_V1 << BIT_SHIFT_RXFF0_WTPTR_V1) +#define BIT_CLEAR_RXFF0_WTPTR_V1(x) ((x) & (~BITS_RXFF0_WTPTR_V1)) +#define BIT_GET_RXFF0_WTPTR_V1(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V1) & BIT_MASK_RXFF0_WTPTR_V1) +#define BIT_SET_RXFF0_WTPTR_V1(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V1(x) | BIT_RXFF0_WTPTR_V1(v)) +#endif -#define BIT_SHIFT_RXFF0_WTPTR 0 -#define BIT_MASK_RXFF0_WTPTR 0xffff -#define BIT_RXFF0_WTPTR(x) (((x) & BIT_MASK_RXFF0_WTPTR) << BIT_SHIFT_RXFF0_WTPTR) -#define BIT_GET_RXFF0_WTPTR(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR) & BIT_MASK_RXFF0_WTPTR) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXFF_PTR (Offset 0x011C) */ -#endif +#define BIT_SHIFT_RXFF0_RDPTR 16 +#define BIT_MASK_RXFF0_RDPTR 0xffff +#define BIT_RXFF0_RDPTR(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR) << BIT_SHIFT_RXFF0_RDPTR) +#define BITS_RXFF0_RDPTR (BIT_MASK_RXFF0_RDPTR << BIT_SHIFT_RXFF0_RDPTR) +#define BIT_CLEAR_RXFF0_RDPTR(x) ((x) & (~BITS_RXFF0_RDPTR)) +#define BIT_GET_RXFF0_RDPTR(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR) & BIT_MASK_RXFF0_RDPTR) +#define BIT_SET_RXFF0_RDPTR(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR(x) | BIT_RXFF0_RDPTR(v)) +#define BIT_SHIFT_RXFF0_WTPTR 0 +#define BIT_MASK_RXFF0_WTPTR 0xffff +#define BIT_RXFF0_WTPTR(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR) << BIT_SHIFT_RXFF0_WTPTR) +#define BITS_RXFF0_WTPTR (BIT_MASK_RXFF0_WTPTR << BIT_SHIFT_RXFF0_WTPTR) +#define BIT_CLEAR_RXFF0_WTPTR(x) ((x) & (~BITS_RXFF0_WTPTR)) +#define BIT_GET_RXFF0_WTPTR(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR) & BIT_MASK_RXFF0_WTPTR) +#define BIT_SET_RXFF0_WTPTR(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR(x) | BIT_RXFF0_WTPTR(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_BB_STOP_RX_INT_EN BIT(29) +#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_EN BIT(31) #endif +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_FE1IMR (Offset 0x0120) */ + +#define BIT_FS_SW_PLL_LEAVE_32K_INT_EN BIT(31) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_FS_RXDMA2_DONE_INT_EN BIT(28) -#define BIT_FS_RXDONE3_INT_EN BIT(27) -#define BIT_FS_RXDONE2_INT_EN BIT(26) -#define BIT_FS_RX_BCN_P4_INT_EN BIT(25) -#define BIT_FS_RX_BCN_P3_INT_EN BIT(24) -#define BIT_FS_RX_BCN_P2_INT_EN BIT(23) -#define BIT_FS_RX_BCN_P1_INT_EN BIT(22) -#define BIT_FS_RX_BCN_P0_INT_EN BIT(21) -#define BIT_FS_RX_UMD0_INT_EN BIT(20) -#define BIT_FS_RX_UMD1_INT_EN BIT(19) -#define BIT_FS_RX_BMD0_INT_EN BIT(18) -#define BIT_FS_RX_BMD1_INT_EN BIT(17) -#define BIT_FS_RXDONE_INT_EN BIT(16) -#define BIT_FS_WWLAN_INT_EN BIT(15) -#define BIT_FS_SOUND_DONE_INT_EN BIT(14) -#define BIT_FS_LP_STBY_INT_EN BIT(13) -#define BIT_FS_TRL_MTR_INT_EN BIT(12) -#define BIT_FS_BF1_PRETO_INT_EN BIT(11) -#define BIT_FS_BF0_PRETO_INT_EN BIT(10) -#define BIT_FS_PTCL_RELEASE_MACID_INT_EN BIT(9) +#define BIT_FWFF_FULL_INT_EN BIT(30) #endif +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_FE1IMR (Offset 0x0120) */ + +#define BIT_FS_FWFF_FULL_INT_EN BIT(30) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_FS_LTE_COEX_EN BIT(6) +#define BIT_BB_STOP_RX_INT_EN BIT(29) #endif +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_FE1IMR (Offset 0x0120) */ + +#define BIT_FS_BB_STOP_RX_INT_EN BIT(29) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_FS_WLACTOFF_INT_EN BIT(5) -#define BIT_FS_WLACTON_INT_EN BIT(4) -#define BIT_FS_BTCMD_INT_EN BIT(3) +#define BIT_FS_RXDMA2_DONE_INT_EN BIT(28) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_RXDONE3_INT_EN BIT(27) -/* 2 REG_FEIMR (Offset 0x0120) */ +#endif -#define BIT_REG_MAILBOX_TO_I2C_INT BIT(2) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_RXDONE2_INT_EN BIT(26) +#define BIT_FS_RX_BCN_P4_INT_EN BIT(25) +#define BIT_FS_RX_BCN_P3_INT_EN BIT(24) +#define BIT_FS_RX_BCN_P2_INT_EN BIT(23) +#define BIT_FS_RX_BCN_P1_INT_EN BIT(22) +#define BIT_FS_RX_BCN_P0_INT_EN BIT(21) +#define BIT_FS_RX_UMD0_INT_EN BIT(20) +#define BIT_FS_RX_UMD1_INT_EN BIT(19) +#define BIT_FS_RX_BMD0_INT_EN BIT(18) +#define BIT_FS_RX_BMD1_INT_EN BIT(17) +#define BIT_FS_RXDONE_INT_EN BIT(16) +#define BIT_FS_WWLAN_INT_EN BIT(15) +#define BIT_FS_SOUND_DONE_INT_EN BIT(14) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN BIT(2) +#define BIT_FS_LP_STBY_INT_EN BIT(13) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_TRL_MTR_INT_EN BIT(12) -/* 2 REG_FEIMR (Offset 0x0120) */ +#endif -#define BIT_TRPC_TO_INT_EN BIT(1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_BF1_PRETO_INT_EN BIT(11) +#define BIT_FS_BF0_PRETO_INT_EN BIT(10) +#define BIT_FS_PTCL_RELEASE_MACID_INT_EN BIT(9) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_FS_TRPC_TO_INT_EN_V1 BIT(1) +#define BIT_PRETXERR_HANDLE_FSIMR BIT(8) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_PRETX_ERRHLD_INT_EN BIT(8) -/* 2 REG_FEIMR (Offset 0x0120) */ +#endif -#define BIT_BIT_RPC_O_T_INT_EN BIT(0) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_PRETX_ERRHLD_INT_EN BIT(8) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_FS_RPC_O_T_INT_EN_V1 BIT(0) +#define BIT_FS_GTRD_INT_EN BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_LTE_COEX_EN BIT(6) -/* 2 REG_FE1ISR (Offset 0x0124) */ +#endif -#define BIT_BB_STOP_RX_INT BIT(29) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_WLACTOFF_INT_EN BIT(5) +#define BIT_FS_WLACTON_INT_EN BIT(4) +#define BIT_FS_BTCMD_INT_EN BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT) -/* 2 REG_FE1ISR (Offset 0x0124) */ +/* 2 REG_FEIMR (Offset 0x0120) */ -#define BIT_FS_RXDMA2_DONE_INT BIT(28) -#define BIT_FS_RXDONE3_INT BIT(27) -#define BIT_FS_RXDONE2_INT BIT(26) -#define BIT_FS_RX_BCN_P4_INT BIT(25) -#define BIT_FS_RX_BCN_P3_INT BIT(24) -#define BIT_FS_RX_BCN_P2_INT BIT(23) -#define BIT_FS_RX_BCN_P1_INT BIT(22) -#define BIT_FS_RX_BCN_P0_INT BIT(21) -#define BIT_FS_RX_UMD0_INT BIT(20) -#define BIT_FS_RX_UMD1_INT BIT(19) -#define BIT_FS_RX_BMD0_INT BIT(18) -#define BIT_FS_RX_BMD1_INT BIT(17) -#define BIT_FS_RXDONE_INT BIT(16) -#define BIT_FS_WWLAN_INT BIT(15) -#define BIT_FS_SOUND_DONE_INT BIT(14) -#define BIT_FS_LP_STBY_INT BIT(13) -#define BIT_FS_TRL_MTR_INT BIT(12) -#define BIT_FS_BF1_PRETO_INT BIT(11) -#define BIT_FS_BF0_PRETO_INT BIT(10) -#define BIT_FS_PTCL_RELEASE_MACID_INT BIT(9) +#define BIT_REG_MAILBOX_TO_I2C_INT BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN BIT(2) -/* 2 REG_FE1ISR (Offset 0x0124) */ +#endif -#define BIT_FS_LTE_COEX_INT BIT(6) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_TRPC_TO_INT_EN BIT(1) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE1ISR (Offset 0x0124) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_FS_WLACTOFF_INT BIT(5) -#define BIT_FS_WLACTON_INT BIT(4) -#define BIT_FS_BCN_RX_INT_INT BIT(3) +#define BIT_FS_TRPC_TO_INT_EN_V1 BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_BIT_RPC_O_T_INT_EN BIT(0) -/* 2 REG_FEISR (Offset 0x0124) */ +#endif -#define BIT_MAILBOX_TO_I2C BIT(2) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_RPC_O_T_INT_EN_V1 BIT(0) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_FS_MAILBOX_TO_I2C_INT BIT(2) +#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT BIT(31) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_SW_PLL_LEAVE_32K_INT BIT(31) -/* 2 REG_FEISR (Offset 0x0124) */ +#endif -#define BIT_TRPC_TO_INT BIT(1) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FWFF_FULL_INT BIT(30) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_FS_TRPC_TO_INT BIT(1) +#define BIT_FS_FS_FWFF_FULL_INT BIT(30) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_BB_STOP_RX_INT BIT(29) -/* 2 REG_FEISR (Offset 0x0124) */ +#endif -#define BIT_RPC_O_T_INT BIT(0) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_BB_STOP_RX_INT BIT(29) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_FS_RPC_O_T_INT BIT(0) +#define BIT_FS_RXDMA2_DONE_INT BIT(28) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_RXDONE3_INT BIT(27) -/* 2 REG_CPWM (Offset 0x012C) */ +#endif -#define BIT_CPWM_TOGGLING BIT(31) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_CPWM_MOD 24 -#define BIT_MASK_CPWM_MOD 0x7f -#define BIT_CPWM_MOD(x) (((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD) -#define BIT_GET_CPWM_MOD(x) (((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_RXDONE3_INT_INT BIT(27) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_RXDONE2_INT BIT(26) +#define BIT_FS_RX_BCN_P4_INT BIT(25) +#define BIT_FS_RX_BCN_P3_INT BIT(24) +#define BIT_FS_RX_BCN_P2_INT BIT(23) +#define BIT_FS_RX_BCN_P1_INT BIT(22) +#define BIT_FS_RX_BCN_P0_INT BIT(21) +#define BIT_FS_RX_UMD0_INT BIT(20) +#define BIT_FS_RX_UMD1_INT BIT(19) +#define BIT_FS_RX_BMD0_INT BIT(18) +#define BIT_FS_RX_BMD1_INT BIT(17) +#define BIT_FS_RXDONE_INT BIT(16) +#define BIT_FS_WWLAN_INT BIT(15) +#define BIT_FS_SOUND_DONE_INT BIT(14) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB7_INT_EN BIT(31) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_LP_STBY_INT BIT(13) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_SOUND_DONE_MSK BIT(30) +#define BIT_FS_TRL_MTR_INT BIT(12) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_BF1_PRETO_INT BIT(11) +#define BIT_FS_BF0_PRETO_INT BIT(10) +#define BIT_FS_PTCL_RELEASE_MACID_INT BIT(9) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB6_INT_EN BIT(30) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_PRETXERR_HANDLE_FSISR BIT(8) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_TRY_DONE_MSK BIT(29) +#define BIT_PRETX_ERRHLD_INT BIT(8) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_PRETX_ERRHLD_INT BIT(8) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB5_INT_EN BIT(29) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_SND_RDY_INT BIT(7) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_TXRPT_CNT_FULL_MSK BIT(28) +#define BIT_FS_LTE_COEX_INT BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_WLACTOFF_INT BIT(5) +#define BIT_FS_WLACTON_INT BIT(4) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB4_INT_EN BIT(28) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_BCN_RX_INT_INT BIT(3) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_WLACTOFF_INT_EN BIT(27) +#define BIT_BT_CMD_INT BIT(3) #endif +#if (HALMAC_8192E_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_MAILBOX_TO_I2C BIT(2) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB3_INT_EN BIT(27) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_MAILBOX_TO_I2C_INT BIT(2) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_WLACTON_INT_EN BIT(26) +#define BIT_TRPC_TO_INT BIT(1) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_TRPC_TO_INT BIT(1) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB2_INT_EN BIT(26) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_RPC_O_T_INT BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_TXPKTIN_INT_EN BIT(25) +#define BIT_FS_RPC_O_T_INT BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_CPWM (Offset 0x012C) */ + +#define BIT_CPWM_TOGGLING BIT(31) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_CPWM_MOD 24 +#define BIT_MASK_CPWM_MOD 0x7f +#define BIT_CPWM_MOD(x) (((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD) +#define BITS_CPWM_MOD (BIT_MASK_CPWM_MOD << BIT_SHIFT_CPWM_MOD) +#define BIT_CLEAR_CPWM_MOD(x) ((x) & (~BITS_CPWM_MOD)) +#define BIT_GET_CPWM_MOD(x) (((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD) +#define BIT_SET_CPWM_MOD(x, v) (BIT_CLEAR_CPWM_MOD(x) | BIT_CPWM_MOD(v)) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXBCNOK_MB1_INT_EN BIT(25) +#define BIT_FS_TXBCNOK_MB7_INT_EN BIT(31) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_TXBCNOK_MSK BIT(24) +#define BIT_SOUND_DONE_MSK BIT(30) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXBCNOK_MB0_INT_EN BIT(24) +#define BIT_FS_TXBCNOK_MB6_INT_EN BIT(30) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_TXBCNERR_MSK BIT(23) +#define BIT_TRY_DONE_MSK BIT(29) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXBCNERR_MB7_INT_EN BIT(23) +#define BIT_FS_TXBCNOK_MB5_INT_EN BIT(29) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_RX_UMD0_EN BIT(22) +#define BIT_TXRPT_CNT_FULL_MSK BIT(28) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXBCNERR_MB6_INT_EN BIT(22) +#define BIT_FS_TXBCNOK_MB4_INT_EN BIT(28) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_RX_UMD1_EN BIT(21) +#define BIT_WLACTOFF_INT_EN BIT(27) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXBCNERR_MB5_INT_EN BIT(21) +#define BIT_FS_TXBCNOK_MB3_INT_EN BIT(27) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_RX_BMD0_EN BIT(20) +#define BIT_WLACTON_INT_EN BIT(26) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXBCNERR_MB4_INT_EN BIT(20) +#define BIT_FS_TXBCNOK_MB2_INT_EN BIT(26) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_RX_BMD1_EN BIT(19) +#define BIT_TXPKTIN_INT_EN BIT(25) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXBCNERR_MB3_INT_EN BIT(19) +#define BIT_FS_TXBCNOK_MB1_INT_EN BIT(25) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCN_RX_INT_EN BIT(18) +#define BIT_TXBCNOK_MSK BIT(24) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXBCNERR_MB2_INT_EN BIT(18) +#define BIT_FS_TXBCNOK_MB0_INT_EN BIT(24) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_TBTTINT_MSK BIT(17) +#define BIT_TXBCNERR_MSK BIT(23) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXBCNERR_MB1_INT_EN BIT(17) +#define BIT_FS_TXBCNERR_MB7_INT_EN BIT(23) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNERLY_MSK BIT(16) +#define BIT_RX_UMD0_EN BIT(22) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXBCNERR_MB0_INT_EN BIT(16) +#define BIT_FS_TXBCNERR_MB6_INT_EN BIT(22) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNDMA7_MSK BIT(15) +#define BIT_RX_UMD1_EN BIT(21) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN BIT(15) +#define BIT_FS_TXBCNERR_MB5_INT_EN BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_FWIMR (Offset 0x0130) */ + +#define BIT_RX_BMD0_EN BIT(20) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_CPU_MGQ_TXDONE_INT_EN BIT(15) +#define BIT_FS_TXBCNERR_MB4_INT_EN BIT(20) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNDMA6_MSK BIT(14) +#define BIT_RX_BMD1_EN BIT(19) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_SIFS_OVERSPEC_INT_EN BIT(14) +#define BIT_FS_TXBCNERR_MB3_INT_EN BIT(19) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNDMA5_MSK BIT(13) +#define BIT_BCN_RX_INT_EN BIT(18) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN BIT(13) +#define BIT_FS_TXBCNERR_MB2_INT_EN BIT(18) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNDMA4_MSK BIT(12) +#define BIT_TBTTINT_MSK BIT(17) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_MGNTQFF_TO_INT_EN BIT(12) +#define BIT_FS_TXBCNERR_MB1_INT_EN BIT(17) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNDMA3_MSK BIT(11) +#define BIT_BCNERLY_MSK BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ + +#define BIT_FS_TXBCNERR_MB0_INT_EN BIT(16) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN BIT(11) +#define BIT_BCNDMA7_MSK BIT(15) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FWIMR (Offset 0x0130) */ + +#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN BIT(15) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_DDMA1_LP_INT_EN BIT(11) +#define BIT_CPU_MGQ_TXDONE_INT_EN BIT(15) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNDMA2_MSK BIT(10) +#define BIT_BCNDMA6_MSK BIT(14) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_DDMA1_HP_INT_EN BIT(10) +#define BIT_SIFS_OVERSPEC_INT_EN BIT(14) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNDMA1_MSK BIT(9) +#define BIT_BCNDMA5_MSK BIT(13) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_DDMA0_LP_INT_EN BIT(9) +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN BIT(13) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNDMA0_MSK BIT(8) +#define BIT_BCNDMA4_MSK BIT(12) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_DDMA0_HP_INT_EN BIT(8) +#define BIT_FS_MGNTQFF_TO_INT_EN BIT(12) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_LP_STBY_MSK BIT(7) +#define BIT_BCNDMA3_MSK BIT(11) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TRXRPT_INT_EN BIT(7) +#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN BIT(11) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ + +#define BIT_FS_CPUMGQ_ERR_INT_EN BIT(11) + +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_CTWENDINT_MSK BIT(6) +#define BIT_FS_DDMA1_LP_INT_EN BIT(11) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_FWIMR (Offset 0x0130) */ + +#define BIT_BCNDMA2_MSK BIT(10) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_C2H_W_READY_INT_EN BIT(6) +#define BIT_FS_DDMA1_HP_INT_EN BIT(10) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_HRCV_MSK BIT(5) +#define BIT_BCNDMA1_MSK BIT(9) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_HRCV_INT_EN BIT(5) +#define BIT_FS_DDMA0_LP_INT_EN BIT(9) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_H2CCMD_MSK BIT(4) +#define BIT_BCNDMA0_MSK BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_H2CCMD_INT_EN BIT(4) +#define BIT_FS_DDMA0_HP_INT_EN BIT(8) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_RXDONE_MSK BIT(3) +#define BIT_LP_STBY_MSK BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXPKTIN_INT_EN BIT(3) +#define BIT_FS_TRXRPT_INT_EN BIT(7) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_ERRORHDL_MSK BIT(2) +#define BIT_CTWENDINT_MSK BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FWIMR (Offset 0x0130) */ + +#define BIT_FS_C2H_W_READY_INT_EN BIT(6) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_ERRORHDL_INT_EN BIT(2) +#define BIT_HRCV_MSK BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ + +#define BIT_FS_HRCV_INT_EN BIT(5) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_TXCCX_MSK_FW BIT(1) +#define BIT_H2CCMD_MSK BIT(4) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FWIMR (Offset 0x0130) */ + +#define BIT_FS_H2CCMD_INT_EN BIT(4) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXCCX_INT_EN BIT(1) +#define BIT_RXDONE_MSK BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ + +#define BIT_FS_TXPKTIN_INT_EN BIT(3) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_TXCLOSE_MSK BIT(0) +#define BIT_ERRORHDL_MSK BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_ERRORHDL_INT_EN BIT(2) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXCLOSE_INT_EN BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_TXBCNOK_MB7_INT BIT(31) +#define BIT_TXCCX_MSK_FW BIT(1) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXCCX_INT_EN BIT(1) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_SOUND_DONE_INT BIT(30) +#define BIT_TXCLOSE_MSK BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXCLOSE_INT_EN BIT(0) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNOK_MB6_INT BIT(30) +#define BIT_FS_TXBCNOK_MB7_INT BIT(31) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_TRY_DONE_INT BIT(29) +#define BIT_SOUND_DONE_INT BIT(30) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNOK_MB5_INT BIT(29) +#define BIT_FS_TXBCNOK_MB6_INT BIT(30) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_TXRPT_CNT_FULL_INT BIT(28) +#define BIT_TRY_DONE_INT BIT(29) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNOK_MB4_INT BIT(28) +#define BIT_FS_TXBCNOK_MB5_INT BIT(29) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_WLACTOFF_INT BIT(27) +#define BIT_TXRPT_CNT_FULL_INT BIT(28) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNOK_MB3_INT BIT(27) +#define BIT_FS_TXBCNOK_MB4_INT BIT(28) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_WLACTON_INT BIT(26) +#define BIT_WLACTOFF_INT BIT(27) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNOK_MB2_INT BIT(26) +#define BIT_FS_TXBCNOK_MB3_INT BIT(27) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_TXPKTIN_INT BIT(25) +#define BIT_WLACTON_INT BIT(26) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNOK_MB1_INT BIT(25) +#define BIT_FS_TXBCNOK_MB2_INT BIT(26) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_TXBCNOK_INT BIT(24) +#define BIT_TXPKTIN_INT BIT(25) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNOK_MB0_INT BIT(24) +#define BIT_FS_TXBCNOK_MB1_INT BIT(25) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_TXBCNERR_INT BIT(23) +#define BIT_TXBCNOK_INT BIT(24) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNERR_MB7_INT BIT(23) +#define BIT_FS_TXBCNOK_MB0_INT BIT(24) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_RX_UMD0_INT BIT(22) +#define BIT_TXBCNERR_INT BIT(23) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNERR_MB6_INT BIT(22) +#define BIT_FS_TXBCNERR_MB7_INT BIT(23) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_RX_UMD1_INT BIT(21) +#define BIT_RX_UMD0_INT BIT(22) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNERR_MB5_INT BIT(21) +#define BIT_FS_TXBCNERR_MB6_INT BIT(22) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_RX_BMD0_INT BIT(20) +#define BIT_RX_UMD1_INT BIT(21) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNERR_MB4_INT BIT(20) +#define BIT_FS_TXBCNERR_MB5_INT BIT(21) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_RX_BMD1_INT BIT(19) +#define BIT_RX_BMD0_INT BIT(20) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNERR_MB3_INT BIT(19) +#define BIT_FS_TXBCNERR_MB4_INT BIT(20) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_BCN_RX_INT_INT BIT(18) +#define BIT_RX_BMD1_INT BIT(19) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNERR_MB2_INT BIT(18) +#define BIT_FS_TXBCNERR_MB3_INT BIT(19) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_TBTTINT_INT BIT(17) +#define BIT_BCN_RX_INT_INT BIT(18) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNERR_MB1_INT BIT(17) +#define BIT_FS_TXBCNERR_MB2_INT BIT(18) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_BCNERLY_INT BIT(16) +#define BIT_TBTTINT_INT BIT(17) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXBCNERR_MB0_INT BIT(16) +#define BIT_FS_TXBCNERR_MB1_INT BIT(17) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_BCNDMA7_INT BIT(15) +#define BIT_BCNERLY_INT BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXBCNERR_MB0_INT BIT(16) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_CPUMGN_POLLED_PKT_DONE_INT BIT(15) +#define BIT_BCNDMA7_INT BIT(15) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ + +#define BIT_CPUMGN_POLLED_PKT_DONE_INT BIT(15) + +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_CPU_MGQ_TXDONE_INT BIT(15) +#define BIT_CPU_MGQ_TXDONE_INT BIT(15) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_BCNDMA6_INT BIT(14) +#define BIT_BCNDMA6_INT BIT(14) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_SIFS_OVERSPEC_INT BIT(14) +#define BIT_SIFS_OVERSPEC_INT BIT(14) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_BCNDMA5_INT BIT(13) +#define BIT_BCNDMA5_INT BIT(13) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_MGNTQ_RPTR_RELEASE_INT BIT(13) +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT BIT(13) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_BCNDMA4_INT BIT(12) +#define BIT_BCNDMA4_INT BIT(12) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_MGNTQFF_TO_INT BIT(12) +#define BIT_FS_MGNTQFF_TO_INT BIT(12) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_BCNDMA3_INT BIT(11) +#define BIT_BCNDMA3_INT BIT(11) #endif - #if (HALMAC_8197F_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT BIT(11) +#define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT BIT(11) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FWISR (Offset 0x0134) */ + +#define BIT_FS_CPUMGQ_ERR_INT BIT(11) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_DDMA1_LP_INT BIT(11) +#define BIT_FS_DDMA1_LP_INT BIT(11) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_BCNDMA2_INT BIT(10) +#define BIT_BCNDMA2_INT BIT(10) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ + +#define BIT_FS_DDMA1_HP_INT BIT(10) + +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_DDMA1_HP_INT BIT(10) +#define BIT_FWCMD_PKTIN_INT BIT(10) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_BCNDMA1_INT BIT(9) +#define BIT_BCNDMA1_INT BIT(9) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_DDMA0_LP_INT BIT(9) +#define BIT_FS_DDMA0_LP_INT BIT(9) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_BCNDMA0_INT BIT(8) +#define BIT_BCNDMA0_INT BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_DDMA0_HP_INT BIT(8) +#define BIT_FS_DDMA0_HP_INT BIT(8) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_LP_STBY_INT BIT(7) +#define BIT_LP_STBY_INT BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TRXRPT_INT BIT(7) +#define BIT_FS_TRXRPT_INT BIT(7) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_CTWENDINT_INT BIT(6) +#define BIT_CTWENDINT_INT BIT(6) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_C2H_W_READY_INT BIT(6) +#define BIT_FS_C2H_W_READY_INT BIT(6) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_HRCV_INT BIT(5) +#define BIT_HRCV_INT BIT(5) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_HRCV_INT BIT(5) +#define BIT_FS_HRCV_INT BIT(5) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_H2CCMD_INT BIT(4) +#define BIT_H2CCMD_INT BIT(4) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_H2CCMD_INT BIT(4) +#define BIT_FS_H2CCMD_INT BIT(4) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_RXDONE_INT BIT(3) +#define BIT_RXDONE_INT BIT(3) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXPKTIN_INT BIT(3) +#define BIT_FS_TXPKTIN_INT BIT(3) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_ERRORHDL_INT BIT(2) +#define BIT_ERRORHDL_INT BIT(2) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_ERRORHDL_INT BIT(2) +#define BIT_FS_ERRORHDL_INT BIT(2) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_TXCCX_INT BIT(1) +#define BIT_TXCCX_INT BIT(1) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXCCX_INT BIT(1) +#define BIT_FS_TXCCX_INT BIT(1) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_TXCLOSE_INT BIT(0) +#define BIT_TXCLOSE_INT BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_TXCLOSE_INT BIT(0) +#define BIT_FS_TXCLOSE_INT BIT(0) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_GTINT6_MSK BIT(31) -#define BIT_TX_NULL1_INT_MSK BIT(30) -#define BIT_TX_NULL0_INT_MSK BIT(29) -#define BIT_MTI_BCNIVLEAR_INT_MSK BIT(28) -#define BIT_ATIMINT_MSK BIT(27) -#define BIT_WWLAN_INT_EN BIT(26) -#define BIT_C2H_W_READY_EN BIT(25) -#define BIT_TRL_MTR_EN BIT(24) -#define BIT_CLR_PS_STATUS_MSK BIT(23) +#define BIT_GTINT6_MSK BIT(31) +#define BIT_TX_NULL1_INT_MSK BIT(30) +#define BIT_TX_NULL0_INT_MSK BIT(29) +#define BIT_MTI_BCNIVLEAR_INT_MSK BIT(28) +#define BIT_ATIMINT_MSK BIT(27) +#define BIT_WWLAN_INT_EN BIT(26) +#define BIT_C2H_W_READY_EN BIT(25) +#define BIT_TRL_MTR_EN BIT(24) +#define BIT_CLR_PS_STATUS_MSK BIT(23) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_PS_TIMER_C_EARLY_INT_EN BIT(23) +#define BIT_PS_TIMER_C_EARLY_INT_EN BIT(23) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_RETRIEVE_BUFFERED_MSK BIT(22) +#define BIT_RETRIEVE_BUFFERED_MSK BIT(22) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_PS_TIMER_B_EARLY_INT_EN BIT(22) +#define BIT_PS_TIMER_B_EARLY_INT_EN BIT(22) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_RPWMINT2_MSK BIT(21) +#define BIT_RPWMINT2_MSK BIT(21) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_PS_TIMER_A_EARLY_INT_EN BIT(21) +#define BIT_PS_TIMER_A_EARLY_INT_EN BIT(21) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_TSF_BIT32_TOGGLE_MSK_V1 BIT(20) +#define BIT_TSF_BIT32_TOGGLE_MSK_V1 BIT(20) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN BIT(20) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN BIT(20) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_TRIGGER_PKT_MSK BIT(19) +#define BIT_TRIGGER_PKT_MSK BIT(19) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_PS_TIMER_C_INT_EN BIT(19) +#define BIT_PS_TIMER_C_INT_EN BIT(19) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FW_BTCMD_INTMSK BIT(18) +#define BIT_FW_BTCMD_INTMSK BIT(18) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_PS_TIMER_B_INT_EN BIT(18) +#define BIT_PS_TIMER_B_INT_EN BIT(18) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_P2P_RFOFF_INTMSK BIT(17) +#define BIT_P2P_RFOFF_INTMSK BIT(17) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_PS_TIMER_A_INT_EN BIT(17) +#define BIT_PS_TIMER_A_INT_EN BIT(17) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_P2P_RFON_INTMSK BIT(16) +#define BIT_P2P_RFON_INTMSK BIT(16) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_CPUMGQ_TX_TIMER_INT_EN BIT(16) +#define BIT_CPUMGQ_TX_TIMER_INT_EN BIT(16) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_TXBCN1ERR_MSK BIT(15) +#define BIT_TXBCN1ERR_MSK BIT(15) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FS_PS_TIMEOUT2_EN BIT(15) +#define BIT_FS_PS_TIMEOUT2_EN BIT(15) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_TXBCN1OK_MSK BIT(14) +#define BIT_TXBCN1OK_MSK BIT(14) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FS_PS_TIMEOUT1_EN BIT(14) +#define BIT_FS_PS_TIMEOUT1_EN BIT(14) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FT_ATIMEND_EMSK BIT(13) +#define BIT_FT_ATIMEND_EMSK BIT(13) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FS_PS_TIMEOUT0_EN BIT(13) +#define BIT_FS_PS_TIMEOUT0_EN BIT(13) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_BCNDMAINT_EMSK BIT(12) -#define BIT_GTINT5_MSK BIT(11) -#define BIT_EOSP_INT_MSK BIT(10) -#define BIT_RX_BCN_E_MSK BIT(9) -#define BIT_RPWM_INT_EN BIT(8) +#define BIT_BCNDMAINT_EMSK BIT(12) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FS_GTINT8_EN BIT(8) +#define BIT_FS_GTINT12_EN BIT(12) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_PSTIMER_MSK BIT(7) +#define BIT_GTINT5_MSK BIT(11) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FS_GTINT7_EN BIT(7) +#define BIT_FS_GTINT11_EN BIT(11) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_TIMEOUT1_MSK BIT(6) +#define BIT_EOSP_INT_MSK BIT(10) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FS_GTINT6_EN BIT(6) +#define BIT_FS_GTINT10_EN BIT(10) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_TIMEOUT0_MSK BIT(5) +#define BIT_RX_BCN_E_MSK BIT(9) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FS_GTINT5_EN BIT(5) +#define BIT_FS_GTINT9_EN BIT(9) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FT_GTINT4_MSK BIT(4) +#define BIT_RPWM_INT_EN BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FS_GTINT4_EN BIT(4) +#define BIT_FS_GTINT8_EN BIT(8) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FT_GTINT3_MSK BIT(3) +#define BIT_PSTIMER_MSK BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FTIMR (Offset 0x0138) */ + +#define BIT_FS_GTINT7_EN BIT(7) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FS_GTINT3_EN BIT(3) +#define BIT_TIMEOUT1_MSK BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ + +#define BIT_FS_GTINT6_EN BIT(6) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_GTINT2_MSK BIT(2) +#define BIT_TIMEOUT0_MSK BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FTIMR (Offset 0x0138) */ + +#define BIT_FS_GTINT5_EN BIT(5) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FS_GTINT2_EN BIT(2) +#define BIT_FT_GTINT4_MSK BIT(4) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT4_EN BIT(4) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_GTINT1_MSK BIT(1) +#define BIT_FT_GTINT3_MSK BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ + +#define BIT_FS_GTINT3_EN BIT(3) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FS_GTINT1_EN BIT(1) +#define BIT_GTINT2_MSK BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ + +#define BIT_FS_GTINT2_EN BIT(2) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_GTINT0_MSK BIT(0) +#define BIT_GTINT1_MSK BIT(1) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FTIMR (Offset 0x0138) */ + +#define BIT_FS_GTINT1_EN BIT(1) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_FS_GTINT0_EN BIT(0) +#define BIT_GTINT0_MSK BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT0_EN BIT(0) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_GT6INT BIT(31) -#define BIT_TX_NULL1_INT BIT(30) -#define BIT_TX_NULL0_INT BIT(29) -#define BIT_MTI_BCNIVLEAR_INT BIT(28) -#define BIT_ATIM_INT BIT(27) -#define BIT_WWLAN_INT BIT(26) -#define BIT_C2H_W_READY BIT(25) -#define BIT_TRL_MTR_INT BIT(24) -#define BIT_CLR_PS_STATUS BIT(23) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_GT6INT BIT(31) +#define BIT_TX_NULL1_INT BIT(30) +#define BIT_TX_NULL0_INT BIT(29) +#define BIT_MTI_BCNIVLEAR_INT BIT(28) +#define BIT_ATIM_INT BIT(27) +#define BIT_WWLAN_INT BIT(26) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_PS_TIMER_C_EARLY__INT BIT(23) +#define BIT_PS_TIMER_5_EARLY__INT BIT(26) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_RETRIEVE_BUFFERED_INT BIT(22) +#define BIT_C2H_W_READY BIT(25) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_PS_TIMER_B_EARLY__INT BIT(22) +#define BIT_PS_TIMER_4_EARLY__INT BIT(25) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_RPWM2INT BIT(21) +#define BIT_TRL_MTR_INT BIT(24) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_PS_TIMER_A_EARLY__INT BIT(21) +#define BIT_PS_TIMER_3_EARLY__INT BIT(24) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_TSF_BIT32_TOGGLE_INT_V1 BIT(20) +#define BIT_CLR_PS_STATUS BIT(23) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_PS_TIMER_C_EARLY__INT BIT(23) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_CPUMGQ_TX_TIMER_EARLY_INT BIT(20) +#define BIT_PS_TIMER_2_EARLY__INT BIT(23) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_TRIGGER_PKT BIT(19) +#define BIT_RETRIEVE_BUFFERED_INT BIT(22) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_PS_TIMER_B_EARLY__INT BIT(22) + +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_PS_TIMER_C_INT BIT(19) +#define BIT_PS_TIMER_1_EARLY__INT BIT(22) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FW_BTCMD_INT BIT(18) +#define BIT_RPWM2INT BIT(21) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_PS_TIMER_A_EARLY__INT BIT(21) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_PS_TIMER_B_INT BIT(18) +#define BIT_PS_TIMER_0_EARLY__INT BIT(21) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_P2P_RFOFF_INT BIT(17) +#define BIT_TSF_BIT32_TOGGLE_INT_V1 BIT(20) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_PS_TIMER_A_INT BIT(17) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT BIT(20) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_P2P_RFON_INT BIT(16) +#define BIT_TRIGGER_PKT BIT(19) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_PS_TIMER_C_INT BIT(19) + +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_CPUMGQ_TX_TIMER_INT BIT(16) +#define BIT_PS_TIMER_5_INT BIT(19) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_TX_BCN1ERR_INT BIT(15) +#define BIT_FW_BTCMD_INT BIT(18) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_PS_TIMER_B_INT BIT(18) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FS_PS_TIMEOUT2_INT BIT(15) +#define BIT_PS_TIMER_4_INT BIT(18) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_TX_BCN1OK_INT BIT(14) +#define BIT_P2P_RFOFF_INT BIT(17) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_PS_TIMER_A_INT BIT(17) + +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FS_PS_TIMEOUT1_INT BIT(14) +#define BIT_PS_TIMER_3_INT BIT(17) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FT_ATIMEND_E BIT(13) +#define BIT_P2P_RFON_INT BIT(16) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FS_PS_TIMEOUT0_INT BIT(13) +#define BIT_CPUMGQ_TX_TIMER_INT BIT(16) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_BCNDMAINT_E_V1 BIT(12) -#define BIT_GT5INT BIT(11) -#define BIT_EOSP_INT BIT(10) -#define BIT_RX_BCN_E_INT BIT(9) -#define BIT_RPWMINT BIT(8) +#define BIT_TX_BCN1ERR_INT BIT(15) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_FS_PS_TIMEOUT2_INT BIT(15) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FS_GTINT8_INT BIT(8) +#define BIT_PS_TIMER_2_INT BIT(15) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_PSTIMER_INT BIT(7) +#define BIT_TX_BCN1OK_INT BIT(14) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_FS_PS_TIMEOUT1_INT BIT(14) + +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FS_GTINT7_INT BIT(7) +#define BIT_PS_TIMER_1_INT BIT(14) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_TIMEOUT1_INT BIT(6) +#define BIT_FT_ATIMEND_E BIT(13) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_FS_PS_TIMEOUT0_INT BIT(13) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FS_GTINT6_INT BIT(6) +#define BIT_PS_TIMER_0_INT BIT(13) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_TIMEOUT0_INT BIT(5) +#define BIT_BCNDMAINT_E_V1 BIT(12) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FS_GTINT5_INT BIT(5) +#define BIT_FS_GTINT12_INT BIT(12) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FT_GT4INT BIT(4) +#define BIT_GT5INT BIT(11) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FS_GTINT4_INT BIT(4) +#define BIT_FS_GTINT11_INT BIT(11) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FT_GT3INT BIT(3) +#define BIT_EOSP_INT BIT(10) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_FS_GTINT10_INT BIT(10) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FS_GTINT3_INT BIT(3) +#define BIT_RX_BCN_E_INT BIT(9) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_FS_GTINT9_INT BIT(9) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_GT2INT BIT(2) +#define BIT_RPWMINT BIT(8) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_FS_GTINT8_INT BIT(8) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FS_GTINT2_INT BIT(2) +#define BIT_PSTIMER_INT BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_FS_GTINT7_INT BIT(7) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_GT1INT BIT(1) +#define BIT_TIMEOUT1_INT BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_FS_GTINT6_INT BIT(6) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FS_GTINT1_INT BIT(1) +#define BIT_TIMEOUT0_INT BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_FS_GTINT5_INT BIT(5) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_GT0INT BIT(0) +#define BIT_FT_GT4INT BIT(4) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_FS_GTINT4_INT BIT(4) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_FS_GTINT0_INT BIT(0) +#define BIT_FT_GT3INT BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_GTINT3_INT BIT(3) -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKTBUF_WRITE_EN 24 -#define BIT_MASK_PKTBUF_WRITE_EN 0xff -#define BIT_PKTBUF_WRITE_EN(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN) -#define BIT_GET_PKTBUF_WRITE_EN(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_GT2INT BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_GTINT2_INT BIT(2) -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#endif -#define BIT_TXPKT_BUF_READ_EN BIT(23) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_GT1INT BIT(1) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +/* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_TXRPTBUF_DBG BIT(23) +#define BIT_FS_GTINT1_INT BIT(1) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ - -#define BIT_TXRPT_BUF_READ_EN BIT(20) +#define BIT_GT0INT BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FTISR (Offset 0x013C) */ + +#define BIT_FS_GTINT0_INT BIT(0) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ -#define BIT_TXPKTBUF_DBG_V2 BIT(20) +#define BIT_SHIFT_PKTBUF_WRITE_EN 24 +#define BIT_MASK_PKTBUF_WRITE_EN 0xff +#define BIT_PKTBUF_WRITE_EN(x) \ + (((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN) +#define BITS_PKTBUF_WRITE_EN \ + (BIT_MASK_PKTBUF_WRITE_EN << BIT_SHIFT_PKTBUF_WRITE_EN) +#define BIT_CLEAR_PKTBUF_WRITE_EN(x) ((x) & (~BITS_PKTBUF_WRITE_EN)) +#define BIT_GET_PKTBUF_WRITE_EN(x) \ + (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN) +#define BIT_SET_PKTBUF_WRITE_EN(x, v) \ + (BIT_CLEAR_PKTBUF_WRITE_EN(x) | BIT_PKTBUF_WRITE_EN(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ -#define BIT_RXPKT_BUF_READ_EN BIT(16) +#define BIT_TXPKT_BUF_READ_EN BIT(23) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ -#define BIT_RXPKTBUF_DBG BIT(16) +#define BIT_TXRPTBUF_DBG BIT(23) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_TXRPT_BUF_READ_EN BIT(20) -#define BIT_SHIFT_PKTBUF_ADDR 0 -#define BIT_MASK_PKTBUF_ADDR 0x1fff -#define BIT_PKTBUF_ADDR(x) (((x) & BIT_MASK_PKTBUF_ADDR) << BIT_SHIFT_PKTBUF_ADDR) -#define BIT_GET_PKTBUF_ADDR(x) (((x) >> BIT_SHIFT_PKTBUF_ADDR) & BIT_MASK_PKTBUF_ADDR) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_TXPKTBUF_DBG_V2 BIT(20) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_RXPKT_BUF_READ_EN BIT(16) -#define BIT_SHIFT_PKTBUF_DBG_ADDR 0 -#define BIT_MASK_PKTBUF_DBG_ADDR 0x1fff -#define BIT_PKTBUF_DBG_ADDR(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR) << BIT_SHIFT_PKTBUF_DBG_ADDR) -#define BIT_GET_PKTBUF_DBG_ADDR(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR) & BIT_MASK_PKTBUF_DBG_ADDR) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_RXPKTBUF_DBG BIT(16) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_PKTBUF_DBG_DATA_L (Offset 0x0144) */ +/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_SHIFT_PKTBUF_ADDR 0 +#define BIT_MASK_PKTBUF_ADDR 0x1fff +#define BIT_PKTBUF_ADDR(x) \ + (((x) & BIT_MASK_PKTBUF_ADDR) << BIT_SHIFT_PKTBUF_ADDR) +#define BITS_PKTBUF_ADDR (BIT_MASK_PKTBUF_ADDR << BIT_SHIFT_PKTBUF_ADDR) +#define BIT_CLEAR_PKTBUF_ADDR(x) ((x) & (~BITS_PKTBUF_ADDR)) +#define BIT_GET_PKTBUF_ADDR(x) \ + (((x) >> BIT_SHIFT_PKTBUF_ADDR) & BIT_MASK_PKTBUF_ADDR) +#define BIT_SET_PKTBUF_ADDR(x, v) \ + (BIT_CLEAR_PKTBUF_ADDR(x) | BIT_PKTBUF_ADDR(v)) -#define BIT_SHIFT_PKTBUF_DBG_DATA_L 0 -#define BIT_MASK_PKTBUF_DBG_DATA_L 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_L(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L) -#define BIT_GET_PKTBUF_DBG_DATA_L(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_PKTBUF_DBG_DATA_H (Offset 0x0148) */ +/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_SHIFT_PKTBUF_DBG_ADDR 0 +#define BIT_MASK_PKTBUF_DBG_ADDR 0x1fff +#define BIT_PKTBUF_DBG_ADDR(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_ADDR) << BIT_SHIFT_PKTBUF_DBG_ADDR) +#define BITS_PKTBUF_DBG_ADDR \ + (BIT_MASK_PKTBUF_DBG_ADDR << BIT_SHIFT_PKTBUF_DBG_ADDR) +#define BIT_CLEAR_PKTBUF_DBG_ADDR(x) ((x) & (~BITS_PKTBUF_DBG_ADDR)) +#define BIT_GET_PKTBUF_DBG_ADDR(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR) & BIT_MASK_PKTBUF_DBG_ADDR) +#define BIT_SET_PKTBUF_DBG_ADDR(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_ADDR(x) | BIT_PKTBUF_DBG_ADDR(v)) -#define BIT_SHIFT_PKTBUF_DBG_DATA_H 0 -#define BIT_MASK_PKTBUF_DBG_DATA_H 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_H(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H) << BIT_SHIFT_PKTBUF_DBG_DATA_H) -#define BIT_GET_PKTBUF_DBG_DATA_H(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H) & BIT_MASK_PKTBUF_DBG_DATA_H) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_CPWM2 (Offset 0x014C) */ +/* 2 REG_PKTBUF_DBG_DATA_L (Offset 0x0144) */ +#define BIT_SHIFT_PKTBUF_DBG_DATA_L 0 +#define BIT_MASK_PKTBUF_DBG_DATA_L 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_L(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L) +#define BITS_PKTBUF_DBG_DATA_L \ + (BIT_MASK_PKTBUF_DBG_DATA_L << BIT_SHIFT_PKTBUF_DBG_DATA_L) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L(x) ((x) & (~BITS_PKTBUF_DBG_DATA_L)) +#define BIT_GET_PKTBUF_DBG_DATA_L(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L) +#define BIT_SET_PKTBUF_DBG_DATA_L(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_L(x) | BIT_PKTBUF_DBG_DATA_L(v)) -#define BIT_SHIFT_L0S_TO_RCVY_NUM 16 -#define BIT_MASK_L0S_TO_RCVY_NUM 0xff -#define BIT_L0S_TO_RCVY_NUM(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM) -#define BIT_GET_L0S_TO_RCVY_NUM(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM) +/* 2 REG_PKTBUF_DBG_DATA_H (Offset 0x0148) */ -#define BIT_CPWM2_TOGGLING BIT(15) +#define BIT_SHIFT_PKTBUF_DBG_DATA_H 0 +#define BIT_MASK_PKTBUF_DBG_DATA_H 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_H(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_H) << BIT_SHIFT_PKTBUF_DBG_DATA_H) +#define BITS_PKTBUF_DBG_DATA_H \ + (BIT_MASK_PKTBUF_DBG_DATA_H << BIT_SHIFT_PKTBUF_DBG_DATA_H) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H(x) ((x) & (~BITS_PKTBUF_DBG_DATA_H)) +#define BIT_GET_PKTBUF_DBG_DATA_H(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H) & BIT_MASK_PKTBUF_DBG_DATA_H) +#define BIT_SET_PKTBUF_DBG_DATA_H(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_H(x) | BIT_PKTBUF_DBG_DATA_H(v)) -#define BIT_SHIFT_CPWM2_MOD 0 -#define BIT_MASK_CPWM2_MOD 0x7fff -#define BIT_CPWM2_MOD(x) (((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD) -#define BIT_GET_CPWM2_MOD(x) (((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD) +/* 2 REG_CPWM2 (Offset 0x014C) */ +#define BIT_SHIFT_L0S_TO_RCVY_NUM 16 +#define BIT_MASK_L0S_TO_RCVY_NUM 0xff +#define BIT_L0S_TO_RCVY_NUM(x) \ + (((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM) +#define BITS_L0S_TO_RCVY_NUM \ + (BIT_MASK_L0S_TO_RCVY_NUM << BIT_SHIFT_L0S_TO_RCVY_NUM) +#define BIT_CLEAR_L0S_TO_RCVY_NUM(x) ((x) & (~BITS_L0S_TO_RCVY_NUM)) +#define BIT_GET_L0S_TO_RCVY_NUM(x) \ + (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM) +#define BIT_SET_L0S_TO_RCVY_NUM(x, v) \ + (BIT_CLEAR_L0S_TO_RCVY_NUM(x) | BIT_L0S_TO_RCVY_NUM(v)) + +#define BIT_CPWM2_TOGGLING BIT(15) + +#define BIT_SHIFT_CPWM2_MOD 0 +#define BIT_MASK_CPWM2_MOD 0x7fff +#define BIT_CPWM2_MOD(x) (((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD) +#define BITS_CPWM2_MOD (BIT_MASK_CPWM2_MOD << BIT_SHIFT_CPWM2_MOD) +#define BIT_CLEAR_CPWM2_MOD(x) ((x) & (~BITS_CPWM2_MOD)) +#define BIT_GET_CPWM2_MOD(x) (((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD) +#define BIT_SET_CPWM2_MOD(x, v) (BIT_CLEAR_CPWM2_MOD(x) | BIT_CPWM2_MOD(v)) /* 2 REG_TC0_CTRL (Offset 0x0150) */ -#define BIT_TC0INT_EN BIT(26) -#define BIT_TC0MODE BIT(25) -#define BIT_TC0EN BIT(24) - -#define BIT_SHIFT_TC0DATA 0 -#define BIT_MASK_TC0DATA 0xffffff -#define BIT_TC0DATA(x) (((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA) -#define BIT_GET_TC0DATA(x) (((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA) +#define BIT_TC0INT_EN BIT(26) +#define BIT_TC0MODE BIT(25) +#define BIT_TC0EN BIT(24) +#define BIT_SHIFT_TC0DATA 0 +#define BIT_MASK_TC0DATA 0xffffff +#define BIT_TC0DATA(x) (((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA) +#define BITS_TC0DATA (BIT_MASK_TC0DATA << BIT_SHIFT_TC0DATA) +#define BIT_CLEAR_TC0DATA(x) ((x) & (~BITS_TC0DATA)) +#define BIT_GET_TC0DATA(x) (((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA) +#define BIT_SET_TC0DATA(x, v) (BIT_CLEAR_TC0DATA(x) | BIT_TC0DATA(v)) /* 2 REG_TC1_CTRL (Offset 0x0154) */ -#define BIT_TC1INT_EN BIT(26) -#define BIT_TC1MODE BIT(25) -#define BIT_TC1EN BIT(24) - -#define BIT_SHIFT_TC1DATA 0 -#define BIT_MASK_TC1DATA 0xffffff -#define BIT_TC1DATA(x) (((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA) -#define BIT_GET_TC1DATA(x) (((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA) +#define BIT_TC1INT_EN BIT(26) +#define BIT_TC1MODE BIT(25) +#define BIT_TC1EN BIT(24) +#define BIT_SHIFT_TC1DATA 0 +#define BIT_MASK_TC1DATA 0xffffff +#define BIT_TC1DATA(x) (((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA) +#define BITS_TC1DATA (BIT_MASK_TC1DATA << BIT_SHIFT_TC1DATA) +#define BIT_CLEAR_TC1DATA(x) ((x) & (~BITS_TC1DATA)) +#define BIT_GET_TC1DATA(x) (((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA) +#define BIT_SET_TC1DATA(x, v) (BIT_CLEAR_TC1DATA(x) | BIT_TC1DATA(v)) /* 2 REG_TC2_CTRL (Offset 0x0158) */ -#define BIT_TC2INT_EN BIT(26) -#define BIT_TC2MODE BIT(25) -#define BIT_TC2EN BIT(24) - -#define BIT_SHIFT_TC2DATA 0 -#define BIT_MASK_TC2DATA 0xffffff -#define BIT_TC2DATA(x) (((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA) -#define BIT_GET_TC2DATA(x) (((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA) +#define BIT_TC2INT_EN BIT(26) +#define BIT_TC2MODE BIT(25) +#define BIT_TC2EN BIT(24) +#define BIT_SHIFT_TC2DATA 0 +#define BIT_MASK_TC2DATA 0xffffff +#define BIT_TC2DATA(x) (((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA) +#define BITS_TC2DATA (BIT_MASK_TC2DATA << BIT_SHIFT_TC2DATA) +#define BIT_CLEAR_TC2DATA(x) ((x) & (~BITS_TC2DATA)) +#define BIT_GET_TC2DATA(x) (((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA) +#define BIT_SET_TC2DATA(x, v) (BIT_CLEAR_TC2DATA(x) | BIT_TC2DATA(v)) /* 2 REG_TC3_CTRL (Offset 0x015C) */ -#define BIT_TC3INT_EN BIT(26) -#define BIT_TC3MODE BIT(25) -#define BIT_TC3EN BIT(24) - -#define BIT_SHIFT_TC3DATA 0 -#define BIT_MASK_TC3DATA 0xffffff -#define BIT_TC3DATA(x) (((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA) -#define BIT_GET_TC3DATA(x) (((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA) +#define BIT_TC3INT_EN BIT(26) +#define BIT_TC3MODE BIT(25) +#define BIT_TC3EN BIT(24) +#define BIT_SHIFT_TC3DATA 0 +#define BIT_MASK_TC3DATA 0xffffff +#define BIT_TC3DATA(x) (((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA) +#define BITS_TC3DATA (BIT_MASK_TC3DATA << BIT_SHIFT_TC3DATA) +#define BIT_CLEAR_TC3DATA(x) ((x) & (~BITS_TC3DATA)) +#define BIT_GET_TC3DATA(x) (((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA) +#define BIT_SET_TC3DATA(x, v) (BIT_CLEAR_TC3DATA(x) | BIT_TC3DATA(v)) /* 2 REG_TC4_CTRL (Offset 0x0160) */ -#define BIT_TC4INT_EN BIT(26) -#define BIT_TC4MODE BIT(25) -#define BIT_TC4EN BIT(24) - -#define BIT_SHIFT_TC4DATA 0 -#define BIT_MASK_TC4DATA 0xffffff -#define BIT_TC4DATA(x) (((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA) -#define BIT_GET_TC4DATA(x) (((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA) +#define BIT_TC4INT_EN BIT(26) +#define BIT_TC4MODE BIT(25) +#define BIT_TC4EN BIT(24) +#define BIT_SHIFT_TC4DATA 0 +#define BIT_MASK_TC4DATA 0xffffff +#define BIT_TC4DATA(x) (((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA) +#define BITS_TC4DATA (BIT_MASK_TC4DATA << BIT_SHIFT_TC4DATA) +#define BIT_CLEAR_TC4DATA(x) ((x) & (~BITS_TC4DATA)) +#define BIT_GET_TC4DATA(x) (((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA) +#define BIT_SET_TC4DATA(x, v) (BIT_CLEAR_TC4DATA(x) | BIT_TC4DATA(v)) /* 2 REG_TCUNIT_BASE (Offset 0x0164) */ - -#define BIT_SHIFT_TCUNIT_BASE 0 -#define BIT_MASK_TCUNIT_BASE 0x3fff -#define BIT_TCUNIT_BASE(x) (((x) & BIT_MASK_TCUNIT_BASE) << BIT_SHIFT_TCUNIT_BASE) -#define BIT_GET_TCUNIT_BASE(x) (((x) >> BIT_SHIFT_TCUNIT_BASE) & BIT_MASK_TCUNIT_BASE) - +#define BIT_SHIFT_TCUNIT_BASE 0 +#define BIT_MASK_TCUNIT_BASE 0x3fff +#define BIT_TCUNIT_BASE(x) \ + (((x) & BIT_MASK_TCUNIT_BASE) << BIT_SHIFT_TCUNIT_BASE) +#define BITS_TCUNIT_BASE (BIT_MASK_TCUNIT_BASE << BIT_SHIFT_TCUNIT_BASE) +#define BIT_CLEAR_TCUNIT_BASE(x) ((x) & (~BITS_TCUNIT_BASE)) +#define BIT_GET_TCUNIT_BASE(x) \ + (((x) >> BIT_SHIFT_TCUNIT_BASE) & BIT_MASK_TCUNIT_BASE) +#define BIT_SET_TCUNIT_BASE(x, v) \ + (BIT_CLEAR_TCUNIT_BASE(x) | BIT_TCUNIT_BASE(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_TC5_CTRL (Offset 0x0168) */ -#define BIT_TC50INT_EN BIT(26) +#define BIT_TC50INT_EN BIT(26) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TC5_CTRL (Offset 0x0168) */ -#define BIT_TC5INT_EN BIT(26) +#define BIT_TC5INT_EN BIT(26) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_TC5_CTRL (Offset 0x0168) */ -#define BIT_TC5MODE BIT(25) -#define BIT_TC5EN BIT(24) - -#define BIT_SHIFT_TC5DATA 0 -#define BIT_MASK_TC5DATA 0xffffff -#define BIT_TC5DATA(x) (((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA) -#define BIT_GET_TC5DATA(x) (((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA) +#define BIT_TC5MODE BIT(25) +#define BIT_TC5EN BIT(24) +#define BIT_SHIFT_TC5DATA 0 +#define BIT_MASK_TC5DATA 0xffffff +#define BIT_TC5DATA(x) (((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA) +#define BITS_TC5DATA (BIT_MASK_TC5DATA << BIT_SHIFT_TC5DATA) +#define BIT_CLEAR_TC5DATA(x) ((x) & (~BITS_TC5DATA)) +#define BIT_GET_TC5DATA(x) (((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA) +#define BIT_SET_TC5DATA(x, v) (BIT_CLEAR_TC5DATA(x) | BIT_TC5DATA(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_TC6_CTRL (Offset 0x016C) */ -#define BIT_TC60INT_EN BIT(26) +#define BIT_TC60INT_EN BIT(26) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TC6_CTRL (Offset 0x016C) */ -#define BIT_TC6INT_EN BIT(26) +#define BIT_TC6INT_EN BIT(26) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_TC6_CTRL (Offset 0x016C) */ -#define BIT_TC6MODE BIT(25) -#define BIT_TC6EN BIT(24) - -#define BIT_SHIFT_TC6DATA 0 -#define BIT_MASK_TC6DATA 0xffffff -#define BIT_TC6DATA(x) (((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA) -#define BIT_GET_TC6DATA(x) (((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA) +#define BIT_TC6MODE BIT(25) +#define BIT_TC6EN BIT(24) +#define BIT_SHIFT_TC6DATA 0 +#define BIT_MASK_TC6DATA 0xffffff +#define BIT_TC6DATA(x) (((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA) +#define BITS_TC6DATA (BIT_MASK_TC6DATA << BIT_SHIFT_TC6DATA) +#define BIT_CLEAR_TC6DATA(x) ((x) & (~BITS_TC6DATA)) +#define BIT_GET_TC6DATA(x) (((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA) +#define BIT_SET_TC6DATA(x, v) (BIT_CLEAR_TC6DATA(x) | BIT_TC6DATA(v)) -/* 2 REG_MBIST_FAIL (Offset 0x0170) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_8051_MBIST_FAIL 26 -#define BIT_MASK_8051_MBIST_FAIL 0x7 -#define BIT_8051_MBIST_FAIL(x) (((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL) -#define BIT_GET_8051_MBIST_FAIL(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL) +/* 2 REG_MBIST_FAIL (Offset 0x0170) */ +#define BIT_SHIFT_8051_MBIST_FAIL 26 +#define BIT_MASK_8051_MBIST_FAIL 0x7 +#define BIT_8051_MBIST_FAIL(x) \ + (((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL) +#define BITS_8051_MBIST_FAIL \ + (BIT_MASK_8051_MBIST_FAIL << BIT_SHIFT_8051_MBIST_FAIL) +#define BIT_CLEAR_8051_MBIST_FAIL(x) ((x) & (~BITS_8051_MBIST_FAIL)) +#define BIT_GET_8051_MBIST_FAIL(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL) +#define BIT_SET_8051_MBIST_FAIL(x, v) \ + (BIT_CLEAR_8051_MBIST_FAIL(x) | BIT_8051_MBIST_FAIL(v)) -#define BIT_SHIFT_USB_MBIST_FAIL 24 -#define BIT_MASK_USB_MBIST_FAIL 0x3 -#define BIT_USB_MBIST_FAIL(x) (((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL) -#define BIT_GET_USB_MBIST_FAIL(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PCIE_MBIST_FAIL 16 -#define BIT_MASK_PCIE_MBIST_FAIL 0x3f -#define BIT_PCIE_MBIST_FAIL(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL) -#define BIT_GET_PCIE_MBIST_FAIL(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL) +/* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */ +#define BIT_SHIFT_8051_MBIST_DRF_FAIL 26 +#define BIT_MASK_8051_MBIST_DRF_FAIL 0x3f +#define BIT_8051_MBIST_DRF_FAIL(x) \ + (((x) & BIT_MASK_8051_MBIST_DRF_FAIL) << BIT_SHIFT_8051_MBIST_DRF_FAIL) +#define BITS_8051_MBIST_DRF_FAIL \ + (BIT_MASK_8051_MBIST_DRF_FAIL << BIT_SHIFT_8051_MBIST_DRF_FAIL) +#define BIT_CLEAR_8051_MBIST_DRF_FAIL(x) ((x) & (~BITS_8051_MBIST_DRF_FAIL)) +#define BIT_GET_8051_MBIST_DRF_FAIL(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL) & BIT_MASK_8051_MBIST_DRF_FAIL) +#define BIT_SET_8051_MBIST_DRF_FAIL(x, v) \ + (BIT_CLEAR_8051_MBIST_DRF_FAIL(x) | BIT_8051_MBIST_DRF_FAIL(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBIST_FAIL (Offset 0x0170) */ +#define BIT_SHIFT_USB_MBIST_FAIL 24 +#define BIT_MASK_USB_MBIST_FAIL 0x3 +#define BIT_USB_MBIST_FAIL(x) \ + (((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL) +#define BITS_USB_MBIST_FAIL \ + (BIT_MASK_USB_MBIST_FAIL << BIT_SHIFT_USB_MBIST_FAIL) +#define BIT_CLEAR_USB_MBIST_FAIL(x) ((x) & (~BITS_USB_MBIST_FAIL)) +#define BIT_GET_USB_MBIST_FAIL(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL) +#define BIT_SET_USB_MBIST_FAIL(x, v) \ + (BIT_CLEAR_USB_MBIST_FAIL(x) | BIT_USB_MBIST_FAIL(v)) + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */ + +#define BIT_SHIFT_USB_MBIST_DRF_FAIL 24 +#define BIT_MASK_USB_MBIST_DRF_FAIL 0x3 +#define BIT_USB_MBIST_DRF_FAIL(x) \ + (((x) & BIT_MASK_USB_MBIST_DRF_FAIL) << BIT_SHIFT_USB_MBIST_DRF_FAIL) +#define BITS_USB_MBIST_DRF_FAIL \ + (BIT_MASK_USB_MBIST_DRF_FAIL << BIT_SHIFT_USB_MBIST_DRF_FAIL) +#define BIT_CLEAR_USB_MBIST_DRF_FAIL(x) ((x) & (~BITS_USB_MBIST_DRF_FAIL)) +#define BIT_GET_USB_MBIST_DRF_FAIL(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL) & BIT_MASK_USB_MBIST_DRF_FAIL) +#define BIT_SET_USB_MBIST_DRF_FAIL(x, v) \ + (BIT_CLEAR_USB_MBIST_DRF_FAIL(x) | BIT_USB_MBIST_DRF_FAIL(v)) + +#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL 18 +#define BIT_MASK_PCIE_MBIST_DRF_FAIL 0x3f +#define BIT_PCIE_MBIST_DRF_FAIL(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL) << BIT_SHIFT_PCIE_MBIST_DRF_FAIL) +#define BITS_PCIE_MBIST_DRF_FAIL \ + (BIT_MASK_PCIE_MBIST_DRF_FAIL << BIT_SHIFT_PCIE_MBIST_DRF_FAIL) +#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL(x) ((x) & (~BITS_PCIE_MBIST_DRF_FAIL)) +#define BIT_GET_PCIE_MBIST_DRF_FAIL(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL) & BIT_MASK_PCIE_MBIST_DRF_FAIL) +#define BIT_SET_PCIE_MBIST_DRF_FAIL(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DRF_FAIL(x) | BIT_PCIE_MBIST_DRF_FAIL(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_FAIL (Offset 0x0170) */ +#define BIT_SHIFT_PCIE_MBIST_FAIL 16 +#define BIT_MASK_PCIE_MBIST_FAIL 0x3f +#define BIT_PCIE_MBIST_FAIL(x) \ + (((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL) +#define BITS_PCIE_MBIST_FAIL \ + (BIT_MASK_PCIE_MBIST_FAIL << BIT_SHIFT_PCIE_MBIST_FAIL) +#define BIT_CLEAR_PCIE_MBIST_FAIL(x) ((x) & (~BITS_PCIE_MBIST_FAIL)) +#define BIT_GET_PCIE_MBIST_FAIL(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL) +#define BIT_SET_PCIE_MBIST_FAIL(x, v) \ + (BIT_CLEAR_PCIE_MBIST_FAIL(x) | BIT_PCIE_MBIST_FAIL(v)) -#define BIT_SHIFT_MAC_MBIST_FAIL 0 -#define BIT_MASK_MAC_MBIST_FAIL 0xfff -#define BIT_MAC_MBIST_FAIL(x) (((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL) -#define BIT_GET_MAC_MBIST_FAIL(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_MBIST_FAIL (Offset 0x0170) */ +#define BIT_SHIFT_MAC_MBIST_FAIL 0 +#define BIT_MASK_MAC_MBIST_FAIL 0xfff +#define BIT_MAC_MBIST_FAIL(x) \ + (((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL) +#define BITS_MAC_MBIST_FAIL \ + (BIT_MASK_MAC_MBIST_FAIL << BIT_SHIFT_MAC_MBIST_FAIL) +#define BIT_CLEAR_MAC_MBIST_FAIL(x) ((x) & (~BITS_MAC_MBIST_FAIL)) +#define BIT_GET_MAC_MBIST_FAIL(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL) +#define BIT_SET_MAC_MBIST_FAIL(x, v) \ + (BIT_CLEAR_MAC_MBIST_FAIL(x) | BIT_MAC_MBIST_FAIL(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_MBIST_FAIL (Offset 0x0170) */ +#define BIT_SHIFT_MAC_MBIST_FAIL_DRF 0 +#define BIT_MASK_MAC_MBIST_FAIL_DRF 0x3ffff +#define BIT_MAC_MBIST_FAIL_DRF(x) \ + (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF) << BIT_SHIFT_MAC_MBIST_FAIL_DRF) +#define BITS_MAC_MBIST_FAIL_DRF \ + (BIT_MASK_MAC_MBIST_FAIL_DRF << BIT_SHIFT_MAC_MBIST_FAIL_DRF) +#define BIT_CLEAR_MAC_MBIST_FAIL_DRF(x) ((x) & (~BITS_MAC_MBIST_FAIL_DRF)) +#define BIT_GET_MAC_MBIST_FAIL_DRF(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF) & BIT_MASK_MAC_MBIST_FAIL_DRF) +#define BIT_SET_MAC_MBIST_FAIL_DRF(x, v) \ + (BIT_CLEAR_MAC_MBIST_FAIL_DRF(x) | BIT_MAC_MBIST_FAIL_DRF(v)) -#define BIT_SHIFT_MAC_MBIST_FAIL_DRF 0 -#define BIT_MASK_MAC_MBIST_FAIL_DRF 0x3ffff -#define BIT_MAC_MBIST_FAIL_DRF(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF) << BIT_SHIFT_MAC_MBIST_FAIL_DRF) -#define BIT_GET_MAC_MBIST_FAIL_DRF(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF) & BIT_MASK_MAC_MBIST_FAIL_DRF) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */ +#define BIT_SHIFT_MAC_MBIST_DRF_FAIL 0 +#define BIT_MASK_MAC_MBIST_DRF_FAIL 0x3ffff +#define BIT_MAC_MBIST_DRF_FAIL(x) \ + (((x) & BIT_MASK_MAC_MBIST_DRF_FAIL) << BIT_SHIFT_MAC_MBIST_DRF_FAIL) +#define BITS_MAC_MBIST_DRF_FAIL \ + (BIT_MASK_MAC_MBIST_DRF_FAIL << BIT_SHIFT_MAC_MBIST_DRF_FAIL) +#define BIT_CLEAR_MAC_MBIST_DRF_FAIL(x) ((x) & (~BITS_MAC_MBIST_DRF_FAIL)) +#define BIT_GET_MAC_MBIST_DRF_FAIL(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL) & BIT_MASK_MAC_MBIST_DRF_FAIL) +#define BIT_SET_MAC_MBIST_DRF_FAIL(x, v) \ + (BIT_CLEAR_MAC_MBIST_DRF_FAIL(x) | BIT_MAC_MBIST_DRF_FAIL(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_8051_MBIST_START_PAUSE 26 +#define BIT_MASK_8051_MBIST_START_PAUSE 0x7 +#define BIT_8051_MBIST_START_PAUSE(x) \ + (((x) & BIT_MASK_8051_MBIST_START_PAUSE) \ + << BIT_SHIFT_8051_MBIST_START_PAUSE) +#define BITS_8051_MBIST_START_PAUSE \ + (BIT_MASK_8051_MBIST_START_PAUSE << BIT_SHIFT_8051_MBIST_START_PAUSE) +#define BIT_CLEAR_8051_MBIST_START_PAUSE(x) \ + ((x) & (~BITS_8051_MBIST_START_PAUSE)) +#define BIT_GET_8051_MBIST_START_PAUSE(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) & \ + BIT_MASK_8051_MBIST_START_PAUSE) +#define BIT_SET_8051_MBIST_START_PAUSE(x, v) \ + (BIT_CLEAR_8051_MBIST_START_PAUSE(x) | BIT_8051_MBIST_START_PAUSE(v)) -#define BIT_SHIFT_8051_MBIST_START_PAUSE 26 -#define BIT_MASK_8051_MBIST_START_PAUSE 0x7 -#define BIT_8051_MBIST_START_PAUSE(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE) << BIT_SHIFT_8051_MBIST_START_PAUSE) -#define BIT_GET_8051_MBIST_START_PAUSE(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) & BIT_MASK_8051_MBIST_START_PAUSE) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_USB_MBIST_START_PAUSE 24 -#define BIT_MASK_USB_MBIST_START_PAUSE 0x3 -#define BIT_USB_MBIST_START_PAUSE(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE) << BIT_SHIFT_USB_MBIST_START_PAUSE) -#define BIT_GET_USB_MBIST_START_PAUSE(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) & BIT_MASK_USB_MBIST_START_PAUSE) +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1 26 +#define BIT_MASK_8051_MBIST_START_PAUSE_V1 0x3f +#define BIT_8051_MBIST_START_PAUSE_V1(x) \ + (((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1) \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_V1) +#define BITS_8051_MBIST_START_PAUSE_V1 \ + (BIT_MASK_8051_MBIST_START_PAUSE_V1 \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_V1) +#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1(x) \ + ((x) & (~BITS_8051_MBIST_START_PAUSE_V1)) +#define BIT_GET_8051_MBIST_START_PAUSE_V1(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1) & \ + BIT_MASK_8051_MBIST_START_PAUSE_V1) +#define BIT_SET_8051_MBIST_START_PAUSE_V1(x, v) \ + (BIT_CLEAR_8051_MBIST_START_PAUSE_V1(x) | \ + BIT_8051_MBIST_START_PAUSE_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PCIE_MBIST_START_PAUSE 16 -#define BIT_MASK_PCIE_MBIST_START_PAUSE 0x3f -#define BIT_PCIE_MBIST_START_PAUSE(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE) << BIT_SHIFT_PCIE_MBIST_START_PAUSE) -#define BIT_GET_PCIE_MBIST_START_PAUSE(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) & BIT_MASK_PCIE_MBIST_START_PAUSE) +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_USB_MBIST_START_PAUSE 24 +#define BIT_MASK_USB_MBIST_START_PAUSE 0x3 +#define BIT_USB_MBIST_START_PAUSE(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE) +#define BITS_USB_MBIST_START_PAUSE \ + (BIT_MASK_USB_MBIST_START_PAUSE << BIT_SHIFT_USB_MBIST_START_PAUSE) +#define BIT_CLEAR_USB_MBIST_START_PAUSE(x) ((x) & (~BITS_USB_MBIST_START_PAUSE)) +#define BIT_GET_USB_MBIST_START_PAUSE(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) & \ + BIT_MASK_USB_MBIST_START_PAUSE) +#define BIT_SET_USB_MBIST_START_PAUSE(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE(x) | BIT_USB_MBIST_START_PAUSE(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1 24 +#define BIT_MASK_USB_MBIST_START_PAUSE_V1 0x3 +#define BIT_USB_MBIST_START_PAUSE_V1(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V1) +#define BITS_USB_MBIST_START_PAUSE_V1 \ + (BIT_MASK_USB_MBIST_START_PAUSE_V1 \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V1) +#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1(x) \ + ((x) & (~BITS_USB_MBIST_START_PAUSE_V1)) +#define BIT_GET_USB_MBIST_START_PAUSE_V1(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1) & \ + BIT_MASK_USB_MBIST_START_PAUSE_V1) +#define BIT_SET_USB_MBIST_START_PAUSE_V1(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE_V1(x) | \ + BIT_USB_MBIST_START_PAUSE_V1(v)) + +#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1 18 +#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1 0x3f +#define BIT_PCIE_MBIST_START_PAUSE_V1(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1) +#define BITS_PCIE_MBIST_START_PAUSE_V1 \ + (BIT_MASK_PCIE_MBIST_START_PAUSE_V1 \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1)) +#define BIT_GET_PCIE_MBIST_START_PAUSE_V1(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE_V1) +#define BIT_SET_PCIE_MBIST_START_PAUSE_V1(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1(x) | \ + BIT_PCIE_MBIST_START_PAUSE_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MAC_MBIST_START_PAUSE 0 -#define BIT_MASK_MAC_MBIST_START_PAUSE 0xfff -#define BIT_MAC_MBIST_START_PAUSE(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE) << BIT_SHIFT_MAC_MBIST_START_PAUSE) -#define BIT_GET_MAC_MBIST_START_PAUSE(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) & BIT_MASK_MAC_MBIST_START_PAUSE) +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_PCIE_MBIST_START_PAUSE 16 +#define BIT_MASK_PCIE_MBIST_START_PAUSE 0x3f +#define BIT_PCIE_MBIST_START_PAUSE(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE) +#define BITS_PCIE_MBIST_START_PAUSE \ + (BIT_MASK_PCIE_MBIST_START_PAUSE << BIT_SHIFT_PCIE_MBIST_START_PAUSE) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE)) +#define BIT_GET_PCIE_MBIST_START_PAUSE(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE) +#define BIT_SET_PCIE_MBIST_START_PAUSE(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE(x) | BIT_PCIE_MBIST_START_PAUSE(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ - -#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1 0 -#define BIT_MASK_MAC_MBIST_START_PAUSE_V1 0x3ffff -#define BIT_MAC_MBIST_START_PAUSE_V1(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1) << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) -#define BIT_GET_MAC_MBIST_START_PAUSE_V1(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) & BIT_MASK_MAC_MBIST_START_PAUSE_V1) - +#define BIT_SHIFT_MAC_MBIST_START_PAUSE 0 +#define BIT_MASK_MAC_MBIST_START_PAUSE 0xfff +#define BIT_MAC_MBIST_START_PAUSE(x) \ + (((x) & BIT_MASK_MAC_MBIST_START_PAUSE) \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE) +#define BITS_MAC_MBIST_START_PAUSE \ + (BIT_MASK_MAC_MBIST_START_PAUSE << BIT_SHIFT_MAC_MBIST_START_PAUSE) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE(x) ((x) & (~BITS_MAC_MBIST_START_PAUSE)) +#define BIT_GET_MAC_MBIST_START_PAUSE(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) & \ + BIT_MASK_MAC_MBIST_START_PAUSE) +#define BIT_SET_MAC_MBIST_START_PAUSE(x, v) \ + (BIT_CLEAR_MAC_MBIST_START_PAUSE(x) | BIT_MAC_MBIST_START_PAUSE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1 0 +#define BIT_MASK_MAC_MBIST_START_PAUSE_V1 0x3ffff +#define BIT_MAC_MBIST_START_PAUSE_V1(x) \ + (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1) \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) +#define BITS_MAC_MBIST_START_PAUSE_V1 \ + (BIT_MASK_MAC_MBIST_START_PAUSE_V1 \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1(x) \ + ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1)) +#define BIT_GET_MAC_MBIST_START_PAUSE_V1(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) & \ + BIT_MASK_MAC_MBIST_START_PAUSE_V1) +#define BIT_SET_MAC_MBIST_START_PAUSE_V1(x, v) \ + (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1(x) | \ + BIT_MAC_MBIST_START_PAUSE_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_8051_MBIST_DONE 26 +#define BIT_MASK_8051_MBIST_DONE 0x7 +#define BIT_8051_MBIST_DONE(x) \ + (((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE) +#define BITS_8051_MBIST_DONE \ + (BIT_MASK_8051_MBIST_DONE << BIT_SHIFT_8051_MBIST_DONE) +#define BIT_CLEAR_8051_MBIST_DONE(x) ((x) & (~BITS_8051_MBIST_DONE)) +#define BIT_GET_8051_MBIST_DONE(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE) +#define BIT_SET_8051_MBIST_DONE(x, v) \ + (BIT_CLEAR_8051_MBIST_DONE(x) | BIT_8051_MBIST_DONE(v)) -#define BIT_SHIFT_8051_MBIST_DONE 26 -#define BIT_MASK_8051_MBIST_DONE 0x7 -#define BIT_8051_MBIST_DONE(x) (((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE) -#define BIT_GET_8051_MBIST_DONE(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_USB_MBIST_DONE 24 -#define BIT_MASK_USB_MBIST_DONE 0x3 -#define BIT_USB_MBIST_DONE(x) (((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE) -#define BIT_GET_USB_MBIST_DONE(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE) +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_8051_MBIST_DONE_V1 26 +#define BIT_MASK_8051_MBIST_DONE_V1 0x3f +#define BIT_8051_MBIST_DONE_V1(x) \ + (((x) & BIT_MASK_8051_MBIST_DONE_V1) << BIT_SHIFT_8051_MBIST_DONE_V1) +#define BITS_8051_MBIST_DONE_V1 \ + (BIT_MASK_8051_MBIST_DONE_V1 << BIT_SHIFT_8051_MBIST_DONE_V1) +#define BIT_CLEAR_8051_MBIST_DONE_V1(x) ((x) & (~BITS_8051_MBIST_DONE_V1)) +#define BIT_GET_8051_MBIST_DONE_V1(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DONE_V1) & BIT_MASK_8051_MBIST_DONE_V1) +#define BIT_SET_8051_MBIST_DONE_V1(x, v) \ + (BIT_CLEAR_8051_MBIST_DONE_V1(x) | BIT_8051_MBIST_DONE_V1(v)) -#define BIT_SHIFT_PCIE_MBIST_DONE 16 -#define BIT_MASK_PCIE_MBIST_DONE 0x3f -#define BIT_PCIE_MBIST_DONE(x) (((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE) -#define BIT_GET_PCIE_MBIST_DONE(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_USB_MBIST_DONE 24 +#define BIT_MASK_USB_MBIST_DONE 0x3 +#define BIT_USB_MBIST_DONE(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE) +#define BITS_USB_MBIST_DONE \ + (BIT_MASK_USB_MBIST_DONE << BIT_SHIFT_USB_MBIST_DONE) +#define BIT_CLEAR_USB_MBIST_DONE(x) ((x) & (~BITS_USB_MBIST_DONE)) +#define BIT_GET_USB_MBIST_DONE(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE) +#define BIT_SET_USB_MBIST_DONE(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE(x) | BIT_USB_MBIST_DONE(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_USB_MBIST_DONE_V1 24 +#define BIT_MASK_USB_MBIST_DONE_V1 0x3 +#define BIT_USB_MBIST_DONE_V1(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE_V1) << BIT_SHIFT_USB_MBIST_DONE_V1) +#define BITS_USB_MBIST_DONE_V1 \ + (BIT_MASK_USB_MBIST_DONE_V1 << BIT_SHIFT_USB_MBIST_DONE_V1) +#define BIT_CLEAR_USB_MBIST_DONE_V1(x) ((x) & (~BITS_USB_MBIST_DONE_V1)) +#define BIT_GET_USB_MBIST_DONE_V1(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE_V1) & BIT_MASK_USB_MBIST_DONE_V1) +#define BIT_SET_USB_MBIST_DONE_V1(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE_V1(x) | BIT_USB_MBIST_DONE_V1(v)) + +#define BIT_SHIFT_PCIE_MBIST_DONE_V1 18 +#define BIT_MASK_PCIE_MBIST_DONE_V1 0x3f +#define BIT_PCIE_MBIST_DONE_V1(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE_V1) << BIT_SHIFT_PCIE_MBIST_DONE_V1) +#define BITS_PCIE_MBIST_DONE_V1 \ + (BIT_MASK_PCIE_MBIST_DONE_V1 << BIT_SHIFT_PCIE_MBIST_DONE_V1) +#define BIT_CLEAR_PCIE_MBIST_DONE_V1(x) ((x) & (~BITS_PCIE_MBIST_DONE_V1)) +#define BIT_GET_PCIE_MBIST_DONE_V1(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1) & BIT_MASK_PCIE_MBIST_DONE_V1) +#define BIT_SET_PCIE_MBIST_DONE_V1(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE_V1(x) | BIT_PCIE_MBIST_DONE_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MAC_MBIST_DONE 0 -#define BIT_MASK_MAC_MBIST_DONE 0xfff -#define BIT_MAC_MBIST_DONE(x) (((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE) -#define BIT_GET_MAC_MBIST_DONE(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE) +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_PCIE_MBIST_DONE 16 +#define BIT_MASK_PCIE_MBIST_DONE 0x3f +#define BIT_PCIE_MBIST_DONE(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE) +#define BITS_PCIE_MBIST_DONE \ + (BIT_MASK_PCIE_MBIST_DONE << BIT_SHIFT_PCIE_MBIST_DONE) +#define BIT_CLEAR_PCIE_MBIST_DONE(x) ((x) & (~BITS_PCIE_MBIST_DONE)) +#define BIT_GET_PCIE_MBIST_DONE(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE) +#define BIT_SET_PCIE_MBIST_DONE(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE(x) | BIT_PCIE_MBIST_DONE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_MAC_MBIST_DONE 0 +#define BIT_MASK_MAC_MBIST_DONE 0xfff +#define BIT_MAC_MBIST_DONE(x) \ + (((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE) +#define BITS_MAC_MBIST_DONE \ + (BIT_MASK_MAC_MBIST_DONE << BIT_SHIFT_MAC_MBIST_DONE) +#define BIT_CLEAR_MAC_MBIST_DONE(x) ((x) & (~BITS_MAC_MBIST_DONE)) +#define BIT_GET_MAC_MBIST_DONE(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE) +#define BIT_SET_MAC_MBIST_DONE(x, v) \ + (BIT_CLEAR_MAC_MBIST_DONE(x) | BIT_MAC_MBIST_DONE(v)) -/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MAC_MBIST_DONE_V1 0 -#define BIT_MASK_MAC_MBIST_DONE_V1 0x3ffff -#define BIT_MAC_MBIST_DONE_V1(x) (((x) & BIT_MASK_MAC_MBIST_DONE_V1) << BIT_SHIFT_MAC_MBIST_DONE_V1) -#define BIT_GET_MAC_MBIST_DONE_V1(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1) & BIT_MASK_MAC_MBIST_DONE_V1) +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_MAC_MBIST_DONE_V1 0 +#define BIT_MASK_MAC_MBIST_DONE_V1 0x3ffff +#define BIT_MAC_MBIST_DONE_V1(x) \ + (((x) & BIT_MASK_MAC_MBIST_DONE_V1) << BIT_SHIFT_MAC_MBIST_DONE_V1) +#define BITS_MAC_MBIST_DONE_V1 \ + (BIT_MASK_MAC_MBIST_DONE_V1 << BIT_SHIFT_MAC_MBIST_DONE_V1) +#define BIT_CLEAR_MAC_MBIST_DONE_V1(x) ((x) & (~BITS_MAC_MBIST_DONE_V1)) +#define BIT_GET_MAC_MBIST_DONE_V1(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1) & BIT_MASK_MAC_MBIST_DONE_V1) +#define BIT_SET_MAC_MBIST_DONE_V1(x, v) \ + (BIT_CLEAR_MAC_MBIST_DONE_V1(x) | BIT_MAC_MBIST_DONE_V1(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_MBIST_ROM_CRC_DATA (Offset 0x017C) */ - -#define BIT_SHIFT_MBIST_ROM_CRC_DATA 0 -#define BIT_MASK_MBIST_ROM_CRC_DATA 0xffffffffL -#define BIT_MBIST_ROM_CRC_DATA(x) (((x) & BIT_MASK_MBIST_ROM_CRC_DATA) << BIT_SHIFT_MBIST_ROM_CRC_DATA) -#define BIT_GET_MBIST_ROM_CRC_DATA(x) (((x) >> BIT_SHIFT_MBIST_ROM_CRC_DATA) & BIT_MASK_MBIST_ROM_CRC_DATA) - +#define BIT_SHIFT_MBIST_ROM_CRC_DATA 0 +#define BIT_MASK_MBIST_ROM_CRC_DATA 0xffffffffL +#define BIT_MBIST_ROM_CRC_DATA(x) \ + (((x) & BIT_MASK_MBIST_ROM_CRC_DATA) << BIT_SHIFT_MBIST_ROM_CRC_DATA) +#define BITS_MBIST_ROM_CRC_DATA \ + (BIT_MASK_MBIST_ROM_CRC_DATA << BIT_SHIFT_MBIST_ROM_CRC_DATA) +#define BIT_CLEAR_MBIST_ROM_CRC_DATA(x) ((x) & (~BITS_MBIST_ROM_CRC_DATA)) +#define BIT_GET_MBIST_ROM_CRC_DATA(x) \ + (((x) >> BIT_SHIFT_MBIST_ROM_CRC_DATA) & BIT_MASK_MBIST_ROM_CRC_DATA) +#define BIT_SET_MBIST_ROM_CRC_DATA(x, v) \ + (BIT_CLEAR_MBIST_ROM_CRC_DATA(x) | BIT_MBIST_ROM_CRC_DATA(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */ - -#define BIT_SHIFT_MBIST_FAIL_NRML_V1 0 -#define BIT_MASK_MBIST_FAIL_NRML_V1 0x3ffff -#define BIT_MBIST_FAIL_NRML_V1(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_V1) << BIT_SHIFT_MBIST_FAIL_NRML_V1) -#define BIT_GET_MBIST_FAIL_NRML_V1(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1) & BIT_MASK_MBIST_FAIL_NRML_V1) - +#define BIT_SHIFT_MBIST_FAIL_NRML_V1 0 +#define BIT_MASK_MBIST_FAIL_NRML_V1 0x3ffff +#define BIT_MBIST_FAIL_NRML_V1(x) \ + (((x) & BIT_MASK_MBIST_FAIL_NRML_V1) << BIT_SHIFT_MBIST_FAIL_NRML_V1) +#define BITS_MBIST_FAIL_NRML_V1 \ + (BIT_MASK_MBIST_FAIL_NRML_V1 << BIT_SHIFT_MBIST_FAIL_NRML_V1) +#define BIT_CLEAR_MBIST_FAIL_NRML_V1(x) ((x) & (~BITS_MBIST_FAIL_NRML_V1)) +#define BIT_GET_MBIST_FAIL_NRML_V1(x) \ + (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1) & BIT_MASK_MBIST_FAIL_NRML_V1) +#define BIT_SET_MBIST_FAIL_NRML_V1(x, v) \ + (BIT_CLEAR_MBIST_FAIL_NRML_V1(x) | BIT_MBIST_FAIL_NRML_V1(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */ +#define BIT_SHIFT_MBIST_FAIL_NRML 0 +#define BIT_MASK_MBIST_FAIL_NRML 0xffffffffL +#define BIT_MBIST_FAIL_NRML(x) \ + (((x) & BIT_MASK_MBIST_FAIL_NRML) << BIT_SHIFT_MBIST_FAIL_NRML) +#define BITS_MBIST_FAIL_NRML \ + (BIT_MASK_MBIST_FAIL_NRML << BIT_SHIFT_MBIST_FAIL_NRML) +#define BIT_CLEAR_MBIST_FAIL_NRML(x) ((x) & (~BITS_MBIST_FAIL_NRML)) +#define BIT_GET_MBIST_FAIL_NRML(x) \ + (((x) >> BIT_SHIFT_MBIST_FAIL_NRML) & BIT_MASK_MBIST_FAIL_NRML) +#define BIT_SET_MBIST_FAIL_NRML(x, v) \ + (BIT_CLEAR_MBIST_FAIL_NRML(x) | BIT_MBIST_FAIL_NRML(v)) + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) +#define BITS_R_WMAC_IPV6_MYIPAD \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD) +#define BIT_SET_R_WMAC_IPV6_MYIPAD(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD(x) | BIT_R_WMAC_IPV6_MYIPAD(v)) + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MBIST_READ_BIST_RPT (Offset 0x017C) */ + +#define BIT_SHIFT_MBIST_READ_BIST_RPT 0 +#define BIT_MASK_MBIST_READ_BIST_RPT 0xffffffffL +#define BIT_MBIST_READ_BIST_RPT(x) \ + (((x) & BIT_MASK_MBIST_READ_BIST_RPT) << BIT_SHIFT_MBIST_READ_BIST_RPT) +#define BITS_MBIST_READ_BIST_RPT \ + (BIT_MASK_MBIST_READ_BIST_RPT << BIT_SHIFT_MBIST_READ_BIST_RPT) +#define BIT_CLEAR_MBIST_READ_BIST_RPT(x) ((x) & (~BITS_MBIST_READ_BIST_RPT)) +#define BIT_GET_MBIST_READ_BIST_RPT(x) \ + (((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT) & BIT_MASK_MBIST_READ_BIST_RPT) +#define BIT_SET_MBIST_READ_BIST_RPT(x, v) \ + (BIT_CLEAR_MBIST_READ_BIST_RPT(x) | BIT_MBIST_READ_BIST_RPT(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */ +/* 2 REG_AES_DECRPT_DATA (Offset 0x0180) */ +#define BIT_SHIFT_IPS_CFG_ADDR 0 +#define BIT_MASK_IPS_CFG_ADDR 0xff +#define BIT_IPS_CFG_ADDR(x) \ + (((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR) +#define BITS_IPS_CFG_ADDR (BIT_MASK_IPS_CFG_ADDR << BIT_SHIFT_IPS_CFG_ADDR) +#define BIT_CLEAR_IPS_CFG_ADDR(x) ((x) & (~BITS_IPS_CFG_ADDR)) +#define BIT_GET_IPS_CFG_ADDR(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR) +#define BIT_SET_IPS_CFG_ADDR(x, v) \ + (BIT_CLEAR_IPS_CFG_ADDR(x) | BIT_IPS_CFG_ADDR(v)) -#define BIT_SHIFT_MBIST_FAIL_NRML 0 -#define BIT_MASK_MBIST_FAIL_NRML 0xffffffffL -#define BIT_MBIST_FAIL_NRML(x) (((x) & BIT_MASK_MBIST_FAIL_NRML) << BIT_SHIFT_MBIST_FAIL_NRML) -#define BIT_GET_MBIST_FAIL_NRML(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML) & BIT_MASK_MBIST_FAIL_NRML) +/* 2 REG_AES_DECRPT_CFG (Offset 0x0184) */ +#define BIT_SHIFT_IPS_CFG_DATA 0 +#define BIT_MASK_IPS_CFG_DATA 0xffffffffL +#define BIT_IPS_CFG_DATA(x) \ + (((x) & BIT_MASK_IPS_CFG_DATA) << BIT_SHIFT_IPS_CFG_DATA) +#define BITS_IPS_CFG_DATA (BIT_MASK_IPS_CFG_DATA << BIT_SHIFT_IPS_CFG_DATA) +#define BIT_CLEAR_IPS_CFG_DATA(x) ((x) & (~BITS_IPS_CFG_DATA)) +#define BIT_GET_IPS_CFG_DATA(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_DATA) & BIT_MASK_IPS_CFG_DATA) +#define BIT_SET_IPS_CFG_DATA(x, v) \ + (BIT_CLEAR_IPS_CFG_DATA(x) | BIT_IPS_CFG_DATA(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIOE_CTRL (Offset 0x0188) */ +#define BIT_HIOE_CFG_FILE_LOC_SEL BIT(31) -/* 2 REG_AES_DECRPT_DATA (Offset 0x0180) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_IPS_CFG_ADDR 0 -#define BIT_MASK_IPS_CFG_ADDR 0xff -#define BIT_IPS_CFG_ADDR(x) (((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR) -#define BIT_GET_IPS_CFG_ADDR(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR) +/* 2 REG_HIOE_CTRL (Offset 0x0188) */ +#define BIT_HIOE_WRITE_REQ BIT(30) +#define BIT_HIOE_READ_REQ BIT(29) +#define BIT_INST_FORMAT_ERR BIT(25) +#define BIT_OP_TIMEOUT_ERR BIT(24) -/* 2 REG_AES_DECRPT_CFG (Offset 0x0184) */ +#define BIT_SHIFT_HIOE_OP_TIMEOUT 16 +#define BIT_MASK_HIOE_OP_TIMEOUT 0xff +#define BIT_HIOE_OP_TIMEOUT(x) \ + (((x) & BIT_MASK_HIOE_OP_TIMEOUT) << BIT_SHIFT_HIOE_OP_TIMEOUT) +#define BITS_HIOE_OP_TIMEOUT \ + (BIT_MASK_HIOE_OP_TIMEOUT << BIT_SHIFT_HIOE_OP_TIMEOUT) +#define BIT_CLEAR_HIOE_OP_TIMEOUT(x) ((x) & (~BITS_HIOE_OP_TIMEOUT)) +#define BIT_GET_HIOE_OP_TIMEOUT(x) \ + (((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT) & BIT_MASK_HIOE_OP_TIMEOUT) +#define BIT_SET_HIOE_OP_TIMEOUT(x, v) \ + (BIT_CLEAR_HIOE_OP_TIMEOUT(x) | BIT_HIOE_OP_TIMEOUT(v)) +#define BIT_SHIFT_BITDATA_CHECKSUM 0 +#define BIT_MASK_BITDATA_CHECKSUM 0xffff +#define BIT_BITDATA_CHECKSUM(x) \ + (((x) & BIT_MASK_BITDATA_CHECKSUM) << BIT_SHIFT_BITDATA_CHECKSUM) +#define BITS_BITDATA_CHECKSUM \ + (BIT_MASK_BITDATA_CHECKSUM << BIT_SHIFT_BITDATA_CHECKSUM) +#define BIT_CLEAR_BITDATA_CHECKSUM(x) ((x) & (~BITS_BITDATA_CHECKSUM)) +#define BIT_GET_BITDATA_CHECKSUM(x) \ + (((x) >> BIT_SHIFT_BITDATA_CHECKSUM) & BIT_MASK_BITDATA_CHECKSUM) +#define BIT_SET_BITDATA_CHECKSUM(x, v) \ + (BIT_CLEAR_BITDATA_CHECKSUM(x) | BIT_BITDATA_CHECKSUM(v)) -#define BIT_SHIFT_IPS_CFG_DATA 0 -#define BIT_MASK_IPS_CFG_DATA 0xffffffffL -#define BIT_IPS_CFG_DATA(x) (((x) & BIT_MASK_IPS_CFG_DATA) << BIT_SHIFT_IPS_CFG_DATA) -#define BIT_GET_IPS_CFG_DATA(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA) & BIT_MASK_IPS_CFG_DATA) +/* 2 REG_HIOE_CFG_FILE (Offset 0x018C) */ +#define BIT_SHIFT_TXBF_END_ADDR 16 +#define BIT_MASK_TXBF_END_ADDR 0xffff +#define BIT_TXBF_END_ADDR(x) \ + (((x) & BIT_MASK_TXBF_END_ADDR) << BIT_SHIFT_TXBF_END_ADDR) +#define BITS_TXBF_END_ADDR (BIT_MASK_TXBF_END_ADDR << BIT_SHIFT_TXBF_END_ADDR) +#define BIT_CLEAR_TXBF_END_ADDR(x) ((x) & (~BITS_TXBF_END_ADDR)) +#define BIT_GET_TXBF_END_ADDR(x) \ + (((x) >> BIT_SHIFT_TXBF_END_ADDR) & BIT_MASK_TXBF_END_ADDR) +#define BIT_SET_TXBF_END_ADDR(x, v) \ + (BIT_CLEAR_TXBF_END_ADDR(x) | BIT_TXBF_END_ADDR(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_MACCLKFRQ (Offset 0x018C) */ +#define BIT_SHIFT_MACCLK_FREQ_LOW32 0 +#define BIT_MASK_MACCLK_FREQ_LOW32 0xffffffffL +#define BIT_MACCLK_FREQ_LOW32(x) \ + (((x) & BIT_MASK_MACCLK_FREQ_LOW32) << BIT_SHIFT_MACCLK_FREQ_LOW32) +#define BITS_MACCLK_FREQ_LOW32 \ + (BIT_MASK_MACCLK_FREQ_LOW32 << BIT_SHIFT_MACCLK_FREQ_LOW32) +#define BIT_CLEAR_MACCLK_FREQ_LOW32(x) ((x) & (~BITS_MACCLK_FREQ_LOW32)) +#define BIT_GET_MACCLK_FREQ_LOW32(x) \ + (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32) & BIT_MASK_MACCLK_FREQ_LOW32) +#define BIT_SET_MACCLK_FREQ_LOW32(x, v) \ + (BIT_CLEAR_MACCLK_FREQ_LOW32(x) | BIT_MACCLK_FREQ_LOW32(v)) -#define BIT_SHIFT_MACCLK_FREQ_LOW32 0 -#define BIT_MASK_MACCLK_FREQ_LOW32 0xffffffffL -#define BIT_MACCLK_FREQ_LOW32(x) (((x) & BIT_MASK_MACCLK_FREQ_LOW32) << BIT_SHIFT_MACCLK_FREQ_LOW32) -#define BIT_GET_MACCLK_FREQ_LOW32(x) (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32) & BIT_MASK_MACCLK_FREQ_LOW32) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HIOE_CFG_FILE (Offset 0x018C) */ +#define BIT_SHIFT_TXBF_STR_ADDR 0 +#define BIT_MASK_TXBF_STR_ADDR 0xffff +#define BIT_TXBF_STR_ADDR(x) \ + (((x) & BIT_MASK_TXBF_STR_ADDR) << BIT_SHIFT_TXBF_STR_ADDR) +#define BITS_TXBF_STR_ADDR (BIT_MASK_TXBF_STR_ADDR << BIT_SHIFT_TXBF_STR_ADDR) +#define BIT_CLEAR_TXBF_STR_ADDR(x) ((x) & (~BITS_TXBF_STR_ADDR)) +#define BIT_GET_TXBF_STR_ADDR(x) \ + (((x) >> BIT_SHIFT_TXBF_STR_ADDR) & BIT_MASK_TXBF_STR_ADDR) +#define BIT_SET_TXBF_STR_ADDR(x, v) \ + (BIT_CLEAR_TXBF_STR_ADDR(x) | BIT_TXBF_STR_ADDR(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TMETER (Offset 0x0190) */ -#define BIT_TEMP_VALID BIT(31) +#define BIT_TEMP_VALID BIT(31) -#define BIT_SHIFT_TEMP_VALUE 24 -#define BIT_MASK_TEMP_VALUE 0x3f -#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE) -#define BIT_GET_TEMP_VALUE(x) (((x) >> BIT_SHIFT_TEMP_VALUE) & BIT_MASK_TEMP_VALUE) +#define BIT_SHIFT_TEMP_VALUE 24 +#define BIT_MASK_TEMP_VALUE 0x3f +#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE) +#define BITS_TEMP_VALUE (BIT_MASK_TEMP_VALUE << BIT_SHIFT_TEMP_VALUE) +#define BIT_CLEAR_TEMP_VALUE(x) ((x) & (~BITS_TEMP_VALUE)) +#define BIT_GET_TEMP_VALUE(x) \ + (((x) >> BIT_SHIFT_TEMP_VALUE) & BIT_MASK_TEMP_VALUE) +#define BIT_SET_TEMP_VALUE(x, v) (BIT_CLEAR_TEMP_VALUE(x) | BIT_TEMP_VALUE(v)) +#endif -#define BIT_SHIFT_REG_TMETER_TIMER 8 -#define BIT_MASK_REG_TMETER_TIMER 0xfff -#define BIT_REG_TMETER_TIMER(x) (((x) & BIT_MASK_REG_TMETER_TIMER) << BIT_SHIFT_REG_TMETER_TIMER) -#define BIT_GET_REG_TMETER_TIMER(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER) & BIT_MASK_REG_TMETER_TIMER) - +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_REG_TEMP_DELTA 2 -#define BIT_MASK_REG_TEMP_DELTA 0x3f -#define BIT_REG_TEMP_DELTA(x) (((x) & BIT_MASK_REG_TEMP_DELTA) << BIT_SHIFT_REG_TEMP_DELTA) -#define BIT_GET_REG_TEMP_DELTA(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA) & BIT_MASK_REG_TEMP_DELTA) +/* 2 REG_TMETER (Offset 0x0190) */ -#define BIT_REG_TMETER_EN BIT(0) +#define BIT_SHIFT_NCO_OUTCLK_FREQ 12 +#define BIT_MASK_NCO_OUTCLK_FREQ 0xfffff +#define BIT_NCO_OUTCLK_FREQ(x) \ + (((x) & BIT_MASK_NCO_OUTCLK_FREQ) << BIT_SHIFT_NCO_OUTCLK_FREQ) +#define BITS_NCO_OUTCLK_FREQ \ + (BIT_MASK_NCO_OUTCLK_FREQ << BIT_SHIFT_NCO_OUTCLK_FREQ) +#define BIT_CLEAR_NCO_OUTCLK_FREQ(x) ((x) & (~BITS_NCO_OUTCLK_FREQ)) +#define BIT_GET_NCO_OUTCLK_FREQ(x) \ + (((x) >> BIT_SHIFT_NCO_OUTCLK_FREQ) & BIT_MASK_NCO_OUTCLK_FREQ) +#define BIT_SET_NCO_OUTCLK_FREQ(x, v) \ + (BIT_CLEAR_NCO_OUTCLK_FREQ(x) | BIT_NCO_OUTCLK_FREQ(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TMETER (Offset 0x0190) */ +#define BIT_SHIFT_REG_TMETER_TIMER 8 +#define BIT_MASK_REG_TMETER_TIMER 0xfff +#define BIT_REG_TMETER_TIMER(x) \ + (((x) & BIT_MASK_REG_TMETER_TIMER) << BIT_SHIFT_REG_TMETER_TIMER) +#define BITS_REG_TMETER_TIMER \ + (BIT_MASK_REG_TMETER_TIMER << BIT_SHIFT_REG_TMETER_TIMER) +#define BIT_CLEAR_REG_TMETER_TIMER(x) ((x) & (~BITS_REG_TMETER_TIMER)) +#define BIT_GET_REG_TMETER_TIMER(x) \ + (((x) >> BIT_SHIFT_REG_TMETER_TIMER) & BIT_MASK_REG_TMETER_TIMER) +#define BIT_SET_REG_TMETER_TIMER(x, v) \ + (BIT_CLEAR_REG_TMETER_TIMER(x) | BIT_REG_TMETER_TIMER(v)) -#define BIT_SHIFT_MACCLK_FREQ_HIGH10 0 -#define BIT_MASK_MACCLK_FREQ_HIGH10 0x3ff -#define BIT_MACCLK_FREQ_HIGH10(x) (((x) & BIT_MASK_MACCLK_FREQ_HIGH10) << BIT_SHIFT_MACCLK_FREQ_HIGH10) -#define BIT_GET_MACCLK_FREQ_HIGH10(x) (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10) & BIT_MASK_MACCLK_FREQ_HIGH10) +#define BIT_SHIFT_REG_TEMP_DELTA 2 +#define BIT_MASK_REG_TEMP_DELTA 0x3f +#define BIT_REG_TEMP_DELTA(x) \ + (((x) & BIT_MASK_REG_TEMP_DELTA) << BIT_SHIFT_REG_TEMP_DELTA) +#define BITS_REG_TEMP_DELTA \ + (BIT_MASK_REG_TEMP_DELTA << BIT_SHIFT_REG_TEMP_DELTA) +#define BIT_CLEAR_REG_TEMP_DELTA(x) ((x) & (~BITS_REG_TEMP_DELTA)) +#define BIT_GET_REG_TEMP_DELTA(x) \ + (((x) >> BIT_SHIFT_REG_TEMP_DELTA) & BIT_MASK_REG_TEMP_DELTA) +#define BIT_SET_REG_TEMP_DELTA(x, v) \ + (BIT_CLEAR_REG_TEMP_DELTA(x) | BIT_REG_TEMP_DELTA(v)) +#define BIT_REG_TMETER_EN BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TMETER (Offset 0x0190) */ +#define BIT_SHIFT_MACCLK_FREQ_HIGH10 0 +#define BIT_MASK_MACCLK_FREQ_HIGH10 0x3ff +#define BIT_MACCLK_FREQ_HIGH10(x) \ + (((x) & BIT_MASK_MACCLK_FREQ_HIGH10) << BIT_SHIFT_MACCLK_FREQ_HIGH10) +#define BITS_MACCLK_FREQ_HIGH10 \ + (BIT_MASK_MACCLK_FREQ_HIGH10 << BIT_SHIFT_MACCLK_FREQ_HIGH10) +#define BIT_CLEAR_MACCLK_FREQ_HIGH10(x) ((x) & (~BITS_MACCLK_FREQ_HIGH10)) +#define BIT_GET_MACCLK_FREQ_HIGH10(x) \ + (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10) & BIT_MASK_MACCLK_FREQ_HIGH10) +#define BIT_SET_MACCLK_FREQ_HIGH10(x, v) \ + (BIT_CLEAR_MACCLK_FREQ_HIGH10(x) | BIT_MACCLK_FREQ_HIGH10(v)) -/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_OSC_32K_CLKGEN_0 16 -#define BIT_MASK_OSC_32K_CLKGEN_0 0xffff -#define BIT_OSC_32K_CLKGEN_0(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0) << BIT_SHIFT_OSC_32K_CLKGEN_0) -#define BIT_GET_OSC_32K_CLKGEN_0(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0) & BIT_MASK_OSC_32K_CLKGEN_0) +/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +#define BIT_SHIFT_OSC_32K_CLKGEN_0 16 +#define BIT_MASK_OSC_32K_CLKGEN_0 0xffff +#define BIT_OSC_32K_CLKGEN_0(x) \ + (((x) & BIT_MASK_OSC_32K_CLKGEN_0) << BIT_SHIFT_OSC_32K_CLKGEN_0) +#define BITS_OSC_32K_CLKGEN_0 \ + (BIT_MASK_OSC_32K_CLKGEN_0 << BIT_SHIFT_OSC_32K_CLKGEN_0) +#define BIT_CLEAR_OSC_32K_CLKGEN_0(x) ((x) & (~BITS_OSC_32K_CLKGEN_0)) +#define BIT_GET_OSC_32K_CLKGEN_0(x) \ + (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0) & BIT_MASK_OSC_32K_CLKGEN_0) +#define BIT_SET_OSC_32K_CLKGEN_0(x, v) \ + (BIT_CLEAR_OSC_32K_CLKGEN_0(x) | BIT_OSC_32K_CLKGEN_0(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ -#define BIT_32K_CLK_OUT_RDY BIT(12) - -#define BIT_SHIFT_MONITOR_CYCLE_LOG2 8 -#define BIT_MASK_MONITOR_CYCLE_LOG2 0xf -#define BIT_MONITOR_CYCLE_LOG2(x) (((x) & BIT_MASK_MONITOR_CYCLE_LOG2) << BIT_SHIFT_MONITOR_CYCLE_LOG2) -#define BIT_GET_MONITOR_CYCLE_LOG2(x) (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2) & BIT_MASK_MONITOR_CYCLE_LOG2) +#define BIT_32K_CLK_OUT_RDY BIT(12) +#define BIT_SHIFT_MONITOR_CYCLE_LOG2 8 +#define BIT_MASK_MONITOR_CYCLE_LOG2 0xf +#define BIT_MONITOR_CYCLE_LOG2(x) \ + (((x) & BIT_MASK_MONITOR_CYCLE_LOG2) << BIT_SHIFT_MONITOR_CYCLE_LOG2) +#define BITS_MONITOR_CYCLE_LOG2 \ + (BIT_MASK_MONITOR_CYCLE_LOG2 << BIT_SHIFT_MONITOR_CYCLE_LOG2) +#define BIT_CLEAR_MONITOR_CYCLE_LOG2(x) ((x) & (~BITS_MONITOR_CYCLE_LOG2)) +#define BIT_GET_MONITOR_CYCLE_LOG2(x) \ + (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2) & BIT_MASK_MONITOR_CYCLE_LOG2) +#define BIT_SET_MONITOR_CYCLE_LOG2(x, v) \ + (BIT_CLEAR_MONITOR_CYCLE_LOG2(x) | BIT_MONITOR_CYCLE_LOG2(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +#define BIT_SHIFT_OSC_32K_RES_COMP 4 +#define BIT_MASK_OSC_32K_RES_COMP 0x3 +#define BIT_OSC_32K_RES_COMP(x) \ + (((x) & BIT_MASK_OSC_32K_RES_COMP) << BIT_SHIFT_OSC_32K_RES_COMP) +#define BITS_OSC_32K_RES_COMP \ + (BIT_MASK_OSC_32K_RES_COMP << BIT_SHIFT_OSC_32K_RES_COMP) +#define BIT_CLEAR_OSC_32K_RES_COMP(x) ((x) & (~BITS_OSC_32K_RES_COMP)) +#define BIT_GET_OSC_32K_RES_COMP(x) \ + (((x) >> BIT_SHIFT_OSC_32K_RES_COMP) & BIT_MASK_OSC_32K_RES_COMP) +#define BIT_SET_OSC_32K_RES_COMP(x, v) \ + (BIT_CLEAR_OSC_32K_RES_COMP(x) | BIT_OSC_32K_RES_COMP(v)) -#define BIT_SHIFT_OSC_32K_RES_COMP 4 -#define BIT_MASK_OSC_32K_RES_COMP 0x3 -#define BIT_OSC_32K_RES_COMP(x) (((x) & BIT_MASK_OSC_32K_RES_COMP) << BIT_SHIFT_OSC_32K_RES_COMP) -#define BIT_GET_OSC_32K_RES_COMP(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP) & BIT_MASK_OSC_32K_RES_COMP) - -#define BIT_OSC_32K_OUT_SEL BIT(3) +#define BIT_OSC_32K_OUT_SEL BIT(3) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ -#define BIT_ISO_WL_2_OSC_32K BIT(1) +#define BIT_ISO_WL_2_OSC_32K BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ -#define BIT_POW_CKGEN BIT(0) +#define BIT_POW_CKGEN BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ -#define BIT_CAL_32K_REG_WR BIT(31) -#define BIT_CAL_32K_DBG_SEL BIT(22) - -#define BIT_SHIFT_CAL_32K_REG_ADDR 16 -#define BIT_MASK_CAL_32K_REG_ADDR 0x3f -#define BIT_CAL_32K_REG_ADDR(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR) << BIT_SHIFT_CAL_32K_REG_ADDR) -#define BIT_GET_CAL_32K_REG_ADDR(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR) & BIT_MASK_CAL_32K_REG_ADDR) +#define BIT_CAL_32K_REG_WR BIT(31) +#define BIT_CAL_32K_DBG_SEL BIT(22) +#define BIT_SHIFT_CAL_32K_REG_ADDR 16 +#define BIT_MASK_CAL_32K_REG_ADDR 0x3f +#define BIT_CAL_32K_REG_ADDR(x) \ + (((x) & BIT_MASK_CAL_32K_REG_ADDR) << BIT_SHIFT_CAL_32K_REG_ADDR) +#define BITS_CAL_32K_REG_ADDR \ + (BIT_MASK_CAL_32K_REG_ADDR << BIT_SHIFT_CAL_32K_REG_ADDR) +#define BIT_CLEAR_CAL_32K_REG_ADDR(x) ((x) & (~BITS_CAL_32K_REG_ADDR)) +#define BIT_GET_CAL_32K_REG_ADDR(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR) & BIT_MASK_CAL_32K_REG_ADDR) +#define BIT_SET_CAL_32K_REG_ADDR(x, v) \ + (BIT_CLEAR_CAL_32K_REG_ADDR(x) | BIT_CAL_32K_REG_ADDR(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ +#define BIT_SHIFT_FREQVALUE_UNREGCLK 8 +#define BIT_MASK_FREQVALUE_UNREGCLK 0xffffff +#define BIT_FREQVALUE_UNREGCLK(x) \ + (((x) & BIT_MASK_FREQVALUE_UNREGCLK) << BIT_SHIFT_FREQVALUE_UNREGCLK) +#define BITS_FREQVALUE_UNREGCLK \ + (BIT_MASK_FREQVALUE_UNREGCLK << BIT_SHIFT_FREQVALUE_UNREGCLK) +#define BIT_CLEAR_FREQVALUE_UNREGCLK(x) ((x) & (~BITS_FREQVALUE_UNREGCLK)) +#define BIT_GET_FREQVALUE_UNREGCLK(x) \ + (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK) & BIT_MASK_FREQVALUE_UNREGCLK) +#define BIT_SET_FREQVALUE_UNREGCLK(x, v) \ + (BIT_CLEAR_FREQVALUE_UNREGCLK(x) | BIT_FREQVALUE_UNREGCLK(v)) -#define BIT_SHIFT_FREQVALUE_UNREGCLK 8 -#define BIT_MASK_FREQVALUE_UNREGCLK 0xffffff -#define BIT_FREQVALUE_UNREGCLK(x) (((x) & BIT_MASK_FREQVALUE_UNREGCLK) << BIT_SHIFT_FREQVALUE_UNREGCLK) -#define BIT_GET_FREQVALUE_UNREGCLK(x) (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK) & BIT_MASK_FREQVALUE_UNREGCLK) - -#define BIT_CAL32K_DBGMOD BIT(7) +#define BIT_CAL32K_DBGMOD BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ - -#define BIT_SHIFT_CAL_32K_REG_DATA 0 -#define BIT_MASK_CAL_32K_REG_DATA 0xffff -#define BIT_CAL_32K_REG_DATA(x) (((x) & BIT_MASK_CAL_32K_REG_DATA) << BIT_SHIFT_CAL_32K_REG_DATA) -#define BIT_GET_CAL_32K_REG_DATA(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA) & BIT_MASK_CAL_32K_REG_DATA) - +#define BIT_SHIFT_CAL_32K_REG_DATA 0 +#define BIT_MASK_CAL_32K_REG_DATA 0xffff +#define BIT_CAL_32K_REG_DATA(x) \ + (((x) & BIT_MASK_CAL_32K_REG_DATA) << BIT_SHIFT_CAL_32K_REG_DATA) +#define BITS_CAL_32K_REG_DATA \ + (BIT_MASK_CAL_32K_REG_DATA << BIT_SHIFT_CAL_32K_REG_DATA) +#define BIT_CLEAR_CAL_32K_REG_DATA(x) ((x) & (~BITS_CAL_32K_REG_DATA)) +#define BIT_GET_CAL_32K_REG_DATA(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_DATA) & BIT_MASK_CAL_32K_REG_DATA) +#define BIT_SET_CAL_32K_REG_DATA(x, v) \ + (BIT_CLEAR_CAL_32K_REG_DATA(x) | BIT_CAL_32K_REG_DATA(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ - -#define BIT_SHIFT_NCO_THRS 0 -#define BIT_MASK_NCO_THRS 0x7f -#define BIT_NCO_THRS(x) (((x) & BIT_MASK_NCO_THRS) << BIT_SHIFT_NCO_THRS) -#define BIT_GET_NCO_THRS(x) (((x) >> BIT_SHIFT_NCO_THRS) & BIT_MASK_NCO_THRS) - +#define BIT_SHIFT_NCO_THRS 0 +#define BIT_MASK_NCO_THRS 0x7f +#define BIT_NCO_THRS(x) (((x) & BIT_MASK_NCO_THRS) << BIT_SHIFT_NCO_THRS) +#define BITS_NCO_THRS (BIT_MASK_NCO_THRS << BIT_SHIFT_NCO_THRS) +#define BIT_CLEAR_NCO_THRS(x) ((x) & (~BITS_NCO_THRS)) +#define BIT_GET_NCO_THRS(x) (((x) >> BIT_SHIFT_NCO_THRS) & BIT_MASK_NCO_THRS) +#define BIT_SET_NCO_THRS(x, v) (BIT_CLEAR_NCO_THRS(x) | BIT_NCO_THRS(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_C2HEVT (Offset 0x01A0) */ - -#define BIT_SHIFT_C2HEVT_MSG 0 -#define BIT_MASK_C2HEVT_MSG 0xffffffffffffffffffffffffffffffffL -#define BIT_C2HEVT_MSG(x) (((x) & BIT_MASK_C2HEVT_MSG) << BIT_SHIFT_C2HEVT_MSG) -#define BIT_GET_C2HEVT_MSG(x) (((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG) - +#define BIT_SHIFT_C2HEVT_MSG 0 +#define BIT_MASK_C2HEVT_MSG 0xffffffffffffffffffffffffffffffffL +#define BIT_C2HEVT_MSG(x) (((x) & BIT_MASK_C2HEVT_MSG) << BIT_SHIFT_C2HEVT_MSG) +#define BITS_C2HEVT_MSG (BIT_MASK_C2HEVT_MSG << BIT_SHIFT_C2HEVT_MSG) +#define BIT_CLEAR_C2HEVT_MSG(x) ((x) & (~BITS_C2HEVT_MSG)) +#define BIT_GET_C2HEVT_MSG(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG) +#define BIT_SET_C2HEVT_MSG(x, v) (BIT_CLEAR_C2HEVT_MSG(x) | BIT_C2HEVT_MSG(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_C2HEVT (Offset 0x01A0) */ - -#define BIT_SHIFT_C2HEVT_MSG_V1 0 -#define BIT_MASK_C2HEVT_MSG_V1 0xffffffffL -#define BIT_C2HEVT_MSG_V1(x) (((x) & BIT_MASK_C2HEVT_MSG_V1) << BIT_SHIFT_C2HEVT_MSG_V1) -#define BIT_GET_C2HEVT_MSG_V1(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_V1) & BIT_MASK_C2HEVT_MSG_V1) - +#define BIT_SHIFT_C2HEVT_MSG_V1 0 +#define BIT_MASK_C2HEVT_MSG_V1 0xffffffffL +#define BIT_C2HEVT_MSG_V1(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_V1) << BIT_SHIFT_C2HEVT_MSG_V1) +#define BITS_C2HEVT_MSG_V1 (BIT_MASK_C2HEVT_MSG_V1 << BIT_SHIFT_C2HEVT_MSG_V1) +#define BIT_CLEAR_C2HEVT_MSG_V1(x) ((x) & (~BITS_C2HEVT_MSG_V1)) +#define BIT_GET_C2HEVT_MSG_V1(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_V1) & BIT_MASK_C2HEVT_MSG_V1) +#define BIT_SET_C2HEVT_MSG_V1(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_V1(x) | BIT_C2HEVT_MSG_V1(v)) /* 2 REG_C2HEVT_1 (Offset 0x01A4) */ - -#define BIT_SHIFT_C2HEVT_MSG_1 0 -#define BIT_MASK_C2HEVT_MSG_1 0xffffffffL -#define BIT_C2HEVT_MSG_1(x) (((x) & BIT_MASK_C2HEVT_MSG_1) << BIT_SHIFT_C2HEVT_MSG_1) -#define BIT_GET_C2HEVT_MSG_1(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_1) & BIT_MASK_C2HEVT_MSG_1) - +#define BIT_SHIFT_C2HEVT_MSG_1 0 +#define BIT_MASK_C2HEVT_MSG_1 0xffffffffL +#define BIT_C2HEVT_MSG_1(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_1) << BIT_SHIFT_C2HEVT_MSG_1) +#define BITS_C2HEVT_MSG_1 (BIT_MASK_C2HEVT_MSG_1 << BIT_SHIFT_C2HEVT_MSG_1) +#define BIT_CLEAR_C2HEVT_MSG_1(x) ((x) & (~BITS_C2HEVT_MSG_1)) +#define BIT_GET_C2HEVT_MSG_1(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_1) & BIT_MASK_C2HEVT_MSG_1) +#define BIT_SET_C2HEVT_MSG_1(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_1(x) | BIT_C2HEVT_MSG_1(v)) /* 2 REG_C2HEVT_2 (Offset 0x01A8) */ - -#define BIT_SHIFT_C2HEVT_MSG_2 0 -#define BIT_MASK_C2HEVT_MSG_2 0xffffffffL -#define BIT_C2HEVT_MSG_2(x) (((x) & BIT_MASK_C2HEVT_MSG_2) << BIT_SHIFT_C2HEVT_MSG_2) -#define BIT_GET_C2HEVT_MSG_2(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_2) & BIT_MASK_C2HEVT_MSG_2) - +#define BIT_SHIFT_C2HEVT_MSG_2 0 +#define BIT_MASK_C2HEVT_MSG_2 0xffffffffL +#define BIT_C2HEVT_MSG_2(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_2) << BIT_SHIFT_C2HEVT_MSG_2) +#define BITS_C2HEVT_MSG_2 (BIT_MASK_C2HEVT_MSG_2 << BIT_SHIFT_C2HEVT_MSG_2) +#define BIT_CLEAR_C2HEVT_MSG_2(x) ((x) & (~BITS_C2HEVT_MSG_2)) +#define BIT_GET_C2HEVT_MSG_2(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_2) & BIT_MASK_C2HEVT_MSG_2) +#define BIT_SET_C2HEVT_MSG_2(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_2(x) | BIT_C2HEVT_MSG_2(v)) /* 2 REG_C2HEVT_3 (Offset 0x01AC) */ - -#define BIT_SHIFT_C2HEVT_MSG_3 0 -#define BIT_MASK_C2HEVT_MSG_3 0xffffffffL -#define BIT_C2HEVT_MSG_3(x) (((x) & BIT_MASK_C2HEVT_MSG_3) << BIT_SHIFT_C2HEVT_MSG_3) -#define BIT_GET_C2HEVT_MSG_3(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_3) & BIT_MASK_C2HEVT_MSG_3) - +#define BIT_SHIFT_C2HEVT_MSG_3 0 +#define BIT_MASK_C2HEVT_MSG_3 0xffffffffL +#define BIT_C2HEVT_MSG_3(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_3) << BIT_SHIFT_C2HEVT_MSG_3) +#define BITS_C2HEVT_MSG_3 (BIT_MASK_C2HEVT_MSG_3 << BIT_SHIFT_C2HEVT_MSG_3) +#define BIT_CLEAR_C2HEVT_MSG_3(x) ((x) & (~BITS_C2HEVT_MSG_3)) +#define BIT_GET_C2HEVT_MSG_3(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_3) & BIT_MASK_C2HEVT_MSG_3) +#define BIT_SET_C2HEVT_MSG_3(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_3(x) | BIT_C2HEVT_MSG_3(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TC7_CTRL (Offset 0x01B0) */ +#define BIT_TC7INT_EN BIT(26) +#define BIT_TC7MODE BIT(25) +#define BIT_TC7EN BIT(24) -/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ +#define BIT_SHIFT_TC7DATA 0 +#define BIT_MASK_TC7DATA 0xffffff +#define BIT_TC7DATA(x) (((x) & BIT_MASK_TC7DATA) << BIT_SHIFT_TC7DATA) +#define BITS_TC7DATA (BIT_MASK_TC7DATA << BIT_SHIFT_TC7DATA) +#define BIT_CLEAR_TC7DATA(x) ((x) & (~BITS_TC7DATA)) +#define BIT_GET_TC7DATA(x) (((x) >> BIT_SHIFT_TC7DATA) & BIT_MASK_TC7DATA) +#define BIT_SET_TC7DATA(x, v) (BIT_CLEAR_TC7DATA(x) | BIT_TC7DATA(v)) + +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_SW_DEFINED_PAGE1 0 -#define BIT_MASK_SW_DEFINED_PAGE1 0xffffffffffffffffL -#define BIT_SW_DEFINED_PAGE1(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1) << BIT_SHIFT_SW_DEFINED_PAGE1) -#define BIT_GET_SW_DEFINED_PAGE1(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1) +/* 2 REG_RXDESC_BUFF_RPTR (Offset 0x01B0) */ +#define BIT_SHIFT_RXDESC_BUFF_RPTR 0 +#define BIT_MASK_RXDESC_BUFF_RPTR 0xffffffffL +#define BIT_RXDESC_BUFF_RPTR(x) \ + (((x) & BIT_MASK_RXDESC_BUFF_RPTR) << BIT_SHIFT_RXDESC_BUFF_RPTR) +#define BITS_RXDESC_BUFF_RPTR \ + (BIT_MASK_RXDESC_BUFF_RPTR << BIT_SHIFT_RXDESC_BUFF_RPTR) +#define BIT_CLEAR_RXDESC_BUFF_RPTR(x) ((x) & (~BITS_RXDESC_BUFF_RPTR)) +#define BIT_GET_RXDESC_BUFF_RPTR(x) \ + (((x) >> BIT_SHIFT_RXDESC_BUFF_RPTR) & BIT_MASK_RXDESC_BUFF_RPTR) +#define BIT_SET_RXDESC_BUFF_RPTR(x, v) \ + (BIT_CLEAR_RXDESC_BUFF_RPTR(x) | BIT_RXDESC_BUFF_RPTR(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_TC8_CTRL (Offset 0x01B4) */ +#define BIT_TC8INT_EN BIT(26) +#define BIT_TC8MODE BIT(25) +#define BIT_TC8EN BIT(24) -/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ +#define BIT_SHIFT_TC8DATA 0 +#define BIT_MASK_TC8DATA 0xffffff +#define BIT_TC8DATA(x) (((x) & BIT_MASK_TC8DATA) << BIT_SHIFT_TC8DATA) +#define BITS_TC8DATA (BIT_MASK_TC8DATA << BIT_SHIFT_TC8DATA) +#define BIT_CLEAR_TC8DATA(x) ((x) & (~BITS_TC8DATA)) +#define BIT_GET_TC8DATA(x) (((x) >> BIT_SHIFT_TC8DATA) & BIT_MASK_TC8DATA) +#define BIT_SET_TC8DATA(x, v) (BIT_CLEAR_TC8DATA(x) | BIT_TC8DATA(v)) +#endif -#define BIT_SHIFT_SW_DEFINED_PAGE1_V1 0 -#define BIT_MASK_SW_DEFINED_PAGE1_V1 0xffffffffL -#define BIT_SW_DEFINED_PAGE1_V1(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1) << BIT_SHIFT_SW_DEFINED_PAGE1_V1) -#define BIT_GET_SW_DEFINED_PAGE1_V1(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1) & BIT_MASK_SW_DEFINED_PAGE1_V1) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_RXDESC_BUFF_WPTR (Offset 0x01B4) */ -/* 2 REG_SW_DEFINED_PAGE2 (Offset 0x01BC) */ +#define BIT_SHIFT_RXDESC_BUFF_WPTR 0 +#define BIT_MASK_RXDESC_BUFF_WPTR 0xffffffffL +#define BIT_RXDESC_BUFF_WPTR(x) \ + (((x) & BIT_MASK_RXDESC_BUFF_WPTR) << BIT_SHIFT_RXDESC_BUFF_WPTR) +#define BITS_RXDESC_BUFF_WPTR \ + (BIT_MASK_RXDESC_BUFF_WPTR << BIT_SHIFT_RXDESC_BUFF_WPTR) +#define BIT_CLEAR_RXDESC_BUFF_WPTR(x) ((x) & (~BITS_RXDESC_BUFF_WPTR)) +#define BIT_GET_RXDESC_BUFF_WPTR(x) \ + (((x) >> BIT_SHIFT_RXDESC_BUFF_WPTR) & BIT_MASK_RXDESC_BUFF_WPTR) +#define BIT_SET_RXDESC_BUFF_WPTR(x, v) \ + (BIT_CLEAR_RXDESC_BUFF_WPTR(x) | BIT_RXDESC_BUFF_WPTR(v)) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SW_DEFINED_PAGE2 0 -#define BIT_MASK_SW_DEFINED_PAGE2 0xffffffffL -#define BIT_SW_DEFINED_PAGE2(x) (((x) & BIT_MASK_SW_DEFINED_PAGE2) << BIT_SHIFT_SW_DEFINED_PAGE2) -#define BIT_GET_SW_DEFINED_PAGE2(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2) & BIT_MASK_SW_DEFINED_PAGE2) +/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ +#define BIT_SHIFT_SW_DEFINED_PAGE1 0 +#define BIT_MASK_SW_DEFINED_PAGE1 0xffffffffffffffffL +#define BIT_SW_DEFINED_PAGE1(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1) << BIT_SHIFT_SW_DEFINED_PAGE1) +#define BITS_SW_DEFINED_PAGE1 \ + (BIT_MASK_SW_DEFINED_PAGE1 << BIT_SHIFT_SW_DEFINED_PAGE1) +#define BIT_CLEAR_SW_DEFINED_PAGE1(x) ((x) & (~BITS_SW_DEFINED_PAGE1)) +#define BIT_GET_SW_DEFINED_PAGE1(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1) +#define BIT_SET_SW_DEFINED_PAGE1(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1(x) | BIT_SW_DEFINED_PAGE1(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ +#define BIT_SHIFT_SW_DEFINED_PAGE1_V1 0 +#define BIT_MASK_SW_DEFINED_PAGE1_V1 0xffffffffL +#define BIT_SW_DEFINED_PAGE1_V1(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1) << BIT_SHIFT_SW_DEFINED_PAGE1_V1) +#define BITS_SW_DEFINED_PAGE1_V1 \ + (BIT_MASK_SW_DEFINED_PAGE1_V1 << BIT_SHIFT_SW_DEFINED_PAGE1_V1) +#define BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) ((x) & (~BITS_SW_DEFINED_PAGE1_V1)) +#define BIT_GET_SW_DEFINED_PAGE1_V1(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1) & BIT_MASK_SW_DEFINED_PAGE1_V1) +#define BIT_SET_SW_DEFINED_PAGE1_V1(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) | BIT_SW_DEFINED_PAGE1_V1(v)) -/* 2 REG_MCUTST_I (Offset 0x01C0) */ +/* 2 REG_SW_DEFINED_PAGE2 (Offset 0x01BC) */ +#define BIT_SHIFT_SW_DEFINED_PAGE2 0 +#define BIT_MASK_SW_DEFINED_PAGE2 0xffffffffL +#define BIT_SW_DEFINED_PAGE2(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE2) << BIT_SHIFT_SW_DEFINED_PAGE2) +#define BITS_SW_DEFINED_PAGE2 \ + (BIT_MASK_SW_DEFINED_PAGE2 << BIT_SHIFT_SW_DEFINED_PAGE2) +#define BIT_CLEAR_SW_DEFINED_PAGE2(x) ((x) & (~BITS_SW_DEFINED_PAGE2)) +#define BIT_GET_SW_DEFINED_PAGE2(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2) & BIT_MASK_SW_DEFINED_PAGE2) +#define BIT_SET_SW_DEFINED_PAGE2(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE2(x) | BIT_SW_DEFINED_PAGE2(v)) -#define BIT_SHIFT_MCUDMSG_I 0 -#define BIT_MASK_MCUDMSG_I 0xffffffffL -#define BIT_MCUDMSG_I(x) (((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I) -#define BIT_GET_MCUDMSG_I(x) (((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_MCUTST_II (Offset 0x01C4) */ +/* 2 REG_MCUTST_I (Offset 0x01C0) */ +#define BIT_SHIFT_MCUDMSG_I 0 +#define BIT_MASK_MCUDMSG_I 0xffffffffL +#define BIT_MCUDMSG_I(x) (((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I) +#define BITS_MCUDMSG_I (BIT_MASK_MCUDMSG_I << BIT_SHIFT_MCUDMSG_I) +#define BIT_CLEAR_MCUDMSG_I(x) ((x) & (~BITS_MCUDMSG_I)) +#define BIT_GET_MCUDMSG_I(x) (((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I) +#define BIT_SET_MCUDMSG_I(x, v) (BIT_CLEAR_MCUDMSG_I(x) | BIT_MCUDMSG_I(v)) -#define BIT_SHIFT_MCUDMSG_II 0 -#define BIT_MASK_MCUDMSG_II 0xffffffffL -#define BIT_MCUDMSG_II(x) (((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II) -#define BIT_GET_MCUDMSG_II(x) (((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II) +/* 2 REG_MCUTST_II (Offset 0x01C4) */ +#define BIT_SHIFT_MCUDMSG_II 0 +#define BIT_MASK_MCUDMSG_II 0xffffffffL +#define BIT_MCUDMSG_II(x) (((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II) +#define BITS_MCUDMSG_II (BIT_MASK_MCUDMSG_II << BIT_SHIFT_MCUDMSG_II) +#define BIT_CLEAR_MCUDMSG_II(x) ((x) & (~BITS_MCUDMSG_II)) +#define BIT_GET_MCUDMSG_II(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II) +#define BIT_SET_MCUDMSG_II(x, v) (BIT_CLEAR_MCUDMSG_II(x) | BIT_MCUDMSG_II(v)) /* 2 REG_FMETHR (Offset 0x01C8) */ -#define BIT_FMSG_INT BIT(31) - -#define BIT_SHIFT_FW_MSG 0 -#define BIT_MASK_FW_MSG 0xffffffffL -#define BIT_FW_MSG(x) (((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG) -#define BIT_GET_FW_MSG(x) (((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG) +#define BIT_FMSG_INT BIT(31) +#define BIT_SHIFT_FW_MSG 0 +#define BIT_MASK_FW_MSG 0xffffffffL +#define BIT_FW_MSG(x) (((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG) +#define BITS_FW_MSG (BIT_MASK_FW_MSG << BIT_SHIFT_FW_MSG) +#define BIT_CLEAR_FW_MSG(x) ((x) & (~BITS_FW_MSG)) +#define BIT_GET_FW_MSG(x) (((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG) +#define BIT_SET_FW_MSG(x, v) (BIT_CLEAR_FW_MSG(x) | BIT_FW_MSG(v)) /* 2 REG_HMETFR (Offset 0x01CC) */ +#define BIT_SHIFT_HRCV_MSG 24 +#define BIT_MASK_HRCV_MSG 0xff +#define BIT_HRCV_MSG(x) (((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG) +#define BITS_HRCV_MSG (BIT_MASK_HRCV_MSG << BIT_SHIFT_HRCV_MSG) +#define BIT_CLEAR_HRCV_MSG(x) ((x) & (~BITS_HRCV_MSG)) +#define BIT_GET_HRCV_MSG(x) (((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG) +#define BIT_SET_HRCV_MSG(x, v) (BIT_CLEAR_HRCV_MSG(x) | BIT_HRCV_MSG(v)) -#define BIT_SHIFT_HRCV_MSG 24 -#define BIT_MASK_HRCV_MSG 0xff -#define BIT_HRCV_MSG(x) (((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG) -#define BIT_GET_HRCV_MSG(x) (((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG) - -#define BIT_INT_BOX3 BIT(3) -#define BIT_INT_BOX2 BIT(2) -#define BIT_INT_BOX1 BIT(1) -#define BIT_INT_BOX0 BIT(0) +#define BIT_INT_BOX3 BIT(3) +#define BIT_INT_BOX2 BIT(2) +#define BIT_INT_BOX1 BIT(1) +#define BIT_INT_BOX0 BIT(0) /* 2 REG_HMEBOX0 (Offset 0x01D0) */ - -#define BIT_SHIFT_HOST_MSG_0 0 -#define BIT_MASK_HOST_MSG_0 0xffffffffL -#define BIT_HOST_MSG_0(x) (((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0) -#define BIT_GET_HOST_MSG_0(x) (((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0) - +#define BIT_SHIFT_HOST_MSG_0 0 +#define BIT_MASK_HOST_MSG_0 0xffffffffL +#define BIT_HOST_MSG_0(x) (((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0) +#define BITS_HOST_MSG_0 (BIT_MASK_HOST_MSG_0 << BIT_SHIFT_HOST_MSG_0) +#define BIT_CLEAR_HOST_MSG_0(x) ((x) & (~BITS_HOST_MSG_0)) +#define BIT_GET_HOST_MSG_0(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0) +#define BIT_SET_HOST_MSG_0(x, v) (BIT_CLEAR_HOST_MSG_0(x) | BIT_HOST_MSG_0(v)) /* 2 REG_HMEBOX1 (Offset 0x01D4) */ - -#define BIT_SHIFT_HOST_MSG_1 0 -#define BIT_MASK_HOST_MSG_1 0xffffffffL -#define BIT_HOST_MSG_1(x) (((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1) -#define BIT_GET_HOST_MSG_1(x) (((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1) - +#define BIT_SHIFT_HOST_MSG_1 0 +#define BIT_MASK_HOST_MSG_1 0xffffffffL +#define BIT_HOST_MSG_1(x) (((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1) +#define BITS_HOST_MSG_1 (BIT_MASK_HOST_MSG_1 << BIT_SHIFT_HOST_MSG_1) +#define BIT_CLEAR_HOST_MSG_1(x) ((x) & (~BITS_HOST_MSG_1)) +#define BIT_GET_HOST_MSG_1(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1) +#define BIT_SET_HOST_MSG_1(x, v) (BIT_CLEAR_HOST_MSG_1(x) | BIT_HOST_MSG_1(v)) /* 2 REG_HMEBOX2 (Offset 0x01D8) */ - -#define BIT_SHIFT_HOST_MSG_2 0 -#define BIT_MASK_HOST_MSG_2 0xffffffffL -#define BIT_HOST_MSG_2(x) (((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2) -#define BIT_GET_HOST_MSG_2(x) (((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2) - +#define BIT_SHIFT_HOST_MSG_2 0 +#define BIT_MASK_HOST_MSG_2 0xffffffffL +#define BIT_HOST_MSG_2(x) (((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2) +#define BITS_HOST_MSG_2 (BIT_MASK_HOST_MSG_2 << BIT_SHIFT_HOST_MSG_2) +#define BIT_CLEAR_HOST_MSG_2(x) ((x) & (~BITS_HOST_MSG_2)) +#define BIT_GET_HOST_MSG_2(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2) +#define BIT_SET_HOST_MSG_2(x, v) (BIT_CLEAR_HOST_MSG_2(x) | BIT_HOST_MSG_2(v)) /* 2 REG_HMEBOX3 (Offset 0x01DC) */ +#define BIT_SHIFT_HOST_MSG_3 0 +#define BIT_MASK_HOST_MSG_3 0xffffffffL +#define BIT_HOST_MSG_3(x) (((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3) +#define BITS_HOST_MSG_3 (BIT_MASK_HOST_MSG_3 << BIT_SHIFT_HOST_MSG_3) +#define BIT_CLEAR_HOST_MSG_3(x) ((x) & (~BITS_HOST_MSG_3)) +#define BIT_GET_HOST_MSG_3(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3) +#define BIT_SET_HOST_MSG_3(x, v) (BIT_CLEAR_HOST_MSG_3(x) | BIT_HOST_MSG_3(v)) -#define BIT_SHIFT_HOST_MSG_3 0 -#define BIT_MASK_HOST_MSG_3 0xffffffffL -#define BIT_HOST_MSG_3(x) (((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3) -#define BIT_GET_HOST_MSG_3(x) (((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_LLT_INIT (Offset 0x01E0) */ - -#define BIT_SHIFT_LLTE_RWM 30 -#define BIT_MASK_LLTE_RWM 0x3 -#define BIT_LLTE_RWM(x) (((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM) -#define BIT_GET_LLTE_RWM(x) (((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM) - +#define BIT_SHIFT_LLTE_RWM 30 +#define BIT_MASK_LLTE_RWM 0x3 +#define BIT_LLTE_RWM(x) (((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM) +#define BITS_LLTE_RWM (BIT_MASK_LLTE_RWM << BIT_SHIFT_LLTE_RWM) +#define BIT_CLEAR_LLTE_RWM(x) ((x) & (~BITS_LLTE_RWM)) +#define BIT_GET_LLTE_RWM(x) (((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM) +#define BIT_SET_LLTE_RWM(x, v) (BIT_CLEAR_LLTE_RWM(x) | BIT_LLTE_RWM(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXDESC_BUFF_BNDY (Offset 0x01E0) */ +#define BIT_FW_FIFO_PTR_RST BIT(18) +#define BIT_PHY_FIFO_PTR_RST BIT(17) -/* 2 REG_LLT_INIT (Offset 0x01E0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LLTINI_PDATA 16 -#define BIT_MASK_LLTINI_PDATA 0xff -#define BIT_LLTINI_PDATA(x) (((x) & BIT_MASK_LLTINI_PDATA) << BIT_SHIFT_LLTINI_PDATA) -#define BIT_GET_LLTINI_PDATA(x) (((x) >> BIT_SHIFT_LLTINI_PDATA) & BIT_MASK_LLTINI_PDATA) +/* 2 REG_LLT_INIT (Offset 0x01E0) */ +#define BIT_SHIFT_LLTINI_PDATA 16 +#define BIT_MASK_LLTINI_PDATA 0xff +#define BIT_LLTINI_PDATA(x) \ + (((x) & BIT_MASK_LLTINI_PDATA) << BIT_SHIFT_LLTINI_PDATA) +#define BITS_LLTINI_PDATA (BIT_MASK_LLTINI_PDATA << BIT_SHIFT_LLTINI_PDATA) +#define BIT_CLEAR_LLTINI_PDATA(x) ((x) & (~BITS_LLTINI_PDATA)) +#define BIT_GET_LLTINI_PDATA(x) \ + (((x) >> BIT_SHIFT_LLTINI_PDATA) & BIT_MASK_LLTINI_PDATA) +#define BIT_SET_LLTINI_PDATA(x, v) \ + (BIT_CLEAR_LLTINI_PDATA(x) | BIT_LLTINI_PDATA(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LLT_INIT (Offset 0x01E0) */ - -#define BIT_SHIFT_LLTINI_PDATA_V1 16 -#define BIT_MASK_LLTINI_PDATA_V1 0xfff -#define BIT_LLTINI_PDATA_V1(x) (((x) & BIT_MASK_LLTINI_PDATA_V1) << BIT_SHIFT_LLTINI_PDATA_V1) -#define BIT_GET_LLTINI_PDATA_V1(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1) & BIT_MASK_LLTINI_PDATA_V1) - +#define BIT_SHIFT_LLTINI_PDATA_V1 16 +#define BIT_MASK_LLTINI_PDATA_V1 0xfff +#define BIT_LLTINI_PDATA_V1(x) \ + (((x) & BIT_MASK_LLTINI_PDATA_V1) << BIT_SHIFT_LLTINI_PDATA_V1) +#define BITS_LLTINI_PDATA_V1 \ + (BIT_MASK_LLTINI_PDATA_V1 << BIT_SHIFT_LLTINI_PDATA_V1) +#define BIT_CLEAR_LLTINI_PDATA_V1(x) ((x) & (~BITS_LLTINI_PDATA_V1)) +#define BIT_GET_LLTINI_PDATA_V1(x) \ + (((x) >> BIT_SHIFT_LLTINI_PDATA_V1) & BIT_MASK_LLTINI_PDATA_V1) +#define BIT_SET_LLTINI_PDATA_V1(x, v) \ + (BIT_CLEAR_LLTINI_PDATA_V1(x) | BIT_LLTINI_PDATA_V1(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_LLT_INIT (Offset 0x01E0) */ +#define BIT_SHIFT_LLTINI_ADDR 8 +#define BIT_MASK_LLTINI_ADDR 0xff +#define BIT_LLTINI_ADDR(x) \ + (((x) & BIT_MASK_LLTINI_ADDR) << BIT_SHIFT_LLTINI_ADDR) +#define BITS_LLTINI_ADDR (BIT_MASK_LLTINI_ADDR << BIT_SHIFT_LLTINI_ADDR) +#define BIT_CLEAR_LLTINI_ADDR(x) ((x) & (~BITS_LLTINI_ADDR)) +#define BIT_GET_LLTINI_ADDR(x) \ + (((x) >> BIT_SHIFT_LLTINI_ADDR) & BIT_MASK_LLTINI_ADDR) +#define BIT_SET_LLTINI_ADDR(x, v) \ + (BIT_CLEAR_LLTINI_ADDR(x) | BIT_LLTINI_ADDR(v)) + +#define BIT_SHIFT_LLTINI_HDATA 0 +#define BIT_MASK_LLTINI_HDATA 0xff +#define BIT_LLTINI_HDATA(x) \ + (((x) & BIT_MASK_LLTINI_HDATA) << BIT_SHIFT_LLTINI_HDATA) +#define BITS_LLTINI_HDATA (BIT_MASK_LLTINI_HDATA << BIT_SHIFT_LLTINI_HDATA) +#define BIT_CLEAR_LLTINI_HDATA(x) ((x) & (~BITS_LLTINI_HDATA)) +#define BIT_GET_LLTINI_HDATA(x) \ + (((x) >> BIT_SHIFT_LLTINI_HDATA) & BIT_MASK_LLTINI_HDATA) +#define BIT_SET_LLTINI_HDATA(x, v) \ + (BIT_CLEAR_LLTINI_HDATA(x) | BIT_LLTINI_HDATA(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_LLTINI_ADDR 8 -#define BIT_MASK_LLTINI_ADDR 0xff -#define BIT_LLTINI_ADDR(x) (((x) & BIT_MASK_LLTINI_ADDR) << BIT_SHIFT_LLTINI_ADDR) -#define BIT_GET_LLTINI_ADDR(x) (((x) >> BIT_SHIFT_LLTINI_ADDR) & BIT_MASK_LLTINI_ADDR) - - -#define BIT_SHIFT_LLTINI_HDATA 0 -#define BIT_MASK_LLTINI_HDATA 0xff -#define BIT_LLTINI_HDATA(x) (((x) & BIT_MASK_LLTINI_HDATA) << BIT_SHIFT_LLTINI_HDATA) -#define BIT_GET_LLTINI_HDATA(x) (((x) >> BIT_SHIFT_LLTINI_HDATA) & BIT_MASK_LLTINI_HDATA) +/* 2 REG_LLT_INIT (Offset 0x01E0) */ +#define BIT_SHIFT_LLTINI_HDATA_V1 0 +#define BIT_MASK_LLTINI_HDATA_V1 0xfff +#define BIT_LLTINI_HDATA_V1(x) \ + (((x) & BIT_MASK_LLTINI_HDATA_V1) << BIT_SHIFT_LLTINI_HDATA_V1) +#define BITS_LLTINI_HDATA_V1 \ + (BIT_MASK_LLTINI_HDATA_V1 << BIT_SHIFT_LLTINI_HDATA_V1) +#define BIT_CLEAR_LLTINI_HDATA_V1(x) ((x) & (~BITS_LLTINI_HDATA_V1)) +#define BIT_GET_LLTINI_HDATA_V1(x) \ + (((x) >> BIT_SHIFT_LLTINI_HDATA_V1) & BIT_MASK_LLTINI_HDATA_V1) +#define BIT_SET_LLTINI_HDATA_V1(x, v) \ + (BIT_CLEAR_LLTINI_HDATA_V1(x) | BIT_LLTINI_HDATA_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_LLT_INIT (Offset 0x01E0) */ - - -#define BIT_SHIFT_LLTINI_HDATA_V1 0 -#define BIT_MASK_LLTINI_HDATA_V1 0xfff -#define BIT_LLTINI_HDATA_V1(x) (((x) & BIT_MASK_LLTINI_HDATA_V1) << BIT_SHIFT_LLTINI_HDATA_V1) -#define BIT_GET_LLTINI_HDATA_V1(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1) & BIT_MASK_LLTINI_HDATA_V1) +/* 2 REG_RXDESC_BUFF_BNDY (Offset 0x01E0) */ +#define BIT_SHIFT_RXDESC_BUFF_BNDY 0 +#define BIT_MASK_RXDESC_BUFF_BNDY 0xffffffffL +#define BIT_RXDESC_BUFF_BNDY(x) \ + (((x) & BIT_MASK_RXDESC_BUFF_BNDY) << BIT_SHIFT_RXDESC_BUFF_BNDY) +#define BITS_RXDESC_BUFF_BNDY \ + (BIT_MASK_RXDESC_BUFF_BNDY << BIT_SHIFT_RXDESC_BUFF_BNDY) +#define BIT_CLEAR_RXDESC_BUFF_BNDY(x) ((x) & (~BITS_RXDESC_BUFF_BNDY)) +#define BIT_GET_RXDESC_BUFF_BNDY(x) \ + (((x) >> BIT_SHIFT_RXDESC_BUFF_BNDY) & BIT_MASK_RXDESC_BUFF_BNDY) +#define BIT_SET_RXDESC_BUFF_BNDY(x, v) \ + (BIT_CLEAR_RXDESC_BUFF_BNDY(x) | BIT_RXDESC_BUFF_BNDY(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_GENTST (Offset 0x01E4) */ - -#define BIT_SHIFT_GENTST 0 -#define BIT_MASK_GENTST 0xffffffffL -#define BIT_GENTST(x) (((x) & BIT_MASK_GENTST) << BIT_SHIFT_GENTST) -#define BIT_GET_GENTST(x) (((x) >> BIT_SHIFT_GENTST) & BIT_MASK_GENTST) - +#define BIT_SHIFT_GENTST 0 +#define BIT_MASK_GENTST 0xffffffffL +#define BIT_GENTST(x) (((x) & BIT_MASK_GENTST) << BIT_SHIFT_GENTST) +#define BITS_GENTST (BIT_MASK_GENTST << BIT_SHIFT_GENTST) +#define BIT_CLEAR_GENTST(x) ((x) & (~BITS_GENTST)) +#define BIT_GET_GENTST(x) (((x) >> BIT_SHIFT_GENTST) & BIT_MASK_GENTST) +#define BIT_SET_GENTST(x, v) (BIT_CLEAR_GENTST(x) | BIT_GENTST(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LLT_INIT_ADDR (Offset 0x01E4) */ - -#define BIT_SHIFT_LLTINI_ADDR_V1 0 -#define BIT_MASK_LLTINI_ADDR_V1 0xfff -#define BIT_LLTINI_ADDR_V1(x) (((x) & BIT_MASK_LLTINI_ADDR_V1) << BIT_SHIFT_LLTINI_ADDR_V1) -#define BIT_GET_LLTINI_ADDR_V1(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1) & BIT_MASK_LLTINI_ADDR_V1) - +#define BIT_SHIFT_LLTINI_ADDR_V1 0 +#define BIT_MASK_LLTINI_ADDR_V1 0xfff +#define BIT_LLTINI_ADDR_V1(x) \ + (((x) & BIT_MASK_LLTINI_ADDR_V1) << BIT_SHIFT_LLTINI_ADDR_V1) +#define BITS_LLTINI_ADDR_V1 \ + (BIT_MASK_LLTINI_ADDR_V1 << BIT_SHIFT_LLTINI_ADDR_V1) +#define BIT_CLEAR_LLTINI_ADDR_V1(x) ((x) & (~BITS_LLTINI_ADDR_V1)) +#define BIT_GET_LLTINI_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_LLTINI_ADDR_V1) & BIT_MASK_LLTINI_ADDR_V1) +#define BIT_SET_LLTINI_ADDR_V1(x, v) \ + (BIT_CLEAR_LLTINI_ADDR_V1(x) | BIT_LLTINI_ADDR_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ - -#define BIT_SHIFT_BB_WRITE_READ 30 -#define BIT_MASK_BB_WRITE_READ 0x3 -#define BIT_BB_WRITE_READ(x) (((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ) -#define BIT_GET_BB_WRITE_READ(x) (((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ) - +#define BIT_SHIFT_BB_WRITE_READ 30 +#define BIT_MASK_BB_WRITE_READ 0x3 +#define BIT_BB_WRITE_READ(x) \ + (((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ) +#define BITS_BB_WRITE_READ (BIT_MASK_BB_WRITE_READ << BIT_SHIFT_BB_WRITE_READ) +#define BIT_CLEAR_BB_WRITE_READ(x) ((x) & (~BITS_BB_WRITE_READ)) +#define BIT_GET_BB_WRITE_READ(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ) +#define BIT_SET_BB_WRITE_READ(x, v) \ + (BIT_CLEAR_BB_WRITE_READ(x) | BIT_BB_WRITE_READ(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ - -#define BIT_SHIFT_BB_WRITE_EN_V1 16 -#define BIT_MASK_BB_WRITE_EN_V1 0xf -#define BIT_BB_WRITE_EN_V1(x) (((x) & BIT_MASK_BB_WRITE_EN_V1) << BIT_SHIFT_BB_WRITE_EN_V1) -#define BIT_GET_BB_WRITE_EN_V1(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_V1) & BIT_MASK_BB_WRITE_EN_V1) - +#define BIT_SHIFT_BB_WRITE_EN_V1 16 +#define BIT_MASK_BB_WRITE_EN_V1 0xf +#define BIT_BB_WRITE_EN_V1(x) \ + (((x) & BIT_MASK_BB_WRITE_EN_V1) << BIT_SHIFT_BB_WRITE_EN_V1) +#define BITS_BB_WRITE_EN_V1 \ + (BIT_MASK_BB_WRITE_EN_V1 << BIT_SHIFT_BB_WRITE_EN_V1) +#define BIT_CLEAR_BB_WRITE_EN_V1(x) ((x) & (~BITS_BB_WRITE_EN_V1)) +#define BIT_GET_BB_WRITE_EN_V1(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN_V1) & BIT_MASK_BB_WRITE_EN_V1) +#define BIT_SET_BB_WRITE_EN_V1(x, v) \ + (BIT_CLEAR_BB_WRITE_EN_V1(x) | BIT_BB_WRITE_EN_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ +#define BIT_SHIFT_BB_WRITE_EN 12 +#define BIT_MASK_BB_WRITE_EN 0xf +#define BIT_BB_WRITE_EN(x) \ + (((x) & BIT_MASK_BB_WRITE_EN) << BIT_SHIFT_BB_WRITE_EN) +#define BITS_BB_WRITE_EN (BIT_MASK_BB_WRITE_EN << BIT_SHIFT_BB_WRITE_EN) +#define BIT_CLEAR_BB_WRITE_EN(x) ((x) & (~BITS_BB_WRITE_EN)) +#define BIT_GET_BB_WRITE_EN(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN) & BIT_MASK_BB_WRITE_EN) +#define BIT_SET_BB_WRITE_EN(x, v) \ + (BIT_CLEAR_BB_WRITE_EN(x) | BIT_BB_WRITE_EN(v)) -#define BIT_SHIFT_BB_WRITE_EN 12 -#define BIT_MASK_BB_WRITE_EN 0xf -#define BIT_BB_WRITE_EN(x) (((x) & BIT_MASK_BB_WRITE_EN) << BIT_SHIFT_BB_WRITE_EN) -#define BIT_GET_BB_WRITE_EN(x) (((x) >> BIT_SHIFT_BB_WRITE_EN) & BIT_MASK_BB_WRITE_EN) - - -#define BIT_SHIFT_BB_ADDR 2 -#define BIT_MASK_BB_ADDR 0x1ff -#define BIT_BB_ADDR(x) (((x) & BIT_MASK_BB_ADDR) << BIT_SHIFT_BB_ADDR) -#define BIT_GET_BB_ADDR(x) (((x) >> BIT_SHIFT_BB_ADDR) & BIT_MASK_BB_ADDR) - +#define BIT_SHIFT_BB_ADDR 2 +#define BIT_MASK_BB_ADDR 0x1ff +#define BIT_BB_ADDR(x) (((x) & BIT_MASK_BB_ADDR) << BIT_SHIFT_BB_ADDR) +#define BITS_BB_ADDR (BIT_MASK_BB_ADDR << BIT_SHIFT_BB_ADDR) +#define BIT_CLEAR_BB_ADDR(x) ((x) & (~BITS_BB_ADDR)) +#define BIT_GET_BB_ADDR(x) (((x) >> BIT_SHIFT_BB_ADDR) & BIT_MASK_BB_ADDR) +#define BIT_SET_BB_ADDR(x, v) (BIT_CLEAR_BB_ADDR(x) | BIT_BB_ADDR(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ - -#define BIT_SHIFT_BB_ADDR_V1 2 -#define BIT_MASK_BB_ADDR_V1 0xfff -#define BIT_BB_ADDR_V1(x) (((x) & BIT_MASK_BB_ADDR_V1) << BIT_SHIFT_BB_ADDR_V1) -#define BIT_GET_BB_ADDR_V1(x) (((x) >> BIT_SHIFT_BB_ADDR_V1) & BIT_MASK_BB_ADDR_V1) - +#define BIT_SHIFT_BB_ADDR_V1 2 +#define BIT_MASK_BB_ADDR_V1 0xfff +#define BIT_BB_ADDR_V1(x) (((x) & BIT_MASK_BB_ADDR_V1) << BIT_SHIFT_BB_ADDR_V1) +#define BITS_BB_ADDR_V1 (BIT_MASK_BB_ADDR_V1 << BIT_SHIFT_BB_ADDR_V1) +#define BIT_CLEAR_BB_ADDR_V1(x) ((x) & (~BITS_BB_ADDR_V1)) +#define BIT_GET_BB_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_BB_ADDR_V1) & BIT_MASK_BB_ADDR_V1) +#define BIT_SET_BB_ADDR_V1(x, v) (BIT_CLEAR_BB_ADDR_V1(x) | BIT_BB_ADDR_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ -#define BIT_BB_ERRACC BIT(0) +#define BIT_BB_ERRACC BIT(0) /* 2 REG_BB_ACCESS_DATA (Offset 0x01EC) */ - -#define BIT_SHIFT_BB_DATA 0 -#define BIT_MASK_BB_DATA 0xffffffffL -#define BIT_BB_DATA(x) (((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA) -#define BIT_GET_BB_DATA(x) (((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA) - +#define BIT_SHIFT_BB_DATA 0 +#define BIT_MASK_BB_DATA 0xffffffffL +#define BIT_BB_DATA(x) (((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA) +#define BITS_BB_DATA (BIT_MASK_BB_DATA << BIT_SHIFT_BB_DATA) +#define BIT_CLEAR_BB_DATA(x) ((x) & (~BITS_BB_DATA)) +#define BIT_GET_BB_DATA(x) (((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA) +#define BIT_SET_BB_DATA(x, v) (BIT_CLEAR_BB_DATA(x) | BIT_BB_DATA(v)) /* 2 REG_HMEBOX_E0 (Offset 0x01F0) */ - -#define BIT_SHIFT_HMEBOX_E0 0 -#define BIT_MASK_HMEBOX_E0 0xffffffffL -#define BIT_HMEBOX_E0(x) (((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0) -#define BIT_GET_HMEBOX_E0(x) (((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0) - +#define BIT_SHIFT_HMEBOX_E0 0 +#define BIT_MASK_HMEBOX_E0 0xffffffffL +#define BIT_HMEBOX_E0(x) (((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0) +#define BITS_HMEBOX_E0 (BIT_MASK_HMEBOX_E0 << BIT_SHIFT_HMEBOX_E0) +#define BIT_CLEAR_HMEBOX_E0(x) ((x) & (~BITS_HMEBOX_E0)) +#define BIT_GET_HMEBOX_E0(x) (((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0) +#define BIT_SET_HMEBOX_E0(x, v) (BIT_CLEAR_HMEBOX_E0(x) | BIT_HMEBOX_E0(v)) /* 2 REG_HMEBOX_E1 (Offset 0x01F4) */ - -#define BIT_SHIFT_HMEBOX_E1 0 -#define BIT_MASK_HMEBOX_E1 0xffffffffL -#define BIT_HMEBOX_E1(x) (((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1) -#define BIT_GET_HMEBOX_E1(x) (((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1) - +#define BIT_SHIFT_HMEBOX_E1 0 +#define BIT_MASK_HMEBOX_E1 0xffffffffL +#define BIT_HMEBOX_E1(x) (((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1) +#define BITS_HMEBOX_E1 (BIT_MASK_HMEBOX_E1 << BIT_SHIFT_HMEBOX_E1) +#define BIT_CLEAR_HMEBOX_E1(x) ((x) & (~BITS_HMEBOX_E1)) +#define BIT_GET_HMEBOX_E1(x) (((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1) +#define BIT_SET_HMEBOX_E1(x, v) (BIT_CLEAR_HMEBOX_E1(x) | BIT_HMEBOX_E1(v)) /* 2 REG_HMEBOX_E2 (Offset 0x01F8) */ +#define BIT_SHIFT_HMEBOX_E2 0 +#define BIT_MASK_HMEBOX_E2 0xffffffffL +#define BIT_HMEBOX_E2(x) (((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2) +#define BITS_HMEBOX_E2 (BIT_MASK_HMEBOX_E2 << BIT_SHIFT_HMEBOX_E2) +#define BIT_CLEAR_HMEBOX_E2(x) ((x) & (~BITS_HMEBOX_E2)) +#define BIT_GET_HMEBOX_E2(x) (((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2) +#define BIT_SET_HMEBOX_E2(x, v) (BIT_CLEAR_HMEBOX_E2(x) | BIT_HMEBOX_E2(v)) -#define BIT_SHIFT_HMEBOX_E2 0 -#define BIT_MASK_HMEBOX_E2 0xffffffffL -#define BIT_HMEBOX_E2(x) (((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2) -#define BIT_GET_HMEBOX_E2(x) (((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2) +/* 2 REG_HMEBOX_E3 (Offset 0x01FC) */ +#define BIT_SHIFT_HMEBOX_E3 0 +#define BIT_MASK_HMEBOX_E3 0xffffffffL +#define BIT_HMEBOX_E3(x) (((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3) +#define BITS_HMEBOX_E3 (BIT_MASK_HMEBOX_E3 << BIT_SHIFT_HMEBOX_E3) +#define BIT_CLEAR_HMEBOX_E3(x) ((x) & (~BITS_HMEBOX_E3)) +#define BIT_GET_HMEBOX_E3(x) (((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3) +#define BIT_SET_HMEBOX_E3(x, v) (BIT_CLEAR_HMEBOX_E3(x) | BIT_HMEBOX_E3(v)) -/* 2 REG_HMEBOX_E3 (Offset 0x01FC) */ +#endif -#define BIT_LD_RQPN BIT(31) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HMEBOX_E3 0 -#define BIT_MASK_HMEBOX_E3 0xffffffffL -#define BIT_HMEBOX_E3(x) (((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3) -#define BIT_GET_HMEBOX_E3(x) (((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3) +/* 2 REG_BCN_CTRL_0 (Offset 0x0200) */ +#define BIT_BCN1_VALID BIT(31) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */ -#define BIT_EPQ_PUBLIC_DIS BIT(27) -#define BIT_NPQ_PUBLIC_DIS BIT(26) -#define BIT_LPQ_PUBLIC_DIS BIT(25) -#define BIT_HPQ_PUBLIC_DIS BIT(24) - -#define BIT_SHIFT_PUBQ 16 -#define BIT_MASK_PUBQ 0xff -#define BIT_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ) -#define BIT_GET_PUBQ(x) (((x) >> BIT_SHIFT_PUBQ) & BIT_MASK_PUBQ) +#define BIT_EPQ_PUBLIC_DIS BIT(27) +#define BIT_NPQ_PUBLIC_DIS BIT(26) +#define BIT_LPQ_PUBLIC_DIS BIT(25) +#define BIT_HPQ_PUBLIC_DIS BIT(24) +#define BIT_SHIFT_PUBQ 16 +#define BIT_MASK_PUBQ 0xff +#define BIT_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ) +#define BITS_PUBQ (BIT_MASK_PUBQ << BIT_SHIFT_PUBQ) +#define BIT_CLEAR_PUBQ(x) ((x) & (~BITS_PUBQ)) +#define BIT_GET_PUBQ(x) (((x) >> BIT_SHIFT_PUBQ) & BIT_MASK_PUBQ) +#define BIT_SET_PUBQ(x, v) (BIT_CLEAR_PUBQ(x) | BIT_PUBQ(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ - -#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1 16 -#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 0xff -#define BIT_TX_OQT_HE_FREE_SPACE_V1(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) -#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) - +#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1 16 +#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 0xff +#define BIT_TX_OQT_HE_FREE_SPACE_V1(x) \ + (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) +#define BITS_TX_OQT_HE_FREE_SPACE_V1 \ + (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1(x) \ + ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1(x) \ + (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) & \ + BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) +#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1(x, v) \ + (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1(x) | BIT_TX_OQT_HE_FREE_SPACE_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCN_CTRL_0 (Offset 0x0200) */ +#define BIT_SHIFT_BCN1_HEAD 16 +#define BIT_MASK_BCN1_HEAD 0xfff +#define BIT_BCN1_HEAD(x) (((x) & BIT_MASK_BCN1_HEAD) << BIT_SHIFT_BCN1_HEAD) +#define BITS_BCN1_HEAD (BIT_MASK_BCN1_HEAD << BIT_SHIFT_BCN1_HEAD) +#define BIT_CLEAR_BCN1_HEAD(x) ((x) & (~BITS_BCN1_HEAD)) +#define BIT_GET_BCN1_HEAD(x) (((x) >> BIT_SHIFT_BCN1_HEAD) & BIT_MASK_BCN1_HEAD) +#define BIT_SET_BCN1_HEAD(x, v) (BIT_CLEAR_BCN1_HEAD(x) | BIT_BCN1_HEAD(v)) -/* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */ +#define BIT_BCN0_VALID BIT(15) +#endif -#define BIT_SHIFT_LPQ 8 -#define BIT_MASK_LPQ 0xff -#define BIT_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ) -#define BIT_GET_LPQ(x) (((x) >> BIT_SHIFT_LPQ) & BIT_MASK_LPQ) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */ -#define BIT_SHIFT_HPQ 0 -#define BIT_MASK_HPQ 0xff -#define BIT_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ) -#define BIT_GET_HPQ(x) (((x) >> BIT_SHIFT_HPQ) & BIT_MASK_HPQ) +#define BIT_SHIFT_LPQ 8 +#define BIT_MASK_LPQ 0xff +#define BIT_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ) +#define BITS_LPQ (BIT_MASK_LPQ << BIT_SHIFT_LPQ) +#define BIT_CLEAR_LPQ(x) ((x) & (~BITS_LPQ)) +#define BIT_GET_LPQ(x) (((x) >> BIT_SHIFT_LPQ) & BIT_MASK_LPQ) +#define BIT_SET_LPQ(x, v) (BIT_CLEAR_LPQ(x) | BIT_LPQ(v)) +#define BIT_SHIFT_HPQ 0 +#define BIT_MASK_HPQ 0xff +#define BIT_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ) +#define BITS_HPQ (BIT_MASK_HPQ << BIT_SHIFT_HPQ) +#define BIT_CLEAR_HPQ(x) ((x) & (~BITS_HPQ)) +#define BIT_GET_HPQ(x) (((x) >> BIT_SHIFT_HPQ) & BIT_MASK_HPQ) +#define BIT_SET_HPQ(x, v) (BIT_CLEAR_HPQ(x) | BIT_HPQ(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ +#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1 0 +#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 0xff +#define BIT_TX_OQT_NL_FREE_SPACE_V1(x) \ + (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) +#define BITS_TX_OQT_NL_FREE_SPACE_V1 \ + (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1(x) \ + ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1(x) \ + (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) & \ + BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) +#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1(x, v) \ + (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1(x) | BIT_TX_OQT_NL_FREE_SPACE_V1(v)) -#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1 0 -#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 0xff -#define BIT_TX_OQT_NL_FREE_SPACE_V1(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) -#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +/* 2 REG_BCN_CTRL_0 (Offset 0x0200) */ -#define BIT_BCN_VALID_1_V1 BIT(31) +#define BIT_SHIFT_BCN0_HEAD 0 +#define BIT_MASK_BCN0_HEAD 0xfff +#define BIT_BCN0_HEAD(x) (((x) & BIT_MASK_BCN0_HEAD) << BIT_SHIFT_BCN0_HEAD) +#define BITS_BCN0_HEAD (BIT_MASK_BCN0_HEAD << BIT_SHIFT_BCN0_HEAD) +#define BIT_CLEAR_BCN0_HEAD(x) ((x) & (~BITS_BCN0_HEAD)) +#define BIT_GET_BCN0_HEAD(x) (((x) >> BIT_SHIFT_BCN0_HEAD) & BIT_MASK_BCN0_HEAD) +#define BIT_SET_BCN0_HEAD(x, v) (BIT_CLEAR_BCN0_HEAD(x) | BIT_BCN0_HEAD(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ +/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +#define BIT_BCN_VALID_1_V1 BIT(31) -#define BIT_SHIFT_TXPKTNUM 24 -#define BIT_MASK_TXPKTNUM 0xff -#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM) -#define BIT_GET_TXPKTNUM(x) (((x) >> BIT_SHIFT_TXPKTNUM) & BIT_MASK_TXPKTNUM) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_PUBQ_AVAL_PG 16 -#define BIT_MASK_PUBQ_AVAL_PG 0xff -#define BIT_PUBQ_AVAL_PG(x) (((x) & BIT_MASK_PUBQ_AVAL_PG) << BIT_SHIFT_PUBQ_AVAL_PG) -#define BIT_GET_PUBQ_AVAL_PG(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG) & BIT_MASK_PUBQ_AVAL_PG) +/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ +#define BIT_BCN3_VALID BIT(31) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ +#define BIT_SHIFT_TXPKTNUM 24 +#define BIT_MASK_TXPKTNUM 0xff +#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM) +#define BITS_TXPKTNUM (BIT_MASK_TXPKTNUM << BIT_SHIFT_TXPKTNUM) +#define BIT_CLEAR_TXPKTNUM(x) ((x) & (~BITS_TXPKTNUM)) +#define BIT_GET_TXPKTNUM(x) (((x) >> BIT_SHIFT_TXPKTNUM) & BIT_MASK_TXPKTNUM) +#define BIT_SET_TXPKTNUM(x, v) (BIT_CLEAR_TXPKTNUM(x) | BIT_TXPKTNUM(v)) -/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCN_HEAD_1_V1 16 -#define BIT_MASK_BCN_HEAD_1_V1 0xfff -#define BIT_BCN_HEAD_1_V1(x) (((x) & BIT_MASK_BCN_HEAD_1_V1) << BIT_SHIFT_BCN_HEAD_1_V1) -#define BIT_GET_BCN_HEAD_1_V1(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1) & BIT_MASK_BCN_HEAD_1_V1) +/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ -#define BIT_BCN_VALID_V1 BIT(15) +#define BIT_SHIFT_R_BCN_HEAD_SEL_V1 20 +#define BIT_MASK_R_BCN_HEAD_SEL_V1 0x7 +#define BIT_R_BCN_HEAD_SEL_V1(x) \ + (((x) & BIT_MASK_R_BCN_HEAD_SEL_V1) << BIT_SHIFT_R_BCN_HEAD_SEL_V1) +#define BITS_R_BCN_HEAD_SEL_V1 \ + (BIT_MASK_R_BCN_HEAD_SEL_V1 << BIT_SHIFT_R_BCN_HEAD_SEL_V1) +#define BIT_CLEAR_R_BCN_HEAD_SEL_V1(x) ((x) & (~BITS_R_BCN_HEAD_SEL_V1)) +#define BIT_GET_R_BCN_HEAD_SEL_V1(x) \ + (((x) >> BIT_SHIFT_R_BCN_HEAD_SEL_V1) & BIT_MASK_R_BCN_HEAD_SEL_V1) +#define BIT_SET_R_BCN_HEAD_SEL_V1(x, v) \ + (BIT_CLEAR_R_BCN_HEAD_SEL_V1(x) | BIT_R_BCN_HEAD_SEL_V1(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ +#define BIT_SHIFT_PUBQ_AVAL_PG 16 +#define BIT_MASK_PUBQ_AVAL_PG 0xff +#define BIT_PUBQ_AVAL_PG(x) \ + (((x) & BIT_MASK_PUBQ_AVAL_PG) << BIT_SHIFT_PUBQ_AVAL_PG) +#define BITS_PUBQ_AVAL_PG (BIT_MASK_PUBQ_AVAL_PG << BIT_SHIFT_PUBQ_AVAL_PG) +#define BIT_CLEAR_PUBQ_AVAL_PG(x) ((x) & (~BITS_PUBQ_AVAL_PG)) +#define BIT_GET_PUBQ_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_PUBQ_AVAL_PG) & BIT_MASK_PUBQ_AVAL_PG) +#define BIT_SET_PUBQ_AVAL_PG(x, v) \ + (BIT_CLEAR_PUBQ_AVAL_PG(x) | BIT_PUBQ_AVAL_PG(v)) -#define BIT_SHIFT_LPQ_AVAL_PG 8 -#define BIT_MASK_LPQ_AVAL_PG 0xff -#define BIT_LPQ_AVAL_PG(x) (((x) & BIT_MASK_LPQ_AVAL_PG) << BIT_SHIFT_LPQ_AVAL_PG) -#define BIT_GET_LPQ_AVAL_PG(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG) & BIT_MASK_LPQ_AVAL_PG) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HPQ_AVAL_PG 0 -#define BIT_MASK_HPQ_AVAL_PG 0xff -#define BIT_HPQ_AVAL_PG(x) (((x) & BIT_MASK_HPQ_AVAL_PG) << BIT_SHIFT_HPQ_AVAL_PG) -#define BIT_GET_HPQ_AVAL_PG(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG) & BIT_MASK_HPQ_AVAL_PG) +/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +#define BIT_SHIFT_BCN_HEAD_1_V1 16 +#define BIT_MASK_BCN_HEAD_1_V1 0xfff +#define BIT_BCN_HEAD_1_V1(x) \ + (((x) & BIT_MASK_BCN_HEAD_1_V1) << BIT_SHIFT_BCN_HEAD_1_V1) +#define BITS_BCN_HEAD_1_V1 (BIT_MASK_BCN_HEAD_1_V1 << BIT_SHIFT_BCN_HEAD_1_V1) +#define BIT_CLEAR_BCN_HEAD_1_V1(x) ((x) & (~BITS_BCN_HEAD_1_V1)) +#define BIT_GET_BCN_HEAD_1_V1(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_1_V1) & BIT_MASK_BCN_HEAD_1_V1) +#define BIT_SET_BCN_HEAD_1_V1(x, v) \ + (BIT_CLEAR_BCN_HEAD_1_V1(x) | BIT_BCN_HEAD_1_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ +#define BIT_SHIFT_BCN3_HEAD 16 +#define BIT_MASK_BCN3_HEAD 0xfff +#define BIT_BCN3_HEAD(x) (((x) & BIT_MASK_BCN3_HEAD) << BIT_SHIFT_BCN3_HEAD) +#define BITS_BCN3_HEAD (BIT_MASK_BCN3_HEAD << BIT_SHIFT_BCN3_HEAD) +#define BIT_CLEAR_BCN3_HEAD(x) ((x) & (~BITS_BCN3_HEAD)) +#define BIT_GET_BCN3_HEAD(x) (((x) >> BIT_SHIFT_BCN3_HEAD) & BIT_MASK_BCN3_HEAD) +#define BIT_SET_BCN3_HEAD(x, v) (BIT_CLEAR_BCN3_HEAD(x) | BIT_BCN3_HEAD(v)) -/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BCN_HEAD_V1 0 -#define BIT_MASK_BCN_HEAD_V1 0xfff -#define BIT_BCN_HEAD_V1(x) (((x) & BIT_MASK_BCN_HEAD_V1) << BIT_SHIFT_BCN_HEAD_V1) -#define BIT_GET_BCN_HEAD_V1(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1) & BIT_MASK_BCN_HEAD_V1) +/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +#define BIT_BCN_VALID_V1 BIT(15) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ +#define BIT_BCN2_VALID BIT(15) -/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LLT_FREE_PAGE 24 -#define BIT_MASK_LLT_FREE_PAGE 0xff -#define BIT_LLT_FREE_PAGE(x) (((x) & BIT_MASK_LLT_FREE_PAGE) << BIT_SHIFT_LLT_FREE_PAGE) -#define BIT_GET_LLT_FREE_PAGE(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE) & BIT_MASK_LLT_FREE_PAGE) +/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ +#define BIT_SHIFT_LPQ_AVAL_PG 8 +#define BIT_MASK_LPQ_AVAL_PG 0xff +#define BIT_LPQ_AVAL_PG(x) \ + (((x) & BIT_MASK_LPQ_AVAL_PG) << BIT_SHIFT_LPQ_AVAL_PG) +#define BITS_LPQ_AVAL_PG (BIT_MASK_LPQ_AVAL_PG << BIT_SHIFT_LPQ_AVAL_PG) +#define BIT_CLEAR_LPQ_AVAL_PG(x) ((x) & (~BITS_LPQ_AVAL_PG)) +#define BIT_GET_LPQ_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_LPQ_AVAL_PG) & BIT_MASK_LPQ_AVAL_PG) +#define BIT_SET_LPQ_AVAL_PG(x, v) \ + (BIT_CLEAR_LPQ_AVAL_PG(x) | BIT_LPQ_AVAL_PG(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ +#define BIT_TDE_ERROR_STOP BIT(3) -/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 24 -#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 0xff -#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) -#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) +/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ +#define BIT_SHIFT_HPQ_AVAL_PG 0 +#define BIT_MASK_HPQ_AVAL_PG 0xff +#define BIT_HPQ_AVAL_PG(x) \ + (((x) & BIT_MASK_HPQ_AVAL_PG) << BIT_SHIFT_HPQ_AVAL_PG) +#define BITS_HPQ_AVAL_PG (BIT_MASK_HPQ_AVAL_PG << BIT_SHIFT_HPQ_AVAL_PG) +#define BIT_CLEAR_HPQ_AVAL_PG(x) ((x) & (~BITS_HPQ_AVAL_PG)) +#define BIT_GET_HPQ_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_HPQ_AVAL_PG) & BIT_MASK_HPQ_AVAL_PG) +#define BIT_SET_HPQ_AVAL_PG(x, v) \ + (BIT_CLEAR_HPQ_AVAL_PG(x) | BIT_HPQ_AVAL_PG(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +#define BIT_SHIFT_BCN_HEAD_V1 0 +#define BIT_MASK_BCN_HEAD_V1 0xfff +#define BIT_BCN_HEAD_V1(x) \ + (((x) & BIT_MASK_BCN_HEAD_V1) << BIT_SHIFT_BCN_HEAD_V1) +#define BITS_BCN_HEAD_V1 (BIT_MASK_BCN_HEAD_V1 << BIT_SHIFT_BCN_HEAD_V1) +#define BIT_CLEAR_BCN_HEAD_V1(x) ((x) & (~BITS_BCN_HEAD_V1)) +#define BIT_GET_BCN_HEAD_V1(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_V1) & BIT_MASK_BCN_HEAD_V1) +#define BIT_SET_BCN_HEAD_V1(x, v) \ + (BIT_CLEAR_BCN_HEAD_V1(x) | BIT_BCN_HEAD_V1(v)) -/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ +#endif -#define BIT_BCN_VALID BIT(16) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCN_HEAD 8 -#define BIT_MASK_BCN_HEAD 0xff -#define BIT_BCN_HEAD(x) (((x) & BIT_MASK_BCN_HEAD) << BIT_SHIFT_BCN_HEAD) -#define BIT_GET_BCN_HEAD(x) (((x) >> BIT_SHIFT_BCN_HEAD) & BIT_MASK_BCN_HEAD) +/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ +#define BIT_SHIFT_BCN2_HEAD 0 +#define BIT_MASK_BCN2_HEAD 0xfff +#define BIT_BCN2_HEAD(x) (((x) & BIT_MASK_BCN2_HEAD) << BIT_SHIFT_BCN2_HEAD) +#define BITS_BCN2_HEAD (BIT_MASK_BCN2_HEAD << BIT_SHIFT_BCN2_HEAD) +#define BIT_CLEAR_BCN2_HEAD(x) ((x) & (~BITS_BCN2_HEAD)) +#define BIT_GET_BCN2_HEAD(x) (((x) >> BIT_SHIFT_BCN2_HEAD) & BIT_MASK_BCN2_HEAD) +#define BIT_SET_BCN2_HEAD(x, v) (BIT_CLEAR_BCN2_HEAD(x) | BIT_BCN2_HEAD(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ +#define BIT_SHIFT_LLT_FREE_PAGE 24 +#define BIT_MASK_LLT_FREE_PAGE 0xff +#define BIT_LLT_FREE_PAGE(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE) << BIT_SHIFT_LLT_FREE_PAGE) +#define BITS_LLT_FREE_PAGE (BIT_MASK_LLT_FREE_PAGE << BIT_SHIFT_LLT_FREE_PAGE) +#define BIT_CLEAR_LLT_FREE_PAGE(x) ((x) & (~BITS_LLT_FREE_PAGE)) +#define BIT_GET_LLT_FREE_PAGE(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE) & BIT_MASK_LLT_FREE_PAGE) +#define BIT_SET_LLT_FREE_PAGE(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE(x) | BIT_LLT_FREE_PAGE(v)) -/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_LLT_FREE_PAGE_V1 8 -#define BIT_MASK_LLT_FREE_PAGE_V1 0xffff -#define BIT_LLT_FREE_PAGE_V1(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1) << BIT_SHIFT_LLT_FREE_PAGE_V1) -#define BIT_GET_LLT_FREE_PAGE_V1(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1) & BIT_MASK_LLT_FREE_PAGE_V1) +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 24 +#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 0xff +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) +#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 \ + (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) +#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ + ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) & \ + BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) +#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) | \ + BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(v)) #endif - -#if (HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_SHIFT_MAX_TX_PKT_V1 24 +#define BIT_MASK_MAX_TX_PKT_V1 0xff +#define BIT_MAX_TX_PKT_V1(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_V1) << BIT_SHIFT_MAX_TX_PKT_V1) +#define BITS_MAX_TX_PKT_V1 (BIT_MASK_MAX_TX_PKT_V1 << BIT_SHIFT_MAX_TX_PKT_V1) +#define BIT_CLEAR_MAX_TX_PKT_V1(x) ((x) & (~BITS_MAX_TX_PKT_V1)) +#define BIT_GET_MAX_TX_PKT_V1(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_V1) & BIT_MASK_MAX_TX_PKT_V1) +#define BIT_SET_MAX_TX_PKT_V1(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_V1(x) | BIT_MAX_TX_PKT_V1(v)) -#define BIT_SHIFT_LLT_FREE_PAGE_V2 8 -#define BIT_MASK_LLT_FREE_PAGE_V2 0xfff -#define BIT_LLT_FREE_PAGE_V2(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V2) << BIT_SHIFT_LLT_FREE_PAGE_V2) -#define BIT_GET_LLT_FREE_PAGE_V2(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2) & BIT_MASK_LLT_FREE_PAGE_V2) +#endif +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_TDE_ERROR_STOP_V1 BIT(23) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ +#define BIT_BCN_VALID BIT(16) -#define BIT_SHIFT_BLK_DESC_NUM 4 -#define BIT_MASK_BLK_DESC_NUM 0xf -#define BIT_BLK_DESC_NUM(x) (((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM) -#define BIT_GET_BLK_DESC_NUM(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM) - +#define BIT_SHIFT_BCN_HEAD 8 +#define BIT_MASK_BCN_HEAD 0xff +#define BIT_BCN_HEAD(x) (((x) & BIT_MASK_BCN_HEAD) << BIT_SHIFT_BCN_HEAD) +#define BITS_BCN_HEAD (BIT_MASK_BCN_HEAD << BIT_SHIFT_BCN_HEAD) +#define BIT_CLEAR_BCN_HEAD(x) ((x) & (~BITS_BCN_HEAD)) +#define BIT_GET_BCN_HEAD(x) (((x) >> BIT_SHIFT_BCN_HEAD) & BIT_MASK_BCN_HEAD) +#define BIT_SET_BCN_HEAD(x, v) (BIT_CLEAR_BCN_HEAD(x) | BIT_BCN_HEAD(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ + +#define BIT_SHIFT_LLT_FREE_PAGE_V1 8 +#define BIT_MASK_LLT_FREE_PAGE_V1 0xffff +#define BIT_LLT_FREE_PAGE_V1(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V1) << BIT_SHIFT_LLT_FREE_PAGE_V1) +#define BITS_LLT_FREE_PAGE_V1 \ + (BIT_MASK_LLT_FREE_PAGE_V1 << BIT_SHIFT_LLT_FREE_PAGE_V1) +#define BIT_CLEAR_LLT_FREE_PAGE_V1(x) ((x) & (~BITS_LLT_FREE_PAGE_V1)) +#define BIT_GET_LLT_FREE_PAGE_V1(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1) & BIT_MASK_LLT_FREE_PAGE_V1) +#define BIT_SET_LLT_FREE_PAGE_V1(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V1(x) | BIT_LLT_FREE_PAGE_V1(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ -#define BIT_R_BCN_HEAD_SEL BIT(3) -#define BIT_R_EN_BCN_SW_HEAD_SEL BIT(2) -#define BIT_LLT_DBG_SEL BIT(1) -#define BIT_AUTO_INIT_LLT_V1 BIT(0) +#define BIT_SHIFT_LLT_FREE_PAGE_V2 8 +#define BIT_MASK_LLT_FREE_PAGE_V2 0xfff +#define BIT_LLT_FREE_PAGE_V2(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V2) << BIT_SHIFT_LLT_FREE_PAGE_V2) +#define BITS_LLT_FREE_PAGE_V2 \ + (BIT_MASK_LLT_FREE_PAGE_V2 << BIT_SHIFT_LLT_FREE_PAGE_V2) +#define BIT_CLEAR_LLT_FREE_PAGE_V2(x) ((x) & (~BITS_LLT_FREE_PAGE_V2)) +#define BIT_GET_LLT_FREE_PAGE_V2(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2) & BIT_MASK_LLT_FREE_PAGE_V2) +#define BIT_SET_LLT_FREE_PAGE_V2(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V2(x) | BIT_LLT_FREE_PAGE_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ +#define BIT_SHIFT_BLK_DESC_NUM 4 +#define BIT_MASK_BLK_DESC_NUM 0xf +#define BIT_BLK_DESC_NUM(x) \ + (((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM) +#define BITS_BLK_DESC_NUM (BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM) +#define BIT_CLEAR_BLK_DESC_NUM(x) ((x) & (~BITS_BLK_DESC_NUM)) +#define BIT_GET_BLK_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM) +#define BIT_SET_BLK_DESC_NUM(x, v) \ + (BIT_CLEAR_BLK_DESC_NUM(x) | BIT_BLK_DESC_NUM(v)) -/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#endif -#define BIT_EM_CHKSUM_FIN BIT(31) -#define BIT_EMN_PCIE_DMA_MOD BIT(30) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_R_BCN_HEAD_SEL BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ -#define BIT_EN_TXQUE_CLR BIT(29) -#define BIT_EN_PCIE_FIFO_MODE BIT(28) +#define BIT_R_EN_BCN_SW_HEAD_SEL BIT(2) +#define BIT_LLT_DBG_SEL BIT(1) +#define BIT_AUTO_INIT_LLT_V1 BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_EM_CHKSUM_FIN BIT(31) +#define BIT_EMN_PCIE_DMA_MOD BIT(30) -/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PG_UNDER_TH 16 -#define BIT_MASK_PG_UNDER_TH 0xff -#define BIT_PG_UNDER_TH(x) (((x) & BIT_MASK_PG_UNDER_TH) << BIT_SHIFT_PG_UNDER_TH) -#define BIT_GET_PG_UNDER_TH(x) (((x) >> BIT_SHIFT_PG_UNDER_TH) & BIT_MASK_PG_UNDER_TH) +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_EN_TXQUE_CLR BIT(29) +#define BIT_EN_PCIE_FIFO_MODE BIT(28) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_SHIFT_PG_UNDER_TH 16 +#define BIT_MASK_PG_UNDER_TH 0xff +#define BIT_PG_UNDER_TH(x) \ + (((x) & BIT_MASK_PG_UNDER_TH) << BIT_SHIFT_PG_UNDER_TH) +#define BITS_PG_UNDER_TH (BIT_MASK_PG_UNDER_TH << BIT_SHIFT_PG_UNDER_TH) +#define BIT_CLEAR_PG_UNDER_TH(x) ((x) & (~BITS_PG_UNDER_TH)) +#define BIT_GET_PG_UNDER_TH(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH) & BIT_MASK_PG_UNDER_TH) +#define BIT_SET_PG_UNDER_TH(x, v) \ + (BIT_CLEAR_PG_UNDER_TH(x) | BIT_PG_UNDER_TH(v)) -/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PG_UNDER_TH_V1 16 -#define BIT_MASK_PG_UNDER_TH_V1 0xfff -#define BIT_PG_UNDER_TH_V1(x) (((x) & BIT_MASK_PG_UNDER_TH_V1) << BIT_SHIFT_PG_UNDER_TH_V1) -#define BIT_GET_PG_UNDER_TH_V1(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1) & BIT_MASK_PG_UNDER_TH_V1) +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_SHIFT_PG_UNDER_TH_V1 16 +#define BIT_MASK_PG_UNDER_TH_V1 0xfff +#define BIT_PG_UNDER_TH_V1(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V1) << BIT_SHIFT_PG_UNDER_TH_V1) +#define BITS_PG_UNDER_TH_V1 \ + (BIT_MASK_PG_UNDER_TH_V1 << BIT_SHIFT_PG_UNDER_TH_V1) +#define BIT_CLEAR_PG_UNDER_TH_V1(x) ((x) & (~BITS_PG_UNDER_TH_V1)) +#define BIT_GET_PG_UNDER_TH_V1(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V1) & BIT_MASK_PG_UNDER_TH_V1) +#define BIT_SET_PG_UNDER_TH_V1(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V1(x) | BIT_PG_UNDER_TH_V1(v)) #endif - #if (HALMAC_8197F_SUPPORT) - /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ -#define BIT_EN_RESET_RESTORE_H2C BIT(15) +#define BIT_EN_RESET_RESTORE_H2C BIT(15) #endif - -#if (HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ -#define BIT_RESTORE_H2C_ADDRESS BIT(15) +#define BIT_R_EN_RESET_RESTORE_H2C BIT(15) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8822B_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ -#define BIT_SDIO_TDE_FINISH BIT(14) +#define BIT_RESTORE_H2C_ADDRESS BIT(15) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ -#define BIT_SDIO_TXDESC_CHKSUM_EN BIT(13) -#define BIT_RST_RDPTR BIT(12) -#define BIT_RST_WRPTR BIT(11) -#define BIT_CHK_PG_TH_EN BIT(10) -#define BIT_DROP_DATA_EN BIT(9) -#define BIT_CHECK_OFFSET_EN BIT(8) +#define BIT_SDIO_TDE_FINISH BIT(14) + +#endif -#define BIT_SHIFT_CHECK_OFFSET 0 -#define BIT_MASK_CHECK_OFFSET 0xff -#define BIT_CHECK_OFFSET(x) (((x) & BIT_MASK_CHECK_OFFSET) << BIT_SHIFT_CHECK_OFFSET) -#define BIT_GET_CHECK_OFFSET(x) (((x) >> BIT_SHIFT_CHECK_OFFSET) & BIT_MASK_CHECK_OFFSET) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ -#endif +#define BIT_SDIO_TXDESC_CHKSUM_EN BIT(13) +#define BIT_RST_RDPTR BIT(12) +#define BIT_RST_WRPTR BIT(11) +#define BIT_CHK_PG_TH_EN BIT(10) +#define BIT_DROP_DATA_EN BIT(9) +#define BIT_CHECK_OFFSET_EN BIT(8) +#define BIT_SHIFT_CHECK_OFFSET 0 +#define BIT_MASK_CHECK_OFFSET 0xff +#define BIT_CHECK_OFFSET(x) \ + (((x) & BIT_MASK_CHECK_OFFSET) << BIT_SHIFT_CHECK_OFFSET) +#define BITS_CHECK_OFFSET (BIT_MASK_CHECK_OFFSET << BIT_SHIFT_CHECK_OFFSET) +#define BIT_CLEAR_CHECK_OFFSET(x) ((x) & (~BITS_CHECK_OFFSET)) +#define BIT_GET_CHECK_OFFSET(x) \ + (((x) >> BIT_SHIFT_CHECK_OFFSET) & BIT_MASK_CHECK_OFFSET) +#define BIT_SET_CHECK_OFFSET(x, v) \ + (BIT_CLEAR_CHECK_OFFSET(x) | BIT_CHECK_OFFSET(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ -#define BIT_TXPKTBUF_REQ_ERR BIT(18) +#define BIT_AMSDU_PKT_SIZE_ERR BIT(31) +#define BIT_AMSDU_EN_ERR BIT(30) +#define BIT_CHKSUM_AMSDU_EN_ERR BIT(29) +#define BIT_TXPKTBF_REQ_ERR BIT(28) +#define BIT_OQT_UDN_16 BIT(27) +#define BIT_OQT_OVF_16 BIT(26) +#define BIT_OQT_UDN_14_15 BIT(25) +#define BIT_OQT_OVF_14_15 BIT(24) +#define BIT_OQT_UDN_13 BIT(23) +#define BIT_OQT_OVF_13 BIT(22) +#define BIT_OQT_UDN_12 BIT(21) +#define BIT_OQT_OVF_12 BIT(20) +#define BIT_OQT_UDN_8_11 BIT(19) +#define BIT_OQT_OVF_8_11 BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ -#define BIT_HI_OQT_UDN BIT(17) -#define BIT_HI_OQT_OVF BIT(16) -#define BIT_PAYLOAD_CHKSUM_ERR BIT(15) -#define BIT_PAYLOAD_UDN BIT(14) -#define BIT_PAYLOAD_OVF BIT(13) -#define BIT_DSC_CHKSUM_FAIL BIT(12) -#define BIT_UNKNOWN_QSEL BIT(11) -#define BIT_EP_QSEL_DIFF BIT(10) -#define BIT_TX_OFFS_UNMATCH BIT(9) -#define BIT_TXOQT_UDN BIT(8) -#define BIT_TXOQT_OVF BIT(7) -#define BIT_TXDMA_SFF_UDN BIT(6) -#define BIT_TXDMA_SFF_OVF BIT(5) -#define BIT_LLT_NULL_PG BIT(4) -#define BIT_PAGE_UDN BIT(3) -#define BIT_PAGE_OVF BIT(2) -#define BIT_TXFF_PG_UDN BIT(1) -#define BIT_TXFF_PG_OVF BIT(0) +#define BIT_TXPKTBUF_REQ_ERR BIT(18) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_RQPN_NPQ (Offset 0x0214) */ +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_HI_OQT_UDN BIT(17) -#define BIT_SHIFT_EXQ_AVAL_PG 24 -#define BIT_MASK_EXQ_AVAL_PG 0xff -#define BIT_EXQ_AVAL_PG(x) (((x) & BIT_MASK_EXQ_AVAL_PG) << BIT_SHIFT_EXQ_AVAL_PG) -#define BIT_GET_EXQ_AVAL_PG(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG) & BIT_MASK_EXQ_AVAL_PG) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_EXQ 16 -#define BIT_MASK_EXQ 0xff -#define BIT_EXQ(x) (((x) & BIT_MASK_EXQ) << BIT_SHIFT_EXQ) -#define BIT_GET_EXQ(x) (((x) >> BIT_SHIFT_EXQ) & BIT_MASK_EXQ) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_OQT_UDN_4_7 BIT(17) -#define BIT_SHIFT_NPQ 0 -#define BIT_MASK_NPQ 0xff -#define BIT_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ) -#define BIT_GET_NPQ(x) (((x) >> BIT_SHIFT_NPQ) & BIT_MASK_NPQ) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_TQPNT1 (Offset 0x0218) */ +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_HI_OQT_OVF BIT(16) -#define BIT_SHIFT_NPQ_HIGH_TH 24 -#define BIT_MASK_NPQ_HIGH_TH 0xff -#define BIT_NPQ_HIGH_TH(x) (((x) & BIT_MASK_NPQ_HIGH_TH) << BIT_SHIFT_NPQ_HIGH_TH) -#define BIT_GET_NPQ_HIGH_TH(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH) & BIT_MASK_NPQ_HIGH_TH) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_NPQ_LOW_TH 16 -#define BIT_MASK_NPQ_LOW_TH 0xff -#define BIT_NPQ_LOW_TH(x) (((x) & BIT_MASK_NPQ_LOW_TH) << BIT_SHIFT_NPQ_LOW_TH) -#define BIT_GET_NPQ_LOW_TH(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH) & BIT_MASK_NPQ_LOW_TH) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_OQT_OVF_4_7 BIT(16) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_PAYLOAD_CHKSUM_ERR BIT(15) -/* 2 REG_TQPNT1 (Offset 0x0218) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HPQ_HIGH_TH_V1 16 -#define BIT_MASK_HPQ_HIGH_TH_V1 0xfff -#define BIT_HPQ_HIGH_TH_V1(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1) << BIT_SHIFT_HPQ_HIGH_TH_V1) -#define BIT_GET_HPQ_HIGH_TH_V1(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1) & BIT_MASK_HPQ_HIGH_TH_V1) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_RX_CLOSE_EN BIT(15) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_PAYLOAD_UDN BIT(14) -/* 2 REG_TQPNT1 (Offset 0x0218) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ + +#define BIT_STOP_BCNQ BIT(14) -#define BIT_SHIFT_HPQ_HIGH_TH 8 -#define BIT_MASK_HPQ_HIGH_TH 0xff -#define BIT_HPQ_HIGH_TH(x) (((x) & BIT_MASK_HPQ_HIGH_TH) << BIT_SHIFT_HPQ_HIGH_TH) -#define BIT_GET_HPQ_HIGH_TH(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH) & BIT_MASK_HPQ_HIGH_TH) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HPQ_LOW_TH 0 -#define BIT_MASK_HPQ_LOW_TH 0xff -#define BIT_HPQ_LOW_TH(x) (((x) & BIT_MASK_HPQ_LOW_TH) << BIT_SHIFT_HPQ_LOW_TH) -#define BIT_GET_HPQ_LOW_TH(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH) & BIT_MASK_HPQ_LOW_TH) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_PAYLOAD_OVF BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_MGQ BIT(13) -/* 2 REG_TQPNT1 (Offset 0x0218) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HPQ_LOW_TH_V1 0 -#define BIT_MASK_HPQ_LOW_TH_V1 0xfff -#define BIT_HPQ_LOW_TH_V1(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1) << BIT_SHIFT_HPQ_LOW_TH_V1) -#define BIT_GET_HPQ_LOW_TH_V1(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1) & BIT_MASK_HPQ_LOW_TH_V1) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_DSC_CHKSUM_FAIL BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_VOQ BIT(12) +#define BIT_UNKNOWN_QSEL BIT(11) +#define BIT_STOP_VIQ BIT(11) -/* 2 REG_TQPNT2 (Offset 0x021C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_EXQ_HIGH_TH 24 -#define BIT_MASK_EXQ_HIGH_TH 0xff -#define BIT_EXQ_HIGH_TH(x) (((x) & BIT_MASK_EXQ_HIGH_TH) << BIT_SHIFT_EXQ_HIGH_TH) -#define BIT_GET_EXQ_HIGH_TH(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH) & BIT_MASK_EXQ_HIGH_TH) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ + +#define BIT_EP_QSEL_DIFF BIT(10) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_EXQ_LOW_TH 16 -#define BIT_MASK_EXQ_LOW_TH 0xff -#define BIT_EXQ_LOW_TH(x) (((x) & BIT_MASK_EXQ_LOW_TH) << BIT_SHIFT_EXQ_LOW_TH) -#define BIT_GET_EXQ_LOW_TH(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH) & BIT_MASK_EXQ_LOW_TH) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_BEQ BIT(10) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TX_OFFS_UNMATCH BIT(9) -/* 2 REG_TQPNT2 (Offset 0x021C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NPQ_HIGH_TH_V1 16 -#define BIT_MASK_NPQ_HIGH_TH_V1 0xfff -#define BIT_NPQ_HIGH_TH_V1(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1) << BIT_SHIFT_NPQ_HIGH_TH_V1) -#define BIT_GET_NPQ_HIGH_TH_V1(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1) & BIT_MASK_NPQ_HIGH_TH_V1) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_BKQ BIT(9) +#define BIT_TXOQT_UDN BIT(8) +#define BIT_STOP_RXQ BIT(8) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXOQT_UDN_0_3 BIT(8) -/* 2 REG_TQPNT2 (Offset 0x021C) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXOQT_OVF BIT(7) +#define BIT_STOP_HI7Q BIT(7) -#define BIT_SHIFT_LPQ_HIGH_TH 8 -#define BIT_MASK_LPQ_HIGH_TH 0xff -#define BIT_LPQ_HIGH_TH(x) (((x) & BIT_MASK_LPQ_HIGH_TH) << BIT_SHIFT_LPQ_HIGH_TH) -#define BIT_GET_LPQ_HIGH_TH(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH) & BIT_MASK_LPQ_HIGH_TH) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_LPQ_LOW_TH 0 -#define BIT_MASK_LPQ_LOW_TH 0xff -#define BIT_LPQ_LOW_TH(x) (((x) & BIT_MASK_LPQ_LOW_TH) << BIT_SHIFT_LPQ_LOW_TH) -#define BIT_GET_LPQ_LOW_TH(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH) & BIT_MASK_LPQ_LOW_TH) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXOQT_OVF_0_3 BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXDMA_SFF_UDN BIT(6) -/* 2 REG_TQPNT2 (Offset 0x021C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NPQ_LOW_TH_V1 0 -#define BIT_MASK_NPQ_LOW_TH_V1 0xfff -#define BIT_NPQ_LOW_TH_V1(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1) << BIT_SHIFT_NPQ_LOW_TH_V1) -#define BIT_GET_NPQ_LOW_TH_V1(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1) & BIT_MASK_NPQ_LOW_TH_V1) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_HI6Q BIT(6) -/* 2 REG_TQPNT3 (Offset 0x0220) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LPQ_HIGH_TH_V1 16 -#define BIT_MASK_LPQ_HIGH_TH_V1 0xfff -#define BIT_LPQ_HIGH_TH_V1(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1) << BIT_SHIFT_LPQ_HIGH_TH_V1) -#define BIT_GET_LPQ_HIGH_TH_V1(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1) & BIT_MASK_LPQ_HIGH_TH_V1) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXDMA_SFF_OVF BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_HI5Q BIT(5) -/* 2 REG_TDE_DEBUG (Offset 0x0220) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TDE_DEBUG 0 -#define BIT_MASK_TDE_DEBUG 0xffffffffL -#define BIT_TDE_DEBUG(x) (((x) & BIT_MASK_TDE_DEBUG) << BIT_SHIFT_TDE_DEBUG) -#define BIT_GET_TDE_DEBUG(x) (((x) >> BIT_SHIFT_TDE_DEBUG) & BIT_MASK_TDE_DEBUG) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_LLT_NULL_PG BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_HI4Q BIT(4) -/* 2 REG_TQPNT3 (Offset 0x0220) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LPQ_LOW_TH_V1 0 -#define BIT_MASK_LPQ_LOW_TH_V1 0xfff -#define BIT_LPQ_LOW_TH_V1(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1) << BIT_SHIFT_LPQ_LOW_TH_V1) -#define BIT_GET_LPQ_LOW_TH_V1(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1) & BIT_MASK_LPQ_LOW_TH_V1) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_PAGE_UDN BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_HI3Q BIT(3) -/* 2 REG_AUTO_LLT (Offset 0x0224) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TXPKTNUM_V1 24 -#define BIT_MASK_TXPKTNUM_V1 0xff -#define BIT_TXPKTNUM_V1(x) (((x) & BIT_MASK_TXPKTNUM_V1) << BIT_SHIFT_TXPKTNUM_V1) -#define BIT_GET_TXPKTNUM_V1(x) (((x) >> BIT_SHIFT_TXPKTNUM_V1) & BIT_MASK_TXPKTNUM_V1) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ -#define BIT_TDE_DBG_SEL BIT(23) -#define BIT_AUTO_INIT_LLT BIT(16) +#define BIT_PAGE_OVF BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_HI2Q BIT(2) -/* 2 REG_TQPNT4 (Offset 0x0224) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_EXQ_HIGH_TH_V1 16 -#define BIT_MASK_EXQ_HIGH_TH_V1 0xfff -#define BIT_EXQ_HIGH_TH_V1(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1) << BIT_SHIFT_EXQ_HIGH_TH_V1) -#define BIT_GET_EXQ_HIGH_TH_V1(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1) & BIT_MASK_EXQ_HIGH_TH_V1) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXFF_PG_UDN BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_HI1Q BIT(1) -/* 2 REG_AUTO_LLT (Offset 0x0224) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE 8 -#define BIT_MASK_TX_OQT_HE_FREE_SPACE 0xff -#define BIT_TX_OQT_HE_FREE_SPACE(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE) -#define BIT_GET_TX_OQT_HE_FREE_SPACE(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE) & BIT_MASK_TX_OQT_HE_FREE_SPACE) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXFF_PG_OVF BIT(0) -#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE 0 -#define BIT_MASK_TX_OQT_NL_FREE_SPACE 0xff -#define BIT_TX_OQT_NL_FREE_SPACE(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE) -#define BIT_GET_TX_OQT_NL_FREE_SPACE(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE) & BIT_MASK_TX_OQT_NL_FREE_SPACE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_HI0Q BIT(0) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_TQPNT4 (Offset 0x0224) */ +/* 2 REG_RQPN_NPQ (Offset 0x0214) */ +#define BIT_SHIFT_EXQ_AVAL_PG 24 +#define BIT_MASK_EXQ_AVAL_PG 0xff +#define BIT_EXQ_AVAL_PG(x) \ + (((x) & BIT_MASK_EXQ_AVAL_PG) << BIT_SHIFT_EXQ_AVAL_PG) +#define BITS_EXQ_AVAL_PG (BIT_MASK_EXQ_AVAL_PG << BIT_SHIFT_EXQ_AVAL_PG) +#define BIT_CLEAR_EXQ_AVAL_PG(x) ((x) & (~BITS_EXQ_AVAL_PG)) +#define BIT_GET_EXQ_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_EXQ_AVAL_PG) & BIT_MASK_EXQ_AVAL_PG) +#define BIT_SET_EXQ_AVAL_PG(x, v) \ + (BIT_CLEAR_EXQ_AVAL_PG(x) | BIT_EXQ_AVAL_PG(v)) + +#define BIT_SHIFT_EXQ 16 +#define BIT_MASK_EXQ 0xff +#define BIT_EXQ(x) (((x) & BIT_MASK_EXQ) << BIT_SHIFT_EXQ) +#define BITS_EXQ (BIT_MASK_EXQ << BIT_SHIFT_EXQ) +#define BIT_CLEAR_EXQ(x) ((x) & (~BITS_EXQ)) +#define BIT_GET_EXQ(x) (((x) >> BIT_SHIFT_EXQ) & BIT_MASK_EXQ) +#define BIT_SET_EXQ(x, v) (BIT_CLEAR_EXQ(x) | BIT_EXQ(v)) + +#define BIT_SHIFT_NPQ 0 +#define BIT_MASK_NPQ 0xff +#define BIT_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ) +#define BITS_NPQ (BIT_MASK_NPQ << BIT_SHIFT_NPQ) +#define BIT_CLEAR_NPQ(x) ((x) & (~BITS_NPQ)) +#define BIT_GET_NPQ(x) (((x) >> BIT_SHIFT_NPQ) & BIT_MASK_NPQ) +#define BIT_SET_NPQ(x, v) (BIT_CLEAR_NPQ(x) | BIT_NPQ(v)) + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_EXQ_LOW_TH_V1 0 -#define BIT_MASK_EXQ_LOW_TH_V1 0xfff -#define BIT_EXQ_LOW_TH_V1(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1) << BIT_SHIFT_EXQ_LOW_TH_V1) -#define BIT_GET_EXQ_LOW_TH_V1(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1) & BIT_MASK_EXQ_LOW_TH_V1) +/* 2 REG_TQPNT1 (Offset 0x0218) */ +#define BIT_HPQ_INT_EN BIT(31) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TQPNT1 (Offset 0x0218) */ -/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ +#define BIT_SHIFT_NPQ_HIGH_TH 24 +#define BIT_MASK_NPQ_HIGH_TH 0xff +#define BIT_NPQ_HIGH_TH(x) \ + (((x) & BIT_MASK_NPQ_HIGH_TH) << BIT_SHIFT_NPQ_HIGH_TH) +#define BITS_NPQ_HIGH_TH (BIT_MASK_NPQ_HIGH_TH << BIT_SHIFT_NPQ_HIGH_TH) +#define BIT_CLEAR_NPQ_HIGH_TH(x) ((x) & (~BITS_NPQ_HIGH_TH)) +#define BIT_GET_NPQ_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_NPQ_HIGH_TH) & BIT_MASK_NPQ_HIGH_TH) +#define BIT_SET_NPQ_HIGH_TH(x, v) \ + (BIT_CLEAR_NPQ_HIGH_TH(x) | BIT_NPQ_HIGH_TH(v)) -#define BIT_SW_BCN_SEL BIT(20) -#define BIT_SW_BCN_SEL_EN BIT(17) -#define BIT_BCN_VALID_1 BIT(16) +#define BIT_SHIFT_NPQ_LOW_TH 16 +#define BIT_MASK_NPQ_LOW_TH 0xff +#define BIT_NPQ_LOW_TH(x) (((x) & BIT_MASK_NPQ_LOW_TH) << BIT_SHIFT_NPQ_LOW_TH) +#define BITS_NPQ_LOW_TH (BIT_MASK_NPQ_LOW_TH << BIT_SHIFT_NPQ_LOW_TH) +#define BIT_CLEAR_NPQ_LOW_TH(x) ((x) & (~BITS_NPQ_LOW_TH)) +#define BIT_GET_NPQ_LOW_TH(x) \ + (((x) >> BIT_SHIFT_NPQ_LOW_TH) & BIT_MASK_NPQ_LOW_TH) +#define BIT_SET_NPQ_LOW_TH(x, v) (BIT_CLEAR_NPQ_LOW_TH(x) | BIT_NPQ_LOW_TH(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TQPNT1 (Offset 0x0218) */ +#define BIT_SHIFT_HPQ_HIGH_TH_V1 16 +#define BIT_MASK_HPQ_HIGH_TH_V1 0xfff +#define BIT_HPQ_HIGH_TH_V1(x) \ + (((x) & BIT_MASK_HPQ_HIGH_TH_V1) << BIT_SHIFT_HPQ_HIGH_TH_V1) +#define BITS_HPQ_HIGH_TH_V1 \ + (BIT_MASK_HPQ_HIGH_TH_V1 << BIT_SHIFT_HPQ_HIGH_TH_V1) +#define BIT_CLEAR_HPQ_HIGH_TH_V1(x) ((x) & (~BITS_HPQ_HIGH_TH_V1)) +#define BIT_GET_HPQ_HIGH_TH_V1(x) \ + (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1) & BIT_MASK_HPQ_HIGH_TH_V1) +#define BIT_SET_HPQ_HIGH_TH_V1(x, v) \ + (BIT_CLEAR_HPQ_HIGH_TH_V1(x) | BIT_HPQ_HIGH_TH_V1(v)) -/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TXPKTNUM_H 16 -#define BIT_MASK_TXPKTNUM_H 0xffff -#define BIT_TXPKTNUM_H(x) (((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H) -#define BIT_GET_TXPKTNUM_H(x) (((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H) +/* 2 REG_DMA_RQPN_INFO_PUB (Offset 0x0218) */ +#define BIT_SHIFT_PUB_AVAL_PG 16 +#define BIT_MASK_PUB_AVAL_PG 0xfff +#define BIT_PUB_AVAL_PG(x) \ + (((x) & BIT_MASK_PUB_AVAL_PG) << BIT_SHIFT_PUB_AVAL_PG) +#define BITS_PUB_AVAL_PG (BIT_MASK_PUB_AVAL_PG << BIT_SHIFT_PUB_AVAL_PG) +#define BIT_CLEAR_PUB_AVAL_PG(x) ((x) & (~BITS_PUB_AVAL_PG)) +#define BIT_GET_PUB_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_PUB_AVAL_PG) & BIT_MASK_PUB_AVAL_PG) +#define BIT_SET_PUB_AVAL_PG(x, v) \ + (BIT_CLEAR_PUB_AVAL_PG(x) | BIT_PUB_AVAL_PG(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TQPNT1 (Offset 0x0218) */ -/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ +#define BIT_SHIFT_HPQ_HIGH_TH 8 +#define BIT_MASK_HPQ_HIGH_TH 0xff +#define BIT_HPQ_HIGH_TH(x) \ + (((x) & BIT_MASK_HPQ_HIGH_TH) << BIT_SHIFT_HPQ_HIGH_TH) +#define BITS_HPQ_HIGH_TH (BIT_MASK_HPQ_HIGH_TH << BIT_SHIFT_HPQ_HIGH_TH) +#define BIT_CLEAR_HPQ_HIGH_TH(x) ((x) & (~BITS_HPQ_HIGH_TH)) +#define BIT_GET_HPQ_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_HPQ_HIGH_TH) & BIT_MASK_HPQ_HIGH_TH) +#define BIT_SET_HPQ_HIGH_TH(x, v) \ + (BIT_CLEAR_HPQ_HIGH_TH(x) | BIT_HPQ_HIGH_TH(v)) +#define BIT_SHIFT_HPQ_LOW_TH 0 +#define BIT_MASK_HPQ_LOW_TH 0xff +#define BIT_HPQ_LOW_TH(x) (((x) & BIT_MASK_HPQ_LOW_TH) << BIT_SHIFT_HPQ_LOW_TH) +#define BITS_HPQ_LOW_TH (BIT_MASK_HPQ_LOW_TH << BIT_SHIFT_HPQ_LOW_TH) +#define BIT_CLEAR_HPQ_LOW_TH(x) ((x) & (~BITS_HPQ_LOW_TH)) +#define BIT_GET_HPQ_LOW_TH(x) \ + (((x) >> BIT_SHIFT_HPQ_LOW_TH) & BIT_MASK_HPQ_LOW_TH) +#define BIT_SET_HPQ_LOW_TH(x, v) (BIT_CLEAR_HPQ_LOW_TH(x) | BIT_HPQ_LOW_TH(v)) -#define BIT_SHIFT_BCN_HEAD_1 8 -#define BIT_MASK_BCN_HEAD_1 0xff -#define BIT_BCN_HEAD_1(x) (((x) & BIT_MASK_BCN_HEAD_1) << BIT_SHIFT_BCN_HEAD_1) -#define BIT_GET_BCN_HEAD_1(x) (((x) >> BIT_SHIFT_BCN_HEAD_1) & BIT_MASK_BCN_HEAD_1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO 0 -#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO 0xff -#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) -#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO) +/* 2 REG_TQPNT1 (Offset 0x0218) */ +#define BIT_SHIFT_HPQ_LOW_TH_V1 0 +#define BIT_MASK_HPQ_LOW_TH_V1 0xfff +#define BIT_HPQ_LOW_TH_V1(x) \ + (((x) & BIT_MASK_HPQ_LOW_TH_V1) << BIT_SHIFT_HPQ_LOW_TH_V1) +#define BITS_HPQ_LOW_TH_V1 (BIT_MASK_HPQ_LOW_TH_V1 << BIT_SHIFT_HPQ_LOW_TH_V1) +#define BIT_CLEAR_HPQ_LOW_TH_V1(x) ((x) & (~BITS_HPQ_LOW_TH_V1)) +#define BIT_GET_HPQ_LOW_TH_V1(x) \ + (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1) & BIT_MASK_HPQ_LOW_TH_V1) +#define BIT_SET_HPQ_LOW_TH_V1(x, v) \ + (BIT_CLEAR_HPQ_LOW_TH_V1(x) | BIT_HPQ_LOW_TH_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +/* 2 REG_DMA_RQPN_INFO_PUB (Offset 0x0218) */ +#define BIT_SHIFT_PUB_RSVD_PG 0 +#define BIT_MASK_PUB_RSVD_PG 0xfff +#define BIT_PUB_RSVD_PG(x) \ + (((x) & BIT_MASK_PUB_RSVD_PG) << BIT_SHIFT_PUB_RSVD_PG) +#define BITS_PUB_RSVD_PG (BIT_MASK_PUB_RSVD_PG << BIT_SHIFT_PUB_RSVD_PG) +#define BIT_CLEAR_PUB_RSVD_PG(x) ((x) & (~BITS_PUB_RSVD_PG)) +#define BIT_GET_PUB_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_PUB_RSVD_PG) & BIT_MASK_PUB_RSVD_PG) +#define BIT_SET_PUB_RSVD_PG(x, v) \ + (BIT_CLEAR_PUB_RSVD_PG(x) | BIT_PUB_RSVD_PG(v)) -#define BIT_SHIFT_TXPKTNUM_H_V1 0 -#define BIT_MASK_TXPKTNUM_H_V1 0xffff -#define BIT_TXPKTNUM_H_V1(x) (((x) & BIT_MASK_TXPKTNUM_H_V1) << BIT_SHIFT_TXPKTNUM_H_V1) -#define BIT_GET_TXPKTNUM_H_V1(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_V1) & BIT_MASK_TXPKTNUM_H_V1) +/* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */ +#define BIT_LD_RQPN_V1 BIT(31) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_TQPNT2 (Offset 0x021C) */ -/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +#define BIT_NPQ_INT_EN BIT(31) +#endif -#define BIT_SHIFT_TXPKTNUM_V2 0 -#define BIT_MASK_TXPKTNUM_V2 0xffff -#define BIT_TXPKTNUM_V2(x) (((x) & BIT_MASK_TXPKTNUM_V2) << BIT_SHIFT_TXPKTNUM_V2) -#define BIT_GET_TXPKTNUM_V2(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2) & BIT_MASK_TXPKTNUM_V2) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TQPNT2 (Offset 0x021C) */ -#endif +#define BIT_SHIFT_EXQ_HIGH_TH 24 +#define BIT_MASK_EXQ_HIGH_TH 0xff +#define BIT_EXQ_HIGH_TH(x) \ + (((x) & BIT_MASK_EXQ_HIGH_TH) << BIT_SHIFT_EXQ_HIGH_TH) +#define BITS_EXQ_HIGH_TH (BIT_MASK_EXQ_HIGH_TH << BIT_SHIFT_EXQ_HIGH_TH) +#define BIT_CLEAR_EXQ_HIGH_TH(x) ((x) & (~BITS_EXQ_HIGH_TH)) +#define BIT_GET_EXQ_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_EXQ_HIGH_TH) & BIT_MASK_EXQ_HIGH_TH) +#define BIT_SET_EXQ_HIGH_TH(x, v) \ + (BIT_CLEAR_EXQ_HIGH_TH(x) | BIT_EXQ_HIGH_TH(v)) +#define BIT_SHIFT_EXQ_LOW_TH 16 +#define BIT_MASK_EXQ_LOW_TH 0xff +#define BIT_EXQ_LOW_TH(x) (((x) & BIT_MASK_EXQ_LOW_TH) << BIT_SHIFT_EXQ_LOW_TH) +#define BITS_EXQ_LOW_TH (BIT_MASK_EXQ_LOW_TH << BIT_SHIFT_EXQ_LOW_TH) +#define BIT_CLEAR_EXQ_LOW_TH(x) ((x) & (~BITS_EXQ_LOW_TH)) +#define BIT_GET_EXQ_LOW_TH(x) \ + (((x) >> BIT_SHIFT_EXQ_LOW_TH) & BIT_MASK_EXQ_LOW_TH) +#define BIT_SET_EXQ_LOW_TH(x, v) (BIT_CLEAR_EXQ_LOW_TH(x) | BIT_EXQ_LOW_TH(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ +/* 2 REG_TQPNT2 (Offset 0x021C) */ -#define BIT_EXQ_PUBLIC_DIS_V1 BIT(19) -#define BIT_NPQ_PUBLIC_DIS_V1 BIT(18) -#define BIT_LPQ_PUBLIC_DIS_V1 BIT(17) -#define BIT_HPQ_PUBLIC_DIS_V1 BIT(16) +#define BIT_SHIFT_NPQ_HIGH_TH_V1 16 +#define BIT_MASK_NPQ_HIGH_TH_V1 0xfff +#define BIT_NPQ_HIGH_TH_V1(x) \ + (((x) & BIT_MASK_NPQ_HIGH_TH_V1) << BIT_SHIFT_NPQ_HIGH_TH_V1) +#define BITS_NPQ_HIGH_TH_V1 \ + (BIT_MASK_NPQ_HIGH_TH_V1 << BIT_SHIFT_NPQ_HIGH_TH_V1) +#define BIT_CLEAR_NPQ_HIGH_TH_V1(x) ((x) & (~BITS_NPQ_HIGH_TH_V1)) +#define BIT_GET_NPQ_HIGH_TH_V1(x) \ + (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1) & BIT_MASK_NPQ_HIGH_TH_V1) +#define BIT_SET_NPQ_HIGH_TH_V1(x, v) \ + (BIT_CLEAR_NPQ_HIGH_TH_V1(x) | BIT_NPQ_HIGH_TH_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */ +#define BIT_CH16_PUBLIC_DIS BIT(16) +#define BIT_CH15_PUBLIC_DIS BIT(15) +#define BIT_CH14_PUBLIC_DIS BIT(14) +#define BIT_CH13_PUBLIC_DIS BIT(13) +#define BIT_CH12_PUBLIC_DIS BIT(12) +#define BIT_CH11_PUBLIC_DIS BIT(11) +#define BIT_CH10_PUBLIC_DIS BIT(10) +#define BIT_CH9_PUBLIC_DIS BIT(9) -/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ +#endif -#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN BIT(15) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE 0 -#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE 0xfff -#define BIT_SDIO_TXAGG_ALIGN_SIZE(x) (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE) << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) -#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE(x) (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE) +/* 2 REG_TQPNT2 (Offset 0x021C) */ +#define BIT_SHIFT_LPQ_HIGH_TH 8 +#define BIT_MASK_LPQ_HIGH_TH 0xff +#define BIT_LPQ_HIGH_TH(x) \ + (((x) & BIT_MASK_LPQ_HIGH_TH) << BIT_SHIFT_LPQ_HIGH_TH) +#define BITS_LPQ_HIGH_TH (BIT_MASK_LPQ_HIGH_TH << BIT_SHIFT_LPQ_HIGH_TH) +#define BIT_CLEAR_LPQ_HIGH_TH(x) ((x) & (~BITS_LPQ_HIGH_TH)) +#define BIT_GET_LPQ_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_LPQ_HIGH_TH) & BIT_MASK_LPQ_HIGH_TH) +#define BIT_SET_LPQ_HIGH_TH(x, v) \ + (BIT_CLEAR_LPQ_HIGH_TH(x) | BIT_LPQ_HIGH_TH(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */ +#define BIT_CH8_PUBLIC_DIS BIT(8) +#define BIT_CH7_PUBLIC_DIS BIT(7) +#define BIT_CH6_PUBLIC_DIS BIT(6) +#define BIT_CH5_PUBLIC_DIS BIT(5) +#define BIT_CH4_PUBLIC_DIS BIT(4) +#define BIT_CH3_PUBLIC_DIS BIT(3) +#define BIT_CH2_PUBLIC_DIS BIT(2) +#define BIT_CH1_PUBLIC_DIS BIT(1) -/* 2 REG_FIFOPAGE_INFO_1 (Offset 0x0230) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HPQ_AVAL_PG_V1 16 -#define BIT_MASK_HPQ_AVAL_PG_V1 0xfff -#define BIT_HPQ_AVAL_PG_V1(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1) << BIT_SHIFT_HPQ_AVAL_PG_V1) -#define BIT_GET_HPQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1) & BIT_MASK_HPQ_AVAL_PG_V1) +/* 2 REG_TQPNT2 (Offset 0x021C) */ +#define BIT_SHIFT_LPQ_LOW_TH 0 +#define BIT_MASK_LPQ_LOW_TH 0xff +#define BIT_LPQ_LOW_TH(x) (((x) & BIT_MASK_LPQ_LOW_TH) << BIT_SHIFT_LPQ_LOW_TH) +#define BITS_LPQ_LOW_TH (BIT_MASK_LPQ_LOW_TH << BIT_SHIFT_LPQ_LOW_TH) +#define BIT_CLEAR_LPQ_LOW_TH(x) ((x) & (~BITS_LPQ_LOW_TH)) +#define BIT_GET_LPQ_LOW_TH(x) \ + (((x) >> BIT_SHIFT_LPQ_LOW_TH) & BIT_MASK_LPQ_LOW_TH) +#define BIT_SET_LPQ_LOW_TH(x, v) (BIT_CLEAR_LPQ_LOW_TH(x) | BIT_LPQ_LOW_TH(v)) -#define BIT_SHIFT_HPQ_V1 0 -#define BIT_MASK_HPQ_V1 0xfff -#define BIT_HPQ_V1(x) (((x) & BIT_MASK_HPQ_V1) << BIT_SHIFT_HPQ_V1) -#define BIT_GET_HPQ_V1(x) (((x) >> BIT_SHIFT_HPQ_V1) & BIT_MASK_HPQ_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FIFOPAGE_INFO_2 (Offset 0x0234) */ +/* 2 REG_TQPNT2 (Offset 0x021C) */ + +#define BIT_SHIFT_NPQ_LOW_TH_V1 0 +#define BIT_MASK_NPQ_LOW_TH_V1 0xfff +#define BIT_NPQ_LOW_TH_V1(x) \ + (((x) & BIT_MASK_NPQ_LOW_TH_V1) << BIT_SHIFT_NPQ_LOW_TH_V1) +#define BITS_NPQ_LOW_TH_V1 (BIT_MASK_NPQ_LOW_TH_V1 << BIT_SHIFT_NPQ_LOW_TH_V1) +#define BIT_CLEAR_NPQ_LOW_TH_V1(x) ((x) & (~BITS_NPQ_LOW_TH_V1)) +#define BIT_GET_NPQ_LOW_TH_V1(x) \ + (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1) & BIT_MASK_NPQ_LOW_TH_V1) +#define BIT_SET_NPQ_LOW_TH_V1(x, v) \ + (BIT_CLEAR_NPQ_LOW_TH_V1(x) | BIT_NPQ_LOW_TH_V1(v)) + +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_LPQ_AVAL_PG_V1 16 -#define BIT_MASK_LPQ_AVAL_PG_V1 0xfff -#define BIT_LPQ_AVAL_PG_V1(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1) << BIT_SHIFT_LPQ_AVAL_PG_V1) -#define BIT_GET_LPQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1) & BIT_MASK_LPQ_AVAL_PG_V1) +/* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */ +#define BIT_CH0_PUBLIC_DIS BIT(0) -#define BIT_SHIFT_LPQ_V1 0 -#define BIT_MASK_LPQ_V1 0xfff -#define BIT_LPQ_V1(x) (((x) & BIT_MASK_LPQ_V1) << BIT_SHIFT_LPQ_V1) -#define BIT_GET_LPQ_V1(x) (((x) >> BIT_SHIFT_LPQ_V1) & BIT_MASK_LPQ_V1) +/* 2 REG_BCN_CTRL_2 (Offset 0x0220) */ +#define BIT_BCN0_EXT_VALID BIT(31) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TQPNT3 (Offset 0x0220) */ +#define BIT_LPQ_INT_EN BIT(31) -/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NPQ_AVAL_PG_V1 16 -#define BIT_MASK_NPQ_AVAL_PG_V1 0xfff -#define BIT_NPQ_AVAL_PG_V1(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1) << BIT_SHIFT_NPQ_AVAL_PG_V1) -#define BIT_GET_NPQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1) & BIT_MASK_NPQ_AVAL_PG_V1) +/* 2 REG_TQPNT3 (Offset 0x0220) */ +#define BIT_SHIFT_LPQ_HIGH_TH_V1 16 +#define BIT_MASK_LPQ_HIGH_TH_V1 0xfff +#define BIT_LPQ_HIGH_TH_V1(x) \ + (((x) & BIT_MASK_LPQ_HIGH_TH_V1) << BIT_SHIFT_LPQ_HIGH_TH_V1) +#define BITS_LPQ_HIGH_TH_V1 \ + (BIT_MASK_LPQ_HIGH_TH_V1 << BIT_SHIFT_LPQ_HIGH_TH_V1) +#define BIT_CLEAR_LPQ_HIGH_TH_V1(x) ((x) & (~BITS_LPQ_HIGH_TH_V1)) +#define BIT_GET_LPQ_HIGH_TH_V1(x) \ + (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1) & BIT_MASK_LPQ_HIGH_TH_V1) +#define BIT_SET_LPQ_HIGH_TH_V1(x, v) \ + (BIT_CLEAR_LPQ_HIGH_TH_V1(x) | BIT_LPQ_HIGH_TH_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_BCN_CTRL_2 (Offset 0x0220) */ + +#define BIT_SHIFT_BCN0_EXT_HEAD 16 +#define BIT_MASK_BCN0_EXT_HEAD 0xfff +#define BIT_BCN0_EXT_HEAD(x) \ + (((x) & BIT_MASK_BCN0_EXT_HEAD) << BIT_SHIFT_BCN0_EXT_HEAD) +#define BITS_BCN0_EXT_HEAD (BIT_MASK_BCN0_EXT_HEAD << BIT_SHIFT_BCN0_EXT_HEAD) +#define BIT_CLEAR_BCN0_EXT_HEAD(x) ((x) & (~BITS_BCN0_EXT_HEAD)) +#define BIT_GET_BCN0_EXT_HEAD(x) \ + (((x) >> BIT_SHIFT_BCN0_EXT_HEAD) & BIT_MASK_BCN0_EXT_HEAD) +#define BIT_SET_BCN0_EXT_HEAD(x, v) \ + (BIT_CLEAR_BCN0_EXT_HEAD(x) | BIT_BCN0_EXT_HEAD(v)) + +#define BIT_SHIFT_TXPKTNUM_CH4_7 16 +#define BIT_MASK_TXPKTNUM_CH4_7 0xfff +#define BIT_TXPKTNUM_CH4_7(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH4_7) << BIT_SHIFT_TXPKTNUM_CH4_7) +#define BITS_TXPKTNUM_CH4_7 \ + (BIT_MASK_TXPKTNUM_CH4_7 << BIT_SHIFT_TXPKTNUM_CH4_7) +#define BIT_CLEAR_TXPKTNUM_CH4_7(x) ((x) & (~BITS_TXPKTNUM_CH4_7)) +#define BIT_GET_TXPKTNUM_CH4_7(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH4_7) & BIT_MASK_TXPKTNUM_CH4_7) +#define BIT_SET_TXPKTNUM_CH4_7(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH4_7(x) | BIT_TXPKTNUM_CH4_7(v)) + +#define BIT_SHIFT_TXPKTNUM_CH12 16 +#define BIT_MASK_TXPKTNUM_CH12 0xfff +#define BIT_TXPKTNUM_CH12(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH12) << BIT_SHIFT_TXPKTNUM_CH12) +#define BITS_TXPKTNUM_CH12 (BIT_MASK_TXPKTNUM_CH12 << BIT_SHIFT_TXPKTNUM_CH12) +#define BIT_CLEAR_TXPKTNUM_CH12(x) ((x) & (~BITS_TXPKTNUM_CH12)) +#define BIT_GET_TXPKTNUM_CH12(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH12) & BIT_MASK_TXPKTNUM_CH12) +#define BIT_SET_TXPKTNUM_CH12(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH12(x) | BIT_TXPKTNUM_CH12(v)) + +#define BIT_SHIFT_TXPKTNUM_CH14_15 16 +#define BIT_MASK_TXPKTNUM_CH14_15 0xfff +#define BIT_TXPKTNUM_CH14_15(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH14_15) << BIT_SHIFT_TXPKTNUM_CH14_15) +#define BITS_TXPKTNUM_CH14_15 \ + (BIT_MASK_TXPKTNUM_CH14_15 << BIT_SHIFT_TXPKTNUM_CH14_15) +#define BIT_CLEAR_TXPKTNUM_CH14_15(x) ((x) & (~BITS_TXPKTNUM_CH14_15)) +#define BIT_GET_TXPKTNUM_CH14_15(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH14_15) & BIT_MASK_TXPKTNUM_CH14_15) +#define BIT_SET_TXPKTNUM_CH14_15(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH14_15(x) | BIT_TXPKTNUM_CH14_15(v)) + +#define BIT_BCN4_VALID BIT(15) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_TDE_DEBUG (Offset 0x0220) */ -/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ +#define BIT_SHIFT_TDE_DEBUG 0 +#define BIT_MASK_TDE_DEBUG 0xffffffffL +#define BIT_TDE_DEBUG(x) (((x) & BIT_MASK_TDE_DEBUG) << BIT_SHIFT_TDE_DEBUG) +#define BITS_TDE_DEBUG (BIT_MASK_TDE_DEBUG << BIT_SHIFT_TDE_DEBUG) +#define BIT_CLEAR_TDE_DEBUG(x) ((x) & (~BITS_TDE_DEBUG)) +#define BIT_GET_TDE_DEBUG(x) (((x) >> BIT_SHIFT_TDE_DEBUG) & BIT_MASK_TDE_DEBUG) +#define BIT_SET_TDE_DEBUG(x, v) (BIT_CLEAR_TDE_DEBUG(x) | BIT_TDE_DEBUG(v)) +#endif -#define BIT_SHIFT_NPQ_V1 0 -#define BIT_MASK_NPQ_V1 0xfff -#define BIT_NPQ_V1(x) (((x) & BIT_MASK_NPQ_V1) << BIT_SHIFT_NPQ_V1) -#define BIT_GET_NPQ_V1(x) (((x) >> BIT_SHIFT_NPQ_V1) & BIT_MASK_NPQ_V1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_TQPNT3 (Offset 0x0220) */ -/* 2 REG_FIFOPAGE_INFO_4 (Offset 0x023C) */ +#define BIT_SHIFT_LPQ_LOW_TH_V1 0 +#define BIT_MASK_LPQ_LOW_TH_V1 0xfff +#define BIT_LPQ_LOW_TH_V1(x) \ + (((x) & BIT_MASK_LPQ_LOW_TH_V1) << BIT_SHIFT_LPQ_LOW_TH_V1) +#define BITS_LPQ_LOW_TH_V1 (BIT_MASK_LPQ_LOW_TH_V1 << BIT_SHIFT_LPQ_LOW_TH_V1) +#define BIT_CLEAR_LPQ_LOW_TH_V1(x) ((x) & (~BITS_LPQ_LOW_TH_V1)) +#define BIT_GET_LPQ_LOW_TH_V1(x) \ + (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1) & BIT_MASK_LPQ_LOW_TH_V1) +#define BIT_SET_LPQ_LOW_TH_V1(x, v) \ + (BIT_CLEAR_LPQ_LOW_TH_V1(x) | BIT_LPQ_LOW_TH_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_BCN_CTRL_2 (Offset 0x0220) */ + +#define BIT_SHIFT_BCN4_HEAD 0 +#define BIT_MASK_BCN4_HEAD 0xfff +#define BIT_BCN4_HEAD(x) (((x) & BIT_MASK_BCN4_HEAD) << BIT_SHIFT_BCN4_HEAD) +#define BITS_BCN4_HEAD (BIT_MASK_BCN4_HEAD << BIT_SHIFT_BCN4_HEAD) +#define BIT_CLEAR_BCN4_HEAD(x) ((x) & (~BITS_BCN4_HEAD)) +#define BIT_GET_BCN4_HEAD(x) (((x) >> BIT_SHIFT_BCN4_HEAD) & BIT_MASK_BCN4_HEAD) +#define BIT_SET_BCN4_HEAD(x, v) (BIT_CLEAR_BCN4_HEAD(x) | BIT_BCN4_HEAD(v)) + +#define BIT_SHIFT_TXPKTNUM_CH0_3 0 +#define BIT_MASK_TXPKTNUM_CH0_3 0xfff +#define BIT_TXPKTNUM_CH0_3(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH0_3) << BIT_SHIFT_TXPKTNUM_CH0_3) +#define BITS_TXPKTNUM_CH0_3 \ + (BIT_MASK_TXPKTNUM_CH0_3 << BIT_SHIFT_TXPKTNUM_CH0_3) +#define BIT_CLEAR_TXPKTNUM_CH0_3(x) ((x) & (~BITS_TXPKTNUM_CH0_3)) +#define BIT_GET_TXPKTNUM_CH0_3(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH0_3) & BIT_MASK_TXPKTNUM_CH0_3) +#define BIT_SET_TXPKTNUM_CH0_3(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH0_3(x) | BIT_TXPKTNUM_CH0_3(v)) + +#define BIT_SHIFT_TXPKTNUM_CH8_11 0 +#define BIT_MASK_TXPKTNUM_CH8_11 0xfff +#define BIT_TXPKTNUM_CH8_11(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH8_11) << BIT_SHIFT_TXPKTNUM_CH8_11) +#define BITS_TXPKTNUM_CH8_11 \ + (BIT_MASK_TXPKTNUM_CH8_11 << BIT_SHIFT_TXPKTNUM_CH8_11) +#define BIT_CLEAR_TXPKTNUM_CH8_11(x) ((x) & (~BITS_TXPKTNUM_CH8_11)) +#define BIT_GET_TXPKTNUM_CH8_11(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH8_11) & BIT_MASK_TXPKTNUM_CH8_11) +#define BIT_SET_TXPKTNUM_CH8_11(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH8_11(x) | BIT_TXPKTNUM_CH8_11(v)) + +#define BIT_SHIFT_TXPKTNUM_CH13 0 +#define BIT_MASK_TXPKTNUM_CH13 0xfff +#define BIT_TXPKTNUM_CH13(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH13) << BIT_SHIFT_TXPKTNUM_CH13) +#define BITS_TXPKTNUM_CH13 (BIT_MASK_TXPKTNUM_CH13 << BIT_SHIFT_TXPKTNUM_CH13) +#define BIT_CLEAR_TXPKTNUM_CH13(x) ((x) & (~BITS_TXPKTNUM_CH13)) +#define BIT_GET_TXPKTNUM_CH13(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH13) & BIT_MASK_TXPKTNUM_CH13) +#define BIT_SET_TXPKTNUM_CH13(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH13(x) | BIT_TXPKTNUM_CH13(v)) + +#define BIT_SHIFT_TXPKTNUM_CH16 0 +#define BIT_MASK_TXPKTNUM_CH16 0xfff +#define BIT_TXPKTNUM_CH16(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH16) << BIT_SHIFT_TXPKTNUM_CH16) +#define BITS_TXPKTNUM_CH16 (BIT_MASK_TXPKTNUM_CH16 << BIT_SHIFT_TXPKTNUM_CH16) +#define BIT_CLEAR_TXPKTNUM_CH16(x) ((x) & (~BITS_TXPKTNUM_CH16)) +#define BIT_GET_TXPKTNUM_CH16(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH16) & BIT_MASK_TXPKTNUM_CH16) +#define BIT_SET_TXPKTNUM_CH16(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH16(x) | BIT_TXPKTNUM_CH16(v)) + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TQPNT4 (Offset 0x0224) */ -#define BIT_SHIFT_EXQ_AVAL_PG_V1 16 -#define BIT_MASK_EXQ_AVAL_PG_V1 0xfff -#define BIT_EXQ_AVAL_PG_V1(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1) << BIT_SHIFT_EXQ_AVAL_PG_V1) -#define BIT_GET_EXQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1) & BIT_MASK_EXQ_AVAL_PG_V1) +#define BIT_EXQ_INT_EN BIT(31) +#endif -#define BIT_SHIFT_EXQ_V1 0 -#define BIT_MASK_EXQ_V1 0xfff -#define BIT_EXQ_V1(x) (((x) & BIT_MASK_EXQ_V1) << BIT_SHIFT_EXQ_V1) -#define BIT_GET_EXQ_V1(x) (((x) >> BIT_SHIFT_EXQ_V1) & BIT_MASK_EXQ_V1) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AUTO_LLT (Offset 0x0224) */ -/* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */ +#define BIT_SHIFT_TXPKTNUM_V1 24 +#define BIT_MASK_TXPKTNUM_V1 0xff +#define BIT_TXPKTNUM_V1(x) \ + (((x) & BIT_MASK_TXPKTNUM_V1) << BIT_SHIFT_TXPKTNUM_V1) +#define BITS_TXPKTNUM_V1 (BIT_MASK_TXPKTNUM_V1 << BIT_SHIFT_TXPKTNUM_V1) +#define BIT_CLEAR_TXPKTNUM_V1(x) ((x) & (~BITS_TXPKTNUM_V1)) +#define BIT_GET_TXPKTNUM_V1(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_V1) & BIT_MASK_TXPKTNUM_V1) +#define BIT_SET_TXPKTNUM_V1(x, v) \ + (BIT_CLEAR_TXPKTNUM_V1(x) | BIT_TXPKTNUM_V1(v)) +#define BIT_TDE_DBG_SEL BIT(23) +#define BIT_AUTO_INIT_LLT BIT(16) -#define BIT_SHIFT_PUBQ_AVAL_PG_V1 16 -#define BIT_MASK_PUBQ_AVAL_PG_V1 0xfff -#define BIT_PUBQ_AVAL_PG_V1(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1) << BIT_SHIFT_PUBQ_AVAL_PG_V1) -#define BIT_GET_PUBQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1) & BIT_MASK_PUBQ_AVAL_PG_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PUBQ_V1 0 -#define BIT_MASK_PUBQ_V1 0xfff -#define BIT_PUBQ_V1(x) (((x) & BIT_MASK_PUBQ_V1) << BIT_SHIFT_PUBQ_V1) -#define BIT_GET_PUBQ_V1(x) (((x) >> BIT_SHIFT_PUBQ_V1) & BIT_MASK_PUBQ_V1) +/* 2 REG_TQPNT4 (Offset 0x0224) */ +#define BIT_SHIFT_EXQ_HIGH_TH_V1 16 +#define BIT_MASK_EXQ_HIGH_TH_V1 0xfff +#define BIT_EXQ_HIGH_TH_V1(x) \ + (((x) & BIT_MASK_EXQ_HIGH_TH_V1) << BIT_SHIFT_EXQ_HIGH_TH_V1) +#define BITS_EXQ_HIGH_TH_V1 \ + (BIT_MASK_EXQ_HIGH_TH_V1 << BIT_SHIFT_EXQ_HIGH_TH_V1) +#define BIT_CLEAR_EXQ_HIGH_TH_V1(x) ((x) & (~BITS_EXQ_HIGH_TH_V1)) +#define BIT_GET_EXQ_HIGH_TH_V1(x) \ + (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1) & BIT_MASK_EXQ_HIGH_TH_V1) +#define BIT_SET_EXQ_HIGH_TH_V1(x, v) \ + (BIT_CLEAR_EXQ_HIGH_TH_V1(x) | BIT_EXQ_HIGH_TH_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AUTO_LLT (Offset 0x0224) */ +#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE 8 +#define BIT_MASK_TX_OQT_HE_FREE_SPACE 0xff +#define BIT_TX_OQT_HE_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE) +#define BITS_TX_OQT_HE_FREE_SPACE \ + (BIT_MASK_TX_OQT_HE_FREE_SPACE << BIT_SHIFT_TX_OQT_HE_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_HE_FREE_SPACE)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE) & \ + BIT_MASK_TX_OQT_HE_FREE_SPACE) +#define BIT_SET_TX_OQT_HE_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) | BIT_TX_OQT_HE_FREE_SPACE(v)) + +#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE 0 +#define BIT_MASK_TX_OQT_NL_FREE_SPACE 0xff +#define BIT_TX_OQT_NL_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE) +#define BITS_TX_OQT_NL_FREE_SPACE \ + (BIT_MASK_TX_OQT_NL_FREE_SPACE << BIT_SHIFT_TX_OQT_NL_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_NL_FREE_SPACE)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE) & \ + BIT_MASK_TX_OQT_NL_FREE_SPACE) +#define BIT_SET_TX_OQT_NL_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) | BIT_TX_OQT_NL_FREE_SPACE(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_H2C_HEAD (Offset 0x0244) */ +/* 2 REG_TQPNT4 (Offset 0x0224) */ +#define BIT_SHIFT_EXQ_LOW_TH_V1 0 +#define BIT_MASK_EXQ_LOW_TH_V1 0xfff +#define BIT_EXQ_LOW_TH_V1(x) \ + (((x) & BIT_MASK_EXQ_LOW_TH_V1) << BIT_SHIFT_EXQ_LOW_TH_V1) +#define BITS_EXQ_LOW_TH_V1 (BIT_MASK_EXQ_LOW_TH_V1 << BIT_SHIFT_EXQ_LOW_TH_V1) +#define BIT_CLEAR_EXQ_LOW_TH_V1(x) ((x) & (~BITS_EXQ_LOW_TH_V1)) +#define BIT_GET_EXQ_LOW_TH_V1(x) \ + (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1) & BIT_MASK_EXQ_LOW_TH_V1) +#define BIT_SET_EXQ_LOW_TH_V1(x, v) \ + (BIT_CLEAR_EXQ_LOW_TH_V1(x) | BIT_EXQ_LOW_TH_V1(v)) -#define BIT_SHIFT_H2C_HEAD 0 -#define BIT_MASK_H2C_HEAD 0x3ffff -#define BIT_H2C_HEAD(x) (((x) & BIT_MASK_H2C_HEAD) << BIT_SHIFT_H2C_HEAD) -#define BIT_GET_H2C_HEAD(x) (((x) >> BIT_SHIFT_H2C_HEAD) & BIT_MASK_H2C_HEAD) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_H2C_TAIL (Offset 0x0248) */ +/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ +#define BIT_SW_BCN_SEL BIT(20) +#define BIT_SW_BCN_SEL_EN BIT(17) +#define BIT_BCN_VALID_1 BIT(16) -#define BIT_SHIFT_H2C_TAIL 0 -#define BIT_MASK_H2C_TAIL 0x3ffff -#define BIT_H2C_TAIL(x) (((x) & BIT_MASK_H2C_TAIL) << BIT_SHIFT_H2C_TAIL) -#define BIT_GET_H2C_TAIL(x) (((x) >> BIT_SHIFT_H2C_TAIL) & BIT_MASK_H2C_TAIL) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_H2C_READ_ADDR (Offset 0x024C) */ +/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +#define BIT_SHIFT_TXPKTNUM_H 16 +#define BIT_MASK_TXPKTNUM_H 0xffff +#define BIT_TXPKTNUM_H(x) (((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H) +#define BITS_TXPKTNUM_H (BIT_MASK_TXPKTNUM_H << BIT_SHIFT_TXPKTNUM_H) +#define BIT_CLEAR_TXPKTNUM_H(x) ((x) & (~BITS_TXPKTNUM_H)) +#define BIT_GET_TXPKTNUM_H(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H) +#define BIT_SET_TXPKTNUM_H(x, v) (BIT_CLEAR_TXPKTNUM_H(x) | BIT_TXPKTNUM_H(v)) -#define BIT_SHIFT_H2C_READ_ADDR 0 -#define BIT_MASK_H2C_READ_ADDR 0x3ffff -#define BIT_H2C_READ_ADDR(x) (((x) & BIT_MASK_H2C_READ_ADDR) << BIT_SHIFT_H2C_READ_ADDR) -#define BIT_GET_H2C_READ_ADDR(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR) & BIT_MASK_H2C_READ_ADDR) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_H2C_WR_ADDR (Offset 0x0250) */ +/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +#define BIT_SHIFT_TXPKTNUM_H_V2 16 +#define BIT_MASK_TXPKTNUM_H_V2 0xfff +#define BIT_TXPKTNUM_H_V2(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_V2) << BIT_SHIFT_TXPKTNUM_H_V2) +#define BITS_TXPKTNUM_H_V2 (BIT_MASK_TXPKTNUM_H_V2 << BIT_SHIFT_TXPKTNUM_H_V2) +#define BIT_CLEAR_TXPKTNUM_H_V2(x) ((x) & (~BITS_TXPKTNUM_H_V2)) +#define BIT_GET_TXPKTNUM_H_V2(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_V2) & BIT_MASK_TXPKTNUM_H_V2) +#define BIT_SET_TXPKTNUM_H_V2(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_V2(x) | BIT_TXPKTNUM_H_V2(v)) -#define BIT_SHIFT_H2C_WR_ADDR 0 -#define BIT_MASK_H2C_WR_ADDR 0x3ffff -#define BIT_H2C_WR_ADDR(x) (((x) & BIT_MASK_H2C_WR_ADDR) << BIT_SHIFT_H2C_WR_ADDR) -#define BIT_GET_H2C_WR_ADDR(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR) & BIT_MASK_H2C_WR_ADDR) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ +#define BIT_SHIFT_BCN_HEAD_1 8 +#define BIT_MASK_BCN_HEAD_1 0xff +#define BIT_BCN_HEAD_1(x) (((x) & BIT_MASK_BCN_HEAD_1) << BIT_SHIFT_BCN_HEAD_1) +#define BITS_BCN_HEAD_1 (BIT_MASK_BCN_HEAD_1 << BIT_SHIFT_BCN_HEAD_1) +#define BIT_CLEAR_BCN_HEAD_1(x) ((x) & (~BITS_BCN_HEAD_1)) +#define BIT_GET_BCN_HEAD_1(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_1) & BIT_MASK_BCN_HEAD_1) +#define BIT_SET_BCN_HEAD_1(x, v) (BIT_CLEAR_BCN_HEAD_1(x) | BIT_BCN_HEAD_1(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_H2C_INFO (Offset 0x0254) */ +/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +#define BIT_RST_PGSUB_CNT BIT(1) -#define BIT_SHIFT_VI_PUB_LIMIT 16 -#define BIT_MASK_VI_PUB_LIMIT 0xfff -#define BIT_VI_PUB_LIMIT(x) (((x) & BIT_MASK_VI_PUB_LIMIT) << BIT_SHIFT_VI_PUB_LIMIT) -#define BIT_GET_VI_PUB_LIMIT(x) (((x) >> BIT_SHIFT_VI_PUB_LIMIT) & BIT_MASK_VI_PUB_LIMIT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BK_PUB_LIMIT 16 -#define BIT_MASK_BK_PUB_LIMIT 0xfff -#define BIT_BK_PUB_LIMIT(x) (((x) & BIT_MASK_BK_PUB_LIMIT) << BIT_SHIFT_BK_PUB_LIMIT) -#define BIT_GET_BK_PUB_LIMIT(x) (((x) >> BIT_SHIFT_BK_PUB_LIMIT) & BIT_MASK_BK_PUB_LIMIT) +/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ -#define BIT_EXQ_EN_PUBLIC_LIMIT BIT(11) -#define BIT_NPQ_EN_PUBLIC_LIMIT BIT(10) -#define BIT_LPQ_EN_PUBLIC_LIMIT BIT(9) -#define BIT_HPQ_EN_PUBLIC_LIMIT BIT(8) +#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO 0 +#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO 0xff +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO) \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) +#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO \ + (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) +#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO(x) \ + ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO)) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) & \ + BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO) +#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO(x) | \ + BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +#define BIT_SHIFT_TXPKTNUM_H_V1 0 +#define BIT_MASK_TXPKTNUM_H_V1 0xffff +#define BIT_TXPKTNUM_H_V1(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_V1) << BIT_SHIFT_TXPKTNUM_H_V1) +#define BITS_TXPKTNUM_H_V1 (BIT_MASK_TXPKTNUM_H_V1 << BIT_SHIFT_TXPKTNUM_H_V1) +#define BIT_CLEAR_TXPKTNUM_H_V1(x) ((x) & (~BITS_TXPKTNUM_H_V1)) +#define BIT_GET_TXPKTNUM_H_V1(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_V1) & BIT_MASK_TXPKTNUM_H_V1) +#define BIT_SET_TXPKTNUM_H_V1(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_V1(x) | BIT_TXPKTNUM_H_V1(v)) -/* 2 REG_H2C_INFO (Offset 0x0254) */ +#endif -#define BIT_H2C_SPACE_VLD BIT(3) -#define BIT_H2C_WR_ADDR_RST BIT(2) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_H2C_LEN_SEL 0 -#define BIT_MASK_H2C_LEN_SEL 0x3 -#define BIT_H2C_LEN_SEL(x) (((x) & BIT_MASK_H2C_LEN_SEL) << BIT_SHIFT_H2C_LEN_SEL) -#define BIT_GET_H2C_LEN_SEL(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL) & BIT_MASK_H2C_LEN_SEL) +/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +#define BIT_SHIFT_TXPKTNUM_V2 0 +#define BIT_MASK_TXPKTNUM_V2 0xffff +#define BIT_TXPKTNUM_V2(x) \ + (((x) & BIT_MASK_TXPKTNUM_V2) << BIT_SHIFT_TXPKTNUM_V2) +#define BITS_TXPKTNUM_V2 (BIT_MASK_TXPKTNUM_V2 << BIT_SHIFT_TXPKTNUM_V2) +#define BIT_CLEAR_TXPKTNUM_V2(x) ((x) & (~BITS_TXPKTNUM_V2)) +#define BIT_GET_TXPKTNUM_V2(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_V2) & BIT_MASK_TXPKTNUM_V2) +#define BIT_SET_TXPKTNUM_V2(x, v) \ + (BIT_CLEAR_TXPKTNUM_V2(x) | BIT_TXPKTNUM_V2(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ -/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_SHIFT_TXPKTNUM_V3 0 +#define BIT_MASK_TXPKTNUM_V3 0xfff +#define BIT_TXPKTNUM_V3(x) \ + (((x) & BIT_MASK_TXPKTNUM_V3) << BIT_SHIFT_TXPKTNUM_V3) +#define BITS_TXPKTNUM_V3 (BIT_MASK_TXPKTNUM_V3 << BIT_SHIFT_TXPKTNUM_V3) +#define BIT_CLEAR_TXPKTNUM_V3(x) ((x) & (~BITS_TXPKTNUM_V3)) +#define BIT_GET_TXPKTNUM_V3(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_V3) & BIT_MASK_TXPKTNUM_V3) +#define BIT_SET_TXPKTNUM_V3(x, v) \ + (BIT_CLEAR_TXPKTNUM_V3(x) | BIT_TXPKTNUM_V3(v)) +#define BIT_PGSUB_CNT_EN BIT(0) -#define BIT_SHIFT_VO_PUB_LIMIT 0 -#define BIT_MASK_VO_PUB_LIMIT 0xfff -#define BIT_VO_PUB_LIMIT(x) (((x) & BIT_MASK_VO_PUB_LIMIT) << BIT_SHIFT_VO_PUB_LIMIT) -#define BIT_GET_VO_PUB_LIMIT(x) (((x) >> BIT_SHIFT_VO_PUB_LIMIT) & BIT_MASK_VO_PUB_LIMIT) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_BE_PUB_LIMIT 0 -#define BIT_MASK_BE_PUB_LIMIT 0xfff -#define BIT_BE_PUB_LIMIT(x) (((x) & BIT_MASK_BE_PUB_LIMIT) << BIT_SHIFT_BE_PUB_LIMIT) -#define BIT_GET_BE_PUB_LIMIT(x) (((x) >> BIT_SHIFT_BE_PUB_LIMIT) & BIT_MASK_BE_PUB_LIMIT) +/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ +#define BIT_EX2Q_PUBLIC_DIS_V1 BIT(21) +#define BIT_EX1Q_PUBLIC_DIS_V1 BIT(20) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ -#define BIT_USB_RXDMA_AGG_EN BIT(31) +#define BIT_EXQ_PUBLIC_DIS_V1 BIT(19) +#define BIT_NPQ_PUBLIC_DIS_V1 BIT(18) +#define BIT_LPQ_PUBLIC_DIS_V1 BIT(17) +#define BIT_HPQ_PUBLIC_DIS_V1 BIT(16) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN BIT(15) -#define BIT_DMA_STORE_MODE BIT(31) -#define BIT_EN_FW_ADD BIT(30) -#define BIT_EN_PRE_CALC BIT(29) -#define BIT_RXAGG_SW_EN BIT(28) +#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE 0 +#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE 0xfff +#define BIT_SDIO_TXAGG_ALIGN_SIZE(x) \ + (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE) \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) +#define BITS_SDIO_TXAGG_ALIGN_SIZE \ + (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) +#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE(x) ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE)) +#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE(x) \ + (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) & \ + BIT_MASK_SDIO_TXAGG_ALIGN_SIZE) +#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE(x, v) \ + (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE(x) | BIT_SDIO_TXAGG_ALIGN_SIZE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_FIFOPAGE_INFO_1 (Offset 0x0230) */ -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_SHIFT_HPQ_AVAL_PG_V1 16 +#define BIT_MASK_HPQ_AVAL_PG_V1 0xfff +#define BIT_HPQ_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_HPQ_AVAL_PG_V1) << BIT_SHIFT_HPQ_AVAL_PG_V1) +#define BITS_HPQ_AVAL_PG_V1 \ + (BIT_MASK_HPQ_AVAL_PG_V1 << BIT_SHIFT_HPQ_AVAL_PG_V1) +#define BIT_CLEAR_HPQ_AVAL_PG_V1(x) ((x) & (~BITS_HPQ_AVAL_PG_V1)) +#define BIT_GET_HPQ_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1) & BIT_MASK_HPQ_AVAL_PG_V1) +#define BIT_SET_HPQ_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_HPQ_AVAL_PG_V1(x) | BIT_HPQ_AVAL_PG_V1(v)) + +#define BIT_SHIFT_HPQ_V1 0 +#define BIT_MASK_HPQ_V1 0xfff +#define BIT_HPQ_V1(x) (((x) & BIT_MASK_HPQ_V1) << BIT_SHIFT_HPQ_V1) +#define BITS_HPQ_V1 (BIT_MASK_HPQ_V1 << BIT_SHIFT_HPQ_V1) +#define BIT_CLEAR_HPQ_V1(x) ((x) & (~BITS_HPQ_V1)) +#define BIT_GET_HPQ_V1(x) (((x) >> BIT_SHIFT_HPQ_V1) & BIT_MASK_HPQ_V1) +#define BIT_SET_HPQ_V1(x, v) (BIT_CLEAR_HPQ_V1(x) | BIT_HPQ_V1(v)) +/* 2 REG_FIFOPAGE_INFO_2 (Offset 0x0234) */ -#define BIT_SHIFT_RXDMA_AGG_OLD_MOD 24 -#define BIT_MASK_RXDMA_AGG_OLD_MOD 0xff -#define BIT_RXDMA_AGG_OLD_MOD(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD) << BIT_SHIFT_RXDMA_AGG_OLD_MOD) -#define BIT_GET_RXDMA_AGG_OLD_MOD(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD) & BIT_MASK_RXDMA_AGG_OLD_MOD) +#define BIT_SHIFT_LPQ_AVAL_PG_V1 16 +#define BIT_MASK_LPQ_AVAL_PG_V1 0xfff +#define BIT_LPQ_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_LPQ_AVAL_PG_V1) << BIT_SHIFT_LPQ_AVAL_PG_V1) +#define BITS_LPQ_AVAL_PG_V1 \ + (BIT_MASK_LPQ_AVAL_PG_V1 << BIT_SHIFT_LPQ_AVAL_PG_V1) +#define BIT_CLEAR_LPQ_AVAL_PG_V1(x) ((x) & (~BITS_LPQ_AVAL_PG_V1)) +#define BIT_GET_LPQ_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1) & BIT_MASK_LPQ_AVAL_PG_V1) +#define BIT_SET_LPQ_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_LPQ_AVAL_PG_V1(x) | BIT_LPQ_AVAL_PG_V1(v)) +#define BIT_SHIFT_LPQ_V1 0 +#define BIT_MASK_LPQ_V1 0xfff +#define BIT_LPQ_V1(x) (((x) & BIT_MASK_LPQ_V1) << BIT_SHIFT_LPQ_V1) +#define BITS_LPQ_V1 (BIT_MASK_LPQ_V1 << BIT_SHIFT_LPQ_V1) +#define BIT_CLEAR_LPQ_V1(x) ((x) & (~BITS_LPQ_V1)) +#define BIT_GET_LPQ_V1(x) (((x) >> BIT_SHIFT_LPQ_V1) & BIT_MASK_LPQ_V1) +#define BIT_SET_LPQ_V1(x, v) (BIT_CLEAR_LPQ_V1(x) | BIT_LPQ_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ +#define BIT_SHIFT_NPQ_AVAL_PG_V1 16 +#define BIT_MASK_NPQ_AVAL_PG_V1 0xfff +#define BIT_NPQ_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_NPQ_AVAL_PG_V1) << BIT_SHIFT_NPQ_AVAL_PG_V1) +#define BITS_NPQ_AVAL_PG_V1 \ + (BIT_MASK_NPQ_AVAL_PG_V1 << BIT_SHIFT_NPQ_AVAL_PG_V1) +#define BIT_CLEAR_NPQ_AVAL_PG_V1(x) ((x) & (~BITS_NPQ_AVAL_PG_V1)) +#define BIT_GET_NPQ_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1) & BIT_MASK_NPQ_AVAL_PG_V1) +#define BIT_SET_NPQ_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_NPQ_AVAL_PG_V1(x) | BIT_NPQ_AVAL_PG_V1(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PKT_NUM_WOL 16 -#define BIT_MASK_PKT_NUM_WOL 0xff -#define BIT_PKT_NUM_WOL(x) (((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL) -#define BIT_GET_PKT_NUM_WOL(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL) +/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ +#define BIT_SHIFT_NPQ_V1 0 +#define BIT_MASK_NPQ_V1 0xfff +#define BIT_NPQ_V1(x) (((x) & BIT_MASK_NPQ_V1) << BIT_SHIFT_NPQ_V1) +#define BITS_NPQ_V1 (BIT_MASK_NPQ_V1 << BIT_SHIFT_NPQ_V1) +#define BIT_CLEAR_NPQ_V1(x) ((x) & (~BITS_NPQ_V1)) +#define BIT_GET_NPQ_V1(x) (((x) >> BIT_SHIFT_NPQ_V1) & BIT_MASK_NPQ_V1) +#define BIT_SET_NPQ_V1(x, v) (BIT_CLEAR_NPQ_V1(x) | BIT_NPQ_V1(v)) -#endif +/* 2 REG_FIFOPAGE_INFO_4 (Offset 0x023C) */ +#define BIT_SHIFT_EXQ_AVAL_PG_V1 16 +#define BIT_MASK_EXQ_AVAL_PG_V1 0xfff +#define BIT_EXQ_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_EXQ_AVAL_PG_V1) << BIT_SHIFT_EXQ_AVAL_PG_V1) +#define BITS_EXQ_AVAL_PG_V1 \ + (BIT_MASK_EXQ_AVAL_PG_V1 << BIT_SHIFT_EXQ_AVAL_PG_V1) +#define BIT_CLEAR_EXQ_AVAL_PG_V1(x) ((x) & (~BITS_EXQ_AVAL_PG_V1)) +#define BIT_GET_EXQ_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1) & BIT_MASK_EXQ_AVAL_PG_V1) +#define BIT_SET_EXQ_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_EXQ_AVAL_PG_V1(x) | BIT_EXQ_AVAL_PG_V1(v)) + +#define BIT_SHIFT_EXQ_V1 0 +#define BIT_MASK_EXQ_V1 0xfff +#define BIT_EXQ_V1(x) (((x) & BIT_MASK_EXQ_V1) << BIT_SHIFT_EXQ_V1) +#define BITS_EXQ_V1 (BIT_MASK_EXQ_V1 << BIT_SHIFT_EXQ_V1) +#define BIT_CLEAR_EXQ_V1(x) ((x) & (~BITS_EXQ_V1)) +#define BIT_GET_EXQ_V1(x) (((x) >> BIT_SHIFT_EXQ_V1) & BIT_MASK_EXQ_V1) +#define BIT_SET_EXQ_V1(x, v) (BIT_CLEAR_EXQ_V1(x) | BIT_EXQ_V1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */ +#define BIT_SHIFT_PUBQ_AVAL_PG_V1 16 +#define BIT_MASK_PUBQ_AVAL_PG_V1 0xfff +#define BIT_PUBQ_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_PUBQ_AVAL_PG_V1) << BIT_SHIFT_PUBQ_AVAL_PG_V1) +#define BITS_PUBQ_AVAL_PG_V1 \ + (BIT_MASK_PUBQ_AVAL_PG_V1 << BIT_SHIFT_PUBQ_AVAL_PG_V1) +#define BIT_CLEAR_PUBQ_AVAL_PG_V1(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1)) +#define BIT_GET_PUBQ_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1) & BIT_MASK_PUBQ_AVAL_PG_V1) +#define BIT_SET_PUBQ_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_PUBQ_AVAL_PG_V1(x) | BIT_PUBQ_AVAL_PG_V1(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_DMA_AGG_TO_V1 8 -#define BIT_MASK_DMA_AGG_TO_V1 0xff -#define BIT_DMA_AGG_TO_V1(x) (((x) & BIT_MASK_DMA_AGG_TO_V1) << BIT_SHIFT_DMA_AGG_TO_V1) -#define BIT_GET_DMA_AGG_TO_V1(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_V1) & BIT_MASK_DMA_AGG_TO_V1) +/* 2 REG_TX_AGG_ALIGN (Offset 0x0240) */ +#define BIT_SHIFT_HW_FLOW_CTL_EN 16 +#define BIT_MASK_HW_FLOW_CTL_EN 0xffff +#define BIT_HW_FLOW_CTL_EN(x) \ + (((x) & BIT_MASK_HW_FLOW_CTL_EN) << BIT_SHIFT_HW_FLOW_CTL_EN) +#define BITS_HW_FLOW_CTL_EN \ + (BIT_MASK_HW_FLOW_CTL_EN << BIT_SHIFT_HW_FLOW_CTL_EN) +#define BIT_CLEAR_HW_FLOW_CTL_EN(x) ((x) & (~BITS_HW_FLOW_CTL_EN)) +#define BIT_GET_HW_FLOW_CTL_EN(x) \ + (((x) >> BIT_SHIFT_HW_FLOW_CTL_EN) & BIT_MASK_HW_FLOW_CTL_EN) +#define BIT_SET_HW_FLOW_CTL_EN(x, v) \ + (BIT_CLEAR_HW_FLOW_CTL_EN(x) | BIT_HW_FLOW_CTL_EN(v)) + +#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_V1 BIT(15) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */ +#define BIT_SHIFT_PUBQ_V1 0 +#define BIT_MASK_PUBQ_V1 0xfff +#define BIT_PUBQ_V1(x) (((x) & BIT_MASK_PUBQ_V1) << BIT_SHIFT_PUBQ_V1) +#define BITS_PUBQ_V1 (BIT_MASK_PUBQ_V1 << BIT_SHIFT_PUBQ_V1) +#define BIT_CLEAR_PUBQ_V1(x) ((x) & (~BITS_PUBQ_V1)) +#define BIT_GET_PUBQ_V1(x) (((x) >> BIT_SHIFT_PUBQ_V1) & BIT_MASK_PUBQ_V1) +#define BIT_SET_PUBQ_V1(x, v) (BIT_CLEAR_PUBQ_V1(x) | BIT_PUBQ_V1(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH 8 -#define BIT_MASK_RXDMA_AGG_TIMEOUT_TH 0xff -#define BIT_RXDMA_AGG_TIMEOUT_TH(x) (((x) & BIT_MASK_RXDMA_AGG_TIMEOUT_TH) << BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH) -#define BIT_GET_RXDMA_AGG_TIMEOUT_TH(x) (((x) >> BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH) & BIT_MASK_RXDMA_AGG_TIMEOUT_TH) +/* 2 REG_TX_AGG_ALIGN (Offset 0x0240) */ +#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1 0 +#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1 0xfff +#define BIT_SDIO_TXAGG_ALIGN_SIZE_V1(x) \ + (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1) \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1) +#define BITS_SDIO_TXAGG_ALIGN_SIZE_V1 \ + (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1 \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1) +#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1(x) \ + ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_V1)) +#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_V1(x) \ + (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1) & \ + BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1) +#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_V1(x, v) \ + (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1(x) | \ + BIT_SDIO_TXAGG_ALIGN_SIZE_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_H2C_HEAD (Offset 0x0244) */ +#define BIT_SHIFT_H2C_HEAD 0 +#define BIT_MASK_H2C_HEAD 0x3ffff +#define BIT_H2C_HEAD(x) (((x) & BIT_MASK_H2C_HEAD) << BIT_SHIFT_H2C_HEAD) +#define BITS_H2C_HEAD (BIT_MASK_H2C_HEAD << BIT_SHIFT_H2C_HEAD) +#define BIT_CLEAR_H2C_HEAD(x) ((x) & (~BITS_H2C_HEAD)) +#define BIT_GET_H2C_HEAD(x) (((x) >> BIT_SHIFT_H2C_HEAD) & BIT_MASK_H2C_HEAD) +#define BIT_SET_H2C_HEAD(x, v) (BIT_CLEAR_H2C_HEAD(x) | BIT_H2C_HEAD(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_DMA_AGG_TO 8 -#define BIT_MASK_DMA_AGG_TO 0xf -#define BIT_DMA_AGG_TO(x) (((x) & BIT_MASK_DMA_AGG_TO) << BIT_SHIFT_DMA_AGG_TO) -#define BIT_GET_DMA_AGG_TO(x) (((x) >> BIT_SHIFT_DMA_AGG_TO) & BIT_MASK_DMA_AGG_TO) +/* 2 REG_H2C_HEAD (Offset 0x0244) */ +#define BIT_SHIFT_H2C_HEAD_V1 0 +#define BIT_MASK_H2C_HEAD_V1 0x7ffff +#define BIT_H2C_HEAD_V1(x) \ + (((x) & BIT_MASK_H2C_HEAD_V1) << BIT_SHIFT_H2C_HEAD_V1) +#define BITS_H2C_HEAD_V1 (BIT_MASK_H2C_HEAD_V1 << BIT_SHIFT_H2C_HEAD_V1) +#define BIT_CLEAR_H2C_HEAD_V1(x) ((x) & (~BITS_H2C_HEAD_V1)) +#define BIT_GET_H2C_HEAD_V1(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_V1) & BIT_MASK_H2C_HEAD_V1) +#define BIT_SET_H2C_HEAD_V1(x, v) \ + (BIT_CLEAR_H2C_HEAD_V1(x) | BIT_H2C_HEAD_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_H2C_TAIL (Offset 0x0248) */ +#define BIT_SHIFT_H2C_TAIL 0 +#define BIT_MASK_H2C_TAIL 0x3ffff +#define BIT_H2C_TAIL(x) (((x) & BIT_MASK_H2C_TAIL) << BIT_SHIFT_H2C_TAIL) +#define BITS_H2C_TAIL (BIT_MASK_H2C_TAIL << BIT_SHIFT_H2C_TAIL) +#define BIT_CLEAR_H2C_TAIL(x) ((x) & (~BITS_H2C_TAIL)) +#define BIT_GET_H2C_TAIL(x) (((x) >> BIT_SHIFT_H2C_TAIL) & BIT_MASK_H2C_TAIL) +#define BIT_SET_H2C_TAIL(x, v) (BIT_CLEAR_H2C_TAIL(x) | BIT_H2C_TAIL(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1 0 -#define BIT_MASK_RXDMA_AGG_PG_TH_V1 0xf -#define BIT_RXDMA_AGG_PG_TH_V1(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1) -#define BIT_GET_RXDMA_AGG_PG_TH_V1(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1) & BIT_MASK_RXDMA_AGG_PG_TH_V1) +/* 2 REG_H2C_TAIL (Offset 0x0248) */ +#define BIT_SHIFT_H2C_TAIL_V1 0 +#define BIT_MASK_H2C_TAIL_V1 0x7ffff +#define BIT_H2C_TAIL_V1(x) \ + (((x) & BIT_MASK_H2C_TAIL_V1) << BIT_SHIFT_H2C_TAIL_V1) +#define BITS_H2C_TAIL_V1 (BIT_MASK_H2C_TAIL_V1 << BIT_SHIFT_H2C_TAIL_V1) +#define BIT_CLEAR_H2C_TAIL_V1(x) ((x) & (~BITS_H2C_TAIL_V1)) +#define BIT_GET_H2C_TAIL_V1(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_V1) & BIT_MASK_H2C_TAIL_V1) +#define BIT_SET_H2C_TAIL_V1(x, v) \ + (BIT_CLEAR_H2C_TAIL_V1(x) | BIT_H2C_TAIL_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_H2C_READ_ADDR (Offset 0x024C) */ +#define BIT_SHIFT_H2C_READ_ADDR 0 +#define BIT_MASK_H2C_READ_ADDR 0x3ffff +#define BIT_H2C_READ_ADDR(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR) << BIT_SHIFT_H2C_READ_ADDR) +#define BITS_H2C_READ_ADDR (BIT_MASK_H2C_READ_ADDR << BIT_SHIFT_H2C_READ_ADDR) +#define BIT_CLEAR_H2C_READ_ADDR(x) ((x) & (~BITS_H2C_READ_ADDR)) +#define BIT_GET_H2C_READ_ADDR(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR) & BIT_MASK_H2C_READ_ADDR) +#define BIT_SET_H2C_READ_ADDR(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR(x) | BIT_H2C_READ_ADDR(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RXDMA_AGG_PG_TH 0 -#define BIT_MASK_RXDMA_AGG_PG_TH 0xff -#define BIT_RXDMA_AGG_PG_TH(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH) << BIT_SHIFT_RXDMA_AGG_PG_TH) -#define BIT_GET_RXDMA_AGG_PG_TH(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH) & BIT_MASK_RXDMA_AGG_PG_TH) +/* 2 REG_H2C_READ_ADDR (Offset 0x024C) */ +#define BIT_SHIFT_H2C_READ_ADDR_V1 0 +#define BIT_MASK_H2C_READ_ADDR_V1 0x7ffff +#define BIT_H2C_READ_ADDR_V1(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_V1) << BIT_SHIFT_H2C_READ_ADDR_V1) +#define BITS_H2C_READ_ADDR_V1 \ + (BIT_MASK_H2C_READ_ADDR_V1 << BIT_SHIFT_H2C_READ_ADDR_V1) +#define BIT_CLEAR_H2C_READ_ADDR_V1(x) ((x) & (~BITS_H2C_READ_ADDR_V1)) +#define BIT_GET_H2C_READ_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_V1) & BIT_MASK_H2C_READ_ADDR_V1) +#define BIT_SET_H2C_READ_ADDR_V1(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_V1(x) | BIT_H2C_READ_ADDR_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) +/* 2 REG_H2C_WR_ADDR (Offset 0x0250) */ +#define BIT_SHIFT_H2C_WR_ADDR 0 +#define BIT_MASK_H2C_WR_ADDR 0x3ffff +#define BIT_H2C_WR_ADDR(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR) << BIT_SHIFT_H2C_WR_ADDR) +#define BITS_H2C_WR_ADDR (BIT_MASK_H2C_WR_ADDR << BIT_SHIFT_H2C_WR_ADDR) +#define BIT_CLEAR_H2C_WR_ADDR(x) ((x) & (~BITS_H2C_WR_ADDR)) +#define BIT_GET_H2C_WR_ADDR(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR) & BIT_MASK_H2C_WR_ADDR) +#define BIT_SET_H2C_WR_ADDR(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR(x) | BIT_H2C_WR_ADDR(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RXDMA_AGG_PG_TH_V2 0 -#define BIT_MASK_RXDMA_AGG_PG_TH_V2 0xff -#define BIT_RXDMA_AGG_PG_TH_V2(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V2) << BIT_SHIFT_RXDMA_AGG_PG_TH_V2) -#define BIT_GET_RXDMA_AGG_PG_TH_V2(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V2) & BIT_MASK_RXDMA_AGG_PG_TH_V2) +/* 2 REG_H2C_WR_ADDR (Offset 0x0250) */ +#define BIT_SHIFT_H2C_WR_ADDR_V1 0 +#define BIT_MASK_H2C_WR_ADDR_V1 0x7ffff +#define BIT_H2C_WR_ADDR_V1(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_V1) << BIT_SHIFT_H2C_WR_ADDR_V1) +#define BITS_H2C_WR_ADDR_V1 \ + (BIT_MASK_H2C_WR_ADDR_V1 << BIT_SHIFT_H2C_WR_ADDR_V1) +#define BIT_CLEAR_H2C_WR_ADDR_V1(x) ((x) & (~BITS_H2C_WR_ADDR_V1)) +#define BIT_GET_H2C_WR_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_V1) & BIT_MASK_H2C_WR_ADDR_V1) +#define BIT_SET_H2C_WR_ADDR_V1(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_V1(x) | BIT_H2C_WR_ADDR_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT) + +/* 2 REG_H2C_INFO (Offset 0x0254) */ -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_SHIFT_VI_PUB_LIMIT 16 +#define BIT_MASK_VI_PUB_LIMIT 0xfff +#define BIT_VI_PUB_LIMIT(x) \ + (((x) & BIT_MASK_VI_PUB_LIMIT) << BIT_SHIFT_VI_PUB_LIMIT) +#define BITS_VI_PUB_LIMIT (BIT_MASK_VI_PUB_LIMIT << BIT_SHIFT_VI_PUB_LIMIT) +#define BIT_CLEAR_VI_PUB_LIMIT(x) ((x) & (~BITS_VI_PUB_LIMIT)) +#define BIT_GET_VI_PUB_LIMIT(x) \ + (((x) >> BIT_SHIFT_VI_PUB_LIMIT) & BIT_MASK_VI_PUB_LIMIT) +#define BIT_SET_VI_PUB_LIMIT(x, v) \ + (BIT_CLEAR_VI_PUB_LIMIT(x) | BIT_VI_PUB_LIMIT(v)) +#define BIT_SHIFT_BK_PUB_LIMIT 16 +#define BIT_MASK_BK_PUB_LIMIT 0xfff +#define BIT_BK_PUB_LIMIT(x) \ + (((x) & BIT_MASK_BK_PUB_LIMIT) << BIT_SHIFT_BK_PUB_LIMIT) +#define BITS_BK_PUB_LIMIT (BIT_MASK_BK_PUB_LIMIT << BIT_SHIFT_BK_PUB_LIMIT) +#define BIT_CLEAR_BK_PUB_LIMIT(x) ((x) & (~BITS_BK_PUB_LIMIT)) +#define BIT_GET_BK_PUB_LIMIT(x) \ + (((x) >> BIT_SHIFT_BK_PUB_LIMIT) & BIT_MASK_BK_PUB_LIMIT) +#define BIT_SET_BK_PUB_LIMIT(x, v) \ + (BIT_CLEAR_BK_PUB_LIMIT(x) | BIT_BK_PUB_LIMIT(v)) -/* 2 REG_RXPKT_NUM (Offset 0x0284) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RXPKT_NUM 24 -#define BIT_MASK_RXPKT_NUM 0xff -#define BIT_RXPKT_NUM(x) (((x) & BIT_MASK_RXPKT_NUM) << BIT_SHIFT_RXPKT_NUM) -#define BIT_GET_RXPKT_NUM(x) (((x) >> BIT_SHIFT_RXPKT_NUM) & BIT_MASK_RXPKT_NUM) +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_EX2Q_EN_PUBLIC_LIMIT BIT(13) +#define BIT_EX1Q_EN_PUBLIC_LIMIT BIT(12) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_EXQ_EN_PUBLIC_LIMIT BIT(11) -/* 2 REG_RXPKT_NUM (Offset 0x0284) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16 20 -#define BIT_MASK_FW_UPD_RDPTR19_TO_16 0xf -#define BIT_FW_UPD_RDPTR19_TO_16(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16) -#define BIT_GET_FW_UPD_RDPTR19_TO_16(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16) & BIT_MASK_FW_UPD_RDPTR19_TO_16) +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_EQ_EN_PUBLIC_LIMIT BIT(11) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_NPQ_EN_PUBLIC_LIMIT BIT(10) -/* 2 REG_RXPKT_NUM (Offset 0x0284) */ +#endif -#define BIT_RXDMA_REQ BIT(19) -#define BIT_RW_RELEASE_EN BIT(18) -#define BIT_RXDMA_IDLE BIT(17) -#define BIT_RXPKT_RELEASE_POLL BIT(16) +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_FW_UPD_RDPTR 0 -#define BIT_MASK_FW_UPD_RDPTR 0xffff -#define BIT_FW_UPD_RDPTR(x) (((x) & BIT_MASK_FW_UPD_RDPTR) << BIT_SHIFT_FW_UPD_RDPTR) -#define BIT_GET_FW_UPD_RDPTR(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR) & BIT_MASK_FW_UPD_RDPTR) +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_NQ_EN_PUBLIC_LIMIT BIT(10) #endif - #if (HALMAC_8197F_SUPPORT) +/* 2 REG_H2C_INFO (Offset 0x0254) */ -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ - -#define BIT_FC2H_PKT_OVERFLOW BIT(8) +#define BIT_LPQ_EN_PUBLIC_LIMIT BIT(9) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_LQ_EN_PUBLIC_LIMIT BIT(9) -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#endif -#define BIT_C2H_PKT_OVF BIT(7) +#if (HALMAC_8197F_SUPPORT) -#endif +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_HPQ_EN_PUBLIC_LIMIT BIT(8) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +/* 2 REG_H2C_INFO (Offset 0x0254) */ -#define BIT_AGG_CFG_ISSUE BIT(6) +#define BIT_HQ_EN_PUBLIC_LIMIT BIT(8) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_H2C_INFO (Offset 0x0254) */ -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#define BIT_H2C_SPACE_VLD BIT(3) +#define BIT_H2C_WR_ADDR_RST BIT(2) -#define BIT_AGG_CONFGI_ISSUE BIT(6) +#define BIT_SHIFT_H2C_LEN_SEL 0 +#define BIT_MASK_H2C_LEN_SEL 0x3 +#define BIT_H2C_LEN_SEL(x) \ + (((x) & BIT_MASK_H2C_LEN_SEL) << BIT_SHIFT_H2C_LEN_SEL) +#define BITS_H2C_LEN_SEL (BIT_MASK_H2C_LEN_SEL << BIT_SHIFT_H2C_LEN_SEL) +#define BIT_CLEAR_H2C_LEN_SEL(x) ((x) & (~BITS_H2C_LEN_SEL)) +#define BIT_GET_H2C_LEN_SEL(x) \ + (((x) >> BIT_SHIFT_H2C_LEN_SEL) & BIT_MASK_H2C_LEN_SEL) +#define BIT_SET_H2C_LEN_SEL(x, v) \ + (BIT_CLEAR_H2C_LEN_SEL(x) | BIT_H2C_LEN_SEL(v)) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_SHIFT_VO_PUB_LIMIT 0 +#define BIT_MASK_VO_PUB_LIMIT 0xfff +#define BIT_VO_PUB_LIMIT(x) \ + (((x) & BIT_MASK_VO_PUB_LIMIT) << BIT_SHIFT_VO_PUB_LIMIT) +#define BITS_VO_PUB_LIMIT (BIT_MASK_VO_PUB_LIMIT << BIT_SHIFT_VO_PUB_LIMIT) +#define BIT_CLEAR_VO_PUB_LIMIT(x) ((x) & (~BITS_VO_PUB_LIMIT)) +#define BIT_GET_VO_PUB_LIMIT(x) \ + (((x) >> BIT_SHIFT_VO_PUB_LIMIT) & BIT_MASK_VO_PUB_LIMIT) +#define BIT_SET_VO_PUB_LIMIT(x, v) \ + (BIT_CLEAR_VO_PUB_LIMIT(x) | BIT_VO_PUB_LIMIT(v)) + +#define BIT_SHIFT_BE_PUB_LIMIT 0 +#define BIT_MASK_BE_PUB_LIMIT 0xfff +#define BIT_BE_PUB_LIMIT(x) \ + (((x) & BIT_MASK_BE_PUB_LIMIT) << BIT_SHIFT_BE_PUB_LIMIT) +#define BITS_BE_PUB_LIMIT (BIT_MASK_BE_PUB_LIMIT << BIT_SHIFT_BE_PUB_LIMIT) +#define BIT_CLEAR_BE_PUB_LIMIT(x) ((x) & (~BITS_BE_PUB_LIMIT)) +#define BIT_GET_BE_PUB_LIMIT(x) \ + (((x) >> BIT_SHIFT_BE_PUB_LIMIT) & BIT_MASK_BE_PUB_LIMIT) +#define BIT_SET_BE_PUB_LIMIT(x, v) \ + (BIT_CLEAR_BE_PUB_LIMIT(x) | BIT_BE_PUB_LIMIT(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DMA_OQT_0 (Offset 0x0260) */ + +#define BIT_SHIFT_TX_OQT_12_FREE_SPACE 24 +#define BIT_MASK_TX_OQT_12_FREE_SPACE 0xff +#define BIT_TX_OQT_12_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_12_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_12_FREE_SPACE) +#define BITS_TX_OQT_12_FREE_SPACE \ + (BIT_MASK_TX_OQT_12_FREE_SPACE << BIT_SHIFT_TX_OQT_12_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_12_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_12_FREE_SPACE)) +#define BIT_GET_TX_OQT_12_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_12_FREE_SPACE) & \ + BIT_MASK_TX_OQT_12_FREE_SPACE) +#define BIT_SET_TX_OQT_12_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_12_FREE_SPACE(x) | BIT_TX_OQT_12_FREE_SPACE(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_TQPNT5 (Offset 0x0260) */ + +#define BIT_SHIFT_EX1Q_HIGH_TH_V1 16 +#define BIT_MASK_EX1Q_HIGH_TH_V1 0xfff +#define BIT_EX1Q_HIGH_TH_V1(x) \ + (((x) & BIT_MASK_EX1Q_HIGH_TH_V1) << BIT_SHIFT_EX1Q_HIGH_TH_V1) +#define BITS_EX1Q_HIGH_TH_V1 \ + (BIT_MASK_EX1Q_HIGH_TH_V1 << BIT_SHIFT_EX1Q_HIGH_TH_V1) +#define BIT_CLEAR_EX1Q_HIGH_TH_V1(x) ((x) & (~BITS_EX1Q_HIGH_TH_V1)) +#define BIT_GET_EX1Q_HIGH_TH_V1(x) \ + (((x) >> BIT_SHIFT_EX1Q_HIGH_TH_V1) & BIT_MASK_EX1Q_HIGH_TH_V1) +#define BIT_SET_EX1Q_HIGH_TH_V1(x, v) \ + (BIT_CLEAR_EX1Q_HIGH_TH_V1(x) | BIT_EX1Q_HIGH_TH_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DMA_OQT_0 (Offset 0x0260) */ + +#define BIT_SHIFT_TX_OQT_8_11_FREE_SPACE 16 +#define BIT_MASK_TX_OQT_8_11_FREE_SPACE 0xff +#define BIT_TX_OQT_8_11_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_8_11_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE) +#define BITS_TX_OQT_8_11_FREE_SPACE \ + (BIT_MASK_TX_OQT_8_11_FREE_SPACE << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_8_11_FREE_SPACE(x) \ + ((x) & (~BITS_TX_OQT_8_11_FREE_SPACE)) +#define BIT_GET_TX_OQT_8_11_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_8_11_FREE_SPACE) & \ + BIT_MASK_TX_OQT_8_11_FREE_SPACE) +#define BIT_SET_TX_OQT_8_11_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_8_11_FREE_SPACE(x) | BIT_TX_OQT_8_11_FREE_SPACE(v)) + +#define BIT_SHIFT_TX_OQT_16_FREE_SPACE 16 +#define BIT_MASK_TX_OQT_16_FREE_SPACE 0xff +#define BIT_TX_OQT_16_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_16_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_16_FREE_SPACE) +#define BITS_TX_OQT_16_FREE_SPACE \ + (BIT_MASK_TX_OQT_16_FREE_SPACE << BIT_SHIFT_TX_OQT_16_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_16_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_16_FREE_SPACE)) +#define BIT_GET_TX_OQT_16_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_16_FREE_SPACE) & \ + BIT_MASK_TX_OQT_16_FREE_SPACE) +#define BIT_SET_TX_OQT_16_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_16_FREE_SPACE(x) | BIT_TX_OQT_16_FREE_SPACE(v)) + +#define BIT_SHIFT_TX_OQT_4_7_FREE_SPACE 8 +#define BIT_MASK_TX_OQT_4_7_FREE_SPACE 0xff +#define BIT_TX_OQT_4_7_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_4_7_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE) +#define BITS_TX_OQT_4_7_FREE_SPACE \ + (BIT_MASK_TX_OQT_4_7_FREE_SPACE << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_4_7_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_4_7_FREE_SPACE)) +#define BIT_GET_TX_OQT_4_7_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_4_7_FREE_SPACE) & \ + BIT_MASK_TX_OQT_4_7_FREE_SPACE) +#define BIT_SET_TX_OQT_4_7_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_4_7_FREE_SPACE(x) | BIT_TX_OQT_4_7_FREE_SPACE(v)) + +#define BIT_SHIFT_TX_OQT_14_15_FREE_SPACE 8 +#define BIT_MASK_TX_OQT_14_15_FREE_SPACE 0xff +#define BIT_TX_OQT_14_15_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_14_15_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE) +#define BITS_TX_OQT_14_15_FREE_SPACE \ + (BIT_MASK_TX_OQT_14_15_FREE_SPACE << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_14_15_FREE_SPACE(x) \ + ((x) & (~BITS_TX_OQT_14_15_FREE_SPACE)) +#define BIT_GET_TX_OQT_14_15_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_14_15_FREE_SPACE) & \ + BIT_MASK_TX_OQT_14_15_FREE_SPACE) +#define BIT_SET_TX_OQT_14_15_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_14_15_FREE_SPACE(x) | BIT_TX_OQT_14_15_FREE_SPACE(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_TQPNT5 (Offset 0x0260) */ + +#define BIT_SHIFT_EX1Q_LOW_TH_V1 0 +#define BIT_MASK_EX1Q_LOW_TH_V1 0xfff +#define BIT_EX1Q_LOW_TH_V1(x) \ + (((x) & BIT_MASK_EX1Q_LOW_TH_V1) << BIT_SHIFT_EX1Q_LOW_TH_V1) +#define BITS_EX1Q_LOW_TH_V1 \ + (BIT_MASK_EX1Q_LOW_TH_V1 << BIT_SHIFT_EX1Q_LOW_TH_V1) +#define BIT_CLEAR_EX1Q_LOW_TH_V1(x) ((x) & (~BITS_EX1Q_LOW_TH_V1)) +#define BIT_GET_EX1Q_LOW_TH_V1(x) \ + (((x) >> BIT_SHIFT_EX1Q_LOW_TH_V1) & BIT_MASK_EX1Q_LOW_TH_V1) +#define BIT_SET_EX1Q_LOW_TH_V1(x, v) \ + (BIT_CLEAR_EX1Q_LOW_TH_V1(x) | BIT_EX1Q_LOW_TH_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DMA_OQT_0 (Offset 0x0260) */ + +#define BIT_SHIFT_TX_OQT_0_3_FREE_SPACE 0 +#define BIT_MASK_TX_OQT_0_3_FREE_SPACE 0xff +#define BIT_TX_OQT_0_3_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_0_3_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE) +#define BITS_TX_OQT_0_3_FREE_SPACE \ + (BIT_MASK_TX_OQT_0_3_FREE_SPACE << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_0_3_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_0_3_FREE_SPACE)) +#define BIT_GET_TX_OQT_0_3_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_0_3_FREE_SPACE) & \ + BIT_MASK_TX_OQT_0_3_FREE_SPACE) +#define BIT_SET_TX_OQT_0_3_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_0_3_FREE_SPACE(x) | BIT_TX_OQT_0_3_FREE_SPACE(v)) + +#define BIT_SHIFT_TX_OQT_13_FREE_SPACE 0 +#define BIT_MASK_TX_OQT_13_FREE_SPACE 0xff +#define BIT_TX_OQT_13_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_13_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_13_FREE_SPACE) +#define BITS_TX_OQT_13_FREE_SPACE \ + (BIT_MASK_TX_OQT_13_FREE_SPACE << BIT_SHIFT_TX_OQT_13_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_13_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_13_FREE_SPACE)) +#define BIT_GET_TX_OQT_13_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_13_FREE_SPACE) & \ + BIT_MASK_TX_OQT_13_FREE_SPACE) +#define BIT_SET_TX_OQT_13_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_13_FREE_SPACE(x) | BIT_TX_OQT_13_FREE_SPACE(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_TQPNT6 (Offset 0x0264) */ + +#define BIT_SHIFT_EX2Q_HIGH_TH_V1 16 +#define BIT_MASK_EX2Q_HIGH_TH_V1 0xfff +#define BIT_EX2Q_HIGH_TH_V1(x) \ + (((x) & BIT_MASK_EX2Q_HIGH_TH_V1) << BIT_SHIFT_EX2Q_HIGH_TH_V1) +#define BITS_EX2Q_HIGH_TH_V1 \ + (BIT_MASK_EX2Q_HIGH_TH_V1 << BIT_SHIFT_EX2Q_HIGH_TH_V1) +#define BIT_CLEAR_EX2Q_HIGH_TH_V1(x) ((x) & (~BITS_EX2Q_HIGH_TH_V1)) +#define BIT_GET_EX2Q_HIGH_TH_V1(x) \ + (((x) >> BIT_SHIFT_EX2Q_HIGH_TH_V1) & BIT_MASK_EX2Q_HIGH_TH_V1) +#define BIT_SET_EX2Q_HIGH_TH_V1(x, v) \ + (BIT_CLEAR_EX2Q_HIGH_TH_V1(x) | BIT_EX2Q_HIGH_TH_V1(v)) + +#define BIT_SHIFT_EX2Q_LOW_TH_V1 0 +#define BIT_MASK_EX2Q_LOW_TH_V1 0xfff +#define BIT_EX2Q_LOW_TH_V1(x) \ + (((x) & BIT_MASK_EX2Q_LOW_TH_V1) << BIT_SHIFT_EX2Q_LOW_TH_V1) +#define BITS_EX2Q_LOW_TH_V1 \ + (BIT_MASK_EX2Q_LOW_TH_V1 << BIT_SHIFT_EX2Q_LOW_TH_V1) +#define BIT_CLEAR_EX2Q_LOW_TH_V1(x) ((x) & (~BITS_EX2Q_LOW_TH_V1)) +#define BIT_GET_EX2Q_LOW_TH_V1(x) \ + (((x) >> BIT_SHIFT_EX2Q_LOW_TH_V1) & BIT_MASK_EX2Q_LOW_TH_V1) +#define BIT_SET_EX2Q_LOW_TH_V1(x, v) \ + (BIT_CLEAR_EX2Q_LOW_TH_V1(x) | BIT_EX2Q_LOW_TH_V1(v)) + +/* 2 REG_FIFOPAGE_INFO_6 (Offset 0x0268) */ + +#define BIT_SHIFT_EX1Q_AVAL_PG_V1 16 +#define BIT_MASK_EX1Q_AVAL_PG_V1 0xfff +#define BIT_EX1Q_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_EX1Q_AVAL_PG_V1) << BIT_SHIFT_EX1Q_AVAL_PG_V1) +#define BITS_EX1Q_AVAL_PG_V1 \ + (BIT_MASK_EX1Q_AVAL_PG_V1 << BIT_SHIFT_EX1Q_AVAL_PG_V1) +#define BIT_CLEAR_EX1Q_AVAL_PG_V1(x) ((x) & (~BITS_EX1Q_AVAL_PG_V1)) +#define BIT_GET_EX1Q_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_EX1Q_AVAL_PG_V1) & BIT_MASK_EX1Q_AVAL_PG_V1) +#define BIT_SET_EX1Q_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_EX1Q_AVAL_PG_V1(x) | BIT_EX1Q_AVAL_PG_V1(v)) + +#define BIT_SHIFT_EX1Q_V1 0 +#define BIT_MASK_EX1Q_V1 0xfff +#define BIT_EX1Q_V1(x) (((x) & BIT_MASK_EX1Q_V1) << BIT_SHIFT_EX1Q_V1) +#define BITS_EX1Q_V1 (BIT_MASK_EX1Q_V1 << BIT_SHIFT_EX1Q_V1) +#define BIT_CLEAR_EX1Q_V1(x) ((x) & (~BITS_EX1Q_V1)) +#define BIT_GET_EX1Q_V1(x) (((x) >> BIT_SHIFT_EX1Q_V1) & BIT_MASK_EX1Q_V1) +#define BIT_SET_EX1Q_V1(x, v) (BIT_CLEAR_EX1Q_V1(x) | BIT_EX1Q_V1(v)) + +/* 2 REG_FIFOPAGE_INFO_7 (Offset 0x026C) */ + +#define BIT_SHIFT_EX2Q_AVAL_PG_V1 16 +#define BIT_MASK_EX2Q_AVAL_PG_V1 0xfff +#define BIT_EX2Q_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_EX2Q_AVAL_PG_V1) << BIT_SHIFT_EX2Q_AVAL_PG_V1) +#define BITS_EX2Q_AVAL_PG_V1 \ + (BIT_MASK_EX2Q_AVAL_PG_V1 << BIT_SHIFT_EX2Q_AVAL_PG_V1) +#define BIT_CLEAR_EX2Q_AVAL_PG_V1(x) ((x) & (~BITS_EX2Q_AVAL_PG_V1)) +#define BIT_GET_EX2Q_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_EX2Q_AVAL_PG_V1) & BIT_MASK_EX2Q_AVAL_PG_V1) +#define BIT_SET_EX2Q_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_EX2Q_AVAL_PG_V1(x) | BIT_EX2Q_AVAL_PG_V1(v)) + +#define BIT_SHIFT_EX2Q_V1 0 +#define BIT_MASK_EX2Q_V1 0xfff +#define BIT_EX2Q_V1(x) (((x) & BIT_MASK_EX2Q_V1) << BIT_SHIFT_EX2Q_V1) +#define BITS_EX2Q_V1 (BIT_MASK_EX2Q_V1 << BIT_SHIFT_EX2Q_V1) +#define BIT_CLEAR_EX2Q_V1(x) ((x) & (~BITS_EX2Q_V1)) +#define BIT_GET_EX2Q_V1(x) (((x) >> BIT_SHIFT_EX2Q_V1) & BIT_MASK_EX2Q_V1) +#define BIT_SET_EX2Q_V1(x, v) (BIT_CLEAR_EX2Q_V1(x) | BIT_EX2Q_V1(v)) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_PGSUB_H (Offset 0x0270) */ + +#define BIT_SHIFT_HPQ_PGSUB_CNT 0 +#define BIT_MASK_HPQ_PGSUB_CNT 0xffffffffL +#define BIT_HPQ_PGSUB_CNT(x) \ + (((x) & BIT_MASK_HPQ_PGSUB_CNT) << BIT_SHIFT_HPQ_PGSUB_CNT) +#define BITS_HPQ_PGSUB_CNT (BIT_MASK_HPQ_PGSUB_CNT << BIT_SHIFT_HPQ_PGSUB_CNT) +#define BIT_CLEAR_HPQ_PGSUB_CNT(x) ((x) & (~BITS_HPQ_PGSUB_CNT)) +#define BIT_GET_HPQ_PGSUB_CNT(x) \ + (((x) >> BIT_SHIFT_HPQ_PGSUB_CNT) & BIT_MASK_HPQ_PGSUB_CNT) +#define BIT_SET_HPQ_PGSUB_CNT(x, v) \ + (BIT_CLEAR_HPQ_PGSUB_CNT(x) | BIT_HPQ_PGSUB_CNT(v)) + +/* 2 REG_PGSUB_N (Offset 0x0274) */ + +#define BIT_SHIFT_NPQ_PGSUB_CNT 0 +#define BIT_MASK_NPQ_PGSUB_CNT 0xffffffffL +#define BIT_NPQ_PGSUB_CNT(x) \ + (((x) & BIT_MASK_NPQ_PGSUB_CNT) << BIT_SHIFT_NPQ_PGSUB_CNT) +#define BITS_NPQ_PGSUB_CNT (BIT_MASK_NPQ_PGSUB_CNT << BIT_SHIFT_NPQ_PGSUB_CNT) +#define BIT_CLEAR_NPQ_PGSUB_CNT(x) ((x) & (~BITS_NPQ_PGSUB_CNT)) +#define BIT_GET_NPQ_PGSUB_CNT(x) \ + (((x) >> BIT_SHIFT_NPQ_PGSUB_CNT) & BIT_MASK_NPQ_PGSUB_CNT) +#define BIT_SET_NPQ_PGSUB_CNT(x, v) \ + (BIT_CLEAR_NPQ_PGSUB_CNT(x) | BIT_NPQ_PGSUB_CNT(v)) + +/* 2 REG_PGSUB_L (Offset 0x0278) */ + +#define BIT_SHIFT_LPQ_PGSUB_CNT 0 +#define BIT_MASK_LPQ_PGSUB_CNT 0xffffffffL +#define BIT_LPQ_PGSUB_CNT(x) \ + (((x) & BIT_MASK_LPQ_PGSUB_CNT) << BIT_SHIFT_LPQ_PGSUB_CNT) +#define BITS_LPQ_PGSUB_CNT (BIT_MASK_LPQ_PGSUB_CNT << BIT_SHIFT_LPQ_PGSUB_CNT) +#define BIT_CLEAR_LPQ_PGSUB_CNT(x) ((x) & (~BITS_LPQ_PGSUB_CNT)) +#define BIT_GET_LPQ_PGSUB_CNT(x) \ + (((x) >> BIT_SHIFT_LPQ_PGSUB_CNT) & BIT_MASK_LPQ_PGSUB_CNT) +#define BIT_SET_LPQ_PGSUB_CNT(x, v) \ + (BIT_CLEAR_LPQ_PGSUB_CNT(x) | BIT_LPQ_PGSUB_CNT(v)) + +/* 2 REG_PGSUB_E (Offset 0x027C) */ + +#define BIT_SHIFT_EPQ_PGSUB_CNT 0 +#define BIT_MASK_EPQ_PGSUB_CNT 0xffffffffL +#define BIT_EPQ_PGSUB_CNT(x) \ + (((x) & BIT_MASK_EPQ_PGSUB_CNT) << BIT_SHIFT_EPQ_PGSUB_CNT) +#define BITS_EPQ_PGSUB_CNT (BIT_MASK_EPQ_PGSUB_CNT << BIT_SHIFT_EPQ_PGSUB_CNT) +#define BIT_CLEAR_EPQ_PGSUB_CNT(x) ((x) & (~BITS_EPQ_PGSUB_CNT)) +#define BIT_GET_EPQ_PGSUB_CNT(x) \ + (((x) >> BIT_SHIFT_EPQ_PGSUB_CNT) & BIT_MASK_EPQ_PGSUB_CNT) +#define BIT_SET_EPQ_PGSUB_CNT(x, v) \ + (BIT_CLEAR_EPQ_PGSUB_CNT(x) | BIT_EPQ_PGSUB_CNT(v)) + +#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V2 0 +#define BIT_MASK_FWFF_PKT_STR_ADDR_V2 0x3fff +#define BIT_FWFF_PKT_STR_ADDR_V2(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V2) \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2) +#define BITS_FWFF_PKT_STR_ADDR_V2 \ + (BIT_MASK_FWFF_PKT_STR_ADDR_V2 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V2(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_V2)) +#define BIT_GET_FWFF_PKT_STR_ADDR_V2(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V2) & \ + BIT_MASK_FWFF_PKT_STR_ADDR_V2) +#define BIT_SET_FWFF_PKT_STR_ADDR_V2(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR_V2(x) | BIT_FWFF_PKT_STR_ADDR_V2(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ -#define BIT_FW_POLL_ISSUE BIT(5) -#define BIT_RX_DATA_UDN BIT(4) -#define BIT_RX_SFF_UDN BIT(3) -#define BIT_RX_SFF_OVF BIT(2) +#define BIT_USB_RXDMA_AGG_EN BIT(31) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_DMA_STORE_MODE BIT(31) -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#endif -#define BIT_USB_REQ_LEN_OVF BIT(1) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_RXDMA_AGG_OLD_MOD_V1 BIT(31) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ -#define BIT_RXPKT_OVF BIT(0) +#define BIT_DMA_STORE BIT(31) -/* 2 REG_RXDMA_DPR (Offset 0x028C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RDE_DEBUG 0 -#define BIT_MASK_RDE_DEBUG 0xffffffffL -#define BIT_RDE_DEBUG(x) (((x) & BIT_MASK_RDE_DEBUG) << BIT_SHIFT_RDE_DEBUG) -#define BIT_GET_RDE_DEBUG(x) (((x) >> BIT_SHIFT_RDE_DEBUG) & BIT_MASK_RDE_DEBUG) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_EN_FW_ADD BIT(30) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_EN_PRE_CALC BIT(29) +#define BIT_RXAGG_SW_EN BIT(28) -/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PKTNUM_TH_V2 24 -#define BIT_MASK_PKTNUM_TH_V2 0x1f -#define BIT_PKTNUM_TH_V2(x) (((x) & BIT_MASK_PKTNUM_TH_V2) << BIT_SHIFT_PKTNUM_TH_V2) -#define BIT_GET_PKTNUM_TH_V2(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2) & BIT_MASK_PKTNUM_TH_V2) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ -#define BIT_TXBA_BREAK_USBAGG BIT(23) +#define BIT_RXAGG_SW_TRIG BIT(27) -#define BIT_SHIFT_PKTLEN_PARA 16 -#define BIT_MASK_PKTLEN_PARA 0x7 -#define BIT_PKTLEN_PARA(x) (((x) & BIT_MASK_PKTLEN_PARA) << BIT_SHIFT_PKTLEN_PARA) -#define BIT_GET_PKTLEN_PARA(x) (((x) >> BIT_SHIFT_PKTLEN_PARA) & BIT_MASK_PKTLEN_PARA) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_SHIFT_RXDMA_AGG_OLD_MOD 24 +#define BIT_MASK_RXDMA_AGG_OLD_MOD 0xff +#define BIT_RXDMA_AGG_OLD_MOD(x) \ + (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD) << BIT_SHIFT_RXDMA_AGG_OLD_MOD) +#define BITS_RXDMA_AGG_OLD_MOD \ + (BIT_MASK_RXDMA_AGG_OLD_MOD << BIT_SHIFT_RXDMA_AGG_OLD_MOD) +#define BIT_CLEAR_RXDMA_AGG_OLD_MOD(x) ((x) & (~BITS_RXDMA_AGG_OLD_MOD)) +#define BIT_GET_RXDMA_AGG_OLD_MOD(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD) & BIT_MASK_RXDMA_AGG_OLD_MOD) +#define BIT_SET_RXDMA_AGG_OLD_MOD(x, v) \ + (BIT_CLEAR_RXDMA_AGG_OLD_MOD(x) | BIT_RXDMA_AGG_OLD_MOD(v)) -#if (HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ -#define BIT_GRAYCODE_SYNC_WITH_BIN BIT(8) +#define BIT_SHIFT_PKT_NUM_WOL 16 +#define BIT_MASK_PKT_NUM_WOL 0xff +#define BIT_PKT_NUM_WOL(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL) +#define BITS_PKT_NUM_WOL (BIT_MASK_PKT_NUM_WOL << BIT_SHIFT_PKT_NUM_WOL) +#define BIT_CLEAR_PKT_NUM_WOL(x) ((x) & (~BITS_PKT_NUM_WOL)) +#define BIT_GET_PKT_NUM_WOL(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL) +#define BIT_SET_PKT_NUM_WOL(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL(x) | BIT_PKT_NUM_WOL(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_SHIFT_DMA_AGG_TO_V1 8 +#define BIT_MASK_DMA_AGG_TO_V1 0xff +#define BIT_DMA_AGG_TO_V1(x) \ + (((x) & BIT_MASK_DMA_AGG_TO_V1) << BIT_SHIFT_DMA_AGG_TO_V1) +#define BITS_DMA_AGG_TO_V1 (BIT_MASK_DMA_AGG_TO_V1 << BIT_SHIFT_DMA_AGG_TO_V1) +#define BIT_CLEAR_DMA_AGG_TO_V1(x) ((x) & (~BITS_DMA_AGG_TO_V1)) +#define BIT_GET_DMA_AGG_TO_V1(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO_V1) & BIT_MASK_DMA_AGG_TO_V1) +#define BIT_SET_DMA_AGG_TO_V1(x, v) \ + (BIT_CLEAR_DMA_AGG_TO_V1(x) | BIT_DMA_AGG_TO_V1(v)) +#endif -/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ + +#define BIT_SHIFT_DMA_AGG_TO 8 +#define BIT_MASK_DMA_AGG_TO 0xf +#define BIT_DMA_AGG_TO(x) (((x) & BIT_MASK_DMA_AGG_TO) << BIT_SHIFT_DMA_AGG_TO) +#define BITS_DMA_AGG_TO (BIT_MASK_DMA_AGG_TO << BIT_SHIFT_DMA_AGG_TO) +#define BIT_CLEAR_DMA_AGG_TO(x) ((x) & (~BITS_DMA_AGG_TO)) +#define BIT_GET_DMA_AGG_TO(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO) & BIT_MASK_DMA_AGG_TO) +#define BIT_SET_DMA_AGG_TO(x, v) (BIT_CLEAR_DMA_AGG_TO(x) | BIT_DMA_AGG_TO(v)) -#define BIT_SHIFT_BURST_SIZE 4 -#define BIT_MASK_BURST_SIZE 0x3 -#define BIT_BURST_SIZE(x) (((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE) -#define BIT_GET_BURST_SIZE(x) (((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BURST_CNT 2 -#define BIT_MASK_BURST_CNT 0x3 -#define BIT_BURST_CNT(x) (((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT) -#define BIT_GET_BURST_CNT(x) (((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_V1 0xf +#define BIT_RXDMA_AGG_PG_TH_V1(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1) +#define BITS_RXDMA_AGG_PG_TH_V1 \ + (BIT_MASK_RXDMA_AGG_PG_TH_V1 << BIT_SHIFT_RXDMA_AGG_PG_TH_V1) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_V1(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_V1)) +#define BIT_GET_RXDMA_AGG_PG_TH_V1(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1) & BIT_MASK_RXDMA_AGG_PG_TH_V1) +#define BIT_SET_RXDMA_AGG_PG_TH_V1(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_V1(x) | BIT_RXDMA_AGG_PG_TH_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_SHIFT_RXDMA_AGG_PG_TH 0 +#define BIT_MASK_RXDMA_AGG_PG_TH 0xff +#define BIT_RXDMA_AGG_PG_TH(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH) << BIT_SHIFT_RXDMA_AGG_PG_TH) +#define BITS_RXDMA_AGG_PG_TH \ + (BIT_MASK_RXDMA_AGG_PG_TH << BIT_SHIFT_RXDMA_AGG_PG_TH) +#define BIT_CLEAR_RXDMA_AGG_PG_TH(x) ((x) & (~BITS_RXDMA_AGG_PG_TH)) +#define BIT_GET_RXDMA_AGG_PG_TH(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH) & BIT_MASK_RXDMA_AGG_PG_TH) +#define BIT_SET_RXDMA_AGG_PG_TH(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH(x) | BIT_RXDMA_AGG_PG_TH(v)) -/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#endif -#define BIT_DAM_MODE BIT(1) +#if (HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_SHIFT_RXDMA_AGG_PG_TH_V2 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_V2 0xff +#define BIT_RXDMA_AGG_PG_TH_V2(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V2) << BIT_SHIFT_RXDMA_AGG_PG_TH_V2) +#define BITS_RXDMA_AGG_PG_TH_V2 \ + (BIT_MASK_RXDMA_AGG_PG_TH_V2 << BIT_SHIFT_RXDMA_AGG_PG_TH_V2) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_V2(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_V2)) +#define BIT_GET_RXDMA_AGG_PG_TH_V2(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V2) & BIT_MASK_RXDMA_AGG_PG_TH_V2) +#define BIT_SET_RXDMA_AGG_PG_TH_V2(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_V2(x) | BIT_RXDMA_AGG_PG_TH_V2(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +/* 2 REG_RXPKT_NUM (Offset 0x0284) */ -#define BIT_DMA_MODE BIT(1) +#define BIT_SHIFT_RXPKT_NUM 24 +#define BIT_MASK_RXPKT_NUM 0xff +#define BIT_RXPKT_NUM(x) (((x) & BIT_MASK_RXPKT_NUM) << BIT_SHIFT_RXPKT_NUM) +#define BITS_RXPKT_NUM (BIT_MASK_RXPKT_NUM << BIT_SHIFT_RXPKT_NUM) +#define BIT_CLEAR_RXPKT_NUM(x) ((x) & (~BITS_RXPKT_NUM)) +#define BIT_GET_RXPKT_NUM(x) (((x) >> BIT_SHIFT_RXPKT_NUM) & BIT_MASK_RXPKT_NUM) +#define BIT_SET_RXPKT_NUM(x, v) (BIT_CLEAR_RXPKT_NUM(x) | BIT_RXPKT_NUM(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_RXPKT_NUM (Offset 0x0284) */ -/* 2 REG_C2H_PKT (Offset 0x0294) */ +#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16 20 +#define BIT_MASK_FW_UPD_RDPTR19_TO_16 0xf +#define BIT_FW_UPD_RDPTR19_TO_16(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16) \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16) +#define BITS_FW_UPD_RDPTR19_TO_16 \ + (BIT_MASK_FW_UPD_RDPTR19_TO_16 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16(x) ((x) & (~BITS_FW_UPD_RDPTR19_TO_16)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16) & \ + BIT_MASK_FW_UPD_RDPTR19_TO_16) +#define BIT_SET_FW_UPD_RDPTR19_TO_16(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR19_TO_16(x) | BIT_FW_UPD_RDPTR19_TO_16(v)) +#endif -#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19 24 -#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19 0xf -#define BIT_R_C2H_STR_ADDR_16_TO_19(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) -#define BIT_GET_R_C2H_STR_ADDR_16_TO_19(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) +/* 2 REG_RXPKT_NUM (Offset 0x0284) */ -#define BIT_SHIFT_MDIO_PHY_ADDR 24 -#define BIT_MASK_MDIO_PHY_ADDR 0x1f -#define BIT_MDIO_PHY_ADDR(x) (((x) & BIT_MASK_MDIO_PHY_ADDR) << BIT_SHIFT_MDIO_PHY_ADDR) -#define BIT_GET_MDIO_PHY_ADDR(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR) & BIT_MASK_MDIO_PHY_ADDR) +#define BIT_RXDMA_REQ BIT(19) +#define BIT_RW_RELEASE_EN BIT(18) +#define BIT_RXDMA_IDLE BIT(17) +#define BIT_RXPKT_RELEASE_POLL BIT(16) +#define BIT_SHIFT_FW_UPD_RDPTR 0 +#define BIT_MASK_FW_UPD_RDPTR 0xffff +#define BIT_FW_UPD_RDPTR(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR) << BIT_SHIFT_FW_UPD_RDPTR) +#define BITS_FW_UPD_RDPTR (BIT_MASK_FW_UPD_RDPTR << BIT_SHIFT_FW_UPD_RDPTR) +#define BIT_CLEAR_FW_UPD_RDPTR(x) ((x) & (~BITS_FW_UPD_RDPTR)) +#define BIT_GET_FW_UPD_RDPTR(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR) & BIT_MASK_FW_UPD_RDPTR) +#define BIT_SET_FW_UPD_RDPTR(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR(x) | BIT_FW_UPD_RDPTR(v)) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#define BIT_FC2H_PKT_OVERFLOW BIT(8) -/* 2 REG_C2H_PKT (Offset 0x0294) */ +#endif -#define BIT_R_C2H_PKT_REQ BIT(16) -#define BIT_RX_CLOSE_EN BIT(15) -#define BIT_STOP_BCNQ BIT(14) -#define BIT_STOP_MGQ BIT(13) -#define BIT_STOP_VOQ BIT(12) -#define BIT_STOP_VIQ BIT(11) -#define BIT_STOP_BEQ BIT(10) -#define BIT_STOP_BKQ BIT(9) -#define BIT_STOP_RXQ BIT(8) -#define BIT_STOP_HI7Q BIT(7) -#define BIT_STOP_HI6Q BIT(6) -#define BIT_STOP_HI5Q BIT(5) -#define BIT_STOP_HI4Q BIT(4) -#define BIT_STOP_HI3Q BIT(3) -#define BIT_STOP_HI2Q BIT(2) -#define BIT_STOP_HI1Q BIT(1) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_C2H_STR_ADDR 0 -#define BIT_MASK_R_C2H_STR_ADDR 0xffff -#define BIT_R_C2H_STR_ADDR(x) (((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR) -#define BIT_GET_R_C2H_STR_ADDR(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR) +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ -#define BIT_STOP_HI0Q BIT(0) +#define BIT_C2H_PKT_OVF BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FWFF_C2H (Offset 0x0298) */ +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#define BIT_AGG_CFG_ISSUE BIT(6) -#define BIT_SHIFT_C2H_DMA_ADDR 0 -#define BIT_MASK_C2H_DMA_ADDR 0x3ffff -#define BIT_C2H_DMA_ADDR(x) (((x) & BIT_MASK_C2H_DMA_ADDR) << BIT_SHIFT_C2H_DMA_ADDR) -#define BIT_GET_C2H_DMA_ADDR(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR) & BIT_MASK_C2H_DMA_ADDR) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWFF_CTRL (Offset 0x029C) */ +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ -#define BIT_FWFF_DMAPKT_REQ BIT(31) +#define BIT_AGG_CONFGI_ISSUE BIT(6) -#define BIT_SHIFT_FWFF_DMA_PKT_NUM 16 -#define BIT_MASK_FWFF_DMA_PKT_NUM 0xff -#define BIT_FWFF_DMA_PKT_NUM(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM) << BIT_SHIFT_FWFF_DMA_PKT_NUM) -#define BIT_GET_FWFF_DMA_PKT_NUM(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM) & BIT_MASK_FWFF_DMA_PKT_NUM) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FWFF_STR_ADDR 0 -#define BIT_MASK_FWFF_STR_ADDR 0xffff -#define BIT_FWFF_STR_ADDR(x) (((x) & BIT_MASK_FWFF_STR_ADDR) << BIT_SHIFT_FWFF_STR_ADDR) -#define BIT_GET_FWFF_STR_ADDR(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR) & BIT_MASK_FWFF_STR_ADDR) +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#define BIT_FW_POLL_ISSUE BIT(5) +#define BIT_RX_DATA_UDN BIT(4) +#define BIT_RX_SFF_UDN BIT(3) +#define BIT_RX_SFF_OVF BIT(2) -/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FWFF_PKT_QUEUED 16 -#define BIT_MASK_FWFF_PKT_QUEUED 0xff -#define BIT_FWFF_PKT_QUEUED(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED) << BIT_SHIFT_FWFF_PKT_QUEUED) -#define BIT_GET_FWFF_PKT_QUEUED(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED) & BIT_MASK_FWFF_PKT_QUEUED) +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#define BIT_USB_REQ_LEN_OVF BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#define BIT_RXPKT_OVF BIT(0) -/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +/* 2 REG_RXDMA_DPR (Offset 0x028C) */ +#define BIT_SHIFT_RDE_DEBUG 0 +#define BIT_MASK_RDE_DEBUG 0xffffffffL +#define BIT_RDE_DEBUG(x) (((x) & BIT_MASK_RDE_DEBUG) << BIT_SHIFT_RDE_DEBUG) +#define BITS_RDE_DEBUG (BIT_MASK_RDE_DEBUG << BIT_SHIFT_RDE_DEBUG) +#define BIT_CLEAR_RDE_DEBUG(x) ((x) & (~BITS_RDE_DEBUG)) +#define BIT_GET_RDE_DEBUG(x) (((x) >> BIT_SHIFT_RDE_DEBUG) & BIT_MASK_RDE_DEBUG) +#define BIT_SET_RDE_DEBUG(x, v) (BIT_CLEAR_RDE_DEBUG(x) | BIT_RDE_DEBUG(v)) -#define BIT_SHIFT_FWFF_PKT_STR_ADDR 0 -#define BIT_MASK_FWFF_PKT_STR_ADDR 0xffff -#define BIT_FWFF_PKT_STR_ADDR(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR) << BIT_SHIFT_FWFF_PKT_STR_ADDR) -#define BIT_GET_FWFF_PKT_STR_ADDR(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR) & BIT_MASK_FWFF_PKT_STR_ADDR) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_SHIFT_PKTNUM_TH_V2 24 +#define BIT_MASK_PKTNUM_TH_V2 0x1f +#define BIT_PKTNUM_TH_V2(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V2) << BIT_SHIFT_PKTNUM_TH_V2) +#define BITS_PKTNUM_TH_V2 (BIT_MASK_PKTNUM_TH_V2 << BIT_SHIFT_PKTNUM_TH_V2) +#define BIT_CLEAR_PKTNUM_TH_V2(x) ((x) & (~BITS_PKTNUM_TH_V2)) +#define BIT_GET_PKTNUM_TH_V2(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V2) & BIT_MASK_PKTNUM_TH_V2) +#define BIT_SET_PKTNUM_TH_V2(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V2(x) | BIT_PKTNUM_TH_V2(v)) -#if (HALMAC_8814AMP_SUPPORT) +#define BIT_TXBA_BREAK_USBAGG BIT(23) +#define BIT_SHIFT_PKTLEN_PARA 16 +#define BIT_MASK_PKTLEN_PARA 0x7 +#define BIT_PKTLEN_PARA(x) \ + (((x) & BIT_MASK_PKTLEN_PARA) << BIT_SHIFT_PKTLEN_PARA) +#define BITS_PKTLEN_PARA (BIT_MASK_PKTLEN_PARA << BIT_SHIFT_PKTLEN_PARA) +#define BIT_CLEAR_PKTLEN_PARA(x) ((x) & (~BITS_PKTLEN_PARA)) +#define BIT_GET_PKTLEN_PARA(x) \ + (((x) >> BIT_SHIFT_PKTLEN_PARA) & BIT_MASK_PKTLEN_PARA) +#define BIT_SET_PKTLEN_PARA(x, v) \ + (BIT_CLEAR_PKTLEN_PARA(x) | BIT_PKTLEN_PARA(v)) -/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V1 0 -#define BIT_MASK_FWFF_PKT_STR_ADDR_V1 0x7ff -#define BIT_FWFF_PKT_STR_ADDR_V1(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V1) << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) -#define BIT_GET_FWFF_PKT_STR_ADDR_V1(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) & BIT_MASK_FWFF_PKT_STR_ADDR_V1) +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_EN_SDIO_FAIL BIT(9) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_GRAYCODE_SYNC_WITH_BIN BIT(8) -/* 2 REG_FC2H_INFO (Offset 0x02A6) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_FC2H_STR_ADDR 17 -#define BIT_MASK_FC2H_STR_ADDR 0x7fff -#define BIT_FC2H_STR_ADDR(x) (((x) & BIT_MASK_FC2H_STR_ADDR) << BIT_SHIFT_FC2H_STR_ADDR) -#define BIT_GET_FC2H_STR_ADDR(x) (((x) >> BIT_SHIFT_FC2H_STR_ADDR) & BIT_MASK_FC2H_STR_ADDR) +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ -#define BIT_FC2H_PKT_REQ BIT(16) +#define BIT_RXDMA_DBD_SEL BIT(7) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_RX_DBG_SEL BIT(7) -/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#endif -#define BIT_PCIEIO_PERSTB_SEL BIT(31) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_EN_SPD BIT(6) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_HCI_CTRL (Offset 0x0300) */ +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ + +#define BIT_SHIFT_BURST_SIZE 4 +#define BIT_MASK_BURST_SIZE 0x3 +#define BIT_BURST_SIZE(x) (((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE) +#define BITS_BURST_SIZE (BIT_MASK_BURST_SIZE << BIT_SHIFT_BURST_SIZE) +#define BIT_CLEAR_BURST_SIZE(x) ((x) & (~BITS_BURST_SIZE)) +#define BIT_GET_BURST_SIZE(x) \ + (((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE) +#define BIT_SET_BURST_SIZE(x, v) (BIT_CLEAR_BURST_SIZE(x) | BIT_BURST_SIZE(v)) -#define BIT_HCIIO_PERSTB_SEL BIT(31) +#define BIT_SHIFT_BURST_CNT 2 +#define BIT_MASK_BURST_CNT 0x3 +#define BIT_BURST_CNT(x) (((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT) +#define BITS_BURST_CNT (BIT_MASK_BURST_CNT << BIT_SHIFT_BURST_CNT) +#define BIT_CLEAR_BURST_CNT(x) ((x) & (~BITS_BURST_CNT)) +#define BIT_GET_BURST_CNT(x) (((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT) +#define BIT_SET_BURST_CNT(x, v) (BIT_CLEAR_BURST_CNT(x) | BIT_BURST_CNT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_DAM_MODE BIT(1) -/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PCIE_MAX_RXDMA 28 -#define BIT_MASK_PCIE_MAX_RXDMA 0x7 -#define BIT_PCIE_MAX_RXDMA(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA) << BIT_SHIFT_PCIE_MAX_RXDMA) -#define BIT_GET_PCIE_MAX_RXDMA(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA) & BIT_MASK_PCIE_MAX_RXDMA) +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_DMA_MODE BIT(1) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_C2H_PKT (Offset 0x0294) */ -/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19 24 +#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19 0xf +#define BIT_R_C2H_STR_ADDR_16_TO_19(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19) \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) +#define BITS_R_C2H_STR_ADDR_16_TO_19 \ + (BIT_MASK_R_C2H_STR_ADDR_16_TO_19 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19(x) \ + ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) & \ + BIT_MASK_R_C2H_STR_ADDR_16_TO_19) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19(x) | BIT_R_C2H_STR_ADDR_16_TO_19(v)) + +#define BIT_SHIFT_MDIO_PHY_ADDR 24 +#define BIT_MASK_MDIO_PHY_ADDR 0x1f +#define BIT_MDIO_PHY_ADDR(x) \ + (((x) & BIT_MASK_MDIO_PHY_ADDR) << BIT_SHIFT_MDIO_PHY_ADDR) +#define BITS_MDIO_PHY_ADDR (BIT_MASK_MDIO_PHY_ADDR << BIT_SHIFT_MDIO_PHY_ADDR) +#define BIT_CLEAR_MDIO_PHY_ADDR(x) ((x) & (~BITS_MDIO_PHY_ADDR)) +#define BIT_GET_MDIO_PHY_ADDR(x) \ + (((x) >> BIT_SHIFT_MDIO_PHY_ADDR) & BIT_MASK_MDIO_PHY_ADDR) +#define BIT_SET_MDIO_PHY_ADDR(x, v) \ + (BIT_CLEAR_MDIO_PHY_ADDR(x) | BIT_MDIO_PHY_ADDR(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) +/* 2 REG_C2H_PKT (Offset 0x0294) */ -#define BIT_SHIFT_HCI_MAX_RXDMA 28 -#define BIT_MASK_HCI_MAX_RXDMA 0x7 -#define BIT_HCI_MAX_RXDMA(x) (((x) & BIT_MASK_HCI_MAX_RXDMA) << BIT_SHIFT_HCI_MAX_RXDMA) -#define BIT_GET_HCI_MAX_RXDMA(x) (((x) >> BIT_SHIFT_HCI_MAX_RXDMA) & BIT_MASK_HCI_MAX_RXDMA) +#define BIT_R_C2H_PKT_REQ BIT(16) +#define BIT_SHIFT_R_C2H_STR_ADDR 0 +#define BIT_MASK_R_C2H_STR_ADDR 0xffff +#define BIT_R_C2H_STR_ADDR(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR) +#define BITS_R_C2H_STR_ADDR \ + (BIT_MASK_R_C2H_STR_ADDR << BIT_SHIFT_R_C2H_STR_ADDR) +#define BIT_CLEAR_R_C2H_STR_ADDR(x) ((x) & (~BITS_R_C2H_STR_ADDR)) +#define BIT_GET_R_C2H_STR_ADDR(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR) +#define BIT_SET_R_C2H_STR_ADDR(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR(x) | BIT_R_C2H_STR_ADDR(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_FWFF_C2H (Offset 0x0298) */ +#define BIT_SHIFT_C2H_DMA_ADDR 0 +#define BIT_MASK_C2H_DMA_ADDR 0x3ffff +#define BIT_C2H_DMA_ADDR(x) \ + (((x) & BIT_MASK_C2H_DMA_ADDR) << BIT_SHIFT_C2H_DMA_ADDR) +#define BITS_C2H_DMA_ADDR (BIT_MASK_C2H_DMA_ADDR << BIT_SHIFT_C2H_DMA_ADDR) +#define BIT_CLEAR_C2H_DMA_ADDR(x) ((x) & (~BITS_C2H_DMA_ADDR)) +#define BIT_GET_C2H_DMA_ADDR(x) \ + (((x) >> BIT_SHIFT_C2H_DMA_ADDR) & BIT_MASK_C2H_DMA_ADDR) +#define BIT_SET_C2H_DMA_ADDR(x, v) \ + (BIT_CLEAR_C2H_DMA_ADDR(x) | BIT_C2H_DMA_ADDR(v)) -/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +/* 2 REG_FWFF_CTRL (Offset 0x029C) */ -#define BIT_RX_LIT_EDN_SEL BIT(27) -#define BIT_TX_LIT_EDN_SEL BIT(26) -#define BIT_WT_LIT_EDN BIT(25) +#define BIT_FWFF_DMAPKT_REQ BIT(31) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWFF_CTRL (Offset 0x029C) */ +#define BIT_SHIFT_FWFF_DMA_PKT_NUM 16 +#define BIT_MASK_FWFF_DMA_PKT_NUM 0xff +#define BIT_FWFF_DMA_PKT_NUM(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM) << BIT_SHIFT_FWFF_DMA_PKT_NUM) +#define BITS_FWFF_DMA_PKT_NUM \ + (BIT_MASK_FWFF_DMA_PKT_NUM << BIT_SHIFT_FWFF_DMA_PKT_NUM) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM)) +#define BIT_GET_FWFF_DMA_PKT_NUM(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM) & BIT_MASK_FWFF_DMA_PKT_NUM) +#define BIT_SET_FWFF_DMA_PKT_NUM(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM(x) | BIT_FWFF_DMA_PKT_NUM(v)) -/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_PCIE_MAX_TXDMA 24 -#define BIT_MASK_PCIE_MAX_TXDMA 0x7 -#define BIT_PCIE_MAX_TXDMA(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA) << BIT_SHIFT_PCIE_MAX_TXDMA) -#define BIT_GET_PCIE_MAX_TXDMA(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA) & BIT_MASK_PCIE_MAX_TXDMA) +/* 2 REG_FWFF_CTRL (Offset 0x029C) */ +#define BIT_SHIFT_FWFF_DMA_PKT_NUM_V1 16 +#define BIT_MASK_FWFF_DMA_PKT_NUM_V1 0x7fff +#define BIT_FWFF_DMA_PKT_NUM_V1(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_V1) << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1) +#define BITS_FWFF_DMA_PKT_NUM_V1 \ + (BIT_MASK_FWFF_DMA_PKT_NUM_V1 << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_V1(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM_V1)) +#define BIT_GET_FWFF_DMA_PKT_NUM_V1(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_V1) & BIT_MASK_FWFF_DMA_PKT_NUM_V1) +#define BIT_SET_FWFF_DMA_PKT_NUM_V1(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM_V1(x) | BIT_FWFF_DMA_PKT_NUM_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FWFF_CTRL (Offset 0x029C) */ +#define BIT_SHIFT_FWFF_STR_ADDR 0 +#define BIT_MASK_FWFF_STR_ADDR 0xffff +#define BIT_FWFF_STR_ADDR(x) \ + (((x) & BIT_MASK_FWFF_STR_ADDR) << BIT_SHIFT_FWFF_STR_ADDR) +#define BITS_FWFF_STR_ADDR (BIT_MASK_FWFF_STR_ADDR << BIT_SHIFT_FWFF_STR_ADDR) +#define BIT_CLEAR_FWFF_STR_ADDR(x) ((x) & (~BITS_FWFF_STR_ADDR)) +#define BIT_GET_FWFF_STR_ADDR(x) \ + (((x) >> BIT_SHIFT_FWFF_STR_ADDR) & BIT_MASK_FWFF_STR_ADDR) +#define BIT_SET_FWFF_STR_ADDR(x, v) \ + (BIT_CLEAR_FWFF_STR_ADDR(x) | BIT_FWFF_STR_ADDR(v)) -/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HCI_MAX_TXDMA 24 -#define BIT_MASK_HCI_MAX_TXDMA 0x7 -#define BIT_HCI_MAX_TXDMA(x) (((x) & BIT_MASK_HCI_MAX_TXDMA) << BIT_SHIFT_HCI_MAX_TXDMA) -#define BIT_GET_HCI_MAX_TXDMA(x) (((x) >> BIT_SHIFT_HCI_MAX_TXDMA) & BIT_MASK_HCI_MAX_TXDMA) +/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#define BIT_SHIFT_FWFF_PKT_QUEUED 16 +#define BIT_MASK_FWFF_PKT_QUEUED 0xff +#define BIT_FWFF_PKT_QUEUED(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED) << BIT_SHIFT_FWFF_PKT_QUEUED) +#define BITS_FWFF_PKT_QUEUED \ + (BIT_MASK_FWFF_PKT_QUEUED << BIT_SHIFT_FWFF_PKT_QUEUED) +#define BIT_CLEAR_FWFF_PKT_QUEUED(x) ((x) & (~BITS_FWFF_PKT_QUEUED)) +#define BIT_GET_FWFF_PKT_QUEUED(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED) & BIT_MASK_FWFF_PKT_QUEUED) +#define BIT_SET_FWFF_PKT_QUEUED(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED(x) | BIT_FWFF_PKT_QUEUED(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - - -/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ -#define BIT_RD_LITT_EDN BIT(24) +#define BIT_SHIFT_FWFF_PKT_READ_ADDR 16 +#define BIT_MASK_FWFF_PKT_READ_ADDR 0xffff +#define BIT_FWFF_PKT_READ_ADDR(x) \ + (((x) & BIT_MASK_FWFF_PKT_READ_ADDR) << BIT_SHIFT_FWFF_PKT_READ_ADDR) +#define BITS_FWFF_PKT_READ_ADDR \ + (BIT_MASK_FWFF_PKT_READ_ADDR << BIT_SHIFT_FWFF_PKT_READ_ADDR) +#define BIT_CLEAR_FWFF_PKT_READ_ADDR(x) ((x) & (~BITS_FWFF_PKT_READ_ADDR)) +#define BIT_GET_FWFF_PKT_READ_ADDR(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_READ_ADDR) & BIT_MASK_FWFF_PKT_READ_ADDR) +#define BIT_SET_FWFF_PKT_READ_ADDR(x, v) \ + (BIT_CLEAR_FWFF_PKT_READ_ADDR(x) | BIT_FWFF_PKT_READ_ADDR(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#define BIT_ECRC_EN_V1 BIT(7) +#define BIT_MDIO_RFLAG_V1 BIT(6) +#define BIT_MDIO_WFLAG_V1 BIT(5) -/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#endif -#define BIT_PCIE_RST_TRXDMA_INTF BIT(20) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#define BIT_SHIFT_FWFF_PKT_STR_ADDR 0 +#define BIT_MASK_FWFF_PKT_STR_ADDR 0xffff +#define BIT_FWFF_PKT_STR_ADDR(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR) << BIT_SHIFT_FWFF_PKT_STR_ADDR) +#define BITS_FWFF_PKT_STR_ADDR \ + (BIT_MASK_FWFF_PKT_STR_ADDR << BIT_SHIFT_FWFF_PKT_STR_ADDR) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR)) +#define BIT_GET_FWFF_PKT_STR_ADDR(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR) & BIT_MASK_FWFF_PKT_STR_ADDR) +#define BIT_SET_FWFF_PKT_STR_ADDR(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR(x) | BIT_FWFF_PKT_STR_ADDR(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814AMP_SUPPORT) -/* 2 REG_HCI_CTRL (Offset 0x0300) */ +/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ -#define BIT_HCI_RST_TRXDMA_INTF BIT(20) +#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V1 0 +#define BIT_MASK_FWFF_PKT_STR_ADDR_V1 0x7ff +#define BIT_FWFF_PKT_STR_ADDR_V1(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V1) \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) +#define BITS_FWFF_PKT_STR_ADDR_V1 \ + (BIT_MASK_FWFF_PKT_STR_ADDR_V1 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V1(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_V1)) +#define BIT_GET_FWFF_PKT_STR_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) & \ + BIT_MASK_FWFF_PKT_STR_ADDR_V1) +#define BIT_SET_FWFF_PKT_STR_ADDR_V1(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR_V1(x) | BIT_FWFF_PKT_STR_ADDR_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#define BIT_SHIFT_FWFF_PKT_WRITE_ADDR 0 +#define BIT_MASK_FWFF_PKT_WRITE_ADDR 0xffff +#define BIT_FWFF_PKT_WRITE_ADDR(x) \ + (((x) & BIT_MASK_FWFF_PKT_WRITE_ADDR) << BIT_SHIFT_FWFF_PKT_WRITE_ADDR) +#define BITS_FWFF_PKT_WRITE_ADDR \ + (BIT_MASK_FWFF_PKT_WRITE_ADDR << BIT_SHIFT_FWFF_PKT_WRITE_ADDR) +#define BIT_CLEAR_FWFF_PKT_WRITE_ADDR(x) ((x) & (~BITS_FWFF_PKT_WRITE_ADDR)) +#define BIT_GET_FWFF_PKT_WRITE_ADDR(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_WRITE_ADDR) & BIT_MASK_FWFF_PKT_WRITE_ADDR) +#define BIT_SET_FWFF_PKT_WRITE_ADDR(x, v) \ + (BIT_CLEAR_FWFF_PKT_WRITE_ADDR(x) | BIT_FWFF_PKT_WRITE_ADDR(v)) -/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#endif +#if (HALMAC_8197F_SUPPORT) -#define BIT_SHIFT_MAX_RXDMA 20 -#define BIT_MASK_MAX_RXDMA 0x7 -#define BIT_MAX_RXDMA(x) (((x) & BIT_MASK_MAX_RXDMA) << BIT_SHIFT_MAX_RXDMA) -#define BIT_GET_MAX_RXDMA(x) (((x) >> BIT_SHIFT_MAX_RXDMA) & BIT_MASK_MAX_RXDMA) +/* 2 REG_FC2H_INFO (Offset 0x02A4) */ +#define BIT_FC2H_PKT_REQ BIT(16) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FC2H_INFO (Offset 0x02A4) */ +#define BIT_FC2H_DMAPKT_REQ BIT(16) -/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_PCIE_EN_SWENT_L23 BIT(17) +/* 2 REG_FC2H_INFO (Offset 0x02A4) */ + +#define BIT_SHIFT_FC2H_STR_ADDR 0 +#define BIT_MASK_FC2H_STR_ADDR 0xffff +#define BIT_FC2H_STR_ADDR(x) \ + (((x) & BIT_MASK_FC2H_STR_ADDR) << BIT_SHIFT_FC2H_STR_ADDR) +#define BITS_FC2H_STR_ADDR (BIT_MASK_FC2H_STR_ADDR << BIT_SHIFT_FC2H_STR_ADDR) +#define BIT_CLEAR_FC2H_STR_ADDR(x) ((x) & (~BITS_FC2H_STR_ADDR)) +#define BIT_GET_FC2H_STR_ADDR(x) \ + (((x) >> BIT_SHIFT_FC2H_STR_ADDR) & BIT_MASK_FC2H_STR_ADDR) +#define BIT_SET_FC2H_STR_ADDR(x, v) \ + (BIT_CLEAR_FC2H_STR_ADDR(x) | BIT_FC2H_STR_ADDR(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FWFF_PKT_INFO2 (Offset 0x02A4) */ +#define BIT_SHIFT_FWFF_PKT_QUEUED_V1 0 +#define BIT_MASK_FWFF_PKT_QUEUED_V1 0xffff +#define BIT_FWFF_PKT_QUEUED_V1(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED_V1) << BIT_SHIFT_FWFF_PKT_QUEUED_V1) +#define BITS_FWFF_PKT_QUEUED_V1 \ + (BIT_MASK_FWFF_PKT_QUEUED_V1 << BIT_SHIFT_FWFF_PKT_QUEUED_V1) +#define BIT_CLEAR_FWFF_PKT_QUEUED_V1(x) ((x) & (~BITS_FWFF_PKT_QUEUED_V1)) +#define BIT_GET_FWFF_PKT_QUEUED_V1(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_V1) & BIT_MASK_FWFF_PKT_QUEUED_V1) +#define BIT_SET_FWFF_PKT_QUEUED_V1(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED_V1(x) | BIT_FWFF_PKT_QUEUED_V1(v)) + +#define BIT_SHIFT_FW_UPD_RXDES_RD_PTR 0 +#define BIT_MASK_FW_UPD_RXDES_RD_PTR 0x3ffff +#define BIT_FW_UPD_RXDES_RD_PTR(x) \ + (((x) & BIT_MASK_FW_UPD_RXDES_RD_PTR) << BIT_SHIFT_FW_UPD_RXDES_RD_PTR) +#define BITS_FW_UPD_RXDES_RD_PTR \ + (BIT_MASK_FW_UPD_RXDES_RD_PTR << BIT_SHIFT_FW_UPD_RXDES_RD_PTR) +#define BIT_CLEAR_FW_UPD_RXDES_RD_PTR(x) ((x) & (~BITS_FW_UPD_RXDES_RD_PTR)) +#define BIT_GET_FW_UPD_RXDES_RD_PTR(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RXDES_RD_PTR) & BIT_MASK_FW_UPD_RXDES_RD_PTR) +#define BIT_SET_FW_UPD_RXDES_RD_PTR(x, v) \ + (BIT_CLEAR_FW_UPD_RXDES_RD_PTR(x) | BIT_FW_UPD_RXDES_RD_PTR(v)) + +#endif -/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_HCI_EN_SWENT_L23 BIT(17) +/* 2 REG_RXPKTNUM (Offset 0x02B0) */ -#endif +#define BIT_SHIFT_PKT_NUM_WOL_V1 16 +#define BIT_MASK_PKT_NUM_WOL_V1 0xffff +#define BIT_PKT_NUM_WOL_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL_V1) << BIT_SHIFT_PKT_NUM_WOL_V1) +#define BITS_PKT_NUM_WOL_V1 \ + (BIT_MASK_PKT_NUM_WOL_V1 << BIT_SHIFT_PKT_NUM_WOL_V1) +#define BIT_CLEAR_PKT_NUM_WOL_V1(x) ((x) & (~BITS_PKT_NUM_WOL_V1)) +#define BIT_GET_PKT_NUM_WOL_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL_V1) & BIT_MASK_PKT_NUM_WOL_V1) +#define BIT_SET_PKT_NUM_WOL_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL_V1(x) | BIT_PKT_NUM_WOL_V1(v)) +#define BIT_SHIFT_RXPKT_NUM_V1 0 +#define BIT_MASK_RXPKT_NUM_V1 0xffff +#define BIT_RXPKT_NUM_V1(x) \ + (((x) & BIT_MASK_RXPKT_NUM_V1) << BIT_SHIFT_RXPKT_NUM_V1) +#define BITS_RXPKT_NUM_V1 (BIT_MASK_RXPKT_NUM_V1 << BIT_SHIFT_RXPKT_NUM_V1) +#define BIT_CLEAR_RXPKT_NUM_V1(x) ((x) & (~BITS_RXPKT_NUM_V1)) +#define BIT_GET_RXPKT_NUM_V1(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_V1) & BIT_MASK_RXPKT_NUM_V1) +#define BIT_SET_RXPKT_NUM_V1(x, v) \ + (BIT_CLEAR_RXPKT_NUM_V1(x) | BIT_RXPKT_NUM_V1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_RXPKT_NUM_TH 0 +#define BIT_MASK_RXPKT_NUM_TH 0xff +#define BIT_RXPKT_NUM_TH(x) \ + (((x) & BIT_MASK_RXPKT_NUM_TH) << BIT_SHIFT_RXPKT_NUM_TH) +#define BITS_RXPKT_NUM_TH (BIT_MASK_RXPKT_NUM_TH << BIT_SHIFT_RXPKT_NUM_TH) +#define BIT_CLEAR_RXPKT_NUM_TH(x) ((x) & (~BITS_RXPKT_NUM_TH)) +#define BIT_GET_RXPKT_NUM_TH(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_TH) & BIT_MASK_RXPKT_NUM_TH) +#define BIT_SET_RXPKT_NUM_TH(x, v) \ + (BIT_CLEAR_RXPKT_NUM_TH(x) | BIT_RXPKT_NUM_TH(v)) +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_FW_MSG1 (Offset 0x02E0) */ + +#define BIT_SHIFT_FW_MSG_REG1 0 +#define BIT_MASK_FW_MSG_REG1 0xffffffffL +#define BIT_FW_MSG_REG1(x) \ + (((x) & BIT_MASK_FW_MSG_REG1) << BIT_SHIFT_FW_MSG_REG1) +#define BITS_FW_MSG_REG1 (BIT_MASK_FW_MSG_REG1 << BIT_SHIFT_FW_MSG_REG1) +#define BIT_CLEAR_FW_MSG_REG1(x) ((x) & (~BITS_FW_MSG_REG1)) +#define BIT_GET_FW_MSG_REG1(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG1) & BIT_MASK_FW_MSG_REG1) +#define BIT_SET_FW_MSG_REG1(x, v) \ + (BIT_CLEAR_FW_MSG_REG1(x) | BIT_FW_MSG_REG1(v)) + +/* 2 REG_FW_MSG2 (Offset 0x02E4) */ + +#define BIT_SHIFT_FW_MSG_REG2 0 +#define BIT_MASK_FW_MSG_REG2 0xffffffffL +#define BIT_FW_MSG_REG2(x) \ + (((x) & BIT_MASK_FW_MSG_REG2) << BIT_SHIFT_FW_MSG_REG2) +#define BITS_FW_MSG_REG2 (BIT_MASK_FW_MSG_REG2 << BIT_SHIFT_FW_MSG_REG2) +#define BIT_CLEAR_FW_MSG_REG2(x) ((x) & (~BITS_FW_MSG_REG2)) +#define BIT_GET_FW_MSG_REG2(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG2) & BIT_MASK_FW_MSG_REG2) +#define BIT_SET_FW_MSG_REG2(x, v) \ + (BIT_CLEAR_FW_MSG_REG2(x) | BIT_FW_MSG_REG2(v)) + +/* 2 REG_FW_MSG3 (Offset 0x02E8) */ + +#define BIT_SHIFT_FW_MSG_REG3 0 +#define BIT_MASK_FW_MSG_REG3 0xffffffffL +#define BIT_FW_MSG_REG3(x) \ + (((x) & BIT_MASK_FW_MSG_REG3) << BIT_SHIFT_FW_MSG_REG3) +#define BITS_FW_MSG_REG3 (BIT_MASK_FW_MSG_REG3 << BIT_SHIFT_FW_MSG_REG3) +#define BIT_CLEAR_FW_MSG_REG3(x) ((x) & (~BITS_FW_MSG_REG3)) +#define BIT_GET_FW_MSG_REG3(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG3) & BIT_MASK_FW_MSG_REG3) +#define BIT_SET_FW_MSG_REG3(x, v) \ + (BIT_CLEAR_FW_MSG_REG3(x) | BIT_FW_MSG_REG3(v)) + +/* 2 REG_FW_MSG4 (Offset 0x02EC) */ + +#define BIT_SHIFT_FW_MSG_REG4 0 +#define BIT_MASK_FW_MSG_REG4 0xffffffffL +#define BIT_FW_MSG_REG4(x) \ + (((x) & BIT_MASK_FW_MSG_REG4) << BIT_SHIFT_FW_MSG_REG4) +#define BITS_FW_MSG_REG4 (BIT_MASK_FW_MSG_REG4 << BIT_SHIFT_FW_MSG_REG4) +#define BIT_CLEAR_FW_MSG_REG4(x) ((x) & (~BITS_FW_MSG_REG4)) +#define BIT_GET_FW_MSG_REG4(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG4) & BIT_MASK_FW_MSG_REG4) +#define BIT_SET_FW_MSG_REG4(x, v) \ + (BIT_CLEAR_FW_MSG_REG4(x) | BIT_FW_MSG_REG4(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ -#define BIT_PCIE_EN_HWEXT_L1 BIT(16) +#define BIT_PCIEIO_PERSTB_SEL BIT(31) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_CTRL (Offset 0x0300) */ -#define BIT_HCI_EN_HWEXT_L1 BIT(16) +#define BIT_HCIIO_PERSTB_SEL BIT(31) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_SHIFT_PCIE_MAX_RXDMA 28 +#define BIT_MASK_PCIE_MAX_RXDMA 0x7 +#define BIT_PCIE_MAX_RXDMA(x) \ + (((x) & BIT_MASK_PCIE_MAX_RXDMA) << BIT_SHIFT_PCIE_MAX_RXDMA) +#define BITS_PCIE_MAX_RXDMA \ + (BIT_MASK_PCIE_MAX_RXDMA << BIT_SHIFT_PCIE_MAX_RXDMA) +#define BIT_CLEAR_PCIE_MAX_RXDMA(x) ((x) & (~BITS_PCIE_MAX_RXDMA)) +#define BIT_GET_PCIE_MAX_RXDMA(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA) & BIT_MASK_PCIE_MAX_RXDMA) +#define BIT_SET_PCIE_MAX_RXDMA(x, v) \ + (BIT_CLEAR_PCIE_MAX_RXDMA(x) | BIT_PCIE_MAX_RXDMA(v)) -/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_MAX_TXDMA 16 -#define BIT_MASK_MAX_TXDMA 0x7 -#define BIT_MAX_TXDMA(x) (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA) -#define BIT_GET_MAX_TXDMA(x) (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA) +/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_SHIFT_HCI_MAX_RXDMA 28 +#define BIT_MASK_HCI_MAX_RXDMA 0x7 +#define BIT_HCI_MAX_RXDMA(x) \ + (((x) & BIT_MASK_HCI_MAX_RXDMA) << BIT_SHIFT_HCI_MAX_RXDMA) +#define BITS_HCI_MAX_RXDMA (BIT_MASK_HCI_MAX_RXDMA << BIT_SHIFT_HCI_MAX_RXDMA) +#define BIT_CLEAR_HCI_MAX_RXDMA(x) ((x) & (~BITS_HCI_MAX_RXDMA)) +#define BIT_GET_HCI_MAX_RXDMA(x) \ + (((x) >> BIT_SHIFT_HCI_MAX_RXDMA) & BIT_MASK_HCI_MAX_RXDMA) +#define BIT_SET_HCI_MAX_RXDMA(x, v) \ + (BIT_CLEAR_HCI_MAX_RXDMA(x) | BIT_HCI_MAX_RXDMA(v)) #endif +#if (HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#define BIT_RX_LIT_EDN_SEL BIT(27) +#define BIT_TX_LIT_EDN_SEL BIT(26) +#define BIT_WT_LIT_EDN BIT(25) -/* 2 REG_INT_MIG (Offset 0x0304) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TXTTIMER_MATCH_NUM 28 -#define BIT_MASK_TXTTIMER_MATCH_NUM 0xf -#define BIT_TXTTIMER_MATCH_NUM(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM) << BIT_SHIFT_TXTTIMER_MATCH_NUM) -#define BIT_GET_TXTTIMER_MATCH_NUM(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM) & BIT_MASK_TXTTIMER_MATCH_NUM) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_SHIFT_PCIE_MAX_TXDMA 24 +#define BIT_MASK_PCIE_MAX_TXDMA 0x7 +#define BIT_PCIE_MAX_TXDMA(x) \ + (((x) & BIT_MASK_PCIE_MAX_TXDMA) << BIT_SHIFT_PCIE_MAX_TXDMA) +#define BITS_PCIE_MAX_TXDMA \ + (BIT_MASK_PCIE_MAX_TXDMA << BIT_SHIFT_PCIE_MAX_TXDMA) +#define BIT_CLEAR_PCIE_MAX_TXDMA(x) ((x) & (~BITS_PCIE_MAX_TXDMA)) +#define BIT_GET_PCIE_MAX_TXDMA(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA) & BIT_MASK_PCIE_MAX_TXDMA) +#define BIT_SET_PCIE_MAX_TXDMA(x, v) \ + (BIT_CLEAR_PCIE_MAX_TXDMA(x) | BIT_PCIE_MAX_TXDMA(v)) -#define BIT_SHIFT_TXPKT_NUM_MATCH 24 -#define BIT_MASK_TXPKT_NUM_MATCH 0xf -#define BIT_TXPKT_NUM_MATCH(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH) << BIT_SHIFT_TXPKT_NUM_MATCH) -#define BIT_GET_TXPKT_NUM_MATCH(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH) & BIT_MASK_TXPKT_NUM_MATCH) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RXTTIMER_MATCH_NUM 20 -#define BIT_MASK_RXTTIMER_MATCH_NUM 0xf -#define BIT_RXTTIMER_MATCH_NUM(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM) << BIT_SHIFT_RXTTIMER_MATCH_NUM) -#define BIT_GET_RXTTIMER_MATCH_NUM(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM) & BIT_MASK_RXTTIMER_MATCH_NUM) +/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_SHIFT_HCI_MAX_TXDMA 24 +#define BIT_MASK_HCI_MAX_TXDMA 0x7 +#define BIT_HCI_MAX_TXDMA(x) \ + (((x) & BIT_MASK_HCI_MAX_TXDMA) << BIT_SHIFT_HCI_MAX_TXDMA) +#define BITS_HCI_MAX_TXDMA (BIT_MASK_HCI_MAX_TXDMA << BIT_SHIFT_HCI_MAX_TXDMA) +#define BIT_CLEAR_HCI_MAX_TXDMA(x) ((x) & (~BITS_HCI_MAX_TXDMA)) +#define BIT_GET_HCI_MAX_TXDMA(x) \ + (((x) >> BIT_SHIFT_HCI_MAX_TXDMA) & BIT_MASK_HCI_MAX_TXDMA) +#define BIT_SET_HCI_MAX_TXDMA(x, v) \ + (BIT_CLEAR_HCI_MAX_TXDMA(x) | BIT_HCI_MAX_TXDMA(v)) -#define BIT_SHIFT_RXPKT_NUM_MATCH 16 -#define BIT_MASK_RXPKT_NUM_MATCH 0xf -#define BIT_RXPKT_NUM_MATCH(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH) << BIT_SHIFT_RXPKT_NUM_MATCH) -#define BIT_GET_RXPKT_NUM_MATCH(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH) & BIT_MASK_RXPKT_NUM_MATCH) +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MIGRATE_TIMER 0 -#define BIT_MASK_MIGRATE_TIMER 0xffff -#define BIT_MIGRATE_TIMER(x) (((x) & BIT_MASK_MIGRATE_TIMER) << BIT_SHIFT_MIGRATE_TIMER) -#define BIT_GET_MIGRATE_TIMER(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER) & BIT_MASK_MIGRATE_TIMER) +/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#define BIT_RD_LITT_EDN BIT(24) -/* 2 REG_BCNQ_TXBD_DESA (Offset 0x0308) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCNQ_TXBD_DESA 0 -#define BIT_MASK_BCNQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_BCNQ_TXBD_DESA(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA) << BIT_SHIFT_BCNQ_TXBD_DESA) -#define BIT_GET_BCNQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA) & BIT_MASK_BCNQ_TXBD_DESA) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_PWR_SCALE_START_PS BIT(23) -/* 2 REG_MGQ_TXBD_DESA (Offset 0x0310) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MGQ_TXBD_DESA 0 -#define BIT_MASK_MGQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_MGQ_TXBD_DESA(x) (((x) & BIT_MASK_MGQ_TXBD_DESA) << BIT_SHIFT_MGQ_TXBD_DESA) -#define BIT_GET_MGQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA) & BIT_MASK_MGQ_TXBD_DESA) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_PCIE_RST_TRXDMA_INTF BIT(20) -/* 2 REG_VOQ_TXBD_DESA (Offset 0x0318) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_VOQ_TXBD_DESA 0 -#define BIT_MASK_VOQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_VOQ_TXBD_DESA(x) (((x) & BIT_MASK_VOQ_TXBD_DESA) << BIT_SHIFT_VOQ_TXBD_DESA) -#define BIT_GET_VOQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA) & BIT_MASK_VOQ_TXBD_DESA) +/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_HCI_RST_TRXDMA_INTF BIT(20) -/* 2 REG_VIQ_TXBD_DESA (Offset 0x0320) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VIQ_TXBD_DESA 0 -#define BIT_MASK_VIQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_VIQ_TXBD_DESA(x) (((x) & BIT_MASK_VIQ_TXBD_DESA) << BIT_SHIFT_VIQ_TXBD_DESA) -#define BIT_GET_VIQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA) & BIT_MASK_VIQ_TXBD_DESA) +/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#define BIT_SHIFT_MAX_RXDMA 20 +#define BIT_MASK_MAX_RXDMA 0x7 +#define BIT_MAX_RXDMA(x) (((x) & BIT_MASK_MAX_RXDMA) << BIT_SHIFT_MAX_RXDMA) +#define BITS_MAX_RXDMA (BIT_MASK_MAX_RXDMA << BIT_SHIFT_MAX_RXDMA) +#define BIT_CLEAR_MAX_RXDMA(x) ((x) & (~BITS_MAX_RXDMA)) +#define BIT_GET_MAX_RXDMA(x) (((x) >> BIT_SHIFT_MAX_RXDMA) & BIT_MASK_MAX_RXDMA) +#define BIT_SET_MAX_RXDMA(x, v) (BIT_CLEAR_MAX_RXDMA(x) | BIT_MAX_RXDMA(v)) -/* 2 REG_BEQ_TXBD_DESA (Offset 0x0328) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BEQ_TXBD_DESA 0 -#define BIT_MASK_BEQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_BEQ_TXBD_DESA(x) (((x) & BIT_MASK_BEQ_TXBD_DESA) << BIT_SHIFT_BEQ_TXBD_DESA) -#define BIT_GET_BEQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA) & BIT_MASK_BEQ_TXBD_DESA) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_PCIE_EN_SWENT_L23 BIT(17) -/* 2 REG_BKQ_TXBD_DESA (Offset 0x0330) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_BKQ_TXBD_DESA 0 -#define BIT_MASK_BKQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_BKQ_TXBD_DESA(x) (((x) & BIT_MASK_BKQ_TXBD_DESA) << BIT_SHIFT_BKQ_TXBD_DESA) -#define BIT_GET_BKQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA) & BIT_MASK_BKQ_TXBD_DESA) +/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_HCI_EN_SWENT_L23 BIT(17) -/* 2 REG_RXQ_RXBD_DESA (Offset 0x0338) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXQ_RXBD_DESA 0 -#define BIT_MASK_RXQ_RXBD_DESA 0xffffffffffffffffL -#define BIT_RXQ_RXBD_DESA(x) (((x) & BIT_MASK_RXQ_RXBD_DESA) << BIT_SHIFT_RXQ_RXBD_DESA) -#define BIT_GET_RXQ_RXBD_DESA(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA) & BIT_MASK_RXQ_RXBD_DESA) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_PCIE_EN_HWEXT_L1 BIT(16) -/* 2 REG_HI0Q_TXBD_DESA (Offset 0x0340) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_HI0Q_TXBD_DESA 0 -#define BIT_MASK_HI0Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI0Q_TXBD_DESA(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA) << BIT_SHIFT_HI0Q_TXBD_DESA) -#define BIT_GET_HI0Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA) & BIT_MASK_HI0Q_TXBD_DESA) +/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_HCI_EN_HWEXT_L1 BIT(16) -/* 2 REG_HI1Q_TXBD_DESA (Offset 0x0348) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HI1Q_TXBD_DESA 0 -#define BIT_MASK_HI1Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI1Q_TXBD_DESA(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA) << BIT_SHIFT_HI1Q_TXBD_DESA) -#define BIT_GET_HI1Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA) & BIT_MASK_HI1Q_TXBD_DESA) +/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#define BIT_SHIFT_MAX_TXDMA 16 +#define BIT_MASK_MAX_TXDMA 0x7 +#define BIT_MAX_TXDMA(x) (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA) +#define BITS_MAX_TXDMA (BIT_MASK_MAX_TXDMA << BIT_SHIFT_MAX_TXDMA) +#define BIT_CLEAR_MAX_TXDMA(x) ((x) & (~BITS_MAX_TXDMA)) +#define BIT_GET_MAX_TXDMA(x) (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA) +#define BIT_SET_MAX_TXDMA(x, v) (BIT_CLEAR_MAX_TXDMA(x) | BIT_MAX_TXDMA(v)) -/* 2 REG_HI2Q_TXBD_DESA (Offset 0x0350) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HI2Q_TXBD_DESA 0 -#define BIT_MASK_HI2Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI2Q_TXBD_DESA(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA) << BIT_SHIFT_HI2Q_TXBD_DESA) -#define BIT_GET_HI2Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA) & BIT_MASK_HI2Q_TXBD_DESA) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_STOP_P0_MPRT_BCNQ4 BIT(6) +#define BIT_STOP_P0_MPRT_BCNQ3 BIT(4) +#define BIT_STOP_P0_MPRT_BCNQ2 BIT(2) +#define BIT_STOP_P0_MPRT_BCNQ1 BIT(0) -/* 2 REG_HI3Q_TXBD_DESA (Offset 0x0358) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HI3Q_TXBD_DESA 0 -#define BIT_MASK_HI3Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI3Q_TXBD_DESA(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA) << BIT_SHIFT_HI3Q_TXBD_DESA) -#define BIT_GET_HI3Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA) & BIT_MASK_HI3Q_TXBD_DESA) +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_TXTTIMER_MATCH_NUM 28 +#define BIT_MASK_TXTTIMER_MATCH_NUM 0xf +#define BIT_TXTTIMER_MATCH_NUM(x) \ + (((x) & BIT_MASK_TXTTIMER_MATCH_NUM) << BIT_SHIFT_TXTTIMER_MATCH_NUM) +#define BITS_TXTTIMER_MATCH_NUM \ + (BIT_MASK_TXTTIMER_MATCH_NUM << BIT_SHIFT_TXTTIMER_MATCH_NUM) +#define BIT_CLEAR_TXTTIMER_MATCH_NUM(x) ((x) & (~BITS_TXTTIMER_MATCH_NUM)) +#define BIT_GET_TXTTIMER_MATCH_NUM(x) \ + (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM) & BIT_MASK_TXTTIMER_MATCH_NUM) +#define BIT_SET_TXTTIMER_MATCH_NUM(x, v) \ + (BIT_CLEAR_TXTTIMER_MATCH_NUM(x) | BIT_TXTTIMER_MATCH_NUM(v)) -/* 2 REG_HI4Q_TXBD_DESA (Offset 0x0360) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HI4Q_TXBD_DESA 0 -#define BIT_MASK_HI4Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI4Q_TXBD_DESA(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA) << BIT_SHIFT_HI4Q_TXBD_DESA) -#define BIT_GET_HI4Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA) & BIT_MASK_HI4Q_TXBD_DESA) +/* 2 REG_ACH_CTRL (Offset 0x0304) */ +#define BIT_STOP_P0HIQ19 BIT(27) +#define BIT_STOP_P0HIQ18 BIT(26) +#define BIT_STOP_P0HIQ17 BIT(25) -/* 2 REG_HI5Q_TXBD_DESA (Offset 0x0368) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HI5Q_TXBD_DESA 0 -#define BIT_MASK_HI5Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI5Q_TXBD_DESA(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA) << BIT_SHIFT_HI5Q_TXBD_DESA) -#define BIT_GET_HI5Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA) & BIT_MASK_HI5Q_TXBD_DESA) +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_TXPKT_NUM_MATCH 24 +#define BIT_MASK_TXPKT_NUM_MATCH 0xf +#define BIT_TXPKT_NUM_MATCH(x) \ + (((x) & BIT_MASK_TXPKT_NUM_MATCH) << BIT_SHIFT_TXPKT_NUM_MATCH) +#define BITS_TXPKT_NUM_MATCH \ + (BIT_MASK_TXPKT_NUM_MATCH << BIT_SHIFT_TXPKT_NUM_MATCH) +#define BIT_CLEAR_TXPKT_NUM_MATCH(x) ((x) & (~BITS_TXPKT_NUM_MATCH)) +#define BIT_GET_TXPKT_NUM_MATCH(x) \ + (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH) & BIT_MASK_TXPKT_NUM_MATCH) +#define BIT_SET_TXPKT_NUM_MATCH(x, v) \ + (BIT_CLEAR_TXPKT_NUM_MATCH(x) | BIT_TXPKT_NUM_MATCH(v)) -/* 2 REG_HI6Q_TXBD_DESA (Offset 0x0370) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HI6Q_TXBD_DESA 0 -#define BIT_MASK_HI6Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI6Q_TXBD_DESA(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA) << BIT_SHIFT_HI6Q_TXBD_DESA) -#define BIT_GET_HI6Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA) & BIT_MASK_HI6Q_TXBD_DESA) +/* 2 REG_ACH_CTRL (Offset 0x0304) */ +#define BIT_STOP_P0HIQ16 BIT(24) -/* 2 REG_HI7Q_TXBD_DESA (Offset 0x0378) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HI7Q_TXBD_DESA 0 -#define BIT_MASK_HI7Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI7Q_TXBD_DESA(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA) << BIT_SHIFT_HI7Q_TXBD_DESA) -#define BIT_GET_HI7Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA) & BIT_MASK_HI7Q_TXBD_DESA) +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_TRXCOUNTER_MATCH 24 +#define BIT_MASK_TRXCOUNTER_MATCH 0xff +#define BIT_TRXCOUNTER_MATCH(x) \ + (((x) & BIT_MASK_TRXCOUNTER_MATCH) << BIT_SHIFT_TRXCOUNTER_MATCH) +#define BITS_TRXCOUNTER_MATCH \ + (BIT_MASK_TRXCOUNTER_MATCH << BIT_SHIFT_TRXCOUNTER_MATCH) +#define BIT_CLEAR_TRXCOUNTER_MATCH(x) ((x) & (~BITS_TRXCOUNTER_MATCH)) +#define BIT_GET_TRXCOUNTER_MATCH(x) \ + (((x) >> BIT_SHIFT_TRXCOUNTER_MATCH) & BIT_MASK_TRXCOUNTER_MATCH) +#define BIT_SET_TRXCOUNTER_MATCH(x, v) \ + (BIT_CLEAR_TRXCOUNTER_MATCH(x) | BIT_TRXCOUNTER_MATCH(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACH_CTRL (Offset 0x0304) */ - -/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ - -#define BIT_PCIE_MGQ_FLAG BIT(14) +#define BIT_RX_CLOSE_EN_V1 BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_RXTTIMER_MATCH_NUM 20 +#define BIT_MASK_RXTTIMER_MATCH_NUM 0xf +#define BIT_RXTTIMER_MATCH_NUM(x) \ + (((x) & BIT_MASK_RXTTIMER_MATCH_NUM) << BIT_SHIFT_RXTTIMER_MATCH_NUM) +#define BITS_RXTTIMER_MATCH_NUM \ + (BIT_MASK_RXTTIMER_MATCH_NUM << BIT_SHIFT_RXTTIMER_MATCH_NUM) +#define BIT_CLEAR_RXTTIMER_MATCH_NUM(x) ((x) & (~BITS_RXTTIMER_MATCH_NUM)) +#define BIT_GET_RXTTIMER_MATCH_NUM(x) \ + (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM) & BIT_MASK_RXTTIMER_MATCH_NUM) +#define BIT_SET_RXTTIMER_MATCH_NUM(x, v) \ + (BIT_CLEAR_RXTTIMER_MATCH_NUM(x) | BIT_RXTTIMER_MATCH_NUM(v)) -/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ +#endif -#define BIT_HCI_MGQ_FLAG BIT(14) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ACH_CTRL (Offset 0x0304) */ +#define BIT_STOP_FWCMDQ BIT(20) +#define BIT_STOP_P0BCNQ BIT(18) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_RXPKT_NUM_MATCH 16 +#define BIT_MASK_RXPKT_NUM_MATCH 0xf +#define BIT_RXPKT_NUM_MATCH(x) \ + (((x) & BIT_MASK_RXPKT_NUM_MATCH) << BIT_SHIFT_RXPKT_NUM_MATCH) +#define BITS_RXPKT_NUM_MATCH \ + (BIT_MASK_RXPKT_NUM_MATCH << BIT_SHIFT_RXPKT_NUM_MATCH) +#define BIT_CLEAR_RXPKT_NUM_MATCH(x) ((x) & (~BITS_RXPKT_NUM_MATCH)) +#define BIT_GET_RXPKT_NUM_MATCH(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH) & BIT_MASK_RXPKT_NUM_MATCH) +#define BIT_SET_RXPKT_NUM_MATCH(x, v) \ + (BIT_CLEAR_RXPKT_NUM_MATCH(x) | BIT_RXPKT_NUM_MATCH(v)) -#define BIT_SHIFT_MGQ_DESC_MODE 12 -#define BIT_MASK_MGQ_DESC_MODE 0x3 -#define BIT_MGQ_DESC_MODE(x) (((x) & BIT_MASK_MGQ_DESC_MODE) << BIT_SHIFT_MGQ_DESC_MODE) -#define BIT_GET_MGQ_DESC_MODE(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE) & BIT_MASK_MGQ_DESC_MODE) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_MGQ_DESC_NUM 0 -#define BIT_MASK_MGQ_DESC_NUM 0xfff -#define BIT_MGQ_DESC_NUM(x) (((x) & BIT_MASK_MGQ_DESC_NUM) << BIT_SHIFT_MGQ_DESC_NUM) -#define BIT_GET_MGQ_DESC_NUM(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM) & BIT_MASK_MGQ_DESC_NUM) +/* 2 REG_ACH_CTRL (Offset 0x0304) */ +#define BIT_STOP_P0MGQ BIT(16) -/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ +#endif -#define BIT_SYS_32_64 BIT(15) +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BCNQ_DESC_MODE 13 -#define BIT_MASK_BCNQ_DESC_MODE 0x3 -#define BIT_BCNQ_DESC_MODE(x) (((x) & BIT_MASK_BCNQ_DESC_MODE) << BIT_SHIFT_BCNQ_DESC_MODE) -#define BIT_GET_BCNQ_DESC_MODE(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE) & BIT_MASK_BCNQ_DESC_MODE) +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_TRXTIMER_MATCH 16 +#define BIT_MASK_TRXTIMER_MATCH 0xff +#define BIT_TRXTIMER_MATCH(x) \ + (((x) & BIT_MASK_TRXTIMER_MATCH) << BIT_SHIFT_TRXTIMER_MATCH) +#define BITS_TRXTIMER_MATCH \ + (BIT_MASK_TRXTIMER_MATCH << BIT_SHIFT_TRXTIMER_MATCH) +#define BIT_CLEAR_TRXTIMER_MATCH(x) ((x) & (~BITS_TRXTIMER_MATCH)) +#define BIT_GET_TRXTIMER_MATCH(x) \ + (((x) >> BIT_SHIFT_TRXTIMER_MATCH) & BIT_MASK_TRXTIMER_MATCH) +#define BIT_SET_TRXTIMER_MATCH(x, v) \ + (BIT_CLEAR_TRXTIMER_MATCH(x) | BIT_TRXTIMER_MATCH(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACH_CTRL (Offset 0x0304) */ +#define BIT_STOP_ACH13 BIT(15) +#define BIT_STOP_ACH12 BIT(14) +#define BIT_STOP_ACH11 BIT(13) +#define BIT_STOP_ACH10 BIT(12) +#define BIT_STOP_ACH9 BIT(11) +#define BIT_STOP_ACH8 BIT(10) +#define BIT_STOP_ACH7 BIT(9) +#define BIT_STOP_ACH6 BIT(8) +#define BIT_STOP_ACH5 BIT(7) +#define BIT_STOP_ACH4 BIT(6) +#define BIT_STOP_ACH3 BIT(5) +#define BIT_STOP_ACH2 BIT(4) +#define BIT_STOP_ACH1 BIT(3) +#define BIT_STOP_ACH0 BIT(2) -/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ +#endif -#define BIT_PCIE_BCNQ_FLAG BIT(12) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_MIGRATE_TIMER 0 +#define BIT_MASK_MIGRATE_TIMER 0xffff +#define BIT_MIGRATE_TIMER(x) \ + (((x) & BIT_MASK_MIGRATE_TIMER) << BIT_SHIFT_MIGRATE_TIMER) +#define BITS_MIGRATE_TIMER (BIT_MASK_MIGRATE_TIMER << BIT_SHIFT_MIGRATE_TIMER) +#define BIT_CLEAR_MIGRATE_TIMER(x) ((x) & (~BITS_MIGRATE_TIMER)) +#define BIT_GET_MIGRATE_TIMER(x) \ + (((x) >> BIT_SHIFT_MIGRATE_TIMER) & BIT_MASK_MIGRATE_TIMER) +#define BIT_SET_MIGRATE_TIMER(x, v) \ + (BIT_CLEAR_MIGRATE_TIMER(x) | BIT_MIGRATE_TIMER(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ +/* 2 REG_ACH_CTRL (Offset 0x0304) */ -#define BIT_HCI_BCNQ_FLAG BIT(12) +#define BIT_STOP_P0RX BIT(0) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_TRXTIMER_UNIT 0 +#define BIT_MASK_TRXTIMER_UNIT 0x3 +#define BIT_TRXTIMER_UNIT(x) \ + (((x) & BIT_MASK_TRXTIMER_UNIT) << BIT_SHIFT_TRXTIMER_UNIT) +#define BITS_TRXTIMER_UNIT (BIT_MASK_TRXTIMER_UNIT << BIT_SHIFT_TRXTIMER_UNIT) +#define BIT_CLEAR_TRXTIMER_UNIT(x) ((x) & (~BITS_TRXTIMER_UNIT)) +#define BIT_GET_TRXTIMER_UNIT(x) \ + (((x) >> BIT_SHIFT_TRXTIMER_UNIT) & BIT_MASK_TRXTIMER_UNIT) +#define BIT_SET_TRXTIMER_UNIT(x, v) \ + (BIT_CLEAR_TRXTIMER_UNIT(x) | BIT_TRXTIMER_UNIT(v)) -/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RXQ_DESC_NUM 0 -#define BIT_MASK_RXQ_DESC_NUM 0xfff -#define BIT_RXQ_DESC_NUM(x) (((x) & BIT_MASK_RXQ_DESC_NUM) << BIT_SHIFT_RXQ_DESC_NUM) -#define BIT_GET_RXQ_DESC_NUM(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM) & BIT_MASK_RXQ_DESC_NUM) +/* 2 REG_HIQ_CTRL (Offset 0x0308) */ +#define BIT_STOP_P0HIQ15 BIT(15) +#define BIT_STOP_P0HIQ14 BIT(14) +#define BIT_STOP_P0HIQ13 BIT(13) +#define BIT_STOP_P0HIQ12 BIT(12) +#define BIT_STOP_P0HIQ11 BIT(11) +#define BIT_STOP_P0HIQ10 BIT(10) +#define BIT_STOP_P0HIQ9 BIT(9) +#define BIT_STOP_P0HIQ8 BIT(8) +#define BIT_STOP_P0HIQ7 BIT(7) +#define BIT_STOP_P0HIQ6 BIT(6) +#define BIT_STOP_P0HIQ5 BIT(5) +#define BIT_STOP_P0HIQ4 BIT(4) +#define BIT_STOP_P0HIQ3 BIT(3) +#define BIT_STOP_P0HIQ2 BIT(2) +#define BIT_STOP_P0HIQ1 BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCNQ_TXBD_DESA (Offset 0x0308) */ +#define BIT_SHIFT_BCNQ_TXBD_DESA 0 +#define BIT_MASK_BCNQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_BCNQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_BCNQ_TXBD_DESA) << BIT_SHIFT_BCNQ_TXBD_DESA) +#define BITS_BCNQ_TXBD_DESA \ + (BIT_MASK_BCNQ_TXBD_DESA << BIT_SHIFT_BCNQ_TXBD_DESA) +#define BIT_CLEAR_BCNQ_TXBD_DESA(x) ((x) & (~BITS_BCNQ_TXBD_DESA)) +#define BIT_GET_BCNQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA) & BIT_MASK_BCNQ_TXBD_DESA) +#define BIT_SET_BCNQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_BCNQ_TXBD_DESA(x) | BIT_BCNQ_TXBD_DESA(v)) -/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ +#endif -#define BIT_PCIE_VOQ_FLAG BIT(14) +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIQ_CTRL (Offset 0x0308) */ + +#define BIT_STOP_P0HIQ0 BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_MGQ_TXBD_DESA (Offset 0x0310) */ +#define BIT_SHIFT_MGQ_TXBD_DESA 0 +#define BIT_MASK_MGQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_MGQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_MGQ_TXBD_DESA) << BIT_SHIFT_MGQ_TXBD_DESA) +#define BITS_MGQ_TXBD_DESA (BIT_MASK_MGQ_TXBD_DESA << BIT_SHIFT_MGQ_TXBD_DESA) +#define BIT_CLEAR_MGQ_TXBD_DESA(x) ((x) & (~BITS_MGQ_TXBD_DESA)) +#define BIT_GET_MGQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_MGQ_TXBD_DESA) & BIT_MASK_MGQ_TXBD_DESA) +#define BIT_SET_MGQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_MGQ_TXBD_DESA(x) | BIT_MGQ_TXBD_DESA(v)) -/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ +/* 2 REG_VOQ_TXBD_DESA (Offset 0x0318) */ -#define BIT_HCI_VOQ_FLAG BIT(14) +#define BIT_SHIFT_VOQ_TXBD_DESA 0 +#define BIT_MASK_VOQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_VOQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_VOQ_TXBD_DESA) << BIT_SHIFT_VOQ_TXBD_DESA) +#define BITS_VOQ_TXBD_DESA (BIT_MASK_VOQ_TXBD_DESA << BIT_SHIFT_VOQ_TXBD_DESA) +#define BIT_CLEAR_VOQ_TXBD_DESA(x) ((x) & (~BITS_VOQ_TXBD_DESA)) +#define BIT_GET_VOQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_VOQ_TXBD_DESA) & BIT_MASK_VOQ_TXBD_DESA) +#define BIT_SET_VOQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_VOQ_TXBD_DESA(x) | BIT_VOQ_TXBD_DESA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACH0_TXBD_DESA_L (Offset 0x0318) */ +#define BIT_SHIFT_ACH0_TXBD_DESA_L 0 +#define BIT_MASK_ACH0_TXBD_DESA_L 0xffffffffL +#define BIT_ACH0_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH0_TXBD_DESA_L) << BIT_SHIFT_ACH0_TXBD_DESA_L) +#define BITS_ACH0_TXBD_DESA_L \ + (BIT_MASK_ACH0_TXBD_DESA_L << BIT_SHIFT_ACH0_TXBD_DESA_L) +#define BIT_CLEAR_ACH0_TXBD_DESA_L(x) ((x) & (~BITS_ACH0_TXBD_DESA_L)) +#define BIT_GET_ACH0_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_L) & BIT_MASK_ACH0_TXBD_DESA_L) +#define BIT_SET_ACH0_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH0_TXBD_DESA_L(x) | BIT_ACH0_TXBD_DESA_L(v)) -/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ +/* 2 REG_ACH0_TXBD_DESA_H (Offset 0x031C) */ +#define BIT_SHIFT_ACH0_TXBD_DESA_H 0 +#define BIT_MASK_ACH0_TXBD_DESA_H 0xffffffffL +#define BIT_ACH0_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH0_TXBD_DESA_H) << BIT_SHIFT_ACH0_TXBD_DESA_H) +#define BITS_ACH0_TXBD_DESA_H \ + (BIT_MASK_ACH0_TXBD_DESA_H << BIT_SHIFT_ACH0_TXBD_DESA_H) +#define BIT_CLEAR_ACH0_TXBD_DESA_H(x) ((x) & (~BITS_ACH0_TXBD_DESA_H)) +#define BIT_GET_ACH0_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_H) & BIT_MASK_ACH0_TXBD_DESA_H) +#define BIT_SET_ACH0_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH0_TXBD_DESA_H(x) | BIT_ACH0_TXBD_DESA_H(v)) -#define BIT_SHIFT_VOQ_DESC_MODE 12 -#define BIT_MASK_VOQ_DESC_MODE 0x3 -#define BIT_VOQ_DESC_MODE(x) (((x) & BIT_MASK_VOQ_DESC_MODE) << BIT_SHIFT_VOQ_DESC_MODE) -#define BIT_GET_VOQ_DESC_MODE(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE) & BIT_MASK_VOQ_DESC_MODE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VOQ_DESC_NUM 0 -#define BIT_MASK_VOQ_DESC_NUM 0xfff -#define BIT_VOQ_DESC_NUM(x) (((x) & BIT_MASK_VOQ_DESC_NUM) << BIT_SHIFT_VOQ_DESC_NUM) -#define BIT_GET_VOQ_DESC_NUM(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM) & BIT_MASK_VOQ_DESC_NUM) +/* 2 REG_VIQ_TXBD_DESA (Offset 0x0320) */ +#define BIT_SHIFT_VIQ_TXBD_DESA 0 +#define BIT_MASK_VIQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_VIQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_VIQ_TXBD_DESA) << BIT_SHIFT_VIQ_TXBD_DESA) +#define BITS_VIQ_TXBD_DESA (BIT_MASK_VIQ_TXBD_DESA << BIT_SHIFT_VIQ_TXBD_DESA) +#define BIT_CLEAR_VIQ_TXBD_DESA(x) ((x) & (~BITS_VIQ_TXBD_DESA)) +#define BIT_GET_VIQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_VIQ_TXBD_DESA) & BIT_MASK_VIQ_TXBD_DESA) +#define BIT_SET_VIQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_VIQ_TXBD_DESA(x) | BIT_VIQ_TXBD_DESA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACH1_TXBD_DESA_L (Offset 0x0320) */ +#define BIT_SHIFT_ACH1_TXBD_DESA_L 0 +#define BIT_MASK_ACH1_TXBD_DESA_L 0xffffffffL +#define BIT_ACH1_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH1_TXBD_DESA_L) << BIT_SHIFT_ACH1_TXBD_DESA_L) +#define BITS_ACH1_TXBD_DESA_L \ + (BIT_MASK_ACH1_TXBD_DESA_L << BIT_SHIFT_ACH1_TXBD_DESA_L) +#define BIT_CLEAR_ACH1_TXBD_DESA_L(x) ((x) & (~BITS_ACH1_TXBD_DESA_L)) +#define BIT_GET_ACH1_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_L) & BIT_MASK_ACH1_TXBD_DESA_L) +#define BIT_SET_ACH1_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH1_TXBD_DESA_L(x) | BIT_ACH1_TXBD_DESA_L(v)) -/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ +/* 2 REG_ACH1_TXBD_DESA_H (Offset 0x0324) */ -#define BIT_PCIE_VIQ_FLAG BIT(14) +#define BIT_SHIFT_ACH1_TXBD_DESA_H 0 +#define BIT_MASK_ACH1_TXBD_DESA_H 0xffffffffL +#define BIT_ACH1_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH1_TXBD_DESA_H) << BIT_SHIFT_ACH1_TXBD_DESA_H) +#define BITS_ACH1_TXBD_DESA_H \ + (BIT_MASK_ACH1_TXBD_DESA_H << BIT_SHIFT_ACH1_TXBD_DESA_H) +#define BIT_CLEAR_ACH1_TXBD_DESA_H(x) ((x) & (~BITS_ACH1_TXBD_DESA_H)) +#define BIT_GET_ACH1_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_H) & BIT_MASK_ACH1_TXBD_DESA_H) +#define BIT_SET_ACH1_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH1_TXBD_DESA_H(x) | BIT_ACH1_TXBD_DESA_H(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ +/* 2 REG_BEQ_TXBD_DESA (Offset 0x0328) */ -#define BIT_HCI_VIQ_FLAG BIT(14) +#define BIT_SHIFT_BEQ_TXBD_DESA 0 +#define BIT_MASK_BEQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_BEQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_BEQ_TXBD_DESA) << BIT_SHIFT_BEQ_TXBD_DESA) +#define BITS_BEQ_TXBD_DESA (BIT_MASK_BEQ_TXBD_DESA << BIT_SHIFT_BEQ_TXBD_DESA) +#define BIT_CLEAR_BEQ_TXBD_DESA(x) ((x) & (~BITS_BEQ_TXBD_DESA)) +#define BIT_GET_BEQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_BEQ_TXBD_DESA) & BIT_MASK_BEQ_TXBD_DESA) +#define BIT_SET_BEQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_BEQ_TXBD_DESA(x) | BIT_BEQ_TXBD_DESA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACH2_TXBD_DESA_L (Offset 0x0328) */ +#define BIT_SHIFT_ACH2_TXBD_DESA_L 0 +#define BIT_MASK_ACH2_TXBD_DESA_L 0xffffffffL +#define BIT_ACH2_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH2_TXBD_DESA_L) << BIT_SHIFT_ACH2_TXBD_DESA_L) +#define BITS_ACH2_TXBD_DESA_L \ + (BIT_MASK_ACH2_TXBD_DESA_L << BIT_SHIFT_ACH2_TXBD_DESA_L) +#define BIT_CLEAR_ACH2_TXBD_DESA_L(x) ((x) & (~BITS_ACH2_TXBD_DESA_L)) +#define BIT_GET_ACH2_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_L) & BIT_MASK_ACH2_TXBD_DESA_L) +#define BIT_SET_ACH2_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH2_TXBD_DESA_L(x) | BIT_ACH2_TXBD_DESA_L(v)) -/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ +/* 2 REG_ACH2_TXBD_DESA_H (Offset 0x032C) */ +#define BIT_SHIFT_ACH2_TXBD_DESA_H 0 +#define BIT_MASK_ACH2_TXBD_DESA_H 0xffffffffL +#define BIT_ACH2_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH2_TXBD_DESA_H) << BIT_SHIFT_ACH2_TXBD_DESA_H) +#define BITS_ACH2_TXBD_DESA_H \ + (BIT_MASK_ACH2_TXBD_DESA_H << BIT_SHIFT_ACH2_TXBD_DESA_H) +#define BIT_CLEAR_ACH2_TXBD_DESA_H(x) ((x) & (~BITS_ACH2_TXBD_DESA_H)) +#define BIT_GET_ACH2_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_H) & BIT_MASK_ACH2_TXBD_DESA_H) +#define BIT_SET_ACH2_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH2_TXBD_DESA_H(x) | BIT_ACH2_TXBD_DESA_H(v)) -#define BIT_SHIFT_VIQ_DESC_MODE 12 -#define BIT_MASK_VIQ_DESC_MODE 0x3 -#define BIT_VIQ_DESC_MODE(x) (((x) & BIT_MASK_VIQ_DESC_MODE) << BIT_SHIFT_VIQ_DESC_MODE) -#define BIT_GET_VIQ_DESC_MODE(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE) & BIT_MASK_VIQ_DESC_MODE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VIQ_DESC_NUM 0 -#define BIT_MASK_VIQ_DESC_NUM 0xfff -#define BIT_VIQ_DESC_NUM(x) (((x) & BIT_MASK_VIQ_DESC_NUM) << BIT_SHIFT_VIQ_DESC_NUM) -#define BIT_GET_VIQ_DESC_NUM(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM) & BIT_MASK_VIQ_DESC_NUM) +/* 2 REG_BKQ_TXBD_DESA (Offset 0x0330) */ +#define BIT_SHIFT_BKQ_TXBD_DESA 0 +#define BIT_MASK_BKQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_BKQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_BKQ_TXBD_DESA) << BIT_SHIFT_BKQ_TXBD_DESA) +#define BITS_BKQ_TXBD_DESA (BIT_MASK_BKQ_TXBD_DESA << BIT_SHIFT_BKQ_TXBD_DESA) +#define BIT_CLEAR_BKQ_TXBD_DESA(x) ((x) & (~BITS_BKQ_TXBD_DESA)) +#define BIT_GET_BKQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_BKQ_TXBD_DESA) & BIT_MASK_BKQ_TXBD_DESA) +#define BIT_SET_BKQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_BKQ_TXBD_DESA(x) | BIT_BKQ_TXBD_DESA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACH3_TXBD_DESA_L (Offset 0x0330) */ +#define BIT_SHIFT_ACH3_TXBD_DESA_L 0 +#define BIT_MASK_ACH3_TXBD_DESA_L 0xffffffffL +#define BIT_ACH3_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH3_TXBD_DESA_L) << BIT_SHIFT_ACH3_TXBD_DESA_L) +#define BITS_ACH3_TXBD_DESA_L \ + (BIT_MASK_ACH3_TXBD_DESA_L << BIT_SHIFT_ACH3_TXBD_DESA_L) +#define BIT_CLEAR_ACH3_TXBD_DESA_L(x) ((x) & (~BITS_ACH3_TXBD_DESA_L)) +#define BIT_GET_ACH3_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_L) & BIT_MASK_ACH3_TXBD_DESA_L) +#define BIT_SET_ACH3_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH3_TXBD_DESA_L(x) | BIT_ACH3_TXBD_DESA_L(v)) -/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ +/* 2 REG_ACH3_TXBD_DESA_H (Offset 0x0334) */ -#define BIT_PCIE_BEQ_FLAG BIT(14) +#define BIT_SHIFT_ACH3_TXBD_DESA_H 0 +#define BIT_MASK_ACH3_TXBD_DESA_H 0xffffffffL +#define BIT_ACH3_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH3_TXBD_DESA_H) << BIT_SHIFT_ACH3_TXBD_DESA_H) +#define BITS_ACH3_TXBD_DESA_H \ + (BIT_MASK_ACH3_TXBD_DESA_H << BIT_SHIFT_ACH3_TXBD_DESA_H) +#define BIT_CLEAR_ACH3_TXBD_DESA_H(x) ((x) & (~BITS_ACH3_TXBD_DESA_H)) +#define BIT_GET_ACH3_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_H) & BIT_MASK_ACH3_TXBD_DESA_H) +#define BIT_SET_ACH3_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH3_TXBD_DESA_H(x) | BIT_ACH3_TXBD_DESA_H(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ +/* 2 REG_RXQ_RXBD_DESA (Offset 0x0338) */ -#define BIT_HCI_BEQ_FLAG BIT(14) +#define BIT_SHIFT_RXQ_RXBD_DESA 0 +#define BIT_MASK_RXQ_RXBD_DESA 0xffffffffffffffffL +#define BIT_RXQ_RXBD_DESA(x) \ + (((x) & BIT_MASK_RXQ_RXBD_DESA) << BIT_SHIFT_RXQ_RXBD_DESA) +#define BITS_RXQ_RXBD_DESA (BIT_MASK_RXQ_RXBD_DESA << BIT_SHIFT_RXQ_RXBD_DESA) +#define BIT_CLEAR_RXQ_RXBD_DESA(x) ((x) & (~BITS_RXQ_RXBD_DESA)) +#define BIT_GET_RXQ_RXBD_DESA(x) \ + (((x) >> BIT_SHIFT_RXQ_RXBD_DESA) & BIT_MASK_RXQ_RXBD_DESA) +#define BIT_SET_RXQ_RXBD_DESA(x, v) \ + (BIT_CLEAR_RXQ_RXBD_DESA(x) | BIT_RXQ_RXBD_DESA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P0RXQ_RXBD_DESA_L (Offset 0x0338) */ +#define BIT_SHIFT_P0RXQ_RXBD_DESA_L 0 +#define BIT_MASK_P0RXQ_RXBD_DESA_L 0xffffffffL +#define BIT_P0RXQ_RXBD_DESA_L(x) \ + (((x) & BIT_MASK_P0RXQ_RXBD_DESA_L) << BIT_SHIFT_P0RXQ_RXBD_DESA_L) +#define BITS_P0RXQ_RXBD_DESA_L \ + (BIT_MASK_P0RXQ_RXBD_DESA_L << BIT_SHIFT_P0RXQ_RXBD_DESA_L) +#define BIT_CLEAR_P0RXQ_RXBD_DESA_L(x) ((x) & (~BITS_P0RXQ_RXBD_DESA_L)) +#define BIT_GET_P0RXQ_RXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_L) & BIT_MASK_P0RXQ_RXBD_DESA_L) +#define BIT_SET_P0RXQ_RXBD_DESA_L(x, v) \ + (BIT_CLEAR_P0RXQ_RXBD_DESA_L(x) | BIT_P0RXQ_RXBD_DESA_L(v)) -/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ +/* 2 REG_P0RXQ_RXBD_DESA_H (Offset 0x033C) */ +#define BIT_SHIFT_P0RXQ_RXBD_DESA_H 0 +#define BIT_MASK_P0RXQ_RXBD_DESA_H 0xffffffffL +#define BIT_P0RXQ_RXBD_DESA_H(x) \ + (((x) & BIT_MASK_P0RXQ_RXBD_DESA_H) << BIT_SHIFT_P0RXQ_RXBD_DESA_H) +#define BITS_P0RXQ_RXBD_DESA_H \ + (BIT_MASK_P0RXQ_RXBD_DESA_H << BIT_SHIFT_P0RXQ_RXBD_DESA_H) +#define BIT_CLEAR_P0RXQ_RXBD_DESA_H(x) ((x) & (~BITS_P0RXQ_RXBD_DESA_H)) +#define BIT_GET_P0RXQ_RXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_H) & BIT_MASK_P0RXQ_RXBD_DESA_H) +#define BIT_SET_P0RXQ_RXBD_DESA_H(x, v) \ + (BIT_CLEAR_P0RXQ_RXBD_DESA_H(x) | BIT_P0RXQ_RXBD_DESA_H(v)) -#define BIT_SHIFT_BEQ_DESC_MODE 12 -#define BIT_MASK_BEQ_DESC_MODE 0x3 -#define BIT_BEQ_DESC_MODE(x) (((x) & BIT_MASK_BEQ_DESC_MODE) << BIT_SHIFT_BEQ_DESC_MODE) -#define BIT_GET_BEQ_DESC_MODE(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE) & BIT_MASK_BEQ_DESC_MODE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BEQ_DESC_NUM 0 -#define BIT_MASK_BEQ_DESC_NUM 0xfff -#define BIT_BEQ_DESC_NUM(x) (((x) & BIT_MASK_BEQ_DESC_NUM) << BIT_SHIFT_BEQ_DESC_NUM) -#define BIT_GET_BEQ_DESC_NUM(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM) & BIT_MASK_BEQ_DESC_NUM) +/* 2 REG_HI0Q_TXBD_DESA (Offset 0x0340) */ +#define BIT_SHIFT_HI0Q_TXBD_DESA 0 +#define BIT_MASK_HI0Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI0Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA) << BIT_SHIFT_HI0Q_TXBD_DESA) +#define BITS_HI0Q_TXBD_DESA \ + (BIT_MASK_HI0Q_TXBD_DESA << BIT_SHIFT_HI0Q_TXBD_DESA) +#define BIT_CLEAR_HI0Q_TXBD_DESA(x) ((x) & (~BITS_HI0Q_TXBD_DESA)) +#define BIT_GET_HI0Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA) & BIT_MASK_HI0Q_TXBD_DESA) +#define BIT_SET_HI0Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA(x) | BIT_HI0Q_TXBD_DESA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P0BCNQ_TXBD_DESA_L (Offset 0x0340) */ +#define BIT_SHIFT_P0BCNQ_TXBD_DESA_L 0 +#define BIT_MASK_P0BCNQ_TXBD_DESA_L 0xffffffffL +#define BIT_P0BCNQ_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_L) << BIT_SHIFT_P0BCNQ_TXBD_DESA_L) +#define BITS_P0BCNQ_TXBD_DESA_L \ + (BIT_MASK_P0BCNQ_TXBD_DESA_L << BIT_SHIFT_P0BCNQ_TXBD_DESA_L) +#define BIT_CLEAR_P0BCNQ_TXBD_DESA_L(x) ((x) & (~BITS_P0BCNQ_TXBD_DESA_L)) +#define BIT_GET_P0BCNQ_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_L) & BIT_MASK_P0BCNQ_TXBD_DESA_L) +#define BIT_SET_P0BCNQ_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_P0BCNQ_TXBD_DESA_L(x) | BIT_P0BCNQ_TXBD_DESA_L(v)) -/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ +/* 2 REG_P0BCNQ_TXBD_DESA_H (Offset 0x0344) */ -#define BIT_PCIE_BKQ_FLAG BIT(14) +#define BIT_SHIFT_P0BCNQ_TXBD_DESA_H 0 +#define BIT_MASK_P0BCNQ_TXBD_DESA_H 0xffffffffL +#define BIT_P0BCNQ_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_H) << BIT_SHIFT_P0BCNQ_TXBD_DESA_H) +#define BITS_P0BCNQ_TXBD_DESA_H \ + (BIT_MASK_P0BCNQ_TXBD_DESA_H << BIT_SHIFT_P0BCNQ_TXBD_DESA_H) +#define BIT_CLEAR_P0BCNQ_TXBD_DESA_H(x) ((x) & (~BITS_P0BCNQ_TXBD_DESA_H)) +#define BIT_GET_P0BCNQ_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_H) & BIT_MASK_P0BCNQ_TXBD_DESA_H) +#define BIT_SET_P0BCNQ_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_P0BCNQ_TXBD_DESA_H(x) | BIT_P0BCNQ_TXBD_DESA_H(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HI1Q_TXBD_DESA (Offset 0x0348) */ +#define BIT_SHIFT_HI1Q_TXBD_DESA 0 +#define BIT_MASK_HI1Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI1Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA) << BIT_SHIFT_HI1Q_TXBD_DESA) +#define BITS_HI1Q_TXBD_DESA \ + (BIT_MASK_HI1Q_TXBD_DESA << BIT_SHIFT_HI1Q_TXBD_DESA) +#define BIT_CLEAR_HI1Q_TXBD_DESA(x) ((x) & (~BITS_HI1Q_TXBD_DESA)) +#define BIT_GET_HI1Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA) & BIT_MASK_HI1Q_TXBD_DESA) +#define BIT_SET_HI1Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA(x) | BIT_HI1Q_TXBD_DESA(v)) -/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ +#endif -#define BIT_HCI_BKQ_FLAG BIT(14) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_FWCMDQ_TXBD_DESA_L (Offset 0x0348) */ +#define BIT_SHIFT_FWCMDQ_TXBD_DESA_L 0 +#define BIT_MASK_FWCMDQ_TXBD_DESA_L 0xffffffffL +#define BIT_FWCMDQ_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_L) << BIT_SHIFT_FWCMDQ_TXBD_DESA_L) +#define BITS_FWCMDQ_TXBD_DESA_L \ + (BIT_MASK_FWCMDQ_TXBD_DESA_L << BIT_SHIFT_FWCMDQ_TXBD_DESA_L) +#define BIT_CLEAR_FWCMDQ_TXBD_DESA_L(x) ((x) & (~BITS_FWCMDQ_TXBD_DESA_L)) +#define BIT_GET_FWCMDQ_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_L) & BIT_MASK_FWCMDQ_TXBD_DESA_L) +#define BIT_SET_FWCMDQ_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_FWCMDQ_TXBD_DESA_L(x) | BIT_FWCMDQ_TXBD_DESA_L(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWCMDQ_TXBD_DESA_H (Offset 0x034C) */ +#define BIT_SHIFT_FWCMDQ_TXBD_DESA_H 0 +#define BIT_MASK_FWCMDQ_TXBD_DESA_H 0xffffffffL +#define BIT_FWCMDQ_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_H) << BIT_SHIFT_FWCMDQ_TXBD_DESA_H) +#define BITS_FWCMDQ_TXBD_DESA_H \ + (BIT_MASK_FWCMDQ_TXBD_DESA_H << BIT_SHIFT_FWCMDQ_TXBD_DESA_H) +#define BIT_CLEAR_FWCMDQ_TXBD_DESA_H(x) ((x) & (~BITS_FWCMDQ_TXBD_DESA_H)) +#define BIT_GET_FWCMDQ_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_H) & BIT_MASK_FWCMDQ_TXBD_DESA_H) +#define BIT_SET_FWCMDQ_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_FWCMDQ_TXBD_DESA_H(x) | BIT_FWCMDQ_TXBD_DESA_H(v)) -/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HI2Q_TXBD_DESA (Offset 0x0350) */ -#define BIT_SHIFT_BKQ_DESC_MODE 12 -#define BIT_MASK_BKQ_DESC_MODE 0x3 -#define BIT_BKQ_DESC_MODE(x) (((x) & BIT_MASK_BKQ_DESC_MODE) << BIT_SHIFT_BKQ_DESC_MODE) -#define BIT_GET_BKQ_DESC_MODE(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE) & BIT_MASK_BKQ_DESC_MODE) +#define BIT_SHIFT_HI2Q_TXBD_DESA 0 +#define BIT_MASK_HI2Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI2Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA) << BIT_SHIFT_HI2Q_TXBD_DESA) +#define BITS_HI2Q_TXBD_DESA \ + (BIT_MASK_HI2Q_TXBD_DESA << BIT_SHIFT_HI2Q_TXBD_DESA) +#define BIT_CLEAR_HI2Q_TXBD_DESA(x) ((x) & (~BITS_HI2Q_TXBD_DESA)) +#define BIT_GET_HI2Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA) & BIT_MASK_HI2Q_TXBD_DESA) +#define BIT_SET_HI2Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA(x) | BIT_HI2Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_PCIE_HRPWM1_HCPWM1_DCPU (Offset 0x0354) */ + +#define BIT_SHIFT_PCIE_HCPWM1_DCPU 16 +#define BIT_MASK_PCIE_HCPWM1_DCPU 0xff +#define BIT_PCIE_HCPWM1_DCPU(x) \ + (((x) & BIT_MASK_PCIE_HCPWM1_DCPU) << BIT_SHIFT_PCIE_HCPWM1_DCPU) +#define BITS_PCIE_HCPWM1_DCPU \ + (BIT_MASK_PCIE_HCPWM1_DCPU << BIT_SHIFT_PCIE_HCPWM1_DCPU) +#define BIT_CLEAR_PCIE_HCPWM1_DCPU(x) ((x) & (~BITS_PCIE_HCPWM1_DCPU)) +#define BIT_GET_PCIE_HCPWM1_DCPU(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM1_DCPU) & BIT_MASK_PCIE_HCPWM1_DCPU) +#define BIT_SET_PCIE_HCPWM1_DCPU(x, v) \ + (BIT_CLEAR_PCIE_HCPWM1_DCPU(x) | BIT_PCIE_HCPWM1_DCPU(v)) + +#define BIT_SHIFT_PCIE_HRPWM1_DCPU 8 +#define BIT_MASK_PCIE_HRPWM1_DCPU 0xff +#define BIT_PCIE_HRPWM1_DCPU(x) \ + (((x) & BIT_MASK_PCIE_HRPWM1_DCPU) << BIT_SHIFT_PCIE_HRPWM1_DCPU) +#define BITS_PCIE_HRPWM1_DCPU \ + (BIT_MASK_PCIE_HRPWM1_DCPU << BIT_SHIFT_PCIE_HRPWM1_DCPU) +#define BIT_CLEAR_PCIE_HRPWM1_DCPU(x) ((x) & (~BITS_PCIE_HRPWM1_DCPU)) +#define BIT_GET_PCIE_HRPWM1_DCPU(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM1_DCPU) & BIT_MASK_PCIE_HRPWM1_DCPU) +#define BIT_SET_PCIE_HRPWM1_DCPU(x, v) \ + (BIT_CLEAR_PCIE_HRPWM1_DCPU(x) | BIT_PCIE_HRPWM1_DCPU(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HI3Q_TXBD_DESA (Offset 0x0358) */ -#define BIT_SHIFT_BKQ_DESC_NUM 0 -#define BIT_MASK_BKQ_DESC_NUM 0xfff -#define BIT_BKQ_DESC_NUM(x) (((x) & BIT_MASK_BKQ_DESC_NUM) << BIT_SHIFT_BKQ_DESC_NUM) -#define BIT_GET_BKQ_DESC_NUM(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM) & BIT_MASK_BKQ_DESC_NUM) +#define BIT_SHIFT_HI3Q_TXBD_DESA 0 +#define BIT_MASK_HI3Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI3Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA) << BIT_SHIFT_HI3Q_TXBD_DESA) +#define BITS_HI3Q_TXBD_DESA \ + (BIT_MASK_HI3Q_TXBD_DESA << BIT_SHIFT_HI3Q_TXBD_DESA) +#define BIT_CLEAR_HI3Q_TXBD_DESA(x) ((x) & (~BITS_HI3Q_TXBD_DESA)) +#define BIT_GET_HI3Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA) & BIT_MASK_HI3Q_TXBD_DESA) +#define BIT_SET_HI3Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA(x) | BIT_HI3Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_L (Offset 0x0358) */ + +#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L 0 +#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L 0xffffffffL +#define BIT_P0_MPRT_BCNQ_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L) \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L) +#define BITS_P0_MPRT_BCNQ_TXBD_DESA_L \ + (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L) +#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L(x) \ + ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_L)) +#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L) & \ + BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L) +#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L(x) | \ + BIT_P0_MPRT_BCNQ_TXBD_DESA_L(v)) + +/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_H (Offset 0x035C) */ + +#define BIT_CLR_P0HI15Q_HW_IDX BIT(29) +#define BIT_CLR_P0HI14Q_HW_IDX BIT(28) +#define BIT_CLR_P0HI13Q_HW_IDX BIT(27) +#define BIT_CLR_P0HI12Q_HW_IDX BIT(26) +#define BIT_CLR_P0HI11Q_HW_IDX BIT(25) +#define BIT_CLR_P0HI10Q_HW_IDX BIT(24) +#define BIT_CLR_P0HI9Q_HW_IDX BIT(23) +#define BIT_CLR_P0HI8Q_HW_IDX BIT(22) +#define BIT_CLR_ACH7_HW_IDX BIT(21) +#define BIT_CLR_ACH13_HW_IDX BIT(21) +#define BIT_CLR_ACH6_HW_IDX BIT(20) +#define BIT_CLR_ACH12_HW_IDX BIT(20) +#define BIT_CLR_ACH5_HW_IDX BIT(19) +#define BIT_CLR_ACH11_HW_IDX BIT(19) +#define BIT_CLR_ACH4_HW_IDX BIT(18) +#define BIT_CLR_ACH10_HW_IDX BIT(18) +#define BIT_CLR_ACH9_HW_IDX BIT(17) +#define BIT_CLR_ACH8_HW_IDX BIT(16) + +#define BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE 13 +#define BIT_MASK_P0_MPRT_BCNQ_DESC_MODE 0x3 +#define BIT_P0_MPRT_BCNQ_DESC_MODE(x) \ + (((x) & BIT_MASK_P0_MPRT_BCNQ_DESC_MODE) \ + << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE) +#define BITS_P0_MPRT_BCNQ_DESC_MODE \ + (BIT_MASK_P0_MPRT_BCNQ_DESC_MODE << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE) +#define BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE(x) \ + ((x) & (~BITS_P0_MPRT_BCNQ_DESC_MODE)) +#define BIT_GET_P0_MPRT_BCNQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE) & \ + BIT_MASK_P0_MPRT_BCNQ_DESC_MODE) +#define BIT_SET_P0_MPRT_BCNQ_DESC_MODE(x, v) \ + (BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE(x) | BIT_P0_MPRT_BCNQ_DESC_MODE(v)) + +#define BIT_CLR_P0HI15Q_HOST_IDX BIT(13) +#define BIT_CLR_P0HI14Q_HOST_IDX BIT(12) +#define BIT_PCIE_P0MPRT_BCNQ4_FLAG BIT(11) +#define BIT_CLR_P0HI13Q_HOST_IDX BIT(11) +#define BIT_PCIE_P0MPRT_BCNQ3_FLAG BIT(10) +#define BIT_CLR_P0HI12Q_HOST_IDX BIT(10) +#define BIT_PCIE_P0MPRT_BCNQ2_FLAG BIT(9) +#define BIT_CLR_P0HI11Q_HOST_IDX BIT(9) +#define BIT_PCIE_P0MPRT_BCNQ1_FLAG BIT(8) +#define BIT_CLR_P0HI10Q_HOST_IDX BIT(8) +#define BIT_CLR_P0HI9Q_HOST_IDX BIT(7) +#define BIT_CLR_P0HI8Q_HOST_IDX BIT(6) +#define BIT_CLR_ACH7_HOST_IDX BIT(5) +#define BIT_CLR_ACH13_HOST_IDX BIT(5) +#define BIT_CLR_ACH6_HOST_IDX BIT(4) +#define BIT_CLR_ACH12_HOST_IDX BIT(4) +#define BIT_CLR_ACH5_HOST_IDX BIT(3) +#define BIT_CLR_ACH11_HOST_IDX BIT(3) +#define BIT_CLR_ACH4_HOST_IDX BIT(2) +#define BIT_CLR_ACH10_HOST_IDX BIT(2) +#define BIT_EPHY_CAL_DONE BIT(1) +#define BIT_CLR_ACH9_HOST_IDX BIT(1) + +#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H 0 +#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H 0xffffffffL +#define BIT_P0_MPRT_BCNQ_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H) \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H) +#define BITS_P0_MPRT_BCNQ_TXBD_DESA_H \ + (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H) +#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H(x) \ + ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_H)) +#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H) & \ + BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H) +#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H(x) | \ + BIT_P0_MPRT_BCNQ_TXBD_DESA_H(v)) + +#define BIT_RESET_APHY BIT(0) +#define BIT_CLR_ACH8_HOST_IDX BIT(0) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HI4Q_TXBD_DESA (Offset 0x0360) */ -/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ +#define BIT_SHIFT_HI4Q_TXBD_DESA 0 +#define BIT_MASK_HI4Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI4Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA) << BIT_SHIFT_HI4Q_TXBD_DESA) +#define BITS_HI4Q_TXBD_DESA \ + (BIT_MASK_HI4Q_TXBD_DESA << BIT_SHIFT_HI4Q_TXBD_DESA) +#define BIT_CLEAR_HI4Q_TXBD_DESA(x) ((x) & (~BITS_HI4Q_TXBD_DESA)) +#define BIT_GET_HI4Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA) & BIT_MASK_HI4Q_TXBD_DESA) +#define BIT_SET_HI4Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA(x) | BIT_HI4Q_TXBD_DESA(v)) -#define BIT_HI0Q_FLAG BIT(14) +/* 2 REG_HI5Q_TXBD_DESA (Offset 0x0368) */ -#define BIT_SHIFT_HI0Q_DESC_MODE 12 -#define BIT_MASK_HI0Q_DESC_MODE 0x3 -#define BIT_HI0Q_DESC_MODE(x) (((x) & BIT_MASK_HI0Q_DESC_MODE) << BIT_SHIFT_HI0Q_DESC_MODE) -#define BIT_GET_HI0Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE) & BIT_MASK_HI0Q_DESC_MODE) +#define BIT_SHIFT_HI5Q_TXBD_DESA 0 +#define BIT_MASK_HI5Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI5Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA) << BIT_SHIFT_HI5Q_TXBD_DESA) +#define BITS_HI5Q_TXBD_DESA \ + (BIT_MASK_HI5Q_TXBD_DESA << BIT_SHIFT_HI5Q_TXBD_DESA) +#define BIT_CLEAR_HI5Q_TXBD_DESA(x) ((x) & (~BITS_HI5Q_TXBD_DESA)) +#define BIT_GET_HI5Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA) & BIT_MASK_HI5Q_TXBD_DESA) +#define BIT_SET_HI5Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA(x) | BIT_HI5Q_TXBD_DESA(v)) +/* 2 REG_HI6Q_TXBD_DESA (Offset 0x0370) */ -#define BIT_SHIFT_HI0Q_DESC_NUM 0 -#define BIT_MASK_HI0Q_DESC_NUM 0xfff -#define BIT_HI0Q_DESC_NUM(x) (((x) & BIT_MASK_HI0Q_DESC_NUM) << BIT_SHIFT_HI0Q_DESC_NUM) -#define BIT_GET_HI0Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM) & BIT_MASK_HI0Q_DESC_NUM) +#define BIT_SHIFT_HI6Q_TXBD_DESA 0 +#define BIT_MASK_HI6Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI6Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA) << BIT_SHIFT_HI6Q_TXBD_DESA) +#define BITS_HI6Q_TXBD_DESA \ + (BIT_MASK_HI6Q_TXBD_DESA << BIT_SHIFT_HI6Q_TXBD_DESA) +#define BIT_CLEAR_HI6Q_TXBD_DESA(x) ((x) & (~BITS_HI6Q_TXBD_DESA)) +#define BIT_GET_HI6Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA) & BIT_MASK_HI6Q_TXBD_DESA) +#define BIT_SET_HI6Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA(x) | BIT_HI6Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM (Offset 0x0378) */ + +#define BIT_SYS_32_64_V1 BIT(31) + +#define BIT_SHIFT_P0BCNQ_DESC_MODE 29 +#define BIT_MASK_P0BCNQ_DESC_MODE 0x3 +#define BIT_P0BCNQ_DESC_MODE(x) \ + (((x) & BIT_MASK_P0BCNQ_DESC_MODE) << BIT_SHIFT_P0BCNQ_DESC_MODE) +#define BITS_P0BCNQ_DESC_MODE \ + (BIT_MASK_P0BCNQ_DESC_MODE << BIT_SHIFT_P0BCNQ_DESC_MODE) +#define BIT_CLEAR_P0BCNQ_DESC_MODE(x) ((x) & (~BITS_P0BCNQ_DESC_MODE)) +#define BIT_GET_P0BCNQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0BCNQ_DESC_MODE) & BIT_MASK_P0BCNQ_DESC_MODE) +#define BIT_SET_P0BCNQ_DESC_MODE(x, v) \ + (BIT_CLEAR_P0BCNQ_DESC_MODE(x) | BIT_P0BCNQ_DESC_MODE(v)) + +#define BIT_PCIE_P0BCNQ_FLAG BIT(28) + +#define BIT_SHIFT_P0RXQ_DESC_NUM 16 +#define BIT_MASK_P0RXQ_DESC_NUM 0xfff +#define BIT_P0RXQ_DESC_NUM(x) \ + (((x) & BIT_MASK_P0RXQ_DESC_NUM) << BIT_SHIFT_P0RXQ_DESC_NUM) +#define BITS_P0RXQ_DESC_NUM \ + (BIT_MASK_P0RXQ_DESC_NUM << BIT_SHIFT_P0RXQ_DESC_NUM) +#define BIT_CLEAR_P0RXQ_DESC_NUM(x) ((x) & (~BITS_P0RXQ_DESC_NUM)) +#define BIT_GET_P0RXQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0RXQ_DESC_NUM) & BIT_MASK_P0RXQ_DESC_NUM) +#define BIT_SET_P0RXQ_DESC_NUM(x, v) \ + (BIT_CLEAR_P0RXQ_DESC_NUM(x) | BIT_P0RXQ_DESC_NUM(v)) + +#define BIT_PCIE_P0MGQ_FLAG BIT(14) + +#define BIT_SHIFT_P0MGQ_DESC_MODE 12 +#define BIT_MASK_P0MGQ_DESC_MODE 0x3 +#define BIT_P0MGQ_DESC_MODE(x) \ + (((x) & BIT_MASK_P0MGQ_DESC_MODE) << BIT_SHIFT_P0MGQ_DESC_MODE) +#define BITS_P0MGQ_DESC_MODE \ + (BIT_MASK_P0MGQ_DESC_MODE << BIT_SHIFT_P0MGQ_DESC_MODE) +#define BIT_CLEAR_P0MGQ_DESC_MODE(x) ((x) & (~BITS_P0MGQ_DESC_MODE)) +#define BIT_GET_P0MGQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0MGQ_DESC_MODE) & BIT_MASK_P0MGQ_DESC_MODE) +#define BIT_SET_P0MGQ_DESC_MODE(x, v) \ + (BIT_CLEAR_P0MGQ_DESC_MODE(x) | BIT_P0MGQ_DESC_MODE(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HI7Q_TXBD_DESA (Offset 0x0378) */ -/* 2 REG_HI1Q_TXBD_NUM (Offset 0x038E) */ +#define BIT_SHIFT_HI7Q_TXBD_DESA 0 +#define BIT_MASK_HI7Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI7Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA) << BIT_SHIFT_HI7Q_TXBD_DESA) +#define BITS_HI7Q_TXBD_DESA \ + (BIT_MASK_HI7Q_TXBD_DESA << BIT_SHIFT_HI7Q_TXBD_DESA) +#define BIT_CLEAR_HI7Q_TXBD_DESA(x) ((x) & (~BITS_HI7Q_TXBD_DESA)) +#define BIT_GET_HI7Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA) & BIT_MASK_HI7Q_TXBD_DESA) +#define BIT_SET_HI7Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA(x) | BIT_HI7Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM (Offset 0x0378) */ + +#define BIT_SHIFT_P0MGQ_DESC_NUM 0 +#define BIT_MASK_P0MGQ_DESC_NUM 0xfff +#define BIT_P0MGQ_DESC_NUM(x) \ + (((x) & BIT_MASK_P0MGQ_DESC_NUM) << BIT_SHIFT_P0MGQ_DESC_NUM) +#define BITS_P0MGQ_DESC_NUM \ + (BIT_MASK_P0MGQ_DESC_NUM << BIT_SHIFT_P0MGQ_DESC_NUM) +#define BIT_CLEAR_P0MGQ_DESC_NUM(x) ((x) & (~BITS_P0MGQ_DESC_NUM)) +#define BIT_GET_P0MGQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0MGQ_DESC_NUM) & BIT_MASK_P0MGQ_DESC_NUM) +#define BIT_SET_P0MGQ_DESC_NUM(x, v) \ + (BIT_CLEAR_P0MGQ_DESC_NUM(x) | BIT_P0MGQ_DESC_NUM(v)) + +/* 2 REG_CHNL_DMA_CFG (Offset 0x037C) */ + +#define BIT_TXHCI_EN BIT(26) +#define BIT_TXHCI_IDLE BIT(25) +#define BIT_DMA_PRI_EN BIT(24) +#define BIT_PCIE_FWCMDQ_FLAG BIT(14) + +#define BIT_SHIFT_FWCMDQ_DESC_MODE 12 +#define BIT_MASK_FWCMDQ_DESC_MODE 0x3 +#define BIT_FWCMDQ_DESC_MODE(x) \ + (((x) & BIT_MASK_FWCMDQ_DESC_MODE) << BIT_SHIFT_FWCMDQ_DESC_MODE) +#define BITS_FWCMDQ_DESC_MODE \ + (BIT_MASK_FWCMDQ_DESC_MODE << BIT_SHIFT_FWCMDQ_DESC_MODE) +#define BIT_CLEAR_FWCMDQ_DESC_MODE(x) ((x) & (~BITS_FWCMDQ_DESC_MODE)) +#define BIT_GET_FWCMDQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_DESC_MODE) & BIT_MASK_FWCMDQ_DESC_MODE) +#define BIT_SET_FWCMDQ_DESC_MODE(x, v) \ + (BIT_CLEAR_FWCMDQ_DESC_MODE(x) | BIT_FWCMDQ_DESC_MODE(v)) + +#define BIT_SHIFT_FWCMDQ_DESC_NUM 0 +#define BIT_MASK_FWCMDQ_DESC_NUM 0xfff +#define BIT_FWCMDQ_DESC_NUM(x) \ + (((x) & BIT_MASK_FWCMDQ_DESC_NUM) << BIT_SHIFT_FWCMDQ_DESC_NUM) +#define BITS_FWCMDQ_DESC_NUM \ + (BIT_MASK_FWCMDQ_DESC_NUM << BIT_SHIFT_FWCMDQ_DESC_NUM) +#define BIT_CLEAR_FWCMDQ_DESC_NUM(x) ((x) & (~BITS_FWCMDQ_DESC_NUM)) +#define BIT_GET_FWCMDQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_DESC_NUM) & BIT_MASK_FWCMDQ_DESC_NUM) +#define BIT_SET_FWCMDQ_DESC_NUM(x, v) \ + (BIT_CLEAR_FWCMDQ_DESC_NUM(x) | BIT_FWCMDQ_DESC_NUM(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_HI1Q_FLAG BIT(14) +/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ -#define BIT_SHIFT_HI1Q_DESC_MODE 12 -#define BIT_MASK_HI1Q_DESC_MODE 0x3 -#define BIT_HI1Q_DESC_MODE(x) (((x) & BIT_MASK_HI1Q_DESC_MODE) << BIT_SHIFT_HI1Q_DESC_MODE) -#define BIT_GET_HI1Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE) & BIT_MASK_HI1Q_DESC_MODE) +#define BIT_PCIE_MGQ_FLAG BIT(14) +#endif -#define BIT_SHIFT_HI1Q_DESC_NUM 0 -#define BIT_MASK_HI1Q_DESC_NUM 0xfff -#define BIT_HI1Q_DESC_NUM(x) (((x) & BIT_MASK_HI1Q_DESC_NUM) << BIT_SHIFT_HI1Q_DESC_NUM) -#define BIT_GET_HI1Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM) & BIT_MASK_HI1Q_DESC_NUM) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) +/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ -/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ +#define BIT_HCI_MGQ_FLAG BIT(14) -#define BIT_HI2Q_FLAG BIT(14) +#endif -#define BIT_SHIFT_HI2Q_DESC_MODE 12 -#define BIT_MASK_HI2Q_DESC_MODE 0x3 -#define BIT_HI2Q_DESC_MODE(x) (((x) & BIT_MASK_HI2Q_DESC_MODE) << BIT_SHIFT_HI2Q_DESC_MODE) -#define BIT_GET_HI2Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE) & BIT_MASK_HI2Q_DESC_MODE) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ -#define BIT_SHIFT_HI2Q_DESC_NUM 0 -#define BIT_MASK_HI2Q_DESC_NUM 0xfff -#define BIT_HI2Q_DESC_NUM(x) (((x) & BIT_MASK_HI2Q_DESC_NUM) << BIT_SHIFT_HI2Q_DESC_NUM) -#define BIT_GET_HI2Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM) & BIT_MASK_HI2Q_DESC_NUM) +#define BIT_SHIFT_MGQ_DESC_MODE 12 +#define BIT_MASK_MGQ_DESC_MODE 0x3 +#define BIT_MGQ_DESC_MODE(x) \ + (((x) & BIT_MASK_MGQ_DESC_MODE) << BIT_SHIFT_MGQ_DESC_MODE) +#define BITS_MGQ_DESC_MODE (BIT_MASK_MGQ_DESC_MODE << BIT_SHIFT_MGQ_DESC_MODE) +#define BIT_CLEAR_MGQ_DESC_MODE(x) ((x) & (~BITS_MGQ_DESC_MODE)) +#define BIT_GET_MGQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_MODE) & BIT_MASK_MGQ_DESC_MODE) +#define BIT_SET_MGQ_DESC_MODE(x, v) \ + (BIT_CLEAR_MGQ_DESC_MODE(x) | BIT_MGQ_DESC_MODE(v)) + +#define BIT_SHIFT_MGQ_DESC_NUM 0 +#define BIT_MASK_MGQ_DESC_NUM 0xfff +#define BIT_MGQ_DESC_NUM(x) \ + (((x) & BIT_MASK_MGQ_DESC_NUM) << BIT_SHIFT_MGQ_DESC_NUM) +#define BITS_MGQ_DESC_NUM (BIT_MASK_MGQ_DESC_NUM << BIT_SHIFT_MGQ_DESC_NUM) +#define BIT_CLEAR_MGQ_DESC_NUM(x) ((x) & (~BITS_MGQ_DESC_NUM)) +#define BIT_GET_MGQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_NUM) & BIT_MASK_MGQ_DESC_NUM) +#define BIT_SET_MGQ_DESC_NUM(x, v) \ + (BIT_CLEAR_MGQ_DESC_NUM(x) | BIT_MGQ_DESC_NUM(v)) +/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ -/* 2 REG_HI3Q_TXBD_NUM (Offset 0x0392) */ +#define BIT_SYS_32_64 BIT(15) -#define BIT_HI3Q_FLAG BIT(14) +#define BIT_SHIFT_BCNQ_DESC_MODE 13 +#define BIT_MASK_BCNQ_DESC_MODE 0x3 +#define BIT_BCNQ_DESC_MODE(x) \ + (((x) & BIT_MASK_BCNQ_DESC_MODE) << BIT_SHIFT_BCNQ_DESC_MODE) +#define BITS_BCNQ_DESC_MODE \ + (BIT_MASK_BCNQ_DESC_MODE << BIT_SHIFT_BCNQ_DESC_MODE) +#define BIT_CLEAR_BCNQ_DESC_MODE(x) ((x) & (~BITS_BCNQ_DESC_MODE)) +#define BIT_GET_BCNQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_BCNQ_DESC_MODE) & BIT_MASK_BCNQ_DESC_MODE) +#define BIT_SET_BCNQ_DESC_MODE(x, v) \ + (BIT_CLEAR_BCNQ_DESC_MODE(x) | BIT_BCNQ_DESC_MODE(v)) -#define BIT_SHIFT_HI3Q_DESC_MODE 12 -#define BIT_MASK_HI3Q_DESC_MODE 0x3 -#define BIT_HI3Q_DESC_MODE(x) (((x) & BIT_MASK_HI3Q_DESC_MODE) << BIT_SHIFT_HI3Q_DESC_MODE) -#define BIT_GET_HI3Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE) & BIT_MASK_HI3Q_DESC_MODE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HI3Q_DESC_NUM 0 -#define BIT_MASK_HI3Q_DESC_NUM 0xfff -#define BIT_HI3Q_DESC_NUM(x) (((x) & BIT_MASK_HI3Q_DESC_NUM) << BIT_SHIFT_HI3Q_DESC_NUM) -#define BIT_GET_HI3Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM) & BIT_MASK_HI3Q_DESC_NUM) +/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ +#define BIT_PCIE_BCNQ_FLAG BIT(12) -/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ +#endif -#define BIT_HI4Q_FLAG BIT(14) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_HI4Q_DESC_MODE 12 -#define BIT_MASK_HI4Q_DESC_MODE 0x3 -#define BIT_HI4Q_DESC_MODE(x) (((x) & BIT_MASK_HI4Q_DESC_MODE) << BIT_SHIFT_HI4Q_DESC_MODE) -#define BIT_GET_HI4Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE) & BIT_MASK_HI4Q_DESC_MODE) +/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ +#define BIT_HCI_BCNQ_FLAG BIT(12) -#define BIT_SHIFT_HI4Q_DESC_NUM 0 -#define BIT_MASK_HI4Q_DESC_NUM 0xfff -#define BIT_HI4Q_DESC_NUM(x) (((x) & BIT_MASK_HI4Q_DESC_NUM) << BIT_SHIFT_HI4Q_DESC_NUM) -#define BIT_GET_HI4Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM) & BIT_MASK_HI4Q_DESC_NUM) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_HI5Q_TXBD_NUM (Offset 0x0396) */ +/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ -#define BIT_HI5Q_FLAG BIT(14) +#define BIT_SHIFT_RXQ_DESC_NUM 0 +#define BIT_MASK_RXQ_DESC_NUM 0xfff +#define BIT_RXQ_DESC_NUM(x) \ + (((x) & BIT_MASK_RXQ_DESC_NUM) << BIT_SHIFT_RXQ_DESC_NUM) +#define BITS_RXQ_DESC_NUM (BIT_MASK_RXQ_DESC_NUM << BIT_SHIFT_RXQ_DESC_NUM) +#define BIT_CLEAR_RXQ_DESC_NUM(x) ((x) & (~BITS_RXQ_DESC_NUM)) +#define BIT_GET_RXQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_RXQ_DESC_NUM) & BIT_MASK_RXQ_DESC_NUM) +#define BIT_SET_RXQ_DESC_NUM(x, v) \ + (BIT_CLEAR_RXQ_DESC_NUM(x) | BIT_RXQ_DESC_NUM(v)) -#define BIT_SHIFT_HI5Q_DESC_MODE 12 -#define BIT_MASK_HI5Q_DESC_MODE 0x3 -#define BIT_HI5Q_DESC_MODE(x) (((x) & BIT_MASK_HI5Q_DESC_MODE) << BIT_SHIFT_HI5Q_DESC_MODE) -#define BIT_GET_HI5Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE) & BIT_MASK_HI5Q_DESC_MODE) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HI5Q_DESC_NUM 0 -#define BIT_MASK_HI5Q_DESC_NUM 0xfff -#define BIT_HI5Q_DESC_NUM(x) (((x) & BIT_MASK_HI5Q_DESC_NUM) << BIT_SHIFT_HI5Q_DESC_NUM) -#define BIT_GET_HI5Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM) & BIT_MASK_HI5Q_DESC_NUM) +/* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */ +#define BIT_PCIE_ACH1_FLAG_V1 BIT(30) -/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ +#define BIT_SHIFT_ACH1_DESC_MODE_V1 28 +#define BIT_MASK_ACH1_DESC_MODE_V1 0x3 +#define BIT_ACH1_DESC_MODE_V1(x) \ + (((x) & BIT_MASK_ACH1_DESC_MODE_V1) << BIT_SHIFT_ACH1_DESC_MODE_V1) +#define BITS_ACH1_DESC_MODE_V1 \ + (BIT_MASK_ACH1_DESC_MODE_V1 << BIT_SHIFT_ACH1_DESC_MODE_V1) +#define BIT_CLEAR_ACH1_DESC_MODE_V1(x) ((x) & (~BITS_ACH1_DESC_MODE_V1)) +#define BIT_GET_ACH1_DESC_MODE_V1(x) \ + (((x) >> BIT_SHIFT_ACH1_DESC_MODE_V1) & BIT_MASK_ACH1_DESC_MODE_V1) +#define BIT_SET_ACH1_DESC_MODE_V1(x, v) \ + (BIT_CLEAR_ACH1_DESC_MODE_V1(x) | BIT_ACH1_DESC_MODE_V1(v)) -#define BIT_HI6Q_FLAG BIT(14) +#define BIT_SHIFT_ACH1_DESC_NUM_V1 16 +#define BIT_MASK_ACH1_DESC_NUM_V1 0xfff +#define BIT_ACH1_DESC_NUM_V1(x) \ + (((x) & BIT_MASK_ACH1_DESC_NUM_V1) << BIT_SHIFT_ACH1_DESC_NUM_V1) +#define BITS_ACH1_DESC_NUM_V1 \ + (BIT_MASK_ACH1_DESC_NUM_V1 << BIT_SHIFT_ACH1_DESC_NUM_V1) +#define BIT_CLEAR_ACH1_DESC_NUM_V1(x) ((x) & (~BITS_ACH1_DESC_NUM_V1)) +#define BIT_GET_ACH1_DESC_NUM_V1(x) \ + (((x) >> BIT_SHIFT_ACH1_DESC_NUM_V1) & BIT_MASK_ACH1_DESC_NUM_V1) +#define BIT_SET_ACH1_DESC_NUM_V1(x, v) \ + (BIT_CLEAR_ACH1_DESC_NUM_V1(x) | BIT_ACH1_DESC_NUM_V1(v)) -#define BIT_SHIFT_HI6Q_DESC_MODE 12 -#define BIT_MASK_HI6Q_DESC_MODE 0x3 -#define BIT_HI6Q_DESC_MODE(x) (((x) & BIT_MASK_HI6Q_DESC_MODE) << BIT_SHIFT_HI6Q_DESC_MODE) -#define BIT_GET_HI6Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE) & BIT_MASK_HI6Q_DESC_MODE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HI6Q_DESC_NUM 0 -#define BIT_MASK_HI6Q_DESC_NUM 0xfff -#define BIT_HI6Q_DESC_NUM(x) (((x) & BIT_MASK_HI6Q_DESC_NUM) << BIT_SHIFT_HI6Q_DESC_NUM) -#define BIT_GET_HI6Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM) & BIT_MASK_HI6Q_DESC_NUM) +/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ +#define BIT_PCIE_VOQ_FLAG BIT(14) -/* 2 REG_HI7Q_TXBD_NUM (Offset 0x039A) */ +#endif -#define BIT_HI7Q_FLAG BIT(14) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_HI7Q_DESC_MODE 12 -#define BIT_MASK_HI7Q_DESC_MODE 0x3 -#define BIT_HI7Q_DESC_MODE(x) (((x) & BIT_MASK_HI7Q_DESC_MODE) << BIT_SHIFT_HI7Q_DESC_MODE) -#define BIT_GET_HI7Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE) & BIT_MASK_HI7Q_DESC_MODE) +/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ +#define BIT_HCI_VOQ_FLAG BIT(14) -#define BIT_SHIFT_HI7Q_DESC_NUM 0 -#define BIT_MASK_HI7Q_DESC_NUM 0xfff -#define BIT_HI7Q_DESC_NUM(x) (((x) & BIT_MASK_HI7Q_DESC_NUM) << BIT_SHIFT_HI7Q_DESC_NUM) -#define BIT_GET_HI7Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM) & BIT_MASK_HI7Q_DESC_NUM) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */ -#define BIT_CLR_HI7Q_HW_IDX BIT(29) -#define BIT_CLR_HI6Q_HW_IDX BIT(28) -#define BIT_CLR_HI5Q_HW_IDX BIT(27) -#define BIT_CLR_HI4Q_HW_IDX BIT(26) -#define BIT_CLR_HI3Q_HW_IDX BIT(25) -#define BIT_CLR_HI2Q_HW_IDX BIT(24) -#define BIT_CLR_HI1Q_HW_IDX BIT(23) +#define BIT_PCIE_ACH0_FLAG BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ +#define BIT_SHIFT_VOQ_DESC_MODE 12 +#define BIT_MASK_VOQ_DESC_MODE 0x3 +#define BIT_VOQ_DESC_MODE(x) \ + (((x) & BIT_MASK_VOQ_DESC_MODE) << BIT_SHIFT_VOQ_DESC_MODE) +#define BITS_VOQ_DESC_MODE (BIT_MASK_VOQ_DESC_MODE << BIT_SHIFT_VOQ_DESC_MODE) +#define BIT_CLEAR_VOQ_DESC_MODE(x) ((x) & (~BITS_VOQ_DESC_MODE)) +#define BIT_GET_VOQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_MODE) & BIT_MASK_VOQ_DESC_MODE) +#define BIT_SET_VOQ_DESC_MODE(x, v) \ + (BIT_CLEAR_VOQ_DESC_MODE(x) | BIT_VOQ_DESC_MODE(v)) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_BCN7DOK BIT(23) -#define BIT_BCN7DOKM BIT(23) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */ +#define BIT_SHIFT_ACH0_DESC_MODE 12 +#define BIT_MASK_ACH0_DESC_MODE 0x3 +#define BIT_ACH0_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH0_DESC_MODE) << BIT_SHIFT_ACH0_DESC_MODE) +#define BITS_ACH0_DESC_MODE \ + (BIT_MASK_ACH0_DESC_MODE << BIT_SHIFT_ACH0_DESC_MODE) +#define BIT_CLEAR_ACH0_DESC_MODE(x) ((x) & (~BITS_ACH0_DESC_MODE)) +#define BIT_GET_ACH0_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH0_DESC_MODE) & BIT_MASK_ACH0_DESC_MODE) +#define BIT_SET_ACH0_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH0_DESC_MODE(x) | BIT_ACH0_DESC_MODE(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ -#define BIT_CLR_HI0Q_HW_IDX BIT(22) +#define BIT_SHIFT_VOQ_DESC_NUM 0 +#define BIT_MASK_VOQ_DESC_NUM 0xfff +#define BIT_VOQ_DESC_NUM(x) \ + (((x) & BIT_MASK_VOQ_DESC_NUM) << BIT_SHIFT_VOQ_DESC_NUM) +#define BITS_VOQ_DESC_NUM (BIT_MASK_VOQ_DESC_NUM << BIT_SHIFT_VOQ_DESC_NUM) +#define BIT_CLEAR_VOQ_DESC_NUM(x) ((x) & (~BITS_VOQ_DESC_NUM)) +#define BIT_GET_VOQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_NUM) & BIT_MASK_VOQ_DESC_NUM) +#define BIT_SET_VOQ_DESC_NUM(x, v) \ + (BIT_CLEAR_VOQ_DESC_NUM(x) | BIT_VOQ_DESC_NUM(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */ +#define BIT_SHIFT_ACH0_DESC_NUM 0 +#define BIT_MASK_ACH0_DESC_NUM 0xfff +#define BIT_ACH0_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH0_DESC_NUM) << BIT_SHIFT_ACH0_DESC_NUM) +#define BITS_ACH0_DESC_NUM (BIT_MASK_ACH0_DESC_NUM << BIT_SHIFT_ACH0_DESC_NUM) +#define BIT_CLEAR_ACH0_DESC_NUM(x) ((x) & (~BITS_ACH0_DESC_NUM)) +#define BIT_GET_ACH0_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH0_DESC_NUM) & BIT_MASK_ACH0_DESC_NUM) +#define BIT_SET_ACH0_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH0_DESC_NUM(x) | BIT_ACH0_DESC_NUM(v)) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_BCN6DOK BIT(22) -#define BIT_BCN6DOKM BIT(22) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ +#define BIT_PCIE_VIQ_FLAG BIT(14) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ -#define BIT_CLR_BKQ_HW_IDX BIT(21) +#define BIT_HCI_VIQ_FLAG BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ +#define BIT_SHIFT_VIQ_DESC_MODE 12 +#define BIT_MASK_VIQ_DESC_MODE 0x3 +#define BIT_VIQ_DESC_MODE(x) \ + (((x) & BIT_MASK_VIQ_DESC_MODE) << BIT_SHIFT_VIQ_DESC_MODE) +#define BITS_VIQ_DESC_MODE (BIT_MASK_VIQ_DESC_MODE << BIT_SHIFT_VIQ_DESC_MODE) +#define BIT_CLEAR_VIQ_DESC_MODE(x) ((x) & (~BITS_VIQ_DESC_MODE)) +#define BIT_GET_VIQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_MODE) & BIT_MASK_VIQ_DESC_MODE) +#define BIT_SET_VIQ_DESC_MODE(x, v) \ + (BIT_CLEAR_VIQ_DESC_MODE(x) | BIT_VIQ_DESC_MODE(v)) + +#define BIT_SHIFT_VIQ_DESC_NUM 0 +#define BIT_MASK_VIQ_DESC_NUM 0xfff +#define BIT_VIQ_DESC_NUM(x) \ + (((x) & BIT_MASK_VIQ_DESC_NUM) << BIT_SHIFT_VIQ_DESC_NUM) +#define BITS_VIQ_DESC_NUM (BIT_MASK_VIQ_DESC_NUM << BIT_SHIFT_VIQ_DESC_NUM) +#define BIT_CLEAR_VIQ_DESC_NUM(x) ((x) & (~BITS_VIQ_DESC_NUM)) +#define BIT_GET_VIQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_NUM) & BIT_MASK_VIQ_DESC_NUM) +#define BIT_SET_VIQ_DESC_NUM(x, v) \ + (BIT_CLEAR_VIQ_DESC_NUM(x) | BIT_VIQ_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */ + +#define BIT_PCIE_ACH3_FLAG_V1 BIT(30) + +#define BIT_SHIFT_ACH3_DESC_MODE_V1 28 +#define BIT_MASK_ACH3_DESC_MODE_V1 0x3 +#define BIT_ACH3_DESC_MODE_V1(x) \ + (((x) & BIT_MASK_ACH3_DESC_MODE_V1) << BIT_SHIFT_ACH3_DESC_MODE_V1) +#define BITS_ACH3_DESC_MODE_V1 \ + (BIT_MASK_ACH3_DESC_MODE_V1 << BIT_SHIFT_ACH3_DESC_MODE_V1) +#define BIT_CLEAR_ACH3_DESC_MODE_V1(x) ((x) & (~BITS_ACH3_DESC_MODE_V1)) +#define BIT_GET_ACH3_DESC_MODE_V1(x) \ + (((x) >> BIT_SHIFT_ACH3_DESC_MODE_V1) & BIT_MASK_ACH3_DESC_MODE_V1) +#define BIT_SET_ACH3_DESC_MODE_V1(x, v) \ + (BIT_CLEAR_ACH3_DESC_MODE_V1(x) | BIT_ACH3_DESC_MODE_V1(v)) + +#define BIT_SHIFT_ACH3_DESC_NUM_V1 16 +#define BIT_MASK_ACH3_DESC_NUM_V1 0xfff +#define BIT_ACH3_DESC_NUM_V1(x) \ + (((x) & BIT_MASK_ACH3_DESC_NUM_V1) << BIT_SHIFT_ACH3_DESC_NUM_V1) +#define BITS_ACH3_DESC_NUM_V1 \ + (BIT_MASK_ACH3_DESC_NUM_V1 << BIT_SHIFT_ACH3_DESC_NUM_V1) +#define BIT_CLEAR_ACH3_DESC_NUM_V1(x) ((x) & (~BITS_ACH3_DESC_NUM_V1)) +#define BIT_GET_ACH3_DESC_NUM_V1(x) \ + (((x) >> BIT_SHIFT_ACH3_DESC_NUM_V1) & BIT_MASK_ACH3_DESC_NUM_V1) +#define BIT_SET_ACH3_DESC_NUM_V1(x, v) \ + (BIT_CLEAR_ACH3_DESC_NUM_V1(x) | BIT_ACH3_DESC_NUM_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ -#define BIT_BCN5DOK BIT(21) -#define BIT_BCN5DOKM BIT(21) +#define BIT_PCIE_BEQ_FLAG BIT(14) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ +#define BIT_HCI_BEQ_FLAG BIT(14) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_BEQ_HW_IDX BIT(20) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */ +#define BIT_PCIE_ACH2_FLAG BIT(14) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ -#define BIT_BCN4DOK BIT(20) -#define BIT_BCN4DOKM BIT(20) -#define BIT_RX_OVER_RD_ERR BIT(20) +#define BIT_SHIFT_BEQ_DESC_MODE 12 +#define BIT_MASK_BEQ_DESC_MODE 0x3 +#define BIT_BEQ_DESC_MODE(x) \ + (((x) & BIT_MASK_BEQ_DESC_MODE) << BIT_SHIFT_BEQ_DESC_MODE) +#define BITS_BEQ_DESC_MODE (BIT_MASK_BEQ_DESC_MODE << BIT_SHIFT_BEQ_DESC_MODE) +#define BIT_CLEAR_BEQ_DESC_MODE(x) ((x) & (~BITS_BEQ_DESC_MODE)) +#define BIT_GET_BEQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_MODE) & BIT_MASK_BEQ_DESC_MODE) +#define BIT_SET_BEQ_DESC_MODE(x, v) \ + (BIT_CLEAR_BEQ_DESC_MODE(x) | BIT_BEQ_DESC_MODE(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */ +#define BIT_SHIFT_ACH2_DESC_MODE 12 +#define BIT_MASK_ACH2_DESC_MODE 0x3 +#define BIT_ACH2_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH2_DESC_MODE) << BIT_SHIFT_ACH2_DESC_MODE) +#define BITS_ACH2_DESC_MODE \ + (BIT_MASK_ACH2_DESC_MODE << BIT_SHIFT_ACH2_DESC_MODE) +#define BIT_CLEAR_ACH2_DESC_MODE(x) ((x) & (~BITS_ACH2_DESC_MODE)) +#define BIT_GET_ACH2_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH2_DESC_MODE) & BIT_MASK_ACH2_DESC_MODE) +#define BIT_SET_ACH2_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH2_DESC_MODE(x) | BIT_ACH2_DESC_MODE(v)) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_VIQ_HW_IDX BIT(19) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ +#define BIT_SHIFT_BEQ_DESC_NUM 0 +#define BIT_MASK_BEQ_DESC_NUM 0xfff +#define BIT_BEQ_DESC_NUM(x) \ + (((x) & BIT_MASK_BEQ_DESC_NUM) << BIT_SHIFT_BEQ_DESC_NUM) +#define BITS_BEQ_DESC_NUM (BIT_MASK_BEQ_DESC_NUM << BIT_SHIFT_BEQ_DESC_NUM) +#define BIT_CLEAR_BEQ_DESC_NUM(x) ((x) & (~BITS_BEQ_DESC_NUM)) +#define BIT_GET_BEQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_NUM) & BIT_MASK_BEQ_DESC_NUM) +#define BIT_SET_BEQ_DESC_NUM(x, v) \ + (BIT_CLEAR_BEQ_DESC_NUM(x) | BIT_BEQ_DESC_NUM(v)) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */ -#define BIT_BCN3DOK BIT(19) -#define BIT_BCN3DOKM BIT(19) -#define BIT_RXDMA_STUCK BIT(19) +#define BIT_SHIFT_ACH2_DESC_NUM 0 +#define BIT_MASK_ACH2_DESC_NUM 0xfff +#define BIT_ACH2_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH2_DESC_NUM) << BIT_SHIFT_ACH2_DESC_NUM) +#define BITS_ACH2_DESC_NUM (BIT_MASK_ACH2_DESC_NUM << BIT_SHIFT_ACH2_DESC_NUM) +#define BIT_CLEAR_ACH2_DESC_NUM(x) ((x) & (~BITS_ACH2_DESC_NUM)) +#define BIT_GET_ACH2_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH2_DESC_NUM) & BIT_MASK_ACH2_DESC_NUM) +#define BIT_SET_ACH2_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH2_DESC_NUM(x) | BIT_ACH2_DESC_NUM(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ +#define BIT_PCIE_BKQ_FLAG BIT(14) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_CLR_VOQ_HW_IDX BIT(18) +/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ + +#define BIT_HCI_BKQ_FLAG BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ +#define BIT_SHIFT_BKQ_DESC_MODE 12 +#define BIT_MASK_BKQ_DESC_MODE 0x3 +#define BIT_BKQ_DESC_MODE(x) \ + (((x) & BIT_MASK_BKQ_DESC_MODE) << BIT_SHIFT_BKQ_DESC_MODE) +#define BITS_BKQ_DESC_MODE (BIT_MASK_BKQ_DESC_MODE << BIT_SHIFT_BKQ_DESC_MODE) +#define BIT_CLEAR_BKQ_DESC_MODE(x) ((x) & (~BITS_BKQ_DESC_MODE)) +#define BIT_GET_BKQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_MODE) & BIT_MASK_BKQ_DESC_MODE) +#define BIT_SET_BKQ_DESC_MODE(x, v) \ + (BIT_CLEAR_BKQ_DESC_MODE(x) | BIT_BKQ_DESC_MODE(v)) + +#define BIT_SHIFT_BKQ_DESC_NUM 0 +#define BIT_MASK_BKQ_DESC_NUM 0xfff +#define BIT_BKQ_DESC_NUM(x) \ + (((x) & BIT_MASK_BKQ_DESC_NUM) << BIT_SHIFT_BKQ_DESC_NUM) +#define BITS_BKQ_DESC_NUM (BIT_MASK_BKQ_DESC_NUM << BIT_SHIFT_BKQ_DESC_NUM) +#define BIT_CLEAR_BKQ_DESC_NUM(x) ((x) & (~BITS_BKQ_DESC_NUM)) +#define BIT_GET_BKQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_NUM) & BIT_MASK_BKQ_DESC_NUM) +#define BIT_SET_BKQ_DESC_NUM(x, v) \ + (BIT_CLEAR_BKQ_DESC_NUM(x) | BIT_BKQ_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */ + +#define BIT_P0HI1Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI1Q_DESC_MODE 28 +#define BIT_MASK_P0HI1Q_DESC_MODE 0x3 +#define BIT_P0HI1Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI1Q_DESC_MODE) << BIT_SHIFT_P0HI1Q_DESC_MODE) +#define BITS_P0HI1Q_DESC_MODE \ + (BIT_MASK_P0HI1Q_DESC_MODE << BIT_SHIFT_P0HI1Q_DESC_MODE) +#define BIT_CLEAR_P0HI1Q_DESC_MODE(x) ((x) & (~BITS_P0HI1Q_DESC_MODE)) +#define BIT_GET_P0HI1Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_DESC_MODE) & BIT_MASK_P0HI1Q_DESC_MODE) +#define BIT_SET_P0HI1Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI1Q_DESC_MODE(x) | BIT_P0HI1Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI1Q_DESC_NUM 16 +#define BIT_MASK_P0HI1Q_DESC_NUM 0xfff +#define BIT_P0HI1Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI1Q_DESC_NUM) << BIT_SHIFT_P0HI1Q_DESC_NUM) +#define BITS_P0HI1Q_DESC_NUM \ + (BIT_MASK_P0HI1Q_DESC_NUM << BIT_SHIFT_P0HI1Q_DESC_NUM) +#define BIT_CLEAR_P0HI1Q_DESC_NUM(x) ((x) & (~BITS_P0HI1Q_DESC_NUM)) +#define BIT_GET_P0HI1Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_DESC_NUM) & BIT_MASK_P0HI1Q_DESC_NUM) +#define BIT_SET_P0HI1Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI1Q_DESC_NUM(x) | BIT_P0HI1Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ -#define BIT_BCN2DOK BIT(18) -#define BIT_BCN2DOKM BIT(18) +#define BIT_HI0Q_FLAG BIT(14) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */ +#define BIT_P0HI0Q_FLAG BIT(14) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_MGQ_HW_IDX BIT(17) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ +#define BIT_SHIFT_HI0Q_DESC_MODE 12 +#define BIT_MASK_HI0Q_DESC_MODE 0x3 +#define BIT_HI0Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI0Q_DESC_MODE) << BIT_SHIFT_HI0Q_DESC_MODE) +#define BITS_HI0Q_DESC_MODE \ + (BIT_MASK_HI0Q_DESC_MODE << BIT_SHIFT_HI0Q_DESC_MODE) +#define BIT_CLEAR_HI0Q_DESC_MODE(x) ((x) & (~BITS_HI0Q_DESC_MODE)) +#define BIT_GET_HI0Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_MODE) & BIT_MASK_HI0Q_DESC_MODE) +#define BIT_SET_HI0Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI0Q_DESC_MODE(x) | BIT_HI0Q_DESC_MODE(v)) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */ -#define BIT_BCN1DOK BIT(17) -#define BIT_BCN1DOKM BIT(17) +#define BIT_SHIFT_P0HI0Q_DESC_MODE 12 +#define BIT_MASK_P0HI0Q_DESC_MODE 0x3 +#define BIT_P0HI0Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI0Q_DESC_MODE) << BIT_SHIFT_P0HI0Q_DESC_MODE) +#define BITS_P0HI0Q_DESC_MODE \ + (BIT_MASK_P0HI0Q_DESC_MODE << BIT_SHIFT_P0HI0Q_DESC_MODE) +#define BIT_CLEAR_P0HI0Q_DESC_MODE(x) ((x) & (~BITS_P0HI0Q_DESC_MODE)) +#define BIT_GET_P0HI0Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_DESC_MODE) & BIT_MASK_P0HI0Q_DESC_MODE) +#define BIT_SET_P0HI0Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI0Q_DESC_MODE(x) | BIT_P0HI0Q_DESC_MODE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ +#define BIT_SHIFT_HI0Q_DESC_NUM 0 +#define BIT_MASK_HI0Q_DESC_NUM 0xfff +#define BIT_HI0Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI0Q_DESC_NUM) << BIT_SHIFT_HI0Q_DESC_NUM) +#define BITS_HI0Q_DESC_NUM (BIT_MASK_HI0Q_DESC_NUM << BIT_SHIFT_HI0Q_DESC_NUM) +#define BIT_CLEAR_HI0Q_DESC_NUM(x) ((x) & (~BITS_HI0Q_DESC_NUM)) +#define BIT_GET_HI0Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_NUM) & BIT_MASK_HI0Q_DESC_NUM) +#define BIT_SET_HI0Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI0Q_DESC_NUM(x) | BIT_HI0Q_DESC_NUM(v)) -/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TSFT2_HCI 16 -#define BIT_MASK_TSFT2_HCI 0xffff -#define BIT_TSFT2_HCI(x) (((x) & BIT_MASK_TSFT2_HCI) << BIT_SHIFT_TSFT2_HCI) -#define BIT_GET_TSFT2_HCI(x) (((x) >> BIT_SHIFT_TSFT2_HCI) & BIT_MASK_TSFT2_HCI) +/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */ -#define BIT_CLR_RXQ_HW_IDX BIT(16) +#define BIT_SHIFT_P0HI0Q_DESC_NUM 0 +#define BIT_MASK_P0HI0Q_DESC_NUM 0xfff +#define BIT_P0HI0Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI0Q_DESC_NUM) << BIT_SHIFT_P0HI0Q_DESC_NUM) +#define BITS_P0HI0Q_DESC_NUM \ + (BIT_MASK_P0HI0Q_DESC_NUM << BIT_SHIFT_P0HI0Q_DESC_NUM) +#define BIT_CLEAR_P0HI0Q_DESC_NUM(x) ((x) & (~BITS_P0HI0Q_DESC_NUM)) +#define BIT_GET_P0HI0Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_DESC_NUM) & BIT_MASK_P0HI0Q_DESC_NUM) +#define BIT_SET_P0HI0Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI0Q_DESC_NUM(x) | BIT_P0HI0Q_DESC_NUM(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_HI1Q_TXBD_NUM (Offset 0x038E) */ +#define BIT_HI1Q_FLAG BIT(14) + +#define BIT_SHIFT_HI1Q_DESC_MODE 12 +#define BIT_MASK_HI1Q_DESC_MODE 0x3 +#define BIT_HI1Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI1Q_DESC_MODE) << BIT_SHIFT_HI1Q_DESC_MODE) +#define BITS_HI1Q_DESC_MODE \ + (BIT_MASK_HI1Q_DESC_MODE << BIT_SHIFT_HI1Q_DESC_MODE) +#define BIT_CLEAR_HI1Q_DESC_MODE(x) ((x) & (~BITS_HI1Q_DESC_MODE)) +#define BIT_GET_HI1Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_MODE) & BIT_MASK_HI1Q_DESC_MODE) +#define BIT_SET_HI1Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI1Q_DESC_MODE(x) | BIT_HI1Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI1Q_DESC_NUM 0 +#define BIT_MASK_HI1Q_DESC_NUM 0xfff +#define BIT_HI1Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI1Q_DESC_NUM) << BIT_SHIFT_HI1Q_DESC_NUM) +#define BITS_HI1Q_DESC_NUM (BIT_MASK_HI1Q_DESC_NUM << BIT_SHIFT_HI1Q_DESC_NUM) +#define BIT_CLEAR_HI1Q_DESC_NUM(x) ((x) & (~BITS_HI1Q_DESC_NUM)) +#define BIT_GET_HI1Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_NUM) & BIT_MASK_HI1Q_DESC_NUM) +#define BIT_SET_HI1Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI1Q_DESC_NUM(x) | BIT_HI1Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */ + +#define BIT_P0HI3Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI3Q_DESC_MODE 28 +#define BIT_MASK_P0HI3Q_DESC_MODE 0x3 +#define BIT_P0HI3Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI3Q_DESC_MODE) << BIT_SHIFT_P0HI3Q_DESC_MODE) +#define BITS_P0HI3Q_DESC_MODE \ + (BIT_MASK_P0HI3Q_DESC_MODE << BIT_SHIFT_P0HI3Q_DESC_MODE) +#define BIT_CLEAR_P0HI3Q_DESC_MODE(x) ((x) & (~BITS_P0HI3Q_DESC_MODE)) +#define BIT_GET_P0HI3Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_DESC_MODE) & BIT_MASK_P0HI3Q_DESC_MODE) +#define BIT_SET_P0HI3Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI3Q_DESC_MODE(x) | BIT_P0HI3Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI3Q_DESC_NUM 16 +#define BIT_MASK_P0HI3Q_DESC_NUM 0xfff +#define BIT_P0HI3Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI3Q_DESC_NUM) << BIT_SHIFT_P0HI3Q_DESC_NUM) +#define BITS_P0HI3Q_DESC_NUM \ + (BIT_MASK_P0HI3Q_DESC_NUM << BIT_SHIFT_P0HI3Q_DESC_NUM) +#define BIT_CLEAR_P0HI3Q_DESC_NUM(x) ((x) & (~BITS_P0HI3Q_DESC_NUM)) +#define BIT_GET_P0HI3Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_DESC_NUM) & BIT_MASK_P0HI3Q_DESC_NUM) +#define BIT_SET_P0HI3Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI3Q_DESC_NUM(x) | BIT_P0HI3Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ -#define BIT_BCN0DOK BIT(16) -#define BIT_BCN0DOKM BIT(16) +#define BIT_HI2Q_FLAG BIT(14) -#define BIT_SHIFT_RX_STATE 16 -#define BIT_MASK_RX_STATE 0x7 -#define BIT_RX_STATE(x) (((x) & BIT_MASK_RX_STATE) << BIT_SHIFT_RX_STATE) -#define BIT_GET_RX_STATE(x) (((x) >> BIT_SHIFT_RX_STATE) & BIT_MASK_RX_STATE) +#endif -#define BIT_SRST_TX BIT(15) -#define BIT_M7DOK BIT(15) -#define BIT_M7DOKM BIT(15) -#define BIT_TDE_NO_IDLE BIT(15) -#define BIT_SRST_RX BIT(14) -#define BIT_M6DOK BIT(14) -#define BIT_M6DOKM BIT(14) -#define BIT_TXDMA_STUCK BIT(14) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */ +#define BIT_P0HI2Q_FLAG BIT(14) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ -#define BIT_CLR_HI7Q_HOST_IDX BIT(13) +#define BIT_SHIFT_HI2Q_DESC_MODE 12 +#define BIT_MASK_HI2Q_DESC_MODE 0x3 +#define BIT_HI2Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI2Q_DESC_MODE) << BIT_SHIFT_HI2Q_DESC_MODE) +#define BITS_HI2Q_DESC_MODE \ + (BIT_MASK_HI2Q_DESC_MODE << BIT_SHIFT_HI2Q_DESC_MODE) +#define BIT_CLEAR_HI2Q_DESC_MODE(x) ((x) & (~BITS_HI2Q_DESC_MODE)) +#define BIT_GET_HI2Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_MODE) & BIT_MASK_HI2Q_DESC_MODE) +#define BIT_SET_HI2Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI2Q_DESC_MODE(x) | BIT_HI2Q_DESC_MODE(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */ +#define BIT_SHIFT_P0HI2Q_DESC_MODE 12 +#define BIT_MASK_P0HI2Q_DESC_MODE 0x3 +#define BIT_P0HI2Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI2Q_DESC_MODE) << BIT_SHIFT_P0HI2Q_DESC_MODE) +#define BITS_P0HI2Q_DESC_MODE \ + (BIT_MASK_P0HI2Q_DESC_MODE << BIT_SHIFT_P0HI2Q_DESC_MODE) +#define BIT_CLEAR_P0HI2Q_DESC_MODE(x) ((x) & (~BITS_P0HI2Q_DESC_MODE)) +#define BIT_GET_P0HI2Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_DESC_MODE) & BIT_MASK_P0HI2Q_DESC_MODE) +#define BIT_SET_P0HI2Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI2Q_DESC_MODE(x) | BIT_P0HI2Q_DESC_MODE(v)) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_M5DOK BIT(13) -#define BIT_M5DOKM BIT(13) -#define BIT_TDE_FULL_ERR BIT(13) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ +#define BIT_SHIFT_HI2Q_DESC_NUM 0 +#define BIT_MASK_HI2Q_DESC_NUM 0xfff +#define BIT_HI2Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI2Q_DESC_NUM) << BIT_SHIFT_HI2Q_DESC_NUM) +#define BITS_HI2Q_DESC_NUM (BIT_MASK_HI2Q_DESC_NUM << BIT_SHIFT_HI2Q_DESC_NUM) +#define BIT_CLEAR_HI2Q_DESC_NUM(x) ((x) & (~BITS_HI2Q_DESC_NUM)) +#define BIT_GET_HI2Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_NUM) & BIT_MASK_HI2Q_DESC_NUM) +#define BIT_SET_HI2Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI2Q_DESC_NUM(x) | BIT_HI2Q_DESC_NUM(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */ -#define BIT_CLR_HI6Q_HOST_IDX BIT(12) +#define BIT_SHIFT_P0HI2Q_DESC_NUM 0 +#define BIT_MASK_P0HI2Q_DESC_NUM 0xfff +#define BIT_P0HI2Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI2Q_DESC_NUM) << BIT_SHIFT_P0HI2Q_DESC_NUM) +#define BITS_P0HI2Q_DESC_NUM \ + (BIT_MASK_P0HI2Q_DESC_NUM << BIT_SHIFT_P0HI2Q_DESC_NUM) +#define BIT_CLEAR_P0HI2Q_DESC_NUM(x) ((x) & (~BITS_P0HI2Q_DESC_NUM)) +#define BIT_GET_P0HI2Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_DESC_NUM) & BIT_MASK_P0HI2Q_DESC_NUM) +#define BIT_SET_P0HI2Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI2Q_DESC_NUM(x) | BIT_P0HI2Q_DESC_NUM(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_HI3Q_TXBD_NUM (Offset 0x0392) */ +#define BIT_HI3Q_FLAG BIT(14) + +#define BIT_SHIFT_HI3Q_DESC_MODE 12 +#define BIT_MASK_HI3Q_DESC_MODE 0x3 +#define BIT_HI3Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI3Q_DESC_MODE) << BIT_SHIFT_HI3Q_DESC_MODE) +#define BITS_HI3Q_DESC_MODE \ + (BIT_MASK_HI3Q_DESC_MODE << BIT_SHIFT_HI3Q_DESC_MODE) +#define BIT_CLEAR_HI3Q_DESC_MODE(x) ((x) & (~BITS_HI3Q_DESC_MODE)) +#define BIT_GET_HI3Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_MODE) & BIT_MASK_HI3Q_DESC_MODE) +#define BIT_SET_HI3Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI3Q_DESC_MODE(x) | BIT_HI3Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI3Q_DESC_NUM 0 +#define BIT_MASK_HI3Q_DESC_NUM 0xfff +#define BIT_HI3Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI3Q_DESC_NUM) << BIT_SHIFT_HI3Q_DESC_NUM) +#define BITS_HI3Q_DESC_NUM (BIT_MASK_HI3Q_DESC_NUM << BIT_SHIFT_HI3Q_DESC_NUM) +#define BIT_CLEAR_HI3Q_DESC_NUM(x) ((x) & (~BITS_HI3Q_DESC_NUM)) +#define BIT_GET_HI3Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_NUM) & BIT_MASK_HI3Q_DESC_NUM) +#define BIT_SET_HI3Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI3Q_DESC_NUM(x) | BIT_HI3Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */ + +#define BIT_P0HI5Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI5Q_DESC_MODE 28 +#define BIT_MASK_P0HI5Q_DESC_MODE 0x3 +#define BIT_P0HI5Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI5Q_DESC_MODE) << BIT_SHIFT_P0HI5Q_DESC_MODE) +#define BITS_P0HI5Q_DESC_MODE \ + (BIT_MASK_P0HI5Q_DESC_MODE << BIT_SHIFT_P0HI5Q_DESC_MODE) +#define BIT_CLEAR_P0HI5Q_DESC_MODE(x) ((x) & (~BITS_P0HI5Q_DESC_MODE)) +#define BIT_GET_P0HI5Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_DESC_MODE) & BIT_MASK_P0HI5Q_DESC_MODE) +#define BIT_SET_P0HI5Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI5Q_DESC_MODE(x) | BIT_P0HI5Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI5Q_DESC_NUM 16 +#define BIT_MASK_P0HI5Q_DESC_NUM 0xfff +#define BIT_P0HI5Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI5Q_DESC_NUM) << BIT_SHIFT_P0HI5Q_DESC_NUM) +#define BITS_P0HI5Q_DESC_NUM \ + (BIT_MASK_P0HI5Q_DESC_NUM << BIT_SHIFT_P0HI5Q_DESC_NUM) +#define BIT_CLEAR_P0HI5Q_DESC_NUM(x) ((x) & (~BITS_P0HI5Q_DESC_NUM)) +#define BIT_GET_P0HI5Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_DESC_NUM) & BIT_MASK_P0HI5Q_DESC_NUM) +#define BIT_SET_P0HI5Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI5Q_DESC_NUM(x) | BIT_P0HI5Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ -#define BIT_M4DOK BIT(12) -#define BIT_M4DOKM BIT(12) -#define BIT_HD_SIZE_ERR BIT(12) +#define BIT_HI4Q_FLAG BIT(14) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */ +#define BIT_P0HI4Q_FLAG BIT(14) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_HI5Q_HOST_IDX BIT(11) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ +#define BIT_SHIFT_HI4Q_DESC_MODE 12 +#define BIT_MASK_HI4Q_DESC_MODE 0x3 +#define BIT_HI4Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI4Q_DESC_MODE) << BIT_SHIFT_HI4Q_DESC_MODE) +#define BITS_HI4Q_DESC_MODE \ + (BIT_MASK_HI4Q_DESC_MODE << BIT_SHIFT_HI4Q_DESC_MODE) +#define BIT_CLEAR_HI4Q_DESC_MODE(x) ((x) & (~BITS_HI4Q_DESC_MODE)) +#define BIT_GET_HI4Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_MODE) & BIT_MASK_HI4Q_DESC_MODE) +#define BIT_SET_HI4Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI4Q_DESC_MODE(x) | BIT_HI4Q_DESC_MODE(v)) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */ -#define BIT_M3DOK BIT(11) -#define BIT_M3DOKM BIT(11) +#define BIT_SHIFT_P0HI4Q_DESC_MODE 12 +#define BIT_MASK_P0HI4Q_DESC_MODE 0x3 +#define BIT_P0HI4Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI4Q_DESC_MODE) << BIT_SHIFT_P0HI4Q_DESC_MODE) +#define BITS_P0HI4Q_DESC_MODE \ + (BIT_MASK_P0HI4Q_DESC_MODE << BIT_SHIFT_P0HI4Q_DESC_MODE) +#define BIT_CLEAR_P0HI4Q_DESC_MODE(x) ((x) & (~BITS_P0HI4Q_DESC_MODE)) +#define BIT_GET_P0HI4Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_DESC_MODE) & BIT_MASK_P0HI4Q_DESC_MODE) +#define BIT_SET_P0HI4Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI4Q_DESC_MODE(x) | BIT_P0HI4Q_DESC_MODE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ +#define BIT_SHIFT_HI4Q_DESC_NUM 0 +#define BIT_MASK_HI4Q_DESC_NUM 0xfff +#define BIT_HI4Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI4Q_DESC_NUM) << BIT_SHIFT_HI4Q_DESC_NUM) +#define BITS_HI4Q_DESC_NUM (BIT_MASK_HI4Q_DESC_NUM << BIT_SHIFT_HI4Q_DESC_NUM) +#define BIT_CLEAR_HI4Q_DESC_NUM(x) ((x) & (~BITS_HI4Q_DESC_NUM)) +#define BIT_GET_HI4Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_NUM) & BIT_MASK_HI4Q_DESC_NUM) +#define BIT_SET_HI4Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI4Q_DESC_NUM(x) | BIT_HI4Q_DESC_NUM(v)) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_HI4Q_HOST_IDX BIT(10) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */ +#define BIT_SHIFT_P0HI4Q_DESC_NUM 0 +#define BIT_MASK_P0HI4Q_DESC_NUM 0xfff +#define BIT_P0HI4Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI4Q_DESC_NUM) << BIT_SHIFT_P0HI4Q_DESC_NUM) +#define BITS_P0HI4Q_DESC_NUM \ + (BIT_MASK_P0HI4Q_DESC_NUM << BIT_SHIFT_P0HI4Q_DESC_NUM) +#define BIT_CLEAR_P0HI4Q_DESC_NUM(x) ((x) & (~BITS_P0HI4Q_DESC_NUM)) +#define BIT_GET_P0HI4Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_DESC_NUM) & BIT_MASK_P0HI4Q_DESC_NUM) +#define BIT_SET_P0HI4Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI4Q_DESC_NUM(x) | BIT_P0HI4Q_DESC_NUM(v)) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_HI5Q_TXBD_NUM (Offset 0x0396) */ -#define BIT_M2DOK BIT(10) -#define BIT_M2DOKM BIT(10) +#define BIT_HI5Q_FLAG BIT(14) + +#define BIT_SHIFT_HI5Q_DESC_MODE 12 +#define BIT_MASK_HI5Q_DESC_MODE 0x3 +#define BIT_HI5Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI5Q_DESC_MODE) << BIT_SHIFT_HI5Q_DESC_MODE) +#define BITS_HI5Q_DESC_MODE \ + (BIT_MASK_HI5Q_DESC_MODE << BIT_SHIFT_HI5Q_DESC_MODE) +#define BIT_CLEAR_HI5Q_DESC_MODE(x) ((x) & (~BITS_HI5Q_DESC_MODE)) +#define BIT_GET_HI5Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_MODE) & BIT_MASK_HI5Q_DESC_MODE) +#define BIT_SET_HI5Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI5Q_DESC_MODE(x) | BIT_HI5Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI5Q_DESC_NUM 0 +#define BIT_MASK_HI5Q_DESC_NUM 0xfff +#define BIT_HI5Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI5Q_DESC_NUM) << BIT_SHIFT_HI5Q_DESC_NUM) +#define BITS_HI5Q_DESC_NUM (BIT_MASK_HI5Q_DESC_NUM << BIT_SHIFT_HI5Q_DESC_NUM) +#define BIT_CLEAR_HI5Q_DESC_NUM(x) ((x) & (~BITS_HI5Q_DESC_NUM)) +#define BIT_GET_HI5Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_NUM) & BIT_MASK_HI5Q_DESC_NUM) +#define BIT_SET_HI5Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI5Q_DESC_NUM(x) | BIT_HI5Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */ + +#define BIT_P0HI7Q_FLAG BIT(30) +#define BIT_CLR_FWCMDQ_HW_IDX BIT(30) +#define BIT_CLR_P0HI7Q_HW_IDX BIT(29) + +#define BIT_SHIFT_P0HI7Q_DESC_MODE 28 +#define BIT_MASK_P0HI7Q_DESC_MODE 0x3 +#define BIT_P0HI7Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI7Q_DESC_MODE) << BIT_SHIFT_P0HI7Q_DESC_MODE) +#define BITS_P0HI7Q_DESC_MODE \ + (BIT_MASK_P0HI7Q_DESC_MODE << BIT_SHIFT_P0HI7Q_DESC_MODE) +#define BIT_CLEAR_P0HI7Q_DESC_MODE(x) ((x) & (~BITS_P0HI7Q_DESC_MODE)) +#define BIT_GET_P0HI7Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_DESC_MODE) & BIT_MASK_P0HI7Q_DESC_MODE) +#define BIT_SET_P0HI7Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI7Q_DESC_MODE(x) | BIT_P0HI7Q_DESC_MODE(v)) + +#define BIT_CLR_P0HI6Q_HW_IDX BIT(28) +#define BIT_CLR_P0HI5Q_HW_IDX BIT(27) +#define BIT_CLR_P0HI4Q_HW_IDX BIT(26) +#define BIT_CLR_P0HI3Q_HW_IDX BIT(25) +#define BIT_CLR_P0HI2Q_HW_IDX BIT(24) +#define BIT_CLR_P0HI1Q_HW_IDX BIT(23) +#define BIT_CLR_P0HI0Q_HW_IDX BIT(22) +#define BIT_CLR_ACH3_HW_IDX BIT(21) +#define BIT_CLR_ACH2_HW_IDX BIT(20) +#define BIT_CLR_ACH1_HW_IDX BIT(19) +#define BIT_CLR_ACH0_HW_IDX BIT(18) +#define BIT_CLR_P0MGQ_HW_IDX BIT(17) + +#define BIT_SHIFT_P0HI7Q_DESC_NUM 16 +#define BIT_MASK_P0HI7Q_DESC_NUM 0xfff +#define BIT_P0HI7Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI7Q_DESC_NUM) << BIT_SHIFT_P0HI7Q_DESC_NUM) +#define BITS_P0HI7Q_DESC_NUM \ + (BIT_MASK_P0HI7Q_DESC_NUM << BIT_SHIFT_P0HI7Q_DESC_NUM) +#define BIT_CLEAR_P0HI7Q_DESC_NUM(x) ((x) & (~BITS_P0HI7Q_DESC_NUM)) +#define BIT_GET_P0HI7Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_DESC_NUM) & BIT_MASK_P0HI7Q_DESC_NUM) +#define BIT_SET_P0HI7Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI7Q_DESC_NUM(x) | BIT_P0HI7Q_DESC_NUM(v)) + +#define BIT_CLR_P0RXQ_HW_IDX BIT(16) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ +#define BIT_HI6Q_FLAG BIT(14) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */ -#define BIT_CLR_HI3Q_HOST_IDX BIT(9) +#define BIT_P0HI6Q_FLAG BIT(14) +#define BIT_CLR_PFWCMDQ_HOST_IDX BIT(14) +#define BIT_CLR_P0HI7Q_HOST_IDX BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ +#define BIT_SHIFT_HI6Q_DESC_MODE 12 +#define BIT_MASK_HI6Q_DESC_MODE 0x3 +#define BIT_HI6Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI6Q_DESC_MODE) << BIT_SHIFT_HI6Q_DESC_MODE) +#define BITS_HI6Q_DESC_MODE \ + (BIT_MASK_HI6Q_DESC_MODE << BIT_SHIFT_HI6Q_DESC_MODE) +#define BIT_CLEAR_HI6Q_DESC_MODE(x) ((x) & (~BITS_HI6Q_DESC_MODE)) +#define BIT_GET_HI6Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_MODE) & BIT_MASK_HI6Q_DESC_MODE) +#define BIT_SET_HI6Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI6Q_DESC_MODE(x) | BIT_HI6Q_DESC_MODE(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */ + +#define BIT_SHIFT_P0HI6Q_DESC_MODE 12 +#define BIT_MASK_P0HI6Q_DESC_MODE 0x3 +#define BIT_P0HI6Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI6Q_DESC_MODE) << BIT_SHIFT_P0HI6Q_DESC_MODE) +#define BITS_P0HI6Q_DESC_MODE \ + (BIT_MASK_P0HI6Q_DESC_MODE << BIT_SHIFT_P0HI6Q_DESC_MODE) +#define BIT_CLEAR_P0HI6Q_DESC_MODE(x) ((x) & (~BITS_P0HI6Q_DESC_MODE)) +#define BIT_GET_P0HI6Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_DESC_MODE) & BIT_MASK_P0HI6Q_DESC_MODE) +#define BIT_SET_P0HI6Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI6Q_DESC_MODE(x) | BIT_P0HI6Q_DESC_MODE(v)) + +#define BIT_CLR_P0HI6Q_HOST_IDX BIT(12) +#define BIT_CLR_P0HI5Q_HOST_IDX BIT(11) +#define BIT_CLR_P0HI4Q_HOST_IDX BIT(10) +#define BIT_CLR_P0HI3Q_HOST_IDX BIT(9) +#define BIT_CLR_P0HI2Q_HOST_IDX BIT(8) +#define BIT_CLR_P0HI1Q_HOST_IDX BIT(7) +#define BIT_CLR_P0HI0Q_HOST_IDX BIT(6) +#define BIT_CLR_ACH3_HOST_IDX BIT(5) +#define BIT_CLR_ACH2_HOST_IDX BIT(4) +#define BIT_CLR_ACH1_HOST_IDX BIT(3) +#define BIT_CLR_ACH0_HOST_IDX BIT(2) +#define BIT_CLR_P0MGQ_HOST_IDX BIT(1) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ -#define BIT_M1DOK BIT(9) -#define BIT_M1DOKM BIT(9) +#define BIT_SHIFT_HI6Q_DESC_NUM 0 +#define BIT_MASK_HI6Q_DESC_NUM 0xfff +#define BIT_HI6Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI6Q_DESC_NUM) << BIT_SHIFT_HI6Q_DESC_NUM) +#define BITS_HI6Q_DESC_NUM (BIT_MASK_HI6Q_DESC_NUM << BIT_SHIFT_HI6Q_DESC_NUM) +#define BIT_CLEAR_HI6Q_DESC_NUM(x) ((x) & (~BITS_HI6Q_DESC_NUM)) +#define BIT_GET_HI6Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_NUM) & BIT_MASK_HI6Q_DESC_NUM) +#define BIT_SET_HI6Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI6Q_DESC_NUM(x) | BIT_HI6Q_DESC_NUM(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */ -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_SHIFT_P0HI6Q_DESC_NUM 0 +#define BIT_MASK_P0HI6Q_DESC_NUM 0xfff +#define BIT_P0HI6Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI6Q_DESC_NUM) << BIT_SHIFT_P0HI6Q_DESC_NUM) +#define BITS_P0HI6Q_DESC_NUM \ + (BIT_MASK_P0HI6Q_DESC_NUM << BIT_SHIFT_P0HI6Q_DESC_NUM) +#define BIT_CLEAR_P0HI6Q_DESC_NUM(x) ((x) & (~BITS_P0HI6Q_DESC_NUM)) +#define BIT_GET_P0HI6Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_DESC_NUM) & BIT_MASK_P0HI6Q_DESC_NUM) +#define BIT_SET_P0HI6Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI6Q_DESC_NUM(x) | BIT_P0HI6Q_DESC_NUM(v)) -#define BIT_CLR_HI2Q_HOST_IDX BIT(8) +#define BIT_CLR_P0RXQ_HOST_IDX BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_HI7Q_TXBD_NUM (Offset 0x039A) */ +#define BIT_HI7Q_FLAG BIT(14) + +#define BIT_SHIFT_HI7Q_DESC_MODE 12 +#define BIT_MASK_HI7Q_DESC_MODE 0x3 +#define BIT_HI7Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI7Q_DESC_MODE) << BIT_SHIFT_HI7Q_DESC_MODE) +#define BITS_HI7Q_DESC_MODE \ + (BIT_MASK_HI7Q_DESC_MODE << BIT_SHIFT_HI7Q_DESC_MODE) +#define BIT_CLEAR_HI7Q_DESC_MODE(x) ((x) & (~BITS_HI7Q_DESC_MODE)) +#define BIT_GET_HI7Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_MODE) & BIT_MASK_HI7Q_DESC_MODE) +#define BIT_SET_HI7Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI7Q_DESC_MODE(x) | BIT_HI7Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI7Q_DESC_NUM 0 +#define BIT_MASK_HI7Q_DESC_NUM 0xfff +#define BIT_HI7Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI7Q_DESC_NUM) << BIT_SHIFT_HI7Q_DESC_NUM) +#define BITS_HI7Q_DESC_NUM (BIT_MASK_HI7Q_DESC_NUM << BIT_SHIFT_HI7Q_DESC_NUM) +#define BIT_CLEAR_HI7Q_DESC_NUM(x) ((x) & (~BITS_HI7Q_DESC_NUM)) +#define BIT_GET_HI7Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_NUM) & BIT_MASK_HI7Q_DESC_NUM) +#define BIT_SET_HI7Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI7Q_DESC_NUM(x) | BIT_HI7Q_DESC_NUM(v)) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_M0DOK BIT(8) -#define BIT_M0DOKM BIT(8) +#define BIT_CLR_HI7Q_HW_IDX BIT(29) +#define BIT_CLR_HI6Q_HW_IDX BIT(28) +#define BIT_CLR_HI5Q_HW_IDX BIT(27) +#define BIT_CLR_HI4Q_HW_IDX BIT(26) +#define BIT_CLR_HI3Q_HW_IDX BIT(25) +#define BIT_CLR_HI2Q_HW_IDX BIT(24) +#define BIT_CLR_HI1Q_HW_IDX BIT(23) -#define BIT_SHIFT_TX_STATE 8 -#define BIT_MASK_TX_STATE 0xf -#define BIT_TX_STATE(x) (((x) & BIT_MASK_TX_STATE) << BIT_SHIFT_TX_STATE) -#define BIT_GET_TX_STATE(x) (((x) >> BIT_SHIFT_TX_STATE) & BIT_MASK_TX_STATE) +#endif +#if (HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_BCN7DOK BIT(23) +#define BIT_BCN7DOKM BIT(23) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_CLR_HI1Q_HOST_IDX BIT(7) -#define BIT_CLR_HI0Q_HOST_IDX BIT(6) +#define BIT_CLR_HI0Q_HW_IDX BIT(22) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_MGQDOK BIT(6) -#define BIT_MGQDOKM BIT(6) +#define BIT_BCN6DOK BIT(22) +#define BIT_BCN6DOKM BIT(22) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_CLR_BKQ_HOST_IDX BIT(5) +#define BIT_CLR_BKQ_HW_IDX BIT(21) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_BKQDOK BIT(5) -#define BIT_BKQDOKM BIT(5) +#define BIT_BCN5DOK BIT(21) +#define BIT_BCN5DOKM BIT(21) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_CLR_BEQ_HOST_IDX BIT(4) +#define BIT_CLR_BEQ_HW_IDX BIT(20) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ - -#define BIT_SHIFT_HPS_CLKR 4 -#define BIT_MASK_HPS_CLKR 0x3 -#define BIT_HPS_CLKR(x) (((x) & BIT_MASK_HPS_CLKR) << BIT_SHIFT_HPS_CLKR) -#define BIT_GET_HPS_CLKR(x) (((x) >> BIT_SHIFT_HPS_CLKR) & BIT_MASK_HPS_CLKR) - -#define BIT_BEQDOK BIT(4) -#define BIT_BEQDOKM BIT(4) +#define BIT_BCN4DOK BIT(20) +#define BIT_BCN4DOKM BIT(20) +#define BIT_RX_OVER_RD_ERR BIT(20) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_CLR_VIQ_HOST_IDX BIT(3) +#define BIT_CLR_VIQ_HW_IDX BIT(19) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_LX_INT BIT(3) -#define BIT_VIQDOK BIT(3) -#define BIT_VIQDOKM BIT(3) -#define BIT_MST_BUSY BIT(3) +#define BIT_BCN3DOK BIT(19) +#define BIT_BCN3DOKM BIT(19) +#define BIT_RXDMA_STUCK BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_CLR_VOQ_HOST_IDX BIT(2) +#define BIT_CLR_VOQ_HW_IDX BIT(18) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_VOQDOK BIT(2) -#define BIT_VOQDOKM BIT(2) -#define BIT_SLV_BUSY BIT(2) +#define BIT_BCN2DOK BIT(18) +#define BIT_BCN2DOKM BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_CLR_MGQ_HOST_IDX BIT(1) +#define BIT_CLR_MGQ_HW_IDX BIT(17) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_RDUM BIT(1) -#define BIT_RXDES_UNAVAIL BIT(1) +#define BIT_BCN1DOK BIT(17) +#define BIT_BCN1DOKM BIT(17) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ +#define BIT_SHIFT_TSFT2_HCI 16 +#define BIT_MASK_TSFT2_HCI 0xffff +#define BIT_TSFT2_HCI(x) (((x) & BIT_MASK_TSFT2_HCI) << BIT_SHIFT_TSFT2_HCI) +#define BITS_TSFT2_HCI (BIT_MASK_TSFT2_HCI << BIT_SHIFT_TSFT2_HCI) +#define BIT_CLEAR_TSFT2_HCI(x) ((x) & (~BITS_TSFT2_HCI)) +#define BIT_GET_TSFT2_HCI(x) (((x) >> BIT_SHIFT_TSFT2_HCI) & BIT_MASK_TSFT2_HCI) +#define BIT_SET_TSFT2_HCI(x, v) (BIT_CLEAR_TSFT2_HCI(x) | BIT_TSFT2_HCI(v)) -/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TSFT1_HCI 0 -#define BIT_MASK_TSFT1_HCI 0xffff -#define BIT_TSFT1_HCI(x) (((x) & BIT_MASK_TSFT1_HCI) << BIT_SHIFT_TSFT1_HCI) -#define BIT_GET_TSFT1_HCI(x) (((x) >> BIT_SHIFT_TSFT1_HCI) & BIT_MASK_TSFT1_HCI) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_CLR_RXQ_HOST_IDX BIT(0) +#define BIT_CLR_RXQ_HW_IDX BIT(16) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_RXDOK BIT(0) -#define BIT_RXDOKM BIT(0) -#define BIT_EN_DBG_STUCK BIT(0) +#define BIT_BCN0DOK BIT(16) +#define BIT_BCN0DOKM BIT(16) -#endif +#define BIT_SHIFT_RX_STATE 16 +#define BIT_MASK_RX_STATE 0x7 +#define BIT_RX_STATE(x) (((x) & BIT_MASK_RX_STATE) << BIT_SHIFT_RX_STATE) +#define BITS_RX_STATE (BIT_MASK_RX_STATE << BIT_SHIFT_RX_STATE) +#define BIT_CLEAR_RX_STATE(x) ((x) & (~BITS_RX_STATE)) +#define BIT_GET_RX_STATE(x) (((x) >> BIT_SHIFT_RX_STATE) & BIT_MASK_RX_STATE) +#define BIT_SET_RX_STATE(x, v) (BIT_CLEAR_RX_STATE(x) | BIT_RX_STATE(v)) +#define BIT_SRST_TX BIT(15) +#define BIT_M7DOK BIT(15) +#define BIT_M7DOKM BIT(15) +#define BIT_TDE_NO_IDLE BIT(15) +#define BIT_SRST_RX BIT(14) +#define BIT_M6DOK BIT(14) +#define BIT_M6DOKM BIT(14) +#define BIT_TXDMA_STUCK BIT(14) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */ +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI7Q_HOST_IDX BIT(13) -#define BIT_SHIFT_VOQ_HW_IDX 16 -#define BIT_MASK_VOQ_HW_IDX 0xfff -#define BIT_VOQ_HW_IDX(x) (((x) & BIT_MASK_VOQ_HW_IDX) << BIT_SHIFT_VOQ_HW_IDX) -#define BIT_GET_VOQ_HW_IDX(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX) & BIT_MASK_VOQ_HW_IDX) +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VOQ_HOST_IDX 0 -#define BIT_MASK_VOQ_HOST_IDX 0xfff -#define BIT_VOQ_HOST_IDX(x) (((x) & BIT_MASK_VOQ_HOST_IDX) << BIT_SHIFT_VOQ_HOST_IDX) -#define BIT_GET_VOQ_HOST_IDX(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX) & BIT_MASK_VOQ_HOST_IDX) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_M5DOK BIT(13) +#define BIT_M5DOKM BIT(13) +#define BIT_TDE_FULL_ERR BIT(13) -/* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VIQ_HW_IDX 16 -#define BIT_MASK_VIQ_HW_IDX 0xfff -#define BIT_VIQ_HW_IDX(x) (((x) & BIT_MASK_VIQ_HW_IDX) << BIT_SHIFT_VIQ_HW_IDX) -#define BIT_GET_VIQ_HW_IDX(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX) & BIT_MASK_VIQ_HW_IDX) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI6Q_HOST_IDX BIT(12) -#define BIT_SHIFT_VIQ_HOST_IDX 0 -#define BIT_MASK_VIQ_HOST_IDX 0xfff -#define BIT_VIQ_HOST_IDX(x) (((x) & BIT_MASK_VIQ_HOST_IDX) << BIT_SHIFT_VIQ_HOST_IDX) -#define BIT_GET_VIQ_HOST_IDX(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX) & BIT_MASK_VIQ_HOST_IDX) +#endif +#if (HALMAC_8881A_SUPPORT) -/* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */ +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_M4DOK BIT(12) +#define BIT_M4DOKM BIT(12) +#define BIT_HD_SIZE_ERR BIT(12) -#define BIT_SHIFT_BEQ_HW_IDX 16 -#define BIT_MASK_BEQ_HW_IDX 0xfff -#define BIT_BEQ_HW_IDX(x) (((x) & BIT_MASK_BEQ_HW_IDX) << BIT_SHIFT_BEQ_HW_IDX) -#define BIT_GET_BEQ_HW_IDX(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX) & BIT_MASK_BEQ_HW_IDX) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BEQ_HOST_IDX 0 -#define BIT_MASK_BEQ_HOST_IDX 0xfff -#define BIT_BEQ_HOST_IDX(x) (((x) & BIT_MASK_BEQ_HOST_IDX) << BIT_SHIFT_BEQ_HOST_IDX) -#define BIT_GET_BEQ_HOST_IDX(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX) & BIT_MASK_BEQ_HOST_IDX) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI5Q_HOST_IDX BIT(11) -/* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BKQ_HW_IDX 16 -#define BIT_MASK_BKQ_HW_IDX 0xfff -#define BIT_BKQ_HW_IDX(x) (((x) & BIT_MASK_BKQ_HW_IDX) << BIT_SHIFT_BKQ_HW_IDX) -#define BIT_GET_BKQ_HW_IDX(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX) & BIT_MASK_BKQ_HW_IDX) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_M3DOK BIT(11) +#define BIT_M3DOKM BIT(11) -#define BIT_SHIFT_BKQ_HOST_IDX 0 -#define BIT_MASK_BKQ_HOST_IDX 0xfff -#define BIT_BKQ_HOST_IDX(x) (((x) & BIT_MASK_BKQ_HOST_IDX) << BIT_SHIFT_BKQ_HOST_IDX) -#define BIT_GET_BKQ_HOST_IDX(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX) & BIT_MASK_BKQ_HOST_IDX) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */ +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI4Q_HOST_IDX BIT(10) -#define BIT_SHIFT_MGQ_HW_IDX 16 -#define BIT_MASK_MGQ_HW_IDX 0xfff -#define BIT_MGQ_HW_IDX(x) (((x) & BIT_MASK_MGQ_HW_IDX) << BIT_SHIFT_MGQ_HW_IDX) -#define BIT_GET_MGQ_HW_IDX(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX) & BIT_MASK_MGQ_HW_IDX) +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MGQ_HOST_IDX 0 -#define BIT_MASK_MGQ_HOST_IDX 0xfff -#define BIT_MGQ_HOST_IDX(x) (((x) & BIT_MASK_MGQ_HOST_IDX) << BIT_SHIFT_MGQ_HOST_IDX) -#define BIT_GET_MGQ_HOST_IDX(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX) & BIT_MASK_MGQ_HOST_IDX) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_M2DOK BIT(10) +#define BIT_M2DOKM BIT(10) -/* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RXQ_HW_IDX 16 -#define BIT_MASK_RXQ_HW_IDX 0xfff -#define BIT_RXQ_HW_IDX(x) (((x) & BIT_MASK_RXQ_HW_IDX) << BIT_SHIFT_RXQ_HW_IDX) -#define BIT_GET_RXQ_HW_IDX(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX) & BIT_MASK_RXQ_HW_IDX) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI3Q_HOST_IDX BIT(9) -#define BIT_SHIFT_RXQ_HOST_IDX 0 -#define BIT_MASK_RXQ_HOST_IDX 0xfff -#define BIT_RXQ_HOST_IDX(x) (((x) & BIT_MASK_RXQ_HOST_IDX) << BIT_SHIFT_RXQ_HOST_IDX) -#define BIT_GET_RXQ_HOST_IDX(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX) & BIT_MASK_RXQ_HOST_IDX) +#endif +#if (HALMAC_8881A_SUPPORT) -/* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */ +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_M1DOK BIT(9) +#define BIT_M1DOKM BIT(9) -#define BIT_SHIFT_HI0Q_HW_IDX 16 -#define BIT_MASK_HI0Q_HW_IDX 0xfff -#define BIT_HI0Q_HW_IDX(x) (((x) & BIT_MASK_HI0Q_HW_IDX) << BIT_SHIFT_HI0Q_HW_IDX) -#define BIT_GET_HI0Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX) & BIT_MASK_HI0Q_HW_IDX) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HI0Q_HOST_IDX 0 -#define BIT_MASK_HI0Q_HOST_IDX 0xfff -#define BIT_HI0Q_HOST_IDX(x) (((x) & BIT_MASK_HI0Q_HOST_IDX) << BIT_SHIFT_HI0Q_HOST_IDX) -#define BIT_GET_HI0Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX) & BIT_MASK_HI0Q_HOST_IDX) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI2Q_HOST_IDX BIT(8) -/* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HI1Q_HW_IDX 16 -#define BIT_MASK_HI1Q_HW_IDX 0xfff -#define BIT_HI1Q_HW_IDX(x) (((x) & BIT_MASK_HI1Q_HW_IDX) << BIT_SHIFT_HI1Q_HW_IDX) -#define BIT_GET_HI1Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX) & BIT_MASK_HI1Q_HW_IDX) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_M0DOK BIT(8) +#define BIT_M0DOKM BIT(8) -#define BIT_SHIFT_HI1Q_HOST_IDX 0 -#define BIT_MASK_HI1Q_HOST_IDX 0xfff -#define BIT_HI1Q_HOST_IDX(x) (((x) & BIT_MASK_HI1Q_HOST_IDX) << BIT_SHIFT_HI1Q_HOST_IDX) -#define BIT_GET_HI1Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX) & BIT_MASK_HI1Q_HOST_IDX) +#define BIT_SHIFT_TX_STATE 8 +#define BIT_MASK_TX_STATE 0xf +#define BIT_TX_STATE(x) (((x) & BIT_MASK_TX_STATE) << BIT_SHIFT_TX_STATE) +#define BITS_TX_STATE (BIT_MASK_TX_STATE << BIT_SHIFT_TX_STATE) +#define BIT_CLEAR_TX_STATE(x) ((x) & (~BITS_TX_STATE)) +#define BIT_GET_TX_STATE(x) (((x) >> BIT_SHIFT_TX_STATE) & BIT_MASK_TX_STATE) +#define BIT_SET_TX_STATE(x, v) (BIT_CLEAR_TX_STATE(x) | BIT_TX_STATE(v)) +#endif -/* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_SHIFT_HI2Q_HW_IDX 16 -#define BIT_MASK_HI2Q_HW_IDX 0xfff -#define BIT_HI2Q_HW_IDX(x) (((x) & BIT_MASK_HI2Q_HW_IDX) << BIT_SHIFT_HI2Q_HW_IDX) -#define BIT_GET_HI2Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX) & BIT_MASK_HI2Q_HW_IDX) +#define BIT_CLR_HI1Q_HOST_IDX BIT(7) +#define BIT_CLR_HI0Q_HOST_IDX BIT(6) +#endif -#define BIT_SHIFT_HI2Q_HOST_IDX 0 -#define BIT_MASK_HI2Q_HOST_IDX 0xfff -#define BIT_HI2Q_HOST_IDX(x) (((x) & BIT_MASK_HI2Q_HOST_IDX) << BIT_SHIFT_HI2Q_HOST_IDX) -#define BIT_GET_HI2Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX) & BIT_MASK_HI2Q_HOST_IDX) +#if (HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -/* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */ +#define BIT_MGQDOK BIT(6) +#define BIT_MGQDOKM BIT(6) +#endif -#define BIT_SHIFT_HI3Q_HW_IDX 16 -#define BIT_MASK_HI3Q_HW_IDX 0xfff -#define BIT_HI3Q_HW_IDX(x) (((x) & BIT_MASK_HI3Q_HW_IDX) << BIT_SHIFT_HI3Q_HW_IDX) -#define BIT_GET_HI3Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX) & BIT_MASK_HI3Q_HW_IDX) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_SHIFT_HI3Q_HOST_IDX 0 -#define BIT_MASK_HI3Q_HOST_IDX 0xfff -#define BIT_HI3Q_HOST_IDX(x) (((x) & BIT_MASK_HI3Q_HOST_IDX) << BIT_SHIFT_HI3Q_HOST_IDX) -#define BIT_GET_HI3Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX) & BIT_MASK_HI3Q_HOST_IDX) +#define BIT_CLR_BKQ_HOST_IDX BIT(5) +#endif -/* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */ +#if (HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_SHIFT_HI4Q_HW_IDX 16 -#define BIT_MASK_HI4Q_HW_IDX 0xfff -#define BIT_HI4Q_HW_IDX(x) (((x) & BIT_MASK_HI4Q_HW_IDX) << BIT_SHIFT_HI4Q_HW_IDX) -#define BIT_GET_HI4Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX) & BIT_MASK_HI4Q_HW_IDX) +#define BIT_BKQDOK BIT(5) +#define BIT_BKQDOKM BIT(5) +#endif -#define BIT_SHIFT_HI4Q_HOST_IDX 0 -#define BIT_MASK_HI4Q_HOST_IDX 0xfff -#define BIT_HI4Q_HOST_IDX(x) (((x) & BIT_MASK_HI4Q_HOST_IDX) << BIT_SHIFT_HI4Q_HOST_IDX) -#define BIT_GET_HI4Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX) & BIT_MASK_HI4Q_HOST_IDX) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -/* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */ +#define BIT_CLR_BEQ_HOST_IDX BIT(4) +#endif -#define BIT_SHIFT_HI5Q_HW_IDX 16 -#define BIT_MASK_HI5Q_HW_IDX 0xfff -#define BIT_HI5Q_HW_IDX(x) (((x) & BIT_MASK_HI5Q_HW_IDX) << BIT_SHIFT_HI5Q_HW_IDX) -#define BIT_GET_HI5Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX) & BIT_MASK_HI5Q_HW_IDX) +#if (HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_SHIFT_HI5Q_HOST_IDX 0 -#define BIT_MASK_HI5Q_HOST_IDX 0xfff -#define BIT_HI5Q_HOST_IDX(x) (((x) & BIT_MASK_HI5Q_HOST_IDX) << BIT_SHIFT_HI5Q_HOST_IDX) -#define BIT_GET_HI5Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX) & BIT_MASK_HI5Q_HOST_IDX) +#define BIT_SHIFT_HPS_CLKR 4 +#define BIT_MASK_HPS_CLKR 0x3 +#define BIT_HPS_CLKR(x) (((x) & BIT_MASK_HPS_CLKR) << BIT_SHIFT_HPS_CLKR) +#define BITS_HPS_CLKR (BIT_MASK_HPS_CLKR << BIT_SHIFT_HPS_CLKR) +#define BIT_CLEAR_HPS_CLKR(x) ((x) & (~BITS_HPS_CLKR)) +#define BIT_GET_HPS_CLKR(x) (((x) >> BIT_SHIFT_HPS_CLKR) & BIT_MASK_HPS_CLKR) +#define BIT_SET_HPS_CLKR(x, v) (BIT_CLEAR_HPS_CLKR(x) | BIT_HPS_CLKR(v)) +#define BIT_BEQDOK BIT(4) +#define BIT_BEQDOKM BIT(4) -/* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HI6Q_HW_IDX 16 -#define BIT_MASK_HI6Q_HW_IDX 0xfff -#define BIT_HI6Q_HW_IDX(x) (((x) & BIT_MASK_HI6Q_HW_IDX) << BIT_SHIFT_HI6Q_HW_IDX) -#define BIT_GET_HI6Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX) & BIT_MASK_HI6Q_HW_IDX) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_VIQ_HOST_IDX BIT(3) -#define BIT_SHIFT_HI6Q_HOST_IDX 0 -#define BIT_MASK_HI6Q_HOST_IDX 0xfff -#define BIT_HI6Q_HOST_IDX(x) (((x) & BIT_MASK_HI6Q_HOST_IDX) << BIT_SHIFT_HI6Q_HOST_IDX) -#define BIT_GET_HI6Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX) & BIT_MASK_HI6Q_HOST_IDX) +#endif +#if (HALMAC_8881A_SUPPORT) -/* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */ +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_LX_INT BIT(3) +#define BIT_VIQDOK BIT(3) +#define BIT_VIQDOKM BIT(3) +#define BIT_MST_BUSY BIT(3) -#define BIT_SHIFT_HI7Q_HW_IDX 16 -#define BIT_MASK_HI7Q_HW_IDX 0xfff -#define BIT_HI7Q_HW_IDX(x) (((x) & BIT_MASK_HI7Q_HW_IDX) << BIT_SHIFT_HI7Q_HW_IDX) -#define BIT_GET_HI7Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX) & BIT_MASK_HI7Q_HW_IDX) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HI7Q_HOST_IDX 0 -#define BIT_MASK_HI7Q_HOST_IDX 0xfff -#define BIT_HI7Q_HOST_IDX(x) (((x) & BIT_MASK_HI7Q_HOST_IDX) << BIT_SHIFT_HI7Q_HOST_IDX) -#define BIT_GET_HI7Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX) & BIT_MASK_HI7Q_HOST_IDX) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_VOQ_HOST_IDX BIT(2) #endif +#if (HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_VOQDOK BIT(2) +#define BIT_VOQDOKM BIT(2) +#define BIT_SLV_BUSY BIT(2) -/* 2 REG_DBG_SEL_V1 (Offset 0x03D8) */ +#endif -#define BIT_DIS_TXDMA_PRE BIT(7) -#define BIT_DIS_RXDMA_PRE BIT(6) -#define BIT_TXFLAG_EXIT_L1_EN BIT(2) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DBG_SEL 0 -#define BIT_MASK_DBG_SEL 0xff -#define BIT_DBG_SEL(x) (((x) & BIT_MASK_DBG_SEL) << BIT_SHIFT_DBG_SEL) -#define BIT_GET_DBG_SEL(x) (((x) >> BIT_SHIFT_DBG_SEL) & BIT_MASK_DBG_SEL) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_MGQ_HOST_IDX BIT(1) #endif +#if (HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_RDUM BIT(1) +#define BIT_RXDES_UNAVAIL BIT(1) -/* 2 REG_PCIE_HRPWM1_V1 (Offset 0x03D9) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PCIE_HRPWM 0 -#define BIT_MASK_PCIE_HRPWM 0xff -#define BIT_PCIE_HRPWM(x) (((x) & BIT_MASK_PCIE_HRPWM) << BIT_SHIFT_PCIE_HRPWM) -#define BIT_GET_PCIE_HRPWM(x) (((x) >> BIT_SHIFT_PCIE_HRPWM) & BIT_MASK_PCIE_HRPWM) +/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ +#define BIT_SHIFT_TSFT1_HCI 0 +#define BIT_MASK_TSFT1_HCI 0xffff +#define BIT_TSFT1_HCI(x) (((x) & BIT_MASK_TSFT1_HCI) << BIT_SHIFT_TSFT1_HCI) +#define BITS_TSFT1_HCI (BIT_MASK_TSFT1_HCI << BIT_SHIFT_TSFT1_HCI) +#define BIT_CLEAR_TSFT1_HCI(x) ((x) & (~BITS_TSFT1_HCI)) +#define BIT_GET_TSFT1_HCI(x) (((x) >> BIT_SHIFT_TSFT1_HCI) & BIT_MASK_TSFT1_HCI) +#define BIT_SET_TSFT1_HCI(x, v) (BIT_CLEAR_TSFT1_HCI(x) | BIT_TSFT1_HCI(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_RXQ_HOST_IDX BIT(0) -/* 2 REG_HCI_HRPWM1_V1 (Offset 0x03D9) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HCI_HRPWM 0 -#define BIT_MASK_HCI_HRPWM 0xff -#define BIT_HCI_HRPWM(x) (((x) & BIT_MASK_HCI_HRPWM) << BIT_SHIFT_HCI_HRPWM) -#define BIT_GET_HCI_HRPWM(x) (((x) >> BIT_SHIFT_HCI_HRPWM) & BIT_MASK_HCI_HRPWM) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_RXDOK BIT(0) +#define BIT_RXDOKM BIT(0) +#define BIT_EN_DBG_STUCK BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */ +#define BIT_SHIFT_VOQ_HW_IDX 16 +#define BIT_MASK_VOQ_HW_IDX 0xfff +#define BIT_VOQ_HW_IDX(x) (((x) & BIT_MASK_VOQ_HW_IDX) << BIT_SHIFT_VOQ_HW_IDX) +#define BITS_VOQ_HW_IDX (BIT_MASK_VOQ_HW_IDX << BIT_SHIFT_VOQ_HW_IDX) +#define BIT_CLEAR_VOQ_HW_IDX(x) ((x) & (~BITS_VOQ_HW_IDX)) +#define BIT_GET_VOQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_VOQ_HW_IDX) & BIT_MASK_VOQ_HW_IDX) +#define BIT_SET_VOQ_HW_IDX(x, v) (BIT_CLEAR_VOQ_HW_IDX(x) | BIT_VOQ_HW_IDX(v)) -/* 2 REG_PCIE_HCPWM1_V1 (Offset 0x03DA) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_PCIE_HCPWM 0 -#define BIT_MASK_PCIE_HCPWM 0xff -#define BIT_PCIE_HCPWM(x) (((x) & BIT_MASK_PCIE_HCPWM) << BIT_SHIFT_PCIE_HCPWM) -#define BIT_GET_PCIE_HCPWM(x) (((x) >> BIT_SHIFT_PCIE_HCPWM) & BIT_MASK_PCIE_HCPWM) +/* 2 REG_ACH0_TXBD_IDX (Offset 0x03A0) */ +#define BIT_SHIFT_ACH0_HW_IDX 16 +#define BIT_MASK_ACH0_HW_IDX 0xfff +#define BIT_ACH0_HW_IDX(x) \ + (((x) & BIT_MASK_ACH0_HW_IDX) << BIT_SHIFT_ACH0_HW_IDX) +#define BITS_ACH0_HW_IDX (BIT_MASK_ACH0_HW_IDX << BIT_SHIFT_ACH0_HW_IDX) +#define BIT_CLEAR_ACH0_HW_IDX(x) ((x) & (~BITS_ACH0_HW_IDX)) +#define BIT_GET_ACH0_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH0_HW_IDX) & BIT_MASK_ACH0_HW_IDX) +#define BIT_SET_ACH0_HW_IDX(x, v) \ + (BIT_CLEAR_ACH0_HW_IDX(x) | BIT_ACH0_HW_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */ +#define BIT_SHIFT_VOQ_HOST_IDX 0 +#define BIT_MASK_VOQ_HOST_IDX 0xfff +#define BIT_VOQ_HOST_IDX(x) \ + (((x) & BIT_MASK_VOQ_HOST_IDX) << BIT_SHIFT_VOQ_HOST_IDX) +#define BITS_VOQ_HOST_IDX (BIT_MASK_VOQ_HOST_IDX << BIT_SHIFT_VOQ_HOST_IDX) +#define BIT_CLEAR_VOQ_HOST_IDX(x) ((x) & (~BITS_VOQ_HOST_IDX)) +#define BIT_GET_VOQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_VOQ_HOST_IDX) & BIT_MASK_VOQ_HOST_IDX) +#define BIT_SET_VOQ_HOST_IDX(x, v) \ + (BIT_CLEAR_VOQ_HOST_IDX(x) | BIT_VOQ_HOST_IDX(v)) -/* 2 REG_HCI_HCPWM1_V1 (Offset 0x03DA) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HCI_HCPWM 0 -#define BIT_MASK_HCI_HCPWM 0xff -#define BIT_HCI_HCPWM(x) (((x) & BIT_MASK_HCI_HCPWM) << BIT_SHIFT_HCI_HCPWM) -#define BIT_GET_HCI_HCPWM(x) (((x) >> BIT_SHIFT_HCI_HCPWM) & BIT_MASK_HCI_HCPWM) +/* 2 REG_ACH0_TXBD_IDX (Offset 0x03A0) */ +#define BIT_SHIFT_ACH0_HOST_IDX 0 +#define BIT_MASK_ACH0_HOST_IDX 0xfff +#define BIT_ACH0_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH0_HOST_IDX) << BIT_SHIFT_ACH0_HOST_IDX) +#define BITS_ACH0_HOST_IDX (BIT_MASK_ACH0_HOST_IDX << BIT_SHIFT_ACH0_HOST_IDX) +#define BIT_CLEAR_ACH0_HOST_IDX(x) ((x) & (~BITS_ACH0_HOST_IDX)) +#define BIT_GET_ACH0_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH0_HOST_IDX) & BIT_MASK_ACH0_HOST_IDX) +#define BIT_SET_ACH0_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH0_HOST_IDX(x) | BIT_ACH0_HOST_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */ +#define BIT_SHIFT_VIQ_HW_IDX 16 +#define BIT_MASK_VIQ_HW_IDX 0xfff +#define BIT_VIQ_HW_IDX(x) (((x) & BIT_MASK_VIQ_HW_IDX) << BIT_SHIFT_VIQ_HW_IDX) +#define BITS_VIQ_HW_IDX (BIT_MASK_VIQ_HW_IDX << BIT_SHIFT_VIQ_HW_IDX) +#define BIT_CLEAR_VIQ_HW_IDX(x) ((x) & (~BITS_VIQ_HW_IDX)) +#define BIT_GET_VIQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_VIQ_HW_IDX) & BIT_MASK_VIQ_HW_IDX) +#define BIT_SET_VIQ_HW_IDX(x, v) (BIT_CLEAR_VIQ_HW_IDX(x) | BIT_VIQ_HW_IDX(v)) -/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HPS_CLKR_PCIE 4 -#define BIT_MASK_HPS_CLKR_PCIE 0x3 -#define BIT_HPS_CLKR_PCIE(x) (((x) & BIT_MASK_HPS_CLKR_PCIE) << BIT_SHIFT_HPS_CLKR_PCIE) -#define BIT_GET_HPS_CLKR_PCIE(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE) & BIT_MASK_HPS_CLKR_PCIE) +/* 2 REG_ACH1_TXBD_IDX (Offset 0x03A4) */ +#define BIT_SHIFT_ACH1_HW_IDX 16 +#define BIT_MASK_ACH1_HW_IDX 0xfff +#define BIT_ACH1_HW_IDX(x) \ + (((x) & BIT_MASK_ACH1_HW_IDX) << BIT_SHIFT_ACH1_HW_IDX) +#define BITS_ACH1_HW_IDX (BIT_MASK_ACH1_HW_IDX << BIT_SHIFT_ACH1_HW_IDX) +#define BIT_CLEAR_ACH1_HW_IDX(x) ((x) & (~BITS_ACH1_HW_IDX)) +#define BIT_GET_ACH1_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH1_HW_IDX) & BIT_MASK_ACH1_HW_IDX) +#define BIT_SET_ACH1_HW_IDX(x, v) \ + (BIT_CLEAR_ACH1_HW_IDX(x) | BIT_ACH1_HW_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */ +#define BIT_SHIFT_VIQ_HOST_IDX 0 +#define BIT_MASK_VIQ_HOST_IDX 0xfff +#define BIT_VIQ_HOST_IDX(x) \ + (((x) & BIT_MASK_VIQ_HOST_IDX) << BIT_SHIFT_VIQ_HOST_IDX) +#define BITS_VIQ_HOST_IDX (BIT_MASK_VIQ_HOST_IDX << BIT_SHIFT_VIQ_HOST_IDX) +#define BIT_CLEAR_VIQ_HOST_IDX(x) ((x) & (~BITS_VIQ_HOST_IDX)) +#define BIT_GET_VIQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_VIQ_HOST_IDX) & BIT_MASK_VIQ_HOST_IDX) +#define BIT_SET_VIQ_HOST_IDX(x, v) \ + (BIT_CLEAR_VIQ_HOST_IDX(x) | BIT_VIQ_HOST_IDX(v)) -/* 2 REG_HCI_CTRL2 (Offset 0x03DB) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HPS_CLKR_HCI 4 -#define BIT_MASK_HPS_CLKR_HCI 0x3 -#define BIT_HPS_CLKR_HCI(x) (((x) & BIT_MASK_HPS_CLKR_HCI) << BIT_SHIFT_HPS_CLKR_HCI) -#define BIT_GET_HPS_CLKR_HCI(x) (((x) >> BIT_SHIFT_HPS_CLKR_HCI) & BIT_MASK_HPS_CLKR_HCI) +/* 2 REG_ACH1_TXBD_IDX (Offset 0x03A4) */ +#define BIT_SHIFT_ACH1_HOST_IDX 0 +#define BIT_MASK_ACH1_HOST_IDX 0xfff +#define BIT_ACH1_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH1_HOST_IDX) << BIT_SHIFT_ACH1_HOST_IDX) +#define BITS_ACH1_HOST_IDX (BIT_MASK_ACH1_HOST_IDX << BIT_SHIFT_ACH1_HOST_IDX) +#define BIT_CLEAR_ACH1_HOST_IDX(x) ((x) & (~BITS_ACH1_HOST_IDX)) +#define BIT_GET_ACH1_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH1_HOST_IDX) & BIT_MASK_ACH1_HOST_IDX) +#define BIT_SET_ACH1_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH1_HOST_IDX(x) | BIT_ACH1_HOST_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ +/* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */ -#define BIT_PCIE_INT BIT(3) +#define BIT_SHIFT_BEQ_HW_IDX 16 +#define BIT_MASK_BEQ_HW_IDX 0xfff +#define BIT_BEQ_HW_IDX(x) (((x) & BIT_MASK_BEQ_HW_IDX) << BIT_SHIFT_BEQ_HW_IDX) +#define BITS_BEQ_HW_IDX (BIT_MASK_BEQ_HW_IDX << BIT_SHIFT_BEQ_HW_IDX) +#define BIT_CLEAR_BEQ_HW_IDX(x) ((x) & (~BITS_BEQ_HW_IDX)) +#define BIT_GET_BEQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_BEQ_HW_IDX) & BIT_MASK_BEQ_HW_IDX) +#define BIT_SET_BEQ_HW_IDX(x, v) (BIT_CLEAR_BEQ_HW_IDX(x) | BIT_BEQ_HW_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_HCI_CTRL2 (Offset 0x03DB) */ +/* 2 REG_ACH2_TXBD_IDX (Offset 0x03A8) */ -#define BIT_HCI_INT BIT(3) +#define BIT_SHIFT_ACH2_HW_IDX 16 +#define BIT_MASK_ACH2_HW_IDX 0xfff +#define BIT_ACH2_HW_IDX(x) \ + (((x) & BIT_MASK_ACH2_HW_IDX) << BIT_SHIFT_ACH2_HW_IDX) +#define BITS_ACH2_HW_IDX (BIT_MASK_ACH2_HW_IDX << BIT_SHIFT_ACH2_HW_IDX) +#define BIT_CLEAR_ACH2_HW_IDX(x) ((x) & (~BITS_ACH2_HW_IDX)) +#define BIT_GET_ACH2_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH2_HW_IDX) & BIT_MASK_ACH2_HW_IDX) +#define BIT_SET_ACH2_HW_IDX(x, v) \ + (BIT_CLEAR_ACH2_HW_IDX(x) | BIT_ACH2_HW_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ +/* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */ -#define BIT_EN_RXDMA_ALIGN BIT(1) -#define BIT_EN_TXDMA_ALIGN BIT(0) +#define BIT_SHIFT_BEQ_HOST_IDX 0 +#define BIT_MASK_BEQ_HOST_IDX 0xfff +#define BIT_BEQ_HOST_IDX(x) \ + (((x) & BIT_MASK_BEQ_HOST_IDX) << BIT_SHIFT_BEQ_HOST_IDX) +#define BITS_BEQ_HOST_IDX (BIT_MASK_BEQ_HOST_IDX << BIT_SHIFT_BEQ_HOST_IDX) +#define BIT_CLEAR_BEQ_HOST_IDX(x) ((x) & (~BITS_BEQ_HOST_IDX)) +#define BIT_GET_BEQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_BEQ_HOST_IDX) & BIT_MASK_BEQ_HOST_IDX) +#define BIT_SET_BEQ_HOST_IDX(x, v) \ + (BIT_CLEAR_BEQ_HOST_IDX(x) | BIT_BEQ_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACH2_TXBD_IDX (Offset 0x03A8) */ +#define BIT_SHIFT_ACH2_HOST_IDX 0 +#define BIT_MASK_ACH2_HOST_IDX 0xfff +#define BIT_ACH2_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH2_HOST_IDX) << BIT_SHIFT_ACH2_HOST_IDX) +#define BITS_ACH2_HOST_IDX (BIT_MASK_ACH2_HOST_IDX << BIT_SHIFT_ACH2_HOST_IDX) +#define BIT_CLEAR_ACH2_HOST_IDX(x) ((x) & (~BITS_ACH2_HOST_IDX)) +#define BIT_GET_ACH2_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH2_HOST_IDX) & BIT_MASK_ACH2_HOST_IDX) +#define BIT_SET_ACH2_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH2_HOST_IDX(x) | BIT_ACH2_HOST_IDX(v)) -/* 2 REG_PCIE_HRPWM2_V1 (Offset 0x03DC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PCIE_HRPWM2 0 -#define BIT_MASK_PCIE_HRPWM2 0xffff -#define BIT_PCIE_HRPWM2(x) (((x) & BIT_MASK_PCIE_HRPWM2) << BIT_SHIFT_PCIE_HRPWM2) -#define BIT_GET_PCIE_HRPWM2(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2) & BIT_MASK_PCIE_HRPWM2) +/* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */ +#define BIT_SHIFT_BKQ_HW_IDX 16 +#define BIT_MASK_BKQ_HW_IDX 0xfff +#define BIT_BKQ_HW_IDX(x) (((x) & BIT_MASK_BKQ_HW_IDX) << BIT_SHIFT_BKQ_HW_IDX) +#define BITS_BKQ_HW_IDX (BIT_MASK_BKQ_HW_IDX << BIT_SHIFT_BKQ_HW_IDX) +#define BIT_CLEAR_BKQ_HW_IDX(x) ((x) & (~BITS_BKQ_HW_IDX)) +#define BIT_GET_BKQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_BKQ_HW_IDX) & BIT_MASK_BKQ_HW_IDX) +#define BIT_SET_BKQ_HW_IDX(x, v) (BIT_CLEAR_BKQ_HW_IDX(x) | BIT_BKQ_HW_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ACH3_TXBD_IDX (Offset 0x03AC) */ +#define BIT_SHIFT_ACH3_HW_IDX 16 +#define BIT_MASK_ACH3_HW_IDX 0xfff +#define BIT_ACH3_HW_IDX(x) \ + (((x) & BIT_MASK_ACH3_HW_IDX) << BIT_SHIFT_ACH3_HW_IDX) +#define BITS_ACH3_HW_IDX (BIT_MASK_ACH3_HW_IDX << BIT_SHIFT_ACH3_HW_IDX) +#define BIT_CLEAR_ACH3_HW_IDX(x) ((x) & (~BITS_ACH3_HW_IDX)) +#define BIT_GET_ACH3_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH3_HW_IDX) & BIT_MASK_ACH3_HW_IDX) +#define BIT_SET_ACH3_HW_IDX(x, v) \ + (BIT_CLEAR_ACH3_HW_IDX(x) | BIT_ACH3_HW_IDX(v)) -/* 2 REG_HCI_HRPWM2_V1 (Offset 0x03DC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HCI_HRPWM2 0 -#define BIT_MASK_HCI_HRPWM2 0xffff -#define BIT_HCI_HRPWM2(x) (((x) & BIT_MASK_HCI_HRPWM2) << BIT_SHIFT_HCI_HRPWM2) -#define BIT_GET_HCI_HRPWM2(x) (((x) >> BIT_SHIFT_HCI_HRPWM2) & BIT_MASK_HCI_HRPWM2) +/* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */ +#define BIT_SHIFT_BKQ_HOST_IDX 0 +#define BIT_MASK_BKQ_HOST_IDX 0xfff +#define BIT_BKQ_HOST_IDX(x) \ + (((x) & BIT_MASK_BKQ_HOST_IDX) << BIT_SHIFT_BKQ_HOST_IDX) +#define BITS_BKQ_HOST_IDX (BIT_MASK_BKQ_HOST_IDX << BIT_SHIFT_BKQ_HOST_IDX) +#define BIT_CLEAR_BKQ_HOST_IDX(x) ((x) & (~BITS_BKQ_HOST_IDX)) +#define BIT_GET_BKQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_BKQ_HOST_IDX) & BIT_MASK_BKQ_HOST_IDX) +#define BIT_SET_BKQ_HOST_IDX(x, v) \ + (BIT_CLEAR_BKQ_HOST_IDX(x) | BIT_BKQ_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACH3_TXBD_IDX (Offset 0x03AC) */ +#define BIT_SHIFT_ACH3_HOST_IDX 0 +#define BIT_MASK_ACH3_HOST_IDX 0xfff +#define BIT_ACH3_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH3_HOST_IDX) << BIT_SHIFT_ACH3_HOST_IDX) +#define BITS_ACH3_HOST_IDX (BIT_MASK_ACH3_HOST_IDX << BIT_SHIFT_ACH3_HOST_IDX) +#define BIT_CLEAR_ACH3_HOST_IDX(x) ((x) & (~BITS_ACH3_HOST_IDX)) +#define BIT_GET_ACH3_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH3_HOST_IDX) & BIT_MASK_ACH3_HOST_IDX) +#define BIT_SET_ACH3_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH3_HOST_IDX(x) | BIT_ACH3_HOST_IDX(v)) -/* 2 REG_PCIE_HCPWM2_V1 (Offset 0x03DE) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PCIE_HCPWM2 0 -#define BIT_MASK_PCIE_HCPWM2 0xffff -#define BIT_PCIE_HCPWM2(x) (((x) & BIT_MASK_PCIE_HCPWM2) << BIT_SHIFT_PCIE_HCPWM2) -#define BIT_GET_PCIE_HCPWM2(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2) & BIT_MASK_PCIE_HCPWM2) +/* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */ +#define BIT_SHIFT_MGQ_HW_IDX 16 +#define BIT_MASK_MGQ_HW_IDX 0xfff +#define BIT_MGQ_HW_IDX(x) (((x) & BIT_MASK_MGQ_HW_IDX) << BIT_SHIFT_MGQ_HW_IDX) +#define BITS_MGQ_HW_IDX (BIT_MASK_MGQ_HW_IDX << BIT_SHIFT_MGQ_HW_IDX) +#define BIT_CLEAR_MGQ_HW_IDX(x) ((x) & (~BITS_MGQ_HW_IDX)) +#define BIT_GET_MGQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_MGQ_HW_IDX) & BIT_MASK_MGQ_HW_IDX) +#define BIT_SET_MGQ_HW_IDX(x, v) (BIT_CLEAR_MGQ_HW_IDX(x) | BIT_MGQ_HW_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_P0MGQ_TXBD_IDX (Offset 0x03B0) */ +#define BIT_SHIFT_P0MGQ_HW_IDX 16 +#define BIT_MASK_P0MGQ_HW_IDX 0xfff +#define BIT_P0MGQ_HW_IDX(x) \ + (((x) & BIT_MASK_P0MGQ_HW_IDX) << BIT_SHIFT_P0MGQ_HW_IDX) +#define BITS_P0MGQ_HW_IDX (BIT_MASK_P0MGQ_HW_IDX << BIT_SHIFT_P0MGQ_HW_IDX) +#define BIT_CLEAR_P0MGQ_HW_IDX(x) ((x) & (~BITS_P0MGQ_HW_IDX)) +#define BIT_GET_P0MGQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0MGQ_HW_IDX) & BIT_MASK_P0MGQ_HW_IDX) +#define BIT_SET_P0MGQ_HW_IDX(x, v) \ + (BIT_CLEAR_P0MGQ_HW_IDX(x) | BIT_P0MGQ_HW_IDX(v)) -/* 2 REG_HCI_HCPWM2_V1 (Offset 0x03DE) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HCI_HCPWM2 0 -#define BIT_MASK_HCI_HCPWM2 0xffff -#define BIT_HCI_HCPWM2(x) (((x) & BIT_MASK_HCI_HCPWM2) << BIT_SHIFT_HCI_HCPWM2) -#define BIT_GET_HCI_HCPWM2(x) (((x) >> BIT_SHIFT_HCI_HCPWM2) & BIT_MASK_HCI_HCPWM2) +/* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */ +#define BIT_SHIFT_MGQ_HOST_IDX 0 +#define BIT_MASK_MGQ_HOST_IDX 0xfff +#define BIT_MGQ_HOST_IDX(x) \ + (((x) & BIT_MASK_MGQ_HOST_IDX) << BIT_SHIFT_MGQ_HOST_IDX) +#define BITS_MGQ_HOST_IDX (BIT_MASK_MGQ_HOST_IDX << BIT_SHIFT_MGQ_HOST_IDX) +#define BIT_CLEAR_MGQ_HOST_IDX(x) ((x) & (~BITS_MGQ_HOST_IDX)) +#define BIT_GET_MGQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_MGQ_HOST_IDX) & BIT_MASK_MGQ_HOST_IDX) +#define BIT_SET_MGQ_HOST_IDX(x, v) \ + (BIT_CLEAR_MGQ_HOST_IDX(x) | BIT_MGQ_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P0MGQ_TXBD_IDX (Offset 0x03B0) */ +#define BIT_SHIFT_P0MGQ_HOST_IDX 0 +#define BIT_MASK_P0MGQ_HOST_IDX 0xfff +#define BIT_P0MGQ_HOST_IDX(x) \ + (((x) & BIT_MASK_P0MGQ_HOST_IDX) << BIT_SHIFT_P0MGQ_HOST_IDX) +#define BITS_P0MGQ_HOST_IDX \ + (BIT_MASK_P0MGQ_HOST_IDX << BIT_SHIFT_P0MGQ_HOST_IDX) +#define BIT_CLEAR_P0MGQ_HOST_IDX(x) ((x) & (~BITS_P0MGQ_HOST_IDX)) +#define BIT_GET_P0MGQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0MGQ_HOST_IDX) & BIT_MASK_P0MGQ_HOST_IDX) +#define BIT_SET_P0MGQ_HOST_IDX(x, v) \ + (BIT_CLEAR_P0MGQ_HOST_IDX(x) | BIT_P0MGQ_HOST_IDX(v)) -/* 2 REG_PCIE_H2C_MSG_V1 (Offset 0x03E0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DRV2FW_INFO 0 -#define BIT_MASK_DRV2FW_INFO 0xffffffffL -#define BIT_DRV2FW_INFO(x) (((x) & BIT_MASK_DRV2FW_INFO) << BIT_SHIFT_DRV2FW_INFO) -#define BIT_GET_DRV2FW_INFO(x) (((x) >> BIT_SHIFT_DRV2FW_INFO) & BIT_MASK_DRV2FW_INFO) +/* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */ +#define BIT_SHIFT_RXQ_HW_IDX 16 +#define BIT_MASK_RXQ_HW_IDX 0xfff +#define BIT_RXQ_HW_IDX(x) (((x) & BIT_MASK_RXQ_HW_IDX) << BIT_SHIFT_RXQ_HW_IDX) +#define BITS_RXQ_HW_IDX (BIT_MASK_RXQ_HW_IDX << BIT_SHIFT_RXQ_HW_IDX) +#define BIT_CLEAR_RXQ_HW_IDX(x) ((x) & (~BITS_RXQ_HW_IDX)) +#define BIT_GET_RXQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_RXQ_HW_IDX) & BIT_MASK_RXQ_HW_IDX) +#define BIT_SET_RXQ_HW_IDX(x, v) (BIT_CLEAR_RXQ_HW_IDX(x) | BIT_RXQ_HW_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P0RXQ_RXBD_IDX (Offset 0x03B4) */ +#define BIT_SHIFT_P0RXQ_HW_IDX 16 +#define BIT_MASK_P0RXQ_HW_IDX 0xfff +#define BIT_P0RXQ_HW_IDX(x) \ + (((x) & BIT_MASK_P0RXQ_HW_IDX) << BIT_SHIFT_P0RXQ_HW_IDX) +#define BITS_P0RXQ_HW_IDX (BIT_MASK_P0RXQ_HW_IDX << BIT_SHIFT_P0RXQ_HW_IDX) +#define BIT_CLEAR_P0RXQ_HW_IDX(x) ((x) & (~BITS_P0RXQ_HW_IDX)) +#define BIT_GET_P0RXQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0RXQ_HW_IDX) & BIT_MASK_P0RXQ_HW_IDX) +#define BIT_SET_P0RXQ_HW_IDX(x, v) \ + (BIT_CLEAR_P0RXQ_HW_IDX(x) | BIT_P0RXQ_HW_IDX(v)) -/* 2 REG_PCIE_C2H_MSG_V1 (Offset 0x03E4) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HCI_PCIE_C2H_MSG 0 -#define BIT_MASK_HCI_PCIE_C2H_MSG 0xffffffffL -#define BIT_HCI_PCIE_C2H_MSG(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG) << BIT_SHIFT_HCI_PCIE_C2H_MSG) -#define BIT_GET_HCI_PCIE_C2H_MSG(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG) & BIT_MASK_HCI_PCIE_C2H_MSG) +/* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */ +#define BIT_SHIFT_RXQ_HOST_IDX 0 +#define BIT_MASK_RXQ_HOST_IDX 0xfff +#define BIT_RXQ_HOST_IDX(x) \ + (((x) & BIT_MASK_RXQ_HOST_IDX) << BIT_SHIFT_RXQ_HOST_IDX) +#define BITS_RXQ_HOST_IDX (BIT_MASK_RXQ_HOST_IDX << BIT_SHIFT_RXQ_HOST_IDX) +#define BIT_CLEAR_RXQ_HOST_IDX(x) ((x) & (~BITS_RXQ_HOST_IDX)) +#define BIT_GET_RXQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_RXQ_HOST_IDX) & BIT_MASK_RXQ_HOST_IDX) +#define BIT_SET_RXQ_HOST_IDX(x, v) \ + (BIT_CLEAR_RXQ_HOST_IDX(x) | BIT_RXQ_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_P0RXQ_RXBD_IDX (Offset 0x03B4) */ +#define BIT_SHIFT_P0RXQ_HOST_IDX 0 +#define BIT_MASK_P0RXQ_HOST_IDX 0xfff +#define BIT_P0RXQ_HOST_IDX(x) \ + (((x) & BIT_MASK_P0RXQ_HOST_IDX) << BIT_SHIFT_P0RXQ_HOST_IDX) +#define BITS_P0RXQ_HOST_IDX \ + (BIT_MASK_P0RXQ_HOST_IDX << BIT_SHIFT_P0RXQ_HOST_IDX) +#define BIT_CLEAR_P0RXQ_HOST_IDX(x) ((x) & (~BITS_P0RXQ_HOST_IDX)) +#define BIT_GET_P0RXQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0RXQ_HOST_IDX) & BIT_MASK_P0RXQ_HOST_IDX) +#define BIT_SET_P0RXQ_HOST_IDX(x, v) \ + (BIT_CLEAR_P0RXQ_HOST_IDX(x) | BIT_P0RXQ_HOST_IDX(v)) -/* 2 REG_HCI_C2H_MSG_V1 (Offset 0x03E4) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HCI_C2H_MSG 0 -#define BIT_MASK_HCI_C2H_MSG 0xffffffffL -#define BIT_HCI_C2H_MSG(x) (((x) & BIT_MASK_HCI_C2H_MSG) << BIT_SHIFT_HCI_C2H_MSG) -#define BIT_GET_HCI_C2H_MSG(x) (((x) >> BIT_SHIFT_HCI_C2H_MSG) & BIT_MASK_HCI_C2H_MSG) +/* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */ +#define BIT_SHIFT_HI0Q_HW_IDX 16 +#define BIT_MASK_HI0Q_HW_IDX 0xfff +#define BIT_HI0Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI0Q_HW_IDX) << BIT_SHIFT_HI0Q_HW_IDX) +#define BITS_HI0Q_HW_IDX (BIT_MASK_HI0Q_HW_IDX << BIT_SHIFT_HI0Q_HW_IDX) +#define BIT_CLEAR_HI0Q_HW_IDX(x) ((x) & (~BITS_HI0Q_HW_IDX)) +#define BIT_GET_HI0Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI0Q_HW_IDX) & BIT_MASK_HI0Q_HW_IDX) +#define BIT_SET_HI0Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI0Q_HW_IDX(x) | BIT_HI0Q_HW_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_P0HI0Q_TXBD_IDX (Offset 0x03B8) */ +#define BIT_SHIFT_P0HI0Q_HW_IDX 16 +#define BIT_MASK_P0HI0Q_HW_IDX 0xfff +#define BIT_P0HI0Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI0Q_HW_IDX) << BIT_SHIFT_P0HI0Q_HW_IDX) +#define BITS_P0HI0Q_HW_IDX (BIT_MASK_P0HI0Q_HW_IDX << BIT_SHIFT_P0HI0Q_HW_IDX) +#define BIT_CLEAR_P0HI0Q_HW_IDX(x) ((x) & (~BITS_P0HI0Q_HW_IDX)) +#define BIT_GET_P0HI0Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_HW_IDX) & BIT_MASK_P0HI0Q_HW_IDX) +#define BIT_SET_P0HI0Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI0Q_HW_IDX(x) | BIT_P0HI0Q_HW_IDX(v)) -/* 2 REG_DBI_WDATA_V1 (Offset 0x03E8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DBI_WDATA 0 -#define BIT_MASK_DBI_WDATA 0xffffffffL -#define BIT_DBI_WDATA(x) (((x) & BIT_MASK_DBI_WDATA) << BIT_SHIFT_DBI_WDATA) -#define BIT_GET_DBI_WDATA(x) (((x) >> BIT_SHIFT_DBI_WDATA) & BIT_MASK_DBI_WDATA) +/* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */ +#define BIT_SHIFT_HI0Q_HOST_IDX 0 +#define BIT_MASK_HI0Q_HOST_IDX 0xfff +#define BIT_HI0Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI0Q_HOST_IDX) << BIT_SHIFT_HI0Q_HOST_IDX) +#define BITS_HI0Q_HOST_IDX (BIT_MASK_HI0Q_HOST_IDX << BIT_SHIFT_HI0Q_HOST_IDX) +#define BIT_CLEAR_HI0Q_HOST_IDX(x) ((x) & (~BITS_HI0Q_HOST_IDX)) +#define BIT_GET_HI0Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI0Q_HOST_IDX) & BIT_MASK_HI0Q_HOST_IDX) +#define BIT_SET_HI0Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI0Q_HOST_IDX(x) | BIT_HI0Q_HOST_IDX(v)) -/* 2 REG_DBI_RDATA_V1 (Offset 0x03EC) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_DBI_RDATA 0 -#define BIT_MASK_DBI_RDATA 0xffffffffL -#define BIT_DBI_RDATA(x) (((x) & BIT_MASK_DBI_RDATA) << BIT_SHIFT_DBI_RDATA) -#define BIT_GET_DBI_RDATA(x) (((x) >> BIT_SHIFT_DBI_RDATA) & BIT_MASK_DBI_RDATA) +/* 2 REG_P0HI0Q_TXBD_IDX (Offset 0x03B8) */ +#define BIT_SHIFT_P0HI0Q_HOST_IDX 0 +#define BIT_MASK_P0HI0Q_HOST_IDX 0xfff +#define BIT_P0HI0Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI0Q_HOST_IDX) << BIT_SHIFT_P0HI0Q_HOST_IDX) +#define BITS_P0HI0Q_HOST_IDX \ + (BIT_MASK_P0HI0Q_HOST_IDX << BIT_SHIFT_P0HI0Q_HOST_IDX) +#define BIT_CLEAR_P0HI0Q_HOST_IDX(x) ((x) & (~BITS_P0HI0Q_HOST_IDX)) +#define BIT_GET_P0HI0Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_HOST_IDX) & BIT_MASK_P0HI0Q_HOST_IDX) +#define BIT_SET_P0HI0Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI0Q_HOST_IDX(x) | BIT_P0HI0Q_HOST_IDX(v)) -/* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */ +#endif -#define BIT_EN_STUCK_DBG BIT(26) -#define BIT_RX_STUCK BIT(25) -#define BIT_TX_STUCK BIT(24) -#define BIT_DBI_RFLAG BIT(17) -#define BIT_DBI_WFLAG BIT(16) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DBI_WREN 12 -#define BIT_MASK_DBI_WREN 0xf -#define BIT_DBI_WREN(x) (((x) & BIT_MASK_DBI_WREN) << BIT_SHIFT_DBI_WREN) -#define BIT_GET_DBI_WREN(x) (((x) >> BIT_SHIFT_DBI_WREN) & BIT_MASK_DBI_WREN) +/* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */ +#define BIT_SHIFT_HI1Q_HW_IDX 16 +#define BIT_MASK_HI1Q_HW_IDX 0xfff +#define BIT_HI1Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI1Q_HW_IDX) << BIT_SHIFT_HI1Q_HW_IDX) +#define BITS_HI1Q_HW_IDX (BIT_MASK_HI1Q_HW_IDX << BIT_SHIFT_HI1Q_HW_IDX) +#define BIT_CLEAR_HI1Q_HW_IDX(x) ((x) & (~BITS_HI1Q_HW_IDX)) +#define BIT_GET_HI1Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI1Q_HW_IDX) & BIT_MASK_HI1Q_HW_IDX) +#define BIT_SET_HI1Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI1Q_HW_IDX(x) | BIT_HI1Q_HW_IDX(v)) -#define BIT_SHIFT_DBI_ADDR 0 -#define BIT_MASK_DBI_ADDR 0xfff -#define BIT_DBI_ADDR(x) (((x) & BIT_MASK_DBI_ADDR) << BIT_SHIFT_DBI_ADDR) -#define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_MDIO_V1 (Offset 0x03F4) */ +/* 2 REG_P0HI1Q_TXBD_IDX (Offset 0x03BC) */ +#define BIT_SHIFT_P0HI1Q_HW_IDX 16 +#define BIT_MASK_P0HI1Q_HW_IDX 0xfff +#define BIT_P0HI1Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI1Q_HW_IDX) << BIT_SHIFT_P0HI1Q_HW_IDX) +#define BITS_P0HI1Q_HW_IDX (BIT_MASK_P0HI1Q_HW_IDX << BIT_SHIFT_P0HI1Q_HW_IDX) +#define BIT_CLEAR_P0HI1Q_HW_IDX(x) ((x) & (~BITS_P0HI1Q_HW_IDX)) +#define BIT_GET_P0HI1Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_HW_IDX) & BIT_MASK_P0HI1Q_HW_IDX) +#define BIT_SET_P0HI1Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI1Q_HW_IDX(x) | BIT_P0HI1Q_HW_IDX(v)) -#define BIT_SHIFT_MDIO_RDATA 16 -#define BIT_MASK_MDIO_RDATA 0xffff -#define BIT_MDIO_RDATA(x) (((x) & BIT_MASK_MDIO_RDATA) << BIT_SHIFT_MDIO_RDATA) -#define BIT_GET_MDIO_RDATA(x) (((x) >> BIT_SHIFT_MDIO_RDATA) & BIT_MASK_MDIO_RDATA) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MDIO_WDATA 0 -#define BIT_MASK_MDIO_WDATA 0xffff -#define BIT_MDIO_WDATA(x) (((x) & BIT_MASK_MDIO_WDATA) << BIT_SHIFT_MDIO_WDATA) -#define BIT_GET_MDIO_WDATA(x) (((x) >> BIT_SHIFT_MDIO_WDATA) & BIT_MASK_MDIO_WDATA) +/* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */ +#define BIT_SHIFT_HI1Q_HOST_IDX 0 +#define BIT_MASK_HI1Q_HOST_IDX 0xfff +#define BIT_HI1Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI1Q_HOST_IDX) << BIT_SHIFT_HI1Q_HOST_IDX) +#define BITS_HI1Q_HOST_IDX (BIT_MASK_HI1Q_HOST_IDX << BIT_SHIFT_HI1Q_HOST_IDX) +#define BIT_CLEAR_HI1Q_HOST_IDX(x) ((x) & (~BITS_HI1Q_HOST_IDX)) +#define BIT_GET_HI1Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI1Q_HOST_IDX) & BIT_MASK_HI1Q_HOST_IDX) +#define BIT_SET_HI1Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI1Q_HOST_IDX(x) | BIT_HI1Q_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_P0HI1Q_TXBD_IDX (Offset 0x03BC) */ +#define BIT_SHIFT_P0HI1Q_HOST_IDX 0 +#define BIT_MASK_P0HI1Q_HOST_IDX 0xfff +#define BIT_P0HI1Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI1Q_HOST_IDX) << BIT_SHIFT_P0HI1Q_HOST_IDX) +#define BITS_P0HI1Q_HOST_IDX \ + (BIT_MASK_P0HI1Q_HOST_IDX << BIT_SHIFT_P0HI1Q_HOST_IDX) +#define BIT_CLEAR_P0HI1Q_HOST_IDX(x) ((x) & (~BITS_P0HI1Q_HOST_IDX)) +#define BIT_GET_P0HI1Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_HOST_IDX) & BIT_MASK_P0HI1Q_HOST_IDX) +#define BIT_SET_P0HI1Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI1Q_HOST_IDX(x) | BIT_P0HI1Q_HOST_IDX(v)) -/* 2 REG_BUS_MIX_CFG (Offset 0x03F8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DELAY_TIME 24 -#define BIT_MASK_DELAY_TIME 0xff -#define BIT_DELAY_TIME(x) (((x) & BIT_MASK_DELAY_TIME) << BIT_SHIFT_DELAY_TIME) -#define BIT_GET_DELAY_TIME(x) (((x) >> BIT_SHIFT_DELAY_TIME) & BIT_MASK_DELAY_TIME) +/* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */ -#define BIT_RX_TIMER_DELAY_EN BIT(17) +#define BIT_SHIFT_HI2Q_HW_IDX 16 +#define BIT_MASK_HI2Q_HW_IDX 0xfff +#define BIT_HI2Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI2Q_HW_IDX) << BIT_SHIFT_HI2Q_HW_IDX) +#define BITS_HI2Q_HW_IDX (BIT_MASK_HI2Q_HW_IDX << BIT_SHIFT_HI2Q_HW_IDX) +#define BIT_CLEAR_HI2Q_HW_IDX(x) ((x) & (~BITS_HI2Q_HW_IDX)) +#define BIT_GET_HI2Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI2Q_HW_IDX) & BIT_MASK_HI2Q_HW_IDX) +#define BIT_SET_HI2Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI2Q_HW_IDX(x) | BIT_HI2Q_HW_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ +/* 2 REG_P0HI2Q_TXBD_IDX (Offset 0x03C0) */ -#define BIT_EN_WATCH_DOG BIT(8) +#define BIT_SHIFT_P0HI2Q_HW_IDX 16 +#define BIT_MASK_P0HI2Q_HW_IDX 0xfff +#define BIT_P0HI2Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI2Q_HW_IDX) << BIT_SHIFT_P0HI2Q_HW_IDX) +#define BITS_P0HI2Q_HW_IDX (BIT_MASK_P0HI2Q_HW_IDX << BIT_SHIFT_P0HI2Q_HW_IDX) +#define BIT_CLEAR_P0HI2Q_HW_IDX(x) ((x) & (~BITS_P0HI2Q_HW_IDX)) +#define BIT_GET_P0HI2Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_HW_IDX) & BIT_MASK_P0HI2Q_HW_IDX) +#define BIT_SET_P0HI2Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI2Q_HW_IDX(x) | BIT_P0HI2Q_HW_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */ +#define BIT_SHIFT_HI2Q_HOST_IDX 0 +#define BIT_MASK_HI2Q_HOST_IDX 0xfff +#define BIT_HI2Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI2Q_HOST_IDX) << BIT_SHIFT_HI2Q_HOST_IDX) +#define BITS_HI2Q_HOST_IDX (BIT_MASK_HI2Q_HOST_IDX << BIT_SHIFT_HI2Q_HOST_IDX) +#define BIT_CLEAR_HI2Q_HOST_IDX(x) ((x) & (~BITS_HI2Q_HOST_IDX)) +#define BIT_GET_HI2Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI2Q_HOST_IDX) & BIT_MASK_HI2Q_HOST_IDX) +#define BIT_SET_HI2Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI2Q_HOST_IDX(x) | BIT_HI2Q_HOST_IDX(v)) -/* 2 REG_MDIO2_V1 (Offset 0x03F8) */ +#endif -#define BIT_ECRC_EN BIT(7) -#define BIT_MDIO_RFLAG BIT(6) -#define BIT_MDIO_WFLAG BIT(5) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_MDIO_ADDR 0 -#define BIT_MASK_MDIO_ADDR 0x1f -#define BIT_MDIO_ADDR(x) (((x) & BIT_MASK_MDIO_ADDR) << BIT_SHIFT_MDIO_ADDR) -#define BIT_GET_MDIO_ADDR(x) (((x) >> BIT_SHIFT_MDIO_ADDR) & BIT_MASK_MDIO_ADDR) +/* 2 REG_P0HI2Q_TXBD_IDX (Offset 0x03C0) */ +#define BIT_SHIFT_P0HI2Q_HOST_IDX 0 +#define BIT_MASK_P0HI2Q_HOST_IDX 0xfff +#define BIT_P0HI2Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI2Q_HOST_IDX) << BIT_SHIFT_P0HI2Q_HOST_IDX) +#define BITS_P0HI2Q_HOST_IDX \ + (BIT_MASK_P0HI2Q_HOST_IDX << BIT_SHIFT_P0HI2Q_HOST_IDX) +#define BIT_CLEAR_P0HI2Q_HOST_IDX(x) ((x) & (~BITS_P0HI2Q_HOST_IDX)) +#define BIT_GET_P0HI2Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_HOST_IDX) & BIT_MASK_P0HI2Q_HOST_IDX) +#define BIT_SET_P0HI2Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI2Q_HOST_IDX(x) | BIT_P0HI2Q_HOST_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */ +#define BIT_SHIFT_HI3Q_HW_IDX 16 +#define BIT_MASK_HI3Q_HW_IDX 0xfff +#define BIT_HI3Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI3Q_HW_IDX) << BIT_SHIFT_HI3Q_HW_IDX) +#define BITS_HI3Q_HW_IDX (BIT_MASK_HI3Q_HW_IDX << BIT_SHIFT_HI3Q_HW_IDX) +#define BIT_CLEAR_HI3Q_HW_IDX(x) ((x) & (~BITS_HI3Q_HW_IDX)) +#define BIT_GET_HI3Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI3Q_HW_IDX) & BIT_MASK_HI3Q_HW_IDX) +#define BIT_SET_HI3Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI3Q_HW_IDX(x) | BIT_HI3Q_HW_IDX(v)) -/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_MDIO_REG_ADDR_V1 0 -#define BIT_MASK_MDIO_REG_ADDR_V1 0x1f -#define BIT_MDIO_REG_ADDR_V1(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1) -#define BIT_GET_MDIO_REG_ADDR_V1(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1) & BIT_MASK_MDIO_REG_ADDR_V1) +/* 2 REG_P0HI3Q_TXBD_IDX (Offset 0x03C4) */ +#define BIT_SHIFT_P0HI3Q_HW_IDX 16 +#define BIT_MASK_P0HI3Q_HW_IDX 0xfff +#define BIT_P0HI3Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI3Q_HW_IDX) << BIT_SHIFT_P0HI3Q_HW_IDX) +#define BITS_P0HI3Q_HW_IDX (BIT_MASK_P0HI3Q_HW_IDX << BIT_SHIFT_P0HI3Q_HW_IDX) +#define BIT_CLEAR_P0HI3Q_HW_IDX(x) ((x) & (~BITS_P0HI3Q_HW_IDX)) +#define BIT_GET_P0HI3Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_HW_IDX) & BIT_MASK_P0HI3Q_HW_IDX) +#define BIT_SET_P0HI3Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI3Q_HW_IDX(x) | BIT_P0HI3Q_HW_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */ +#define BIT_SHIFT_HI3Q_HOST_IDX 0 +#define BIT_MASK_HI3Q_HOST_IDX 0xfff +#define BIT_HI3Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI3Q_HOST_IDX) << BIT_SHIFT_HI3Q_HOST_IDX) +#define BITS_HI3Q_HOST_IDX (BIT_MASK_HI3Q_HOST_IDX << BIT_SHIFT_HI3Q_HOST_IDX) +#define BIT_CLEAR_HI3Q_HOST_IDX(x) ((x) & (~BITS_HI3Q_HOST_IDX)) +#define BIT_GET_HI3Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI3Q_HOST_IDX) & BIT_MASK_HI3Q_HOST_IDX) +#define BIT_SET_HI3Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI3Q_HOST_IDX(x) | BIT_HI3Q_HOST_IDX(v)) -/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#endif -#define BIT_RXRST_BACKDOOR BIT(31) -#define BIT_TXRST_BACKDOOR BIT(30) -#define BIT_RXIDX_RSTB BIT(29) -#define BIT_TXIDX_RSTB BIT(28) -#define BIT_DROP_NEXT_RXPKT BIT(27) -#define BIT_SHORT_CORE_RST_SEL BIT(26) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_P0HI3Q_TXBD_IDX (Offset 0x03C4) */ +#define BIT_SHIFT_P0HI3Q_HOST_IDX 0 +#define BIT_MASK_P0HI3Q_HOST_IDX 0xfff +#define BIT_P0HI3Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI3Q_HOST_IDX) << BIT_SHIFT_P0HI3Q_HOST_IDX) +#define BITS_P0HI3Q_HOST_IDX \ + (BIT_MASK_P0HI3Q_HOST_IDX << BIT_SHIFT_P0HI3Q_HOST_IDX) +#define BIT_CLEAR_P0HI3Q_HOST_IDX(x) ((x) & (~BITS_P0HI3Q_HOST_IDX)) +#define BIT_GET_P0HI3Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_HOST_IDX) & BIT_MASK_P0HI3Q_HOST_IDX) +#define BIT_SET_P0HI3Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI3Q_HOST_IDX(x) | BIT_P0HI3Q_HOST_IDX(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +/* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */ -#define BIT_EXCEPT_RESUME_EN BIT(25) -#define BIT_EXCEPT_RESUME_FLAG BIT(24) +#define BIT_SHIFT_HI4Q_HW_IDX 16 +#define BIT_MASK_HI4Q_HW_IDX 0xfff +#define BIT_HI4Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI4Q_HW_IDX) << BIT_SHIFT_HI4Q_HW_IDX) +#define BITS_HI4Q_HW_IDX (BIT_MASK_HI4Q_HW_IDX << BIT_SHIFT_HI4Q_HW_IDX) +#define BIT_CLEAR_HI4Q_HW_IDX(x) ((x) & (~BITS_HI4Q_HW_IDX)) +#define BIT_GET_HI4Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI4Q_HW_IDX) & BIT_MASK_HI4Q_HW_IDX) +#define BIT_SET_HI4Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI4Q_HW_IDX(x) | BIT_HI4Q_HW_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_P0HI4Q_TXBD_IDX (Offset 0x03C8) */ +#define BIT_SHIFT_P0HI4Q_HW_IDX 16 +#define BIT_MASK_P0HI4Q_HW_IDX 0xfff +#define BIT_P0HI4Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI4Q_HW_IDX) << BIT_SHIFT_P0HI4Q_HW_IDX) +#define BITS_P0HI4Q_HW_IDX (BIT_MASK_P0HI4Q_HW_IDX << BIT_SHIFT_P0HI4Q_HW_IDX) +#define BIT_CLEAR_P0HI4Q_HW_IDX(x) ((x) & (~BITS_P0HI4Q_HW_IDX)) +#define BIT_GET_P0HI4Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_HW_IDX) & BIT_MASK_P0HI4Q_HW_IDX) +#define BIT_SET_P0HI4Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI4Q_HW_IDX(x) | BIT_P0HI4Q_HW_IDX(v)) -/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#endif -#define BIT_ALIGN_MTU BIT(23) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */ +#define BIT_SHIFT_HI4Q_HOST_IDX 0 +#define BIT_MASK_HI4Q_HOST_IDX 0xfff +#define BIT_HI4Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI4Q_HOST_IDX) << BIT_SHIFT_HI4Q_HOST_IDX) +#define BITS_HI4Q_HOST_IDX (BIT_MASK_HI4Q_HOST_IDX << BIT_SHIFT_HI4Q_HOST_IDX) +#define BIT_CLEAR_HI4Q_HOST_IDX(x) ((x) & (~BITS_HI4Q_HOST_IDX)) +#define BIT_GET_HI4Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI4Q_HOST_IDX) & BIT_MASK_HI4Q_HOST_IDX) +#define BIT_SET_HI4Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI4Q_HOST_IDX(x) | BIT_HI4Q_HOST_IDX(v)) -#if (HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +/* 2 REG_P0HI4Q_TXBD_IDX (Offset 0x03C8) */ -#define BIT_EARLY_TAG_RETURN BIT(22) +#define BIT_SHIFT_P0HI4Q_HOST_IDX 0 +#define BIT_MASK_P0HI4Q_HOST_IDX 0xfff +#define BIT_P0HI4Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI4Q_HOST_IDX) << BIT_SHIFT_P0HI4Q_HOST_IDX) +#define BITS_P0HI4Q_HOST_IDX \ + (BIT_MASK_P0HI4Q_HOST_IDX << BIT_SHIFT_P0HI4Q_HOST_IDX) +#define BIT_CLEAR_P0HI4Q_HOST_IDX(x) ((x) & (~BITS_P0HI4Q_HOST_IDX)) +#define BIT_GET_P0HI4Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_HOST_IDX) & BIT_MASK_P0HI4Q_HOST_IDX) +#define BIT_SET_P0HI4Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI4Q_HOST_IDX(x) | BIT_P0HI4Q_HOST_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */ +#define BIT_SHIFT_HI5Q_HW_IDX 16 +#define BIT_MASK_HI5Q_HW_IDX 0xfff +#define BIT_HI5Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI5Q_HW_IDX) << BIT_SHIFT_HI5Q_HW_IDX) +#define BITS_HI5Q_HW_IDX (BIT_MASK_HI5Q_HW_IDX << BIT_SHIFT_HI5Q_HW_IDX) +#define BIT_CLEAR_HI5Q_HW_IDX(x) ((x) & (~BITS_HI5Q_HW_IDX)) +#define BIT_GET_HI5Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI5Q_HW_IDX) & BIT_MASK_HI5Q_HW_IDX) +#define BIT_SET_HI5Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI5Q_HW_IDX(x) | BIT_HI5Q_HW_IDX(v)) -/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#endif -#define BIT_HOST_GEN2_SUPPORT BIT(20) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TXDMA_ERR_FLAG 16 -#define BIT_MASK_TXDMA_ERR_FLAG 0xf -#define BIT_TXDMA_ERR_FLAG(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG) << BIT_SHIFT_TXDMA_ERR_FLAG) -#define BIT_GET_TXDMA_ERR_FLAG(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG) & BIT_MASK_TXDMA_ERR_FLAG) +/* 2 REG_P0HI5Q_TXBD_IDX (Offset 0x03CC) */ +#define BIT_SHIFT_P0HI5Q_HW_IDX 16 +#define BIT_MASK_P0HI5Q_HW_IDX 0xfff +#define BIT_P0HI5Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI5Q_HW_IDX) << BIT_SHIFT_P0HI5Q_HW_IDX) +#define BITS_P0HI5Q_HW_IDX (BIT_MASK_P0HI5Q_HW_IDX << BIT_SHIFT_P0HI5Q_HW_IDX) +#define BIT_CLEAR_P0HI5Q_HW_IDX(x) ((x) & (~BITS_P0HI5Q_HW_IDX)) +#define BIT_GET_P0HI5Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_HW_IDX) & BIT_MASK_P0HI5Q_HW_IDX) +#define BIT_SET_P0HI5Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI5Q_HW_IDX(x) | BIT_P0HI5Q_HW_IDX(v)) -#define BIT_SHIFT_EARLY_MODE_SEL 12 -#define BIT_MASK_EARLY_MODE_SEL 0xf -#define BIT_EARLY_MODE_SEL(x) (((x) & BIT_MASK_EARLY_MODE_SEL) << BIT_SHIFT_EARLY_MODE_SEL) -#define BIT_GET_EARLY_MODE_SEL(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL) & BIT_MASK_EARLY_MODE_SEL) +#endif -#define BIT_EPHY_RX50_EN BIT(11) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MSI_TIMEOUT_ID_V1 8 -#define BIT_MASK_MSI_TIMEOUT_ID_V1 0x7 -#define BIT_MSI_TIMEOUT_ID_V1(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1) << BIT_SHIFT_MSI_TIMEOUT_ID_V1) -#define BIT_GET_MSI_TIMEOUT_ID_V1(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1) & BIT_MASK_MSI_TIMEOUT_ID_V1) +/* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */ -#define BIT_RADDR_RD BIT(7) -#define BIT_EN_MUL_TAG BIT(6) -#define BIT_EN_EARLY_MODE BIT(5) -#define BIT_L0S_LINK_OFF BIT(4) -#define BIT_ACT_LINK_OFF BIT(3) +#define BIT_SHIFT_HI5Q_HOST_IDX 0 +#define BIT_MASK_HI5Q_HOST_IDX 0xfff +#define BIT_HI5Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI5Q_HOST_IDX) << BIT_SHIFT_HI5Q_HOST_IDX) +#define BITS_HI5Q_HOST_IDX (BIT_MASK_HI5Q_HOST_IDX << BIT_SHIFT_HI5Q_HOST_IDX) +#define BIT_CLEAR_HI5Q_HOST_IDX(x) ((x) & (~BITS_HI5Q_HOST_IDX)) +#define BIT_GET_HI5Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI5Q_HOST_IDX) & BIT_MASK_HI5Q_HOST_IDX) +#define BIT_SET_HI5Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI5Q_HOST_IDX(x) | BIT_HI5Q_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +/* 2 REG_P0HI5Q_TXBD_IDX (Offset 0x03CC) */ -#define BIT_EN_SLOW_MAC_TX BIT(2) -#define BIT_EN_SLOW_MAC_RX BIT(1) +#define BIT_SHIFT_P0HI5Q_HOST_IDX 0 +#define BIT_MASK_P0HI5Q_HOST_IDX 0xfff +#define BIT_P0HI5Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI5Q_HOST_IDX) << BIT_SHIFT_P0HI5Q_HOST_IDX) +#define BITS_P0HI5Q_HOST_IDX \ + (BIT_MASK_P0HI5Q_HOST_IDX << BIT_SHIFT_P0HI5Q_HOST_IDX) +#define BIT_CLEAR_P0HI5Q_HOST_IDX(x) ((x) & (~BITS_P0HI5Q_HOST_IDX)) +#define BIT_GET_P0HI5Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_HOST_IDX) & BIT_MASK_P0HI5Q_HOST_IDX) +#define BIT_SET_P0HI5Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI5Q_HOST_IDX(x) | BIT_P0HI5Q_HOST_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */ +#define BIT_SHIFT_HI6Q_HW_IDX 16 +#define BIT_MASK_HI6Q_HW_IDX 0xfff +#define BIT_HI6Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI6Q_HW_IDX) << BIT_SHIFT_HI6Q_HW_IDX) +#define BITS_HI6Q_HW_IDX (BIT_MASK_HI6Q_HW_IDX << BIT_SHIFT_HI6Q_HW_IDX) +#define BIT_CLEAR_HI6Q_HW_IDX(x) ((x) & (~BITS_HI6Q_HW_IDX)) +#define BIT_GET_HI6Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI6Q_HW_IDX) & BIT_MASK_HI6Q_HW_IDX) +#define BIT_SET_HI6Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI6Q_HW_IDX(x) | BIT_HI6Q_HW_IDX(v)) -/* 2 REG_Q0_INFO (Offset 0x0400) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_QUEUEMACID_Q0_V1 25 -#define BIT_MASK_QUEUEMACID_Q0_V1 0x7f -#define BIT_QUEUEMACID_Q0_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1) -#define BIT_GET_QUEUEMACID_Q0_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1) +/* 2 REG_P0HI6Q_TXBD_IDX (Offset 0x03D0) */ +#define BIT_SHIFT_P0HI6Q_HW_IDX 16 +#define BIT_MASK_P0HI6Q_HW_IDX 0xfff +#define BIT_P0HI6Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI6Q_HW_IDX) << BIT_SHIFT_P0HI6Q_HW_IDX) +#define BITS_P0HI6Q_HW_IDX (BIT_MASK_P0HI6Q_HW_IDX << BIT_SHIFT_P0HI6Q_HW_IDX) +#define BIT_CLEAR_P0HI6Q_HW_IDX(x) ((x) & (~BITS_P0HI6Q_HW_IDX)) +#define BIT_GET_P0HI6Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_HW_IDX) & BIT_MASK_P0HI6Q_HW_IDX) +#define BIT_SET_P0HI6Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI6Q_HW_IDX(x) | BIT_P0HI6Q_HW_IDX(v)) -#define BIT_SHIFT_QUEUEAC_Q0_V1 23 -#define BIT_MASK_QUEUEAC_Q0_V1 0x3 -#define BIT_QUEUEAC_Q0_V1(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1) -#define BIT_GET_QUEUEAC_Q0_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */ +#define BIT_SHIFT_HI6Q_HOST_IDX 0 +#define BIT_MASK_HI6Q_HOST_IDX 0xfff +#define BIT_HI6Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI6Q_HOST_IDX) << BIT_SHIFT_HI6Q_HOST_IDX) +#define BITS_HI6Q_HOST_IDX (BIT_MASK_HI6Q_HOST_IDX << BIT_SHIFT_HI6Q_HOST_IDX) +#define BIT_CLEAR_HI6Q_HOST_IDX(x) ((x) & (~BITS_HI6Q_HOST_IDX)) +#define BIT_GET_HI6Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI6Q_HOST_IDX) & BIT_MASK_HI6Q_HOST_IDX) +#define BIT_SET_HI6Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI6Q_HOST_IDX(x) | BIT_HI6Q_HOST_IDX(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_Q0_INFO (Offset 0x0400) */ +/* 2 REG_P0HI6Q_TXBD_IDX (Offset 0x03D0) */ -#define BIT_TIDEMPTY_Q0_V1 BIT(22) +#define BIT_SHIFT_P0HI6Q_HOST_IDX 0 +#define BIT_MASK_P0HI6Q_HOST_IDX 0xfff +#define BIT_P0HI6Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI6Q_HOST_IDX) << BIT_SHIFT_P0HI6Q_HOST_IDX) +#define BITS_P0HI6Q_HOST_IDX \ + (BIT_MASK_P0HI6Q_HOST_IDX << BIT_SHIFT_P0HI6Q_HOST_IDX) +#define BIT_CLEAR_P0HI6Q_HOST_IDX(x) ((x) & (~BITS_P0HI6Q_HOST_IDX)) +#define BIT_GET_P0HI6Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_HOST_IDX) & BIT_MASK_P0HI6Q_HOST_IDX) +#define BIT_SET_P0HI6Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI6Q_HOST_IDX(x) | BIT_P0HI6Q_HOST_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */ +#define BIT_SHIFT_HI7Q_HW_IDX 16 +#define BIT_MASK_HI7Q_HW_IDX 0xfff +#define BIT_HI7Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI7Q_HW_IDX) << BIT_SHIFT_HI7Q_HW_IDX) +#define BITS_HI7Q_HW_IDX (BIT_MASK_HI7Q_HW_IDX << BIT_SHIFT_HI7Q_HW_IDX) +#define BIT_CLEAR_HI7Q_HW_IDX(x) ((x) & (~BITS_HI7Q_HW_IDX)) +#define BIT_GET_HI7Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI7Q_HW_IDX) & BIT_MASK_HI7Q_HW_IDX) +#define BIT_SET_HI7Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI7Q_HW_IDX(x) | BIT_HI7Q_HW_IDX(v)) -/* 2 REG_Q0_INFO (Offset 0x0400) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q0_V1 15 -#define BIT_MASK_TAIL_PKT_Q0_V1 0xff -#define BIT_TAIL_PKT_Q0_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V1) << BIT_SHIFT_TAIL_PKT_Q0_V1) -#define BIT_GET_TAIL_PKT_Q0_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V1) & BIT_MASK_TAIL_PKT_Q0_V1) +/* 2 REG_P0HI7Q_TXBD_IDX (Offset 0x03D4) */ +#define BIT_SHIFT_P0HI7Q_HW_IDX 16 +#define BIT_MASK_P0HI7Q_HW_IDX 0xfff +#define BIT_P0HI7Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI7Q_HW_IDX) << BIT_SHIFT_P0HI7Q_HW_IDX) +#define BITS_P0HI7Q_HW_IDX (BIT_MASK_P0HI7Q_HW_IDX << BIT_SHIFT_P0HI7Q_HW_IDX) +#define BIT_CLEAR_P0HI7Q_HW_IDX(x) ((x) & (~BITS_P0HI7Q_HW_IDX)) +#define BIT_GET_P0HI7Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_HW_IDX) & BIT_MASK_P0HI7Q_HW_IDX) +#define BIT_SET_P0HI7Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI7Q_HW_IDX(x) | BIT_P0HI7Q_HW_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */ +#define BIT_SHIFT_HI7Q_HOST_IDX 0 +#define BIT_MASK_HI7Q_HOST_IDX 0xfff +#define BIT_HI7Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI7Q_HOST_IDX) << BIT_SHIFT_HI7Q_HOST_IDX) +#define BITS_HI7Q_HOST_IDX (BIT_MASK_HI7Q_HOST_IDX << BIT_SHIFT_HI7Q_HOST_IDX) +#define BIT_CLEAR_HI7Q_HOST_IDX(x) ((x) & (~BITS_HI7Q_HOST_IDX)) +#define BIT_GET_HI7Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI7Q_HOST_IDX) & BIT_MASK_HI7Q_HOST_IDX) +#define BIT_SET_HI7Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI7Q_HOST_IDX(x) | BIT_HI7Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI7Q_TXBD_IDX (Offset 0x03D4) */ + +#define BIT_SHIFT_P0HI7Q_HOST_IDX 0 +#define BIT_MASK_P0HI7Q_HOST_IDX 0xfff +#define BIT_P0HI7Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI7Q_HOST_IDX) << BIT_SHIFT_P0HI7Q_HOST_IDX) +#define BITS_P0HI7Q_HOST_IDX \ + (BIT_MASK_P0HI7Q_HOST_IDX << BIT_SHIFT_P0HI7Q_HOST_IDX) +#define BIT_CLEAR_P0HI7Q_HOST_IDX(x) ((x) & (~BITS_P0HI7Q_HOST_IDX)) +#define BIT_GET_P0HI7Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_HOST_IDX) & BIT_MASK_P0HI7Q_HOST_IDX) +#define BIT_SET_P0HI7Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI7Q_HOST_IDX(x) | BIT_P0HI7Q_HOST_IDX(v)) + +/* 2 REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1 (Offset 0x03D8) */ + +#define BIT_DIS_TXDMA_PRE_V1 BIT(31) +#define BIT_DIS_RXDMA_PRE_V1 BIT(30) + +#define BIT_SHIFT_HPS_CLKR_PCIE_V1 28 +#define BIT_MASK_HPS_CLKR_PCIE_V1 0x3 +#define BIT_HPS_CLKR_PCIE_V1(x) \ + (((x) & BIT_MASK_HPS_CLKR_PCIE_V1) << BIT_SHIFT_HPS_CLKR_PCIE_V1) +#define BITS_HPS_CLKR_PCIE_V1 \ + (BIT_MASK_HPS_CLKR_PCIE_V1 << BIT_SHIFT_HPS_CLKR_PCIE_V1) +#define BIT_CLEAR_HPS_CLKR_PCIE_V1(x) ((x) & (~BITS_HPS_CLKR_PCIE_V1)) +#define BIT_GET_HPS_CLKR_PCIE_V1(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_V1) & BIT_MASK_HPS_CLKR_PCIE_V1) +#define BIT_SET_HPS_CLKR_PCIE_V1(x, v) \ + (BIT_CLEAR_HPS_CLKR_PCIE_V1(x) | BIT_HPS_CLKR_PCIE_V1(v)) + +#define BIT_PCIE_INT_V1 BIT(27) +#define BIT_TXFLAG_EXIT_L1_EN_V1 BIT(26) +#define BIT_EN_RXDMA_ALIGN_V2 BIT(25) +#define BIT_EN_TXDMA_ALIGN_V2 BIT(24) + +#define BIT_SHIFT_PCIE_HCPWM_V1 16 +#define BIT_MASK_PCIE_HCPWM_V1 0xff +#define BIT_PCIE_HCPWM_V1(x) \ + (((x) & BIT_MASK_PCIE_HCPWM_V1) << BIT_SHIFT_PCIE_HCPWM_V1) +#define BITS_PCIE_HCPWM_V1 (BIT_MASK_PCIE_HCPWM_V1 << BIT_SHIFT_PCIE_HCPWM_V1) +#define BIT_CLEAR_PCIE_HCPWM_V1(x) ((x) & (~BITS_PCIE_HCPWM_V1)) +#define BIT_GET_PCIE_HCPWM_V1(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM_V1) & BIT_MASK_PCIE_HCPWM_V1) +#define BIT_SET_PCIE_HCPWM_V1(x, v) \ + (BIT_CLEAR_PCIE_HCPWM_V1(x) | BIT_PCIE_HCPWM_V1(v)) + +#define BIT_SHIFT_PCIE_HRPWM_V1 8 +#define BIT_MASK_PCIE_HRPWM_V1 0xff +#define BIT_PCIE_HRPWM_V1(x) \ + (((x) & BIT_MASK_PCIE_HRPWM_V1) << BIT_SHIFT_PCIE_HRPWM_V1) +#define BITS_PCIE_HRPWM_V1 (BIT_MASK_PCIE_HRPWM_V1 << BIT_SHIFT_PCIE_HRPWM_V1) +#define BIT_CLEAR_PCIE_HRPWM_V1(x) ((x) & (~BITS_PCIE_HRPWM_V1)) +#define BIT_GET_PCIE_HRPWM_V1(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM_V1) & BIT_MASK_PCIE_HRPWM_V1) +#define BIT_SET_PCIE_HRPWM_V1(x, v) \ + (BIT_CLEAR_PCIE_HRPWM_V1(x) | BIT_PCIE_HRPWM_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_Q0_INFO (Offset 0x0400) */ +/* 2 REG_DBG_SEL_V1 (Offset 0x03D8) */ +#define BIT_SHIFT_DBG_SEL 0 +#define BIT_MASK_DBG_SEL 0xff +#define BIT_DBG_SEL(x) (((x) & BIT_MASK_DBG_SEL) << BIT_SHIFT_DBG_SEL) +#define BITS_DBG_SEL (BIT_MASK_DBG_SEL << BIT_SHIFT_DBG_SEL) +#define BIT_CLEAR_DBG_SEL(x) ((x) & (~BITS_DBG_SEL)) +#define BIT_GET_DBG_SEL(x) (((x) >> BIT_SHIFT_DBG_SEL) & BIT_MASK_DBG_SEL) +#define BIT_SET_DBG_SEL(x, v) (BIT_CLEAR_DBG_SEL(x) | BIT_DBG_SEL(v)) -#define BIT_SHIFT_TAIL_PKT_Q0_V2 11 -#define BIT_MASK_TAIL_PKT_Q0_V2 0x7ff -#define BIT_TAIL_PKT_Q0_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2) << BIT_SHIFT_TAIL_PKT_Q0_V2) -#define BIT_GET_TAIL_PKT_Q0_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2) & BIT_MASK_TAIL_PKT_Q0_V2) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_PCIE_HRPWM1_V1 (Offset 0x03D9) */ +#define BIT_SHIFT_PCIE_HRPWM 0 +#define BIT_MASK_PCIE_HRPWM 0xff +#define BIT_PCIE_HRPWM(x) (((x) & BIT_MASK_PCIE_HRPWM) << BIT_SHIFT_PCIE_HRPWM) +#define BITS_PCIE_HRPWM (BIT_MASK_PCIE_HRPWM << BIT_SHIFT_PCIE_HRPWM) +#define BIT_CLEAR_PCIE_HRPWM(x) ((x) & (~BITS_PCIE_HRPWM)) +#define BIT_GET_PCIE_HRPWM(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM) & BIT_MASK_PCIE_HRPWM) +#define BIT_SET_PCIE_HRPWM(x, v) (BIT_CLEAR_PCIE_HRPWM(x) | BIT_PCIE_HRPWM(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_Q0_INFO (Offset 0x0400) */ +/* 2 REG_HCI_HRPWM1_V1 (Offset 0x03D9) */ +#define BIT_SHIFT_HCI_HRPWM 0 +#define BIT_MASK_HCI_HRPWM 0xff +#define BIT_HCI_HRPWM(x) (((x) & BIT_MASK_HCI_HRPWM) << BIT_SHIFT_HCI_HRPWM) +#define BITS_HCI_HRPWM (BIT_MASK_HCI_HRPWM << BIT_SHIFT_HCI_HRPWM) +#define BIT_CLEAR_HCI_HRPWM(x) ((x) & (~BITS_HCI_HRPWM)) +#define BIT_GET_HCI_HRPWM(x) (((x) >> BIT_SHIFT_HCI_HRPWM) & BIT_MASK_HCI_HRPWM) +#define BIT_SET_HCI_HRPWM(x, v) (BIT_CLEAR_HCI_HRPWM(x) | BIT_HCI_HRPWM(v)) -#define BIT_SHIFT_PKT_NUM_Q0_V1 8 -#define BIT_MASK_PKT_NUM_Q0_V1 0x7f -#define BIT_PKT_NUM_Q0_V1(x) (((x) & BIT_MASK_PKT_NUM_Q0_V1) << BIT_SHIFT_PKT_NUM_Q0_V1) -#define BIT_GET_PKT_NUM_Q0_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q0_V1) & BIT_MASK_PKT_NUM_Q0_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q0 0 -#define BIT_MASK_HEAD_PKT_Q0 0xff -#define BIT_HEAD_PKT_Q0(x) (((x) & BIT_MASK_HEAD_PKT_Q0) << BIT_SHIFT_HEAD_PKT_Q0) -#define BIT_GET_HEAD_PKT_Q0(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0) & BIT_MASK_HEAD_PKT_Q0) +/* 2 REG_PCIE_HCPWM1_V1 (Offset 0x03DA) */ +#define BIT_SHIFT_PCIE_HCPWM 0 +#define BIT_MASK_PCIE_HCPWM 0xff +#define BIT_PCIE_HCPWM(x) (((x) & BIT_MASK_PCIE_HCPWM) << BIT_SHIFT_PCIE_HCPWM) +#define BITS_PCIE_HCPWM (BIT_MASK_PCIE_HCPWM << BIT_SHIFT_PCIE_HCPWM) +#define BIT_CLEAR_PCIE_HCPWM(x) ((x) & (~BITS_PCIE_HCPWM)) +#define BIT_GET_PCIE_HCPWM(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM) & BIT_MASK_PCIE_HCPWM) +#define BIT_SET_PCIE_HCPWM(x, v) (BIT_CLEAR_PCIE_HCPWM(x) | BIT_PCIE_HCPWM(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HCI_HCPWM1_V1 (Offset 0x03DA) */ +#define BIT_SHIFT_HCI_HCPWM 0 +#define BIT_MASK_HCI_HCPWM 0xff +#define BIT_HCI_HCPWM(x) (((x) & BIT_MASK_HCI_HCPWM) << BIT_SHIFT_HCI_HCPWM) +#define BITS_HCI_HCPWM (BIT_MASK_HCI_HCPWM << BIT_SHIFT_HCI_HCPWM) +#define BIT_CLEAR_HCI_HCPWM(x) ((x) & (~BITS_HCI_HCPWM)) +#define BIT_GET_HCI_HCPWM(x) (((x) >> BIT_SHIFT_HCI_HCPWM) & BIT_MASK_HCI_HCPWM) +#define BIT_SET_HCI_HCPWM(x, v) (BIT_CLEAR_HCI_HCPWM(x) | BIT_HCI_HCPWM(v)) -/* 2 REG_Q0_INFO (Offset 0x0400) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q0_V1 0 -#define BIT_MASK_HEAD_PKT_Q0_V1 0x7ff -#define BIT_HEAD_PKT_Q0_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1) << BIT_SHIFT_HEAD_PKT_Q0_V1) -#define BIT_GET_HEAD_PKT_Q0_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1) & BIT_MASK_HEAD_PKT_Q0_V1) +/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ +#define BIT_SHIFT_HPS_CLKR_PCIE 4 +#define BIT_MASK_HPS_CLKR_PCIE 0x3 +#define BIT_HPS_CLKR_PCIE(x) \ + (((x) & BIT_MASK_HPS_CLKR_PCIE) << BIT_SHIFT_HPS_CLKR_PCIE) +#define BITS_HPS_CLKR_PCIE (BIT_MASK_HPS_CLKR_PCIE << BIT_SHIFT_HPS_CLKR_PCIE) +#define BIT_CLEAR_HPS_CLKR_PCIE(x) ((x) & (~BITS_HPS_CLKR_PCIE)) +#define BIT_GET_HPS_CLKR_PCIE(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_PCIE) & BIT_MASK_HPS_CLKR_PCIE) +#define BIT_SET_HPS_CLKR_PCIE(x, v) \ + (BIT_CLEAR_HPS_CLKR_PCIE(x) | BIT_HPS_CLKR_PCIE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_CTRL2 (Offset 0x03DB) */ +#define BIT_SHIFT_HPS_CLKR_HCI 4 +#define BIT_MASK_HPS_CLKR_HCI 0x3 +#define BIT_HPS_CLKR_HCI(x) \ + (((x) & BIT_MASK_HPS_CLKR_HCI) << BIT_SHIFT_HPS_CLKR_HCI) +#define BITS_HPS_CLKR_HCI (BIT_MASK_HPS_CLKR_HCI << BIT_SHIFT_HPS_CLKR_HCI) +#define BIT_CLEAR_HPS_CLKR_HCI(x) ((x) & (~BITS_HPS_CLKR_HCI)) +#define BIT_GET_HPS_CLKR_HCI(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_HCI) & BIT_MASK_HPS_CLKR_HCI) +#define BIT_SET_HPS_CLKR_HCI(x, v) \ + (BIT_CLEAR_HPS_CLKR_HCI(x) | BIT_HPS_CLKR_HCI(v)) -/* 2 REG_Q1_INFO (Offset 0x0404) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_QUEUEMACID_Q1_V1 25 -#define BIT_MASK_QUEUEMACID_Q1_V1 0x7f -#define BIT_QUEUEMACID_Q1_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1) -#define BIT_GET_QUEUEMACID_Q1_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1) +/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ +#define BIT_PCIE_INT BIT(3) -#define BIT_SHIFT_QUEUEAC_Q1_V1 23 -#define BIT_MASK_QUEUEAC_Q1_V1 0x3 -#define BIT_QUEUEAC_Q1_V1(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1) -#define BIT_GET_QUEUEAC_Q1_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_HCI_CTRL2 (Offset 0x03DB) */ +#define BIT_HCI_INT BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_Q1_INFO (Offset 0x0404) */ +/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ -#define BIT_TIDEMPTY_Q1_V1 BIT(22) +#define BIT_EN_RXDMA_ALIGN BIT(1) +#define BIT_EN_TXDMA_ALIGN BIT(0) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PCIE_HRPWM2_HCPWM2_V1 (Offset 0x03DC) */ +#define BIT_SHIFT_PCIE_HCPWM2_V1 16 +#define BIT_MASK_PCIE_HCPWM2_V1 0xffff +#define BIT_PCIE_HCPWM2_V1(x) \ + (((x) & BIT_MASK_PCIE_HCPWM2_V1) << BIT_SHIFT_PCIE_HCPWM2_V1) +#define BITS_PCIE_HCPWM2_V1 \ + (BIT_MASK_PCIE_HCPWM2_V1 << BIT_SHIFT_PCIE_HCPWM2_V1) +#define BIT_CLEAR_PCIE_HCPWM2_V1(x) ((x) & (~BITS_PCIE_HCPWM2_V1)) +#define BIT_GET_PCIE_HCPWM2_V1(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM2_V1) & BIT_MASK_PCIE_HCPWM2_V1) +#define BIT_SET_PCIE_HCPWM2_V1(x, v) \ + (BIT_CLEAR_PCIE_HCPWM2_V1(x) | BIT_PCIE_HCPWM2_V1(v)) -/* 2 REG_Q1_INFO (Offset 0x0404) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q1_V1 15 -#define BIT_MASK_TAIL_PKT_Q1_V1 0xff -#define BIT_TAIL_PKT_Q1_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V1) << BIT_SHIFT_TAIL_PKT_Q1_V1) -#define BIT_GET_TAIL_PKT_Q1_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V1) & BIT_MASK_TAIL_PKT_Q1_V1) +/* 2 REG_PCIE_HRPWM2_V1 (Offset 0x03DC) */ +#define BIT_SHIFT_PCIE_HRPWM2 0 +#define BIT_MASK_PCIE_HRPWM2 0xffff +#define BIT_PCIE_HRPWM2(x) \ + (((x) & BIT_MASK_PCIE_HRPWM2) << BIT_SHIFT_PCIE_HRPWM2) +#define BITS_PCIE_HRPWM2 (BIT_MASK_PCIE_HRPWM2 << BIT_SHIFT_PCIE_HRPWM2) +#define BIT_CLEAR_PCIE_HRPWM2(x) ((x) & (~BITS_PCIE_HRPWM2)) +#define BIT_GET_PCIE_HRPWM2(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM2) & BIT_MASK_PCIE_HRPWM2) +#define BIT_SET_PCIE_HRPWM2(x, v) \ + (BIT_CLEAR_PCIE_HRPWM2(x) | BIT_PCIE_HRPWM2(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HCI_HRPWM2_V1 (Offset 0x03DC) */ +#define BIT_SHIFT_HCI_HRPWM2 0 +#define BIT_MASK_HCI_HRPWM2 0xffff +#define BIT_HCI_HRPWM2(x) (((x) & BIT_MASK_HCI_HRPWM2) << BIT_SHIFT_HCI_HRPWM2) +#define BITS_HCI_HRPWM2 (BIT_MASK_HCI_HRPWM2 << BIT_SHIFT_HCI_HRPWM2) +#define BIT_CLEAR_HCI_HRPWM2(x) ((x) & (~BITS_HCI_HRPWM2)) +#define BIT_GET_HCI_HRPWM2(x) \ + (((x) >> BIT_SHIFT_HCI_HRPWM2) & BIT_MASK_HCI_HRPWM2) +#define BIT_SET_HCI_HRPWM2(x, v) (BIT_CLEAR_HCI_HRPWM2(x) | BIT_HCI_HRPWM2(v)) -/* 2 REG_Q1_INFO (Offset 0x0404) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q1_V2 11 -#define BIT_MASK_TAIL_PKT_Q1_V2 0x7ff -#define BIT_TAIL_PKT_Q1_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2) << BIT_SHIFT_TAIL_PKT_Q1_V2) -#define BIT_GET_TAIL_PKT_Q1_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2) & BIT_MASK_TAIL_PKT_Q1_V2) +/* 2 REG_PCIE_HCPWM2_V1 (Offset 0x03DE) */ +#define BIT_SHIFT_PCIE_HCPWM2 0 +#define BIT_MASK_PCIE_HCPWM2 0xffff +#define BIT_PCIE_HCPWM2(x) \ + (((x) & BIT_MASK_PCIE_HCPWM2) << BIT_SHIFT_PCIE_HCPWM2) +#define BITS_PCIE_HCPWM2 (BIT_MASK_PCIE_HCPWM2 << BIT_SHIFT_PCIE_HCPWM2) +#define BIT_CLEAR_PCIE_HCPWM2(x) ((x) & (~BITS_PCIE_HCPWM2)) +#define BIT_GET_PCIE_HCPWM2(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM2) & BIT_MASK_PCIE_HCPWM2) +#define BIT_SET_PCIE_HCPWM2(x, v) \ + (BIT_CLEAR_PCIE_HCPWM2(x) | BIT_PCIE_HCPWM2(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_HCPWM2_V1 (Offset 0x03DE) */ +#define BIT_SHIFT_HCI_HCPWM2 0 +#define BIT_MASK_HCI_HCPWM2 0xffff +#define BIT_HCI_HCPWM2(x) (((x) & BIT_MASK_HCI_HCPWM2) << BIT_SHIFT_HCI_HCPWM2) +#define BITS_HCI_HCPWM2 (BIT_MASK_HCI_HCPWM2 << BIT_SHIFT_HCI_HCPWM2) +#define BIT_CLEAR_HCI_HCPWM2(x) ((x) & (~BITS_HCI_HCPWM2)) +#define BIT_GET_HCI_HCPWM2(x) \ + (((x) >> BIT_SHIFT_HCI_HCPWM2) & BIT_MASK_HCI_HCPWM2) +#define BIT_SET_HCI_HCPWM2(x, v) (BIT_CLEAR_HCI_HCPWM2(x) | BIT_HCI_HCPWM2(v)) -/* 2 REG_Q1_INFO (Offset 0x0404) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKT_NUM_Q1_V1 8 -#define BIT_MASK_PKT_NUM_Q1_V1 0x7f -#define BIT_PKT_NUM_Q1_V1(x) (((x) & BIT_MASK_PKT_NUM_Q1_V1) << BIT_SHIFT_PKT_NUM_Q1_V1) -#define BIT_GET_PKT_NUM_Q1_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q1_V1) & BIT_MASK_PKT_NUM_Q1_V1) +/* 2 REG_PCIE_H2C_MSG_V1 (Offset 0x03E0) */ +#define BIT_AC7Q_EMPTY BIT(7) +#define BIT_AC6Q_EMPTY BIT(6) +#define BIT_AC5Q_EMPTY BIT(5) +#define BIT_AC4Q_EMPTY BIT(4) +#define BIT_AC3Q_EMPTY BIT(3) +#define BIT_AC2Q_EMPTY BIT(2) +#define BIT_AC1Q_EMPTY BIT(1) -#define BIT_SHIFT_HEAD_PKT_Q1 0 -#define BIT_MASK_HEAD_PKT_Q1 0xff -#define BIT_HEAD_PKT_Q1(x) (((x) & BIT_MASK_HEAD_PKT_Q1) << BIT_SHIFT_HEAD_PKT_Q1) -#define BIT_GET_HEAD_PKT_Q1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1) & BIT_MASK_HEAD_PKT_Q1) +#define BIT_SHIFT_DRV2FW_INFO 0 +#define BIT_MASK_DRV2FW_INFO 0xffffffffL +#define BIT_DRV2FW_INFO(x) \ + (((x) & BIT_MASK_DRV2FW_INFO) << BIT_SHIFT_DRV2FW_INFO) +#define BITS_DRV2FW_INFO (BIT_MASK_DRV2FW_INFO << BIT_SHIFT_DRV2FW_INFO) +#define BIT_CLEAR_DRV2FW_INFO(x) ((x) & (~BITS_DRV2FW_INFO)) +#define BIT_GET_DRV2FW_INFO(x) \ + (((x) >> BIT_SHIFT_DRV2FW_INFO) & BIT_MASK_DRV2FW_INFO) +#define BIT_SET_DRV2FW_INFO(x, v) \ + (BIT_CLEAR_DRV2FW_INFO(x) | BIT_DRV2FW_INFO(v)) +#define BIT_AC0Q_EMPTY BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PCIE_C2H_MSG_V1 (Offset 0x03E4) */ +#define BIT_SHIFT_HCI_PCIE_C2H_MSG 0 +#define BIT_MASK_HCI_PCIE_C2H_MSG 0xffffffffL +#define BIT_HCI_PCIE_C2H_MSG(x) \ + (((x) & BIT_MASK_HCI_PCIE_C2H_MSG) << BIT_SHIFT_HCI_PCIE_C2H_MSG) +#define BITS_HCI_PCIE_C2H_MSG \ + (BIT_MASK_HCI_PCIE_C2H_MSG << BIT_SHIFT_HCI_PCIE_C2H_MSG) +#define BIT_CLEAR_HCI_PCIE_C2H_MSG(x) ((x) & (~BITS_HCI_PCIE_C2H_MSG)) +#define BIT_GET_HCI_PCIE_C2H_MSG(x) \ + (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG) & BIT_MASK_HCI_PCIE_C2H_MSG) +#define BIT_SET_HCI_PCIE_C2H_MSG(x, v) \ + (BIT_CLEAR_HCI_PCIE_C2H_MSG(x) | BIT_HCI_PCIE_C2H_MSG(v)) -/* 2 REG_Q1_INFO (Offset 0x0404) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q1_V1 0 -#define BIT_MASK_HEAD_PKT_Q1_V1 0x7ff -#define BIT_HEAD_PKT_Q1_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1) << BIT_SHIFT_HEAD_PKT_Q1_V1) -#define BIT_GET_HEAD_PKT_Q1_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1) & BIT_MASK_HEAD_PKT_Q1_V1) +/* 2 REG_HCI_C2H_MSG_V1 (Offset 0x03E4) */ +#define BIT_SHIFT_HCI_C2H_MSG 0 +#define BIT_MASK_HCI_C2H_MSG 0xffffffffL +#define BIT_HCI_C2H_MSG(x) \ + (((x) & BIT_MASK_HCI_C2H_MSG) << BIT_SHIFT_HCI_C2H_MSG) +#define BITS_HCI_C2H_MSG (BIT_MASK_HCI_C2H_MSG << BIT_SHIFT_HCI_C2H_MSG) +#define BIT_CLEAR_HCI_C2H_MSG(x) ((x) & (~BITS_HCI_C2H_MSG)) +#define BIT_GET_HCI_C2H_MSG(x) \ + (((x) >> BIT_SHIFT_HCI_C2H_MSG) & BIT_MASK_HCI_C2H_MSG) +#define BIT_SET_HCI_C2H_MSG(x, v) \ + (BIT_CLEAR_HCI_C2H_MSG(x) | BIT_HCI_C2H_MSG(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DBI_WDATA_V1 (Offset 0x03E8) */ +#define BIT_SHIFT_DBI_WDATA 0 +#define BIT_MASK_DBI_WDATA 0xffffffffL +#define BIT_DBI_WDATA(x) (((x) & BIT_MASK_DBI_WDATA) << BIT_SHIFT_DBI_WDATA) +#define BITS_DBI_WDATA (BIT_MASK_DBI_WDATA << BIT_SHIFT_DBI_WDATA) +#define BIT_CLEAR_DBI_WDATA(x) ((x) & (~BITS_DBI_WDATA)) +#define BIT_GET_DBI_WDATA(x) (((x) >> BIT_SHIFT_DBI_WDATA) & BIT_MASK_DBI_WDATA) +#define BIT_SET_DBI_WDATA(x, v) (BIT_CLEAR_DBI_WDATA(x) | BIT_DBI_WDATA(v)) -/* 2 REG_Q2_INFO (Offset 0x0408) */ +/* 2 REG_DBI_RDATA_V1 (Offset 0x03EC) */ +#define BIT_SHIFT_DBI_RDATA 0 +#define BIT_MASK_DBI_RDATA 0xffffffffL +#define BIT_DBI_RDATA(x) (((x) & BIT_MASK_DBI_RDATA) << BIT_SHIFT_DBI_RDATA) +#define BITS_DBI_RDATA (BIT_MASK_DBI_RDATA << BIT_SHIFT_DBI_RDATA) +#define BIT_CLEAR_DBI_RDATA(x) ((x) & (~BITS_DBI_RDATA)) +#define BIT_GET_DBI_RDATA(x) (((x) >> BIT_SHIFT_DBI_RDATA) & BIT_MASK_DBI_RDATA) +#define BIT_SET_DBI_RDATA(x, v) (BIT_CLEAR_DBI_RDATA(x) | BIT_DBI_RDATA(v)) -#define BIT_SHIFT_QUEUEMACID_Q2_V1 25 -#define BIT_MASK_QUEUEMACID_Q2_V1 0x7f -#define BIT_QUEUEMACID_Q2_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1) -#define BIT_GET_QUEUEMACID_Q2_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_QUEUEAC_Q2_V1 23 -#define BIT_MASK_QUEUEAC_Q2_V1 0x3 -#define BIT_QUEUEAC_Q2_V1(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1) -#define BIT_GET_QUEUEAC_Q2_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1) +/* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */ +#define BIT_SHIFT_LOOPBACK_DBG_SEL 28 +#define BIT_MASK_LOOPBACK_DBG_SEL 0xf +#define BIT_LOOPBACK_DBG_SEL(x) \ + (((x) & BIT_MASK_LOOPBACK_DBG_SEL) << BIT_SHIFT_LOOPBACK_DBG_SEL) +#define BITS_LOOPBACK_DBG_SEL \ + (BIT_MASK_LOOPBACK_DBG_SEL << BIT_SHIFT_LOOPBACK_DBG_SEL) +#define BIT_CLEAR_LOOPBACK_DBG_SEL(x) ((x) & (~BITS_LOOPBACK_DBG_SEL)) +#define BIT_GET_LOOPBACK_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_LOOPBACK_DBG_SEL) & BIT_MASK_LOOPBACK_DBG_SEL) +#define BIT_SET_LOOPBACK_DBG_SEL(x, v) \ + (BIT_CLEAR_LOOPBACK_DBG_SEL(x) | BIT_LOOPBACK_DBG_SEL(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */ +#define BIT_EN_STUCK_DBG BIT(26) +#define BIT_RX_STUCK BIT(25) +#define BIT_TX_STUCK BIT(24) +#define BIT_DBI_RFLAG BIT(17) +#define BIT_DBI_WFLAG BIT(16) + +#define BIT_SHIFT_DBI_WREN 12 +#define BIT_MASK_DBI_WREN 0xf +#define BIT_DBI_WREN(x) (((x) & BIT_MASK_DBI_WREN) << BIT_SHIFT_DBI_WREN) +#define BITS_DBI_WREN (BIT_MASK_DBI_WREN << BIT_SHIFT_DBI_WREN) +#define BIT_CLEAR_DBI_WREN(x) ((x) & (~BITS_DBI_WREN)) +#define BIT_GET_DBI_WREN(x) (((x) >> BIT_SHIFT_DBI_WREN) & BIT_MASK_DBI_WREN) +#define BIT_SET_DBI_WREN(x, v) (BIT_CLEAR_DBI_WREN(x) | BIT_DBI_WREN(v)) + +#define BIT_SHIFT_DBI_ADDR 0 +#define BIT_MASK_DBI_ADDR 0xfff +#define BIT_DBI_ADDR(x) (((x) & BIT_MASK_DBI_ADDR) << BIT_SHIFT_DBI_ADDR) +#define BITS_DBI_ADDR (BIT_MASK_DBI_ADDR << BIT_SHIFT_DBI_ADDR) +#define BIT_CLEAR_DBI_ADDR(x) ((x) & (~BITS_DBI_ADDR)) +#define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR) +#define BIT_SET_DBI_ADDR(x, v) (BIT_CLEAR_DBI_ADDR(x) | BIT_DBI_ADDR(v)) -/* 2 REG_Q2_INFO (Offset 0x0408) */ +/* 2 REG_MDIO_V1 (Offset 0x03F4) */ -#define BIT_TIDEMPTY_Q2_V1 BIT(22) +#define BIT_SHIFT_MDIO_RDATA 16 +#define BIT_MASK_MDIO_RDATA 0xffff +#define BIT_MDIO_RDATA(x) (((x) & BIT_MASK_MDIO_RDATA) << BIT_SHIFT_MDIO_RDATA) +#define BITS_MDIO_RDATA (BIT_MASK_MDIO_RDATA << BIT_SHIFT_MDIO_RDATA) +#define BIT_CLEAR_MDIO_RDATA(x) ((x) & (~BITS_MDIO_RDATA)) +#define BIT_GET_MDIO_RDATA(x) \ + (((x) >> BIT_SHIFT_MDIO_RDATA) & BIT_MASK_MDIO_RDATA) +#define BIT_SET_MDIO_RDATA(x, v) (BIT_CLEAR_MDIO_RDATA(x) | BIT_MDIO_RDATA(v)) + +#define BIT_SHIFT_MDIO_WDATA 0 +#define BIT_MASK_MDIO_WDATA 0xffff +#define BIT_MDIO_WDATA(x) (((x) & BIT_MASK_MDIO_WDATA) << BIT_SHIFT_MDIO_WDATA) +#define BITS_MDIO_WDATA (BIT_MASK_MDIO_WDATA << BIT_SHIFT_MDIO_WDATA) +#define BIT_CLEAR_MDIO_WDATA(x) ((x) & (~BITS_MDIO_WDATA)) +#define BIT_GET_MDIO_WDATA(x) \ + (((x) >> BIT_SHIFT_MDIO_WDATA) & BIT_MASK_MDIO_WDATA) +#define BIT_SET_MDIO_WDATA(x, v) (BIT_CLEAR_MDIO_WDATA(x) | BIT_MDIO_WDATA(v)) #endif +#if (HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BUS_MIX_CFG (Offset 0x03F8) */ +#define BIT_SHIFT_DELAY_TIME 24 +#define BIT_MASK_DELAY_TIME 0xff +#define BIT_DELAY_TIME(x) (((x) & BIT_MASK_DELAY_TIME) << BIT_SHIFT_DELAY_TIME) +#define BITS_DELAY_TIME (BIT_MASK_DELAY_TIME << BIT_SHIFT_DELAY_TIME) +#define BIT_CLEAR_DELAY_TIME(x) ((x) & (~BITS_DELAY_TIME)) +#define BIT_GET_DELAY_TIME(x) \ + (((x) >> BIT_SHIFT_DELAY_TIME) & BIT_MASK_DELAY_TIME) +#define BIT_SET_DELAY_TIME(x, v) (BIT_CLEAR_DELAY_TIME(x) | BIT_DELAY_TIME(v)) -/* 2 REG_Q2_INFO (Offset 0x0408) */ +#define BIT_RX_TIMER_DELAY_EN BIT(17) + +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q2_V1 15 -#define BIT_MASK_TAIL_PKT_Q2_V1 0xff -#define BIT_TAIL_PKT_Q2_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V1) << BIT_SHIFT_TAIL_PKT_Q2_V1) -#define BIT_GET_TAIL_PKT_Q2_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V1) & BIT_MASK_TAIL_PKT_Q2_V1) +/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ +#define BIT_EN_WATCH_DOG BIT(8) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_MDIO2_V1 (Offset 0x03F8) */ -/* 2 REG_Q2_INFO (Offset 0x0408) */ +#define BIT_ECRC_EN BIT(7) +#define BIT_MDIO_RFLAG BIT(6) +#define BIT_MDIO_WFLAG BIT(5) +#endif -#define BIT_SHIFT_TAIL_PKT_Q2_V2 11 -#define BIT_MASK_TAIL_PKT_Q2_V2 0x7ff -#define BIT_TAIL_PKT_Q2_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2) << BIT_SHIFT_TAIL_PKT_Q2_V2) -#define BIT_GET_TAIL_PKT_Q2_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2) & BIT_MASK_TAIL_PKT_Q2_V2) +#if (HALMAC_8192E_SUPPORT) +/* 2 REG_MDIO2_V1 (Offset 0x03F8) */ -#endif +#define BIT_SHIFT_MDIO_ADDR 0 +#define BIT_MASK_MDIO_ADDR 0x1f +#define BIT_MDIO_ADDR(x) (((x) & BIT_MASK_MDIO_ADDR) << BIT_SHIFT_MDIO_ADDR) +#define BITS_MDIO_ADDR (BIT_MASK_MDIO_ADDR << BIT_SHIFT_MDIO_ADDR) +#define BIT_CLEAR_MDIO_ADDR(x) ((x) & (~BITS_MDIO_ADDR)) +#define BIT_GET_MDIO_ADDR(x) (((x) >> BIT_SHIFT_MDIO_ADDR) & BIT_MASK_MDIO_ADDR) +#define BIT_SET_MDIO_ADDR(x, v) (BIT_CLEAR_MDIO_ADDR(x) | BIT_MDIO_ADDR(v)) +#define BIT_SHIFT_TXFAIL_DROPCNT 0 +#define BIT_MASK_TXFAIL_DROPCNT 0xffff +#define BIT_TXFAIL_DROPCNT(x) \ + (((x) & BIT_MASK_TXFAIL_DROPCNT) << BIT_SHIFT_TXFAIL_DROPCNT) +#define BITS_TXFAIL_DROPCNT \ + (BIT_MASK_TXFAIL_DROPCNT << BIT_SHIFT_TXFAIL_DROPCNT) +#define BIT_CLEAR_TXFAIL_DROPCNT(x) ((x) & (~BITS_TXFAIL_DROPCNT)) +#define BIT_GET_TXFAIL_DROPCNT(x) \ + (((x) >> BIT_SHIFT_TXFAIL_DROPCNT) & BIT_MASK_TXFAIL_DROPCNT) +#define BIT_SET_TXFAIL_DROPCNT(x, v) \ + (BIT_CLEAR_TXFAIL_DROPCNT(x) | BIT_TXFAIL_DROPCNT(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_Q2_INFO (Offset 0x0408) */ +/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ +#define BIT_SHIFT_MDIO_REG_ADDR_V1 0 +#define BIT_MASK_MDIO_REG_ADDR_V1 0x1f +#define BIT_MDIO_REG_ADDR_V1(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1) +#define BITS_MDIO_REG_ADDR_V1 \ + (BIT_MASK_MDIO_REG_ADDR_V1 << BIT_SHIFT_MDIO_REG_ADDR_V1) +#define BIT_CLEAR_MDIO_REG_ADDR_V1(x) ((x) & (~BITS_MDIO_REG_ADDR_V1)) +#define BIT_GET_MDIO_REG_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1) & BIT_MASK_MDIO_REG_ADDR_V1) +#define BIT_SET_MDIO_REG_ADDR_V1(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR_V1(x) | BIT_MDIO_REG_ADDR_V1(v)) -#define BIT_SHIFT_PKT_NUM_Q2_V1 8 -#define BIT_MASK_PKT_NUM_Q2_V1 0x7f -#define BIT_PKT_NUM_Q2_V1(x) (((x) & BIT_MASK_PKT_NUM_Q2_V1) << BIT_SHIFT_PKT_NUM_Q2_V1) -#define BIT_GET_PKT_NUM_Q2_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q2_V1) & BIT_MASK_PKT_NUM_Q2_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q2 0 -#define BIT_MASK_HEAD_PKT_Q2 0xff -#define BIT_HEAD_PKT_Q2(x) (((x) & BIT_MASK_HEAD_PKT_Q2) << BIT_SHIFT_HEAD_PKT_Q2) -#define BIT_GET_HEAD_PKT_Q2(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2) & BIT_MASK_HEAD_PKT_Q2) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_RXRST_BACKDOOR BIT(31) +#define BIT_TXRST_BACKDOOR BIT(30) +#define BIT_RXIDX_RSTB BIT(29) +#define BIT_TXIDX_RSTB BIT(28) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_SHIFT_WATCH_DOG_TIMER 28 +#define BIT_MASK_WATCH_DOG_TIMER 0xf +#define BIT_WATCH_DOG_TIMER(x) \ + (((x) & BIT_MASK_WATCH_DOG_TIMER) << BIT_SHIFT_WATCH_DOG_TIMER) +#define BITS_WATCH_DOG_TIMER \ + (BIT_MASK_WATCH_DOG_TIMER << BIT_SHIFT_WATCH_DOG_TIMER) +#define BIT_CLEAR_WATCH_DOG_TIMER(x) ((x) & (~BITS_WATCH_DOG_TIMER)) +#define BIT_GET_WATCH_DOG_TIMER(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_TIMER) & BIT_MASK_WATCH_DOG_TIMER) +#define BIT_SET_WATCH_DOG_TIMER(x, v) \ + (BIT_CLEAR_WATCH_DOG_TIMER(x) | BIT_WATCH_DOG_TIMER(v)) -/* 2 REG_Q2_INFO (Offset 0x0408) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q2_V1 0 -#define BIT_MASK_HEAD_PKT_Q2_V1 0x7ff -#define BIT_HEAD_PKT_Q2_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1) << BIT_SHIFT_HEAD_PKT_Q2_V1) -#define BIT_GET_HEAD_PKT_Q2_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1) & BIT_MASK_HEAD_PKT_Q2_V1) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_DROP_NEXT_RXPKT BIT(27) +#define BIT_SHORT_CORE_RST_SEL BIT(26) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EXCEPT_RESUME_EN BIT(25) +#define BIT_EXCEPT_RESUME_FLAG BIT(24) -/* 2 REG_Q3_INFO (Offset 0x040C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_QUEUEMACID_Q3_V1 25 -#define BIT_MASK_QUEUEMACID_Q3_V1 0x7f -#define BIT_QUEUEMACID_Q3_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1) -#define BIT_GET_QUEUEMACID_Q3_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_ALIGN_MTU BIT(23) -#define BIT_SHIFT_QUEUEAC_Q3_V1 23 -#define BIT_MASK_QUEUEAC_Q3_V1 0x3 -#define BIT_QUEUEAC_Q3_V1(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1) -#define BIT_GET_QUEUEAC_Q3_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_ALIGN_MTU BIT(23) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814AMP_SUPPORT) -/* 2 REG_Q3_INFO (Offset 0x040C) */ +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ -#define BIT_TIDEMPTY_Q3_V1 BIT(22) +#define BIT_EARLY_TAG_RETURN BIT(22) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_SHIFT_LATENCY_CONTROL 21 +#define BIT_MASK_LATENCY_CONTROL 0x3 +#define BIT_LATENCY_CONTROL(x) \ + (((x) & BIT_MASK_LATENCY_CONTROL) << BIT_SHIFT_LATENCY_CONTROL) +#define BITS_LATENCY_CONTROL \ + (BIT_MASK_LATENCY_CONTROL << BIT_SHIFT_LATENCY_CONTROL) +#define BIT_CLEAR_LATENCY_CONTROL(x) ((x) & (~BITS_LATENCY_CONTROL)) +#define BIT_GET_LATENCY_CONTROL(x) \ + (((x) >> BIT_SHIFT_LATENCY_CONTROL) & BIT_MASK_LATENCY_CONTROL) +#define BIT_SET_LATENCY_CONTROL(x, v) \ + (BIT_CLEAR_LATENCY_CONTROL(x) | BIT_LATENCY_CONTROL(v)) -/* 2 REG_Q3_INFO (Offset 0x040C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q3_V1 15 -#define BIT_MASK_TAIL_PKT_Q3_V1 0xff -#define BIT_TAIL_PKT_Q3_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V1) << BIT_SHIFT_TAIL_PKT_Q3_V1) -#define BIT_GET_TAIL_PKT_Q3_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V1) & BIT_MASK_TAIL_PKT_Q3_V1) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_HOST_GEN2_SUPPORT BIT(20) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_SHIFT_TXDMA_ERR_FLAG 16 +#define BIT_MASK_TXDMA_ERR_FLAG 0xf +#define BIT_TXDMA_ERR_FLAG(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG) << BIT_SHIFT_TXDMA_ERR_FLAG) +#define BITS_TXDMA_ERR_FLAG \ + (BIT_MASK_TXDMA_ERR_FLAG << BIT_SHIFT_TXDMA_ERR_FLAG) +#define BIT_CLEAR_TXDMA_ERR_FLAG(x) ((x) & (~BITS_TXDMA_ERR_FLAG)) +#define BIT_GET_TXDMA_ERR_FLAG(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG) & BIT_MASK_TXDMA_ERR_FLAG) +#define BIT_SET_TXDMA_ERR_FLAG(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG(x) | BIT_TXDMA_ERR_FLAG(v)) -/* 2 REG_Q3_INFO (Offset 0x040C) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q3_V2 11 -#define BIT_MASK_TAIL_PKT_Q3_V2 0x7ff -#define BIT_TAIL_PKT_Q3_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2) << BIT_SHIFT_TAIL_PKT_Q3_V2) -#define BIT_GET_TAIL_PKT_Q3_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2) & BIT_MASK_TAIL_PKT_Q3_V2) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_SHIFT_TXDMA_ERR_FLAG_V1 15 +#define BIT_MASK_TXDMA_ERR_FLAG_V1 0x1f +#define BIT_TXDMA_ERR_FLAG_V1(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG_V1) << BIT_SHIFT_TXDMA_ERR_FLAG_V1) +#define BITS_TXDMA_ERR_FLAG_V1 \ + (BIT_MASK_TXDMA_ERR_FLAG_V1 << BIT_SHIFT_TXDMA_ERR_FLAG_V1) +#define BIT_CLEAR_TXDMA_ERR_FLAG_V1(x) ((x) & (~BITS_TXDMA_ERR_FLAG_V1)) +#define BIT_GET_TXDMA_ERR_FLAG_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1) & BIT_MASK_TXDMA_ERR_FLAG_V1) +#define BIT_SET_TXDMA_ERR_FLAG_V1(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG_V1(x) | BIT_TXDMA_ERR_FLAG_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ -/* 2 REG_Q3_INFO (Offset 0x040C) */ +#define BIT_SHIFT_EARLY_MODE_SEL 12 +#define BIT_MASK_EARLY_MODE_SEL 0xf +#define BIT_EARLY_MODE_SEL(x) \ + (((x) & BIT_MASK_EARLY_MODE_SEL) << BIT_SHIFT_EARLY_MODE_SEL) +#define BITS_EARLY_MODE_SEL \ + (BIT_MASK_EARLY_MODE_SEL << BIT_SHIFT_EARLY_MODE_SEL) +#define BIT_CLEAR_EARLY_MODE_SEL(x) ((x) & (~BITS_EARLY_MODE_SEL)) +#define BIT_GET_EARLY_MODE_SEL(x) \ + (((x) >> BIT_SHIFT_EARLY_MODE_SEL) & BIT_MASK_EARLY_MODE_SEL) +#define BIT_SET_EARLY_MODE_SEL(x, v) \ + (BIT_CLEAR_EARLY_MODE_SEL(x) | BIT_EARLY_MODE_SEL(v)) +#endif -#define BIT_SHIFT_PKT_NUM_Q3_V1 8 -#define BIT_MASK_PKT_NUM_Q3_V1 0x7f -#define BIT_PKT_NUM_Q3_V1(x) (((x) & BIT_MASK_PKT_NUM_Q3_V1) << BIT_SHIFT_PKT_NUM_Q3_V1) -#define BIT_GET_PKT_NUM_Q3_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q3_V1) & BIT_MASK_PKT_NUM_Q3_V1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ -#define BIT_SHIFT_HEAD_PKT_Q3 0 -#define BIT_MASK_HEAD_PKT_Q3 0xff -#define BIT_HEAD_PKT_Q3(x) (((x) & BIT_MASK_HEAD_PKT_Q3) << BIT_SHIFT_HEAD_PKT_Q3) -#define BIT_GET_HEAD_PKT_Q3(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3) & BIT_MASK_HEAD_PKT_Q3) +#define BIT_EPHY_RX50_EN BIT(11) +#define BIT_SHIFT_MSI_TIMEOUT_ID_V1 8 +#define BIT_MASK_MSI_TIMEOUT_ID_V1 0x7 +#define BIT_MSI_TIMEOUT_ID_V1(x) \ + (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1) << BIT_SHIFT_MSI_TIMEOUT_ID_V1) +#define BITS_MSI_TIMEOUT_ID_V1 \ + (BIT_MASK_MSI_TIMEOUT_ID_V1 << BIT_SHIFT_MSI_TIMEOUT_ID_V1) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1(x) ((x) & (~BITS_MSI_TIMEOUT_ID_V1)) +#define BIT_GET_MSI_TIMEOUT_ID_V1(x) \ + (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1) & BIT_MASK_MSI_TIMEOUT_ID_V1) +#define BIT_SET_MSI_TIMEOUT_ID_V1(x, v) \ + (BIT_CLEAR_MSI_TIMEOUT_ID_V1(x) | BIT_MSI_TIMEOUT_ID_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_SHIFT_RXDMA_ERR_CNT 8 +#define BIT_MASK_RXDMA_ERR_CNT 0xff +#define BIT_RXDMA_ERR_CNT(x) \ + (((x) & BIT_MASK_RXDMA_ERR_CNT) << BIT_SHIFT_RXDMA_ERR_CNT) +#define BITS_RXDMA_ERR_CNT (BIT_MASK_RXDMA_ERR_CNT << BIT_SHIFT_RXDMA_ERR_CNT) +#define BIT_CLEAR_RXDMA_ERR_CNT(x) ((x) & (~BITS_RXDMA_ERR_CNT)) +#define BIT_GET_RXDMA_ERR_CNT(x) \ + (((x) >> BIT_SHIFT_RXDMA_ERR_CNT) & BIT_MASK_RXDMA_ERR_CNT) +#define BIT_SET_RXDMA_ERR_CNT(x, v) \ + (BIT_CLEAR_RXDMA_ERR_CNT(x) | BIT_RXDMA_ERR_CNT(v)) -/* 2 REG_Q3_INFO (Offset 0x040C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q3_V1 0 -#define BIT_MASK_HEAD_PKT_Q3_V1 0x7ff -#define BIT_HEAD_PKT_Q3_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1) << BIT_SHIFT_HEAD_PKT_Q3_V1) -#define BIT_GET_HEAD_PKT_Q3_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1) & BIT_MASK_HEAD_PKT_Q3_V1) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_RADDR_RD BIT(7) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_TXDMA_ERR_HANDLE_REQ BIT(7) -/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_QUEUEMACID_MGQ_V1 25 -#define BIT_MASK_QUEUEMACID_MGQ_V1 0x7f -#define BIT_QUEUEMACID_MGQ_V1(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1) -#define BIT_GET_QUEUEMACID_MGQ_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_MUL_TAG BIT(6) -#define BIT_SHIFT_QUEUEAC_MGQ_V1 23 -#define BIT_MASK_QUEUEAC_MGQ_V1 0x3 -#define BIT_QUEUEAC_MGQ_V1(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1) -#define BIT_GET_QUEUEAC_MGQ_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_TXDMA_ERROR_PS BIT(6) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_MGQ_INFO (Offset 0x0410) */ +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ -#define BIT_TIDEMPTY_MGQ_V1 BIT(22) +#define BIT_L1OFF_PWR_OFF_EN BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_EARLY_MODE BIT(5) -/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_MGQ_V1 15 -#define BIT_MASK_TAIL_PKT_MGQ_V1 0xff -#define BIT_TAIL_PKT_MGQ_V1(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V1) << BIT_SHIFT_TAIL_PKT_MGQ_V1) -#define BIT_GET_TAIL_PKT_MGQ_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V1) & BIT_MASK_TAIL_PKT_MGQ_V1) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_TXDMA_STUCK_ERR_HANDLE BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_L0S_LINK_OFF BIT(4) -/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_MGQ_V2 11 -#define BIT_MASK_TAIL_PKT_MGQ_V2 0x7ff -#define BIT_TAIL_PKT_MGQ_V2(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2) << BIT_SHIFT_TAIL_PKT_MGQ_V2) -#define BIT_GET_TAIL_PKT_MGQ_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2) & BIT_MASK_TAIL_PKT_MGQ_V2) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_TXDMA_RTN_ERR_HANDLE BIT(4) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_ACT_LINK_OFF BIT(3) -/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_RXDMA_ERR_HANDLE_REQ BIT(3) -#define BIT_SHIFT_PKT_NUM_MGQ_V1 8 -#define BIT_MASK_PKT_NUM_MGQ_V1 0x7f -#define BIT_PKT_NUM_MGQ_V1(x) (((x) & BIT_MASK_PKT_NUM_MGQ_V1) << BIT_SHIFT_PKT_NUM_MGQ_V1) -#define BIT_GET_PKT_NUM_MGQ_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_MGQ_V1) & BIT_MASK_PKT_NUM_MGQ_V1) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_MGQ 0 -#define BIT_MASK_HEAD_PKT_MGQ 0xff -#define BIT_HEAD_PKT_MGQ(x) (((x) & BIT_MASK_HEAD_PKT_MGQ) << BIT_SHIFT_HEAD_PKT_MGQ) -#define BIT_GET_HEAD_PKT_MGQ(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ) & BIT_MASK_HEAD_PKT_MGQ) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_SLOW_MAC_TX BIT(2) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_RXDMA_ERROR_PS BIT(2) -/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_MGQ_V1 0 -#define BIT_MASK_HEAD_PKT_MGQ_V1 0x7ff -#define BIT_HEAD_PKT_MGQ_V1(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1) << BIT_SHIFT_HEAD_PKT_MGQ_V1) -#define BIT_GET_HEAD_PKT_MGQ_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1) & BIT_MASK_HEAD_PKT_MGQ_V1) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_SLOW_MAC_RX BIT(1) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_EN_RXDMA_STUCK_ERR_HANDLE BIT(1) +#define BIT_EN_SLOW_MAC_HW BIT(0) +#define BIT_EN_RXDMA_RTN_ERR_HANDLE BIT(0) +#endif -/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q0_INFO (Offset 0x0400) */ -#define BIT_SHIFT_QUEUEMACID_HIQ_V1 25 -#define BIT_MASK_QUEUEMACID_HIQ_V1 0x7f -#define BIT_QUEUEMACID_HIQ_V1(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1) -#define BIT_GET_QUEUEMACID_HIQ_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1) +#define BIT_SHIFT_QUEUEMACID_Q0_V1 25 +#define BIT_MASK_QUEUEMACID_Q0_V1 0x7f +#define BIT_QUEUEMACID_Q0_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1) +#define BITS_QUEUEMACID_Q0_V1 \ + (BIT_MASK_QUEUEMACID_Q0_V1 << BIT_SHIFT_QUEUEMACID_Q0_V1) +#define BIT_CLEAR_QUEUEMACID_Q0_V1(x) ((x) & (~BITS_QUEUEMACID_Q0_V1)) +#define BIT_GET_QUEUEMACID_Q0_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1) +#define BIT_SET_QUEUEMACID_Q0_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q0_V1(x) | BIT_QUEUEMACID_Q0_V1(v)) +#endif -#define BIT_SHIFT_QUEUEAC_HIQ_V1 23 -#define BIT_MASK_QUEUEAC_HIQ_V1 0x3 -#define BIT_QUEUEAC_HIQ_V1(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1) -#define BIT_GET_QUEUEAC_HIQ_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1) +#if (HALMAC_8198F_SUPPORT) +/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ -#endif +#define BIT_SHIFT_QUEUEMACID 25 +#define BIT_MASK_QUEUEMACID 0x7f +#define BIT_QUEUEMACID(x) (((x) & BIT_MASK_QUEUEMACID) << BIT_SHIFT_QUEUEMACID) +#define BITS_QUEUEMACID (BIT_MASK_QUEUEMACID << BIT_SHIFT_QUEUEMACID) +#define BIT_CLEAR_QUEUEMACID(x) ((x) & (~BITS_QUEUEMACID)) +#define BIT_GET_QUEUEMACID(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID) & BIT_MASK_QUEUEMACID) +#define BIT_SET_QUEUEMACID(x, v) (BIT_CLEAR_QUEUEMACID(x) | BIT_QUEUEMACID(v)) +#define BIT_DONE BIT(24) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_HIQ_INFO (Offset 0x0414) */ +/* 2 REG_Q0_INFO (Offset 0x0400) */ -#define BIT_TIDEMPTY_HIQ_V1 BIT(22) +#define BIT_SHIFT_QUEUEAC_Q0_V1 23 +#define BIT_MASK_QUEUEAC_Q0_V1 0x3 +#define BIT_QUEUEAC_Q0_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1) +#define BITS_QUEUEAC_Q0_V1 (BIT_MASK_QUEUEAC_Q0_V1 << BIT_SHIFT_QUEUEAC_Q0_V1) +#define BIT_CLEAR_QUEUEAC_Q0_V1(x) ((x) & (~BITS_QUEUEAC_Q0_V1)) +#define BIT_GET_QUEUEAC_Q0_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1) +#define BIT_SET_QUEUEAC_Q0_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q0_V1(x) | BIT_QUEUEAC_Q0_V1(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ +#define BIT_SHIFT_QUEUEAC 23 +#define BIT_MASK_QUEUEAC 0x3 +#define BIT_QUEUEAC(x) (((x) & BIT_MASK_QUEUEAC) << BIT_SHIFT_QUEUEAC) +#define BITS_QUEUEAC (BIT_MASK_QUEUEAC << BIT_SHIFT_QUEUEAC) +#define BIT_CLEAR_QUEUEAC(x) ((x) & (~BITS_QUEUEAC)) +#define BIT_GET_QUEUEAC(x) (((x) >> BIT_SHIFT_QUEUEAC) & BIT_MASK_QUEUEAC) +#define BIT_SET_QUEUEAC(x, v) (BIT_CLEAR_QUEUEAC(x) | BIT_QUEUEAC(v)) -/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_HIQ_V1 15 -#define BIT_MASK_TAIL_PKT_HIQ_V1 0xff -#define BIT_TAIL_PKT_HIQ_V1(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V1) << BIT_SHIFT_TAIL_PKT_HIQ_V1) -#define BIT_GET_TAIL_PKT_HIQ_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V1) & BIT_MASK_TAIL_PKT_HIQ_V1) +/* 2 REG_Q0_INFO (Offset 0x0400) */ +#define BIT_TIDEMPTY_Q0_V1 BIT(22) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ +#define BIT_TIDEMPTY BIT(22) -/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_ACCWBITEN 20 +#define BIT_MASK_ACCWBITEN 0xf +#define BIT_ACCWBITEN(x) (((x) & BIT_MASK_ACCWBITEN) << BIT_SHIFT_ACCWBITEN) +#define BITS_ACCWBITEN (BIT_MASK_ACCWBITEN << BIT_SHIFT_ACCWBITEN) +#define BIT_CLEAR_ACCWBITEN(x) ((x) & (~BITS_ACCWBITEN)) +#define BIT_GET_ACCWBITEN(x) (((x) >> BIT_SHIFT_ACCWBITEN) & BIT_MASK_ACCWBITEN) +#define BIT_SET_ACCWBITEN(x, v) (BIT_CLEAR_ACCWBITEN(x) | BIT_ACCWBITEN(v)) +#define BIT_BCNQ_EMPTY_V1 BIT(19) +#define BIT_HIQ_EMPTY_V1 BIT(18) +#define BIT_MQQ_EMPTY_V1 BIT(17) -#define BIT_SHIFT_TAIL_PKT_HIQ_V2 11 -#define BIT_MASK_TAIL_PKT_HIQ_V2 0x7ff -#define BIT_TAIL_PKT_HIQ_V2(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2) << BIT_SHIFT_TAIL_PKT_HIQ_V2) -#define BIT_GET_TAIL_PKT_HIQ_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2) & BIT_MASK_TAIL_PKT_HIQ_V2) +#define BIT_SHIFT_COL_CNT 16 +#define BIT_MASK_COL_CNT 0xf +#define BIT_COL_CNT(x) (((x) & BIT_MASK_COL_CNT) << BIT_SHIFT_COL_CNT) +#define BITS_COL_CNT (BIT_MASK_COL_CNT << BIT_SHIFT_COL_CNT) +#define BIT_CLEAR_COL_CNT(x) ((x) & (~BITS_COL_CNT)) +#define BIT_GET_COL_CNT(x) (((x) >> BIT_SHIFT_COL_CNT) & BIT_MASK_COL_CNT) +#define BIT_SET_COL_CNT(x, v) (BIT_CLEAR_COL_CNT(x) | BIT_COL_CNT(v)) +#define BIT_CPU_MGT_EMPTY BIT(16) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q0_INFO (Offset 0x0400) */ -/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_TAIL_PKT_Q0_V1 15 +#define BIT_MASK_TAIL_PKT_Q0_V1 0xff +#define BIT_TAIL_PKT_Q0_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q0_V1) << BIT_SHIFT_TAIL_PKT_Q0_V1) +#define BITS_TAIL_PKT_Q0_V1 \ + (BIT_MASK_TAIL_PKT_Q0_V1 << BIT_SHIFT_TAIL_PKT_Q0_V1) +#define BIT_CLEAR_TAIL_PKT_Q0_V1(x) ((x) & (~BITS_TAIL_PKT_Q0_V1)) +#define BIT_GET_TAIL_PKT_Q0_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V1) & BIT_MASK_TAIL_PKT_Q0_V1) +#define BIT_SET_TAIL_PKT_Q0_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q0_V1(x) | BIT_TAIL_PKT_Q0_V1(v)) +#endif -#define BIT_SHIFT_PKT_NUM_HIQ_V1 8 -#define BIT_MASK_PKT_NUM_HIQ_V1 0x7f -#define BIT_PKT_NUM_HIQ_V1(x) (((x) & BIT_MASK_PKT_NUM_HIQ_V1) << BIT_SHIFT_PKT_NUM_HIQ_V1) -#define BIT_GET_PKT_NUM_HIQ_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_HIQ_V1) & BIT_MASK_PKT_NUM_HIQ_V1) +#if (HALMAC_8198F_SUPPORT) +/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ -#define BIT_SHIFT_HEAD_PKT_HIQ 0 -#define BIT_MASK_HEAD_PKT_HIQ 0xff -#define BIT_HEAD_PKT_HIQ(x) (((x) & BIT_MASK_HEAD_PKT_HIQ) << BIT_SHIFT_HEAD_PKT_HIQ) -#define BIT_GET_HEAD_PKT_HIQ(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ) & BIT_MASK_HEAD_PKT_HIQ) +#define BIT_AC_MACID_NOT_SAME BIT(15) +#define BIT_SHIFT_GROUP_TABLE_ID 12 +#define BIT_MASK_GROUP_TABLE_ID 0x7 +#define BIT_GROUP_TABLE_ID(x) \ + (((x) & BIT_MASK_GROUP_TABLE_ID) << BIT_SHIFT_GROUP_TABLE_ID) +#define BITS_GROUP_TABLE_ID \ + (BIT_MASK_GROUP_TABLE_ID << BIT_SHIFT_GROUP_TABLE_ID) +#define BIT_CLEAR_GROUP_TABLE_ID(x) ((x) & (~BITS_GROUP_TABLE_ID)) +#define BIT_GET_GROUP_TABLE_ID(x) \ + (((x) >> BIT_SHIFT_GROUP_TABLE_ID) & BIT_MASK_GROUP_TABLE_ID) +#define BIT_SET_GROUP_TABLE_ID(x, v) \ + (BIT_CLEAR_GROUP_TABLE_ID(x) | BIT_GROUP_TABLE_ID(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_Q0_INFO (Offset 0x0400) */ +#define BIT_SHIFT_TAIL_PKT_Q0_V2 11 +#define BIT_MASK_TAIL_PKT_Q0_V2 0x7ff +#define BIT_TAIL_PKT_Q0_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q0_V2) << BIT_SHIFT_TAIL_PKT_Q0_V2) +#define BITS_TAIL_PKT_Q0_V2 \ + (BIT_MASK_TAIL_PKT_Q0_V2 << BIT_SHIFT_TAIL_PKT_Q0_V2) +#define BIT_CLEAR_TAIL_PKT_Q0_V2(x) ((x) & (~BITS_TAIL_PKT_Q0_V2)) +#define BIT_GET_TAIL_PKT_Q0_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2) & BIT_MASK_TAIL_PKT_Q0_V2) +#define BIT_SET_TAIL_PKT_Q0_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q0_V2(x) | BIT_TAIL_PKT_Q0_V2(v)) -/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_HIQ_V1 0 -#define BIT_MASK_HEAD_PKT_HIQ_V1 0x7ff -#define BIT_HEAD_PKT_HIQ_V1(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1) << BIT_SHIFT_HEAD_PKT_HIQ_V1) -#define BIT_GET_HEAD_PKT_HIQ_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1) & BIT_MASK_HEAD_PKT_HIQ_V1) +/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ +#define BIT_SHIFT_TAIL_PKT 11 +#define BIT_MASK_TAIL_PKT 0x7ff +#define BIT_TAIL_PKT(x) (((x) & BIT_MASK_TAIL_PKT) << BIT_SHIFT_TAIL_PKT) +#define BITS_TAIL_PKT (BIT_MASK_TAIL_PKT << BIT_SHIFT_TAIL_PKT) +#define BIT_CLEAR_TAIL_PKT(x) ((x) & (~BITS_TAIL_PKT)) +#define BIT_GET_TAIL_PKT(x) (((x) >> BIT_SHIFT_TAIL_PKT) & BIT_MASK_TAIL_PKT) +#define BIT_SET_TAIL_PKT(x, v) (BIT_CLEAR_TAIL_PKT(x) | BIT_TAIL_PKT(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q0_INFO (Offset 0x0400) */ -/* 2 REG_BCNQ_INFO (Offset 0x0418) */ +#define BIT_SHIFT_PKT_NUM_Q0_V1 8 +#define BIT_MASK_PKT_NUM_Q0_V1 0x7f +#define BIT_PKT_NUM_Q0_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q0_V1) << BIT_SHIFT_PKT_NUM_Q0_V1) +#define BITS_PKT_NUM_Q0_V1 (BIT_MASK_PKT_NUM_Q0_V1 << BIT_SHIFT_PKT_NUM_Q0_V1) +#define BIT_CLEAR_PKT_NUM_Q0_V1(x) ((x) & (~BITS_PKT_NUM_Q0_V1)) +#define BIT_GET_PKT_NUM_Q0_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q0_V1) & BIT_MASK_PKT_NUM_Q0_V1) +#define BIT_SET_PKT_NUM_Q0_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q0_V1(x) | BIT_PKT_NUM_Q0_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q0 0 +#define BIT_MASK_HEAD_PKT_Q0 0xff +#define BIT_HEAD_PKT_Q0(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q0) << BIT_SHIFT_HEAD_PKT_Q0) +#define BITS_HEAD_PKT_Q0 (BIT_MASK_HEAD_PKT_Q0 << BIT_SHIFT_HEAD_PKT_Q0) +#define BIT_CLEAR_HEAD_PKT_Q0(x) ((x) & (~BITS_HEAD_PKT_Q0)) +#define BIT_GET_HEAD_PKT_Q0(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q0) & BIT_MASK_HEAD_PKT_Q0) +#define BIT_SET_HEAD_PKT_Q0(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q0(x) | BIT_HEAD_PKT_Q0(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_Q0_INFO (Offset 0x0400) */ -#define BIT_SHIFT_PKT_NUM_BCNQ 8 -#define BIT_MASK_PKT_NUM_BCNQ 0xff -#define BIT_PKT_NUM_BCNQ(x) (((x) & BIT_MASK_PKT_NUM_BCNQ) << BIT_SHIFT_PKT_NUM_BCNQ) -#define BIT_GET_PKT_NUM_BCNQ(x) (((x) >> BIT_SHIFT_PKT_NUM_BCNQ) & BIT_MASK_PKT_NUM_BCNQ) +#define BIT_SHIFT_HEAD_PKT_Q0_V1 0 +#define BIT_MASK_HEAD_PKT_Q0_V1 0x7ff +#define BIT_HEAD_PKT_Q0_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q0_V1) << BIT_SHIFT_HEAD_PKT_Q0_V1) +#define BITS_HEAD_PKT_Q0_V1 \ + (BIT_MASK_HEAD_PKT_Q0_V1 << BIT_SHIFT_HEAD_PKT_Q0_V1) +#define BIT_CLEAR_HEAD_PKT_Q0_V1(x) ((x) & (~BITS_HEAD_PKT_Q0_V1)) +#define BIT_GET_HEAD_PKT_Q0_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1) & BIT_MASK_HEAD_PKT_Q0_V1) +#define BIT_SET_HEAD_PKT_Q0_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q0_V1(x) | BIT_HEAD_PKT_Q0_V1(v)) +#endif -#define BIT_SHIFT_BCNQ_HEAD_PG 0 -#define BIT_MASK_BCNQ_HEAD_PG 0xff -#define BIT_BCNQ_HEAD_PG(x) (((x) & BIT_MASK_BCNQ_HEAD_PG) << BIT_SHIFT_BCNQ_HEAD_PG) -#define BIT_GET_BCNQ_HEAD_PG(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG) & BIT_MASK_BCNQ_HEAD_PG) +#if (HALMAC_8198F_SUPPORT) +/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ -#endif +#define BIT_SHIFT_HEAD_PKT 0 +#define BIT_MASK_HEAD_PKT 0x7ff +#define BIT_HEAD_PKT(x) (((x) & BIT_MASK_HEAD_PKT) << BIT_SHIFT_HEAD_PKT) +#define BITS_HEAD_PKT (BIT_MASK_HEAD_PKT << BIT_SHIFT_HEAD_PKT) +#define BIT_CLEAR_HEAD_PKT(x) ((x) & (~BITS_HEAD_PKT)) +#define BIT_GET_HEAD_PKT(x) (((x) >> BIT_SHIFT_HEAD_PKT) & BIT_MASK_HEAD_PKT) +#define BIT_SET_HEAD_PKT(x, v) (BIT_CLEAR_HEAD_PKT(x) | BIT_HEAD_PKT(v)) +#define BIT_SHIFT_PKT_NUMBER 0 +#define BIT_MASK_PKT_NUMBER 0xfff +#define BIT_PKT_NUMBER(x) (((x) & BIT_MASK_PKT_NUMBER) << BIT_SHIFT_PKT_NUMBER) +#define BITS_PKT_NUMBER (BIT_MASK_PKT_NUMBER << BIT_SHIFT_PKT_NUMBER) +#define BIT_CLEAR_PKT_NUMBER(x) ((x) & (~BITS_PKT_NUMBER)) +#define BIT_GET_PKT_NUMBER(x) \ + (((x) >> BIT_SHIFT_PKT_NUMBER) & BIT_MASK_PKT_NUMBER) +#define BIT_SET_PKT_NUMBER(x, v) (BIT_CLEAR_PKT_NUMBER(x) | BIT_PKT_NUMBER(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_ACCW 0 +#define BIT_MASK_ACCW 0x3ff +#define BIT_ACCW(x) (((x) & BIT_MASK_ACCW) << BIT_SHIFT_ACCW) +#define BITS_ACCW (BIT_MASK_ACCW << BIT_SHIFT_ACCW) +#define BIT_CLEAR_ACCW(x) ((x) & (~BITS_ACCW)) +#define BIT_GET_ACCW(x) (((x) >> BIT_SHIFT_ACCW) & BIT_MASK_ACCW) +#define BIT_SET_ACCW(x, v) (BIT_CLEAR_ACCW(x) | BIT_ACCW(v)) +#define BIT_SHIFT_QINFO_INDEX 0 +#define BIT_MASK_QINFO_INDEX 0x1f +#define BIT_QINFO_INDEX(x) \ + (((x) & BIT_MASK_QINFO_INDEX) << BIT_SHIFT_QINFO_INDEX) +#define BITS_QINFO_INDEX (BIT_MASK_QINFO_INDEX << BIT_SHIFT_QINFO_INDEX) +#define BIT_CLEAR_QINFO_INDEX(x) ((x) & (~BITS_QINFO_INDEX)) +#define BIT_GET_QINFO_INDEX(x) \ + (((x) >> BIT_SHIFT_QINFO_INDEX) & BIT_MASK_QINFO_INDEX) +#define BIT_SET_QINFO_INDEX(x, v) \ + (BIT_CLEAR_QINFO_INDEX(x) | BIT_QINFO_INDEX(v)) -/* 2 REG_BCNQ_INFO (Offset 0x0418) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCNQ_HEAD_PG_V1 0 -#define BIT_MASK_BCNQ_HEAD_PG_V1 0xfff -#define BIT_BCNQ_HEAD_PG_V1(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1) << BIT_SHIFT_BCNQ_HEAD_PG_V1) -#define BIT_GET_BCNQ_HEAD_PG_V1(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1) & BIT_MASK_BCNQ_HEAD_PG_V1) +/* 2 REG_QUEUELIST_INFO0 (Offset 0x0400) */ +#define BIT_SHIFT_QINFO0 0 +#define BIT_MASK_QINFO0 0xffffffffL +#define BIT_QINFO0(x) (((x) & BIT_MASK_QINFO0) << BIT_SHIFT_QINFO0) +#define BITS_QINFO0 (BIT_MASK_QINFO0 << BIT_SHIFT_QINFO0) +#define BIT_CLEAR_QINFO0(x) ((x) & (~BITS_QINFO0)) +#define BIT_GET_QINFO0(x) (((x) >> BIT_SHIFT_QINFO0) & BIT_MASK_QINFO0) +#define BIT_SET_QINFO0(x, v) (BIT_CLEAR_QINFO0(x) | BIT_QINFO0(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q1_INFO (Offset 0x0404) */ +#define BIT_SHIFT_QUEUEMACID_Q1_V1 25 +#define BIT_MASK_QUEUEMACID_Q1_V1 0x7f +#define BIT_QUEUEMACID_Q1_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1) +#define BITS_QUEUEMACID_Q1_V1 \ + (BIT_MASK_QUEUEMACID_Q1_V1 << BIT_SHIFT_QUEUEMACID_Q1_V1) +#define BIT_CLEAR_QUEUEMACID_Q1_V1(x) ((x) & (~BITS_QUEUEMACID_Q1_V1)) +#define BIT_GET_QUEUEMACID_Q1_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1) +#define BIT_SET_QUEUEMACID_Q1_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q1_V1(x) | BIT_QUEUEMACID_Q1_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q1_V1 23 +#define BIT_MASK_QUEUEAC_Q1_V1 0x3 +#define BIT_QUEUEAC_Q1_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1) +#define BITS_QUEUEAC_Q1_V1 (BIT_MASK_QUEUEAC_Q1_V1 << BIT_SHIFT_QUEUEAC_Q1_V1) +#define BIT_CLEAR_QUEUEAC_Q1_V1(x) ((x) & (~BITS_QUEUEAC_Q1_V1)) +#define BIT_GET_QUEUEAC_Q1_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1) +#define BIT_SET_QUEUEAC_Q1_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q1_V1(x) | BIT_QUEUEAC_Q1_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TXPKT_EMPTY (Offset 0x041A) */ +/* 2 REG_Q1_INFO (Offset 0x0404) */ -#define BIT_BCNQ_EMPTY BIT(11) -#define BIT_HQQ_EMPTY BIT(10) -#define BIT_MQQ_EMPTY BIT(9) -#define BIT_MGQ_CPU_EMPTY BIT(8) -#define BIT_AC7Q_EMPTY BIT(7) -#define BIT_AC6Q_EMPTY BIT(6) -#define BIT_AC5Q_EMPTY BIT(5) -#define BIT_AC4Q_EMPTY BIT(4) -#define BIT_AC3Q_EMPTY BIT(3) -#define BIT_AC2Q_EMPTY BIT(2) -#define BIT_AC1Q_EMPTY BIT(1) -#define BIT_AC0Q_EMPTY BIT(0) +#define BIT_TIDEMPTY_Q1_V1 BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +/* 2 REG_Q1_INFO (Offset 0x0404) */ -#define BIT_BCN1_POLL BIT(30) +#define BIT_SHIFT_TAIL_PKT_Q1_V1 15 +#define BIT_MASK_TAIL_PKT_Q1_V1 0xff +#define BIT_TAIL_PKT_Q1_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q1_V1) << BIT_SHIFT_TAIL_PKT_Q1_V1) +#define BITS_TAIL_PKT_Q1_V1 \ + (BIT_MASK_TAIL_PKT_Q1_V1 << BIT_SHIFT_TAIL_PKT_Q1_V1) +#define BIT_CLEAR_TAIL_PKT_Q1_V1(x) ((x) & (~BITS_TAIL_PKT_Q1_V1)) +#define BIT_GET_TAIL_PKT_Q1_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V1) & BIT_MASK_TAIL_PKT_Q1_V1) +#define BIT_SET_TAIL_PKT_Q1_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q1_V1(x) | BIT_TAIL_PKT_Q1_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +/* 2 REG_Q1_INFO (Offset 0x0404) */ -#define BIT_CPUMGT_POLL BIT(29) -#define BIT_BCN_POLL BIT(28) +#define BIT_SHIFT_TAIL_PKT_Q1_V2 11 +#define BIT_MASK_TAIL_PKT_Q1_V2 0x7ff +#define BIT_TAIL_PKT_Q1_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q1_V2) << BIT_SHIFT_TAIL_PKT_Q1_V2) +#define BITS_TAIL_PKT_Q1_V2 \ + (BIT_MASK_TAIL_PKT_Q1_V2 << BIT_SHIFT_TAIL_PKT_Q1_V2) +#define BIT_CLEAR_TAIL_PKT_Q1_V2(x) ((x) & (~BITS_TAIL_PKT_Q1_V2)) +#define BIT_GET_TAIL_PKT_Q1_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2) & BIT_MASK_TAIL_PKT_Q1_V2) +#define BIT_SET_TAIL_PKT_Q1_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q1_V2(x) | BIT_TAIL_PKT_Q1_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_Q1_INFO (Offset 0x0404) */ +#define BIT_SHIFT_PKT_NUM_Q1_V1 8 +#define BIT_MASK_PKT_NUM_Q1_V1 0x7f +#define BIT_PKT_NUM_Q1_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q1_V1) << BIT_SHIFT_PKT_NUM_Q1_V1) +#define BITS_PKT_NUM_Q1_V1 (BIT_MASK_PKT_NUM_Q1_V1 << BIT_SHIFT_PKT_NUM_Q1_V1) +#define BIT_CLEAR_PKT_NUM_Q1_V1(x) ((x) & (~BITS_PKT_NUM_Q1_V1)) +#define BIT_GET_PKT_NUM_Q1_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q1_V1) & BIT_MASK_PKT_NUM_Q1_V1) +#define BIT_SET_PKT_NUM_Q1_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q1_V1(x) | BIT_PKT_NUM_Q1_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q1 0 +#define BIT_MASK_HEAD_PKT_Q1 0xff +#define BIT_HEAD_PKT_Q1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q1) << BIT_SHIFT_HEAD_PKT_Q1) +#define BITS_HEAD_PKT_Q1 (BIT_MASK_HEAD_PKT_Q1 << BIT_SHIFT_HEAD_PKT_Q1) +#define BIT_CLEAR_HEAD_PKT_Q1(x) ((x) & (~BITS_HEAD_PKT_Q1)) +#define BIT_GET_HEAD_PKT_Q1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q1) & BIT_MASK_HEAD_PKT_Q1) +#define BIT_SET_HEAD_PKT_Q1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q1(x) | BIT_HEAD_PKT_Q1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +/* 2 REG_Q1_INFO (Offset 0x0404) */ -#define BIT_CPUMGQ_FW_NUM_V1 BIT(12) +#define BIT_SHIFT_HEAD_PKT_Q1_V1 0 +#define BIT_MASK_HEAD_PKT_Q1_V1 0x7ff +#define BIT_HEAD_PKT_Q1_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q1_V1) << BIT_SHIFT_HEAD_PKT_Q1_V1) +#define BITS_HEAD_PKT_Q1_V1 \ + (BIT_MASK_HEAD_PKT_Q1_V1 << BIT_SHIFT_HEAD_PKT_Q1_V1) +#define BIT_CLEAR_HEAD_PKT_Q1_V1(x) ((x) & (~BITS_HEAD_PKT_Q1_V1)) +#define BIT_GET_HEAD_PKT_Q1_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1) & BIT_MASK_HEAD_PKT_Q1_V1) +#define BIT_SET_HEAD_PKT_Q1_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q1_V1(x) | BIT_HEAD_PKT_Q1_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUELIST_INFO1 (Offset 0x0404) */ +#define BIT_SHIFT_QINFO1 0 +#define BIT_MASK_QINFO1 0xffffffffL +#define BIT_QINFO1(x) (((x) & BIT_MASK_QINFO1) << BIT_SHIFT_QINFO1) +#define BITS_QINFO1 (BIT_MASK_QINFO1 << BIT_SHIFT_QINFO1) +#define BIT_CLEAR_QINFO1(x) ((x) & (~BITS_QINFO1)) +#define BIT_GET_QINFO1(x) (((x) >> BIT_SHIFT_QINFO1) & BIT_MASK_QINFO1) +#define BIT_SET_QINFO1(x, v) (BIT_CLEAR_QINFO1(x) | BIT_QINFO1(v)) -/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#endif -#define BIT_CPUMGQ_FW_NUM BIT(8) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CPUMGQ_HEAD_PG 0 -#define BIT_MASK_CPUMGQ_HEAD_PG 0xff -#define BIT_CPUMGQ_HEAD_PG(x) (((x) & BIT_MASK_CPUMGQ_HEAD_PG) << BIT_SHIFT_CPUMGQ_HEAD_PG) -#define BIT_GET_CPUMGQ_HEAD_PG(x) (((x) >> BIT_SHIFT_CPUMGQ_HEAD_PG) & BIT_MASK_CPUMGQ_HEAD_PG) +/* 2 REG_Q2_INFO (Offset 0x0408) */ + +#define BIT_SHIFT_QUEUEMACID_Q2_V1 25 +#define BIT_MASK_QUEUEMACID_Q2_V1 0x7f +#define BIT_QUEUEMACID_Q2_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1) +#define BITS_QUEUEMACID_Q2_V1 \ + (BIT_MASK_QUEUEMACID_Q2_V1 << BIT_SHIFT_QUEUEMACID_Q2_V1) +#define BIT_CLEAR_QUEUEMACID_Q2_V1(x) ((x) & (~BITS_QUEUEMACID_Q2_V1)) +#define BIT_GET_QUEUEMACID_Q2_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1) +#define BIT_SET_QUEUEMACID_Q2_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q2_V1(x) | BIT_QUEUEMACID_Q2_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q2_V1 23 +#define BIT_MASK_QUEUEAC_Q2_V1 0x3 +#define BIT_QUEUEAC_Q2_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1) +#define BITS_QUEUEAC_Q2_V1 (BIT_MASK_QUEUEAC_Q2_V1 << BIT_SHIFT_QUEUEAC_Q2_V1) +#define BIT_CLEAR_QUEUEAC_Q2_V1(x) ((x) & (~BITS_QUEUEAC_Q2_V1)) +#define BIT_GET_QUEUEAC_Q2_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1) +#define BIT_SET_QUEUEAC_Q2_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q2_V1(x) | BIT_QUEUEAC_Q2_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_Q2_INFO (Offset 0x0408) */ +#define BIT_TIDEMPTY_Q2_V1 BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_Q2_INFO (Offset 0x0408) */ +#define BIT_SHIFT_TAIL_PKT_Q2_V1 15 +#define BIT_MASK_TAIL_PKT_Q2_V1 0xff +#define BIT_TAIL_PKT_Q2_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q2_V1) << BIT_SHIFT_TAIL_PKT_Q2_V1) +#define BITS_TAIL_PKT_Q2_V1 \ + (BIT_MASK_TAIL_PKT_Q2_V1 << BIT_SHIFT_TAIL_PKT_Q2_V1) +#define BIT_CLEAR_TAIL_PKT_Q2_V1(x) ((x) & (~BITS_TAIL_PKT_Q2_V1)) +#define BIT_GET_TAIL_PKT_Q2_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V1) & BIT_MASK_TAIL_PKT_Q2_V1) +#define BIT_SET_TAIL_PKT_Q2_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q2_V1(x) | BIT_TAIL_PKT_Q2_V1(v)) -/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_FW_FREE_TAIL_V1 0 -#define BIT_MASK_FW_FREE_TAIL_V1 0xfff -#define BIT_FW_FREE_TAIL_V1(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1) << BIT_SHIFT_FW_FREE_TAIL_V1) -#define BIT_GET_FW_FREE_TAIL_V1(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1) & BIT_MASK_FW_FREE_TAIL_V1) +/* 2 REG_Q2_INFO (Offset 0x0408) */ +#define BIT_SHIFT_TAIL_PKT_Q2_V2 11 +#define BIT_MASK_TAIL_PKT_Q2_V2 0x7ff +#define BIT_TAIL_PKT_Q2_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q2_V2) << BIT_SHIFT_TAIL_PKT_Q2_V2) +#define BITS_TAIL_PKT_Q2_V2 \ + (BIT_MASK_TAIL_PKT_Q2_V2 << BIT_SHIFT_TAIL_PKT_Q2_V2) +#define BIT_CLEAR_TAIL_PKT_Q2_V2(x) ((x) & (~BITS_TAIL_PKT_Q2_V2)) +#define BIT_GET_TAIL_PKT_Q2_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2) & BIT_MASK_TAIL_PKT_Q2_V2) +#define BIT_SET_TAIL_PKT_Q2_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q2_V2(x) | BIT_TAIL_PKT_Q2_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q2_INFO (Offset 0x0408) */ +#define BIT_SHIFT_PKT_NUM_Q2_V1 8 +#define BIT_MASK_PKT_NUM_Q2_V1 0x7f +#define BIT_PKT_NUM_Q2_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q2_V1) << BIT_SHIFT_PKT_NUM_Q2_V1) +#define BITS_PKT_NUM_Q2_V1 (BIT_MASK_PKT_NUM_Q2_V1 << BIT_SHIFT_PKT_NUM_Q2_V1) +#define BIT_CLEAR_PKT_NUM_Q2_V1(x) ((x) & (~BITS_PKT_NUM_Q2_V1)) +#define BIT_GET_PKT_NUM_Q2_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q2_V1) & BIT_MASK_PKT_NUM_Q2_V1) +#define BIT_SET_PKT_NUM_Q2_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q2_V1(x) | BIT_PKT_NUM_Q2_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q2 0 +#define BIT_MASK_HEAD_PKT_Q2 0xff +#define BIT_HEAD_PKT_Q2(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q2) << BIT_SHIFT_HEAD_PKT_Q2) +#define BITS_HEAD_PKT_Q2 (BIT_MASK_HEAD_PKT_Q2 << BIT_SHIFT_HEAD_PKT_Q2) +#define BIT_CLEAR_HEAD_PKT_Q2(x) ((x) & (~BITS_HEAD_PKT_Q2)) +#define BIT_GET_HEAD_PKT_Q2(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q2) & BIT_MASK_HEAD_PKT_Q2) +#define BIT_SET_HEAD_PKT_Q2(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q2(x) | BIT_HEAD_PKT_Q2(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +/* 2 REG_Q2_INFO (Offset 0x0408) */ + +#define BIT_SHIFT_HEAD_PKT_Q2_V1 0 +#define BIT_MASK_HEAD_PKT_Q2_V1 0x7ff +#define BIT_HEAD_PKT_Q2_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q2_V1) << BIT_SHIFT_HEAD_PKT_Q2_V1) +#define BITS_HEAD_PKT_Q2_V1 \ + (BIT_MASK_HEAD_PKT_Q2_V1 << BIT_SHIFT_HEAD_PKT_Q2_V1) +#define BIT_CLEAR_HEAD_PKT_Q2_V1(x) ((x) & (~BITS_HEAD_PKT_Q2_V1)) +#define BIT_GET_HEAD_PKT_Q2_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1) & BIT_MASK_HEAD_PKT_Q2_V1) +#define BIT_SET_HEAD_PKT_Q2_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q2_V1(x) | BIT_HEAD_PKT_Q2_V1(v)) + +#endif -#define BIT_RTS_LIMIT_IN_OFDM BIT(23) -#define BIT_EN_BCNQ_DL BIT(22) -#define BIT_EN_RD_RESP_NAV_BK BIT(21) -#define BIT_EN_WR_FREE_TAIL BIT(20) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_EN_QUEUE_RPT 8 -#define BIT_MASK_EN_QUEUE_RPT 0xff -#define BIT_EN_QUEUE_RPT(x) (((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT) -#define BIT_GET_EN_QUEUE_RPT(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT) +/* 2 REG_QUEUELIST_INFO2 (Offset 0x0408) */ -#define BIT_EN_RTY_BK BIT(7) -#define BIT_EN_USE_INI_RAT BIT(6) -#define BIT_EN_RTS_NAV_BK BIT(5) -#define BIT_DIS_SSN_CHECK BIT(4) -#define BIT_MACID_MATCH_RTS BIT(3) +#define BIT_SHIFT_QINFO2 0 +#define BIT_MASK_QINFO2 0xffffffffL +#define BIT_QINFO2(x) (((x) & BIT_MASK_QINFO2) << BIT_SHIFT_QINFO2) +#define BITS_QINFO2 (BIT_MASK_QINFO2 << BIT_SHIFT_QINFO2) +#define BIT_CLEAR_QINFO2(x) ((x) & (~BITS_QINFO2)) +#define BIT_GET_QINFO2(x) (((x) >> BIT_SHIFT_QINFO2) & BIT_MASK_QINFO2) +#define BIT_SET_QINFO2(x, v) (BIT_CLEAR_QINFO2(x) | BIT_QINFO2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_Q3_INFO (Offset 0x040C) */ +#define BIT_SHIFT_QUEUEMACID_Q3_V1 25 +#define BIT_MASK_QUEUEMACID_Q3_V1 0x7f +#define BIT_QUEUEMACID_Q3_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1) +#define BITS_QUEUEMACID_Q3_V1 \ + (BIT_MASK_QUEUEMACID_Q3_V1 << BIT_SHIFT_QUEUEMACID_Q3_V1) +#define BIT_CLEAR_QUEUEMACID_Q3_V1(x) ((x) & (~BITS_QUEUEMACID_Q3_V1)) +#define BIT_GET_QUEUEMACID_Q3_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1) +#define BIT_SET_QUEUEMACID_Q3_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q3_V1(x) | BIT_QUEUEMACID_Q3_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q3_V1 23 +#define BIT_MASK_QUEUEAC_Q3_V1 0x3 +#define BIT_QUEUEAC_Q3_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1) +#define BITS_QUEUEAC_Q3_V1 (BIT_MASK_QUEUEAC_Q3_V1 << BIT_SHIFT_QUEUEAC_Q3_V1) +#define BIT_CLEAR_QUEUEAC_Q3_V1(x) ((x) & (~BITS_QUEUEAC_Q3_V1)) +#define BIT_GET_QUEUEAC_Q3_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1) +#define BIT_SET_QUEUEAC_Q3_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q3_V1(x) | BIT_QUEUEAC_Q3_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +/* 2 REG_Q3_INFO (Offset 0x040C) */ -#define BIT_EN_BCN_TRXRPT_V1 BIT(2) +#define BIT_TIDEMPTY_Q3_V1 BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_Q3_INFO (Offset 0x040C) */ -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#define BIT_SHIFT_TAIL_PKT_Q3_V1 15 +#define BIT_MASK_TAIL_PKT_Q3_V1 0xff +#define BIT_TAIL_PKT_Q3_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q3_V1) << BIT_SHIFT_TAIL_PKT_Q3_V1) +#define BITS_TAIL_PKT_Q3_V1 \ + (BIT_MASK_TAIL_PKT_Q3_V1 << BIT_SHIFT_TAIL_PKT_Q3_V1) +#define BIT_CLEAR_TAIL_PKT_Q3_V1(x) ((x) & (~BITS_TAIL_PKT_Q3_V1)) +#define BIT_GET_TAIL_PKT_Q3_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V1) & BIT_MASK_TAIL_PKT_Q3_V1) +#define BIT_SET_TAIL_PKT_Q3_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q3_V1(x) | BIT_TAIL_PKT_Q3_V1(v)) +#endif -/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_R_EN_FTMRPT BIT(1) +/* 2 REG_Q3_INFO (Offset 0x040C) */ + +#define BIT_SHIFT_TAIL_PKT_Q3_V2 11 +#define BIT_MASK_TAIL_PKT_Q3_V2 0x7ff +#define BIT_TAIL_PKT_Q3_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q3_V2) << BIT_SHIFT_TAIL_PKT_Q3_V2) +#define BITS_TAIL_PKT_Q3_V2 \ + (BIT_MASK_TAIL_PKT_Q3_V2 << BIT_SHIFT_TAIL_PKT_Q3_V2) +#define BIT_CLEAR_TAIL_PKT_Q3_V2(x) ((x) & (~BITS_TAIL_PKT_Q3_V2)) +#define BIT_GET_TAIL_PKT_Q3_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2) & BIT_MASK_TAIL_PKT_Q3_V2) +#define BIT_SET_TAIL_PKT_Q3_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q3_V2(x) | BIT_TAIL_PKT_Q3_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_Q3_INFO (Offset 0x040C) */ +#define BIT_SHIFT_PKT_NUM_Q3_V1 8 +#define BIT_MASK_PKT_NUM_Q3_V1 0x7f +#define BIT_PKT_NUM_Q3_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q3_V1) << BIT_SHIFT_PKT_NUM_Q3_V1) +#define BITS_PKT_NUM_Q3_V1 (BIT_MASK_PKT_NUM_Q3_V1 << BIT_SHIFT_PKT_NUM_Q3_V1) +#define BIT_CLEAR_PKT_NUM_Q3_V1(x) ((x) & (~BITS_PKT_NUM_Q3_V1)) +#define BIT_GET_PKT_NUM_Q3_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q3_V1) & BIT_MASK_PKT_NUM_Q3_V1) +#define BIT_SET_PKT_NUM_Q3_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q3_V1(x) | BIT_PKT_NUM_Q3_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q3 0 +#define BIT_MASK_HEAD_PKT_Q3 0xff +#define BIT_HEAD_PKT_Q3(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q3) << BIT_SHIFT_HEAD_PKT_Q3) +#define BITS_HEAD_PKT_Q3 (BIT_MASK_HEAD_PKT_Q3 << BIT_SHIFT_HEAD_PKT_Q3) +#define BIT_CLEAR_HEAD_PKT_Q3(x) ((x) & (~BITS_HEAD_PKT_Q3)) +#define BIT_GET_HEAD_PKT_Q3(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q3) & BIT_MASK_HEAD_PKT_Q3) +#define BIT_SET_HEAD_PKT_Q3(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q3(x) | BIT_HEAD_PKT_Q3(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +/* 2 REG_Q3_INFO (Offset 0x040C) */ -#define BIT_EN_FTMACKRPT BIT(1) +#define BIT_SHIFT_HEAD_PKT_Q3_V1 0 +#define BIT_MASK_HEAD_PKT_Q3_V1 0x7ff +#define BIT_HEAD_PKT_Q3_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q3_V1) << BIT_SHIFT_HEAD_PKT_Q3_V1) +#define BITS_HEAD_PKT_Q3_V1 \ + (BIT_MASK_HEAD_PKT_Q3_V1 << BIT_SHIFT_HEAD_PKT_Q3_V1) +#define BIT_CLEAR_HEAD_PKT_Q3_V1(x) ((x) & (~BITS_HEAD_PKT_Q3_V1)) +#define BIT_GET_HEAD_PKT_Q3_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1) & BIT_MASK_HEAD_PKT_Q3_V1) +#define BIT_SET_HEAD_PKT_Q3_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q3_V1(x) | BIT_HEAD_PKT_Q3_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_QUEUELIST_INFO3 (Offset 0x040C) */ +#define BIT_SHIFT_QINFO3 0 +#define BIT_MASK_QINFO3 0xffffffffL +#define BIT_QINFO3(x) (((x) & BIT_MASK_QINFO3) << BIT_SHIFT_QINFO3) +#define BITS_QINFO3 (BIT_MASK_QINFO3 << BIT_SHIFT_QINFO3) +#define BIT_CLEAR_QINFO3(x) ((x) & (~BITS_QINFO3)) +#define BIT_GET_QINFO3(x) (((x) >> BIT_SHIFT_QINFO3) & BIT_MASK_QINFO3) +#define BIT_SET_QINFO3(x, v) (BIT_CLEAR_QINFO3(x) | BIT_QINFO3(v)) -/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ -#define BIT_R_BMC_NAV_PROTECT BIT(0) +#define BIT_FWCMDQ_EMPTY BIT(31) +#define BIT_MGQ_CPU_EMPTY_V1 BIT(30) +#define BIT_BCNQ_EMPTY_EXTP0 BIT(29) +#define BIT_BCNQ_EMPTY_PORT4 BIT(28) +#define BIT_BCNQ_EMPTY_PORT3 BIT(27) +#define BIT_BCNQ_EMPTY_PORT2 BIT(26) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_SHIFT_QUEUEMACID_MGQ_V1 25 +#define BIT_MASK_QUEUEMACID_MGQ_V1 0x7f +#define BIT_QUEUEMACID_MGQ_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1) +#define BITS_QUEUEMACID_MGQ_V1 \ + (BIT_MASK_QUEUEMACID_MGQ_V1 << BIT_SHIFT_QUEUEMACID_MGQ_V1) +#define BIT_CLEAR_QUEUEMACID_MGQ_V1(x) ((x) & (~BITS_QUEUEMACID_MGQ_V1)) +#define BIT_GET_QUEUEMACID_MGQ_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1) +#define BIT_SET_QUEUEMACID_MGQ_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_MGQ_V1(x) | BIT_QUEUEMACID_MGQ_V1(v)) -/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#endif -#define BIT_EN_FTMRPT BIT(0) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ +#define BIT_BCNQ_EMPTY_PORT1 BIT(25) +#define BIT_BCNQ_EMPTY_PORT0 BIT(24) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ +/* 2 REG_MGQ_INFO (Offset 0x0410) */ -#define BIT_HWSEQ_CPUM_EN BIT(7) -#define BIT_HWSEQ_BCN_EN BIT(6) -#define BIT_HWSEQ_HI_EN BIT(5) -#define BIT_HWSEQ_MGT_EN BIT(4) -#define BIT_HWSEQ_BK_EN BIT(3) -#define BIT_HWSEQ_BE_EN BIT(2) +#define BIT_SHIFT_QUEUEAC_MGQ_V1 23 +#define BIT_MASK_QUEUEAC_MGQ_V1 0x3 +#define BIT_QUEUEAC_MGQ_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1) +#define BITS_QUEUEAC_MGQ_V1 \ + (BIT_MASK_QUEUEAC_MGQ_V1 << BIT_SHIFT_QUEUEAC_MGQ_V1) +#define BIT_CLEAR_QUEUEAC_MGQ_V1(x) ((x) & (~BITS_QUEUEAC_MGQ_V1)) +#define BIT_GET_QUEUEAC_MGQ_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1) +#define BIT_SET_QUEUEAC_MGQ_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_MGQ_V1(x) | BIT_QUEUEAC_MGQ_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ +#define BIT_HQQ_EMPTY_V1 BIT(23) -/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#endif -#define BIT__R_EN_RTY_BK_COD BIT(2) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_TIDEMPTY_MGQ_V1 BIT(22) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ -#define BIT_HWSEQ_VI_EN BIT(1) -#define BIT_HWSEQ_VO_EN BIT(0) +#define BIT_MQQ_EMPTY_V2 BIT(22) +#define BIT_S1_EMPTY BIT(21) +#define BIT_S0_EMPTY BIT(20) +#define BIT_AC19Q_EMPTY BIT(19) +#define BIT_AC18Q_EMPTY BIT(18) +#define BIT_AC17Q_EMPTY BIT(17) +#define BIT_AC16Q_EMPTY BIT(16) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_SHIFT_TAIL_PKT_MGQ_V1 15 +#define BIT_MASK_TAIL_PKT_MGQ_V1 0xff +#define BIT_TAIL_PKT_MGQ_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_MGQ_V1) << BIT_SHIFT_TAIL_PKT_MGQ_V1) +#define BITS_TAIL_PKT_MGQ_V1 \ + (BIT_MASK_TAIL_PKT_MGQ_V1 << BIT_SHIFT_TAIL_PKT_MGQ_V1) +#define BIT_CLEAR_TAIL_PKT_MGQ_V1(x) ((x) & (~BITS_TAIL_PKT_MGQ_V1)) +#define BIT_GET_TAIL_PKT_MGQ_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V1) & BIT_MASK_TAIL_PKT_MGQ_V1) +#define BIT_SET_TAIL_PKT_MGQ_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_MGQ_V1(x) | BIT_TAIL_PKT_MGQ_V1(v)) -/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT__R_DATA_FALLBACK_SEL 0 -#define BIT_MASK__R_DATA_FALLBACK_SEL 0x3 -#define BIT__R_DATA_FALLBACK_SEL(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL) << BIT_SHIFT__R_DATA_FALLBACK_SEL) -#define BIT_GET__R_DATA_FALLBACK_SEL(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL) & BIT_MASK__R_DATA_FALLBACK_SEL) +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ +#define BIT_AC15Q_EMPTY BIT(15) +#define BIT_AC14Q_EMPTY BIT(14) +#define BIT_AC13Q_EMPTY BIT(13) +#define BIT_AC12Q_EMPTY BIT(12) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_SHIFT_TAIL_PKT_MGQ_V2 11 +#define BIT_MASK_TAIL_PKT_MGQ_V2 0x7ff +#define BIT_TAIL_PKT_MGQ_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_MGQ_V2) << BIT_SHIFT_TAIL_PKT_MGQ_V2) +#define BITS_TAIL_PKT_MGQ_V2 \ + (BIT_MASK_TAIL_PKT_MGQ_V2 << BIT_SHIFT_TAIL_PKT_MGQ_V2) +#define BIT_CLEAR_TAIL_PKT_MGQ_V2(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2)) +#define BIT_GET_TAIL_PKT_MGQ_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2) & BIT_MASK_TAIL_PKT_MGQ_V2) +#define BIT_SET_TAIL_PKT_MGQ_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_MGQ_V2(x) | BIT_TAIL_PKT_MGQ_V2(v)) -/* 2 REG_BCNQ_BDNY (Offset 0x0424) */ +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCNQ_PGBNDY 0 -#define BIT_MASK_BCNQ_PGBNDY 0xff -#define BIT_BCNQ_PGBNDY(x) (((x) & BIT_MASK_BCNQ_PGBNDY) << BIT_SHIFT_BCNQ_PGBNDY) -#define BIT_GET_BCNQ_PGBNDY(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY) & BIT_MASK_BCNQ_PGBNDY) +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ +#define BIT_AC11Q_EMPTY BIT(11) +#define BIT_AC10Q_EMPTY BIT(10) +#define BIT_AC9Q_EMPTY BIT(9) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_SHIFT_PKT_NUM_MGQ_V1 8 +#define BIT_MASK_PKT_NUM_MGQ_V1 0x7f +#define BIT_PKT_NUM_MGQ_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_MGQ_V1) << BIT_SHIFT_PKT_NUM_MGQ_V1) +#define BITS_PKT_NUM_MGQ_V1 \ + (BIT_MASK_PKT_NUM_MGQ_V1 << BIT_SHIFT_PKT_NUM_MGQ_V1) +#define BIT_CLEAR_PKT_NUM_MGQ_V1(x) ((x) & (~BITS_PKT_NUM_MGQ_V1)) +#define BIT_GET_PKT_NUM_MGQ_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_MGQ_V1) & BIT_MASK_PKT_NUM_MGQ_V1) +#define BIT_SET_PKT_NUM_MGQ_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_MGQ_V1(x) | BIT_PKT_NUM_MGQ_V1(v)) -/* 2 REG_BCNQ_BDNY_V1 (Offset 0x0424) */ +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCNQ_PGBNDY_V1 0 -#define BIT_MASK_BCNQ_PGBNDY_V1 0xfff -#define BIT_BCNQ_PGBNDY_V1(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1) << BIT_SHIFT_BCNQ_PGBNDY_V1) -#define BIT_GET_BCNQ_PGBNDY_V1(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1) & BIT_MASK_BCNQ_PGBNDY_V1) +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ +#define BIT_AC8Q_EMPTY BIT(8) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ + +#define BIT_SHIFT_HEAD_PKT_MGQ 0 +#define BIT_MASK_HEAD_PKT_MGQ 0xff +#define BIT_HEAD_PKT_MGQ(x) \ + (((x) & BIT_MASK_HEAD_PKT_MGQ) << BIT_SHIFT_HEAD_PKT_MGQ) +#define BITS_HEAD_PKT_MGQ (BIT_MASK_HEAD_PKT_MGQ << BIT_SHIFT_HEAD_PKT_MGQ) +#define BIT_CLEAR_HEAD_PKT_MGQ(x) ((x) & (~BITS_HEAD_PKT_MGQ)) +#define BIT_GET_HEAD_PKT_MGQ(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_MGQ) & BIT_MASK_HEAD_PKT_MGQ) +#define BIT_SET_HEAD_PKT_MGQ(x, v) \ + (BIT_CLEAR_HEAD_PKT_MGQ(x) | BIT_HEAD_PKT_MGQ(v)) -/* 2 REG_MGQ_BDNY (Offset 0x0425) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MGQ_PGBNDY 0 -#define BIT_MASK_MGQ_PGBNDY 0xff -#define BIT_MGQ_PGBNDY(x) (((x) & BIT_MASK_MGQ_PGBNDY) << BIT_SHIFT_MGQ_PGBNDY) -#define BIT_GET_MGQ_PGBNDY(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY) & BIT_MASK_MGQ_PGBNDY) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_SHIFT_HEAD_PKT_MGQ_V1 0 +#define BIT_MASK_HEAD_PKT_MGQ_V1 0x7ff +#define BIT_HEAD_PKT_MGQ_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_MGQ_V1) << BIT_SHIFT_HEAD_PKT_MGQ_V1) +#define BITS_HEAD_PKT_MGQ_V1 \ + (BIT_MASK_HEAD_PKT_MGQ_V1 << BIT_SHIFT_HEAD_PKT_MGQ_V1) +#define BIT_CLEAR_HEAD_PKT_MGQ_V1(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1)) +#define BIT_GET_HEAD_PKT_MGQ_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1) & BIT_MASK_HEAD_PKT_MGQ_V1) +#define BIT_SET_HEAD_PKT_MGQ_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_MGQ_V1(x) | BIT_HEAD_PKT_MGQ_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_QUEUEMACID_HIQ_V1 25 +#define BIT_MASK_QUEUEMACID_HIQ_V1 0x7f +#define BIT_QUEUEMACID_HIQ_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1) +#define BITS_QUEUEMACID_HIQ_V1 \ + (BIT_MASK_QUEUEMACID_HIQ_V1 << BIT_SHIFT_QUEUEMACID_HIQ_V1) +#define BIT_CLEAR_QUEUEMACID_HIQ_V1(x) ((x) & (~BITS_QUEUEMACID_HIQ_V1)) +#define BIT_GET_QUEUEMACID_HIQ_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1) +#define BIT_SET_QUEUEMACID_HIQ_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_HIQ_V1(x) | BIT_QUEUEMACID_HIQ_V1(v)) -/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +#endif -#define BIT_BT_INT_CPU BIT(7) -#define BIT_BT_INT_PTA BIT(6) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ +#define BIT_SHIFT_QINFO_CTRL 24 +#define BIT_MASK_QINFO_CTRL 0x3f +#define BIT_QINFO_CTRL(x) (((x) & BIT_MASK_QINFO_CTRL) << BIT_SHIFT_QINFO_CTRL) +#define BITS_QINFO_CTRL (BIT_MASK_QINFO_CTRL << BIT_SHIFT_QINFO_CTRL) +#define BIT_CLEAR_QINFO_CTRL(x) ((x) & (~BITS_QINFO_CTRL)) +#define BIT_GET_QINFO_CTRL(x) \ + (((x) >> BIT_SHIFT_QINFO_CTRL) & BIT_MASK_QINFO_CTRL) +#define BIT_SET_QINFO_CTRL(x, v) (BIT_CLEAR_QINFO_CTRL(x) | BIT_QINFO_CTRL(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +/* 2 REG_HIQ_INFO (Offset 0x0414) */ -#define BIT_SPERPT_ENTRY BIT(5) -#define BIT_RTYCNT_FB BIT(4) +#define BIT_SHIFT_QUEUEAC_HIQ_V1 23 +#define BIT_MASK_QUEUEAC_HIQ_V1 0x3 +#define BIT_QUEUEAC_HIQ_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1) +#define BITS_QUEUEAC_HIQ_V1 \ + (BIT_MASK_QUEUEAC_HIQ_V1 << BIT_SHIFT_QUEUEAC_HIQ_V1) +#define BIT_CLEAR_QUEUEAC_HIQ_V1(x) ((x) & (~BITS_QUEUEAC_HIQ_V1)) +#define BIT_GET_QUEUEAC_HIQ_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1) +#define BIT_SET_QUEUEAC_HIQ_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_HIQ_V1(x) | BIT_QUEUEAC_HIQ_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_TIDEMPTY_HIQ_V1 BIT(22) -/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +#endif -#define BIT_EN_CTRL_RTYBIT BIT(4) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ +#define BIT_SHIFT_QINFO_MODE_BAND 20 +#define BIT_MASK_QINFO_MODE_BAND 0x7 +#define BIT_QINFO_MODE_BAND(x) \ + (((x) & BIT_MASK_QINFO_MODE_BAND) << BIT_SHIFT_QINFO_MODE_BAND) +#define BITS_QINFO_MODE_BAND \ + (BIT_MASK_QINFO_MODE_BAND << BIT_SHIFT_QINFO_MODE_BAND) +#define BIT_CLEAR_QINFO_MODE_BAND(x) ((x) & (~BITS_QINFO_MODE_BAND)) +#define BIT_GET_QINFO_MODE_BAND(x) \ + (((x) >> BIT_SHIFT_QINFO_MODE_BAND) & BIT_MASK_QINFO_MODE_BAND) +#define BIT_SET_QINFO_MODE_BAND(x, v) \ + (BIT_CLEAR_QINFO_MODE_BAND(x) | BIT_QINFO_MODE_BAND(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_ACQ19_ENABLE BIT(19) +#define BIT_ACQ18_ENABLE BIT(18) +#define BIT_ACQ17_ENABLE BIT(17) +#define BIT_ACQ16_ENABLE BIT(16) +#endif -/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_HIQ_INFO (Offset 0x0414) */ -#define BIT_LIFETIME_BK_EN BIT(3) -#define BIT_LIFETIME_BE_EN BIT(2) -#define BIT_LIFETIME_VI_EN BIT(1) -#define BIT_LIFETIME_VO_EN BIT(0) +#define BIT_SHIFT_TAIL_PKT_HIQ_V1 15 +#define BIT_MASK_TAIL_PKT_HIQ_V1 0xff +#define BIT_TAIL_PKT_HIQ_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_HIQ_V1) << BIT_SHIFT_TAIL_PKT_HIQ_V1) +#define BITS_TAIL_PKT_HIQ_V1 \ + (BIT_MASK_TAIL_PKT_HIQ_V1 << BIT_SHIFT_TAIL_PKT_HIQ_V1) +#define BIT_CLEAR_TAIL_PKT_HIQ_V1(x) ((x) & (~BITS_TAIL_PKT_HIQ_V1)) +#define BIT_GET_TAIL_PKT_HIQ_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V1) & BIT_MASK_TAIL_PKT_HIQ_V1) +#define BIT_SET_TAIL_PKT_HIQ_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_HIQ_V1(x) | BIT_TAIL_PKT_HIQ_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ +#define BIT_ACQ15_ENABLE BIT(15) +#define BIT_ACQ14_ENABLE BIT(14) +#define BIT_ACQ13_ENABLE BIT(13) +#define BIT_ACQ12_ENABLE BIT(12) -/* 2 REG_FW_FREE_TAIL (Offset 0x0427) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_FW_FREE_TAIL 0 -#define BIT_MASK_FW_FREE_TAIL 0xff -#define BIT_FW_FREE_TAIL(x) (((x) & BIT_MASK_FW_FREE_TAIL) << BIT_SHIFT_FW_FREE_TAIL) -#define BIT_GET_FW_FREE_TAIL(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL) & BIT_MASK_FW_FREE_TAIL) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_TAIL_PKT_HIQ_V2 11 +#define BIT_MASK_TAIL_PKT_HIQ_V2 0x7ff +#define BIT_TAIL_PKT_HIQ_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_HIQ_V2) << BIT_SHIFT_TAIL_PKT_HIQ_V2) +#define BITS_TAIL_PKT_HIQ_V2 \ + (BIT_MASK_TAIL_PKT_HIQ_V2 << BIT_SHIFT_TAIL_PKT_HIQ_V2) +#define BIT_CLEAR_TAIL_PKT_HIQ_V2(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2)) +#define BIT_GET_TAIL_PKT_HIQ_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2) & BIT_MASK_TAIL_PKT_HIQ_V2) +#define BIT_SET_TAIL_PKT_HIQ_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_HIQ_V2(x) | BIT_TAIL_PKT_HIQ_V2(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ +#define BIT_ACQ11_ENABLE BIT(11) +#define BIT_ACQ10_ENABLE BIT(10) +#define BIT_ACQ9_ENABLE BIT(9) -/* 2 REG_SPEC_SIFS (Offset 0x0428) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL 8 -#define BIT_MASK_SPEC_SIFS_OFDM_PTCL 0xff -#define BIT_SPEC_SIFS_OFDM_PTCL(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) -#define BIT_GET_SPEC_SIFS_OFDM_PTCL(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_PKT_NUM_HIQ_V1 8 +#define BIT_MASK_PKT_NUM_HIQ_V1 0x7f +#define BIT_PKT_NUM_HIQ_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_HIQ_V1) << BIT_SHIFT_PKT_NUM_HIQ_V1) +#define BITS_PKT_NUM_HIQ_V1 \ + (BIT_MASK_PKT_NUM_HIQ_V1 << BIT_SHIFT_PKT_NUM_HIQ_V1) +#define BIT_CLEAR_PKT_NUM_HIQ_V1(x) ((x) & (~BITS_PKT_NUM_HIQ_V1)) +#define BIT_GET_PKT_NUM_HIQ_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_HIQ_V1) & BIT_MASK_PKT_NUM_HIQ_V1) +#define BIT_SET_PKT_NUM_HIQ_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_HIQ_V1(x) | BIT_PKT_NUM_HIQ_V1(v)) -#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL 0 -#define BIT_MASK_SPEC_SIFS_CCK_PTCL 0xff -#define BIT_SPEC_SIFS_CCK_PTCL(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL) -#define BIT_GET_SPEC_SIFS_CCK_PTCL(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_RETRY_LIMIT (Offset 0x042A) */ +/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ +#define BIT_ACQ8_ENABLE BIT(8) +#define BIT_ACQ7_ENABLE BIT(7) +#define BIT_ACQ6_ENABLE BIT(6) +#define BIT_ACQ5_ENABLE BIT(5) +#define BIT_ACQ4_ENABLE BIT(4) +#define BIT_ACQ3_ENABLE BIT(3) +#define BIT_ACQ2_ENABLE BIT(2) +#define BIT_ACQ1_ENABLE BIT(1) -#define BIT_SHIFT_SRL 8 -#define BIT_MASK_SRL 0x3f -#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL) -#define BIT_GET_SRL(x) (((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LRL 0 -#define BIT_MASK_LRL 0x3f -#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL) -#define BIT_GET_LRL(x) (((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_HEAD_PKT_HIQ 0 +#define BIT_MASK_HEAD_PKT_HIQ 0xff +#define BIT_HEAD_PKT_HIQ(x) \ + (((x) & BIT_MASK_HEAD_PKT_HIQ) << BIT_SHIFT_HEAD_PKT_HIQ) +#define BITS_HEAD_PKT_HIQ (BIT_MASK_HEAD_PKT_HIQ << BIT_SHIFT_HEAD_PKT_HIQ) +#define BIT_CLEAR_HEAD_PKT_HIQ(x) ((x) & (~BITS_HEAD_PKT_HIQ)) +#define BIT_GET_HEAD_PKT_HIQ(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_HIQ) & BIT_MASK_HEAD_PKT_HIQ) +#define BIT_SET_HEAD_PKT_HIQ(x, v) \ + (BIT_CLEAR_HEAD_PKT_HIQ(x) | BIT_HEAD_PKT_HIQ(v)) -/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#endif -#define BIT_R_ENABLE_NDPA BIT(31) -#define BIT_USE_NDPA_PARAMETER BIT(30) -#define BIT_R_PROP_TXBF BIT(29) -#define BIT_R_EN_NDPA_INT BIT(28) -#define BIT_R_TXBF1_80M BIT(27) -#define BIT_R_TXBF1_40M BIT(26) -#define BIT_R_TXBF1_20M BIT(25) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_TXBF1_AID 16 -#define BIT_MASK_R_TXBF1_AID 0x1ff -#define BIT_R_TXBF1_AID(x) (((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID) -#define BIT_GET_R_TXBF1_AID(x) (((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_HEAD_PKT_HIQ_V1 0 +#define BIT_MASK_HEAD_PKT_HIQ_V1 0x7ff +#define BIT_HEAD_PKT_HIQ_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_HIQ_V1) << BIT_SHIFT_HEAD_PKT_HIQ_V1) +#define BITS_HEAD_PKT_HIQ_V1 \ + (BIT_MASK_HEAD_PKT_HIQ_V1 << BIT_SHIFT_HEAD_PKT_HIQ_V1) +#define BIT_CLEAR_HEAD_PKT_HIQ_V1(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1)) +#define BIT_GET_HEAD_PKT_HIQ_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1) & BIT_MASK_HEAD_PKT_HIQ_V1) +#define BIT_SET_HEAD_PKT_HIQ_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_HIQ_V1(x) | BIT_HEAD_PKT_HIQ_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ +#define BIT_ACQ0_ENABLE BIT(0) -/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +/* 2 REG_BCNQ_BDNY_V2 (Offset 0x0418) */ -#define BIT_DIS_NDP_BFEN BIT(15) +#define BIT_SHIFT_BCNQ_PGBNDY_WSEL 28 +#define BIT_MASK_BCNQ_PGBNDY_WSEL 0x7 +#define BIT_BCNQ_PGBNDY_WSEL(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_WSEL) << BIT_SHIFT_BCNQ_PGBNDY_WSEL) +#define BITS_BCNQ_PGBNDY_WSEL \ + (BIT_MASK_BCNQ_PGBNDY_WSEL << BIT_SHIFT_BCNQ_PGBNDY_WSEL) +#define BIT_CLEAR_BCNQ_PGBNDY_WSEL(x) ((x) & (~BITS_BCNQ_PGBNDY_WSEL)) +#define BIT_GET_BCNQ_PGBNDY_WSEL(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WSEL) & BIT_MASK_BCNQ_PGBNDY_WSEL) +#define BIT_SET_BCNQ_PGBNDY_WSEL(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_WSEL(x) | BIT_BCNQ_PGBNDY_WSEL(v)) + +#define BIT_SHIFT_BCNQ_PGBNDY_RCONTENT 12 +#define BIT_MASK_BCNQ_PGBNDY_RCONTENT 0xfff +#define BIT_BCNQ_PGBNDY_RCONTENT(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_RCONTENT) \ + << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT) +#define BITS_BCNQ_PGBNDY_RCONTENT \ + (BIT_MASK_BCNQ_PGBNDY_RCONTENT << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT) +#define BIT_CLEAR_BCNQ_PGBNDY_RCONTENT(x) ((x) & (~BITS_BCNQ_PGBNDY_RCONTENT)) +#define BIT_GET_BCNQ_PGBNDY_RCONTENT(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RCONTENT) & \ + BIT_MASK_BCNQ_PGBNDY_RCONTENT) +#define BIT_SET_BCNQ_PGBNDY_RCONTENT(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_RCONTENT(x) | BIT_BCNQ_PGBNDY_RCONTENT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCNQ_INFO (Offset 0x0418) */ +#define BIT_SHIFT_PKT_NUM_BCNQ 8 +#define BIT_MASK_PKT_NUM_BCNQ 0xff +#define BIT_PKT_NUM_BCNQ(x) \ + (((x) & BIT_MASK_PKT_NUM_BCNQ) << BIT_SHIFT_PKT_NUM_BCNQ) +#define BITS_PKT_NUM_BCNQ (BIT_MASK_PKT_NUM_BCNQ << BIT_SHIFT_PKT_NUM_BCNQ) +#define BIT_CLEAR_PKT_NUM_BCNQ(x) ((x) & (~BITS_PKT_NUM_BCNQ)) +#define BIT_GET_PKT_NUM_BCNQ(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_BCNQ) & BIT_MASK_PKT_NUM_BCNQ) +#define BIT_SET_PKT_NUM_BCNQ(x, v) \ + (BIT_CLEAR_PKT_NUM_BCNQ(x) | BIT_PKT_NUM_BCNQ(v)) + +#define BIT_SHIFT_BCNQ_HEAD_PG 0 +#define BIT_MASK_BCNQ_HEAD_PG 0xff +#define BIT_BCNQ_HEAD_PG(x) \ + (((x) & BIT_MASK_BCNQ_HEAD_PG) << BIT_SHIFT_BCNQ_HEAD_PG) +#define BITS_BCNQ_HEAD_PG (BIT_MASK_BCNQ_HEAD_PG << BIT_SHIFT_BCNQ_HEAD_PG) +#define BIT_CLEAR_BCNQ_HEAD_PG(x) ((x) & (~BITS_BCNQ_HEAD_PG)) +#define BIT_GET_BCNQ_HEAD_PG(x) \ + (((x) >> BIT_SHIFT_BCNQ_HEAD_PG) & BIT_MASK_BCNQ_HEAD_PG) +#define BIT_SET_BCNQ_HEAD_PG(x, v) \ + (BIT_CLEAR_BCNQ_HEAD_PG(x) | BIT_BCNQ_HEAD_PG(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +/* 2 REG_BCNQ_INFO (Offset 0x0418) */ -#define BIT_R_TXBCN_NOBLOCK_NDP BIT(14) +#define BIT_SHIFT_BCNQ_HEAD_PG_V1 0 +#define BIT_MASK_BCNQ_HEAD_PG_V1 0xfff +#define BIT_BCNQ_HEAD_PG_V1(x) \ + (((x) & BIT_MASK_BCNQ_HEAD_PG_V1) << BIT_SHIFT_BCNQ_HEAD_PG_V1) +#define BITS_BCNQ_HEAD_PG_V1 \ + (BIT_MASK_BCNQ_HEAD_PG_V1 << BIT_SHIFT_BCNQ_HEAD_PG_V1) +#define BIT_CLEAR_BCNQ_HEAD_PG_V1(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1)) +#define BIT_GET_BCNQ_HEAD_PG_V1(x) \ + (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1) & BIT_MASK_BCNQ_HEAD_PG_V1) +#define BIT_SET_BCNQ_HEAD_PG_V1(x, v) \ + (BIT_CLEAR_BCNQ_HEAD_PG_V1(x) | BIT_BCNQ_HEAD_PG_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCNQ_BDNY_V2 (Offset 0x0418) */ +#define BIT_SHIFT_BCNQ_PGBNDY_WCONTENT 0 +#define BIT_MASK_BCNQ_PGBNDY_WCONTENT 0xfff +#define BIT_BCNQ_PGBNDY_WCONTENT(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_WCONTENT) \ + << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT) +#define BITS_BCNQ_PGBNDY_WCONTENT \ + (BIT_MASK_BCNQ_PGBNDY_WCONTENT << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT) +#define BIT_CLEAR_BCNQ_PGBNDY_WCONTENT(x) ((x) & (~BITS_BCNQ_PGBNDY_WCONTENT)) +#define BIT_GET_BCNQ_PGBNDY_WCONTENT(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WCONTENT) & \ + BIT_MASK_BCNQ_PGBNDY_WCONTENT) +#define BIT_SET_BCNQ_PGBNDY_WCONTENT(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_WCONTENT(x) | BIT_BCNQ_PGBNDY_WCONTENT(v)) -/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#endif -#define BIT_R_TXBF0_80M BIT(11) -#define BIT_R_TXBF0_40M BIT(10) -#define BIT_R_TXBF0_20M BIT(9) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_TXBF0_AID 0 -#define BIT_MASK_R_TXBF0_AID 0x1ff -#define BIT_R_TXBF0_AID(x) (((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID) -#define BIT_GET_R_TXBF0_AID(x) (((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID) +/* 2 REG_TXPKT_EMPTY (Offset 0x041A) */ +#define BIT_BCNQ_EMPTY BIT(11) +#define BIT_HQQ_EMPTY BIT(10) +#define BIT_MQQ_EMPTY BIT(9) +#define BIT_MGQ_CPU_EMPTY BIT(8) -/* 2 REG_DARFRC (Offset 0x0430) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DARF_RC8 (56 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC8 0x1f -#define BIT_DARF_RC8(x) (((x) & BIT_MASK_DARF_RC8) << BIT_SHIFT_DARF_RC8) -#define BIT_GET_DARF_RC8(x) (((x) >> BIT_SHIFT_DARF_RC8) & BIT_MASK_DARF_RC8) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_BCN1_POLL BIT(30) -#define BIT_SHIFT_DARF_RC7 (48 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC7 0x1f -#define BIT_DARF_RC7(x) (((x) & BIT_MASK_DARF_RC7) << BIT_SHIFT_DARF_RC7) -#define BIT_GET_DARF_RC7(x) (((x) >> BIT_SHIFT_DARF_RC7) & BIT_MASK_DARF_RC7) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_DARF_RC6 (40 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC6 0x1f -#define BIT_DARF_RC6(x) (((x) & BIT_MASK_DARF_RC6) << BIT_SHIFT_DARF_RC6) -#define BIT_GET_DARF_RC6(x) (((x) >> BIT_SHIFT_DARF_RC6) & BIT_MASK_DARF_RC6) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_CPUMGT_CLR_V1 BIT(30) -#define BIT_SHIFT_DARF_RC5 (32 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC5 0x1f -#define BIT_DARF_RC5(x) (((x) & BIT_MASK_DARF_RC5) << BIT_SHIFT_DARF_RC5) -#define BIT_GET_DARF_RC5(x) (((x) >> BIT_SHIFT_DARF_RC5) & BIT_MASK_DARF_RC5) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DARF_RC4 24 -#define BIT_MASK_DARF_RC4 0x1f -#define BIT_DARF_RC4(x) (((x) & BIT_MASK_DARF_RC4) << BIT_SHIFT_DARF_RC4) -#define BIT_GET_DARF_RC4(x) (((x) >> BIT_SHIFT_DARF_RC4) & BIT_MASK_DARF_RC4) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_CPUMGT_POLL BIT(29) -#define BIT_SHIFT_DARF_RC3 16 -#define BIT_MASK_DARF_RC3 0x1f -#define BIT_DARF_RC3(x) (((x) & BIT_MASK_DARF_RC3) << BIT_SHIFT_DARF_RC3) -#define BIT_GET_DARF_RC3(x) (((x) >> BIT_SHIFT_DARF_RC3) & BIT_MASK_DARF_RC3) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DARF_RC2 8 -#define BIT_MASK_DARF_RC2 0x1f -#define BIT_DARF_RC2(x) (((x) & BIT_MASK_DARF_RC2) << BIT_SHIFT_DARF_RC2) -#define BIT_GET_DARF_RC2(x) (((x) >> BIT_SHIFT_DARF_RC2) & BIT_MASK_DARF_RC2) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_BCN_POLL BIT(28) -#define BIT_SHIFT_DARF_RC1 0 -#define BIT_MASK_DARF_RC1 0x1f -#define BIT_DARF_RC1(x) (((x) & BIT_MASK_DARF_RC1) << BIT_SHIFT_DARF_RC1) -#define BIT_GET_DARF_RC1(x) (((x) >> BIT_SHIFT_DARF_RC1) & BIT_MASK_DARF_RC1) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_RARFRC (Offset 0x0438) */ +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_CPUMGT_CLR BIT(27) -#define BIT_SHIFT_RARF_RC8 (56 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC8 0x1f -#define BIT_RARF_RC8(x) (((x) & BIT_MASK_RARF_RC8) << BIT_SHIFT_RARF_RC8) -#define BIT_GET_RARF_RC8(x) (((x) >> BIT_SHIFT_RARF_RC8) & BIT_MASK_RARF_RC8) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RARF_RC7 (48 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC7 0x1f -#define BIT_RARF_RC7(x) (((x) & BIT_MASK_RARF_RC7) << BIT_SHIFT_RARF_RC7) -#define BIT_GET_RARF_RC7(x) (((x) >> BIT_SHIFT_RARF_RC7) & BIT_MASK_RARF_RC7) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_BCN_EXT_POLL BIT(21) +#define BIT_BCN4_POLL BIT(20) +#define BIT_BCN3_POLL BIT(19) +#define BIT_BCN2_POLL BIT(18) +#define BIT_BCN1_POLL_V1 BIT(17) +#define BIT_BCN_POLL_V1 BIT(16) -#define BIT_SHIFT_RARF_RC6 (40 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC6 0x1f -#define BIT_RARF_RC6(x) (((x) & BIT_MASK_RARF_RC6) << BIT_SHIFT_RARF_RC6) -#define BIT_GET_RARF_RC6(x) (((x) >> BIT_SHIFT_RARF_RC6) & BIT_MASK_RARF_RC6) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RARF_RC5 (32 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC5 0x1f -#define BIT_RARF_RC5(x) (((x) & BIT_MASK_RARF_RC5) << BIT_SHIFT_RARF_RC5) -#define BIT_GET_RARF_RC5(x) (((x) >> BIT_SHIFT_RARF_RC5) & BIT_MASK_RARF_RC5) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_CPUMGQ_FW_NUM_V1 BIT(12) -#define BIT_SHIFT_RARF_RC4 24 -#define BIT_MASK_RARF_RC4 0x1f -#define BIT_RARF_RC4(x) (((x) & BIT_MASK_RARF_RC4) << BIT_SHIFT_RARF_RC4) -#define BIT_GET_RARF_RC4(x) (((x) >> BIT_SHIFT_RARF_RC4) & BIT_MASK_RARF_RC4) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RARF_RC3 16 -#define BIT_MASK_RARF_RC3 0x1f -#define BIT_RARF_RC3(x) (((x) & BIT_MASK_RARF_RC3) << BIT_SHIFT_RARF_RC3) -#define BIT_GET_RARF_RC3(x) (((x) >> BIT_SHIFT_RARF_RC3) & BIT_MASK_RARF_RC3) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_CPUMGQ_FW_NUM BIT(8) -#define BIT_SHIFT_RARF_RC2 8 -#define BIT_MASK_RARF_RC2 0x1f -#define BIT_RARF_RC2(x) (((x) & BIT_MASK_RARF_RC2) << BIT_SHIFT_RARF_RC2) -#define BIT_GET_RARF_RC2(x) (((x) >> BIT_SHIFT_RARF_RC2) & BIT_MASK_RARF_RC2) +#define BIT_SHIFT_CPUMGQ_HEAD_PG 0 +#define BIT_MASK_CPUMGQ_HEAD_PG 0xff +#define BIT_CPUMGQ_HEAD_PG(x) \ + (((x) & BIT_MASK_CPUMGQ_HEAD_PG) << BIT_SHIFT_CPUMGQ_HEAD_PG) +#define BITS_CPUMGQ_HEAD_PG \ + (BIT_MASK_CPUMGQ_HEAD_PG << BIT_SHIFT_CPUMGQ_HEAD_PG) +#define BIT_CLEAR_CPUMGQ_HEAD_PG(x) ((x) & (~BITS_CPUMGQ_HEAD_PG)) +#define BIT_GET_CPUMGQ_HEAD_PG(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_HEAD_PG) & BIT_MASK_CPUMGQ_HEAD_PG) +#define BIT_SET_CPUMGQ_HEAD_PG(x, v) \ + (BIT_CLEAR_CPUMGQ_HEAD_PG(x) | BIT_CPUMGQ_HEAD_PG(v)) +#endif -#define BIT_SHIFT_RARF_RC1 0 -#define BIT_MASK_RARF_RC1 0x1f -#define BIT_RARF_RC1(x) (((x) & BIT_MASK_RARF_RC1) << BIT_SHIFT_RARF_RC1) -#define BIT_GET_RARF_RC1(x) (((x) >> BIT_SHIFT_RARF_RC1) & BIT_MASK_RARF_RC1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ -#endif - +#define BIT_SHIFT_FW_FREE_TAIL_V1 0 +#define BIT_MASK_FW_FREE_TAIL_V1 0xfff +#define BIT_FW_FREE_TAIL_V1(x) \ + (((x) & BIT_MASK_FW_FREE_TAIL_V1) << BIT_SHIFT_FW_FREE_TAIL_V1) +#define BITS_FW_FREE_TAIL_V1 \ + (BIT_MASK_FW_FREE_TAIL_V1 << BIT_SHIFT_FW_FREE_TAIL_V1) +#define BIT_CLEAR_FW_FREE_TAIL_V1(x) ((x) & (~BITS_FW_FREE_TAIL_V1)) +#define BIT_GET_FW_FREE_TAIL_V1(x) \ + (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1) & BIT_MASK_FW_FREE_TAIL_V1) +#define BIT_SET_FW_FREE_TAIL_V1(x, v) \ + (BIT_CLEAR_FW_FREE_TAIL_V1(x) | BIT_FW_FREE_TAIL_V1(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_RRSR (Offset 0x0440) */ +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ -#define BIT_EN_VHTBW_FALL BIT(31) -#define BIT_EN_HTBW_FALL BIT(30) +#define BIT_SHIFT_FREE_TAIL_PAGE 0 +#define BIT_MASK_FREE_TAIL_PAGE 0xfff +#define BIT_FREE_TAIL_PAGE(x) \ + (((x) & BIT_MASK_FREE_TAIL_PAGE) << BIT_SHIFT_FREE_TAIL_PAGE) +#define BITS_FREE_TAIL_PAGE \ + (BIT_MASK_FREE_TAIL_PAGE << BIT_SHIFT_FREE_TAIL_PAGE) +#define BIT_CLEAR_FREE_TAIL_PAGE(x) ((x) & (~BITS_FREE_TAIL_PAGE)) +#define BIT_GET_FREE_TAIL_PAGE(x) \ + (((x) >> BIT_SHIFT_FREE_TAIL_PAGE) & BIT_MASK_FREE_TAIL_PAGE) +#define BIT_SET_FREE_TAIL_PAGE(x, v) \ + (BIT_CLEAR_FREE_TAIL_PAGE(x) | BIT_FREE_TAIL_PAGE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_RTS_LIMIT_IN_OFDM BIT(23) -/* 2 REG_RRSR (Offset 0x0440) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RRSR_RSC 21 -#define BIT_MASK_RRSR_RSC 0x3 -#define BIT_RRSR_RSC(x) (((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC) -#define BIT_GET_RRSR_RSC(x) (((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ -#define BIT_RRSR_BW BIT(20) +#define BIT_EN_BCNQ_DL BIT(22) -#define BIT_SHIFT_RRSC_BITMAP 0 -#define BIT_MASK_RRSC_BITMAP 0xfffff -#define BIT_RRSC_BITMAP(x) (((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP) -#define BIT_GET_RRSC_BITMAP(x) (((x) >> BIT_SHIFT_RRSC_BITMAP) & BIT_MASK_RRSC_BITMAP) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_ARFR0 (Offset 0x0444) */ +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_RD_RESP_NAV_BK BIT(21) +#define BIT_EN_WR_FREE_TAIL BIT(20) -#define BIT_SHIFT_ARFR0_V1 0 -#define BIT_MASK_ARFR0_V1 0xffffffffffffffffL -#define BIT_ARFR0_V1(x) (((x) & BIT_MASK_ARFR0_V1) << BIT_SHIFT_ARFR0_V1) -#define BIT_GET_ARFR0_V1(x) (((x) >> BIT_SHIFT_ARFR0_V1) & BIT_MASK_ARFR0_V1) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_ARFR1_V1 (Offset 0x044C) */ +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_TXRPT_DIS BIT(19) -#define BIT_SHIFT_ARFR1_V1 0 -#define BIT_MASK_ARFR1_V1 0xffffffffffffffffL -#define BIT_ARFR1_V1(x) (((x) & BIT_MASK_ARFR1_V1) << BIT_SHIFT_ARFR1_V1) -#define BIT_GET_ARFR1_V1(x) (((x) >> BIT_SHIFT_ARFR1_V1) & BIT_MASK_ARFR1_V1) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_CCK_CHECK (Offset 0x0454) */ +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ -#define BIT_CHECK_CCK_EN BIT(7) -#define BIT_EN_BCN_PKT_REL BIT(6) -#define BIT_BCN_PORT_SEL BIT(5) -#define BIT_MOREDATA_BYPASS BIT(4) -#define BIT_EN_CLR_CMD_REL_BCN_PKT BIT(3) +#define BIT_NOTXRPT_USERATE_EN BIT(19) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_DIS_TXFAIL_RPT BIT(18) -/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#endif -#define BIT_R_EN_SET_MOREDATA BIT(2) -#define BIT__R_DIS_CLEAR_MACID_RELEASE BIT(1) -#define BIT__R_MACID_RELEASE_EN BIT(0) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_FTM_TIMEOUT_BYPASS BIT(16) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_AMPDU_BURST_CTRL (Offset 0x0455) */ +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ -#define BIT_AMPDU_BURST_GLOBAL_EN BIT(0) +#define BIT_EN_BCNQ_DL5 BIT(13) +#define BIT_EN_BCNQ_DL4 BIT(12) +#define BIT_EN_BCNQ_DL3 BIT(11) +#define BIT_EN_BCNQ_DL2 BIT(10) +#define BIT_EN_BCNQ_DL1 BIT(9) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_SHIFT_EN_QUEUE_RPT 8 +#define BIT_MASK_EN_QUEUE_RPT 0xff +#define BIT_EN_QUEUE_RPT(x) \ + (((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT) +#define BITS_EN_QUEUE_RPT (BIT_MASK_EN_QUEUE_RPT << BIT_SHIFT_EN_QUEUE_RPT) +#define BIT_CLEAR_EN_QUEUE_RPT(x) ((x) & (~BITS_EN_QUEUE_RPT)) +#define BIT_GET_EN_QUEUE_RPT(x) \ + (((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT) +#define BIT_SET_EN_QUEUE_RPT(x, v) \ + (BIT_CLEAR_EN_QUEUE_RPT(x) | BIT_EN_QUEUE_RPT(v)) -/* 2 REG_AMPDU_MAX_TIME (Offset 0x0456) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_AMPDU_MAX_TIME 0 -#define BIT_MASK_AMPDU_MAX_TIME 0xff -#define BIT_AMPDU_MAX_TIME(x) (((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME) -#define BIT_GET_AMPDU_MAX_TIME(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_BCNQ_DL0 BIT(8) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_RTY_BK BIT(7) +#define BIT_EN_USE_INI_RAT BIT(6) +#define BIT_EN_RTS_NAV_BK BIT(5) +#define BIT_DIS_SSN_CHECK BIT(4) +#define BIT_MACID_MATCH_RTS BIT(3) -/* 2 REG_BCNQ1_BDNY_V1 (Offset 0x0456) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BCNQ1_PGBNDY_V1 0 -#define BIT_MASK_BCNQ1_PGBNDY_V1 0xfff -#define BIT_BCNQ1_PGBNDY_V1(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1) << BIT_SHIFT_BCNQ1_PGBNDY_V1) -#define BIT_GET_BCNQ1_PGBNDY_V1(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1) & BIT_MASK_BCNQ1_PGBNDY_V1) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_BCN_TRXRPT_V1 BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_R_EN_FTMRPT BIT(1) -/* 2 REG_BCNQ1_BDNY (Offset 0x0457) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCNQ1_PGBNDY 0 -#define BIT_MASK_BCNQ1_PGBNDY 0xff -#define BIT_BCNQ1_PGBNDY(x) (((x) & BIT_MASK_BCNQ1_PGBNDY) << BIT_SHIFT_BCNQ1_PGBNDY) -#define BIT_GET_BCNQ1_PGBNDY(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY) & BIT_MASK_BCNQ1_PGBNDY) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_FTMRPT_V1 BIT(1) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_AMPDU_MAX_LENGTH (Offset 0x0458) */ +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_R_EN_FTMRPT_V1 BIT(1) -#define BIT_SHIFT_AMPDU_MAX_LENGTH 0 -#define BIT_MASK_AMPDU_MAX_LENGTH 0xffffffffL -#define BIT_AMPDU_MAX_LENGTH(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH) -#define BIT_GET_AMPDU_MAX_LENGTH(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH) +#endif +#if (HALMAC_8822B_SUPPORT) -/* 2 REG_ACQ_STOP (Offset 0x045C) */ +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ -#define BIT_AC7Q_STOP BIT(7) -#define BIT_AC6Q_STOP BIT(6) -#define BIT_AC5Q_STOP BIT(5) -#define BIT_AC4Q_STOP BIT(4) -#define BIT_AC3Q_STOP BIT(3) -#define BIT_AC2Q_STOP BIT(2) -#define BIT_AC1Q_STOP BIT(1) -#define BIT_AC0Q_STOP BIT(0) +#define BIT_EN_FTMACKRPT BIT(1) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_R_BMC_NAV_PROTECT BIT(0) -/* 2 REG_WMAC_LBK_BUF_HD (Offset 0x045D) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_WMAC_LBK_BUF_HEAD 0 -#define BIT_MASK_WMAC_LBK_BUF_HEAD 0xff -#define BIT_WMAC_LBK_BUF_HEAD(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD) << BIT_SHIFT_WMAC_LBK_BUF_HEAD) -#define BIT_GET_WMAC_LBK_BUF_HEAD(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD) & BIT_MASK_WMAC_LBK_BUF_HEAD) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_BMC_NAV_PROTECT BIT(0) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_FTMRPT BIT(0) -/* 2 REG_NDPA_RATE (Offset 0x045D) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_NDPA_RATE_V1 0 -#define BIT_MASK_R_NDPA_RATE_V1 0xff -#define BIT_R_NDPA_RATE_V1(x) (((x) & BIT_MASK_R_NDPA_RATE_V1) << BIT_SHIFT_R_NDPA_RATE_V1) -#define BIT_GET_R_NDPA_RATE_V1(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1) & BIT_MASK_R_NDPA_RATE_V1) +/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ +#define BIT_HWSEQ_CPUM_EN BIT(7) +#define BIT_HWSEQ_BCN_EN BIT(6) +#define BIT_HWSEQ_HI_EN BIT(5) +#define BIT_HWSEQ_MGT_EN BIT(4) +#define BIT_HWSEQ_BK_EN BIT(3) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#define BIT_R_BROADCAST_RETRY_EN BIT(3) -/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +#endif -#define BIT_R_EN_GNT_BT_AWAKE BIT(3) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#define BIT_BROADCAST_RTY_EN BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ -#define BIT_EN_EOF_V1 BIT(2) +#define BIT_HWSEQ_BE_EN BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#define BIT__R_EN_RTY_BK_COD BIT(2) -/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +#endif -#define BIT_DIS_OQT_BLOCK BIT(1) -#define BIT_SEARCH_QUEUE_EN BIT(0) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#define BIT_EN_RTY_BK_COD BIT(2) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ -#define BIT_R_DIS_MACID_RELEASE_RTY BIT(5) +#define BIT_HWSEQ_VI_EN BIT(1) +#define BIT_HWSEQ_VO_EN BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#define BIT_SHIFT__R_DATA_FALLBACK_SEL 0 +#define BIT_MASK__R_DATA_FALLBACK_SEL 0x3 +#define BIT__R_DATA_FALLBACK_SEL(x) \ + (((x) & BIT_MASK__R_DATA_FALLBACK_SEL) \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL) +#define BITS__R_DATA_FALLBACK_SEL \ + (BIT_MASK__R_DATA_FALLBACK_SEL << BIT_SHIFT__R_DATA_FALLBACK_SEL) +#define BIT_CLEAR__R_DATA_FALLBACK_SEL(x) ((x) & (~BITS__R_DATA_FALLBACK_SEL)) +#define BIT_GET__R_DATA_FALLBACK_SEL(x) \ + (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL) & \ + BIT_MASK__R_DATA_FALLBACK_SEL) +#define BIT_SET__R_DATA_FALLBACK_SEL(x, v) \ + (BIT_CLEAR__R_DATA_FALLBACK_SEL(x) | BIT__R_DATA_FALLBACK_SEL(v)) -/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BW_SIGTA 3 -#define BIT_MASK_BW_SIGTA 0x3 -#define BIT_BW_SIGTA(x) (((x) & BIT_MASK_BW_SIGTA) << BIT_SHIFT_BW_SIGTA) -#define BIT_GET_BW_SIGTA(x) (((x) >> BIT_SHIFT_BW_SIGTA) & BIT_MASK_BW_SIGTA) +/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#define BIT_SHIFT__DATA_FALLBACK_SEL 0 +#define BIT_MASK__DATA_FALLBACK_SEL 0x3 +#define BIT__DATA_FALLBACK_SEL(x) \ + (((x) & BIT_MASK__DATA_FALLBACK_SEL) << BIT_SHIFT__DATA_FALLBACK_SEL) +#define BITS__DATA_FALLBACK_SEL \ + (BIT_MASK__DATA_FALLBACK_SEL << BIT_SHIFT__DATA_FALLBACK_SEL) +#define BIT_CLEAR__DATA_FALLBACK_SEL(x) ((x) & (~BITS__DATA_FALLBACK_SEL)) +#define BIT_GET__DATA_FALLBACK_SEL(x) \ + (((x) >> BIT_SHIFT__DATA_FALLBACK_SEL) & BIT_MASK__DATA_FALLBACK_SEL) +#define BIT_SET__DATA_FALLBACK_SEL(x, v) \ + (BIT_CLEAR__DATA_FALLBACK_SEL(x) | BIT__DATA_FALLBACK_SEL(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCNQ_BDNY (Offset 0x0424) */ -/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ - +#define BIT_SHIFT_BCNQ_PGBNDY 0 +#define BIT_MASK_BCNQ_PGBNDY 0xff +#define BIT_BCNQ_PGBNDY(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY) << BIT_SHIFT_BCNQ_PGBNDY) +#define BITS_BCNQ_PGBNDY (BIT_MASK_BCNQ_PGBNDY << BIT_SHIFT_BCNQ_PGBNDY) +#define BIT_CLEAR_BCNQ_PGBNDY(x) ((x) & (~BITS_BCNQ_PGBNDY)) +#define BIT_GET_BCNQ_PGBNDY(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY) & BIT_MASK_BCNQ_PGBNDY) +#define BIT_SET_BCNQ_PGBNDY(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY(x) | BIT_BCNQ_PGBNDY(v)) -#define BIT_SHIFT_R_NDPA_RATE 2 -#define BIT_MASK_R_NDPA_RATE 0x3f -#define BIT_R_NDPA_RATE(x) (((x) & BIT_MASK_R_NDPA_RATE) << BIT_SHIFT_R_NDPA_RATE) -#define BIT_GET_R_NDPA_RATE(x) (((x) >> BIT_SHIFT_R_NDPA_RATE) & BIT_MASK_R_NDPA_RATE) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BCNQ_BDNY_V1 (Offset 0x0424) */ +#define BIT_SHIFT_BCNQ_PGBNDY_V1 0 +#define BIT_MASK_BCNQ_PGBNDY_V1 0xfff +#define BIT_BCNQ_PGBNDY_V1(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_V1) << BIT_SHIFT_BCNQ_PGBNDY_V1) +#define BITS_BCNQ_PGBNDY_V1 \ + (BIT_MASK_BCNQ_PGBNDY_V1 << BIT_SHIFT_BCNQ_PGBNDY_V1) +#define BIT_CLEAR_BCNQ_PGBNDY_V1(x) ((x) & (~BITS_BCNQ_PGBNDY_V1)) +#define BIT_GET_BCNQ_PGBNDY_V1(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1) & BIT_MASK_BCNQ_PGBNDY_V1) +#define BIT_SET_BCNQ_PGBNDY_V1(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_V1(x) | BIT_BCNQ_PGBNDY_V1(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +/* 2 REG_TXBDNY (Offset 0x0424) */ -#define BIT_EN_BAR_SIGTA BIT(2) +#define BIT_SHIFT_TXBNDY 0 +#define BIT_MASK_TXBNDY 0xfff +#define BIT_TXBNDY(x) (((x) & BIT_MASK_TXBNDY) << BIT_SHIFT_TXBNDY) +#define BITS_TXBNDY (BIT_MASK_TXBNDY << BIT_SHIFT_TXBNDY) +#define BIT_CLEAR_TXBNDY(x) ((x) & (~BITS_TXBNDY)) +#define BIT_GET_TXBNDY(x) (((x) >> BIT_SHIFT_TXBNDY) & BIT_MASK_TXBNDY) +#define BIT_SET_TXBNDY(x, v) (BIT_CLEAR_TXBNDY(x) | BIT_TXBNDY(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MGQ_BDNY (Offset 0x0425) */ +#define BIT_SHIFT_MGQ_PGBNDY 0 +#define BIT_MASK_MGQ_PGBNDY 0xff +#define BIT_MGQ_PGBNDY(x) (((x) & BIT_MASK_MGQ_PGBNDY) << BIT_SHIFT_MGQ_PGBNDY) +#define BITS_MGQ_PGBNDY (BIT_MASK_MGQ_PGBNDY << BIT_SHIFT_MGQ_PGBNDY) +#define BIT_CLEAR_MGQ_PGBNDY(x) ((x) & (~BITS_MGQ_PGBNDY)) +#define BIT_GET_MGQ_PGBNDY(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY) & BIT_MASK_MGQ_PGBNDY) +#define BIT_SET_MGQ_PGBNDY(x, v) (BIT_CLEAR_MGQ_PGBNDY(x) | BIT_MGQ_PGBNDY(v)) -/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_NDPA_BW 0 -#define BIT_MASK_R_NDPA_BW 0x3 -#define BIT_R_NDPA_BW(x) (((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW) -#define BIT_GET_R_NDPA_BW(x) (((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW) +/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +#define BIT_BT_INT_CPU BIT(7) +#define BIT_BT_INT_PTA BIT(6) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_LIFETIME_EN (Offset 0x0426) */ -/* 2 REG_FAST_EDCA_CTRL (Offset 0x0460) */ +#define BIT_SPERPT_ENTRY BIT(5) +#define BIT_RTYCNT_FB BIT(4) +#endif -#define BIT_SHIFT_FAST_EDCA_TO_V1 16 -#define BIT_MASK_FAST_EDCA_TO_V1 0xff -#define BIT_FAST_EDCA_TO_V1(x) (((x) & BIT_MASK_FAST_EDCA_TO_V1) << BIT_SHIFT_FAST_EDCA_TO_V1) -#define BIT_GET_FAST_EDCA_TO_V1(x) (((x) >> BIT_SHIFT_FAST_EDCA_TO_V1) & BIT_MASK_FAST_EDCA_TO_V1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_LIFETIME_EN (Offset 0x0426) */ -#define BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH 12 -#define BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH 0xf -#define BIT_AC3_AC7_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH) << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) -#define BIT_GET_AC3_AC7_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) & BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH) +#define BIT_EN_CTRL_RTYBIT BIT(4) +#endif -#define BIT_SHIFT_AC2_FAST_EDCA_PKT_TH 8 -#define BIT_MASK_AC2_FAST_EDCA_PKT_TH 0xf -#define BIT_AC2_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_AC2_FAST_EDCA_PKT_TH) << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) -#define BIT_GET_AC2_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) & BIT_MASK_AC2_FAST_EDCA_PKT_TH) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) +/* 2 REG_LIFETIME_EN (Offset 0x0426) */ -#define BIT_SHIFT_AC1_FAST_EDCA_PKT_TH 4 -#define BIT_MASK_AC1_FAST_EDCA_PKT_TH 0xf -#define BIT_AC1_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_AC1_FAST_EDCA_PKT_TH) << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) -#define BIT_GET_AC1_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) & BIT_MASK_AC1_FAST_EDCA_PKT_TH) +#define BIT_LIFETIME_BK_EN BIT(3) +#define BIT_LIFETIME_BE_EN BIT(2) +#define BIT_LIFETIME_VI_EN BIT(1) +#define BIT_LIFETIME_VO_EN BIT(0) +#endif -#define BIT_SHIFT_AC0_FAST_EDCA_PKT_TH 0 -#define BIT_MASK_AC0_FAST_EDCA_PKT_TH 0xf -#define BIT_AC0_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_AC0_FAST_EDCA_PKT_TH) << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) -#define BIT_GET_AC0_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) & BIT_MASK_AC0_FAST_EDCA_PKT_TH) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FW_FREE_TAIL (Offset 0x0427) */ -/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ +#define BIT_SHIFT_FW_FREE_TAIL 0 +#define BIT_MASK_FW_FREE_TAIL 0xff +#define BIT_FW_FREE_TAIL(x) \ + (((x) & BIT_MASK_FW_FREE_TAIL) << BIT_SHIFT_FW_FREE_TAIL) +#define BITS_FW_FREE_TAIL (BIT_MASK_FW_FREE_TAIL << BIT_SHIFT_FW_FREE_TAIL) +#define BIT_CLEAR_FW_FREE_TAIL(x) ((x) & (~BITS_FW_FREE_TAIL)) +#define BIT_GET_FW_FREE_TAIL(x) \ + (((x) >> BIT_SHIFT_FW_FREE_TAIL) & BIT_MASK_FW_FREE_TAIL) +#define BIT_SET_FW_FREE_TAIL(x, v) \ + (BIT_CLEAR_FW_FREE_TAIL(x) | BIT_FW_FREE_TAIL(v)) +#endif -#define BIT_SHIFT_RD_RESP_PKT_TH 0 -#define BIT_MASK_RD_RESP_PKT_TH 0x1f -#define BIT_RD_RESP_PKT_TH(x) (((x) & BIT_MASK_RD_RESP_PKT_TH) << BIT_SHIFT_RD_RESP_PKT_TH) -#define BIT_GET_RD_RESP_PKT_TH(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH) & BIT_MASK_RD_RESP_PKT_TH) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) +/* 2 REG_SPEC_SIFS (Offset 0x0428) */ -#endif +#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL 8 +#define BIT_MASK_SPEC_SIFS_OFDM_PTCL 0xff +#define BIT_SPEC_SIFS_OFDM_PTCL(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) +#define BITS_SPEC_SIFS_OFDM_PTCL \ + (BIT_MASK_SPEC_SIFS_OFDM_PTCL << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) | BIT_SPEC_SIFS_OFDM_PTCL(v)) + +#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL 0 +#define BIT_MASK_SPEC_SIFS_CCK_PTCL 0xff +#define BIT_SPEC_SIFS_CCK_PTCL(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL) +#define BITS_SPEC_SIFS_CCK_PTCL \ + (BIT_MASK_SPEC_SIFS_CCK_PTCL << BIT_SHIFT_SPEC_SIFS_CCK_PTCL) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) ((x) & (~BITS_SPEC_SIFS_CCK_PTCL)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL) +#define BIT_SET_SPEC_SIFS_CCK_PTCL(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) | BIT_SPEC_SIFS_CCK_PTCL(v)) +/* 2 REG_RETRY_LIMIT (Offset 0x042A) */ -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_SRL 8 +#define BIT_MASK_SRL 0x3f +#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL) +#define BITS_SRL (BIT_MASK_SRL << BIT_SHIFT_SRL) +#define BIT_CLEAR_SRL(x) ((x) & (~BITS_SRL)) +#define BIT_GET_SRL(x) (((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL) +#define BIT_SET_SRL(x, v) (BIT_CLEAR_SRL(x) | BIT_SRL(v)) +#define BIT_SHIFT_LRL 0 +#define BIT_MASK_LRL 0x3f +#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL) +#define BITS_LRL (BIT_MASK_LRL << BIT_SHIFT_LRL) +#define BIT_CLEAR_LRL(x) ((x) & (~BITS_LRL)) +#define BIT_GET_LRL(x) (((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL) +#define BIT_SET_LRL(x, v) (BIT_CLEAR_LRL(x) | BIT_LRL(v)) -/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RD_RESP_PKT_TH_V1 0 -#define BIT_MASK_RD_RESP_PKT_TH_V1 0x3f -#define BIT_RD_RESP_PKT_TH_V1(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1) << BIT_SHIFT_RD_RESP_PKT_TH_V1) -#define BIT_GET_RD_RESP_PKT_TH_V1(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1) & BIT_MASK_RD_RESP_PKT_TH_V1) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_ENABLE_NDPA BIT(31) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_ENABLE_NDPA BIT(31) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_QUEUEMACID_CMDQ_V1 25 -#define BIT_MASK_QUEUEMACID_CMDQ_V1 0x7f -#define BIT_QUEUEMACID_CMDQ_V1(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1) << BIT_SHIFT_QUEUEMACID_CMDQ_V1) -#define BIT_GET_QUEUEMACID_CMDQ_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1) & BIT_MASK_QUEUEMACID_CMDQ_V1) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_USE_NDPA_PARAMETER BIT(30) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_NDPA_PARA BIT(30) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKT_NUM_CMDQ_V2 24 -#define BIT_MASK_PKT_NUM_CMDQ_V2 0xff -#define BIT_PKT_NUM_CMDQ_V2(x) (((x) & BIT_MASK_PKT_NUM_CMDQ_V2) << BIT_SHIFT_PKT_NUM_CMDQ_V2) -#define BIT_GET_PKT_NUM_CMDQ_V2(x) (((x) >> BIT_SHIFT_PKT_NUM_CMDQ_V2) & BIT_MASK_PKT_NUM_CMDQ_V2) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_PROP_TXBF BIT(29) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_PROP_TXBF BIT(29) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKT_NUM 23 -#define BIT_MASK_PKT_NUM 0x1ff -#define BIT_PKT_NUM(x) (((x) & BIT_MASK_PKT_NUM) << BIT_SHIFT_PKT_NUM) -#define BIT_GET_PKT_NUM(x) (((x) >> BIT_SHIFT_PKT_NUM) & BIT_MASK_PKT_NUM) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_EN_NDPA_INT BIT(28) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_EN_NDPA_INT BIT(28) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_QUEUEAC_CMDQ_V1 23 -#define BIT_MASK_QUEUEAC_CMDQ_V1 0x3 -#define BIT_QUEUEAC_CMDQ_V1(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1) << BIT_SHIFT_QUEUEAC_CMDQ_V1) -#define BIT_GET_QUEUEAC_CMDQ_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1) & BIT_MASK_QUEUEAC_CMDQ_V1) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBF1_80M BIT(27) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ -#define BIT_TIDEMPTY_CMDQ_V1 BIT(22) +#define BIT_TXBF1_80M_160M BIT(27) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBF1_40M BIT(26) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_CMDQ 16 -#define BIT_MASK_TAIL_PKT_CMDQ 0xff -#define BIT_TAIL_PKT_CMDQ(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ) << BIT_SHIFT_TAIL_PKT_CMDQ) -#define BIT_GET_TAIL_PKT_CMDQ(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ) & BIT_MASK_TAIL_PKT_CMDQ) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBF1_40M BIT(26) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBF1_20M BIT(25) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_CMDQ_V2 11 -#define BIT_MASK_TAIL_PKT_CMDQ_V2 0x7ff -#define BIT_TAIL_PKT_CMDQ_V2(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2) << BIT_SHIFT_TAIL_PKT_CMDQ_V2) -#define BIT_GET_TAIL_PKT_CMDQ_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2) & BIT_MASK_TAIL_PKT_CMDQ_V2) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBF1_20M BIT(25) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_SHIFT_R_TXBF1_AID 16 +#define BIT_MASK_R_TXBF1_AID 0x1ff +#define BIT_R_TXBF1_AID(x) \ + (((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID) +#define BITS_R_TXBF1_AID (BIT_MASK_R_TXBF1_AID << BIT_SHIFT_R_TXBF1_AID) +#define BIT_CLEAR_R_TXBF1_AID(x) ((x) & (~BITS_R_TXBF1_AID)) +#define BIT_GET_R_TXBF1_AID(x) \ + (((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID) +#define BIT_SET_R_TXBF1_AID(x, v) \ + (BIT_CLEAR_R_TXBF1_AID(x) | BIT_R_TXBF1_AID(v)) -#define BIT_SHIFT_PKT_NUM_CMDQ 8 -#define BIT_MASK_PKT_NUM_CMDQ 0xff -#define BIT_PKT_NUM_CMDQ(x) (((x) & BIT_MASK_PKT_NUM_CMDQ) << BIT_SHIFT_PKT_NUM_CMDQ) -#define BIT_GET_PKT_NUM_CMDQ(x) (((x) >> BIT_SHIFT_PKT_NUM_CMDQ) & BIT_MASK_PKT_NUM_CMDQ) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_CMDQ 0 -#define BIT_MASK_HEAD_PKT_CMDQ 0xff -#define BIT_HEAD_PKT_CMDQ(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ) << BIT_SHIFT_HEAD_PKT_CMDQ) -#define BIT_GET_HEAD_PKT_CMDQ(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ) & BIT_MASK_HEAD_PKT_CMDQ) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_SHIFT_TXBF1_AID 16 +#define BIT_MASK_TXBF1_AID 0x1ff +#define BIT_TXBF1_AID(x) (((x) & BIT_MASK_TXBF1_AID) << BIT_SHIFT_TXBF1_AID) +#define BITS_TXBF1_AID (BIT_MASK_TXBF1_AID << BIT_SHIFT_TXBF1_AID) +#define BIT_CLEAR_TXBF1_AID(x) ((x) & (~BITS_TXBF1_AID)) +#define BIT_GET_TXBF1_AID(x) (((x) >> BIT_SHIFT_TXBF1_AID) & BIT_MASK_TXBF1_AID) +#define BIT_SET_TXBF1_AID(x, v) (BIT_CLEAR_TXBF1_AID(x) | BIT_TXBF1_AID(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_DIS_NDP_BFEN BIT(15) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_CMDQ_V1 0 -#define BIT_MASK_HEAD_PKT_CMDQ_V1 0x7ff -#define BIT_HEAD_PKT_CMDQ_V1(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1) << BIT_SHIFT_HEAD_PKT_CMDQ_V1) -#define BIT_GET_HEAD_PKT_CMDQ_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1) & BIT_MASK_HEAD_PKT_CMDQ_V1) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBCN_NOBLOCK_NDP BIT(14) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBCN_NOBLOCK_NDP BIT(14) -/* 2 REG_Q4_INFO (Offset 0x0468) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_QUEUEMACID_Q4_V1 25 -#define BIT_MASK_QUEUEMACID_Q4_V1 0x7f -#define BIT_QUEUEMACID_Q4_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1) -#define BIT_GET_QUEUEMACID_Q4_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBF0_80M BIT(11) -#define BIT_SHIFT_QUEUEAC_Q4_V1 23 -#define BIT_MASK_QUEUEAC_Q4_V1 0x3 -#define BIT_QUEUEAC_Q4_V1(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1) -#define BIT_GET_QUEUEAC_Q4_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1) +#endif +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBF0_80M_160M BIT(11) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_Q4_INFO (Offset 0x0468) */ +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ -#define BIT_TIDEMPTY_Q4_V1 BIT(22) +#define BIT_R_TXBF0_40M BIT(10) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBF0_40M BIT(10) -/* 2 REG_Q4_INFO (Offset 0x0468) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q4_V1 15 -#define BIT_MASK_TAIL_PKT_Q4_V1 0xff -#define BIT_TAIL_PKT_Q4_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V1) << BIT_SHIFT_TAIL_PKT_Q4_V1) -#define BIT_GET_TAIL_PKT_Q4_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V1) & BIT_MASK_TAIL_PKT_Q4_V1) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBF0_20M BIT(9) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBF0_20M BIT(9) -/* 2 REG_Q4_INFO (Offset 0x0468) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q4_V2 11 -#define BIT_MASK_TAIL_PKT_Q4_V2 0x7ff -#define BIT_TAIL_PKT_Q4_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2) << BIT_SHIFT_TAIL_PKT_Q4_V2) -#define BIT_GET_TAIL_PKT_Q4_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2) & BIT_MASK_TAIL_PKT_Q4_V2) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_SHIFT_R_TXBF0_AID 0 +#define BIT_MASK_R_TXBF0_AID 0x1ff +#define BIT_R_TXBF0_AID(x) \ + (((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID) +#define BITS_R_TXBF0_AID (BIT_MASK_R_TXBF0_AID << BIT_SHIFT_R_TXBF0_AID) +#define BIT_CLEAR_R_TXBF0_AID(x) ((x) & (~BITS_R_TXBF0_AID)) +#define BIT_GET_R_TXBF0_AID(x) \ + (((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID) +#define BIT_SET_R_TXBF0_AID(x, v) \ + (BIT_CLEAR_R_TXBF0_AID(x) | BIT_R_TXBF0_AID(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_SHIFT_TXBF0_AID 0 +#define BIT_MASK_TXBF0_AID 0x1ff +#define BIT_TXBF0_AID(x) (((x) & BIT_MASK_TXBF0_AID) << BIT_SHIFT_TXBF0_AID) +#define BITS_TXBF0_AID (BIT_MASK_TXBF0_AID << BIT_SHIFT_TXBF0_AID) +#define BIT_CLEAR_TXBF0_AID(x) ((x) & (~BITS_TXBF0_AID)) +#define BIT_GET_TXBF0_AID(x) (((x) >> BIT_SHIFT_TXBF0_AID) & BIT_MASK_TXBF0_AID) +#define BIT_SET_TXBF0_AID(x, v) (BIT_CLEAR_TXBF0_AID(x) | BIT_TXBF0_AID(v)) -/* 2 REG_Q4_INFO (Offset 0x0468) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKT_NUM_Q4_V1 8 -#define BIT_MASK_PKT_NUM_Q4_V1 0x7f -#define BIT_PKT_NUM_Q4_V1(x) (((x) & BIT_MASK_PKT_NUM_Q4_V1) << BIT_SHIFT_PKT_NUM_Q4_V1) -#define BIT_GET_PKT_NUM_Q4_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q4_V1) & BIT_MASK_PKT_NUM_Q4_V1) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC8 (56 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC8 0x1f +#define BIT_DARF_RC8(x) (((x) & BIT_MASK_DARF_RC8) << BIT_SHIFT_DARF_RC8) +#define BITS_DARF_RC8 (BIT_MASK_DARF_RC8 << BIT_SHIFT_DARF_RC8) +#define BIT_CLEAR_DARF_RC8(x) ((x) & (~BITS_DARF_RC8)) +#define BIT_GET_DARF_RC8(x) (((x) >> BIT_SHIFT_DARF_RC8) & BIT_MASK_DARF_RC8) +#define BIT_SET_DARF_RC8(x, v) (BIT_CLEAR_DARF_RC8(x) | BIT_DARF_RC8(v)) + +#define BIT_SHIFT_DARF_RC7 (48 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC7 0x1f +#define BIT_DARF_RC7(x) (((x) & BIT_MASK_DARF_RC7) << BIT_SHIFT_DARF_RC7) +#define BITS_DARF_RC7 (BIT_MASK_DARF_RC7 << BIT_SHIFT_DARF_RC7) +#define BIT_CLEAR_DARF_RC7(x) ((x) & (~BITS_DARF_RC7)) +#define BIT_GET_DARF_RC7(x) (((x) >> BIT_SHIFT_DARF_RC7) & BIT_MASK_DARF_RC7) +#define BIT_SET_DARF_RC7(x, v) (BIT_CLEAR_DARF_RC7(x) | BIT_DARF_RC7(v)) + +#define BIT_SHIFT_DARF_RC6 (40 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC6 0x1f +#define BIT_DARF_RC6(x) (((x) & BIT_MASK_DARF_RC6) << BIT_SHIFT_DARF_RC6) +#define BITS_DARF_RC6 (BIT_MASK_DARF_RC6 << BIT_SHIFT_DARF_RC6) +#define BIT_CLEAR_DARF_RC6(x) ((x) & (~BITS_DARF_RC6)) +#define BIT_GET_DARF_RC6(x) (((x) >> BIT_SHIFT_DARF_RC6) & BIT_MASK_DARF_RC6) +#define BIT_SET_DARF_RC6(x, v) (BIT_CLEAR_DARF_RC6(x) | BIT_DARF_RC6(v)) + +#define BIT_SHIFT_DARF_RC5 (32 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC5 0x1f +#define BIT_DARF_RC5(x) (((x) & BIT_MASK_DARF_RC5) << BIT_SHIFT_DARF_RC5) +#define BITS_DARF_RC5 (BIT_MASK_DARF_RC5 << BIT_SHIFT_DARF_RC5) +#define BIT_CLEAR_DARF_RC5(x) ((x) & (~BITS_DARF_RC5)) +#define BIT_GET_DARF_RC5(x) (((x) >> BIT_SHIFT_DARF_RC5) & BIT_MASK_DARF_RC5) +#define BIT_SET_DARF_RC5(x, v) (BIT_CLEAR_DARF_RC5(x) | BIT_DARF_RC5(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q4 0 -#define BIT_MASK_HEAD_PKT_Q4 0xff -#define BIT_HEAD_PKT_Q4(x) (((x) & BIT_MASK_HEAD_PKT_Q4) << BIT_SHIFT_HEAD_PKT_Q4) -#define BIT_GET_HEAD_PKT_Q4(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4) & BIT_MASK_HEAD_PKT_Q4) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC4 24 +#define BIT_MASK_DARF_RC4 0x1f +#define BIT_DARF_RC4(x) (((x) & BIT_MASK_DARF_RC4) << BIT_SHIFT_DARF_RC4) +#define BITS_DARF_RC4 (BIT_MASK_DARF_RC4 << BIT_SHIFT_DARF_RC4) +#define BIT_CLEAR_DARF_RC4(x) ((x) & (~BITS_DARF_RC4)) +#define BIT_GET_DARF_RC4(x) (((x) >> BIT_SHIFT_DARF_RC4) & BIT_MASK_DARF_RC4) +#define BIT_SET_DARF_RC4(x, v) (BIT_CLEAR_DARF_RC4(x) | BIT_DARF_RC4(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC4_V1 24 +#define BIT_MASK_DARF_RC4_V1 0x3f +#define BIT_DARF_RC4_V1(x) \ + (((x) & BIT_MASK_DARF_RC4_V1) << BIT_SHIFT_DARF_RC4_V1) +#define BITS_DARF_RC4_V1 (BIT_MASK_DARF_RC4_V1 << BIT_SHIFT_DARF_RC4_V1) +#define BIT_CLEAR_DARF_RC4_V1(x) ((x) & (~BITS_DARF_RC4_V1)) +#define BIT_GET_DARF_RC4_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_V1) & BIT_MASK_DARF_RC4_V1) +#define BIT_SET_DARF_RC4_V1(x, v) \ + (BIT_CLEAR_DARF_RC4_V1(x) | BIT_DARF_RC4_V1(v)) -/* 2 REG_Q4_INFO (Offset 0x0468) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q4_V1 0 -#define BIT_MASK_HEAD_PKT_Q4_V1 0x7ff -#define BIT_HEAD_PKT_Q4_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1) << BIT_SHIFT_HEAD_PKT_Q4_V1) -#define BIT_GET_HEAD_PKT_Q4_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1) & BIT_MASK_HEAD_PKT_Q4_V1) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC3 16 +#define BIT_MASK_DARF_RC3 0x1f +#define BIT_DARF_RC3(x) (((x) & BIT_MASK_DARF_RC3) << BIT_SHIFT_DARF_RC3) +#define BITS_DARF_RC3 (BIT_MASK_DARF_RC3 << BIT_SHIFT_DARF_RC3) +#define BIT_CLEAR_DARF_RC3(x) ((x) & (~BITS_DARF_RC3)) +#define BIT_GET_DARF_RC3(x) (((x) >> BIT_SHIFT_DARF_RC3) & BIT_MASK_DARF_RC3) +#define BIT_SET_DARF_RC3(x, v) (BIT_CLEAR_DARF_RC3(x) | BIT_DARF_RC3(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC3_V1 16 +#define BIT_MASK_DARF_RC3_V1 0x3f +#define BIT_DARF_RC3_V1(x) \ + (((x) & BIT_MASK_DARF_RC3_V1) << BIT_SHIFT_DARF_RC3_V1) +#define BITS_DARF_RC3_V1 (BIT_MASK_DARF_RC3_V1 << BIT_SHIFT_DARF_RC3_V1) +#define BIT_CLEAR_DARF_RC3_V1(x) ((x) & (~BITS_DARF_RC3_V1)) +#define BIT_GET_DARF_RC3_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_V1) & BIT_MASK_DARF_RC3_V1) +#define BIT_SET_DARF_RC3_V1(x, v) \ + (BIT_CLEAR_DARF_RC3_V1(x) | BIT_DARF_RC3_V1(v)) -/* 2 REG_Q5_INFO (Offset 0x046C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_QUEUEMACID_Q5_V1 25 -#define BIT_MASK_QUEUEMACID_Q5_V1 0x7f -#define BIT_QUEUEMACID_Q5_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1) -#define BIT_GET_QUEUEMACID_Q5_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC2 8 +#define BIT_MASK_DARF_RC2 0x1f +#define BIT_DARF_RC2(x) (((x) & BIT_MASK_DARF_RC2) << BIT_SHIFT_DARF_RC2) +#define BITS_DARF_RC2 (BIT_MASK_DARF_RC2 << BIT_SHIFT_DARF_RC2) +#define BIT_CLEAR_DARF_RC2(x) ((x) & (~BITS_DARF_RC2)) +#define BIT_GET_DARF_RC2(x) (((x) >> BIT_SHIFT_DARF_RC2) & BIT_MASK_DARF_RC2) +#define BIT_SET_DARF_RC2(x, v) (BIT_CLEAR_DARF_RC2(x) | BIT_DARF_RC2(v)) -#define BIT_SHIFT_QUEUEAC_Q5_V1 23 -#define BIT_MASK_QUEUEAC_Q5_V1 0x3 -#define BIT_QUEUEAC_Q5_V1(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1) -#define BIT_GET_QUEUEAC_Q5_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC2_V1 8 +#define BIT_MASK_DARF_RC2_V1 0x3f +#define BIT_DARF_RC2_V1(x) \ + (((x) & BIT_MASK_DARF_RC2_V1) << BIT_SHIFT_DARF_RC2_V1) +#define BITS_DARF_RC2_V1 (BIT_MASK_DARF_RC2_V1 << BIT_SHIFT_DARF_RC2_V1) +#define BIT_CLEAR_DARF_RC2_V1(x) ((x) & (~BITS_DARF_RC2_V1)) +#define BIT_GET_DARF_RC2_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_V1) & BIT_MASK_DARF_RC2_V1) +#define BIT_SET_DARF_RC2_V1(x, v) \ + (BIT_CLEAR_DARF_RC2_V1(x) | BIT_DARF_RC2_V1(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_Q5_INFO (Offset 0x046C) */ +/* 2 REG_DARFRC (Offset 0x0430) */ -#define BIT_TIDEMPTY_Q5_V1 BIT(22) +#define BIT_SHIFT_DARF_RC1 0 +#define BIT_MASK_DARF_RC1 0x1f +#define BIT_DARF_RC1(x) (((x) & BIT_MASK_DARF_RC1) << BIT_SHIFT_DARF_RC1) +#define BITS_DARF_RC1 (BIT_MASK_DARF_RC1 << BIT_SHIFT_DARF_RC1) +#define BIT_CLEAR_DARF_RC1(x) ((x) & (~BITS_DARF_RC1)) +#define BIT_GET_DARF_RC1(x) (((x) >> BIT_SHIFT_DARF_RC1) & BIT_MASK_DARF_RC1) +#define BIT_SET_DARF_RC1(x, v) (BIT_CLEAR_DARF_RC1(x) | BIT_DARF_RC1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC1_V1 0 +#define BIT_MASK_DARF_RC1_V1 0x3f +#define BIT_DARF_RC1_V1(x) \ + (((x) & BIT_MASK_DARF_RC1_V1) << BIT_SHIFT_DARF_RC1_V1) +#define BITS_DARF_RC1_V1 (BIT_MASK_DARF_RC1_V1 << BIT_SHIFT_DARF_RC1_V1) +#define BIT_CLEAR_DARF_RC1_V1(x) ((x) & (~BITS_DARF_RC1_V1)) +#define BIT_GET_DARF_RC1_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_V1) & BIT_MASK_DARF_RC1_V1) +#define BIT_SET_DARF_RC1_V1(x, v) \ + (BIT_CLEAR_DARF_RC1_V1(x) | BIT_DARF_RC1_V1(v)) + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DARFRCH (Offset 0x0434) */ + +#define BIT_SHIFT_DARF_RC8_V1 24 +#define BIT_MASK_DARF_RC8_V1 0x1f +#define BIT_DARF_RC8_V1(x) \ + (((x) & BIT_MASK_DARF_RC8_V1) << BIT_SHIFT_DARF_RC8_V1) +#define BITS_DARF_RC8_V1 (BIT_MASK_DARF_RC8_V1 << BIT_SHIFT_DARF_RC8_V1) +#define BIT_CLEAR_DARF_RC8_V1(x) ((x) & (~BITS_DARF_RC8_V1)) +#define BIT_GET_DARF_RC8_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_V1) & BIT_MASK_DARF_RC8_V1) +#define BIT_SET_DARF_RC8_V1(x, v) \ + (BIT_CLEAR_DARF_RC8_V1(x) | BIT_DARF_RC8_V1(v)) + +#define BIT_SHIFT_DARF_RC7_V1 16 +#define BIT_MASK_DARF_RC7_V1 0x1f +#define BIT_DARF_RC7_V1(x) \ + (((x) & BIT_MASK_DARF_RC7_V1) << BIT_SHIFT_DARF_RC7_V1) +#define BITS_DARF_RC7_V1 (BIT_MASK_DARF_RC7_V1 << BIT_SHIFT_DARF_RC7_V1) +#define BIT_CLEAR_DARF_RC7_V1(x) ((x) & (~BITS_DARF_RC7_V1)) +#define BIT_GET_DARF_RC7_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_V1) & BIT_MASK_DARF_RC7_V1) +#define BIT_SET_DARF_RC7_V1(x, v) \ + (BIT_CLEAR_DARF_RC7_V1(x) | BIT_DARF_RC7_V1(v)) + +#define BIT_SHIFT_DARF_RC6_V1 8 +#define BIT_MASK_DARF_RC6_V1 0x1f +#define BIT_DARF_RC6_V1(x) \ + (((x) & BIT_MASK_DARF_RC6_V1) << BIT_SHIFT_DARF_RC6_V1) +#define BITS_DARF_RC6_V1 (BIT_MASK_DARF_RC6_V1 << BIT_SHIFT_DARF_RC6_V1) +#define BIT_CLEAR_DARF_RC6_V1(x) ((x) & (~BITS_DARF_RC6_V1)) +#define BIT_GET_DARF_RC6_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_V1) & BIT_MASK_DARF_RC6_V1) +#define BIT_SET_DARF_RC6_V1(x, v) \ + (BIT_CLEAR_DARF_RC6_V1(x) | BIT_DARF_RC6_V1(v)) + +#define BIT_SHIFT_DARF_RC5_V1 0 +#define BIT_MASK_DARF_RC5_V1 0x1f +#define BIT_DARF_RC5_V1(x) \ + (((x) & BIT_MASK_DARF_RC5_V1) << BIT_SHIFT_DARF_RC5_V1) +#define BITS_DARF_RC5_V1 (BIT_MASK_DARF_RC5_V1 << BIT_SHIFT_DARF_RC5_V1) +#define BIT_CLEAR_DARF_RC5_V1(x) ((x) & (~BITS_DARF_RC5_V1)) +#define BIT_GET_DARF_RC5_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_V1) & BIT_MASK_DARF_RC5_V1) +#define BIT_SET_DARF_RC5_V1(x, v) \ + (BIT_CLEAR_DARF_RC5_V1(x) | BIT_DARF_RC5_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_Q5_INFO (Offset 0x046C) */ +/* 2 REG_RARFRC (Offset 0x0438) */ +#define BIT_SHIFT_RARF_RC8 (56 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC8 0x1f +#define BIT_RARF_RC8(x) (((x) & BIT_MASK_RARF_RC8) << BIT_SHIFT_RARF_RC8) +#define BITS_RARF_RC8 (BIT_MASK_RARF_RC8 << BIT_SHIFT_RARF_RC8) +#define BIT_CLEAR_RARF_RC8(x) ((x) & (~BITS_RARF_RC8)) +#define BIT_GET_RARF_RC8(x) (((x) >> BIT_SHIFT_RARF_RC8) & BIT_MASK_RARF_RC8) +#define BIT_SET_RARF_RC8(x, v) (BIT_CLEAR_RARF_RC8(x) | BIT_RARF_RC8(v)) + +#define BIT_SHIFT_RARF_RC7 (48 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC7 0x1f +#define BIT_RARF_RC7(x) (((x) & BIT_MASK_RARF_RC7) << BIT_SHIFT_RARF_RC7) +#define BITS_RARF_RC7 (BIT_MASK_RARF_RC7 << BIT_SHIFT_RARF_RC7) +#define BIT_CLEAR_RARF_RC7(x) ((x) & (~BITS_RARF_RC7)) +#define BIT_GET_RARF_RC7(x) (((x) >> BIT_SHIFT_RARF_RC7) & BIT_MASK_RARF_RC7) +#define BIT_SET_RARF_RC7(x, v) (BIT_CLEAR_RARF_RC7(x) | BIT_RARF_RC7(v)) + +#define BIT_SHIFT_RARF_RC6 (40 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC6 0x1f +#define BIT_RARF_RC6(x) (((x) & BIT_MASK_RARF_RC6) << BIT_SHIFT_RARF_RC6) +#define BITS_RARF_RC6 (BIT_MASK_RARF_RC6 << BIT_SHIFT_RARF_RC6) +#define BIT_CLEAR_RARF_RC6(x) ((x) & (~BITS_RARF_RC6)) +#define BIT_GET_RARF_RC6(x) (((x) >> BIT_SHIFT_RARF_RC6) & BIT_MASK_RARF_RC6) +#define BIT_SET_RARF_RC6(x, v) (BIT_CLEAR_RARF_RC6(x) | BIT_RARF_RC6(v)) + +#define BIT_SHIFT_RARF_RC5 (32 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC5 0x1f +#define BIT_RARF_RC5(x) (((x) & BIT_MASK_RARF_RC5) << BIT_SHIFT_RARF_RC5) +#define BITS_RARF_RC5 (BIT_MASK_RARF_RC5 << BIT_SHIFT_RARF_RC5) +#define BIT_CLEAR_RARF_RC5(x) ((x) & (~BITS_RARF_RC5)) +#define BIT_GET_RARF_RC5(x) (((x) >> BIT_SHIFT_RARF_RC5) & BIT_MASK_RARF_RC5) +#define BIT_SET_RARF_RC5(x, v) (BIT_CLEAR_RARF_RC5(x) | BIT_RARF_RC5(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q5_V1 15 -#define BIT_MASK_TAIL_PKT_Q5_V1 0xff -#define BIT_TAIL_PKT_Q5_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V1) << BIT_SHIFT_TAIL_PKT_Q5_V1) -#define BIT_GET_TAIL_PKT_Q5_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V1) & BIT_MASK_TAIL_PKT_Q5_V1) +/* 2 REG_RARFRC (Offset 0x0438) */ + +#define BIT_SHIFT_RARF_RC4 24 +#define BIT_MASK_RARF_RC4 0x1f +#define BIT_RARF_RC4(x) (((x) & BIT_MASK_RARF_RC4) << BIT_SHIFT_RARF_RC4) +#define BITS_RARF_RC4 (BIT_MASK_RARF_RC4 << BIT_SHIFT_RARF_RC4) +#define BIT_CLEAR_RARF_RC4(x) ((x) & (~BITS_RARF_RC4)) +#define BIT_GET_RARF_RC4(x) (((x) >> BIT_SHIFT_RARF_RC4) & BIT_MASK_RARF_RC4) +#define BIT_SET_RARF_RC4(x, v) (BIT_CLEAR_RARF_RC4(x) | BIT_RARF_RC4(v)) + +#define BIT_SHIFT_RARF_RC3 16 +#define BIT_MASK_RARF_RC3 0x1f +#define BIT_RARF_RC3(x) (((x) & BIT_MASK_RARF_RC3) << BIT_SHIFT_RARF_RC3) +#define BITS_RARF_RC3 (BIT_MASK_RARF_RC3 << BIT_SHIFT_RARF_RC3) +#define BIT_CLEAR_RARF_RC3(x) ((x) & (~BITS_RARF_RC3)) +#define BIT_GET_RARF_RC3(x) (((x) >> BIT_SHIFT_RARF_RC3) & BIT_MASK_RARF_RC3) +#define BIT_SET_RARF_RC3(x, v) (BIT_CLEAR_RARF_RC3(x) | BIT_RARF_RC3(v)) + +#define BIT_SHIFT_RARF_RC2 8 +#define BIT_MASK_RARF_RC2 0x1f +#define BIT_RARF_RC2(x) (((x) & BIT_MASK_RARF_RC2) << BIT_SHIFT_RARF_RC2) +#define BITS_RARF_RC2 (BIT_MASK_RARF_RC2 << BIT_SHIFT_RARF_RC2) +#define BIT_CLEAR_RARF_RC2(x) ((x) & (~BITS_RARF_RC2)) +#define BIT_GET_RARF_RC2(x) (((x) >> BIT_SHIFT_RARF_RC2) & BIT_MASK_RARF_RC2) +#define BIT_SET_RARF_RC2(x, v) (BIT_CLEAR_RARF_RC2(x) | BIT_RARF_RC2(v)) + +#define BIT_SHIFT_RARF_RC1 0 +#define BIT_MASK_RARF_RC1 0x1f +#define BIT_RARF_RC1(x) (((x) & BIT_MASK_RARF_RC1) << BIT_SHIFT_RARF_RC1) +#define BITS_RARF_RC1 (BIT_MASK_RARF_RC1 << BIT_SHIFT_RARF_RC1) +#define BIT_CLEAR_RARF_RC1(x) ((x) & (~BITS_RARF_RC1)) +#define BIT_GET_RARF_RC1(x) (((x) >> BIT_SHIFT_RARF_RC1) & BIT_MASK_RARF_RC1) +#define BIT_SET_RARF_RC1(x, v) (BIT_CLEAR_RARF_RC1(x) | BIT_RARF_RC1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_RARFRCH (Offset 0x043C) */ + +#define BIT_SHIFT_RARF_RC8_V1 24 +#define BIT_MASK_RARF_RC8_V1 0x1f +#define BIT_RARF_RC8_V1(x) \ + (((x) & BIT_MASK_RARF_RC8_V1) << BIT_SHIFT_RARF_RC8_V1) +#define BITS_RARF_RC8_V1 (BIT_MASK_RARF_RC8_V1 << BIT_SHIFT_RARF_RC8_V1) +#define BIT_CLEAR_RARF_RC8_V1(x) ((x) & (~BITS_RARF_RC8_V1)) +#define BIT_GET_RARF_RC8_V1(x) \ + (((x) >> BIT_SHIFT_RARF_RC8_V1) & BIT_MASK_RARF_RC8_V1) +#define BIT_SET_RARF_RC8_V1(x, v) \ + (BIT_CLEAR_RARF_RC8_V1(x) | BIT_RARF_RC8_V1(v)) + +#define BIT_SHIFT_RARF_RC7_V1 16 +#define BIT_MASK_RARF_RC7_V1 0x1f +#define BIT_RARF_RC7_V1(x) \ + (((x) & BIT_MASK_RARF_RC7_V1) << BIT_SHIFT_RARF_RC7_V1) +#define BITS_RARF_RC7_V1 (BIT_MASK_RARF_RC7_V1 << BIT_SHIFT_RARF_RC7_V1) +#define BIT_CLEAR_RARF_RC7_V1(x) ((x) & (~BITS_RARF_RC7_V1)) +#define BIT_GET_RARF_RC7_V1(x) \ + (((x) >> BIT_SHIFT_RARF_RC7_V1) & BIT_MASK_RARF_RC7_V1) +#define BIT_SET_RARF_RC7_V1(x, v) \ + (BIT_CLEAR_RARF_RC7_V1(x) | BIT_RARF_RC7_V1(v)) + +#define BIT_SHIFT_RARF_RC6_V1 8 +#define BIT_MASK_RARF_RC6_V1 0x1f +#define BIT_RARF_RC6_V1(x) \ + (((x) & BIT_MASK_RARF_RC6_V1) << BIT_SHIFT_RARF_RC6_V1) +#define BITS_RARF_RC6_V1 (BIT_MASK_RARF_RC6_V1 << BIT_SHIFT_RARF_RC6_V1) +#define BIT_CLEAR_RARF_RC6_V1(x) ((x) & (~BITS_RARF_RC6_V1)) +#define BIT_GET_RARF_RC6_V1(x) \ + (((x) >> BIT_SHIFT_RARF_RC6_V1) & BIT_MASK_RARF_RC6_V1) +#define BIT_SET_RARF_RC6_V1(x, v) \ + (BIT_CLEAR_RARF_RC6_V1(x) | BIT_RARF_RC6_V1(v)) + +#define BIT_SHIFT_RARF_RC5_V1 0 +#define BIT_MASK_RARF_RC5_V1 0x1f +#define BIT_RARF_RC5_V1(x) \ + (((x) & BIT_MASK_RARF_RC5_V1) << BIT_SHIFT_RARF_RC5_V1) +#define BITS_RARF_RC5_V1 (BIT_MASK_RARF_RC5_V1 << BIT_SHIFT_RARF_RC5_V1) +#define BIT_CLEAR_RARF_RC5_V1(x) ((x) & (~BITS_RARF_RC5_V1)) +#define BIT_GET_RARF_RC5_V1(x) \ + (((x) >> BIT_SHIFT_RARF_RC5_V1) & BIT_MASK_RARF_RC5_V1) +#define BIT_SET_RARF_RC5_V1(x, v) \ + (BIT_CLEAR_RARF_RC5_V1(x) | BIT_RARF_RC5_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_RRSR (Offset 0x0440) */ +#define BIT_EN_VHTBW_FALL BIT(31) +#define BIT_EN_HTBW_FALL BIT(30) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RRSR (Offset 0x0440) */ +#define BIT_SHIFT_RRSR_RSC 21 +#define BIT_MASK_RRSR_RSC 0x3 +#define BIT_RRSR_RSC(x) (((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC) +#define BITS_RRSR_RSC (BIT_MASK_RRSR_RSC << BIT_SHIFT_RRSR_RSC) +#define BIT_CLEAR_RRSR_RSC(x) ((x) & (~BITS_RRSR_RSC)) +#define BIT_GET_RRSR_RSC(x) (((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC) +#define BIT_SET_RRSR_RSC(x, v) (BIT_CLEAR_RRSR_RSC(x) | BIT_RRSR_RSC(v)) -/* 2 REG_Q5_INFO (Offset 0x046C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q5_V2 11 -#define BIT_MASK_TAIL_PKT_Q5_V2 0x7ff -#define BIT_TAIL_PKT_Q5_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2) << BIT_SHIFT_TAIL_PKT_Q5_V2) -#define BIT_GET_TAIL_PKT_Q5_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2) & BIT_MASK_TAIL_PKT_Q5_V2) +/* 2 REG_RRSR (Offset 0x0440) */ +#define BIT_RRSR_BW BIT(20) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RRSR (Offset 0x0440) */ +#define BIT_SHIFT_RRSC_BITMAP 0 +#define BIT_MASK_RRSC_BITMAP 0xfffff +#define BIT_RRSC_BITMAP(x) \ + (((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP) +#define BITS_RRSC_BITMAP (BIT_MASK_RRSC_BITMAP << BIT_SHIFT_RRSC_BITMAP) +#define BIT_CLEAR_RRSC_BITMAP(x) ((x) & (~BITS_RRSC_BITMAP)) +#define BIT_GET_RRSC_BITMAP(x) \ + (((x) >> BIT_SHIFT_RRSC_BITMAP) & BIT_MASK_RRSC_BITMAP) +#define BIT_SET_RRSC_BITMAP(x, v) \ + (BIT_CLEAR_RRSC_BITMAP(x) | BIT_RRSC_BITMAP(v)) -/* 2 REG_Q5_INFO (Offset 0x046C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKT_NUM_Q5_V1 8 -#define BIT_MASK_PKT_NUM_Q5_V1 0x7f -#define BIT_PKT_NUM_Q5_V1(x) (((x) & BIT_MASK_PKT_NUM_Q5_V1) << BIT_SHIFT_PKT_NUM_Q5_V1) -#define BIT_GET_PKT_NUM_Q5_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q5_V1) & BIT_MASK_PKT_NUM_Q5_V1) +/* 2 REG_ARFR0 (Offset 0x0444) */ +#define BIT_SHIFT_ARFR0_V1 0 +#define BIT_MASK_ARFR0_V1 0xffffffffffffffffL +#define BIT_ARFR0_V1(x) (((x) & BIT_MASK_ARFR0_V1) << BIT_SHIFT_ARFR0_V1) +#define BITS_ARFR0_V1 (BIT_MASK_ARFR0_V1 << BIT_SHIFT_ARFR0_V1) +#define BIT_CLEAR_ARFR0_V1(x) ((x) & (~BITS_ARFR0_V1)) +#define BIT_GET_ARFR0_V1(x) (((x) >> BIT_SHIFT_ARFR0_V1) & BIT_MASK_ARFR0_V1) +#define BIT_SET_ARFR0_V1(x, v) (BIT_CLEAR_ARFR0_V1(x) | BIT_ARFR0_V1(v)) -#define BIT_SHIFT_HEAD_PKT_Q5 0 -#define BIT_MASK_HEAD_PKT_Q5 0xff -#define BIT_HEAD_PKT_Q5(x) (((x) & BIT_MASK_HEAD_PKT_Q5) << BIT_SHIFT_HEAD_PKT_Q5) -#define BIT_GET_HEAD_PKT_Q5(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5) & BIT_MASK_HEAD_PKT_Q5) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ARFR0 (Offset 0x0444) */ +#define BIT_SHIFT_ARFRL0 0 +#define BIT_MASK_ARFRL0 0xffffffffL +#define BIT_ARFRL0(x) (((x) & BIT_MASK_ARFRL0) << BIT_SHIFT_ARFRL0) +#define BITS_ARFRL0 (BIT_MASK_ARFRL0 << BIT_SHIFT_ARFRL0) +#define BIT_CLEAR_ARFRL0(x) ((x) & (~BITS_ARFRL0)) +#define BIT_GET_ARFRL0(x) (((x) >> BIT_SHIFT_ARFRL0) & BIT_MASK_ARFRL0) +#define BIT_SET_ARFRL0(x, v) (BIT_CLEAR_ARFRL0(x) | BIT_ARFRL0(v)) + +/* 2 REG_ARFRH0 (Offset 0x0448) */ + +#define BIT_SHIFT_ARFRH0 0 +#define BIT_MASK_ARFRH0 0xffffffffL +#define BIT_ARFRH0(x) (((x) & BIT_MASK_ARFRH0) << BIT_SHIFT_ARFRH0) +#define BITS_ARFRH0 (BIT_MASK_ARFRH0 << BIT_SHIFT_ARFRH0) +#define BIT_CLEAR_ARFRH0(x) ((x) & (~BITS_ARFRH0)) +#define BIT_GET_ARFRH0(x) (((x) >> BIT_SHIFT_ARFRH0) & BIT_MASK_ARFRH0) +#define BIT_SET_ARFRH0(x, v) (BIT_CLEAR_ARFRH0(x) | BIT_ARFRH0(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_REG_ARFR_WT0 (Offset 0x044C) */ + +#define BIT_SHIFT_RATE7_WEIGHTING 28 +#define BIT_MASK_RATE7_WEIGHTING 0xf +#define BIT_RATE7_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE7_WEIGHTING) << BIT_SHIFT_RATE7_WEIGHTING) +#define BITS_RATE7_WEIGHTING \ + (BIT_MASK_RATE7_WEIGHTING << BIT_SHIFT_RATE7_WEIGHTING) +#define BIT_CLEAR_RATE7_WEIGHTING(x) ((x) & (~BITS_RATE7_WEIGHTING)) +#define BIT_GET_RATE7_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE7_WEIGHTING) & BIT_MASK_RATE7_WEIGHTING) +#define BIT_SET_RATE7_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE7_WEIGHTING(x) | BIT_RATE7_WEIGHTING(v)) + +#define BIT_SHIFT_RATE6_WEIGHTING 24 +#define BIT_MASK_RATE6_WEIGHTING 0xf +#define BIT_RATE6_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE6_WEIGHTING) << BIT_SHIFT_RATE6_WEIGHTING) +#define BITS_RATE6_WEIGHTING \ + (BIT_MASK_RATE6_WEIGHTING << BIT_SHIFT_RATE6_WEIGHTING) +#define BIT_CLEAR_RATE6_WEIGHTING(x) ((x) & (~BITS_RATE6_WEIGHTING)) +#define BIT_GET_RATE6_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE6_WEIGHTING) & BIT_MASK_RATE6_WEIGHTING) +#define BIT_SET_RATE6_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE6_WEIGHTING(x) | BIT_RATE6_WEIGHTING(v)) + +#define BIT_SHIFT_RATE5_WEIGHTING 20 +#define BIT_MASK_RATE5_WEIGHTING 0xf +#define BIT_RATE5_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE5_WEIGHTING) << BIT_SHIFT_RATE5_WEIGHTING) +#define BITS_RATE5_WEIGHTING \ + (BIT_MASK_RATE5_WEIGHTING << BIT_SHIFT_RATE5_WEIGHTING) +#define BIT_CLEAR_RATE5_WEIGHTING(x) ((x) & (~BITS_RATE5_WEIGHTING)) +#define BIT_GET_RATE5_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE5_WEIGHTING) & BIT_MASK_RATE5_WEIGHTING) +#define BIT_SET_RATE5_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE5_WEIGHTING(x) | BIT_RATE5_WEIGHTING(v)) + +#define BIT_SHIFT_RATE4_WEIGHTING 16 +#define BIT_MASK_RATE4_WEIGHTING 0xf +#define BIT_RATE4_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE4_WEIGHTING) << BIT_SHIFT_RATE4_WEIGHTING) +#define BITS_RATE4_WEIGHTING \ + (BIT_MASK_RATE4_WEIGHTING << BIT_SHIFT_RATE4_WEIGHTING) +#define BIT_CLEAR_RATE4_WEIGHTING(x) ((x) & (~BITS_RATE4_WEIGHTING)) +#define BIT_GET_RATE4_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE4_WEIGHTING) & BIT_MASK_RATE4_WEIGHTING) +#define BIT_SET_RATE4_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE4_WEIGHTING(x) | BIT_RATE4_WEIGHTING(v)) + +#define BIT_SHIFT_RATE3_WEIGHTING 12 +#define BIT_MASK_RATE3_WEIGHTING 0xf +#define BIT_RATE3_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE3_WEIGHTING) << BIT_SHIFT_RATE3_WEIGHTING) +#define BITS_RATE3_WEIGHTING \ + (BIT_MASK_RATE3_WEIGHTING << BIT_SHIFT_RATE3_WEIGHTING) +#define BIT_CLEAR_RATE3_WEIGHTING(x) ((x) & (~BITS_RATE3_WEIGHTING)) +#define BIT_GET_RATE3_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE3_WEIGHTING) & BIT_MASK_RATE3_WEIGHTING) +#define BIT_SET_RATE3_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE3_WEIGHTING(x) | BIT_RATE3_WEIGHTING(v)) + +#define BIT_SHIFT_RATE2_WEIGHTING 8 +#define BIT_MASK_RATE2_WEIGHTING 0xf +#define BIT_RATE2_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE2_WEIGHTING) << BIT_SHIFT_RATE2_WEIGHTING) +#define BITS_RATE2_WEIGHTING \ + (BIT_MASK_RATE2_WEIGHTING << BIT_SHIFT_RATE2_WEIGHTING) +#define BIT_CLEAR_RATE2_WEIGHTING(x) ((x) & (~BITS_RATE2_WEIGHTING)) +#define BIT_GET_RATE2_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE2_WEIGHTING) & BIT_MASK_RATE2_WEIGHTING) +#define BIT_SET_RATE2_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE2_WEIGHTING(x) | BIT_RATE2_WEIGHTING(v)) + +#define BIT_SHIFT_RATE1_WEIGHTING 4 +#define BIT_MASK_RATE1_WEIGHTING 0xf +#define BIT_RATE1_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE1_WEIGHTING) << BIT_SHIFT_RATE1_WEIGHTING) +#define BITS_RATE1_WEIGHTING \ + (BIT_MASK_RATE1_WEIGHTING << BIT_SHIFT_RATE1_WEIGHTING) +#define BIT_CLEAR_RATE1_WEIGHTING(x) ((x) & (~BITS_RATE1_WEIGHTING)) +#define BIT_GET_RATE1_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE1_WEIGHTING) & BIT_MASK_RATE1_WEIGHTING) +#define BIT_SET_RATE1_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE1_WEIGHTING(x) | BIT_RATE1_WEIGHTING(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ARFR1_V1 (Offset 0x044C) */ +#define BIT_SHIFT_ARFR1_V1 0 +#define BIT_MASK_ARFR1_V1 0xffffffffffffffffL +#define BIT_ARFR1_V1(x) (((x) & BIT_MASK_ARFR1_V1) << BIT_SHIFT_ARFR1_V1) +#define BITS_ARFR1_V1 (BIT_MASK_ARFR1_V1 << BIT_SHIFT_ARFR1_V1) +#define BIT_CLEAR_ARFR1_V1(x) ((x) & (~BITS_ARFR1_V1)) +#define BIT_GET_ARFR1_V1(x) (((x) >> BIT_SHIFT_ARFR1_V1) & BIT_MASK_ARFR1_V1) +#define BIT_SET_ARFR1_V1(x, v) (BIT_CLEAR_ARFR1_V1(x) | BIT_ARFR1_V1(v)) -/* 2 REG_Q5_INFO (Offset 0x046C) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q5_V1 0 -#define BIT_MASK_HEAD_PKT_Q5_V1 0x7ff -#define BIT_HEAD_PKT_Q5_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1) << BIT_SHIFT_HEAD_PKT_Q5_V1) -#define BIT_GET_HEAD_PKT_Q5_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1) & BIT_MASK_HEAD_PKT_Q5_V1) +/* 2 REG_REG_ARFR_WT0 (Offset 0x044C) */ +#define BIT_SHIFT_RATE0_WEIGHTING 0 +#define BIT_MASK_RATE0_WEIGHTING 0xf +#define BIT_RATE0_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE0_WEIGHTING) << BIT_SHIFT_RATE0_WEIGHTING) +#define BITS_RATE0_WEIGHTING \ + (BIT_MASK_RATE0_WEIGHTING << BIT_SHIFT_RATE0_WEIGHTING) +#define BIT_CLEAR_RATE0_WEIGHTING(x) ((x) & (~BITS_RATE0_WEIGHTING)) +#define BIT_GET_RATE0_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE0_WEIGHTING) & BIT_MASK_RATE0_WEIGHTING) +#define BIT_SET_RATE0_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE0_WEIGHTING(x) | BIT_RATE0_WEIGHTING(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ARFR1_V1 (Offset 0x044C) */ +#define BIT_SHIFT_ARFRL1 0 +#define BIT_MASK_ARFRL1 0xffffffffL +#define BIT_ARFRL1(x) (((x) & BIT_MASK_ARFRL1) << BIT_SHIFT_ARFRL1) +#define BITS_ARFRL1 (BIT_MASK_ARFRL1 << BIT_SHIFT_ARFRL1) +#define BIT_CLEAR_ARFRL1(x) ((x) & (~BITS_ARFRL1)) +#define BIT_GET_ARFRL1(x) (((x) >> BIT_SHIFT_ARFRL1) & BIT_MASK_ARFRL1) +#define BIT_SET_ARFRL1(x, v) (BIT_CLEAR_ARFRL1(x) | BIT_ARFRL1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_REG_ARFR_WT1 (Offset 0x0450) */ + +#define BIT_SHIFT_RATE15_WEIGHTING 28 +#define BIT_MASK_RATE15_WEIGHTING 0xf +#define BIT_RATE15_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE15_WEIGHTING) << BIT_SHIFT_RATE15_WEIGHTING) +#define BITS_RATE15_WEIGHTING \ + (BIT_MASK_RATE15_WEIGHTING << BIT_SHIFT_RATE15_WEIGHTING) +#define BIT_CLEAR_RATE15_WEIGHTING(x) ((x) & (~BITS_RATE15_WEIGHTING)) +#define BIT_GET_RATE15_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE15_WEIGHTING) & BIT_MASK_RATE15_WEIGHTING) +#define BIT_SET_RATE15_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE15_WEIGHTING(x) | BIT_RATE15_WEIGHTING(v)) + +#define BIT_SHIFT_RATE14_WEIGHTING 24 +#define BIT_MASK_RATE14_WEIGHTING 0xf +#define BIT_RATE14_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE14_WEIGHTING) << BIT_SHIFT_RATE14_WEIGHTING) +#define BITS_RATE14_WEIGHTING \ + (BIT_MASK_RATE14_WEIGHTING << BIT_SHIFT_RATE14_WEIGHTING) +#define BIT_CLEAR_RATE14_WEIGHTING(x) ((x) & (~BITS_RATE14_WEIGHTING)) +#define BIT_GET_RATE14_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE14_WEIGHTING) & BIT_MASK_RATE14_WEIGHTING) +#define BIT_SET_RATE14_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE14_WEIGHTING(x) | BIT_RATE14_WEIGHTING(v)) + +#define BIT_SHIFT_RATE13_WEIGHTING 20 +#define BIT_MASK_RATE13_WEIGHTING 0xf +#define BIT_RATE13_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE13_WEIGHTING) << BIT_SHIFT_RATE13_WEIGHTING) +#define BITS_RATE13_WEIGHTING \ + (BIT_MASK_RATE13_WEIGHTING << BIT_SHIFT_RATE13_WEIGHTING) +#define BIT_CLEAR_RATE13_WEIGHTING(x) ((x) & (~BITS_RATE13_WEIGHTING)) +#define BIT_GET_RATE13_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE13_WEIGHTING) & BIT_MASK_RATE13_WEIGHTING) +#define BIT_SET_RATE13_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE13_WEIGHTING(x) | BIT_RATE13_WEIGHTING(v)) + +#define BIT_SHIFT_RATE12_WEIGHTING 16 +#define BIT_MASK_RATE12_WEIGHTING 0xf +#define BIT_RATE12_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE12_WEIGHTING) << BIT_SHIFT_RATE12_WEIGHTING) +#define BITS_RATE12_WEIGHTING \ + (BIT_MASK_RATE12_WEIGHTING << BIT_SHIFT_RATE12_WEIGHTING) +#define BIT_CLEAR_RATE12_WEIGHTING(x) ((x) & (~BITS_RATE12_WEIGHTING)) +#define BIT_GET_RATE12_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE12_WEIGHTING) & BIT_MASK_RATE12_WEIGHTING) +#define BIT_SET_RATE12_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE12_WEIGHTING(x) | BIT_RATE12_WEIGHTING(v)) + +#define BIT_SHIFT_RATE11_WEIGHTING 12 +#define BIT_MASK_RATE11_WEIGHTING 0xf +#define BIT_RATE11_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE11_WEIGHTING) << BIT_SHIFT_RATE11_WEIGHTING) +#define BITS_RATE11_WEIGHTING \ + (BIT_MASK_RATE11_WEIGHTING << BIT_SHIFT_RATE11_WEIGHTING) +#define BIT_CLEAR_RATE11_WEIGHTING(x) ((x) & (~BITS_RATE11_WEIGHTING)) +#define BIT_GET_RATE11_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE11_WEIGHTING) & BIT_MASK_RATE11_WEIGHTING) +#define BIT_SET_RATE11_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE11_WEIGHTING(x) | BIT_RATE11_WEIGHTING(v)) + +#define BIT_SHIFT_RATE10_WEIGHTING 8 +#define BIT_MASK_RATE10_WEIGHTING 0xf +#define BIT_RATE10_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE10_WEIGHTING) << BIT_SHIFT_RATE10_WEIGHTING) +#define BITS_RATE10_WEIGHTING \ + (BIT_MASK_RATE10_WEIGHTING << BIT_SHIFT_RATE10_WEIGHTING) +#define BIT_CLEAR_RATE10_WEIGHTING(x) ((x) & (~BITS_RATE10_WEIGHTING)) +#define BIT_GET_RATE10_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE10_WEIGHTING) & BIT_MASK_RATE10_WEIGHTING) +#define BIT_SET_RATE10_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE10_WEIGHTING(x) | BIT_RATE10_WEIGHTING(v)) + +#define BIT_SHIFT_RATE9_WEIGHTING 4 +#define BIT_MASK_RATE9_WEIGHTING 0xf +#define BIT_RATE9_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE9_WEIGHTING) << BIT_SHIFT_RATE9_WEIGHTING) +#define BITS_RATE9_WEIGHTING \ + (BIT_MASK_RATE9_WEIGHTING << BIT_SHIFT_RATE9_WEIGHTING) +#define BIT_CLEAR_RATE9_WEIGHTING(x) ((x) & (~BITS_RATE9_WEIGHTING)) +#define BIT_GET_RATE9_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE9_WEIGHTING) & BIT_MASK_RATE9_WEIGHTING) +#define BIT_SET_RATE9_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE9_WEIGHTING(x) | BIT_RATE9_WEIGHTING(v)) + +#define BIT_SHIFT_RATE8_WEIGHTING 0 +#define BIT_MASK_RATE8_WEIGHTING 0xf +#define BIT_RATE8_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE8_WEIGHTING) << BIT_SHIFT_RATE8_WEIGHTING) +#define BITS_RATE8_WEIGHTING \ + (BIT_MASK_RATE8_WEIGHTING << BIT_SHIFT_RATE8_WEIGHTING) +#define BIT_CLEAR_RATE8_WEIGHTING(x) ((x) & (~BITS_RATE8_WEIGHTING)) +#define BIT_GET_RATE8_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE8_WEIGHTING) & BIT_MASK_RATE8_WEIGHTING) +#define BIT_SET_RATE8_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE8_WEIGHTING(x) | BIT_RATE8_WEIGHTING(v)) + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ARFRH1_V1 (Offset 0x0450) */ + +#define BIT_SHIFT_ARFRH1 0 +#define BIT_MASK_ARFRH1 0xffffffffL +#define BIT_ARFRH1(x) (((x) & BIT_MASK_ARFRH1) << BIT_SHIFT_ARFRH1) +#define BITS_ARFRH1 (BIT_MASK_ARFRH1 << BIT_SHIFT_ARFRH1) +#define BIT_CLEAR_ARFRH1(x) ((x) & (~BITS_ARFRH1)) +#define BIT_GET_ARFRH1(x) (((x) >> BIT_SHIFT_ARFRH1) & BIT_MASK_ARFRH1) +#define BIT_SET_ARFRH1(x, v) (BIT_CLEAR_ARFRH1(x) | BIT_ARFRH1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_Q6_INFO (Offset 0x0470) */ +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_CHECK_CCK_EN BIT(7) -#define BIT_SHIFT_QUEUEMACID_Q6_V1 25 -#define BIT_MASK_QUEUEMACID_Q6_V1 0x7f -#define BIT_QUEUEMACID_Q6_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1) -#define BIT_GET_QUEUEMACID_Q6_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_QUEUEAC_Q6_V1 23 -#define BIT_MASK_QUEUEAC_Q6_V1 0x3 -#define BIT_QUEUEAC_Q6_V1(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1) -#define BIT_GET_QUEUEAC_Q6_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_EN_BCN_PKT_REL BIT(6) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_Q6_INFO (Offset 0x0470) */ +/* 2 REG_CCK_CHECK (Offset 0x0454) */ -#define BIT_TIDEMPTY_Q6_V1 BIT(22) +#define BIT_EN_BCN_PKT_REL_P0 BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_BCN_PORT_SEL BIT(5) +#define BIT_MOREDATA_BYPASS BIT(4) -/* 2 REG_Q6_INFO (Offset 0x0470) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q6_V1 15 -#define BIT_MASK_TAIL_PKT_Q6_V1 0xff -#define BIT_TAIL_PKT_Q6_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V1) << BIT_SHIFT_TAIL_PKT_Q6_V1) -#define BIT_GET_TAIL_PKT_Q6_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V1) & BIT_MASK_TAIL_PKT_Q6_V1) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_EN_CLR_CMD_REL_BCN_PKT BIT(3) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P0 BIT(3) -/* 2 REG_Q6_INFO (Offset 0x0470) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q6_V2 11 -#define BIT_MASK_TAIL_PKT_Q6_V2 0x7ff -#define BIT_TAIL_PKT_Q6_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2) << BIT_SHIFT_TAIL_PKT_Q6_V2) -#define BIT_GET_TAIL_PKT_Q6_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2) & BIT_MASK_TAIL_PKT_Q6_V2) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_R_EN_SET_MOREDATA BIT(2) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_Q6_INFO (Offset 0x0470) */ +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_EN_SET_MOREDATA BIT(2) -#define BIT_SHIFT_PKT_NUM_Q6_V1 8 -#define BIT_MASK_PKT_NUM_Q6_V1 0x7f -#define BIT_PKT_NUM_Q6_V1(x) (((x) & BIT_MASK_PKT_NUM_Q6_V1) << BIT_SHIFT_PKT_NUM_Q6_V1) -#define BIT_GET_PKT_NUM_Q6_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q6_V1) & BIT_MASK_PKT_NUM_Q6_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q6 0 -#define BIT_MASK_HEAD_PKT_Q6 0xff -#define BIT_HEAD_PKT_Q6(x) (((x) & BIT_MASK_HEAD_PKT_Q6) << BIT_SHIFT_HEAD_PKT_Q6) -#define BIT_GET_HEAD_PKT_Q6(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6) & BIT_MASK_HEAD_PKT_Q6) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT__R_DIS_CLEAR_MACID_RELEASE BIT(1) +#define BIT__R_MACID_RELEASE_EN BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AMPDU_BURST_CTRL (Offset 0x0455) */ +#define BIT_AMPDU_BURST_GLOBAL_EN BIT(0) -/* 2 REG_Q6_INFO (Offset 0x0470) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q6_V1 0 -#define BIT_MASK_HEAD_PKT_Q6_V1 0x7ff -#define BIT_HEAD_PKT_Q6_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1) << BIT_SHIFT_HEAD_PKT_Q6_V1) -#define BIT_GET_HEAD_PKT_Q6_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1) & BIT_MASK_HEAD_PKT_Q6_V1) +/* 2 REG_AMPDU_MAX_TIME (Offset 0x0456) */ +#define BIT_SHIFT_AMPDU_MAX_TIME 0 +#define BIT_MASK_AMPDU_MAX_TIME 0xff +#define BIT_AMPDU_MAX_TIME(x) \ + (((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME) +#define BITS_AMPDU_MAX_TIME \ + (BIT_MASK_AMPDU_MAX_TIME << BIT_SHIFT_AMPDU_MAX_TIME) +#define BIT_CLEAR_AMPDU_MAX_TIME(x) ((x) & (~BITS_AMPDU_MAX_TIME)) +#define BIT_GET_AMPDU_MAX_TIME(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME) +#define BIT_SET_AMPDU_MAX_TIME(x, v) \ + (BIT_CLEAR_AMPDU_MAX_TIME(x) | BIT_AMPDU_MAX_TIME(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCNQ1_BDNY_V1 (Offset 0x0456) */ +#define BIT_SHIFT_BCNQ1_PGBNDY_V1 0 +#define BIT_MASK_BCNQ1_PGBNDY_V1 0xfff +#define BIT_BCNQ1_PGBNDY_V1(x) \ + (((x) & BIT_MASK_BCNQ1_PGBNDY_V1) << BIT_SHIFT_BCNQ1_PGBNDY_V1) +#define BITS_BCNQ1_PGBNDY_V1 \ + (BIT_MASK_BCNQ1_PGBNDY_V1 << BIT_SHIFT_BCNQ1_PGBNDY_V1) +#define BIT_CLEAR_BCNQ1_PGBNDY_V1(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1)) +#define BIT_GET_BCNQ1_PGBNDY_V1(x) \ + (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1) & BIT_MASK_BCNQ1_PGBNDY_V1) +#define BIT_SET_BCNQ1_PGBNDY_V1(x, v) \ + (BIT_CLEAR_BCNQ1_PGBNDY_V1(x) | BIT_BCNQ1_PGBNDY_V1(v)) -/* 2 REG_Q7_INFO (Offset 0x0474) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_QUEUEMACID_Q7_V1 25 -#define BIT_MASK_QUEUEMACID_Q7_V1 0x7f -#define BIT_QUEUEMACID_Q7_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1) -#define BIT_GET_QUEUEMACID_Q7_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1) +/* 2 REG_TAB_SEL (Offset 0x0456) */ +#define BIT_SHIFT_RATE_SEL 0 +#define BIT_MASK_RATE_SEL 0xf +#define BIT_RATE_SEL(x) (((x) & BIT_MASK_RATE_SEL) << BIT_SHIFT_RATE_SEL) +#define BITS_RATE_SEL (BIT_MASK_RATE_SEL << BIT_SHIFT_RATE_SEL) +#define BIT_CLEAR_RATE_SEL(x) ((x) & (~BITS_RATE_SEL)) +#define BIT_GET_RATE_SEL(x) (((x) >> BIT_SHIFT_RATE_SEL) & BIT_MASK_RATE_SEL) +#define BIT_SET_RATE_SEL(x, v) (BIT_CLEAR_RATE_SEL(x) | BIT_RATE_SEL(v)) -#define BIT_SHIFT_QUEUEAC_Q7_V1 23 -#define BIT_MASK_QUEUEAC_Q7_V1 0x3 -#define BIT_QUEUEAC_Q7_V1(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1) -#define BIT_GET_QUEUEAC_Q7_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1) +/* 2 REG_BCN_INVALID_CTRL (Offset 0x0457) */ +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P4 BIT(7) +#define BIT_EN_BCN_PKT_REL_P4 BIT(6) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P3 BIT(5) +#define BIT_EN_BCN_PKT_REL_P3 BIT(4) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P2 BIT(3) +#define BIT_EN_BCN_PKT_REL_P2 BIT(2) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P1 BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCNQ1_BDNY (Offset 0x0457) */ +#define BIT_SHIFT_BCNQ1_PGBNDY 0 +#define BIT_MASK_BCNQ1_PGBNDY 0xff +#define BIT_BCNQ1_PGBNDY(x) \ + (((x) & BIT_MASK_BCNQ1_PGBNDY) << BIT_SHIFT_BCNQ1_PGBNDY) +#define BITS_BCNQ1_PGBNDY (BIT_MASK_BCNQ1_PGBNDY << BIT_SHIFT_BCNQ1_PGBNDY) +#define BIT_CLEAR_BCNQ1_PGBNDY(x) ((x) & (~BITS_BCNQ1_PGBNDY)) +#define BIT_GET_BCNQ1_PGBNDY(x) \ + (((x) >> BIT_SHIFT_BCNQ1_PGBNDY) & BIT_MASK_BCNQ1_PGBNDY) +#define BIT_SET_BCNQ1_PGBNDY(x, v) \ + (BIT_CLEAR_BCNQ1_PGBNDY(x) | BIT_BCNQ1_PGBNDY(v)) -/* 2 REG_Q7_INFO (Offset 0x0474) */ +#endif -#define BIT_TIDEMPTY_Q7_V1 BIT(22) +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_BCN_INVALID_CTRL (Offset 0x0457) */ + +#define BIT_EN_BCN_PKT_REL_P1 BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AMPDU_MAX_LENGTH (Offset 0x0458) */ +#define BIT_SHIFT_AMPDU_MAX_LENGTH 0 +#define BIT_MASK_AMPDU_MAX_LENGTH 0xffffffffL +#define BIT_AMPDU_MAX_LENGTH(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH) +#define BITS_AMPDU_MAX_LENGTH \ + (BIT_MASK_AMPDU_MAX_LENGTH << BIT_SHIFT_AMPDU_MAX_LENGTH) +#define BIT_CLEAR_AMPDU_MAX_LENGTH(x) ((x) & (~BITS_AMPDU_MAX_LENGTH)) +#define BIT_GET_AMPDU_MAX_LENGTH(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH) +#define BIT_SET_AMPDU_MAX_LENGTH(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH(x) | BIT_AMPDU_MAX_LENGTH(v)) -/* 2 REG_Q7_INFO (Offset 0x0474) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q7_V1 15 -#define BIT_MASK_TAIL_PKT_Q7_V1 0xff -#define BIT_TAIL_PKT_Q7_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V1) << BIT_SHIFT_TAIL_PKT_Q7_V1) -#define BIT_GET_TAIL_PKT_Q7_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V1) & BIT_MASK_TAIL_PKT_Q7_V1) +/* 2 REG_AMPDU_MAX_LENGTH_HT (Offset 0x0458) */ +#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_HT 0xffff +#define BIT_AMPDU_MAX_LENGTH_HT(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT) << BIT_SHIFT_AMPDU_MAX_LENGTH_HT) +#define BITS_AMPDU_MAX_LENGTH_HT \ + (BIT_MASK_AMPDU_MAX_LENGTH_HT << BIT_SHIFT_AMPDU_MAX_LENGTH_HT) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_HT)) +#define BIT_GET_AMPDU_MAX_LENGTH_HT(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT) & BIT_MASK_AMPDU_MAX_LENGTH_HT) +#define BIT_SET_AMPDU_MAX_LENGTH_HT(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_HT(x) | BIT_AMPDU_MAX_LENGTH_HT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ACQ_STOP (Offset 0x045C) */ +#define BIT_AC7Q_STOP BIT(7) +#define BIT_AC6Q_STOP BIT(6) +#define BIT_AC5Q_STOP BIT(5) +#define BIT_AC4Q_STOP BIT(4) +#define BIT_AC3Q_STOP BIT(3) +#define BIT_AC2Q_STOP BIT(2) +#define BIT_AC1Q_STOP BIT(1) +#define BIT_AC0Q_STOP BIT(0) -/* 2 REG_Q7_INFO (Offset 0x0474) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q7_V2 11 -#define BIT_MASK_TAIL_PKT_Q7_V2 0x7ff -#define BIT_TAIL_PKT_Q7_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2) << BIT_SHIFT_TAIL_PKT_Q7_V2) -#define BIT_GET_TAIL_PKT_Q7_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2) & BIT_MASK_TAIL_PKT_Q7_V2) +/* 2 REG_WMAC_LBK_BUF_HD (Offset 0x045D) */ +#define BIT_SHIFT_WMAC_LBK_BUF_HEAD 0 +#define BIT_MASK_WMAC_LBK_BUF_HEAD 0xff +#define BIT_WMAC_LBK_BUF_HEAD(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD) << BIT_SHIFT_WMAC_LBK_BUF_HEAD) +#define BITS_WMAC_LBK_BUF_HEAD \ + (BIT_MASK_WMAC_LBK_BUF_HEAD << BIT_SHIFT_WMAC_LBK_BUF_HEAD) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD)) +#define BIT_GET_WMAC_LBK_BUF_HEAD(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD) & BIT_MASK_WMAC_LBK_BUF_HEAD) +#define BIT_SET_WMAC_LBK_BUF_HEAD(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) | BIT_WMAC_LBK_BUF_HEAD(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_Q7_INFO (Offset 0x0474) */ +/* 2 REG_NDPA_RATE (Offset 0x045D) */ +#define BIT_SHIFT_R_NDPA_RATE_V1 0 +#define BIT_MASK_R_NDPA_RATE_V1 0xff +#define BIT_R_NDPA_RATE_V1(x) \ + (((x) & BIT_MASK_R_NDPA_RATE_V1) << BIT_SHIFT_R_NDPA_RATE_V1) +#define BITS_R_NDPA_RATE_V1 \ + (BIT_MASK_R_NDPA_RATE_V1 << BIT_SHIFT_R_NDPA_RATE_V1) +#define BIT_CLEAR_R_NDPA_RATE_V1(x) ((x) & (~BITS_R_NDPA_RATE_V1)) +#define BIT_GET_R_NDPA_RATE_V1(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE_V1) & BIT_MASK_R_NDPA_RATE_V1) +#define BIT_SET_R_NDPA_RATE_V1(x, v) \ + (BIT_CLEAR_R_NDPA_RATE_V1(x) | BIT_R_NDPA_RATE_V1(v)) -#define BIT_SHIFT_PKT_NUM_Q7_V1 8 -#define BIT_MASK_PKT_NUM_Q7_V1 0x7f -#define BIT_PKT_NUM_Q7_V1(x) (((x) & BIT_MASK_PKT_NUM_Q7_V1) << BIT_SHIFT_PKT_NUM_Q7_V1) -#define BIT_GET_PKT_NUM_Q7_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q7_V1) & BIT_MASK_PKT_NUM_Q7_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q7 0 -#define BIT_MASK_HEAD_PKT_Q7 0xff -#define BIT_HEAD_PKT_Q7(x) (((x) & BIT_MASK_HEAD_PKT_Q7) << BIT_SHIFT_HEAD_PKT_Q7) -#define BIT_GET_HEAD_PKT_Q7(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7) & BIT_MASK_HEAD_PKT_Q7) +/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +#define BIT_R_EN_GNT_BT_AWAKE BIT(3) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +#define BIT_EN_GNT_BT_AWAKE BIT(3) -/* 2 REG_Q7_INFO (Offset 0x0474) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q7_V1 0 -#define BIT_MASK_HEAD_PKT_Q7_V1 0x7ff -#define BIT_HEAD_PKT_Q7_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1) << BIT_SHIFT_HEAD_PKT_Q7_V1) -#define BIT_GET_HEAD_PKT_Q7_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1) & BIT_MASK_HEAD_PKT_Q7_V1) +/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +#define BIT_EN_EOF_V1 BIT(2) -/* 2 REG_WMAC_LBK_BUF_HD_V1 (Offset 0x0478) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1 0 -#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1 0xfff -#define BIT_WMAC_LBK_BUF_HEAD_V1(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) -#define BIT_GET_WMAC_LBK_BUF_HEAD_V1(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1) +/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +#define BIT_DIS_OQT_BLOCK BIT(1) +#define BIT_SEARCH_QUEUE_EN BIT(0) -/* 2 REG_MGQ_BDNY_V1 (Offset 0x047A) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MGQ_PGBNDY_V1 0 -#define BIT_MASK_MGQ_PGBNDY_V1 0xfff -#define BIT_MGQ_PGBNDY_V1(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1) << BIT_SHIFT_MGQ_PGBNDY_V1) -#define BIT_GET_MGQ_PGBNDY_V1(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1) & BIT_MASK_MGQ_PGBNDY_V1) +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#define BIT_R_DIS_MACID_RELEASE_RTY BIT(5) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#define BIT_DIS_MACID_RELEASE_RTY BIT(5) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SPC_READ_PTR 24 -#define BIT_MASK_SPC_READ_PTR 0xf -#define BIT_SPC_READ_PTR(x) (((x) & BIT_MASK_SPC_READ_PTR) << BIT_SHIFT_SPC_READ_PTR) -#define BIT_GET_SPC_READ_PTR(x) (((x) >> BIT_SHIFT_SPC_READ_PTR) & BIT_MASK_SPC_READ_PTR) +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#define BIT_SHIFT_BW_SIGTA 3 +#define BIT_MASK_BW_SIGTA 0x3 +#define BIT_BW_SIGTA(x) (((x) & BIT_MASK_BW_SIGTA) << BIT_SHIFT_BW_SIGTA) +#define BITS_BW_SIGTA (BIT_MASK_BW_SIGTA << BIT_SHIFT_BW_SIGTA) +#define BIT_CLEAR_BW_SIGTA(x) ((x) & (~BITS_BW_SIGTA)) +#define BIT_GET_BW_SIGTA(x) (((x) >> BIT_SHIFT_BW_SIGTA) & BIT_MASK_BW_SIGTA) +#define BIT_SET_BW_SIGTA(x, v) (BIT_CLEAR_BW_SIGTA(x) | BIT_BW_SIGTA(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#define BIT_SHIFT_R_NDPA_RATE 2 +#define BIT_MASK_R_NDPA_RATE 0x3f +#define BIT_R_NDPA_RATE(x) \ + (((x) & BIT_MASK_R_NDPA_RATE) << BIT_SHIFT_R_NDPA_RATE) +#define BITS_R_NDPA_RATE (BIT_MASK_R_NDPA_RATE << BIT_SHIFT_R_NDPA_RATE) +#define BIT_CLEAR_R_NDPA_RATE(x) ((x) & (~BITS_R_NDPA_RATE)) +#define BIT_GET_R_NDPA_RATE(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE) & BIT_MASK_R_NDPA_RATE) +#define BIT_SET_R_NDPA_RATE(x, v) \ + (BIT_CLEAR_R_NDPA_RATE(x) | BIT_R_NDPA_RATE(v)) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TRXRPT_TIMER_TH 24 -#define BIT_MASK_TRXRPT_TIMER_TH 0xff -#define BIT_TRXRPT_TIMER_TH(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH) << BIT_SHIFT_TRXRPT_TIMER_TH) -#define BIT_GET_TRXRPT_TIMER_TH(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH) & BIT_MASK_TRXRPT_TIMER_TH) +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#define BIT_EN_BAR_SIGTA BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#define BIT_SHIFT_R_NDPA_BW 0 +#define BIT_MASK_R_NDPA_BW 0x3 +#define BIT_R_NDPA_BW(x) (((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW) +#define BITS_R_NDPA_BW (BIT_MASK_R_NDPA_BW << BIT_SHIFT_R_NDPA_BW) +#define BIT_CLEAR_R_NDPA_BW(x) ((x) & (~BITS_R_NDPA_BW)) +#define BIT_GET_R_NDPA_BW(x) (((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW) +#define BIT_SET_R_NDPA_BW(x, v) (BIT_CLEAR_R_NDPA_BW(x) | BIT_R_NDPA_BW(v)) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_SPC_WRITE_PTR 16 -#define BIT_MASK_SPC_WRITE_PTR 0xf -#define BIT_SPC_WRITE_PTR(x) (((x) & BIT_MASK_SPC_WRITE_PTR) << BIT_SHIFT_SPC_WRITE_PTR) -#define BIT_GET_SPC_WRITE_PTR(x) (((x) >> BIT_SHIFT_SPC_WRITE_PTR) & BIT_MASK_SPC_WRITE_PTR) +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#define BIT_SHIFT_NDPA_BW 0 +#define BIT_MASK_NDPA_BW 0x3 +#define BIT_NDPA_BW(x) (((x) & BIT_MASK_NDPA_BW) << BIT_SHIFT_NDPA_BW) +#define BITS_NDPA_BW (BIT_MASK_NDPA_BW << BIT_SHIFT_NDPA_BW) +#define BIT_CLEAR_NDPA_BW(x) ((x) & (~BITS_NDPA_BW)) +#define BIT_GET_NDPA_BW(x) (((x) >> BIT_SHIFT_NDPA_BW) & BIT_MASK_NDPA_BW) +#define BIT_SET_NDPA_BW(x, v) (BIT_CLEAR_NDPA_BW(x) | BIT_NDPA_BW(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FAST_EDCA_CTRL (Offset 0x0460) */ +#define BIT_SHIFT_FAST_EDCA_TO_V1 16 +#define BIT_MASK_FAST_EDCA_TO_V1 0xff +#define BIT_FAST_EDCA_TO_V1(x) \ + (((x) & BIT_MASK_FAST_EDCA_TO_V1) << BIT_SHIFT_FAST_EDCA_TO_V1) +#define BITS_FAST_EDCA_TO_V1 \ + (BIT_MASK_FAST_EDCA_TO_V1 << BIT_SHIFT_FAST_EDCA_TO_V1) +#define BIT_CLEAR_FAST_EDCA_TO_V1(x) ((x) & (~BITS_FAST_EDCA_TO_V1)) +#define BIT_GET_FAST_EDCA_TO_V1(x) \ + (((x) >> BIT_SHIFT_FAST_EDCA_TO_V1) & BIT_MASK_FAST_EDCA_TO_V1) +#define BIT_SET_FAST_EDCA_TO_V1(x, v) \ + (BIT_CLEAR_FAST_EDCA_TO_V1(x) | BIT_FAST_EDCA_TO_V1(v)) + +#define BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH 12 +#define BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH 0xf +#define BIT_AC3_AC7_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH) \ + << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) +#define BITS_AC3_AC7_FAST_EDCA_PKT_TH \ + (BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH \ + << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_AC3_AC7_FAST_EDCA_PKT_TH(x) \ + ((x) & (~BITS_AC3_AC7_FAST_EDCA_PKT_TH)) +#define BIT_GET_AC3_AC7_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) & \ + BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH) +#define BIT_SET_AC3_AC7_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_AC3_AC7_FAST_EDCA_PKT_TH(x) | \ + BIT_AC3_AC7_FAST_EDCA_PKT_TH(v)) + +#define BIT_SHIFT_AC2_FAST_EDCA_PKT_TH 8 +#define BIT_MASK_AC2_FAST_EDCA_PKT_TH 0xf +#define BIT_AC2_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_AC2_FAST_EDCA_PKT_TH) \ + << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) +#define BITS_AC2_FAST_EDCA_PKT_TH \ + (BIT_MASK_AC2_FAST_EDCA_PKT_TH << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_AC2_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC2_FAST_EDCA_PKT_TH)) +#define BIT_GET_AC2_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) & \ + BIT_MASK_AC2_FAST_EDCA_PKT_TH) +#define BIT_SET_AC2_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_AC2_FAST_EDCA_PKT_TH(x) | BIT_AC2_FAST_EDCA_PKT_TH(v)) + +#define BIT_SHIFT_AC1_FAST_EDCA_PKT_TH 4 +#define BIT_MASK_AC1_FAST_EDCA_PKT_TH 0xf +#define BIT_AC1_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_AC1_FAST_EDCA_PKT_TH) \ + << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) +#define BITS_AC1_FAST_EDCA_PKT_TH \ + (BIT_MASK_AC1_FAST_EDCA_PKT_TH << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_AC1_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC1_FAST_EDCA_PKT_TH)) +#define BIT_GET_AC1_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) & \ + BIT_MASK_AC1_FAST_EDCA_PKT_TH) +#define BIT_SET_AC1_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_AC1_FAST_EDCA_PKT_TH(x) | BIT_AC1_FAST_EDCA_PKT_TH(v)) + +#define BIT_SHIFT_AC0_FAST_EDCA_PKT_TH 0 +#define BIT_MASK_AC0_FAST_EDCA_PKT_TH 0xf +#define BIT_AC0_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_AC0_FAST_EDCA_PKT_TH) \ + << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) +#define BITS_AC0_FAST_EDCA_PKT_TH \ + (BIT_MASK_AC0_FAST_EDCA_PKT_TH << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_AC0_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC0_FAST_EDCA_PKT_TH)) +#define BIT_GET_AC0_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) & \ + BIT_MASK_AC0_FAST_EDCA_PKT_TH) +#define BIT_SET_AC0_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_AC0_FAST_EDCA_PKT_TH(x) | BIT_AC0_FAST_EDCA_PKT_TH(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_AMPDU_MAX_LENGTH_VHT (Offset 0x0460) */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_VHT 0x3ffff +#define BIT_AMPDU_MAX_LENGTH_VHT(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT) +#define BITS_AMPDU_MAX_LENGTH_VHT \ + (BIT_MASK_AMPDU_MAX_LENGTH_VHT << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT)) +#define BIT_GET_AMPDU_MAX_LENGTH_VHT(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT) & \ + BIT_MASK_AMPDU_MAX_LENGTH_VHT) +#define BIT_SET_AMPDU_MAX_LENGTH_VHT(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT(x) | BIT_AMPDU_MAX_LENGTH_VHT(v)) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_AMPDU_MAX_LENGTH_VHT (Offset 0x0460) */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1 0xfffff +#define BIT_AMPDU_MAX_LENGTH_VHT_V1(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1) +#define BITS_AMPDU_MAX_LENGTH_VHT_V1 \ + (BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1 << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_V1)) +#define BIT_GET_AMPDU_MAX_LENGTH_VHT_V1(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1) & \ + BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1) +#define BIT_SET_AMPDU_MAX_LENGTH_VHT_V1(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1(x) | BIT_AMPDU_MAX_LENGTH_VHT_V1(v)) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TRXRPT_LEN_TH 16 -#define BIT_MASK_TRXRPT_LEN_TH 0xff -#define BIT_TRXRPT_LEN_TH(x) (((x) & BIT_MASK_TRXRPT_LEN_TH) << BIT_SHIFT_TRXRPT_LEN_TH) -#define BIT_GET_TRXRPT_LEN_TH(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH) & BIT_MASK_TRXRPT_LEN_TH) +/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ +#define BIT_SHIFT_RD_RESP_PKT_TH 0 +#define BIT_MASK_RD_RESP_PKT_TH 0x1f +#define BIT_RD_RESP_PKT_TH(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH) << BIT_SHIFT_RD_RESP_PKT_TH) +#define BITS_RD_RESP_PKT_TH \ + (BIT_MASK_RD_RESP_PKT_TH << BIT_SHIFT_RD_RESP_PKT_TH) +#define BIT_CLEAR_RD_RESP_PKT_TH(x) ((x) & (~BITS_RD_RESP_PKT_TH)) +#define BIT_GET_RD_RESP_PKT_TH(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH) & BIT_MASK_RD_RESP_PKT_TH) +#define BIT_SET_RD_RESP_PKT_TH(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH(x) | BIT_RD_RESP_PKT_TH(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ +#define BIT_SHIFT_RD_RESP_PKT_TH_V1 0 +#define BIT_MASK_RD_RESP_PKT_TH_V1 0x3f +#define BIT_RD_RESP_PKT_TH_V1(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH_V1) << BIT_SHIFT_RD_RESP_PKT_TH_V1) +#define BITS_RD_RESP_PKT_TH_V1 \ + (BIT_MASK_RD_RESP_PKT_TH_V1 << BIT_SHIFT_RD_RESP_PKT_TH_V1) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1(x) ((x) & (~BITS_RD_RESP_PKT_TH_V1)) +#define BIT_GET_RD_RESP_PKT_TH_V1(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1) & BIT_MASK_RD_RESP_PKT_TH_V1) +#define BIT_SET_RD_RESP_PKT_TH_V1(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH_V1(x) | BIT_RD_RESP_PKT_TH_V1(v)) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AC_READ_PTR 8 -#define BIT_MASK_AC_READ_PTR 0xf -#define BIT_AC_READ_PTR(x) (((x) & BIT_MASK_AC_READ_PTR) << BIT_SHIFT_AC_READ_PTR) -#define BIT_GET_AC_READ_PTR(x) (((x) >> BIT_SHIFT_AC_READ_PTR) & BIT_MASK_AC_READ_PTR) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_QUEUEMACID_CMDQ_V1 25 +#define BIT_MASK_QUEUEMACID_CMDQ_V1 0x7f +#define BIT_QUEUEMACID_CMDQ_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1) << BIT_SHIFT_QUEUEMACID_CMDQ_V1) +#define BITS_QUEUEMACID_CMDQ_V1 \ + (BIT_MASK_QUEUEMACID_CMDQ_V1 << BIT_SHIFT_QUEUEMACID_CMDQ_V1) +#define BIT_CLEAR_QUEUEMACID_CMDQ_V1(x) ((x) & (~BITS_QUEUEMACID_CMDQ_V1)) +#define BIT_GET_QUEUEMACID_CMDQ_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1) & BIT_MASK_QUEUEMACID_CMDQ_V1) +#define BIT_SET_QUEUEMACID_CMDQ_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_CMDQ_V1(x) | BIT_QUEUEMACID_CMDQ_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_PKT_NUM_CMDQ_V2 24 +#define BIT_MASK_PKT_NUM_CMDQ_V2 0xff +#define BIT_PKT_NUM_CMDQ_V2(x) \ + (((x) & BIT_MASK_PKT_NUM_CMDQ_V2) << BIT_SHIFT_PKT_NUM_CMDQ_V2) +#define BITS_PKT_NUM_CMDQ_V2 \ + (BIT_MASK_PKT_NUM_CMDQ_V2 << BIT_SHIFT_PKT_NUM_CMDQ_V2) +#define BIT_CLEAR_PKT_NUM_CMDQ_V2(x) ((x) & (~BITS_PKT_NUM_CMDQ_V2)) +#define BIT_GET_PKT_NUM_CMDQ_V2(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_CMDQ_V2) & BIT_MASK_PKT_NUM_CMDQ_V2) +#define BIT_SET_PKT_NUM_CMDQ_V2(x, v) \ + (BIT_CLEAR_PKT_NUM_CMDQ_V2(x) | BIT_PKT_NUM_CMDQ_V2(v)) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8197F_SUPPORT) -#define BIT_SHIFT_TRXRPT_READ_PTR 8 -#define BIT_MASK_TRXRPT_READ_PTR 0xff -#define BIT_TRXRPT_READ_PTR(x) (((x) & BIT_MASK_TRXRPT_READ_PTR) << BIT_SHIFT_TRXRPT_READ_PTR) -#define BIT_GET_TRXRPT_READ_PTR(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR) & BIT_MASK_TRXRPT_READ_PTR) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_PKT_NUM 23 +#define BIT_MASK_PKT_NUM 0x1ff +#define BIT_PKT_NUM(x) (((x) & BIT_MASK_PKT_NUM) << BIT_SHIFT_PKT_NUM) +#define BITS_PKT_NUM (BIT_MASK_PKT_NUM << BIT_SHIFT_PKT_NUM) +#define BIT_CLEAR_PKT_NUM(x) ((x) & (~BITS_PKT_NUM)) +#define BIT_GET_PKT_NUM(x) (((x) >> BIT_SHIFT_PKT_NUM) & BIT_MASK_PKT_NUM) +#define BIT_SET_PKT_NUM(x, v) (BIT_CLEAR_PKT_NUM(x) | BIT_PKT_NUM(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_QUEUEAC_CMDQ_V1 23 +#define BIT_MASK_QUEUEAC_CMDQ_V1 0x3 +#define BIT_QUEUEAC_CMDQ_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_CMDQ_V1) << BIT_SHIFT_QUEUEAC_CMDQ_V1) +#define BITS_QUEUEAC_CMDQ_V1 \ + (BIT_MASK_QUEUEAC_CMDQ_V1 << BIT_SHIFT_QUEUEAC_CMDQ_V1) +#define BIT_CLEAR_QUEUEAC_CMDQ_V1(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1)) +#define BIT_GET_QUEUEAC_CMDQ_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1) & BIT_MASK_QUEUEAC_CMDQ_V1) +#define BIT_SET_QUEUEAC_CMDQ_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_CMDQ_V1(x) | BIT_QUEUEAC_CMDQ_V1(v)) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AC_WRITE_PTR 0 -#define BIT_MASK_AC_WRITE_PTR 0xf -#define BIT_AC_WRITE_PTR(x) (((x) & BIT_MASK_AC_WRITE_PTR) << BIT_SHIFT_AC_WRITE_PTR) -#define BIT_GET_AC_WRITE_PTR(x) (((x) >> BIT_SHIFT_AC_WRITE_PTR) & BIT_MASK_AC_WRITE_PTR) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_TIDEMPTY_CMDQ_V1 BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_TAIL_PKT_CMDQ 16 +#define BIT_MASK_TAIL_PKT_CMDQ 0xff +#define BIT_TAIL_PKT_CMDQ(x) \ + (((x) & BIT_MASK_TAIL_PKT_CMDQ) << BIT_SHIFT_TAIL_PKT_CMDQ) +#define BITS_TAIL_PKT_CMDQ (BIT_MASK_TAIL_PKT_CMDQ << BIT_SHIFT_TAIL_PKT_CMDQ) +#define BIT_CLEAR_TAIL_PKT_CMDQ(x) ((x) & (~BITS_TAIL_PKT_CMDQ)) +#define BIT_GET_TAIL_PKT_CMDQ(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ) & BIT_MASK_TAIL_PKT_CMDQ) +#define BIT_SET_TAIL_PKT_CMDQ(x, v) \ + (BIT_CLEAR_TAIL_PKT_CMDQ(x) | BIT_TAIL_PKT_CMDQ(v)) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_TRXRPT_WRITE_PTR 0 -#define BIT_MASK_TRXRPT_WRITE_PTR 0xff -#define BIT_TRXRPT_WRITE_PTR(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR) << BIT_SHIFT_TRXRPT_WRITE_PTR) -#define BIT_GET_TRXRPT_WRITE_PTR(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR) & BIT_MASK_TRXRPT_WRITE_PTR) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_TAIL_PKT_CMDQ_V2 11 +#define BIT_MASK_TAIL_PKT_CMDQ_V2 0x7ff +#define BIT_TAIL_PKT_CMDQ_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2) << BIT_SHIFT_TAIL_PKT_CMDQ_V2) +#define BITS_TAIL_PKT_CMDQ_V2 \ + (BIT_MASK_TAIL_PKT_CMDQ_V2 << BIT_SHIFT_TAIL_PKT_CMDQ_V2) +#define BIT_CLEAR_TAIL_PKT_CMDQ_V2(x) ((x) & (~BITS_TAIL_PKT_CMDQ_V2)) +#define BIT_GET_TAIL_PKT_CMDQ_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2) & BIT_MASK_TAIL_PKT_CMDQ_V2) +#define BIT_SET_TAIL_PKT_CMDQ_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_CMDQ_V2(x) | BIT_TAIL_PKT_CMDQ_V2(v)) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_NEW_EDCA_CTRL_V1 (Offset 0x0464) */ +#define BIT_SHIFT_RANDOM_VALUE_SHIFT 9 +#define BIT_MASK_RANDOM_VALUE_SHIFT 0x7 +#define BIT_RANDOM_VALUE_SHIFT(x) \ + (((x) & BIT_MASK_RANDOM_VALUE_SHIFT) << BIT_SHIFT_RANDOM_VALUE_SHIFT) +#define BITS_RANDOM_VALUE_SHIFT \ + (BIT_MASK_RANDOM_VALUE_SHIFT << BIT_SHIFT_RANDOM_VALUE_SHIFT) +#define BIT_CLEAR_RANDOM_VALUE_SHIFT(x) ((x) & (~BITS_RANDOM_VALUE_SHIFT)) +#define BIT_GET_RANDOM_VALUE_SHIFT(x) \ + (((x) >> BIT_SHIFT_RANDOM_VALUE_SHIFT) & BIT_MASK_RANDOM_VALUE_SHIFT) +#define BIT_SET_RANDOM_VALUE_SHIFT(x, v) \ + (BIT_CLEAR_RANDOM_VALUE_SHIFT(x) | BIT_RANDOM_VALUE_SHIFT(v)) -/* 2 REG_INIRTS_RATE_SEL (Offset 0x0480) */ +#endif -#define BIT_LEAG_RTS_BW_DUP BIT(5) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BASIC_CFEND_RATE (Offset 0x0481) */ +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_PKT_NUM_CMDQ 8 +#define BIT_MASK_PKT_NUM_CMDQ 0xff +#define BIT_PKT_NUM_CMDQ(x) \ + (((x) & BIT_MASK_PKT_NUM_CMDQ) << BIT_SHIFT_PKT_NUM_CMDQ) +#define BITS_PKT_NUM_CMDQ (BIT_MASK_PKT_NUM_CMDQ << BIT_SHIFT_PKT_NUM_CMDQ) +#define BIT_CLEAR_PKT_NUM_CMDQ(x) ((x) & (~BITS_PKT_NUM_CMDQ)) +#define BIT_GET_PKT_NUM_CMDQ(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_CMDQ) & BIT_MASK_PKT_NUM_CMDQ) +#define BIT_SET_PKT_NUM_CMDQ(x, v) \ + (BIT_CLEAR_PKT_NUM_CMDQ(x) | BIT_PKT_NUM_CMDQ(v)) -#define BIT_SHIFT_BASIC_CFEND_RATE 0 -#define BIT_MASK_BASIC_CFEND_RATE 0x1f -#define BIT_BASIC_CFEND_RATE(x) (((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE) -#define BIT_GET_BASIC_CFEND_RATE(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE) +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -/* 2 REG_STBC_CFEND_RATE (Offset 0x0482) */ +/* 2 REG_NEW_EDCA_CTRL_V1 (Offset 0x0464) */ +#define BIT_ENABLE_NEW_EDCA BIT(8) -#define BIT_SHIFT_STBC_CFEND_RATE 0 -#define BIT_MASK_STBC_CFEND_RATE 0x1f -#define BIT_STBC_CFEND_RATE(x) (((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE) -#define BIT_GET_STBC_CFEND_RATE(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DATA_SC (Offset 0x0483) */ +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_HEAD_PKT_CMDQ 0 +#define BIT_MASK_HEAD_PKT_CMDQ 0xff +#define BIT_HEAD_PKT_CMDQ(x) \ + (((x) & BIT_MASK_HEAD_PKT_CMDQ) << BIT_SHIFT_HEAD_PKT_CMDQ) +#define BITS_HEAD_PKT_CMDQ (BIT_MASK_HEAD_PKT_CMDQ << BIT_SHIFT_HEAD_PKT_CMDQ) +#define BIT_CLEAR_HEAD_PKT_CMDQ(x) ((x) & (~BITS_HEAD_PKT_CMDQ)) +#define BIT_GET_HEAD_PKT_CMDQ(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ) & BIT_MASK_HEAD_PKT_CMDQ) +#define BIT_SET_HEAD_PKT_CMDQ(x, v) \ + (BIT_CLEAR_HEAD_PKT_CMDQ(x) | BIT_HEAD_PKT_CMDQ(v)) -#define BIT_SHIFT_TXSC_40M 4 -#define BIT_MASK_TXSC_40M 0xf -#define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) -#define BIT_GET_TXSC_40M(x) (((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TXSC_20M 0 -#define BIT_MASK_TXSC_20M 0xf -#define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) -#define BIT_GET_TXSC_20M(x) (((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_HEAD_PKT_CMDQ_V1 0 +#define BIT_MASK_HEAD_PKT_CMDQ_V1 0x7ff +#define BIT_HEAD_PKT_CMDQ_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1) << BIT_SHIFT_HEAD_PKT_CMDQ_V1) +#define BITS_HEAD_PKT_CMDQ_V1 \ + (BIT_MASK_HEAD_PKT_CMDQ_V1 << BIT_SHIFT_HEAD_PKT_CMDQ_V1) +#define BIT_CLEAR_HEAD_PKT_CMDQ_V1(x) ((x) & (~BITS_HEAD_PKT_CMDQ_V1)) +#define BIT_GET_HEAD_PKT_CMDQ_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1) & BIT_MASK_HEAD_PKT_CMDQ_V1) +#define BIT_SET_HEAD_PKT_CMDQ_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_CMDQ_V1(x) | BIT_HEAD_PKT_CMDQ_V1(v)) -/* 2 REG_MACID_SLEEP3 (Offset 0x0484) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_MACID127_96_PKTSLEEP 0 -#define BIT_MASK_MACID127_96_PKTSLEEP 0xffffffffL -#define BIT_MACID127_96_PKTSLEEP(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP) << BIT_SHIFT_MACID127_96_PKTSLEEP) -#define BIT_GET_MACID127_96_PKTSLEEP(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) & BIT_MASK_MACID127_96_PKTSLEEP) +/* 2 REG_NEW_EDCA_CTRL_V1 (Offset 0x0464) */ +#define BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER 0 +#define BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER 0xff +#define BIT_MEDIUM_HAS_IDKE_TRIGGER(x) \ + (((x) & BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER) \ + << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER) +#define BITS_MEDIUM_HAS_IDKE_TRIGGER \ + (BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER) +#define BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER(x) \ + ((x) & (~BITS_MEDIUM_HAS_IDKE_TRIGGER)) +#define BIT_GET_MEDIUM_HAS_IDKE_TRIGGER(x) \ + (((x) >> BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER) & \ + BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER) +#define BIT_SET_MEDIUM_HAS_IDKE_TRIGGER(x, v) \ + (BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER(x) | BIT_MEDIUM_HAS_IDKE_TRIGGER(v)) -/* 2 REG_MACID_SLEEP1 (Offset 0x0488) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MACID63_32_PKTSLEEP 0 -#define BIT_MASK_MACID63_32_PKTSLEEP 0xffffffffL -#define BIT_MACID63_32_PKTSLEEP(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP) -#define BIT_GET_MACID63_32_PKTSLEEP(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP) +/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_SHIFT_QUEUEMACID_Q4_V1 25 +#define BIT_MASK_QUEUEMACID_Q4_V1 0x7f +#define BIT_QUEUEMACID_Q4_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1) +#define BITS_QUEUEMACID_Q4_V1 \ + (BIT_MASK_QUEUEMACID_Q4_V1 << BIT_SHIFT_QUEUEMACID_Q4_V1) +#define BIT_CLEAR_QUEUEMACID_Q4_V1(x) ((x) & (~BITS_QUEUEMACID_Q4_V1)) +#define BIT_GET_QUEUEMACID_Q4_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1) +#define BIT_SET_QUEUEMACID_Q4_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q4_V1(x) | BIT_QUEUEMACID_Q4_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q4_V1 23 +#define BIT_MASK_QUEUEAC_Q4_V1 0x3 +#define BIT_QUEUEAC_Q4_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1) +#define BITS_QUEUEAC_Q4_V1 (BIT_MASK_QUEUEAC_Q4_V1 << BIT_SHIFT_QUEUEAC_Q4_V1) +#define BIT_CLEAR_QUEUEAC_Q4_V1(x) ((x) & (~BITS_QUEUEAC_Q4_V1)) +#define BIT_GET_QUEUEAC_Q4_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1) +#define BIT_SET_QUEUEAC_Q4_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q4_V1(x) | BIT_QUEUEAC_Q4_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_ARFR2_V1 (Offset 0x048C) */ +/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_TIDEMPTY_Q4_V1 BIT(22) -#define BIT_SHIFT_ARFR2_V1 0 -#define BIT_MASK_ARFR2_V1 0xffffffffffffffffL -#define BIT_ARFR2_V1(x) (((x) & BIT_MASK_ARFR2_V1) << BIT_SHIFT_ARFR2_V1) -#define BIT_GET_ARFR2_V1(x) (((x) >> BIT_SHIFT_ARFR2_V1) & BIT_MASK_ARFR2_V1) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_ARFR3_V1 (Offset 0x0494) */ +/* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */ +#define BIT_AC19Q_STOP BIT(19) +#define BIT_AC18Q_STOP BIT(18) +#define BIT_AC17Q_STOP BIT(17) +#define BIT_AC16Q_STOP BIT(16) -#define BIT_SHIFT_ARFR3_V1 0 -#define BIT_MASK_ARFR3_V1 0xffffffffffffffffL -#define BIT_ARFR3_V1(x) (((x) & BIT_MASK_ARFR3_V1) << BIT_SHIFT_ARFR3_V1) -#define BIT_GET_ARFR3_V1(x) (((x) >> BIT_SHIFT_ARFR3_V1) & BIT_MASK_ARFR3_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_ARFR4 (Offset 0x049C) */ +/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_SHIFT_TAIL_PKT_Q4_V1 15 +#define BIT_MASK_TAIL_PKT_Q4_V1 0xff +#define BIT_TAIL_PKT_Q4_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V1) << BIT_SHIFT_TAIL_PKT_Q4_V1) +#define BITS_TAIL_PKT_Q4_V1 \ + (BIT_MASK_TAIL_PKT_Q4_V1 << BIT_SHIFT_TAIL_PKT_Q4_V1) +#define BIT_CLEAR_TAIL_PKT_Q4_V1(x) ((x) & (~BITS_TAIL_PKT_Q4_V1)) +#define BIT_GET_TAIL_PKT_Q4_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V1) & BIT_MASK_TAIL_PKT_Q4_V1) +#define BIT_SET_TAIL_PKT_Q4_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V1(x) | BIT_TAIL_PKT_Q4_V1(v)) -#define BIT_SHIFT_ARFR4 0 -#define BIT_MASK_ARFR4 0xffffffffffffffffL -#define BIT_ARFR4(x) (((x) & BIT_MASK_ARFR4) << BIT_SHIFT_ARFR4) -#define BIT_GET_ARFR4(x) (((x) >> BIT_SHIFT_ARFR4) & BIT_MASK_ARFR4) +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -/* 2 REG_ARFR5 (Offset 0x04A4) */ +/* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */ +#define BIT_AC15Q_STOP BIT(15) +#define BIT_AC14Q_STOP BIT(14) +#define BIT_AC13Q_STOP BIT(13) +#define BIT_AC12Q_STOP BIT(12) -#define BIT_SHIFT_ARFR5 0 -#define BIT_MASK_ARFR5 0xffffffffffffffffL -#define BIT_ARFR5(x) (((x) & BIT_MASK_ARFR5) << BIT_SHIFT_ARFR5) -#define BIT_GET_ARFR5(x) (((x) >> BIT_SHIFT_ARFR5) & BIT_MASK_ARFR5) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_SHIFT_TAIL_PKT_Q4_V2 11 +#define BIT_MASK_TAIL_PKT_Q4_V2 0x7ff +#define BIT_TAIL_PKT_Q4_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2) << BIT_SHIFT_TAIL_PKT_Q4_V2) +#define BITS_TAIL_PKT_Q4_V2 \ + (BIT_MASK_TAIL_PKT_Q4_V2 << BIT_SHIFT_TAIL_PKT_Q4_V2) +#define BIT_CLEAR_TAIL_PKT_Q4_V2(x) ((x) & (~BITS_TAIL_PKT_Q4_V2)) +#define BIT_GET_TAIL_PKT_Q4_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2) & BIT_MASK_TAIL_PKT_Q4_V2) +#define BIT_SET_TAIL_PKT_Q4_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2(x) | BIT_TAIL_PKT_Q4_V2(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +/* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */ -#define BIT_SHCUT_PARSE_DASA BIT(25) +#define BIT_AC11Q_STOP BIT(11) +#define BIT_AC10Q_STOP BIT(10) +#define BIT_AC9Q_STOP BIT(9) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q4_INFO (Offset 0x0468) */ -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_PKT_NUM_Q4_V1 8 +#define BIT_MASK_PKT_NUM_Q4_V1 0x7f +#define BIT_PKT_NUM_Q4_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q4_V1) << BIT_SHIFT_PKT_NUM_Q4_V1) +#define BITS_PKT_NUM_Q4_V1 (BIT_MASK_PKT_NUM_Q4_V1 << BIT_SHIFT_PKT_NUM_Q4_V1) +#define BIT_CLEAR_PKT_NUM_Q4_V1(x) ((x) & (~BITS_PKT_NUM_Q4_V1)) +#define BIT_GET_PKT_NUM_Q4_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q4_V1) & BIT_MASK_PKT_NUM_Q4_V1) +#define BIT_SET_PKT_NUM_Q4_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q4_V1(x) | BIT_PKT_NUM_Q4_V1(v)) + +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_LOC_AMPDU_BURST_CTRL 24 -#define BIT_MASK_LOC_AMPDU_BURST_CTRL 0xff -#define BIT_LOC_AMPDU_BURST_CTRL(x) (((x) & BIT_MASK_LOC_AMPDU_BURST_CTRL) << BIT_SHIFT_LOC_AMPDU_BURST_CTRL) -#define BIT_GET_LOC_AMPDU_BURST_CTRL(x) (((x) >> BIT_SHIFT_LOC_AMPDU_BURST_CTRL) & BIT_MASK_LOC_AMPDU_BURST_CTRL) +/* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */ +#define BIT_AC8Q_STOP BIT(8) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_SHIFT_HEAD_PKT_Q4 0 +#define BIT_MASK_HEAD_PKT_Q4 0xff +#define BIT_HEAD_PKT_Q4(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q4) << BIT_SHIFT_HEAD_PKT_Q4) +#define BITS_HEAD_PKT_Q4 (BIT_MASK_HEAD_PKT_Q4 << BIT_SHIFT_HEAD_PKT_Q4) +#define BIT_CLEAR_HEAD_PKT_Q4(x) ((x) & (~BITS_HEAD_PKT_Q4)) +#define BIT_GET_HEAD_PKT_Q4(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q4) & BIT_MASK_HEAD_PKT_Q4) +#define BIT_SET_HEAD_PKT_Q4(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q4(x) | BIT_HEAD_PKT_Q4(v)) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif -#define BIT_SHCUT_BYPASS BIT(24) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_SHIFT_HEAD_PKT_Q4_V1 0 +#define BIT_MASK_HEAD_PKT_Q4_V1 0x7ff +#define BIT_HEAD_PKT_Q4_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q4_V1) << BIT_SHIFT_HEAD_PKT_Q4_V1) +#define BITS_HEAD_PKT_Q4_V1 \ + (BIT_MASK_HEAD_PKT_Q4_V1 << BIT_SHIFT_HEAD_PKT_Q4_V1) +#define BIT_CLEAR_HEAD_PKT_Q4_V1(x) ((x) & (~BITS_HEAD_PKT_Q4_V1)) +#define BIT_GET_HEAD_PKT_Q4_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1) & BIT_MASK_HEAD_PKT_Q4_V1) +#define BIT_SET_HEAD_PKT_Q4_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q4_V1(x) | BIT_HEAD_PKT_Q4_V1(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +/* 2 REG_Q5_INFO (Offset 0x046C) */ +#define BIT_SHIFT_QUEUEMACID_Q5_V1 25 +#define BIT_MASK_QUEUEMACID_Q5_V1 0x7f +#define BIT_QUEUEMACID_Q5_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1) +#define BITS_QUEUEMACID_Q5_V1 \ + (BIT_MASK_QUEUEMACID_Q5_V1 << BIT_SHIFT_QUEUEMACID_Q5_V1) +#define BIT_CLEAR_QUEUEMACID_Q5_V1(x) ((x) & (~BITS_QUEUEMACID_Q5_V1)) +#define BIT_GET_QUEUEMACID_Q5_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1) +#define BIT_SET_QUEUEMACID_Q5_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q5_V1(x) | BIT_QUEUEMACID_Q5_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q5_V1 23 +#define BIT_MASK_QUEUEAC_Q5_V1 0x3 +#define BIT_QUEUEAC_Q5_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1) +#define BITS_QUEUEAC_Q5_V1 (BIT_MASK_QUEUEAC_Q5_V1 << BIT_SHIFT_QUEUEAC_Q5_V1) +#define BIT_CLEAR_QUEUEAC_Q5_V1(x) ((x) & (~BITS_QUEUEAC_Q5_V1)) +#define BIT_GET_QUEUEAC_Q5_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1) +#define BIT_SET_QUEUEAC_Q5_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q5_V1(x) | BIT_QUEUEAC_Q5_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET 24 -#define BIT_MASK_R_MUTAB_TXRPT_OFFSET 0xff -#define BIT_R_MUTAB_TXRPT_OFFSET(x) (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET) << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) -#define BIT_GET_R_MUTAB_TXRPT_OFFSET(x) (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) & BIT_MASK_R_MUTAB_TXRPT_OFFSET) +/* 2 REG_Q5_INFO (Offset 0x046C) */ +#define BIT_TIDEMPTY_Q5_V1 BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_Q5_INFO (Offset 0x046C) */ +#define BIT_SHIFT_TAIL_PKT_Q5_V1 15 +#define BIT_MASK_TAIL_PKT_Q5_V1 0xff +#define BIT_TAIL_PKT_Q5_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q5_V1) << BIT_SHIFT_TAIL_PKT_Q5_V1) +#define BITS_TAIL_PKT_Q5_V1 \ + (BIT_MASK_TAIL_PKT_Q5_V1 << BIT_SHIFT_TAIL_PKT_Q5_V1) +#define BIT_CLEAR_TAIL_PKT_Q5_V1(x) ((x) & (~BITS_TAIL_PKT_Q5_V1)) +#define BIT_GET_TAIL_PKT_Q5_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V1) & BIT_MASK_TAIL_PKT_Q5_V1) +#define BIT_SET_TAIL_PKT_Q5_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q5_V1(x) | BIT_TAIL_PKT_Q5_V1(v)) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MACID_MURATE_OFFSET 24 -#define BIT_MASK_MACID_MURATE_OFFSET 0xff -#define BIT_MACID_MURATE_OFFSET(x) (((x) & BIT_MASK_MACID_MURATE_OFFSET) << BIT_SHIFT_MACID_MURATE_OFFSET) -#define BIT_GET_MACID_MURATE_OFFSET(x) (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET) & BIT_MASK_MACID_MURATE_OFFSET) +/* 2 REG_Q5_INFO (Offset 0x046C) */ +#define BIT_SHIFT_TAIL_PKT_Q5_V2 11 +#define BIT_MASK_TAIL_PKT_Q5_V2 0x7ff +#define BIT_TAIL_PKT_Q5_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q5_V2) << BIT_SHIFT_TAIL_PKT_Q5_V2) +#define BITS_TAIL_PKT_Q5_V2 \ + (BIT_MASK_TAIL_PKT_Q5_V2 << BIT_SHIFT_TAIL_PKT_Q5_V2) +#define BIT_CLEAR_TAIL_PKT_Q5_V2(x) ((x) & (~BITS_TAIL_PKT_Q5_V2)) +#define BIT_GET_TAIL_PKT_Q5_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2) & BIT_MASK_TAIL_PKT_Q5_V2) +#define BIT_SET_TAIL_PKT_Q5_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q5_V2(x) | BIT_TAIL_PKT_Q5_V2(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q5_INFO (Offset 0x046C) */ -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ - +#define BIT_SHIFT_PKT_NUM_Q5_V1 8 +#define BIT_MASK_PKT_NUM_Q5_V1 0x7f +#define BIT_PKT_NUM_Q5_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q5_V1) << BIT_SHIFT_PKT_NUM_Q5_V1) +#define BITS_PKT_NUM_Q5_V1 (BIT_MASK_PKT_NUM_Q5_V1 << BIT_SHIFT_PKT_NUM_Q5_V1) +#define BIT_CLEAR_PKT_NUM_Q5_V1(x) ((x) & (~BITS_PKT_NUM_Q5_V1)) +#define BIT_GET_PKT_NUM_Q5_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q5_V1) & BIT_MASK_PKT_NUM_Q5_V1) +#define BIT_SET_PKT_NUM_Q5_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q5_V1(x) | BIT_PKT_NUM_Q5_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q5 0 +#define BIT_MASK_HEAD_PKT_Q5 0xff +#define BIT_HEAD_PKT_Q5(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q5) << BIT_SHIFT_HEAD_PKT_Q5) +#define BITS_HEAD_PKT_Q5 (BIT_MASK_HEAD_PKT_Q5 << BIT_SHIFT_HEAD_PKT_Q5) +#define BIT_CLEAR_HEAD_PKT_Q5(x) ((x) & (~BITS_HEAD_PKT_Q5)) +#define BIT_GET_HEAD_PKT_Q5(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q5) & BIT_MASK_HEAD_PKT_Q5) +#define BIT_SET_HEAD_PKT_Q5(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q5(x) | BIT_HEAD_PKT_Q5(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LOC_BCN_RPT 16 -#define BIT_MASK_LOC_BCN_RPT 0xff -#define BIT_LOC_BCN_RPT(x) (((x) & BIT_MASK_LOC_BCN_RPT) << BIT_SHIFT_LOC_BCN_RPT) -#define BIT_GET_LOC_BCN_RPT(x) (((x) >> BIT_SHIFT_LOC_BCN_RPT) & BIT_MASK_LOC_BCN_RPT) +/* 2 REG_Q5_INFO (Offset 0x046C) */ +#define BIT_SHIFT_HEAD_PKT_Q5_V1 0 +#define BIT_MASK_HEAD_PKT_Q5_V1 0x7ff +#define BIT_HEAD_PKT_Q5_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q5_V1) << BIT_SHIFT_HEAD_PKT_Q5_V1) +#define BITS_HEAD_PKT_Q5_V1 \ + (BIT_MASK_HEAD_PKT_Q5_V1 << BIT_SHIFT_HEAD_PKT_Q5_V1) +#define BIT_CLEAR_HEAD_PKT_Q5_V1(x) ((x) & (~BITS_HEAD_PKT_Q5_V1)) +#define BIT_GET_HEAD_PKT_Q5_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1) & BIT_MASK_HEAD_PKT_Q5_V1) +#define BIT_SET_HEAD_PKT_Q5_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q5_V1(x) | BIT_HEAD_PKT_Q5_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_Q6_INFO (Offset 0x0470) */ +#define BIT_SHIFT_QUEUEMACID_Q6_V1 25 +#define BIT_MASK_QUEUEMACID_Q6_V1 0x7f +#define BIT_QUEUEMACID_Q6_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1) +#define BITS_QUEUEMACID_Q6_V1 \ + (BIT_MASK_QUEUEMACID_Q6_V1 << BIT_SHIFT_QUEUEMACID_Q6_V1) +#define BIT_CLEAR_QUEUEMACID_Q6_V1(x) ((x) & (~BITS_QUEUEMACID_Q6_V1)) +#define BIT_GET_QUEUEMACID_Q6_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1) +#define BIT_SET_QUEUEMACID_Q6_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q6_V1(x) | BIT_QUEUEMACID_Q6_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q6_V1 23 +#define BIT_MASK_QUEUEAC_Q6_V1 0x3 +#define BIT_QUEUEAC_Q6_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1) +#define BITS_QUEUEAC_Q6_V1 (BIT_MASK_QUEUEAC_Q6_V1 << BIT_SHIFT_QUEUEAC_Q6_V1) +#define BIT_CLEAR_QUEUEAC_Q6_V1(x) ((x) & (~BITS_QUEUEAC_Q6_V1)) +#define BIT_GET_QUEUEAC_Q6_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1) +#define BIT_SET_QUEUEAC_Q6_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q6_V1(x) | BIT_QUEUEAC_Q6_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +/* 2 REG_Q6_INFO (Offset 0x0470) */ -#define BIT__R_RPTFIFO_1K BIT(16) +#define BIT_TIDEMPTY_Q6_V1 BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_Q6_INFO (Offset 0x0470) */ +#define BIT_SHIFT_TAIL_PKT_Q6_V1 15 +#define BIT_MASK_TAIL_PKT_Q6_V1 0xff +#define BIT_TAIL_PKT_Q6_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q6_V1) << BIT_SHIFT_TAIL_PKT_Q6_V1) +#define BITS_TAIL_PKT_Q6_V1 \ + (BIT_MASK_TAIL_PKT_Q6_V1 << BIT_SHIFT_TAIL_PKT_Q6_V1) +#define BIT_CLEAR_TAIL_PKT_Q6_V1(x) ((x) & (~BITS_TAIL_PKT_Q6_V1)) +#define BIT_GET_TAIL_PKT_Q6_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V1) & BIT_MASK_TAIL_PKT_Q6_V1) +#define BIT_SET_TAIL_PKT_Q6_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q6_V1(x) | BIT_TAIL_PKT_Q6_V1(v)) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MACID_SHCUT_OFFSET 16 -#define BIT_MASK_MACID_SHCUT_OFFSET 0xff -#define BIT_MACID_SHCUT_OFFSET(x) (((x) & BIT_MASK_MACID_SHCUT_OFFSET) << BIT_SHIFT_MACID_SHCUT_OFFSET) -#define BIT_GET_MACID_SHCUT_OFFSET(x) (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET) & BIT_MASK_MACID_SHCUT_OFFSET) +/* 2 REG_Q6_INFO (Offset 0x0470) */ +#define BIT_SHIFT_TAIL_PKT_Q6_V2 11 +#define BIT_MASK_TAIL_PKT_Q6_V2 0x7ff +#define BIT_TAIL_PKT_Q6_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q6_V2) << BIT_SHIFT_TAIL_PKT_Q6_V2) +#define BITS_TAIL_PKT_Q6_V2 \ + (BIT_MASK_TAIL_PKT_Q6_V2 << BIT_SHIFT_TAIL_PKT_Q6_V2) +#define BIT_CLEAR_TAIL_PKT_Q6_V2(x) ((x) & (~BITS_TAIL_PKT_Q6_V2)) +#define BIT_GET_TAIL_PKT_Q6_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2) & BIT_MASK_TAIL_PKT_Q6_V2) +#define BIT_SET_TAIL_PKT_Q6_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q6_V2(x) | BIT_TAIL_PKT_Q6_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_Q6_INFO (Offset 0x0470) */ +#define BIT_SHIFT_PKT_NUM_Q6_V1 8 +#define BIT_MASK_PKT_NUM_Q6_V1 0x7f +#define BIT_PKT_NUM_Q6_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q6_V1) << BIT_SHIFT_PKT_NUM_Q6_V1) +#define BITS_PKT_NUM_Q6_V1 (BIT_MASK_PKT_NUM_Q6_V1 << BIT_SHIFT_PKT_NUM_Q6_V1) +#define BIT_CLEAR_PKT_NUM_Q6_V1(x) ((x) & (~BITS_PKT_NUM_Q6_V1)) +#define BIT_GET_PKT_NUM_Q6_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q6_V1) & BIT_MASK_PKT_NUM_Q6_V1) +#define BIT_SET_PKT_NUM_Q6_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q6_V1(x) | BIT_PKT_NUM_Q6_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q6 0 +#define BIT_MASK_HEAD_PKT_Q6 0xff +#define BIT_HEAD_PKT_Q6(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q6) << BIT_SHIFT_HEAD_PKT_Q6) +#define BITS_HEAD_PKT_Q6 (BIT_MASK_HEAD_PKT_Q6 << BIT_SHIFT_HEAD_PKT_Q6) +#define BIT_CLEAR_HEAD_PKT_Q6(x) ((x) & (~BITS_HEAD_PKT_Q6)) +#define BIT_GET_HEAD_PKT_Q6(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q6) & BIT_MASK_HEAD_PKT_Q6) +#define BIT_SET_HEAD_PKT_Q6(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q6(x) | BIT_HEAD_PKT_Q6(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +/* 2 REG_Q6_INFO (Offset 0x0470) */ -#define BIT_RPTFIFO_SIZE_OPT BIT(16) +#define BIT_SHIFT_HEAD_PKT_Q6_V1 0 +#define BIT_MASK_HEAD_PKT_Q6_V1 0x7ff +#define BIT_HEAD_PKT_Q6_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q6_V1) << BIT_SHIFT_HEAD_PKT_Q6_V1) +#define BITS_HEAD_PKT_Q6_V1 \ + (BIT_MASK_HEAD_PKT_Q6_V1 << BIT_SHIFT_HEAD_PKT_Q6_V1) +#define BIT_CLEAR_HEAD_PKT_Q6_V1(x) ((x) & (~BITS_HEAD_PKT_Q6_V1)) +#define BIT_GET_HEAD_PKT_Q6_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1) & BIT_MASK_HEAD_PKT_Q6_V1) +#define BIT_SET_HEAD_PKT_Q6_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q6_V1(x) | BIT_HEAD_PKT_Q6_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - - -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +/* 2 REG_Q7_INFO (Offset 0x0474) */ +#define BIT_SHIFT_QUEUEMACID_Q7_V1 25 +#define BIT_MASK_QUEUEMACID_Q7_V1 0x7f +#define BIT_QUEUEMACID_Q7_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1) +#define BITS_QUEUEMACID_Q7_V1 \ + (BIT_MASK_QUEUEMACID_Q7_V1 << BIT_SHIFT_QUEUEMACID_Q7_V1) +#define BIT_CLEAR_QUEUEMACID_Q7_V1(x) ((x) & (~BITS_QUEUEMACID_Q7_V1)) +#define BIT_GET_QUEUEMACID_Q7_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1) +#define BIT_SET_QUEUEMACID_Q7_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q7_V1(x) | BIT_QUEUEMACID_Q7_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q7_V1 23 +#define BIT_MASK_QUEUEAC_Q7_V1 0x3 +#define BIT_QUEUEAC_Q7_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1) +#define BITS_QUEUEAC_Q7_V1 (BIT_MASK_QUEUEAC_Q7_V1 << BIT_SHIFT_QUEUEAC_Q7_V1) +#define BIT_CLEAR_QUEUEAC_Q7_V1(x) ((x) & (~BITS_QUEUEAC_Q7_V1)) +#define BIT_GET_QUEUEAC_Q7_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1) +#define BIT_SET_QUEUEAC_Q7_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q7_V1(x) | BIT_QUEUEAC_Q7_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BFRPT_PARA_USERID_SEL 12 -#define BIT_MASK_BFRPT_PARA_USERID_SEL 0x7 -#define BIT_BFRPT_PARA_USERID_SEL(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL) << BIT_SHIFT_BFRPT_PARA_USERID_SEL) -#define BIT_GET_BFRPT_PARA_USERID_SEL(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL) & BIT_MASK_BFRPT_PARA_USERID_SEL) +/* 2 REG_Q7_INFO (Offset 0x0474) */ +#define BIT_TIDEMPTY_Q7_V1 BIT(22) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q7_INFO (Offset 0x0474) */ -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_TAIL_PKT_Q7_V1 15 +#define BIT_MASK_TAIL_PKT_Q7_V1 0xff +#define BIT_TAIL_PKT_Q7_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q7_V1) << BIT_SHIFT_TAIL_PKT_Q7_V1) +#define BITS_TAIL_PKT_Q7_V1 \ + (BIT_MASK_TAIL_PKT_Q7_V1 << BIT_SHIFT_TAIL_PKT_Q7_V1) +#define BIT_CLEAR_TAIL_PKT_Q7_V1(x) ((x) & (~BITS_TAIL_PKT_Q7_V1)) +#define BIT_GET_TAIL_PKT_Q7_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V1) & BIT_MASK_TAIL_PKT_Q7_V1) +#define BIT_SET_TAIL_PKT_Q7_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q7_V1(x) | BIT_TAIL_PKT_Q7_V1(v)) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LOC_TXRPT 8 -#define BIT_MASK_LOC_TXRPT 0xff -#define BIT_LOC_TXRPT(x) (((x) & BIT_MASK_LOC_TXRPT) << BIT_SHIFT_LOC_TXRPT) -#define BIT_GET_LOC_TXRPT(x) (((x) >> BIT_SHIFT_LOC_TXRPT) & BIT_MASK_LOC_TXRPT) +/* 2 REG_Q7_INFO (Offset 0x0474) */ +#define BIT_SHIFT_TAIL_PKT_Q7_V2 11 +#define BIT_MASK_TAIL_PKT_Q7_V2 0x7ff +#define BIT_TAIL_PKT_Q7_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q7_V2) << BIT_SHIFT_TAIL_PKT_Q7_V2) +#define BITS_TAIL_PKT_Q7_V2 \ + (BIT_MASK_TAIL_PKT_Q7_V2 << BIT_SHIFT_TAIL_PKT_Q7_V2) +#define BIT_CLEAR_TAIL_PKT_Q7_V2(x) ((x) & (~BITS_TAIL_PKT_Q7_V2)) +#define BIT_GET_TAIL_PKT_Q7_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2) & BIT_MASK_TAIL_PKT_Q7_V2) +#define BIT_SET_TAIL_PKT_Q7_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q7_V2(x) | BIT_TAIL_PKT_Q7_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_Q7_INFO (Offset 0x0474) */ +#define BIT_SHIFT_PKT_NUM_Q7_V1 8 +#define BIT_MASK_PKT_NUM_Q7_V1 0x7f +#define BIT_PKT_NUM_Q7_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q7_V1) << BIT_SHIFT_PKT_NUM_Q7_V1) +#define BITS_PKT_NUM_Q7_V1 (BIT_MASK_PKT_NUM_Q7_V1 << BIT_SHIFT_PKT_NUM_Q7_V1) +#define BIT_CLEAR_PKT_NUM_Q7_V1(x) ((x) & (~BITS_PKT_NUM_Q7_V1)) +#define BIT_GET_PKT_NUM_Q7_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q7_V1) & BIT_MASK_PKT_NUM_Q7_V1) +#define BIT_SET_PKT_NUM_Q7_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q7_V1(x) | BIT_PKT_NUM_Q7_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q7 0 +#define BIT_MASK_HEAD_PKT_Q7 0xff +#define BIT_HEAD_PKT_Q7(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q7) << BIT_SHIFT_HEAD_PKT_Q7) +#define BITS_HEAD_PKT_Q7 (BIT_MASK_HEAD_PKT_Q7 << BIT_SHIFT_HEAD_PKT_Q7) +#define BIT_CLEAR_HEAD_PKT_Q7(x) ((x) & (~BITS_HEAD_PKT_Q7)) +#define BIT_GET_HEAD_PKT_Q7(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q7) & BIT_MASK_HEAD_PKT_Q7) +#define BIT_SET_HEAD_PKT_Q7(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q7(x) | BIT_HEAD_PKT_Q7(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +/* 2 REG_Q7_INFO (Offset 0x0474) */ +#define BIT_SHIFT_HEAD_PKT_Q7_V1 0 +#define BIT_MASK_HEAD_PKT_Q7_V1 0x7ff +#define BIT_HEAD_PKT_Q7_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q7_V1) << BIT_SHIFT_HEAD_PKT_Q7_V1) +#define BITS_HEAD_PKT_Q7_V1 \ + (BIT_MASK_HEAD_PKT_Q7_V1 << BIT_SHIFT_HEAD_PKT_Q7_V1) +#define BIT_CLEAR_HEAD_PKT_Q7_V1(x) ((x) & (~BITS_HEAD_PKT_Q7_V1)) +#define BIT_GET_HEAD_PKT_Q7_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1) & BIT_MASK_HEAD_PKT_Q7_V1) +#define BIT_SET_HEAD_PKT_Q7_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q7_V1(x) | BIT_HEAD_PKT_Q7_V1(v)) -#define BIT_SHIFT_MACID_CTRL_OFFSET 8 -#define BIT_MASK_MACID_CTRL_OFFSET 0xff -#define BIT_MACID_CTRL_OFFSET(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET) -#define BIT_GET_MACID_CTRL_OFFSET(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_WMAC_LBK_BUF_HD_V1 (Offset 0x0478) */ +#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1 0 +#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1 0xfff +#define BIT_WMAC_LBK_BUF_HEAD_V1(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1) \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) +#define BITS_WMAC_LBK_BUF_HEAD_V1 \ + (BIT_MASK_WMAC_LBK_BUF_HEAD_V1 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) & \ + BIT_MASK_WMAC_LBK_BUF_HEAD_V1) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1(x) | BIT_WMAC_LBK_BUF_HEAD_V1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MGQ_BDNY_V1 (Offset 0x047A) */ +#define BIT_SHIFT_MGQ_PGBNDY_V1 0 +#define BIT_MASK_MGQ_PGBNDY_V1 0xfff +#define BIT_MGQ_PGBNDY_V1(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V1) << BIT_SHIFT_MGQ_PGBNDY_V1) +#define BITS_MGQ_PGBNDY_V1 (BIT_MASK_MGQ_PGBNDY_V1 << BIT_SHIFT_MGQ_PGBNDY_V1) +#define BIT_CLEAR_MGQ_PGBNDY_V1(x) ((x) & (~BITS_MGQ_PGBNDY_V1)) +#define BIT_GET_MGQ_PGBNDY_V1(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1) & BIT_MASK_MGQ_PGBNDY_V1) +#define BIT_SET_MGQ_PGBNDY_V1(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V1(x) | BIT_MGQ_PGBNDY_V1(v)) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LOC_SRFF 0 -#define BIT_MASK_LOC_SRFF 0xff -#define BIT_LOC_SRFF(x) (((x) & BIT_MASK_LOC_SRFF) << BIT_SHIFT_LOC_SRFF) -#define BIT_GET_LOC_SRFF(x) (((x) >> BIT_SHIFT_LOC_SRFF) & BIT_MASK_LOC_SRFF) +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_SHIFT_SPC_READ_PTR 24 +#define BIT_MASK_SPC_READ_PTR 0xf +#define BIT_SPC_READ_PTR(x) \ + (((x) & BIT_MASK_SPC_READ_PTR) << BIT_SHIFT_SPC_READ_PTR) +#define BITS_SPC_READ_PTR (BIT_MASK_SPC_READ_PTR << BIT_SHIFT_SPC_READ_PTR) +#define BIT_CLEAR_SPC_READ_PTR(x) ((x) & (~BITS_SPC_READ_PTR)) +#define BIT_GET_SPC_READ_PTR(x) \ + (((x) >> BIT_SHIFT_SPC_READ_PTR) & BIT_MASK_SPC_READ_PTR) +#define BIT_SET_SPC_READ_PTR(x, v) \ + (BIT_CLEAR_SPC_READ_PTR(x) | BIT_SPC_READ_PTR(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_SHIFT_TRXRPT_TIMER_TH 24 +#define BIT_MASK_TRXRPT_TIMER_TH 0xff +#define BIT_TRXRPT_TIMER_TH(x) \ + (((x) & BIT_MASK_TRXRPT_TIMER_TH) << BIT_SHIFT_TRXRPT_TIMER_TH) +#define BITS_TRXRPT_TIMER_TH \ + (BIT_MASK_TRXRPT_TIMER_TH << BIT_SHIFT_TRXRPT_TIMER_TH) +#define BIT_CLEAR_TRXRPT_TIMER_TH(x) ((x) & (~BITS_TRXRPT_TIMER_TH)) +#define BIT_GET_TRXRPT_TIMER_TH(x) \ + (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH) & BIT_MASK_TRXRPT_TIMER_TH) +#define BIT_SET_TRXRPT_TIMER_TH(x, v) \ + (BIT_CLEAR_TRXRPT_TIMER_TH(x) | BIT_TRXRPT_TIMER_TH(v)) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_AMPDU_TXRPT_OFFSET 0 -#define BIT_MASK_AMPDU_TXRPT_OFFSET 0xff -#define BIT_AMPDU_TXRPT_OFFSET(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET) -#define BIT_GET_AMPDU_TXRPT_OFFSET(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET) +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_SHIFT_SPC_WRITE_PTR 16 +#define BIT_MASK_SPC_WRITE_PTR 0xf +#define BIT_SPC_WRITE_PTR(x) \ + (((x) & BIT_MASK_SPC_WRITE_PTR) << BIT_SHIFT_SPC_WRITE_PTR) +#define BITS_SPC_WRITE_PTR (BIT_MASK_SPC_WRITE_PTR << BIT_SHIFT_SPC_WRITE_PTR) +#define BIT_CLEAR_SPC_WRITE_PTR(x) ((x) & (~BITS_SPC_WRITE_PTR)) +#define BIT_GET_SPC_WRITE_PTR(x) \ + (((x) >> BIT_SHIFT_SPC_WRITE_PTR) & BIT_MASK_SPC_WRITE_PTR) +#define BIT_SET_SPC_WRITE_PTR(x, v) \ + (BIT_CLEAR_SPC_WRITE_PTR(x) | BIT_SPC_WRITE_PTR(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_SHIFT_TRXRPT_LEN_TH 16 +#define BIT_MASK_TRXRPT_LEN_TH 0xff +#define BIT_TRXRPT_LEN_TH(x) \ + (((x) & BIT_MASK_TRXRPT_LEN_TH) << BIT_SHIFT_TRXRPT_LEN_TH) +#define BITS_TRXRPT_LEN_TH (BIT_MASK_TRXRPT_LEN_TH << BIT_SHIFT_TRXRPT_LEN_TH) +#define BIT_CLEAR_TRXRPT_LEN_TH(x) ((x) & (~BITS_TRXRPT_LEN_TH)) +#define BIT_GET_TRXRPT_LEN_TH(x) \ + (((x) >> BIT_SHIFT_TRXRPT_LEN_TH) & BIT_MASK_TRXRPT_LEN_TH) +#define BIT_SET_TRXRPT_LEN_TH(x, v) \ + (BIT_CLEAR_TRXRPT_LEN_TH(x) | BIT_TRXRPT_LEN_TH(v)) -/* 2 REG_TRYING_CNT_TH (Offset 0x04B0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_INDEX_15 24 -#define BIT_MASK_INDEX_15 0xff -#define BIT_INDEX_15(x) (((x) & BIT_MASK_INDEX_15) << BIT_SHIFT_INDEX_15) -#define BIT_GET_INDEX_15(x) (((x) >> BIT_SHIFT_INDEX_15) & BIT_MASK_INDEX_15) +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_SHIFT_AC_READ_PTR 8 +#define BIT_MASK_AC_READ_PTR 0xf +#define BIT_AC_READ_PTR(x) \ + (((x) & BIT_MASK_AC_READ_PTR) << BIT_SHIFT_AC_READ_PTR) +#define BITS_AC_READ_PTR (BIT_MASK_AC_READ_PTR << BIT_SHIFT_AC_READ_PTR) +#define BIT_CLEAR_AC_READ_PTR(x) ((x) & (~BITS_AC_READ_PTR)) +#define BIT_GET_AC_READ_PTR(x) \ + (((x) >> BIT_SHIFT_AC_READ_PTR) & BIT_MASK_AC_READ_PTR) +#define BIT_SET_AC_READ_PTR(x, v) \ + (BIT_CLEAR_AC_READ_PTR(x) | BIT_AC_READ_PTR(v)) -#define BIT_SHIFT_INDEX_14 16 -#define BIT_MASK_INDEX_14 0xff -#define BIT_INDEX_14(x) (((x) & BIT_MASK_INDEX_14) << BIT_SHIFT_INDEX_14) -#define BIT_GET_INDEX_14(x) (((x) >> BIT_SHIFT_INDEX_14) & BIT_MASK_INDEX_14) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_INDEX_13 8 -#define BIT_MASK_INDEX_13 0xff -#define BIT_INDEX_13(x) (((x) & BIT_MASK_INDEX_13) << BIT_SHIFT_INDEX_13) -#define BIT_GET_INDEX_13(x) (((x) >> BIT_SHIFT_INDEX_13) & BIT_MASK_INDEX_13) +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_SHIFT_TRXRPT_READ_PTR 8 +#define BIT_MASK_TRXRPT_READ_PTR 0xff +#define BIT_TRXRPT_READ_PTR(x) \ + (((x) & BIT_MASK_TRXRPT_READ_PTR) << BIT_SHIFT_TRXRPT_READ_PTR) +#define BITS_TRXRPT_READ_PTR \ + (BIT_MASK_TRXRPT_READ_PTR << BIT_SHIFT_TRXRPT_READ_PTR) +#define BIT_CLEAR_TRXRPT_READ_PTR(x) ((x) & (~BITS_TRXRPT_READ_PTR)) +#define BIT_GET_TRXRPT_READ_PTR(x) \ + (((x) >> BIT_SHIFT_TRXRPT_READ_PTR) & BIT_MASK_TRXRPT_READ_PTR) +#define BIT_SET_TRXRPT_READ_PTR(x, v) \ + (BIT_CLEAR_TRXRPT_READ_PTR(x) | BIT_TRXRPT_READ_PTR(v)) -#define BIT_SHIFT_INDEX_12 0 -#define BIT_MASK_INDEX_12 0xff -#define BIT_INDEX_12(x) (((x) & BIT_MASK_INDEX_12) << BIT_SHIFT_INDEX_12) -#define BIT_GET_INDEX_12(x) (((x) >> BIT_SHIFT_INDEX_12) & BIT_MASK_INDEX_12) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT 0 -#define BIT_MASK_RA_TRY_RATE_AGG_LMT 0x1f -#define BIT_RA_TRY_RATE_AGG_LMT(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT) -#define BIT_GET_RA_TRY_RATE_AGG_LMT(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT) & BIT_MASK_RA_TRY_RATE_AGG_LMT) +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_SHIFT_AC_WRITE_PTR 0 +#define BIT_MASK_AC_WRITE_PTR 0xf +#define BIT_AC_WRITE_PTR(x) \ + (((x) & BIT_MASK_AC_WRITE_PTR) << BIT_SHIFT_AC_WRITE_PTR) +#define BITS_AC_WRITE_PTR (BIT_MASK_AC_WRITE_PTR << BIT_SHIFT_AC_WRITE_PTR) +#define BIT_CLEAR_AC_WRITE_PTR(x) ((x) & (~BITS_AC_WRITE_PTR)) +#define BIT_GET_AC_WRITE_PTR(x) \ + (((x) >> BIT_SHIFT_AC_WRITE_PTR) & BIT_MASK_AC_WRITE_PTR) +#define BIT_SET_AC_WRITE_PTR(x, v) \ + (BIT_CLEAR_AC_WRITE_PTR(x) | BIT_AC_WRITE_PTR(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ -#define BIT_PTA_WL_PRI_MASK_CPU_MGQ BIT(31) -#define BIT_PTA_WL_PRI_MASK_BCNQ BIT(30) -#define BIT_PTA_WL_PRI_MASK_HIQ BIT(29) -#define BIT_PTA_WL_PRI_MASK_MGQ BIT(28) -#define BIT_PTA_WL_PRI_MASK_BK BIT(27) -#define BIT_PTA_WL_PRI_MASK_BE BIT(26) -#define BIT_PTA_WL_PRI_MASK_VI BIT(25) -#define BIT_PTA_WL_PRI_MASK_VO BIT(24) +#define BIT_SHIFT_TRXRPT_WRITE_PTR 0 +#define BIT_MASK_TRXRPT_WRITE_PTR 0xff +#define BIT_TRXRPT_WRITE_PTR(x) \ + (((x) & BIT_MASK_TRXRPT_WRITE_PTR) << BIT_SHIFT_TRXRPT_WRITE_PTR) +#define BITS_TRXRPT_WRITE_PTR \ + (BIT_MASK_TRXRPT_WRITE_PTR << BIT_SHIFT_TRXRPT_WRITE_PTR) +#define BIT_CLEAR_TRXRPT_WRITE_PTR(x) ((x) & (~BITS_TRXRPT_WRITE_PTR)) +#define BIT_GET_TRXRPT_WRITE_PTR(x) \ + (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR) & BIT_MASK_TRXRPT_WRITE_PTR) +#define BIT_SET_TRXRPT_WRITE_PTR(x, v) \ + (BIT_CLEAR_TRXRPT_WRITE_PTR(x) | BIT_TRXRPT_WRITE_PTR(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_INIRTS_RATE_SEL (Offset 0x0480) */ +#define BIT_LEAG_RTS_BW_DUP BIT(5) -/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ +/* 2 REG_BASIC_CFEND_RATE (Offset 0x0481) */ + +#define BIT_SHIFT_BASIC_CFEND_RATE 0 +#define BIT_MASK_BASIC_CFEND_RATE 0x1f +#define BIT_BASIC_CFEND_RATE(x) \ + (((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE) +#define BITS_BASIC_CFEND_RATE \ + (BIT_MASK_BASIC_CFEND_RATE << BIT_SHIFT_BASIC_CFEND_RATE) +#define BIT_CLEAR_BASIC_CFEND_RATE(x) ((x) & (~BITS_BASIC_CFEND_RATE)) +#define BIT_GET_BASIC_CFEND_RATE(x) \ + (((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE) +#define BIT_SET_BASIC_CFEND_RATE(x, v) \ + (BIT_CLEAR_BASIC_CFEND_RATE(x) | BIT_BASIC_CFEND_RATE(v)) +/* 2 REG_STBC_CFEND_RATE (Offset 0x0482) */ -#define BIT_SHIFT_POWER_STAGE1 0 -#define BIT_MASK_POWER_STAGE1 0xffffff -#define BIT_POWER_STAGE1(x) (((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1) -#define BIT_GET_POWER_STAGE1(x) (((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1) +#define BIT_SHIFT_STBC_CFEND_RATE 0 +#define BIT_MASK_STBC_CFEND_RATE 0x1f +#define BIT_STBC_CFEND_RATE(x) \ + (((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE) +#define BITS_STBC_CFEND_RATE \ + (BIT_MASK_STBC_CFEND_RATE << BIT_SHIFT_STBC_CFEND_RATE) +#define BIT_CLEAR_STBC_CFEND_RATE(x) ((x) & (~BITS_STBC_CFEND_RATE)) +#define BIT_GET_STBC_CFEND_RATE(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE) +#define BIT_SET_STBC_CFEND_RATE(x, v) \ + (BIT_CLEAR_STBC_CFEND_RATE(x) | BIT_STBC_CFEND_RATE(v)) +/* 2 REG_DATA_SC (Offset 0x0483) */ -#endif +#define BIT_SHIFT_TXSC_40M 4 +#define BIT_MASK_TXSC_40M 0xf +#define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) +#define BITS_TXSC_40M (BIT_MASK_TXSC_40M << BIT_SHIFT_TXSC_40M) +#define BIT_CLEAR_TXSC_40M(x) ((x) & (~BITS_TXSC_40M)) +#define BIT_GET_TXSC_40M(x) (((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M) +#define BIT_SET_TXSC_40M(x, v) (BIT_CLEAR_TXSC_40M(x) | BIT_TXSC_40M(v)) +#define BIT_SHIFT_TXSC_20M 0 +#define BIT_MASK_TXSC_20M 0xf +#define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) +#define BITS_TXSC_20M (BIT_MASK_TXSC_20M << BIT_SHIFT_TXSC_20M) +#define BIT_CLEAR_TXSC_20M(x) ((x) & (~BITS_TXSC_20M)) +#define BIT_GET_TXSC_20M(x) (((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M) +#define BIT_SET_TXSC_20M(x, v) (BIT_CLEAR_TXSC_20M(x) | BIT_TXSC_20M(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ +/* 2 REG_MACID_SLEEP3 (Offset 0x0484) */ -#define BIT__R_CTRL_PKT_POW_ADJ BIT(24) +#define BIT_SHIFT_MACID127_96_PKTSLEEP 0 +#define BIT_MASK_MACID127_96_PKTSLEEP 0xffffffffL +#define BIT_MACID127_96_PKTSLEEP(x) \ + (((x) & BIT_MASK_MACID127_96_PKTSLEEP) \ + << BIT_SHIFT_MACID127_96_PKTSLEEP) +#define BITS_MACID127_96_PKTSLEEP \ + (BIT_MASK_MACID127_96_PKTSLEEP << BIT_SHIFT_MACID127_96_PKTSLEEP) +#define BIT_CLEAR_MACID127_96_PKTSLEEP(x) ((x) & (~BITS_MACID127_96_PKTSLEEP)) +#define BIT_GET_MACID127_96_PKTSLEEP(x) \ + (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) & \ + BIT_MASK_MACID127_96_PKTSLEEP) +#define BIT_SET_MACID127_96_PKTSLEEP(x, v) \ + (BIT_CLEAR_MACID127_96_PKTSLEEP(x) | BIT_MACID127_96_PKTSLEEP(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DATA_SC1 (Offset 0x0487) */ +#define BIT_SHIFT_TXSC_160M 4 +#define BIT_MASK_TXSC_160M 0xf +#define BIT_TXSC_160M(x) (((x) & BIT_MASK_TXSC_160M) << BIT_SHIFT_TXSC_160M) +#define BITS_TXSC_160M (BIT_MASK_TXSC_160M << BIT_SHIFT_TXSC_160M) +#define BIT_CLEAR_TXSC_160M(x) ((x) & (~BITS_TXSC_160M)) +#define BIT_GET_TXSC_160M(x) (((x) >> BIT_SHIFT_TXSC_160M) & BIT_MASK_TXSC_160M) +#define BIT_SET_TXSC_160M(x, v) (BIT_CLEAR_TXSC_160M(x) | BIT_TXSC_160M(v)) -/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ +#define BIT_SHIFT_TXSC_80M 0 +#define BIT_MASK_TXSC_80M 0xf +#define BIT_TXSC_80M(x) (((x) & BIT_MASK_TXSC_80M) << BIT_SHIFT_TXSC_80M) +#define BITS_TXSC_80M (BIT_MASK_TXSC_80M << BIT_SHIFT_TXSC_80M) +#define BIT_CLEAR_TXSC_80M(x) ((x) & (~BITS_TXSC_80M)) +#define BIT_GET_TXSC_80M(x) (((x) >> BIT_SHIFT_TXSC_80M) & BIT_MASK_TXSC_80M) +#define BIT_SET_TXSC_80M(x, v) (BIT_CLEAR_TXSC_80M(x) | BIT_TXSC_80M(v)) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_POWER_STAGE2 0 -#define BIT_MASK_POWER_STAGE2 0xffffff -#define BIT_POWER_STAGE2(x) (((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2) -#define BIT_GET_POWER_STAGE2(x) (((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2) +/* 2 REG_MACID_SLEEP1 (Offset 0x0488) */ +#define BIT_SHIFT_MACID63_32_PKTSLEEP 0 +#define BIT_MASK_MACID63_32_PKTSLEEP 0xffffffffL +#define BIT_MACID63_32_PKTSLEEP(x) \ + (((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP) +#define BITS_MACID63_32_PKTSLEEP \ + (BIT_MASK_MACID63_32_PKTSLEEP << BIT_SHIFT_MACID63_32_PKTSLEEP) +#define BIT_CLEAR_MACID63_32_PKTSLEEP(x) ((x) & (~BITS_MACID63_32_PKTSLEEP)) +#define BIT_GET_MACID63_32_PKTSLEEP(x) \ + (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP) +#define BIT_SET_MACID63_32_PKTSLEEP(x, v) \ + (BIT_CLEAR_MACID63_32_PKTSLEEP(x) | BIT_MACID63_32_PKTSLEEP(v)) -/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PAD_NUM_THRES 24 -#define BIT_MASK_PAD_NUM_THRES 0x3f -#define BIT_PAD_NUM_THRES(x) (((x) & BIT_MASK_PAD_NUM_THRES) << BIT_SHIFT_PAD_NUM_THRES) -#define BIT_GET_PAD_NUM_THRES(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES) & BIT_MASK_PAD_NUM_THRES) +/* 2 REG_ARFR2_V1 (Offset 0x048C) */ +#define BIT_SHIFT_ARFR2_V1 0 +#define BIT_MASK_ARFR2_V1 0xffffffffffffffffL +#define BIT_ARFR2_V1(x) (((x) & BIT_MASK_ARFR2_V1) << BIT_SHIFT_ARFR2_V1) +#define BITS_ARFR2_V1 (BIT_MASK_ARFR2_V1 << BIT_SHIFT_ARFR2_V1) +#define BIT_CLEAR_ARFR2_V1(x) ((x) & (~BITS_ARFR2_V1)) +#define BIT_GET_ARFR2_V1(x) (((x) >> BIT_SHIFT_ARFR2_V1) & BIT_MASK_ARFR2_V1) +#define BIT_SET_ARFR2_V1(x, v) (BIT_CLEAR_ARFR2_V1(x) | BIT_ARFR2_V1(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ARFR2_V1 (Offset 0x048C) */ -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_SHIFT_ARFRL2 0 +#define BIT_MASK_ARFRL2 0xffffffffL +#define BIT_ARFRL2(x) (((x) & BIT_MASK_ARFRL2) << BIT_SHIFT_ARFRL2) +#define BITS_ARFRL2 (BIT_MASK_ARFRL2 << BIT_SHIFT_ARFRL2) +#define BIT_CLEAR_ARFRL2(x) ((x) & (~BITS_ARFRL2)) +#define BIT_GET_ARFRL2(x) (((x) >> BIT_SHIFT_ARFRL2) & BIT_MASK_ARFRL2) +#define BIT_SET_ARFRL2(x, v) (BIT_CLEAR_ARFRL2(x) | BIT_ARFRL2(v)) +/* 2 REG_ARFRH2_V1 (Offset 0x0490) */ -/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_SHIFT_ARFRH2 0 +#define BIT_MASK_ARFRH2 0xffffffffL +#define BIT_ARFRH2(x) (((x) & BIT_MASK_ARFRH2) << BIT_SHIFT_ARFRH2) +#define BITS_ARFRH2 (BIT_MASK_ARFRH2 << BIT_SHIFT_ARFRH2) +#define BIT_CLEAR_ARFRH2(x) ((x) & (~BITS_ARFRH2)) +#define BIT_GET_ARFRH2(x) (((x) >> BIT_SHIFT_ARFRH2) & BIT_MASK_ARFRH2) +#define BIT_SET_ARFRH2(x, v) (BIT_CLEAR_ARFRH2(x) | BIT_ARFRH2(v)) -#define BIT_R_DMA_THIS_QUEUE_BK BIT(23) -#define BIT_R_DMA_THIS_QUEUE_BE BIT(22) -#define BIT_R_DMA_THIS_QUEUE_VI BIT(21) -#define BIT_R_DMA_THIS_QUEUE_VO BIT(20) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_TOTAL_LEN_TH 8 -#define BIT_MASK_R_TOTAL_LEN_TH 0xfff -#define BIT_R_TOTAL_LEN_TH(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH) << BIT_SHIFT_R_TOTAL_LEN_TH) -#define BIT_GET_R_TOTAL_LEN_TH(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH) & BIT_MASK_R_TOTAL_LEN_TH) +/* 2 REG_ARFR3_V1 (Offset 0x0494) */ +#define BIT_SHIFT_ARFR3_V1 0 +#define BIT_MASK_ARFR3_V1 0xffffffffffffffffL +#define BIT_ARFR3_V1(x) (((x) & BIT_MASK_ARFR3_V1) << BIT_SHIFT_ARFR3_V1) +#define BITS_ARFR3_V1 (BIT_MASK_ARFR3_V1 << BIT_SHIFT_ARFR3_V1) +#define BIT_CLEAR_ARFR3_V1(x) ((x) & (~BITS_ARFR3_V1)) +#define BIT_GET_ARFR3_V1(x) (((x) >> BIT_SHIFT_ARFR3_V1) & BIT_MASK_ARFR3_V1) +#define BIT_SET_ARFR3_V1(x, v) (BIT_CLEAR_ARFR3_V1(x) | BIT_ARFR3_V1(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ARFR3_V1 (Offset 0x0494) */ +#define BIT_SHIFT_ARFRL3 0 +#define BIT_MASK_ARFRL3 0xffffffffL +#define BIT_ARFRL3(x) (((x) & BIT_MASK_ARFRL3) << BIT_SHIFT_ARFRL3) +#define BITS_ARFRL3 (BIT_MASK_ARFRL3 << BIT_SHIFT_ARFRL3) +#define BIT_CLEAR_ARFRL3(x) ((x) & (~BITS_ARFRL3)) +#define BIT_GET_ARFRL3(x) (((x) >> BIT_SHIFT_ARFRL3) & BIT_MASK_ARFRL3) +#define BIT_SET_ARFRL3(x, v) (BIT_CLEAR_ARFRL3(x) | BIT_ARFRL3(v)) -/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +/* 2 REG_ARFRH3_V1 (Offset 0x0498) */ -#define BIT_EN_NEW_EARLY BIT(7) +#define BIT_SHIFT_ARFRH3 0 +#define BIT_MASK_ARFRH3 0xffffffffL +#define BIT_ARFRH3(x) (((x) & BIT_MASK_ARFRH3) << BIT_SHIFT_ARFRH3) +#define BITS_ARFRH3 (BIT_MASK_ARFRH3 << BIT_SHIFT_ARFRH3) +#define BIT_CLEAR_ARFRH3(x) ((x) & (~BITS_ARFRH3)) +#define BIT_GET_ARFRH3(x) (((x) >> BIT_SHIFT_ARFRH3) & BIT_MASK_ARFRH3) +#define BIT_SET_ARFRH3(x, v) (BIT_CLEAR_ARFRH3(x) | BIT_ARFRH3(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_ARFR4 (Offset 0x049C) */ -/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_SHIFT_ARFR4 0 +#define BIT_MASK_ARFR4 0xffffffffffffffffL +#define BIT_ARFR4(x) (((x) & BIT_MASK_ARFR4) << BIT_SHIFT_ARFR4) +#define BITS_ARFR4 (BIT_MASK_ARFR4 << BIT_SHIFT_ARFR4) +#define BIT_CLEAR_ARFR4(x) ((x) & (~BITS_ARFR4)) +#define BIT_GET_ARFR4(x) (((x) >> BIT_SHIFT_ARFR4) & BIT_MASK_ARFR4) +#define BIT_SET_ARFR4(x, v) (BIT_CLEAR_ARFR4(x) | BIT_ARFR4(v)) -#define BIT_PRE_TX_CMD BIT(6) +#endif -#define BIT_SHIFT_NUM_SCL_EN 4 -#define BIT_MASK_NUM_SCL_EN 0x3 -#define BIT_NUM_SCL_EN(x) (((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN) -#define BIT_GET_NUM_SCL_EN(x) (((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN) +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_BK_EN BIT(3) -#define BIT_BE_EN BIT(2) -#define BIT_VI_EN BIT(1) -#define BIT_VO_EN BIT(0) +/* 2 REG_ARFR4 (Offset 0x049C) */ -/* 2 REG_PKT_LIFE_TIME (Offset 0x04C0) */ +#define BIT_SHIFT_ARFRL4 0 +#define BIT_MASK_ARFRL4 0xffffffffL +#define BIT_ARFRL4(x) (((x) & BIT_MASK_ARFRL4) << BIT_SHIFT_ARFRL4) +#define BITS_ARFRL4 (BIT_MASK_ARFRL4 << BIT_SHIFT_ARFRL4) +#define BIT_CLEAR_ARFRL4(x) ((x) & (~BITS_ARFRL4)) +#define BIT_GET_ARFRL4(x) (((x) >> BIT_SHIFT_ARFRL4) & BIT_MASK_ARFRL4) +#define BIT_SET_ARFRL4(x, v) (BIT_CLEAR_ARFRL4(x) | BIT_ARFRL4(v)) +/* 2 REG_ARFRH4 (Offset 0x04A0) */ -#define BIT_SHIFT_PKT_LIFTIME_BEBK 16 -#define BIT_MASK_PKT_LIFTIME_BEBK 0xffff -#define BIT_PKT_LIFTIME_BEBK(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK) -#define BIT_GET_PKT_LIFTIME_BEBK(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK) +#define BIT_SHIFT_ARFRH4 0 +#define BIT_MASK_ARFRH4 0xffffffffL +#define BIT_ARFRH4(x) (((x) & BIT_MASK_ARFRH4) << BIT_SHIFT_ARFRH4) +#define BITS_ARFRH4 (BIT_MASK_ARFRH4 << BIT_SHIFT_ARFRH4) +#define BIT_CLEAR_ARFRH4(x) ((x) & (~BITS_ARFRH4)) +#define BIT_GET_ARFRH4(x) (((x) >> BIT_SHIFT_ARFRH4) & BIT_MASK_ARFRH4) +#define BIT_SET_ARFRH4(x, v) (BIT_CLEAR_ARFRH4(x) | BIT_ARFRH4(v)) +#endif -#define BIT_SHIFT_PKT_LIFTIME_VOVI 0 -#define BIT_MASK_PKT_LIFTIME_VOVI 0xffff -#define BIT_PKT_LIFTIME_VOVI(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI) -#define BIT_GET_PKT_LIFTIME_VOVI(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) +/* 2 REG_ARFR5 (Offset 0x04A4) */ -/* 2 REG_STBC_SETTING (Offset 0x04C4) */ +#define BIT_SHIFT_ARFR5 0 +#define BIT_MASK_ARFR5 0xffffffffffffffffL +#define BIT_ARFR5(x) (((x) & BIT_MASK_ARFR5) << BIT_SHIFT_ARFR5) +#define BITS_ARFR5 (BIT_MASK_ARFR5 << BIT_SHIFT_ARFR5) +#define BIT_CLEAR_ARFR5(x) ((x) & (~BITS_ARFR5)) +#define BIT_GET_ARFR5(x) (((x) >> BIT_SHIFT_ARFR5) & BIT_MASK_ARFR5) +#define BIT_SET_ARFR5(x, v) (BIT_CLEAR_ARFR5(x) | BIT_ARFR5(v)) +#endif -#define BIT_SHIFT_CDEND_TXTIME_L 4 -#define BIT_MASK_CDEND_TXTIME_L 0xf -#define BIT_CDEND_TXTIME_L(x) (((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L) -#define BIT_GET_CDEND_TXTIME_L(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L) +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_ARFR5 (Offset 0x04A4) */ -#define BIT_SHIFT_NESS 2 -#define BIT_MASK_NESS 0x3 -#define BIT_NESS(x) (((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS) -#define BIT_GET_NESS(x) (((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS) +#define BIT_SHIFT_ARFRL5 0 +#define BIT_MASK_ARFRL5 0xffffffffL +#define BIT_ARFRL5(x) (((x) & BIT_MASK_ARFRL5) << BIT_SHIFT_ARFRL5) +#define BITS_ARFRL5 (BIT_MASK_ARFRL5 << BIT_SHIFT_ARFRL5) +#define BIT_CLEAR_ARFRL5(x) ((x) & (~BITS_ARFRL5)) +#define BIT_GET_ARFRL5(x) (((x) >> BIT_SHIFT_ARFRL5) & BIT_MASK_ARFRL5) +#define BIT_SET_ARFRL5(x, v) (BIT_CLEAR_ARFRL5(x) | BIT_ARFRL5(v)) +/* 2 REG_ARFRH5 (Offset 0x04A8) */ -#define BIT_SHIFT_STBC_CFEND 0 -#define BIT_MASK_STBC_CFEND 0x3 -#define BIT_STBC_CFEND(x) (((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND) -#define BIT_GET_STBC_CFEND(x) (((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND) +#define BIT_SHIFT_ARFRH5 0 +#define BIT_MASK_ARFRH5 0xffffffffL +#define BIT_ARFRH5(x) (((x) & BIT_MASK_ARFRH5) << BIT_SHIFT_ARFRH5) +#define BITS_ARFRH5 (BIT_MASK_ARFRH5 << BIT_SHIFT_ARFRH5) +#define BIT_CLEAR_ARFRH5(x) ((x) & (~BITS_ARFRH5)) +#define BIT_GET_ARFRH5(x) (((x) >> BIT_SHIFT_ARFRH5) & BIT_MASK_ARFRH5) +#define BIT_SET_ARFRH5(x, v) (BIT_CLEAR_ARFRH5(x) | BIT_ARFRH5(v)) +#endif -/* 2 REG_STBC_SETTING2 (Offset 0x04C5) */ +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ -#define BIT_SHIFT_CDEND_TXTIME_H 0 -#define BIT_MASK_CDEND_TXTIME_H 0x1f -#define BIT_CDEND_TXTIME_H(x) (((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H) -#define BIT_GET_CDEND_TXTIME_H(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H) +#define BIT_RPTFIFO_RPTNUM_OPT BIT(31) +#define BIT_SHIFT_MISSED_RPT_NUM 28 +#define BIT_MASK_MISSED_RPT_NUM 0x7 +#define BIT_MISSED_RPT_NUM(x) \ + (((x) & BIT_MASK_MISSED_RPT_NUM) << BIT_SHIFT_MISSED_RPT_NUM) +#define BITS_MISSED_RPT_NUM \ + (BIT_MASK_MISSED_RPT_NUM << BIT_SHIFT_MISSED_RPT_NUM) +#define BIT_CLEAR_MISSED_RPT_NUM(x) ((x) & (~BITS_MISSED_RPT_NUM)) +#define BIT_GET_MISSED_RPT_NUM(x) \ + (((x) >> BIT_SHIFT_MISSED_RPT_NUM) & BIT_MASK_MISSED_RPT_NUM) +#define BIT_SET_MISSED_RPT_NUM(x, v) \ + (BIT_CLEAR_MISSED_RPT_NUM(x) | BIT_MISSED_RPT_NUM(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHCUT_PARSE_DASA BIT(25) -/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ +#endif -#define BIT_PTA_EDCCA_EN BIT(5) -#define BIT_PTA_WL_TX_EN BIT(4) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_LOC_AMPDU_BURST_CTRL 24 +#define BIT_MASK_LOC_AMPDU_BURST_CTRL 0xff +#define BIT_LOC_AMPDU_BURST_CTRL(x) \ + (((x) & BIT_MASK_LOC_AMPDU_BURST_CTRL) \ + << BIT_SHIFT_LOC_AMPDU_BURST_CTRL) +#define BITS_LOC_AMPDU_BURST_CTRL \ + (BIT_MASK_LOC_AMPDU_BURST_CTRL << BIT_SHIFT_LOC_AMPDU_BURST_CTRL) +#define BIT_CLEAR_LOC_AMPDU_BURST_CTRL(x) ((x) & (~BITS_LOC_AMPDU_BURST_CTRL)) +#define BIT_GET_LOC_AMPDU_BURST_CTRL(x) \ + (((x) >> BIT_SHIFT_LOC_AMPDU_BURST_CTRL) & \ + BIT_MASK_LOC_AMPDU_BURST_CTRL) +#define BIT_SET_LOC_AMPDU_BURST_CTRL(x, v) \ + (BIT_CLEAR_LOC_AMPDU_BURST_CTRL(x) | BIT_LOC_AMPDU_BURST_CTRL(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ -#define BIT_R_USE_DATA_BW BIT(3) -#define BIT_TRI_PKT_INT_MODE1 BIT(2) -#define BIT_TRI_PKT_INT_MODE0 BIT(1) -#define BIT_ACQ_MODE_SEL BIT(0) +#define BIT_SHCUT_BYPASS BIT(24) -/* 2 REG_SINGLE_AMPDU_CTRL (Offset 0x04C7) */ +#endif -#define BIT_EN_SINGLE_APMDU BIT(7) +#if (HALMAC_8821C_SUPPORT) -/* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */ +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET 24 +#define BIT_MASK_R_MUTAB_TXRPT_OFFSET 0xff +#define BIT_R_MUTAB_TXRPT_OFFSET(x) \ + (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET) \ + << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) +#define BITS_R_MUTAB_TXRPT_OFFSET \ + (BIT_MASK_R_MUTAB_TXRPT_OFFSET << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) +#define BIT_CLEAR_R_MUTAB_TXRPT_OFFSET(x) ((x) & (~BITS_R_MUTAB_TXRPT_OFFSET)) +#define BIT_GET_R_MUTAB_TXRPT_OFFSET(x) \ + (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) & \ + BIT_MASK_R_MUTAB_TXRPT_OFFSET) +#define BIT_SET_R_MUTAB_TXRPT_OFFSET(x, v) \ + (BIT_CLEAR_R_MUTAB_TXRPT_OFFSET(x) | BIT_R_MUTAB_TXRPT_OFFSET(v)) -#define BIT_SHIFT_RTS_MAX_AGG_NUM 24 -#define BIT_MASK_RTS_MAX_AGG_NUM 0x3f -#define BIT_RTS_MAX_AGG_NUM(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM) -#define BIT_GET_RTS_MAX_AGG_NUM(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM) +#endif +#if (HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MAX_AGG_NUM 16 -#define BIT_MASK_MAX_AGG_NUM 0x3f -#define BIT_MAX_AGG_NUM(x) (((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM) -#define BIT_GET_MAX_AGG_NUM(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_MACID_MURATE_OFFSET 24 +#define BIT_MASK_MACID_MURATE_OFFSET 0xff +#define BIT_MACID_MURATE_OFFSET(x) \ + (((x) & BIT_MASK_MACID_MURATE_OFFSET) << BIT_SHIFT_MACID_MURATE_OFFSET) +#define BITS_MACID_MURATE_OFFSET \ + (BIT_MASK_MACID_MURATE_OFFSET << BIT_SHIFT_MACID_MURATE_OFFSET) +#define BIT_CLEAR_MACID_MURATE_OFFSET(x) ((x) & (~BITS_MACID_MURATE_OFFSET)) +#define BIT_GET_MACID_MURATE_OFFSET(x) \ + (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET) & BIT_MASK_MACID_MURATE_OFFSET) +#define BIT_SET_MACID_MURATE_OFFSET(x, v) \ + (BIT_CLEAR_MACID_MURATE_OFFSET(x) | BIT_MACID_MURATE_OFFSET(v)) -#define BIT_SHIFT_RTS_TXTIME_TH 8 -#define BIT_MASK_RTS_TXTIME_TH 0xff -#define BIT_RTS_TXTIME_TH(x) (((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH) -#define BIT_GET_RTS_TXTIME_TH(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH) +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RTS_LEN_TH 0 -#define BIT_MASK_RTS_LEN_TH 0xff -#define BIT_RTS_LEN_TH(x) (((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH) -#define BIT_GET_RTS_LEN_TH(x) (((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_TXRPT_MISS_COUNT 17 +#define BIT_MASK_TXRPT_MISS_COUNT 0x7 +#define BIT_TXRPT_MISS_COUNT(x) \ + (((x) & BIT_MASK_TXRPT_MISS_COUNT) << BIT_SHIFT_TXRPT_MISS_COUNT) +#define BITS_TXRPT_MISS_COUNT \ + (BIT_MASK_TXRPT_MISS_COUNT << BIT_SHIFT_TXRPT_MISS_COUNT) +#define BIT_CLEAR_TXRPT_MISS_COUNT(x) ((x) & (~BITS_TXRPT_MISS_COUNT)) +#define BIT_GET_TXRPT_MISS_COUNT(x) \ + (((x) >> BIT_SHIFT_TXRPT_MISS_COUNT) & BIT_MASK_TXRPT_MISS_COUNT) +#define BIT_SET_TXRPT_MISS_COUNT(x, v) \ + (BIT_CLEAR_TXRPT_MISS_COUNT(x) | BIT_TXRPT_MISS_COUNT(v)) -/* 2 REG_BAR_MODE_CTRL (Offset 0x04CC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BAR_RTY_LMT 16 -#define BIT_MASK_BAR_RTY_LMT 0x3 -#define BIT_BAR_RTY_LMT(x) (((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT) -#define BIT_GET_BAR_RTY_LMT(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_LOC_BCN_RPT 16 +#define BIT_MASK_LOC_BCN_RPT 0xff +#define BIT_LOC_BCN_RPT(x) \ + (((x) & BIT_MASK_LOC_BCN_RPT) << BIT_SHIFT_LOC_BCN_RPT) +#define BITS_LOC_BCN_RPT (BIT_MASK_LOC_BCN_RPT << BIT_SHIFT_LOC_BCN_RPT) +#define BIT_CLEAR_LOC_BCN_RPT(x) ((x) & (~BITS_LOC_BCN_RPT)) +#define BIT_GET_LOC_BCN_RPT(x) \ + (((x) >> BIT_SHIFT_LOC_BCN_RPT) & BIT_MASK_LOC_BCN_RPT) +#define BIT_SET_LOC_BCN_RPT(x, v) \ + (BIT_CLEAR_LOC_BCN_RPT(x) | BIT_LOC_BCN_RPT(v)) -#define BIT_SHIFT_BAR_PKT_TXTIME_TH 8 -#define BIT_MASK_BAR_PKT_TXTIME_TH 0xff -#define BIT_BAR_PKT_TXTIME_TH(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH) << BIT_SHIFT_BAR_PKT_TXTIME_TH) -#define BIT_GET_BAR_PKT_TXTIME_TH(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH) & BIT_MASK_BAR_PKT_TXTIME_TH) +#endif -#define BIT_BAR_EN_V1 BIT(6) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT) -#define BIT_SHIFT_BAR_PKTNUM_TH_V1 0 -#define BIT_MASK_BAR_PKTNUM_TH_V1 0x3f -#define BIT_BAR_PKTNUM_TH_V1(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1) -#define BIT_GET_BAR_PKTNUM_TH_V1(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT__R_RPTFIFO_1K BIT(16) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_MACID_SHCUT_OFFSET 16 +#define BIT_MASK_MACID_SHCUT_OFFSET 0xff +#define BIT_MACID_SHCUT_OFFSET(x) \ + (((x) & BIT_MASK_MACID_SHCUT_OFFSET) << BIT_SHIFT_MACID_SHCUT_OFFSET) +#define BITS_MACID_SHCUT_OFFSET \ + (BIT_MASK_MACID_SHCUT_OFFSET << BIT_SHIFT_MACID_SHCUT_OFFSET) +#define BIT_CLEAR_MACID_SHCUT_OFFSET(x) ((x) & (~BITS_MACID_SHCUT_OFFSET)) +#define BIT_GET_MACID_SHCUT_OFFSET(x) \ + (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET) & BIT_MASK_MACID_SHCUT_OFFSET) +#define BIT_SET_MACID_SHCUT_OFFSET(x, v) \ + (BIT_CLEAR_MACID_SHCUT_OFFSET(x) | BIT_MACID_SHCUT_OFFSET(v)) -/* 2 REG_RA_TRY_RATE_AGG_LMT (Offset 0x04CF) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1 0 -#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 0x3f -#define BIT_RA_TRY_RATE_AGG_LMT_V1(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) -#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_MACID_CTRL_OFFSET_V1 16 +#define BIT_MASK_MACID_CTRL_OFFSET_V1 0x1ff +#define BIT_MACID_CTRL_OFFSET_V1(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET_V1) \ + << BIT_SHIFT_MACID_CTRL_OFFSET_V1) +#define BITS_MACID_CTRL_OFFSET_V1 \ + (BIT_MASK_MACID_CTRL_OFFSET_V1 << BIT_SHIFT_MACID_CTRL_OFFSET_V1) +#define BIT_CLEAR_MACID_CTRL_OFFSET_V1(x) ((x) & (~BITS_MACID_CTRL_OFFSET_V1)) +#define BIT_GET_MACID_CTRL_OFFSET_V1(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_V1) & \ + BIT_MASK_MACID_CTRL_OFFSET_V1) +#define BIT_SET_MACID_CTRL_OFFSET_V1(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET_V1(x) | BIT_MACID_CTRL_OFFSET_V1(v)) #endif +#if (HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_RPTFIFO_SIZE_OPT BIT(16) -/* 2 REG_MACID_SLEEP2 (Offset 0x04D0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MACID95_64PKTSLEEP 0 -#define BIT_MASK_MACID95_64PKTSLEEP 0xffffffffL -#define BIT_MACID95_64PKTSLEEP(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP) -#define BIT_GET_MACID95_64PKTSLEEP(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_LOC_TXRPT 8 +#define BIT_MASK_LOC_TXRPT 0xff +#define BIT_LOC_TXRPT(x) (((x) & BIT_MASK_LOC_TXRPT) << BIT_SHIFT_LOC_TXRPT) +#define BITS_LOC_TXRPT (BIT_MASK_LOC_TXRPT << BIT_SHIFT_LOC_TXRPT) +#define BIT_CLEAR_LOC_TXRPT(x) ((x) & (~BITS_LOC_TXRPT)) +#define BIT_GET_LOC_TXRPT(x) (((x) >> BIT_SHIFT_LOC_TXRPT) & BIT_MASK_LOC_TXRPT) +#define BIT_SET_LOC_TXRPT(x, v) (BIT_CLEAR_LOC_TXRPT(x) | BIT_LOC_TXRPT(v)) -/* 2 REG_MACID_SLEEP (Offset 0x04D4) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MACID31_0_PKTSLEEP 0 -#define BIT_MASK_MACID31_0_PKTSLEEP 0xffffffffL -#define BIT_MACID31_0_PKTSLEEP(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP) -#define BIT_GET_MACID31_0_PKTSLEEP(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_MACID_CTRL_OFFSET 8 +#define BIT_MASK_MACID_CTRL_OFFSET 0xff +#define BIT_MACID_CTRL_OFFSET(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET) +#define BITS_MACID_CTRL_OFFSET \ + (BIT_MASK_MACID_CTRL_OFFSET << BIT_SHIFT_MACID_CTRL_OFFSET) +#define BIT_CLEAR_MACID_CTRL_OFFSET(x) ((x) & (~BITS_MACID_CTRL_OFFSET)) +#define BIT_GET_MACID_CTRL_OFFSET(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET) +#define BIT_SET_MACID_CTRL_OFFSET(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET(x) | BIT_MACID_CTRL_OFFSET(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_LOC_SRFF 0 +#define BIT_MASK_LOC_SRFF 0xff +#define BIT_LOC_SRFF(x) (((x) & BIT_MASK_LOC_SRFF) << BIT_SHIFT_LOC_SRFF) +#define BITS_LOC_SRFF (BIT_MASK_LOC_SRFF << BIT_SHIFT_LOC_SRFF) +#define BIT_CLEAR_LOC_SRFF(x) ((x) & (~BITS_LOC_SRFF)) +#define BIT_GET_LOC_SRFF(x) (((x) >> BIT_SHIFT_LOC_SRFF) & BIT_MASK_LOC_SRFF) +#define BIT_SET_LOC_SRFF(x, v) (BIT_CLEAR_LOC_SRFF(x) | BIT_LOC_SRFF(v)) -/* 2 REG_HW_SEQ0 (Offset 0x04D8) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HW_SSN_SEQ0 0 -#define BIT_MASK_HW_SSN_SEQ0 0xfff -#define BIT_HW_SSN_SEQ0(x) (((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0) -#define BIT_GET_HW_SSN_SEQ0(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_AMPDU_TXRPT_OFFSET 0 +#define BIT_MASK_AMPDU_TXRPT_OFFSET 0xff +#define BIT_AMPDU_TXRPT_OFFSET(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET) +#define BITS_AMPDU_TXRPT_OFFSET \ + (BIT_MASK_AMPDU_TXRPT_OFFSET << BIT_SHIFT_AMPDU_TXRPT_OFFSET) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET)) +#define BIT_GET_AMPDU_TXRPT_OFFSET(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET) +#define BIT_SET_AMPDU_TXRPT_OFFSET(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) | BIT_AMPDU_TXRPT_OFFSET(v)) -/* 2 REG_HW_SEQ1 (Offset 0x04DA) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HW_SSN_SEQ1 0 -#define BIT_MASK_HW_SSN_SEQ1 0xfff -#define BIT_HW_SSN_SEQ1(x) (((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1) -#define BIT_GET_HW_SSN_SEQ1(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1 0 +#define BIT_MASK_AMPDU_TXRPT_OFFSET_V1 0x1ff +#define BIT_AMPDU_TXRPT_OFFSET_V1(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_V1) \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1) +#define BITS_AMPDU_TXRPT_OFFSET_V1 \ + (BIT_MASK_AMPDU_TXRPT_OFFSET_V1 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET_V1)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_V1(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1) & \ + BIT_MASK_AMPDU_TXRPT_OFFSET_V1) +#define BIT_SET_AMPDU_TXRPT_OFFSET_V1(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1(x) | BIT_AMPDU_TXRPT_OFFSET_V1(v)) -/* 2 REG_HW_SEQ2 (Offset 0x04DC) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_TRYING_CNT_TH (Offset 0x04B0) */ +#define BIT_SHIFT_INDEX_15 24 +#define BIT_MASK_INDEX_15 0xff +#define BIT_INDEX_15(x) (((x) & BIT_MASK_INDEX_15) << BIT_SHIFT_INDEX_15) +#define BITS_INDEX_15 (BIT_MASK_INDEX_15 << BIT_SHIFT_INDEX_15) +#define BIT_CLEAR_INDEX_15(x) ((x) & (~BITS_INDEX_15)) +#define BIT_GET_INDEX_15(x) (((x) >> BIT_SHIFT_INDEX_15) & BIT_MASK_INDEX_15) +#define BIT_SET_INDEX_15(x, v) (BIT_CLEAR_INDEX_15(x) | BIT_INDEX_15(v)) + +#define BIT_SHIFT_INDEX_14 16 +#define BIT_MASK_INDEX_14 0xff +#define BIT_INDEX_14(x) (((x) & BIT_MASK_INDEX_14) << BIT_SHIFT_INDEX_14) +#define BITS_INDEX_14 (BIT_MASK_INDEX_14 << BIT_SHIFT_INDEX_14) +#define BIT_CLEAR_INDEX_14(x) ((x) & (~BITS_INDEX_14)) +#define BIT_GET_INDEX_14(x) (((x) >> BIT_SHIFT_INDEX_14) & BIT_MASK_INDEX_14) +#define BIT_SET_INDEX_14(x, v) (BIT_CLEAR_INDEX_14(x) | BIT_INDEX_14(v)) + +#define BIT_SHIFT_INDEX_13 8 +#define BIT_MASK_INDEX_13 0xff +#define BIT_INDEX_13(x) (((x) & BIT_MASK_INDEX_13) << BIT_SHIFT_INDEX_13) +#define BITS_INDEX_13 (BIT_MASK_INDEX_13 << BIT_SHIFT_INDEX_13) +#define BIT_CLEAR_INDEX_13(x) ((x) & (~BITS_INDEX_13)) +#define BIT_GET_INDEX_13(x) (((x) >> BIT_SHIFT_INDEX_13) & BIT_MASK_INDEX_13) +#define BIT_SET_INDEX_13(x, v) (BIT_CLEAR_INDEX_13(x) | BIT_INDEX_13(v)) + +#define BIT_SHIFT_INDEX_12 0 +#define BIT_MASK_INDEX_12 0xff +#define BIT_INDEX_12(x) (((x) & BIT_MASK_INDEX_12) << BIT_SHIFT_INDEX_12) +#define BITS_INDEX_12 (BIT_MASK_INDEX_12 << BIT_SHIFT_INDEX_12) +#define BIT_CLEAR_INDEX_12(x) ((x) & (~BITS_INDEX_12)) +#define BIT_GET_INDEX_12(x) (((x) >> BIT_SHIFT_INDEX_12) & BIT_MASK_INDEX_12) +#define BIT_SET_INDEX_12(x, v) (BIT_CLEAR_INDEX_12(x) | BIT_INDEX_12(v)) + +#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT 0 +#define BIT_MASK_RA_TRY_RATE_AGG_LMT 0x1f +#define BIT_RA_TRY_RATE_AGG_LMT(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT) +#define BITS_RA_TRY_RATE_AGG_LMT \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT << BIT_SHIFT_RA_TRY_RATE_AGG_LMT) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT(x) ((x) & (~BITS_RA_TRY_RATE_AGG_LMT)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT) & BIT_MASK_RA_TRY_RATE_AGG_LMT) +#define BIT_SET_RA_TRY_RATE_AGG_LMT(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT(x) | BIT_RA_TRY_RATE_AGG_LMT(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HW_SSN_SEQ2 0 -#define BIT_MASK_HW_SSN_SEQ2 0xfff -#define BIT_HW_SSN_SEQ2(x) (((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2) -#define BIT_GET_HW_SSN_SEQ2(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2) +/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ +#define BIT_PTA_WL_PRI_MASK_CPU_MGQ BIT(31) +#define BIT_PTA_WL_PRI_MASK_BCNQ BIT(30) +#define BIT_PTA_WL_PRI_MASK_HIQ BIT(29) +#define BIT_PTA_WL_PRI_MASK_MGQ BIT(28) +#define BIT_PTA_WL_PRI_MASK_BK BIT(27) +#define BIT_PTA_WL_PRI_MASK_BE BIT(26) +#define BIT_PTA_WL_PRI_MASK_VI BIT(25) +#define BIT_PTA_WL_PRI_MASK_VO BIT(24) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ +#define BIT_SHIFT_POWER_STAGE1 0 +#define BIT_MASK_POWER_STAGE1 0xffffff +#define BIT_POWER_STAGE1(x) \ + (((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1) +#define BITS_POWER_STAGE1 (BIT_MASK_POWER_STAGE1 << BIT_SHIFT_POWER_STAGE1) +#define BIT_CLEAR_POWER_STAGE1(x) ((x) & (~BITS_POWER_STAGE1)) +#define BIT_GET_POWER_STAGE1(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1) +#define BIT_SET_POWER_STAGE1(x, v) \ + (BIT_CLEAR_POWER_STAGE1(x) | BIT_POWER_STAGE1(v)) -/* 2 REG_HW_SEQ3 (Offset 0x04DE) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_CSI_HWSSN_SEL 12 -#define BIT_MASK_CSI_HWSSN_SEL 0x3 -#define BIT_CSI_HWSSN_SEL(x) (((x) & BIT_MASK_CSI_HWSSN_SEL) << BIT_SHIFT_CSI_HWSSN_SEL) -#define BIT_GET_CSI_HWSSN_SEL(x) (((x) >> BIT_SHIFT_CSI_HWSSN_SEL) & BIT_MASK_CSI_HWSSN_SEL) +/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ +#define BIT__R_CTRL_PKT_POW_ADJ BIT(24) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ +#define BIT__CTRL_PKT_POW_ADJ BIT(24) -/* 2 REG_HW_SEQ3 (Offset 0x04DE) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HW_SSN_SEQ3 0 -#define BIT_MASK_HW_SSN_SEQ3 0xfff -#define BIT_HW_SSN_SEQ3(x) (((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3) -#define BIT_GET_HW_SSN_SEQ3(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3) +/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ +#define BIT_SHIFT_POWER_STAGE2 0 +#define BIT_MASK_POWER_STAGE2 0xffffff +#define BIT_POWER_STAGE2(x) \ + (((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2) +#define BITS_POWER_STAGE2 (BIT_MASK_POWER_STAGE2 << BIT_SHIFT_POWER_STAGE2) +#define BIT_CLEAR_POWER_STAGE2(x) ((x) & (~BITS_POWER_STAGE2)) +#define BIT_GET_POWER_STAGE2(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2) +#define BIT_SET_POWER_STAGE2(x, v) \ + (BIT_CLEAR_POWER_STAGE2(x) | BIT_POWER_STAGE2(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_SHIFT_PAD_NUM_THRES 24 +#define BIT_MASK_PAD_NUM_THRES 0x3f +#define BIT_PAD_NUM_THRES(x) \ + (((x) & BIT_MASK_PAD_NUM_THRES) << BIT_SHIFT_PAD_NUM_THRES) +#define BITS_PAD_NUM_THRES (BIT_MASK_PAD_NUM_THRES << BIT_SHIFT_PAD_NUM_THRES) +#define BIT_CLEAR_PAD_NUM_THRES(x) ((x) & (~BITS_PAD_NUM_THRES)) +#define BIT_GET_PAD_NUM_THRES(x) \ + (((x) >> BIT_SHIFT_PAD_NUM_THRES) & BIT_MASK_PAD_NUM_THRES) +#define BIT_SET_PAD_NUM_THRES(x, v) \ + (BIT_CLEAR_PAD_NUM_THRES(x) | BIT_PAD_NUM_THRES(v)) -/* 2 REG_CSI_SEQ (Offset 0x04DE) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HW_CSI_SEQ 0 -#define BIT_MASK_HW_CSI_SEQ 0xfff -#define BIT_HW_CSI_SEQ(x) (((x) & BIT_MASK_HW_CSI_SEQ) << BIT_SHIFT_HW_CSI_SEQ) -#define BIT_GET_HW_CSI_SEQ(x) (((x) >> BIT_SHIFT_HW_CSI_SEQ) & BIT_MASK_HW_CSI_SEQ) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_R_DMA_THIS_QUEUE_BK BIT(23) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_DMA_THIS_QUEUE_BK BIT(23) -/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PTCL_TOTAL_PG_V1 2 -#define BIT_MASK_PTCL_TOTAL_PG_V1 0x1fff -#define BIT_PTCL_TOTAL_PG_V1(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V1) << BIT_SHIFT_PTCL_TOTAL_PG_V1) -#define BIT_GET_PTCL_TOTAL_PG_V1(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1) & BIT_MASK_PTCL_TOTAL_PG_V1) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_R_DMA_THIS_QUEUE_BE BIT(22) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_DMA_THIS_QUEUE_BE BIT(22) -/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PTCL_TOTAL_PG_V2 2 -#define BIT_MASK_PTCL_TOTAL_PG_V2 0x3fff -#define BIT_PTCL_TOTAL_PG_V2(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2) << BIT_SHIFT_PTCL_TOTAL_PG_V2) -#define BIT_GET_PTCL_TOTAL_PG_V2(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2) & BIT_MASK_PTCL_TOTAL_PG_V2) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_R_DMA_THIS_QUEUE_VI BIT(21) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_NULL_PKT_STATUS (Offset 0x04E0) */ +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ -#define BIT_TX_NULL_1 BIT(1) -#define BIT_TX_NULL_0 BIT(0) +#define BIT_DMA_THIS_QUEUE_VI BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_R_DMA_THIS_QUEUE_VO BIT(20) -/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#endif -#define BIT_PTCL_RATE_TABLE_INVALID BIT(7) -#define BIT_FTM_T2R_ERROR BIT(6) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_DMA_THIS_QUEUE_VO BIT(20) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ -#define BIT_PTCL_ERR0 BIT(5) -#define BIT_PTCL_ERR1 BIT(4) -#define BIT_PTCL_ERR2 BIT(3) -#define BIT_PTCL_ERR3 BIT(2) -#define BIT_PTCL_ERR4 BIT(1) -#define BIT_PTCL_ERR5 BIT(0) +#define BIT_SHIFT_R_TOTAL_LEN_TH 8 +#define BIT_MASK_R_TOTAL_LEN_TH 0xfff +#define BIT_R_TOTAL_LEN_TH(x) \ + (((x) & BIT_MASK_R_TOTAL_LEN_TH) << BIT_SHIFT_R_TOTAL_LEN_TH) +#define BITS_R_TOTAL_LEN_TH \ + (BIT_MASK_R_TOTAL_LEN_TH << BIT_SHIFT_R_TOTAL_LEN_TH) +#define BIT_CLEAR_R_TOTAL_LEN_TH(x) ((x) & (~BITS_R_TOTAL_LEN_TH)) +#define BIT_GET_R_TOTAL_LEN_TH(x) \ + (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH) & BIT_MASK_R_TOTAL_LEN_TH) +#define BIT_SET_R_TOTAL_LEN_TH(x, v) \ + (BIT_CLEAR_R_TOTAL_LEN_TH(x) | BIT_R_TOTAL_LEN_TH(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_SHIFT_TOTAL_LEN_TH 8 +#define BIT_MASK_TOTAL_LEN_TH 0xfff +#define BIT_TOTAL_LEN_TH(x) \ + (((x) & BIT_MASK_TOTAL_LEN_TH) << BIT_SHIFT_TOTAL_LEN_TH) +#define BITS_TOTAL_LEN_TH (BIT_MASK_TOTAL_LEN_TH << BIT_SHIFT_TOTAL_LEN_TH) +#define BIT_CLEAR_TOTAL_LEN_TH(x) ((x) & (~BITS_TOTAL_LEN_TH)) +#define BIT_GET_TOTAL_LEN_TH(x) \ + (((x) >> BIT_SHIFT_TOTAL_LEN_TH) & BIT_MASK_TOTAL_LEN_TH) +#define BIT_SET_TOTAL_LEN_TH(x, v) \ + (BIT_CLEAR_TOTAL_LEN_TH(x) | BIT_TOTAL_LEN_TH(v)) -/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ +#endif -#define BIT_CLI3_TX_NULL_1 BIT(7) -#define BIT_CLI3_TX_NULL_0 BIT(6) -#define BIT_CLI2_TX_NULL_1 BIT(5) -#define BIT_CLI2_TX_NULL_0 BIT(4) -#define BIT_CLI1_TX_NULL_1 BIT(3) -#define BIT_CLI1_TX_NULL_0 BIT(2) -#define BIT_CLI0_TX_NULL_1 BIT(1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_EN_NEW_EARLY BIT(7) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_PTCL_PKT_NUM (Offset 0x04E3) */ +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_PRE_TX_CMD BIT(6) -#define BIT_SHIFT_PTCL_TOTAL_PG 0 -#define BIT_MASK_PTCL_TOTAL_PG 0xff -#define BIT_PTCL_TOTAL_PG(x) (((x) & BIT_MASK_PTCL_TOTAL_PG) << BIT_SHIFT_PTCL_TOTAL_PG) -#define BIT_GET_PTCL_TOTAL_PG(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG) & BIT_MASK_PTCL_TOTAL_PG) +#define BIT_SHIFT_NUM_SCL_EN 4 +#define BIT_MASK_NUM_SCL_EN 0x3 +#define BIT_NUM_SCL_EN(x) (((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN) +#define BITS_NUM_SCL_EN (BIT_MASK_NUM_SCL_EN << BIT_SHIFT_NUM_SCL_EN) +#define BIT_CLEAR_NUM_SCL_EN(x) ((x) & (~BITS_NUM_SCL_EN)) +#define BIT_GET_NUM_SCL_EN(x) \ + (((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN) +#define BIT_SET_NUM_SCL_EN(x, v) (BIT_CLEAR_NUM_SCL_EN(x) | BIT_NUM_SCL_EN(v)) +#define BIT_BK_EN BIT(3) +#define BIT_BE_EN BIT(2) +#define BIT_VI_EN BIT(1) +#define BIT_VO_EN BIT(0) -#endif +/* 2 REG_PKT_LIFE_TIME (Offset 0x04C0) */ +#define BIT_SHIFT_PKT_LIFTIME_BEBK 16 +#define BIT_MASK_PKT_LIFTIME_BEBK 0xffff +#define BIT_PKT_LIFTIME_BEBK(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK) +#define BITS_PKT_LIFTIME_BEBK \ + (BIT_MASK_PKT_LIFTIME_BEBK << BIT_SHIFT_PKT_LIFTIME_BEBK) +#define BIT_CLEAR_PKT_LIFTIME_BEBK(x) ((x) & (~BITS_PKT_LIFTIME_BEBK)) +#define BIT_GET_PKT_LIFTIME_BEBK(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK) +#define BIT_SET_PKT_LIFTIME_BEBK(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_BEBK(x) | BIT_PKT_LIFTIME_BEBK(v)) + +#define BIT_SHIFT_PKT_LIFTIME_VOVI 0 +#define BIT_MASK_PKT_LIFTIME_VOVI 0xffff +#define BIT_PKT_LIFTIME_VOVI(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI) +#define BITS_PKT_LIFTIME_VOVI \ + (BIT_MASK_PKT_LIFTIME_VOVI << BIT_SHIFT_PKT_LIFTIME_VOVI) +#define BIT_CLEAR_PKT_LIFTIME_VOVI(x) ((x) & (~BITS_PKT_LIFTIME_VOVI)) +#define BIT_GET_PKT_LIFTIME_VOVI(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI) +#define BIT_SET_PKT_LIFTIME_VOVI(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_VOVI(x) | BIT_PKT_LIFTIME_VOVI(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_STBC_SETTING (Offset 0x04C4) */ +#define BIT_SHIFT_CDEND_TXTIME_L 4 +#define BIT_MASK_CDEND_TXTIME_L 0xf +#define BIT_CDEND_TXTIME_L(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L) +#define BITS_CDEND_TXTIME_L \ + (BIT_MASK_CDEND_TXTIME_L << BIT_SHIFT_CDEND_TXTIME_L) +#define BIT_CLEAR_CDEND_TXTIME_L(x) ((x) & (~BITS_CDEND_TXTIME_L)) +#define BIT_GET_CDEND_TXTIME_L(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L) +#define BIT_SET_CDEND_TXTIME_L(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_L(x) | BIT_CDEND_TXTIME_L(v)) + +#define BIT_SHIFT_NESS 2 +#define BIT_MASK_NESS 0x3 +#define BIT_NESS(x) (((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS) +#define BITS_NESS (BIT_MASK_NESS << BIT_SHIFT_NESS) +#define BIT_CLEAR_NESS(x) ((x) & (~BITS_NESS)) +#define BIT_GET_NESS(x) (((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS) +#define BIT_SET_NESS(x, v) (BIT_CLEAR_NESS(x) | BIT_NESS(v)) + +#define BIT_SHIFT_STBC_CFEND 0 +#define BIT_MASK_STBC_CFEND 0x3 +#define BIT_STBC_CFEND(x) (((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND) +#define BITS_STBC_CFEND (BIT_MASK_STBC_CFEND << BIT_SHIFT_STBC_CFEND) +#define BIT_CLEAR_STBC_CFEND(x) ((x) & (~BITS_STBC_CFEND)) +#define BIT_GET_STBC_CFEND(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND) +#define BIT_SET_STBC_CFEND(x, v) (BIT_CLEAR_STBC_CFEND(x) | BIT_STBC_CFEND(v)) -/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ +/* 2 REG_STBC_SETTING2 (Offset 0x04C5) */ -#define BIT_CLI0_TX_NULL_0 BIT(0) +#define BIT_SHIFT_CDEND_TXTIME_H 0 +#define BIT_MASK_CDEND_TXTIME_H 0x1f +#define BIT_CDEND_TXTIME_H(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H) +#define BITS_CDEND_TXTIME_H \ + (BIT_MASK_CDEND_TXTIME_H << BIT_SHIFT_CDEND_TXTIME_H) +#define BIT_CLEAR_CDEND_TXTIME_H(x) ((x) & (~BITS_CDEND_TXTIME_H)) +#define BIT_GET_CDEND_TXTIME_H(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H) +#define BIT_SET_CDEND_TXTIME_H(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_H(x) | BIT_CDEND_TXTIME_H(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ +#define BIT_FORCE_RND_PRI BIT(6) -/* 2 REG_TRXRPT_MISS_CNT (Offset 0x04E3) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TRXRPT_MISS_CNT 0 -#define BIT_MASK_TRXRPT_MISS_CNT 0x7 -#define BIT_TRXRPT_MISS_CNT(x) (((x) & BIT_MASK_TRXRPT_MISS_CNT) << BIT_SHIFT_TRXRPT_MISS_CNT) -#define BIT_GET_TRXRPT_MISS_CNT(x) (((x) >> BIT_SHIFT_TRXRPT_MISS_CNT) & BIT_MASK_TRXRPT_MISS_CNT) +/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ +#define BIT_PTA_EDCCA_EN BIT(5) +#define BIT_PTA_WL_TX_EN BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ +#define BIT_R_USE_DATA_BW BIT(3) -/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ +#endif -#define BIT_VIDEO_JUST_DROP BIT(1) -#define BIT_VIDEO_ENHANCEMENT_FUN_EN BIT(0) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ +#define BIT_USE_DATA_BW BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_BT_POLLUTE_PKT_CNT (Offset 0x04E8) */ +/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ +#define BIT_TRI_PKT_INT_MODE1 BIT(2) +#define BIT_TRI_PKT_INT_MODE0 BIT(1) +#define BIT_ACQ_MODE_SEL BIT(0) -#define BIT_SHIFT_BT_POLLUTE_PKT_CNT 0 -#define BIT_MASK_BT_POLLUTE_PKT_CNT 0xffff -#define BIT_BT_POLLUTE_PKT_CNT(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT) -#define BIT_GET_BT_POLLUTE_PKT_CNT(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT) +/* 2 REG_SINGLE_AMPDU_CTRL (Offset 0x04C7) */ +#define BIT_EN_SINGLE_APMDU BIT(7) -/* 2 REG_PTCL_DBG (Offset 0x04EC) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PTCL_DBG 0 -#define BIT_MASK_PTCL_DBG 0xffffffffL -#define BIT_PTCL_DBG(x) (((x) & BIT_MASK_PTCL_DBG) << BIT_SHIFT_PTCL_DBG) -#define BIT_GET_PTCL_DBG(x) (((x) >> BIT_SHIFT_PTCL_DBG) & BIT_MASK_PTCL_DBG) +/* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */ +#define BIT_SND_SIFS_TXDATA BIT(31) +#define BIT_TX_SND_MATCH_MACID BIT(30) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */ +#define BIT_SHIFT_RTS_MAX_AGG_NUM 24 +#define BIT_MASK_RTS_MAX_AGG_NUM 0x3f +#define BIT_RTS_MAX_AGG_NUM(x) \ + (((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM) +#define BITS_RTS_MAX_AGG_NUM \ + (BIT_MASK_RTS_MAX_AGG_NUM << BIT_SHIFT_RTS_MAX_AGG_NUM) +#define BIT_CLEAR_RTS_MAX_AGG_NUM(x) ((x) & (~BITS_RTS_MAX_AGG_NUM)) +#define BIT_GET_RTS_MAX_AGG_NUM(x) \ + (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM) +#define BIT_SET_RTS_MAX_AGG_NUM(x, v) \ + (BIT_CLEAR_RTS_MAX_AGG_NUM(x) | BIT_RTS_MAX_AGG_NUM(v)) + +#define BIT_SHIFT_MAX_AGG_NUM 16 +#define BIT_MASK_MAX_AGG_NUM 0x3f +#define BIT_MAX_AGG_NUM(x) \ + (((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM) +#define BITS_MAX_AGG_NUM (BIT_MASK_MAX_AGG_NUM << BIT_SHIFT_MAX_AGG_NUM) +#define BIT_CLEAR_MAX_AGG_NUM(x) ((x) & (~BITS_MAX_AGG_NUM)) +#define BIT_GET_MAX_AGG_NUM(x) \ + (((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM) +#define BIT_SET_MAX_AGG_NUM(x, v) \ + (BIT_CLEAR_MAX_AGG_NUM(x) | BIT_MAX_AGG_NUM(v)) + +#define BIT_SHIFT_RTS_TXTIME_TH 8 +#define BIT_MASK_RTS_TXTIME_TH 0xff +#define BIT_RTS_TXTIME_TH(x) \ + (((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH) +#define BITS_RTS_TXTIME_TH (BIT_MASK_RTS_TXTIME_TH << BIT_SHIFT_RTS_TXTIME_TH) +#define BIT_CLEAR_RTS_TXTIME_TH(x) ((x) & (~BITS_RTS_TXTIME_TH)) +#define BIT_GET_RTS_TXTIME_TH(x) \ + (((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH) +#define BIT_SET_RTS_TXTIME_TH(x, v) \ + (BIT_CLEAR_RTS_TXTIME_TH(x) | BIT_RTS_TXTIME_TH(v)) + +#define BIT_SHIFT_RTS_LEN_TH 0 +#define BIT_MASK_RTS_LEN_TH 0xff +#define BIT_RTS_LEN_TH(x) (((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH) +#define BITS_RTS_LEN_TH (BIT_MASK_RTS_LEN_TH << BIT_SHIFT_RTS_LEN_TH) +#define BIT_CLEAR_RTS_LEN_TH(x) ((x) & (~BITS_RTS_LEN_TH)) +#define BIT_GET_RTS_LEN_TH(x) \ + (((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH) +#define BIT_SET_RTS_LEN_TH(x, v) (BIT_CLEAR_RTS_LEN_TH(x) | BIT_RTS_LEN_TH(v)) -/* 2 REG_PTCL_TX_RPT (Offset 0x04F0) */ +/* 2 REG_BAR_MODE_CTRL (Offset 0x04CC) */ +#define BIT_SHIFT_BAR_RTY_LMT 16 +#define BIT_MASK_BAR_RTY_LMT 0x3 +#define BIT_BAR_RTY_LMT(x) \ + (((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT) +#define BITS_BAR_RTY_LMT (BIT_MASK_BAR_RTY_LMT << BIT_SHIFT_BAR_RTY_LMT) +#define BIT_CLEAR_BAR_RTY_LMT(x) ((x) & (~BITS_BAR_RTY_LMT)) +#define BIT_GET_BAR_RTY_LMT(x) \ + (((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT) +#define BIT_SET_BAR_RTY_LMT(x, v) \ + (BIT_CLEAR_BAR_RTY_LMT(x) | BIT_BAR_RTY_LMT(v)) + +#define BIT_SHIFT_BAR_PKT_TXTIME_TH 8 +#define BIT_MASK_BAR_PKT_TXTIME_TH 0xff +#define BIT_BAR_PKT_TXTIME_TH(x) \ + (((x) & BIT_MASK_BAR_PKT_TXTIME_TH) << BIT_SHIFT_BAR_PKT_TXTIME_TH) +#define BITS_BAR_PKT_TXTIME_TH \ + (BIT_MASK_BAR_PKT_TXTIME_TH << BIT_SHIFT_BAR_PKT_TXTIME_TH) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH(x) ((x) & (~BITS_BAR_PKT_TXTIME_TH)) +#define BIT_GET_BAR_PKT_TXTIME_TH(x) \ + (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH) & BIT_MASK_BAR_PKT_TXTIME_TH) +#define BIT_SET_BAR_PKT_TXTIME_TH(x, v) \ + (BIT_CLEAR_BAR_PKT_TXTIME_TH(x) | BIT_BAR_PKT_TXTIME_TH(v)) + +#define BIT_BAR_EN_V1 BIT(6) + +#define BIT_SHIFT_BAR_PKTNUM_TH_V1 0 +#define BIT_MASK_BAR_PKTNUM_TH_V1 0x3f +#define BIT_BAR_PKTNUM_TH_V1(x) \ + (((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1) +#define BITS_BAR_PKTNUM_TH_V1 \ + (BIT_MASK_BAR_PKTNUM_TH_V1 << BIT_SHIFT_BAR_PKTNUM_TH_V1) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1(x) ((x) & (~BITS_BAR_PKTNUM_TH_V1)) +#define BIT_GET_BAR_PKTNUM_TH_V1(x) \ + (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1) +#define BIT_SET_BAR_PKTNUM_TH_V1(x, v) \ + (BIT_CLEAR_BAR_PKTNUM_TH_V1(x) | BIT_BAR_PKTNUM_TH_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AC_TX_RPT_INFO 0 -#define BIT_MASK_AC_TX_RPT_INFO 0xffffffffffffffffL -#define BIT_AC_TX_RPT_INFO(x) (((x) & BIT_MASK_AC_TX_RPT_INFO) << BIT_SHIFT_AC_TX_RPT_INFO) -#define BIT_GET_AC_TX_RPT_INFO(x) (((x) >> BIT_SHIFT_AC_TX_RPT_INFO) & BIT_MASK_AC_TX_RPT_INFO) +/* 2 REG_RA_TRY_RATE_AGG_LMT (Offset 0x04CF) */ +#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1 0 +#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 0x3f +#define BIT_RA_TRY_RATE_AGG_LMT_V1(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) +#define BITS_RA_TRY_RATE_AGG_LMT_V1 \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1(x) \ + ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) & \ + BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1(x) | BIT_RA_TRY_RATE_AGG_LMT_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_MACID_SLEEP_CTRL (Offset 0x04D0) */ + +#define BIT_SHIFT_DEBUG_PROTOCOL 24 +#define BIT_MASK_DEBUG_PROTOCOL 0xff +#define BIT_DEBUG_PROTOCOL(x) \ + (((x) & BIT_MASK_DEBUG_PROTOCOL) << BIT_SHIFT_DEBUG_PROTOCOL) +#define BITS_DEBUG_PROTOCOL \ + (BIT_MASK_DEBUG_PROTOCOL << BIT_SHIFT_DEBUG_PROTOCOL) +#define BIT_CLEAR_DEBUG_PROTOCOL(x) ((x) & (~BITS_DEBUG_PROTOCOL)) +#define BIT_GET_DEBUG_PROTOCOL(x) \ + (((x) >> BIT_SHIFT_DEBUG_PROTOCOL) & BIT_MASK_DEBUG_PROTOCOL) +#define BIT_SET_DEBUG_PROTOCOL(x, v) \ + (BIT_CLEAR_DEBUG_PROTOCOL(x) | BIT_DEBUG_PROTOCOL(v)) + +#define BIT_SHIFT_BCNQ_PGBNDY_RSEL 16 +#define BIT_MASK_BCNQ_PGBNDY_RSEL 0x7 +#define BIT_BCNQ_PGBNDY_RSEL(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_RSEL) << BIT_SHIFT_BCNQ_PGBNDY_RSEL) +#define BITS_BCNQ_PGBNDY_RSEL \ + (BIT_MASK_BCNQ_PGBNDY_RSEL << BIT_SHIFT_BCNQ_PGBNDY_RSEL) +#define BIT_CLEAR_BCNQ_PGBNDY_RSEL(x) ((x) & (~BITS_BCNQ_PGBNDY_RSEL)) +#define BIT_GET_BCNQ_PGBNDY_RSEL(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RSEL) & BIT_MASK_BCNQ_PGBNDY_RSEL) +#define BIT_SET_BCNQ_PGBNDY_RSEL(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_RSEL(x) | BIT_BCNQ_PGBNDY_RSEL(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_MACID_SLEEP2 (Offset 0x04D0) */ +#define BIT_SHIFT_MACID95_64PKTSLEEP 0 +#define BIT_MASK_MACID95_64PKTSLEEP 0xffffffffL +#define BIT_MACID95_64PKTSLEEP(x) \ + (((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP) +#define BITS_MACID95_64PKTSLEEP \ + (BIT_MASK_MACID95_64PKTSLEEP << BIT_SHIFT_MACID95_64PKTSLEEP) +#define BIT_CLEAR_MACID95_64PKTSLEEP(x) ((x) & (~BITS_MACID95_64PKTSLEEP)) +#define BIT_GET_MACID95_64PKTSLEEP(x) \ + (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP) +#define BIT_SET_MACID95_64PKTSLEEP(x, v) \ + (BIT_CLEAR_MACID95_64PKTSLEEP(x) | BIT_MACID95_64PKTSLEEP(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_TXOP_EXTRA_CTRL (Offset 0x04F0) */ +/* 2 REG_MACID_SLEEP_CTRL (Offset 0x04D0) */ -#define BIT_TXOP_EFFICIENCY_EN BIT(0) +#define BIT_SHIFT_MACID_SLEEP_SEL 0 +#define BIT_MASK_MACID_SLEEP_SEL 0x7 +#define BIT_MACID_SLEEP_SEL(x) \ + (((x) & BIT_MASK_MACID_SLEEP_SEL) << BIT_SHIFT_MACID_SLEEP_SEL) +#define BITS_MACID_SLEEP_SEL \ + (BIT_MASK_MACID_SLEEP_SEL << BIT_SHIFT_MACID_SLEEP_SEL) +#define BIT_CLEAR_MACID_SLEEP_SEL(x) ((x) & (~BITS_MACID_SLEEP_SEL)) +#define BIT_GET_MACID_SLEEP_SEL(x) \ + (((x) >> BIT_SHIFT_MACID_SLEEP_SEL) & BIT_MASK_MACID_SLEEP_SEL) +#define BIT_SET_MACID_SLEEP_SEL(x, v) \ + (BIT_CLEAR_MACID_SLEEP_SEL(x) | BIT_MACID_SLEEP_SEL(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MACID_SLEEP (Offset 0x04D4) */ +#define BIT_SHIFT_MACID31_0_PKTSLEEP 0 +#define BIT_MASK_MACID31_0_PKTSLEEP 0xffffffffL +#define BIT_MACID31_0_PKTSLEEP(x) \ + (((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP) +#define BITS_MACID31_0_PKTSLEEP \ + (BIT_MASK_MACID31_0_PKTSLEEP << BIT_SHIFT_MACID31_0_PKTSLEEP) +#define BIT_CLEAR_MACID31_0_PKTSLEEP(x) ((x) & (~BITS_MACID31_0_PKTSLEEP)) +#define BIT_GET_MACID31_0_PKTSLEEP(x) \ + (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP) +#define BIT_SET_MACID31_0_PKTSLEEP(x, v) \ + (BIT_CLEAR_MACID31_0_PKTSLEEP(x) | BIT_MACID31_0_PKTSLEEP(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_MACID_SLEEP_INFO (Offset 0x04D4) */ + +#define BIT_SHIFT_MACID_SLEEP_INFO 0 +#define BIT_MASK_MACID_SLEEP_INFO 0xffffffffL +#define BIT_MACID_SLEEP_INFO(x) \ + (((x) & BIT_MASK_MACID_SLEEP_INFO) << BIT_SHIFT_MACID_SLEEP_INFO) +#define BITS_MACID_SLEEP_INFO \ + (BIT_MASK_MACID_SLEEP_INFO << BIT_SHIFT_MACID_SLEEP_INFO) +#define BIT_CLEAR_MACID_SLEEP_INFO(x) ((x) & (~BITS_MACID_SLEEP_INFO)) +#define BIT_GET_MACID_SLEEP_INFO(x) \ + (((x) >> BIT_SHIFT_MACID_SLEEP_INFO) & BIT_MASK_MACID_SLEEP_INFO) +#define BIT_SET_MACID_SLEEP_INFO(x, v) \ + (BIT_CLEAR_MACID_SLEEP_INFO(x) | BIT_MACID_SLEEP_INFO(v)) + +#define BIT_SHIFT_PTCL_TOTAL_PG_V3 0 +#define BIT_MASK_PTCL_TOTAL_PG_V3 0x1fff +#define BIT_PTCL_TOTAL_PG_V3(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V3) << BIT_SHIFT_PTCL_TOTAL_PG_V3) +#define BITS_PTCL_TOTAL_PG_V3 \ + (BIT_MASK_PTCL_TOTAL_PG_V3 << BIT_SHIFT_PTCL_TOTAL_PG_V3) +#define BIT_CLEAR_PTCL_TOTAL_PG_V3(x) ((x) & (~BITS_PTCL_TOTAL_PG_V3)) +#define BIT_GET_PTCL_TOTAL_PG_V3(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V3) & BIT_MASK_PTCL_TOTAL_PG_V3) +#define BIT_SET_PTCL_TOTAL_PG_V3(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V3(x) | BIT_PTCL_TOTAL_PG_V3(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_CPUMGQ_TIMER_CTRL2 (Offset 0x04F4) */ +/* 2 REG_HW_SEQ0 (Offset 0x04D8) */ -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME BIT(31) +#define BIT_SHIFT_HW_SSN_SEQ0 0 +#define BIT_MASK_HW_SSN_SEQ0 0xfff +#define BIT_HW_SSN_SEQ0(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0) +#define BITS_HW_SSN_SEQ0 (BIT_MASK_HW_SSN_SEQ0 << BIT_SHIFT_HW_SSN_SEQ0) +#define BIT_CLEAR_HW_SSN_SEQ0(x) ((x) & (~BITS_HW_SSN_SEQ0)) +#define BIT_GET_HW_SSN_SEQ0(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0) +#define BIT_SET_HW_SSN_SEQ0(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ0(x) | BIT_HW_SSN_SEQ0(v)) -#define BIT_SHIFT_GTAB_ID 28 -#define BIT_MASK_GTAB_ID 0x7 -#define BIT_GTAB_ID(x) (((x) & BIT_MASK_GTAB_ID) << BIT_SHIFT_GTAB_ID) -#define BIT_GET_GTAB_ID(x) (((x) >> BIT_SHIFT_GTAB_ID) & BIT_MASK_GTAB_ID) +/* 2 REG_HW_SEQ1 (Offset 0x04DA) */ +#define BIT_SHIFT_HW_SSN_SEQ1 0 +#define BIT_MASK_HW_SSN_SEQ1 0xfff +#define BIT_HW_SSN_SEQ1(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1) +#define BITS_HW_SSN_SEQ1 (BIT_MASK_HW_SSN_SEQ1 << BIT_SHIFT_HW_SSN_SEQ1) +#define BIT_CLEAR_HW_SSN_SEQ1(x) ((x) & (~BITS_HW_SSN_SEQ1)) +#define BIT_GET_HW_SSN_SEQ1(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1) +#define BIT_SET_HW_SSN_SEQ1(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ1(x) | BIT_HW_SSN_SEQ1(v)) -#define BIT_SHIFT_TRI_HEAD_ADDR 16 -#define BIT_MASK_TRI_HEAD_ADDR 0xfff -#define BIT_TRI_HEAD_ADDR(x) (((x) & BIT_MASK_TRI_HEAD_ADDR) << BIT_SHIFT_TRI_HEAD_ADDR) -#define BIT_GET_TRI_HEAD_ADDR(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR) & BIT_MASK_TRI_HEAD_ADDR) +/* 2 REG_HW_SEQ2 (Offset 0x04DC) */ -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1 BIT(15) +#define BIT_SHIFT_HW_SSN_SEQ2 0 +#define BIT_MASK_HW_SSN_SEQ2 0xfff +#define BIT_HW_SSN_SEQ2(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2) +#define BITS_HW_SSN_SEQ2 (BIT_MASK_HW_SSN_SEQ2 << BIT_SHIFT_HW_SSN_SEQ2) +#define BIT_CLEAR_HW_SSN_SEQ2(x) ((x) & (~BITS_HW_SSN_SEQ2)) +#define BIT_GET_HW_SSN_SEQ2(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2) +#define BIT_SET_HW_SSN_SEQ2(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ2(x) | BIT_HW_SSN_SEQ2(v)) -#define BIT_SHIFT_GTAB_ID_V1 12 -#define BIT_MASK_GTAB_ID_V1 0x7 -#define BIT_GTAB_ID_V1(x) (((x) & BIT_MASK_GTAB_ID_V1) << BIT_SHIFT_GTAB_ID_V1) -#define BIT_GET_GTAB_ID_V1(x) (((x) >> BIT_SHIFT_GTAB_ID_V1) & BIT_MASK_GTAB_ID_V1) +#endif -#define BIT_DROP_TH_EN BIT(8) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_DROP_TH 0 -#define BIT_MASK_DROP_TH 0xff -#define BIT_DROP_TH(x) (((x) & BIT_MASK_DROP_TH) << BIT_SHIFT_DROP_TH) -#define BIT_GET_DROP_TH(x) (((x) >> BIT_SHIFT_DROP_TH) & BIT_MASK_DROP_TH) +/* 2 REG_HW_SEQ3 (Offset 0x04DE) */ +#define BIT_SHIFT_CSI_HWSSN_SEL 12 +#define BIT_MASK_CSI_HWSSN_SEL 0x3 +#define BIT_CSI_HWSSN_SEL(x) \ + (((x) & BIT_MASK_CSI_HWSSN_SEL) << BIT_SHIFT_CSI_HWSSN_SEL) +#define BITS_CSI_HWSSN_SEL (BIT_MASK_CSI_HWSSN_SEL << BIT_SHIFT_CSI_HWSSN_SEL) +#define BIT_CLEAR_CSI_HWSSN_SEL(x) ((x) & (~BITS_CSI_HWSSN_SEL)) +#define BIT_GET_CSI_HWSSN_SEL(x) \ + (((x) >> BIT_SHIFT_CSI_HWSSN_SEL) & BIT_MASK_CSI_HWSSN_SEL) +#define BIT_SET_CSI_HWSSN_SEL(x, v) \ + (BIT_CLEAR_CSI_HWSSN_SEL(x) | BIT_CSI_HWSSN_SEL(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_HW_SEQ3 (Offset 0x04DE) */ +#define BIT_SHIFT_CSI_HWSEQ_SEL 12 +#define BIT_MASK_CSI_HWSEQ_SEL 0x3 +#define BIT_CSI_HWSEQ_SEL(x) \ + (((x) & BIT_MASK_CSI_HWSEQ_SEL) << BIT_SHIFT_CSI_HWSEQ_SEL) +#define BITS_CSI_HWSEQ_SEL (BIT_MASK_CSI_HWSEQ_SEL << BIT_SHIFT_CSI_HWSEQ_SEL) +#define BIT_CLEAR_CSI_HWSEQ_SEL(x) ((x) & (~BITS_CSI_HWSEQ_SEL)) +#define BIT_GET_CSI_HWSEQ_SEL(x) \ + (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL) & BIT_MASK_CSI_HWSEQ_SEL) +#define BIT_SET_CSI_HWSEQ_SEL(x, v) \ + (BIT_CLEAR_CSI_HWSEQ_SEL(x) | BIT_CSI_HWSEQ_SEL(v)) -/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#endif -#define BIT_MOREDATA_CTRL2_EN BIT(19) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HW_SEQ3 (Offset 0x04DE) */ +#define BIT_SHIFT_HW_SSN_SEQ3 0 +#define BIT_MASK_HW_SSN_SEQ3 0xfff +#define BIT_HW_SSN_SEQ3(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3) +#define BITS_HW_SSN_SEQ3 (BIT_MASK_HW_SSN_SEQ3 << BIT_SHIFT_HW_SSN_SEQ3) +#define BIT_CLEAR_HW_SSN_SEQ3(x) ((x) & (~BITS_HW_SSN_SEQ3)) +#define BIT_GET_HW_SSN_SEQ3(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3) +#define BIT_SET_HW_SSN_SEQ3(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ3(x) | BIT_HW_SSN_SEQ3(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +/* 2 REG_CSI_SEQ (Offset 0x04DE) */ -#define BIT_MOREDATA_CTRL2_EN_V2 BIT(19) +#define BIT_SHIFT_HW_CSI_SEQ 0 +#define BIT_MASK_HW_CSI_SEQ 0xfff +#define BIT_HW_CSI_SEQ(x) (((x) & BIT_MASK_HW_CSI_SEQ) << BIT_SHIFT_HW_CSI_SEQ) +#define BITS_HW_CSI_SEQ (BIT_MASK_HW_CSI_SEQ << BIT_SHIFT_HW_CSI_SEQ) +#define BIT_CLEAR_HW_CSI_SEQ(x) ((x) & (~BITS_HW_CSI_SEQ)) +#define BIT_GET_HW_CSI_SEQ(x) \ + (((x) >> BIT_SHIFT_HW_CSI_SEQ) & BIT_MASK_HW_CSI_SEQ) +#define BIT_SET_HW_CSI_SEQ(x, v) (BIT_CLEAR_HW_CSI_SEQ(x) | BIT_HW_CSI_SEQ(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ +#define BIT_SHIFT_PTCL_TOTAL_PG_V1 2 +#define BIT_MASK_PTCL_TOTAL_PG_V1 0x1fff +#define BIT_PTCL_TOTAL_PG_V1(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V1) << BIT_SHIFT_PTCL_TOTAL_PG_V1) +#define BITS_PTCL_TOTAL_PG_V1 \ + (BIT_MASK_PTCL_TOTAL_PG_V1 << BIT_SHIFT_PTCL_TOTAL_PG_V1) +#define BIT_CLEAR_PTCL_TOTAL_PG_V1(x) ((x) & (~BITS_PTCL_TOTAL_PG_V1)) +#define BIT_GET_PTCL_TOTAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1) & BIT_MASK_PTCL_TOTAL_PG_V1) +#define BIT_SET_PTCL_TOTAL_PG_V1(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V1(x) | BIT_PTCL_TOTAL_PG_V1(v)) -/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#endif -#define BIT_MOREDATA_CTRL1_EN BIT(18) +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ +#define BIT_SHIFT_PTCL_TOTAL_PG_V2 2 +#define BIT_MASK_PTCL_TOTAL_PG_V2 0x3fff +#define BIT_PTCL_TOTAL_PG_V2(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V2) << BIT_SHIFT_PTCL_TOTAL_PG_V2) +#define BITS_PTCL_TOTAL_PG_V2 \ + (BIT_MASK_PTCL_TOTAL_PG_V2 << BIT_SHIFT_PTCL_TOTAL_PG_V2) +#define BIT_CLEAR_PTCL_TOTAL_PG_V2(x) ((x) & (~BITS_PTCL_TOTAL_PG_V2)) +#define BIT_GET_PTCL_TOTAL_PG_V2(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2) & BIT_MASK_PTCL_TOTAL_PG_V2) +#define BIT_SET_PTCL_TOTAL_PG_V2(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V2(x) | BIT_PTCL_TOTAL_PG_V2(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +/* 2 REG_NULL_PKT_STATUS (Offset 0x04E0) */ -#define BIT_MOREDATA_CTRL1_EN_V2 BIT(18) +#define BIT_TX_NULL_1 BIT(1) +#define BIT_TX_NULL_0 BIT(0) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_MUARB_SEARCH_ERR BIT(14) +#define BIT_MU_BFEN_ERR BIT(12) +#define BIT_NDPA_DROPNULL_ERR BIT(11) +#define BIT_NDPA_DROPPKT_ERR BIT(10) +#define BIT_PTCL_PKYIN_ERR BIT(9) +#define BIT_PTCL_QSELCNL_ERR BIT(8) -/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#endif -#define BIT_EN_BCN_TRXRPT BIT(17) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#define BIT_PTCL_RATE_TABLE_INVALID BIT(7) +#define BIT_FTM_T2R_ERROR BIT(6) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ -#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE BIT(16) +#define BIT_PTCL_ERR0 BIT(5) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_TXTIMEOUT_ERR BIT(5) -/* 2 REG_DUMMY_PAGE4_V1 (Offset 0x04FC) */ +#endif -#define BIT_BCN_EN_EXTHWSEQ BIT(1) -#define BIT_BCN_EN_HWSEQ BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#define BIT_PTCL_ERR1 BIT(4) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_MOREDATA (Offset 0x04FE) */ +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ -#define BIT_MOREDATA_CTRL2_EN_V1 BIT(3) -#define BIT_MOREDATA_CTRL1_EN_V1 BIT(2) -#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1 BIT(0) +#define BIT_NULLPAGE_ERR BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#define BIT_PTCL_ERR2 BIT(3) -/* 2 REG_EDCA_VO_PARAM (Offset 0x0500) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TXOPLIMIT 16 -#define BIT_MASK_TXOPLIMIT 0x7ff -#define BIT_TXOPLIMIT(x) (((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT) -#define BIT_GET_TXOPLIMIT(x) (((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_CONTENTION_ERR BIT(3) -#define BIT_SHIFT_CW 8 -#define BIT_MASK_CW 0xff -#define BIT_CW(x) (((x) & BIT_MASK_CW) << BIT_SHIFT_CW) -#define BIT_GET_CW(x) (((x) >> BIT_SHIFT_CW) & BIT_MASK_CW) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_AIFS 0 -#define BIT_MASK_AIFS 0xff -#define BIT_AIFS(x) (((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS) -#define BIT_GET_AIFS(x) (((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS) +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#define BIT_PTCL_ERR3 BIT(2) -/* 2 REG_BCNTCFG (Offset 0x0510) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCNCW_MAX 12 -#define BIT_MASK_BCNCW_MAX 0xf -#define BIT_BCNCW_MAX(x) (((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX) -#define BIT_GET_BCNCW_MAX(x) (((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_HEADNULL_ERR BIT(2) -#define BIT_SHIFT_BCNCW_MIN 8 -#define BIT_MASK_BCNCW_MIN 0xf -#define BIT_BCNCW_MIN(x) (((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN) -#define BIT_GET_BCNCW_MIN(x) (((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BCNIFS 0 -#define BIT_MASK_BCNIFS 0xff -#define BIT_BCNIFS(x) (((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS) -#define BIT_GET_BCNIFS(x) (((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS) +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#define BIT_PTCL_ERR4 BIT(1) -/* 2 REG_PIFS (Offset 0x0512) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_PIFS 0 -#define BIT_MASK_PIFS 0xff -#define BIT_PIFS(x) (((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS) -#define BIT_GET_PIFS(x) (((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_OVERFLOW_ERR BIT(1) -/* 2 REG_RDG_PIFS (Offset 0x0513) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RDG_PIFS 0 -#define BIT_MASK_RDG_PIFS 0xff -#define BIT_RDG_PIFS(x) (((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS) -#define BIT_GET_RDG_PIFS(x) (((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS) +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#define BIT_PTCL_ERR5 BIT(0) -/* 2 REG_SIFS (Offset 0x0514) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_SIFS_OFDM_TRX 24 -#define BIT_MASK_SIFS_OFDM_TRX 0xff -#define BIT_SIFS_OFDM_TRX(x) (((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX) -#define BIT_GET_SIFS_OFDM_TRX(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_QUEUE_INDEX_ERR BIT(0) -#define BIT_SHIFT_SIFS_CCK_TRX 16 -#define BIT_MASK_SIFS_CCK_TRX 0xff -#define BIT_SIFS_CCK_TRX(x) (((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX) -#define BIT_GET_SIFS_CCK_TRX(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SIFS_OFDM_CTX 8 -#define BIT_MASK_SIFS_OFDM_CTX 0xff -#define BIT_SIFS_OFDM_CTX(x) (((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX) -#define BIT_GET_SIFS_OFDM_CTX(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX) +/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ +#define BIT_CLI3_TX_NULL_1 BIT(7) +#define BIT_CLI3_TX_NULL_0 BIT(6) +#define BIT_CLI2_TX_NULL_1 BIT(5) +#define BIT_CLI2_TX_NULL_0 BIT(4) +#define BIT_CLI1_TX_NULL_1 BIT(3) +#define BIT_CLI1_TX_NULL_0 BIT(2) +#define BIT_CLI0_TX_NULL_1 BIT(1) -#define BIT_SHIFT_SIFS_CCK_CTX 0 -#define BIT_MASK_SIFS_CCK_CTX 0xff -#define BIT_SIFS_CCK_CTX(x) (((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX) -#define BIT_GET_SIFS_CCK_CTX(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_TSFTR_SYN_OFFSET (Offset 0x0518) */ +/* 2 REG_PTCL_PKT_NUM (Offset 0x04E3) */ +#define BIT_SHIFT_PTCL_TOTAL_PG 0 +#define BIT_MASK_PTCL_TOTAL_PG 0xff +#define BIT_PTCL_TOTAL_PG(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG) << BIT_SHIFT_PTCL_TOTAL_PG) +#define BITS_PTCL_TOTAL_PG (BIT_MASK_PTCL_TOTAL_PG << BIT_SHIFT_PTCL_TOTAL_PG) +#define BIT_CLEAR_PTCL_TOTAL_PG(x) ((x) & (~BITS_PTCL_TOTAL_PG)) +#define BIT_GET_PTCL_TOTAL_PG(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG) & BIT_MASK_PTCL_TOTAL_PG) +#define BIT_SET_PTCL_TOTAL_PG(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG(x) | BIT_PTCL_TOTAL_PG(v)) -#define BIT_SHIFT_TSFTR_SNC_OFFSET 0 -#define BIT_MASK_TSFTR_SNC_OFFSET 0xffff -#define BIT_TSFTR_SNC_OFFSET(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET) -#define BIT_GET_TSFTR_SNC_OFFSET(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_AGGR_BREAK_TIME (Offset 0x051A) */ +/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ +#define BIT_CLI0_TX_NULL_0 BIT(0) -#define BIT_SHIFT_AGGR_BK_TIME 0 -#define BIT_MASK_AGGR_BK_TIME 0xff -#define BIT_AGGR_BK_TIME(x) (((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME) -#define BIT_GET_AGGR_BK_TIME(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_SLOT (Offset 0x051B) */ +/* 2 REG_TRXRPT_MISS_CNT (Offset 0x04E3) */ +#define BIT_SHIFT_TRXRPT_MISS_CNT 0 +#define BIT_MASK_TRXRPT_MISS_CNT 0x7 +#define BIT_TRXRPT_MISS_CNT(x) \ + (((x) & BIT_MASK_TRXRPT_MISS_CNT) << BIT_SHIFT_TRXRPT_MISS_CNT) +#define BITS_TRXRPT_MISS_CNT \ + (BIT_MASK_TRXRPT_MISS_CNT << BIT_SHIFT_TRXRPT_MISS_CNT) +#define BIT_CLEAR_TRXRPT_MISS_CNT(x) ((x) & (~BITS_TRXRPT_MISS_CNT)) +#define BIT_GET_TRXRPT_MISS_CNT(x) \ + (((x) >> BIT_SHIFT_TRXRPT_MISS_CNT) & BIT_MASK_TRXRPT_MISS_CNT) +#define BIT_SET_TRXRPT_MISS_CNT(x, v) \ + (BIT_CLEAR_TRXRPT_MISS_CNT(x) | BIT_TRXRPT_MISS_CNT(v)) -#define BIT_SHIFT_SLOT 0 -#define BIT_MASK_SLOT 0xff -#define BIT_SLOT(x) (((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT) -#define BIT_GET_SLOT(x) (((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_TX_PTCL_CTRL (Offset 0x0520) */ +/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ -#define BIT_DIS_EDCCA BIT(15) -#define BIT_DIS_CCA BIT(14) -#define BIT_LSIG_TXOP_TXCMD_NAV BIT(13) -#define BIT_SIFS_BK_EN BIT(12) - -#define BIT_SHIFT_TXQ_NAV_MSK 8 -#define BIT_MASK_TXQ_NAV_MSK 0xf -#define BIT_TXQ_NAV_MSK(x) (((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK) -#define BIT_GET_TXQ_NAV_MSK(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK) - -#define BIT_DIS_CW BIT(7) -#define BIT_NAV_END_TXOP BIT(6) -#define BIT_RDG_END_TXOP BIT(5) -#define BIT_AC_INBCN_HOLD BIT(4) -#define BIT_MGTQ_TXOP_EN BIT(3) -#define BIT_MGTQ_RTSMF_EN BIT(2) -#define BIT_HIQ_RTSMF_EN BIT(1) -#define BIT_BCN_RTSMF_EN BIT(0) +#define BIT_MAX_PRETX_AGGR_EN BIT(19) -/* 2 REG_TXPAUSE (Offset 0x0522) */ +#define BIT_SHIFT_MAX_PRETX_AGGR_TIME 8 +#define BIT_MASK_MAX_PRETX_AGGR_TIME 0x7ff +#define BIT_MAX_PRETX_AGGR_TIME(x) \ + (((x) & BIT_MASK_MAX_PRETX_AGGR_TIME) << BIT_SHIFT_MAX_PRETX_AGGR_TIME) +#define BITS_MAX_PRETX_AGGR_TIME \ + (BIT_MASK_MAX_PRETX_AGGR_TIME << BIT_SHIFT_MAX_PRETX_AGGR_TIME) +#define BIT_CLEAR_MAX_PRETX_AGGR_TIME(x) ((x) & (~BITS_MAX_PRETX_AGGR_TIME)) +#define BIT_GET_MAX_PRETX_AGGR_TIME(x) \ + (((x) >> BIT_SHIFT_MAX_PRETX_AGGR_TIME) & BIT_MASK_MAX_PRETX_AGGR_TIME) +#define BIT_SET_MAX_PRETX_AGGR_TIME(x, v) \ + (BIT_CLEAR_MAX_PRETX_AGGR_TIME(x) | BIT_MAX_PRETX_AGGR_TIME(v)) -#define BIT_STOP_BCN_HI_MGT BIT(7) -#define BIT_MAC_STOPBCNQ BIT(6) -#define BIT_MAC_STOPHIQ BIT(5) -#define BIT_MAC_STOPMGQ BIT(4) -#define BIT_MAC_STOPBK BIT(3) -#define BIT_MAC_STOPBE BIT(2) -#define BIT_MAC_STOPVI BIT(1) -#define BIT_MAC_STOPVO BIT(0) +#define BIT_HGQ_DEL_EN BIT(7) -/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ +#endif -#define BIT_DIS_BT_CCA BIT(7) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ +#define BIT_HIQ_DROP BIT(7) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ +/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ -#define BIT_DIS_TXREQ_CLR_CPUMGQ BIT(6) +#define BIT_MGQ_DEL_EN BIT(6) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ +#define BIT_MGQ_DROP BIT(6) -/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ +#endif -#define BIT_DIS_TXREQ_CLR_HI BIT(5) -#define BIT_DIS_TXREQ_CLR_MGQ BIT(4) -#define BIT_DIS_TXREQ_CLR_VO BIT(3) -#define BIT_DIS_TXREQ_CLR_VI BIT(2) -#define BIT_DIS_TXREQ_CLR_BE BIT(1) -#define BIT_DIS_TXREQ_CLR_BK BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_RD_CTRL (Offset 0x0524) */ +/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ -#define BIT_EN_CLR_TXREQ_INCCA BIT(15) -#define BIT_DIS_TX_OVER_BCNQ BIT(14) +#define BIT_VIDEO_JUST_DROP BIT(1) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_NULL_PKT_STATUS_V2 (Offset 0x04E4) */ +#define BIT_TX_NULL_1_V1 BIT(1) -/* 2 REG_RD_CTRL (Offset 0x0524) */ +#endif -#define BIT_EN_BCNERR_INCCCA BIT(13) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ +#define BIT_VIDEO_ENHANCEMENT_FUN_EN BIT(0) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_RD_CTRL (Offset 0x0524) */ +/* 2 REG_NULL_PKT_STATUS_V2 (Offset 0x04E4) */ -#define BIT_EN_BCNERR_INCCA BIT(13) -#define BIT_EN_BCNERR_INEDCCA BIT(12) +#define BIT_TX_NULL_0_V1 BIT(0) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PRECNT_CTRL (Offset 0x04E5) */ +#define BIT_EN_PRECNT BIT(11) +#define BIT_DATA_FW_STS_FILTER BIT(2) +#define BIT_CTRL_FW_STS_FILTER BIT(1) -/* 2 REG_RD_CTRL (Offset 0x0524) */ +#define BIT_SHIFT_PRECNT_TH 0 +#define BIT_MASK_PRECNT_TH 0x7ff +#define BIT_PRECNT_TH(x) (((x) & BIT_MASK_PRECNT_TH) << BIT_SHIFT_PRECNT_TH) +#define BITS_PRECNT_TH (BIT_MASK_PRECNT_TH << BIT_SHIFT_PRECNT_TH) +#define BIT_CLEAR_PRECNT_TH(x) ((x) & (~BITS_PRECNT_TH)) +#define BIT_GET_PRECNT_TH(x) (((x) >> BIT_SHIFT_PRECNT_TH) & BIT_MASK_PRECNT_TH) +#define BIT_SET_PRECNT_TH(x, v) (BIT_CLEAR_PRECNT_TH(x) | BIT_PRECNT_TH(v)) -#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11) -#define BIT_DIS_TXOP_CFE BIT(10) -#define BIT_DIS_LSIG_CFE BIT(9) -#define BIT_DIS_STBC_CFE BIT(8) -#define BIT_BKQ_RD_INIT_EN BIT(7) -#define BIT_BEQ_RD_INIT_EN BIT(6) -#define BIT_VIQ_RD_INIT_EN BIT(5) -#define BIT_VOQ_RD_INIT_EN BIT(4) -#define BIT_BKQ_RD_RESP_EN BIT(3) -#define BIT_BEQ_RD_RESP_EN BIT(2) -#define BIT_VIQ_RD_RESP_EN BIT(1) -#define BIT_VOQ_RD_RESP_EN BIT(0) +#define BIT_MGNT_FW_STS_FILTER BIT(0) -/* 2 REG_MBSSID_CTRL (Offset 0x0526) */ +#endif -#define BIT_MBID_BCNQ7_EN BIT(7) -#define BIT_MBID_BCNQ6_EN BIT(6) -#define BIT_MBID_BCNQ5_EN BIT(5) -#define BIT_MBID_BCNQ4_EN BIT(4) -#define BIT_MBID_BCNQ3_EN BIT(3) -#define BIT_MBID_BCNQ2_EN BIT(2) -#define BIT_MBID_BCNQ1_EN BIT(1) -#define BIT_MBID_BCNQ0_EN BIT(0) +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +/* 2 REG_NULL_PKT_STATUS_EXTEND_V1 (Offset 0x04E7) */ -#define BIT_P2P_CTW_ALLSTASLEEP BIT(7) -#define BIT_P2P_OFF_DISTX_EN BIT(6) -#define BIT_PWR_MGT_EN BIT(5) +#define BIT_CLI3_TX_NULL_1_V1 BIT(7) +#define BIT_CLI3_TX_NULL_0_V1 BIT(6) +#define BIT_CLI2_TX_NULL_1_V1 BIT(5) +#define BIT_CLI2_TX_NULL_0_V1 BIT(4) +#define BIT_CLI1_TX_NULL_1_V1 BIT(3) +#define BIT_CLI1_TX_NULL_0_V1 BIT(2) +#define BIT_CLI0_TX_NULL_1_V1 BIT(1) +#define BIT_CLI0_TX_NULL_0_V1 BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BT_POLLUTE_PKT_CNT (Offset 0x04E8) */ +#define BIT_SHIFT_BT_POLLUTE_PKT_CNT 0 +#define BIT_MASK_BT_POLLUTE_PKT_CNT 0xffff +#define BIT_BT_POLLUTE_PKT_CNT(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT) +#define BITS_BT_POLLUTE_PKT_CNT \ + (BIT_MASK_BT_POLLUTE_PKT_CNT << BIT_SHIFT_BT_POLLUTE_PKT_CNT) +#define BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) ((x) & (~BITS_BT_POLLUTE_PKT_CNT)) +#define BIT_GET_BT_POLLUTE_PKT_CNT(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT) +#define BIT_SET_BT_POLLUTE_PKT_CNT(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) | BIT_BT_POLLUTE_PKT_CNT(v)) -/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +#endif -#define BIT_P2P_BCN_AREA_EN BIT(4) -#define BIT_P2P_CTWND_EN BIT(3) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_PTCL_DBG (Offset 0x04EC) */ +#define BIT_SHIFT_PTCL_DBG 0 +#define BIT_MASK_PTCL_DBG 0xffffffffL +#define BIT_PTCL_DBG(x) (((x) & BIT_MASK_PTCL_DBG) << BIT_SHIFT_PTCL_DBG) +#define BITS_PTCL_DBG (BIT_MASK_PTCL_DBG << BIT_SHIFT_PTCL_DBG) +#define BIT_CLEAR_PTCL_DBG(x) ((x) & (~BITS_PTCL_DBG)) +#define BIT_GET_PTCL_DBG(x) (((x) >> BIT_SHIFT_PTCL_DBG) & BIT_MASK_PTCL_DBG) +#define BIT_SET_PTCL_DBG(x, v) (BIT_CLEAR_PTCL_DBG(x) | BIT_PTCL_DBG(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +/* 2 REG_DROP_NUM (Offset 0x04EC) */ -#define BIT_P2P_NOA1_EN BIT(2) -#define BIT_P2P_NOA0_EN BIT(1) +#define BIT_SHIFT_DROP_PKT_NUM 0 +#define BIT_MASK_DROP_PKT_NUM 0xffff +#define BIT_DROP_PKT_NUM(x) \ + (((x) & BIT_MASK_DROP_PKT_NUM) << BIT_SHIFT_DROP_PKT_NUM) +#define BITS_DROP_PKT_NUM (BIT_MASK_DROP_PKT_NUM << BIT_SHIFT_DROP_PKT_NUM) +#define BIT_CLEAR_DROP_PKT_NUM(x) ((x) & (~BITS_DROP_PKT_NUM)) +#define BIT_GET_DROP_PKT_NUM(x) \ + (((x) >> BIT_SHIFT_DROP_PKT_NUM) & BIT_MASK_DROP_PKT_NUM) +#define BIT_SET_DROP_PKT_NUM(x, v) \ + (BIT_CLEAR_DROP_PKT_NUM(x) | BIT_DROP_PKT_NUM(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PTCL_TX_RPT (Offset 0x04F0) */ -/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ - -#define BIT_P2P_BCN_SEL BIT(0) +#define BIT_SHIFT_AC_TX_RPT_INFO 0 +#define BIT_MASK_AC_TX_RPT_INFO 0xffffffffffffffffL +#define BIT_AC_TX_RPT_INFO(x) \ + (((x) & BIT_MASK_AC_TX_RPT_INFO) << BIT_SHIFT_AC_TX_RPT_INFO) +#define BITS_AC_TX_RPT_INFO \ + (BIT_MASK_AC_TX_RPT_INFO << BIT_SHIFT_AC_TX_RPT_INFO) +#define BIT_CLEAR_AC_TX_RPT_INFO(x) ((x) & (~BITS_AC_TX_RPT_INFO)) +#define BIT_GET_AC_TX_RPT_INFO(x) \ + (((x) >> BIT_SHIFT_AC_TX_RPT_INFO) & BIT_MASK_AC_TX_RPT_INFO) +#define BIT_SET_AC_TX_RPT_INFO(x, v) \ + (BIT_CLEAR_AC_TX_RPT_INFO(x) | BIT_AC_TX_RPT_INFO(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_TXOP_EXTRA_CTRL (Offset 0x04F0) */ + +#define BIT_TXOP_EFFICIENCY_EN BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +/* 2 REG_BT_POLLUTE_PKTCNT (Offset 0x04F0) */ -#define BIT_EN_P2P_CTWND1 BIT(23) +#define BIT_SHIFT_BT_POLLUTE_PKTCNT 0 +#define BIT_MASK_BT_POLLUTE_PKTCNT 0xffff +#define BIT_BT_POLLUTE_PKTCNT(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKTCNT) << BIT_SHIFT_BT_POLLUTE_PKTCNT) +#define BITS_BT_POLLUTE_PKTCNT \ + (BIT_MASK_BT_POLLUTE_PKTCNT << BIT_SHIFT_BT_POLLUTE_PKTCNT) +#define BIT_CLEAR_BT_POLLUTE_PKTCNT(x) ((x) & (~BITS_BT_POLLUTE_PKTCNT)) +#define BIT_GET_BT_POLLUTE_PKTCNT(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKTCNT) & BIT_MASK_BT_POLLUTE_PKTCNT) +#define BIT_SET_BT_POLLUTE_PKTCNT(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKTCNT(x) | BIT_BT_POLLUTE_PKTCNT(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_CPUMGQ_TIMER_CTRL2 (Offset 0x04F4) */ +#define BIT_SHIFT_TRI_HEAD_ADDR 16 +#define BIT_MASK_TRI_HEAD_ADDR 0xfff +#define BIT_TRI_HEAD_ADDR(x) \ + (((x) & BIT_MASK_TRI_HEAD_ADDR) << BIT_SHIFT_TRI_HEAD_ADDR) +#define BITS_TRI_HEAD_ADDR (BIT_MASK_TRI_HEAD_ADDR << BIT_SHIFT_TRI_HEAD_ADDR) +#define BIT_CLEAR_TRI_HEAD_ADDR(x) ((x) & (~BITS_TRI_HEAD_ADDR)) +#define BIT_GET_TRI_HEAD_ADDR(x) \ + (((x) >> BIT_SHIFT_TRI_HEAD_ADDR) & BIT_MASK_TRI_HEAD_ADDR) +#define BIT_SET_TRI_HEAD_ADDR(x, v) \ + (BIT_CLEAR_TRI_HEAD_ADDR(x) | BIT_TRI_HEAD_ADDR(v)) -/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +#define BIT_DROP_TH_EN BIT(8) -#define BIT_EN_TBTT_AREA_FOR_BB BIT(23) +#define BIT_SHIFT_DROP_TH 0 +#define BIT_MASK_DROP_TH 0xff +#define BIT_DROP_TH(x) (((x) & BIT_MASK_DROP_TH) << BIT_SHIFT_DROP_TH) +#define BITS_DROP_TH (BIT_MASK_DROP_TH << BIT_SHIFT_DROP_TH) +#define BIT_CLEAR_DROP_TH(x) ((x) & (~BITS_DROP_TH)) +#define BIT_GET_DROP_TH(x) (((x) >> BIT_SHIFT_DROP_TH) & BIT_MASK_DROP_TH) +#define BIT_SET_DROP_TH(x, v) (BIT_CLEAR_DROP_TH(x) | BIT_DROP_TH(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PTCL_DBG_OUT (Offset 0x04F8) */ +#define BIT_SHIFT_PTCL_DBG_OUT 0 +#define BIT_MASK_PTCL_DBG_OUT 0xffffffffL +#define BIT_PTCL_DBG_OUT(x) \ + (((x) & BIT_MASK_PTCL_DBG_OUT) << BIT_SHIFT_PTCL_DBG_OUT) +#define BITS_PTCL_DBG_OUT (BIT_MASK_PTCL_DBG_OUT << BIT_SHIFT_PTCL_DBG_OUT) +#define BIT_CLEAR_PTCL_DBG_OUT(x) ((x) & (~BITS_PTCL_DBG_OUT)) +#define BIT_GET_PTCL_DBG_OUT(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_OUT) & BIT_MASK_PTCL_DBG_OUT) +#define BIT_SET_PTCL_DBG_OUT(x, v) \ + (BIT_CLEAR_PTCL_DBG_OUT(x) | BIT_PTCL_DBG_OUT(v)) -/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +#endif -#define BIT_EN_BKF_CLR_TXREQ BIT(22) -#define BIT_EN_TSFBIT32_RST_P2P BIT(21) -#define BIT_EN_BCN_TX_BTCCA BIT(20) -#define BIT_DIS_PKT_TX_ATIM BIT(19) -#define BIT_DIS_BCN_DIS_CTN BIT(18) -#define BIT_EN_NAVEND_RST_TXOP BIT(17) -#define BIT_EN_FILTER_CCA BIT(16) +#if (HALMAC_8192E_SUPPORT) -#define BIT_SHIFT_CCA_FILTER_THRS 8 -#define BIT_MASK_CCA_FILTER_THRS 0xff -#define BIT_CCA_FILTER_THRS(x) (((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS) -#define BIT_GET_CCA_FILTER_THRS(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS) +/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#define BIT_MOREDATA_CTRL2_EN BIT(19) -#define BIT_SHIFT_EDCCA_THRS 0 -#define BIT_MASK_EDCCA_THRS 0xff -#define BIT_EDCCA_THRS(x) (((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS) -#define BIT_GET_EDCCA_THRS(x) (((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_P2PPS_SPEC_STATE (Offset 0x052B) */ +/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ -#define BIT_SPEC_POWER_STATE BIT(7) -#define BIT_SPEC_CTWINDOW_ON BIT(6) -#define BIT_SPEC_BEACON_AREA_ON BIT(5) -#define BIT_SPEC_CTWIN_EARLY_DISTX BIT(4) -#define BIT_SPEC_NOA1_OFF_PERIOD BIT(3) -#define BIT_SPEC_FORCE_DOZE1 BIT(2) -#define BIT_SPEC_NOA0_OFF_PERIOD BIT(1) -#define BIT_SPEC_FORCE_DOZE0 BIT(0) +#define BIT_MOREDATA_CTRL2_EN_V2 BIT(19) #endif +#if (HALMAC_8192E_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#define BIT_MOREDATA_CTRL1_EN BIT(18) -/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_BK_QUEUE_THR 24 -#define BIT_MASK_BK_QUEUE_THR 0xff -#define BIT_BK_QUEUE_THR(x) (((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR) -#define BIT_GET_BK_QUEUE_THR(x) (((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR) +/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#define BIT_MOREDATA_CTRL1_EN_V2 BIT(18) -#define BIT_SHIFT_BE_QUEUE_THR 16 -#define BIT_MASK_BE_QUEUE_THR 0xff -#define BIT_BE_QUEUE_THR(x) (((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR) -#define BIT_GET_BE_QUEUE_THR(x) (((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VI_QUEUE_THR 8 -#define BIT_MASK_VI_QUEUE_THR 0xff -#define BIT_VI_QUEUE_THR(x) (((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR) -#define BIT_GET_VI_QUEUE_THR(x) (((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR) +/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#define BIT_EN_BCN_TRXRPT BIT(17) -#define BIT_SHIFT_VO_QUEUE_THR 0 -#define BIT_MASK_VO_QUEUE_THR 0xff -#define BIT_VO_QUEUE_THR(x) (((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR) -#define BIT_GET_VO_QUEUE_THR(x) (((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ -#define BIT_QUEUE_INCOL_EN BIT(16) +#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE BIT(16) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DUMMY_PAGE4_V1 (Offset 0x04FC) */ +#define BIT_BCN_EN_EXTHWSEQ BIT(1) +#define BIT_BCN_EN_HWSEQ BIT(0) -/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION 0xffffffffffffffffL +#define BIT_R_MU_STA_GTAB_POSITION(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION) +#define BITS_R_MU_STA_GTAB_POSITION \ + (BIT_MASK_R_MU_STA_GTAB_POSITION << BIT_SHIFT_R_MU_STA_GTAB_POSITION) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION)) +#define BIT_GET_R_MU_STA_GTAB_POSITION(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION) +#define BIT_SET_R_MU_STA_GTAB_POSITION(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION(x) | BIT_R_MU_STA_GTAB_POSITION(v)) + +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BK_TRIGGER_NUM_V1 12 -#define BIT_MASK_BK_TRIGGER_NUM_V1 0xf -#define BIT_BK_TRIGGER_NUM_V1(x) (((x) & BIT_MASK_BK_TRIGGER_NUM_V1) << BIT_SHIFT_BK_TRIGGER_NUM_V1) -#define BIT_GET_BK_TRIGGER_NUM_V1(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1) & BIT_MASK_BK_TRIGGER_NUM_V1) +/* 2 REG_MOREDATA (Offset 0x04FE) */ +#define BIT_MOREDATA_CTRL2_EN_V1 BIT(3) +#define BIT_MOREDATA_CTRL1_EN_V1 BIT(2) +#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1 BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_EDCA_VO_PARAM (Offset 0x0500) */ +#define BIT_SHIFT_TXOPLIMIT 16 +#define BIT_MASK_TXOPLIMIT 0x7ff +#define BIT_TXOPLIMIT(x) (((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT) +#define BITS_TXOPLIMIT (BIT_MASK_TXOPLIMIT << BIT_SHIFT_TXOPLIMIT) +#define BIT_CLEAR_TXOPLIMIT(x) ((x) & (~BITS_TXOPLIMIT)) +#define BIT_GET_TXOPLIMIT(x) (((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT) +#define BIT_SET_TXOPLIMIT(x, v) (BIT_CLEAR_TXOPLIMIT(x) | BIT_TXOPLIMIT(v)) + +#define BIT_SHIFT_CW 8 +#define BIT_MASK_CW 0xff +#define BIT_CW(x) (((x) & BIT_MASK_CW) << BIT_SHIFT_CW) +#define BITS_CW (BIT_MASK_CW << BIT_SHIFT_CW) +#define BIT_CLEAR_CW(x) ((x) & (~BITS_CW)) +#define BIT_GET_CW(x) (((x) >> BIT_SHIFT_CW) & BIT_MASK_CW) +#define BIT_SET_CW(x, v) (BIT_CLEAR_CW(x) | BIT_CW(v)) + +#define BIT_SHIFT_AIFS 0 +#define BIT_MASK_AIFS 0xff +#define BIT_AIFS(x) (((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS) +#define BITS_AIFS (BIT_MASK_AIFS << BIT_SHIFT_AIFS) +#define BIT_CLEAR_AIFS(x) ((x) & (~BITS_AIFS)) +#define BIT_GET_AIFS(x) (((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS) +#define BIT_SET_AIFS(x, v) (BIT_CLEAR_AIFS(x) | BIT_AIFS(v)) -/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +/* 2 REG_BCNTCFG (Offset 0x0510) */ +#define BIT_SHIFT_BCNCW_MAX 12 +#define BIT_MASK_BCNCW_MAX 0xf +#define BIT_BCNCW_MAX(x) (((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX) +#define BITS_BCNCW_MAX (BIT_MASK_BCNCW_MAX << BIT_SHIFT_BCNCW_MAX) +#define BIT_CLEAR_BCNCW_MAX(x) ((x) & (~BITS_BCNCW_MAX)) +#define BIT_GET_BCNCW_MAX(x) (((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX) +#define BIT_SET_BCNCW_MAX(x, v) (BIT_CLEAR_BCNCW_MAX(x) | BIT_BCNCW_MAX(v)) + +#define BIT_SHIFT_BCNCW_MIN 8 +#define BIT_MASK_BCNCW_MIN 0xf +#define BIT_BCNCW_MIN(x) (((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN) +#define BITS_BCNCW_MIN (BIT_MASK_BCNCW_MIN << BIT_SHIFT_BCNCW_MIN) +#define BIT_CLEAR_BCNCW_MIN(x) ((x) & (~BITS_BCNCW_MIN)) +#define BIT_GET_BCNCW_MIN(x) (((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN) +#define BIT_SET_BCNCW_MIN(x, v) (BIT_CLEAR_BCNCW_MIN(x) | BIT_BCNCW_MIN(v)) + +#define BIT_SHIFT_BCNIFS 0 +#define BIT_MASK_BCNIFS 0xff +#define BIT_BCNIFS(x) (((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS) +#define BITS_BCNIFS (BIT_MASK_BCNIFS << BIT_SHIFT_BCNIFS) +#define BIT_CLEAR_BCNIFS(x) ((x) & (~BITS_BCNIFS)) +#define BIT_GET_BCNIFS(x) (((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS) +#define BIT_SET_BCNIFS(x, v) (BIT_CLEAR_BCNIFS(x) | BIT_BCNIFS(v)) -#define BIT_SHIFT_BE_TRIGGER_NUM 12 -#define BIT_MASK_BE_TRIGGER_NUM 0xf -#define BIT_BE_TRIGGER_NUM(x) (((x) & BIT_MASK_BE_TRIGGER_NUM) << BIT_SHIFT_BE_TRIGGER_NUM) -#define BIT_GET_BE_TRIGGER_NUM(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM) & BIT_MASK_BE_TRIGGER_NUM) +/* 2 REG_PIFS (Offset 0x0512) */ +#define BIT_SHIFT_PIFS 0 +#define BIT_MASK_PIFS 0xff +#define BIT_PIFS(x) (((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS) +#define BITS_PIFS (BIT_MASK_PIFS << BIT_SHIFT_PIFS) +#define BIT_CLEAR_PIFS(x) ((x) & (~BITS_PIFS)) +#define BIT_GET_PIFS(x) (((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS) +#define BIT_SET_PIFS(x, v) (BIT_CLEAR_PIFS(x) | BIT_PIFS(v)) -#endif +/* 2 REG_RDG_PIFS (Offset 0x0513) */ +#define BIT_SHIFT_RDG_PIFS 0 +#define BIT_MASK_RDG_PIFS 0xff +#define BIT_RDG_PIFS(x) (((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS) +#define BITS_RDG_PIFS (BIT_MASK_RDG_PIFS << BIT_SHIFT_RDG_PIFS) +#define BIT_CLEAR_RDG_PIFS(x) ((x) & (~BITS_RDG_PIFS)) +#define BIT_GET_RDG_PIFS(x) (((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS) +#define BIT_SET_RDG_PIFS(x, v) (BIT_CLEAR_RDG_PIFS(x) | BIT_RDG_PIFS(v)) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SIFS (Offset 0x0514) */ +#define BIT_SHIFT_SIFS_OFDM_TRX 24 +#define BIT_MASK_SIFS_OFDM_TRX 0xff +#define BIT_SIFS_OFDM_TRX(x) \ + (((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX) +#define BITS_SIFS_OFDM_TRX (BIT_MASK_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX) +#define BIT_CLEAR_SIFS_OFDM_TRX(x) ((x) & (~BITS_SIFS_OFDM_TRX)) +#define BIT_GET_SIFS_OFDM_TRX(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX) +#define BIT_SET_SIFS_OFDM_TRX(x, v) \ + (BIT_CLEAR_SIFS_OFDM_TRX(x) | BIT_SIFS_OFDM_TRX(v)) + +#define BIT_SHIFT_SIFS_CCK_TRX 16 +#define BIT_MASK_SIFS_CCK_TRX 0xff +#define BIT_SIFS_CCK_TRX(x) \ + (((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX) +#define BITS_SIFS_CCK_TRX (BIT_MASK_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) +#define BIT_CLEAR_SIFS_CCK_TRX(x) ((x) & (~BITS_SIFS_CCK_TRX)) +#define BIT_GET_SIFS_CCK_TRX(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX) +#define BIT_SET_SIFS_CCK_TRX(x, v) \ + (BIT_CLEAR_SIFS_CCK_TRX(x) | BIT_SIFS_CCK_TRX(v)) + +#define BIT_SHIFT_SIFS_OFDM_CTX 8 +#define BIT_MASK_SIFS_OFDM_CTX 0xff +#define BIT_SIFS_OFDM_CTX(x) \ + (((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX) +#define BITS_SIFS_OFDM_CTX (BIT_MASK_SIFS_OFDM_CTX << BIT_SHIFT_SIFS_OFDM_CTX) +#define BIT_CLEAR_SIFS_OFDM_CTX(x) ((x) & (~BITS_SIFS_OFDM_CTX)) +#define BIT_GET_SIFS_OFDM_CTX(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX) +#define BIT_SET_SIFS_OFDM_CTX(x, v) \ + (BIT_CLEAR_SIFS_OFDM_CTX(x) | BIT_SIFS_OFDM_CTX(v)) + +#define BIT_SHIFT_SIFS_CCK_CTX 0 +#define BIT_MASK_SIFS_CCK_CTX 0xff +#define BIT_SIFS_CCK_CTX(x) \ + (((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX) +#define BITS_SIFS_CCK_CTX (BIT_MASK_SIFS_CCK_CTX << BIT_SHIFT_SIFS_CCK_CTX) +#define BIT_CLEAR_SIFS_CCK_CTX(x) ((x) & (~BITS_SIFS_CCK_CTX)) +#define BIT_GET_SIFS_CCK_CTX(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX) +#define BIT_SET_SIFS_CCK_CTX(x, v) \ + (BIT_CLEAR_SIFS_CCK_CTX(x) | BIT_SIFS_CCK_CTX(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +/* 2 REG_TSFTR_SYN_OFFSET (Offset 0x0518) */ +#define BIT_SHIFT_TSFTR_SNC_OFFSET 0 +#define BIT_MASK_TSFTR_SNC_OFFSET 0xffff +#define BIT_TSFTR_SNC_OFFSET(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET) +#define BITS_TSFTR_SNC_OFFSET \ + (BIT_MASK_TSFTR_SNC_OFFSET << BIT_SHIFT_TSFTR_SNC_OFFSET) +#define BIT_CLEAR_TSFTR_SNC_OFFSET(x) ((x) & (~BITS_TSFTR_SNC_OFFSET)) +#define BIT_GET_TSFTR_SNC_OFFSET(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET) +#define BIT_SET_TSFTR_SNC_OFFSET(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET(x) | BIT_TSFTR_SNC_OFFSET(v)) -#define BIT_SHIFT_BE_TRIGGER_NUM_V1 8 -#define BIT_MASK_BE_TRIGGER_NUM_V1 0xf -#define BIT_BE_TRIGGER_NUM_V1(x) (((x) & BIT_MASK_BE_TRIGGER_NUM_V1) << BIT_SHIFT_BE_TRIGGER_NUM_V1) -#define BIT_GET_BE_TRIGGER_NUM_V1(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1) & BIT_MASK_BE_TRIGGER_NUM_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_AGGR_BREAK_TIME (Offset 0x051A) */ +#define BIT_SHIFT_AGGR_BK_TIME 0 +#define BIT_MASK_AGGR_BK_TIME 0xff +#define BIT_AGGR_BK_TIME(x) \ + (((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME) +#define BITS_AGGR_BK_TIME (BIT_MASK_AGGR_BK_TIME << BIT_SHIFT_AGGR_BK_TIME) +#define BIT_CLEAR_AGGR_BK_TIME(x) ((x) & (~BITS_AGGR_BK_TIME)) +#define BIT_GET_AGGR_BK_TIME(x) \ + (((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME) +#define BIT_SET_AGGR_BK_TIME(x, v) \ + (BIT_CLEAR_AGGR_BK_TIME(x) | BIT_AGGR_BK_TIME(v)) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_SLOT (Offset 0x051B) */ +#define BIT_SHIFT_SLOT 0 +#define BIT_MASK_SLOT 0xff +#define BIT_SLOT(x) (((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT) +#define BITS_SLOT (BIT_MASK_SLOT << BIT_SHIFT_SLOT) +#define BIT_CLEAR_SLOT(x) ((x) & (~BITS_SLOT)) +#define BIT_GET_SLOT(x) (((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT) +#define BIT_SET_SLOT(x, v) (BIT_CLEAR_SLOT(x) | BIT_SLOT(v)) -/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BK_TRIGGER_NUM 8 -#define BIT_MASK_BK_TRIGGER_NUM 0xf -#define BIT_BK_TRIGGER_NUM(x) (((x) & BIT_MASK_BK_TRIGGER_NUM) << BIT_SHIFT_BK_TRIGGER_NUM) -#define BIT_GET_BK_TRIGGER_NUM(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM) & BIT_MASK_BK_TRIGGER_NUM) +/* 2 REG_EDCA_CPUMGQ_PARAM (Offset 0x051C) */ +#define BIT_SHIFT_CW_V1 8 +#define BIT_MASK_CW_V1 0xff +#define BIT_CW_V1(x) (((x) & BIT_MASK_CW_V1) << BIT_SHIFT_CW_V1) +#define BITS_CW_V1 (BIT_MASK_CW_V1 << BIT_SHIFT_CW_V1) +#define BIT_CLEAR_CW_V1(x) ((x) & (~BITS_CW_V1)) +#define BIT_GET_CW_V1(x) (((x) >> BIT_SHIFT_CW_V1) & BIT_MASK_CW_V1) +#define BIT_SET_CW_V1(x, v) (BIT_CLEAR_CW_V1(x) | BIT_CW_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +/* 2 REG_NOA_ON_ERLY_TIME (Offset 0x051C) */ +#define BIT_SHIFT__NOA_ON_ERLY_TIME 0 +#define BIT_MASK__NOA_ON_ERLY_TIME 0xff +#define BIT__NOA_ON_ERLY_TIME(x) \ + (((x) & BIT_MASK__NOA_ON_ERLY_TIME) << BIT_SHIFT__NOA_ON_ERLY_TIME) +#define BITS__NOA_ON_ERLY_TIME \ + (BIT_MASK__NOA_ON_ERLY_TIME << BIT_SHIFT__NOA_ON_ERLY_TIME) +#define BIT_CLEAR__NOA_ON_ERLY_TIME(x) ((x) & (~BITS__NOA_ON_ERLY_TIME)) +#define BIT_GET__NOA_ON_ERLY_TIME(x) \ + (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME) & BIT_MASK__NOA_ON_ERLY_TIME) +#define BIT_SET__NOA_ON_ERLY_TIME(x, v) \ + (BIT_CLEAR__NOA_ON_ERLY_TIME(x) | BIT__NOA_ON_ERLY_TIME(v)) -#define BIT_SHIFT_VI_TRIGGER_NUM 4 -#define BIT_MASK_VI_TRIGGER_NUM 0xf -#define BIT_VI_TRIGGER_NUM(x) (((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM) -#define BIT_GET_VI_TRIGGER_NUM(x) (((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_VO_TRIGGER_NUM 0 -#define BIT_MASK_VO_TRIGGER_NUM 0xf -#define BIT_VO_TRIGGER_NUM(x) (((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM) -#define BIT_GET_VO_TRIGGER_NUM(x) (((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM) +/* 2 REG_EDCA_CPUMGQ_PARAM (Offset 0x051C) */ +#define BIT_SHIFT_AIFS_V1 0 +#define BIT_MASK_AIFS_V1 0xff +#define BIT_AIFS_V1(x) (((x) & BIT_MASK_AIFS_V1) << BIT_SHIFT_AIFS_V1) +#define BITS_AIFS_V1 (BIT_MASK_AIFS_V1 << BIT_SHIFT_AIFS_V1) +#define BIT_CLEAR_AIFS_V1(x) ((x) & (~BITS_AIFS_V1)) +#define BIT_GET_AIFS_V1(x) (((x) >> BIT_SHIFT_AIFS_V1) & BIT_MASK_AIFS_V1) +#define BIT_SET_AIFS_V1(x, v) (BIT_CLEAR_AIFS_V1(x) | BIT_AIFS_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_NOA_OFF_ERLY_TIME (Offset 0x051D) */ +#define BIT_SHIFT__NOA_OFF_ERLY_TIME 0 +#define BIT_MASK__NOA_OFF_ERLY_TIME 0xff +#define BIT__NOA_OFF_ERLY_TIME(x) \ + (((x) & BIT_MASK__NOA_OFF_ERLY_TIME) << BIT_SHIFT__NOA_OFF_ERLY_TIME) +#define BITS__NOA_OFF_ERLY_TIME \ + (BIT_MASK__NOA_OFF_ERLY_TIME << BIT_SHIFT__NOA_OFF_ERLY_TIME) +#define BIT_CLEAR__NOA_OFF_ERLY_TIME(x) ((x) & (~BITS__NOA_OFF_ERLY_TIME)) +#define BIT_GET__NOA_OFF_ERLY_TIME(x) \ + (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME) & BIT_MASK__NOA_OFF_ERLY_TIME) +#define BIT_SET__NOA_OFF_ERLY_TIME(x, v) \ + (BIT_CLEAR__NOA_OFF_ERLY_TIME(x) | BIT__NOA_OFF_ERLY_TIME(v)) -/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 -#define BIT_MASK_TBTT_HOLD_TIME_AP 0xfff -#define BIT_TBTT_HOLD_TIME_AP(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP) -#define BIT_GET_TBTT_HOLD_TIME_AP(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP) +/* 2 REG_CPUMGQ_PAUSE (Offset 0x051E) */ +#define BIT_MAC_STOP_CPUMGQ_V1 BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TX_PTCL_CTRL (Offset 0x0520) */ +#define BIT_DIS_EDCCA BIT(15) +#define BIT_DIS_CCA BIT(14) +#define BIT_LSIG_TXOP_TXCMD_NAV BIT(13) +#define BIT_SIFS_BK_EN BIT(12) + +#define BIT_SHIFT_TXQ_NAV_MSK 8 +#define BIT_MASK_TXQ_NAV_MSK 0xf +#define BIT_TXQ_NAV_MSK(x) \ + (((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK) +#define BITS_TXQ_NAV_MSK (BIT_MASK_TXQ_NAV_MSK << BIT_SHIFT_TXQ_NAV_MSK) +#define BIT_CLEAR_TXQ_NAV_MSK(x) ((x) & (~BITS_TXQ_NAV_MSK)) +#define BIT_GET_TXQ_NAV_MSK(x) \ + (((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK) +#define BIT_SET_TXQ_NAV_MSK(x, v) \ + (BIT_CLEAR_TXQ_NAV_MSK(x) | BIT_TXQ_NAV_MSK(v)) + +#define BIT_DIS_CW BIT(7) +#define BIT_NAV_END_TXOP BIT(6) +#define BIT_RDG_END_TXOP BIT(5) +#define BIT_AC_INBCN_HOLD BIT(4) +#define BIT_MGTQ_TXOP_EN BIT(3) +#define BIT_MGTQ_RTSMF_EN BIT(2) +#define BIT_HIQ_RTSMF_EN BIT(1) +#define BIT_BCN_RTSMF_EN BIT(0) -/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ +/* 2 REG_TXPAUSE (Offset 0x0522) */ +#define BIT_STOP_BCN_HI_MGT BIT(7) +#define BIT_MAC_STOPBCNQ BIT(6) +#define BIT_MAC_STOPHIQ BIT(5) +#define BIT_MAC_STOPMGQ BIT(4) +#define BIT_MAC_STOPBK BIT(3) +#define BIT_MAC_STOPBE BIT(2) +#define BIT_MAC_STOPVI BIT(1) +#define BIT_MAC_STOPVO BIT(0) -#define BIT_SHIFT_TBTT_HOLD_TIME_INFRA 4 -#define BIT_MASK_TBTT_HOLD_TIME_INFRA 0xf -#define BIT_TBTT_HOLD_TIME_INFRA(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_INFRA) << BIT_SHIFT_TBTT_HOLD_TIME_INFRA) -#define BIT_GET_TBTT_HOLD_TIME_INFRA(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_INFRA) & BIT_MASK_TBTT_HOLD_TIME_INFRA) +/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ +#define BIT_DIS_BT_CCA BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ +#define BIT_DIS_TXREQ_CLR_CPUMGQ BIT(6) -/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TBTT_PROHIBIT_SETUP 0 -#define BIT_MASK_TBTT_PROHIBIT_SETUP 0xf -#define BIT_TBTT_PROHIBIT_SETUP(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP) -#define BIT_GET_TBTT_PROHIBIT_SETUP(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP) +/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ +#define BIT_DIS_TXREQ_CLR_HI BIT(5) +#define BIT_DIS_TXREQ_CLR_MGQ BIT(4) +#define BIT_DIS_TXREQ_CLR_VO BIT(3) +#define BIT_DIS_TXREQ_CLR_VI BIT(2) +#define BIT_DIS_TXREQ_CLR_BE BIT(1) +#define BIT_DIS_TXREQ_CLR_BK BIT(0) -/* 2 REG_P2PPS_STATE (Offset 0x0543) */ +/* 2 REG_RD_CTRL (Offset 0x0524) */ -#define BIT_POWER_STATE BIT(7) -#define BIT_CTWINDOW_ON BIT(6) -#define BIT_BEACON_AREA_ON BIT(5) -#define BIT_CTWIN_EARLY_DISTX BIT(4) -#define BIT_NOA1_OFF_PERIOD BIT(3) -#define BIT_FORCE_DOZE1 BIT(2) -#define BIT_NOA0_OFF_PERIOD BIT(1) -#define BIT_FORCE_DOZE0 BIT(0) +#define BIT_EN_CLR_TXREQ_INCCA BIT(15) +#define BIT_DIS_TX_OVER_BCNQ BIT(14) -/* 2 REG_RD_NAV_NXT (Offset 0x0544) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RD_NAV_PROT_NXT 0 -#define BIT_MASK_RD_NAV_PROT_NXT 0xffff -#define BIT_RD_NAV_PROT_NXT(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT) -#define BIT_GET_RD_NAV_PROT_NXT(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT) +/* 2 REG_RD_CTRL (Offset 0x0524) */ +#define BIT_EN_BCNERR_INCCCA BIT(13) -/* 2 REG_NAV_PROT_LEN (Offset 0x0546) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_NAV_PROT_LEN 0 -#define BIT_MASK_NAV_PROT_LEN 0xffff -#define BIT_NAV_PROT_LEN(x) (((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN) -#define BIT_GET_NAV_PROT_LEN(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN) +/* 2 REG_RD_CTRL (Offset 0x0524) */ +#define BIT_EN_BCNERR_INCCA BIT(13) +#define BIT_EN_BCNERR_INEDCCA BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_FTM_CTRL (Offset 0x0548) */ +/* 2 REG_RD_CTRL (Offset 0x0524) */ +#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11) +#define BIT_DIS_TXOP_CFE BIT(10) +#define BIT_DIS_LSIG_CFE BIT(9) -#define BIT_SHIFT_FTM_TSF_R2T_PORT 22 -#define BIT_MASK_FTM_TSF_R2T_PORT 0x7 -#define BIT_FTM_TSF_R2T_PORT(x) (((x) & BIT_MASK_FTM_TSF_R2T_PORT) << BIT_SHIFT_FTM_TSF_R2T_PORT) -#define BIT_GET_FTM_TSF_R2T_PORT(x) (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT) & BIT_MASK_FTM_TSF_R2T_PORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FTM_TSF_T2R_PORT 19 -#define BIT_MASK_FTM_TSF_T2R_PORT 0x7 -#define BIT_FTM_TSF_T2R_PORT(x) (((x) & BIT_MASK_FTM_TSF_T2R_PORT) << BIT_SHIFT_FTM_TSF_T2R_PORT) -#define BIT_GET_FTM_TSF_T2R_PORT(x) (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT) & BIT_MASK_FTM_TSF_T2R_PORT) +/* 2 REG_RD_CTRL (Offset 0x0524) */ +#define BIT_DIS_STBC_CFE BIT(8) -#define BIT_SHIFT_FTM_PTT_PORT 16 -#define BIT_MASK_FTM_PTT_PORT 0x7 -#define BIT_FTM_PTT_PORT(x) (((x) & BIT_MASK_FTM_PTT_PORT) << BIT_SHIFT_FTM_PTT_PORT) -#define BIT_GET_FTM_PTT_PORT(x) (((x) >> BIT_SHIFT_FTM_PTT_PORT) & BIT_MASK_FTM_PTT_PORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FTM_PTT 0 -#define BIT_MASK_FTM_PTT 0xffff -#define BIT_FTM_PTT(x) (((x) & BIT_MASK_FTM_PTT) << BIT_SHIFT_FTM_PTT) -#define BIT_GET_FTM_PTT(x) (((x) >> BIT_SHIFT_FTM_PTT) & BIT_MASK_FTM_PTT) +/* 2 REG_RD_CTRL (Offset 0x0524) */ +#define BIT_BKQ_RD_INIT_EN BIT(7) +#define BIT_BEQ_RD_INIT_EN BIT(6) +#define BIT_VIQ_RD_INIT_EN BIT(5) +#define BIT_VOQ_RD_INIT_EN BIT(4) +#define BIT_BKQ_RD_RESP_EN BIT(3) +#define BIT_BEQ_RD_RESP_EN BIT(2) +#define BIT_VIQ_RD_RESP_EN BIT(1) +#define BIT_VOQ_RD_RESP_EN BIT(0) -/* 2 REG_FTM_TSF_CNT (Offset 0x054C) */ +/* 2 REG_MBSSID_CTRL (Offset 0x0526) */ +#define BIT_MBID_BCNQ7_EN BIT(7) +#define BIT_MBID_BCNQ6_EN BIT(6) +#define BIT_MBID_BCNQ5_EN BIT(5) +#define BIT_MBID_BCNQ4_EN BIT(4) +#define BIT_MBID_BCNQ3_EN BIT(3) +#define BIT_MBID_BCNQ2_EN BIT(2) +#define BIT_MBID_BCNQ1_EN BIT(1) +#define BIT_MBID_BCNQ0_EN BIT(0) -#define BIT_SHIFT_FTM_TSF_R2T 16 -#define BIT_MASK_FTM_TSF_R2T 0xffff -#define BIT_FTM_TSF_R2T(x) (((x) & BIT_MASK_FTM_TSF_R2T) << BIT_SHIFT_FTM_TSF_R2T) -#define BIT_GET_FTM_TSF_R2T(x) (((x) >> BIT_SHIFT_FTM_TSF_R2T) & BIT_MASK_FTM_TSF_R2T) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FTM_TSF_T2R 0 -#define BIT_MASK_FTM_TSF_T2R 0xffff -#define BIT_FTM_TSF_T2R(x) (((x) & BIT_MASK_FTM_TSF_T2R) << BIT_SHIFT_FTM_TSF_T2R) -#define BIT_GET_FTM_TSF_T2R(x) (((x) >> BIT_SHIFT_FTM_TSF_T2R) & BIT_MASK_FTM_TSF_T2R) +/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +#define BIT_P2P_CTW_ALLSTASLEEP BIT(7) +#define BIT_P2P_OFF_DISTX_EN BIT(6) +#define BIT_PWR_MGT_EN BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +#define BIT_P2P_BCN_AREA_EN BIT(4) +#define BIT_P2P_CTWND_EN BIT(3) -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +#endif -#define BIT_DIS_RX_BSSID_FIT BIT(6) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +#define BIT_P2P_NOA1_EN BIT(2) +#define BIT_P2P_NOA0_EN BIT(1) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ -#define BIT_P0_EN_TXBCN_RPT BIT(5) +#define BIT_P2P_BCN_SEL BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +#define BIT_EN_P2P_CTWND1 BIT(23) -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +#endif -#define BIT_DIS_TSF_UDT BIT(4) -#define BIT_EN_BCN_FUNCTION BIT(3) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +#define BIT_EN_TBTT_AREA_FOR_BB BIT(23) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ -#define BIT_EN_TXBCN_RPT BIT(2) +#define BIT_EN_BKF_CLR_TXREQ BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +#define BIT_EN_TSFBIT32_RST_P2P BIT(21) -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +#endif -#define BIT_P0_EN_RXBCN_RPT BIT(2) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +#define BIT_EN_BCN_TX_BTCCA BIT(20) +#define BIT_DIS_PKT_TX_ATIM BIT(19) +#define BIT_DIS_BCN_DIS_CTN BIT(18) +#define BIT_EN_NAVEND_RST_TXOP BIT(17) +#define BIT_EN_FILTER_CCA BIT(16) + +#define BIT_SHIFT_CCA_FILTER_THRS 8 +#define BIT_MASK_CCA_FILTER_THRS 0xff +#define BIT_CCA_FILTER_THRS(x) \ + (((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS) +#define BITS_CCA_FILTER_THRS \ + (BIT_MASK_CCA_FILTER_THRS << BIT_SHIFT_CCA_FILTER_THRS) +#define BIT_CLEAR_CCA_FILTER_THRS(x) ((x) & (~BITS_CCA_FILTER_THRS)) +#define BIT_GET_CCA_FILTER_THRS(x) \ + (((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS) +#define BIT_SET_CCA_FILTER_THRS(x, v) \ + (BIT_CLEAR_CCA_FILTER_THRS(x) | BIT_CCA_FILTER_THRS(v)) + +#define BIT_SHIFT_EDCCA_THRS 0 +#define BIT_MASK_EDCCA_THRS 0xff +#define BIT_EDCCA_THRS(x) (((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS) +#define BITS_EDCCA_THRS (BIT_MASK_EDCCA_THRS << BIT_SHIFT_EDCCA_THRS) +#define BIT_CLEAR_EDCCA_THRS(x) ((x) & (~BITS_EDCCA_THRS)) +#define BIT_GET_EDCCA_THRS(x) \ + (((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS) +#define BIT_SET_EDCCA_THRS(x, v) (BIT_CLEAR_EDCCA_THRS(x) | BIT_EDCCA_THRS(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P2PPS_SPEC_STATE (Offset 0x052B) */ +#define BIT_SPEC_POWER_STATE BIT(7) +#define BIT_SPEC_CTWINDOW_ON BIT(6) +#define BIT_SPEC_BEACON_AREA_ON BIT(5) +#define BIT_SPEC_CTWIN_EARLY_DISTX BIT(4) +#define BIT_SPEC_NOA1_OFF_PERIOD BIT(3) +#define BIT_SPEC_FORCE_DOZE1 BIT(2) +#define BIT_SPEC_NOA0_OFF_PERIOD BIT(1) +#define BIT_SPEC_FORCE_DOZE0 BIT(0) + +#define BIT_SHIFT_TBTT_PROHIBIT_SETUP 0 +#define BIT_MASK_TBTT_PROHIBIT_SETUP 0xf +#define BIT_TBTT_PROHIBIT_SETUP(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP) +#define BITS_TBTT_PROHIBIT_SETUP \ + (BIT_MASK_TBTT_PROHIBIT_SETUP << BIT_SHIFT_TBTT_PROHIBIT_SETUP) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) ((x) & (~BITS_TBTT_PROHIBIT_SETUP)) +#define BIT_GET_TBTT_PROHIBIT_SETUP(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP) +#define BIT_SET_TBTT_PROHIBIT_SETUP(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) | BIT_TBTT_PROHIBIT_SETUP(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_TXOP_LIMIT_CTRL (Offset 0x052C) */ + +#define BIT_SHIFT_TXOP_TBTT_CNT 24 +#define BIT_MASK_TXOP_TBTT_CNT 0xff +#define BIT_TXOP_TBTT_CNT(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT) << BIT_SHIFT_TXOP_TBTT_CNT) +#define BITS_TXOP_TBTT_CNT (BIT_MASK_TXOP_TBTT_CNT << BIT_SHIFT_TXOP_TBTT_CNT) +#define BIT_CLEAR_TXOP_TBTT_CNT(x) ((x) & (~BITS_TXOP_TBTT_CNT)) +#define BIT_GET_TXOP_TBTT_CNT(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT) & BIT_MASK_TXOP_TBTT_CNT) +#define BIT_SET_TXOP_TBTT_CNT(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT(x) | BIT_TXOP_TBTT_CNT(v)) + +#define BIT_SHIFT_TXOP_TBTT_CNT_SEL 20 +#define BIT_MASK_TXOP_TBTT_CNT_SEL 0xf +#define BIT_TXOP_TBTT_CNT_SEL(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL) << BIT_SHIFT_TXOP_TBTT_CNT_SEL) +#define BITS_TXOP_TBTT_CNT_SEL \ + (BIT_MASK_TXOP_TBTT_CNT_SEL << BIT_SHIFT_TXOP_TBTT_CNT_SEL) +#define BIT_CLEAR_TXOP_TBTT_CNT_SEL(x) ((x) & (~BITS_TXOP_TBTT_CNT_SEL)) +#define BIT_GET_TXOP_TBTT_CNT_SEL(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL) & BIT_MASK_TXOP_TBTT_CNT_SEL) +#define BIT_SET_TXOP_TBTT_CNT_SEL(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_SEL(x) | BIT_TXOP_TBTT_CNT_SEL(v)) + +#define BIT_SHIFT_TXOP_LMT_EN 16 +#define BIT_MASK_TXOP_LMT_EN 0xf +#define BIT_TXOP_LMT_EN(x) \ + (((x) & BIT_MASK_TXOP_LMT_EN) << BIT_SHIFT_TXOP_LMT_EN) +#define BITS_TXOP_LMT_EN (BIT_MASK_TXOP_LMT_EN << BIT_SHIFT_TXOP_LMT_EN) +#define BIT_CLEAR_TXOP_LMT_EN(x) ((x) & (~BITS_TXOP_LMT_EN)) +#define BIT_GET_TXOP_LMT_EN(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_EN) & BIT_MASK_TXOP_LMT_EN) +#define BIT_SET_TXOP_LMT_EN(x, v) \ + (BIT_CLEAR_TXOP_LMT_EN(x) | BIT_TXOP_LMT_EN(v)) + +#define BIT_SHIFT_TXOP_LMT_TX_TIME 8 +#define BIT_MASK_TXOP_LMT_TX_TIME 0xff +#define BIT_TXOP_LMT_TX_TIME(x) \ + (((x) & BIT_MASK_TXOP_LMT_TX_TIME) << BIT_SHIFT_TXOP_LMT_TX_TIME) +#define BITS_TXOP_LMT_TX_TIME \ + (BIT_MASK_TXOP_LMT_TX_TIME << BIT_SHIFT_TXOP_LMT_TX_TIME) +#define BIT_CLEAR_TXOP_LMT_TX_TIME(x) ((x) & (~BITS_TXOP_LMT_TX_TIME)) +#define BIT_GET_TXOP_LMT_TX_TIME(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME) & BIT_MASK_TXOP_LMT_TX_TIME) +#define BIT_SET_TXOP_LMT_TX_TIME(x, v) \ + (BIT_CLEAR_TXOP_LMT_TX_TIME(x) | BIT_TXOP_LMT_TX_TIME(v)) + +#define BIT_TXOP_CNT_TRIGGER_RESET BIT(7) + +#define BIT_SHIFT_TXOP_LMT_PKT_NUM 0 +#define BIT_MASK_TXOP_LMT_PKT_NUM 0x3f +#define BIT_TXOP_LMT_PKT_NUM(x) \ + (((x) & BIT_MASK_TXOP_LMT_PKT_NUM) << BIT_SHIFT_TXOP_LMT_PKT_NUM) +#define BITS_TXOP_LMT_PKT_NUM \ + (BIT_MASK_TXOP_LMT_PKT_NUM << BIT_SHIFT_TXOP_LMT_PKT_NUM) +#define BIT_CLEAR_TXOP_LMT_PKT_NUM(x) ((x) & (~BITS_TXOP_LMT_PKT_NUM)) +#define BIT_GET_TXOP_LMT_PKT_NUM(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM) & BIT_MASK_TXOP_LMT_PKT_NUM) +#define BIT_SET_TXOP_LMT_PKT_NUM(x, v) \ + (BIT_CLEAR_TXOP_LMT_PKT_NUM(x) | BIT_TXOP_LMT_PKT_NUM(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_P2PON_DIS_TXTIME (Offset 0x0531) */ + +#define BIT_SHIFT_P2PON_DIS_TXTIME 0 +#define BIT_MASK_P2PON_DIS_TXTIME 0xff +#define BIT_P2PON_DIS_TXTIME(x) \ + (((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME) +#define BITS_P2PON_DIS_TXTIME \ + (BIT_MASK_P2PON_DIS_TXTIME << BIT_SHIFT_P2PON_DIS_TXTIME) +#define BIT_CLEAR_P2PON_DIS_TXTIME(x) ((x) & (~BITS_P2PON_DIS_TXTIME)) +#define BIT_GET_P2PON_DIS_TXTIME(x) \ + (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME) +#define BIT_SET_P2PON_DIS_TXTIME(x, v) \ + (BIT_CLEAR_P2PON_DIS_TXTIME(x) | BIT_P2PON_DIS_TXTIME(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CCA_TXEN_CNT (Offset 0x0534) */ + +#define BIT_CCA_TXEN_CNT_SWITCH BIT(17) +#define BIT_CCA_TXEN_CNT_EN BIT(16) + +#define BIT_SHIFT_CCA_TXEN_BIG_CNT 8 +#define BIT_MASK_CCA_TXEN_BIG_CNT 0xff +#define BIT_CCA_TXEN_BIG_CNT(x) \ + (((x) & BIT_MASK_CCA_TXEN_BIG_CNT) << BIT_SHIFT_CCA_TXEN_BIG_CNT) +#define BITS_CCA_TXEN_BIG_CNT \ + (BIT_MASK_CCA_TXEN_BIG_CNT << BIT_SHIFT_CCA_TXEN_BIG_CNT) +#define BIT_CLEAR_CCA_TXEN_BIG_CNT(x) ((x) & (~BITS_CCA_TXEN_BIG_CNT)) +#define BIT_GET_CCA_TXEN_BIG_CNT(x) \ + (((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT) & BIT_MASK_CCA_TXEN_BIG_CNT) +#define BIT_SET_CCA_TXEN_BIG_CNT(x, v) \ + (BIT_CLEAR_CCA_TXEN_BIG_CNT(x) | BIT_CCA_TXEN_BIG_CNT(v)) + +#define BIT_SHIFT_CCA_TXEN_SMALL_CNT 0 +#define BIT_MASK_CCA_TXEN_SMALL_CNT 0xff +#define BIT_CCA_TXEN_SMALL_CNT(x) \ + (((x) & BIT_MASK_CCA_TXEN_SMALL_CNT) << BIT_SHIFT_CCA_TXEN_SMALL_CNT) +#define BITS_CCA_TXEN_SMALL_CNT \ + (BIT_MASK_CCA_TXEN_SMALL_CNT << BIT_SHIFT_CCA_TXEN_SMALL_CNT) +#define BIT_CLEAR_CCA_TXEN_SMALL_CNT(x) ((x) & (~BITS_CCA_TXEN_SMALL_CNT)) +#define BIT_GET_CCA_TXEN_SMALL_CNT(x) \ + (((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT) & BIT_MASK_CCA_TXEN_SMALL_CNT) +#define BIT_SET_CCA_TXEN_SMALL_CNT(x, v) \ + (BIT_CLEAR_CCA_TXEN_SMALL_CNT(x) | BIT_CCA_TXEN_SMALL_CNT(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ -#define BIT_DIS_BCNQ_SUB BIT(1) +#define BIT_SHIFT_BK_QUEUE_THR 24 +#define BIT_MASK_BK_QUEUE_THR 0xff +#define BIT_BK_QUEUE_THR(x) \ + (((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR) +#define BITS_BK_QUEUE_THR (BIT_MASK_BK_QUEUE_THR << BIT_SHIFT_BK_QUEUE_THR) +#define BIT_CLEAR_BK_QUEUE_THR(x) ((x) & (~BITS_BK_QUEUE_THR)) +#define BIT_GET_BK_QUEUE_THR(x) \ + (((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR) +#define BIT_SET_BK_QUEUE_THR(x, v) \ + (BIT_CLEAR_BK_QUEUE_THR(x) | BIT_BK_QUEUE_THR(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */ +#define BIT_SHIFT_MAX_INTER_COLLISION_BK 24 +#define BIT_MASK_MAX_INTER_COLLISION_BK 0xff +#define BIT_MAX_INTER_COLLISION_BK(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_BK) \ + << BIT_SHIFT_MAX_INTER_COLLISION_BK) +#define BITS_MAX_INTER_COLLISION_BK \ + (BIT_MASK_MAX_INTER_COLLISION_BK << BIT_SHIFT_MAX_INTER_COLLISION_BK) +#define BIT_CLEAR_MAX_INTER_COLLISION_BK(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_BK)) +#define BIT_GET_MAX_INTER_COLLISION_BK(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK) & \ + BIT_MASK_MAX_INTER_COLLISION_BK) +#define BIT_SET_MAX_INTER_COLLISION_BK(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_BK(x) | BIT_MAX_INTER_COLLISION_BK(v)) -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +#endif -#define BIT_EN_P2P_CTWINDOW BIT(1) -#define BIT_EN_P2P_BCNQ_AREA BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ +#define BIT_SHIFT_BE_QUEUE_THR 16 +#define BIT_MASK_BE_QUEUE_THR 0xff +#define BIT_BE_QUEUE_THR(x) \ + (((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR) +#define BITS_BE_QUEUE_THR (BIT_MASK_BE_QUEUE_THR << BIT_SHIFT_BE_QUEUE_THR) +#define BIT_CLEAR_BE_QUEUE_THR(x) ((x) & (~BITS_BE_QUEUE_THR)) +#define BIT_GET_BE_QUEUE_THR(x) \ + (((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR) +#define BIT_SET_BE_QUEUE_THR(x, v) \ + (BIT_CLEAR_BE_QUEUE_THR(x) | BIT_BE_QUEUE_THR(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +/* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */ -#define BIT_DIS_RX_BSSID_FIT1 BIT(6) +#define BIT_SHIFT_MAX_INTER_COLLISION_BE 16 +#define BIT_MASK_MAX_INTER_COLLISION_BE 0xff +#define BIT_MAX_INTER_COLLISION_BE(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_BE) \ + << BIT_SHIFT_MAX_INTER_COLLISION_BE) +#define BITS_MAX_INTER_COLLISION_BE \ + (BIT_MASK_MAX_INTER_COLLISION_BE << BIT_SHIFT_MAX_INTER_COLLISION_BE) +#define BIT_CLEAR_MAX_INTER_COLLISION_BE(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_BE)) +#define BIT_GET_MAX_INTER_COLLISION_BE(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE) & \ + BIT_MASK_MAX_INTER_COLLISION_BE) +#define BIT_SET_MAX_INTER_COLLISION_BE(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_BE(x) | BIT_MAX_INTER_COLLISION_BE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ +#define BIT_SHIFT_VI_QUEUE_THR 8 +#define BIT_MASK_VI_QUEUE_THR 0xff +#define BIT_VI_QUEUE_THR(x) \ + (((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR) +#define BITS_VI_QUEUE_THR (BIT_MASK_VI_QUEUE_THR << BIT_SHIFT_VI_QUEUE_THR) +#define BIT_CLEAR_VI_QUEUE_THR(x) ((x) & (~BITS_VI_QUEUE_THR)) +#define BIT_GET_VI_QUEUE_THR(x) \ + (((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR) +#define BIT_SET_VI_QUEUE_THR(x, v) \ + (BIT_CLEAR_VI_QUEUE_THR(x) | BIT_VI_QUEUE_THR(v)) -/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#endif -#define BIT_CLI0_DIS_RX_BSSID_FIT BIT(6) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */ +#define BIT_SHIFT_MAX_INTER_COLLISION_VI 8 +#define BIT_MASK_MAX_INTER_COLLISION_VI 0xff +#define BIT_MAX_INTER_COLLISION_VI(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_VI) \ + << BIT_SHIFT_MAX_INTER_COLLISION_VI) +#define BITS_MAX_INTER_COLLISION_VI \ + (BIT_MASK_MAX_INTER_COLLISION_VI << BIT_SHIFT_MAX_INTER_COLLISION_VI) +#define BIT_CLEAR_MAX_INTER_COLLISION_VI(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_VI)) +#define BIT_GET_MAX_INTER_COLLISION_VI(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI) & \ + BIT_MASK_MAX_INTER_COLLISION_VI) +#define BIT_SET_MAX_INTER_COLLISION_VI(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_VI(x) | BIT_MAX_INTER_COLLISION_VI(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ -#define BIT_DIS_TSF1_UDT BIT(4) +#define BIT_SHIFT_VO_QUEUE_THR 0 +#define BIT_MASK_VO_QUEUE_THR 0xff +#define BIT_VO_QUEUE_THR(x) \ + (((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR) +#define BITS_VO_QUEUE_THR (BIT_MASK_VO_QUEUE_THR << BIT_SHIFT_VO_QUEUE_THR) +#define BIT_CLEAR_VO_QUEUE_THR(x) ((x) & (~BITS_VO_QUEUE_THR)) +#define BIT_GET_VO_QUEUE_THR(x) \ + (((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR) +#define BIT_SET_VO_QUEUE_THR(x, v) \ + (BIT_CLEAR_VO_QUEUE_THR(x) | BIT_VO_QUEUE_THR(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */ +#define BIT_SHIFT_MAX_INTER_COLLISION_VO 0 +#define BIT_MASK_MAX_INTER_COLLISION_VO 0xff +#define BIT_MAX_INTER_COLLISION_VO(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_VO) \ + << BIT_SHIFT_MAX_INTER_COLLISION_VO) +#define BITS_MAX_INTER_COLLISION_VO \ + (BIT_MASK_MAX_INTER_COLLISION_VO << BIT_SHIFT_MAX_INTER_COLLISION_VO) +#define BIT_CLEAR_MAX_INTER_COLLISION_VO(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_VO)) +#define BIT_GET_MAX_INTER_COLLISION_VO(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO) & \ + BIT_MASK_MAX_INTER_COLLISION_VO) +#define BIT_SET_MAX_INTER_COLLISION_VO(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_VO(x) | BIT_MAX_INTER_COLLISION_VO(v)) -/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#endif -#define BIT_CLI0_DIS_TSF_UDT BIT(4) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#define BIT_QUEUE_INCOL_EN BIT(16) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ -#define BIT_EN_BCN1_FUNCTION BIT(3) +#define BIT_MAX_INTER_COLLISION_EN BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#define BIT_SHIFT_BK_TRIGGER_NUM_V1 12 +#define BIT_MASK_BK_TRIGGER_NUM_V1 0xf +#define BIT_BK_TRIGGER_NUM_V1(x) \ + (((x) & BIT_MASK_BK_TRIGGER_NUM_V1) << BIT_SHIFT_BK_TRIGGER_NUM_V1) +#define BITS_BK_TRIGGER_NUM_V1 \ + (BIT_MASK_BK_TRIGGER_NUM_V1 << BIT_SHIFT_BK_TRIGGER_NUM_V1) +#define BIT_CLEAR_BK_TRIGGER_NUM_V1(x) ((x) & (~BITS_BK_TRIGGER_NUM_V1)) +#define BIT_GET_BK_TRIGGER_NUM_V1(x) \ + (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1) & BIT_MASK_BK_TRIGGER_NUM_V1) +#define BIT_SET_BK_TRIGGER_NUM_V1(x, v) \ + (BIT_CLEAR_BK_TRIGGER_NUM_V1(x) | BIT_BK_TRIGGER_NUM_V1(v)) -/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#endif -#define BIT_CLI0_EN_BCN_FUNCTION BIT(3) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK 12 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK 0xf +#define BIT_MAX_INTER_COLLISION_CNT_BK(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK) +#define BITS_MAX_INTER_COLLISION_CNT_BK \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_BK \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_BK(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_BK) +#define BIT_SET_MAX_INTER_COLLISION_CNT_BK(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK(x) | \ + BIT_MAX_INTER_COLLISION_CNT_BK(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8822B_SUPPORT) -/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ -#define BIT_EN_TXBCN1_RPT BIT(2) +#define BIT_SHIFT_BE_TRIGGER_NUM 12 +#define BIT_MASK_BE_TRIGGER_NUM 0xf +#define BIT_BE_TRIGGER_NUM(x) \ + (((x) & BIT_MASK_BE_TRIGGER_NUM) << BIT_SHIFT_BE_TRIGGER_NUM) +#define BITS_BE_TRIGGER_NUM \ + (BIT_MASK_BE_TRIGGER_NUM << BIT_SHIFT_BE_TRIGGER_NUM) +#define BIT_CLEAR_BE_TRIGGER_NUM(x) ((x) & (~BITS_BE_TRIGGER_NUM)) +#define BIT_GET_BE_TRIGGER_NUM(x) \ + (((x) >> BIT_SHIFT_BE_TRIGGER_NUM) & BIT_MASK_BE_TRIGGER_NUM) +#define BIT_SET_BE_TRIGGER_NUM(x, v) \ + (BIT_CLEAR_BE_TRIGGER_NUM(x) | BIT_BE_TRIGGER_NUM(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#define BIT_SHIFT_BE_TRIGGER_NUM_V1 8 +#define BIT_MASK_BE_TRIGGER_NUM_V1 0xf +#define BIT_BE_TRIGGER_NUM_V1(x) \ + (((x) & BIT_MASK_BE_TRIGGER_NUM_V1) << BIT_SHIFT_BE_TRIGGER_NUM_V1) +#define BITS_BE_TRIGGER_NUM_V1 \ + (BIT_MASK_BE_TRIGGER_NUM_V1 << BIT_SHIFT_BE_TRIGGER_NUM_V1) +#define BIT_CLEAR_BE_TRIGGER_NUM_V1(x) ((x) & (~BITS_BE_TRIGGER_NUM_V1)) +#define BIT_GET_BE_TRIGGER_NUM_V1(x) \ + (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1) & BIT_MASK_BE_TRIGGER_NUM_V1) +#define BIT_SET_BE_TRIGGER_NUM_V1(x, v) \ + (BIT_CLEAR_BE_TRIGGER_NUM_V1(x) | BIT_BE_TRIGGER_NUM_V1(v)) -/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#endif -#define BIT_CLI0_EN_RXBCN_RPT BIT(2) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE 8 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE 0xf +#define BIT_MAX_INTER_COLLISION_CNT_BE(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE) +#define BITS_MAX_INTER_COLLISION_CNT_BE \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_BE \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_BE(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_BE) +#define BIT_SET_MAX_INTER_COLLISION_CNT_BE(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE(x) | \ + BIT_MAX_INTER_COLLISION_CNT_BE(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8822B_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ -#define BIT_CLI0_EN_BCN_RPT BIT(2) +#define BIT_SHIFT_BK_TRIGGER_NUM 8 +#define BIT_MASK_BK_TRIGGER_NUM 0xf +#define BIT_BK_TRIGGER_NUM(x) \ + (((x) & BIT_MASK_BK_TRIGGER_NUM) << BIT_SHIFT_BK_TRIGGER_NUM) +#define BITS_BK_TRIGGER_NUM \ + (BIT_MASK_BK_TRIGGER_NUM << BIT_SHIFT_BK_TRIGGER_NUM) +#define BIT_CLEAR_BK_TRIGGER_NUM(x) ((x) & (~BITS_BK_TRIGGER_NUM)) +#define BIT_GET_BK_TRIGGER_NUM(x) \ + (((x) >> BIT_SHIFT_BK_TRIGGER_NUM) & BIT_MASK_BK_TRIGGER_NUM) +#define BIT_SET_BK_TRIGGER_NUM(x, v) \ + (BIT_CLEAR_BK_TRIGGER_NUM(x) | BIT_BK_TRIGGER_NUM(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#define BIT_SHIFT_VI_TRIGGER_NUM 4 +#define BIT_MASK_VI_TRIGGER_NUM 0xf +#define BIT_VI_TRIGGER_NUM(x) \ + (((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM) +#define BITS_VI_TRIGGER_NUM \ + (BIT_MASK_VI_TRIGGER_NUM << BIT_SHIFT_VI_TRIGGER_NUM) +#define BIT_CLEAR_VI_TRIGGER_NUM(x) ((x) & (~BITS_VI_TRIGGER_NUM)) +#define BIT_GET_VI_TRIGGER_NUM(x) \ + (((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM) +#define BIT_SET_VI_TRIGGER_NUM(x, v) \ + (BIT_CLEAR_VI_TRIGGER_NUM(x) | BIT_VI_TRIGGER_NUM(v)) -/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +#endif -#define BIT_DIS_BCNQ1_SUB BIT(1) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI 4 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI 0xf +#define BIT_MAX_INTER_COLLISION_CNT_VI(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI) +#define BITS_MAX_INTER_COLLISION_CNT_VI \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_VI \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_VI(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_VI) +#define BIT_SET_MAX_INTER_COLLISION_CNT_VI(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI(x) | \ + BIT_MAX_INTER_COLLISION_CNT_VI(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ -#define BIT_CLI0_ENP2P_CTWINDOW BIT(1) -#define BIT_CLI0_ENP2P_BCNQ_AREA BIT(0) +#define BIT_SHIFT_VO_TRIGGER_NUM 0 +#define BIT_MASK_VO_TRIGGER_NUM 0xf +#define BIT_VO_TRIGGER_NUM(x) \ + (((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM) +#define BITS_VO_TRIGGER_NUM \ + (BIT_MASK_VO_TRIGGER_NUM << BIT_SHIFT_VO_TRIGGER_NUM) +#define BIT_CLEAR_VO_TRIGGER_NUM(x) ((x) & (~BITS_VO_TRIGGER_NUM)) +#define BIT_GET_VO_TRIGGER_NUM(x) \ + (((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM) +#define BIT_SET_VO_TRIGGER_NUM(x, v) \ + (BIT_CLEAR_VO_TRIGGER_NUM(x) | BIT_VO_TRIGGER_NUM(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO 0 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO 0xf +#define BIT_MAX_INTER_COLLISION_CNT_VO(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO) +#define BITS_MAX_INTER_COLLISION_CNT_VO \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_VO \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_VO(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_VO) +#define BIT_SET_MAX_INTER_COLLISION_CNT_VO(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO(x) | \ + BIT_MAX_INTER_COLLISION_CNT_VO(v)) -/* 2 REG_MBID_NUM (Offset 0x0552) */ +#endif -#define BIT_EN_PRE_DL_BEACON BIT(3) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MBID_BCN_NUM 0 -#define BIT_MASK_MBID_BCN_NUM 0x7 -#define BIT_MBID_BCN_NUM(x) (((x) & BIT_MASK_MBID_BCN_NUM) << BIT_SHIFT_MBID_BCN_NUM) -#define BIT_GET_MBID_BCN_NUM(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM) & BIT_MASK_MBID_BCN_NUM) +/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ +#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 +#define BIT_MASK_TBTT_HOLD_TIME_AP 0xfff +#define BIT_TBTT_HOLD_TIME_AP(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP) +#define BITS_TBTT_HOLD_TIME_AP \ + (BIT_MASK_TBTT_HOLD_TIME_AP << BIT_SHIFT_TBTT_HOLD_TIME_AP) +#define BIT_CLEAR_TBTT_HOLD_TIME_AP(x) ((x) & (~BITS_TBTT_HOLD_TIME_AP)) +#define BIT_GET_TBTT_HOLD_TIME_AP(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP) +#define BIT_SET_TBTT_HOLD_TIME_AP(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_AP(x) | BIT_TBTT_HOLD_TIME_AP(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ - -#define BIT_P2P_PWR_RST1 BIT(6) -#define BIT_SCHEDULER_RST BIT(5) +#define BIT_SHIFT_TBTT_HOLD_TIME_INFRA 4 +#define BIT_MASK_TBTT_HOLD_TIME_INFRA 0xf +#define BIT_TBTT_HOLD_TIME_INFRA(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_INFRA) \ + << BIT_SHIFT_TBTT_HOLD_TIME_INFRA) +#define BITS_TBTT_HOLD_TIME_INFRA \ + (BIT_MASK_TBTT_HOLD_TIME_INFRA << BIT_SHIFT_TBTT_HOLD_TIME_INFRA) +#define BIT_CLEAR_TBTT_HOLD_TIME_INFRA(x) ((x) & (~BITS_TBTT_HOLD_TIME_INFRA)) +#define BIT_GET_TBTT_HOLD_TIME_INFRA(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_INFRA) & \ + BIT_MASK_TBTT_HOLD_TIME_INFRA) +#define BIT_SET_TBTT_HOLD_TIME_INFRA(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_INFRA(x) | BIT_TBTT_HOLD_TIME_INFRA(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_P2PPS_STATE (Offset 0x0543) */ +#define BIT_POWER_STATE BIT(7) +#define BIT_CTWINDOW_ON BIT(6) +#define BIT_BEACON_AREA_ON BIT(5) +#define BIT_CTWIN_EARLY_DISTX BIT(4) +#define BIT_NOA1_OFF_PERIOD BIT(3) +#define BIT_FORCE_DOZE1 BIT(2) +#define BIT_NOA0_OFF_PERIOD BIT(1) +#define BIT_FORCE_DOZE0 BIT(0) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_RD_NAV_NXT (Offset 0x0544) */ -#define BIT_FREECNT_RST BIT(5) +#define BIT_SHIFT_RD_NAV_PROT_NXT 0 +#define BIT_MASK_RD_NAV_PROT_NXT 0xffff +#define BIT_RD_NAV_PROT_NXT(x) \ + (((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT) +#define BITS_RD_NAV_PROT_NXT \ + (BIT_MASK_RD_NAV_PROT_NXT << BIT_SHIFT_RD_NAV_PROT_NXT) +#define BIT_CLEAR_RD_NAV_PROT_NXT(x) ((x) & (~BITS_RD_NAV_PROT_NXT)) +#define BIT_GET_RD_NAV_PROT_NXT(x) \ + (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT) +#define BIT_SET_RD_NAV_PROT_NXT(x, v) \ + (BIT_CLEAR_RD_NAV_PROT_NXT(x) | BIT_RD_NAV_PROT_NXT(v)) -#endif +/* 2 REG_NAV_PROT_LEN (Offset 0x0546) */ +#define BIT_DIS_RX_BSSID_FIT BIT(6) +#define BIT_DIS_TSF_UDT BIT(4) + +#define BIT_SHIFT_NAV_PROT_LEN 0 +#define BIT_MASK_NAV_PROT_LEN 0xffff +#define BIT_NAV_PROT_LEN(x) \ + (((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN) +#define BITS_NAV_PROT_LEN (BIT_MASK_NAV_PROT_LEN << BIT_SHIFT_NAV_PROT_LEN) +#define BIT_CLEAR_NAV_PROT_LEN(x) ((x) & (~BITS_NAV_PROT_LEN)) +#define BIT_GET_NAV_PROT_LEN(x) \ + (((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN) +#define BIT_SET_NAV_PROT_LEN(x, v) \ + (BIT_CLEAR_NAV_PROT_LEN(x) | BIT_NAV_PROT_LEN(v)) + +#define BIT_SHIFT_DRVERLYITV 0 +#define BIT_MASK_DRVERLYITV 0xff +#define BIT_DRVERLYITV(x) (((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV) +#define BITS_DRVERLYITV (BIT_MASK_DRVERLYITV << BIT_SHIFT_DRVERLYITV) +#define BIT_CLEAR_DRVERLYITV(x) ((x) & (~BITS_DRVERLYITV)) +#define BIT_GET_DRVERLYITV(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV) +#define BIT_SET_DRVERLYITV(x, v) (BIT_CLEAR_DRVERLYITV(x) | BIT_DRVERLYITV(v)) + +#define BIT_SHIFT_BCNDMATIM 0 +#define BIT_MASK_BCNDMATIM 0xff +#define BIT_BCNDMATIM(x) (((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM) +#define BITS_BCNDMATIM (BIT_MASK_BCNDMATIM << BIT_SHIFT_BCNDMATIM) +#define BIT_CLEAR_BCNDMATIM(x) ((x) & (~BITS_BCNDMATIM)) +#define BIT_GET_BCNDMATIM(x) (((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM) +#define BIT_SET_BCNDMATIM(x, v) (BIT_CLEAR_BCNDMATIM(x) | BIT_BCNDMATIM(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTM_CTRL (Offset 0x0548) */ +#define BIT_SHIFT_FTM_TSF_R2T_PORT 22 +#define BIT_MASK_FTM_TSF_R2T_PORT 0x7 +#define BIT_FTM_TSF_R2T_PORT(x) \ + (((x) & BIT_MASK_FTM_TSF_R2T_PORT) << BIT_SHIFT_FTM_TSF_R2T_PORT) +#define BITS_FTM_TSF_R2T_PORT \ + (BIT_MASK_FTM_TSF_R2T_PORT << BIT_SHIFT_FTM_TSF_R2T_PORT) +#define BIT_CLEAR_FTM_TSF_R2T_PORT(x) ((x) & (~BITS_FTM_TSF_R2T_PORT)) +#define BIT_GET_FTM_TSF_R2T_PORT(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT) & BIT_MASK_FTM_TSF_R2T_PORT) +#define BIT_SET_FTM_TSF_R2T_PORT(x, v) \ + (BIT_CLEAR_FTM_TSF_R2T_PORT(x) | BIT_FTM_TSF_R2T_PORT(v)) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#endif -#define BIT_P2P_PWR_RST0 BIT(4) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FTM_PTT (Offset 0x0548) */ +#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL 22 +#define BIT_MASK_FTM_PTT_TSF_R2T_SEL 0x7 +#define BIT_FTM_PTT_TSF_R2T_SEL(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL) << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL) +#define BITS_FTM_PTT_TSF_R2T_SEL \ + (BIT_MASK_FTM_PTT_TSF_R2T_SEL << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL) +#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_R2T_SEL)) +#define BIT_GET_FTM_PTT_TSF_R2T_SEL(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL) & BIT_MASK_FTM_PTT_TSF_R2T_SEL) +#define BIT_SET_FTM_PTT_TSF_R2T_SEL(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_R2T_SEL(x) | BIT_FTM_PTT_TSF_R2T_SEL(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_FTM_CTRL (Offset 0x0548) */ -#define BIT_TSFTR_CLI3_RST BIT(4) +#define BIT_SHIFT_FTM_TSF_T2R_PORT 19 +#define BIT_MASK_FTM_TSF_T2R_PORT 0x7 +#define BIT_FTM_TSF_T2R_PORT(x) \ + (((x) & BIT_MASK_FTM_TSF_T2R_PORT) << BIT_SHIFT_FTM_TSF_T2R_PORT) +#define BITS_FTM_TSF_T2R_PORT \ + (BIT_MASK_FTM_TSF_T2R_PORT << BIT_SHIFT_FTM_TSF_T2R_PORT) +#define BIT_CLEAR_FTM_TSF_T2R_PORT(x) ((x) & (~BITS_FTM_TSF_T2R_PORT)) +#define BIT_GET_FTM_TSF_T2R_PORT(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT) & BIT_MASK_FTM_TSF_T2R_PORT) +#define BIT_SET_FTM_TSF_T2R_PORT(x, v) \ + (BIT_CLEAR_FTM_TSF_T2R_PORT(x) | BIT_FTM_TSF_T2R_PORT(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTM_PTT (Offset 0x0548) */ +#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL 19 +#define BIT_MASK_FTM_PTT_TSF_T2R_SEL 0x7 +#define BIT_FTM_PTT_TSF_T2R_SEL(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL) << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL) +#define BITS_FTM_PTT_TSF_T2R_SEL \ + (BIT_MASK_FTM_PTT_TSF_T2R_SEL << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL) +#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_T2R_SEL)) +#define BIT_GET_FTM_PTT_TSF_T2R_SEL(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL) & BIT_MASK_FTM_PTT_TSF_T2R_SEL) +#define BIT_SET_FTM_PTT_TSF_T2R_SEL(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_T2R_SEL(x) | BIT_FTM_PTT_TSF_T2R_SEL(v)) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#endif -#define BIT_TSFTR1_SYNC_EN BIT(3) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FTM_CTRL (Offset 0x0548) */ +#define BIT_SHIFT_FTM_PTT_PORT 16 +#define BIT_MASK_FTM_PTT_PORT 0x7 +#define BIT_FTM_PTT_PORT(x) \ + (((x) & BIT_MASK_FTM_PTT_PORT) << BIT_SHIFT_FTM_PTT_PORT) +#define BITS_FTM_PTT_PORT (BIT_MASK_FTM_PTT_PORT << BIT_SHIFT_FTM_PTT_PORT) +#define BIT_CLEAR_FTM_PTT_PORT(x) ((x) & (~BITS_FTM_PTT_PORT)) +#define BIT_GET_FTM_PTT_PORT(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_PORT) & BIT_MASK_FTM_PTT_PORT) +#define BIT_SET_FTM_PTT_PORT(x, v) \ + (BIT_CLEAR_FTM_PTT_PORT(x) | BIT_FTM_PTT_PORT(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_FTM_PTT (Offset 0x0548) */ -#define BIT_TSFTR_CLI2_RST BIT(3) +#define BIT_SHIFT_FTM_PTT_TSF_SEL 16 +#define BIT_MASK_FTM_PTT_TSF_SEL 0x7 +#define BIT_FTM_PTT_TSF_SEL(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_SEL) << BIT_SHIFT_FTM_PTT_TSF_SEL) +#define BITS_FTM_PTT_TSF_SEL \ + (BIT_MASK_FTM_PTT_TSF_SEL << BIT_SHIFT_FTM_PTT_TSF_SEL) +#define BIT_CLEAR_FTM_PTT_TSF_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_SEL)) +#define BIT_GET_FTM_PTT_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL) & BIT_MASK_FTM_PTT_TSF_SEL) +#define BIT_SET_FTM_PTT_TSF_SEL(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_SEL(x) | BIT_FTM_PTT_TSF_SEL(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTM_CTRL (Offset 0x0548) */ +#define BIT_SHIFT_FTM_PTT 0 +#define BIT_MASK_FTM_PTT 0xffff +#define BIT_FTM_PTT(x) (((x) & BIT_MASK_FTM_PTT) << BIT_SHIFT_FTM_PTT) +#define BITS_FTM_PTT (BIT_MASK_FTM_PTT << BIT_SHIFT_FTM_PTT) +#define BIT_CLEAR_FTM_PTT(x) ((x) & (~BITS_FTM_PTT)) +#define BIT_GET_FTM_PTT(x) (((x) >> BIT_SHIFT_FTM_PTT) & BIT_MASK_FTM_PTT) +#define BIT_SET_FTM_PTT(x, v) (BIT_CLEAR_FTM_PTT(x) | BIT_FTM_PTT(v)) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#endif -#define BIT_TSFTR_SYNC_EN BIT(2) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FTM_PTT (Offset 0x0548) */ +#define BIT_SHIFT_FTM_PTT_VALUE 0 +#define BIT_MASK_FTM_PTT_VALUE 0xffff +#define BIT_FTM_PTT_VALUE(x) \ + (((x) & BIT_MASK_FTM_PTT_VALUE) << BIT_SHIFT_FTM_PTT_VALUE) +#define BITS_FTM_PTT_VALUE (BIT_MASK_FTM_PTT_VALUE << BIT_SHIFT_FTM_PTT_VALUE) +#define BIT_CLEAR_FTM_PTT_VALUE(x) ((x) & (~BITS_FTM_PTT_VALUE)) +#define BIT_GET_FTM_PTT_VALUE(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_VALUE) & BIT_MASK_FTM_PTT_VALUE) +#define BIT_SET_FTM_PTT_VALUE(x, v) \ + (BIT_CLEAR_FTM_PTT_VALUE(x) | BIT_FTM_PTT_VALUE(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_FTM_TSF_CNT (Offset 0x054C) */ -#define BIT_TSFTR_CLI1_RST BIT(2) +#define BIT_SHIFT_FTM_TSF_R2T 16 +#define BIT_MASK_FTM_TSF_R2T 0xffff +#define BIT_FTM_TSF_R2T(x) \ + (((x) & BIT_MASK_FTM_TSF_R2T) << BIT_SHIFT_FTM_TSF_R2T) +#define BITS_FTM_TSF_R2T (BIT_MASK_FTM_TSF_R2T << BIT_SHIFT_FTM_TSF_R2T) +#define BIT_CLEAR_FTM_TSF_R2T(x) ((x) & (~BITS_FTM_TSF_R2T)) +#define BIT_GET_FTM_TSF_R2T(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_R2T) & BIT_MASK_FTM_TSF_R2T) +#define BIT_SET_FTM_TSF_R2T(x, v) \ + (BIT_CLEAR_FTM_TSF_R2T(x) | BIT_FTM_TSF_R2T(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTM_TSF (Offset 0x054C) */ +#define BIT_SHIFT_FTM_T2_TSF 16 +#define BIT_MASK_FTM_T2_TSF 0xffff +#define BIT_FTM_T2_TSF(x) (((x) & BIT_MASK_FTM_T2_TSF) << BIT_SHIFT_FTM_T2_TSF) +#define BITS_FTM_T2_TSF (BIT_MASK_FTM_T2_TSF << BIT_SHIFT_FTM_T2_TSF) +#define BIT_CLEAR_FTM_T2_TSF(x) ((x) & (~BITS_FTM_T2_TSF)) +#define BIT_GET_FTM_T2_TSF(x) \ + (((x) >> BIT_SHIFT_FTM_T2_TSF) & BIT_MASK_FTM_T2_TSF) +#define BIT_SET_FTM_T2_TSF(x, v) (BIT_CLEAR_FTM_T2_TSF(x) | BIT_FTM_T2_TSF(v)) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#endif -#define BIT_TSFTR1_RST BIT(1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FTM_TSF_CNT (Offset 0x054C) */ +#define BIT_SHIFT_FTM_TSF_T2R 0 +#define BIT_MASK_FTM_TSF_T2R 0xffff +#define BIT_FTM_TSF_T2R(x) \ + (((x) & BIT_MASK_FTM_TSF_T2R) << BIT_SHIFT_FTM_TSF_T2R) +#define BITS_FTM_TSF_T2R (BIT_MASK_FTM_TSF_T2R << BIT_SHIFT_FTM_TSF_T2R) +#define BIT_CLEAR_FTM_TSF_T2R(x) ((x) & (~BITS_FTM_TSF_T2R)) +#define BIT_GET_FTM_TSF_T2R(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_T2R) & BIT_MASK_FTM_TSF_T2R) +#define BIT_SET_FTM_TSF_T2R(x, v) \ + (BIT_CLEAR_FTM_TSF_T2R(x) | BIT_FTM_TSF_T2R(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_FTM_TSF (Offset 0x054C) */ -#define BIT_TSFTR_CLI0_RST BIT(1) +#define BIT_SHIFT_FTM_T1_TSF 0 +#define BIT_MASK_FTM_T1_TSF 0xffff +#define BIT_FTM_T1_TSF(x) (((x) & BIT_MASK_FTM_T1_TSF) << BIT_SHIFT_FTM_T1_TSF) +#define BITS_FTM_T1_TSF (BIT_MASK_FTM_T1_TSF << BIT_SHIFT_FTM_T1_TSF) +#define BIT_CLEAR_FTM_T1_TSF(x) ((x) & (~BITS_FTM_T1_TSF)) +#define BIT_GET_FTM_T1_TSF(x) \ + (((x) >> BIT_SHIFT_FTM_T1_TSF) & BIT_MASK_FTM_T1_TSF) +#define BIT_SET_FTM_T1_TSF(x, v) (BIT_CLEAR_FTM_T1_TSF(x) | BIT_FTM_T1_TSF(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_BCN_CTRL (Offset 0x0550) */ + +#define BIT_P0_EN_TXBCN_RPT BIT(5) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_BCN_CTRL (Offset 0x0550) */ -#define BIT_TSFTR_RST BIT(0) +#define BIT_EN_BCN_FUNCTION BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL (Offset 0x0550) */ +#define BIT_EN_TXBCN_RPT BIT(2) -/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BCN_TIMER_SEL_FWRD 28 -#define BIT_MASK_BCN_TIMER_SEL_FWRD 0x7 -#define BIT_BCN_TIMER_SEL_FWRD(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD) -#define BIT_GET_BCN_TIMER_SEL_FWRD(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD) +/* 2 REG_BCN_CTRL (Offset 0x0550) */ +#define BIT_P0_EN_RXBCN_RPT BIT(2) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCN_CTRL (Offset 0x0550) */ -/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ - +#define BIT_DIS_BCNQ_SUB BIT(1) -#define BIT_SHIFT_BCN_SPACE1 16 -#define BIT_MASK_BCN_SPACE1 0xffff -#define BIT_BCN_SPACE1(x) (((x) & BIT_MASK_BCN_SPACE1) << BIT_SHIFT_BCN_SPACE1) -#define BIT_GET_BCN_SPACE1(x) (((x) >> BIT_SHIFT_BCN_SPACE1) & BIT_MASK_BCN_SPACE1) +/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +#define BIT_DIS_RX_BSSID_FIT1 BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#define BIT_CLI0_DIS_RX_BSSID_FIT BIT(6) -/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BCN_SPACE_CLINT0 16 -#define BIT_MASK_BCN_SPACE_CLINT0 0xfff -#define BIT_BCN_SPACE_CLINT0(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0) -#define BIT_GET_BCN_SPACE_CLINT0(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0) +/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +#define BIT_DIS_TSF1_UDT BIT(4) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#define BIT_CLI0_DIS_TSF_UDT BIT(4) -/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BCN_SPACE0 0 -#define BIT_MASK_BCN_SPACE0 0xffff -#define BIT_BCN_SPACE0(x) (((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0) -#define BIT_GET_BCN_SPACE0(x) (((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0) +/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +#define BIT_EN_BCN1_FUNCTION BIT(3) -/* 2 REG_DRVERLYINT (Offset 0x0558) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DRVERLYITV 0 -#define BIT_MASK_DRVERLYITV 0xff -#define BIT_DRVERLYITV(x) (((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV) -#define BIT_GET_DRVERLYITV(x) (((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV) +/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#define BIT_CLI0_EN_BCN_FUNCTION BIT(3) -/* 2 REG_BCNDMATIM (Offset 0x0559) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BCNDMATIM 0 -#define BIT_MASK_BCNDMATIM 0xff -#define BIT_BCNDMATIM(x) (((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM) -#define BIT_GET_BCNDMATIM(x) (((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM) +/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +#define BIT_EN_TXBCN1_RPT BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#define BIT_CLI0_EN_RXBCN_RPT BIT(2) -/* 2 REG_ATIMWND (Offset 0x055A) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_ATIMWND 0 -#define BIT_MASK_ATIMWND 0xffff -#define BIT_ATIMWND(x) (((x) & BIT_MASK_ATIMWND) << BIT_SHIFT_ATIMWND) -#define BIT_GET_ATIMWND(x) (((x) >> BIT_SHIFT_ATIMWND) & BIT_MASK_ATIMWND) +/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#define BIT_CLI0_EN_BCN_RPT BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +#define BIT_DIS_BCNQ1_SUB BIT(1) -/* 2 REG_ATIMWND (Offset 0x055A) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_ATIMWND0 0 -#define BIT_MASK_ATIMWND0 0xffff -#define BIT_ATIMWND0(x) (((x) & BIT_MASK_ATIMWND0) << BIT_SHIFT_ATIMWND0) -#define BIT_GET_ATIMWND0(x) (((x) >> BIT_SHIFT_ATIMWND0) & BIT_MASK_ATIMWND0) +/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#define BIT_CLI0_ENP2P_CTWINDOW BIT(1) +#define BIT_CLI0_ENP2P_BCNQ_AREA BIT(0) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBID_NUM (Offset 0x0552) */ +#define BIT_SHIFT_MBID_BCN_NUM_V2 4 +#define BIT_MASK_MBID_BCN_NUM_V2 0xf +#define BIT_MBID_BCN_NUM_V2(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_V2) << BIT_SHIFT_MBID_BCN_NUM_V2) +#define BITS_MBID_BCN_NUM_V2 \ + (BIT_MASK_MBID_BCN_NUM_V2 << BIT_SHIFT_MBID_BCN_NUM_V2) +#define BIT_CLEAR_MBID_BCN_NUM_V2(x) ((x) & (~BITS_MBID_BCN_NUM_V2)) +#define BIT_GET_MBID_BCN_NUM_V2(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_V2) & BIT_MASK_MBID_BCN_NUM_V2) +#define BIT_SET_MBID_BCN_NUM_V2(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_V2(x) | BIT_MBID_BCN_NUM_V2(v)) -/* 2 REG_USTIME_TSF (Offset 0x055C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_USTIME_TSF_V1 0 -#define BIT_MASK_USTIME_TSF_V1 0xff -#define BIT_USTIME_TSF_V1(x) (((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1) -#define BIT_GET_USTIME_TSF_V1(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1) +/* 2 REG_MBID_NUM (Offset 0x0552) */ +#define BIT_EN_PRE_DL_BEACON BIT(3) -/* 2 REG_BCN_MAX_ERR (Offset 0x055D) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BCN_MAX_ERR 0 -#define BIT_MASK_BCN_MAX_ERR 0xff -#define BIT_BCN_MAX_ERR(x) (((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR) -#define BIT_GET_BCN_MAX_ERR(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR) +/* 2 REG_MBID_NUM (Offset 0x0552) */ +#define BIT_SHIFT_MBID_BCN_NUM 0 +#define BIT_MASK_MBID_BCN_NUM 0x7 +#define BIT_MBID_BCN_NUM(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM) << BIT_SHIFT_MBID_BCN_NUM) +#define BITS_MBID_BCN_NUM (BIT_MASK_MBID_BCN_NUM << BIT_SHIFT_MBID_BCN_NUM) +#define BIT_CLEAR_MBID_BCN_NUM(x) ((x) & (~BITS_MBID_BCN_NUM)) +#define BIT_GET_MBID_BCN_NUM(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM) & BIT_MASK_MBID_BCN_NUM) +#define BIT_SET_MBID_BCN_NUM(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM(x) | BIT_MBID_BCN_NUM(v)) -/* 2 REG_RXTSF_OFFSET_CCK (Offset 0x055E) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CCK_RXTSF_OFFSET 0 -#define BIT_MASK_CCK_RXTSF_OFFSET 0xff -#define BIT_CCK_RXTSF_OFFSET(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET) -#define BIT_GET_CCK_RXTSF_OFFSET(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_P2P_PWR_RST1 BIT(6) +#define BIT_SCHEDULER_RST BIT(5) -/* 2 REG_RXTSF_OFFSET_OFDM (Offset 0x055F) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_OFDM_RXTSF_OFFSET 0 -#define BIT_MASK_OFDM_RXTSF_OFFSET 0xff -#define BIT_OFDM_RXTSF_OFFSET(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET) -#define BIT_GET_OFDM_RXTSF_OFFSET(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_FREECNT_RST BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_P2P_PWR_RST0 BIT(4) -/* 2 REG_TSFTR (Offset 0x0560) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TSF_TIMER 0 -#define BIT_MASK_TSF_TIMER 0xffffffffffffffffL -#define BIT_TSF_TIMER(x) (((x) & BIT_MASK_TSF_TIMER) << BIT_SHIFT_TSF_TIMER) -#define BIT_GET_TSF_TIMER(x) (((x) >> BIT_SHIFT_TSF_TIMER) & BIT_MASK_TSF_TIMER) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR_CLI3_RST BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR1_SYNC_EN BIT(3) -/* 2 REG_TSFTR (Offset 0x0560) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TSF_TIMER_V1 0 -#define BIT_MASK_TSF_TIMER_V1 0xffffffffL -#define BIT_TSF_TIMER_V1(x) (((x) & BIT_MASK_TSF_TIMER_V1) << BIT_SHIFT_TSF_TIMER_V1) -#define BIT_GET_TSF_TIMER_V1(x) (((x) >> BIT_SHIFT_TSF_TIMER_V1) & BIT_MASK_TSF_TIMER_V1) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR_CLI2_RST BIT(3) -/* 2 REG_TSFTR_1 (Offset 0x0564) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TSF_TIMER_V2 0 -#define BIT_MASK_TSF_TIMER_V2 0xffffffffL -#define BIT_TSF_TIMER_V2(x) (((x) & BIT_MASK_TSF_TIMER_V2) << BIT_SHIFT_TSF_TIMER_V2) -#define BIT_GET_TSF_TIMER_V2(x) (((x) >> BIT_SHIFT_TSF_TIMER_V2) & BIT_MASK_TSF_TIMER_V2) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR_SYNC_EN BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR_CLI1_RST BIT(2) -/* 2 REG_TSFTR1 (Offset 0x0568) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TSF_TIMER1 0 -#define BIT_MASK_TSF_TIMER1 0xffffffffffffffffL -#define BIT_TSF_TIMER1(x) (((x) & BIT_MASK_TSF_TIMER1) << BIT_SHIFT_TSF_TIMER1) -#define BIT_GET_TSF_TIMER1(x) (((x) >> BIT_SHIFT_TSF_TIMER1) & BIT_MASK_TSF_TIMER1) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR1_RST BIT(1) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR_CLI0_RST BIT(1) -/* 2 REG_FREERUN_CNT (Offset 0x0568) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FREERUN_CNT 0 -#define BIT_MASK_FREERUN_CNT 0xffffffffffffffffL -#define BIT_FREERUN_CNT(x) (((x) & BIT_MASK_FREERUN_CNT) << BIT_SHIFT_FREERUN_CNT) -#define BIT_GET_FREERUN_CNT(x) (((x) >> BIT_SHIFT_FREERUN_CNT) & BIT_MASK_FREERUN_CNT) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR_RST BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#define BIT_SHIFT_BCN_TIMER_SEL_FWRD 28 +#define BIT_MASK_BCN_TIMER_SEL_FWRD 0x7 +#define BIT_BCN_TIMER_SEL_FWRD(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD) +#define BITS_BCN_TIMER_SEL_FWRD \ + (BIT_MASK_BCN_TIMER_SEL_FWRD << BIT_SHIFT_BCN_TIMER_SEL_FWRD) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD)) +#define BIT_GET_BCN_TIMER_SEL_FWRD(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD) +#define BIT_SET_BCN_TIMER_SEL_FWRD(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) | BIT_BCN_TIMER_SEL_FWRD(v)) -/* 2 REG_FREERUN_CNT (Offset 0x0568) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FREERUN_CNT_V1 0 -#define BIT_MASK_FREERUN_CNT_V1 0xffffffffL -#define BIT_FREERUN_CNT_V1(x) (((x) & BIT_MASK_FREERUN_CNT_V1) << BIT_SHIFT_FREERUN_CNT_V1) -#define BIT_GET_FREERUN_CNT_V1(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V1) & BIT_MASK_FREERUN_CNT_V1) +/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#define BIT_SHIFT_BCN_SPACE1 16 +#define BIT_MASK_BCN_SPACE1 0xffff +#define BIT_BCN_SPACE1(x) (((x) & BIT_MASK_BCN_SPACE1) << BIT_SHIFT_BCN_SPACE1) +#define BITS_BCN_SPACE1 (BIT_MASK_BCN_SPACE1 << BIT_SHIFT_BCN_SPACE1) +#define BIT_CLEAR_BCN_SPACE1(x) ((x) & (~BITS_BCN_SPACE1)) +#define BIT_GET_BCN_SPACE1(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE1) & BIT_MASK_BCN_SPACE1) +#define BIT_SET_BCN_SPACE1(x, v) (BIT_CLEAR_BCN_SPACE1(x) | BIT_BCN_SPACE1(v)) -/* 2 REG_FREERUN_CNT_1 (Offset 0x056C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_FREERUN_CNT_V2 0 -#define BIT_MASK_FREERUN_CNT_V2 0xffffffffL -#define BIT_FREERUN_CNT_V2(x) (((x) & BIT_MASK_FREERUN_CNT_V2) << BIT_SHIFT_FREERUN_CNT_V2) -#define BIT_GET_FREERUN_CNT_V2(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V2) & BIT_MASK_FREERUN_CNT_V2) +/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#define BIT_SHIFT_BCN_SPACE_CLINT0 16 +#define BIT_MASK_BCN_SPACE_CLINT0 0xfff +#define BIT_BCN_SPACE_CLINT0(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0) +#define BITS_BCN_SPACE_CLINT0 \ + (BIT_MASK_BCN_SPACE_CLINT0 << BIT_SHIFT_BCN_SPACE_CLINT0) +#define BIT_CLEAR_BCN_SPACE_CLINT0(x) ((x) & (~BITS_BCN_SPACE_CLINT0)) +#define BIT_GET_BCN_SPACE_CLINT0(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0) +#define BIT_SET_BCN_SPACE_CLINT0(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT0(x) | BIT_BCN_SPACE_CLINT0(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#define BIT_SHIFT_BCN_SPACE0 0 +#define BIT_MASK_BCN_SPACE0 0xffff +#define BIT_BCN_SPACE0(x) (((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0) +#define BITS_BCN_SPACE0 (BIT_MASK_BCN_SPACE0 << BIT_SHIFT_BCN_SPACE0) +#define BIT_CLEAR_BCN_SPACE0(x) ((x) & (~BITS_BCN_SPACE0)) +#define BIT_GET_BCN_SPACE0(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0) +#define BIT_SET_BCN_SPACE0(x, v) (BIT_CLEAR_BCN_SPACE0(x) | BIT_BCN_SPACE0(v)) -/* 2 REG_ATIMWND1 (Offset 0x0570) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_ATIMWND1 0 -#define BIT_MASK_ATIMWND1 0xffff -#define BIT_ATIMWND1(x) (((x) & BIT_MASK_ATIMWND1) << BIT_SHIFT_ATIMWND1) -#define BIT_GET_ATIMWND1(x) (((x) >> BIT_SHIFT_ATIMWND1) & BIT_MASK_ATIMWND1) +/* 2 REG_ATIMWND (Offset 0x055A) */ +#define BIT_SHIFT_ATIMWND 0 +#define BIT_MASK_ATIMWND 0xffff +#define BIT_ATIMWND(x) (((x) & BIT_MASK_ATIMWND) << BIT_SHIFT_ATIMWND) +#define BITS_ATIMWND (BIT_MASK_ATIMWND << BIT_SHIFT_ATIMWND) +#define BIT_CLEAR_ATIMWND(x) ((x) & (~BITS_ATIMWND)) +#define BIT_GET_ATIMWND(x) (((x) >> BIT_SHIFT_ATIMWND) & BIT_MASK_ATIMWND) +#define BIT_SET_ATIMWND(x, v) (BIT_CLEAR_ATIMWND(x) | BIT_ATIMWND(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ATIMWND (Offset 0x055A) */ +#define BIT_SHIFT_ATIMWND0 0 +#define BIT_MASK_ATIMWND0 0xffff +#define BIT_ATIMWND0(x) (((x) & BIT_MASK_ATIMWND0) << BIT_SHIFT_ATIMWND0) +#define BITS_ATIMWND0 (BIT_MASK_ATIMWND0 << BIT_SHIFT_ATIMWND0) +#define BIT_CLEAR_ATIMWND0(x) ((x) & (~BITS_ATIMWND0)) +#define BIT_GET_ATIMWND0(x) (((x) >> BIT_SHIFT_ATIMWND0) & BIT_MASK_ATIMWND0) +#define BIT_SET_ATIMWND0(x, v) (BIT_CLEAR_ATIMWND0(x) | BIT_ATIMWND0(v)) -/* 2 REG_ATIMWND1_V1 (Offset 0x0570) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_ATIMWND1_V1 0 -#define BIT_MASK_ATIMWND1_V1 0xff -#define BIT_ATIMWND1_V1(x) (((x) & BIT_MASK_ATIMWND1_V1) << BIT_SHIFT_ATIMWND1_V1) -#define BIT_GET_ATIMWND1_V1(x) (((x) >> BIT_SHIFT_ATIMWND1_V1) & BIT_MASK_ATIMWND1_V1) +/* 2 REG_USTIME_TSF (Offset 0x055C) */ +#define BIT_SHIFT_USTIME_TSF_V1 0 +#define BIT_MASK_USTIME_TSF_V1 0xff +#define BIT_USTIME_TSF_V1(x) \ + (((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1) +#define BITS_USTIME_TSF_V1 (BIT_MASK_USTIME_TSF_V1 << BIT_SHIFT_USTIME_TSF_V1) +#define BIT_CLEAR_USTIME_TSF_V1(x) ((x) & (~BITS_USTIME_TSF_V1)) +#define BIT_GET_USTIME_TSF_V1(x) \ + (((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1) +#define BIT_SET_USTIME_TSF_V1(x, v) \ + (BIT_CLEAR_USTIME_TSF_V1(x) | BIT_USTIME_TSF_V1(v)) -/* 2 REG_TBTT_PROHIBIT_INFRA (Offset 0x0571) */ +/* 2 REG_BCN_MAX_ERR (Offset 0x055D) */ +#define BIT_SHIFT_BCN_MAX_ERR 0 +#define BIT_MASK_BCN_MAX_ERR 0xff +#define BIT_BCN_MAX_ERR(x) \ + (((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR) +#define BITS_BCN_MAX_ERR (BIT_MASK_BCN_MAX_ERR << BIT_SHIFT_BCN_MAX_ERR) +#define BIT_CLEAR_BCN_MAX_ERR(x) ((x) & (~BITS_BCN_MAX_ERR)) +#define BIT_GET_BCN_MAX_ERR(x) \ + (((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR) +#define BIT_SET_BCN_MAX_ERR(x, v) \ + (BIT_CLEAR_BCN_MAX_ERR(x) | BIT_BCN_MAX_ERR(v)) -#define BIT_SHIFT_TBTT_PROHIBIT_INFRA 0 -#define BIT_MASK_TBTT_PROHIBIT_INFRA 0xff -#define BIT_TBTT_PROHIBIT_INFRA(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA) -#define BIT_GET_TBTT_PROHIBIT_INFRA(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA) +/* 2 REG_RXTSF_OFFSET_CCK (Offset 0x055E) */ +#define BIT_SHIFT_CCK_RXTSF_OFFSET 0 +#define BIT_MASK_CCK_RXTSF_OFFSET 0xff +#define BIT_CCK_RXTSF_OFFSET(x) \ + (((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET) +#define BITS_CCK_RXTSF_OFFSET \ + (BIT_MASK_CCK_RXTSF_OFFSET << BIT_SHIFT_CCK_RXTSF_OFFSET) +#define BIT_CLEAR_CCK_RXTSF_OFFSET(x) ((x) & (~BITS_CCK_RXTSF_OFFSET)) +#define BIT_GET_CCK_RXTSF_OFFSET(x) \ + (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET) +#define BIT_SET_CCK_RXTSF_OFFSET(x, v) \ + (BIT_CLEAR_CCK_RXTSF_OFFSET(x) | BIT_CCK_RXTSF_OFFSET(v)) -#endif +/* 2 REG_RXTSF_OFFSET_OFDM (Offset 0x055F) */ + +#define BIT_SHIFT_OFDM_RXTSF_OFFSET 0 +#define BIT_MASK_OFDM_RXTSF_OFFSET 0xff +#define BIT_OFDM_RXTSF_OFFSET(x) \ + (((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET) +#define BITS_OFDM_RXTSF_OFFSET \ + (BIT_MASK_OFDM_RXTSF_OFFSET << BIT_SHIFT_OFDM_RXTSF_OFFSET) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET(x) ((x) & (~BITS_OFDM_RXTSF_OFFSET)) +#define BIT_GET_OFDM_RXTSF_OFFSET(x) \ + (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET) +#define BIT_SET_OFDM_RXTSF_OFFSET(x, v) \ + (BIT_CLEAR_OFDM_RXTSF_OFFSET(x) | BIT_OFDM_RXTSF_OFFSET(v)) +#define BIT_SHIFT_CTWND 0 +#define BIT_MASK_CTWND 0xff +#define BIT_CTWND(x) (((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND) +#define BITS_CTWND (BIT_MASK_CTWND << BIT_SHIFT_CTWND) +#define BIT_CLEAR_CTWND(x) ((x) & (~BITS_CTWND)) +#define BIT_GET_CTWND(x) (((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND) +#define BIT_SET_CTWND(x, v) (BIT_CLEAR_CTWND(x) | BIT_CTWND(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_CTWND (Offset 0x0572) */ +/* 2 REG_TSFTR (Offset 0x0560) */ +#define BIT_SHIFT_TSF_TIMER 0 +#define BIT_MASK_TSF_TIMER 0xffffffffffffffffL +#define BIT_TSF_TIMER(x) (((x) & BIT_MASK_TSF_TIMER) << BIT_SHIFT_TSF_TIMER) +#define BITS_TSF_TIMER (BIT_MASK_TSF_TIMER << BIT_SHIFT_TSF_TIMER) +#define BIT_CLEAR_TSF_TIMER(x) ((x) & (~BITS_TSF_TIMER)) +#define BIT_GET_TSF_TIMER(x) (((x) >> BIT_SHIFT_TSF_TIMER) & BIT_MASK_TSF_TIMER) +#define BIT_SET_TSF_TIMER(x, v) (BIT_CLEAR_TSF_TIMER(x) | BIT_TSF_TIMER(v)) -#define BIT_SHIFT_CTWND 0 -#define BIT_MASK_CTWND 0xff -#define BIT_CTWND(x) (((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND) -#define BIT_GET_CTWND(x) (((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BCNIVLCUNT (Offset 0x0573) */ +/* 2 REG_TSFTR (Offset 0x0560) */ +#define BIT_SHIFT_TSF_TIMER_V1 0 +#define BIT_MASK_TSF_TIMER_V1 0xffffffffL +#define BIT_TSF_TIMER_V1(x) \ + (((x) & BIT_MASK_TSF_TIMER_V1) << BIT_SHIFT_TSF_TIMER_V1) +#define BITS_TSF_TIMER_V1 (BIT_MASK_TSF_TIMER_V1 << BIT_SHIFT_TSF_TIMER_V1) +#define BIT_CLEAR_TSF_TIMER_V1(x) ((x) & (~BITS_TSF_TIMER_V1)) +#define BIT_GET_TSF_TIMER_V1(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_V1) & BIT_MASK_TSF_TIMER_V1) +#define BIT_SET_TSF_TIMER_V1(x, v) \ + (BIT_CLEAR_TSF_TIMER_V1(x) | BIT_TSF_TIMER_V1(v)) -#define BIT_SHIFT_BCNIVLCUNT 0 -#define BIT_MASK_BCNIVLCUNT 0x7f -#define BIT_BCNIVLCUNT(x) (((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT) -#define BIT_GET_BCNIVLCUNT(x) (((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT) +/* 2 REG_TSFTR_1 (Offset 0x0564) */ +#define BIT_SHIFT_TSF_TIMER_V2 0 +#define BIT_MASK_TSF_TIMER_V2 0xffffffffL +#define BIT_TSF_TIMER_V2(x) \ + (((x) & BIT_MASK_TSF_TIMER_V2) << BIT_SHIFT_TSF_TIMER_V2) +#define BITS_TSF_TIMER_V2 (BIT_MASK_TSF_TIMER_V2 << BIT_SHIFT_TSF_TIMER_V2) +#define BIT_CLEAR_TSF_TIMER_V2(x) ((x) & (~BITS_TSF_TIMER_V2)) +#define BIT_GET_TSF_TIMER_V2(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_V2) & BIT_MASK_TSF_TIMER_V2) +#define BIT_SET_TSF_TIMER_V2(x, v) \ + (BIT_CLEAR_TSF_TIMER_V2(x) | BIT_TSF_TIMER_V2(v)) -/* 2 REG_BCNDROPCTRL (Offset 0x0574) */ +#endif -#define BIT_BEACON_DROP_EN BIT(7) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BEACON_DROP_IVL 0 -#define BIT_MASK_BEACON_DROP_IVL 0x7f -#define BIT_BEACON_DROP_IVL(x) (((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL) -#define BIT_GET_BEACON_DROP_IVL(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL) +/* 2 REG_TSFTR1 (Offset 0x0568) */ +#define BIT_SHIFT_TSF_TIMER1 0 +#define BIT_MASK_TSF_TIMER1 0xffffffffffffffffL +#define BIT_TSF_TIMER1(x) (((x) & BIT_MASK_TSF_TIMER1) << BIT_SHIFT_TSF_TIMER1) +#define BITS_TSF_TIMER1 (BIT_MASK_TSF_TIMER1 << BIT_SHIFT_TSF_TIMER1) +#define BIT_CLEAR_TSF_TIMER1(x) ((x) & (~BITS_TSF_TIMER1)) +#define BIT_GET_TSF_TIMER1(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER1) & BIT_MASK_TSF_TIMER1) +#define BIT_SET_TSF_TIMER1(x, v) (BIT_CLEAR_TSF_TIMER1(x) | BIT_TSF_TIMER1(v)) -/* 2 REG_HGQ_TIMEOUT_PERIOD (Offset 0x0575) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD 0 -#define BIT_MASK_HGQ_TIMEOUT_PERIOD 0xff -#define BIT_HGQ_TIMEOUT_PERIOD(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD) -#define BIT_GET_HGQ_TIMEOUT_PERIOD(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD) +/* 2 REG_FREERUN_CNT (Offset 0x0568) */ +#define BIT_SHIFT_FREERUN_CNT 0 +#define BIT_MASK_FREERUN_CNT 0xffffffffffffffffL +#define BIT_FREERUN_CNT(x) \ + (((x) & BIT_MASK_FREERUN_CNT) << BIT_SHIFT_FREERUN_CNT) +#define BITS_FREERUN_CNT (BIT_MASK_FREERUN_CNT << BIT_SHIFT_FREERUN_CNT) +#define BIT_CLEAR_FREERUN_CNT(x) ((x) & (~BITS_FREERUN_CNT)) +#define BIT_GET_FREERUN_CNT(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT) & BIT_MASK_FREERUN_CNT) +#define BIT_SET_FREERUN_CNT(x, v) \ + (BIT_CLEAR_FREERUN_CNT(x) | BIT_FREERUN_CNT(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FREERUN_CNT (Offset 0x0568) */ +#define BIT_SHIFT_FREERUN_CNT_V1 0 +#define BIT_MASK_FREERUN_CNT_V1 0xffffffffL +#define BIT_FREERUN_CNT_V1(x) \ + (((x) & BIT_MASK_FREERUN_CNT_V1) << BIT_SHIFT_FREERUN_CNT_V1) +#define BITS_FREERUN_CNT_V1 \ + (BIT_MASK_FREERUN_CNT_V1 << BIT_SHIFT_FREERUN_CNT_V1) +#define BIT_CLEAR_FREERUN_CNT_V1(x) ((x) & (~BITS_FREERUN_CNT_V1)) +#define BIT_GET_FREERUN_CNT_V1(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_V1) & BIT_MASK_FREERUN_CNT_V1) +#define BIT_SET_FREERUN_CNT_V1(x, v) \ + (BIT_CLEAR_FREERUN_CNT_V1(x) | BIT_FREERUN_CNT_V1(v)) -/* 2 REG_TXCMD_TIMEOUT_PERIOD (Offset 0x0576) */ +/* 2 REG_FREERUN_CNT_1 (Offset 0x056C) */ +#define BIT_SHIFT_FREERUN_CNT_V2 0 +#define BIT_MASK_FREERUN_CNT_V2 0xffffffffL +#define BIT_FREERUN_CNT_V2(x) \ + (((x) & BIT_MASK_FREERUN_CNT_V2) << BIT_SHIFT_FREERUN_CNT_V2) +#define BITS_FREERUN_CNT_V2 \ + (BIT_MASK_FREERUN_CNT_V2 << BIT_SHIFT_FREERUN_CNT_V2) +#define BIT_CLEAR_FREERUN_CNT_V2(x) ((x) & (~BITS_FREERUN_CNT_V2)) +#define BIT_GET_FREERUN_CNT_V2(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_V2) & BIT_MASK_FREERUN_CNT_V2) +#define BIT_SET_FREERUN_CNT_V2(x, v) \ + (BIT_CLEAR_FREERUN_CNT_V2(x) | BIT_FREERUN_CNT_V2(v)) -#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD 0 -#define BIT_MASK_TXCMD_TIMEOUT_PERIOD 0xff -#define BIT_TXCMD_TIMEOUT_PERIOD(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) -#define BIT_GET_TXCMD_TIMEOUT_PERIOD(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_ATIMWND1 (Offset 0x0570) */ +#define BIT_SHIFT_ATIMWND1 0 +#define BIT_MASK_ATIMWND1 0xffff +#define BIT_ATIMWND1(x) (((x) & BIT_MASK_ATIMWND1) << BIT_SHIFT_ATIMWND1) +#define BITS_ATIMWND1 (BIT_MASK_ATIMWND1 << BIT_SHIFT_ATIMWND1) +#define BIT_CLEAR_ATIMWND1(x) ((x) & (~BITS_ATIMWND1)) +#define BIT_GET_ATIMWND1(x) (((x) >> BIT_SHIFT_ATIMWND1) & BIT_MASK_ATIMWND1) +#define BIT_SET_ATIMWND1(x, v) (BIT_CLEAR_ATIMWND1(x) | BIT_ATIMWND1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ATIMWND1_V1 (Offset 0x0570) */ +#define BIT_SHIFT_ATIMWND1_V1 0 +#define BIT_MASK_ATIMWND1_V1 0xff +#define BIT_ATIMWND1_V1(x) \ + (((x) & BIT_MASK_ATIMWND1_V1) << BIT_SHIFT_ATIMWND1_V1) +#define BITS_ATIMWND1_V1 (BIT_MASK_ATIMWND1_V1 << BIT_SHIFT_ATIMWND1_V1) +#define BIT_CLEAR_ATIMWND1_V1(x) ((x) & (~BITS_ATIMWND1_V1)) +#define BIT_GET_ATIMWND1_V1(x) \ + (((x) >> BIT_SHIFT_ATIMWND1_V1) & BIT_MASK_ATIMWND1_V1) +#define BIT_SET_ATIMWND1_V1(x, v) \ + (BIT_CLEAR_ATIMWND1_V1(x) | BIT_ATIMWND1_V1(v)) -/* 2 REG_MISC_CTRL (Offset 0x0577) */ +/* 2 REG_TBTT_PROHIBIT_INFRA (Offset 0x0571) */ -#define BIT_DIS_MARK_TSF_US BIT(7) -#define BIT_EN_TSFAUTO_SYNC BIT(6) +#define BIT_SHIFT_TBTT_PROHIBIT_INFRA 0 +#define BIT_MASK_TBTT_PROHIBIT_INFRA 0xff +#define BIT_TBTT_PROHIBIT_INFRA(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA) +#define BITS_TBTT_PROHIBIT_INFRA \ + (BIT_MASK_TBTT_PROHIBIT_INFRA << BIT_SHIFT_TBTT_PROHIBIT_INFRA) +#define BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) ((x) & (~BITS_TBTT_PROHIBIT_INFRA)) +#define BIT_GET_TBTT_PROHIBIT_INFRA(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA) +#define BIT_SET_TBTT_PROHIBIT_INFRA(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) | BIT_TBTT_PROHIBIT_INFRA(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_BCNIVLCUNT (Offset 0x0573) */ -/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_SHIFT_BCNIVLCUNT 0 +#define BIT_MASK_BCNIVLCUNT 0x7f +#define BIT_BCNIVLCUNT(x) (((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT) +#define BITS_BCNIVLCUNT (BIT_MASK_BCNIVLCUNT << BIT_SHIFT_BCNIVLCUNT) +#define BIT_CLEAR_BCNIVLCUNT(x) ((x) & (~BITS_BCNIVLCUNT)) +#define BIT_GET_BCNIVLCUNT(x) \ + (((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT) +#define BIT_SET_BCNIVLCUNT(x, v) (BIT_CLEAR_BCNIVLCUNT(x) | BIT_BCNIVLCUNT(v)) -#define BIT_DIS_TRX_CAL_BCN BIT(5) -#define BIT_DIS_TX_CAL_TBTT BIT(4) -#define BIT_EN_FREECNT BIT(3) -#define BIT_BCN_AGGRESSION BIT(2) +/* 2 REG_BCNDROPCTRL (Offset 0x0574) */ -#define BIT_SHIFT_DIS_SECONDARY_CCA 0 -#define BIT_MASK_DIS_SECONDARY_CCA 0x3 -#define BIT_DIS_SECONDARY_CCA(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA) -#define BIT_GET_DIS_SECONDARY_CCA(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA) +#define BIT_BEACON_DROP_EN BIT(7) +#define BIT_SHIFT_BEACON_DROP_IVL 0 +#define BIT_MASK_BEACON_DROP_IVL 0x7f +#define BIT_BEACON_DROP_IVL(x) \ + (((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL) +#define BITS_BEACON_DROP_IVL \ + (BIT_MASK_BEACON_DROP_IVL << BIT_SHIFT_BEACON_DROP_IVL) +#define BIT_CLEAR_BEACON_DROP_IVL(x) ((x) & (~BITS_BEACON_DROP_IVL)) +#define BIT_GET_BEACON_DROP_IVL(x) \ + (((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL) +#define BIT_SET_BEACON_DROP_IVL(x, v) \ + (BIT_CLEAR_BEACON_DROP_IVL(x) | BIT_BEACON_DROP_IVL(v)) -/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +/* 2 REG_HGQ_TIMEOUT_PERIOD (Offset 0x0575) */ -#define BIT_CLI1_DIS_RX_BSSID_FIT BIT(6) -#define BIT_CLI1_DIS_TSF_UDT BIT(4) -#define BIT_CLI1_EN_BCN_FUNCTION BIT(3) +#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD 0 +#define BIT_MASK_HGQ_TIMEOUT_PERIOD 0xff +#define BIT_HGQ_TIMEOUT_PERIOD(x) \ + (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD) +#define BITS_HGQ_TIMEOUT_PERIOD \ + (BIT_MASK_HGQ_TIMEOUT_PERIOD << BIT_SHIFT_HGQ_TIMEOUT_PERIOD) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) ((x) & (~BITS_HGQ_TIMEOUT_PERIOD)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD(x) \ + (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD) +#define BIT_SET_HGQ_TIMEOUT_PERIOD(x, v) \ + (BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) | BIT_HGQ_TIMEOUT_PERIOD(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_TXCMD_TIMEOUT_PERIOD (Offset 0x0576) */ + +#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD 0 +#define BIT_MASK_TXCMD_TIMEOUT_PERIOD 0xff +#define BIT_TXCMD_TIMEOUT_PERIOD(x) \ + (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) +#define BITS_TXCMD_TIMEOUT_PERIOD \ + (BIT_MASK_TXCMD_TIMEOUT_PERIOD << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD(x) \ + (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) & \ + BIT_MASK_TXCMD_TIMEOUT_PERIOD) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD(x, v) \ + (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) | BIT_TXCMD_TIMEOUT_PERIOD(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +/* 2 REG_MISC_CTRL (Offset 0x0577) */ -#define BIT_CLI1_EN_RXBCN_RPT BIT(2) +#define BIT_DIS_MARK_TSF_US BIT(7) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_DIS_MARK_TSF_US_V2 BIT(7) -/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_MISC_CTRL (Offset 0x0577) */ -#define BIT_CLI1_EN_BCN_RPT BIT(2) +#define BIT_EN_TSFAUTO_SYNC BIT(6) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_AUTO_SYNC_BY_TBTT BIT(6) -/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +#endif -#define BIT_CLI1_ENP2P_CTWINDOW BIT(1) -#define BIT_CLI1_ENP2P_BCNQ_AREA BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +/* 2 REG_MISC_CTRL (Offset 0x0577) */ -#define BIT_CLI2_DIS_RX_BSSID_FIT BIT(6) -#define BIT_CLI2_DIS_TSF_UDT BIT(4) -#define BIT_CLI2_EN_BCN_FUNCTION BIT(3) +#define BIT_DIS_TRX_CAL_BCN BIT(5) +#define BIT_DIS_TX_CAL_TBTT BIT(4) +#define BIT_EN_FREECNT BIT(3) +#define BIT_BCN_AGGRESSION BIT(2) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_DIS_SECONDARY_CCA_80M BIT(2) +#define BIT_DIS_SECONDARY_CCA_40M BIT(1) -/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +#endif -#define BIT_CLI2_EN_RXBCN_RPT BIT(2) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_MISC_CTRL (Offset 0x0577) */ + +#define BIT_SHIFT_DIS_SECONDARY_CCA 0 +#define BIT_MASK_DIS_SECONDARY_CCA 0x3 +#define BIT_DIS_SECONDARY_CCA(x) \ + (((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA) +#define BITS_DIS_SECONDARY_CCA \ + (BIT_MASK_DIS_SECONDARY_CCA << BIT_SHIFT_DIS_SECONDARY_CCA) +#define BIT_CLEAR_DIS_SECONDARY_CCA(x) ((x) & (~BITS_DIS_SECONDARY_CCA)) +#define BIT_GET_DIS_SECONDARY_CCA(x) \ + (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA) +#define BIT_SET_DIS_SECONDARY_CCA(x, v) \ + (BIT_CLEAR_DIS_SECONDARY_CCA(x) | BIT_DIS_SECONDARY_CCA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_DIS_SECONDARY_CCA_20M BIT(0) -/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_CLI2_EN_BCN_RPT BIT(2) +/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ + +#define BIT_CLI1_DIS_RX_BSSID_FIT BIT(6) +#define BIT_CLI1_DIS_TSF_UDT BIT(4) +#define BIT_CLI1_EN_BCN_FUNCTION BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +#define BIT_CLI1_EN_RXBCN_RPT BIT(2) -/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +#endif -#define BIT_CLI2_ENP2P_CTWINDOW BIT(1) -#define BIT_CLI2_ENP2P_BCNQ_AREA BIT(0) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ -#define BIT_CLI3_DIS_RX_BSSID_FIT BIT(6) -#define BIT_CLI3_DIS_TSF_UDT BIT(4) -#define BIT_CLI3_EN_BCN_FUNCTION BIT(3) +#define BIT_CLI1_EN_BCN_RPT BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +#define BIT_CLI1_ENP2P_CTWINDOW BIT(1) +#define BIT_CLI1_ENP2P_BCNQ_AREA BIT(0) -/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ -#define BIT_CLI3_EN_RXBCN_RPT BIT(2) +#define BIT_CLI2_DIS_RX_BSSID_FIT BIT(6) +#define BIT_CLI2_DIS_TSF_UDT BIT(4) +#define BIT_CLI2_EN_BCN_FUNCTION BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +#define BIT_CLI2_EN_RXBCN_RPT BIT(2) -/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ -#define BIT_CLI3_EN_BCN_RPT BIT(2) +#define BIT_CLI2_EN_BCN_RPT BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +#define BIT_CLI2_ENP2P_CTWINDOW BIT(1) +#define BIT_CLI2_ENP2P_BCNQ_AREA BIT(0) /* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ -#define BIT_CLI3_ENP2P_CTWINDOW BIT(1) -#define BIT_CLI3_ENP2P_BCNQ_AREA BIT(0) +#define BIT_CLI3_DIS_RX_BSSID_FIT BIT(6) +#define BIT_CLI3_DIS_TSF_UDT BIT(4) +#define BIT_CLI3_EN_BCN_FUNCTION BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +#define BIT_CLI3_EN_RXBCN_RPT BIT(2) -/* 2 REG_EXTEND_CTRL (Offset 0x057B) */ +#endif -#define BIT_EN_TSFBIT32_RST_P2P2 BIT(5) -#define BIT_EN_TSFBIT32_RST_P2P1 BIT(4) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_PORT_SEL 0 -#define BIT_MASK_PORT_SEL 0x7 -#define BIT_PORT_SEL(x) (((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL) -#define BIT_GET_PORT_SEL(x) (((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL) +/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +#define BIT_CLI3_EN_BCN_RPT BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +#define BIT_CLI3_ENP2P_CTWINDOW BIT(1) +#define BIT_CLI3_ENP2P_BCNQ_AREA BIT(0) -/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ +#endif -#define BIT_P2P1_SPEC_POWER_STATE BIT(7) -#define BIT_P2P1_SPEC_CTWINDOW_ON BIT(6) -#define BIT_P2P1_SPEC_BCN_AREA_ON BIT(5) -#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX BIT(4) -#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD BIT(3) -#define BIT_P2P1_SPEC_FORCE_DOZE1 BIT(2) -#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD BIT(1) -#define BIT_P2P1_SPEC_FORCE_DOZE0 BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_P2PPS1_STATE (Offset 0x057D) */ +/* 2 REG_EXTEND_CTRL (Offset 0x057B) */ -#define BIT_P2P1_POWER_STATE BIT(7) -#define BIT_P2P1_CTWINDOW_ON BIT(6) -#define BIT_P2P1_BEACON_AREA_ON BIT(5) -#define BIT_P2P1_CTWIN_EARLY_DISTX BIT(4) -#define BIT_P2P1_NOA1_OFF_PERIOD BIT(3) -#define BIT_P2P1_FORCE_DOZE1 BIT(2) -#define BIT_P2P1_NOA0_OFF_PERIOD BIT(1) -#define BIT_P2P1_FORCE_DOZE0 BIT(0) +#define BIT_EN_TSFBIT32_RST_P2P2 BIT(5) +#define BIT_EN_TSFBIT32_RST_P2P1 BIT(4) -/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ +#define BIT_SHIFT_PORT_SEL 0 +#define BIT_MASK_PORT_SEL 0x7 +#define BIT_PORT_SEL(x) (((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL) +#define BITS_PORT_SEL (BIT_MASK_PORT_SEL << BIT_SHIFT_PORT_SEL) +#define BIT_CLEAR_PORT_SEL(x) ((x) & (~BITS_PORT_SEL)) +#define BIT_GET_PORT_SEL(x) (((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL) +#define BIT_SET_PORT_SEL(x, v) (BIT_CLEAR_PORT_SEL(x) | BIT_PORT_SEL(v)) + +#endif -#define BIT_P2P2_SPEC_POWER_STATE BIT(7) -#define BIT_P2P2_SPEC_CTWINDOW_ON BIT(6) -#define BIT_P2P2_SPEC_BCN_AREA_ON BIT(5) -#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX BIT(4) -#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD BIT(3) -#define BIT_P2P2_SPEC_FORCE_DOZE1 BIT(2) -#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD BIT(1) -#define BIT_P2P2_SPEC_FORCE_DOZE0 BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_P2PPS2_STATE (Offset 0x057F) */ +/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ -#define BIT_P2P2_POWER_STATE BIT(7) -#define BIT_P2P2_CTWINDOW_ON BIT(6) -#define BIT_P2P2_BEACON_AREA_ON BIT(5) -#define BIT_P2P2_CTWIN_EARLY_DISTX BIT(4) -#define BIT_P2P2_NOA1_OFF_PERIOD BIT(3) -#define BIT_P2P2_FORCE_DOZE1 BIT(2) -#define BIT_P2P2_NOA0_OFF_PERIOD BIT(1) -#define BIT_P2P2_FORCE_DOZE0 BIT(0) +#define BIT_P2P1_SPEC_POWER_STATE BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ +#define BIT_P2P1_SPEC_CTWINDOW_ON BIT(6) -/* 2 REG_PS_TIMER (Offset 0x0580) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PSTIMER_INT 5 -#define BIT_MASK_PSTIMER_INT 0x7ffffff -#define BIT_PSTIMER_INT(x) (((x) & BIT_MASK_PSTIMER_INT) << BIT_SHIFT_PSTIMER_INT) -#define BIT_GET_PSTIMER_INT(x) (((x) >> BIT_SHIFT_PSTIMER_INT) & BIT_MASK_PSTIMER_INT) +/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ +#define BIT_P2P1_SPEC_BCN_AREA_ON BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ +#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX BIT(4) +#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD BIT(3) +#define BIT_P2P1_SPEC_FORCE_DOZE1 BIT(2) +#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD BIT(1) +#define BIT_P2P1_SPEC_FORCE_DOZE0 BIT(0) -/* 2 REG_PS_TIMER0 (Offset 0x0580) */ +/* 2 REG_P2PPS1_STATE (Offset 0x057D) */ + +#define BIT_P2P1_POWER_STATE BIT(7) +#define BIT_P2P1_CTWINDOW_ON BIT(6) +#define BIT_P2P1_BEACON_AREA_ON BIT(5) +#define BIT_P2P1_CTWIN_EARLY_DISTX BIT(4) +#define BIT_P2P1_NOA1_OFF_PERIOD BIT(3) +#define BIT_P2P1_FORCE_DOZE1 BIT(2) +#define BIT_P2P1_NOA0_OFF_PERIOD BIT(1) +#define BIT_P2P1_FORCE_DOZE0 BIT(0) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PSTIMER0_INT 5 -#define BIT_MASK_PSTIMER0_INT 0x7ffffff -#define BIT_PSTIMER0_INT(x) (((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT) -#define BIT_GET_PSTIMER0_INT(x) (((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT) +/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ +#define BIT_P2P2_SPEC_POWER_STATE BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ +#define BIT_P2P2_SPEC_CTWINDOW_ON BIT(6) -/* 2 REG_PS_TIMER (Offset 0x0580) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PSTIMER_INT_V1 5 -#define BIT_MASK_PSTIMER_INT_V1 0x7ffffff -#define BIT_PSTIMER_INT_V1(x) (((x) & BIT_MASK_PSTIMER_INT_V1) << BIT_SHIFT_PSTIMER_INT_V1) -#define BIT_GET_PSTIMER_INT_V1(x) (((x) >> BIT_SHIFT_PSTIMER_INT_V1) & BIT_MASK_PSTIMER_INT_V1) +/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ +#define BIT_P2P2_SPEC_BCN_AREA_ON BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ -/* 2 REG_TIMER0 (Offset 0x0584) */ +#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX BIT(4) +#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD BIT(3) +#define BIT_P2P2_SPEC_FORCE_DOZE1 BIT(2) +#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD BIT(1) +#define BIT_P2P2_SPEC_FORCE_DOZE0 BIT(0) +/* 2 REG_P2PPS2_STATE (Offset 0x057F) */ -#define BIT_SHIFT_TIMER0_INT 5 -#define BIT_MASK_TIMER0_INT 0x7ffffff -#define BIT_TIMER0_INT(x) (((x) & BIT_MASK_TIMER0_INT) << BIT_SHIFT_TIMER0_INT) -#define BIT_GET_TIMER0_INT(x) (((x) >> BIT_SHIFT_TIMER0_INT) & BIT_MASK_TIMER0_INT) +#define BIT_P2P2_POWER_STATE BIT(7) +#define BIT_P2P2_CTWINDOW_ON BIT(6) +#define BIT_P2P2_BEACON_AREA_ON BIT(5) +#define BIT_P2P2_CTWIN_EARLY_DISTX BIT(4) +#define BIT_P2P2_NOA1_OFF_PERIOD BIT(3) +#define BIT_P2P2_FORCE_DOZE1 BIT(2) +#define BIT_P2P2_NOA0_OFF_PERIOD BIT(1) +#define BIT_P2P2_FORCE_DOZE0 BIT(0) +#define BIT_SHIFT_EARLY_128US 0 +#define BIT_MASK_EARLY_128US 0x7 +#define BIT_EARLY_128US(x) \ + (((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US) +#define BITS_EARLY_128US (BIT_MASK_EARLY_128US << BIT_SHIFT_EARLY_128US) +#define BIT_CLEAR_EARLY_128US(x) ((x) & (~BITS_EARLY_128US)) +#define BIT_GET_EARLY_128US(x) \ + (((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US) +#define BIT_SET_EARLY_128US(x, v) \ + (BIT_CLEAR_EARLY_128US(x) | BIT_EARLY_128US(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PS_TIMER (Offset 0x0580) */ +#define BIT_SHIFT_PSTIMER 5 +#define BIT_MASK_PSTIMER 0x7ffffff +#define BIT_PSTIMER(x) (((x) & BIT_MASK_PSTIMER) << BIT_SHIFT_PSTIMER) +#define BITS_PSTIMER (BIT_MASK_PSTIMER << BIT_SHIFT_PSTIMER) +#define BIT_CLEAR_PSTIMER(x) ((x) & (~BITS_PSTIMER)) +#define BIT_GET_PSTIMER(x) (((x) >> BIT_SHIFT_PSTIMER) & BIT_MASK_PSTIMER) +#define BIT_SET_PSTIMER(x, v) (BIT_CLEAR_PSTIMER(x) | BIT_PSTIMER(v)) -/* 2 REG_PS_TIMER1 (Offset 0x0584) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PSTIMER1_INT 5 -#define BIT_MASK_PSTIMER1_INT 0x7ffffff -#define BIT_PSTIMER1_INT(x) (((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT) -#define BIT_GET_PSTIMER1_INT(x) (((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT) +/* 2 REG_PS_TIMER0 (Offset 0x0580) */ +#define BIT_SHIFT_PSTIMER0_INT 5 +#define BIT_MASK_PSTIMER0_INT 0x7ffffff +#define BIT_PSTIMER0_INT(x) \ + (((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT) +#define BITS_PSTIMER0_INT (BIT_MASK_PSTIMER0_INT << BIT_SHIFT_PSTIMER0_INT) +#define BIT_CLEAR_PSTIMER0_INT(x) ((x) & (~BITS_PSTIMER0_INT)) +#define BIT_GET_PSTIMER0_INT(x) \ + (((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT) +#define BIT_SET_PSTIMER0_INT(x, v) \ + (BIT_CLEAR_PSTIMER0_INT(x) | BIT_PSTIMER0_INT(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TIMER0 (Offset 0x0584) */ + +#define BIT_SHIFT_TIMER0_INT 5 +#define BIT_MASK_TIMER0_INT 0x7ffffff +#define BIT_TIMER0_INT(x) (((x) & BIT_MASK_TIMER0_INT) << BIT_SHIFT_TIMER0_INT) +#define BITS_TIMER0_INT (BIT_MASK_TIMER0_INT << BIT_SHIFT_TIMER0_INT) +#define BIT_CLEAR_TIMER0_INT(x) ((x) & (~BITS_TIMER0_INT)) +#define BIT_GET_TIMER0_INT(x) \ + (((x) >> BIT_SHIFT_TIMER0_INT) & BIT_MASK_TIMER0_INT) +#define BIT_SET_TIMER0_INT(x, v) (BIT_CLEAR_TIMER0_INT(x) | BIT_TIMER0_INT(v)) -/* 2 REG_TIMER1 (Offset 0x0588) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TIMER1_INT 5 -#define BIT_MASK_TIMER1_INT 0x7ffffff -#define BIT_TIMER1_INT(x) (((x) & BIT_MASK_TIMER1_INT) << BIT_SHIFT_TIMER1_INT) -#define BIT_GET_TIMER1_INT(x) (((x) >> BIT_SHIFT_TIMER1_INT) & BIT_MASK_TIMER1_INT) +/* 2 REG_PS_TIMER1 (Offset 0x0584) */ +#define BIT_SHIFT_PSTIMER1_INT 5 +#define BIT_MASK_PSTIMER1_INT 0x7ffffff +#define BIT_PSTIMER1_INT(x) \ + (((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT) +#define BITS_PSTIMER1_INT (BIT_MASK_PSTIMER1_INT << BIT_SHIFT_PSTIMER1_INT) +#define BIT_CLEAR_PSTIMER1_INT(x) ((x) & (~BITS_PSTIMER1_INT)) +#define BIT_GET_PSTIMER1_INT(x) \ + (((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT) +#define BIT_SET_PSTIMER1_INT(x, v) \ + (BIT_CLEAR_PSTIMER1_INT(x) | BIT_PSTIMER1_INT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TIMER1 (Offset 0x0588) */ +#define BIT_SHIFT_TIMER1_INT 5 +#define BIT_MASK_TIMER1_INT 0x7ffffff +#define BIT_TIMER1_INT(x) (((x) & BIT_MASK_TIMER1_INT) << BIT_SHIFT_TIMER1_INT) +#define BITS_TIMER1_INT (BIT_MASK_TIMER1_INT << BIT_SHIFT_TIMER1_INT) +#define BIT_CLEAR_TIMER1_INT(x) ((x) & (~BITS_TIMER1_INT)) +#define BIT_GET_TIMER1_INT(x) \ + (((x) >> BIT_SHIFT_TIMER1_INT) & BIT_MASK_TIMER1_INT) +#define BIT_SET_TIMER1_INT(x, v) (BIT_CLEAR_TIMER1_INT(x) | BIT_TIMER1_INT(v)) -/* 2 REG_PS_TIMER2 (Offset 0x0588) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PSTIMER2_INT 5 -#define BIT_MASK_PSTIMER2_INT 0x7ffffff -#define BIT_PSTIMER2_INT(x) (((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT) -#define BIT_GET_PSTIMER2_INT(x) (((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT) +/* 2 REG_PS_TIMER2 (Offset 0x0588) */ +#define BIT_SHIFT_PSTIMER2_INT 5 +#define BIT_MASK_PSTIMER2_INT 0x7ffffff +#define BIT_PSTIMER2_INT(x) \ + (((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT) +#define BITS_PSTIMER2_INT (BIT_MASK_PSTIMER2_INT << BIT_SHIFT_PSTIMER2_INT) +#define BIT_CLEAR_PSTIMER2_INT(x) ((x) & (~BITS_PSTIMER2_INT)) +#define BIT_GET_PSTIMER2_INT(x) \ + (((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT) +#define BIT_SET_PSTIMER2_INT(x, v) \ + (BIT_CLEAR_PSTIMER2_INT(x) | BIT_PSTIMER2_INT(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_TBTT_CTN_AREA (Offset 0x058C) */ +#define BIT_SHIFT_TBTT_CTN_AREA 0 +#define BIT_MASK_TBTT_CTN_AREA 0xff +#define BIT_TBTT_CTN_AREA(x) \ + (((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA) +#define BITS_TBTT_CTN_AREA (BIT_MASK_TBTT_CTN_AREA << BIT_SHIFT_TBTT_CTN_AREA) +#define BIT_CLEAR_TBTT_CTN_AREA(x) ((x) & (~BITS_TBTT_CTN_AREA)) +#define BIT_GET_TBTT_CTN_AREA(x) \ + (((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA) +#define BIT_SET_TBTT_CTN_AREA(x, v) \ + (BIT_CLEAR_TBTT_CTN_AREA(x) | BIT_TBTT_CTN_AREA(v)) -#define BIT_SHIFT_TBTT_CTN_AREA 0 -#define BIT_MASK_TBTT_CTN_AREA 0xff -#define BIT_TBTT_CTN_AREA(x) (((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA) -#define BIT_GET_TBTT_CTN_AREA(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA) +/* 2 REG_FORCE_BCN_IFS (Offset 0x058E) */ +#define BIT_SHIFT_FORCE_BCN_IFS 0 +#define BIT_MASK_FORCE_BCN_IFS 0xff +#define BIT_FORCE_BCN_IFS(x) \ + (((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS) +#define BITS_FORCE_BCN_IFS (BIT_MASK_FORCE_BCN_IFS << BIT_SHIFT_FORCE_BCN_IFS) +#define BIT_CLEAR_FORCE_BCN_IFS(x) ((x) & (~BITS_FORCE_BCN_IFS)) +#define BIT_GET_FORCE_BCN_IFS(x) \ + (((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS) +#define BIT_SET_FORCE_BCN_IFS(x, v) \ + (BIT_CLEAR_FORCE_BCN_IFS(x) | BIT_FORCE_BCN_IFS(v)) -/* 2 REG_FORCE_BCN_IFS (Offset 0x058E) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_FORCE_BCN_IFS 0 -#define BIT_MASK_FORCE_BCN_IFS 0xff -#define BIT_FORCE_BCN_IFS(x) (((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS) -#define BIT_GET_FORCE_BCN_IFS(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS) +/* 2 REG_TXOP_MIN (Offset 0x0590) */ +#define BIT_NAV_BLK_HGQ BIT(15) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TXOP_MIN (Offset 0x0590) */ + +#define BIT_HIQ_NAV_BREAK_EN BIT(15) + +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_TXOP_MIN (Offset 0x0590) */ -#define BIT_NAV_BLK_HGQ BIT(15) -#define BIT_NAV_BLK_MGQ BIT(14) +#define BIT_NAV_BLK_MGQ BIT(14) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXOP_MIN (Offset 0x0590) */ +#define BIT_MGQ_NAV_BREAK_EN BIT(14) -/* 2 REG_TXOP_MIN (Offset 0x0590) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TXOP_MIN 0 -#define BIT_MASK_TXOP_MIN 0x3fff -#define BIT_TXOP_MIN(x) (((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN) -#define BIT_GET_TXOP_MIN(x) (((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN) +/* 2 REG_TXOP_MIN (Offset 0x0590) */ +#define BIT_SHIFT_TXOP_MIN 0 +#define BIT_MASK_TXOP_MIN 0x3fff +#define BIT_TXOP_MIN(x) (((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN) +#define BITS_TXOP_MIN (BIT_MASK_TXOP_MIN << BIT_SHIFT_TXOP_MIN) +#define BIT_CLEAR_TXOP_MIN(x) ((x) & (~BITS_TXOP_MIN)) +#define BIT_GET_TXOP_MIN(x) (((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN) +#define BIT_SET_TXOP_MIN(x, v) (BIT_CLEAR_TXOP_MIN(x) | BIT_TXOP_MIN(v)) /* 2 REG_PRE_BKF_TIME (Offset 0x0592) */ +#define BIT_SHIFT_PRE_BKF_TIME 0 +#define BIT_MASK_PRE_BKF_TIME 0xff +#define BIT_PRE_BKF_TIME(x) \ + (((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME) +#define BITS_PRE_BKF_TIME (BIT_MASK_PRE_BKF_TIME << BIT_SHIFT_PRE_BKF_TIME) +#define BIT_CLEAR_PRE_BKF_TIME(x) ((x) & (~BITS_PRE_BKF_TIME)) +#define BIT_GET_PRE_BKF_TIME(x) \ + (((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME) +#define BIT_SET_PRE_BKF_TIME(x, v) \ + (BIT_CLEAR_PRE_BKF_TIME(x) | BIT_PRE_BKF_TIME(v)) -#define BIT_SHIFT_PRE_BKF_TIME 0 -#define BIT_MASK_PRE_BKF_TIME 0xff -#define BIT_PRE_BKF_TIME(x) (((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME) -#define BIT_GET_PRE_BKF_TIME(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME) +#endif +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ +#define BIT_NOPKT_END_RTSMF BIT(7) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ -#define BIT_TXFAIL_BREACK_TXOP_EN BIT(3) +#define BIT_TBTT_RETRY BIT(4) #endif +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ + +#define BIT_TXOP_FAIL_BREAK BIT(3) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ -#define BIT_DTIM_BYPASS BIT(2) -#define BIT_RTS_NAV_TXOP BIT(1) -#define BIT_NOT_CROSS_TXOP BIT(0) +#define BIT_TXFAIL_BREACK_TXOP_EN BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ +#define BIT_DTIM_BYPASS BIT(2) -/* 2 REG_TBTT_INT_SHIFT_CLI0 (Offset 0x0594) */ +#endif -#define BIT_TBTT_INT_SHIFT_DIR_CLI0 BIT(7) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0 0 -#define BIT_MASK_TBTT_INT_SHIFT_CLI0 0x7f -#define BIT_TBTT_INT_SHIFT_CLI0(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0) -#define BIT_GET_TBTT_INT_SHIFT_CLI0(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0) & BIT_MASK_TBTT_INT_SHIFT_CLI0) +/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ +#define BIT_RTS_NAV_TXOP BIT(1) +#define BIT_NOT_CROSS_TXOP BIT(0) -/* 2 REG_TBTT_INT_SHIFT_CLI1 (Offset 0x0595) */ +#endif -#define BIT_TBTT_INT_SHIFT_DIR_CLI1 BIT(7) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1 0 -#define BIT_MASK_TBTT_INT_SHIFT_CLI1 0x7f -#define BIT_TBTT_INT_SHIFT_CLI1(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1) -#define BIT_GET_TBTT_INT_SHIFT_CLI1(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1) & BIT_MASK_TBTT_INT_SHIFT_CLI1) +/* 2 REG_TBTT_INT_SHIFT_CLI0 (Offset 0x0594) */ +#define BIT_TBTT_INT_SHIFT_DIR_CLI0 BIT(7) -/* 2 REG_TBTT_INT_SHIFT_CLI2 (Offset 0x0596) */ +#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0 0 +#define BIT_MASK_TBTT_INT_SHIFT_CLI0 0x7f +#define BIT_TBTT_INT_SHIFT_CLI0(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0) +#define BITS_TBTT_INT_SHIFT_CLI0 \ + (BIT_MASK_TBTT_INT_SHIFT_CLI0 << BIT_SHIFT_TBTT_INT_SHIFT_CLI0) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI0)) +#define BIT_GET_TBTT_INT_SHIFT_CLI0(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0) & BIT_MASK_TBTT_INT_SHIFT_CLI0) +#define BIT_SET_TBTT_INT_SHIFT_CLI0(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) | BIT_TBTT_INT_SHIFT_CLI0(v)) -#define BIT_TBTT_INT_SHIFT_DIR_CLI2 BIT(7) +/* 2 REG_TBTT_INT_SHIFT_CLI1 (Offset 0x0595) */ -#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2 0 -#define BIT_MASK_TBTT_INT_SHIFT_CLI2 0x7f -#define BIT_TBTT_INT_SHIFT_CLI2(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2) -#define BIT_GET_TBTT_INT_SHIFT_CLI2(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2) & BIT_MASK_TBTT_INT_SHIFT_CLI2) +#define BIT_TBTT_INT_SHIFT_DIR_CLI1 BIT(7) +#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1 0 +#define BIT_MASK_TBTT_INT_SHIFT_CLI1 0x7f +#define BIT_TBTT_INT_SHIFT_CLI1(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1) +#define BITS_TBTT_INT_SHIFT_CLI1 \ + (BIT_MASK_TBTT_INT_SHIFT_CLI1 << BIT_SHIFT_TBTT_INT_SHIFT_CLI1) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI1)) +#define BIT_GET_TBTT_INT_SHIFT_CLI1(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1) & BIT_MASK_TBTT_INT_SHIFT_CLI1) +#define BIT_SET_TBTT_INT_SHIFT_CLI1(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI1(x) | BIT_TBTT_INT_SHIFT_CLI1(v)) -/* 2 REG_TBTT_INT_SHIFT_CLI3 (Offset 0x0597) */ +/* 2 REG_TBTT_INT_SHIFT_CLI2 (Offset 0x0596) */ -#define BIT_TBTT_INT_SHIFT_DIR_CLI3 BIT(7) +#define BIT_TBTT_INT_SHIFT_DIR_CLI2 BIT(7) -#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3 0 -#define BIT_MASK_TBTT_INT_SHIFT_CLI3 0x7f -#define BIT_TBTT_INT_SHIFT_CLI3(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3) -#define BIT_GET_TBTT_INT_SHIFT_CLI3(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3) & BIT_MASK_TBTT_INT_SHIFT_CLI3) +#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2 0 +#define BIT_MASK_TBTT_INT_SHIFT_CLI2 0x7f +#define BIT_TBTT_INT_SHIFT_CLI2(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2) +#define BITS_TBTT_INT_SHIFT_CLI2 \ + (BIT_MASK_TBTT_INT_SHIFT_CLI2 << BIT_SHIFT_TBTT_INT_SHIFT_CLI2) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI2)) +#define BIT_GET_TBTT_INT_SHIFT_CLI2(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2) & BIT_MASK_TBTT_INT_SHIFT_CLI2) +#define BIT_SET_TBTT_INT_SHIFT_CLI2(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI2(x) | BIT_TBTT_INT_SHIFT_CLI2(v)) +/* 2 REG_TBTT_INT_SHIFT_CLI3 (Offset 0x0597) */ -/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */ +#define BIT_TBTT_INT_SHIFT_DIR_CLI3 BIT(7) -#define BIT_EN_TBTT_RTY BIT(1) -#define BIT_TBTT_INT_SHIFT_ENABLE BIT(0) +#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3 0 +#define BIT_MASK_TBTT_INT_SHIFT_CLI3 0x7f +#define BIT_TBTT_INT_SHIFT_CLI3(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3) +#define BITS_TBTT_INT_SHIFT_CLI3 \ + (BIT_MASK_TBTT_INT_SHIFT_CLI3 << BIT_SHIFT_TBTT_INT_SHIFT_CLI3) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI3)) +#define BIT_GET_TBTT_INT_SHIFT_CLI3(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3) & BIT_MASK_TBTT_INT_SHIFT_CLI3) +#define BIT_SET_TBTT_INT_SHIFT_CLI3(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI3(x) | BIT_TBTT_INT_SHIFT_CLI3(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_ATIMWND2 (Offset 0x05A0) */ +/* 2 REG_RX_TBTT_SHIFT_V1 (Offset 0x0598) */ +#define BIT_RX_TBTT_SHIFT_RW_FLAG_V1 BIT(31) -#define BIT_SHIFT_ATIMWND2 0 -#define BIT_MASK_ATIMWND2 0xff -#define BIT_ATIMWND2(x) (((x) & BIT_MASK_ATIMWND2) << BIT_SHIFT_ATIMWND2) -#define BIT_GET_ATIMWND2(x) (((x) >> BIT_SHIFT_ATIMWND2) & BIT_MASK_ATIMWND2) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_ATIMWND3 (Offset 0x05A1) */ +/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */ +#define BIT_BCNERR_CNT_EN BIT(20) -#define BIT_SHIFT_ATIMWND3 0 -#define BIT_MASK_ATIMWND3 0xff -#define BIT_ATIMWND3(x) (((x) & BIT_MASK_ATIMWND3) << BIT_SHIFT_ATIMWND3) -#define BIT_GET_ATIMWND3(x) (((x) >> BIT_SHIFT_ATIMWND3) & BIT_MASK_ATIMWND3) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_ATIMWND4 (Offset 0x05A2) */ +/* 2 REG_RX_TBTT_SHIFT_V1 (Offset 0x0598) */ +#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1 16 +#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1 0xfff +#define BIT_RX_TBTT_SHIFT_OFFSET_V1(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1) \ + << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1) +#define BITS_RX_TBTT_SHIFT_OFFSET_V1 \ + (BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1 << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1) +#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1(x) \ + ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_V1)) +#define BIT_GET_RX_TBTT_SHIFT_OFFSET_V1(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1) & \ + BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1) +#define BIT_SET_RX_TBTT_SHIFT_OFFSET_V1(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1(x) | BIT_RX_TBTT_SHIFT_OFFSET_V1(v)) -#define BIT_SHIFT_ATIMWND4 0 -#define BIT_MASK_ATIMWND4 0xff -#define BIT_ATIMWND4(x) (((x) & BIT_MASK_ATIMWND4) << BIT_SHIFT_ATIMWND4) -#define BIT_GET_ATIMWND4(x) (((x) >> BIT_SHIFT_ATIMWND4) & BIT_MASK_ATIMWND4) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_ATIMWND5 (Offset 0x05A3) */ +/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */ +#define BIT_CHANGE_POW_BCN_AREA BIT(9) -#define BIT_SHIFT_ATIMWND5 0 -#define BIT_MASK_ATIMWND5 0xff -#define BIT_ATIMWND5(x) (((x) & BIT_MASK_ATIMWND5) << BIT_SHIFT_ATIMWND5) -#define BIT_GET_ATIMWND5(x) (((x) >> BIT_SHIFT_ATIMWND5) & BIT_MASK_ATIMWND5) +#define BIT_SHIFT_TXPAUSE1 8 +#define BIT_MASK_TXPAUSE1 0xff +#define BIT_TXPAUSE1(x) (((x) & BIT_MASK_TXPAUSE1) << BIT_SHIFT_TXPAUSE1) +#define BITS_TXPAUSE1 (BIT_MASK_TXPAUSE1 << BIT_SHIFT_TXPAUSE1) +#define BIT_CLEAR_TXPAUSE1(x) ((x) & (~BITS_TXPAUSE1)) +#define BIT_GET_TXPAUSE1(x) (((x) >> BIT_SHIFT_TXPAUSE1) & BIT_MASK_TXPAUSE1) +#define BIT_SET_TXPAUSE1(x, v) (BIT_CLEAR_TXPAUSE1(x) | BIT_TXPAUSE1(v)) +#endif -/* 2 REG_ATIMWND6 (Offset 0x05A4) */ +#if (HALMAC_8822C_SUPPORT) +/* 2 REG_RX_TBTT_SHIFT_V1 (Offset 0x0598) */ -#define BIT_SHIFT_ATIMWND6 0 -#define BIT_MASK_ATIMWND6 0xff -#define BIT_ATIMWND6(x) (((x) & BIT_MASK_ATIMWND6) << BIT_SHIFT_ATIMWND6) -#define BIT_GET_ATIMWND6(x) (((x) >> BIT_SHIFT_ATIMWND6) & BIT_MASK_ATIMWND6) +#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1 8 +#define BIT_MASK_RX_TBTT_SHIFT_SEL_V1 0x7 +#define BIT_RX_TBTT_SHIFT_SEL_V1(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_V1) \ + << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1) +#define BITS_RX_TBTT_SHIFT_SEL_V1 \ + (BIT_MASK_RX_TBTT_SHIFT_SEL_V1 << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1) +#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1(x) ((x) & (~BITS_RX_TBTT_SHIFT_SEL_V1)) +#define BIT_GET_RX_TBTT_SHIFT_SEL_V1(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1) & \ + BIT_MASK_RX_TBTT_SHIFT_SEL_V1) +#define BIT_SET_RX_TBTT_SHIFT_SEL_V1(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1(x) | BIT_RX_TBTT_SHIFT_SEL_V1(v)) +#endif -/* 2 REG_ATIMWND7 (Offset 0x05A5) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) +/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */ -#define BIT_SHIFT_ATIMWND7 0 -#define BIT_MASK_ATIMWND7 0xff -#define BIT_ATIMWND7(x) (((x) & BIT_MASK_ATIMWND7) << BIT_SHIFT_ATIMWND7) -#define BIT_GET_ATIMWND7(x) (((x) >> BIT_SHIFT_ATIMWND7) & BIT_MASK_ATIMWND7) +#define BIT_EN_TBTT_RTY BIT(1) +#define BIT_TBTT_INT_SHIFT_ENABLE BIT(0) +#define BIT_SHIFT_BCN_ELY_ADJ 0 +#define BIT_MASK_BCN_ELY_ADJ 0xffff +#define BIT_BCN_ELY_ADJ(x) \ + (((x) & BIT_MASK_BCN_ELY_ADJ) << BIT_SHIFT_BCN_ELY_ADJ) +#define BITS_BCN_ELY_ADJ (BIT_MASK_BCN_ELY_ADJ << BIT_SHIFT_BCN_ELY_ADJ) +#define BIT_CLEAR_BCN_ELY_ADJ(x) ((x) & (~BITS_BCN_ELY_ADJ)) +#define BIT_GET_BCN_ELY_ADJ(x) \ + (((x) >> BIT_SHIFT_BCN_ELY_ADJ) & BIT_MASK_BCN_ELY_ADJ) +#define BIT_SET_BCN_ELY_ADJ(x, v) \ + (BIT_CLEAR_BCN_ELY_ADJ(x) | BIT_BCN_ELY_ADJ(v)) -/* 2 REG_ATIMUGT (Offset 0x05A6) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_ATIM_URGENT 0 -#define BIT_MASK_ATIM_URGENT 0xff -#define BIT_ATIM_URGENT(x) (((x) & BIT_MASK_ATIM_URGENT) << BIT_SHIFT_ATIM_URGENT) -#define BIT_GET_ATIM_URGENT(x) (((x) >> BIT_SHIFT_ATIM_URGENT) & BIT_MASK_ATIM_URGENT) +/* 2 REG_ATIMWND2 (Offset 0x05A0) */ +#define BIT_SHIFT_ATIMWND2 0 +#define BIT_MASK_ATIMWND2 0xff +#define BIT_ATIMWND2(x) (((x) & BIT_MASK_ATIMWND2) << BIT_SHIFT_ATIMWND2) +#define BITS_ATIMWND2 (BIT_MASK_ATIMWND2 << BIT_SHIFT_ATIMWND2) +#define BIT_CLEAR_ATIMWND2(x) ((x) & (~BITS_ATIMWND2)) +#define BIT_GET_ATIMWND2(x) (((x) >> BIT_SHIFT_ATIMWND2) & BIT_MASK_ATIMWND2) +#define BIT_SET_ATIMWND2(x, v) (BIT_CLEAR_ATIMWND2(x) | BIT_ATIMWND2(v)) -/* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */ +#endif -#define BIT_HIQ_NO_LMT_EN_VAP7 BIT(7) -#define BIT_HIQ_NO_LMT_EN_VAP6 BIT(6) -#define BIT_HIQ_NO_LMT_EN_VAP5 BIT(5) -#define BIT_HIQ_NO_LMT_EN_VAP4 BIT(4) -#define BIT_HIQ_NO_LMT_EN_VAP3 BIT(3) -#define BIT_HIQ_NO_LMT_EN_VAP2 BIT(2) -#define BIT_HIQ_NO_LMT_EN_VAP1 BIT(1) -#define BIT_HIQ_NO_LMT_EN_ROOT BIT(0) +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_DTIM_COUNTER_ROOT (Offset 0x05A8) */ +/* 2 REG_ATIMWND_GROUP1 (Offset 0x05A0) */ +#define BIT_SHIFT_ATIMWND_GROUP1 0 +#define BIT_MASK_ATIMWND_GROUP1 0xff +#define BIT_ATIMWND_GROUP1(x) \ + (((x) & BIT_MASK_ATIMWND_GROUP1) << BIT_SHIFT_ATIMWND_GROUP1) +#define BITS_ATIMWND_GROUP1 \ + (BIT_MASK_ATIMWND_GROUP1 << BIT_SHIFT_ATIMWND_GROUP1) +#define BIT_CLEAR_ATIMWND_GROUP1(x) ((x) & (~BITS_ATIMWND_GROUP1)) +#define BIT_GET_ATIMWND_GROUP1(x) \ + (((x) >> BIT_SHIFT_ATIMWND_GROUP1) & BIT_MASK_ATIMWND_GROUP1) +#define BIT_SET_ATIMWND_GROUP1(x, v) \ + (BIT_CLEAR_ATIMWND_GROUP1(x) | BIT_ATIMWND_GROUP1(v)) -#define BIT_SHIFT_DTIM_COUNT_ROOT 0 -#define BIT_MASK_DTIM_COUNT_ROOT 0xff -#define BIT_DTIM_COUNT_ROOT(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT) << BIT_SHIFT_DTIM_COUNT_ROOT) -#define BIT_GET_DTIM_COUNT_ROOT(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT) & BIT_MASK_DTIM_COUNT_ROOT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DTIM_COUNTER_VAP1 (Offset 0x05A9) */ +/* 2 REG_ATIMWND3 (Offset 0x05A1) */ +#define BIT_SHIFT_ATIMWND3 0 +#define BIT_MASK_ATIMWND3 0xff +#define BIT_ATIMWND3(x) (((x) & BIT_MASK_ATIMWND3) << BIT_SHIFT_ATIMWND3) +#define BITS_ATIMWND3 (BIT_MASK_ATIMWND3 << BIT_SHIFT_ATIMWND3) +#define BIT_CLEAR_ATIMWND3(x) ((x) & (~BITS_ATIMWND3)) +#define BIT_GET_ATIMWND3(x) (((x) >> BIT_SHIFT_ATIMWND3) & BIT_MASK_ATIMWND3) +#define BIT_SET_ATIMWND3(x, v) (BIT_CLEAR_ATIMWND3(x) | BIT_ATIMWND3(v)) -#define BIT_SHIFT_DTIM_COUNT_VAP1 0 -#define BIT_MASK_DTIM_COUNT_VAP1 0xff -#define BIT_DTIM_COUNT_VAP1(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1) << BIT_SHIFT_DTIM_COUNT_VAP1) -#define BIT_GET_DTIM_COUNT_VAP1(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1) & BIT_MASK_DTIM_COUNT_VAP1) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_DTIM_COUNTER_VAP2 (Offset 0x05AA) */ +/* 2 REG_ATIMWND_GROUP2 (Offset 0x05A1) */ +#define BIT_SHIFT_ATIMWND_GROUP2 0 +#define BIT_MASK_ATIMWND_GROUP2 0xff +#define BIT_ATIMWND_GROUP2(x) \ + (((x) & BIT_MASK_ATIMWND_GROUP2) << BIT_SHIFT_ATIMWND_GROUP2) +#define BITS_ATIMWND_GROUP2 \ + (BIT_MASK_ATIMWND_GROUP2 << BIT_SHIFT_ATIMWND_GROUP2) +#define BIT_CLEAR_ATIMWND_GROUP2(x) ((x) & (~BITS_ATIMWND_GROUP2)) +#define BIT_GET_ATIMWND_GROUP2(x) \ + (((x) >> BIT_SHIFT_ATIMWND_GROUP2) & BIT_MASK_ATIMWND_GROUP2) +#define BIT_SET_ATIMWND_GROUP2(x, v) \ + (BIT_CLEAR_ATIMWND_GROUP2(x) | BIT_ATIMWND_GROUP2(v)) -#define BIT_SHIFT_DTIM_COUNT_VAP2 0 -#define BIT_MASK_DTIM_COUNT_VAP2 0xff -#define BIT_DTIM_COUNT_VAP2(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2) << BIT_SHIFT_DTIM_COUNT_VAP2) -#define BIT_GET_DTIM_COUNT_VAP2(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2) & BIT_MASK_DTIM_COUNT_VAP2) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DTIM_COUNTER_VAP3 (Offset 0x05AB) */ +/* 2 REG_ATIMWND4 (Offset 0x05A2) */ +#define BIT_SHIFT_ATIMWND4 0 +#define BIT_MASK_ATIMWND4 0xff +#define BIT_ATIMWND4(x) (((x) & BIT_MASK_ATIMWND4) << BIT_SHIFT_ATIMWND4) +#define BITS_ATIMWND4 (BIT_MASK_ATIMWND4 << BIT_SHIFT_ATIMWND4) +#define BIT_CLEAR_ATIMWND4(x) ((x) & (~BITS_ATIMWND4)) +#define BIT_GET_ATIMWND4(x) (((x) >> BIT_SHIFT_ATIMWND4) & BIT_MASK_ATIMWND4) +#define BIT_SET_ATIMWND4(x, v) (BIT_CLEAR_ATIMWND4(x) | BIT_ATIMWND4(v)) -#define BIT_SHIFT_DTIM_COUNT_VAP3 0 -#define BIT_MASK_DTIM_COUNT_VAP3 0xff -#define BIT_DTIM_COUNT_VAP3(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3) << BIT_SHIFT_DTIM_COUNT_VAP3) -#define BIT_GET_DTIM_COUNT_VAP3(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3) & BIT_MASK_DTIM_COUNT_VAP3) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_DTIM_COUNTER_VAP4 (Offset 0x05AC) */ +/* 2 REG_ATIMWND_GROUP3 (Offset 0x05A2) */ +#define BIT_SHIFT_ATIMWND_GROUP3 0 +#define BIT_MASK_ATIMWND_GROUP3 0xff +#define BIT_ATIMWND_GROUP3(x) \ + (((x) & BIT_MASK_ATIMWND_GROUP3) << BIT_SHIFT_ATIMWND_GROUP3) +#define BITS_ATIMWND_GROUP3 \ + (BIT_MASK_ATIMWND_GROUP3 << BIT_SHIFT_ATIMWND_GROUP3) +#define BIT_CLEAR_ATIMWND_GROUP3(x) ((x) & (~BITS_ATIMWND_GROUP3)) +#define BIT_GET_ATIMWND_GROUP3(x) \ + (((x) >> BIT_SHIFT_ATIMWND_GROUP3) & BIT_MASK_ATIMWND_GROUP3) +#define BIT_SET_ATIMWND_GROUP3(x, v) \ + (BIT_CLEAR_ATIMWND_GROUP3(x) | BIT_ATIMWND_GROUP3(v)) -#define BIT_SHIFT_DTIM_COUNT_VAP4 0 -#define BIT_MASK_DTIM_COUNT_VAP4 0xff -#define BIT_DTIM_COUNT_VAP4(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4) << BIT_SHIFT_DTIM_COUNT_VAP4) -#define BIT_GET_DTIM_COUNT_VAP4(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4) & BIT_MASK_DTIM_COUNT_VAP4) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DTIM_COUNTER_VAP5 (Offset 0x05AD) */ +/* 2 REG_ATIMWND5 (Offset 0x05A3) */ +#define BIT_SHIFT_ATIMWND5 0 +#define BIT_MASK_ATIMWND5 0xff +#define BIT_ATIMWND5(x) (((x) & BIT_MASK_ATIMWND5) << BIT_SHIFT_ATIMWND5) +#define BITS_ATIMWND5 (BIT_MASK_ATIMWND5 << BIT_SHIFT_ATIMWND5) +#define BIT_CLEAR_ATIMWND5(x) ((x) & (~BITS_ATIMWND5)) +#define BIT_GET_ATIMWND5(x) (((x) >> BIT_SHIFT_ATIMWND5) & BIT_MASK_ATIMWND5) +#define BIT_SET_ATIMWND5(x, v) (BIT_CLEAR_ATIMWND5(x) | BIT_ATIMWND5(v)) -#define BIT_SHIFT_DTIM_COUNT_VAP5 0 -#define BIT_MASK_DTIM_COUNT_VAP5 0xff -#define BIT_DTIM_COUNT_VAP5(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5) << BIT_SHIFT_DTIM_COUNT_VAP5) -#define BIT_GET_DTIM_COUNT_VAP5(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5) & BIT_MASK_DTIM_COUNT_VAP5) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_DTIM_COUNTER_VAP6 (Offset 0x05AE) */ +/* 2 REG_ATIMWND_GROUP4 (Offset 0x05A3) */ +#define BIT_SHIFT_ATIMWND_GROUP4 0 +#define BIT_MASK_ATIMWND_GROUP4 0xff +#define BIT_ATIMWND_GROUP4(x) \ + (((x) & BIT_MASK_ATIMWND_GROUP4) << BIT_SHIFT_ATIMWND_GROUP4) +#define BITS_ATIMWND_GROUP4 \ + (BIT_MASK_ATIMWND_GROUP4 << BIT_SHIFT_ATIMWND_GROUP4) +#define BIT_CLEAR_ATIMWND_GROUP4(x) ((x) & (~BITS_ATIMWND_GROUP4)) +#define BIT_GET_ATIMWND_GROUP4(x) \ + (((x) >> BIT_SHIFT_ATIMWND_GROUP4) & BIT_MASK_ATIMWND_GROUP4) +#define BIT_SET_ATIMWND_GROUP4(x, v) \ + (BIT_CLEAR_ATIMWND_GROUP4(x) | BIT_ATIMWND_GROUP4(v)) -#define BIT_SHIFT_DTIM_COUNT_VAP6 0 -#define BIT_MASK_DTIM_COUNT_VAP6 0xff -#define BIT_DTIM_COUNT_VAP6(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6) << BIT_SHIFT_DTIM_COUNT_VAP6) -#define BIT_GET_DTIM_COUNT_VAP6(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6) & BIT_MASK_DTIM_COUNT_VAP6) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DTIM_COUNTER_VAP7 (Offset 0x05AF) */ +/* 2 REG_ATIMWND6 (Offset 0x05A4) */ +#define BIT_SHIFT_ATIMWND6 0 +#define BIT_MASK_ATIMWND6 0xff +#define BIT_ATIMWND6(x) (((x) & BIT_MASK_ATIMWND6) << BIT_SHIFT_ATIMWND6) +#define BITS_ATIMWND6 (BIT_MASK_ATIMWND6 << BIT_SHIFT_ATIMWND6) +#define BIT_CLEAR_ATIMWND6(x) ((x) & (~BITS_ATIMWND6)) +#define BIT_GET_ATIMWND6(x) (((x) >> BIT_SHIFT_ATIMWND6) & BIT_MASK_ATIMWND6) +#define BIT_SET_ATIMWND6(x, v) (BIT_CLEAR_ATIMWND6(x) | BIT_ATIMWND6(v)) -#define BIT_SHIFT_DTIM_COUNT_VAP7 0 -#define BIT_MASK_DTIM_COUNT_VAP7 0xff -#define BIT_DTIM_COUNT_VAP7(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7) << BIT_SHIFT_DTIM_COUNT_VAP7) -#define BIT_GET_DTIM_COUNT_VAP7(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7) & BIT_MASK_DTIM_COUNT_VAP7) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_DIS_ATIM (Offset 0x05B0) */ +/* 2 REG_DTIM_COUNT_GROUP1 (Offset 0x05A4) */ -#define BIT_DIS_ATIM_VAP7 BIT(7) -#define BIT_DIS_ATIM_VAP6 BIT(6) -#define BIT_DIS_ATIM_VAP5 BIT(5) -#define BIT_DIS_ATIM_VAP4 BIT(4) -#define BIT_DIS_ATIM_VAP3 BIT(3) -#define BIT_DIS_ATIM_VAP2 BIT(2) -#define BIT_DIS_ATIM_VAP1 BIT(1) -#define BIT_DIS_ATIM_ROOT BIT(0) +#define BIT_SHIFT_DTIM_COUNT_GROUP1 0 +#define BIT_MASK_DTIM_COUNT_GROUP1 0xff +#define BIT_DTIM_COUNT_GROUP1(x) \ + (((x) & BIT_MASK_DTIM_COUNT_GROUP1) << BIT_SHIFT_DTIM_COUNT_GROUP1) +#define BITS_DTIM_COUNT_GROUP1 \ + (BIT_MASK_DTIM_COUNT_GROUP1 << BIT_SHIFT_DTIM_COUNT_GROUP1) +#define BIT_CLEAR_DTIM_COUNT_GROUP1(x) ((x) & (~BITS_DTIM_COUNT_GROUP1)) +#define BIT_GET_DTIM_COUNT_GROUP1(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP1) & BIT_MASK_DTIM_COUNT_GROUP1) +#define BIT_SET_DTIM_COUNT_GROUP1(x, v) \ + (BIT_CLEAR_DTIM_COUNT_GROUP1(x) | BIT_DTIM_COUNT_GROUP1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ATIMWND7 (Offset 0x05A5) */ +#define BIT_SHIFT_ATIMWND7 0 +#define BIT_MASK_ATIMWND7 0xff +#define BIT_ATIMWND7(x) (((x) & BIT_MASK_ATIMWND7) << BIT_SHIFT_ATIMWND7) +#define BITS_ATIMWND7 (BIT_MASK_ATIMWND7 << BIT_SHIFT_ATIMWND7) +#define BIT_CLEAR_ATIMWND7(x) ((x) & (~BITS_ATIMWND7)) +#define BIT_GET_ATIMWND7(x) (((x) >> BIT_SHIFT_ATIMWND7) & BIT_MASK_ATIMWND7) +#define BIT_SET_ATIMWND7(x, v) (BIT_CLEAR_ATIMWND7(x) | BIT_ATIMWND7(v)) -/* 2 REG_EARLY_128US (Offset 0x05B1) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_TSFT_SEL_TIMER1 3 -#define BIT_MASK_TSFT_SEL_TIMER1 0x7 -#define BIT_TSFT_SEL_TIMER1(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1) -#define BIT_GET_TSFT_SEL_TIMER1(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1) +/* 2 REG_DTIM_COUNT_GROUP2 (Offset 0x05A5) */ +#define BIT_SHIFT_DTIM_COUNT_GROUP2 0 +#define BIT_MASK_DTIM_COUNT_GROUP2 0xff +#define BIT_DTIM_COUNT_GROUP2(x) \ + (((x) & BIT_MASK_DTIM_COUNT_GROUP2) << BIT_SHIFT_DTIM_COUNT_GROUP2) +#define BITS_DTIM_COUNT_GROUP2 \ + (BIT_MASK_DTIM_COUNT_GROUP2 << BIT_SHIFT_DTIM_COUNT_GROUP2) +#define BIT_CLEAR_DTIM_COUNT_GROUP2(x) ((x) & (~BITS_DTIM_COUNT_GROUP2)) +#define BIT_GET_DTIM_COUNT_GROUP2(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP2) & BIT_MASK_DTIM_COUNT_GROUP2) +#define BIT_SET_DTIM_COUNT_GROUP2(x, v) \ + (BIT_CLEAR_DTIM_COUNT_GROUP2(x) | BIT_DTIM_COUNT_GROUP2(v)) -#define BIT_SHIFT_EARLY_128US 0 -#define BIT_MASK_EARLY_128US 0x7 -#define BIT_EARLY_128US(x) (((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US) -#define BIT_GET_EARLY_128US(x) (((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ +/* 2 REG_ATIMUGT (Offset 0x05A6) */ -#define BIT_P2P1_CTW_ALLSTASLEEP BIT(7) -#define BIT_P2P1_OFF_DISTX_EN BIT(6) -#define BIT_P2P1_PWR_MGT_EN BIT(5) -#define BIT_P2P1_NOA1_EN BIT(2) -#define BIT_P2P1_NOA0_EN BIT(1) +#define BIT_SHIFT_ATIM_URGENT 0 +#define BIT_MASK_ATIM_URGENT 0xff +#define BIT_ATIM_URGENT(x) \ + (((x) & BIT_MASK_ATIM_URGENT) << BIT_SHIFT_ATIM_URGENT) +#define BITS_ATIM_URGENT (BIT_MASK_ATIM_URGENT << BIT_SHIFT_ATIM_URGENT) +#define BIT_CLEAR_ATIM_URGENT(x) ((x) & (~BITS_ATIM_URGENT)) +#define BIT_GET_ATIM_URGENT(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT) & BIT_MASK_ATIM_URGENT) +#define BIT_SET_ATIM_URGENT(x, v) \ + (BIT_CLEAR_ATIM_URGENT(x) | BIT_ATIM_URGENT(v)) -/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ +#endif -#define BIT_P2P2_CTW_ALLSTASLEEP BIT(7) -#define BIT_P2P2_OFF_DISTX_EN BIT(6) -#define BIT_P2P2_PWR_MGT_EN BIT(5) -#define BIT_P2P2_NOA1_EN BIT(2) -#define BIT_P2P2_NOA0_EN BIT(1) +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_TIMER0_SRC_SEL (Offset 0x05B4) */ +/* 2 REG_DTIM_COUNT_GROUP3 (Offset 0x05A6) */ +#define BIT_SHIFT_DTIM_COUNT_GROUP3 0 +#define BIT_MASK_DTIM_COUNT_GROUP3 0xff +#define BIT_DTIM_COUNT_GROUP3(x) \ + (((x) & BIT_MASK_DTIM_COUNT_GROUP3) << BIT_SHIFT_DTIM_COUNT_GROUP3) +#define BITS_DTIM_COUNT_GROUP3 \ + (BIT_MASK_DTIM_COUNT_GROUP3 << BIT_SHIFT_DTIM_COUNT_GROUP3) +#define BIT_CLEAR_DTIM_COUNT_GROUP3(x) ((x) & (~BITS_DTIM_COUNT_GROUP3)) +#define BIT_GET_DTIM_COUNT_GROUP3(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP3) & BIT_MASK_DTIM_COUNT_GROUP3) +#define BIT_SET_DTIM_COUNT_GROUP3(x, v) \ + (BIT_CLEAR_DTIM_COUNT_GROUP3(x) | BIT_DTIM_COUNT_GROUP3(v)) -#define BIT_SHIFT_SYNC_CLI_SEL 4 -#define BIT_MASK_SYNC_CLI_SEL 0x7 -#define BIT_SYNC_CLI_SEL(x) (((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL) -#define BIT_GET_SYNC_CLI_SEL(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TSFT_SEL_TIMER0 0 -#define BIT_MASK_TSFT_SEL_TIMER0 0x7 -#define BIT_TSFT_SEL_TIMER0(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0) -#define BIT_GET_TSFT_SEL_TIMER0(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0) +/* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */ +#define BIT_HIQ_NO_LMT_EN_VAP7 BIT(7) +#define BIT_HIQ_NO_LMT_EN_VAP6 BIT(6) +#define BIT_HIQ_NO_LMT_EN_VAP5 BIT(5) +#define BIT_HIQ_NO_LMT_EN_VAP4 BIT(4) +#define BIT_HIQ_NO_LMT_EN_VAP3 BIT(3) +#define BIT_HIQ_NO_LMT_EN_VAP2 BIT(2) +#define BIT_HIQ_NO_LMT_EN_VAP1 BIT(1) -/* 2 REG_NOA_UNIT_SEL (Offset 0x05B5) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NOA_UNIT2_SEL 8 -#define BIT_MASK_NOA_UNIT2_SEL 0x7 -#define BIT_NOA_UNIT2_SEL(x) (((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL) -#define BIT_GET_NOA_UNIT2_SEL(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL) +/* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */ +#define BIT_HIQ_NO_LMT_EN_ROOT BIT(0) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_DTIM_COUNT_GROUP4 (Offset 0x05A7) */ + +#define BIT_SHIFT_DTIM_COUNT_GROUP4 0 +#define BIT_MASK_DTIM_COUNT_GROUP4 0xff +#define BIT_DTIM_COUNT_GROUP4(x) \ + (((x) & BIT_MASK_DTIM_COUNT_GROUP4) << BIT_SHIFT_DTIM_COUNT_GROUP4) +#define BITS_DTIM_COUNT_GROUP4 \ + (BIT_MASK_DTIM_COUNT_GROUP4 << BIT_SHIFT_DTIM_COUNT_GROUP4) +#define BIT_CLEAR_DTIM_COUNT_GROUP4(x) ((x) & (~BITS_DTIM_COUNT_GROUP4)) +#define BIT_GET_DTIM_COUNT_GROUP4(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP4) & BIT_MASK_DTIM_COUNT_GROUP4) +#define BIT_SET_DTIM_COUNT_GROUP4(x, v) \ + (BIT_CLEAR_DTIM_COUNT_GROUP4(x) | BIT_DTIM_COUNT_GROUP4(v)) + +/* 2 REG_HIQ_NO_LMT_EN_V2 (Offset 0x05A8) */ + +#define BIT_SHIFT_ATIM_CFG_SEL 24 +#define BIT_MASK_ATIM_CFG_SEL 0x3 +#define BIT_ATIM_CFG_SEL(x) \ + (((x) & BIT_MASK_ATIM_CFG_SEL) << BIT_SHIFT_ATIM_CFG_SEL) +#define BITS_ATIM_CFG_SEL (BIT_MASK_ATIM_CFG_SEL << BIT_SHIFT_ATIM_CFG_SEL) +#define BIT_CLEAR_ATIM_CFG_SEL(x) ((x) & (~BITS_ATIM_CFG_SEL)) +#define BIT_GET_ATIM_CFG_SEL(x) \ + (((x) >> BIT_SHIFT_ATIM_CFG_SEL) & BIT_MASK_ATIM_CFG_SEL) +#define BIT_SET_ATIM_CFG_SEL(x, v) \ + (BIT_CLEAR_ATIM_CFG_SEL(x) | BIT_ATIM_CFG_SEL(v)) + +#define BIT_SHIFT_DIS_ATIM 16 +#define BIT_MASK_DIS_ATIM 0xffff +#define BIT_DIS_ATIM(x) (((x) & BIT_MASK_DIS_ATIM) << BIT_SHIFT_DIS_ATIM) +#define BITS_DIS_ATIM (BIT_MASK_DIS_ATIM << BIT_SHIFT_DIS_ATIM) +#define BIT_CLEAR_DIS_ATIM(x) ((x) & (~BITS_DIS_ATIM)) +#define BIT_GET_DIS_ATIM(x) (((x) >> BIT_SHIFT_DIS_ATIM) & BIT_MASK_DIS_ATIM) +#define BIT_SET_DIS_ATIM(x, v) (BIT_CLEAR_DIS_ATIM(x) | BIT_DIS_ATIM(v)) + +#define BIT_SHIFT_ATIM_URGENT_V1 16 +#define BIT_MASK_ATIM_URGENT_V1 0xff +#define BIT_ATIM_URGENT_V1(x) \ + (((x) & BIT_MASK_ATIM_URGENT_V1) << BIT_SHIFT_ATIM_URGENT_V1) +#define BITS_ATIM_URGENT_V1 \ + (BIT_MASK_ATIM_URGENT_V1 << BIT_SHIFT_ATIM_URGENT_V1) +#define BIT_CLEAR_ATIM_URGENT_V1(x) ((x) & (~BITS_ATIM_URGENT_V1)) +#define BIT_GET_ATIM_URGENT_V1(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT_V1) & BIT_MASK_ATIM_URGENT_V1) +#define BIT_SET_ATIM_URGENT_V1(x, v) \ + (BIT_CLEAR_ATIM_URGENT_V1(x) | BIT_ATIM_URGENT_V1(v)) + +#define BIT_SHIFT_BCNERR_PORT_SEL_V1 16 +#define BIT_MASK_BCNERR_PORT_SEL_V1 0xf +#define BIT_BCNERR_PORT_SEL_V1(x) \ + (((x) & BIT_MASK_BCNERR_PORT_SEL_V1) << BIT_SHIFT_BCNERR_PORT_SEL_V1) +#define BITS_BCNERR_PORT_SEL_V1 \ + (BIT_MASK_BCNERR_PORT_SEL_V1 << BIT_SHIFT_BCNERR_PORT_SEL_V1) +#define BIT_CLEAR_BCNERR_PORT_SEL_V1(x) ((x) & (~BITS_BCNERR_PORT_SEL_V1)) +#define BIT_GET_BCNERR_PORT_SEL_V1(x) \ + (((x) >> BIT_SHIFT_BCNERR_PORT_SEL_V1) & BIT_MASK_BCNERR_PORT_SEL_V1) +#define BIT_SET_BCNERR_PORT_SEL_V1(x, v) \ + (BIT_CLEAR_BCNERR_PORT_SEL_V1(x) | BIT_BCNERR_PORT_SEL_V1(v)) + +#define BIT_DIS_NDPA_NAV_CHK BIT(8) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NOA_UNIT1_SEL 4 -#define BIT_MASK_NOA_UNIT1_SEL 0x7 -#define BIT_NOA_UNIT1_SEL(x) (((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL) -#define BIT_GET_NOA_UNIT1_SEL(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL) +/* 2 REG_DTIM_COUNTER_ROOT (Offset 0x05A8) */ +#define BIT_SHIFT_DTIM_COUNT_ROOT 0 +#define BIT_MASK_DTIM_COUNT_ROOT 0xff +#define BIT_DTIM_COUNT_ROOT(x) \ + (((x) & BIT_MASK_DTIM_COUNT_ROOT) << BIT_SHIFT_DTIM_COUNT_ROOT) +#define BITS_DTIM_COUNT_ROOT \ + (BIT_MASK_DTIM_COUNT_ROOT << BIT_SHIFT_DTIM_COUNT_ROOT) +#define BIT_CLEAR_DTIM_COUNT_ROOT(x) ((x) & (~BITS_DTIM_COUNT_ROOT)) +#define BIT_GET_DTIM_COUNT_ROOT(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT) & BIT_MASK_DTIM_COUNT_ROOT) +#define BIT_SET_DTIM_COUNT_ROOT(x, v) \ + (BIT_CLEAR_DTIM_COUNT_ROOT(x) | BIT_DTIM_COUNT_ROOT(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HIQ_NO_LMT_EN_V2 (Offset 0x05A8) */ + +#define BIT_SHIFT_MBID_BCNQ_EN 0 +#define BIT_MASK_MBID_BCNQ_EN 0xffff +#define BIT_MBID_BCNQ_EN(x) \ + (((x) & BIT_MASK_MBID_BCNQ_EN) << BIT_SHIFT_MBID_BCNQ_EN) +#define BITS_MBID_BCNQ_EN (BIT_MASK_MBID_BCNQ_EN << BIT_SHIFT_MBID_BCNQ_EN) +#define BIT_CLEAR_MBID_BCNQ_EN(x) ((x) & (~BITS_MBID_BCNQ_EN)) +#define BIT_GET_MBID_BCNQ_EN(x) \ + (((x) >> BIT_SHIFT_MBID_BCNQ_EN) & BIT_MASK_MBID_BCNQ_EN) +#define BIT_SET_MBID_BCNQ_EN(x, v) \ + (BIT_CLEAR_MBID_BCNQ_EN(x) | BIT_MBID_BCNQ_EN(v)) + +#define BIT_SHIFT_MHDR_NAV_OFFSET 0 +#define BIT_MASK_MHDR_NAV_OFFSET 0xff +#define BIT_MHDR_NAV_OFFSET(x) \ + (((x) & BIT_MASK_MHDR_NAV_OFFSET) << BIT_SHIFT_MHDR_NAV_OFFSET) +#define BITS_MHDR_NAV_OFFSET \ + (BIT_MASK_MHDR_NAV_OFFSET << BIT_SHIFT_MHDR_NAV_OFFSET) +#define BIT_CLEAR_MHDR_NAV_OFFSET(x) ((x) & (~BITS_MHDR_NAV_OFFSET)) +#define BIT_GET_MHDR_NAV_OFFSET(x) \ + (((x) >> BIT_SHIFT_MHDR_NAV_OFFSET) & BIT_MASK_MHDR_NAV_OFFSET) +#define BIT_SET_MHDR_NAV_OFFSET(x, v) \ + (BIT_CLEAR_MHDR_NAV_OFFSET(x) | BIT_MHDR_NAV_OFFSET(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NOA_UNIT0_SEL 0 -#define BIT_MASK_NOA_UNIT0_SEL 0x7 -#define BIT_NOA_UNIT0_SEL(x) (((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL) -#define BIT_GET_NOA_UNIT0_SEL(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL) +/* 2 REG_DTIM_COUNTER_VAP1 (Offset 0x05A9) */ +#define BIT_SHIFT_DTIM_COUNT_VAP1 0 +#define BIT_MASK_DTIM_COUNT_VAP1 0xff +#define BIT_DTIM_COUNT_VAP1(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP1) << BIT_SHIFT_DTIM_COUNT_VAP1) +#define BITS_DTIM_COUNT_VAP1 \ + (BIT_MASK_DTIM_COUNT_VAP1 << BIT_SHIFT_DTIM_COUNT_VAP1) +#define BIT_CLEAR_DTIM_COUNT_VAP1(x) ((x) & (~BITS_DTIM_COUNT_VAP1)) +#define BIT_GET_DTIM_COUNT_VAP1(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1) & BIT_MASK_DTIM_COUNT_VAP1) +#define BIT_SET_DTIM_COUNT_VAP1(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP1(x) | BIT_DTIM_COUNT_VAP1(v)) -/* 2 REG_P2POFF_DIS_TXTIME (Offset 0x05B7) */ +/* 2 REG_DTIM_COUNTER_VAP2 (Offset 0x05AA) */ +#define BIT_SHIFT_DTIM_COUNT_VAP2 0 +#define BIT_MASK_DTIM_COUNT_VAP2 0xff +#define BIT_DTIM_COUNT_VAP2(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP2) << BIT_SHIFT_DTIM_COUNT_VAP2) +#define BITS_DTIM_COUNT_VAP2 \ + (BIT_MASK_DTIM_COUNT_VAP2 << BIT_SHIFT_DTIM_COUNT_VAP2) +#define BIT_CLEAR_DTIM_COUNT_VAP2(x) ((x) & (~BITS_DTIM_COUNT_VAP2)) +#define BIT_GET_DTIM_COUNT_VAP2(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2) & BIT_MASK_DTIM_COUNT_VAP2) +#define BIT_SET_DTIM_COUNT_VAP2(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP2(x) | BIT_DTIM_COUNT_VAP2(v)) -#define BIT_SHIFT_P2POFF_DIS_TXTIME 0 -#define BIT_MASK_P2POFF_DIS_TXTIME 0xff -#define BIT_P2POFF_DIS_TXTIME(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME) -#define BIT_GET_P2POFF_DIS_TXTIME(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME) +/* 2 REG_DTIM_COUNTER_VAP3 (Offset 0x05AB) */ +#define BIT_SHIFT_DTIM_COUNT_VAP3 0 +#define BIT_MASK_DTIM_COUNT_VAP3 0xff +#define BIT_DTIM_COUNT_VAP3(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP3) << BIT_SHIFT_DTIM_COUNT_VAP3) +#define BITS_DTIM_COUNT_VAP3 \ + (BIT_MASK_DTIM_COUNT_VAP3 << BIT_SHIFT_DTIM_COUNT_VAP3) +#define BIT_CLEAR_DTIM_COUNT_VAP3(x) ((x) & (~BITS_DTIM_COUNT_VAP3)) +#define BIT_GET_DTIM_COUNT_VAP3(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3) & BIT_MASK_DTIM_COUNT_VAP3) +#define BIT_SET_DTIM_COUNT_VAP3(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP3(x) | BIT_DTIM_COUNT_VAP3(v)) -/* 2 REG_MBSSID_BCN_SPACE2 (Offset 0x05B8) */ +/* 2 REG_DTIM_COUNTER_VAP4 (Offset 0x05AC) */ +#define BIT_SHIFT_DTIM_COUNT_VAP4 0 +#define BIT_MASK_DTIM_COUNT_VAP4 0xff +#define BIT_DTIM_COUNT_VAP4(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP4) << BIT_SHIFT_DTIM_COUNT_VAP4) +#define BITS_DTIM_COUNT_VAP4 \ + (BIT_MASK_DTIM_COUNT_VAP4 << BIT_SHIFT_DTIM_COUNT_VAP4) +#define BIT_CLEAR_DTIM_COUNT_VAP4(x) ((x) & (~BITS_DTIM_COUNT_VAP4)) +#define BIT_GET_DTIM_COUNT_VAP4(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4) & BIT_MASK_DTIM_COUNT_VAP4) +#define BIT_SET_DTIM_COUNT_VAP4(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP4(x) | BIT_DTIM_COUNT_VAP4(v)) -#define BIT_SHIFT_BCN_SPACE_CLINT2 16 -#define BIT_MASK_BCN_SPACE_CLINT2 0xfff -#define BIT_BCN_SPACE_CLINT2(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2) -#define BIT_GET_BCN_SPACE_CLINT2(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2) +/* 2 REG_DTIM_COUNTER_VAP5 (Offset 0x05AD) */ +#define BIT_SHIFT_DTIM_COUNT_VAP5 0 +#define BIT_MASK_DTIM_COUNT_VAP5 0xff +#define BIT_DTIM_COUNT_VAP5(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP5) << BIT_SHIFT_DTIM_COUNT_VAP5) +#define BITS_DTIM_COUNT_VAP5 \ + (BIT_MASK_DTIM_COUNT_VAP5 << BIT_SHIFT_DTIM_COUNT_VAP5) +#define BIT_CLEAR_DTIM_COUNT_VAP5(x) ((x) & (~BITS_DTIM_COUNT_VAP5)) +#define BIT_GET_DTIM_COUNT_VAP5(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5) & BIT_MASK_DTIM_COUNT_VAP5) +#define BIT_SET_DTIM_COUNT_VAP5(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP5(x) | BIT_DTIM_COUNT_VAP5(v)) -#define BIT_SHIFT_BCN_SPACE_CLINT1 0 -#define BIT_MASK_BCN_SPACE_CLINT1 0xfff -#define BIT_BCN_SPACE_CLINT1(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1) -#define BIT_GET_BCN_SPACE_CLINT1(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1) +/* 2 REG_DTIM_COUNTER_VAP6 (Offset 0x05AE) */ +#define BIT_SHIFT_DTIM_COUNT_VAP6 0 +#define BIT_MASK_DTIM_COUNT_VAP6 0xff +#define BIT_DTIM_COUNT_VAP6(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP6) << BIT_SHIFT_DTIM_COUNT_VAP6) +#define BITS_DTIM_COUNT_VAP6 \ + (BIT_MASK_DTIM_COUNT_VAP6 << BIT_SHIFT_DTIM_COUNT_VAP6) +#define BIT_CLEAR_DTIM_COUNT_VAP6(x) ((x) & (~BITS_DTIM_COUNT_VAP6)) +#define BIT_GET_DTIM_COUNT_VAP6(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6) & BIT_MASK_DTIM_COUNT_VAP6) +#define BIT_SET_DTIM_COUNT_VAP6(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP6(x) | BIT_DTIM_COUNT_VAP6(v)) -#endif +/* 2 REG_DTIM_COUNTER_VAP7 (Offset 0x05AF) */ +#define BIT_SHIFT_DTIM_COUNT_VAP7 0 +#define BIT_MASK_DTIM_COUNT_VAP7 0xff +#define BIT_DTIM_COUNT_VAP7(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP7) << BIT_SHIFT_DTIM_COUNT_VAP7) +#define BITS_DTIM_COUNT_VAP7 \ + (BIT_MASK_DTIM_COUNT_VAP7 << BIT_SHIFT_DTIM_COUNT_VAP7) +#define BIT_CLEAR_DTIM_COUNT_VAP7(x) ((x) & (~BITS_DTIM_COUNT_VAP7)) +#define BIT_GET_DTIM_COUNT_VAP7(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7) & BIT_MASK_DTIM_COUNT_VAP7) +#define BIT_SET_DTIM_COUNT_VAP7(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP7(x) | BIT_DTIM_COUNT_VAP7(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ +/* 2 REG_DIS_ATIM (Offset 0x05B0) */ +#define BIT_DIS_ATIM_VAP7 BIT(7) +#define BIT_DIS_ATIM_VAP6 BIT(6) +#define BIT_DIS_ATIM_VAP5 BIT(5) +#define BIT_DIS_ATIM_VAP4 BIT(4) +#define BIT_DIS_ATIM_VAP3 BIT(3) +#define BIT_DIS_ATIM_VAP2 BIT(2) +#define BIT_DIS_ATIM_VAP1 BIT(1) -#define BIT_SHIFT_BCNERR_CNT_OTHERS 24 -#define BIT_MASK_BCNERR_CNT_OTHERS 0xff -#define BIT_BCNERR_CNT_OTHERS(x) (((x) & BIT_MASK_BCNERR_CNT_OTHERS) << BIT_SHIFT_BCNERR_CNT_OTHERS) -#define BIT_GET_BCNERR_CNT_OTHERS(x) (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS) & BIT_MASK_BCNERR_CNT_OTHERS) +#endif -#define BIT_BCNERR_CNT_EN BIT(20) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SUB_BCN_SPACE_V1 16 -#define BIT_MASK_SUB_BCN_SPACE_V1 0xfff -#define BIT_SUB_BCN_SPACE_V1(x) (((x) & BIT_MASK_SUB_BCN_SPACE_V1) << BIT_SHIFT_SUB_BCN_SPACE_V1) -#define BIT_GET_SUB_BCN_SPACE_V1(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V1) & BIT_MASK_SUB_BCN_SPACE_V1) +/* 2 REG_DIS_ATIM (Offset 0x05B0) */ +#define BIT_DIS_ATIM_ROOT BIT(0) -#define BIT_SHIFT_BCNERR_PORT_SEL 16 -#define BIT_MASK_BCNERR_PORT_SEL 0x7 -#define BIT_BCNERR_PORT_SEL(x) (((x) & BIT_MASK_BCNERR_PORT_SEL) << BIT_SHIFT_BCNERR_PORT_SEL) -#define BIT_GET_BCNERR_PORT_SEL(x) (((x) >> BIT_SHIFT_BCNERR_PORT_SEL) & BIT_MASK_BCNERR_PORT_SEL) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXBCN_TIMER 16 -#define BIT_MASK_RXBCN_TIMER 0xffff -#define BIT_RXBCN_TIMER(x) (((x) & BIT_MASK_RXBCN_TIMER) << BIT_SHIFT_RXBCN_TIMER) -#define BIT_GET_RXBCN_TIMER(x) (((x) >> BIT_SHIFT_RXBCN_TIMER) & BIT_MASK_RXBCN_TIMER) +/* 2 REG_EARLY_128US (Offset 0x05B1) */ +#define BIT_SHIFT_TSFT_SEL_TIMER1 3 +#define BIT_MASK_TSFT_SEL_TIMER1 0x7 +#define BIT_TSFT_SEL_TIMER1(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1) +#define BITS_TSFT_SEL_TIMER1 \ + (BIT_MASK_TSFT_SEL_TIMER1 << BIT_SHIFT_TSFT_SEL_TIMER1) +#define BIT_CLEAR_TSFT_SEL_TIMER1(x) ((x) & (~BITS_TSFT_SEL_TIMER1)) +#define BIT_GET_TSFT_SEL_TIMER1(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1) +#define BIT_SET_TSFT_SEL_TIMER1(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER1(x) | BIT_TSFT_SEL_TIMER1(v)) -#define BIT_SHIFT_BCNERR_CNT_INVALID 16 -#define BIT_MASK_BCNERR_CNT_INVALID 0xff -#define BIT_BCNERR_CNT_INVALID(x) (((x) & BIT_MASK_BCNERR_CNT_INVALID) << BIT_SHIFT_BCNERR_CNT_INVALID) -#define BIT_GET_BCNERR_CNT_INVALID(x) (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID) & BIT_MASK_BCNERR_CNT_INVALID) +/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ +#define BIT_P2P1_CTW_ALLSTASLEEP BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ - - -#define BIT_SHIFT_SUB_BCN_SPACE 16 -#define BIT_MASK_SUB_BCN_SPACE 0xff -#define BIT_SUB_BCN_SPACE(x) (((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE) -#define BIT_GET_SUB_BCN_SPACE(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE) +/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ +#define BIT_P2P1_OFF_DISTX_EN BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ - - -#define BIT_SHIFT_TXPAUSE1 8 -#define BIT_MASK_TXPAUSE1 0xff -#define BIT_TXPAUSE1(x) (((x) & BIT_MASK_TXPAUSE1) << BIT_SHIFT_TXPAUSE1) -#define BIT_GET_TXPAUSE1(x) (((x) >> BIT_SHIFT_TXPAUSE1) & BIT_MASK_TXPAUSE1) +/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ +#define BIT_P2P1_PWR_MGT_EN BIT(5) +#define BIT_P2P1_NOA1_EN BIT(2) +#define BIT_P2P1_NOA0_EN BIT(1) -#define BIT_SHIFT_BCNERR_CNT_MAC 8 -#define BIT_MASK_BCNERR_CNT_MAC 0xff -#define BIT_BCNERR_CNT_MAC(x) (((x) & BIT_MASK_BCNERR_CNT_MAC) << BIT_SHIFT_BCNERR_CNT_MAC) -#define BIT_GET_BCNERR_CNT_MAC(x) (((x) >> BIT_SHIFT_BCNERR_CNT_MAC) & BIT_MASK_BCNERR_CNT_MAC) +/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ -#define BIT_CHANGE_POW_BCN_AREA BIT(1) +#define BIT_P2P2_CTW_ALLSTASLEEP BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ - - -#define BIT_SHIFT_BCN_SPACE_CLINT3 0 -#define BIT_MASK_BCN_SPACE_CLINT3 0xfff -#define BIT_BCN_SPACE_CLINT3(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3) -#define BIT_GET_BCN_SPACE_CLINT3(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3) +/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ +#define BIT_P2P2_OFF_DISTX_EN BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ +#define BIT_P2P2_PWR_MGT_EN BIT(5) +#define BIT_P2P2_NOA1_EN BIT(2) +#define BIT_P2P2_NOA0_EN BIT(1) -/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ +/* 2 REG_TIMER0_SRC_SEL (Offset 0x05B4) */ +#define BIT_SHIFT_SYNC_CLI_SEL 4 +#define BIT_MASK_SYNC_CLI_SEL 0x7 +#define BIT_SYNC_CLI_SEL(x) \ + (((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL) +#define BITS_SYNC_CLI_SEL (BIT_MASK_SYNC_CLI_SEL << BIT_SHIFT_SYNC_CLI_SEL) +#define BIT_CLEAR_SYNC_CLI_SEL(x) ((x) & (~BITS_SYNC_CLI_SEL)) +#define BIT_GET_SYNC_CLI_SEL(x) \ + (((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL) +#define BIT_SET_SYNC_CLI_SEL(x, v) \ + (BIT_CLEAR_SYNC_CLI_SEL(x) | BIT_SYNC_CLI_SEL(v)) + +#define BIT_SHIFT_TSFT_SEL_TIMER0 0 +#define BIT_MASK_TSFT_SEL_TIMER0 0x7 +#define BIT_TSFT_SEL_TIMER0(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0) +#define BITS_TSFT_SEL_TIMER0 \ + (BIT_MASK_TSFT_SEL_TIMER0 << BIT_SHIFT_TSFT_SEL_TIMER0) +#define BIT_CLEAR_TSFT_SEL_TIMER0(x) ((x) & (~BITS_TSFT_SEL_TIMER0)) +#define BIT_GET_TSFT_SEL_TIMER0(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0) +#define BIT_SET_TSFT_SEL_TIMER0(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER0(x) | BIT_TSFT_SEL_TIMER0(v)) -#define BIT_SHIFT_BW_CFG 0 -#define BIT_MASK_BW_CFG 0x3 -#define BIT_BW_CFG(x) (((x) & BIT_MASK_BW_CFG) << BIT_SHIFT_BW_CFG) -#define BIT_GET_BW_CFG(x) (((x) >> BIT_SHIFT_BW_CFG) & BIT_MASK_BW_CFG) +/* 2 REG_NOA_UNIT_SEL (Offset 0x05B5) */ +#define BIT_SHIFT_NOA_UNIT2_SEL 8 +#define BIT_MASK_NOA_UNIT2_SEL 0x7 +#define BIT_NOA_UNIT2_SEL(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL) +#define BITS_NOA_UNIT2_SEL (BIT_MASK_NOA_UNIT2_SEL << BIT_SHIFT_NOA_UNIT2_SEL) +#define BIT_CLEAR_NOA_UNIT2_SEL(x) ((x) & (~BITS_NOA_UNIT2_SEL)) +#define BIT_GET_NOA_UNIT2_SEL(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL) +#define BIT_SET_NOA_UNIT2_SEL(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL(x) | BIT_NOA_UNIT2_SEL(v)) + +#define BIT_SHIFT_NOA_UNIT1_SEL 4 +#define BIT_MASK_NOA_UNIT1_SEL 0x7 +#define BIT_NOA_UNIT1_SEL(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL) +#define BITS_NOA_UNIT1_SEL (BIT_MASK_NOA_UNIT1_SEL << BIT_SHIFT_NOA_UNIT1_SEL) +#define BIT_CLEAR_NOA_UNIT1_SEL(x) ((x) & (~BITS_NOA_UNIT1_SEL)) +#define BIT_GET_NOA_UNIT1_SEL(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL) +#define BIT_SET_NOA_UNIT1_SEL(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL(x) | BIT_NOA_UNIT1_SEL(v)) + +#define BIT_SHIFT_NOA_UNIT0_SEL 0 +#define BIT_MASK_NOA_UNIT0_SEL 0x7 +#define BIT_NOA_UNIT0_SEL(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL) +#define BITS_NOA_UNIT0_SEL (BIT_MASK_NOA_UNIT0_SEL << BIT_SHIFT_NOA_UNIT0_SEL) +#define BIT_CLEAR_NOA_UNIT0_SEL(x) ((x) & (~BITS_NOA_UNIT0_SEL)) +#define BIT_GET_NOA_UNIT0_SEL(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL) +#define BIT_SET_NOA_UNIT0_SEL(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL(x) | BIT_NOA_UNIT0_SEL(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BCN_ELY_ADJ 0 -#define BIT_MASK_BCN_ELY_ADJ 0xffff -#define BIT_BCN_ELY_ADJ(x) (((x) & BIT_MASK_BCN_ELY_ADJ) << BIT_SHIFT_BCN_ELY_ADJ) -#define BIT_GET_BCN_ELY_ADJ(x) (((x) >> BIT_SHIFT_BCN_ELY_ADJ) & BIT_MASK_BCN_ELY_ADJ) +/* 2 REG_P2POFF_DIS_TXTIME (Offset 0x05B7) */ +#define BIT_SHIFT_P2POFF_DIS_TXTIME 0 +#define BIT_MASK_P2POFF_DIS_TXTIME 0xff +#define BIT_P2POFF_DIS_TXTIME(x) \ + (((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME) +#define BITS_P2POFF_DIS_TXTIME \ + (BIT_MASK_P2POFF_DIS_TXTIME << BIT_SHIFT_P2POFF_DIS_TXTIME) +#define BIT_CLEAR_P2POFF_DIS_TXTIME(x) ((x) & (~BITS_P2POFF_DIS_TXTIME)) +#define BIT_GET_P2POFF_DIS_TXTIME(x) \ + (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME) +#define BIT_SET_P2POFF_DIS_TXTIME(x, v) \ + (BIT_CLEAR_P2POFF_DIS_TXTIME(x) | BIT_P2POFF_DIS_TXTIME(v)) -#define BIT_SHIFT_BCNERR_CNT_CCA 0 -#define BIT_MASK_BCNERR_CNT_CCA 0xff -#define BIT_BCNERR_CNT_CCA(x) (((x) & BIT_MASK_BCNERR_CNT_CCA) << BIT_SHIFT_BCNERR_CNT_CCA) -#define BIT_GET_BCNERR_CNT_CCA(x) (((x) >> BIT_SHIFT_BCNERR_CNT_CCA) & BIT_MASK_BCNERR_CNT_CCA) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MBSSID_BCN_SPACE2 (Offset 0x05B8) */ +#define BIT_SHIFT_BCN_SPACE_CLINT2 16 +#define BIT_MASK_BCN_SPACE_CLINT2 0xfff +#define BIT_BCN_SPACE_CLINT2(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2) +#define BITS_BCN_SPACE_CLINT2 \ + (BIT_MASK_BCN_SPACE_CLINT2 << BIT_SHIFT_BCN_SPACE_CLINT2) +#define BIT_CLEAR_BCN_SPACE_CLINT2(x) ((x) & (~BITS_BCN_SPACE_CLINT2)) +#define BIT_GET_BCN_SPACE_CLINT2(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2) +#define BIT_SET_BCN_SPACE_CLINT2(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT2(x) | BIT_BCN_SPACE_CLINT2(v)) + +#define BIT_SHIFT_BCN_SPACE_CLINT1 0 +#define BIT_MASK_BCN_SPACE_CLINT1 0xfff +#define BIT_BCN_SPACE_CLINT1(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1) +#define BITS_BCN_SPACE_CLINT1 \ + (BIT_MASK_BCN_SPACE_CLINT1 << BIT_SHIFT_BCN_SPACE_CLINT1) +#define BIT_CLEAR_BCN_SPACE_CLINT1(x) ((x) & (~BITS_BCN_SPACE_CLINT1)) +#define BIT_GET_BCN_SPACE_CLINT1(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1) +#define BIT_SET_BCN_SPACE_CLINT1(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT1(x) | BIT_BCN_SPACE_CLINT1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ +#define BIT_SHIFT_SUB_BCN_SPACE 16 +#define BIT_MASK_SUB_BCN_SPACE 0xff +#define BIT_SUB_BCN_SPACE(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE) +#define BITS_SUB_BCN_SPACE (BIT_MASK_SUB_BCN_SPACE << BIT_SHIFT_SUB_BCN_SPACE) +#define BIT_CLEAR_SUB_BCN_SPACE(x) ((x) & (~BITS_SUB_BCN_SPACE)) +#define BIT_GET_SUB_BCN_SPACE(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE) +#define BIT_SET_SUB_BCN_SPACE(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE(x) | BIT_SUB_BCN_SPACE(v)) + +#define BIT_SHIFT_BCN_SPACE_CLINT3 0 +#define BIT_MASK_BCN_SPACE_CLINT3 0xfff +#define BIT_BCN_SPACE_CLINT3(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3) +#define BITS_BCN_SPACE_CLINT3 \ + (BIT_MASK_BCN_SPACE_CLINT3 << BIT_SHIFT_BCN_SPACE_CLINT3) +#define BIT_CLEAR_BCN_SPACE_CLINT3(x) ((x) & (~BITS_BCN_SPACE_CLINT3)) +#define BIT_GET_BCN_SPACE_CLINT3(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3) +#define BIT_SET_BCN_SPACE_CLINT3(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT3(x) | BIT_BCN_SPACE_CLINT3(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_ACMHWCTRL (Offset 0x05C0) */ -#define BIT_BEQ_ACM_STATUS BIT(7) -#define BIT_VIQ_ACM_STATUS BIT(6) -#define BIT_VOQ_ACM_STATUS BIT(5) -#define BIT_BEQ_ACM_EN BIT(3) -#define BIT_VIQ_ACM_EN BIT(2) -#define BIT_VOQ_ACM_EN BIT(1) -#define BIT_ACMHWEN BIT(0) +#define BIT_BEQ_ACM_STATUS BIT(7) +#define BIT_VIQ_ACM_STATUS BIT(6) +#define BIT_VOQ_ACM_STATUS BIT(5) +#define BIT_BEQ_ACM_EN BIT(3) +#define BIT_VIQ_ACM_EN BIT(2) +#define BIT_VOQ_ACM_EN BIT(1) +#define BIT_ACMHWEN BIT(0) /* 2 REG_ACMRSTCTRL (Offset 0x05C1) */ -#define BIT_BE_ACM_RESET_USED_TIME BIT(2) -#define BIT_VI_ACM_RESET_USED_TIME BIT(1) -#define BIT_VO_ACM_RESET_USED_TIME BIT(0) +#define BIT_BE_ACM_RESET_USED_TIME BIT(2) +#define BIT_VI_ACM_RESET_USED_TIME BIT(1) +#define BIT_VO_ACM_RESET_USED_TIME BIT(0) /* 2 REG_ACMAVG (Offset 0x05C2) */ - -#define BIT_SHIFT_AVGPERIOD 0 -#define BIT_MASK_AVGPERIOD 0xffff -#define BIT_AVGPERIOD(x) (((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD) -#define BIT_GET_AVGPERIOD(x) (((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD) - +#define BIT_SHIFT_AVGPERIOD 0 +#define BIT_MASK_AVGPERIOD 0xffff +#define BIT_AVGPERIOD(x) (((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD) +#define BITS_AVGPERIOD (BIT_MASK_AVGPERIOD << BIT_SHIFT_AVGPERIOD) +#define BIT_CLEAR_AVGPERIOD(x) ((x) & (~BITS_AVGPERIOD)) +#define BIT_GET_AVGPERIOD(x) (((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD) +#define BIT_SET_AVGPERIOD(x, v) (BIT_CLEAR_AVGPERIOD(x) | BIT_AVGPERIOD(v)) /* 2 REG_VO_ADMTIME (Offset 0x05C4) */ - -#define BIT_SHIFT_VO_ADMITTED_TIME 0 -#define BIT_MASK_VO_ADMITTED_TIME 0xffff -#define BIT_VO_ADMITTED_TIME(x) (((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME) -#define BIT_GET_VO_ADMITTED_TIME(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME) - +#define BIT_SHIFT_VO_ADMITTED_TIME 0 +#define BIT_MASK_VO_ADMITTED_TIME 0xffff +#define BIT_VO_ADMITTED_TIME(x) \ + (((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME) +#define BITS_VO_ADMITTED_TIME \ + (BIT_MASK_VO_ADMITTED_TIME << BIT_SHIFT_VO_ADMITTED_TIME) +#define BIT_CLEAR_VO_ADMITTED_TIME(x) ((x) & (~BITS_VO_ADMITTED_TIME)) +#define BIT_GET_VO_ADMITTED_TIME(x) \ + (((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME) +#define BIT_SET_VO_ADMITTED_TIME(x, v) \ + (BIT_CLEAR_VO_ADMITTED_TIME(x) | BIT_VO_ADMITTED_TIME(v)) /* 2 REG_VI_ADMTIME (Offset 0x05C6) */ - -#define BIT_SHIFT_VI_ADMITTED_TIME 0 -#define BIT_MASK_VI_ADMITTED_TIME 0xffff -#define BIT_VI_ADMITTED_TIME(x) (((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME) -#define BIT_GET_VI_ADMITTED_TIME(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME) - +#define BIT_SHIFT_VI_ADMITTED_TIME 0 +#define BIT_MASK_VI_ADMITTED_TIME 0xffff +#define BIT_VI_ADMITTED_TIME(x) \ + (((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME) +#define BITS_VI_ADMITTED_TIME \ + (BIT_MASK_VI_ADMITTED_TIME << BIT_SHIFT_VI_ADMITTED_TIME) +#define BIT_CLEAR_VI_ADMITTED_TIME(x) ((x) & (~BITS_VI_ADMITTED_TIME)) +#define BIT_GET_VI_ADMITTED_TIME(x) \ + (((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME) +#define BIT_SET_VI_ADMITTED_TIME(x, v) \ + (BIT_CLEAR_VI_ADMITTED_TIME(x) | BIT_VI_ADMITTED_TIME(v)) /* 2 REG_BE_ADMTIME (Offset 0x05C8) */ +#define BIT_SHIFT_BE_ADMITTED_TIME 0 +#define BIT_MASK_BE_ADMITTED_TIME 0xffff +#define BIT_BE_ADMITTED_TIME(x) \ + (((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME) +#define BITS_BE_ADMITTED_TIME \ + (BIT_MASK_BE_ADMITTED_TIME << BIT_SHIFT_BE_ADMITTED_TIME) +#define BIT_CLEAR_BE_ADMITTED_TIME(x) ((x) & (~BITS_BE_ADMITTED_TIME)) +#define BIT_GET_BE_ADMITTED_TIME(x) \ + (((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME) +#define BIT_SET_BE_ADMITTED_TIME(x, v) \ + (BIT_CLEAR_BE_ADMITTED_TIME(x) | BIT_BE_ADMITTED_TIME(v)) -#define BIT_SHIFT_BE_ADMITTED_TIME 0 -#define BIT_MASK_BE_ADMITTED_TIME 0xffff -#define BIT_BE_ADMITTED_TIME(x) (((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME) -#define BIT_GET_BE_ADMITTED_TIME(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME) - - -/* 2 REG_EDCA_RANDOM_GEN (Offset 0x05CC) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RANDOM_GEN 0 -#define BIT_MASK_RANDOM_GEN 0xffffff -#define BIT_RANDOM_GEN(x) (((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN) -#define BIT_GET_RANDOM_GEN(x) (((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN) +/* 2 REG_MAC_HEADER_NAV_OFFSET (Offset 0x05CA) */ +#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET 0 +#define BIT_MASK_MAC_HEADER_NAV_OFFSET 0xff +#define BIT_MAC_HEADER_NAV_OFFSET(x) \ + (((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET) \ + << BIT_SHIFT_MAC_HEADER_NAV_OFFSET) +#define BITS_MAC_HEADER_NAV_OFFSET \ + (BIT_MASK_MAC_HEADER_NAV_OFFSET << BIT_SHIFT_MAC_HEADER_NAV_OFFSET) +#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET(x) ((x) & (~BITS_MAC_HEADER_NAV_OFFSET)) +#define BIT_GET_MAC_HEADER_NAV_OFFSET(x) \ + (((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET) & \ + BIT_MASK_MAC_HEADER_NAV_OFFSET) +#define BIT_SET_MAC_HEADER_NAV_OFFSET(x, v) \ + (BIT_CLEAR_MAC_HEADER_NAV_OFFSET(x) | BIT_MAC_HEADER_NAV_OFFSET(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) - - -/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ +/* 2 REG_DIS_NDPA_NAV_CHECK (Offset 0x05CB) */ -#define BIT_NOA_SEL BIT(4) +#define BIT_CHG_POWER_BCN_AREA_V1 BIT(1) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_DIS_NDPA_NAV_CHECK (Offset 0x05CB) */ -/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ +#define BIT_DIS_NDPA_NAV_CHECK BIT(0) +#endif -#define BIT_SHIFT_NOA_SEL 4 -#define BIT_MASK_NOA_SEL 0x7 -#define BIT_NOA_SEL(x) (((x) & BIT_MASK_NOA_SEL) << BIT_SHIFT_NOA_SEL) -#define BIT_GET_NOA_SEL(x) (((x) >> BIT_SHIFT_NOA_SEL) & BIT_MASK_NOA_SEL) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) +/* 2 REG_EDCA_RANDOM_GEN (Offset 0x05CC) */ -#endif +#define BIT_SHIFT_RANDOM_GEN 0 +#define BIT_MASK_RANDOM_GEN 0xffffff +#define BIT_RANDOM_GEN(x) (((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN) +#define BITS_RANDOM_GEN (BIT_MASK_RANDOM_GEN << BIT_SHIFT_RANDOM_GEN) +#define BIT_CLEAR_RANDOM_GEN(x) ((x) & (~BITS_RANDOM_GEN)) +#define BIT_GET_RANDOM_GEN(x) \ + (((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN) +#define BIT_SET_RANDOM_GEN(x, v) (BIT_CLEAR_RANDOM_GEN(x) | BIT_RANDOM_GEN(v)) +#define BIT_SHIFT_TXCMD_SEG_SEL 0 +#define BIT_MASK_TXCMD_SEG_SEL 0xf +#define BIT_TXCMD_SEG_SEL(x) \ + (((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL) +#define BITS_TXCMD_SEG_SEL (BIT_MASK_TXCMD_SEG_SEL << BIT_SHIFT_TXCMD_SEG_SEL) +#define BIT_CLEAR_TXCMD_SEG_SEL(x) ((x) & (~BITS_TXCMD_SEG_SEL)) +#define BIT_GET_TXCMD_SEG_SEL(x) \ + (((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL) +#define BIT_SET_TXCMD_SEG_SEL(x, v) \ + (BIT_CLEAR_TXCMD_SEG_SEL(x) | BIT_TXCMD_SEG_SEL(v)) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ -#define BIT_NOA_SEL_V1 BIT(4) +#define BIT_NOA_SEL BIT(4) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ +#define BIT_SHIFT_NOA_SEL_V2 4 +#define BIT_MASK_NOA_SEL_V2 0x7 +#define BIT_NOA_SEL_V2(x) (((x) & BIT_MASK_NOA_SEL_V2) << BIT_SHIFT_NOA_SEL_V2) +#define BITS_NOA_SEL_V2 (BIT_MASK_NOA_SEL_V2 << BIT_SHIFT_NOA_SEL_V2) +#define BIT_CLEAR_NOA_SEL_V2(x) ((x) & (~BITS_NOA_SEL_V2)) +#define BIT_GET_NOA_SEL_V2(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V2) & BIT_MASK_NOA_SEL_V2) +#define BIT_SET_NOA_SEL_V2(x, v) (BIT_CLEAR_NOA_SEL_V2(x) | BIT_NOA_SEL_V2(v)) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_32K_CLK_SEL (Offset 0x05D0) */ + +#define BIT_R_BCNERR_CNT_EN BIT(20) + +#define BIT_SHIFT_R_BCNERR_PORT_SEL 16 +#define BIT_MASK_R_BCNERR_PORT_SEL 0x7 +#define BIT_R_BCNERR_PORT_SEL(x) \ + (((x) & BIT_MASK_R_BCNERR_PORT_SEL) << BIT_SHIFT_R_BCNERR_PORT_SEL) +#define BITS_R_BCNERR_PORT_SEL \ + (BIT_MASK_R_BCNERR_PORT_SEL << BIT_SHIFT_R_BCNERR_PORT_SEL) +#define BIT_CLEAR_R_BCNERR_PORT_SEL(x) ((x) & (~BITS_R_BCNERR_PORT_SEL)) +#define BIT_GET_R_BCNERR_PORT_SEL(x) \ + (((x) >> BIT_SHIFT_R_BCNERR_PORT_SEL) & BIT_MASK_R_BCNERR_PORT_SEL) +#define BIT_SET_R_BCNERR_PORT_SEL(x, v) \ + (BIT_CLEAR_R_BCNERR_PORT_SEL(x) | BIT_R_BCNERR_PORT_SEL(v)) + +#define BIT_SHIFT_R_TXPAUSE1 8 +#define BIT_MASK_R_TXPAUSE1 0xff +#define BIT_R_TXPAUSE1(x) (((x) & BIT_MASK_R_TXPAUSE1) << BIT_SHIFT_R_TXPAUSE1) +#define BITS_R_TXPAUSE1 (BIT_MASK_R_TXPAUSE1 << BIT_SHIFT_R_TXPAUSE1) +#define BIT_CLEAR_R_TXPAUSE1(x) ((x) & (~BITS_R_TXPAUSE1)) +#define BIT_GET_R_TXPAUSE1(x) \ + (((x) >> BIT_SHIFT_R_TXPAUSE1) & BIT_MASK_R_TXPAUSE1) +#define BIT_SET_R_TXPAUSE1(x, v) (BIT_CLEAR_R_TXPAUSE1(x) | BIT_R_TXPAUSE1(v)) + +#define BIT_SLEEP_32K_EN_V1 BIT(2) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_EARLYINT_ADJUST (Offset 0x05D4) */ + +#define BIT_SHIFT_RXBCN_TIMER 16 +#define BIT_MASK_RXBCN_TIMER 0xffff +#define BIT_RXBCN_TIMER(x) \ + (((x) & BIT_MASK_RXBCN_TIMER) << BIT_SHIFT_RXBCN_TIMER) +#define BITS_RXBCN_TIMER (BIT_MASK_RXBCN_TIMER << BIT_SHIFT_RXBCN_TIMER) +#define BIT_CLEAR_RXBCN_TIMER(x) ((x) & (~BITS_RXBCN_TIMER)) +#define BIT_GET_RXBCN_TIMER(x) \ + (((x) >> BIT_SHIFT_RXBCN_TIMER) & BIT_MASK_RXBCN_TIMER) +#define BIT_SET_RXBCN_TIMER(x, v) \ + (BIT_CLEAR_RXBCN_TIMER(x) | BIT_RXBCN_TIMER(v)) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_EARLYINT_ADJUST (Offset 0x05D4) */ + +#define BIT_SHIFT_R_ERLYINTADJ 0 +#define BIT_MASK_R_ERLYINTADJ 0xffff +#define BIT_R_ERLYINTADJ(x) \ + (((x) & BIT_MASK_R_ERLYINTADJ) << BIT_SHIFT_R_ERLYINTADJ) +#define BITS_R_ERLYINTADJ (BIT_MASK_R_ERLYINTADJ << BIT_SHIFT_R_ERLYINTADJ) +#define BIT_CLEAR_R_ERLYINTADJ(x) ((x) & (~BITS_R_ERLYINTADJ)) +#define BIT_GET_R_ERLYINTADJ(x) \ + (((x) >> BIT_SHIFT_R_ERLYINTADJ) & BIT_MASK_R_ERLYINTADJ) +#define BIT_SET_R_ERLYINTADJ(x, v) \ + (BIT_CLEAR_R_ERLYINTADJ(x) | BIT_R_ERLYINTADJ(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_BCNERR_CNT (Offset 0x05D8) */ + +#define BIT_SHIFT_BCNERR_CNT_OTHERS 24 +#define BIT_MASK_BCNERR_CNT_OTHERS 0xff +#define BIT_BCNERR_CNT_OTHERS(x) \ + (((x) & BIT_MASK_BCNERR_CNT_OTHERS) << BIT_SHIFT_BCNERR_CNT_OTHERS) +#define BITS_BCNERR_CNT_OTHERS \ + (BIT_MASK_BCNERR_CNT_OTHERS << BIT_SHIFT_BCNERR_CNT_OTHERS) +#define BIT_CLEAR_BCNERR_CNT_OTHERS(x) ((x) & (~BITS_BCNERR_CNT_OTHERS)) +#define BIT_GET_BCNERR_CNT_OTHERS(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS) & BIT_MASK_BCNERR_CNT_OTHERS) +#define BIT_SET_BCNERR_CNT_OTHERS(x, v) \ + (BIT_CLEAR_BCNERR_CNT_OTHERS(x) | BIT_BCNERR_CNT_OTHERS(v)) + +#define BIT_SHIFT_BCNERR_CNT_INVALID 16 +#define BIT_MASK_BCNERR_CNT_INVALID 0xff +#define BIT_BCNERR_CNT_INVALID(x) \ + (((x) & BIT_MASK_BCNERR_CNT_INVALID) << BIT_SHIFT_BCNERR_CNT_INVALID) +#define BITS_BCNERR_CNT_INVALID \ + (BIT_MASK_BCNERR_CNT_INVALID << BIT_SHIFT_BCNERR_CNT_INVALID) +#define BIT_CLEAR_BCNERR_CNT_INVALID(x) ((x) & (~BITS_BCNERR_CNT_INVALID)) +#define BIT_GET_BCNERR_CNT_INVALID(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID) & BIT_MASK_BCNERR_CNT_INVALID) +#define BIT_SET_BCNERR_CNT_INVALID(x, v) \ + (BIT_CLEAR_BCNERR_CNT_INVALID(x) | BIT_BCNERR_CNT_INVALID(v)) + +#define BIT_SHIFT_BCNERR_CNT_MAC 8 +#define BIT_MASK_BCNERR_CNT_MAC 0xff +#define BIT_BCNERR_CNT_MAC(x) \ + (((x) & BIT_MASK_BCNERR_CNT_MAC) << BIT_SHIFT_BCNERR_CNT_MAC) +#define BITS_BCNERR_CNT_MAC \ + (BIT_MASK_BCNERR_CNT_MAC << BIT_SHIFT_BCNERR_CNT_MAC) +#define BIT_CLEAR_BCNERR_CNT_MAC(x) ((x) & (~BITS_BCNERR_CNT_MAC)) +#define BIT_GET_BCNERR_CNT_MAC(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_MAC) & BIT_MASK_BCNERR_CNT_MAC) +#define BIT_SET_BCNERR_CNT_MAC(x, v) \ + (BIT_CLEAR_BCNERR_CNT_MAC(x) | BIT_BCNERR_CNT_MAC(v)) + +#define BIT_SHIFT_BCNERR_CNT_CCA 0 +#define BIT_MASK_BCNERR_CNT_CCA 0xff +#define BIT_BCNERR_CNT_CCA(x) \ + (((x) & BIT_MASK_BCNERR_CNT_CCA) << BIT_SHIFT_BCNERR_CNT_CCA) +#define BITS_BCNERR_CNT_CCA \ + (BIT_MASK_BCNERR_CNT_CCA << BIT_SHIFT_BCNERR_CNT_CCA) +#define BIT_CLEAR_BCNERR_CNT_CCA(x) ((x) & (~BITS_BCNERR_CNT_CCA)) +#define BIT_GET_BCNERR_CNT_CCA(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_CCA) & BIT_MASK_BCNERR_CNT_CCA) +#define BIT_SET_BCNERR_CNT_CCA(x, v) \ + (BIT_CLEAR_BCNERR_CNT_CCA(x) | BIT_BCNERR_CNT_CCA(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TXCMD_SEG_SEL 0 -#define BIT_MASK_TXCMD_SEG_SEL 0xf -#define BIT_TXCMD_SEG_SEL(x) (((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL) -#define BIT_GET_TXCMD_SEG_SEL(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL) +/* 2 REG_NOA_PARAM (Offset 0x05E0) */ +#define BIT_SHIFT_NOA_COUNT (96 & CPU_OPT_WIDTH) +#define BIT_MASK_NOA_COUNT 0xff +#define BIT_NOA_COUNT(x) (((x) & BIT_MASK_NOA_COUNT) << BIT_SHIFT_NOA_COUNT) +#define BITS_NOA_COUNT (BIT_MASK_NOA_COUNT << BIT_SHIFT_NOA_COUNT) +#define BIT_CLEAR_NOA_COUNT(x) ((x) & (~BITS_NOA_COUNT)) +#define BIT_GET_NOA_COUNT(x) (((x) >> BIT_SHIFT_NOA_COUNT) & BIT_MASK_NOA_COUNT) +#define BIT_SET_NOA_COUNT(x, v) (BIT_CLEAR_NOA_COUNT(x) | BIT_NOA_COUNT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_NOA_PARAM (Offset 0x05E0) */ +#define BIT_SHIFT_NOA_DURATION 0 +#define BIT_MASK_NOA_DURATION 0xffffffffL +#define BIT_NOA_DURATION(x) \ + (((x) & BIT_MASK_NOA_DURATION) << BIT_SHIFT_NOA_DURATION) +#define BITS_NOA_DURATION (BIT_MASK_NOA_DURATION << BIT_SHIFT_NOA_DURATION) +#define BIT_CLEAR_NOA_DURATION(x) ((x) & (~BITS_NOA_DURATION)) +#define BIT_GET_NOA_DURATION(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION) & BIT_MASK_NOA_DURATION) +#define BIT_SET_NOA_DURATION(x, v) \ + (BIT_CLEAR_NOA_DURATION(x) | BIT_NOA_DURATION(v)) -/* 2 REG_NOA_PARAM (Offset 0x05E0) */ +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NOA_COUNT (96 & CPU_OPT_WIDTH) -#define BIT_MASK_NOA_COUNT 0xff -#define BIT_NOA_COUNT(x) (((x) & BIT_MASK_NOA_COUNT) << BIT_SHIFT_NOA_COUNT) -#define BIT_GET_NOA_COUNT(x) (((x) >> BIT_SHIFT_NOA_COUNT) & BIT_MASK_NOA_COUNT) +/* 2 REG_NOA_PARAM (Offset 0x05E0) */ +#define BIT_SHIFT_NOA_DURATION_V1 0 +#define BIT_MASK_NOA_DURATION_V1 0xffffffffL +#define BIT_NOA_DURATION_V1(x) \ + (((x) & BIT_MASK_NOA_DURATION_V1) << BIT_SHIFT_NOA_DURATION_V1) +#define BITS_NOA_DURATION_V1 \ + (BIT_MASK_NOA_DURATION_V1 << BIT_SHIFT_NOA_DURATION_V1) +#define BIT_CLEAR_NOA_DURATION_V1(x) ((x) & (~BITS_NOA_DURATION_V1)) +#define BIT_GET_NOA_DURATION_V1(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION_V1) & BIT_MASK_NOA_DURATION_V1) +#define BIT_SET_NOA_DURATION_V1(x, v) \ + (BIT_CLEAR_NOA_DURATION_V1(x) | BIT_NOA_DURATION_V1(v)) -#define BIT_SHIFT_NOA_START_TIME (64 & CPU_OPT_WIDTH) -#define BIT_MASK_NOA_START_TIME 0xffffffffL -#define BIT_NOA_START_TIME(x) (((x) & BIT_MASK_NOA_START_TIME) << BIT_SHIFT_NOA_START_TIME) -#define BIT_GET_NOA_START_TIME(x) (((x) >> BIT_SHIFT_NOA_START_TIME) & BIT_MASK_NOA_START_TIME) +/* 2 REG_NOA_PARAM_1 (Offset 0x05E4) */ +#define BIT_SHIFT_NOA_INTERVAL_V1 0 +#define BIT_MASK_NOA_INTERVAL_V1 0xffffffffL +#define BIT_NOA_INTERVAL_V1(x) \ + (((x) & BIT_MASK_NOA_INTERVAL_V1) << BIT_SHIFT_NOA_INTERVAL_V1) +#define BITS_NOA_INTERVAL_V1 \ + (BIT_MASK_NOA_INTERVAL_V1 << BIT_SHIFT_NOA_INTERVAL_V1) +#define BIT_CLEAR_NOA_INTERVAL_V1(x) ((x) & (~BITS_NOA_INTERVAL_V1)) +#define BIT_GET_NOA_INTERVAL_V1(x) \ + (((x) >> BIT_SHIFT_NOA_INTERVAL_V1) & BIT_MASK_NOA_INTERVAL_V1) +#define BIT_SET_NOA_INTERVAL_V1(x, v) \ + (BIT_CLEAR_NOA_INTERVAL_V1(x) | BIT_NOA_INTERVAL_V1(v)) -#define BIT_SHIFT_NOA_INTERVAL (32 & CPU_OPT_WIDTH) -#define BIT_MASK_NOA_INTERVAL 0xffffffffL -#define BIT_NOA_INTERVAL(x) (((x) & BIT_MASK_NOA_INTERVAL) << BIT_SHIFT_NOA_INTERVAL) -#define BIT_GET_NOA_INTERVAL(x) (((x) >> BIT_SHIFT_NOA_INTERVAL) & BIT_MASK_NOA_INTERVAL) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_NOA_DURATION 0 -#define BIT_MASK_NOA_DURATION 0xffffffffL -#define BIT_NOA_DURATION(x) (((x) & BIT_MASK_NOA_DURATION) << BIT_SHIFT_NOA_DURATION) -#define BIT_GET_NOA_DURATION(x) (((x) >> BIT_SHIFT_NOA_DURATION) & BIT_MASK_NOA_DURATION) +/* 2 REG_MU_DBG_INFO (Offset 0x05E8) */ +#define BIT_SHIFT_MU_DBG_INFO 0 +#define BIT_MASK_MU_DBG_INFO 0xffffffffL +#define BIT_MU_DBG_INFO(x) \ + (((x) & BIT_MASK_MU_DBG_INFO) << BIT_SHIFT_MU_DBG_INFO) +#define BITS_MU_DBG_INFO (BIT_MASK_MU_DBG_INFO << BIT_SHIFT_MU_DBG_INFO) +#define BIT_CLEAR_MU_DBG_INFO(x) ((x) & (~BITS_MU_DBG_INFO)) +#define BIT_GET_MU_DBG_INFO(x) \ + (((x) >> BIT_SHIFT_MU_DBG_INFO) & BIT_MASK_MU_DBG_INFO) +#define BIT_SET_MU_DBG_INFO(x, v) \ + (BIT_CLEAR_MU_DBG_INFO(x) | BIT_MU_DBG_INFO(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_NOA_PARAM_2 (Offset 0x05E8) */ +#define BIT_SHIFT_NOA_START_TIME_V1 0 +#define BIT_MASK_NOA_START_TIME_V1 0xffffffffL +#define BIT_NOA_START_TIME_V1(x) \ + (((x) & BIT_MASK_NOA_START_TIME_V1) << BIT_SHIFT_NOA_START_TIME_V1) +#define BITS_NOA_START_TIME_V1 \ + (BIT_MASK_NOA_START_TIME_V1 << BIT_SHIFT_NOA_START_TIME_V1) +#define BIT_CLEAR_NOA_START_TIME_V1(x) ((x) & (~BITS_NOA_START_TIME_V1)) +#define BIT_GET_NOA_START_TIME_V1(x) \ + (((x) >> BIT_SHIFT_NOA_START_TIME_V1) & BIT_MASK_NOA_START_TIME_V1) +#define BIT_SET_NOA_START_TIME_V1(x, v) \ + (BIT_CLEAR_NOA_START_TIME_V1(x) | BIT_NOA_START_TIME_V1(v)) -/* 2 REG_NOA_PARAM (Offset 0x05E0) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_NOA_DURATION_V1 0 -#define BIT_MASK_NOA_DURATION_V1 0xffffffffL -#define BIT_NOA_DURATION_V1(x) (((x) & BIT_MASK_NOA_DURATION_V1) << BIT_SHIFT_NOA_DURATION_V1) -#define BIT_GET_NOA_DURATION_V1(x) (((x) >> BIT_SHIFT_NOA_DURATION_V1) & BIT_MASK_NOA_DURATION_V1) +/* 2 REG_MU_DBG_INFO_1 (Offset 0x05EC) */ +#define BIT_SHIFT_MU_DBG_INFO_1 0 +#define BIT_MASK_MU_DBG_INFO_1 0xffffffffL +#define BIT_MU_DBG_INFO_1(x) \ + (((x) & BIT_MASK_MU_DBG_INFO_1) << BIT_SHIFT_MU_DBG_INFO_1) +#define BITS_MU_DBG_INFO_1 (BIT_MASK_MU_DBG_INFO_1 << BIT_SHIFT_MU_DBG_INFO_1) +#define BIT_CLEAR_MU_DBG_INFO_1(x) ((x) & (~BITS_MU_DBG_INFO_1)) +#define BIT_GET_MU_DBG_INFO_1(x) \ + (((x) >> BIT_SHIFT_MU_DBG_INFO_1) & BIT_MASK_MU_DBG_INFO_1) +#define BIT_SET_MU_DBG_INFO_1(x, v) \ + (BIT_CLEAR_MU_DBG_INFO_1(x) | BIT_MU_DBG_INFO_1(v)) -/* 2 REG_NOA_PARAM_1 (Offset 0x05E4) */ +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NOA_INTERVAL_V1 0 -#define BIT_MASK_NOA_INTERVAL_V1 0xffffffffL -#define BIT_NOA_INTERVAL_V1(x) (((x) & BIT_MASK_NOA_INTERVAL_V1) << BIT_SHIFT_NOA_INTERVAL_V1) -#define BIT_GET_NOA_INTERVAL_V1(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_V1) & BIT_MASK_NOA_INTERVAL_V1) +/* 2 REG_NOA_PARAM_3 (Offset 0x05EC) */ +#define BIT_SHIFT_NOA_COUNT_V1 0 +#define BIT_MASK_NOA_COUNT_V1 0xffffffffL +#define BIT_NOA_COUNT_V1(x) \ + (((x) & BIT_MASK_NOA_COUNT_V1) << BIT_SHIFT_NOA_COUNT_V1) +#define BITS_NOA_COUNT_V1 (BIT_MASK_NOA_COUNT_V1 << BIT_SHIFT_NOA_COUNT_V1) +#define BIT_CLEAR_NOA_COUNT_V1(x) ((x) & (~BITS_NOA_COUNT_V1)) +#define BIT_GET_NOA_COUNT_V1(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_V1) & BIT_MASK_NOA_COUNT_V1) +#define BIT_SET_NOA_COUNT_V1(x, v) \ + (BIT_CLEAR_NOA_COUNT_V1(x) | BIT_NOA_COUNT_V1(v)) -/* 2 REG_NOA_PARAM_2 (Offset 0x05E8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NOA_START_TIME_V1 0 -#define BIT_MASK_NOA_START_TIME_V1 0xffffffffL -#define BIT_NOA_START_TIME_V1(x) (((x) & BIT_MASK_NOA_START_TIME_V1) << BIT_SHIFT_NOA_START_TIME_V1) -#define BIT_GET_NOA_START_TIME_V1(x) (((x) >> BIT_SHIFT_NOA_START_TIME_V1) & BIT_MASK_NOA_START_TIME_V1) +/* 2 REG_NOA_SUBIE (Offset 0x05ED) */ +#define BIT_MORE_NOA_DESC BIT(19) +#define BIT_NOA_DESC1_VALID BIT(18) +#define BIT_NOA_DESC0_VALID BIT(17) +#define BIT_NOA_HEAD_VALID BIT(16) +#define BIT_NOA_OPP_PS BIT(15) -/* 2 REG_NOA_PARAM_3 (Offset 0x05EC) */ +#define BIT_SHIFT_NOA_CTW 8 +#define BIT_MASK_NOA_CTW 0x7f +#define BIT_NOA_CTW(x) (((x) & BIT_MASK_NOA_CTW) << BIT_SHIFT_NOA_CTW) +#define BITS_NOA_CTW (BIT_MASK_NOA_CTW << BIT_SHIFT_NOA_CTW) +#define BIT_CLEAR_NOA_CTW(x) ((x) & (~BITS_NOA_CTW)) +#define BIT_GET_NOA_CTW(x) (((x) >> BIT_SHIFT_NOA_CTW) & BIT_MASK_NOA_CTW) +#define BIT_SET_NOA_CTW(x, v) (BIT_CLEAR_NOA_CTW(x) | BIT_NOA_CTW(v)) +#define BIT_SHIFT_NOA_INDEX 0 +#define BIT_MASK_NOA_INDEX 0xff +#define BIT_NOA_INDEX(x) (((x) & BIT_MASK_NOA_INDEX) << BIT_SHIFT_NOA_INDEX) +#define BITS_NOA_INDEX (BIT_MASK_NOA_INDEX << BIT_SHIFT_NOA_INDEX) +#define BIT_CLEAR_NOA_INDEX(x) ((x) & (~BITS_NOA_INDEX)) +#define BIT_GET_NOA_INDEX(x) (((x) >> BIT_SHIFT_NOA_INDEX) & BIT_MASK_NOA_INDEX) +#define BIT_SET_NOA_INDEX(x, v) (BIT_CLEAR_NOA_INDEX(x) | BIT_NOA_INDEX(v)) -#define BIT_SHIFT_NOA_COUNT_V1 0 -#define BIT_MASK_NOA_COUNT_V1 0xffffffffL -#define BIT_NOA_COUNT_V1(x) (((x) & BIT_MASK_NOA_COUNT_V1) << BIT_SHIFT_NOA_COUNT_V1) -#define BIT_GET_NOA_COUNT_V1(x) (((x) >> BIT_SHIFT_NOA_COUNT_V1) & BIT_MASK_NOA_COUNT_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_P2P_RST (Offset 0x05F0) */ +#define BIT_P2P2_PWR_RST1 BIT(5) +#define BIT_P2P2_PWR_RST0 BIT(4) +#define BIT_P2P1_PWR_RST1 BIT(3) +#define BIT_P2P1_PWR_RST0 BIT(2) +#define BIT_P2P_PWR_RST1_V1 BIT(1) +#define BIT_P2P_PWR_RST0_V1 BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_NOA_SUBIE (Offset 0x05ED) */ +/* 2 REG_SCH_DBG_SEL (Offset 0x05F0) */ -#define BIT_MORE_NOA_DESC BIT(19) -#define BIT_NOA_DESC1_VALID BIT(18) -#define BIT_NOA_DESC0_VALID BIT(17) -#define BIT_NOA_HEAD_VALID BIT(16) -#define BIT_NOA_OPP_PS BIT(15) +#define BIT_SHIFT_SCH_DBG_SEL 0 +#define BIT_MASK_SCH_DBG_SEL 0xff +#define BIT_SCH_DBG_SEL(x) \ + (((x) & BIT_MASK_SCH_DBG_SEL) << BIT_SHIFT_SCH_DBG_SEL) +#define BITS_SCH_DBG_SEL (BIT_MASK_SCH_DBG_SEL << BIT_SHIFT_SCH_DBG_SEL) +#define BIT_CLEAR_SCH_DBG_SEL(x) ((x) & (~BITS_SCH_DBG_SEL)) +#define BIT_GET_SCH_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_SCH_DBG_SEL) & BIT_MASK_SCH_DBG_SEL) +#define BIT_SET_SCH_DBG_SEL(x, v) \ + (BIT_CLEAR_SCH_DBG_SEL(x) | BIT_SCH_DBG_SEL(v)) -#define BIT_SHIFT_NOA_CTW 8 -#define BIT_MASK_NOA_CTW 0x7f -#define BIT_NOA_CTW(x) (((x) & BIT_MASK_NOA_CTW) << BIT_SHIFT_NOA_CTW) -#define BIT_GET_NOA_CTW(x) (((x) >> BIT_SHIFT_NOA_CTW) & BIT_MASK_NOA_CTW) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NOA_INDEX 0 -#define BIT_MASK_NOA_INDEX 0xff -#define BIT_NOA_INDEX(x) (((x) & BIT_MASK_NOA_INDEX) << BIT_SHIFT_NOA_INDEX) -#define BIT_GET_NOA_INDEX(x) (((x) >> BIT_SHIFT_NOA_INDEX) & BIT_MASK_NOA_INDEX) +/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +#define BIT_MAC_STOP_CPUMGQ BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +#define BIT_SYNC_TSF_NOW BIT(2) -/* 2 REG_P2P_RST (Offset 0x05F0) */ +#endif -#define BIT_P2P2_PWR_RST1 BIT(5) -#define BIT_P2P2_PWR_RST0 BIT(4) -#define BIT_P2P1_PWR_RST1 BIT(3) -#define BIT_P2P1_PWR_RST0 BIT(2) -#define BIT_P2P_PWR_RST1_V1 BIT(1) -#define BIT_P2P_PWR_RST0_V1 BIT(0) +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +#define BIT_SYNC_CLI_ONCE_RIGHT_NOW BIT(2) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) /* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ -#define BIT_STOP_CPUMGQ BIT(16) -#define BIT_SYNC_TSF_NOW BIT(2) +#define BIT_SYNC_CLI BIT(1) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ + +#define BIT_SYNC_CLI_ONCE_BY_TBTT BIT(1) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ -#define BIT_SYNC_CLI BIT(1) -#define BIT_SCHEDULER_RST_V1 BIT(0) +#define BIT_SCHEDULER_RST_V1 BIT(0) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_MU_DBG_ERR_FLAG (Offset 0x05F2) */ +#define BIT_BCN_PORTID_ERR BIT(2) -/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +#define BIT_SHIFT_MU_DBG_ERR_FLAG 0 +#define BIT_MASK_MU_DBG_ERR_FLAG 0x3 +#define BIT_MU_DBG_ERR_FLAG(x) \ + (((x) & BIT_MASK_MU_DBG_ERR_FLAG) << BIT_SHIFT_MU_DBG_ERR_FLAG) +#define BITS_MU_DBG_ERR_FLAG \ + (BIT_MASK_MU_DBG_ERR_FLAG << BIT_SHIFT_MU_DBG_ERR_FLAG) +#define BIT_CLEAR_MU_DBG_ERR_FLAG(x) ((x) & (~BITS_MU_DBG_ERR_FLAG)) +#define BIT_GET_MU_DBG_ERR_FLAG(x) \ + (((x) >> BIT_SHIFT_MU_DBG_ERR_FLAG) & BIT_MASK_MU_DBG_ERR_FLAG) +#define BIT_SET_MU_DBG_ERR_FLAG(x, v) \ + (BIT_CLEAR_MU_DBG_ERR_FLAG(x) | BIT_MU_DBG_ERR_FLAG(v)) +/* 2 REG_TX_ERR_RECOVERY_RST (Offset 0x05F3) */ -#define BIT_SHIFT_CPUMGQ_PARAMETER 0 -#define BIT_MASK_CPUMGQ_PARAMETER 0xffff -#define BIT_CPUMGQ_PARAMETER(x) (((x) & BIT_MASK_CPUMGQ_PARAMETER) << BIT_SHIFT_CPUMGQ_PARAMETER) -#define BIT_GET_CPUMGQ_PARAMETER(x) (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER) & BIT_MASK_CPUMGQ_PARAMETER) +#define BIT_SHIFT_ERR_RECOVER_CNT 4 +#define BIT_MASK_ERR_RECOVER_CNT 0xf +#define BIT_ERR_RECOVER_CNT(x) \ + (((x) & BIT_MASK_ERR_RECOVER_CNT) << BIT_SHIFT_ERR_RECOVER_CNT) +#define BITS_ERR_RECOVER_CNT \ + (BIT_MASK_ERR_RECOVER_CNT << BIT_SHIFT_ERR_RECOVER_CNT) +#define BIT_CLEAR_ERR_RECOVER_CNT(x) ((x) & (~BITS_ERR_RECOVER_CNT)) +#define BIT_GET_ERR_RECOVER_CNT(x) \ + (((x) >> BIT_SHIFT_ERR_RECOVER_CNT) & BIT_MASK_ERR_RECOVER_CNT) +#define BIT_SET_ERR_RECOVER_CNT(x, v) \ + (BIT_CLEAR_ERR_RECOVER_CNT(x) | BIT_ERR_RECOVER_CNT(v)) +#define BIT_RX_HANG_ERR BIT(2) +#define BIT_TX_HANG_ERR BIT(1) +#define BIT_TX_ERR_RECOVERY_RST BIT(0) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SCH_DBG_VALUE (Offset 0x05F4) */ +#define BIT_SHIFT_SCH_DBG_VALUE 0 +#define BIT_MASK_SCH_DBG_VALUE 0xffffffffL +#define BIT_SCH_DBG_VALUE(x) \ + (((x) & BIT_MASK_SCH_DBG_VALUE) << BIT_SHIFT_SCH_DBG_VALUE) +#define BITS_SCH_DBG_VALUE (BIT_MASK_SCH_DBG_VALUE << BIT_SHIFT_SCH_DBG_VALUE) +#define BIT_CLEAR_SCH_DBG_VALUE(x) ((x) & (~BITS_SCH_DBG_VALUE)) +#define BIT_GET_SCH_DBG_VALUE(x) \ + (((x) >> BIT_SHIFT_SCH_DBG_VALUE) & BIT_MASK_SCH_DBG_VALUE) +#define BIT_SET_SCH_DBG_VALUE(x, v) \ + (BIT_CLEAR_SCH_DBG_VALUE(x) | BIT_SCH_DBG_VALUE(v)) -/* 2 REG_SCH_TXCMD (Offset 0x05F8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SCH_TXCMD 0 -#define BIT_MASK_SCH_TXCMD 0xffffffffL -#define BIT_SCH_TXCMD(x) (((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD) -#define BIT_GET_SCH_TXCMD(x) (((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD) +/* 2 REG_SCH_TXCMD (Offset 0x05F8) */ +#define BIT_SHIFT_SCH_TXCMD 0 +#define BIT_MASK_SCH_TXCMD 0xffffffffL +#define BIT_SCH_TXCMD(x) (((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD) +#define BITS_SCH_TXCMD (BIT_MASK_SCH_TXCMD << BIT_SHIFT_SCH_TXCMD) +#define BIT_CLEAR_SCH_TXCMD(x) ((x) & (~BITS_SCH_TXCMD)) +#define BIT_GET_SCH_TXCMD(x) (((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD) +#define BIT_SET_SCH_TXCMD(x, v) (BIT_CLEAR_SCH_TXCMD(x) | BIT_SCH_TXCMD(v)) #endif +#if (HALMAC_8821C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_PAGE5_DUMMY (Offset 0x05FC) */ +#define BIT_ECO_TXOP_BREAK_FORCE_CFEND BIT(0) -/* 2 REG_WMAC_CR (Offset 0x0600) */ +#endif -#define BIT_APSDOFF_STATUS BIT(7) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_WMAC_CR (Offset 0x0600) */ +#define BIT_APSDOFF_STATUS BIT(7) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) /* 2 REG_WMAC_CR (Offset 0x0600) */ -#define BIT_APSDOFF BIT(6) +#define BIT_APSDOFF BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WMAC_CR (Offset 0x0600) */ -#define BIT_STANDBY_STATUS BIT(5) +#define BIT_STANDBY_STATUS BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_CR (Offset 0x0600) */ -#define BIT_IC_MACPHY_M BIT(0) +#define BIT_IC_MACPHY_M BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ -#define BIT_FWEN BIT(7) +#define BIT_FWEN BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ -#define BIT_PHYSTS_PKT_CTRL BIT(6) +#define BIT_FWRX_EN BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ +#define BIT_PHYSTS_PKT_CTRL BIT(6) -/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ +#endif -#define BIT_APPHDR_MIDSRCH_FAIL BIT(4) -#define BIT_FWPARSING_EN BIT(3) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) -#define BIT_SHIFT_APPEND_MHDR_LEN 0 -#define BIT_MASK_APPEND_MHDR_LEN 0x7 -#define BIT_APPEND_MHDR_LEN(x) (((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN) -#define BIT_GET_APPEND_MHDR_LEN(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN) +/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ +#define BIT_FWFULL_TO_RXFF_EN BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - +/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ -/* 2 REG_FW_STS_FILTER (Offset 0x0602) */ +#define BIT_APPHDR_MIDSRCH_FAIL BIT(4) +#define BIT_FWPARSING_EN BIT(3) -#define BIT_DATA_FW_STS_FILTER BIT(2) -#define BIT_CTRL_FW_STS_FILTER BIT(1) -#define BIT_MGNT_FW_STS_FILTER BIT(0) +#define BIT_SHIFT_APPEND_MHDR_LEN 0 +#define BIT_MASK_APPEND_MHDR_LEN 0x7 +#define BIT_APPEND_MHDR_LEN(x) \ + (((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN) +#define BITS_APPEND_MHDR_LEN \ + (BIT_MASK_APPEND_MHDR_LEN << BIT_SHIFT_APPEND_MHDR_LEN) +#define BIT_CLEAR_APPEND_MHDR_LEN(x) ((x) & (~BITS_APPEND_MHDR_LEN)) +#define BIT_GET_APPEND_MHDR_LEN(x) \ + (((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN) +#define BIT_SET_APPEND_MHDR_LEN(x, v) \ + (BIT_CLEAR_APPEND_MHDR_LEN(x) | BIT_APPEND_MHDR_LEN(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BWOPMODE (Offset 0x0603) */ +#define BIT_WMAC_20MHZBW BIT(2) +#define BIT_WMAC_M11J BIT(0) -/* 2 REG_TCR (Offset 0x0604) */ +#endif -#define BIT_WMAC_EN_RTS_ADDR BIT(31) -#define BIT_WMAC_DISABLE_CCK BIT(30) -#define BIT_WMAC_RAW_LEN BIT(29) -#define BIT_WMAC_NOTX_IN_RXNDP BIT(28) -#define BIT_WMAC_EN_EOF BIT(27) -#define BIT_WMAC_BF_SEL BIT(26) -#define BIT_WMAC_ANTMODE_SEL BIT(25) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_EN_RTS_ADDR BIT(31) +#define BIT_WMAC_DISABLE_CCK BIT(30) +#define BIT_WMAC_RAW_LEN BIT(29) +#define BIT_WMAC_NOTX_IN_RXNDP BIT(28) +#define BIT_WMAC_EN_EOF BIT(27) +#define BIT_WMAC_BF_SEL BIT(26) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ -#define BIT_WMAC_TCRPWRMGT_HWCTL BIT(24) +#define BIT_WMAC_ANTMODE_SEL BIT(25) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ + +#define BIT_WMAC_TCRPWRMGT_HWCTL BIT(24) + +#endif +#if (HALMAC_8814A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ -#define BIT_RXLEN_SEL BIT(24) +#define BIT_RXLEN_SEL BIT(24) #endif +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_TCR (Offset 0x0604) */ + +#define BIT_WMAC_TCRPWRMGT_HWCTL_EN BIT(24) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ -#define BIT_WMAC_SMOOTH_VAL BIT(23) +#define BIT_WMAC_SMOOTH_VAL BIT(23) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_EN_SCRAM_INC BIT(22) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ -#define BIT_UNDERFLOWEN_CMPLEN_SEL BIT(21) +#define BIT_UNDERFLOWEN_CMPLEN_SEL BIT(21) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_TCR (Offset 0x0604) */ +#define BIT_SHIFT_TSFT_CMP 20 +#define BIT_MASK_TSFT_CMP 0xf +#define BIT_TSFT_CMP(x) (((x) & BIT_MASK_TSFT_CMP) << BIT_SHIFT_TSFT_CMP) +#define BITS_TSFT_CMP (BIT_MASK_TSFT_CMP << BIT_SHIFT_TSFT_CMP) +#define BIT_CLEAR_TSFT_CMP(x) ((x) & (~BITS_TSFT_CMP)) +#define BIT_GET_TSFT_CMP(x) (((x) >> BIT_SHIFT_TSFT_CMP) & BIT_MASK_TSFT_CMP) +#define BIT_SET_TSFT_CMP(x, v) (BIT_CLEAR_TSFT_CMP(x) | BIT_TSFT_CMP(v)) -#define BIT_SHIFT_TSFT_CMP 20 -#define BIT_MASK_TSFT_CMP 0xf -#define BIT_TSFT_CMP(x) (((x) & BIT_MASK_TSFT_CMP) << BIT_SHIFT_TSFT_CMP) -#define BIT_GET_TSFT_CMP(x) (((x) >> BIT_SHIFT_TSFT_CMP) & BIT_MASK_TSFT_CMP) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_FETCH_MPDU_AFTER_WSEC_RDY BIT(20) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ -#define BIT_FETCH_MPDU_AFTER_WSEC_RDY BIT(20) +#define BIT_WMAC_TCR_EN_20MST BIT(19) +#define BIT_WMAC_DIS_SIGTA BIT(18) +#define BIT_WMAC_DIS_A2B0 BIT(17) +#define BIT_WMAC_MSK_SIGBCRC BIT(16) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_TCR (Offset 0x0604) */ + +#define BIT_WMAC_TCR_ERRSTEN_3 BIT(15) +#define BIT_WMAC_TCR_ERRSTEN_2 BIT(14) +#define BIT_WMAC_TCR_ERRSTEN_1 BIT(13) +#define BIT_WMAC_TCR_ERRSTEN_0 BIT(12) +#define BIT_WMAC_TCR_TXSK_PERPKT BIT(11) +#define BIT_ICV BIT(10) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ -#define BIT_WMAC_TCR_EN_20MST BIT(19) -#define BIT_WMAC_DIS_SIGTA BIT(18) -#define BIT_WMAC_DIS_A2B0 BIT(17) -#define BIT_WMAC_MSK_SIGBCRC BIT(16) +#define BIT_CFEND_FORMAT BIT(9) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_TCR (Offset 0x0604) */ + +#define BIT_CRC BIT(8) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ -#define BIT_WMAC_TCR_ERRSTEN_3 BIT(15) -#define BIT_WMAC_TCR_ERRSTEN_2 BIT(14) -#define BIT_WMAC_TCR_ERRSTEN_1 BIT(13) -#define BIT_WMAC_TCR_ERRSTEN_0 BIT(12) -#define BIT_WMAC_TCR_TXSK_PERPKT BIT(11) -#define BIT_ICV BIT(10) -#define BIT_CFEND_FORMAT BIT(9) -#define BIT_CRC BIT(8) -#define BIT_PWRBIT_OW_EN BIT(7) -#define BIT_PWR_ST BIT(6) -#define BIT_WMAC_TCR_UPD_TIMIE BIT(5) -#define BIT_WMAC_TCR_UPD_HGQMD BIT(4) +#define BIT_PWRBIT_OW_EN BIT(7) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_TCR (Offset 0x0604) */ + +#define BIT_WMAC_TCRPWRMGT_HWDATA_EN BIT(7) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ -#define BIT_VHTSIGA1_TXPS BIT(3) +#define BIT_PWR_ST BIT(6) +#define BIT_WMAC_TCR_UPD_TIMIE BIT(5) +#define BIT_WMAC_TCR_UPD_HGQMD BIT(4) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_TCR (Offset 0x0604) */ + +#define BIT_VHTSIGA1_TXPS BIT(3) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ -#define BIT_PAD_SEL BIT(2) -#define BIT_DIS_GCLK BIT(1) +#define BIT_PAD_SEL BIT(2) +#define BIT_DIS_GCLK BIT(1) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_TCR (Offset 0x0604) */ -#define BIT_TSFRST BIT(0) +#define BIT_TSFRST BIT(0) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_TCR (Offset 0x0604) */ -#define BIT_R_WMAC_TCR_LSIG BIT(0) +#define BIT_R_WMAC_TCR_LSIG BIT(0) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_TCRPWRMGT_HWACT_EN BIT(0) -/* 2 REG_RCR (Offset 0x0608) */ +#endif -#define BIT_APP_FCS BIT(31) -#define BIT_APP_MIC BIT(30) -#define BIT_APP_ICV BIT(29) -#define BIT_APP_PHYSTS BIT(28) -#define BIT_APP_BASSN BIT(27) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_APP_FCS BIT(31) +#define BIT_APP_MIC BIT(30) +#define BIT_APP_ICV BIT(29) +#define BIT_APP_PHYSTS BIT(28) +#define BIT_APP_BASSN BIT(27) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ -#define BIT_VHT_DACK BIT(26) +#define BIT_VHT_DACK BIT(26) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_RCR (Offset 0x0608) */ + +#define BIT_TCPOFLD_EN BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ -#define BIT_TCPOFLD_EN BIT(25) -#define BIT_ENMBID BIT(24) -#define BIT_LSIGEN BIT(23) -#define BIT_MFBEN BIT(22) -#define BIT_DISCHKPPDLLEN BIT(21) -#define BIT_PKTCTL_DLEN BIT(20) -#define BIT_TIM_PARSER_EN BIT(18) -#define BIT_BC_MD_EN BIT(17) -#define BIT_UC_MD_EN BIT(16) -#define BIT_RXSK_PERPKT BIT(15) -#define BIT_HTC_LOC_CTRL BIT(14) +#define BIT_ENMBID BIT(24) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RCR (Offset 0x0608) */ + +#define BIT_ENADDRCAM BIT(24) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ -#define BIT_AMF BIT(13) -#define BIT_ACF BIT(12) +#define BIT_LSIGEN BIT(23) +#define BIT_MFBEN BIT(22) +#define BIT_DISCHKPPDLLEN BIT(21) +#define BIT_PKTCTL_DLEN BIT(20) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RCR (Offset 0x0608) */ + +#define BIT_DISGCLK BIT(19) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ -#define BIT_RPFM_CAM_ENABLE BIT(12) +#define BIT_TIM_PARSER_EN BIT(18) +#define BIT_BC_MD_EN BIT(17) +#define BIT_UC_MD_EN BIT(16) +#define BIT_RXSK_PERPKT BIT(15) +#define BIT_HTC_LOC_CTRL BIT(14) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_RCR (Offset 0x0608) */ -#define BIT_ADF BIT(11) +#define BIT_AMF BIT(13) #endif +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_RCR (Offset 0x0608) */ + +#define BIT_CHK_PREVTCA2 BIT(13) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ -#define BIT_TA_BCN BIT(11) +#define BIT_ACK_WITH_CBSSID_DATA_OPTION BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_RCR (Offset 0x0608) */ + +#define BIT_ACF BIT(12) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ -#define BIT_DISDECMYPKT BIT(10) -#define BIT_AICV BIT(9) -#define BIT_ACRC32 BIT(8) -#define BIT_CBSSID_BCN BIT(7) -#define BIT_CBSSID_DATA BIT(6) -#define BIT_APWRMGT BIT(5) -#define BIT_ADD3 BIT(4) -#define BIT_AB BIT(3) -#define BIT_AM BIT(2) -#define BIT_APM BIT(1) -#define BIT_AAP BIT(0) +#define BIT_RPFM_CAM_ENABLE BIT(12) -/* 2 REG_RX_PKT_LIMIT (Offset 0x060C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RXPKTLMT 0 -#define BIT_MASK_RXPKTLMT 0x3f -#define BIT_RXPKTLMT(x) (((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT) -#define BIT_GET_RXPKTLMT(x) (((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_ADF BIT(11) -/* 2 REG_RX_DLK_TIME (Offset 0x060D) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RX_DLK_TIME 0 -#define BIT_MASK_RX_DLK_TIME 0xff -#define BIT_RX_DLK_TIME(x) (((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME) -#define BIT_GET_RX_DLK_TIME(x) (((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_TA_BCN BIT(11) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_DISDECMYPKT BIT(10) +#define BIT_AICV BIT(9) +#define BIT_ACRC32 BIT(8) +#define BIT_CBSSID_BCN BIT(7) +#define BIT_CBSSID_DATA BIT(6) +#define BIT_APWRMGT BIT(5) +#define BIT_ADD3 BIT(4) +#define BIT_AB BIT(3) +#define BIT_AM BIT(2) +#define BIT_APM BIT(1) +#define BIT_AAP BIT(0) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +/* 2 REG_RX_PKT_LIMIT (Offset 0x060C) */ -#define BIT_DATA_RPFM15EN BIT(15) -#define BIT_DATA_RPFM14EN BIT(14) -#define BIT_DATA_RPFM13EN BIT(13) -#define BIT_DATA_RPFM12EN BIT(12) -#define BIT_DATA_RPFM11EN BIT(11) -#define BIT_DATA_RPFM10EN BIT(10) -#define BIT_DATA_RPFM9EN BIT(9) -#define BIT_DATA_RPFM8EN BIT(8) +#define BIT_SHIFT_RXPKTLMT 0 +#define BIT_MASK_RXPKTLMT 0x3f +#define BIT_RXPKTLMT(x) (((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT) +#define BITS_RXPKTLMT (BIT_MASK_RXPKTLMT << BIT_SHIFT_RXPKTLMT) +#define BIT_CLEAR_RXPKTLMT(x) ((x) & (~BITS_RXPKTLMT)) +#define BIT_GET_RXPKTLMT(x) (((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT) +#define BIT_SET_RXPKTLMT(x, v) (BIT_CLEAR_RXPKTLMT(x) | BIT_RXPKTLMT(v)) -#endif +/* 2 REG_RX_DLK_TIME (Offset 0x060D) */ +#define BIT_SHIFT_RX_DLK_TIME 0 +#define BIT_MASK_RX_DLK_TIME 0xff +#define BIT_RX_DLK_TIME(x) \ + (((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME) +#define BITS_RX_DLK_TIME (BIT_MASK_RX_DLK_TIME << BIT_SHIFT_RX_DLK_TIME) +#define BIT_CLEAR_RX_DLK_TIME(x) ((x) & (~BITS_RX_DLK_TIME)) +#define BIT_GET_RX_DLK_TIME(x) \ + (((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME) +#define BIT_SET_RX_DLK_TIME(x, v) \ + (BIT_CLEAR_RX_DLK_TIME(x) | BIT_RX_DLK_TIME(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ -#define BIT_APP_PHYSTS_PER_SUBMPDU BIT(7) +#define BIT_APP_PHYSTS_PER_SUBMPDU BIT(7) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ -#define BIT_PHYSTS_PER_PKT_MODE BIT(7) -#define BIT_DATA_RPFM7EN BIT(7) +#define BIT_PHYSTS_PER_PKT_MODE BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ -#define BIT_APP_MH_SHIFT_VAL BIT(6) +#define BIT_APP_MH_SHIFT_VAL BIT(6) +#define BIT_WMAC_ENSHIFT BIT(5) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ -#define BIT_DATA_RPFM6EN BIT(6) +#define BIT_SHIFT_DRVINFO_SZ 0 +#define BIT_MASK_DRVINFO_SZ 0xff +#define BIT_DRVINFO_SZ(x) (((x) & BIT_MASK_DRVINFO_SZ) << BIT_SHIFT_DRVINFO_SZ) +#define BITS_DRVINFO_SZ (BIT_MASK_DRVINFO_SZ << BIT_SHIFT_DRVINFO_SZ) +#define BIT_CLEAR_DRVINFO_SZ(x) ((x) & (~BITS_DRVINFO_SZ)) +#define BIT_GET_DRVINFO_SZ(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ) & BIT_MASK_DRVINFO_SZ) +#define BIT_SET_DRVINFO_SZ(x, v) (BIT_CLEAR_DRVINFO_SZ(x) | BIT_DRVINFO_SZ(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ -#define BIT_WMAC_ENSHIFT BIT(5) +#define BIT_SHIFT_DRVINFO_SZ_V1 0 +#define BIT_MASK_DRVINFO_SZ_V1 0xf +#define BIT_DRVINFO_SZ_V1(x) \ + (((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1) +#define BITS_DRVINFO_SZ_V1 (BIT_MASK_DRVINFO_SZ_V1 << BIT_SHIFT_DRVINFO_SZ_V1) +#define BIT_CLEAR_DRVINFO_SZ_V1(x) ((x) & (~BITS_DRVINFO_SZ_V1)) +#define BIT_GET_DRVINFO_SZ_V1(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1) +#define BIT_SET_DRVINFO_SZ_V1(x, v) \ + (BIT_CLEAR_DRVINFO_SZ_V1(x) | BIT_DRVINFO_SZ_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MACID (Offset 0x0610) */ +#define BIT_SHIFT_MACID 0 +#define BIT_MASK_MACID 0xffffffffffffL +#define BIT_MACID(x) (((x) & BIT_MASK_MACID) << BIT_SHIFT_MACID) +#define BITS_MACID (BIT_MASK_MACID << BIT_SHIFT_MACID) +#define BIT_CLEAR_MACID(x) ((x) & (~BITS_MACID)) +#define BIT_GET_MACID(x) (((x) >> BIT_SHIFT_MACID) & BIT_MASK_MACID) +#define BIT_SET_MACID(x, v) (BIT_CLEAR_MACID(x) | BIT_MACID(v)) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#endif -#define BIT_DATA_RPFM5EN BIT(5) -#define BIT_DATA_RPFM4EN BIT(4) -#define BIT_DATA_RPFM3EN BIT(3) -#define BIT_DATA_RPFM2EN BIT(2) -#define BIT_DATA_RPFM1EN BIT(1) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MACID (Offset 0x0610) */ +#define BIT_SHIFT_MACID_V1 0 +#define BIT_MASK_MACID_V1 0xffffffffL +#define BIT_MACID_V1(x) (((x) & BIT_MASK_MACID_V1) << BIT_SHIFT_MACID_V1) +#define BITS_MACID_V1 (BIT_MASK_MACID_V1 << BIT_SHIFT_MACID_V1) +#define BIT_CLEAR_MACID_V1(x) ((x) & (~BITS_MACID_V1)) +#define BIT_GET_MACID_V1(x) (((x) >> BIT_SHIFT_MACID_V1) & BIT_MASK_MACID_V1) +#define BIT_SET_MACID_V1(x, v) (BIT_CLEAR_MACID_V1(x) | BIT_MACID_V1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MACID_H (Offset 0x0614) */ +#define BIT_SHIFT_MACID_H_V1 0 +#define BIT_MASK_MACID_H_V1 0xffff +#define BIT_MACID_H_V1(x) (((x) & BIT_MASK_MACID_H_V1) << BIT_SHIFT_MACID_H_V1) +#define BITS_MACID_H_V1 (BIT_MASK_MACID_H_V1 << BIT_SHIFT_MACID_H_V1) +#define BIT_CLEAR_MACID_H_V1(x) ((x) & (~BITS_MACID_H_V1)) +#define BIT_GET_MACID_H_V1(x) \ + (((x) >> BIT_SHIFT_MACID_H_V1) & BIT_MASK_MACID_H_V1) +#define BIT_SET_MACID_H_V1(x, v) (BIT_CLEAR_MACID_H_V1(x) | BIT_MACID_H_V1(v)) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DRVINFO_SZ 0 -#define BIT_MASK_DRVINFO_SZ 0xff -#define BIT_DRVINFO_SZ(x) (((x) & BIT_MASK_DRVINFO_SZ) << BIT_SHIFT_DRVINFO_SZ) -#define BIT_GET_DRVINFO_SZ(x) (((x) >> BIT_SHIFT_DRVINFO_SZ) & BIT_MASK_DRVINFO_SZ) +/* 2 REG_BSSID (Offset 0x0618) */ +#define BIT_SHIFT_BSSID 0 +#define BIT_MASK_BSSID 0xffffffffffffL +#define BIT_BSSID(x) (((x) & BIT_MASK_BSSID) << BIT_SHIFT_BSSID) +#define BITS_BSSID (BIT_MASK_BSSID << BIT_SHIFT_BSSID) +#define BIT_CLEAR_BSSID(x) ((x) & (~BITS_BSSID)) +#define BIT_GET_BSSID(x) (((x) >> BIT_SHIFT_BSSID) & BIT_MASK_BSSID) +#define BIT_SET_BSSID(x, v) (BIT_CLEAR_BSSID(x) | BIT_BSSID(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BSSID (Offset 0x0618) */ +#define BIT_SHIFT_BSSID_V1 0 +#define BIT_MASK_BSSID_V1 0xffffffffL +#define BIT_BSSID_V1(x) (((x) & BIT_MASK_BSSID_V1) << BIT_SHIFT_BSSID_V1) +#define BITS_BSSID_V1 (BIT_MASK_BSSID_V1 << BIT_SHIFT_BSSID_V1) +#define BIT_CLEAR_BSSID_V1(x) ((x) & (~BITS_BSSID_V1)) +#define BIT_GET_BSSID_V1(x) (((x) >> BIT_SHIFT_BSSID_V1) & BIT_MASK_BSSID_V1) +#define BIT_SET_BSSID_V1(x, v) (BIT_CLEAR_BSSID_V1(x) | BIT_BSSID_V1(v)) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#define BIT_SHIFT_BSSID_H_V1 0 +#define BIT_MASK_BSSID_H_V1 0xffff +#define BIT_BSSID_H_V1(x) (((x) & BIT_MASK_BSSID_H_V1) << BIT_SHIFT_BSSID_H_V1) +#define BITS_BSSID_H_V1 (BIT_MASK_BSSID_H_V1 << BIT_SHIFT_BSSID_H_V1) +#define BIT_CLEAR_BSSID_H_V1(x) ((x) & (~BITS_BSSID_H_V1)) +#define BIT_GET_BSSID_H_V1(x) \ + (((x) >> BIT_SHIFT_BSSID_H_V1) & BIT_MASK_BSSID_H_V1) +#define BIT_SET_BSSID_H_V1(x, v) (BIT_CLEAR_BSSID_H_V1(x) | BIT_BSSID_H_V1(v)) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DRVINFO_SZ_V1 0 -#define BIT_MASK_DRVINFO_SZ_V1 0xf -#define BIT_DRVINFO_SZ_V1(x) (((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1) -#define BIT_GET_DRVINFO_SZ_V1(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1) +/* 2 REG_MAR (Offset 0x0620) */ +#define BIT_SHIFT_MAR 0 +#define BIT_MASK_MAR 0xffffffffffffffffL +#define BIT_MAR(x) (((x) & BIT_MASK_MAR) << BIT_SHIFT_MAR) +#define BITS_MAR (BIT_MASK_MAR << BIT_SHIFT_MAR) +#define BIT_CLEAR_MAR(x) ((x) & (~BITS_MAR)) +#define BIT_GET_MAR(x) (((x) >> BIT_SHIFT_MAR) & BIT_MASK_MAR) +#define BIT_SET_MAR(x, v) (BIT_CLEAR_MAR(x) | BIT_MAR(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MAR (Offset 0x0620) */ +#define BIT_SHIFT_MAR_V1 0 +#define BIT_MASK_MAR_V1 0xffffffffL +#define BIT_MAR_V1(x) (((x) & BIT_MASK_MAR_V1) << BIT_SHIFT_MAR_V1) +#define BITS_MAR_V1 (BIT_MASK_MAR_V1 << BIT_SHIFT_MAR_V1) +#define BIT_CLEAR_MAR_V1(x) ((x) & (~BITS_MAR_V1)) +#define BIT_GET_MAR_V1(x) (((x) >> BIT_SHIFT_MAR_V1) & BIT_MASK_MAR_V1) +#define BIT_SET_MAR_V1(x, v) (BIT_CLEAR_MAR_V1(x) | BIT_MAR_V1(v)) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +/* 2 REG_MAR_H (Offset 0x0624) */ -#define BIT_DATA_RPFM0EN BIT(0) +#define BIT_SHIFT_MAR_H_V1 0 +#define BIT_MASK_MAR_H_V1 0xffffffffL +#define BIT_MAR_H_V1(x) (((x) & BIT_MASK_MAR_H_V1) << BIT_SHIFT_MAR_H_V1) +#define BITS_MAR_H_V1 (BIT_MASK_MAR_H_V1 << BIT_SHIFT_MAR_H_V1) +#define BIT_CLEAR_MAR_H_V1(x) ((x) & (~BITS_MAR_H_V1)) +#define BIT_GET_MAR_H_V1(x) (((x) >> BIT_SHIFT_MAR_H_V1) & BIT_MASK_MAR_H_V1) +#define BIT_SET_MAR_H_V1(x, v) (BIT_CLEAR_MAR_H_V1(x) | BIT_MAR_H_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBIDCAMCFG_1 (Offset 0x0628) */ +#define BIT_SHIFT_MBIDCAM_RWDATA_L 0 +#define BIT_MASK_MBIDCAM_RWDATA_L 0xffffffffL +#define BIT_MBIDCAM_RWDATA_L(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_L) << BIT_SHIFT_MBIDCAM_RWDATA_L) +#define BITS_MBIDCAM_RWDATA_L \ + (BIT_MASK_MBIDCAM_RWDATA_L << BIT_SHIFT_MBIDCAM_RWDATA_L) +#define BIT_CLEAR_MBIDCAM_RWDATA_L(x) ((x) & (~BITS_MBIDCAM_RWDATA_L)) +#define BIT_GET_MBIDCAM_RWDATA_L(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L) & BIT_MASK_MBIDCAM_RWDATA_L) +#define BIT_SET_MBIDCAM_RWDATA_L(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_L(x) | BIT_MBIDCAM_RWDATA_L(v)) -/* 2 REG_MACID (Offset 0x0610) */ +/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ +#define BIT_MBIDCAM_POLL BIT(31) +#define BIT_MBIDCAM_WT_EN BIT(30) -#define BIT_SHIFT_MACID 0 -#define BIT_MASK_MACID 0xffffffffffffL -#define BIT_MACID(x) (((x) & BIT_MASK_MACID) << BIT_SHIFT_MACID) -#define BIT_GET_MACID(x) (((x) >> BIT_SHIFT_MACID) & BIT_MASK_MACID) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BSSID (Offset 0x0618) */ +/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ +#define BIT_SHIFT_MBIDCAM_ADDR 24 +#define BIT_MASK_MBIDCAM_ADDR 0x1f +#define BIT_MBIDCAM_ADDR(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR) << BIT_SHIFT_MBIDCAM_ADDR) +#define BITS_MBIDCAM_ADDR (BIT_MASK_MBIDCAM_ADDR << BIT_SHIFT_MBIDCAM_ADDR) +#define BIT_CLEAR_MBIDCAM_ADDR(x) ((x) & (~BITS_MBIDCAM_ADDR)) +#define BIT_GET_MBIDCAM_ADDR(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR) & BIT_MASK_MBIDCAM_ADDR) +#define BIT_SET_MBIDCAM_ADDR(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR(x) | BIT_MBIDCAM_ADDR(v)) -#define BIT_SHIFT_BSSID 0 -#define BIT_MASK_BSSID 0xffffffffffffL -#define BIT_BSSID(x) (((x) & BIT_MASK_BSSID) << BIT_SHIFT_BSSID) -#define BIT_GET_BSSID(x) (((x) >> BIT_SHIFT_BSSID) & BIT_MASK_BSSID) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_MAR (Offset 0x0620) */ +/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ +#define BIT_SHIFT_MBIDCAM_ADDR_V1 24 +#define BIT_MASK_MBIDCAM_ADDR_V1 0x3f +#define BIT_MBIDCAM_ADDR_V1(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR_V1) << BIT_SHIFT_MBIDCAM_ADDR_V1) +#define BITS_MBIDCAM_ADDR_V1 \ + (BIT_MASK_MBIDCAM_ADDR_V1 << BIT_SHIFT_MBIDCAM_ADDR_V1) +#define BIT_CLEAR_MBIDCAM_ADDR_V1(x) ((x) & (~BITS_MBIDCAM_ADDR_V1)) +#define BIT_GET_MBIDCAM_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1) & BIT_MASK_MBIDCAM_ADDR_V1) +#define BIT_SET_MBIDCAM_ADDR_V1(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR_V1(x) | BIT_MBIDCAM_ADDR_V1(v)) -#define BIT_SHIFT_MAR 0 -#define BIT_MASK_MAR 0xffffffffffffffffL -#define BIT_MAR(x) (((x) & BIT_MASK_MAR) << BIT_SHIFT_MAR) -#define BIT_GET_MAR(x) (((x) >> BIT_SHIFT_MAR) & BIT_MASK_MAR) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_MBIDCAMCFG_1 (Offset 0x0628) */ +/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ +#define BIT_MBIDCAM_VALID BIT(23) -#define BIT_SHIFT_MBIDCAM_RWDATA_L 0 -#define BIT_MASK_MBIDCAM_RWDATA_L 0xffffffffL -#define BIT_MBIDCAM_RWDATA_L(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L) << BIT_SHIFT_MBIDCAM_RWDATA_L) -#define BIT_GET_MBIDCAM_RWDATA_L(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L) & BIT_MASK_MBIDCAM_RWDATA_L) +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ -#define BIT_MBIDCAM_POLL BIT(31) -#define BIT_MBIDCAM_WT_EN BIT(30) - -#define BIT_SHIFT_MBIDCAM_ADDR 24 -#define BIT_MASK_MBIDCAM_ADDR 0x1f -#define BIT_MBIDCAM_ADDR(x) (((x) & BIT_MASK_MBIDCAM_ADDR) << BIT_SHIFT_MBIDCAM_ADDR) -#define BIT_GET_MBIDCAM_ADDR(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR) & BIT_MASK_MBIDCAM_ADDR) +#define BIT_SHIFT_MBIDCAM_ADDR_V2 23 +#define BIT_MASK_MBIDCAM_ADDR_V2 0x7f +#define BIT_MBIDCAM_ADDR_V2(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR_V2) << BIT_SHIFT_MBIDCAM_ADDR_V2) +#define BITS_MBIDCAM_ADDR_V2 \ + (BIT_MASK_MBIDCAM_ADDR_V2 << BIT_SHIFT_MBIDCAM_ADDR_V2) +#define BIT_CLEAR_MBIDCAM_ADDR_V2(x) ((x) & (~BITS_MBIDCAM_ADDR_V2)) +#define BIT_GET_MBIDCAM_ADDR_V2(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V2) & BIT_MASK_MBIDCAM_ADDR_V2) +#define BIT_SET_MBIDCAM_ADDR_V2(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR_V2(x) | BIT_MBIDCAM_ADDR_V2(v)) -#define BIT_MBIDCAM_VALID BIT(23) -#define BIT_LSIC_TXOP_EN BIT(17) +#define BIT_MBIDCAM_RST BIT(19) +#define BIT_MBIDCAM_VALID_V1 BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ -#define BIT_CTS_EN BIT(16) +#define BIT_LSIC_TXOP_EN BIT(17) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ -#define BIT_REPEAT_MODE_EN BIT(16) +#define BIT_CTS_EN BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_REPEAT_MODE_EN BIT(16) +#endif -/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_WMAC_DEBUG_SEL (Offset 0x062C) */ -#define BIT_SHIFT_MBIDCAM_RWDATA_H 0 -#define BIT_MASK_MBIDCAM_RWDATA_H 0xffff -#define BIT_MBIDCAM_RWDATA_H(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H) -#define BIT_GET_MBIDCAM_RWDATA_H(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H) +#define BIT_SHIFT_WMAC_ARB_DBG_SEL 3 +#define BIT_MASK_WMAC_ARB_DBG_SEL 0x3 +#define BIT_WMAC_ARB_DBG_SEL(x) \ + (((x) & BIT_MASK_WMAC_ARB_DBG_SEL) << BIT_SHIFT_WMAC_ARB_DBG_SEL) +#define BITS_WMAC_ARB_DBG_SEL \ + (BIT_MASK_WMAC_ARB_DBG_SEL << BIT_SHIFT_WMAC_ARB_DBG_SEL) +#define BIT_CLEAR_WMAC_ARB_DBG_SEL(x) ((x) & (~BITS_WMAC_ARB_DBG_SEL)) +#define BIT_GET_WMAC_ARB_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_ARB_DBG_SEL) & BIT_MASK_WMAC_ARB_DBG_SEL) +#define BIT_SET_WMAC_ARB_DBG_SEL(x, v) \ + (BIT_CLEAR_WMAC_ARB_DBG_SEL(x) | BIT_WMAC_ARB_DBG_SEL(v)) +#define BIT_WMAC_EXT_DBG_SEL BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ +#define BIT_SHIFT_MBIDCAM_RWDATA_H 0 +#define BIT_MASK_MBIDCAM_RWDATA_H 0xffff +#define BIT_MBIDCAM_RWDATA_H(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H) +#define BITS_MBIDCAM_RWDATA_H \ + (BIT_MASK_MBIDCAM_RWDATA_H << BIT_SHIFT_MBIDCAM_RWDATA_H) +#define BIT_CLEAR_MBIDCAM_RWDATA_H(x) ((x) & (~BITS_MBIDCAM_RWDATA_H)) +#define BIT_GET_MBIDCAM_RWDATA_H(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H) +#define BIT_SET_MBIDCAM_RWDATA_H(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_H(x) | BIT_MBIDCAM_RWDATA_H(v)) -/* 2 REG_MCU_TEST_1 (Offset 0x0630) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_MCU_RSVD 0 -#define BIT_MASK_MCU_RSVD 0xffffffffL -#define BIT_MCU_RSVD(x) (((x) & BIT_MASK_MCU_RSVD) << BIT_SHIFT_MCU_RSVD) -#define BIT_GET_MCU_RSVD(x) (((x) >> BIT_SHIFT_MCU_RSVD) & BIT_MASK_MCU_RSVD) +/* 2 REG_WMAC_DEBUG_SEL (Offset 0x062C) */ +#define BIT_SHIFT_WMAC_MU_DBGSEL_V1 0 +#define BIT_MASK_WMAC_MU_DBGSEL_V1 0x3 +#define BIT_WMAC_MU_DBGSEL_V1(x) \ + (((x) & BIT_MASK_WMAC_MU_DBGSEL_V1) << BIT_SHIFT_WMAC_MU_DBGSEL_V1) +#define BITS_WMAC_MU_DBGSEL_V1 \ + (BIT_MASK_WMAC_MU_DBGSEL_V1 << BIT_SHIFT_WMAC_MU_DBGSEL_V1) +#define BIT_CLEAR_WMAC_MU_DBGSEL_V1(x) ((x) & (~BITS_WMAC_MU_DBGSEL_V1)) +#define BIT_GET_WMAC_MU_DBGSEL_V1(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_V1) & BIT_MASK_WMAC_MU_DBGSEL_V1) +#define BIT_SET_WMAC_MU_DBGSEL_V1(x, v) \ + (BIT_CLEAR_WMAC_MU_DBGSEL_V1(x) | BIT_WMAC_MU_DBGSEL_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MCU_TEST_1 (Offset 0x0630) */ +#define BIT_SHIFT_MCU_RSVD 0 +#define BIT_MASK_MCU_RSVD 0xffffffffL +#define BIT_MCU_RSVD(x) (((x) & BIT_MASK_MCU_RSVD) << BIT_SHIFT_MCU_RSVD) +#define BITS_MCU_RSVD (BIT_MASK_MCU_RSVD << BIT_SHIFT_MCU_RSVD) +#define BIT_CLEAR_MCU_RSVD(x) ((x) & (~BITS_MCU_RSVD)) +#define BIT_GET_MCU_RSVD(x) (((x) >> BIT_SHIFT_MCU_RSVD) & BIT_MASK_MCU_RSVD) +#define BIT_SET_MCU_RSVD(x, v) (BIT_CLEAR_MCU_RSVD(x) | BIT_MCU_RSVD(v)) -/* 2 REG_WMAC_TCR_TSFT_OFS (Offset 0x0630) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_TCR_TSFT_OFS 0 -#define BIT_MASK_WMAC_TCR_TSFT_OFS 0xffff -#define BIT_WMAC_TCR_TSFT_OFS(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS) -#define BIT_GET_WMAC_TCR_TSFT_OFS(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS) +/* 2 REG_WMAC_TCR_TSFT_OFS (Offset 0x0630) */ +#define BIT_SHIFT_WMAC_TCR_TSFT_OFS 0 +#define BIT_MASK_WMAC_TCR_TSFT_OFS 0xffff +#define BIT_WMAC_TCR_TSFT_OFS(x) \ + (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS) +#define BITS_WMAC_TCR_TSFT_OFS \ + (BIT_MASK_WMAC_TCR_TSFT_OFS << BIT_SHIFT_WMAC_TCR_TSFT_OFS) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) ((x) & (~BITS_WMAC_TCR_TSFT_OFS)) +#define BIT_GET_WMAC_TCR_TSFT_OFS(x) \ + (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS) +#define BIT_SET_WMAC_TCR_TSFT_OFS(x, v) \ + (BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) | BIT_WMAC_TCR_TSFT_OFS(v)) -/* 2 REG_UDF_THSD (Offset 0x0632) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_UDF_THSD 0 -#define BIT_MASK_UDF_THSD 0xff -#define BIT_UDF_THSD(x) (((x) & BIT_MASK_UDF_THSD) << BIT_SHIFT_UDF_THSD) -#define BIT_GET_UDF_THSD(x) (((x) >> BIT_SHIFT_UDF_THSD) & BIT_MASK_UDF_THSD) +/* 2 REG_UDF_THSD (Offset 0x0632) */ +#define BIT_UDF_THSD_V1 BIT(7) -/* 2 REG_ZLD_NUM (Offset 0x0633) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_ZLD_NUM 0 -#define BIT_MASK_ZLD_NUM 0xff -#define BIT_ZLD_NUM(x) (((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM) -#define BIT_GET_ZLD_NUM(x) (((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM) +/* 2 REG_UDF_THSD (Offset 0x0632) */ +#define BIT_SHIFT_UDF_THSD 0 +#define BIT_MASK_UDF_THSD 0xff +#define BIT_UDF_THSD(x) (((x) & BIT_MASK_UDF_THSD) << BIT_SHIFT_UDF_THSD) +#define BITS_UDF_THSD (BIT_MASK_UDF_THSD << BIT_SHIFT_UDF_THSD) +#define BIT_CLEAR_UDF_THSD(x) ((x) & (~BITS_UDF_THSD)) +#define BIT_GET_UDF_THSD(x) (((x) >> BIT_SHIFT_UDF_THSD) & BIT_MASK_UDF_THSD) +#define BIT_SET_UDF_THSD(x, v) (BIT_CLEAR_UDF_THSD(x) | BIT_UDF_THSD(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_UDF_THSD (Offset 0x0632) */ +#define BIT_SHIFT_UDF_THSD_VALUE 0 +#define BIT_MASK_UDF_THSD_VALUE 0x7f +#define BIT_UDF_THSD_VALUE(x) \ + (((x) & BIT_MASK_UDF_THSD_VALUE) << BIT_SHIFT_UDF_THSD_VALUE) +#define BITS_UDF_THSD_VALUE \ + (BIT_MASK_UDF_THSD_VALUE << BIT_SHIFT_UDF_THSD_VALUE) +#define BIT_CLEAR_UDF_THSD_VALUE(x) ((x) & (~BITS_UDF_THSD_VALUE)) +#define BIT_GET_UDF_THSD_VALUE(x) \ + (((x) >> BIT_SHIFT_UDF_THSD_VALUE) & BIT_MASK_UDF_THSD_VALUE) +#define BIT_SET_UDF_THSD_VALUE(x, v) \ + (BIT_CLEAR_UDF_THSD_VALUE(x) | BIT_UDF_THSD_VALUE(v)) -/* 2 REG_MCU_TEST_2 (Offset 0x0634) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MCU_RSVD_2 0 -#define BIT_MASK_MCU_RSVD_2 0xffffffffL -#define BIT_MCU_RSVD_2(x) (((x) & BIT_MASK_MCU_RSVD_2) << BIT_SHIFT_MCU_RSVD_2) -#define BIT_GET_MCU_RSVD_2(x) (((x) >> BIT_SHIFT_MCU_RSVD_2) & BIT_MASK_MCU_RSVD_2) +/* 2 REG_ZLD_NUM (Offset 0x0633) */ +#define BIT_SHIFT_ZLD_NUM 0 +#define BIT_MASK_ZLD_NUM 0xff +#define BIT_ZLD_NUM(x) (((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM) +#define BITS_ZLD_NUM (BIT_MASK_ZLD_NUM << BIT_SHIFT_ZLD_NUM) +#define BIT_CLEAR_ZLD_NUM(x) ((x) & (~BITS_ZLD_NUM)) +#define BIT_GET_ZLD_NUM(x) (((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM) +#define BIT_SET_ZLD_NUM(x, v) (BIT_CLEAR_ZLD_NUM(x) | BIT_ZLD_NUM(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MCU_TEST_2 (Offset 0x0634) */ +#define BIT_SHIFT_MCU_RSVD_2 0 +#define BIT_MASK_MCU_RSVD_2 0xffffffffL +#define BIT_MCU_RSVD_2(x) (((x) & BIT_MASK_MCU_RSVD_2) << BIT_SHIFT_MCU_RSVD_2) +#define BITS_MCU_RSVD_2 (BIT_MASK_MCU_RSVD_2 << BIT_SHIFT_MCU_RSVD_2) +#define BIT_CLEAR_MCU_RSVD_2(x) ((x) & (~BITS_MCU_RSVD_2)) +#define BIT_GET_MCU_RSVD_2(x) \ + (((x) >> BIT_SHIFT_MCU_RSVD_2) & BIT_MASK_MCU_RSVD_2) +#define BIT_SET_MCU_RSVD_2(x, v) (BIT_CLEAR_MCU_RSVD_2(x) | BIT_MCU_RSVD_2(v)) -/* 2 REG_STMP_THSD (Offset 0x0634) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_STMP_THSD 0 -#define BIT_MASK_STMP_THSD 0xff -#define BIT_STMP_THSD(x) (((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD) -#define BIT_GET_STMP_THSD(x) (((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD) +/* 2 REG_STMP_THSD (Offset 0x0634) */ +#define BIT_SHIFT_STMP_THSD 0 +#define BIT_MASK_STMP_THSD 0xff +#define BIT_STMP_THSD(x) (((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD) +#define BITS_STMP_THSD (BIT_MASK_STMP_THSD << BIT_SHIFT_STMP_THSD) +#define BIT_CLEAR_STMP_THSD(x) ((x) & (~BITS_STMP_THSD)) +#define BIT_GET_STMP_THSD(x) (((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD) +#define BIT_SET_STMP_THSD(x, v) (BIT_CLEAR_STMP_THSD(x) | BIT_STMP_THSD(v)) /* 2 REG_WMAC_TXTIMEOUT (Offset 0x0635) */ +#define BIT_SHIFT_WMAC_TXTIMEOUT 0 +#define BIT_MASK_WMAC_TXTIMEOUT 0xff +#define BIT_WMAC_TXTIMEOUT(x) \ + (((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT) +#define BITS_WMAC_TXTIMEOUT \ + (BIT_MASK_WMAC_TXTIMEOUT << BIT_SHIFT_WMAC_TXTIMEOUT) +#define BIT_CLEAR_WMAC_TXTIMEOUT(x) ((x) & (~BITS_WMAC_TXTIMEOUT)) +#define BIT_GET_WMAC_TXTIMEOUT(x) \ + (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT) +#define BIT_SET_WMAC_TXTIMEOUT(x, v) \ + (BIT_CLEAR_WMAC_TXTIMEOUT(x) | BIT_WMAC_TXTIMEOUT(v)) -#define BIT_SHIFT_WMAC_TXTIMEOUT 0 -#define BIT_MASK_WMAC_TXTIMEOUT 0xff -#define BIT_WMAC_TXTIMEOUT(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT) -#define BIT_GET_WMAC_TXTIMEOUT(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_MCU_TEST_2_V1 (Offset 0x0636) */ - -#define BIT_SHIFT_MCU_RSVD_2_V1 0 -#define BIT_MASK_MCU_RSVD_2_V1 0xffff -#define BIT_MCU_RSVD_2_V1(x) (((x) & BIT_MASK_MCU_RSVD_2_V1) << BIT_SHIFT_MCU_RSVD_2_V1) -#define BIT_GET_MCU_RSVD_2_V1(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1) & BIT_MASK_MCU_RSVD_2_V1) - +#define BIT_SHIFT_MCU_RSVD_2_V1 0 +#define BIT_MASK_MCU_RSVD_2_V1 0xffff +#define BIT_MCU_RSVD_2_V1(x) \ + (((x) & BIT_MASK_MCU_RSVD_2_V1) << BIT_SHIFT_MCU_RSVD_2_V1) +#define BITS_MCU_RSVD_2_V1 (BIT_MASK_MCU_RSVD_2_V1 << BIT_SHIFT_MCU_RSVD_2_V1) +#define BIT_CLEAR_MCU_RSVD_2_V1(x) ((x) & (~BITS_MCU_RSVD_2_V1)) +#define BIT_GET_MCU_RSVD_2_V1(x) \ + (((x) >> BIT_SHIFT_MCU_RSVD_2_V1) & BIT_MASK_MCU_RSVD_2_V1) +#define BIT_SET_MCU_RSVD_2_V1(x, v) \ + (BIT_CLEAR_MCU_RSVD_2_V1(x) | BIT_MCU_RSVD_2_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_USTIME_EDCA (Offset 0x0638) */ - -#define BIT_SHIFT_USTIME_EDCA 0 -#define BIT_MASK_USTIME_EDCA 0xff -#define BIT_USTIME_EDCA(x) (((x) & BIT_MASK_USTIME_EDCA) << BIT_SHIFT_USTIME_EDCA) -#define BIT_GET_USTIME_EDCA(x) (((x) >> BIT_SHIFT_USTIME_EDCA) & BIT_MASK_USTIME_EDCA) - +#define BIT_SHIFT_USTIME_EDCA 0 +#define BIT_MASK_USTIME_EDCA 0xff +#define BIT_USTIME_EDCA(x) \ + (((x) & BIT_MASK_USTIME_EDCA) << BIT_SHIFT_USTIME_EDCA) +#define BITS_USTIME_EDCA (BIT_MASK_USTIME_EDCA << BIT_SHIFT_USTIME_EDCA) +#define BIT_CLEAR_USTIME_EDCA(x) ((x) & (~BITS_USTIME_EDCA)) +#define BIT_GET_USTIME_EDCA(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA) & BIT_MASK_USTIME_EDCA) +#define BIT_SET_USTIME_EDCA(x, v) \ + (BIT_CLEAR_USTIME_EDCA(x) | BIT_USTIME_EDCA(v)) #endif - -#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_USTIME_EDCA (Offset 0x0638) */ - -#define BIT_SHIFT_USTIME_EDCA_V1 0 -#define BIT_MASK_USTIME_EDCA_V1 0x1ff -#define BIT_USTIME_EDCA_V1(x) (((x) & BIT_MASK_USTIME_EDCA_V1) << BIT_SHIFT_USTIME_EDCA_V1) -#define BIT_GET_USTIME_EDCA_V1(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1) & BIT_MASK_USTIME_EDCA_V1) - +#define BIT_SHIFT_USTIME_EDCA_V1 0 +#define BIT_MASK_USTIME_EDCA_V1 0x1ff +#define BIT_USTIME_EDCA_V1(x) \ + (((x) & BIT_MASK_USTIME_EDCA_V1) << BIT_SHIFT_USTIME_EDCA_V1) +#define BITS_USTIME_EDCA_V1 \ + (BIT_MASK_USTIME_EDCA_V1 << BIT_SHIFT_USTIME_EDCA_V1) +#define BIT_CLEAR_USTIME_EDCA_V1(x) ((x) & (~BITS_USTIME_EDCA_V1)) +#define BIT_GET_USTIME_EDCA_V1(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA_V1) & BIT_MASK_USTIME_EDCA_V1) +#define BIT_SET_USTIME_EDCA_V1(x, v) \ + (BIT_CLEAR_USTIME_EDCA_V1(x) | BIT_USTIME_EDCA_V1(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_ACKTO_CCK (Offset 0x0639) */ - -#define BIT_SHIFT_ACKTO_CCK 0 -#define BIT_MASK_ACKTO_CCK 0xff -#define BIT_ACKTO_CCK(x) (((x) & BIT_MASK_ACKTO_CCK) << BIT_SHIFT_ACKTO_CCK) -#define BIT_GET_ACKTO_CCK(x) (((x) >> BIT_SHIFT_ACKTO_CCK) & BIT_MASK_ACKTO_CCK) - +#define BIT_SHIFT_ACKTO_CCK 0 +#define BIT_MASK_ACKTO_CCK 0xff +#define BIT_ACKTO_CCK(x) (((x) & BIT_MASK_ACKTO_CCK) << BIT_SHIFT_ACKTO_CCK) +#define BITS_ACKTO_CCK (BIT_MASK_ACKTO_CCK << BIT_SHIFT_ACKTO_CCK) +#define BIT_CLEAR_ACKTO_CCK(x) ((x) & (~BITS_ACKTO_CCK)) +#define BIT_GET_ACKTO_CCK(x) (((x) >> BIT_SHIFT_ACKTO_CCK) & BIT_MASK_ACKTO_CCK) +#define BIT_SET_ACKTO_CCK(x, v) (BIT_CLEAR_ACKTO_CCK(x) | BIT_ACKTO_CCK(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_MAC_SPEC_SIFS (Offset 0x063A) */ - -#define BIT_SHIFT_SPEC_SIFS_OFDM 8 -#define BIT_MASK_SPEC_SIFS_OFDM 0xff -#define BIT_SPEC_SIFS_OFDM(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM) -#define BIT_GET_SPEC_SIFS_OFDM(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM) - - -#define BIT_SHIFT_SPEC_SIFS_CCK 0 -#define BIT_MASK_SPEC_SIFS_CCK 0xff -#define BIT_SPEC_SIFS_CCK(x) (((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK) -#define BIT_GET_SPEC_SIFS_CCK(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK) - +#define BIT_SHIFT_SPEC_SIFS_OFDM 8 +#define BIT_MASK_SPEC_SIFS_OFDM 0xff +#define BIT_SPEC_SIFS_OFDM(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM) +#define BITS_SPEC_SIFS_OFDM \ + (BIT_MASK_SPEC_SIFS_OFDM << BIT_SHIFT_SPEC_SIFS_OFDM) +#define BIT_CLEAR_SPEC_SIFS_OFDM(x) ((x) & (~BITS_SPEC_SIFS_OFDM)) +#define BIT_GET_SPEC_SIFS_OFDM(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM) +#define BIT_SET_SPEC_SIFS_OFDM(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM(x) | BIT_SPEC_SIFS_OFDM(v)) + +#define BIT_SHIFT_SPEC_SIFS_CCK 0 +#define BIT_MASK_SPEC_SIFS_CCK 0xff +#define BIT_SPEC_SIFS_CCK(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK) +#define BITS_SPEC_SIFS_CCK (BIT_MASK_SPEC_SIFS_CCK << BIT_SHIFT_SPEC_SIFS_CCK) +#define BIT_CLEAR_SPEC_SIFS_CCK(x) ((x) & (~BITS_SPEC_SIFS_CCK)) +#define BIT_GET_SPEC_SIFS_CCK(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK) +#define BIT_SET_SPEC_SIFS_CCK(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK(x) | BIT_SPEC_SIFS_CCK(v)) /* 2 REG_RESP_SIFS_CCK (Offset 0x063C) */ - -#define BIT_SHIFT_SIFS_R2T_CCK 8 -#define BIT_MASK_SIFS_R2T_CCK 0xff -#define BIT_SIFS_R2T_CCK(x) (((x) & BIT_MASK_SIFS_R2T_CCK) << BIT_SHIFT_SIFS_R2T_CCK) -#define BIT_GET_SIFS_R2T_CCK(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK) & BIT_MASK_SIFS_R2T_CCK) - - -#define BIT_SHIFT_SIFS_T2T_CCK 0 -#define BIT_MASK_SIFS_T2T_CCK 0xff -#define BIT_SIFS_T2T_CCK(x) (((x) & BIT_MASK_SIFS_T2T_CCK) << BIT_SHIFT_SIFS_T2T_CCK) -#define BIT_GET_SIFS_T2T_CCK(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK) & BIT_MASK_SIFS_T2T_CCK) - +#define BIT_SHIFT_SIFS_R2T_CCK 8 +#define BIT_MASK_SIFS_R2T_CCK 0xff +#define BIT_SIFS_R2T_CCK(x) \ + (((x) & BIT_MASK_SIFS_R2T_CCK) << BIT_SHIFT_SIFS_R2T_CCK) +#define BITS_SIFS_R2T_CCK (BIT_MASK_SIFS_R2T_CCK << BIT_SHIFT_SIFS_R2T_CCK) +#define BIT_CLEAR_SIFS_R2T_CCK(x) ((x) & (~BITS_SIFS_R2T_CCK)) +#define BIT_GET_SIFS_R2T_CCK(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_CCK) & BIT_MASK_SIFS_R2T_CCK) +#define BIT_SET_SIFS_R2T_CCK(x, v) \ + (BIT_CLEAR_SIFS_R2T_CCK(x) | BIT_SIFS_R2T_CCK(v)) + +#define BIT_SHIFT_SIFS_T2T_CCK 0 +#define BIT_MASK_SIFS_T2T_CCK 0xff +#define BIT_SIFS_T2T_CCK(x) \ + (((x) & BIT_MASK_SIFS_T2T_CCK) << BIT_SHIFT_SIFS_T2T_CCK) +#define BITS_SIFS_T2T_CCK (BIT_MASK_SIFS_T2T_CCK << BIT_SHIFT_SIFS_T2T_CCK) +#define BIT_CLEAR_SIFS_T2T_CCK(x) ((x) & (~BITS_SIFS_T2T_CCK)) +#define BIT_GET_SIFS_T2T_CCK(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_CCK) & BIT_MASK_SIFS_T2T_CCK) +#define BIT_SET_SIFS_T2T_CCK(x, v) \ + (BIT_CLEAR_SIFS_T2T_CCK(x) | BIT_SIFS_T2T_CCK(v)) /* 2 REG_RESP_SIFS_OFDM (Offset 0x063E) */ - -#define BIT_SHIFT_SIFS_R2T_OFDM 8 -#define BIT_MASK_SIFS_R2T_OFDM 0xff -#define BIT_SIFS_R2T_OFDM(x) (((x) & BIT_MASK_SIFS_R2T_OFDM) << BIT_SHIFT_SIFS_R2T_OFDM) -#define BIT_GET_SIFS_R2T_OFDM(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM) & BIT_MASK_SIFS_R2T_OFDM) - - -#define BIT_SHIFT_SIFS_T2T_OFDM 0 -#define BIT_MASK_SIFS_T2T_OFDM 0xff -#define BIT_SIFS_T2T_OFDM(x) (((x) & BIT_MASK_SIFS_T2T_OFDM) << BIT_SHIFT_SIFS_T2T_OFDM) -#define BIT_GET_SIFS_T2T_OFDM(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM) & BIT_MASK_SIFS_T2T_OFDM) - +#define BIT_SHIFT_SIFS_R2T_OFDM 8 +#define BIT_MASK_SIFS_R2T_OFDM 0xff +#define BIT_SIFS_R2T_OFDM(x) \ + (((x) & BIT_MASK_SIFS_R2T_OFDM) << BIT_SHIFT_SIFS_R2T_OFDM) +#define BITS_SIFS_R2T_OFDM (BIT_MASK_SIFS_R2T_OFDM << BIT_SHIFT_SIFS_R2T_OFDM) +#define BIT_CLEAR_SIFS_R2T_OFDM(x) ((x) & (~BITS_SIFS_R2T_OFDM)) +#define BIT_GET_SIFS_R2T_OFDM(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_OFDM) & BIT_MASK_SIFS_R2T_OFDM) +#define BIT_SET_SIFS_R2T_OFDM(x, v) \ + (BIT_CLEAR_SIFS_R2T_OFDM(x) | BIT_SIFS_R2T_OFDM(v)) + +#define BIT_SHIFT_SIFS_T2T_OFDM 0 +#define BIT_MASK_SIFS_T2T_OFDM 0xff +#define BIT_SIFS_T2T_OFDM(x) \ + (((x) & BIT_MASK_SIFS_T2T_OFDM) << BIT_SHIFT_SIFS_T2T_OFDM) +#define BITS_SIFS_T2T_OFDM (BIT_MASK_SIFS_T2T_OFDM << BIT_SHIFT_SIFS_T2T_OFDM) +#define BIT_CLEAR_SIFS_T2T_OFDM(x) ((x) & (~BITS_SIFS_T2T_OFDM)) +#define BIT_GET_SIFS_T2T_OFDM(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_OFDM) & BIT_MASK_SIFS_T2T_OFDM) +#define BIT_SET_SIFS_T2T_OFDM(x, v) \ + (BIT_CLEAR_SIFS_T2T_OFDM(x) | BIT_SIFS_T2T_OFDM(v)) /* 2 REG_ACKTO (Offset 0x0640) */ - -#define BIT_SHIFT_ACKTO 0 -#define BIT_MASK_ACKTO 0xff -#define BIT_ACKTO(x) (((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO) -#define BIT_GET_ACKTO(x) (((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO) - +#define BIT_SHIFT_ACKTO 0 +#define BIT_MASK_ACKTO 0xff +#define BIT_ACKTO(x) (((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO) +#define BITS_ACKTO (BIT_MASK_ACKTO << BIT_SHIFT_ACKTO) +#define BIT_CLEAR_ACKTO(x) ((x) & (~BITS_ACKTO)) +#define BIT_GET_ACKTO(x) (((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO) +#define BIT_SET_ACKTO(x, v) (BIT_CLEAR_ACKTO(x) | BIT_ACKTO(v)) /* 2 REG_CTS2TO (Offset 0x0641) */ - -#define BIT_SHIFT_CTS2TO 0 -#define BIT_MASK_CTS2TO 0xff -#define BIT_CTS2TO(x) (((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO) -#define BIT_GET_CTS2TO(x) (((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO) - +#define BIT_SHIFT_CTS2TO 0 +#define BIT_MASK_CTS2TO 0xff +#define BIT_CTS2TO(x) (((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO) +#define BITS_CTS2TO (BIT_MASK_CTS2TO << BIT_SHIFT_CTS2TO) +#define BIT_CLEAR_CTS2TO(x) ((x) & (~BITS_CTS2TO)) +#define BIT_GET_CTS2TO(x) (((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO) +#define BIT_SET_CTS2TO(x, v) (BIT_CLEAR_CTS2TO(x) | BIT_CTS2TO(v)) /* 2 REG_EIFS (Offset 0x0642) */ +#define BIT_SHIFT_EIFS 0 +#define BIT_MASK_EIFS 0xffff +#define BIT_EIFS(x) (((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS) +#define BITS_EIFS (BIT_MASK_EIFS << BIT_SHIFT_EIFS) +#define BIT_CLEAR_EIFS(x) ((x) & (~BITS_EIFS)) +#define BIT_GET_EIFS(x) (((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS) +#define BIT_SET_EIFS(x, v) (BIT_CLEAR_EIFS(x) | BIT_EIFS(v)) -#define BIT_SHIFT_EIFS 0 -#define BIT_MASK_EIFS 0xffff -#define BIT_EIFS(x) (((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS) -#define BIT_GET_EIFS(x) (((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_RPFM_MAP0 (Offset 0x0644) */ +#define BIT_MGT_RPFM15EN BIT(15) +#define BIT_MGT_RPFM14EN BIT(14) +#define BIT_MGT_RPFM13EN BIT(13) +#define BIT_MGT_RPFM12EN BIT(12) +#define BIT_MGT_RPFM11EN BIT(11) +#define BIT_MGT_RPFM10EN BIT(10) +#define BIT_MGT_RPFM9EN BIT(9) +#define BIT_MGT_RPFM8EN BIT(8) +#define BIT_MGT_RPFM7EN BIT(7) +#define BIT_MGT_RPFM6EN BIT(6) +#define BIT_MGT_RPFM5EN BIT(5) +#define BIT_MGT_RPFM4EN BIT(4) +#define BIT_MGT_RPFM3EN BIT(3) +#define BIT_MGT_RPFM2EN BIT(2) +#define BIT_MGT_RPFM1EN BIT(1) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_RPFM_MAP0 (Offset 0x0644) */ -#define BIT_MGT_RPFM15EN BIT(15) -#define BIT_MGT_RPFM14EN BIT(14) -#define BIT_MGT_RPFM13EN BIT(13) -#define BIT_MGT_RPFM12EN BIT(12) -#define BIT_MGT_RPFM11EN BIT(11) -#define BIT_MGT_RPFM10EN BIT(10) -#define BIT_MGT_RPFM9EN BIT(9) -#define BIT_MGT_RPFM8EN BIT(8) -#define BIT_MGT_RPFM7EN BIT(7) -#define BIT_MGT_RPFM6EN BIT(6) -#define BIT_MGT_RPFM5EN BIT(5) -#define BIT_MGT_RPFM4EN BIT(4) -#define BIT_MGT_RPFM3EN BIT(3) -#define BIT_MGT_RPFM2EN BIT(2) -#define BIT_MGT_RPFM1EN BIT(1) -#define BIT_MGT_RPFM0EN BIT(0) +#define BIT_SHIFT_RPFM_MAP0 0 +#define BIT_MASK_RPFM_MAP0 0xffff +#define BIT_RPFM_MAP0(x) (((x) & BIT_MASK_RPFM_MAP0) << BIT_SHIFT_RPFM_MAP0) +#define BITS_RPFM_MAP0 (BIT_MASK_RPFM_MAP0 << BIT_SHIFT_RPFM_MAP0) +#define BIT_CLEAR_RPFM_MAP0(x) ((x) & (~BITS_RPFM_MAP0)) +#define BIT_GET_RPFM_MAP0(x) (((x) >> BIT_SHIFT_RPFM_MAP0) & BIT_MASK_RPFM_MAP0) +#define BIT_SET_RPFM_MAP0(x, v) (BIT_CLEAR_RPFM_MAP0(x) | BIT_RPFM_MAP0(v)) -/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ +#endif -#define BIT_RPFM_CAM_POLLING BIT(31) -#define BIT_RPFM_CAM_CLR BIT(30) -#define BIT_RPFM_CAM_WE BIT(16) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RPFM_CAM_ADDR 0 -#define BIT_MASK_RPFM_CAM_ADDR 0x7f -#define BIT_RPFM_CAM_ADDR(x) (((x) & BIT_MASK_RPFM_CAM_ADDR) << BIT_SHIFT_RPFM_CAM_ADDR) -#define BIT_GET_RPFM_CAM_ADDR(x) (((x) >> BIT_SHIFT_RPFM_CAM_ADDR) & BIT_MASK_RPFM_CAM_ADDR) +/* 2 REG_RPFM_MAP0 (Offset 0x0644) */ +#define BIT_MGT_RPFM0EN BIT(0) -/* 2 REG_RPFM_CAM_RWD (Offset 0x064C) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RPFM_CAM_RWD 0 -#define BIT_MASK_RPFM_CAM_RWD 0xffffffffL -#define BIT_RPFM_CAM_RWD(x) (((x) & BIT_MASK_RPFM_CAM_RWD) << BIT_SHIFT_RPFM_CAM_RWD) -#define BIT_GET_RPFM_CAM_RWD(x) (((x) >> BIT_SHIFT_RPFM_CAM_RWD) & BIT_MASK_RPFM_CAM_RWD) +/* 2 REG_RPFM_MAP1 (Offset 0x0646) */ +#define BIT_SHIFT_RPFM_MAP1 0 +#define BIT_MASK_RPFM_MAP1 0xffff +#define BIT_RPFM_MAP1(x) (((x) & BIT_MASK_RPFM_MAP1) << BIT_SHIFT_RPFM_MAP1) +#define BITS_RPFM_MAP1 (BIT_MASK_RPFM_MAP1 << BIT_SHIFT_RPFM_MAP1) +#define BIT_CLEAR_RPFM_MAP1(x) ((x) & (~BITS_RPFM_MAP1)) +#define BIT_GET_RPFM_MAP1(x) (((x) >> BIT_SHIFT_RPFM_MAP1) & BIT_MASK_RPFM_MAP1) +#define BIT_SET_RPFM_MAP1(x, v) (BIT_CLEAR_RPFM_MAP1(x) | BIT_RPFM_MAP1(v)) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ +#define BIT_RPFM_CAM_POLLING BIT(31) +#define BIT_RPFM_CAM_CLR BIT(30) -/* 2 REG_NAV_CTRL (Offset 0x0650) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_NAV_UPPER 16 -#define BIT_MASK_NAV_UPPER 0xff -#define BIT_NAV_UPPER(x) (((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER) -#define BIT_GET_NAV_UPPER(x) (((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER) +/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ +#define BIT_RPFM_CAM_WR BIT(16) -#define BIT_SHIFT_RXMYRTS_NAV 8 -#define BIT_MASK_RXMYRTS_NAV 0xf -#define BIT_RXMYRTS_NAV(x) (((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV) -#define BIT_GET_RXMYRTS_NAV(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RTSRST 0 -#define BIT_MASK_RTSRST 0xff -#define BIT_RTSRST(x) (((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST) -#define BIT_GET_RTSRST(x) (((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST) +/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ +#define BIT_RPFM_CAM_WE BIT(16) -/* 2 REG_BACAMCMD (Offset 0x0654) */ +#endif -#define BIT_BACAM_POLL BIT(31) -#define BIT_BACAM_RST BIT(17) -#define BIT_BACAM_RW BIT(16) +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TXSBM 14 -#define BIT_MASK_TXSBM 0x3 -#define BIT_TXSBM(x) (((x) & BIT_MASK_TXSBM) << BIT_SHIFT_TXSBM) -#define BIT_GET_TXSBM(x) (((x) >> BIT_SHIFT_TXSBM) & BIT_MASK_TXSBM) +/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ +#define BIT_SHIFT_RPFM_CAM_ADDR 0 +#define BIT_MASK_RPFM_CAM_ADDR 0x7f +#define BIT_RPFM_CAM_ADDR(x) \ + (((x) & BIT_MASK_RPFM_CAM_ADDR) << BIT_SHIFT_RPFM_CAM_ADDR) +#define BITS_RPFM_CAM_ADDR (BIT_MASK_RPFM_CAM_ADDR << BIT_SHIFT_RPFM_CAM_ADDR) +#define BIT_CLEAR_RPFM_CAM_ADDR(x) ((x) & (~BITS_RPFM_CAM_ADDR)) +#define BIT_GET_RPFM_CAM_ADDR(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_ADDR) & BIT_MASK_RPFM_CAM_ADDR) +#define BIT_SET_RPFM_CAM_ADDR(x, v) \ + (BIT_CLEAR_RPFM_CAM_ADDR(x) | BIT_RPFM_CAM_ADDR(v)) -#define BIT_SHIFT_BACAM_ADDR 0 -#define BIT_MASK_BACAM_ADDR 0x3f -#define BIT_BACAM_ADDR(x) (((x) & BIT_MASK_BACAM_ADDR) << BIT_SHIFT_BACAM_ADDR) -#define BIT_GET_BACAM_ADDR(x) (((x) >> BIT_SHIFT_BACAM_ADDR) & BIT_MASK_BACAM_ADDR) +/* 2 REG_RPFM_CAM_RWD (Offset 0x064C) */ +#define BIT_SHIFT_RPFM_CAM_RWD 0 +#define BIT_MASK_RPFM_CAM_RWD 0xffffffffL +#define BIT_RPFM_CAM_RWD(x) \ + (((x) & BIT_MASK_RPFM_CAM_RWD) << BIT_SHIFT_RPFM_CAM_RWD) +#define BITS_RPFM_CAM_RWD (BIT_MASK_RPFM_CAM_RWD << BIT_SHIFT_RPFM_CAM_RWD) +#define BIT_CLEAR_RPFM_CAM_RWD(x) ((x) & (~BITS_RPFM_CAM_RWD)) +#define BIT_GET_RPFM_CAM_RWD(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_RWD) & BIT_MASK_RPFM_CAM_RWD) +#define BIT_SET_RPFM_CAM_RWD(x, v) \ + (BIT_CLEAR_RPFM_CAM_RWD(x) | BIT_RPFM_CAM_RWD(v)) -/* 2 REG_BACAMCONTENT (Offset 0x0658) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BA_CONTENT_H (32 & CPU_OPT_WIDTH) -#define BIT_MASK_BA_CONTENT_H 0xffffffffL -#define BIT_BA_CONTENT_H(x) (((x) & BIT_MASK_BA_CONTENT_H) << BIT_SHIFT_BA_CONTENT_H) -#define BIT_GET_BA_CONTENT_H(x) (((x) >> BIT_SHIFT_BA_CONTENT_H) & BIT_MASK_BA_CONTENT_H) +/* 2 REG_NAV_CTRL (Offset 0x0650) */ +#define BIT_SHIFT_NAV_UPPER 16 +#define BIT_MASK_NAV_UPPER 0xff +#define BIT_NAV_UPPER(x) (((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER) +#define BITS_NAV_UPPER (BIT_MASK_NAV_UPPER << BIT_SHIFT_NAV_UPPER) +#define BIT_CLEAR_NAV_UPPER(x) ((x) & (~BITS_NAV_UPPER)) +#define BIT_GET_NAV_UPPER(x) (((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER) +#define BIT_SET_NAV_UPPER(x, v) (BIT_CLEAR_NAV_UPPER(x) | BIT_NAV_UPPER(v)) + +#define BIT_SHIFT_RXMYRTS_NAV 8 +#define BIT_MASK_RXMYRTS_NAV 0xf +#define BIT_RXMYRTS_NAV(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV) +#define BITS_RXMYRTS_NAV (BIT_MASK_RXMYRTS_NAV << BIT_SHIFT_RXMYRTS_NAV) +#define BIT_CLEAR_RXMYRTS_NAV(x) ((x) & (~BITS_RXMYRTS_NAV)) +#define BIT_GET_RXMYRTS_NAV(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV) +#define BIT_SET_RXMYRTS_NAV(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV(x) | BIT_RXMYRTS_NAV(v)) + +#define BIT_SHIFT_RTSRST 0 +#define BIT_MASK_RTSRST 0xff +#define BIT_RTSRST(x) (((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST) +#define BITS_RTSRST (BIT_MASK_RTSRST << BIT_SHIFT_RTSRST) +#define BIT_CLEAR_RTSRST(x) ((x) & (~BITS_RTSRST)) +#define BIT_GET_RTSRST(x) (((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST) +#define BIT_SET_RTSRST(x, v) (BIT_CLEAR_RTSRST(x) | BIT_RTSRST(v)) -#define BIT_SHIFT_BA_CONTENT_L 0 -#define BIT_MASK_BA_CONTENT_L 0xffffffffL -#define BIT_BA_CONTENT_L(x) (((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L) -#define BIT_GET_BA_CONTENT_L(x) (((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L) +/* 2 REG_BACAMCMD (Offset 0x0654) */ +#define BIT_BACAM_POLL BIT(31) +#define BIT_BACAM_RST BIT(17) +#define BIT_BACAM_RW BIT(16) + +#define BIT_SHIFT_TXSBM 14 +#define BIT_MASK_TXSBM 0x3 +#define BIT_TXSBM(x) (((x) & BIT_MASK_TXSBM) << BIT_SHIFT_TXSBM) +#define BITS_TXSBM (BIT_MASK_TXSBM << BIT_SHIFT_TXSBM) +#define BIT_CLEAR_TXSBM(x) ((x) & (~BITS_TXSBM)) +#define BIT_GET_TXSBM(x) (((x) >> BIT_SHIFT_TXSBM) & BIT_MASK_TXSBM) +#define BIT_SET_TXSBM(x, v) (BIT_CLEAR_TXSBM(x) | BIT_TXSBM(v)) + +#define BIT_SHIFT_BACAM_ADDR 0 +#define BIT_MASK_BACAM_ADDR 0x3f +#define BIT_BACAM_ADDR(x) (((x) & BIT_MASK_BACAM_ADDR) << BIT_SHIFT_BACAM_ADDR) +#define BITS_BACAM_ADDR (BIT_MASK_BACAM_ADDR << BIT_SHIFT_BACAM_ADDR) +#define BIT_CLEAR_BACAM_ADDR(x) ((x) & (~BITS_BACAM_ADDR)) +#define BIT_GET_BACAM_ADDR(x) \ + (((x) >> BIT_SHIFT_BACAM_ADDR) & BIT_MASK_BACAM_ADDR) +#define BIT_SET_BACAM_ADDR(x, v) (BIT_CLEAR_BACAM_ADDR(x) | BIT_BACAM_ADDR(v)) -/* 2 REG_LBDLY (Offset 0x0660) */ +/* 2 REG_BACAMCONTENT (Offset 0x0658) */ +#define BIT_SHIFT_BA_CONTENT_L 0 +#define BIT_MASK_BA_CONTENT_L 0xffffffffL +#define BIT_BA_CONTENT_L(x) \ + (((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L) +#define BITS_BA_CONTENT_L (BIT_MASK_BA_CONTENT_L << BIT_SHIFT_BA_CONTENT_L) +#define BIT_CLEAR_BA_CONTENT_L(x) ((x) & (~BITS_BA_CONTENT_L)) +#define BIT_GET_BA_CONTENT_L(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L) +#define BIT_SET_BA_CONTENT_L(x, v) \ + (BIT_CLEAR_BA_CONTENT_L(x) | BIT_BA_CONTENT_L(v)) -#define BIT_SHIFT_LBDLY 0 -#define BIT_MASK_LBDLY 0x1f -#define BIT_LBDLY(x) (((x) & BIT_MASK_LBDLY) << BIT_SHIFT_LBDLY) -#define BIT_GET_LBDLY(x) (((x) >> BIT_SHIFT_LBDLY) & BIT_MASK_LBDLY) +/* 2 REG_LBDLY (Offset 0x0660) */ +#define BIT_SHIFT_LBDLY 0 +#define BIT_MASK_LBDLY 0x1f +#define BIT_LBDLY(x) (((x) & BIT_MASK_LBDLY) << BIT_SHIFT_LBDLY) +#define BITS_LBDLY (BIT_MASK_LBDLY << BIT_SHIFT_LBDLY) +#define BIT_CLEAR_LBDLY(x) ((x) & (~BITS_LBDLY)) +#define BIT_GET_LBDLY(x) (((x) >> BIT_SHIFT_LBDLY) & BIT_MASK_LBDLY) +#define BIT_SET_LBDLY(x, v) (BIT_CLEAR_LBDLY(x) | BIT_LBDLY(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ +#define BIT_SHIFT_BITMAP_SSNBK_COUNTER 2 +#define BIT_MASK_BITMAP_SSNBK_COUNTER 0x3f +#define BIT_BITMAP_SSNBK_COUNTER(x) \ + (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER) \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER) +#define BITS_BITMAP_SSNBK_COUNTER \ + (BIT_MASK_BITMAP_SSNBK_COUNTER << BIT_SHIFT_BITMAP_SSNBK_COUNTER) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) ((x) & (~BITS_BITMAP_SSNBK_COUNTER)) +#define BIT_GET_BITMAP_SSNBK_COUNTER(x) \ + (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) & \ + BIT_MASK_BITMAP_SSNBK_COUNTER) +#define BIT_SET_BITMAP_SSNBK_COUNTER(x, v) \ + (BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) | BIT_BITMAP_SSNBK_COUNTER(v)) -#define BIT_SHIFT_BITMAP_SSNBK_COUNTER 2 -#define BIT_MASK_BITMAP_SSNBK_COUNTER 0x3f -#define BIT_BITMAP_SSNBK_COUNTER(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER) << BIT_SHIFT_BITMAP_SSNBK_COUNTER) -#define BIT_GET_BITMAP_SSNBK_COUNTER(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) & BIT_MASK_BITMAP_SSNBK_COUNTER) - -#define BIT_BITMAP_EN BIT(1) +#define BIT_BITMAP_EN BIT(1) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ -#define BIT_WMAC_BACAM_RPMEN BIT(0) +#define BIT_WMAC_BACAM_RPMEN BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TX_RX (Offset 0x0662) */ +#define BIT_SHIFT_RXPKT_TYPE 2 +#define BIT_MASK_RXPKT_TYPE 0x3f +#define BIT_RXPKT_TYPE(x) (((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE) +#define BITS_RXPKT_TYPE (BIT_MASK_RXPKT_TYPE << BIT_SHIFT_RXPKT_TYPE) +#define BIT_CLEAR_RXPKT_TYPE(x) ((x) & (~BITS_RXPKT_TYPE)) +#define BIT_GET_RXPKT_TYPE(x) \ + (((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE) +#define BIT_SET_RXPKT_TYPE(x, v) (BIT_CLEAR_RXPKT_TYPE(x) | BIT_RXPKT_TYPE(v)) -#define BIT_SHIFT_RXPKT_TYPE 2 -#define BIT_MASK_RXPKT_TYPE 0x3f -#define BIT_RXPKT_TYPE(x) (((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE) -#define BIT_GET_RXPKT_TYPE(x) (((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE) - -#define BIT_TXACT_IND BIT(1) -#define BIT_RXACT_IND BIT(0) +#define BIT_TXACT_IND BIT(1) +#define BIT_RXACT_IND BIT(0) /* 2 REG_WMAC_BITMAP_CTL (Offset 0x0663) */ -#define BIT_BITMAP_VO BIT(7) -#define BIT_BITMAP_VI BIT(6) -#define BIT_BITMAP_BE BIT(5) -#define BIT_BITMAP_BK BIT(4) +#define BIT_BITMAP_VO BIT(7) +#define BIT_BITMAP_VI BIT(6) +#define BIT_BITMAP_BE BIT(5) +#define BIT_BITMAP_BK BIT(4) -#define BIT_SHIFT_BITMAP_CONDITION 2 -#define BIT_MASK_BITMAP_CONDITION 0x3 -#define BIT_BITMAP_CONDITION(x) (((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION) -#define BIT_GET_BITMAP_CONDITION(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION) +#define BIT_SHIFT_BITMAP_CONDITION 2 +#define BIT_MASK_BITMAP_CONDITION 0x3 +#define BIT_BITMAP_CONDITION(x) \ + (((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION) +#define BITS_BITMAP_CONDITION \ + (BIT_MASK_BITMAP_CONDITION << BIT_SHIFT_BITMAP_CONDITION) +#define BIT_CLEAR_BITMAP_CONDITION(x) ((x) & (~BITS_BITMAP_CONDITION)) +#define BIT_GET_BITMAP_CONDITION(x) \ + (((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION) +#define BIT_SET_BITMAP_CONDITION(x, v) \ + (BIT_CLEAR_BITMAP_CONDITION(x) | BIT_BITMAP_CONDITION(v)) -#define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1) -#define BIT_BITMAP_FORCE BIT(0) +#define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1) +#define BIT_BITMAP_FORCE BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ - -#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0 28 -#define BIT_MASK_RXERR_RPT_SEL_V1_3_0 0xf -#define BIT_RXERR_RPT_SEL_V1_3_0(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) -#define BIT_GET_RXERR_RPT_SEL_V1_3_0(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) - +#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0 28 +#define BIT_MASK_RXERR_RPT_SEL_V1_3_0 0xf +#define BIT_RXERR_RPT_SEL_V1_3_0(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) +#define BITS_RXERR_RPT_SEL_V1_3_0 \ + (BIT_MASK_RXERR_RPT_SEL_V1_3_0 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) & \ + BIT_MASK_RXERR_RPT_SEL_V1_3_0) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) | BIT_RXERR_RPT_SEL_V1_3_0(v)) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_RXERR_RPT (Offset 0x0664) */ - -#define BIT_SHIFT_RXERR_RPT_SEL 28 -#define BIT_MASK_RXERR_RPT_SEL 0xf -#define BIT_RXERR_RPT_SEL(x) (((x) & BIT_MASK_RXERR_RPT_SEL) << BIT_SHIFT_RXERR_RPT_SEL) -#define BIT_GET_RXERR_RPT_SEL(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL) & BIT_MASK_RXERR_RPT_SEL) - +#define BIT_SHIFT_RXERR_RPT_SEL 28 +#define BIT_MASK_RXERR_RPT_SEL 0xf +#define BIT_RXERR_RPT_SEL(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL) << BIT_SHIFT_RXERR_RPT_SEL) +#define BITS_RXERR_RPT_SEL (BIT_MASK_RXERR_RPT_SEL << BIT_SHIFT_RXERR_RPT_SEL) +#define BIT_CLEAR_RXERR_RPT_SEL(x) ((x) & (~BITS_RXERR_RPT_SEL)) +#define BIT_GET_RXERR_RPT_SEL(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL) & BIT_MASK_RXERR_RPT_SEL) +#define BIT_SET_RXERR_RPT_SEL(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL(x) | BIT_RXERR_RPT_SEL(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ -#define BIT_RXERR_RPT_RST BIT(27) +#define BIT_RXERR_RPT_RST BIT(27) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ -#define BIT_RXERR_RPT_SEL_V1_4 BIT(26) +#define BIT_RXERR_RPT_SEL_V1_4 BIT(26) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ - -#define BIT_SHIFT_UD_SELECT_BSSID_2_1 24 -#define BIT_MASK_UD_SELECT_BSSID_2_1 0x3 -#define BIT_UD_SELECT_BSSID_2_1(x) (((x) & BIT_MASK_UD_SELECT_BSSID_2_1) << BIT_SHIFT_UD_SELECT_BSSID_2_1) -#define BIT_GET_UD_SELECT_BSSID_2_1(x) (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1) & BIT_MASK_UD_SELECT_BSSID_2_1) - +#define BIT_SHIFT_UD_SELECT_BSSID_2_1 24 +#define BIT_MASK_UD_SELECT_BSSID_2_1 0x3 +#define BIT_UD_SELECT_BSSID_2_1(x) \ + (((x) & BIT_MASK_UD_SELECT_BSSID_2_1) << BIT_SHIFT_UD_SELECT_BSSID_2_1) +#define BITS_UD_SELECT_BSSID_2_1 \ + (BIT_MASK_UD_SELECT_BSSID_2_1 << BIT_SHIFT_UD_SELECT_BSSID_2_1) +#define BIT_CLEAR_UD_SELECT_BSSID_2_1(x) ((x) & (~BITS_UD_SELECT_BSSID_2_1)) +#define BIT_GET_UD_SELECT_BSSID_2_1(x) \ + (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1) & BIT_MASK_UD_SELECT_BSSID_2_1) +#define BIT_SET_UD_SELECT_BSSID_2_1(x, v) \ + (BIT_CLEAR_UD_SELECT_BSSID_2_1(x) | BIT_UD_SELECT_BSSID_2_1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ -#define BIT_W1S BIT(23) +#define BIT_W1S BIT(23) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ -#define BIT_UD_SELECT_BSSID BIT(22) +#define BIT_UD_SELECT_BSSID BIT(22) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ -#define BIT_UD_SELECT_BSSID_0 BIT(22) +#define BIT_UD_SELECT_BSSID_0 BIT(22) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ - -#define BIT_SHIFT_UD_SUB_TYPE 18 -#define BIT_MASK_UD_SUB_TYPE 0xf -#define BIT_UD_SUB_TYPE(x) (((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE) -#define BIT_GET_UD_SUB_TYPE(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE) - - -#define BIT_SHIFT_UD_TYPE 16 -#define BIT_MASK_UD_TYPE 0x3 -#define BIT_UD_TYPE(x) (((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE) -#define BIT_GET_UD_TYPE(x) (((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE) - - -#define BIT_SHIFT_RPT_COUNTER 0 -#define BIT_MASK_RPT_COUNTER 0xffff -#define BIT_RPT_COUNTER(x) (((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER) -#define BIT_GET_RPT_COUNTER(x) (((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER) - +#define BIT_SHIFT_UD_SUB_TYPE 18 +#define BIT_MASK_UD_SUB_TYPE 0xf +#define BIT_UD_SUB_TYPE(x) \ + (((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE) +#define BITS_UD_SUB_TYPE (BIT_MASK_UD_SUB_TYPE << BIT_SHIFT_UD_SUB_TYPE) +#define BIT_CLEAR_UD_SUB_TYPE(x) ((x) & (~BITS_UD_SUB_TYPE)) +#define BIT_GET_UD_SUB_TYPE(x) \ + (((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE) +#define BIT_SET_UD_SUB_TYPE(x, v) \ + (BIT_CLEAR_UD_SUB_TYPE(x) | BIT_UD_SUB_TYPE(v)) + +#define BIT_SHIFT_UD_TYPE 16 +#define BIT_MASK_UD_TYPE 0x3 +#define BIT_UD_TYPE(x) (((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE) +#define BITS_UD_TYPE (BIT_MASK_UD_TYPE << BIT_SHIFT_UD_TYPE) +#define BIT_CLEAR_UD_TYPE(x) ((x) & (~BITS_UD_TYPE)) +#define BIT_GET_UD_TYPE(x) (((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE) +#define BIT_SET_UD_TYPE(x, v) (BIT_CLEAR_UD_TYPE(x) | BIT_UD_TYPE(v)) + +#define BIT_SHIFT_RPT_COUNTER 0 +#define BIT_MASK_RPT_COUNTER 0xffff +#define BIT_RPT_COUNTER(x) \ + (((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER) +#define BITS_RPT_COUNTER (BIT_MASK_RPT_COUNTER << BIT_SHIFT_RPT_COUNTER) +#define BIT_CLEAR_RPT_COUNTER(x) ((x) & (~BITS_RPT_COUNTER)) +#define BIT_GET_RPT_COUNTER(x) \ + (((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER) +#define BIT_SET_RPT_COUNTER(x, v) \ + (BIT_CLEAR_RPT_COUNTER(x) | BIT_RPT_COUNTER(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_RXBA_IGNOREA2 BIT(42) +#define BIT_EN_SAVE_ALL_TXOPADDR BIT(41) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV BIT(40) -#define BIT_SHIFT_ACKBA_TYPSEL (60 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBA_TYPSEL 0xf -#define BIT_ACKBA_TYPSEL(x) (((x) & BIT_MASK_ACKBA_TYPSEL) << BIT_SHIFT_ACKBA_TYPSEL) -#define BIT_GET_ACKBA_TYPSEL(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL) & BIT_MASK_ACKBA_TYPSEL) - - -#define BIT_SHIFT_ACKBA_ACKPCHK (56 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBA_ACKPCHK 0xf -#define BIT_ACKBA_ACKPCHK(x) (((x) & BIT_MASK_ACKBA_ACKPCHK) << BIT_SHIFT_ACKBA_ACKPCHK) -#define BIT_GET_ACKBA_ACKPCHK(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK) & BIT_MASK_ACKBA_ACKPCHK) - - -#define BIT_SHIFT_ACKBAR_TYPESEL (48 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBAR_TYPESEL 0xff -#define BIT_ACKBAR_TYPESEL(x) (((x) & BIT_MASK_ACKBAR_TYPESEL) << BIT_SHIFT_ACKBAR_TYPESEL) -#define BIT_GET_ACKBAR_TYPESEL(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL) & BIT_MASK_ACKBAR_TYPESEL) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_ACKBAR_ACKPCHK (44 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBAR_ACKPCHK 0xf -#define BIT_ACKBAR_ACKPCHK(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK) << BIT_SHIFT_ACKBAR_ACKPCHK) -#define BIT_GET_ACKBAR_ACKPCHK(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK) & BIT_MASK_ACKBAR_ACKPCHK) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_DIS_TXBA_AMPDUFCSERR BIT(39) +#define BIT_DIS_TXBA_RXBARINFULL BIT(38) +#define BIT_DIS_TXCFE_INFULL BIT(37) +#define BIT_DIS_TXCTS_INFULL BIT(36) +#define BIT_EN_TXACKBA_IN_TX_RDG BIT(35) +#define BIT_EN_TXACKBA_IN_TXOP BIT(34) +#define BIT_EN_TXCTS_IN_RXNAV BIT(33) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ -#define BIT_RXBA_IGNOREA2 BIT(42) -#define BIT_EN_SAVE_ALL_TXOPADDR BIT(41) -#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV BIT(40) +#define BIT_EN_TXCTS_INTXOP BIT(32) +#define BIT_BLK_EDCA_BBSLP BIT(31) +#define BIT_BLK_EDCA_BBSBY BIT(30) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ -#define BIT_DIS_TXBA_AMPDUFCSERR BIT(39) -#define BIT_DIS_TXBA_RXBARINFULL BIT(38) -#define BIT_DIS_TXCFE_INFULL BIT(37) -#define BIT_DIS_TXCTS_INFULL BIT(36) -#define BIT_EN_TXACKBA_IN_TX_RDG BIT(35) -#define BIT_EN_TXACKBA_IN_TXOP BIT(34) -#define BIT_EN_TXCTS_IN_RXNAV BIT(33) -#define BIT_EN_TXCTS_INTXOP BIT(32) -#define BIT_BLK_EDCA_BBSLP BIT(31) -#define BIT_BLK_EDCA_BBSBY BIT(30) -#define BIT_ACKTO_BLOCK_SCH_EN BIT(27) -#define BIT_EIFS_BLOCK_SCH_EN BIT(26) -#define BIT_PLCPCHK_RST_EIFS BIT(25) -#define BIT_CCA_RST_EIFS BIT(24) -#define BIT_DIS_UPD_MYRXPKTNAV BIT(23) -#define BIT_EARLY_TXBA BIT(22) +#define BIT_ACKTO_BLOCK_SCH_EN BIT(27) +#define BIT_EIFS_BLOCK_SCH_EN BIT(26) +#define BIT_PLCPCHK_RST_EIFS BIT(25) +#define BIT_CCA_RST_EIFS BIT(24) +#define BIT_DIS_UPD_MYRXPKTNAV BIT(23) +#define BIT_EARLY_TXBA BIT(22) -#define BIT_SHIFT_RESP_CHNBUSY 20 -#define BIT_MASK_RESP_CHNBUSY 0x3 -#define BIT_RESP_CHNBUSY(x) (((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY) -#define BIT_GET_RESP_CHNBUSY(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY) +#define BIT_SHIFT_RESP_CHNBUSY 20 +#define BIT_MASK_RESP_CHNBUSY 0x3 +#define BIT_RESP_CHNBUSY(x) \ + (((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY) +#define BITS_RESP_CHNBUSY (BIT_MASK_RESP_CHNBUSY << BIT_SHIFT_RESP_CHNBUSY) +#define BIT_CLEAR_RESP_CHNBUSY(x) ((x) & (~BITS_RESP_CHNBUSY)) +#define BIT_GET_RESP_CHNBUSY(x) \ + (((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY) +#define BIT_SET_RESP_CHNBUSY(x, v) \ + (BIT_CLEAR_RESP_CHNBUSY(x) | BIT_RESP_CHNBUSY(v)) -#define BIT_RESP_DCTS_EN BIT(19) -#define BIT_RESP_DCFE_EN BIT(18) -#define BIT_RESP_SPLCPEN BIT(17) -#define BIT_RESP_SGIEN BIT(16) +#define BIT_RESP_DCTS_EN BIT(19) +#define BIT_RESP_DCFE_EN BIT(18) +#define BIT_RESP_SPLCPEN BIT(17) +#define BIT_RESP_SGIEN BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ -#define BIT_RESP_LDPC_EN BIT(15) -#define BIT_DIS_RESP_ACKINCCA BIT(14) -#define BIT_DIS_RESP_CTSINCCA BIT(13) +#define BIT_RESP_LDPC_EN BIT(15) +#define BIT_DIS_RESP_ACKINCCA BIT(14) +#define BIT_DIS_RESP_CTSINCCA BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ - -#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER 10 -#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER 0x7 -#define BIT_R_WMAC_SECOND_CCA_TIMER(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) -#define BIT_GET_R_WMAC_SECOND_CCA_TIMER(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER) - +#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER 10 +#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER 0x7 +#define BIT_R_WMAC_SECOND_CCA_TIMER(x) \ + (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER) \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) +#define BITS_R_WMAC_SECOND_CCA_TIMER \ + (BIT_MASK_R_WMAC_SECOND_CCA_TIMER << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER(x) \ + ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) & \ + BIT_MASK_R_WMAC_SECOND_CCA_TIMER) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER(x, v) \ + (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER(x) | BIT_R_WMAC_SECOND_CCA_TIMER(v)) #endif - #if (HALMAC_8814AMP_SUPPORT) - /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ - -#define BIT_SHIFT_SECOND_CCA_CNT 10 -#define BIT_MASK_SECOND_CCA_CNT 0x7 -#define BIT_SECOND_CCA_CNT(x) (((x) & BIT_MASK_SECOND_CCA_CNT) << BIT_SHIFT_SECOND_CCA_CNT) -#define BIT_GET_SECOND_CCA_CNT(x) (((x) >> BIT_SHIFT_SECOND_CCA_CNT) & BIT_MASK_SECOND_CCA_CNT) - +#define BIT_SHIFT_SECOND_CCA_CNT 10 +#define BIT_MASK_SECOND_CCA_CNT 0x7 +#define BIT_SECOND_CCA_CNT(x) \ + (((x) & BIT_MASK_SECOND_CCA_CNT) << BIT_SHIFT_SECOND_CCA_CNT) +#define BITS_SECOND_CCA_CNT \ + (BIT_MASK_SECOND_CCA_CNT << BIT_SHIFT_SECOND_CCA_CNT) +#define BIT_CLEAR_SECOND_CCA_CNT(x) ((x) & (~BITS_SECOND_CCA_CNT)) +#define BIT_GET_SECOND_CCA_CNT(x) \ + (((x) >> BIT_SHIFT_SECOND_CCA_CNT) & BIT_MASK_SECOND_CCA_CNT) +#define BIT_SET_SECOND_CCA_CNT(x, v) \ + (BIT_CLEAR_SECOND_CCA_CNT(x) | BIT_SECOND_CCA_CNT(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ - -#define BIT_SHIFT_RFMOD 7 -#define BIT_MASK_RFMOD 0x3 -#define BIT_RFMOD(x) (((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD) -#define BIT_GET_RFMOD(x) (((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD) - +#define BIT_SHIFT_RFMOD 7 +#define BIT_MASK_RFMOD 0x3 +#define BIT_RFMOD(x) (((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD) +#define BITS_RFMOD (BIT_MASK_RFMOD << BIT_SHIFT_RFMOD) +#define BIT_CLEAR_RFMOD(x) ((x) & (~BITS_RFMOD)) +#define BIT_GET_RFMOD(x) (((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD) +#define BIT_SET_RFMOD(x, v) (BIT_CLEAR_RFMOD(x) | BIT_RFMOD(v)) #endif - #if (HALMAC_8814AMP_SUPPORT) - /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ - -#define BIT_SHIFT_RF_MOD 7 -#define BIT_MASK_RF_MOD 0x3 -#define BIT_RF_MOD(x) (((x) & BIT_MASK_RF_MOD) << BIT_SHIFT_RF_MOD) -#define BIT_GET_RF_MOD(x) (((x) >> BIT_SHIFT_RF_MOD) & BIT_MASK_RF_MOD) - +#define BIT_SHIFT_RF_MOD 7 +#define BIT_MASK_RF_MOD 0x3 +#define BIT_RF_MOD(x) (((x) & BIT_MASK_RF_MOD) << BIT_SHIFT_RF_MOD) +#define BITS_RF_MOD (BIT_MASK_RF_MOD << BIT_SHIFT_RF_MOD) +#define BIT_CLEAR_RF_MOD(x) ((x) & (~BITS_RF_MOD)) +#define BIT_GET_RF_MOD(x) (((x) >> BIT_SHIFT_RF_MOD) & BIT_MASK_RF_MOD) +#define BIT_SET_RF_MOD(x, v) (BIT_CLEAR_RF_MOD(x) | BIT_RF_MOD(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ - -#define BIT_SHIFT_RESP_CTS_DYNBW_SEL 5 -#define BIT_MASK_RESP_CTS_DYNBW_SEL 0x3 -#define BIT_RESP_CTS_DYNBW_SEL(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL) -#define BIT_GET_RESP_CTS_DYNBW_SEL(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL) - +#define BIT_SHIFT_RESP_CTS_DYNBW_SEL 5 +#define BIT_MASK_RESP_CTS_DYNBW_SEL 0x3 +#define BIT_RESP_CTS_DYNBW_SEL(x) \ + (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL) +#define BITS_RESP_CTS_DYNBW_SEL \ + (BIT_MASK_RESP_CTS_DYNBW_SEL << BIT_SHIFT_RESP_CTS_DYNBW_SEL) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) ((x) & (~BITS_RESP_CTS_DYNBW_SEL)) +#define BIT_GET_RESP_CTS_DYNBW_SEL(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL) +#define BIT_SET_RESP_CTS_DYNBW_SEL(x, v) \ + (BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) | BIT_RESP_CTS_DYNBW_SEL(v)) #endif - #if (HALMAC_8814AMP_SUPPORT) - /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ - -#define BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL 5 -#define BIT_MASK_RESP_CTS_BW_DYNBW_SEL 0x3 -#define BIT_RESP_CTS_BW_DYNBW_SEL(x) (((x) & BIT_MASK_RESP_CTS_BW_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) -#define BIT_GET_RESP_CTS_BW_DYNBW_SEL(x) (((x) >> BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) & BIT_MASK_RESP_CTS_BW_DYNBW_SEL) - +#define BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL 5 +#define BIT_MASK_RESP_CTS_BW_DYNBW_SEL 0x3 +#define BIT_RESP_CTS_BW_DYNBW_SEL(x) \ + (((x) & BIT_MASK_RESP_CTS_BW_DYNBW_SEL) \ + << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) +#define BITS_RESP_CTS_BW_DYNBW_SEL \ + (BIT_MASK_RESP_CTS_BW_DYNBW_SEL << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) +#define BIT_CLEAR_RESP_CTS_BW_DYNBW_SEL(x) ((x) & (~BITS_RESP_CTS_BW_DYNBW_SEL)) +#define BIT_GET_RESP_CTS_BW_DYNBW_SEL(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) & \ + BIT_MASK_RESP_CTS_BW_DYNBW_SEL) +#define BIT_SET_RESP_CTS_BW_DYNBW_SEL(x, v) \ + (BIT_CLEAR_RESP_CTS_BW_DYNBW_SEL(x) | BIT_RESP_CTS_BW_DYNBW_SEL(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ -#define BIT_DLY_TX_WAIT_RXANTSEL BIT(4) +#define BIT_DLY_TX_WAIT_RXANTSEL BIT(4) #endif - #if (HALMAC_8814AMP_SUPPORT) - /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ -#define BIT_DELAY_TX_USE_RX_ANTSEL BIT(4) +#define BIT_DELAY_TX_USE_RX_ANTSEL BIT(4) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ -#define BIT_TXRESP_BY_RXANTSEL BIT(3) +#define BIT_TXRESP_BY_RXANTSEL BIT(3) #endif - #if (HALMAC_8814AMP_SUPPORT) - /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ -#define BIT_TX_USE_RX_ANTSEL BIT(3) +#define BIT_TX_USE_RX_ANTSEL BIT(3) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ -#define BIT_RESP_EARLY_TXACK_RWEPTKIP BIT(2) +#define BIT_RESP_EARLY_TXACK_RWEPTKIP BIT(2) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_SHIFT_ORIG_DCTS_CHK 0 +#define BIT_MASK_ORIG_DCTS_CHK 0x3 +#define BIT_ORIG_DCTS_CHK(x) \ + (((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK) +#define BITS_ORIG_DCTS_CHK (BIT_MASK_ORIG_DCTS_CHK << BIT_SHIFT_ORIG_DCTS_CHK) +#define BIT_CLEAR_ORIG_DCTS_CHK(x) ((x) & (~BITS_ORIG_DCTS_CHK)) +#define BIT_GET_ORIG_DCTS_CHK(x) \ + (((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK) +#define BIT_SET_ORIG_DCTS_CHK(x, v) \ + (BIT_CLEAR_ORIG_DCTS_CHK(x) | BIT_ORIG_DCTS_CHK(v)) -#define BIT_SHIFT_ORIG_DCTS_CHK 0 -#define BIT_MASK_ORIG_DCTS_CHK 0x3 -#define BIT_ORIG_DCTS_CHK(x) (((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK) -#define BIT_GET_ORIG_DCTS_CHK(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_WMAC_TRXPTCL_CTL_H (Offset 0x066C) */ +#define BIT_RPT_VALID BIT(13) +#define BIT_RXBA_IGNOREA2_V1 BIT(10) +#define BIT_EN_SAVE_ALL_TXOPADDR_V1 BIT(9) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1 BIT(8) +#define BIT_DIS_TXBA_AMPDUFCSERR_V1 BIT(7) +#define BIT_DIS_TXBA_RXBARINFULL_V1 BIT(6) +#define BIT_DIS_TXCFE_INFULL_V1 BIT(5) +#define BIT_DIS_TXCTS_INFULL_V1 BIT(4) +#define BIT_EN_TXACKBA_IN_TX_RDG_V1 BIT(3) +#define BIT_EN_TXACKBA_IN_TXOP_V1 BIT(2) +#define BIT_EN_TXCTS_IN_RXNAV_V1 BIT(1) +#define BIT_EN_TXCTS_INTXOP_V1 BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CAMCMD (Offset 0x0670) */ -#define BIT_SECCAM_POLLING BIT(31) -#define BIT_SECCAM_CLR BIT(30) -#define BIT_MFBCAM_CLR BIT(29) +#define BIT_SECCAM_POLLING BIT(31) +#define BIT_SECCAM_CLR BIT(30) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_CAMCMD (Offset 0x0670) */ -#define BIT_SECCAM_WE BIT(16) +#define BIT_MFBCAM_CLR BIT(29) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_CAMCMD (Offset 0x0670) */ +#define BIT_SECCAM_WE BIT(16) + +#endif -#define BIT_SHIFT_SECCAM_ADDR_V1 0 -#define BIT_MASK_SECCAM_ADDR_V1 0xff -#define BIT_SECCAM_ADDR_V1(x) (((x) & BIT_MASK_SECCAM_ADDR_V1) << BIT_SHIFT_SECCAM_ADDR_V1) -#define BIT_GET_SECCAM_ADDR_V1(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V1) & BIT_MASK_SECCAM_ADDR_V1) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CAMCMD (Offset 0x0670) */ -#define BIT_SHIFT_WKFCAM_NUM 0 -#define BIT_MASK_WKFCAM_NUM 0x7f -#define BIT_WKFCAM_NUM(x) (((x) & BIT_MASK_WKFCAM_NUM) << BIT_SHIFT_WKFCAM_NUM) -#define BIT_GET_WKFCAM_NUM(x) (((x) >> BIT_SHIFT_WKFCAM_NUM) & BIT_MASK_WKFCAM_NUM) +#define BIT_SHIFT_SECCAM_ADDR_V1 0 +#define BIT_MASK_SECCAM_ADDR_V1 0xff +#define BIT_SECCAM_ADDR_V1(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V1) << BIT_SHIFT_SECCAM_ADDR_V1) +#define BITS_SECCAM_ADDR_V1 \ + (BIT_MASK_SECCAM_ADDR_V1 << BIT_SHIFT_SECCAM_ADDR_V1) +#define BIT_CLEAR_SECCAM_ADDR_V1(x) ((x) & (~BITS_SECCAM_ADDR_V1)) +#define BIT_GET_SECCAM_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V1) & BIT_MASK_SECCAM_ADDR_V1) +#define BIT_SET_SECCAM_ADDR_V1(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V1(x) | BIT_SECCAM_ADDR_V1(v)) +#define BIT_SHIFT_WKFCAM_NUM 0 +#define BIT_MASK_WKFCAM_NUM 0x7f +#define BIT_WKFCAM_NUM(x) (((x) & BIT_MASK_WKFCAM_NUM) << BIT_SHIFT_WKFCAM_NUM) +#define BITS_WKFCAM_NUM (BIT_MASK_WKFCAM_NUM << BIT_SHIFT_WKFCAM_NUM) +#define BIT_CLEAR_WKFCAM_NUM(x) ((x) & (~BITS_WKFCAM_NUM)) +#define BIT_GET_WKFCAM_NUM(x) \ + (((x) >> BIT_SHIFT_WKFCAM_NUM) & BIT_MASK_WKFCAM_NUM) +#define BIT_SET_WKFCAM_NUM(x, v) (BIT_CLEAR_WKFCAM_NUM(x) | BIT_WKFCAM_NUM(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CAMCMD (Offset 0x0670) */ +#define BIT_SHIFT_SECCAM_ADDR_V2 0 +#define BIT_MASK_SECCAM_ADDR_V2 0x3ff +#define BIT_SECCAM_ADDR_V2(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V2) << BIT_SHIFT_SECCAM_ADDR_V2) +#define BITS_SECCAM_ADDR_V2 \ + (BIT_MASK_SECCAM_ADDR_V2 << BIT_SHIFT_SECCAM_ADDR_V2) +#define BIT_CLEAR_SECCAM_ADDR_V2(x) ((x) & (~BITS_SECCAM_ADDR_V2)) +#define BIT_GET_SECCAM_ADDR_V2(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V2) & BIT_MASK_SECCAM_ADDR_V2) +#define BIT_SET_SECCAM_ADDR_V2(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V2(x) | BIT_SECCAM_ADDR_V2(v)) -/* 2 REG_CAMCMD (Offset 0x0670) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_SECCAM_ADDR_V2 0 -#define BIT_MASK_SECCAM_ADDR_V2 0x3ff -#define BIT_SECCAM_ADDR_V2(x) (((x) & BIT_MASK_SECCAM_ADDR_V2) << BIT_SHIFT_SECCAM_ADDR_V2) -#define BIT_GET_SECCAM_ADDR_V2(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2) & BIT_MASK_SECCAM_ADDR_V2) +/* 2 REG_CAMCMD (Offset 0x0670) */ +#define BIT_SHIFT_SECCAM_ADDR 0 +#define BIT_MASK_SECCAM_ADDR 0xff +#define BIT_SECCAM_ADDR(x) \ + (((x) & BIT_MASK_SECCAM_ADDR) << BIT_SHIFT_SECCAM_ADDR) +#define BITS_SECCAM_ADDR (BIT_MASK_SECCAM_ADDR << BIT_SHIFT_SECCAM_ADDR) +#define BIT_CLEAR_SECCAM_ADDR(x) ((x) & (~BITS_SECCAM_ADDR)) +#define BIT_GET_SECCAM_ADDR(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR) & BIT_MASK_SECCAM_ADDR) +#define BIT_SET_SECCAM_ADDR(x, v) \ + (BIT_CLEAR_SECCAM_ADDR(x) | BIT_SECCAM_ADDR(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_CAMWRITE (Offset 0x0674) */ +#define BIT_SHIFT_CAMW_DATA 0 +#define BIT_MASK_CAMW_DATA 0xffffffffL +#define BIT_CAMW_DATA(x) (((x) & BIT_MASK_CAMW_DATA) << BIT_SHIFT_CAMW_DATA) +#define BITS_CAMW_DATA (BIT_MASK_CAMW_DATA << BIT_SHIFT_CAMW_DATA) +#define BIT_CLEAR_CAMW_DATA(x) ((x) & (~BITS_CAMW_DATA)) +#define BIT_GET_CAMW_DATA(x) (((x) >> BIT_SHIFT_CAMW_DATA) & BIT_MASK_CAMW_DATA) +#define BIT_SET_CAMW_DATA(x, v) (BIT_CLEAR_CAMW_DATA(x) | BIT_CAMW_DATA(v)) -/* 2 REG_CAMCMD (Offset 0x0670) */ +/* 2 REG_CAMREAD (Offset 0x0678) */ +#define BIT_SHIFT_CAMR_DATA 0 +#define BIT_MASK_CAMR_DATA 0xffffffffL +#define BIT_CAMR_DATA(x) (((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA) +#define BITS_CAMR_DATA (BIT_MASK_CAMR_DATA << BIT_SHIFT_CAMR_DATA) +#define BIT_CLEAR_CAMR_DATA(x) ((x) & (~BITS_CAMR_DATA)) +#define BIT_GET_CAMR_DATA(x) (((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA) +#define BIT_SET_CAMR_DATA(x, v) (BIT_CLEAR_CAMR_DATA(x) | BIT_CAMR_DATA(v)) -#define BIT_SHIFT_SECCAM_ADDR 0 -#define BIT_MASK_SECCAM_ADDR 0xff -#define BIT_SECCAM_ADDR(x) (((x) & BIT_MASK_SECCAM_ADDR) << BIT_SHIFT_SECCAM_ADDR) -#define BIT_GET_SECCAM_ADDR(x) (((x) >> BIT_SHIFT_SECCAM_ADDR) & BIT_MASK_SECCAM_ADDR) +/* 2 REG_CAMDBG (Offset 0x067C) */ +#define BIT_SECCAM_INFO BIT(31) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_CAMDBG (Offset 0x067C) */ -/* 2 REG_CAMWRITE (Offset 0x0674) */ +#define BIT_SEC_KEYFOUND_V1 BIT(19) +#define BIT_SHIFT_CAMDBG_SEC_TYPE_V1 16 +#define BIT_MASK_CAMDBG_SEC_TYPE_V1 0x7 +#define BIT_CAMDBG_SEC_TYPE_V1(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE_V1) << BIT_SHIFT_CAMDBG_SEC_TYPE_V1) +#define BITS_CAMDBG_SEC_TYPE_V1 \ + (BIT_MASK_CAMDBG_SEC_TYPE_V1 << BIT_SHIFT_CAMDBG_SEC_TYPE_V1) +#define BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_V1)) +#define BIT_GET_CAMDBG_SEC_TYPE_V1(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_V1) & BIT_MASK_CAMDBG_SEC_TYPE_V1) +#define BIT_SET_CAMDBG_SEC_TYPE_V1(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) | BIT_CAMDBG_SEC_TYPE_V1(v)) -#define BIT_SHIFT_CAMW_DATA 0 -#define BIT_MASK_CAMW_DATA 0xffffffffL -#define BIT_CAMW_DATA(x) (((x) & BIT_MASK_CAMW_DATA) << BIT_SHIFT_CAMW_DATA) -#define BIT_GET_CAMW_DATA(x) (((x) >> BIT_SHIFT_CAMW_DATA) & BIT_MASK_CAMW_DATA) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_CAMREAD (Offset 0x0678) */ +/* 2 REG_CAMDBG (Offset 0x067C) */ +#define BIT_SEC_KEYFOUND BIT(15) -#define BIT_SHIFT_CAMR_DATA 0 -#define BIT_MASK_CAMR_DATA 0xffffffffL -#define BIT_CAMR_DATA(x) (((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA) -#define BIT_GET_CAMR_DATA(x) (((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA) +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ -#define BIT_SECCAM_INFO BIT(31) -#define BIT_SEC_KEYFOUND BIT(15) +#define BIT_CAMDBG_EXT_SEC_TYPE_V1 BIT(15) -#define BIT_SHIFT_CAMDBG_SEC_TYPE 12 -#define BIT_MASK_CAMDBG_SEC_TYPE 0x7 -#define BIT_CAMDBG_SEC_TYPE(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE) << BIT_SHIFT_CAMDBG_SEC_TYPE) -#define BIT_GET_CAMDBG_SEC_TYPE(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE) & BIT_MASK_CAMDBG_SEC_TYPE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_CAMDBG (Offset 0x067C) */ +#define BIT_SHIFT_CAMDBG_SEC_TYPE 12 +#define BIT_MASK_CAMDBG_SEC_TYPE 0x7 +#define BIT_CAMDBG_SEC_TYPE(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE) << BIT_SHIFT_CAMDBG_SEC_TYPE) +#define BITS_CAMDBG_SEC_TYPE \ + (BIT_MASK_CAMDBG_SEC_TYPE << BIT_SHIFT_CAMDBG_SEC_TYPE) +#define BIT_CLEAR_CAMDBG_SEC_TYPE(x) ((x) & (~BITS_CAMDBG_SEC_TYPE)) +#define BIT_GET_CAMDBG_SEC_TYPE(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE) & BIT_MASK_CAMDBG_SEC_TYPE) +#define BIT_SET_CAMDBG_SEC_TYPE(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE(x) | BIT_CAMDBG_SEC_TYPE(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ -#define BIT_CAMDBG_EXT_SEC_TYPE BIT(11) +#define BIT_CAMDBG_EXT_SEC_TYPE BIT(11) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ -#define BIT_CAMDBG_EXT_SECTYPE BIT(11) +#define BIT_CAMDBG_EXT_SECTYPE BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ +#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1 7 +#define BIT_MASK_CAMDBG_MIC_KEY_IDX_V1 0x7f +#define BIT_CAMDBG_MIC_KEY_IDX_V1(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_V1) \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1) +#define BITS_CAMDBG_MIC_KEY_IDX_V1 \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX_V1 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V1(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_V1)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_V1(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1) & \ + BIT_MASK_CAMDBG_MIC_KEY_IDX_V1) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_V1(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V1(x) | BIT_CAMDBG_MIC_KEY_IDX_V1(v)) -#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX 5 -#define BIT_MASK_CAMDBG_MIC_KEY_IDX 0x1f -#define BIT_CAMDBG_MIC_KEY_IDX(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX) -#define BIT_GET_CAMDBG_MIC_KEY_IDX(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX) & BIT_MASK_CAMDBG_MIC_KEY_IDX) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX 0 -#define BIT_MASK_CAMDBG_SEC_KEY_IDX 0x1f -#define BIT_CAMDBG_SEC_KEY_IDX(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX) -#define BIT_GET_CAMDBG_SEC_KEY_IDX(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX) & BIT_MASK_CAMDBG_SEC_KEY_IDX) +/* 2 REG_CAMDBG (Offset 0x067C) */ +#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX 5 +#define BIT_MASK_CAMDBG_MIC_KEY_IDX 0x1f +#define BIT_CAMDBG_MIC_KEY_IDX(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX) +#define BITS_CAMDBG_MIC_KEY_IDX \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX << BIT_SHIFT_CAMDBG_MIC_KEY_IDX) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX) & BIT_MASK_CAMDBG_MIC_KEY_IDX) +#define BIT_SET_CAMDBG_MIC_KEY_IDX(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX(x) | BIT_CAMDBG_MIC_KEY_IDX(v)) + +#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX 0 +#define BIT_MASK_CAMDBG_SEC_KEY_IDX 0x1f +#define BIT_CAMDBG_SEC_KEY_IDX(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX) +#define BITS_CAMDBG_SEC_KEY_IDX \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX << BIT_SHIFT_CAMDBG_SEC_KEY_IDX) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX) & BIT_MASK_CAMDBG_SEC_KEY_IDX) +#define BIT_SET_CAMDBG_SEC_KEY_IDX(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX(x) | BIT_CAMDBG_SEC_KEY_IDX(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_SECCFG (Offset 0x0680) */ +/* 2 REG_CAMDBG (Offset 0x067C) */ -#define BIT_DIS_GCLK_WAPI BIT(15) -#define BIT_DIS_GCLK_AES BIT(14) -#define BIT_DIS_GCLK_TKIP BIT(13) +#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1 0 +#define BIT_MASK_CAMDBG_SEC_KEY_IDX_V1 0x7f +#define BIT_CAMDBG_SEC_KEY_IDX_V1(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_V1) \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1) +#define BITS_CAMDBG_SEC_KEY_IDX_V1 \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX_V1 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V1(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_V1)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_V1(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1) & \ + BIT_MASK_CAMDBG_SEC_KEY_IDX_V1) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_V1(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V1(x) | BIT_CAMDBG_SEC_KEY_IDX_V1(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SECCFG (Offset 0x0680) */ -#define BIT_AES_SEL_QC_1 BIT(12) -#define BIT_AES_SEL_QC_0 BIT(11) +#define BIT_DIS_GCLK_WAPI BIT(15) +#define BIT_DIS_GCLK_AES BIT(14) +#define BIT_DIS_GCLK_TKIP BIT(13) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SECCFG (Offset 0x0680) */ -#define BIT_WMAC_CKECK_BMC BIT(9) +#define BIT_AES_SEL_QC_1 BIT(12) +#define BIT_AES_SEL_QC_0 BIT(11) #endif - -#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_SECCFG (Offset 0x0680) */ -#define BIT_CHK_BMC BIT(9) +#define BIT_WMAC_CKECK_BMC BIT(9) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SECCFG (Offset 0x0680) */ -#define BIT_CHK_KEYID BIT(8) -#define BIT_RXBCUSEDK BIT(7) -#define BIT_TXBCUSEDK BIT(6) -#define BIT_NOSKMC BIT(5) -#define BIT_SKBYA2 BIT(4) -#define BIT_RXDEC BIT(3) -#define BIT_TXENC BIT(2) -#define BIT_RXUHUSEDK BIT(1) -#define BIT_TXUHUSEDK BIT(0) +#define BIT_CHK_BMC BIT(9) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SECCFG (Offset 0x0680) */ +#define BIT_CHK_KEYID BIT(8) +#define BIT_RXBCUSEDK BIT(7) +#define BIT_TXBCUSEDK BIT(6) +#define BIT_NOSKMC BIT(5) +#define BIT_SKBYA2 BIT(4) +#define BIT_RXDEC BIT(3) +#define BIT_TXENC BIT(2) +#define BIT_RXUHUSEDK BIT(1) +#define BIT_TXUHUSEDK BIT(0) -/* 2 REG_RXFILTER_CATEGORY_1 (Offset 0x0682) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXFILTER_CATEGORY_1 0 -#define BIT_MASK_RXFILTER_CATEGORY_1 0xff -#define BIT_RXFILTER_CATEGORY_1(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1) -#define BIT_GET_RXFILTER_CATEGORY_1(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1) +/* 2 REG_RXFILTER_CATEGORY_1 (Offset 0x0682) */ +#define BIT_SHIFT_RXFILTER_CATEGORY_1 0 +#define BIT_MASK_RXFILTER_CATEGORY_1 0xff +#define BIT_RXFILTER_CATEGORY_1(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1) +#define BITS_RXFILTER_CATEGORY_1 \ + (BIT_MASK_RXFILTER_CATEGORY_1 << BIT_SHIFT_RXFILTER_CATEGORY_1) +#define BIT_CLEAR_RXFILTER_CATEGORY_1(x) ((x) & (~BITS_RXFILTER_CATEGORY_1)) +#define BIT_GET_RXFILTER_CATEGORY_1(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1) +#define BIT_SET_RXFILTER_CATEGORY_1(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_1(x) | BIT_RXFILTER_CATEGORY_1(v)) /* 2 REG_RXFILTER_ACTION_1 (Offset 0x0683) */ - -#define BIT_SHIFT_RXFILTER_ACTION_1 0 -#define BIT_MASK_RXFILTER_ACTION_1 0xff -#define BIT_RXFILTER_ACTION_1(x) (((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1) -#define BIT_GET_RXFILTER_ACTION_1(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1) - +#define BIT_SHIFT_RXFILTER_ACTION_1 0 +#define BIT_MASK_RXFILTER_ACTION_1 0xff +#define BIT_RXFILTER_ACTION_1(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1) +#define BITS_RXFILTER_ACTION_1 \ + (BIT_MASK_RXFILTER_ACTION_1 << BIT_SHIFT_RXFILTER_ACTION_1) +#define BIT_CLEAR_RXFILTER_ACTION_1(x) ((x) & (~BITS_RXFILTER_ACTION_1)) +#define BIT_GET_RXFILTER_ACTION_1(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1) +#define BIT_SET_RXFILTER_ACTION_1(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_1(x) | BIT_RXFILTER_ACTION_1(v)) /* 2 REG_RXFILTER_CATEGORY_2 (Offset 0x0684) */ - -#define BIT_SHIFT_RXFILTER_CATEGORY_2 0 -#define BIT_MASK_RXFILTER_CATEGORY_2 0xff -#define BIT_RXFILTER_CATEGORY_2(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2) -#define BIT_GET_RXFILTER_CATEGORY_2(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2) - +#define BIT_SHIFT_RXFILTER_CATEGORY_2 0 +#define BIT_MASK_RXFILTER_CATEGORY_2 0xff +#define BIT_RXFILTER_CATEGORY_2(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2) +#define BITS_RXFILTER_CATEGORY_2 \ + (BIT_MASK_RXFILTER_CATEGORY_2 << BIT_SHIFT_RXFILTER_CATEGORY_2) +#define BIT_CLEAR_RXFILTER_CATEGORY_2(x) ((x) & (~BITS_RXFILTER_CATEGORY_2)) +#define BIT_GET_RXFILTER_CATEGORY_2(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2) +#define BIT_SET_RXFILTER_CATEGORY_2(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_2(x) | BIT_RXFILTER_CATEGORY_2(v)) /* 2 REG_RXFILTER_ACTION_2 (Offset 0x0685) */ - -#define BIT_SHIFT_RXFILTER_ACTION_2 0 -#define BIT_MASK_RXFILTER_ACTION_2 0xff -#define BIT_RXFILTER_ACTION_2(x) (((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2) -#define BIT_GET_RXFILTER_ACTION_2(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2) - +#define BIT_SHIFT_RXFILTER_ACTION_2 0 +#define BIT_MASK_RXFILTER_ACTION_2 0xff +#define BIT_RXFILTER_ACTION_2(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2) +#define BITS_RXFILTER_ACTION_2 \ + (BIT_MASK_RXFILTER_ACTION_2 << BIT_SHIFT_RXFILTER_ACTION_2) +#define BIT_CLEAR_RXFILTER_ACTION_2(x) ((x) & (~BITS_RXFILTER_ACTION_2)) +#define BIT_GET_RXFILTER_ACTION_2(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2) +#define BIT_SET_RXFILTER_ACTION_2(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_2(x) | BIT_RXFILTER_ACTION_2(v)) /* 2 REG_RXFILTER_CATEGORY_3 (Offset 0x0686) */ - -#define BIT_SHIFT_RXFILTER_CATEGORY_3 0 -#define BIT_MASK_RXFILTER_CATEGORY_3 0xff -#define BIT_RXFILTER_CATEGORY_3(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3) -#define BIT_GET_RXFILTER_CATEGORY_3(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3) - +#define BIT_SHIFT_RXFILTER_CATEGORY_3 0 +#define BIT_MASK_RXFILTER_CATEGORY_3 0xff +#define BIT_RXFILTER_CATEGORY_3(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3) +#define BITS_RXFILTER_CATEGORY_3 \ + (BIT_MASK_RXFILTER_CATEGORY_3 << BIT_SHIFT_RXFILTER_CATEGORY_3) +#define BIT_CLEAR_RXFILTER_CATEGORY_3(x) ((x) & (~BITS_RXFILTER_CATEGORY_3)) +#define BIT_GET_RXFILTER_CATEGORY_3(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3) +#define BIT_SET_RXFILTER_CATEGORY_3(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_3(x) | BIT_RXFILTER_CATEGORY_3(v)) /* 2 REG_RXFILTER_ACTION_3 (Offset 0x0687) */ - -#define BIT_SHIFT_RXFILTER_ACTION_3 0 -#define BIT_MASK_RXFILTER_ACTION_3 0xff -#define BIT_RXFILTER_ACTION_3(x) (((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3) -#define BIT_GET_RXFILTER_ACTION_3(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3) - +#define BIT_SHIFT_RXFILTER_ACTION_3 0 +#define BIT_MASK_RXFILTER_ACTION_3 0xff +#define BIT_RXFILTER_ACTION_3(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3) +#define BITS_RXFILTER_ACTION_3 \ + (BIT_MASK_RXFILTER_ACTION_3 << BIT_SHIFT_RXFILTER_ACTION_3) +#define BIT_CLEAR_RXFILTER_ACTION_3(x) ((x) & (~BITS_RXFILTER_ACTION_3)) +#define BIT_GET_RXFILTER_ACTION_3(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3) +#define BIT_SET_RXFILTER_ACTION_3(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_3(x) | BIT_RXFILTER_ACTION_3(v)) /* 2 REG_RXFLTMAP3 (Offset 0x0688) */ -#define BIT_MGTFLT15EN_FW BIT(15) -#define BIT_MGTFLT14EN_FW BIT(14) -#define BIT_MGTFLT13EN_FW BIT(13) -#define BIT_MGTFLT12EN_FW BIT(12) -#define BIT_MGTFLT11EN_FW BIT(11) -#define BIT_MGTFLT10EN_FW BIT(10) -#define BIT_MGTFLT9EN_FW BIT(9) -#define BIT_MGTFLT8EN_FW BIT(8) -#define BIT_MGTFLT7EN_FW BIT(7) -#define BIT_MGTFLT6EN_FW BIT(6) -#define BIT_MGTFLT5EN_FW BIT(5) -#define BIT_MGTFLT4EN_FW BIT(4) -#define BIT_MGTFLT3EN_FW BIT(3) -#define BIT_MGTFLT2EN_FW BIT(2) -#define BIT_MGTFLT1EN_FW BIT(1) -#define BIT_MGTFLT0EN_FW BIT(0) +#define BIT_MGTFLT15EN_FW BIT(15) +#define BIT_MGTFLT14EN_FW BIT(14) +#define BIT_MGTFLT13EN_FW BIT(13) +#define BIT_MGTFLT12EN_FW BIT(12) +#define BIT_MGTFLT11EN_FW BIT(11) +#define BIT_MGTFLT10EN_FW BIT(10) +#define BIT_MGTFLT9EN_FW BIT(9) +#define BIT_MGTFLT8EN_FW BIT(8) +#define BIT_MGTFLT7EN_FW BIT(7) +#define BIT_MGTFLT6EN_FW BIT(6) +#define BIT_MGTFLT5EN_FW BIT(5) +#define BIT_MGTFLT4EN_FW BIT(4) +#define BIT_MGTFLT3EN_FW BIT(3) +#define BIT_MGTFLT2EN_FW BIT(2) +#define BIT_MGTFLT1EN_FW BIT(1) +#define BIT_MGTFLT0EN_FW BIT(0) /* 2 REG_RXFLTMAP4 (Offset 0x068A) */ -#define BIT_CTRLFLT15EN_FW BIT(15) -#define BIT_CTRLFLT14EN_FW BIT(14) -#define BIT_CTRLFLT13EN_FW BIT(13) -#define BIT_CTRLFLT12EN_FW BIT(12) -#define BIT_CTRLFLT11EN_FW BIT(11) -#define BIT_CTRLFLT10EN_FW BIT(10) -#define BIT_CTRLFLT9EN_FW BIT(9) -#define BIT_CTRLFLT8EN_FW BIT(8) -#define BIT_CTRLFLT7EN_FW BIT(7) -#define BIT_CTRLFLT6EN_FW BIT(6) -#define BIT_CTRLFLT5EN_FW BIT(5) -#define BIT_CTRLFLT4EN_FW BIT(4) -#define BIT_CTRLFLT3EN_FW BIT(3) -#define BIT_CTRLFLT2EN_FW BIT(2) -#define BIT_CTRLFLT1EN_FW BIT(1) -#define BIT_CTRLFLT0EN_FW BIT(0) +#define BIT_CTRLFLT15EN_FW BIT(15) +#define BIT_CTRLFLT14EN_FW BIT(14) +#define BIT_CTRLFLT13EN_FW BIT(13) +#define BIT_CTRLFLT12EN_FW BIT(12) +#define BIT_CTRLFLT11EN_FW BIT(11) +#define BIT_CTRLFLT10EN_FW BIT(10) +#define BIT_CTRLFLT9EN_FW BIT(9) +#define BIT_CTRLFLT8EN_FW BIT(8) +#define BIT_CTRLFLT7EN_FW BIT(7) +#define BIT_CTRLFLT6EN_FW BIT(6) +#define BIT_CTRLFLT5EN_FW BIT(5) +#define BIT_CTRLFLT4EN_FW BIT(4) +#define BIT_CTRLFLT3EN_FW BIT(3) +#define BIT_CTRLFLT2EN_FW BIT(2) +#define BIT_CTRLFLT1EN_FW BIT(1) +#define BIT_CTRLFLT0EN_FW BIT(0) /* 2 REG_RXFLTMAP5 (Offset 0x068C) */ -#define BIT_DATAFLT15EN_FW BIT(15) -#define BIT_DATAFLT14EN_FW BIT(14) -#define BIT_DATAFLT13EN_FW BIT(13) -#define BIT_DATAFLT12EN_FW BIT(12) -#define BIT_DATAFLT11EN_FW BIT(11) -#define BIT_DATAFLT10EN_FW BIT(10) -#define BIT_DATAFLT9EN_FW BIT(9) -#define BIT_DATAFLT8EN_FW BIT(8) -#define BIT_DATAFLT7EN_FW BIT(7) -#define BIT_DATAFLT6EN_FW BIT(6) -#define BIT_DATAFLT5EN_FW BIT(5) -#define BIT_DATAFLT4EN_FW BIT(4) -#define BIT_DATAFLT3EN_FW BIT(3) -#define BIT_DATAFLT2EN_FW BIT(2) -#define BIT_DATAFLT1EN_FW BIT(1) -#define BIT_DATAFLT0EN_FW BIT(0) +#define BIT_DATAFLT15EN_FW BIT(15) +#define BIT_DATAFLT14EN_FW BIT(14) +#define BIT_DATAFLT13EN_FW BIT(13) +#define BIT_DATAFLT12EN_FW BIT(12) +#define BIT_DATAFLT11EN_FW BIT(11) +#define BIT_DATAFLT10EN_FW BIT(10) +#define BIT_DATAFLT9EN_FW BIT(9) +#define BIT_DATAFLT8EN_FW BIT(8) +#define BIT_DATAFLT7EN_FW BIT(7) +#define BIT_DATAFLT6EN_FW BIT(6) +#define BIT_DATAFLT5EN_FW BIT(5) +#define BIT_DATAFLT4EN_FW BIT(4) +#define BIT_DATAFLT3EN_FW BIT(3) +#define BIT_DATAFLT2EN_FW BIT(2) +#define BIT_DATAFLT1EN_FW BIT(1) +#define BIT_DATAFLT0EN_FW BIT(0) /* 2 REG_RXFLTMAP6 (Offset 0x068E) */ -#define BIT_ACTIONFLT15EN_FW BIT(15) -#define BIT_ACTIONFLT14EN_FW BIT(14) -#define BIT_ACTIONFLT13EN_FW BIT(13) -#define BIT_ACTIONFLT12EN_FW BIT(12) -#define BIT_ACTIONFLT11EN_FW BIT(11) -#define BIT_ACTIONFLT10EN_FW BIT(10) -#define BIT_ACTIONFLT9EN_FW BIT(9) -#define BIT_ACTIONFLT8EN_FW BIT(8) -#define BIT_ACTIONFLT7EN_FW BIT(7) -#define BIT_ACTIONFLT6EN_FW BIT(6) -#define BIT_ACTIONFLT5EN_FW BIT(5) -#define BIT_ACTIONFLT4EN_FW BIT(4) -#define BIT_ACTIONFLT3EN_FW BIT(3) -#define BIT_ACTIONFLT2EN_FW BIT(2) -#define BIT_ACTIONFLT1EN_FW BIT(1) -#define BIT_ACTIONFLT0EN_FW BIT(0) +#define BIT_ACTIONFLT15EN_FW BIT(15) +#define BIT_ACTIONFLT14EN_FW BIT(14) +#define BIT_ACTIONFLT13EN_FW BIT(13) +#define BIT_ACTIONFLT12EN_FW BIT(12) +#define BIT_ACTIONFLT11EN_FW BIT(11) +#define BIT_ACTIONFLT10EN_FW BIT(10) +#define BIT_ACTIONFLT9EN_FW BIT(9) +#define BIT_ACTIONFLT8EN_FW BIT(8) +#define BIT_ACTIONFLT7EN_FW BIT(7) +#define BIT_ACTIONFLT6EN_FW BIT(6) +#define BIT_ACTIONFLT5EN_FW BIT(5) +#define BIT_ACTIONFLT4EN_FW BIT(4) +#define BIT_ACTIONFLT3EN_FW BIT(3) +#define BIT_ACTIONFLT2EN_FW BIT(2) +#define BIT_ACTIONFLT1EN_FW BIT(1) +#define BIT_ACTIONFLT0EN_FW BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ +#define BIT_SHIFT_PSF_BSSIDSEL_B2B1 6 +#define BIT_MASK_PSF_BSSIDSEL_B2B1 0x3 +#define BIT_PSF_BSSIDSEL_B2B1(x) \ + (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1) << BIT_SHIFT_PSF_BSSIDSEL_B2B1) +#define BITS_PSF_BSSIDSEL_B2B1 \ + (BIT_MASK_PSF_BSSIDSEL_B2B1 << BIT_SHIFT_PSF_BSSIDSEL_B2B1) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1(x) ((x) & (~BITS_PSF_BSSIDSEL_B2B1)) +#define BIT_GET_PSF_BSSIDSEL_B2B1(x) \ + (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1) & BIT_MASK_PSF_BSSIDSEL_B2B1) +#define BIT_SET_PSF_BSSIDSEL_B2B1(x, v) \ + (BIT_CLEAR_PSF_BSSIDSEL_B2B1(x) | BIT_PSF_BSSIDSEL_B2B1(v)) -#define BIT_SHIFT_PSF_BSSIDSEL_B2B1 6 -#define BIT_MASK_PSF_BSSIDSEL_B2B1 0x3 -#define BIT_PSF_BSSIDSEL_B2B1(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1) << BIT_SHIFT_PSF_BSSIDSEL_B2B1) -#define BIT_GET_PSF_BSSIDSEL_B2B1(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1) & BIT_MASK_PSF_BSSIDSEL_B2B1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_WOW_CTRL (Offset 0x0690) */ +#define BIT_WOWHCI BIT(5) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ -#define BIT_WOWHCI BIT(5) +#define BIT_PSF_BSSIDSEL BIT(4) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ -#define BIT_PSF_BSSIDSEL BIT(4) +#define BIT_PSF_BSSIDSEL_B0 BIT(4) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ -#define BIT_PSF_BSSIDSEL_B0 BIT(4) +#define BIT_UWF BIT(3) +#define BIT_MAGIC BIT(2) +#define BIT_WOWEN BIT(1) +#define BIT_FORCE_WAKEUP BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_NAN_RX_TSF_FILTER (Offset 0x0691) */ +#define BIT_CHK_TSF_TA BIT(2) +#define BIT_CHK_TSF_CBSSID BIT(1) +#define BIT_CHK_TSF_EN BIT(0) -/* 2 REG_WOW_CTRL (Offset 0x0690) */ +/* 2 REG_PS_RX_INFO (Offset 0x0692) */ -#define BIT_UWF BIT(3) -#define BIT_MAGIC BIT(2) -#define BIT_WOWEN BIT(1) -#define BIT_FORCE_WAKEUP BIT(0) +#define BIT_SHIFT_PORTSEL__PS_RX_INFO 5 +#define BIT_MASK_PORTSEL__PS_RX_INFO 0x7 +#define BIT_PORTSEL__PS_RX_INFO(x) \ + (((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO) +#define BITS_PORTSEL__PS_RX_INFO \ + (BIT_MASK_PORTSEL__PS_RX_INFO << BIT_SHIFT_PORTSEL__PS_RX_INFO) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO(x) ((x) & (~BITS_PORTSEL__PS_RX_INFO)) +#define BIT_GET_PORTSEL__PS_RX_INFO(x) \ + (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO) +#define BIT_SET_PORTSEL__PS_RX_INFO(x, v) \ + (BIT_CLEAR_PORTSEL__PS_RX_INFO(x) | BIT_PORTSEL__PS_RX_INFO(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_NAN_RX_TSF_FILTER (Offset 0x0691) */ - -#define BIT_CHK_TSF_TA BIT(2) -#define BIT_CHK_TSF_CBSSID BIT(1) -#define BIT_CHK_TSF_EN BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PS_RX_INFO (Offset 0x0692) */ +#define BIT_RXCTRLIN0 BIT(4) +#define BIT_RXMGTIN0 BIT(3) +#define BIT_RXDATAIN2 BIT(2) +#define BIT_RXDATAIN1 BIT(1) +#define BIT_RXDATAIN0 BIT(0) -#define BIT_SHIFT_PORTSEL__PS_RX_INFO 5 -#define BIT_MASK_PORTSEL__PS_RX_INFO 0x7 -#define BIT_PORTSEL__PS_RX_INFO(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO) -#define BIT_GET_PORTSEL__PS_RX_INFO(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO) +/* 2 REG_WMMPS_UAPSD_TID (Offset 0x0693) */ +#define BIT_WMMPS_UAPSD_TID7 BIT(7) +#define BIT_WMMPS_UAPSD_TID6 BIT(6) +#define BIT_WMMPS_UAPSD_TID5 BIT(5) +#define BIT_WMMPS_UAPSD_TID4 BIT(4) +#define BIT_WMMPS_UAPSD_TID3 BIT(3) +#define BIT_WMMPS_UAPSD_TID2 BIT(2) +#define BIT_WMMPS_UAPSD_TID1 BIT(1) +#define BIT_WMMPS_UAPSD_TID0 BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_LPNAV_CTRL (Offset 0x0694) */ +#define BIT_LPNAV_EN BIT(31) -/* 2 REG_PS_RX_INFO (Offset 0x0692) */ +#define BIT_SHIFT_LPNAV_EARLY 16 +#define BIT_MASK_LPNAV_EARLY 0x7fff +#define BIT_LPNAV_EARLY(x) \ + (((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY) +#define BITS_LPNAV_EARLY (BIT_MASK_LPNAV_EARLY << BIT_SHIFT_LPNAV_EARLY) +#define BIT_CLEAR_LPNAV_EARLY(x) ((x) & (~BITS_LPNAV_EARLY)) +#define BIT_GET_LPNAV_EARLY(x) \ + (((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY) +#define BIT_SET_LPNAV_EARLY(x, v) \ + (BIT_CLEAR_LPNAV_EARLY(x) | BIT_LPNAV_EARLY(v)) -#define BIT_RXCTRLIN0 BIT(4) -#define BIT_RXMGTIN0 BIT(3) -#define BIT_RXDATAIN2 BIT(2) -#define BIT_RXDATAIN1 BIT(1) -#define BIT_RXDATAIN0 BIT(0) +#define BIT_SHIFT_LPNAV_TH 0 +#define BIT_MASK_LPNAV_TH 0xffff +#define BIT_LPNAV_TH(x) (((x) & BIT_MASK_LPNAV_TH) << BIT_SHIFT_LPNAV_TH) +#define BITS_LPNAV_TH (BIT_MASK_LPNAV_TH << BIT_SHIFT_LPNAV_TH) +#define BIT_CLEAR_LPNAV_TH(x) ((x) & (~BITS_LPNAV_TH)) +#define BIT_GET_LPNAV_TH(x) (((x) >> BIT_SHIFT_LPNAV_TH) & BIT_MASK_LPNAV_TH) +#define BIT_SET_LPNAV_TH(x, v) (BIT_CLEAR_LPNAV_TH(x) | BIT_LPNAV_TH(v)) -/* 2 REG_WMMPS_UAPSD_TID (Offset 0x0693) */ +#endif -#define BIT_WMMPS_UAPSD_TID7 BIT(7) -#define BIT_WMMPS_UAPSD_TID6 BIT(6) -#define BIT_WMMPS_UAPSD_TID5 BIT(5) -#define BIT_WMMPS_UAPSD_TID4 BIT(4) -#define BIT_WMMPS_UAPSD_TID3 BIT(3) -#define BIT_WMMPS_UAPSD_TID2 BIT(2) -#define BIT_WMMPS_UAPSD_TID1 BIT(1) -#define BIT_WMMPS_UAPSD_TID0 BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_LPNAV_CTRL (Offset 0x0694) */ +/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ -#define BIT_LPNAV_EN BIT(31) +#define BIT_WKFCAM_POLLING_V1 BIT(31) +#define BIT_WKFCAM_CLR_V1 BIT(30) -#define BIT_SHIFT_LPNAV_EARLY 16 -#define BIT_MASK_LPNAV_EARLY 0x7fff -#define BIT_LPNAV_EARLY(x) (((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY) -#define BIT_GET_LPNAV_EARLY(x) (((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LPNAV_TH 0 -#define BIT_MASK_LPNAV_TH 0xffff -#define BIT_LPNAV_TH(x) (((x) & BIT_MASK_LPNAV_TH) << BIT_SHIFT_LPNAV_TH) -#define BIT_GET_LPNAV_TH(x) (((x) >> BIT_SHIFT_LPNAV_TH) & BIT_MASK_LPNAV_TH) +/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ +#define BIT_WKFCAM_WE BIT(16) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ -#define BIT_WKFCAM_POLLING_V1 BIT(31) -#define BIT_WKFCAM_CLR_V1 BIT(30) +#define BIT_SHIFT_WKFCAM_ADDR_V2 8 +#define BIT_MASK_WKFCAM_ADDR_V2 0xff +#define BIT_WKFCAM_ADDR_V2(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2) +#define BITS_WKFCAM_ADDR_V2 \ + (BIT_MASK_WKFCAM_ADDR_V2 << BIT_SHIFT_WKFCAM_ADDR_V2) +#define BIT_CLEAR_WKFCAM_ADDR_V2(x) ((x) & (~BITS_WKFCAM_ADDR_V2)) +#define BIT_GET_WKFCAM_ADDR_V2(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2) +#define BIT_SET_WKFCAM_ADDR_V2(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR_V2(x) | BIT_WKFCAM_ADDR_V2(v)) + +#define BIT_WMAC_RESP_NONSTA1_DIS BIT(7) + +#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4 +#define BIT_MASK_WMAC_TXMU_ACKPOLICY 0x3 +#define BIT_WMAC_TXMU_ACKPOLICY(x) \ + (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY) +#define BITS_WMAC_TXMU_ACKPOLICY \ + (BIT_MASK_WMAC_TXMU_ACKPOLICY << BIT_SHIFT_WMAC_TXMU_ACKPOLICY) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY(x) ((x) & (~BITS_WMAC_TXMU_ACKPOLICY)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY(x) \ + (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY) & BIT_MASK_WMAC_TXMU_ACKPOLICY) +#define BIT_SET_WMAC_TXMU_ACKPOLICY(x, v) \ + (BIT_CLEAR_WMAC_TXMU_ACKPOLICY(x) | BIT_WMAC_TXMU_ACKPOLICY(v)) + +#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL 1 +#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL 0x7 +#define BIT_WMAC_MU_BFEE_PORT_SEL(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) +#define BITS_WMAC_MU_BFEE_PORT_SEL \ + (BIT_MASK_WMAC_MU_BFEE_PORT_SEL << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) & \ + BIT_MASK_WMAC_MU_BFEE_PORT_SEL) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) | BIT_WMAC_MU_BFEE_PORT_SEL(v)) + +#define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0 +#define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff +#define BIT_WKFCAM_CAM_NUM_V1(x) \ + (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1) +#define BITS_WKFCAM_CAM_NUM_V1 \ + (BIT_MASK_WKFCAM_CAM_NUM_V1 << BIT_SHIFT_WKFCAM_CAM_NUM_V1) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1(x) ((x) & (~BITS_WKFCAM_CAM_NUM_V1)) +#define BIT_GET_WKFCAM_CAM_NUM_V1(x) \ + (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1) & BIT_MASK_WKFCAM_CAM_NUM_V1) +#define BIT_SET_WKFCAM_CAM_NUM_V1(x, v) \ + (BIT_CLEAR_WKFCAM_CAM_NUM_V1(x) | BIT_WKFCAM_CAM_NUM_V1(v)) + +#define BIT_WMAC_MU_BFEE_DIS BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ -#define BIT_WKFCAM_WE BIT(16) +#define BIT_SHIFT_WKFCAM_ADDR 0 +#define BIT_MASK_WKFCAM_ADDR 0x7f +#define BIT_WKFCAM_ADDR(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR) << BIT_SHIFT_WKFCAM_ADDR) +#define BITS_WKFCAM_ADDR (BIT_MASK_WKFCAM_ADDR << BIT_SHIFT_WKFCAM_ADDR) +#define BIT_CLEAR_WKFCAM_ADDR(x) ((x) & (~BITS_WKFCAM_ADDR)) +#define BIT_GET_WKFCAM_ADDR(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR) & BIT_MASK_WKFCAM_ADDR) +#define BIT_SET_WKFCAM_ADDR(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR(x) | BIT_WKFCAM_ADDR(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ +/* 2 REG_WKFMCAM_RWD (Offset 0x069C) */ +#define BIT_SHIFT_WKFMCAM_RWD 0 +#define BIT_MASK_WKFMCAM_RWD 0xffffffffL +#define BIT_WKFMCAM_RWD(x) \ + (((x) & BIT_MASK_WKFMCAM_RWD) << BIT_SHIFT_WKFMCAM_RWD) +#define BITS_WKFMCAM_RWD (BIT_MASK_WKFMCAM_RWD << BIT_SHIFT_WKFMCAM_RWD) +#define BIT_CLEAR_WKFMCAM_RWD(x) ((x) & (~BITS_WKFMCAM_RWD)) +#define BIT_GET_WKFMCAM_RWD(x) \ + (((x) >> BIT_SHIFT_WKFMCAM_RWD) & BIT_MASK_WKFMCAM_RWD) +#define BIT_SET_WKFMCAM_RWD(x, v) \ + (BIT_CLEAR_WKFMCAM_RWD(x) | BIT_WKFMCAM_RWD(v)) -#define BIT_SHIFT_WKFCAM_ADDR_V2 8 -#define BIT_MASK_WKFCAM_ADDR_V2 0xff -#define BIT_WKFCAM_ADDR_V2(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2) -#define BIT_GET_WKFCAM_ADDR_V2(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0 -#define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff -#define BIT_WKFCAM_CAM_NUM_V1(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1) -#define BIT_GET_WKFCAM_CAM_NUM_V1(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1) & BIT_MASK_WKFCAM_CAM_NUM_V1) +/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ +#define BIT_DATAFLT15EN BIT(15) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ +#define BIT_MGTFLT15EN BIT(15) -/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WKFCAM_ADDR 0 -#define BIT_MASK_WKFCAM_ADDR 0x7f -#define BIT_WKFCAM_ADDR(x) (((x) & BIT_MASK_WKFCAM_ADDR) << BIT_SHIFT_WKFCAM_ADDR) -#define BIT_GET_WKFCAM_ADDR(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR) & BIT_MASK_WKFCAM_ADDR) +/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ +#define BIT_DATAFLT14EN BIT(14) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_WKFMCAM_RWD (Offset 0x069C) */ +/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ +#define BIT_MGTFLT14EN BIT(14) -#define BIT_SHIFT_WKFMCAM_RWD 0 -#define BIT_MASK_WKFMCAM_RWD 0xffffffffL -#define BIT_WKFMCAM_RWD(x) (((x) & BIT_MASK_WKFMCAM_RWD) << BIT_SHIFT_WKFMCAM_RWD) -#define BIT_GET_WKFMCAM_RWD(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD) & BIT_MASK_WKFMCAM_RWD) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ -#define BIT_MGTFLT15EN BIT(15) -#define BIT_MGTFLT14EN BIT(14) +#define BIT_MGTFLT13EN BIT(13) +#define BIT_DATAFLT13EN BIT(13) +#define BIT_MGTFLT12EN BIT(12) +#define BIT_DATAFLT12EN BIT(12) +#define BIT_MGTFLT11EN BIT(11) +#define BIT_DATAFLT11EN BIT(11) +#define BIT_MGTFLT10EN BIT(10) +#define BIT_DATAFLT10EN BIT(10) +#define BIT_MGTFLT9EN BIT(9) +#define BIT_DATAFLT9EN BIT(9) +#define BIT_MGTFLT8EN BIT(8) +#define BIT_DATAFLT8EN BIT(8) +#define BIT_DATAFLT7EN BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ -#define BIT_MGTFLT13EN BIT(13) -#define BIT_MGTFLT12EN BIT(12) -#define BIT_MGTFLT11EN BIT(11) -#define BIT_MGTFLT10EN BIT(10) -#define BIT_MGTFLT9EN BIT(9) -#define BIT_MGTFLT8EN BIT(8) +#define BIT_MGTFLT7EN BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ -#define BIT_MGTFLT7EN BIT(7) -#define BIT_MGTFLT6EN BIT(6) +#define BIT_DATAFLT6EN BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ + +#define BIT_MGTFLT6EN BIT(6) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ -#define BIT_MGTFLT5EN BIT(5) -#define BIT_MGTFLT4EN BIT(4) -#define BIT_MGTFLT3EN BIT(3) -#define BIT_MGTFLT2EN BIT(2) -#define BIT_MGTFLT1EN BIT(1) -#define BIT_MGTFLT0EN BIT(0) +#define BIT_MGTFLT5EN BIT(5) +#define BIT_DATAFLT5EN BIT(5) +#define BIT_MGTFLT4EN BIT(4) +#define BIT_DATAFLT4EN BIT(4) +#define BIT_MGTFLT3EN BIT(3) +#define BIT_DATAFLT3EN BIT(3) +#define BIT_MGTFLT2EN BIT(2) +#define BIT_DATAFLT2EN BIT(2) +#define BIT_MGTFLT1EN BIT(1) +#define BIT_DATAFLT1EN BIT(1) +#define BIT_MGTFLT0EN BIT(0) +#define BIT_DATAFLT0EN BIT(0) /* 2 REG_RXFLTMAP1 (Offset 0x06A2) */ -#define BIT_CTRLFLT15EN BIT(15) -#define BIT_CTRLFLT14EN BIT(14) -#define BIT_CTRLFLT13EN BIT(13) -#define BIT_CTRLFLT12EN BIT(12) -#define BIT_CTRLFLT11EN BIT(11) -#define BIT_CTRLFLT10EN BIT(10) -#define BIT_CTRLFLT9EN BIT(9) -#define BIT_CTRLFLT8EN BIT(8) -#define BIT_CTRLFLT7EN BIT(7) -#define BIT_CTRLFLT6EN BIT(6) +#define BIT_CTRLFLT15EN BIT(15) +#define BIT_CTRLFLT14EN BIT(14) +#define BIT_CTRLFLT13EN BIT(13) +#define BIT_CTRLFLT12EN BIT(12) +#define BIT_CTRLFLT11EN BIT(11) +#define BIT_CTRLFLT10EN BIT(10) +#define BIT_CTRLFLT9EN BIT(9) +#define BIT_CTRLFLT8EN BIT(8) +#define BIT_CTRLFLT7EN BIT(7) +#define BIT_CTRLFLT6EN BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXFLTMAP1 (Offset 0x06A2) */ -#define BIT_CTRLFLT5EN BIT(5) -#define BIT_CTRLFLT4EN BIT(4) -#define BIT_CTRLFLT3EN BIT(3) -#define BIT_CTRLFLT2EN BIT(2) -#define BIT_CTRLFLT1EN BIT(1) -#define BIT_CTRLFLT0EN BIT(0) +#define BIT_CTRLFLT5EN BIT(5) +#define BIT_CTRLFLT4EN BIT(4) +#define BIT_CTRLFLT3EN BIT(3) +#define BIT_CTRLFLT2EN BIT(2) +#define BIT_CTRLFLT1EN BIT(1) +#define BIT_CTRLFLT0EN BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_BCN_PSR_RPT (Offset 0x06A8) */ -/* 2 REG_RXFLTMAP (Offset 0x06A4) */ +#define BIT_SHIFT_DTIM_CNT 24 +#define BIT_MASK_DTIM_CNT 0xff +#define BIT_DTIM_CNT(x) (((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT) +#define BITS_DTIM_CNT (BIT_MASK_DTIM_CNT << BIT_SHIFT_DTIM_CNT) +#define BIT_CLEAR_DTIM_CNT(x) ((x) & (~BITS_DTIM_CNT)) +#define BIT_GET_DTIM_CNT(x) (((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT) +#define BIT_SET_DTIM_CNT(x, v) (BIT_CLEAR_DTIM_CNT(x) | BIT_DTIM_CNT(v)) + +#define BIT_SHIFT_DTIM_PERIOD 16 +#define BIT_MASK_DTIM_PERIOD 0xff +#define BIT_DTIM_PERIOD(x) \ + (((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD) +#define BITS_DTIM_PERIOD (BIT_MASK_DTIM_PERIOD << BIT_SHIFT_DTIM_PERIOD) +#define BIT_CLEAR_DTIM_PERIOD(x) ((x) & (~BITS_DTIM_PERIOD)) +#define BIT_GET_DTIM_PERIOD(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD) +#define BIT_SET_DTIM_PERIOD(x, v) \ + (BIT_CLEAR_DTIM_PERIOD(x) | BIT_DTIM_PERIOD(v)) + +#define BIT_DTIM BIT(15) +#define BIT_TIM BIT(14) + +#define BIT_SHIFT_PS_AID_0 0 +#define BIT_MASK_PS_AID_0 0x7ff +#define BIT_PS_AID_0(x) (((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0) +#define BITS_PS_AID_0 (BIT_MASK_PS_AID_0 << BIT_SHIFT_PS_AID_0) +#define BIT_CLEAR_PS_AID_0(x) ((x) & (~BITS_PS_AID_0)) +#define BIT_GET_PS_AID_0(x) (((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0) +#define BIT_SET_PS_AID_0(x, v) (BIT_CLEAR_PS_AID_0(x) | BIT_PS_AID_0(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_DATAFLT15EN BIT(15) -#define BIT_DATAFLT14EN BIT(14) -#define BIT_DATAFLT13EN BIT(13) -#define BIT_DATAFLT12EN BIT(12) -#define BIT_DATAFLT11EN BIT(11) -#define BIT_DATAFLT10EN BIT(10) -#define BIT_DATAFLT9EN BIT(9) -#define BIT_DATAFLT8EN BIT(8) -#define BIT_DATAFLT7EN BIT(7) -#define BIT_DATAFLT6EN BIT(6) -#define BIT_DATAFLT5EN BIT(5) -#define BIT_DATAFLT4EN BIT(4) -#define BIT_DATAFLT3EN BIT(3) -#define BIT_DATAFLT2EN BIT(2) -#define BIT_DATAFLT1EN BIT(1) -#define BIT_DATAFLT0EN BIT(0) +/* 2 REG_FLC_RPC (Offset 0x06AC) */ -/* 2 REG_BCN_PSR_RPT (Offset 0x06A8) */ +#define BIT_SHIFT_FLC_RPC 0 +#define BIT_MASK_FLC_RPC 0xff +#define BIT_FLC_RPC(x) (((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC) +#define BITS_FLC_RPC (BIT_MASK_FLC_RPC << BIT_SHIFT_FLC_RPC) +#define BIT_CLEAR_FLC_RPC(x) ((x) & (~BITS_FLC_RPC)) +#define BIT_GET_FLC_RPC(x) (((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC) +#define BIT_SET_FLC_RPC(x, v) (BIT_CLEAR_FLC_RPC(x) | BIT_FLC_RPC(v)) +/* 2 REG_FLC_RPCT (Offset 0x06AD) */ -#define BIT_SHIFT_DTIM_CNT 24 -#define BIT_MASK_DTIM_CNT 0xff -#define BIT_DTIM_CNT(x) (((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT) -#define BIT_GET_DTIM_CNT(x) (((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT) +#define BIT_SHIFT_FLC_RPCT 0 +#define BIT_MASK_FLC_RPCT 0xff +#define BIT_FLC_RPCT(x) (((x) & BIT_MASK_FLC_RPCT) << BIT_SHIFT_FLC_RPCT) +#define BITS_FLC_RPCT (BIT_MASK_FLC_RPCT << BIT_SHIFT_FLC_RPCT) +#define BIT_CLEAR_FLC_RPCT(x) ((x) & (~BITS_FLC_RPCT)) +#define BIT_GET_FLC_RPCT(x) (((x) >> BIT_SHIFT_FLC_RPCT) & BIT_MASK_FLC_RPCT) +#define BIT_SET_FLC_RPCT(x, v) (BIT_CLEAR_FLC_RPCT(x) | BIT_FLC_RPCT(v)) +/* 2 REG_FLC_PTS (Offset 0x06AE) */ -#define BIT_SHIFT_DTIM_PERIOD 16 -#define BIT_MASK_DTIM_PERIOD 0xff -#define BIT_DTIM_PERIOD(x) (((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD) -#define BIT_GET_DTIM_PERIOD(x) (((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD) +#define BIT_CMF BIT(2) +#define BIT_CCF BIT(1) +#define BIT_CDF BIT(0) -#define BIT_DTIM BIT(15) -#define BIT_TIM BIT(14) +/* 2 REG_FLC_TRPC (Offset 0x06AF) */ -#define BIT_SHIFT_PS_AID_0 0 -#define BIT_MASK_PS_AID_0 0x7ff -#define BIT_PS_AID_0(x) (((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0) -#define BIT_GET_PS_AID_0(x) (((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0) +#define BIT_FLC_RPCT_V1 BIT(7) +#define BIT_MODE BIT(6) +#define BIT_SHIFT_TRPCD 0 +#define BIT_MASK_TRPCD 0x3f +#define BIT_TRPCD(x) (((x) & BIT_MASK_TRPCD) << BIT_SHIFT_TRPCD) +#define BITS_TRPCD (BIT_MASK_TRPCD << BIT_SHIFT_TRPCD) +#define BIT_CLEAR_TRPCD(x) ((x) & (~BITS_TRPCD)) +#define BIT_GET_TRPCD(x) (((x) >> BIT_SHIFT_TRPCD) & BIT_MASK_TRPCD) +#define BIT_SET_TRPCD(x, v) (BIT_CLEAR_TRPCD(x) | BIT_TRPCD(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXPKTMON_CTRL (Offset 0x06B0) */ +#define BIT_SHIFT_RXBKQPKT_SEQ 20 +#define BIT_MASK_RXBKQPKT_SEQ 0xf +#define BIT_RXBKQPKT_SEQ(x) \ + (((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ) +#define BITS_RXBKQPKT_SEQ (BIT_MASK_RXBKQPKT_SEQ << BIT_SHIFT_RXBKQPKT_SEQ) +#define BIT_CLEAR_RXBKQPKT_SEQ(x) ((x) & (~BITS_RXBKQPKT_SEQ)) +#define BIT_GET_RXBKQPKT_SEQ(x) \ + (((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ) +#define BIT_SET_RXBKQPKT_SEQ(x, v) \ + (BIT_CLEAR_RXBKQPKT_SEQ(x) | BIT_RXBKQPKT_SEQ(v)) + +#define BIT_SHIFT_RXBEQPKT_SEQ 16 +#define BIT_MASK_RXBEQPKT_SEQ 0xf +#define BIT_RXBEQPKT_SEQ(x) \ + (((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ) +#define BITS_RXBEQPKT_SEQ (BIT_MASK_RXBEQPKT_SEQ << BIT_SHIFT_RXBEQPKT_SEQ) +#define BIT_CLEAR_RXBEQPKT_SEQ(x) ((x) & (~BITS_RXBEQPKT_SEQ)) +#define BIT_GET_RXBEQPKT_SEQ(x) \ + (((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ) +#define BIT_SET_RXBEQPKT_SEQ(x, v) \ + (BIT_CLEAR_RXBEQPKT_SEQ(x) | BIT_RXBEQPKT_SEQ(v)) + +#define BIT_SHIFT_RXVIQPKT_SEQ 12 +#define BIT_MASK_RXVIQPKT_SEQ 0xf +#define BIT_RXVIQPKT_SEQ(x) \ + (((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ) +#define BITS_RXVIQPKT_SEQ (BIT_MASK_RXVIQPKT_SEQ << BIT_SHIFT_RXVIQPKT_SEQ) +#define BIT_CLEAR_RXVIQPKT_SEQ(x) ((x) & (~BITS_RXVIQPKT_SEQ)) +#define BIT_GET_RXVIQPKT_SEQ(x) \ + (((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ) +#define BIT_SET_RXVIQPKT_SEQ(x, v) \ + (BIT_CLEAR_RXVIQPKT_SEQ(x) | BIT_RXVIQPKT_SEQ(v)) + +#define BIT_SHIFT_RXVOQPKT_SEQ 8 +#define BIT_MASK_RXVOQPKT_SEQ 0xf +#define BIT_RXVOQPKT_SEQ(x) \ + (((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ) +#define BITS_RXVOQPKT_SEQ (BIT_MASK_RXVOQPKT_SEQ << BIT_SHIFT_RXVOQPKT_SEQ) +#define BIT_CLEAR_RXVOQPKT_SEQ(x) ((x) & (~BITS_RXVOQPKT_SEQ)) +#define BIT_GET_RXVOQPKT_SEQ(x) \ + (((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ) +#define BIT_SET_RXVOQPKT_SEQ(x, v) \ + (BIT_CLEAR_RXVOQPKT_SEQ(x) | BIT_RXVOQPKT_SEQ(v)) + +#define BIT_RXBKQPKT_ERR BIT(7) +#define BIT_RXBEQPKT_ERR BIT(6) +#define BIT_RXVIQPKT_ERR BIT(5) +#define BIT_RXVOQPKT_ERR BIT(4) +#define BIT_RXDMA_MON_EN BIT(2) +#define BIT_RXPKT_MON_RST BIT(1) +#define BIT_RXPKT_MON_EN BIT(0) -/* 2 REG_FLC_RPC (Offset 0x06AC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FLC_RPC 0 -#define BIT_MASK_FLC_RPC 0xff -#define BIT_FLC_RPC(x) (((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC) -#define BIT_GET_FLC_RPC(x) (((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC) +/* 2 REG_STATE_MON (Offset 0x06B4) */ +#define BIT_SHIFT_DMA_MON_EN 24 +#define BIT_MASK_DMA_MON_EN 0x1f +#define BIT_DMA_MON_EN(x) (((x) & BIT_MASK_DMA_MON_EN) << BIT_SHIFT_DMA_MON_EN) +#define BITS_DMA_MON_EN (BIT_MASK_DMA_MON_EN << BIT_SHIFT_DMA_MON_EN) +#define BIT_CLEAR_DMA_MON_EN(x) ((x) & (~BITS_DMA_MON_EN)) +#define BIT_GET_DMA_MON_EN(x) \ + (((x) >> BIT_SHIFT_DMA_MON_EN) & BIT_MASK_DMA_MON_EN) +#define BIT_SET_DMA_MON_EN(x, v) (BIT_CLEAR_DMA_MON_EN(x) | BIT_DMA_MON_EN(v)) -/* 2 REG_FLC_RPCT (Offset 0x06AD) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_FLC_RPCT 0 -#define BIT_MASK_FLC_RPCT 0xff -#define BIT_FLC_RPCT(x) (((x) & BIT_MASK_FLC_RPCT) << BIT_SHIFT_FLC_RPCT) -#define BIT_GET_FLC_RPCT(x) (((x) >> BIT_SHIFT_FLC_RPCT) & BIT_MASK_FLC_RPCT) +/* 2 REG_STATE_MON (Offset 0x06B4) */ +#define BIT_SHIFT_STATE_SEL 24 +#define BIT_MASK_STATE_SEL 0x1f +#define BIT_STATE_SEL(x) (((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL) +#define BITS_STATE_SEL (BIT_MASK_STATE_SEL << BIT_SHIFT_STATE_SEL) +#define BIT_CLEAR_STATE_SEL(x) ((x) & (~BITS_STATE_SEL)) +#define BIT_GET_STATE_SEL(x) (((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL) +#define BIT_SET_STATE_SEL(x, v) (BIT_CLEAR_STATE_SEL(x) | BIT_STATE_SEL(v)) -/* 2 REG_FLC_PTS (Offset 0x06AE) */ +#define BIT_SHIFT_STATE_INFO 8 +#define BIT_MASK_STATE_INFO 0xff +#define BIT_STATE_INFO(x) (((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO) +#define BITS_STATE_INFO (BIT_MASK_STATE_INFO << BIT_SHIFT_STATE_INFO) +#define BIT_CLEAR_STATE_INFO(x) ((x) & (~BITS_STATE_INFO)) +#define BIT_GET_STATE_INFO(x) \ + (((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO) +#define BIT_SET_STATE_INFO(x, v) (BIT_CLEAR_STATE_INFO(x) | BIT_STATE_INFO(v)) -#define BIT_CMF BIT(2) -#define BIT_CCF BIT(1) -#define BIT_CDF BIT(0) +#define BIT_UPD_NXT_STATE BIT(7) -/* 2 REG_FLC_TRPC (Offset 0x06AF) */ +#endif -#define BIT_FLC_RPCT_V1 BIT(7) -#define BIT_MODE BIT(6) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TRPCD 0 -#define BIT_MASK_TRPCD 0x3f -#define BIT_TRPCD(x) (((x) & BIT_MASK_TRPCD) << BIT_SHIFT_TRPCD) -#define BIT_GET_TRPCD(x) (((x) >> BIT_SHIFT_TRPCD) & BIT_MASK_TRPCD) +/* 2 REG_STATE_MON (Offset 0x06B4) */ +#define BIT_SHIFT_PKT_MON_EN 0 +#define BIT_MASK_PKT_MON_EN 0x7f +#define BIT_PKT_MON_EN(x) (((x) & BIT_MASK_PKT_MON_EN) << BIT_SHIFT_PKT_MON_EN) +#define BITS_PKT_MON_EN (BIT_MASK_PKT_MON_EN << BIT_SHIFT_PKT_MON_EN) +#define BIT_CLEAR_PKT_MON_EN(x) ((x) & (~BITS_PKT_MON_EN)) +#define BIT_GET_PKT_MON_EN(x) \ + (((x) >> BIT_SHIFT_PKT_MON_EN) & BIT_MASK_PKT_MON_EN) +#define BIT_SET_PKT_MON_EN(x, v) (BIT_CLEAR_PKT_MON_EN(x) | BIT_PKT_MON_EN(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RXPKTMON_CTRL (Offset 0x06B0) */ +/* 2 REG_STATE_MON (Offset 0x06B4) */ +#define BIT_SHIFT_CUR_STATE 0 +#define BIT_MASK_CUR_STATE 0x7f +#define BIT_CUR_STATE(x) (((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE) +#define BITS_CUR_STATE (BIT_MASK_CUR_STATE << BIT_SHIFT_CUR_STATE) +#define BIT_CLEAR_CUR_STATE(x) ((x) & (~BITS_CUR_STATE)) +#define BIT_GET_CUR_STATE(x) (((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE) +#define BIT_SET_CUR_STATE(x, v) (BIT_CLEAR_CUR_STATE(x) | BIT_CUR_STATE(v)) -#define BIT_SHIFT_RXBKQPKT_SEQ 20 -#define BIT_MASK_RXBKQPKT_SEQ 0xf -#define BIT_RXBKQPKT_SEQ(x) (((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ) -#define BIT_GET_RXBKQPKT_SEQ(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXBEQPKT_SEQ 16 -#define BIT_MASK_RXBEQPKT_SEQ 0xf -#define BIT_RXBEQPKT_SEQ(x) (((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ) -#define BIT_GET_RXBEQPKT_SEQ(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ) +/* 2 REG_ERROR_MON (Offset 0x06B8) */ +#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC BIT(23) +#define BIT_CSI_CHKSUM_ERROR BIT(22) -#define BIT_SHIFT_RXVIQPKT_SEQ 12 -#define BIT_MASK_RXVIQPKT_SEQ 0xf -#define BIT_RXVIQPKT_SEQ(x) (((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ) -#define BIT_GET_RXVIQPKT_SEQ(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RXVOQPKT_SEQ 8 -#define BIT_MASK_RXVOQPKT_SEQ 0xf -#define BIT_RXVOQPKT_SEQ(x) (((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ) -#define BIT_GET_RXVOQPKT_SEQ(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ) +/* 2 REG_ERROR_MON (Offset 0x06B8) */ -#define BIT_RXBKQPKT_ERR BIT(7) -#define BIT_RXBEQPKT_ERR BIT(6) -#define BIT_RXVIQPKT_ERR BIT(5) -#define BIT_RXVOQPKT_ERR BIT(4) -#define BIT_RXDMA_MON_EN BIT(2) -#define BIT_RXPKT_MON_RST BIT(1) -#define BIT_RXPKT_MON_EN BIT(0) +#define BIT_BFM_RPTNUM_ERROR BIT(21) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ERROR_MON (Offset 0x06B8) */ +#define BIT_MACRX_ERR_5 BIT(21) -/* 2 REG_STATE_MON (Offset 0x06B4) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_DMA_MON_EN 24 -#define BIT_MASK_DMA_MON_EN 0x1f -#define BIT_DMA_MON_EN(x) (((x) & BIT_MASK_DMA_MON_EN) << BIT_SHIFT_DMA_MON_EN) -#define BIT_GET_DMA_MON_EN(x) (((x) >> BIT_SHIFT_DMA_MON_EN) & BIT_MASK_DMA_MON_EN) +/* 2 REG_ERROR_MON (Offset 0x06B8) */ +#define BIT_BFM_CHECKSUM_ERROR BIT(20) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_STATE_MON (Offset 0x06B4) */ +/* 2 REG_ERROR_MON (Offset 0x06B8) */ +#define BIT_MACRX_ERR_4 BIT(20) +#define BIT_MACRX_ERR_3 BIT(19) +#define BIT_MACRX_ERR_2 BIT(18) -#define BIT_SHIFT_STATE_SEL 24 -#define BIT_MASK_STATE_SEL 0x1f -#define BIT_STATE_SEL(x) (((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL) -#define BIT_GET_STATE_SEL(x) (((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_STATE_INFO 8 -#define BIT_MASK_STATE_INFO 0xff -#define BIT_STATE_INFO(x) (((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO) -#define BIT_GET_STATE_INFO(x) (((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO) +/* 2 REG_ERROR_MON (Offset 0x06B8) */ -#define BIT_UPD_NXT_STATE BIT(7) +#define BIT_MACRX_ERR_1 BIT(17) +#define BIT_MACRX_ERR_0 BIT(16) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ERROR_MON (Offset 0x06B8) */ +#define BIT_PRETX_ERRHDL_EN BIT(15) -/* 2 REG_STATE_MON (Offset 0x06B4) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PKT_MON_EN 0 -#define BIT_MASK_PKT_MON_EN 0x7f -#define BIT_PKT_MON_EN(x) (((x) & BIT_MASK_PKT_MON_EN) << BIT_SHIFT_PKT_MON_EN) -#define BIT_GET_PKT_MON_EN(x) (((x) >> BIT_SHIFT_PKT_MON_EN) & BIT_MASK_PKT_MON_EN) +/* 2 REG_ERROR_MON (Offset 0x06B8) */ +#define BIT_WMAC_PRETX_ERRHDL_EN BIT(15) +#define BIT_MACTX_ERR_5 BIT(5) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_STATE_MON (Offset 0x06B4) */ +/* 2 REG_ERROR_MON (Offset 0x06B8) */ +#define BIT_MACTX_ERR_4 BIT(4) -#define BIT_SHIFT_CUR_STATE 0 -#define BIT_MASK_CUR_STATE 0x7f -#define BIT_CUR_STATE(x) (((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE) -#define BIT_GET_CUR_STATE(x) (((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ERROR_MON (Offset 0x06B8) */ -#define BIT_MACRX_ERR_1 BIT(17) -#define BIT_MACRX_ERR_0 BIT(16) -#define BIT_MACTX_ERR_3 BIT(3) -#define BIT_MACTX_ERR_2 BIT(2) -#define BIT_MACTX_ERR_1 BIT(1) -#define BIT_MACTX_ERR_0 BIT(0) +#define BIT_MACTX_ERR_3 BIT(3) +#define BIT_MACTX_ERR_2 BIT(2) +#define BIT_MACTX_ERR_1 BIT(1) +#define BIT_MACTX_ERR_0 BIT(0) /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ -#define BIT_EN_TXRPTBUF_CLK BIT(31) +#define BIT_EN_TXRPTBUF_CLK BIT(31) -#define BIT_SHIFT_INFO_INDEX_OFFSET 16 -#define BIT_MASK_INFO_INDEX_OFFSET 0x1fff -#define BIT_INFO_INDEX_OFFSET(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET) -#define BIT_GET_INFO_INDEX_OFFSET(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SEARCH_MACID (Offset 0x06BC) */ +#define BIT_SHIFT_INFO_INDEX_OFFSET 16 +#define BIT_MASK_INFO_INDEX_OFFSET 0x1fff +#define BIT_INFO_INDEX_OFFSET(x) \ + (((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET) +#define BITS_INFO_INDEX_OFFSET \ + (BIT_MASK_INFO_INDEX_OFFSET << BIT_SHIFT_INFO_INDEX_OFFSET) +#define BIT_CLEAR_INFO_INDEX_OFFSET(x) ((x) & (~BITS_INFO_INDEX_OFFSET)) +#define BIT_GET_INFO_INDEX_OFFSET(x) \ + (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET) +#define BIT_SET_INFO_INDEX_OFFSET(x, v) \ + (BIT_CLEAR_INFO_INDEX_OFFSET(x) | BIT_INFO_INDEX_OFFSET(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ -#define BIT_WMAC_SRCH_FIFOFULL BIT(15) +#define BIT_WMAC_SRCH_FIFOFULL BIT(15) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SEARCH_MACID (Offset 0x06BC) */ +#define BIT_DIS_INFOSRCH BIT(14) -/* 2 REG_SEARCH_MACID (Offset 0x06BC) */ +#endif -#define BIT_DIS_INFOSRCH BIT(14) -#define BIT_DISABLE_B0 BIT(13) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_INFO_ADDR_OFFSET 0 -#define BIT_MASK_INFO_ADDR_OFFSET 0x1fff -#define BIT_INFO_ADDR_OFFSET(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET) -#define BIT_GET_INFO_ADDR_OFFSET(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET) +/* 2 REG_SEARCH_MACID (Offset 0x06BC) */ +#define BIT_DISABLE_B0 BIT(13) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_SEARCH_MACID (Offset 0x06BC) */ -/* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */ +#define BIT_SHIFT_INFO_ADDR_OFFSET 0 +#define BIT_MASK_INFO_ADDR_OFFSET 0x1fff +#define BIT_INFO_ADDR_OFFSET(x) \ + (((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET) +#define BITS_INFO_ADDR_OFFSET \ + (BIT_MASK_INFO_ADDR_OFFSET << BIT_SHIFT_INFO_ADDR_OFFSET) +#define BIT_CLEAR_INFO_ADDR_OFFSET(x) ((x) & (~BITS_INFO_ADDR_OFFSET)) +#define BIT_GET_INFO_ADDR_OFFSET(x) \ + (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET) +#define BIT_SET_INFO_ADDR_OFFSET(x, v) \ + (BIT_CLEAR_INFO_ADDR_OFFSET(x) | BIT_INFO_ADDR_OFFSET(v)) -#define BIT_PRI_MASK_RX_RESP BIT(126) -#define BIT_PRI_MASK_RXOFDM BIT(125) -#define BIT_PRI_MASK_RXCCK BIT(124) +#endif -#define BIT_SHIFT_PRI_MASK_TXAC (117 & CPU_OPT_WIDTH) -#define BIT_MASK_PRI_MASK_TXAC 0x7f -#define BIT_PRI_MASK_TXAC(x) (((x) & BIT_MASK_PRI_MASK_TXAC) << BIT_SHIFT_PRI_MASK_TXAC) -#define BIT_GET_PRI_MASK_TXAC(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC) & BIT_MASK_PRI_MASK_TXAC) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) +/* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */ -#define BIT_SHIFT_PRI_MASK_NAV (109 & CPU_OPT_WIDTH) -#define BIT_MASK_PRI_MASK_NAV 0xff -#define BIT_PRI_MASK_NAV(x) (((x) & BIT_MASK_PRI_MASK_NAV) << BIT_SHIFT_PRI_MASK_NAV) -#define BIT_GET_PRI_MASK_NAV(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV) & BIT_MASK_PRI_MASK_NAV) +#define BIT_PRI_MASK_RX_RESP BIT(126) +#define BIT_PRI_MASK_RXOFDM BIT(125) +#define BIT_PRI_MASK_RXCCK BIT(124) +#define BIT_PRI_MASK_CCK BIT(108) +#define BIT_PRI_MASK_OFDM BIT(107) +#define BIT_PRI_MASK_RTY BIT(106) +#define BIT_OOB BIT(97) +#define BIT_ANT_SEL BIT(96) -#define BIT_PRI_MASK_CCK BIT(108) -#define BIT_PRI_MASK_OFDM BIT(107) -#define BIT_PRI_MASK_RTY BIT(106) +#endif -#define BIT_SHIFT_PRI_MASK_NUM (102 & CPU_OPT_WIDTH) -#define BIT_MASK_PRI_MASK_NUM 0xf -#define BIT_PRI_MASK_NUM(x) (((x) & BIT_MASK_PRI_MASK_NUM) << BIT_SHIFT_PRI_MASK_NUM) -#define BIT_GET_PRI_MASK_NUM(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM) & BIT_MASK_PRI_MASK_NUM) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) +/* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */ -#define BIT_SHIFT_PRI_MASK_TYPE (98 & CPU_OPT_WIDTH) -#define BIT_MASK_PRI_MASK_TYPE 0xf -#define BIT_PRI_MASK_TYPE(x) (((x) & BIT_MASK_PRI_MASK_TYPE) << BIT_SHIFT_PRI_MASK_TYPE) -#define BIT_GET_PRI_MASK_TYPE(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE) & BIT_MASK_PRI_MASK_TYPE) +#define BIT_SHIFT_COEX_TABLE_1 0 +#define BIT_MASK_COEX_TABLE_1 0xffffffffL +#define BIT_COEX_TABLE_1(x) \ + (((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1) +#define BITS_COEX_TABLE_1 (BIT_MASK_COEX_TABLE_1 << BIT_SHIFT_COEX_TABLE_1) +#define BIT_CLEAR_COEX_TABLE_1(x) ((x) & (~BITS_COEX_TABLE_1)) +#define BIT_GET_COEX_TABLE_1(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1) +#define BIT_SET_COEX_TABLE_1(x, v) \ + (BIT_CLEAR_COEX_TABLE_1(x) | BIT_COEX_TABLE_1(v)) -#define BIT_OOB BIT(97) -#define BIT_ANT_SEL BIT(96) +#endif -#define BIT_SHIFT_BREAK_TABLE_2 (80 & CPU_OPT_WIDTH) -#define BIT_MASK_BREAK_TABLE_2 0xffff -#define BIT_BREAK_TABLE_2(x) (((x) & BIT_MASK_BREAK_TABLE_2) << BIT_SHIFT_BREAK_TABLE_2) -#define BIT_GET_BREAK_TABLE_2(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2) & BIT_MASK_BREAK_TABLE_2) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_BT_COEX_TABLE_H (Offset 0x06CC) */ -#define BIT_SHIFT_BREAK_TABLE_1 (64 & CPU_OPT_WIDTH) -#define BIT_MASK_BREAK_TABLE_1 0xffff -#define BIT_BREAK_TABLE_1(x) (((x) & BIT_MASK_BREAK_TABLE_1) << BIT_SHIFT_BREAK_TABLE_1) -#define BIT_GET_BREAK_TABLE_1(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1) & BIT_MASK_BREAK_TABLE_1) +#define BIT_PRI_MASK_RX_RESP_V1 BIT(30) +#define BIT_PRI_MASK_RXOFDM_V1 BIT(29) +#define BIT_PRI_MASK_RXCCK_V1 BIT(28) +#define BIT_PRI_MASK_CCK_V1 BIT(12) +#define BIT_PRI_MASK_OFDM_V1 BIT(11) +#define BIT_PRI_MASK_RTY_V1 BIT(10) +#define BIT_OOB_V1 BIT(1) +#define BIT_ANT_SEL_V1 BIT(0) +#endif -#define BIT_SHIFT_COEX_TABLE_2 (32 & CPU_OPT_WIDTH) -#define BIT_MASK_COEX_TABLE_2 0xffffffffL -#define BIT_COEX_TABLE_2(x) (((x) & BIT_MASK_COEX_TABLE_2) << BIT_SHIFT_COEX_TABLE_2) -#define BIT_GET_COEX_TABLE_2(x) (((x) >> BIT_SHIFT_COEX_TABLE_2) & BIT_MASK_COEX_TABLE_2) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_RXCMD_0 (Offset 0x06D0) */ -#define BIT_SHIFT_COEX_TABLE_1 0 -#define BIT_MASK_COEX_TABLE_1 0xffffffffL -#define BIT_COEX_TABLE_1(x) (((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1) -#define BIT_GET_COEX_TABLE_1(x) (((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1) +#define BIT_RXCMD_EN BIT(31) +#define BIT_SHIFT_RXCMD_INFO 0 +#define BIT_MASK_RXCMD_INFO 0x7fffffffL +#define BIT_RXCMD_INFO(x) (((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO) +#define BITS_RXCMD_INFO (BIT_MASK_RXCMD_INFO << BIT_SHIFT_RXCMD_INFO) +#define BIT_CLEAR_RXCMD_INFO(x) ((x) & (~BITS_RXCMD_INFO)) +#define BIT_GET_RXCMD_INFO(x) \ + (((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO) +#define BIT_SET_RXCMD_INFO(x, v) (BIT_CLEAR_RXCMD_INFO(x) | BIT_RXCMD_INFO(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RXCMD_1 (Offset 0x06D4) */ +#define BIT_SHIFT_CSI_RADDR_LATCH_V1 24 +#define BIT_MASK_CSI_RADDR_LATCH_V1 0x3f +#define BIT_CSI_RADDR_LATCH_V1(x) \ + (((x) & BIT_MASK_CSI_RADDR_LATCH_V1) << BIT_SHIFT_CSI_RADDR_LATCH_V1) +#define BITS_CSI_RADDR_LATCH_V1 \ + (BIT_MASK_CSI_RADDR_LATCH_V1 << BIT_SHIFT_CSI_RADDR_LATCH_V1) +#define BIT_CLEAR_CSI_RADDR_LATCH_V1(x) ((x) & (~BITS_CSI_RADDR_LATCH_V1)) +#define BIT_GET_CSI_RADDR_LATCH_V1(x) \ + (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V1) & BIT_MASK_CSI_RADDR_LATCH_V1) +#define BIT_SET_CSI_RADDR_LATCH_V1(x, v) \ + (BIT_CLEAR_CSI_RADDR_LATCH_V1(x) | BIT_CSI_RADDR_LATCH_V1(v)) -/* 2 REG_RXCMD_0 (Offset 0x06D0) */ +#endif -#define BIT_RXCMD_EN BIT(31) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) + +/* 2 REG_RXCMD_1 (Offset 0x06D4) */ + +#define BIT_SHIFT_CSI_RADDR_LATCH 24 +#define BIT_MASK_CSI_RADDR_LATCH 0xff +#define BIT_CSI_RADDR_LATCH(x) \ + (((x) & BIT_MASK_CSI_RADDR_LATCH) << BIT_SHIFT_CSI_RADDR_LATCH) +#define BITS_CSI_RADDR_LATCH \ + (BIT_MASK_CSI_RADDR_LATCH << BIT_SHIFT_CSI_RADDR_LATCH) +#define BIT_CLEAR_CSI_RADDR_LATCH(x) ((x) & (~BITS_CSI_RADDR_LATCH)) +#define BIT_GET_CSI_RADDR_LATCH(x) \ + (((x) >> BIT_SHIFT_CSI_RADDR_LATCH) & BIT_MASK_CSI_RADDR_LATCH) +#define BIT_SET_CSI_RADDR_LATCH(x, v) \ + (BIT_CLEAR_CSI_RADDR_LATCH(x) | BIT_CSI_RADDR_LATCH(v)) -#define BIT_SHIFT_RXCMD_INFO 0 -#define BIT_MASK_RXCMD_INFO 0x7fffffffL -#define BIT_RXCMD_INFO(x) (((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO) -#define BIT_GET_RXCMD_INFO(x) (((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO) +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_RXCMD_1 (Offset 0x06D4) */ +#define BIT_SHIFT_CSI_WADDR_LATCH_V1 16 +#define BIT_MASK_CSI_WADDR_LATCH_V1 0x3f +#define BIT_CSI_WADDR_LATCH_V1(x) \ + (((x) & BIT_MASK_CSI_WADDR_LATCH_V1) << BIT_SHIFT_CSI_WADDR_LATCH_V1) +#define BITS_CSI_WADDR_LATCH_V1 \ + (BIT_MASK_CSI_WADDR_LATCH_V1 << BIT_SHIFT_CSI_WADDR_LATCH_V1) +#define BIT_CLEAR_CSI_WADDR_LATCH_V1(x) ((x) & (~BITS_CSI_WADDR_LATCH_V1)) +#define BIT_GET_CSI_WADDR_LATCH_V1(x) \ + (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V1) & BIT_MASK_CSI_WADDR_LATCH_V1) +#define BIT_SET_CSI_WADDR_LATCH_V1(x, v) \ + (BIT_CLEAR_CSI_WADDR_LATCH_V1(x) | BIT_CSI_WADDR_LATCH_V1(v)) -#define BIT_SHIFT_RXCMD_PRD 0 -#define BIT_MASK_RXCMD_PRD 0xffff -#define BIT_RXCMD_PRD(x) (((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD) -#define BIT_GET_RXCMD_PRD(x) (((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) -/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +/* 2 REG_RXCMD_1 (Offset 0x06D4) */ +#define BIT_SHIFT_CSI_WADDR_LATCH 16 +#define BIT_MASK_CSI_WADDR_LATCH 0xff +#define BIT_CSI_WADDR_LATCH(x) \ + (((x) & BIT_MASK_CSI_WADDR_LATCH) << BIT_SHIFT_CSI_WADDR_LATCH) +#define BITS_CSI_WADDR_LATCH \ + (BIT_MASK_CSI_WADDR_LATCH << BIT_SHIFT_CSI_WADDR_LATCH) +#define BIT_CLEAR_CSI_WADDR_LATCH(x) ((x) & (~BITS_CSI_WADDR_LATCH)) +#define BIT_GET_CSI_WADDR_LATCH(x) \ + (((x) >> BIT_SHIFT_CSI_WADDR_LATCH) & BIT_MASK_CSI_WADDR_LATCH) +#define BIT_SET_CSI_WADDR_LATCH(x, v) \ + (BIT_CLEAR_CSI_WADDR_LATCH(x) | BIT_CSI_WADDR_LATCH(v)) -#define BIT_SHIFT_WMAC_RESP_MFB 25 -#define BIT_MASK_WMAC_RESP_MFB 0x7f -#define BIT_WMAC_RESP_MFB(x) (((x) & BIT_MASK_WMAC_RESP_MFB) << BIT_SHIFT_WMAC_RESP_MFB) -#define BIT_GET_WMAC_RESP_MFB(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB) & BIT_MASK_WMAC_RESP_MFB) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_ANTINF_SEL 23 -#define BIT_MASK_WMAC_ANTINF_SEL 0x3 -#define BIT_WMAC_ANTINF_SEL(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL) << BIT_SHIFT_WMAC_ANTINF_SEL) -#define BIT_GET_WMAC_ANTINF_SEL(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL) & BIT_MASK_WMAC_ANTINF_SEL) +/* 2 REG_RXCMD_1 (Offset 0x06D4) */ +#define BIT_SHIFT_RXCMD_PRD 0 +#define BIT_MASK_RXCMD_PRD 0xffff +#define BIT_RXCMD_PRD(x) (((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD) +#define BITS_RXCMD_PRD (BIT_MASK_RXCMD_PRD << BIT_SHIFT_RXCMD_PRD) +#define BIT_CLEAR_RXCMD_PRD(x) ((x) & (~BITS_RXCMD_PRD)) +#define BIT_GET_RXCMD_PRD(x) (((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD) +#define BIT_SET_RXCMD_PRD(x, v) (BIT_CLEAR_RXCMD_PRD(x) | BIT_RXCMD_PRD(v)) -#define BIT_SHIFT_WMAC_ANTSEL_SEL 21 -#define BIT_MASK_WMAC_ANTSEL_SEL 0x3 -#define BIT_WMAC_ANTSEL_SEL(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL) << BIT_SHIFT_WMAC_ANTSEL_SEL) -#define BIT_GET_WMAC_ANTSEL_SEL(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL) & BIT_MASK_WMAC_ANTSEL_SEL) +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#define BIT_SHIFT_WMAC_RESP_MFB 25 +#define BIT_MASK_WMAC_RESP_MFB 0x7f +#define BIT_WMAC_RESP_MFB(x) \ + (((x) & BIT_MASK_WMAC_RESP_MFB) << BIT_SHIFT_WMAC_RESP_MFB) +#define BITS_WMAC_RESP_MFB (BIT_MASK_WMAC_RESP_MFB << BIT_SHIFT_WMAC_RESP_MFB) +#define BIT_CLEAR_WMAC_RESP_MFB(x) ((x) & (~BITS_WMAC_RESP_MFB)) +#define BIT_GET_WMAC_RESP_MFB(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_MFB) & BIT_MASK_WMAC_RESP_MFB) +#define BIT_SET_WMAC_RESP_MFB(x, v) \ + (BIT_CLEAR_WMAC_RESP_MFB(x) | BIT_WMAC_RESP_MFB(v)) + +#define BIT_SHIFT_WMAC_ANTINF_SEL 23 +#define BIT_MASK_WMAC_ANTINF_SEL 0x3 +#define BIT_WMAC_ANTINF_SEL(x) \ + (((x) & BIT_MASK_WMAC_ANTINF_SEL) << BIT_SHIFT_WMAC_ANTINF_SEL) +#define BITS_WMAC_ANTINF_SEL \ + (BIT_MASK_WMAC_ANTINF_SEL << BIT_SHIFT_WMAC_ANTINF_SEL) +#define BIT_CLEAR_WMAC_ANTINF_SEL(x) ((x) & (~BITS_WMAC_ANTINF_SEL)) +#define BIT_GET_WMAC_ANTINF_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL) & BIT_MASK_WMAC_ANTINF_SEL) +#define BIT_SET_WMAC_ANTINF_SEL(x, v) \ + (BIT_CLEAR_WMAC_ANTINF_SEL(x) | BIT_WMAC_ANTINF_SEL(v)) + +#define BIT_SHIFT_WMAC_ANTSEL_SEL 21 +#define BIT_MASK_WMAC_ANTSEL_SEL 0x3 +#define BIT_WMAC_ANTSEL_SEL(x) \ + (((x) & BIT_MASK_WMAC_ANTSEL_SEL) << BIT_SHIFT_WMAC_ANTSEL_SEL) +#define BITS_WMAC_ANTSEL_SEL \ + (BIT_MASK_WMAC_ANTSEL_SEL << BIT_SHIFT_WMAC_ANTSEL_SEL) +#define BIT_CLEAR_WMAC_ANTSEL_SEL(x) ((x) & (~BITS_WMAC_ANTSEL_SEL)) +#define BIT_GET_WMAC_ANTSEL_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL) & BIT_MASK_WMAC_ANTSEL_SEL) +#define BIT_SET_WMAC_ANTSEL_SEL(x, v) \ + (BIT_CLEAR_WMAC_ANTSEL_SEL(x) | BIT_WMAC_ANTSEL_SEL(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#define BIT_SHIFT_RESP_TXPOWER 18 +#define BIT_MASK_RESP_TXPOWER 0x7 +#define BIT_RESP_TXPOWER(x) \ + (((x) & BIT_MASK_RESP_TXPOWER) << BIT_SHIFT_RESP_TXPOWER) +#define BITS_RESP_TXPOWER (BIT_MASK_RESP_TXPOWER << BIT_SHIFT_RESP_TXPOWER) +#define BIT_CLEAR_RESP_TXPOWER(x) ((x) & (~BITS_RESP_TXPOWER)) +#define BIT_GET_RESP_TXPOWER(x) \ + (((x) >> BIT_SHIFT_RESP_TXPOWER) & BIT_MASK_RESP_TXPOWER) +#define BIT_SET_RESP_TXPOWER(x, v) \ + (BIT_CLEAR_RESP_TXPOWER(x) | BIT_RESP_TXPOWER(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_RESP_TXPOWER 18 -#define BIT_MASK_RESP_TXPOWER 0x7 -#define BIT_RESP_TXPOWER(x) (((x) & BIT_MASK_RESP_TXPOWER) << BIT_SHIFT_RESP_TXPOWER) -#define BIT_GET_RESP_TXPOWER(x) (((x) >> BIT_SHIFT_RESP_TXPOWER) & BIT_MASK_RESP_TXPOWER) +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#define BIT_SHIFT_R_WMAC_RESP_TXPOWER 18 +#define BIT_MASK_R_WMAC_RESP_TXPOWER 0x7 +#define BIT_R_WMAC_RESP_TXPOWER(x) \ + (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER) << BIT_SHIFT_R_WMAC_RESP_TXPOWER) +#define BITS_R_WMAC_RESP_TXPOWER \ + (BIT_MASK_R_WMAC_RESP_TXPOWER << BIT_SHIFT_R_WMAC_RESP_TXPOWER) +#define BIT_CLEAR_R_WMAC_RESP_TXPOWER(x) ((x) & (~BITS_R_WMAC_RESP_TXPOWER)) +#define BIT_GET_R_WMAC_RESP_TXPOWER(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER) & BIT_MASK_R_WMAC_RESP_TXPOWER) +#define BIT_SET_R_WMAC_RESP_TXPOWER(x, v) \ + (BIT_CLEAR_R_WMAC_RESP_TXPOWER(x) | BIT_R_WMAC_RESP_TXPOWER(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ + +#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE 18 +#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE 0x3 +#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE) \ + << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE) +#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE \ + (BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE \ + << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE) +#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) \ + ((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE)) +#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE) & \ + BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE) +#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) | \ + BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#define BIT_SHIFT_RESP_TXAGC_B 13 +#define BIT_MASK_RESP_TXAGC_B 0x1f +#define BIT_RESP_TXAGC_B(x) \ + (((x) & BIT_MASK_RESP_TXAGC_B) << BIT_SHIFT_RESP_TXAGC_B) +#define BITS_RESP_TXAGC_B (BIT_MASK_RESP_TXAGC_B << BIT_SHIFT_RESP_TXAGC_B) +#define BIT_CLEAR_RESP_TXAGC_B(x) ((x) & (~BITS_RESP_TXAGC_B)) +#define BIT_GET_RESP_TXAGC_B(x) \ + (((x) >> BIT_SHIFT_RESP_TXAGC_B) & BIT_MASK_RESP_TXAGC_B) +#define BIT_SET_RESP_TXAGC_B(x, v) \ + (BIT_CLEAR_RESP_TXAGC_B(x) | BIT_RESP_TXAGC_B(v)) -#define BIT_SHIFT_R_WMAC_RESP_TXPOWER 18 -#define BIT_MASK_R_WMAC_RESP_TXPOWER 0x7 -#define BIT_R_WMAC_RESP_TXPOWER(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER) << BIT_SHIFT_R_WMAC_RESP_TXPOWER) -#define BIT_GET_R_WMAC_RESP_TXPOWER(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER) & BIT_MASK_R_WMAC_RESP_TXPOWER) +#define BIT_SHIFT_RESP_TXAGC_A 8 +#define BIT_MASK_RESP_TXAGC_A 0x1f +#define BIT_RESP_TXAGC_A(x) \ + (((x) & BIT_MASK_RESP_TXAGC_A) << BIT_SHIFT_RESP_TXAGC_A) +#define BITS_RESP_TXAGC_A (BIT_MASK_RESP_TXAGC_A << BIT_SHIFT_RESP_TXAGC_A) +#define BIT_CLEAR_RESP_TXAGC_A(x) ((x) & (~BITS_RESP_TXAGC_A)) +#define BIT_GET_RESP_TXAGC_A(x) \ + (((x) >> BIT_SHIFT_RESP_TXAGC_A) & BIT_MASK_RESP_TXAGC_A) +#define BIT_SET_RESP_TXAGC_A(x, v) \ + (BIT_CLEAR_RESP_TXAGC_A(x) | BIT_RESP_TXAGC_A(v)) +#define BIT_RESP_ANTSEL_B BIT(7) +#define BIT_RESP_ANTSEL_A BIT(6) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ + +#define BIT_SHIFT_WMAC_RESP_TXANT_V1 6 +#define BIT_MASK_WMAC_RESP_TXANT_V1 0xfff +#define BIT_WMAC_RESP_TXANT_V1(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT_V1) << BIT_SHIFT_WMAC_RESP_TXANT_V1) +#define BITS_WMAC_RESP_TXANT_V1 \ + (BIT_MASK_WMAC_RESP_TXANT_V1 << BIT_SHIFT_WMAC_RESP_TXANT_V1) +#define BIT_CLEAR_WMAC_RESP_TXANT_V1(x) ((x) & (~BITS_WMAC_RESP_TXANT_V1)) +#define BIT_GET_WMAC_RESP_TXANT_V1(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1) & BIT_MASK_WMAC_RESP_TXANT_V1) +#define BIT_SET_WMAC_RESP_TXANT_V1(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT_V1(x) | BIT_WMAC_RESP_TXANT_V1(v)) + +#endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ + +#define BIT_SHIFT_RESP_TXANT_CCK 4 +#define BIT_MASK_RESP_TXANT_CCK 0x3 +#define BIT_RESP_TXANT_CCK(x) \ + (((x) & BIT_MASK_RESP_TXANT_CCK) << BIT_SHIFT_RESP_TXANT_CCK) +#define BITS_RESP_TXANT_CCK \ + (BIT_MASK_RESP_TXANT_CCK << BIT_SHIFT_RESP_TXANT_CCK) +#define BIT_CLEAR_RESP_TXANT_CCK(x) ((x) & (~BITS_RESP_TXANT_CCK)) +#define BIT_GET_RESP_TXANT_CCK(x) \ + (((x) >> BIT_SHIFT_RESP_TXANT_CCK) & BIT_MASK_RESP_TXANT_CCK) +#define BIT_SET_RESP_TXANT_CCK(x, v) \ + (BIT_CLEAR_RESP_TXANT_CCK(x) | BIT_RESP_TXANT_CCK(v)) + +#define BIT_SHIFT_RESP_TXANT_L 2 +#define BIT_MASK_RESP_TXANT_L 0x3 +#define BIT_RESP_TXANT_L(x) \ + (((x) & BIT_MASK_RESP_TXANT_L) << BIT_SHIFT_RESP_TXANT_L) +#define BITS_RESP_TXANT_L (BIT_MASK_RESP_TXANT_L << BIT_SHIFT_RESP_TXANT_L) +#define BIT_CLEAR_RESP_TXANT_L(x) ((x) & (~BITS_RESP_TXANT_L)) +#define BIT_GET_RESP_TXANT_L(x) \ + (((x) >> BIT_SHIFT_RESP_TXANT_L) & BIT_MASK_RESP_TXANT_L) +#define BIT_SET_RESP_TXANT_L(x, v) \ + (BIT_CLEAR_RESP_TXANT_L(x) | BIT_RESP_TXANT_L(v)) + +#define BIT_SHIFT_RESP_TXANT_HT 0 +#define BIT_MASK_RESP_TXANT_HT 0x3 +#define BIT_RESP_TXANT_HT(x) \ + (((x) & BIT_MASK_RESP_TXANT_HT) << BIT_SHIFT_RESP_TXANT_HT) +#define BITS_RESP_TXANT_HT (BIT_MASK_RESP_TXANT_HT << BIT_SHIFT_RESP_TXANT_HT) +#define BIT_CLEAR_RESP_TXANT_HT(x) ((x) & (~BITS_RESP_TXANT_HT)) +#define BIT_GET_RESP_TXANT_HT(x) \ + (((x) >> BIT_SHIFT_RESP_TXANT_HT) & BIT_MASK_RESP_TXANT_HT) +#define BIT_SET_RESP_TXANT_HT(x, v) \ + (BIT_CLEAR_RESP_TXANT_HT(x) | BIT_RESP_TXANT_HT(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#define BIT_SHIFT_WMAC_RESP_TXANT 0 +#define BIT_MASK_WMAC_RESP_TXANT 0x3ffff +#define BIT_WMAC_RESP_TXANT(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT) << BIT_SHIFT_WMAC_RESP_TXANT) +#define BITS_WMAC_RESP_TXANT \ + (BIT_MASK_WMAC_RESP_TXANT << BIT_SHIFT_WMAC_RESP_TXANT) +#define BIT_CLEAR_WMAC_RESP_TXANT(x) ((x) & (~BITS_WMAC_RESP_TXANT)) +#define BIT_GET_WMAC_RESP_TXANT(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT) & BIT_MASK_WMAC_RESP_TXANT) +#define BIT_SET_WMAC_RESP_TXANT(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT(x) | BIT_WMAC_RESP_TXANT(v)) -#define BIT_SHIFT_RESP_TXAGC_B 13 -#define BIT_MASK_RESP_TXAGC_B 0x1f -#define BIT_RESP_TXAGC_B(x) (((x) & BIT_MASK_RESP_TXAGC_B) << BIT_SHIFT_RESP_TXAGC_B) -#define BIT_GET_RESP_TXAGC_B(x) (((x) >> BIT_SHIFT_RESP_TXAGC_B) & BIT_MASK_RESP_TXAGC_B) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RESP_TXAGC_A 8 -#define BIT_MASK_RESP_TXAGC_A 0x1f -#define BIT_RESP_TXAGC_A(x) (((x) & BIT_MASK_RESP_TXAGC_A) << BIT_SHIFT_RESP_TXAGC_A) -#define BIT_GET_RESP_TXAGC_A(x) (((x) >> BIT_SHIFT_RESP_TXAGC_A) & BIT_MASK_RESP_TXAGC_A) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ -#define BIT_RESP_ANTSEL_B BIT(7) -#define BIT_RESP_ANTSEL_A BIT(6) +#define BIT_CTL_IDLE_CLR_CSI_RPT BIT(31) -#define BIT_SHIFT_RESP_TXANT_CCK 4 -#define BIT_MASK_RESP_TXANT_CCK 0x3 -#define BIT_RESP_TXANT_CCK(x) (((x) & BIT_MASK_RESP_TXANT_CCK) << BIT_SHIFT_RESP_TXANT_CCK) -#define BIT_GET_RESP_TXANT_CCK(x) (((x) >> BIT_SHIFT_RESP_TXANT_CCK) & BIT_MASK_RESP_TXANT_CCK) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RESP_TXANT_L 2 -#define BIT_MASK_RESP_TXANT_L 0x3 -#define BIT_RESP_TXANT_L(x) (((x) & BIT_MASK_RESP_TXANT_L) << BIT_SHIFT_RESP_TXANT_L) -#define BIT_GET_RESP_TXANT_L(x) (((x) >> BIT_SHIFT_RESP_TXANT_L) & BIT_MASK_RESP_TXANT_L) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_WMAC_USE_NDPARATE BIT(30) -#define BIT_SHIFT_RESP_TXANT_HT 0 -#define BIT_MASK_RESP_TXANT_HT 0x3 -#define BIT_RESP_TXANT_HT(x) (((x) & BIT_MASK_RESP_TXANT_HT) << BIT_SHIFT_RESP_TXANT_HT) -#define BIT_GET_RESP_TXANT_HT(x) (((x) >> BIT_SHIFT_RESP_TXANT_HT) & BIT_MASK_RESP_TXANT_HT) +#define BIT_SHIFT_WMAC_CSI_RATE 24 +#define BIT_MASK_WMAC_CSI_RATE 0x3f +#define BIT_WMAC_CSI_RATE(x) \ + (((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE) +#define BITS_WMAC_CSI_RATE (BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE) +#define BIT_CLEAR_WMAC_CSI_RATE(x) ((x) & (~BITS_WMAC_CSI_RATE)) +#define BIT_GET_WMAC_CSI_RATE(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE) +#define BIT_SET_WMAC_CSI_RATE(x, v) \ + (BIT_CLEAR_WMAC_CSI_RATE(x) | BIT_WMAC_CSI_RATE(v)) +#define BIT_SHIFT_WMAC_RESP_TXRATE 16 +#define BIT_MASK_WMAC_RESP_TXRATE 0xff +#define BIT_WMAC_RESP_TXRATE(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXRATE) << BIT_SHIFT_WMAC_RESP_TXRATE) +#define BITS_WMAC_RESP_TXRATE \ + (BIT_MASK_WMAC_RESP_TXRATE << BIT_SHIFT_WMAC_RESP_TXRATE) +#define BIT_CLEAR_WMAC_RESP_TXRATE(x) ((x) & (~BITS_WMAC_RESP_TXRATE)) +#define BIT_GET_WMAC_RESP_TXRATE(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE) & BIT_MASK_WMAC_RESP_TXRATE) +#define BIT_SET_WMAC_RESP_TXRATE(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXRATE(x) | BIT_WMAC_RESP_TXRATE(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_WMAC_CSI_RATE_FORCE_EN BIT(15) -/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) -#define BIT_SHIFT_WMAC_RESP_TXANT 0 -#define BIT_MASK_WMAC_RESP_TXANT 0x3ffff -#define BIT_WMAC_RESP_TXANT(x) (((x) & BIT_MASK_WMAC_RESP_TXANT) << BIT_SHIFT_WMAC_RESP_TXANT) -#define BIT_GET_WMAC_RESP_TXANT(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT) & BIT_MASK_WMAC_RESP_TXANT) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_CSI_FORCE_RATE_EN BIT(15) #endif +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ + +#define BIT_SHIFT_WMAC_CSI_RSC_FORCE 13 +#define BIT_MASK_WMAC_CSI_RSC_FORCE 0x3 +#define BIT_WMAC_CSI_RSC_FORCE(x) \ + (((x) & BIT_MASK_WMAC_CSI_RSC_FORCE) << BIT_SHIFT_WMAC_CSI_RSC_FORCE) +#define BITS_WMAC_CSI_RSC_FORCE \ + (BIT_MASK_WMAC_CSI_RSC_FORCE << BIT_SHIFT_WMAC_CSI_RSC_FORCE) +#define BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) ((x) & (~BITS_WMAC_CSI_RSC_FORCE)) +#define BIT_GET_WMAC_CSI_RSC_FORCE(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RSC_FORCE) & BIT_MASK_WMAC_CSI_RSC_FORCE) +#define BIT_SET_WMAC_CSI_RSC_FORCE(x, v) \ + (BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) | BIT_WMAC_CSI_RSC_FORCE(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ -#define BIT_CTL_IDLE_CLR_CSI_RPT BIT(31) +#define BIT_SHIFT_CSI_RSC 13 +#define BIT_MASK_CSI_RSC 0x3 +#define BIT_CSI_RSC(x) (((x) & BIT_MASK_CSI_RSC) << BIT_SHIFT_CSI_RSC) +#define BITS_CSI_RSC (BIT_MASK_CSI_RSC << BIT_SHIFT_CSI_RSC) +#define BIT_CLEAR_CSI_RSC(x) ((x) & (~BITS_CSI_RSC)) +#define BIT_GET_CSI_RSC(x) (((x) >> BIT_SHIFT_CSI_RSC) & BIT_MASK_CSI_RSC) +#define BIT_SET_CSI_RSC(x, v) (BIT_CLEAR_CSI_RSC(x) | BIT_CSI_RSC(v)) #endif +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ + +#define BIT_WMAC_CSI_GID_SEL BIT(12) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ -#define BIT_WMAC_USE_NDPARATE BIT(30) +#define BIT_CSI_GID_SEL BIT(12) -#define BIT_SHIFT_WMAC_CSI_RATE 24 -#define BIT_MASK_WMAC_CSI_RATE 0x3f -#define BIT_WMAC_CSI_RATE(x) (((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE) -#define BIT_GET_WMAC_CSI_RATE(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE) +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) -#define BIT_SHIFT_WMAC_RESP_TXRATE 16 -#define BIT_MASK_WMAC_RESP_TXRATE 0xff -#define BIT_WMAC_RESP_TXRATE(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE) << BIT_SHIFT_WMAC_RESP_TXRATE) -#define BIT_GET_WMAC_RESP_TXRATE(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE) & BIT_MASK_WMAC_RESP_TXRATE) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_RDCSIMD_FLAG_TRIG_SEL BIT(11) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1 BIT(10) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_NDPVLD_PROTECT_RDRDY_DIS BIT(9) -/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#endif -#define BIT_CSI_FORCE_RATE_EN BIT(15) +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_CSI_RSC 13 -#define BIT_MASK_CSI_RSC 0x3 -#define BIT_CSI_RSC(x) (((x) & BIT_MASK_CSI_RSC) << BIT_SHIFT_CSI_RSC) -#define BIT_GET_CSI_RSC(x) (((x) >> BIT_SHIFT_CSI_RSC) & BIT_MASK_CSI_RSC) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ -#define BIT_CSI_GID_SEL BIT(12) -#define BIT_RDCSIMD_FLAG_TRIG_SEL BIT(11) -#define BIT_NDPVLD_POS_RST_FFPTR_DIS BIT(10) -#define BIT_NDPVLD_PROTECT_RDRDY_DIS BIT(9) -#define BIT_RDCSI_EMPTY_APPZERO BIT(8) +#define BIT_CSIRD_EMPTY_APPZERO BIT(8) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ + +#define BIT_RDCSI_EMPTY_APPZERO BIT(8) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ -#define BIT_BBPSF_MPDUCHKEN BIT(5) +#define BIT_WMC_CSI_RATE_FB_EN BIT(7) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_CSI_RATE_FB_EN BIT(7) -/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#endif -#define BIT_BBPSF_MHCHKEN BIT(4) -#define BIT_BBPSF_ERRCHKEN BIT(3) +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BBPSF_ERRTHR 0 -#define BIT_MASK_BBPSF_ERRTHR 0x7 -#define BIT_BBPSF_ERRTHR(x) (((x) & BIT_MASK_BBPSF_ERRTHR) << BIT_SHIFT_BBPSF_ERRTHR) -#define BIT_GET_BBPSF_ERRTHR(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR) & BIT_MASK_BBPSF_ERRTHR) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_RXFIFO_WRPTR_WO_CHKSUM BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_BBPSF_MPDUCHKEN BIT(5) -/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ +#endif -#define BIT_NOA_PARSER_EN BIT(15) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ + +#define BIT_BBPSF_MHCHKEN BIT(4) +#define BIT_BBPSF_ERRCHKEN BIT(3) +#define BIT_SHIFT_BBPSF_ERRTHR 0 +#define BIT_MASK_BBPSF_ERRTHR 0x7 +#define BIT_BBPSF_ERRTHR(x) \ + (((x) & BIT_MASK_BBPSF_ERRTHR) << BIT_SHIFT_BBPSF_ERRTHR) +#define BITS_BBPSF_ERRTHR (BIT_MASK_BBPSF_ERRTHR << BIT_SHIFT_BBPSF_ERRTHR) +#define BIT_CLEAR_BBPSF_ERRTHR(x) ((x) & (~BITS_BBPSF_ERRTHR)) +#define BIT_GET_BBPSF_ERRTHR(x) \ + (((x) >> BIT_SHIFT_BBPSF_ERRTHR) & BIT_MASK_BBPSF_ERRTHR) +#define BIT_SET_BBPSF_ERRTHR(x, v) \ + (BIT_CLEAR_BBPSF_ERRTHR(x) | BIT_BBPSF_ERRTHR(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ -#define BIT_BSSID_SEL BIT(14) +#define BIT_NOA_PARSER_EN BIT(15) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ +#define BIT_BSSID_SEL BIT(14) -#define BIT_SHIFT_BSSID_SEL 12 -#define BIT_MASK_BSSID_SEL 0x7 -#define BIT_BSSID_SEL(x) (((x) & BIT_MASK_BSSID_SEL) << BIT_SHIFT_BSSID_SEL) -#define BIT_GET_BSSID_SEL(x) (((x) >> BIT_SHIFT_BSSID_SEL) & BIT_MASK_BSSID_SEL) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ +#define BIT_SHIFT_BSSID_SEL_V1 12 +#define BIT_MASK_BSSID_SEL_V1 0x7 +#define BIT_BSSID_SEL_V1(x) \ + (((x) & BIT_MASK_BSSID_SEL_V1) << BIT_SHIFT_BSSID_SEL_V1) +#define BITS_BSSID_SEL_V1 (BIT_MASK_BSSID_SEL_V1 << BIT_SHIFT_BSSID_SEL_V1) +#define BIT_CLEAR_BSSID_SEL_V1(x) ((x) & (~BITS_BSSID_SEL_V1)) +#define BIT_GET_BSSID_SEL_V1(x) \ + (((x) >> BIT_SHIFT_BSSID_SEL_V1) & BIT_MASK_BSSID_SEL_V1) +#define BIT_SET_BSSID_SEL_V1(x, v) \ + (BIT_CLEAR_BSSID_SEL_V1(x) | BIT_BSSID_SEL_V1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ +#define BIT_SHIFT_P2P_OUI_TYPE 0 +#define BIT_MASK_P2P_OUI_TYPE 0xff +#define BIT_P2P_OUI_TYPE(x) \ + (((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE) +#define BITS_P2P_OUI_TYPE (BIT_MASK_P2P_OUI_TYPE << BIT_SHIFT_P2P_OUI_TYPE) +#define BIT_CLEAR_P2P_OUI_TYPE(x) ((x) & (~BITS_P2P_OUI_TYPE)) +#define BIT_GET_P2P_OUI_TYPE(x) \ + (((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE) +#define BIT_SET_P2P_OUI_TYPE(x, v) \ + (BIT_CLEAR_P2P_OUI_TYPE(x) | BIT_P2P_OUI_TYPE(v)) -#define BIT_SHIFT_P2P_OUI_TYPE 0 -#define BIT_MASK_P2P_OUI_TYPE 0xff -#define BIT_P2P_OUI_TYPE(x) (((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE) -#define BIT_GET_P2P_OUI_TYPE(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_ASSOCIATED_BFMER0_INFO (Offset 0x06E4) */ +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 0xffffffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) +#define BITS_R_WMAC_SOUNDING_RXADD_R0 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0(v)) -#define BIT_SHIFT_R_WMAC_TXCSI_AID0 (48 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_TXCSI_AID0 0x1ff -#define BIT_R_WMAC_TXCSI_AID0(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0) << BIT_SHIFT_R_WMAC_TXCSI_AID0) -#define BIT_GET_R_WMAC_TXCSI_AID0(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0) & BIT_MASK_R_WMAC_TXCSI_AID0) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0 0 -#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R0(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) +/* 2 REG_ASSOCIATED_BFMER0_INFO (Offset 0x06E4) */ +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_V1(v)) + +/* 2 REG_ASSOCIATED_BFMER0_INFO_H (Offset 0x06E8) */ + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_ASSOCIATED_BFMER1_INFO (Offset 0x06EC) */ +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 0xffffffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) +#define BITS_R_WMAC_SOUNDING_RXADD_R1 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1(v)) -#define BIT_SHIFT_R_WMAC_TXCSI_AID1 (48 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_TXCSI_AID1 0x1ff -#define BIT_R_WMAC_TXCSI_AID1(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1) << BIT_SHIFT_R_WMAC_TXCSI_AID1) -#define BIT_GET_R_WMAC_TXCSI_AID1(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1) & BIT_MASK_R_WMAC_TXCSI_AID1) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1 0 -#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R1(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) +/* 2 REG_ASSOCIATED_BFMER1_INFO (Offset 0x06EC) */ +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_V1(v)) + +/* 2 REG_ASSOCIATED_BFMER1_INFO_H (Offset 0x06F0) */ + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_TX_CSI_RPT_PARAM_BW20 (Offset 0x06F4) */ +#define BIT_SHIFT_R_WMAC_BFINFO_20M_1 16 +#define BIT_MASK_R_WMAC_BFINFO_20M_1 0xfff +#define BIT_R_WMAC_BFINFO_20M_1(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1) +#define BITS_R_WMAC_BFINFO_20M_1 \ + (BIT_MASK_R_WMAC_BFINFO_20M_1 << BIT_SHIFT_R_WMAC_BFINFO_20M_1) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_1)) +#define BIT_GET_R_WMAC_BFINFO_20M_1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1) +#define BIT_SET_R_WMAC_BFINFO_20M_1(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) | BIT_R_WMAC_BFINFO_20M_1(v)) -#define BIT_SHIFT_R_WMAC_BFINFO_20M_1 16 -#define BIT_MASK_R_WMAC_BFINFO_20M_1 0xfff -#define BIT_R_WMAC_BFINFO_20M_1(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1) -#define BIT_GET_R_WMAC_BFINFO_20M_1(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1) - - -#define BIT_SHIFT_R_WMAC_BFINFO_20M_0 0 -#define BIT_MASK_R_WMAC_BFINFO_20M_0 0xfff -#define BIT_R_WMAC_BFINFO_20M_0(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0) -#define BIT_GET_R_WMAC_BFINFO_20M_0(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0) - +#define BIT_SHIFT_R_WMAC_BFINFO_20M_0 0 +#define BIT_MASK_R_WMAC_BFINFO_20M_0 0xfff +#define BIT_R_WMAC_BFINFO_20M_0(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0) +#define BITS_R_WMAC_BFINFO_20M_0 \ + (BIT_MASK_R_WMAC_BFINFO_20M_0 << BIT_SHIFT_R_WMAC_BFINFO_20M_0) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_0)) +#define BIT_GET_R_WMAC_BFINFO_20M_0(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0) +#define BIT_SET_R_WMAC_BFINFO_20M_0(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) | BIT_R_WMAC_BFINFO_20M_0(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ +#define BIT_SHIFT_R_WMAC_BFINFO_40M_1 13 +#define BIT_MASK_R_WMAC_BFINFO_40M_1 0x7fff +#define BIT_R_WMAC_BFINFO_40M_1(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_40M_1) << BIT_SHIFT_R_WMAC_BFINFO_40M_1) +#define BITS_R_WMAC_BFINFO_40M_1 \ + (BIT_MASK_R_WMAC_BFINFO_40M_1 << BIT_SHIFT_R_WMAC_BFINFO_40M_1) +#define BIT_CLEAR_R_WMAC_BFINFO_40M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_40M_1)) +#define BIT_GET_R_WMAC_BFINFO_40M_1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_1) & BIT_MASK_R_WMAC_BFINFO_40M_1) +#define BIT_SET_R_WMAC_BFINFO_40M_1(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_40M_1(x) | BIT_R_WMAC_BFINFO_40M_1(v)) -#define BIT_SHIFT_R_WMAC_BFINFO_40M_1 13 -#define BIT_MASK_R_WMAC_BFINFO_40M_1 0x7fff -#define BIT_R_WMAC_BFINFO_40M_1(x) (((x) & BIT_MASK_R_WMAC_BFINFO_40M_1) << BIT_SHIFT_R_WMAC_BFINFO_40M_1) -#define BIT_GET_R_WMAC_BFINFO_40M_1(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_1) & BIT_MASK_R_WMAC_BFINFO_40M_1) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_BFINFO_40M_0 0 -#define BIT_MASK_R_WMAC_BFINFO_40M_0 0xfff -#define BIT_R_WMAC_BFINFO_40M_0(x) (((x) & BIT_MASK_R_WMAC_BFINFO_40M_0) << BIT_SHIFT_R_WMAC_BFINFO_40M_0) -#define BIT_GET_R_WMAC_BFINFO_40M_0(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_0) & BIT_MASK_R_WMAC_BFINFO_40M_0) +/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ +#define BIT_SHIFT_WMAC_RESP_ANTD 12 +#define BIT_MASK_WMAC_RESP_ANTD 0xf +#define BIT_WMAC_RESP_ANTD(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTD) << BIT_SHIFT_WMAC_RESP_ANTD) +#define BITS_WMAC_RESP_ANTD \ + (BIT_MASK_WMAC_RESP_ANTD << BIT_SHIFT_WMAC_RESP_ANTD) +#define BIT_CLEAR_WMAC_RESP_ANTD(x) ((x) & (~BITS_WMAC_RESP_ANTD)) +#define BIT_GET_WMAC_RESP_ANTD(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTD) & BIT_MASK_WMAC_RESP_ANTD) +#define BIT_SET_WMAC_RESP_ANTD(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTD(x) | BIT_WMAC_RESP_ANTD(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTC 8 +#define BIT_MASK_WMAC_RESP_ANTC 0xf +#define BIT_WMAC_RESP_ANTC(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTC) << BIT_SHIFT_WMAC_RESP_ANTC) +#define BITS_WMAC_RESP_ANTC \ + (BIT_MASK_WMAC_RESP_ANTC << BIT_SHIFT_WMAC_RESP_ANTC) +#define BIT_CLEAR_WMAC_RESP_ANTC(x) ((x) & (~BITS_WMAC_RESP_ANTC)) +#define BIT_GET_WMAC_RESP_ANTC(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTC) & BIT_MASK_WMAC_RESP_ANTC) +#define BIT_SET_WMAC_RESP_ANTC(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTC(x) | BIT_WMAC_RESP_ANTC(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTB 4 +#define BIT_MASK_WMAC_RESP_ANTB 0xf +#define BIT_WMAC_RESP_ANTB(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTB) << BIT_SHIFT_WMAC_RESP_ANTB) +#define BITS_WMAC_RESP_ANTB \ + (BIT_MASK_WMAC_RESP_ANTB << BIT_SHIFT_WMAC_RESP_ANTB) +#define BIT_CLEAR_WMAC_RESP_ANTB(x) ((x) & (~BITS_WMAC_RESP_ANTB)) +#define BIT_GET_WMAC_RESP_ANTB(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTB) & BIT_MASK_WMAC_RESP_ANTB) +#define BIT_SET_WMAC_RESP_ANTB(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTB(x) | BIT_WMAC_RESP_ANTB(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ +#define BIT_SHIFT_R_WMAC_BFINFO_40M_0 0 +#define BIT_MASK_R_WMAC_BFINFO_40M_0 0xfff +#define BIT_R_WMAC_BFINFO_40M_0(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_40M_0) << BIT_SHIFT_R_WMAC_BFINFO_40M_0) +#define BITS_R_WMAC_BFINFO_40M_0 \ + (BIT_MASK_R_WMAC_BFINFO_40M_0 << BIT_SHIFT_R_WMAC_BFINFO_40M_0) +#define BIT_CLEAR_R_WMAC_BFINFO_40M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_40M_0)) +#define BIT_GET_R_WMAC_BFINFO_40M_0(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_0) & BIT_MASK_R_WMAC_BFINFO_40M_0) +#define BIT_SET_R_WMAC_BFINFO_40M_0(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_40M_0(x) | BIT_R_WMAC_BFINFO_40M_0(v)) -/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_WMAC_RESP_ANTCD 0 -#define BIT_MASK_WMAC_RESP_ANTCD 0xf -#define BIT_WMAC_RESP_ANTCD(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD) << BIT_SHIFT_WMAC_RESP_ANTCD) -#define BIT_GET_WMAC_RESP_ANTCD(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD) & BIT_MASK_WMAC_RESP_ANTCD) +/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ +#define BIT_SHIFT_WMAC_RESP_ANTCD 0 +#define BIT_MASK_WMAC_RESP_ANTCD 0xf +#define BIT_WMAC_RESP_ANTCD(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTCD) << BIT_SHIFT_WMAC_RESP_ANTCD) +#define BITS_WMAC_RESP_ANTCD \ + (BIT_MASK_WMAC_RESP_ANTCD << BIT_SHIFT_WMAC_RESP_ANTCD) +#define BIT_CLEAR_WMAC_RESP_ANTCD(x) ((x) & (~BITS_WMAC_RESP_ANTCD)) +#define BIT_GET_WMAC_RESP_ANTCD(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD) & BIT_MASK_WMAC_RESP_ANTCD) +#define BIT_SET_WMAC_RESP_ANTCD(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTCD(x) | BIT_WMAC_RESP_ANTCD(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ +#define BIT_SHIFT_WMAC_RESP_ANTA 0 +#define BIT_MASK_WMAC_RESP_ANTA 0xf +#define BIT_WMAC_RESP_ANTA(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTA) << BIT_SHIFT_WMAC_RESP_ANTA) +#define BITS_WMAC_RESP_ANTA \ + (BIT_MASK_WMAC_RESP_ANTA << BIT_SHIFT_WMAC_RESP_ANTA) +#define BIT_CLEAR_WMAC_RESP_ANTA(x) ((x) & (~BITS_WMAC_RESP_ANTA)) +#define BIT_GET_WMAC_RESP_ANTA(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTA) & BIT_MASK_WMAC_RESP_ANTA) +#define BIT_SET_WMAC_RESP_ANTA(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTA(x) | BIT_WMAC_RESP_ANTA(v)) -/* 2 REG_TX_CSI_RPT_PARAM_BW80 (Offset 0x06FC) */ +#endif + +#if (HALMAC_8198F_SUPPORT) +/* 2 REG_CSI_RRSR_V1 (Offset 0x06FC) */ -#define BIT_SHIFT_R_WMAC_BFINFO_80M_1 16 -#define BIT_MASK_R_WMAC_BFINFO_80M_1 0xfff -#define BIT_R_WMAC_BFINFO_80M_1(x) (((x) & BIT_MASK_R_WMAC_BFINFO_80M_1) << BIT_SHIFT_R_WMAC_BFINFO_80M_1) -#define BIT_GET_R_WMAC_BFINFO_80M_1(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_1) & BIT_MASK_R_WMAC_BFINFO_80M_1) +#define BIT_WMAC_CSI_LDPC_EN BIT(29) +#define BIT_WMAC_CSI_STBC_EN BIT(28) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_BFINFO_80M_0 0 -#define BIT_MASK_R_WMAC_BFINFO_80M_0 0xfff -#define BIT_R_WMAC_BFINFO_80M_0(x) (((x) & BIT_MASK_R_WMAC_BFINFO_80M_0) << BIT_SHIFT_R_WMAC_BFINFO_80M_0) -#define BIT_GET_R_WMAC_BFINFO_80M_0(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_0) & BIT_MASK_R_WMAC_BFINFO_80M_0) +/* 2 REG_TX_CSI_RPT_PARAM_BW80 (Offset 0x06FC) */ +#define BIT_SHIFT_R_WMAC_BFINFO_80M_1 16 +#define BIT_MASK_R_WMAC_BFINFO_80M_1 0xfff +#define BIT_R_WMAC_BFINFO_80M_1(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_80M_1) << BIT_SHIFT_R_WMAC_BFINFO_80M_1) +#define BITS_R_WMAC_BFINFO_80M_1 \ + (BIT_MASK_R_WMAC_BFINFO_80M_1 << BIT_SHIFT_R_WMAC_BFINFO_80M_1) +#define BIT_CLEAR_R_WMAC_BFINFO_80M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_80M_1)) +#define BIT_GET_R_WMAC_BFINFO_80M_1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_1) & BIT_MASK_R_WMAC_BFINFO_80M_1) +#define BIT_SET_R_WMAC_BFINFO_80M_1(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_80M_1(x) | BIT_R_WMAC_BFINFO_80M_1(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CSI_PTR (Offset 0x06FC) */ +#define BIT_SHIFT_CSI_RADDR_LATCH_V2 16 +#define BIT_MASK_CSI_RADDR_LATCH_V2 0xffff +#define BIT_CSI_RADDR_LATCH_V2(x) \ + (((x) & BIT_MASK_CSI_RADDR_LATCH_V2) << BIT_SHIFT_CSI_RADDR_LATCH_V2) +#define BITS_CSI_RADDR_LATCH_V2 \ + (BIT_MASK_CSI_RADDR_LATCH_V2 << BIT_SHIFT_CSI_RADDR_LATCH_V2) +#define BIT_CLEAR_CSI_RADDR_LATCH_V2(x) ((x) & (~BITS_CSI_RADDR_LATCH_V2)) +#define BIT_GET_CSI_RADDR_LATCH_V2(x) \ + (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V2) & BIT_MASK_CSI_RADDR_LATCH_V2) +#define BIT_SET_CSI_RADDR_LATCH_V2(x, v) \ + (BIT_CLEAR_CSI_RADDR_LATCH_V2(x) | BIT_CSI_RADDR_LATCH_V2(v)) -/* 2 REG_MACID1 (Offset 0x0700) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_MACID1 0 -#define BIT_MASK_MACID1 0xffffffffffffL -#define BIT_MACID1(x) (((x) & BIT_MASK_MACID1) << BIT_SHIFT_MACID1) -#define BIT_GET_MACID1(x) (((x) >> BIT_SHIFT_MACID1) & BIT_MASK_MACID1) +/* 2 REG_CSI_RRSR_V1 (Offset 0x06FC) */ +#define BIT_SHIFT_WMAC_CSI_RRSC_BITMAP 4 +#define BIT_MASK_WMAC_CSI_RRSC_BITMAP 0xffffff +#define BIT_WMAC_CSI_RRSC_BITMAP(x) \ + (((x) & BIT_MASK_WMAC_CSI_RRSC_BITMAP) \ + << BIT_SHIFT_WMAC_CSI_RRSC_BITMAP) +#define BITS_WMAC_CSI_RRSC_BITMAP \ + (BIT_MASK_WMAC_CSI_RRSC_BITMAP << BIT_SHIFT_WMAC_CSI_RRSC_BITMAP) +#define BIT_CLEAR_WMAC_CSI_RRSC_BITMAP(x) ((x) & (~BITS_WMAC_CSI_RRSC_BITMAP)) +#define BIT_GET_WMAC_CSI_RRSC_BITMAP(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RRSC_BITMAP) & \ + BIT_MASK_WMAC_CSI_RRSC_BITMAP) +#define BIT_SET_WMAC_CSI_RRSC_BITMAP(x, v) \ + (BIT_CLEAR_WMAC_CSI_RRSC_BITMAP(x) | BIT_WMAC_CSI_RRSC_BITMAP(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_TX_CSI_RPT_PARAM_BW80 (Offset 0x06FC) */ +#define BIT_SHIFT_R_WMAC_BFINFO_80M_0 0 +#define BIT_MASK_R_WMAC_BFINFO_80M_0 0xfff +#define BIT_R_WMAC_BFINFO_80M_0(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_80M_0) << BIT_SHIFT_R_WMAC_BFINFO_80M_0) +#define BITS_R_WMAC_BFINFO_80M_0 \ + (BIT_MASK_R_WMAC_BFINFO_80M_0 << BIT_SHIFT_R_WMAC_BFINFO_80M_0) +#define BIT_CLEAR_R_WMAC_BFINFO_80M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_80M_0)) +#define BIT_GET_R_WMAC_BFINFO_80M_0(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_0) & BIT_MASK_R_WMAC_BFINFO_80M_0) +#define BIT_SET_R_WMAC_BFINFO_80M_0(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_80M_0(x) | BIT_R_WMAC_BFINFO_80M_0(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_CSI_RRSR_V1 (Offset 0x06FC) */ + +#define BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH 0 +#define BIT_MASK_WMAC_CSI_OFDM_LEN_TH 0xf +#define BIT_WMAC_CSI_OFDM_LEN_TH(x) \ + (((x) & BIT_MASK_WMAC_CSI_OFDM_LEN_TH) \ + << BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH) +#define BITS_WMAC_CSI_OFDM_LEN_TH \ + (BIT_MASK_WMAC_CSI_OFDM_LEN_TH << BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH) +#define BIT_CLEAR_WMAC_CSI_OFDM_LEN_TH(x) ((x) & (~BITS_WMAC_CSI_OFDM_LEN_TH)) +#define BIT_GET_WMAC_CSI_OFDM_LEN_TH(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH) & \ + BIT_MASK_WMAC_CSI_OFDM_LEN_TH) +#define BIT_SET_WMAC_CSI_OFDM_LEN_TH(x, v) \ + (BIT_CLEAR_WMAC_CSI_OFDM_LEN_TH(x) | BIT_WMAC_CSI_OFDM_LEN_TH(v)) + +#define BIT_SHIFT_CSI_PARA_RDY_DLYCNT 0 +#define BIT_MASK_CSI_PARA_RDY_DLYCNT 0x1f +#define BIT_CSI_PARA_RDY_DLYCNT(x) \ + (((x) & BIT_MASK_CSI_PARA_RDY_DLYCNT) << BIT_SHIFT_CSI_PARA_RDY_DLYCNT) +#define BITS_CSI_PARA_RDY_DLYCNT \ + (BIT_MASK_CSI_PARA_RDY_DLYCNT << BIT_SHIFT_CSI_PARA_RDY_DLYCNT) +#define BIT_CLEAR_CSI_PARA_RDY_DLYCNT(x) ((x) & (~BITS_CSI_PARA_RDY_DLYCNT)) +#define BIT_GET_CSI_PARA_RDY_DLYCNT(x) \ + (((x) >> BIT_SHIFT_CSI_PARA_RDY_DLYCNT) & BIT_MASK_CSI_PARA_RDY_DLYCNT) +#define BIT_SET_CSI_PARA_RDY_DLYCNT(x, v) \ + (BIT_CLEAR_CSI_PARA_RDY_DLYCNT(x) | BIT_CSI_PARA_RDY_DLYCNT(v)) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_CSI_PTR (Offset 0x06FC) */ + +#define BIT_SHIFT_CSI_WADDR_LATCH_V2 0 +#define BIT_MASK_CSI_WADDR_LATCH_V2 0xffff +#define BIT_CSI_WADDR_LATCH_V2(x) \ + (((x) & BIT_MASK_CSI_WADDR_LATCH_V2) << BIT_SHIFT_CSI_WADDR_LATCH_V2) +#define BITS_CSI_WADDR_LATCH_V2 \ + (BIT_MASK_CSI_WADDR_LATCH_V2 << BIT_SHIFT_CSI_WADDR_LATCH_V2) +#define BIT_CLEAR_CSI_WADDR_LATCH_V2(x) ((x) & (~BITS_CSI_WADDR_LATCH_V2)) +#define BIT_GET_CSI_WADDR_LATCH_V2(x) \ + (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V2) & BIT_MASK_CSI_WADDR_LATCH_V2) +#define BIT_SET_CSI_WADDR_LATCH_V2(x, v) \ + (BIT_CLEAR_CSI_WADDR_LATCH_V2(x) | BIT_CSI_WADDR_LATCH_V2(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_MACID1 (Offset 0x0700) */ +#define BIT_SHIFT_MACID1 0 +#define BIT_MASK_MACID1 0xffffffffffffL +#define BIT_MACID1(x) (((x) & BIT_MASK_MACID1) << BIT_SHIFT_MACID1) +#define BITS_MACID1 (BIT_MASK_MACID1 << BIT_SHIFT_MACID1) +#define BIT_CLEAR_MACID1(x) ((x) & (~BITS_MACID1)) +#define BIT_GET_MACID1(x) (((x) >> BIT_SHIFT_MACID1) & BIT_MASK_MACID1) +#define BIT_SET_MACID1(x, v) (BIT_CLEAR_MACID1(x) | BIT_MACID1(v)) -#define BIT_SHIFT_MACID1_0 0 -#define BIT_MASK_MACID1_0 0xffffffffL -#define BIT_MACID1_0(x) (((x) & BIT_MASK_MACID1_0) << BIT_SHIFT_MACID1_0) -#define BIT_GET_MACID1_0(x) (((x) >> BIT_SHIFT_MACID1_0) & BIT_MASK_MACID1_0) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_MACID1_1 (Offset 0x0704) */ +/* 2 REG_MACID1 (Offset 0x0700) */ +#define BIT_SHIFT_MACID1_0 0 +#define BIT_MASK_MACID1_0 0xffffffffL +#define BIT_MACID1_0(x) (((x) & BIT_MASK_MACID1_0) << BIT_SHIFT_MACID1_0) +#define BITS_MACID1_0 (BIT_MASK_MACID1_0 << BIT_SHIFT_MACID1_0) +#define BIT_CLEAR_MACID1_0(x) ((x) & (~BITS_MACID1_0)) +#define BIT_GET_MACID1_0(x) (((x) >> BIT_SHIFT_MACID1_0) & BIT_MASK_MACID1_0) +#define BIT_SET_MACID1_0(x, v) (BIT_CLEAR_MACID1_0(x) | BIT_MACID1_0(v)) -#define BIT_SHIFT_MACID1_1 0 -#define BIT_MASK_MACID1_1 0xffff -#define BIT_MACID1_1(x) (((x) & BIT_MASK_MACID1_1) << BIT_SHIFT_MACID1_1) -#define BIT_GET_MACID1_1(x) (((x) >> BIT_SHIFT_MACID1_1) & BIT_MASK_MACID1_1) +/* 2 REG_MACID1_1 (Offset 0x0704) */ +#define BIT_SHIFT_MACID1_1 0 +#define BIT_MASK_MACID1_1 0xffff +#define BIT_MACID1_1(x) (((x) & BIT_MASK_MACID1_1) << BIT_SHIFT_MACID1_1) +#define BITS_MACID1_1 (BIT_MASK_MACID1_1 << BIT_SHIFT_MACID1_1) +#define BIT_CLEAR_MACID1_1(x) ((x) & (~BITS_MACID1_1)) +#define BIT_GET_MACID1_1(x) (((x) >> BIT_SHIFT_MACID1_1) & BIT_MASK_MACID1_1) +#define BIT_SET_MACID1_1(x, v) (BIT_CLEAR_MACID1_1(x) | BIT_MACID1_1(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BSSID1 (Offset 0x0708) */ - -#define BIT_SHIFT_BSSID1 0 -#define BIT_MASK_BSSID1 0xffffffffffffL -#define BIT_BSSID1(x) (((x) & BIT_MASK_BSSID1) << BIT_SHIFT_BSSID1) -#define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1) - +#define BIT_SHIFT_BSSID1 0 +#define BIT_MASK_BSSID1 0xffffffffffffL +#define BIT_BSSID1(x) (((x) & BIT_MASK_BSSID1) << BIT_SHIFT_BSSID1) +#define BITS_BSSID1 (BIT_MASK_BSSID1 << BIT_SHIFT_BSSID1) +#define BIT_CLEAR_BSSID1(x) ((x) & (~BITS_BSSID1)) +#define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1) +#define BIT_SET_BSSID1(x, v) (BIT_CLEAR_BSSID1(x) | BIT_BSSID1(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BSSID1 (Offset 0x0708) */ +#define BIT_SHIFT_BSSID1_0 0 +#define BIT_MASK_BSSID1_0 0xffffffffL +#define BIT_BSSID1_0(x) (((x) & BIT_MASK_BSSID1_0) << BIT_SHIFT_BSSID1_0) +#define BITS_BSSID1_0 (BIT_MASK_BSSID1_0 << BIT_SHIFT_BSSID1_0) +#define BIT_CLEAR_BSSID1_0(x) ((x) & (~BITS_BSSID1_0)) +#define BIT_GET_BSSID1_0(x) (((x) >> BIT_SHIFT_BSSID1_0) & BIT_MASK_BSSID1_0) +#define BIT_SET_BSSID1_0(x, v) (BIT_CLEAR_BSSID1_0(x) | BIT_BSSID1_0(v)) -#define BIT_SHIFT_BSSID1_0 0 -#define BIT_MASK_BSSID1_0 0xffffffffL -#define BIT_BSSID1_0(x) (((x) & BIT_MASK_BSSID1_0) << BIT_SHIFT_BSSID1_0) -#define BIT_GET_BSSID1_0(x) (((x) >> BIT_SHIFT_BSSID1_0) & BIT_MASK_BSSID1_0) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_BSSID1_1 (Offset 0x070C) */ +/* 2 REG_PCIE_CFG_FORCE_LINK_L (Offset 0x0709) */ +#define BIT_PCIE_CFG_FORCE_EN BIT(7) -#define BIT_SHIFT_BSSID1_1 0 -#define BIT_MASK_BSSID1_1 0xffff -#define BIT_BSSID1_1(x) (((x) & BIT_MASK_BSSID1_1) << BIT_SHIFT_BSSID1_1) -#define BIT_GET_BSSID1_1(x) (((x) >> BIT_SHIFT_BSSID1_1) & BIT_MASK_BSSID1_1) +/* 2 REG_PCIE_CFG_FORCE_LINK_H (Offset 0x070A) */ +#define BIT_PCIE_CFG_TRXACT_DIS_IDLE_TIMER BIT(6) + +#define BIT_SHIFT_PCIE_CFG_LINK_STATE 0 +#define BIT_MASK_PCIE_CFG_LINK_STATE 0x3f +#define BIT_PCIE_CFG_LINK_STATE(x) \ + (((x) & BIT_MASK_PCIE_CFG_LINK_STATE) << BIT_SHIFT_PCIE_CFG_LINK_STATE) +#define BITS_PCIE_CFG_LINK_STATE \ + (BIT_MASK_PCIE_CFG_LINK_STATE << BIT_SHIFT_PCIE_CFG_LINK_STATE) +#define BIT_CLEAR_PCIE_CFG_LINK_STATE(x) ((x) & (~BITS_PCIE_CFG_LINK_STATE)) +#define BIT_GET_PCIE_CFG_LINK_STATE(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_LINK_STATE) & BIT_MASK_PCIE_CFG_LINK_STATE) +#define BIT_SET_PCIE_CFG_LINK_STATE(x, v) \ + (BIT_CLEAR_PCIE_CFG_LINK_STATE(x) | BIT_PCIE_CFG_LINK_STATE(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BSSID1_1 (Offset 0x070C) */ +#define BIT_SHIFT_BSSID1_1 0 +#define BIT_MASK_BSSID1_1 0xffff +#define BIT_BSSID1_1(x) (((x) & BIT_MASK_BSSID1_1) << BIT_SHIFT_BSSID1_1) +#define BITS_BSSID1_1 (BIT_MASK_BSSID1_1 << BIT_SHIFT_BSSID1_1) +#define BIT_CLEAR_BSSID1_1(x) ((x) & (~BITS_BSSID1_1)) +#define BIT_GET_BSSID1_1(x) (((x) >> BIT_SHIFT_BSSID1_1) & BIT_MASK_BSSID1_1) +#define BIT_SET_BSSID1_1(x, v) (BIT_CLEAR_BSSID1_1(x) | BIT_BSSID1_1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY (Offset 0x070C) */ + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0 +#define BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0xff +#define BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY) +#define BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY \ + (BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY)) +#define BIT_GET_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY) & \ + BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY) +#define BIT_SET_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) | \ + BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY(v)) + +/* 2 REG_PCIE_CFG_CX_NFTS (Offset 0x070D) */ + +#define BIT_SHIFT_PCIE_CFG_CX_NFTS 0 +#define BIT_MASK_PCIE_CFG_CX_NFTS 0xff +#define BIT_PCIE_CFG_CX_NFTS(x) \ + (((x) & BIT_MASK_PCIE_CFG_CX_NFTS) << BIT_SHIFT_PCIE_CFG_CX_NFTS) +#define BITS_PCIE_CFG_CX_NFTS \ + (BIT_MASK_PCIE_CFG_CX_NFTS << BIT_SHIFT_PCIE_CFG_CX_NFTS) +#define BIT_CLEAR_PCIE_CFG_CX_NFTS(x) ((x) & (~BITS_PCIE_CFG_CX_NFTS)) +#define BIT_GET_PCIE_CFG_CX_NFTS(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_CX_NFTS) & BIT_MASK_PCIE_CFG_CX_NFTS) +#define BIT_SET_PCIE_CFG_CX_NFTS(x, v) \ + (BIT_CLEAR_PCIE_CFG_CX_NFTS(x) | BIT_PCIE_CFG_CX_NFTS(v)) + +/* 2 REG_PCIE_CFG_DEFAULT_ENTR_LATENCY (Offset 0x070F) */ + +#define BIT_PCIE_CFG_REAL_EN_L0S BIT(7) +#define BIT_PCIE_CFG_ENTER_ASPM BIT(6) + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY 3 +#define BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY 0x7 +#define BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) +#define BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY \ + (BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)) +#define BIT_GET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) & \ + BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) +#define BIT_SET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) | \ + BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(v)) + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY 0 +#define BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY 0x7 +#define BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) +#define BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY \ + (BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)) +#define BIT_GET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) & \ + BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) +#define BIT_SET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) | \ + BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ +#define BIT_TXUSER_ID1 BIT(25) -#define BIT_SHIFT_DTIM_CNT1 24 -#define BIT_MASK_DTIM_CNT1 0xff -#define BIT_DTIM_CNT1(x) (((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1) -#define BIT_GET_DTIM_CNT1(x) (((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1) +#define BIT_SHIFT_DTIM_CNT1 24 +#define BIT_MASK_DTIM_CNT1 0xff +#define BIT_DTIM_CNT1(x) (((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1) +#define BITS_DTIM_CNT1 (BIT_MASK_DTIM_CNT1 << BIT_SHIFT_DTIM_CNT1) +#define BIT_CLEAR_DTIM_CNT1(x) ((x) & (~BITS_DTIM_CNT1)) +#define BIT_GET_DTIM_CNT1(x) (((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1) +#define BIT_SET_DTIM_CNT1(x, v) (BIT_CLEAR_DTIM_CNT1(x) | BIT_DTIM_CNT1(v)) +#define BIT_SHIFT_DTIM_PERIOD1 16 +#define BIT_MASK_DTIM_PERIOD1 0xff +#define BIT_DTIM_PERIOD1(x) \ + (((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1) +#define BITS_DTIM_PERIOD1 (BIT_MASK_DTIM_PERIOD1 << BIT_SHIFT_DTIM_PERIOD1) +#define BIT_CLEAR_DTIM_PERIOD1(x) ((x) & (~BITS_DTIM_PERIOD1)) +#define BIT_GET_DTIM_PERIOD1(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1) +#define BIT_SET_DTIM_PERIOD1(x, v) \ + (BIT_CLEAR_DTIM_PERIOD1(x) | BIT_DTIM_PERIOD1(v)) -#define BIT_SHIFT_DTIM_PERIOD1 16 -#define BIT_MASK_DTIM_PERIOD1 0xff -#define BIT_DTIM_PERIOD1(x) (((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1) -#define BIT_GET_DTIM_PERIOD1(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1) +#define BIT_SHIFT_AID1 16 +#define BIT_MASK_AID1 0x1ff +#define BIT_AID1(x) (((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1) +#define BITS_AID1 (BIT_MASK_AID1 << BIT_SHIFT_AID1) +#define BIT_CLEAR_AID1(x) ((x) & (~BITS_AID1)) +#define BIT_GET_AID1(x) (((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1) +#define BIT_SET_AID1(x, v) (BIT_CLEAR_AID1(x) | BIT_AID1(v)) -#define BIT_DTIM1 BIT(15) -#define BIT_TIM1 BIT(14) +#define BIT_DTIM1 BIT(15) +#define BIT_TIM1 BIT(14) -#define BIT_SHIFT_PS_AID_1 0 -#define BIT_MASK_PS_AID_1 0x7ff -#define BIT_PS_AID_1(x) (((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1) -#define BIT_GET_PS_AID_1(x) (((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1) +#endif +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ +#define BIT_BCN_VALID_V2 BIT(13) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */ +/* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ +#define BIT_TXUSER_ID0 BIT(9) -#define BIT_SHIFT_RD_BF_SEL 29 -#define BIT_MASK_RD_BF_SEL 0x7 -#define BIT_RD_BF_SEL(x) (((x) & BIT_MASK_RD_BF_SEL) << BIT_SHIFT_RD_BF_SEL) -#define BIT_GET_RD_BF_SEL(x) (((x) >> BIT_SHIFT_RD_BF_SEL) & BIT_MASK_RD_BF_SEL) +#define BIT_SHIFT_PS_AID_1 0 +#define BIT_MASK_PS_AID_1 0x7ff +#define BIT_PS_AID_1(x) (((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1) +#define BITS_PS_AID_1 (BIT_MASK_PS_AID_1 << BIT_SHIFT_PS_AID_1) +#define BIT_CLEAR_PS_AID_1(x) ((x) & (~BITS_PS_AID_1)) +#define BIT_GET_PS_AID_1(x) (((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1) +#define BIT_SET_PS_AID_1(x, v) (BIT_CLEAR_PS_AID_1(x) | BIT_PS_AID_1(v)) +#define BIT_SHIFT_AID0 0 +#define BIT_MASK_AID0 0x1ff +#define BIT_AID0(x) (((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0) +#define BITS_AID0 (BIT_MASK_AID0 << BIT_SHIFT_AID0) +#define BIT_CLEAR_AID0(x) ((x) & (~BITS_AID0)) +#define BIT_GET_AID0(x) (((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0) +#define BIT_SET_AID0(x, v) (BIT_CLEAR_AID0(x) | BIT_AID0(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PCIE_CFG_L1_MISC_SEL (Offset 0x0711) */ +#define BIT_PCIE_CFG_L1_RIDLE_SEL BIT(6) +#define BIT_PCIE_CFG_L1_TIMEOUT_SEL BIT(5) +#define BIT_PCIE_CFG_L1_EIDLE_SEL BIT(4) -/* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */ +#define BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE 0 +#define BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE 0xf +#define BIT_PCIE_CFG_DEFAULT_LINK_RATE(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE) +#define BITS_PCIE_CFG_DEFAULT_LINK_RATE \ + (BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_LINK_RATE)) +#define BIT_GET_PCIE_CFG_DEFAULT_LINK_RATE(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE) & \ + BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE) +#define BIT_SET_PCIE_CFG_DEFAULT_LINK_RATE(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE(x) | \ + BIT_PCIE_CFG_DEFAULT_LINK_RATE(v)) + +#endif -#define BIT_TXUSER_ID1 BIT(25) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_AID1 16 -#define BIT_MASK_AID1 0x1ff -#define BIT_AID1(x) (((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1) -#define BIT_GET_AID1(x) (((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1) +/* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */ -#define BIT_TXUSER_ID0 BIT(9) +#define BIT_SHIFT_RD_BF_SEL 29 +#define BIT_MASK_RD_BF_SEL 0x7 +#define BIT_RD_BF_SEL(x) (((x) & BIT_MASK_RD_BF_SEL) << BIT_SHIFT_RD_BF_SEL) +#define BITS_RD_BF_SEL (BIT_MASK_RD_BF_SEL << BIT_SHIFT_RD_BF_SEL) +#define BIT_CLEAR_RD_BF_SEL(x) ((x) & (~BITS_RD_BF_SEL)) +#define BIT_GET_RD_BF_SEL(x) (((x) >> BIT_SHIFT_RD_BF_SEL) & BIT_MASK_RD_BF_SEL) +#define BIT_SET_RD_BF_SEL(x, v) (BIT_CLEAR_RD_BF_SEL(x) | BIT_RD_BF_SEL(v)) -#define BIT_SHIFT_AID0 0 -#define BIT_MASK_AID0 0x1ff -#define BIT_AID0(x) (((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0) -#define BIT_GET_AID0(x) (((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_NDP_RX_STANDBY_TIMER 24 +#define BIT_MASK_NDP_RX_STANDBY_TIMER 0xff +#define BIT_NDP_RX_STANDBY_TIMER(x) \ + (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER) \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER) +#define BITS_NDP_RX_STANDBY_TIMER \ + (BIT_MASK_NDP_RX_STANDBY_TIMER << BIT_SHIFT_NDP_RX_STANDBY_TIMER) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) ((x) & (~BITS_NDP_RX_STANDBY_TIMER)) +#define BIT_GET_NDP_RX_STANDBY_TIMER(x) \ + (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) & \ + BIT_MASK_NDP_RX_STANDBY_TIMER) +#define BIT_SET_NDP_RX_STANDBY_TIMER(x, v) \ + (BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) | BIT_NDP_RX_STANDBY_TIMER(v)) -#define BIT_SHIFT_NDP_RX_STANDBY_TIMER 24 -#define BIT_MASK_NDP_RX_STANDBY_TIMER 0xff -#define BIT_NDP_RX_STANDBY_TIMER(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER) << BIT_SHIFT_NDP_RX_STANDBY_TIMER) -#define BIT_GET_NDP_RX_STANDBY_TIMER(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) & BIT_MASK_NDP_RX_STANDBY_TIMER) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_CSI_RPT_OFFSET_HT 16 -#define BIT_MASK_CSI_RPT_OFFSET_HT 0xff -#define BIT_CSI_RPT_OFFSET_HT(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT) << BIT_SHIFT_CSI_RPT_OFFSET_HT) -#define BIT_GET_CSI_RPT_OFFSET_HT(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT) & BIT_MASK_CSI_RPT_OFFSET_HT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_WMAC_CHK_RPTPOLL_A2_DIS BIT(23) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_R_WMAC_CHK_RPTPOLL_A2_DIS BIT(23) -/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_CSI_RPT_OFFSET_VHT 8 -#define BIT_MASK_CSI_RPT_OFFSET_VHT 0xff -#define BIT_CSI_RPT_OFFSET_VHT(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT) << BIT_SHIFT_CSI_RPT_OFFSET_VHT) -#define BIT_GET_CSI_RPT_OFFSET_VHT(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT) & BIT_MASK_CSI_RPT_OFFSET_VHT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_WMAC_CHK_UCNDPA_A2_DIS BIT(22) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_R_WMAC_CHK_UCNDPA_A2_DIS BIT(22) -/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) -#define BIT_SHIFT_R_WMAC_VHT_CATEGORY 8 -#define BIT_MASK_R_WMAC_VHT_CATEGORY 0xff -#define BIT_R_WMAC_VHT_CATEGORY(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY) << BIT_SHIFT_R_WMAC_VHT_CATEGORY) -#define BIT_GET_R_WMAC_VHT_CATEGORY(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY) & BIT_MASK_R_WMAC_VHT_CATEGORY) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_CSI_RPT_OFFSET_HT 16 +#define BIT_MASK_CSI_RPT_OFFSET_HT 0xff +#define BIT_CSI_RPT_OFFSET_HT(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT) << BIT_SHIFT_CSI_RPT_OFFSET_HT) +#define BITS_CSI_RPT_OFFSET_HT \ + (BIT_MASK_CSI_RPT_OFFSET_HT << BIT_SHIFT_CSI_RPT_OFFSET_HT) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT)) +#define BIT_GET_CSI_RPT_OFFSET_HT(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT) & BIT_MASK_CSI_RPT_OFFSET_HT) +#define BIT_SET_CSI_RPT_OFFSET_HT(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT(x) | BIT_CSI_RPT_OFFSET_HT(v)) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ + +#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1 16 +#define BIT_MASK_CSI_RPT_OFFSET_HT_V1 0x3f +#define BIT_CSI_RPT_OFFSET_HT_V1(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1) \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) +#define BITS_CSI_RPT_OFFSET_HT_V1 \ + (BIT_MASK_CSI_RPT_OFFSET_HT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT_V1)) +#define BIT_GET_CSI_RPT_OFFSET_HT_V1(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) & \ + BIT_MASK_CSI_RPT_OFFSET_HT_V1) +#define BIT_SET_CSI_RPT_OFFSET_HT_V1(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) | BIT_CSI_RPT_OFFSET_HT_V1(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ -#define BIT_R_WMAC_USE_NSTS BIT(7) -#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC BIT(6) -#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC BIT(5) -#define BIT_R_WMAC_BFPARAM_SEL BIT(4) -#define BIT_R_WMAC_CSISEQ_SEL BIT(3) -#define BIT_R_WMAC_CSI_WITHHTC_EN BIT(2) -#define BIT_R_WMAC_HT_NDPA_EN BIT(1) -#define BIT_R_WMAC_VHT_NDPA_EN BIT(0) +#define BIT_WMAC_OFFSET_RPTPOLL_EN BIT(15) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL BIT(15) -/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ +#endif -#define BIT_WRITE_ENABLE BIT(31) -#define BIT_WRITE_USERID BIT(12) +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WRITE_BW 10 -#define BIT_MASK_WRITE_BW 0x3 -#define BIT_WRITE_BW(x) (((x) & BIT_MASK_WRITE_BW) << BIT_SHIFT_WRITE_BW) -#define BIT_GET_WRITE_BW(x) (((x) >> BIT_SHIFT_WRITE_BW) & BIT_MASK_WRITE_BW) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_R_WMAC_OFFSET_RPTPOLL_EN BIT(15) -#define BIT_SHIFT_WRITE_CB 8 -#define BIT_MASK_WRITE_CB 0x3 -#define BIT_WRITE_CB(x) (((x) & BIT_MASK_WRITE_CB) << BIT_SHIFT_WRITE_CB) -#define BIT_GET_WRITE_CB(x) (((x) >> BIT_SHIFT_WRITE_CB) & BIT_MASK_WRITE_CB) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_WRITE_GROUPING 6 -#define BIT_MASK_WRITE_GROUPING 0x3 -#define BIT_WRITE_GROUPING(x) (((x) & BIT_MASK_WRITE_GROUPING) << BIT_SHIFT_WRITE_GROUPING) -#define BIT_GET_WRITE_GROUPING(x) (((x) >> BIT_SHIFT_WRITE_GROUPING) & BIT_MASK_WRITE_GROUPING) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_WMAC_CSI_CHKSUM_DIS BIT(14) -#define BIT_SHIFT_WRITE_NR 3 -#define BIT_MASK_WRITE_NR 0x7 -#define BIT_WRITE_NR(x) (((x) & BIT_MASK_WRITE_NR) << BIT_SHIFT_WRITE_NR) -#define BIT_GET_WRITE_NR(x) (((x) >> BIT_SHIFT_WRITE_NR) & BIT_MASK_WRITE_NR) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WRITE_NC 0 -#define BIT_MASK_WRITE_NC 0x7 -#define BIT_WRITE_NC(x) (((x) & BIT_MASK_WRITE_NC) << BIT_SHIFT_WRITE_NC) -#define BIT_GET_WRITE_NC(x) (((x) >> BIT_SHIFT_WRITE_NC) & BIT_MASK_WRITE_NC) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_R_WMAC_CSI_CHKSUM_DIS BIT(14) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_NDPVLD_POS_RST_FFPTR_DIS BIT(14) -/* 2 REG_NS_ARP_CTRL (Offset 0x0720) */ +#endif -#define BIT_R_WMAC_NSARP_RSPEN BIT(15) -#define BIT_R_WMAC_NSARP_RARP BIT(9) -#define BIT_R_WMAC_NSARP_RIPV6 BIT(8) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_R_WMAC_NSARP_MODEN 6 -#define BIT_MASK_R_WMAC_NSARP_MODEN 0x3 -#define BIT_R_WMAC_NSARP_MODEN(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN) << BIT_SHIFT_R_WMAC_NSARP_MODEN) -#define BIT_GET_R_WMAC_NSARP_MODEN(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN) & BIT_MASK_R_WMAC_NSARP_MODEN) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_CSI_RPT_OFFSET_VHT 8 +#define BIT_MASK_CSI_RPT_OFFSET_VHT 0xff +#define BIT_CSI_RPT_OFFSET_VHT(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT) << BIT_SHIFT_CSI_RPT_OFFSET_VHT) +#define BITS_CSI_RPT_OFFSET_VHT \ + (BIT_MASK_CSI_RPT_OFFSET_VHT << BIT_SHIFT_CSI_RPT_OFFSET_VHT) +#define BIT_CLEAR_CSI_RPT_OFFSET_VHT(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT)) +#define BIT_GET_CSI_RPT_OFFSET_VHT(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT) & BIT_MASK_CSI_RPT_OFFSET_VHT) +#define BIT_SET_CSI_RPT_OFFSET_VHT(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_VHT(x) | BIT_CSI_RPT_OFFSET_VHT(v)) -#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP 4 -#define BIT_MASK_R_WMAC_NSARP_RSPFTP 0x3 -#define BIT_R_WMAC_NSARP_RSPFTP(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP) -#define BIT_GET_R_WMAC_NSARP_RSPFTP(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP) & BIT_MASK_R_WMAC_NSARP_RSPFTP) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC 0 -#define BIT_MASK_R_WMAC_NSARP_RSPSEC 0xf -#define BIT_R_WMAC_NSARP_RSPSEC(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC) -#define BIT_GET_R_WMAC_NSARP_RSPSEC(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC) & BIT_MASK_R_WMAC_NSARP_RSPSEC) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1 8 +#define BIT_MASK_CSI_RPT_OFFSET_VHT_V1 0x3f +#define BIT_CSI_RPT_OFFSET_VHT_V1(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_V1) \ + << BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1) +#define BITS_CSI_RPT_OFFSET_VHT_V1 \ + (BIT_MASK_CSI_RPT_OFFSET_VHT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1) +#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_V1(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT_V1)) +#define BIT_GET_CSI_RPT_OFFSET_VHT_V1(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1) & \ + BIT_MASK_CSI_RPT_OFFSET_VHT_V1) +#define BIT_SET_CSI_RPT_OFFSET_VHT_V1(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_VHT_V1(x) | BIT_CSI_RPT_OFFSET_VHT_V1(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_R_WMAC_VHT_CATEGORY 8 +#define BIT_MASK_R_WMAC_VHT_CATEGORY 0xff +#define BIT_R_WMAC_VHT_CATEGORY(x) \ + (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY) << BIT_SHIFT_R_WMAC_VHT_CATEGORY) +#define BITS_R_WMAC_VHT_CATEGORY \ + (BIT_MASK_R_WMAC_VHT_CATEGORY << BIT_SHIFT_R_WMAC_VHT_CATEGORY) +#define BIT_CLEAR_R_WMAC_VHT_CATEGORY(x) ((x) & (~BITS_R_WMAC_VHT_CATEGORY)) +#define BIT_GET_R_WMAC_VHT_CATEGORY(x) \ + (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY) & BIT_MASK_R_WMAC_VHT_CATEGORY) +#define BIT_SET_R_WMAC_VHT_CATEGORY(x, v) \ + (BIT_CLEAR_R_WMAC_VHT_CATEGORY(x) | BIT_R_WMAC_VHT_CATEGORY(v)) -/* 2 REG_NS_ARP_INFO (Offset 0x0724) */ +#endif -#define BIT_REQ_IS_MCNS BIT(23) -#define BIT_REQ_IS_UCNS BIT(22) -#define BIT_REQ_IS_USNS BIT(21) -#define BIT_REQ_IS_ARP BIT(20) -#define BIT_EXPRSP_MH_WITHQC BIT(19) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_EXPRSP_SECTYPE 16 -#define BIT_MASK_EXPRSP_SECTYPE 0x7 -#define BIT_EXPRSP_SECTYPE(x) (((x) & BIT_MASK_EXPRSP_SECTYPE) << BIT_SHIFT_EXPRSP_SECTYPE) -#define BIT_GET_EXPRSP_SECTYPE(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE) & BIT_MASK_EXPRSP_SECTYPE) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1 8 +#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1 0x3f +#define BIT_R_CSI_RPT_OFFSET_VHT_V1(x) \ + (((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1) \ + << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1) +#define BITS_R_CSI_RPT_OFFSET_VHT_V1 \ + (BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1 << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1) +#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1(x) \ + ((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1)) +#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1(x) \ + (((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1) & \ + BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1) +#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1(x, v) \ + (BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1(x) | BIT_R_CSI_RPT_OFFSET_VHT_V1(v)) -#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0 8 -#define BIT_MASK_EXPRSP_CHKSM_7_TO_0 0xff -#define BIT_EXPRSP_CHKSM_7_TO_0(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) -#define BIT_GET_EXPRSP_CHKSM_7_TO_0(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8 0 -#define BIT_MASK_EXPRSP_CHKSM_15_TO_8 0xff -#define BIT_EXPRSP_CHKSM_15_TO_8(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) -#define BIT_GET_EXPRSP_CHKSM_15_TO_8(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) & BIT_MASK_EXPRSP_CHKSM_15_TO_8) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1 8 +#define BIT_MASK_R_WMAC_VHT_CATEGORY_V1 0x3f +#define BIT_R_WMAC_VHT_CATEGORY_V1(x) \ + (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1) \ + << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) +#define BITS_R_WMAC_VHT_CATEGORY_V1 \ + (BIT_MASK_R_WMAC_VHT_CATEGORY_V1 << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) +#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x) \ + ((x) & (~BITS_R_WMAC_VHT_CATEGORY_V1)) +#define BIT_GET_R_WMAC_VHT_CATEGORY_V1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) & \ + BIT_MASK_R_WMAC_VHT_CATEGORY_V1) +#define BIT_SET_R_WMAC_VHT_CATEGORY_V1(x, v) \ + (BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x) | BIT_R_WMAC_VHT_CATEGORY_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_R_WMAC_USE_NSTS BIT(7) +#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC BIT(6) -/* 2 REG_BEAMFORMING_INFO_NSARP_V1 (Offset 0x0728) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_WMAC_ARPIP 0 -#define BIT_MASK_WMAC_ARPIP 0xffffffffL -#define BIT_WMAC_ARPIP(x) (((x) & BIT_MASK_WMAC_ARPIP) << BIT_SHIFT_WMAC_ARPIP) -#define BIT_GET_WMAC_ARPIP(x) (((x) >> BIT_SHIFT_WMAC_ARPIP) & BIT_MASK_WMAC_ARPIP) +/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */ +#define BIT_PCIE_CFG_REAL_PTM_ENABLE BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC BIT(5) -/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BEAMFORMING_INFO 0 -#define BIT_MASK_BEAMFORMING_INFO 0xffffffffL -#define BIT_BEAMFORMING_INFO(x) (((x) & BIT_MASK_BEAMFORMING_INFO) << BIT_SHIFT_BEAMFORMING_INFO) -#define BIT_GET_BEAMFORMING_INFO(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO) +/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */ +#define BIT_PCIE_CFG_REAL_EN_L1SUB BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_R_WMAC_BFPARAM_SEL BIT(4) +#define BIT_R_WMAC_CSISEQ_SEL BIT(3) +#define BIT_R_WMAC_CSI_WITHHTC_EN BIT(2) +#define BIT_R_WMAC_HT_NDPA_EN BIT(1) +#define BIT_R_WMAC_VHT_NDPA_EN BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */ + +#define BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM 0 +#define BIT_MASK_PCIE_CFG_MAX_FUNC_NUM 0x7 +#define BIT_PCIE_CFG_MAX_FUNC_NUM(x) \ + (((x) & BIT_MASK_PCIE_CFG_MAX_FUNC_NUM) \ + << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM) +#define BITS_PCIE_CFG_MAX_FUNC_NUM \ + (BIT_MASK_PCIE_CFG_MAX_FUNC_NUM << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM) +#define BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM(x) ((x) & (~BITS_PCIE_CFG_MAX_FUNC_NUM)) +#define BIT_GET_PCIE_CFG_MAX_FUNC_NUM(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM) & \ + BIT_MASK_PCIE_CFG_MAX_FUNC_NUM) +#define BIT_SET_PCIE_CFG_MAX_FUNC_NUM(x, v) \ + (BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM(x) | BIT_PCIE_CFG_MAX_FUNC_NUM(v)) + +/* 2 REG_PCIE_CFG_FORCE_CLKREQ_N_PAD (Offset 0x0719) */ + +#define BIT_PCIE_CFG_REAL_EN_64BITS BIT(5) +#define BIT_PCIE_CFG_REAL_EN_CLKREQ BIT(4) +#define BIT_PCIE_CFG_REAL_EN_L1 BIT(3) +#define BIT_PCIE_CFG_WAKE_N_EN BIT(2) +#define BIT_PCIE_CFG_BYPASS_LTR_OPTION BIT(1) +#define BIT_PCIE_CFG_FORCE_CLKREQ_N_PAD BIT(0) + +/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY (Offset 0x071A) */ + +#define BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK 0 +#define BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK 0xff +#define BIT_PCIE_CFG_TIMER_MOD_ACK_NAK(x) \ + (((x) & BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK) \ + << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK) +#define BITS_PCIE_CFG_TIMER_MOD_ACK_NAK \ + (BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK \ + << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK) +#define BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK(x) \ + ((x) & (~BITS_PCIE_CFG_TIMER_MOD_ACK_NAK)) +#define BIT_GET_PCIE_CFG_TIMER_MOD_ACK_NAK(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK) & \ + BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK) +#define BIT_SET_PCIE_CFG_TIMER_MOD_ACK_NAK(x, v) \ + (BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK(x) | \ + BIT_PCIE_CFG_TIMER_MOD_ACK_NAK(v)) + +/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG (Offset 0x071B) */ + +#define BIT_PCIE_CFG_BYPASS_L1_SUBSTATE_OPTION BIT(7) + +#define BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR 5 +#define BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR 0x3 +#define BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) \ + (((x) & BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR) \ + << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR) +#define BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR \ + (BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR \ + << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR) +#define BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) \ + ((x) & (~BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR)) +#define BIT_GET_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR) & \ + BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR) +#define BIT_SET_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x, v) \ + (BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) | \ + BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR(v)) + +#define BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER 0 +#define BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER 0x1f +#define BIT_PCIE_CFG_UPDATE_FREQ_TIMER(x) \ + (((x) & BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER) \ + << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER) +#define BITS_PCIE_CFG_UPDATE_FREQ_TIMER \ + (BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER \ + << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER) +#define BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER(x) \ + ((x) & (~BITS_PCIE_CFG_UPDATE_FREQ_TIMER)) +#define BIT_GET_PCIE_CFG_UPDATE_FREQ_TIMER(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER) & \ + BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER) +#define BIT_SET_PCIE_CFG_UPDATE_FREQ_TIMER(x, v) \ + (BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER(x) | \ + BIT_PCIE_CFG_UPDATE_FREQ_TIMER(v)) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_IPV6 (Offset 0x0730) */ +/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ +#define BIT_WRITE_ENABLE BIT(31) -#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0 0 -#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_0(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_0(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_IPV6_1 (Offset 0x0734) */ +/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ +#define BIT_WMAC_CHECK_SOUNDING_SEQ BIT(30) +#define BIT_ANTTRN_SWITCH BIT(19) -#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1 0 -#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_1(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_1(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_IPV6_2 (Offset 0x0738) */ +/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ +#define BIT_WRITE_USERID BIT(12) + +#define BIT_SHIFT_WRITE_BW 10 +#define BIT_MASK_WRITE_BW 0x3 +#define BIT_WRITE_BW(x) (((x) & BIT_MASK_WRITE_BW) << BIT_SHIFT_WRITE_BW) +#define BITS_WRITE_BW (BIT_MASK_WRITE_BW << BIT_SHIFT_WRITE_BW) +#define BIT_CLEAR_WRITE_BW(x) ((x) & (~BITS_WRITE_BW)) +#define BIT_GET_WRITE_BW(x) (((x) >> BIT_SHIFT_WRITE_BW) & BIT_MASK_WRITE_BW) +#define BIT_SET_WRITE_BW(x, v) (BIT_CLEAR_WRITE_BW(x) | BIT_WRITE_BW(v)) + +#define BIT_SHIFT_WRITE_CB 8 +#define BIT_MASK_WRITE_CB 0x3 +#define BIT_WRITE_CB(x) (((x) & BIT_MASK_WRITE_CB) << BIT_SHIFT_WRITE_CB) +#define BITS_WRITE_CB (BIT_MASK_WRITE_CB << BIT_SHIFT_WRITE_CB) +#define BIT_CLEAR_WRITE_CB(x) ((x) & (~BITS_WRITE_CB)) +#define BIT_GET_WRITE_CB(x) (((x) >> BIT_SHIFT_WRITE_CB) & BIT_MASK_WRITE_CB) +#define BIT_SET_WRITE_CB(x, v) (BIT_CLEAR_WRITE_CB(x) | BIT_WRITE_CB(v)) + +#define BIT_SHIFT_WRITE_GROUPING 6 +#define BIT_MASK_WRITE_GROUPING 0x3 +#define BIT_WRITE_GROUPING(x) \ + (((x) & BIT_MASK_WRITE_GROUPING) << BIT_SHIFT_WRITE_GROUPING) +#define BITS_WRITE_GROUPING \ + (BIT_MASK_WRITE_GROUPING << BIT_SHIFT_WRITE_GROUPING) +#define BIT_CLEAR_WRITE_GROUPING(x) ((x) & (~BITS_WRITE_GROUPING)) +#define BIT_GET_WRITE_GROUPING(x) \ + (((x) >> BIT_SHIFT_WRITE_GROUPING) & BIT_MASK_WRITE_GROUPING) +#define BIT_SET_WRITE_GROUPING(x, v) \ + (BIT_CLEAR_WRITE_GROUPING(x) | BIT_WRITE_GROUPING(v)) + +#define BIT_SHIFT_WRITE_NR 3 +#define BIT_MASK_WRITE_NR 0x7 +#define BIT_WRITE_NR(x) (((x) & BIT_MASK_WRITE_NR) << BIT_SHIFT_WRITE_NR) +#define BITS_WRITE_NR (BIT_MASK_WRITE_NR << BIT_SHIFT_WRITE_NR) +#define BIT_CLEAR_WRITE_NR(x) ((x) & (~BITS_WRITE_NR)) +#define BIT_GET_WRITE_NR(x) (((x) >> BIT_SHIFT_WRITE_NR) & BIT_MASK_WRITE_NR) +#define BIT_SET_WRITE_NR(x, v) (BIT_CLEAR_WRITE_NR(x) | BIT_WRITE_NR(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2 0 -#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_2(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_2(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2) +/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ +#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD 1 +#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD 0xffffff +#define BIT_VHTHT_MIMO_CTRL_FIELD(x) \ + (((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD) \ + << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) +#define BITS_VHTHT_MIMO_CTRL_FIELD \ + (BIT_MASK_VHTHT_MIMO_CTRL_FIELD << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) +#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) ((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD)) +#define BIT_GET_VHTHT_MIMO_CTRL_FIELD(x) \ + (((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) & \ + BIT_MASK_VHTHT_MIMO_CTRL_FIELD) +#define BIT_SET_VHTHT_MIMO_CTRL_FIELD(x, v) \ + (BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) | BIT_VHTHT_MIMO_CTRL_FIELD(v)) -/* 2 REG_IPV6_3 (Offset 0x073C) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3 0 -#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_3(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_3(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3) +/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ +#define BIT_SHIFT_WRITE_NC 0 +#define BIT_MASK_WRITE_NC 0x7 +#define BIT_WRITE_NC(x) (((x) & BIT_MASK_WRITE_NC) << BIT_SHIFT_WRITE_NC) +#define BITS_WRITE_NC (BIT_MASK_WRITE_NC << BIT_SHIFT_WRITE_NC) +#define BIT_CLEAR_WRITE_NC(x) ((x) & (~BITS_WRITE_NC)) +#define BIT_GET_WRITE_NC(x) (((x) >> BIT_SHIFT_WRITE_NC) & BIT_MASK_WRITE_NC) +#define BIT_SET_WRITE_NC(x, v) (BIT_CLEAR_WRITE_NC(x) | BIT_WRITE_NC(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ +#define BIT_CSI_INTERRUPT_STATUS BIT(0) -/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG (Offset 0x0750) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE 4 -#define BIT_MASK_R_WMAC_CTX_SUBTYPE 0xf -#define BIT_R_WMAC_CTX_SUBTYPE(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE) -#define BIT_GET_R_WMAC_CTX_SUBTYPE(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE) +/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_L (Offset 0x071C) */ +#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L 0 +#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L 0xff +#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) \ + (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L) \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L) +#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L \ + (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L) +#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) \ + ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L)) +#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L) & \ + BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L) +#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_L(x, v) \ + (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) | \ + BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L(v)) -#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE 0 -#define BIT_MASK_R_WMAC_RTX_SUBTYPE 0xf -#define BIT_R_WMAC_RTX_SUBTYPE(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE) -#define BIT_GET_R_WMAC_RTX_SUBTYPE(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE) +/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_H (Offset 0x071D) */ +#define BIT_PCIE_CFG_DISABLE_FC_WATCHDOG_TIMER BIT(7) -/* 2 REG_BT_COEX_V2 (Offset 0x0762) */ +#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H 0 +#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H 0x7 +#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) \ + (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H) \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H) +#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H \ + (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H) +#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) \ + ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H)) +#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H) & \ + BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H) +#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_H(x, v) \ + (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) | \ + BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H(v)) -#define BIT_GNT_BT_POLARITY BIT(12) -#define BIT_GNT_BT_BYPASS_PRIORITY BIT(8) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TIMER 0 -#define BIT_MASK_TIMER 0xff -#define BIT_TIMER(x) (((x) & BIT_MASK_TIMER) << BIT_SHIFT_TIMER) -#define BIT_GET_TIMER(x) (((x) >> BIT_SHIFT_TIMER) & BIT_MASK_TIMER) +/* 2 REG_NS_ARP_CTRL (Offset 0x0720) */ +#define BIT_R_WMAC_NSARP_RSPEN BIT(15) +#define BIT_R_WMAC_NSARP_RARP BIT(9) +#define BIT_R_WMAC_NSARP_RIPV6 BIT(8) + +#define BIT_SHIFT_R_WMAC_NSARP_MODEN 6 +#define BIT_MASK_R_WMAC_NSARP_MODEN 0x3 +#define BIT_R_WMAC_NSARP_MODEN(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_MODEN) << BIT_SHIFT_R_WMAC_NSARP_MODEN) +#define BITS_R_WMAC_NSARP_MODEN \ + (BIT_MASK_R_WMAC_NSARP_MODEN << BIT_SHIFT_R_WMAC_NSARP_MODEN) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN(x) ((x) & (~BITS_R_WMAC_NSARP_MODEN)) +#define BIT_GET_R_WMAC_NSARP_MODEN(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN) & BIT_MASK_R_WMAC_NSARP_MODEN) +#define BIT_SET_R_WMAC_NSARP_MODEN(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_MODEN(x) | BIT_R_WMAC_NSARP_MODEN(v)) + +#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP 4 +#define BIT_MASK_R_WMAC_NSARP_RSPFTP 0x3 +#define BIT_R_WMAC_NSARP_RSPFTP(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP) +#define BITS_R_WMAC_NSARP_RSPFTP \ + (BIT_MASK_R_WMAC_NSARP_RSPFTP << BIT_SHIFT_R_WMAC_NSARP_RSPFTP) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP(x) ((x) & (~BITS_R_WMAC_NSARP_RSPFTP)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP) & BIT_MASK_R_WMAC_NSARP_RSPFTP) +#define BIT_SET_R_WMAC_NSARP_RSPFTP(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPFTP(x) | BIT_R_WMAC_NSARP_RSPFTP(v)) + +#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC 0 +#define BIT_MASK_R_WMAC_NSARP_RSPSEC 0xf +#define BIT_R_WMAC_NSARP_RSPSEC(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC) +#define BITS_R_WMAC_NSARP_RSPSEC \ + (BIT_MASK_R_WMAC_NSARP_RSPSEC << BIT_SHIFT_R_WMAC_NSARP_RSPSEC) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC(x) ((x) & (~BITS_R_WMAC_NSARP_RSPSEC)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC) & BIT_MASK_R_WMAC_NSARP_RSPSEC) +#define BIT_SET_R_WMAC_NSARP_RSPSEC(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPSEC(x) | BIT_R_WMAC_NSARP_RSPSEC(v)) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BT_COEX (Offset 0x0764) */ +/* 2 REG_NS_ARP_INFO (Offset 0x0724) */ -#define BIT_R_GNT_BT_RFC_SW BIT(12) -#define BIT_R_GNT_BT_RFC_SW_EN BIT(11) -#define BIT_R_GNT_BT_BB_SW BIT(10) -#define BIT_R_GNT_BT_BB_SW_EN BIT(9) -#define BIT_R_BT_CNT_THREN BIT(8) +#define BIT_REQ_IS_MCNS BIT(23) +#define BIT_REQ_IS_UCNS BIT(22) +#define BIT_REQ_IS_USNS BIT(21) +#define BIT_REQ_IS_ARP BIT(20) +#define BIT_EXPRSP_MH_WITHQC BIT(19) + +#define BIT_SHIFT_EXPRSP_SECTYPE 16 +#define BIT_MASK_EXPRSP_SECTYPE 0x7 +#define BIT_EXPRSP_SECTYPE(x) \ + (((x) & BIT_MASK_EXPRSP_SECTYPE) << BIT_SHIFT_EXPRSP_SECTYPE) +#define BITS_EXPRSP_SECTYPE \ + (BIT_MASK_EXPRSP_SECTYPE << BIT_SHIFT_EXPRSP_SECTYPE) +#define BIT_CLEAR_EXPRSP_SECTYPE(x) ((x) & (~BITS_EXPRSP_SECTYPE)) +#define BIT_GET_EXPRSP_SECTYPE(x) \ + (((x) >> BIT_SHIFT_EXPRSP_SECTYPE) & BIT_MASK_EXPRSP_SECTYPE) +#define BIT_SET_EXPRSP_SECTYPE(x, v) \ + (BIT_CLEAR_EXPRSP_SECTYPE(x) | BIT_EXPRSP_SECTYPE(v)) + +#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0 8 +#define BIT_MASK_EXPRSP_CHKSM_7_TO_0 0xff +#define BIT_EXPRSP_CHKSM_7_TO_0(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) +#define BITS_EXPRSP_CHKSM_7_TO_0 \ + (BIT_MASK_EXPRSP_CHKSM_7_TO_0 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) +#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0(x) ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0)) +#define BIT_GET_EXPRSP_CHKSM_7_TO_0(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) +#define BIT_SET_EXPRSP_CHKSM_7_TO_0(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0(x) | BIT_EXPRSP_CHKSM_7_TO_0(v)) + +#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8 0 +#define BIT_MASK_EXPRSP_CHKSM_15_TO_8 0xff +#define BIT_EXPRSP_CHKSM_15_TO_8(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8) \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) +#define BITS_EXPRSP_CHKSM_15_TO_8 \ + (BIT_MASK_EXPRSP_CHKSM_15_TO_8 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) +#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8(x) ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8)) +#define BIT_GET_EXPRSP_CHKSM_15_TO_8(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) & \ + BIT_MASK_EXPRSP_CHKSM_15_TO_8) +#define BIT_SET_EXPRSP_CHKSM_15_TO_8(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8(x) | BIT_EXPRSP_CHKSM_15_TO_8(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_PCIE_CFG_L1_UNIT_SEL (Offset 0x0724) */ + +#define BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL 0 +#define BIT_MASK_PCIE_CFG_L1_UNIT_SEL 0xff +#define BIT_PCIE_CFG_L1_UNIT_SEL(x) \ + (((x) & BIT_MASK_PCIE_CFG_L1_UNIT_SEL) \ + << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL) +#define BITS_PCIE_CFG_L1_UNIT_SEL \ + (BIT_MASK_PCIE_CFG_L1_UNIT_SEL << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL) +#define BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL(x) ((x) & (~BITS_PCIE_CFG_L1_UNIT_SEL)) +#define BIT_GET_PCIE_CFG_L1_UNIT_SEL(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL) & \ + BIT_MASK_PCIE_CFG_L1_UNIT_SEL) +#define BIT_SET_PCIE_CFG_L1_UNIT_SEL(x, v) \ + (BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL(x) | BIT_PCIE_CFG_L1_UNIT_SEL(v)) + +/* 2 REG_PCIE_CFG_MIN_CLKREQ_SEL (Offset 0x0725) */ + +#define BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL 0 +#define BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL 0xf +#define BIT_PCIE_CFG_MIN_CLKREQ_SEL(x) \ + (((x) & BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL) \ + << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL) +#define BITS_PCIE_CFG_MIN_CLKREQ_SEL \ + (BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL) +#define BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL(x) \ + ((x) & (~BITS_PCIE_CFG_MIN_CLKREQ_SEL)) +#define BIT_GET_PCIE_CFG_MIN_CLKREQ_SEL(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL) & \ + BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL) +#define BIT_SET_PCIE_CFG_MIN_CLKREQ_SEL(x, v) \ + (BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL(x) | BIT_PCIE_CFG_MIN_CLKREQ_SEL(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_BT_CNT_THR 0 -#define BIT_MASK_R_BT_CNT_THR 0xff -#define BIT_R_BT_CNT_THR(x) (((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR) -#define BIT_GET_R_BT_CNT_THR(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR) +/* 2 REG_BEAMFORMING_INFO_NSARP_V1 (Offset 0x0728) */ +#define BIT_SHIFT_WMAC_ARPIP 0 +#define BIT_MASK_WMAC_ARPIP 0xffffffffL +#define BIT_WMAC_ARPIP(x) (((x) & BIT_MASK_WMAC_ARPIP) << BIT_SHIFT_WMAC_ARPIP) +#define BITS_WMAC_ARPIP (BIT_MASK_WMAC_ARPIP << BIT_SHIFT_WMAC_ARPIP) +#define BIT_CLEAR_WMAC_ARPIP(x) ((x) & (~BITS_WMAC_ARPIP)) +#define BIT_GET_WMAC_ARPIP(x) \ + (((x) >> BIT_SHIFT_WMAC_ARPIP) & BIT_MASK_WMAC_ARPIP) +#define BIT_SET_WMAC_ARPIP(x, v) (BIT_CLEAR_WMAC_ARPIP(x) | BIT_WMAC_ARPIP(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ +#define BIT_SHIFT_UPD_BFMEE_USERID 13 +#define BIT_MASK_UPD_BFMEE_USERID 0x7 +#define BIT_UPD_BFMEE_USERID(x) \ + (((x) & BIT_MASK_UPD_BFMEE_USERID) << BIT_SHIFT_UPD_BFMEE_USERID) +#define BITS_UPD_BFMEE_USERID \ + (BIT_MASK_UPD_BFMEE_USERID << BIT_SHIFT_UPD_BFMEE_USERID) +#define BIT_CLEAR_UPD_BFMEE_USERID(x) ((x) & (~BITS_UPD_BFMEE_USERID)) +#define BIT_GET_UPD_BFMEE_USERID(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_USERID) & BIT_MASK_UPD_BFMEE_USERID) +#define BIT_SET_UPD_BFMEE_USERID(x, v) \ + (BIT_CLEAR_UPD_BFMEE_USERID(x) | BIT_UPD_BFMEE_USERID(v)) + +#define BIT_UPD_BFMEE_FBTP BIT(12) + +#define BIT_SHIFT_UPD_BFMEE_CB 8 +#define BIT_MASK_UPD_BFMEE_CB 0x3 +#define BIT_UPD_BFMEE_CB(x) \ + (((x) & BIT_MASK_UPD_BFMEE_CB) << BIT_SHIFT_UPD_BFMEE_CB) +#define BITS_UPD_BFMEE_CB (BIT_MASK_UPD_BFMEE_CB << BIT_SHIFT_UPD_BFMEE_CB) +#define BIT_CLEAR_UPD_BFMEE_CB(x) ((x) & (~BITS_UPD_BFMEE_CB)) +#define BIT_GET_UPD_BFMEE_CB(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_CB) & BIT_MASK_UPD_BFMEE_CB) +#define BIT_SET_UPD_BFMEE_CB(x, v) \ + (BIT_CLEAR_UPD_BFMEE_CB(x) | BIT_UPD_BFMEE_CB(v)) + +#define BIT_SHIFT_UPD_BFMEE_NG 6 +#define BIT_MASK_UPD_BFMEE_NG 0x3 +#define BIT_UPD_BFMEE_NG(x) \ + (((x) & BIT_MASK_UPD_BFMEE_NG) << BIT_SHIFT_UPD_BFMEE_NG) +#define BITS_UPD_BFMEE_NG (BIT_MASK_UPD_BFMEE_NG << BIT_SHIFT_UPD_BFMEE_NG) +#define BIT_CLEAR_UPD_BFMEE_NG(x) ((x) & (~BITS_UPD_BFMEE_NG)) +#define BIT_GET_UPD_BFMEE_NG(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_NG) & BIT_MASK_UPD_BFMEE_NG) +#define BIT_SET_UPD_BFMEE_NG(x, v) \ + (BIT_CLEAR_UPD_BFMEE_NG(x) | BIT_UPD_BFMEE_NG(v)) + +#define BIT_SHIFT_UPD_BFMEE_NR 3 +#define BIT_MASK_UPD_BFMEE_NR 0x7 +#define BIT_UPD_BFMEE_NR(x) \ + (((x) & BIT_MASK_UPD_BFMEE_NR) << BIT_SHIFT_UPD_BFMEE_NR) +#define BITS_UPD_BFMEE_NR (BIT_MASK_UPD_BFMEE_NR << BIT_SHIFT_UPD_BFMEE_NR) +#define BIT_CLEAR_UPD_BFMEE_NR(x) ((x) & (~BITS_UPD_BFMEE_NR)) +#define BIT_GET_UPD_BFMEE_NR(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_NR) & BIT_MASK_UPD_BFMEE_NR) +#define BIT_SET_UPD_BFMEE_NR(x, v) \ + (BIT_CLEAR_UPD_BFMEE_NR(x) | BIT_UPD_BFMEE_NR(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ +/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ -#define BIT_WLRX_TER_BY_CTL BIT(43) -#define BIT_WLRX_TER_BY_AD BIT(42) -#define BIT_ANT_DIVERSITY_SEL BIT(41) -#define BIT_ANTSEL_FOR_BT_CTRL_EN BIT(40) -#define BIT_WLACT_LOW_GNTWL_EN BIT(34) -#define BIT_WLACT_HIGH_GNTBT_EN BIT(33) +#define BIT_SHIFT_BEAMFORMING_INFO 0 +#define BIT_MASK_BEAMFORMING_INFO 0xffffffffL +#define BIT_BEAMFORMING_INFO(x) \ + (((x) & BIT_MASK_BEAMFORMING_INFO) << BIT_SHIFT_BEAMFORMING_INFO) +#define BITS_BEAMFORMING_INFO \ + (BIT_MASK_BEAMFORMING_INFO << BIT_SHIFT_BEAMFORMING_INFO) +#define BIT_CLEAR_BEAMFORMING_INFO(x) ((x) & (~BITS_BEAMFORMING_INFO)) +#define BIT_GET_BEAMFORMING_INFO(x) \ + (((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO) +#define BIT_SET_BEAMFORMING_INFO(x, v) \ + (BIT_CLEAR_BEAMFORMING_INFO(x) | BIT_BEAMFORMING_INFO(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) - +/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ -/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ +#define BIT_SHIFT_UPD_BFMEE_BW 0 +#define BIT_MASK_UPD_BFMEE_BW 0xfff +#define BIT_UPD_BFMEE_BW(x) \ + (((x) & BIT_MASK_UPD_BFMEE_BW) << BIT_SHIFT_UPD_BFMEE_BW) +#define BITS_UPD_BFMEE_BW (BIT_MASK_UPD_BFMEE_BW << BIT_SHIFT_UPD_BFMEE_BW) +#define BIT_CLEAR_UPD_BFMEE_BW(x) ((x) & (~BITS_UPD_BFMEE_BW)) +#define BIT_GET_UPD_BFMEE_BW(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_BW) & BIT_MASK_UPD_BFMEE_BW) +#define BIT_SET_UPD_BFMEE_BW(x, v) \ + (BIT_CLEAR_UPD_BFMEE_BW(x) | BIT_UPD_BFMEE_BW(v)) -#define BIT_NAV_UPPER_V1 BIT(32) +#define BIT_SHIFT_UPD_BFMEE_NC 0 +#define BIT_MASK_UPD_BFMEE_NC 0x7 +#define BIT_UPD_BFMEE_NC(x) \ + (((x) & BIT_MASK_UPD_BFMEE_NC) << BIT_SHIFT_UPD_BFMEE_NC) +#define BITS_UPD_BFMEE_NC (BIT_MASK_UPD_BFMEE_NC << BIT_SHIFT_UPD_BFMEE_NC) +#define BIT_CLEAR_UPD_BFMEE_NC(x) ((x) & (~BITS_UPD_BFMEE_NC)) +#define BIT_GET_UPD_BFMEE_NC(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_NC) & BIT_MASK_UPD_BFMEE_NC) +#define BIT_SET_UPD_BFMEE_NC(x, v) \ + (BIT_CLEAR_UPD_BFMEE_NC(x) | BIT_UPD_BFMEE_NC(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_IPV6 (Offset 0x0730) */ +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_0(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) +#define BITS_R_WMAC_IPV6_MYIPAD_0 \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_0 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_0(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_0) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_0(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0(x) | BIT_R_WMAC_IPV6_MYIPAD_0(v)) -/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ +/* 2 REG_IPV6_1 (Offset 0x0734) */ +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_1(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) +#define BITS_R_WMAC_IPV6_MYIPAD_1 \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_1 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_1) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_1(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1(x) | BIT_R_WMAC_IPV6_MYIPAD_1(v)) -#define BIT_SHIFT_RXMYRTS_NAV_V1 8 -#define BIT_MASK_RXMYRTS_NAV_V1 0xff -#define BIT_RXMYRTS_NAV_V1(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1) << BIT_SHIFT_RXMYRTS_NAV_V1) -#define BIT_GET_RXMYRTS_NAV_V1(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1) & BIT_MASK_RXMYRTS_NAV_V1) +/* 2 REG_IPV6_2 (Offset 0x0738) */ +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_2(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) +#define BITS_R_WMAC_IPV6_MYIPAD_2 \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_2 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_2(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_2) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_2(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2(x) | BIT_R_WMAC_IPV6_MYIPAD_2(v)) -#define BIT_SHIFT_RTSRST_V1 0 -#define BIT_MASK_RTSRST_V1 0xff -#define BIT_RTSRST_V1(x) (((x) & BIT_MASK_RTSRST_V1) << BIT_SHIFT_RTSRST_V1) -#define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1) +/* 2 REG_IPV6_3 (Offset 0x073C) */ +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_3(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) +#define BITS_R_WMAC_IPV6_MYIPAD_3 \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_3 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_3(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_3) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_3(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3(x) | BIT_R_WMAC_IPV6_MYIPAD_3(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG (Offset 0x0750) */ +#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE 4 +#define BIT_MASK_R_WMAC_CTX_SUBTYPE 0xf +#define BIT_R_WMAC_CTX_SUBTYPE(x) \ + (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE) +#define BITS_R_WMAC_CTX_SUBTYPE \ + (BIT_MASK_R_WMAC_CTX_SUBTYPE << BIT_SHIFT_R_WMAC_CTX_SUBTYPE) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) ((x) & (~BITS_R_WMAC_CTX_SUBTYPE)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE(x) \ + (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE) +#define BIT_SET_R_WMAC_CTX_SUBTYPE(x, v) \ + (BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) | BIT_R_WMAC_CTX_SUBTYPE(v)) + +#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE 0 +#define BIT_MASK_R_WMAC_RTX_SUBTYPE 0xf +#define BIT_R_WMAC_RTX_SUBTYPE(x) \ + (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE) +#define BITS_R_WMAC_RTX_SUBTYPE \ + (BIT_MASK_R_WMAC_RTX_SUBTYPE << BIT_SHIFT_R_WMAC_RTX_SUBTYPE) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) ((x) & (~BITS_R_WMAC_RTX_SUBTYPE)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE) +#define BIT_SET_R_WMAC_RTX_SUBTYPE(x, v) \ + (BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) | BIT_R_WMAC_RTX_SUBTYPE(v)) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_WMAC_SWAES_DIO_B63_B32 (Offset 0x0754) */ + +#define BIT_SHIFT_WMAC_SWAES_DIO_B63_B32 0 +#define BIT_MASK_WMAC_SWAES_DIO_B63_B32 0xffffffffL +#define BIT_WMAC_SWAES_DIO_B63_B32(x) \ + (((x) & BIT_MASK_WMAC_SWAES_DIO_B63_B32) \ + << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32) +#define BITS_WMAC_SWAES_DIO_B63_B32 \ + (BIT_MASK_WMAC_SWAES_DIO_B63_B32 << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32) +#define BIT_CLEAR_WMAC_SWAES_DIO_B63_B32(x) \ + ((x) & (~BITS_WMAC_SWAES_DIO_B63_B32)) +#define BIT_GET_WMAC_SWAES_DIO_B63_B32(x) \ + (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B63_B32) & \ + BIT_MASK_WMAC_SWAES_DIO_B63_B32) +#define BIT_SET_WMAC_SWAES_DIO_B63_B32(x, v) \ + (BIT_CLEAR_WMAC_SWAES_DIO_B63_B32(x) | BIT_WMAC_SWAES_DIO_B63_B32(v)) + +/* 2 REG_WMAC_SWAES_DIO_B95_B64 (Offset 0x0758) */ + +#define BIT_SHIFT_WMAC_SWAES_DIO_B95_B64 0 +#define BIT_MASK_WMAC_SWAES_DIO_B95_B64 0xffffffffL +#define BIT_WMAC_SWAES_DIO_B95_B64(x) \ + (((x) & BIT_MASK_WMAC_SWAES_DIO_B95_B64) \ + << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64) +#define BITS_WMAC_SWAES_DIO_B95_B64 \ + (BIT_MASK_WMAC_SWAES_DIO_B95_B64 << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64) +#define BIT_CLEAR_WMAC_SWAES_DIO_B95_B64(x) \ + ((x) & (~BITS_WMAC_SWAES_DIO_B95_B64)) +#define BIT_GET_WMAC_SWAES_DIO_B95_B64(x) \ + (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B95_B64) & \ + BIT_MASK_WMAC_SWAES_DIO_B95_B64) +#define BIT_SET_WMAC_SWAES_DIO_B95_B64(x, v) \ + (BIT_CLEAR_WMAC_SWAES_DIO_B95_B64(x) | BIT_WMAC_SWAES_DIO_B95_B64(v)) + +/* 2 REG_WMAC_SWAES_DIO_B127_B96 (Offset 0x075C) */ + +#define BIT_SHIFT_WMAC_SWAES_DIO_B127_B96 0 +#define BIT_MASK_WMAC_SWAES_DIO_B127_B96 0xffffffffL +#define BIT_WMAC_SWAES_DIO_B127_B96(x) \ + (((x) & BIT_MASK_WMAC_SWAES_DIO_B127_B96) \ + << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96) +#define BITS_WMAC_SWAES_DIO_B127_B96 \ + (BIT_MASK_WMAC_SWAES_DIO_B127_B96 << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96) +#define BIT_CLEAR_WMAC_SWAES_DIO_B127_B96(x) \ + ((x) & (~BITS_WMAC_SWAES_DIO_B127_B96)) +#define BIT_GET_WMAC_SWAES_DIO_B127_B96(x) \ + (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B127_B96) & \ + BIT_MASK_WMAC_SWAES_DIO_B127_B96) +#define BIT_SET_WMAC_SWAES_DIO_B127_B96(x, v) \ + (BIT_CLEAR_WMAC_SWAES_DIO_B127_B96(x) | BIT_WMAC_SWAES_DIO_B127_B96(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_WLAN_ACT_MASK_CTRL_1 (Offset 0x076C) */ +/* 2 REG_BT_COEX_V2 (Offset 0x0762) */ -#define BIT_WLRX_TER_BY_CTL_1 BIT(11) -#define BIT_WLRX_TER_BY_AD_1 BIT(10) -#define BIT_ANT_DIVERSITY_SEL_1 BIT(9) -#define BIT_ANTSEL_FOR_BT_CTRL_EN_1 BIT(8) -#define BIT_WLACT_LOW_GNTWL_EN_1 BIT(2) -#define BIT_WLACT_HIGH_GNTBT_EN_1 BIT(1) -#define BIT_NAV_UPPER_1_V1 BIT(0) +#define BIT_GNT_BT_POLARITY BIT(12) +#define BIT_GNT_BT_BYPASS_PRIORITY BIT(8) -#endif +#define BIT_SHIFT_TIMER 0 +#define BIT_MASK_TIMER 0xff +#define BIT_TIMER(x) (((x) & BIT_MASK_TIMER) << BIT_SHIFT_TIMER) +#define BITS_TIMER (BIT_MASK_TIMER << BIT_SHIFT_TIMER) +#define BIT_CLEAR_TIMER(x) ((x) & (~BITS_TIMER)) +#define BIT_GET_TIMER(x) (((x) >> BIT_SHIFT_TIMER) & BIT_MASK_TIMER) +#define BIT_SET_TIMER(x, v) (BIT_CLEAR_TIMER(x) | BIT_TIMER(v)) +/* 2 REG_BT_COEX (Offset 0x0764) */ -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_R_GNT_BT_RFC_SW BIT(12) +#define BIT_R_GNT_BT_RFC_SW_EN BIT(11) +#define BIT_R_GNT_BT_BB_SW BIT(10) +#define BIT_R_GNT_BT_BB_SW_EN BIT(9) +#define BIT_R_BT_CNT_THREN BIT(8) +#define BIT_SHIFT_R_BT_CNT_THR 0 +#define BIT_MASK_R_BT_CNT_THR 0xff +#define BIT_R_BT_CNT_THR(x) \ + (((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR) +#define BITS_R_BT_CNT_THR (BIT_MASK_R_BT_CNT_THR << BIT_SHIFT_R_BT_CNT_THR) +#define BIT_CLEAR_R_BT_CNT_THR(x) ((x) & (~BITS_R_BT_CNT_THR)) +#define BIT_GET_R_BT_CNT_THR(x) \ + (((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR) +#define BIT_SET_R_BT_CNT_THR(x, v) \ + (BIT_CLEAR_R_BT_CNT_THR(x) | BIT_R_BT_CNT_THR(v)) -/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL (Offset 0x076E) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_BT_STAT_DELAY 12 -#define BIT_MASK_BT_STAT_DELAY 0xf -#define BIT_BT_STAT_DELAY(x) (((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY) -#define BIT_GET_BT_STAT_DELAY(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY) +/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ +#define BIT_WLRX_TER_BY_CTL BIT(43) +#define BIT_WLRX_TER_BY_AD BIT(42) +#define BIT_ANT_DIVERSITY_SEL BIT(41) +#define BIT_ANTSEL_FOR_BT_CTRL_EN BIT(40) +#define BIT_WLACT_LOW_GNTWL_EN BIT(34) +#define BIT_WLACT_HIGH_GNTBT_EN BIT(33) -#define BIT_SHIFT_BT_TRX_INIT_DETECT 8 -#define BIT_MASK_BT_TRX_INIT_DETECT 0xf -#define BIT_BT_TRX_INIT_DETECT(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT) -#define BIT_GET_BT_TRX_INIT_DETECT(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT) +#endif +#if (HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_BT_PRI_DETECT_TO 4 -#define BIT_MASK_BT_PRI_DETECT_TO 0xf -#define BIT_BT_PRI_DETECT_TO(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO) -#define BIT_GET_BT_PRI_DETECT_TO(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO) +/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ -#define BIT_R_GRANTALL_WLMASK BIT(3) -#define BIT_STATIS_BT_EN BIT(2) -#define BIT_WL_ACT_MASK_ENABLE BIT(1) -#define BIT_ENHANCED_BT BIT(0) +#define BIT_NAV_UPPER_V1 BIT(32) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ -/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ +#define BIT_SHIFT_RXMYRTS_NAV_V1 8 +#define BIT_MASK_RXMYRTS_NAV_V1 0xff +#define BIT_RXMYRTS_NAV_V1(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_V1) << BIT_SHIFT_RXMYRTS_NAV_V1) +#define BITS_RXMYRTS_NAV_V1 \ + (BIT_MASK_RXMYRTS_NAV_V1 << BIT_SHIFT_RXMYRTS_NAV_V1) +#define BIT_CLEAR_RXMYRTS_NAV_V1(x) ((x) & (~BITS_RXMYRTS_NAV_V1)) +#define BIT_GET_RXMYRTS_NAV_V1(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1) & BIT_MASK_RXMYRTS_NAV_V1) +#define BIT_SET_RXMYRTS_NAV_V1(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_V1(x) | BIT_RXMYRTS_NAV_V1(v)) +#define BIT_SHIFT_RTSRST_V1 0 +#define BIT_MASK_RTSRST_V1 0xff +#define BIT_RTSRST_V1(x) (((x) & BIT_MASK_RTSRST_V1) << BIT_SHIFT_RTSRST_V1) +#define BITS_RTSRST_V1 (BIT_MASK_RTSRST_V1 << BIT_SHIFT_RTSRST_V1) +#define BIT_CLEAR_RTSRST_V1(x) ((x) & (~BITS_RTSRST_V1)) +#define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1) +#define BIT_SET_RTSRST_V1(x, v) (BIT_CLEAR_RTSRST_V1(x) | BIT_RTSRST_V1(v)) -#define BIT_SHIFT_STATIS_BT_LO_RX (48 & CPU_OPT_WIDTH) -#define BIT_MASK_STATIS_BT_LO_RX 0xffff -#define BIT_STATIS_BT_LO_RX(x) (((x) & BIT_MASK_STATIS_BT_LO_RX) << BIT_SHIFT_STATIS_BT_LO_RX) -#define BIT_GET_STATIS_BT_LO_RX(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX) & BIT_MASK_STATIS_BT_LO_RX) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_STATIS_BT_LO_TX (32 & CPU_OPT_WIDTH) -#define BIT_MASK_STATIS_BT_LO_TX 0xffff -#define BIT_STATIS_BT_LO_TX(x) (((x) & BIT_MASK_STATIS_BT_LO_TX) << BIT_SHIFT_STATIS_BT_LO_TX) -#define BIT_GET_STATIS_BT_LO_TX(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX) +/* 2 REG_WLAN_ACT_MASK_CTRL_1 (Offset 0x076C) */ +#define BIT_WLRX_TER_BY_CTL_1 BIT(11) +#define BIT_WLRX_TER_BY_AD_1 BIT(10) +#define BIT_ANT_DIVERSITY_SEL_1 BIT(9) +#define BIT_ANTSEL_FOR_BT_CTRL_EN_1 BIT(8) +#define BIT_WLACT_LOW_GNTWL_EN_1 BIT(2) +#define BIT_WLACT_HIGH_GNTBT_EN_1 BIT(1) +#define BIT_NAV_UPPER_1_V1 BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL (Offset 0x076E) */ +#define BIT_SHIFT_BT_STAT_DELAY 12 +#define BIT_MASK_BT_STAT_DELAY 0xf +#define BIT_BT_STAT_DELAY(x) \ + (((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY) +#define BITS_BT_STAT_DELAY (BIT_MASK_BT_STAT_DELAY << BIT_SHIFT_BT_STAT_DELAY) +#define BIT_CLEAR_BT_STAT_DELAY(x) ((x) & (~BITS_BT_STAT_DELAY)) +#define BIT_GET_BT_STAT_DELAY(x) \ + (((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY) +#define BIT_SET_BT_STAT_DELAY(x, v) \ + (BIT_CLEAR_BT_STAT_DELAY(x) | BIT_BT_STAT_DELAY(v)) + +#define BIT_SHIFT_BT_TRX_INIT_DETECT 8 +#define BIT_MASK_BT_TRX_INIT_DETECT 0xf +#define BIT_BT_TRX_INIT_DETECT(x) \ + (((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT) +#define BITS_BT_TRX_INIT_DETECT \ + (BIT_MASK_BT_TRX_INIT_DETECT << BIT_SHIFT_BT_TRX_INIT_DETECT) +#define BIT_CLEAR_BT_TRX_INIT_DETECT(x) ((x) & (~BITS_BT_TRX_INIT_DETECT)) +#define BIT_GET_BT_TRX_INIT_DETECT(x) \ + (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT) +#define BIT_SET_BT_TRX_INIT_DETECT(x, v) \ + (BIT_CLEAR_BT_TRX_INIT_DETECT(x) | BIT_BT_TRX_INIT_DETECT(v)) + +#define BIT_SHIFT_BT_PRI_DETECT_TO 4 +#define BIT_MASK_BT_PRI_DETECT_TO 0xf +#define BIT_BT_PRI_DETECT_TO(x) \ + (((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO) +#define BITS_BT_PRI_DETECT_TO \ + (BIT_MASK_BT_PRI_DETECT_TO << BIT_SHIFT_BT_PRI_DETECT_TO) +#define BIT_CLEAR_BT_PRI_DETECT_TO(x) ((x) & (~BITS_BT_PRI_DETECT_TO)) +#define BIT_GET_BT_PRI_DETECT_TO(x) \ + (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO) +#define BIT_SET_BT_PRI_DETECT_TO(x, v) \ + (BIT_CLEAR_BT_PRI_DETECT_TO(x) | BIT_BT_PRI_DETECT_TO(v)) + +#define BIT_R_GRANTALL_WLMASK BIT(3) +#define BIT_STATIS_BT_EN BIT(2) +#define BIT_WL_ACT_MASK_ENABLE BIT(1) +#define BIT_ENHANCED_BT BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ +#define BIT_SHIFT_STATIS_BT_LO_RX (48 & CPU_OPT_WIDTH) +#define BIT_MASK_STATIS_BT_LO_RX 0xffff +#define BIT_STATIS_BT_LO_RX(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX) << BIT_SHIFT_STATIS_BT_LO_RX) +#define BITS_STATIS_BT_LO_RX \ + (BIT_MASK_STATIS_BT_LO_RX << BIT_SHIFT_STATIS_BT_LO_RX) +#define BIT_CLEAR_STATIS_BT_LO_RX(x) ((x) & (~BITS_STATIS_BT_LO_RX)) +#define BIT_GET_STATIS_BT_LO_RX(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX) & BIT_MASK_STATIS_BT_LO_RX) +#define BIT_SET_STATIS_BT_LO_RX(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX(x) | BIT_STATIS_BT_LO_RX(v)) + +#define BIT_SHIFT_STATIS_BT_LO_TX (32 & CPU_OPT_WIDTH) +#define BIT_MASK_STATIS_BT_LO_TX 0xffff +#define BIT_STATIS_BT_LO_TX(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX) << BIT_SHIFT_STATIS_BT_LO_TX) +#define BITS_STATIS_BT_LO_TX \ + (BIT_MASK_STATIS_BT_LO_TX << BIT_SHIFT_STATIS_BT_LO_TX) +#define BIT_CLEAR_STATIS_BT_LO_TX(x) ((x) & (~BITS_STATIS_BT_LO_TX)) +#define BIT_GET_STATIS_BT_LO_TX(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX) +#define BIT_SET_STATIS_BT_LO_TX(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX(x) | BIT_STATIS_BT_LO_TX(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_STATIS_BT_HI_RX 16 -#define BIT_MASK_STATIS_BT_HI_RX 0xffff -#define BIT_STATIS_BT_HI_RX(x) (((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX) -#define BIT_GET_STATIS_BT_HI_RX(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX) & BIT_MASK_STATIS_BT_HI_RX) - - -#define BIT_SHIFT_STATIS_BT_HI_TX 0 -#define BIT_MASK_STATIS_BT_HI_TX 0xffff -#define BIT_STATIS_BT_HI_TX(x) (((x) & BIT_MASK_STATIS_BT_HI_TX) << BIT_SHIFT_STATIS_BT_HI_TX) -#define BIT_GET_STATIS_BT_HI_TX(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX) +/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ +#define BIT_SHIFT_STATIS_BT_HI_RX 16 +#define BIT_MASK_STATIS_BT_HI_RX 0xffff +#define BIT_STATIS_BT_HI_RX(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX) +#define BITS_STATIS_BT_HI_RX \ + (BIT_MASK_STATIS_BT_HI_RX << BIT_SHIFT_STATIS_BT_HI_RX) +#define BIT_CLEAR_STATIS_BT_HI_RX(x) ((x) & (~BITS_STATIS_BT_HI_RX)) +#define BIT_GET_STATIS_BT_HI_RX(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_RX) & BIT_MASK_STATIS_BT_HI_RX) +#define BIT_SET_STATIS_BT_HI_RX(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_RX(x) | BIT_STATIS_BT_HI_RX(v)) + +#define BIT_SHIFT_STATIS_BT_HI_TX 0 +#define BIT_MASK_STATIS_BT_HI_TX 0xffff +#define BIT_STATIS_BT_HI_TX(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_TX) << BIT_SHIFT_STATIS_BT_HI_TX) +#define BITS_STATIS_BT_HI_TX \ + (BIT_MASK_STATIS_BT_HI_TX << BIT_SHIFT_STATIS_BT_HI_TX) +#define BIT_CLEAR_STATIS_BT_HI_TX(x) ((x) & (~BITS_STATIS_BT_HI_TX)) +#define BIT_GET_STATIS_BT_HI_TX(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX) +#define BIT_SET_STATIS_BT_HI_TX(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_TX(x) | BIT_STATIS_BT_HI_TX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BT_ACT_STATISTICS_1 (Offset 0x0774) */ +#define BIT_SHIFT_STATIS_BT_LO_RX_1 16 +#define BIT_MASK_STATIS_BT_LO_RX_1 0xffff +#define BIT_STATIS_BT_LO_RX_1(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX_1) << BIT_SHIFT_STATIS_BT_LO_RX_1) +#define BITS_STATIS_BT_LO_RX_1 \ + (BIT_MASK_STATIS_BT_LO_RX_1 << BIT_SHIFT_STATIS_BT_LO_RX_1) +#define BIT_CLEAR_STATIS_BT_LO_RX_1(x) ((x) & (~BITS_STATIS_BT_LO_RX_1)) +#define BIT_GET_STATIS_BT_LO_RX_1(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1) & BIT_MASK_STATIS_BT_LO_RX_1) +#define BIT_SET_STATIS_BT_LO_RX_1(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX_1(x) | BIT_STATIS_BT_LO_RX_1(v)) + +#define BIT_SHIFT_STATIS_BT_LO_TX_1 0 +#define BIT_MASK_STATIS_BT_LO_TX_1 0xffff +#define BIT_STATIS_BT_LO_TX_1(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX_1) << BIT_SHIFT_STATIS_BT_LO_TX_1) +#define BITS_STATIS_BT_LO_TX_1 \ + (BIT_MASK_STATIS_BT_LO_TX_1 << BIT_SHIFT_STATIS_BT_LO_TX_1) +#define BIT_CLEAR_STATIS_BT_LO_TX_1(x) ((x) & (~BITS_STATIS_BT_LO_TX_1)) +#define BIT_GET_STATIS_BT_LO_TX_1(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1) & BIT_MASK_STATIS_BT_LO_TX_1) +#define BIT_SET_STATIS_BT_LO_TX_1(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX_1(x) | BIT_STATIS_BT_LO_TX_1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_BT_STATISTICS_CONTROL_REGISTER (Offset 0x0778) */ +#define BIT_SHIFT_R_BT_CMD_RPT 16 +#define BIT_MASK_R_BT_CMD_RPT 0xffff +#define BIT_R_BT_CMD_RPT(x) \ + (((x) & BIT_MASK_R_BT_CMD_RPT) << BIT_SHIFT_R_BT_CMD_RPT) +#define BITS_R_BT_CMD_RPT (BIT_MASK_R_BT_CMD_RPT << BIT_SHIFT_R_BT_CMD_RPT) +#define BIT_CLEAR_R_BT_CMD_RPT(x) ((x) & (~BITS_R_BT_CMD_RPT)) +#define BIT_GET_R_BT_CMD_RPT(x) \ + (((x) >> BIT_SHIFT_R_BT_CMD_RPT) & BIT_MASK_R_BT_CMD_RPT) +#define BIT_SET_R_BT_CMD_RPT(x, v) \ + (BIT_CLEAR_R_BT_CMD_RPT(x) | BIT_R_BT_CMD_RPT(v)) + +#define BIT_SHIFT_R_RPT_FROM_BT 8 +#define BIT_MASK_R_RPT_FROM_BT 0xff +#define BIT_R_RPT_FROM_BT(x) \ + (((x) & BIT_MASK_R_RPT_FROM_BT) << BIT_SHIFT_R_RPT_FROM_BT) +#define BITS_R_RPT_FROM_BT (BIT_MASK_R_RPT_FROM_BT << BIT_SHIFT_R_RPT_FROM_BT) +#define BIT_CLEAR_R_RPT_FROM_BT(x) ((x) & (~BITS_R_RPT_FROM_BT)) +#define BIT_GET_R_RPT_FROM_BT(x) \ + (((x) >> BIT_SHIFT_R_RPT_FROM_BT) & BIT_MASK_R_RPT_FROM_BT) +#define BIT_SET_R_RPT_FROM_BT(x, v) \ + (BIT_CLEAR_R_RPT_FROM_BT(x) | BIT_R_RPT_FROM_BT(v)) + +#define BIT_SHIFT_BT_HID_ISR_SET 6 +#define BIT_MASK_BT_HID_ISR_SET 0x3 +#define BIT_BT_HID_ISR_SET(x) \ + (((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET) +#define BITS_BT_HID_ISR_SET \ + (BIT_MASK_BT_HID_ISR_SET << BIT_SHIFT_BT_HID_ISR_SET) +#define BIT_CLEAR_BT_HID_ISR_SET(x) ((x) & (~BITS_BT_HID_ISR_SET)) +#define BIT_GET_BT_HID_ISR_SET(x) \ + (((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET) +#define BIT_SET_BT_HID_ISR_SET(x, v) \ + (BIT_CLEAR_BT_HID_ISR_SET(x) | BIT_BT_HID_ISR_SET(v)) + +#define BIT_TDMA_BT_START_NOTIFY BIT(5) +#define BIT_ENABLE_TDMA_FW_MODE BIT(4) +#define BIT_ENABLE_PTA_TDMA_MODE BIT(3) +#define BIT_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) +#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) +#define BIT_RTK_BT_ENABLE BIT(0) -/* 2 REG_BT_ACT_STATISTICS_1 (Offset 0x0774) */ +/* 2 REG_BT_STATUS_REPORT_REGISTER (Offset 0x077C) */ +#define BIT_SHIFT_BT_PROFILE 24 +#define BIT_MASK_BT_PROFILE 0xff +#define BIT_BT_PROFILE(x) (((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE) +#define BITS_BT_PROFILE (BIT_MASK_BT_PROFILE << BIT_SHIFT_BT_PROFILE) +#define BIT_CLEAR_BT_PROFILE(x) ((x) & (~BITS_BT_PROFILE)) +#define BIT_GET_BT_PROFILE(x) \ + (((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE) +#define BIT_SET_BT_PROFILE(x, v) (BIT_CLEAR_BT_PROFILE(x) | BIT_BT_PROFILE(v)) + +#define BIT_SHIFT_BT_POWER 16 +#define BIT_MASK_BT_POWER 0xff +#define BIT_BT_POWER(x) (((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER) +#define BITS_BT_POWER (BIT_MASK_BT_POWER << BIT_SHIFT_BT_POWER) +#define BIT_CLEAR_BT_POWER(x) ((x) & (~BITS_BT_POWER)) +#define BIT_GET_BT_POWER(x) (((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER) +#define BIT_SET_BT_POWER(x, v) (BIT_CLEAR_BT_POWER(x) | BIT_BT_POWER(v)) + +#define BIT_SHIFT_BT_PREDECT_STATUS 8 +#define BIT_MASK_BT_PREDECT_STATUS 0xff +#define BIT_BT_PREDECT_STATUS(x) \ + (((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS) +#define BITS_BT_PREDECT_STATUS \ + (BIT_MASK_BT_PREDECT_STATUS << BIT_SHIFT_BT_PREDECT_STATUS) +#define BIT_CLEAR_BT_PREDECT_STATUS(x) ((x) & (~BITS_BT_PREDECT_STATUS)) +#define BIT_GET_BT_PREDECT_STATUS(x) \ + (((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS) +#define BIT_SET_BT_PREDECT_STATUS(x, v) \ + (BIT_CLEAR_BT_PREDECT_STATUS(x) | BIT_BT_PREDECT_STATUS(v)) + +#define BIT_SHIFT_BT_CMD_INFO 0 +#define BIT_MASK_BT_CMD_INFO 0xff +#define BIT_BT_CMD_INFO(x) \ + (((x) & BIT_MASK_BT_CMD_INFO) << BIT_SHIFT_BT_CMD_INFO) +#define BITS_BT_CMD_INFO (BIT_MASK_BT_CMD_INFO << BIT_SHIFT_BT_CMD_INFO) +#define BIT_CLEAR_BT_CMD_INFO(x) ((x) & (~BITS_BT_CMD_INFO)) +#define BIT_GET_BT_CMD_INFO(x) \ + (((x) >> BIT_SHIFT_BT_CMD_INFO) & BIT_MASK_BT_CMD_INFO) +#define BIT_SET_BT_CMD_INFO(x, v) \ + (BIT_CLEAR_BT_CMD_INFO(x) | BIT_BT_CMD_INFO(v)) -#define BIT_SHIFT_STATIS_BT_LO_RX_1 16 -#define BIT_MASK_STATIS_BT_LO_RX_1 0xffff -#define BIT_STATIS_BT_LO_RX_1(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_1) << BIT_SHIFT_STATIS_BT_LO_RX_1) -#define BIT_GET_STATIS_BT_LO_RX_1(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1) & BIT_MASK_STATIS_BT_LO_RX_1) +/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER (Offset 0x0780) */ +#define BIT_EN_MAC_NULL_PKT_NOTIFY BIT(31) +#define BIT_EN_WLAN_RPT_AND_BT_QUERY BIT(30) +#define BIT_EN_BT_STSTUS_RPT BIT(29) +#define BIT_EN_BT_POWER BIT(28) +#define BIT_EN_BT_CHANNEL BIT(27) +#define BIT_EN_BT_SLOT_CHANGE BIT(26) +#define BIT_EN_BT_PROFILE_OR_HID BIT(25) +#define BIT_WLAN_RPT_NOTIFY BIT(24) + +#define BIT_SHIFT_WLAN_RPT_DATA 16 +#define BIT_MASK_WLAN_RPT_DATA 0xff +#define BIT_WLAN_RPT_DATA(x) \ + (((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA) +#define BITS_WLAN_RPT_DATA (BIT_MASK_WLAN_RPT_DATA << BIT_SHIFT_WLAN_RPT_DATA) +#define BIT_CLEAR_WLAN_RPT_DATA(x) ((x) & (~BITS_WLAN_RPT_DATA)) +#define BIT_GET_WLAN_RPT_DATA(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA) +#define BIT_SET_WLAN_RPT_DATA(x, v) \ + (BIT_CLEAR_WLAN_RPT_DATA(x) | BIT_WLAN_RPT_DATA(v)) + +#define BIT_SHIFT_CMD_ID 8 +#define BIT_MASK_CMD_ID 0xff +#define BIT_CMD_ID(x) (((x) & BIT_MASK_CMD_ID) << BIT_SHIFT_CMD_ID) +#define BITS_CMD_ID (BIT_MASK_CMD_ID << BIT_SHIFT_CMD_ID) +#define BIT_CLEAR_CMD_ID(x) ((x) & (~BITS_CMD_ID)) +#define BIT_GET_CMD_ID(x) (((x) >> BIT_SHIFT_CMD_ID) & BIT_MASK_CMD_ID) +#define BIT_SET_CMD_ID(x, v) (BIT_CLEAR_CMD_ID(x) | BIT_CMD_ID(v)) + +#define BIT_SHIFT_BT_DATA 0 +#define BIT_MASK_BT_DATA 0xff +#define BIT_BT_DATA(x) (((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA) +#define BITS_BT_DATA (BIT_MASK_BT_DATA << BIT_SHIFT_BT_DATA) +#define BIT_CLEAR_BT_DATA(x) ((x) & (~BITS_BT_DATA)) +#define BIT_GET_BT_DATA(x) (((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA) +#define BIT_SET_BT_DATA(x, v) (BIT_CLEAR_BT_DATA(x) | BIT_BT_DATA(v)) -#define BIT_SHIFT_STATIS_BT_LO_TX_1 0 -#define BIT_MASK_STATIS_BT_LO_TX_1 0xffff -#define BIT_STATIS_BT_LO_TX_1(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_1) << BIT_SHIFT_STATIS_BT_LO_TX_1) -#define BIT_GET_STATIS_BT_LO_TX_1(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1) & BIT_MASK_STATIS_BT_LO_TX_1) +/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */ +#define BIT_SHIFT_WLAN_RPT_TO 0 +#define BIT_MASK_WLAN_RPT_TO 0xff +#define BIT_WLAN_RPT_TO(x) \ + (((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO) +#define BITS_WLAN_RPT_TO (BIT_MASK_WLAN_RPT_TO << BIT_SHIFT_WLAN_RPT_TO) +#define BIT_CLEAR_WLAN_RPT_TO(x) ((x) & (~BITS_WLAN_RPT_TO)) +#define BIT_GET_WLAN_RPT_TO(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO) +#define BIT_SET_WLAN_RPT_TO(x, v) \ + (BIT_CLEAR_WLAN_RPT_TO(x) | BIT_WLAN_RPT_TO(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ +#define BIT_SHIFT_ISOLATION_CHK 1 +#define BIT_MASK_ISOLATION_CHK 0x7fffffffffffffffffffL +#define BIT_ISOLATION_CHK(x) \ + (((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK) +#define BITS_ISOLATION_CHK (BIT_MASK_ISOLATION_CHK << BIT_SHIFT_ISOLATION_CHK) +#define BIT_CLEAR_ISOLATION_CHK(x) ((x) & (~BITS_ISOLATION_CHK)) +#define BIT_GET_ISOLATION_CHK(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK) +#define BIT_SET_ISOLATION_CHK(x, v) \ + (BIT_CLEAR_ISOLATION_CHK(x) | BIT_ISOLATION_CHK(v)) -/* 2 REG_BT_STATISTICS_CONTROL_REGISTER (Offset 0x0778) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_BT_CMD_RPT 16 -#define BIT_MASK_R_BT_CMD_RPT 0xffff -#define BIT_R_BT_CMD_RPT(x) (((x) & BIT_MASK_R_BT_CMD_RPT) << BIT_SHIFT_R_BT_CMD_RPT) -#define BIT_GET_R_BT_CMD_RPT(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT) & BIT_MASK_R_BT_CMD_RPT) +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ +#define BIT_SHIFT_ISOLATION_CHK_0 1 +#define BIT_MASK_ISOLATION_CHK_0 0x7fffff +#define BIT_ISOLATION_CHK_0(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_0) << BIT_SHIFT_ISOLATION_CHK_0) +#define BITS_ISOLATION_CHK_0 \ + (BIT_MASK_ISOLATION_CHK_0 << BIT_SHIFT_ISOLATION_CHK_0) +#define BIT_CLEAR_ISOLATION_CHK_0(x) ((x) & (~BITS_ISOLATION_CHK_0)) +#define BIT_GET_ISOLATION_CHK_0(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_0) & BIT_MASK_ISOLATION_CHK_0) +#define BIT_SET_ISOLATION_CHK_0(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_0(x) | BIT_ISOLATION_CHK_0(v)) -#define BIT_SHIFT_R_RPT_FROM_BT 8 -#define BIT_MASK_R_RPT_FROM_BT 0xff -#define BIT_R_RPT_FROM_BT(x) (((x) & BIT_MASK_R_RPT_FROM_BT) << BIT_SHIFT_R_RPT_FROM_BT) -#define BIT_GET_R_RPT_FROM_BT(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT) & BIT_MASK_R_RPT_FROM_BT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BT_HID_ISR_SET 6 -#define BIT_MASK_BT_HID_ISR_SET 0x3 -#define BIT_BT_HID_ISR_SET(x) (((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET) -#define BIT_GET_BT_HID_ISR_SET(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET) +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ -#define BIT_TDMA_BT_START_NOTIFY BIT(5) -#define BIT_ENABLE_TDMA_FW_MODE BIT(4) -#define BIT_ENABLE_PTA_TDMA_MODE BIT(3) -#define BIT_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) -#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) -#define BIT_RTK_BT_ENABLE BIT(0) +#define BIT_ISOLATION_EN BIT(0) -/* 2 REG_BT_STATUS_REPORT_REGISTER (Offset 0x077C) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BT_PROFILE 24 -#define BIT_MASK_BT_PROFILE 0xff -#define BIT_BT_PROFILE(x) (((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE) -#define BIT_GET_BT_PROFILE(x) (((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE) +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 (Offset 0x0788) */ +#define BIT_SHIFT_ISOLATION_CHK_1 0 +#define BIT_MASK_ISOLATION_CHK_1 0xffffffffL +#define BIT_ISOLATION_CHK_1(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_1) << BIT_SHIFT_ISOLATION_CHK_1) +#define BITS_ISOLATION_CHK_1 \ + (BIT_MASK_ISOLATION_CHK_1 << BIT_SHIFT_ISOLATION_CHK_1) +#define BIT_CLEAR_ISOLATION_CHK_1(x) ((x) & (~BITS_ISOLATION_CHK_1)) +#define BIT_GET_ISOLATION_CHK_1(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_1) & BIT_MASK_ISOLATION_CHK_1) +#define BIT_SET_ISOLATION_CHK_1(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_1(x) | BIT_ISOLATION_CHK_1(v)) -#define BIT_SHIFT_BT_POWER 16 -#define BIT_MASK_BT_POWER 0xff -#define BIT_BT_POWER(x) (((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER) -#define BIT_GET_BT_POWER(x) (((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER) +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 (Offset 0x078C) */ +#define BIT_APPEND_MACID_IN_RESP_EN_1 BIT(18) +#define BIT_ADDR2_MATCH_EN_1 BIT(17) +#define BIT_ANTTRN_EN_1 BIT(16) -#define BIT_SHIFT_BT_PREDECT_STATUS 8 -#define BIT_MASK_BT_PREDECT_STATUS 0xff -#define BIT_BT_PREDECT_STATUS(x) (((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS) -#define BIT_GET_BT_PREDECT_STATUS(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS) +#define BIT_SHIFT_ISOLATION_CHK_2 0 +#define BIT_MASK_ISOLATION_CHK_2 0xffffff +#define BIT_ISOLATION_CHK_2(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_2) << BIT_SHIFT_ISOLATION_CHK_2) +#define BITS_ISOLATION_CHK_2 \ + (BIT_MASK_ISOLATION_CHK_2 << BIT_SHIFT_ISOLATION_CHK_2) +#define BIT_CLEAR_ISOLATION_CHK_2(x) ((x) & (~BITS_ISOLATION_CHK_2)) +#define BIT_GET_ISOLATION_CHK_2(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_2) & BIT_MASK_ISOLATION_CHK_2) +#define BIT_SET_ISOLATION_CHK_2(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_2(x) | BIT_ISOLATION_CHK_2(v)) +#endif -#define BIT_SHIFT_BT_CMD_INFO 0 -#define BIT_MASK_BT_CMD_INFO 0xff -#define BIT_BT_CMD_INFO(x) (((x) & BIT_MASK_BT_CMD_INFO) << BIT_SHIFT_BT_CMD_INFO) -#define BIT_GET_BT_CMD_INFO(x) (((x) >> BIT_SHIFT_BT_CMD_INFO) & BIT_MASK_BT_CMD_INFO) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_BT_INTERRUPT_STATUS_REGISTER (Offset 0x078F) */ -/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER (Offset 0x0780) */ +#define BIT_BT_HID_ISR BIT(7) +#define BIT_BT_QUERY_ISR BIT(6) +#define BIT_MAC_NULL_PKT_NOTIFY_ISR BIT(5) +#define BIT_WLAN_RPT_ISR BIT(4) +#define BIT_BT_POWER_ISR BIT(3) +#define BIT_BT_CHANNEL_ISR BIT(2) +#define BIT_BT_SLOT_CHANGE_ISR BIT(1) +#define BIT_BT_PROFILE_ISR BIT(0) -#define BIT_EN_MAC_NULL_PKT_NOTIFY BIT(31) -#define BIT_EN_WLAN_RPT_AND_BT_QUERY BIT(30) -#define BIT_EN_BT_STSTUS_RPT BIT(29) -#define BIT_EN_BT_POWER BIT(28) -#define BIT_EN_BT_CHANNEL BIT(27) -#define BIT_EN_BT_SLOT_CHANGE BIT(26) -#define BIT_EN_BT_PROFILE_OR_HID BIT(25) -#define BIT_WLAN_RPT_NOTIFY BIT(24) +/* 2 REG_BT_TDMA_TIME_REGISTER (Offset 0x0790) */ -#define BIT_SHIFT_WLAN_RPT_DATA 16 -#define BIT_MASK_WLAN_RPT_DATA 0xff -#define BIT_WLAN_RPT_DATA(x) (((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA) -#define BIT_GET_WLAN_RPT_DATA(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA) +#define BIT_SHIFT_BT_TIME 6 +#define BIT_MASK_BT_TIME 0x3ffffff +#define BIT_BT_TIME(x) (((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME) +#define BITS_BT_TIME (BIT_MASK_BT_TIME << BIT_SHIFT_BT_TIME) +#define BIT_CLEAR_BT_TIME(x) ((x) & (~BITS_BT_TIME)) +#define BIT_GET_BT_TIME(x) (((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME) +#define BIT_SET_BT_TIME(x, v) (BIT_CLEAR_BT_TIME(x) | BIT_BT_TIME(v)) +#define BIT_SHIFT_BT_RPT_SAMPLE_RATE 0 +#define BIT_MASK_BT_RPT_SAMPLE_RATE 0x3f +#define BIT_BT_RPT_SAMPLE_RATE(x) \ + (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE) +#define BITS_BT_RPT_SAMPLE_RATE \ + (BIT_MASK_BT_RPT_SAMPLE_RATE << BIT_SHIFT_BT_RPT_SAMPLE_RATE) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) ((x) & (~BITS_BT_RPT_SAMPLE_RATE)) +#define BIT_GET_BT_RPT_SAMPLE_RATE(x) \ + (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE) +#define BIT_SET_BT_RPT_SAMPLE_RATE(x, v) \ + (BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) | BIT_BT_RPT_SAMPLE_RATE(v)) -#define BIT_SHIFT_CMD_ID 8 -#define BIT_MASK_CMD_ID 0xff -#define BIT_CMD_ID(x) (((x) & BIT_MASK_CMD_ID) << BIT_SHIFT_CMD_ID) -#define BIT_GET_CMD_ID(x) (((x) >> BIT_SHIFT_CMD_ID) & BIT_MASK_CMD_ID) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_BT_DATA 0 -#define BIT_MASK_BT_DATA 0xff -#define BIT_BT_DATA(x) (((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA) -#define BIT_GET_BT_DATA(x) (((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA) +/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ +#define BIT_SHIFT_R_OFDM_LEN 26 +#define BIT_MASK_R_OFDM_LEN 0x3f +#define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN) +#define BITS_R_OFDM_LEN (BIT_MASK_R_OFDM_LEN << BIT_SHIFT_R_OFDM_LEN) +#define BIT_CLEAR_R_OFDM_LEN(x) ((x) & (~BITS_R_OFDM_LEN)) +#define BIT_GET_R_OFDM_LEN(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN) & BIT_MASK_R_OFDM_LEN) +#define BIT_SET_R_OFDM_LEN(x, v) (BIT_CLEAR_R_OFDM_LEN(x) | BIT_R_OFDM_LEN(v)) -/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */ +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ -#define BIT_SHIFT_WLAN_RPT_TO 0 -#define BIT_MASK_WLAN_RPT_TO 0xff -#define BIT_WLAN_RPT_TO(x) (((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO) -#define BIT_GET_WLAN_RPT_TO(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO) +#define BIT_SHIFT_BT_EISR_EN 16 +#define BIT_MASK_BT_EISR_EN 0xff +#define BIT_BT_EISR_EN(x) (((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN) +#define BITS_BT_EISR_EN (BIT_MASK_BT_EISR_EN << BIT_SHIFT_BT_EISR_EN) +#define BIT_CLEAR_BT_EISR_EN(x) ((x) & (~BITS_BT_EISR_EN)) +#define BIT_GET_BT_EISR_EN(x) \ + (((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN) +#define BIT_SET_BT_EISR_EN(x, v) (BIT_CLEAR_BT_EISR_EN(x) | BIT_BT_EISR_EN(v)) +#define BIT_BT_ACT_FALLING_ISR BIT(10) +#define BIT_BT_ACT_RISING_ISR BIT(9) +#define BIT_TDMA_TO_ISR BIT(8) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ +#define BIT_SHIFT_BT_CH 0 +#define BIT_MASK_BT_CH 0xff +#define BIT_BT_CH(x) (((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH) +#define BITS_BT_CH (BIT_MASK_BT_CH << BIT_SHIFT_BT_CH) +#define BIT_CLEAR_BT_CH(x) ((x) & (~BITS_BT_CH)) +#define BIT_GET_BT_CH(x) (((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH) +#define BIT_SET_BT_CH(x, v) (BIT_CLEAR_BT_CH(x) | BIT_BT_CH(v)) -/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_ISOLATION_CHK 1 -#define BIT_MASK_ISOLATION_CHK 0x7fffffffffffffffffffL -#define BIT_ISOLATION_CHK(x) (((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK) -#define BIT_GET_ISOLATION_CHK(x) (((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK) +/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ +#define BIT_SHIFT_BT_CH_V1 0 +#define BIT_MASK_BT_CH_V1 0x7f +#define BIT_BT_CH_V1(x) (((x) & BIT_MASK_BT_CH_V1) << BIT_SHIFT_BT_CH_V1) +#define BITS_BT_CH_V1 (BIT_MASK_BT_CH_V1 << BIT_SHIFT_BT_CH_V1) +#define BIT_CLEAR_BT_CH_V1(x) ((x) & (~BITS_BT_CH_V1)) +#define BIT_GET_BT_CH_V1(x) (((x) >> BIT_SHIFT_BT_CH_V1) & BIT_MASK_BT_CH_V1) +#define BIT_SET_BT_CH_V1(x, v) (BIT_CLEAR_BT_CH_V1(x) | BIT_BT_CH_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_OBFF_CTRL_BASIC (Offset 0x0798) */ +#define BIT_OBFF_EN_V1 BIT(31) + +#define BIT_SHIFT_OBFF_STATE_V1 28 +#define BIT_MASK_OBFF_STATE_V1 0x3 +#define BIT_OBFF_STATE_V1(x) \ + (((x) & BIT_MASK_OBFF_STATE_V1) << BIT_SHIFT_OBFF_STATE_V1) +#define BITS_OBFF_STATE_V1 (BIT_MASK_OBFF_STATE_V1 << BIT_SHIFT_OBFF_STATE_V1) +#define BIT_CLEAR_OBFF_STATE_V1(x) ((x) & (~BITS_OBFF_STATE_V1)) +#define BIT_GET_OBFF_STATE_V1(x) \ + (((x) >> BIT_SHIFT_OBFF_STATE_V1) & BIT_MASK_OBFF_STATE_V1) +#define BIT_SET_OBFF_STATE_V1(x, v) \ + (BIT_CLEAR_OBFF_STATE_V1(x) | BIT_OBFF_STATE_V1(v)) + +#define BIT_OBFF_ACT_RXDMA_EN BIT(27) +#define BIT_OBFF_BLOCK_INT_EN BIT(26) +#define BIT_OBFF_AUTOACT_EN BIT(25) +#define BIT_OBFF_AUTOIDLE_EN BIT(24) + +#define BIT_SHIFT_WAKE_MAX_PLS 20 +#define BIT_MASK_WAKE_MAX_PLS 0x7 +#define BIT_WAKE_MAX_PLS(x) \ + (((x) & BIT_MASK_WAKE_MAX_PLS) << BIT_SHIFT_WAKE_MAX_PLS) +#define BITS_WAKE_MAX_PLS (BIT_MASK_WAKE_MAX_PLS << BIT_SHIFT_WAKE_MAX_PLS) +#define BIT_CLEAR_WAKE_MAX_PLS(x) ((x) & (~BITS_WAKE_MAX_PLS)) +#define BIT_GET_WAKE_MAX_PLS(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_PLS) & BIT_MASK_WAKE_MAX_PLS) +#define BIT_SET_WAKE_MAX_PLS(x, v) \ + (BIT_CLEAR_WAKE_MAX_PLS(x) | BIT_WAKE_MAX_PLS(v)) + +#define BIT_SHIFT_WAKE_MIN_PLS 16 +#define BIT_MASK_WAKE_MIN_PLS 0x7 +#define BIT_WAKE_MIN_PLS(x) \ + (((x) & BIT_MASK_WAKE_MIN_PLS) << BIT_SHIFT_WAKE_MIN_PLS) +#define BITS_WAKE_MIN_PLS (BIT_MASK_WAKE_MIN_PLS << BIT_SHIFT_WAKE_MIN_PLS) +#define BIT_CLEAR_WAKE_MIN_PLS(x) ((x) & (~BITS_WAKE_MIN_PLS)) +#define BIT_GET_WAKE_MIN_PLS(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_PLS) & BIT_MASK_WAKE_MIN_PLS) +#define BIT_SET_WAKE_MIN_PLS(x, v) \ + (BIT_CLEAR_WAKE_MIN_PLS(x) | BIT_WAKE_MIN_PLS(v)) + +#define BIT_SHIFT_WAKE_MAX_F2F 12 +#define BIT_MASK_WAKE_MAX_F2F 0x7 +#define BIT_WAKE_MAX_F2F(x) \ + (((x) & BIT_MASK_WAKE_MAX_F2F) << BIT_SHIFT_WAKE_MAX_F2F) +#define BITS_WAKE_MAX_F2F (BIT_MASK_WAKE_MAX_F2F << BIT_SHIFT_WAKE_MAX_F2F) +#define BIT_CLEAR_WAKE_MAX_F2F(x) ((x) & (~BITS_WAKE_MAX_F2F)) +#define BIT_GET_WAKE_MAX_F2F(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_F2F) & BIT_MASK_WAKE_MAX_F2F) +#define BIT_SET_WAKE_MAX_F2F(x, v) \ + (BIT_CLEAR_WAKE_MAX_F2F(x) | BIT_WAKE_MAX_F2F(v)) + +#define BIT_SHIFT_WAKE_MIN_F2F 8 +#define BIT_MASK_WAKE_MIN_F2F 0x7 +#define BIT_WAKE_MIN_F2F(x) \ + (((x) & BIT_MASK_WAKE_MIN_F2F) << BIT_SHIFT_WAKE_MIN_F2F) +#define BITS_WAKE_MIN_F2F (BIT_MASK_WAKE_MIN_F2F << BIT_SHIFT_WAKE_MIN_F2F) +#define BIT_CLEAR_WAKE_MIN_F2F(x) ((x) & (~BITS_WAKE_MIN_F2F)) +#define BIT_GET_WAKE_MIN_F2F(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_F2F) & BIT_MASK_WAKE_MIN_F2F) +#define BIT_SET_WAKE_MIN_F2F(x, v) \ + (BIT_CLEAR_WAKE_MIN_F2F(x) | BIT_WAKE_MIN_F2F(v)) + +#define BIT_APP_CPU_ACT_V1 BIT(3) +#define BIT_APP_OBFF_V1 BIT(2) +#define BIT_APP_IDLE_V1 BIT(1) +#define BIT_APP_INIT_V1 BIT(0) -/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ +/* 2 REG_OBFF_CTRL2_TIMER (Offset 0x079C) */ +#define BIT_SHIFT_RX_HIGH_TIMER_IDX 24 +#define BIT_MASK_RX_HIGH_TIMER_IDX 0x7 +#define BIT_RX_HIGH_TIMER_IDX(x) \ + (((x) & BIT_MASK_RX_HIGH_TIMER_IDX) << BIT_SHIFT_RX_HIGH_TIMER_IDX) +#define BITS_RX_HIGH_TIMER_IDX \ + (BIT_MASK_RX_HIGH_TIMER_IDX << BIT_SHIFT_RX_HIGH_TIMER_IDX) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX(x) ((x) & (~BITS_RX_HIGH_TIMER_IDX)) +#define BIT_GET_RX_HIGH_TIMER_IDX(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX) & BIT_MASK_RX_HIGH_TIMER_IDX) +#define BIT_SET_RX_HIGH_TIMER_IDX(x, v) \ + (BIT_CLEAR_RX_HIGH_TIMER_IDX(x) | BIT_RX_HIGH_TIMER_IDX(v)) + +#define BIT_SHIFT_RX_MED_TIMER_IDX 16 +#define BIT_MASK_RX_MED_TIMER_IDX 0x7 +#define BIT_RX_MED_TIMER_IDX(x) \ + (((x) & BIT_MASK_RX_MED_TIMER_IDX) << BIT_SHIFT_RX_MED_TIMER_IDX) +#define BITS_RX_MED_TIMER_IDX \ + (BIT_MASK_RX_MED_TIMER_IDX << BIT_SHIFT_RX_MED_TIMER_IDX) +#define BIT_CLEAR_RX_MED_TIMER_IDX(x) ((x) & (~BITS_RX_MED_TIMER_IDX)) +#define BIT_GET_RX_MED_TIMER_IDX(x) \ + (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX) & BIT_MASK_RX_MED_TIMER_IDX) +#define BIT_SET_RX_MED_TIMER_IDX(x, v) \ + (BIT_CLEAR_RX_MED_TIMER_IDX(x) | BIT_RX_MED_TIMER_IDX(v)) + +#define BIT_SHIFT_RX_LOW_TIMER_IDX 8 +#define BIT_MASK_RX_LOW_TIMER_IDX 0x7 +#define BIT_RX_LOW_TIMER_IDX(x) \ + (((x) & BIT_MASK_RX_LOW_TIMER_IDX) << BIT_SHIFT_RX_LOW_TIMER_IDX) +#define BITS_RX_LOW_TIMER_IDX \ + (BIT_MASK_RX_LOW_TIMER_IDX << BIT_SHIFT_RX_LOW_TIMER_IDX) +#define BIT_CLEAR_RX_LOW_TIMER_IDX(x) ((x) & (~BITS_RX_LOW_TIMER_IDX)) +#define BIT_GET_RX_LOW_TIMER_IDX(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX) & BIT_MASK_RX_LOW_TIMER_IDX) +#define BIT_SET_RX_LOW_TIMER_IDX(x, v) \ + (BIT_CLEAR_RX_LOW_TIMER_IDX(x) | BIT_RX_LOW_TIMER_IDX(v)) + +#define BIT_SHIFT_OBFF_INT_TIMER_IDX 0 +#define BIT_MASK_OBFF_INT_TIMER_IDX 0x7 +#define BIT_OBFF_INT_TIMER_IDX(x) \ + (((x) & BIT_MASK_OBFF_INT_TIMER_IDX) << BIT_SHIFT_OBFF_INT_TIMER_IDX) +#define BITS_OBFF_INT_TIMER_IDX \ + (BIT_MASK_OBFF_INT_TIMER_IDX << BIT_SHIFT_OBFF_INT_TIMER_IDX) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX(x) ((x) & (~BITS_OBFF_INT_TIMER_IDX)) +#define BIT_GET_OBFF_INT_TIMER_IDX(x) \ + (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX) & BIT_MASK_OBFF_INT_TIMER_IDX) +#define BIT_SET_OBFF_INT_TIMER_IDX(x, v) \ + (BIT_CLEAR_OBFF_INT_TIMER_IDX(x) | BIT_OBFF_INT_TIMER_IDX(v)) -#define BIT_SHIFT_ISOLATION_CHK_0 1 -#define BIT_MASK_ISOLATION_CHK_0 0x7fffff -#define BIT_ISOLATION_CHK_0(x) (((x) & BIT_MASK_ISOLATION_CHK_0) << BIT_SHIFT_ISOLATION_CHK_0) -#define BIT_GET_ISOLATION_CHK_0(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_0) & BIT_MASK_ISOLATION_CHK_0) +/* 2 REG_LTR_CTRL_BASIC (Offset 0x07A0) */ +#define BIT_LTR_EN_V1 BIT(31) +#define BIT_LTR_HW_EN_V1 BIT(30) +#define BIT_LRT_ACT_CTS_EN BIT(29) +#define BIT_LTR_ACT_RXPKT_EN BIT(28) +#define BIT_LTR_ACT_RXDMA_EN BIT(27) +#define BIT_LTR_IDLE_NO_SNOOP BIT(26) +#define BIT_SPDUP_MGTPKT BIT(25) +#define BIT_RX_AGG_EN BIT(24) +#define BIT_APP_LTR_ACT BIT(23) +#define BIT_APP_LTR_IDLE BIT(22) + +#define BIT_SHIFT_HIGH_RATE_TRIG_SEL 20 +#define BIT_MASK_HIGH_RATE_TRIG_SEL 0x3 +#define BIT_HIGH_RATE_TRIG_SEL(x) \ + (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL) << BIT_SHIFT_HIGH_RATE_TRIG_SEL) +#define BITS_HIGH_RATE_TRIG_SEL \ + (BIT_MASK_HIGH_RATE_TRIG_SEL << BIT_SHIFT_HIGH_RATE_TRIG_SEL) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL(x) ((x) & (~BITS_HIGH_RATE_TRIG_SEL)) +#define BIT_GET_HIGH_RATE_TRIG_SEL(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL) & BIT_MASK_HIGH_RATE_TRIG_SEL) +#define BIT_SET_HIGH_RATE_TRIG_SEL(x, v) \ + (BIT_CLEAR_HIGH_RATE_TRIG_SEL(x) | BIT_HIGH_RATE_TRIG_SEL(v)) + +#define BIT_SHIFT_MED_RATE_TRIG_SEL 18 +#define BIT_MASK_MED_RATE_TRIG_SEL 0x3 +#define BIT_MED_RATE_TRIG_SEL(x) \ + (((x) & BIT_MASK_MED_RATE_TRIG_SEL) << BIT_SHIFT_MED_RATE_TRIG_SEL) +#define BITS_MED_RATE_TRIG_SEL \ + (BIT_MASK_MED_RATE_TRIG_SEL << BIT_SHIFT_MED_RATE_TRIG_SEL) +#define BIT_CLEAR_MED_RATE_TRIG_SEL(x) ((x) & (~BITS_MED_RATE_TRIG_SEL)) +#define BIT_GET_MED_RATE_TRIG_SEL(x) \ + (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL) & BIT_MASK_MED_RATE_TRIG_SEL) +#define BIT_SET_MED_RATE_TRIG_SEL(x, v) \ + (BIT_CLEAR_MED_RATE_TRIG_SEL(x) | BIT_MED_RATE_TRIG_SEL(v)) + +#define BIT_SHIFT_LOW_RATE_TRIG_SEL 16 +#define BIT_MASK_LOW_RATE_TRIG_SEL 0x3 +#define BIT_LOW_RATE_TRIG_SEL(x) \ + (((x) & BIT_MASK_LOW_RATE_TRIG_SEL) << BIT_SHIFT_LOW_RATE_TRIG_SEL) +#define BITS_LOW_RATE_TRIG_SEL \ + (BIT_MASK_LOW_RATE_TRIG_SEL << BIT_SHIFT_LOW_RATE_TRIG_SEL) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL(x) ((x) & (~BITS_LOW_RATE_TRIG_SEL)) +#define BIT_GET_LOW_RATE_TRIG_SEL(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL) & BIT_MASK_LOW_RATE_TRIG_SEL) +#define BIT_SET_LOW_RATE_TRIG_SEL(x, v) \ + (BIT_CLEAR_LOW_RATE_TRIG_SEL(x) | BIT_LOW_RATE_TRIG_SEL(v)) + +#define BIT_SHIFT_HIGH_RATE_BD_IDX 8 +#define BIT_MASK_HIGH_RATE_BD_IDX 0x7f +#define BIT_HIGH_RATE_BD_IDX(x) \ + (((x) & BIT_MASK_HIGH_RATE_BD_IDX) << BIT_SHIFT_HIGH_RATE_BD_IDX) +#define BITS_HIGH_RATE_BD_IDX \ + (BIT_MASK_HIGH_RATE_BD_IDX << BIT_SHIFT_HIGH_RATE_BD_IDX) +#define BIT_CLEAR_HIGH_RATE_BD_IDX(x) ((x) & (~BITS_HIGH_RATE_BD_IDX)) +#define BIT_GET_HIGH_RATE_BD_IDX(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX) & BIT_MASK_HIGH_RATE_BD_IDX) +#define BIT_SET_HIGH_RATE_BD_IDX(x, v) \ + (BIT_CLEAR_HIGH_RATE_BD_IDX(x) | BIT_HIGH_RATE_BD_IDX(v)) + +#define BIT_SHIFT_LOW_RATE_BD_IDX 0 +#define BIT_MASK_LOW_RATE_BD_IDX 0x7f +#define BIT_LOW_RATE_BD_IDX(x) \ + (((x) & BIT_MASK_LOW_RATE_BD_IDX) << BIT_SHIFT_LOW_RATE_BD_IDX) +#define BITS_LOW_RATE_BD_IDX \ + (BIT_MASK_LOW_RATE_BD_IDX << BIT_SHIFT_LOW_RATE_BD_IDX) +#define BIT_CLEAR_LOW_RATE_BD_IDX(x) ((x) & (~BITS_LOW_RATE_BD_IDX)) +#define BIT_GET_LOW_RATE_BD_IDX(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX) & BIT_MASK_LOW_RATE_BD_IDX) +#define BIT_SET_LOW_RATE_BD_IDX(x, v) \ + (BIT_CLEAR_LOW_RATE_BD_IDX(x) | BIT_LOW_RATE_BD_IDX(v)) -#endif +/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD (Offset 0x07A4) */ +#define BIT_SHIFT_RX_EMPTY_TIMER_IDX 24 +#define BIT_MASK_RX_EMPTY_TIMER_IDX 0x7 +#define BIT_RX_EMPTY_TIMER_IDX(x) \ + (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX) << BIT_SHIFT_RX_EMPTY_TIMER_IDX) +#define BITS_RX_EMPTY_TIMER_IDX \ + (BIT_MASK_RX_EMPTY_TIMER_IDX << BIT_SHIFT_RX_EMPTY_TIMER_IDX) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX(x) ((x) & (~BITS_RX_EMPTY_TIMER_IDX)) +#define BIT_GET_RX_EMPTY_TIMER_IDX(x) \ + (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX) & BIT_MASK_RX_EMPTY_TIMER_IDX) +#define BIT_SET_RX_EMPTY_TIMER_IDX(x, v) \ + (BIT_CLEAR_RX_EMPTY_TIMER_IDX(x) | BIT_RX_EMPTY_TIMER_IDX(v)) + +#define BIT_SHIFT_RX_AFULL_TH_IDX 20 +#define BIT_MASK_RX_AFULL_TH_IDX 0x7 +#define BIT_RX_AFULL_TH_IDX(x) \ + (((x) & BIT_MASK_RX_AFULL_TH_IDX) << BIT_SHIFT_RX_AFULL_TH_IDX) +#define BITS_RX_AFULL_TH_IDX \ + (BIT_MASK_RX_AFULL_TH_IDX << BIT_SHIFT_RX_AFULL_TH_IDX) +#define BIT_CLEAR_RX_AFULL_TH_IDX(x) ((x) & (~BITS_RX_AFULL_TH_IDX)) +#define BIT_GET_RX_AFULL_TH_IDX(x) \ + (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX) & BIT_MASK_RX_AFULL_TH_IDX) +#define BIT_SET_RX_AFULL_TH_IDX(x, v) \ + (BIT_CLEAR_RX_AFULL_TH_IDX(x) | BIT_RX_AFULL_TH_IDX(v)) + +#define BIT_SHIFT_RX_HIGH_TH_IDX 16 +#define BIT_MASK_RX_HIGH_TH_IDX 0x7 +#define BIT_RX_HIGH_TH_IDX(x) \ + (((x) & BIT_MASK_RX_HIGH_TH_IDX) << BIT_SHIFT_RX_HIGH_TH_IDX) +#define BITS_RX_HIGH_TH_IDX \ + (BIT_MASK_RX_HIGH_TH_IDX << BIT_SHIFT_RX_HIGH_TH_IDX) +#define BIT_CLEAR_RX_HIGH_TH_IDX(x) ((x) & (~BITS_RX_HIGH_TH_IDX)) +#define BIT_GET_RX_HIGH_TH_IDX(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX) & BIT_MASK_RX_HIGH_TH_IDX) +#define BIT_SET_RX_HIGH_TH_IDX(x, v) \ + (BIT_CLEAR_RX_HIGH_TH_IDX(x) | BIT_RX_HIGH_TH_IDX(v)) + +#define BIT_SHIFT_RX_MED_TH_IDX 12 +#define BIT_MASK_RX_MED_TH_IDX 0x7 +#define BIT_RX_MED_TH_IDX(x) \ + (((x) & BIT_MASK_RX_MED_TH_IDX) << BIT_SHIFT_RX_MED_TH_IDX) +#define BITS_RX_MED_TH_IDX (BIT_MASK_RX_MED_TH_IDX << BIT_SHIFT_RX_MED_TH_IDX) +#define BIT_CLEAR_RX_MED_TH_IDX(x) ((x) & (~BITS_RX_MED_TH_IDX)) +#define BIT_GET_RX_MED_TH_IDX(x) \ + (((x) >> BIT_SHIFT_RX_MED_TH_IDX) & BIT_MASK_RX_MED_TH_IDX) +#define BIT_SET_RX_MED_TH_IDX(x, v) \ + (BIT_CLEAR_RX_MED_TH_IDX(x) | BIT_RX_MED_TH_IDX(v)) + +#define BIT_SHIFT_RX_LOW_TH_IDX 8 +#define BIT_MASK_RX_LOW_TH_IDX 0x7 +#define BIT_RX_LOW_TH_IDX(x) \ + (((x) & BIT_MASK_RX_LOW_TH_IDX) << BIT_SHIFT_RX_LOW_TH_IDX) +#define BITS_RX_LOW_TH_IDX (BIT_MASK_RX_LOW_TH_IDX << BIT_SHIFT_RX_LOW_TH_IDX) +#define BIT_CLEAR_RX_LOW_TH_IDX(x) ((x) & (~BITS_RX_LOW_TH_IDX)) +#define BIT_GET_RX_LOW_TH_IDX(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TH_IDX) & BIT_MASK_RX_LOW_TH_IDX) +#define BIT_SET_RX_LOW_TH_IDX(x, v) \ + (BIT_CLEAR_RX_LOW_TH_IDX(x) | BIT_RX_LOW_TH_IDX(v)) + +#define BIT_SHIFT_LTR_SPACE_IDX 4 +#define BIT_MASK_LTR_SPACE_IDX 0x3 +#define BIT_LTR_SPACE_IDX(x) \ + (((x) & BIT_MASK_LTR_SPACE_IDX) << BIT_SHIFT_LTR_SPACE_IDX) +#define BITS_LTR_SPACE_IDX (BIT_MASK_LTR_SPACE_IDX << BIT_SHIFT_LTR_SPACE_IDX) +#define BIT_CLEAR_LTR_SPACE_IDX(x) ((x) & (~BITS_LTR_SPACE_IDX)) +#define BIT_GET_LTR_SPACE_IDX(x) \ + (((x) >> BIT_SHIFT_LTR_SPACE_IDX) & BIT_MASK_LTR_SPACE_IDX) +#define BIT_SET_LTR_SPACE_IDX(x, v) \ + (BIT_CLEAR_LTR_SPACE_IDX(x) | BIT_LTR_SPACE_IDX(v)) + +#define BIT_SHIFT_LTR_IDLE_TIMER_IDX 0 +#define BIT_MASK_LTR_IDLE_TIMER_IDX 0x7 +#define BIT_LTR_IDLE_TIMER_IDX(x) \ + (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX) << BIT_SHIFT_LTR_IDLE_TIMER_IDX) +#define BITS_LTR_IDLE_TIMER_IDX \ + (BIT_MASK_LTR_IDLE_TIMER_IDX << BIT_SHIFT_LTR_IDLE_TIMER_IDX) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX(x) ((x) & (~BITS_LTR_IDLE_TIMER_IDX)) +#define BIT_GET_LTR_IDLE_TIMER_IDX(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX) & BIT_MASK_LTR_IDLE_TIMER_IDX) +#define BIT_SET_LTR_IDLE_TIMER_IDX(x, v) \ + (BIT_CLEAR_LTR_IDLE_TIMER_IDX(x) | BIT_LTR_IDLE_TIMER_IDX(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_LTR_IDLE_LATENCY_V1 (Offset 0x07A8) */ +#define BIT_SHIFT_LTR_IDLE_L 0 +#define BIT_MASK_LTR_IDLE_L 0xffffffffL +#define BIT_LTR_IDLE_L(x) (((x) & BIT_MASK_LTR_IDLE_L) << BIT_SHIFT_LTR_IDLE_L) +#define BITS_LTR_IDLE_L (BIT_MASK_LTR_IDLE_L << BIT_SHIFT_LTR_IDLE_L) +#define BIT_CLEAR_LTR_IDLE_L(x) ((x) & (~BITS_LTR_IDLE_L)) +#define BIT_GET_LTR_IDLE_L(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_L) & BIT_MASK_LTR_IDLE_L) +#define BIT_SET_LTR_IDLE_L(x, v) (BIT_CLEAR_LTR_IDLE_L(x) | BIT_LTR_IDLE_L(v)) -/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ +/* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */ -#define BIT_ISOLATION_EN BIT(0) +#define BIT_SHIFT_LTR_ACT_L 0 +#define BIT_MASK_LTR_ACT_L 0xffffffffL +#define BIT_LTR_ACT_L(x) (((x) & BIT_MASK_LTR_ACT_L) << BIT_SHIFT_LTR_ACT_L) +#define BITS_LTR_ACT_L (BIT_MASK_LTR_ACT_L << BIT_SHIFT_LTR_ACT_L) +#define BIT_CLEAR_LTR_ACT_L(x) ((x) & (~BITS_LTR_ACT_L)) +#define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L) +#define BIT_SET_LTR_ACT_L(x, v) (BIT_CLEAR_LTR_ACT_L(x) | BIT_LTR_ACT_L(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */ +#define BIT_SHIFT_ANT_ADDR2_1 0 +#define BIT_MASK_ANT_ADDR2_1 0xffffffffL +#define BIT_ANT_ADDR2_1(x) \ + (((x) & BIT_MASK_ANT_ADDR2_1) << BIT_SHIFT_ANT_ADDR2_1) +#define BITS_ANT_ADDR2_1 (BIT_MASK_ANT_ADDR2_1 << BIT_SHIFT_ANT_ADDR2_1) +#define BIT_CLEAR_ANT_ADDR2_1(x) ((x) & (~BITS_ANT_ADDR2_1)) +#define BIT_GET_ANT_ADDR2_1(x) \ + (((x) >> BIT_SHIFT_ANT_ADDR2_1) & BIT_MASK_ANT_ADDR2_1) +#define BIT_SET_ANT_ADDR2_1(x, v) \ + (BIT_CLEAR_ANT_ADDR2_1(x) | BIT_ANT_ADDR2_1(v)) -/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 (Offset 0x0788) */ +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ -#define BIT_SHIFT_ISOLATION_CHK_1 0 -#define BIT_MASK_ISOLATION_CHK_1 0xffffffffL -#define BIT_ISOLATION_CHK_1(x) (((x) & BIT_MASK_ISOLATION_CHK_1) << BIT_SHIFT_ISOLATION_CHK_1) -#define BIT_GET_ISOLATION_CHK_1(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_1) & BIT_MASK_ISOLATION_CHK_1) +#define BIT_APPEND_MACID_IN_RESP_EN BIT(50) +#define BIT_ADDR2_MATCH_EN BIT(49) +#define BIT_ANTTRN_EN BIT(48) +#define BIT_SHIFT_TRAIN_STA_ADDR 0 +#define BIT_MASK_TRAIN_STA_ADDR 0xffffffffffffL +#define BIT_TRAIN_STA_ADDR(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR) << BIT_SHIFT_TRAIN_STA_ADDR) +#define BITS_TRAIN_STA_ADDR \ + (BIT_MASK_TRAIN_STA_ADDR << BIT_SHIFT_TRAIN_STA_ADDR) +#define BIT_CLEAR_TRAIN_STA_ADDR(x) ((x) & (~BITS_TRAIN_STA_ADDR)) +#define BIT_GET_TRAIN_STA_ADDR(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR) & BIT_MASK_TRAIN_STA_ADDR) +#define BIT_SET_TRAIN_STA_ADDR(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR(x) | BIT_TRAIN_STA_ADDR(v)) -/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 (Offset 0x078C) */ +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_ISOLATION_CHK_2 0 -#define BIT_MASK_ISOLATION_CHK_2 0xffffff -#define BIT_ISOLATION_CHK_2(x) (((x) & BIT_MASK_ISOLATION_CHK_2) << BIT_SHIFT_ISOLATION_CHK_2) -#define BIT_GET_ISOLATION_CHK_2(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_2) & BIT_MASK_ISOLATION_CHK_2) +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ +#define BIT_SHIFT_TRAIN_STA_ADDR_0 0 +#define BIT_MASK_TRAIN_STA_ADDR_0 0xffffffffL +#define BIT_TRAIN_STA_ADDR_0(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_0) << BIT_SHIFT_TRAIN_STA_ADDR_0) +#define BITS_TRAIN_STA_ADDR_0 \ + (BIT_MASK_TRAIN_STA_ADDR_0 << BIT_SHIFT_TRAIN_STA_ADDR_0) +#define BIT_CLEAR_TRAIN_STA_ADDR_0(x) ((x) & (~BITS_TRAIN_STA_ADDR_0)) +#define BIT_GET_TRAIN_STA_ADDR_0(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0) & BIT_MASK_TRAIN_STA_ADDR_0) +#define BIT_SET_TRAIN_STA_ADDR_0(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_0(x) | BIT_TRAIN_STA_ADDR_0(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SMART_ANT_CTRL (Offset 0x07B4) */ +#define BIT_SHIFT_ANT_ADDR2_2 0 +#define BIT_MASK_ANT_ADDR2_2 0xffff +#define BIT_ANT_ADDR2_2(x) \ + (((x) & BIT_MASK_ANT_ADDR2_2) << BIT_SHIFT_ANT_ADDR2_2) +#define BITS_ANT_ADDR2_2 (BIT_MASK_ANT_ADDR2_2 << BIT_SHIFT_ANT_ADDR2_2) +#define BIT_CLEAR_ANT_ADDR2_2(x) ((x) & (~BITS_ANT_ADDR2_2)) +#define BIT_GET_ANT_ADDR2_2(x) \ + (((x) >> BIT_SHIFT_ANT_ADDR2_2) & BIT_MASK_ANT_ADDR2_2) +#define BIT_SET_ANT_ADDR2_2(x, v) \ + (BIT_CLEAR_ANT_ADDR2_2(x) | BIT_ANT_ADDR2_2(v)) -/* 2 REG_BT_INTERRUPT_STATUS_REGISTER (Offset 0x078F) */ +#endif -#define BIT_BT_HID_ISR BIT(7) -#define BIT_BT_QUERY_ISR BIT(6) -#define BIT_MAC_NULL_PKT_NOTIFY_ISR BIT(5) -#define BIT_WLAN_RPT_ISR BIT(4) -#define BIT_BT_POWER_ISR BIT(3) -#define BIT_BT_CHANNEL_ISR BIT(2) -#define BIT_BT_SLOT_CHANGE_ISR BIT(1) -#define BIT_BT_PROFILE_ISR BIT(0) +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BT_TDMA_TIME_REGISTER (Offset 0x0790) */ +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 (Offset 0x07B4) */ +#define BIT_SHIFT_TRAIN_STA_ADDR_1 0 +#define BIT_MASK_TRAIN_STA_ADDR_1 0xffff +#define BIT_TRAIN_STA_ADDR_1(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_1) << BIT_SHIFT_TRAIN_STA_ADDR_1) +#define BITS_TRAIN_STA_ADDR_1 \ + (BIT_MASK_TRAIN_STA_ADDR_1 << BIT_SHIFT_TRAIN_STA_ADDR_1) +#define BIT_CLEAR_TRAIN_STA_ADDR_1(x) ((x) & (~BITS_TRAIN_STA_ADDR_1)) +#define BIT_GET_TRAIN_STA_ADDR_1(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1) & BIT_MASK_TRAIN_STA_ADDR_1) +#define BIT_SET_TRAIN_STA_ADDR_1(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_1(x) | BIT_TRAIN_STA_ADDR_1(v)) -#define BIT_SHIFT_BT_TIME 6 -#define BIT_MASK_BT_TIME 0x3ffffff -#define BIT_BT_TIME(x) (((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME) -#define BIT_GET_BT_TIME(x) (((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BT_RPT_SAMPLE_RATE 0 -#define BIT_MASK_BT_RPT_SAMPLE_RATE 0x3f -#define BIT_BT_RPT_SAMPLE_RATE(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE) -#define BIT_GET_BT_RPT_SAMPLE_RATE(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE) +/* 2 REG_WMAC_PKTCNT_RWD (Offset 0x07B8) */ +#define BIT_SHIFT_PKTCNT_BSSIDMAP 4 +#define BIT_MASK_PKTCNT_BSSIDMAP 0xf +#define BIT_PKTCNT_BSSIDMAP(x) \ + (((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP) +#define BITS_PKTCNT_BSSIDMAP \ + (BIT_MASK_PKTCNT_BSSIDMAP << BIT_SHIFT_PKTCNT_BSSIDMAP) +#define BIT_CLEAR_PKTCNT_BSSIDMAP(x) ((x) & (~BITS_PKTCNT_BSSIDMAP)) +#define BIT_GET_PKTCNT_BSSIDMAP(x) \ + (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP) +#define BIT_SET_PKTCNT_BSSIDMAP(x, v) \ + (BIT_CLEAR_PKTCNT_BSSIDMAP(x) | BIT_PKTCNT_BSSIDMAP(v)) -/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ +#define BIT_PKTCNT_CNTRST BIT(1) +#define BIT_PKTCNT_CNTEN BIT(0) +#endif -#define BIT_SHIFT_BT_EISR_EN 16 -#define BIT_MASK_BT_EISR_EN 0xff -#define BIT_BT_EISR_EN(x) (((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN) -#define BIT_GET_BT_EISR_EN(x) (((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN) +#if (HALMAC_8814B_SUPPORT) -#define BIT_BT_ACT_FALLING_ISR BIT(10) -#define BIT_BT_ACT_RISING_ISR BIT(9) -#define BIT_TDMA_TO_ISR BIT(8) +/* 2 REG_CONTROL_FRAME_REPORT (Offset 0x07B8) */ -#define BIT_SHIFT_BT_CH 0 -#define BIT_MASK_BT_CH 0xff -#define BIT_BT_CH(x) (((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH) -#define BIT_GET_BT_CH(x) (((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH) +#define BIT_SHIFT_CONTROL_FRAME_REPORT 0 +#define BIT_MASK_CONTROL_FRAME_REPORT 0xffffffffL +#define BIT_CONTROL_FRAME_REPORT(x) \ + (((x) & BIT_MASK_CONTROL_FRAME_REPORT) \ + << BIT_SHIFT_CONTROL_FRAME_REPORT) +#define BITS_CONTROL_FRAME_REPORT \ + (BIT_MASK_CONTROL_FRAME_REPORT << BIT_SHIFT_CONTROL_FRAME_REPORT) +#define BIT_CLEAR_CONTROL_FRAME_REPORT(x) ((x) & (~BITS_CONTROL_FRAME_REPORT)) +#define BIT_GET_CONTROL_FRAME_REPORT(x) \ + (((x) >> BIT_SHIFT_CONTROL_FRAME_REPORT) & \ + BIT_MASK_CONTROL_FRAME_REPORT) +#define BIT_SET_CONTROL_FRAME_REPORT(x, v) \ + (BIT_CLEAR_CONTROL_FRAME_REPORT(x) | BIT_CONTROL_FRAME_REPORT(v)) +#endif -/* 2 REG_OBFF_CTRL_BASIC (Offset 0x0798) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_OBFF_EN_V1 BIT(31) +/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ -#define BIT_SHIFT_OBFF_STATE_V1 28 -#define BIT_MASK_OBFF_STATE_V1 0x3 -#define BIT_OBFF_STATE_V1(x) (((x) & BIT_MASK_OBFF_STATE_V1) << BIT_SHIFT_OBFF_STATE_V1) -#define BIT_GET_OBFF_STATE_V1(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1) & BIT_MASK_OBFF_STATE_V1) +#define BIT_WMAC_PKTCNT_TRST BIT(9) -#define BIT_OBFF_ACT_RXDMA_EN BIT(27) -#define BIT_OBFF_BLOCK_INT_EN BIT(26) -#define BIT_OBFF_AUTOACT_EN BIT(25) -#define BIT_OBFF_AUTOIDLE_EN BIT(24) +#endif -#define BIT_SHIFT_WAKE_MAX_PLS 20 -#define BIT_MASK_WAKE_MAX_PLS 0x7 -#define BIT_WAKE_MAX_PLS(x) (((x) & BIT_MASK_WAKE_MAX_PLS) << BIT_SHIFT_WAKE_MAX_PLS) -#define BIT_GET_WAKE_MAX_PLS(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS) & BIT_MASK_WAKE_MAX_PLS) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_CONTROL_FRAME_CNT_CTRL (Offset 0x07BC) */ -#define BIT_SHIFT_WAKE_MIN_PLS 16 -#define BIT_MASK_WAKE_MIN_PLS 0x7 -#define BIT_WAKE_MIN_PLS(x) (((x) & BIT_MASK_WAKE_MIN_PLS) << BIT_SHIFT_WAKE_MIN_PLS) -#define BIT_GET_WAKE_MIN_PLS(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS) & BIT_MASK_WAKE_MIN_PLS) +#define BIT_ALLCNTRST BIT(9) +#endif -#define BIT_SHIFT_WAKE_MAX_F2F 12 -#define BIT_MASK_WAKE_MAX_F2F 0x7 -#define BIT_WAKE_MAX_F2F(x) (((x) & BIT_MASK_WAKE_MAX_F2F) << BIT_SHIFT_WAKE_MAX_F2F) -#define BIT_GET_WAKE_MAX_F2F(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F) & BIT_MASK_WAKE_MAX_F2F) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ -#define BIT_SHIFT_WAKE_MIN_F2F 8 -#define BIT_MASK_WAKE_MIN_F2F 0x7 -#define BIT_WAKE_MIN_F2F(x) (((x) & BIT_MASK_WAKE_MIN_F2F) << BIT_SHIFT_WAKE_MIN_F2F) -#define BIT_GET_WAKE_MIN_F2F(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F) & BIT_MASK_WAKE_MIN_F2F) +#define BIT_WMAC_PKTCNT_FEN BIT(8) -#define BIT_APP_CPU_ACT_V1 BIT(3) -#define BIT_APP_OBFF_V1 BIT(2) -#define BIT_APP_IDLE_V1 BIT(1) -#define BIT_APP_INIT_V1 BIT(0) +#endif -/* 2 REG_OBFF_CTRL2_TIMER (Offset 0x079C) */ +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_CONTROL_FRAME_CNT_CTRL (Offset 0x07BC) */ -#define BIT_SHIFT_RX_HIGH_TIMER_IDX 24 -#define BIT_MASK_RX_HIGH_TIMER_IDX 0x7 -#define BIT_RX_HIGH_TIMER_IDX(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX) << BIT_SHIFT_RX_HIGH_TIMER_IDX) -#define BIT_GET_RX_HIGH_TIMER_IDX(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX) & BIT_MASK_RX_HIGH_TIMER_IDX) +#define BIT__ALLCNTEN BIT(8) +#define BIT_SHIFT_ADDR 4 +#define BIT_MASK_ADDR 0xf +#define BIT_ADDR(x) (((x) & BIT_MASK_ADDR) << BIT_SHIFT_ADDR) +#define BITS_ADDR (BIT_MASK_ADDR << BIT_SHIFT_ADDR) +#define BIT_CLEAR_ADDR(x) ((x) & (~BITS_ADDR)) +#define BIT_GET_ADDR(x) (((x) >> BIT_SHIFT_ADDR) & BIT_MASK_ADDR) +#define BIT_SET_ADDR(x, v) (BIT_CLEAR_ADDR(x) | BIT_ADDR(v)) -#define BIT_SHIFT_RX_MED_TIMER_IDX 16 -#define BIT_MASK_RX_MED_TIMER_IDX 0x7 -#define BIT_RX_MED_TIMER_IDX(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX) << BIT_SHIFT_RX_MED_TIMER_IDX) -#define BIT_GET_RX_MED_TIMER_IDX(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX) & BIT_MASK_RX_MED_TIMER_IDX) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RX_LOW_TIMER_IDX 8 -#define BIT_MASK_RX_LOW_TIMER_IDX 0x7 -#define BIT_RX_LOW_TIMER_IDX(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX) << BIT_SHIFT_RX_LOW_TIMER_IDX) -#define BIT_GET_RX_LOW_TIMER_IDX(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX) & BIT_MASK_RX_LOW_TIMER_IDX) +/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ +#define BIT_SHIFT_WMAC_PKTCNT_CFGAD 0 +#define BIT_MASK_WMAC_PKTCNT_CFGAD 0xff +#define BIT_WMAC_PKTCNT_CFGAD(x) \ + (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD) +#define BITS_WMAC_PKTCNT_CFGAD \ + (BIT_MASK_WMAC_PKTCNT_CFGAD << BIT_SHIFT_WMAC_PKTCNT_CFGAD) +#define BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) ((x) & (~BITS_WMAC_PKTCNT_CFGAD)) +#define BIT_GET_WMAC_PKTCNT_CFGAD(x) \ + (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD) +#define BIT_SET_WMAC_PKTCNT_CFGAD(x, v) \ + (BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) | BIT_WMAC_PKTCNT_CFGAD(v)) -#define BIT_SHIFT_OBFF_INT_TIMER_IDX 0 -#define BIT_MASK_OBFF_INT_TIMER_IDX 0x7 -#define BIT_OBFF_INT_TIMER_IDX(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX) << BIT_SHIFT_OBFF_INT_TIMER_IDX) -#define BIT_GET_OBFF_INT_TIMER_IDX(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX) & BIT_MASK_OBFF_INT_TIMER_IDX) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_LTR_CTRL_BASIC (Offset 0x07A0) */ +/* 2 REG_CONTROL_FRAME_CNT_CTRL (Offset 0x07BC) */ -#define BIT_LTR_EN_V1 BIT(31) -#define BIT_LTR_HW_EN_V1 BIT(30) -#define BIT_LRT_ACT_CTS_EN BIT(29) -#define BIT_LTR_ACT_RXPKT_EN BIT(28) -#define BIT_LTR_ACT_RXDMA_EN BIT(27) -#define BIT_LTR_IDLE_NO_SNOOP BIT(26) -#define BIT_SPDUP_MGTPKT BIT(25) -#define BIT_RX_AGG_EN BIT(24) -#define BIT_APP_LTR_ACT BIT(23) -#define BIT_APP_LTR_IDLE BIT(22) +#define BIT_SHIFT_CTRL_SEL 0 +#define BIT_MASK_CTRL_SEL 0xf +#define BIT_CTRL_SEL(x) (((x) & BIT_MASK_CTRL_SEL) << BIT_SHIFT_CTRL_SEL) +#define BITS_CTRL_SEL (BIT_MASK_CTRL_SEL << BIT_SHIFT_CTRL_SEL) +#define BIT_CLEAR_CTRL_SEL(x) ((x) & (~BITS_CTRL_SEL)) +#define BIT_GET_CTRL_SEL(x) (((x) >> BIT_SHIFT_CTRL_SEL) & BIT_MASK_CTRL_SEL) +#define BIT_SET_CTRL_SEL(x, v) (BIT_CLEAR_CTRL_SEL(x) | BIT_CTRL_SEL(v)) -#define BIT_SHIFT_HIGH_RATE_TRIG_SEL 20 -#define BIT_MASK_HIGH_RATE_TRIG_SEL 0x3 -#define BIT_HIGH_RATE_TRIG_SEL(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL) << BIT_SHIFT_HIGH_RATE_TRIG_SEL) -#define BIT_GET_HIGH_RATE_TRIG_SEL(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL) & BIT_MASK_HIGH_RATE_TRIG_SEL) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_MED_RATE_TRIG_SEL 18 -#define BIT_MASK_MED_RATE_TRIG_SEL 0x3 -#define BIT_MED_RATE_TRIG_SEL(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL) << BIT_SHIFT_MED_RATE_TRIG_SEL) -#define BIT_GET_MED_RATE_TRIG_SEL(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL) & BIT_MASK_MED_RATE_TRIG_SEL) +/* 2 REG_IQ_DUMP (Offset 0x07C0) */ +#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC (64 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_MATCH_REF_MAC 0xffffffffL +#define BIT_R_WMAC_MATCH_REF_MAC(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC) +#define BITS_R_WMAC_MATCH_REF_MAC \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC << BIT_SHIFT_R_WMAC_MATCH_REF_MAC) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC(x) ((x) & (~BITS_R_WMAC_MATCH_REF_MAC)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC) +#define BIT_SET_R_WMAC_MATCH_REF_MAC(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC(x) | BIT_R_WMAC_MATCH_REF_MAC(v)) + +#define BIT_SHIFT_R_WMAC_RX_FIL_LEN (64 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_RX_FIL_LEN 0xffff +#define BIT_R_WMAC_RX_FIL_LEN(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN) << BIT_SHIFT_R_WMAC_RX_FIL_LEN) +#define BITS_R_WMAC_RX_FIL_LEN \ + (BIT_MASK_R_WMAC_RX_FIL_LEN << BIT_SHIFT_R_WMAC_RX_FIL_LEN) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN(x) ((x) & (~BITS_R_WMAC_RX_FIL_LEN)) +#define BIT_GET_R_WMAC_RX_FIL_LEN(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN) & BIT_MASK_R_WMAC_RX_FIL_LEN) +#define BIT_SET_R_WMAC_RX_FIL_LEN(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN(x) | BIT_R_WMAC_RX_FIL_LEN(v)) + +#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH (56 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH 0xff +#define BIT_R_WMAC_RXFIFO_FULL_TH(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) +#define BITS_R_WMAC_RXFIFO_FULL_TH \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH(x) ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH(x) | BIT_R_WMAC_RXFIFO_FULL_TH(v)) + +#define BIT_R_WMAC_SRCH_TXRPT_TYPE BIT(51) +#define BIT_R_WMAC_NDP_RST BIT(50) +#define BIT_R_WMAC_POWINT_EN BIT(49) +#define BIT_R_WMAC_SRCH_TXRPT_PERPKT BIT(48) +#define BIT_R_WMAC_SRCH_TXRPT_MID BIT(47) +#define BIT_R_WMAC_PFIN_TOEN BIT(46) +#define BIT_R_WMAC_FIL_SECERR BIT(45) +#define BIT_R_WMAC_FIL_CTLPKTLEN BIT(44) +#define BIT_R_WMAC_FIL_FCTYPE BIT(43) +#define BIT_R_WMAC_FIL_FCPROVER BIT(42) +#define BIT_R_WMAC_PHYSTS_SNIF BIT(41) +#define BIT_R_WMAC_PHYSTS_PLCP BIT(40) +#define BIT_R_MAC_TCR_VBONF_RD BIT(39) +#define BIT_R_WMAC_TCR_MPAR_NDP BIT(38) +#define BIT_R_WMAC_NDP_FILTER BIT(37) +#define BIT_R_WMAC_RXLEN_SEL BIT(36) +#define BIT_R_WMAC_RXLEN_SEL1 BIT(35) +#define BIT_R_OFDM_FILTER BIT(34) +#define BIT_R_WMAC_CHK_OFDM_LEN BIT(33) + +#define BIT_SHIFT_R_WMAC_MASK_LA_MAC (32 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_MASK_LA_MAC 0xffffffffL +#define BIT_R_WMAC_MASK_LA_MAC(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC) << BIT_SHIFT_R_WMAC_MASK_LA_MAC) +#define BITS_R_WMAC_MASK_LA_MAC \ + (BIT_MASK_R_WMAC_MASK_LA_MAC << BIT_SHIFT_R_WMAC_MASK_LA_MAC) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC)) +#define BIT_GET_R_WMAC_MASK_LA_MAC(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC) & BIT_MASK_R_WMAC_MASK_LA_MAC) +#define BIT_SET_R_WMAC_MASK_LA_MAC(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC(x) | BIT_R_WMAC_MASK_LA_MAC(v)) + +#define BIT_R_WMAC_CHK_CCK_LEN BIT(32) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LOW_RATE_TRIG_SEL 16 -#define BIT_MASK_LOW_RATE_TRIG_SEL 0x3 -#define BIT_LOW_RATE_TRIG_SEL(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL) << BIT_SHIFT_LOW_RATE_TRIG_SEL) -#define BIT_GET_LOW_RATE_TRIG_SEL(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL) & BIT_MASK_LOW_RATE_TRIG_SEL) +/* 2 REG_IQ_DUMP (Offset 0x07C0) */ +#define BIT_SHIFT_DUMP_OK_ADDR 16 +#define BIT_MASK_DUMP_OK_ADDR 0xffff +#define BIT_DUMP_OK_ADDR(x) \ + (((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR) +#define BITS_DUMP_OK_ADDR (BIT_MASK_DUMP_OK_ADDR << BIT_SHIFT_DUMP_OK_ADDR) +#define BIT_CLEAR_DUMP_OK_ADDR(x) ((x) & (~BITS_DUMP_OK_ADDR)) +#define BIT_GET_DUMP_OK_ADDR(x) \ + (((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR) +#define BIT_SET_DUMP_OK_ADDR(x, v) \ + (BIT_CLEAR_DUMP_OK_ADDR(x) | BIT_DUMP_OK_ADDR(v)) -#define BIT_SHIFT_HIGH_RATE_BD_IDX 8 -#define BIT_MASK_HIGH_RATE_BD_IDX 0x7f -#define BIT_HIGH_RATE_BD_IDX(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX) << BIT_SHIFT_HIGH_RATE_BD_IDX) -#define BIT_GET_HIGH_RATE_BD_IDX(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX) & BIT_MASK_HIGH_RATE_BD_IDX) +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LOW_RATE_BD_IDX 0 -#define BIT_MASK_LOW_RATE_BD_IDX 0x7f -#define BIT_LOW_RATE_BD_IDX(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX) << BIT_SHIFT_LOW_RATE_BD_IDX) -#define BIT_GET_LOW_RATE_BD_IDX(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX) & BIT_MASK_LOW_RATE_BD_IDX) +/* 2 REG_IQ_DUMP (Offset 0x07C0) */ +#define BIT_MACDBG_TRIG_IQDUMP BIT(15) -/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD (Offset 0x07A4) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RX_EMPTY_TIMER_IDX 24 -#define BIT_MASK_RX_EMPTY_TIMER_IDX 0x7 -#define BIT_RX_EMPTY_TIMER_IDX(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX) << BIT_SHIFT_RX_EMPTY_TIMER_IDX) -#define BIT_GET_RX_EMPTY_TIMER_IDX(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX) & BIT_MASK_RX_EMPTY_TIMER_IDX) +/* 2 REG_IQ_DUMP (Offset 0x07C0) */ +#define BIT_SHIFT_R_TRIG_TIME_SEL 8 +#define BIT_MASK_R_TRIG_TIME_SEL 0x7f +#define BIT_R_TRIG_TIME_SEL(x) \ + (((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL) +#define BITS_R_TRIG_TIME_SEL \ + (BIT_MASK_R_TRIG_TIME_SEL << BIT_SHIFT_R_TRIG_TIME_SEL) +#define BIT_CLEAR_R_TRIG_TIME_SEL(x) ((x) & (~BITS_R_TRIG_TIME_SEL)) +#define BIT_GET_R_TRIG_TIME_SEL(x) \ + (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL) +#define BIT_SET_R_TRIG_TIME_SEL(x, v) \ + (BIT_CLEAR_R_TRIG_TIME_SEL(x) | BIT_R_TRIG_TIME_SEL(v)) + +#define BIT_SHIFT_R_MAC_TRIG_SEL 6 +#define BIT_MASK_R_MAC_TRIG_SEL 0x3 +#define BIT_R_MAC_TRIG_SEL(x) \ + (((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL) +#define BITS_R_MAC_TRIG_SEL \ + (BIT_MASK_R_MAC_TRIG_SEL << BIT_SHIFT_R_MAC_TRIG_SEL) +#define BIT_CLEAR_R_MAC_TRIG_SEL(x) ((x) & (~BITS_R_MAC_TRIG_SEL)) +#define BIT_GET_R_MAC_TRIG_SEL(x) \ + (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL) +#define BIT_SET_R_MAC_TRIG_SEL(x, v) \ + (BIT_CLEAR_R_MAC_TRIG_SEL(x) | BIT_R_MAC_TRIG_SEL(v)) + +#define BIT_MAC_TRIG_REG BIT(5) + +#define BIT_SHIFT_R_LEVEL_PULSE_SEL 3 +#define BIT_MASK_R_LEVEL_PULSE_SEL 0x3 +#define BIT_R_LEVEL_PULSE_SEL(x) \ + (((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL) +#define BITS_R_LEVEL_PULSE_SEL \ + (BIT_MASK_R_LEVEL_PULSE_SEL << BIT_SHIFT_R_LEVEL_PULSE_SEL) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL(x) ((x) & (~BITS_R_LEVEL_PULSE_SEL)) +#define BIT_GET_R_LEVEL_PULSE_SEL(x) \ + (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL) +#define BIT_SET_R_LEVEL_PULSE_SEL(x, v) \ + (BIT_CLEAR_R_LEVEL_PULSE_SEL(x) | BIT_R_LEVEL_PULSE_SEL(v)) + +#define BIT_EN_LA_MAC BIT(2) +#define BIT_R_EN_IQDUMP BIT(1) +#define BIT_R_IQDATA_DUMP BIT(0) + +#define BIT_SHIFT_R_CCK_LEN 0 +#define BIT_MASK_R_CCK_LEN 0xffff +#define BIT_R_CCK_LEN(x) (((x) & BIT_MASK_R_CCK_LEN) << BIT_SHIFT_R_CCK_LEN) +#define BITS_R_CCK_LEN (BIT_MASK_R_CCK_LEN << BIT_SHIFT_R_CCK_LEN) +#define BIT_CLEAR_R_CCK_LEN(x) ((x) & (~BITS_R_CCK_LEN)) +#define BIT_GET_R_CCK_LEN(x) (((x) >> BIT_SHIFT_R_CCK_LEN) & BIT_MASK_R_CCK_LEN) +#define BIT_SET_R_CCK_LEN(x, v) (BIT_CLEAR_R_CCK_LEN(x) | BIT_R_CCK_LEN(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RX_AFULL_TH_IDX 20 -#define BIT_MASK_RX_AFULL_TH_IDX 0x7 -#define BIT_RX_AFULL_TH_IDX(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX) << BIT_SHIFT_RX_AFULL_TH_IDX) -#define BIT_GET_RX_AFULL_TH_IDX(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX) & BIT_MASK_RX_AFULL_TH_IDX) +/* 2 REG_IQ_DUMP_1 (Offset 0x07C4) */ +#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1 0 +#define BIT_MASK_R_WMAC_MASK_LA_MAC_1 0xffffffffL +#define BIT_R_WMAC_MASK_LA_MAC_1(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1) \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) +#define BITS_R_WMAC_MASK_LA_MAC_1 \ + (BIT_MASK_R_WMAC_MASK_LA_MAC_1 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) & \ + BIT_MASK_R_WMAC_MASK_LA_MAC_1) +#define BIT_SET_R_WMAC_MASK_LA_MAC_1(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1(x) | BIT_R_WMAC_MASK_LA_MAC_1(v)) -#define BIT_SHIFT_RX_HIGH_TH_IDX 16 -#define BIT_MASK_RX_HIGH_TH_IDX 0x7 -#define BIT_RX_HIGH_TH_IDX(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX) << BIT_SHIFT_RX_HIGH_TH_IDX) -#define BIT_GET_RX_HIGH_TH_IDX(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX) & BIT_MASK_RX_HIGH_TH_IDX) +/* 2 REG_IQ_DUMP_2 (Offset 0x07C8) */ +#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2 0 +#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2 0xffffffffL +#define BIT_R_WMAC_MATCH_REF_MAC_2(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) +#define BITS_R_WMAC_MATCH_REF_MAC_2 \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC_2 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2(x) \ + ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_2(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC_2) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_2(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2(x) | BIT_R_WMAC_MATCH_REF_MAC_2(v)) -#define BIT_SHIFT_RX_MED_TH_IDX 12 -#define BIT_MASK_RX_MED_TH_IDX 0x7 -#define BIT_RX_MED_TH_IDX(x) (((x) & BIT_MASK_RX_MED_TH_IDX) << BIT_SHIFT_RX_MED_TH_IDX) -#define BIT_GET_RX_MED_TH_IDX(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX) & BIT_MASK_RX_MED_TH_IDX) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RX_LOW_TH_IDX 8 -#define BIT_MASK_RX_LOW_TH_IDX 0x7 -#define BIT_RX_LOW_TH_IDX(x) (((x) & BIT_MASK_RX_LOW_TH_IDX) << BIT_SHIFT_RX_LOW_TH_IDX) -#define BIT_GET_RX_LOW_TH_IDX(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX) & BIT_MASK_RX_LOW_TH_IDX) +/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ +#define BIT_RXFTM_TXACK_SC BIT(6) +#define BIT_RXFTM_TXACK_BW BIT(5) +#define BIT_RXFTM_EN BIT(3) +#define BIT_RXFTMREQ_BYDRV BIT(2) +#define BIT_RXFTMREQ_EN BIT(1) +#define BIT_FTM_EN BIT(0) -#define BIT_SHIFT_LTR_SPACE_IDX 4 -#define BIT_MASK_LTR_SPACE_IDX 0x3 -#define BIT_LTR_SPACE_IDX(x) (((x) & BIT_MASK_LTR_SPACE_IDX) << BIT_SHIFT_LTR_SPACE_IDX) -#define BIT_GET_LTR_SPACE_IDX(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX) & BIT_MASK_LTR_SPACE_IDX) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_LTR_IDLE_TIMER_IDX 0 -#define BIT_MASK_LTR_IDLE_TIMER_IDX 0x7 -#define BIT_LTR_IDLE_TIMER_IDX(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX) << BIT_SHIFT_LTR_IDLE_TIMER_IDX) -#define BIT_GET_LTR_IDLE_TIMER_IDX(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX) & BIT_MASK_LTR_IDLE_TIMER_IDX) +/* 2 REG_IQ_DUMP_EXT (Offset 0x07CF) */ +#define BIT_SHIFT_R_TIME_UNIT_SEL 0 +#define BIT_MASK_R_TIME_UNIT_SEL 0x7 +#define BIT_R_TIME_UNIT_SEL(x) \ + (((x) & BIT_MASK_R_TIME_UNIT_SEL) << BIT_SHIFT_R_TIME_UNIT_SEL) +#define BITS_R_TIME_UNIT_SEL \ + (BIT_MASK_R_TIME_UNIT_SEL << BIT_SHIFT_R_TIME_UNIT_SEL) +#define BIT_CLEAR_R_TIME_UNIT_SEL(x) ((x) & (~BITS_R_TIME_UNIT_SEL)) +#define BIT_GET_R_TIME_UNIT_SEL(x) \ + (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL) & BIT_MASK_R_TIME_UNIT_SEL) +#define BIT_SET_R_TIME_UNIT_SEL(x, v) \ + (BIT_CLEAR_R_TIME_UNIT_SEL(x) | BIT_R_TIME_UNIT_SEL(v)) -/* 2 REG_LTR_IDLE_LATENCY_V1 (Offset 0x07A8) */ +#endif +#if (HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_LTR_IDLE_L 0 -#define BIT_MASK_LTR_IDLE_L 0xffffffffL -#define BIT_LTR_IDLE_L(x) (((x) & BIT_MASK_LTR_IDLE_L) << BIT_SHIFT_LTR_IDLE_L) -#define BIT_GET_LTR_IDLE_L(x) (((x) >> BIT_SHIFT_LTR_IDLE_L) & BIT_MASK_LTR_IDLE_L) +/* 2 REG_OFDM_CCK_LEN_MASK (Offset 0x07D0) */ +#define BIT_MICICV_CLR BIT(86) +#define BIT_MPDU_RDY_SET BIT(85) +#define BIT_CLR_SEC_TYPE BIT(84) +#define BIT_NEWPKT_IN BIT(83) +#define BIT_FCS_END BIT(82) +#define BIT_DEL_MESH_TYPE BIT(81) +#define BIT_MASK_MESH_TYPE BIT(80) -/* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LTR_ACT_L 0 -#define BIT_MASK_LTR_ACT_L 0xffffffffL -#define BIT_LTR_ACT_L(x) (((x) & BIT_MASK_LTR_ACT_L) << BIT_SHIFT_LTR_ACT_L) -#define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L) +/* 2 REG_WMAC_OPTION_FUNCTION (Offset 0x07D0) */ +#define BIT_SHIFT_R_OFDM_LEN_V1 16 +#define BIT_MASK_R_OFDM_LEN_V1 0xffff +#define BIT_R_OFDM_LEN_V1(x) \ + (((x) & BIT_MASK_R_OFDM_LEN_V1) << BIT_SHIFT_R_OFDM_LEN_V1) +#define BITS_R_OFDM_LEN_V1 (BIT_MASK_R_OFDM_LEN_V1 << BIT_SHIFT_R_OFDM_LEN_V1) +#define BIT_CLEAR_R_OFDM_LEN_V1(x) ((x) & (~BITS_R_OFDM_LEN_V1)) +#define BIT_GET_R_OFDM_LEN_V1(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN_V1) & BIT_MASK_R_OFDM_LEN_V1) +#define BIT_SET_R_OFDM_LEN_V1(x, v) \ + (BIT_CLEAR_R_OFDM_LEN_V1(x) | BIT_R_OFDM_LEN_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ +/* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */ -#define BIT_APPEND_MACID_IN_RESP_EN BIT(50) -#define BIT_ADDR2_MATCH_EN BIT(49) -#define BIT_ANTTRN_EN BIT(48) +#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1 24 +#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 0xff +#define BIT_R_WMAC_RXFIFO_FULL_TH_1(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) +#define BITS_R_WMAC_RXFIFO_FULL_TH_1 \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x) \ + ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x) | BIT_R_WMAC_RXFIFO_FULL_TH_1(v)) + +#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1 BIT(23) +#define BIT_R_WMAC_RXRST_DLY_1 BIT(22) +#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1 BIT(21) +#define BIT_R_WMAC_SRCH_TXRPT_UA1_1 BIT(20) +#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1 BIT(19) +#define BIT_R_WMAC_NDP_RST_1 BIT(18) +#define BIT_R_WMAC_POWINT_EN_1 BIT(17) +#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1 BIT(16) +#define BIT_R_WMAC_SRCH_TXRPT_MID_1 BIT(15) +#define BIT_R_WMAC_PFIN_TOEN_1 BIT(14) +#define BIT_R_WMAC_FIL_SECERR_1 BIT(13) +#define BIT_R_WMAC_FIL_CTLPKTLEN_1 BIT(12) +#define BIT_R_WMAC_FIL_FCTYPE_1 BIT(11) +#define BIT_R_WMAC_FIL_FCPROVER_1 BIT(10) +#define BIT_R_WMAC_PHYSTS_SNIF_1 BIT(9) +#define BIT_R_WMAC_PHYSTS_PLCP_1 BIT(8) +#define BIT_R_MAC_TCR_VBONF_RD_1 BIT(7) +#define BIT_R_WMAC_TCR_MPAR_NDP_1 BIT(6) +#define BIT_R_WMAC_NDP_FILTER_1 BIT(5) +#define BIT_R_WMAC_RXLEN_SEL_1 BIT(4) +#define BIT_R_WMAC_RXLEN_SEL1_1 BIT(3) +#define BIT_R_OFDM_FILTER_1 BIT(2) +#define BIT_R_WMAC_CHK_OFDM_LEN_1 BIT(1) +#define BIT_R_WMAC_CHK_CCK_LEN_1 BIT(0) -#define BIT_SHIFT_TRAIN_STA_ADDR 0 -#define BIT_MASK_TRAIN_STA_ADDR 0xffffffffffffL -#define BIT_TRAIN_STA_ADDR(x) (((x) & BIT_MASK_TRAIN_STA_ADDR) << BIT_SHIFT_TRAIN_STA_ADDR) -#define BIT_GET_TRAIN_STA_ADDR(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR) & BIT_MASK_TRAIN_STA_ADDR) +/* 2 REG_WMAC_OPTION_FUNCTION_2 (Offset 0x07D8) */ +#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2 0 +#define BIT_MASK_R_WMAC_RX_FIL_LEN_2 0xffff +#define BIT_R_WMAC_RX_FIL_LEN_2(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) +#define BITS_R_WMAC_RX_FIL_LEN_2 \ + (BIT_MASK_R_WMAC_RX_FIL_LEN_2 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_2(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) +#define BIT_SET_R_WMAC_RX_FIL_LEN_2(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) | BIT_R_WMAC_RX_FIL_LEN_2(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_R_WMAC_RXHANG_EN BIT(15) -/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TRAIN_STA_ADDR_0 0 -#define BIT_MASK_TRAIN_STA_ADDR_0 0xffffffffL -#define BIT_TRAIN_STA_ADDR_0(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_0) << BIT_SHIFT_TRAIN_STA_ADDR_0) -#define BIT_GET_TRAIN_STA_ADDR_0(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0) & BIT_MASK_TRAIN_STA_ADDR_0) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_RXHANG_EN BIT(15) -/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 (Offset 0x07B4) */ +#endif -#define BIT_APPEND_MACID_IN_RESP_EN_1 BIT(18) -#define BIT_ADDR2_MATCH_EN_1 BIT(17) -#define BIT_ANTTRN_EN_1 BIT(16) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TRAIN_STA_ADDR_1 0 -#define BIT_MASK_TRAIN_STA_ADDR_1 0xffff -#define BIT_TRAIN_STA_ADDR_1(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_1) << BIT_SHIFT_TRAIN_STA_ADDR_1) -#define BIT_GET_TRAIN_STA_ADDR_1(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1) & BIT_MASK_TRAIN_STA_ADDR_1) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_R_WMAC_MHRDDY_LATCH BIT(14) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_R_MHRDDY_CLR BIT(13) -/* 2 REG_WMAC_PKTCNT_RWD (Offset 0x07B8) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PKTCNT_BSSIDMAP 4 -#define BIT_MASK_PKTCNT_BSSIDMAP 0xf -#define BIT_PKTCNT_BSSIDMAP(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP) -#define BIT_GET_PKTCNT_BSSIDMAP(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ -#define BIT_PKTCNT_CNTRST BIT(1) -#define BIT_PKTCNT_CNTEN BIT(0) +#define BIT_R_WMAC_MHRDDY_CLR BIT(13) -/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ +#endif -#define BIT_WMAC_PKTCNT_TRST BIT(9) -#define BIT_WMAC_PKTCNT_FEN BIT(8) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_PKTCNT_CFGAD 0 -#define BIT_MASK_WMAC_PKTCNT_CFGAD 0xff -#define BIT_WMAC_PKTCNT_CFGAD(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD) -#define BIT_GET_WMAC_PKTCNT_CFGAD(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1 BIT(12) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_IQ_DUMP (Offset 0x07C0) */ +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) -#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC (64 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_MATCH_REF_MAC 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC) -#define BIT_GET_R_WMAC_MATCH_REF_MAC(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC) & BIT_MASK_R_WMAC_MATCH_REF_MAC) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_RX_FIL_LEN (64 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_RX_FIL_LEN 0xffff -#define BIT_R_WMAC_RX_FIL_LEN(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN) << BIT_SHIFT_R_WMAC_RX_FIL_LEN) -#define BIT_GET_R_WMAC_RX_FIL_LEN(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN) & BIT_MASK_R_WMAC_RX_FIL_LEN) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) -#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH (56 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH) +#endif -#define BIT_R_WMAC_SRCH_TXRPT_TYPE BIT(51) -#define BIT_R_WMAC_NDP_RST BIT(50) -#define BIT_R_WMAC_POWINT_EN BIT(49) -#define BIT_R_WMAC_SRCH_TXRPT_PERPKT BIT(48) -#define BIT_R_WMAC_SRCH_TXRPT_MID BIT(47) -#define BIT_R_WMAC_PFIN_TOEN BIT(46) -#define BIT_R_WMAC_FIL_SECERR BIT(45) -#define BIT_R_WMAC_FIL_CTLPKTLEN BIT(44) -#define BIT_R_WMAC_FIL_FCTYPE BIT(43) -#define BIT_R_WMAC_FIL_FCPROVER BIT(42) -#define BIT_R_WMAC_PHYSTS_SNIF BIT(41) -#define BIT_R_WMAC_PHYSTS_PLCP BIT(40) -#define BIT_R_MAC_TCR_VBONF_RD BIT(39) -#define BIT_R_WMAC_TCR_MPAR_NDP BIT(38) -#define BIT_R_WMAC_NDP_FILTER BIT(37) -#define BIT_R_WMAC_RXLEN_SEL BIT(36) -#define BIT_R_WMAC_RXLEN_SEL1 BIT(35) -#define BIT_R_OFDM_FILTER BIT(34) -#define BIT_R_WMAC_CHK_OFDM_LEN BIT(33) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_MASK_LA_MAC (32 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_MASK_LA_MAC 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC) << BIT_SHIFT_R_WMAC_MASK_LA_MAC) -#define BIT_GET_R_WMAC_MASK_LA_MAC(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC) & BIT_MASK_R_WMAC_MASK_LA_MAC) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ -#define BIT_R_WMAC_CHK_CCK_LEN BIT(32) +#define BIT_R_CHK_DELIMIT_LEN BIT(10) +#define BIT_R_REAPTER_ADDR_MATCH BIT(9) +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8) +#define BIT_R_LATCH_MACHRDY BIT(7) +#define BIT_R_WMAC_RXFIL_REND BIT(6) +#define BIT_R_WMAC_MPDURDY_CLR BIT(5) +#define BIT_R_WMAC_CLRRXSEC BIT(4) +#define BIT_R_WMAC_RXFIL_RDEL BIT(3) +#define BIT_R_WMAC_RXFIL_FCSE BIT(2) +#define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1) +#define BIT_R_WMAC_RXFIL_MASKM BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_NDP_SIG (Offset 0x07E0) */ -/* 2 REG_IQ_DUMP (Offset 0x07C0) */ +#define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0 +#define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff +#define BIT_R_WMAC_TXNDP_SIGB(x) \ + (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB) +#define BITS_R_WMAC_TXNDP_SIGB \ + (BIT_MASK_R_WMAC_TXNDP_SIGB << BIT_SHIFT_R_WMAC_TXNDP_SIGB) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) ((x) & (~BITS_R_WMAC_TXNDP_SIGB)) +#define BIT_GET_R_WMAC_TXNDP_SIGB(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB) +#define BIT_SET_R_WMAC_TXNDP_SIGB(x, v) \ + (BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) | BIT_R_WMAC_TXNDP_SIGB(v)) +#endif -#define BIT_SHIFT_R_OFDM_LEN 26 -#define BIT_MASK_R_OFDM_LEN 0x3f -#define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN) -#define BIT_GET_R_OFDM_LEN(x) (((x) >> BIT_SHIFT_R_OFDM_LEN) & BIT_MASK_R_OFDM_LEN) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ -#define BIT_SHIFT_DUMP_OK_ADDR 15 -#define BIT_MASK_DUMP_OK_ADDR 0x1ffff -#define BIT_DUMP_OK_ADDR(x) (((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR) -#define BIT_GET_DUMP_OK_ADDR(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR) +#define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH) +#define BIT_MASK_R_MAC_DEBUG 0xffffffffL +#define BIT_R_MAC_DEBUG(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG) +#define BITS_R_MAC_DEBUG (BIT_MASK_R_MAC_DEBUG << BIT_SHIFT_R_MAC_DEBUG) +#define BIT_CLEAR_R_MAC_DEBUG(x) ((x) & (~BITS_R_MAC_DEBUG)) +#define BIT_GET_R_MAC_DEBUG(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG) +#define BIT_SET_R_MAC_DEBUG(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG(x) | BIT_R_MAC_DEBUG(v)) +#endif -#define BIT_SHIFT_R_TRIG_TIME_SEL 8 -#define BIT_MASK_R_TRIG_TIME_SEL 0x7f -#define BIT_R_TRIG_TIME_SEL(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL) -#define BIT_GET_R_TRIG_TIME_SEL(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ -#define BIT_SHIFT_R_MAC_TRIG_SEL 6 -#define BIT_MASK_R_MAC_TRIG_SEL 0x3 -#define BIT_R_MAC_TRIG_SEL(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL) -#define BIT_GET_R_MAC_TRIG_SEL(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL) +#define BIT_SHIFT_R_MAC_DBG_SHIFT 8 +#define BIT_MASK_R_MAC_DBG_SHIFT 0x7 +#define BIT_R_MAC_DBG_SHIFT(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT) +#define BITS_R_MAC_DBG_SHIFT \ + (BIT_MASK_R_MAC_DBG_SHIFT << BIT_SHIFT_R_MAC_DBG_SHIFT) +#define BIT_CLEAR_R_MAC_DBG_SHIFT(x) ((x) & (~BITS_R_MAC_DBG_SHIFT)) +#define BIT_GET_R_MAC_DBG_SHIFT(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT) & BIT_MASK_R_MAC_DBG_SHIFT) +#define BIT_SET_R_MAC_DBG_SHIFT(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SHIFT(x) | BIT_R_MAC_DBG_SHIFT(v)) -#define BIT_MAC_TRIG_REG BIT(5) +#define BIT_SHIFT_R_MAC_DBG_SEL 0 +#define BIT_MASK_R_MAC_DBG_SEL 0x3 +#define BIT_R_MAC_DBG_SEL(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SEL) << BIT_SHIFT_R_MAC_DBG_SEL) +#define BITS_R_MAC_DBG_SEL (BIT_MASK_R_MAC_DBG_SEL << BIT_SHIFT_R_MAC_DBG_SEL) +#define BIT_CLEAR_R_MAC_DBG_SEL(x) ((x) & (~BITS_R_MAC_DBG_SEL)) +#define BIT_GET_R_MAC_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SEL) & BIT_MASK_R_MAC_DBG_SEL) +#define BIT_SET_R_MAC_DBG_SEL(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SEL(x) | BIT_R_MAC_DBG_SEL(v)) -#define BIT_SHIFT_R_LEVEL_PULSE_SEL 3 -#define BIT_MASK_R_LEVEL_PULSE_SEL 0x3 -#define BIT_R_LEVEL_PULSE_SEL(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL) -#define BIT_GET_R_LEVEL_PULSE_SEL(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL) +#endif -#define BIT_EN_LA_MAC BIT(2) -#define BIT_R_EN_IQDUMP BIT(1) -#define BIT_R_IQDATA_DUMP BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_R_CCK_LEN 0 -#define BIT_MASK_R_CCK_LEN 0xffff -#define BIT_R_CCK_LEN(x) (((x) & BIT_MASK_R_CCK_LEN) << BIT_SHIFT_R_CCK_LEN) -#define BIT_GET_R_CCK_LEN(x) (((x) >> BIT_SHIFT_R_CCK_LEN) & BIT_MASK_R_CCK_LEN) +/* 2 REG_SEC_OPT (Offset 0x07E8) */ +#define BIT_MASK_IV BIT(18) +#define BIT_EIVL_ENDIAN BIT(17) +#define BIT_EIVH_ENDIAN BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_SEC_OPT (Offset 0x07E8) */ +#define BIT_SHIFT_BT_TIME_CNT 0 +#define BIT_MASK_BT_TIME_CNT 0xff +#define BIT_BT_TIME_CNT(x) \ + (((x) & BIT_MASK_BT_TIME_CNT) << BIT_SHIFT_BT_TIME_CNT) +#define BITS_BT_TIME_CNT (BIT_MASK_BT_TIME_CNT << BIT_SHIFT_BT_TIME_CNT) +#define BIT_CLEAR_BT_TIME_CNT(x) ((x) & (~BITS_BT_TIME_CNT)) +#define BIT_GET_BT_TIME_CNT(x) \ + (((x) >> BIT_SHIFT_BT_TIME_CNT) & BIT_MASK_BT_TIME_CNT) +#define BIT_SET_BT_TIME_CNT(x, v) \ + (BIT_CLEAR_BT_TIME_CNT(x) | BIT_BT_TIME_CNT(v)) -/* 2 REG_IQ_DUMP_1 (Offset 0x07C4) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1 0 -#define BIT_MASK_R_WMAC_MASK_LA_MAC_1 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC_1(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) -#define BIT_GET_R_WMAC_MASK_LA_MAC_1(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) & BIT_MASK_R_WMAC_MASK_LA_MAC_1) +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1 (Offset 0x07E8) */ +#define BIT_SHIFT_R_MAC_DEBUG_1 0 +#define BIT_MASK_R_MAC_DEBUG_1 0xffffffffL +#define BIT_R_MAC_DEBUG_1(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG_1) << BIT_SHIFT_R_MAC_DEBUG_1) +#define BITS_R_MAC_DEBUG_1 (BIT_MASK_R_MAC_DEBUG_1 << BIT_SHIFT_R_MAC_DEBUG_1) +#define BIT_CLEAR_R_MAC_DEBUG_1(x) ((x) & (~BITS_R_MAC_DEBUG_1)) +#define BIT_GET_R_MAC_DEBUG_1(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG_1) & BIT_MASK_R_MAC_DEBUG_1) +#define BIT_SET_R_MAC_DEBUG_1(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG_1(x) | BIT_R_MAC_DEBUG_1(v)) -/* 2 REG_IQ_DUMP_2 (Offset 0x07C8) */ +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2 0 -#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC_2(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) -#define BIT_GET_R_WMAC_MATCH_REF_MAC_2(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2) +/* 2 REG_WSEC_OPTION (Offset 0x07EC) */ +#define BIT_RXDEC_BM_MGNT BIT(22) +#define BIT_TXENC_BM_MGNT BIT(21) +#define BIT_RXDEC_UNI_MGNT BIT(20) +#define BIT_TXENC_UNI_MGNT BIT(19) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_WSEC_OPTION (Offset 0x07EC) */ -/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ +#define BIT_WMAC_SEC_MASKIV BIT(18) -#define BIT_RXFTM_TXACK_SC BIT(6) -#define BIT_RXFTM_TXACK_BW BIT(5) -#define BIT_RXFTM_EN BIT(3) -#define BIT_RXFTMREQ_BYDRV BIT(2) -#define BIT_RXFTMREQ_EN BIT(1) -#define BIT_FTM_EN BIT(0) +#define BIT_SHIFT_WMAC_SEC_PN_SEL 16 +#define BIT_MASK_WMAC_SEC_PN_SEL 0x3 +#define BIT_WMAC_SEC_PN_SEL(x) \ + (((x) & BIT_MASK_WMAC_SEC_PN_SEL) << BIT_SHIFT_WMAC_SEC_PN_SEL) +#define BITS_WMAC_SEC_PN_SEL \ + (BIT_MASK_WMAC_SEC_PN_SEL << BIT_SHIFT_WMAC_SEC_PN_SEL) +#define BIT_CLEAR_WMAC_SEC_PN_SEL(x) ((x) & (~BITS_WMAC_SEC_PN_SEL)) +#define BIT_GET_WMAC_SEC_PN_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_SEC_PN_SEL) & BIT_MASK_WMAC_SEC_PN_SEL) +#define BIT_SET_WMAC_SEC_PN_SEL(x, v) \ + (BIT_CLEAR_WMAC_SEC_PN_SEL(x) | BIT_WMAC_SEC_PN_SEL(v)) #endif +#if (HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_RTS_ADDR0 (Offset 0x07F0) */ +#define BIT_SHIFT_RTS_ADDR0 0 +#define BIT_MASK_RTS_ADDR0 0xffffffffffffL +#define BIT_RTS_ADDR0(x) (((x) & BIT_MASK_RTS_ADDR0) << BIT_SHIFT_RTS_ADDR0) +#define BITS_RTS_ADDR0 (BIT_MASK_RTS_ADDR0 << BIT_SHIFT_RTS_ADDR0) +#define BIT_CLEAR_RTS_ADDR0(x) ((x) & (~BITS_RTS_ADDR0)) +#define BIT_GET_RTS_ADDR0(x) (((x) >> BIT_SHIFT_RTS_ADDR0) & BIT_MASK_RTS_ADDR0) +#define BIT_SET_RTS_ADDR0(x, v) (BIT_CLEAR_RTS_ADDR0(x) | BIT_RTS_ADDR0(v)) -/* 2 REG_IQ_DUMP_EXT (Offset 0x07CF) */ +/* 2 REG_RTS_ADDR1 (Offset 0x07F8) */ +#define BIT_SHIFT_RTS_ADDR1 0 +#define BIT_MASK_RTS_ADDR1 0xffffffffffffL +#define BIT_RTS_ADDR1(x) (((x) & BIT_MASK_RTS_ADDR1) << BIT_SHIFT_RTS_ADDR1) +#define BITS_RTS_ADDR1 (BIT_MASK_RTS_ADDR1 << BIT_SHIFT_RTS_ADDR1) +#define BIT_CLEAR_RTS_ADDR1(x) ((x) & (~BITS_RTS_ADDR1)) +#define BIT_GET_RTS_ADDR1(x) (((x) >> BIT_SHIFT_RTS_ADDR1) & BIT_MASK_RTS_ADDR1) +#define BIT_SET_RTS_ADDR1(x, v) (BIT_CLEAR_RTS_ADDR1(x) | BIT_RTS_ADDR1(v)) -#define BIT_SHIFT_R_TIME_UNIT_SEL 0 -#define BIT_MASK_R_TIME_UNIT_SEL 0x7 -#define BIT_R_TIME_UNIT_SEL(x) (((x) & BIT_MASK_R_TIME_UNIT_SEL) << BIT_SHIFT_R_TIME_UNIT_SEL) -#define BIT_GET_R_TIME_UNIT_SEL(x) (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL) & BIT_MASK_R_TIME_UNIT_SEL) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG__RPFM_MAP1 (Offset 0x07FE) */ +#define BIT_DATA_RPFM15EN BIT(15) +#define BIT_DATA_RPFM14EN BIT(14) +#define BIT_DATA_RPFM13EN BIT(13) +#define BIT_DATA_RPFM12EN BIT(12) +#define BIT_DATA_RPFM11EN BIT(11) +#define BIT_DATA_RPFM10EN BIT(10) +#define BIT_DATA_RPFM9EN BIT(9) +#define BIT_DATA_RPFM8EN BIT(8) +#define BIT_DATA_RPFM7EN BIT(7) +#define BIT_DATA_RPFM6EN BIT(6) +#define BIT_DATA_RPFM5EN BIT(5) +#define BIT_DATA_RPFM4EN BIT(4) +#define BIT_DATA_RPFM3EN BIT(3) +#define BIT_DATA_RPFM2EN BIT(2) +#define BIT_DATA_RPFM1EN BIT(1) +#define BIT_DATA_RPFM0EN BIT(0) -#if (HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_OFDM_CCK_LEN_MASK (Offset 0x07D0) */ +/* 2 REG_SYS_CFG3 (Offset 0x1000) */ -#define BIT_MICICV_CLR BIT(86) -#define BIT_MPDU_RDY_SET BIT(85) -#define BIT_CLR_SEC_TYPE BIT(84) -#define BIT_NEWPKT_IN BIT(83) -#define BIT_FCS_END BIT(82) -#define BIT_DEL_MESH_TYPE BIT(81) -#define BIT_MASK_MESH_TYPE BIT(80) +#define BIT_FEN_BB_GLB_RSTN_V1 BIT(17) +#define BIT_FEN_BBRSTB_V1 BIT(16) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +#define BIT_PWC_MA33V BIT(15) -/* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SYS_CFG3 (Offset 0x1000) */ -#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1 24 -#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH_1(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) - -#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1 BIT(23) -#define BIT_R_WMAC_RXRST_DLY_1 BIT(22) -#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1 BIT(21) -#define BIT_R_WMAC_SRCH_TXRPT_UA1_1 BIT(20) -#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1 BIT(19) -#define BIT_R_WMAC_NDP_RST_1 BIT(18) -#define BIT_R_WMAC_POWINT_EN_1 BIT(17) -#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1 BIT(16) -#define BIT_R_WMAC_SRCH_TXRPT_MID_1 BIT(15) -#define BIT_R_WMAC_PFIN_TOEN_1 BIT(14) -#define BIT_R_WMAC_FIL_SECERR_1 BIT(13) -#define BIT_R_WMAC_FIL_CTLPKTLEN_1 BIT(12) -#define BIT_R_WMAC_FIL_FCTYPE_1 BIT(11) -#define BIT_R_WMAC_FIL_FCPROVER_1 BIT(10) -#define BIT_R_WMAC_PHYSTS_SNIF_1 BIT(9) -#define BIT_R_WMAC_PHYSTS_PLCP_1 BIT(8) -#define BIT_R_MAC_TCR_VBONF_RD_1 BIT(7) -#define BIT_R_WMAC_TCR_MPAR_NDP_1 BIT(6) -#define BIT_R_WMAC_NDP_FILTER_1 BIT(5) -#define BIT_R_WMAC_RXLEN_SEL_1 BIT(4) -#define BIT_R_WMAC_RXLEN_SEL1_1 BIT(3) -#define BIT_R_OFDM_FILTER_1 BIT(2) -#define BIT_R_WMAC_CHK_OFDM_LEN_1 BIT(1) -#define BIT_R_WMAC_CHK_CCK_LEN_1 BIT(0) +#define BIT_PWC_EV25V_1 BIT(14) -/* 2 REG_WMAC_OPTION_FUNCTION_2 (Offset 0x07D8) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2 0 -#define BIT_MASK_R_WMAC_RX_FIL_LEN_2 0xffff -#define BIT_R_WMAC_RX_FIL_LEN_2(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) -#define BIT_GET_R_WMAC_RX_FIL_LEN_2(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) +/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +#define BIT_PWC_MA12V BIT(14) +#define BIT_PWC_MD12V BIT(13) +#define BIT_PWC_PD12V BIT(12) +#define BIT_PWC_UD12V BIT(11) +#define BIT_ISO_MA2MD BIT(1) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_OCP_L_0 BIT(31) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#endif -#define BIT_R_WMAC_RXHANG_EN BIT(15) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_OCP_L BIT(31) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_R_WMAC_MHRDDY_LATCH BIT(14) +#define BIT_POWOCP_L BIT(30) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_CF_L_1_0 28 +#define BIT_MASK_CF_L_1_0 0x3 +#define BIT_CF_L_1_0(x) (((x) & BIT_MASK_CF_L_1_0) << BIT_SHIFT_CF_L_1_0) +#define BITS_CF_L_1_0 (BIT_MASK_CF_L_1_0 << BIT_SHIFT_CF_L_1_0) +#define BIT_CLEAR_CF_L_1_0(x) ((x) & (~BITS_CF_L_1_0)) +#define BIT_GET_CF_L_1_0(x) (((x) >> BIT_SHIFT_CF_L_1_0) & BIT_MASK_CF_L_1_0) +#define BIT_SET_CF_L_1_0(x, v) (BIT_CLEAR_CF_L_1_0(x) | BIT_CF_L_1_0(v)) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#endif -#define BIT_R_MHRDDY_CLR BIT(13) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_CF_L_V2 28 +#define BIT_MASK_CF_L_V2 0x3 +#define BIT_CF_L_V2(x) (((x) & BIT_MASK_CF_L_V2) << BIT_SHIFT_CF_L_V2) +#define BITS_CF_L_V2 (BIT_MASK_CF_L_V2 << BIT_SHIFT_CF_L_V2) +#define BIT_CLEAR_CF_L_V2(x) ((x) & (~BITS_CF_L_V2)) +#define BIT_GET_CF_L_V2(x) (((x) >> BIT_SHIFT_CF_L_V2) & BIT_MASK_CF_L_V2) +#define BIT_SET_CF_L_V2(x, v) (BIT_CLEAR_CF_L_V2(x) | BIT_CF_L_V2(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_R_WMAC_MHRDDY_CLR BIT(13) +#define BIT_SHIFT_CFC_L_1_0 26 +#define BIT_MASK_CFC_L_1_0 0x3 +#define BIT_CFC_L_1_0(x) (((x) & BIT_MASK_CFC_L_1_0) << BIT_SHIFT_CFC_L_1_0) +#define BITS_CFC_L_1_0 (BIT_MASK_CFC_L_1_0 << BIT_SHIFT_CFC_L_1_0) +#define BIT_CLEAR_CFC_L_1_0(x) ((x) & (~BITS_CFC_L_1_0)) +#define BIT_GET_CFC_L_1_0(x) (((x) >> BIT_SHIFT_CFC_L_1_0) & BIT_MASK_CFC_L_1_0) +#define BIT_SET_CFC_L_1_0(x, v) (BIT_CLEAR_CFC_L_1_0(x) | BIT_CFC_L_1_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_CFC_L_V2 26 +#define BIT_MASK_CFC_L_V2 0x3 +#define BIT_CFC_L_V2(x) (((x) & BIT_MASK_CFC_L_V2) << BIT_SHIFT_CFC_L_V2) +#define BITS_CFC_L_V2 (BIT_MASK_CFC_L_V2 << BIT_SHIFT_CFC_L_V2) +#define BIT_CLEAR_CFC_L_V2(x) ((x) & (~BITS_CFC_L_V2)) +#define BIT_GET_CFC_L_V2(x) (((x) >> BIT_SHIFT_CFC_L_V2) & BIT_MASK_CFC_L_V2) +#define BIT_SET_CFC_L_V2(x, v) (BIT_CLEAR_CFC_L_V2(x) | BIT_CFC_L_V2(v)) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#endif -#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1 BIT(12) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_R3_L_1_0 24 +#define BIT_MASK_R3_L_1_0 0x3 +#define BIT_R3_L_1_0(x) (((x) & BIT_MASK_R3_L_1_0) << BIT_SHIFT_R3_L_1_0) +#define BITS_R3_L_1_0 (BIT_MASK_R3_L_1_0 << BIT_SHIFT_R3_L_1_0) +#define BIT_CLEAR_R3_L_1_0(x) ((x) & (~BITS_R3_L_1_0)) +#define BIT_GET_R3_L_1_0(x) (((x) >> BIT_SHIFT_R3_L_1_0) & BIT_MASK_R3_L_1_0) +#define BIT_SET_R3_L_1_0(x, v) (BIT_CLEAR_R3_L_1_0(x) | BIT_R3_L_1_0(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) +#define BIT_SHIFT_R3_L_V2 24 +#define BIT_MASK_R3_L_V2 0x3 +#define BIT_R3_L_V2(x) (((x) & BIT_MASK_R3_L_V2) << BIT_SHIFT_R3_L_V2) +#define BITS_R3_L_V2 (BIT_MASK_R3_L_V2 << BIT_SHIFT_R3_L_V2) +#define BIT_CLEAR_R3_L_V2(x) ((x) & (~BITS_R3_L_V2)) +#define BIT_GET_R3_L_V2(x) (((x) >> BIT_SHIFT_R3_L_V2) & BIT_MASK_R3_L_V2) +#define BIT_SET_R3_L_V2(x, v) (BIT_CLEAR_R3_L_V2(x) | BIT_R3_L_V2(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_R2_L_1_0 22 +#define BIT_MASK_R2_L_1_0 0x3 +#define BIT_R2_L_1_0(x) (((x) & BIT_MASK_R2_L_1_0) << BIT_SHIFT_R2_L_1_0) +#define BITS_R2_L_1_0 (BIT_MASK_R2_L_1_0 << BIT_SHIFT_R2_L_1_0) +#define BIT_CLEAR_R2_L_1_0(x) ((x) & (~BITS_R2_L_1_0)) +#define BIT_GET_R2_L_1_0(x) (((x) >> BIT_SHIFT_R2_L_1_0) & BIT_MASK_R2_L_1_0) +#define BIT_SET_R2_L_1_0(x, v) (BIT_CLEAR_R2_L_1_0(x) | BIT_R2_L_1_0(v)) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#endif -#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_R2_L 22 +#define BIT_MASK_R2_L 0x3 +#define BIT_R2_L(x) (((x) & BIT_MASK_R2_L) << BIT_SHIFT_R2_L) +#define BITS_R2_L (BIT_MASK_R2_L << BIT_SHIFT_R2_L) +#define BIT_CLEAR_R2_L(x) ((x) & (~BITS_R2_L)) +#define BIT_GET_R2_L(x) (((x) >> BIT_SHIFT_R2_L) & BIT_MASK_R2_L) +#define BIT_SET_R2_L(x, v) (BIT_CLEAR_R2_L(x) | BIT_R2_L(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_R_CHK_DELIMIT_LEN BIT(10) -#define BIT_R_REAPTER_ADDR_MATCH BIT(9) -#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8) -#define BIT_R_LATCH_MACHRDY BIT(7) -#define BIT_R_WMAC_RXFIL_REND BIT(6) -#define BIT_R_WMAC_MPDURDY_CLR BIT(5) -#define BIT_R_WMAC_CLRRXSEC BIT(4) -#define BIT_R_WMAC_RXFIL_RDEL BIT(3) -#define BIT_R_WMAC_RXFIL_FCSE BIT(2) -#define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1) -#define BIT_R_WMAC_RXFIL_MASKM BIT(0) +#define BIT_SHIFT_R1_L_1_0 20 +#define BIT_MASK_R1_L_1_0 0x3 +#define BIT_R1_L_1_0(x) (((x) & BIT_MASK_R1_L_1_0) << BIT_SHIFT_R1_L_1_0) +#define BITS_R1_L_1_0 (BIT_MASK_R1_L_1_0 << BIT_SHIFT_R1_L_1_0) +#define BIT_CLEAR_R1_L_1_0(x) ((x) & (~BITS_R1_L_1_0)) +#define BIT_GET_R1_L_1_0(x) (((x) >> BIT_SHIFT_R1_L_1_0) & BIT_MASK_R1_L_1_0) +#define BIT_SET_R1_L_1_0(x, v) (BIT_CLEAR_R1_L_1_0(x) | BIT_R1_L_1_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_R1_L 20 +#define BIT_MASK_R1_L 0x3 +#define BIT_R1_L(x) (((x) & BIT_MASK_R1_L) << BIT_SHIFT_R1_L) +#define BITS_R1_L (BIT_MASK_R1_L << BIT_SHIFT_R1_L) +#define BIT_CLEAR_R1_L(x) ((x) & (~BITS_R1_L)) +#define BIT_GET_R1_L(x) (((x) >> BIT_SHIFT_R1_L) & BIT_MASK_R1_L) +#define BIT_SET_R1_L(x, v) (BIT_CLEAR_R1_L(x) | BIT_R1_L(v)) -/* 2 REG_NDP_SIG (Offset 0x07E0) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0 -#define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff -#define BIT_R_WMAC_TXNDP_SIGB(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB) -#define BIT_GET_R_WMAC_TXNDP_SIGB(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_C3_L_1_0 18 +#define BIT_MASK_C3_L_1_0 0x3 +#define BIT_C3_L_1_0(x) (((x) & BIT_MASK_C3_L_1_0) << BIT_SHIFT_C3_L_1_0) +#define BITS_C3_L_1_0 (BIT_MASK_C3_L_1_0 << BIT_SHIFT_C3_L_1_0) +#define BIT_CLEAR_C3_L_1_0(x) ((x) & (~BITS_C3_L_1_0)) +#define BIT_GET_C3_L_1_0(x) (((x) >> BIT_SHIFT_C3_L_1_0) & BIT_MASK_C3_L_1_0) +#define BIT_SET_C3_L_1_0(x, v) (BIT_CLEAR_C3_L_1_0(x) | BIT_C3_L_1_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_C3_L 18 +#define BIT_MASK_C3_L 0x3 +#define BIT_C3_L(x) (((x) & BIT_MASK_C3_L) << BIT_SHIFT_C3_L) +#define BITS_C3_L (BIT_MASK_C3_L << BIT_SHIFT_C3_L) +#define BIT_CLEAR_C3_L(x) ((x) & (~BITS_C3_L)) +#define BIT_GET_C3_L(x) (((x) >> BIT_SHIFT_C3_L) & BIT_MASK_C3_L) +#define BIT_SET_C3_L(x, v) (BIT_CLEAR_C3_L(x) | BIT_C3_L(v)) -/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH) -#define BIT_MASK_R_MAC_DEBUG 0xffffffffL -#define BIT_R_MAC_DEBUG(x) (((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG) -#define BIT_GET_R_MAC_DEBUG(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_C2_L_1_0 16 +#define BIT_MASK_C2_L_1_0 0x3 +#define BIT_C2_L_1_0(x) (((x) & BIT_MASK_C2_L_1_0) << BIT_SHIFT_C2_L_1_0) +#define BITS_C2_L_1_0 (BIT_MASK_C2_L_1_0 << BIT_SHIFT_C2_L_1_0) +#define BIT_CLEAR_C2_L_1_0(x) ((x) & (~BITS_C2_L_1_0)) +#define BIT_GET_C2_L_1_0(x) (((x) >> BIT_SHIFT_C2_L_1_0) & BIT_MASK_C2_L_1_0) +#define BIT_SET_C2_L_1_0(x, v) (BIT_CLEAR_C2_L_1_0(x) | BIT_C2_L_1_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_C2_L 16 +#define BIT_MASK_C2_L 0x3 +#define BIT_C2_L(x) (((x) & BIT_MASK_C2_L) << BIT_SHIFT_C2_L) +#define BITS_C2_L (BIT_MASK_C2_L << BIT_SHIFT_C2_L) +#define BIT_CLEAR_C2_L(x) ((x) & (~BITS_C2_L)) +#define BIT_GET_C2_L(x) (((x) >> BIT_SHIFT_C2_L) & BIT_MASK_C2_L) +#define BIT_SET_C2_L(x, v) (BIT_CLEAR_C2_L(x) | BIT_C2_L(v)) -/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_R_MAC_DBG_SHIFT 8 -#define BIT_MASK_R_MAC_DBG_SHIFT 0x7 -#define BIT_R_MAC_DBG_SHIFT(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT) -#define BIT_GET_R_MAC_DBG_SHIFT(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT) & BIT_MASK_R_MAC_DBG_SHIFT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_C1_L_1_0 14 +#define BIT_MASK_C1_L_1_0 0x3 +#define BIT_C1_L_1_0(x) (((x) & BIT_MASK_C1_L_1_0) << BIT_SHIFT_C1_L_1_0) +#define BITS_C1_L_1_0 (BIT_MASK_C1_L_1_0 << BIT_SHIFT_C1_L_1_0) +#define BIT_CLEAR_C1_L_1_0(x) ((x) & (~BITS_C1_L_1_0)) +#define BIT_GET_C1_L_1_0(x) (((x) >> BIT_SHIFT_C1_L_1_0) & BIT_MASK_C1_L_1_0) +#define BIT_SET_C1_L_1_0(x, v) (BIT_CLEAR_C1_L_1_0(x) | BIT_C1_L_1_0(v)) -#define BIT_SHIFT_R_MAC_DBG_SEL 0 -#define BIT_MASK_R_MAC_DBG_SEL 0x3 -#define BIT_R_MAC_DBG_SEL(x) (((x) & BIT_MASK_R_MAC_DBG_SEL) << BIT_SHIFT_R_MAC_DBG_SEL) -#define BIT_GET_R_MAC_DBG_SEL(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL) & BIT_MASK_R_MAC_DBG_SEL) +#endif +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_C1_L_V2 14 +#define BIT_MASK_C1_L_V2 0x3 +#define BIT_C1_L_V2(x) (((x) & BIT_MASK_C1_L_V2) << BIT_SHIFT_C1_L_V2) +#define BITS_C1_L_V2 (BIT_MASK_C1_L_V2 << BIT_SHIFT_C1_L_V2) +#define BIT_CLEAR_C1_L_V2(x) ((x) & (~BITS_C1_L_V2)) +#define BIT_GET_C1_L_V2(x) (((x) >> BIT_SHIFT_C1_L_V2) & BIT_MASK_C1_L_V2) +#define BIT_SET_C1_L_V2(x, v) (BIT_CLEAR_C1_L_V2(x) | BIT_C1_L_V2(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1 (Offset 0x07E8) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_REG_TYPE_L_V2 BIT(13) +#define BIT_REG_PWM_L BIT(12) -#define BIT_SHIFT_R_MAC_DEBUG_1 0 -#define BIT_MASK_R_MAC_DEBUG_1 0xffffffffL -#define BIT_R_MAC_DEBUG_1(x) (((x) & BIT_MASK_R_MAC_DEBUG_1) << BIT_SHIFT_R_MAC_DEBUG_1) -#define BIT_GET_R_MAC_DEBUG_1(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_1) & BIT_MASK_R_MAC_DEBUG_1) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_WSEC_OPTION (Offset 0x07EC) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_RXDEC_BM_MGNT BIT(22) -#define BIT_TXENC_BM_MGNT BIT(21) -#define BIT_RXDEC_UNI_MGNT BIT(20) -#define BIT_TXENC_UNI_MGNT BIT(19) +#define BIT_SHIFT_V15ADJ_L_2_0 9 +#define BIT_MASK_V15ADJ_L_2_0 0x7 +#define BIT_V15ADJ_L_2_0(x) \ + (((x) & BIT_MASK_V15ADJ_L_2_0) << BIT_SHIFT_V15ADJ_L_2_0) +#define BITS_V15ADJ_L_2_0 (BIT_MASK_V15ADJ_L_2_0 << BIT_SHIFT_V15ADJ_L_2_0) +#define BIT_CLEAR_V15ADJ_L_2_0(x) ((x) & (~BITS_V15ADJ_L_2_0)) +#define BIT_GET_V15ADJ_L_2_0(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L_2_0) & BIT_MASK_V15ADJ_L_2_0) +#define BIT_SET_V15ADJ_L_2_0(x, v) \ + (BIT_CLEAR_V15ADJ_L_2_0(x) | BIT_V15ADJ_L_2_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_V15ADJ_L 9 +#define BIT_MASK_V15ADJ_L 0x7 +#define BIT_V15ADJ_L(x) (((x) & BIT_MASK_V15ADJ_L) << BIT_SHIFT_V15ADJ_L) +#define BITS_V15ADJ_L (BIT_MASK_V15ADJ_L << BIT_SHIFT_V15ADJ_L) +#define BIT_CLEAR_V15ADJ_L(x) ((x) & (~BITS_V15ADJ_L)) +#define BIT_GET_V15ADJ_L(x) (((x) >> BIT_SHIFT_V15ADJ_L) & BIT_MASK_V15ADJ_L) +#define BIT_SET_V15ADJ_L(x, v) (BIT_CLEAR_V15ADJ_L(x) | BIT_V15ADJ_L(v)) -/* 2 REG_SEC_OPT_V2 (Offset 0x07EC) */ +#endif -#define BIT_MASK_IV BIT(18) -#define BIT_EIVL_ENDIAN BIT(17) -#define BIT_EIVH_ENDIAN BIT(16) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BT_TIME_CNT 0 -#define BIT_MASK_BT_TIME_CNT 0xff -#define BIT_BT_TIME_CNT(x) (((x) & BIT_MASK_BT_TIME_CNT) << BIT_SHIFT_BT_TIME_CNT) -#define BIT_GET_BT_TIME_CNT(x) (((x) >> BIT_SHIFT_BT_TIME_CNT) & BIT_MASK_BT_TIME_CNT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_IN_L_2_0 6 +#define BIT_MASK_IN_L_2_0 0x7 +#define BIT_IN_L_2_0(x) (((x) & BIT_MASK_IN_L_2_0) << BIT_SHIFT_IN_L_2_0) +#define BITS_IN_L_2_0 (BIT_MASK_IN_L_2_0 << BIT_SHIFT_IN_L_2_0) +#define BIT_CLEAR_IN_L_2_0(x) ((x) & (~BITS_IN_L_2_0)) +#define BIT_GET_IN_L_2_0(x) (((x) >> BIT_SHIFT_IN_L_2_0) & BIT_MASK_IN_L_2_0) +#define BIT_SET_IN_L_2_0(x, v) (BIT_CLEAR_IN_L_2_0(x) | BIT_IN_L_2_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_IN_L 6 +#define BIT_MASK_IN_L 0x7 +#define BIT_IN_L(x) (((x) & BIT_MASK_IN_L) << BIT_SHIFT_IN_L) +#define BITS_IN_L (BIT_MASK_IN_L << BIT_SHIFT_IN_L) +#define BIT_CLEAR_IN_L(x) ((x) & (~BITS_IN_L)) +#define BIT_GET_IN_L(x) (((x) >> BIT_SHIFT_IN_L) & BIT_MASK_IN_L) +#define BIT_SET_IN_L(x, v) (BIT_CLEAR_IN_L(x) | BIT_IN_L(v)) -/* 2 REG_RTS_ADDR0 (Offset 0x07F0) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RTS_ADDR0 0 -#define BIT_MASK_RTS_ADDR0 0xffffffffffffL -#define BIT_RTS_ADDR0(x) (((x) & BIT_MASK_RTS_ADDR0) << BIT_SHIFT_RTS_ADDR0) -#define BIT_GET_RTS_ADDR0(x) (((x) >> BIT_SHIFT_RTS_ADDR0) & BIT_MASK_RTS_ADDR0) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_STD_L_1_0 4 +#define BIT_MASK_STD_L_1_0 0x3 +#define BIT_STD_L_1_0(x) (((x) & BIT_MASK_STD_L_1_0) << BIT_SHIFT_STD_L_1_0) +#define BITS_STD_L_1_0 (BIT_MASK_STD_L_1_0 << BIT_SHIFT_STD_L_1_0) +#define BIT_CLEAR_STD_L_1_0(x) ((x) & (~BITS_STD_L_1_0)) +#define BIT_GET_STD_L_1_0(x) (((x) >> BIT_SHIFT_STD_L_1_0) & BIT_MASK_STD_L_1_0) +#define BIT_SET_STD_L_1_0(x, v) (BIT_CLEAR_STD_L_1_0(x) | BIT_STD_L_1_0(v)) -/* 2 REG_RTS_ADDR1 (Offset 0x07F8) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RTS_ADDR1 0 -#define BIT_MASK_RTS_ADDR1 0xffffffffffffL -#define BIT_RTS_ADDR1(x) (((x) & BIT_MASK_RTS_ADDR1) << BIT_SHIFT_RTS_ADDR1) -#define BIT_GET_RTS_ADDR1(x) (((x) >> BIT_SHIFT_RTS_ADDR1) & BIT_MASK_RTS_ADDR1) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_STD_L 4 +#define BIT_MASK_STD_L 0x3 +#define BIT_STD_L(x) (((x) & BIT_MASK_STD_L) << BIT_SHIFT_STD_L) +#define BITS_STD_L (BIT_MASK_STD_L << BIT_SHIFT_STD_L) +#define BIT_CLEAR_STD_L(x) ((x) & (~BITS_STD_L)) +#define BIT_GET_STD_L(x) (((x) >> BIT_SHIFT_STD_L) & BIT_MASK_STD_L) +#define BIT_SET_STD_L(x, v) (BIT_CLEAR_STD_L(x) | BIT_STD_L(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_FEN_BB_GLB_RSTN_V1 BIT(17) -#define BIT_FEN_BBRSTB_V1 BIT(16) +#define BIT_SHIFT_VOL_L_3_0 0 +#define BIT_MASK_VOL_L_3_0 0xf +#define BIT_VOL_L_3_0(x) (((x) & BIT_MASK_VOL_L_3_0) << BIT_SHIFT_VOL_L_3_0) +#define BITS_VOL_L_3_0 (BIT_MASK_VOL_L_3_0 << BIT_SHIFT_VOL_L_3_0) +#define BIT_CLEAR_VOL_L_3_0(x) ((x) & (~BITS_VOL_L_3_0)) +#define BIT_GET_VOL_L_3_0(x) (((x) >> BIT_SHIFT_VOL_L_3_0) & BIT_MASK_VOL_L_3_0) +#define BIT_SET_VOL_L_3_0(x, v) (BIT_CLEAR_VOL_L_3_0(x) | BIT_VOL_L_3_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_VOL_L 0 +#define BIT_MASK_VOL_L 0xf +#define BIT_VOL_L(x) (((x) & BIT_MASK_VOL_L) << BIT_SHIFT_VOL_L) +#define BITS_VOL_L (BIT_MASK_VOL_L << BIT_SHIFT_VOL_L) +#define BIT_CLEAR_VOL_L(x) ((x) & (~BITS_VOL_L)) +#define BIT_GET_VOL_L(x) (((x) >> BIT_SHIFT_VOL_L) & BIT_MASK_VOL_L) +#define BIT_SET_VOL_L(x, v) (BIT_CLEAR_VOL_L(x) | BIT_VOL_L(v)) -/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ -#define BIT_PWC_MA33V BIT(15) +#define BIT_SHIFT_OCP_L_PFM 29 +#define BIT_MASK_OCP_L_PFM 0x7 +#define BIT_OCP_L_PFM(x) (((x) & BIT_MASK_OCP_L_PFM) << BIT_SHIFT_OCP_L_PFM) +#define BITS_OCP_L_PFM (BIT_MASK_OCP_L_PFM << BIT_SHIFT_OCP_L_PFM) +#define BIT_CLEAR_OCP_L_PFM(x) ((x) & (~BITS_OCP_L_PFM)) +#define BIT_GET_OCP_L_PFM(x) (((x) >> BIT_SHIFT_OCP_L_PFM) & BIT_MASK_OCP_L_PFM) +#define BIT_SET_OCP_L_PFM(x, v) (BIT_CLEAR_OCP_L_PFM(x) | BIT_OCP_L_PFM(v)) -#endif +#define BIT_SHIFT_CFC_L_PFM 27 +#define BIT_MASK_CFC_L_PFM 0x3 +#define BIT_CFC_L_PFM(x) (((x) & BIT_MASK_CFC_L_PFM) << BIT_SHIFT_CFC_L_PFM) +#define BITS_CFC_L_PFM (BIT_MASK_CFC_L_PFM << BIT_SHIFT_CFC_L_PFM) +#define BIT_CLEAR_CFC_L_PFM(x) ((x) & (~BITS_CFC_L_PFM)) +#define BIT_GET_CFC_L_PFM(x) (((x) >> BIT_SHIFT_CFC_L_PFM) & BIT_MASK_CFC_L_PFM) +#define BIT_SET_CFC_L_PFM(x, v) (BIT_CLEAR_CFC_L_PFM(x) | BIT_CFC_L_PFM(v)) +#endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ -/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +#define BIT_SHIFT_REG_FREQ_L_V1 20 +#define BIT_MASK_REG_FREQ_L_V1 0x7 +#define BIT_REG_FREQ_L_V1(x) \ + (((x) & BIT_MASK_REG_FREQ_L_V1) << BIT_SHIFT_REG_FREQ_L_V1) +#define BITS_REG_FREQ_L_V1 (BIT_MASK_REG_FREQ_L_V1 << BIT_SHIFT_REG_FREQ_L_V1) +#define BIT_CLEAR_REG_FREQ_L_V1(x) ((x) & (~BITS_REG_FREQ_L_V1)) +#define BIT_GET_REG_FREQ_L_V1(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L_V1) & BIT_MASK_REG_FREQ_L_V1) +#define BIT_SET_REG_FREQ_L_V1(x, v) \ + (BIT_CLEAR_REG_FREQ_L_V1(x) | BIT_REG_FREQ_L_V1(v)) -#define BIT_PWC_EV25V_1 BIT(14) +#define BIT_EN_DUTY BIT(19) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_SHIFT_REG_MOS_HALF 17 +#define BIT_MASK_REG_MOS_HALF 0x3 +#define BIT_REG_MOS_HALF(x) \ + (((x) & BIT_MASK_REG_MOS_HALF) << BIT_SHIFT_REG_MOS_HALF) +#define BITS_REG_MOS_HALF (BIT_MASK_REG_MOS_HALF << BIT_SHIFT_REG_MOS_HALF) +#define BIT_CLEAR_REG_MOS_HALF(x) ((x) & (~BITS_REG_MOS_HALF)) +#define BIT_GET_REG_MOS_HALF(x) \ + (((x) >> BIT_SHIFT_REG_MOS_HALF) & BIT_MASK_REG_MOS_HALF) +#define BIT_SET_REG_MOS_HALF(x, v) \ + (BIT_CLEAR_REG_MOS_HALF(x) | BIT_REG_MOS_HALF(v)) -/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +#endif -#define BIT_PWC_MA12V BIT(14) -#define BIT_PWC_MD12V BIT(13) -#define BIT_PWC_PD12V BIT(12) -#define BIT_PWC_UD12V BIT(11) -#define BIT_ISO_MA2MD BIT(1) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_SHIFT_REG_MODE_V2 17 +#define BIT_MASK_REG_MODE_V2 0x3 +#define BIT_REG_MODE_V2(x) \ + (((x) & BIT_MASK_REG_MODE_V2) << BIT_SHIFT_REG_MODE_V2) +#define BITS_REG_MODE_V2 (BIT_MASK_REG_MODE_V2 << BIT_SHIFT_REG_MODE_V2) +#define BIT_CLEAR_REG_MODE_V2(x) ((x) & (~BITS_REG_MODE_V2)) +#define BIT_GET_REG_MODE_V2(x) \ + (((x) >> BIT_SHIFT_REG_MODE_V2) & BIT_MASK_REG_MODE_V2) +#define BIT_SET_REG_MODE_V2(x, v) \ + (BIT_CLEAR_REG_MODE_V2(x) | BIT_REG_MODE_V2(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_SYS_CFG4 (Offset 0x1034) */ +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ -#define BIT_EF_CSER_1 BIT(26) -#define BIT_SW_PG_EN_1 BIT(10) +#define BIT_EN_SP BIT(16) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_REG_AUTO_L_V1 BIT(15) -/* 2 REG_SYS_CFG5 (Offset 0x1070) */ +#endif -#define BIT_LPS_STATUS BIT(3) -#define BIT_HCI_TXDMA_BUSY BIT(2) -#define BIT_HCI_TXDMA_ALLOW BIT(1) -#define BIT_FW_CTRL_HCI_TXDMA_EN BIT(0) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_REG_AUTO_L_V2 BIT(15) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ -#define BIT_WDT_AUTO_MODE BIT(22) -#define BIT_WDT_PLATFORM_EN BIT(21) -#define BIT_WDT_CPU_EN BIT(20) +#define BIT_REG_LDOF_L_V2 BIT(14) +#define BIT_REG_OCPS_L_V2 BIT(13) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_VO15_V1P05_H BIT(12) -/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ +#endif -#define BIT_WDT_OPT_IOWRAPPER BIT(19) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_ARENB_L_V1 BIT(11) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ -#define BIT_ANA_PORT_IDLE BIT(18) -#define BIT_MAC_PORT_IDLE BIT(17) -#define BIT_WL_PLATFORM_RST BIT(16) -#define BIT_WL_SECURITY_CLK BIT(15) +#define BIT_ARENB_L_V2 BIT(11) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_SHIFT_TBOX_L1_1_0 9 +#define BIT_MASK_TBOX_L1_1_0 0x3 +#define BIT_TBOX_L1_1_0(x) \ + (((x) & BIT_MASK_TBOX_L1_1_0) << BIT_SHIFT_TBOX_L1_1_0) +#define BITS_TBOX_L1_1_0 (BIT_MASK_TBOX_L1_1_0 << BIT_SHIFT_TBOX_L1_1_0) +#define BIT_CLEAR_TBOX_L1_1_0(x) ((x) & (~BITS_TBOX_L1_1_0)) +#define BIT_GET_TBOX_L1_1_0(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_1_0) & BIT_MASK_TBOX_L1_1_0) +#define BIT_SET_TBOX_L1_1_0(x, v) \ + (BIT_CLEAR_TBOX_L1_1_0(x) | BIT_TBOX_L1_1_0(v)) -/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_CPU_DMEM_CON 0 -#define BIT_MASK_CPU_DMEM_CON 0xff -#define BIT_CPU_DMEM_CON(x) (((x) & BIT_MASK_CPU_DMEM_CON) << BIT_SHIFT_CPU_DMEM_CON) -#define BIT_GET_CPU_DMEM_CON(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON) & BIT_MASK_CPU_DMEM_CON) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_SHIFT_TBOX_L1_V2 9 +#define BIT_MASK_TBOX_L1_V2 0x3 +#define BIT_TBOX_L1_V2(x) (((x) & BIT_MASK_TBOX_L1_V2) << BIT_SHIFT_TBOX_L1_V2) +#define BITS_TBOX_L1_V2 (BIT_MASK_TBOX_L1_V2 << BIT_SHIFT_TBOX_L1_V2) +#define BIT_CLEAR_TBOX_L1_V2(x) ((x) & (~BITS_TBOX_L1_V2)) +#define BIT_GET_TBOX_L1_V2(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_V2) & BIT_MASK_TBOX_L1_V2) +#define BIT_SET_TBOX_L1_V2(x, v) (BIT_CLEAR_TBOX_L1_V2(x) | BIT_TBOX_L1_V2(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_SHIFT_REG_DELAY_L_1_0 7 +#define BIT_MASK_REG_DELAY_L_1_0 0x3 +#define BIT_REG_DELAY_L_1_0(x) \ + (((x) & BIT_MASK_REG_DELAY_L_1_0) << BIT_SHIFT_REG_DELAY_L_1_0) +#define BITS_REG_DELAY_L_1_0 \ + (BIT_MASK_REG_DELAY_L_1_0 << BIT_SHIFT_REG_DELAY_L_1_0) +#define BIT_CLEAR_REG_DELAY_L_1_0(x) ((x) & (~BITS_REG_DELAY_L_1_0)) +#define BIT_GET_REG_DELAY_L_1_0(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_L_1_0) & BIT_MASK_REG_DELAY_L_1_0) +#define BIT_SET_REG_DELAY_L_1_0(x, v) \ + (BIT_CLEAR_REG_DELAY_L_1_0(x) | BIT_REG_DELAY_L_1_0(v)) -/* 2 REG_BOOT_REASON (Offset 0x1088) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BOOT_REASON 0 -#define BIT_MASK_BOOT_REASON 0x7 -#define BIT_BOOT_REASON(x) (((x) & BIT_MASK_BOOT_REASON) << BIT_SHIFT_BOOT_REASON) -#define BIT_GET_BOOT_REASON(x) (((x) >> BIT_SHIFT_BOOT_REASON) & BIT_MASK_BOOT_REASON) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_SHIFT_REG_DELAY_L 7 +#define BIT_MASK_REG_DELAY_L 0x3 +#define BIT_REG_DELAY_L(x) \ + (((x) & BIT_MASK_REG_DELAY_L) << BIT_SHIFT_REG_DELAY_L) +#define BITS_REG_DELAY_L (BIT_MASK_REG_DELAY_L << BIT_SHIFT_REG_DELAY_L) +#define BIT_CLEAR_REG_DELAY_L(x) ((x) & (~BITS_REG_DELAY_L)) +#define BIT_GET_REG_DELAY_L(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_L) & BIT_MASK_REG_DELAY_L) +#define BIT_SET_REG_DELAY_L(x, v) \ + (BIT_CLEAR_REG_DELAY_L(x) | BIT_REG_DELAY_L(v)) -/* 2 REG_NFCPAD_CTRL (Offset 0x10A8) */ +#endif -#define BIT_PAD_SHUTDW BIT(18) -#define BIT_SYSON_NFC_PAD BIT(17) -#define BIT_NFC_INT_PAD_CTRL BIT(16) -#define BIT_NFC_RFDIS_PAD_CTRL BIT(15) -#define BIT_NFC_CLK_PAD_CTRL BIT(14) -#define BIT_NFC_DATA_PAD_CTRL BIT(13) -#define BIT_NFC_PAD_PULL_CTRL BIT(12) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NFCPAD_IO_SEL 8 -#define BIT_MASK_NFCPAD_IO_SEL 0xf -#define BIT_NFCPAD_IO_SEL(x) (((x) & BIT_MASK_NFCPAD_IO_SEL) << BIT_SHIFT_NFCPAD_IO_SEL) -#define BIT_GET_NFCPAD_IO_SEL(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL) & BIT_MASK_NFCPAD_IO_SEL) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_REG_CLAMP_D_L BIT(6) -#define BIT_SHIFT_NFCPAD_OUT 4 -#define BIT_MASK_NFCPAD_OUT 0xf -#define BIT_NFCPAD_OUT(x) (((x) & BIT_MASK_NFCPAD_OUT) << BIT_SHIFT_NFCPAD_OUT) -#define BIT_GET_NFCPAD_OUT(x) (((x) >> BIT_SHIFT_NFCPAD_OUT) & BIT_MASK_NFCPAD_OUT) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_NFCPAD_IN 0 -#define BIT_MASK_NFCPAD_IN 0xf -#define BIT_NFCPAD_IN(x) (((x) & BIT_MASK_NFCPAD_IN) << BIT_SHIFT_NFCPAD_IN) -#define BIT_GET_NFCPAD_IN(x) (((x) >> BIT_SHIFT_NFCPAD_IN) & BIT_MASK_NFCPAD_IN) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_REG_BYPASS_L_V1 BIT(5) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_REG_BYPASS_L_V2 BIT(5) -/* 2 REG_HIMR2 (Offset 0x10B0) */ +#endif -#define BIT_BCNDMAINT_P4_MSK BIT(31) -#define BIT_BCNDMAINT_P3_MSK BIT(30) -#define BIT_BCNDMAINT_P2_MSK BIT(29) -#define BIT_BCNDMAINT_P1_MSK BIT(28) -#define BIT_ATIMEND7_MSK BIT(22) -#define BIT_ATIMEND6_MSK BIT(21) -#define BIT_ATIMEND5_MSK BIT(20) -#define BIT_ATIMEND4_MSK BIT(19) -#define BIT_ATIMEND3_MSK BIT(18) -#define BIT_ATIMEND2_MSK BIT(17) -#define BIT_ATIMEND1_MSK BIT(16) -#define BIT_TXBCN7OK_MSK BIT(14) -#define BIT_TXBCN6OK_MSK BIT(13) -#define BIT_TXBCN5OK_MSK BIT(12) -#define BIT_TXBCN4OK_MSK BIT(11) -#define BIT_TXBCN3OK_MSK BIT(10) -#define BIT_TXBCN2OK_MSK BIT(9) -#define BIT_TXBCN1OK_MSK_V1 BIT(8) -#define BIT_TXBCN7ERR_MSK BIT(6) -#define BIT_TXBCN6ERR_MSK BIT(5) -#define BIT_TXBCN5ERR_MSK BIT(4) -#define BIT_TXBCN4ERR_MSK BIT(3) -#define BIT_TXBCN3ERR_MSK BIT(2) -#define BIT_TXBCN2ERR_MSK BIT(1) -#define BIT_TXBCN1ERR_MSK_V1 BIT(0) - -/* 2 REG_HISR2 (Offset 0x10B4) */ - -#define BIT_BCNDMAINT_P4 BIT(31) -#define BIT_BCNDMAINT_P3 BIT(30) -#define BIT_BCNDMAINT_P2 BIT(29) -#define BIT_BCNDMAINT_P1 BIT(28) -#define BIT_ATIMEND7 BIT(22) -#define BIT_ATIMEND6 BIT(21) -#define BIT_ATIMEND5 BIT(20) -#define BIT_ATIMEND4 BIT(19) -#define BIT_ATIMEND3 BIT(18) -#define BIT_ATIMEND2 BIT(17) -#define BIT_ATIMEND1 BIT(16) -#define BIT_TXBCN7OK BIT(14) -#define BIT_TXBCN6OK BIT(13) -#define BIT_TXBCN5OK BIT(12) -#define BIT_TXBCN4OK BIT(11) -#define BIT_TXBCN3OK BIT(10) -#define BIT_TXBCN2OK BIT(9) -#define BIT_TXBCN1OK BIT(8) -#define BIT_TXBCN7ERR BIT(6) -#define BIT_TXBCN6ERR BIT(5) -#define BIT_TXBCN5ERR BIT(4) -#define BIT_TXBCN4ERR BIT(3) -#define BIT_TXBCN3ERR BIT(2) -#define BIT_TXBCN2ERR BIT(1) -#define BIT_TXBCN1ERR BIT(0) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_REG_AUTOZCD_L BIT(4) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_HIMR3 (Offset 0x10B8) */ +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ -#define BIT_WDT_PLATFORM_INT_MSK BIT(18) -#define BIT_WDT_CPU_INT_MSK BIT(17) +#define BIT_POW_ZCD_L_V1 BIT(3) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_POW_ZCD_L_V2 BIT(3) +#define BIT_REG_HALF_L BIT(2) -/* 2 REG_HIMR3 (Offset 0x10B8) */ +#endif -#define BIT_SETH2CDOK_MASK BIT(16) -#define BIT_H2C_CMD_FULL_MASK BIT(15) -#define BIT_PWR_INT_127_MASK BIT(14) -#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK BIT(13) -#define BIT_TXSHORTCUT_BKUPDATEOK_MASK BIT(12) -#define BIT_TXSHORTCUT_BEUPDATEOK_MASK BIT(11) -#define BIT_TXSHORTCUT_VIUPDATEOK_MAS BIT(10) -#define BIT_TXSHORTCUT_VOUPDATEOK_MASK BIT(9) -#define BIT_PWR_INT_127_MASK_V1 BIT(8) -#define BIT_PWR_INT_126TO96_MASK BIT(7) -#define BIT_PWR_INT_95TO64_MASK BIT(6) -#define BIT_PWR_INT_63TO32_MASK BIT(5) -#define BIT_PWR_INT_31TO0_MASK BIT(4) -#define BIT_DDMA0_LP_INT_MSK BIT(1) -#define BIT_DDMA0_HP_INT_MSK BIT(0) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_SHIFT_OCP_L_2_1 0 +#define BIT_MASK_OCP_L_2_1 0x3 +#define BIT_OCP_L_2_1(x) (((x) & BIT_MASK_OCP_L_2_1) << BIT_SHIFT_OCP_L_2_1) +#define BITS_OCP_L_2_1 (BIT_MASK_OCP_L_2_1 << BIT_SHIFT_OCP_L_2_1) +#define BIT_CLEAR_OCP_L_2_1(x) ((x) & (~BITS_OCP_L_2_1)) +#define BIT_GET_OCP_L_2_1(x) (((x) >> BIT_SHIFT_OCP_L_2_1) & BIT_MASK_OCP_L_2_1) +#define BIT_SET_OCP_L_2_1(x, v) (BIT_CLEAR_OCP_L_2_1(x) | BIT_OCP_L_2_1(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_HISR3 (Offset 0x10BC) */ +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ -#define BIT_WDT_PLATFORM_INT BIT(18) -#define BIT_WDT_CPU_INT BIT(17) +#define BIT_SHIFT_OCP_L_V2 0 +#define BIT_MASK_OCP_L_V2 0x3 +#define BIT_OCP_L_V2(x) (((x) & BIT_MASK_OCP_L_V2) << BIT_SHIFT_OCP_L_V2) +#define BITS_OCP_L_V2 (BIT_MASK_OCP_L_V2 << BIT_SHIFT_OCP_L_V2) +#define BIT_CLEAR_OCP_L_V2(x) ((x) & (~BITS_OCP_L_V2)) +#define BIT_GET_OCP_L_V2(x) (((x) >> BIT_SHIFT_OCP_L_V2) & BIT_MASK_OCP_L_V2) +#define BIT_SET_OCP_L_V2(x, v) (BIT_CLEAR_OCP_L_V2(x) | BIT_OCP_L_V2(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_LPF_C2_1_0 30 +#define BIT_MASK_LPF_C2_1_0 0x3 +#define BIT_LPF_C2_1_0(x) (((x) & BIT_MASK_LPF_C2_1_0) << BIT_SHIFT_LPF_C2_1_0) +#define BITS_LPF_C2_1_0 (BIT_MASK_LPF_C2_1_0 << BIT_SHIFT_LPF_C2_1_0) +#define BIT_CLEAR_LPF_C2_1_0(x) ((x) & (~BITS_LPF_C2_1_0)) +#define BIT_GET_LPF_C2_1_0(x) \ + (((x) >> BIT_SHIFT_LPF_C2_1_0) & BIT_MASK_LPF_C2_1_0) +#define BIT_SET_LPF_C2_1_0(x, v) (BIT_CLEAR_LPF_C2_1_0(x) | BIT_LPF_C2_1_0(v)) -/* 2 REG_HISR3 (Offset 0x10BC) */ +#endif -#define BIT_SETH2CDOK BIT(16) -#define BIT_H2C_CMD_FULL BIT(15) -#define BIT_PWR_INT_127 BIT(14) -#define BIT_TXSHORTCUT_TXDESUPDATEOK BIT(13) -#define BIT_TXSHORTCUT_BKUPDATEOK BIT(12) -#define BIT_TXSHORTCUT_BEUPDATEOK BIT(11) -#define BIT_TXSHORTCUT_VIUPDATEOK BIT(10) -#define BIT_TXSHORTCUT_VOUPDATEOK BIT(9) -#define BIT_PWR_INT_127_V1 BIT(8) -#define BIT_PWR_INT_126TO96 BIT(7) -#define BIT_PWR_INT_95TO64 BIT(6) -#define BIT_PWR_INT_63TO32 BIT(5) -#define BIT_PWR_INT_31TO0 BIT(4) -#define BIT_DDMA0_LP_INT BIT(1) -#define BIT_DDMA0_HP_INT BIT(0) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_REG_LPF_R3 29 +#define BIT_MASK_REG_LPF_R3 0x7 +#define BIT_REG_LPF_R3(x) (((x) & BIT_MASK_REG_LPF_R3) << BIT_SHIFT_REG_LPF_R3) +#define BITS_REG_LPF_R3 (BIT_MASK_REG_LPF_R3 << BIT_SHIFT_REG_LPF_R3) +#define BIT_CLEAR_REG_LPF_R3(x) ((x) & (~BITS_REG_LPF_R3)) +#define BIT_GET_REG_LPF_R3(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R3) & BIT_MASK_REG_LPF_R3) +#define BIT_SET_REG_LPF_R3(x, v) (BIT_CLEAR_REG_LPF_R3(x) | BIT_REG_LPF_R3(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_SW_MDIO (Offset 0x10C0) */ +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ -#define BIT_DIS_TIMEOUT_IO BIT(24) +#define BIT_EN_XTAL_AAC_TRIG BIT(28) +#define BIT_EN_XTAL_AAC BIT(27) +#define BIT_EN_XTAL_AAC_DIGI BIT(26) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_LPF_C1_5_0 24 +#define BIT_MASK_LPF_C1_5_0 0x3f +#define BIT_LPF_C1_5_0(x) (((x) & BIT_MASK_LPF_C1_5_0) << BIT_SHIFT_LPF_C1_5_0) +#define BITS_LPF_C1_5_0 (BIT_MASK_LPF_C1_5_0 << BIT_SHIFT_LPF_C1_5_0) +#define BIT_CLEAR_LPF_C1_5_0(x) ((x) & (~BITS_LPF_C1_5_0)) +#define BIT_GET_LPF_C1_5_0(x) \ + (((x) >> BIT_SHIFT_LPF_C1_5_0) & BIT_MASK_LPF_C1_5_0) +#define BIT_SET_LPF_C1_5_0(x, v) (BIT_CLEAR_LPF_C1_5_0(x) | BIT_LPF_C1_5_0(v)) -/* 2 REG_SW_MDIO (Offset 0x10C0) */ +#endif -#define BIT_SUS_PL BIT(18) -#define BIT_SOP_ESUS BIT(17) -#define BIT_SOP_DLDO BIT(16) -#define BIT_R_OCP_ST_CLR BIT(8) -#define BIT_SW_USB3_MD_SEL BIT(5) -#define BIT_SW_PCIE_MD_SEL BIT(4) -#define BIT_SW_MDCK BIT(2) -#define BIT_SW_MDI BIT(1) -#define BIT_MDO BIT(0) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_REG_LPF_R2 24 +#define BIT_MASK_REG_LPF_R2 0x1f +#define BIT_REG_LPF_R2(x) (((x) & BIT_MASK_REG_LPF_R2) << BIT_SHIFT_REG_LPF_R2) +#define BITS_REG_LPF_R2 (BIT_MASK_REG_LPF_R2 << BIT_SHIFT_REG_LPF_R2) +#define BIT_CLEAR_REG_LPF_R2(x) ((x) & (~BITS_REG_LPF_R2)) +#define BIT_GET_REG_LPF_R2(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R2) & BIT_MASK_REG_LPF_R2) +#define BIT_SET_REG_LPF_R2(x, v) (BIT_CLEAR_REG_LPF_R2(x) | BIT_REG_LPF_R2(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_SW_FLUSH (Offset 0x10C4) */ +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ -#define BIT_FLUSH_HOLDN_EN BIT(25) -#define BIT_FLUSH_WR_EN BIT(24) -#define BIT_SW_FLASH_CONTROL BIT(23) -#define BIT_SW_FLASH_WEN_E BIT(19) -#define BIT_SW_FLASH_HOLDN_E BIT(18) -#define BIT_SW_FLASH_SO_E BIT(17) -#define BIT_SW_FLASH_SI_E BIT(16) -#define BIT_SW_FLASH_SK_O BIT(13) -#define BIT_SW_FLASH_CEN_O BIT(12) -#define BIT_SW_FLASH_WEN_O BIT(11) -#define BIT_SW_FLASH_HOLDN_O BIT(10) -#define BIT_SW_FLASH_SO_O BIT(9) -#define BIT_SW_FLASH_SI_O BIT(8) -#define BIT_SW_FLASH_WEN_I BIT(3) -#define BIT_SW_FLASH_HOLDN_I BIT(2) -#define BIT_SW_FLASH_SO_I BIT(1) -#define BIT_SW_FLASH_SI_I BIT(0) +#define BIT_LPF_TIEL BIT(23) +#define BIT_LPF_TIEH BIT(22) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_REG_LPF_C3 21 +#define BIT_MASK_REG_LPF_C3 0x7 +#define BIT_REG_LPF_C3(x) (((x) & BIT_MASK_REG_LPF_C3) << BIT_SHIFT_REG_LPF_C3) +#define BITS_REG_LPF_C3 (BIT_MASK_REG_LPF_C3 << BIT_SHIFT_REG_LPF_C3) +#define BIT_CLEAR_REG_LPF_C3(x) ((x) & (~BITS_REG_LPF_C3)) +#define BIT_GET_REG_LPF_C3(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C3) & BIT_MASK_REG_LPF_C3) +#define BIT_SET_REG_LPF_C3(x, v) (BIT_CLEAR_REG_LPF_C3(x) | BIT_REG_LPF_C3(v)) -/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_DBG_GPIO_BMUX_7 21 -#define BIT_MASK_DBG_GPIO_BMUX_7 0x7 -#define BIT_DBG_GPIO_BMUX_7(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_7) << BIT_SHIFT_DBG_GPIO_BMUX_7) -#define BIT_GET_DBG_GPIO_BMUX_7(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7) & BIT_MASK_DBG_GPIO_BMUX_7) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_LOCKDET_VREF_L_1_0 20 +#define BIT_MASK_LOCKDET_VREF_L_1_0 0x3 +#define BIT_LOCKDET_VREF_L_1_0(x) \ + (((x) & BIT_MASK_LOCKDET_VREF_L_1_0) << BIT_SHIFT_LOCKDET_VREF_L_1_0) +#define BITS_LOCKDET_VREF_L_1_0 \ + (BIT_MASK_LOCKDET_VREF_L_1_0 << BIT_SHIFT_LOCKDET_VREF_L_1_0) +#define BIT_CLEAR_LOCKDET_VREF_L_1_0(x) ((x) & (~BITS_LOCKDET_VREF_L_1_0)) +#define BIT_GET_LOCKDET_VREF_L_1_0(x) \ + (((x) >> BIT_SHIFT_LOCKDET_VREF_L_1_0) & BIT_MASK_LOCKDET_VREF_L_1_0) +#define BIT_SET_LOCKDET_VREF_L_1_0(x, v) \ + (BIT_CLEAR_LOCKDET_VREF_L_1_0(x) | BIT_LOCKDET_VREF_L_1_0(v)) -#define BIT_SHIFT_DBG_GPIO_BMUX_6 18 -#define BIT_MASK_DBG_GPIO_BMUX_6 0x7 -#define BIT_DBG_GPIO_BMUX_6(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_6) << BIT_SHIFT_DBG_GPIO_BMUX_6) -#define BIT_GET_DBG_GPIO_BMUX_6(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6) & BIT_MASK_DBG_GPIO_BMUX_6) +#define BIT_SHIFT_LOCKDET_VREF_H_1_0 18 +#define BIT_MASK_LOCKDET_VREF_H_1_0 0x3 +#define BIT_LOCKDET_VREF_H_1_0(x) \ + (((x) & BIT_MASK_LOCKDET_VREF_H_1_0) << BIT_SHIFT_LOCKDET_VREF_H_1_0) +#define BITS_LOCKDET_VREF_H_1_0 \ + (BIT_MASK_LOCKDET_VREF_H_1_0 << BIT_SHIFT_LOCKDET_VREF_H_1_0) +#define BIT_CLEAR_LOCKDET_VREF_H_1_0(x) ((x) & (~BITS_LOCKDET_VREF_H_1_0)) +#define BIT_GET_LOCKDET_VREF_H_1_0(x) \ + (((x) >> BIT_SHIFT_LOCKDET_VREF_H_1_0) & BIT_MASK_LOCKDET_VREF_H_1_0) +#define BIT_SET_LOCKDET_VREF_H_1_0(x, v) \ + (BIT_CLEAR_LOCKDET_VREF_H_1_0(x) | BIT_LOCKDET_VREF_H_1_0(v)) +#endif -#define BIT_SHIFT_DBG_GPIO_BMUX_5 15 -#define BIT_MASK_DBG_GPIO_BMUX_5 0x7 -#define BIT_DBG_GPIO_BMUX_5(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_5) << BIT_SHIFT_DBG_GPIO_BMUX_5) -#define BIT_GET_DBG_GPIO_BMUX_5(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5) & BIT_MASK_DBG_GPIO_BMUX_5) +#if (HALMAC_8822C_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ -#define BIT_SHIFT_DBG_GPIO_BMUX_4 12 -#define BIT_MASK_DBG_GPIO_BMUX_4 0x7 -#define BIT_DBG_GPIO_BMUX_4(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_4) << BIT_SHIFT_DBG_GPIO_BMUX_4) -#define BIT_GET_DBG_GPIO_BMUX_4(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4) & BIT_MASK_DBG_GPIO_BMUX_4) +#define BIT_SHIFT_REG_LPF_C2 18 +#define BIT_MASK_REG_LPF_C2 0x7 +#define BIT_REG_LPF_C2(x) (((x) & BIT_MASK_REG_LPF_C2) << BIT_SHIFT_REG_LPF_C2) +#define BITS_REG_LPF_C2 (BIT_MASK_REG_LPF_C2 << BIT_SHIFT_REG_LPF_C2) +#define BIT_CLEAR_REG_LPF_C2(x) ((x) & (~BITS_REG_LPF_C2)) +#define BIT_GET_REG_LPF_C2(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C2) & BIT_MASK_REG_LPF_C2) +#define BIT_SET_REG_LPF_C2(x, v) (BIT_CLEAR_REG_LPF_C2(x) | BIT_REG_LPF_C2(v)) +#endif -#define BIT_SHIFT_DBG_GPIO_BMUX_3 9 -#define BIT_MASK_DBG_GPIO_BMUX_3 0x7 -#define BIT_DBG_GPIO_BMUX_3(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_3) << BIT_SHIFT_DBG_GPIO_BMUX_3) -#define BIT_GET_DBG_GPIO_BMUX_3(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3) & BIT_MASK_DBG_GPIO_BMUX_3) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ -#define BIT_SHIFT_DBG_GPIO_BMUX_2 6 -#define BIT_MASK_DBG_GPIO_BMUX_2 0x7 -#define BIT_DBG_GPIO_BMUX_2(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_2) << BIT_SHIFT_DBG_GPIO_BMUX_2) -#define BIT_GET_DBG_GPIO_BMUX_2(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2) & BIT_MASK_DBG_GPIO_BMUX_2) +#define BIT_SHIFT_LDO_SEL_1_0 16 +#define BIT_MASK_LDO_SEL_1_0 0x3 +#define BIT_LDO_SEL_1_0(x) \ + (((x) & BIT_MASK_LDO_SEL_1_0) << BIT_SHIFT_LDO_SEL_1_0) +#define BITS_LDO_SEL_1_0 (BIT_MASK_LDO_SEL_1_0 << BIT_SHIFT_LDO_SEL_1_0) +#define BIT_CLEAR_LDO_SEL_1_0(x) ((x) & (~BITS_LDO_SEL_1_0)) +#define BIT_GET_LDO_SEL_1_0(x) \ + (((x) >> BIT_SHIFT_LDO_SEL_1_0) & BIT_MASK_LDO_SEL_1_0) +#define BIT_SET_LDO_SEL_1_0(x, v) \ + (BIT_CLEAR_LDO_SEL_1_0(x) | BIT_LDO_SEL_1_0(v)) +#endif -#define BIT_SHIFT_DBG_GPIO_BMUX_1 3 -#define BIT_MASK_DBG_GPIO_BMUX_1 0x7 -#define BIT_DBG_GPIO_BMUX_1(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_1) << BIT_SHIFT_DBG_GPIO_BMUX_1) -#define BIT_GET_DBG_GPIO_BMUX_1(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1) & BIT_MASK_DBG_GPIO_BMUX_1) +#if (HALMAC_8822C_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ -#define BIT_SHIFT_DBG_GPIO_BMUX_0 0 -#define BIT_MASK_DBG_GPIO_BMUX_0 0x7 -#define BIT_DBG_GPIO_BMUX_0(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_0) << BIT_SHIFT_DBG_GPIO_BMUX_0) -#define BIT_GET_DBG_GPIO_BMUX_0(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0) & BIT_MASK_DBG_GPIO_BMUX_0) +#define BIT_SHIFT_REG_LPF_C1 15 +#define BIT_MASK_REG_LPF_C1 0x7 +#define BIT_REG_LPF_C1(x) (((x) & BIT_MASK_REG_LPF_C1) << BIT_SHIFT_REG_LPF_C1) +#define BITS_REG_LPF_C1 (BIT_MASK_REG_LPF_C1 << BIT_SHIFT_REG_LPF_C1) +#define BIT_CLEAR_REG_LPF_C1(x) ((x) & (~BITS_REG_LPF_C1)) +#define BIT_GET_REG_LPF_C1(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C1) & BIT_MASK_REG_LPF_C1) +#define BIT_SET_REG_LPF_C1(x, v) (BIT_CLEAR_REG_LPF_C1(x) | BIT_REG_LPF_C1(v)) +#define BIT_SHIFT_REG_LDO_SEL_V1 13 +#define BIT_MASK_REG_LDO_SEL_V1 0x3 +#define BIT_REG_LDO_SEL_V1(x) \ + (((x) & BIT_MASK_REG_LDO_SEL_V1) << BIT_SHIFT_REG_LDO_SEL_V1) +#define BITS_REG_LDO_SEL_V1 \ + (BIT_MASK_REG_LDO_SEL_V1 << BIT_SHIFT_REG_LDO_SEL_V1) +#define BIT_CLEAR_REG_LDO_SEL_V1(x) ((x) & (~BITS_REG_LDO_SEL_V1)) +#define BIT_GET_REG_LDO_SEL_V1(x) \ + (((x) >> BIT_SHIFT_REG_LDO_SEL_V1) & BIT_MASK_REG_LDO_SEL_V1) +#define BIT_SET_REG_LDO_SEL_V1(x, v) \ + (BIT_CLEAR_REG_LDO_SEL_V1(x) | BIT_REG_LDO_SEL_V1(v)) -/* 2 REG_FPGA_TAG (Offset 0x10CC) */ +#define BIT_REG_CP_ICPX2 BIT(12) -#define BIT_WL_DSS_RSTN BIT(27) -#define BIT_WL_DSS_EN_CLK BIT(26) -#define BIT_WL_DSS_SPEED_EN BIT(25) +#endif -#define BIT_SHIFT_FPGA_TAG 0 -#define BIT_MASK_FPGA_TAG 0xffffffffL -#define BIT_FPGA_TAG(x) (((x) & BIT_MASK_FPGA_TAG) << BIT_SHIFT_FPGA_TAG) -#define BIT_GET_FPGA_TAG(x) (((x) >> BIT_SHIFT_FPGA_TAG) & BIT_MASK_FPGA_TAG) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ -#define BIT_SHIFT_WL_DSS_COUNT_OUT 0 -#define BIT_MASK_WL_DSS_COUNT_OUT 0xfffff -#define BIT_WL_DSS_COUNT_OUT(x) (((x) & BIT_MASK_WL_DSS_COUNT_OUT) << BIT_SHIFT_WL_DSS_COUNT_OUT) -#define BIT_GET_WL_DSS_COUNT_OUT(x) (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT) & BIT_MASK_WL_DSS_COUNT_OUT) +#define BIT_SHIFT_IOFFSET_5_0 10 +#define BIT_MASK_IOFFSET_5_0 0x3f +#define BIT_IOFFSET_5_0(x) \ + (((x) & BIT_MASK_IOFFSET_5_0) << BIT_SHIFT_IOFFSET_5_0) +#define BITS_IOFFSET_5_0 (BIT_MASK_IOFFSET_5_0 << BIT_SHIFT_IOFFSET_5_0) +#define BIT_CLEAR_IOFFSET_5_0(x) ((x) & (~BITS_IOFFSET_5_0)) +#define BIT_GET_IOFFSET_5_0(x) \ + (((x) >> BIT_SHIFT_IOFFSET_5_0) & BIT_MASK_IOFFSET_5_0) +#define BIT_SET_IOFFSET_5_0(x, v) \ + (BIT_CLEAR_IOFFSET_5_0(x) | BIT_IOFFSET_5_0(v)) +#define BIT_CP_ICPX2 BIT(9) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_REG_CP_ICP_SEL_FAST 9 +#define BIT_MASK_REG_CP_ICP_SEL_FAST 0x7 +#define BIT_REG_CP_ICP_SEL_FAST(x) \ + (((x) & BIT_MASK_REG_CP_ICP_SEL_FAST) << BIT_SHIFT_REG_CP_ICP_SEL_FAST) +#define BITS_REG_CP_ICP_SEL_FAST \ + (BIT_MASK_REG_CP_ICP_SEL_FAST << BIT_SHIFT_REG_CP_ICP_SEL_FAST) +#define BIT_CLEAR_REG_CP_ICP_SEL_FAST(x) ((x) & (~BITS_REG_CP_ICP_SEL_FAST)) +#define BIT_GET_REG_CP_ICP_SEL_FAST(x) \ + (((x) >> BIT_SHIFT_REG_CP_ICP_SEL_FAST) & BIT_MASK_REG_CP_ICP_SEL_FAST) +#define BIT_SET_REG_CP_ICP_SEL_FAST(x, v) \ + (BIT_CLEAR_REG_CP_ICP_SEL_FAST(x) | BIT_REG_CP_ICP_SEL_FAST(v)) -/* 2 REG_H2C_PKT_READADDR (Offset 0x10D0) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_H2C_PKT_READADDR 0 -#define BIT_MASK_H2C_PKT_READADDR 0x3ffff -#define BIT_H2C_PKT_READADDR(x) (((x) & BIT_MASK_H2C_PKT_READADDR) << BIT_SHIFT_H2C_PKT_READADDR) -#define BIT_GET_H2C_PKT_READADDR(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR) & BIT_MASK_H2C_PKT_READADDR) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_GM_STEP BIT(7) -/* 2 REG_H2C_PKT_WRITEADDR (Offset 0x10D4) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_H2C_PKT_WRITEADDR 0 -#define BIT_MASK_H2C_PKT_WRITEADDR 0x3ffff -#define BIT_H2C_PKT_WRITEADDR(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR) << BIT_SHIFT_H2C_PKT_WRITEADDR) -#define BIT_GET_H2C_PKT_WRITEADDR(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_PKT_WRITEADDR) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_REG_CP_ICP_SEL 6 +#define BIT_MASK_REG_CP_ICP_SEL 0x7 +#define BIT_REG_CP_ICP_SEL(x) \ + (((x) & BIT_MASK_REG_CP_ICP_SEL) << BIT_SHIFT_REG_CP_ICP_SEL) +#define BITS_REG_CP_ICP_SEL \ + (BIT_MASK_REG_CP_ICP_SEL << BIT_SHIFT_REG_CP_ICP_SEL) +#define BIT_CLEAR_REG_CP_ICP_SEL(x) ((x) & (~BITS_REG_CP_ICP_SEL)) +#define BIT_GET_REG_CP_ICP_SEL(x) \ + (((x) >> BIT_SHIFT_REG_CP_ICP_SEL) & BIT_MASK_REG_CP_ICP_SEL) +#define BIT_SET_REG_CP_ICP_SEL(x, v) \ + (BIT_CLEAR_REG_CP_ICP_SEL(x) | BIT_REG_CP_ICP_SEL(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ -/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ +#define BIT_SHIFT_CP_ICP_SEL_4_0 4 +#define BIT_MASK_CP_ICP_SEL_4_0 0x1f +#define BIT_CP_ICP_SEL_4_0(x) \ + (((x) & BIT_MASK_CP_ICP_SEL_4_0) << BIT_SHIFT_CP_ICP_SEL_4_0) +#define BITS_CP_ICP_SEL_4_0 \ + (BIT_MASK_CP_ICP_SEL_4_0 << BIT_SHIFT_CP_ICP_SEL_4_0) +#define BIT_CLEAR_CP_ICP_SEL_4_0(x) ((x) & (~BITS_CP_ICP_SEL_4_0)) +#define BIT_GET_CP_ICP_SEL_4_0(x) \ + (((x) >> BIT_SHIFT_CP_ICP_SEL_4_0) & BIT_MASK_CP_ICP_SEL_4_0) +#define BIT_SET_CP_ICP_SEL_4_0(x, v) \ + (BIT_CLEAR_CP_ICP_SEL_4_0(x) | BIT_CP_ICP_SEL_4_0(v)) -#define BIT_WL_DSS_WIRE_SEL BIT(24) +#endif -#define BIT_SHIFT_WL_DSS_RO_SEL 20 -#define BIT_MASK_WL_DSS_RO_SEL 0x7 -#define BIT_WL_DSS_RO_SEL(x) (((x) & BIT_MASK_WL_DSS_RO_SEL) << BIT_SHIFT_WL_DSS_RO_SEL) -#define BIT_GET_WL_DSS_RO_SEL(x) (((x) >> BIT_SHIFT_WL_DSS_RO_SEL) & BIT_MASK_WL_DSS_RO_SEL) +#if (HALMAC_8822C_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ -#endif +#define BIT_SHIFT_REG_IB_PI 4 +#define BIT_MASK_REG_IB_PI 0x3 +#define BIT_REG_IB_PI(x) (((x) & BIT_MASK_REG_IB_PI) << BIT_SHIFT_REG_IB_PI) +#define BITS_REG_IB_PI (BIT_MASK_REG_IB_PI << BIT_SHIFT_REG_IB_PI) +#define BIT_CLEAR_REG_IB_PI(x) ((x) & (~BITS_REG_IB_PI)) +#define BIT_GET_REG_IB_PI(x) (((x) >> BIT_SHIFT_REG_IB_PI) & BIT_MASK_REG_IB_PI) +#define BIT_SET_REG_IB_PI(x, v) (BIT_CLEAR_REG_IB_PI(x) | BIT_REG_IB_PI(v)) +#define BIT_LDO2PWRCUT BIT(3) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ -#define BIT_MEM_BB_SD BIT(17) -#define BIT_MEM_BB_DS BIT(16) -#define BIT_MEM_BT_DS BIT(10) -#define BIT_MEM_SDIO_LS BIT(9) -#define BIT_MEM_SDIO_DS BIT(8) -#define BIT_MEM_USB_LS BIT(7) -#define BIT_MEM_USB_DS BIT(6) -#define BIT_MEM_PCI_LS BIT(5) -#define BIT_MEM_PCI_DS BIT(4) -#define BIT_MEM_WLMAC_LS BIT(3) -#define BIT_MEM_WLMAC_DS BIT(2) -#define BIT_MEM_WLMCU_LS BIT(1) +#define BIT_SHIFT_IB_PI_1_0 2 +#define BIT_MASK_IB_PI_1_0 0x3 +#define BIT_IB_PI_1_0(x) (((x) & BIT_MASK_IB_PI_1_0) << BIT_SHIFT_IB_PI_1_0) +#define BITS_IB_PI_1_0 (BIT_MASK_IB_PI_1_0 << BIT_SHIFT_IB_PI_1_0) +#define BIT_CLEAR_IB_PI_1_0(x) ((x) & (~BITS_IB_PI_1_0)) +#define BIT_GET_IB_PI_1_0(x) (((x) >> BIT_SHIFT_IB_PI_1_0) & BIT_MASK_IB_PI_1_0) +#define BIT_SET_IB_PI_1_0(x, v) (BIT_CLEAR_IB_PI_1_0(x) | BIT_IB_PI_1_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_VPULSE_LDO BIT(2) -/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WL_DSS_DATA_IN 0 -#define BIT_MASK_WL_DSS_DATA_IN 0xfffff -#define BIT_WL_DSS_DATA_IN(x) (((x) & BIT_MASK_WL_DSS_DATA_IN) << BIT_SHIFT_WL_DSS_DATA_IN) -#define BIT_GET_WL_DSS_DATA_IN(x) (((x) >> BIT_SHIFT_WL_DSS_DATA_IN) & BIT_MASK_WL_DSS_DATA_IN) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_OFFSET_PLUS BIT(1) -#endif +#define BIT_SHIFT_LDO_VSEL 0 +#define BIT_MASK_LDO_VSEL 0x3 +#define BIT_LDO_VSEL(x) (((x) & BIT_MASK_LDO_VSEL) << BIT_SHIFT_LDO_VSEL) +#define BITS_LDO_VSEL (BIT_MASK_LDO_VSEL << BIT_SHIFT_LDO_VSEL) +#define BIT_CLEAR_LDO_VSEL(x) ((x) & (~BITS_LDO_VSEL)) +#define BIT_GET_LDO_VSEL(x) (((x) >> BIT_SHIFT_LDO_VSEL) & BIT_MASK_LDO_VSEL) +#define BIT_SET_LDO_VSEL(x, v) (BIT_CLEAR_LDO_VSEL(x) | BIT_LDO_VSEL(v)) +#define BIT_RESET_N BIT(0) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ -#define BIT_MEM_WLMCU_DS BIT(0) +#define BIT_SHIFT_CKX_USB_IB_SEL 29 +#define BIT_MASK_CKX_USB_IB_SEL 0x7 +#define BIT_CKX_USB_IB_SEL(x) \ + (((x) & BIT_MASK_CKX_USB_IB_SEL) << BIT_SHIFT_CKX_USB_IB_SEL) +#define BITS_CKX_USB_IB_SEL \ + (BIT_MASK_CKX_USB_IB_SEL << BIT_SHIFT_CKX_USB_IB_SEL) +#define BIT_CLEAR_CKX_USB_IB_SEL(x) ((x) & (~BITS_CKX_USB_IB_SEL)) +#define BIT_GET_CKX_USB_IB_SEL(x) \ + (((x) >> BIT_SHIFT_CKX_USB_IB_SEL) & BIT_MASK_CKX_USB_IB_SEL) +#define BIT_SET_CKX_USB_IB_SEL(x, v) \ + (BIT_CLEAR_CKX_USB_IB_SEL(x) | BIT_CKX_USB_IB_SEL(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_REG_CK_MON_SEL 29 +#define BIT_MASK_REG_CK_MON_SEL 0x7 +#define BIT_REG_CK_MON_SEL(x) \ + (((x) & BIT_MASK_REG_CK_MON_SEL) << BIT_SHIFT_REG_CK_MON_SEL) +#define BITS_REG_CK_MON_SEL \ + (BIT_MASK_REG_CK_MON_SEL << BIT_SHIFT_REG_CK_MON_SEL) +#define BIT_CLEAR_REG_CK_MON_SEL(x) ((x) & (~BITS_REG_CK_MON_SEL)) +#define BIT_GET_REG_CK_MON_SEL(x) \ + (((x) >> BIT_SHIFT_REG_CK_MON_SEL) & BIT_MASK_REG_CK_MON_SEL) +#define BIT_SET_REG_CK_MON_SEL(x, v) \ + (BIT_CLEAR_REG_CK_MON_SEL(x) | BIT_REG_CK_MON_SEL(v)) -/* 2 REG_WL_DSS_STATUS1 (Offset 0x10DC) */ +#endif -#define BIT_WL_DSS_READY BIT(21) -#define BIT_WL_DSS_WSORT_GO BIT(20) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_PFD_DN_GATED BIT(28) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FW_DBG0 (Offset 0x10E0) */ +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_REG_CK_MON_EN BIT(28) -#define BIT_SHIFT_FW_DBG0 0 -#define BIT_MASK_FW_DBG0 0xffffffffL -#define BIT_FW_DBG0(x) (((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0) -#define BIT_GET_FW_DBG0(x) (((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FW_DBG1 (Offset 0x10E4) */ +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_PFD_UP_GATED BIT(27) -#define BIT_SHIFT_FW_DBG1 0 -#define BIT_MASK_FW_DBG1 0xffffffffL -#define BIT_FW_DBG1(x) (((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1) -#define BIT_GET_FW_DBG1(x) (((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FW_DBG2 (Offset 0x10E8) */ +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_REG_XTAL_FREQ_SEL BIT(27) -#define BIT_SHIFT_FW_DBG2 0 -#define BIT_MASK_FW_DBG2 0xffffffffL -#define BIT_FW_DBG2(x) (((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2) -#define BIT_GET_FW_DBG2(x) (((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FW_DBG3 (Offset 0x10EC) */ +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_PFD_RESET_GATED BIT(26) -#define BIT_SHIFT_FW_DBG3 0 -#define BIT_MASK_FW_DBG3 0xffffffffL -#define BIT_FW_DBG3(x) (((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3) -#define BIT_GET_FW_DBG3(x) (((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FW_DBG4 (Offset 0x10F0) */ +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_REG_XTAL_EDGE_SEL BIT(26) +#define BIT_REG_VCO_KVCO BIT(25) -#define BIT_SHIFT_FW_DBG4 0 -#define BIT_MASK_FW_DBG4 0xffffffffL -#define BIT_FW_DBG4(x) (((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4) -#define BIT_GET_FW_DBG4(x) (((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FW_DBG5 (Offset 0x10F4) */ +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_PFD_OUT_DRV_1_0 24 +#define BIT_MASK_PFD_OUT_DRV_1_0 0x3 +#define BIT_PFD_OUT_DRV_1_0(x) \ + (((x) & BIT_MASK_PFD_OUT_DRV_1_0) << BIT_SHIFT_PFD_OUT_DRV_1_0) +#define BITS_PFD_OUT_DRV_1_0 \ + (BIT_MASK_PFD_OUT_DRV_1_0 << BIT_SHIFT_PFD_OUT_DRV_1_0) +#define BIT_CLEAR_PFD_OUT_DRV_1_0(x) ((x) & (~BITS_PFD_OUT_DRV_1_0)) +#define BIT_GET_PFD_OUT_DRV_1_0(x) \ + (((x) >> BIT_SHIFT_PFD_OUT_DRV_1_0) & BIT_MASK_PFD_OUT_DRV_1_0) +#define BIT_SET_PFD_OUT_DRV_1_0(x, v) \ + (BIT_CLEAR_PFD_OUT_DRV_1_0(x) | BIT_PFD_OUT_DRV_1_0(v)) -#define BIT_SHIFT_FW_DBG5 0 -#define BIT_MASK_FW_DBG5 0xffffffffL -#define BIT_FW_DBG5(x) (((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5) -#define BIT_GET_FW_DBG5(x) (((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FW_DBG6 (Offset 0x10F8) */ +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_REG_SDM_EDGE_SEL BIT(24) +#define BIT_REG_SDM_CK_SEL BIT(23) +#define BIT_REG_SDM_CK_GATED BIT(22) +#define BIT_REG_PFD_RESET_GATED BIT(21) -#define BIT_SHIFT_FW_DBG6 0 -#define BIT_MASK_FW_DBG6 0xffffffffL -#define BIT_FW_DBG6(x) (((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6) -#define BIT_GET_FW_DBG6(x) (((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FW_DBG7 (Offset 0x10FC) */ +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_LPF_TIEMID_2_0 20 +#define BIT_MASK_LPF_TIEMID_2_0 0x7 +#define BIT_LPF_TIEMID_2_0(x) \ + (((x) & BIT_MASK_LPF_TIEMID_2_0) << BIT_SHIFT_LPF_TIEMID_2_0) +#define BITS_LPF_TIEMID_2_0 \ + (BIT_MASK_LPF_TIEMID_2_0 << BIT_SHIFT_LPF_TIEMID_2_0) +#define BIT_CLEAR_LPF_TIEMID_2_0(x) ((x) & (~BITS_LPF_TIEMID_2_0)) +#define BIT_GET_LPF_TIEMID_2_0(x) \ + (((x) >> BIT_SHIFT_LPF_TIEMID_2_0) & BIT_MASK_LPF_TIEMID_2_0) +#define BIT_SET_LPF_TIEMID_2_0(x, v) \ + (BIT_CLEAR_LPF_TIEMID_2_0(x) | BIT_LPF_TIEMID_2_0(v)) -#define BIT_SHIFT_FW_DBG7 0 -#define BIT_MASK_FW_DBG7 0xffffffffL -#define BIT_FW_DBG7(x) (((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7) -#define BIT_GET_FW_DBG7(x) (((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_CR_EXT (Offset 0x1100) */ +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_REG_LPF_R3_FAST 16 +#define BIT_MASK_REG_LPF_R3_FAST 0x1f +#define BIT_REG_LPF_R3_FAST(x) \ + (((x) & BIT_MASK_REG_LPF_R3_FAST) << BIT_SHIFT_REG_LPF_R3_FAST) +#define BITS_REG_LPF_R3_FAST \ + (BIT_MASK_REG_LPF_R3_FAST << BIT_SHIFT_REG_LPF_R3_FAST) +#define BIT_CLEAR_REG_LPF_R3_FAST(x) ((x) & (~BITS_REG_LPF_R3_FAST)) +#define BIT_GET_REG_LPF_R3_FAST(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R3_FAST) & BIT_MASK_REG_LPF_R3_FAST) +#define BIT_SET_REG_LPF_R3_FAST(x, v) \ + (BIT_CLEAR_REG_LPF_R3_FAST(x) | BIT_REG_LPF_R3_FAST(v)) -#define BIT_SHIFT_PHY_REQ_DELAY 24 -#define BIT_MASK_PHY_REQ_DELAY 0xf -#define BIT_PHY_REQ_DELAY(x) (((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY) -#define BIT_GET_PHY_REQ_DELAY(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY) +#endif -#define BIT_SPD_DOWN BIT(16) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_NETYPE4 4 -#define BIT_MASK_NETYPE4 0x3 -#define BIT_NETYPE4(x) (((x) & BIT_MASK_NETYPE4) << BIT_SHIFT_NETYPE4) -#define BIT_GET_NETYPE4(x) (((x) >> BIT_SHIFT_NETYPE4) & BIT_MASK_NETYPE4) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_LPF_R3_4_0 15 +#define BIT_MASK_LPF_R3_4_0 0x1f +#define BIT_LPF_R3_4_0(x) (((x) & BIT_MASK_LPF_R3_4_0) << BIT_SHIFT_LPF_R3_4_0) +#define BITS_LPF_R3_4_0 (BIT_MASK_LPF_R3_4_0 << BIT_SHIFT_LPF_R3_4_0) +#define BIT_CLEAR_LPF_R3_4_0(x) ((x) & (~BITS_LPF_R3_4_0)) +#define BIT_GET_LPF_R3_4_0(x) \ + (((x) >> BIT_SHIFT_LPF_R3_4_0) & BIT_MASK_LPF_R3_4_0) +#define BIT_SET_LPF_R3_4_0(x, v) (BIT_CLEAR_LPF_R3_4_0(x) | BIT_LPF_R3_4_0(v)) -#define BIT_SHIFT_NETYPE3 2 -#define BIT_MASK_NETYPE3 0x3 -#define BIT_NETYPE3(x) (((x) & BIT_MASK_NETYPE3) << BIT_SHIFT_NETYPE3) -#define BIT_GET_NETYPE3(x) (((x) >> BIT_SHIFT_NETYPE3) & BIT_MASK_NETYPE3) +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NETYPE2 0 -#define BIT_MASK_NETYPE2 0x3 -#define BIT_NETYPE2(x) (((x) & BIT_MASK_NETYPE2) << BIT_SHIFT_NETYPE2) -#define BIT_GET_NETYPE2(x) (((x) >> BIT_SHIFT_NETYPE2) & BIT_MASK_NETYPE2) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_REG_LPF_R2_FAST 11 +#define BIT_MASK_REG_LPF_R2_FAST 0x1f +#define BIT_REG_LPF_R2_FAST(x) \ + (((x) & BIT_MASK_REG_LPF_R2_FAST) << BIT_SHIFT_REG_LPF_R2_FAST) +#define BITS_REG_LPF_R2_FAST \ + (BIT_MASK_REG_LPF_R2_FAST << BIT_SHIFT_REG_LPF_R2_FAST) +#define BIT_CLEAR_REG_LPF_R2_FAST(x) ((x) & (~BITS_REG_LPF_R2_FAST)) +#define BIT_GET_REG_LPF_R2_FAST(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R2_FAST) & BIT_MASK_REG_LPF_R2_FAST) +#define BIT_SET_REG_LPF_R2_FAST(x, v) \ + (BIT_CLEAR_REG_LPF_R2_FAST(x) | BIT_REG_LPF_R2_FAST(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_LPF_R2_4_0 10 +#define BIT_MASK_LPF_R2_4_0 0x1f +#define BIT_LPF_R2_4_0(x) (((x) & BIT_MASK_LPF_R2_4_0) << BIT_SHIFT_LPF_R2_4_0) +#define BITS_LPF_R2_4_0 (BIT_MASK_LPF_R2_4_0 << BIT_SHIFT_LPF_R2_4_0) +#define BIT_CLEAR_LPF_R2_4_0(x) ((x) & (~BITS_LPF_R2_4_0)) +#define BIT_GET_LPF_R2_4_0(x) \ + (((x) >> BIT_SHIFT_LPF_R2_4_0) & BIT_MASK_LPF_R2_4_0) +#define BIT_SET_LPF_R2_4_0(x, v) (BIT_CLEAR_LPF_R2_4_0(x) | BIT_LPF_R2_4_0(v)) -/* 2 REG_FWFF (Offset 0x1114) */ +#endif + +#if (HALMAC_8822C_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ -#define BIT_SHIFT_PKTNUM_TH 24 -#define BIT_MASK_PKTNUM_TH 0xff -#define BIT_PKTNUM_TH(x) (((x) & BIT_MASK_PKTNUM_TH) << BIT_SHIFT_PKTNUM_TH) -#define BIT_GET_PKTNUM_TH(x) (((x) >> BIT_SHIFT_PKTNUM_TH) & BIT_MASK_PKTNUM_TH) +#define BIT_SHIFT_REG_LPF_C3_FAST 8 +#define BIT_MASK_REG_LPF_C3_FAST 0x7 +#define BIT_REG_LPF_C3_FAST(x) \ + (((x) & BIT_MASK_REG_LPF_C3_FAST) << BIT_SHIFT_REG_LPF_C3_FAST) +#define BITS_REG_LPF_C3_FAST \ + (BIT_MASK_REG_LPF_C3_FAST << BIT_SHIFT_REG_LPF_C3_FAST) +#define BIT_CLEAR_REG_LPF_C3_FAST(x) ((x) & (~BITS_REG_LPF_C3_FAST)) +#define BIT_GET_REG_LPF_C3_FAST(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C3_FAST) & BIT_MASK_REG_LPF_C3_FAST) +#define BIT_SET_REG_LPF_C3_FAST(x, v) \ + (BIT_CLEAR_REG_LPF_C3_FAST(x) | BIT_REG_LPF_C3_FAST(v)) +#define BIT_SHIFT_REG_LPF_C2_FAST 5 +#define BIT_MASK_REG_LPF_C2_FAST 0x7 +#define BIT_REG_LPF_C2_FAST(x) \ + (((x) & BIT_MASK_REG_LPF_C2_FAST) << BIT_SHIFT_REG_LPF_C2_FAST) +#define BITS_REG_LPF_C2_FAST \ + (BIT_MASK_REG_LPF_C2_FAST << BIT_SHIFT_REG_LPF_C2_FAST) +#define BIT_CLEAR_REG_LPF_C2_FAST(x) ((x) & (~BITS_REG_LPF_C2_FAST)) +#define BIT_GET_REG_LPF_C2_FAST(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C2_FAST) & BIT_MASK_REG_LPF_C2_FAST) +#define BIT_SET_REG_LPF_C2_FAST(x, v) \ + (BIT_CLEAR_REG_LPF_C2_FAST(x) | BIT_REG_LPF_C2_FAST(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_LPF_C3_5_0 4 +#define BIT_MASK_LPF_C3_5_0 0x3f +#define BIT_LPF_C3_5_0(x) (((x) & BIT_MASK_LPF_C3_5_0) << BIT_SHIFT_LPF_C3_5_0) +#define BITS_LPF_C3_5_0 (BIT_MASK_LPF_C3_5_0 << BIT_SHIFT_LPF_C3_5_0) +#define BIT_CLEAR_LPF_C3_5_0(x) ((x) & (~BITS_LPF_C3_5_0)) +#define BIT_GET_LPF_C3_5_0(x) \ + (((x) >> BIT_SHIFT_LPF_C3_5_0) & BIT_MASK_LPF_C3_5_0) +#define BIT_SET_LPF_C3_5_0(x, v) (BIT_CLEAR_LPF_C3_5_0(x) | BIT_LPF_C3_5_0(v)) -/* 2 REG_FWFF (Offset 0x1114) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PKTNUM_TH_V1 24 -#define BIT_MASK_PKTNUM_TH_V1 0xff -#define BIT_PKTNUM_TH_V1(x) (((x) & BIT_MASK_PKTNUM_TH_V1) << BIT_SHIFT_PKTNUM_TH_V1) -#define BIT_GET_PKTNUM_TH_V1(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1) & BIT_MASK_PKTNUM_TH_V1) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_REG_LPF_C1_FAST 2 +#define BIT_MASK_REG_LPF_C1_FAST 0x7 +#define BIT_REG_LPF_C1_FAST(x) \ + (((x) & BIT_MASK_REG_LPF_C1_FAST) << BIT_SHIFT_REG_LPF_C1_FAST) +#define BITS_REG_LPF_C1_FAST \ + (BIT_MASK_REG_LPF_C1_FAST << BIT_SHIFT_REG_LPF_C1_FAST) +#define BIT_CLEAR_REG_LPF_C1_FAST(x) ((x) & (~BITS_REG_LPF_C1_FAST)) +#define BIT_GET_REG_LPF_C1_FAST(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C1_FAST) & BIT_MASK_REG_LPF_C1_FAST) +#define BIT_SET_REG_LPF_C1_FAST(x, v) \ + (BIT_CLEAR_REG_LPF_C1_FAST(x) | BIT_REG_LPF_C1_FAST(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_LPF_C2_5_2 0 +#define BIT_MASK_LPF_C2_5_2 0xf +#define BIT_LPF_C2_5_2(x) (((x) & BIT_MASK_LPF_C2_5_2) << BIT_SHIFT_LPF_C2_5_2) +#define BITS_LPF_C2_5_2 (BIT_MASK_LPF_C2_5_2 << BIT_SHIFT_LPF_C2_5_2) +#define BIT_CLEAR_LPF_C2_5_2(x) ((x) & (~BITS_LPF_C2_5_2)) +#define BIT_GET_LPF_C2_5_2(x) \ + (((x) >> BIT_SHIFT_LPF_C2_5_2) & BIT_MASK_LPF_C2_5_2) +#define BIT_SET_LPF_C2_5_2(x, v) (BIT_CLEAR_LPF_C2_5_2(x) | BIT_LPF_C2_5_2(v)) -/* 2 REG_FWFF (Offset 0x1114) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TIMER_TH 16 -#define BIT_MASK_TIMER_TH 0xff -#define BIT_TIMER_TH(x) (((x) & BIT_MASK_TIMER_TH) << BIT_SHIFT_TIMER_TH) -#define BIT_GET_TIMER_TH(x) (((x) >> BIT_SHIFT_TIMER_TH) & BIT_MASK_TIMER_TH) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_REG_LPF_R3_V1 0 +#define BIT_MASK_REG_LPF_R3_V1 0x3 +#define BIT_REG_LPF_R3_V1(x) \ + (((x) & BIT_MASK_REG_LPF_R3_V1) << BIT_SHIFT_REG_LPF_R3_V1) +#define BITS_REG_LPF_R3_V1 (BIT_MASK_REG_LPF_R3_V1 << BIT_SHIFT_REG_LPF_R3_V1) +#define BIT_CLEAR_REG_LPF_R3_V1(x) ((x) & (~BITS_REG_LPF_R3_V1)) +#define BIT_GET_REG_LPF_R3_V1(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R3_V1) & BIT_MASK_REG_LPF_R3_V1) +#define BIT_SET_REG_LPF_R3_V1(x, v) \ + (BIT_CLEAR_REG_LPF_R3_V1(x) | BIT_REG_LPF_R3_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_CK_PHASE_SEL BIT(31) +#define BIT_CK960M_EN BIT(30) -/* 2 REG_FWFF (Offset 0x1114) */ +#endif + +#if (HALMAC_8822C_SUPPORT) -#define BIT_EN_SPD BIT(6) -#define BIT_EN_RXDMA_ALIGN_V1 BIT(1) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_SHIFT_AGPIO_DRV_V1 30 +#define BIT_MASK_AGPIO_DRV_V1 0x3 +#define BIT_AGPIO_DRV_V1(x) \ + (((x) & BIT_MASK_AGPIO_DRV_V1) << BIT_SHIFT_AGPIO_DRV_V1) +#define BITS_AGPIO_DRV_V1 (BIT_MASK_AGPIO_DRV_V1 << BIT_SHIFT_AGPIO_DRV_V1) +#define BIT_CLEAR_AGPIO_DRV_V1(x) ((x) & (~BITS_AGPIO_DRV_V1)) +#define BIT_GET_AGPIO_DRV_V1(x) \ + (((x) >> BIT_SHIFT_AGPIO_DRV_V1) & BIT_MASK_AGPIO_DRV_V1) +#define BIT_SET_AGPIO_DRV_V1(x, v) \ + (BIT_CLEAR_AGPIO_DRV_V1(x) | BIT_AGPIO_DRV_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_CK640M_EN BIT(29) -/* 2 REG_FWFF (Offset 0x1114) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXPKT1ENADDR 0 -#define BIT_MASK_RXPKT1ENADDR 0xffff -#define BIT_RXPKT1ENADDR(x) (((x) & BIT_MASK_RXPKT1ENADDR) << BIT_SHIFT_RXPKT1ENADDR) -#define BIT_GET_RXPKT1ENADDR(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR) & BIT_MASK_RXPKT1ENADDR) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_AGPIO_GPO_V1 BIT(29) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_CK240M_EN BIT(28) -/* 2 REG_FWFF (Offset 0x1114) */ +#endif -#define BIT_EN_TXDMA_ALIGN_V1 BIT(0) +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MDIO_REG_ADDR 0 -#define BIT_MASK_MDIO_REG_ADDR 0x1f -#define BIT_MDIO_REG_ADDR(x) (((x) & BIT_MASK_MDIO_REG_ADDR) << BIT_SHIFT_MDIO_REG_ADDR) -#define BIT_GET_MDIO_REG_ADDR(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR) & BIT_MASK_MDIO_REG_ADDR) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_AGPIO_GPE_V1 BIT(28) +#define BIT_SEL_CLK BIT(27) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ -/* 2 REG_FE2IMR (Offset 0x1120) */ +#define BIT_SHIFT_CK_MON_SEL_2_0 25 +#define BIT_MASK_CK_MON_SEL_2_0 0x7 +#define BIT_CK_MON_SEL_2_0(x) \ + (((x) & BIT_MASK_CK_MON_SEL_2_0) << BIT_SHIFT_CK_MON_SEL_2_0) +#define BITS_CK_MON_SEL_2_0 \ + (BIT_MASK_CK_MON_SEL_2_0 << BIT_SHIFT_CK_MON_SEL_2_0) +#define BIT_CLEAR_CK_MON_SEL_2_0(x) ((x) & (~BITS_CK_MON_SEL_2_0)) +#define BIT_GET_CK_MON_SEL_2_0(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL_2_0) & BIT_MASK_CK_MON_SEL_2_0) +#define BIT_SET_CK_MON_SEL_2_0(x, v) \ + (BIT_CLEAR_CK_MON_SEL_2_0(x) | BIT_CK_MON_SEL_2_0(v)) -#define BIT__FE4ISR__IND_MSK BIT(29) +#define BIT_CK_MON_EN_V1 BIT(24) +#define BIT_XTAL_SOURCE_SEL BIT(23) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_SHIFT_LS_XTAL_SEL 23 +#define BIT_MASK_LS_XTAL_SEL 0xf +#define BIT_LS_XTAL_SEL(x) \ + (((x) & BIT_MASK_LS_XTAL_SEL) << BIT_SHIFT_LS_XTAL_SEL) +#define BITS_LS_XTAL_SEL (BIT_MASK_LS_XTAL_SEL << BIT_SHIFT_LS_XTAL_SEL) +#define BIT_CLEAR_LS_XTAL_SEL(x) ((x) & (~BITS_LS_XTAL_SEL)) +#define BIT_GET_LS_XTAL_SEL(x) \ + (((x) >> BIT_SHIFT_LS_XTAL_SEL) & BIT_MASK_LS_XTAL_SEL) +#define BIT_SET_LS_XTAL_SEL(x, v) \ + (BIT_CLEAR_LS_XTAL_SEL(x) | BIT_LS_XTAL_SEL(v)) -/* 2 REG_FE2IMR (Offset 0x1120) */ +#endif -#define BIT_FS_TXSC_DESC_DONE_INT_EN BIT(28) -#define BIT_FS_TXSC_BKDONE_INT_EN BIT(27) -#define BIT_FS_TXSC_BEDONE_INT_EN BIT(26) -#define BIT_FS_TXSC_VIDONE_INT_EN BIT(25) -#define BIT_FS_TXSC_VODONE_INT_EN BIT(24) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_XTAL_FREQ_SEL BIT(22) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FE2IMR (Offset 0x1120) */ +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ -#define BIT_FS_ATIM_MB7_INT_EN BIT(23) -#define BIT_FS_ATIM_MB6_INT_EN BIT(22) -#define BIT_FS_ATIM_MB5_INT_EN BIT(21) -#define BIT_FS_ATIM_MB4_INT_EN BIT(20) -#define BIT_FS_ATIM_MB3_INT_EN BIT(19) -#define BIT_FS_ATIM_MB2_INT_EN BIT(18) -#define BIT_FS_ATIM_MB1_INT_EN BIT(17) -#define BIT_FS_ATIM_MB0_INT_EN BIT(16) -#define BIT_FS_TBTT4INT_EN BIT(11) -#define BIT_FS_TBTT3INT_EN BIT(10) -#define BIT_FS_TBTT2INT_EN BIT(9) -#define BIT_FS_TBTT1INT_EN BIT(8) -#define BIT_FS_TBTT0_MB7INT_EN BIT(7) -#define BIT_FS_TBTT0_MB6INT_EN BIT(6) -#define BIT_FS_TBTT0_MB5INT_EN BIT(5) -#define BIT_FS_TBTT0_MB4INT_EN BIT(4) -#define BIT_FS_TBTT0_MB3INT_EN BIT(3) -#define BIT_FS_TBTT0_MB2INT_EN BIT(2) -#define BIT_FS_TBTT0_MB1INT_EN BIT(1) -#define BIT_FS_TBTT0_INT_EN BIT(0) +#define BIT_LS_SDM_ORDER_V1 BIT(22) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_XTAL_EDGE_SEL BIT(21) -/* 2 REG_FE2ISR (Offset 0x1124) */ +#endif -#define BIT__FE4ISR__IND_INT BIT(29) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_LS_DELAY_PH BIT(21) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE2ISR (Offset 0x1124) */ +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ -#define BIT_FS_TXSC_DESC_DONE_INT BIT(28) -#define BIT_FS_TXSC_BKDONE_INT BIT(27) -#define BIT_FS_TXSC_BEDONE_INT BIT(26) -#define BIT_FS_TXSC_VIDONE_INT BIT(25) -#define BIT_FS_TXSC_VODONE_INT BIT(24) +#define BIT_XTAL_BUF_SEL BIT(20) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_DIVIDER_SEL BIT(20) -/* 2 REG_FE2ISR (Offset 0x1124) */ +#define BIT_SHIFT_PCODE 15 +#define BIT_MASK_PCODE 0x1f +#define BIT_PCODE(x) (((x) & BIT_MASK_PCODE) << BIT_SHIFT_PCODE) +#define BITS_PCODE (BIT_MASK_PCODE << BIT_SHIFT_PCODE) +#define BIT_CLEAR_PCODE(x) ((x) & (~BITS_PCODE)) +#define BIT_GET_PCODE(x) (((x) >> BIT_SHIFT_PCODE) & BIT_MASK_PCODE) +#define BIT_SET_PCODE(x, v) (BIT_CLEAR_PCODE(x) | BIT_PCODE(v)) -#define BIT_FS_ATIM_MB7_INT BIT(23) -#define BIT_FS_ATIM_MB6_INT BIT(22) -#define BIT_FS_ATIM_MB5_INT BIT(21) -#define BIT_FS_ATIM_MB4_INT BIT(20) -#define BIT_FS_ATIM_MB3_INT BIT(19) -#define BIT_FS_ATIM_MB2_INT BIT(18) -#define BIT_FS_ATIM_MB1_INT BIT(17) -#define BIT_FS_ATIM_MB0_INT BIT(16) -#define BIT_FS_TBTT4INT BIT(11) -#define BIT_FS_TBTT3INT BIT(10) -#define BIT_FS_TBTT2INT BIT(9) -#define BIT_FS_TBTT1INT BIT(8) -#define BIT_FS_TBTT0_MB7INT BIT(7) -#define BIT_FS_TBTT0_MB6INT BIT(6) -#define BIT_FS_TBTT0_MB5INT BIT(5) -#define BIT_FS_TBTT0_MB4INT BIT(4) -#define BIT_FS_TBTT0_MB3INT BIT(3) -#define BIT_FS_TBTT0_MB2INT BIT(2) -#define BIT_FS_TBTT0_MB1INT BIT(1) -#define BIT_FS_TBTT0_INT BIT(0) +#define BIT_SHIFT_NCODE 7 +#define BIT_MASK_NCODE 0xff +#define BIT_NCODE(x) (((x) & BIT_MASK_NCODE) << BIT_SHIFT_NCODE) +#define BITS_NCODE (BIT_MASK_NCODE << BIT_SHIFT_NCODE) +#define BIT_CLEAR_NCODE(x) ((x) & (~BITS_NCODE)) +#define BIT_GET_NCODE(x) (((x) >> BIT_SHIFT_NCODE) & BIT_MASK_NCODE) +#define BIT_SET_NCODE(x, v) (BIT_CLEAR_NCODE(x) | BIT_NCODE(v)) -#endif +#define BIT_REG_BEACON BIT(6) +#define BIT_REG_MBIASE BIT(5) +#endif -#if (HALMAC_8197F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ -/* 2 REG_FE3IMR (Offset 0x1128) */ +#define BIT_SHIFT_VCO_CV_7_0 4 +#define BIT_MASK_VCO_CV_7_0 0xff +#define BIT_VCO_CV_7_0(x) (((x) & BIT_MASK_VCO_CV_7_0) << BIT_SHIFT_VCO_CV_7_0) +#define BITS_VCO_CV_7_0 (BIT_MASK_VCO_CV_7_0 << BIT_SHIFT_VCO_CV_7_0) +#define BIT_CLEAR_VCO_CV_7_0(x) ((x) & (~BITS_VCO_CV_7_0)) +#define BIT_GET_VCO_CV_7_0(x) \ + (((x) >> BIT_SHIFT_VCO_CV_7_0) & BIT_MASK_VCO_CV_7_0) +#define BIT_SET_VCO_CV_7_0(x, v) (BIT_CLEAR_VCO_CV_7_0(x) | BIT_VCO_CV_7_0(v)) -#define BIT_FS_BCNELY4_AGGR_INT_EN BIT(31) +#define BIT_VCO_KVCO BIT(3) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FE3IMR (Offset 0x1128) */ +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ -#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN BIT(31) +#define BIT_SHIFT_REG_FAST_SEL 3 +#define BIT_MASK_REG_FAST_SEL 0x3 +#define BIT_REG_FAST_SEL(x) \ + (((x) & BIT_MASK_REG_FAST_SEL) << BIT_SHIFT_REG_FAST_SEL) +#define BITS_REG_FAST_SEL (BIT_MASK_REG_FAST_SEL << BIT_SHIFT_REG_FAST_SEL) +#define BIT_CLEAR_REG_FAST_SEL(x) ((x) & (~BITS_REG_FAST_SEL)) +#define BIT_GET_REG_FAST_SEL(x) \ + (((x) >> BIT_SHIFT_REG_FAST_SEL) & BIT_MASK_REG_FAST_SEL) +#define BIT_SET_REG_FAST_SEL(x, v) \ + (BIT_CLEAR_REG_FAST_SEL(x) | BIT_REG_FAST_SEL(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_SDM_EDGE_SEL BIT(2) -/* 2 REG_FE3IMR (Offset 0x1128) */ +#endif -#define BIT_FS_BCNELY3_AGGR_INT_EN BIT(30) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_REG_CK960M_EN BIT(2) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE3IMR (Offset 0x1128) */ +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ -#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN BIT(30) +#define BIT_SDM_CK_SEL BIT(1) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_REG_CK320M_EN BIT(1) -/* 2 REG_FE3IMR (Offset 0x1128) */ +#endif -#define BIT_FS_BCNELY2_AGGR_INT_EN BIT(29) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_SDM_CK_GATED BIT(0) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FE3IMR (Offset 0x1128) */ +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ -#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN BIT(29) +#define BIT_REG_CK_5M_EN BIT(0) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_3 (Offset 0x1024) */ +#define BIT_SHIFT_LCK_WAIT_CYCLE_2_0 28 +#define BIT_MASK_LCK_WAIT_CYCLE_2_0 0x7 +#define BIT_LCK_WAIT_CYCLE_2_0(x) \ + (((x) & BIT_MASK_LCK_WAIT_CYCLE_2_0) << BIT_SHIFT_LCK_WAIT_CYCLE_2_0) +#define BITS_LCK_WAIT_CYCLE_2_0 \ + (BIT_MASK_LCK_WAIT_CYCLE_2_0 << BIT_SHIFT_LCK_WAIT_CYCLE_2_0) +#define BIT_CLEAR_LCK_WAIT_CYCLE_2_0(x) ((x) & (~BITS_LCK_WAIT_CYCLE_2_0)) +#define BIT_GET_LCK_WAIT_CYCLE_2_0(x) \ + (((x) >> BIT_SHIFT_LCK_WAIT_CYCLE_2_0) & BIT_MASK_LCK_WAIT_CYCLE_2_0) +#define BIT_SET_LCK_WAIT_CYCLE_2_0(x, v) \ + (BIT_CLEAR_LCK_WAIT_CYCLE_2_0(x) | BIT_LCK_WAIT_CYCLE_2_0(v)) -/* 2 REG_FE3IMR (Offset 0x1128) */ +#define BIT_SHIFT_LCK_VCO_DIVISOR_1_0 26 +#define BIT_MASK_LCK_VCO_DIVISOR_1_0 0x3 +#define BIT_LCK_VCO_DIVISOR_1_0(x) \ + (((x) & BIT_MASK_LCK_VCO_DIVISOR_1_0) << BIT_SHIFT_LCK_VCO_DIVISOR_1_0) +#define BITS_LCK_VCO_DIVISOR_1_0 \ + (BIT_MASK_LCK_VCO_DIVISOR_1_0 << BIT_SHIFT_LCK_VCO_DIVISOR_1_0) +#define BIT_CLEAR_LCK_VCO_DIVISOR_1_0(x) ((x) & (~BITS_LCK_VCO_DIVISOR_1_0)) +#define BIT_GET_LCK_VCO_DIVISOR_1_0(x) \ + (((x) >> BIT_SHIFT_LCK_VCO_DIVISOR_1_0) & BIT_MASK_LCK_VCO_DIVISOR_1_0) +#define BIT_SET_LCK_VCO_DIVISOR_1_0(x, v) \ + (BIT_CLEAR_LCK_VCO_DIVISOR_1_0(x) | BIT_LCK_VCO_DIVISOR_1_0(v)) -#define BIT_FS_BCNELY1_AGGR_INT_EN BIT(28) +#define BIT_SHIFT_LCK_SEARCH_MODE_1_0 24 +#define BIT_MASK_LCK_SEARCH_MODE_1_0 0x3 +#define BIT_LCK_SEARCH_MODE_1_0(x) \ + (((x) & BIT_MASK_LCK_SEARCH_MODE_1_0) << BIT_SHIFT_LCK_SEARCH_MODE_1_0) +#define BITS_LCK_SEARCH_MODE_1_0 \ + (BIT_MASK_LCK_SEARCH_MODE_1_0 << BIT_SHIFT_LCK_SEARCH_MODE_1_0) +#define BIT_CLEAR_LCK_SEARCH_MODE_1_0(x) ((x) & (~BITS_LCK_SEARCH_MODE_1_0)) +#define BIT_GET_LCK_SEARCH_MODE_1_0(x) \ + (((x) >> BIT_SHIFT_LCK_SEARCH_MODE_1_0) & BIT_MASK_LCK_SEARCH_MODE_1_0) +#define BIT_SET_LCK_SEARCH_MODE_1_0(x, v) \ + (BIT_CLEAR_LCK_SEARCH_MODE_1_0(x) | BIT_LCK_SEARCH_MODE_1_0(v)) -#endif +#define BIT_SHIFT_LS_CV_OFFSET_3_0 12 +#define BIT_MASK_LS_CV_OFFSET_3_0 0xf +#define BIT_LS_CV_OFFSET_3_0(x) \ + (((x) & BIT_MASK_LS_CV_OFFSET_3_0) << BIT_SHIFT_LS_CV_OFFSET_3_0) +#define BITS_LS_CV_OFFSET_3_0 \ + (BIT_MASK_LS_CV_OFFSET_3_0 << BIT_SHIFT_LS_CV_OFFSET_3_0) +#define BIT_CLEAR_LS_CV_OFFSET_3_0(x) ((x) & (~BITS_LS_CV_OFFSET_3_0)) +#define BIT_GET_LS_CV_OFFSET_3_0(x) \ + (((x) >> BIT_SHIFT_LS_CV_OFFSET_3_0) & BIT_MASK_LS_CV_OFFSET_3_0) +#define BIT_SET_LS_CV_OFFSET_3_0(x, v) \ + (BIT_CLEAR_LS_CV_OFFSET_3_0(x) | BIT_LS_CV_OFFSET_3_0(v)) +#define BIT_LS_EN_LC_CK40M BIT(11) +#define BIT_LS__CV_MANUAL BIT(10) +#define BIT_LS_PYPASS_PI BIT(9) +#define BIT_MBIASE BIT(4) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_4 (Offset 0x1028) */ +#define BIT_LS_TIE_MID_MODE BIT(28) -/* 2 REG_FE3IMR (Offset 0x1128) */ +#define BIT_SHIFT_LS_SYNC_CYCLE_1_0 26 +#define BIT_MASK_LS_SYNC_CYCLE_1_0 0x3 +#define BIT_LS_SYNC_CYCLE_1_0(x) \ + (((x) & BIT_MASK_LS_SYNC_CYCLE_1_0) << BIT_SHIFT_LS_SYNC_CYCLE_1_0) +#define BITS_LS_SYNC_CYCLE_1_0 \ + (BIT_MASK_LS_SYNC_CYCLE_1_0 << BIT_SHIFT_LS_SYNC_CYCLE_1_0) +#define BIT_CLEAR_LS_SYNC_CYCLE_1_0(x) ((x) & (~BITS_LS_SYNC_CYCLE_1_0)) +#define BIT_GET_LS_SYNC_CYCLE_1_0(x) \ + (((x) >> BIT_SHIFT_LS_SYNC_CYCLE_1_0) & BIT_MASK_LS_SYNC_CYCLE_1_0) +#define BIT_SET_LS_SYNC_CYCLE_1_0(x, v) \ + (BIT_CLEAR_LS_SYNC_CYCLE_1_0(x) | BIT_LS_SYNC_CYCLE_1_0(v)) + +#define BIT_LS_SDM_ORDER BIT(25) +#define BIT_LS_RST_LC_CAL BIT(14) +#define BIT_LS_RSTB BIT(13) +#define BIT_LS_POW_LC_CAL_PREP BIT(11) -#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN BIT(28) +#define BIT_SHIFT_LCK_XTAL_DIVISOR_1_0 0 +#define BIT_MASK_LCK_XTAL_DIVISOR_1_0 0x3 +#define BIT_LCK_XTAL_DIVISOR_1_0(x) \ + (((x) & BIT_MASK_LCK_XTAL_DIVISOR_1_0) \ + << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0) +#define BITS_LCK_XTAL_DIVISOR_1_0 \ + (BIT_MASK_LCK_XTAL_DIVISOR_1_0 << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0) +#define BIT_CLEAR_LCK_XTAL_DIVISOR_1_0(x) ((x) & (~BITS_LCK_XTAL_DIVISOR_1_0)) +#define BIT_GET_LCK_XTAL_DIVISOR_1_0(x) \ + (((x) >> BIT_SHIFT_LCK_XTAL_DIVISOR_1_0) & \ + BIT_MASK_LCK_XTAL_DIVISOR_1_0) +#define BIT_SET_LCK_XTAL_DIVISOR_1_0(x, v) \ + (BIT_CLEAR_LCK_XTAL_DIVISOR_1_0(x) | BIT_LCK_XTAL_DIVISOR_1_0(v)) + +/* 2 REG_ANAPAR_MAC_5 (Offset 0x102C) */ + +#define BIT_SHIFT_LS_XTAL_SEL_3_0 0 +#define BIT_MASK_LS_XTAL_SEL_3_0 0xf +#define BIT_LS_XTAL_SEL_3_0(x) \ + (((x) & BIT_MASK_LS_XTAL_SEL_3_0) << BIT_SHIFT_LS_XTAL_SEL_3_0) +#define BITS_LS_XTAL_SEL_3_0 \ + (BIT_MASK_LS_XTAL_SEL_3_0 << BIT_SHIFT_LS_XTAL_SEL_3_0) +#define BIT_CLEAR_LS_XTAL_SEL_3_0(x) ((x) & (~BITS_LS_XTAL_SEL_3_0)) +#define BIT_GET_LS_XTAL_SEL_3_0(x) \ + (((x) >> BIT_SHIFT_LS_XTAL_SEL_3_0) & BIT_MASK_LS_XTAL_SEL_3_0) +#define BIT_SET_LS_XTAL_SEL_3_0(x, v) \ + (BIT_CLEAR_LS_XTAL_SEL_3_0(x) | BIT_LS_XTAL_SEL_3_0(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_CFG4 (Offset 0x1034) */ +#define BIT_EF_CSER_1 BIT(26) +#define BIT_SW_PG_EN_1 BIT(10) -/* 2 REG_FE3IMR (Offset 0x1128) */ +#endif -#define BIT_FS_BCNDMA4_INT_EN BIT(27) -#define BIT_FS_BCNDMA3_INT_EN BIT(26) -#define BIT_FS_BCNDMA2_INT_EN BIT(25) -#define BIT_FS_BCNDMA1_INT_EN BIT(24) -#define BIT_FS_BCNDMA0_MB7_INT_EN BIT(23) -#define BIT_FS_BCNDMA0_MB6_INT_EN BIT(22) -#define BIT_FS_BCNDMA0_MB5_INT_EN BIT(21) -#define BIT_FS_BCNDMA0_MB4_INT_EN BIT(20) -#define BIT_FS_BCNDMA0_MB3_INT_EN BIT(19) -#define BIT_FS_BCNDMA0_MB2_INT_EN BIT(18) -#define BIT_FS_BCNDMA0_MB1_INT_EN BIT(17) -#define BIT_FS_BCNDMA0_INT_EN BIT(16) -#define BIT_FS_MTI_BCNIVLEAR_INT__EN BIT(15) -#define BIT_FS_BCNERLY4_INT_EN BIT(11) -#define BIT_FS_BCNERLY3_INT_EN BIT(10) -#define BIT_FS_BCNERLY2_INT_EN BIT(9) -#define BIT_FS_BCNERLY1_INT_EN BIT(8) -#define BIT_FS_BCNERLY0_MB7INT_EN BIT(7) -#define BIT_FS_BCNERLY0_MB6INT_EN BIT(6) -#define BIT_FS_BCNERLY0_MB5INT_EN BIT(5) -#define BIT_FS_BCNERLY0_MB4INT_EN BIT(4) -#define BIT_FS_BCNERLY0_MB3INT_EN BIT(3) -#define BIT_FS_BCNERLY0_MB2INT_EN BIT(2) -#define BIT_FS_BCNERLY0_MB1INT_EN BIT(1) -#define BIT_FS_BCNERLY0_INT_EN BIT(0) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ +#define BIT_XTAL_DRV_RF1_0 BIT(31) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FE3ISR (Offset 0x112C) */ +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ -#define BIT_FS_BCNELY4_AGGR_INT BIT(31) +#define BIT_XTAL_SC_LPS BIT(31) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ +#define BIT_XTAL_GATED_RF1N BIT(30) +#define BIT_XTAL_GATED_RF1P BIT(29) +#define BIT_XTAL_GM_SEP_V2 BIT(28) -/* 2 REG_FE3ISR (Offset 0x112C) */ +#define BIT_SHIFT_XTAL_LDO_1_0 26 +#define BIT_MASK_XTAL_LDO_1_0 0x3 +#define BIT_XTAL_LDO_1_0(x) \ + (((x) & BIT_MASK_XTAL_LDO_1_0) << BIT_SHIFT_XTAL_LDO_1_0) +#define BITS_XTAL_LDO_1_0 (BIT_MASK_XTAL_LDO_1_0 << BIT_SHIFT_XTAL_LDO_1_0) +#define BIT_CLEAR_XTAL_LDO_1_0(x) ((x) & (~BITS_XTAL_LDO_1_0)) +#define BIT_GET_XTAL_LDO_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_1_0) & BIT_MASK_XTAL_LDO_1_0) +#define BIT_SET_XTAL_LDO_1_0(x, v) \ + (BIT_CLEAR_XTAL_LDO_1_0(x) | BIT_XTAL_LDO_1_0(v)) -#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT BIT(31) +#define BIT_XQSEL_V1 BIT(25) +#define BIT_GATED_XTAL_OK0 BIT(24) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ +#define BIT_SHIFT_XTAL_SC_INIT 24 +#define BIT_MASK_XTAL_SC_INIT 0x7f +#define BIT_XTAL_SC_INIT(x) \ + (((x) & BIT_MASK_XTAL_SC_INIT) << BIT_SHIFT_XTAL_SC_INIT) +#define BITS_XTAL_SC_INIT (BIT_MASK_XTAL_SC_INIT << BIT_SHIFT_XTAL_SC_INIT) +#define BIT_CLEAR_XTAL_SC_INIT(x) ((x) & (~BITS_XTAL_SC_INIT)) +#define BIT_GET_XTAL_SC_INIT(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_INIT) & BIT_MASK_XTAL_SC_INIT) +#define BIT_SET_XTAL_SC_INIT(x, v) \ + (BIT_CLEAR_XTAL_SC_INIT(x) | BIT_XTAL_SC_INIT(v)) -/* 2 REG_FE3ISR (Offset 0x112C) */ +#endif -#define BIT_FS_BCNELY3_AGGR_INT BIT(30) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ +#define BIT_SHIFT_XTAL_SC_XO_6_0 17 +#define BIT_MASK_XTAL_SC_XO_6_0 0x7f +#define BIT_XTAL_SC_XO_6_0(x) \ + (((x) & BIT_MASK_XTAL_SC_XO_6_0) << BIT_SHIFT_XTAL_SC_XO_6_0) +#define BITS_XTAL_SC_XO_6_0 \ + (BIT_MASK_XTAL_SC_XO_6_0 << BIT_SHIFT_XTAL_SC_XO_6_0) +#define BIT_CLEAR_XTAL_SC_XO_6_0(x) ((x) & (~BITS_XTAL_SC_XO_6_0)) +#define BIT_GET_XTAL_SC_XO_6_0(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XO_6_0) & BIT_MASK_XTAL_SC_XO_6_0) +#define BIT_SET_XTAL_SC_XO_6_0(x, v) \ + (BIT_CLEAR_XTAL_SC_XO_6_0(x) | BIT_XTAL_SC_XO_6_0(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FE3ISR (Offset 0x112C) */ +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ -#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT BIT(30) +#define BIT_SHIFT_XTAL_SC_XO 17 +#define BIT_MASK_XTAL_SC_XO 0x7f +#define BIT_XTAL_SC_XO(x) (((x) & BIT_MASK_XTAL_SC_XO) << BIT_SHIFT_XTAL_SC_XO) +#define BITS_XTAL_SC_XO (BIT_MASK_XTAL_SC_XO << BIT_SHIFT_XTAL_SC_XO) +#define BIT_CLEAR_XTAL_SC_XO(x) ((x) & (~BITS_XTAL_SC_XO)) +#define BIT_GET_XTAL_SC_XO(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XO) & BIT_MASK_XTAL_SC_XO) +#define BIT_SET_XTAL_SC_XO(x, v) (BIT_CLEAR_XTAL_SC_XO(x) | BIT_XTAL_SC_XO(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ +#define BIT_SHIFT_XTAL_SC_XI_6_0 10 +#define BIT_MASK_XTAL_SC_XI_6_0 0x7f +#define BIT_XTAL_SC_XI_6_0(x) \ + (((x) & BIT_MASK_XTAL_SC_XI_6_0) << BIT_SHIFT_XTAL_SC_XI_6_0) +#define BITS_XTAL_SC_XI_6_0 \ + (BIT_MASK_XTAL_SC_XI_6_0 << BIT_SHIFT_XTAL_SC_XI_6_0) +#define BIT_CLEAR_XTAL_SC_XI_6_0(x) ((x) & (~BITS_XTAL_SC_XI_6_0)) +#define BIT_GET_XTAL_SC_XI_6_0(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XI_6_0) & BIT_MASK_XTAL_SC_XI_6_0) +#define BIT_SET_XTAL_SC_XI_6_0(x, v) \ + (BIT_CLEAR_XTAL_SC_XI_6_0(x) | BIT_XTAL_SC_XI_6_0(v)) -/* 2 REG_FE3ISR (Offset 0x112C) */ +#endif -#define BIT_FS_BCNELY2_AGGR_INT BIT(29) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ +#define BIT_SHIFT_XTAL_SC_XI 10 +#define BIT_MASK_XTAL_SC_XI 0x7f +#define BIT_XTAL_SC_XI(x) (((x) & BIT_MASK_XTAL_SC_XI) << BIT_SHIFT_XTAL_SC_XI) +#define BITS_XTAL_SC_XI (BIT_MASK_XTAL_SC_XI << BIT_SHIFT_XTAL_SC_XI) +#define BIT_CLEAR_XTAL_SC_XI(x) ((x) & (~BITS_XTAL_SC_XI)) +#define BIT_GET_XTAL_SC_XI(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XI) & BIT_MASK_XTAL_SC_XI) +#define BIT_SET_XTAL_SC_XI(x, v) (BIT_CLEAR_XTAL_SC_XI(x) | BIT_XTAL_SC_XI(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE3ISR (Offset 0x112C) */ +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ -#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT BIT(29) +#define BIT_SHIFT_XTAL_GMN_4_0 5 +#define BIT_MASK_XTAL_GMN_4_0 0x1f +#define BIT_XTAL_GMN_4_0(x) \ + (((x) & BIT_MASK_XTAL_GMN_4_0) << BIT_SHIFT_XTAL_GMN_4_0) +#define BITS_XTAL_GMN_4_0 (BIT_MASK_XTAL_GMN_4_0 << BIT_SHIFT_XTAL_GMN_4_0) +#define BIT_CLEAR_XTAL_GMN_4_0(x) ((x) & (~BITS_XTAL_GMN_4_0)) +#define BIT_GET_XTAL_GMN_4_0(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_4_0) & BIT_MASK_XTAL_GMN_4_0) +#define BIT_SET_XTAL_GMN_4_0(x, v) \ + (BIT_CLEAR_XTAL_GMN_4_0(x) | BIT_XTAL_GMN_4_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ +#define BIT_SHIFT_XTAL_GMN_V3 5 +#define BIT_MASK_XTAL_GMN_V3 0x1f +#define BIT_XTAL_GMN_V3(x) \ + (((x) & BIT_MASK_XTAL_GMN_V3) << BIT_SHIFT_XTAL_GMN_V3) +#define BITS_XTAL_GMN_V3 (BIT_MASK_XTAL_GMN_V3 << BIT_SHIFT_XTAL_GMN_V3) +#define BIT_CLEAR_XTAL_GMN_V3(x) ((x) & (~BITS_XTAL_GMN_V3)) +#define BIT_GET_XTAL_GMN_V3(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V3) & BIT_MASK_XTAL_GMN_V3) +#define BIT_SET_XTAL_GMN_V3(x, v) \ + (BIT_CLEAR_XTAL_GMN_V3(x) | BIT_XTAL_GMN_V3(v)) -/* 2 REG_FE3ISR (Offset 0x112C) */ +#endif + +#if (HALMAC_8814B_SUPPORT) -#define BIT_FS_BCNELY1_AGGR_INT BIT(28) +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_SHIFT_XTAL_GMP_4_0 0 +#define BIT_MASK_XTAL_GMP_4_0 0x1f +#define BIT_XTAL_GMP_4_0(x) \ + (((x) & BIT_MASK_XTAL_GMP_4_0) << BIT_SHIFT_XTAL_GMP_4_0) +#define BITS_XTAL_GMP_4_0 (BIT_MASK_XTAL_GMP_4_0 << BIT_SHIFT_XTAL_GMP_4_0) +#define BIT_CLEAR_XTAL_GMP_4_0(x) ((x) & (~BITS_XTAL_GMP_4_0)) +#define BIT_GET_XTAL_GMP_4_0(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_4_0) & BIT_MASK_XTAL_GMP_4_0) +#define BIT_SET_XTAL_GMP_4_0(x, v) \ + (BIT_CLEAR_XTAL_GMP_4_0(x) | BIT_XTAL_GMP_4_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ +#define BIT_SHIFT_XTAL_GMP_V3 0 +#define BIT_MASK_XTAL_GMP_V3 0x1f +#define BIT_XTAL_GMP_V3(x) \ + (((x) & BIT_MASK_XTAL_GMP_V3) << BIT_SHIFT_XTAL_GMP_V3) +#define BITS_XTAL_GMP_V3 (BIT_MASK_XTAL_GMP_V3 << BIT_SHIFT_XTAL_GMP_V3) +#define BIT_CLEAR_XTAL_GMP_V3(x) ((x) & (~BITS_XTAL_GMP_V3)) +#define BIT_GET_XTAL_GMP_V3(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V3) & BIT_MASK_XTAL_GMP_V3) +#define BIT_SET_XTAL_GMP_V3(x, v) \ + (BIT_CLEAR_XTAL_GMP_V3(x) | BIT_XTAL_GMP_V3(v)) -/* 2 REG_FE3ISR (Offset 0x112C) */ +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT BIT(28) +#define BIT_XTAL_SEL_TOK_V1 BIT(31) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_SHIFT_XTAL_LDO_OK_1_0 30 +#define BIT_MASK_XTAL_LDO_OK_1_0 0x3 +#define BIT_XTAL_LDO_OK_1_0(x) \ + (((x) & BIT_MASK_XTAL_LDO_OK_1_0) << BIT_SHIFT_XTAL_LDO_OK_1_0) +#define BITS_XTAL_LDO_OK_1_0 \ + (BIT_MASK_XTAL_LDO_OK_1_0 << BIT_SHIFT_XTAL_LDO_OK_1_0) +#define BIT_CLEAR_XTAL_LDO_OK_1_0(x) ((x) & (~BITS_XTAL_LDO_OK_1_0)) +#define BIT_GET_XTAL_LDO_OK_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_OK_1_0) & BIT_MASK_XTAL_LDO_OK_1_0) +#define BIT_SET_XTAL_LDO_OK_1_0(x, v) \ + (BIT_CLEAR_XTAL_LDO_OK_1_0(x) | BIT_XTAL_LDO_OK_1_0(v)) -/* 2 REG_FE3ISR (Offset 0x112C) */ +#endif -#define BIT_FS_BCNDMA4_INT BIT(27) -#define BIT_FS_BCNDMA3_INT BIT(26) -#define BIT_FS_BCNDMA2_INT BIT(25) -#define BIT_FS_BCNDMA1_INT BIT(24) -#define BIT_FS_BCNDMA0_MB7_INT BIT(23) -#define BIT_FS_BCNDMA0_MB6_INT BIT(22) -#define BIT_FS_BCNDMA0_MB5_INT BIT(21) -#define BIT_FS_BCNDMA0_MB4_INT BIT(20) -#define BIT_FS_BCNDMA0_MB3_INT BIT(19) -#define BIT_FS_BCNDMA0_MB2_INT BIT(18) -#define BIT_FS_BCNDMA0_MB1_INT BIT(17) -#define BIT_FS_BCNDMA0_INT BIT(16) -#define BIT_FS_MTI_BCNIVLEAR_INT BIT(15) -#define BIT_FS_BCNERLY4_INT BIT(11) -#define BIT_FS_BCNERLY3_INT BIT(10) -#define BIT_FS_BCNERLY2_INT BIT(9) -#define BIT_FS_BCNERLY1_INT BIT(8) -#define BIT_FS_BCNERLY0_MB7INT BIT(7) -#define BIT_FS_BCNERLY0_MB6INT BIT(6) -#define BIT_FS_BCNERLY0_MB5INT BIT(5) -#define BIT_FS_BCNERLY0_MB4INT BIT(4) -#define BIT_FS_BCNERLY0_MB3INT BIT(3) -#define BIT_FS_BCNERLY0_MB2INT BIT(2) -#define BIT_FS_BCNERLY0_MB1INT BIT(1) -#define BIT_FS_BCNERLY0_INT BIT(0) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_XTAL_DELAY_DIGI_V2 BIT(30) +#define BIT_XTAL_DELAY_USB_V2 BIT(29) +#define BIT_XTAL_DELAY_AFE_V2 BIT(28) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -#define BIT_PORT4_PKTIN_INT_EN BIT(19) +#define BIT_SHIFT_XTAL_XORES_SEL_2_0 27 +#define BIT_MASK_XTAL_XORES_SEL_2_0 0x7 +#define BIT_XTAL_XORES_SEL_2_0(x) \ + (((x) & BIT_MASK_XTAL_XORES_SEL_2_0) << BIT_SHIFT_XTAL_XORES_SEL_2_0) +#define BITS_XTAL_XORES_SEL_2_0 \ + (BIT_MASK_XTAL_XORES_SEL_2_0 << BIT_SHIFT_XTAL_XORES_SEL_2_0) +#define BIT_CLEAR_XTAL_XORES_SEL_2_0(x) ((x) & (~BITS_XTAL_XORES_SEL_2_0)) +#define BIT_GET_XTAL_XORES_SEL_2_0(x) \ + (((x) >> BIT_SHIFT_XTAL_XORES_SEL_2_0) & BIT_MASK_XTAL_XORES_SEL_2_0) +#define BIT_SET_XTAL_XORES_SEL_2_0(x, v) \ + (BIT_CLEAR_XTAL_XORES_SEL_2_0(x) | BIT_XTAL_XORES_SEL_2_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_SHIFT_XTAL_DRV_DIGI_V2 26 +#define BIT_MASK_XTAL_DRV_DIGI_V2 0x3 +#define BIT_XTAL_DRV_DIGI_V2(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_V2) << BIT_SHIFT_XTAL_DRV_DIGI_V2) +#define BITS_XTAL_DRV_DIGI_V2 \ + (BIT_MASK_XTAL_DRV_DIGI_V2 << BIT_SHIFT_XTAL_DRV_DIGI_V2) +#define BIT_CLEAR_XTAL_DRV_DIGI_V2(x) ((x) & (~BITS_XTAL_DRV_DIGI_V2)) +#define BIT_GET_XTAL_DRV_DIGI_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_V2) & BIT_MASK_XTAL_DRV_DIGI_V2) +#define BIT_SET_XTAL_DRV_DIGI_V2(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_V2(x) | BIT_XTAL_DRV_DIGI_V2(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_FS_CLI3_TXPKTIN_INT_EN BIT(19) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_SHIFT_XTAL_AAC_PK_SEL_1_0 25 +#define BIT_MASK_XTAL_AAC_PK_SEL_1_0 0x3 +#define BIT_XTAL_AAC_PK_SEL_1_0(x) \ + (((x) & BIT_MASK_XTAL_AAC_PK_SEL_1_0) << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0) +#define BITS_XTAL_AAC_PK_SEL_1_0 \ + (BIT_MASK_XTAL_AAC_PK_SEL_1_0 << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0) +#define BIT_CLEAR_XTAL_AAC_PK_SEL_1_0(x) ((x) & (~BITS_XTAL_AAC_PK_SEL_1_0)) +#define BIT_GET_XTAL_AAC_PK_SEL_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_AAC_PK_SEL_1_0) & BIT_MASK_XTAL_AAC_PK_SEL_1_0) +#define BIT_SET_XTAL_AAC_PK_SEL_1_0(x, v) \ + (BIT_CLEAR_XTAL_AAC_PK_SEL_1_0(x) | BIT_XTAL_AAC_PK_SEL_1_0(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -#define BIT_PORT3_PKTIN_INT_EN BIT(18) +#define BIT_EN_XTAL_DRV_LPS BIT(25) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_EN_XTAL_AAC_PKDET BIT(24) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_FS_CLI2_TXPKTIN_INT_EN BIT(18) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_EN_XTAL_DRV_DIGI_V2 BIT(24) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -#define BIT_PORT2_PKTIN_INT_EN BIT(17) +#define BIT_EN_XTAL_AAC_GM BIT(23) +#define BIT_XTAL_LPMODE BIT(22) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -/* 2 REG_FE4IMR (Offset 0x1130) */ +#define BIT_SHIFT_XTAL_DRV_USB 22 +#define BIT_MASK_XTAL_DRV_USB 0x3 +#define BIT_XTAL_DRV_USB(x) \ + (((x) & BIT_MASK_XTAL_DRV_USB) << BIT_SHIFT_XTAL_DRV_USB) +#define BITS_XTAL_DRV_USB (BIT_MASK_XTAL_DRV_USB << BIT_SHIFT_XTAL_DRV_USB) +#define BIT_CLEAR_XTAL_DRV_USB(x) ((x) & (~BITS_XTAL_DRV_USB)) +#define BIT_GET_XTAL_DRV_USB(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_USB) & BIT_MASK_XTAL_DRV_USB) +#define BIT_SET_XTAL_DRV_USB(x, v) \ + (BIT_CLEAR_XTAL_DRV_USB(x) | BIT_XTAL_DRV_USB(v)) -#define BIT_FS_CLI1_TXPKTIN_INT_EN BIT(17) +#define BIT_EN_XTAL_DRV_USB BIT(21) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -#define BIT_PORT1_PKTIN_INT_EN BIT(16) +#define BIT_SHIFT_XTAL_SEL_TOK_2_0 19 +#define BIT_MASK_XTAL_SEL_TOK_2_0 0x7 +#define BIT_XTAL_SEL_TOK_2_0(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_2_0) << BIT_SHIFT_XTAL_SEL_TOK_2_0) +#define BITS_XTAL_SEL_TOK_2_0 \ + (BIT_MASK_XTAL_SEL_TOK_2_0 << BIT_SHIFT_XTAL_SEL_TOK_2_0) +#define BIT_CLEAR_XTAL_SEL_TOK_2_0(x) ((x) & (~BITS_XTAL_SEL_TOK_2_0)) +#define BIT_GET_XTAL_SEL_TOK_2_0(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_2_0) & BIT_MASK_XTAL_SEL_TOK_2_0) +#define BIT_SET_XTAL_SEL_TOK_2_0(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_2_0(x) | BIT_XTAL_SEL_TOK_2_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -#define BIT_FS_CLI0_TXPKTIN_INT_EN BIT(16) +#define BIT_SHIFT_XTAL_DRV_AFE_V2 19 +#define BIT_MASK_XTAL_DRV_AFE_V2 0x3 +#define BIT_XTAL_DRV_AFE_V2(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_V2) << BIT_SHIFT_XTAL_DRV_AFE_V2) +#define BITS_XTAL_DRV_AFE_V2 \ + (BIT_MASK_XTAL_DRV_AFE_V2 << BIT_SHIFT_XTAL_DRV_AFE_V2) +#define BIT_CLEAR_XTAL_DRV_AFE_V2(x) ((x) & (~BITS_XTAL_DRV_AFE_V2)) +#define BIT_GET_XTAL_DRV_AFE_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_V2) & BIT_MASK_XTAL_DRV_AFE_V2) +#define BIT_SET_XTAL_DRV_AFE_V2(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_V2(x) | BIT_XTAL_DRV_AFE_V2(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_XQSEL_RF_AWAKE_V2 BIT(18) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT4_RXUCMD0_OK_INT_EN BIT(15) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_EN_XTAL_DRV_AFE BIT(18) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -#define BIT_FS_CLI3_RX_UMD0_INT_EN BIT(15) +#define BIT_XQSEL_RF_INITIAL_V2 BIT(17) +#define BIT_XTAL_DELAY_USB_V1 BIT(16) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_SHIFT_XTAL_DRV_RF2_V2 16 +#define BIT_MASK_XTAL_DRV_RF2_V2 0x3 +#define BIT_XTAL_DRV_RF2_V2(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_V2) << BIT_SHIFT_XTAL_DRV_RF2_V2) +#define BITS_XTAL_DRV_RF2_V2 \ + (BIT_MASK_XTAL_DRV_RF2_V2 << BIT_SHIFT_XTAL_DRV_RF2_V2) +#define BIT_CLEAR_XTAL_DRV_RF2_V2(x) ((x) & (~BITS_XTAL_DRV_RF2_V2)) +#define BIT_GET_XTAL_DRV_RF2_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_V2) & BIT_MASK_XTAL_DRV_RF2_V2) +#define BIT_SET_XTAL_DRV_RF2_V2(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_V2(x) | BIT_XTAL_DRV_RF2_V2(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT4_RXUCMD1_OK_INT_EN BIT(14) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_XTAL_DELAY_DIGI_V1 BIT(15) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -#define BIT_FS_CLI3_RX_UMD1_INT_EN BIT(14) +#define BIT_EN_XTAL_DRV_RF2 BIT(15) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_XTAL_DELAY_AFE_V1 BIT(14) +#define BIT_XTAL_DRV_RF_LATCH_V3 BIT(13) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT4_RXBCMD0_OK_INT_EN BIT(13) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_EN_XTAL_DRV_RF1 BIT(12) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -#define BIT_FS_CLI3_RX_BMD0_INT_EN BIT(13) +#define BIT_SHIFT_XTAL_DRV_DIGI_1_0 11 +#define BIT_MASK_XTAL_DRV_DIGI_1_0 0x3 +#define BIT_XTAL_DRV_DIGI_1_0(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_1_0) << BIT_SHIFT_XTAL_DRV_DIGI_1_0) +#define BITS_XTAL_DRV_DIGI_1_0 \ + (BIT_MASK_XTAL_DRV_DIGI_1_0 << BIT_SHIFT_XTAL_DRV_DIGI_1_0) +#define BIT_CLEAR_XTAL_DRV_DIGI_1_0(x) ((x) & (~BITS_XTAL_DRV_DIGI_1_0)) +#define BIT_GET_XTAL_DRV_DIGI_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_1_0) & BIT_MASK_XTAL_DRV_DIGI_1_0) +#define BIT_SET_XTAL_DRV_DIGI_1_0(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_1_0(x) | BIT_XTAL_DRV_DIGI_1_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_XTAL_DRV_RF_LATCH_V4 BIT(11) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT4_RXBCMD1_OK_INT_EN BIT(12) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_XTAL_GATED_DIGIN BIT(10) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -#define BIT_FS_CLI3_RX_BMD1_INT_EN BIT(12) +#define BIT_XTAL_GM_SEP_V3 BIT(10) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_XTAL_GATED_DIGIP BIT(9) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT3_RXUCMD0_OK_INT_EN BIT(11) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_XQSEL_RF_AWAKE_V3 BIT(9) +#define BIT_XQSEL_RF_INITIAL_V3 BIT(8) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -#define BIT_FS_CLI2_RX_UMD0_INT_EN BIT(11) +#define BIT_SHIFT_XTAL_DRV_USB_1_0 7 +#define BIT_MASK_XTAL_DRV_USB_1_0 0x3 +#define BIT_XTAL_DRV_USB_1_0(x) \ + (((x) & BIT_MASK_XTAL_DRV_USB_1_0) << BIT_SHIFT_XTAL_DRV_USB_1_0) +#define BITS_XTAL_DRV_USB_1_0 \ + (BIT_MASK_XTAL_DRV_USB_1_0 << BIT_SHIFT_XTAL_DRV_USB_1_0) +#define BIT_CLEAR_XTAL_DRV_USB_1_0(x) ((x) & (~BITS_XTAL_DRV_USB_1_0)) +#define BIT_GET_XTAL_DRV_USB_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_USB_1_0) & BIT_MASK_XTAL_DRV_USB_1_0) +#define BIT_SET_XTAL_DRV_USB_1_0(x, v) \ + (BIT_CLEAR_XTAL_DRV_USB_1_0(x) | BIT_XTAL_DRV_USB_1_0(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_XQSEL_V2 BIT(7) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT3_RXUCMD1_OK_INT_EN BIT(10) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_XTAL_GATED_USBN BIT(6) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ -#define BIT_FS_CLI2_RX_UMD1_INT_EN BIT(10) +#define BIT_GATED_XTAL_OK0_V2 BIT(6) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_XTAL_GATED_USBP BIT(5) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#define BIT_SHIFT_XTAL_DRV_AFE_1_0 3 +#define BIT_MASK_XTAL_DRV_AFE_1_0 0x3 +#define BIT_XTAL_DRV_AFE_1_0(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_1_0) << BIT_SHIFT_XTAL_DRV_AFE_1_0) +#define BITS_XTAL_DRV_AFE_1_0 \ + (BIT_MASK_XTAL_DRV_AFE_1_0 << BIT_SHIFT_XTAL_DRV_AFE_1_0) +#define BIT_CLEAR_XTAL_DRV_AFE_1_0(x) ((x) & (~BITS_XTAL_DRV_AFE_1_0)) +#define BIT_GET_XTAL_DRV_AFE_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_1_0) & BIT_MASK_XTAL_DRV_AFE_1_0) +#define BIT_SET_XTAL_DRV_AFE_1_0(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_1_0(x) | BIT_XTAL_DRV_AFE_1_0(v)) -#define BIT_PORT3_RXBCMD0_OK_INT_EN BIT(9) +#define BIT_XTAL_GATED_AFEN BIT(2) +#define BIT_XTAL_GATED_AFEP BIT(1) +#define BIT_XTAL_DRV_RF1_1 BIT(0) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ +#define BIT_SHIFT_XTAL_SC_LPS_V2 0 +#define BIT_MASK_XTAL_SC_LPS_V2 0x3f +#define BIT_XTAL_SC_LPS_V2(x) \ + (((x) & BIT_MASK_XTAL_SC_LPS_V2) << BIT_SHIFT_XTAL_SC_LPS_V2) +#define BITS_XTAL_SC_LPS_V2 \ + (BIT_MASK_XTAL_SC_LPS_V2 << BIT_SHIFT_XTAL_SC_LPS_V2) +#define BIT_CLEAR_XTAL_SC_LPS_V2(x) ((x) & (~BITS_XTAL_SC_LPS_V2)) +#define BIT_GET_XTAL_SC_LPS_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_LPS_V2) & BIT_MASK_XTAL_SC_LPS_V2) +#define BIT_SET_XTAL_SC_LPS_V2(x, v) \ + (BIT_CLEAR_XTAL_SC_LPS_V2(x) | BIT_XTAL_SC_LPS_V2(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ -#define BIT_FS_CLI2_RX_BMD0_INT_EN BIT(9) +#define BIT_XTAL_AAC_CAP BIT(31) -#endif +#define BIT_SHIFT_XTAL_PDSW 29 +#define BIT_MASK_XTAL_PDSW 0x3 +#define BIT_XTAL_PDSW(x) (((x) & BIT_MASK_XTAL_PDSW) << BIT_SHIFT_XTAL_PDSW) +#define BITS_XTAL_PDSW (BIT_MASK_XTAL_PDSW << BIT_SHIFT_XTAL_PDSW) +#define BIT_CLEAR_XTAL_PDSW(x) ((x) & (~BITS_XTAL_PDSW)) +#define BIT_GET_XTAL_PDSW(x) (((x) >> BIT_SHIFT_XTAL_PDSW) & BIT_MASK_XTAL_PDSW) +#define BIT_SET_XTAL_PDSW(x, v) (BIT_CLEAR_XTAL_PDSW(x) | BIT_XTAL_PDSW(v)) +#define BIT_SHIFT_XTAL_LPS_BUF_VB 27 +#define BIT_MASK_XTAL_LPS_BUF_VB 0x3 +#define BIT_XTAL_LPS_BUF_VB(x) \ + (((x) & BIT_MASK_XTAL_LPS_BUF_VB) << BIT_SHIFT_XTAL_LPS_BUF_VB) +#define BITS_XTAL_LPS_BUF_VB \ + (BIT_MASK_XTAL_LPS_BUF_VB << BIT_SHIFT_XTAL_LPS_BUF_VB) +#define BIT_CLEAR_XTAL_LPS_BUF_VB(x) ((x) & (~BITS_XTAL_LPS_BUF_VB)) +#define BIT_GET_XTAL_LPS_BUF_VB(x) \ + (((x) >> BIT_SHIFT_XTAL_LPS_BUF_VB) & BIT_MASK_XTAL_LPS_BUF_VB) +#define BIT_SET_XTAL_LPS_BUF_VB(x, v) \ + (BIT_CLEAR_XTAL_LPS_BUF_VB(x) | BIT_XTAL_LPS_BUF_VB(v)) -#if (HALMAC_8197F_SUPPORT) +#define BIT_XTAL_PDCK_MANU BIT(26) +#define BIT_XTAL_PDCK_OK_MANU BIT(25) +#define BIT_SHIFT_XTAL_VREF_SEL 20 +#define BIT_MASK_XTAL_VREF_SEL 0x1f +#define BIT_XTAL_VREF_SEL(x) \ + (((x) & BIT_MASK_XTAL_VREF_SEL) << BIT_SHIFT_XTAL_VREF_SEL) +#define BITS_XTAL_VREF_SEL (BIT_MASK_XTAL_VREF_SEL << BIT_SHIFT_XTAL_VREF_SEL) +#define BIT_CLEAR_XTAL_VREF_SEL(x) ((x) & (~BITS_XTAL_VREF_SEL)) +#define BIT_GET_XTAL_VREF_SEL(x) \ + (((x) >> BIT_SHIFT_XTAL_VREF_SEL) & BIT_MASK_XTAL_VREF_SEL) +#define BIT_SET_XTAL_VREF_SEL(x, v) \ + (BIT_CLEAR_XTAL_VREF_SEL(x) | BIT_XTAL_VREF_SEL(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#define BIT_EN_XTAL_PDCK_VREF BIT(19) +#define BIT_XTAL_SEL_PWR_V1 BIT(18) +#define BIT_XTAL_LPS_DIVISOR BIT(17) +#define BIT_XTAL_CKDIGI_SEL BIT(16) +#define BIT_EN_XTAL_LPS_CLK BIT(15) +#define BIT_EN_XTAL_SCHMITT BIT(14) +#define BIT_XTAL_PK_SEL_OFFSET BIT(13) -#define BIT_PORT3_RXBCMD1_OK_INT_EN BIT(8) +#define BIT_SHIFT_XTAL_MANU_PK_SEL 11 +#define BIT_MASK_XTAL_MANU_PK_SEL 0x3 +#define BIT_XTAL_MANU_PK_SEL(x) \ + (((x) & BIT_MASK_XTAL_MANU_PK_SEL) << BIT_SHIFT_XTAL_MANU_PK_SEL) +#define BITS_XTAL_MANU_PK_SEL \ + (BIT_MASK_XTAL_MANU_PK_SEL << BIT_SHIFT_XTAL_MANU_PK_SEL) +#define BIT_CLEAR_XTAL_MANU_PK_SEL(x) ((x) & (~BITS_XTAL_MANU_PK_SEL)) +#define BIT_GET_XTAL_MANU_PK_SEL(x) \ + (((x) >> BIT_SHIFT_XTAL_MANU_PK_SEL) & BIT_MASK_XTAL_MANU_PK_SEL) +#define BIT_SET_XTAL_MANU_PK_SEL(x, v) \ + (BIT_CLEAR_XTAL_MANU_PK_SEL(x) | BIT_XTAL_MANU_PK_SEL(v)) -#endif +#define BIT_XTAL_AACK_PK_MANU BIT(10) +#define BIT_EN_XTAL_AAC_PKDET_V1 BIT(9) +#define BIT_EN_XTAL_AAC_GM_V1 BIT(8) +#define BIT_XTAL_LDO_OPVB_SEL BIT(7) +#define BIT_SHIFT_XTAL_DUMMY_V1 7 +#define BIT_MASK_XTAL_DUMMY_V1 0x3f +#define BIT_XTAL_DUMMY_V1(x) \ + (((x) & BIT_MASK_XTAL_DUMMY_V1) << BIT_SHIFT_XTAL_DUMMY_V1) +#define BITS_XTAL_DUMMY_V1 (BIT_MASK_XTAL_DUMMY_V1 << BIT_SHIFT_XTAL_DUMMY_V1) +#define BIT_CLEAR_XTAL_DUMMY_V1(x) ((x) & (~BITS_XTAL_DUMMY_V1)) +#define BIT_GET_XTAL_DUMMY_V1(x) \ + (((x) >> BIT_SHIFT_XTAL_DUMMY_V1) & BIT_MASK_XTAL_DUMMY_V1) +#define BIT_SET_XTAL_DUMMY_V1(x, v) \ + (BIT_CLEAR_XTAL_DUMMY_V1(x) | BIT_XTAL_DUMMY_V1(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ -#define BIT_FS_CLI2_RX_BMD1_INT_EN BIT(8) +#define BIT_XTAL_DRV_RF2_LATCH BIT(6) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ -#define BIT_PORT2_RXUCMD0_OK_INT_EN BIT(7) +#define BIT_XTAL_LDO_NC BIT(6) +#define BIT_XTAL_EN_LNBUF BIT(6) +#define BIT_XTAL__AAC_TIE_MID BIT(5) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ -/* 2 REG_FE4IMR (Offset 0x1130) */ +#define BIT_SHIFT_XTAL_DRV_RF2_1_0 4 +#define BIT_MASK_XTAL_DRV_RF2_1_0 0x3 +#define BIT_XTAL_DRV_RF2_1_0(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_1_0) << BIT_SHIFT_XTAL_DRV_RF2_1_0) +#define BITS_XTAL_DRV_RF2_1_0 \ + (BIT_MASK_XTAL_DRV_RF2_1_0 << BIT_SHIFT_XTAL_DRV_RF2_1_0) +#define BIT_CLEAR_XTAL_DRV_RF2_1_0(x) ((x) & (~BITS_XTAL_DRV_RF2_1_0)) +#define BIT_GET_XTAL_DRV_RF2_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_1_0) & BIT_MASK_XTAL_DRV_RF2_1_0) +#define BIT_SET_XTAL_DRV_RF2_1_0(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_1_0(x) | BIT_XTAL_DRV_RF2_1_0(v)) -#define BIT_FS_CLI1_RX_UMD0_INT_EN BIT(7) +#define BIT_XTAL_GATED_RF2N BIT(3) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ -/* 2 REG_FE4IMR (Offset 0x1130) */ +#define BIT_SHIFT_XTAL_LDO_VREF_V2 3 +#define BIT_MASK_XTAL_LDO_VREF_V2 0x7 +#define BIT_XTAL_LDO_VREF_V2(x) \ + (((x) & BIT_MASK_XTAL_LDO_VREF_V2) << BIT_SHIFT_XTAL_LDO_VREF_V2) +#define BITS_XTAL_LDO_VREF_V2 \ + (BIT_MASK_XTAL_LDO_VREF_V2 << BIT_SHIFT_XTAL_LDO_VREF_V2) +#define BIT_CLEAR_XTAL_LDO_VREF_V2(x) ((x) & (~BITS_XTAL_LDO_VREF_V2)) +#define BIT_GET_XTAL_LDO_VREF_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_VREF_V2) & BIT_MASK_XTAL_LDO_VREF_V2) +#define BIT_SET_XTAL_LDO_VREF_V2(x, v) \ + (BIT_CLEAR_XTAL_LDO_VREF_V2(x) | BIT_XTAL_LDO_VREF_V2(v)) -#define BIT_PORT2_RXUCMD1_OK_INT_EN BIT(6) +#define BIT_SHIFT_XTAL_AAC_OPCUR 3 +#define BIT_MASK_XTAL_AAC_OPCUR 0x3 +#define BIT_XTAL_AAC_OPCUR(x) \ + (((x) & BIT_MASK_XTAL_AAC_OPCUR) << BIT_SHIFT_XTAL_AAC_OPCUR) +#define BITS_XTAL_AAC_OPCUR \ + (BIT_MASK_XTAL_AAC_OPCUR << BIT_SHIFT_XTAL_AAC_OPCUR) +#define BIT_CLEAR_XTAL_AAC_OPCUR(x) ((x) & (~BITS_XTAL_AAC_OPCUR)) +#define BIT_GET_XTAL_AAC_OPCUR(x) \ + (((x) >> BIT_SHIFT_XTAL_AAC_OPCUR) & BIT_MASK_XTAL_AAC_OPCUR) +#define BIT_SET_XTAL_AAC_OPCUR(x, v) \ + (BIT_CLEAR_XTAL_AAC_OPCUR(x) | BIT_XTAL_AAC_OPCUR(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ +#define BIT_XTAL_GATED_RF2P BIT(2) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_FS_CLI1_RX_UMD1_INT_EN BIT(6) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ +#define BIT_XTAL_LPMODE_V1 BIT(2) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ -#define BIT_PORT2_RXBCMD0_OK_INT_EN BIT(5) +#define BIT_XTAL_LDO_DI BIT(1) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ +#define BIT_SHIFT_XTAL_AAC_IOFFSET 1 +#define BIT_MASK_XTAL_AAC_IOFFSET 0x3 +#define BIT_XTAL_AAC_IOFFSET(x) \ + (((x) & BIT_MASK_XTAL_AAC_IOFFSET) << BIT_SHIFT_XTAL_AAC_IOFFSET) +#define BITS_XTAL_AAC_IOFFSET \ + (BIT_MASK_XTAL_AAC_IOFFSET << BIT_SHIFT_XTAL_AAC_IOFFSET) +#define BIT_CLEAR_XTAL_AAC_IOFFSET(x) ((x) & (~BITS_XTAL_AAC_IOFFSET)) +#define BIT_GET_XTAL_AAC_IOFFSET(x) \ + (((x) >> BIT_SHIFT_XTAL_AAC_IOFFSET) & BIT_MASK_XTAL_AAC_IOFFSET) +#define BIT_SET_XTAL_AAC_IOFFSET(x, v) \ + (BIT_CLEAR_XTAL_AAC_IOFFSET(x) | BIT_XTAL_AAC_IOFFSET(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_FS_CLI1_RX_BMD0_INT_EN BIT(5) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ +#define BIT_XTAL_SEL_PWR BIT(0) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_SHIFT_XTAL_SEL_TOK_V3 0 +#define BIT_MASK_XTAL_SEL_TOK_V3 0x3 +#define BIT_XTAL_SEL_TOK_V3(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_V3) << BIT_SHIFT_XTAL_SEL_TOK_V3) +#define BITS_XTAL_SEL_TOK_V3 \ + (BIT_MASK_XTAL_SEL_TOK_V3 << BIT_SHIFT_XTAL_SEL_TOK_V3) +#define BIT_CLEAR_XTAL_SEL_TOK_V3(x) ((x) & (~BITS_XTAL_SEL_TOK_V3)) +#define BIT_GET_XTAL_SEL_TOK_V3(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V3) & BIT_MASK_XTAL_SEL_TOK_V3) +#define BIT_SET_XTAL_SEL_TOK_V3(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_V3(x) | BIT_XTAL_SEL_TOK_V3(v)) -#define BIT_PORT2_RXBCMD1_OK_INT_EN BIT(4) +#define BIT_XTAL_AAC_CAP_V1 BIT(0) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_XTAL_AAC (Offset 0x104C) */ +#define BIT_SHIFT_GM_MANUAL_4_0 21 +#define BIT_MASK_GM_MANUAL_4_0 0x1f +#define BIT_GM_MANUAL_4_0(x) \ + (((x) & BIT_MASK_GM_MANUAL_4_0) << BIT_SHIFT_GM_MANUAL_4_0) +#define BITS_GM_MANUAL_4_0 (BIT_MASK_GM_MANUAL_4_0 << BIT_SHIFT_GM_MANUAL_4_0) +#define BIT_CLEAR_GM_MANUAL_4_0(x) ((x) & (~BITS_GM_MANUAL_4_0)) +#define BIT_GET_GM_MANUAL_4_0(x) \ + (((x) >> BIT_SHIFT_GM_MANUAL_4_0) & BIT_MASK_GM_MANUAL_4_0) +#define BIT_SET_GM_MANUAL_4_0(x, v) \ + (BIT_CLEAR_GM_MANUAL_4_0(x) | BIT_GM_MANUAL_4_0(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#define BIT_SHIFT_GM_STUP_4_0 16 +#define BIT_MASK_GM_STUP_4_0 0x1f +#define BIT_GM_STUP_4_0(x) \ + (((x) & BIT_MASK_GM_STUP_4_0) << BIT_SHIFT_GM_STUP_4_0) +#define BITS_GM_STUP_4_0 (BIT_MASK_GM_STUP_4_0 << BIT_SHIFT_GM_STUP_4_0) +#define BIT_CLEAR_GM_STUP_4_0(x) ((x) & (~BITS_GM_STUP_4_0)) +#define BIT_GET_GM_STUP_4_0(x) \ + (((x) >> BIT_SHIFT_GM_STUP_4_0) & BIT_MASK_GM_STUP_4_0) +#define BIT_SET_GM_STUP_4_0(x, v) \ + (BIT_CLEAR_GM_STUP_4_0(x) | BIT_GM_STUP_4_0(v)) -#define BIT_FS_CLI1_RX_BMD1_INT_EN BIT(4) +#define BIT_SHIFT_XTAL_CK_SET_2_0 13 +#define BIT_MASK_XTAL_CK_SET_2_0 0x7 +#define BIT_XTAL_CK_SET_2_0(x) \ + (((x) & BIT_MASK_XTAL_CK_SET_2_0) << BIT_SHIFT_XTAL_CK_SET_2_0) +#define BITS_XTAL_CK_SET_2_0 \ + (BIT_MASK_XTAL_CK_SET_2_0 << BIT_SHIFT_XTAL_CK_SET_2_0) +#define BIT_CLEAR_XTAL_CK_SET_2_0(x) ((x) & (~BITS_XTAL_CK_SET_2_0)) +#define BIT_GET_XTAL_CK_SET_2_0(x) \ + (((x) >> BIT_SHIFT_XTAL_CK_SET_2_0) & BIT_MASK_XTAL_CK_SET_2_0) +#define BIT_SET_XTAL_CK_SET_2_0(x, v) \ + (BIT_CLEAR_XTAL_CK_SET_2_0(x) | BIT_XTAL_CK_SET_2_0(v)) + +#define BIT_SHIFT_GM_INIT_4_0 8 +#define BIT_MASK_GM_INIT_4_0 0x1f +#define BIT_GM_INIT_4_0(x) \ + (((x) & BIT_MASK_GM_INIT_4_0) << BIT_SHIFT_GM_INIT_4_0) +#define BITS_GM_INIT_4_0 (BIT_MASK_GM_INIT_4_0 << BIT_SHIFT_GM_INIT_4_0) +#define BIT_CLEAR_GM_INIT_4_0(x) ((x) & (~BITS_GM_INIT_4_0)) +#define BIT_GET_GM_INIT_4_0(x) \ + (((x) >> BIT_SHIFT_GM_INIT_4_0) & BIT_MASK_GM_INIT_4_0) +#define BIT_SET_GM_INIT_4_0(x, v) \ + (BIT_CLEAR_GM_INIT_4_0(x) | BIT_GM_INIT_4_0(v)) + +#define BIT_SHIFT_XAAC_GM_OFFSET_4_0 2 +#define BIT_MASK_XAAC_GM_OFFSET_4_0 0x1f +#define BIT_XAAC_GM_OFFSET_4_0(x) \ + (((x) & BIT_MASK_XAAC_GM_OFFSET_4_0) << BIT_SHIFT_XAAC_GM_OFFSET_4_0) +#define BITS_XAAC_GM_OFFSET_4_0 \ + (BIT_MASK_XAAC_GM_OFFSET_4_0 << BIT_SHIFT_XAAC_GM_OFFSET_4_0) +#define BIT_CLEAR_XAAC_GM_OFFSET_4_0(x) ((x) & (~BITS_XAAC_GM_OFFSET_4_0)) +#define BIT_GET_XAAC_GM_OFFSET_4_0(x) \ + (((x) >> BIT_SHIFT_XAAC_GM_OFFSET_4_0) & BIT_MASK_XAAC_GM_OFFSET_4_0) +#define BIT_SET_XAAC_GM_OFFSET_4_0(x, v) \ + (BIT_CLEAR_XAAC_GM_OFFSET_4_0(x) | BIT_XAAC_GM_OFFSET_4_0(v)) + +/* 2 REG_ANAPAR_XTAL_R_ONLY (Offset 0x1050) */ + +#define BIT_XTAL_PKDET_OUT BIT(6) + +#define BIT_SHIFT_XTAL_GM_AAC_4_0 1 +#define BIT_MASK_XTAL_GM_AAC_4_0 0x1f +#define BIT_XTAL_GM_AAC_4_0(x) \ + (((x) & BIT_MASK_XTAL_GM_AAC_4_0) << BIT_SHIFT_XTAL_GM_AAC_4_0) +#define BITS_XTAL_GM_AAC_4_0 \ + (BIT_MASK_XTAL_GM_AAC_4_0 << BIT_SHIFT_XTAL_GM_AAC_4_0) +#define BIT_CLEAR_XTAL_GM_AAC_4_0(x) ((x) & (~BITS_XTAL_GM_AAC_4_0)) +#define BIT_GET_XTAL_GM_AAC_4_0(x) \ + (((x) >> BIT_SHIFT_XTAL_GM_AAC_4_0) & BIT_MASK_XTAL_GM_AAC_4_0) +#define BIT_SET_XTAL_GM_AAC_4_0(x, v) \ + (BIT_CLEAR_XTAL_GM_AAC_4_0(x) | BIT_XTAL_GM_AAC_4_0(v)) + +#define BIT_XAAC_READY BIT(0) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ + +#define BIT_XAAC_LPOW BIT(31) + +#define BIT_SHIFT_AAC_MODE 29 +#define BIT_MASK_AAC_MODE 0x3 +#define BIT_AAC_MODE(x) (((x) & BIT_MASK_AAC_MODE) << BIT_SHIFT_AAC_MODE) +#define BITS_AAC_MODE (BIT_MASK_AAC_MODE << BIT_SHIFT_AAC_MODE) +#define BIT_CLEAR_AAC_MODE(x) ((x) & (~BITS_AAC_MODE)) +#define BIT_GET_AAC_MODE(x) (((x) >> BIT_SHIFT_AAC_MODE) & BIT_MASK_AAC_MODE) +#define BIT_SET_AAC_MODE(x, v) (BIT_CLEAR_AAC_MODE(x) | BIT_AAC_MODE(v)) + +#define BIT_SHIFT_GM_MANUAL 21 +#define BIT_MASK_GM_MANUAL 0x1f +#define BIT_GM_MANUAL(x) (((x) & BIT_MASK_GM_MANUAL) << BIT_SHIFT_GM_MANUAL) +#define BITS_GM_MANUAL (BIT_MASK_GM_MANUAL << BIT_SHIFT_GM_MANUAL) +#define BIT_CLEAR_GM_MANUAL(x) ((x) & (~BITS_GM_MANUAL)) +#define BIT_GET_GM_MANUAL(x) (((x) >> BIT_SHIFT_GM_MANUAL) & BIT_MASK_GM_MANUAL) +#define BIT_SET_GM_MANUAL(x, v) (BIT_CLEAR_GM_MANUAL(x) | BIT_GM_MANUAL(v)) + +#define BIT_SHIFT_XTAL_LDO_LPS 21 +#define BIT_MASK_XTAL_LDO_LPS 0x7 +#define BIT_XTAL_LDO_LPS(x) \ + (((x) & BIT_MASK_XTAL_LDO_LPS) << BIT_SHIFT_XTAL_LDO_LPS) +#define BITS_XTAL_LDO_LPS (BIT_MASK_XTAL_LDO_LPS << BIT_SHIFT_XTAL_LDO_LPS) +#define BIT_CLEAR_XTAL_LDO_LPS(x) ((x) & (~BITS_XTAL_LDO_LPS)) +#define BIT_GET_XTAL_LDO_LPS(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_LPS) & BIT_MASK_XTAL_LDO_LPS) +#define BIT_SET_XTAL_LDO_LPS(x, v) \ + (BIT_CLEAR_XTAL_LDO_LPS(x) | BIT_XTAL_LDO_LPS(v)) + +#define BIT_SHIFT_GM_STUP 16 +#define BIT_MASK_GM_STUP 0x1f +#define BIT_GM_STUP(x) (((x) & BIT_MASK_GM_STUP) << BIT_SHIFT_GM_STUP) +#define BITS_GM_STUP (BIT_MASK_GM_STUP << BIT_SHIFT_GM_STUP) +#define BIT_CLEAR_GM_STUP(x) ((x) & (~BITS_GM_STUP)) +#define BIT_GET_GM_STUP(x) (((x) >> BIT_SHIFT_GM_STUP) & BIT_MASK_GM_STUP) +#define BIT_SET_GM_STUP(x, v) (BIT_CLEAR_GM_STUP(x) | BIT_GM_STUP(v)) + +#define BIT_SHIFT_XTAL_WAIT_CYC 15 +#define BIT_MASK_XTAL_WAIT_CYC 0x3f +#define BIT_XTAL_WAIT_CYC(x) \ + (((x) & BIT_MASK_XTAL_WAIT_CYC) << BIT_SHIFT_XTAL_WAIT_CYC) +#define BITS_XTAL_WAIT_CYC (BIT_MASK_XTAL_WAIT_CYC << BIT_SHIFT_XTAL_WAIT_CYC) +#define BIT_CLEAR_XTAL_WAIT_CYC(x) ((x) & (~BITS_XTAL_WAIT_CYC)) +#define BIT_GET_XTAL_WAIT_CYC(x) \ + (((x) >> BIT_SHIFT_XTAL_WAIT_CYC) & BIT_MASK_XTAL_WAIT_CYC) +#define BIT_SET_XTAL_WAIT_CYC(x, v) \ + (BIT_CLEAR_XTAL_WAIT_CYC(x) | BIT_XTAL_WAIT_CYC(v)) + +#define BIT_SHIFT_XTAL_CK_SET 13 +#define BIT_MASK_XTAL_CK_SET 0x7 +#define BIT_XTAL_CK_SET(x) \ + (((x) & BIT_MASK_XTAL_CK_SET) << BIT_SHIFT_XTAL_CK_SET) +#define BITS_XTAL_CK_SET (BIT_MASK_XTAL_CK_SET << BIT_SHIFT_XTAL_CK_SET) +#define BIT_CLEAR_XTAL_CK_SET(x) ((x) & (~BITS_XTAL_CK_SET)) +#define BIT_GET_XTAL_CK_SET(x) \ + (((x) >> BIT_SHIFT_XTAL_CK_SET) & BIT_MASK_XTAL_CK_SET) +#define BIT_SET_XTAL_CK_SET(x, v) \ + (BIT_CLEAR_XTAL_CK_SET(x) | BIT_XTAL_CK_SET(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CPHY_LDO (Offset 0x1054) */ + +#define BIT_SHIFT_CPHY_LDO_PD 12 +#define BIT_MASK_CPHY_LDO_PD 0x3 +#define BIT_CPHY_LDO_PD(x) \ + (((x) & BIT_MASK_CPHY_LDO_PD) << BIT_SHIFT_CPHY_LDO_PD) +#define BITS_CPHY_LDO_PD (BIT_MASK_CPHY_LDO_PD << BIT_SHIFT_CPHY_LDO_PD) +#define BIT_CLEAR_CPHY_LDO_PD(x) ((x) & (~BITS_CPHY_LDO_PD)) +#define BIT_GET_CPHY_LDO_PD(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_PD) & BIT_MASK_CPHY_LDO_PD) +#define BIT_SET_CPHY_LDO_PD(x, v) \ + (BIT_CLEAR_CPHY_LDO_PD(x) | BIT_CPHY_LDO_PD(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ + +#define BIT_SHIFT_XTAL_LDO_OK 12 +#define BIT_MASK_XTAL_LDO_OK 0x7 +#define BIT_XTAL_LDO_OK(x) \ + (((x) & BIT_MASK_XTAL_LDO_OK) << BIT_SHIFT_XTAL_LDO_OK) +#define BITS_XTAL_LDO_OK (BIT_MASK_XTAL_LDO_OK << BIT_SHIFT_XTAL_LDO_OK) +#define BIT_CLEAR_XTAL_LDO_OK(x) ((x) & (~BITS_XTAL_LDO_OK)) +#define BIT_GET_XTAL_LDO_OK(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_OK) & BIT_MASK_XTAL_LDO_OK) +#define BIT_SET_XTAL_LDO_OK(x, v) \ + (BIT_CLEAR_XTAL_LDO_OK(x) | BIT_XTAL_LDO_OK(v)) +#define BIT_XTAL_MD_LPOW BIT(11) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT1_RXUCMD0_OK_INT_EN BIT(3) +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CPHY_LDO (Offset 0x1054) */ + +#define BIT_SHIFT_CPHY_LDO_SR 10 +#define BIT_MASK_CPHY_LDO_SR 0x3 +#define BIT_CPHY_LDO_SR(x) \ + (((x) & BIT_MASK_CPHY_LDO_SR) << BIT_SHIFT_CPHY_LDO_SR) +#define BITS_CPHY_LDO_SR (BIT_MASK_CPHY_LDO_SR << BIT_SHIFT_CPHY_LDO_SR) +#define BIT_CLEAR_CPHY_LDO_SR(x) ((x) & (~BITS_CPHY_LDO_SR)) +#define BIT_GET_CPHY_LDO_SR(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_SR) & BIT_MASK_CPHY_LDO_SR) +#define BIT_SET_CPHY_LDO_SR(x, v) \ + (BIT_CLEAR_CPHY_LDO_SR(x) | BIT_CPHY_LDO_SR(v)) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ + +#define BIT_SHIFT_XTAL_OV_RATIO 9 +#define BIT_MASK_XTAL_OV_RATIO 0x3 +#define BIT_XTAL_OV_RATIO(x) \ + (((x) & BIT_MASK_XTAL_OV_RATIO) << BIT_SHIFT_XTAL_OV_RATIO) +#define BITS_XTAL_OV_RATIO (BIT_MASK_XTAL_OV_RATIO << BIT_SHIFT_XTAL_OV_RATIO) +#define BIT_CLEAR_XTAL_OV_RATIO(x) ((x) & (~BITS_XTAL_OV_RATIO)) +#define BIT_GET_XTAL_OV_RATIO(x) \ + (((x) >> BIT_SHIFT_XTAL_OV_RATIO) & BIT_MASK_XTAL_OV_RATIO) +#define BIT_SET_XTAL_OV_RATIO(x, v) \ + (BIT_CLEAR_XTAL_OV_RATIO(x) | BIT_XTAL_OV_RATIO(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CPHY_LDO (Offset 0x1054) */ +#define BIT_SHIFT_CPHY_LDO_TUNEREF 8 +#define BIT_MASK_CPHY_LDO_TUNEREF 0x3 +#define BIT_CPHY_LDO_TUNEREF(x) \ + (((x) & BIT_MASK_CPHY_LDO_TUNEREF) << BIT_SHIFT_CPHY_LDO_TUNEREF) +#define BITS_CPHY_LDO_TUNEREF \ + (BIT_MASK_CPHY_LDO_TUNEREF << BIT_SHIFT_CPHY_LDO_TUNEREF) +#define BIT_CLEAR_CPHY_LDO_TUNEREF(x) ((x) & (~BITS_CPHY_LDO_TUNEREF)) +#define BIT_GET_CPHY_LDO_TUNEREF(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_TUNEREF) & BIT_MASK_CPHY_LDO_TUNEREF) +#define BIT_SET_CPHY_LDO_TUNEREF(x, v) \ + (BIT_CLEAR_CPHY_LDO_TUNEREF(x) | BIT_CPHY_LDO_TUNEREF(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_FS_CLI0_RX_UMD0_INT_EN BIT(3) +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ +#define BIT_SHIFT_GM_INIT 8 +#define BIT_MASK_GM_INIT 0x1f +#define BIT_GM_INIT(x) (((x) & BIT_MASK_GM_INIT) << BIT_SHIFT_GM_INIT) +#define BITS_GM_INIT (BIT_MASK_GM_INIT << BIT_SHIFT_GM_INIT) +#define BIT_CLEAR_GM_INIT(x) ((x) & (~BITS_GM_INIT)) +#define BIT_GET_GM_INIT(x) (((x) >> BIT_SHIFT_GM_INIT) & BIT_MASK_GM_INIT) +#define BIT_SET_GM_INIT(x, v) (BIT_CLEAR_GM_INIT(x) | BIT_GM_INIT(v)) -#if (HALMAC_8197F_SUPPORT) +#define BIT_SHIFT_XTAL_OV_UNIT 6 +#define BIT_MASK_XTAL_OV_UNIT 0x7 +#define BIT_XTAL_OV_UNIT(x) \ + (((x) & BIT_MASK_XTAL_OV_UNIT) << BIT_SHIFT_XTAL_OV_UNIT) +#define BITS_XTAL_OV_UNIT (BIT_MASK_XTAL_OV_UNIT << BIT_SHIFT_XTAL_OV_UNIT) +#define BIT_CLEAR_XTAL_OV_UNIT(x) ((x) & (~BITS_XTAL_OV_UNIT)) +#define BIT_GET_XTAL_OV_UNIT(x) \ + (((x) >> BIT_SHIFT_XTAL_OV_UNIT) & BIT_MASK_XTAL_OV_UNIT) +#define BIT_SET_XTAL_OV_UNIT(x, v) \ + (BIT_CLEAR_XTAL_OV_UNIT(x) | BIT_XTAL_OV_UNIT(v)) +#endif -/* 2 REG_FE4IMR (Offset 0x1130) */ +#if (HALMAC_8814B_SUPPORT) -#define BIT_PORT1_RXUCMD1_OK_INT_EN BIT(2) +/* 2 REG_CPHY_LDO (Offset 0x1054) */ + +#define BIT_SHIFT_CPHY_LDO_TUNE_VO 5 +#define BIT_MASK_CPHY_LDO_TUNE_VO 0x7 +#define BIT_CPHY_LDO_TUNE_VO(x) \ + (((x) & BIT_MASK_CPHY_LDO_TUNE_VO) << BIT_SHIFT_CPHY_LDO_TUNE_VO) +#define BITS_CPHY_LDO_TUNE_VO \ + (BIT_MASK_CPHY_LDO_TUNE_VO << BIT_SHIFT_CPHY_LDO_TUNE_VO) +#define BIT_CLEAR_CPHY_LDO_TUNE_VO(x) ((x) & (~BITS_CPHY_LDO_TUNE_VO)) +#define BIT_GET_CPHY_LDO_TUNE_VO(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_TUNE_VO) & BIT_MASK_CPHY_LDO_TUNE_VO) +#define BIT_SET_CPHY_LDO_TUNE_VO(x, v) \ + (BIT_CLEAR_CPHY_LDO_TUNE_VO(x) | BIT_CPHY_LDO_TUNE_VO(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ +#define BIT_SHIFT_XTAL_MODE_MANUAL 4 +#define BIT_MASK_XTAL_MODE_MANUAL 0x3 +#define BIT_XTAL_MODE_MANUAL(x) \ + (((x) & BIT_MASK_XTAL_MODE_MANUAL) << BIT_SHIFT_XTAL_MODE_MANUAL) +#define BITS_XTAL_MODE_MANUAL \ + (BIT_MASK_XTAL_MODE_MANUAL << BIT_SHIFT_XTAL_MODE_MANUAL) +#define BIT_CLEAR_XTAL_MODE_MANUAL(x) ((x) & (~BITS_XTAL_MODE_MANUAL)) +#define BIT_GET_XTAL_MODE_MANUAL(x) \ + (((x) >> BIT_SHIFT_XTAL_MODE_MANUAL) & BIT_MASK_XTAL_MODE_MANUAL) +#define BIT_SET_XTAL_MODE_MANUAL(x, v) \ + (BIT_CLEAR_XTAL_MODE_MANUAL(x) | BIT_XTAL_MODE_MANUAL(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#define BIT_SHIFT_PK_END_AR 3 +#define BIT_MASK_PK_END_AR 0x3 +#define BIT_PK_END_AR(x) (((x) & BIT_MASK_PK_END_AR) << BIT_SHIFT_PK_END_AR) +#define BITS_PK_END_AR (BIT_MASK_PK_END_AR << BIT_SHIFT_PK_END_AR) +#define BIT_CLEAR_PK_END_AR(x) ((x) & (~BITS_PK_END_AR)) +#define BIT_GET_PK_END_AR(x) (((x) >> BIT_SHIFT_PK_END_AR) & BIT_MASK_PK_END_AR) +#define BIT_SET_PK_END_AR(x, v) (BIT_CLEAR_PK_END_AR(x) | BIT_PK_END_AR(v)) -#define BIT_FS_DMEM1_WPTR_UPDATE_INT_EN BIT(2) +#define BIT_XTAL_MANU_SEL BIT(3) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CPHY_LDO (Offset 0x1054) */ +#define BIT_SHIFT_CPHY_LDO_OCP_VTH 2 +#define BIT_MASK_CPHY_LDO_OCP_VTH 0x7 +#define BIT_CPHY_LDO_OCP_VTH(x) \ + (((x) & BIT_MASK_CPHY_LDO_OCP_VTH) << BIT_SHIFT_CPHY_LDO_OCP_VTH) +#define BITS_CPHY_LDO_OCP_VTH \ + (BIT_MASK_CPHY_LDO_OCP_VTH << BIT_SHIFT_CPHY_LDO_OCP_VTH) +#define BIT_CLEAR_CPHY_LDO_OCP_VTH(x) ((x) & (~BITS_CPHY_LDO_OCP_VTH)) +#define BIT_GET_CPHY_LDO_OCP_VTH(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_OCP_VTH) & BIT_MASK_CPHY_LDO_OCP_VTH) +#define BIT_SET_CPHY_LDO_OCP_VTH(x, v) \ + (BIT_CLEAR_CPHY_LDO_OCP_VTH(x) | BIT_CPHY_LDO_OCP_VTH(v)) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ + +#define BIT_SHIFT_XAAC_GM_OFFSET 2 +#define BIT_MASK_XAAC_GM_OFFSET 0x1f +#define BIT_XAAC_GM_OFFSET(x) \ + (((x) & BIT_MASK_XAAC_GM_OFFSET) << BIT_SHIFT_XAAC_GM_OFFSET) +#define BITS_XAAC_GM_OFFSET \ + (BIT_MASK_XAAC_GM_OFFSET << BIT_SHIFT_XAAC_GM_OFFSET) +#define BIT_CLEAR_XAAC_GM_OFFSET(x) ((x) & (~BITS_XAAC_GM_OFFSET)) +#define BIT_GET_XAAC_GM_OFFSET(x) \ + (((x) >> BIT_SHIFT_XAAC_GM_OFFSET) & BIT_MASK_XAAC_GM_OFFSET) +#define BIT_SET_XAAC_GM_OFFSET(x, v) \ + (BIT_CLEAR_XAAC_GM_OFFSET(x) | BIT_XAAC_GM_OFFSET(v)) + +#define BIT_SHIFT_PK_START_AR 1 +#define BIT_MASK_PK_START_AR 0x3 +#define BIT_PK_START_AR(x) \ + (((x) & BIT_MASK_PK_START_AR) << BIT_SHIFT_PK_START_AR) +#define BITS_PK_START_AR (BIT_MASK_PK_START_AR << BIT_SHIFT_PK_START_AR) +#define BIT_CLEAR_PK_START_AR(x) ((x) & (~BITS_PK_START_AR)) +#define BIT_GET_PK_START_AR(x) \ + (((x) >> BIT_SHIFT_PK_START_AR) & BIT_MASK_PK_START_AR) +#define BIT_SET_PK_START_AR(x, v) \ + (BIT_CLEAR_PK_START_AR(x) | BIT_PK_START_AR(v)) + +#define BIT_XTAL_MODE BIT(1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CPHY_LDO (Offset 0x1054) */ + +#define BIT_SHIFT_VREF_LDO_OK 0 +#define BIT_MASK_VREF_LDO_OK 0x3 +#define BIT_VREF_LDO_OK(x) \ + (((x) & BIT_MASK_VREF_LDO_OK) << BIT_SHIFT_VREF_LDO_OK) +#define BITS_VREF_LDO_OK (BIT_MASK_VREF_LDO_OK << BIT_SHIFT_VREF_LDO_OK) +#define BIT_CLEAR_VREF_LDO_OK(x) ((x) & (~BITS_VREF_LDO_OK)) +#define BIT_GET_VREF_LDO_OK(x) \ + (((x) >> BIT_SHIFT_VREF_LDO_OK) & BIT_MASK_VREF_LDO_OK) +#define BIT_SET_VREF_LDO_OK(x, v) \ + (BIT_CLEAR_VREF_LDO_OK(x) | BIT_VREF_LDO_OK(v)) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ + +#define BIT_XAAC_LUT_MANUAL_EN BIT(0) +#define BIT_RESET_N_DECODER BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CPHY_BG (Offset 0x1058) */ + +#define BIT_TXBCN_OK_PORT4 BIT(31) +#define BIT_ATIMEND_PORT4 BIT(31) +#define BIT_TXBCN_OK_PORT3 BIT(30) +#define BIT_ATIMEND_PORT3 BIT(30) +#define BIT_TXBCN_OK_PORT2 BIT(29) +#define BIT_ATIMEND_PORT2 BIT(29) +#define BIT_TXBCN_OK_PORT1 BIT(28) +#define BIT_ATIMEND_PORT1 BIT(28) +#define BIT_TXBCN15OK BIT(23) +#define BIT_BCNDMAINT15 BIT(23) +#define BIT_ATIMEND15 BIT(23) +#define BIT_TXBCN14OK BIT(22) +#define BIT_BCNDMAINT14 BIT(22) +#define BIT_ATIMEND14 BIT(22) +#define BIT_TXBCN13OK BIT(21) +#define BIT_BCNDMAINT13 BIT(21) +#define BIT_ATIMEND13 BIT(21) +#define BIT_TXBCN12OK BIT(20) +#define BIT_BCNDMAINT12 BIT(20) +#define BIT_ATIMEND12 BIT(20) +#define BIT_TXBCN11OK BIT(19) +#define BIT_BCNDMAINT11 BIT(19) +#define BIT_ATIMEND11 BIT(19) +#define BIT_TXBCN10OK BIT(18) +#define BIT_BCNDMAINT10 BIT(18) +#define BIT_ATIMEND10 BIT(18) +#define BIT_TXBCN9OK BIT(17) +#define BIT_BCNDMAINT9 BIT(17) +#define BIT_ATIMEND9 BIT(17) +#define BIT_TXBCN8OK BIT(16) +#define BIT_BCNDMAINT8 BIT(16) +#define BIT_ATIMEND8 BIT(16) +#define BIT_BCNDERR_PORT4 BIT(15) +#define BIT_BCNDERR_PORT3 BIT(14) +#define BIT_BCNDERR_PORT2 BIT(13) +#define BIT_BCNDERR_PORT1 BIT(12) +#define BIT_TXBCN15ERR BIT(7) +#define BIT_BCNDERR15 BIT(7) +#define BIT_TXBCN14ERR BIT(6) +#define BIT_BCNDERR14 BIT(6) +#define BIT_TXBCN13ERR BIT(5) +#define BIT_BCNDERR13 BIT(5) +#define BIT_PS_TIMER_EARLY_INT_5 BIT(5) +#define BIT_TXBCN12ERR BIT(4) +#define BIT_BCNDERR12 BIT(4) +#define BIT_PS_TIMER_EARLY_INT_4 BIT(4) +#define BIT_TXBCN11ERR BIT(3) +#define BIT_BCNDERR11 BIT(3) +#define BIT_PS_TIMER_EARLY_INT_3 BIT(3) +#define BIT_TXBCN10ERR BIT(2) +#define BIT_BCNDERR10 BIT(2) +#define BIT_PS_TIMER_EARLY_INT_2 BIT(2) +#define BIT_TXBCN9ERR BIT(1) +#define BIT_BCNDERR9 BIT(1) +#define BIT_PS_TIMER_EARLY_INT_1 BIT(1) + +#define BIT_SHIFT_BG 0 +#define BIT_MASK_BG 0x7 +#define BIT_BG(x) (((x) & BIT_MASK_BG) << BIT_SHIFT_BG) +#define BITS_BG (BIT_MASK_BG << BIT_SHIFT_BG) +#define BIT_CLEAR_BG(x) ((x) & (~BITS_BG)) +#define BIT_GET_BG(x) (((x) >> BIT_SHIFT_BG) & BIT_MASK_BG) +#define BIT_SET_BG(x, v) (BIT_CLEAR_BG(x) | BIT_BG(v)) + +#define BIT_TXBCN8ERR BIT(0) +#define BIT_BCNDERR8 BIT(0) +#define BIT_PS_TIMER_EARLY_INT_0 BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_SYS_CFG5 (Offset 0x1070) */ -#define BIT_FS_CLI0_RX_UMD1_INT_EN BIT(2) +#define BIT_LPS_STATUS BIT(3) +#define BIT_HCI_TXDMA_BUSY BIT(2) +#define BIT_HCI_TXDMA_ALLOW BIT(1) +#define BIT_FW_CTRL_HCI_TXDMA_EN BIT(0) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ +#define BIT_SCH_PHY_TXOP_SIFS_INT BIT(23) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT1_RXBCMD0_OK_INT_EN BIT(1) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ +#define BIT_WDT_AUTO_MODE BIT(22) +#define BIT_WDT_PLATFORM_EN BIT(21) +#define BIT_WDT_CPU_EN BIT(20) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ -#define BIT_FS_CLI0_RX_BMD0_INT_EN BIT(1) +#define BIT_WDT_OPT_IOWRAPPER BIT(19) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ +#define BIT_ANA_PORT_IDLE BIT(18) +#define BIT_MAC_PORT_IDLE BIT(17) +#define BIT_WL_PLATFORM_RST BIT(16) +#define BIT_WL_SECURITY_CLK BIT(15) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT1_RXBCMD1_OK_INT_EN BIT(0) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ +#define BIT_DDMA_EN BIT(8) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ -#define BIT_FS_CLI0_RX_BMD1_INT_EN BIT(0) +#define BIT_SHIFT_CPU_DMEM_CON 0 +#define BIT_MASK_CPU_DMEM_CON 0xff +#define BIT_CPU_DMEM_CON(x) \ + (((x) & BIT_MASK_CPU_DMEM_CON) << BIT_SHIFT_CPU_DMEM_CON) +#define BITS_CPU_DMEM_CON (BIT_MASK_CPU_DMEM_CON << BIT_SHIFT_CPU_DMEM_CON) +#define BIT_CLEAR_CPU_DMEM_CON(x) ((x) & (~BITS_CPU_DMEM_CON)) +#define BIT_GET_CPU_DMEM_CON(x) \ + (((x) >> BIT_SHIFT_CPU_DMEM_CON) & BIT_MASK_CPU_DMEM_CON) +#define BIT_SET_CPU_DMEM_CON(x, v) \ + (BIT_CLEAR_CPU_DMEM_CON(x) | BIT_CPU_DMEM_CON(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BOOT_REASON (Offset 0x1088) */ +#define BIT_SHIFT_BOOT_REASON_V1 0 +#define BIT_MASK_BOOT_REASON_V1 0x7 +#define BIT_BOOT_REASON_V1(x) \ + (((x) & BIT_MASK_BOOT_REASON_V1) << BIT_SHIFT_BOOT_REASON_V1) +#define BITS_BOOT_REASON_V1 \ + (BIT_MASK_BOOT_REASON_V1 << BIT_SHIFT_BOOT_REASON_V1) +#define BIT_CLEAR_BOOT_REASON_V1(x) ((x) & (~BITS_BOOT_REASON_V1)) +#define BIT_GET_BOOT_REASON_V1(x) \ + (((x) >> BIT_SHIFT_BOOT_REASON_V1) & BIT_MASK_BOOT_REASON_V1) +#define BIT_SET_BOOT_REASON_V1(x, v) \ + (BIT_CLEAR_BOOT_REASON_V1(x) | BIT_BOOT_REASON_V1(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT4_PKTIN_INT BIT(19) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_HIMR4 (Offset 0x1090) */ +#define BIT_ATIM_END_INT16_MSK BIT(32) +#define BIT_ATIM_END_INT15_MSK BIT(31) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ -#define BIT_FS_CLI3_TXPKTIN_INT BIT(19) +#define BIT_DATA_FW_READY BIT(31) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HIMR4 (Offset 0x1090) */ +#define BIT_ATIM_END_INT14_MSK BIT(30) +#define BIT_ATIM_END_INT13_MSK BIT(29) +#define BIT_ATIM_END_INT12_MSK BIT(28) +#define BIT_ATIM_END_INT11_MSK BIT(27) +#define BIT_ATIM_END_INT10_MSK BIT(26) +#define BIT_ATIM_END_INT9_MSK BIT(25) +#define BIT_ATIM_END_INT8_MSK BIT(24) +#define BIT_TX_BCN_ERR_INT15_MSK BIT(23) +#define BIT_TX_BCN_ERR_INT14_MSK BIT(22) +#define BIT_TX_BCN_ERR_INT13_MSK BIT(21) +#define BIT_TX_BCN_ERR_INT12_MSK BIT(20) +#define BIT_TX_BCN_ERR_INT11_MSK BIT(19) +#define BIT_TX_BCN_ERR_INT10_MSK BIT(18) +#define BIT_TX_BCN_ERR_INT9_MSK BIT(17) +#define BIT_TX_BCN_ERR_INT8_MSK BIT(16) +#define BIT_TX_BCN_OK_INT15_MSK BIT(15) +#define BIT_TX_BCN_OK_INT14_MSK BIT(14) +#define BIT_TX_BCN_OK_INT13_MSK BIT(13) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT3_PKTIN_INT BIT(18) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ +#define BIT_WDT_SYS_RST BIT(13) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HIMR4 (Offset 0x1090) */ -#define BIT_FS_CLI2_TXPKTIN_INT BIT(18) +#define BIT_TX_BCN_OK_INT12_MSK BIT(12) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ +#define BIT_WDT_ENABLE BIT(12) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT2_PKTIN_INT BIT(17) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_HIMR4 (Offset 0x1090) */ +#define BIT_TX_BCN_OK_INT11_MSK BIT(11) +#define BIT_TX_BCN_OK_INT10_MSK BIT(10) +#define BIT_TX_BCN_OK_INT9_MSK BIT(9) +#define BIT_TX_BCN_OK_INT8_MSK BIT(8) +#define BIT_BCN_DMA_INT15_MSK BIT(7) +#define BIT_BCN_DMA_INT14_MSK BIT(6) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ -#define BIT_FS_CLI1_TXPKTIN_INT BIT(17) +#define BIT_SHIFT_BOOT_SEL 6 +#define BIT_MASK_BOOT_SEL 0x3 +#define BIT_BOOT_SEL(x) (((x) & BIT_MASK_BOOT_SEL) << BIT_SHIFT_BOOT_SEL) +#define BITS_BOOT_SEL (BIT_MASK_BOOT_SEL << BIT_SHIFT_BOOT_SEL) +#define BIT_CLEAR_BOOT_SEL(x) ((x) & (~BITS_BOOT_SEL)) +#define BIT_GET_BOOT_SEL(x) (((x) >> BIT_SHIFT_BOOT_SEL) & BIT_MASK_BOOT_SEL) +#define BIT_SET_BOOT_SEL(x, v) (BIT_CLEAR_BOOT_SEL(x) | BIT_BOOT_SEL(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HIMR4 (Offset 0x1090) */ +#define BIT_BCN_DMA_INT13_MSK BIT(5) +#define BIT_BCN_DMA_INT12_MSK BIT(4) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT1_PKTIN_INT BIT(16) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ +#define BIT_CLK_SEL BIT(4) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HIMR4 (Offset 0x1090) */ -#define BIT_FS_CLI0_TXPKTIN_INT BIT(16) +#define BIT_BCN_DMA_INT11_MSK BIT(3) +#define BIT_BCN_DMA_INT10_MSK BIT(2) +#define BIT_BCN_DMA_INT9_MSK BIT(1) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ +#define BIT_DATA_PLATFORM_RST BIT(1) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT4_RXUCMD0_OK_INT BIT(15) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_HIMR4 (Offset 0x1090) */ +#define BIT_BCN_DMA_INT8_MSK BIT(0) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ -#define BIT_FS_CLI3_RX_UMD0_INT BIT(15) +#define BIT_DATA_CPU_RST BIT(0) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HISR4 (Offset 0x1094) */ +#define BIT_TX_BCN_ERR_INT15 BIT(23) +#define BIT_TX_BCN_ERR_INT14 BIT(22) +#define BIT_TX_BCN_ERR_INT13 BIT(21) +#define BIT_TX_BCN_ERR_INT12 BIT(20) +#define BIT_TX_BCN_ERR_INT11 BIT(19) +#define BIT_TX_BCN_ERR_INT10 BIT(18) +#define BIT_TX_BCN_ERR_INT9 BIT(17) +#define BIT_TX_BCN_ERR_INT8 BIT(16) +#define BIT_TX_BCN_OK_INT15 BIT(15) +#define BIT_TX_BCN_OK_INT14 BIT(14) +#define BIT_TX_BCN_OK_INT13 BIT(13) +#define BIT_TX_BCN_OK_INT12 BIT(12) +#define BIT_TX_BCN_OK_INT11 BIT(11) +#define BIT_TX_BCN_OK_INT10 BIT(10) +#define BIT_TX_BCN_OK_INT9 BIT(9) +#define BIT_TX_BCN_OK_INT8 BIT(8) +#define BIT_BCN_DMA_INT15 BIT(7) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT4_RXUCMD1_OK_INT BIT(14) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ +#define BIT_HOST_INTERFACE_IO_PATH BIT(7) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HISR4 (Offset 0x1094) */ -#define BIT_FS_CLI3_RX_UMD1_INT BIT(14) +#define BIT_BCN_DMA_INT14 BIT(6) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ +#define BIT_EN_TXDMA_OFLD BIT(6) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT4_RXBCMD0_OK_INT BIT(13) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_HISR4 (Offset 0x1094) */ +#define BIT_BCN_DMA_INT13 BIT(5) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ -#define BIT_FS_CLI3_RX_BMD0_INT BIT(13) +#define BIT_EN_RXDMA_OFLD BIT(5) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HISR4 (Offset 0x1094) */ +#define BIT_BCN_DMA_INT12 BIT(4) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT4_RXBCMD1_OK_INT BIT(12) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ +#define BIT_EN_HCI_DMA_TX BIT(4) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HISR4 (Offset 0x1094) */ -#define BIT_FS_CLI3_RX_BMD1_INT BIT(12) +#define BIT_BCN_DMA_INT11 BIT(3) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ +#define BIT_EN_HCI_DMA_RX BIT(3) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT3_RXUCMD0_OK_INT BIT(11) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_HISR4 (Offset 0x1094) */ +#define BIT_BCN_DMA_INT10 BIT(2) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ -#define BIT_FS_CLI2_RX_UMD0_INT BIT(11) +#define BIT_EN_AXI_DMA_TX BIT(2) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HISR4 (Offset 0x1094) */ +#define BIT_BCN_DMA_INT9 BIT(1) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT3_RXUCMD1_OK_INT BIT(10) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ +#define BIT_EN_AXI_DMA_RX BIT(1) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HISR4 (Offset 0x1094) */ -#define BIT_FS_CLI2_RX_UMD1_INT BIT(10) +#define BIT_BCN_DMA_INT8 BIT(0) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ +#define BIT_EN_PKT_ENG BIT(0) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT3_RXBCMD0_OK_INT BIT(9) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_HIMR5 (Offset 0x1098) */ +#define BIT_BCN_QDMA_ERR_INT15_MSK BIT(7) +#define BIT_BCN_QDMA_ERR_INT14_MSK BIT(6) +#define BIT_BCN_QDMA_ERR_INT13_MSK BIT(5) +#define BIT_BCN_QDMA_ERR_INT12_MSK BIT(4) +#define BIT_BCN_QDMA_ERR_INT11_MSK BIT(3) +#define BIT_BCN_QDMA_ERR_INT10_MSK BIT(2) +#define BIT_BCN_QDMA_ERR_INT9_MSK BIT(1) +#define BIT_BCN_QDMA_ERR_INT8_MSK BIT(0) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_TXDMA_STOP_HIMR (Offset 0x1098) */ -#define BIT_FS_CLI2_RX_BMD0_INT BIT(9) +#define BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK 0 +#define BIT_MASK_NTH_TXDMA_STOP_INT_MSK 0x1ffff +#define BIT_NTH_TXDMA_STOP_INT_MSK(x) \ + (((x) & BIT_MASK_NTH_TXDMA_STOP_INT_MSK) \ + << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK) +#define BITS_NTH_TXDMA_STOP_INT_MSK \ + (BIT_MASK_NTH_TXDMA_STOP_INT_MSK << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK) +#define BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK(x) \ + ((x) & (~BITS_NTH_TXDMA_STOP_INT_MSK)) +#define BIT_GET_NTH_TXDMA_STOP_INT_MSK(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK) & \ + BIT_MASK_NTH_TXDMA_STOP_INT_MSK) +#define BIT_SET_NTH_TXDMA_STOP_INT_MSK(x, v) \ + (BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK(x) | BIT_NTH_TXDMA_STOP_INT_MSK(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HISR5 (Offset 0x109C) */ +#define BIT_BCN_QDMA_ERR_INT15 BIT(7) +#define BIT_BCN_QDMA_ERR_INT14 BIT(6) +#define BIT_BCN_QDMA_ERR_INT13 BIT(5) +#define BIT_BCN_QDMA_ERR_INT12 BIT(4) +#define BIT_BCN_QDMA_ERR_INT11 BIT(3) +#define BIT_BCN_QDMA_ERR_INT10 BIT(2) +#define BIT_BCN_QDMA_ERR_INT9 BIT(1) +#define BIT_BCN_QDMA_ERR_INT8 BIT(0) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT3_RXBCMD1_OK_INT BIT(8) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_TXDMA_STOP_HISR (Offset 0x109C) */ +#define BIT_SHIFT_NTH_TXDMA_STOP_INT 0 +#define BIT_MASK_NTH_TXDMA_STOP_INT 0x1ffff +#define BIT_NTH_TXDMA_STOP_INT(x) \ + (((x) & BIT_MASK_NTH_TXDMA_STOP_INT) << BIT_SHIFT_NTH_TXDMA_STOP_INT) +#define BITS_NTH_TXDMA_STOP_INT \ + (BIT_MASK_NTH_TXDMA_STOP_INT << BIT_SHIFT_NTH_TXDMA_STOP_INT) +#define BIT_CLEAR_NTH_TXDMA_STOP_INT(x) ((x) & (~BITS_NTH_TXDMA_STOP_INT)) +#define BIT_GET_NTH_TXDMA_STOP_INT(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT) & BIT_MASK_NTH_TXDMA_STOP_INT) +#define BIT_SET_NTH_TXDMA_STOP_INT(x, v) \ + (BIT_CLEAR_NTH_TXDMA_STOP_INT(x) | BIT_NTH_TXDMA_STOP_INT(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_START_HIMR (Offset 0x10A0) */ +#define BIT_SHIFT_NTH_TXDMA_START_INT_MSK 0 +#define BIT_MASK_NTH_TXDMA_START_INT_MSK 0x1ffff +#define BIT_NTH_TXDMA_START_INT_MSK(x) \ + (((x) & BIT_MASK_NTH_TXDMA_START_INT_MSK) \ + << BIT_SHIFT_NTH_TXDMA_START_INT_MSK) +#define BITS_NTH_TXDMA_START_INT_MSK \ + (BIT_MASK_NTH_TXDMA_START_INT_MSK << BIT_SHIFT_NTH_TXDMA_START_INT_MSK) +#define BIT_CLEAR_NTH_TXDMA_START_INT_MSK(x) \ + ((x) & (~BITS_NTH_TXDMA_START_INT_MSK)) +#define BIT_GET_NTH_TXDMA_START_INT_MSK(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_MSK) & \ + BIT_MASK_NTH_TXDMA_START_INT_MSK) +#define BIT_SET_NTH_TXDMA_START_INT_MSK(x, v) \ + (BIT_CLEAR_NTH_TXDMA_START_INT_MSK(x) | BIT_NTH_TXDMA_START_INT_MSK(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_TXDMA_START_HISR (Offset 0x10A4) */ -#define BIT_FS_CLI2_RX_BMD1_INT BIT(8) +#define BIT_SHIFT_NTH_TXDMA_START_INT 0 +#define BIT_MASK_NTH_TXDMA_START_INT 0x1ffff +#define BIT_NTH_TXDMA_START_INT(x) \ + (((x) & BIT_MASK_NTH_TXDMA_START_INT) << BIT_SHIFT_NTH_TXDMA_START_INT) +#define BITS_NTH_TXDMA_START_INT \ + (BIT_MASK_NTH_TXDMA_START_INT << BIT_SHIFT_NTH_TXDMA_START_INT) +#define BIT_CLEAR_NTH_TXDMA_START_INT(x) ((x) & (~BITS_NTH_TXDMA_START_INT)) +#define BIT_GET_NTH_TXDMA_START_INT(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT) & BIT_MASK_NTH_TXDMA_START_INT) +#define BIT_SET_NTH_TXDMA_START_INT(x, v) \ + (BIT_CLEAR_NTH_TXDMA_START_INT(x) | BIT_NTH_TXDMA_START_INT(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_NFCPAD_CTRL (Offset 0x10A8) */ +#define BIT_PAD_SHUTDW BIT(18) +#define BIT_SYSON_NFC_PAD BIT(17) +#define BIT_NFC_INT_PAD_CTRL BIT(16) +#define BIT_NFC_RFDIS_PAD_CTRL BIT(15) +#define BIT_NFC_CLK_PAD_CTRL BIT(14) +#define BIT_NFC_DATA_PAD_CTRL BIT(13) +#define BIT_NFC_PAD_PULL_CTRL BIT(12) + +#define BIT_SHIFT_NFCPAD_IO_SEL 8 +#define BIT_MASK_NFCPAD_IO_SEL 0xf +#define BIT_NFCPAD_IO_SEL(x) \ + (((x) & BIT_MASK_NFCPAD_IO_SEL) << BIT_SHIFT_NFCPAD_IO_SEL) +#define BITS_NFCPAD_IO_SEL (BIT_MASK_NFCPAD_IO_SEL << BIT_SHIFT_NFCPAD_IO_SEL) +#define BIT_CLEAR_NFCPAD_IO_SEL(x) ((x) & (~BITS_NFCPAD_IO_SEL)) +#define BIT_GET_NFCPAD_IO_SEL(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IO_SEL) & BIT_MASK_NFCPAD_IO_SEL) +#define BIT_SET_NFCPAD_IO_SEL(x, v) \ + (BIT_CLEAR_NFCPAD_IO_SEL(x) | BIT_NFCPAD_IO_SEL(v)) + +#define BIT_SHIFT_NFCPAD_OUT 4 +#define BIT_MASK_NFCPAD_OUT 0xf +#define BIT_NFCPAD_OUT(x) (((x) & BIT_MASK_NFCPAD_OUT) << BIT_SHIFT_NFCPAD_OUT) +#define BITS_NFCPAD_OUT (BIT_MASK_NFCPAD_OUT << BIT_SHIFT_NFCPAD_OUT) +#define BIT_CLEAR_NFCPAD_OUT(x) ((x) & (~BITS_NFCPAD_OUT)) +#define BIT_GET_NFCPAD_OUT(x) \ + (((x) >> BIT_SHIFT_NFCPAD_OUT) & BIT_MASK_NFCPAD_OUT) +#define BIT_SET_NFCPAD_OUT(x, v) (BIT_CLEAR_NFCPAD_OUT(x) | BIT_NFCPAD_OUT(v)) + +#define BIT_SHIFT_NFCPAD_IN 0 +#define BIT_MASK_NFCPAD_IN 0xf +#define BIT_NFCPAD_IN(x) (((x) & BIT_MASK_NFCPAD_IN) << BIT_SHIFT_NFCPAD_IN) +#define BITS_NFCPAD_IN (BIT_MASK_NFCPAD_IN << BIT_SHIFT_NFCPAD_IN) +#define BIT_CLEAR_NFCPAD_IN(x) ((x) & (~BITS_NFCPAD_IN)) +#define BIT_GET_NFCPAD_IN(x) (((x) >> BIT_SHIFT_NFCPAD_IN) & BIT_MASK_NFCPAD_IN) +#define BIT_SET_NFCPAD_IN(x, v) (BIT_CLEAR_NFCPAD_IN(x) | BIT_NFCPAD_IN(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HIMR2 (Offset 0x10B0) */ -#define BIT_PORT2_RXUCMD0_OK_INT BIT(7) +#define BIT_BCNDMAINT_P4_MSK BIT(31) +#define BIT_BCNDMAINT_P4 BIT(31) +#define BIT_BCNDMAINT_P3_MSK BIT(30) +#define BIT_BCNDMAINT_P3 BIT(30) +#define BIT_BCNDMAINT_P2_MSK BIT(29) +#define BIT_BCNDMAINT_P2 BIT(29) +#define BIT_BCNDMAINT_P1_MSK BIT(28) +#define BIT_BCNDMAINT_P1 BIT(28) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HIMR2 (Offset 0x10B0) */ -#define BIT_FS_CLI1_RX_UMD0_INT BIT(7) +#define BIT_SCH_PHY_TXOP_SIFS_INT_MSK BIT(23) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HIMR2 (Offset 0x10B0) */ +#define BIT_ATIMEND7_MSK BIT(22) +#define BIT_ATIMEND7 BIT(22) +#define BIT_ATIMEND6_MSK BIT(21) +#define BIT_ATIMEND6 BIT(21) +#define BIT_ATIMEND5_MSK BIT(20) +#define BIT_ATIMEND5 BIT(20) +#define BIT_ATIMEND4_MSK BIT(19) +#define BIT_ATIMEND4 BIT(19) +#define BIT_ATIMEND3_MSK BIT(18) +#define BIT_ATIMEND3 BIT(18) +#define BIT_ATIMEND2_MSK BIT(17) +#define BIT_ATIMEND2 BIT(17) +#define BIT_ATIMEND1_MSK BIT(16) +#define BIT_ATIMEND1 BIT(16) +#define BIT_TXBCN7OK_MSK BIT(14) +#define BIT_TXBCN7OK BIT(14) +#define BIT_TXBCN6OK_MSK BIT(13) +#define BIT_TXBCN6OK BIT(13) +#define BIT_TXBCN5OK_MSK BIT(12) +#define BIT_TXBCN5OK BIT(12) +#define BIT_TXBCN4OK_MSK BIT(11) +#define BIT_TXBCN4OK BIT(11) +#define BIT_TXBCN3OK_MSK BIT(10) +#define BIT_TXBCN3OK BIT(10) +#define BIT_TXBCN2OK_MSK BIT(9) +#define BIT_TXBCN2OK BIT(9) +#define BIT_TXBCN1OK_MSK_V1 BIT(8) +#define BIT_TXBCN1OK BIT(8) +#define BIT_TXBCN7ERR_MSK BIT(6) +#define BIT_TXBCN7ERR BIT(6) +#define BIT_TXBCN6ERR_MSK BIT(5) +#define BIT_TXBCN6ERR BIT(5) +#define BIT_TXBCN5ERR_MSK BIT(4) +#define BIT_TXBCN5ERR BIT(4) +#define BIT_TXBCN4ERR_MSK BIT(3) +#define BIT_TXBCN4ERR BIT(3) +#define BIT_TXBCN3ERR_MSK BIT(2) +#define BIT_TXBCN3ERR BIT(2) +#define BIT_TXBCN2ERR_MSK BIT(1) +#define BIT_TXBCN2ERR BIT(1) +#define BIT_TXBCN1ERR_MSK_V1 BIT(0) +#define BIT_TXBCN1ERR BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HIMR3 (Offset 0x10B8) */ -#define BIT_PORT2_RXUCMD1_OK_INT BIT(6) +#define BIT_GTINT12 BIT(24) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_GTINT12_MSK BIT(24) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_FS_CLI1_RX_UMD1_INT BIT(6) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_GTINT11 BIT(23) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HIMR3 (Offset 0x10B8) */ -#define BIT_PORT2_RXBCMD0_OK_INT BIT(5) +#define BIT_GTINT11_MSK BIT(23) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_GTINT10 BIT(22) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_FS_CLI1_RX_BMD0_INT BIT(5) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_GTINT10_MSK BIT(22) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HIMR3 (Offset 0x10B8) */ -#define BIT_PORT2_RXBCMD1_OK_INT BIT(4) +#define BIT_GTINT9 BIT(21) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_GTINT9_MSK BIT(21) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_FS_CLI1_RX_BMD1_INT BIT(4) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_RX_DESC_BUF_FULL BIT(20) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HIMR3 (Offset 0x10B8) */ -#define BIT_PORT1_RXUCMD0_OK_INT BIT(3) +#define BIT_RX_DESC_BUF_FULL_MSK BIT(20) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_CPHY_LDO_OCP_DET_INT BIT(19) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_FS_CLI0_RX_UMD0_INT BIT(3) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_CPHY_LDO_OCP_DET_INT_MSK BIT(19) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HIMR3 (Offset 0x10B8) */ -#define BIT_PORT1_RXUCMD1_OK_INT BIT(2) +#define BIT_WDT_PLATFORM_INT_MSK BIT(18) +#define BIT_WDT_PLATFORM_INT BIT(18) +#define BIT_WDT_CPU_INT_MSK BIT(17) +#define BIT_WDT_CPU_INT BIT(17) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_SETH2CDOK_MASK BIT(16) +#define BIT_SETH2CDOK BIT(16) +#define BIT_H2C_CMD_FULL_MASK BIT(15) +#define BIT_H2C_CMD_FULL BIT(15) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_FS_DMEM1_WPTR_UPDATE_INT BIT(2) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_PWR_INT_127_MASK BIT(14) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HIMR3 (Offset 0x10B8) */ -#define BIT_FS_CLI0_RX_UMD1_INT BIT(2) +#define BIT_PKT_TRANS_ERR BIT(14) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_PKT_TRANS_ERR_MASK BIT(14) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT1_RXBCMD0_OK_INT BIT(1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK BIT(13) +#define BIT_TXSHORTCUT_TXDESUPDATEOK BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_MASK BIT(12) +#define BIT_TXSHORTCUT_BKUPDATEOK BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_MASK BIT(11) +#define BIT_TXSHORTCUT_BEUPDATEOK BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_MAS BIT(10) +#define BIT_TXSHORTCUT_VIUPDATEOK BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_MASK BIT(9) +#define BIT_TXSHORTCUT_VOUPDATEOK BIT(9) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HIMR3 (Offset 0x10B8) */ -#define BIT_FS_CLI0_RX_BMD0_INT BIT(1) +#define BIT_PWR_INT_127_MASK_V1 BIT(8) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_SEARCH_FAIL BIT(8) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT1_RXBCMD1_OK_INT BIT(0) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_SEARCH_FAIL_MSK BIT(8) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_HIMR3 (Offset 0x10B8) */ -#define BIT_FS_CLI0_RX_BMD1_INT BIT(0) +#define BIT_PWR_INT_126TO96_MASK BIT(7) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_PWR_INT_127TO96 BIT(7) -/* 2 REG_FT1IMR (Offset 0x1138) */ +#endif -#define BIT__FT2ISR__IND_MSK BIT(30) -#define BIT_FTM_PTT_INT_EN BIT(29) -#define BIT_RXFTMREQ_INT_EN BIT(28) -#define BIT_RXFTM_INT_EN BIT(27) -#define BIT_TXFTM_INT_EN BIT(26) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_HIMR3 (Offset 0x10B8) */ +#define BIT_PWR_INT_127TO96_MASK BIT(7) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT1IMR (Offset 0x1138) */ +/* 2 REG_HIMR3 (Offset 0x10B8) */ -#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25) -#define BIT_FS_H2C_CMD_FULL_INT_EN BIT(24) +#define BIT_PWR_INT_95TO64_MASK BIT(6) +#define BIT_PWR_INT_95TO64 BIT(6) +#define BIT_PWR_INT_63TO32_MASK BIT(5) +#define BIT_PWR_INT_63TO32 BIT(5) +#define BIT_PWR_INT_31TO0_MASK BIT(4) +#define BIT_PWR_INT_31TO0 BIT(4) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_HIMR3 (Offset 0x10B8) */ -/* 2 REG_FT1IMR (Offset 0x1138) */ +#define BIT_RX_DMA_STUCK_MSK BIT(3) +#define BIT_RX_DMA_STUCK BIT(3) +#define BIT_TX_DMA_STUCK_MSK BIT(2) +#define BIT_TX_DMA_STUCK BIT(2) -#define BIT_FS_MACID_PWRCHANGE5_INT_EN BIT(23) -#define BIT_FS_MACID_PWRCHANGE4_INT_EN BIT(22) -#define BIT_FS_MACID_PWRCHANGE3_INT_EN BIT(21) -#define BIT_FS_MACID_PWRCHANGE2_INT_EN BIT(20) -#define BIT_FS_MACID_PWRCHANGE1_INT_EN BIT(19) -#define BIT_FS_MACID_PWRCHANGE0_INT_EN BIT(18) -#define BIT_FS_CTWEND2_INT_EN BIT(17) -#define BIT_FS_CTWEND1_INT_EN BIT(16) -#define BIT_FS_CTWEND0_INT_EN BIT(15) -#define BIT_FS_TX_NULL1_INT_EN BIT(14) -#define BIT_FS_TX_NULL0_INT_EN BIT(13) -#define BIT_FS_TSF_BIT32_TOGGLE_EN BIT(12) -#define BIT_FS_P2P_RFON2_INT_EN BIT(11) -#define BIT_FS_P2P_RFOFF2_INT_EN BIT(10) -#define BIT_FS_P2P_RFON1_INT_EN BIT(9) -#define BIT_FS_P2P_RFOFF1_INT_EN BIT(8) -#define BIT_FS_P2P_RFON0_INT_EN BIT(7) -#define BIT_FS_P2P_RFOFF0_INT_EN BIT(6) -#define BIT_FS_RX_UAPSDMD1_EN BIT(5) -#define BIT_FS_RX_UAPSDMD0_EN BIT(4) -#define BIT_FS_TRIGGER_PKT_EN BIT(3) -#define BIT_FS_EOSP_INT_EN BIT(2) -#define BIT_FS_RPWM2_INT_EN BIT(1) -#define BIT_FS_RPWM_INT_EN BIT(0) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT1ISR (Offset 0x113C) */ +/* 2 REG_HIMR3 (Offset 0x10B8) */ -#define BIT__FT2ISR__IND_INT BIT(30) -#define BIT_FTM_PTT_INT BIT(29) -#define BIT_RXFTMREQ_INT BIT(28) -#define BIT_RXFTM_INT BIT(27) -#define BIT_TXFTM_INT BIT(26) +#define BIT_DDMA0_LP_INT_MSK BIT(1) +#define BIT_DDMA0_LP_INT BIT(1) +#define BIT_DDMA0_HP_INT_MSK BIT(0) +#define BIT_DDMA0_HP_INT BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FT1ISR (Offset 0x113C) */ +/* 2 REG_HISR3 (Offset 0x10BC) */ -#define BIT_FS_H2C_CMD_OK_INT BIT(25) -#define BIT_FS_H2C_CMD_FULL_INT BIT(24) +#define BIT_PWR_INT_127 BIT(14) +#define BIT_PWR_INT_127_V1 BIT(8) +#define BIT_PWR_INT_126TO96 BIT(7) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SW_MDIO (Offset 0x10C0) */ +#define BIT_DIS_TIMEOUT_IO BIT(24) -/* 2 REG_FT1ISR (Offset 0x113C) */ +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_FS_MACID_PWRCHANGE5_INT BIT(23) -#define BIT_FS_MACID_PWRCHANGE4_INT BIT(22) -#define BIT_FS_MACID_PWRCHANGE3_INT BIT(21) -#define BIT_FS_MACID_PWRCHANGE2_INT BIT(20) -#define BIT_FS_MACID_PWRCHANGE1_INT BIT(19) -#define BIT_FS_MACID_PWRCHANGE0_INT BIT(18) -#define BIT_FS_CTWEND2_INT BIT(17) -#define BIT_FS_CTWEND1_INT BIT(16) -#define BIT_FS_CTWEND0_INT BIT(15) -#define BIT_FS_TX_NULL1_INT BIT(14) -#define BIT_FS_TX_NULL0_INT BIT(13) -#define BIT_FS_TSF_BIT32_TOGGLE_INT BIT(12) -#define BIT_FS_P2P_RFON2_INT BIT(11) -#define BIT_FS_P2P_RFOFF2_INT BIT(10) -#define BIT_FS_P2P_RFON1_INT BIT(9) -#define BIT_FS_P2P_RFOFF1_INT BIT(8) -#define BIT_FS_P2P_RFON0_INT BIT(7) -#define BIT_FS_P2P_RFOFF0_INT BIT(6) -#define BIT_FS_RX_UAPSDMD1_INT BIT(5) -#define BIT_FS_RX_UAPSDMD0_INT BIT(4) -#define BIT_FS_TRIGGER_PKT_INT BIT(3) -#define BIT_FS_EOSP_INT BIT(2) -#define BIT_FS_RPWM2_INT BIT(1) -#define BIT_FS_RPWM_INT BIT(0) +/* 2 REG_SW_MDIO (Offset 0x10C0) */ -/* 2 REG_SPWR0 (Offset 0x1140) */ +#define BIT_SUS_PL BIT(18) +#define BIT_SOP_ESUS BIT(17) +#define BIT_SOP_DLDO BIT(16) +#define BIT_R_OCP_ST_CLR BIT(8) +#define BIT_SW_USB3_MD_SEL BIT(5) +#define BIT_SW_PCIE_MD_SEL BIT(4) +#define BIT_SW_MDCK BIT(2) +#define BIT_SW_MDI BIT(1) +#define BIT_MDO BIT(0) +#endif -#define BIT_SHIFT_MID_31TO0 0 -#define BIT_MASK_MID_31TO0 0xffffffffL -#define BIT_MID_31TO0(x) (((x) & BIT_MASK_MID_31TO0) << BIT_SHIFT_MID_31TO0) -#define BIT_GET_MID_31TO0(x) (((x) >> BIT_SHIFT_MID_31TO0) & BIT_MASK_MID_31TO0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SW_FLUSH (Offset 0x10C4) */ -/* 2 REG_SPWR1 (Offset 0x1144) */ +#define BIT_FLUSH_HOLDN_EN BIT(25) +#define BIT_FLUSH_WR_EN BIT(24) +#define BIT_SW_FLASH_CONTROL BIT(23) +#define BIT_SW_FLASH_WEN_E BIT(19) +#define BIT_SW_FLASH_HOLDN_E BIT(18) +#define BIT_SW_FLASH_SO_E BIT(17) +#define BIT_SW_FLASH_SI_E BIT(16) +#define BIT_SW_FLASH_SK_O BIT(13) +#define BIT_SW_FLASH_CEN_O BIT(12) +#define BIT_SW_FLASH_WEN_O BIT(11) +#define BIT_SW_FLASH_HOLDN_O BIT(10) +#define BIT_SW_FLASH_SO_O BIT(9) +#define BIT_SW_FLASH_SI_O BIT(8) +#define BIT_SW_FLASH_WEN_I BIT(3) +#define BIT_SW_FLASH_HOLDN_I BIT(2) +#define BIT_SW_FLASH_SO_I BIT(1) +#define BIT_SW_FLASH_SI_I BIT(0) +#endif -#define BIT_SHIFT_MID_63TO32 0 -#define BIT_MASK_MID_63TO32 0xffffffffL -#define BIT_MID_63TO32(x) (((x) & BIT_MASK_MID_63TO32) << BIT_SHIFT_MID_63TO32) -#define BIT_GET_MID_63TO32(x) (((x) >> BIT_SHIFT_MID_63TO32) & BIT_MASK_MID_63TO32) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_HIMR_7 (Offset 0x10C8) */ -/* 2 REG_SPWR2 (Offset 0x1148) */ +#define BIT_DATA_CPU_WDT_INT_MSK BIT(31) +#define BIT_OFLD_TXDMA_ERR_MSK BIT(30) +#define BIT_OFLD_TXDMA_FULL_MSK BIT(29) +#define BIT_OFLD_RXDMA_OVR_MSK BIT(28) +#define BIT_OFLD_RXDMA_ERR_MSK BIT(27) +#define BIT_OFLD_RXDMA_DES_UA_MSK BIT(26) +#endif -#define BIT_SHIFT_MID_95O64 0 -#define BIT_MASK_MID_95O64 0xffffffffL -#define BIT_MID_95O64(x) (((x) & BIT_MASK_MID_95O64) << BIT_SHIFT_MID_95O64) -#define BIT_GET_MID_95O64(x) (((x) >> BIT_SHIFT_MID_95O64) & BIT_MASK_MID_95O64) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ -/* 2 REG_SPWR3 (Offset 0x114C) */ +#define BIT_SHIFT_DBG_GPIO_BMUX_7 21 +#define BIT_MASK_DBG_GPIO_BMUX_7 0x7 +#define BIT_DBG_GPIO_BMUX_7(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_7) << BIT_SHIFT_DBG_GPIO_BMUX_7) +#define BITS_DBG_GPIO_BMUX_7 \ + (BIT_MASK_DBG_GPIO_BMUX_7 << BIT_SHIFT_DBG_GPIO_BMUX_7) +#define BIT_CLEAR_DBG_GPIO_BMUX_7(x) ((x) & (~BITS_DBG_GPIO_BMUX_7)) +#define BIT_GET_DBG_GPIO_BMUX_7(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7) & BIT_MASK_DBG_GPIO_BMUX_7) +#define BIT_SET_DBG_GPIO_BMUX_7(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_7(x) | BIT_DBG_GPIO_BMUX_7(v)) +#define BIT_SHIFT_DBG_GPIO_BMUX_6 18 +#define BIT_MASK_DBG_GPIO_BMUX_6 0x7 +#define BIT_DBG_GPIO_BMUX_6(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_6) << BIT_SHIFT_DBG_GPIO_BMUX_6) +#define BITS_DBG_GPIO_BMUX_6 \ + (BIT_MASK_DBG_GPIO_BMUX_6 << BIT_SHIFT_DBG_GPIO_BMUX_6) +#define BIT_CLEAR_DBG_GPIO_BMUX_6(x) ((x) & (~BITS_DBG_GPIO_BMUX_6)) +#define BIT_GET_DBG_GPIO_BMUX_6(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6) & BIT_MASK_DBG_GPIO_BMUX_6) +#define BIT_SET_DBG_GPIO_BMUX_6(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_6(x) | BIT_DBG_GPIO_BMUX_6(v)) -#define BIT_SHIFT_MID_127TO96 0 -#define BIT_MASK_MID_127TO96 0xffffffffL -#define BIT_MID_127TO96(x) (((x) & BIT_MASK_MID_127TO96) << BIT_SHIFT_MID_127TO96) -#define BIT_GET_MID_127TO96(x) (((x) >> BIT_SHIFT_MID_127TO96) & BIT_MASK_MID_127TO96) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_POWSEQ (Offset 0x1150) */ +/* 2 REG_HIMR_7 (Offset 0x10C8) */ +#define BIT_TXDMAOK_CHANNEL_16_MSK BIT(16) -#define BIT_SHIFT_SEQNUM_MID 16 -#define BIT_MASK_SEQNUM_MID 0xffff -#define BIT_SEQNUM_MID(x) (((x) & BIT_MASK_SEQNUM_MID) << BIT_SHIFT_SEQNUM_MID) -#define BIT_GET_SEQNUM_MID(x) (((x) >> BIT_SHIFT_SEQNUM_MID) & BIT_MASK_SEQNUM_MID) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_REF_MID 0 -#define BIT_MASK_REF_MID 0x7f -#define BIT_REF_MID(x) (((x) & BIT_MASK_REF_MID) << BIT_SHIFT_REF_MID) -#define BIT_GET_REF_MID(x) (((x) >> BIT_SHIFT_REF_MID) & BIT_MASK_REF_MID) +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ +#define BIT_SHIFT_DBG_GPIO_BMUX_5 15 +#define BIT_MASK_DBG_GPIO_BMUX_5 0x7 +#define BIT_DBG_GPIO_BMUX_5(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_5) << BIT_SHIFT_DBG_GPIO_BMUX_5) +#define BITS_DBG_GPIO_BMUX_5 \ + (BIT_MASK_DBG_GPIO_BMUX_5 << BIT_SHIFT_DBG_GPIO_BMUX_5) +#define BIT_CLEAR_DBG_GPIO_BMUX_5(x) ((x) & (~BITS_DBG_GPIO_BMUX_5)) +#define BIT_GET_DBG_GPIO_BMUX_5(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5) & BIT_MASK_DBG_GPIO_BMUX_5) +#define BIT_SET_DBG_GPIO_BMUX_5(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_5(x) | BIT_DBG_GPIO_BMUX_5(v)) -/* 2 REG_TC7_CTRL_V1 (Offset 0x1158) */ +#endif -#define BIT_TC7INT_EN BIT(26) -#define BIT_TC7MODE BIT(25) -#define BIT_TC7EN BIT(24) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TC7DATA 0 -#define BIT_MASK_TC7DATA 0xffffff -#define BIT_TC7DATA(x) (((x) & BIT_MASK_TC7DATA) << BIT_SHIFT_TC7DATA) -#define BIT_GET_TC7DATA(x) (((x) >> BIT_SHIFT_TC7DATA) & BIT_MASK_TC7DATA) +/* 2 REG_HIMR_7 (Offset 0x10C8) */ +#define BIT_TXDMAOK_CHANNEL_13_MSK BIT(13) -/* 2 REG_TC8_CTRL_V1 (Offset 0x115C) */ +#endif -#define BIT_TC8INT_EN BIT(26) -#define BIT_TC8MODE BIT(25) -#define BIT_TC8EN BIT(24) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_TC8DATA 0 -#define BIT_MASK_TC8DATA 0xffffff -#define BIT_TC8DATA(x) (((x) & BIT_MASK_TC8DATA) << BIT_SHIFT_TC8DATA) -#define BIT_GET_TC8DATA(x) (((x) >> BIT_SHIFT_TC8DATA) & BIT_MASK_TC8DATA) +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ +#define BIT_SHIFT_DBG_GPIO_BMUX_4 12 +#define BIT_MASK_DBG_GPIO_BMUX_4 0x7 +#define BIT_DBG_GPIO_BMUX_4(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_4) << BIT_SHIFT_DBG_GPIO_BMUX_4) +#define BITS_DBG_GPIO_BMUX_4 \ + (BIT_MASK_DBG_GPIO_BMUX_4 << BIT_SHIFT_DBG_GPIO_BMUX_4) +#define BIT_CLEAR_DBG_GPIO_BMUX_4(x) ((x) & (~BITS_DBG_GPIO_BMUX_4)) +#define BIT_GET_DBG_GPIO_BMUX_4(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4) & BIT_MASK_DBG_GPIO_BMUX_4) +#define BIT_SET_DBG_GPIO_BMUX_4(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_4(x) | BIT_DBG_GPIO_BMUX_4(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HIMR_7 (Offset 0x10C8) */ +#define BIT_TXDMAOK_CHANNEL_12_MSK BIT(12) +#define BIT_TXDMAOK_CHANNEL_11_MSK BIT(11) +#define BIT_TXDMAOK_CHANNEL_10_MSK BIT(10) -/* 2 REG_EXT_QUEUE_REG (Offset 0x11C0) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_PCIE_PRIORITY_SEL 0 -#define BIT_MASK_PCIE_PRIORITY_SEL 0x3 -#define BIT_PCIE_PRIORITY_SEL(x) (((x) & BIT_MASK_PCIE_PRIORITY_SEL) << BIT_SHIFT_PCIE_PRIORITY_SEL) -#define BIT_GET_PCIE_PRIORITY_SEL(x) (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL) & BIT_MASK_PCIE_PRIORITY_SEL) +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ +#define BIT_SHIFT_DBG_GPIO_BMUX_3 9 +#define BIT_MASK_DBG_GPIO_BMUX_3 0x7 +#define BIT_DBG_GPIO_BMUX_3(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_3) << BIT_SHIFT_DBG_GPIO_BMUX_3) +#define BITS_DBG_GPIO_BMUX_3 \ + (BIT_MASK_DBG_GPIO_BMUX_3 << BIT_SHIFT_DBG_GPIO_BMUX_3) +#define BIT_CLEAR_DBG_GPIO_BMUX_3(x) ((x) & (~BITS_DBG_GPIO_BMUX_3)) +#define BIT_GET_DBG_GPIO_BMUX_3(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3) & BIT_MASK_DBG_GPIO_BMUX_3) +#define BIT_SET_DBG_GPIO_BMUX_3(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_3(x) | BIT_DBG_GPIO_BMUX_3(v)) -/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_COUNTER_BASE 16 -#define BIT_MASK_COUNTER_BASE 0x1fff -#define BIT_COUNTER_BASE(x) (((x) & BIT_MASK_COUNTER_BASE) << BIT_SHIFT_COUNTER_BASE) -#define BIT_GET_COUNTER_BASE(x) (((x) >> BIT_SHIFT_COUNTER_BASE) & BIT_MASK_COUNTER_BASE) +/* 2 REG_HIMR_7 (Offset 0x10C8) */ -#define BIT_EN_RTS_REQ BIT(9) -#define BIT_EN_EDCA_REQ BIT(8) -#define BIT_EN_PTCL_REQ BIT(7) -#define BIT_EN_SCH_REQ BIT(6) -#define BIT_EN_USB_CNT BIT(5) -#define BIT_EN_PCIE_CNT BIT(4) -#define BIT_RQPN_CNT BIT(3) -#define BIT_RDE_CNT BIT(2) -#define BIT_TDE_CNT BIT(1) -#define BIT_DIS_CNT BIT(0) +#define BIT_TXDMAOK_CHANNEL_9_MSK BIT(9) +#define BIT_TXDMAOK_CHANNEL_8_MSK BIT(8) +#define BIT_TXDMAOK_CHANNEL_7_MSK BIT(7) -/* 2 REG_COUNTER_TH (Offset 0x11C8) */ +#endif -#define BIT_CNT_ALL_MACID BIT(31) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_CNT_MACID 24 -#define BIT_MASK_CNT_MACID 0x7f -#define BIT_CNT_MACID(x) (((x) & BIT_MASK_CNT_MACID) << BIT_SHIFT_CNT_MACID) -#define BIT_GET_CNT_MACID(x) (((x) >> BIT_SHIFT_CNT_MACID) & BIT_MASK_CNT_MACID) +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ +#define BIT_SHIFT_DBG_GPIO_BMUX_2 6 +#define BIT_MASK_DBG_GPIO_BMUX_2 0x7 +#define BIT_DBG_GPIO_BMUX_2(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_2) << BIT_SHIFT_DBG_GPIO_BMUX_2) +#define BITS_DBG_GPIO_BMUX_2 \ + (BIT_MASK_DBG_GPIO_BMUX_2 << BIT_SHIFT_DBG_GPIO_BMUX_2) +#define BIT_CLEAR_DBG_GPIO_BMUX_2(x) ((x) & (~BITS_DBG_GPIO_BMUX_2)) +#define BIT_GET_DBG_GPIO_BMUX_2(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2) & BIT_MASK_DBG_GPIO_BMUX_2) +#define BIT_SET_DBG_GPIO_BMUX_2(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_2(x) | BIT_DBG_GPIO_BMUX_2(v)) -#define BIT_SHIFT_AGG_VALUE2 16 -#define BIT_MASK_AGG_VALUE2 0x7f -#define BIT_AGG_VALUE2(x) (((x) & BIT_MASK_AGG_VALUE2) << BIT_SHIFT_AGG_VALUE2) -#define BIT_GET_AGG_VALUE2(x) (((x) >> BIT_SHIFT_AGG_VALUE2) & BIT_MASK_AGG_VALUE2) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_AGG_VALUE1 8 -#define BIT_MASK_AGG_VALUE1 0x7f -#define BIT_AGG_VALUE1(x) (((x) & BIT_MASK_AGG_VALUE1) << BIT_SHIFT_AGG_VALUE1) -#define BIT_GET_AGG_VALUE1(x) (((x) >> BIT_SHIFT_AGG_VALUE1) & BIT_MASK_AGG_VALUE1) +/* 2 REG_HIMR_7 (Offset 0x10C8) */ +#define BIT_TXDMAOK_CHANNEL_6_MSK BIT(6) +#define BIT_TXDMAOK_CHANNEL_5_MSK BIT(5) +#define BIT_TXDMAOK_CHANNEL_4_MSK BIT(4) -#define BIT_SHIFT_AGG_VALUE0 0 -#define BIT_MASK_AGG_VALUE0 0x7f -#define BIT_AGG_VALUE0(x) (((x) & BIT_MASK_AGG_VALUE0) << BIT_SHIFT_AGG_VALUE0) -#define BIT_GET_AGG_VALUE0(x) (((x) >> BIT_SHIFT_AGG_VALUE0) & BIT_MASK_AGG_VALUE0) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_COUNTER_SET (Offset 0x11CC) */ +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ -#define BIT_RTS_RST BIT(24) -#define BIT_PTCL_RST BIT(23) -#define BIT_SCH_RST BIT(22) -#define BIT_EDCA_RST BIT(21) -#define BIT_RQPN_RST BIT(20) -#define BIT_USB_RST BIT(19) -#define BIT_PCIE_RST BIT(18) -#define BIT_RXDMA_RST BIT(17) -#define BIT_TXDMA_RST BIT(16) -#define BIT_EN_RTS_START BIT(8) -#define BIT_EN_PTCL_START BIT(7) -#define BIT_EN_SCH_START BIT(6) -#define BIT_EN_EDCA_START BIT(5) -#define BIT_EN_RQPN_START BIT(4) -#define BIT_EN_USB_START BIT(3) -#define BIT_EN_PCIE_START BIT(2) -#define BIT_EN_RXDMA_START BIT(1) -#define BIT_EN_TXDMA_START BIT(0) +#define BIT_SHIFT_DBG_GPIO_BMUX_1 3 +#define BIT_MASK_DBG_GPIO_BMUX_1 0x7 +#define BIT_DBG_GPIO_BMUX_1(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_1) << BIT_SHIFT_DBG_GPIO_BMUX_1) +#define BITS_DBG_GPIO_BMUX_1 \ + (BIT_MASK_DBG_GPIO_BMUX_1 << BIT_SHIFT_DBG_GPIO_BMUX_1) +#define BIT_CLEAR_DBG_GPIO_BMUX_1(x) ((x) & (~BITS_DBG_GPIO_BMUX_1)) +#define BIT_GET_DBG_GPIO_BMUX_1(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1) & BIT_MASK_DBG_GPIO_BMUX_1) +#define BIT_SET_DBG_GPIO_BMUX_1(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_1(x) | BIT_DBG_GPIO_BMUX_1(v)) -/* 2 REG_COUNTER_OVERFLOW (Offset 0x11D0) */ +#define BIT_SHIFT_DBG_GPIO_BMUX_0 0 +#define BIT_MASK_DBG_GPIO_BMUX_0 0x7 +#define BIT_DBG_GPIO_BMUX_0(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_0) << BIT_SHIFT_DBG_GPIO_BMUX_0) +#define BITS_DBG_GPIO_BMUX_0 \ + (BIT_MASK_DBG_GPIO_BMUX_0 << BIT_SHIFT_DBG_GPIO_BMUX_0) +#define BIT_CLEAR_DBG_GPIO_BMUX_0(x) ((x) & (~BITS_DBG_GPIO_BMUX_0)) +#define BIT_GET_DBG_GPIO_BMUX_0(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0) & BIT_MASK_DBG_GPIO_BMUX_0) +#define BIT_SET_DBG_GPIO_BMUX_0(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_0(x) | BIT_DBG_GPIO_BMUX_0(v)) -#define BIT_RTS_OVF BIT(8) -#define BIT_PTCL_OVF BIT(7) -#define BIT_SCH_OVF BIT(6) -#define BIT_EDCA_OVF BIT(5) -#define BIT_RQPN_OVF BIT(4) -#define BIT_USB_OVF BIT(3) -#define BIT_PCIE_OVF BIT(2) -#define BIT_RXDMA_OVF BIT(1) -#define BIT_TXDMA_OVF BIT(0) +#endif -/* 2 REG_TDE_LEN_TH (Offset 0x11D4) */ +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_HISR_7 (Offset 0x10CC) */ -#define BIT_SHIFT_TXDMA_LEN_TH0 16 -#define BIT_MASK_TXDMA_LEN_TH0 0xffff -#define BIT_TXDMA_LEN_TH0(x) (((x) & BIT_MASK_TXDMA_LEN_TH0) << BIT_SHIFT_TXDMA_LEN_TH0) -#define BIT_GET_TXDMA_LEN_TH0(x) (((x) >> BIT_SHIFT_TXDMA_LEN_TH0) & BIT_MASK_TXDMA_LEN_TH0) +#define BIT_DATA_CPU_WDT_INT BIT(31) +#define BIT_OFLD_TXDMA_ERR BIT(30) +#define BIT_OFLD_TXDMA_FULL BIT(29) +#define BIT_OFLD_RXDMA_OVR BIT(28) +#endif -#define BIT_SHIFT_TXDMA_LEN_TH1 0 -#define BIT_MASK_TXDMA_LEN_TH1 0xffff -#define BIT_TXDMA_LEN_TH1(x) (((x) & BIT_MASK_TXDMA_LEN_TH1) << BIT_SHIFT_TXDMA_LEN_TH1) -#define BIT_GET_TXDMA_LEN_TH1(x) (((x) >> BIT_SHIFT_TXDMA_LEN_TH1) & BIT_MASK_TXDMA_LEN_TH1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) +/* 2 REG_FPGA_TAG (Offset 0x10CC) */ -/* 2 REG_RDE_LEN_TH (Offset 0x11D8) */ +#define BIT_WL_DSS_RSTN BIT(27) +#endif -#define BIT_SHIFT_RXDMA_LEN_TH0 16 -#define BIT_MASK_RXDMA_LEN_TH0 0xffff -#define BIT_RXDMA_LEN_TH0(x) (((x) & BIT_MASK_RXDMA_LEN_TH0) << BIT_SHIFT_RXDMA_LEN_TH0) -#define BIT_GET_RXDMA_LEN_TH0(x) (((x) >> BIT_SHIFT_RXDMA_LEN_TH0) & BIT_MASK_RXDMA_LEN_TH0) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_HISR_7 (Offset 0x10CC) */ -#define BIT_SHIFT_RXDMA_LEN_TH1 0 -#define BIT_MASK_RXDMA_LEN_TH1 0xffff -#define BIT_RXDMA_LEN_TH1(x) (((x) & BIT_MASK_RXDMA_LEN_TH1) << BIT_SHIFT_RXDMA_LEN_TH1) -#define BIT_GET_RXDMA_LEN_TH1(x) (((x) >> BIT_SHIFT_RXDMA_LEN_TH1) & BIT_MASK_RXDMA_LEN_TH1) +#define BIT_OFLD_RXDMA_ERR BIT(27) +#endif -/* 2 REG_PCIE_EXEC_TIME (Offset 0x11DC) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) +/* 2 REG_FPGA_TAG (Offset 0x10CC) */ + +#define BIT_WL_DSS_EN_CLK BIT(26) -#define BIT_SHIFT_COUNTER_INTERVAL_SEL 16 -#define BIT_MASK_COUNTER_INTERVAL_SEL 0x3 -#define BIT_COUNTER_INTERVAL_SEL(x) (((x) & BIT_MASK_COUNTER_INTERVAL_SEL) << BIT_SHIFT_COUNTER_INTERVAL_SEL) -#define BIT_GET_COUNTER_INTERVAL_SEL(x) (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL) & BIT_MASK_COUNTER_INTERVAL_SEL) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_PCIE_TRANS_DATA_TH1 0 -#define BIT_MASK_PCIE_TRANS_DATA_TH1 0xffff -#define BIT_PCIE_TRANS_DATA_TH1(x) (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1) << BIT_SHIFT_PCIE_TRANS_DATA_TH1) -#define BIT_GET_PCIE_TRANS_DATA_TH1(x) (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1) & BIT_MASK_PCIE_TRANS_DATA_TH1) +/* 2 REG_HISR_7 (Offset 0x10CC) */ +#define BIT_OFLD_RXDMA_DES_UA BIT(26) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_FPGA_TAG (Offset 0x10CC) */ -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#define BIT_WL_DSS_SPEED_EN BIT(25) +#define BIT_WL_DSS_WIRE_SEL BIT(24) -#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN BIT(31) +#define BIT_SHIFT_WL_DSS_RO_SEL 20 +#define BIT_MASK_WL_DSS_RO_SEL 0x7 +#define BIT_WL_DSS_RO_SEL(x) \ + (((x) & BIT_MASK_WL_DSS_RO_SEL) << BIT_SHIFT_WL_DSS_RO_SEL) +#define BITS_WL_DSS_RO_SEL (BIT_MASK_WL_DSS_RO_SEL << BIT_SHIFT_WL_DSS_RO_SEL) +#define BIT_CLEAR_WL_DSS_RO_SEL(x) ((x) & (~BITS_WL_DSS_RO_SEL)) +#define BIT_GET_WL_DSS_RO_SEL(x) \ + (((x) >> BIT_SHIFT_WL_DSS_RO_SEL) & BIT_MASK_WL_DSS_RO_SEL) +#define BIT_SET_WL_DSS_RO_SEL(x, v) \ + (BIT_CLEAR_WL_DSS_RO_SEL(x) | BIT_WL_DSS_RO_SEL(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_HISR_7 (Offset 0x10CC) */ -#define BIT_FS_CLI3_RX_UAPSDMD1_EN BIT(31) +#define BIT_TXDMAOK_CHANNEL_16 BIT(16) +#define BIT_TXDMAOK_CHANNEL_13 BIT(13) +#define BIT_TXDMAOK_CHANNEL_12 BIT(12) +#define BIT_TXDMAOK_CHANNEL_11 BIT(11) +#define BIT_TXDMAOK_CHANNEL_10 BIT(10) +#define BIT_TXDMAOK_CHANNEL_9 BIT(9) +#define BIT_TXDMAOK_CHANNEL_8 BIT(8) +#define BIT_TXDMAOK_CHANNEL_7 BIT(7) +#define BIT_TXDMAOK_CHANNEL_6 BIT(6) +#define BIT_TXDMAOK_CHANNEL_5 BIT(5) +#define BIT_TXDMAOK_CHANNEL_4 BIT(4) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_FPGA_TAG (Offset 0x10CC) */ -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#define BIT_SHIFT_FPGA_TAG 0 +#define BIT_MASK_FPGA_TAG 0xffffffffL +#define BIT_FPGA_TAG(x) (((x) & BIT_MASK_FPGA_TAG) << BIT_SHIFT_FPGA_TAG) +#define BITS_FPGA_TAG (BIT_MASK_FPGA_TAG << BIT_SHIFT_FPGA_TAG) +#define BIT_CLEAR_FPGA_TAG(x) ((x) & (~BITS_FPGA_TAG)) +#define BIT_GET_FPGA_TAG(x) (((x) >> BIT_SHIFT_FPGA_TAG) & BIT_MASK_FPGA_TAG) +#define BIT_SET_FPGA_TAG(x, v) (BIT_CLEAR_FPGA_TAG(x) | BIT_FPGA_TAG(v)) -#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN BIT(30) +#define BIT_SHIFT_WL_DSS_COUNT_OUT 0 +#define BIT_MASK_WL_DSS_COUNT_OUT 0xfffff +#define BIT_WL_DSS_COUNT_OUT(x) \ + (((x) & BIT_MASK_WL_DSS_COUNT_OUT) << BIT_SHIFT_WL_DSS_COUNT_OUT) +#define BITS_WL_DSS_COUNT_OUT \ + (BIT_MASK_WL_DSS_COUNT_OUT << BIT_SHIFT_WL_DSS_COUNT_OUT) +#define BIT_CLEAR_WL_DSS_COUNT_OUT(x) ((x) & (~BITS_WL_DSS_COUNT_OUT)) +#define BIT_GET_WL_DSS_COUNT_OUT(x) \ + (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT) & BIT_MASK_WL_DSS_COUNT_OUT) +#define BIT_SET_WL_DSS_COUNT_OUT(x, v) \ + (BIT_CLEAR_WL_DSS_COUNT_OUT(x) | BIT_WL_DSS_COUNT_OUT(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_H2C_PKT_READADDR (Offset 0x10D0) */ +#define BIT_SHIFT_H2C_PKT_READADDR 0 +#define BIT_MASK_H2C_PKT_READADDR 0x3ffff +#define BIT_H2C_PKT_READADDR(x) \ + (((x) & BIT_MASK_H2C_PKT_READADDR) << BIT_SHIFT_H2C_PKT_READADDR) +#define BITS_H2C_PKT_READADDR \ + (BIT_MASK_H2C_PKT_READADDR << BIT_SHIFT_H2C_PKT_READADDR) +#define BIT_CLEAR_H2C_PKT_READADDR(x) ((x) & (~BITS_H2C_PKT_READADDR)) +#define BIT_GET_H2C_PKT_READADDR(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_READADDR) & BIT_MASK_H2C_PKT_READADDR) +#define BIT_SET_H2C_PKT_READADDR(x, v) \ + (BIT_CLEAR_H2C_PKT_READADDR(x) | BIT_H2C_PKT_READADDR(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_H2C_PKT_WRITEADDR (Offset 0x10D4) */ -#define BIT_FS_CLI3_RX_UAPSDMD0_EN BIT(30) +#define BIT_SHIFT_H2C_PKT_WRITEADDR 0 +#define BIT_MASK_H2C_PKT_WRITEADDR 0x3ffff +#define BIT_H2C_PKT_WRITEADDR(x) \ + (((x) & BIT_MASK_H2C_PKT_WRITEADDR) << BIT_SHIFT_H2C_PKT_WRITEADDR) +#define BITS_H2C_PKT_WRITEADDR \ + (BIT_MASK_H2C_PKT_WRITEADDR << BIT_SHIFT_H2C_PKT_WRITEADDR) +#define BIT_CLEAR_H2C_PKT_WRITEADDR(x) ((x) & (~BITS_H2C_PKT_WRITEADDR)) +#define BIT_GET_H2C_PKT_WRITEADDR(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_PKT_WRITEADDR) +#define BIT_SET_H2C_PKT_WRITEADDR(x, v) \ + (BIT_CLEAR_H2C_PKT_WRITEADDR(x) | BIT_H2C_PKT_WRITEADDR(v)) -#endif +/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ +#define BIT_MEM_BB_SD BIT(17) +#define BIT_MEM_BB_DS BIT(16) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ -#define BIT_PORT4_TRIPKT_OK_INT_EN BIT(29) +#define BIT_MEM_DENG_LS BIT(13) +#define BIT_MEM_DENG_DS BIT(12) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ -#define BIT_FS_CLI3_TRIGGER_PKT_EN BIT(29) +#define BIT_MEM_BT_DS BIT(10) +#define BIT_MEM_SDIO_LS BIT(9) +#define BIT_MEM_SDIO_DS BIT(8) +#define BIT_MEM_USB_LS BIT(7) +#define BIT_MEM_USB_DS BIT(6) +#define BIT_MEM_PCI_LS BIT(5) +#define BIT_MEM_PCI_DS BIT(4) +#define BIT_MEM_WLMAC_LS BIT(3) +#define BIT_MEM_WLMAC_DS BIT(2) +#define BIT_MEM_WLMCU_LS BIT(1) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ +#define BIT_SHIFT_WL_DSS_DATA_IN 0 +#define BIT_MASK_WL_DSS_DATA_IN 0xfffff +#define BIT_WL_DSS_DATA_IN(x) \ + (((x) & BIT_MASK_WL_DSS_DATA_IN) << BIT_SHIFT_WL_DSS_DATA_IN) +#define BITS_WL_DSS_DATA_IN \ + (BIT_MASK_WL_DSS_DATA_IN << BIT_SHIFT_WL_DSS_DATA_IN) +#define BIT_CLEAR_WL_DSS_DATA_IN(x) ((x) & (~BITS_WL_DSS_DATA_IN)) +#define BIT_GET_WL_DSS_DATA_IN(x) \ + (((x) >> BIT_SHIFT_WL_DSS_DATA_IN) & BIT_MASK_WL_DSS_DATA_IN) +#define BIT_SET_WL_DSS_DATA_IN(x, v) \ + (BIT_CLEAR_WL_DSS_DATA_IN(x) | BIT_WL_DSS_DATA_IN(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT4_RX_EOSP_OK_INT_EN BIT(28) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ +#define BIT_MEM_WLMCU_DS BIT(0) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_WL_DSS_STATUS1 (Offset 0x10DC) */ -#define BIT_FS_CLI3_EOSP_INT_EN BIT(28) +#define BIT_WL_DSS_READY BIT(21) +#define BIT_WL_DSS_WSORT_GO BIT(20) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FW_DRV_HANDSHAKE (Offset 0x10DC) */ +#define BIT_SHIFT_FW_DRV_HANDSHAKE 0 +#define BIT_MASK_FW_DRV_HANDSHAKE 0xffffffffL +#define BIT_FW_DRV_HANDSHAKE(x) \ + (((x) & BIT_MASK_FW_DRV_HANDSHAKE) << BIT_SHIFT_FW_DRV_HANDSHAKE) +#define BITS_FW_DRV_HANDSHAKE \ + (BIT_MASK_FW_DRV_HANDSHAKE << BIT_SHIFT_FW_DRV_HANDSHAKE) +#define BIT_CLEAR_FW_DRV_HANDSHAKE(x) ((x) & (~BITS_FW_DRV_HANDSHAKE)) +#define BIT_GET_FW_DRV_HANDSHAKE(x) \ + (((x) >> BIT_SHIFT_FW_DRV_HANDSHAKE) & BIT_MASK_FW_DRV_HANDSHAKE) +#define BIT_SET_FW_DRV_HANDSHAKE(x, v) \ + (BIT_CLEAR_FW_DRV_HANDSHAKE(x) | BIT_FW_DRV_HANDSHAKE(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN BIT(27) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_FW_DBG0 (Offset 0x10E0) */ +#define BIT_SHIFT_FW_DBG0 0 +#define BIT_MASK_FW_DBG0 0xffffffffL +#define BIT_FW_DBG0(x) (((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0) +#define BITS_FW_DBG0 (BIT_MASK_FW_DBG0 << BIT_SHIFT_FW_DBG0) +#define BIT_CLEAR_FW_DBG0(x) ((x) & (~BITS_FW_DBG0)) +#define BIT_GET_FW_DBG0(x) (((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0) +#define BIT_SET_FW_DBG0(x, v) (BIT_CLEAR_FW_DBG0(x) | BIT_FW_DBG0(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FW_DBG1 (Offset 0x10E4) */ +#define BIT_SHIFT_FW_DBG1 0 +#define BIT_MASK_FW_DBG1 0xffffffffL +#define BIT_FW_DBG1(x) (((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1) +#define BITS_FW_DBG1 (BIT_MASK_FW_DBG1 << BIT_SHIFT_FW_DBG1) +#define BIT_CLEAR_FW_DBG1(x) ((x) & (~BITS_FW_DBG1)) +#define BIT_GET_FW_DBG1(x) (((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1) +#define BIT_SET_FW_DBG1(x, v) (BIT_CLEAR_FW_DBG1(x) | BIT_FW_DBG1(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FW_DBG2 (Offset 0x10E8) */ -#define BIT_FS_CLI2_RX_UAPSDMD1_EN BIT(27) +#define BIT_SHIFT_FW_DBG2 0 +#define BIT_MASK_FW_DBG2 0xffffffffL +#define BIT_FW_DBG2(x) (((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2) +#define BITS_FW_DBG2 (BIT_MASK_FW_DBG2 << BIT_SHIFT_FW_DBG2) +#define BIT_CLEAR_FW_DBG2(x) ((x) & (~BITS_FW_DBG2)) +#define BIT_GET_FW_DBG2(x) (((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2) +#define BIT_SET_FW_DBG2(x, v) (BIT_CLEAR_FW_DBG2(x) | BIT_FW_DBG2(v)) -#endif +/* 2 REG_FW_DBG3 (Offset 0x10EC) */ +#define BIT_SHIFT_FW_DBG3 0 +#define BIT_MASK_FW_DBG3 0xffffffffL +#define BIT_FW_DBG3(x) (((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3) +#define BITS_FW_DBG3 (BIT_MASK_FW_DBG3 << BIT_SHIFT_FW_DBG3) +#define BIT_CLEAR_FW_DBG3(x) ((x) & (~BITS_FW_DBG3)) +#define BIT_GET_FW_DBG3(x) (((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3) +#define BIT_SET_FW_DBG3(x, v) (BIT_CLEAR_FW_DBG3(x) | BIT_FW_DBG3(v)) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FW_DBG4 (Offset 0x10F0) */ +#define BIT_SHIFT_FW_DBG4 0 +#define BIT_MASK_FW_DBG4 0xffffffffL +#define BIT_FW_DBG4(x) (((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4) +#define BITS_FW_DBG4 (BIT_MASK_FW_DBG4 << BIT_SHIFT_FW_DBG4) +#define BIT_CLEAR_FW_DBG4(x) ((x) & (~BITS_FW_DBG4)) +#define BIT_GET_FW_DBG4(x) (((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4) +#define BIT_SET_FW_DBG4(x, v) (BIT_CLEAR_FW_DBG4(x) | BIT_FW_DBG4(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FW_DBG5 (Offset 0x10F4) */ -#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN BIT(26) +#define BIT_SHIFT_FW_DBG5 0 +#define BIT_MASK_FW_DBG5 0xffffffffL +#define BIT_FW_DBG5(x) (((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5) +#define BITS_FW_DBG5 (BIT_MASK_FW_DBG5 << BIT_SHIFT_FW_DBG5) +#define BIT_CLEAR_FW_DBG5(x) ((x) & (~BITS_FW_DBG5)) +#define BIT_GET_FW_DBG5(x) (((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5) +#define BIT_SET_FW_DBG5(x, v) (BIT_CLEAR_FW_DBG5(x) | BIT_FW_DBG5(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FW_DBG6 (Offset 0x10F8) */ +#define BIT_SHIFT_FW_DBG6 0 +#define BIT_MASK_FW_DBG6 0xffffffffL +#define BIT_FW_DBG6(x) (((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6) +#define BITS_FW_DBG6 (BIT_MASK_FW_DBG6 << BIT_SHIFT_FW_DBG6) +#define BIT_CLEAR_FW_DBG6(x) ((x) & (~BITS_FW_DBG6)) +#define BIT_GET_FW_DBG6(x) (((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6) +#define BIT_SET_FW_DBG6(x, v) (BIT_CLEAR_FW_DBG6(x) | BIT_FW_DBG6(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FW_DBG7 (Offset 0x10FC) */ -#define BIT_FS_CLI2_RX_UAPSDMD0_EN BIT(26) +#define BIT_SHIFT_FW_DBG7 0 +#define BIT_MASK_FW_DBG7 0xffffffffL +#define BIT_FW_DBG7(x) (((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7) +#define BITS_FW_DBG7 (BIT_MASK_FW_DBG7 << BIT_SHIFT_FW_DBG7) +#define BIT_CLEAR_FW_DBG7(x) ((x) & (~BITS_FW_DBG7)) +#define BIT_GET_FW_DBG7(x) (((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7) +#define BIT_SET_FW_DBG7(x, v) (BIT_CLEAR_FW_DBG7(x) | BIT_FW_DBG7(v)) -#endif +/* 2 REG_CR_EXT (Offset 0x1100) */ +#define BIT_SHIFT_PHY_REQ_DELAY 24 +#define BIT_MASK_PHY_REQ_DELAY 0xf +#define BIT_PHY_REQ_DELAY(x) \ + (((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY) +#define BITS_PHY_REQ_DELAY (BIT_MASK_PHY_REQ_DELAY << BIT_SHIFT_PHY_REQ_DELAY) +#define BIT_CLEAR_PHY_REQ_DELAY(x) ((x) & (~BITS_PHY_REQ_DELAY)) +#define BIT_GET_PHY_REQ_DELAY(x) \ + (((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY) +#define BIT_SET_PHY_REQ_DELAY(x, v) \ + (BIT_CLEAR_PHY_REQ_DELAY(x) | BIT_PHY_REQ_DELAY(v)) + +#define BIT_SPD_DOWN BIT(16) + +#define BIT_SHIFT_NETYPE4 4 +#define BIT_MASK_NETYPE4 0x3 +#define BIT_NETYPE4(x) (((x) & BIT_MASK_NETYPE4) << BIT_SHIFT_NETYPE4) +#define BITS_NETYPE4 (BIT_MASK_NETYPE4 << BIT_SHIFT_NETYPE4) +#define BIT_CLEAR_NETYPE4(x) ((x) & (~BITS_NETYPE4)) +#define BIT_GET_NETYPE4(x) (((x) >> BIT_SHIFT_NETYPE4) & BIT_MASK_NETYPE4) +#define BIT_SET_NETYPE4(x, v) (BIT_CLEAR_NETYPE4(x) | BIT_NETYPE4(v)) + +#define BIT_SHIFT_NETYPE3 2 +#define BIT_MASK_NETYPE3 0x3 +#define BIT_NETYPE3(x) (((x) & BIT_MASK_NETYPE3) << BIT_SHIFT_NETYPE3) +#define BITS_NETYPE3 (BIT_MASK_NETYPE3 << BIT_SHIFT_NETYPE3) +#define BIT_CLEAR_NETYPE3(x) ((x) & (~BITS_NETYPE3)) +#define BIT_GET_NETYPE3(x) (((x) >> BIT_SHIFT_NETYPE3) & BIT_MASK_NETYPE3) +#define BIT_SET_NETYPE3(x, v) (BIT_CLEAR_NETYPE3(x) | BIT_NETYPE3(v)) + +#define BIT_SHIFT_NETYPE2 0 +#define BIT_MASK_NETYPE2 0x3 +#define BIT_NETYPE2(x) (((x) & BIT_MASK_NETYPE2) << BIT_SHIFT_NETYPE2) +#define BITS_NETYPE2 (BIT_MASK_NETYPE2 << BIT_SHIFT_NETYPE2) +#define BIT_CLEAR_NETYPE2(x) ((x) & (~BITS_NETYPE2)) +#define BIT_GET_NETYPE2(x) (((x) >> BIT_SHIFT_NETYPE2) & BIT_MASK_NETYPE2) +#define BIT_SET_NETYPE2(x, v) (BIT_CLEAR_NETYPE2(x) | BIT_NETYPE2(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_TC9_CTRL (Offset 0x1104) */ + +#define BIT_TC9INT_EN BIT(26) +#define BIT_TC9MODE BIT(25) +#define BIT_TC9EN BIT(24) + +#define BIT_SHIFT_TC9DATA 0 +#define BIT_MASK_TC9DATA 0xffffff +#define BIT_TC9DATA(x) (((x) & BIT_MASK_TC9DATA) << BIT_SHIFT_TC9DATA) +#define BITS_TC9DATA (BIT_MASK_TC9DATA << BIT_SHIFT_TC9DATA) +#define BIT_CLEAR_TC9DATA(x) ((x) & (~BITS_TC9DATA)) +#define BIT_GET_TC9DATA(x) (((x) >> BIT_SHIFT_TC9DATA) & BIT_MASK_TC9DATA) +#define BIT_SET_TC9DATA(x, v) (BIT_CLEAR_TC9DATA(x) | BIT_TC9DATA(v)) + +/* 2 REG_TC10_CTRL (Offset 0x1108) */ + +#define BIT_TC10INT_EN BIT(26) +#define BIT_TC10MODE BIT(25) +#define BIT_TC10EN BIT(24) + +#define BIT_SHIFT_TC10DATA 0 +#define BIT_MASK_TC10DATA 0xffffff +#define BIT_TC10DATA(x) (((x) & BIT_MASK_TC10DATA) << BIT_SHIFT_TC10DATA) +#define BITS_TC10DATA (BIT_MASK_TC10DATA << BIT_SHIFT_TC10DATA) +#define BIT_CLEAR_TC10DATA(x) ((x) & (~BITS_TC10DATA)) +#define BIT_GET_TC10DATA(x) (((x) >> BIT_SHIFT_TC10DATA) & BIT_MASK_TC10DATA) +#define BIT_SET_TC10DATA(x, v) (BIT_CLEAR_TC10DATA(x) | BIT_TC10DATA(v)) + +/* 2 REG_TC11_CTRL (Offset 0x110C) */ + +#define BIT_TC11INT_EN BIT(26) +#define BIT_TC11MODE BIT(25) +#define BIT_TC11EN BIT(24) + +#define BIT_SHIFT_TC11DATA 0 +#define BIT_MASK_TC11DATA 0xffffff +#define BIT_TC11DATA(x) (((x) & BIT_MASK_TC11DATA) << BIT_SHIFT_TC11DATA) +#define BITS_TC11DATA (BIT_MASK_TC11DATA << BIT_SHIFT_TC11DATA) +#define BIT_CLEAR_TC11DATA(x) ((x) & (~BITS_TC11DATA)) +#define BIT_GET_TC11DATA(x) (((x) >> BIT_SHIFT_TC11DATA) & BIT_MASK_TC11DATA) +#define BIT_SET_TC11DATA(x, v) (BIT_CLEAR_TC11DATA(x) | BIT_TC11DATA(v)) + +/* 2 REG_TC12_CTRL (Offset 0x1110) */ + +#define BIT_TC12INT_EN BIT(26) +#define BIT_TC12MODE BIT(25) +#define BIT_TC12EN BIT(24) +#define BIT_P2P_PWROFF_NOA2_ERLY_INT BIT(22) +#define BIT_P2P_PWROFF_NOA1_ERLY_INT BIT(21) +#define BIT_P2P_PWROFF_NOA0_ERLY_INT BIT(20) + +#define BIT_SHIFT_TC12DATA 0 +#define BIT_MASK_TC12DATA 0xffffff +#define BIT_TC12DATA(x) (((x) & BIT_MASK_TC12DATA) << BIT_SHIFT_TC12DATA) +#define BITS_TC12DATA (BIT_MASK_TC12DATA << BIT_SHIFT_TC12DATA) +#define BIT_CLEAR_TC12DATA(x) ((x) & (~BITS_TC12DATA)) +#define BIT_GET_TC12DATA(x) (((x) >> BIT_SHIFT_TC12DATA) & BIT_MASK_TC12DATA) +#define BIT_SET_TC12DATA(x, v) (BIT_CLEAR_TC12DATA(x) | BIT_TC12DATA(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FWFF (Offset 0x1114) */ +#define BIT_SHIFT_PKTNUM_TH 24 +#define BIT_MASK_PKTNUM_TH 0xff +#define BIT_PKTNUM_TH(x) (((x) & BIT_MASK_PKTNUM_TH) << BIT_SHIFT_PKTNUM_TH) +#define BITS_PKTNUM_TH (BIT_MASK_PKTNUM_TH << BIT_SHIFT_PKTNUM_TH) +#define BIT_CLEAR_PKTNUM_TH(x) ((x) & (~BITS_PKTNUM_TH)) +#define BIT_GET_PKTNUM_TH(x) (((x) >> BIT_SHIFT_PKTNUM_TH) & BIT_MASK_PKTNUM_TH) +#define BIT_SET_PKTNUM_TH(x, v) (BIT_CLEAR_PKTNUM_TH(x) | BIT_PKTNUM_TH(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT3_TRIPKT_OK_INT_EN BIT(25) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWFF (Offset 0x1114) */ +#define BIT_SHIFT_PKTNUM_TH_V1 24 +#define BIT_MASK_PKTNUM_TH_V1 0xff +#define BIT_PKTNUM_TH_V1(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V1) << BIT_SHIFT_PKTNUM_TH_V1) +#define BITS_PKTNUM_TH_V1 (BIT_MASK_PKTNUM_TH_V1 << BIT_SHIFT_PKTNUM_TH_V1) +#define BIT_CLEAR_PKTNUM_TH_V1(x) ((x) & (~BITS_PKTNUM_TH_V1)) +#define BIT_GET_PKTNUM_TH_V1(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V1) & BIT_MASK_PKTNUM_TH_V1) +#define BIT_SET_PKTNUM_TH_V1(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V1(x) | BIT_PKTNUM_TH_V1(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FWFF (Offset 0x1114) */ -#define BIT_FS_CLI2_TRIGGER_PKT_EN BIT(25) +#define BIT_SHIFT_TIMER_TH 16 +#define BIT_MASK_TIMER_TH 0xff +#define BIT_TIMER_TH(x) (((x) & BIT_MASK_TIMER_TH) << BIT_SHIFT_TIMER_TH) +#define BITS_TIMER_TH (BIT_MASK_TIMER_TH << BIT_SHIFT_TIMER_TH) +#define BIT_CLEAR_TIMER_TH(x) ((x) & (~BITS_TIMER_TH)) +#define BIT_GET_TIMER_TH(x) (((x) >> BIT_SHIFT_TIMER_TH) & BIT_MASK_TIMER_TH) +#define BIT_SET_TIMER_TH(x, v) (BIT_CLEAR_TIMER_TH(x) | BIT_TIMER_TH(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FWFF (Offset 0x1114) */ +#define BIT_EN_RXDMA_ALIGN_V1 BIT(1) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT3_RX_EOSP_OK_INT_EN BIT(24) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWFF (Offset 0x1114) */ +#define BIT_SHIFT_RXPKT1ENADDR 0 +#define BIT_MASK_RXPKT1ENADDR 0xffff +#define BIT_RXPKT1ENADDR(x) \ + (((x) & BIT_MASK_RXPKT1ENADDR) << BIT_SHIFT_RXPKT1ENADDR) +#define BITS_RXPKT1ENADDR (BIT_MASK_RXPKT1ENADDR << BIT_SHIFT_RXPKT1ENADDR) +#define BIT_CLEAR_RXPKT1ENADDR(x) ((x) & (~BITS_RXPKT1ENADDR)) +#define BIT_GET_RXPKT1ENADDR(x) \ + (((x) >> BIT_SHIFT_RXPKT1ENADDR) & BIT_MASK_RXPKT1ENADDR) +#define BIT_SET_RXPKT1ENADDR(x, v) \ + (BIT_CLEAR_RXPKT1ENADDR(x) | BIT_RXPKT1ENADDR(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FWFF (Offset 0x1114) */ -#define BIT_FS_CLI2_EOSP_INT_EN BIT(24) +#define BIT_EN_TXDMA_ALIGN_V1 BIT(0) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FE2IMR (Offset 0x1120) */ +#define BIT__FE4ISR__IND_MSK BIT(29) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN BIT(23) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE2IMR (Offset 0x1120) */ +#define BIT_FS_TXSC_DESC_DONE_INT_EN BIT(28) +#define BIT_FS_TXSC_BKDONE_INT_EN BIT(27) +#define BIT_FS_TXSC_BEDONE_INT_EN BIT(26) +#define BIT_FS_TXSC_VIDONE_INT_EN BIT(25) +#define BIT_FS_TXSC_VODONE_INT_EN BIT(24) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FE2IMR (Offset 0x1120) */ -#define BIT_FS_CLI1_RX_UAPSDMD1_EN BIT(23) +#define BIT_FS_ATIM_MB7_INT_EN BIT(23) +#define BIT_FS_ATIM_MB6_INT_EN BIT(22) +#define BIT_FS_ATIM_MB5_INT_EN BIT(21) +#define BIT_FS_ATIM_MB4_INT_EN BIT(20) +#define BIT_FS_ATIM_MB3_INT_EN BIT(19) +#define BIT_FS_ATIM_MB2_INT_EN BIT(18) +#define BIT_FS_ATIM_MB1_INT_EN BIT(17) +#define BIT_FS_ATIM_MB0_INT_EN BIT(16) +#define BIT_FS_TBTT4INT_EN BIT(11) +#define BIT_FS_TBTT3INT_EN BIT(10) +#define BIT_FS_TBTT2INT_EN BIT(9) +#define BIT_FS_TBTT1INT_EN BIT(8) +#define BIT_FS_TBTT0_MB7INT_EN BIT(7) +#define BIT_FS_TBTT0_MB6INT_EN BIT(6) +#define BIT_FS_TBTT0_MB5INT_EN BIT(5) +#define BIT_FS_TBTT0_MB4INT_EN BIT(4) +#define BIT_FS_TBTT0_MB3INT_EN BIT(3) +#define BIT_FS_TBTT0_MB2INT_EN BIT(2) +#define BIT_FS_TBTT0_MB1INT_EN BIT(1) +#define BIT_FS_TBTT0_INT_EN BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE2ISR (Offset 0x1124) */ +#define BIT__FE4ISR__IND_INT BIT(29) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FE2ISR (Offset 0x1124) */ -#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN BIT(22) +#define BIT_FS_TXSC_DESC_DONE_INT BIT(28) +#define BIT_FS_TXSC_BKDONE_INT BIT(27) +#define BIT_FS_TXSC_BEDONE_INT BIT(26) +#define BIT_FS_TXSC_VIDONE_INT BIT(25) +#define BIT_FS_TXSC_VODONE_INT BIT(24) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE2ISR (Offset 0x1124) */ +#define BIT_FS_ATIM_MB7_INT BIT(23) +#define BIT_FS_ATIM_MB6_INT BIT(22) +#define BIT_FS_ATIM_MB5_INT BIT(21) +#define BIT_FS_ATIM_MB4_INT BIT(20) +#define BIT_FS_ATIM_MB3_INT BIT(19) +#define BIT_FS_ATIM_MB2_INT BIT(18) +#define BIT_FS_ATIM_MB1_INT BIT(17) +#define BIT_FS_ATIM_MB0_INT BIT(16) +#define BIT_FS_TBTT4INT BIT(11) +#define BIT_FS_TBTT3INT BIT(10) +#define BIT_FS_TBTT2INT BIT(9) +#define BIT_FS_TBTT1INT BIT(8) +#define BIT_FS_TBTT0_MB7INT BIT(7) +#define BIT_FS_TBTT0_MB6INT BIT(6) +#define BIT_FS_TBTT0_MB5INT BIT(5) +#define BIT_FS_TBTT0_MB4INT BIT(4) +#define BIT_FS_TBTT0_MB3INT BIT(3) +#define BIT_FS_TBTT0_MB2INT BIT(2) +#define BIT_FS_TBTT0_MB1INT BIT(1) +#define BIT_FS_TBTT0_INT BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FE3IMR (Offset 0x1128) */ -#define BIT_FS_CLI1_RX_UAPSDMD0_EN BIT(22) +#define BIT_FS_BCNELY4_AGGR_INT_EN BIT(31) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FE3IMR (Offset 0x1128) */ -#define BIT_PORT2_TRIPKT_OK_INT_EN BIT(21) +#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN BIT(31) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE3IMR (Offset 0x1128) */ +#define BIT_FS_BCNELY3_AGGR_INT_EN BIT(30) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_CLI1_TRIGGER_PKT_EN BIT(21) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE3IMR (Offset 0x1128) */ +#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN BIT(30) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FE3IMR (Offset 0x1128) */ -#define BIT_PORT2_RX_EOSP_OK_INT_EN BIT(20) +#define BIT_FS_BCNELY2_AGGR_INT_EN BIT(29) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE3IMR (Offset 0x1128) */ +#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN BIT(29) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_CLI1_EOSP_INT_EN BIT(20) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FE3IMR (Offset 0x1128) */ +#define BIT_FS_BCNELY1_AGGR_INT_EN BIT(28) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FE3IMR (Offset 0x1128) */ -#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN BIT(19) +#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN BIT(28) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE3IMR (Offset 0x1128) */ +#define BIT_FS_BCNDMA4_INT_EN BIT(27) +#define BIT_FS_BCNDMA3_INT_EN BIT(26) +#define BIT_FS_BCNDMA2_INT_EN BIT(25) +#define BIT_FS_BCNDMA1_INT_EN BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT_EN BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT_EN BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT_EN BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT_EN BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT_EN BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT_EN BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT_EN BIT(17) +#define BIT_FS_BCNDMA0_INT_EN BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT__EN BIT(15) +#define BIT_FS_BCNERLY4_INT_EN BIT(11) +#define BIT_FS_BCNERLY3_INT_EN BIT(10) +#define BIT_FS_BCNERLY2_INT_EN BIT(9) +#define BIT_FS_BCNERLY1_INT_EN BIT(8) +#define BIT_FS_BCNERLY0_MB7INT_EN BIT(7) +#define BIT_FS_BCNERLY0_MB6INT_EN BIT(6) +#define BIT_FS_BCNERLY0_MB5INT_EN BIT(5) +#define BIT_FS_BCNERLY0_MB4INT_EN BIT(4) +#define BIT_FS_BCNERLY0_MB3INT_EN BIT(3) +#define BIT_FS_BCNERLY0_MB2INT_EN BIT(2) +#define BIT_FS_BCNERLY0_MB1INT_EN BIT(1) +#define BIT_FS_BCNERLY0_INT_EN BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FE3ISR (Offset 0x112C) */ -#define BIT_FS_CLI0_RX_UAPSDMD1_EN BIT(19) +#define BIT_FS_BCNELY4_AGGR_INT BIT(31) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FE3ISR (Offset 0x112C) */ +#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT BIT(31) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN BIT(18) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FE3ISR (Offset 0x112C) */ +#define BIT_FS_BCNELY3_AGGR_INT BIT(30) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_BCNELY2_AGGR_INT BIT(29) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT BIT(29) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_BCNELY1_AGGR_INT BIT(28) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT BIT(28) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_BCNDMA4_INT BIT(27) +#define BIT_FS_BCNDMA3_INT BIT(26) +#define BIT_FS_BCNDMA2_INT BIT(25) +#define BIT_FS_BCNDMA1_INT BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT BIT(17) +#define BIT_FS_BCNDMA0_INT BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT BIT(15) +#define BIT_FS_BCNERLY4_INT BIT(11) +#define BIT_FS_BCNERLY3_INT BIT(10) +#define BIT_FS_BCNERLY2_INT BIT(9) +#define BIT_FS_BCNERLY1_INT BIT(8) +#define BIT_FS_BCNERLY0_MB7INT BIT(7) +#define BIT_FS_BCNERLY0_MB6INT BIT(6) +#define BIT_FS_BCNERLY0_MB5INT BIT(5) +#define BIT_FS_BCNERLY0_MB4INT BIT(4) +#define BIT_FS_BCNERLY0_MB3INT BIT(3) +#define BIT_FS_BCNERLY0_MB2INT BIT(2) +#define BIT_FS_BCNERLY0_MB1INT BIT(1) +#define BIT_FS_BCNERLY0_INT BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT4_PKTIN_INT_EN BIT(19) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI3_TXPKTIN_INT_EN BIT(19) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT3_PKTIN_INT_EN BIT(18) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI2_TXPKTIN_INT_EN BIT(18) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT2_PKTIN_INT_EN BIT(17) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI1_TXPKTIN_INT_EN BIT(17) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT1_PKTIN_INT_EN BIT(16) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI0_TXPKTIN_INT_EN BIT(16) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT4_RXUCMD0_OK_INT_EN BIT(15) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI3_RX_UMD0_INT_EN BIT(15) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT4_RXUCMD1_OK_INT_EN BIT(14) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI3_RX_UMD1_INT_EN BIT(14) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT4_RXBCMD0_OK_INT_EN BIT(13) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI3_RX_BMD0_INT_EN BIT(13) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT4_RXBCMD1_OK_INT_EN BIT(12) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI3_RX_BMD1_INT_EN BIT(12) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT3_RXUCMD0_OK_INT_EN BIT(11) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI2_RX_UMD0_INT_EN BIT(11) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT3_RXUCMD1_OK_INT_EN BIT(10) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI2_RX_UMD1_INT_EN BIT(10) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT3_RXBCMD0_OK_INT_EN BIT(9) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI2_RX_BMD0_INT_EN BIT(9) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT3_RXBCMD1_OK_INT_EN BIT(8) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI2_RX_BMD1_INT_EN BIT(8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT2_RXUCMD0_OK_INT_EN BIT(7) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI1_RX_UMD0_INT_EN BIT(7) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT2_RXUCMD1_OK_INT_EN BIT(6) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI1_RX_UMD1_INT_EN BIT(6) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT2_RXBCMD0_OK_INT_EN BIT(5) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI1_RX_BMD0_INT_EN BIT(5) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT2_RXBCMD1_OK_INT_EN BIT(4) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI1_RX_BMD1_INT_EN BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT1_RXUCMD0_OK_INT_EN BIT(3) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI0_RX_UMD0_INT_EN BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT1_RXUCMD1_OK_INT_EN BIT(2) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_DMEM1_WPTR_UPDATE_INT_EN BIT(2) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI0_RX_UMD1_INT_EN BIT(2) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT1_RXBCMD0_OK_INT_EN BIT(1) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI0_RX_BMD0_INT_EN BIT(1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT1_RXBCMD1_OK_INT_EN BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI0_RX_BMD1_INT_EN BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT4_PKTIN_INT BIT(19) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI3_TXPKTIN_INT BIT(19) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT3_PKTIN_INT BIT(18) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI2_TXPKTIN_INT BIT(18) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT2_PKTIN_INT BIT(17) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI1_TXPKTIN_INT BIT(17) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT1_PKTIN_INT BIT(16) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI0_TXPKTIN_INT BIT(16) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT4_RXUCMD0_OK_INT BIT(15) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI3_RX_UMD0_INT BIT(15) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT4_RXUCMD1_OK_INT BIT(14) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI3_RX_UMD1_INT BIT(14) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT4_RXBCMD0_OK_INT BIT(13) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI3_RX_BMD0_INT BIT(13) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT4_RXBCMD1_OK_INT BIT(12) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI3_RX_BMD1_INT BIT(12) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT3_RXUCMD0_OK_INT BIT(11) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI2_RX_UMD0_INT BIT(11) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT3_RXUCMD1_OK_INT BIT(10) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI2_RX_UMD1_INT BIT(10) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT3_RXBCMD0_OK_INT BIT(9) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI2_RX_BMD0_INT BIT(9) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT3_RXBCMD1_OK_INT BIT(8) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI2_RX_BMD1_INT BIT(8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT2_RXUCMD0_OK_INT BIT(7) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI1_RX_UMD0_INT BIT(7) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT2_RXUCMD1_OK_INT BIT(6) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI1_RX_UMD1_INT BIT(6) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT2_RXBCMD0_OK_INT BIT(5) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI1_RX_BMD0_INT BIT(5) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT2_RXBCMD1_OK_INT BIT(4) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI1_RX_BMD1_INT BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT1_RXUCMD0_OK_INT BIT(3) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI0_RX_UMD0_INT BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT1_RXUCMD1_OK_INT BIT(2) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_DMEM1_WPTR_UPDATE_INT BIT(2) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI0_RX_UMD1_INT BIT(2) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT1_RXBCMD0_OK_INT BIT(1) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI0_RX_BMD0_INT BIT(1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT1_RXBCMD1_OK_INT BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI0_RX_BMD1_INT BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1IMR (Offset 0x1138) */ + +#define BIT__FT2ISR__IND_MSK BIT(30) +#define BIT_FTM_PTT_INT_EN BIT(29) +#define BIT_RXFTMREQ_INT_EN BIT(28) +#define BIT_RXFTM_INT_EN BIT(27) +#define BIT_TXFTM_INT_EN BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1IMR (Offset 0x1138) */ + +#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT_EN BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1IMR (Offset 0x1138) */ + +#define BIT_FS_MACID_PWRCHANGE5_INT_EN BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT_EN BIT(22) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1IMR (Offset 0x1138) */ + +#define BIT_FS_MACID_SEARCH_FAIL_INT_EN BIT(22) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1IMR (Offset 0x1138) */ + +#define BIT_FS_MACID_PWRCHANGE3_INT_EN BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT_EN BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT_EN BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT_EN BIT(18) +#define BIT_FS_CTWEND2_INT_EN BIT(17) +#define BIT_FS_CTWEND1_INT_EN BIT(16) +#define BIT_FS_CTWEND0_INT_EN BIT(15) +#define BIT_FS_TX_NULL1_INT_EN BIT(14) +#define BIT_FS_TX_NULL0_INT_EN BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_EN BIT(12) +#define BIT_FS_P2P_RFON2_INT_EN BIT(11) +#define BIT_FS_P2P_RFOFF2_INT_EN BIT(10) +#define BIT_FS_P2P_RFON1_INT_EN BIT(9) +#define BIT_FS_P2P_RFOFF1_INT_EN BIT(8) +#define BIT_FS_P2P_RFON0_INT_EN BIT(7) +#define BIT_FS_P2P_RFOFF0_INT_EN BIT(6) +#define BIT_FS_RX_UAPSDMD1_EN BIT(5) +#define BIT_FS_RX_UAPSDMD0_EN BIT(4) +#define BIT_FS_TRIGGER_PKT_EN BIT(3) +#define BIT_FS_EOSP_INT_EN BIT(2) +#define BIT_FS_RPWM2_INT_EN BIT(1) +#define BIT_FS_RPWM_INT_EN BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT__FT2ISR__IND_INT BIT(30) +#define BIT_FTM_PTT_INT BIT(29) +#define BIT_RXFTMREQ_INT BIT(28) +#define BIT_RXFTM_INT BIT(27) +#define BIT_TXFTM_INT BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_H2C_CMD_OK_INT BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_MACID_PWRCHANGE5_INT BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT BIT(22) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_MACID_SEARCH_FAIL_INT BIT(22) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_MACID_PWRCHANGE3_INT BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT BIT(18) +#define BIT_FS_CTWEND2_INT BIT(17) +#define BIT_FS_CTWEND1_INT BIT(16) +#define BIT_FS_CTWEND0_INT BIT(15) +#define BIT_FS_TX_NULL1_INT BIT(14) +#define BIT_FS_TX_NULL0_INT BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_INT BIT(12) +#define BIT_FS_P2P_RFON2_INT BIT(11) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNOK_PORT4_INT_EN BIT(11) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_P2P_RFOFF2_INT BIT(10) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNOK_PORT3_INT_EN BIT(10) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_P2P_RFON1_INT BIT(9) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNOK_PORT2_INT_EN BIT(9) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_P2P_RFOFF1_INT BIT(8) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNOK_PORT1_INT_EN BIT(8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_P2P_RFON0_INT BIT(7) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNERR_PORT4_INT_EN BIT(7) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_P2P_RFOFF0_INT BIT(6) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNERR_PORT3_INT_EN BIT(6) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_RX_UAPSDMD1_INT BIT(5) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNERR_PORT2_INT_EN BIT(5) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_RX_UAPSDMD0_INT BIT(4) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNERR_PORT1_INT_EN BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TRIGGER_PKT_INT BIT(3) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_ATIM_PORT4_INT_EN BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_EOSP_INT BIT(2) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_ATIM_PORT3_INT_EN BIT(2) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_RPWM2_INT BIT(1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_ATIM_PORT2_INT_EN BIT(1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_RPWM_INT BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_ATIM_PORT1_INT_EN BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SPWR0 (Offset 0x1140) */ + +#define BIT_SHIFT_MID_31TO0 0 +#define BIT_MASK_MID_31TO0 0xffffffffL +#define BIT_MID_31TO0(x) (((x) & BIT_MASK_MID_31TO0) << BIT_SHIFT_MID_31TO0) +#define BITS_MID_31TO0 (BIT_MASK_MID_31TO0 << BIT_SHIFT_MID_31TO0) +#define BIT_CLEAR_MID_31TO0(x) ((x) & (~BITS_MID_31TO0)) +#define BIT_GET_MID_31TO0(x) (((x) >> BIT_SHIFT_MID_31TO0) & BIT_MASK_MID_31TO0) +#define BIT_SET_MID_31TO0(x, v) (BIT_CLEAR_MID_31TO0(x) | BIT_MID_31TO0(v)) + +/* 2 REG_SPWR1 (Offset 0x1144) */ + +#define BIT_SHIFT_MID_63TO32 0 +#define BIT_MASK_MID_63TO32 0xffffffffL +#define BIT_MID_63TO32(x) (((x) & BIT_MASK_MID_63TO32) << BIT_SHIFT_MID_63TO32) +#define BITS_MID_63TO32 (BIT_MASK_MID_63TO32 << BIT_SHIFT_MID_63TO32) +#define BIT_CLEAR_MID_63TO32(x) ((x) & (~BITS_MID_63TO32)) +#define BIT_GET_MID_63TO32(x) \ + (((x) >> BIT_SHIFT_MID_63TO32) & BIT_MASK_MID_63TO32) +#define BIT_SET_MID_63TO32(x, v) (BIT_CLEAR_MID_63TO32(x) | BIT_MID_63TO32(v)) + +/* 2 REG_SPWR2 (Offset 0x1148) */ + +#define BIT_SHIFT_MID_95O64 0 +#define BIT_MASK_MID_95O64 0xffffffffL +#define BIT_MID_95O64(x) (((x) & BIT_MASK_MID_95O64) << BIT_SHIFT_MID_95O64) +#define BITS_MID_95O64 (BIT_MASK_MID_95O64 << BIT_SHIFT_MID_95O64) +#define BIT_CLEAR_MID_95O64(x) ((x) & (~BITS_MID_95O64)) +#define BIT_GET_MID_95O64(x) (((x) >> BIT_SHIFT_MID_95O64) & BIT_MASK_MID_95O64) +#define BIT_SET_MID_95O64(x, v) (BIT_CLEAR_MID_95O64(x) | BIT_MID_95O64(v)) + +/* 2 REG_SPWR3 (Offset 0x114C) */ + +#define BIT_SHIFT_MID_127TO96 0 +#define BIT_MASK_MID_127TO96 0xffffffffL +#define BIT_MID_127TO96(x) \ + (((x) & BIT_MASK_MID_127TO96) << BIT_SHIFT_MID_127TO96) +#define BITS_MID_127TO96 (BIT_MASK_MID_127TO96 << BIT_SHIFT_MID_127TO96) +#define BIT_CLEAR_MID_127TO96(x) ((x) & (~BITS_MID_127TO96)) +#define BIT_GET_MID_127TO96(x) \ + (((x) >> BIT_SHIFT_MID_127TO96) & BIT_MASK_MID_127TO96) +#define BIT_SET_MID_127TO96(x, v) \ + (BIT_CLEAR_MID_127TO96(x) | BIT_MID_127TO96(v)) + +/* 2 REG_POWSEQ (Offset 0x1150) */ + +#define BIT_SHIFT_SEQNUM_MID 16 +#define BIT_MASK_SEQNUM_MID 0xffff +#define BIT_SEQNUM_MID(x) (((x) & BIT_MASK_SEQNUM_MID) << BIT_SHIFT_SEQNUM_MID) +#define BITS_SEQNUM_MID (BIT_MASK_SEQNUM_MID << BIT_SHIFT_SEQNUM_MID) +#define BIT_CLEAR_SEQNUM_MID(x) ((x) & (~BITS_SEQNUM_MID)) +#define BIT_GET_SEQNUM_MID(x) \ + (((x) >> BIT_SHIFT_SEQNUM_MID) & BIT_MASK_SEQNUM_MID) +#define BIT_SET_SEQNUM_MID(x, v) (BIT_CLEAR_SEQNUM_MID(x) | BIT_SEQNUM_MID(v)) + +#define BIT_SHIFT_REF_MID 0 +#define BIT_MASK_REF_MID 0x7f +#define BIT_REF_MID(x) (((x) & BIT_MASK_REF_MID) << BIT_SHIFT_REF_MID) +#define BITS_REF_MID (BIT_MASK_REF_MID << BIT_SHIFT_REF_MID) +#define BIT_CLEAR_REF_MID(x) ((x) & (~BITS_REF_MID)) +#define BIT_GET_REF_MID(x) (((x) >> BIT_SHIFT_REF_MID) & BIT_MASK_REF_MID) +#define BIT_SET_REF_MID(x, v) (BIT_CLEAR_REF_MID(x) | BIT_REF_MID(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_RX_BCN_TBTT_ITVL0 (Offset 0x1160) */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2 24 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT2(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT2 \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2 \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT2(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1 16 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT1(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT1 \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1 \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT1(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0 8 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT0(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT0 \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0 \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT0(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0 0xff +#define BIT_RX_BCN_TBTT_ITVL_PORT0(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0) +#define BITS_RX_BCN_TBTT_ITVL_PORT0 \ + (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0)) +#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_PORT0) +#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0(x) | BIT_RX_BCN_TBTT_ITVL_PORT0(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL1 (Offset 0x1164) */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT3(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT3 \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3 \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT3(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) + +/* 2 REG_FWIMR1 (Offset 0x1168) */ + +#define BIT_FS_ATIM_MB15_INT_EN BIT(31) +#define BIT_FS_ATIM_MB14_INT_EN BIT(30) +#define BIT_FS_ATIM_MB13_INT_EN BIT(29) +#define BIT_FS_ATIM_MB12_INT_EN BIT(28) +#define BIT_FS_ATIM_MB11_INT_EN BIT(27) +#define BIT_FS_ATIM_MB10_INT_EN BIT(26) +#define BIT_FS_ATIM_MB9_INT_EN BIT(25) +#define BIT_FS_ATIM_MB8_INT_EN BIT(24) +#define BIT_FS_TXBCNERR_MB15_INT_EN BIT(23) +#define BIT_FS_TXBCNERR_MB14_INT_EN BIT(22) +#define BIT_FS_TXBCNERR_MB13_INT_EN BIT(21) +#define BIT_FS_TXBCNERR_MB12_INT_EN BIT(20) +#define BIT_FS_TXBCNERR_MB11_INT_EN BIT(19) +#define BIT_FS_TXBCNERR_MB10_INT_EN BIT(18) +#define BIT_FS_TXBCNERR_MB9_INT_EN BIT(17) +#define BIT_FS_TXBCNERR_MB8_INT_EN BIT(16) +#define BIT_FS_TXBCNOK_MB15_INT_EN BIT(15) +#define BIT_FS_TXBCNOK_MB14_INT_EN BIT(14) +#define BIT_FS_TXBCNOK_MB13_INT_EN BIT(13) +#define BIT_FS_TXBCNOK_MB12_INT_EN BIT(12) +#define BIT_FS_TXBCNOK_MB11_INT_EN BIT(11) +#define BIT_FS_TXBCNOK_MB10_INT_EN BIT(10) +#define BIT_FS_TXBCNOK_MB9_INT_EN BIT(9) +#define BIT_FS_TXBCNOK_MB8_INT_EN BIT(8) +#define BIT_FS_BCNERLY0_MB15INT_EN BIT(7) +#define BIT_FS_BCNERLY0_MB14INT_EN BIT(6) +#define BIT_FS_BCNERLY0_MB13INT_EN BIT(5) +#define BIT_FS_BCNERLY0_MB12INT_EN BIT(4) +#define BIT_FS_BCNERLY0_MB11INT_EN BIT(3) +#define BIT_FS_BCNERLY0_MB10INT_EN BIT(2) +#define BIT_FS_BCNERLY0_MB9INT_EN BIT(1) +#define BIT_FS_BCNERLY0_MB8INT_EN BIT(0) + +/* 2 REG_FWISR1 (Offset 0x116C) */ + +#define BIT_FS_ATIM_MB15_INT BIT(31) +#define BIT_FS_ATIM_MB14_INT BIT(30) +#define BIT_FS_ATIM_MB13_INT BIT(29) +#define BIT_FS_ATIM_MB12_INT BIT(28) +#define BIT_FS_ATIM_MB11_INT BIT(27) +#define BIT_FS_ATIM_MB10_INT BIT(26) +#define BIT_FS_ATIM_MB9_INT BIT(25) +#define BIT_FS_ATIM_MB8_INT BIT(24) +#define BIT_FS_TXBCNERR_MB15_INT BIT(23) +#define BIT_FS_TXBCNERR_MB14_INT BIT(22) +#define BIT_FS_TXBCNERR_MB13_INT BIT(21) +#define BIT_FS_TXBCNERR_MB12_INT BIT(20) +#define BIT_FS_TXBCNERR_MB11_INT BIT(19) +#define BIT_FS_TXBCNERR_MB10_INT BIT(18) +#define BIT_FS_TXBCNERR_MB9_INT BIT(17) +#define BIT_FS_TXBCNERR_MB8_INT BIT(16) +#define BIT_FS_TXBCNOK_MB15_INT BIT(15) +#define BIT_FS_TXBCNOK_MB14_INT BIT(14) +#define BIT_FS_TXBCNOK_MB13_INT BIT(13) +#define BIT_FS_TXBCNOK_MB12_INT BIT(12) +#define BIT_FS_TXBCNOK_MB11_INT BIT(11) +#define BIT_FS_TXBCNOK_MB10_INT BIT(10) +#define BIT_FS_TXBCNOK_MB9_INT BIT(9) +#define BIT_FS_TXBCNOK_MB8_INT BIT(8) +#define BIT_FS_BCNERLY0_MB15INT BIT(7) +#define BIT_FS_BCNERLY0_MB14INT BIT(6) +#define BIT_FS_BCNERLY0_MB13INT BIT(5) +#define BIT_FS_BCNERLY0_MB12INT BIT(4) +#define BIT_FS_BCNERLY0_MB11INT BIT(3) +#define BIT_FS_BCNERLY0_MB10INT BIT(2) +#define BIT_FS_BCNERLY0_MB9INT BIT(1) +#define BIT_FS_BCNERLY0_MB8INT BIT(0) + +/* 2 REG_FWIMR2 (Offset 0x1170) */ + +#define BIT_FS_BCNDMA0_MB15_INT_EN BIT(15) +#define BIT_FS_BCNDMA0_MB14_INT_EN BIT(14) +#define BIT_FS_BCNDMA0_MB13_INT_EN BIT(13) +#define BIT_FS_BCNDMA0_MB12_INT_EN BIT(12) +#define BIT_FS_BCNDMA0_MB11_INT_EN BIT(11) +#define BIT_FS_BCNDMA0_MB10_INT_EN BIT(10) +#define BIT_FS_BCNDMA0_MB9_INT_EN BIT(9) +#define BIT_FS_BCNDMA0_MB8_INT_EN BIT(8) +#define BIT_FS_TBTT0_MB15INT_EN BIT(7) +#define BIT_FS_TBTT0_MB14INT_EN BIT(6) +#define BIT_FS_TBTT0_MB13INT_EN BIT(5) +#define BIT_FS_TBTT0_MB12INT_EN BIT(4) +#define BIT_FS_TBTT0_MB11INT_EN BIT(3) +#define BIT_FS_TBTT0_MB10INT_EN BIT(2) +#define BIT_FS_TBTT0_MB9INT_EN BIT(1) +#define BIT_FS_TBTT0_MB8INT_EN BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_IO_WRAP_ERR_FLAG (Offset 0x1170) */ + +#define BIT_IO_WRAP_ERR BIT(0) + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) + +/* 2 REG_FWISR2 (Offset 0x1174) */ + +#define BIT_FS_BCNDMA0_MB15_INT BIT(15) +#define BIT_FS_BCNDMA0_MB14_INT BIT(14) +#define BIT_FS_BCNDMA0_MB13_INT BIT(13) +#define BIT_FS_BCNDMA0_MB12_INT BIT(12) +#define BIT_FS_BCNDMA0_MB11_INT BIT(11) +#define BIT_FS_BCNDMA0_MB10_INT BIT(10) +#define BIT_FS_BCNDMA0_MB9_INT BIT(9) +#define BIT_FS_BCNDMA0_MB8_INT BIT(8) +#define BIT_FS_TBTT0_MB15INT BIT(7) +#define BIT_FS_TBTT0_MB14INT BIT(6) +#define BIT_FS_TBTT0_MB13INT BIT(5) +#define BIT_FS_TBTT0_MB12INT BIT(4) +#define BIT_FS_TBTT0_MB11INT BIT(3) +#define BIT_FS_TBTT0_MB10INT BIT(2) +#define BIT_FS_TBTT0_MB9INT BIT(1) +#define BIT_FS_TBTT0_MB8INT BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FWISR3 (Offset 0x117C) */ + +#define BIT_FS_TXBCNOK_PORT4_INT BIT(11) +#define BIT_FS_TXBCNOK_PORT3_INT BIT(10) +#define BIT_FS_TXBCNOK_PORT2_INT BIT(9) +#define BIT_FS_TXBCNOK_PORT1_INT BIT(8) +#define BIT_FS_TXBCNERR_PORT4_INT BIT(7) +#define BIT_FS_TXBCNERR_PORT3_INT BIT(6) +#define BIT_FS_TXBCNERR_PORT2_INT BIT(5) +#define BIT_FS_TXBCNERR_PORT1_INT BIT(4) +#define BIT_FS_ATIM_PORT4_INT BIT(3) +#define BIT_FS_ATIM_PORT3_INT BIT(2) +#define BIT_FS_ATIM_PORT2_INT BIT(1) +#define BIT_FS_ATIM_PORT1_INT BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SPEED_SENSOR (Offset 0x1180) */ + +#define BIT_DSS_1_RST_N BIT(31) +#define BIT_DSS_1_SPEED_EN BIT(30) +#define BIT_DSS_1_WIRE_SEL BIT(29) +#define BIT_DSS_ENCLK BIT(28) + +#define BIT_SHIFT_DSS_1_RO_SEL 24 +#define BIT_MASK_DSS_1_RO_SEL 0x7 +#define BIT_DSS_1_RO_SEL(x) \ + (((x) & BIT_MASK_DSS_1_RO_SEL) << BIT_SHIFT_DSS_1_RO_SEL) +#define BITS_DSS_1_RO_SEL (BIT_MASK_DSS_1_RO_SEL << BIT_SHIFT_DSS_1_RO_SEL) +#define BIT_CLEAR_DSS_1_RO_SEL(x) ((x) & (~BITS_DSS_1_RO_SEL)) +#define BIT_GET_DSS_1_RO_SEL(x) \ + (((x) >> BIT_SHIFT_DSS_1_RO_SEL) & BIT_MASK_DSS_1_RO_SEL) +#define BIT_SET_DSS_1_RO_SEL(x, v) \ + (BIT_CLEAR_DSS_1_RO_SEL(x) | BIT_DSS_1_RO_SEL(v)) + +#define BIT_SHIFT_DSS_1_DATA_IN 0 +#define BIT_MASK_DSS_1_DATA_IN 0xfffff +#define BIT_DSS_1_DATA_IN(x) \ + (((x) & BIT_MASK_DSS_1_DATA_IN) << BIT_SHIFT_DSS_1_DATA_IN) +#define BITS_DSS_1_DATA_IN (BIT_MASK_DSS_1_DATA_IN << BIT_SHIFT_DSS_1_DATA_IN) +#define BIT_CLEAR_DSS_1_DATA_IN(x) ((x) & (~BITS_DSS_1_DATA_IN)) +#define BIT_GET_DSS_1_DATA_IN(x) \ + (((x) >> BIT_SHIFT_DSS_1_DATA_IN) & BIT_MASK_DSS_1_DATA_IN) +#define BIT_SET_DSS_1_DATA_IN(x, v) \ + (BIT_CLEAR_DSS_1_DATA_IN(x) | BIT_DSS_1_DATA_IN(v)) + +/* 2 REG_SPEED_SENSOR1 (Offset 0x1184) */ + +#define BIT_DSS_1_READY BIT(31) +#define BIT_DSS_1_WSORT_GO BIT(30) + +#define BIT_SHIFT_DSS_1_COUNT_OUT 0 +#define BIT_MASK_DSS_1_COUNT_OUT 0xfffff +#define BIT_DSS_1_COUNT_OUT(x) \ + (((x) & BIT_MASK_DSS_1_COUNT_OUT) << BIT_SHIFT_DSS_1_COUNT_OUT) +#define BITS_DSS_1_COUNT_OUT \ + (BIT_MASK_DSS_1_COUNT_OUT << BIT_SHIFT_DSS_1_COUNT_OUT) +#define BIT_CLEAR_DSS_1_COUNT_OUT(x) ((x) & (~BITS_DSS_1_COUNT_OUT)) +#define BIT_GET_DSS_1_COUNT_OUT(x) \ + (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT) & BIT_MASK_DSS_1_COUNT_OUT) +#define BIT_SET_DSS_1_COUNT_OUT(x, v) \ + (BIT_CLEAR_DSS_1_COUNT_OUT(x) | BIT_DSS_1_COUNT_OUT(v)) + +/* 2 REG_SPEED_SENSOR2 (Offset 0x1188) */ + +#define BIT_DSS_2_RST_N BIT(31) +#define BIT_DSS_2_SPEED_EN BIT(30) +#define BIT_DSS_2_WIRE_SEL BIT(29) + +#define BIT_SHIFT_DSS_2_RO_SEL 24 +#define BIT_MASK_DSS_2_RO_SEL 0x7 +#define BIT_DSS_2_RO_SEL(x) \ + (((x) & BIT_MASK_DSS_2_RO_SEL) << BIT_SHIFT_DSS_2_RO_SEL) +#define BITS_DSS_2_RO_SEL (BIT_MASK_DSS_2_RO_SEL << BIT_SHIFT_DSS_2_RO_SEL) +#define BIT_CLEAR_DSS_2_RO_SEL(x) ((x) & (~BITS_DSS_2_RO_SEL)) +#define BIT_GET_DSS_2_RO_SEL(x) \ + (((x) >> BIT_SHIFT_DSS_2_RO_SEL) & BIT_MASK_DSS_2_RO_SEL) +#define BIT_SET_DSS_2_RO_SEL(x, v) \ + (BIT_CLEAR_DSS_2_RO_SEL(x) | BIT_DSS_2_RO_SEL(v)) + +#define BIT_SHIFT_DSS_2_DATA_IN 0 +#define BIT_MASK_DSS_2_DATA_IN 0xfffff +#define BIT_DSS_2_DATA_IN(x) \ + (((x) & BIT_MASK_DSS_2_DATA_IN) << BIT_SHIFT_DSS_2_DATA_IN) +#define BITS_DSS_2_DATA_IN (BIT_MASK_DSS_2_DATA_IN << BIT_SHIFT_DSS_2_DATA_IN) +#define BIT_CLEAR_DSS_2_DATA_IN(x) ((x) & (~BITS_DSS_2_DATA_IN)) +#define BIT_GET_DSS_2_DATA_IN(x) \ + (((x) >> BIT_SHIFT_DSS_2_DATA_IN) & BIT_MASK_DSS_2_DATA_IN) +#define BIT_SET_DSS_2_DATA_IN(x, v) \ + (BIT_CLEAR_DSS_2_DATA_IN(x) | BIT_DSS_2_DATA_IN(v)) + +/* 2 REG_SPEED_SENSOR3 (Offset 0x118C) */ + +#define BIT_DSS_2_READY BIT(31) +#define BIT_DSS_2_WSORT_GO BIT(30) + +#define BIT_SHIFT_DSS_2_COUNT_OUT 0 +#define BIT_MASK_DSS_2_COUNT_OUT 0xfffff +#define BIT_DSS_2_COUNT_OUT(x) \ + (((x) & BIT_MASK_DSS_2_COUNT_OUT) << BIT_SHIFT_DSS_2_COUNT_OUT) +#define BITS_DSS_2_COUNT_OUT \ + (BIT_MASK_DSS_2_COUNT_OUT << BIT_SHIFT_DSS_2_COUNT_OUT) +#define BIT_CLEAR_DSS_2_COUNT_OUT(x) ((x) & (~BITS_DSS_2_COUNT_OUT)) +#define BIT_GET_DSS_2_COUNT_OUT(x) \ + (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT) & BIT_MASK_DSS_2_COUNT_OUT) +#define BIT_SET_DSS_2_COUNT_OUT(x, v) \ + (BIT_CLEAR_DSS_2_COUNT_OUT(x) | BIT_DSS_2_COUNT_OUT(v)) + +/* 2 REG_SPEED_SENSOR4 (Offset 0x1190) */ + +#define BIT_DSS_3_RST_N BIT(31) +#define BIT_DSS_3_SPEED_EN BIT(30) +#define BIT_DSS_3_WIRE_SEL BIT(29) + +#define BIT_SHIFT_DSS_3_RO_SEL 24 +#define BIT_MASK_DSS_3_RO_SEL 0x7 +#define BIT_DSS_3_RO_SEL(x) \ + (((x) & BIT_MASK_DSS_3_RO_SEL) << BIT_SHIFT_DSS_3_RO_SEL) +#define BITS_DSS_3_RO_SEL (BIT_MASK_DSS_3_RO_SEL << BIT_SHIFT_DSS_3_RO_SEL) +#define BIT_CLEAR_DSS_3_RO_SEL(x) ((x) & (~BITS_DSS_3_RO_SEL)) +#define BIT_GET_DSS_3_RO_SEL(x) \ + (((x) >> BIT_SHIFT_DSS_3_RO_SEL) & BIT_MASK_DSS_3_RO_SEL) +#define BIT_SET_DSS_3_RO_SEL(x, v) \ + (BIT_CLEAR_DSS_3_RO_SEL(x) | BIT_DSS_3_RO_SEL(v)) + +#define BIT_SHIFT_DSS_3_DATA_IN 0 +#define BIT_MASK_DSS_3_DATA_IN 0xfffff +#define BIT_DSS_3_DATA_IN(x) \ + (((x) & BIT_MASK_DSS_3_DATA_IN) << BIT_SHIFT_DSS_3_DATA_IN) +#define BITS_DSS_3_DATA_IN (BIT_MASK_DSS_3_DATA_IN << BIT_SHIFT_DSS_3_DATA_IN) +#define BIT_CLEAR_DSS_3_DATA_IN(x) ((x) & (~BITS_DSS_3_DATA_IN)) +#define BIT_GET_DSS_3_DATA_IN(x) \ + (((x) >> BIT_SHIFT_DSS_3_DATA_IN) & BIT_MASK_DSS_3_DATA_IN) +#define BIT_SET_DSS_3_DATA_IN(x, v) \ + (BIT_CLEAR_DSS_3_DATA_IN(x) | BIT_DSS_3_DATA_IN(v)) + +/* 2 REG_SPEED_SENSOR5 (Offset 0x1194) */ + +#define BIT_DSS_3_READY BIT(31) +#define BIT_DSS_3_WSORT_GO BIT(30) + +#define BIT_SHIFT_DSS_3_COUNT_OUT 0 +#define BIT_MASK_DSS_3_COUNT_OUT 0xfffff +#define BIT_DSS_3_COUNT_OUT(x) \ + (((x) & BIT_MASK_DSS_3_COUNT_OUT) << BIT_SHIFT_DSS_3_COUNT_OUT) +#define BITS_DSS_3_COUNT_OUT \ + (BIT_MASK_DSS_3_COUNT_OUT << BIT_SHIFT_DSS_3_COUNT_OUT) +#define BIT_CLEAR_DSS_3_COUNT_OUT(x) ((x) & (~BITS_DSS_3_COUNT_OUT)) +#define BIT_GET_DSS_3_COUNT_OUT(x) \ + (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT) & BIT_MASK_DSS_3_COUNT_OUT) +#define BIT_SET_DSS_3_COUNT_OUT(x, v) \ + (BIT_CLEAR_DSS_3_COUNT_OUT(x) | BIT_DSS_3_COUNT_OUT(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_RXPKTBUF_1_MAX_ADDR (Offset 0x1198) */ + +#define BIT_SHIFT_RXPKTBUF_SIZE 30 +#define BIT_MASK_RXPKTBUF_SIZE 0x3 +#define BIT_RXPKTBUF_SIZE(x) \ + (((x) & BIT_MASK_RXPKTBUF_SIZE) << BIT_SHIFT_RXPKTBUF_SIZE) +#define BITS_RXPKTBUF_SIZE (BIT_MASK_RXPKTBUF_SIZE << BIT_SHIFT_RXPKTBUF_SIZE) +#define BIT_CLEAR_RXPKTBUF_SIZE(x) ((x) & (~BITS_RXPKTBUF_SIZE)) +#define BIT_GET_RXPKTBUF_SIZE(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_SIZE) & BIT_MASK_RXPKTBUF_SIZE) +#define BIT_SET_RXPKTBUF_SIZE(x, v) \ + (BIT_CLEAR_RXPKTBUF_SIZE(x) | BIT_RXPKTBUF_SIZE(v)) + +#define BIT_RXPKTBUF_DBG_SEL BIT(29) + +#define BIT_SHIFT_RXPKTBUF_1_MAX_ADDR 0 +#define BIT_MASK_RXPKTBUF_1_MAX_ADDR 0x3ffff +#define BIT_RXPKTBUF_1_MAX_ADDR(x) \ + (((x) & BIT_MASK_RXPKTBUF_1_MAX_ADDR) << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR) +#define BITS_RXPKTBUF_1_MAX_ADDR \ + (BIT_MASK_RXPKTBUF_1_MAX_ADDR << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR) +#define BIT_CLEAR_RXPKTBUF_1_MAX_ADDR(x) ((x) & (~BITS_RXPKTBUF_1_MAX_ADDR)) +#define BIT_GET_RXPKTBUF_1_MAX_ADDR(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_1_MAX_ADDR) & BIT_MASK_RXPKTBUF_1_MAX_ADDR) +#define BIT_SET_RXPKTBUF_1_MAX_ADDR(x, v) \ + (BIT_CLEAR_RXPKTBUF_1_MAX_ADDR(x) | BIT_RXPKTBUF_1_MAX_ADDR(v)) + +/* 2 REG_RXFWBUF_1_MAX_ADDR (Offset 0x119C) */ + +#define BIT_SHIFT_RXFWBUF_1_MAX_ADDR 0 +#define BIT_MASK_RXFWBUF_1_MAX_ADDR 0xffff +#define BIT_RXFWBUF_1_MAX_ADDR(x) \ + (((x) & BIT_MASK_RXFWBUF_1_MAX_ADDR) << BIT_SHIFT_RXFWBUF_1_MAX_ADDR) +#define BITS_RXFWBUF_1_MAX_ADDR \ + (BIT_MASK_RXFWBUF_1_MAX_ADDR << BIT_SHIFT_RXFWBUF_1_MAX_ADDR) +#define BIT_CLEAR_RXFWBUF_1_MAX_ADDR(x) ((x) & (~BITS_RXFWBUF_1_MAX_ADDR)) +#define BIT_GET_RXFWBUF_1_MAX_ADDR(x) \ + (((x) >> BIT_SHIFT_RXFWBUF_1_MAX_ADDR) & BIT_MASK_RXFWBUF_1_MAX_ADDR) +#define BIT_SET_RXFWBUF_1_MAX_ADDR(x, v) \ + (BIT_CLEAR_RXFWBUF_1_MAX_ADDR(x) | BIT_RXFWBUF_1_MAX_ADDR(v)) + +/* 2 REG_RXPKTBUF_1_READ (Offset 0x11A4) */ + +#define BIT_SHIFT_RXPKTBUF_1_READ 0 +#define BIT_MASK_RXPKTBUF_1_READ 0x3ffff +#define BIT_RXPKTBUF_1_READ(x) \ + (((x) & BIT_MASK_RXPKTBUF_1_READ) << BIT_SHIFT_RXPKTBUF_1_READ) +#define BITS_RXPKTBUF_1_READ \ + (BIT_MASK_RXPKTBUF_1_READ << BIT_SHIFT_RXPKTBUF_1_READ) +#define BIT_CLEAR_RXPKTBUF_1_READ(x) ((x) & (~BITS_RXPKTBUF_1_READ)) +#define BIT_GET_RXPKTBUF_1_READ(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_1_READ) & BIT_MASK_RXPKTBUF_1_READ) +#define BIT_SET_RXPKTBUF_1_READ(x, v) \ + (BIT_CLEAR_RXPKTBUF_1_READ(x) | BIT_RXPKTBUF_1_READ(v)) + +/* 2 REG_RXPKTBUF_1_WRITE (Offset 0x11A8) */ + +#define BIT_SHIFT_R_OQT_DBG_SEL 16 +#define BIT_MASK_R_OQT_DBG_SEL 0xff +#define BIT_R_OQT_DBG_SEL(x) \ + (((x) & BIT_MASK_R_OQT_DBG_SEL) << BIT_SHIFT_R_OQT_DBG_SEL) +#define BITS_R_OQT_DBG_SEL (BIT_MASK_R_OQT_DBG_SEL << BIT_SHIFT_R_OQT_DBG_SEL) +#define BIT_CLEAR_R_OQT_DBG_SEL(x) ((x) & (~BITS_R_OQT_DBG_SEL)) +#define BIT_GET_R_OQT_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_R_OQT_DBG_SEL) & BIT_MASK_R_OQT_DBG_SEL) +#define BIT_SET_R_OQT_DBG_SEL(x, v) \ + (BIT_CLEAR_R_OQT_DBG_SEL(x) | BIT_R_OQT_DBG_SEL(v)) + +#define BIT_SHIFT_R_TXPKTBF_DBG_SEL 8 +#define BIT_MASK_R_TXPKTBF_DBG_SEL 0x7 +#define BIT_R_TXPKTBF_DBG_SEL(x) \ + (((x) & BIT_MASK_R_TXPKTBF_DBG_SEL) << BIT_SHIFT_R_TXPKTBF_DBG_SEL) +#define BITS_R_TXPKTBF_DBG_SEL \ + (BIT_MASK_R_TXPKTBF_DBG_SEL << BIT_SHIFT_R_TXPKTBF_DBG_SEL) +#define BIT_CLEAR_R_TXPKTBF_DBG_SEL(x) ((x) & (~BITS_R_TXPKTBF_DBG_SEL)) +#define BIT_GET_R_TXPKTBF_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_R_TXPKTBF_DBG_SEL) & BIT_MASK_R_TXPKTBF_DBG_SEL) +#define BIT_SET_R_TXPKTBF_DBG_SEL(x, v) \ + (BIT_CLEAR_R_TXPKTBF_DBG_SEL(x) | BIT_R_TXPKTBF_DBG_SEL(v)) + +#define BIT_SHIFT_R_RXPKT_DBG_SEL 6 +#define BIT_MASK_R_RXPKT_DBG_SEL 0x3 +#define BIT_R_RXPKT_DBG_SEL(x) \ + (((x) & BIT_MASK_R_RXPKT_DBG_SEL) << BIT_SHIFT_R_RXPKT_DBG_SEL) +#define BITS_R_RXPKT_DBG_SEL \ + (BIT_MASK_R_RXPKT_DBG_SEL << BIT_SHIFT_R_RXPKT_DBG_SEL) +#define BIT_CLEAR_R_RXPKT_DBG_SEL(x) ((x) & (~BITS_R_RXPKT_DBG_SEL)) +#define BIT_GET_R_RXPKT_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_R_RXPKT_DBG_SEL) & BIT_MASK_R_RXPKT_DBG_SEL) +#define BIT_SET_R_RXPKT_DBG_SEL(x, v) \ + (BIT_CLEAR_R_RXPKT_DBG_SEL(x) | BIT_R_RXPKT_DBG_SEL(v)) + +#define BIT_SHIFT_RXPKTBUF_1_WRITE 0 +#define BIT_MASK_RXPKTBUF_1_WRITE 0x3ffff +#define BIT_RXPKTBUF_1_WRITE(x) \ + (((x) & BIT_MASK_RXPKTBUF_1_WRITE) << BIT_SHIFT_RXPKTBUF_1_WRITE) +#define BITS_RXPKTBUF_1_WRITE \ + (BIT_MASK_RXPKTBUF_1_WRITE << BIT_SHIFT_RXPKTBUF_1_WRITE) +#define BIT_CLEAR_RXPKTBUF_1_WRITE(x) ((x) & (~BITS_RXPKTBUF_1_WRITE)) +#define BIT_GET_RXPKTBUF_1_WRITE(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_1_WRITE) & BIT_MASK_RXPKTBUF_1_WRITE) +#define BIT_SET_RXPKTBUF_1_WRITE(x, v) \ + (BIT_CLEAR_RXPKTBUF_1_WRITE(x) | BIT_RXPKTBUF_1_WRITE(v)) + +#define BIT_SHIFT_R_RXPKTBF_DBG_SEL 0 +#define BIT_MASK_R_RXPKTBF_DBG_SEL 0x3 +#define BIT_R_RXPKTBF_DBG_SEL(x) \ + (((x) & BIT_MASK_R_RXPKTBF_DBG_SEL) << BIT_SHIFT_R_RXPKTBF_DBG_SEL) +#define BITS_R_RXPKTBF_DBG_SEL \ + (BIT_MASK_R_RXPKTBF_DBG_SEL << BIT_SHIFT_R_RXPKTBF_DBG_SEL) +#define BIT_CLEAR_R_RXPKTBF_DBG_SEL(x) ((x) & (~BITS_R_RXPKTBF_DBG_SEL)) +#define BIT_GET_R_RXPKTBF_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_R_RXPKTBF_DBG_SEL) & BIT_MASK_R_RXPKTBF_DBG_SEL) +#define BIT_SET_R_RXPKTBF_DBG_SEL(x, v) \ + (BIT_CLEAR_R_RXPKTBF_DBG_SEL(x) | BIT_R_RXPKTBF_DBG_SEL(v)) + +/* 2 REG_RFE_CTRL_PAD_E2 (Offset 0x11B0) */ + +#define BIT_RFE_CTRL_ANTSW_E2 BIT(16) +#define BIT_RFE_CTRL_PIN15_E2 BIT(15) +#define BIT_RFE_CTRL_PIN14_E2 BIT(14) +#define BIT_RFE_CTRL_PIN13_E2 BIT(13) +#define BIT_RFE_CTRL_PIN12_E2 BIT(12) +#define BIT_RFE_CTRL_PIN11_E2 BIT(11) +#define BIT_RFE_CTRL_PIN10_E2 BIT(10) +#define BIT_RFE_CTRL_PIN9_E2 BIT(9) +#define BIT_RFE_CTRL_PIN8_E2 BIT(8) +#define BIT_RFE_CTRL_PIN7_E2 BIT(7) +#define BIT_RFE_CTRL_PIN6_E2 BIT(6) +#define BIT_RFE_CTRL_PIN5_E2 BIT(5) +#define BIT_RFE_CTRL_PIN4_E2 BIT(4) +#define BIT_RFE_CTRL_PIN3_E2 BIT(3) +#define BIT_RFE_CTRL_PIN2_E2 BIT(2) +#define BIT_RFE_CTRL_PIN1_E2 BIT(1) +#define BIT_RFE_CTRL_PIN0_E2 BIT(0) + +/* 2 REG_RFE_CTRL_PAD_SR (Offset 0x11B4) */ + +#define BIT_RFE_CTRL_ANTSW_SR BIT(16) +#define BIT_RFE_CTRL_PIN15_SR BIT(15) +#define BIT_RFE_CTRL_PIN14_SR BIT(14) +#define BIT_RFE_CTRL_PIN13_SR BIT(13) +#define BIT_RFE_CTRL_PIN12_SR BIT(12) +#define BIT_RFE_CTRL_PIN11_SR BIT(11) +#define BIT_RFE_CTRL_PIN10_SR BIT(10) +#define BIT_RFE_CTRL_PIN9_SR BIT(9) +#define BIT_RFE_CTRL_PIN8_SR BIT(8) +#define BIT_RFE_CTRL_PIN7_SR BIT(7) +#define BIT_RFE_CTRL_PIN6_SR BIT(6) +#define BIT_RFE_CTRL_PIN5_SR BIT(5) +#define BIT_RFE_CTRL_PIN4_SR BIT(4) +#define BIT_RFE_CTRL_PIN3_SR BIT(3) +#define BIT_RFE_CTRL_PIN2_SR BIT(2) +#define BIT_RFE_CTRL_PIN1_SR BIT(1) +#define BIT_RFE_CTRL_PIN0_SR BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_EXT_QUEUE_REG (Offset 0x11C0) */ + +#define BIT_SHIFT_PCIE_PRIORITY_SEL 0 +#define BIT_MASK_PCIE_PRIORITY_SEL 0x3 +#define BIT_PCIE_PRIORITY_SEL(x) \ + (((x) & BIT_MASK_PCIE_PRIORITY_SEL) << BIT_SHIFT_PCIE_PRIORITY_SEL) +#define BITS_PCIE_PRIORITY_SEL \ + (BIT_MASK_PCIE_PRIORITY_SEL << BIT_SHIFT_PCIE_PRIORITY_SEL) +#define BIT_CLEAR_PCIE_PRIORITY_SEL(x) ((x) & (~BITS_PCIE_PRIORITY_SEL)) +#define BIT_GET_PCIE_PRIORITY_SEL(x) \ + (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL) & BIT_MASK_PCIE_PRIORITY_SEL) +#define BIT_SET_PCIE_PRIORITY_SEL(x, v) \ + (BIT_CLEAR_PCIE_PRIORITY_SEL(x) | BIT_PCIE_PRIORITY_SEL(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_H2C_PRIORITY_SEL (Offset 0x11C0) */ + +#define BIT_SHIFT_H2C_PRIORITY_SEL 0 +#define BIT_MASK_H2C_PRIORITY_SEL 0x3 +#define BIT_H2C_PRIORITY_SEL(x) \ + (((x) & BIT_MASK_H2C_PRIORITY_SEL) << BIT_SHIFT_H2C_PRIORITY_SEL) +#define BITS_H2C_PRIORITY_SEL \ + (BIT_MASK_H2C_PRIORITY_SEL << BIT_SHIFT_H2C_PRIORITY_SEL) +#define BIT_CLEAR_H2C_PRIORITY_SEL(x) ((x) & (~BITS_H2C_PRIORITY_SEL)) +#define BIT_GET_H2C_PRIORITY_SEL(x) \ + (((x) >> BIT_SHIFT_H2C_PRIORITY_SEL) & BIT_MASK_H2C_PRIORITY_SEL) +#define BIT_SET_H2C_PRIORITY_SEL(x, v) \ + (BIT_CLEAR_H2C_PRIORITY_SEL(x) | BIT_H2C_PRIORITY_SEL(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ + +#define BIT_EN_USB_CNT BIT(5) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ + +#define BIT_USB_COUNT_EN BIT(5) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ + +#define BIT_EN_PCIE_CNT BIT(4) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ + +#define BIT_PCIE_COUNT_EN BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ + +#define BIT_RQPN_CNT BIT(3) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ + +#define BIT_RQPN_COUNT_EN BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ + +#define BIT_RDE_CNT BIT(2) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ + +#define BIT_RDE_COUNT_EN BIT(2) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ + +#define BIT_TDE_CNT BIT(1) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ + +#define BIT_TDE_COUNT_EN BIT(1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ + +#define BIT_DIS_CNT BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ + +#define BIT_DISABLE_COUNTER BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_TH (Offset 0x11C8) */ + +#define BIT_CNT_ALL_MACID BIT(31) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_THRESHOLD (Offset 0x11C8) */ + +#define BIT_SEL_ALL_MACID BIT(31) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_TH (Offset 0x11C8) */ + +#define BIT_SHIFT_CNT_MACID 24 +#define BIT_MASK_CNT_MACID 0x7f +#define BIT_CNT_MACID(x) (((x) & BIT_MASK_CNT_MACID) << BIT_SHIFT_CNT_MACID) +#define BITS_CNT_MACID (BIT_MASK_CNT_MACID << BIT_SHIFT_CNT_MACID) +#define BIT_CLEAR_CNT_MACID(x) ((x) & (~BITS_CNT_MACID)) +#define BIT_GET_CNT_MACID(x) (((x) >> BIT_SHIFT_CNT_MACID) & BIT_MASK_CNT_MACID) +#define BIT_SET_CNT_MACID(x, v) (BIT_CLEAR_CNT_MACID(x) | BIT_CNT_MACID(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_THRESHOLD (Offset 0x11C8) */ + +#define BIT_SHIFT_COUNTER_MACID 24 +#define BIT_MASK_COUNTER_MACID 0x7f +#define BIT_COUNTER_MACID(x) \ + (((x) & BIT_MASK_COUNTER_MACID) << BIT_SHIFT_COUNTER_MACID) +#define BITS_COUNTER_MACID (BIT_MASK_COUNTER_MACID << BIT_SHIFT_COUNTER_MACID) +#define BIT_CLEAR_COUNTER_MACID(x) ((x) & (~BITS_COUNTER_MACID)) +#define BIT_GET_COUNTER_MACID(x) \ + (((x) >> BIT_SHIFT_COUNTER_MACID) & BIT_MASK_COUNTER_MACID) +#define BIT_SET_COUNTER_MACID(x, v) \ + (BIT_CLEAR_COUNTER_MACID(x) | BIT_COUNTER_MACID(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_SET (Offset 0x11CC) */ + +#define BIT_RTS_RST BIT(24) +#define BIT_PTCL_RST BIT(23) +#define BIT_SCH_RST BIT(22) +#define BIT_EDCA_RST BIT(21) +#define BIT_RQPN_RST BIT(20) +#define BIT_USB_RST BIT(19) +#define BIT_PCIE_RST BIT(18) +#define BIT_RXDMA_RST BIT(17) +#define BIT_TXDMA_RST BIT(16) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_SET (Offset 0x11CC) */ + +#define BIT_SHIFT_REQUEST_RESET 16 +#define BIT_MASK_REQUEST_RESET 0xffff +#define BIT_REQUEST_RESET(x) \ + (((x) & BIT_MASK_REQUEST_RESET) << BIT_SHIFT_REQUEST_RESET) +#define BITS_REQUEST_RESET (BIT_MASK_REQUEST_RESET << BIT_SHIFT_REQUEST_RESET) +#define BIT_CLEAR_REQUEST_RESET(x) ((x) & (~BITS_REQUEST_RESET)) +#define BIT_GET_REQUEST_RESET(x) \ + (((x) >> BIT_SHIFT_REQUEST_RESET) & BIT_MASK_REQUEST_RESET) +#define BIT_SET_REQUEST_RESET(x, v) \ + (BIT_CLEAR_REQUEST_RESET(x) | BIT_REQUEST_RESET(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_SET (Offset 0x11CC) */ + +#define BIT_EN_RTS_START BIT(8) +#define BIT_EN_PTCL_START BIT(7) +#define BIT_EN_SCH_START BIT(6) +#define BIT_EN_EDCA_START BIT(5) +#define BIT_EN_RQPN_START BIT(4) +#define BIT_EN_USB_START BIT(3) +#define BIT_EN_PCIE_START BIT(2) +#define BIT_EN_RXDMA_START BIT(1) +#define BIT_EN_TXDMA_START BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_SET (Offset 0x11CC) */ + +#define BIT_SHIFT_REQUEST_START 0 +#define BIT_MASK_REQUEST_START 0xffff +#define BIT_REQUEST_START(x) \ + (((x) & BIT_MASK_REQUEST_START) << BIT_SHIFT_REQUEST_START) +#define BITS_REQUEST_START (BIT_MASK_REQUEST_START << BIT_SHIFT_REQUEST_START) +#define BIT_CLEAR_REQUEST_START(x) ((x) & (~BITS_REQUEST_START)) +#define BIT_GET_REQUEST_START(x) \ + (((x) >> BIT_SHIFT_REQUEST_START) & BIT_MASK_REQUEST_START) +#define BIT_SET_REQUEST_START(x, v) \ + (BIT_CLEAR_REQUEST_START(x) | BIT_REQUEST_START(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_OVERFLOW (Offset 0x11D0) */ + +#define BIT_RTS_OVF BIT(8) +#define BIT_PTCL_OVF BIT(7) +#define BIT_SCH_OVF BIT(6) +#define BIT_EDCA_OVF BIT(5) +#define BIT_RQPN_OVF BIT(4) +#define BIT_USB_OVF BIT(3) +#define BIT_PCIE_OVF BIT(2) +#define BIT_RXDMA_OVF BIT(1) +#define BIT_TXDMA_OVF BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_OVERFLOW (Offset 0x11D0) */ + +#define BIT_SHIFT_CNT_OVF_REG 0 +#define BIT_MASK_CNT_OVF_REG 0xffff +#define BIT_CNT_OVF_REG(x) \ + (((x) & BIT_MASK_CNT_OVF_REG) << BIT_SHIFT_CNT_OVF_REG) +#define BITS_CNT_OVF_REG (BIT_MASK_CNT_OVF_REG << BIT_SHIFT_CNT_OVF_REG) +#define BIT_CLEAR_CNT_OVF_REG(x) ((x) & (~BITS_CNT_OVF_REG)) +#define BIT_GET_CNT_OVF_REG(x) \ + (((x) >> BIT_SHIFT_CNT_OVF_REG) & BIT_MASK_CNT_OVF_REG) +#define BIT_SET_CNT_OVF_REG(x, v) \ + (BIT_CLEAR_CNT_OVF_REG(x) | BIT_CNT_OVF_REG(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_TDE_LEN_TH (Offset 0x11D4) */ + +#define BIT_SHIFT_TXDMA_LEN_TH0 16 +#define BIT_MASK_TXDMA_LEN_TH0 0xffff +#define BIT_TXDMA_LEN_TH0(x) \ + (((x) & BIT_MASK_TXDMA_LEN_TH0) << BIT_SHIFT_TXDMA_LEN_TH0) +#define BITS_TXDMA_LEN_TH0 (BIT_MASK_TXDMA_LEN_TH0 << BIT_SHIFT_TXDMA_LEN_TH0) +#define BIT_CLEAR_TXDMA_LEN_TH0(x) ((x) & (~BITS_TXDMA_LEN_TH0)) +#define BIT_GET_TXDMA_LEN_TH0(x) \ + (((x) >> BIT_SHIFT_TXDMA_LEN_TH0) & BIT_MASK_TXDMA_LEN_TH0) +#define BIT_SET_TXDMA_LEN_TH0(x, v) \ + (BIT_CLEAR_TXDMA_LEN_TH0(x) | BIT_TXDMA_LEN_TH0(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_TXDMA_LEN_THRESHOLD (Offset 0x11D4) */ + +#define BIT_SHIFT_TDE_LEN_TH1 16 +#define BIT_MASK_TDE_LEN_TH1 0xffff +#define BIT_TDE_LEN_TH1(x) \ + (((x) & BIT_MASK_TDE_LEN_TH1) << BIT_SHIFT_TDE_LEN_TH1) +#define BITS_TDE_LEN_TH1 (BIT_MASK_TDE_LEN_TH1 << BIT_SHIFT_TDE_LEN_TH1) +#define BIT_CLEAR_TDE_LEN_TH1(x) ((x) & (~BITS_TDE_LEN_TH1)) +#define BIT_GET_TDE_LEN_TH1(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH1) & BIT_MASK_TDE_LEN_TH1) +#define BIT_SET_TDE_LEN_TH1(x, v) \ + (BIT_CLEAR_TDE_LEN_TH1(x) | BIT_TDE_LEN_TH1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_TDE_LEN_TH (Offset 0x11D4) */ + +#define BIT_SHIFT_TXDMA_LEN_TH1 0 +#define BIT_MASK_TXDMA_LEN_TH1 0xffff +#define BIT_TXDMA_LEN_TH1(x) \ + (((x) & BIT_MASK_TXDMA_LEN_TH1) << BIT_SHIFT_TXDMA_LEN_TH1) +#define BITS_TXDMA_LEN_TH1 (BIT_MASK_TXDMA_LEN_TH1 << BIT_SHIFT_TXDMA_LEN_TH1) +#define BIT_CLEAR_TXDMA_LEN_TH1(x) ((x) & (~BITS_TXDMA_LEN_TH1)) +#define BIT_GET_TXDMA_LEN_TH1(x) \ + (((x) >> BIT_SHIFT_TXDMA_LEN_TH1) & BIT_MASK_TXDMA_LEN_TH1) +#define BIT_SET_TXDMA_LEN_TH1(x, v) \ + (BIT_CLEAR_TXDMA_LEN_TH1(x) | BIT_TXDMA_LEN_TH1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_TXDMA_LEN_THRESHOLD (Offset 0x11D4) */ + +#define BIT_SHIFT_TDE_LEN_TH0 0 +#define BIT_MASK_TDE_LEN_TH0 0xffff +#define BIT_TDE_LEN_TH0(x) \ + (((x) & BIT_MASK_TDE_LEN_TH0) << BIT_SHIFT_TDE_LEN_TH0) +#define BITS_TDE_LEN_TH0 (BIT_MASK_TDE_LEN_TH0 << BIT_SHIFT_TDE_LEN_TH0) +#define BIT_CLEAR_TDE_LEN_TH0(x) ((x) & (~BITS_TDE_LEN_TH0)) +#define BIT_GET_TDE_LEN_TH0(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH0) & BIT_MASK_TDE_LEN_TH0) +#define BIT_SET_TDE_LEN_TH0(x, v) \ + (BIT_CLEAR_TDE_LEN_TH0(x) | BIT_TDE_LEN_TH0(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_RDE_LEN_TH (Offset 0x11D8) */ + +#define BIT_SHIFT_RXDMA_LEN_TH0 16 +#define BIT_MASK_RXDMA_LEN_TH0 0xffff +#define BIT_RXDMA_LEN_TH0(x) \ + (((x) & BIT_MASK_RXDMA_LEN_TH0) << BIT_SHIFT_RXDMA_LEN_TH0) +#define BITS_RXDMA_LEN_TH0 (BIT_MASK_RXDMA_LEN_TH0 << BIT_SHIFT_RXDMA_LEN_TH0) +#define BIT_CLEAR_RXDMA_LEN_TH0(x) ((x) & (~BITS_RXDMA_LEN_TH0)) +#define BIT_GET_RXDMA_LEN_TH0(x) \ + (((x) >> BIT_SHIFT_RXDMA_LEN_TH0) & BIT_MASK_RXDMA_LEN_TH0) +#define BIT_SET_RXDMA_LEN_TH0(x, v) \ + (BIT_CLEAR_RXDMA_LEN_TH0(x) | BIT_RXDMA_LEN_TH0(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_RXDMA_LEN_THRESHOLD (Offset 0x11D8) */ + +#define BIT_SHIFT_RDE_LEN_TH1 16 +#define BIT_MASK_RDE_LEN_TH1 0xffff +#define BIT_RDE_LEN_TH1(x) \ + (((x) & BIT_MASK_RDE_LEN_TH1) << BIT_SHIFT_RDE_LEN_TH1) +#define BITS_RDE_LEN_TH1 (BIT_MASK_RDE_LEN_TH1 << BIT_SHIFT_RDE_LEN_TH1) +#define BIT_CLEAR_RDE_LEN_TH1(x) ((x) & (~BITS_RDE_LEN_TH1)) +#define BIT_GET_RDE_LEN_TH1(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH1) & BIT_MASK_RDE_LEN_TH1) +#define BIT_SET_RDE_LEN_TH1(x, v) \ + (BIT_CLEAR_RDE_LEN_TH1(x) | BIT_RDE_LEN_TH1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_RDE_LEN_TH (Offset 0x11D8) */ + +#define BIT_SHIFT_RXDMA_LEN_TH1 0 +#define BIT_MASK_RXDMA_LEN_TH1 0xffff +#define BIT_RXDMA_LEN_TH1(x) \ + (((x) & BIT_MASK_RXDMA_LEN_TH1) << BIT_SHIFT_RXDMA_LEN_TH1) +#define BITS_RXDMA_LEN_TH1 (BIT_MASK_RXDMA_LEN_TH1 << BIT_SHIFT_RXDMA_LEN_TH1) +#define BIT_CLEAR_RXDMA_LEN_TH1(x) ((x) & (~BITS_RXDMA_LEN_TH1)) +#define BIT_GET_RXDMA_LEN_TH1(x) \ + (((x) >> BIT_SHIFT_RXDMA_LEN_TH1) & BIT_MASK_RXDMA_LEN_TH1) +#define BIT_SET_RXDMA_LEN_TH1(x, v) \ + (BIT_CLEAR_RXDMA_LEN_TH1(x) | BIT_RXDMA_LEN_TH1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_RXDMA_LEN_THRESHOLD (Offset 0x11D8) */ + +#define BIT_SHIFT_RDE_LEN_TH0 0 +#define BIT_MASK_RDE_LEN_TH0 0xffff +#define BIT_RDE_LEN_TH0(x) \ + (((x) & BIT_MASK_RDE_LEN_TH0) << BIT_SHIFT_RDE_LEN_TH0) +#define BITS_RDE_LEN_TH0 (BIT_MASK_RDE_LEN_TH0 << BIT_SHIFT_RDE_LEN_TH0) +#define BIT_CLEAR_RDE_LEN_TH0(x) ((x) & (~BITS_RDE_LEN_TH0)) +#define BIT_GET_RDE_LEN_TH0(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH0) & BIT_MASK_RDE_LEN_TH0) +#define BIT_SET_RDE_LEN_TH0(x, v) \ + (BIT_CLEAR_RDE_LEN_TH0(x) | BIT_RDE_LEN_TH0(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_PCIE_EXEC_TIME (Offset 0x11DC) */ + +#define BIT_SHIFT_COUNTER_INTERVAL_SEL 16 +#define BIT_MASK_COUNTER_INTERVAL_SEL 0x3 +#define BIT_COUNTER_INTERVAL_SEL(x) \ + (((x) & BIT_MASK_COUNTER_INTERVAL_SEL) \ + << BIT_SHIFT_COUNTER_INTERVAL_SEL) +#define BITS_COUNTER_INTERVAL_SEL \ + (BIT_MASK_COUNTER_INTERVAL_SEL << BIT_SHIFT_COUNTER_INTERVAL_SEL) +#define BIT_CLEAR_COUNTER_INTERVAL_SEL(x) ((x) & (~BITS_COUNTER_INTERVAL_SEL)) +#define BIT_GET_COUNTER_INTERVAL_SEL(x) \ + (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL) & \ + BIT_MASK_COUNTER_INTERVAL_SEL) +#define BIT_SET_COUNTER_INTERVAL_SEL(x, v) \ + (BIT_CLEAR_COUNTER_INTERVAL_SEL(x) | BIT_COUNTER_INTERVAL_SEL(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_PCIE_EXEC_TIME_THRESHOLD (Offset 0x11DC) */ + +#define BIT_SHIFT_COUNT_INT_SEL 16 +#define BIT_MASK_COUNT_INT_SEL 0x3 +#define BIT_COUNT_INT_SEL(x) \ + (((x) & BIT_MASK_COUNT_INT_SEL) << BIT_SHIFT_COUNT_INT_SEL) +#define BITS_COUNT_INT_SEL (BIT_MASK_COUNT_INT_SEL << BIT_SHIFT_COUNT_INT_SEL) +#define BIT_CLEAR_COUNT_INT_SEL(x) ((x) & (~BITS_COUNT_INT_SEL)) +#define BIT_GET_COUNT_INT_SEL(x) \ + (((x) >> BIT_SHIFT_COUNT_INT_SEL) & BIT_MASK_COUNT_INT_SEL) +#define BIT_SET_COUNT_INT_SEL(x, v) \ + (BIT_CLEAR_COUNT_INT_SEL(x) | BIT_COUNT_INT_SEL(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_PCIE_EXEC_TIME (Offset 0x11DC) */ + +#define BIT_SHIFT_PCIE_TRANS_DATA_TH1 0 +#define BIT_MASK_PCIE_TRANS_DATA_TH1 0xffff +#define BIT_PCIE_TRANS_DATA_TH1(x) \ + (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1) << BIT_SHIFT_PCIE_TRANS_DATA_TH1) +#define BITS_PCIE_TRANS_DATA_TH1 \ + (BIT_MASK_PCIE_TRANS_DATA_TH1 << BIT_SHIFT_PCIE_TRANS_DATA_TH1) +#define BIT_CLEAR_PCIE_TRANS_DATA_TH1(x) ((x) & (~BITS_PCIE_TRANS_DATA_TH1)) +#define BIT_GET_PCIE_TRANS_DATA_TH1(x) \ + (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1) & BIT_MASK_PCIE_TRANS_DATA_TH1) +#define BIT_SET_PCIE_TRANS_DATA_TH1(x, v) \ + (BIT_CLEAR_PCIE_TRANS_DATA_TH1(x) | BIT_PCIE_TRANS_DATA_TH1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_PCIE_EXEC_TIME_THRESHOLD (Offset 0x11DC) */ + +#define BIT_SHIFT_EXEC_TIME_TH 0 +#define BIT_MASK_EXEC_TIME_TH 0xffff +#define BIT_EXEC_TIME_TH(x) \ + (((x) & BIT_MASK_EXEC_TIME_TH) << BIT_SHIFT_EXEC_TIME_TH) +#define BITS_EXEC_TIME_TH (BIT_MASK_EXEC_TIME_TH << BIT_SHIFT_EXEC_TIME_TH) +#define BIT_CLEAR_EXEC_TIME_TH(x) ((x) & (~BITS_EXEC_TIME_TH)) +#define BIT_GET_EXEC_TIME_TH(x) \ + (((x) >> BIT_SHIFT_EXEC_TIME_TH) & BIT_MASK_EXEC_TIME_TH) +#define BIT_SET_EXEC_TIME_TH(x, v) \ + (BIT_CLEAR_EXEC_TIME_TH(x) | BIT_EXEC_TIME_TH(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN BIT(31) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI3_RX_UAPSDMD1_EN BIT(31) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN BIT(30) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI3_RX_UAPSDMD0_EN BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT4_TRIPKT_OK_INT_EN BIT(29) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI3_TRIGGER_PKT_EN BIT(29) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT4_RX_EOSP_OK_INT_EN BIT(28) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI3_EOSP_INT_EN BIT(28) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN BIT(27) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI2_RX_UAPSDMD1_EN BIT(27) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN BIT(26) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI2_RX_UAPSDMD0_EN BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT3_TRIPKT_OK_INT_EN BIT(25) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI2_TRIGGER_PKT_EN BIT(25) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT3_RX_EOSP_OK_INT_EN BIT(24) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI2_EOSP_INT_EN BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN BIT(23) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI1_RX_UAPSDMD1_EN BIT(23) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN BIT(22) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ -#define BIT_FS_CLI0_RX_UAPSDMD0_EN BIT(18) +#define BIT_FS_CLI1_RX_UAPSDMD0_EN BIT(22) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT2_TRIPKT_OK_INT_EN BIT(21) +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ -#define BIT_PORT1_TRIPKT_OK_INT_EN BIT(17) +#define BIT_FS_CLI1_TRIGGER_PKT_EN BIT(21) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2IMR (Offset 0x11E0) */ +#define BIT_PORT2_RX_EOSP_OK_INT_EN BIT(20) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ -#define BIT_FS_CLI0_TRIGGER_PKT_EN BIT(17) +#define BIT_FS_CLI1_EOSP_INT_EN BIT(20) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN BIT(19) + +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ -#define BIT_PORT1_RX_EOSP_OK_INT_EN BIT(16) +#define BIT_FS_CLI0_RX_UAPSDMD1_EN BIT(19) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN BIT(18) + +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ -#define BIT_FS_CLI0_EOSP_INT_EN BIT(16) +#define BIT_FS_CLI0_RX_UAPSDMD0_EN BIT(18) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT1_TRIPKT_OK_INT_EN BIT(17) +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ -#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN BIT(9) +#define BIT_FS_CLI0_TRIGGER_PKT_EN BIT(17) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2IMR (Offset 0x11E0) */ +#define BIT_PORT1_RX_EOSP_OK_INT_EN BIT(16) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ -#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN BIT(9) +#define BIT_FS_CLI0_EOSP_INT_EN BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN BIT(9) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN BIT(9) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN BIT(8) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN BIT(8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT4_TX_NULL1_DONE_INT_EN BIT(7) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI3_TX_NULL1_INT_EN BIT(7) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT4_TX_NULL0_DONE_INT_EN BIT(6) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI3_TX_NULL0_INT_EN BIT(6) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT3_TX_NULL1_DONE_INT_EN BIT(5) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI2_TX_NULL1_INT_EN BIT(5) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT3_TX_NULL0_DONE_INT_EN BIT(4) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI2_TX_NULL0_INT_EN BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT2_TX_NULL1_DONE_INT_EN BIT(3) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI1_TX_NULL1_INT_EN BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT2_TX_NULL0_DONE_INT_EN BIT(2) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI1_TX_NULL0_INT_EN BIT(2) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT1_TX_NULL1_DONE_INT_EN BIT(1) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI0_TX_NULL1_INT_EN BIT(1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT1_TX_NULL0_DONE_INT_EN BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ -#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN BIT(8) +#define BIT_FS_CLI0_TX_NULL0_INT_EN BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT BIT(31) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI3_RX_UAPSDMD1_INT BIT(31) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT BIT(30) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI3_RX_UAPSDMD0_INT BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT4_TRIPKT_OK_INT BIT(29) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI3_TRIGGER_PKT_INT BIT(29) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT4_RX_EOSP_OK_INT BIT(28) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI3_EOSP_INT BIT(28) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT BIT(27) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI2_RX_UAPSDMD1_INT BIT(27) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT BIT(26) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI2_RX_UAPSDMD0_INT BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT3_TRIPKT_OK_INT BIT(25) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI2_TRIGGER_PKT_INT BIT(25) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT3_RX_EOSP_OK_INT BIT(24) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI2_EOSP_INT BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT BIT(23) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI1_RX_UAPSDMD1_INT BIT(23) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT BIT(22) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN BIT(8) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_FS_CLI1_RX_UAPSDMD0_INT BIT(22) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_PORT4_TX_NULL1_DONE_INT_EN BIT(7) +#define BIT_PORT2_TRIPKT_OK_INT BIT(21) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_FS_CLI1_TRIGGER_PKT_INT BIT(21) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_CLI3_TX_NULL1_INT_EN BIT(7) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_PORT2_RX_EOSP_OK_INT BIT(20) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_PORT4_TX_NULL0_DONE_INT_EN BIT(6) +#define BIT_FS_CLI1_EOSP_INT BIT(20) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT BIT(19) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_CLI3_TX_NULL0_INT_EN BIT(6) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_FS_CLI0_RX_UAPSDMD1_INT BIT(19) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_PORT3_TX_NULL1_DONE_INT_EN BIT(5) +#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT BIT(18) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_FS_CLI0_RX_UAPSDMD0_INT BIT(18) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_CLI2_TX_NULL1_INT_EN BIT(5) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_PORT1_TRIPKT_OK_INT BIT(17) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_PORT3_TX_NULL0_DONE_INT_EN BIT(4) +#define BIT_FS_CLI0_TRIGGER_PKT_INT BIT(17) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_PORT1_RX_EOSP_OK_INT BIT(16) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_CLI2_TX_NULL0_INT_EN BIT(4) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_FS_CLI0_EOSP_INT BIT(16) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_PORT2_TX_NULL1_DONE_INT_EN BIT(3) +#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT BIT(9) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT BIT(9) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_CLI1_TX_NULL1_INT_EN BIT(3) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT BIT(8) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_PORT2_TX_NULL0_DONE_INT_EN BIT(2) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT BIT(8) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_PORT4_TX_NULL1_DONE_INT BIT(7) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_CLI1_TX_NULL0_INT_EN BIT(2) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_FS_CLI3_TX_NULL1_INT BIT(7) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_PORT1_TX_NULL1_DONE_INT_EN BIT(1) +#define BIT_PORT4_TX_NULL0_DONE_INT BIT(6) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_FS_CLI3_TX_NULL0_INT BIT(6) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_CLI0_TX_NULL1_INT_EN BIT(1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_PORT3_TX_NULL1_DONE_INT BIT(5) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_PORT1_TX_NULL0_DONE_INT_EN BIT(0) +#define BIT_FS_CLI2_TX_NULL1_INT BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_PORT3_TX_NULL0_DONE_INT BIT(4) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_CLI0_TX_NULL0_INT_EN BIT(0) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_FS_CLI2_TX_NULL0_INT BIT(4) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT BIT(31) +#define BIT_PORT2_TX_NULL1_DONE_INT BIT(3) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_FS_CLI3_RX_UAPSDMD1_INT BIT(31) +#define BIT_FS_CLI1_TX_NULL1_INT BIT(3) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT BIT(30) +#define BIT_PORT2_TX_NULL0_DONE_INT BIT(2) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_FS_CLI3_RX_UAPSDMD0_INT BIT(30) +#define BIT_FS_CLI1_TX_NULL0_INT BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT1_TX_NULL1_DONE_INT BIT(1) +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_PORT4_TRIPKT_OK_INT BIT(29) +#define BIT_FS_CLI0_TX_NULL1_INT BIT(1) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_PORT1_TX_NULL0_DONE_INT BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ -#define BIT_FS_CLI3_TRIGGER_PKT_INT BIT(29) +#define BIT_FS_CLI0_TX_NULL0_INT BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_MSG2 (Offset 0x11F0) */ +#define BIT_SHIFT_FW_MSG2 0 +#define BIT_MASK_FW_MSG2 0xffffffffL +#define BIT_FW_MSG2(x) (((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2) +#define BITS_FW_MSG2 (BIT_MASK_FW_MSG2 << BIT_SHIFT_FW_MSG2) +#define BIT_CLEAR_FW_MSG2(x) ((x) & (~BITS_FW_MSG2)) +#define BIT_GET_FW_MSG2(x) (((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2) +#define BIT_SET_FW_MSG2(x, v) (BIT_CLEAR_FW_MSG2(x) | BIT_FW_MSG2(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_MSG3 (Offset 0x11F4) */ -#define BIT_PORT4_RX_EOSP_OK_INT BIT(28) +#define BIT_SHIFT_FW_MSG3 0 +#define BIT_MASK_FW_MSG3 0xffffffffL +#define BIT_FW_MSG3(x) (((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3) +#define BITS_FW_MSG3 (BIT_MASK_FW_MSG3 << BIT_SHIFT_FW_MSG3) +#define BIT_CLEAR_FW_MSG3(x) ((x) & (~BITS_FW_MSG3)) +#define BIT_GET_FW_MSG3(x) (((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3) +#define BIT_SET_FW_MSG3(x, v) (BIT_CLEAR_FW_MSG3(x) | BIT_FW_MSG3(v)) -#endif +/* 2 REG_MSG4 (Offset 0x11F8) */ +#define BIT_SHIFT_FW_MSG4 0 +#define BIT_MASK_FW_MSG4 0xffffffffL +#define BIT_FW_MSG4(x) (((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4) +#define BITS_FW_MSG4 (BIT_MASK_FW_MSG4 << BIT_SHIFT_FW_MSG4) +#define BIT_CLEAR_FW_MSG4(x) ((x) & (~BITS_FW_MSG4)) +#define BIT_GET_FW_MSG4(x) (((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4) +#define BIT_SET_FW_MSG4(x, v) (BIT_CLEAR_FW_MSG4(x) | BIT_FW_MSG4(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MSG5 (Offset 0x11FC) */ +#define BIT_SHIFT_FW_MSG5 0 +#define BIT_MASK_FW_MSG5 0xffffffffL +#define BIT_FW_MSG5(x) (((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5) +#define BITS_FW_MSG5 (BIT_MASK_FW_MSG5 << BIT_SHIFT_FW_MSG5) +#define BIT_CLEAR_FW_MSG5(x) ((x) & (~BITS_FW_MSG5)) +#define BIT_GET_FW_MSG5(x) (((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5) +#define BIT_SET_FW_MSG5(x, v) (BIT_CLEAR_FW_MSG5(x) | BIT_FW_MSG5(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH0SA (Offset 0x1200) */ -#define BIT_FS_CLI3_EOSP_INT BIT(28) +#define BIT_SHIFT_DDMACH0_SA 0 +#define BIT_MASK_DDMACH0_SA 0xffffffffL +#define BIT_DDMACH0_SA(x) (((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA) +#define BITS_DDMACH0_SA (BIT_MASK_DDMACH0_SA << BIT_SHIFT_DDMACH0_SA) +#define BIT_CLEAR_DDMACH0_SA(x) ((x) & (~BITS_DDMACH0_SA)) +#define BIT_GET_DDMACH0_SA(x) \ + (((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA) +#define BIT_SET_DDMACH0_SA(x, v) (BIT_CLEAR_DDMACH0_SA(x) | BIT_DDMACH0_SA(v)) -#endif +/* 2 REG_DDMA_CH0DA (Offset 0x1204) */ +#define BIT_SHIFT_DDMACH0_DA 0 +#define BIT_MASK_DDMACH0_DA 0xffffffffL +#define BIT_DDMACH0_DA(x) (((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA) +#define BITS_DDMACH0_DA (BIT_MASK_DDMACH0_DA << BIT_SHIFT_DDMACH0_DA) +#define BIT_CLEAR_DDMACH0_DA(x) ((x) & (~BITS_DDMACH0_DA)) +#define BIT_GET_DDMACH0_DA(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA) +#define BIT_SET_DDMACH0_DA(x, v) (BIT_CLEAR_DDMACH0_DA(x) | BIT_DDMACH0_DA(v)) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ +#define BIT_DDMACH0_OWN BIT(31) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT BIT(27) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ +#define BIT_DDMACH0_ERR_MON BIT(30) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ -#define BIT_FS_CLI2_RX_UAPSDMD1_INT BIT(27) +#define BIT_DDMACH0_IDMEM_ERR BIT(30) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ +#define BIT_DDMACH0_CHKSUM_EN BIT(29) +#define BIT_DDMACH0_DA_W_DISABLE BIT(28) +#define BIT_DDMACH0_CHKSUM_STS BIT(27) +#define BIT_DDMACH0_DDMA_MODE BIT(26) +#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH0_CHKSUM_CONT BIT(24) + +#define BIT_SHIFT_DDMACH0_DLEN 0 +#define BIT_MASK_DDMACH0_DLEN 0x3ffff +#define BIT_DDMACH0_DLEN(x) \ + (((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN) +#define BITS_DDMACH0_DLEN (BIT_MASK_DDMACH0_DLEN << BIT_SHIFT_DDMACH0_DLEN) +#define BIT_CLEAR_DDMACH0_DLEN(x) ((x) & (~BITS_DDMACH0_DLEN)) +#define BIT_GET_DDMACH0_DLEN(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN) +#define BIT_SET_DDMACH0_DLEN(x, v) \ + (BIT_CLEAR_DDMACH0_DLEN(x) | BIT_DDMACH0_DLEN(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH1SA (Offset 0x1210) */ -#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT BIT(26) +#define BIT_SHIFT_DDMACH1_SA 0 +#define BIT_MASK_DDMACH1_SA 0xffffffffL +#define BIT_DDMACH1_SA(x) (((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA) +#define BITS_DDMACH1_SA (BIT_MASK_DDMACH1_SA << BIT_SHIFT_DDMACH1_SA) +#define BIT_CLEAR_DDMACH1_SA(x) ((x) & (~BITS_DDMACH1_SA)) +#define BIT_GET_DDMACH1_SA(x) \ + (((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA) +#define BIT_SET_DDMACH1_SA(x, v) (BIT_CLEAR_DDMACH1_SA(x) | BIT_DDMACH1_SA(v)) -#endif +/* 2 REG_DDMA_CH1DA (Offset 0x1214) */ +#define BIT_SHIFT_DDMACH1_DA 0 +#define BIT_MASK_DDMACH1_DA 0xffffffffL +#define BIT_DDMACH1_DA(x) (((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA) +#define BITS_DDMACH1_DA (BIT_MASK_DDMACH1_DA << BIT_SHIFT_DDMACH1_DA) +#define BIT_CLEAR_DDMACH1_DA(x) ((x) & (~BITS_DDMACH1_DA)) +#define BIT_GET_DDMACH1_DA(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA) +#define BIT_SET_DDMACH1_DA(x, v) (BIT_CLEAR_DDMACH1_DA(x) | BIT_DDMACH1_DA(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ +#define BIT_DDMACH1_OWN BIT(31) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI2_RX_UAPSDMD0_INT BIT(26) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ +#define BIT_DDMACH1_ERR_MON BIT(30) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ -#define BIT_PORT3_TRIPKT_OK_INT BIT(25) +#define BIT_DDMACH1_IDMEM_ERR BIT(30) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ +#define BIT_DDMACH1_CHKSUM_EN BIT(29) +#define BIT_DDMACH1_DA_W_DISABLE BIT(28) +#define BIT_DDMACH1_CHKSUM_STS BIT(27) +#define BIT_DDMACH1_DDMA_MODE BIT(26) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI2_TRIGGER_PKT_INT BIT(25) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ +#define BIT_DDMACH1_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH1_CHKSUM_CONT BIT(24) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ -#define BIT_PORT3_RX_EOSP_OK_INT BIT(24) +#define BIT_SHIFT_DDMACH1_DLEN 0 +#define BIT_MASK_DDMACH1_DLEN 0x3ffff +#define BIT_DDMACH1_DLEN(x) \ + (((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN) +#define BITS_DDMACH1_DLEN (BIT_MASK_DDMACH1_DLEN << BIT_SHIFT_DDMACH1_DLEN) +#define BIT_CLEAR_DDMACH1_DLEN(x) ((x) & (~BITS_DDMACH1_DLEN)) +#define BIT_GET_DDMACH1_DLEN(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN) +#define BIT_SET_DDMACH1_DLEN(x, v) \ + (BIT_CLEAR_DDMACH1_DLEN(x) | BIT_DDMACH1_DLEN(v)) -#endif +/* 2 REG_DDMA_CH2SA (Offset 0x1220) */ +#define BIT_SHIFT_DDMACH2_SA 0 +#define BIT_MASK_DDMACH2_SA 0xffffffffL +#define BIT_DDMACH2_SA(x) (((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA) +#define BITS_DDMACH2_SA (BIT_MASK_DDMACH2_SA << BIT_SHIFT_DDMACH2_SA) +#define BIT_CLEAR_DDMACH2_SA(x) ((x) & (~BITS_DDMACH2_SA)) +#define BIT_GET_DDMACH2_SA(x) \ + (((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA) +#define BIT_SET_DDMACH2_SA(x, v) (BIT_CLEAR_DDMACH2_SA(x) | BIT_DDMACH2_SA(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DDMA_CH2DA (Offset 0x1224) */ +#define BIT_SHIFT_DDMACH2_DA 0 +#define BIT_MASK_DDMACH2_DA 0xffffffffL +#define BIT_DDMACH2_DA(x) (((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA) +#define BITS_DDMACH2_DA (BIT_MASK_DDMACH2_DA << BIT_SHIFT_DDMACH2_DA) +#define BIT_CLEAR_DDMACH2_DA(x) ((x) & (~BITS_DDMACH2_DA)) +#define BIT_GET_DDMACH2_DA(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA) +#define BIT_SET_DDMACH2_DA(x, v) (BIT_CLEAR_DDMACH2_DA(x) | BIT_DDMACH2_DA(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ -#define BIT_FS_CLI2_EOSP_INT BIT(24) +#define BIT_DDMACH2_OWN BIT(31) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ +#define BIT_DDMACH2_ERR_MON BIT(30) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT BIT(23) +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ +#define BIT_DDMACH2_IDMEM_ERR BIT(30) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ -#define BIT_FS_CLI1_RX_UAPSDMD1_INT BIT(23) +#define BIT_DDMACH2_CHKSUM_EN BIT(29) +#define BIT_DDMACH2_DA_W_DISABLE BIT(28) +#define BIT_DDMACH2_CHKSUM_STS BIT(27) +#define BIT_DDMACH2_DDMA_MODE BIT(26) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ +#define BIT_DDMACH2_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH2_CHKSUM_CONT BIT(24) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT BIT(22) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ +#define BIT_SHIFT_DDMACH2_DLEN 0 +#define BIT_MASK_DDMACH2_DLEN 0x3ffff +#define BIT_DDMACH2_DLEN(x) \ + (((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN) +#define BITS_DDMACH2_DLEN (BIT_MASK_DDMACH2_DLEN << BIT_SHIFT_DDMACH2_DLEN) +#define BIT_CLEAR_DDMACH2_DLEN(x) ((x) & (~BITS_DDMACH2_DLEN)) +#define BIT_GET_DDMACH2_DLEN(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN) +#define BIT_SET_DDMACH2_DLEN(x, v) \ + (BIT_CLEAR_DDMACH2_DLEN(x) | BIT_DDMACH2_DLEN(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DDMA_CH3SA (Offset 0x1230) */ +#define BIT_SHIFT_DDMACH3_SA 0 +#define BIT_MASK_DDMACH3_SA 0xffffffffL +#define BIT_DDMACH3_SA(x) (((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA) +#define BITS_DDMACH3_SA (BIT_MASK_DDMACH3_SA << BIT_SHIFT_DDMACH3_SA) +#define BIT_CLEAR_DDMACH3_SA(x) ((x) & (~BITS_DDMACH3_SA)) +#define BIT_GET_DDMACH3_SA(x) \ + (((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA) +#define BIT_SET_DDMACH3_SA(x, v) (BIT_CLEAR_DDMACH3_SA(x) | BIT_DDMACH3_SA(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH3DA (Offset 0x1234) */ -#define BIT_FS_CLI1_RX_UAPSDMD0_INT BIT(22) +#define BIT_SHIFT_DDMACH3_DA 0 +#define BIT_MASK_DDMACH3_DA 0xffffffffL +#define BIT_DDMACH3_DA(x) (((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA) +#define BITS_DDMACH3_DA (BIT_MASK_DDMACH3_DA << BIT_SHIFT_DDMACH3_DA) +#define BIT_CLEAR_DDMACH3_DA(x) ((x) & (~BITS_DDMACH3_DA)) +#define BIT_GET_DDMACH3_DA(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA) +#define BIT_SET_DDMACH3_DA(x, v) (BIT_CLEAR_DDMACH3_DA(x) | BIT_DDMACH3_DA(v)) -#endif +/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ +#define BIT_DDMACH3_OWN BIT(31) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ -#define BIT_PORT2_TRIPKT_OK_INT BIT(21) +#define BIT_DDMACH3_ERR_MON BIT(30) #endif +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ +#define BIT_DDMACH3_IDMEM_ERR BIT(30) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI1_TRIGGER_PKT_INT BIT(21) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ +#define BIT_DDMACH3_CHKSUM_EN BIT(29) +#define BIT_DDMACH3_DA_W_DISABLE BIT(28) +#define BIT_DDMACH3_CHKSUM_STS BIT(27) +#define BIT_DDMACH3_DDMA_MODE BIT(26) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ -#define BIT_PORT2_RX_EOSP_OK_INT BIT(20) +#define BIT_DDMACH3_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH3_CHKSUM_CONT BIT(24) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ +#define BIT_SHIFT_DDMACH3_DLEN 0 +#define BIT_MASK_DDMACH3_DLEN 0x3ffff +#define BIT_DDMACH3_DLEN(x) \ + (((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN) +#define BITS_DDMACH3_DLEN (BIT_MASK_DDMACH3_DLEN << BIT_SHIFT_DDMACH3_DLEN) +#define BIT_CLEAR_DDMACH3_DLEN(x) ((x) & (~BITS_DDMACH3_DLEN)) +#define BIT_GET_DDMACH3_DLEN(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN) +#define BIT_SET_DDMACH3_DLEN(x, v) \ + (BIT_CLEAR_DDMACH3_DLEN(x) | BIT_DDMACH3_DLEN(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH4SA (Offset 0x1240) */ -#define BIT_FS_CLI1_EOSP_INT BIT(20) +#define BIT_SHIFT_DDMACH4_SA 0 +#define BIT_MASK_DDMACH4_SA 0xffffffffL +#define BIT_DDMACH4_SA(x) (((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA) +#define BITS_DDMACH4_SA (BIT_MASK_DDMACH4_SA << BIT_SHIFT_DDMACH4_SA) +#define BIT_CLEAR_DDMACH4_SA(x) ((x) & (~BITS_DDMACH4_SA)) +#define BIT_GET_DDMACH4_SA(x) \ + (((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA) +#define BIT_SET_DDMACH4_SA(x, v) (BIT_CLEAR_DDMACH4_SA(x) | BIT_DDMACH4_SA(v)) -#endif +/* 2 REG_DDMA_CH4DA (Offset 0x1244) */ +#define BIT_SHIFT_DDMACH4_DA 0 +#define BIT_MASK_DDMACH4_DA 0xffffffffL +#define BIT_DDMACH4_DA(x) (((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA) +#define BITS_DDMACH4_DA (BIT_MASK_DDMACH4_DA << BIT_SHIFT_DDMACH4_DA) +#define BIT_CLEAR_DDMACH4_DA(x) ((x) & (~BITS_DDMACH4_DA)) +#define BIT_GET_DDMACH4_DA(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA) +#define BIT_SET_DDMACH4_DA(x, v) (BIT_CLEAR_DDMACH4_DA(x) | BIT_DDMACH4_DA(v)) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ +#define BIT_DDMACH4_OWN BIT(31) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT BIT(19) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ +#define BIT_DDMACH4_ERR_MON BIT(30) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ -#define BIT_FS_CLI0_RX_UAPSDMD1_INT BIT(19) +#define BIT_DDMACH4_IDMEM_ERR BIT(30) +#define BIT_DDMACH5_IDMEM_ERR BIT(30) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ +#define BIT_DDMACH4_CHKSUM_EN BIT(29) +#define BIT_DDMACH4_DA_W_DISABLE BIT(28) +#define BIT_DDMACH4_CHKSUM_STS BIT(27) +#define BIT_DDMACH4_DDMA_MODE BIT(26) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT BIT(18) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ +#define BIT_DDMACH4_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH4_CHKSUM_CONT BIT(24) +#define BIT_DDMACH5_CHKSUM_CONT BIT(24) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ -#define BIT_FS_CLI0_RX_UAPSDMD0_INT BIT(18) +#define BIT_SHIFT_DDMACH4_DLEN 0 +#define BIT_MASK_DDMACH4_DLEN 0x3ffff +#define BIT_DDMACH4_DLEN(x) \ + (((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN) +#define BITS_DDMACH4_DLEN (BIT_MASK_DDMACH4_DLEN << BIT_SHIFT_DDMACH4_DLEN) +#define BIT_CLEAR_DDMACH4_DLEN(x) ((x) & (~BITS_DDMACH4_DLEN)) +#define BIT_GET_DDMACH4_DLEN(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN) +#define BIT_SET_DDMACH4_DLEN(x, v) \ + (BIT_CLEAR_DDMACH4_DLEN(x) | BIT_DDMACH4_DLEN(v)) -#endif +/* 2 REG_DDMA_CH5SA (Offset 0x1250) */ +#define BIT_SHIFT_DDMACH5_SA 0 +#define BIT_MASK_DDMACH5_SA 0xffffffffL +#define BIT_DDMACH5_SA(x) (((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA) +#define BITS_DDMACH5_SA (BIT_MASK_DDMACH5_SA << BIT_SHIFT_DDMACH5_SA) +#define BIT_CLEAR_DDMACH5_SA(x) ((x) & (~BITS_DDMACH5_SA)) +#define BIT_GET_DDMACH5_SA(x) \ + (((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA) +#define BIT_SET_DDMACH5_SA(x, v) (BIT_CLEAR_DDMACH5_SA(x) | BIT_DDMACH5_SA(v)) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DDMA_CH5DA (Offset 0x1254) */ +#define BIT_DDMACH5_OWN BIT(31) +#define BIT_DDMACH5_CHKSUM_EN BIT(29) +#define BIT_DDMACH5_DA_W_DISABLE BIT(28) +#define BIT_DDMACH5_CHKSUM_STS BIT(27) +#define BIT_DDMACH5_DDMA_MODE BIT(26) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_SHIFT_DDMACH5_DA 0 +#define BIT_MASK_DDMACH5_DA 0xffffffffL +#define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA) +#define BITS_DDMACH5_DA (BIT_MASK_DDMACH5_DA << BIT_SHIFT_DDMACH5_DA) +#define BIT_CLEAR_DDMACH5_DA(x) ((x) & (~BITS_DDMACH5_DA)) +#define BIT_GET_DDMACH5_DA(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA) +#define BIT_SET_DDMACH5_DA(x, v) (BIT_CLEAR_DDMACH5_DA(x) | BIT_DDMACH5_DA(v)) -#define BIT_PORT1_TRIPKT_OK_INT BIT(17) +#define BIT_SHIFT_DDMACH5_DLEN 0 +#define BIT_MASK_DDMACH5_DLEN 0x3ffff +#define BIT_DDMACH5_DLEN(x) \ + (((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN) +#define BITS_DDMACH5_DLEN (BIT_MASK_DDMACH5_DLEN << BIT_SHIFT_DDMACH5_DLEN) +#define BIT_CLEAR_DDMACH5_DLEN(x) ((x) & (~BITS_DDMACH5_DLEN)) +#define BIT_GET_DDMACH5_DLEN(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN) +#define BIT_SET_DDMACH5_DLEN(x, v) \ + (BIT_CLEAR_DDMACH5_DLEN(x) | BIT_DDMACH5_DLEN(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_REG_DDMA_CH5CTRL (Offset 0x1258) */ +#define BIT_DDMACH5_ERR_MON BIT(30) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI0_TRIGGER_PKT_INT BIT(17) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_DDMA_INT_MSK (Offset 0x12E0) */ +#define BIT_DDMACH5_MSK BIT(5) +#define BIT_DDMACH4_MSK BIT(4) +#define BIT_DDMACH3_MSK BIT(3) +#define BIT_DDMACH2_MSK BIT(2) +#define BIT_DDMACH1_MSK BIT(1) +#define BIT_DDMACH0_MSK BIT(0) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DDMA_CHSTATUS (Offset 0x12E8) */ +#define BIT_DDMACH5_BUSY BIT(5) +#define BIT_DDMACH4_BUSY BIT(4) +#define BIT_DDMACH3_BUSY BIT(3) +#define BIT_DDMACH2_BUSY BIT(2) +#define BIT_DDMACH1_BUSY BIT(1) +#define BIT_DDMACH0_BUSY BIT(0) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_DDMA_CHKSUM (Offset 0x12F0) */ -#define BIT_PORT1_RX_EOSP_OK_INT BIT(16) +#define BIT_SHIFT_IDDMA0_CHKSUM 0 +#define BIT_MASK_IDDMA0_CHKSUM 0xffff +#define BIT_IDDMA0_CHKSUM(x) \ + (((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM) +#define BITS_IDDMA0_CHKSUM (BIT_MASK_IDDMA0_CHKSUM << BIT_SHIFT_IDDMA0_CHKSUM) +#define BIT_CLEAR_IDDMA0_CHKSUM(x) ((x) & (~BITS_IDDMA0_CHKSUM)) +#define BIT_GET_IDDMA0_CHKSUM(x) \ + (((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM) +#define BIT_SET_IDDMA0_CHKSUM(x, v) \ + (BIT_CLEAR_IDDMA0_CHKSUM(x) | BIT_IDDMA0_CHKSUM(v)) -#endif +/* 2 REG_DDMA_MONITOR (Offset 0x12FC) */ +#define BIT_IDDMA0_PERMU_UNDERFLOW BIT(14) +#define BIT_IDDMA0_FIFO_UNDERFLOW BIT(13) +#define BIT_IDDMA0_FIFO_OVERFLOW BIT(12) +#define BIT_CH5_ERR BIT(5) +#define BIT_CH4_ERR BIT(4) +#define BIT_CH3_ERR BIT(3) +#define BIT_CH2_ERR BIT(2) +#define BIT_CH1_ERR BIT(1) +#define BIT_CH0_ERR BIT(0) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_STC_INT_CS (Offset 0x1300) */ -#define BIT_FS_CLI0_EOSP_INT BIT(16) +#define BIT_STC_INT_EN BIT(31) +#define BIT_STC_INT_GRP_EN BIT(31) + +#define BIT_SHIFT_STC_INT_FLAG 16 +#define BIT_MASK_STC_INT_FLAG 0xff +#define BIT_STC_INT_FLAG(x) \ + (((x) & BIT_MASK_STC_INT_FLAG) << BIT_SHIFT_STC_INT_FLAG) +#define BITS_STC_INT_FLAG (BIT_MASK_STC_INT_FLAG << BIT_SHIFT_STC_INT_FLAG) +#define BIT_CLEAR_STC_INT_FLAG(x) ((x) & (~BITS_STC_INT_FLAG)) +#define BIT_GET_STC_INT_FLAG(x) \ + (((x) >> BIT_SHIFT_STC_INT_FLAG) & BIT_MASK_STC_INT_FLAG) +#define BIT_SET_STC_INT_FLAG(x, v) \ + (BIT_CLEAR_STC_INT_FLAG(x) | BIT_STC_INT_FLAG(v)) + +#define BIT_SHIFT_STC_INT_IDX 8 +#define BIT_MASK_STC_INT_IDX 0x7 +#define BIT_STC_INT_IDX(x) \ + (((x) & BIT_MASK_STC_INT_IDX) << BIT_SHIFT_STC_INT_IDX) +#define BITS_STC_INT_IDX (BIT_MASK_STC_INT_IDX << BIT_SHIFT_STC_INT_IDX) +#define BIT_CLEAR_STC_INT_IDX(x) ((x) & (~BITS_STC_INT_IDX)) +#define BIT_GET_STC_INT_IDX(x) \ + (((x) >> BIT_SHIFT_STC_INT_IDX) & BIT_MASK_STC_INT_IDX) +#define BIT_SET_STC_INT_IDX(x, v) \ + (BIT_CLEAR_STC_INT_IDX(x) | BIT_STC_INT_IDX(v)) + +#define BIT_SHIFT_STC_INT_EXPECT_LS 8 +#define BIT_MASK_STC_INT_EXPECT_LS 0x3f +#define BIT_STC_INT_EXPECT_LS(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_LS) << BIT_SHIFT_STC_INT_EXPECT_LS) +#define BITS_STC_INT_EXPECT_LS \ + (BIT_MASK_STC_INT_EXPECT_LS << BIT_SHIFT_STC_INT_EXPECT_LS) +#define BIT_CLEAR_STC_INT_EXPECT_LS(x) ((x) & (~BITS_STC_INT_EXPECT_LS)) +#define BIT_GET_STC_INT_EXPECT_LS(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS) & BIT_MASK_STC_INT_EXPECT_LS) +#define BIT_SET_STC_INT_EXPECT_LS(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_LS(x) | BIT_STC_INT_EXPECT_LS(v)) + +#define BIT_SHIFT_STC_INT_REALTIME_CS 0 +#define BIT_MASK_STC_INT_REALTIME_CS 0x3f +#define BIT_STC_INT_REALTIME_CS(x) \ + (((x) & BIT_MASK_STC_INT_REALTIME_CS) << BIT_SHIFT_STC_INT_REALTIME_CS) +#define BITS_STC_INT_REALTIME_CS \ + (BIT_MASK_STC_INT_REALTIME_CS << BIT_SHIFT_STC_INT_REALTIME_CS) +#define BIT_CLEAR_STC_INT_REALTIME_CS(x) ((x) & (~BITS_STC_INT_REALTIME_CS)) +#define BIT_GET_STC_INT_REALTIME_CS(x) \ + (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS) & BIT_MASK_STC_INT_REALTIME_CS) +#define BIT_SET_STC_INT_REALTIME_CS(x, v) \ + (BIT_CLEAR_STC_INT_REALTIME_CS(x) | BIT_STC_INT_REALTIME_CS(v)) + +#define BIT_SHIFT_STC_INT_EXPECT_CS 0 +#define BIT_MASK_STC_INT_EXPECT_CS 0x3f +#define BIT_STC_INT_EXPECT_CS(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_CS) << BIT_SHIFT_STC_INT_EXPECT_CS) +#define BITS_STC_INT_EXPECT_CS \ + (BIT_MASK_STC_INT_EXPECT_CS << BIT_SHIFT_STC_INT_EXPECT_CS) +#define BIT_CLEAR_STC_INT_EXPECT_CS(x) ((x) & (~BITS_STC_INT_EXPECT_CS)) +#define BIT_GET_STC_INT_EXPECT_CS(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS) & BIT_MASK_STC_INT_EXPECT_CS) +#define BIT_SET_STC_INT_EXPECT_CS(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_CS(x) | BIT_STC_INT_EXPECT_CS(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH4_ACH5_TXBD_NUM (Offset 0x130C) */ + +#define BIT_PCIE_ACH5_FLAG BIT(30) + +#define BIT_SHIFT_ACH5_DESC_MODE 28 +#define BIT_MASK_ACH5_DESC_MODE 0x3 +#define BIT_ACH5_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH5_DESC_MODE) << BIT_SHIFT_ACH5_DESC_MODE) +#define BITS_ACH5_DESC_MODE \ + (BIT_MASK_ACH5_DESC_MODE << BIT_SHIFT_ACH5_DESC_MODE) +#define BIT_CLEAR_ACH5_DESC_MODE(x) ((x) & (~BITS_ACH5_DESC_MODE)) +#define BIT_GET_ACH5_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH5_DESC_MODE) & BIT_MASK_ACH5_DESC_MODE) +#define BIT_SET_ACH5_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH5_DESC_MODE(x) | BIT_ACH5_DESC_MODE(v)) + +#define BIT_SHIFT_ACH5_DESC_NUM 16 +#define BIT_MASK_ACH5_DESC_NUM 0xfff +#define BIT_ACH5_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH5_DESC_NUM) << BIT_SHIFT_ACH5_DESC_NUM) +#define BITS_ACH5_DESC_NUM (BIT_MASK_ACH5_DESC_NUM << BIT_SHIFT_ACH5_DESC_NUM) +#define BIT_CLEAR_ACH5_DESC_NUM(x) ((x) & (~BITS_ACH5_DESC_NUM)) +#define BIT_GET_ACH5_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH5_DESC_NUM) & BIT_MASK_ACH5_DESC_NUM) +#define BIT_SET_ACH5_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH5_DESC_NUM(x) | BIT_ACH5_DESC_NUM(v)) + +#define BIT_PCIE_ACH4_FLAG BIT(14) + +#define BIT_SHIFT_ACH4_DESC_MODE 12 +#define BIT_MASK_ACH4_DESC_MODE 0x3 +#define BIT_ACH4_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH4_DESC_MODE) << BIT_SHIFT_ACH4_DESC_MODE) +#define BITS_ACH4_DESC_MODE \ + (BIT_MASK_ACH4_DESC_MODE << BIT_SHIFT_ACH4_DESC_MODE) +#define BIT_CLEAR_ACH4_DESC_MODE(x) ((x) & (~BITS_ACH4_DESC_MODE)) +#define BIT_GET_ACH4_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH4_DESC_MODE) & BIT_MASK_ACH4_DESC_MODE) +#define BIT_SET_ACH4_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH4_DESC_MODE(x) | BIT_ACH4_DESC_MODE(v)) + +#define BIT_SHIFT_ACH4_DESC_NUM 0 +#define BIT_MASK_ACH4_DESC_NUM 0xfff +#define BIT_ACH4_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH4_DESC_NUM) << BIT_SHIFT_ACH4_DESC_NUM) +#define BITS_ACH4_DESC_NUM (BIT_MASK_ACH4_DESC_NUM << BIT_SHIFT_ACH4_DESC_NUM) +#define BIT_CLEAR_ACH4_DESC_NUM(x) ((x) & (~BITS_ACH4_DESC_NUM)) +#define BIT_GET_ACH4_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH4_DESC_NUM) & BIT_MASK_ACH4_DESC_NUM) +#define BIT_SET_ACH4_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH4_DESC_NUM(x) | BIT_ACH4_DESC_NUM(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_CMU_DLY_CTRL (Offset 0x1310) */ +#define BIT_CMU_DLY_EN BIT(31) +#define BIT_CMU_DLY_MODE BIT(30) + +#define BIT_SHIFT_CMU_DLY_PRE_DIV 0 +#define BIT_MASK_CMU_DLY_PRE_DIV 0xff +#define BIT_CMU_DLY_PRE_DIV(x) \ + (((x) & BIT_MASK_CMU_DLY_PRE_DIV) << BIT_SHIFT_CMU_DLY_PRE_DIV) +#define BITS_CMU_DLY_PRE_DIV \ + (BIT_MASK_CMU_DLY_PRE_DIV << BIT_SHIFT_CMU_DLY_PRE_DIV) +#define BIT_CLEAR_CMU_DLY_PRE_DIV(x) ((x) & (~BITS_CMU_DLY_PRE_DIV)) +#define BIT_GET_CMU_DLY_PRE_DIV(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV) & BIT_MASK_CMU_DLY_PRE_DIV) +#define BIT_SET_CMU_DLY_PRE_DIV(x, v) \ + (BIT_CLEAR_CMU_DLY_PRE_DIV(x) | BIT_CMU_DLY_PRE_DIV(v)) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_CMU_DLY_CFG (Offset 0x1314) */ +#define BIT_SHIFT_CMU_DLY_LTR_A2I 24 +#define BIT_MASK_CMU_DLY_LTR_A2I 0xff +#define BIT_CMU_DLY_LTR_A2I(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_A2I) << BIT_SHIFT_CMU_DLY_LTR_A2I) +#define BITS_CMU_DLY_LTR_A2I \ + (BIT_MASK_CMU_DLY_LTR_A2I << BIT_SHIFT_CMU_DLY_LTR_A2I) +#define BIT_CLEAR_CMU_DLY_LTR_A2I(x) ((x) & (~BITS_CMU_DLY_LTR_A2I)) +#define BIT_GET_CMU_DLY_LTR_A2I(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I) & BIT_MASK_CMU_DLY_LTR_A2I) +#define BIT_SET_CMU_DLY_LTR_A2I(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_A2I(x) | BIT_CMU_DLY_LTR_A2I(v)) + +#define BIT_SHIFT_CMU_DLY_LTR_I2A 16 +#define BIT_MASK_CMU_DLY_LTR_I2A 0xff +#define BIT_CMU_DLY_LTR_I2A(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_I2A) << BIT_SHIFT_CMU_DLY_LTR_I2A) +#define BITS_CMU_DLY_LTR_I2A \ + (BIT_MASK_CMU_DLY_LTR_I2A << BIT_SHIFT_CMU_DLY_LTR_I2A) +#define BIT_CLEAR_CMU_DLY_LTR_I2A(x) ((x) & (~BITS_CMU_DLY_LTR_I2A)) +#define BIT_GET_CMU_DLY_LTR_I2A(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A) & BIT_MASK_CMU_DLY_LTR_I2A) +#define BIT_SET_CMU_DLY_LTR_I2A(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_I2A(x) | BIT_CMU_DLY_LTR_I2A(v)) + +#define BIT_SHIFT_CMU_DLY_LTR_IDLE 8 +#define BIT_MASK_CMU_DLY_LTR_IDLE 0xff +#define BIT_CMU_DLY_LTR_IDLE(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_IDLE) << BIT_SHIFT_CMU_DLY_LTR_IDLE) +#define BITS_CMU_DLY_LTR_IDLE \ + (BIT_MASK_CMU_DLY_LTR_IDLE << BIT_SHIFT_CMU_DLY_LTR_IDLE) +#define BIT_CLEAR_CMU_DLY_LTR_IDLE(x) ((x) & (~BITS_CMU_DLY_LTR_IDLE)) +#define BIT_GET_CMU_DLY_LTR_IDLE(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE) & BIT_MASK_CMU_DLY_LTR_IDLE) +#define BIT_SET_CMU_DLY_LTR_IDLE(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_IDLE(x) | BIT_CMU_DLY_LTR_IDLE(v)) + +#define BIT_SHIFT_CMU_DLY_LTR_ACT 0 +#define BIT_MASK_CMU_DLY_LTR_ACT 0xff +#define BIT_CMU_DLY_LTR_ACT(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_ACT) << BIT_SHIFT_CMU_DLY_LTR_ACT) +#define BITS_CMU_DLY_LTR_ACT \ + (BIT_MASK_CMU_DLY_LTR_ACT << BIT_SHIFT_CMU_DLY_LTR_ACT) +#define BIT_CLEAR_CMU_DLY_LTR_ACT(x) ((x) & (~BITS_CMU_DLY_LTR_ACT)) +#define BIT_GET_CMU_DLY_LTR_ACT(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT) & BIT_MASK_CMU_DLY_LTR_ACT) +#define BIT_SET_CMU_DLY_LTR_ACT(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_ACT(x) | BIT_CMU_DLY_LTR_ACT(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FWCMDQ_TXBD_IDX (Offset 0x1318) */ + +#define BIT_SHIFT_FWCMDQ_HW_IDX 16 +#define BIT_MASK_FWCMDQ_HW_IDX 0xfff +#define BIT_FWCMDQ_HW_IDX(x) \ + (((x) & BIT_MASK_FWCMDQ_HW_IDX) << BIT_SHIFT_FWCMDQ_HW_IDX) +#define BITS_FWCMDQ_HW_IDX (BIT_MASK_FWCMDQ_HW_IDX << BIT_SHIFT_FWCMDQ_HW_IDX) +#define BIT_CLEAR_FWCMDQ_HW_IDX(x) ((x) & (~BITS_FWCMDQ_HW_IDX)) +#define BIT_GET_FWCMDQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_HW_IDX) & BIT_MASK_FWCMDQ_HW_IDX) +#define BIT_SET_FWCMDQ_HW_IDX(x, v) \ + (BIT_CLEAR_FWCMDQ_HW_IDX(x) | BIT_FWCMDQ_HW_IDX(v)) + +#define BIT_SHIFT_FWCMDQ_HOST_IDX 0 +#define BIT_MASK_FWCMDQ_HOST_IDX 0xfff +#define BIT_FWCMDQ_HOST_IDX(x) \ + (((x) & BIT_MASK_FWCMDQ_HOST_IDX) << BIT_SHIFT_FWCMDQ_HOST_IDX) +#define BITS_FWCMDQ_HOST_IDX \ + (BIT_MASK_FWCMDQ_HOST_IDX << BIT_SHIFT_FWCMDQ_HOST_IDX) +#define BIT_CLEAR_FWCMDQ_HOST_IDX(x) ((x) & (~BITS_FWCMDQ_HOST_IDX)) +#define BIT_GET_FWCMDQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_HOST_IDX) & BIT_MASK_FWCMDQ_HOST_IDX) +#define BIT_SET_FWCMDQ_HOST_IDX(x, v) \ + (BIT_CLEAR_FWCMDQ_HOST_IDX(x) | BIT_FWCMDQ_HOST_IDX(v)) + +/* 2 REG_P0HI8Q_TXBD_IDX (Offset 0x131C) */ + +#define BIT_SHIFT_P0HI8Q_HW_IDX 16 +#define BIT_MASK_P0HI8Q_HW_IDX 0xfff +#define BIT_P0HI8Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI8Q_HW_IDX) << BIT_SHIFT_P0HI8Q_HW_IDX) +#define BITS_P0HI8Q_HW_IDX (BIT_MASK_P0HI8Q_HW_IDX << BIT_SHIFT_P0HI8Q_HW_IDX) +#define BIT_CLEAR_P0HI8Q_HW_IDX(x) ((x) & (~BITS_P0HI8Q_HW_IDX)) +#define BIT_GET_P0HI8Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_HW_IDX) & BIT_MASK_P0HI8Q_HW_IDX) +#define BIT_SET_P0HI8Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI8Q_HW_IDX(x) | BIT_P0HI8Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI8Q_HOST_IDX 0 +#define BIT_MASK_P0HI8Q_HOST_IDX 0xfff +#define BIT_P0HI8Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI8Q_HOST_IDX) << BIT_SHIFT_P0HI8Q_HOST_IDX) +#define BITS_P0HI8Q_HOST_IDX \ + (BIT_MASK_P0HI8Q_HOST_IDX << BIT_SHIFT_P0HI8Q_HOST_IDX) +#define BIT_CLEAR_P0HI8Q_HOST_IDX(x) ((x) & (~BITS_P0HI8Q_HOST_IDX)) +#define BIT_GET_P0HI8Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_HOST_IDX) & BIT_MASK_P0HI8Q_HOST_IDX) +#define BIT_SET_P0HI8Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI8Q_HOST_IDX(x) | BIT_P0HI8Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_H2CQ_TXBD_DESA (Offset 0x1320) */ -#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT BIT(9) +#define BIT_SHIFT_H2CQ_TXBD_DESA 0 +#define BIT_MASK_H2CQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_H2CQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA) << BIT_SHIFT_H2CQ_TXBD_DESA) +#define BITS_H2CQ_TXBD_DESA \ + (BIT_MASK_H2CQ_TXBD_DESA << BIT_SHIFT_H2CQ_TXBD_DESA) +#define BIT_CLEAR_H2CQ_TXBD_DESA(x) ((x) & (~BITS_H2CQ_TXBD_DESA)) +#define BIT_GET_H2CQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA) & BIT_MASK_H2CQ_TXBD_DESA) +#define BIT_SET_H2CQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA(x) | BIT_H2CQ_TXBD_DESA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_H2CQ_TXBD_DESA_L (Offset 0x1320) */ +#define BIT_SHIFT_H2CQ_TXBD_DESA_L 0 +#define BIT_MASK_H2CQ_TXBD_DESA_L 0xffffffffL +#define BIT_H2CQ_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_L) << BIT_SHIFT_H2CQ_TXBD_DESA_L) +#define BITS_H2CQ_TXBD_DESA_L \ + (BIT_MASK_H2CQ_TXBD_DESA_L << BIT_SHIFT_H2CQ_TXBD_DESA_L) +#define BIT_CLEAR_H2CQ_TXBD_DESA_L(x) ((x) & (~BITS_H2CQ_TXBD_DESA_L)) +#define BIT_GET_H2CQ_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_L) & BIT_MASK_H2CQ_TXBD_DESA_L) +#define BIT_SET_H2CQ_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_L(x) | BIT_H2CQ_TXBD_DESA_L(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_H2CQ_TXBD_DESA_H (Offset 0x1324) */ -#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT BIT(9) +#define BIT_SHIFT_H2CQ_TXBD_DESA_H 0 +#define BIT_MASK_H2CQ_TXBD_DESA_H 0xffffffffL +#define BIT_H2CQ_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_H) << BIT_SHIFT_H2CQ_TXBD_DESA_H) +#define BITS_H2CQ_TXBD_DESA_H \ + (BIT_MASK_H2CQ_TXBD_DESA_H << BIT_SHIFT_H2CQ_TXBD_DESA_H) +#define BIT_CLEAR_H2CQ_TXBD_DESA_H(x) ((x) & (~BITS_H2CQ_TXBD_DESA_H)) +#define BIT_GET_H2CQ_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_H) & BIT_MASK_H2CQ_TXBD_DESA_H) +#define BIT_SET_H2CQ_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_H(x) | BIT_H2CQ_TXBD_DESA_H(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ -#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT BIT(8) +#define BIT_HCI_H2CQ_FLAG BIT(14) #endif +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ +#define BIT_PCIE_H2CQ_FLAG BIT(14) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT BIT(8) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ +#define BIT_SHIFT_H2CQ_DESC_MODE 12 +#define BIT_MASK_H2CQ_DESC_MODE 0x3 +#define BIT_H2CQ_DESC_MODE(x) \ + (((x) & BIT_MASK_H2CQ_DESC_MODE) << BIT_SHIFT_H2CQ_DESC_MODE) +#define BITS_H2CQ_DESC_MODE \ + (BIT_MASK_H2CQ_DESC_MODE << BIT_SHIFT_H2CQ_DESC_MODE) +#define BIT_CLEAR_H2CQ_DESC_MODE(x) ((x) & (~BITS_H2CQ_DESC_MODE)) +#define BIT_GET_H2CQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_MODE) & BIT_MASK_H2CQ_DESC_MODE) +#define BIT_SET_H2CQ_DESC_MODE(x, v) \ + (BIT_CLEAR_H2CQ_DESC_MODE(x) | BIT_H2CQ_DESC_MODE(v)) + +#define BIT_SHIFT_H2CQ_DESC_NUM 0 +#define BIT_MASK_H2CQ_DESC_NUM 0xfff +#define BIT_H2CQ_DESC_NUM(x) \ + (((x) & BIT_MASK_H2CQ_DESC_NUM) << BIT_SHIFT_H2CQ_DESC_NUM) +#define BITS_H2CQ_DESC_NUM (BIT_MASK_H2CQ_DESC_NUM << BIT_SHIFT_H2CQ_DESC_NUM) +#define BIT_CLEAR_H2CQ_DESC_NUM(x) ((x) & (~BITS_H2CQ_DESC_NUM)) +#define BIT_GET_H2CQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_NUM) & BIT_MASK_H2CQ_DESC_NUM) +#define BIT_SET_H2CQ_DESC_NUM(x, v) \ + (BIT_CLEAR_H2CQ_DESC_NUM(x) | BIT_H2CQ_DESC_NUM(v)) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_H2CQ_TXBD_IDX (Offset 0x132C) */ +#define BIT_SHIFT_H2CQ_HW_IDX 16 +#define BIT_MASK_H2CQ_HW_IDX 0xfff +#define BIT_H2CQ_HW_IDX(x) \ + (((x) & BIT_MASK_H2CQ_HW_IDX) << BIT_SHIFT_H2CQ_HW_IDX) +#define BITS_H2CQ_HW_IDX (BIT_MASK_H2CQ_HW_IDX << BIT_SHIFT_H2CQ_HW_IDX) +#define BIT_CLEAR_H2CQ_HW_IDX(x) ((x) & (~BITS_H2CQ_HW_IDX)) +#define BIT_GET_H2CQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_H2CQ_HW_IDX) & BIT_MASK_H2CQ_HW_IDX) +#define BIT_SET_H2CQ_HW_IDX(x, v) \ + (BIT_CLEAR_H2CQ_HW_IDX(x) | BIT_H2CQ_HW_IDX(v)) + +#define BIT_SHIFT_H2CQ_HOST_IDX 0 +#define BIT_MASK_H2CQ_HOST_IDX 0xfff +#define BIT_H2CQ_HOST_IDX(x) \ + (((x) & BIT_MASK_H2CQ_HOST_IDX) << BIT_SHIFT_H2CQ_HOST_IDX) +#define BITS_H2CQ_HOST_IDX (BIT_MASK_H2CQ_HOST_IDX << BIT_SHIFT_H2CQ_HOST_IDX) +#define BIT_CLEAR_H2CQ_HOST_IDX(x) ((x) & (~BITS_H2CQ_HOST_IDX)) +#define BIT_GET_H2CQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_H2CQ_HOST_IDX) & BIT_MASK_H2CQ_HOST_IDX) +#define BIT_SET_H2CQ_HOST_IDX(x, v) \ + (BIT_CLEAR_H2CQ_HOST_IDX(x) | BIT_H2CQ_HOST_IDX(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_H2CQ_CSR (Offset 0x1330) */ -#define BIT_PORT4_TX_NULL1_DONE_INT BIT(7) +#define BIT_H2CQ_FULL BIT(31) +#define BIT_CLR_H2CQ_HOST_IDX BIT(16) +#define BIT_CLR_H2CQ_HW_IDX BIT(8) +#define BIT_STOP_H2CQ BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI9Q_TXBD_IDX (Offset 0x1334) */ + +#define BIT_SHIFT_P0HI9Q_HW_IDX 16 +#define BIT_MASK_P0HI9Q_HW_IDX 0xfff +#define BIT_P0HI9Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI9Q_HW_IDX) << BIT_SHIFT_P0HI9Q_HW_IDX) +#define BITS_P0HI9Q_HW_IDX (BIT_MASK_P0HI9Q_HW_IDX << BIT_SHIFT_P0HI9Q_HW_IDX) +#define BIT_CLEAR_P0HI9Q_HW_IDX(x) ((x) & (~BITS_P0HI9Q_HW_IDX)) +#define BIT_GET_P0HI9Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_HW_IDX) & BIT_MASK_P0HI9Q_HW_IDX) +#define BIT_SET_P0HI9Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI9Q_HW_IDX(x) | BIT_P0HI9Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI9Q_HOST_IDX 0 +#define BIT_MASK_P0HI9Q_HOST_IDX 0xfff +#define BIT_P0HI9Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI9Q_HOST_IDX) << BIT_SHIFT_P0HI9Q_HOST_IDX) +#define BITS_P0HI9Q_HOST_IDX \ + (BIT_MASK_P0HI9Q_HOST_IDX << BIT_SHIFT_P0HI9Q_HOST_IDX) +#define BIT_CLEAR_P0HI9Q_HOST_IDX(x) ((x) & (~BITS_P0HI9Q_HOST_IDX)) +#define BIT_GET_P0HI9Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_HOST_IDX) & BIT_MASK_P0HI9Q_HOST_IDX) +#define BIT_SET_P0HI9Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI9Q_HOST_IDX(x) | BIT_P0HI9Q_HOST_IDX(v)) + +/* 2 REG_P0HI10Q_TXBD_IDX (Offset 0x1338) */ + +#define BIT_SHIFT_P0HI10Q_HW_IDX 16 +#define BIT_MASK_P0HI10Q_HW_IDX 0xfff +#define BIT_P0HI10Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI10Q_HW_IDX) << BIT_SHIFT_P0HI10Q_HW_IDX) +#define BITS_P0HI10Q_HW_IDX \ + (BIT_MASK_P0HI10Q_HW_IDX << BIT_SHIFT_P0HI10Q_HW_IDX) +#define BIT_CLEAR_P0HI10Q_HW_IDX(x) ((x) & (~BITS_P0HI10Q_HW_IDX)) +#define BIT_GET_P0HI10Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_HW_IDX) & BIT_MASK_P0HI10Q_HW_IDX) +#define BIT_SET_P0HI10Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI10Q_HW_IDX(x) | BIT_P0HI10Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI10Q_HOST_IDX 0 +#define BIT_MASK_P0HI10Q_HOST_IDX 0xfff +#define BIT_P0HI10Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI10Q_HOST_IDX) << BIT_SHIFT_P0HI10Q_HOST_IDX) +#define BITS_P0HI10Q_HOST_IDX \ + (BIT_MASK_P0HI10Q_HOST_IDX << BIT_SHIFT_P0HI10Q_HOST_IDX) +#define BIT_CLEAR_P0HI10Q_HOST_IDX(x) ((x) & (~BITS_P0HI10Q_HOST_IDX)) +#define BIT_GET_P0HI10Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_HOST_IDX) & BIT_MASK_P0HI10Q_HOST_IDX) +#define BIT_SET_P0HI10Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI10Q_HOST_IDX(x) | BIT_P0HI10Q_HOST_IDX(v)) + +/* 2 REG_P0HI11Q_TXBD_IDX (Offset 0x133C) */ + +#define BIT_SHIFT_P0HI11Q_HW_IDX 16 +#define BIT_MASK_P0HI11Q_HW_IDX 0xfff +#define BIT_P0HI11Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI11Q_HW_IDX) << BIT_SHIFT_P0HI11Q_HW_IDX) +#define BITS_P0HI11Q_HW_IDX \ + (BIT_MASK_P0HI11Q_HW_IDX << BIT_SHIFT_P0HI11Q_HW_IDX) +#define BIT_CLEAR_P0HI11Q_HW_IDX(x) ((x) & (~BITS_P0HI11Q_HW_IDX)) +#define BIT_GET_P0HI11Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_HW_IDX) & BIT_MASK_P0HI11Q_HW_IDX) +#define BIT_SET_P0HI11Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI11Q_HW_IDX(x) | BIT_P0HI11Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI11Q_HOST_IDX 0 +#define BIT_MASK_P0HI11Q_HOST_IDX 0xfff +#define BIT_P0HI11Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI11Q_HOST_IDX) << BIT_SHIFT_P0HI11Q_HOST_IDX) +#define BITS_P0HI11Q_HOST_IDX \ + (BIT_MASK_P0HI11Q_HOST_IDX << BIT_SHIFT_P0HI11Q_HOST_IDX) +#define BIT_CLEAR_P0HI11Q_HOST_IDX(x) ((x) & (~BITS_P0HI11Q_HOST_IDX)) +#define BIT_GET_P0HI11Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_HOST_IDX) & BIT_MASK_P0HI11Q_HOST_IDX) +#define BIT_SET_P0HI11Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI11Q_HOST_IDX(x) | BIT_P0HI11Q_HOST_IDX(v)) + +/* 2 REG_P0HI12Q_TXBD_IDX (Offset 0x1340) */ + +#define BIT_SHIFT_P0HI12Q_HW_IDX 16 +#define BIT_MASK_P0HI12Q_HW_IDX 0xfff +#define BIT_P0HI12Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI12Q_HW_IDX) << BIT_SHIFT_P0HI12Q_HW_IDX) +#define BITS_P0HI12Q_HW_IDX \ + (BIT_MASK_P0HI12Q_HW_IDX << BIT_SHIFT_P0HI12Q_HW_IDX) +#define BIT_CLEAR_P0HI12Q_HW_IDX(x) ((x) & (~BITS_P0HI12Q_HW_IDX)) +#define BIT_GET_P0HI12Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_HW_IDX) & BIT_MASK_P0HI12Q_HW_IDX) +#define BIT_SET_P0HI12Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI12Q_HW_IDX(x) | BIT_P0HI12Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI12Q_HOST_IDX 0 +#define BIT_MASK_P0HI12Q_HOST_IDX 0xfff +#define BIT_P0HI12Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI12Q_HOST_IDX) << BIT_SHIFT_P0HI12Q_HOST_IDX) +#define BITS_P0HI12Q_HOST_IDX \ + (BIT_MASK_P0HI12Q_HOST_IDX << BIT_SHIFT_P0HI12Q_HOST_IDX) +#define BIT_CLEAR_P0HI12Q_HOST_IDX(x) ((x) & (~BITS_P0HI12Q_HOST_IDX)) +#define BIT_GET_P0HI12Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_HOST_IDX) & BIT_MASK_P0HI12Q_HOST_IDX) +#define BIT_SET_P0HI12Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI12Q_HOST_IDX(x) | BIT_P0HI12Q_HOST_IDX(v)) + +/* 2 REG_P0HI13Q_TXBD_IDX (Offset 0x1344) */ + +#define BIT_SHIFT_P0HI13Q_HW_IDX 16 +#define BIT_MASK_P0HI13Q_HW_IDX 0xfff +#define BIT_P0HI13Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI13Q_HW_IDX) << BIT_SHIFT_P0HI13Q_HW_IDX) +#define BITS_P0HI13Q_HW_IDX \ + (BIT_MASK_P0HI13Q_HW_IDX << BIT_SHIFT_P0HI13Q_HW_IDX) +#define BIT_CLEAR_P0HI13Q_HW_IDX(x) ((x) & (~BITS_P0HI13Q_HW_IDX)) +#define BIT_GET_P0HI13Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_HW_IDX) & BIT_MASK_P0HI13Q_HW_IDX) +#define BIT_SET_P0HI13Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI13Q_HW_IDX(x) | BIT_P0HI13Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI13Q_HOST_IDX 0 +#define BIT_MASK_P0HI13Q_HOST_IDX 0xfff +#define BIT_P0HI13Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI13Q_HOST_IDX) << BIT_SHIFT_P0HI13Q_HOST_IDX) +#define BITS_P0HI13Q_HOST_IDX \ + (BIT_MASK_P0HI13Q_HOST_IDX << BIT_SHIFT_P0HI13Q_HOST_IDX) +#define BIT_CLEAR_P0HI13Q_HOST_IDX(x) ((x) & (~BITS_P0HI13Q_HOST_IDX)) +#define BIT_GET_P0HI13Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_HOST_IDX) & BIT_MASK_P0HI13Q_HOST_IDX) +#define BIT_SET_P0HI13Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI13Q_HOST_IDX(x) | BIT_P0HI13Q_HOST_IDX(v)) + +/* 2 REG_P0HI14Q_TXBD_IDX (Offset 0x1348) */ + +#define BIT_SHIFT_P0HI14Q_HW_IDX 16 +#define BIT_MASK_P0HI14Q_HW_IDX 0xfff +#define BIT_P0HI14Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI14Q_HW_IDX) << BIT_SHIFT_P0HI14Q_HW_IDX) +#define BITS_P0HI14Q_HW_IDX \ + (BIT_MASK_P0HI14Q_HW_IDX << BIT_SHIFT_P0HI14Q_HW_IDX) +#define BIT_CLEAR_P0HI14Q_HW_IDX(x) ((x) & (~BITS_P0HI14Q_HW_IDX)) +#define BIT_GET_P0HI14Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_HW_IDX) & BIT_MASK_P0HI14Q_HW_IDX) +#define BIT_SET_P0HI14Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI14Q_HW_IDX(x) | BIT_P0HI14Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI14Q_HOST_IDX 0 +#define BIT_MASK_P0HI14Q_HOST_IDX 0xfff +#define BIT_P0HI14Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI14Q_HOST_IDX) << BIT_SHIFT_P0HI14Q_HOST_IDX) +#define BITS_P0HI14Q_HOST_IDX \ + (BIT_MASK_P0HI14Q_HOST_IDX << BIT_SHIFT_P0HI14Q_HOST_IDX) +#define BIT_CLEAR_P0HI14Q_HOST_IDX(x) ((x) & (~BITS_P0HI14Q_HOST_IDX)) +#define BIT_GET_P0HI14Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_HOST_IDX) & BIT_MASK_P0HI14Q_HOST_IDX) +#define BIT_SET_P0HI14Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI14Q_HOST_IDX(x) | BIT_P0HI14Q_HOST_IDX(v)) + +/* 2 REG_P0HI15Q_TXBD_IDX (Offset 0x134C) */ + +#define BIT_SHIFT_P0HI15Q_HW_IDX 16 +#define BIT_MASK_P0HI15Q_HW_IDX 0xfff +#define BIT_P0HI15Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI15Q_HW_IDX) << BIT_SHIFT_P0HI15Q_HW_IDX) +#define BITS_P0HI15Q_HW_IDX \ + (BIT_MASK_P0HI15Q_HW_IDX << BIT_SHIFT_P0HI15Q_HW_IDX) +#define BIT_CLEAR_P0HI15Q_HW_IDX(x) ((x) & (~BITS_P0HI15Q_HW_IDX)) +#define BIT_GET_P0HI15Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_HW_IDX) & BIT_MASK_P0HI15Q_HW_IDX) +#define BIT_SET_P0HI15Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI15Q_HW_IDX(x) | BIT_P0HI15Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI15Q_HOST_IDX 0 +#define BIT_MASK_P0HI15Q_HOST_IDX 0xfff +#define BIT_P0HI15Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI15Q_HOST_IDX) << BIT_SHIFT_P0HI15Q_HOST_IDX) +#define BITS_P0HI15Q_HOST_IDX \ + (BIT_MASK_P0HI15Q_HOST_IDX << BIT_SHIFT_P0HI15Q_HOST_IDX) +#define BIT_CLEAR_P0HI15Q_HOST_IDX(x) ((x) & (~BITS_P0HI15Q_HOST_IDX)) +#define BIT_GET_P0HI15Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_HOST_IDX) & BIT_MASK_P0HI15Q_HOST_IDX) +#define BIT_SET_P0HI15Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI15Q_HOST_IDX(x) | BIT_P0HI15Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ +#define BIT_AXI_RXDMA_TIMEOUT_RE BIT(21) +#define BIT_AXI_TXDMA_TIMEOUT_RE BIT(20) +#define BIT_AXI_DECERR_W_RE BIT(19) +#define BIT_AXI_DECERR_R_RE BIT(18) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822B_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ -#define BIT_FS_CLI3_TX_NULL1_INT BIT(7) +#define BIT_CHANGE_PCIE_SPEED BIT(18) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ +#define BIT_AXI_SLVERR_W_RE BIT(17) +#define BIT_AXI_SLVERR_R_RE BIT(16) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT4_TX_NULL0_DONE_INT BIT(6) +#if (HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ +#define BIT_SHIFT_GEN1_GEN2 16 +#define BIT_MASK_GEN1_GEN2 0x3 +#define BIT_GEN1_GEN2(x) (((x) & BIT_MASK_GEN1_GEN2) << BIT_SHIFT_GEN1_GEN2) +#define BITS_GEN1_GEN2 (BIT_MASK_GEN1_GEN2 << BIT_SHIFT_GEN1_GEN2) +#define BIT_CLEAR_GEN1_GEN2(x) ((x) & (~BITS_GEN1_GEN2)) +#define BIT_GET_GEN1_GEN2(x) (((x) >> BIT_SHIFT_GEN1_GEN2) & BIT_MASK_GEN1_GEN2) +#define BIT_SET_GEN1_GEN2(x, v) (BIT_CLEAR_GEN1_GEN2(x) | BIT_GEN1_GEN2(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ -#define BIT_FS_CLI3_TX_NULL0_INT BIT(6) +#define BIT_AXI_RXDMA_TIMEOUT_IE BIT(13) +#define BIT_AXI_TXDMA_TIMEOUT_IE BIT(12) +#define BIT_AXI_DECERR_W_IE BIT(11) +#define BIT_AXI_DECERR_R_IE BIT(10) +#define BIT_AXI_SLVERR_W_IE BIT(9) +#define BIT_AXI_SLVERR_R_IE BIT(8) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_SHIFT_RXDMA_ERROR_COUNTER 8 +#define BIT_MASK_RXDMA_ERROR_COUNTER 0xff +#define BIT_RXDMA_ERROR_COUNTER(x) \ + (((x) & BIT_MASK_RXDMA_ERROR_COUNTER) << BIT_SHIFT_RXDMA_ERROR_COUNTER) +#define BITS_RXDMA_ERROR_COUNTER \ + (BIT_MASK_RXDMA_ERROR_COUNTER << BIT_SHIFT_RXDMA_ERROR_COUNTER) +#define BIT_CLEAR_RXDMA_ERROR_COUNTER(x) ((x) & (~BITS_RXDMA_ERROR_COUNTER)) +#define BIT_GET_RXDMA_ERROR_COUNTER(x) \ + (((x) >> BIT_SHIFT_RXDMA_ERROR_COUNTER) & BIT_MASK_RXDMA_ERROR_COUNTER) +#define BIT_SET_RXDMA_ERROR_COUNTER(x, v) \ + (BIT_CLEAR_RXDMA_ERROR_COUNTER(x) | BIT_RXDMA_ERROR_COUNTER(v)) -#define BIT_PORT3_TX_NULL1_DONE_INT BIT(5) +#define BIT_TXDMA_ERROR_HANDLE_STATUS BIT(7) +#define BIT_TXDMA_ERROR_PULSE BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ +#define BIT_AXI_RXDMA_TIMEOUT_FLAG BIT(5) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI2_TX_NULL1_INT BIT(5) +#if (HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ +#define BIT_TXDMA_STUCK_ERROR_HANDLE_ENABLE BIT(5) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ -#define BIT_PORT3_TX_NULL0_DONE_INT BIT(4) +#define BIT_AXI_TXDMA_TIMEOUT_FLAG BIT(4) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ +#define BIT_TXDMA_RETURN_ERROR_ENABLE BIT(4) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI2_TX_NULL0_INT BIT(4) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ +#define BIT_AXI_DECERR_W_FLAG BIT(3) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8822B_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ -#define BIT_PORT2_TX_NULL1_DONE_INT BIT(3) +#define BIT_RXDMA_ERROR_HANDLE_STATUS BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ +#define BIT_AXI_DECERR_R_FLAG BIT(2) +#define BIT_AXI_SLVERR_W_FLAG BIT(1) +#define BIT_AXI_SLVERR_R_FLAG BIT(0) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8822B_SUPPORT) + +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ -#define BIT_FS_CLI1_TX_NULL1_INT BIT(3) +#define BIT_SHIFT_AUTO_HANG_RELEASE 0 +#define BIT_MASK_AUTO_HANG_RELEASE 0x7 +#define BIT_AUTO_HANG_RELEASE(x) \ + (((x) & BIT_MASK_AUTO_HANG_RELEASE) << BIT_SHIFT_AUTO_HANG_RELEASE) +#define BITS_AUTO_HANG_RELEASE \ + (BIT_MASK_AUTO_HANG_RELEASE << BIT_SHIFT_AUTO_HANG_RELEASE) +#define BIT_CLEAR_AUTO_HANG_RELEASE(x) ((x) & (~BITS_AUTO_HANG_RELEASE)) +#define BIT_GET_AUTO_HANG_RELEASE(x) \ + (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE) & BIT_MASK_AUTO_HANG_RELEASE) +#define BIT_SET_AUTO_HANG_RELEASE(x, v) \ + (BIT_CLEAR_AUTO_HANG_RELEASE(x) | BIT_AUTO_HANG_RELEASE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_AXI_EXCEPT_TIME (Offset 0x1354) */ +#define BIT_SHIFT_AXI_RECOVERY_TIME 24 +#define BIT_MASK_AXI_RECOVERY_TIME 0xff +#define BIT_AXI_RECOVERY_TIME(x) \ + (((x) & BIT_MASK_AXI_RECOVERY_TIME) << BIT_SHIFT_AXI_RECOVERY_TIME) +#define BITS_AXI_RECOVERY_TIME \ + (BIT_MASK_AXI_RECOVERY_TIME << BIT_SHIFT_AXI_RECOVERY_TIME) +#define BIT_CLEAR_AXI_RECOVERY_TIME(x) ((x) & (~BITS_AXI_RECOVERY_TIME)) +#define BIT_GET_AXI_RECOVERY_TIME(x) \ + (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME) & BIT_MASK_AXI_RECOVERY_TIME) +#define BIT_SET_AXI_RECOVERY_TIME(x, v) \ + (BIT_CLEAR_AXI_RECOVERY_TIME(x) | BIT_AXI_RECOVERY_TIME(v)) + +#define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL 12 +#define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL 0xfff +#define BIT_AXI_RXDMA_TIMEOUT_VAL(x) \ + (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL) \ + << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) +#define BITS_AXI_RXDMA_TIMEOUT_VAL \ + (BIT_MASK_AXI_RXDMA_TIMEOUT_VAL << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) +#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL(x) ((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL)) +#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL(x) \ + (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) & \ + BIT_MASK_AXI_RXDMA_TIMEOUT_VAL) +#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL(x, v) \ + (BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL(x) | BIT_AXI_RXDMA_TIMEOUT_VAL(v)) + +#define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL 0 +#define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL 0xfff +#define BIT_AXI_TXDMA_TIMEOUT_VAL(x) \ + (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL) \ + << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) +#define BITS_AXI_TXDMA_TIMEOUT_VAL \ + (BIT_MASK_AXI_TXDMA_TIMEOUT_VAL << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) +#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL(x) ((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL)) +#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL(x) \ + (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) & \ + BIT_MASK_AXI_TXDMA_TIMEOUT_VAL) +#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL(x, v) \ + (BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL(x) | BIT_AXI_TXDMA_TIMEOUT_VAL(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DEBUG_STATE1 (Offset 0x1354) */ + +#define BIT_SHIFT_DEBUG_STATE1 0 +#define BIT_MASK_DEBUG_STATE1 0xffffffffL +#define BIT_DEBUG_STATE1(x) \ + (((x) & BIT_MASK_DEBUG_STATE1) << BIT_SHIFT_DEBUG_STATE1) +#define BITS_DEBUG_STATE1 (BIT_MASK_DEBUG_STATE1 << BIT_SHIFT_DEBUG_STATE1) +#define BIT_CLEAR_DEBUG_STATE1(x) ((x) & (~BITS_DEBUG_STATE1)) +#define BIT_GET_DEBUG_STATE1(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE1) & BIT_MASK_DEBUG_STATE1) +#define BIT_SET_DEBUG_STATE1(x, v) \ + (BIT_CLEAR_DEBUG_STATE1(x) | BIT_DEBUG_STATE1(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI8Q_TXBD_IDX (Offset 0x1358) */ + +#define BIT_SHIFT_HI8Q_HW_IDX 16 +#define BIT_MASK_HI8Q_HW_IDX 0xfff +#define BIT_HI8Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI8Q_HW_IDX) << BIT_SHIFT_HI8Q_HW_IDX) +#define BITS_HI8Q_HW_IDX (BIT_MASK_HI8Q_HW_IDX << BIT_SHIFT_HI8Q_HW_IDX) +#define BIT_CLEAR_HI8Q_HW_IDX(x) ((x) & (~BITS_HI8Q_HW_IDX)) +#define BIT_GET_HI8Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI8Q_HW_IDX) & BIT_MASK_HI8Q_HW_IDX) +#define BIT_SET_HI8Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI8Q_HW_IDX(x) | BIT_HI8Q_HW_IDX(v)) + +#define BIT_SHIFT_HI8Q_HOST_IDX 0 +#define BIT_MASK_HI8Q_HOST_IDX 0xfff +#define BIT_HI8Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI8Q_HOST_IDX) << BIT_SHIFT_HI8Q_HOST_IDX) +#define BITS_HI8Q_HOST_IDX (BIT_MASK_HI8Q_HOST_IDX << BIT_SHIFT_HI8Q_HOST_IDX) +#define BIT_CLEAR_HI8Q_HOST_IDX(x) ((x) & (~BITS_HI8Q_HOST_IDX)) +#define BIT_GET_HI8Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI8Q_HOST_IDX) & BIT_MASK_HI8Q_HOST_IDX) +#define BIT_SET_HI8Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI8Q_HOST_IDX(x) | BIT_HI8Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DEBUG_STATE2 (Offset 0x1358) */ + +#define BIT_SHIFT_DEBUG_STATE2 0 +#define BIT_MASK_DEBUG_STATE2 0xffffffffL +#define BIT_DEBUG_STATE2(x) \ + (((x) & BIT_MASK_DEBUG_STATE2) << BIT_SHIFT_DEBUG_STATE2) +#define BITS_DEBUG_STATE2 (BIT_MASK_DEBUG_STATE2 << BIT_SHIFT_DEBUG_STATE2) +#define BIT_CLEAR_DEBUG_STATE2(x) ((x) & (~BITS_DEBUG_STATE2)) +#define BIT_GET_DEBUG_STATE2(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE2) & BIT_MASK_DEBUG_STATE2) +#define BIT_SET_DEBUG_STATE2(x, v) \ + (BIT_CLEAR_DEBUG_STATE2(x) | BIT_DEBUG_STATE2(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI9Q_TXBD_IDX (Offset 0x135C) */ + +#define BIT_SHIFT_HI9Q_HW_IDX 16 +#define BIT_MASK_HI9Q_HW_IDX 0xfff +#define BIT_HI9Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI9Q_HW_IDX) << BIT_SHIFT_HI9Q_HW_IDX) +#define BITS_HI9Q_HW_IDX (BIT_MASK_HI9Q_HW_IDX << BIT_SHIFT_HI9Q_HW_IDX) +#define BIT_CLEAR_HI9Q_HW_IDX(x) ((x) & (~BITS_HI9Q_HW_IDX)) +#define BIT_GET_HI9Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI9Q_HW_IDX) & BIT_MASK_HI9Q_HW_IDX) +#define BIT_SET_HI9Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI9Q_HW_IDX(x) | BIT_HI9Q_HW_IDX(v)) + +#define BIT_SHIFT_HI9Q_HOST_IDX 0 +#define BIT_MASK_HI9Q_HOST_IDX 0xfff +#define BIT_HI9Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI9Q_HOST_IDX) << BIT_SHIFT_HI9Q_HOST_IDX) +#define BITS_HI9Q_HOST_IDX (BIT_MASK_HI9Q_HOST_IDX << BIT_SHIFT_HI9Q_HOST_IDX) +#define BIT_CLEAR_HI9Q_HOST_IDX(x) ((x) & (~BITS_HI9Q_HOST_IDX)) +#define BIT_GET_HI9Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI9Q_HOST_IDX) & BIT_MASK_HI9Q_HOST_IDX) +#define BIT_SET_HI9Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI9Q_HOST_IDX(x) | BIT_HI9Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DEBUG_STATE3 (Offset 0x135C) */ + +#define BIT_SHIFT_DEBUG_STATE3 0 +#define BIT_MASK_DEBUG_STATE3 0xffffffffL +#define BIT_DEBUG_STATE3(x) \ + (((x) & BIT_MASK_DEBUG_STATE3) << BIT_SHIFT_DEBUG_STATE3) +#define BITS_DEBUG_STATE3 (BIT_MASK_DEBUG_STATE3 << BIT_SHIFT_DEBUG_STATE3) +#define BIT_CLEAR_DEBUG_STATE3(x) ((x) & (~BITS_DEBUG_STATE3)) +#define BIT_GET_DEBUG_STATE3(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE3) & BIT_MASK_DEBUG_STATE3) +#define BIT_SET_DEBUG_STATE3(x, v) \ + (BIT_CLEAR_DEBUG_STATE3(x) | BIT_DEBUG_STATE3(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI10Q_TXBD_IDX (Offset 0x1360) */ + +#define BIT_SHIFT_HI10Q_HW_IDX 16 +#define BIT_MASK_HI10Q_HW_IDX 0xfff +#define BIT_HI10Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI10Q_HW_IDX) << BIT_SHIFT_HI10Q_HW_IDX) +#define BITS_HI10Q_HW_IDX (BIT_MASK_HI10Q_HW_IDX << BIT_SHIFT_HI10Q_HW_IDX) +#define BIT_CLEAR_HI10Q_HW_IDX(x) ((x) & (~BITS_HI10Q_HW_IDX)) +#define BIT_GET_HI10Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI10Q_HW_IDX) & BIT_MASK_HI10Q_HW_IDX) +#define BIT_SET_HI10Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI10Q_HW_IDX(x) | BIT_HI10Q_HW_IDX(v)) + +#define BIT_SHIFT_HI10Q_HOST_IDX 0 +#define BIT_MASK_HI10Q_HOST_IDX 0xfff +#define BIT_HI10Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI10Q_HOST_IDX) << BIT_SHIFT_HI10Q_HOST_IDX) +#define BITS_HI10Q_HOST_IDX \ + (BIT_MASK_HI10Q_HOST_IDX << BIT_SHIFT_HI10Q_HOST_IDX) +#define BIT_CLEAR_HI10Q_HOST_IDX(x) ((x) & (~BITS_HI10Q_HOST_IDX)) +#define BIT_GET_HI10Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI10Q_HOST_IDX) & BIT_MASK_HI10Q_HOST_IDX) +#define BIT_SET_HI10Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI10Q_HOST_IDX(x) | BIT_HI10Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH5_TXBD_DESA_L (Offset 0x1360) */ + +#define BIT_SHIFT_ACH5_TXBD_DESA_L 0 +#define BIT_MASK_ACH5_TXBD_DESA_L 0xffffffffL +#define BIT_ACH5_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH5_TXBD_DESA_L) << BIT_SHIFT_ACH5_TXBD_DESA_L) +#define BITS_ACH5_TXBD_DESA_L \ + (BIT_MASK_ACH5_TXBD_DESA_L << BIT_SHIFT_ACH5_TXBD_DESA_L) +#define BIT_CLEAR_ACH5_TXBD_DESA_L(x) ((x) & (~BITS_ACH5_TXBD_DESA_L)) +#define BIT_GET_ACH5_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_L) & BIT_MASK_ACH5_TXBD_DESA_L) +#define BIT_SET_ACH5_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH5_TXBD_DESA_L(x) | BIT_ACH5_TXBD_DESA_L(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI11Q_TXBD_IDX (Offset 0x1364) */ + +#define BIT_SHIFT_HI11Q_HW_IDX 16 +#define BIT_MASK_HI11Q_HW_IDX 0xfff +#define BIT_HI11Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI11Q_HW_IDX) << BIT_SHIFT_HI11Q_HW_IDX) +#define BITS_HI11Q_HW_IDX (BIT_MASK_HI11Q_HW_IDX << BIT_SHIFT_HI11Q_HW_IDX) +#define BIT_CLEAR_HI11Q_HW_IDX(x) ((x) & (~BITS_HI11Q_HW_IDX)) +#define BIT_GET_HI11Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI11Q_HW_IDX) & BIT_MASK_HI11Q_HW_IDX) +#define BIT_SET_HI11Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI11Q_HW_IDX(x) | BIT_HI11Q_HW_IDX(v)) + +#define BIT_SHIFT_HI11Q_HOST_IDX 0 +#define BIT_MASK_HI11Q_HOST_IDX 0xfff +#define BIT_HI11Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI11Q_HOST_IDX) << BIT_SHIFT_HI11Q_HOST_IDX) +#define BITS_HI11Q_HOST_IDX \ + (BIT_MASK_HI11Q_HOST_IDX << BIT_SHIFT_HI11Q_HOST_IDX) +#define BIT_CLEAR_HI11Q_HOST_IDX(x) ((x) & (~BITS_HI11Q_HOST_IDX)) +#define BIT_GET_HI11Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI11Q_HOST_IDX) & BIT_MASK_HI11Q_HOST_IDX) +#define BIT_SET_HI11Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI11Q_HOST_IDX(x) | BIT_HI11Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH5_TXBD_DESA_H (Offset 0x1364) */ + +#define BIT_SHIFT_ACH5_TXBD_DESA_H 0 +#define BIT_MASK_ACH5_TXBD_DESA_H 0xffffffffL +#define BIT_ACH5_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH5_TXBD_DESA_H) << BIT_SHIFT_ACH5_TXBD_DESA_H) +#define BITS_ACH5_TXBD_DESA_H \ + (BIT_MASK_ACH5_TXBD_DESA_H << BIT_SHIFT_ACH5_TXBD_DESA_H) +#define BIT_CLEAR_ACH5_TXBD_DESA_H(x) ((x) & (~BITS_ACH5_TXBD_DESA_H)) +#define BIT_GET_ACH5_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_H) & BIT_MASK_ACH5_TXBD_DESA_H) +#define BIT_SET_ACH5_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH5_TXBD_DESA_H(x) | BIT_ACH5_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI12Q_TXBD_IDX (Offset 0x1368) */ + +#define BIT_SHIFT_HI12Q_HW_IDX 16 +#define BIT_MASK_HI12Q_HW_IDX 0xfff +#define BIT_HI12Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI12Q_HW_IDX) << BIT_SHIFT_HI12Q_HW_IDX) +#define BITS_HI12Q_HW_IDX (BIT_MASK_HI12Q_HW_IDX << BIT_SHIFT_HI12Q_HW_IDX) +#define BIT_CLEAR_HI12Q_HW_IDX(x) ((x) & (~BITS_HI12Q_HW_IDX)) +#define BIT_GET_HI12Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI12Q_HW_IDX) & BIT_MASK_HI12Q_HW_IDX) +#define BIT_SET_HI12Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI12Q_HW_IDX(x) | BIT_HI12Q_HW_IDX(v)) + +#define BIT_SHIFT_HI12Q_HOST_IDX 0 +#define BIT_MASK_HI12Q_HOST_IDX 0xfff +#define BIT_HI12Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI12Q_HOST_IDX) << BIT_SHIFT_HI12Q_HOST_IDX) +#define BITS_HI12Q_HOST_IDX \ + (BIT_MASK_HI12Q_HOST_IDX << BIT_SHIFT_HI12Q_HOST_IDX) +#define BIT_CLEAR_HI12Q_HOST_IDX(x) ((x) & (~BITS_HI12Q_HOST_IDX)) +#define BIT_GET_HI12Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI12Q_HOST_IDX) & BIT_MASK_HI12Q_HOST_IDX) +#define BIT_SET_HI12Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI12Q_HOST_IDX(x) | BIT_HI12Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH6_TXBD_DESA_L (Offset 0x1368) */ + +#define BIT_SHIFT_ACH6_TXBD_DESA_L 0 +#define BIT_MASK_ACH6_TXBD_DESA_L 0xffffffffL +#define BIT_ACH6_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH6_TXBD_DESA_L) << BIT_SHIFT_ACH6_TXBD_DESA_L) +#define BITS_ACH6_TXBD_DESA_L \ + (BIT_MASK_ACH6_TXBD_DESA_L << BIT_SHIFT_ACH6_TXBD_DESA_L) +#define BIT_CLEAR_ACH6_TXBD_DESA_L(x) ((x) & (~BITS_ACH6_TXBD_DESA_L)) +#define BIT_GET_ACH6_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_L) & BIT_MASK_ACH6_TXBD_DESA_L) +#define BIT_SET_ACH6_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH6_TXBD_DESA_L(x) | BIT_ACH6_TXBD_DESA_L(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI13Q_TXBD_IDX (Offset 0x136C) */ + +#define BIT_SHIFT_HI13Q_HW_IDX 16 +#define BIT_MASK_HI13Q_HW_IDX 0xfff +#define BIT_HI13Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI13Q_HW_IDX) << BIT_SHIFT_HI13Q_HW_IDX) +#define BITS_HI13Q_HW_IDX (BIT_MASK_HI13Q_HW_IDX << BIT_SHIFT_HI13Q_HW_IDX) +#define BIT_CLEAR_HI13Q_HW_IDX(x) ((x) & (~BITS_HI13Q_HW_IDX)) +#define BIT_GET_HI13Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI13Q_HW_IDX) & BIT_MASK_HI13Q_HW_IDX) +#define BIT_SET_HI13Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI13Q_HW_IDX(x) | BIT_HI13Q_HW_IDX(v)) + +#define BIT_SHIFT_HI13Q_HOST_IDX 0 +#define BIT_MASK_HI13Q_HOST_IDX 0xfff +#define BIT_HI13Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI13Q_HOST_IDX) << BIT_SHIFT_HI13Q_HOST_IDX) +#define BITS_HI13Q_HOST_IDX \ + (BIT_MASK_HI13Q_HOST_IDX << BIT_SHIFT_HI13Q_HOST_IDX) +#define BIT_CLEAR_HI13Q_HOST_IDX(x) ((x) & (~BITS_HI13Q_HOST_IDX)) +#define BIT_GET_HI13Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI13Q_HOST_IDX) & BIT_MASK_HI13Q_HOST_IDX) +#define BIT_SET_HI13Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI13Q_HOST_IDX(x) | BIT_HI13Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH6_TXBD_DESA_H (Offset 0x136C) */ + +#define BIT_SHIFT_ACH6_TXBD_DESA_H 0 +#define BIT_MASK_ACH6_TXBD_DESA_H 0xffffffffL +#define BIT_ACH6_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH6_TXBD_DESA_H) << BIT_SHIFT_ACH6_TXBD_DESA_H) +#define BITS_ACH6_TXBD_DESA_H \ + (BIT_MASK_ACH6_TXBD_DESA_H << BIT_SHIFT_ACH6_TXBD_DESA_H) +#define BIT_CLEAR_ACH6_TXBD_DESA_H(x) ((x) & (~BITS_ACH6_TXBD_DESA_H)) +#define BIT_GET_ACH6_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_H) & BIT_MASK_ACH6_TXBD_DESA_H) +#define BIT_SET_ACH6_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH6_TXBD_DESA_H(x) | BIT_ACH6_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI14Q_TXBD_IDX (Offset 0x1370) */ + +#define BIT_SHIFT_HI14Q_HW_IDX 16 +#define BIT_MASK_HI14Q_HW_IDX 0xfff +#define BIT_HI14Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI14Q_HW_IDX) << BIT_SHIFT_HI14Q_HW_IDX) +#define BITS_HI14Q_HW_IDX (BIT_MASK_HI14Q_HW_IDX << BIT_SHIFT_HI14Q_HW_IDX) +#define BIT_CLEAR_HI14Q_HW_IDX(x) ((x) & (~BITS_HI14Q_HW_IDX)) +#define BIT_GET_HI14Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI14Q_HW_IDX) & BIT_MASK_HI14Q_HW_IDX) +#define BIT_SET_HI14Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI14Q_HW_IDX(x) | BIT_HI14Q_HW_IDX(v)) + +#define BIT_SHIFT_HI14Q_HOST_IDX 0 +#define BIT_MASK_HI14Q_HOST_IDX 0xfff +#define BIT_HI14Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI14Q_HOST_IDX) << BIT_SHIFT_HI14Q_HOST_IDX) +#define BITS_HI14Q_HOST_IDX \ + (BIT_MASK_HI14Q_HOST_IDX << BIT_SHIFT_HI14Q_HOST_IDX) +#define BIT_CLEAR_HI14Q_HOST_IDX(x) ((x) & (~BITS_HI14Q_HOST_IDX)) +#define BIT_GET_HI14Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI14Q_HOST_IDX) & BIT_MASK_HI14Q_HOST_IDX) +#define BIT_SET_HI14Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI14Q_HOST_IDX(x) | BIT_HI14Q_HOST_IDX(v)) + +#endif -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#if (HALMAC_8814B_SUPPORT) -#define BIT_PORT2_TX_NULL0_DONE_INT BIT(2) +/* 2 REG_ACH7_TXBD_DESA_L (Offset 0x1370) */ -#endif +#define BIT_SHIFT_ACH7_TXBD_DESA_L 0 +#define BIT_MASK_ACH7_TXBD_DESA_L 0xffffffffL +#define BIT_ACH7_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH7_TXBD_DESA_L) << BIT_SHIFT_ACH7_TXBD_DESA_L) +#define BITS_ACH7_TXBD_DESA_L \ + (BIT_MASK_ACH7_TXBD_DESA_L << BIT_SHIFT_ACH7_TXBD_DESA_L) +#define BIT_CLEAR_ACH7_TXBD_DESA_L(x) ((x) & (~BITS_ACH7_TXBD_DESA_L)) +#define BIT_GET_ACH7_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_L) & BIT_MASK_ACH7_TXBD_DESA_L) +#define BIT_SET_ACH7_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH7_TXBD_DESA_L(x) | BIT_ACH7_TXBD_DESA_L(v)) +#endif -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8198F_SUPPORT) +/* 2 REG_HI15Q_TXBD_IDX (Offset 0x1374) */ -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_SHIFT_HI15Q_HW_IDX 16 +#define BIT_MASK_HI15Q_HW_IDX 0xfff +#define BIT_HI15Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI15Q_HW_IDX) << BIT_SHIFT_HI15Q_HW_IDX) +#define BITS_HI15Q_HW_IDX (BIT_MASK_HI15Q_HW_IDX << BIT_SHIFT_HI15Q_HW_IDX) +#define BIT_CLEAR_HI15Q_HW_IDX(x) ((x) & (~BITS_HI15Q_HW_IDX)) +#define BIT_GET_HI15Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI15Q_HW_IDX) & BIT_MASK_HI15Q_HW_IDX) +#define BIT_SET_HI15Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI15Q_HW_IDX(x) | BIT_HI15Q_HW_IDX(v)) -#define BIT_FS_CLI1_TX_NULL0_INT BIT(2) +#define BIT_SHIFT_HI15Q_HOST_IDX 0 +#define BIT_MASK_HI15Q_HOST_IDX 0xfff +#define BIT_HI15Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI15Q_HOST_IDX) << BIT_SHIFT_HI15Q_HOST_IDX) +#define BITS_HI15Q_HOST_IDX \ + (BIT_MASK_HI15Q_HOST_IDX << BIT_SHIFT_HI15Q_HOST_IDX) +#define BIT_CLEAR_HI15Q_HOST_IDX(x) ((x) & (~BITS_HI15Q_HOST_IDX)) +#define BIT_GET_HI15Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI15Q_HOST_IDX) & BIT_MASK_HI15Q_HOST_IDX) +#define BIT_SET_HI15Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI15Q_HOST_IDX(x) | BIT_HI15Q_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ACH7_TXBD_DESA_H (Offset 0x1374) */ +#define BIT_SHIFT_ACH7_TXBD_DESA_H 0 +#define BIT_MASK_ACH7_TXBD_DESA_H 0xffffffffL +#define BIT_ACH7_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH7_TXBD_DESA_H) << BIT_SHIFT_ACH7_TXBD_DESA_H) +#define BITS_ACH7_TXBD_DESA_H \ + (BIT_MASK_ACH7_TXBD_DESA_H << BIT_SHIFT_ACH7_TXBD_DESA_H) +#define BIT_CLEAR_ACH7_TXBD_DESA_H(x) ((x) & (~BITS_ACH7_TXBD_DESA_H)) +#define BIT_GET_ACH7_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_H) & BIT_MASK_ACH7_TXBD_DESA_H) +#define BIT_SET_ACH7_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH7_TXBD_DESA_H(x) | BIT_ACH7_TXBD_DESA_H(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT1_TX_NULL1_DONE_INT BIT(1) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_HI8Q_TXBD_DESA (Offset 0x1378) */ +#define BIT_SHIFT_HI8Q_TXBD_DESA 0 +#define BIT_MASK_HI8Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI8Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI8Q_TXBD_DESA) << BIT_SHIFT_HI8Q_TXBD_DESA) +#define BITS_HI8Q_TXBD_DESA \ + (BIT_MASK_HI8Q_TXBD_DESA << BIT_SHIFT_HI8Q_TXBD_DESA) +#define BIT_CLEAR_HI8Q_TXBD_DESA(x) ((x) & (~BITS_HI8Q_TXBD_DESA)) +#define BIT_GET_HI8Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA) & BIT_MASK_HI8Q_TXBD_DESA) +#define BIT_SET_HI8Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI8Q_TXBD_DESA(x) | BIT_HI8Q_TXBD_DESA(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_ACH8_TXBD_DESA_L (Offset 0x1378) */ -#define BIT_FS_CLI0_TX_NULL1_INT BIT(1) +#define BIT_SHIFT_ACH8_TXBD_DESA_L 0 +#define BIT_MASK_ACH8_TXBD_DESA_L 0xffffffffL +#define BIT_ACH8_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH8_TXBD_DESA_L) << BIT_SHIFT_ACH8_TXBD_DESA_L) +#define BITS_ACH8_TXBD_DESA_L \ + (BIT_MASK_ACH8_TXBD_DESA_L << BIT_SHIFT_ACH8_TXBD_DESA_L) +#define BIT_CLEAR_ACH8_TXBD_DESA_L(x) ((x) & (~BITS_ACH8_TXBD_DESA_L)) +#define BIT_GET_ACH8_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_L) & BIT_MASK_ACH8_TXBD_DESA_L) +#define BIT_SET_ACH8_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH8_TXBD_DESA_L(x) | BIT_ACH8_TXBD_DESA_L(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_CHNL_DMA_CFG_V1 (Offset 0x137C) */ +#define BIT_TXHCI_EN_V1 BIT(26) +#define BIT_TXHCI_IDLE_V1 BIT(25) +#define BIT_DMA_PRI_EN_V1 BIT(24) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT1_TX_NULL0_DONE_INT BIT(0) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ACH8_TXBD_DESA_H (Offset 0x137C) */ +#define BIT_SHIFT_ACH8_TXBD_DESA_H 0 +#define BIT_MASK_ACH8_TXBD_DESA_H 0xffffffffL +#define BIT_ACH8_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH8_TXBD_DESA_H) << BIT_SHIFT_ACH8_TXBD_DESA_H) +#define BITS_ACH8_TXBD_DESA_H \ + (BIT_MASK_ACH8_TXBD_DESA_H << BIT_SHIFT_ACH8_TXBD_DESA_H) +#define BIT_CLEAR_ACH8_TXBD_DESA_H(x) ((x) & (~BITS_ACH8_TXBD_DESA_H)) +#define BIT_GET_ACH8_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_H) & BIT_MASK_ACH8_TXBD_DESA_H) +#define BIT_SET_ACH8_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH8_TXBD_DESA_H(x) | BIT_ACH8_TXBD_DESA_H(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_HI9Q_TXBD_DESA (Offset 0x1380) */ -#define BIT_FS_CLI0_TX_NULL0_INT BIT(0) +#define BIT_SHIFT_HI9Q_TXBD_DESA 0 +#define BIT_MASK_HI9Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI9Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI9Q_TXBD_DESA) << BIT_SHIFT_HI9Q_TXBD_DESA) +#define BITS_HI9Q_TXBD_DESA \ + (BIT_MASK_HI9Q_TXBD_DESA << BIT_SHIFT_HI9Q_TXBD_DESA) +#define BIT_CLEAR_HI9Q_TXBD_DESA(x) ((x) & (~BITS_HI9Q_TXBD_DESA)) +#define BIT_GET_HI9Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA) & BIT_MASK_HI9Q_TXBD_DESA) +#define BIT_SET_HI9Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI9Q_TXBD_DESA(x) | BIT_HI9Q_TXBD_DESA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ACH9_TXBD_DESA_L (Offset 0x1380) */ +#define BIT_SHIFT_ACH9_TXBD_DESA_L 0 +#define BIT_MASK_ACH9_TXBD_DESA_L 0xffffffffL +#define BIT_ACH9_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH9_TXBD_DESA_L) << BIT_SHIFT_ACH9_TXBD_DESA_L) +#define BITS_ACH9_TXBD_DESA_L \ + (BIT_MASK_ACH9_TXBD_DESA_L << BIT_SHIFT_ACH9_TXBD_DESA_L) +#define BIT_CLEAR_ACH9_TXBD_DESA_L(x) ((x) & (~BITS_ACH9_TXBD_DESA_L)) +#define BIT_GET_ACH9_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_L) & BIT_MASK_ACH9_TXBD_DESA_L) +#define BIT_SET_ACH9_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH9_TXBD_DESA_L(x) | BIT_ACH9_TXBD_DESA_L(v)) -/* 2 REG_MSG2 (Offset 0x11F0) */ +/* 2 REG_ACH9_TXBD_DESA_H (Offset 0x1384) */ +#define BIT_SHIFT_ACH9_TXBD_DESA_H 0 +#define BIT_MASK_ACH9_TXBD_DESA_H 0xffffffffL +#define BIT_ACH9_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH9_TXBD_DESA_H) << BIT_SHIFT_ACH9_TXBD_DESA_H) +#define BITS_ACH9_TXBD_DESA_H \ + (BIT_MASK_ACH9_TXBD_DESA_H << BIT_SHIFT_ACH9_TXBD_DESA_H) +#define BIT_CLEAR_ACH9_TXBD_DESA_H(x) ((x) & (~BITS_ACH9_TXBD_DESA_H)) +#define BIT_GET_ACH9_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_H) & BIT_MASK_ACH9_TXBD_DESA_H) +#define BIT_SET_ACH9_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH9_TXBD_DESA_H(x) | BIT_ACH9_TXBD_DESA_H(v)) -#define BIT_SHIFT_FW_MSG2 0 -#define BIT_MASK_FW_MSG2 0xffffffffL -#define BIT_FW_MSG2(x) (((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2) -#define BIT_GET_FW_MSG2(x) (((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_MSG3 (Offset 0x11F4) */ +/* 2 REG_HI10Q_TXBD_DESA (Offset 0x1388) */ +#define BIT_SHIFT_HI10Q_TXBD_DESA 0 +#define BIT_MASK_HI10Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI10Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI10Q_TXBD_DESA) << BIT_SHIFT_HI10Q_TXBD_DESA) +#define BITS_HI10Q_TXBD_DESA \ + (BIT_MASK_HI10Q_TXBD_DESA << BIT_SHIFT_HI10Q_TXBD_DESA) +#define BIT_CLEAR_HI10Q_TXBD_DESA(x) ((x) & (~BITS_HI10Q_TXBD_DESA)) +#define BIT_GET_HI10Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA) & BIT_MASK_HI10Q_TXBD_DESA) +#define BIT_SET_HI10Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI10Q_TXBD_DESA(x) | BIT_HI10Q_TXBD_DESA(v)) -#define BIT_SHIFT_FW_MSG3 0 -#define BIT_MASK_FW_MSG3 0xffffffffL -#define BIT_FW_MSG3(x) (((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3) -#define BIT_GET_FW_MSG3(x) (((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_MSG4 (Offset 0x11F8) */ +/* 2 REG_ACH10_TXBD_DESA_L (Offset 0x1388) */ +#define BIT_SHIFT_ACH10_TXBD_DESA_L 0 +#define BIT_MASK_ACH10_TXBD_DESA_L 0xffffffffL +#define BIT_ACH10_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH10_TXBD_DESA_L) << BIT_SHIFT_ACH10_TXBD_DESA_L) +#define BITS_ACH10_TXBD_DESA_L \ + (BIT_MASK_ACH10_TXBD_DESA_L << BIT_SHIFT_ACH10_TXBD_DESA_L) +#define BIT_CLEAR_ACH10_TXBD_DESA_L(x) ((x) & (~BITS_ACH10_TXBD_DESA_L)) +#define BIT_GET_ACH10_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_L) & BIT_MASK_ACH10_TXBD_DESA_L) +#define BIT_SET_ACH10_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH10_TXBD_DESA_L(x) | BIT_ACH10_TXBD_DESA_L(v)) + +/* 2 REG_ACH10_TXBD_DESA_H (Offset 0x138C) */ + +#define BIT_SHIFT_ACH10_TXBD_DESA_H 0 +#define BIT_MASK_ACH10_TXBD_DESA_H 0xffffffffL +#define BIT_ACH10_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH10_TXBD_DESA_H) << BIT_SHIFT_ACH10_TXBD_DESA_H) +#define BITS_ACH10_TXBD_DESA_H \ + (BIT_MASK_ACH10_TXBD_DESA_H << BIT_SHIFT_ACH10_TXBD_DESA_H) +#define BIT_CLEAR_ACH10_TXBD_DESA_H(x) ((x) & (~BITS_ACH10_TXBD_DESA_H)) +#define BIT_GET_ACH10_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_H) & BIT_MASK_ACH10_TXBD_DESA_H) +#define BIT_SET_ACH10_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH10_TXBD_DESA_H(x) | BIT_ACH10_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI11Q_TXBD_DESA (Offset 0x1390) */ + +#define BIT_SHIFT_HI11Q_TXBD_DESA 0 +#define BIT_MASK_HI11Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI11Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI11Q_TXBD_DESA) << BIT_SHIFT_HI11Q_TXBD_DESA) +#define BITS_HI11Q_TXBD_DESA \ + (BIT_MASK_HI11Q_TXBD_DESA << BIT_SHIFT_HI11Q_TXBD_DESA) +#define BIT_CLEAR_HI11Q_TXBD_DESA(x) ((x) & (~BITS_HI11Q_TXBD_DESA)) +#define BIT_GET_HI11Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA) & BIT_MASK_HI11Q_TXBD_DESA) +#define BIT_SET_HI11Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI11Q_TXBD_DESA(x) | BIT_HI11Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH11_TXBD_DESA_L (Offset 0x1390) */ + +#define BIT_SHIFT_ACH11_TXBD_DESA_L 0 +#define BIT_MASK_ACH11_TXBD_DESA_L 0xffffffffL +#define BIT_ACH11_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH11_TXBD_DESA_L) << BIT_SHIFT_ACH11_TXBD_DESA_L) +#define BITS_ACH11_TXBD_DESA_L \ + (BIT_MASK_ACH11_TXBD_DESA_L << BIT_SHIFT_ACH11_TXBD_DESA_L) +#define BIT_CLEAR_ACH11_TXBD_DESA_L(x) ((x) & (~BITS_ACH11_TXBD_DESA_L)) +#define BIT_GET_ACH11_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_L) & BIT_MASK_ACH11_TXBD_DESA_L) +#define BIT_SET_ACH11_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH11_TXBD_DESA_L(x) | BIT_ACH11_TXBD_DESA_L(v)) + +/* 2 REG_ACH11_TXBD_DESA_H (Offset 0x1394) */ + +#define BIT_SHIFT_ACH11_TXBD_DESA_H 0 +#define BIT_MASK_ACH11_TXBD_DESA_H 0xffffffffL +#define BIT_ACH11_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH11_TXBD_DESA_H) << BIT_SHIFT_ACH11_TXBD_DESA_H) +#define BITS_ACH11_TXBD_DESA_H \ + (BIT_MASK_ACH11_TXBD_DESA_H << BIT_SHIFT_ACH11_TXBD_DESA_H) +#define BIT_CLEAR_ACH11_TXBD_DESA_H(x) ((x) & (~BITS_ACH11_TXBD_DESA_H)) +#define BIT_GET_ACH11_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_H) & BIT_MASK_ACH11_TXBD_DESA_H) +#define BIT_SET_ACH11_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH11_TXBD_DESA_H(x) | BIT_ACH11_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI12Q_TXBD_DESA (Offset 0x1398) */ + +#define BIT_SHIFT_HI12Q_TXBD_DESA 0 +#define BIT_MASK_HI12Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI12Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI12Q_TXBD_DESA) << BIT_SHIFT_HI12Q_TXBD_DESA) +#define BITS_HI12Q_TXBD_DESA \ + (BIT_MASK_HI12Q_TXBD_DESA << BIT_SHIFT_HI12Q_TXBD_DESA) +#define BIT_CLEAR_HI12Q_TXBD_DESA(x) ((x) & (~BITS_HI12Q_TXBD_DESA)) +#define BIT_GET_HI12Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA) & BIT_MASK_HI12Q_TXBD_DESA) +#define BIT_SET_HI12Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI12Q_TXBD_DESA(x) | BIT_HI12Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH12_TXBD_DESA_L (Offset 0x1398) */ + +#define BIT_SHIFT_ACH12_TXBD_DESA_L 0 +#define BIT_MASK_ACH12_TXBD_DESA_L 0xffffffffL +#define BIT_ACH12_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH12_TXBD_DESA_L) << BIT_SHIFT_ACH12_TXBD_DESA_L) +#define BITS_ACH12_TXBD_DESA_L \ + (BIT_MASK_ACH12_TXBD_DESA_L << BIT_SHIFT_ACH12_TXBD_DESA_L) +#define BIT_CLEAR_ACH12_TXBD_DESA_L(x) ((x) & (~BITS_ACH12_TXBD_DESA_L)) +#define BIT_GET_ACH12_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_L) & BIT_MASK_ACH12_TXBD_DESA_L) +#define BIT_SET_ACH12_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH12_TXBD_DESA_L(x) | BIT_ACH12_TXBD_DESA_L(v)) + +/* 2 REG_ACH12_TXBD_DESA_H (Offset 0x139C) */ + +#define BIT_SHIFT_ACH12_TXBD_DESA_H 0 +#define BIT_MASK_ACH12_TXBD_DESA_H 0xffffffffL +#define BIT_ACH12_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH12_TXBD_DESA_H) << BIT_SHIFT_ACH12_TXBD_DESA_H) +#define BITS_ACH12_TXBD_DESA_H \ + (BIT_MASK_ACH12_TXBD_DESA_H << BIT_SHIFT_ACH12_TXBD_DESA_H) +#define BIT_CLEAR_ACH12_TXBD_DESA_H(x) ((x) & (~BITS_ACH12_TXBD_DESA_H)) +#define BIT_GET_ACH12_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_H) & BIT_MASK_ACH12_TXBD_DESA_H) +#define BIT_SET_ACH12_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH12_TXBD_DESA_H(x) | BIT_ACH12_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI13Q_TXBD_DESA (Offset 0x13A0) */ + +#define BIT_SHIFT_HI13Q_TXBD_DESA 0 +#define BIT_MASK_HI13Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI13Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI13Q_TXBD_DESA) << BIT_SHIFT_HI13Q_TXBD_DESA) +#define BITS_HI13Q_TXBD_DESA \ + (BIT_MASK_HI13Q_TXBD_DESA << BIT_SHIFT_HI13Q_TXBD_DESA) +#define BIT_CLEAR_HI13Q_TXBD_DESA(x) ((x) & (~BITS_HI13Q_TXBD_DESA)) +#define BIT_GET_HI13Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA) & BIT_MASK_HI13Q_TXBD_DESA) +#define BIT_SET_HI13Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI13Q_TXBD_DESA(x) | BIT_HI13Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH13_TXBD_DESA_L (Offset 0x13A0) */ + +#define BIT_SHIFT_ACH13_TXBD_DESA_L 0 +#define BIT_MASK_ACH13_TXBD_DESA_L 0xffffffffL +#define BIT_ACH13_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH13_TXBD_DESA_L) << BIT_SHIFT_ACH13_TXBD_DESA_L) +#define BITS_ACH13_TXBD_DESA_L \ + (BIT_MASK_ACH13_TXBD_DESA_L << BIT_SHIFT_ACH13_TXBD_DESA_L) +#define BIT_CLEAR_ACH13_TXBD_DESA_L(x) ((x) & (~BITS_ACH13_TXBD_DESA_L)) +#define BIT_GET_ACH13_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_L) & BIT_MASK_ACH13_TXBD_DESA_L) +#define BIT_SET_ACH13_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH13_TXBD_DESA_L(x) | BIT_ACH13_TXBD_DESA_L(v)) + +/* 2 REG_ACH13_TXBD_DESA_H (Offset 0x13A4) */ + +#define BIT_SHIFT_ACH13_TXBD_DESA_H 0 +#define BIT_MASK_ACH13_TXBD_DESA_H 0xffffffffL +#define BIT_ACH13_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH13_TXBD_DESA_H) << BIT_SHIFT_ACH13_TXBD_DESA_H) +#define BITS_ACH13_TXBD_DESA_H \ + (BIT_MASK_ACH13_TXBD_DESA_H << BIT_SHIFT_ACH13_TXBD_DESA_H) +#define BIT_CLEAR_ACH13_TXBD_DESA_H(x) ((x) & (~BITS_ACH13_TXBD_DESA_H)) +#define BIT_GET_ACH13_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_H) & BIT_MASK_ACH13_TXBD_DESA_H) +#define BIT_SET_ACH13_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH13_TXBD_DESA_H(x) | BIT_ACH13_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI14Q_TXBD_DESA (Offset 0x13A8) */ + +#define BIT_SHIFT_HI14Q_TXBD_DESA 0 +#define BIT_MASK_HI14Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI14Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI14Q_TXBD_DESA) << BIT_SHIFT_HI14Q_TXBD_DESA) +#define BITS_HI14Q_TXBD_DESA \ + (BIT_MASK_HI14Q_TXBD_DESA << BIT_SHIFT_HI14Q_TXBD_DESA) +#define BIT_CLEAR_HI14Q_TXBD_DESA(x) ((x) & (~BITS_HI14Q_TXBD_DESA)) +#define BIT_GET_HI14Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA) & BIT_MASK_HI14Q_TXBD_DESA) +#define BIT_SET_HI14Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI14Q_TXBD_DESA(x) | BIT_HI14Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HI0Q_TXBD_DESA_L (Offset 0x13A8) */ + +#define BIT_SHIFT_HI0Q_TXBD_DESA_L 0 +#define BIT_MASK_HI0Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI0Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_L) << BIT_SHIFT_HI0Q_TXBD_DESA_L) +#define BITS_HI0Q_TXBD_DESA_L \ + (BIT_MASK_HI0Q_TXBD_DESA_L << BIT_SHIFT_HI0Q_TXBD_DESA_L) +#define BIT_CLEAR_HI0Q_TXBD_DESA_L(x) ((x) & (~BITS_HI0Q_TXBD_DESA_L)) +#define BIT_GET_HI0Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_L) & BIT_MASK_HI0Q_TXBD_DESA_L) +#define BIT_SET_HI0Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_L(x) | BIT_HI0Q_TXBD_DESA_L(v)) + +/* 2 REG_HI0Q_TXBD_DESA_H (Offset 0x13AC) */ + +#define BIT_SHIFT_HI0Q_TXBD_DESA_H 0 +#define BIT_MASK_HI0Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI0Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_H) << BIT_SHIFT_HI0Q_TXBD_DESA_H) +#define BITS_HI0Q_TXBD_DESA_H \ + (BIT_MASK_HI0Q_TXBD_DESA_H << BIT_SHIFT_HI0Q_TXBD_DESA_H) +#define BIT_CLEAR_HI0Q_TXBD_DESA_H(x) ((x) & (~BITS_HI0Q_TXBD_DESA_H)) +#define BIT_GET_HI0Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_H) & BIT_MASK_HI0Q_TXBD_DESA_H) +#define BIT_SET_HI0Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_H(x) | BIT_HI0Q_TXBD_DESA_H(v)) -#define BIT_SHIFT_FW_MSG4 0 -#define BIT_MASK_FW_MSG4 0xffffffffL -#define BIT_FW_MSG4(x) (((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4) -#define BIT_GET_FW_MSG4(x) (((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4) +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI15Q_TXBD_DESA (Offset 0x13B0) */ + +#define BIT_SHIFT_HI15Q_TXBD_DESA 0 +#define BIT_MASK_HI15Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI15Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI15Q_TXBD_DESA) << BIT_SHIFT_HI15Q_TXBD_DESA) +#define BITS_HI15Q_TXBD_DESA \ + (BIT_MASK_HI15Q_TXBD_DESA << BIT_SHIFT_HI15Q_TXBD_DESA) +#define BIT_CLEAR_HI15Q_TXBD_DESA(x) ((x) & (~BITS_HI15Q_TXBD_DESA)) +#define BIT_GET_HI15Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA) & BIT_MASK_HI15Q_TXBD_DESA) +#define BIT_SET_HI15Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI15Q_TXBD_DESA(x) | BIT_HI15Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HI1Q_TXBD_DESA_L (Offset 0x13B0) */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_L 0 +#define BIT_MASK_HI1Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI1Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_L) << BIT_SHIFT_HI1Q_TXBD_DESA_L) +#define BITS_HI1Q_TXBD_DESA_L \ + (BIT_MASK_HI1Q_TXBD_DESA_L << BIT_SHIFT_HI1Q_TXBD_DESA_L) +#define BIT_CLEAR_HI1Q_TXBD_DESA_L(x) ((x) & (~BITS_HI1Q_TXBD_DESA_L)) +#define BIT_GET_HI1Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_L) & BIT_MASK_HI1Q_TXBD_DESA_L) +#define BIT_SET_HI1Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_L(x) | BIT_HI1Q_TXBD_DESA_L(v)) + +/* 2 REG_HI1Q_TXBD_DESA_H (Offset 0x13B4) */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_H 0 +#define BIT_MASK_HI1Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI1Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_H) << BIT_SHIFT_HI1Q_TXBD_DESA_H) +#define BITS_HI1Q_TXBD_DESA_H \ + (BIT_MASK_HI1Q_TXBD_DESA_H << BIT_SHIFT_HI1Q_TXBD_DESA_H) +#define BIT_CLEAR_HI1Q_TXBD_DESA_H(x) ((x) & (~BITS_HI1Q_TXBD_DESA_H)) +#define BIT_GET_HI1Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_H) & BIT_MASK_HI1Q_TXBD_DESA_H) +#define BIT_SET_HI1Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_H(x) | BIT_HI1Q_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI8Q_TXBD_NUM (Offset 0x13B8) */ + +#define BIT_HI8Q_FLAG BIT(14) + +#define BIT_SHIFT_HI8Q_DESC_MODE 12 +#define BIT_MASK_HI8Q_DESC_MODE 0x3 +#define BIT_HI8Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI8Q_DESC_MODE) << BIT_SHIFT_HI8Q_DESC_MODE) +#define BITS_HI8Q_DESC_MODE \ + (BIT_MASK_HI8Q_DESC_MODE << BIT_SHIFT_HI8Q_DESC_MODE) +#define BIT_CLEAR_HI8Q_DESC_MODE(x) ((x) & (~BITS_HI8Q_DESC_MODE)) +#define BIT_GET_HI8Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI8Q_DESC_MODE) & BIT_MASK_HI8Q_DESC_MODE) +#define BIT_SET_HI8Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI8Q_DESC_MODE(x) | BIT_HI8Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI8Q_DESC_NUM 0 +#define BIT_MASK_HI8Q_DESC_NUM 0xfff +#define BIT_HI8Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI8Q_DESC_NUM) << BIT_SHIFT_HI8Q_DESC_NUM) +#define BITS_HI8Q_DESC_NUM (BIT_MASK_HI8Q_DESC_NUM << BIT_SHIFT_HI8Q_DESC_NUM) +#define BIT_CLEAR_HI8Q_DESC_NUM(x) ((x) & (~BITS_HI8Q_DESC_NUM)) +#define BIT_GET_HI8Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI8Q_DESC_NUM) & BIT_MASK_HI8Q_DESC_NUM) +#define BIT_SET_HI8Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI8Q_DESC_NUM(x) | BIT_HI8Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HI2Q_TXBD_DESA_L (Offset 0x13B8) */ + +#define BIT_SHIFT_HI2Q_TXBD_DESA_L 0 +#define BIT_MASK_HI2Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI2Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_L) << BIT_SHIFT_HI2Q_TXBD_DESA_L) +#define BITS_HI2Q_TXBD_DESA_L \ + (BIT_MASK_HI2Q_TXBD_DESA_L << BIT_SHIFT_HI2Q_TXBD_DESA_L) +#define BIT_CLEAR_HI2Q_TXBD_DESA_L(x) ((x) & (~BITS_HI2Q_TXBD_DESA_L)) +#define BIT_GET_HI2Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_L) & BIT_MASK_HI2Q_TXBD_DESA_L) +#define BIT_SET_HI2Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_L(x) | BIT_HI2Q_TXBD_DESA_L(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI9Q_TXBD_NUM (Offset 0x13BA) */ + +#define BIT_HI9Q_FLAG BIT(14) + +#define BIT_SHIFT_HI9Q_DESC_MODE 12 +#define BIT_MASK_HI9Q_DESC_MODE 0x3 +#define BIT_HI9Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI9Q_DESC_MODE) << BIT_SHIFT_HI9Q_DESC_MODE) +#define BITS_HI9Q_DESC_MODE \ + (BIT_MASK_HI9Q_DESC_MODE << BIT_SHIFT_HI9Q_DESC_MODE) +#define BIT_CLEAR_HI9Q_DESC_MODE(x) ((x) & (~BITS_HI9Q_DESC_MODE)) +#define BIT_GET_HI9Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI9Q_DESC_MODE) & BIT_MASK_HI9Q_DESC_MODE) +#define BIT_SET_HI9Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI9Q_DESC_MODE(x) | BIT_HI9Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI9Q_DESC_NUM 0 +#define BIT_MASK_HI9Q_DESC_NUM 0xfff +#define BIT_HI9Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI9Q_DESC_NUM) << BIT_SHIFT_HI9Q_DESC_NUM) +#define BITS_HI9Q_DESC_NUM (BIT_MASK_HI9Q_DESC_NUM << BIT_SHIFT_HI9Q_DESC_NUM) +#define BIT_CLEAR_HI9Q_DESC_NUM(x) ((x) & (~BITS_HI9Q_DESC_NUM)) +#define BIT_GET_HI9Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI9Q_DESC_NUM) & BIT_MASK_HI9Q_DESC_NUM) +#define BIT_SET_HI9Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI9Q_DESC_NUM(x) | BIT_HI9Q_DESC_NUM(v)) + +/* 2 REG_HI10Q_TXBD_NUM (Offset 0x13BC) */ + +#define BIT_HI10Q_FLAG BIT(14) + +#define BIT_SHIFT_HI10Q_DESC_MODE 12 +#define BIT_MASK_HI10Q_DESC_MODE 0x3 +#define BIT_HI10Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI10Q_DESC_MODE) << BIT_SHIFT_HI10Q_DESC_MODE) +#define BITS_HI10Q_DESC_MODE \ + (BIT_MASK_HI10Q_DESC_MODE << BIT_SHIFT_HI10Q_DESC_MODE) +#define BIT_CLEAR_HI10Q_DESC_MODE(x) ((x) & (~BITS_HI10Q_DESC_MODE)) +#define BIT_GET_HI10Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI10Q_DESC_MODE) & BIT_MASK_HI10Q_DESC_MODE) +#define BIT_SET_HI10Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI10Q_DESC_MODE(x) | BIT_HI10Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI10Q_DESC_NUM 0 +#define BIT_MASK_HI10Q_DESC_NUM 0xfff +#define BIT_HI10Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI10Q_DESC_NUM) << BIT_SHIFT_HI10Q_DESC_NUM) +#define BITS_HI10Q_DESC_NUM \ + (BIT_MASK_HI10Q_DESC_NUM << BIT_SHIFT_HI10Q_DESC_NUM) +#define BIT_CLEAR_HI10Q_DESC_NUM(x) ((x) & (~BITS_HI10Q_DESC_NUM)) +#define BIT_GET_HI10Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI10Q_DESC_NUM) & BIT_MASK_HI10Q_DESC_NUM) +#define BIT_SET_HI10Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI10Q_DESC_NUM(x) | BIT_HI10Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HI2Q_TXBD_DESA_H (Offset 0x13BC) */ + +#define BIT_SHIFT_HI2Q_TXBD_DESA_H 0 +#define BIT_MASK_HI2Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI2Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_H) << BIT_SHIFT_HI2Q_TXBD_DESA_H) +#define BITS_HI2Q_TXBD_DESA_H \ + (BIT_MASK_HI2Q_TXBD_DESA_H << BIT_SHIFT_HI2Q_TXBD_DESA_H) +#define BIT_CLEAR_HI2Q_TXBD_DESA_H(x) ((x) & (~BITS_HI2Q_TXBD_DESA_H)) +#define BIT_GET_HI2Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_H) & BIT_MASK_HI2Q_TXBD_DESA_H) +#define BIT_SET_HI2Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_H(x) | BIT_HI2Q_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI11Q_TXBD_NUM (Offset 0x13BE) */ + +#define BIT_HI11Q_FLAG BIT(14) + +#define BIT_SHIFT_HI11Q_DESC_MODE 12 +#define BIT_MASK_HI11Q_DESC_MODE 0x3 +#define BIT_HI11Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI11Q_DESC_MODE) << BIT_SHIFT_HI11Q_DESC_MODE) +#define BITS_HI11Q_DESC_MODE \ + (BIT_MASK_HI11Q_DESC_MODE << BIT_SHIFT_HI11Q_DESC_MODE) +#define BIT_CLEAR_HI11Q_DESC_MODE(x) ((x) & (~BITS_HI11Q_DESC_MODE)) +#define BIT_GET_HI11Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI11Q_DESC_MODE) & BIT_MASK_HI11Q_DESC_MODE) +#define BIT_SET_HI11Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI11Q_DESC_MODE(x) | BIT_HI11Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI11Q_DESC_NUM 0 +#define BIT_MASK_HI11Q_DESC_NUM 0xfff +#define BIT_HI11Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI11Q_DESC_NUM) << BIT_SHIFT_HI11Q_DESC_NUM) +#define BITS_HI11Q_DESC_NUM \ + (BIT_MASK_HI11Q_DESC_NUM << BIT_SHIFT_HI11Q_DESC_NUM) +#define BIT_CLEAR_HI11Q_DESC_NUM(x) ((x) & (~BITS_HI11Q_DESC_NUM)) +#define BIT_GET_HI11Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI11Q_DESC_NUM) & BIT_MASK_HI11Q_DESC_NUM) +#define BIT_SET_HI11Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI11Q_DESC_NUM(x) | BIT_HI11Q_DESC_NUM(v)) + +/* 2 REG_HI12Q_TXBD_NUM (Offset 0x13C0) */ + +#define BIT_HI12Q_FLAG BIT(14) + +#define BIT_SHIFT_HI12Q_DESC_MODE 12 +#define BIT_MASK_HI12Q_DESC_MODE 0x3 +#define BIT_HI12Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI12Q_DESC_MODE) << BIT_SHIFT_HI12Q_DESC_MODE) +#define BITS_HI12Q_DESC_MODE \ + (BIT_MASK_HI12Q_DESC_MODE << BIT_SHIFT_HI12Q_DESC_MODE) +#define BIT_CLEAR_HI12Q_DESC_MODE(x) ((x) & (~BITS_HI12Q_DESC_MODE)) +#define BIT_GET_HI12Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI12Q_DESC_MODE) & BIT_MASK_HI12Q_DESC_MODE) +#define BIT_SET_HI12Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI12Q_DESC_MODE(x) | BIT_HI12Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI12Q_DESC_NUM 0 +#define BIT_MASK_HI12Q_DESC_NUM 0xfff +#define BIT_HI12Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI12Q_DESC_NUM) << BIT_SHIFT_HI12Q_DESC_NUM) +#define BITS_HI12Q_DESC_NUM \ + (BIT_MASK_HI12Q_DESC_NUM << BIT_SHIFT_HI12Q_DESC_NUM) +#define BIT_CLEAR_HI12Q_DESC_NUM(x) ((x) & (~BITS_HI12Q_DESC_NUM)) +#define BIT_GET_HI12Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI12Q_DESC_NUM) & BIT_MASK_HI12Q_DESC_NUM) +#define BIT_SET_HI12Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI12Q_DESC_NUM(x) | BIT_HI12Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HI3Q_TXBD_DESA_L (Offset 0x13C0) */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_L 0 +#define BIT_MASK_HI3Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI3Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_L) << BIT_SHIFT_HI3Q_TXBD_DESA_L) +#define BITS_HI3Q_TXBD_DESA_L \ + (BIT_MASK_HI3Q_TXBD_DESA_L << BIT_SHIFT_HI3Q_TXBD_DESA_L) +#define BIT_CLEAR_HI3Q_TXBD_DESA_L(x) ((x) & (~BITS_HI3Q_TXBD_DESA_L)) +#define BIT_GET_HI3Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_L) & BIT_MASK_HI3Q_TXBD_DESA_L) +#define BIT_SET_HI3Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_L(x) | BIT_HI3Q_TXBD_DESA_L(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI13Q_TXBD_NUM (Offset 0x13C2) */ + +#define BIT_HI13Q_FLAG BIT(14) + +#define BIT_SHIFT_HI13Q_DESC_MODE 12 +#define BIT_MASK_HI13Q_DESC_MODE 0x3 +#define BIT_HI13Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI13Q_DESC_MODE) << BIT_SHIFT_HI13Q_DESC_MODE) +#define BITS_HI13Q_DESC_MODE \ + (BIT_MASK_HI13Q_DESC_MODE << BIT_SHIFT_HI13Q_DESC_MODE) +#define BIT_CLEAR_HI13Q_DESC_MODE(x) ((x) & (~BITS_HI13Q_DESC_MODE)) +#define BIT_GET_HI13Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI13Q_DESC_MODE) & BIT_MASK_HI13Q_DESC_MODE) +#define BIT_SET_HI13Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI13Q_DESC_MODE(x) | BIT_HI13Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI13Q_DESC_NUM 0 +#define BIT_MASK_HI13Q_DESC_NUM 0xfff +#define BIT_HI13Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI13Q_DESC_NUM) << BIT_SHIFT_HI13Q_DESC_NUM) +#define BITS_HI13Q_DESC_NUM \ + (BIT_MASK_HI13Q_DESC_NUM << BIT_SHIFT_HI13Q_DESC_NUM) +#define BIT_CLEAR_HI13Q_DESC_NUM(x) ((x) & (~BITS_HI13Q_DESC_NUM)) +#define BIT_GET_HI13Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI13Q_DESC_NUM) & BIT_MASK_HI13Q_DESC_NUM) +#define BIT_SET_HI13Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI13Q_DESC_NUM(x) | BIT_HI13Q_DESC_NUM(v)) + +/* 2 REG_HI14Q_TXBD_NUM (Offset 0x13C4) */ + +#define BIT_HI14Q_FLAG BIT(14) + +#define BIT_SHIFT_HI14Q_DESC_MODE 12 +#define BIT_MASK_HI14Q_DESC_MODE 0x3 +#define BIT_HI14Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI14Q_DESC_MODE) << BIT_SHIFT_HI14Q_DESC_MODE) +#define BITS_HI14Q_DESC_MODE \ + (BIT_MASK_HI14Q_DESC_MODE << BIT_SHIFT_HI14Q_DESC_MODE) +#define BIT_CLEAR_HI14Q_DESC_MODE(x) ((x) & (~BITS_HI14Q_DESC_MODE)) +#define BIT_GET_HI14Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI14Q_DESC_MODE) & BIT_MASK_HI14Q_DESC_MODE) +#define BIT_SET_HI14Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI14Q_DESC_MODE(x) | BIT_HI14Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI14Q_DESC_NUM 0 +#define BIT_MASK_HI14Q_DESC_NUM 0xfff +#define BIT_HI14Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI14Q_DESC_NUM) << BIT_SHIFT_HI14Q_DESC_NUM) +#define BITS_HI14Q_DESC_NUM \ + (BIT_MASK_HI14Q_DESC_NUM << BIT_SHIFT_HI14Q_DESC_NUM) +#define BIT_CLEAR_HI14Q_DESC_NUM(x) ((x) & (~BITS_HI14Q_DESC_NUM)) +#define BIT_GET_HI14Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI14Q_DESC_NUM) & BIT_MASK_HI14Q_DESC_NUM) +#define BIT_SET_HI14Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI14Q_DESC_NUM(x) | BIT_HI14Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HI3Q_TXBD_DESA_H (Offset 0x13C4) */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_H 0 +#define BIT_MASK_HI3Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI3Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_H) << BIT_SHIFT_HI3Q_TXBD_DESA_H) +#define BITS_HI3Q_TXBD_DESA_H \ + (BIT_MASK_HI3Q_TXBD_DESA_H << BIT_SHIFT_HI3Q_TXBD_DESA_H) +#define BIT_CLEAR_HI3Q_TXBD_DESA_H(x) ((x) & (~BITS_HI3Q_TXBD_DESA_H)) +#define BIT_GET_HI3Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_H) & BIT_MASK_HI3Q_TXBD_DESA_H) +#define BIT_SET_HI3Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_H(x) | BIT_HI3Q_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI15Q_TXBD_NUM (Offset 0x13C6) */ + +#define BIT_HI15Q_FLAG BIT(14) + +#define BIT_SHIFT_HI15Q_DESC_MODE 12 +#define BIT_MASK_HI15Q_DESC_MODE 0x3 +#define BIT_HI15Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI15Q_DESC_MODE) << BIT_SHIFT_HI15Q_DESC_MODE) +#define BITS_HI15Q_DESC_MODE \ + (BIT_MASK_HI15Q_DESC_MODE << BIT_SHIFT_HI15Q_DESC_MODE) +#define BIT_CLEAR_HI15Q_DESC_MODE(x) ((x) & (~BITS_HI15Q_DESC_MODE)) +#define BIT_GET_HI15Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI15Q_DESC_MODE) & BIT_MASK_HI15Q_DESC_MODE) +#define BIT_SET_HI15Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI15Q_DESC_MODE(x) | BIT_HI15Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI15Q_DESC_NUM 0 +#define BIT_MASK_HI15Q_DESC_NUM 0xfff +#define BIT_HI15Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI15Q_DESC_NUM) << BIT_SHIFT_HI15Q_DESC_NUM) +#define BITS_HI15Q_DESC_NUM \ + (BIT_MASK_HI15Q_DESC_NUM << BIT_SHIFT_HI15Q_DESC_NUM) +#define BIT_CLEAR_HI15Q_DESC_NUM(x) ((x) & (~BITS_HI15Q_DESC_NUM)) +#define BIT_GET_HI15Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI15Q_DESC_NUM) & BIT_MASK_HI15Q_DESC_NUM) +#define BIT_SET_HI15Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI15Q_DESC_NUM(x) | BIT_HI15Q_DESC_NUM(v)) + +/* 2 REG_HIQ_DMA_STOP (Offset 0x13C8) */ + +#define BIT_STOP_HI15Q BIT(7) +#define BIT_STOP_HI14Q BIT(6) +#define BIT_STOP_HI13Q BIT(5) +#define BIT_STOP_HI12Q BIT(4) +#define BIT_STOP_HI11Q BIT(3) +#define BIT_STOP_HI10Q BIT(2) +#define BIT_STOP_HI9Q BIT(1) +#define BIT_STOP_HI8Q BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HI4Q_TXBD_DESA_L (Offset 0x13C8) */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_L 0 +#define BIT_MASK_HI4Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI4Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_L) << BIT_SHIFT_HI4Q_TXBD_DESA_L) +#define BITS_HI4Q_TXBD_DESA_L \ + (BIT_MASK_HI4Q_TXBD_DESA_L << BIT_SHIFT_HI4Q_TXBD_DESA_L) +#define BIT_CLEAR_HI4Q_TXBD_DESA_L(x) ((x) & (~BITS_HI4Q_TXBD_DESA_L)) +#define BIT_GET_HI4Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_L) & BIT_MASK_HI4Q_TXBD_DESA_L) +#define BIT_SET_HI4Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_L(x) | BIT_HI4Q_TXBD_DESA_L(v)) + +/* 2 REG_HI4Q_TXBD_DESA_H (Offset 0x13CC) */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_H 0 +#define BIT_MASK_HI4Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI4Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_H) << BIT_SHIFT_HI4Q_TXBD_DESA_H) +#define BITS_HI4Q_TXBD_DESA_H \ + (BIT_MASK_HI4Q_TXBD_DESA_H << BIT_SHIFT_HI4Q_TXBD_DESA_H) +#define BIT_CLEAR_HI4Q_TXBD_DESA_H(x) ((x) & (~BITS_HI4Q_TXBD_DESA_H)) +#define BIT_GET_HI4Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_H) & BIT_MASK_HI4Q_TXBD_DESA_H) +#define BIT_SET_HI4Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_H(x) | BIT_HI4Q_TXBD_DESA_H(v)) + +/* 2 REG_HI5Q_TXBD_DESA_L (Offset 0x13D0) */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_L 0 +#define BIT_MASK_HI5Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI5Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_L) << BIT_SHIFT_HI5Q_TXBD_DESA_L) +#define BITS_HI5Q_TXBD_DESA_L \ + (BIT_MASK_HI5Q_TXBD_DESA_L << BIT_SHIFT_HI5Q_TXBD_DESA_L) +#define BIT_CLEAR_HI5Q_TXBD_DESA_L(x) ((x) & (~BITS_HI5Q_TXBD_DESA_L)) +#define BIT_GET_HI5Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_L) & BIT_MASK_HI5Q_TXBD_DESA_L) +#define BIT_SET_HI5Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_L(x) | BIT_HI5Q_TXBD_DESA_L(v)) + +/* 2 REG_HI5Q_TXBD_DESA_H (Offset 0x13D4) */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_H 0 +#define BIT_MASK_HI5Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI5Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_H) << BIT_SHIFT_HI5Q_TXBD_DESA_H) +#define BITS_HI5Q_TXBD_DESA_H \ + (BIT_MASK_HI5Q_TXBD_DESA_H << BIT_SHIFT_HI5Q_TXBD_DESA_H) +#define BIT_CLEAR_HI5Q_TXBD_DESA_H(x) ((x) & (~BITS_HI5Q_TXBD_DESA_H)) +#define BIT_GET_HI5Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_H) & BIT_MASK_HI5Q_TXBD_DESA_H) +#define BIT_SET_HI5Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_H(x) | BIT_HI5Q_TXBD_DESA_H(v)) + +/* 2 REG_HI6Q_TXBD_DESA_L (Offset 0x13D8) */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_L 0 +#define BIT_MASK_HI6Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI6Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_L) << BIT_SHIFT_HI6Q_TXBD_DESA_L) +#define BITS_HI6Q_TXBD_DESA_L \ + (BIT_MASK_HI6Q_TXBD_DESA_L << BIT_SHIFT_HI6Q_TXBD_DESA_L) +#define BIT_CLEAR_HI6Q_TXBD_DESA_L(x) ((x) & (~BITS_HI6Q_TXBD_DESA_L)) +#define BIT_GET_HI6Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_L) & BIT_MASK_HI6Q_TXBD_DESA_L) +#define BIT_SET_HI6Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_L(x) | BIT_HI6Q_TXBD_DESA_L(v)) + +/* 2 REG_HI6Q_TXBD_DESA_H (Offset 0x13DC) */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_H 0 +#define BIT_MASK_HI6Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI6Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_H) << BIT_SHIFT_HI6Q_TXBD_DESA_H) +#define BITS_HI6Q_TXBD_DESA_H \ + (BIT_MASK_HI6Q_TXBD_DESA_H << BIT_SHIFT_HI6Q_TXBD_DESA_H) +#define BIT_CLEAR_HI6Q_TXBD_DESA_H(x) ((x) & (~BITS_HI6Q_TXBD_DESA_H)) +#define BIT_GET_HI6Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_H) & BIT_MASK_HI6Q_TXBD_DESA_H) +#define BIT_SET_HI6Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_H(x) | BIT_HI6Q_TXBD_DESA_H(v)) + +/* 2 REG_HI7Q_TXBD_DESA_L (Offset 0x13E0) */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_L 0 +#define BIT_MASK_HI7Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI7Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_L) << BIT_SHIFT_HI7Q_TXBD_DESA_L) +#define BITS_HI7Q_TXBD_DESA_L \ + (BIT_MASK_HI7Q_TXBD_DESA_L << BIT_SHIFT_HI7Q_TXBD_DESA_L) +#define BIT_CLEAR_HI7Q_TXBD_DESA_L(x) ((x) & (~BITS_HI7Q_TXBD_DESA_L)) +#define BIT_GET_HI7Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_L) & BIT_MASK_HI7Q_TXBD_DESA_L) +#define BIT_SET_HI7Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_L(x) | BIT_HI7Q_TXBD_DESA_L(v)) + +/* 2 REG_HI7Q_TXBD_DESA_H (Offset 0x13E4) */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_H 0 +#define BIT_MASK_HI7Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI7Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_H) << BIT_SHIFT_HI7Q_TXBD_DESA_H) +#define BITS_HI7Q_TXBD_DESA_H \ + (BIT_MASK_HI7Q_TXBD_DESA_H << BIT_SHIFT_HI7Q_TXBD_DESA_H) +#define BIT_CLEAR_HI7Q_TXBD_DESA_H(x) ((x) & (~BITS_HI7Q_TXBD_DESA_H)) +#define BIT_GET_HI7Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_H) & BIT_MASK_HI7Q_TXBD_DESA_H) +#define BIT_SET_HI7Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_H(x) | BIT_HI7Q_TXBD_DESA_H(v)) + +/* 2 REG_ACH8_ACH9_TXBD_NUM (Offset 0x13E8) */ + +#define BIT_PCIE_ACH9_FLAG BIT(30) + +#define BIT_SHIFT_ACH9_DESC_MODE 28 +#define BIT_MASK_ACH9_DESC_MODE 0x3 +#define BIT_ACH9_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH9_DESC_MODE) << BIT_SHIFT_ACH9_DESC_MODE) +#define BITS_ACH9_DESC_MODE \ + (BIT_MASK_ACH9_DESC_MODE << BIT_SHIFT_ACH9_DESC_MODE) +#define BIT_CLEAR_ACH9_DESC_MODE(x) ((x) & (~BITS_ACH9_DESC_MODE)) +#define BIT_GET_ACH9_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH9_DESC_MODE) & BIT_MASK_ACH9_DESC_MODE) +#define BIT_SET_ACH9_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH9_DESC_MODE(x) | BIT_ACH9_DESC_MODE(v)) + +#define BIT_SHIFT_ACH9_DESC_NUM 16 +#define BIT_MASK_ACH9_DESC_NUM 0xfff +#define BIT_ACH9_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH9_DESC_NUM) << BIT_SHIFT_ACH9_DESC_NUM) +#define BITS_ACH9_DESC_NUM (BIT_MASK_ACH9_DESC_NUM << BIT_SHIFT_ACH9_DESC_NUM) +#define BIT_CLEAR_ACH9_DESC_NUM(x) ((x) & (~BITS_ACH9_DESC_NUM)) +#define BIT_GET_ACH9_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH9_DESC_NUM) & BIT_MASK_ACH9_DESC_NUM) +#define BIT_SET_ACH9_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH9_DESC_NUM(x) | BIT_ACH9_DESC_NUM(v)) + +#define BIT_PCIE_ACH8_FLAG BIT(14) + +#define BIT_SHIFT_ACH8_DESC_MODE 12 +#define BIT_MASK_ACH8_DESC_MODE 0x3 +#define BIT_ACH8_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH8_DESC_MODE) << BIT_SHIFT_ACH8_DESC_MODE) +#define BITS_ACH8_DESC_MODE \ + (BIT_MASK_ACH8_DESC_MODE << BIT_SHIFT_ACH8_DESC_MODE) +#define BIT_CLEAR_ACH8_DESC_MODE(x) ((x) & (~BITS_ACH8_DESC_MODE)) +#define BIT_GET_ACH8_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH8_DESC_MODE) & BIT_MASK_ACH8_DESC_MODE) +#define BIT_SET_ACH8_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH8_DESC_MODE(x) | BIT_ACH8_DESC_MODE(v)) + +#define BIT_SHIFT_ACH8_DESC_NUM 0 +#define BIT_MASK_ACH8_DESC_NUM 0xfff +#define BIT_ACH8_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH8_DESC_NUM) << BIT_SHIFT_ACH8_DESC_NUM) +#define BITS_ACH8_DESC_NUM (BIT_MASK_ACH8_DESC_NUM << BIT_SHIFT_ACH8_DESC_NUM) +#define BIT_CLEAR_ACH8_DESC_NUM(x) ((x) & (~BITS_ACH8_DESC_NUM)) +#define BIT_GET_ACH8_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH8_DESC_NUM) & BIT_MASK_ACH8_DESC_NUM) +#define BIT_SET_ACH8_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH8_DESC_NUM(x) | BIT_ACH8_DESC_NUM(v)) + +/* 2 REG_ACH10_ACH11_TXBD_NUM (Offset 0x13EC) */ + +#define BIT_PCIE_ACH11_FLAG BIT(30) + +#define BIT_SHIFT_ACH11_DESC_MODE 28 +#define BIT_MASK_ACH11_DESC_MODE 0x3 +#define BIT_ACH11_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH11_DESC_MODE) << BIT_SHIFT_ACH11_DESC_MODE) +#define BITS_ACH11_DESC_MODE \ + (BIT_MASK_ACH11_DESC_MODE << BIT_SHIFT_ACH11_DESC_MODE) +#define BIT_CLEAR_ACH11_DESC_MODE(x) ((x) & (~BITS_ACH11_DESC_MODE)) +#define BIT_GET_ACH11_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH11_DESC_MODE) & BIT_MASK_ACH11_DESC_MODE) +#define BIT_SET_ACH11_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH11_DESC_MODE(x) | BIT_ACH11_DESC_MODE(v)) + +#define BIT_SHIFT_ACH11_DESC_NUM 16 +#define BIT_MASK_ACH11_DESC_NUM 0xfff +#define BIT_ACH11_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH11_DESC_NUM) << BIT_SHIFT_ACH11_DESC_NUM) +#define BITS_ACH11_DESC_NUM \ + (BIT_MASK_ACH11_DESC_NUM << BIT_SHIFT_ACH11_DESC_NUM) +#define BIT_CLEAR_ACH11_DESC_NUM(x) ((x) & (~BITS_ACH11_DESC_NUM)) +#define BIT_GET_ACH11_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH11_DESC_NUM) & BIT_MASK_ACH11_DESC_NUM) +#define BIT_SET_ACH11_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH11_DESC_NUM(x) | BIT_ACH11_DESC_NUM(v)) + +#define BIT_PCIE_ACH10_FLAG BIT(14) + +#define BIT_SHIFT_ACH10_DESC_MODE 12 +#define BIT_MASK_ACH10_DESC_MODE 0x3 +#define BIT_ACH10_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH10_DESC_MODE) << BIT_SHIFT_ACH10_DESC_MODE) +#define BITS_ACH10_DESC_MODE \ + (BIT_MASK_ACH10_DESC_MODE << BIT_SHIFT_ACH10_DESC_MODE) +#define BIT_CLEAR_ACH10_DESC_MODE(x) ((x) & (~BITS_ACH10_DESC_MODE)) +#define BIT_GET_ACH10_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH10_DESC_MODE) & BIT_MASK_ACH10_DESC_MODE) +#define BIT_SET_ACH10_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH10_DESC_MODE(x) | BIT_ACH10_DESC_MODE(v)) + +#define BIT_SHIFT_ACH10_DESC_NUM 0 +#define BIT_MASK_ACH10_DESC_NUM 0xfff +#define BIT_ACH10_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH10_DESC_NUM) << BIT_SHIFT_ACH10_DESC_NUM) +#define BITS_ACH10_DESC_NUM \ + (BIT_MASK_ACH10_DESC_NUM << BIT_SHIFT_ACH10_DESC_NUM) +#define BIT_CLEAR_ACH10_DESC_NUM(x) ((x) & (~BITS_ACH10_DESC_NUM)) +#define BIT_GET_ACH10_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH10_DESC_NUM) & BIT_MASK_ACH10_DESC_NUM) +#define BIT_SET_ACH10_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH10_DESC_NUM(x) | BIT_ACH10_DESC_NUM(v)) + +/* 2 REG_ACH12_ACH13_TXBD_NUM (Offset 0x13F0) */ + +#define BIT_PCIE_ACH13_FLAG BIT(30) + +#define BIT_SHIFT_ACH13_DESC_MODE 28 +#define BIT_MASK_ACH13_DESC_MODE 0x3 +#define BIT_ACH13_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH13_DESC_MODE) << BIT_SHIFT_ACH13_DESC_MODE) +#define BITS_ACH13_DESC_MODE \ + (BIT_MASK_ACH13_DESC_MODE << BIT_SHIFT_ACH13_DESC_MODE) +#define BIT_CLEAR_ACH13_DESC_MODE(x) ((x) & (~BITS_ACH13_DESC_MODE)) +#define BIT_GET_ACH13_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH13_DESC_MODE) & BIT_MASK_ACH13_DESC_MODE) +#define BIT_SET_ACH13_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH13_DESC_MODE(x) | BIT_ACH13_DESC_MODE(v)) + +#define BIT_SHIFT_ACH13_DESC_NUM 16 +#define BIT_MASK_ACH13_DESC_NUM 0xfff +#define BIT_ACH13_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH13_DESC_NUM) << BIT_SHIFT_ACH13_DESC_NUM) +#define BITS_ACH13_DESC_NUM \ + (BIT_MASK_ACH13_DESC_NUM << BIT_SHIFT_ACH13_DESC_NUM) +#define BIT_CLEAR_ACH13_DESC_NUM(x) ((x) & (~BITS_ACH13_DESC_NUM)) +#define BIT_GET_ACH13_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH13_DESC_NUM) & BIT_MASK_ACH13_DESC_NUM) +#define BIT_SET_ACH13_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH13_DESC_NUM(x) | BIT_ACH13_DESC_NUM(v)) + +#define BIT_PCIE_ACH12_FLAG BIT(14) + +#define BIT_SHIFT_ACH12_DESC_MODE 12 +#define BIT_MASK_ACH12_DESC_MODE 0x3 +#define BIT_ACH12_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH12_DESC_MODE) << BIT_SHIFT_ACH12_DESC_MODE) +#define BITS_ACH12_DESC_MODE \ + (BIT_MASK_ACH12_DESC_MODE << BIT_SHIFT_ACH12_DESC_MODE) +#define BIT_CLEAR_ACH12_DESC_MODE(x) ((x) & (~BITS_ACH12_DESC_MODE)) +#define BIT_GET_ACH12_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH12_DESC_MODE) & BIT_MASK_ACH12_DESC_MODE) +#define BIT_SET_ACH12_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH12_DESC_MODE(x) | BIT_ACH12_DESC_MODE(v)) + +#define BIT_SHIFT_ACH12_DESC_NUM 0 +#define BIT_MASK_ACH12_DESC_NUM 0xfff +#define BIT_ACH12_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH12_DESC_NUM) << BIT_SHIFT_ACH12_DESC_NUM) +#define BITS_ACH12_DESC_NUM \ + (BIT_MASK_ACH12_DESC_NUM << BIT_SHIFT_ACH12_DESC_NUM) +#define BIT_CLEAR_ACH12_DESC_NUM(x) ((x) & (~BITS_ACH12_DESC_NUM)) +#define BIT_GET_ACH12_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH12_DESC_NUM) & BIT_MASK_ACH12_DESC_NUM) +#define BIT_SET_ACH12_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH12_DESC_NUM(x) | BIT_ACH12_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_OLD_DEHANG (Offset 0x13F4) */ -/* 2 REG_MSG5 (Offset 0x11FC) */ +#define BIT_OLD_DEHANG BIT(1) +#endif -#define BIT_SHIFT_FW_MSG5 0 -#define BIT_MASK_FW_MSG5 0xffffffffL -#define BIT_FW_MSG5(x) (((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5) -#define BIT_GET_FW_MSG5(x) (((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_ACH4_TXBD_DESA_L (Offset 0x13F8) */ -/* 2 REG_DDMA_CH0SA (Offset 0x1200) */ +#define BIT_SHIFT_ACH4_TXBD_DESA_L 0 +#define BIT_MASK_ACH4_TXBD_DESA_L 0xffffffffL +#define BIT_ACH4_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH4_TXBD_DESA_L) << BIT_SHIFT_ACH4_TXBD_DESA_L) +#define BITS_ACH4_TXBD_DESA_L \ + (BIT_MASK_ACH4_TXBD_DESA_L << BIT_SHIFT_ACH4_TXBD_DESA_L) +#define BIT_CLEAR_ACH4_TXBD_DESA_L(x) ((x) & (~BITS_ACH4_TXBD_DESA_L)) +#define BIT_GET_ACH4_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_L) & BIT_MASK_ACH4_TXBD_DESA_L) +#define BIT_SET_ACH4_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH4_TXBD_DESA_L(x) | BIT_ACH4_TXBD_DESA_L(v)) +/* 2 REG_ACH4_TXBD_DESA_H (Offset 0x13FC) */ -#define BIT_SHIFT_DDMACH0_SA 0 -#define BIT_MASK_DDMACH0_SA 0xffffffffL -#define BIT_DDMACH0_SA(x) (((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA) -#define BIT_GET_DDMACH0_SA(x) (((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA) +#define BIT_SHIFT_ACH4_TXBD_DESA_H 0 +#define BIT_MASK_ACH4_TXBD_DESA_H 0xffffffffL +#define BIT_ACH4_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH4_TXBD_DESA_H) << BIT_SHIFT_ACH4_TXBD_DESA_H) +#define BITS_ACH4_TXBD_DESA_H \ + (BIT_MASK_ACH4_TXBD_DESA_H << BIT_SHIFT_ACH4_TXBD_DESA_H) +#define BIT_CLEAR_ACH4_TXBD_DESA_H(x) ((x) & (~BITS_ACH4_TXBD_DESA_H)) +#define BIT_GET_ACH4_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_H) & BIT_MASK_ACH4_TXBD_DESA_H) +#define BIT_SET_ACH4_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH4_TXBD_DESA_H(x) | BIT_ACH4_TXBD_DESA_H(v)) +#endif -/* 2 REG_DDMA_CH0DA (Offset 0x1204) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_Q0_Q1_INFO (Offset 0x1400) */ -#define BIT_SHIFT_DDMACH0_DA 0 -#define BIT_MASK_DDMACH0_DA 0xffffffffL -#define BIT_DDMACH0_DA(x) (((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA) -#define BIT_GET_DDMACH0_DA(x) (((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA) +#define BIT_SHIFT_AC1_PKT_INFO 16 +#define BIT_MASK_AC1_PKT_INFO 0xfff +#define BIT_AC1_PKT_INFO(x) \ + (((x) & BIT_MASK_AC1_PKT_INFO) << BIT_SHIFT_AC1_PKT_INFO) +#define BITS_AC1_PKT_INFO (BIT_MASK_AC1_PKT_INFO << BIT_SHIFT_AC1_PKT_INFO) +#define BIT_CLEAR_AC1_PKT_INFO(x) ((x) & (~BITS_AC1_PKT_INFO)) +#define BIT_GET_AC1_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC1_PKT_INFO) & BIT_MASK_AC1_PKT_INFO) +#define BIT_SET_AC1_PKT_INFO(x, v) \ + (BIT_CLEAR_AC1_PKT_INFO(x) | BIT_AC1_PKT_INFO(v)) +#endif -/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ +#if (HALMAC_8814B_SUPPORT) -#define BIT_DDMACH0_OWN BIT(31) -#define BIT_DDMACH0_CHKSUM_EN BIT(29) -#define BIT_DDMACH0_DA_W_DISABLE BIT(28) -#define BIT_DDMACH0_CHKSUM_STS BIT(27) -#define BIT_DDMACH0_DDMA_MODE BIT(26) -#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) -#define BIT_DDMACH0_CHKSUM_CONT BIT(24) +/* 2 REG_MU_OFFSET (Offset 0x1400) */ -#define BIT_SHIFT_DDMACH0_DLEN 0 -#define BIT_MASK_DDMACH0_DLEN 0x3ffff -#define BIT_DDMACH0_DLEN(x) (((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN) -#define BIT_GET_DDMACH0_DLEN(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN) +#define BIT_SHIFT_MU_RATETABLE_OFFSET 16 +#define BIT_MASK_MU_RATETABLE_OFFSET 0x1ff +#define BIT_MU_RATETABLE_OFFSET(x) \ + (((x) & BIT_MASK_MU_RATETABLE_OFFSET) << BIT_SHIFT_MU_RATETABLE_OFFSET) +#define BITS_MU_RATETABLE_OFFSET \ + (BIT_MASK_MU_RATETABLE_OFFSET << BIT_SHIFT_MU_RATETABLE_OFFSET) +#define BIT_CLEAR_MU_RATETABLE_OFFSET(x) ((x) & (~BITS_MU_RATETABLE_OFFSET)) +#define BIT_GET_MU_RATETABLE_OFFSET(x) \ + (((x) >> BIT_SHIFT_MU_RATETABLE_OFFSET) & BIT_MASK_MU_RATETABLE_OFFSET) +#define BIT_SET_MU_RATETABLE_OFFSET(x, v) \ + (BIT_CLEAR_MU_RATETABLE_OFFSET(x) | BIT_MU_RATETABLE_OFFSET(v)) +#endif -/* 2 REG_DDMA_CH1SA (Offset 0x1210) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_Q0_Q1_INFO (Offset 0x1400) */ -#define BIT_SHIFT_DDMACH1_SA 0 -#define BIT_MASK_DDMACH1_SA 0xffffffffL -#define BIT_DDMACH1_SA(x) (((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA) -#define BIT_GET_DDMACH1_SA(x) (((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA) +#define BIT_SHIFT_AC0_PKT_INFO 0 +#define BIT_MASK_AC0_PKT_INFO 0xfff +#define BIT_AC0_PKT_INFO(x) \ + (((x) & BIT_MASK_AC0_PKT_INFO) << BIT_SHIFT_AC0_PKT_INFO) +#define BITS_AC0_PKT_INFO (BIT_MASK_AC0_PKT_INFO << BIT_SHIFT_AC0_PKT_INFO) +#define BIT_CLEAR_AC0_PKT_INFO(x) ((x) & (~BITS_AC0_PKT_INFO)) +#define BIT_GET_AC0_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC0_PKT_INFO) & BIT_MASK_AC0_PKT_INFO) +#define BIT_SET_AC0_PKT_INFO(x, v) \ + (BIT_CLEAR_AC0_PKT_INFO(x) | BIT_AC0_PKT_INFO(v)) +#endif -/* 2 REG_DDMA_CH1DA (Offset 0x1214) */ +#if (HALMAC_8198F_SUPPORT) +/* 2 REG_ARFR6 (Offset 0x1400) */ -#define BIT_SHIFT_DDMACH1_DA 0 -#define BIT_MASK_DDMACH1_DA 0xffffffffL -#define BIT_DDMACH1_DA(x) (((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA) -#define BIT_GET_DDMACH1_DA(x) (((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA) +#define BIT_SHIFT_ARFR6_V1 0 +#define BIT_MASK_ARFR6_V1 0xffffffffffffffffL +#define BIT_ARFR6_V1(x) (((x) & BIT_MASK_ARFR6_V1) << BIT_SHIFT_ARFR6_V1) +#define BITS_ARFR6_V1 (BIT_MASK_ARFR6_V1 << BIT_SHIFT_ARFR6_V1) +#define BIT_CLEAR_ARFR6_V1(x) ((x) & (~BITS_ARFR6_V1)) +#define BIT_GET_ARFR6_V1(x) (((x) >> BIT_SHIFT_ARFR6_V1) & BIT_MASK_ARFR6_V1) +#define BIT_SET_ARFR6_V1(x, v) (BIT_CLEAR_ARFR6_V1(x) | BIT_ARFR6_V1(v)) +#endif -/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ +#if (HALMAC_8814B_SUPPORT) -#define BIT_DDMACH1_OWN BIT(31) -#define BIT_DDMACH1_CHKSUM_EN BIT(29) -#define BIT_DDMACH1_DA_W_DISABLE BIT(28) -#define BIT_DDMACH1_CHKSUM_STS BIT(27) -#define BIT_DDMACH1_DDMA_MODE BIT(26) -#define BIT_DDMACH1_RESET_CHKSUM_STS BIT(25) -#define BIT_DDMACH1_CHKSUM_CONT BIT(24) +/* 2 REG_MU_OFFSET (Offset 0x1400) */ -#define BIT_SHIFT_DDMACH1_DLEN 0 -#define BIT_MASK_DDMACH1_DLEN 0x3ffff -#define BIT_DDMACH1_DLEN(x) (((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN) -#define BIT_GET_DDMACH1_DLEN(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN) +#define BIT_SHIFT_MU_SCORETABLE_OFFSET 0 +#define BIT_MASK_MU_SCORETABLE_OFFSET 0x1ff +#define BIT_MU_SCORETABLE_OFFSET(x) \ + (((x) & BIT_MASK_MU_SCORETABLE_OFFSET) \ + << BIT_SHIFT_MU_SCORETABLE_OFFSET) +#define BITS_MU_SCORETABLE_OFFSET \ + (BIT_MASK_MU_SCORETABLE_OFFSET << BIT_SHIFT_MU_SCORETABLE_OFFSET) +#define BIT_CLEAR_MU_SCORETABLE_OFFSET(x) ((x) & (~BITS_MU_SCORETABLE_OFFSET)) +#define BIT_GET_MU_SCORETABLE_OFFSET(x) \ + (((x) >> BIT_SHIFT_MU_SCORETABLE_OFFSET) & \ + BIT_MASK_MU_SCORETABLE_OFFSET) +#define BIT_SET_MU_SCORETABLE_OFFSET(x, v) \ + (BIT_CLEAR_MU_SCORETABLE_OFFSET(x) | BIT_MU_SCORETABLE_OFFSET(v)) +#endif -/* 2 REG_DDMA_CH2SA (Offset 0x1220) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_Q2_Q3_INFO (Offset 0x1404) */ -#define BIT_SHIFT_DDMACH2_SA 0 -#define BIT_MASK_DDMACH2_SA 0xffffffffL -#define BIT_DDMACH2_SA(x) (((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA) -#define BIT_GET_DDMACH2_SA(x) (((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA) +#define BIT_SHIFT_AC3_PKT_INFO 16 +#define BIT_MASK_AC3_PKT_INFO 0xfff +#define BIT_AC3_PKT_INFO(x) \ + (((x) & BIT_MASK_AC3_PKT_INFO) << BIT_SHIFT_AC3_PKT_INFO) +#define BITS_AC3_PKT_INFO (BIT_MASK_AC3_PKT_INFO << BIT_SHIFT_AC3_PKT_INFO) +#define BIT_CLEAR_AC3_PKT_INFO(x) ((x) & (~BITS_AC3_PKT_INFO)) +#define BIT_GET_AC3_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC3_PKT_INFO) & BIT_MASK_AC3_PKT_INFO) +#define BIT_SET_AC3_PKT_INFO(x, v) \ + (BIT_CLEAR_AC3_PKT_INFO(x) | BIT_AC3_PKT_INFO(v)) + +#define BIT_SHIFT_AC2_PKT_INFO 0 +#define BIT_MASK_AC2_PKT_INFO 0xfff +#define BIT_AC2_PKT_INFO(x) \ + (((x) & BIT_MASK_AC2_PKT_INFO) << BIT_SHIFT_AC2_PKT_INFO) +#define BITS_AC2_PKT_INFO (BIT_MASK_AC2_PKT_INFO << BIT_SHIFT_AC2_PKT_INFO) +#define BIT_CLEAR_AC2_PKT_INFO(x) ((x) & (~BITS_AC2_PKT_INFO)) +#define BIT_GET_AC2_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC2_PKT_INFO) & BIT_MASK_AC2_PKT_INFO) +#define BIT_SET_AC2_PKT_INFO(x, v) \ + (BIT_CLEAR_AC2_PKT_INFO(x) | BIT_AC2_PKT_INFO(v)) +/* 2 REG_Q4_Q5_INFO (Offset 0x1408) */ -/* 2 REG_DDMA_CH2DA (Offset 0x1224) */ +#define BIT_SHIFT_AC5_PKT_INFO 16 +#define BIT_MASK_AC5_PKT_INFO 0xfff +#define BIT_AC5_PKT_INFO(x) \ + (((x) & BIT_MASK_AC5_PKT_INFO) << BIT_SHIFT_AC5_PKT_INFO) +#define BITS_AC5_PKT_INFO (BIT_MASK_AC5_PKT_INFO << BIT_SHIFT_AC5_PKT_INFO) +#define BIT_CLEAR_AC5_PKT_INFO(x) ((x) & (~BITS_AC5_PKT_INFO)) +#define BIT_GET_AC5_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC5_PKT_INFO) & BIT_MASK_AC5_PKT_INFO) +#define BIT_SET_AC5_PKT_INFO(x, v) \ + (BIT_CLEAR_AC5_PKT_INFO(x) | BIT_AC5_PKT_INFO(v)) +#define BIT_SHIFT_AC4_PKT_INFO 0 +#define BIT_MASK_AC4_PKT_INFO 0xfff +#define BIT_AC4_PKT_INFO(x) \ + (((x) & BIT_MASK_AC4_PKT_INFO) << BIT_SHIFT_AC4_PKT_INFO) +#define BITS_AC4_PKT_INFO (BIT_MASK_AC4_PKT_INFO << BIT_SHIFT_AC4_PKT_INFO) +#define BIT_CLEAR_AC4_PKT_INFO(x) ((x) & (~BITS_AC4_PKT_INFO)) +#define BIT_GET_AC4_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC4_PKT_INFO) & BIT_MASK_AC4_PKT_INFO) +#define BIT_SET_AC4_PKT_INFO(x, v) \ + (BIT_CLEAR_AC4_PKT_INFO(x) | BIT_AC4_PKT_INFO(v)) -#define BIT_SHIFT_DDMACH2_DA 0 -#define BIT_MASK_DDMACH2_DA 0xffffffffL -#define BIT_DDMACH2_DA(x) (((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA) -#define BIT_GET_DDMACH2_DA(x) (((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ +/* 2 REG_ARFR7 (Offset 0x1408) */ -#define BIT_DDMACH2_OWN BIT(31) -#define BIT_DDMACH2_CHKSUM_EN BIT(29) -#define BIT_DDMACH2_DA_W_DISABLE BIT(28) -#define BIT_DDMACH2_CHKSUM_STS BIT(27) -#define BIT_DDMACH2_DDMA_MODE BIT(26) -#define BIT_DDMACH2_RESET_CHKSUM_STS BIT(25) -#define BIT_DDMACH2_CHKSUM_CONT BIT(24) +#define BIT_SHIFT_ARFR7_V1 0 +#define BIT_MASK_ARFR7_V1 0xffffffffffffffffL +#define BIT_ARFR7_V1(x) (((x) & BIT_MASK_ARFR7_V1) << BIT_SHIFT_ARFR7_V1) +#define BITS_ARFR7_V1 (BIT_MASK_ARFR7_V1 << BIT_SHIFT_ARFR7_V1) +#define BIT_CLEAR_ARFR7_V1(x) ((x) & (~BITS_ARFR7_V1)) +#define BIT_GET_ARFR7_V1(x) (((x) >> BIT_SHIFT_ARFR7_V1) & BIT_MASK_ARFR7_V1) +#define BIT_SET_ARFR7_V1(x, v) (BIT_CLEAR_ARFR7_V1(x) | BIT_ARFR7_V1(v)) -#define BIT_SHIFT_DDMACH2_DLEN 0 -#define BIT_MASK_DDMACH2_DLEN 0x3ffff -#define BIT_DDMACH2_DLEN(x) (((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN) -#define BIT_GET_DDMACH2_DLEN(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DDMA_CH3SA (Offset 0x1230) */ +/* 2 REG_Q6_Q7_INFO (Offset 0x140C) */ +#define BIT_SHIFT_AC7_PKT_INFO 16 +#define BIT_MASK_AC7_PKT_INFO 0xfff +#define BIT_AC7_PKT_INFO(x) \ + (((x) & BIT_MASK_AC7_PKT_INFO) << BIT_SHIFT_AC7_PKT_INFO) +#define BITS_AC7_PKT_INFO (BIT_MASK_AC7_PKT_INFO << BIT_SHIFT_AC7_PKT_INFO) +#define BIT_CLEAR_AC7_PKT_INFO(x) ((x) & (~BITS_AC7_PKT_INFO)) +#define BIT_GET_AC7_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC7_PKT_INFO) & BIT_MASK_AC7_PKT_INFO) +#define BIT_SET_AC7_PKT_INFO(x, v) \ + (BIT_CLEAR_AC7_PKT_INFO(x) | BIT_AC7_PKT_INFO(v)) + +#define BIT_SHIFT_AC6_PKT_INFO 0 +#define BIT_MASK_AC6_PKT_INFO 0xfff +#define BIT_AC6_PKT_INFO(x) \ + (((x) & BIT_MASK_AC6_PKT_INFO) << BIT_SHIFT_AC6_PKT_INFO) +#define BITS_AC6_PKT_INFO (BIT_MASK_AC6_PKT_INFO << BIT_SHIFT_AC6_PKT_INFO) +#define BIT_CLEAR_AC6_PKT_INFO(x) ((x) & (~BITS_AC6_PKT_INFO)) +#define BIT_GET_AC6_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC6_PKT_INFO) & BIT_MASK_AC6_PKT_INFO) +#define BIT_SET_AC6_PKT_INFO(x, v) \ + (BIT_CLEAR_AC6_PKT_INFO(x) | BIT_AC6_PKT_INFO(v)) -#define BIT_SHIFT_DDMACH3_SA 0 -#define BIT_MASK_DDMACH3_SA 0xffffffffL -#define BIT_DDMACH3_SA(x) (((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA) -#define BIT_GET_DDMACH3_SA(x) (((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA) +/* 2 REG_MGQ_HIQ_INFO (Offset 0x1410) */ +#define BIT_SHIFT_HIQ_PKT_INFO 16 +#define BIT_MASK_HIQ_PKT_INFO 0xfff +#define BIT_HIQ_PKT_INFO(x) \ + (((x) & BIT_MASK_HIQ_PKT_INFO) << BIT_SHIFT_HIQ_PKT_INFO) +#define BITS_HIQ_PKT_INFO (BIT_MASK_HIQ_PKT_INFO << BIT_SHIFT_HIQ_PKT_INFO) +#define BIT_CLEAR_HIQ_PKT_INFO(x) ((x) & (~BITS_HIQ_PKT_INFO)) +#define BIT_GET_HIQ_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_HIQ_PKT_INFO) & BIT_MASK_HIQ_PKT_INFO) +#define BIT_SET_HIQ_PKT_INFO(x, v) \ + (BIT_CLEAR_HIQ_PKT_INFO(x) | BIT_HIQ_PKT_INFO(v)) + +#define BIT_SHIFT_MGQ_PKT_INFO 0 +#define BIT_MASK_MGQ_PKT_INFO 0xfff +#define BIT_MGQ_PKT_INFO(x) \ + (((x) & BIT_MASK_MGQ_PKT_INFO) << BIT_SHIFT_MGQ_PKT_INFO) +#define BITS_MGQ_PKT_INFO (BIT_MASK_MGQ_PKT_INFO << BIT_SHIFT_MGQ_PKT_INFO) +#define BIT_CLEAR_MGQ_PKT_INFO(x) ((x) & (~BITS_MGQ_PKT_INFO)) +#define BIT_GET_MGQ_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_MGQ_PKT_INFO) & BIT_MASK_MGQ_PKT_INFO) +#define BIT_SET_MGQ_PKT_INFO(x, v) \ + (BIT_CLEAR_MGQ_PKT_INFO(x) | BIT_MGQ_PKT_INFO(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_ARFR8 (Offset 0x1410) */ + +#define BIT_SHIFT_ARFR8_V1 0 +#define BIT_MASK_ARFR8_V1 0xffffffffffffffffL +#define BIT_ARFR8_V1(x) (((x) & BIT_MASK_ARFR8_V1) << BIT_SHIFT_ARFR8_V1) +#define BITS_ARFR8_V1 (BIT_MASK_ARFR8_V1 << BIT_SHIFT_ARFR8_V1) +#define BIT_CLEAR_ARFR8_V1(x) ((x) & (~BITS_ARFR8_V1)) +#define BIT_GET_ARFR8_V1(x) (((x) >> BIT_SHIFT_ARFR8_V1) & BIT_MASK_ARFR8_V1) +#define BIT_SET_ARFR8_V1(x, v) (BIT_CLEAR_ARFR8_V1(x) | BIT_ARFR8_V1(v)) + +#define BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER 0 +#define BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER 0xff +#define BIT_MEDIUM_HAS_IDLE_TRIGGER(x) \ + (((x) & BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER) \ + << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) +#define BITS_MEDIUM_HAS_IDLE_TRIGGER \ + (BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) +#define BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x) \ + ((x) & (~BITS_MEDIUM_HAS_IDLE_TRIGGER)) +#define BIT_GET_MEDIUM_HAS_IDLE_TRIGGER(x) \ + (((x) >> BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) & \ + BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER) +#define BIT_SET_MEDIUM_HAS_IDLE_TRIGGER(x, v) \ + (BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x) | BIT_MEDIUM_HAS_IDLE_TRIGGER(v)) -/* 2 REG_DDMA_CH3DA (Offset 0x1234) */ +#endif +#if (HALMAC_8197F_SUPPORT) -#define BIT_SHIFT_DDMACH3_DA 0 -#define BIT_MASK_DDMACH3_DA 0xffffffffL -#define BIT_DDMACH3_DA(x) (((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA) -#define BIT_GET_DDMACH3_DA(x) (((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA) +/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +#define BIT_SHIFT_BCNQ_PKT_INFO_V1 16 +#define BIT_MASK_BCNQ_PKT_INFO_V1 0xfff +#define BIT_BCNQ_PKT_INFO_V1(x) \ + (((x) & BIT_MASK_BCNQ_PKT_INFO_V1) << BIT_SHIFT_BCNQ_PKT_INFO_V1) +#define BITS_BCNQ_PKT_INFO_V1 \ + (BIT_MASK_BCNQ_PKT_INFO_V1 << BIT_SHIFT_BCNQ_PKT_INFO_V1) +#define BIT_CLEAR_BCNQ_PKT_INFO_V1(x) ((x) & (~BITS_BCNQ_PKT_INFO_V1)) +#define BIT_GET_BCNQ_PKT_INFO_V1(x) \ + (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1) & BIT_MASK_BCNQ_PKT_INFO_V1) +#define BIT_SET_BCNQ_PKT_INFO_V1(x, v) \ + (BIT_CLEAR_BCNQ_PKT_INFO_V1(x) | BIT_BCNQ_PKT_INFO_V1(v)) + +#define BIT_SHIFT_BCNERR_PORT_SEL 16 +#define BIT_MASK_BCNERR_PORT_SEL 0x7 +#define BIT_BCNERR_PORT_SEL(x) \ + (((x) & BIT_MASK_BCNERR_PORT_SEL) << BIT_SHIFT_BCNERR_PORT_SEL) +#define BITS_BCNERR_PORT_SEL \ + (BIT_MASK_BCNERR_PORT_SEL << BIT_SHIFT_BCNERR_PORT_SEL) +#define BIT_CLEAR_BCNERR_PORT_SEL(x) ((x) & (~BITS_BCNERR_PORT_SEL)) +#define BIT_GET_BCNERR_PORT_SEL(x) \ + (((x) >> BIT_SHIFT_BCNERR_PORT_SEL) & BIT_MASK_BCNERR_PORT_SEL) +#define BIT_SET_BCNERR_PORT_SEL(x, v) \ + (BIT_CLEAR_BCNERR_PORT_SEL(x) | BIT_BCNERR_PORT_SEL(v)) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ +/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ -#define BIT_DDMACH3_OWN BIT(31) -#define BIT_DDMACH3_CHKSUM_EN BIT(29) -#define BIT_DDMACH3_DA_W_DISABLE BIT(28) -#define BIT_DDMACH3_CHKSUM_STS BIT(27) -#define BIT_DDMACH3_DDMA_MODE BIT(26) -#define BIT_DDMACH3_RESET_CHKSUM_STS BIT(25) -#define BIT_DDMACH3_CHKSUM_CONT BIT(24) +#define BIT_SHIFT_CMDQ_PKT_INFO 16 +#define BIT_MASK_CMDQ_PKT_INFO 0xfff +#define BIT_CMDQ_PKT_INFO(x) \ + (((x) & BIT_MASK_CMDQ_PKT_INFO) << BIT_SHIFT_CMDQ_PKT_INFO) +#define BITS_CMDQ_PKT_INFO (BIT_MASK_CMDQ_PKT_INFO << BIT_SHIFT_CMDQ_PKT_INFO) +#define BIT_CLEAR_CMDQ_PKT_INFO(x) ((x) & (~BITS_CMDQ_PKT_INFO)) +#define BIT_GET_CMDQ_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_CMDQ_PKT_INFO) & BIT_MASK_CMDQ_PKT_INFO) +#define BIT_SET_CMDQ_PKT_INFO(x, v) \ + (BIT_CLEAR_CMDQ_PKT_INFO(x) | BIT_CMDQ_PKT_INFO(v)) -#define BIT_SHIFT_DDMACH3_DLEN 0 -#define BIT_MASK_DDMACH3_DLEN 0x3ffff -#define BIT_DDMACH3_DLEN(x) (((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN) -#define BIT_GET_DDMACH3_DLEN(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN) +#endif +#if (HALMAC_8197F_SUPPORT) -/* 2 REG_DDMA_CH4SA (Offset 0x1240) */ +/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +#define BIT_SHIFT_CMDQ_PKT_INFO_V1 0 +#define BIT_MASK_CMDQ_PKT_INFO_V1 0xfff +#define BIT_CMDQ_PKT_INFO_V1(x) \ + (((x) & BIT_MASK_CMDQ_PKT_INFO_V1) << BIT_SHIFT_CMDQ_PKT_INFO_V1) +#define BITS_CMDQ_PKT_INFO_V1 \ + (BIT_MASK_CMDQ_PKT_INFO_V1 << BIT_SHIFT_CMDQ_PKT_INFO_V1) +#define BIT_CLEAR_CMDQ_PKT_INFO_V1(x) ((x) & (~BITS_CMDQ_PKT_INFO_V1)) +#define BIT_GET_CMDQ_PKT_INFO_V1(x) \ + (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1) & BIT_MASK_CMDQ_PKT_INFO_V1) +#define BIT_SET_CMDQ_PKT_INFO_V1(x, v) \ + (BIT_CLEAR_CMDQ_PKT_INFO_V1(x) | BIT_CMDQ_PKT_INFO_V1(v)) -#define BIT_SHIFT_DDMACH4_SA 0 -#define BIT_MASK_DDMACH4_SA 0xffffffffL -#define BIT_DDMACH4_SA(x) (((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA) -#define BIT_GET_DDMACH4_SA(x) (((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DDMA_CH4DA (Offset 0x1244) */ +/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +#define BIT_SHIFT_BCNQ_PKT_INFO 0 +#define BIT_MASK_BCNQ_PKT_INFO 0xfff +#define BIT_BCNQ_PKT_INFO(x) \ + (((x) & BIT_MASK_BCNQ_PKT_INFO) << BIT_SHIFT_BCNQ_PKT_INFO) +#define BITS_BCNQ_PKT_INFO (BIT_MASK_BCNQ_PKT_INFO << BIT_SHIFT_BCNQ_PKT_INFO) +#define BIT_CLEAR_BCNQ_PKT_INFO(x) ((x) & (~BITS_BCNQ_PKT_INFO)) +#define BIT_GET_BCNQ_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_BCNQ_PKT_INFO) & BIT_MASK_BCNQ_PKT_INFO) +#define BIT_SET_BCNQ_PKT_INFO(x, v) \ + (BIT_CLEAR_BCNQ_PKT_INFO(x) | BIT_BCNQ_PKT_INFO(v)) -#define BIT_SHIFT_DDMACH4_DA 0 -#define BIT_MASK_DDMACH4_DA 0xffffffffL -#define BIT_DDMACH4_DA(x) (((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA) -#define BIT_GET_DDMACH4_DA(x) (((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ +/* 2 REG_USEREG_SETTING (Offset 0x1420) */ -#define BIT_DDMACH4_OWN BIT(31) -#define BIT_DDMACH4_CHKSUM_EN BIT(29) -#define BIT_DDMACH4_DA_W_DISABLE BIT(28) -#define BIT_DDMACH4_CHKSUM_STS BIT(27) -#define BIT_DDMACH4_DDMA_MODE BIT(26) -#define BIT_DDMACH4_RESET_CHKSUM_STS BIT(25) -#define BIT_DDMACH4_CHKSUM_CONT BIT(24) +#define BIT_NDPA_USEREG BIT(21) -#define BIT_SHIFT_DDMACH4_DLEN 0 -#define BIT_MASK_DDMACH4_DLEN 0x3ffff -#define BIT_DDMACH4_DLEN(x) (((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN) -#define BIT_GET_DDMACH4_DLEN(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN) +#define BIT_SHIFT_RETRY_USEREG 19 +#define BIT_MASK_RETRY_USEREG 0x3 +#define BIT_RETRY_USEREG(x) \ + (((x) & BIT_MASK_RETRY_USEREG) << BIT_SHIFT_RETRY_USEREG) +#define BITS_RETRY_USEREG (BIT_MASK_RETRY_USEREG << BIT_SHIFT_RETRY_USEREG) +#define BIT_CLEAR_RETRY_USEREG(x) ((x) & (~BITS_RETRY_USEREG)) +#define BIT_GET_RETRY_USEREG(x) \ + (((x) >> BIT_SHIFT_RETRY_USEREG) & BIT_MASK_RETRY_USEREG) +#define BIT_SET_RETRY_USEREG(x, v) \ + (BIT_CLEAR_RETRY_USEREG(x) | BIT_RETRY_USEREG(v)) +#define BIT_SHIFT_TRYPKT_USEREG 17 +#define BIT_MASK_TRYPKT_USEREG 0x3 +#define BIT_TRYPKT_USEREG(x) \ + (((x) & BIT_MASK_TRYPKT_USEREG) << BIT_SHIFT_TRYPKT_USEREG) +#define BITS_TRYPKT_USEREG (BIT_MASK_TRYPKT_USEREG << BIT_SHIFT_TRYPKT_USEREG) +#define BIT_CLEAR_TRYPKT_USEREG(x) ((x) & (~BITS_TRYPKT_USEREG)) +#define BIT_GET_TRYPKT_USEREG(x) \ + (((x) >> BIT_SHIFT_TRYPKT_USEREG) & BIT_MASK_TRYPKT_USEREG) +#define BIT_SET_TRYPKT_USEREG(x, v) \ + (BIT_CLEAR_TRYPKT_USEREG(x) | BIT_TRYPKT_USEREG(v)) -/* 2 REG_DDMA_CH5SA (Offset 0x1250) */ +#define BIT_CTLPKT_USEREG BIT(16) +#endif -#define BIT_SHIFT_DDMACH5_SA 0 -#define BIT_MASK_DDMACH5_SA 0xffffffffL -#define BIT_DDMACH5_SA(x) (((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA) -#define BIT_GET_DDMACH5_SA(x) (((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_AESIV_SETTING (Offset 0x1424) */ -/* 2 REG_DDMA_CH5DA (Offset 0x1254) */ +#define BIT_SHIFT_AESIV_OFFSET 0 +#define BIT_MASK_AESIV_OFFSET 0xfff +#define BIT_AESIV_OFFSET(x) \ + (((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET) +#define BITS_AESIV_OFFSET (BIT_MASK_AESIV_OFFSET << BIT_SHIFT_AESIV_OFFSET) +#define BIT_CLEAR_AESIV_OFFSET(x) ((x) & (~BITS_AESIV_OFFSET)) +#define BIT_GET_AESIV_OFFSET(x) \ + (((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET) +#define BIT_SET_AESIV_OFFSET(x, v) \ + (BIT_CLEAR_AESIV_OFFSET(x) | BIT_AESIV_OFFSET(v)) -#define BIT_DDMACH5_OWN BIT(31) -#define BIT_DDMACH5_CHKSUM_EN BIT(29) -#define BIT_DDMACH5_DA_W_DISABLE BIT(28) -#define BIT_DDMACH5_CHKSUM_STS BIT(27) -#define BIT_DDMACH5_DDMA_MODE BIT(26) -#define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25) -#define BIT_DDMACH5_CHKSUM_CONT BIT(24) +#endif -#define BIT_SHIFT_DDMACH5_DA 0 -#define BIT_MASK_DDMACH5_DA 0xffffffffL -#define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA) -#define BIT_GET_DDMACH5_DA(x) (((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_BF0_TIME_SETTING (Offset 0x1428) */ -#define BIT_SHIFT_DDMACH5_DLEN 0 -#define BIT_MASK_DDMACH5_DLEN 0x3ffff -#define BIT_DDMACH5_DLEN(x) (((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN) -#define BIT_GET_DDMACH5_DLEN(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN) +#define BIT_BF0_TIMER_SET BIT(31) +#define BIT_BF0_TIMER_CLR BIT(30) +#define BIT_BF0_UPDATE_EN BIT(29) +#define BIT_BF0_TIMER_EN BIT(28) + +#define BIT_SHIFT_BF0_PRETIME_OVER 16 +#define BIT_MASK_BF0_PRETIME_OVER 0xfff +#define BIT_BF0_PRETIME_OVER(x) \ + (((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER) +#define BITS_BF0_PRETIME_OVER \ + (BIT_MASK_BF0_PRETIME_OVER << BIT_SHIFT_BF0_PRETIME_OVER) +#define BIT_CLEAR_BF0_PRETIME_OVER(x) ((x) & (~BITS_BF0_PRETIME_OVER)) +#define BIT_GET_BF0_PRETIME_OVER(x) \ + (((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER) +#define BIT_SET_BF0_PRETIME_OVER(x, v) \ + (BIT_CLEAR_BF0_PRETIME_OVER(x) | BIT_BF0_PRETIME_OVER(v)) + +#define BIT_SHIFT_BF0_LIFETIME 0 +#define BIT_MASK_BF0_LIFETIME 0xffff +#define BIT_BF0_LIFETIME(x) \ + (((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME) +#define BITS_BF0_LIFETIME (BIT_MASK_BF0_LIFETIME << BIT_SHIFT_BF0_LIFETIME) +#define BIT_CLEAR_BF0_LIFETIME(x) ((x) & (~BITS_BF0_LIFETIME)) +#define BIT_GET_BF0_LIFETIME(x) \ + (((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME) +#define BIT_SET_BF0_LIFETIME(x, v) \ + (BIT_CLEAR_BF0_LIFETIME(x) | BIT_BF0_LIFETIME(v)) +/* 2 REG_BF1_TIME_SETTING (Offset 0x142C) */ -/* 2 REG_DDMA_INT_MSK (Offset 0x12E0) */ +#define BIT_BF1_TIMER_SET BIT(31) +#define BIT_BF1_TIMER_CLR BIT(30) +#define BIT_BF1_UPDATE_EN BIT(29) +#define BIT_BF1_TIMER_EN BIT(28) + +#define BIT_SHIFT_BF1_PRETIME_OVER 16 +#define BIT_MASK_BF1_PRETIME_OVER 0xfff +#define BIT_BF1_PRETIME_OVER(x) \ + (((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER) +#define BITS_BF1_PRETIME_OVER \ + (BIT_MASK_BF1_PRETIME_OVER << BIT_SHIFT_BF1_PRETIME_OVER) +#define BIT_CLEAR_BF1_PRETIME_OVER(x) ((x) & (~BITS_BF1_PRETIME_OVER)) +#define BIT_GET_BF1_PRETIME_OVER(x) \ + (((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER) +#define BIT_SET_BF1_PRETIME_OVER(x, v) \ + (BIT_CLEAR_BF1_PRETIME_OVER(x) | BIT_BF1_PRETIME_OVER(v)) + +#define BIT_SHIFT_BF1_LIFETIME 0 +#define BIT_MASK_BF1_LIFETIME 0xffff +#define BIT_BF1_LIFETIME(x) \ + (((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME) +#define BITS_BF1_LIFETIME (BIT_MASK_BF1_LIFETIME << BIT_SHIFT_BF1_LIFETIME) +#define BIT_CLEAR_BF1_LIFETIME(x) ((x) & (~BITS_BF1_LIFETIME)) +#define BIT_GET_BF1_LIFETIME(x) \ + (((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME) +#define BIT_SET_BF1_LIFETIME(x, v) \ + (BIT_CLEAR_BF1_LIFETIME(x) | BIT_BF1_LIFETIME(v)) -#define BIT_DDMACH5_MSK BIT(5) -#define BIT_DDMACH4_MSK BIT(4) -#define BIT_DDMACH3_MSK BIT(3) -#define BIT_DDMACH2_MSK BIT(2) -#define BIT_DDMACH1_MSK BIT(1) -#define BIT_DDMACH0_MSK BIT(0) +/* 2 REG_BF_TIMEOUT_EN (Offset 0x1430) */ -/* 2 REG_DDMA_CHSTATUS (Offset 0x12E8) */ +#define BIT_EN_VHT_LDPC BIT(9) +#define BIT_EN_HT_LDPC BIT(8) +#define BIT_BF1_TIMEOUT_EN BIT(1) +#define BIT_BF0_TIMEOUT_EN BIT(0) -#define BIT_DDMACH5_BUSY BIT(5) -#define BIT_DDMACH4_BUSY BIT(4) -#define BIT_DDMACH3_BUSY BIT(3) -#define BIT_DDMACH2_BUSY BIT(2) -#define BIT_DDMACH1_BUSY BIT(1) -#define BIT_DDMACH0_BUSY BIT(0) +#endif -/* 2 REG_DDMA_CHKSUM (Offset 0x12F0) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_MACID_RELEASE0 (Offset 0x1434) */ +#define BIT_SHIFT_MACID31_0_RELEASE 0 +#define BIT_MASK_MACID31_0_RELEASE 0xffffffffL +#define BIT_MACID31_0_RELEASE(x) \ + (((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE) +#define BITS_MACID31_0_RELEASE \ + (BIT_MASK_MACID31_0_RELEASE << BIT_SHIFT_MACID31_0_RELEASE) +#define BIT_CLEAR_MACID31_0_RELEASE(x) ((x) & (~BITS_MACID31_0_RELEASE)) +#define BIT_GET_MACID31_0_RELEASE(x) \ + (((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE) +#define BIT_SET_MACID31_0_RELEASE(x, v) \ + (BIT_CLEAR_MACID31_0_RELEASE(x) | BIT_MACID31_0_RELEASE(v)) -#define BIT_SHIFT_IDDMA0_CHKSUM 0 -#define BIT_MASK_IDDMA0_CHKSUM 0xffff -#define BIT_IDDMA0_CHKSUM(x) (((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM) -#define BIT_GET_IDDMA0_CHKSUM(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_DDMA_MONITOR (Offset 0x12FC) */ +/* 2 REG_MACID_RELEASE_INFO (Offset 0x1434) */ -#define BIT_IDDMA0_PERMU_UNDERFLOW BIT(14) -#define BIT_IDDMA0_FIFO_UNDERFLOW BIT(13) -#define BIT_IDDMA0_FIFO_OVERFLOW BIT(12) -#define BIT_ECRC_EN_V1 BIT(7) -#define BIT_MDIO_RFLAG_V1 BIT(6) -#define BIT_CH5_ERR BIT(5) -#define BIT_MDIO_WFLAG_V1 BIT(5) -#define BIT_CH4_ERR BIT(4) -#define BIT_CH3_ERR BIT(3) -#define BIT_CH2_ERR BIT(2) -#define BIT_CH1_ERR BIT(1) -#define BIT_CH0_ERR BIT(0) +#define BIT_SHIFT_MACID_RELEASE_INFO 0 +#define BIT_MASK_MACID_RELEASE_INFO 0xffffffffL +#define BIT_MACID_RELEASE_INFO(x) \ + (((x) & BIT_MASK_MACID_RELEASE_INFO) << BIT_SHIFT_MACID_RELEASE_INFO) +#define BITS_MACID_RELEASE_INFO \ + (BIT_MASK_MACID_RELEASE_INFO << BIT_SHIFT_MACID_RELEASE_INFO) +#define BIT_CLEAR_MACID_RELEASE_INFO(x) ((x) & (~BITS_MACID_RELEASE_INFO)) +#define BIT_GET_MACID_RELEASE_INFO(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_INFO) & BIT_MASK_MACID_RELEASE_INFO) +#define BIT_SET_MACID_RELEASE_INFO(x, v) \ + (BIT_CLEAR_MACID_RELEASE_INFO(x) | BIT_MACID_RELEASE_INFO(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MACID_RELEASE1 (Offset 0x1438) */ +#define BIT_SHIFT_MACID63_32_RELEASE 0 +#define BIT_MASK_MACID63_32_RELEASE 0xffffffffL +#define BIT_MACID63_32_RELEASE(x) \ + (((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE) +#define BITS_MACID63_32_RELEASE \ + (BIT_MASK_MACID63_32_RELEASE << BIT_SHIFT_MACID63_32_RELEASE) +#define BIT_CLEAR_MACID63_32_RELEASE(x) ((x) & (~BITS_MACID63_32_RELEASE)) +#define BIT_GET_MACID63_32_RELEASE(x) \ + (((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE) +#define BIT_SET_MACID63_32_RELEASE(x, v) \ + (BIT_CLEAR_MACID63_32_RELEASE(x) | BIT_MACID63_32_RELEASE(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_MACID_RELEASE_SUCCESS_INFO (Offset 0x1438) */ + +#define BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO 0 +#define BIT_MASK_MACID_RELEASE_SUCCESS_INFO 0xffffffffL +#define BIT_MACID_RELEASE_SUCCESS_INFO(x) \ + (((x) & BIT_MASK_MACID_RELEASE_SUCCESS_INFO) \ + << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO) +#define BITS_MACID_RELEASE_SUCCESS_INFO \ + (BIT_MASK_MACID_RELEASE_SUCCESS_INFO \ + << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO) +#define BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO(x) \ + ((x) & (~BITS_MACID_RELEASE_SUCCESS_INFO)) +#define BIT_GET_MACID_RELEASE_SUCCESS_INFO(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO) & \ + BIT_MASK_MACID_RELEASE_SUCCESS_INFO) +#define BIT_SET_MACID_RELEASE_SUCCESS_INFO(x, v) \ + (BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO(x) | \ + BIT_MACID_RELEASE_SUCCESS_INFO(v)) + +/* 2 REG_MACID_RELEASE_CTRL (Offset 0x143C) */ + +#define BIT_SHIFT_MACID_RELEASE_SEL 24 +#define BIT_MASK_MACID_RELEASE_SEL 0x7 +#define BIT_MACID_RELEASE_SEL(x) \ + (((x) & BIT_MASK_MACID_RELEASE_SEL) << BIT_SHIFT_MACID_RELEASE_SEL) +#define BITS_MACID_RELEASE_SEL \ + (BIT_MASK_MACID_RELEASE_SEL << BIT_SHIFT_MACID_RELEASE_SEL) +#define BIT_CLEAR_MACID_RELEASE_SEL(x) ((x) & (~BITS_MACID_RELEASE_SEL)) +#define BIT_GET_MACID_RELEASE_SEL(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_SEL) & BIT_MASK_MACID_RELEASE_SEL) +#define BIT_SET_MACID_RELEASE_SEL(x, v) \ + (BIT_CLEAR_MACID_RELEASE_SEL(x) | BIT_MACID_RELEASE_SEL(v)) + +#define BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET 16 +#define BIT_MASK_MACID_RELEASE_CLEAR_OFFSET 0xff +#define BIT_MACID_RELEASE_CLEAR_OFFSET(x) \ + (((x) & BIT_MASK_MACID_RELEASE_CLEAR_OFFSET) \ + << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET) +#define BITS_MACID_RELEASE_CLEAR_OFFSET \ + (BIT_MASK_MACID_RELEASE_CLEAR_OFFSET \ + << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET) +#define BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET(x) \ + ((x) & (~BITS_MACID_RELEASE_CLEAR_OFFSET)) +#define BIT_GET_MACID_RELEASE_CLEAR_OFFSET(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET) & \ + BIT_MASK_MACID_RELEASE_CLEAR_OFFSET) +#define BIT_SET_MACID_RELEASE_CLEAR_OFFSET(x, v) \ + (BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET(x) | \ + BIT_MACID_RELEASE_CLEAR_OFFSET(v)) + +#define BIT_MACID_RELEASE_VALUE BIT(8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_STC_INT_CS (Offset 0x1300) */ +/* 2 REG_MACID_RELEASE2 (Offset 0x143C) */ + +#define BIT_SHIFT_MACID95_64_RELEASE 0 +#define BIT_MASK_MACID95_64_RELEASE 0xffffffffL +#define BIT_MACID95_64_RELEASE(x) \ + (((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE) +#define BITS_MACID95_64_RELEASE \ + (BIT_MASK_MACID95_64_RELEASE << BIT_SHIFT_MACID95_64_RELEASE) +#define BIT_CLEAR_MACID95_64_RELEASE(x) ((x) & (~BITS_MACID95_64_RELEASE)) +#define BIT_GET_MACID95_64_RELEASE(x) \ + (((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE) +#define BIT_SET_MACID95_64_RELEASE(x, v) \ + (BIT_CLEAR_MACID95_64_RELEASE(x) | BIT_MACID95_64_RELEASE(v)) -#define BIT_STC_INT_EN BIT(31) +#endif -#define BIT_SHIFT_STC_INT_FLAG 16 -#define BIT_MASK_STC_INT_FLAG 0xff -#define BIT_STC_INT_FLAG(x) (((x) & BIT_MASK_STC_INT_FLAG) << BIT_SHIFT_STC_INT_FLAG) -#define BIT_GET_STC_INT_FLAG(x) (((x) >> BIT_SHIFT_STC_INT_FLAG) & BIT_MASK_STC_INT_FLAG) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_MACID_RELEASE_CTRL (Offset 0x143C) */ -#define BIT_SHIFT_STC_INT_IDX 8 -#define BIT_MASK_STC_INT_IDX 0x7 -#define BIT_STC_INT_IDX(x) (((x) & BIT_MASK_STC_INT_IDX) << BIT_SHIFT_STC_INT_IDX) -#define BIT_GET_STC_INT_IDX(x) (((x) >> BIT_SHIFT_STC_INT_IDX) & BIT_MASK_STC_INT_IDX) +#define BIT_SHIFT_MACID_RELEASE_OFFSET 0 +#define BIT_MASK_MACID_RELEASE_OFFSET 0xff +#define BIT_MACID_RELEASE_OFFSET(x) \ + (((x) & BIT_MASK_MACID_RELEASE_OFFSET) \ + << BIT_SHIFT_MACID_RELEASE_OFFSET) +#define BITS_MACID_RELEASE_OFFSET \ + (BIT_MASK_MACID_RELEASE_OFFSET << BIT_SHIFT_MACID_RELEASE_OFFSET) +#define BIT_CLEAR_MACID_RELEASE_OFFSET(x) ((x) & (~BITS_MACID_RELEASE_OFFSET)) +#define BIT_GET_MACID_RELEASE_OFFSET(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_OFFSET) & \ + BIT_MASK_MACID_RELEASE_OFFSET) +#define BIT_SET_MACID_RELEASE_OFFSET(x, v) \ + (BIT_CLEAR_MACID_RELEASE_OFFSET(x) | BIT_MACID_RELEASE_OFFSET(v)) +#endif -#define BIT_SHIFT_STC_INT_REALTIME_CS 0 -#define BIT_MASK_STC_INT_REALTIME_CS 0x3f -#define BIT_STC_INT_REALTIME_CS(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS) << BIT_SHIFT_STC_INT_REALTIME_CS) -#define BIT_GET_STC_INT_REALTIME_CS(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS) & BIT_MASK_STC_INT_REALTIME_CS) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_MACID_RELEASE3 (Offset 0x1440) */ -/* 2 REG_ST_INT_CFG (Offset 0x1304) */ +#define BIT_SHIFT_MACID127_96_RELEASE 0 +#define BIT_MASK_MACID127_96_RELEASE 0xffffffffL +#define BIT_MACID127_96_RELEASE(x) \ + (((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE) +#define BITS_MACID127_96_RELEASE \ + (BIT_MASK_MACID127_96_RELEASE << BIT_SHIFT_MACID127_96_RELEASE) +#define BIT_CLEAR_MACID127_96_RELEASE(x) ((x) & (~BITS_MACID127_96_RELEASE)) +#define BIT_GET_MACID127_96_RELEASE(x) \ + (((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE) +#define BIT_SET_MACID127_96_RELEASE(x, v) \ + (BIT_CLEAR_MACID127_96_RELEASE(x) | BIT_MACID127_96_RELEASE(v)) -#define BIT_STC_INT_GRP_EN BIT(31) +/* 2 REG_MACID_RELEASE_SETTING (Offset 0x1444) */ -#define BIT_SHIFT_STC_INT_EXPECT_LS 8 -#define BIT_MASK_STC_INT_EXPECT_LS 0x3f -#define BIT_STC_INT_EXPECT_LS(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS) << BIT_SHIFT_STC_INT_EXPECT_LS) -#define BIT_GET_STC_INT_EXPECT_LS(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS) & BIT_MASK_STC_INT_EXPECT_LS) +#define BIT_MACID_VALUE BIT(7) +#define BIT_SHIFT_MACID_OFFSET 0 +#define BIT_MASK_MACID_OFFSET 0x7f +#define BIT_MACID_OFFSET(x) \ + (((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET) +#define BITS_MACID_OFFSET (BIT_MASK_MACID_OFFSET << BIT_SHIFT_MACID_OFFSET) +#define BIT_CLEAR_MACID_OFFSET(x) ((x) & (~BITS_MACID_OFFSET)) +#define BIT_GET_MACID_OFFSET(x) \ + (((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET) +#define BIT_SET_MACID_OFFSET(x, v) \ + (BIT_CLEAR_MACID_OFFSET(x) | BIT_MACID_OFFSET(v)) -#define BIT_SHIFT_STC_INT_EXPECT_CS 0 -#define BIT_MASK_STC_INT_EXPECT_CS 0x3f -#define BIT_STC_INT_EXPECT_CS(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS) << BIT_SHIFT_STC_INT_EXPECT_CS) -#define BIT_GET_STC_INT_EXPECT_CS(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS) & BIT_MASK_STC_INT_EXPECT_CS) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_CMU_DLY_CTRL (Offset 0x1310) */ +/* 2 REG_FAST_EDCA_VOVI_SETTING (Offset 0x1448) */ -#define BIT_CMU_DLY_EN BIT(31) -#define BIT_CMU_DLY_MODE BIT(30) +#define BIT_SHIFT_VI_FAST_EDCA_TO 24 +#define BIT_MASK_VI_FAST_EDCA_TO 0xff +#define BIT_VI_FAST_EDCA_TO(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO) +#define BITS_VI_FAST_EDCA_TO \ + (BIT_MASK_VI_FAST_EDCA_TO << BIT_SHIFT_VI_FAST_EDCA_TO) +#define BIT_CLEAR_VI_FAST_EDCA_TO(x) ((x) & (~BITS_VI_FAST_EDCA_TO)) +#define BIT_GET_VI_FAST_EDCA_TO(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO) +#define BIT_SET_VI_FAST_EDCA_TO(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_TO(x) | BIT_VI_FAST_EDCA_TO(v)) + +#define BIT_VI_THRESHOLD_SEL BIT(23) + +#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH 16 +#define BIT_MASK_VI_FAST_EDCA_PKT_TH 0x7f +#define BIT_VI_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH) +#define BITS_VI_FAST_EDCA_PKT_TH \ + (BIT_MASK_VI_FAST_EDCA_PKT_TH << BIT_SHIFT_VI_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_VI_FAST_EDCA_PKT_TH)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH) +#define BIT_SET_VI_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) | BIT_VI_FAST_EDCA_PKT_TH(v)) + +#define BIT_SHIFT_VO_FAST_EDCA_TO 8 +#define BIT_MASK_VO_FAST_EDCA_TO 0xff +#define BIT_VO_FAST_EDCA_TO(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO) +#define BITS_VO_FAST_EDCA_TO \ + (BIT_MASK_VO_FAST_EDCA_TO << BIT_SHIFT_VO_FAST_EDCA_TO) +#define BIT_CLEAR_VO_FAST_EDCA_TO(x) ((x) & (~BITS_VO_FAST_EDCA_TO)) +#define BIT_GET_VO_FAST_EDCA_TO(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO) +#define BIT_SET_VO_FAST_EDCA_TO(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO(x) | BIT_VO_FAST_EDCA_TO(v)) + +#define BIT_VO_THRESHOLD_SEL BIT(7) + +#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH 0 +#define BIT_MASK_VO_FAST_EDCA_PKT_TH 0x7f +#define BIT_VO_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH) +#define BITS_VO_FAST_EDCA_PKT_TH \ + (BIT_MASK_VO_FAST_EDCA_PKT_TH << BIT_SHIFT_VO_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_VO_FAST_EDCA_PKT_TH)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH) +#define BIT_SET_VO_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) | BIT_VO_FAST_EDCA_PKT_TH(v)) -#define BIT_SHIFT_CMU_DLY_PRE_DIV 0 -#define BIT_MASK_CMU_DLY_PRE_DIV 0xff -#define BIT_CMU_DLY_PRE_DIV(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV) << BIT_SHIFT_CMU_DLY_PRE_DIV) -#define BIT_GET_CMU_DLY_PRE_DIV(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV) & BIT_MASK_CMU_DLY_PRE_DIV) +/* 2 REG_FAST_EDCA_BEBK_SETTING (Offset 0x144C) */ +#define BIT_SHIFT_BK_FAST_EDCA_TO 24 +#define BIT_MASK_BK_FAST_EDCA_TO 0xff +#define BIT_BK_FAST_EDCA_TO(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO) +#define BITS_BK_FAST_EDCA_TO \ + (BIT_MASK_BK_FAST_EDCA_TO << BIT_SHIFT_BK_FAST_EDCA_TO) +#define BIT_CLEAR_BK_FAST_EDCA_TO(x) ((x) & (~BITS_BK_FAST_EDCA_TO)) +#define BIT_GET_BK_FAST_EDCA_TO(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO) +#define BIT_SET_BK_FAST_EDCA_TO(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_TO(x) | BIT_BK_FAST_EDCA_TO(v)) + +#define BIT_BK_THRESHOLD_SEL BIT(23) + +#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH 16 +#define BIT_MASK_BK_FAST_EDCA_PKT_TH 0x7f +#define BIT_BK_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH) +#define BITS_BK_FAST_EDCA_PKT_TH \ + (BIT_MASK_BK_FAST_EDCA_PKT_TH << BIT_SHIFT_BK_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_BK_FAST_EDCA_PKT_TH)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH) +#define BIT_SET_BK_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) | BIT_BK_FAST_EDCA_PKT_TH(v)) + +#define BIT_SHIFT_BE_FAST_EDCA_TO 8 +#define BIT_MASK_BE_FAST_EDCA_TO 0xff +#define BIT_BE_FAST_EDCA_TO(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO) +#define BITS_BE_FAST_EDCA_TO \ + (BIT_MASK_BE_FAST_EDCA_TO << BIT_SHIFT_BE_FAST_EDCA_TO) +#define BIT_CLEAR_BE_FAST_EDCA_TO(x) ((x) & (~BITS_BE_FAST_EDCA_TO)) +#define BIT_GET_BE_FAST_EDCA_TO(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO) +#define BIT_SET_BE_FAST_EDCA_TO(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO(x) | BIT_BE_FAST_EDCA_TO(v)) + +#define BIT_BE_THRESHOLD_SEL BIT(7) +#define BIT_EN_P2P_CTWINDOW BIT(1) + +#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH 0 +#define BIT_MASK_BE_FAST_EDCA_PKT_TH 0x7f +#define BIT_BE_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH) +#define BITS_BE_FAST_EDCA_PKT_TH \ + (BIT_MASK_BE_FAST_EDCA_PKT_TH << BIT_SHIFT_BE_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_BE_FAST_EDCA_PKT_TH)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH) +#define BIT_SET_BE_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) | BIT_BE_FAST_EDCA_PKT_TH(v)) + +#define BIT_EN_P2P_BCNQ_AREA BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_CMU_DLY_CFG (Offset 0x1314) */ +/* 2 REG_MACID_DROP0 (Offset 0x1450) */ +#define BIT_SHIFT_MACID31_0_DROP 0 +#define BIT_MASK_MACID31_0_DROP 0xffffffffL +#define BIT_MACID31_0_DROP(x) \ + (((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP) +#define BITS_MACID31_0_DROP \ + (BIT_MASK_MACID31_0_DROP << BIT_SHIFT_MACID31_0_DROP) +#define BIT_CLEAR_MACID31_0_DROP(x) ((x) & (~BITS_MACID31_0_DROP)) +#define BIT_GET_MACID31_0_DROP(x) \ + (((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP) +#define BIT_SET_MACID31_0_DROP(x, v) \ + (BIT_CLEAR_MACID31_0_DROP(x) | BIT_MACID31_0_DROP(v)) -#define BIT_SHIFT_CMU_DLY_LTR_A2I 24 -#define BIT_MASK_CMU_DLY_LTR_A2I 0xff -#define BIT_CMU_DLY_LTR_A2I(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I) << BIT_SHIFT_CMU_DLY_LTR_A2I) -#define BIT_GET_CMU_DLY_LTR_A2I(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I) & BIT_MASK_CMU_DLY_LTR_A2I) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_CMU_DLY_LTR_I2A 16 -#define BIT_MASK_CMU_DLY_LTR_I2A 0xff -#define BIT_CMU_DLY_LTR_I2A(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A) << BIT_SHIFT_CMU_DLY_LTR_I2A) -#define BIT_GET_CMU_DLY_LTR_I2A(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A) & BIT_MASK_CMU_DLY_LTR_I2A) +/* 2 REG_MACID_DROP_INFO (Offset 0x1450) */ +#define BIT_SHIFT_MACID_DROP_INFO 0 +#define BIT_MASK_MACID_DROP_INFO 0xffffffffL +#define BIT_MACID_DROP_INFO(x) \ + (((x) & BIT_MASK_MACID_DROP_INFO) << BIT_SHIFT_MACID_DROP_INFO) +#define BITS_MACID_DROP_INFO \ + (BIT_MASK_MACID_DROP_INFO << BIT_SHIFT_MACID_DROP_INFO) +#define BIT_CLEAR_MACID_DROP_INFO(x) ((x) & (~BITS_MACID_DROP_INFO)) +#define BIT_GET_MACID_DROP_INFO(x) \ + (((x) >> BIT_SHIFT_MACID_DROP_INFO) & BIT_MASK_MACID_DROP_INFO) +#define BIT_SET_MACID_DROP_INFO(x, v) \ + (BIT_CLEAR_MACID_DROP_INFO(x) | BIT_MACID_DROP_INFO(v)) -#define BIT_SHIFT_CMU_DLY_LTR_IDLE 8 -#define BIT_MASK_CMU_DLY_LTR_IDLE 0xff -#define BIT_CMU_DLY_LTR_IDLE(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE) << BIT_SHIFT_CMU_DLY_LTR_IDLE) -#define BIT_GET_CMU_DLY_LTR_IDLE(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE) & BIT_MASK_CMU_DLY_LTR_IDLE) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_CMU_DLY_LTR_ACT 0 -#define BIT_MASK_CMU_DLY_LTR_ACT 0xff -#define BIT_CMU_DLY_LTR_ACT(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT) << BIT_SHIFT_CMU_DLY_LTR_ACT) -#define BIT_GET_CMU_DLY_LTR_ACT(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT) & BIT_MASK_CMU_DLY_LTR_ACT) +/* 2 REG_MACID_DROP1 (Offset 0x1454) */ +#define BIT_SHIFT_MACID63_32_DROP 0 +#define BIT_MASK_MACID63_32_DROP 0xffffffffL +#define BIT_MACID63_32_DROP(x) \ + (((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP) +#define BITS_MACID63_32_DROP \ + (BIT_MASK_MACID63_32_DROP << BIT_SHIFT_MACID63_32_DROP) +#define BIT_CLEAR_MACID63_32_DROP(x) ((x) & (~BITS_MACID63_32_DROP)) +#define BIT_GET_MACID63_32_DROP(x) \ + (((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP) +#define BIT_SET_MACID63_32_DROP(x, v) \ + (BIT_CLEAR_MACID63_32_DROP(x) | BIT_MACID63_32_DROP(v)) -/* 2 REG_H2CQ_TXBD_DESA (Offset 0x1320) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_H2CQ_TXBD_DESA 0 -#define BIT_MASK_H2CQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_H2CQ_TXBD_DESA(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA) << BIT_SHIFT_H2CQ_TXBD_DESA) -#define BIT_GET_H2CQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA) & BIT_MASK_H2CQ_TXBD_DESA) +/* 2 REG_MACID_DROP_CTRL (Offset 0x1454) */ +#define BIT_SHIFT_MACID_DROP_SEL 0 +#define BIT_MASK_MACID_DROP_SEL 0x7 +#define BIT_MACID_DROP_SEL(x) \ + (((x) & BIT_MASK_MACID_DROP_SEL) << BIT_SHIFT_MACID_DROP_SEL) +#define BITS_MACID_DROP_SEL \ + (BIT_MASK_MACID_DROP_SEL << BIT_SHIFT_MACID_DROP_SEL) +#define BIT_CLEAR_MACID_DROP_SEL(x) ((x) & (~BITS_MACID_DROP_SEL)) +#define BIT_GET_MACID_DROP_SEL(x) \ + (((x) >> BIT_SHIFT_MACID_DROP_SEL) & BIT_MASK_MACID_DROP_SEL) +#define BIT_SET_MACID_DROP_SEL(x, v) \ + (BIT_CLEAR_MACID_DROP_SEL(x) | BIT_MACID_DROP_SEL(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_MACID_DROP2 (Offset 0x1458) */ +#define BIT_SHIFT_MACID95_64_DROP 0 +#define BIT_MASK_MACID95_64_DROP 0xffffffffL +#define BIT_MACID95_64_DROP(x) \ + (((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP) +#define BITS_MACID95_64_DROP \ + (BIT_MASK_MACID95_64_DROP << BIT_SHIFT_MACID95_64_DROP) +#define BIT_CLEAR_MACID95_64_DROP(x) ((x) & (~BITS_MACID95_64_DROP)) +#define BIT_GET_MACID95_64_DROP(x) \ + (((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP) +#define BIT_SET_MACID95_64_DROP(x, v) \ + (BIT_CLEAR_MACID95_64_DROP(x) | BIT_MACID95_64_DROP(v)) -/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ +/* 2 REG_MACID_DROP3 (Offset 0x145C) */ -#define BIT_HCI_H2CQ_FLAG BIT(14) +#define BIT_SHIFT_MACID127_96_DROP 0 +#define BIT_MASK_MACID127_96_DROP 0xffffffffL +#define BIT_MACID127_96_DROP(x) \ + (((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP) +#define BITS_MACID127_96_DROP \ + (BIT_MASK_MACID127_96_DROP << BIT_SHIFT_MACID127_96_DROP) +#define BIT_CLEAR_MACID127_96_DROP(x) ((x) & (~BITS_MACID127_96_DROP)) +#define BIT_GET_MACID127_96_DROP(x) \ + (((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP) +#define BIT_SET_MACID127_96_DROP(x, v) \ + (BIT_CLEAR_MACID127_96_DROP(x) | BIT_MACID127_96_DROP(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_R_MACID_RELEASE_SUCCESS_0 (Offset 0x1460) */ +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_0(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) +#define BITS_R_MACID_RELEASE_SUCCESS_0 \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_0 \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_0) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_0(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_0(v)) -/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ +/* 2 REG_R_MACID_RELEASE_SUCCESS_1 (Offset 0x1464) */ -#define BIT_PCIE_H2CQ_FLAG BIT(14) +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_1(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) +#define BITS_R_MACID_RELEASE_SUCCESS_1 \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_1 \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_1) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_1(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_1(v)) -#endif +/* 2 REG_R_MACID_RELEASE_SUCCESS_2 (Offset 0x1468) */ +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_2(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) +#define BITS_R_MACID_RELEASE_SUCCESS_2 \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_2 \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_2) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_2(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_2(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_R_MACID_RELEASE_SUCCESS_3 (Offset 0x146C) */ +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_3(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) +#define BITS_R_MACID_RELEASE_SUCCESS_3 \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_3 \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_3) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_3(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_3(v)) -/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_H2CQ_DESC_MODE 12 -#define BIT_MASK_H2CQ_DESC_MODE 0x3 -#define BIT_H2CQ_DESC_MODE(x) (((x) & BIT_MASK_H2CQ_DESC_MODE) << BIT_SHIFT_H2CQ_DESC_MODE) -#define BIT_GET_H2CQ_DESC_MODE(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE) & BIT_MASK_H2CQ_DESC_MODE) +/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ +#define BIT_R_MGG_FIFO_EN BIT(31) -#define BIT_SHIFT_H2CQ_DESC_NUM 0 -#define BIT_MASK_H2CQ_DESC_NUM 0xfff -#define BIT_H2CQ_DESC_NUM(x) (((x) & BIT_MASK_H2CQ_DESC_NUM) << BIT_SHIFT_H2CQ_DESC_NUM) -#define BIT_GET_H2CQ_DESC_NUM(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM) & BIT_MASK_H2CQ_DESC_NUM) +#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE 28 +#define BIT_MASK_R_MGG_FIFO_PG_SIZE 0x7 +#define BIT_R_MGG_FIFO_PG_SIZE(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE) +#define BITS_R_MGG_FIFO_PG_SIZE \ + (BIT_MASK_R_MGG_FIFO_PG_SIZE << BIT_SHIFT_R_MGG_FIFO_PG_SIZE) +#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE(x) ((x) & (~BITS_R_MGG_FIFO_PG_SIZE)) +#define BIT_GET_R_MGG_FIFO_PG_SIZE(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE) & BIT_MASK_R_MGG_FIFO_PG_SIZE) +#define BIT_SET_R_MGG_FIFO_PG_SIZE(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_PG_SIZE(x) | BIT_R_MGG_FIFO_PG_SIZE(v)) +#define BIT_SHIFT_R_MGG_FIFO_START_PG 16 +#define BIT_MASK_R_MGG_FIFO_START_PG 0xfff +#define BIT_R_MGG_FIFO_START_PG(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_START_PG) << BIT_SHIFT_R_MGG_FIFO_START_PG) +#define BITS_R_MGG_FIFO_START_PG \ + (BIT_MASK_R_MGG_FIFO_START_PG << BIT_SHIFT_R_MGG_FIFO_START_PG) +#define BIT_CLEAR_R_MGG_FIFO_START_PG(x) ((x) & (~BITS_R_MGG_FIFO_START_PG)) +#define BIT_GET_R_MGG_FIFO_START_PG(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG) & BIT_MASK_R_MGG_FIFO_START_PG) +#define BIT_SET_R_MGG_FIFO_START_PG(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_START_PG(x) | BIT_R_MGG_FIFO_START_PG(v)) -/* 2 REG_H2CQ_TXBD_IDX (Offset 0x132C) */ +#define BIT_SHIFT_R_MGG_FIFO_SIZE 14 +#define BIT_MASK_R_MGG_FIFO_SIZE 0x3 +#define BIT_R_MGG_FIFO_SIZE(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_SIZE) << BIT_SHIFT_R_MGG_FIFO_SIZE) +#define BITS_R_MGG_FIFO_SIZE \ + (BIT_MASK_R_MGG_FIFO_SIZE << BIT_SHIFT_R_MGG_FIFO_SIZE) +#define BIT_CLEAR_R_MGG_FIFO_SIZE(x) ((x) & (~BITS_R_MGG_FIFO_SIZE)) +#define BIT_GET_R_MGG_FIFO_SIZE(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE) & BIT_MASK_R_MGG_FIFO_SIZE) +#define BIT_SET_R_MGG_FIFO_SIZE(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_SIZE(x) | BIT_R_MGG_FIFO_SIZE(v)) +#define BIT_R_MGG_FIFO_PAUSE BIT(13) -#define BIT_SHIFT_H2CQ_HW_IDX 16 -#define BIT_MASK_H2CQ_HW_IDX 0xfff -#define BIT_H2CQ_HW_IDX(x) (((x) & BIT_MASK_H2CQ_HW_IDX) << BIT_SHIFT_H2CQ_HW_IDX) -#define BIT_GET_H2CQ_HW_IDX(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX) & BIT_MASK_H2CQ_HW_IDX) +#define BIT_SHIFT_R_MGG_FIFO_RPTR 8 +#define BIT_MASK_R_MGG_FIFO_RPTR 0x1f +#define BIT_R_MGG_FIFO_RPTR(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_RPTR) << BIT_SHIFT_R_MGG_FIFO_RPTR) +#define BITS_R_MGG_FIFO_RPTR \ + (BIT_MASK_R_MGG_FIFO_RPTR << BIT_SHIFT_R_MGG_FIFO_RPTR) +#define BIT_CLEAR_R_MGG_FIFO_RPTR(x) ((x) & (~BITS_R_MGG_FIFO_RPTR)) +#define BIT_GET_R_MGG_FIFO_RPTR(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR) & BIT_MASK_R_MGG_FIFO_RPTR) +#define BIT_SET_R_MGG_FIFO_RPTR(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_RPTR(x) | BIT_R_MGG_FIFO_RPTR(v)) +#define BIT_R_MGG_FIFO_OV BIT(7) -#define BIT_SHIFT_H2CQ_HOST_IDX 0 -#define BIT_MASK_H2CQ_HOST_IDX 0xfff -#define BIT_H2CQ_HOST_IDX(x) (((x) & BIT_MASK_H2CQ_HOST_IDX) << BIT_SHIFT_H2CQ_HOST_IDX) -#define BIT_GET_H2CQ_HOST_IDX(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX) & BIT_MASK_H2CQ_HOST_IDX) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_H2CQ_CSR (Offset 0x1330) */ +/* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */ -#define BIT_H2CQ_FULL BIT(31) -#define BIT_CLR_H2CQ_HOST_IDX BIT(16) -#define BIT_CLR_H2CQ_HW_IDX BIT(8) +#define BIT_MGQ_FIFO_OV BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ +#define BIT_R_MGG_FIFO_WPTR_ERROR BIT(6) -/* 2 REG_H2CQ_CSR (Offset 0x1330) */ +#endif -#define BIT_STOP_H2CQ BIT(0) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */ +#define BIT_MGQ_FIFO_WPTR_ERROR BIT(6) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ +/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ -#define BIT_AXI_RXDMA_TIMEOUT_RE BIT(21) -#define BIT_AXI_TXDMA_TIMEOUT_RE BIT(20) -#define BIT_AXI_DECERR_W_RE BIT(19) -#define BIT_AXI_DECERR_R_RE BIT(18) +#define BIT_R_EN_CPU_LIFETIME BIT(5) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */ +#define BIT_EN_MGQ_FIFO_LIFETIME BIT(5) -/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ +#endif -#define BIT_CHANGE_PCIE_SPEED BIT(18) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ +#define BIT_SHIFT_R_MGG_FIFO_WPTR 0 +#define BIT_MASK_R_MGG_FIFO_WPTR 0x1f +#define BIT_R_MGG_FIFO_WPTR(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_WPTR) << BIT_SHIFT_R_MGG_FIFO_WPTR) +#define BITS_R_MGG_FIFO_WPTR \ + (BIT_MASK_R_MGG_FIFO_WPTR << BIT_SHIFT_R_MGG_FIFO_WPTR) +#define BIT_CLEAR_R_MGG_FIFO_WPTR(x) ((x) & (~BITS_R_MGG_FIFO_WPTR)) +#define BIT_GET_R_MGG_FIFO_WPTR(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR) & BIT_MASK_R_MGG_FIFO_WPTR) +#define BIT_SET_R_MGG_FIFO_WPTR(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_WPTR(x) | BIT_R_MGG_FIFO_WPTR(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ +/* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */ -#define BIT_AXI_SLVERR_W_RE BIT(17) -#define BIT_AXI_SLVERR_R_RE BIT(16) +#define BIT_SHIFT_MGQ_FIFO_WPTR 0 +#define BIT_MASK_MGQ_FIFO_WPTR 0x1f +#define BIT_MGQ_FIFO_WPTR(x) \ + (((x) & BIT_MASK_MGQ_FIFO_WPTR) << BIT_SHIFT_MGQ_FIFO_WPTR) +#define BITS_MGQ_FIFO_WPTR (BIT_MASK_MGQ_FIFO_WPTR << BIT_SHIFT_MGQ_FIFO_WPTR) +#define BIT_CLEAR_MGQ_FIFO_WPTR(x) ((x) & (~BITS_MGQ_FIFO_WPTR)) +#define BIT_GET_MGQ_FIFO_WPTR(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR) & BIT_MASK_MGQ_FIFO_WPTR) +#define BIT_SET_MGQ_FIFO_WPTR(x, v) \ + (BIT_CLEAR_MGQ_FIFO_WPTR(x) | BIT_MGQ_FIFO_WPTR(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_MGQ_FIFO_ENABLE (Offset 0x1472) */ +#define BIT_MGQ_FIFO_EN_V1 BIT(15) -/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_GEN1_GEN2 16 -#define BIT_MASK_GEN1_GEN2 0x3 -#define BIT_GEN1_GEN2(x) (((x) & BIT_MASK_GEN1_GEN2) << BIT_SHIFT_GEN1_GEN2) -#define BIT_GET_GEN1_GEN2(x) (((x) >> BIT_SHIFT_GEN1_GEN2) & BIT_MASK_GEN1_GEN2) +/* 2 REG_MGQ_FIFO_ENABLE (Offset 0x1472) */ +#define BIT_MGQ_FIFO_EN BIT(15) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_MGQ_FIFO_READ_POINTER (Offset 0x1472) */ +#define BIT_SHIFT_MGQ_FIFO_SIZE 14 +#define BIT_MASK_MGQ_FIFO_SIZE 0x3 +#define BIT_MGQ_FIFO_SIZE(x) \ + (((x) & BIT_MASK_MGQ_FIFO_SIZE) << BIT_SHIFT_MGQ_FIFO_SIZE) +#define BITS_MGQ_FIFO_SIZE (BIT_MASK_MGQ_FIFO_SIZE << BIT_SHIFT_MGQ_FIFO_SIZE) +#define BIT_CLEAR_MGQ_FIFO_SIZE(x) ((x) & (~BITS_MGQ_FIFO_SIZE)) +#define BIT_GET_MGQ_FIFO_SIZE(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE) & BIT_MASK_MGQ_FIFO_SIZE) +#define BIT_SET_MGQ_FIFO_SIZE(x, v) \ + (BIT_CLEAR_MGQ_FIFO_SIZE(x) | BIT_MGQ_FIFO_SIZE(v)) -/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ +#define BIT_MGQ_FIFO_PAUSE BIT(13) + +#define BIT_SHIFT_MGQ_FIFO_PG_SIZE 12 +#define BIT_MASK_MGQ_FIFO_PG_SIZE 0x7 +#define BIT_MGQ_FIFO_PG_SIZE(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE) << BIT_SHIFT_MGQ_FIFO_PG_SIZE) +#define BITS_MGQ_FIFO_PG_SIZE \ + (BIT_MASK_MGQ_FIFO_PG_SIZE << BIT_SHIFT_MGQ_FIFO_PG_SIZE) +#define BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) ((x) & (~BITS_MGQ_FIFO_PG_SIZE)) +#define BIT_GET_MGQ_FIFO_PG_SIZE(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE) & BIT_MASK_MGQ_FIFO_PG_SIZE) +#define BIT_SET_MGQ_FIFO_PG_SIZE(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) | BIT_MGQ_FIFO_PG_SIZE(v)) -#define BIT_AXI_RXDMA_TIMEOUT_IE BIT(13) -#define BIT_AXI_TXDMA_TIMEOUT_IE BIT(12) -#define BIT_AXI_DECERR_W_IE BIT(11) -#define BIT_AXI_DECERR_R_IE BIT(10) -#define BIT_AXI_SLVERR_W_IE BIT(9) -#define BIT_AXI_SLVERR_R_IE BIT(8) -#define BIT_AXI_RXDMA_TIMEOUT_FLAG BIT(5) -#define BIT_AXI_TXDMA_TIMEOUT_FLAG BIT(4) -#define BIT_AXI_DECERR_W_FLAG BIT(3) -#define BIT_AXI_DECERR_R_FLAG BIT(2) -#define BIT_AXI_SLVERR_W_FLAG BIT(1) -#define BIT_AXI_SLVERR_R_FLAG BIT(0) +#define BIT_SHIFT_MGQ_FIFO_RPTR 8 +#define BIT_MASK_MGQ_FIFO_RPTR 0x1f +#define BIT_MGQ_FIFO_RPTR(x) \ + (((x) & BIT_MASK_MGQ_FIFO_RPTR) << BIT_SHIFT_MGQ_FIFO_RPTR) +#define BITS_MGQ_FIFO_RPTR (BIT_MASK_MGQ_FIFO_RPTR << BIT_SHIFT_MGQ_FIFO_RPTR) +#define BIT_CLEAR_MGQ_FIFO_RPTR(x) ((x) & (~BITS_MGQ_FIFO_RPTR)) +#define BIT_GET_MGQ_FIFO_RPTR(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR) & BIT_MASK_MGQ_FIFO_RPTR) +#define BIT_SET_MGQ_FIFO_RPTR(x, v) \ + (BIT_CLEAR_MGQ_FIFO_RPTR(x) | BIT_MGQ_FIFO_RPTR(v)) + +#define BIT_SHIFT_MGQ_FIFO_START_PG 0 +#define BIT_MASK_MGQ_FIFO_START_PG 0xfff +#define BIT_MGQ_FIFO_START_PG(x) \ + (((x) & BIT_MASK_MGQ_FIFO_START_PG) << BIT_SHIFT_MGQ_FIFO_START_PG) +#define BITS_MGQ_FIFO_START_PG \ + (BIT_MASK_MGQ_FIFO_START_PG << BIT_SHIFT_MGQ_FIFO_START_PG) +#define BIT_CLEAR_MGQ_FIFO_START_PG(x) ((x) & (~BITS_MGQ_FIFO_START_PG)) +#define BIT_GET_MGQ_FIFO_START_PG(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG) & BIT_MASK_MGQ_FIFO_START_PG) +#define BIT_SET_MGQ_FIFO_START_PG(x, v) \ + (BIT_CLEAR_MGQ_FIFO_START_PG(x) | BIT_MGQ_FIFO_START_PG(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_MGG_FIFO_INT (Offset 0x1474) */ +#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG 16 +#define BIT_MASK_R_MGG_FIFO_INT_FLAG 0xffff +#define BIT_R_MGG_FIFO_INT_FLAG(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG) +#define BITS_R_MGG_FIFO_INT_FLAG \ + (BIT_MASK_R_MGG_FIFO_INT_FLAG << BIT_SHIFT_R_MGG_FIFO_INT_FLAG) +#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG(x) ((x) & (~BITS_R_MGG_FIFO_INT_FLAG)) +#define BIT_GET_R_MGG_FIFO_INT_FLAG(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG) & BIT_MASK_R_MGG_FIFO_INT_FLAG) +#define BIT_SET_R_MGG_FIFO_INT_FLAG(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_INT_FLAG(x) | BIT_R_MGG_FIFO_INT_FLAG(v)) + +#define BIT_SHIFT_R_MGG_FIFO_INT_MASK 0 +#define BIT_MASK_R_MGG_FIFO_INT_MASK 0xffff +#define BIT_R_MGG_FIFO_INT_MASK(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK) << BIT_SHIFT_R_MGG_FIFO_INT_MASK) +#define BITS_R_MGG_FIFO_INT_MASK \ + (BIT_MASK_R_MGG_FIFO_INT_MASK << BIT_SHIFT_R_MGG_FIFO_INT_MASK) +#define BIT_CLEAR_R_MGG_FIFO_INT_MASK(x) ((x) & (~BITS_R_MGG_FIFO_INT_MASK)) +#define BIT_GET_R_MGG_FIFO_INT_MASK(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK) & BIT_MASK_R_MGG_FIFO_INT_MASK) +#define BIT_SET_R_MGG_FIFO_INT_MASK(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_INT_MASK(x) | BIT_R_MGG_FIFO_INT_MASK(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK (Offset 0x1474) */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_MASK 0xffff +#define BIT_MGQ_FIFO_REL_INT_MASK(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK) +#define BITS_MGQ_FIFO_REL_INT_MASK \ + (BIT_MASK_MGQ_FIFO_REL_INT_MASK << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK(x) ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK)) +#define BIT_GET_MGQ_FIFO_REL_INT_MASK(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK) & \ + BIT_MASK_MGQ_FIFO_REL_INT_MASK) +#define BIT_SET_MGQ_FIFO_REL_INT_MASK(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK(x) | BIT_MGQ_FIFO_REL_INT_MASK(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG (Offset 0x1476) */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG 0xffff +#define BIT_MGQ_FIFO_REL_INT_FLAG(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG) +#define BITS_MGQ_FIFO_REL_INT_FLAG \ + (BIT_MASK_MGQ_FIFO_REL_INT_FLAG << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG(x) ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG)) +#define BIT_GET_MGQ_FIFO_REL_INT_FLAG(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG) & \ + BIT_MASK_MGQ_FIFO_REL_INT_FLAG) +#define BIT_SET_MGQ_FIFO_REL_INT_FLAG(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG(x) | BIT_MGQ_FIFO_REL_INT_FLAG(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ +/* 2 REG_MGG_FIFO_LIFETIME (Offset 0x1478) */ + +#define BIT_SHIFT_R_MGG_FIFO_LIFETIME 16 +#define BIT_MASK_R_MGG_FIFO_LIFETIME 0xffff +#define BIT_R_MGG_FIFO_LIFETIME(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME) << BIT_SHIFT_R_MGG_FIFO_LIFETIME) +#define BITS_R_MGG_FIFO_LIFETIME \ + (BIT_MASK_R_MGG_FIFO_LIFETIME << BIT_SHIFT_R_MGG_FIFO_LIFETIME) +#define BIT_CLEAR_R_MGG_FIFO_LIFETIME(x) ((x) & (~BITS_R_MGG_FIFO_LIFETIME)) +#define BIT_GET_R_MGG_FIFO_LIFETIME(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME) & BIT_MASK_R_MGG_FIFO_LIFETIME) +#define BIT_SET_R_MGG_FIFO_LIFETIME(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_LIFETIME(x) | BIT_R_MGG_FIFO_LIFETIME(v)) + +#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP 0 +#define BIT_MASK_R_MGG_FIFO_VALID_MAP 0xffff +#define BIT_R_MGG_FIFO_VALID_MAP(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP) \ + << BIT_SHIFT_R_MGG_FIFO_VALID_MAP) +#define BITS_R_MGG_FIFO_VALID_MAP \ + (BIT_MASK_R_MGG_FIFO_VALID_MAP << BIT_SHIFT_R_MGG_FIFO_VALID_MAP) +#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP(x) ((x) & (~BITS_R_MGG_FIFO_VALID_MAP)) +#define BIT_GET_R_MGG_FIFO_VALID_MAP(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP) & \ + BIT_MASK_R_MGG_FIFO_VALID_MAP) +#define BIT_SET_R_MGG_FIFO_VALID_MAP(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_VALID_MAP(x) | BIT_R_MGG_FIFO_VALID_MAP(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MGQ_FIFO_VALID_MAP (Offset 0x1478) */ + +#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP 0 +#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP 0xffff +#define BIT_MGQ_FIFO_PKT_VALID_MAP(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP) \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP) +#define BITS_MGQ_FIFO_PKT_VALID_MAP \ + (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP) +#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP(x) \ + ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP)) +#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP) & \ + BIT_MASK_MGQ_FIFO_PKT_VALID_MAP) +#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP(x) | BIT_MGQ_FIFO_PKT_VALID_MAP(v)) + +/* 2 REG_MGQ_FIFO_LIFETIME (Offset 0x147A) */ + +#define BIT_SHIFT_MGQ_FIFO_LIFETIME 0 +#define BIT_MASK_MGQ_FIFO_LIFETIME 0xffff +#define BIT_MGQ_FIFO_LIFETIME(x) \ + (((x) & BIT_MASK_MGQ_FIFO_LIFETIME) << BIT_SHIFT_MGQ_FIFO_LIFETIME) +#define BITS_MGQ_FIFO_LIFETIME \ + (BIT_MASK_MGQ_FIFO_LIFETIME << BIT_SHIFT_MGQ_FIFO_LIFETIME) +#define BIT_CLEAR_MGQ_FIFO_LIFETIME(x) ((x) & (~BITS_MGQ_FIFO_LIFETIME)) +#define BIT_GET_MGQ_FIFO_LIFETIME(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME) & BIT_MASK_MGQ_FIFO_LIFETIME) +#define BIT_SET_MGQ_FIFO_LIFETIME(x, v) \ + (BIT_CLEAR_MGQ_FIFO_LIFETIME(x) | BIT_MGQ_FIFO_LIFETIME(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET (Offset 0x147C) */ +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x7f +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) +#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_PKT_TRANS (Offset 0x1480) */ + +#define BIT_SHIFT_IE_DESC_OFFSET 16 +#define BIT_MASK_IE_DESC_OFFSET 0x1ff +#define BIT_IE_DESC_OFFSET(x) \ + (((x) & BIT_MASK_IE_DESC_OFFSET) << BIT_SHIFT_IE_DESC_OFFSET) +#define BITS_IE_DESC_OFFSET \ + (BIT_MASK_IE_DESC_OFFSET << BIT_SHIFT_IE_DESC_OFFSET) +#define BIT_CLEAR_IE_DESC_OFFSET(x) ((x) & (~BITS_IE_DESC_OFFSET)) +#define BIT_GET_IE_DESC_OFFSET(x) \ + (((x) >> BIT_SHIFT_IE_DESC_OFFSET) & BIT_MASK_IE_DESC_OFFSET) +#define BIT_SET_IE_DESC_OFFSET(x, v) \ + (BIT_CLEAR_IE_DESC_OFFSET(x) | BIT_IE_DESC_OFFSET(v)) + +#define BIT_DIS_FWCMD_PATH_ERRCHK BIT(13) +#define BIT_MAC_HDR_CONVERT_EN BIT(12) +#define BIT_TXDESC_TRANS_EN BIT(8) +#define BIT_PKT_TRANS_ERRINT_EN BIT(7) + +#define BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL 4 +#define BIT_MASK_PKT_TRANS_ERR_MACID_SEL 0x3 +#define BIT_PKT_TRANS_ERR_MACID_SEL(x) \ + (((x) & BIT_MASK_PKT_TRANS_ERR_MACID_SEL) \ + << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL) +#define BITS_PKT_TRANS_ERR_MACID_SEL \ + (BIT_MASK_PKT_TRANS_ERR_MACID_SEL << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL) +#define BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL(x) \ + ((x) & (~BITS_PKT_TRANS_ERR_MACID_SEL)) +#define BIT_GET_PKT_TRANS_ERR_MACID_SEL(x) \ + (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL) & \ + BIT_MASK_PKT_TRANS_ERR_MACID_SEL) +#define BIT_SET_PKT_TRANS_ERR_MACID_SEL(x, v) \ + (BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL(x) | BIT_PKT_TRANS_ERR_MACID_SEL(v)) + +#define BIT_PKT_TRANS_IEINIT_ERR BIT(3) +#define BIT_PKT_TRANS_IENUM_ERR BIT(2) +#define BIT_PKT_TRANS_IECNT_ERR1 BIT(1) +#define BIT_PKT_TRANS_IECNT_ERR0 BIT(0) + +/* 2 REG_SHCUT_LLC_ETH_TYPE1 (Offset 0x1488) */ + +#define BIT_SHIFT_SHCUT_MHDR_OFFSET 16 +#define BIT_MASK_SHCUT_MHDR_OFFSET 0x1ff +#define BIT_SHCUT_MHDR_OFFSET(x) \ + (((x) & BIT_MASK_SHCUT_MHDR_OFFSET) << BIT_SHIFT_SHCUT_MHDR_OFFSET) +#define BITS_SHCUT_MHDR_OFFSET \ + (BIT_MASK_SHCUT_MHDR_OFFSET << BIT_SHIFT_SHCUT_MHDR_OFFSET) +#define BIT_CLEAR_SHCUT_MHDR_OFFSET(x) ((x) & (~BITS_SHCUT_MHDR_OFFSET)) +#define BIT_GET_SHCUT_MHDR_OFFSET(x) \ + (((x) >> BIT_SHIFT_SHCUT_MHDR_OFFSET) & BIT_MASK_SHCUT_MHDR_OFFSET) +#define BIT_SET_SHCUT_MHDR_OFFSET(x, v) \ + (BIT_CLEAR_SHCUT_MHDR_OFFSET(x) | BIT_SHCUT_MHDR_OFFSET(v)) + +#define BIT_SHIFT_PKT_TRANS_ERR_MACID 0 +#define BIT_MASK_PKT_TRANS_ERR_MACID 0xffffffffL +#define BIT_PKT_TRANS_ERR_MACID(x) \ + (((x) & BIT_MASK_PKT_TRANS_ERR_MACID) << BIT_SHIFT_PKT_TRANS_ERR_MACID) +#define BITS_PKT_TRANS_ERR_MACID \ + (BIT_MASK_PKT_TRANS_ERR_MACID << BIT_SHIFT_PKT_TRANS_ERR_MACID) +#define BIT_CLEAR_PKT_TRANS_ERR_MACID(x) ((x) & (~BITS_PKT_TRANS_ERR_MACID)) +#define BIT_GET_PKT_TRANS_ERR_MACID(x) \ + (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID) & BIT_MASK_PKT_TRANS_ERR_MACID) +#define BIT_SET_PKT_TRANS_ERR_MACID(x, v) \ + (BIT_CLEAR_PKT_TRANS_ERR_MACID(x) | BIT_PKT_TRANS_ERR_MACID(v)) + +/* 2 REG_FWCMDQ_CTRL (Offset 0x14A0) */ + +#define BIT_FW_RELEASEPKT_POLLING BIT(31) + +#define BIT_SHIFT_FWCMDQ_RELEASE_HEAD 16 +#define BIT_MASK_FWCMDQ_RELEASE_HEAD 0xfff +#define BIT_FWCMDQ_RELEASE_HEAD(x) \ + (((x) & BIT_MASK_FWCMDQ_RELEASE_HEAD) << BIT_SHIFT_FWCMDQ_RELEASE_HEAD) +#define BITS_FWCMDQ_RELEASE_HEAD \ + (BIT_MASK_FWCMDQ_RELEASE_HEAD << BIT_SHIFT_FWCMDQ_RELEASE_HEAD) +#define BIT_CLEAR_FWCMDQ_RELEASE_HEAD(x) ((x) & (~BITS_FWCMDQ_RELEASE_HEAD)) +#define BIT_GET_FWCMDQ_RELEASE_HEAD(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_RELEASE_HEAD) & BIT_MASK_FWCMDQ_RELEASE_HEAD) +#define BIT_SET_FWCMDQ_RELEASE_HEAD(x, v) \ + (BIT_CLEAR_FWCMDQ_RELEASE_HEAD(x) | BIT_FWCMDQ_RELEASE_HEAD(v)) + +#define BIT_FW_GETPKTT_POLLING BIT(15) + +#define BIT_SHIFT_FWCMDQ_H 0 +#define BIT_MASK_FWCMDQ_H 0xfff +#define BIT_FWCMDQ_H(x) (((x) & BIT_MASK_FWCMDQ_H) << BIT_SHIFT_FWCMDQ_H) +#define BITS_FWCMDQ_H (BIT_MASK_FWCMDQ_H << BIT_SHIFT_FWCMDQ_H) +#define BIT_CLEAR_FWCMDQ_H(x) ((x) & (~BITS_FWCMDQ_H)) +#define BIT_GET_FWCMDQ_H(x) (((x) >> BIT_SHIFT_FWCMDQ_H) & BIT_MASK_FWCMDQ_H) +#define BIT_SET_FWCMDQ_H(x, v) (BIT_CLEAR_FWCMDQ_H(x) | BIT_FWCMDQ_H(v)) + +/* 2 REG_FWCMDQ_PAGE (Offset 0x14A4) */ + +#define BIT_SHIFT_FWCMDQ_TOTAL_PAGE 16 +#define BIT_MASK_FWCMDQ_TOTAL_PAGE 0xfff +#define BIT_FWCMDQ_TOTAL_PAGE(x) \ + (((x) & BIT_MASK_FWCMDQ_TOTAL_PAGE) << BIT_SHIFT_FWCMDQ_TOTAL_PAGE) +#define BITS_FWCMDQ_TOTAL_PAGE \ + (BIT_MASK_FWCMDQ_TOTAL_PAGE << BIT_SHIFT_FWCMDQ_TOTAL_PAGE) +#define BIT_CLEAR_FWCMDQ_TOTAL_PAGE(x) ((x) & (~BITS_FWCMDQ_TOTAL_PAGE)) +#define BIT_GET_FWCMDQ_TOTAL_PAGE(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PAGE) & BIT_MASK_FWCMDQ_TOTAL_PAGE) +#define BIT_SET_FWCMDQ_TOTAL_PAGE(x, v) \ + (BIT_CLEAR_FWCMDQ_TOTAL_PAGE(x) | BIT_FWCMDQ_TOTAL_PAGE(v)) + +#define BIT_SHIFT_FWCMDQ_QUEUE_PAGE 0 +#define BIT_MASK_FWCMDQ_QUEUE_PAGE 0xfff +#define BIT_FWCMDQ_QUEUE_PAGE(x) \ + (((x) & BIT_MASK_FWCMDQ_QUEUE_PAGE) << BIT_SHIFT_FWCMDQ_QUEUE_PAGE) +#define BITS_FWCMDQ_QUEUE_PAGE \ + (BIT_MASK_FWCMDQ_QUEUE_PAGE << BIT_SHIFT_FWCMDQ_QUEUE_PAGE) +#define BIT_CLEAR_FWCMDQ_QUEUE_PAGE(x) ((x) & (~BITS_FWCMDQ_QUEUE_PAGE)) +#define BIT_GET_FWCMDQ_QUEUE_PAGE(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PAGE) & BIT_MASK_FWCMDQ_QUEUE_PAGE) +#define BIT_SET_FWCMDQ_QUEUE_PAGE(x, v) \ + (BIT_CLEAR_FWCMDQ_QUEUE_PAGE(x) | BIT_FWCMDQ_QUEUE_PAGE(v)) + +/* 2 REG_FWCMDQ_INFO (Offset 0x14A8) */ + +#define BIT_FWCMD_READY BIT(31) +#define BIT_FWCMDQ_OVERFLOW BIT(30) +#define BIT_FWCMDQ_UNDERFLOW BIT(29) +#define BIT_FWCMDQ_RELEASE_MISS BIT(28) + +#define BIT_SHIFT_FWCMDQ_TOTAL_PKT 16 +#define BIT_MASK_FWCMDQ_TOTAL_PKT 0xfff +#define BIT_FWCMDQ_TOTAL_PKT(x) \ + (((x) & BIT_MASK_FWCMDQ_TOTAL_PKT) << BIT_SHIFT_FWCMDQ_TOTAL_PKT) +#define BITS_FWCMDQ_TOTAL_PKT \ + (BIT_MASK_FWCMDQ_TOTAL_PKT << BIT_SHIFT_FWCMDQ_TOTAL_PKT) +#define BIT_CLEAR_FWCMDQ_TOTAL_PKT(x) ((x) & (~BITS_FWCMDQ_TOTAL_PKT)) +#define BIT_GET_FWCMDQ_TOTAL_PKT(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PKT) & BIT_MASK_FWCMDQ_TOTAL_PKT) +#define BIT_SET_FWCMDQ_TOTAL_PKT(x, v) \ + (BIT_CLEAR_FWCMDQ_TOTAL_PKT(x) | BIT_FWCMDQ_TOTAL_PKT(v)) + +#define BIT_SHIFT_FWCMDQ_QUEUE_PKT 0 +#define BIT_MASK_FWCMDQ_QUEUE_PKT 0xfff +#define BIT_FWCMDQ_QUEUE_PKT(x) \ + (((x) & BIT_MASK_FWCMDQ_QUEUE_PKT) << BIT_SHIFT_FWCMDQ_QUEUE_PKT) +#define BITS_FWCMDQ_QUEUE_PKT \ + (BIT_MASK_FWCMDQ_QUEUE_PKT << BIT_SHIFT_FWCMDQ_QUEUE_PKT) +#define BIT_CLEAR_FWCMDQ_QUEUE_PKT(x) ((x) & (~BITS_FWCMDQ_QUEUE_PKT)) +#define BIT_GET_FWCMDQ_QUEUE_PKT(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PKT) & BIT_MASK_FWCMDQ_QUEUE_PKT) +#define BIT_SET_FWCMDQ_QUEUE_PKT(x, v) \ + (BIT_CLEAR_FWCMDQ_QUEUE_PKT(x) | BIT_FWCMDQ_QUEUE_PKT(v)) + +/* 2 REG_FWCMDQ_HOLD_PKTNUM (Offset 0x14AC) */ + +#define BIT_SHIFT_FWCMDQ_HOLD__PKTNUM 0 +#define BIT_MASK_FWCMDQ_HOLD__PKTNUM 0xfff +#define BIT_FWCMDQ_HOLD__PKTNUM(x) \ + (((x) & BIT_MASK_FWCMDQ_HOLD__PKTNUM) << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM) +#define BITS_FWCMDQ_HOLD__PKTNUM \ + (BIT_MASK_FWCMDQ_HOLD__PKTNUM << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM) +#define BIT_CLEAR_FWCMDQ_HOLD__PKTNUM(x) ((x) & (~BITS_FWCMDQ_HOLD__PKTNUM)) +#define BIT_GET_FWCMDQ_HOLD__PKTNUM(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_HOLD__PKTNUM) & BIT_MASK_FWCMDQ_HOLD__PKTNUM) +#define BIT_SET_FWCMDQ_HOLD__PKTNUM(x, v) \ + (BIT_CLEAR_FWCMDQ_HOLD__PKTNUM(x) | BIT_FWCMDQ_HOLD__PKTNUM(v)) + +/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ + +#define BIT_SEARCH_DONE_RDY BIT(31) +#define BIT_MU_EN BIT(30) +#define BIT_MU_SECONDARY_WAITMODE_EN BIT(29) +#define BIT_MU_BB_SCORE_EN BIT(28) +#define BIT_MU_SECONDARY_ANT_COUNT_EN BIT(27) +#define BIT_MUARB_SEARCH_ERR_EN BIT(26) + +#define BIT_SHIFT_DIS_SU_TXBF 16 +#define BIT_MASK_DIS_SU_TXBF 0x3f +#define BIT_DIS_SU_TXBF(x) \ + (((x) & BIT_MASK_DIS_SU_TXBF) << BIT_SHIFT_DIS_SU_TXBF) +#define BITS_DIS_SU_TXBF (BIT_MASK_DIS_SU_TXBF << BIT_SHIFT_DIS_SU_TXBF) +#define BIT_CLEAR_DIS_SU_TXBF(x) ((x) & (~BITS_DIS_SU_TXBF)) +#define BIT_GET_DIS_SU_TXBF(x) \ + (((x) >> BIT_SHIFT_DIS_SU_TXBF) & BIT_MASK_DIS_SU_TXBF) +#define BIT_SET_DIS_SU_TXBF(x, v) \ + (BIT_CLEAR_DIS_SU_TXBF(x) | BIT_DIS_SU_TXBF(v)) + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AUTO_HANG_RELEASE 0 -#define BIT_MASK_AUTO_HANG_RELEASE 0x7 -#define BIT_AUTO_HANG_RELEASE(x) (((x) & BIT_MASK_AUTO_HANG_RELEASE) << BIT_SHIFT_AUTO_HANG_RELEASE) -#define BIT_GET_AUTO_HANG_RELEASE(x) (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE) & BIT_MASK_AUTO_HANG_RELEASE) +/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ +#define BIT_R_MU_P1_WAIT_STATE_EN BIT(16) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ +#define BIT_SHIFT_MU_RL 12 +#define BIT_MASK_MU_RL 0xf +#define BIT_MU_RL(x) (((x) & BIT_MASK_MU_RL) << BIT_SHIFT_MU_RL) +#define BITS_MU_RL (BIT_MASK_MU_RL << BIT_SHIFT_MU_RL) +#define BIT_CLEAR_MU_RL(x) ((x) & (~BITS_MU_RL)) +#define BIT_GET_MU_RL(x) (((x) >> BIT_SHIFT_MU_RL) & BIT_MASK_MU_RL) +#define BIT_SET_MU_RL(x, v) (BIT_CLEAR_MU_RL(x) | BIT_MU_RL(v)) -/* 2 REG_AXI_EXCEPT_TIME (Offset 0x1354) */ +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AXI_RECOVERY_TIME 24 -#define BIT_MASK_AXI_RECOVERY_TIME 0xff -#define BIT_AXI_RECOVERY_TIME(x) (((x) & BIT_MASK_AXI_RECOVERY_TIME) << BIT_SHIFT_AXI_RECOVERY_TIME) -#define BIT_GET_AXI_RECOVERY_TIME(x) (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME) & BIT_MASK_AXI_RECOVERY_TIME) +/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ + +#define BIT_SHIFT_R_MU_RL 12 +#define BIT_MASK_R_MU_RL 0xf +#define BIT_R_MU_RL(x) (((x) & BIT_MASK_R_MU_RL) << BIT_SHIFT_R_MU_RL) +#define BITS_R_MU_RL (BIT_MASK_R_MU_RL << BIT_SHIFT_R_MU_RL) +#define BIT_CLEAR_R_MU_RL(x) ((x) & (~BITS_R_MU_RL)) +#define BIT_GET_R_MU_RL(x) (((x) >> BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL) +#define BIT_SET_R_MU_RL(x, v) (BIT_CLEAR_R_MU_RL(x) | BIT_R_MU_RL(v)) +#define BIT_R_FORCE_P1_RATEDOWN BIT(11) -#define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL 12 -#define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL 0xfff -#define BIT_AXI_RXDMA_TIMEOUT_VAL(x) (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL) << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) -#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL(x) (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL 0 -#define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL 0xfff -#define BIT_AXI_TXDMA_TIMEOUT_VAL(x) (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL) << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) -#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL(x) (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL) +/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ +#define BIT_SHIFT_MU_TAB_SEL 8 +#define BIT_MASK_MU_TAB_SEL 0xf +#define BIT_MU_TAB_SEL(x) (((x) & BIT_MASK_MU_TAB_SEL) << BIT_SHIFT_MU_TAB_SEL) +#define BITS_MU_TAB_SEL (BIT_MASK_MU_TAB_SEL << BIT_SHIFT_MU_TAB_SEL) +#define BIT_CLEAR_MU_TAB_SEL(x) ((x) & (~BITS_MU_TAB_SEL)) +#define BIT_GET_MU_TAB_SEL(x) \ + (((x) >> BIT_SHIFT_MU_TAB_SEL) & BIT_MASK_MU_TAB_SEL) +#define BIT_SET_MU_TAB_SEL(x, v) (BIT_CLEAR_MU_TAB_SEL(x) | BIT_MU_TAB_SEL(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) - +/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ -/* 2 REG_OLD_DEHANG (Offset 0x13F4) */ +#define BIT_SHIFT_R_MU_TAB_SEL 8 +#define BIT_MASK_R_MU_TAB_SEL 0x7 +#define BIT_R_MU_TAB_SEL(x) \ + (((x) & BIT_MASK_R_MU_TAB_SEL) << BIT_SHIFT_R_MU_TAB_SEL) +#define BITS_R_MU_TAB_SEL (BIT_MASK_R_MU_TAB_SEL << BIT_SHIFT_R_MU_TAB_SEL) +#define BIT_CLEAR_R_MU_TAB_SEL(x) ((x) & (~BITS_R_MU_TAB_SEL)) +#define BIT_GET_R_MU_TAB_SEL(x) \ + (((x) >> BIT_SHIFT_R_MU_TAB_SEL) & BIT_MASK_R_MU_TAB_SEL) +#define BIT_SET_R_MU_TAB_SEL(x, v) \ + (BIT_CLEAR_R_MU_TAB_SEL(x) | BIT_R_MU_TAB_SEL(v)) -#define BIT_OLD_DEHANG BIT(1) +#define BIT_R_EN_MU_MIMO BIT(7) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ +#define BIT_R_EN_REVERS_GTAB BIT(6) -/* 2 REG_Q0_Q1_INFO (Offset 0x1400) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_AC1_PKT_INFO 16 -#define BIT_MASK_AC1_PKT_INFO 0xfff -#define BIT_AC1_PKT_INFO(x) (((x) & BIT_MASK_AC1_PKT_INFO) << BIT_SHIFT_AC1_PKT_INFO) -#define BIT_GET_AC1_PKT_INFO(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO) & BIT_MASK_AC1_PKT_INFO) +/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ +#define BIT_SHIFT_MU_TAB_VALID 0 +#define BIT_MASK_MU_TAB_VALID 0x3f +#define BIT_MU_TAB_VALID(x) \ + (((x) & BIT_MASK_MU_TAB_VALID) << BIT_SHIFT_MU_TAB_VALID) +#define BITS_MU_TAB_VALID (BIT_MASK_MU_TAB_VALID << BIT_SHIFT_MU_TAB_VALID) +#define BIT_CLEAR_MU_TAB_VALID(x) ((x) & (~BITS_MU_TAB_VALID)) +#define BIT_GET_MU_TAB_VALID(x) \ + (((x) >> BIT_SHIFT_MU_TAB_VALID) & BIT_MASK_MU_TAB_VALID) +#define BIT_SET_MU_TAB_VALID(x, v) \ + (BIT_CLEAR_MU_TAB_VALID(x) | BIT_MU_TAB_VALID(v)) -#define BIT_SHIFT_AC0_PKT_INFO 0 -#define BIT_MASK_AC0_PKT_INFO 0xfff -#define BIT_AC0_PKT_INFO(x) (((x) & BIT_MASK_AC0_PKT_INFO) << BIT_SHIFT_AC0_PKT_INFO) -#define BIT_GET_AC0_PKT_INFO(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO) & BIT_MASK_AC0_PKT_INFO) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_Q2_Q3_INFO (Offset 0x1404) */ +/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ +#define BIT_SHIFT_R_MU_TABLE_VALID 0 +#define BIT_MASK_R_MU_TABLE_VALID 0x3f +#define BIT_R_MU_TABLE_VALID(x) \ + (((x) & BIT_MASK_R_MU_TABLE_VALID) << BIT_SHIFT_R_MU_TABLE_VALID) +#define BITS_R_MU_TABLE_VALID \ + (BIT_MASK_R_MU_TABLE_VALID << BIT_SHIFT_R_MU_TABLE_VALID) +#define BIT_CLEAR_R_MU_TABLE_VALID(x) ((x) & (~BITS_R_MU_TABLE_VALID)) +#define BIT_GET_R_MU_TABLE_VALID(x) \ + (((x) >> BIT_SHIFT_R_MU_TABLE_VALID) & BIT_MASK_R_MU_TABLE_VALID) +#define BIT_SET_R_MU_TABLE_VALID(x, v) \ + (BIT_CLEAR_R_MU_TABLE_VALID(x) | BIT_R_MU_TABLE_VALID(v)) + +#endif -#define BIT_SHIFT_AC3_PKT_INFO 16 -#define BIT_MASK_AC3_PKT_INFO 0xfff -#define BIT_AC3_PKT_INFO(x) (((x) & BIT_MASK_AC3_PKT_INFO) << BIT_SHIFT_AC3_PKT_INFO) -#define BIT_GET_AC3_PKT_INFO(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO) & BIT_MASK_AC3_PKT_INFO) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_MU_STA_GID_VLD (Offset 0x14C4) */ -#define BIT_SHIFT_AC2_PKT_INFO 0 -#define BIT_MASK_AC2_PKT_INFO 0xfff -#define BIT_AC2_PKT_INFO(x) (((x) & BIT_MASK_AC2_PKT_INFO) << BIT_SHIFT_AC2_PKT_INFO) -#define BIT_GET_AC2_PKT_INFO(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO) & BIT_MASK_AC2_PKT_INFO) +#define BIT_SHIFT_MU_STA_GTAB_VALID 0 +#define BIT_MASK_MU_STA_GTAB_VALID 0xffffffffL +#define BIT_MU_STA_GTAB_VALID(x) \ + (((x) & BIT_MASK_MU_STA_GTAB_VALID) << BIT_SHIFT_MU_STA_GTAB_VALID) +#define BITS_MU_STA_GTAB_VALID \ + (BIT_MASK_MU_STA_GTAB_VALID << BIT_SHIFT_MU_STA_GTAB_VALID) +#define BIT_CLEAR_MU_STA_GTAB_VALID(x) ((x) & (~BITS_MU_STA_GTAB_VALID)) +#define BIT_GET_MU_STA_GTAB_VALID(x) \ + (((x) >> BIT_SHIFT_MU_STA_GTAB_VALID) & BIT_MASK_MU_STA_GTAB_VALID) +#define BIT_SET_MU_STA_GTAB_VALID(x, v) \ + (BIT_CLEAR_MU_STA_GTAB_VALID(x) | BIT_MU_STA_GTAB_VALID(v)) + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MU_STA_GID_VLD (Offset 0x14C4) */ + +#define BIT_SHIFT_R_MU_STA_GTAB_VALID 0 +#define BIT_MASK_R_MU_STA_GTAB_VALID 0xffffffffL +#define BIT_R_MU_STA_GTAB_VALID(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID) << BIT_SHIFT_R_MU_STA_GTAB_VALID) +#define BITS_R_MU_STA_GTAB_VALID \ + (BIT_MASK_R_MU_STA_GTAB_VALID << BIT_SHIFT_R_MU_STA_GTAB_VALID) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID(x) ((x) & (~BITS_R_MU_STA_GTAB_VALID)) +#define BIT_GET_R_MU_STA_GTAB_VALID(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID) & BIT_MASK_R_MU_STA_GTAB_VALID) +#define BIT_SET_R_MU_STA_GTAB_VALID(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID(x) | BIT_R_MU_STA_GTAB_VALID(v)) +#endif -/* 2 REG_Q4_Q5_INFO (Offset 0x1408) */ +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_MU_STA_USER_POS_INFO (Offset 0x14C8) */ -#define BIT_SHIFT_AC5_PKT_INFO 16 -#define BIT_MASK_AC5_PKT_INFO 0xfff -#define BIT_AC5_PKT_INFO(x) (((x) & BIT_MASK_AC5_PKT_INFO) << BIT_SHIFT_AC5_PKT_INFO) -#define BIT_GET_AC5_PKT_INFO(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO) & BIT_MASK_AC5_PKT_INFO) +#define BIT_SHIFT_MU_STA_GTAB_POSITION_L 0 +#define BIT_MASK_MU_STA_GTAB_POSITION_L 0xffffffffL +#define BIT_MU_STA_GTAB_POSITION_L(x) \ + (((x) & BIT_MASK_MU_STA_GTAB_POSITION_L) \ + << BIT_SHIFT_MU_STA_GTAB_POSITION_L) +#define BITS_MU_STA_GTAB_POSITION_L \ + (BIT_MASK_MU_STA_GTAB_POSITION_L << BIT_SHIFT_MU_STA_GTAB_POSITION_L) +#define BIT_CLEAR_MU_STA_GTAB_POSITION_L(x) \ + ((x) & (~BITS_MU_STA_GTAB_POSITION_L)) +#define BIT_GET_MU_STA_GTAB_POSITION_L(x) \ + (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_L) & \ + BIT_MASK_MU_STA_GTAB_POSITION_L) +#define BIT_SET_MU_STA_GTAB_POSITION_L(x, v) \ + (BIT_CLEAR_MU_STA_GTAB_POSITION_L(x) | BIT_MU_STA_GTAB_POSITION_L(v)) +#endif -#define BIT_SHIFT_AC4_PKT_INFO 0 -#define BIT_MASK_AC4_PKT_INFO 0xfff -#define BIT_AC4_PKT_INFO(x) (((x) & BIT_MASK_AC4_PKT_INFO) << BIT_SHIFT_AC4_PKT_INFO) -#define BIT_GET_AC4_PKT_INFO(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO) & BIT_MASK_AC4_PKT_INFO) +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_MU_STA_USER_POS_INFO (Offset 0x14C8) */ -/* 2 REG_Q6_Q7_INFO (Offset 0x140C) */ +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_L 0xffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_L(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L) +#define BITS_R_MU_STA_GTAB_POSITION_L \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_L \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_L)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_L(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_L) +#define BIT_SET_R_MU_STA_GTAB_POSITION_L(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_L(x) | \ + BIT_R_MU_STA_GTAB_POSITION_L(v)) +#endif -#define BIT_SHIFT_AC7_PKT_INFO 16 -#define BIT_MASK_AC7_PKT_INFO 0xfff -#define BIT_AC7_PKT_INFO(x) (((x) & BIT_MASK_AC7_PKT_INFO) << BIT_SHIFT_AC7_PKT_INFO) -#define BIT_GET_AC7_PKT_INFO(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO) & BIT_MASK_AC7_PKT_INFO) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_MU_STA_USER_POS_INFO_H (Offset 0x14CC) */ -#define BIT_SHIFT_AC6_PKT_INFO 0 -#define BIT_MASK_AC6_PKT_INFO 0xfff -#define BIT_AC6_PKT_INFO(x) (((x) & BIT_MASK_AC6_PKT_INFO) << BIT_SHIFT_AC6_PKT_INFO) -#define BIT_GET_AC6_PKT_INFO(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO) & BIT_MASK_AC6_PKT_INFO) +#define BIT_SHIFT_MU_STA_GTAB_POSITION_H 0 +#define BIT_MASK_MU_STA_GTAB_POSITION_H 0xffffffffL +#define BIT_MU_STA_GTAB_POSITION_H(x) \ + (((x) & BIT_MASK_MU_STA_GTAB_POSITION_H) \ + << BIT_SHIFT_MU_STA_GTAB_POSITION_H) +#define BITS_MU_STA_GTAB_POSITION_H \ + (BIT_MASK_MU_STA_GTAB_POSITION_H << BIT_SHIFT_MU_STA_GTAB_POSITION_H) +#define BIT_CLEAR_MU_STA_GTAB_POSITION_H(x) \ + ((x) & (~BITS_MU_STA_GTAB_POSITION_H)) +#define BIT_GET_MU_STA_GTAB_POSITION_H(x) \ + (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_H) & \ + BIT_MASK_MU_STA_GTAB_POSITION_H) +#define BIT_SET_MU_STA_GTAB_POSITION_H(x, v) \ + (BIT_CLEAR_MU_STA_GTAB_POSITION_H(x) | BIT_MU_STA_GTAB_POSITION_H(v)) +#endif -/* 2 REG_MGQ_HIQ_INFO (Offset 0x1410) */ +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MU_STA_USER_POS_INFO_H (Offset 0x14CC) */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_H 0xffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_H(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H) +#define BITS_R_MU_STA_GTAB_POSITION_H \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_H \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_H)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_H(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_H) +#define BIT_SET_R_MU_STA_GTAB_POSITION_H(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_H(x) | \ + BIT_R_MU_STA_GTAB_POSITION_H(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ + +#define BIT_MU_DNGCNT_RST BIT(20) -#define BIT_SHIFT_HIQ_PKT_INFO 16 -#define BIT_MASK_HIQ_PKT_INFO 0xfff -#define BIT_HIQ_PKT_INFO(x) (((x) & BIT_MASK_HIQ_PKT_INFO) << BIT_SHIFT_HIQ_PKT_INFO) -#define BIT_GET_HIQ_PKT_INFO(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO) & BIT_MASK_HIQ_PKT_INFO) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_MGQ_PKT_INFO 0 -#define BIT_MASK_MGQ_PKT_INFO 0xfff -#define BIT_MGQ_PKT_INFO(x) (((x) & BIT_MASK_MGQ_PKT_INFO) << BIT_SHIFT_MGQ_PKT_INFO) -#define BIT_GET_MGQ_PKT_INFO(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO) & BIT_MASK_MGQ_PKT_INFO) +/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ +#define BIT_SHIFT_MU_DBGCNT_SEL 16 +#define BIT_MASK_MU_DBGCNT_SEL 0xf +#define BIT_MU_DBGCNT_SEL(x) \ + (((x) & BIT_MASK_MU_DBGCNT_SEL) << BIT_SHIFT_MU_DBGCNT_SEL) +#define BITS_MU_DBGCNT_SEL (BIT_MASK_MU_DBGCNT_SEL << BIT_SHIFT_MU_DBGCNT_SEL) +#define BIT_CLEAR_MU_DBGCNT_SEL(x) ((x) & (~BITS_MU_DBGCNT_SEL)) +#define BIT_GET_MU_DBGCNT_SEL(x) \ + (((x) >> BIT_SHIFT_MU_DBGCNT_SEL) & BIT_MASK_MU_DBGCNT_SEL) +#define BIT_SET_MU_DBGCNT_SEL(x, v) \ + (BIT_CLEAR_MU_DBGCNT_SEL(x) | BIT_MU_DBGCNT_SEL(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */ +#define BIT_CHNL_REF_RXNAV BIT(7) +#define BIT_CHNL_REF_VBON BIT(6) -/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_BCNQ_PKT_INFO_V1 16 -#define BIT_MASK_BCNQ_PKT_INFO_V1 0xfff -#define BIT_BCNQ_PKT_INFO_V1(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_V1) << BIT_SHIFT_BCNQ_PKT_INFO_V1) -#define BIT_GET_BCNQ_PKT_INFO_V1(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1) & BIT_MASK_BCNQ_PKT_INFO_V1) +/* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */ +#define BIT_CHNL_REF_EDCCA BIT(5) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */ +#define BIT_CHNL_REF_EDCA BIT(5) +#define BIT_CHNL_REF_CCA BIT(4) -/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_CMDQ_PKT_INFO 16 -#define BIT_MASK_CMDQ_PKT_INFO 0xfff -#define BIT_CMDQ_PKT_INFO(x) (((x) & BIT_MASK_CMDQ_PKT_INFO) << BIT_SHIFT_CMDQ_PKT_INFO) -#define BIT_GET_CMDQ_PKT_INFO(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO) & BIT_MASK_CMDQ_PKT_INFO) +/* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */ +#define BIT_RST_CHNL_BUSY BIT(3) +#define BIT_RST_CHNL_IDLE BIT(2) +#define BIT_CHNL_INFO_RST BIT(1) +#define BIT_ATM_AIRTIME_EN BIT(0) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ + +#define BIT_SHIFT_MU_DNGCNT 0 +#define BIT_MASK_MU_DNGCNT 0xffff +#define BIT_MU_DNGCNT(x) (((x) & BIT_MASK_MU_DNGCNT) << BIT_SHIFT_MU_DNGCNT) +#define BITS_MU_DNGCNT (BIT_MASK_MU_DNGCNT << BIT_SHIFT_MU_DNGCNT) +#define BIT_CLEAR_MU_DNGCNT(x) ((x) & (~BITS_MU_DNGCNT)) +#define BIT_GET_MU_DNGCNT(x) (((x) >> BIT_SHIFT_MU_DNGCNT) & BIT_MASK_MU_DNGCNT) +#define BIT_SET_MU_DNGCNT(x, v) (BIT_CLEAR_MU_DNGCNT(x) | BIT_MU_DNGCNT(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_CHNL_IDLE_TIME (Offset 0x14D4) */ + +#define BIT_SHIFT_CHNL_IDLE_TIME 0 +#define BIT_MASK_CHNL_IDLE_TIME 0xffffffffL +#define BIT_CHNL_IDLE_TIME(x) \ + (((x) & BIT_MASK_CHNL_IDLE_TIME) << BIT_SHIFT_CHNL_IDLE_TIME) +#define BITS_CHNL_IDLE_TIME \ + (BIT_MASK_CHNL_IDLE_TIME << BIT_SHIFT_CHNL_IDLE_TIME) +#define BIT_CLEAR_CHNL_IDLE_TIME(x) ((x) & (~BITS_CHNL_IDLE_TIME)) +#define BIT_GET_CHNL_IDLE_TIME(x) \ + (((x) >> BIT_SHIFT_CHNL_IDLE_TIME) & BIT_MASK_CHNL_IDLE_TIME) +#define BIT_SET_CHNL_IDLE_TIME(x, v) \ + (BIT_CLEAR_CHNL_IDLE_TIME(x) | BIT_CHNL_IDLE_TIME(v)) + +/* 2 REG_CHNL_BUSY_TIME (Offset 0x14D8) */ + +#define BIT_SHIFT_CHNL_BUSY_TIME 0 +#define BIT_MASK_CHNL_BUSY_TIME 0xffffffffL +#define BIT_CHNL_BUSY_TIME(x) \ + (((x) & BIT_MASK_CHNL_BUSY_TIME) << BIT_SHIFT_CHNL_BUSY_TIME) +#define BITS_CHNL_BUSY_TIME \ + (BIT_MASK_CHNL_BUSY_TIME << BIT_SHIFT_CHNL_BUSY_TIME) +#define BIT_CLEAR_CHNL_BUSY_TIME(x) ((x) & (~BITS_CHNL_BUSY_TIME)) +#define BIT_GET_CHNL_BUSY_TIME(x) \ + (((x) >> BIT_SHIFT_CHNL_BUSY_TIME) & BIT_MASK_CHNL_BUSY_TIME) +#define BIT_SET_CHNL_BUSY_TIME(x, v) \ + (BIT_CLEAR_CHNL_BUSY_TIME(x) | BIT_CHNL_BUSY_TIME(v)) + +#define BIT_SHIFT_BW_CFG 0 +#define BIT_MASK_BW_CFG 0x3 +#define BIT_BW_CFG(x) (((x) & BIT_MASK_BW_CFG) << BIT_SHIFT_BW_CFG) +#define BITS_BW_CFG (BIT_MASK_BW_CFG << BIT_SHIFT_BW_CFG) +#define BIT_CLEAR_BW_CFG(x) ((x) & (~BITS_BW_CFG)) +#define BIT_GET_BW_CFG(x) (((x) >> BIT_SHIFT_BW_CFG) & BIT_MASK_BW_CFG) +#define BIT_SET_BW_CFG(x, v) (BIT_CLEAR_BW_CFG(x) | BIT_BW_CFG(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_MU_TRX_DBG_CNT_V1 (Offset 0x14DC) */ + +#define BIT_FORCE_SND_STS_EN BIT(31) + +#define BIT_SHIFT_SND_STS_VALUE 24 +#define BIT_MASK_SND_STS_VALUE 0x3f +#define BIT_SND_STS_VALUE(x) \ + (((x) & BIT_MASK_SND_STS_VALUE) << BIT_SHIFT_SND_STS_VALUE) +#define BITS_SND_STS_VALUE (BIT_MASK_SND_STS_VALUE << BIT_SHIFT_SND_STS_VALUE) +#define BIT_CLEAR_SND_STS_VALUE(x) ((x) & (~BITS_SND_STS_VALUE)) +#define BIT_GET_SND_STS_VALUE(x) \ + (((x) >> BIT_SHIFT_SND_STS_VALUE) & BIT_MASK_SND_STS_VALUE) +#define BIT_SET_SND_STS_VALUE(x, v) \ + (BIT_CLEAR_SND_STS_VALUE(x) | BIT_SND_STS_VALUE(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MU_TRX_DBG_CNT_V1 (Offset 0x14DC) */ + +#define BIT_SHIFT_MU_DNGCNT_SEL 16 +#define BIT_MASK_MU_DNGCNT_SEL 0xf +#define BIT_MU_DNGCNT_SEL(x) \ + (((x) & BIT_MASK_MU_DNGCNT_SEL) << BIT_SHIFT_MU_DNGCNT_SEL) +#define BITS_MU_DNGCNT_SEL (BIT_MASK_MU_DNGCNT_SEL << BIT_SHIFT_MU_DNGCNT_SEL) +#define BIT_CLEAR_MU_DNGCNT_SEL(x) ((x) & (~BITS_MU_DNGCNT_SEL)) +#define BIT_GET_MU_DNGCNT_SEL(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_SEL) & BIT_MASK_MU_DNGCNT_SEL) +#define BIT_SET_MU_DNGCNT_SEL(x, v) \ + (BIT_CLEAR_MU_DNGCNT_SEL(x) | BIT_MU_DNGCNT_SEL(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) + +/* 2 REG_SWPS_CTRL (Offset 0x14F4) */ + +#define BIT_SHIFT_SWPS_RPT_LENGTH 8 +#define BIT_MASK_SWPS_RPT_LENGTH 0x7f +#define BIT_SWPS_RPT_LENGTH(x) \ + (((x) & BIT_MASK_SWPS_RPT_LENGTH) << BIT_SHIFT_SWPS_RPT_LENGTH) +#define BITS_SWPS_RPT_LENGTH \ + (BIT_MASK_SWPS_RPT_LENGTH << BIT_SHIFT_SWPS_RPT_LENGTH) +#define BIT_CLEAR_SWPS_RPT_LENGTH(x) ((x) & (~BITS_SWPS_RPT_LENGTH)) +#define BIT_GET_SWPS_RPT_LENGTH(x) \ + (((x) >> BIT_SHIFT_SWPS_RPT_LENGTH) & BIT_MASK_SWPS_RPT_LENGTH) +#define BIT_SET_SWPS_RPT_LENGTH(x, v) \ + (BIT_CLEAR_SWPS_RPT_LENGTH(x) | BIT_SWPS_RPT_LENGTH(v)) + +#define BIT_SHIFT_MACID_SWPS_EN_SEL 2 +#define BIT_MASK_MACID_SWPS_EN_SEL 0x3 +#define BIT_MACID_SWPS_EN_SEL(x) \ + (((x) & BIT_MASK_MACID_SWPS_EN_SEL) << BIT_SHIFT_MACID_SWPS_EN_SEL) +#define BITS_MACID_SWPS_EN_SEL \ + (BIT_MASK_MACID_SWPS_EN_SEL << BIT_SHIFT_MACID_SWPS_EN_SEL) +#define BIT_CLEAR_MACID_SWPS_EN_SEL(x) ((x) & (~BITS_MACID_SWPS_EN_SEL)) +#define BIT_GET_MACID_SWPS_EN_SEL(x) \ + (((x) >> BIT_SHIFT_MACID_SWPS_EN_SEL) & BIT_MASK_MACID_SWPS_EN_SEL) +#define BIT_SET_MACID_SWPS_EN_SEL(x, v) \ + (BIT_CLEAR_MACID_SWPS_EN_SEL(x) | BIT_MACID_SWPS_EN_SEL(v)) + +#define BIT_SWPS_MANUALL_POLLING BIT(1) +#define BIT_SWPS_EN BIT(0) + +/* 2 REG_SWPS_PKT_TH (Offset 0x14F6) */ + +#define BIT_SHIFT_SWPS_PKT_TH 0 +#define BIT_MASK_SWPS_PKT_TH 0xffff +#define BIT_SWPS_PKT_TH(x) \ + (((x) & BIT_MASK_SWPS_PKT_TH) << BIT_SHIFT_SWPS_PKT_TH) +#define BITS_SWPS_PKT_TH (BIT_MASK_SWPS_PKT_TH << BIT_SHIFT_SWPS_PKT_TH) +#define BIT_CLEAR_SWPS_PKT_TH(x) ((x) & (~BITS_SWPS_PKT_TH)) +#define BIT_GET_SWPS_PKT_TH(x) \ + (((x) >> BIT_SHIFT_SWPS_PKT_TH) & BIT_MASK_SWPS_PKT_TH) +#define BIT_SET_SWPS_PKT_TH(x, v) \ + (BIT_CLEAR_SWPS_PKT_TH(x) | BIT_SWPS_PKT_TH(v)) + +/* 2 REG_SWPS_TIME_TH (Offset 0x14F8) */ + +#define BIT_SHIFT_SWPS_PSTIME_TH 16 +#define BIT_MASK_SWPS_PSTIME_TH 0xffff +#define BIT_SWPS_PSTIME_TH(x) \ + (((x) & BIT_MASK_SWPS_PSTIME_TH) << BIT_SHIFT_SWPS_PSTIME_TH) +#define BITS_SWPS_PSTIME_TH \ + (BIT_MASK_SWPS_PSTIME_TH << BIT_SHIFT_SWPS_PSTIME_TH) +#define BIT_CLEAR_SWPS_PSTIME_TH(x) ((x) & (~BITS_SWPS_PSTIME_TH)) +#define BIT_GET_SWPS_PSTIME_TH(x) \ + (((x) >> BIT_SHIFT_SWPS_PSTIME_TH) & BIT_MASK_SWPS_PSTIME_TH) +#define BIT_SET_SWPS_PSTIME_TH(x, v) \ + (BIT_CLEAR_SWPS_PSTIME_TH(x) | BIT_SWPS_PSTIME_TH(v)) + +#define BIT_SHIFT_SWPS_TIME_TH 0 +#define BIT_MASK_SWPS_TIME_TH 0xffff +#define BIT_SWPS_TIME_TH(x) \ + (((x) & BIT_MASK_SWPS_TIME_TH) << BIT_SHIFT_SWPS_TIME_TH) +#define BITS_SWPS_TIME_TH (BIT_MASK_SWPS_TIME_TH << BIT_SHIFT_SWPS_TIME_TH) +#define BIT_CLEAR_SWPS_TIME_TH(x) ((x) & (~BITS_SWPS_TIME_TH)) +#define BIT_GET_SWPS_TIME_TH(x) \ + (((x) >> BIT_SHIFT_SWPS_TIME_TH) & BIT_MASK_SWPS_TIME_TH) +#define BIT_SET_SWPS_TIME_TH(x, v) \ + (BIT_CLEAR_SWPS_TIME_TH(x) | BIT_SWPS_TIME_TH(v)) + +/* 2 REG_MACID_SWPS_EN (Offset 0x14FC) */ + +#define BIT_SHIFT_MACID_SWPS_EN 0 +#define BIT_MASK_MACID_SWPS_EN 0xffffffffL +#define BIT_MACID_SWPS_EN(x) \ + (((x) & BIT_MASK_MACID_SWPS_EN) << BIT_SHIFT_MACID_SWPS_EN) +#define BITS_MACID_SWPS_EN (BIT_MASK_MACID_SWPS_EN << BIT_SHIFT_MACID_SWPS_EN) +#define BIT_CLEAR_MACID_SWPS_EN(x) ((x) & (~BITS_MACID_SWPS_EN)) +#define BIT_GET_MACID_SWPS_EN(x) \ + (((x) >> BIT_SHIFT_MACID_SWPS_EN) & BIT_MASK_MACID_SWPS_EN) +#define BIT_SET_MACID_SWPS_EN(x, v) \ + (BIT_CLEAR_MACID_SWPS_EN(x) | BIT_MACID_SWPS_EN(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_PORT_CTRL_SEL (Offset 0x1500) */ + +#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1 4 +#define BIT_MASK_BCN_TIMER_SEL_FWRD_V1 0x7 +#define BIT_BCN_TIMER_SEL_FWRD_V1(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_V1) \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1) +#define BITS_BCN_TIMER_SEL_FWRD_V1 \ + (BIT_MASK_BCN_TIMER_SEL_FWRD_V1 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD_V1)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_V1(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1) & \ + BIT_MASK_BCN_TIMER_SEL_FWRD_V1) +#define BIT_SET_BCN_TIMER_SEL_FWRD_V1(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1(x) | BIT_BCN_TIMER_SEL_FWRD_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_CPUMGQ_TX_TIMER (Offset 0x1500) */ + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_V1 0xffffffffL +#define BIT_CPUMGQ_TX_TIMER_V1(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1) +#define BITS_CPUMGQ_TX_TIMER_V1 \ + (BIT_MASK_CPUMGQ_TX_TIMER_V1 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_V1)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1) +#define BIT_SET_CPUMGQ_TX_TIMER_V1(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) | BIT_CPUMGQ_TX_TIMER_V1(v)) + +#endif -/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +#if (HALMAC_8814B_SUPPORT) -#define BIT_CHNL_REF_RXNAV BIT(7) -#define BIT_CHNL_REF_VBON BIT(6) -#define BIT_CHNL_REF_EDCCA BIT(5) -#define BIT_RST_CHNL_BUSY BIT(3) -#define BIT_RST_CHNL_IDLE BIT(2) -#define BIT_CHNL_INFO_RST BIT(1) +/* 2 REG_PORT_CTRL_SEL (Offset 0x1500) */ -#define BIT_SHIFT_CMDQ_PKT_INFO_V1 0 -#define BIT_MASK_CMDQ_PKT_INFO_V1 0xfff -#define BIT_CMDQ_PKT_INFO_V1(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_V1) << BIT_SHIFT_CMDQ_PKT_INFO_V1) -#define BIT_GET_CMDQ_PKT_INFO_V1(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1) & BIT_MASK_CMDQ_PKT_INFO_V1) +#define BIT_SHIFT_PORT_CTRL_SEL 0 +#define BIT_MASK_PORT_CTRL_SEL 0x7 +#define BIT_PORT_CTRL_SEL(x) \ + (((x) & BIT_MASK_PORT_CTRL_SEL) << BIT_SHIFT_PORT_CTRL_SEL) +#define BITS_PORT_CTRL_SEL (BIT_MASK_PORT_CTRL_SEL << BIT_SHIFT_PORT_CTRL_SEL) +#define BIT_CLEAR_PORT_CTRL_SEL(x) ((x) & (~BITS_PORT_CTRL_SEL)) +#define BIT_GET_PORT_CTRL_SEL(x) \ + (((x) >> BIT_SHIFT_PORT_CTRL_SEL) & BIT_MASK_PORT_CTRL_SEL) +#define BIT_SET_PORT_CTRL_SEL(x, v) \ + (BIT_CLEAR_PORT_CTRL_SEL(x) | BIT_PORT_CTRL_SEL(v)) -#define BIT_ATM_AIRTIME_EN BIT(0) +/* 2 REG_PORT_CTRL_CFG (Offset 0x1501) */ -#define BIT_SHIFT_CHNL_IDLE_TIME 0 -#define BIT_MASK_CHNL_IDLE_TIME 0xffffffffL -#define BIT_CHNL_IDLE_TIME(x) (((x) & BIT_MASK_CHNL_IDLE_TIME) << BIT_SHIFT_CHNL_IDLE_TIME) -#define BIT_GET_CHNL_IDLE_TIME(x) (((x) >> BIT_SHIFT_CHNL_IDLE_TIME) & BIT_MASK_CHNL_IDLE_TIME) +#define BIT_BCNERR_CNT_EN_V1 BIT(11) +#define BIT_DIS_TRX_CAL_BCN_V1 BIT(10) +#define BIT_DIS_TX_CAL_TBTT_V1 BIT(9) +#define BIT_BCN_AGGRESSION_V1 BIT(8) +#define BIT_TSFTR_RST_V1 BIT(7) +#define BIT_EN_TXBCN_RPT_V1 BIT(5) +#define BIT_EN_PORT_FUNCTION BIT(3) +#define BIT_EN_RXBCN_RPT BIT(2) +/* 2 REG_TBTT_PROHIBIT_CFG (Offset 0x1504) */ -#define BIT_SHIFT_CHNL_BUSY_TIME 0 -#define BIT_MASK_CHNL_BUSY_TIME 0xffffffffL -#define BIT_CHNL_BUSY_TIME(x) (((x) & BIT_MASK_CHNL_BUSY_TIME) << BIT_SHIFT_CHNL_BUSY_TIME) -#define BIT_GET_CHNL_BUSY_TIME(x) (((x) >> BIT_SHIFT_CHNL_BUSY_TIME) & BIT_MASK_CHNL_BUSY_TIME) +#define BIT_MASK_PROHIBIT BIT(23) +#define BIT_SHIFT_TBTT_HOLD_TIME 8 +#define BIT_MASK_TBTT_HOLD_TIME 0xfff +#define BIT_TBTT_HOLD_TIME(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME) << BIT_SHIFT_TBTT_HOLD_TIME) +#define BITS_TBTT_HOLD_TIME \ + (BIT_MASK_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME) +#define BIT_CLEAR_TBTT_HOLD_TIME(x) ((x) & (~BITS_TBTT_HOLD_TIME)) +#define BIT_GET_TBTT_HOLD_TIME(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME) & BIT_MASK_TBTT_HOLD_TIME) +#define BIT_SET_TBTT_HOLD_TIME(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME(x) | BIT_TBTT_HOLD_TIME(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PS_TIMER_A (Offset 0x1504) */ +#define BIT_SHIFT_PS_TIMER_A_V1 0 +#define BIT_MASK_PS_TIMER_A_V1 0xffffffffL +#define BIT_PS_TIMER_A_V1(x) \ + (((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1) +#define BITS_PS_TIMER_A_V1 (BIT_MASK_PS_TIMER_A_V1 << BIT_SHIFT_PS_TIMER_A_V1) +#define BIT_CLEAR_PS_TIMER_A_V1(x) ((x) & (~BITS_PS_TIMER_A_V1)) +#define BIT_GET_PS_TIMER_A_V1(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1) +#define BIT_SET_PS_TIMER_A_V1(x, v) \ + (BIT_CLEAR_PS_TIMER_A_V1(x) | BIT_PS_TIMER_A_V1(v)) -/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +/* 2 REG_PS_TIMER_B (Offset 0x1508) */ +#define BIT_SHIFT_PS_TIMER_B_V1 0 +#define BIT_MASK_PS_TIMER_B_V1 0xffffffffL +#define BIT_PS_TIMER_B_V1(x) \ + (((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1) +#define BITS_PS_TIMER_B_V1 (BIT_MASK_PS_TIMER_B_V1 << BIT_SHIFT_PS_TIMER_B_V1) +#define BIT_CLEAR_PS_TIMER_B_V1(x) ((x) & (~BITS_PS_TIMER_B_V1)) +#define BIT_GET_PS_TIMER_B_V1(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1) +#define BIT_SET_PS_TIMER_B_V1(x, v) \ + (BIT_CLEAR_PS_TIMER_B_V1(x) | BIT_PS_TIMER_B_V1(v)) -#define BIT_SHIFT_BCNQ_PKT_INFO 0 -#define BIT_MASK_BCNQ_PKT_INFO 0xfff -#define BIT_BCNQ_PKT_INFO(x) (((x) & BIT_MASK_BCNQ_PKT_INFO) << BIT_SHIFT_BCNQ_PKT_INFO) -#define BIT_GET_BCNQ_PKT_INFO(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO) & BIT_MASK_BCNQ_PKT_INFO) +/* 2 REG_PS_TIMER_C (Offset 0x150C) */ +#define BIT_SHIFT_PS_TIMER_C_V1 0 +#define BIT_MASK_PS_TIMER_C_V1 0xffffffffL +#define BIT_PS_TIMER_C_V1(x) \ + (((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1) +#define BITS_PS_TIMER_C_V1 (BIT_MASK_PS_TIMER_C_V1 << BIT_SHIFT_PS_TIMER_C_V1) +#define BIT_CLEAR_PS_TIMER_C_V1(x) ((x) & (~BITS_PS_TIMER_C_V1)) +#define BIT_GET_PS_TIMER_C_V1(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1) +#define BIT_SET_PS_TIMER_C_V1(x, v) \ + (BIT_CLEAR_PS_TIMER_C_V1(x) | BIT_PS_TIMER_C_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_TSFTR_SYNC_OFFSET_CFG (Offset 0x150C) */ -/* 2 REG_USEREG_SETTING (Offset 0x1420) */ +#define BIT_SHIFT_TSFTR_SNC_OFFSET_V1 0 +#define BIT_MASK_TSFTR_SNC_OFFSET_V1 0xffffff +#define BIT_TSFTR_SNC_OFFSET_V1(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET_V1) << BIT_SHIFT_TSFTR_SNC_OFFSET_V1) +#define BITS_TSFTR_SNC_OFFSET_V1 \ + (BIT_MASK_TSFTR_SNC_OFFSET_V1 << BIT_SHIFT_TSFTR_SNC_OFFSET_V1) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_V1(x) ((x) & (~BITS_TSFTR_SNC_OFFSET_V1)) +#define BIT_GET_TSFTR_SNC_OFFSET_V1(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_V1) & BIT_MASK_TSFTR_SNC_OFFSET_V1) +#define BIT_SET_TSFTR_SNC_OFFSET_V1(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET_V1(x) | BIT_TSFTR_SNC_OFFSET_V1(v)) -#define BIT_NDPA_USEREG BIT(21) +/* 2 REG_TSFTR_SYNC_CTRL_CFG (Offset 0x150F) */ -#define BIT_SHIFT_RETRY_USEREG 19 -#define BIT_MASK_RETRY_USEREG 0x3 -#define BIT_RETRY_USEREG(x) (((x) & BIT_MASK_RETRY_USEREG) << BIT_SHIFT_RETRY_USEREG) -#define BIT_GET_RETRY_USEREG(x) (((x) >> BIT_SHIFT_RETRY_USEREG) & BIT_MASK_RETRY_USEREG) +#define BIT_SYNC_TSF_NOW_V1 BIT(5) +#define BIT_SYNC_TSF_ONCE BIT(4) +#define BIT_SYNC_TSF_AUTO BIT(3) +#define BIT_SHIFT_SYNC_PORT_SEL 0 +#define BIT_MASK_SYNC_PORT_SEL 0x7 +#define BIT_SYNC_PORT_SEL(x) \ + (((x) & BIT_MASK_SYNC_PORT_SEL) << BIT_SHIFT_SYNC_PORT_SEL) +#define BITS_SYNC_PORT_SEL (BIT_MASK_SYNC_PORT_SEL << BIT_SHIFT_SYNC_PORT_SEL) +#define BIT_CLEAR_SYNC_PORT_SEL(x) ((x) & (~BITS_SYNC_PORT_SEL)) +#define BIT_GET_SYNC_PORT_SEL(x) \ + (((x) >> BIT_SHIFT_SYNC_PORT_SEL) & BIT_MASK_SYNC_PORT_SEL) +#define BIT_SET_SYNC_PORT_SEL(x, v) \ + (BIT_CLEAR_SYNC_PORT_SEL(x) | BIT_SYNC_PORT_SEL(v)) -#define BIT_SHIFT_TRYPKT_USEREG 17 -#define BIT_MASK_TRYPKT_USEREG 0x3 -#define BIT_TRYPKT_USEREG(x) (((x) & BIT_MASK_TRYPKT_USEREG) << BIT_SHIFT_TRYPKT_USEREG) -#define BIT_GET_TRYPKT_USEREG(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG) & BIT_MASK_TRYPKT_USEREG) +#endif -#define BIT_CTLPKT_USEREG BIT(16) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_AESIV_SETTING (Offset 0x1424) */ +/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL (Offset 0x1510) */ +#define BIT_CPUMGQ_TIMER_EN BIT(31) +#define BIT_CPUMGQ_TX_EN BIT(28) + +#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL 24 +#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL 0x7 +#define BIT_CPUMGQ_TIMER_TSF_SEL(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) +#define BITS_CPUMGQ_TIMER_TSF_SEL \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) | BIT_CPUMGQ_TIMER_TSF_SEL(v)) + +#define BIT_PS_TIMER_C_EN BIT(23) + +#define BIT_SHIFT_PS_TIMER_C_TSF_SEL 16 +#define BIT_MASK_PS_TIMER_C_TSF_SEL 0x7 +#define BIT_PS_TIMER_C_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL) +#define BITS_PS_TIMER_C_TSF_SEL \ + (BIT_MASK_PS_TIMER_C_TSF_SEL << BIT_SHIFT_PS_TIMER_C_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_C_TSF_SEL)) +#define BIT_GET_PS_TIMER_C_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL) +#define BIT_SET_PS_TIMER_C_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) | BIT_PS_TIMER_C_TSF_SEL(v)) + +#define BIT_PS_TIMER_B_EN BIT(15) + +#define BIT_SHIFT_PS_TIMER_B_TSF_SEL 8 +#define BIT_MASK_PS_TIMER_B_TSF_SEL 0x7 +#define BIT_PS_TIMER_B_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL) +#define BITS_PS_TIMER_B_TSF_SEL \ + (BIT_MASK_PS_TIMER_B_TSF_SEL << BIT_SHIFT_PS_TIMER_B_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_B_TSF_SEL)) +#define BIT_GET_PS_TIMER_B_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL) +#define BIT_SET_PS_TIMER_B_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) | BIT_PS_TIMER_B_TSF_SEL(v)) + +#define BIT_PS_TIMER_A_EN BIT(7) + +#define BIT_SHIFT_PS_TIMER_A_TSF_SEL 0 +#define BIT_MASK_PS_TIMER_A_TSF_SEL 0x7 +#define BIT_PS_TIMER_A_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL) +#define BITS_PS_TIMER_A_TSF_SEL \ + (BIT_MASK_PS_TIMER_A_TSF_SEL << BIT_SHIFT_PS_TIMER_A_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_A_TSF_SEL)) +#define BIT_GET_PS_TIMER_A_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL) +#define BIT_SET_PS_TIMER_A_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) | BIT_PS_TIMER_A_TSF_SEL(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_BCN_SPACE_CFG (Offset 0x1510) */ + +#define BIT_SHIFT_BCN_SPACE 0 +#define BIT_MASK_BCN_SPACE 0xffff +#define BIT_BCN_SPACE(x) (((x) & BIT_MASK_BCN_SPACE) << BIT_SHIFT_BCN_SPACE) +#define BITS_BCN_SPACE (BIT_MASK_BCN_SPACE << BIT_SHIFT_BCN_SPACE) +#define BIT_CLEAR_BCN_SPACE(x) ((x) & (~BITS_BCN_SPACE)) +#define BIT_GET_BCN_SPACE(x) (((x) >> BIT_SHIFT_BCN_SPACE) & BIT_MASK_BCN_SPACE) +#define BIT_SET_BCN_SPACE(x, v) (BIT_CLEAR_BCN_SPACE(x) | BIT_BCN_SPACE(v)) + +/* 2 REG_EARLY_INT_ADJUST_CFG (Offset 0x1512) */ + +#define BIT_SHIFT_EARLY_INT_ADJUST 0 +#define BIT_MASK_EARLY_INT_ADJUST 0xffff +#define BIT_EARLY_INT_ADJUST(x) \ + (((x) & BIT_MASK_EARLY_INT_ADJUST) << BIT_SHIFT_EARLY_INT_ADJUST) +#define BITS_EARLY_INT_ADJUST \ + (BIT_MASK_EARLY_INT_ADJUST << BIT_SHIFT_EARLY_INT_ADJUST) +#define BIT_CLEAR_EARLY_INT_ADJUST(x) ((x) & (~BITS_EARLY_INT_ADJUST)) +#define BIT_GET_EARLY_INT_ADJUST(x) \ + (((x) >> BIT_SHIFT_EARLY_INT_ADJUST) & BIT_MASK_EARLY_INT_ADJUST) +#define BIT_SET_EARLY_INT_ADJUST(x, v) \ + (BIT_CLEAR_EARLY_INT_ADJUST(x) | BIT_EARLY_INT_ADJUST(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AESIV_OFFSET 0 -#define BIT_MASK_AESIV_OFFSET 0xfff -#define BIT_AESIV_OFFSET(x) (((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET) -#define BIT_GET_AESIV_OFFSET(x) (((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET) +/* 2 REG_CPUMGQ_TX_TIMER_EARLY (Offset 0x1514) */ +#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY 0xff +#define BIT_CPUMGQ_TX_TIMER_EARLY(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) +#define BITS_CPUMGQ_TX_TIMER_EARLY \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) | BIT_CPUMGQ_TX_TIMER_EARLY(v)) -/* 2 REG_BF0_TIME_SETTING (Offset 0x1428) */ +/* 2 REG_PS_TIMER_A_EARLY (Offset 0x1515) */ -#define BIT_BF0_TIMER_SET BIT(31) -#define BIT_BF0_TIMER_CLR BIT(30) -#define BIT_BF0_UPDATE_EN BIT(29) -#define BIT_BF0_TIMER_EN BIT(28) +#define BIT_SHIFT_PS_TIMER_A_EARLY 0 +#define BIT_MASK_PS_TIMER_A_EARLY 0xff +#define BIT_PS_TIMER_A_EARLY(x) \ + (((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY) +#define BITS_PS_TIMER_A_EARLY \ + (BIT_MASK_PS_TIMER_A_EARLY << BIT_SHIFT_PS_TIMER_A_EARLY) +#define BIT_CLEAR_PS_TIMER_A_EARLY(x) ((x) & (~BITS_PS_TIMER_A_EARLY)) +#define BIT_GET_PS_TIMER_A_EARLY(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY) +#define BIT_SET_PS_TIMER_A_EARLY(x, v) \ + (BIT_CLEAR_PS_TIMER_A_EARLY(x) | BIT_PS_TIMER_A_EARLY(v)) -#define BIT_SHIFT_BF0_PRETIME_OVER 16 -#define BIT_MASK_BF0_PRETIME_OVER 0xfff -#define BIT_BF0_PRETIME_OVER(x) (((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER) -#define BIT_GET_BF0_PRETIME_OVER(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER) +/* 2 REG_PS_TIMER_B_EARLY (Offset 0x1516) */ +#define BIT_SHIFT_PS_TIMER_B_EARLY 0 +#define BIT_MASK_PS_TIMER_B_EARLY 0xff +#define BIT_PS_TIMER_B_EARLY(x) \ + (((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY) +#define BITS_PS_TIMER_B_EARLY \ + (BIT_MASK_PS_TIMER_B_EARLY << BIT_SHIFT_PS_TIMER_B_EARLY) +#define BIT_CLEAR_PS_TIMER_B_EARLY(x) ((x) & (~BITS_PS_TIMER_B_EARLY)) +#define BIT_GET_PS_TIMER_B_EARLY(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY) +#define BIT_SET_PS_TIMER_B_EARLY(x, v) \ + (BIT_CLEAR_PS_TIMER_B_EARLY(x) | BIT_PS_TIMER_B_EARLY(v)) -#define BIT_SHIFT_BF0_LIFETIME 0 -#define BIT_MASK_BF0_LIFETIME 0xffff -#define BIT_BF0_LIFETIME(x) (((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME) -#define BIT_GET_BF0_LIFETIME(x) (((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME) +/* 2 REG_PS_TIMER_C_EARLY (Offset 0x1517) */ +#define BIT_SHIFT_PS_TIMER_C_EARLY 0 +#define BIT_MASK_PS_TIMER_C_EARLY 0xff +#define BIT_PS_TIMER_C_EARLY(x) \ + (((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY) +#define BITS_PS_TIMER_C_EARLY \ + (BIT_MASK_PS_TIMER_C_EARLY << BIT_SHIFT_PS_TIMER_C_EARLY) +#define BIT_CLEAR_PS_TIMER_C_EARLY(x) ((x) & (~BITS_PS_TIMER_C_EARLY)) +#define BIT_GET_PS_TIMER_C_EARLY(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY) +#define BIT_SET_PS_TIMER_C_EARLY(x, v) \ + (BIT_CLEAR_PS_TIMER_C_EARLY(x) | BIT_PS_TIMER_C_EARLY(v)) -/* 2 REG_BF1_TIME_SETTING (Offset 0x142C) */ +#endif -#define BIT_BF1_TIMER_SET BIT(31) -#define BIT_BF1_TIMER_CLR BIT(30) -#define BIT_BF1_UPDATE_EN BIT(29) -#define BIT_BF1_TIMER_EN BIT(28) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_BF1_PRETIME_OVER 16 -#define BIT_MASK_BF1_PRETIME_OVER 0xfff -#define BIT_BF1_PRETIME_OVER(x) (((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER) -#define BIT_GET_BF1_PRETIME_OVER(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER) +/* 2 REG_CPUMGQ_PARAMETER (Offset 0x1518) */ +#define BIT_STOP_CPUMGQ BIT(16) -#define BIT_SHIFT_BF1_LIFETIME 0 -#define BIT_MASK_BF1_LIFETIME 0xffff -#define BIT_BF1_LIFETIME(x) (((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME) -#define BIT_GET_BF1_LIFETIME(x) (((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME) +#define BIT_SHIFT_CPUMGQ_PARAMETER 0 +#define BIT_MASK_CPUMGQ_PARAMETER 0xffff +#define BIT_CPUMGQ_PARAMETER(x) \ + (((x) & BIT_MASK_CPUMGQ_PARAMETER) << BIT_SHIFT_CPUMGQ_PARAMETER) +#define BITS_CPUMGQ_PARAMETER \ + (BIT_MASK_CPUMGQ_PARAMETER << BIT_SHIFT_CPUMGQ_PARAMETER) +#define BIT_CLEAR_CPUMGQ_PARAMETER(x) ((x) & (~BITS_CPUMGQ_PARAMETER)) +#define BIT_GET_CPUMGQ_PARAMETER(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER) & BIT_MASK_CPUMGQ_PARAMETER) +#define BIT_SET_CPUMGQ_PARAMETER(x, v) \ + (BIT_CLEAR_CPUMGQ_PARAMETER(x) | BIT_CPUMGQ_PARAMETER(v)) +#endif -/* 2 REG_BF_TIMEOUT_EN (Offset 0x1430) */ +#if (HALMAC_8814B_SUPPORT) -#define BIT_EN_VHT_LDPC BIT(9) -#define BIT_EN_HT_LDPC BIT(8) -#define BIT_BF1_TIMEOUT_EN BIT(1) -#define BIT_BF0_TIMEOUT_EN BIT(0) +/* 2 REG_SW_TBTT_TSF_INFO (Offset 0x151C) */ -/* 2 REG_MACID_RELEASE0 (Offset 0x1434) */ +#define BIT_SHIFT_SW_TBTT_TSF_INFO 0 +#define BIT_MASK_SW_TBTT_TSF_INFO 0xffffffffL +#define BIT_SW_TBTT_TSF_INFO(x) \ + (((x) & BIT_MASK_SW_TBTT_TSF_INFO) << BIT_SHIFT_SW_TBTT_TSF_INFO) +#define BITS_SW_TBTT_TSF_INFO \ + (BIT_MASK_SW_TBTT_TSF_INFO << BIT_SHIFT_SW_TBTT_TSF_INFO) +#define BIT_CLEAR_SW_TBTT_TSF_INFO(x) ((x) & (~BITS_SW_TBTT_TSF_INFO)) +#define BIT_GET_SW_TBTT_TSF_INFO(x) \ + (((x) >> BIT_SHIFT_SW_TBTT_TSF_INFO) & BIT_MASK_SW_TBTT_TSF_INFO) +#define BIT_SET_SW_TBTT_TSF_INFO(x, v) \ + (BIT_CLEAR_SW_TBTT_TSF_INFO(x) | BIT_SW_TBTT_TSF_INFO(v)) +#endif -#define BIT_SHIFT_MACID31_0_RELEASE 0 -#define BIT_MASK_MACID31_0_RELEASE 0xffffffffL -#define BIT_MACID31_0_RELEASE(x) (((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE) -#define BIT_GET_MACID31_0_RELEASE(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE) +#if (HALMAC_8822C_SUPPORT) +/* 2 REG_TSF_SYNC_ADJ (Offset 0x1520) */ -/* 2 REG_MACID_RELEASE1 (Offset 0x1438) */ +#define BIT_SHIFT_R_P0_TSFT_ADJ_VAL 16 +#define BIT_MASK_R_P0_TSFT_ADJ_VAL 0xffff +#define BIT_R_P0_TSFT_ADJ_VAL(x) \ + (((x) & BIT_MASK_R_P0_TSFT_ADJ_VAL) << BIT_SHIFT_R_P0_TSFT_ADJ_VAL) +#define BITS_R_P0_TSFT_ADJ_VAL \ + (BIT_MASK_R_P0_TSFT_ADJ_VAL << BIT_SHIFT_R_P0_TSFT_ADJ_VAL) +#define BIT_CLEAR_R_P0_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_P0_TSFT_ADJ_VAL)) +#define BIT_GET_R_P0_TSFT_ADJ_VAL(x) \ + (((x) >> BIT_SHIFT_R_P0_TSFT_ADJ_VAL) & BIT_MASK_R_P0_TSFT_ADJ_VAL) +#define BIT_SET_R_P0_TSFT_ADJ_VAL(x, v) \ + (BIT_CLEAR_R_P0_TSFT_ADJ_VAL(x) | BIT_R_P0_TSFT_ADJ_VAL(v)) +#define BIT_R_X_COMP_Y_OVER BIT(8) -#define BIT_SHIFT_MACID63_32_RELEASE 0 -#define BIT_MASK_MACID63_32_RELEASE 0xffffffffL -#define BIT_MACID63_32_RELEASE(x) (((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE) -#define BIT_GET_MACID63_32_RELEASE(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_MACID_RELEASE2 (Offset 0x143C) */ +/* 2 REG_TSF_SYN_CTRL0 (Offset 0x1520) */ +#define BIT_TSF_SYNC_COMPARE_POLLING BIT(7) +#define BIT_TSF_SYNC_POLLING BIT(6) -#define BIT_SHIFT_MACID95_64_RELEASE 0 -#define BIT_MASK_MACID95_64_RELEASE 0xffffffffL -#define BIT_MACID95_64_RELEASE(x) (((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE) -#define BIT_GET_MACID95_64_RELEASE(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE) +#define BIT_SHIFT_TSF_SYNC_DUT 3 +#define BIT_MASK_TSF_SYNC_DUT 0x7 +#define BIT_TSF_SYNC_DUT(x) \ + (((x) & BIT_MASK_TSF_SYNC_DUT) << BIT_SHIFT_TSF_SYNC_DUT) +#define BITS_TSF_SYNC_DUT (BIT_MASK_TSF_SYNC_DUT << BIT_SHIFT_TSF_SYNC_DUT) +#define BIT_CLEAR_TSF_SYNC_DUT(x) ((x) & (~BITS_TSF_SYNC_DUT)) +#define BIT_GET_TSF_SYNC_DUT(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_DUT) & BIT_MASK_TSF_SYNC_DUT) +#define BIT_SET_TSF_SYNC_DUT(x, v) \ + (BIT_CLEAR_TSF_SYNC_DUT(x) | BIT_TSF_SYNC_DUT(v)) +#endif -/* 2 REG_MACID_RELEASE3 (Offset 0x1440) */ +#if (HALMAC_8822C_SUPPORT) +/* 2 REG_TSF_SYNC_ADJ (Offset 0x1520) */ -#define BIT_SHIFT_MACID127_96_RELEASE 0 -#define BIT_MASK_MACID127_96_RELEASE 0xffffffffL -#define BIT_MACID127_96_RELEASE(x) (((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE) -#define BIT_GET_MACID127_96_RELEASE(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE) +#define BIT_SHIFT_R_X_SYNC_SEL 3 +#define BIT_MASK_R_X_SYNC_SEL 0x7 +#define BIT_R_X_SYNC_SEL(x) \ + (((x) & BIT_MASK_R_X_SYNC_SEL) << BIT_SHIFT_R_X_SYNC_SEL) +#define BITS_R_X_SYNC_SEL (BIT_MASK_R_X_SYNC_SEL << BIT_SHIFT_R_X_SYNC_SEL) +#define BIT_CLEAR_R_X_SYNC_SEL(x) ((x) & (~BITS_R_X_SYNC_SEL)) +#define BIT_GET_R_X_SYNC_SEL(x) \ + (((x) >> BIT_SHIFT_R_X_SYNC_SEL) & BIT_MASK_R_X_SYNC_SEL) +#define BIT_SET_R_X_SYNC_SEL(x, v) \ + (BIT_CLEAR_R_X_SYNC_SEL(x) | BIT_R_X_SYNC_SEL(v)) +#endif -/* 2 REG_MACID_RELEASE_SETTING (Offset 0x1444) */ +#if (HALMAC_8198F_SUPPORT) -#define BIT_MACID_VALUE BIT(7) +/* 2 REG_TSF_SYN_CTRL0 (Offset 0x1520) */ -#define BIT_SHIFT_MACID_OFFSET 0 -#define BIT_MASK_MACID_OFFSET 0x7f -#define BIT_MACID_OFFSET(x) (((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET) -#define BIT_GET_MACID_OFFSET(x) (((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET) +#define BIT_SHIFT_TSF_SYNC_SOURCE 0 +#define BIT_MASK_TSF_SYNC_SOURCE 0x7 +#define BIT_TSF_SYNC_SOURCE(x) \ + (((x) & BIT_MASK_TSF_SYNC_SOURCE) << BIT_SHIFT_TSF_SYNC_SOURCE) +#define BITS_TSF_SYNC_SOURCE \ + (BIT_MASK_TSF_SYNC_SOURCE << BIT_SHIFT_TSF_SYNC_SOURCE) +#define BIT_CLEAR_TSF_SYNC_SOURCE(x) ((x) & (~BITS_TSF_SYNC_SOURCE)) +#define BIT_GET_TSF_SYNC_SOURCE(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_SOURCE) & BIT_MASK_TSF_SYNC_SOURCE) +#define BIT_SET_TSF_SYNC_SOURCE(x, v) \ + (BIT_CLEAR_TSF_SYNC_SOURCE(x) | BIT_TSF_SYNC_SOURCE(v)) +#define BIT_TSF_SYNC_SIGNAL BIT(0) -/* 2 REG_FAST_EDCA_VOVI_SETTING (Offset 0x1448) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_VI_FAST_EDCA_TO 24 -#define BIT_MASK_VI_FAST_EDCA_TO 0xff -#define BIT_VI_FAST_EDCA_TO(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO) -#define BIT_GET_VI_FAST_EDCA_TO(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO) +/* 2 REG_TSFTR_LOW (Offset 0x1520) */ -#define BIT_VI_THRESHOLD_SEL BIT(23) +#define BIT_SHIFT_TSF_TIMER_LOW 0 +#define BIT_MASK_TSF_TIMER_LOW 0xffffffffL +#define BIT_TSF_TIMER_LOW(x) \ + (((x) & BIT_MASK_TSF_TIMER_LOW) << BIT_SHIFT_TSF_TIMER_LOW) +#define BITS_TSF_TIMER_LOW (BIT_MASK_TSF_TIMER_LOW << BIT_SHIFT_TSF_TIMER_LOW) +#define BIT_CLEAR_TSF_TIMER_LOW(x) ((x) & (~BITS_TSF_TIMER_LOW)) +#define BIT_GET_TSF_TIMER_LOW(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_LOW) & BIT_MASK_TSF_TIMER_LOW) +#define BIT_SET_TSF_TIMER_LOW(x, v) \ + (BIT_CLEAR_TSF_TIMER_LOW(x) | BIT_TSF_TIMER_LOW(v)) -#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH 16 -#define BIT_MASK_VI_FAST_EDCA_PKT_TH 0x7f -#define BIT_VI_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH) -#define BIT_GET_VI_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH) +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_VO_FAST_EDCA_TO 8 -#define BIT_MASK_VO_FAST_EDCA_TO 0xff -#define BIT_VO_FAST_EDCA_TO(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO) -#define BIT_GET_VO_FAST_EDCA_TO(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO) +/* 2 REG_TSF_SYNC_ADJ (Offset 0x1520) */ -#define BIT_VO_THRESHOLD_SEL BIT(7) +#define BIT_SHIFT_R_SYNC_Y_SEL 0 +#define BIT_MASK_R_SYNC_Y_SEL 0x7 +#define BIT_R_SYNC_Y_SEL(x) \ + (((x) & BIT_MASK_R_SYNC_Y_SEL) << BIT_SHIFT_R_SYNC_Y_SEL) +#define BITS_R_SYNC_Y_SEL (BIT_MASK_R_SYNC_Y_SEL << BIT_SHIFT_R_SYNC_Y_SEL) +#define BIT_CLEAR_R_SYNC_Y_SEL(x) ((x) & (~BITS_R_SYNC_Y_SEL)) +#define BIT_GET_R_SYNC_Y_SEL(x) \ + (((x) >> BIT_SHIFT_R_SYNC_Y_SEL) & BIT_MASK_R_SYNC_Y_SEL) +#define BIT_SET_R_SYNC_Y_SEL(x, v) \ + (BIT_CLEAR_R_SYNC_Y_SEL(x) | BIT_R_SYNC_Y_SEL(v)) -#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH 0 -#define BIT_MASK_VO_FAST_EDCA_PKT_TH 0x7f -#define BIT_VO_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH) -#define BIT_GET_VO_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FAST_EDCA_BEBK_SETTING (Offset 0x144C) */ +/* 2 REG_TSF_SYN_OFFSET0 (Offset 0x1522) */ +#define BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0 0 +#define BIT_MASK_TSF_SYNC_INTERVAL_PORT0 0xffff +#define BIT_TSF_SYNC_INTERVAL_PORT0(x) \ + (((x) & BIT_MASK_TSF_SYNC_INTERVAL_PORT0) \ + << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0) +#define BITS_TSF_SYNC_INTERVAL_PORT0 \ + (BIT_MASK_TSF_SYNC_INTERVAL_PORT0 << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0) +#define BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0(x) \ + ((x) & (~BITS_TSF_SYNC_INTERVAL_PORT0)) +#define BIT_GET_TSF_SYNC_INTERVAL_PORT0(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0) & \ + BIT_MASK_TSF_SYNC_INTERVAL_PORT0) +#define BIT_SET_TSF_SYNC_INTERVAL_PORT0(x, v) \ + (BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0(x) | BIT_TSF_SYNC_INTERVAL_PORT0(v)) -#define BIT_SHIFT_BK_FAST_EDCA_TO 24 -#define BIT_MASK_BK_FAST_EDCA_TO 0xff -#define BIT_BK_FAST_EDCA_TO(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO) -#define BIT_GET_BK_FAST_EDCA_TO(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO) +/* 2 REG_TSF_SYN_OFFSET1 (Offset 0x1524) */ -#define BIT_BK_THRESHOLD_SEL BIT(23) +#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1 16 +#define BIT_MASK_TSF_SYNC_INTERVAL_CLI1 0xffff +#define BIT_TSF_SYNC_INTERVAL_CLI1(x) \ + (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI1) \ + << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) +#define BITS_TSF_SYNC_INTERVAL_CLI1 \ + (BIT_MASK_TSF_SYNC_INTERVAL_CLI1 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) +#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x) \ + ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI1)) +#define BIT_GET_TSF_SYNC_INTERVAL_CLI1(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) & \ + BIT_MASK_TSF_SYNC_INTERVAL_CLI1) +#define BIT_SET_TSF_SYNC_INTERVAL_CLI1(x, v) \ + (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x) | BIT_TSF_SYNC_INTERVAL_CLI1(v)) -#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH 16 -#define BIT_MASK_BK_FAST_EDCA_PKT_TH 0x7f -#define BIT_BK_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH) -#define BIT_GET_BK_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH) +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BE_FAST_EDCA_TO 8 -#define BIT_MASK_BE_FAST_EDCA_TO 0xff -#define BIT_BE_FAST_EDCA_TO(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO) -#define BIT_GET_BE_FAST_EDCA_TO(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO) +/* 2 REG_TSF_ADJ_VLAUE (Offset 0x1524) */ -#define BIT_BE_THRESHOLD_SEL BIT(7) +#define BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL 16 +#define BIT_MASK_R_CLI1_TSFT_ADJ_VAL 0xffff +#define BIT_R_CLI1_TSFT_ADJ_VAL(x) \ + (((x) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL) +#define BITS_R_CLI1_TSFT_ADJ_VAL \ + (BIT_MASK_R_CLI1_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL) +#define BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI1_TSFT_ADJ_VAL)) +#define BIT_GET_R_CLI1_TSFT_ADJ_VAL(x) \ + (((x) >> BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL) +#define BIT_SET_R_CLI1_TSFT_ADJ_VAL(x, v) \ + (BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL(x) | BIT_R_CLI1_TSFT_ADJ_VAL(v)) -#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH 0 -#define BIT_MASK_BE_FAST_EDCA_PKT_TH 0x7f -#define BIT_BE_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH) -#define BIT_GET_BE_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_MACID_DROP0 (Offset 0x1450) */ +/* 2 REG_TSF_SYN_OFFSET1 (Offset 0x1524) */ +#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0 0 +#define BIT_MASK_TSF_SYNC_INTERVAL_CLI0 0xffff +#define BIT_TSF_SYNC_INTERVAL_CLI0(x) \ + (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI0) \ + << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) +#define BITS_TSF_SYNC_INTERVAL_CLI0 \ + (BIT_MASK_TSF_SYNC_INTERVAL_CLI0 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) +#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x) \ + ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI0)) +#define BIT_GET_TSF_SYNC_INTERVAL_CLI0(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) & \ + BIT_MASK_TSF_SYNC_INTERVAL_CLI0) +#define BIT_SET_TSF_SYNC_INTERVAL_CLI0(x, v) \ + (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x) | BIT_TSF_SYNC_INTERVAL_CLI0(v)) -#define BIT_SHIFT_MACID31_0_DROP 0 -#define BIT_MASK_MACID31_0_DROP 0xffffffffL -#define BIT_MACID31_0_DROP(x) (((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP) -#define BIT_GET_MACID31_0_DROP(x) (((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_MACID_DROP1 (Offset 0x1454) */ +/* 2 REG_TSFTR_HIGH (Offset 0x1524) */ +#define BIT_SHIFT_TSF_TIMER_HIGH 0 +#define BIT_MASK_TSF_TIMER_HIGH 0xffffffffL +#define BIT_TSF_TIMER_HIGH(x) \ + (((x) & BIT_MASK_TSF_TIMER_HIGH) << BIT_SHIFT_TSF_TIMER_HIGH) +#define BITS_TSF_TIMER_HIGH \ + (BIT_MASK_TSF_TIMER_HIGH << BIT_SHIFT_TSF_TIMER_HIGH) +#define BIT_CLEAR_TSF_TIMER_HIGH(x) ((x) & (~BITS_TSF_TIMER_HIGH)) +#define BIT_GET_TSF_TIMER_HIGH(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_HIGH) & BIT_MASK_TSF_TIMER_HIGH) +#define BIT_SET_TSF_TIMER_HIGH(x, v) \ + (BIT_CLEAR_TSF_TIMER_HIGH(x) | BIT_TSF_TIMER_HIGH(v)) -#define BIT_SHIFT_MACID63_32_DROP 0 -#define BIT_MASK_MACID63_32_DROP 0xffffffffL -#define BIT_MACID63_32_DROP(x) (((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP) -#define BIT_GET_MACID63_32_DROP(x) (((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_MACID_DROP2 (Offset 0x1458) */ +/* 2 REG_TSF_ADJ_VLAUE (Offset 0x1524) */ +#define BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL 0 +#define BIT_MASK_R_CLI0_TSFT_ADJ_VAL 0xffff +#define BIT_R_CLI0_TSFT_ADJ_VAL(x) \ + (((x) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL) +#define BITS_R_CLI0_TSFT_ADJ_VAL \ + (BIT_MASK_R_CLI0_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL) +#define BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI0_TSFT_ADJ_VAL)) +#define BIT_GET_R_CLI0_TSFT_ADJ_VAL(x) \ + (((x) >> BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL) +#define BIT_SET_R_CLI0_TSFT_ADJ_VAL(x, v) \ + (BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL(x) | BIT_R_CLI0_TSFT_ADJ_VAL(v)) -#define BIT_SHIFT_MACID95_64_DROP 0 -#define BIT_MASK_MACID95_64_DROP 0xffffffffL -#define BIT_MACID95_64_DROP(x) (((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP) -#define BIT_GET_MACID95_64_DROP(x) (((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_MACID_DROP3 (Offset 0x145C) */ +/* 2 REG_TSF_SYN_OFFSET2 (Offset 0x1528) */ +#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3 16 +#define BIT_MASK_TSF_SYNC_INTERVAL_CLI3 0xffff +#define BIT_TSF_SYNC_INTERVAL_CLI3(x) \ + (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI3) \ + << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) +#define BITS_TSF_SYNC_INTERVAL_CLI3 \ + (BIT_MASK_TSF_SYNC_INTERVAL_CLI3 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) +#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x) \ + ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI3)) +#define BIT_GET_TSF_SYNC_INTERVAL_CLI3(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) & \ + BIT_MASK_TSF_SYNC_INTERVAL_CLI3) +#define BIT_SET_TSF_SYNC_INTERVAL_CLI3(x, v) \ + (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x) | BIT_TSF_SYNC_INTERVAL_CLI3(v)) -#define BIT_SHIFT_MACID127_96_DROP 0 -#define BIT_MASK_MACID127_96_DROP 0xffffffffL -#define BIT_MACID127_96_DROP(x) (((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP) -#define BIT_GET_MACID127_96_DROP(x) (((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP) +#endif +#if (HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_TSF_ADJ_VLAUE_2 (Offset 0x1528) */ +#define BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL 16 +#define BIT_MASK_R_CLI3_TSFT_ADJ_VAL 0xffff +#define BIT_R_CLI3_TSFT_ADJ_VAL(x) \ + (((x) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL) +#define BITS_R_CLI3_TSFT_ADJ_VAL \ + (BIT_MASK_R_CLI3_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL) +#define BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI3_TSFT_ADJ_VAL)) +#define BIT_GET_R_CLI3_TSFT_ADJ_VAL(x) \ + (((x) >> BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL) +#define BIT_SET_R_CLI3_TSFT_ADJ_VAL(x, v) \ + (BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL(x) | BIT_R_CLI3_TSFT_ADJ_VAL(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TSF_SYN_OFFSET2 (Offset 0x1528) */ + +#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2 0 +#define BIT_MASK_TSF_SYNC_INTERVAL_CLI2 0xffff +#define BIT_TSF_SYNC_INTERVAL_CLI2(x) \ + (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI2) \ + << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) +#define BITS_TSF_SYNC_INTERVAL_CLI2 \ + (BIT_MASK_TSF_SYNC_INTERVAL_CLI2 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) +#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x) \ + ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI2)) +#define BIT_GET_TSF_SYNC_INTERVAL_CLI2(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) & \ + BIT_MASK_TSF_SYNC_INTERVAL_CLI2) +#define BIT_SET_TSF_SYNC_INTERVAL_CLI2(x, v) \ + (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x) | BIT_TSF_SYNC_INTERVAL_CLI2(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_BCN_ERR_CNT_MAC (Offset 0x1528) */ + +#define BIT_SHIFT_BCN_ERR_CNT_MAC 0 +#define BIT_MASK_BCN_ERR_CNT_MAC 0xff +#define BIT_BCN_ERR_CNT_MAC(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_MAC) << BIT_SHIFT_BCN_ERR_CNT_MAC) +#define BITS_BCN_ERR_CNT_MAC \ + (BIT_MASK_BCN_ERR_CNT_MAC << BIT_SHIFT_BCN_ERR_CNT_MAC) +#define BIT_CLEAR_BCN_ERR_CNT_MAC(x) ((x) & (~BITS_BCN_ERR_CNT_MAC)) +#define BIT_GET_BCN_ERR_CNT_MAC(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_MAC) & BIT_MASK_BCN_ERR_CNT_MAC) +#define BIT_SET_BCN_ERR_CNT_MAC(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_MAC(x) | BIT_BCN_ERR_CNT_MAC(v)) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_TSF_ADJ_VLAUE_2 (Offset 0x1528) */ + +#define BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL 0 +#define BIT_MASK_R_CLI2_TSFT_ADJ_VAL 0xffff +#define BIT_R_CLI2_TSFT_ADJ_VAL(x) \ + (((x) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL) +#define BITS_R_CLI2_TSFT_ADJ_VAL \ + (BIT_MASK_R_CLI2_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL) +#define BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI2_TSFT_ADJ_VAL)) +#define BIT_GET_R_CLI2_TSFT_ADJ_VAL(x) \ + (((x) >> BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL) +#define BIT_SET_R_CLI2_TSFT_ADJ_VAL(x, v) \ + (BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL(x) | BIT_R_CLI2_TSFT_ADJ_VAL(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_BCN_ERR_CNT_EDCCA (Offset 0x1529) */ + +#define BIT_SHIFT_BCN_ERR_CNT_EDCCA 0 +#define BIT_MASK_BCN_ERR_CNT_EDCCA 0xff +#define BIT_BCN_ERR_CNT_EDCCA(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_EDCCA) << BIT_SHIFT_BCN_ERR_CNT_EDCCA) +#define BITS_BCN_ERR_CNT_EDCCA \ + (BIT_MASK_BCN_ERR_CNT_EDCCA << BIT_SHIFT_BCN_ERR_CNT_EDCCA) +#define BIT_CLEAR_BCN_ERR_CNT_EDCCA(x) ((x) & (~BITS_BCN_ERR_CNT_EDCCA)) +#define BIT_GET_BCN_ERR_CNT_EDCCA(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_EDCCA) & BIT_MASK_BCN_ERR_CNT_EDCCA) +#define BIT_SET_BCN_ERR_CNT_EDCCA(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_EDCCA(x) | BIT_BCN_ERR_CNT_EDCCA(v)) + +/* 2 REG_BCN_ERR_CNT_CCA (Offset 0x152A) */ + +#define BIT_SHIFT_BCN_ERR_CNT_CCA 0 +#define BIT_MASK_BCN_ERR_CNT_CCA 0xff +#define BIT_BCN_ERR_CNT_CCA(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_CCA) << BIT_SHIFT_BCN_ERR_CNT_CCA) +#define BITS_BCN_ERR_CNT_CCA \ + (BIT_MASK_BCN_ERR_CNT_CCA << BIT_SHIFT_BCN_ERR_CNT_CCA) +#define BIT_CLEAR_BCN_ERR_CNT_CCA(x) ((x) & (~BITS_BCN_ERR_CNT_CCA)) +#define BIT_GET_BCN_ERR_CNT_CCA(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_CCA) & BIT_MASK_BCN_ERR_CNT_CCA) +#define BIT_SET_BCN_ERR_CNT_CCA(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_CCA(x) | BIT_BCN_ERR_CNT_CCA(v)) + +/* 2 REG_BCN_ERR_CNT_INVALID (Offset 0x152B) */ + +#define BIT_SHIFT_BCN_ERR_CNT_INVALID 0 +#define BIT_MASK_BCN_ERR_CNT_INVALID 0xff +#define BIT_BCN_ERR_CNT_INVALID(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_INVALID) << BIT_SHIFT_BCN_ERR_CNT_INVALID) +#define BITS_BCN_ERR_CNT_INVALID \ + (BIT_MASK_BCN_ERR_CNT_INVALID << BIT_SHIFT_BCN_ERR_CNT_INVALID) +#define BIT_CLEAR_BCN_ERR_CNT_INVALID(x) ((x) & (~BITS_BCN_ERR_CNT_INVALID)) +#define BIT_GET_BCN_ERR_CNT_INVALID(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_INVALID) & BIT_MASK_BCN_ERR_CNT_INVALID) +#define BIT_SET_BCN_ERR_CNT_INVALID(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_INVALID(x) | BIT_BCN_ERR_CNT_INVALID(v)) + +/* 2 REG_BCN_ERR_CNT_OTHERS (Offset 0x152C) */ + +#define BIT_SHIFT_BCN_ERR_CNT_OTHERS 0 +#define BIT_MASK_BCN_ERR_CNT_OTHERS 0xff +#define BIT_BCN_ERR_CNT_OTHERS(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_OTHERS) << BIT_SHIFT_BCN_ERR_CNT_OTHERS) +#define BITS_BCN_ERR_CNT_OTHERS \ + (BIT_MASK_BCN_ERR_CNT_OTHERS << BIT_SHIFT_BCN_ERR_CNT_OTHERS) +#define BIT_CLEAR_BCN_ERR_CNT_OTHERS(x) ((x) & (~BITS_BCN_ERR_CNT_OTHERS)) +#define BIT_GET_BCN_ERR_CNT_OTHERS(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_OTHERS) & BIT_MASK_BCN_ERR_CNT_OTHERS) +#define BIT_SET_BCN_ERR_CNT_OTHERS(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_OTHERS(x) | BIT_BCN_ERR_CNT_OTHERS(v)) + +/* 2 REG_RX_BCN_TIMER (Offset 0x152D) */ + +#define BIT_SHIFT_RX_BCN_TIMER 0 +#define BIT_MASK_RX_BCN_TIMER 0xffff +#define BIT_RX_BCN_TIMER(x) \ + (((x) & BIT_MASK_RX_BCN_TIMER) << BIT_SHIFT_RX_BCN_TIMER) +#define BITS_RX_BCN_TIMER (BIT_MASK_RX_BCN_TIMER << BIT_SHIFT_RX_BCN_TIMER) +#define BIT_CLEAR_RX_BCN_TIMER(x) ((x) & (~BITS_RX_BCN_TIMER)) +#define BIT_GET_RX_BCN_TIMER(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TIMER) & BIT_MASK_RX_BCN_TIMER) +#define BIT_SET_RX_BCN_TIMER(x, v) \ + (BIT_CLEAR_RX_BCN_TIMER(x) | BIT_RX_BCN_TIMER(v)) + +/* 2 REG_SUB_BCN_SPACE (Offset 0x1534) */ + +#define BIT_SHIFT_SUB_BCN_SPACE_V2 0 +#define BIT_MASK_SUB_BCN_SPACE_V2 0xff +#define BIT_SUB_BCN_SPACE_V2(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE_V2) << BIT_SHIFT_SUB_BCN_SPACE_V2) +#define BITS_SUB_BCN_SPACE_V2 \ + (BIT_MASK_SUB_BCN_SPACE_V2 << BIT_SHIFT_SUB_BCN_SPACE_V2) +#define BIT_CLEAR_SUB_BCN_SPACE_V2(x) ((x) & (~BITS_SUB_BCN_SPACE_V2)) +#define BIT_GET_SUB_BCN_SPACE_V2(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V2) & BIT_MASK_SUB_BCN_SPACE_V2) +#define BIT_SET_SUB_BCN_SPACE_V2(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE_V2(x) | BIT_SUB_BCN_SPACE_V2(v)) + +/* 2 REG_MBID_NUM_V1 (Offset 0x1535) */ + +#define BIT_SHIFT_BCN_ERR_PORT_SEL 4 +#define BIT_MASK_BCN_ERR_PORT_SEL 0xf +#define BIT_BCN_ERR_PORT_SEL(x) \ + (((x) & BIT_MASK_BCN_ERR_PORT_SEL) << BIT_SHIFT_BCN_ERR_PORT_SEL) +#define BITS_BCN_ERR_PORT_SEL \ + (BIT_MASK_BCN_ERR_PORT_SEL << BIT_SHIFT_BCN_ERR_PORT_SEL) +#define BIT_CLEAR_BCN_ERR_PORT_SEL(x) ((x) & (~BITS_BCN_ERR_PORT_SEL)) +#define BIT_GET_BCN_ERR_PORT_SEL(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_PORT_SEL) & BIT_MASK_BCN_ERR_PORT_SEL) +#define BIT_SET_BCN_ERR_PORT_SEL(x, v) \ + (BIT_CLEAR_BCN_ERR_PORT_SEL(x) | BIT_BCN_ERR_PORT_SEL(v)) + +#define BIT_SHIFT_MBID_BCN_NUM_V1 0 +#define BIT_MASK_MBID_BCN_NUM_V1 0xf +#define BIT_MBID_BCN_NUM_V1(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_V1) << BIT_SHIFT_MBID_BCN_NUM_V1) +#define BITS_MBID_BCN_NUM_V1 \ + (BIT_MASK_MBID_BCN_NUM_V1 << BIT_SHIFT_MBID_BCN_NUM_V1) +#define BIT_CLEAR_MBID_BCN_NUM_V1(x) ((x) & (~BITS_MBID_BCN_NUM_V1)) +#define BIT_GET_MBID_BCN_NUM_V1(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_V1) & BIT_MASK_MBID_BCN_NUM_V1) +#define BIT_SET_MBID_BCN_NUM_V1(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_V1(x) | BIT_MBID_BCN_NUM_V1(v)) + +/* 2 REG_MBSSID_CTRL_V1 (Offset 0x1536) */ + +#define BIT_MBID_BCNQ15_EN BIT(15) +#define BIT_MBID_BCNQ14_EN BIT(14) +#define BIT_MBID_BCNQ13_EN BIT(13) +#define BIT_MBID_BCNQ12_EN BIT(12) +#define BIT_MBID_BCNQ11_EN BIT(11) +#define BIT_MBID_BCNQ10_EN BIT(10) +#define BIT_MBID_BCNQ9_EN BIT(9) +#define BIT_MBID_BCNQ8_EN BIT(8) + +/* 2 REG_BW_CFG (Offset 0x1539) */ + +#define BIT_SLEEP_32K_EN BIT(3) +#define BIT_DIS_MARK_TSF_US_V1 BIT(2) + +/* 2 REG_ATIMWND_CFG (Offset 0x153A) */ + +#define BIT_SHIFT_ATIMWND_V1 0 +#define BIT_MASK_ATIMWND_V1 0xff +#define BIT_ATIMWND_V1(x) (((x) & BIT_MASK_ATIMWND_V1) << BIT_SHIFT_ATIMWND_V1) +#define BITS_ATIMWND_V1 (BIT_MASK_ATIMWND_V1 << BIT_SHIFT_ATIMWND_V1) +#define BIT_CLEAR_ATIMWND_V1(x) ((x) & (~BITS_ATIMWND_V1)) +#define BIT_GET_ATIMWND_V1(x) \ + (((x) >> BIT_SHIFT_ATIMWND_V1) & BIT_MASK_ATIMWND_V1) +#define BIT_SET_ATIMWND_V1(x, v) (BIT_CLEAR_ATIMWND_V1(x) | BIT_ATIMWND_V1(v)) + +/* 2 REG_DTIM_COUNTER_CFG (Offset 0x153B) */ + +#define BIT_SHIFT_DTIM_COUNT 0 +#define BIT_MASK_DTIM_COUNT 0xff +#define BIT_DTIM_COUNT(x) (((x) & BIT_MASK_DTIM_COUNT) << BIT_SHIFT_DTIM_COUNT) +#define BITS_DTIM_COUNT (BIT_MASK_DTIM_COUNT << BIT_SHIFT_DTIM_COUNT) +#define BIT_CLEAR_DTIM_COUNT(x) ((x) & (~BITS_DTIM_COUNT)) +#define BIT_GET_DTIM_COUNT(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT) & BIT_MASK_DTIM_COUNT) +#define BIT_SET_DTIM_COUNT(x, v) (BIT_CLEAR_DTIM_COUNT(x) | BIT_DTIM_COUNT(v)) + +/* 2 REG_ATIM_DTIM_CTRL_SEL (Offset 0x153C) */ + +#define BIT_DTIM_BYPASS_V1 BIT(7) + +#define BIT_SHIFT_ATIM_DTIM_SEL 0 +#define BIT_MASK_ATIM_DTIM_SEL 0x1f +#define BIT_ATIM_DTIM_SEL(x) \ + (((x) & BIT_MASK_ATIM_DTIM_SEL) << BIT_SHIFT_ATIM_DTIM_SEL) +#define BITS_ATIM_DTIM_SEL (BIT_MASK_ATIM_DTIM_SEL << BIT_SHIFT_ATIM_DTIM_SEL) +#define BIT_CLEAR_ATIM_DTIM_SEL(x) ((x) & (~BITS_ATIM_DTIM_SEL)) +#define BIT_GET_ATIM_DTIM_SEL(x) \ + (((x) >> BIT_SHIFT_ATIM_DTIM_SEL) & BIT_MASK_ATIM_DTIM_SEL) +#define BIT_SET_ATIM_DTIM_SEL(x, v) \ + (BIT_CLEAR_ATIM_DTIM_SEL(x) | BIT_ATIM_DTIM_SEL(v)) + +/* 2 REG_DIS_ATIM_V1 (Offset 0x1540) */ + +#define BIT_DIS_ATIM_P4 BIT(19) +#define BIT_DIS_ATIM_P3 BIT(18) +#define BIT_DIS_ATIM_P2 BIT(17) +#define BIT_DIS_ATIM_P1 BIT(16) +#define BIT_DIS_ATIM_VAP15 BIT(15) +#define BIT_DIS_ATIM_VAP14 BIT(14) +#define BIT_DIS_ATIM_VAP13 BIT(13) +#define BIT_DIS_ATIM_VAP12 BIT(12) +#define BIT_DIS_ATIM_VAP11 BIT(11) +#define BIT_DIS_ATIM_VAP10 BIT(10) +#define BIT_DIS_ATIM_VAP9 BIT(9) +#define BIT_DIS_ATIM_VAP8 BIT(8) +#define BIT_DIS_ATIM_ROOT_P0 BIT(0) + +/* 2 REG_HIQ_NO_LMT_EN_V1 (Offset 0x1544) */ + +#define BIT_HIQ_NO_LMT_EN_P4 BIT(19) +#define BIT_HIQ_NO_LMT_EN_P3 BIT(18) +#define BIT_HIQ_NO_LMT_EN_P2 BIT(17) +#define BIT_HIQ_NO_LMT_EN_P1 BIT(16) + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) + +/* 2 REG_HIQ_NO_LMT_EN_V1 (Offset 0x1544) */ + +#define BIT_HIQ_NO_LMT_EN_VAP15 BIT(15) +#define BIT_HIQ_NO_LMT_EN_VAP14 BIT(14) +#define BIT_HIQ_NO_LMT_EN_VAP13 BIT(13) +#define BIT_HIQ_NO_LMT_EN_VAP12 BIT(12) +#define BIT_HIQ_NO_LMT_EN_VAP11 BIT(11) +#define BIT_HIQ_NO_LMT_EN_VAP10 BIT(10) +#define BIT_HIQ_NO_LMT_EN_VAP9 BIT(9) +#define BIT_HIQ_NO_LMT_EN_VAP8 BIT(8) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIQ_NO_LMT_EN_V1 (Offset 0x1544) */ + +#define BIT_HIQ_NO_LMT_EN_ROOT_P0 BIT(0) + +/* 2 REG_P2PPS_CTRL_V1 (Offset 0x1548) */ + +#define BIT_P2P_PWR_RST1_V2 BIT(15) +#define BIT_P2P_PWR_RST0_V2 BIT(14) +#define BIT_EN_TSFBIT32_RST_P2P_V1 BIT(13) + +#define BIT_SHIFT_NOA_UNIT0_SEL_V1 8 +#define BIT_MASK_NOA_UNIT0_SEL_V1 0x7 +#define BIT_NOA_UNIT0_SEL_V1(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL_V1) << BIT_SHIFT_NOA_UNIT0_SEL_V1) +#define BITS_NOA_UNIT0_SEL_V1 \ + (BIT_MASK_NOA_UNIT0_SEL_V1 << BIT_SHIFT_NOA_UNIT0_SEL_V1) +#define BIT_CLEAR_NOA_UNIT0_SEL_V1(x) ((x) & (~BITS_NOA_UNIT0_SEL_V1)) +#define BIT_GET_NOA_UNIT0_SEL_V1(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_V1) & BIT_MASK_NOA_UNIT0_SEL_V1) +#define BIT_SET_NOA_UNIT0_SEL_V1(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL_V1(x) | BIT_NOA_UNIT0_SEL_V1(v)) + +#define BIT_P2P_CTW_ALLSTASLEEP_V1 BIT(7) +#define BIT_P2P_OFF_DISTX_EN_V1 BIT(6) +#define BIT_PWR_MGT_EN_V1 BIT(5) +#define BIT_P2P_NOA1_EN_V1 BIT(2) +#define BIT_P2P_NOA0_EN_V1 BIT(1) + +/* 2 REG_P2PPS1_CTRL_V1 (Offset 0x154C) */ + +#define BIT_P2P1_PWR_RST1_V2 BIT(15) +#define BIT_P2P1_PWR_RST0_V2 BIT(14) +#define BIT_EN_TSFBIT32_RST_P2P1_V1 BIT(13) + +#define BIT_SHIFT_NOA_UNIT1_SEL_V1 8 +#define BIT_MASK_NOA_UNIT1_SEL_V1 0x7 +#define BIT_NOA_UNIT1_SEL_V1(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL_V1) << BIT_SHIFT_NOA_UNIT1_SEL_V1) +#define BITS_NOA_UNIT1_SEL_V1 \ + (BIT_MASK_NOA_UNIT1_SEL_V1 << BIT_SHIFT_NOA_UNIT1_SEL_V1) +#define BIT_CLEAR_NOA_UNIT1_SEL_V1(x) ((x) & (~BITS_NOA_UNIT1_SEL_V1)) +#define BIT_GET_NOA_UNIT1_SEL_V1(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_V1) & BIT_MASK_NOA_UNIT1_SEL_V1) +#define BIT_SET_NOA_UNIT1_SEL_V1(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL_V1(x) | BIT_NOA_UNIT1_SEL_V1(v)) + +#define BIT_P2P1_CTW_ALLSTASLEEP_V1 BIT(7) +#define BIT_P2P1_PWR_MGT_EN_V1 BIT(5) +#define BIT_P2P1_NOA1_EN_V1 BIT(2) +#define BIT_P2P1_NOA0_EN_V1 BIT(1) + +/* 2 REG_P2PPS1_SPEC_STATE_V1 (Offset 0x154E) */ + +#define BIT_P2P1_SPEC_POWER_STATEP BIT(7) +#define BIT_P2P1_SPEC_BEACON_AREA_ON BIT(5) + +/* 2 REG_P2PPS2_CTRL_V1 (Offset 0x1550) */ + +#define BIT_P2P2_PWR_RST1_V2 BIT(15) +#define BIT_P2P2_PWR_RST0_V2 BIT(14) +#define BIT_EN_TSFBIT32_RST_P2P2_V1 BIT(13) + +#define BIT_SHIFT_NOA_UNIT2_SEL_V1 8 +#define BIT_MASK_NOA_UNIT2_SEL_V1 0x7 +#define BIT_NOA_UNIT2_SEL_V1(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL_V1) << BIT_SHIFT_NOA_UNIT2_SEL_V1) +#define BITS_NOA_UNIT2_SEL_V1 \ + (BIT_MASK_NOA_UNIT2_SEL_V1 << BIT_SHIFT_NOA_UNIT2_SEL_V1) +#define BIT_CLEAR_NOA_UNIT2_SEL_V1(x) ((x) & (~BITS_NOA_UNIT2_SEL_V1)) +#define BIT_GET_NOA_UNIT2_SEL_V1(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_V1) & BIT_MASK_NOA_UNIT2_SEL_V1) +#define BIT_SET_NOA_UNIT2_SEL_V1(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL_V1(x) | BIT_NOA_UNIT2_SEL_V1(v)) + +#define BIT_P2P2_CTW_ALLSTASLEEP_V1 BIT(7) +#define BIT_P2P2_OFF_DISTX_EN_V1 BIT(6) +#define BIT_P2P2_PWR_MGT_EN_V1 BIT(5) +#define BIT_P2P2_NOA1_EN_V1 BIT(2) +#define BIT_P2P2_NOA0_EN_V1 BIT(1) + +/* 2 REG_P2PPS2_SPEC_STATE_V1 (Offset 0x1552) */ + +#define BIT_P2P2_SPEC_POWER_STATEP BIT(7) +#define BIT_P2P2_SPEC_BEACON_AREA_ON BIT(5) + +/* 2 REG_CHG_POWER_BCN_AREA (Offset 0x1556) */ + +#define BIT_CHG_POWER_BCN_AREA BIT(0) + +/* 2 REG_NOA_SEL (Offset 0x1557) */ + +#define BIT_SHIFT_NOA_SEL_V1 0 +#define BIT_MASK_NOA_SEL_V1 0x7 +#define BIT_NOA_SEL_V1(x) (((x) & BIT_MASK_NOA_SEL_V1) << BIT_SHIFT_NOA_SEL_V1) +#define BITS_NOA_SEL_V1 (BIT_MASK_NOA_SEL_V1 << BIT_SHIFT_NOA_SEL_V1) +#define BIT_CLEAR_NOA_SEL_V1(x) ((x) & (~BITS_NOA_SEL_V1)) +#define BIT_GET_NOA_SEL_V1(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V1) & BIT_MASK_NOA_SEL_V1) +#define BIT_SET_NOA_SEL_V1(x, v) (BIT_CLEAR_NOA_SEL_V1(x) | BIT_NOA_SEL_V1(v)) + +/* 2 REG_NOA_PARAM_3_V1 (Offset 0x1564) */ + +#define BIT_SHIFT_NOA_COUNT_V2 0 +#define BIT_MASK_NOA_COUNT_V2 0xffffffffL +#define BIT_NOA_COUNT_V2(x) \ + (((x) & BIT_MASK_NOA_COUNT_V2) << BIT_SHIFT_NOA_COUNT_V2) +#define BITS_NOA_COUNT_V2 (BIT_MASK_NOA_COUNT_V2 << BIT_SHIFT_NOA_COUNT_V2) +#define BIT_CLEAR_NOA_COUNT_V2(x) ((x) & (~BITS_NOA_COUNT_V2)) +#define BIT_GET_NOA_COUNT_V2(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_V2) & BIT_MASK_NOA_COUNT_V2) +#define BIT_SET_NOA_COUNT_V2(x, v) \ + (BIT_CLEAR_NOA_COUNT_V2(x) | BIT_NOA_COUNT_V2(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL (Offset 0x156C) */ + +#define BIT_P2PPS_NOA_STOP_TX_HANG BIT(31) +#define BIT_P2PPS_MACID_PAUSE_EN BIT(11) +#define BIT_P2PPS__MGQ_PAUSE BIT(10) +#define BIT_P2PPS__HIQ_PAUSE BIT(9) +#define BIT_P2PPS__BCNQ_PAUSE BIT(8) + +#define BIT_SHIFT_P2PPS_MACID_PAUSE 0 +#define BIT_MASK_P2PPS_MACID_PAUSE 0xff +#define BIT_P2PPS_MACID_PAUSE(x) \ + (((x) & BIT_MASK_P2PPS_MACID_PAUSE) << BIT_SHIFT_P2PPS_MACID_PAUSE) +#define BITS_P2PPS_MACID_PAUSE \ + (BIT_MASK_P2PPS_MACID_PAUSE << BIT_SHIFT_P2PPS_MACID_PAUSE) +#define BIT_CLEAR_P2PPS_MACID_PAUSE(x) ((x) & (~BITS_P2PPS_MACID_PAUSE)) +#define BIT_GET_P2PPS_MACID_PAUSE(x) \ + (((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE) & BIT_MASK_P2PPS_MACID_PAUSE) +#define BIT_SET_P2PPS_MACID_PAUSE(x, v) \ + (BIT_CLEAR_P2PPS_MACID_PAUSE(x) | BIT_P2PPS_MACID_PAUSE(v)) + +/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL (Offset 0x1570) */ + +#define BIT_P2PPS1_NOA_STOP_TX_HANG BIT(31) +#define BIT_P2PPS1_MACID_PAUSE_EN BIT(11) +#define BIT_P2PPS1__MGQ_PAUSE BIT(10) +#define BIT_P2PPS1__HIQ_PAUSE BIT(9) +#define BIT_P2PPS1__BCNQ_PAUSE BIT(8) + +#define BIT_SHIFT_P2PPS1_MACID_PAUSE 0 +#define BIT_MASK_P2PPS1_MACID_PAUSE 0xff +#define BIT_P2PPS1_MACID_PAUSE(x) \ + (((x) & BIT_MASK_P2PPS1_MACID_PAUSE) << BIT_SHIFT_P2PPS1_MACID_PAUSE) +#define BITS_P2PPS1_MACID_PAUSE \ + (BIT_MASK_P2PPS1_MACID_PAUSE << BIT_SHIFT_P2PPS1_MACID_PAUSE) +#define BIT_CLEAR_P2PPS1_MACID_PAUSE(x) ((x) & (~BITS_P2PPS1_MACID_PAUSE)) +#define BIT_GET_P2PPS1_MACID_PAUSE(x) \ + (((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE) & BIT_MASK_P2PPS1_MACID_PAUSE) +#define BIT_SET_P2PPS1_MACID_PAUSE(x, v) \ + (BIT_CLEAR_P2PPS1_MACID_PAUSE(x) | BIT_P2PPS1_MACID_PAUSE(v)) + +/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL (Offset 0x1574) */ + +#define BIT_P2PPS2_NOA_STOP_TX_HANG BIT(31) +#define BIT_P2PPS2_MACID_PAUSE_EN BIT(11) +#define BIT_P2PPS2__MGQ_PAUSE BIT(10) +#define BIT_P2PPS2__HIQ_PAUSE BIT(9) +#define BIT_P2PPS2__BCNQ_PAUSE BIT(8) + +#define BIT_SHIFT_P2PPS2_MACID_PAUSE 0 +#define BIT_MASK_P2PPS2_MACID_PAUSE 0xff +#define BIT_P2PPS2_MACID_PAUSE(x) \ + (((x) & BIT_MASK_P2PPS2_MACID_PAUSE) << BIT_SHIFT_P2PPS2_MACID_PAUSE) +#define BITS_P2PPS2_MACID_PAUSE \ + (BIT_MASK_P2PPS2_MACID_PAUSE << BIT_SHIFT_P2PPS2_MACID_PAUSE) +#define BIT_CLEAR_P2PPS2_MACID_PAUSE(x) ((x) & (~BITS_P2PPS2_MACID_PAUSE)) +#define BIT_GET_P2PPS2_MACID_PAUSE(x) \ + (((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE) & BIT_MASK_P2PPS2_MACID_PAUSE) +#define BIT_SET_P2PPS2_MACID_PAUSE(x, v) \ + (BIT_CLEAR_P2PPS2_MACID_PAUSE(x) | BIT_P2PPS2_MACID_PAUSE(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_RX_TBTT_SHIFT (Offset 0x1578) */ + +#define BIT_SHIFT_RX_TBTT_SHIFT_SEL 24 +#define BIT_MASK_RX_TBTT_SHIFT_SEL 0x7 +#define BIT_RX_TBTT_SHIFT_SEL(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL) << BIT_SHIFT_RX_TBTT_SHIFT_SEL) +#define BITS_RX_TBTT_SHIFT_SEL \ + (BIT_MASK_RX_TBTT_SHIFT_SEL << BIT_SHIFT_RX_TBTT_SHIFT_SEL) +#define BIT_CLEAR_RX_TBTT_SHIFT_SEL(x) ((x) & (~BITS_RX_TBTT_SHIFT_SEL)) +#define BIT_GET_RX_TBTT_SHIFT_SEL(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL) & BIT_MASK_RX_TBTT_SHIFT_SEL) +#define BIT_SET_RX_TBTT_SHIFT_SEL(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_SEL(x) | BIT_RX_TBTT_SHIFT_SEL(v)) + +#define BIT_RX_TBTT_SHIFT_RW_FLAG BIT(15) + +#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET 0 +#define BIT_MASK_RX_TBTT_SHIFT_OFFSET 0xfff +#define BIT_RX_TBTT_SHIFT_OFFSET(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET) \ + << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET) +#define BITS_RX_TBTT_SHIFT_OFFSET \ + (BIT_MASK_RX_TBTT_SHIFT_OFFSET << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET) +#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET(x) ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET)) +#define BIT_GET_RX_TBTT_SHIFT_OFFSET(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET) & \ + BIT_MASK_RX_TBTT_SHIFT_OFFSET) +#define BIT_SET_RX_TBTT_SHIFT_OFFSET(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET(x) | BIT_RX_TBTT_SHIFT_OFFSET(v)) + +/* 2 REG_FREERUN_CNT_LOW (Offset 0x1580) */ + +#define BIT_SHIFT_FREERUN_CNT_LOW 0 +#define BIT_MASK_FREERUN_CNT_LOW 0xffffffffL +#define BIT_FREERUN_CNT_LOW(x) \ + (((x) & BIT_MASK_FREERUN_CNT_LOW) << BIT_SHIFT_FREERUN_CNT_LOW) +#define BITS_FREERUN_CNT_LOW \ + (BIT_MASK_FREERUN_CNT_LOW << BIT_SHIFT_FREERUN_CNT_LOW) +#define BIT_CLEAR_FREERUN_CNT_LOW(x) ((x) & (~BITS_FREERUN_CNT_LOW)) +#define BIT_GET_FREERUN_CNT_LOW(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_LOW) & BIT_MASK_FREERUN_CNT_LOW) +#define BIT_SET_FREERUN_CNT_LOW(x, v) \ + (BIT_CLEAR_FREERUN_CNT_LOW(x) | BIT_FREERUN_CNT_LOW(v)) + +/* 2 REG_FREERUN_CNT_HIGH (Offset 0x1584) */ + +#define BIT_SHIFT_FREERUN_CNT_HIGH 0 +#define BIT_MASK_FREERUN_CNT_HIGH 0xffffffffL +#define BIT_FREERUN_CNT_HIGH(x) \ + (((x) & BIT_MASK_FREERUN_CNT_HIGH) << BIT_SHIFT_FREERUN_CNT_HIGH) +#define BITS_FREERUN_CNT_HIGH \ + (BIT_MASK_FREERUN_CNT_HIGH << BIT_SHIFT_FREERUN_CNT_HIGH) +#define BIT_CLEAR_FREERUN_CNT_HIGH(x) ((x) & (~BITS_FREERUN_CNT_HIGH)) +#define BIT_GET_FREERUN_CNT_HIGH(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_HIGH) & BIT_MASK_FREERUN_CNT_HIGH) +#define BIT_SET_FREERUN_CNT_HIGH(x, v) \ + (BIT_CLEAR_FREERUN_CNT_HIGH(x) | BIT_FREERUN_CNT_HIGH(v)) + +/* 2 REG_PS_TIMER_0 (Offset 0x158C) */ + +#define BIT_SHIFT_PS_TIMER_0 0 +#define BIT_MASK_PS_TIMER_0 0xffffffffL +#define BIT_PS_TIMER_0(x) (((x) & BIT_MASK_PS_TIMER_0) << BIT_SHIFT_PS_TIMER_0) +#define BITS_PS_TIMER_0 (BIT_MASK_PS_TIMER_0 << BIT_SHIFT_PS_TIMER_0) +#define BIT_CLEAR_PS_TIMER_0(x) ((x) & (~BITS_PS_TIMER_0)) +#define BIT_GET_PS_TIMER_0(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_0) & BIT_MASK_PS_TIMER_0) +#define BIT_SET_PS_TIMER_0(x, v) (BIT_CLEAR_PS_TIMER_0(x) | BIT_PS_TIMER_0(v)) + +/* 2 REG_PS_TIMER_1 (Offset 0x1590) */ + +#define BIT_SHIFT_PS_TIMER_1 0 +#define BIT_MASK_PS_TIMER_1 0xffffffffL +#define BIT_PS_TIMER_1(x) (((x) & BIT_MASK_PS_TIMER_1) << BIT_SHIFT_PS_TIMER_1) +#define BITS_PS_TIMER_1 (BIT_MASK_PS_TIMER_1 << BIT_SHIFT_PS_TIMER_1) +#define BIT_CLEAR_PS_TIMER_1(x) ((x) & (~BITS_PS_TIMER_1)) +#define BIT_GET_PS_TIMER_1(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_1) & BIT_MASK_PS_TIMER_1) +#define BIT_SET_PS_TIMER_1(x, v) (BIT_CLEAR_PS_TIMER_1(x) | BIT_PS_TIMER_1(v)) + +/* 2 REG_PS_TIMER_2 (Offset 0x1594) */ + +#define BIT_SHIFT_PS_TIMER_2 0 +#define BIT_MASK_PS_TIMER_2 0xffffffffL +#define BIT_PS_TIMER_2(x) (((x) & BIT_MASK_PS_TIMER_2) << BIT_SHIFT_PS_TIMER_2) +#define BITS_PS_TIMER_2 (BIT_MASK_PS_TIMER_2 << BIT_SHIFT_PS_TIMER_2) +#define BIT_CLEAR_PS_TIMER_2(x) ((x) & (~BITS_PS_TIMER_2)) +#define BIT_GET_PS_TIMER_2(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_2) & BIT_MASK_PS_TIMER_2) +#define BIT_SET_PS_TIMER_2(x, v) (BIT_CLEAR_PS_TIMER_2(x) | BIT_PS_TIMER_2(v)) + +/* 2 REG_PS_TIMER_3 (Offset 0x1598) */ + +#define BIT_SHIFT_PS_TIMER_3 0 +#define BIT_MASK_PS_TIMER_3 0xffffffffL +#define BIT_PS_TIMER_3(x) (((x) & BIT_MASK_PS_TIMER_3) << BIT_SHIFT_PS_TIMER_3) +#define BITS_PS_TIMER_3 (BIT_MASK_PS_TIMER_3 << BIT_SHIFT_PS_TIMER_3) +#define BIT_CLEAR_PS_TIMER_3(x) ((x) & (~BITS_PS_TIMER_3)) +#define BIT_GET_PS_TIMER_3(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_3) & BIT_MASK_PS_TIMER_3) +#define BIT_SET_PS_TIMER_3(x, v) (BIT_CLEAR_PS_TIMER_3(x) | BIT_PS_TIMER_3(v)) + +/* 2 REG_PS_TIMER_4 (Offset 0x159C) */ + +#define BIT_SHIFT_PS_TIMER_4 0 +#define BIT_MASK_PS_TIMER_4 0xffffffffL +#define BIT_PS_TIMER_4(x) (((x) & BIT_MASK_PS_TIMER_4) << BIT_SHIFT_PS_TIMER_4) +#define BITS_PS_TIMER_4 (BIT_MASK_PS_TIMER_4 << BIT_SHIFT_PS_TIMER_4) +#define BIT_CLEAR_PS_TIMER_4(x) ((x) & (~BITS_PS_TIMER_4)) +#define BIT_GET_PS_TIMER_4(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_4) & BIT_MASK_PS_TIMER_4) +#define BIT_SET_PS_TIMER_4(x, v) (BIT_CLEAR_PS_TIMER_4(x) | BIT_PS_TIMER_4(v)) + +/* 2 REG_PS_TIMER_5 (Offset 0x15A0) */ + +#define BIT_SHIFT_PS_TIMER_5 0 +#define BIT_MASK_PS_TIMER_5 0xffffffffL +#define BIT_PS_TIMER_5(x) (((x) & BIT_MASK_PS_TIMER_5) << BIT_SHIFT_PS_TIMER_5) +#define BITS_PS_TIMER_5 (BIT_MASK_PS_TIMER_5 << BIT_SHIFT_PS_TIMER_5) +#define BIT_CLEAR_PS_TIMER_5(x) ((x) & (~BITS_PS_TIMER_5)) +#define BIT_GET_PS_TIMER_5(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_5) & BIT_MASK_PS_TIMER_5) +#define BIT_SET_PS_TIMER_5(x, v) (BIT_CLEAR_PS_TIMER_5(x) | BIT_PS_TIMER_5(v)) + +/* 2 REG_PS_TIMER_01_CTRL (Offset 0x15A4) */ + +#define BIT_SHIFT_PS_TIMER_1_EARLY_TIME 24 +#define BIT_MASK_PS_TIMER_1_EARLY_TIME 0xff +#define BIT_PS_TIMER_1_EARLY_TIME(x) \ + (((x) & BIT_MASK_PS_TIMER_1_EARLY_TIME) \ + << BIT_SHIFT_PS_TIMER_1_EARLY_TIME) +#define BITS_PS_TIMER_1_EARLY_TIME \ + (BIT_MASK_PS_TIMER_1_EARLY_TIME << BIT_SHIFT_PS_TIMER_1_EARLY_TIME) +#define BIT_CLEAR_PS_TIMER_1_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_1_EARLY_TIME)) +#define BIT_GET_PS_TIMER_1_EARLY_TIME(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_1_EARLY_TIME) & \ + BIT_MASK_PS_TIMER_1_EARLY_TIME) +#define BIT_SET_PS_TIMER_1_EARLY_TIME(x, v) \ + (BIT_CLEAR_PS_TIMER_1_EARLY_TIME(x) | BIT_PS_TIMER_1_EARLY_TIME(v)) + +#define BIT_PS_TIMER_1_EN BIT(23) + +#define BIT_SHIFT_PS_TIMER_1_TSF_SEL 16 +#define BIT_MASK_PS_TIMER_1_TSF_SEL 0x7 +#define BIT_PS_TIMER_1_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_1_TSF_SEL) << BIT_SHIFT_PS_TIMER_1_TSF_SEL) +#define BITS_PS_TIMER_1_TSF_SEL \ + (BIT_MASK_PS_TIMER_1_TSF_SEL << BIT_SHIFT_PS_TIMER_1_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_1_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_1_TSF_SEL)) +#define BIT_GET_PS_TIMER_1_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_1_TSF_SEL) & BIT_MASK_PS_TIMER_1_TSF_SEL) +#define BIT_SET_PS_TIMER_1_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_1_TSF_SEL(x) | BIT_PS_TIMER_1_TSF_SEL(v)) + +#define BIT_SHIFT_PS_TIMER_0_EARLY_TIME 8 +#define BIT_MASK_PS_TIMER_0_EARLY_TIME 0xff +#define BIT_PS_TIMER_0_EARLY_TIME(x) \ + (((x) & BIT_MASK_PS_TIMER_0_EARLY_TIME) \ + << BIT_SHIFT_PS_TIMER_0_EARLY_TIME) +#define BITS_PS_TIMER_0_EARLY_TIME \ + (BIT_MASK_PS_TIMER_0_EARLY_TIME << BIT_SHIFT_PS_TIMER_0_EARLY_TIME) +#define BIT_CLEAR_PS_TIMER_0_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_0_EARLY_TIME)) +#define BIT_GET_PS_TIMER_0_EARLY_TIME(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_0_EARLY_TIME) & \ + BIT_MASK_PS_TIMER_0_EARLY_TIME) +#define BIT_SET_PS_TIMER_0_EARLY_TIME(x, v) \ + (BIT_CLEAR_PS_TIMER_0_EARLY_TIME(x) | BIT_PS_TIMER_0_EARLY_TIME(v)) + +#define BIT_PS_TIMER_0_EN BIT(7) + +#define BIT_SHIFT_PS_TIMER_0_TSF_SEL 0 +#define BIT_MASK_PS_TIMER_0_TSF_SEL 0x7 +#define BIT_PS_TIMER_0_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_0_TSF_SEL) << BIT_SHIFT_PS_TIMER_0_TSF_SEL) +#define BITS_PS_TIMER_0_TSF_SEL \ + (BIT_MASK_PS_TIMER_0_TSF_SEL << BIT_SHIFT_PS_TIMER_0_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_0_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_0_TSF_SEL)) +#define BIT_GET_PS_TIMER_0_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_0_TSF_SEL) & BIT_MASK_PS_TIMER_0_TSF_SEL) +#define BIT_SET_PS_TIMER_0_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_0_TSF_SEL(x) | BIT_PS_TIMER_0_TSF_SEL(v)) + +/* 2 REG_PS_TIMER_23_CTRL (Offset 0x15A8) */ + +#define BIT_SHIFT_PS_TIMER_3_EARLY_TIME 24 +#define BIT_MASK_PS_TIMER_3_EARLY_TIME 0xff +#define BIT_PS_TIMER_3_EARLY_TIME(x) \ + (((x) & BIT_MASK_PS_TIMER_3_EARLY_TIME) \ + << BIT_SHIFT_PS_TIMER_3_EARLY_TIME) +#define BITS_PS_TIMER_3_EARLY_TIME \ + (BIT_MASK_PS_TIMER_3_EARLY_TIME << BIT_SHIFT_PS_TIMER_3_EARLY_TIME) +#define BIT_CLEAR_PS_TIMER_3_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_3_EARLY_TIME)) +#define BIT_GET_PS_TIMER_3_EARLY_TIME(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_3_EARLY_TIME) & \ + BIT_MASK_PS_TIMER_3_EARLY_TIME) +#define BIT_SET_PS_TIMER_3_EARLY_TIME(x, v) \ + (BIT_CLEAR_PS_TIMER_3_EARLY_TIME(x) | BIT_PS_TIMER_3_EARLY_TIME(v)) + +#define BIT_PS_TIMER_3_EN BIT(23) + +#define BIT_SHIFT_PS_TIMER_3_TSF_SEL 16 +#define BIT_MASK_PS_TIMER_3_TSF_SEL 0x7 +#define BIT_PS_TIMER_3_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_3_TSF_SEL) << BIT_SHIFT_PS_TIMER_3_TSF_SEL) +#define BITS_PS_TIMER_3_TSF_SEL \ + (BIT_MASK_PS_TIMER_3_TSF_SEL << BIT_SHIFT_PS_TIMER_3_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_3_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_3_TSF_SEL)) +#define BIT_GET_PS_TIMER_3_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_3_TSF_SEL) & BIT_MASK_PS_TIMER_3_TSF_SEL) +#define BIT_SET_PS_TIMER_3_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_3_TSF_SEL(x) | BIT_PS_TIMER_3_TSF_SEL(v)) + +#define BIT_SHIFT_PS_TIMER_2_EARLY_TIME 8 +#define BIT_MASK_PS_TIMER_2_EARLY_TIME 0xff +#define BIT_PS_TIMER_2_EARLY_TIME(x) \ + (((x) & BIT_MASK_PS_TIMER_2_EARLY_TIME) \ + << BIT_SHIFT_PS_TIMER_2_EARLY_TIME) +#define BITS_PS_TIMER_2_EARLY_TIME \ + (BIT_MASK_PS_TIMER_2_EARLY_TIME << BIT_SHIFT_PS_TIMER_2_EARLY_TIME) +#define BIT_CLEAR_PS_TIMER_2_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_2_EARLY_TIME)) +#define BIT_GET_PS_TIMER_2_EARLY_TIME(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_2_EARLY_TIME) & \ + BIT_MASK_PS_TIMER_2_EARLY_TIME) +#define BIT_SET_PS_TIMER_2_EARLY_TIME(x, v) \ + (BIT_CLEAR_PS_TIMER_2_EARLY_TIME(x) | BIT_PS_TIMER_2_EARLY_TIME(v)) + +#define BIT_PS_TIMER_2_EN BIT(7) + +#define BIT_SHIFT_PS_TIMER_2_TSF_SEL 0 +#define BIT_MASK_PS_TIMER_2_TSF_SEL 0x7 +#define BIT_PS_TIMER_2_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_2_TSF_SEL) << BIT_SHIFT_PS_TIMER_2_TSF_SEL) +#define BITS_PS_TIMER_2_TSF_SEL \ + (BIT_MASK_PS_TIMER_2_TSF_SEL << BIT_SHIFT_PS_TIMER_2_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_2_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_2_TSF_SEL)) +#define BIT_GET_PS_TIMER_2_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_2_TSF_SEL) & BIT_MASK_PS_TIMER_2_TSF_SEL) +#define BIT_SET_PS_TIMER_2_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_2_TSF_SEL(x) | BIT_PS_TIMER_2_TSF_SEL(v)) + +/* 2 REG_PS_TIMER_45_CTRL (Offset 0x15AC) */ + +#define BIT_SHIFT_PS_TIMER_5_EARLY_TIME 24 +#define BIT_MASK_PS_TIMER_5_EARLY_TIME 0xff +#define BIT_PS_TIMER_5_EARLY_TIME(x) \ + (((x) & BIT_MASK_PS_TIMER_5_EARLY_TIME) \ + << BIT_SHIFT_PS_TIMER_5_EARLY_TIME) +#define BITS_PS_TIMER_5_EARLY_TIME \ + (BIT_MASK_PS_TIMER_5_EARLY_TIME << BIT_SHIFT_PS_TIMER_5_EARLY_TIME) +#define BIT_CLEAR_PS_TIMER_5_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_5_EARLY_TIME)) +#define BIT_GET_PS_TIMER_5_EARLY_TIME(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_5_EARLY_TIME) & \ + BIT_MASK_PS_TIMER_5_EARLY_TIME) +#define BIT_SET_PS_TIMER_5_EARLY_TIME(x, v) \ + (BIT_CLEAR_PS_TIMER_5_EARLY_TIME(x) | BIT_PS_TIMER_5_EARLY_TIME(v)) + +#define BIT_PS_TIMER_5_EN BIT(23) + +#define BIT_SHIFT_PS_TIMER_5_TSF_SEL 16 +#define BIT_MASK_PS_TIMER_5_TSF_SEL 0x7 +#define BIT_PS_TIMER_5_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_5_TSF_SEL) << BIT_SHIFT_PS_TIMER_5_TSF_SEL) +#define BITS_PS_TIMER_5_TSF_SEL \ + (BIT_MASK_PS_TIMER_5_TSF_SEL << BIT_SHIFT_PS_TIMER_5_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_5_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_5_TSF_SEL)) +#define BIT_GET_PS_TIMER_5_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_5_TSF_SEL) & BIT_MASK_PS_TIMER_5_TSF_SEL) +#define BIT_SET_PS_TIMER_5_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_5_TSF_SEL(x) | BIT_PS_TIMER_5_TSF_SEL(v)) + +#define BIT_SHIFT_PS_TIMER_4_EARLY_TIME 8 +#define BIT_MASK_PS_TIMER_4_EARLY_TIME 0xff +#define BIT_PS_TIMER_4_EARLY_TIME(x) \ + (((x) & BIT_MASK_PS_TIMER_4_EARLY_TIME) \ + << BIT_SHIFT_PS_TIMER_4_EARLY_TIME) +#define BITS_PS_TIMER_4_EARLY_TIME \ + (BIT_MASK_PS_TIMER_4_EARLY_TIME << BIT_SHIFT_PS_TIMER_4_EARLY_TIME) +#define BIT_CLEAR_PS_TIMER_4_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_4_EARLY_TIME)) +#define BIT_GET_PS_TIMER_4_EARLY_TIME(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_4_EARLY_TIME) & \ + BIT_MASK_PS_TIMER_4_EARLY_TIME) +#define BIT_SET_PS_TIMER_4_EARLY_TIME(x, v) \ + (BIT_CLEAR_PS_TIMER_4_EARLY_TIME(x) | BIT_PS_TIMER_4_EARLY_TIME(v)) + +#define BIT_PS_TIMER_4_EN BIT(7) + +#define BIT_SHIFT_PS_TIMER_4_TSF_SEL 0 +#define BIT_MASK_PS_TIMER_4_TSF_SEL 0x7 +#define BIT_PS_TIMER_4_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_4_TSF_SEL) << BIT_SHIFT_PS_TIMER_4_TSF_SEL) +#define BITS_PS_TIMER_4_TSF_SEL \ + (BIT_MASK_PS_TIMER_4_TSF_SEL << BIT_SHIFT_PS_TIMER_4_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_4_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_4_TSF_SEL)) +#define BIT_GET_PS_TIMER_4_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_4_TSF_SEL) & BIT_MASK_PS_TIMER_4_TSF_SEL) +#define BIT_SET_PS_TIMER_4_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_4_TSF_SEL(x) | BIT_PS_TIMER_4_TSF_SEL(v)) + +/* 2 REG_CPUMGQ_FREERUN_TIMER_CTRL (Offset 0x15B0) */ + +#define BIT_FREECNT_RST_V1 BIT(23) +#define BIT_EN_FREECNT_V1 BIT(16) + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1 8 +#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1 0xff +#define BIT_CPUMGQ_TX_TIMER_EARLY_V1(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1) +#define BITS_CPUMGQ_TX_TIMER_EARLY_V1 \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1 \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_V1)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_V1(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_V1(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1(x) | \ + BIT_CPUMGQ_TX_TIMER_EARLY_V1(v)) + +#define BIT_CPUMGQ_TIMER_EN_V1 BIT(7) +#define BIT_CPUMGQ_DROP_BY_HOLDTIME BIT(5) +#define BIT_CPUMGQ_TX_EN_V1 BIT(4) + +#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1 0 +#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1 0x7 +#define BIT_CPUMGQ_TIMER_TSF_SEL_V1(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1) +#define BITS_CPUMGQ_TIMER_TSF_SEL_V1 \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1(x) \ + ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_V1)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_V1(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_V1(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1(x) | BIT_CPUMGQ_TIMER_TSF_SEL_V1(v)) + +/* 2 REG_CPUMGQ_PROHIBIT (Offset 0x15B4) */ + +#define BIT_SHIFT_CPUMGQ_HOLD_TIME 8 +#define BIT_MASK_CPUMGQ_HOLD_TIME 0xfff +#define BIT_CPUMGQ_HOLD_TIME(x) \ + (((x) & BIT_MASK_CPUMGQ_HOLD_TIME) << BIT_SHIFT_CPUMGQ_HOLD_TIME) +#define BITS_CPUMGQ_HOLD_TIME \ + (BIT_MASK_CPUMGQ_HOLD_TIME << BIT_SHIFT_CPUMGQ_HOLD_TIME) +#define BIT_CLEAR_CPUMGQ_HOLD_TIME(x) ((x) & (~BITS_CPUMGQ_HOLD_TIME)) +#define BIT_GET_CPUMGQ_HOLD_TIME(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_HOLD_TIME) & BIT_MASK_CPUMGQ_HOLD_TIME) +#define BIT_SET_CPUMGQ_HOLD_TIME(x, v) \ + (BIT_CLEAR_CPUMGQ_HOLD_TIME(x) | BIT_CPUMGQ_HOLD_TIME(v)) + +#define BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP 0 +#define BIT_MASK_CPUMGQ_PROHIBIT_SETUP 0xf +#define BIT_CPUMGQ_PROHIBIT_SETUP(x) \ + (((x) & BIT_MASK_CPUMGQ_PROHIBIT_SETUP) \ + << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP) +#define BITS_CPUMGQ_PROHIBIT_SETUP \ + (BIT_MASK_CPUMGQ_PROHIBIT_SETUP << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP) +#define BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP(x) ((x) & (~BITS_CPUMGQ_PROHIBIT_SETUP)) +#define BIT_GET_CPUMGQ_PROHIBIT_SETUP(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP) & \ + BIT_MASK_CPUMGQ_PROHIBIT_SETUP) +#define BIT_SET_CPUMGQ_PROHIBIT_SETUP(x, v) \ + (BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP(x) | BIT_CPUMGQ_PROHIBIT_SETUP(v)) + +/* 2 REG_TIMER_COMPARE (Offset 0x15C0) */ + +#define BIT_COMP_TRIGGER BIT(7) + +#define BIT_SHIFT_Y_COMP 4 +#define BIT_MASK_Y_COMP 0x7 +#define BIT_Y_COMP(x) (((x) & BIT_MASK_Y_COMP) << BIT_SHIFT_Y_COMP) +#define BITS_Y_COMP (BIT_MASK_Y_COMP << BIT_SHIFT_Y_COMP) +#define BIT_CLEAR_Y_COMP(x) ((x) & (~BITS_Y_COMP)) +#define BIT_GET_Y_COMP(x) (((x) >> BIT_SHIFT_Y_COMP) & BIT_MASK_Y_COMP) +#define BIT_SET_Y_COMP(x, v) (BIT_CLEAR_Y_COMP(x) | BIT_Y_COMP(v)) + +#define BIT_X_COMP_Y_OVERFLOW BIT(3) + +#define BIT_SHIFT_X_COMP 0 +#define BIT_MASK_X_COMP 0x7 +#define BIT_X_COMP(x) (((x) & BIT_MASK_X_COMP) << BIT_SHIFT_X_COMP) +#define BITS_X_COMP (BIT_MASK_X_COMP << BIT_SHIFT_X_COMP) +#define BIT_CLEAR_X_COMP(x) ((x) & (~BITS_X_COMP)) +#define BIT_GET_X_COMP(x) (((x) >> BIT_SHIFT_X_COMP) & BIT_MASK_X_COMP) +#define BIT_SET_X_COMP(x, v) (BIT_CLEAR_X_COMP(x) | BIT_X_COMP(v)) + +/* 2 REG_TIMER_COMPARE_VALUE_LOW (Offset 0x15C4) */ + +#define BIT_SHIFT_COMP_VALUE_LOW 0 +#define BIT_MASK_COMP_VALUE_LOW 0xffffffffL +#define BIT_COMP_VALUE_LOW(x) \ + (((x) & BIT_MASK_COMP_VALUE_LOW) << BIT_SHIFT_COMP_VALUE_LOW) +#define BITS_COMP_VALUE_LOW \ + (BIT_MASK_COMP_VALUE_LOW << BIT_SHIFT_COMP_VALUE_LOW) +#define BIT_CLEAR_COMP_VALUE_LOW(x) ((x) & (~BITS_COMP_VALUE_LOW)) +#define BIT_GET_COMP_VALUE_LOW(x) \ + (((x) >> BIT_SHIFT_COMP_VALUE_LOW) & BIT_MASK_COMP_VALUE_LOW) +#define BIT_SET_COMP_VALUE_LOW(x, v) \ + (BIT_CLEAR_COMP_VALUE_LOW(x) | BIT_COMP_VALUE_LOW(v)) + +/* 2 REG_TIMER_COMPARE_VALUE_HIGH (Offset 0x15C8) */ + +#define BIT_SHIFT_COMP_VALUE_HIGH 0 +#define BIT_MASK_COMP_VALUE_HIGH 0xffffffffL +#define BIT_COMP_VALUE_HIGH(x) \ + (((x) & BIT_MASK_COMP_VALUE_HIGH) << BIT_SHIFT_COMP_VALUE_HIGH) +#define BITS_COMP_VALUE_HIGH \ + (BIT_MASK_COMP_VALUE_HIGH << BIT_SHIFT_COMP_VALUE_HIGH) +#define BIT_CLEAR_COMP_VALUE_HIGH(x) ((x) & (~BITS_COMP_VALUE_HIGH)) +#define BIT_GET_COMP_VALUE_HIGH(x) \ + (((x) >> BIT_SHIFT_COMP_VALUE_HIGH) & BIT_MASK_COMP_VALUE_HIGH) +#define BIT_SET_COMP_VALUE_HIGH(x, v) \ + (BIT_CLEAR_COMP_VALUE_HIGH(x) | BIT_COMP_VALUE_HIGH(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_BCN_PSR_RPT2 (Offset 0x1600) */ -/* 2 REG_R_MACID_RELEASE_SUCCESS_0 (Offset 0x1460) */ +#define BIT_SHIFT_DTIM_CNT2 24 +#define BIT_MASK_DTIM_CNT2 0xff +#define BIT_DTIM_CNT2(x) (((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2) +#define BITS_DTIM_CNT2 (BIT_MASK_DTIM_CNT2 << BIT_SHIFT_DTIM_CNT2) +#define BIT_CLEAR_DTIM_CNT2(x) ((x) & (~BITS_DTIM_CNT2)) +#define BIT_GET_DTIM_CNT2(x) (((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2) +#define BIT_SET_DTIM_CNT2(x, v) (BIT_CLEAR_DTIM_CNT2(x) | BIT_DTIM_CNT2(v)) + +#define BIT_SHIFT_DTIM_PERIOD2 16 +#define BIT_MASK_DTIM_PERIOD2 0xff +#define BIT_DTIM_PERIOD2(x) \ + (((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2) +#define BITS_DTIM_PERIOD2 (BIT_MASK_DTIM_PERIOD2 << BIT_SHIFT_DTIM_PERIOD2) +#define BIT_CLEAR_DTIM_PERIOD2(x) ((x) & (~BITS_DTIM_PERIOD2)) +#define BIT_GET_DTIM_PERIOD2(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2) +#define BIT_SET_DTIM_PERIOD2(x, v) \ + (BIT_CLEAR_DTIM_PERIOD2(x) | BIT_DTIM_PERIOD2(v)) + +#define BIT_DTIM2 BIT(15) +#define BIT_TIM2 BIT(14) + +#define BIT_SHIFT_PS_AID_2 0 +#define BIT_MASK_PS_AID_2 0x7ff +#define BIT_PS_AID_2(x) (((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2) +#define BITS_PS_AID_2 (BIT_MASK_PS_AID_2 << BIT_SHIFT_PS_AID_2) +#define BIT_CLEAR_PS_AID_2(x) ((x) & (~BITS_PS_AID_2)) +#define BIT_GET_PS_AID_2(x) (((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2) +#define BIT_SET_PS_AID_2(x, v) (BIT_CLEAR_PS_AID_2(x) | BIT_PS_AID_2(v)) +/* 2 REG_BCN_PSR_RPT3 (Offset 0x1604) */ -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_0(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) +#define BIT_SHIFT_DTIM_CNT3 24 +#define BIT_MASK_DTIM_CNT3 0xff +#define BIT_DTIM_CNT3(x) (((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3) +#define BITS_DTIM_CNT3 (BIT_MASK_DTIM_CNT3 << BIT_SHIFT_DTIM_CNT3) +#define BIT_CLEAR_DTIM_CNT3(x) ((x) & (~BITS_DTIM_CNT3)) +#define BIT_GET_DTIM_CNT3(x) (((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3) +#define BIT_SET_DTIM_CNT3(x, v) (BIT_CLEAR_DTIM_CNT3(x) | BIT_DTIM_CNT3(v)) + +#define BIT_SHIFT_DTIM_PERIOD3 16 +#define BIT_MASK_DTIM_PERIOD3 0xff +#define BIT_DTIM_PERIOD3(x) \ + (((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3) +#define BITS_DTIM_PERIOD3 (BIT_MASK_DTIM_PERIOD3 << BIT_SHIFT_DTIM_PERIOD3) +#define BIT_CLEAR_DTIM_PERIOD3(x) ((x) & (~BITS_DTIM_PERIOD3)) +#define BIT_GET_DTIM_PERIOD3(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3) +#define BIT_SET_DTIM_PERIOD3(x, v) \ + (BIT_CLEAR_DTIM_PERIOD3(x) | BIT_DTIM_PERIOD3(v)) + +#define BIT_DTIM3 BIT(15) +#define BIT_TIM3 BIT(14) + +#define BIT_SHIFT_PS_AID_3 0 +#define BIT_MASK_PS_AID_3 0x7ff +#define BIT_PS_AID_3(x) (((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3) +#define BITS_PS_AID_3 (BIT_MASK_PS_AID_3 << BIT_SHIFT_PS_AID_3) +#define BIT_CLEAR_PS_AID_3(x) ((x) & (~BITS_PS_AID_3)) +#define BIT_GET_PS_AID_3(x) (((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3) +#define BIT_SET_PS_AID_3(x, v) (BIT_CLEAR_PS_AID_3(x) | BIT_PS_AID_3(v)) +/* 2 REG_BCN_PSR_RPT4 (Offset 0x1608) */ -/* 2 REG_R_MACID_RELEASE_SUCCESS_1 (Offset 0x1464) */ +#define BIT_SHIFT_DTIM_CNT4 24 +#define BIT_MASK_DTIM_CNT4 0xff +#define BIT_DTIM_CNT4(x) (((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4) +#define BITS_DTIM_CNT4 (BIT_MASK_DTIM_CNT4 << BIT_SHIFT_DTIM_CNT4) +#define BIT_CLEAR_DTIM_CNT4(x) ((x) & (~BITS_DTIM_CNT4)) +#define BIT_GET_DTIM_CNT4(x) (((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4) +#define BIT_SET_DTIM_CNT4(x, v) (BIT_CLEAR_DTIM_CNT4(x) | BIT_DTIM_CNT4(v)) + +#define BIT_SHIFT_DTIM_PERIOD4 16 +#define BIT_MASK_DTIM_PERIOD4 0xff +#define BIT_DTIM_PERIOD4(x) \ + (((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4) +#define BITS_DTIM_PERIOD4 (BIT_MASK_DTIM_PERIOD4 << BIT_SHIFT_DTIM_PERIOD4) +#define BIT_CLEAR_DTIM_PERIOD4(x) ((x) & (~BITS_DTIM_PERIOD4)) +#define BIT_GET_DTIM_PERIOD4(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4) +#define BIT_SET_DTIM_PERIOD4(x, v) \ + (BIT_CLEAR_DTIM_PERIOD4(x) | BIT_DTIM_PERIOD4(v)) + +#define BIT_DTIM4 BIT(15) +#define BIT_TIM4 BIT(14) + +#define BIT_SHIFT_PS_AID_4 0 +#define BIT_MASK_PS_AID_4 0x7ff +#define BIT_PS_AID_4(x) (((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4) +#define BITS_PS_AID_4 (BIT_MASK_PS_AID_4 << BIT_SHIFT_PS_AID_4) +#define BIT_CLEAR_PS_AID_4(x) ((x) & (~BITS_PS_AID_4)) +#define BIT_GET_PS_AID_4(x) (((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4) +#define BIT_SET_PS_AID_4(x, v) (BIT_CLEAR_PS_AID_4(x) | BIT_PS_AID_4(v)) +/* 2 REG_A1_ADDR_MASK (Offset 0x160C) */ -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_1(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) +#define BIT_SHIFT_A1_ADDR_MASK 0 +#define BIT_MASK_A1_ADDR_MASK 0xffffffffL +#define BIT_A1_ADDR_MASK(x) \ + (((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK) +#define BITS_A1_ADDR_MASK (BIT_MASK_A1_ADDR_MASK << BIT_SHIFT_A1_ADDR_MASK) +#define BIT_CLEAR_A1_ADDR_MASK(x) ((x) & (~BITS_A1_ADDR_MASK)) +#define BIT_GET_A1_ADDR_MASK(x) \ + (((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK) +#define BIT_SET_A1_ADDR_MASK(x, v) \ + (BIT_CLEAR_A1_ADDR_MASK(x) | BIT_A1_ADDR_MASK(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_RXPSF_CTRL (Offset 0x1610) */ + +#define BIT_RXGCK_FIFOTHR_EN BIT(28) + +#define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26 +#define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3 +#define BIT_RXGCK_VHT_FIFOTHR(x) \ + (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR) +#define BITS_RXGCK_VHT_FIFOTHR \ + (BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR) +#define BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) ((x) & (~BITS_RXGCK_VHT_FIFOTHR)) +#define BIT_GET_RXGCK_VHT_FIFOTHR(x) \ + (((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR) & BIT_MASK_RXGCK_VHT_FIFOTHR) +#define BIT_SET_RXGCK_VHT_FIFOTHR(x, v) \ + (BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) | BIT_RXGCK_VHT_FIFOTHR(v)) + +#define BIT_SHIFT_RXGCK_HT_FIFOTHR 24 +#define BIT_MASK_RXGCK_HT_FIFOTHR 0x3 +#define BIT_RXGCK_HT_FIFOTHR(x) \ + (((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR) +#define BITS_RXGCK_HT_FIFOTHR \ + (BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR) +#define BIT_CLEAR_RXGCK_HT_FIFOTHR(x) ((x) & (~BITS_RXGCK_HT_FIFOTHR)) +#define BIT_GET_RXGCK_HT_FIFOTHR(x) \ + (((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR) & BIT_MASK_RXGCK_HT_FIFOTHR) +#define BIT_SET_RXGCK_HT_FIFOTHR(x, v) \ + (BIT_CLEAR_RXGCK_HT_FIFOTHR(x) | BIT_RXGCK_HT_FIFOTHR(v)) + +#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22 +#define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3 +#define BIT_RXGCK_OFDM_FIFOTHR(x) \ + (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) +#define BITS_RXGCK_OFDM_FIFOTHR \ + (BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) +#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) ((x) & (~BITS_RXGCK_OFDM_FIFOTHR)) +#define BIT_GET_RXGCK_OFDM_FIFOTHR(x) \ + (((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR) & BIT_MASK_RXGCK_OFDM_FIFOTHR) +#define BIT_SET_RXGCK_OFDM_FIFOTHR(x, v) \ + (BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) | BIT_RXGCK_OFDM_FIFOTHR(v)) + +#define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20 +#define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3 +#define BIT_RXGCK_CCK_FIFOTHR(x) \ + (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR) +#define BITS_RXGCK_CCK_FIFOTHR \ + (BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR) +#define BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) ((x) & (~BITS_RXGCK_CCK_FIFOTHR)) +#define BIT_GET_RXGCK_CCK_FIFOTHR(x) \ + (((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR) & BIT_MASK_RXGCK_CCK_FIFOTHR) +#define BIT_SET_RXGCK_CCK_FIFOTHR(x, v) \ + (BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) | BIT_RXGCK_CCK_FIFOTHR(v)) + +#define BIT_SHIFT_RXGCK_ENTRY_DELAY 17 +#define BIT_MASK_RXGCK_ENTRY_DELAY 0x7 +#define BIT_RXGCK_ENTRY_DELAY(x) \ + (((x) & BIT_MASK_RXGCK_ENTRY_DELAY) << BIT_SHIFT_RXGCK_ENTRY_DELAY) +#define BITS_RXGCK_ENTRY_DELAY \ + (BIT_MASK_RXGCK_ENTRY_DELAY << BIT_SHIFT_RXGCK_ENTRY_DELAY) +#define BIT_CLEAR_RXGCK_ENTRY_DELAY(x) ((x) & (~BITS_RXGCK_ENTRY_DELAY)) +#define BIT_GET_RXGCK_ENTRY_DELAY(x) \ + (((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY) & BIT_MASK_RXGCK_ENTRY_DELAY) +#define BIT_SET_RXGCK_ENTRY_DELAY(x, v) \ + (BIT_CLEAR_RXGCK_ENTRY_DELAY(x) | BIT_RXGCK_ENTRY_DELAY(v)) + +#define BIT_RXGCK_OFDMCCA_EN BIT(16) + +#define BIT_SHIFT_RXPSF_PKTLENTHR 13 +#define BIT_MASK_RXPSF_PKTLENTHR 0x7 +#define BIT_RXPSF_PKTLENTHR(x) \ + (((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR) +#define BITS_RXPSF_PKTLENTHR \ + (BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR) +#define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR)) +#define BIT_GET_RXPSF_PKTLENTHR(x) \ + (((x) >> BIT_SHIFT_RXPSF_PKTLENTHR) & BIT_MASK_RXPSF_PKTLENTHR) +#define BIT_SET_RXPSF_PKTLENTHR(x, v) \ + (BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v)) + +#define BIT_RXPSF_CTRLEN BIT(12) +#define BIT_RXPSF_VHTCHKEN BIT(11) +#define BIT_RXPSF_HTCHKEN BIT(10) +#define BIT_RXPSF_OFDMCHKEN BIT(9) +#define BIT_RXPSF_CCKCHKEN BIT(8) +#define BIT_RXPSF_OFDMRST BIT(7) +#define BIT_RXPSF_CCKRST BIT(6) +#define BIT_RXPSF_MHCHKEN BIT(5) +#define BIT_RXPSF_CONT_ERRCHKEN BIT(4) +#define BIT_RXPSF_ALL_ERRCHKEN BIT(3) + +#define BIT_SHIFT_RXPSF_ERRTHR 0 +#define BIT_MASK_RXPSF_ERRTHR 0x7 +#define BIT_RXPSF_ERRTHR(x) \ + (((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR) +#define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR) +#define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR)) +#define BIT_GET_RXPSF_ERRTHR(x) \ + (((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR) +#define BIT_SET_RXPSF_ERRTHR(x, v) \ + (BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v)) + +/* 2 REG_RXPSF_TYPE_CTRL (Offset 0x1614) */ + +#define BIT_RXPSF_DATA15EN BIT(31) +#define BIT_RXPSF_DATA14EN BIT(30) +#define BIT_RXPSF_DATA13EN BIT(29) +#define BIT_RXPSF_DATA12EN BIT(28) +#define BIT_RXPSF_DATA11EN BIT(27) +#define BIT_RXPSF_DATA10EN BIT(26) +#define BIT_RXPSF_DATA9EN BIT(25) +#define BIT_RXPSF_DATA8EN BIT(24) +#define BIT_RXPSF_DATA7EN BIT(23) +#define BIT_RXPSF_DATA6EN BIT(22) +#define BIT_RXPSF_DATA5EN BIT(21) +#define BIT_RXPSF_DATA4EN BIT(20) +#define BIT_RXPSF_DATA3EN BIT(19) +#define BIT_RXPSF_DATA2EN BIT(18) +#define BIT_RXPSF_DATA1EN BIT(17) +#define BIT_RXPSF_DATA0EN BIT(16) +#define BIT_RXPSF_MGT15EN BIT(15) +#define BIT_RXPSF_MGT14EN BIT(14) +#define BIT_RXPSF_MGT13EN BIT(13) +#define BIT_RXPSF_MGT12EN BIT(12) +#define BIT_RXPSF_MGT11EN BIT(11) +#define BIT_RXPSF_MGT10EN BIT(10) +#define BIT_RXPSF_MGT9EN BIT(9) +#define BIT_RXPSF_MGT8EN BIT(8) +#define BIT_RXPSF_MGT7EN BIT(7) +#define BIT_RXPSF_MGT6EN BIT(6) +#define BIT_RXPSF_MGT5EN BIT(5) +#define BIT_RXPSF_MGT4EN BIT(4) +#define BIT_RXPSF_MGT3EN BIT(3) +#define BIT_RXPSF_MGT2EN BIT(2) +#define BIT_RXPSF_MGT1EN BIT(1) +#define BIT_RXPSF_MGT0EN BIT(0) + +/* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */ + +#define BIT_INDIRECT_ERR BIT(6) +#define BIT_DIRECT_ERR BIT(5) +#define BIT_DIR_ACCESS_EN_RX_BA BIT(4) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */ + +#define BIT_DIR_ACCESS_EN_ADDRCAM BIT(3) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */ + +#define BIT_DIR_ACCESS_EN_MBSSIDCAM BIT(3) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */ + +#define BIT_DIR_ACCESS_EN_KEY BIT(2) +#define BIT_DIR_ACCESS_EN_WOWLAN BIT(1) +#define BIT_DIR_ACCESS_EN_FW_FILTER BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CUT_AMSDU_CTRL (Offset 0x161C) */ + +#define BIT__CUT_AMSDU_CHKLEN_EN BIT(31) +#define BIT_EN_CUT_AMSDU BIT(30) + +#define BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH 16 +#define BIT_MASK_CUT_AMSDU_CHKLEN_L_TH 0xff +#define BIT_CUT_AMSDU_CHKLEN_L_TH(x) \ + (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_L_TH) \ + << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH) +#define BITS_CUT_AMSDU_CHKLEN_L_TH \ + (BIT_MASK_CUT_AMSDU_CHKLEN_L_TH << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH) +#define BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH(x) ((x) & (~BITS_CUT_AMSDU_CHKLEN_L_TH)) +#define BIT_GET_CUT_AMSDU_CHKLEN_L_TH(x) \ + (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH) & \ + BIT_MASK_CUT_AMSDU_CHKLEN_L_TH) +#define BIT_SET_CUT_AMSDU_CHKLEN_L_TH(x, v) \ + (BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH(x) | BIT_CUT_AMSDU_CHKLEN_L_TH(v)) +#define BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH 0 +#define BIT_MASK_CUT_AMSDU_CHKLEN_H_TH 0xffff +#define BIT_CUT_AMSDU_CHKLEN_H_TH(x) \ + (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_H_TH) \ + << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH) +#define BITS_CUT_AMSDU_CHKLEN_H_TH \ + (BIT_MASK_CUT_AMSDU_CHKLEN_H_TH << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH) +#define BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH(x) ((x) & (~BITS_CUT_AMSDU_CHKLEN_H_TH)) +#define BIT_GET_CUT_AMSDU_CHKLEN_H_TH(x) \ + (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH) & \ + BIT_MASK_CUT_AMSDU_CHKLEN_H_TH) +#define BIT_SET_CUT_AMSDU_CHKLEN_H_TH(x, v) \ + (BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH(x) | BIT_CUT_AMSDU_CHKLEN_H_TH(v)) -/* 2 REG_R_MACID_RELEASE_SUCCESS_2 (Offset 0x1468) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_2(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) +/* 2 REG_HT_SND_REF_RATE (Offset 0x161C) */ +#define BIT_SHIFT_WMAC_HT_CSI_RATE 0 +#define BIT_MASK_WMAC_HT_CSI_RATE 0x3f +#define BIT_WMAC_HT_CSI_RATE(x) \ + (((x) & BIT_MASK_WMAC_HT_CSI_RATE) << BIT_SHIFT_WMAC_HT_CSI_RATE) +#define BITS_WMAC_HT_CSI_RATE \ + (BIT_MASK_WMAC_HT_CSI_RATE << BIT_SHIFT_WMAC_HT_CSI_RATE) +#define BIT_CLEAR_WMAC_HT_CSI_RATE(x) ((x) & (~BITS_WMAC_HT_CSI_RATE)) +#define BIT_GET_WMAC_HT_CSI_RATE(x) \ + (((x) >> BIT_SHIFT_WMAC_HT_CSI_RATE) & BIT_MASK_WMAC_HT_CSI_RATE) +#define BIT_SET_WMAC_HT_CSI_RATE(x, v) \ + (BIT_CLEAR_WMAC_HT_CSI_RATE(x) | BIT_WMAC_HT_CSI_RATE(v)) -/* 2 REG_R_MACID_RELEASE_SUCCESS_3 (Offset 0x146C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_3(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) +/* 2 REG_MACID2 (Offset 0x1620) */ +#define BIT_SHIFT_MACID2 0 +#define BIT_MASK_MACID2 0xffffffffffffL +#define BIT_MACID2(x) (((x) & BIT_MASK_MACID2) << BIT_SHIFT_MACID2) +#define BITS_MACID2 (BIT_MASK_MACID2 << BIT_SHIFT_MACID2) +#define BIT_CLEAR_MACID2(x) ((x) & (~BITS_MACID2)) +#define BIT_GET_MACID2(x) (((x) >> BIT_SHIFT_MACID2) & BIT_MASK_MACID2) +#define BIT_SET_MACID2(x, v) (BIT_CLEAR_MACID2(x) | BIT_MACID2(v)) -/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ +#endif -#define BIT_R_MGG_FIFO_EN BIT(31) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE 28 -#define BIT_MASK_R_MGG_FIFO_PG_SIZE 0x7 -#define BIT_R_MGG_FIFO_PG_SIZE(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE) -#define BIT_GET_R_MGG_FIFO_PG_SIZE(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE) & BIT_MASK_R_MGG_FIFO_PG_SIZE) +/* 2 REG_MACID2 (Offset 0x1620) */ +#define BIT_SHIFT_MACID2_V1 0 +#define BIT_MASK_MACID2_V1 0xffffffffL +#define BIT_MACID2_V1(x) (((x) & BIT_MASK_MACID2_V1) << BIT_SHIFT_MACID2_V1) +#define BITS_MACID2_V1 (BIT_MASK_MACID2_V1 << BIT_SHIFT_MACID2_V1) +#define BIT_CLEAR_MACID2_V1(x) ((x) & (~BITS_MACID2_V1)) +#define BIT_GET_MACID2_V1(x) (((x) >> BIT_SHIFT_MACID2_V1) & BIT_MASK_MACID2_V1) +#define BIT_SET_MACID2_V1(x, v) (BIT_CLEAR_MACID2_V1(x) | BIT_MACID2_V1(v)) -#define BIT_SHIFT_R_MGG_FIFO_START_PG 16 -#define BIT_MASK_R_MGG_FIFO_START_PG 0xfff -#define BIT_R_MGG_FIFO_START_PG(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG) << BIT_SHIFT_R_MGG_FIFO_START_PG) -#define BIT_GET_R_MGG_FIFO_START_PG(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG) & BIT_MASK_R_MGG_FIFO_START_PG) +/* 2 REG_MACID2_H (Offset 0x1624) */ +#define BIT_SHIFT_MACID2_H_V1 0 +#define BIT_MASK_MACID2_H_V1 0xffff +#define BIT_MACID2_H_V1(x) \ + (((x) & BIT_MASK_MACID2_H_V1) << BIT_SHIFT_MACID2_H_V1) +#define BITS_MACID2_H_V1 (BIT_MASK_MACID2_H_V1 << BIT_SHIFT_MACID2_H_V1) +#define BIT_CLEAR_MACID2_H_V1(x) ((x) & (~BITS_MACID2_H_V1)) +#define BIT_GET_MACID2_H_V1(x) \ + (((x) >> BIT_SHIFT_MACID2_H_V1) & BIT_MASK_MACID2_H_V1) +#define BIT_SET_MACID2_H_V1(x, v) \ + (BIT_CLEAR_MACID2_H_V1(x) | BIT_MACID2_H_V1(v)) -#define BIT_SHIFT_R_MGG_FIFO_SIZE 14 -#define BIT_MASK_R_MGG_FIFO_SIZE 0x3 -#define BIT_R_MGG_FIFO_SIZE(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE) << BIT_SHIFT_R_MGG_FIFO_SIZE) -#define BIT_GET_R_MGG_FIFO_SIZE(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE) & BIT_MASK_R_MGG_FIFO_SIZE) +#endif -#define BIT_R_MGG_FIFO_PAUSE BIT(13) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_R_MGG_FIFO_RPTR 8 -#define BIT_MASK_R_MGG_FIFO_RPTR 0x1f -#define BIT_R_MGG_FIFO_RPTR(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR) << BIT_SHIFT_R_MGG_FIFO_RPTR) -#define BIT_GET_R_MGG_FIFO_RPTR(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR) & BIT_MASK_R_MGG_FIFO_RPTR) +/* 2 REG_BSSID2 (Offset 0x1628) */ -#define BIT_R_MGG_FIFO_OV BIT(7) -#define BIT_R_MGG_FIFO_WPTR_ERROR BIT(6) -#define BIT_R_EN_CPU_LIFETIME BIT(5) +#define BIT_SHIFT_BSSID2 0 +#define BIT_MASK_BSSID2 0xffffffffffffL +#define BIT_BSSID2(x) (((x) & BIT_MASK_BSSID2) << BIT_SHIFT_BSSID2) +#define BITS_BSSID2 (BIT_MASK_BSSID2 << BIT_SHIFT_BSSID2) +#define BIT_CLEAR_BSSID2(x) ((x) & (~BITS_BSSID2)) +#define BIT_GET_BSSID2(x) (((x) >> BIT_SHIFT_BSSID2) & BIT_MASK_BSSID2) +#define BIT_SET_BSSID2(x, v) (BIT_CLEAR_BSSID2(x) | BIT_BSSID2(v)) -#define BIT_SHIFT_R_MGG_FIFO_WPTR 0 -#define BIT_MASK_R_MGG_FIFO_WPTR 0x1f -#define BIT_R_MGG_FIFO_WPTR(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR) << BIT_SHIFT_R_MGG_FIFO_WPTR) -#define BIT_GET_R_MGG_FIFO_WPTR(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR) & BIT_MASK_R_MGG_FIFO_WPTR) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_MGG_FIFO_INT (Offset 0x1474) */ +/* 2 REG_BSSID2 (Offset 0x1628) */ +#define BIT_SHIFT_BSSID2_V1 0 +#define BIT_MASK_BSSID2_V1 0xffffffffL +#define BIT_BSSID2_V1(x) (((x) & BIT_MASK_BSSID2_V1) << BIT_SHIFT_BSSID2_V1) +#define BITS_BSSID2_V1 (BIT_MASK_BSSID2_V1 << BIT_SHIFT_BSSID2_V1) +#define BIT_CLEAR_BSSID2_V1(x) ((x) & (~BITS_BSSID2_V1)) +#define BIT_GET_BSSID2_V1(x) (((x) >> BIT_SHIFT_BSSID2_V1) & BIT_MASK_BSSID2_V1) +#define BIT_SET_BSSID2_V1(x, v) (BIT_CLEAR_BSSID2_V1(x) | BIT_BSSID2_V1(v)) -#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG 16 -#define BIT_MASK_R_MGG_FIFO_INT_FLAG 0xffff -#define BIT_R_MGG_FIFO_INT_FLAG(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG) -#define BIT_GET_R_MGG_FIFO_INT_FLAG(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG) & BIT_MASK_R_MGG_FIFO_INT_FLAG) +/* 2 REG_BSSID2_H (Offset 0x162C) */ +#define BIT_SHIFT_BSSID2_H_V1 0 +#define BIT_MASK_BSSID2_H_V1 0xffff +#define BIT_BSSID2_H_V1(x) \ + (((x) & BIT_MASK_BSSID2_H_V1) << BIT_SHIFT_BSSID2_H_V1) +#define BITS_BSSID2_H_V1 (BIT_MASK_BSSID2_H_V1 << BIT_SHIFT_BSSID2_H_V1) +#define BIT_CLEAR_BSSID2_H_V1(x) ((x) & (~BITS_BSSID2_H_V1)) +#define BIT_GET_BSSID2_H_V1(x) \ + (((x) >> BIT_SHIFT_BSSID2_H_V1) & BIT_MASK_BSSID2_H_V1) +#define BIT_SET_BSSID2_H_V1(x, v) \ + (BIT_CLEAR_BSSID2_H_V1(x) | BIT_BSSID2_H_V1(v)) -#define BIT_SHIFT_R_MGG_FIFO_INT_MASK 0 -#define BIT_MASK_R_MGG_FIFO_INT_MASK 0xffff -#define BIT_R_MGG_FIFO_INT_MASK(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK) << BIT_SHIFT_R_MGG_FIFO_INT_MASK) -#define BIT_GET_R_MGG_FIFO_INT_MASK(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK) & BIT_MASK_R_MGG_FIFO_INT_MASK) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_MGG_FIFO_LIFETIME (Offset 0x1478) */ +/* 2 REG_MACID3 (Offset 0x1630) */ +#define BIT_SHIFT_MACID3 0 +#define BIT_MASK_MACID3 0xffffffffffffL +#define BIT_MACID3(x) (((x) & BIT_MASK_MACID3) << BIT_SHIFT_MACID3) +#define BITS_MACID3 (BIT_MASK_MACID3 << BIT_SHIFT_MACID3) +#define BIT_CLEAR_MACID3(x) ((x) & (~BITS_MACID3)) +#define BIT_GET_MACID3(x) (((x) >> BIT_SHIFT_MACID3) & BIT_MASK_MACID3) +#define BIT_SET_MACID3(x, v) (BIT_CLEAR_MACID3(x) | BIT_MACID3(v)) -#define BIT_SHIFT_R_MGG_FIFO_LIFETIME 16 -#define BIT_MASK_R_MGG_FIFO_LIFETIME 0xffff -#define BIT_R_MGG_FIFO_LIFETIME(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME) << BIT_SHIFT_R_MGG_FIFO_LIFETIME) -#define BIT_GET_R_MGG_FIFO_LIFETIME(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME) & BIT_MASK_R_MGG_FIFO_LIFETIME) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP 0 -#define BIT_MASK_R_MGG_FIFO_VALID_MAP 0xffff -#define BIT_R_MGG_FIFO_VALID_MAP(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP) -#define BIT_GET_R_MGG_FIFO_VALID_MAP(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP) & BIT_MASK_R_MGG_FIFO_VALID_MAP) +/* 2 REG_MACID3 (Offset 0x1630) */ +#define BIT_SHIFT_MACID3_V1 0 +#define BIT_MASK_MACID3_V1 0xffffffffL +#define BIT_MACID3_V1(x) (((x) & BIT_MASK_MACID3_V1) << BIT_SHIFT_MACID3_V1) +#define BITS_MACID3_V1 (BIT_MASK_MACID3_V1 << BIT_SHIFT_MACID3_V1) +#define BIT_CLEAR_MACID3_V1(x) ((x) & (~BITS_MACID3_V1)) +#define BIT_GET_MACID3_V1(x) (((x) >> BIT_SHIFT_MACID3_V1) & BIT_MASK_MACID3_V1) +#define BIT_SET_MACID3_V1(x, v) (BIT_CLEAR_MACID3_V1(x) | BIT_MACID3_V1(v)) -/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET (Offset 0x147C) */ +/* 2 REG_MACID3_H (Offset 0x1634) */ +#define BIT_SHIFT_MACID3_H_V1 0 +#define BIT_MASK_MACID3_H_V1 0xffff +#define BIT_MACID3_H_V1(x) \ + (((x) & BIT_MASK_MACID3_H_V1) << BIT_SHIFT_MACID3_H_V1) +#define BITS_MACID3_H_V1 (BIT_MASK_MACID3_H_V1 << BIT_SHIFT_MACID3_H_V1) +#define BIT_CLEAR_MACID3_H_V1(x) ((x) & (~BITS_MACID3_H_V1)) +#define BIT_GET_MACID3_H_V1(x) \ + (((x) >> BIT_SHIFT_MACID3_H_V1) & BIT_MASK_MACID3_H_V1) +#define BIT_SET_MACID3_H_V1(x, v) \ + (BIT_CLEAR_MACID3_H_V1(x) | BIT_MACID3_H_V1(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x7f -#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_P2PON_DIS_TXTIME 0 -#define BIT_MASK_P2PON_DIS_TXTIME 0xff -#define BIT_P2PON_DIS_TXTIME(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME) -#define BIT_GET_P2PON_DIS_TXTIME(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME) +/* 2 REG_BSSID3 (Offset 0x1638) */ +#define BIT_SHIFT_BSSID3 0 +#define BIT_MASK_BSSID3 0xffffffffffffL +#define BIT_BSSID3(x) (((x) & BIT_MASK_BSSID3) << BIT_SHIFT_BSSID3) +#define BITS_BSSID3 (BIT_MASK_BSSID3 << BIT_SHIFT_BSSID3) +#define BIT_CLEAR_BSSID3(x) ((x) & (~BITS_BSSID3)) +#define BIT_GET_BSSID3(x) (((x) >> BIT_SHIFT_BSSID3) & BIT_MASK_BSSID3) +#define BIT_SET_BSSID3(x, v) (BIT_CLEAR_BSSID3(x) | BIT_BSSID3(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_BSSID3 (Offset 0x1638) */ +#define BIT_SHIFT_BSSID3_V1 0 +#define BIT_MASK_BSSID3_V1 0xffffffffL +#define BIT_BSSID3_V1(x) (((x) & BIT_MASK_BSSID3_V1) << BIT_SHIFT_BSSID3_V1) +#define BITS_BSSID3_V1 (BIT_MASK_BSSID3_V1 << BIT_SHIFT_BSSID3_V1) +#define BIT_CLEAR_BSSID3_V1(x) ((x) & (~BITS_BSSID3_V1)) +#define BIT_GET_BSSID3_V1(x) (((x) >> BIT_SHIFT_BSSID3_V1) & BIT_MASK_BSSID3_V1) +#define BIT_SET_BSSID3_V1(x, v) (BIT_CLEAR_BSSID3_V1(x) | BIT_BSSID3_V1(v)) -/* 2 REG_MACID_SHCUT_OFFSET (Offset 0x1480) */ +/* 2 REG_BSSID3_H (Offset 0x163C) */ +#define BIT_SHIFT_BSSID3_H_V1 0 +#define BIT_MASK_BSSID3_H_V1 0xffff +#define BIT_BSSID3_H_V1(x) \ + (((x) & BIT_MASK_BSSID3_H_V1) << BIT_SHIFT_BSSID3_H_V1) +#define BITS_BSSID3_H_V1 (BIT_MASK_BSSID3_H_V1 << BIT_SHIFT_BSSID3_H_V1) +#define BIT_CLEAR_BSSID3_H_V1(x) ((x) & (~BITS_BSSID3_H_V1)) +#define BIT_GET_BSSID3_H_V1(x) \ + (((x) >> BIT_SHIFT_BSSID3_H_V1) & BIT_MASK_BSSID3_H_V1) +#define BIT_SET_BSSID3_H_V1(x, v) \ + (BIT_CLEAR_BSSID3_H_V1(x) | BIT_BSSID3_H_V1(v)) -#define BIT_SHIFT_MACID_SHCUT_OFFSET_V1 0 -#define BIT_MASK_MACID_SHCUT_OFFSET_V1 0xff -#define BIT_MACID_SHCUT_OFFSET_V1(x) (((x) & BIT_MASK_MACID_SHCUT_OFFSET_V1) << BIT_SHIFT_MACID_SHCUT_OFFSET_V1) -#define BIT_GET_MACID_SHCUT_OFFSET_V1(x) (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET_V1) & BIT_MASK_MACID_SHCUT_OFFSET_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_MACID4 (Offset 0x1640) */ +#define BIT_SHIFT_MACID4 0 +#define BIT_MASK_MACID4 0xffffffffffffL +#define BIT_MACID4(x) (((x) & BIT_MASK_MACID4) << BIT_SHIFT_MACID4) +#define BITS_MACID4 (BIT_MASK_MACID4 << BIT_SHIFT_MACID4) +#define BIT_CLEAR_MACID4(x) ((x) & (~BITS_MACID4)) +#define BIT_GET_MACID4(x) (((x) >> BIT_SHIFT_MACID4) & BIT_MASK_MACID4) +#define BIT_SET_MACID4(x, v) (BIT_CLEAR_MACID4(x) | BIT_MACID4(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ +/* 2 REG_MACID4 (Offset 0x1640) */ -#define BIT_R_FORCE_P1_RATEDOWN BIT(11) +#define BIT_SHIFT_MACID4_V1 0 +#define BIT_MASK_MACID4_V1 0xffffffffL +#define BIT_MACID4_V1(x) (((x) & BIT_MASK_MACID4_V1) << BIT_SHIFT_MACID4_V1) +#define BITS_MACID4_V1 (BIT_MASK_MACID4_V1 << BIT_SHIFT_MACID4_V1) +#define BIT_CLEAR_MACID4_V1(x) ((x) & (~BITS_MACID4_V1)) +#define BIT_GET_MACID4_V1(x) (((x) >> BIT_SHIFT_MACID4_V1) & BIT_MASK_MACID4_V1) +#define BIT_SET_MACID4_V1(x, v) (BIT_CLEAR_MACID4_V1(x) | BIT_MACID4_V1(v)) -#define BIT_SHIFT_R_MU_TAB_SEL 8 -#define BIT_MASK_R_MU_TAB_SEL 0x7 -#define BIT_R_MU_TAB_SEL(x) (((x) & BIT_MASK_R_MU_TAB_SEL) << BIT_SHIFT_R_MU_TAB_SEL) -#define BIT_GET_R_MU_TAB_SEL(x) (((x) >> BIT_SHIFT_R_MU_TAB_SEL) & BIT_MASK_R_MU_TAB_SEL) +/* 2 REG_MACID4_H (Offset 0x1644) */ -#define BIT_R_EN_MU_MIMO BIT(7) +#define BIT_SHIFT_MACID4_H_V1 0 +#define BIT_MASK_MACID4_H_V1 0xffff +#define BIT_MACID4_H_V1(x) \ + (((x) & BIT_MASK_MACID4_H_V1) << BIT_SHIFT_MACID4_H_V1) +#define BITS_MACID4_H_V1 (BIT_MASK_MACID4_H_V1 << BIT_SHIFT_MACID4_H_V1) +#define BIT_CLEAR_MACID4_H_V1(x) ((x) & (~BITS_MACID4_H_V1)) +#define BIT_GET_MACID4_H_V1(x) \ + (((x) >> BIT_SHIFT_MACID4_H_V1) & BIT_MASK_MACID4_H_V1) +#define BIT_SET_MACID4_H_V1(x, v) \ + (BIT_CLEAR_MACID4_H_V1(x) | BIT_MACID4_H_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BSSID4 (Offset 0x1648) */ +#define BIT_SHIFT_BSSID4 0 +#define BIT_MASK_BSSID4 0xffffffffffffL +#define BIT_BSSID4(x) (((x) & BIT_MASK_BSSID4) << BIT_SHIFT_BSSID4) +#define BITS_BSSID4 (BIT_MASK_BSSID4 << BIT_SHIFT_BSSID4) +#define BIT_CLEAR_BSSID4(x) ((x) & (~BITS_BSSID4)) +#define BIT_GET_BSSID4(x) (((x) >> BIT_SHIFT_BSSID4) & BIT_MASK_BSSID4) +#define BIT_SET_BSSID4(x, v) (BIT_CLEAR_BSSID4(x) | BIT_BSSID4(v)) -/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ +#endif -#define BIT_R_EN_REVERS_GTAB BIT(6) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_MU_TABLE_VALID 0 -#define BIT_MASK_R_MU_TABLE_VALID 0x3f -#define BIT_R_MU_TABLE_VALID(x) (((x) & BIT_MASK_R_MU_TABLE_VALID) << BIT_SHIFT_R_MU_TABLE_VALID) -#define BIT_GET_R_MU_TABLE_VALID(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID) & BIT_MASK_R_MU_TABLE_VALID) +/* 2 REG_BSSID4 (Offset 0x1648) */ +#define BIT_SHIFT_BSSID4_V1 0 +#define BIT_MASK_BSSID4_V1 0xffffffffL +#define BIT_BSSID4_V1(x) (((x) & BIT_MASK_BSSID4_V1) << BIT_SHIFT_BSSID4_V1) +#define BITS_BSSID4_V1 (BIT_MASK_BSSID4_V1 << BIT_SHIFT_BSSID4_V1) +#define BIT_CLEAR_BSSID4_V1(x) ((x) & (~BITS_BSSID4_V1)) +#define BIT_GET_BSSID4_V1(x) (((x) >> BIT_SHIFT_BSSID4_V1) & BIT_MASK_BSSID4_V1) +#define BIT_SET_BSSID4_V1(x, v) (BIT_CLEAR_BSSID4_V1(x) | BIT_BSSID4_V1(v)) -#define BIT_SHIFT_R_MU_STA_GTAB_VALID 0 -#define BIT_MASK_R_MU_STA_GTAB_VALID 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID) << BIT_SHIFT_R_MU_STA_GTAB_VALID) -#define BIT_GET_R_MU_STA_GTAB_VALID(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID) & BIT_MASK_R_MU_STA_GTAB_VALID) +/* 2 REG_BSSID4_H (Offset 0x164C) */ +#define BIT_SHIFT_BSSID4_H_V1 0 +#define BIT_MASK_BSSID4_H_V1 0xffff +#define BIT_BSSID4_H_V1(x) \ + (((x) & BIT_MASK_BSSID4_H_V1) << BIT_SHIFT_BSSID4_H_V1) +#define BITS_BSSID4_H_V1 (BIT_MASK_BSSID4_H_V1 << BIT_SHIFT_BSSID4_H_V1) +#define BIT_CLEAR_BSSID4_H_V1(x) ((x) & (~BITS_BSSID4_H_V1)) +#define BIT_GET_BSSID4_H_V1(x) \ + (((x) >> BIT_SHIFT_BSSID4_H_V1) & BIT_MASK_BSSID4_H_V1) +#define BIT_SET_BSSID4_H_V1(x, v) \ + (BIT_CLEAR_BSSID4_H_V1(x) | BIT_BSSID4_H_V1(v)) -#define BIT_SHIFT_R_MU_STA_GTAB_POSITION 0 -#define BIT_MASK_R_MU_STA_GTAB_POSITION 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION) << BIT_SHIFT_R_MU_STA_GTAB_POSITION) -#define BIT_GET_R_MU_STA_GTAB_POSITION(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION) & BIT_MASK_R_MU_STA_GTAB_POSITION) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ +/* 2 REG_NOA_REPORT (Offset 0x1650) */ -#define BIT_MU_DNGCNT_RST BIT(20) +#define BIT_SHIFT_NOA_RPT 0 +#define BIT_MASK_NOA_RPT 0xffffffffL +#define BIT_NOA_RPT(x) (((x) & BIT_MASK_NOA_RPT) << BIT_SHIFT_NOA_RPT) +#define BITS_NOA_RPT (BIT_MASK_NOA_RPT << BIT_SHIFT_NOA_RPT) +#define BIT_CLEAR_NOA_RPT(x) ((x) & (~BITS_NOA_RPT)) +#define BIT_GET_NOA_RPT(x) (((x) >> BIT_SHIFT_NOA_RPT) & BIT_MASK_NOA_RPT) +#define BIT_SET_NOA_RPT(x, v) (BIT_CLEAR_NOA_RPT(x) | BIT_NOA_RPT(v)) -#define BIT_SHIFT_MU_DBGCNT_SEL 16 -#define BIT_MASK_MU_DBGCNT_SEL 0xf -#define BIT_MU_DBGCNT_SEL(x) (((x) & BIT_MASK_MU_DBGCNT_SEL) << BIT_SHIFT_MU_DBGCNT_SEL) -#define BIT_GET_MU_DBGCNT_SEL(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL) & BIT_MASK_MU_DBGCNT_SEL) +/* 2 REG_NOA_REPORT_1 (Offset 0x1654) */ +#define BIT_SHIFT_NOA_RPT_1 0 +#define BIT_MASK_NOA_RPT_1 0xffffffffL +#define BIT_NOA_RPT_1(x) (((x) & BIT_MASK_NOA_RPT_1) << BIT_SHIFT_NOA_RPT_1) +#define BITS_NOA_RPT_1 (BIT_MASK_NOA_RPT_1 << BIT_SHIFT_NOA_RPT_1) +#define BIT_CLEAR_NOA_RPT_1(x) ((x) & (~BITS_NOA_RPT_1)) +#define BIT_GET_NOA_RPT_1(x) (((x) >> BIT_SHIFT_NOA_RPT_1) & BIT_MASK_NOA_RPT_1) +#define BIT_SET_NOA_RPT_1(x, v) (BIT_CLEAR_NOA_RPT_1(x) | BIT_NOA_RPT_1(v)) -#define BIT_SHIFT_MU_DNGCNT 0 -#define BIT_MASK_MU_DNGCNT 0xffff -#define BIT_MU_DNGCNT(x) (((x) & BIT_MASK_MU_DNGCNT) << BIT_SHIFT_MU_DNGCNT) -#define BIT_GET_MU_DNGCNT(x) (((x) >> BIT_SHIFT_MU_DNGCNT) & BIT_MASK_MU_DNGCNT) +/* 2 REG_NOA_REPORT_2 (Offset 0x1658) */ +#define BIT_SHIFT_NOA_RPT_2 0 +#define BIT_MASK_NOA_RPT_2 0xffffffffL +#define BIT_NOA_RPT_2(x) (((x) & BIT_MASK_NOA_RPT_2) << BIT_SHIFT_NOA_RPT_2) +#define BITS_NOA_RPT_2 (BIT_MASK_NOA_RPT_2 << BIT_SHIFT_NOA_RPT_2) +#define BIT_CLEAR_NOA_RPT_2(x) ((x) & (~BITS_NOA_RPT_2)) +#define BIT_GET_NOA_RPT_2(x) (((x) >> BIT_SHIFT_NOA_RPT_2) & BIT_MASK_NOA_RPT_2) +#define BIT_SET_NOA_RPT_2(x, v) (BIT_CLEAR_NOA_RPT_2(x) | BIT_NOA_RPT_2(v)) -#endif +/* 2 REG_NOA_REPORT_3 (Offset 0x165C) */ +#define BIT_SHIFT_NOA_RPT_3 0 +#define BIT_MASK_NOA_RPT_3 0xff +#define BIT_NOA_RPT_3(x) (((x) & BIT_MASK_NOA_RPT_3) << BIT_SHIFT_NOA_RPT_3) +#define BITS_NOA_RPT_3 (BIT_MASK_NOA_RPT_3 << BIT_SHIFT_NOA_RPT_3) +#define BIT_CLEAR_NOA_RPT_3(x) ((x) & (~BITS_NOA_RPT_3)) +#define BIT_GET_NOA_RPT_3(x) (((x) >> BIT_SHIFT_NOA_RPT_3) & BIT_MASK_NOA_RPT_3) +#define BIT_SET_NOA_RPT_3(x, v) (BIT_CLEAR_NOA_RPT_3(x) | BIT_NOA_RPT_3(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_CPUMGQ_TX_TIMER (Offset 0x1500) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN BIT(15) +#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN BIT(14) +#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN BIT(13) +#define BIT_CLI3_PWR_ST_V1 BIT(12) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN BIT(11) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN BIT(10) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN BIT(9) +#define BIT_CLI2_PWR_ST_V1 BIT(8) -#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1 0 -#define BIT_MASK_CPUMGQ_TX_TIMER_V1 0xffffffffL -#define BIT_CPUMGQ_TX_TIMER_V1(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1) -#define BIT_GET_CPUMGQ_TX_TIMER_V1(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -/* 2 REG_PS_TIMER_A (Offset 0x1504) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI3_PWRBIT_OW_EN BIT(7) -#define BIT_SHIFT_PS_TIMER_A_V1 0 -#define BIT_MASK_PS_TIMER_A_V1 0xffffffffL -#define BIT_PS_TIMER_A_V1(x) (((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1) -#define BIT_GET_PS_TIMER_A_V1(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_PS_TIMER_B (Offset 0x1508) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN BIT(7) -#define BIT_SHIFT_PS_TIMER_B_V1 0 -#define BIT_MASK_PS_TIMER_B_V1 0xffffffffL -#define BIT_PS_TIMER_B_V1(x) (((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1) -#define BIT_GET_PS_TIMER_B_V1(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -/* 2 REG_PS_TIMER_C (Offset 0x150C) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI3_PWR_ST BIT(6) -#define BIT_SHIFT_PS_TIMER_C_V1 0 -#define BIT_MASK_PS_TIMER_C_V1 0xffffffffL -#define BIT_PS_TIMER_C_V1(x) (((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1) -#define BIT_GET_PS_TIMER_C_V1(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL (Offset 0x1510) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ -#define BIT_CPUMGQ_TIMER_EN BIT(31) -#define BIT_CPUMGQ_TX_EN BIT(28) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN BIT(6) -#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL 24 -#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL 0x7 -#define BIT_CPUMGQ_TIMER_TSF_SEL(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) -#define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) +#endif -#define BIT_PS_TIMER_C_EN BIT(23) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_PS_TIMER_C_TSF_SEL 16 -#define BIT_MASK_PS_TIMER_C_TSF_SEL 0x7 -#define BIT_PS_TIMER_C_TSF_SEL(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL) -#define BIT_GET_PS_TIMER_C_TSF_SEL(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ -#define BIT_PS_TIMER_B_EN BIT(15) +#define BIT_CLI2_PWRBIT_OW_EN BIT(5) -#define BIT_SHIFT_PS_TIMER_B_TSF_SEL 8 -#define BIT_MASK_PS_TIMER_B_TSF_SEL 0x7 -#define BIT_PS_TIMER_B_TSF_SEL(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL) -#define BIT_GET_PS_TIMER_B_TSF_SEL(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL) +#endif -#define BIT_PS_TIMER_A_EN BIT(7) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PS_TIMER_A_TSF_SEL 0 -#define BIT_MASK_PS_TIMER_A_TSF_SEL 0x7 -#define BIT_PS_TIMER_A_TSF_SEL(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL) -#define BIT_GET_PS_TIMER_A_TSF_SEL(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN BIT(5) -/* 2 REG_CPUMGQ_TX_TIMER_EARLY (Offset 0x1514) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY 0 -#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY 0xff -#define BIT_CPUMGQ_TX_TIMER_EARLY(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) -#define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI2_PWR_ST BIT(4) -/* 2 REG_PS_TIMER_A_EARLY (Offset 0x1515) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PS_TIMER_A_EARLY 0 -#define BIT_MASK_PS_TIMER_A_EARLY 0xff -#define BIT_PS_TIMER_A_EARLY(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY) -#define BIT_GET_PS_TIMER_A_EARLY(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI1_PWR_ST_V1 BIT(4) -/* 2 REG_PS_TIMER_B_EARLY (Offset 0x1516) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_PS_TIMER_B_EARLY 0 -#define BIT_MASK_PS_TIMER_B_EARLY 0xff -#define BIT_PS_TIMER_B_EARLY(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY) -#define BIT_GET_PS_TIMER_B_EARLY(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI1_PWRBIT_OW_EN BIT(3) -/* 2 REG_PS_TIMER_C_EARLY (Offset 0x1517) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PS_TIMER_C_EARLY 0 -#define BIT_MASK_PS_TIMER_C_EARLY 0xff -#define BIT_PS_TIMER_C_EARLY(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY) -#define BIT_GET_PS_TIMER_C_EARLY(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_BCN_PSR_RPT2 (Offset 0x1600) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI1_PWR_ST BIT(2) -#define BIT_SHIFT_DTIM_CNT2 24 -#define BIT_MASK_DTIM_CNT2 0xff -#define BIT_DTIM_CNT2(x) (((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2) -#define BIT_GET_DTIM_CNT2(x) (((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DTIM_PERIOD2 16 -#define BIT_MASK_DTIM_PERIOD2 0xff -#define BIT_DTIM_PERIOD2(x) (((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2) -#define BIT_GET_DTIM_PERIOD2(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ -#define BIT_DTIM2 BIT(15) -#define BIT_TIM2 BIT(14) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN BIT(2) -#define BIT_SHIFT_PS_AID_2 0 -#define BIT_MASK_PS_AID_2 0x7ff -#define BIT_PS_AID_2(x) (((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2) -#define BIT_GET_PS_AID_2(x) (((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -/* 2 REG_BCN_PSR_RPT3 (Offset 0x1604) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI0_PWRBIT_OW_EN BIT(1) -#define BIT_SHIFT_DTIM_CNT3 24 -#define BIT_MASK_DTIM_CNT3 0xff -#define BIT_DTIM_CNT3(x) (((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3) -#define BIT_GET_DTIM_CNT3(x) (((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DTIM_PERIOD3 16 -#define BIT_MASK_DTIM_PERIOD3 0xff -#define BIT_DTIM_PERIOD3(x) (((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3) -#define BIT_GET_DTIM_PERIOD3(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ -#define BIT_DTIM3 BIT(15) -#define BIT_TIM3 BIT(14) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN BIT(1) -#define BIT_SHIFT_PS_AID_3 0 -#define BIT_MASK_PS_AID_3 0x7ff -#define BIT_PS_AID_3(x) (((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3) -#define BIT_GET_PS_AID_3(x) (((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -/* 2 REG_BCN_PSR_RPT4 (Offset 0x1608) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI0_PWR_ST BIT(0) -#define BIT_SHIFT_DTIM_CNT4 24 -#define BIT_MASK_DTIM_CNT4 0xff -#define BIT_DTIM_CNT4(x) (((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4) -#define BIT_GET_DTIM_CNT4(x) (((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DTIM_PERIOD4 16 -#define BIT_MASK_DTIM_PERIOD4 0xff -#define BIT_DTIM_PERIOD4(x) (((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4) -#define BIT_GET_DTIM_PERIOD4(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ -#define BIT_DTIM4 BIT(15) -#define BIT_TIM4 BIT(14) +#define BIT_CLI0_PWR_ST_V1 BIT(0) -#define BIT_SHIFT_PS_AID_4 0 -#define BIT_MASK_PS_AID_4 0x7ff -#define BIT_PS_AID_4(x) (((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4) -#define BIT_GET_PS_AID_4(x) (((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_A1_ADDR_MASK (Offset 0x160C) */ +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ +#define BIT_WMAC_EXT_DBG_SEL_V1 BIT(6) +#define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA BIT(4) -#define BIT_SHIFT_A1_ADDR_MASK 0 -#define BIT_MASK_A1_ADDR_MASK 0xffffffffL -#define BIT_A1_ADDR_MASK(x) (((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK) -#define BIT_GET_A1_ADDR_MASK(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_MACID2 (Offset 0x1620) */ +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ +#define BIT_PATTERN_MATCH_FIX_EN BIT(3) -#define BIT_SHIFT_MACID2 0 -#define BIT_MASK_MACID2 0xffffffffffffL -#define BIT_MACID2(x) (((x) & BIT_MASK_MACID2) << BIT_SHIFT_MACID2) -#define BIT_GET_MACID2(x) (((x) >> BIT_SHIFT_MACID2) & BIT_MASK_MACID2) +#endif +#if (HALMAC_8822C_SUPPORT) -/* 2 REG_BSSID2 (Offset 0x1628) */ +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ +#define BIT_RX_DMA_BYPASS_CHECK_MGTBIT_RX_DMA_BYPASS_CHECK_MGT BIT(3) -#define BIT_SHIFT_BSSID2 0 -#define BIT_MASK_BSSID2 0xffffffffffffL -#define BIT_BSSID2(x) (((x) & BIT_MASK_BSSID2) << BIT_SHIFT_BSSID2) -#define BIT_GET_BSSID2(x) (((x) >> BIT_SHIFT_BSSID2) & BIT_MASK_BSSID2) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_MACID3 (Offset 0x1630) */ +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ +#define BIT_TXSERV_FIELD_SEL BIT(2) +#define BIT_RXVHT_LEN_SEL BIT(1) +#define BIT_RXMIC_PROTECT_EN BIT(0) -#define BIT_SHIFT_MACID3 0 -#define BIT_MASK_MACID3 0xffffffffffffL -#define BIT_MACID3(x) (((x) & BIT_MASK_MACID3) << BIT_SHIFT_MACID3) -#define BIT_GET_MACID3(x) (((x) >> BIT_SHIFT_MACID3) & BIT_MASK_MACID3) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_BSSID3 (Offset 0x1638) */ +/* 2 REG_FWPHYFF_RCR (Offset 0x1668) */ +#define BIT_RCR2_AAMSDU BIT(25) +#define BIT_RCR2_CBSSID_BCN BIT(24) +#define BIT_RCR2_ACRC32 BIT(23) +#define BIT_RCR2_TA_BCN BIT(22) +#define BIT_RCR2_CBSSID_DATA BIT(21) +#define BIT_RCR2_ADD3 BIT(20) +#define BIT_RCR2_AB BIT(19) +#define BIT_RCR2_AM BIT(18) +#define BIT_RCR2_APM BIT(17) +#define BIT_RCR2_AAP BIT(16) +#define BIT_RCR1_AAMSDU BIT(9) +#define BIT_RCR1_CBSSID_BCN BIT(8) +#define BIT_RCR1_ACRC32 BIT(7) +#define BIT_RCR1_TA_BCN BIT(6) +#define BIT_RCR1_CBSSID_DATA BIT(5) +#define BIT_RCR1_ADD3 BIT(4) +#define BIT_RCR1_AB BIT(3) +#define BIT_RCR1_AM BIT(2) +#define BIT_RCR1_APM BIT(1) +#define BIT_RCR1_AAP BIT(0) -#define BIT_SHIFT_BSSID3 0 -#define BIT_MASK_BSSID3 0xffffffffffffL -#define BIT_BSSID3(x) (((x) & BIT_MASK_BSSID3) << BIT_SHIFT_BSSID3) -#define BIT_GET_BSSID3(x) (((x) >> BIT_SHIFT_BSSID3) & BIT_MASK_BSSID3) +/* 2 REG_ADDRCAM_WRITE_CONTENT (Offset 0x166C) */ +#define BIT_SHIFT_ADDRCAM_WDATA 0 +#define BIT_MASK_ADDRCAM_WDATA 0xffffffffL +#define BIT_ADDRCAM_WDATA(x) \ + (((x) & BIT_MASK_ADDRCAM_WDATA) << BIT_SHIFT_ADDRCAM_WDATA) +#define BITS_ADDRCAM_WDATA (BIT_MASK_ADDRCAM_WDATA << BIT_SHIFT_ADDRCAM_WDATA) +#define BIT_CLEAR_ADDRCAM_WDATA(x) ((x) & (~BITS_ADDRCAM_WDATA)) +#define BIT_GET_ADDRCAM_WDATA(x) \ + (((x) >> BIT_SHIFT_ADDRCAM_WDATA) & BIT_MASK_ADDRCAM_WDATA) +#define BIT_SET_ADDRCAM_WDATA(x, v) \ + (BIT_CLEAR_ADDRCAM_WDATA(x) | BIT_ADDRCAM_WDATA(v)) -/* 2 REG_MACID4 (Offset 0x1640) */ +/* 2 REG_ADDRCAM_READ_CONTENT (Offset 0x1670) */ +#define BIT_SHIFT_ADDRCAM_RDATA 0 +#define BIT_MASK_ADDRCAM_RDATA 0xffffffffL +#define BIT_ADDRCAM_RDATA(x) \ + (((x) & BIT_MASK_ADDRCAM_RDATA) << BIT_SHIFT_ADDRCAM_RDATA) +#define BITS_ADDRCAM_RDATA (BIT_MASK_ADDRCAM_RDATA << BIT_SHIFT_ADDRCAM_RDATA) +#define BIT_CLEAR_ADDRCAM_RDATA(x) ((x) & (~BITS_ADDRCAM_RDATA)) +#define BIT_GET_ADDRCAM_RDATA(x) \ + (((x) >> BIT_SHIFT_ADDRCAM_RDATA) & BIT_MASK_ADDRCAM_RDATA) +#define BIT_SET_ADDRCAM_RDATA(x, v) \ + (BIT_CLEAR_ADDRCAM_RDATA(x) | BIT_ADDRCAM_RDATA(v)) -#define BIT_SHIFT_MACID4 0 -#define BIT_MASK_MACID4 0xffffffffffffL -#define BIT_MACID4(x) (((x) & BIT_MASK_MACID4) << BIT_SHIFT_MACID4) -#define BIT_GET_MACID4(x) (((x) >> BIT_SHIFT_MACID4) & BIT_MASK_MACID4) +/* 2 REG_ADDRCAM_CFG (Offset 0x1674) */ +#define BIT_ADDRCAM_POLL BIT(31) +#define BIT__ADDRCAM_WT_EN BIT(30) +#define BIT_CLRADDRCAM BIT(29) -/* 2 REG_BSSID4 (Offset 0x1648) */ +#define BIT_SHIFT__ADDRCAM_ADDR 8 +#define BIT_MASK__ADDRCAM_ADDR 0x3ff +#define BIT__ADDRCAM_ADDR(x) \ + (((x) & BIT_MASK__ADDRCAM_ADDR) << BIT_SHIFT__ADDRCAM_ADDR) +#define BITS__ADDRCAM_ADDR (BIT_MASK__ADDRCAM_ADDR << BIT_SHIFT__ADDRCAM_ADDR) +#define BIT_CLEAR__ADDRCAM_ADDR(x) ((x) & (~BITS__ADDRCAM_ADDR)) +#define BIT_GET__ADDRCAM_ADDR(x) \ + (((x) >> BIT_SHIFT__ADDRCAM_ADDR) & BIT_MASK__ADDRCAM_ADDR) +#define BIT_SET__ADDRCAM_ADDR(x, v) \ + (BIT_CLEAR__ADDRCAM_ADDR(x) | BIT__ADDRCAM_ADDR(v)) +#define BIT_SHIFT_ADDRCAM_RANGE 0 +#define BIT_MASK_ADDRCAM_RANGE 0x7f +#define BIT_ADDRCAM_RANGE(x) \ + (((x) & BIT_MASK_ADDRCAM_RANGE) << BIT_SHIFT_ADDRCAM_RANGE) +#define BITS_ADDRCAM_RANGE (BIT_MASK_ADDRCAM_RANGE << BIT_SHIFT_ADDRCAM_RANGE) +#define BIT_CLEAR_ADDRCAM_RANGE(x) ((x) & (~BITS_ADDRCAM_RANGE)) +#define BIT_GET_ADDRCAM_RANGE(x) \ + (((x) >> BIT_SHIFT_ADDRCAM_RANGE) & BIT_MASK_ADDRCAM_RANGE) +#define BIT_SET_ADDRCAM_RANGE(x, v) \ + (BIT_CLEAR_ADDRCAM_RANGE(x) | BIT_ADDRCAM_RANGE(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CSI_RRSR (Offset 0x1678) */ + +#define BIT_CSI_LDPC_EN BIT(29) +#define BIT_CSI_STBC_EN BIT(28) + +#define BIT_SHIFT_CSI_RRSC_BITMAP 4 +#define BIT_MASK_CSI_RRSC_BITMAP 0xffffff +#define BIT_CSI_RRSC_BITMAP(x) \ + (((x) & BIT_MASK_CSI_RRSC_BITMAP) << BIT_SHIFT_CSI_RRSC_BITMAP) +#define BITS_CSI_RRSC_BITMAP \ + (BIT_MASK_CSI_RRSC_BITMAP << BIT_SHIFT_CSI_RRSC_BITMAP) +#define BIT_CLEAR_CSI_RRSC_BITMAP(x) ((x) & (~BITS_CSI_RRSC_BITMAP)) +#define BIT_GET_CSI_RRSC_BITMAP(x) \ + (((x) >> BIT_SHIFT_CSI_RRSC_BITMAP) & BIT_MASK_CSI_RRSC_BITMAP) +#define BIT_SET_CSI_RRSC_BITMAP(x, v) \ + (BIT_CLEAR_CSI_RRSC_BITMAP(x) | BIT_CSI_RRSC_BITMAP(v)) + +#define BIT_SHIFT_OFDM_LEN_TH 0 +#define BIT_MASK_OFDM_LEN_TH 0xf +#define BIT_OFDM_LEN_TH(x) \ + (((x) & BIT_MASK_OFDM_LEN_TH) << BIT_SHIFT_OFDM_LEN_TH) +#define BITS_OFDM_LEN_TH (BIT_MASK_OFDM_LEN_TH << BIT_SHIFT_OFDM_LEN_TH) +#define BIT_CLEAR_OFDM_LEN_TH(x) ((x) & (~BITS_OFDM_LEN_TH)) +#define BIT_GET_OFDM_LEN_TH(x) \ + (((x) >> BIT_SHIFT_OFDM_LEN_TH) & BIT_MASK_OFDM_LEN_TH) +#define BIT_SET_OFDM_LEN_TH(x, v) \ + (BIT_CLEAR_OFDM_LEN_TH(x) | BIT_OFDM_LEN_TH(v)) + +#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE 0 +#define BIT_MASK_WMAC_MULBK_PAGE_SIZE 0xff +#define BIT_WMAC_MULBK_PAGE_SIZE(x) \ + (((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE) \ + << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE) +#define BITS_WMAC_MULBK_PAGE_SIZE \ + (BIT_MASK_WMAC_MULBK_PAGE_SIZE << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE) +#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE(x) ((x) & (~BITS_WMAC_MULBK_PAGE_SIZE)) +#define BIT_GET_WMAC_MULBK_PAGE_SIZE(x) \ + (((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE) & \ + BIT_MASK_WMAC_MULBK_PAGE_SIZE) +#define BIT_SET_WMAC_MULBK_PAGE_SIZE(x, v) \ + (BIT_CLEAR_WMAC_MULBK_PAGE_SIZE(x) | BIT_WMAC_MULBK_PAGE_SIZE(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_BSSID4 0 -#define BIT_MASK_BSSID4 0xffffffffffffL -#define BIT_BSSID4(x) (((x) & BIT_MASK_BSSID4) << BIT_SHIFT_BSSID4) -#define BIT_GET_BSSID4(x) (((x) >> BIT_SHIFT_BSSID4) & BIT_MASK_BSSID4) +/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ +#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MU_BF_OPTION (Offset 0x167C) */ +#define BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) -/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#endif -#define BIT_CLI3_PWRBIT_OW_EN BIT(7) -#define BIT_CLI3_PWR_ST BIT(6) -#define BIT_CLI2_PWRBIT_OW_EN BIT(5) -#define BIT_CLI2_PWR_ST BIT(4) -#define BIT_CLI1_PWRBIT_OW_EN BIT(3) -#define BIT_CLI1_PWR_ST BIT(2) -#define BIT_CLI0_PWRBIT_OW_EN BIT(1) -#define BIT_CLI0_PWR_ST BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ +/* 2 REG_WMAC_PAUSE_BB_CLR_TH (Offset 0x167D) */ -#define BIT_WMAC_RESP_NONSTA1_DIS BIT(7) +#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH 0 +#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH 0xff +#define BIT_WMAC_PAUSE_BB_CLR_TH(x) \ + (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) +#define BITS_WMAC_PAUSE_BB_CLR_TH \ + (BIT_MASK_WMAC_PAUSE_BB_CLR_TH << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x) \ + (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) & \ + BIT_MASK_WMAC_PAUSE_BB_CLR_TH) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH(x, v) \ + (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) | BIT_WMAC_PAUSE_BB_CLR_TH(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_WMAC_MU_ARB (Offset 0x167E) */ -/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ +#define BIT_WMAC_ARB_HW_ADAPT_EN BIT(7) +#define BIT_WMAC_ARB_SW_EN BIT(6) -#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) +#define BIT_SHIFT_WMAC_ARB_SW_STATE 0 +#define BIT_MASK_WMAC_ARB_SW_STATE 0x3f +#define BIT_WMAC_ARB_SW_STATE(x) \ + (((x) & BIT_MASK_WMAC_ARB_SW_STATE) << BIT_SHIFT_WMAC_ARB_SW_STATE) +#define BITS_WMAC_ARB_SW_STATE \ + (BIT_MASK_WMAC_ARB_SW_STATE << BIT_SHIFT_WMAC_ARB_SW_STATE) +#define BIT_CLEAR_WMAC_ARB_SW_STATE(x) ((x) & (~BITS_WMAC_ARB_SW_STATE)) +#define BIT_GET_WMAC_ARB_SW_STATE(x) \ + (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE) & BIT_MASK_WMAC_ARB_SW_STATE) +#define BIT_SET_WMAC_ARB_SW_STATE(x, v) \ + (BIT_CLEAR_WMAC_ARB_SW_STATE(x) | BIT_WMAC_ARB_SW_STATE(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ +#define BIT_NOCHK_BFPOLL_BMP BIT(7) -/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ +#endif -#define BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ +#define BIT_SHIFT_WMAC_MU_DBGSEL 5 +#define BIT_MASK_WMAC_MU_DBGSEL 0x3 +#define BIT_WMAC_MU_DBGSEL(x) \ + (((x) & BIT_MASK_WMAC_MU_DBGSEL) << BIT_SHIFT_WMAC_MU_DBGSEL) +#define BITS_WMAC_MU_DBGSEL \ + (BIT_MASK_WMAC_MU_DBGSEL << BIT_SHIFT_WMAC_MU_DBGSEL) +#define BIT_CLEAR_WMAC_MU_DBGSEL(x) ((x) & (~BITS_WMAC_MU_DBGSEL)) +#define BIT_GET_WMAC_MU_DBGSEL(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL) & BIT_MASK_WMAC_MU_DBGSEL) +#define BIT_SET_WMAC_MU_DBGSEL(x, v) \ + (BIT_CLEAR_WMAC_MU_DBGSEL(x) | BIT_WMAC_MU_DBGSEL(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ +/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ +#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT 0 +#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT 0x1f +#define BIT_WMAC_MU_CPRD_TIMEOUT(x) \ + (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) +#define BITS_WMAC_MU_CPRD_TIMEOUT \ + (BIT_MASK_WMAC_MU_CPRD_TIMEOUT << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) +#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT(x) ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT)) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) & \ + BIT_MASK_WMAC_MU_CPRD_TIMEOUT) +#define BIT_SET_WMAC_MU_CPRD_TIMEOUT(x, v) \ + (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT(x) | BIT_WMAC_MU_CPRD_TIMEOUT(v)) -#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4 -#define BIT_MASK_WMAC_TXMU_ACKPOLICY 0x3 -#define BIT_WMAC_TXMU_ACKPOLICY(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY) -#define BIT_GET_WMAC_TXMU_ACKPOLICY(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY) & BIT_MASK_WMAC_TXMU_ACKPOLICY) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL 1 -#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL 0x7 -#define BIT_WMAC_MU_BFEE_PORT_SEL(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) -#define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) +/* 2 REG_WMAC_MU_BF_CTL (Offset 0x1680) */ -#define BIT_WMAC_MU_BFEE_DIS BIT(0) +#define BIT_WMAC_INVLD_BFPRT_CHK BIT(15) +#define BIT_WMAC_RETXBFRPTSEQ_UPD BIT(14) + +#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL 12 +#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL 0x3 +#define BIT_WMAC_MU_BFRPTSEG_SEL(x) \ + (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) +#define BITS_WMAC_MU_BFRPTSEG_SEL \ + (BIT_MASK_WMAC_MU_BFRPTSEG_SEL << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) & \ + BIT_MASK_WMAC_MU_BFRPTSEG_SEL) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL(x, v) \ + (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) | BIT_WMAC_MU_BFRPTSEG_SEL(v)) + +#define BIT_SHIFT_WMAC_MU_BF_MYAID 0 +#define BIT_MASK_WMAC_MU_BF_MYAID 0xfff +#define BIT_WMAC_MU_BF_MYAID(x) \ + (((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID) +#define BITS_WMAC_MU_BF_MYAID \ + (BIT_MASK_WMAC_MU_BF_MYAID << BIT_SHIFT_WMAC_MU_BF_MYAID) +#define BIT_CLEAR_WMAC_MU_BF_MYAID(x) ((x) & (~BITS_WMAC_MU_BF_MYAID)) +#define BIT_GET_WMAC_MU_BF_MYAID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID) +#define BIT_SET_WMAC_MU_BF_MYAID(x, v) \ + (BIT_CLEAR_WMAC_MU_BF_MYAID(x) | BIT_WMAC_MU_BF_MYAID(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_WMAC_PAUSE_BB_CLR_TH (Offset 0x167D) */ +/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1 13 +#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1 0x7 +#define BIT_BFRPT_PARA_USERID_SEL_V1(x) \ + (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1) \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) +#define BITS_BFRPT_PARA_USERID_SEL_V1 \ + (BIT_MASK_BFRPT_PARA_USERID_SEL_V1 \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x) \ + ((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1)) +#define BIT_GET_BFRPT_PARA_USERID_SEL_V1(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) & \ + BIT_MASK_BFRPT_PARA_USERID_SEL_V1) +#define BIT_SET_BFRPT_PARA_USERID_SEL_V1(x, v) \ + (BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x) | \ + BIT_BFRPT_PARA_USERID_SEL_V1(v)) -#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH 0 -#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH 0xff -#define BIT_WMAC_PAUSE_BB_CLR_TH(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) -#define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) -/* 2 REG_WMAC_MU_ARB (Offset 0x167E) */ +/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ -#define BIT_WMAC_ARB_HW_ADAPT_EN BIT(7) -#define BIT_WMAC_ARB_SW_EN BIT(6) +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL 12 +#define BIT_MASK_BFRPT_PARA_USERID_SEL 0x7 +#define BIT_BFRPT_PARA_USERID_SEL(x) \ + (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL) \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL) +#define BITS_BFRPT_PARA_USERID_SEL \ + (BIT_MASK_BFRPT_PARA_USERID_SEL << BIT_SHIFT_BFRPT_PARA_USERID_SEL) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL(x) ((x) & (~BITS_BFRPT_PARA_USERID_SEL)) +#define BIT_GET_BFRPT_PARA_USERID_SEL(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL) & \ + BIT_MASK_BFRPT_PARA_USERID_SEL) +#define BIT_SET_BFRPT_PARA_USERID_SEL(x, v) \ + (BIT_CLEAR_BFRPT_PARA_USERID_SEL(x) | BIT_BFRPT_PARA_USERID_SEL(v)) -#define BIT_SHIFT_WMAC_ARB_SW_STATE 0 -#define BIT_MASK_WMAC_ARB_SW_STATE 0x3f -#define BIT_WMAC_ARB_SW_STATE(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE) << BIT_SHIFT_WMAC_ARB_SW_STATE) -#define BIT_GET_WMAC_ARB_SW_STATE(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE) & BIT_MASK_WMAC_ARB_SW_STATE) +#endif +#if (HALMAC_8822B_SUPPORT) -/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ +/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ +#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL 12 +#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL 0x7 +#define BIT_BIT_BFRPT_PARA_USERID_SEL(x) \ + (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) \ + << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) +#define BITS_BIT_BFRPT_PARA_USERID_SEL \ + (BIT_MASK_BIT_BFRPT_PARA_USERID_SEL \ + << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) +#define BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL(x) \ + ((x) & (~BITS_BIT_BFRPT_PARA_USERID_SEL)) +#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL(x) \ + (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) & \ + BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) +#define BIT_SET_BIT_BFRPT_PARA_USERID_SEL(x, v) \ + (BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL(x) | \ + BIT_BIT_BFRPT_PARA_USERID_SEL(v)) -#define BIT_SHIFT_WMAC_MU_DBGSEL 5 -#define BIT_MASK_WMAC_MU_DBGSEL 0x3 -#define BIT_WMAC_MU_DBGSEL(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL) << BIT_SHIFT_WMAC_MU_DBGSEL) -#define BIT_GET_WMAC_MU_DBGSEL(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL) & BIT_MASK_WMAC_MU_DBGSEL) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT 0 -#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT 0x1f -#define BIT_WMAC_MU_CPRD_TIMEOUT(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) -#define BIT_GET_WMAC_MU_CPRD_TIMEOUT(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) +/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ +#define BIT_SHIFT_BFRPT_PARA 0 +#define BIT_MASK_BFRPT_PARA 0xfff +#define BIT_BFRPT_PARA(x) (((x) & BIT_MASK_BFRPT_PARA) << BIT_SHIFT_BFRPT_PARA) +#define BITS_BFRPT_PARA (BIT_MASK_BFRPT_PARA << BIT_SHIFT_BFRPT_PARA) +#define BIT_CLEAR_BFRPT_PARA(x) ((x) & (~BITS_BFRPT_PARA)) +#define BIT_GET_BFRPT_PARA(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA) & BIT_MASK_BFRPT_PARA) +#define BIT_SET_BFRPT_PARA(x, v) (BIT_CLEAR_BFRPT_PARA(x) | BIT_BFRPT_PARA(v)) -/* 2 REG_WMAC_MU_BF_CTL (Offset 0x1680) */ +#endif -#define BIT_WMAC_INVLD_BFPRT_CHK BIT(15) -#define BIT_WMAC_RETXBFRPTSEQ_UPD BIT(14) +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL 12 -#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL 0x3 -#define BIT_WMAC_MU_BFRPTSEG_SEL(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) -#define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) +/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ +#define BIT_SHIFT_BFRPT_PARA_V1 0 +#define BIT_MASK_BFRPT_PARA_V1 0x1fff +#define BIT_BFRPT_PARA_V1(x) \ + (((x) & BIT_MASK_BFRPT_PARA_V1) << BIT_SHIFT_BFRPT_PARA_V1) +#define BITS_BFRPT_PARA_V1 (BIT_MASK_BFRPT_PARA_V1 << BIT_SHIFT_BFRPT_PARA_V1) +#define BIT_CLEAR_BFRPT_PARA_V1(x) ((x) & (~BITS_BFRPT_PARA_V1)) +#define BIT_GET_BFRPT_PARA_V1(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_V1) & BIT_MASK_BFRPT_PARA_V1) +#define BIT_SET_BFRPT_PARA_V1(x, v) \ + (BIT_CLEAR_BFRPT_PARA_V1(x) | BIT_BFRPT_PARA_V1(v)) -#define BIT_SHIFT_WMAC_MU_BF_MYAID 0 -#define BIT_MASK_WMAC_MU_BF_MYAID 0xfff -#define BIT_WMAC_MU_BF_MYAID(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID) -#define BIT_GET_WMAC_MU_BF_MYAID(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BFRPT_PARA 0 -#define BIT_MASK_BFRPT_PARA 0xfff -#define BIT_BFRPT_PARA(x) (((x) & BIT_MASK_BFRPT_PARA) << BIT_SHIFT_BFRPT_PARA) -#define BIT_GET_BFRPT_PARA(x) (((x) >> BIT_SHIFT_BFRPT_PARA) & BIT_MASK_BFRPT_PARA) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ +#define BIT_STATUS_BFEE2 BIT(10) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ +#define BIT_WMAC_MU_BFEE2_EN BIT(9) -/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL 12 -#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL 0x7 -#define BIT_BIT_BFRPT_PARA_USERID_SEL(x) (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) -#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL(x) (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ +#define BIT_WMAC_MU_BFEE2_USER_EN BIT(9) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ -#define BIT_STATUS_BFEE2 BIT(10) -#define BIT_WMAC_MU_BFEE2_EN BIT(9) +#define BIT_SHIFT_WMAC_MU_BFEE2_AID 0 +#define BIT_MASK_WMAC_MU_BFEE2_AID 0x1ff +#define BIT_WMAC_MU_BFEE2_AID(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID) +#define BITS_WMAC_MU_BFEE2_AID \ + (BIT_MASK_WMAC_MU_BFEE2_AID << BIT_SHIFT_WMAC_MU_BFEE2_AID) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID(x) ((x) & (~BITS_WMAC_MU_BFEE2_AID)) +#define BIT_GET_WMAC_MU_BFEE2_AID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID) +#define BIT_SET_WMAC_MU_BFEE2_AID(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE2_AID(x) | BIT_WMAC_MU_BFEE2_AID(v)) -#define BIT_SHIFT_WMAC_MU_BFEE2_AID 0 -#define BIT_MASK_WMAC_MU_BFEE2_AID 0x1ff -#define BIT_WMAC_MU_BFEE2_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID) -#define BIT_GET_WMAC_MU_BFEE2_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ +#define BIT_STATUS_BFEE3 BIT(10) -/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ +#endif -#define BIT_STATUS_BFEE3 BIT(10) -#define BIT_WMAC_MU_BFEE3_EN BIT(9) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_MU_BFEE3_AID 0 -#define BIT_MASK_WMAC_MU_BFEE3_AID 0x1ff -#define BIT_WMAC_MU_BFEE3_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID) -#define BIT_GET_WMAC_MU_BFEE3_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ +#define BIT_WMAC_MU_BFEE3_EN BIT(9) -/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4 (Offset 0x1688) */ +#endif -#define BIT_STATUS_BFEE4 BIT(10) -#define BIT_WMAC_MU_BFEE4_EN BIT(9) +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_WMAC_MU_BFEE4_AID 0 -#define BIT_MASK_WMAC_MU_BFEE4_AID 0x1ff -#define BIT_WMAC_MU_BFEE4_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID) -#define BIT_GET_WMAC_MU_BFEE4_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ +#define BIT_WMAC_MU_BFEE3_USER_EN BIT(9) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ -/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ +#define BIT_SHIFT_WMAC_MU_BFEE3_AID 0 +#define BIT_MASK_WMAC_MU_BFEE3_AID 0x1ff +#define BIT_WMAC_MU_BFEE3_AID(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID) +#define BITS_WMAC_MU_BFEE3_AID \ + (BIT_MASK_WMAC_MU_BFEE3_AID << BIT_SHIFT_WMAC_MU_BFEE3_AID) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID(x) ((x) & (~BITS_WMAC_MU_BFEE3_AID)) +#define BIT_GET_WMAC_MU_BFEE3_AID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID) +#define BIT_SET_WMAC_MU_BFEE3_AID(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE3_AID(x) | BIT_WMAC_MU_BFEE3_AID(v)) -#define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55) -#define BIT_R_WMAC_RXRST_DLY BIT(54) -#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53) -#define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52) -#define BIT_STATUS_BFEE5 BIT(10) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4 (Offset 0x1688) */ -#endif +#define BIT_STATUS_BFEE4 BIT(10) +#define BIT_WMAC_MU_BFEE4_EN BIT(9) +#define BIT_SHIFT_WMAC_MU_BFEE4_AID 0 +#define BIT_MASK_WMAC_MU_BFEE4_AID 0x1ff +#define BIT_WMAC_MU_BFEE4_AID(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID) +#define BITS_WMAC_MU_BFEE4_AID \ + (BIT_MASK_WMAC_MU_BFEE4_AID << BIT_SHIFT_WMAC_MU_BFEE4_AID) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID(x) ((x) & (~BITS_WMAC_MU_BFEE4_AID)) +#define BIT_GET_WMAC_MU_BFEE4_AID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID) +#define BIT_SET_WMAC_MU_BFEE4_AID(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE4_AID(x) | BIT_WMAC_MU_BFEE4_AID(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ -#define BIT_BIT_STATUS_BFEE5 BIT(10) +#define BIT_STATUS_BFEE5 BIT(10) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ + +#define BIT_BIT_STATUS_BFEE5 BIT(10) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ -#define BIT_WMAC_MU_BFEE5_EN BIT(9) - -#define BIT_SHIFT_WMAC_MU_BFEE5_AID 0 -#define BIT_MASK_WMAC_MU_BFEE5_AID 0x1ff -#define BIT_WMAC_MU_BFEE5_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID) -#define BIT_GET_WMAC_MU_BFEE5_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID) +#define BIT_WMAC_MU_BFEE5_EN BIT(9) +#define BIT_SHIFT_WMAC_MU_BFEE5_AID 0 +#define BIT_MASK_WMAC_MU_BFEE5_AID 0x1ff +#define BIT_WMAC_MU_BFEE5_AID(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID) +#define BITS_WMAC_MU_BFEE5_AID \ + (BIT_MASK_WMAC_MU_BFEE5_AID << BIT_SHIFT_WMAC_MU_BFEE5_AID) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID(x) ((x) & (~BITS_WMAC_MU_BFEE5_AID)) +#define BIT_GET_WMAC_MU_BFEE5_AID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID) +#define BIT_SET_WMAC_MU_BFEE5_AID(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE5_AID(x) | BIT_WMAC_MU_BFEE5_AID(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6 (Offset 0x168C) */ -#define BIT_STATUS_BFEE6 BIT(10) -#define BIT_WMAC_MU_BFEE6_EN BIT(9) +#define BIT_STATUS_BFEE6 BIT(10) +#define BIT_WMAC_MU_BFEE6_EN BIT(9) -#define BIT_SHIFT_WMAC_MU_BFEE6_AID 0 -#define BIT_MASK_WMAC_MU_BFEE6_AID 0x1ff -#define BIT_WMAC_MU_BFEE6_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID) -#define BIT_GET_WMAC_MU_BFEE6_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID) +#define BIT_SHIFT_WMAC_MU_BFEE6_AID 0 +#define BIT_MASK_WMAC_MU_BFEE6_AID 0x1ff +#define BIT_WMAC_MU_BFEE6_AID(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID) +#define BITS_WMAC_MU_BFEE6_AID \ + (BIT_MASK_WMAC_MU_BFEE6_AID << BIT_SHIFT_WMAC_MU_BFEE6_AID) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID(x) ((x) & (~BITS_WMAC_MU_BFEE6_AID)) +#define BIT_GET_WMAC_MU_BFEE6_AID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID) +#define BIT_SET_WMAC_MU_BFEE6_AID(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE6_AID(x) | BIT_WMAC_MU_BFEE6_AID(v)) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ -#define BIT_BIT_STATUS_BFEE4 BIT(10) -#define BIT_WMAC_MU_BFEE7_EN BIT(9) +#define BIT_BIT_STATUS_BFEE4 BIT(10) -#define BIT_SHIFT_WMAC_MU_BFEE7_AID 0 -#define BIT_MASK_WMAC_MU_BFEE7_AID 0x1ff -#define BIT_WMAC_MU_BFEE7_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID) -#define BIT_GET_WMAC_MU_BFEE7_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_WMAC_BB_STOP_RX_COUNTER (Offset 0x1690) */ +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ + +#define BIT_STATUS_BFEE7 BIT(10) -#define BIT_RST_ALL_COUNTER BIT(31) +#endif -#define BIT_SHIFT_ABORT_RX_VBON_COUNTER 16 -#define BIT_MASK_ABORT_RX_VBON_COUNTER 0xff -#define BIT_ABORT_RX_VBON_COUNTER(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER) << BIT_SHIFT_ABORT_RX_VBON_COUNTER) -#define BIT_GET_ABORT_RX_VBON_COUNTER(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) & BIT_MASK_ABORT_RX_VBON_COUNTER) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ -#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER 8 -#define BIT_MASK_ABORT_RX_RDRDY_COUNTER 0xff -#define BIT_ABORT_RX_RDRDY_COUNTER(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) -#define BIT_GET_ABORT_RX_RDRDY_COUNTER(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) +#define BIT_WMAC_MU_BFEE7_EN BIT(9) +#define BIT_SHIFT_WMAC_MU_BFEE7_AID 0 +#define BIT_MASK_WMAC_MU_BFEE7_AID 0x1ff +#define BIT_WMAC_MU_BFEE7_AID(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID) +#define BITS_WMAC_MU_BFEE7_AID \ + (BIT_MASK_WMAC_MU_BFEE7_AID << BIT_SHIFT_WMAC_MU_BFEE7_AID) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID(x) ((x) & (~BITS_WMAC_MU_BFEE7_AID)) +#define BIT_GET_WMAC_MU_BFEE7_AID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID) +#define BIT_SET_WMAC_MU_BFEE7_AID(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE7_AID(x) | BIT_WMAC_MU_BFEE7_AID(v)) -#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER 0 -#define BIT_MASK_VBON_EARLY_FALLING_COUNTER 0xff -#define BIT_VBON_EARLY_FALLING_COUNTER(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) -#define BIT_GET_VBON_EARLY_FALLING_COUNTER(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) +/* 2 REG_WMAC_BB_STOP_RX_COUNTER (Offset 0x1690) */ +#define BIT_RST_ALL_COUNTER BIT(31) + +#define BIT_SHIFT_ABORT_RX_VBON_COUNTER 16 +#define BIT_MASK_ABORT_RX_VBON_COUNTER 0xff +#define BIT_ABORT_RX_VBON_COUNTER(x) \ + (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER) \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER) +#define BITS_ABORT_RX_VBON_COUNTER \ + (BIT_MASK_ABORT_RX_VBON_COUNTER << BIT_SHIFT_ABORT_RX_VBON_COUNTER) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) ((x) & (~BITS_ABORT_RX_VBON_COUNTER)) +#define BIT_GET_ABORT_RX_VBON_COUNTER(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) & \ + BIT_MASK_ABORT_RX_VBON_COUNTER) +#define BIT_SET_ABORT_RX_VBON_COUNTER(x, v) \ + (BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) | BIT_ABORT_RX_VBON_COUNTER(v)) + +#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER 8 +#define BIT_MASK_ABORT_RX_RDRDY_COUNTER 0xff +#define BIT_ABORT_RX_RDRDY_COUNTER(x) \ + (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) +#define BITS_ABORT_RX_RDRDY_COUNTER \ + (BIT_MASK_ABORT_RX_RDRDY_COUNTER << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x) \ + ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) & \ + BIT_MASK_ABORT_RX_RDRDY_COUNTER) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER(x, v) \ + (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x) | BIT_ABORT_RX_RDRDY_COUNTER(v)) + +#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER 0 +#define BIT_MASK_VBON_EARLY_FALLING_COUNTER 0xff +#define BIT_VBON_EARLY_FALLING_COUNTER(x) \ + (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) +#define BITS_VBON_EARLY_FALLING_COUNTER \ + (BIT_MASK_VBON_EARLY_FALLING_COUNTER \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x) \ + ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER(x) \ + (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) & \ + BIT_MASK_VBON_EARLY_FALLING_COUNTER) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER(x, v) \ + (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x) | \ + BIT_VBON_EARLY_FALLING_COUNTER(v)) /* 2 REG_WMAC_PLCP_MONITOR (Offset 0x1694) */ -#define BIT_WMAC_PLCP_TRX_SEL BIT(31) +#define BIT_WMAC_PLCP_TRX_SEL BIT(31) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL 28 +#define BIT_MASK_WMAC_PLCP_RDSIG_SEL 0x7 +#define BIT_WMAC_PLCP_RDSIG_SEL(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) +#define BITS_WMAC_PLCP_RDSIG_SEL \ + (BIT_MASK_WMAC_PLCP_RDSIG_SEL << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) | BIT_WMAC_PLCP_RDSIG_SEL(v)) + +#define BIT_SHIFT_WMAC_RATE_IDX 24 +#define BIT_MASK_WMAC_RATE_IDX 0xf +#define BIT_WMAC_RATE_IDX(x) \ + (((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX) +#define BITS_WMAC_RATE_IDX (BIT_MASK_WMAC_RATE_IDX << BIT_SHIFT_WMAC_RATE_IDX) +#define BIT_CLEAR_WMAC_RATE_IDX(x) ((x) & (~BITS_WMAC_RATE_IDX)) +#define BIT_GET_WMAC_RATE_IDX(x) \ + (((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX) +#define BIT_SET_WMAC_RATE_IDX(x, v) \ + (BIT_CLEAR_WMAC_RATE_IDX(x) | BIT_WMAC_RATE_IDX(v)) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG 0 +#define BIT_MASK_WMAC_PLCP_RDSIG 0xffffff +#define BIT_WMAC_PLCP_RDSIG(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG) +#define BITS_WMAC_PLCP_RDSIG \ + (BIT_MASK_WMAC_PLCP_RDSIG << BIT_SHIFT_WMAC_PLCP_RDSIG) +#define BIT_CLEAR_WMAC_PLCP_RDSIG(x) ((x) & (~BITS_WMAC_PLCP_RDSIG)) +#define BIT_GET_WMAC_PLCP_RDSIG(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG) +#define BIT_SET_WMAC_PLCP_RDSIG(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG(x) | BIT_WMAC_PLCP_RDSIG(v)) + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL 28 -#define BIT_MASK_WMAC_PLCP_RDSIG_SEL 0x7 -#define BIT_WMAC_PLCP_RDSIG_SEL(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) -#define BIT_GET_WMAC_PLCP_RDSIG_SEL(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) +/* 2 REG_WMAC_PLCP_MONITOR_MUTX (Offset 0x1698) */ +#define BIT_WMAC_MUTX_IDX BIT(24) -#define BIT_SHIFT_WMAC_RATE_IDX 24 -#define BIT_MASK_WMAC_RATE_IDX 0xf -#define BIT_WMAC_RATE_IDX(x) (((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX) -#define BIT_GET_WMAC_RATE_IDX(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_WMAC_PLCP_RDSIG 0 -#define BIT_MASK_WMAC_PLCP_RDSIG 0xffffff -#define BIT_WMAC_PLCP_RDSIG(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG) -#define BIT_GET_WMAC_PLCP_RDSIG(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG) +/* 2 REG_WMAC_DEBUG_PORT (Offset 0x1698) */ +#define BIT_SHIFT_WMAC_DEBUG_PORT 0 +#define BIT_MASK_WMAC_DEBUG_PORT 0xffffffffL +#define BIT_WMAC_DEBUG_PORT(x) \ + (((x) & BIT_MASK_WMAC_DEBUG_PORT) << BIT_SHIFT_WMAC_DEBUG_PORT) +#define BITS_WMAC_DEBUG_PORT \ + (BIT_MASK_WMAC_DEBUG_PORT << BIT_SHIFT_WMAC_DEBUG_PORT) +#define BIT_CLEAR_WMAC_DEBUG_PORT(x) ((x) & (~BITS_WMAC_DEBUG_PORT)) +#define BIT_GET_WMAC_DEBUG_PORT(x) \ + (((x) >> BIT_SHIFT_WMAC_DEBUG_PORT) & BIT_MASK_WMAC_DEBUG_PORT) +#define BIT_SET_WMAC_DEBUG_PORT(x, v) \ + (BIT_CLEAR_WMAC_DEBUG_PORT(x) | BIT_WMAC_DEBUG_PORT(v)) #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_WMAC_CSIDMA_CFG (Offset 0x169C) */ -/* 2 REG_WMAC_PLCP_MONITOR_MUTX (Offset 0x1698) */ +#define BIT_SHIFT_CSI_SEG_SIZE 16 +#define BIT_MASK_CSI_SEG_SIZE 0xfff +#define BIT_CSI_SEG_SIZE(x) \ + (((x) & BIT_MASK_CSI_SEG_SIZE) << BIT_SHIFT_CSI_SEG_SIZE) +#define BITS_CSI_SEG_SIZE (BIT_MASK_CSI_SEG_SIZE << BIT_SHIFT_CSI_SEG_SIZE) +#define BIT_CLEAR_CSI_SEG_SIZE(x) ((x) & (~BITS_CSI_SEG_SIZE)) +#define BIT_GET_CSI_SEG_SIZE(x) \ + (((x) >> BIT_SHIFT_CSI_SEG_SIZE) & BIT_MASK_CSI_SEG_SIZE) +#define BIT_SET_CSI_SEG_SIZE(x, v) \ + (BIT_CLEAR_CSI_SEG_SIZE(x) | BIT_CSI_SEG_SIZE(v)) -#define BIT_WMAC_MUTX_IDX BIT(24) +#define BIT_SHIFT_CSI_START_PAGE 0 +#define BIT_MASK_CSI_START_PAGE 0xfff +#define BIT_CSI_START_PAGE(x) \ + (((x) & BIT_MASK_CSI_START_PAGE) << BIT_SHIFT_CSI_START_PAGE) +#define BITS_CSI_START_PAGE \ + (BIT_MASK_CSI_START_PAGE << BIT_SHIFT_CSI_START_PAGE) +#define BIT_CLEAR_CSI_START_PAGE(x) ((x) & (~BITS_CSI_START_PAGE)) +#define BIT_GET_CSI_START_PAGE(x) \ + (((x) >> BIT_SHIFT_CSI_START_PAGE) & BIT_MASK_CSI_START_PAGE) +#define BIT_SET_CSI_START_PAGE(x, v) \ + (BIT_CLEAR_CSI_START_PAGE(x) | BIT_CSI_START_PAGE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) + +/* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */ + +#define BIT_SHIFT_TA0 0 +#define BIT_MASK_TA0 0xffffffffffffL +#define BIT_TA0(x) (((x) & BIT_MASK_TA0) << BIT_SHIFT_TA0) +#define BITS_TA0 (BIT_MASK_TA0 << BIT_SHIFT_TA0) +#define BIT_CLEAR_TA0(x) ((x) & (~BITS_TA0)) +#define BIT_GET_TA0(x) (((x) >> BIT_SHIFT_TA0) & BIT_MASK_TA0) +#define BIT_SET_TA0(x, v) (BIT_CLEAR_TA0(x) | BIT_TA0(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */ +#define BIT_SHIFT_TA0_V1 0 +#define BIT_MASK_TA0_V1 0xffffffffL +#define BIT_TA0_V1(x) (((x) & BIT_MASK_TA0_V1) << BIT_SHIFT_TA0_V1) +#define BITS_TA0_V1 (BIT_MASK_TA0_V1 << BIT_SHIFT_TA0_V1) +#define BIT_CLEAR_TA0_V1(x) ((x) & (~BITS_TA0_V1)) +#define BIT_GET_TA0_V1(x) (((x) >> BIT_SHIFT_TA0_V1) & BIT_MASK_TA0_V1) +#define BIT_SET_TA0_V1(x, v) (BIT_CLEAR_TA0_V1(x) | BIT_TA0_V1(v)) + +/* 2 REG_TRANSMIT_ADDRSS_0_H (Offset 0x16A4) */ + +#define BIT_SHIFT_TA0_H_V1 0 +#define BIT_MASK_TA0_H_V1 0xffff +#define BIT_TA0_H_V1(x) (((x) & BIT_MASK_TA0_H_V1) << BIT_SHIFT_TA0_H_V1) +#define BITS_TA0_H_V1 (BIT_MASK_TA0_H_V1 << BIT_SHIFT_TA0_H_V1) +#define BIT_CLEAR_TA0_H_V1(x) ((x) & (~BITS_TA0_H_V1)) +#define BIT_GET_TA0_H_V1(x) (((x) >> BIT_SHIFT_TA0_H_V1) & BIT_MASK_TA0_H_V1) +#define BIT_SET_TA0_H_V1(x, v) (BIT_CLEAR_TA0_H_V1(x) | BIT_TA0_H_V1(v)) -#define BIT_SHIFT_TA0 0 -#define BIT_MASK_TA0 0xffffffffffffL -#define BIT_TA0(x) (((x) & BIT_MASK_TA0) << BIT_SHIFT_TA0) -#define BIT_GET_TA0(x) (((x) >> BIT_SHIFT_TA0) & BIT_MASK_TA0) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_1 (Offset 0x16A8) */ +#define BIT_SHIFT_TA1 0 +#define BIT_MASK_TA1 0xffffffffffffL +#define BIT_TA1(x) (((x) & BIT_MASK_TA1) << BIT_SHIFT_TA1) +#define BITS_TA1 (BIT_MASK_TA1 << BIT_SHIFT_TA1) +#define BIT_CLEAR_TA1(x) ((x) & (~BITS_TA1)) +#define BIT_GET_TA1(x) (((x) >> BIT_SHIFT_TA1) & BIT_MASK_TA1) +#define BIT_SET_TA1(x, v) (BIT_CLEAR_TA1(x) | BIT_TA1(v)) -#define BIT_SHIFT_TA1 0 -#define BIT_MASK_TA1 0xffffffffffffL -#define BIT_TA1(x) (((x) & BIT_MASK_TA1) << BIT_SHIFT_TA1) -#define BIT_GET_TA1(x) (((x) >> BIT_SHIFT_TA1) & BIT_MASK_TA1) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TRANSMIT_ADDRSS_2 (Offset 0x16B0) */ +/* 2 REG_TRANSMIT_ADDRSS_1 (Offset 0x16A8) */ +#define BIT_SHIFT_TA1_V1 0 +#define BIT_MASK_TA1_V1 0xffffffffL +#define BIT_TA1_V1(x) (((x) & BIT_MASK_TA1_V1) << BIT_SHIFT_TA1_V1) +#define BITS_TA1_V1 (BIT_MASK_TA1_V1 << BIT_SHIFT_TA1_V1) +#define BIT_CLEAR_TA1_V1(x) ((x) & (~BITS_TA1_V1)) +#define BIT_GET_TA1_V1(x) (((x) >> BIT_SHIFT_TA1_V1) & BIT_MASK_TA1_V1) +#define BIT_SET_TA1_V1(x, v) (BIT_CLEAR_TA1_V1(x) | BIT_TA1_V1(v)) -#define BIT_SHIFT_TA2 0 -#define BIT_MASK_TA2 0xffffffffffffL -#define BIT_TA2(x) (((x) & BIT_MASK_TA2) << BIT_SHIFT_TA2) -#define BIT_GET_TA2(x) (((x) >> BIT_SHIFT_TA2) & BIT_MASK_TA2) +/* 2 REG_TRANSMIT_ADDRSS_1_H (Offset 0x16AC) */ +#define BIT_SHIFT_TA1_H_V1 0 +#define BIT_MASK_TA1_H_V1 0xffff +#define BIT_TA1_H_V1(x) (((x) & BIT_MASK_TA1_H_V1) << BIT_SHIFT_TA1_H_V1) +#define BITS_TA1_H_V1 (BIT_MASK_TA1_H_V1 << BIT_SHIFT_TA1_H_V1) +#define BIT_CLEAR_TA1_H_V1(x) ((x) & (~BITS_TA1_H_V1)) +#define BIT_GET_TA1_H_V1(x) (((x) >> BIT_SHIFT_TA1_H_V1) & BIT_MASK_TA1_H_V1) +#define BIT_SET_TA1_H_V1(x, v) (BIT_CLEAR_TA1_H_V1(x) | BIT_TA1_H_V1(v)) -/* 2 REG_TRANSMIT_ADDRSS_3 (Offset 0x16B8) */ +#define BIT_SHIFT_TA2_V1 0 +#define BIT_MASK_TA2_V1 0xffffffffL +#define BIT_TA2_V1(x) (((x) & BIT_MASK_TA2_V1) << BIT_SHIFT_TA2_V1) +#define BITS_TA2_V1 (BIT_MASK_TA2_V1 << BIT_SHIFT_TA2_V1) +#define BIT_CLEAR_TA2_V1(x) ((x) & (~BITS_TA2_V1)) +#define BIT_GET_TA2_V1(x) (((x) >> BIT_SHIFT_TA2_V1) & BIT_MASK_TA2_V1) +#define BIT_SET_TA2_V1(x, v) (BIT_CLEAR_TA2_V1(x) | BIT_TA2_V1(v)) +#endif -#define BIT_SHIFT_TA3 0 -#define BIT_MASK_TA3 0xffffffffffffL -#define BIT_TA3(x) (((x) & BIT_MASK_TA3) << BIT_SHIFT_TA3) -#define BIT_GET_TA3(x) (((x) >> BIT_SHIFT_TA3) & BIT_MASK_TA3) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TRANSMIT_ADDRSS_2 (Offset 0x16B0) */ -/* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */ +#define BIT_SHIFT_TA2 0 +#define BIT_MASK_TA2 0xffffffffffffL +#define BIT_TA2(x) (((x) & BIT_MASK_TA2) << BIT_SHIFT_TA2) +#define BITS_TA2 (BIT_MASK_TA2 << BIT_SHIFT_TA2) +#define BIT_CLEAR_TA2(x) ((x) & (~BITS_TA2)) +#define BIT_GET_TA2(x) (((x) >> BIT_SHIFT_TA2) & BIT_MASK_TA2) +#define BIT_SET_TA2(x, v) (BIT_CLEAR_TA2(x) | BIT_TA2(v)) +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TA4 0 -#define BIT_MASK_TA4 0xffffffffffffL -#define BIT_TA4(x) (((x) & BIT_MASK_TA4) << BIT_SHIFT_TA4) -#define BIT_GET_TA4(x) (((x) >> BIT_SHIFT_TA4) & BIT_MASK_TA4) +/* 2 REG_TRANSMIT_ADDRSS_2_H (Offset 0x16B4) */ +#define BIT_SHIFT_TA2_H_V1 0 +#define BIT_MASK_TA2_H_V1 0xffff +#define BIT_TA2_H_V1(x) (((x) & BIT_MASK_TA2_H_V1) << BIT_SHIFT_TA2_H_V1) +#define BITS_TA2_H_V1 (BIT_MASK_TA2_H_V1 << BIT_SHIFT_TA2_H_V1) +#define BIT_CLEAR_TA2_H_V1(x) ((x) & (~BITS_TA2_H_V1)) +#define BIT_GET_TA2_H_V1(x) (((x) >> BIT_SHIFT_TA2_H_V1) & BIT_MASK_TA2_H_V1) +#define BIT_SET_TA2_H_V1(x, v) (BIT_CLEAR_TA2_H_V1(x) | BIT_TA2_H_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TRANSMIT_ADDRSS_3 (Offset 0x16B8) */ +#define BIT_SHIFT_TA3 0 +#define BIT_MASK_TA3 0xffffffffffffL +#define BIT_TA3(x) (((x) & BIT_MASK_TA3) << BIT_SHIFT_TA3) +#define BITS_TA3 (BIT_MASK_TA3 << BIT_SHIFT_TA3) +#define BIT_CLEAR_TA3(x) ((x) & (~BITS_TA3)) +#define BIT_GET_TA3(x) (((x) >> BIT_SHIFT_TA3) & BIT_MASK_TA3) +#define BIT_SET_TA3(x, v) (BIT_CLEAR_TA3(x) | BIT_TA3(v)) -/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */ +#endif -#define BIT_LTECOEX_ACCESS_START_V1 BIT(31) -#define BIT_LTECOEX_WRITE_MODE_V1 BIT(30) -#define BIT_LTECOEX_READY_BIT_V1 BIT(29) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WRITE_BYTE_EN_V1 16 -#define BIT_MASK_WRITE_BYTE_EN_V1 0xf -#define BIT_WRITE_BYTE_EN_V1(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1) << BIT_SHIFT_WRITE_BYTE_EN_V1) -#define BIT_GET_WRITE_BYTE_EN_V1(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1) & BIT_MASK_WRITE_BYTE_EN_V1) +/* 2 REG_TRANSMIT_ADDRSS_3_H (Offset 0x16BC) */ +#define BIT_SHIFT_TA3_H_V1 0 +#define BIT_MASK_TA3_H_V1 0xffff +#define BIT_TA3_H_V1(x) (((x) & BIT_MASK_TA3_H_V1) << BIT_SHIFT_TA3_H_V1) +#define BITS_TA3_H_V1 (BIT_MASK_TA3_H_V1 << BIT_SHIFT_TA3_H_V1) +#define BIT_CLEAR_TA3_H_V1(x) ((x) & (~BITS_TA3_H_V1)) +#define BIT_GET_TA3_H_V1(x) (((x) >> BIT_SHIFT_TA3_H_V1) & BIT_MASK_TA3_H_V1) +#define BIT_SET_TA3_H_V1(x, v) (BIT_CLEAR_TA3_H_V1(x) | BIT_TA3_H_V1(v)) -#define BIT_SHIFT_LTECOEX_REG_ADDR_V1 0 -#define BIT_MASK_LTECOEX_REG_ADDR_V1 0xffff -#define BIT_LTECOEX_REG_ADDR_V1(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1) << BIT_SHIFT_LTECOEX_REG_ADDR_V1) -#define BIT_GET_LTECOEX_REG_ADDR_V1(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1) & BIT_MASK_LTECOEX_REG_ADDR_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 (Offset 0x1704) */ +/* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */ + +#define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55) +#define BIT_R_WMAC_RXRST_DLY BIT(54) +#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53) +#define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52) +#define BIT_SHIFT_TA4 0 +#define BIT_MASK_TA4 0xffffffffffffL +#define BIT_TA4(x) (((x) & BIT_MASK_TA4) << BIT_SHIFT_TA4) +#define BITS_TA4 (BIT_MASK_TA4 << BIT_SHIFT_TA4) +#define BIT_CLEAR_TA4(x) ((x) & (~BITS_TA4)) +#define BIT_GET_TA4(x) (((x) >> BIT_SHIFT_TA4) & BIT_MASK_TA4) +#define BIT_SET_TA4(x, v) (BIT_CLEAR_TA4(x) | BIT_TA4(v)) -#define BIT_SHIFT_LTECOEX_W_DATA_V1 0 -#define BIT_MASK_LTECOEX_W_DATA_V1 0xffffffffL -#define BIT_LTECOEX_W_DATA_V1(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1) << BIT_SHIFT_LTECOEX_W_DATA_V1) -#define BIT_GET_LTECOEX_W_DATA_V1(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1) & BIT_MASK_LTECOEX_W_DATA_V1) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 (Offset 0x1708) */ +/* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */ +#define BIT_SHIFT_TA4_V1 0 +#define BIT_MASK_TA4_V1 0xffffffffL +#define BIT_TA4_V1(x) (((x) & BIT_MASK_TA4_V1) << BIT_SHIFT_TA4_V1) +#define BITS_TA4_V1 (BIT_MASK_TA4_V1 << BIT_SHIFT_TA4_V1) +#define BIT_CLEAR_TA4_V1(x) ((x) & (~BITS_TA4_V1)) +#define BIT_GET_TA4_V1(x) (((x) >> BIT_SHIFT_TA4_V1) & BIT_MASK_TA4_V1) +#define BIT_SET_TA4_V1(x, v) (BIT_CLEAR_TA4_V1(x) | BIT_TA4_V1(v)) -#define BIT_SHIFT_LTECOEX_R_DATA_V1 0 -#define BIT_MASK_LTECOEX_R_DATA_V1 0xffffffffL -#define BIT_LTECOEX_R_DATA_V1(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1) << BIT_SHIFT_LTECOEX_R_DATA_V1) -#define BIT_GET_LTECOEX_R_DATA_V1(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1) & BIT_MASK_LTECOEX_R_DATA_V1) +/* 2 REG_TRANSMIT_ADDRSS_4_H (Offset 0x16C4) */ +#define BIT_SHIFT_TA4_H_V1 0 +#define BIT_MASK_TA4_H_V1 0xffff +#define BIT_TA4_H_V1(x) (((x) & BIT_MASK_TA4_H_V1) << BIT_SHIFT_TA4_H_V1) +#define BITS_TA4_H_V1 (BIT_MASK_TA4_H_V1 << BIT_SHIFT_TA4_H_V1) +#define BIT_CLEAR_TA4_H_V1(x) ((x) & (~BITS_TA4_H_V1)) +#define BIT_GET_TA4_H_V1(x) (((x) >> BIT_SHIFT_TA4_H_V1) & BIT_MASK_TA4_H_V1) +#define BIT_SET_TA4_H_V1(x, v) (BIT_CLEAR_TA4_H_V1(x) | BIT_TA4_H_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */ + +#define BIT_LTECOEX_ACCESS_START_V1 BIT(31) +#define BIT_LTECOEX_WRITE_MODE_V1 BIT(30) +#define BIT_LTECOEX_READY_BIT_V1 BIT(29) + +#define BIT_SHIFT_WRITE_BYTE_EN_V1 16 +#define BIT_MASK_WRITE_BYTE_EN_V1 0xf +#define BIT_WRITE_BYTE_EN_V1(x) \ + (((x) & BIT_MASK_WRITE_BYTE_EN_V1) << BIT_SHIFT_WRITE_BYTE_EN_V1) +#define BITS_WRITE_BYTE_EN_V1 \ + (BIT_MASK_WRITE_BYTE_EN_V1 << BIT_SHIFT_WRITE_BYTE_EN_V1) +#define BIT_CLEAR_WRITE_BYTE_EN_V1(x) ((x) & (~BITS_WRITE_BYTE_EN_V1)) +#define BIT_GET_WRITE_BYTE_EN_V1(x) \ + (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1) & BIT_MASK_WRITE_BYTE_EN_V1) +#define BIT_SET_WRITE_BYTE_EN_V1(x, v) \ + (BIT_CLEAR_WRITE_BYTE_EN_V1(x) | BIT_WRITE_BYTE_EN_V1(v)) + +#define BIT_SHIFT_LTECOEX_REG_ADDR_V1 0 +#define BIT_MASK_LTECOEX_REG_ADDR_V1 0xffff +#define BIT_LTECOEX_REG_ADDR_V1(x) \ + (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1) << BIT_SHIFT_LTECOEX_REG_ADDR_V1) +#define BITS_LTECOEX_REG_ADDR_V1 \ + (BIT_MASK_LTECOEX_REG_ADDR_V1 << BIT_SHIFT_LTECOEX_REG_ADDR_V1) +#define BIT_CLEAR_LTECOEX_REG_ADDR_V1(x) ((x) & (~BITS_LTECOEX_REG_ADDR_V1)) +#define BIT_GET_LTECOEX_REG_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1) & BIT_MASK_LTECOEX_REG_ADDR_V1) +#define BIT_SET_LTECOEX_REG_ADDR_V1(x, v) \ + (BIT_CLEAR_LTECOEX_REG_ADDR_V1(x) | BIT_LTECOEX_REG_ADDR_V1(v)) +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 (Offset 0x1704) */ + +#define BIT_SHIFT_LTECOEX_W_DATA_V1 0 +#define BIT_MASK_LTECOEX_W_DATA_V1 0xffffffffL +#define BIT_LTECOEX_W_DATA_V1(x) \ + (((x) & BIT_MASK_LTECOEX_W_DATA_V1) << BIT_SHIFT_LTECOEX_W_DATA_V1) +#define BITS_LTECOEX_W_DATA_V1 \ + (BIT_MASK_LTECOEX_W_DATA_V1 << BIT_SHIFT_LTECOEX_W_DATA_V1) +#define BIT_CLEAR_LTECOEX_W_DATA_V1(x) ((x) & (~BITS_LTECOEX_W_DATA_V1)) +#define BIT_GET_LTECOEX_W_DATA_V1(x) \ + (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1) & BIT_MASK_LTECOEX_W_DATA_V1) +#define BIT_SET_LTECOEX_W_DATA_V1(x, v) \ + (BIT_CLEAR_LTECOEX_W_DATA_V1(x) | BIT_LTECOEX_W_DATA_V1(v)) + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 (Offset 0x1708) */ -#endif/* __RTL_WLAN_BITDEF_H__ */ +#define BIT_SHIFT_LTECOEX_R_DATA_V1 0 +#define BIT_MASK_LTECOEX_R_DATA_V1 0xffffffffL +#define BIT_LTECOEX_R_DATA_V1(x) \ + (((x) & BIT_MASK_LTECOEX_R_DATA_V1) << BIT_SHIFT_LTECOEX_R_DATA_V1) +#define BITS_LTECOEX_R_DATA_V1 \ + (BIT_MASK_LTECOEX_R_DATA_V1 << BIT_SHIFT_LTECOEX_R_DATA_V1) +#define BIT_CLEAR_LTECOEX_R_DATA_V1(x) ((x) & (~BITS_LTECOEX_R_DATA_V1)) +#define BIT_GET_LTECOEX_R_DATA_V1(x) \ + (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1) & BIT_MASK_LTECOEX_R_DATA_V1) +#define BIT_SET_LTECOEX_R_DATA_V1(x, v) \ + (BIT_CLEAR_LTECOEX_R_DATA_V1(x) | BIT_LTECOEX_R_DATA_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DMA_RQPN_INFO_0 (Offset 0x2200) */ + +#define BIT_SHIFT_CH0_AVAL_PG 16 +#define BIT_MASK_CH0_AVAL_PG 0xfff +#define BIT_CH0_AVAL_PG(x) \ + (((x) & BIT_MASK_CH0_AVAL_PG) << BIT_SHIFT_CH0_AVAL_PG) +#define BITS_CH0_AVAL_PG (BIT_MASK_CH0_AVAL_PG << BIT_SHIFT_CH0_AVAL_PG) +#define BIT_CLEAR_CH0_AVAL_PG(x) ((x) & (~BITS_CH0_AVAL_PG)) +#define BIT_GET_CH0_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH0_AVAL_PG) & BIT_MASK_CH0_AVAL_PG) +#define BIT_SET_CH0_AVAL_PG(x, v) \ + (BIT_CLEAR_CH0_AVAL_PG(x) | BIT_CH0_AVAL_PG(v)) + +#define BIT_SHIFT_CH0_RSVD_PG 0 +#define BIT_MASK_CH0_RSVD_PG 0xfff +#define BIT_CH0_RSVD_PG(x) \ + (((x) & BIT_MASK_CH0_RSVD_PG) << BIT_SHIFT_CH0_RSVD_PG) +#define BITS_CH0_RSVD_PG (BIT_MASK_CH0_RSVD_PG << BIT_SHIFT_CH0_RSVD_PG) +#define BIT_CLEAR_CH0_RSVD_PG(x) ((x) & (~BITS_CH0_RSVD_PG)) +#define BIT_GET_CH0_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH0_RSVD_PG) & BIT_MASK_CH0_RSVD_PG) +#define BIT_SET_CH0_RSVD_PG(x, v) \ + (BIT_CLEAR_CH0_RSVD_PG(x) | BIT_CH0_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_1 (Offset 0x2204) */ + +#define BIT_SHIFT_CH1_AVAL_PG 16 +#define BIT_MASK_CH1_AVAL_PG 0xfff +#define BIT_CH1_AVAL_PG(x) \ + (((x) & BIT_MASK_CH1_AVAL_PG) << BIT_SHIFT_CH1_AVAL_PG) +#define BITS_CH1_AVAL_PG (BIT_MASK_CH1_AVAL_PG << BIT_SHIFT_CH1_AVAL_PG) +#define BIT_CLEAR_CH1_AVAL_PG(x) ((x) & (~BITS_CH1_AVAL_PG)) +#define BIT_GET_CH1_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH1_AVAL_PG) & BIT_MASK_CH1_AVAL_PG) +#define BIT_SET_CH1_AVAL_PG(x, v) \ + (BIT_CLEAR_CH1_AVAL_PG(x) | BIT_CH1_AVAL_PG(v)) + +#define BIT_SHIFT_CH1_RSVD_PG 0 +#define BIT_MASK_CH1_RSVD_PG 0xfff +#define BIT_CH1_RSVD_PG(x) \ + (((x) & BIT_MASK_CH1_RSVD_PG) << BIT_SHIFT_CH1_RSVD_PG) +#define BITS_CH1_RSVD_PG (BIT_MASK_CH1_RSVD_PG << BIT_SHIFT_CH1_RSVD_PG) +#define BIT_CLEAR_CH1_RSVD_PG(x) ((x) & (~BITS_CH1_RSVD_PG)) +#define BIT_GET_CH1_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH1_RSVD_PG) & BIT_MASK_CH1_RSVD_PG) +#define BIT_SET_CH1_RSVD_PG(x, v) \ + (BIT_CLEAR_CH1_RSVD_PG(x) | BIT_CH1_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_2 (Offset 0x2208) */ + +#define BIT_SHIFT_CH2_AVAL_PG 16 +#define BIT_MASK_CH2_AVAL_PG 0xfff +#define BIT_CH2_AVAL_PG(x) \ + (((x) & BIT_MASK_CH2_AVAL_PG) << BIT_SHIFT_CH2_AVAL_PG) +#define BITS_CH2_AVAL_PG (BIT_MASK_CH2_AVAL_PG << BIT_SHIFT_CH2_AVAL_PG) +#define BIT_CLEAR_CH2_AVAL_PG(x) ((x) & (~BITS_CH2_AVAL_PG)) +#define BIT_GET_CH2_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH2_AVAL_PG) & BIT_MASK_CH2_AVAL_PG) +#define BIT_SET_CH2_AVAL_PG(x, v) \ + (BIT_CLEAR_CH2_AVAL_PG(x) | BIT_CH2_AVAL_PG(v)) + +#define BIT_SHIFT_CH2_RSVD_PG 0 +#define BIT_MASK_CH2_RSVD_PG 0xfff +#define BIT_CH2_RSVD_PG(x) \ + (((x) & BIT_MASK_CH2_RSVD_PG) << BIT_SHIFT_CH2_RSVD_PG) +#define BITS_CH2_RSVD_PG (BIT_MASK_CH2_RSVD_PG << BIT_SHIFT_CH2_RSVD_PG) +#define BIT_CLEAR_CH2_RSVD_PG(x) ((x) & (~BITS_CH2_RSVD_PG)) +#define BIT_GET_CH2_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH2_RSVD_PG) & BIT_MASK_CH2_RSVD_PG) +#define BIT_SET_CH2_RSVD_PG(x, v) \ + (BIT_CLEAR_CH2_RSVD_PG(x) | BIT_CH2_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_3 (Offset 0x220C) */ + +#define BIT_SHIFT_CH3_AVAL_PG 16 +#define BIT_MASK_CH3_AVAL_PG 0xfff +#define BIT_CH3_AVAL_PG(x) \ + (((x) & BIT_MASK_CH3_AVAL_PG) << BIT_SHIFT_CH3_AVAL_PG) +#define BITS_CH3_AVAL_PG (BIT_MASK_CH3_AVAL_PG << BIT_SHIFT_CH3_AVAL_PG) +#define BIT_CLEAR_CH3_AVAL_PG(x) ((x) & (~BITS_CH3_AVAL_PG)) +#define BIT_GET_CH3_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH3_AVAL_PG) & BIT_MASK_CH3_AVAL_PG) +#define BIT_SET_CH3_AVAL_PG(x, v) \ + (BIT_CLEAR_CH3_AVAL_PG(x) | BIT_CH3_AVAL_PG(v)) + +#define BIT_SHIFT_CH3_RSVD_PG 0 +#define BIT_MASK_CH3_RSVD_PG 0xfff +#define BIT_CH3_RSVD_PG(x) \ + (((x) & BIT_MASK_CH3_RSVD_PG) << BIT_SHIFT_CH3_RSVD_PG) +#define BITS_CH3_RSVD_PG (BIT_MASK_CH3_RSVD_PG << BIT_SHIFT_CH3_RSVD_PG) +#define BIT_CLEAR_CH3_RSVD_PG(x) ((x) & (~BITS_CH3_RSVD_PG)) +#define BIT_GET_CH3_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH3_RSVD_PG) & BIT_MASK_CH3_RSVD_PG) +#define BIT_SET_CH3_RSVD_PG(x, v) \ + (BIT_CLEAR_CH3_RSVD_PG(x) | BIT_CH3_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_4 (Offset 0x2210) */ + +#define BIT_SHIFT_CH4_AVAL_PG 16 +#define BIT_MASK_CH4_AVAL_PG 0xfff +#define BIT_CH4_AVAL_PG(x) \ + (((x) & BIT_MASK_CH4_AVAL_PG) << BIT_SHIFT_CH4_AVAL_PG) +#define BITS_CH4_AVAL_PG (BIT_MASK_CH4_AVAL_PG << BIT_SHIFT_CH4_AVAL_PG) +#define BIT_CLEAR_CH4_AVAL_PG(x) ((x) & (~BITS_CH4_AVAL_PG)) +#define BIT_GET_CH4_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH4_AVAL_PG) & BIT_MASK_CH4_AVAL_PG) +#define BIT_SET_CH4_AVAL_PG(x, v) \ + (BIT_CLEAR_CH4_AVAL_PG(x) | BIT_CH4_AVAL_PG(v)) + +#define BIT_SHIFT_CH4_RSVD_PG 0 +#define BIT_MASK_CH4_RSVD_PG 0xfff +#define BIT_CH4_RSVD_PG(x) \ + (((x) & BIT_MASK_CH4_RSVD_PG) << BIT_SHIFT_CH4_RSVD_PG) +#define BITS_CH4_RSVD_PG (BIT_MASK_CH4_RSVD_PG << BIT_SHIFT_CH4_RSVD_PG) +#define BIT_CLEAR_CH4_RSVD_PG(x) ((x) & (~BITS_CH4_RSVD_PG)) +#define BIT_GET_CH4_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH4_RSVD_PG) & BIT_MASK_CH4_RSVD_PG) +#define BIT_SET_CH4_RSVD_PG(x, v) \ + (BIT_CLEAR_CH4_RSVD_PG(x) | BIT_CH4_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_5 (Offset 0x2214) */ + +#define BIT_SHIFT_CH5_AVAL_PG 16 +#define BIT_MASK_CH5_AVAL_PG 0xfff +#define BIT_CH5_AVAL_PG(x) \ + (((x) & BIT_MASK_CH5_AVAL_PG) << BIT_SHIFT_CH5_AVAL_PG) +#define BITS_CH5_AVAL_PG (BIT_MASK_CH5_AVAL_PG << BIT_SHIFT_CH5_AVAL_PG) +#define BIT_CLEAR_CH5_AVAL_PG(x) ((x) & (~BITS_CH5_AVAL_PG)) +#define BIT_GET_CH5_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH5_AVAL_PG) & BIT_MASK_CH5_AVAL_PG) +#define BIT_SET_CH5_AVAL_PG(x, v) \ + (BIT_CLEAR_CH5_AVAL_PG(x) | BIT_CH5_AVAL_PG(v)) + +#define BIT_SHIFT_CH5_RSVD_PG 0 +#define BIT_MASK_CH5_RSVD_PG 0xfff +#define BIT_CH5_RSVD_PG(x) \ + (((x) & BIT_MASK_CH5_RSVD_PG) << BIT_SHIFT_CH5_RSVD_PG) +#define BITS_CH5_RSVD_PG (BIT_MASK_CH5_RSVD_PG << BIT_SHIFT_CH5_RSVD_PG) +#define BIT_CLEAR_CH5_RSVD_PG(x) ((x) & (~BITS_CH5_RSVD_PG)) +#define BIT_GET_CH5_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH5_RSVD_PG) & BIT_MASK_CH5_RSVD_PG) +#define BIT_SET_CH5_RSVD_PG(x, v) \ + (BIT_CLEAR_CH5_RSVD_PG(x) | BIT_CH5_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_6 (Offset 0x2218) */ + +#define BIT_SHIFT_CH6_AVAL_PG 16 +#define BIT_MASK_CH6_AVAL_PG 0xfff +#define BIT_CH6_AVAL_PG(x) \ + (((x) & BIT_MASK_CH6_AVAL_PG) << BIT_SHIFT_CH6_AVAL_PG) +#define BITS_CH6_AVAL_PG (BIT_MASK_CH6_AVAL_PG << BIT_SHIFT_CH6_AVAL_PG) +#define BIT_CLEAR_CH6_AVAL_PG(x) ((x) & (~BITS_CH6_AVAL_PG)) +#define BIT_GET_CH6_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH6_AVAL_PG) & BIT_MASK_CH6_AVAL_PG) +#define BIT_SET_CH6_AVAL_PG(x, v) \ + (BIT_CLEAR_CH6_AVAL_PG(x) | BIT_CH6_AVAL_PG(v)) + +#define BIT_SHIFT_CH6_RSVD_PG 0 +#define BIT_MASK_CH6_RSVD_PG 0xfff +#define BIT_CH6_RSVD_PG(x) \ + (((x) & BIT_MASK_CH6_RSVD_PG) << BIT_SHIFT_CH6_RSVD_PG) +#define BITS_CH6_RSVD_PG (BIT_MASK_CH6_RSVD_PG << BIT_SHIFT_CH6_RSVD_PG) +#define BIT_CLEAR_CH6_RSVD_PG(x) ((x) & (~BITS_CH6_RSVD_PG)) +#define BIT_GET_CH6_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH6_RSVD_PG) & BIT_MASK_CH6_RSVD_PG) +#define BIT_SET_CH6_RSVD_PG(x, v) \ + (BIT_CLEAR_CH6_RSVD_PG(x) | BIT_CH6_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_7 (Offset 0x221C) */ + +#define BIT_SHIFT_CH7_AVAL_PG 16 +#define BIT_MASK_CH7_AVAL_PG 0xfff +#define BIT_CH7_AVAL_PG(x) \ + (((x) & BIT_MASK_CH7_AVAL_PG) << BIT_SHIFT_CH7_AVAL_PG) +#define BITS_CH7_AVAL_PG (BIT_MASK_CH7_AVAL_PG << BIT_SHIFT_CH7_AVAL_PG) +#define BIT_CLEAR_CH7_AVAL_PG(x) ((x) & (~BITS_CH7_AVAL_PG)) +#define BIT_GET_CH7_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH7_AVAL_PG) & BIT_MASK_CH7_AVAL_PG) +#define BIT_SET_CH7_AVAL_PG(x, v) \ + (BIT_CLEAR_CH7_AVAL_PG(x) | BIT_CH7_AVAL_PG(v)) + +#define BIT_SHIFT_CH7_RSVD_PG 0 +#define BIT_MASK_CH7_RSVD_PG 0xfff +#define BIT_CH7_RSVD_PG(x) \ + (((x) & BIT_MASK_CH7_RSVD_PG) << BIT_SHIFT_CH7_RSVD_PG) +#define BITS_CH7_RSVD_PG (BIT_MASK_CH7_RSVD_PG << BIT_SHIFT_CH7_RSVD_PG) +#define BIT_CLEAR_CH7_RSVD_PG(x) ((x) & (~BITS_CH7_RSVD_PG)) +#define BIT_GET_CH7_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH7_RSVD_PG) & BIT_MASK_CH7_RSVD_PG) +#define BIT_SET_CH7_RSVD_PG(x, v) \ + (BIT_CLEAR_CH7_RSVD_PG(x) | BIT_CH7_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_8 (Offset 0x2220) */ + +#define BIT_SHIFT_CH8_AVAL_PG 16 +#define BIT_MASK_CH8_AVAL_PG 0xfff +#define BIT_CH8_AVAL_PG(x) \ + (((x) & BIT_MASK_CH8_AVAL_PG) << BIT_SHIFT_CH8_AVAL_PG) +#define BITS_CH8_AVAL_PG (BIT_MASK_CH8_AVAL_PG << BIT_SHIFT_CH8_AVAL_PG) +#define BIT_CLEAR_CH8_AVAL_PG(x) ((x) & (~BITS_CH8_AVAL_PG)) +#define BIT_GET_CH8_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH8_AVAL_PG) & BIT_MASK_CH8_AVAL_PG) +#define BIT_SET_CH8_AVAL_PG(x, v) \ + (BIT_CLEAR_CH8_AVAL_PG(x) | BIT_CH8_AVAL_PG(v)) + +#define BIT_SHIFT_CH8_RSVD_PG 0 +#define BIT_MASK_CH8_RSVD_PG 0xfff +#define BIT_CH8_RSVD_PG(x) \ + (((x) & BIT_MASK_CH8_RSVD_PG) << BIT_SHIFT_CH8_RSVD_PG) +#define BITS_CH8_RSVD_PG (BIT_MASK_CH8_RSVD_PG << BIT_SHIFT_CH8_RSVD_PG) +#define BIT_CLEAR_CH8_RSVD_PG(x) ((x) & (~BITS_CH8_RSVD_PG)) +#define BIT_GET_CH8_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH8_RSVD_PG) & BIT_MASK_CH8_RSVD_PG) +#define BIT_SET_CH8_RSVD_PG(x, v) \ + (BIT_CLEAR_CH8_RSVD_PG(x) | BIT_CH8_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_9 (Offset 0x2224) */ + +#define BIT_SHIFT_CH9_AVAL_PG 16 +#define BIT_MASK_CH9_AVAL_PG 0xfff +#define BIT_CH9_AVAL_PG(x) \ + (((x) & BIT_MASK_CH9_AVAL_PG) << BIT_SHIFT_CH9_AVAL_PG) +#define BITS_CH9_AVAL_PG (BIT_MASK_CH9_AVAL_PG << BIT_SHIFT_CH9_AVAL_PG) +#define BIT_CLEAR_CH9_AVAL_PG(x) ((x) & (~BITS_CH9_AVAL_PG)) +#define BIT_GET_CH9_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH9_AVAL_PG) & BIT_MASK_CH9_AVAL_PG) +#define BIT_SET_CH9_AVAL_PG(x, v) \ + (BIT_CLEAR_CH9_AVAL_PG(x) | BIT_CH9_AVAL_PG(v)) + +#define BIT_SHIFT_CH9_RSVD_PG 0 +#define BIT_MASK_CH9_RSVD_PG 0xfff +#define BIT_CH9_RSVD_PG(x) \ + (((x) & BIT_MASK_CH9_RSVD_PG) << BIT_SHIFT_CH9_RSVD_PG) +#define BITS_CH9_RSVD_PG (BIT_MASK_CH9_RSVD_PG << BIT_SHIFT_CH9_RSVD_PG) +#define BIT_CLEAR_CH9_RSVD_PG(x) ((x) & (~BITS_CH9_RSVD_PG)) +#define BIT_GET_CH9_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH9_RSVD_PG) & BIT_MASK_CH9_RSVD_PG) +#define BIT_SET_CH9_RSVD_PG(x, v) \ + (BIT_CLEAR_CH9_RSVD_PG(x) | BIT_CH9_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_10 (Offset 0x2228) */ + +#define BIT_SHIFT_CH10_AVAL_PG 16 +#define BIT_MASK_CH10_AVAL_PG 0xfff +#define BIT_CH10_AVAL_PG(x) \ + (((x) & BIT_MASK_CH10_AVAL_PG) << BIT_SHIFT_CH10_AVAL_PG) +#define BITS_CH10_AVAL_PG (BIT_MASK_CH10_AVAL_PG << BIT_SHIFT_CH10_AVAL_PG) +#define BIT_CLEAR_CH10_AVAL_PG(x) ((x) & (~BITS_CH10_AVAL_PG)) +#define BIT_GET_CH10_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH10_AVAL_PG) & BIT_MASK_CH10_AVAL_PG) +#define BIT_SET_CH10_AVAL_PG(x, v) \ + (BIT_CLEAR_CH10_AVAL_PG(x) | BIT_CH10_AVAL_PG(v)) + +#define BIT_SHIFT_CH10_RSVD_PG 0 +#define BIT_MASK_CH10_RSVD_PG 0xfff +#define BIT_CH10_RSVD_PG(x) \ + (((x) & BIT_MASK_CH10_RSVD_PG) << BIT_SHIFT_CH10_RSVD_PG) +#define BITS_CH10_RSVD_PG (BIT_MASK_CH10_RSVD_PG << BIT_SHIFT_CH10_RSVD_PG) +#define BIT_CLEAR_CH10_RSVD_PG(x) ((x) & (~BITS_CH10_RSVD_PG)) +#define BIT_GET_CH10_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH10_RSVD_PG) & BIT_MASK_CH10_RSVD_PG) +#define BIT_SET_CH10_RSVD_PG(x, v) \ + (BIT_CLEAR_CH10_RSVD_PG(x) | BIT_CH10_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_11 (Offset 0x222C) */ + +#define BIT_SHIFT_CH11_AVAL_PG 16 +#define BIT_MASK_CH11_AVAL_PG 0xfff +#define BIT_CH11_AVAL_PG(x) \ + (((x) & BIT_MASK_CH11_AVAL_PG) << BIT_SHIFT_CH11_AVAL_PG) +#define BITS_CH11_AVAL_PG (BIT_MASK_CH11_AVAL_PG << BIT_SHIFT_CH11_AVAL_PG) +#define BIT_CLEAR_CH11_AVAL_PG(x) ((x) & (~BITS_CH11_AVAL_PG)) +#define BIT_GET_CH11_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH11_AVAL_PG) & BIT_MASK_CH11_AVAL_PG) +#define BIT_SET_CH11_AVAL_PG(x, v) \ + (BIT_CLEAR_CH11_AVAL_PG(x) | BIT_CH11_AVAL_PG(v)) + +#define BIT_SHIFT_CH11_RSVD_PG 0 +#define BIT_MASK_CH11_RSVD_PG 0xfff +#define BIT_CH11_RSVD_PG(x) \ + (((x) & BIT_MASK_CH11_RSVD_PG) << BIT_SHIFT_CH11_RSVD_PG) +#define BITS_CH11_RSVD_PG (BIT_MASK_CH11_RSVD_PG << BIT_SHIFT_CH11_RSVD_PG) +#define BIT_CLEAR_CH11_RSVD_PG(x) ((x) & (~BITS_CH11_RSVD_PG)) +#define BIT_GET_CH11_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH11_RSVD_PG) & BIT_MASK_CH11_RSVD_PG) +#define BIT_SET_CH11_RSVD_PG(x, v) \ + (BIT_CLEAR_CH11_RSVD_PG(x) | BIT_CH11_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_12 (Offset 0x2230) */ + +#define BIT_SHIFT_CH12_AVAL_PG 16 +#define BIT_MASK_CH12_AVAL_PG 0xfff +#define BIT_CH12_AVAL_PG(x) \ + (((x) & BIT_MASK_CH12_AVAL_PG) << BIT_SHIFT_CH12_AVAL_PG) +#define BITS_CH12_AVAL_PG (BIT_MASK_CH12_AVAL_PG << BIT_SHIFT_CH12_AVAL_PG) +#define BIT_CLEAR_CH12_AVAL_PG(x) ((x) & (~BITS_CH12_AVAL_PG)) +#define BIT_GET_CH12_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH12_AVAL_PG) & BIT_MASK_CH12_AVAL_PG) +#define BIT_SET_CH12_AVAL_PG(x, v) \ + (BIT_CLEAR_CH12_AVAL_PG(x) | BIT_CH12_AVAL_PG(v)) + +#define BIT_SHIFT_CH12_RSVD_PG 0 +#define BIT_MASK_CH12_RSVD_PG 0xfff +#define BIT_CH12_RSVD_PG(x) \ + (((x) & BIT_MASK_CH12_RSVD_PG) << BIT_SHIFT_CH12_RSVD_PG) +#define BITS_CH12_RSVD_PG (BIT_MASK_CH12_RSVD_PG << BIT_SHIFT_CH12_RSVD_PG) +#define BIT_CLEAR_CH12_RSVD_PG(x) ((x) & (~BITS_CH12_RSVD_PG)) +#define BIT_GET_CH12_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH12_RSVD_PG) & BIT_MASK_CH12_RSVD_PG) +#define BIT_SET_CH12_RSVD_PG(x, v) \ + (BIT_CLEAR_CH12_RSVD_PG(x) | BIT_CH12_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_13 (Offset 0x2234) */ + +#define BIT_SHIFT_CH13_AVAL_PG 16 +#define BIT_MASK_CH13_AVAL_PG 0xfff +#define BIT_CH13_AVAL_PG(x) \ + (((x) & BIT_MASK_CH13_AVAL_PG) << BIT_SHIFT_CH13_AVAL_PG) +#define BITS_CH13_AVAL_PG (BIT_MASK_CH13_AVAL_PG << BIT_SHIFT_CH13_AVAL_PG) +#define BIT_CLEAR_CH13_AVAL_PG(x) ((x) & (~BITS_CH13_AVAL_PG)) +#define BIT_GET_CH13_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH13_AVAL_PG) & BIT_MASK_CH13_AVAL_PG) +#define BIT_SET_CH13_AVAL_PG(x, v) \ + (BIT_CLEAR_CH13_AVAL_PG(x) | BIT_CH13_AVAL_PG(v)) + +#define BIT_SHIFT_CH13_RSVD_PG 0 +#define BIT_MASK_CH13_RSVD_PG 0xfff +#define BIT_CH13_RSVD_PG(x) \ + (((x) & BIT_MASK_CH13_RSVD_PG) << BIT_SHIFT_CH13_RSVD_PG) +#define BITS_CH13_RSVD_PG (BIT_MASK_CH13_RSVD_PG << BIT_SHIFT_CH13_RSVD_PG) +#define BIT_CLEAR_CH13_RSVD_PG(x) ((x) & (~BITS_CH13_RSVD_PG)) +#define BIT_GET_CH13_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH13_RSVD_PG) & BIT_MASK_CH13_RSVD_PG) +#define BIT_SET_CH13_RSVD_PG(x, v) \ + (BIT_CLEAR_CH13_RSVD_PG(x) | BIT_CH13_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_14 (Offset 0x2238) */ + +#define BIT_SHIFT_CH14_AVAL_PG 16 +#define BIT_MASK_CH14_AVAL_PG 0xfff +#define BIT_CH14_AVAL_PG(x) \ + (((x) & BIT_MASK_CH14_AVAL_PG) << BIT_SHIFT_CH14_AVAL_PG) +#define BITS_CH14_AVAL_PG (BIT_MASK_CH14_AVAL_PG << BIT_SHIFT_CH14_AVAL_PG) +#define BIT_CLEAR_CH14_AVAL_PG(x) ((x) & (~BITS_CH14_AVAL_PG)) +#define BIT_GET_CH14_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH14_AVAL_PG) & BIT_MASK_CH14_AVAL_PG) +#define BIT_SET_CH14_AVAL_PG(x, v) \ + (BIT_CLEAR_CH14_AVAL_PG(x) | BIT_CH14_AVAL_PG(v)) + +#define BIT_SHIFT_CH14_RSVD_PG 0 +#define BIT_MASK_CH14_RSVD_PG 0xfff +#define BIT_CH14_RSVD_PG(x) \ + (((x) & BIT_MASK_CH14_RSVD_PG) << BIT_SHIFT_CH14_RSVD_PG) +#define BITS_CH14_RSVD_PG (BIT_MASK_CH14_RSVD_PG << BIT_SHIFT_CH14_RSVD_PG) +#define BIT_CLEAR_CH14_RSVD_PG(x) ((x) & (~BITS_CH14_RSVD_PG)) +#define BIT_GET_CH14_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH14_RSVD_PG) & BIT_MASK_CH14_RSVD_PG) +#define BIT_SET_CH14_RSVD_PG(x, v) \ + (BIT_CLEAR_CH14_RSVD_PG(x) | BIT_CH14_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_15 (Offset 0x223C) */ + +#define BIT_SHIFT_CH15_AVAL_PG 16 +#define BIT_MASK_CH15_AVAL_PG 0xfff +#define BIT_CH15_AVAL_PG(x) \ + (((x) & BIT_MASK_CH15_AVAL_PG) << BIT_SHIFT_CH15_AVAL_PG) +#define BITS_CH15_AVAL_PG (BIT_MASK_CH15_AVAL_PG << BIT_SHIFT_CH15_AVAL_PG) +#define BIT_CLEAR_CH15_AVAL_PG(x) ((x) & (~BITS_CH15_AVAL_PG)) +#define BIT_GET_CH15_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH15_AVAL_PG) & BIT_MASK_CH15_AVAL_PG) +#define BIT_SET_CH15_AVAL_PG(x, v) \ + (BIT_CLEAR_CH15_AVAL_PG(x) | BIT_CH15_AVAL_PG(v)) + +#define BIT_SHIFT_CH15_RSVD_PG 0 +#define BIT_MASK_CH15_RSVD_PG 0xfff +#define BIT_CH15_RSVD_PG(x) \ + (((x) & BIT_MASK_CH15_RSVD_PG) << BIT_SHIFT_CH15_RSVD_PG) +#define BITS_CH15_RSVD_PG (BIT_MASK_CH15_RSVD_PG << BIT_SHIFT_CH15_RSVD_PG) +#define BIT_CLEAR_CH15_RSVD_PG(x) ((x) & (~BITS_CH15_RSVD_PG)) +#define BIT_GET_CH15_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH15_RSVD_PG) & BIT_MASK_CH15_RSVD_PG) +#define BIT_SET_CH15_RSVD_PG(x, v) \ + (BIT_CLEAR_CH15_RSVD_PG(x) | BIT_CH15_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_16 (Offset 0x2240) */ + +#define BIT_SHIFT_CH16_AVAL_PG 16 +#define BIT_MASK_CH16_AVAL_PG 0xfff +#define BIT_CH16_AVAL_PG(x) \ + (((x) & BIT_MASK_CH16_AVAL_PG) << BIT_SHIFT_CH16_AVAL_PG) +#define BITS_CH16_AVAL_PG (BIT_MASK_CH16_AVAL_PG << BIT_SHIFT_CH16_AVAL_PG) +#define BIT_CLEAR_CH16_AVAL_PG(x) ((x) & (~BITS_CH16_AVAL_PG)) +#define BIT_GET_CH16_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH16_AVAL_PG) & BIT_MASK_CH16_AVAL_PG) +#define BIT_SET_CH16_AVAL_PG(x, v) \ + (BIT_CLEAR_CH16_AVAL_PG(x) | BIT_CH16_AVAL_PG(v)) + +#define BIT_SHIFT_CH16_RSVD_PG 0 +#define BIT_MASK_CH16_RSVD_PG 0xfff +#define BIT_CH16_RSVD_PG(x) \ + (((x) & BIT_MASK_CH16_RSVD_PG) << BIT_SHIFT_CH16_RSVD_PG) +#define BITS_CH16_RSVD_PG (BIT_MASK_CH16_RSVD_PG << BIT_SHIFT_CH16_RSVD_PG) +#define BIT_CLEAR_CH16_RSVD_PG(x) ((x) & (~BITS_CH16_RSVD_PG)) +#define BIT_GET_CH16_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH16_RSVD_PG) & BIT_MASK_CH16_RSVD_PG) +#define BIT_SET_CH16_RSVD_PG(x, v) \ + (BIT_CLEAR_CH16_RSVD_PG(x) | BIT_CH16_RSVD_PG(v)) + +/* 2 REG_HWAMSDU_CTL1 (Offset 0x2250) */ + +#define BIT_SHIFT_HWAMSDU_PKTNUM 8 +#define BIT_MASK_HWAMSDU_PKTNUM 0x3f +#define BIT_HWAMSDU_PKTNUM(x) \ + (((x) & BIT_MASK_HWAMSDU_PKTNUM) << BIT_SHIFT_HWAMSDU_PKTNUM) +#define BITS_HWAMSDU_PKTNUM \ + (BIT_MASK_HWAMSDU_PKTNUM << BIT_SHIFT_HWAMSDU_PKTNUM) +#define BIT_CLEAR_HWAMSDU_PKTNUM(x) ((x) & (~BITS_HWAMSDU_PKTNUM)) +#define BIT_GET_HWAMSDU_PKTNUM(x) \ + (((x) >> BIT_SHIFT_HWAMSDU_PKTNUM) & BIT_MASK_HWAMSDU_PKTNUM) +#define BIT_SET_HWAMSDU_PKTNUM(x, v) \ + (BIT_CLEAR_HWAMSDU_PKTNUM(x) | BIT_HWAMSDU_PKTNUM(v)) + +#define BIT_HWAMSDU_BUSY BIT(7) +#define BIT_SINGLE_AMSDU BIT(2) +#define BIT_HWAMSDU_PADDING_MODE BIT(1) +#define BIT_HWAMSDU_EN BIT(0) + +/* 2 REG_HWAMSDU_CTL2 (Offset 0x2254) */ + +#define BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT 16 +#define BIT_MASK_HWAMSDU_AMSDU_TIMEOUT 0xffff +#define BIT_HWAMSDU_AMSDU_TIMEOUT(x) \ + (((x) & BIT_MASK_HWAMSDU_AMSDU_TIMEOUT) \ + << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT) +#define BITS_HWAMSDU_AMSDU_TIMEOUT \ + (BIT_MASK_HWAMSDU_AMSDU_TIMEOUT << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT) +#define BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT(x) ((x) & (~BITS_HWAMSDU_AMSDU_TIMEOUT)) +#define BIT_GET_HWAMSDU_AMSDU_TIMEOUT(x) \ + (((x) >> BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT) & \ + BIT_MASK_HWAMSDU_AMSDU_TIMEOUT) +#define BIT_SET_HWAMSDU_AMSDU_TIMEOUT(x, v) \ + (BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT(x) | BIT_HWAMSDU_AMSDU_TIMEOUT(v)) + +#define BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT 0 +#define BIT_MASK_HWAMSDU_MSDU_TIMEOUT 0xffff +#define BIT_HWAMSDU_MSDU_TIMEOUT(x) \ + (((x) & BIT_MASK_HWAMSDU_MSDU_TIMEOUT) \ + << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT) +#define BITS_HWAMSDU_MSDU_TIMEOUT \ + (BIT_MASK_HWAMSDU_MSDU_TIMEOUT << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT) +#define BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT(x) ((x) & (~BITS_HWAMSDU_MSDU_TIMEOUT)) +#define BIT_GET_HWAMSDU_MSDU_TIMEOUT(x) \ + (((x) >> BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT) & \ + BIT_MASK_HWAMSDU_MSDU_TIMEOUT) +#define BIT_SET_HWAMSDU_MSDU_TIMEOUT(x, v) \ + (BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT(x) | BIT_HWAMSDU_MSDU_TIMEOUT(v)) + +/* 2 REG_HI8Q_TXBD_DESA_L (Offset 0x2300) */ + +#define BIT_SHIFT_HI8Q_TXBD_DESA_L 0 +#define BIT_MASK_HI8Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI8Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI8Q_TXBD_DESA_L) << BIT_SHIFT_HI8Q_TXBD_DESA_L) +#define BITS_HI8Q_TXBD_DESA_L \ + (BIT_MASK_HI8Q_TXBD_DESA_L << BIT_SHIFT_HI8Q_TXBD_DESA_L) +#define BIT_CLEAR_HI8Q_TXBD_DESA_L(x) ((x) & (~BITS_HI8Q_TXBD_DESA_L)) +#define BIT_GET_HI8Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_L) & BIT_MASK_HI8Q_TXBD_DESA_L) +#define BIT_SET_HI8Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI8Q_TXBD_DESA_L(x) | BIT_HI8Q_TXBD_DESA_L(v)) + +/* 2 REG_HI8Q_TXBD_DESA_H (Offset 0x2304) */ + +#define BIT_SHIFT_HI8Q_TXBD_DESA_H 0 +#define BIT_MASK_HI8Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI8Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI8Q_TXBD_DESA_H) << BIT_SHIFT_HI8Q_TXBD_DESA_H) +#define BITS_HI8Q_TXBD_DESA_H \ + (BIT_MASK_HI8Q_TXBD_DESA_H << BIT_SHIFT_HI8Q_TXBD_DESA_H) +#define BIT_CLEAR_HI8Q_TXBD_DESA_H(x) ((x) & (~BITS_HI8Q_TXBD_DESA_H)) +#define BIT_GET_HI8Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_H) & BIT_MASK_HI8Q_TXBD_DESA_H) +#define BIT_SET_HI8Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI8Q_TXBD_DESA_H(x) | BIT_HI8Q_TXBD_DESA_H(v)) + +/* 2 REG_HI9Q_TXBD_DESA_L (Offset 0x2308) */ + +#define BIT_SHIFT_HI9Q_TXBD_DESA_L 0 +#define BIT_MASK_HI9Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI9Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI9Q_TXBD_DESA_L) << BIT_SHIFT_HI9Q_TXBD_DESA_L) +#define BITS_HI9Q_TXBD_DESA_L \ + (BIT_MASK_HI9Q_TXBD_DESA_L << BIT_SHIFT_HI9Q_TXBD_DESA_L) +#define BIT_CLEAR_HI9Q_TXBD_DESA_L(x) ((x) & (~BITS_HI9Q_TXBD_DESA_L)) +#define BIT_GET_HI9Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_L) & BIT_MASK_HI9Q_TXBD_DESA_L) +#define BIT_SET_HI9Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI9Q_TXBD_DESA_L(x) | BIT_HI9Q_TXBD_DESA_L(v)) + +/* 2 REG_HI9Q_TXBD_DESA_H (Offset 0x230C) */ + +#define BIT_SHIFT_HI9Q_TXBD_DESA_H 0 +#define BIT_MASK_HI9Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI9Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI9Q_TXBD_DESA_H) << BIT_SHIFT_HI9Q_TXBD_DESA_H) +#define BITS_HI9Q_TXBD_DESA_H \ + (BIT_MASK_HI9Q_TXBD_DESA_H << BIT_SHIFT_HI9Q_TXBD_DESA_H) +#define BIT_CLEAR_HI9Q_TXBD_DESA_H(x) ((x) & (~BITS_HI9Q_TXBD_DESA_H)) +#define BIT_GET_HI9Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_H) & BIT_MASK_HI9Q_TXBD_DESA_H) +#define BIT_SET_HI9Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI9Q_TXBD_DESA_H(x) | BIT_HI9Q_TXBD_DESA_H(v)) + +/* 2 REG_HI10Q_TXBD_DESA_L (Offset 0x2310) */ + +#define BIT_SHIFT_HI10Q_TXBD_DESA_L 0 +#define BIT_MASK_HI10Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI10Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI10Q_TXBD_DESA_L) << BIT_SHIFT_HI10Q_TXBD_DESA_L) +#define BITS_HI10Q_TXBD_DESA_L \ + (BIT_MASK_HI10Q_TXBD_DESA_L << BIT_SHIFT_HI10Q_TXBD_DESA_L) +#define BIT_CLEAR_HI10Q_TXBD_DESA_L(x) ((x) & (~BITS_HI10Q_TXBD_DESA_L)) +#define BIT_GET_HI10Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_L) & BIT_MASK_HI10Q_TXBD_DESA_L) +#define BIT_SET_HI10Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI10Q_TXBD_DESA_L(x) | BIT_HI10Q_TXBD_DESA_L(v)) + +/* 2 REG_HI10Q_TXBD_DESA_H (Offset 0x2314) */ + +#define BIT_SHIFT_HI10Q_TXBD_DESA_H 0 +#define BIT_MASK_HI10Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI10Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI10Q_TXBD_DESA_H) << BIT_SHIFT_HI10Q_TXBD_DESA_H) +#define BITS_HI10Q_TXBD_DESA_H \ + (BIT_MASK_HI10Q_TXBD_DESA_H << BIT_SHIFT_HI10Q_TXBD_DESA_H) +#define BIT_CLEAR_HI10Q_TXBD_DESA_H(x) ((x) & (~BITS_HI10Q_TXBD_DESA_H)) +#define BIT_GET_HI10Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_H) & BIT_MASK_HI10Q_TXBD_DESA_H) +#define BIT_SET_HI10Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI10Q_TXBD_DESA_H(x) | BIT_HI10Q_TXBD_DESA_H(v)) + +/* 2 REG_HI11Q_TXBD_DESA_L (Offset 0x2318) */ + +#define BIT_SHIFT_HI11Q_TXBD_DESA_L 0 +#define BIT_MASK_HI11Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI11Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI11Q_TXBD_DESA_L) << BIT_SHIFT_HI11Q_TXBD_DESA_L) +#define BITS_HI11Q_TXBD_DESA_L \ + (BIT_MASK_HI11Q_TXBD_DESA_L << BIT_SHIFT_HI11Q_TXBD_DESA_L) +#define BIT_CLEAR_HI11Q_TXBD_DESA_L(x) ((x) & (~BITS_HI11Q_TXBD_DESA_L)) +#define BIT_GET_HI11Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_L) & BIT_MASK_HI11Q_TXBD_DESA_L) +#define BIT_SET_HI11Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI11Q_TXBD_DESA_L(x) | BIT_HI11Q_TXBD_DESA_L(v)) + +/* 2 REG_HI11Q_TXBD_DESA_H (Offset 0x231C) */ + +#define BIT_SHIFT_HI11Q_TXBD_DESA_H 0 +#define BIT_MASK_HI11Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI11Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI11Q_TXBD_DESA_H) << BIT_SHIFT_HI11Q_TXBD_DESA_H) +#define BITS_HI11Q_TXBD_DESA_H \ + (BIT_MASK_HI11Q_TXBD_DESA_H << BIT_SHIFT_HI11Q_TXBD_DESA_H) +#define BIT_CLEAR_HI11Q_TXBD_DESA_H(x) ((x) & (~BITS_HI11Q_TXBD_DESA_H)) +#define BIT_GET_HI11Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_H) & BIT_MASK_HI11Q_TXBD_DESA_H) +#define BIT_SET_HI11Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI11Q_TXBD_DESA_H(x) | BIT_HI11Q_TXBD_DESA_H(v)) + +/* 2 REG_HI12Q_TXBD_DESA_L (Offset 0x2320) */ + +#define BIT_SHIFT_HI12Q_TXBD_DESA_L 0 +#define BIT_MASK_HI12Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI12Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI12Q_TXBD_DESA_L) << BIT_SHIFT_HI12Q_TXBD_DESA_L) +#define BITS_HI12Q_TXBD_DESA_L \ + (BIT_MASK_HI12Q_TXBD_DESA_L << BIT_SHIFT_HI12Q_TXBD_DESA_L) +#define BIT_CLEAR_HI12Q_TXBD_DESA_L(x) ((x) & (~BITS_HI12Q_TXBD_DESA_L)) +#define BIT_GET_HI12Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_L) & BIT_MASK_HI12Q_TXBD_DESA_L) +#define BIT_SET_HI12Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI12Q_TXBD_DESA_L(x) | BIT_HI12Q_TXBD_DESA_L(v)) + +/* 2 REG_HI12Q_TXBD_DESA_H (Offset 0x2324) */ + +#define BIT_SHIFT_HI12Q_TXBD_DESA_H 0 +#define BIT_MASK_HI12Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI12Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI12Q_TXBD_DESA_H) << BIT_SHIFT_HI12Q_TXBD_DESA_H) +#define BITS_HI12Q_TXBD_DESA_H \ + (BIT_MASK_HI12Q_TXBD_DESA_H << BIT_SHIFT_HI12Q_TXBD_DESA_H) +#define BIT_CLEAR_HI12Q_TXBD_DESA_H(x) ((x) & (~BITS_HI12Q_TXBD_DESA_H)) +#define BIT_GET_HI12Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_H) & BIT_MASK_HI12Q_TXBD_DESA_H) +#define BIT_SET_HI12Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI12Q_TXBD_DESA_H(x) | BIT_HI12Q_TXBD_DESA_H(v)) + +/* 2 REG_HI13Q_TXBD_DESA_L (Offset 0x2328) */ + +#define BIT_SHIFT_HI13Q_TXBD_DESA_L 0 +#define BIT_MASK_HI13Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI13Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI13Q_TXBD_DESA_L) << BIT_SHIFT_HI13Q_TXBD_DESA_L) +#define BITS_HI13Q_TXBD_DESA_L \ + (BIT_MASK_HI13Q_TXBD_DESA_L << BIT_SHIFT_HI13Q_TXBD_DESA_L) +#define BIT_CLEAR_HI13Q_TXBD_DESA_L(x) ((x) & (~BITS_HI13Q_TXBD_DESA_L)) +#define BIT_GET_HI13Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_L) & BIT_MASK_HI13Q_TXBD_DESA_L) +#define BIT_SET_HI13Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI13Q_TXBD_DESA_L(x) | BIT_HI13Q_TXBD_DESA_L(v)) + +/* 2 REG_HI13Q_TXBD_DESA_H (Offset 0x232C) */ + +#define BIT_SHIFT_HI13Q_TXBD_DESA_H 0 +#define BIT_MASK_HI13Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI13Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI13Q_TXBD_DESA_H) << BIT_SHIFT_HI13Q_TXBD_DESA_H) +#define BITS_HI13Q_TXBD_DESA_H \ + (BIT_MASK_HI13Q_TXBD_DESA_H << BIT_SHIFT_HI13Q_TXBD_DESA_H) +#define BIT_CLEAR_HI13Q_TXBD_DESA_H(x) ((x) & (~BITS_HI13Q_TXBD_DESA_H)) +#define BIT_GET_HI13Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_H) & BIT_MASK_HI13Q_TXBD_DESA_H) +#define BIT_SET_HI13Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI13Q_TXBD_DESA_H(x) | BIT_HI13Q_TXBD_DESA_H(v)) + +/* 2 REG_HI14Q_TXBD_DESA_L (Offset 0x2330) */ + +#define BIT_SHIFT_HI14Q_TXBD_DESA_L 0 +#define BIT_MASK_HI14Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI14Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI14Q_TXBD_DESA_L) << BIT_SHIFT_HI14Q_TXBD_DESA_L) +#define BITS_HI14Q_TXBD_DESA_L \ + (BIT_MASK_HI14Q_TXBD_DESA_L << BIT_SHIFT_HI14Q_TXBD_DESA_L) +#define BIT_CLEAR_HI14Q_TXBD_DESA_L(x) ((x) & (~BITS_HI14Q_TXBD_DESA_L)) +#define BIT_GET_HI14Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_L) & BIT_MASK_HI14Q_TXBD_DESA_L) +#define BIT_SET_HI14Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI14Q_TXBD_DESA_L(x) | BIT_HI14Q_TXBD_DESA_L(v)) + +/* 2 REG_HI14Q_TXBD_DESA_H (Offset 0x2334) */ + +#define BIT_SHIFT_HI14Q_TXBD_DESA_H 0 +#define BIT_MASK_HI14Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI14Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI14Q_TXBD_DESA_H) << BIT_SHIFT_HI14Q_TXBD_DESA_H) +#define BITS_HI14Q_TXBD_DESA_H \ + (BIT_MASK_HI14Q_TXBD_DESA_H << BIT_SHIFT_HI14Q_TXBD_DESA_H) +#define BIT_CLEAR_HI14Q_TXBD_DESA_H(x) ((x) & (~BITS_HI14Q_TXBD_DESA_H)) +#define BIT_GET_HI14Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_H) & BIT_MASK_HI14Q_TXBD_DESA_H) +#define BIT_SET_HI14Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI14Q_TXBD_DESA_H(x) | BIT_HI14Q_TXBD_DESA_H(v)) + +/* 2 REG_HI15Q_TXBD_DESA_L (Offset 0x2338) */ + +#define BIT_SHIFT_HI15Q_TXBD_DESA_L 0 +#define BIT_MASK_HI15Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI15Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI15Q_TXBD_DESA_L) << BIT_SHIFT_HI15Q_TXBD_DESA_L) +#define BITS_HI15Q_TXBD_DESA_L \ + (BIT_MASK_HI15Q_TXBD_DESA_L << BIT_SHIFT_HI15Q_TXBD_DESA_L) +#define BIT_CLEAR_HI15Q_TXBD_DESA_L(x) ((x) & (~BITS_HI15Q_TXBD_DESA_L)) +#define BIT_GET_HI15Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_L) & BIT_MASK_HI15Q_TXBD_DESA_L) +#define BIT_SET_HI15Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI15Q_TXBD_DESA_L(x) | BIT_HI15Q_TXBD_DESA_L(v)) + +/* 2 REG_HI15Q_TXBD_DESA_H (Offset 0x233C) */ + +#define BIT_SHIFT_HI15Q_TXBD_DESA_H 0 +#define BIT_MASK_HI15Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI15Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI15Q_TXBD_DESA_H) << BIT_SHIFT_HI15Q_TXBD_DESA_H) +#define BITS_HI15Q_TXBD_DESA_H \ + (BIT_MASK_HI15Q_TXBD_DESA_H << BIT_SHIFT_HI15Q_TXBD_DESA_H) +#define BIT_CLEAR_HI15Q_TXBD_DESA_H(x) ((x) & (~BITS_HI15Q_TXBD_DESA_H)) +#define BIT_GET_HI15Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_H) & BIT_MASK_HI15Q_TXBD_DESA_H) +#define BIT_SET_HI15Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI15Q_TXBD_DESA_H(x) | BIT_HI15Q_TXBD_DESA_H(v)) + +/* 2 REG_HI16Q_TXBD_DESA_L (Offset 0x2340) */ + +#define BIT_SHIFT_HI16Q_TXBD_DESA_L 0 +#define BIT_MASK_HI16Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI16Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI16Q_TXBD_DESA_L) << BIT_SHIFT_HI16Q_TXBD_DESA_L) +#define BITS_HI16Q_TXBD_DESA_L \ + (BIT_MASK_HI16Q_TXBD_DESA_L << BIT_SHIFT_HI16Q_TXBD_DESA_L) +#define BIT_CLEAR_HI16Q_TXBD_DESA_L(x) ((x) & (~BITS_HI16Q_TXBD_DESA_L)) +#define BIT_GET_HI16Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_L) & BIT_MASK_HI16Q_TXBD_DESA_L) +#define BIT_SET_HI16Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI16Q_TXBD_DESA_L(x) | BIT_HI16Q_TXBD_DESA_L(v)) + +/* 2 REG_HI16Q_TXBD_DESA_H (Offset 0x2344) */ + +#define BIT_SHIFT_HI16Q_TXBD_DESA_H 0 +#define BIT_MASK_HI16Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI16Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI16Q_TXBD_DESA_H) << BIT_SHIFT_HI16Q_TXBD_DESA_H) +#define BITS_HI16Q_TXBD_DESA_H \ + (BIT_MASK_HI16Q_TXBD_DESA_H << BIT_SHIFT_HI16Q_TXBD_DESA_H) +#define BIT_CLEAR_HI16Q_TXBD_DESA_H(x) ((x) & (~BITS_HI16Q_TXBD_DESA_H)) +#define BIT_GET_HI16Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_H) & BIT_MASK_HI16Q_TXBD_DESA_H) +#define BIT_SET_HI16Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI16Q_TXBD_DESA_H(x) | BIT_HI16Q_TXBD_DESA_H(v)) + +/* 2 REG_HI17Q_TXBD_DESA_L (Offset 0x2348) */ + +#define BIT_SHIFT_HI17Q_TXBD_DESA_L 0 +#define BIT_MASK_HI17Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI17Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI17Q_TXBD_DESA_L) << BIT_SHIFT_HI17Q_TXBD_DESA_L) +#define BITS_HI17Q_TXBD_DESA_L \ + (BIT_MASK_HI17Q_TXBD_DESA_L << BIT_SHIFT_HI17Q_TXBD_DESA_L) +#define BIT_CLEAR_HI17Q_TXBD_DESA_L(x) ((x) & (~BITS_HI17Q_TXBD_DESA_L)) +#define BIT_GET_HI17Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_L) & BIT_MASK_HI17Q_TXBD_DESA_L) +#define BIT_SET_HI17Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI17Q_TXBD_DESA_L(x) | BIT_HI17Q_TXBD_DESA_L(v)) + +/* 2 REG_HI17Q_TXBD_DESA_H (Offset 0x234C) */ + +#define BIT_SHIFT_HI17Q_TXBD_DESA_H 0 +#define BIT_MASK_HI17Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI17Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI17Q_TXBD_DESA_H) << BIT_SHIFT_HI17Q_TXBD_DESA_H) +#define BITS_HI17Q_TXBD_DESA_H \ + (BIT_MASK_HI17Q_TXBD_DESA_H << BIT_SHIFT_HI17Q_TXBD_DESA_H) +#define BIT_CLEAR_HI17Q_TXBD_DESA_H(x) ((x) & (~BITS_HI17Q_TXBD_DESA_H)) +#define BIT_GET_HI17Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_H) & BIT_MASK_HI17Q_TXBD_DESA_H) +#define BIT_SET_HI17Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI17Q_TXBD_DESA_H(x) | BIT_HI17Q_TXBD_DESA_H(v)) + +/* 2 REG_HI18Q_TXBD_DESA_L (Offset 0x2350) */ + +#define BIT_SHIFT_HI18Q_TXBD_DESA_L 0 +#define BIT_MASK_HI18Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI18Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI18Q_TXBD_DESA_L) << BIT_SHIFT_HI18Q_TXBD_DESA_L) +#define BITS_HI18Q_TXBD_DESA_L \ + (BIT_MASK_HI18Q_TXBD_DESA_L << BIT_SHIFT_HI18Q_TXBD_DESA_L) +#define BIT_CLEAR_HI18Q_TXBD_DESA_L(x) ((x) & (~BITS_HI18Q_TXBD_DESA_L)) +#define BIT_GET_HI18Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_L) & BIT_MASK_HI18Q_TXBD_DESA_L) +#define BIT_SET_HI18Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI18Q_TXBD_DESA_L(x) | BIT_HI18Q_TXBD_DESA_L(v)) + +/* 2 REG_HI18Q_TXBD_DESA_H (Offset 0x2354) */ + +#define BIT_SHIFT_HI18Q_TXBD_DESA_H 0 +#define BIT_MASK_HI18Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI18Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI18Q_TXBD_DESA_H) << BIT_SHIFT_HI18Q_TXBD_DESA_H) +#define BITS_HI18Q_TXBD_DESA_H \ + (BIT_MASK_HI18Q_TXBD_DESA_H << BIT_SHIFT_HI18Q_TXBD_DESA_H) +#define BIT_CLEAR_HI18Q_TXBD_DESA_H(x) ((x) & (~BITS_HI18Q_TXBD_DESA_H)) +#define BIT_GET_HI18Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_H) & BIT_MASK_HI18Q_TXBD_DESA_H) +#define BIT_SET_HI18Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI18Q_TXBD_DESA_H(x) | BIT_HI18Q_TXBD_DESA_H(v)) + +/* 2 REG_HI19Q_TXBD_DESA_L (Offset 0x2358) */ + +#define BIT_SHIFT_HI19Q_TXBD_DESA_L 0 +#define BIT_MASK_HI19Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI19Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI19Q_TXBD_DESA_L) << BIT_SHIFT_HI19Q_TXBD_DESA_L) +#define BITS_HI19Q_TXBD_DESA_L \ + (BIT_MASK_HI19Q_TXBD_DESA_L << BIT_SHIFT_HI19Q_TXBD_DESA_L) +#define BIT_CLEAR_HI19Q_TXBD_DESA_L(x) ((x) & (~BITS_HI19Q_TXBD_DESA_L)) +#define BIT_GET_HI19Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_L) & BIT_MASK_HI19Q_TXBD_DESA_L) +#define BIT_SET_HI19Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI19Q_TXBD_DESA_L(x) | BIT_HI19Q_TXBD_DESA_L(v)) + +/* 2 REG_HI19Q_TXBD_DESA_H (Offset 0x235C) */ + +#define BIT_CLR_P0HI19Q_HW_IDX BIT(25) +#define BIT_CLR_P0HI18Q_HW_IDX BIT(24) +#define BIT_CLR_P0HI17Q_HW_IDX BIT(23) +#define BIT_CLR_P0HI16Q_HW_IDX BIT(22) +#define BIT_CLR_P0HI19Q_HOST_IDX BIT(9) +#define BIT_CLR_P0HI18Q_HOST_IDX BIT(8) +#define BIT_CLR_P0HI17Q_HOST_IDX BIT(7) +#define BIT_CLR_P0HI16Q_HOST_IDX BIT(6) + +#define BIT_SHIFT_HI19Q_TXBD_DESA_H 0 +#define BIT_MASK_HI19Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI19Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI19Q_TXBD_DESA_H) << BIT_SHIFT_HI19Q_TXBD_DESA_H) +#define BITS_HI19Q_TXBD_DESA_H \ + (BIT_MASK_HI19Q_TXBD_DESA_H << BIT_SHIFT_HI19Q_TXBD_DESA_H) +#define BIT_CLEAR_HI19Q_TXBD_DESA_H(x) ((x) & (~BITS_HI19Q_TXBD_DESA_H)) +#define BIT_GET_HI19Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_H) & BIT_MASK_HI19Q_TXBD_DESA_H) +#define BIT_SET_HI19Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI19Q_TXBD_DESA_H(x) | BIT_HI19Q_TXBD_DESA_H(v)) + +/* 2 REG_P0HI16Q_TXBD_IDX (Offset 0x2370) */ + +#define BIT_SHIFT_P0HI16Q_HW_IDX 16 +#define BIT_MASK_P0HI16Q_HW_IDX 0xfff +#define BIT_P0HI16Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI16Q_HW_IDX) << BIT_SHIFT_P0HI16Q_HW_IDX) +#define BITS_P0HI16Q_HW_IDX \ + (BIT_MASK_P0HI16Q_HW_IDX << BIT_SHIFT_P0HI16Q_HW_IDX) +#define BIT_CLEAR_P0HI16Q_HW_IDX(x) ((x) & (~BITS_P0HI16Q_HW_IDX)) +#define BIT_GET_P0HI16Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_HW_IDX) & BIT_MASK_P0HI16Q_HW_IDX) +#define BIT_SET_P0HI16Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI16Q_HW_IDX(x) | BIT_P0HI16Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI16Q_HOST_IDX 0 +#define BIT_MASK_P0HI16Q_HOST_IDX 0xfff +#define BIT_P0HI16Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI16Q_HOST_IDX) << BIT_SHIFT_P0HI16Q_HOST_IDX) +#define BITS_P0HI16Q_HOST_IDX \ + (BIT_MASK_P0HI16Q_HOST_IDX << BIT_SHIFT_P0HI16Q_HOST_IDX) +#define BIT_CLEAR_P0HI16Q_HOST_IDX(x) ((x) & (~BITS_P0HI16Q_HOST_IDX)) +#define BIT_GET_P0HI16Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_HOST_IDX) & BIT_MASK_P0HI16Q_HOST_IDX) +#define BIT_SET_P0HI16Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI16Q_HOST_IDX(x) | BIT_P0HI16Q_HOST_IDX(v)) + +/* 2 REG_P0HI17Q_TXBD_IDX (Offset 0x2374) */ + +#define BIT_SHIFT_P0HI17Q_HW_IDX 16 +#define BIT_MASK_P0HI17Q_HW_IDX 0xfff +#define BIT_P0HI17Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI17Q_HW_IDX) << BIT_SHIFT_P0HI17Q_HW_IDX) +#define BITS_P0HI17Q_HW_IDX \ + (BIT_MASK_P0HI17Q_HW_IDX << BIT_SHIFT_P0HI17Q_HW_IDX) +#define BIT_CLEAR_P0HI17Q_HW_IDX(x) ((x) & (~BITS_P0HI17Q_HW_IDX)) +#define BIT_GET_P0HI17Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_HW_IDX) & BIT_MASK_P0HI17Q_HW_IDX) +#define BIT_SET_P0HI17Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI17Q_HW_IDX(x) | BIT_P0HI17Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI17Q_HOST_IDX 0 +#define BIT_MASK_P0HI17Q_HOST_IDX 0xfff +#define BIT_P0HI17Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI17Q_HOST_IDX) << BIT_SHIFT_P0HI17Q_HOST_IDX) +#define BITS_P0HI17Q_HOST_IDX \ + (BIT_MASK_P0HI17Q_HOST_IDX << BIT_SHIFT_P0HI17Q_HOST_IDX) +#define BIT_CLEAR_P0HI17Q_HOST_IDX(x) ((x) & (~BITS_P0HI17Q_HOST_IDX)) +#define BIT_GET_P0HI17Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_HOST_IDX) & BIT_MASK_P0HI17Q_HOST_IDX) +#define BIT_SET_P0HI17Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI17Q_HOST_IDX(x) | BIT_P0HI17Q_HOST_IDX(v)) + +/* 2 REG_P0HI18Q_TXBD_IDX (Offset 0x2378) */ + +#define BIT_SHIFT_P0HI18Q_HW_IDX 16 +#define BIT_MASK_P0HI18Q_HW_IDX 0xfff +#define BIT_P0HI18Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI18Q_HW_IDX) << BIT_SHIFT_P0HI18Q_HW_IDX) +#define BITS_P0HI18Q_HW_IDX \ + (BIT_MASK_P0HI18Q_HW_IDX << BIT_SHIFT_P0HI18Q_HW_IDX) +#define BIT_CLEAR_P0HI18Q_HW_IDX(x) ((x) & (~BITS_P0HI18Q_HW_IDX)) +#define BIT_GET_P0HI18Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_HW_IDX) & BIT_MASK_P0HI18Q_HW_IDX) +#define BIT_SET_P0HI18Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI18Q_HW_IDX(x) | BIT_P0HI18Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI18Q_HOST_IDX 0 +#define BIT_MASK_P0HI18Q_HOST_IDX 0xfff +#define BIT_P0HI18Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI18Q_HOST_IDX) << BIT_SHIFT_P0HI18Q_HOST_IDX) +#define BITS_P0HI18Q_HOST_IDX \ + (BIT_MASK_P0HI18Q_HOST_IDX << BIT_SHIFT_P0HI18Q_HOST_IDX) +#define BIT_CLEAR_P0HI18Q_HOST_IDX(x) ((x) & (~BITS_P0HI18Q_HOST_IDX)) +#define BIT_GET_P0HI18Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_HOST_IDX) & BIT_MASK_P0HI18Q_HOST_IDX) +#define BIT_SET_P0HI18Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI18Q_HOST_IDX(x) | BIT_P0HI18Q_HOST_IDX(v)) + +/* 2 REG_P0HI19Q_TXBD_IDX (Offset 0x237C) */ + +#define BIT_SHIFT_P0HI19Q_HW_IDX 16 +#define BIT_MASK_P0HI19Q_HW_IDX 0xfff +#define BIT_P0HI19Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI19Q_HW_IDX) << BIT_SHIFT_P0HI19Q_HW_IDX) +#define BITS_P0HI19Q_HW_IDX \ + (BIT_MASK_P0HI19Q_HW_IDX << BIT_SHIFT_P0HI19Q_HW_IDX) +#define BIT_CLEAR_P0HI19Q_HW_IDX(x) ((x) & (~BITS_P0HI19Q_HW_IDX)) +#define BIT_GET_P0HI19Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_HW_IDX) & BIT_MASK_P0HI19Q_HW_IDX) +#define BIT_SET_P0HI19Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI19Q_HW_IDX(x) | BIT_P0HI19Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI19Q_HOST_IDX 0 +#define BIT_MASK_P0HI19Q_HOST_IDX 0xfff +#define BIT_P0HI19Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI19Q_HOST_IDX) << BIT_SHIFT_P0HI19Q_HOST_IDX) +#define BITS_P0HI19Q_HOST_IDX \ + (BIT_MASK_P0HI19Q_HOST_IDX << BIT_SHIFT_P0HI19Q_HOST_IDX) +#define BIT_CLEAR_P0HI19Q_HOST_IDX(x) ((x) & (~BITS_P0HI19Q_HOST_IDX)) +#define BIT_GET_P0HI19Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_HOST_IDX) & BIT_MASK_P0HI19Q_HOST_IDX) +#define BIT_SET_P0HI19Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI19Q_HOST_IDX(x) | BIT_P0HI19Q_HOST_IDX(v)) + +/* 2 REG_P0HI16Q_HI17Q_TXBD_NUM (Offset 0x2380) */ + +#define BIT_P0HI17Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI17Q_DESC_MODE 28 +#define BIT_MASK_P0HI17Q_DESC_MODE 0x3 +#define BIT_P0HI17Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI17Q_DESC_MODE) << BIT_SHIFT_P0HI17Q_DESC_MODE) +#define BITS_P0HI17Q_DESC_MODE \ + (BIT_MASK_P0HI17Q_DESC_MODE << BIT_SHIFT_P0HI17Q_DESC_MODE) +#define BIT_CLEAR_P0HI17Q_DESC_MODE(x) ((x) & (~BITS_P0HI17Q_DESC_MODE)) +#define BIT_GET_P0HI17Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_DESC_MODE) & BIT_MASK_P0HI17Q_DESC_MODE) +#define BIT_SET_P0HI17Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI17Q_DESC_MODE(x) | BIT_P0HI17Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI17Q_DESC_NUM 16 +#define BIT_MASK_P0HI17Q_DESC_NUM 0xfff +#define BIT_P0HI17Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI17Q_DESC_NUM) << BIT_SHIFT_P0HI17Q_DESC_NUM) +#define BITS_P0HI17Q_DESC_NUM \ + (BIT_MASK_P0HI17Q_DESC_NUM << BIT_SHIFT_P0HI17Q_DESC_NUM) +#define BIT_CLEAR_P0HI17Q_DESC_NUM(x) ((x) & (~BITS_P0HI17Q_DESC_NUM)) +#define BIT_GET_P0HI17Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_DESC_NUM) & BIT_MASK_P0HI17Q_DESC_NUM) +#define BIT_SET_P0HI17Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI17Q_DESC_NUM(x) | BIT_P0HI17Q_DESC_NUM(v)) + +#define BIT_P0HI16Q_FLAG BIT(14) + +#define BIT_SHIFT_P0HI16Q_DESC_MODE 12 +#define BIT_MASK_P0HI16Q_DESC_MODE 0x3 +#define BIT_P0HI16Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI16Q_DESC_MODE) << BIT_SHIFT_P0HI16Q_DESC_MODE) +#define BITS_P0HI16Q_DESC_MODE \ + (BIT_MASK_P0HI16Q_DESC_MODE << BIT_SHIFT_P0HI16Q_DESC_MODE) +#define BIT_CLEAR_P0HI16Q_DESC_MODE(x) ((x) & (~BITS_P0HI16Q_DESC_MODE)) +#define BIT_GET_P0HI16Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_DESC_MODE) & BIT_MASK_P0HI16Q_DESC_MODE) +#define BIT_SET_P0HI16Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI16Q_DESC_MODE(x) | BIT_P0HI16Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI16Q_DESC_NUM 0 +#define BIT_MASK_P0HI16Q_DESC_NUM 0xfff +#define BIT_P0HI16Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI16Q_DESC_NUM) << BIT_SHIFT_P0HI16Q_DESC_NUM) +#define BITS_P0HI16Q_DESC_NUM \ + (BIT_MASK_P0HI16Q_DESC_NUM << BIT_SHIFT_P0HI16Q_DESC_NUM) +#define BIT_CLEAR_P0HI16Q_DESC_NUM(x) ((x) & (~BITS_P0HI16Q_DESC_NUM)) +#define BIT_GET_P0HI16Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_DESC_NUM) & BIT_MASK_P0HI16Q_DESC_NUM) +#define BIT_SET_P0HI16Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI16Q_DESC_NUM(x) | BIT_P0HI16Q_DESC_NUM(v)) + +/* 2 REG_P0HI18Q_HI19Q_TXBD_NUM (Offset 0x2384) */ + +#define BIT_P0HI19Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI19Q_DESC_MODE 28 +#define BIT_MASK_P0HI19Q_DESC_MODE 0x3 +#define BIT_P0HI19Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI19Q_DESC_MODE) << BIT_SHIFT_P0HI19Q_DESC_MODE) +#define BITS_P0HI19Q_DESC_MODE \ + (BIT_MASK_P0HI19Q_DESC_MODE << BIT_SHIFT_P0HI19Q_DESC_MODE) +#define BIT_CLEAR_P0HI19Q_DESC_MODE(x) ((x) & (~BITS_P0HI19Q_DESC_MODE)) +#define BIT_GET_P0HI19Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_DESC_MODE) & BIT_MASK_P0HI19Q_DESC_MODE) +#define BIT_SET_P0HI19Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI19Q_DESC_MODE(x) | BIT_P0HI19Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI19Q_DESC_NUM 16 +#define BIT_MASK_P0HI19Q_DESC_NUM 0xfff +#define BIT_P0HI19Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI19Q_DESC_NUM) << BIT_SHIFT_P0HI19Q_DESC_NUM) +#define BITS_P0HI19Q_DESC_NUM \ + (BIT_MASK_P0HI19Q_DESC_NUM << BIT_SHIFT_P0HI19Q_DESC_NUM) +#define BIT_CLEAR_P0HI19Q_DESC_NUM(x) ((x) & (~BITS_P0HI19Q_DESC_NUM)) +#define BIT_GET_P0HI19Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_DESC_NUM) & BIT_MASK_P0HI19Q_DESC_NUM) +#define BIT_SET_P0HI19Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI19Q_DESC_NUM(x) | BIT_P0HI19Q_DESC_NUM(v)) + +#define BIT_P0HI18Q_FLAG BIT(14) + +#define BIT_SHIFT_P0HI18Q_DESC_MODE 12 +#define BIT_MASK_P0HI18Q_DESC_MODE 0x3 +#define BIT_P0HI18Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI18Q_DESC_MODE) << BIT_SHIFT_P0HI18Q_DESC_MODE) +#define BITS_P0HI18Q_DESC_MODE \ + (BIT_MASK_P0HI18Q_DESC_MODE << BIT_SHIFT_P0HI18Q_DESC_MODE) +#define BIT_CLEAR_P0HI18Q_DESC_MODE(x) ((x) & (~BITS_P0HI18Q_DESC_MODE)) +#define BIT_GET_P0HI18Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_DESC_MODE) & BIT_MASK_P0HI18Q_DESC_MODE) +#define BIT_SET_P0HI18Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI18Q_DESC_MODE(x) | BIT_P0HI18Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI18Q_DESC_NUM 0 +#define BIT_MASK_P0HI18Q_DESC_NUM 0xfff +#define BIT_P0HI18Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI18Q_DESC_NUM) << BIT_SHIFT_P0HI18Q_DESC_NUM) +#define BITS_P0HI18Q_DESC_NUM \ + (BIT_MASK_P0HI18Q_DESC_NUM << BIT_SHIFT_P0HI18Q_DESC_NUM) +#define BIT_CLEAR_P0HI18Q_DESC_NUM(x) ((x) & (~BITS_P0HI18Q_DESC_NUM)) +#define BIT_GET_P0HI18Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_DESC_NUM) & BIT_MASK_P0HI18Q_DESC_NUM) +#define BIT_SET_P0HI18Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI18Q_DESC_NUM(x) | BIT_P0HI18Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_PCIE_HISR0 (Offset 0x23B4) */ + +#define BIT_PRE_TX_ERR_INT BIT(31) +#define BIT_HISR1_IND BIT(11) +#define BIT_TXDMAOK_CHANNEL15 BIT(7) +#define BIT_TXDMAOK_CHANNEL14 BIT(6) +#define BIT_TXDMAOK_CHANNEL3 BIT(5) +#define BIT_TXDMAOK_CHANNEL2 BIT(4) +#define BIT_TXDMAOK_CHANNEL1 BIT(3) +#define BIT_TXDMAOK_CHANNEL0 BIT(2) + +/* 2 REG_PCIE_HISR1 (Offset 0x23BC) */ + +#define BIT_CPU_MGQ_EARLY_INT BIT(6) +#define BIT_PSTIMER_5 BIT(4) +#define BIT_PSTIMER_4 BIT(3) +#define BIT_PSTIMER_3 BIT(2) +#define BIT_BB_STOPRX_INT BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI8Q_HI9Q_TXBD_NUM (Offset 0x23C0) */ + +#define BIT_P0HI9Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI9Q_DESC_MODE 28 +#define BIT_MASK_P0HI9Q_DESC_MODE 0x3 +#define BIT_P0HI9Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI9Q_DESC_MODE) << BIT_SHIFT_P0HI9Q_DESC_MODE) +#define BITS_P0HI9Q_DESC_MODE \ + (BIT_MASK_P0HI9Q_DESC_MODE << BIT_SHIFT_P0HI9Q_DESC_MODE) +#define BIT_CLEAR_P0HI9Q_DESC_MODE(x) ((x) & (~BITS_P0HI9Q_DESC_MODE)) +#define BIT_GET_P0HI9Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_DESC_MODE) & BIT_MASK_P0HI9Q_DESC_MODE) +#define BIT_SET_P0HI9Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI9Q_DESC_MODE(x) | BIT_P0HI9Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI9Q_DESC_NUM 16 +#define BIT_MASK_P0HI9Q_DESC_NUM 0xfff +#define BIT_P0HI9Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI9Q_DESC_NUM) << BIT_SHIFT_P0HI9Q_DESC_NUM) +#define BITS_P0HI9Q_DESC_NUM \ + (BIT_MASK_P0HI9Q_DESC_NUM << BIT_SHIFT_P0HI9Q_DESC_NUM) +#define BIT_CLEAR_P0HI9Q_DESC_NUM(x) ((x) & (~BITS_P0HI9Q_DESC_NUM)) +#define BIT_GET_P0HI9Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_DESC_NUM) & BIT_MASK_P0HI9Q_DESC_NUM) +#define BIT_SET_P0HI9Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI9Q_DESC_NUM(x) | BIT_P0HI9Q_DESC_NUM(v)) + +#define BIT_P0HI8Q_FLAG BIT(14) + +#define BIT_SHIFT_P0HI8Q_DESC_MODE 12 +#define BIT_MASK_P0HI8Q_DESC_MODE 0x3 +#define BIT_P0HI8Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI8Q_DESC_MODE) << BIT_SHIFT_P0HI8Q_DESC_MODE) +#define BITS_P0HI8Q_DESC_MODE \ + (BIT_MASK_P0HI8Q_DESC_MODE << BIT_SHIFT_P0HI8Q_DESC_MODE) +#define BIT_CLEAR_P0HI8Q_DESC_MODE(x) ((x) & (~BITS_P0HI8Q_DESC_MODE)) +#define BIT_GET_P0HI8Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_DESC_MODE) & BIT_MASK_P0HI8Q_DESC_MODE) +#define BIT_SET_P0HI8Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI8Q_DESC_MODE(x) | BIT_P0HI8Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI8Q_DESC_NUM 0 +#define BIT_MASK_P0HI8Q_DESC_NUM 0xfff +#define BIT_P0HI8Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI8Q_DESC_NUM) << BIT_SHIFT_P0HI8Q_DESC_NUM) +#define BITS_P0HI8Q_DESC_NUM \ + (BIT_MASK_P0HI8Q_DESC_NUM << BIT_SHIFT_P0HI8Q_DESC_NUM) +#define BIT_CLEAR_P0HI8Q_DESC_NUM(x) ((x) & (~BITS_P0HI8Q_DESC_NUM)) +#define BIT_GET_P0HI8Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_DESC_NUM) & BIT_MASK_P0HI8Q_DESC_NUM) +#define BIT_SET_P0HI8Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI8Q_DESC_NUM(x) | BIT_P0HI8Q_DESC_NUM(v)) + +/* 2 REG_P0HI10Q_HI11Q_TXBD_NUM (Offset 0x23C4) */ + +#define BIT_P0HI11Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI11Q_DESC_MODE 28 +#define BIT_MASK_P0HI11Q_DESC_MODE 0x3 +#define BIT_P0HI11Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI11Q_DESC_MODE) << BIT_SHIFT_P0HI11Q_DESC_MODE) +#define BITS_P0HI11Q_DESC_MODE \ + (BIT_MASK_P0HI11Q_DESC_MODE << BIT_SHIFT_P0HI11Q_DESC_MODE) +#define BIT_CLEAR_P0HI11Q_DESC_MODE(x) ((x) & (~BITS_P0HI11Q_DESC_MODE)) +#define BIT_GET_P0HI11Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_DESC_MODE) & BIT_MASK_P0HI11Q_DESC_MODE) +#define BIT_SET_P0HI11Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI11Q_DESC_MODE(x) | BIT_P0HI11Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI11Q_DESC_NUM 16 +#define BIT_MASK_P0HI11Q_DESC_NUM 0xfff +#define BIT_P0HI11Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI11Q_DESC_NUM) << BIT_SHIFT_P0HI11Q_DESC_NUM) +#define BITS_P0HI11Q_DESC_NUM \ + (BIT_MASK_P0HI11Q_DESC_NUM << BIT_SHIFT_P0HI11Q_DESC_NUM) +#define BIT_CLEAR_P0HI11Q_DESC_NUM(x) ((x) & (~BITS_P0HI11Q_DESC_NUM)) +#define BIT_GET_P0HI11Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_DESC_NUM) & BIT_MASK_P0HI11Q_DESC_NUM) +#define BIT_SET_P0HI11Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI11Q_DESC_NUM(x) | BIT_P0HI11Q_DESC_NUM(v)) + +#define BIT_P0HI10Q_FLAG BIT(14) + +#define BIT_SHIFT_P0HI10Q_DESC_MODE 12 +#define BIT_MASK_P0HI10Q_DESC_MODE 0x3 +#define BIT_P0HI10Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI10Q_DESC_MODE) << BIT_SHIFT_P0HI10Q_DESC_MODE) +#define BITS_P0HI10Q_DESC_MODE \ + (BIT_MASK_P0HI10Q_DESC_MODE << BIT_SHIFT_P0HI10Q_DESC_MODE) +#define BIT_CLEAR_P0HI10Q_DESC_MODE(x) ((x) & (~BITS_P0HI10Q_DESC_MODE)) +#define BIT_GET_P0HI10Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_DESC_MODE) & BIT_MASK_P0HI10Q_DESC_MODE) +#define BIT_SET_P0HI10Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI10Q_DESC_MODE(x) | BIT_P0HI10Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI10Q_DESC_NUM 0 +#define BIT_MASK_P0HI10Q_DESC_NUM 0xfff +#define BIT_P0HI10Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI10Q_DESC_NUM) << BIT_SHIFT_P0HI10Q_DESC_NUM) +#define BITS_P0HI10Q_DESC_NUM \ + (BIT_MASK_P0HI10Q_DESC_NUM << BIT_SHIFT_P0HI10Q_DESC_NUM) +#define BIT_CLEAR_P0HI10Q_DESC_NUM(x) ((x) & (~BITS_P0HI10Q_DESC_NUM)) +#define BIT_GET_P0HI10Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_DESC_NUM) & BIT_MASK_P0HI10Q_DESC_NUM) +#define BIT_SET_P0HI10Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI10Q_DESC_NUM(x) | BIT_P0HI10Q_DESC_NUM(v)) + +/* 2 REG_P0HI12Q_HI13Q_TXBD_NUM (Offset 0x23C8) */ + +#define BIT_P0HI13Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI13Q_DESC_MODE 28 +#define BIT_MASK_P0HI13Q_DESC_MODE 0x3 +#define BIT_P0HI13Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI13Q_DESC_MODE) << BIT_SHIFT_P0HI13Q_DESC_MODE) +#define BITS_P0HI13Q_DESC_MODE \ + (BIT_MASK_P0HI13Q_DESC_MODE << BIT_SHIFT_P0HI13Q_DESC_MODE) +#define BIT_CLEAR_P0HI13Q_DESC_MODE(x) ((x) & (~BITS_P0HI13Q_DESC_MODE)) +#define BIT_GET_P0HI13Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_DESC_MODE) & BIT_MASK_P0HI13Q_DESC_MODE) +#define BIT_SET_P0HI13Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI13Q_DESC_MODE(x) | BIT_P0HI13Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI13Q_DESC_NUM 16 +#define BIT_MASK_P0HI13Q_DESC_NUM 0xfff +#define BIT_P0HI13Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI13Q_DESC_NUM) << BIT_SHIFT_P0HI13Q_DESC_NUM) +#define BITS_P0HI13Q_DESC_NUM \ + (BIT_MASK_P0HI13Q_DESC_NUM << BIT_SHIFT_P0HI13Q_DESC_NUM) +#define BIT_CLEAR_P0HI13Q_DESC_NUM(x) ((x) & (~BITS_P0HI13Q_DESC_NUM)) +#define BIT_GET_P0HI13Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_DESC_NUM) & BIT_MASK_P0HI13Q_DESC_NUM) +#define BIT_SET_P0HI13Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI13Q_DESC_NUM(x) | BIT_P0HI13Q_DESC_NUM(v)) + +#define BIT_P0HI12Q_FLAG BIT(14) + +#define BIT_SHIFT_P0HI12Q_DESC_MODE 12 +#define BIT_MASK_P0HI12Q_DESC_MODE 0x3 +#define BIT_P0HI12Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI12Q_DESC_MODE) << BIT_SHIFT_P0HI12Q_DESC_MODE) +#define BITS_P0HI12Q_DESC_MODE \ + (BIT_MASK_P0HI12Q_DESC_MODE << BIT_SHIFT_P0HI12Q_DESC_MODE) +#define BIT_CLEAR_P0HI12Q_DESC_MODE(x) ((x) & (~BITS_P0HI12Q_DESC_MODE)) +#define BIT_GET_P0HI12Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_DESC_MODE) & BIT_MASK_P0HI12Q_DESC_MODE) +#define BIT_SET_P0HI12Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI12Q_DESC_MODE(x) | BIT_P0HI12Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI12Q_DESC_NUM 0 +#define BIT_MASK_P0HI12Q_DESC_NUM 0xfff +#define BIT_P0HI12Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI12Q_DESC_NUM) << BIT_SHIFT_P0HI12Q_DESC_NUM) +#define BITS_P0HI12Q_DESC_NUM \ + (BIT_MASK_P0HI12Q_DESC_NUM << BIT_SHIFT_P0HI12Q_DESC_NUM) +#define BIT_CLEAR_P0HI12Q_DESC_NUM(x) ((x) & (~BITS_P0HI12Q_DESC_NUM)) +#define BIT_GET_P0HI12Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_DESC_NUM) & BIT_MASK_P0HI12Q_DESC_NUM) +#define BIT_SET_P0HI12Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI12Q_DESC_NUM(x) | BIT_P0HI12Q_DESC_NUM(v)) + +/* 2 REG_P0HI14Q_HI15Q_TXBD_NUM (Offset 0x23CC) */ + +#define BIT_P0HI15Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI15Q_DESC_MODE 28 +#define BIT_MASK_P0HI15Q_DESC_MODE 0x3 +#define BIT_P0HI15Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI15Q_DESC_MODE) << BIT_SHIFT_P0HI15Q_DESC_MODE) +#define BITS_P0HI15Q_DESC_MODE \ + (BIT_MASK_P0HI15Q_DESC_MODE << BIT_SHIFT_P0HI15Q_DESC_MODE) +#define BIT_CLEAR_P0HI15Q_DESC_MODE(x) ((x) & (~BITS_P0HI15Q_DESC_MODE)) +#define BIT_GET_P0HI15Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_DESC_MODE) & BIT_MASK_P0HI15Q_DESC_MODE) +#define BIT_SET_P0HI15Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI15Q_DESC_MODE(x) | BIT_P0HI15Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI15Q_DESC_NUM 16 +#define BIT_MASK_P0HI15Q_DESC_NUM 0xfff +#define BIT_P0HI15Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI15Q_DESC_NUM) << BIT_SHIFT_P0HI15Q_DESC_NUM) +#define BITS_P0HI15Q_DESC_NUM \ + (BIT_MASK_P0HI15Q_DESC_NUM << BIT_SHIFT_P0HI15Q_DESC_NUM) +#define BIT_CLEAR_P0HI15Q_DESC_NUM(x) ((x) & (~BITS_P0HI15Q_DESC_NUM)) +#define BIT_GET_P0HI15Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_DESC_NUM) & BIT_MASK_P0HI15Q_DESC_NUM) +#define BIT_SET_P0HI15Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI15Q_DESC_NUM(x) | BIT_P0HI15Q_DESC_NUM(v)) + +#define BIT_P0HI14Q_FLAG BIT(14) + +#define BIT_SHIFT_P0HI14Q_DESC_MODE 12 +#define BIT_MASK_P0HI14Q_DESC_MODE 0x3 +#define BIT_P0HI14Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI14Q_DESC_MODE) << BIT_SHIFT_P0HI14Q_DESC_MODE) +#define BITS_P0HI14Q_DESC_MODE \ + (BIT_MASK_P0HI14Q_DESC_MODE << BIT_SHIFT_P0HI14Q_DESC_MODE) +#define BIT_CLEAR_P0HI14Q_DESC_MODE(x) ((x) & (~BITS_P0HI14Q_DESC_MODE)) +#define BIT_GET_P0HI14Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_DESC_MODE) & BIT_MASK_P0HI14Q_DESC_MODE) +#define BIT_SET_P0HI14Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI14Q_DESC_MODE(x) | BIT_P0HI14Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI14Q_DESC_NUM 0 +#define BIT_MASK_P0HI14Q_DESC_NUM 0xfff +#define BIT_P0HI14Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI14Q_DESC_NUM) << BIT_SHIFT_P0HI14Q_DESC_NUM) +#define BITS_P0HI14Q_DESC_NUM \ + (BIT_MASK_P0HI14Q_DESC_NUM << BIT_SHIFT_P0HI14Q_DESC_NUM) +#define BIT_CLEAR_P0HI14Q_DESC_NUM(x) ((x) & (~BITS_P0HI14Q_DESC_NUM)) +#define BIT_GET_P0HI14Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_DESC_NUM) & BIT_MASK_P0HI14Q_DESC_NUM) +#define BIT_SET_P0HI14Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI14Q_DESC_NUM(x) | BIT_P0HI14Q_DESC_NUM(v)) + +/* 2 REG_ACH6_ACH7_TXBD_NUM (Offset 0x23F0) */ + +#define BIT_PCIE_ACH7_FLAG BIT(30) + +#define BIT_SHIFT_ACH7_DESC_MODE 28 +#define BIT_MASK_ACH7_DESC_MODE 0x3 +#define BIT_ACH7_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH7_DESC_MODE) << BIT_SHIFT_ACH7_DESC_MODE) +#define BITS_ACH7_DESC_MODE \ + (BIT_MASK_ACH7_DESC_MODE << BIT_SHIFT_ACH7_DESC_MODE) +#define BIT_CLEAR_ACH7_DESC_MODE(x) ((x) & (~BITS_ACH7_DESC_MODE)) +#define BIT_GET_ACH7_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH7_DESC_MODE) & BIT_MASK_ACH7_DESC_MODE) +#define BIT_SET_ACH7_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH7_DESC_MODE(x) | BIT_ACH7_DESC_MODE(v)) + +#define BIT_SHIFT_ACH7_DESC_NUM 16 +#define BIT_MASK_ACH7_DESC_NUM 0xfff +#define BIT_ACH7_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH7_DESC_NUM) << BIT_SHIFT_ACH7_DESC_NUM) +#define BITS_ACH7_DESC_NUM (BIT_MASK_ACH7_DESC_NUM << BIT_SHIFT_ACH7_DESC_NUM) +#define BIT_CLEAR_ACH7_DESC_NUM(x) ((x) & (~BITS_ACH7_DESC_NUM)) +#define BIT_GET_ACH7_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH7_DESC_NUM) & BIT_MASK_ACH7_DESC_NUM) +#define BIT_SET_ACH7_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH7_DESC_NUM(x) | BIT_ACH7_DESC_NUM(v)) + +#define BIT_PCIE_ACH6_FLAG BIT(14) + +#define BIT_SHIFT_ACH6_DESC_MODE 12 +#define BIT_MASK_ACH6_DESC_MODE 0x3 +#define BIT_ACH6_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH6_DESC_MODE) << BIT_SHIFT_ACH6_DESC_MODE) +#define BITS_ACH6_DESC_MODE \ + (BIT_MASK_ACH6_DESC_MODE << BIT_SHIFT_ACH6_DESC_MODE) +#define BIT_CLEAR_ACH6_DESC_MODE(x) ((x) & (~BITS_ACH6_DESC_MODE)) +#define BIT_GET_ACH6_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH6_DESC_MODE) & BIT_MASK_ACH6_DESC_MODE) +#define BIT_SET_ACH6_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH6_DESC_MODE(x) | BIT_ACH6_DESC_MODE(v)) + +#define BIT_SHIFT_ACH6_DESC_NUM 0 +#define BIT_MASK_ACH6_DESC_NUM 0xfff +#define BIT_ACH6_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH6_DESC_NUM) << BIT_SHIFT_ACH6_DESC_NUM) +#define BITS_ACH6_DESC_NUM (BIT_MASK_ACH6_DESC_NUM << BIT_SHIFT_ACH6_DESC_NUM) +#define BIT_CLEAR_ACH6_DESC_NUM(x) ((x) & (~BITS_ACH6_DESC_NUM)) +#define BIT_GET_ACH6_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH6_DESC_NUM) & BIT_MASK_ACH6_DESC_NUM) +#define BIT_SET_ACH6_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH6_DESC_NUM(x) | BIT_ACH6_DESC_NUM(v)) + +/* 2 REG_TXPAGE_INT_CTRL_0 (Offset 0x3200) */ + +#define BIT_CH0_INT_EN BIT(31) + +#define BIT_SHIFT_CH0_HIGH_TH 16 +#define BIT_MASK_CH0_HIGH_TH 0xfff +#define BIT_CH0_HIGH_TH(x) \ + (((x) & BIT_MASK_CH0_HIGH_TH) << BIT_SHIFT_CH0_HIGH_TH) +#define BITS_CH0_HIGH_TH (BIT_MASK_CH0_HIGH_TH << BIT_SHIFT_CH0_HIGH_TH) +#define BIT_CLEAR_CH0_HIGH_TH(x) ((x) & (~BITS_CH0_HIGH_TH)) +#define BIT_GET_CH0_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH0_HIGH_TH) & BIT_MASK_CH0_HIGH_TH) +#define BIT_SET_CH0_HIGH_TH(x, v) \ + (BIT_CLEAR_CH0_HIGH_TH(x) | BIT_CH0_HIGH_TH(v)) + +#define BIT_SHIFT_CH0_LOW_TH 0 +#define BIT_MASK_CH0_LOW_TH 0xfff +#define BIT_CH0_LOW_TH(x) (((x) & BIT_MASK_CH0_LOW_TH) << BIT_SHIFT_CH0_LOW_TH) +#define BITS_CH0_LOW_TH (BIT_MASK_CH0_LOW_TH << BIT_SHIFT_CH0_LOW_TH) +#define BIT_CLEAR_CH0_LOW_TH(x) ((x) & (~BITS_CH0_LOW_TH)) +#define BIT_GET_CH0_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH0_LOW_TH) & BIT_MASK_CH0_LOW_TH) +#define BIT_SET_CH0_LOW_TH(x, v) (BIT_CLEAR_CH0_LOW_TH(x) | BIT_CH0_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_1 (Offset 0x3204) */ + +#define BIT_CH1_INT_EN BIT(31) + +#define BIT_SHIFT_CH1_HIGH_TH 16 +#define BIT_MASK_CH1_HIGH_TH 0xfff +#define BIT_CH1_HIGH_TH(x) \ + (((x) & BIT_MASK_CH1_HIGH_TH) << BIT_SHIFT_CH1_HIGH_TH) +#define BITS_CH1_HIGH_TH (BIT_MASK_CH1_HIGH_TH << BIT_SHIFT_CH1_HIGH_TH) +#define BIT_CLEAR_CH1_HIGH_TH(x) ((x) & (~BITS_CH1_HIGH_TH)) +#define BIT_GET_CH1_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH1_HIGH_TH) & BIT_MASK_CH1_HIGH_TH) +#define BIT_SET_CH1_HIGH_TH(x, v) \ + (BIT_CLEAR_CH1_HIGH_TH(x) | BIT_CH1_HIGH_TH(v)) + +#define BIT_SHIFT_CH1_LOW_TH 0 +#define BIT_MASK_CH1_LOW_TH 0xfff +#define BIT_CH1_LOW_TH(x) (((x) & BIT_MASK_CH1_LOW_TH) << BIT_SHIFT_CH1_LOW_TH) +#define BITS_CH1_LOW_TH (BIT_MASK_CH1_LOW_TH << BIT_SHIFT_CH1_LOW_TH) +#define BIT_CLEAR_CH1_LOW_TH(x) ((x) & (~BITS_CH1_LOW_TH)) +#define BIT_GET_CH1_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH1_LOW_TH) & BIT_MASK_CH1_LOW_TH) +#define BIT_SET_CH1_LOW_TH(x, v) (BIT_CLEAR_CH1_LOW_TH(x) | BIT_CH1_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_2 (Offset 0x3208) */ + +#define BIT_CH2_INT_EN BIT(31) + +#define BIT_SHIFT_CH2_HIGH_TH 16 +#define BIT_MASK_CH2_HIGH_TH 0xfff +#define BIT_CH2_HIGH_TH(x) \ + (((x) & BIT_MASK_CH2_HIGH_TH) << BIT_SHIFT_CH2_HIGH_TH) +#define BITS_CH2_HIGH_TH (BIT_MASK_CH2_HIGH_TH << BIT_SHIFT_CH2_HIGH_TH) +#define BIT_CLEAR_CH2_HIGH_TH(x) ((x) & (~BITS_CH2_HIGH_TH)) +#define BIT_GET_CH2_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH2_HIGH_TH) & BIT_MASK_CH2_HIGH_TH) +#define BIT_SET_CH2_HIGH_TH(x, v) \ + (BIT_CLEAR_CH2_HIGH_TH(x) | BIT_CH2_HIGH_TH(v)) + +#define BIT_SHIFT_CH2_LOW_TH 0 +#define BIT_MASK_CH2_LOW_TH 0xfff +#define BIT_CH2_LOW_TH(x) (((x) & BIT_MASK_CH2_LOW_TH) << BIT_SHIFT_CH2_LOW_TH) +#define BITS_CH2_LOW_TH (BIT_MASK_CH2_LOW_TH << BIT_SHIFT_CH2_LOW_TH) +#define BIT_CLEAR_CH2_LOW_TH(x) ((x) & (~BITS_CH2_LOW_TH)) +#define BIT_GET_CH2_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH2_LOW_TH) & BIT_MASK_CH2_LOW_TH) +#define BIT_SET_CH2_LOW_TH(x, v) (BIT_CLEAR_CH2_LOW_TH(x) | BIT_CH2_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_3 (Offset 0x320C) */ + +#define BIT_CH3_INT_EN BIT(31) + +#define BIT_SHIFT_CH3_HIGH_TH 16 +#define BIT_MASK_CH3_HIGH_TH 0xfff +#define BIT_CH3_HIGH_TH(x) \ + (((x) & BIT_MASK_CH3_HIGH_TH) << BIT_SHIFT_CH3_HIGH_TH) +#define BITS_CH3_HIGH_TH (BIT_MASK_CH3_HIGH_TH << BIT_SHIFT_CH3_HIGH_TH) +#define BIT_CLEAR_CH3_HIGH_TH(x) ((x) & (~BITS_CH3_HIGH_TH)) +#define BIT_GET_CH3_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH3_HIGH_TH) & BIT_MASK_CH3_HIGH_TH) +#define BIT_SET_CH3_HIGH_TH(x, v) \ + (BIT_CLEAR_CH3_HIGH_TH(x) | BIT_CH3_HIGH_TH(v)) + +#define BIT_SHIFT_CH3_LOW_TH 0 +#define BIT_MASK_CH3_LOW_TH 0xfff +#define BIT_CH3_LOW_TH(x) (((x) & BIT_MASK_CH3_LOW_TH) << BIT_SHIFT_CH3_LOW_TH) +#define BITS_CH3_LOW_TH (BIT_MASK_CH3_LOW_TH << BIT_SHIFT_CH3_LOW_TH) +#define BIT_CLEAR_CH3_LOW_TH(x) ((x) & (~BITS_CH3_LOW_TH)) +#define BIT_GET_CH3_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH3_LOW_TH) & BIT_MASK_CH3_LOW_TH) +#define BIT_SET_CH3_LOW_TH(x, v) (BIT_CLEAR_CH3_LOW_TH(x) | BIT_CH3_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_4 (Offset 0x3210) */ + +#define BIT_CH4_INT_EN BIT(31) + +#define BIT_SHIFT_CH4_HIGH_TH 16 +#define BIT_MASK_CH4_HIGH_TH 0xfff +#define BIT_CH4_HIGH_TH(x) \ + (((x) & BIT_MASK_CH4_HIGH_TH) << BIT_SHIFT_CH4_HIGH_TH) +#define BITS_CH4_HIGH_TH (BIT_MASK_CH4_HIGH_TH << BIT_SHIFT_CH4_HIGH_TH) +#define BIT_CLEAR_CH4_HIGH_TH(x) ((x) & (~BITS_CH4_HIGH_TH)) +#define BIT_GET_CH4_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH4_HIGH_TH) & BIT_MASK_CH4_HIGH_TH) +#define BIT_SET_CH4_HIGH_TH(x, v) \ + (BIT_CLEAR_CH4_HIGH_TH(x) | BIT_CH4_HIGH_TH(v)) + +#define BIT_SHIFT_CH4_LOW_TH 0 +#define BIT_MASK_CH4_LOW_TH 0xfff +#define BIT_CH4_LOW_TH(x) (((x) & BIT_MASK_CH4_LOW_TH) << BIT_SHIFT_CH4_LOW_TH) +#define BITS_CH4_LOW_TH (BIT_MASK_CH4_LOW_TH << BIT_SHIFT_CH4_LOW_TH) +#define BIT_CLEAR_CH4_LOW_TH(x) ((x) & (~BITS_CH4_LOW_TH)) +#define BIT_GET_CH4_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH4_LOW_TH) & BIT_MASK_CH4_LOW_TH) +#define BIT_SET_CH4_LOW_TH(x, v) (BIT_CLEAR_CH4_LOW_TH(x) | BIT_CH4_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_5 (Offset 0x3214) */ + +#define BIT_CH5_INT_EN BIT(31) + +#define BIT_SHIFT_CH5_HIGH_TH 16 +#define BIT_MASK_CH5_HIGH_TH 0xfff +#define BIT_CH5_HIGH_TH(x) \ + (((x) & BIT_MASK_CH5_HIGH_TH) << BIT_SHIFT_CH5_HIGH_TH) +#define BITS_CH5_HIGH_TH (BIT_MASK_CH5_HIGH_TH << BIT_SHIFT_CH5_HIGH_TH) +#define BIT_CLEAR_CH5_HIGH_TH(x) ((x) & (~BITS_CH5_HIGH_TH)) +#define BIT_GET_CH5_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH5_HIGH_TH) & BIT_MASK_CH5_HIGH_TH) +#define BIT_SET_CH5_HIGH_TH(x, v) \ + (BIT_CLEAR_CH5_HIGH_TH(x) | BIT_CH5_HIGH_TH(v)) + +#define BIT_SHIFT_CH5_LOW_TH 0 +#define BIT_MASK_CH5_LOW_TH 0xfff +#define BIT_CH5_LOW_TH(x) (((x) & BIT_MASK_CH5_LOW_TH) << BIT_SHIFT_CH5_LOW_TH) +#define BITS_CH5_LOW_TH (BIT_MASK_CH5_LOW_TH << BIT_SHIFT_CH5_LOW_TH) +#define BIT_CLEAR_CH5_LOW_TH(x) ((x) & (~BITS_CH5_LOW_TH)) +#define BIT_GET_CH5_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH5_LOW_TH) & BIT_MASK_CH5_LOW_TH) +#define BIT_SET_CH5_LOW_TH(x, v) (BIT_CLEAR_CH5_LOW_TH(x) | BIT_CH5_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_6 (Offset 0x3218) */ + +#define BIT_CH6_INT_EN BIT(31) + +#define BIT_SHIFT_CH6_HIGH_TH 16 +#define BIT_MASK_CH6_HIGH_TH 0xfff +#define BIT_CH6_HIGH_TH(x) \ + (((x) & BIT_MASK_CH6_HIGH_TH) << BIT_SHIFT_CH6_HIGH_TH) +#define BITS_CH6_HIGH_TH (BIT_MASK_CH6_HIGH_TH << BIT_SHIFT_CH6_HIGH_TH) +#define BIT_CLEAR_CH6_HIGH_TH(x) ((x) & (~BITS_CH6_HIGH_TH)) +#define BIT_GET_CH6_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH6_HIGH_TH) & BIT_MASK_CH6_HIGH_TH) +#define BIT_SET_CH6_HIGH_TH(x, v) \ + (BIT_CLEAR_CH6_HIGH_TH(x) | BIT_CH6_HIGH_TH(v)) + +#define BIT_SHIFT_CH6_LOW_TH 0 +#define BIT_MASK_CH6_LOW_TH 0xfff +#define BIT_CH6_LOW_TH(x) (((x) & BIT_MASK_CH6_LOW_TH) << BIT_SHIFT_CH6_LOW_TH) +#define BITS_CH6_LOW_TH (BIT_MASK_CH6_LOW_TH << BIT_SHIFT_CH6_LOW_TH) +#define BIT_CLEAR_CH6_LOW_TH(x) ((x) & (~BITS_CH6_LOW_TH)) +#define BIT_GET_CH6_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH6_LOW_TH) & BIT_MASK_CH6_LOW_TH) +#define BIT_SET_CH6_LOW_TH(x, v) (BIT_CLEAR_CH6_LOW_TH(x) | BIT_CH6_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_7 (Offset 0x321C) */ + +#define BIT_CH7_INT_EN BIT(31) + +#define BIT_SHIFT_CH7_HIGH_TH 16 +#define BIT_MASK_CH7_HIGH_TH 0xfff +#define BIT_CH7_HIGH_TH(x) \ + (((x) & BIT_MASK_CH7_HIGH_TH) << BIT_SHIFT_CH7_HIGH_TH) +#define BITS_CH7_HIGH_TH (BIT_MASK_CH7_HIGH_TH << BIT_SHIFT_CH7_HIGH_TH) +#define BIT_CLEAR_CH7_HIGH_TH(x) ((x) & (~BITS_CH7_HIGH_TH)) +#define BIT_GET_CH7_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH7_HIGH_TH) & BIT_MASK_CH7_HIGH_TH) +#define BIT_SET_CH7_HIGH_TH(x, v) \ + (BIT_CLEAR_CH7_HIGH_TH(x) | BIT_CH7_HIGH_TH(v)) + +#define BIT_SHIFT_CH7_LOW_TH 0 +#define BIT_MASK_CH7_LOW_TH 0xfff +#define BIT_CH7_LOW_TH(x) (((x) & BIT_MASK_CH7_LOW_TH) << BIT_SHIFT_CH7_LOW_TH) +#define BITS_CH7_LOW_TH (BIT_MASK_CH7_LOW_TH << BIT_SHIFT_CH7_LOW_TH) +#define BIT_CLEAR_CH7_LOW_TH(x) ((x) & (~BITS_CH7_LOW_TH)) +#define BIT_GET_CH7_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH7_LOW_TH) & BIT_MASK_CH7_LOW_TH) +#define BIT_SET_CH7_LOW_TH(x, v) (BIT_CLEAR_CH7_LOW_TH(x) | BIT_CH7_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_8 (Offset 0x3220) */ + +#define BIT_CH8_INT_EN BIT(31) + +#define BIT_SHIFT_CH8_HIGH_TH 16 +#define BIT_MASK_CH8_HIGH_TH 0xfff +#define BIT_CH8_HIGH_TH(x) \ + (((x) & BIT_MASK_CH8_HIGH_TH) << BIT_SHIFT_CH8_HIGH_TH) +#define BITS_CH8_HIGH_TH (BIT_MASK_CH8_HIGH_TH << BIT_SHIFT_CH8_HIGH_TH) +#define BIT_CLEAR_CH8_HIGH_TH(x) ((x) & (~BITS_CH8_HIGH_TH)) +#define BIT_GET_CH8_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH8_HIGH_TH) & BIT_MASK_CH8_HIGH_TH) +#define BIT_SET_CH8_HIGH_TH(x, v) \ + (BIT_CLEAR_CH8_HIGH_TH(x) | BIT_CH8_HIGH_TH(v)) + +#define BIT_SHIFT_CH8_LOW_TH 0 +#define BIT_MASK_CH8_LOW_TH 0xfff +#define BIT_CH8_LOW_TH(x) (((x) & BIT_MASK_CH8_LOW_TH) << BIT_SHIFT_CH8_LOW_TH) +#define BITS_CH8_LOW_TH (BIT_MASK_CH8_LOW_TH << BIT_SHIFT_CH8_LOW_TH) +#define BIT_CLEAR_CH8_LOW_TH(x) ((x) & (~BITS_CH8_LOW_TH)) +#define BIT_GET_CH8_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH8_LOW_TH) & BIT_MASK_CH8_LOW_TH) +#define BIT_SET_CH8_LOW_TH(x, v) (BIT_CLEAR_CH8_LOW_TH(x) | BIT_CH8_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_9 (Offset 0x3224) */ + +#define BIT_CH9_INT_EN BIT(31) + +#define BIT_SHIFT_CH9_HIGH_TH 16 +#define BIT_MASK_CH9_HIGH_TH 0xfff +#define BIT_CH9_HIGH_TH(x) \ + (((x) & BIT_MASK_CH9_HIGH_TH) << BIT_SHIFT_CH9_HIGH_TH) +#define BITS_CH9_HIGH_TH (BIT_MASK_CH9_HIGH_TH << BIT_SHIFT_CH9_HIGH_TH) +#define BIT_CLEAR_CH9_HIGH_TH(x) ((x) & (~BITS_CH9_HIGH_TH)) +#define BIT_GET_CH9_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH9_HIGH_TH) & BIT_MASK_CH9_HIGH_TH) +#define BIT_SET_CH9_HIGH_TH(x, v) \ + (BIT_CLEAR_CH9_HIGH_TH(x) | BIT_CH9_HIGH_TH(v)) + +#define BIT_SHIFT_CH9_LOW_TH 0 +#define BIT_MASK_CH9_LOW_TH 0xfff +#define BIT_CH9_LOW_TH(x) (((x) & BIT_MASK_CH9_LOW_TH) << BIT_SHIFT_CH9_LOW_TH) +#define BITS_CH9_LOW_TH (BIT_MASK_CH9_LOW_TH << BIT_SHIFT_CH9_LOW_TH) +#define BIT_CLEAR_CH9_LOW_TH(x) ((x) & (~BITS_CH9_LOW_TH)) +#define BIT_GET_CH9_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH9_LOW_TH) & BIT_MASK_CH9_LOW_TH) +#define BIT_SET_CH9_LOW_TH(x, v) (BIT_CLEAR_CH9_LOW_TH(x) | BIT_CH9_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_10 (Offset 0x3228) */ + +#define BIT_CH10_INT_EN BIT(31) + +#define BIT_SHIFT_CH10_HIGH_TH 16 +#define BIT_MASK_CH10_HIGH_TH 0xfff +#define BIT_CH10_HIGH_TH(x) \ + (((x) & BIT_MASK_CH10_HIGH_TH) << BIT_SHIFT_CH10_HIGH_TH) +#define BITS_CH10_HIGH_TH (BIT_MASK_CH10_HIGH_TH << BIT_SHIFT_CH10_HIGH_TH) +#define BIT_CLEAR_CH10_HIGH_TH(x) ((x) & (~BITS_CH10_HIGH_TH)) +#define BIT_GET_CH10_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH10_HIGH_TH) & BIT_MASK_CH10_HIGH_TH) +#define BIT_SET_CH10_HIGH_TH(x, v) \ + (BIT_CLEAR_CH10_HIGH_TH(x) | BIT_CH10_HIGH_TH(v)) + +#define BIT_SHIFT_CH10_LOW_TH 0 +#define BIT_MASK_CH10_LOW_TH 0xfff +#define BIT_CH10_LOW_TH(x) \ + (((x) & BIT_MASK_CH10_LOW_TH) << BIT_SHIFT_CH10_LOW_TH) +#define BITS_CH10_LOW_TH (BIT_MASK_CH10_LOW_TH << BIT_SHIFT_CH10_LOW_TH) +#define BIT_CLEAR_CH10_LOW_TH(x) ((x) & (~BITS_CH10_LOW_TH)) +#define BIT_GET_CH10_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH10_LOW_TH) & BIT_MASK_CH10_LOW_TH) +#define BIT_SET_CH10_LOW_TH(x, v) \ + (BIT_CLEAR_CH10_LOW_TH(x) | BIT_CH10_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_11 (Offset 0x322C) */ + +#define BIT_CH11_INT_EN BIT(31) + +#define BIT_SHIFT_CH11_HIGH_TH 16 +#define BIT_MASK_CH11_HIGH_TH 0xfff +#define BIT_CH11_HIGH_TH(x) \ + (((x) & BIT_MASK_CH11_HIGH_TH) << BIT_SHIFT_CH11_HIGH_TH) +#define BITS_CH11_HIGH_TH (BIT_MASK_CH11_HIGH_TH << BIT_SHIFT_CH11_HIGH_TH) +#define BIT_CLEAR_CH11_HIGH_TH(x) ((x) & (~BITS_CH11_HIGH_TH)) +#define BIT_GET_CH11_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH11_HIGH_TH) & BIT_MASK_CH11_HIGH_TH) +#define BIT_SET_CH11_HIGH_TH(x, v) \ + (BIT_CLEAR_CH11_HIGH_TH(x) | BIT_CH11_HIGH_TH(v)) + +#define BIT_SHIFT_CH11_LOW_TH 0 +#define BIT_MASK_CH11_LOW_TH 0xfff +#define BIT_CH11_LOW_TH(x) \ + (((x) & BIT_MASK_CH11_LOW_TH) << BIT_SHIFT_CH11_LOW_TH) +#define BITS_CH11_LOW_TH (BIT_MASK_CH11_LOW_TH << BIT_SHIFT_CH11_LOW_TH) +#define BIT_CLEAR_CH11_LOW_TH(x) ((x) & (~BITS_CH11_LOW_TH)) +#define BIT_GET_CH11_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH11_LOW_TH) & BIT_MASK_CH11_LOW_TH) +#define BIT_SET_CH11_LOW_TH(x, v) \ + (BIT_CLEAR_CH11_LOW_TH(x) | BIT_CH11_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_12 (Offset 0x3230) */ + +#define BIT_CH12_INT_EN BIT(31) + +#define BIT_SHIFT_CH12_HIGH_TH 16 +#define BIT_MASK_CH12_HIGH_TH 0xfff +#define BIT_CH12_HIGH_TH(x) \ + (((x) & BIT_MASK_CH12_HIGH_TH) << BIT_SHIFT_CH12_HIGH_TH) +#define BITS_CH12_HIGH_TH (BIT_MASK_CH12_HIGH_TH << BIT_SHIFT_CH12_HIGH_TH) +#define BIT_CLEAR_CH12_HIGH_TH(x) ((x) & (~BITS_CH12_HIGH_TH)) +#define BIT_GET_CH12_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH12_HIGH_TH) & BIT_MASK_CH12_HIGH_TH) +#define BIT_SET_CH12_HIGH_TH(x, v) \ + (BIT_CLEAR_CH12_HIGH_TH(x) | BIT_CH12_HIGH_TH(v)) + +#define BIT_SHIFT_CH12_LOW_TH 0 +#define BIT_MASK_CH12_LOW_TH 0xfff +#define BIT_CH12_LOW_TH(x) \ + (((x) & BIT_MASK_CH12_LOW_TH) << BIT_SHIFT_CH12_LOW_TH) +#define BITS_CH12_LOW_TH (BIT_MASK_CH12_LOW_TH << BIT_SHIFT_CH12_LOW_TH) +#define BIT_CLEAR_CH12_LOW_TH(x) ((x) & (~BITS_CH12_LOW_TH)) +#define BIT_GET_CH12_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH12_LOW_TH) & BIT_MASK_CH12_LOW_TH) +#define BIT_SET_CH12_LOW_TH(x, v) \ + (BIT_CLEAR_CH12_LOW_TH(x) | BIT_CH12_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_13 (Offset 0x3234) */ + +#define BIT_CH13_INT_EN BIT(31) + +#define BIT_SHIFT_CH13_HIGH_TH 16 +#define BIT_MASK_CH13_HIGH_TH 0xfff +#define BIT_CH13_HIGH_TH(x) \ + (((x) & BIT_MASK_CH13_HIGH_TH) << BIT_SHIFT_CH13_HIGH_TH) +#define BITS_CH13_HIGH_TH (BIT_MASK_CH13_HIGH_TH << BIT_SHIFT_CH13_HIGH_TH) +#define BIT_CLEAR_CH13_HIGH_TH(x) ((x) & (~BITS_CH13_HIGH_TH)) +#define BIT_GET_CH13_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH13_HIGH_TH) & BIT_MASK_CH13_HIGH_TH) +#define BIT_SET_CH13_HIGH_TH(x, v) \ + (BIT_CLEAR_CH13_HIGH_TH(x) | BIT_CH13_HIGH_TH(v)) + +#define BIT_SHIFT_CH13_LOW_TH 0 +#define BIT_MASK_CH13_LOW_TH 0xfff +#define BIT_CH13_LOW_TH(x) \ + (((x) & BIT_MASK_CH13_LOW_TH) << BIT_SHIFT_CH13_LOW_TH) +#define BITS_CH13_LOW_TH (BIT_MASK_CH13_LOW_TH << BIT_SHIFT_CH13_LOW_TH) +#define BIT_CLEAR_CH13_LOW_TH(x) ((x) & (~BITS_CH13_LOW_TH)) +#define BIT_GET_CH13_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH13_LOW_TH) & BIT_MASK_CH13_LOW_TH) +#define BIT_SET_CH13_LOW_TH(x, v) \ + (BIT_CLEAR_CH13_LOW_TH(x) | BIT_CH13_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_14 (Offset 0x3238) */ + +#define BIT_CH14_INT_EN BIT(31) + +#define BIT_SHIFT_CH14_HIGH_TH 16 +#define BIT_MASK_CH14_HIGH_TH 0xfff +#define BIT_CH14_HIGH_TH(x) \ + (((x) & BIT_MASK_CH14_HIGH_TH) << BIT_SHIFT_CH14_HIGH_TH) +#define BITS_CH14_HIGH_TH (BIT_MASK_CH14_HIGH_TH << BIT_SHIFT_CH14_HIGH_TH) +#define BIT_CLEAR_CH14_HIGH_TH(x) ((x) & (~BITS_CH14_HIGH_TH)) +#define BIT_GET_CH14_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH14_HIGH_TH) & BIT_MASK_CH14_HIGH_TH) +#define BIT_SET_CH14_HIGH_TH(x, v) \ + (BIT_CLEAR_CH14_HIGH_TH(x) | BIT_CH14_HIGH_TH(v)) + +#define BIT_SHIFT_CH14_LOW_TH 0 +#define BIT_MASK_CH14_LOW_TH 0xfff +#define BIT_CH14_LOW_TH(x) \ + (((x) & BIT_MASK_CH14_LOW_TH) << BIT_SHIFT_CH14_LOW_TH) +#define BITS_CH14_LOW_TH (BIT_MASK_CH14_LOW_TH << BIT_SHIFT_CH14_LOW_TH) +#define BIT_CLEAR_CH14_LOW_TH(x) ((x) & (~BITS_CH14_LOW_TH)) +#define BIT_GET_CH14_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH14_LOW_TH) & BIT_MASK_CH14_LOW_TH) +#define BIT_SET_CH14_LOW_TH(x, v) \ + (BIT_CLEAR_CH14_LOW_TH(x) | BIT_CH14_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_15 (Offset 0x323C) */ + +#define BIT_CH15_INT_EN BIT(31) + +#define BIT_SHIFT_CH15_HIGH_TH 16 +#define BIT_MASK_CH15_HIGH_TH 0xfff +#define BIT_CH15_HIGH_TH(x) \ + (((x) & BIT_MASK_CH15_HIGH_TH) << BIT_SHIFT_CH15_HIGH_TH) +#define BITS_CH15_HIGH_TH (BIT_MASK_CH15_HIGH_TH << BIT_SHIFT_CH15_HIGH_TH) +#define BIT_CLEAR_CH15_HIGH_TH(x) ((x) & (~BITS_CH15_HIGH_TH)) +#define BIT_GET_CH15_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH15_HIGH_TH) & BIT_MASK_CH15_HIGH_TH) +#define BIT_SET_CH15_HIGH_TH(x, v) \ + (BIT_CLEAR_CH15_HIGH_TH(x) | BIT_CH15_HIGH_TH(v)) + +#define BIT_SHIFT_CH15_LOW_TH 0 +#define BIT_MASK_CH15_LOW_TH 0xfff +#define BIT_CH15_LOW_TH(x) \ + (((x) & BIT_MASK_CH15_LOW_TH) << BIT_SHIFT_CH15_LOW_TH) +#define BITS_CH15_LOW_TH (BIT_MASK_CH15_LOW_TH << BIT_SHIFT_CH15_LOW_TH) +#define BIT_CLEAR_CH15_LOW_TH(x) ((x) & (~BITS_CH15_LOW_TH)) +#define BIT_GET_CH15_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH15_LOW_TH) & BIT_MASK_CH15_LOW_TH) +#define BIT_SET_CH15_LOW_TH(x, v) \ + (BIT_CLEAR_CH15_LOW_TH(x) | BIT_CH15_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_16 (Offset 0x3240) */ + +#define BIT_CH16_INT_EN BIT(31) + +#define BIT_SHIFT_CH16_HIGH_TH 16 +#define BIT_MASK_CH16_HIGH_TH 0xfff +#define BIT_CH16_HIGH_TH(x) \ + (((x) & BIT_MASK_CH16_HIGH_TH) << BIT_SHIFT_CH16_HIGH_TH) +#define BITS_CH16_HIGH_TH (BIT_MASK_CH16_HIGH_TH << BIT_SHIFT_CH16_HIGH_TH) +#define BIT_CLEAR_CH16_HIGH_TH(x) ((x) & (~BITS_CH16_HIGH_TH)) +#define BIT_GET_CH16_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH16_HIGH_TH) & BIT_MASK_CH16_HIGH_TH) +#define BIT_SET_CH16_HIGH_TH(x, v) \ + (BIT_CLEAR_CH16_HIGH_TH(x) | BIT_CH16_HIGH_TH(v)) + +#define BIT_SHIFT_CH16_LOW_TH 0 +#define BIT_MASK_CH16_LOW_TH 0xfff +#define BIT_CH16_LOW_TH(x) \ + (((x) & BIT_MASK_CH16_LOW_TH) << BIT_SHIFT_CH16_LOW_TH) +#define BITS_CH16_LOW_TH (BIT_MASK_CH16_LOW_TH << BIT_SHIFT_CH16_LOW_TH) +#define BIT_CLEAR_CH16_LOW_TH(x) ((x) & (~BITS_CH16_LOW_TH)) +#define BIT_GET_CH16_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH16_LOW_TH) & BIT_MASK_CH16_LOW_TH) +#define BIT_SET_CH16_LOW_TH(x, v) \ + (BIT_CLEAR_CH16_LOW_TH(x) | BIT_CH16_LOW_TH(v)) + +/* 2 REG_ACH4_TXBD_IDX (Offset 0x3340) */ + +#define BIT_SHIFT_ACH4_HW_IDX 16 +#define BIT_MASK_ACH4_HW_IDX 0xfff +#define BIT_ACH4_HW_IDX(x) \ + (((x) & BIT_MASK_ACH4_HW_IDX) << BIT_SHIFT_ACH4_HW_IDX) +#define BITS_ACH4_HW_IDX (BIT_MASK_ACH4_HW_IDX << BIT_SHIFT_ACH4_HW_IDX) +#define BIT_CLEAR_ACH4_HW_IDX(x) ((x) & (~BITS_ACH4_HW_IDX)) +#define BIT_GET_ACH4_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH4_HW_IDX) & BIT_MASK_ACH4_HW_IDX) +#define BIT_SET_ACH4_HW_IDX(x, v) \ + (BIT_CLEAR_ACH4_HW_IDX(x) | BIT_ACH4_HW_IDX(v)) + +#define BIT_SHIFT_ACH4_HOST_IDX 0 +#define BIT_MASK_ACH4_HOST_IDX 0xfff +#define BIT_ACH4_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH4_HOST_IDX) << BIT_SHIFT_ACH4_HOST_IDX) +#define BITS_ACH4_HOST_IDX (BIT_MASK_ACH4_HOST_IDX << BIT_SHIFT_ACH4_HOST_IDX) +#define BIT_CLEAR_ACH4_HOST_IDX(x) ((x) & (~BITS_ACH4_HOST_IDX)) +#define BIT_GET_ACH4_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH4_HOST_IDX) & BIT_MASK_ACH4_HOST_IDX) +#define BIT_SET_ACH4_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH4_HOST_IDX(x) | BIT_ACH4_HOST_IDX(v)) + +/* 2 REG_ACH5_TXBD_IDX (Offset 0x3344) */ + +#define BIT_SHIFT_ACH5_HW_IDX 16 +#define BIT_MASK_ACH5_HW_IDX 0xfff +#define BIT_ACH5_HW_IDX(x) \ + (((x) & BIT_MASK_ACH5_HW_IDX) << BIT_SHIFT_ACH5_HW_IDX) +#define BITS_ACH5_HW_IDX (BIT_MASK_ACH5_HW_IDX << BIT_SHIFT_ACH5_HW_IDX) +#define BIT_CLEAR_ACH5_HW_IDX(x) ((x) & (~BITS_ACH5_HW_IDX)) +#define BIT_GET_ACH5_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH5_HW_IDX) & BIT_MASK_ACH5_HW_IDX) +#define BIT_SET_ACH5_HW_IDX(x, v) \ + (BIT_CLEAR_ACH5_HW_IDX(x) | BIT_ACH5_HW_IDX(v)) + +#define BIT_SHIFT_ACH5_HOST_IDX 0 +#define BIT_MASK_ACH5_HOST_IDX 0xfff +#define BIT_ACH5_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH5_HOST_IDX) << BIT_SHIFT_ACH5_HOST_IDX) +#define BITS_ACH5_HOST_IDX (BIT_MASK_ACH5_HOST_IDX << BIT_SHIFT_ACH5_HOST_IDX) +#define BIT_CLEAR_ACH5_HOST_IDX(x) ((x) & (~BITS_ACH5_HOST_IDX)) +#define BIT_GET_ACH5_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH5_HOST_IDX) & BIT_MASK_ACH5_HOST_IDX) +#define BIT_SET_ACH5_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH5_HOST_IDX(x) | BIT_ACH5_HOST_IDX(v)) + +/* 2 REG_ACH6_TXBD_IDX (Offset 0x3348) */ + +#define BIT_SHIFT_ACH6_HW_IDX 16 +#define BIT_MASK_ACH6_HW_IDX 0xfff +#define BIT_ACH6_HW_IDX(x) \ + (((x) & BIT_MASK_ACH6_HW_IDX) << BIT_SHIFT_ACH6_HW_IDX) +#define BITS_ACH6_HW_IDX (BIT_MASK_ACH6_HW_IDX << BIT_SHIFT_ACH6_HW_IDX) +#define BIT_CLEAR_ACH6_HW_IDX(x) ((x) & (~BITS_ACH6_HW_IDX)) +#define BIT_GET_ACH6_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH6_HW_IDX) & BIT_MASK_ACH6_HW_IDX) +#define BIT_SET_ACH6_HW_IDX(x, v) \ + (BIT_CLEAR_ACH6_HW_IDX(x) | BIT_ACH6_HW_IDX(v)) + +#define BIT_SHIFT_ACH6_HOST_IDX 0 +#define BIT_MASK_ACH6_HOST_IDX 0xfff +#define BIT_ACH6_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH6_HOST_IDX) << BIT_SHIFT_ACH6_HOST_IDX) +#define BITS_ACH6_HOST_IDX (BIT_MASK_ACH6_HOST_IDX << BIT_SHIFT_ACH6_HOST_IDX) +#define BIT_CLEAR_ACH6_HOST_IDX(x) ((x) & (~BITS_ACH6_HOST_IDX)) +#define BIT_GET_ACH6_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH6_HOST_IDX) & BIT_MASK_ACH6_HOST_IDX) +#define BIT_SET_ACH6_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH6_HOST_IDX(x) | BIT_ACH6_HOST_IDX(v)) + +/* 2 REG_ACH7_TXBD_IDX (Offset 0x334C) */ + +#define BIT_SHIFT_ACH7_HW_IDX 16 +#define BIT_MASK_ACH7_HW_IDX 0xfff +#define BIT_ACH7_HW_IDX(x) \ + (((x) & BIT_MASK_ACH7_HW_IDX) << BIT_SHIFT_ACH7_HW_IDX) +#define BITS_ACH7_HW_IDX (BIT_MASK_ACH7_HW_IDX << BIT_SHIFT_ACH7_HW_IDX) +#define BIT_CLEAR_ACH7_HW_IDX(x) ((x) & (~BITS_ACH7_HW_IDX)) +#define BIT_GET_ACH7_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH7_HW_IDX) & BIT_MASK_ACH7_HW_IDX) +#define BIT_SET_ACH7_HW_IDX(x, v) \ + (BIT_CLEAR_ACH7_HW_IDX(x) | BIT_ACH7_HW_IDX(v)) + +#define BIT_SHIFT_ACH7_HOST_IDX 0 +#define BIT_MASK_ACH7_HOST_IDX 0xfff +#define BIT_ACH7_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH7_HOST_IDX) << BIT_SHIFT_ACH7_HOST_IDX) +#define BITS_ACH7_HOST_IDX (BIT_MASK_ACH7_HOST_IDX << BIT_SHIFT_ACH7_HOST_IDX) +#define BIT_CLEAR_ACH7_HOST_IDX(x) ((x) & (~BITS_ACH7_HOST_IDX)) +#define BIT_GET_ACH7_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH7_HOST_IDX) & BIT_MASK_ACH7_HOST_IDX) +#define BIT_SET_ACH7_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH7_HOST_IDX(x) | BIT_ACH7_HOST_IDX(v)) + +/* 2 REG_ACH8_TXBD_IDX (Offset 0x3350) */ + +#define BIT_SHIFT_ACH8_HW_IDX 16 +#define BIT_MASK_ACH8_HW_IDX 0xfff +#define BIT_ACH8_HW_IDX(x) \ + (((x) & BIT_MASK_ACH8_HW_IDX) << BIT_SHIFT_ACH8_HW_IDX) +#define BITS_ACH8_HW_IDX (BIT_MASK_ACH8_HW_IDX << BIT_SHIFT_ACH8_HW_IDX) +#define BIT_CLEAR_ACH8_HW_IDX(x) ((x) & (~BITS_ACH8_HW_IDX)) +#define BIT_GET_ACH8_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH8_HW_IDX) & BIT_MASK_ACH8_HW_IDX) +#define BIT_SET_ACH8_HW_IDX(x, v) \ + (BIT_CLEAR_ACH8_HW_IDX(x) | BIT_ACH8_HW_IDX(v)) + +#define BIT_SHIFT_ACH8_HOST_IDX 0 +#define BIT_MASK_ACH8_HOST_IDX 0xfff +#define BIT_ACH8_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH8_HOST_IDX) << BIT_SHIFT_ACH8_HOST_IDX) +#define BITS_ACH8_HOST_IDX (BIT_MASK_ACH8_HOST_IDX << BIT_SHIFT_ACH8_HOST_IDX) +#define BIT_CLEAR_ACH8_HOST_IDX(x) ((x) & (~BITS_ACH8_HOST_IDX)) +#define BIT_GET_ACH8_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH8_HOST_IDX) & BIT_MASK_ACH8_HOST_IDX) +#define BIT_SET_ACH8_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH8_HOST_IDX(x) | BIT_ACH8_HOST_IDX(v)) + +/* 2 REG_ACH9_TXBD_IDX (Offset 0x3354) */ + +#define BIT_SHIFT_ACH9_HW_IDX 16 +#define BIT_MASK_ACH9_HW_IDX 0xfff +#define BIT_ACH9_HW_IDX(x) \ + (((x) & BIT_MASK_ACH9_HW_IDX) << BIT_SHIFT_ACH9_HW_IDX) +#define BITS_ACH9_HW_IDX (BIT_MASK_ACH9_HW_IDX << BIT_SHIFT_ACH9_HW_IDX) +#define BIT_CLEAR_ACH9_HW_IDX(x) ((x) & (~BITS_ACH9_HW_IDX)) +#define BIT_GET_ACH9_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH9_HW_IDX) & BIT_MASK_ACH9_HW_IDX) +#define BIT_SET_ACH9_HW_IDX(x, v) \ + (BIT_CLEAR_ACH9_HW_IDX(x) | BIT_ACH9_HW_IDX(v)) + +#define BIT_SHIFT_ACH9_HOST_IDX 0 +#define BIT_MASK_ACH9_HOST_IDX 0xfff +#define BIT_ACH9_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH9_HOST_IDX) << BIT_SHIFT_ACH9_HOST_IDX) +#define BITS_ACH9_HOST_IDX (BIT_MASK_ACH9_HOST_IDX << BIT_SHIFT_ACH9_HOST_IDX) +#define BIT_CLEAR_ACH9_HOST_IDX(x) ((x) & (~BITS_ACH9_HOST_IDX)) +#define BIT_GET_ACH9_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH9_HOST_IDX) & BIT_MASK_ACH9_HOST_IDX) +#define BIT_SET_ACH9_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH9_HOST_IDX(x) | BIT_ACH9_HOST_IDX(v)) + +/* 2 REG_ACH10_TXBD_IDX (Offset 0x3358) */ + +#define BIT_SHIFT_ACH10_HW_IDX 16 +#define BIT_MASK_ACH10_HW_IDX 0xfff +#define BIT_ACH10_HW_IDX(x) \ + (((x) & BIT_MASK_ACH10_HW_IDX) << BIT_SHIFT_ACH10_HW_IDX) +#define BITS_ACH10_HW_IDX (BIT_MASK_ACH10_HW_IDX << BIT_SHIFT_ACH10_HW_IDX) +#define BIT_CLEAR_ACH10_HW_IDX(x) ((x) & (~BITS_ACH10_HW_IDX)) +#define BIT_GET_ACH10_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH10_HW_IDX) & BIT_MASK_ACH10_HW_IDX) +#define BIT_SET_ACH10_HW_IDX(x, v) \ + (BIT_CLEAR_ACH10_HW_IDX(x) | BIT_ACH10_HW_IDX(v)) + +#define BIT_SHIFT_ACH10_HOST_IDX 0 +#define BIT_MASK_ACH10_HOST_IDX 0xfff +#define BIT_ACH10_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH10_HOST_IDX) << BIT_SHIFT_ACH10_HOST_IDX) +#define BITS_ACH10_HOST_IDX \ + (BIT_MASK_ACH10_HOST_IDX << BIT_SHIFT_ACH10_HOST_IDX) +#define BIT_CLEAR_ACH10_HOST_IDX(x) ((x) & (~BITS_ACH10_HOST_IDX)) +#define BIT_GET_ACH10_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH10_HOST_IDX) & BIT_MASK_ACH10_HOST_IDX) +#define BIT_SET_ACH10_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH10_HOST_IDX(x) | BIT_ACH10_HOST_IDX(v)) + +/* 2 REG_ACH11_TXBD_IDX (Offset 0x335C) */ + +#define BIT_SHIFT_ACH11_HW_IDX 16 +#define BIT_MASK_ACH11_HW_IDX 0xfff +#define BIT_ACH11_HW_IDX(x) \ + (((x) & BIT_MASK_ACH11_HW_IDX) << BIT_SHIFT_ACH11_HW_IDX) +#define BITS_ACH11_HW_IDX (BIT_MASK_ACH11_HW_IDX << BIT_SHIFT_ACH11_HW_IDX) +#define BIT_CLEAR_ACH11_HW_IDX(x) ((x) & (~BITS_ACH11_HW_IDX)) +#define BIT_GET_ACH11_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH11_HW_IDX) & BIT_MASK_ACH11_HW_IDX) +#define BIT_SET_ACH11_HW_IDX(x, v) \ + (BIT_CLEAR_ACH11_HW_IDX(x) | BIT_ACH11_HW_IDX(v)) + +#define BIT_SHIFT_ACH11_HOST_IDX 0 +#define BIT_MASK_ACH11_HOST_IDX 0xfff +#define BIT_ACH11_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH11_HOST_IDX) << BIT_SHIFT_ACH11_HOST_IDX) +#define BITS_ACH11_HOST_IDX \ + (BIT_MASK_ACH11_HOST_IDX << BIT_SHIFT_ACH11_HOST_IDX) +#define BIT_CLEAR_ACH11_HOST_IDX(x) ((x) & (~BITS_ACH11_HOST_IDX)) +#define BIT_GET_ACH11_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH11_HOST_IDX) & BIT_MASK_ACH11_HOST_IDX) +#define BIT_SET_ACH11_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH11_HOST_IDX(x) | BIT_ACH11_HOST_IDX(v)) + +/* 2 REG_ACH12_TXBD_IDX (Offset 0x3360) */ + +#define BIT_SHIFT_ACH12_HW_IDX 16 +#define BIT_MASK_ACH12_HW_IDX 0xfff +#define BIT_ACH12_HW_IDX(x) \ + (((x) & BIT_MASK_ACH12_HW_IDX) << BIT_SHIFT_ACH12_HW_IDX) +#define BITS_ACH12_HW_IDX (BIT_MASK_ACH12_HW_IDX << BIT_SHIFT_ACH12_HW_IDX) +#define BIT_CLEAR_ACH12_HW_IDX(x) ((x) & (~BITS_ACH12_HW_IDX)) +#define BIT_GET_ACH12_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH12_HW_IDX) & BIT_MASK_ACH12_HW_IDX) +#define BIT_SET_ACH12_HW_IDX(x, v) \ + (BIT_CLEAR_ACH12_HW_IDX(x) | BIT_ACH12_HW_IDX(v)) + +#define BIT_SHIFT_ACH12_HOST_IDX 0 +#define BIT_MASK_ACH12_HOST_IDX 0xfff +#define BIT_ACH12_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH12_HOST_IDX) << BIT_SHIFT_ACH12_HOST_IDX) +#define BITS_ACH12_HOST_IDX \ + (BIT_MASK_ACH12_HOST_IDX << BIT_SHIFT_ACH12_HOST_IDX) +#define BIT_CLEAR_ACH12_HOST_IDX(x) ((x) & (~BITS_ACH12_HOST_IDX)) +#define BIT_GET_ACH12_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH12_HOST_IDX) & BIT_MASK_ACH12_HOST_IDX) +#define BIT_SET_ACH12_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH12_HOST_IDX(x) | BIT_ACH12_HOST_IDX(v)) + +/* 2 REG_ACH13_TXBD_IDX (Offset 0x3364) */ + +#define BIT_SHIFT_ACH13_HW_IDX 16 +#define BIT_MASK_ACH13_HW_IDX 0xfff +#define BIT_ACH13_HW_IDX(x) \ + (((x) & BIT_MASK_ACH13_HW_IDX) << BIT_SHIFT_ACH13_HW_IDX) +#define BITS_ACH13_HW_IDX (BIT_MASK_ACH13_HW_IDX << BIT_SHIFT_ACH13_HW_IDX) +#define BIT_CLEAR_ACH13_HW_IDX(x) ((x) & (~BITS_ACH13_HW_IDX)) +#define BIT_GET_ACH13_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH13_HW_IDX) & BIT_MASK_ACH13_HW_IDX) +#define BIT_SET_ACH13_HW_IDX(x, v) \ + (BIT_CLEAR_ACH13_HW_IDX(x) | BIT_ACH13_HW_IDX(v)) + +#define BIT_SHIFT_ACH13_HOST_IDX 0 +#define BIT_MASK_ACH13_HOST_IDX 0xfff +#define BIT_ACH13_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH13_HOST_IDX) << BIT_SHIFT_ACH13_HOST_IDX) +#define BITS_ACH13_HOST_IDX \ + (BIT_MASK_ACH13_HOST_IDX << BIT_SHIFT_ACH13_HOST_IDX) +#define BIT_CLEAR_ACH13_HOST_IDX(x) ((x) & (~BITS_ACH13_HOST_IDX)) +#define BIT_GET_ACH13_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH13_HOST_IDX) & BIT_MASK_ACH13_HOST_IDX) +#define BIT_SET_ACH13_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH13_HOST_IDX(x) | BIT_ACH13_HOST_IDX(v)) + +/* 2 REG_AC_CHANNEL0_WEIGHT (Offset 0x3368) */ + +#define BIT_SHIFT_AC_CHANNEL0_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL0_WEIGHT 0xff +#define BIT_AC_CHANNEL0_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL0_WEIGHT) << BIT_SHIFT_AC_CHANNEL0_WEIGHT) +#define BITS_AC_CHANNEL0_WEIGHT \ + (BIT_MASK_AC_CHANNEL0_WEIGHT << BIT_SHIFT_AC_CHANNEL0_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL0_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL0_WEIGHT)) +#define BIT_GET_AC_CHANNEL0_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL0_WEIGHT) & BIT_MASK_AC_CHANNEL0_WEIGHT) +#define BIT_SET_AC_CHANNEL0_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL0_WEIGHT(x) | BIT_AC_CHANNEL0_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL1_WEIGHT (Offset 0x3369) */ + +#define BIT_SHIFT_AC_CHANNEL1_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL1_WEIGHT 0xff +#define BIT_AC_CHANNEL1_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL1_WEIGHT) << BIT_SHIFT_AC_CHANNEL1_WEIGHT) +#define BITS_AC_CHANNEL1_WEIGHT \ + (BIT_MASK_AC_CHANNEL1_WEIGHT << BIT_SHIFT_AC_CHANNEL1_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL1_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL1_WEIGHT)) +#define BIT_GET_AC_CHANNEL1_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL1_WEIGHT) & BIT_MASK_AC_CHANNEL1_WEIGHT) +#define BIT_SET_AC_CHANNEL1_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL1_WEIGHT(x) | BIT_AC_CHANNEL1_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL2_WEIGHT (Offset 0x336A) */ + +#define BIT_SHIFT_AC_CHANNEL2_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL2_WEIGHT 0xff +#define BIT_AC_CHANNEL2_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL2_WEIGHT) << BIT_SHIFT_AC_CHANNEL2_WEIGHT) +#define BITS_AC_CHANNEL2_WEIGHT \ + (BIT_MASK_AC_CHANNEL2_WEIGHT << BIT_SHIFT_AC_CHANNEL2_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL2_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL2_WEIGHT)) +#define BIT_GET_AC_CHANNEL2_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL2_WEIGHT) & BIT_MASK_AC_CHANNEL2_WEIGHT) +#define BIT_SET_AC_CHANNEL2_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL2_WEIGHT(x) | BIT_AC_CHANNEL2_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL3_WEIGHT (Offset 0x336B) */ + +#define BIT_SHIFT_AC_CHANNEL3_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL3_WEIGHT 0xff +#define BIT_AC_CHANNEL3_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL3_WEIGHT) << BIT_SHIFT_AC_CHANNEL3_WEIGHT) +#define BITS_AC_CHANNEL3_WEIGHT \ + (BIT_MASK_AC_CHANNEL3_WEIGHT << BIT_SHIFT_AC_CHANNEL3_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL3_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL3_WEIGHT)) +#define BIT_GET_AC_CHANNEL3_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL3_WEIGHT) & BIT_MASK_AC_CHANNEL3_WEIGHT) +#define BIT_SET_AC_CHANNEL3_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL3_WEIGHT(x) | BIT_AC_CHANNEL3_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL4_WEIGHT (Offset 0x336C) */ + +#define BIT_SHIFT_AC_CHANNEL4_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL4_WEIGHT 0xff +#define BIT_AC_CHANNEL4_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL4_WEIGHT) << BIT_SHIFT_AC_CHANNEL4_WEIGHT) +#define BITS_AC_CHANNEL4_WEIGHT \ + (BIT_MASK_AC_CHANNEL4_WEIGHT << BIT_SHIFT_AC_CHANNEL4_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL4_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL4_WEIGHT)) +#define BIT_GET_AC_CHANNEL4_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL4_WEIGHT) & BIT_MASK_AC_CHANNEL4_WEIGHT) +#define BIT_SET_AC_CHANNEL4_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL4_WEIGHT(x) | BIT_AC_CHANNEL4_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL5_WEIGHT (Offset 0x336D) */ + +#define BIT_SHIFT_AC_CHANNEL5_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL5_WEIGHT 0xff +#define BIT_AC_CHANNEL5_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL5_WEIGHT) << BIT_SHIFT_AC_CHANNEL5_WEIGHT) +#define BITS_AC_CHANNEL5_WEIGHT \ + (BIT_MASK_AC_CHANNEL5_WEIGHT << BIT_SHIFT_AC_CHANNEL5_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL5_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL5_WEIGHT)) +#define BIT_GET_AC_CHANNEL5_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL5_WEIGHT) & BIT_MASK_AC_CHANNEL5_WEIGHT) +#define BIT_SET_AC_CHANNEL5_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL5_WEIGHT(x) | BIT_AC_CHANNEL5_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL6_WEIGHT (Offset 0x336E) */ + +#define BIT_SHIFT_AC_CHANNEL6_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL6_WEIGHT 0xff +#define BIT_AC_CHANNEL6_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL6_WEIGHT) << BIT_SHIFT_AC_CHANNEL6_WEIGHT) +#define BITS_AC_CHANNEL6_WEIGHT \ + (BIT_MASK_AC_CHANNEL6_WEIGHT << BIT_SHIFT_AC_CHANNEL6_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL6_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL6_WEIGHT)) +#define BIT_GET_AC_CHANNEL6_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL6_WEIGHT) & BIT_MASK_AC_CHANNEL6_WEIGHT) +#define BIT_SET_AC_CHANNEL6_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL6_WEIGHT(x) | BIT_AC_CHANNEL6_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL7_WEIGHT (Offset 0x336F) */ + +#define BIT_SHIFT_AC_CHANNEL7_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL7_WEIGHT 0xff +#define BIT_AC_CHANNEL7_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL7_WEIGHT) << BIT_SHIFT_AC_CHANNEL7_WEIGHT) +#define BITS_AC_CHANNEL7_WEIGHT \ + (BIT_MASK_AC_CHANNEL7_WEIGHT << BIT_SHIFT_AC_CHANNEL7_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL7_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL7_WEIGHT)) +#define BIT_GET_AC_CHANNEL7_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL7_WEIGHT) & BIT_MASK_AC_CHANNEL7_WEIGHT) +#define BIT_SET_AC_CHANNEL7_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL7_WEIGHT(x) | BIT_AC_CHANNEL7_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL8_WEIGHT (Offset 0x3370) */ + +#define BIT_SHIFT_AC_CHANNEL8_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL8_WEIGHT 0xff +#define BIT_AC_CHANNEL8_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL8_WEIGHT) << BIT_SHIFT_AC_CHANNEL8_WEIGHT) +#define BITS_AC_CHANNEL8_WEIGHT \ + (BIT_MASK_AC_CHANNEL8_WEIGHT << BIT_SHIFT_AC_CHANNEL8_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL8_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL8_WEIGHT)) +#define BIT_GET_AC_CHANNEL8_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL8_WEIGHT) & BIT_MASK_AC_CHANNEL8_WEIGHT) +#define BIT_SET_AC_CHANNEL8_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL8_WEIGHT(x) | BIT_AC_CHANNEL8_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL9_WEIGHT (Offset 0x3371) */ + +#define BIT_SHIFT_AC_CHANNEL9_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL9_WEIGHT 0xff +#define BIT_AC_CHANNEL9_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL9_WEIGHT) << BIT_SHIFT_AC_CHANNEL9_WEIGHT) +#define BITS_AC_CHANNEL9_WEIGHT \ + (BIT_MASK_AC_CHANNEL9_WEIGHT << BIT_SHIFT_AC_CHANNEL9_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL9_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL9_WEIGHT)) +#define BIT_GET_AC_CHANNEL9_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL9_WEIGHT) & BIT_MASK_AC_CHANNEL9_WEIGHT) +#define BIT_SET_AC_CHANNEL9_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL9_WEIGHT(x) | BIT_AC_CHANNEL9_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL10_WEIGHT (Offset 0x3372) */ + +#define BIT_SHIFT_AC_CHANNEL10_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL10_WEIGHT 0xff +#define BIT_AC_CHANNEL10_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL10_WEIGHT) << BIT_SHIFT_AC_CHANNEL10_WEIGHT) +#define BITS_AC_CHANNEL10_WEIGHT \ + (BIT_MASK_AC_CHANNEL10_WEIGHT << BIT_SHIFT_AC_CHANNEL10_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL10_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL10_WEIGHT)) +#define BIT_GET_AC_CHANNEL10_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL10_WEIGHT) & BIT_MASK_AC_CHANNEL10_WEIGHT) +#define BIT_SET_AC_CHANNEL10_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL10_WEIGHT(x) | BIT_AC_CHANNEL10_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL11_WEIGHT (Offset 0x3373) */ + +#define BIT_SHIFT_AC_CHANNEL11_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL11_WEIGHT 0xff +#define BIT_AC_CHANNEL11_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL11_WEIGHT) << BIT_SHIFT_AC_CHANNEL11_WEIGHT) +#define BITS_AC_CHANNEL11_WEIGHT \ + (BIT_MASK_AC_CHANNEL11_WEIGHT << BIT_SHIFT_AC_CHANNEL11_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL11_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL11_WEIGHT)) +#define BIT_GET_AC_CHANNEL11_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL11_WEIGHT) & BIT_MASK_AC_CHANNEL11_WEIGHT) +#define BIT_SET_AC_CHANNEL11_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL11_WEIGHT(x) | BIT_AC_CHANNEL11_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL12_WEIGHT (Offset 0x3374) */ + +#define BIT_SHIFT_AC_CHANNEL12_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL12_WEIGHT 0xff +#define BIT_AC_CHANNEL12_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL12_WEIGHT) << BIT_SHIFT_AC_CHANNEL12_WEIGHT) +#define BITS_AC_CHANNEL12_WEIGHT \ + (BIT_MASK_AC_CHANNEL12_WEIGHT << BIT_SHIFT_AC_CHANNEL12_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL12_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL12_WEIGHT)) +#define BIT_GET_AC_CHANNEL12_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL12_WEIGHT) & BIT_MASK_AC_CHANNEL12_WEIGHT) +#define BIT_SET_AC_CHANNEL12_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL12_WEIGHT(x) | BIT_AC_CHANNEL12_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL13_WEIGHT (Offset 0x3375) */ + +#define BIT_SHIFT_AC_CHANNEL13_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL13_WEIGHT 0xff +#define BIT_AC_CHANNEL13_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL13_WEIGHT) << BIT_SHIFT_AC_CHANNEL13_WEIGHT) +#define BITS_AC_CHANNEL13_WEIGHT \ + (BIT_MASK_AC_CHANNEL13_WEIGHT << BIT_SHIFT_AC_CHANNEL13_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL13_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL13_WEIGHT)) +#define BIT_GET_AC_CHANNEL13_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL13_WEIGHT) & BIT_MASK_AC_CHANNEL13_WEIGHT) +#define BIT_SET_AC_CHANNEL13_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL13_WEIGHT(x) | BIT_AC_CHANNEL13_WEIGHT(v)) + +#endif + +#endif /* __RTL_WLAN_BITDEF_H__ */ diff --git a/hal/halmac/halmac_bit_8197f.h b/hal/halmac/halmac_bit_8197f.h index 2661a70..a8cf8eb 100644 --- a/hal/halmac/halmac_bit_8197f.h +++ b/hal/halmac/halmac_bit_8197f.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -106,20 +106,25 @@ #define BIT_SHIFT_VPDIDX_8197F 8 #define BIT_MASK_VPDIDX_8197F 0xff -#define BIT_VPDIDX_8197F(x) (((x) & BIT_MASK_VPDIDX_8197F) << BIT_SHIFT_VPDIDX_8197F) +#define BIT_VPDIDX_8197F(x) \ + (((x) & BIT_MASK_VPDIDX_8197F) << BIT_SHIFT_VPDIDX_8197F) #define BITS_VPDIDX_8197F (BIT_MASK_VPDIDX_8197F << BIT_SHIFT_VPDIDX_8197F) #define BIT_CLEAR_VPDIDX_8197F(x) ((x) & (~BITS_VPDIDX_8197F)) -#define BIT_GET_VPDIDX_8197F(x) (((x) >> BIT_SHIFT_VPDIDX_8197F) & BIT_MASK_VPDIDX_8197F) -#define BIT_SET_VPDIDX_8197F(x, v) (BIT_CLEAR_VPDIDX_8197F(x) | BIT_VPDIDX_8197F(v)) - +#define BIT_GET_VPDIDX_8197F(x) \ + (((x) >> BIT_SHIFT_VPDIDX_8197F) & BIT_MASK_VPDIDX_8197F) +#define BIT_SET_VPDIDX_8197F(x, v) \ + (BIT_CLEAR_VPDIDX_8197F(x) | BIT_VPDIDX_8197F(v)) #define BIT_SHIFT_EEM1_0_8197F 6 #define BIT_MASK_EEM1_0_8197F 0x3 -#define BIT_EEM1_0_8197F(x) (((x) & BIT_MASK_EEM1_0_8197F) << BIT_SHIFT_EEM1_0_8197F) +#define BIT_EEM1_0_8197F(x) \ + (((x) & BIT_MASK_EEM1_0_8197F) << BIT_SHIFT_EEM1_0_8197F) #define BITS_EEM1_0_8197F (BIT_MASK_EEM1_0_8197F << BIT_SHIFT_EEM1_0_8197F) #define BIT_CLEAR_EEM1_0_8197F(x) ((x) & (~BITS_EEM1_0_8197F)) -#define BIT_GET_EEM1_0_8197F(x) (((x) >> BIT_SHIFT_EEM1_0_8197F) & BIT_MASK_EEM1_0_8197F) -#define BIT_SET_EEM1_0_8197F(x, v) (BIT_CLEAR_EEM1_0_8197F(x) | BIT_EEM1_0_8197F(v)) +#define BIT_GET_EEM1_0_8197F(x) \ + (((x) >> BIT_SHIFT_EEM1_0_8197F) & BIT_MASK_EEM1_0_8197F) +#define BIT_SET_EEM1_0_8197F(x, v) \ + (BIT_CLEAR_EEM1_0_8197F(x) | BIT_EEM1_0_8197F(v)) #define BIT_AUTOLOAD_SUS_8197F BIT(5) #define BIT_EERPOMSEL_8197F BIT(4) @@ -132,42 +137,55 @@ #define BIT_SHIFT_VPD_DATA_8197F 0 #define BIT_MASK_VPD_DATA_8197F 0xffffffffL -#define BIT_VPD_DATA_8197F(x) (((x) & BIT_MASK_VPD_DATA_8197F) << BIT_SHIFT_VPD_DATA_8197F) -#define BITS_VPD_DATA_8197F (BIT_MASK_VPD_DATA_8197F << BIT_SHIFT_VPD_DATA_8197F) +#define BIT_VPD_DATA_8197F(x) \ + (((x) & BIT_MASK_VPD_DATA_8197F) << BIT_SHIFT_VPD_DATA_8197F) +#define BITS_VPD_DATA_8197F \ + (BIT_MASK_VPD_DATA_8197F << BIT_SHIFT_VPD_DATA_8197F) #define BIT_CLEAR_VPD_DATA_8197F(x) ((x) & (~BITS_VPD_DATA_8197F)) -#define BIT_GET_VPD_DATA_8197F(x) (((x) >> BIT_SHIFT_VPD_DATA_8197F) & BIT_MASK_VPD_DATA_8197F) -#define BIT_SET_VPD_DATA_8197F(x, v) (BIT_CLEAR_VPD_DATA_8197F(x) | BIT_VPD_DATA_8197F(v)) - +#define BIT_GET_VPD_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_VPD_DATA_8197F) & BIT_MASK_VPD_DATA_8197F) +#define BIT_SET_VPD_DATA_8197F(x, v) \ + (BIT_CLEAR_VPD_DATA_8197F(x) | BIT_VPD_DATA_8197F(v)) /* 2 REG_SYS_SWR_CTRL1_8197F */ #define BIT_SW18_C2_BIT0_8197F BIT(31) #define BIT_SHIFT_SW18_C1_8197F 29 #define BIT_MASK_SW18_C1_8197F 0x3 -#define BIT_SW18_C1_8197F(x) (((x) & BIT_MASK_SW18_C1_8197F) << BIT_SHIFT_SW18_C1_8197F) +#define BIT_SW18_C1_8197F(x) \ + (((x) & BIT_MASK_SW18_C1_8197F) << BIT_SHIFT_SW18_C1_8197F) #define BITS_SW18_C1_8197F (BIT_MASK_SW18_C1_8197F << BIT_SHIFT_SW18_C1_8197F) #define BIT_CLEAR_SW18_C1_8197F(x) ((x) & (~BITS_SW18_C1_8197F)) -#define BIT_GET_SW18_C1_8197F(x) (((x) >> BIT_SHIFT_SW18_C1_8197F) & BIT_MASK_SW18_C1_8197F) -#define BIT_SET_SW18_C1_8197F(x, v) (BIT_CLEAR_SW18_C1_8197F(x) | BIT_SW18_C1_8197F(v)) - +#define BIT_GET_SW18_C1_8197F(x) \ + (((x) >> BIT_SHIFT_SW18_C1_8197F) & BIT_MASK_SW18_C1_8197F) +#define BIT_SET_SW18_C1_8197F(x, v) \ + (BIT_CLEAR_SW18_C1_8197F(x) | BIT_SW18_C1_8197F(v)) #define BIT_SHIFT_REG_FREQ_L_8197F 25 #define BIT_MASK_REG_FREQ_L_8197F 0x7 -#define BIT_REG_FREQ_L_8197F(x) (((x) & BIT_MASK_REG_FREQ_L_8197F) << BIT_SHIFT_REG_FREQ_L_8197F) -#define BITS_REG_FREQ_L_8197F (BIT_MASK_REG_FREQ_L_8197F << BIT_SHIFT_REG_FREQ_L_8197F) +#define BIT_REG_FREQ_L_8197F(x) \ + (((x) & BIT_MASK_REG_FREQ_L_8197F) << BIT_SHIFT_REG_FREQ_L_8197F) +#define BITS_REG_FREQ_L_8197F \ + (BIT_MASK_REG_FREQ_L_8197F << BIT_SHIFT_REG_FREQ_L_8197F) #define BIT_CLEAR_REG_FREQ_L_8197F(x) ((x) & (~BITS_REG_FREQ_L_8197F)) -#define BIT_GET_REG_FREQ_L_8197F(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8197F) & BIT_MASK_REG_FREQ_L_8197F) -#define BIT_SET_REG_FREQ_L_8197F(x, v) (BIT_CLEAR_REG_FREQ_L_8197F(x) | BIT_REG_FREQ_L_8197F(v)) +#define BIT_GET_REG_FREQ_L_8197F(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L_8197F) & BIT_MASK_REG_FREQ_L_8197F) +#define BIT_SET_REG_FREQ_L_8197F(x, v) \ + (BIT_CLEAR_REG_FREQ_L_8197F(x) | BIT_REG_FREQ_L_8197F(v)) #define BIT_REG_EN_DUTY_8197F BIT(24) #define BIT_SHIFT_REG_MODE_8197F 22 #define BIT_MASK_REG_MODE_8197F 0x3 -#define BIT_REG_MODE_8197F(x) (((x) & BIT_MASK_REG_MODE_8197F) << BIT_SHIFT_REG_MODE_8197F) -#define BITS_REG_MODE_8197F (BIT_MASK_REG_MODE_8197F << BIT_SHIFT_REG_MODE_8197F) +#define BIT_REG_MODE_8197F(x) \ + (((x) & BIT_MASK_REG_MODE_8197F) << BIT_SHIFT_REG_MODE_8197F) +#define BITS_REG_MODE_8197F \ + (BIT_MASK_REG_MODE_8197F << BIT_SHIFT_REG_MODE_8197F) #define BIT_CLEAR_REG_MODE_8197F(x) ((x) & (~BITS_REG_MODE_8197F)) -#define BIT_GET_REG_MODE_8197F(x) (((x) >> BIT_SHIFT_REG_MODE_8197F) & BIT_MASK_REG_MODE_8197F) -#define BIT_SET_REG_MODE_8197F(x, v) (BIT_CLEAR_REG_MODE_8197F(x) | BIT_REG_MODE_8197F(v)) +#define BIT_GET_REG_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_REG_MODE_8197F) & BIT_MASK_REG_MODE_8197F) +#define BIT_SET_REG_MODE_8197F(x, v) \ + (BIT_CLEAR_REG_MODE_8197F(x) | BIT_REG_MODE_8197F(v)) #define BIT_REG_EN_SP_8197F BIT(21) #define BIT_REG_AUTO_L_8197F BIT(20) @@ -176,20 +194,29 @@ #define BIT_SHIFT_SW18_OCP_8197F 15 #define BIT_MASK_SW18_OCP_8197F 0x7 -#define BIT_SW18_OCP_8197F(x) (((x) & BIT_MASK_SW18_OCP_8197F) << BIT_SHIFT_SW18_OCP_8197F) -#define BITS_SW18_OCP_8197F (BIT_MASK_SW18_OCP_8197F << BIT_SHIFT_SW18_OCP_8197F) +#define BIT_SW18_OCP_8197F(x) \ + (((x) & BIT_MASK_SW18_OCP_8197F) << BIT_SHIFT_SW18_OCP_8197F) +#define BITS_SW18_OCP_8197F \ + (BIT_MASK_SW18_OCP_8197F << BIT_SHIFT_SW18_OCP_8197F) #define BIT_CLEAR_SW18_OCP_8197F(x) ((x) & (~BITS_SW18_OCP_8197F)) -#define BIT_GET_SW18_OCP_8197F(x) (((x) >> BIT_SHIFT_SW18_OCP_8197F) & BIT_MASK_SW18_OCP_8197F) -#define BIT_SET_SW18_OCP_8197F(x, v) (BIT_CLEAR_SW18_OCP_8197F(x) | BIT_SW18_OCP_8197F(v)) - +#define BIT_GET_SW18_OCP_8197F(x) \ + (((x) >> BIT_SHIFT_SW18_OCP_8197F) & BIT_MASK_SW18_OCP_8197F) +#define BIT_SET_SW18_OCP_8197F(x, v) \ + (BIT_CLEAR_SW18_OCP_8197F(x) | BIT_SW18_OCP_8197F(v)) #define BIT_SHIFT_CF_L_BIT0_TO_1_8197F 13 #define BIT_MASK_CF_L_BIT0_TO_1_8197F 0x3 -#define BIT_CF_L_BIT0_TO_1_8197F(x) (((x) & BIT_MASK_CF_L_BIT0_TO_1_8197F) << BIT_SHIFT_CF_L_BIT0_TO_1_8197F) -#define BITS_CF_L_BIT0_TO_1_8197F (BIT_MASK_CF_L_BIT0_TO_1_8197F << BIT_SHIFT_CF_L_BIT0_TO_1_8197F) +#define BIT_CF_L_BIT0_TO_1_8197F(x) \ + (((x) & BIT_MASK_CF_L_BIT0_TO_1_8197F) \ + << BIT_SHIFT_CF_L_BIT0_TO_1_8197F) +#define BITS_CF_L_BIT0_TO_1_8197F \ + (BIT_MASK_CF_L_BIT0_TO_1_8197F << BIT_SHIFT_CF_L_BIT0_TO_1_8197F) #define BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) ((x) & (~BITS_CF_L_BIT0_TO_1_8197F)) -#define BIT_GET_CF_L_BIT0_TO_1_8197F(x) (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1_8197F) & BIT_MASK_CF_L_BIT0_TO_1_8197F) -#define BIT_SET_CF_L_BIT0_TO_1_8197F(x, v) (BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) | BIT_CF_L_BIT0_TO_1_8197F(v)) +#define BIT_GET_CF_L_BIT0_TO_1_8197F(x) \ + (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1_8197F) & \ + BIT_MASK_CF_L_BIT0_TO_1_8197F) +#define BIT_SET_CF_L_BIT0_TO_1_8197F(x, v) \ + (BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) | BIT_CF_L_BIT0_TO_1_8197F(v)) #define BIT_SW18_FPWM_8197F BIT(11) #define BIT_SW18_SWEN_8197F BIT(9) @@ -241,21 +268,27 @@ #define BIT_SHIFT_SPS18_OCP_TH_8197F 16 #define BIT_MASK_SPS18_OCP_TH_8197F 0x7fff -#define BIT_SPS18_OCP_TH_8197F(x) (((x) & BIT_MASK_SPS18_OCP_TH_8197F) << BIT_SHIFT_SPS18_OCP_TH_8197F) -#define BITS_SPS18_OCP_TH_8197F (BIT_MASK_SPS18_OCP_TH_8197F << BIT_SHIFT_SPS18_OCP_TH_8197F) +#define BIT_SPS18_OCP_TH_8197F(x) \ + (((x) & BIT_MASK_SPS18_OCP_TH_8197F) << BIT_SHIFT_SPS18_OCP_TH_8197F) +#define BITS_SPS18_OCP_TH_8197F \ + (BIT_MASK_SPS18_OCP_TH_8197F << BIT_SHIFT_SPS18_OCP_TH_8197F) #define BIT_CLEAR_SPS18_OCP_TH_8197F(x) ((x) & (~BITS_SPS18_OCP_TH_8197F)) -#define BIT_GET_SPS18_OCP_TH_8197F(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8197F) & BIT_MASK_SPS18_OCP_TH_8197F) -#define BIT_SET_SPS18_OCP_TH_8197F(x, v) (BIT_CLEAR_SPS18_OCP_TH_8197F(x) | BIT_SPS18_OCP_TH_8197F(v)) - +#define BIT_GET_SPS18_OCP_TH_8197F(x) \ + (((x) >> BIT_SHIFT_SPS18_OCP_TH_8197F) & BIT_MASK_SPS18_OCP_TH_8197F) +#define BIT_SET_SPS18_OCP_TH_8197F(x, v) \ + (BIT_CLEAR_SPS18_OCP_TH_8197F(x) | BIT_SPS18_OCP_TH_8197F(v)) #define BIT_SHIFT_OCP_WINDOW_8197F 0 #define BIT_MASK_OCP_WINDOW_8197F 0xffff -#define BIT_OCP_WINDOW_8197F(x) (((x) & BIT_MASK_OCP_WINDOW_8197F) << BIT_SHIFT_OCP_WINDOW_8197F) -#define BITS_OCP_WINDOW_8197F (BIT_MASK_OCP_WINDOW_8197F << BIT_SHIFT_OCP_WINDOW_8197F) +#define BIT_OCP_WINDOW_8197F(x) \ + (((x) & BIT_MASK_OCP_WINDOW_8197F) << BIT_SHIFT_OCP_WINDOW_8197F) +#define BITS_OCP_WINDOW_8197F \ + (BIT_MASK_OCP_WINDOW_8197F << BIT_SHIFT_OCP_WINDOW_8197F) #define BIT_CLEAR_OCP_WINDOW_8197F(x) ((x) & (~BITS_OCP_WINDOW_8197F)) -#define BIT_GET_OCP_WINDOW_8197F(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8197F) & BIT_MASK_OCP_WINDOW_8197F) -#define BIT_SET_OCP_WINDOW_8197F(x, v) (BIT_CLEAR_OCP_WINDOW_8197F(x) | BIT_OCP_WINDOW_8197F(v)) - +#define BIT_GET_OCP_WINDOW_8197F(x) \ + (((x) >> BIT_SHIFT_OCP_WINDOW_8197F) & BIT_MASK_OCP_WINDOW_8197F) +#define BIT_SET_OCP_WINDOW_8197F(x, v) \ + (BIT_CLEAR_OCP_WINDOW_8197F(x) | BIT_OCP_WINDOW_8197F(v)) /* 2 REG_RSV_CTRL_8197F */ #define BIT_HREG_DBG_8197F BIT(23) @@ -278,21 +311,29 @@ #define BIT_SHIFT_LPLDH12_RSV_8197F 29 #define BIT_MASK_LPLDH12_RSV_8197F 0x7 -#define BIT_LPLDH12_RSV_8197F(x) (((x) & BIT_MASK_LPLDH12_RSV_8197F) << BIT_SHIFT_LPLDH12_RSV_8197F) -#define BITS_LPLDH12_RSV_8197F (BIT_MASK_LPLDH12_RSV_8197F << BIT_SHIFT_LPLDH12_RSV_8197F) +#define BIT_LPLDH12_RSV_8197F(x) \ + (((x) & BIT_MASK_LPLDH12_RSV_8197F) << BIT_SHIFT_LPLDH12_RSV_8197F) +#define BITS_LPLDH12_RSV_8197F \ + (BIT_MASK_LPLDH12_RSV_8197F << BIT_SHIFT_LPLDH12_RSV_8197F) #define BIT_CLEAR_LPLDH12_RSV_8197F(x) ((x) & (~BITS_LPLDH12_RSV_8197F)) -#define BIT_GET_LPLDH12_RSV_8197F(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8197F) & BIT_MASK_LPLDH12_RSV_8197F) -#define BIT_SET_LPLDH12_RSV_8197F(x, v) (BIT_CLEAR_LPLDH12_RSV_8197F(x) | BIT_LPLDH12_RSV_8197F(v)) +#define BIT_GET_LPLDH12_RSV_8197F(x) \ + (((x) >> BIT_SHIFT_LPLDH12_RSV_8197F) & BIT_MASK_LPLDH12_RSV_8197F) +#define BIT_SET_LPLDH12_RSV_8197F(x, v) \ + (BIT_CLEAR_LPLDH12_RSV_8197F(x) | BIT_LPLDH12_RSV_8197F(v)) #define BIT_LPLDH12_SLP_8197F BIT(28) #define BIT_SHIFT_LPLDH12_VADJ_8197F 24 #define BIT_MASK_LPLDH12_VADJ_8197F 0xf -#define BIT_LPLDH12_VADJ_8197F(x) (((x) & BIT_MASK_LPLDH12_VADJ_8197F) << BIT_SHIFT_LPLDH12_VADJ_8197F) -#define BITS_LPLDH12_VADJ_8197F (BIT_MASK_LPLDH12_VADJ_8197F << BIT_SHIFT_LPLDH12_VADJ_8197F) +#define BIT_LPLDH12_VADJ_8197F(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_8197F) << BIT_SHIFT_LPLDH12_VADJ_8197F) +#define BITS_LPLDH12_VADJ_8197F \ + (BIT_MASK_LPLDH12_VADJ_8197F << BIT_SHIFT_LPLDH12_VADJ_8197F) #define BIT_CLEAR_LPLDH12_VADJ_8197F(x) ((x) & (~BITS_LPLDH12_VADJ_8197F)) -#define BIT_GET_LPLDH12_VADJ_8197F(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8197F) & BIT_MASK_LPLDH12_VADJ_8197F) -#define BIT_SET_LPLDH12_VADJ_8197F(x, v) (BIT_CLEAR_LPLDH12_VADJ_8197F(x) | BIT_LPLDH12_VADJ_8197F(v)) +#define BIT_GET_LPLDH12_VADJ_8197F(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_8197F) & BIT_MASK_LPLDH12_VADJ_8197F) +#define BIT_SET_LPLDH12_VADJ_8197F(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_8197F(x) | BIT_LPLDH12_VADJ_8197F(v)) #define BIT_LDH12_EN_8197F BIT(16) #define BIT_POW_REGU_P1_8197F BIT(10) @@ -312,58 +353,79 @@ #define BIT_SHIFT_XTAL_CAP_XI_8197F 25 #define BIT_MASK_XTAL_CAP_XI_8197F 0x3f -#define BIT_XTAL_CAP_XI_8197F(x) (((x) & BIT_MASK_XTAL_CAP_XI_8197F) << BIT_SHIFT_XTAL_CAP_XI_8197F) -#define BITS_XTAL_CAP_XI_8197F (BIT_MASK_XTAL_CAP_XI_8197F << BIT_SHIFT_XTAL_CAP_XI_8197F) +#define BIT_XTAL_CAP_XI_8197F(x) \ + (((x) & BIT_MASK_XTAL_CAP_XI_8197F) << BIT_SHIFT_XTAL_CAP_XI_8197F) +#define BITS_XTAL_CAP_XI_8197F \ + (BIT_MASK_XTAL_CAP_XI_8197F << BIT_SHIFT_XTAL_CAP_XI_8197F) #define BIT_CLEAR_XTAL_CAP_XI_8197F(x) ((x) & (~BITS_XTAL_CAP_XI_8197F)) -#define BIT_GET_XTAL_CAP_XI_8197F(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8197F) & BIT_MASK_XTAL_CAP_XI_8197F) -#define BIT_SET_XTAL_CAP_XI_8197F(x, v) (BIT_CLEAR_XTAL_CAP_XI_8197F(x) | BIT_XTAL_CAP_XI_8197F(v)) - +#define BIT_GET_XTAL_CAP_XI_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XI_8197F) & BIT_MASK_XTAL_CAP_XI_8197F) +#define BIT_SET_XTAL_CAP_XI_8197F(x, v) \ + (BIT_CLEAR_XTAL_CAP_XI_8197F(x) | BIT_XTAL_CAP_XI_8197F(v)) #define BIT_SHIFT_XTAL_DRV_DIGI_8197F 23 #define BIT_MASK_XTAL_DRV_DIGI_8197F 0x3 -#define BIT_XTAL_DRV_DIGI_8197F(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8197F) << BIT_SHIFT_XTAL_DRV_DIGI_8197F) -#define BITS_XTAL_DRV_DIGI_8197F (BIT_MASK_XTAL_DRV_DIGI_8197F << BIT_SHIFT_XTAL_DRV_DIGI_8197F) +#define BIT_XTAL_DRV_DIGI_8197F(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_8197F) << BIT_SHIFT_XTAL_DRV_DIGI_8197F) +#define BITS_XTAL_DRV_DIGI_8197F \ + (BIT_MASK_XTAL_DRV_DIGI_8197F << BIT_SHIFT_XTAL_DRV_DIGI_8197F) #define BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) ((x) & (~BITS_XTAL_DRV_DIGI_8197F)) -#define BIT_GET_XTAL_DRV_DIGI_8197F(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8197F) & BIT_MASK_XTAL_DRV_DIGI_8197F) -#define BIT_SET_XTAL_DRV_DIGI_8197F(x, v) (BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) | BIT_XTAL_DRV_DIGI_8197F(v)) +#define BIT_GET_XTAL_DRV_DIGI_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8197F) & BIT_MASK_XTAL_DRV_DIGI_8197F) +#define BIT_SET_XTAL_DRV_DIGI_8197F(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) | BIT_XTAL_DRV_DIGI_8197F(v)) #define BIT_XTAL_DRV_USB_BIT1_8197F BIT(22) #define BIT_SHIFT_MAC_CLK_SEL_8197F 20 #define BIT_MASK_MAC_CLK_SEL_8197F 0x3 -#define BIT_MAC_CLK_SEL_8197F(x) (((x) & BIT_MASK_MAC_CLK_SEL_8197F) << BIT_SHIFT_MAC_CLK_SEL_8197F) -#define BITS_MAC_CLK_SEL_8197F (BIT_MASK_MAC_CLK_SEL_8197F << BIT_SHIFT_MAC_CLK_SEL_8197F) +#define BIT_MAC_CLK_SEL_8197F(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL_8197F) << BIT_SHIFT_MAC_CLK_SEL_8197F) +#define BITS_MAC_CLK_SEL_8197F \ + (BIT_MASK_MAC_CLK_SEL_8197F << BIT_SHIFT_MAC_CLK_SEL_8197F) #define BIT_CLEAR_MAC_CLK_SEL_8197F(x) ((x) & (~BITS_MAC_CLK_SEL_8197F)) -#define BIT_GET_MAC_CLK_SEL_8197F(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8197F) & BIT_MASK_MAC_CLK_SEL_8197F) -#define BIT_SET_MAC_CLK_SEL_8197F(x, v) (BIT_CLEAR_MAC_CLK_SEL_8197F(x) | BIT_MAC_CLK_SEL_8197F(v)) +#define BIT_GET_MAC_CLK_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL_8197F) & BIT_MASK_MAC_CLK_SEL_8197F) +#define BIT_SET_MAC_CLK_SEL_8197F(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL_8197F(x) | BIT_MAC_CLK_SEL_8197F(v)) #define BIT_XTAL_DRV_USB_BIT0_8197F BIT(19) #define BIT_SHIFT_XTAL_DRV_AFE_8197F 17 #define BIT_MASK_XTAL_DRV_AFE_8197F 0x3 -#define BIT_XTAL_DRV_AFE_8197F(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8197F) << BIT_SHIFT_XTAL_DRV_AFE_8197F) -#define BITS_XTAL_DRV_AFE_8197F (BIT_MASK_XTAL_DRV_AFE_8197F << BIT_SHIFT_XTAL_DRV_AFE_8197F) +#define BIT_XTAL_DRV_AFE_8197F(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_8197F) << BIT_SHIFT_XTAL_DRV_AFE_8197F) +#define BITS_XTAL_DRV_AFE_8197F \ + (BIT_MASK_XTAL_DRV_AFE_8197F << BIT_SHIFT_XTAL_DRV_AFE_8197F) #define BIT_CLEAR_XTAL_DRV_AFE_8197F(x) ((x) & (~BITS_XTAL_DRV_AFE_8197F)) -#define BIT_GET_XTAL_DRV_AFE_8197F(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8197F) & BIT_MASK_XTAL_DRV_AFE_8197F) -#define BIT_SET_XTAL_DRV_AFE_8197F(x, v) (BIT_CLEAR_XTAL_DRV_AFE_8197F(x) | BIT_XTAL_DRV_AFE_8197F(v)) - +#define BIT_GET_XTAL_DRV_AFE_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8197F) & BIT_MASK_XTAL_DRV_AFE_8197F) +#define BIT_SET_XTAL_DRV_AFE_8197F(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_8197F(x) | BIT_XTAL_DRV_AFE_8197F(v)) #define BIT_SHIFT_XTAL_DRV_RF2_8197F 15 #define BIT_MASK_XTAL_DRV_RF2_8197F 0x3 -#define BIT_XTAL_DRV_RF2_8197F(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8197F) << BIT_SHIFT_XTAL_DRV_RF2_8197F) -#define BITS_XTAL_DRV_RF2_8197F (BIT_MASK_XTAL_DRV_RF2_8197F << BIT_SHIFT_XTAL_DRV_RF2_8197F) +#define BIT_XTAL_DRV_RF2_8197F(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_8197F) << BIT_SHIFT_XTAL_DRV_RF2_8197F) +#define BITS_XTAL_DRV_RF2_8197F \ + (BIT_MASK_XTAL_DRV_RF2_8197F << BIT_SHIFT_XTAL_DRV_RF2_8197F) #define BIT_CLEAR_XTAL_DRV_RF2_8197F(x) ((x) & (~BITS_XTAL_DRV_RF2_8197F)) -#define BIT_GET_XTAL_DRV_RF2_8197F(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8197F) & BIT_MASK_XTAL_DRV_RF2_8197F) -#define BIT_SET_XTAL_DRV_RF2_8197F(x, v) (BIT_CLEAR_XTAL_DRV_RF2_8197F(x) | BIT_XTAL_DRV_RF2_8197F(v)) - +#define BIT_GET_XTAL_DRV_RF2_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8197F) & BIT_MASK_XTAL_DRV_RF2_8197F) +#define BIT_SET_XTAL_DRV_RF2_8197F(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_8197F(x) | BIT_XTAL_DRV_RF2_8197F(v)) #define BIT_SHIFT_XTAL_DRV_RF1_8197F 13 #define BIT_MASK_XTAL_DRV_RF1_8197F 0x3 -#define BIT_XTAL_DRV_RF1_8197F(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8197F) << BIT_SHIFT_XTAL_DRV_RF1_8197F) -#define BITS_XTAL_DRV_RF1_8197F (BIT_MASK_XTAL_DRV_RF1_8197F << BIT_SHIFT_XTAL_DRV_RF1_8197F) +#define BIT_XTAL_DRV_RF1_8197F(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF1_8197F) << BIT_SHIFT_XTAL_DRV_RF1_8197F) +#define BITS_XTAL_DRV_RF1_8197F \ + (BIT_MASK_XTAL_DRV_RF1_8197F << BIT_SHIFT_XTAL_DRV_RF1_8197F) #define BIT_CLEAR_XTAL_DRV_RF1_8197F(x) ((x) & (~BITS_XTAL_DRV_RF1_8197F)) -#define BIT_GET_XTAL_DRV_RF1_8197F(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8197F) & BIT_MASK_XTAL_DRV_RF1_8197F) -#define BIT_SET_XTAL_DRV_RF1_8197F(x, v) (BIT_CLEAR_XTAL_DRV_RF1_8197F(x) | BIT_XTAL_DRV_RF1_8197F(v)) +#define BIT_GET_XTAL_DRV_RF1_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8197F) & BIT_MASK_XTAL_DRV_RF1_8197F) +#define BIT_SET_XTAL_DRV_RF1_8197F(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF1_8197F(x) | BIT_XTAL_DRV_RF1_8197F(v)) #define BIT_XTAL_DELAY_DIGI_8197F BIT(12) #define BIT_XTAL_DELAY_USB_8197F BIT(11) @@ -376,20 +438,27 @@ #define BIT_SHIFT_XTAL_GMN_V1_8197F 3 #define BIT_MASK_XTAL_GMN_V1_8197F 0x3 -#define BIT_XTAL_GMN_V1_8197F(x) (((x) & BIT_MASK_XTAL_GMN_V1_8197F) << BIT_SHIFT_XTAL_GMN_V1_8197F) -#define BITS_XTAL_GMN_V1_8197F (BIT_MASK_XTAL_GMN_V1_8197F << BIT_SHIFT_XTAL_GMN_V1_8197F) +#define BIT_XTAL_GMN_V1_8197F(x) \ + (((x) & BIT_MASK_XTAL_GMN_V1_8197F) << BIT_SHIFT_XTAL_GMN_V1_8197F) +#define BITS_XTAL_GMN_V1_8197F \ + (BIT_MASK_XTAL_GMN_V1_8197F << BIT_SHIFT_XTAL_GMN_V1_8197F) #define BIT_CLEAR_XTAL_GMN_V1_8197F(x) ((x) & (~BITS_XTAL_GMN_V1_8197F)) -#define BIT_GET_XTAL_GMN_V1_8197F(x) (((x) >> BIT_SHIFT_XTAL_GMN_V1_8197F) & BIT_MASK_XTAL_GMN_V1_8197F) -#define BIT_SET_XTAL_GMN_V1_8197F(x, v) (BIT_CLEAR_XTAL_GMN_V1_8197F(x) | BIT_XTAL_GMN_V1_8197F(v)) - +#define BIT_GET_XTAL_GMN_V1_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V1_8197F) & BIT_MASK_XTAL_GMN_V1_8197F) +#define BIT_SET_XTAL_GMN_V1_8197F(x, v) \ + (BIT_CLEAR_XTAL_GMN_V1_8197F(x) | BIT_XTAL_GMN_V1_8197F(v)) #define BIT_SHIFT_XTAL_GMP_V1_8197F 1 #define BIT_MASK_XTAL_GMP_V1_8197F 0x3 -#define BIT_XTAL_GMP_V1_8197F(x) (((x) & BIT_MASK_XTAL_GMP_V1_8197F) << BIT_SHIFT_XTAL_GMP_V1_8197F) -#define BITS_XTAL_GMP_V1_8197F (BIT_MASK_XTAL_GMP_V1_8197F << BIT_SHIFT_XTAL_GMP_V1_8197F) +#define BIT_XTAL_GMP_V1_8197F(x) \ + (((x) & BIT_MASK_XTAL_GMP_V1_8197F) << BIT_SHIFT_XTAL_GMP_V1_8197F) +#define BITS_XTAL_GMP_V1_8197F \ + (BIT_MASK_XTAL_GMP_V1_8197F << BIT_SHIFT_XTAL_GMP_V1_8197F) #define BIT_CLEAR_XTAL_GMP_V1_8197F(x) ((x) & (~BITS_XTAL_GMP_V1_8197F)) -#define BIT_GET_XTAL_GMP_V1_8197F(x) (((x) >> BIT_SHIFT_XTAL_GMP_V1_8197F) & BIT_MASK_XTAL_GMP_V1_8197F) -#define BIT_SET_XTAL_GMP_V1_8197F(x, v) (BIT_CLEAR_XTAL_GMP_V1_8197F(x) | BIT_XTAL_GMP_V1_8197F(v)) +#define BIT_GET_XTAL_GMP_V1_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V1_8197F) & BIT_MASK_XTAL_GMP_V1_8197F) +#define BIT_SET_XTAL_GMP_V1_8197F(x, v) \ + (BIT_CLEAR_XTAL_GMP_V1_8197F(x) | BIT_XTAL_GMP_V1_8197F(v)) #define BIT_XTAL_EN_8197F BIT(0) @@ -397,58 +466,78 @@ #define BIT_SHIFT_RS_SET_V2_8197F 26 #define BIT_MASK_RS_SET_V2_8197F 0x7 -#define BIT_RS_SET_V2_8197F(x) (((x) & BIT_MASK_RS_SET_V2_8197F) << BIT_SHIFT_RS_SET_V2_8197F) -#define BITS_RS_SET_V2_8197F (BIT_MASK_RS_SET_V2_8197F << BIT_SHIFT_RS_SET_V2_8197F) +#define BIT_RS_SET_V2_8197F(x) \ + (((x) & BIT_MASK_RS_SET_V2_8197F) << BIT_SHIFT_RS_SET_V2_8197F) +#define BITS_RS_SET_V2_8197F \ + (BIT_MASK_RS_SET_V2_8197F << BIT_SHIFT_RS_SET_V2_8197F) #define BIT_CLEAR_RS_SET_V2_8197F(x) ((x) & (~BITS_RS_SET_V2_8197F)) -#define BIT_GET_RS_SET_V2_8197F(x) (((x) >> BIT_SHIFT_RS_SET_V2_8197F) & BIT_MASK_RS_SET_V2_8197F) -#define BIT_SET_RS_SET_V2_8197F(x, v) (BIT_CLEAR_RS_SET_V2_8197F(x) | BIT_RS_SET_V2_8197F(v)) - +#define BIT_GET_RS_SET_V2_8197F(x) \ + (((x) >> BIT_SHIFT_RS_SET_V2_8197F) & BIT_MASK_RS_SET_V2_8197F) +#define BIT_SET_RS_SET_V2_8197F(x, v) \ + (BIT_CLEAR_RS_SET_V2_8197F(x) | BIT_RS_SET_V2_8197F(v)) #define BIT_SHIFT_CP_BIAS_V2_8197F 18 #define BIT_MASK_CP_BIAS_V2_8197F 0x7 -#define BIT_CP_BIAS_V2_8197F(x) (((x) & BIT_MASK_CP_BIAS_V2_8197F) << BIT_SHIFT_CP_BIAS_V2_8197F) -#define BITS_CP_BIAS_V2_8197F (BIT_MASK_CP_BIAS_V2_8197F << BIT_SHIFT_CP_BIAS_V2_8197F) +#define BIT_CP_BIAS_V2_8197F(x) \ + (((x) & BIT_MASK_CP_BIAS_V2_8197F) << BIT_SHIFT_CP_BIAS_V2_8197F) +#define BITS_CP_BIAS_V2_8197F \ + (BIT_MASK_CP_BIAS_V2_8197F << BIT_SHIFT_CP_BIAS_V2_8197F) #define BIT_CLEAR_CP_BIAS_V2_8197F(x) ((x) & (~BITS_CP_BIAS_V2_8197F)) -#define BIT_GET_CP_BIAS_V2_8197F(x) (((x) >> BIT_SHIFT_CP_BIAS_V2_8197F) & BIT_MASK_CP_BIAS_V2_8197F) -#define BIT_SET_CP_BIAS_V2_8197F(x, v) (BIT_CLEAR_CP_BIAS_V2_8197F(x) | BIT_CP_BIAS_V2_8197F(v)) +#define BIT_GET_CP_BIAS_V2_8197F(x) \ + (((x) >> BIT_SHIFT_CP_BIAS_V2_8197F) & BIT_MASK_CP_BIAS_V2_8197F) +#define BIT_SET_CP_BIAS_V2_8197F(x, v) \ + (BIT_CLEAR_CP_BIAS_V2_8197F(x) | BIT_CP_BIAS_V2_8197F(v)) #define BIT_FREF_SEL_8197F BIT(16) #define BIT_SHIFT_MCCO_V2_8197F 14 #define BIT_MASK_MCCO_V2_8197F 0x3 -#define BIT_MCCO_V2_8197F(x) (((x) & BIT_MASK_MCCO_V2_8197F) << BIT_SHIFT_MCCO_V2_8197F) +#define BIT_MCCO_V2_8197F(x) \ + (((x) & BIT_MASK_MCCO_V2_8197F) << BIT_SHIFT_MCCO_V2_8197F) #define BITS_MCCO_V2_8197F (BIT_MASK_MCCO_V2_8197F << BIT_SHIFT_MCCO_V2_8197F) #define BIT_CLEAR_MCCO_V2_8197F(x) ((x) & (~BITS_MCCO_V2_8197F)) -#define BIT_GET_MCCO_V2_8197F(x) (((x) >> BIT_SHIFT_MCCO_V2_8197F) & BIT_MASK_MCCO_V2_8197F) -#define BIT_SET_MCCO_V2_8197F(x, v) (BIT_CLEAR_MCCO_V2_8197F(x) | BIT_MCCO_V2_8197F(v)) - +#define BIT_GET_MCCO_V2_8197F(x) \ + (((x) >> BIT_SHIFT_MCCO_V2_8197F) & BIT_MASK_MCCO_V2_8197F) +#define BIT_SET_MCCO_V2_8197F(x, v) \ + (BIT_CLEAR_MCCO_V2_8197F(x) | BIT_MCCO_V2_8197F(v)) #define BIT_SHIFT_CK320_EN_8197F 12 #define BIT_MASK_CK320_EN_8197F 0x3 -#define BIT_CK320_EN_8197F(x) (((x) & BIT_MASK_CK320_EN_8197F) << BIT_SHIFT_CK320_EN_8197F) -#define BITS_CK320_EN_8197F (BIT_MASK_CK320_EN_8197F << BIT_SHIFT_CK320_EN_8197F) +#define BIT_CK320_EN_8197F(x) \ + (((x) & BIT_MASK_CK320_EN_8197F) << BIT_SHIFT_CK320_EN_8197F) +#define BITS_CK320_EN_8197F \ + (BIT_MASK_CK320_EN_8197F << BIT_SHIFT_CK320_EN_8197F) #define BIT_CLEAR_CK320_EN_8197F(x) ((x) & (~BITS_CK320_EN_8197F)) -#define BIT_GET_CK320_EN_8197F(x) (((x) >> BIT_SHIFT_CK320_EN_8197F) & BIT_MASK_CK320_EN_8197F) -#define BIT_SET_CK320_EN_8197F(x, v) (BIT_CLEAR_CK320_EN_8197F(x) | BIT_CK320_EN_8197F(v)) +#define BIT_GET_CK320_EN_8197F(x) \ + (((x) >> BIT_SHIFT_CK320_EN_8197F) & BIT_MASK_CK320_EN_8197F) +#define BIT_SET_CK320_EN_8197F(x, v) \ + (BIT_CLEAR_CK320_EN_8197F(x) | BIT_CK320_EN_8197F(v)) #define BIT_AGPIO_GPO_8197F BIT(9) #define BIT_SHIFT_AGPIO_DRV_8197F 7 #define BIT_MASK_AGPIO_DRV_8197F 0x3 -#define BIT_AGPIO_DRV_8197F(x) (((x) & BIT_MASK_AGPIO_DRV_8197F) << BIT_SHIFT_AGPIO_DRV_8197F) -#define BITS_AGPIO_DRV_8197F (BIT_MASK_AGPIO_DRV_8197F << BIT_SHIFT_AGPIO_DRV_8197F) +#define BIT_AGPIO_DRV_8197F(x) \ + (((x) & BIT_MASK_AGPIO_DRV_8197F) << BIT_SHIFT_AGPIO_DRV_8197F) +#define BITS_AGPIO_DRV_8197F \ + (BIT_MASK_AGPIO_DRV_8197F << BIT_SHIFT_AGPIO_DRV_8197F) #define BIT_CLEAR_AGPIO_DRV_8197F(x) ((x) & (~BITS_AGPIO_DRV_8197F)) -#define BIT_GET_AGPIO_DRV_8197F(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8197F) & BIT_MASK_AGPIO_DRV_8197F) -#define BIT_SET_AGPIO_DRV_8197F(x, v) (BIT_CLEAR_AGPIO_DRV_8197F(x) | BIT_AGPIO_DRV_8197F(v)) - +#define BIT_GET_AGPIO_DRV_8197F(x) \ + (((x) >> BIT_SHIFT_AGPIO_DRV_8197F) & BIT_MASK_AGPIO_DRV_8197F) +#define BIT_SET_AGPIO_DRV_8197F(x, v) \ + (BIT_CLEAR_AGPIO_DRV_8197F(x) | BIT_AGPIO_DRV_8197F(v)) #define BIT_SHIFT_XTAL_CAP_XO_8197F 1 #define BIT_MASK_XTAL_CAP_XO_8197F 0x3f -#define BIT_XTAL_CAP_XO_8197F(x) (((x) & BIT_MASK_XTAL_CAP_XO_8197F) << BIT_SHIFT_XTAL_CAP_XO_8197F) -#define BITS_XTAL_CAP_XO_8197F (BIT_MASK_XTAL_CAP_XO_8197F << BIT_SHIFT_XTAL_CAP_XO_8197F) +#define BIT_XTAL_CAP_XO_8197F(x) \ + (((x) & BIT_MASK_XTAL_CAP_XO_8197F) << BIT_SHIFT_XTAL_CAP_XO_8197F) +#define BITS_XTAL_CAP_XO_8197F \ + (BIT_MASK_XTAL_CAP_XO_8197F << BIT_SHIFT_XTAL_CAP_XO_8197F) #define BIT_CLEAR_XTAL_CAP_XO_8197F(x) ((x) & (~BITS_XTAL_CAP_XO_8197F)) -#define BIT_GET_XTAL_CAP_XO_8197F(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8197F) & BIT_MASK_XTAL_CAP_XO_8197F) -#define BIT_SET_XTAL_CAP_XO_8197F(x, v) (BIT_CLEAR_XTAL_CAP_XO_8197F(x) | BIT_XTAL_CAP_XO_8197F(v)) +#define BIT_GET_XTAL_CAP_XO_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XO_8197F) & BIT_MASK_XTAL_CAP_XO_8197F) +#define BIT_SET_XTAL_CAP_XO_8197F(x, v) \ + (BIT_CLEAR_XTAL_CAP_XO_8197F(x) | BIT_XTAL_CAP_XO_8197F(v)) #define BIT_POW_PLL_8197F BIT(0) @@ -456,11 +545,14 @@ #define BIT_SHIFT_PS_V2_8197F 7 #define BIT_MASK_PS_V2_8197F 0x7 -#define BIT_PS_V2_8197F(x) (((x) & BIT_MASK_PS_V2_8197F) << BIT_SHIFT_PS_V2_8197F) +#define BIT_PS_V2_8197F(x) \ + (((x) & BIT_MASK_PS_V2_8197F) << BIT_SHIFT_PS_V2_8197F) #define BITS_PS_V2_8197F (BIT_MASK_PS_V2_8197F << BIT_SHIFT_PS_V2_8197F) #define BIT_CLEAR_PS_V2_8197F(x) ((x) & (~BITS_PS_V2_8197F)) -#define BIT_GET_PS_V2_8197F(x) (((x) >> BIT_SHIFT_PS_V2_8197F) & BIT_MASK_PS_V2_8197F) -#define BIT_SET_PS_V2_8197F(x, v) (BIT_CLEAR_PS_V2_8197F(x) | BIT_PS_V2_8197F(v)) +#define BIT_GET_PS_V2_8197F(x) \ + (((x) >> BIT_SHIFT_PS_V2_8197F) & BIT_MASK_PS_V2_8197F) +#define BIT_SET_PS_V2_8197F(x, v) \ + (BIT_CLEAR_PS_V2_8197F(x) | BIT_PS_V2_8197F(v)) #define BIT_PSEN_8197F BIT(6) #define BIT_DOGENB_8197F BIT(5) @@ -470,127 +562,168 @@ #define BIT_SHIFT_EF_PGPD_8197F 28 #define BIT_MASK_EF_PGPD_8197F 0x7 -#define BIT_EF_PGPD_8197F(x) (((x) & BIT_MASK_EF_PGPD_8197F) << BIT_SHIFT_EF_PGPD_8197F) +#define BIT_EF_PGPD_8197F(x) \ + (((x) & BIT_MASK_EF_PGPD_8197F) << BIT_SHIFT_EF_PGPD_8197F) #define BITS_EF_PGPD_8197F (BIT_MASK_EF_PGPD_8197F << BIT_SHIFT_EF_PGPD_8197F) #define BIT_CLEAR_EF_PGPD_8197F(x) ((x) & (~BITS_EF_PGPD_8197F)) -#define BIT_GET_EF_PGPD_8197F(x) (((x) >> BIT_SHIFT_EF_PGPD_8197F) & BIT_MASK_EF_PGPD_8197F) -#define BIT_SET_EF_PGPD_8197F(x, v) (BIT_CLEAR_EF_PGPD_8197F(x) | BIT_EF_PGPD_8197F(v)) - +#define BIT_GET_EF_PGPD_8197F(x) \ + (((x) >> BIT_SHIFT_EF_PGPD_8197F) & BIT_MASK_EF_PGPD_8197F) +#define BIT_SET_EF_PGPD_8197F(x, v) \ + (BIT_CLEAR_EF_PGPD_8197F(x) | BIT_EF_PGPD_8197F(v)) #define BIT_SHIFT_EF_RDT_8197F 24 #define BIT_MASK_EF_RDT_8197F 0xf -#define BIT_EF_RDT_8197F(x) (((x) & BIT_MASK_EF_RDT_8197F) << BIT_SHIFT_EF_RDT_8197F) +#define BIT_EF_RDT_8197F(x) \ + (((x) & BIT_MASK_EF_RDT_8197F) << BIT_SHIFT_EF_RDT_8197F) #define BITS_EF_RDT_8197F (BIT_MASK_EF_RDT_8197F << BIT_SHIFT_EF_RDT_8197F) #define BIT_CLEAR_EF_RDT_8197F(x) ((x) & (~BITS_EF_RDT_8197F)) -#define BIT_GET_EF_RDT_8197F(x) (((x) >> BIT_SHIFT_EF_RDT_8197F) & BIT_MASK_EF_RDT_8197F) -#define BIT_SET_EF_RDT_8197F(x, v) (BIT_CLEAR_EF_RDT_8197F(x) | BIT_EF_RDT_8197F(v)) - +#define BIT_GET_EF_RDT_8197F(x) \ + (((x) >> BIT_SHIFT_EF_RDT_8197F) & BIT_MASK_EF_RDT_8197F) +#define BIT_SET_EF_RDT_8197F(x, v) \ + (BIT_CLEAR_EF_RDT_8197F(x) | BIT_EF_RDT_8197F(v)) #define BIT_SHIFT_EF_PGTS_8197F 20 #define BIT_MASK_EF_PGTS_8197F 0xf -#define BIT_EF_PGTS_8197F(x) (((x) & BIT_MASK_EF_PGTS_8197F) << BIT_SHIFT_EF_PGTS_8197F) +#define BIT_EF_PGTS_8197F(x) \ + (((x) & BIT_MASK_EF_PGTS_8197F) << BIT_SHIFT_EF_PGTS_8197F) #define BITS_EF_PGTS_8197F (BIT_MASK_EF_PGTS_8197F << BIT_SHIFT_EF_PGTS_8197F) #define BIT_CLEAR_EF_PGTS_8197F(x) ((x) & (~BITS_EF_PGTS_8197F)) -#define BIT_GET_EF_PGTS_8197F(x) (((x) >> BIT_SHIFT_EF_PGTS_8197F) & BIT_MASK_EF_PGTS_8197F) -#define BIT_SET_EF_PGTS_8197F(x, v) (BIT_CLEAR_EF_PGTS_8197F(x) | BIT_EF_PGTS_8197F(v)) +#define BIT_GET_EF_PGTS_8197F(x) \ + (((x) >> BIT_SHIFT_EF_PGTS_8197F) & BIT_MASK_EF_PGTS_8197F) +#define BIT_SET_EF_PGTS_8197F(x, v) \ + (BIT_CLEAR_EF_PGTS_8197F(x) | BIT_EF_PGTS_8197F(v)) #define BIT_EF_PDWN_8197F BIT(19) #define BIT_EF_ALDEN_8197F BIT(18) #define BIT_SHIFT_EF_ADDR_8197F 8 #define BIT_MASK_EF_ADDR_8197F 0x3ff -#define BIT_EF_ADDR_8197F(x) (((x) & BIT_MASK_EF_ADDR_8197F) << BIT_SHIFT_EF_ADDR_8197F) +#define BIT_EF_ADDR_8197F(x) \ + (((x) & BIT_MASK_EF_ADDR_8197F) << BIT_SHIFT_EF_ADDR_8197F) #define BITS_EF_ADDR_8197F (BIT_MASK_EF_ADDR_8197F << BIT_SHIFT_EF_ADDR_8197F) #define BIT_CLEAR_EF_ADDR_8197F(x) ((x) & (~BITS_EF_ADDR_8197F)) -#define BIT_GET_EF_ADDR_8197F(x) (((x) >> BIT_SHIFT_EF_ADDR_8197F) & BIT_MASK_EF_ADDR_8197F) -#define BIT_SET_EF_ADDR_8197F(x, v) (BIT_CLEAR_EF_ADDR_8197F(x) | BIT_EF_ADDR_8197F(v)) - +#define BIT_GET_EF_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_EF_ADDR_8197F) & BIT_MASK_EF_ADDR_8197F) +#define BIT_SET_EF_ADDR_8197F(x, v) \ + (BIT_CLEAR_EF_ADDR_8197F(x) | BIT_EF_ADDR_8197F(v)) #define BIT_SHIFT_EF_DATA_8197F 0 #define BIT_MASK_EF_DATA_8197F 0xff -#define BIT_EF_DATA_8197F(x) (((x) & BIT_MASK_EF_DATA_8197F) << BIT_SHIFT_EF_DATA_8197F) +#define BIT_EF_DATA_8197F(x) \ + (((x) & BIT_MASK_EF_DATA_8197F) << BIT_SHIFT_EF_DATA_8197F) #define BITS_EF_DATA_8197F (BIT_MASK_EF_DATA_8197F << BIT_SHIFT_EF_DATA_8197F) #define BIT_CLEAR_EF_DATA_8197F(x) ((x) & (~BITS_EF_DATA_8197F)) -#define BIT_GET_EF_DATA_8197F(x) (((x) >> BIT_SHIFT_EF_DATA_8197F) & BIT_MASK_EF_DATA_8197F) -#define BIT_SET_EF_DATA_8197F(x, v) (BIT_CLEAR_EF_DATA_8197F(x) | BIT_EF_DATA_8197F(v)) - +#define BIT_GET_EF_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_EF_DATA_8197F) & BIT_MASK_EF_DATA_8197F) +#define BIT_SET_EF_DATA_8197F(x, v) \ + (BIT_CLEAR_EF_DATA_8197F(x) | BIT_EF_DATA_8197F(v)) /* 2 REG_LDO_EFUSE_CTRL_8197F */ #define BIT_LDOE25_EN_8197F BIT(31) #define BIT_SHIFT_LDOE25_V12ADJ_L_8197F 27 #define BIT_MASK_LDOE25_V12ADJ_L_8197F 0xf -#define BIT_LDOE25_V12ADJ_L_8197F(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8197F) << BIT_SHIFT_LDOE25_V12ADJ_L_8197F) -#define BITS_LDOE25_V12ADJ_L_8197F (BIT_MASK_LDOE25_V12ADJ_L_8197F << BIT_SHIFT_LDOE25_V12ADJ_L_8197F) +#define BIT_LDOE25_V12ADJ_L_8197F(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L_8197F) \ + << BIT_SHIFT_LDOE25_V12ADJ_L_8197F) +#define BITS_LDOE25_V12ADJ_L_8197F \ + (BIT_MASK_LDOE25_V12ADJ_L_8197F << BIT_SHIFT_LDOE25_V12ADJ_L_8197F) #define BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8197F)) -#define BIT_GET_LDOE25_V12ADJ_L_8197F(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8197F) & BIT_MASK_LDOE25_V12ADJ_L_8197F) -#define BIT_SET_LDOE25_V12ADJ_L_8197F(x, v) (BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) | BIT_LDOE25_V12ADJ_L_8197F(v)) - +#define BIT_GET_LDOE25_V12ADJ_L_8197F(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8197F) & \ + BIT_MASK_LDOE25_V12ADJ_L_8197F) +#define BIT_SET_LDOE25_V12ADJ_L_8197F(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) | BIT_LDOE25_V12ADJ_L_8197F(v)) #define BIT_SHIFT_EF_SCAN_START_V1_8197F 16 #define BIT_MASK_EF_SCAN_START_V1_8197F 0x3ff -#define BIT_EF_SCAN_START_V1_8197F(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8197F) << BIT_SHIFT_EF_SCAN_START_V1_8197F) -#define BITS_EF_SCAN_START_V1_8197F (BIT_MASK_EF_SCAN_START_V1_8197F << BIT_SHIFT_EF_SCAN_START_V1_8197F) -#define BIT_CLEAR_EF_SCAN_START_V1_8197F(x) ((x) & (~BITS_EF_SCAN_START_V1_8197F)) -#define BIT_GET_EF_SCAN_START_V1_8197F(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8197F) & BIT_MASK_EF_SCAN_START_V1_8197F) -#define BIT_SET_EF_SCAN_START_V1_8197F(x, v) (BIT_CLEAR_EF_SCAN_START_V1_8197F(x) | BIT_EF_SCAN_START_V1_8197F(v)) - +#define BIT_EF_SCAN_START_V1_8197F(x) \ + (((x) & BIT_MASK_EF_SCAN_START_V1_8197F) \ + << BIT_SHIFT_EF_SCAN_START_V1_8197F) +#define BITS_EF_SCAN_START_V1_8197F \ + (BIT_MASK_EF_SCAN_START_V1_8197F << BIT_SHIFT_EF_SCAN_START_V1_8197F) +#define BIT_CLEAR_EF_SCAN_START_V1_8197F(x) \ + ((x) & (~BITS_EF_SCAN_START_V1_8197F)) +#define BIT_GET_EF_SCAN_START_V1_8197F(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8197F) & \ + BIT_MASK_EF_SCAN_START_V1_8197F) +#define BIT_SET_EF_SCAN_START_V1_8197F(x, v) \ + (BIT_CLEAR_EF_SCAN_START_V1_8197F(x) | BIT_EF_SCAN_START_V1_8197F(v)) #define BIT_SHIFT_EF_SCAN_END_8197F 12 #define BIT_MASK_EF_SCAN_END_8197F 0xf -#define BIT_EF_SCAN_END_8197F(x) (((x) & BIT_MASK_EF_SCAN_END_8197F) << BIT_SHIFT_EF_SCAN_END_8197F) -#define BITS_EF_SCAN_END_8197F (BIT_MASK_EF_SCAN_END_8197F << BIT_SHIFT_EF_SCAN_END_8197F) +#define BIT_EF_SCAN_END_8197F(x) \ + (((x) & BIT_MASK_EF_SCAN_END_8197F) << BIT_SHIFT_EF_SCAN_END_8197F) +#define BITS_EF_SCAN_END_8197F \ + (BIT_MASK_EF_SCAN_END_8197F << BIT_SHIFT_EF_SCAN_END_8197F) #define BIT_CLEAR_EF_SCAN_END_8197F(x) ((x) & (~BITS_EF_SCAN_END_8197F)) -#define BIT_GET_EF_SCAN_END_8197F(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8197F) & BIT_MASK_EF_SCAN_END_8197F) -#define BIT_SET_EF_SCAN_END_8197F(x, v) (BIT_CLEAR_EF_SCAN_END_8197F(x) | BIT_EF_SCAN_END_8197F(v)) - +#define BIT_GET_EF_SCAN_END_8197F(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_END_8197F) & BIT_MASK_EF_SCAN_END_8197F) +#define BIT_SET_EF_SCAN_END_8197F(x, v) \ + (BIT_CLEAR_EF_SCAN_END_8197F(x) | BIT_EF_SCAN_END_8197F(v)) #define BIT_SHIFT_EF_CELL_SEL_8197F 8 #define BIT_MASK_EF_CELL_SEL_8197F 0x3 -#define BIT_EF_CELL_SEL_8197F(x) (((x) & BIT_MASK_EF_CELL_SEL_8197F) << BIT_SHIFT_EF_CELL_SEL_8197F) -#define BITS_EF_CELL_SEL_8197F (BIT_MASK_EF_CELL_SEL_8197F << BIT_SHIFT_EF_CELL_SEL_8197F) +#define BIT_EF_CELL_SEL_8197F(x) \ + (((x) & BIT_MASK_EF_CELL_SEL_8197F) << BIT_SHIFT_EF_CELL_SEL_8197F) +#define BITS_EF_CELL_SEL_8197F \ + (BIT_MASK_EF_CELL_SEL_8197F << BIT_SHIFT_EF_CELL_SEL_8197F) #define BIT_CLEAR_EF_CELL_SEL_8197F(x) ((x) & (~BITS_EF_CELL_SEL_8197F)) -#define BIT_GET_EF_CELL_SEL_8197F(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8197F) & BIT_MASK_EF_CELL_SEL_8197F) -#define BIT_SET_EF_CELL_SEL_8197F(x, v) (BIT_CLEAR_EF_CELL_SEL_8197F(x) | BIT_EF_CELL_SEL_8197F(v)) +#define BIT_GET_EF_CELL_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_EF_CELL_SEL_8197F) & BIT_MASK_EF_CELL_SEL_8197F) +#define BIT_SET_EF_CELL_SEL_8197F(x, v) \ + (BIT_CLEAR_EF_CELL_SEL_8197F(x) | BIT_EF_CELL_SEL_8197F(v)) #define BIT_EF_TRPT_8197F BIT(7) #define BIT_SHIFT_EF_TTHD_8197F 0 #define BIT_MASK_EF_TTHD_8197F 0x7f -#define BIT_EF_TTHD_8197F(x) (((x) & BIT_MASK_EF_TTHD_8197F) << BIT_SHIFT_EF_TTHD_8197F) +#define BIT_EF_TTHD_8197F(x) \ + (((x) & BIT_MASK_EF_TTHD_8197F) << BIT_SHIFT_EF_TTHD_8197F) #define BITS_EF_TTHD_8197F (BIT_MASK_EF_TTHD_8197F << BIT_SHIFT_EF_TTHD_8197F) #define BIT_CLEAR_EF_TTHD_8197F(x) ((x) & (~BITS_EF_TTHD_8197F)) -#define BIT_GET_EF_TTHD_8197F(x) (((x) >> BIT_SHIFT_EF_TTHD_8197F) & BIT_MASK_EF_TTHD_8197F) -#define BIT_SET_EF_TTHD_8197F(x, v) (BIT_CLEAR_EF_TTHD_8197F(x) | BIT_EF_TTHD_8197F(v)) - +#define BIT_GET_EF_TTHD_8197F(x) \ + (((x) >> BIT_SHIFT_EF_TTHD_8197F) & BIT_MASK_EF_TTHD_8197F) +#define BIT_SET_EF_TTHD_8197F(x, v) \ + (BIT_CLEAR_EF_TTHD_8197F(x) | BIT_EF_TTHD_8197F(v)) /* 2 REG_PWR_OPTION_CTRL_8197F */ #define BIT_SHIFT_DBG_SEL_V1_8197F 16 #define BIT_MASK_DBG_SEL_V1_8197F 0xff -#define BIT_DBG_SEL_V1_8197F(x) (((x) & BIT_MASK_DBG_SEL_V1_8197F) << BIT_SHIFT_DBG_SEL_V1_8197F) -#define BITS_DBG_SEL_V1_8197F (BIT_MASK_DBG_SEL_V1_8197F << BIT_SHIFT_DBG_SEL_V1_8197F) +#define BIT_DBG_SEL_V1_8197F(x) \ + (((x) & BIT_MASK_DBG_SEL_V1_8197F) << BIT_SHIFT_DBG_SEL_V1_8197F) +#define BITS_DBG_SEL_V1_8197F \ + (BIT_MASK_DBG_SEL_V1_8197F << BIT_SHIFT_DBG_SEL_V1_8197F) #define BIT_CLEAR_DBG_SEL_V1_8197F(x) ((x) & (~BITS_DBG_SEL_V1_8197F)) -#define BIT_GET_DBG_SEL_V1_8197F(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8197F) & BIT_MASK_DBG_SEL_V1_8197F) -#define BIT_SET_DBG_SEL_V1_8197F(x, v) (BIT_CLEAR_DBG_SEL_V1_8197F(x) | BIT_DBG_SEL_V1_8197F(v)) - +#define BIT_GET_DBG_SEL_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_V1_8197F) & BIT_MASK_DBG_SEL_V1_8197F) +#define BIT_SET_DBG_SEL_V1_8197F(x, v) \ + (BIT_CLEAR_DBG_SEL_V1_8197F(x) | BIT_DBG_SEL_V1_8197F(v)) #define BIT_SHIFT_DBG_SEL_BYTE_8197F 14 #define BIT_MASK_DBG_SEL_BYTE_8197F 0x3 -#define BIT_DBG_SEL_BYTE_8197F(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8197F) << BIT_SHIFT_DBG_SEL_BYTE_8197F) -#define BITS_DBG_SEL_BYTE_8197F (BIT_MASK_DBG_SEL_BYTE_8197F << BIT_SHIFT_DBG_SEL_BYTE_8197F) +#define BIT_DBG_SEL_BYTE_8197F(x) \ + (((x) & BIT_MASK_DBG_SEL_BYTE_8197F) << BIT_SHIFT_DBG_SEL_BYTE_8197F) +#define BITS_DBG_SEL_BYTE_8197F \ + (BIT_MASK_DBG_SEL_BYTE_8197F << BIT_SHIFT_DBG_SEL_BYTE_8197F) #define BIT_CLEAR_DBG_SEL_BYTE_8197F(x) ((x) & (~BITS_DBG_SEL_BYTE_8197F)) -#define BIT_GET_DBG_SEL_BYTE_8197F(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8197F) & BIT_MASK_DBG_SEL_BYTE_8197F) -#define BIT_SET_DBG_SEL_BYTE_8197F(x, v) (BIT_CLEAR_DBG_SEL_BYTE_8197F(x) | BIT_DBG_SEL_BYTE_8197F(v)) - +#define BIT_GET_DBG_SEL_BYTE_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8197F) & BIT_MASK_DBG_SEL_BYTE_8197F) +#define BIT_SET_DBG_SEL_BYTE_8197F(x, v) \ + (BIT_CLEAR_DBG_SEL_BYTE_8197F(x) | BIT_DBG_SEL_BYTE_8197F(v)) #define BIT_SHIFT_STD_L1_V1_8197F 12 #define BIT_MASK_STD_L1_V1_8197F 0x3 -#define BIT_STD_L1_V1_8197F(x) (((x) & BIT_MASK_STD_L1_V1_8197F) << BIT_SHIFT_STD_L1_V1_8197F) -#define BITS_STD_L1_V1_8197F (BIT_MASK_STD_L1_V1_8197F << BIT_SHIFT_STD_L1_V1_8197F) +#define BIT_STD_L1_V1_8197F(x) \ + (((x) & BIT_MASK_STD_L1_V1_8197F) << BIT_SHIFT_STD_L1_V1_8197F) +#define BITS_STD_L1_V1_8197F \ + (BIT_MASK_STD_L1_V1_8197F << BIT_SHIFT_STD_L1_V1_8197F) #define BIT_CLEAR_STD_L1_V1_8197F(x) ((x) & (~BITS_STD_L1_V1_8197F)) -#define BIT_GET_STD_L1_V1_8197F(x) (((x) >> BIT_SHIFT_STD_L1_V1_8197F) & BIT_MASK_STD_L1_V1_8197F) -#define BIT_SET_STD_L1_V1_8197F(x, v) (BIT_CLEAR_STD_L1_V1_8197F(x) | BIT_STD_L1_V1_8197F(v)) +#define BIT_GET_STD_L1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_STD_L1_V1_8197F) & BIT_MASK_STD_L1_V1_8197F) +#define BIT_SET_STD_L1_V1_8197F(x, v) \ + (BIT_CLEAR_STD_L1_V1_8197F(x) | BIT_STD_L1_V1_8197F(v)) #define BIT_SYSON_DBG_PAD_E2_8197F BIT(11) #define BIT_SYSON_LED_PAD_E2_8197F BIT(10) @@ -600,70 +733,101 @@ #define BIT_SHIFT_SYSON_SPS0WWV_WT_8197F 4 #define BIT_MASK_SYSON_SPS0WWV_WT_8197F 0x3 -#define BIT_SYSON_SPS0WWV_WT_8197F(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8197F) << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) -#define BITS_SYSON_SPS0WWV_WT_8197F (BIT_MASK_SYSON_SPS0WWV_WT_8197F << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) -#define BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) ((x) & (~BITS_SYSON_SPS0WWV_WT_8197F)) -#define BIT_GET_SYSON_SPS0WWV_WT_8197F(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) & BIT_MASK_SYSON_SPS0WWV_WT_8197F) -#define BIT_SET_SYSON_SPS0WWV_WT_8197F(x, v) (BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) | BIT_SYSON_SPS0WWV_WT_8197F(v)) - +#define BIT_SYSON_SPS0WWV_WT_8197F(x) \ + (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8197F) \ + << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) +#define BITS_SYSON_SPS0WWV_WT_8197F \ + (BIT_MASK_SYSON_SPS0WWV_WT_8197F << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) +#define BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) \ + ((x) & (~BITS_SYSON_SPS0WWV_WT_8197F)) +#define BIT_GET_SYSON_SPS0WWV_WT_8197F(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) & \ + BIT_MASK_SYSON_SPS0WWV_WT_8197F) +#define BIT_SET_SYSON_SPS0WWV_WT_8197F(x, v) \ + (BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) | BIT_SYSON_SPS0WWV_WT_8197F(v)) #define BIT_SHIFT_SYSON_SPS0LDO_WT_8197F 2 #define BIT_MASK_SYSON_SPS0LDO_WT_8197F 0x3 -#define BIT_SYSON_SPS0LDO_WT_8197F(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8197F) << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) -#define BITS_SYSON_SPS0LDO_WT_8197F (BIT_MASK_SYSON_SPS0LDO_WT_8197F << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) -#define BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) ((x) & (~BITS_SYSON_SPS0LDO_WT_8197F)) -#define BIT_GET_SYSON_SPS0LDO_WT_8197F(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) & BIT_MASK_SYSON_SPS0LDO_WT_8197F) -#define BIT_SET_SYSON_SPS0LDO_WT_8197F(x, v) (BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) | BIT_SYSON_SPS0LDO_WT_8197F(v)) - +#define BIT_SYSON_SPS0LDO_WT_8197F(x) \ + (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8197F) \ + << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) +#define BITS_SYSON_SPS0LDO_WT_8197F \ + (BIT_MASK_SYSON_SPS0LDO_WT_8197F << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) +#define BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) \ + ((x) & (~BITS_SYSON_SPS0LDO_WT_8197F)) +#define BIT_GET_SYSON_SPS0LDO_WT_8197F(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) & \ + BIT_MASK_SYSON_SPS0LDO_WT_8197F) +#define BIT_SET_SYSON_SPS0LDO_WT_8197F(x, v) \ + (BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) | BIT_SYSON_SPS0LDO_WT_8197F(v)) #define BIT_SHIFT_SYSON_RCLK_SCALE_8197F 0 #define BIT_MASK_SYSON_RCLK_SCALE_8197F 0x3 -#define BIT_SYSON_RCLK_SCALE_8197F(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8197F) << BIT_SHIFT_SYSON_RCLK_SCALE_8197F) -#define BITS_SYSON_RCLK_SCALE_8197F (BIT_MASK_SYSON_RCLK_SCALE_8197F << BIT_SHIFT_SYSON_RCLK_SCALE_8197F) -#define BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) ((x) & (~BITS_SYSON_RCLK_SCALE_8197F)) -#define BIT_GET_SYSON_RCLK_SCALE_8197F(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8197F) & BIT_MASK_SYSON_RCLK_SCALE_8197F) -#define BIT_SET_SYSON_RCLK_SCALE_8197F(x, v) (BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) | BIT_SYSON_RCLK_SCALE_8197F(v)) - +#define BIT_SYSON_RCLK_SCALE_8197F(x) \ + (((x) & BIT_MASK_SYSON_RCLK_SCALE_8197F) \ + << BIT_SHIFT_SYSON_RCLK_SCALE_8197F) +#define BITS_SYSON_RCLK_SCALE_8197F \ + (BIT_MASK_SYSON_RCLK_SCALE_8197F << BIT_SHIFT_SYSON_RCLK_SCALE_8197F) +#define BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) \ + ((x) & (~BITS_SYSON_RCLK_SCALE_8197F)) +#define BIT_GET_SYSON_RCLK_SCALE_8197F(x) \ + (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8197F) & \ + BIT_MASK_SYSON_RCLK_SCALE_8197F) +#define BIT_SET_SYSON_RCLK_SCALE_8197F(x, v) \ + (BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) | BIT_SYSON_RCLK_SCALE_8197F(v)) /* 2 REG_CAL_TIMER_8197F */ #define BIT_SHIFT_MATCH_CNT_8197F 8 #define BIT_MASK_MATCH_CNT_8197F 0xff -#define BIT_MATCH_CNT_8197F(x) (((x) & BIT_MASK_MATCH_CNT_8197F) << BIT_SHIFT_MATCH_CNT_8197F) -#define BITS_MATCH_CNT_8197F (BIT_MASK_MATCH_CNT_8197F << BIT_SHIFT_MATCH_CNT_8197F) +#define BIT_MATCH_CNT_8197F(x) \ + (((x) & BIT_MASK_MATCH_CNT_8197F) << BIT_SHIFT_MATCH_CNT_8197F) +#define BITS_MATCH_CNT_8197F \ + (BIT_MASK_MATCH_CNT_8197F << BIT_SHIFT_MATCH_CNT_8197F) #define BIT_CLEAR_MATCH_CNT_8197F(x) ((x) & (~BITS_MATCH_CNT_8197F)) -#define BIT_GET_MATCH_CNT_8197F(x) (((x) >> BIT_SHIFT_MATCH_CNT_8197F) & BIT_MASK_MATCH_CNT_8197F) -#define BIT_SET_MATCH_CNT_8197F(x, v) (BIT_CLEAR_MATCH_CNT_8197F(x) | BIT_MATCH_CNT_8197F(v)) - +#define BIT_GET_MATCH_CNT_8197F(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8197F) & BIT_MASK_MATCH_CNT_8197F) +#define BIT_SET_MATCH_CNT_8197F(x, v) \ + (BIT_CLEAR_MATCH_CNT_8197F(x) | BIT_MATCH_CNT_8197F(v)) #define BIT_SHIFT_CAL_SCAL_8197F 0 #define BIT_MASK_CAL_SCAL_8197F 0xff -#define BIT_CAL_SCAL_8197F(x) (((x) & BIT_MASK_CAL_SCAL_8197F) << BIT_SHIFT_CAL_SCAL_8197F) -#define BITS_CAL_SCAL_8197F (BIT_MASK_CAL_SCAL_8197F << BIT_SHIFT_CAL_SCAL_8197F) +#define BIT_CAL_SCAL_8197F(x) \ + (((x) & BIT_MASK_CAL_SCAL_8197F) << BIT_SHIFT_CAL_SCAL_8197F) +#define BITS_CAL_SCAL_8197F \ + (BIT_MASK_CAL_SCAL_8197F << BIT_SHIFT_CAL_SCAL_8197F) #define BIT_CLEAR_CAL_SCAL_8197F(x) ((x) & (~BITS_CAL_SCAL_8197F)) -#define BIT_GET_CAL_SCAL_8197F(x) (((x) >> BIT_SHIFT_CAL_SCAL_8197F) & BIT_MASK_CAL_SCAL_8197F) -#define BIT_SET_CAL_SCAL_8197F(x, v) (BIT_CLEAR_CAL_SCAL_8197F(x) | BIT_CAL_SCAL_8197F(v)) - +#define BIT_GET_CAL_SCAL_8197F(x) \ + (((x) >> BIT_SHIFT_CAL_SCAL_8197F) & BIT_MASK_CAL_SCAL_8197F) +#define BIT_SET_CAL_SCAL_8197F(x, v) \ + (BIT_CLEAR_CAL_SCAL_8197F(x) | BIT_CAL_SCAL_8197F(v)) /* 2 REG_ACLK_MON_8197F */ #define BIT_SHIFT_RCLK_MON_8197F 5 #define BIT_MASK_RCLK_MON_8197F 0x7ff -#define BIT_RCLK_MON_8197F(x) (((x) & BIT_MASK_RCLK_MON_8197F) << BIT_SHIFT_RCLK_MON_8197F) -#define BITS_RCLK_MON_8197F (BIT_MASK_RCLK_MON_8197F << BIT_SHIFT_RCLK_MON_8197F) +#define BIT_RCLK_MON_8197F(x) \ + (((x) & BIT_MASK_RCLK_MON_8197F) << BIT_SHIFT_RCLK_MON_8197F) +#define BITS_RCLK_MON_8197F \ + (BIT_MASK_RCLK_MON_8197F << BIT_SHIFT_RCLK_MON_8197F) #define BIT_CLEAR_RCLK_MON_8197F(x) ((x) & (~BITS_RCLK_MON_8197F)) -#define BIT_GET_RCLK_MON_8197F(x) (((x) >> BIT_SHIFT_RCLK_MON_8197F) & BIT_MASK_RCLK_MON_8197F) -#define BIT_SET_RCLK_MON_8197F(x, v) (BIT_CLEAR_RCLK_MON_8197F(x) | BIT_RCLK_MON_8197F(v)) +#define BIT_GET_RCLK_MON_8197F(x) \ + (((x) >> BIT_SHIFT_RCLK_MON_8197F) & BIT_MASK_RCLK_MON_8197F) +#define BIT_SET_RCLK_MON_8197F(x, v) \ + (BIT_CLEAR_RCLK_MON_8197F(x) | BIT_RCLK_MON_8197F(v)) #define BIT_CAL_EN_8197F BIT(4) #define BIT_SHIFT_DPSTU_8197F 2 #define BIT_MASK_DPSTU_8197F 0x3 -#define BIT_DPSTU_8197F(x) (((x) & BIT_MASK_DPSTU_8197F) << BIT_SHIFT_DPSTU_8197F) +#define BIT_DPSTU_8197F(x) \ + (((x) & BIT_MASK_DPSTU_8197F) << BIT_SHIFT_DPSTU_8197F) #define BITS_DPSTU_8197F (BIT_MASK_DPSTU_8197F << BIT_SHIFT_DPSTU_8197F) #define BIT_CLEAR_DPSTU_8197F(x) ((x) & (~BITS_DPSTU_8197F)) -#define BIT_GET_DPSTU_8197F(x) (((x) >> BIT_SHIFT_DPSTU_8197F) & BIT_MASK_DPSTU_8197F) -#define BIT_SET_DPSTU_8197F(x, v) (BIT_CLEAR_DPSTU_8197F(x) | BIT_DPSTU_8197F(v)) +#define BIT_GET_DPSTU_8197F(x) \ + (((x) >> BIT_SHIFT_DPSTU_8197F) & BIT_MASK_DPSTU_8197F) +#define BIT_SET_DPSTU_8197F(x, v) \ + (BIT_CLEAR_DPSTU_8197F(x) | BIT_DPSTU_8197F(v)) #define BIT_SUS_16X_8197F BIT(1) @@ -674,11 +838,15 @@ #define BIT_SHIFT_PIN_USECASE_8197F 24 #define BIT_MASK_PIN_USECASE_8197F 0xf -#define BIT_PIN_USECASE_8197F(x) (((x) & BIT_MASK_PIN_USECASE_8197F) << BIT_SHIFT_PIN_USECASE_8197F) -#define BITS_PIN_USECASE_8197F (BIT_MASK_PIN_USECASE_8197F << BIT_SHIFT_PIN_USECASE_8197F) +#define BIT_PIN_USECASE_8197F(x) \ + (((x) & BIT_MASK_PIN_USECASE_8197F) << BIT_SHIFT_PIN_USECASE_8197F) +#define BITS_PIN_USECASE_8197F \ + (BIT_MASK_PIN_USECASE_8197F << BIT_SHIFT_PIN_USECASE_8197F) #define BIT_CLEAR_PIN_USECASE_8197F(x) ((x) & (~BITS_PIN_USECASE_8197F)) -#define BIT_GET_PIN_USECASE_8197F(x) (((x) >> BIT_SHIFT_PIN_USECASE_8197F) & BIT_MASK_PIN_USECASE_8197F) -#define BIT_SET_PIN_USECASE_8197F(x, v) (BIT_CLEAR_PIN_USECASE_8197F(x) | BIT_PIN_USECASE_8197F(v)) +#define BIT_GET_PIN_USECASE_8197F(x) \ + (((x) >> BIT_SHIFT_PIN_USECASE_8197F) & BIT_MASK_PIN_USECASE_8197F) +#define BIT_SET_PIN_USECASE_8197F(x, v) \ + (BIT_CLEAR_PIN_USECASE_8197F(x) | BIT_PIN_USECASE_8197F(v)) #define BIT_FSPI_EN_8197F BIT(19) #define BIT_WL_RTS_EXT_32K_SEL_8197F BIT(18) @@ -694,11 +862,14 @@ #define BIT_SHIFT_BTMODE_8197F 6 #define BIT_MASK_BTMODE_8197F 0x3 -#define BIT_BTMODE_8197F(x) (((x) & BIT_MASK_BTMODE_8197F) << BIT_SHIFT_BTMODE_8197F) +#define BIT_BTMODE_8197F(x) \ + (((x) & BIT_MASK_BTMODE_8197F) << BIT_SHIFT_BTMODE_8197F) #define BITS_BTMODE_8197F (BIT_MASK_BTMODE_8197F << BIT_SHIFT_BTMODE_8197F) #define BIT_CLEAR_BTMODE_8197F(x) ((x) & (~BITS_BTMODE_8197F)) -#define BIT_GET_BTMODE_8197F(x) (((x) >> BIT_SHIFT_BTMODE_8197F) & BIT_MASK_BTMODE_8197F) -#define BIT_SET_BTMODE_8197F(x, v) (BIT_CLEAR_BTMODE_8197F(x) | BIT_BTMODE_8197F(v)) +#define BIT_GET_BTMODE_8197F(x) \ + (((x) >> BIT_SHIFT_BTMODE_8197F) & BIT_MASK_BTMODE_8197F) +#define BIT_SET_BTMODE_8197F(x, v) \ + (BIT_CLEAR_BTMODE_8197F(x) | BIT_BTMODE_8197F(v)) #define BIT_ENBT_8197F BIT(5) #define BIT_EROM_EN_8197F BIT(4) @@ -707,60 +878,89 @@ #define BIT_SHIFT_GPIOSEL_8197F 0 #define BIT_MASK_GPIOSEL_8197F 0x3 -#define BIT_GPIOSEL_8197F(x) (((x) & BIT_MASK_GPIOSEL_8197F) << BIT_SHIFT_GPIOSEL_8197F) +#define BIT_GPIOSEL_8197F(x) \ + (((x) & BIT_MASK_GPIOSEL_8197F) << BIT_SHIFT_GPIOSEL_8197F) #define BITS_GPIOSEL_8197F (BIT_MASK_GPIOSEL_8197F << BIT_SHIFT_GPIOSEL_8197F) #define BIT_CLEAR_GPIOSEL_8197F(x) ((x) & (~BITS_GPIOSEL_8197F)) -#define BIT_GET_GPIOSEL_8197F(x) (((x) >> BIT_SHIFT_GPIOSEL_8197F) & BIT_MASK_GPIOSEL_8197F) -#define BIT_SET_GPIOSEL_8197F(x, v) (BIT_CLEAR_GPIOSEL_8197F(x) | BIT_GPIOSEL_8197F(v)) - +#define BIT_GET_GPIOSEL_8197F(x) \ + (((x) >> BIT_SHIFT_GPIOSEL_8197F) & BIT_MASK_GPIOSEL_8197F) +#define BIT_SET_GPIOSEL_8197F(x, v) \ + (BIT_CLEAR_GPIOSEL_8197F(x) | BIT_GPIOSEL_8197F(v)) /* 2 REG_GPIO_PIN_CTRL_8197F */ #define BIT_SHIFT_GPIO_MOD_7_TO_0_8197F 24 #define BIT_MASK_GPIO_MOD_7_TO_0_8197F 0xff -#define BIT_GPIO_MOD_7_TO_0_8197F(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8197F) << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) -#define BITS_GPIO_MOD_7_TO_0_8197F (BIT_MASK_GPIO_MOD_7_TO_0_8197F << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) +#define BIT_GPIO_MOD_7_TO_0_8197F(x) \ + (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8197F) \ + << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) +#define BITS_GPIO_MOD_7_TO_0_8197F \ + (BIT_MASK_GPIO_MOD_7_TO_0_8197F << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) #define BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8197F)) -#define BIT_GET_GPIO_MOD_7_TO_0_8197F(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) & BIT_MASK_GPIO_MOD_7_TO_0_8197F) -#define BIT_SET_GPIO_MOD_7_TO_0_8197F(x, v) (BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) | BIT_GPIO_MOD_7_TO_0_8197F(v)) - +#define BIT_GET_GPIO_MOD_7_TO_0_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) & \ + BIT_MASK_GPIO_MOD_7_TO_0_8197F) +#define BIT_SET_GPIO_MOD_7_TO_0_8197F(x, v) \ + (BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) | BIT_GPIO_MOD_7_TO_0_8197F(v)) #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F 16 #define BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F 0xff -#define BIT_GPIO_IO_SEL_7_TO_0_8197F(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) -#define BITS_GPIO_IO_SEL_7_TO_0_8197F (BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) -#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8197F)) -#define BIT_GET_GPIO_IO_SEL_7_TO_0_8197F(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F) -#define BIT_SET_GPIO_IO_SEL_7_TO_0_8197F(x, v) (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) | BIT_GPIO_IO_SEL_7_TO_0_8197F(v)) - +#define BIT_GPIO_IO_SEL_7_TO_0_8197F(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F) \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) +#define BITS_GPIO_IO_SEL_7_TO_0_8197F \ + (BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) \ + ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8197F)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) & \ + BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F) +#define BIT_SET_GPIO_IO_SEL_7_TO_0_8197F(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) | \ + BIT_GPIO_IO_SEL_7_TO_0_8197F(v)) #define BIT_SHIFT_GPIO_OUT_7_TO_0_8197F 8 #define BIT_MASK_GPIO_OUT_7_TO_0_8197F 0xff -#define BIT_GPIO_OUT_7_TO_0_8197F(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8197F) << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) -#define BITS_GPIO_OUT_7_TO_0_8197F (BIT_MASK_GPIO_OUT_7_TO_0_8197F << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) +#define BIT_GPIO_OUT_7_TO_0_8197F(x) \ + (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8197F) \ + << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) +#define BITS_GPIO_OUT_7_TO_0_8197F \ + (BIT_MASK_GPIO_OUT_7_TO_0_8197F << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) #define BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8197F)) -#define BIT_GET_GPIO_OUT_7_TO_0_8197F(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) & BIT_MASK_GPIO_OUT_7_TO_0_8197F) -#define BIT_SET_GPIO_OUT_7_TO_0_8197F(x, v) (BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) | BIT_GPIO_OUT_7_TO_0_8197F(v)) - +#define BIT_GET_GPIO_OUT_7_TO_0_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) & \ + BIT_MASK_GPIO_OUT_7_TO_0_8197F) +#define BIT_SET_GPIO_OUT_7_TO_0_8197F(x, v) \ + (BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) | BIT_GPIO_OUT_7_TO_0_8197F(v)) #define BIT_SHIFT_GPIO_IN_7_TO_0_8197F 0 #define BIT_MASK_GPIO_IN_7_TO_0_8197F 0xff -#define BIT_GPIO_IN_7_TO_0_8197F(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8197F) << BIT_SHIFT_GPIO_IN_7_TO_0_8197F) -#define BITS_GPIO_IN_7_TO_0_8197F (BIT_MASK_GPIO_IN_7_TO_0_8197F << BIT_SHIFT_GPIO_IN_7_TO_0_8197F) +#define BIT_GPIO_IN_7_TO_0_8197F(x) \ + (((x) & BIT_MASK_GPIO_IN_7_TO_0_8197F) \ + << BIT_SHIFT_GPIO_IN_7_TO_0_8197F) +#define BITS_GPIO_IN_7_TO_0_8197F \ + (BIT_MASK_GPIO_IN_7_TO_0_8197F << BIT_SHIFT_GPIO_IN_7_TO_0_8197F) #define BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8197F)) -#define BIT_GET_GPIO_IN_7_TO_0_8197F(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8197F) & BIT_MASK_GPIO_IN_7_TO_0_8197F) -#define BIT_SET_GPIO_IN_7_TO_0_8197F(x, v) (BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) | BIT_GPIO_IN_7_TO_0_8197F(v)) - +#define BIT_GET_GPIO_IN_7_TO_0_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8197F) & \ + BIT_MASK_GPIO_IN_7_TO_0_8197F) +#define BIT_SET_GPIO_IN_7_TO_0_8197F(x, v) \ + (BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) | BIT_GPIO_IN_7_TO_0_8197F(v)) /* 2 REG_GPIO_INTM_8197F */ #define BIT_SHIFT_MUXDBG_SEL_8197F 30 #define BIT_MASK_MUXDBG_SEL_8197F 0x3 -#define BIT_MUXDBG_SEL_8197F(x) (((x) & BIT_MASK_MUXDBG_SEL_8197F) << BIT_SHIFT_MUXDBG_SEL_8197F) -#define BITS_MUXDBG_SEL_8197F (BIT_MASK_MUXDBG_SEL_8197F << BIT_SHIFT_MUXDBG_SEL_8197F) +#define BIT_MUXDBG_SEL_8197F(x) \ + (((x) & BIT_MASK_MUXDBG_SEL_8197F) << BIT_SHIFT_MUXDBG_SEL_8197F) +#define BITS_MUXDBG_SEL_8197F \ + (BIT_MASK_MUXDBG_SEL_8197F << BIT_SHIFT_MUXDBG_SEL_8197F) #define BIT_CLEAR_MUXDBG_SEL_8197F(x) ((x) & (~BITS_MUXDBG_SEL_8197F)) -#define BIT_GET_MUXDBG_SEL_8197F(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8197F) & BIT_MASK_MUXDBG_SEL_8197F) -#define BIT_SET_MUXDBG_SEL_8197F(x, v) (BIT_CLEAR_MUXDBG_SEL_8197F(x) | BIT_MUXDBG_SEL_8197F(v)) +#define BIT_GET_MUXDBG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL_8197F) & BIT_MASK_MUXDBG_SEL_8197F) +#define BIT_SET_MUXDBG_SEL_8197F(x, v) \ + (BIT_CLEAR_MUXDBG_SEL_8197F(x) | BIT_MUXDBG_SEL_8197F(v)) #define BIT_EXTWOL_SEL_8197F BIT(17) #define BIT_EXTWOL_EN_8197F BIT(16) @@ -793,11 +993,14 @@ #define BIT_SHIFT_LED2CM_8197F 16 #define BIT_MASK_LED2CM_8197F 0x7 -#define BIT_LED2CM_8197F(x) (((x) & BIT_MASK_LED2CM_8197F) << BIT_SHIFT_LED2CM_8197F) +#define BIT_LED2CM_8197F(x) \ + (((x) & BIT_MASK_LED2CM_8197F) << BIT_SHIFT_LED2CM_8197F) #define BITS_LED2CM_8197F (BIT_MASK_LED2CM_8197F << BIT_SHIFT_LED2CM_8197F) #define BIT_CLEAR_LED2CM_8197F(x) ((x) & (~BITS_LED2CM_8197F)) -#define BIT_GET_LED2CM_8197F(x) (((x) >> BIT_SHIFT_LED2CM_8197F) & BIT_MASK_LED2CM_8197F) -#define BIT_SET_LED2CM_8197F(x, v) (BIT_CLEAR_LED2CM_8197F(x) | BIT_LED2CM_8197F(v)) +#define BIT_GET_LED2CM_8197F(x) \ + (((x) >> BIT_SHIFT_LED2CM_8197F) & BIT_MASK_LED2CM_8197F) +#define BIT_SET_LED2CM_8197F(x, v) \ + (BIT_CLEAR_LED2CM_8197F(x) | BIT_LED2CM_8197F(v)) #define BIT_LED1DIS_8197F BIT(15) #define BIT_LED1PL_8197F BIT(12) @@ -805,33 +1008,45 @@ #define BIT_SHIFT_LED1CM_8197F 8 #define BIT_MASK_LED1CM_8197F 0x7 -#define BIT_LED1CM_8197F(x) (((x) & BIT_MASK_LED1CM_8197F) << BIT_SHIFT_LED1CM_8197F) +#define BIT_LED1CM_8197F(x) \ + (((x) & BIT_MASK_LED1CM_8197F) << BIT_SHIFT_LED1CM_8197F) #define BITS_LED1CM_8197F (BIT_MASK_LED1CM_8197F << BIT_SHIFT_LED1CM_8197F) #define BIT_CLEAR_LED1CM_8197F(x) ((x) & (~BITS_LED1CM_8197F)) -#define BIT_GET_LED1CM_8197F(x) (((x) >> BIT_SHIFT_LED1CM_8197F) & BIT_MASK_LED1CM_8197F) -#define BIT_SET_LED1CM_8197F(x, v) (BIT_CLEAR_LED1CM_8197F(x) | BIT_LED1CM_8197F(v)) +#define BIT_GET_LED1CM_8197F(x) \ + (((x) >> BIT_SHIFT_LED1CM_8197F) & BIT_MASK_LED1CM_8197F) +#define BIT_SET_LED1CM_8197F(x, v) \ + (BIT_CLEAR_LED1CM_8197F(x) | BIT_LED1CM_8197F(v)) #define BIT_LED0DIS_8197F BIT(7) #define BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F 5 #define BIT_MASK_AFE_LDO_SWR_CHECK_8197F 0x3 -#define BIT_AFE_LDO_SWR_CHECK_8197F(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8197F) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) -#define BITS_AFE_LDO_SWR_CHECK_8197F (BIT_MASK_AFE_LDO_SWR_CHECK_8197F << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) -#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) ((x) & (~BITS_AFE_LDO_SWR_CHECK_8197F)) -#define BIT_GET_AFE_LDO_SWR_CHECK_8197F(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) & BIT_MASK_AFE_LDO_SWR_CHECK_8197F) -#define BIT_SET_AFE_LDO_SWR_CHECK_8197F(x, v) (BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) | BIT_AFE_LDO_SWR_CHECK_8197F(v)) +#define BIT_AFE_LDO_SWR_CHECK_8197F(x) \ + (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8197F) \ + << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) +#define BITS_AFE_LDO_SWR_CHECK_8197F \ + (BIT_MASK_AFE_LDO_SWR_CHECK_8197F << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) \ + ((x) & (~BITS_AFE_LDO_SWR_CHECK_8197F)) +#define BIT_GET_AFE_LDO_SWR_CHECK_8197F(x) \ + (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) & \ + BIT_MASK_AFE_LDO_SWR_CHECK_8197F) +#define BIT_SET_AFE_LDO_SWR_CHECK_8197F(x, v) \ + (BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) | BIT_AFE_LDO_SWR_CHECK_8197F(v)) #define BIT_LED0PL_8197F BIT(4) #define BIT_LED0SV_8197F BIT(3) #define BIT_SHIFT_LED0CM_8197F 0 #define BIT_MASK_LED0CM_8197F 0x7 -#define BIT_LED0CM_8197F(x) (((x) & BIT_MASK_LED0CM_8197F) << BIT_SHIFT_LED0CM_8197F) +#define BIT_LED0CM_8197F(x) \ + (((x) & BIT_MASK_LED0CM_8197F) << BIT_SHIFT_LED0CM_8197F) #define BITS_LED0CM_8197F (BIT_MASK_LED0CM_8197F << BIT_SHIFT_LED0CM_8197F) #define BIT_CLEAR_LED0CM_8197F(x) ((x) & (~BITS_LED0CM_8197F)) -#define BIT_GET_LED0CM_8197F(x) (((x) >> BIT_SHIFT_LED0CM_8197F) & BIT_MASK_LED0CM_8197F) -#define BIT_SET_LED0CM_8197F(x, v) (BIT_CLEAR_LED0CM_8197F(x) | BIT_LED0CM_8197F(v)) - +#define BIT_GET_LED0CM_8197F(x) \ + (((x) >> BIT_SHIFT_LED0CM_8197F) & BIT_MASK_LED0CM_8197F) +#define BIT_SET_LED0CM_8197F(x, v) \ + (BIT_CLEAR_LED0CM_8197F(x) | BIT_LED0CM_8197F(v)) /* 2 REG_FSIMR_8197F */ #define BIT_FS_PDNINT_EN_8197F BIT(31) @@ -950,39 +1165,64 @@ #define BIT_SHIFT_GPIO_MOD_15_TO_8_8197F 24 #define BIT_MASK_GPIO_MOD_15_TO_8_8197F 0xff -#define BIT_GPIO_MOD_15_TO_8_8197F(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8197F) << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) -#define BITS_GPIO_MOD_15_TO_8_8197F (BIT_MASK_GPIO_MOD_15_TO_8_8197F << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) -#define BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_MOD_15_TO_8_8197F)) -#define BIT_GET_GPIO_MOD_15_TO_8_8197F(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) & BIT_MASK_GPIO_MOD_15_TO_8_8197F) -#define BIT_SET_GPIO_MOD_15_TO_8_8197F(x, v) (BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) | BIT_GPIO_MOD_15_TO_8_8197F(v)) - +#define BIT_GPIO_MOD_15_TO_8_8197F(x) \ + (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8197F) \ + << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) +#define BITS_GPIO_MOD_15_TO_8_8197F \ + (BIT_MASK_GPIO_MOD_15_TO_8_8197F << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) +#define BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) \ + ((x) & (~BITS_GPIO_MOD_15_TO_8_8197F)) +#define BIT_GET_GPIO_MOD_15_TO_8_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) & \ + BIT_MASK_GPIO_MOD_15_TO_8_8197F) +#define BIT_SET_GPIO_MOD_15_TO_8_8197F(x, v) \ + (BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) | BIT_GPIO_MOD_15_TO_8_8197F(v)) #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F 16 #define BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F 0xff -#define BIT_GPIO_IO_SEL_15_TO_8_8197F(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) -#define BITS_GPIO_IO_SEL_15_TO_8_8197F (BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) -#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8197F)) -#define BIT_GET_GPIO_IO_SEL_15_TO_8_8197F(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F) -#define BIT_SET_GPIO_IO_SEL_15_TO_8_8197F(x, v) (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) | BIT_GPIO_IO_SEL_15_TO_8_8197F(v)) - +#define BIT_GPIO_IO_SEL_15_TO_8_8197F(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F) \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) +#define BITS_GPIO_IO_SEL_15_TO_8_8197F \ + (BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) \ + ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8197F)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) & \ + BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F) +#define BIT_SET_GPIO_IO_SEL_15_TO_8_8197F(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) | \ + BIT_GPIO_IO_SEL_15_TO_8_8197F(v)) #define BIT_SHIFT_GPIO_OUT_15_TO_8_8197F 8 #define BIT_MASK_GPIO_OUT_15_TO_8_8197F 0xff -#define BIT_GPIO_OUT_15_TO_8_8197F(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8197F) << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) -#define BITS_GPIO_OUT_15_TO_8_8197F (BIT_MASK_GPIO_OUT_15_TO_8_8197F << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) -#define BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_OUT_15_TO_8_8197F)) -#define BIT_GET_GPIO_OUT_15_TO_8_8197F(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) & BIT_MASK_GPIO_OUT_15_TO_8_8197F) -#define BIT_SET_GPIO_OUT_15_TO_8_8197F(x, v) (BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) | BIT_GPIO_OUT_15_TO_8_8197F(v)) - +#define BIT_GPIO_OUT_15_TO_8_8197F(x) \ + (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8197F) \ + << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) +#define BITS_GPIO_OUT_15_TO_8_8197F \ + (BIT_MASK_GPIO_OUT_15_TO_8_8197F << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) +#define BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) \ + ((x) & (~BITS_GPIO_OUT_15_TO_8_8197F)) +#define BIT_GET_GPIO_OUT_15_TO_8_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) & \ + BIT_MASK_GPIO_OUT_15_TO_8_8197F) +#define BIT_SET_GPIO_OUT_15_TO_8_8197F(x, v) \ + (BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) | BIT_GPIO_OUT_15_TO_8_8197F(v)) #define BIT_SHIFT_GPIO_IN_15_TO_8_8197F 0 #define BIT_MASK_GPIO_IN_15_TO_8_8197F 0xff -#define BIT_GPIO_IN_15_TO_8_8197F(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8197F) << BIT_SHIFT_GPIO_IN_15_TO_8_8197F) -#define BITS_GPIO_IN_15_TO_8_8197F (BIT_MASK_GPIO_IN_15_TO_8_8197F << BIT_SHIFT_GPIO_IN_15_TO_8_8197F) +#define BIT_GPIO_IN_15_TO_8_8197F(x) \ + (((x) & BIT_MASK_GPIO_IN_15_TO_8_8197F) \ + << BIT_SHIFT_GPIO_IN_15_TO_8_8197F) +#define BITS_GPIO_IN_15_TO_8_8197F \ + (BIT_MASK_GPIO_IN_15_TO_8_8197F << BIT_SHIFT_GPIO_IN_15_TO_8_8197F) #define BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8197F)) -#define BIT_GET_GPIO_IN_15_TO_8_8197F(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8197F) & BIT_MASK_GPIO_IN_15_TO_8_8197F) -#define BIT_SET_GPIO_IN_15_TO_8_8197F(x, v) (BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) | BIT_GPIO_IN_15_TO_8_8197F(v)) - +#define BIT_GET_GPIO_IN_15_TO_8_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8197F) & \ + BIT_MASK_GPIO_IN_15_TO_8_8197F) +#define BIT_SET_GPIO_IN_15_TO_8_8197F(x, v) \ + (BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) | BIT_GPIO_IN_15_TO_8_8197F(v)) /* 2 REG_PAD_CTRL1_8197F */ #define BIT_PAPE_WLBT_SEL_8197F BIT(29) @@ -999,11 +1239,15 @@ #define BIT_SHIFT_BTGP_GPIO_SL_8197F 16 #define BIT_MASK_BTGP_GPIO_SL_8197F 0x3 -#define BIT_BTGP_GPIO_SL_8197F(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8197F) << BIT_SHIFT_BTGP_GPIO_SL_8197F) -#define BITS_BTGP_GPIO_SL_8197F (BIT_MASK_BTGP_GPIO_SL_8197F << BIT_SHIFT_BTGP_GPIO_SL_8197F) +#define BIT_BTGP_GPIO_SL_8197F(x) \ + (((x) & BIT_MASK_BTGP_GPIO_SL_8197F) << BIT_SHIFT_BTGP_GPIO_SL_8197F) +#define BITS_BTGP_GPIO_SL_8197F \ + (BIT_MASK_BTGP_GPIO_SL_8197F << BIT_SHIFT_BTGP_GPIO_SL_8197F) #define BIT_CLEAR_BTGP_GPIO_SL_8197F(x) ((x) & (~BITS_BTGP_GPIO_SL_8197F)) -#define BIT_GET_BTGP_GPIO_SL_8197F(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8197F) & BIT_MASK_BTGP_GPIO_SL_8197F) -#define BIT_SET_BTGP_GPIO_SL_8197F(x, v) (BIT_CLEAR_BTGP_GPIO_SL_8197F(x) | BIT_BTGP_GPIO_SL_8197F(v)) +#define BIT_GET_BTGP_GPIO_SL_8197F(x) \ + (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8197F) & BIT_MASK_BTGP_GPIO_SL_8197F) +#define BIT_SET_BTGP_GPIO_SL_8197F(x, v) \ + (BIT_CLEAR_BTGP_GPIO_SL_8197F(x) | BIT_BTGP_GPIO_SL_8197F(v)) #define BIT_PAD_SDIO_SR_8197F BIT(14) #define BIT_GPIO14_OUTPUT_PL_8197F BIT(13) @@ -1054,12 +1298,15 @@ #define BIT_SHIFT_WLCLK_PHASE_8197F 0 #define BIT_MASK_WLCLK_PHASE_8197F 0x1f -#define BIT_WLCLK_PHASE_8197F(x) (((x) & BIT_MASK_WLCLK_PHASE_8197F) << BIT_SHIFT_WLCLK_PHASE_8197F) -#define BITS_WLCLK_PHASE_8197F (BIT_MASK_WLCLK_PHASE_8197F << BIT_SHIFT_WLCLK_PHASE_8197F) +#define BIT_WLCLK_PHASE_8197F(x) \ + (((x) & BIT_MASK_WLCLK_PHASE_8197F) << BIT_SHIFT_WLCLK_PHASE_8197F) +#define BITS_WLCLK_PHASE_8197F \ + (BIT_MASK_WLCLK_PHASE_8197F << BIT_SHIFT_WLCLK_PHASE_8197F) #define BIT_CLEAR_WLCLK_PHASE_8197F(x) ((x) & (~BITS_WLCLK_PHASE_8197F)) -#define BIT_GET_WLCLK_PHASE_8197F(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8197F) & BIT_MASK_WLCLK_PHASE_8197F) -#define BIT_SET_WLCLK_PHASE_8197F(x, v) (BIT_CLEAR_WLCLK_PHASE_8197F(x) | BIT_WLCLK_PHASE_8197F(v)) - +#define BIT_GET_WLCLK_PHASE_8197F(x) \ + (((x) >> BIT_SHIFT_WLCLK_PHASE_8197F) & BIT_MASK_WLCLK_PHASE_8197F) +#define BIT_SET_WLCLK_PHASE_8197F(x, v) \ + (BIT_CLEAR_WLCLK_PHASE_8197F(x) | BIT_WLCLK_PHASE_8197F(v)) /* 2 REG_SYS_SDIO_CTRL_8197F */ #define BIT_DBG_GNT_WL_BT_8197F BIT(27) @@ -1078,11 +1325,15 @@ #define BIT_SHIFT_SDIO_PAD_E_8197F 5 #define BIT_MASK_SDIO_PAD_E_8197F 0x7 -#define BIT_SDIO_PAD_E_8197F(x) (((x) & BIT_MASK_SDIO_PAD_E_8197F) << BIT_SHIFT_SDIO_PAD_E_8197F) -#define BITS_SDIO_PAD_E_8197F (BIT_MASK_SDIO_PAD_E_8197F << BIT_SHIFT_SDIO_PAD_E_8197F) +#define BIT_SDIO_PAD_E_8197F(x) \ + (((x) & BIT_MASK_SDIO_PAD_E_8197F) << BIT_SHIFT_SDIO_PAD_E_8197F) +#define BITS_SDIO_PAD_E_8197F \ + (BIT_MASK_SDIO_PAD_E_8197F << BIT_SHIFT_SDIO_PAD_E_8197F) #define BIT_CLEAR_SDIO_PAD_E_8197F(x) ((x) & (~BITS_SDIO_PAD_E_8197F)) -#define BIT_GET_SDIO_PAD_E_8197F(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8197F) & BIT_MASK_SDIO_PAD_E_8197F) -#define BIT_SET_SDIO_PAD_E_8197F(x, v) (BIT_CLEAR_SDIO_PAD_E_8197F(x) | BIT_SDIO_PAD_E_8197F(v)) +#define BIT_GET_SDIO_PAD_E_8197F(x) \ + (((x) >> BIT_SHIFT_SDIO_PAD_E_8197F) & BIT_MASK_SDIO_PAD_E_8197F) +#define BIT_SET_SDIO_PAD_E_8197F(x, v) \ + (BIT_CLEAR_SDIO_PAD_E_8197F(x) | BIT_SDIO_PAD_E_8197F(v)) #define BIT_USB_LPPLL_EN_8197F BIT(4) #define BIT_ROP_SW15_8197F BIT(2) @@ -1096,11 +1347,15 @@ #define BIT_SHIFT_XTAL_LDO_8197F 20 #define BIT_MASK_XTAL_LDO_8197F 0x7 -#define BIT_XTAL_LDO_8197F(x) (((x) & BIT_MASK_XTAL_LDO_8197F) << BIT_SHIFT_XTAL_LDO_8197F) -#define BITS_XTAL_LDO_8197F (BIT_MASK_XTAL_LDO_8197F << BIT_SHIFT_XTAL_LDO_8197F) +#define BIT_XTAL_LDO_8197F(x) \ + (((x) & BIT_MASK_XTAL_LDO_8197F) << BIT_SHIFT_XTAL_LDO_8197F) +#define BITS_XTAL_LDO_8197F \ + (BIT_MASK_XTAL_LDO_8197F << BIT_SHIFT_XTAL_LDO_8197F) #define BIT_CLEAR_XTAL_LDO_8197F(x) ((x) & (~BITS_XTAL_LDO_8197F)) -#define BIT_GET_XTAL_LDO_8197F(x) (((x) >> BIT_SHIFT_XTAL_LDO_8197F) & BIT_MASK_XTAL_LDO_8197F) -#define BIT_SET_XTAL_LDO_8197F(x, v) (BIT_CLEAR_XTAL_LDO_8197F(x) | BIT_XTAL_LDO_8197F(v)) +#define BIT_GET_XTAL_LDO_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_8197F) & BIT_MASK_XTAL_LDO_8197F) +#define BIT_SET_XTAL_LDO_8197F(x, v) \ + (BIT_CLEAR_XTAL_LDO_8197F(x) | BIT_XTAL_LDO_8197F(v)) #define BIT_ADC_CK_SYNC_EN_8197F BIT(16) @@ -1149,7 +1404,8 @@ #define BIT_RPWM_8197F(x) (((x) & BIT_MASK_RPWM_8197F) << BIT_SHIFT_RPWM_8197F) #define BITS_RPWM_8197F (BIT_MASK_RPWM_8197F << BIT_SHIFT_RPWM_8197F) #define BIT_CLEAR_RPWM_8197F(x) ((x) & (~BITS_RPWM_8197F)) -#define BIT_GET_RPWM_8197F(x) (((x) >> BIT_SHIFT_RPWM_8197F) & BIT_MASK_RPWM_8197F) +#define BIT_GET_RPWM_8197F(x) \ + (((x) >> BIT_SHIFT_RPWM_8197F) & BIT_MASK_RPWM_8197F) #define BIT_SET_RPWM_8197F(x, v) (BIT_CLEAR_RPWM_8197F(x) | BIT_RPWM_8197F(v)) #define BIT_CPRST_8197F BIT(23) @@ -1160,22 +1416,29 @@ #define BIT_SHIFT_ROM_PGE_8197F 16 #define BIT_MASK_ROM_PGE_8197F 0x7 -#define BIT_ROM_PGE_8197F(x) (((x) & BIT_MASK_ROM_PGE_8197F) << BIT_SHIFT_ROM_PGE_8197F) +#define BIT_ROM_PGE_8197F(x) \ + (((x) & BIT_MASK_ROM_PGE_8197F) << BIT_SHIFT_ROM_PGE_8197F) #define BITS_ROM_PGE_8197F (BIT_MASK_ROM_PGE_8197F << BIT_SHIFT_ROM_PGE_8197F) #define BIT_CLEAR_ROM_PGE_8197F(x) ((x) & (~BITS_ROM_PGE_8197F)) -#define BIT_GET_ROM_PGE_8197F(x) (((x) >> BIT_SHIFT_ROM_PGE_8197F) & BIT_MASK_ROM_PGE_8197F) -#define BIT_SET_ROM_PGE_8197F(x, v) (BIT_CLEAR_ROM_PGE_8197F(x) | BIT_ROM_PGE_8197F(v)) +#define BIT_GET_ROM_PGE_8197F(x) \ + (((x) >> BIT_SHIFT_ROM_PGE_8197F) & BIT_MASK_ROM_PGE_8197F) +#define BIT_SET_ROM_PGE_8197F(x, v) \ + (BIT_CLEAR_ROM_PGE_8197F(x) | BIT_ROM_PGE_8197F(v)) #define BIT_FW_INIT_RDY_8197F BIT(15) #define BIT_FW_DW_RDY_8197F BIT(14) #define BIT_SHIFT_CPU_CLK_SEL_8197F 12 #define BIT_MASK_CPU_CLK_SEL_8197F 0x3 -#define BIT_CPU_CLK_SEL_8197F(x) (((x) & BIT_MASK_CPU_CLK_SEL_8197F) << BIT_SHIFT_CPU_CLK_SEL_8197F) -#define BITS_CPU_CLK_SEL_8197F (BIT_MASK_CPU_CLK_SEL_8197F << BIT_SHIFT_CPU_CLK_SEL_8197F) +#define BIT_CPU_CLK_SEL_8197F(x) \ + (((x) & BIT_MASK_CPU_CLK_SEL_8197F) << BIT_SHIFT_CPU_CLK_SEL_8197F) +#define BITS_CPU_CLK_SEL_8197F \ + (BIT_MASK_CPU_CLK_SEL_8197F << BIT_SHIFT_CPU_CLK_SEL_8197F) #define BIT_CLEAR_CPU_CLK_SEL_8197F(x) ((x) & (~BITS_CPU_CLK_SEL_8197F)) -#define BIT_GET_CPU_CLK_SEL_8197F(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8197F) & BIT_MASK_CPU_CLK_SEL_8197F) -#define BIT_SET_CPU_CLK_SEL_8197F(x, v) (BIT_CLEAR_CPU_CLK_SEL_8197F(x) | BIT_CPU_CLK_SEL_8197F(v)) +#define BIT_GET_CPU_CLK_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_CPU_CLK_SEL_8197F) & BIT_MASK_CPU_CLK_SEL_8197F) +#define BIT_SET_CPU_CLK_SEL_8197F(x, v) \ + (BIT_CLEAR_CPU_CLK_SEL_8197F(x) | BIT_CPU_CLK_SEL_8197F(v)) #define BIT_CCLK_CHG_MASK_8197F BIT(11) #define BIT_FW_INIT_RDY_V1_8197F BIT(10) @@ -1193,52 +1456,66 @@ #define BIT_SHIFT_LBKTST_8197F 0 #define BIT_MASK_LBKTST_8197F 0xffff -#define BIT_LBKTST_8197F(x) (((x) & BIT_MASK_LBKTST_8197F) << BIT_SHIFT_LBKTST_8197F) +#define BIT_LBKTST_8197F(x) \ + (((x) & BIT_MASK_LBKTST_8197F) << BIT_SHIFT_LBKTST_8197F) #define BITS_LBKTST_8197F (BIT_MASK_LBKTST_8197F << BIT_SHIFT_LBKTST_8197F) #define BIT_CLEAR_LBKTST_8197F(x) ((x) & (~BITS_LBKTST_8197F)) -#define BIT_GET_LBKTST_8197F(x) (((x) >> BIT_SHIFT_LBKTST_8197F) & BIT_MASK_LBKTST_8197F) -#define BIT_SET_LBKTST_8197F(x, v) (BIT_CLEAR_LBKTST_8197F(x) | BIT_LBKTST_8197F(v)) - +#define BIT_GET_LBKTST_8197F(x) \ + (((x) >> BIT_SHIFT_LBKTST_8197F) & BIT_MASK_LBKTST_8197F) +#define BIT_SET_LBKTST_8197F(x, v) \ + (BIT_CLEAR_LBKTST_8197F(x) | BIT_LBKTST_8197F(v)) /* 2 REG_HMEBOX_E0_E1_8197F */ #define BIT_SHIFT_HOST_MSG_E1_8197F 16 #define BIT_MASK_HOST_MSG_E1_8197F 0xffff -#define BIT_HOST_MSG_E1_8197F(x) (((x) & BIT_MASK_HOST_MSG_E1_8197F) << BIT_SHIFT_HOST_MSG_E1_8197F) -#define BITS_HOST_MSG_E1_8197F (BIT_MASK_HOST_MSG_E1_8197F << BIT_SHIFT_HOST_MSG_E1_8197F) +#define BIT_HOST_MSG_E1_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_E1_8197F) << BIT_SHIFT_HOST_MSG_E1_8197F) +#define BITS_HOST_MSG_E1_8197F \ + (BIT_MASK_HOST_MSG_E1_8197F << BIT_SHIFT_HOST_MSG_E1_8197F) #define BIT_CLEAR_HOST_MSG_E1_8197F(x) ((x) & (~BITS_HOST_MSG_E1_8197F)) -#define BIT_GET_HOST_MSG_E1_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8197F) & BIT_MASK_HOST_MSG_E1_8197F) -#define BIT_SET_HOST_MSG_E1_8197F(x, v) (BIT_CLEAR_HOST_MSG_E1_8197F(x) | BIT_HOST_MSG_E1_8197F(v)) - +#define BIT_GET_HOST_MSG_E1_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E1_8197F) & BIT_MASK_HOST_MSG_E1_8197F) +#define BIT_SET_HOST_MSG_E1_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_E1_8197F(x) | BIT_HOST_MSG_E1_8197F(v)) #define BIT_SHIFT_HOST_MSG_E0_8197F 0 #define BIT_MASK_HOST_MSG_E0_8197F 0xffff -#define BIT_HOST_MSG_E0_8197F(x) (((x) & BIT_MASK_HOST_MSG_E0_8197F) << BIT_SHIFT_HOST_MSG_E0_8197F) -#define BITS_HOST_MSG_E0_8197F (BIT_MASK_HOST_MSG_E0_8197F << BIT_SHIFT_HOST_MSG_E0_8197F) +#define BIT_HOST_MSG_E0_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_E0_8197F) << BIT_SHIFT_HOST_MSG_E0_8197F) +#define BITS_HOST_MSG_E0_8197F \ + (BIT_MASK_HOST_MSG_E0_8197F << BIT_SHIFT_HOST_MSG_E0_8197F) #define BIT_CLEAR_HOST_MSG_E0_8197F(x) ((x) & (~BITS_HOST_MSG_E0_8197F)) -#define BIT_GET_HOST_MSG_E0_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8197F) & BIT_MASK_HOST_MSG_E0_8197F) -#define BIT_SET_HOST_MSG_E0_8197F(x, v) (BIT_CLEAR_HOST_MSG_E0_8197F(x) | BIT_HOST_MSG_E0_8197F(v)) - +#define BIT_GET_HOST_MSG_E0_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E0_8197F) & BIT_MASK_HOST_MSG_E0_8197F) +#define BIT_SET_HOST_MSG_E0_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_E0_8197F(x) | BIT_HOST_MSG_E0_8197F(v)) /* 2 REG_HMEBOX_E2_E3_8197F */ #define BIT_SHIFT_HOST_MSG_E3_8197F 16 #define BIT_MASK_HOST_MSG_E3_8197F 0xffff -#define BIT_HOST_MSG_E3_8197F(x) (((x) & BIT_MASK_HOST_MSG_E3_8197F) << BIT_SHIFT_HOST_MSG_E3_8197F) -#define BITS_HOST_MSG_E3_8197F (BIT_MASK_HOST_MSG_E3_8197F << BIT_SHIFT_HOST_MSG_E3_8197F) +#define BIT_HOST_MSG_E3_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_E3_8197F) << BIT_SHIFT_HOST_MSG_E3_8197F) +#define BITS_HOST_MSG_E3_8197F \ + (BIT_MASK_HOST_MSG_E3_8197F << BIT_SHIFT_HOST_MSG_E3_8197F) #define BIT_CLEAR_HOST_MSG_E3_8197F(x) ((x) & (~BITS_HOST_MSG_E3_8197F)) -#define BIT_GET_HOST_MSG_E3_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8197F) & BIT_MASK_HOST_MSG_E3_8197F) -#define BIT_SET_HOST_MSG_E3_8197F(x, v) (BIT_CLEAR_HOST_MSG_E3_8197F(x) | BIT_HOST_MSG_E3_8197F(v)) - +#define BIT_GET_HOST_MSG_E3_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E3_8197F) & BIT_MASK_HOST_MSG_E3_8197F) +#define BIT_SET_HOST_MSG_E3_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_E3_8197F(x) | BIT_HOST_MSG_E3_8197F(v)) #define BIT_SHIFT_HOST_MSG_E2_8197F 0 #define BIT_MASK_HOST_MSG_E2_8197F 0xffff -#define BIT_HOST_MSG_E2_8197F(x) (((x) & BIT_MASK_HOST_MSG_E2_8197F) << BIT_SHIFT_HOST_MSG_E2_8197F) -#define BITS_HOST_MSG_E2_8197F (BIT_MASK_HOST_MSG_E2_8197F << BIT_SHIFT_HOST_MSG_E2_8197F) +#define BIT_HOST_MSG_E2_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_E2_8197F) << BIT_SHIFT_HOST_MSG_E2_8197F) +#define BITS_HOST_MSG_E2_8197F \ + (BIT_MASK_HOST_MSG_E2_8197F << BIT_SHIFT_HOST_MSG_E2_8197F) #define BIT_CLEAR_HOST_MSG_E2_8197F(x) ((x) & (~BITS_HOST_MSG_E2_8197F)) -#define BIT_GET_HOST_MSG_E2_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8197F) & BIT_MASK_HOST_MSG_E2_8197F) -#define BIT_SET_HOST_MSG_E2_8197F(x, v) (BIT_CLEAR_HOST_MSG_E2_8197F(x) | BIT_HOST_MSG_E2_8197F(v)) - +#define BIT_GET_HOST_MSG_E2_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E2_8197F) & BIT_MASK_HOST_MSG_E2_8197F) +#define BIT_SET_HOST_MSG_E2_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_E2_8197F(x) | BIT_HOST_MSG_E2_8197F(v)) /* 2 REG_WLLPS_CTRL_8197F */ @@ -1279,156 +1556,207 @@ #define BIT_SHIFT_REF_SEL_8197F 25 #define BIT_MASK_REF_SEL_8197F 0xf -#define BIT_REF_SEL_8197F(x) (((x) & BIT_MASK_REF_SEL_8197F) << BIT_SHIFT_REF_SEL_8197F) +#define BIT_REF_SEL_8197F(x) \ + (((x) & BIT_MASK_REF_SEL_8197F) << BIT_SHIFT_REF_SEL_8197F) #define BITS_REF_SEL_8197F (BIT_MASK_REF_SEL_8197F << BIT_SHIFT_REF_SEL_8197F) #define BIT_CLEAR_REF_SEL_8197F(x) ((x) & (~BITS_REF_SEL_8197F)) -#define BIT_GET_REF_SEL_8197F(x) (((x) >> BIT_SHIFT_REF_SEL_8197F) & BIT_MASK_REF_SEL_8197F) -#define BIT_SET_REF_SEL_8197F(x, v) (BIT_CLEAR_REF_SEL_8197F(x) | BIT_REF_SEL_8197F(v)) - +#define BIT_GET_REF_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_REF_SEL_8197F) & BIT_MASK_REF_SEL_8197F) +#define BIT_SET_REF_SEL_8197F(x, v) \ + (BIT_CLEAR_REF_SEL_8197F(x) | BIT_REF_SEL_8197F(v)) #define BIT_SHIFT_F0F_SDM_V2_8197F 12 #define BIT_MASK_F0F_SDM_V2_8197F 0x1fff -#define BIT_F0F_SDM_V2_8197F(x) (((x) & BIT_MASK_F0F_SDM_V2_8197F) << BIT_SHIFT_F0F_SDM_V2_8197F) -#define BITS_F0F_SDM_V2_8197F (BIT_MASK_F0F_SDM_V2_8197F << BIT_SHIFT_F0F_SDM_V2_8197F) +#define BIT_F0F_SDM_V2_8197F(x) \ + (((x) & BIT_MASK_F0F_SDM_V2_8197F) << BIT_SHIFT_F0F_SDM_V2_8197F) +#define BITS_F0F_SDM_V2_8197F \ + (BIT_MASK_F0F_SDM_V2_8197F << BIT_SHIFT_F0F_SDM_V2_8197F) #define BIT_CLEAR_F0F_SDM_V2_8197F(x) ((x) & (~BITS_F0F_SDM_V2_8197F)) -#define BIT_GET_F0F_SDM_V2_8197F(x) (((x) >> BIT_SHIFT_F0F_SDM_V2_8197F) & BIT_MASK_F0F_SDM_V2_8197F) -#define BIT_SET_F0F_SDM_V2_8197F(x, v) (BIT_CLEAR_F0F_SDM_V2_8197F(x) | BIT_F0F_SDM_V2_8197F(v)) - +#define BIT_GET_F0F_SDM_V2_8197F(x) \ + (((x) >> BIT_SHIFT_F0F_SDM_V2_8197F) & BIT_MASK_F0F_SDM_V2_8197F) +#define BIT_SET_F0F_SDM_V2_8197F(x, v) \ + (BIT_CLEAR_F0F_SDM_V2_8197F(x) | BIT_F0F_SDM_V2_8197F(v)) #define BIT_SHIFT_F0N_SDM_V2_8197F 9 #define BIT_MASK_F0N_SDM_V2_8197F 0x7 -#define BIT_F0N_SDM_V2_8197F(x) (((x) & BIT_MASK_F0N_SDM_V2_8197F) << BIT_SHIFT_F0N_SDM_V2_8197F) -#define BITS_F0N_SDM_V2_8197F (BIT_MASK_F0N_SDM_V2_8197F << BIT_SHIFT_F0N_SDM_V2_8197F) +#define BIT_F0N_SDM_V2_8197F(x) \ + (((x) & BIT_MASK_F0N_SDM_V2_8197F) << BIT_SHIFT_F0N_SDM_V2_8197F) +#define BITS_F0N_SDM_V2_8197F \ + (BIT_MASK_F0N_SDM_V2_8197F << BIT_SHIFT_F0N_SDM_V2_8197F) #define BIT_CLEAR_F0N_SDM_V2_8197F(x) ((x) & (~BITS_F0N_SDM_V2_8197F)) -#define BIT_GET_F0N_SDM_V2_8197F(x) (((x) >> BIT_SHIFT_F0N_SDM_V2_8197F) & BIT_MASK_F0N_SDM_V2_8197F) -#define BIT_SET_F0N_SDM_V2_8197F(x, v) (BIT_CLEAR_F0N_SDM_V2_8197F(x) | BIT_F0N_SDM_V2_8197F(v)) - +#define BIT_GET_F0N_SDM_V2_8197F(x) \ + (((x) >> BIT_SHIFT_F0N_SDM_V2_8197F) & BIT_MASK_F0N_SDM_V2_8197F) +#define BIT_SET_F0N_SDM_V2_8197F(x, v) \ + (BIT_CLEAR_F0N_SDM_V2_8197F(x) | BIT_F0N_SDM_V2_8197F(v)) #define BIT_SHIFT_DIVN_SDM_V2_8197F 3 #define BIT_MASK_DIVN_SDM_V2_8197F 0x3f -#define BIT_DIVN_SDM_V2_8197F(x) (((x) & BIT_MASK_DIVN_SDM_V2_8197F) << BIT_SHIFT_DIVN_SDM_V2_8197F) -#define BITS_DIVN_SDM_V2_8197F (BIT_MASK_DIVN_SDM_V2_8197F << BIT_SHIFT_DIVN_SDM_V2_8197F) +#define BIT_DIVN_SDM_V2_8197F(x) \ + (((x) & BIT_MASK_DIVN_SDM_V2_8197F) << BIT_SHIFT_DIVN_SDM_V2_8197F) +#define BITS_DIVN_SDM_V2_8197F \ + (BIT_MASK_DIVN_SDM_V2_8197F << BIT_SHIFT_DIVN_SDM_V2_8197F) #define BIT_CLEAR_DIVN_SDM_V2_8197F(x) ((x) & (~BITS_DIVN_SDM_V2_8197F)) -#define BIT_GET_DIVN_SDM_V2_8197F(x) (((x) >> BIT_SHIFT_DIVN_SDM_V2_8197F) & BIT_MASK_DIVN_SDM_V2_8197F) -#define BIT_SET_DIVN_SDM_V2_8197F(x, v) (BIT_CLEAR_DIVN_SDM_V2_8197F(x) | BIT_DIVN_SDM_V2_8197F(v)) - +#define BIT_GET_DIVN_SDM_V2_8197F(x) \ + (((x) >> BIT_SHIFT_DIVN_SDM_V2_8197F) & BIT_MASK_DIVN_SDM_V2_8197F) +#define BIT_SET_DIVN_SDM_V2_8197F(x, v) \ + (BIT_CLEAR_DIVN_SDM_V2_8197F(x) | BIT_DIVN_SDM_V2_8197F(v)) #define BIT_SHIFT_DITHER_SDM_V2_8197F 0 #define BIT_MASK_DITHER_SDM_V2_8197F 0x7 -#define BIT_DITHER_SDM_V2_8197F(x) (((x) & BIT_MASK_DITHER_SDM_V2_8197F) << BIT_SHIFT_DITHER_SDM_V2_8197F) -#define BITS_DITHER_SDM_V2_8197F (BIT_MASK_DITHER_SDM_V2_8197F << BIT_SHIFT_DITHER_SDM_V2_8197F) +#define BIT_DITHER_SDM_V2_8197F(x) \ + (((x) & BIT_MASK_DITHER_SDM_V2_8197F) << BIT_SHIFT_DITHER_SDM_V2_8197F) +#define BITS_DITHER_SDM_V2_8197F \ + (BIT_MASK_DITHER_SDM_V2_8197F << BIT_SHIFT_DITHER_SDM_V2_8197F) #define BIT_CLEAR_DITHER_SDM_V2_8197F(x) ((x) & (~BITS_DITHER_SDM_V2_8197F)) -#define BIT_GET_DITHER_SDM_V2_8197F(x) (((x) >> BIT_SHIFT_DITHER_SDM_V2_8197F) & BIT_MASK_DITHER_SDM_V2_8197F) -#define BIT_SET_DITHER_SDM_V2_8197F(x, v) (BIT_CLEAR_DITHER_SDM_V2_8197F(x) | BIT_DITHER_SDM_V2_8197F(v)) - +#define BIT_GET_DITHER_SDM_V2_8197F(x) \ + (((x) >> BIT_SHIFT_DITHER_SDM_V2_8197F) & BIT_MASK_DITHER_SDM_V2_8197F) +#define BIT_SET_DITHER_SDM_V2_8197F(x, v) \ + (BIT_CLEAR_DITHER_SDM_V2_8197F(x) | BIT_DITHER_SDM_V2_8197F(v)) /* 2 REG_GPIO_DEBOUNCE_CTRL_8197F */ #define BIT_WLGP_DBC1EN_8197F BIT(15) #define BIT_SHIFT_WLGP_DBC1_8197F 8 #define BIT_MASK_WLGP_DBC1_8197F 0xf -#define BIT_WLGP_DBC1_8197F(x) (((x) & BIT_MASK_WLGP_DBC1_8197F) << BIT_SHIFT_WLGP_DBC1_8197F) -#define BITS_WLGP_DBC1_8197F (BIT_MASK_WLGP_DBC1_8197F << BIT_SHIFT_WLGP_DBC1_8197F) +#define BIT_WLGP_DBC1_8197F(x) \ + (((x) & BIT_MASK_WLGP_DBC1_8197F) << BIT_SHIFT_WLGP_DBC1_8197F) +#define BITS_WLGP_DBC1_8197F \ + (BIT_MASK_WLGP_DBC1_8197F << BIT_SHIFT_WLGP_DBC1_8197F) #define BIT_CLEAR_WLGP_DBC1_8197F(x) ((x) & (~BITS_WLGP_DBC1_8197F)) -#define BIT_GET_WLGP_DBC1_8197F(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8197F) & BIT_MASK_WLGP_DBC1_8197F) -#define BIT_SET_WLGP_DBC1_8197F(x, v) (BIT_CLEAR_WLGP_DBC1_8197F(x) | BIT_WLGP_DBC1_8197F(v)) +#define BIT_GET_WLGP_DBC1_8197F(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC1_8197F) & BIT_MASK_WLGP_DBC1_8197F) +#define BIT_SET_WLGP_DBC1_8197F(x, v) \ + (BIT_CLEAR_WLGP_DBC1_8197F(x) | BIT_WLGP_DBC1_8197F(v)) #define BIT_WLGP_DBC0EN_8197F BIT(7) #define BIT_SHIFT_WLGP_DBC0_8197F 0 #define BIT_MASK_WLGP_DBC0_8197F 0xf -#define BIT_WLGP_DBC0_8197F(x) (((x) & BIT_MASK_WLGP_DBC0_8197F) << BIT_SHIFT_WLGP_DBC0_8197F) -#define BITS_WLGP_DBC0_8197F (BIT_MASK_WLGP_DBC0_8197F << BIT_SHIFT_WLGP_DBC0_8197F) +#define BIT_WLGP_DBC0_8197F(x) \ + (((x) & BIT_MASK_WLGP_DBC0_8197F) << BIT_SHIFT_WLGP_DBC0_8197F) +#define BITS_WLGP_DBC0_8197F \ + (BIT_MASK_WLGP_DBC0_8197F << BIT_SHIFT_WLGP_DBC0_8197F) #define BIT_CLEAR_WLGP_DBC0_8197F(x) ((x) & (~BITS_WLGP_DBC0_8197F)) -#define BIT_GET_WLGP_DBC0_8197F(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8197F) & BIT_MASK_WLGP_DBC0_8197F) -#define BIT_SET_WLGP_DBC0_8197F(x, v) (BIT_CLEAR_WLGP_DBC0_8197F(x) | BIT_WLGP_DBC0_8197F(v)) - +#define BIT_GET_WLGP_DBC0_8197F(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC0_8197F) & BIT_MASK_WLGP_DBC0_8197F) +#define BIT_SET_WLGP_DBC0_8197F(x, v) \ + (BIT_CLEAR_WLGP_DBC0_8197F(x) | BIT_WLGP_DBC0_8197F(v)) /* 2 REG_RPWM2_8197F */ #define BIT_SHIFT_RPWM2_8197F 16 #define BIT_MASK_RPWM2_8197F 0xffff -#define BIT_RPWM2_8197F(x) (((x) & BIT_MASK_RPWM2_8197F) << BIT_SHIFT_RPWM2_8197F) +#define BIT_RPWM2_8197F(x) \ + (((x) & BIT_MASK_RPWM2_8197F) << BIT_SHIFT_RPWM2_8197F) #define BITS_RPWM2_8197F (BIT_MASK_RPWM2_8197F << BIT_SHIFT_RPWM2_8197F) #define BIT_CLEAR_RPWM2_8197F(x) ((x) & (~BITS_RPWM2_8197F)) -#define BIT_GET_RPWM2_8197F(x) (((x) >> BIT_SHIFT_RPWM2_8197F) & BIT_MASK_RPWM2_8197F) -#define BIT_SET_RPWM2_8197F(x, v) (BIT_CLEAR_RPWM2_8197F(x) | BIT_RPWM2_8197F(v)) - +#define BIT_GET_RPWM2_8197F(x) \ + (((x) >> BIT_SHIFT_RPWM2_8197F) & BIT_MASK_RPWM2_8197F) +#define BIT_SET_RPWM2_8197F(x, v) \ + (BIT_CLEAR_RPWM2_8197F(x) | BIT_RPWM2_8197F(v)) /* 2 REG_SYSON_FSM_MON_8197F */ #define BIT_SHIFT_FSM_MON_SEL_8197F 24 #define BIT_MASK_FSM_MON_SEL_8197F 0x7 -#define BIT_FSM_MON_SEL_8197F(x) (((x) & BIT_MASK_FSM_MON_SEL_8197F) << BIT_SHIFT_FSM_MON_SEL_8197F) -#define BITS_FSM_MON_SEL_8197F (BIT_MASK_FSM_MON_SEL_8197F << BIT_SHIFT_FSM_MON_SEL_8197F) +#define BIT_FSM_MON_SEL_8197F(x) \ + (((x) & BIT_MASK_FSM_MON_SEL_8197F) << BIT_SHIFT_FSM_MON_SEL_8197F) +#define BITS_FSM_MON_SEL_8197F \ + (BIT_MASK_FSM_MON_SEL_8197F << BIT_SHIFT_FSM_MON_SEL_8197F) #define BIT_CLEAR_FSM_MON_SEL_8197F(x) ((x) & (~BITS_FSM_MON_SEL_8197F)) -#define BIT_GET_FSM_MON_SEL_8197F(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8197F) & BIT_MASK_FSM_MON_SEL_8197F) -#define BIT_SET_FSM_MON_SEL_8197F(x, v) (BIT_CLEAR_FSM_MON_SEL_8197F(x) | BIT_FSM_MON_SEL_8197F(v)) +#define BIT_GET_FSM_MON_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_FSM_MON_SEL_8197F) & BIT_MASK_FSM_MON_SEL_8197F) +#define BIT_SET_FSM_MON_SEL_8197F(x, v) \ + (BIT_CLEAR_FSM_MON_SEL_8197F(x) | BIT_FSM_MON_SEL_8197F(v)) #define BIT_DOP_ELDO_8197F BIT(23) #define BIT_FSM_MON_UPD_8197F BIT(15) #define BIT_SHIFT_FSM_PAR_8197F 0 #define BIT_MASK_FSM_PAR_8197F 0x7fff -#define BIT_FSM_PAR_8197F(x) (((x) & BIT_MASK_FSM_PAR_8197F) << BIT_SHIFT_FSM_PAR_8197F) +#define BIT_FSM_PAR_8197F(x) \ + (((x) & BIT_MASK_FSM_PAR_8197F) << BIT_SHIFT_FSM_PAR_8197F) #define BITS_FSM_PAR_8197F (BIT_MASK_FSM_PAR_8197F << BIT_SHIFT_FSM_PAR_8197F) #define BIT_CLEAR_FSM_PAR_8197F(x) ((x) & (~BITS_FSM_PAR_8197F)) -#define BIT_GET_FSM_PAR_8197F(x) (((x) >> BIT_SHIFT_FSM_PAR_8197F) & BIT_MASK_FSM_PAR_8197F) -#define BIT_SET_FSM_PAR_8197F(x, v) (BIT_CLEAR_FSM_PAR_8197F(x) | BIT_FSM_PAR_8197F(v)) - +#define BIT_GET_FSM_PAR_8197F(x) \ + (((x) >> BIT_SHIFT_FSM_PAR_8197F) & BIT_MASK_FSM_PAR_8197F) +#define BIT_SET_FSM_PAR_8197F(x, v) \ + (BIT_CLEAR_FSM_PAR_8197F(x) | BIT_FSM_PAR_8197F(v)) /* 2 REG_AFE_CTRL6_8197F */ #define BIT_SHIFT_TSFT_SEL_V1_8197F 0 #define BIT_MASK_TSFT_SEL_V1_8197F 0x7 -#define BIT_TSFT_SEL_V1_8197F(x) (((x) & BIT_MASK_TSFT_SEL_V1_8197F) << BIT_SHIFT_TSFT_SEL_V1_8197F) -#define BITS_TSFT_SEL_V1_8197F (BIT_MASK_TSFT_SEL_V1_8197F << BIT_SHIFT_TSFT_SEL_V1_8197F) +#define BIT_TSFT_SEL_V1_8197F(x) \ + (((x) & BIT_MASK_TSFT_SEL_V1_8197F) << BIT_SHIFT_TSFT_SEL_V1_8197F) +#define BITS_TSFT_SEL_V1_8197F \ + (BIT_MASK_TSFT_SEL_V1_8197F << BIT_SHIFT_TSFT_SEL_V1_8197F) #define BIT_CLEAR_TSFT_SEL_V1_8197F(x) ((x) & (~BITS_TSFT_SEL_V1_8197F)) -#define BIT_GET_TSFT_SEL_V1_8197F(x) (((x) >> BIT_SHIFT_TSFT_SEL_V1_8197F) & BIT_MASK_TSFT_SEL_V1_8197F) -#define BIT_SET_TSFT_SEL_V1_8197F(x, v) (BIT_CLEAR_TSFT_SEL_V1_8197F(x) | BIT_TSFT_SEL_V1_8197F(v)) - +#define BIT_GET_TSFT_SEL_V1_8197F(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_V1_8197F) & BIT_MASK_TSFT_SEL_V1_8197F) +#define BIT_SET_TSFT_SEL_V1_8197F(x, v) \ + (BIT_CLEAR_TSFT_SEL_V1_8197F(x) | BIT_TSFT_SEL_V1_8197F(v)) /* 2 REG_PMC_DBG_CTRL1_8197F */ #define BIT_BT_INT_EN_8197F BIT(31) #define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F 16 #define BIT_MASK_RD_WR_WIFI_BT_INFO_8197F 0x7fff -#define BIT_RD_WR_WIFI_BT_INFO_8197F(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8197F) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) -#define BITS_RD_WR_WIFI_BT_INFO_8197F (BIT_MASK_RD_WR_WIFI_BT_INFO_8197F << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) -#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8197F)) -#define BIT_GET_RD_WR_WIFI_BT_INFO_8197F(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) & BIT_MASK_RD_WR_WIFI_BT_INFO_8197F) -#define BIT_SET_RD_WR_WIFI_BT_INFO_8197F(x, v) (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) | BIT_RD_WR_WIFI_BT_INFO_8197F(v)) +#define BIT_RD_WR_WIFI_BT_INFO_8197F(x) \ + (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8197F) \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) +#define BITS_RD_WR_WIFI_BT_INFO_8197F \ + (BIT_MASK_RD_WR_WIFI_BT_INFO_8197F \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) \ + ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8197F)) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) & \ + BIT_MASK_RD_WR_WIFI_BT_INFO_8197F) +#define BIT_SET_RD_WR_WIFI_BT_INFO_8197F(x, v) \ + (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) | \ + BIT_RD_WR_WIFI_BT_INFO_8197F(v)) #define BIT_PMC_WR_OVF_8197F BIT(8) #define BIT_SHIFT_WLPMC_ERRINT_8197F 0 #define BIT_MASK_WLPMC_ERRINT_8197F 0xff -#define BIT_WLPMC_ERRINT_8197F(x) (((x) & BIT_MASK_WLPMC_ERRINT_8197F) << BIT_SHIFT_WLPMC_ERRINT_8197F) -#define BITS_WLPMC_ERRINT_8197F (BIT_MASK_WLPMC_ERRINT_8197F << BIT_SHIFT_WLPMC_ERRINT_8197F) +#define BIT_WLPMC_ERRINT_8197F(x) \ + (((x) & BIT_MASK_WLPMC_ERRINT_8197F) << BIT_SHIFT_WLPMC_ERRINT_8197F) +#define BITS_WLPMC_ERRINT_8197F \ + (BIT_MASK_WLPMC_ERRINT_8197F << BIT_SHIFT_WLPMC_ERRINT_8197F) #define BIT_CLEAR_WLPMC_ERRINT_8197F(x) ((x) & (~BITS_WLPMC_ERRINT_8197F)) -#define BIT_GET_WLPMC_ERRINT_8197F(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8197F) & BIT_MASK_WLPMC_ERRINT_8197F) -#define BIT_SET_WLPMC_ERRINT_8197F(x, v) (BIT_CLEAR_WLPMC_ERRINT_8197F(x) | BIT_WLPMC_ERRINT_8197F(v)) - +#define BIT_GET_WLPMC_ERRINT_8197F(x) \ + (((x) >> BIT_SHIFT_WLPMC_ERRINT_8197F) & BIT_MASK_WLPMC_ERRINT_8197F) +#define BIT_SET_WLPMC_ERRINT_8197F(x, v) \ + (BIT_CLEAR_WLPMC_ERRINT_8197F(x) | BIT_WLPMC_ERRINT_8197F(v)) /* 2 REG_AFE_CTRL7_8197F */ #define BIT_SHIFT_SEL_V_8197F 30 #define BIT_MASK_SEL_V_8197F 0x3 -#define BIT_SEL_V_8197F(x) (((x) & BIT_MASK_SEL_V_8197F) << BIT_SHIFT_SEL_V_8197F) +#define BIT_SEL_V_8197F(x) \ + (((x) & BIT_MASK_SEL_V_8197F) << BIT_SHIFT_SEL_V_8197F) #define BITS_SEL_V_8197F (BIT_MASK_SEL_V_8197F << BIT_SHIFT_SEL_V_8197F) #define BIT_CLEAR_SEL_V_8197F(x) ((x) & (~BITS_SEL_V_8197F)) -#define BIT_GET_SEL_V_8197F(x) (((x) >> BIT_SHIFT_SEL_V_8197F) & BIT_MASK_SEL_V_8197F) -#define BIT_SET_SEL_V_8197F(x, v) (BIT_CLEAR_SEL_V_8197F(x) | BIT_SEL_V_8197F(v)) +#define BIT_GET_SEL_V_8197F(x) \ + (((x) >> BIT_SHIFT_SEL_V_8197F) & BIT_MASK_SEL_V_8197F) +#define BIT_SET_SEL_V_8197F(x, v) \ + (BIT_CLEAR_SEL_V_8197F(x) | BIT_SEL_V_8197F(v)) #define BIT_SEL_LDO_PC_8197F BIT(29) #define BIT_SHIFT_CK_MON_SEL_V2_8197F 26 #define BIT_MASK_CK_MON_SEL_V2_8197F 0x7 -#define BIT_CK_MON_SEL_V2_8197F(x) (((x) & BIT_MASK_CK_MON_SEL_V2_8197F) << BIT_SHIFT_CK_MON_SEL_V2_8197F) -#define BITS_CK_MON_SEL_V2_8197F (BIT_MASK_CK_MON_SEL_V2_8197F << BIT_SHIFT_CK_MON_SEL_V2_8197F) +#define BIT_CK_MON_SEL_V2_8197F(x) \ + (((x) & BIT_MASK_CK_MON_SEL_V2_8197F) << BIT_SHIFT_CK_MON_SEL_V2_8197F) +#define BITS_CK_MON_SEL_V2_8197F \ + (BIT_MASK_CK_MON_SEL_V2_8197F << BIT_SHIFT_CK_MON_SEL_V2_8197F) #define BIT_CLEAR_CK_MON_SEL_V2_8197F(x) ((x) & (~BITS_CK_MON_SEL_V2_8197F)) -#define BIT_GET_CK_MON_SEL_V2_8197F(x) (((x) >> BIT_SHIFT_CK_MON_SEL_V2_8197F) & BIT_MASK_CK_MON_SEL_V2_8197F) -#define BIT_SET_CK_MON_SEL_V2_8197F(x, v) (BIT_CLEAR_CK_MON_SEL_V2_8197F(x) | BIT_CK_MON_SEL_V2_8197F(v)) +#define BIT_GET_CK_MON_SEL_V2_8197F(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL_V2_8197F) & BIT_MASK_CK_MON_SEL_V2_8197F) +#define BIT_SET_CK_MON_SEL_V2_8197F(x, v) \ + (BIT_CLEAR_CK_MON_SEL_V2_8197F(x) | BIT_CK_MON_SEL_V2_8197F(v)) #define BIT_CK_MON_EN_8197F BIT(25) #define BIT_FREF_EDGE_8197F BIT(24) @@ -1448,7 +1776,8 @@ #define BIT_BCNDMAINT0_MSK_8197F BIT(20) #define BIT_BCNDERR0_MSK_8197F BIT(16) #define BIT_HSISR_IND_ON_INT_MSK_8197F BIT(15) -#define BIT_BCNDMAINT_E_MSK_8197F BIT(14) +#define BIT_HISR3_IND_INT_MSK_8197F BIT(14) +#define BIT_HISR2_IND_INT_MSK_8197F BIT(13) #define BIT_CTWEND_MSK_8197F BIT(12) #define BIT_HISR1_IND_MSK_8197F BIT(11) #define BIT_C2HCMD_MSK_8197F BIT(10) @@ -1464,8 +1793,8 @@ #define BIT_RXOK_MSK_8197F BIT(0) /* 2 REG_HISR0_8197F */ -#define BIT_TIMEOUT_INTERRUPT2_8197F BIT(31) -#define BIT_TIMEOUT_INTERRUTP1_8197F BIT(30) +#define BIT_PSTIMEOUT2_8197F BIT(31) +#define BIT_PSTIMEOUT1_8197F BIT(30) #define BIT_PSTIMEOUT_8197F BIT(29) #define BIT_GTINT4_8197F BIT(28) #define BIT_GTINT3_8197F BIT(27) @@ -1475,7 +1804,8 @@ #define BIT_BCNDMAINT0_8197F BIT(20) #define BIT_BCNDERR0_8197F BIT(16) #define BIT_HSISR_IND_ON_INT_8197F BIT(15) -#define BIT_BCNDMAINT_E_8197F BIT(14) +#define BIT_HISR3_IND_INT_8197F BIT(14) +#define BIT_HISR2_IND_INT_8197F BIT(13) #define BIT_CTWEND_8197F BIT(12) #define BIT_HISR1_IND_INT_8197F BIT(11) #define BIT_C2HCMD_8197F BIT(10) @@ -1542,12 +1872,15 @@ #define BIT_SHIFT_DEBUG_ST_8197F 0 #define BIT_MASK_DEBUG_ST_8197F 0xffffffffL -#define BIT_DEBUG_ST_8197F(x) (((x) & BIT_MASK_DEBUG_ST_8197F) << BIT_SHIFT_DEBUG_ST_8197F) -#define BITS_DEBUG_ST_8197F (BIT_MASK_DEBUG_ST_8197F << BIT_SHIFT_DEBUG_ST_8197F) +#define BIT_DEBUG_ST_8197F(x) \ + (((x) & BIT_MASK_DEBUG_ST_8197F) << BIT_SHIFT_DEBUG_ST_8197F) +#define BITS_DEBUG_ST_8197F \ + (BIT_MASK_DEBUG_ST_8197F << BIT_SHIFT_DEBUG_ST_8197F) #define BIT_CLEAR_DEBUG_ST_8197F(x) ((x) & (~BITS_DEBUG_ST_8197F)) -#define BIT_GET_DEBUG_ST_8197F(x) (((x) >> BIT_SHIFT_DEBUG_ST_8197F) & BIT_MASK_DEBUG_ST_8197F) -#define BIT_SET_DEBUG_ST_8197F(x, v) (BIT_CLEAR_DEBUG_ST_8197F(x) | BIT_DEBUG_ST_8197F(v)) - +#define BIT_GET_DEBUG_ST_8197F(x) \ + (((x) >> BIT_SHIFT_DEBUG_ST_8197F) & BIT_MASK_DEBUG_ST_8197F) +#define BIT_SET_DEBUG_ST_8197F(x, v) \ + (BIT_CLEAR_DEBUG_ST_8197F(x) | BIT_DEBUG_ST_8197F(v)) /* 2 REG_PAD_CTRL2_8197F */ @@ -1574,11 +1907,17 @@ #define BIT_SHIFT_EFUSE_BURN_GNT_8197F 24 #define BIT_MASK_EFUSE_BURN_GNT_8197F 0xff -#define BIT_EFUSE_BURN_GNT_8197F(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8197F) << BIT_SHIFT_EFUSE_BURN_GNT_8197F) -#define BITS_EFUSE_BURN_GNT_8197F (BIT_MASK_EFUSE_BURN_GNT_8197F << BIT_SHIFT_EFUSE_BURN_GNT_8197F) +#define BIT_EFUSE_BURN_GNT_8197F(x) \ + (((x) & BIT_MASK_EFUSE_BURN_GNT_8197F) \ + << BIT_SHIFT_EFUSE_BURN_GNT_8197F) +#define BITS_EFUSE_BURN_GNT_8197F \ + (BIT_MASK_EFUSE_BURN_GNT_8197F << BIT_SHIFT_EFUSE_BURN_GNT_8197F) #define BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) ((x) & (~BITS_EFUSE_BURN_GNT_8197F)) -#define BIT_GET_EFUSE_BURN_GNT_8197F(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8197F) & BIT_MASK_EFUSE_BURN_GNT_8197F) -#define BIT_SET_EFUSE_BURN_GNT_8197F(x, v) (BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) | BIT_EFUSE_BURN_GNT_8197F(v)) +#define BIT_GET_EFUSE_BURN_GNT_8197F(x) \ + (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8197F) & \ + BIT_MASK_EFUSE_BURN_GNT_8197F) +#define BIT_SET_EFUSE_BURN_GNT_8197F(x, v) \ + (BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) | BIT_EFUSE_BURN_GNT_8197F(v)) #define BIT_STOP_WL_PMC_8197F BIT(9) #define BIT_STOP_SYM_PMC_8197F BIT(8) @@ -1589,12 +1928,15 @@ #define BIT_SHIFT_SYSON_REG_ARB_8197F 0 #define BIT_MASK_SYSON_REG_ARB_8197F 0x3 -#define BIT_SYSON_REG_ARB_8197F(x) (((x) & BIT_MASK_SYSON_REG_ARB_8197F) << BIT_SHIFT_SYSON_REG_ARB_8197F) -#define BITS_SYSON_REG_ARB_8197F (BIT_MASK_SYSON_REG_ARB_8197F << BIT_SHIFT_SYSON_REG_ARB_8197F) +#define BIT_SYSON_REG_ARB_8197F(x) \ + (((x) & BIT_MASK_SYSON_REG_ARB_8197F) << BIT_SHIFT_SYSON_REG_ARB_8197F) +#define BITS_SYSON_REG_ARB_8197F \ + (BIT_MASK_SYSON_REG_ARB_8197F << BIT_SHIFT_SYSON_REG_ARB_8197F) #define BIT_CLEAR_SYSON_REG_ARB_8197F(x) ((x) & (~BITS_SYSON_REG_ARB_8197F)) -#define BIT_GET_SYSON_REG_ARB_8197F(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8197F) & BIT_MASK_SYSON_REG_ARB_8197F) -#define BIT_SET_SYSON_REG_ARB_8197F(x, v) (BIT_CLEAR_SYSON_REG_ARB_8197F(x) | BIT_SYSON_REG_ARB_8197F(v)) - +#define BIT_GET_SYSON_REG_ARB_8197F(x) \ + (((x) >> BIT_SHIFT_SYSON_REG_ARB_8197F) & BIT_MASK_SYSON_REG_ARB_8197F) +#define BIT_SET_SYSON_REG_ARB_8197F(x, v) \ + (BIT_CLEAR_SYSON_REG_ARB_8197F(x) | BIT_SYSON_REG_ARB_8197F(v)) /* 2 REG_BIST_CTRL_8197F */ #define BIT_BIST_USB_DIS_8197F BIT(27) @@ -1604,11 +1946,15 @@ #define BIT_SHIFT_BIST_RPT_SEL_8197F 16 #define BIT_MASK_BIST_RPT_SEL_8197F 0xf -#define BIT_BIST_RPT_SEL_8197F(x) (((x) & BIT_MASK_BIST_RPT_SEL_8197F) << BIT_SHIFT_BIST_RPT_SEL_8197F) -#define BITS_BIST_RPT_SEL_8197F (BIT_MASK_BIST_RPT_SEL_8197F << BIT_SHIFT_BIST_RPT_SEL_8197F) +#define BIT_BIST_RPT_SEL_8197F(x) \ + (((x) & BIT_MASK_BIST_RPT_SEL_8197F) << BIT_SHIFT_BIST_RPT_SEL_8197F) +#define BITS_BIST_RPT_SEL_8197F \ + (BIT_MASK_BIST_RPT_SEL_8197F << BIT_SHIFT_BIST_RPT_SEL_8197F) #define BIT_CLEAR_BIST_RPT_SEL_8197F(x) ((x) & (~BITS_BIST_RPT_SEL_8197F)) -#define BIT_GET_BIST_RPT_SEL_8197F(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8197F) & BIT_MASK_BIST_RPT_SEL_8197F) -#define BIT_SET_BIST_RPT_SEL_8197F(x, v) (BIT_CLEAR_BIST_RPT_SEL_8197F(x) | BIT_BIST_RPT_SEL_8197F(v)) +#define BIT_GET_BIST_RPT_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_BIST_RPT_SEL_8197F) & BIT_MASK_BIST_RPT_SEL_8197F) +#define BIT_SET_BIST_RPT_SEL_8197F(x, v) \ + (BIT_CLEAR_BIST_RPT_SEL_8197F(x) | BIT_BIST_RPT_SEL_8197F(v)) #define BIT_BIST_RESUME_PS_8197F BIT(4) #define BIT_BIST_RESUME_8197F BIT(3) @@ -1620,99 +1966,135 @@ #define BIT_SHIFT_MBIST_REPORT_8197F 0 #define BIT_MASK_MBIST_REPORT_8197F 0xffffffffL -#define BIT_MBIST_REPORT_8197F(x) (((x) & BIT_MASK_MBIST_REPORT_8197F) << BIT_SHIFT_MBIST_REPORT_8197F) -#define BITS_MBIST_REPORT_8197F (BIT_MASK_MBIST_REPORT_8197F << BIT_SHIFT_MBIST_REPORT_8197F) +#define BIT_MBIST_REPORT_8197F(x) \ + (((x) & BIT_MASK_MBIST_REPORT_8197F) << BIT_SHIFT_MBIST_REPORT_8197F) +#define BITS_MBIST_REPORT_8197F \ + (BIT_MASK_MBIST_REPORT_8197F << BIT_SHIFT_MBIST_REPORT_8197F) #define BIT_CLEAR_MBIST_REPORT_8197F(x) ((x) & (~BITS_MBIST_REPORT_8197F)) -#define BIT_GET_MBIST_REPORT_8197F(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8197F) & BIT_MASK_MBIST_REPORT_8197F) -#define BIT_SET_MBIST_REPORT_8197F(x, v) (BIT_CLEAR_MBIST_REPORT_8197F(x) | BIT_MBIST_REPORT_8197F(v)) - +#define BIT_GET_MBIST_REPORT_8197F(x) \ + (((x) >> BIT_SHIFT_MBIST_REPORT_8197F) & BIT_MASK_MBIST_REPORT_8197F) +#define BIT_SET_MBIST_REPORT_8197F(x, v) \ + (BIT_CLEAR_MBIST_REPORT_8197F(x) | BIT_MBIST_REPORT_8197F(v)) /* 2 REG_MEM_CTRL_8197F */ #define BIT_UMEM_RME_8197F BIT(31) #define BIT_SHIFT_BT_SPRAM_8197F 28 #define BIT_MASK_BT_SPRAM_8197F 0x3 -#define BIT_BT_SPRAM_8197F(x) (((x) & BIT_MASK_BT_SPRAM_8197F) << BIT_SHIFT_BT_SPRAM_8197F) -#define BITS_BT_SPRAM_8197F (BIT_MASK_BT_SPRAM_8197F << BIT_SHIFT_BT_SPRAM_8197F) +#define BIT_BT_SPRAM_8197F(x) \ + (((x) & BIT_MASK_BT_SPRAM_8197F) << BIT_SHIFT_BT_SPRAM_8197F) +#define BITS_BT_SPRAM_8197F \ + (BIT_MASK_BT_SPRAM_8197F << BIT_SHIFT_BT_SPRAM_8197F) #define BIT_CLEAR_BT_SPRAM_8197F(x) ((x) & (~BITS_BT_SPRAM_8197F)) -#define BIT_GET_BT_SPRAM_8197F(x) (((x) >> BIT_SHIFT_BT_SPRAM_8197F) & BIT_MASK_BT_SPRAM_8197F) -#define BIT_SET_BT_SPRAM_8197F(x, v) (BIT_CLEAR_BT_SPRAM_8197F(x) | BIT_BT_SPRAM_8197F(v)) - +#define BIT_GET_BT_SPRAM_8197F(x) \ + (((x) >> BIT_SHIFT_BT_SPRAM_8197F) & BIT_MASK_BT_SPRAM_8197F) +#define BIT_SET_BT_SPRAM_8197F(x, v) \ + (BIT_CLEAR_BT_SPRAM_8197F(x) | BIT_BT_SPRAM_8197F(v)) #define BIT_SHIFT_BT_ROM_8197F 24 #define BIT_MASK_BT_ROM_8197F 0xf -#define BIT_BT_ROM_8197F(x) (((x) & BIT_MASK_BT_ROM_8197F) << BIT_SHIFT_BT_ROM_8197F) +#define BIT_BT_ROM_8197F(x) \ + (((x) & BIT_MASK_BT_ROM_8197F) << BIT_SHIFT_BT_ROM_8197F) #define BITS_BT_ROM_8197F (BIT_MASK_BT_ROM_8197F << BIT_SHIFT_BT_ROM_8197F) #define BIT_CLEAR_BT_ROM_8197F(x) ((x) & (~BITS_BT_ROM_8197F)) -#define BIT_GET_BT_ROM_8197F(x) (((x) >> BIT_SHIFT_BT_ROM_8197F) & BIT_MASK_BT_ROM_8197F) -#define BIT_SET_BT_ROM_8197F(x, v) (BIT_CLEAR_BT_ROM_8197F(x) | BIT_BT_ROM_8197F(v)) - +#define BIT_GET_BT_ROM_8197F(x) \ + (((x) >> BIT_SHIFT_BT_ROM_8197F) & BIT_MASK_BT_ROM_8197F) +#define BIT_SET_BT_ROM_8197F(x, v) \ + (BIT_CLEAR_BT_ROM_8197F(x) | BIT_BT_ROM_8197F(v)) #define BIT_SHIFT_PCI_DPRAM_8197F 10 #define BIT_MASK_PCI_DPRAM_8197F 0x3 -#define BIT_PCI_DPRAM_8197F(x) (((x) & BIT_MASK_PCI_DPRAM_8197F) << BIT_SHIFT_PCI_DPRAM_8197F) -#define BITS_PCI_DPRAM_8197F (BIT_MASK_PCI_DPRAM_8197F << BIT_SHIFT_PCI_DPRAM_8197F) +#define BIT_PCI_DPRAM_8197F(x) \ + (((x) & BIT_MASK_PCI_DPRAM_8197F) << BIT_SHIFT_PCI_DPRAM_8197F) +#define BITS_PCI_DPRAM_8197F \ + (BIT_MASK_PCI_DPRAM_8197F << BIT_SHIFT_PCI_DPRAM_8197F) #define BIT_CLEAR_PCI_DPRAM_8197F(x) ((x) & (~BITS_PCI_DPRAM_8197F)) -#define BIT_GET_PCI_DPRAM_8197F(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8197F) & BIT_MASK_PCI_DPRAM_8197F) -#define BIT_SET_PCI_DPRAM_8197F(x, v) (BIT_CLEAR_PCI_DPRAM_8197F(x) | BIT_PCI_DPRAM_8197F(v)) - +#define BIT_GET_PCI_DPRAM_8197F(x) \ + (((x) >> BIT_SHIFT_PCI_DPRAM_8197F) & BIT_MASK_PCI_DPRAM_8197F) +#define BIT_SET_PCI_DPRAM_8197F(x, v) \ + (BIT_CLEAR_PCI_DPRAM_8197F(x) | BIT_PCI_DPRAM_8197F(v)) #define BIT_SHIFT_PCI_SPRAM_8197F 8 #define BIT_MASK_PCI_SPRAM_8197F 0x3 -#define BIT_PCI_SPRAM_8197F(x) (((x) & BIT_MASK_PCI_SPRAM_8197F) << BIT_SHIFT_PCI_SPRAM_8197F) -#define BITS_PCI_SPRAM_8197F (BIT_MASK_PCI_SPRAM_8197F << BIT_SHIFT_PCI_SPRAM_8197F) +#define BIT_PCI_SPRAM_8197F(x) \ + (((x) & BIT_MASK_PCI_SPRAM_8197F) << BIT_SHIFT_PCI_SPRAM_8197F) +#define BITS_PCI_SPRAM_8197F \ + (BIT_MASK_PCI_SPRAM_8197F << BIT_SHIFT_PCI_SPRAM_8197F) #define BIT_CLEAR_PCI_SPRAM_8197F(x) ((x) & (~BITS_PCI_SPRAM_8197F)) -#define BIT_GET_PCI_SPRAM_8197F(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8197F) & BIT_MASK_PCI_SPRAM_8197F) -#define BIT_SET_PCI_SPRAM_8197F(x, v) (BIT_CLEAR_PCI_SPRAM_8197F(x) | BIT_PCI_SPRAM_8197F(v)) - +#define BIT_GET_PCI_SPRAM_8197F(x) \ + (((x) >> BIT_SHIFT_PCI_SPRAM_8197F) & BIT_MASK_PCI_SPRAM_8197F) +#define BIT_SET_PCI_SPRAM_8197F(x, v) \ + (BIT_CLEAR_PCI_SPRAM_8197F(x) | BIT_PCI_SPRAM_8197F(v)) #define BIT_SHIFT_USB_SPRAM_8197F 6 #define BIT_MASK_USB_SPRAM_8197F 0x3 -#define BIT_USB_SPRAM_8197F(x) (((x) & BIT_MASK_USB_SPRAM_8197F) << BIT_SHIFT_USB_SPRAM_8197F) -#define BITS_USB_SPRAM_8197F (BIT_MASK_USB_SPRAM_8197F << BIT_SHIFT_USB_SPRAM_8197F) +#define BIT_USB_SPRAM_8197F(x) \ + (((x) & BIT_MASK_USB_SPRAM_8197F) << BIT_SHIFT_USB_SPRAM_8197F) +#define BITS_USB_SPRAM_8197F \ + (BIT_MASK_USB_SPRAM_8197F << BIT_SHIFT_USB_SPRAM_8197F) #define BIT_CLEAR_USB_SPRAM_8197F(x) ((x) & (~BITS_USB_SPRAM_8197F)) -#define BIT_GET_USB_SPRAM_8197F(x) (((x) >> BIT_SHIFT_USB_SPRAM_8197F) & BIT_MASK_USB_SPRAM_8197F) -#define BIT_SET_USB_SPRAM_8197F(x, v) (BIT_CLEAR_USB_SPRAM_8197F(x) | BIT_USB_SPRAM_8197F(v)) - +#define BIT_GET_USB_SPRAM_8197F(x) \ + (((x) >> BIT_SHIFT_USB_SPRAM_8197F) & BIT_MASK_USB_SPRAM_8197F) +#define BIT_SET_USB_SPRAM_8197F(x, v) \ + (BIT_CLEAR_USB_SPRAM_8197F(x) | BIT_USB_SPRAM_8197F(v)) #define BIT_SHIFT_USB_SPRF_8197F 4 #define BIT_MASK_USB_SPRF_8197F 0x3 -#define BIT_USB_SPRF_8197F(x) (((x) & BIT_MASK_USB_SPRF_8197F) << BIT_SHIFT_USB_SPRF_8197F) -#define BITS_USB_SPRF_8197F (BIT_MASK_USB_SPRF_8197F << BIT_SHIFT_USB_SPRF_8197F) +#define BIT_USB_SPRF_8197F(x) \ + (((x) & BIT_MASK_USB_SPRF_8197F) << BIT_SHIFT_USB_SPRF_8197F) +#define BITS_USB_SPRF_8197F \ + (BIT_MASK_USB_SPRF_8197F << BIT_SHIFT_USB_SPRF_8197F) #define BIT_CLEAR_USB_SPRF_8197F(x) ((x) & (~BITS_USB_SPRF_8197F)) -#define BIT_GET_USB_SPRF_8197F(x) (((x) >> BIT_SHIFT_USB_SPRF_8197F) & BIT_MASK_USB_SPRF_8197F) -#define BIT_SET_USB_SPRF_8197F(x, v) (BIT_CLEAR_USB_SPRF_8197F(x) | BIT_USB_SPRF_8197F(v)) - +#define BIT_GET_USB_SPRF_8197F(x) \ + (((x) >> BIT_SHIFT_USB_SPRF_8197F) & BIT_MASK_USB_SPRF_8197F) +#define BIT_SET_USB_SPRF_8197F(x, v) \ + (BIT_CLEAR_USB_SPRF_8197F(x) | BIT_USB_SPRF_8197F(v)) #define BIT_SHIFT_MCU_ROM_8197F 0 #define BIT_MASK_MCU_ROM_8197F 0xf -#define BIT_MCU_ROM_8197F(x) (((x) & BIT_MASK_MCU_ROM_8197F) << BIT_SHIFT_MCU_ROM_8197F) +#define BIT_MCU_ROM_8197F(x) \ + (((x) & BIT_MASK_MCU_ROM_8197F) << BIT_SHIFT_MCU_ROM_8197F) #define BITS_MCU_ROM_8197F (BIT_MASK_MCU_ROM_8197F << BIT_SHIFT_MCU_ROM_8197F) #define BIT_CLEAR_MCU_ROM_8197F(x) ((x) & (~BITS_MCU_ROM_8197F)) -#define BIT_GET_MCU_ROM_8197F(x) (((x) >> BIT_SHIFT_MCU_ROM_8197F) & BIT_MASK_MCU_ROM_8197F) -#define BIT_SET_MCU_ROM_8197F(x, v) (BIT_CLEAR_MCU_ROM_8197F(x) | BIT_MCU_ROM_8197F(v)) - +#define BIT_GET_MCU_ROM_8197F(x) \ + (((x) >> BIT_SHIFT_MCU_ROM_8197F) & BIT_MASK_MCU_ROM_8197F) +#define BIT_SET_MCU_ROM_8197F(x, v) \ + (BIT_CLEAR_MCU_ROM_8197F(x) | BIT_MCU_ROM_8197F(v)) /* 2 REG_AFE_CTRL8_8197F */ #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F 26 #define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F 0x7 -#define BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) -#define BITS_BB_DBG_SEL_AFE_SDM_V4_8197F (BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) -#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4_8197F)) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4_8197F(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F) -#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4_8197F(x, v) (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) | BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(v)) +#define BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F) \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) +#define BITS_BB_DBG_SEL_AFE_SDM_V4_8197F \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) \ + ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4_8197F)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4_8197F(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) & \ + BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4_8197F(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) | \ + BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(v)) #define BIT_SYN_AGPIO_8197F BIT(20) #define BIT_SHIFT_XTAL_SEL_TOK_V2_8197F 0 #define BIT_MASK_XTAL_SEL_TOK_V2_8197F 0x7 -#define BIT_XTAL_SEL_TOK_V2_8197F(x) (((x) & BIT_MASK_XTAL_SEL_TOK_V2_8197F) << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) -#define BITS_XTAL_SEL_TOK_V2_8197F (BIT_MASK_XTAL_SEL_TOK_V2_8197F << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) +#define BIT_XTAL_SEL_TOK_V2_8197F(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_V2_8197F) \ + << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) +#define BITS_XTAL_SEL_TOK_V2_8197F \ + (BIT_MASK_XTAL_SEL_TOK_V2_8197F << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) #define BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) ((x) & (~BITS_XTAL_SEL_TOK_V2_8197F)) -#define BIT_GET_XTAL_SEL_TOK_V2_8197F(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) & BIT_MASK_XTAL_SEL_TOK_V2_8197F) -#define BIT_SET_XTAL_SEL_TOK_V2_8197F(x, v) (BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) | BIT_XTAL_SEL_TOK_V2_8197F(v)) - +#define BIT_GET_XTAL_SEL_TOK_V2_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) & \ + BIT_MASK_XTAL_SEL_TOK_V2_8197F) +#define BIT_SET_XTAL_SEL_TOK_V2_8197F(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) | BIT_XTAL_SEL_TOK_V2_8197F(v)) /* 2 REG_USB_SIE_INTF_8197F */ @@ -1736,32 +2118,41 @@ #define BIT_SHIFT_PCIE_MIO_WE_8197F 8 #define BIT_MASK_PCIE_MIO_WE_8197F 0xf -#define BIT_PCIE_MIO_WE_8197F(x) (((x) & BIT_MASK_PCIE_MIO_WE_8197F) << BIT_SHIFT_PCIE_MIO_WE_8197F) -#define BITS_PCIE_MIO_WE_8197F (BIT_MASK_PCIE_MIO_WE_8197F << BIT_SHIFT_PCIE_MIO_WE_8197F) +#define BIT_PCIE_MIO_WE_8197F(x) \ + (((x) & BIT_MASK_PCIE_MIO_WE_8197F) << BIT_SHIFT_PCIE_MIO_WE_8197F) +#define BITS_PCIE_MIO_WE_8197F \ + (BIT_MASK_PCIE_MIO_WE_8197F << BIT_SHIFT_PCIE_MIO_WE_8197F) #define BIT_CLEAR_PCIE_MIO_WE_8197F(x) ((x) & (~BITS_PCIE_MIO_WE_8197F)) -#define BIT_GET_PCIE_MIO_WE_8197F(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8197F) & BIT_MASK_PCIE_MIO_WE_8197F) -#define BIT_SET_PCIE_MIO_WE_8197F(x, v) (BIT_CLEAR_PCIE_MIO_WE_8197F(x) | BIT_PCIE_MIO_WE_8197F(v)) - +#define BIT_GET_PCIE_MIO_WE_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_WE_8197F) & BIT_MASK_PCIE_MIO_WE_8197F) +#define BIT_SET_PCIE_MIO_WE_8197F(x, v) \ + (BIT_CLEAR_PCIE_MIO_WE_8197F(x) | BIT_PCIE_MIO_WE_8197F(v)) #define BIT_SHIFT_PCIE_MIO_ADDR_8197F 0 #define BIT_MASK_PCIE_MIO_ADDR_8197F 0xff -#define BIT_PCIE_MIO_ADDR_8197F(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8197F) << BIT_SHIFT_PCIE_MIO_ADDR_8197F) -#define BITS_PCIE_MIO_ADDR_8197F (BIT_MASK_PCIE_MIO_ADDR_8197F << BIT_SHIFT_PCIE_MIO_ADDR_8197F) +#define BIT_PCIE_MIO_ADDR_8197F(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_8197F) << BIT_SHIFT_PCIE_MIO_ADDR_8197F) +#define BITS_PCIE_MIO_ADDR_8197F \ + (BIT_MASK_PCIE_MIO_ADDR_8197F << BIT_SHIFT_PCIE_MIO_ADDR_8197F) #define BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) ((x) & (~BITS_PCIE_MIO_ADDR_8197F)) -#define BIT_GET_PCIE_MIO_ADDR_8197F(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8197F) & BIT_MASK_PCIE_MIO_ADDR_8197F) -#define BIT_SET_PCIE_MIO_ADDR_8197F(x, v) (BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) | BIT_PCIE_MIO_ADDR_8197F(v)) - +#define BIT_GET_PCIE_MIO_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8197F) & BIT_MASK_PCIE_MIO_ADDR_8197F) +#define BIT_SET_PCIE_MIO_ADDR_8197F(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) | BIT_PCIE_MIO_ADDR_8197F(v)) /* 2 REG_PCIE_MIO_INTD_8197F */ #define BIT_SHIFT_PCIE_MIO_DATA_8197F 0 #define BIT_MASK_PCIE_MIO_DATA_8197F 0xffffffffL -#define BIT_PCIE_MIO_DATA_8197F(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8197F) << BIT_SHIFT_PCIE_MIO_DATA_8197F) -#define BITS_PCIE_MIO_DATA_8197F (BIT_MASK_PCIE_MIO_DATA_8197F << BIT_SHIFT_PCIE_MIO_DATA_8197F) +#define BIT_PCIE_MIO_DATA_8197F(x) \ + (((x) & BIT_MASK_PCIE_MIO_DATA_8197F) << BIT_SHIFT_PCIE_MIO_DATA_8197F) +#define BITS_PCIE_MIO_DATA_8197F \ + (BIT_MASK_PCIE_MIO_DATA_8197F << BIT_SHIFT_PCIE_MIO_DATA_8197F) #define BIT_CLEAR_PCIE_MIO_DATA_8197F(x) ((x) & (~BITS_PCIE_MIO_DATA_8197F)) -#define BIT_GET_PCIE_MIO_DATA_8197F(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8197F) & BIT_MASK_PCIE_MIO_DATA_8197F) -#define BIT_SET_PCIE_MIO_DATA_8197F(x, v) (BIT_CLEAR_PCIE_MIO_DATA_8197F(x) | BIT_PCIE_MIO_DATA_8197F(v)) - +#define BIT_GET_PCIE_MIO_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8197F) & BIT_MASK_PCIE_MIO_DATA_8197F) +#define BIT_SET_PCIE_MIO_DATA_8197F(x, v) \ + (BIT_CLEAR_PCIE_MIO_DATA_8197F(x) | BIT_PCIE_MIO_DATA_8197F(v)) /* 2 REG_WLRF1_8197F */ @@ -1769,11 +2160,15 @@ #define BIT_SHIFT_TRP_ICFG_8197F 28 #define BIT_MASK_TRP_ICFG_8197F 0xf -#define BIT_TRP_ICFG_8197F(x) (((x) & BIT_MASK_TRP_ICFG_8197F) << BIT_SHIFT_TRP_ICFG_8197F) -#define BITS_TRP_ICFG_8197F (BIT_MASK_TRP_ICFG_8197F << BIT_SHIFT_TRP_ICFG_8197F) +#define BIT_TRP_ICFG_8197F(x) \ + (((x) & BIT_MASK_TRP_ICFG_8197F) << BIT_SHIFT_TRP_ICFG_8197F) +#define BITS_TRP_ICFG_8197F \ + (BIT_MASK_TRP_ICFG_8197F << BIT_SHIFT_TRP_ICFG_8197F) #define BIT_CLEAR_TRP_ICFG_8197F(x) ((x) & (~BITS_TRP_ICFG_8197F)) -#define BIT_GET_TRP_ICFG_8197F(x) (((x) >> BIT_SHIFT_TRP_ICFG_8197F) & BIT_MASK_TRP_ICFG_8197F) -#define BIT_SET_TRP_ICFG_8197F(x, v) (BIT_CLEAR_TRP_ICFG_8197F(x) | BIT_TRP_ICFG_8197F(v)) +#define BIT_GET_TRP_ICFG_8197F(x) \ + (((x) >> BIT_SHIFT_TRP_ICFG_8197F) & BIT_MASK_TRP_ICFG_8197F) +#define BIT_SET_TRP_ICFG_8197F(x, v) \ + (BIT_CLEAR_TRP_ICFG_8197F(x) | BIT_TRP_ICFG_8197F(v)) #define BIT_RF_TYPE_ID_8197F BIT(27) #define BIT_BD_HCI_SEL_8197F BIT(26) @@ -1785,20 +2180,27 @@ #define BIT_SHIFT_VENDOR_ID_8197F 16 #define BIT_MASK_VENDOR_ID_8197F 0xf -#define BIT_VENDOR_ID_8197F(x) (((x) & BIT_MASK_VENDOR_ID_8197F) << BIT_SHIFT_VENDOR_ID_8197F) -#define BITS_VENDOR_ID_8197F (BIT_MASK_VENDOR_ID_8197F << BIT_SHIFT_VENDOR_ID_8197F) +#define BIT_VENDOR_ID_8197F(x) \ + (((x) & BIT_MASK_VENDOR_ID_8197F) << BIT_SHIFT_VENDOR_ID_8197F) +#define BITS_VENDOR_ID_8197F \ + (BIT_MASK_VENDOR_ID_8197F << BIT_SHIFT_VENDOR_ID_8197F) #define BIT_CLEAR_VENDOR_ID_8197F(x) ((x) & (~BITS_VENDOR_ID_8197F)) -#define BIT_GET_VENDOR_ID_8197F(x) (((x) >> BIT_SHIFT_VENDOR_ID_8197F) & BIT_MASK_VENDOR_ID_8197F) -#define BIT_SET_VENDOR_ID_8197F(x, v) (BIT_CLEAR_VENDOR_ID_8197F(x) | BIT_VENDOR_ID_8197F(v)) - +#define BIT_GET_VENDOR_ID_8197F(x) \ + (((x) >> BIT_SHIFT_VENDOR_ID_8197F) & BIT_MASK_VENDOR_ID_8197F) +#define BIT_SET_VENDOR_ID_8197F(x, v) \ + (BIT_CLEAR_VENDOR_ID_8197F(x) | BIT_VENDOR_ID_8197F(v)) #define BIT_SHIFT_CHIP_VER_8197F 12 #define BIT_MASK_CHIP_VER_8197F 0xf -#define BIT_CHIP_VER_8197F(x) (((x) & BIT_MASK_CHIP_VER_8197F) << BIT_SHIFT_CHIP_VER_8197F) -#define BITS_CHIP_VER_8197F (BIT_MASK_CHIP_VER_8197F << BIT_SHIFT_CHIP_VER_8197F) +#define BIT_CHIP_VER_8197F(x) \ + (((x) & BIT_MASK_CHIP_VER_8197F) << BIT_SHIFT_CHIP_VER_8197F) +#define BITS_CHIP_VER_8197F \ + (BIT_MASK_CHIP_VER_8197F << BIT_SHIFT_CHIP_VER_8197F) #define BIT_CLEAR_CHIP_VER_8197F(x) ((x) & (~BITS_CHIP_VER_8197F)) -#define BIT_GET_CHIP_VER_8197F(x) (((x) >> BIT_SHIFT_CHIP_VER_8197F) & BIT_MASK_CHIP_VER_8197F) -#define BIT_SET_CHIP_VER_8197F(x, v) (BIT_CLEAR_CHIP_VER_8197F(x) | BIT_CHIP_VER_8197F(v)) +#define BIT_GET_CHIP_VER_8197F(x) \ + (((x) >> BIT_SHIFT_CHIP_VER_8197F) & BIT_MASK_CHIP_VER_8197F) +#define BIT_SET_CHIP_VER_8197F(x, v) \ + (BIT_CLEAR_CHIP_VER_8197F(x) | BIT_CHIP_VER_8197F(v)) #define BIT_BD_MAC1_8197F BIT(10) #define BIT_BD_MAC2_8197F BIT(9) @@ -1816,21 +2218,29 @@ #define BIT_SHIFT_RF_RL_ID_8197F 28 #define BIT_MASK_RF_RL_ID_8197F 0xf -#define BIT_RF_RL_ID_8197F(x) (((x) & BIT_MASK_RF_RL_ID_8197F) << BIT_SHIFT_RF_RL_ID_8197F) -#define BITS_RF_RL_ID_8197F (BIT_MASK_RF_RL_ID_8197F << BIT_SHIFT_RF_RL_ID_8197F) +#define BIT_RF_RL_ID_8197F(x) \ + (((x) & BIT_MASK_RF_RL_ID_8197F) << BIT_SHIFT_RF_RL_ID_8197F) +#define BITS_RF_RL_ID_8197F \ + (BIT_MASK_RF_RL_ID_8197F << BIT_SHIFT_RF_RL_ID_8197F) #define BIT_CLEAR_RF_RL_ID_8197F(x) ((x) & (~BITS_RF_RL_ID_8197F)) -#define BIT_GET_RF_RL_ID_8197F(x) (((x) >> BIT_SHIFT_RF_RL_ID_8197F) & BIT_MASK_RF_RL_ID_8197F) -#define BIT_SET_RF_RL_ID_8197F(x, v) (BIT_CLEAR_RF_RL_ID_8197F(x) | BIT_RF_RL_ID_8197F(v)) +#define BIT_GET_RF_RL_ID_8197F(x) \ + (((x) >> BIT_SHIFT_RF_RL_ID_8197F) & BIT_MASK_RF_RL_ID_8197F) +#define BIT_SET_RF_RL_ID_8197F(x, v) \ + (BIT_CLEAR_RF_RL_ID_8197F(x) | BIT_RF_RL_ID_8197F(v)) #define BIT_HPHY_ICFG_8197F BIT(19) #define BIT_SHIFT_SEL_0XC0_8197F 16 #define BIT_MASK_SEL_0XC0_8197F 0x3 -#define BIT_SEL_0XC0_8197F(x) (((x) & BIT_MASK_SEL_0XC0_8197F) << BIT_SHIFT_SEL_0XC0_8197F) -#define BITS_SEL_0XC0_8197F (BIT_MASK_SEL_0XC0_8197F << BIT_SHIFT_SEL_0XC0_8197F) +#define BIT_SEL_0XC0_8197F(x) \ + (((x) & BIT_MASK_SEL_0XC0_8197F) << BIT_SHIFT_SEL_0XC0_8197F) +#define BITS_SEL_0XC0_8197F \ + (BIT_MASK_SEL_0XC0_8197F << BIT_SHIFT_SEL_0XC0_8197F) #define BIT_CLEAR_SEL_0XC0_8197F(x) ((x) & (~BITS_SEL_0XC0_8197F)) -#define BIT_GET_SEL_0XC0_8197F(x) (((x) >> BIT_SHIFT_SEL_0XC0_8197F) & BIT_MASK_SEL_0XC0_8197F) -#define BIT_SET_SEL_0XC0_8197F(x, v) (BIT_CLEAR_SEL_0XC0_8197F(x) | BIT_SEL_0XC0_8197F(v)) +#define BIT_GET_SEL_0XC0_8197F(x) \ + (((x) >> BIT_SHIFT_SEL_0XC0_8197F) & BIT_MASK_SEL_0XC0_8197F) +#define BIT_SET_SEL_0XC0_8197F(x, v) \ + (BIT_CLEAR_SEL_0XC0_8197F(x) | BIT_SEL_0XC0_8197F(v)) #define BIT_USB_OPERATION_MODE_8197F BIT(10) #define BIT_BT_PDN_8197F BIT(9) @@ -1840,30 +2250,38 @@ #define BIT_SHIFT_HCI_SEL_8197F 4 #define BIT_MASK_HCI_SEL_8197F 0x3 -#define BIT_HCI_SEL_8197F(x) (((x) & BIT_MASK_HCI_SEL_8197F) << BIT_SHIFT_HCI_SEL_8197F) +#define BIT_HCI_SEL_8197F(x) \ + (((x) & BIT_MASK_HCI_SEL_8197F) << BIT_SHIFT_HCI_SEL_8197F) #define BITS_HCI_SEL_8197F (BIT_MASK_HCI_SEL_8197F << BIT_SHIFT_HCI_SEL_8197F) #define BIT_CLEAR_HCI_SEL_8197F(x) ((x) & (~BITS_HCI_SEL_8197F)) -#define BIT_GET_HCI_SEL_8197F(x) (((x) >> BIT_SHIFT_HCI_SEL_8197F) & BIT_MASK_HCI_SEL_8197F) -#define BIT_SET_HCI_SEL_8197F(x, v) (BIT_CLEAR_HCI_SEL_8197F(x) | BIT_HCI_SEL_8197F(v)) - +#define BIT_GET_HCI_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_8197F) & BIT_MASK_HCI_SEL_8197F) +#define BIT_SET_HCI_SEL_8197F(x, v) \ + (BIT_CLEAR_HCI_SEL_8197F(x) | BIT_HCI_SEL_8197F(v)) #define BIT_SHIFT_PAD_HCI_SEL_8197F 2 #define BIT_MASK_PAD_HCI_SEL_8197F 0x3 -#define BIT_PAD_HCI_SEL_8197F(x) (((x) & BIT_MASK_PAD_HCI_SEL_8197F) << BIT_SHIFT_PAD_HCI_SEL_8197F) -#define BITS_PAD_HCI_SEL_8197F (BIT_MASK_PAD_HCI_SEL_8197F << BIT_SHIFT_PAD_HCI_SEL_8197F) +#define BIT_PAD_HCI_SEL_8197F(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_8197F) << BIT_SHIFT_PAD_HCI_SEL_8197F) +#define BITS_PAD_HCI_SEL_8197F \ + (BIT_MASK_PAD_HCI_SEL_8197F << BIT_SHIFT_PAD_HCI_SEL_8197F) #define BIT_CLEAR_PAD_HCI_SEL_8197F(x) ((x) & (~BITS_PAD_HCI_SEL_8197F)) -#define BIT_GET_PAD_HCI_SEL_8197F(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_8197F) & BIT_MASK_PAD_HCI_SEL_8197F) -#define BIT_SET_PAD_HCI_SEL_8197F(x, v) (BIT_CLEAR_PAD_HCI_SEL_8197F(x) | BIT_PAD_HCI_SEL_8197F(v)) - +#define BIT_GET_PAD_HCI_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_8197F) & BIT_MASK_PAD_HCI_SEL_8197F) +#define BIT_SET_PAD_HCI_SEL_8197F(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_8197F(x) | BIT_PAD_HCI_SEL_8197F(v)) #define BIT_SHIFT_EFS_HCI_SEL_8197F 0 #define BIT_MASK_EFS_HCI_SEL_8197F 0x3 -#define BIT_EFS_HCI_SEL_8197F(x) (((x) & BIT_MASK_EFS_HCI_SEL_8197F) << BIT_SHIFT_EFS_HCI_SEL_8197F) -#define BITS_EFS_HCI_SEL_8197F (BIT_MASK_EFS_HCI_SEL_8197F << BIT_SHIFT_EFS_HCI_SEL_8197F) +#define BIT_EFS_HCI_SEL_8197F(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL_8197F) << BIT_SHIFT_EFS_HCI_SEL_8197F) +#define BITS_EFS_HCI_SEL_8197F \ + (BIT_MASK_EFS_HCI_SEL_8197F << BIT_SHIFT_EFS_HCI_SEL_8197F) #define BIT_CLEAR_EFS_HCI_SEL_8197F(x) ((x) & (~BITS_EFS_HCI_SEL_8197F)) -#define BIT_GET_EFS_HCI_SEL_8197F(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_8197F) & BIT_MASK_EFS_HCI_SEL_8197F) -#define BIT_SET_EFS_HCI_SEL_8197F(x, v) (BIT_CLEAR_EFS_HCI_SEL_8197F(x) | BIT_EFS_HCI_SEL_8197F(v)) - +#define BIT_GET_EFS_HCI_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL_8197F) & BIT_MASK_EFS_HCI_SEL_8197F) +#define BIT_SET_EFS_HCI_SEL_8197F(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL_8197F(x) | BIT_EFS_HCI_SEL_8197F(v)) /* 2 REG_SYS_STATUS2_8197F */ #define BIT_SIO_ALDN_8197F BIT(19) @@ -1873,32 +2291,38 @@ #define BIT_SHIFT_EPVID1_8197F 8 #define BIT_MASK_EPVID1_8197F 0xff -#define BIT_EPVID1_8197F(x) (((x) & BIT_MASK_EPVID1_8197F) << BIT_SHIFT_EPVID1_8197F) +#define BIT_EPVID1_8197F(x) \ + (((x) & BIT_MASK_EPVID1_8197F) << BIT_SHIFT_EPVID1_8197F) #define BITS_EPVID1_8197F (BIT_MASK_EPVID1_8197F << BIT_SHIFT_EPVID1_8197F) #define BIT_CLEAR_EPVID1_8197F(x) ((x) & (~BITS_EPVID1_8197F)) -#define BIT_GET_EPVID1_8197F(x) (((x) >> BIT_SHIFT_EPVID1_8197F) & BIT_MASK_EPVID1_8197F) -#define BIT_SET_EPVID1_8197F(x, v) (BIT_CLEAR_EPVID1_8197F(x) | BIT_EPVID1_8197F(v)) - +#define BIT_GET_EPVID1_8197F(x) \ + (((x) >> BIT_SHIFT_EPVID1_8197F) & BIT_MASK_EPVID1_8197F) +#define BIT_SET_EPVID1_8197F(x, v) \ + (BIT_CLEAR_EPVID1_8197F(x) | BIT_EPVID1_8197F(v)) #define BIT_SHIFT_EPVID0_8197F 0 #define BIT_MASK_EPVID0_8197F 0xff -#define BIT_EPVID0_8197F(x) (((x) & BIT_MASK_EPVID0_8197F) << BIT_SHIFT_EPVID0_8197F) +#define BIT_EPVID0_8197F(x) \ + (((x) & BIT_MASK_EPVID0_8197F) << BIT_SHIFT_EPVID0_8197F) #define BITS_EPVID0_8197F (BIT_MASK_EPVID0_8197F << BIT_SHIFT_EPVID0_8197F) #define BIT_CLEAR_EPVID0_8197F(x) ((x) & (~BITS_EPVID0_8197F)) -#define BIT_GET_EPVID0_8197F(x) (((x) >> BIT_SHIFT_EPVID0_8197F) & BIT_MASK_EPVID0_8197F) -#define BIT_SET_EPVID0_8197F(x, v) (BIT_CLEAR_EPVID0_8197F(x) | BIT_EPVID0_8197F(v)) - +#define BIT_GET_EPVID0_8197F(x) \ + (((x) >> BIT_SHIFT_EPVID0_8197F) & BIT_MASK_EPVID0_8197F) +#define BIT_SET_EPVID0_8197F(x, v) \ + (BIT_CLEAR_EPVID0_8197F(x) | BIT_EPVID0_8197F(v)) /* 2 REG_SYS_CFG2_8197F */ #define BIT_SHIFT_HW_ID_8197F 0 #define BIT_MASK_HW_ID_8197F 0xff -#define BIT_HW_ID_8197F(x) (((x) & BIT_MASK_HW_ID_8197F) << BIT_SHIFT_HW_ID_8197F) +#define BIT_HW_ID_8197F(x) \ + (((x) & BIT_MASK_HW_ID_8197F) << BIT_SHIFT_HW_ID_8197F) #define BITS_HW_ID_8197F (BIT_MASK_HW_ID_8197F << BIT_SHIFT_HW_ID_8197F) #define BIT_CLEAR_HW_ID_8197F(x) ((x) & (~BITS_HW_ID_8197F)) -#define BIT_GET_HW_ID_8197F(x) (((x) >> BIT_SHIFT_HW_ID_8197F) & BIT_MASK_HW_ID_8197F) -#define BIT_SET_HW_ID_8197F(x, v) (BIT_CLEAR_HW_ID_8197F(x) | BIT_HW_ID_8197F(v)) - +#define BIT_GET_HW_ID_8197F(x) \ + (((x) >> BIT_SHIFT_HW_ID_8197F) & BIT_MASK_HW_ID_8197F) +#define BIT_SET_HW_ID_8197F(x, v) \ + (BIT_CLEAR_HW_ID_8197F(x) | BIT_HW_ID_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -1914,12 +2338,15 @@ #define BIT_SHIFT_CPU_DMEM_CON_8197F 0 #define BIT_MASK_CPU_DMEM_CON_8197F 0xff -#define BIT_CPU_DMEM_CON_8197F(x) (((x) & BIT_MASK_CPU_DMEM_CON_8197F) << BIT_SHIFT_CPU_DMEM_CON_8197F) -#define BITS_CPU_DMEM_CON_8197F (BIT_MASK_CPU_DMEM_CON_8197F << BIT_SHIFT_CPU_DMEM_CON_8197F) +#define BIT_CPU_DMEM_CON_8197F(x) \ + (((x) & BIT_MASK_CPU_DMEM_CON_8197F) << BIT_SHIFT_CPU_DMEM_CON_8197F) +#define BITS_CPU_DMEM_CON_8197F \ + (BIT_MASK_CPU_DMEM_CON_8197F << BIT_SHIFT_CPU_DMEM_CON_8197F) #define BIT_CLEAR_CPU_DMEM_CON_8197F(x) ((x) & (~BITS_CPU_DMEM_CON_8197F)) -#define BIT_GET_CPU_DMEM_CON_8197F(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8197F) & BIT_MASK_CPU_DMEM_CON_8197F) -#define BIT_SET_CPU_DMEM_CON_8197F(x, v) (BIT_CLEAR_CPU_DMEM_CON_8197F(x) | BIT_CPU_DMEM_CON_8197F(v)) - +#define BIT_GET_CPU_DMEM_CON_8197F(x) \ + (((x) >> BIT_SHIFT_CPU_DMEM_CON_8197F) & BIT_MASK_CPU_DMEM_CON_8197F) +#define BIT_SET_CPU_DMEM_CON_8197F(x, v) \ + (BIT_CLEAR_CPU_DMEM_CON_8197F(x) | BIT_CPU_DMEM_CON_8197F(v)) /* 2 REG_HIMR2_8197F */ #define BIT_BCNDMAINT_P4_MSK_8197F BIT(31) @@ -2034,86 +2461,129 @@ #define BIT_SHIFT_DBG_GPIO_BMUX_7_8197F 21 #define BIT_MASK_DBG_GPIO_BMUX_7_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_7_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_7_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) -#define BITS_DBG_GPIO_BMUX_7_8197F (BIT_MASK_DBG_GPIO_BMUX_7_8197F << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) +#define BIT_DBG_GPIO_BMUX_7_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_7_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) +#define BITS_DBG_GPIO_BMUX_7_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_7_8197F << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_7_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_7_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) & BIT_MASK_DBG_GPIO_BMUX_7_8197F) -#define BIT_SET_DBG_GPIO_BMUX_7_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) | BIT_DBG_GPIO_BMUX_7_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_7_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_7_8197F) +#define BIT_SET_DBG_GPIO_BMUX_7_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) | BIT_DBG_GPIO_BMUX_7_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_6_8197F 18 #define BIT_MASK_DBG_GPIO_BMUX_6_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_6_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_6_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) -#define BITS_DBG_GPIO_BMUX_6_8197F (BIT_MASK_DBG_GPIO_BMUX_6_8197F << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) +#define BIT_DBG_GPIO_BMUX_6_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_6_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) +#define BITS_DBG_GPIO_BMUX_6_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_6_8197F << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_6_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_6_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) & BIT_MASK_DBG_GPIO_BMUX_6_8197F) -#define BIT_SET_DBG_GPIO_BMUX_6_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) | BIT_DBG_GPIO_BMUX_6_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_6_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_6_8197F) +#define BIT_SET_DBG_GPIO_BMUX_6_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) | BIT_DBG_GPIO_BMUX_6_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_5_8197F 15 #define BIT_MASK_DBG_GPIO_BMUX_5_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_5_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_5_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) -#define BITS_DBG_GPIO_BMUX_5_8197F (BIT_MASK_DBG_GPIO_BMUX_5_8197F << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) +#define BIT_DBG_GPIO_BMUX_5_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_5_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) +#define BITS_DBG_GPIO_BMUX_5_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_5_8197F << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_5_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_5_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) & BIT_MASK_DBG_GPIO_BMUX_5_8197F) -#define BIT_SET_DBG_GPIO_BMUX_5_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) | BIT_DBG_GPIO_BMUX_5_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_5_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_5_8197F) +#define BIT_SET_DBG_GPIO_BMUX_5_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) | BIT_DBG_GPIO_BMUX_5_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_4_8197F 12 #define BIT_MASK_DBG_GPIO_BMUX_4_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_4_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_4_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) -#define BITS_DBG_GPIO_BMUX_4_8197F (BIT_MASK_DBG_GPIO_BMUX_4_8197F << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) +#define BIT_DBG_GPIO_BMUX_4_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_4_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) +#define BITS_DBG_GPIO_BMUX_4_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_4_8197F << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_4_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_4_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) & BIT_MASK_DBG_GPIO_BMUX_4_8197F) -#define BIT_SET_DBG_GPIO_BMUX_4_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) | BIT_DBG_GPIO_BMUX_4_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_4_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_4_8197F) +#define BIT_SET_DBG_GPIO_BMUX_4_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) | BIT_DBG_GPIO_BMUX_4_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_3_8197F 9 #define BIT_MASK_DBG_GPIO_BMUX_3_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_3_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_3_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) -#define BITS_DBG_GPIO_BMUX_3_8197F (BIT_MASK_DBG_GPIO_BMUX_3_8197F << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) +#define BIT_DBG_GPIO_BMUX_3_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_3_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) +#define BITS_DBG_GPIO_BMUX_3_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_3_8197F << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_3_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_3_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) & BIT_MASK_DBG_GPIO_BMUX_3_8197F) -#define BIT_SET_DBG_GPIO_BMUX_3_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) | BIT_DBG_GPIO_BMUX_3_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_3_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_3_8197F) +#define BIT_SET_DBG_GPIO_BMUX_3_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) | BIT_DBG_GPIO_BMUX_3_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_2_8197F 6 #define BIT_MASK_DBG_GPIO_BMUX_2_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_2_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_2_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) -#define BITS_DBG_GPIO_BMUX_2_8197F (BIT_MASK_DBG_GPIO_BMUX_2_8197F << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) +#define BIT_DBG_GPIO_BMUX_2_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_2_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) +#define BITS_DBG_GPIO_BMUX_2_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_2_8197F << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_2_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_2_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) & BIT_MASK_DBG_GPIO_BMUX_2_8197F) -#define BIT_SET_DBG_GPIO_BMUX_2_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) | BIT_DBG_GPIO_BMUX_2_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_2_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_2_8197F) +#define BIT_SET_DBG_GPIO_BMUX_2_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) | BIT_DBG_GPIO_BMUX_2_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_1_8197F 3 #define BIT_MASK_DBG_GPIO_BMUX_1_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_1_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_1_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) -#define BITS_DBG_GPIO_BMUX_1_8197F (BIT_MASK_DBG_GPIO_BMUX_1_8197F << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) +#define BIT_DBG_GPIO_BMUX_1_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_1_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) +#define BITS_DBG_GPIO_BMUX_1_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_1_8197F << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_1_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_1_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) & BIT_MASK_DBG_GPIO_BMUX_1_8197F) -#define BIT_SET_DBG_GPIO_BMUX_1_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) | BIT_DBG_GPIO_BMUX_1_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_1_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_1_8197F) +#define BIT_SET_DBG_GPIO_BMUX_1_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) | BIT_DBG_GPIO_BMUX_1_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_0_8197F 0 #define BIT_MASK_DBG_GPIO_BMUX_0_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_0_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_0_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) -#define BITS_DBG_GPIO_BMUX_0_8197F (BIT_MASK_DBG_GPIO_BMUX_0_8197F << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) +#define BIT_DBG_GPIO_BMUX_0_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_0_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) +#define BITS_DBG_GPIO_BMUX_0_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_0_8197F << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_0_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_0_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) & BIT_MASK_DBG_GPIO_BMUX_0_8197F) -#define BIT_SET_DBG_GPIO_BMUX_0_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) | BIT_DBG_GPIO_BMUX_0_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_0_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_0_8197F) +#define BIT_SET_DBG_GPIO_BMUX_0_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) | BIT_DBG_GPIO_BMUX_0_8197F(v)) /* 2 REG_FPGA_TAG_8197F (NO USE IN ASIC) */ #define BIT_SHIFT_FPGA_TAG_8197F 0 #define BIT_MASK_FPGA_TAG_8197F 0xffffffffL -#define BIT_FPGA_TAG_8197F(x) (((x) & BIT_MASK_FPGA_TAG_8197F) << BIT_SHIFT_FPGA_TAG_8197F) -#define BITS_FPGA_TAG_8197F (BIT_MASK_FPGA_TAG_8197F << BIT_SHIFT_FPGA_TAG_8197F) +#define BIT_FPGA_TAG_8197F(x) \ + (((x) & BIT_MASK_FPGA_TAG_8197F) << BIT_SHIFT_FPGA_TAG_8197F) +#define BITS_FPGA_TAG_8197F \ + (BIT_MASK_FPGA_TAG_8197F << BIT_SHIFT_FPGA_TAG_8197F) #define BIT_CLEAR_FPGA_TAG_8197F(x) ((x) & (~BITS_FPGA_TAG_8197F)) -#define BIT_GET_FPGA_TAG_8197F(x) (((x) >> BIT_SHIFT_FPGA_TAG_8197F) & BIT_MASK_FPGA_TAG_8197F) -#define BIT_SET_FPGA_TAG_8197F(x, v) (BIT_CLEAR_FPGA_TAG_8197F(x) | BIT_FPGA_TAG_8197F(v)) - +#define BIT_GET_FPGA_TAG_8197F(x) \ + (((x) >> BIT_SHIFT_FPGA_TAG_8197F) & BIT_MASK_FPGA_TAG_8197F) +#define BIT_SET_FPGA_TAG_8197F(x, v) \ + (BIT_CLEAR_FPGA_TAG_8197F(x) | BIT_FPGA_TAG_8197F(v)) /* 2 REG_WL_DSS_CTRL0_8197F */ #define BIT_WL_DSS_RSTN_8197F BIT(27) @@ -2122,12 +2592,18 @@ #define BIT_SHIFT_WL_DSS_COUNT_OUT_8197F 0 #define BIT_MASK_WL_DSS_COUNT_OUT_8197F 0xfffff -#define BIT_WL_DSS_COUNT_OUT_8197F(x) (((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) -#define BITS_WL_DSS_COUNT_OUT_8197F (BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) -#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) ((x) & (~BITS_WL_DSS_COUNT_OUT_8197F)) -#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x) (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) -#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v) (BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v)) - +#define BIT_WL_DSS_COUNT_OUT_8197F(x) \ + (((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) \ + << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) +#define BITS_WL_DSS_COUNT_OUT_8197F \ + (BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) +#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) \ + ((x) & (~BITS_WL_DSS_COUNT_OUT_8197F)) +#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x) \ + (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) & \ + BIT_MASK_WL_DSS_COUNT_OUT_8197F) +#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v) \ + (BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v)) /* 2 REG_WL_DSS_CTRL1_8197F */ #define BIT_WL_DSS_RSTN_8197F BIT(27) @@ -2137,21 +2613,29 @@ #define BIT_SHIFT_WL_DSS_RO_SEL_8197F 20 #define BIT_MASK_WL_DSS_RO_SEL_8197F 0x7 -#define BIT_WL_DSS_RO_SEL_8197F(x) (((x) & BIT_MASK_WL_DSS_RO_SEL_8197F) << BIT_SHIFT_WL_DSS_RO_SEL_8197F) -#define BITS_WL_DSS_RO_SEL_8197F (BIT_MASK_WL_DSS_RO_SEL_8197F << BIT_SHIFT_WL_DSS_RO_SEL_8197F) +#define BIT_WL_DSS_RO_SEL_8197F(x) \ + (((x) & BIT_MASK_WL_DSS_RO_SEL_8197F) << BIT_SHIFT_WL_DSS_RO_SEL_8197F) +#define BITS_WL_DSS_RO_SEL_8197F \ + (BIT_MASK_WL_DSS_RO_SEL_8197F << BIT_SHIFT_WL_DSS_RO_SEL_8197F) #define BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) ((x) & (~BITS_WL_DSS_RO_SEL_8197F)) -#define BIT_GET_WL_DSS_RO_SEL_8197F(x) (((x) >> BIT_SHIFT_WL_DSS_RO_SEL_8197F) & BIT_MASK_WL_DSS_RO_SEL_8197F) -#define BIT_SET_WL_DSS_RO_SEL_8197F(x, v) (BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) | BIT_WL_DSS_RO_SEL_8197F(v)) - +#define BIT_GET_WL_DSS_RO_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_WL_DSS_RO_SEL_8197F) & BIT_MASK_WL_DSS_RO_SEL_8197F) +#define BIT_SET_WL_DSS_RO_SEL_8197F(x, v) \ + (BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) | BIT_WL_DSS_RO_SEL_8197F(v)) #define BIT_SHIFT_WL_DSS_DATA_IN_8197F 0 #define BIT_MASK_WL_DSS_DATA_IN_8197F 0xfffff -#define BIT_WL_DSS_DATA_IN_8197F(x) (((x) & BIT_MASK_WL_DSS_DATA_IN_8197F) << BIT_SHIFT_WL_DSS_DATA_IN_8197F) -#define BITS_WL_DSS_DATA_IN_8197F (BIT_MASK_WL_DSS_DATA_IN_8197F << BIT_SHIFT_WL_DSS_DATA_IN_8197F) +#define BIT_WL_DSS_DATA_IN_8197F(x) \ + (((x) & BIT_MASK_WL_DSS_DATA_IN_8197F) \ + << BIT_SHIFT_WL_DSS_DATA_IN_8197F) +#define BITS_WL_DSS_DATA_IN_8197F \ + (BIT_MASK_WL_DSS_DATA_IN_8197F << BIT_SHIFT_WL_DSS_DATA_IN_8197F) #define BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) ((x) & (~BITS_WL_DSS_DATA_IN_8197F)) -#define BIT_GET_WL_DSS_DATA_IN_8197F(x) (((x) >> BIT_SHIFT_WL_DSS_DATA_IN_8197F) & BIT_MASK_WL_DSS_DATA_IN_8197F) -#define BIT_SET_WL_DSS_DATA_IN_8197F(x, v) (BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) | BIT_WL_DSS_DATA_IN_8197F(v)) - +#define BIT_GET_WL_DSS_DATA_IN_8197F(x) \ + (((x) >> BIT_SHIFT_WL_DSS_DATA_IN_8197F) & \ + BIT_MASK_WL_DSS_DATA_IN_8197F) +#define BIT_SET_WL_DSS_DATA_IN_8197F(x, v) \ + (BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) | BIT_WL_DSS_DATA_IN_8197F(v)) /* 2 REG_WL_DSS_STATUS1_8197F */ #define BIT_WL_DSS_READY_8197F BIT(21) @@ -2159,100 +2643,122 @@ #define BIT_SHIFT_WL_DSS_COUNT_OUT_8197F 0 #define BIT_MASK_WL_DSS_COUNT_OUT_8197F 0xfffff -#define BIT_WL_DSS_COUNT_OUT_8197F(x) (((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) -#define BITS_WL_DSS_COUNT_OUT_8197F (BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) -#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) ((x) & (~BITS_WL_DSS_COUNT_OUT_8197F)) -#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x) (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) -#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v) (BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v)) - +#define BIT_WL_DSS_COUNT_OUT_8197F(x) \ + (((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) \ + << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) +#define BITS_WL_DSS_COUNT_OUT_8197F \ + (BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) +#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) \ + ((x) & (~BITS_WL_DSS_COUNT_OUT_8197F)) +#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x) \ + (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) & \ + BIT_MASK_WL_DSS_COUNT_OUT_8197F) +#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v) \ + (BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v)) /* 2 REG_FW_DBG0_8197F */ #define BIT_SHIFT_FW_DBG0_8197F 0 #define BIT_MASK_FW_DBG0_8197F 0xffffffffL -#define BIT_FW_DBG0_8197F(x) (((x) & BIT_MASK_FW_DBG0_8197F) << BIT_SHIFT_FW_DBG0_8197F) +#define BIT_FW_DBG0_8197F(x) \ + (((x) & BIT_MASK_FW_DBG0_8197F) << BIT_SHIFT_FW_DBG0_8197F) #define BITS_FW_DBG0_8197F (BIT_MASK_FW_DBG0_8197F << BIT_SHIFT_FW_DBG0_8197F) #define BIT_CLEAR_FW_DBG0_8197F(x) ((x) & (~BITS_FW_DBG0_8197F)) -#define BIT_GET_FW_DBG0_8197F(x) (((x) >> BIT_SHIFT_FW_DBG0_8197F) & BIT_MASK_FW_DBG0_8197F) -#define BIT_SET_FW_DBG0_8197F(x, v) (BIT_CLEAR_FW_DBG0_8197F(x) | BIT_FW_DBG0_8197F(v)) - +#define BIT_GET_FW_DBG0_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG0_8197F) & BIT_MASK_FW_DBG0_8197F) +#define BIT_SET_FW_DBG0_8197F(x, v) \ + (BIT_CLEAR_FW_DBG0_8197F(x) | BIT_FW_DBG0_8197F(v)) /* 2 REG_FW_DBG1_8197F */ #define BIT_SHIFT_FW_DBG1_8197F 0 #define BIT_MASK_FW_DBG1_8197F 0xffffffffL -#define BIT_FW_DBG1_8197F(x) (((x) & BIT_MASK_FW_DBG1_8197F) << BIT_SHIFT_FW_DBG1_8197F) +#define BIT_FW_DBG1_8197F(x) \ + (((x) & BIT_MASK_FW_DBG1_8197F) << BIT_SHIFT_FW_DBG1_8197F) #define BITS_FW_DBG1_8197F (BIT_MASK_FW_DBG1_8197F << BIT_SHIFT_FW_DBG1_8197F) #define BIT_CLEAR_FW_DBG1_8197F(x) ((x) & (~BITS_FW_DBG1_8197F)) -#define BIT_GET_FW_DBG1_8197F(x) (((x) >> BIT_SHIFT_FW_DBG1_8197F) & BIT_MASK_FW_DBG1_8197F) -#define BIT_SET_FW_DBG1_8197F(x, v) (BIT_CLEAR_FW_DBG1_8197F(x) | BIT_FW_DBG1_8197F(v)) - +#define BIT_GET_FW_DBG1_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG1_8197F) & BIT_MASK_FW_DBG1_8197F) +#define BIT_SET_FW_DBG1_8197F(x, v) \ + (BIT_CLEAR_FW_DBG1_8197F(x) | BIT_FW_DBG1_8197F(v)) /* 2 REG_FW_DBG2_8197F */ #define BIT_SHIFT_FW_DBG2_8197F 0 #define BIT_MASK_FW_DBG2_8197F 0xffffffffL -#define BIT_FW_DBG2_8197F(x) (((x) & BIT_MASK_FW_DBG2_8197F) << BIT_SHIFT_FW_DBG2_8197F) +#define BIT_FW_DBG2_8197F(x) \ + (((x) & BIT_MASK_FW_DBG2_8197F) << BIT_SHIFT_FW_DBG2_8197F) #define BITS_FW_DBG2_8197F (BIT_MASK_FW_DBG2_8197F << BIT_SHIFT_FW_DBG2_8197F) #define BIT_CLEAR_FW_DBG2_8197F(x) ((x) & (~BITS_FW_DBG2_8197F)) -#define BIT_GET_FW_DBG2_8197F(x) (((x) >> BIT_SHIFT_FW_DBG2_8197F) & BIT_MASK_FW_DBG2_8197F) -#define BIT_SET_FW_DBG2_8197F(x, v) (BIT_CLEAR_FW_DBG2_8197F(x) | BIT_FW_DBG2_8197F(v)) - +#define BIT_GET_FW_DBG2_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG2_8197F) & BIT_MASK_FW_DBG2_8197F) +#define BIT_SET_FW_DBG2_8197F(x, v) \ + (BIT_CLEAR_FW_DBG2_8197F(x) | BIT_FW_DBG2_8197F(v)) /* 2 REG_FW_DBG3_8197F */ #define BIT_SHIFT_FW_DBG3_8197F 0 #define BIT_MASK_FW_DBG3_8197F 0xffffffffL -#define BIT_FW_DBG3_8197F(x) (((x) & BIT_MASK_FW_DBG3_8197F) << BIT_SHIFT_FW_DBG3_8197F) +#define BIT_FW_DBG3_8197F(x) \ + (((x) & BIT_MASK_FW_DBG3_8197F) << BIT_SHIFT_FW_DBG3_8197F) #define BITS_FW_DBG3_8197F (BIT_MASK_FW_DBG3_8197F << BIT_SHIFT_FW_DBG3_8197F) #define BIT_CLEAR_FW_DBG3_8197F(x) ((x) & (~BITS_FW_DBG3_8197F)) -#define BIT_GET_FW_DBG3_8197F(x) (((x) >> BIT_SHIFT_FW_DBG3_8197F) & BIT_MASK_FW_DBG3_8197F) -#define BIT_SET_FW_DBG3_8197F(x, v) (BIT_CLEAR_FW_DBG3_8197F(x) | BIT_FW_DBG3_8197F(v)) - +#define BIT_GET_FW_DBG3_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG3_8197F) & BIT_MASK_FW_DBG3_8197F) +#define BIT_SET_FW_DBG3_8197F(x, v) \ + (BIT_CLEAR_FW_DBG3_8197F(x) | BIT_FW_DBG3_8197F(v)) /* 2 REG_FW_DBG4_8197F */ #define BIT_SHIFT_FW_DBG4_8197F 0 #define BIT_MASK_FW_DBG4_8197F 0xffffffffL -#define BIT_FW_DBG4_8197F(x) (((x) & BIT_MASK_FW_DBG4_8197F) << BIT_SHIFT_FW_DBG4_8197F) +#define BIT_FW_DBG4_8197F(x) \ + (((x) & BIT_MASK_FW_DBG4_8197F) << BIT_SHIFT_FW_DBG4_8197F) #define BITS_FW_DBG4_8197F (BIT_MASK_FW_DBG4_8197F << BIT_SHIFT_FW_DBG4_8197F) #define BIT_CLEAR_FW_DBG4_8197F(x) ((x) & (~BITS_FW_DBG4_8197F)) -#define BIT_GET_FW_DBG4_8197F(x) (((x) >> BIT_SHIFT_FW_DBG4_8197F) & BIT_MASK_FW_DBG4_8197F) -#define BIT_SET_FW_DBG4_8197F(x, v) (BIT_CLEAR_FW_DBG4_8197F(x) | BIT_FW_DBG4_8197F(v)) - +#define BIT_GET_FW_DBG4_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG4_8197F) & BIT_MASK_FW_DBG4_8197F) +#define BIT_SET_FW_DBG4_8197F(x, v) \ + (BIT_CLEAR_FW_DBG4_8197F(x) | BIT_FW_DBG4_8197F(v)) /* 2 REG_FW_DBG5_8197F */ #define BIT_SHIFT_FW_DBG5_8197F 0 #define BIT_MASK_FW_DBG5_8197F 0xffffffffL -#define BIT_FW_DBG5_8197F(x) (((x) & BIT_MASK_FW_DBG5_8197F) << BIT_SHIFT_FW_DBG5_8197F) +#define BIT_FW_DBG5_8197F(x) \ + (((x) & BIT_MASK_FW_DBG5_8197F) << BIT_SHIFT_FW_DBG5_8197F) #define BITS_FW_DBG5_8197F (BIT_MASK_FW_DBG5_8197F << BIT_SHIFT_FW_DBG5_8197F) #define BIT_CLEAR_FW_DBG5_8197F(x) ((x) & (~BITS_FW_DBG5_8197F)) -#define BIT_GET_FW_DBG5_8197F(x) (((x) >> BIT_SHIFT_FW_DBG5_8197F) & BIT_MASK_FW_DBG5_8197F) -#define BIT_SET_FW_DBG5_8197F(x, v) (BIT_CLEAR_FW_DBG5_8197F(x) | BIT_FW_DBG5_8197F(v)) - +#define BIT_GET_FW_DBG5_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG5_8197F) & BIT_MASK_FW_DBG5_8197F) +#define BIT_SET_FW_DBG5_8197F(x, v) \ + (BIT_CLEAR_FW_DBG5_8197F(x) | BIT_FW_DBG5_8197F(v)) /* 2 REG_FW_DBG6_8197F */ #define BIT_SHIFT_FW_DBG6_8197F 0 #define BIT_MASK_FW_DBG6_8197F 0xffffffffL -#define BIT_FW_DBG6_8197F(x) (((x) & BIT_MASK_FW_DBG6_8197F) << BIT_SHIFT_FW_DBG6_8197F) +#define BIT_FW_DBG6_8197F(x) \ + (((x) & BIT_MASK_FW_DBG6_8197F) << BIT_SHIFT_FW_DBG6_8197F) #define BITS_FW_DBG6_8197F (BIT_MASK_FW_DBG6_8197F << BIT_SHIFT_FW_DBG6_8197F) #define BIT_CLEAR_FW_DBG6_8197F(x) ((x) & (~BITS_FW_DBG6_8197F)) -#define BIT_GET_FW_DBG6_8197F(x) (((x) >> BIT_SHIFT_FW_DBG6_8197F) & BIT_MASK_FW_DBG6_8197F) -#define BIT_SET_FW_DBG6_8197F(x, v) (BIT_CLEAR_FW_DBG6_8197F(x) | BIT_FW_DBG6_8197F(v)) - +#define BIT_GET_FW_DBG6_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG6_8197F) & BIT_MASK_FW_DBG6_8197F) +#define BIT_SET_FW_DBG6_8197F(x, v) \ + (BIT_CLEAR_FW_DBG6_8197F(x) | BIT_FW_DBG6_8197F(v)) /* 2 REG_FW_DBG7_8197F */ #define BIT_SHIFT_FW_DBG7_8197F 0 #define BIT_MASK_FW_DBG7_8197F 0xffffffffL -#define BIT_FW_DBG7_8197F(x) (((x) & BIT_MASK_FW_DBG7_8197F) << BIT_SHIFT_FW_DBG7_8197F) +#define BIT_FW_DBG7_8197F(x) \ + (((x) & BIT_MASK_FW_DBG7_8197F) << BIT_SHIFT_FW_DBG7_8197F) #define BITS_FW_DBG7_8197F (BIT_MASK_FW_DBG7_8197F << BIT_SHIFT_FW_DBG7_8197F) #define BIT_CLEAR_FW_DBG7_8197F(x) ((x) & (~BITS_FW_DBG7_8197F)) -#define BIT_GET_FW_DBG7_8197F(x) (((x) >> BIT_SHIFT_FW_DBG7_8197F) & BIT_MASK_FW_DBG7_8197F) -#define BIT_SET_FW_DBG7_8197F(x, v) (BIT_CLEAR_FW_DBG7_8197F(x) | BIT_FW_DBG7_8197F(v)) - +#define BIT_GET_FW_DBG7_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG7_8197F) & BIT_MASK_FW_DBG7_8197F) +#define BIT_SET_FW_DBG7_8197F(x, v) \ + (BIT_CLEAR_FW_DBG7_8197F(x) | BIT_FW_DBG7_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -2261,29 +2767,36 @@ #define BIT_SHIFT_LBMODE_8197F 24 #define BIT_MASK_LBMODE_8197F 0x1f -#define BIT_LBMODE_8197F(x) (((x) & BIT_MASK_LBMODE_8197F) << BIT_SHIFT_LBMODE_8197F) +#define BIT_LBMODE_8197F(x) \ + (((x) & BIT_MASK_LBMODE_8197F) << BIT_SHIFT_LBMODE_8197F) #define BITS_LBMODE_8197F (BIT_MASK_LBMODE_8197F << BIT_SHIFT_LBMODE_8197F) #define BIT_CLEAR_LBMODE_8197F(x) ((x) & (~BITS_LBMODE_8197F)) -#define BIT_GET_LBMODE_8197F(x) (((x) >> BIT_SHIFT_LBMODE_8197F) & BIT_MASK_LBMODE_8197F) -#define BIT_SET_LBMODE_8197F(x, v) (BIT_CLEAR_LBMODE_8197F(x) | BIT_LBMODE_8197F(v)) - +#define BIT_GET_LBMODE_8197F(x) \ + (((x) >> BIT_SHIFT_LBMODE_8197F) & BIT_MASK_LBMODE_8197F) +#define BIT_SET_LBMODE_8197F(x, v) \ + (BIT_CLEAR_LBMODE_8197F(x) | BIT_LBMODE_8197F(v)) #define BIT_SHIFT_NETYPE1_8197F 18 #define BIT_MASK_NETYPE1_8197F 0x3 -#define BIT_NETYPE1_8197F(x) (((x) & BIT_MASK_NETYPE1_8197F) << BIT_SHIFT_NETYPE1_8197F) +#define BIT_NETYPE1_8197F(x) \ + (((x) & BIT_MASK_NETYPE1_8197F) << BIT_SHIFT_NETYPE1_8197F) #define BITS_NETYPE1_8197F (BIT_MASK_NETYPE1_8197F << BIT_SHIFT_NETYPE1_8197F) #define BIT_CLEAR_NETYPE1_8197F(x) ((x) & (~BITS_NETYPE1_8197F)) -#define BIT_GET_NETYPE1_8197F(x) (((x) >> BIT_SHIFT_NETYPE1_8197F) & BIT_MASK_NETYPE1_8197F) -#define BIT_SET_NETYPE1_8197F(x, v) (BIT_CLEAR_NETYPE1_8197F(x) | BIT_NETYPE1_8197F(v)) - +#define BIT_GET_NETYPE1_8197F(x) \ + (((x) >> BIT_SHIFT_NETYPE1_8197F) & BIT_MASK_NETYPE1_8197F) +#define BIT_SET_NETYPE1_8197F(x, v) \ + (BIT_CLEAR_NETYPE1_8197F(x) | BIT_NETYPE1_8197F(v)) #define BIT_SHIFT_NETYPE0_8197F 16 #define BIT_MASK_NETYPE0_8197F 0x3 -#define BIT_NETYPE0_8197F(x) (((x) & BIT_MASK_NETYPE0_8197F) << BIT_SHIFT_NETYPE0_8197F) +#define BIT_NETYPE0_8197F(x) \ + (((x) & BIT_MASK_NETYPE0_8197F) << BIT_SHIFT_NETYPE0_8197F) #define BITS_NETYPE0_8197F (BIT_MASK_NETYPE0_8197F << BIT_SHIFT_NETYPE0_8197F) #define BIT_CLEAR_NETYPE0_8197F(x) ((x) & (~BITS_NETYPE0_8197F)) -#define BIT_GET_NETYPE0_8197F(x) (((x) >> BIT_SHIFT_NETYPE0_8197F) & BIT_MASK_NETYPE0_8197F) -#define BIT_SET_NETYPE0_8197F(x, v) (BIT_CLEAR_NETYPE0_8197F(x) | BIT_NETYPE0_8197F(v)) +#define BIT_GET_NETYPE0_8197F(x) \ + (((x) >> BIT_SHIFT_NETYPE0_8197F) & BIT_MASK_NETYPE0_8197F) +#define BIT_SET_NETYPE0_8197F(x, v) \ + (BIT_CLEAR_NETYPE0_8197F(x) | BIT_NETYPE0_8197F(v)) #define BIT_STAT_FUNC_RST_8197F BIT(13) #define BIT_I2C_MAILBOX_EN_8197F BIT(12) @@ -2307,57 +2820,75 @@ #define BIT_SHIFT_TXDMA_HIQ_MAP_8197F 14 #define BIT_MASK_TXDMA_HIQ_MAP_8197F 0x3 -#define BIT_TXDMA_HIQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8197F) << BIT_SHIFT_TXDMA_HIQ_MAP_8197F) -#define BITS_TXDMA_HIQ_MAP_8197F (BIT_MASK_TXDMA_HIQ_MAP_8197F << BIT_SHIFT_TXDMA_HIQ_MAP_8197F) +#define BIT_TXDMA_HIQ_MAP_8197F(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP_8197F) << BIT_SHIFT_TXDMA_HIQ_MAP_8197F) +#define BITS_TXDMA_HIQ_MAP_8197F \ + (BIT_MASK_TXDMA_HIQ_MAP_8197F << BIT_SHIFT_TXDMA_HIQ_MAP_8197F) #define BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8197F)) -#define BIT_GET_TXDMA_HIQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8197F) & BIT_MASK_TXDMA_HIQ_MAP_8197F) -#define BIT_SET_TXDMA_HIQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) | BIT_TXDMA_HIQ_MAP_8197F(v)) - +#define BIT_GET_TXDMA_HIQ_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8197F) & BIT_MASK_TXDMA_HIQ_MAP_8197F) +#define BIT_SET_TXDMA_HIQ_MAP_8197F(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) | BIT_TXDMA_HIQ_MAP_8197F(v)) #define BIT_SHIFT_TXDMA_MGQ_MAP_8197F 12 #define BIT_MASK_TXDMA_MGQ_MAP_8197F 0x3 -#define BIT_TXDMA_MGQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8197F) << BIT_SHIFT_TXDMA_MGQ_MAP_8197F) -#define BITS_TXDMA_MGQ_MAP_8197F (BIT_MASK_TXDMA_MGQ_MAP_8197F << BIT_SHIFT_TXDMA_MGQ_MAP_8197F) +#define BIT_TXDMA_MGQ_MAP_8197F(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP_8197F) << BIT_SHIFT_TXDMA_MGQ_MAP_8197F) +#define BITS_TXDMA_MGQ_MAP_8197F \ + (BIT_MASK_TXDMA_MGQ_MAP_8197F << BIT_SHIFT_TXDMA_MGQ_MAP_8197F) #define BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8197F)) -#define BIT_GET_TXDMA_MGQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8197F) & BIT_MASK_TXDMA_MGQ_MAP_8197F) -#define BIT_SET_TXDMA_MGQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) | BIT_TXDMA_MGQ_MAP_8197F(v)) - +#define BIT_GET_TXDMA_MGQ_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8197F) & BIT_MASK_TXDMA_MGQ_MAP_8197F) +#define BIT_SET_TXDMA_MGQ_MAP_8197F(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) | BIT_TXDMA_MGQ_MAP_8197F(v)) #define BIT_SHIFT_TXDMA_BKQ_MAP_8197F 10 #define BIT_MASK_TXDMA_BKQ_MAP_8197F 0x3 -#define BIT_TXDMA_BKQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8197F) << BIT_SHIFT_TXDMA_BKQ_MAP_8197F) -#define BITS_TXDMA_BKQ_MAP_8197F (BIT_MASK_TXDMA_BKQ_MAP_8197F << BIT_SHIFT_TXDMA_BKQ_MAP_8197F) +#define BIT_TXDMA_BKQ_MAP_8197F(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP_8197F) << BIT_SHIFT_TXDMA_BKQ_MAP_8197F) +#define BITS_TXDMA_BKQ_MAP_8197F \ + (BIT_MASK_TXDMA_BKQ_MAP_8197F << BIT_SHIFT_TXDMA_BKQ_MAP_8197F) #define BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8197F)) -#define BIT_GET_TXDMA_BKQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8197F) & BIT_MASK_TXDMA_BKQ_MAP_8197F) -#define BIT_SET_TXDMA_BKQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) | BIT_TXDMA_BKQ_MAP_8197F(v)) - +#define BIT_GET_TXDMA_BKQ_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8197F) & BIT_MASK_TXDMA_BKQ_MAP_8197F) +#define BIT_SET_TXDMA_BKQ_MAP_8197F(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) | BIT_TXDMA_BKQ_MAP_8197F(v)) #define BIT_SHIFT_TXDMA_BEQ_MAP_8197F 8 #define BIT_MASK_TXDMA_BEQ_MAP_8197F 0x3 -#define BIT_TXDMA_BEQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8197F) << BIT_SHIFT_TXDMA_BEQ_MAP_8197F) -#define BITS_TXDMA_BEQ_MAP_8197F (BIT_MASK_TXDMA_BEQ_MAP_8197F << BIT_SHIFT_TXDMA_BEQ_MAP_8197F) +#define BIT_TXDMA_BEQ_MAP_8197F(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP_8197F) << BIT_SHIFT_TXDMA_BEQ_MAP_8197F) +#define BITS_TXDMA_BEQ_MAP_8197F \ + (BIT_MASK_TXDMA_BEQ_MAP_8197F << BIT_SHIFT_TXDMA_BEQ_MAP_8197F) #define BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8197F)) -#define BIT_GET_TXDMA_BEQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8197F) & BIT_MASK_TXDMA_BEQ_MAP_8197F) -#define BIT_SET_TXDMA_BEQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) | BIT_TXDMA_BEQ_MAP_8197F(v)) - +#define BIT_GET_TXDMA_BEQ_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8197F) & BIT_MASK_TXDMA_BEQ_MAP_8197F) +#define BIT_SET_TXDMA_BEQ_MAP_8197F(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) | BIT_TXDMA_BEQ_MAP_8197F(v)) #define BIT_SHIFT_TXDMA_VIQ_MAP_8197F 6 #define BIT_MASK_TXDMA_VIQ_MAP_8197F 0x3 -#define BIT_TXDMA_VIQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8197F) << BIT_SHIFT_TXDMA_VIQ_MAP_8197F) -#define BITS_TXDMA_VIQ_MAP_8197F (BIT_MASK_TXDMA_VIQ_MAP_8197F << BIT_SHIFT_TXDMA_VIQ_MAP_8197F) +#define BIT_TXDMA_VIQ_MAP_8197F(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP_8197F) << BIT_SHIFT_TXDMA_VIQ_MAP_8197F) +#define BITS_TXDMA_VIQ_MAP_8197F \ + (BIT_MASK_TXDMA_VIQ_MAP_8197F << BIT_SHIFT_TXDMA_VIQ_MAP_8197F) #define BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8197F)) -#define BIT_GET_TXDMA_VIQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8197F) & BIT_MASK_TXDMA_VIQ_MAP_8197F) -#define BIT_SET_TXDMA_VIQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) | BIT_TXDMA_VIQ_MAP_8197F(v)) - +#define BIT_GET_TXDMA_VIQ_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8197F) & BIT_MASK_TXDMA_VIQ_MAP_8197F) +#define BIT_SET_TXDMA_VIQ_MAP_8197F(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) | BIT_TXDMA_VIQ_MAP_8197F(v)) #define BIT_SHIFT_TXDMA_VOQ_MAP_8197F 4 #define BIT_MASK_TXDMA_VOQ_MAP_8197F 0x3 -#define BIT_TXDMA_VOQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8197F) << BIT_SHIFT_TXDMA_VOQ_MAP_8197F) -#define BITS_TXDMA_VOQ_MAP_8197F (BIT_MASK_TXDMA_VOQ_MAP_8197F << BIT_SHIFT_TXDMA_VOQ_MAP_8197F) +#define BIT_TXDMA_VOQ_MAP_8197F(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP_8197F) << BIT_SHIFT_TXDMA_VOQ_MAP_8197F) +#define BITS_TXDMA_VOQ_MAP_8197F \ + (BIT_MASK_TXDMA_VOQ_MAP_8197F << BIT_SHIFT_TXDMA_VOQ_MAP_8197F) #define BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8197F)) -#define BIT_GET_TXDMA_VOQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8197F) & BIT_MASK_TXDMA_VOQ_MAP_8197F) -#define BIT_SET_TXDMA_VOQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) | BIT_TXDMA_VOQ_MAP_8197F(v)) - +#define BIT_GET_TXDMA_VOQ_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8197F) & BIT_MASK_TXDMA_VOQ_MAP_8197F) +#define BIT_SET_TXDMA_VOQ_MAP_8197F(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) | BIT_TXDMA_VOQ_MAP_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_RXDMA_AGG_EN_8197F BIT(2) @@ -2368,21 +2899,31 @@ #define BIT_SHIFT_RXFFOVFL_RSV_V2_8197F 8 #define BIT_MASK_RXFFOVFL_RSV_V2_8197F 0xf -#define BIT_RXFFOVFL_RSV_V2_8197F(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8197F) << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) -#define BITS_RXFFOVFL_RSV_V2_8197F (BIT_MASK_RXFFOVFL_RSV_V2_8197F << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) +#define BIT_RXFFOVFL_RSV_V2_8197F(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8197F) \ + << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) +#define BITS_RXFFOVFL_RSV_V2_8197F \ + (BIT_MASK_RXFFOVFL_RSV_V2_8197F << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) #define BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8197F)) -#define BIT_GET_RXFFOVFL_RSV_V2_8197F(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) & BIT_MASK_RXFFOVFL_RSV_V2_8197F) -#define BIT_SET_RXFFOVFL_RSV_V2_8197F(x, v) (BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) | BIT_RXFFOVFL_RSV_V2_8197F(v)) - +#define BIT_GET_RXFFOVFL_RSV_V2_8197F(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) & \ + BIT_MASK_RXFFOVFL_RSV_V2_8197F) +#define BIT_SET_RXFFOVFL_RSV_V2_8197F(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) | BIT_RXFFOVFL_RSV_V2_8197F(v)) #define BIT_SHIFT_TXPKTBUF_PGBNDY_8197F 0 #define BIT_MASK_TXPKTBUF_PGBNDY_8197F 0xff -#define BIT_TXPKTBUF_PGBNDY_8197F(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8197F) << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) -#define BITS_TXPKTBUF_PGBNDY_8197F (BIT_MASK_TXPKTBUF_PGBNDY_8197F << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) +#define BIT_TXPKTBUF_PGBNDY_8197F(x) \ + (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8197F) \ + << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) +#define BITS_TXPKTBUF_PGBNDY_8197F \ + (BIT_MASK_TXPKTBUF_PGBNDY_8197F << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) #define BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) ((x) & (~BITS_TXPKTBUF_PGBNDY_8197F)) -#define BIT_GET_TXPKTBUF_PGBNDY_8197F(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) & BIT_MASK_TXPKTBUF_PGBNDY_8197F) -#define BIT_SET_TXPKTBUF_PGBNDY_8197F(x, v) (BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) | BIT_TXPKTBUF_PGBNDY_8197F(v)) - +#define BIT_GET_TXPKTBUF_PGBNDY_8197F(x) \ + (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) & \ + BIT_MASK_TXPKTBUF_PGBNDY_8197F) +#define BIT_SET_TXPKTBUF_PGBNDY_8197F(x, v) \ + (BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) | BIT_TXPKTBUF_PGBNDY_8197F(v)) /* 2 REG_PTA_I2C_MBOX_8197F */ @@ -2390,30 +2931,44 @@ #define BIT_SHIFT_I2C_M_STATUS_8197F 8 #define BIT_MASK_I2C_M_STATUS_8197F 0xf -#define BIT_I2C_M_STATUS_8197F(x) (((x) & BIT_MASK_I2C_M_STATUS_8197F) << BIT_SHIFT_I2C_M_STATUS_8197F) -#define BITS_I2C_M_STATUS_8197F (BIT_MASK_I2C_M_STATUS_8197F << BIT_SHIFT_I2C_M_STATUS_8197F) +#define BIT_I2C_M_STATUS_8197F(x) \ + (((x) & BIT_MASK_I2C_M_STATUS_8197F) << BIT_SHIFT_I2C_M_STATUS_8197F) +#define BITS_I2C_M_STATUS_8197F \ + (BIT_MASK_I2C_M_STATUS_8197F << BIT_SHIFT_I2C_M_STATUS_8197F) #define BIT_CLEAR_I2C_M_STATUS_8197F(x) ((x) & (~BITS_I2C_M_STATUS_8197F)) -#define BIT_GET_I2C_M_STATUS_8197F(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8197F) & BIT_MASK_I2C_M_STATUS_8197F) -#define BIT_SET_I2C_M_STATUS_8197F(x, v) (BIT_CLEAR_I2C_M_STATUS_8197F(x) | BIT_I2C_M_STATUS_8197F(v)) - +#define BIT_GET_I2C_M_STATUS_8197F(x) \ + (((x) >> BIT_SHIFT_I2C_M_STATUS_8197F) & BIT_MASK_I2C_M_STATUS_8197F) +#define BIT_SET_I2C_M_STATUS_8197F(x, v) \ + (BIT_CLEAR_I2C_M_STATUS_8197F(x) | BIT_I2C_M_STATUS_8197F(v)) #define BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F 4 #define BIT_MASK_I2C_M_BUS_GNT_FW_8197F 0x7 -#define BIT_I2C_M_BUS_GNT_FW_8197F(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8197F) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) -#define BITS_I2C_M_BUS_GNT_FW_8197F (BIT_MASK_I2C_M_BUS_GNT_FW_8197F << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) -#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) ((x) & (~BITS_I2C_M_BUS_GNT_FW_8197F)) -#define BIT_GET_I2C_M_BUS_GNT_FW_8197F(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) & BIT_MASK_I2C_M_BUS_GNT_FW_8197F) -#define BIT_SET_I2C_M_BUS_GNT_FW_8197F(x, v) (BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) | BIT_I2C_M_BUS_GNT_FW_8197F(v)) +#define BIT_I2C_M_BUS_GNT_FW_8197F(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8197F) \ + << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) +#define BITS_I2C_M_BUS_GNT_FW_8197F \ + (BIT_MASK_I2C_M_BUS_GNT_FW_8197F << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) \ + ((x) & (~BITS_I2C_M_BUS_GNT_FW_8197F)) +#define BIT_GET_I2C_M_BUS_GNT_FW_8197F(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) & \ + BIT_MASK_I2C_M_BUS_GNT_FW_8197F) +#define BIT_SET_I2C_M_BUS_GNT_FW_8197F(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) | BIT_I2C_M_BUS_GNT_FW_8197F(v)) #define BIT_I2C_M_GNT_FW_8197F BIT(3) #define BIT_SHIFT_I2C_M_SPEED_8197F 1 #define BIT_MASK_I2C_M_SPEED_8197F 0x3 -#define BIT_I2C_M_SPEED_8197F(x) (((x) & BIT_MASK_I2C_M_SPEED_8197F) << BIT_SHIFT_I2C_M_SPEED_8197F) -#define BITS_I2C_M_SPEED_8197F (BIT_MASK_I2C_M_SPEED_8197F << BIT_SHIFT_I2C_M_SPEED_8197F) +#define BIT_I2C_M_SPEED_8197F(x) \ + (((x) & BIT_MASK_I2C_M_SPEED_8197F) << BIT_SHIFT_I2C_M_SPEED_8197F) +#define BITS_I2C_M_SPEED_8197F \ + (BIT_MASK_I2C_M_SPEED_8197F << BIT_SHIFT_I2C_M_SPEED_8197F) #define BIT_CLEAR_I2C_M_SPEED_8197F(x) ((x) & (~BITS_I2C_M_SPEED_8197F)) -#define BIT_GET_I2C_M_SPEED_8197F(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8197F) & BIT_MASK_I2C_M_SPEED_8197F) -#define BIT_SET_I2C_M_SPEED_8197F(x, v) (BIT_CLEAR_I2C_M_SPEED_8197F(x) | BIT_I2C_M_SPEED_8197F(v)) +#define BIT_GET_I2C_M_SPEED_8197F(x) \ + (((x) >> BIT_SHIFT_I2C_M_SPEED_8197F) & BIT_MASK_I2C_M_SPEED_8197F) +#define BIT_SET_I2C_M_SPEED_8197F(x, v) \ + (BIT_CLEAR_I2C_M_SPEED_8197F(x) | BIT_I2C_M_SPEED_8197F(v)) #define BIT_I2C_M_UNLOCK_8197F BIT(0) @@ -2423,12 +2978,15 @@ #define BIT_SHIFT_RXFF0_BNDY_V2_8197F 0 #define BIT_MASK_RXFF0_BNDY_V2_8197F 0x3ffff -#define BIT_RXFF0_BNDY_V2_8197F(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8197F) << BIT_SHIFT_RXFF0_BNDY_V2_8197F) -#define BITS_RXFF0_BNDY_V2_8197F (BIT_MASK_RXFF0_BNDY_V2_8197F << BIT_SHIFT_RXFF0_BNDY_V2_8197F) +#define BIT_RXFF0_BNDY_V2_8197F(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V2_8197F) << BIT_SHIFT_RXFF0_BNDY_V2_8197F) +#define BITS_RXFF0_BNDY_V2_8197F \ + (BIT_MASK_RXFF0_BNDY_V2_8197F << BIT_SHIFT_RXFF0_BNDY_V2_8197F) #define BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) ((x) & (~BITS_RXFF0_BNDY_V2_8197F)) -#define BIT_GET_RXFF0_BNDY_V2_8197F(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8197F) & BIT_MASK_RXFF0_BNDY_V2_8197F) -#define BIT_SET_RXFF0_BNDY_V2_8197F(x, v) (BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) | BIT_RXFF0_BNDY_V2_8197F(v)) - +#define BIT_GET_RXFF0_BNDY_V2_8197F(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8197F) & BIT_MASK_RXFF0_BNDY_V2_8197F) +#define BIT_SET_RXFF0_BNDY_V2_8197F(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) | BIT_RXFF0_BNDY_V2_8197F(v)) /* 2 REG_FE1IMR_8197F */ #define BIT_BB_STOP_RX_INT_EN_8197F BIT(29) @@ -2497,12 +3055,15 @@ #define BIT_SHIFT_CPWM_MOD_8197F 24 #define BIT_MASK_CPWM_MOD_8197F 0x7f -#define BIT_CPWM_MOD_8197F(x) (((x) & BIT_MASK_CPWM_MOD_8197F) << BIT_SHIFT_CPWM_MOD_8197F) -#define BITS_CPWM_MOD_8197F (BIT_MASK_CPWM_MOD_8197F << BIT_SHIFT_CPWM_MOD_8197F) +#define BIT_CPWM_MOD_8197F(x) \ + (((x) & BIT_MASK_CPWM_MOD_8197F) << BIT_SHIFT_CPWM_MOD_8197F) +#define BITS_CPWM_MOD_8197F \ + (BIT_MASK_CPWM_MOD_8197F << BIT_SHIFT_CPWM_MOD_8197F) #define BIT_CLEAR_CPWM_MOD_8197F(x) ((x) & (~BITS_CPWM_MOD_8197F)) -#define BIT_GET_CPWM_MOD_8197F(x) (((x) >> BIT_SHIFT_CPWM_MOD_8197F) & BIT_MASK_CPWM_MOD_8197F) -#define BIT_SET_CPWM_MOD_8197F(x, v) (BIT_CLEAR_CPWM_MOD_8197F(x) | BIT_CPWM_MOD_8197F(v)) - +#define BIT_GET_CPWM_MOD_8197F(x) \ + (((x) >> BIT_SHIFT_CPWM_MOD_8197F) & BIT_MASK_CPWM_MOD_8197F) +#define BIT_SET_CPWM_MOD_8197F(x, v) \ + (BIT_CLEAR_CPWM_MOD_8197F(x) | BIT_CPWM_MOD_8197F(v)) /* 2 REG_FWIMR_8197F */ #define BIT_FS_TXBCNOK_MB7_INT_EN_8197F BIT(31) @@ -2524,7 +3085,8 @@ #define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN_8197F BIT(15) #define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8197F BIT(13) #define BIT_FS_MGNTQFF_TO_INT_EN_8197F BIT(12) -#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN_8197F BIT(11) +#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN_8197F \ + BIT(11) #define BIT_FS_DDMA1_HP_INT_EN_8197F BIT(10) #define BIT_FS_DDMA0_LP_INT_EN_8197F BIT(9) #define BIT_FS_DDMA0_HP_INT_EN_8197F BIT(8) @@ -2618,11 +3180,17 @@ #define BIT_SHIFT_PKTBUF_WRITE_EN_8197F 24 #define BIT_MASK_PKTBUF_WRITE_EN_8197F 0xff -#define BIT_PKTBUF_WRITE_EN_8197F(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8197F) << BIT_SHIFT_PKTBUF_WRITE_EN_8197F) -#define BITS_PKTBUF_WRITE_EN_8197F (BIT_MASK_PKTBUF_WRITE_EN_8197F << BIT_SHIFT_PKTBUF_WRITE_EN_8197F) +#define BIT_PKTBUF_WRITE_EN_8197F(x) \ + (((x) & BIT_MASK_PKTBUF_WRITE_EN_8197F) \ + << BIT_SHIFT_PKTBUF_WRITE_EN_8197F) +#define BITS_PKTBUF_WRITE_EN_8197F \ + (BIT_MASK_PKTBUF_WRITE_EN_8197F << BIT_SHIFT_PKTBUF_WRITE_EN_8197F) #define BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8197F)) -#define BIT_GET_PKTBUF_WRITE_EN_8197F(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8197F) & BIT_MASK_PKTBUF_WRITE_EN_8197F) -#define BIT_SET_PKTBUF_WRITE_EN_8197F(x, v) (BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) | BIT_PKTBUF_WRITE_EN_8197F(v)) +#define BIT_GET_PKTBUF_WRITE_EN_8197F(x) \ + (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8197F) & \ + BIT_MASK_PKTBUF_WRITE_EN_8197F) +#define BIT_SET_PKTBUF_WRITE_EN_8197F(x, v) \ + (BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) | BIT_PKTBUF_WRITE_EN_8197F(v)) #define BIT_TXRPTBUF_DBG_8197F BIT(23) @@ -2632,55 +3200,81 @@ #define BIT_SHIFT_PKTBUF_DBG_ADDR_8197F 0 #define BIT_MASK_PKTBUF_DBG_ADDR_8197F 0x1fff -#define BIT_PKTBUF_DBG_ADDR_8197F(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8197F) << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) -#define BITS_PKTBUF_DBG_ADDR_8197F (BIT_MASK_PKTBUF_DBG_ADDR_8197F << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) +#define BIT_PKTBUF_DBG_ADDR_8197F(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8197F) \ + << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) +#define BITS_PKTBUF_DBG_ADDR_8197F \ + (BIT_MASK_PKTBUF_DBG_ADDR_8197F << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) #define BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8197F)) -#define BIT_GET_PKTBUF_DBG_ADDR_8197F(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) & BIT_MASK_PKTBUF_DBG_ADDR_8197F) -#define BIT_SET_PKTBUF_DBG_ADDR_8197F(x, v) (BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) | BIT_PKTBUF_DBG_ADDR_8197F(v)) - +#define BIT_GET_PKTBUF_DBG_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) & \ + BIT_MASK_PKTBUF_DBG_ADDR_8197F) +#define BIT_SET_PKTBUF_DBG_ADDR_8197F(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) | BIT_PKTBUF_DBG_ADDR_8197F(v)) /* 2 REG_PKTBUF_DBG_DATA_L_8197F */ #define BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F 0 #define BIT_MASK_PKTBUF_DBG_DATA_L_8197F 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_L_8197F(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8197F) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) -#define BITS_PKTBUF_DBG_DATA_L_8197F (BIT_MASK_PKTBUF_DBG_DATA_L_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) -#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) ((x) & (~BITS_PKTBUF_DBG_DATA_L_8197F)) -#define BIT_GET_PKTBUF_DBG_DATA_L_8197F(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) & BIT_MASK_PKTBUF_DBG_DATA_L_8197F) -#define BIT_SET_PKTBUF_DBG_DATA_L_8197F(x, v) (BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) | BIT_PKTBUF_DBG_DATA_L_8197F(v)) - +#define BIT_PKTBUF_DBG_DATA_L_8197F(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8197F) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) +#define BITS_PKTBUF_DBG_DATA_L_8197F \ + (BIT_MASK_PKTBUF_DBG_DATA_L_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_L_8197F)) +#define BIT_GET_PKTBUF_DBG_DATA_L_8197F(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) & \ + BIT_MASK_PKTBUF_DBG_DATA_L_8197F) +#define BIT_SET_PKTBUF_DBG_DATA_L_8197F(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) | BIT_PKTBUF_DBG_DATA_L_8197F(v)) /* 2 REG_PKTBUF_DBG_DATA_H_8197F */ #define BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F 0 #define BIT_MASK_PKTBUF_DBG_DATA_H_8197F 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_H_8197F(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8197F) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) -#define BITS_PKTBUF_DBG_DATA_H_8197F (BIT_MASK_PKTBUF_DBG_DATA_H_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) -#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) ((x) & (~BITS_PKTBUF_DBG_DATA_H_8197F)) -#define BIT_GET_PKTBUF_DBG_DATA_H_8197F(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) & BIT_MASK_PKTBUF_DBG_DATA_H_8197F) -#define BIT_SET_PKTBUF_DBG_DATA_H_8197F(x, v) (BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) | BIT_PKTBUF_DBG_DATA_H_8197F(v)) - +#define BIT_PKTBUF_DBG_DATA_H_8197F(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8197F) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) +#define BITS_PKTBUF_DBG_DATA_H_8197F \ + (BIT_MASK_PKTBUF_DBG_DATA_H_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_H_8197F)) +#define BIT_GET_PKTBUF_DBG_DATA_H_8197F(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) & \ + BIT_MASK_PKTBUF_DBG_DATA_H_8197F) +#define BIT_SET_PKTBUF_DBG_DATA_H_8197F(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) | BIT_PKTBUF_DBG_DATA_H_8197F(v)) /* 2 REG_CPWM2_8197F */ #define BIT_SHIFT_L0S_TO_RCVY_NUM_8197F 16 #define BIT_MASK_L0S_TO_RCVY_NUM_8197F 0xff -#define BIT_L0S_TO_RCVY_NUM_8197F(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8197F) << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) -#define BITS_L0S_TO_RCVY_NUM_8197F (BIT_MASK_L0S_TO_RCVY_NUM_8197F << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) +#define BIT_L0S_TO_RCVY_NUM_8197F(x) \ + (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8197F) \ + << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) +#define BITS_L0S_TO_RCVY_NUM_8197F \ + (BIT_MASK_L0S_TO_RCVY_NUM_8197F << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) #define BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8197F)) -#define BIT_GET_L0S_TO_RCVY_NUM_8197F(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) & BIT_MASK_L0S_TO_RCVY_NUM_8197F) -#define BIT_SET_L0S_TO_RCVY_NUM_8197F(x, v) (BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) | BIT_L0S_TO_RCVY_NUM_8197F(v)) +#define BIT_GET_L0S_TO_RCVY_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) & \ + BIT_MASK_L0S_TO_RCVY_NUM_8197F) +#define BIT_SET_L0S_TO_RCVY_NUM_8197F(x, v) \ + (BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) | BIT_L0S_TO_RCVY_NUM_8197F(v)) #define BIT_CPWM2_TOGGLING_8197F BIT(15) #define BIT_SHIFT_CPWM2_MOD_8197F 0 #define BIT_MASK_CPWM2_MOD_8197F 0x7fff -#define BIT_CPWM2_MOD_8197F(x) (((x) & BIT_MASK_CPWM2_MOD_8197F) << BIT_SHIFT_CPWM2_MOD_8197F) -#define BITS_CPWM2_MOD_8197F (BIT_MASK_CPWM2_MOD_8197F << BIT_SHIFT_CPWM2_MOD_8197F) +#define BIT_CPWM2_MOD_8197F(x) \ + (((x) & BIT_MASK_CPWM2_MOD_8197F) << BIT_SHIFT_CPWM2_MOD_8197F) +#define BITS_CPWM2_MOD_8197F \ + (BIT_MASK_CPWM2_MOD_8197F << BIT_SHIFT_CPWM2_MOD_8197F) #define BIT_CLEAR_CPWM2_MOD_8197F(x) ((x) & (~BITS_CPWM2_MOD_8197F)) -#define BIT_GET_CPWM2_MOD_8197F(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8197F) & BIT_MASK_CPWM2_MOD_8197F) -#define BIT_SET_CPWM2_MOD_8197F(x, v) (BIT_CLEAR_CPWM2_MOD_8197F(x) | BIT_CPWM2_MOD_8197F(v)) - +#define BIT_GET_CPWM2_MOD_8197F(x) \ + (((x) >> BIT_SHIFT_CPWM2_MOD_8197F) & BIT_MASK_CPWM2_MOD_8197F) +#define BIT_SET_CPWM2_MOD_8197F(x, v) \ + (BIT_CLEAR_CPWM2_MOD_8197F(x) | BIT_CPWM2_MOD_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -2691,12 +3285,14 @@ #define BIT_SHIFT_TC0DATA_8197F 0 #define BIT_MASK_TC0DATA_8197F 0xffffff -#define BIT_TC0DATA_8197F(x) (((x) & BIT_MASK_TC0DATA_8197F) << BIT_SHIFT_TC0DATA_8197F) +#define BIT_TC0DATA_8197F(x) \ + (((x) & BIT_MASK_TC0DATA_8197F) << BIT_SHIFT_TC0DATA_8197F) #define BITS_TC0DATA_8197F (BIT_MASK_TC0DATA_8197F << BIT_SHIFT_TC0DATA_8197F) #define BIT_CLEAR_TC0DATA_8197F(x) ((x) & (~BITS_TC0DATA_8197F)) -#define BIT_GET_TC0DATA_8197F(x) (((x) >> BIT_SHIFT_TC0DATA_8197F) & BIT_MASK_TC0DATA_8197F) -#define BIT_SET_TC0DATA_8197F(x, v) (BIT_CLEAR_TC0DATA_8197F(x) | BIT_TC0DATA_8197F(v)) - +#define BIT_GET_TC0DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC0DATA_8197F) & BIT_MASK_TC0DATA_8197F) +#define BIT_SET_TC0DATA_8197F(x, v) \ + (BIT_CLEAR_TC0DATA_8197F(x) | BIT_TC0DATA_8197F(v)) /* 2 REG_TC1_CTRL_8197F */ #define BIT_TC1INT_EN_8197F BIT(26) @@ -2705,12 +3301,14 @@ #define BIT_SHIFT_TC1DATA_8197F 0 #define BIT_MASK_TC1DATA_8197F 0xffffff -#define BIT_TC1DATA_8197F(x) (((x) & BIT_MASK_TC1DATA_8197F) << BIT_SHIFT_TC1DATA_8197F) +#define BIT_TC1DATA_8197F(x) \ + (((x) & BIT_MASK_TC1DATA_8197F) << BIT_SHIFT_TC1DATA_8197F) #define BITS_TC1DATA_8197F (BIT_MASK_TC1DATA_8197F << BIT_SHIFT_TC1DATA_8197F) #define BIT_CLEAR_TC1DATA_8197F(x) ((x) & (~BITS_TC1DATA_8197F)) -#define BIT_GET_TC1DATA_8197F(x) (((x) >> BIT_SHIFT_TC1DATA_8197F) & BIT_MASK_TC1DATA_8197F) -#define BIT_SET_TC1DATA_8197F(x, v) (BIT_CLEAR_TC1DATA_8197F(x) | BIT_TC1DATA_8197F(v)) - +#define BIT_GET_TC1DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC1DATA_8197F) & BIT_MASK_TC1DATA_8197F) +#define BIT_SET_TC1DATA_8197F(x, v) \ + (BIT_CLEAR_TC1DATA_8197F(x) | BIT_TC1DATA_8197F(v)) /* 2 REG_TC2_CTRL_8197F */ #define BIT_TC2INT_EN_8197F BIT(26) @@ -2719,12 +3317,14 @@ #define BIT_SHIFT_TC2DATA_8197F 0 #define BIT_MASK_TC2DATA_8197F 0xffffff -#define BIT_TC2DATA_8197F(x) (((x) & BIT_MASK_TC2DATA_8197F) << BIT_SHIFT_TC2DATA_8197F) +#define BIT_TC2DATA_8197F(x) \ + (((x) & BIT_MASK_TC2DATA_8197F) << BIT_SHIFT_TC2DATA_8197F) #define BITS_TC2DATA_8197F (BIT_MASK_TC2DATA_8197F << BIT_SHIFT_TC2DATA_8197F) #define BIT_CLEAR_TC2DATA_8197F(x) ((x) & (~BITS_TC2DATA_8197F)) -#define BIT_GET_TC2DATA_8197F(x) (((x) >> BIT_SHIFT_TC2DATA_8197F) & BIT_MASK_TC2DATA_8197F) -#define BIT_SET_TC2DATA_8197F(x, v) (BIT_CLEAR_TC2DATA_8197F(x) | BIT_TC2DATA_8197F(v)) - +#define BIT_GET_TC2DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC2DATA_8197F) & BIT_MASK_TC2DATA_8197F) +#define BIT_SET_TC2DATA_8197F(x, v) \ + (BIT_CLEAR_TC2DATA_8197F(x) | BIT_TC2DATA_8197F(v)) /* 2 REG_TC3_CTRL_8197F */ #define BIT_TC3INT_EN_8197F BIT(26) @@ -2733,12 +3333,14 @@ #define BIT_SHIFT_TC3DATA_8197F 0 #define BIT_MASK_TC3DATA_8197F 0xffffff -#define BIT_TC3DATA_8197F(x) (((x) & BIT_MASK_TC3DATA_8197F) << BIT_SHIFT_TC3DATA_8197F) +#define BIT_TC3DATA_8197F(x) \ + (((x) & BIT_MASK_TC3DATA_8197F) << BIT_SHIFT_TC3DATA_8197F) #define BITS_TC3DATA_8197F (BIT_MASK_TC3DATA_8197F << BIT_SHIFT_TC3DATA_8197F) #define BIT_CLEAR_TC3DATA_8197F(x) ((x) & (~BITS_TC3DATA_8197F)) -#define BIT_GET_TC3DATA_8197F(x) (((x) >> BIT_SHIFT_TC3DATA_8197F) & BIT_MASK_TC3DATA_8197F) -#define BIT_SET_TC3DATA_8197F(x, v) (BIT_CLEAR_TC3DATA_8197F(x) | BIT_TC3DATA_8197F(v)) - +#define BIT_GET_TC3DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC3DATA_8197F) & BIT_MASK_TC3DATA_8197F) +#define BIT_SET_TC3DATA_8197F(x, v) \ + (BIT_CLEAR_TC3DATA_8197F(x) | BIT_TC3DATA_8197F(v)) /* 2 REG_TC4_CTRL_8197F */ #define BIT_TC4INT_EN_8197F BIT(26) @@ -2747,23 +3349,28 @@ #define BIT_SHIFT_TC4DATA_8197F 0 #define BIT_MASK_TC4DATA_8197F 0xffffff -#define BIT_TC4DATA_8197F(x) (((x) & BIT_MASK_TC4DATA_8197F) << BIT_SHIFT_TC4DATA_8197F) +#define BIT_TC4DATA_8197F(x) \ + (((x) & BIT_MASK_TC4DATA_8197F) << BIT_SHIFT_TC4DATA_8197F) #define BITS_TC4DATA_8197F (BIT_MASK_TC4DATA_8197F << BIT_SHIFT_TC4DATA_8197F) #define BIT_CLEAR_TC4DATA_8197F(x) ((x) & (~BITS_TC4DATA_8197F)) -#define BIT_GET_TC4DATA_8197F(x) (((x) >> BIT_SHIFT_TC4DATA_8197F) & BIT_MASK_TC4DATA_8197F) -#define BIT_SET_TC4DATA_8197F(x, v) (BIT_CLEAR_TC4DATA_8197F(x) | BIT_TC4DATA_8197F(v)) - +#define BIT_GET_TC4DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC4DATA_8197F) & BIT_MASK_TC4DATA_8197F) +#define BIT_SET_TC4DATA_8197F(x, v) \ + (BIT_CLEAR_TC4DATA_8197F(x) | BIT_TC4DATA_8197F(v)) /* 2 REG_TCUNIT_BASE_8197F */ #define BIT_SHIFT_TCUNIT_BASE_8197F 0 #define BIT_MASK_TCUNIT_BASE_8197F 0x3fff -#define BIT_TCUNIT_BASE_8197F(x) (((x) & BIT_MASK_TCUNIT_BASE_8197F) << BIT_SHIFT_TCUNIT_BASE_8197F) -#define BITS_TCUNIT_BASE_8197F (BIT_MASK_TCUNIT_BASE_8197F << BIT_SHIFT_TCUNIT_BASE_8197F) +#define BIT_TCUNIT_BASE_8197F(x) \ + (((x) & BIT_MASK_TCUNIT_BASE_8197F) << BIT_SHIFT_TCUNIT_BASE_8197F) +#define BITS_TCUNIT_BASE_8197F \ + (BIT_MASK_TCUNIT_BASE_8197F << BIT_SHIFT_TCUNIT_BASE_8197F) #define BIT_CLEAR_TCUNIT_BASE_8197F(x) ((x) & (~BITS_TCUNIT_BASE_8197F)) -#define BIT_GET_TCUNIT_BASE_8197F(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8197F) & BIT_MASK_TCUNIT_BASE_8197F) -#define BIT_SET_TCUNIT_BASE_8197F(x, v) (BIT_CLEAR_TCUNIT_BASE_8197F(x) | BIT_TCUNIT_BASE_8197F(v)) - +#define BIT_GET_TCUNIT_BASE_8197F(x) \ + (((x) >> BIT_SHIFT_TCUNIT_BASE_8197F) & BIT_MASK_TCUNIT_BASE_8197F) +#define BIT_SET_TCUNIT_BASE_8197F(x, v) \ + (BIT_CLEAR_TCUNIT_BASE_8197F(x) | BIT_TCUNIT_BASE_8197F(v)) /* 2 REG_TC5_CTRL_8197F */ #define BIT_TC5INT_EN_8197F BIT(26) @@ -2772,12 +3379,14 @@ #define BIT_SHIFT_TC5DATA_8197F 0 #define BIT_MASK_TC5DATA_8197F 0xffffff -#define BIT_TC5DATA_8197F(x) (((x) & BIT_MASK_TC5DATA_8197F) << BIT_SHIFT_TC5DATA_8197F) +#define BIT_TC5DATA_8197F(x) \ + (((x) & BIT_MASK_TC5DATA_8197F) << BIT_SHIFT_TC5DATA_8197F) #define BITS_TC5DATA_8197F (BIT_MASK_TC5DATA_8197F << BIT_SHIFT_TC5DATA_8197F) #define BIT_CLEAR_TC5DATA_8197F(x) ((x) & (~BITS_TC5DATA_8197F)) -#define BIT_GET_TC5DATA_8197F(x) (((x) >> BIT_SHIFT_TC5DATA_8197F) & BIT_MASK_TC5DATA_8197F) -#define BIT_SET_TC5DATA_8197F(x, v) (BIT_CLEAR_TC5DATA_8197F(x) | BIT_TC5DATA_8197F(v)) - +#define BIT_GET_TC5DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC5DATA_8197F) & BIT_MASK_TC5DATA_8197F) +#define BIT_SET_TC5DATA_8197F(x, v) \ + (BIT_CLEAR_TC5DATA_8197F(x) | BIT_TC5DATA_8197F(v)) /* 2 REG_TC6_CTRL_8197F */ #define BIT_TC6INT_EN_8197F BIT(26) @@ -2786,159 +3395,251 @@ #define BIT_SHIFT_TC6DATA_8197F 0 #define BIT_MASK_TC6DATA_8197F 0xffffff -#define BIT_TC6DATA_8197F(x) (((x) & BIT_MASK_TC6DATA_8197F) << BIT_SHIFT_TC6DATA_8197F) +#define BIT_TC6DATA_8197F(x) \ + (((x) & BIT_MASK_TC6DATA_8197F) << BIT_SHIFT_TC6DATA_8197F) #define BITS_TC6DATA_8197F (BIT_MASK_TC6DATA_8197F << BIT_SHIFT_TC6DATA_8197F) #define BIT_CLEAR_TC6DATA_8197F(x) ((x) & (~BITS_TC6DATA_8197F)) -#define BIT_GET_TC6DATA_8197F(x) (((x) >> BIT_SHIFT_TC6DATA_8197F) & BIT_MASK_TC6DATA_8197F) -#define BIT_SET_TC6DATA_8197F(x, v) (BIT_CLEAR_TC6DATA_8197F(x) | BIT_TC6DATA_8197F(v)) - +#define BIT_GET_TC6DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC6DATA_8197F) & BIT_MASK_TC6DATA_8197F) +#define BIT_SET_TC6DATA_8197F(x, v) \ + (BIT_CLEAR_TC6DATA_8197F(x) | BIT_TC6DATA_8197F(v)) /* 2 REG_MBIST_FAIL_8197F */ #define BIT_SHIFT_8051_MBIST_FAIL_8197F 26 #define BIT_MASK_8051_MBIST_FAIL_8197F 0x7 -#define BIT_8051_MBIST_FAIL_8197F(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8197F) << BIT_SHIFT_8051_MBIST_FAIL_8197F) -#define BITS_8051_MBIST_FAIL_8197F (BIT_MASK_8051_MBIST_FAIL_8197F << BIT_SHIFT_8051_MBIST_FAIL_8197F) +#define BIT_8051_MBIST_FAIL_8197F(x) \ + (((x) & BIT_MASK_8051_MBIST_FAIL_8197F) \ + << BIT_SHIFT_8051_MBIST_FAIL_8197F) +#define BITS_8051_MBIST_FAIL_8197F \ + (BIT_MASK_8051_MBIST_FAIL_8197F << BIT_SHIFT_8051_MBIST_FAIL_8197F) #define BIT_CLEAR_8051_MBIST_FAIL_8197F(x) ((x) & (~BITS_8051_MBIST_FAIL_8197F)) -#define BIT_GET_8051_MBIST_FAIL_8197F(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8197F) & BIT_MASK_8051_MBIST_FAIL_8197F) -#define BIT_SET_8051_MBIST_FAIL_8197F(x, v) (BIT_CLEAR_8051_MBIST_FAIL_8197F(x) | BIT_8051_MBIST_FAIL_8197F(v)) - +#define BIT_GET_8051_MBIST_FAIL_8197F(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8197F) & \ + BIT_MASK_8051_MBIST_FAIL_8197F) +#define BIT_SET_8051_MBIST_FAIL_8197F(x, v) \ + (BIT_CLEAR_8051_MBIST_FAIL_8197F(x) | BIT_8051_MBIST_FAIL_8197F(v)) #define BIT_SHIFT_USB_MBIST_FAIL_8197F 24 #define BIT_MASK_USB_MBIST_FAIL_8197F 0x3 -#define BIT_USB_MBIST_FAIL_8197F(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8197F) << BIT_SHIFT_USB_MBIST_FAIL_8197F) -#define BITS_USB_MBIST_FAIL_8197F (BIT_MASK_USB_MBIST_FAIL_8197F << BIT_SHIFT_USB_MBIST_FAIL_8197F) +#define BIT_USB_MBIST_FAIL_8197F(x) \ + (((x) & BIT_MASK_USB_MBIST_FAIL_8197F) \ + << BIT_SHIFT_USB_MBIST_FAIL_8197F) +#define BITS_USB_MBIST_FAIL_8197F \ + (BIT_MASK_USB_MBIST_FAIL_8197F << BIT_SHIFT_USB_MBIST_FAIL_8197F) #define BIT_CLEAR_USB_MBIST_FAIL_8197F(x) ((x) & (~BITS_USB_MBIST_FAIL_8197F)) -#define BIT_GET_USB_MBIST_FAIL_8197F(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8197F) & BIT_MASK_USB_MBIST_FAIL_8197F) -#define BIT_SET_USB_MBIST_FAIL_8197F(x, v) (BIT_CLEAR_USB_MBIST_FAIL_8197F(x) | BIT_USB_MBIST_FAIL_8197F(v)) - +#define BIT_GET_USB_MBIST_FAIL_8197F(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8197F) & \ + BIT_MASK_USB_MBIST_FAIL_8197F) +#define BIT_SET_USB_MBIST_FAIL_8197F(x, v) \ + (BIT_CLEAR_USB_MBIST_FAIL_8197F(x) | BIT_USB_MBIST_FAIL_8197F(v)) #define BIT_SHIFT_PCIE_MBIST_FAIL_8197F 16 #define BIT_MASK_PCIE_MBIST_FAIL_8197F 0x3f -#define BIT_PCIE_MBIST_FAIL_8197F(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8197F) << BIT_SHIFT_PCIE_MBIST_FAIL_8197F) -#define BITS_PCIE_MBIST_FAIL_8197F (BIT_MASK_PCIE_MBIST_FAIL_8197F << BIT_SHIFT_PCIE_MBIST_FAIL_8197F) +#define BIT_PCIE_MBIST_FAIL_8197F(x) \ + (((x) & BIT_MASK_PCIE_MBIST_FAIL_8197F) \ + << BIT_SHIFT_PCIE_MBIST_FAIL_8197F) +#define BITS_PCIE_MBIST_FAIL_8197F \ + (BIT_MASK_PCIE_MBIST_FAIL_8197F << BIT_SHIFT_PCIE_MBIST_FAIL_8197F) #define BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) ((x) & (~BITS_PCIE_MBIST_FAIL_8197F)) -#define BIT_GET_PCIE_MBIST_FAIL_8197F(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8197F) & BIT_MASK_PCIE_MBIST_FAIL_8197F) -#define BIT_SET_PCIE_MBIST_FAIL_8197F(x, v) (BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) | BIT_PCIE_MBIST_FAIL_8197F(v)) - +#define BIT_GET_PCIE_MBIST_FAIL_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8197F) & \ + BIT_MASK_PCIE_MBIST_FAIL_8197F) +#define BIT_SET_PCIE_MBIST_FAIL_8197F(x, v) \ + (BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) | BIT_PCIE_MBIST_FAIL_8197F(v)) #define BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F 0 #define BIT_MASK_MAC_MBIST_FAIL_DRF_8197F 0x3ffff -#define BIT_MAC_MBIST_FAIL_DRF_8197F(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF_8197F) << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) -#define BITS_MAC_MBIST_FAIL_DRF_8197F (BIT_MASK_MAC_MBIST_FAIL_DRF_8197F << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) -#define BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) ((x) & (~BITS_MAC_MBIST_FAIL_DRF_8197F)) -#define BIT_GET_MAC_MBIST_FAIL_DRF_8197F(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) & BIT_MASK_MAC_MBIST_FAIL_DRF_8197F) -#define BIT_SET_MAC_MBIST_FAIL_DRF_8197F(x, v) (BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) | BIT_MAC_MBIST_FAIL_DRF_8197F(v)) - +#define BIT_MAC_MBIST_FAIL_DRF_8197F(x) \ + (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF_8197F) \ + << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) +#define BITS_MAC_MBIST_FAIL_DRF_8197F \ + (BIT_MASK_MAC_MBIST_FAIL_DRF_8197F \ + << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) +#define BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) \ + ((x) & (~BITS_MAC_MBIST_FAIL_DRF_8197F)) +#define BIT_GET_MAC_MBIST_FAIL_DRF_8197F(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) & \ + BIT_MASK_MAC_MBIST_FAIL_DRF_8197F) +#define BIT_SET_MAC_MBIST_FAIL_DRF_8197F(x, v) \ + (BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) | \ + BIT_MAC_MBIST_FAIL_DRF_8197F(v)) /* 2 REG_MBIST_START_PAUSE_8197F */ #define BIT_SHIFT_8051_MBIST_START_PAUSE_8197F 26 #define BIT_MASK_8051_MBIST_START_PAUSE_8197F 0x7 -#define BIT_8051_MBIST_START_PAUSE_8197F(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8197F) << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) -#define BITS_8051_MBIST_START_PAUSE_8197F (BIT_MASK_8051_MBIST_START_PAUSE_8197F << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) -#define BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) ((x) & (~BITS_8051_MBIST_START_PAUSE_8197F)) -#define BIT_GET_8051_MBIST_START_PAUSE_8197F(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) & BIT_MASK_8051_MBIST_START_PAUSE_8197F) -#define BIT_SET_8051_MBIST_START_PAUSE_8197F(x, v) (BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) | BIT_8051_MBIST_START_PAUSE_8197F(v)) - +#define BIT_8051_MBIST_START_PAUSE_8197F(x) \ + (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8197F) \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) +#define BITS_8051_MBIST_START_PAUSE_8197F \ + (BIT_MASK_8051_MBIST_START_PAUSE_8197F \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) +#define BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) \ + ((x) & (~BITS_8051_MBIST_START_PAUSE_8197F)) +#define BIT_GET_8051_MBIST_START_PAUSE_8197F(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) & \ + BIT_MASK_8051_MBIST_START_PAUSE_8197F) +#define BIT_SET_8051_MBIST_START_PAUSE_8197F(x, v) \ + (BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) | \ + BIT_8051_MBIST_START_PAUSE_8197F(v)) #define BIT_SHIFT_USB_MBIST_START_PAUSE_8197F 24 #define BIT_MASK_USB_MBIST_START_PAUSE_8197F 0x3 -#define BIT_USB_MBIST_START_PAUSE_8197F(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8197F) << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) -#define BITS_USB_MBIST_START_PAUSE_8197F (BIT_MASK_USB_MBIST_START_PAUSE_8197F << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) -#define BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) ((x) & (~BITS_USB_MBIST_START_PAUSE_8197F)) -#define BIT_GET_USB_MBIST_START_PAUSE_8197F(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) & BIT_MASK_USB_MBIST_START_PAUSE_8197F) -#define BIT_SET_USB_MBIST_START_PAUSE_8197F(x, v) (BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) | BIT_USB_MBIST_START_PAUSE_8197F(v)) - +#define BIT_USB_MBIST_START_PAUSE_8197F(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8197F) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) +#define BITS_USB_MBIST_START_PAUSE_8197F \ + (BIT_MASK_USB_MBIST_START_PAUSE_8197F \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) +#define BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) \ + ((x) & (~BITS_USB_MBIST_START_PAUSE_8197F)) +#define BIT_GET_USB_MBIST_START_PAUSE_8197F(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) & \ + BIT_MASK_USB_MBIST_START_PAUSE_8197F) +#define BIT_SET_USB_MBIST_START_PAUSE_8197F(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) | \ + BIT_USB_MBIST_START_PAUSE_8197F(v)) #define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F 16 #define BIT_MASK_PCIE_MBIST_START_PAUSE_8197F 0x3f -#define BIT_PCIE_MBIST_START_PAUSE_8197F(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8197F) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) -#define BITS_PCIE_MBIST_START_PAUSE_8197F (BIT_MASK_PCIE_MBIST_START_PAUSE_8197F << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) -#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) ((x) & (~BITS_PCIE_MBIST_START_PAUSE_8197F)) -#define BIT_GET_PCIE_MBIST_START_PAUSE_8197F(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) & BIT_MASK_PCIE_MBIST_START_PAUSE_8197F) -#define BIT_SET_PCIE_MBIST_START_PAUSE_8197F(x, v) (BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) | BIT_PCIE_MBIST_START_PAUSE_8197F(v)) - +#define BIT_PCIE_MBIST_START_PAUSE_8197F(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8197F) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) +#define BITS_PCIE_MBIST_START_PAUSE_8197F \ + (BIT_MASK_PCIE_MBIST_START_PAUSE_8197F \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE_8197F)) +#define BIT_GET_PCIE_MBIST_START_PAUSE_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE_8197F) +#define BIT_SET_PCIE_MBIST_START_PAUSE_8197F(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) | \ + BIT_PCIE_MBIST_START_PAUSE_8197F(v)) #define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F 0 #define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F 0x3ffff -#define BIT_MAC_MBIST_START_PAUSE_V1_8197F(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F) << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) -#define BITS_MAC_MBIST_START_PAUSE_V1_8197F (BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) -#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8197F)) -#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8197F(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F) -#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8197F(x, v) (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) | BIT_MAC_MBIST_START_PAUSE_V1_8197F(v)) - +#define BIT_MAC_MBIST_START_PAUSE_V1_8197F(x) \ + (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F) \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) +#define BITS_MAC_MBIST_START_PAUSE_V1_8197F \ + (BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) \ + ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8197F)) +#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) & \ + BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F) +#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8197F(x, v) \ + (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) | \ + BIT_MAC_MBIST_START_PAUSE_V1_8197F(v)) /* 2 REG_MBIST_DONE_8197F */ #define BIT_SHIFT_8051_MBIST_DONE_8197F 26 #define BIT_MASK_8051_MBIST_DONE_8197F 0x7 -#define BIT_8051_MBIST_DONE_8197F(x) (((x) & BIT_MASK_8051_MBIST_DONE_8197F) << BIT_SHIFT_8051_MBIST_DONE_8197F) -#define BITS_8051_MBIST_DONE_8197F (BIT_MASK_8051_MBIST_DONE_8197F << BIT_SHIFT_8051_MBIST_DONE_8197F) +#define BIT_8051_MBIST_DONE_8197F(x) \ + (((x) & BIT_MASK_8051_MBIST_DONE_8197F) \ + << BIT_SHIFT_8051_MBIST_DONE_8197F) +#define BITS_8051_MBIST_DONE_8197F \ + (BIT_MASK_8051_MBIST_DONE_8197F << BIT_SHIFT_8051_MBIST_DONE_8197F) #define BIT_CLEAR_8051_MBIST_DONE_8197F(x) ((x) & (~BITS_8051_MBIST_DONE_8197F)) -#define BIT_GET_8051_MBIST_DONE_8197F(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8197F) & BIT_MASK_8051_MBIST_DONE_8197F) -#define BIT_SET_8051_MBIST_DONE_8197F(x, v) (BIT_CLEAR_8051_MBIST_DONE_8197F(x) | BIT_8051_MBIST_DONE_8197F(v)) - +#define BIT_GET_8051_MBIST_DONE_8197F(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DONE_8197F) & \ + BIT_MASK_8051_MBIST_DONE_8197F) +#define BIT_SET_8051_MBIST_DONE_8197F(x, v) \ + (BIT_CLEAR_8051_MBIST_DONE_8197F(x) | BIT_8051_MBIST_DONE_8197F(v)) #define BIT_SHIFT_USB_MBIST_DONE_8197F 24 #define BIT_MASK_USB_MBIST_DONE_8197F 0x3 -#define BIT_USB_MBIST_DONE_8197F(x) (((x) & BIT_MASK_USB_MBIST_DONE_8197F) << BIT_SHIFT_USB_MBIST_DONE_8197F) -#define BITS_USB_MBIST_DONE_8197F (BIT_MASK_USB_MBIST_DONE_8197F << BIT_SHIFT_USB_MBIST_DONE_8197F) +#define BIT_USB_MBIST_DONE_8197F(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE_8197F) \ + << BIT_SHIFT_USB_MBIST_DONE_8197F) +#define BITS_USB_MBIST_DONE_8197F \ + (BIT_MASK_USB_MBIST_DONE_8197F << BIT_SHIFT_USB_MBIST_DONE_8197F) #define BIT_CLEAR_USB_MBIST_DONE_8197F(x) ((x) & (~BITS_USB_MBIST_DONE_8197F)) -#define BIT_GET_USB_MBIST_DONE_8197F(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8197F) & BIT_MASK_USB_MBIST_DONE_8197F) -#define BIT_SET_USB_MBIST_DONE_8197F(x, v) (BIT_CLEAR_USB_MBIST_DONE_8197F(x) | BIT_USB_MBIST_DONE_8197F(v)) - +#define BIT_GET_USB_MBIST_DONE_8197F(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE_8197F) & \ + BIT_MASK_USB_MBIST_DONE_8197F) +#define BIT_SET_USB_MBIST_DONE_8197F(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE_8197F(x) | BIT_USB_MBIST_DONE_8197F(v)) #define BIT_SHIFT_PCIE_MBIST_DONE_8197F 16 #define BIT_MASK_PCIE_MBIST_DONE_8197F 0x3f -#define BIT_PCIE_MBIST_DONE_8197F(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8197F) << BIT_SHIFT_PCIE_MBIST_DONE_8197F) -#define BITS_PCIE_MBIST_DONE_8197F (BIT_MASK_PCIE_MBIST_DONE_8197F << BIT_SHIFT_PCIE_MBIST_DONE_8197F) +#define BIT_PCIE_MBIST_DONE_8197F(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE_8197F) \ + << BIT_SHIFT_PCIE_MBIST_DONE_8197F) +#define BITS_PCIE_MBIST_DONE_8197F \ + (BIT_MASK_PCIE_MBIST_DONE_8197F << BIT_SHIFT_PCIE_MBIST_DONE_8197F) #define BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) ((x) & (~BITS_PCIE_MBIST_DONE_8197F)) -#define BIT_GET_PCIE_MBIST_DONE_8197F(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8197F) & BIT_MASK_PCIE_MBIST_DONE_8197F) -#define BIT_SET_PCIE_MBIST_DONE_8197F(x, v) (BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) | BIT_PCIE_MBIST_DONE_8197F(v)) - +#define BIT_GET_PCIE_MBIST_DONE_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8197F) & \ + BIT_MASK_PCIE_MBIST_DONE_8197F) +#define BIT_SET_PCIE_MBIST_DONE_8197F(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) | BIT_PCIE_MBIST_DONE_8197F(v)) #define BIT_SHIFT_MAC_MBIST_DONE_V1_8197F 0 #define BIT_MASK_MAC_MBIST_DONE_V1_8197F 0x3ffff -#define BIT_MAC_MBIST_DONE_V1_8197F(x) (((x) & BIT_MASK_MAC_MBIST_DONE_V1_8197F) << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) -#define BITS_MAC_MBIST_DONE_V1_8197F (BIT_MASK_MAC_MBIST_DONE_V1_8197F << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) -#define BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) ((x) & (~BITS_MAC_MBIST_DONE_V1_8197F)) -#define BIT_GET_MAC_MBIST_DONE_V1_8197F(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) & BIT_MASK_MAC_MBIST_DONE_V1_8197F) -#define BIT_SET_MAC_MBIST_DONE_V1_8197F(x, v) (BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) | BIT_MAC_MBIST_DONE_V1_8197F(v)) - +#define BIT_MAC_MBIST_DONE_V1_8197F(x) \ + (((x) & BIT_MASK_MAC_MBIST_DONE_V1_8197F) \ + << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) +#define BITS_MAC_MBIST_DONE_V1_8197F \ + (BIT_MASK_MAC_MBIST_DONE_V1_8197F << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) +#define BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) \ + ((x) & (~BITS_MAC_MBIST_DONE_V1_8197F)) +#define BIT_GET_MAC_MBIST_DONE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) & \ + BIT_MASK_MAC_MBIST_DONE_V1_8197F) +#define BIT_SET_MAC_MBIST_DONE_V1_8197F(x, v) \ + (BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) | BIT_MAC_MBIST_DONE_V1_8197F(v)) /* 2 REG_MBIST_FAIL_NRML_8197F */ #define BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F 0 #define BIT_MASK_MBIST_FAIL_NRML_V1_8197F 0x3ffff -#define BIT_MBIST_FAIL_NRML_V1_8197F(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_V1_8197F) << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) -#define BITS_MBIST_FAIL_NRML_V1_8197F (BIT_MASK_MBIST_FAIL_NRML_V1_8197F << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) -#define BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) ((x) & (~BITS_MBIST_FAIL_NRML_V1_8197F)) -#define BIT_GET_MBIST_FAIL_NRML_V1_8197F(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) & BIT_MASK_MBIST_FAIL_NRML_V1_8197F) -#define BIT_SET_MBIST_FAIL_NRML_V1_8197F(x, v) (BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) | BIT_MBIST_FAIL_NRML_V1_8197F(v)) - +#define BIT_MBIST_FAIL_NRML_V1_8197F(x) \ + (((x) & BIT_MASK_MBIST_FAIL_NRML_V1_8197F) \ + << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) +#define BITS_MBIST_FAIL_NRML_V1_8197F \ + (BIT_MASK_MBIST_FAIL_NRML_V1_8197F \ + << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) +#define BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) \ + ((x) & (~BITS_MBIST_FAIL_NRML_V1_8197F)) +#define BIT_GET_MBIST_FAIL_NRML_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) & \ + BIT_MASK_MBIST_FAIL_NRML_V1_8197F) +#define BIT_SET_MBIST_FAIL_NRML_V1_8197F(x, v) \ + (BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) | \ + BIT_MBIST_FAIL_NRML_V1_8197F(v)) /* 2 REG_AES_DECRPT_DATA_8197F */ #define BIT_SHIFT_IPS_CFG_ADDR_8197F 0 #define BIT_MASK_IPS_CFG_ADDR_8197F 0xff -#define BIT_IPS_CFG_ADDR_8197F(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8197F) << BIT_SHIFT_IPS_CFG_ADDR_8197F) -#define BITS_IPS_CFG_ADDR_8197F (BIT_MASK_IPS_CFG_ADDR_8197F << BIT_SHIFT_IPS_CFG_ADDR_8197F) +#define BIT_IPS_CFG_ADDR_8197F(x) \ + (((x) & BIT_MASK_IPS_CFG_ADDR_8197F) << BIT_SHIFT_IPS_CFG_ADDR_8197F) +#define BITS_IPS_CFG_ADDR_8197F \ + (BIT_MASK_IPS_CFG_ADDR_8197F << BIT_SHIFT_IPS_CFG_ADDR_8197F) #define BIT_CLEAR_IPS_CFG_ADDR_8197F(x) ((x) & (~BITS_IPS_CFG_ADDR_8197F)) -#define BIT_GET_IPS_CFG_ADDR_8197F(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8197F) & BIT_MASK_IPS_CFG_ADDR_8197F) -#define BIT_SET_IPS_CFG_ADDR_8197F(x, v) (BIT_CLEAR_IPS_CFG_ADDR_8197F(x) | BIT_IPS_CFG_ADDR_8197F(v)) - +#define BIT_GET_IPS_CFG_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8197F) & BIT_MASK_IPS_CFG_ADDR_8197F) +#define BIT_SET_IPS_CFG_ADDR_8197F(x, v) \ + (BIT_CLEAR_IPS_CFG_ADDR_8197F(x) | BIT_IPS_CFG_ADDR_8197F(v)) /* 2 REG_AES_DECRPT_CFG_8197F */ #define BIT_SHIFT_IPS_CFG_DATA_8197F 0 #define BIT_MASK_IPS_CFG_DATA_8197F 0xffffffffL -#define BIT_IPS_CFG_DATA_8197F(x) (((x) & BIT_MASK_IPS_CFG_DATA_8197F) << BIT_SHIFT_IPS_CFG_DATA_8197F) -#define BITS_IPS_CFG_DATA_8197F (BIT_MASK_IPS_CFG_DATA_8197F << BIT_SHIFT_IPS_CFG_DATA_8197F) +#define BIT_IPS_CFG_DATA_8197F(x) \ + (((x) & BIT_MASK_IPS_CFG_DATA_8197F) << BIT_SHIFT_IPS_CFG_DATA_8197F) +#define BITS_IPS_CFG_DATA_8197F \ + (BIT_MASK_IPS_CFG_DATA_8197F << BIT_SHIFT_IPS_CFG_DATA_8197F) #define BIT_CLEAR_IPS_CFG_DATA_8197F(x) ((x) & (~BITS_IPS_CFG_DATA_8197F)) -#define BIT_GET_IPS_CFG_DATA_8197F(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8197F) & BIT_MASK_IPS_CFG_DATA_8197F) -#define BIT_SET_IPS_CFG_DATA_8197F(x, v) (BIT_CLEAR_IPS_CFG_DATA_8197F(x) | BIT_IPS_CFG_DATA_8197F(v)) - +#define BIT_GET_IPS_CFG_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_DATA_8197F) & BIT_MASK_IPS_CFG_DATA_8197F) +#define BIT_SET_IPS_CFG_DATA_8197F(x, v) \ + (BIT_CLEAR_IPS_CFG_DATA_8197F(x) | BIT_IPS_CFG_DATA_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -2946,56 +3647,90 @@ #define BIT_SHIFT_MACCLK_FREQ_LOW32_8197F 0 #define BIT_MASK_MACCLK_FREQ_LOW32_8197F 0xffffffffL -#define BIT_MACCLK_FREQ_LOW32_8197F(x) (((x) & BIT_MASK_MACCLK_FREQ_LOW32_8197F) << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) -#define BITS_MACCLK_FREQ_LOW32_8197F (BIT_MASK_MACCLK_FREQ_LOW32_8197F << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) -#define BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) ((x) & (~BITS_MACCLK_FREQ_LOW32_8197F)) -#define BIT_GET_MACCLK_FREQ_LOW32_8197F(x) (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) & BIT_MASK_MACCLK_FREQ_LOW32_8197F) -#define BIT_SET_MACCLK_FREQ_LOW32_8197F(x, v) (BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) | BIT_MACCLK_FREQ_LOW32_8197F(v)) - +#define BIT_MACCLK_FREQ_LOW32_8197F(x) \ + (((x) & BIT_MASK_MACCLK_FREQ_LOW32_8197F) \ + << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) +#define BITS_MACCLK_FREQ_LOW32_8197F \ + (BIT_MASK_MACCLK_FREQ_LOW32_8197F << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) +#define BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) \ + ((x) & (~BITS_MACCLK_FREQ_LOW32_8197F)) +#define BIT_GET_MACCLK_FREQ_LOW32_8197F(x) \ + (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) & \ + BIT_MASK_MACCLK_FREQ_LOW32_8197F) +#define BIT_SET_MACCLK_FREQ_LOW32_8197F(x, v) \ + (BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) | BIT_MACCLK_FREQ_LOW32_8197F(v)) /* 2 REG_TMETER_8197F */ #define BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F 0 #define BIT_MASK_MACCLK_FREQ_HIGH10_8197F 0x3ff -#define BIT_MACCLK_FREQ_HIGH10_8197F(x) (((x) & BIT_MASK_MACCLK_FREQ_HIGH10_8197F) << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) -#define BITS_MACCLK_FREQ_HIGH10_8197F (BIT_MASK_MACCLK_FREQ_HIGH10_8197F << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) -#define BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) ((x) & (~BITS_MACCLK_FREQ_HIGH10_8197F)) -#define BIT_GET_MACCLK_FREQ_HIGH10_8197F(x) (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) & BIT_MASK_MACCLK_FREQ_HIGH10_8197F) -#define BIT_SET_MACCLK_FREQ_HIGH10_8197F(x, v) (BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) | BIT_MACCLK_FREQ_HIGH10_8197F(v)) - +#define BIT_MACCLK_FREQ_HIGH10_8197F(x) \ + (((x) & BIT_MASK_MACCLK_FREQ_HIGH10_8197F) \ + << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) +#define BITS_MACCLK_FREQ_HIGH10_8197F \ + (BIT_MASK_MACCLK_FREQ_HIGH10_8197F \ + << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) +#define BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) \ + ((x) & (~BITS_MACCLK_FREQ_HIGH10_8197F)) +#define BIT_GET_MACCLK_FREQ_HIGH10_8197F(x) \ + (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) & \ + BIT_MASK_MACCLK_FREQ_HIGH10_8197F) +#define BIT_SET_MACCLK_FREQ_HIGH10_8197F(x, v) \ + (BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) | \ + BIT_MACCLK_FREQ_HIGH10_8197F(v)) /* 2 REG_OSC_32K_CTRL_8197F */ #define BIT_32K_CLK_OUT_RDY_8197F BIT(12) #define BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F 8 #define BIT_MASK_MONITOR_CYCLE_LOG2_8197F 0xf -#define BIT_MONITOR_CYCLE_LOG2_8197F(x) (((x) & BIT_MASK_MONITOR_CYCLE_LOG2_8197F) << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) -#define BITS_MONITOR_CYCLE_LOG2_8197F (BIT_MASK_MONITOR_CYCLE_LOG2_8197F << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) -#define BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) ((x) & (~BITS_MONITOR_CYCLE_LOG2_8197F)) -#define BIT_GET_MONITOR_CYCLE_LOG2_8197F(x) (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) & BIT_MASK_MONITOR_CYCLE_LOG2_8197F) -#define BIT_SET_MONITOR_CYCLE_LOG2_8197F(x, v) (BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) | BIT_MONITOR_CYCLE_LOG2_8197F(v)) - +#define BIT_MONITOR_CYCLE_LOG2_8197F(x) \ + (((x) & BIT_MASK_MONITOR_CYCLE_LOG2_8197F) \ + << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) +#define BITS_MONITOR_CYCLE_LOG2_8197F \ + (BIT_MASK_MONITOR_CYCLE_LOG2_8197F \ + << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) +#define BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) \ + ((x) & (~BITS_MONITOR_CYCLE_LOG2_8197F)) +#define BIT_GET_MONITOR_CYCLE_LOG2_8197F(x) \ + (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) & \ + BIT_MASK_MONITOR_CYCLE_LOG2_8197F) +#define BIT_SET_MONITOR_CYCLE_LOG2_8197F(x, v) \ + (BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) | \ + BIT_MONITOR_CYCLE_LOG2_8197F(v)) /* 2 REG_32K_CAL_REG1_8197F */ #define BIT_SHIFT_FREQVALUE_UNREGCLK_8197F 8 #define BIT_MASK_FREQVALUE_UNREGCLK_8197F 0xffffff -#define BIT_FREQVALUE_UNREGCLK_8197F(x) (((x) & BIT_MASK_FREQVALUE_UNREGCLK_8197F) << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) -#define BITS_FREQVALUE_UNREGCLK_8197F (BIT_MASK_FREQVALUE_UNREGCLK_8197F << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) -#define BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) ((x) & (~BITS_FREQVALUE_UNREGCLK_8197F)) -#define BIT_GET_FREQVALUE_UNREGCLK_8197F(x) (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) & BIT_MASK_FREQVALUE_UNREGCLK_8197F) -#define BIT_SET_FREQVALUE_UNREGCLK_8197F(x, v) (BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) | BIT_FREQVALUE_UNREGCLK_8197F(v)) +#define BIT_FREQVALUE_UNREGCLK_8197F(x) \ + (((x) & BIT_MASK_FREQVALUE_UNREGCLK_8197F) \ + << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) +#define BITS_FREQVALUE_UNREGCLK_8197F \ + (BIT_MASK_FREQVALUE_UNREGCLK_8197F \ + << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) +#define BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) \ + ((x) & (~BITS_FREQVALUE_UNREGCLK_8197F)) +#define BIT_GET_FREQVALUE_UNREGCLK_8197F(x) \ + (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) & \ + BIT_MASK_FREQVALUE_UNREGCLK_8197F) +#define BIT_SET_FREQVALUE_UNREGCLK_8197F(x, v) \ + (BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) | \ + BIT_FREQVALUE_UNREGCLK_8197F(v)) #define BIT_CAL32K_DBGMOD_8197F BIT(7) #define BIT_SHIFT_NCO_THRS_8197F 0 #define BIT_MASK_NCO_THRS_8197F 0x7f -#define BIT_NCO_THRS_8197F(x) (((x) & BIT_MASK_NCO_THRS_8197F) << BIT_SHIFT_NCO_THRS_8197F) -#define BITS_NCO_THRS_8197F (BIT_MASK_NCO_THRS_8197F << BIT_SHIFT_NCO_THRS_8197F) +#define BIT_NCO_THRS_8197F(x) \ + (((x) & BIT_MASK_NCO_THRS_8197F) << BIT_SHIFT_NCO_THRS_8197F) +#define BITS_NCO_THRS_8197F \ + (BIT_MASK_NCO_THRS_8197F << BIT_SHIFT_NCO_THRS_8197F) #define BIT_CLEAR_NCO_THRS_8197F(x) ((x) & (~BITS_NCO_THRS_8197F)) -#define BIT_GET_NCO_THRS_8197F(x) (((x) >> BIT_SHIFT_NCO_THRS_8197F) & BIT_MASK_NCO_THRS_8197F) -#define BIT_SET_NCO_THRS_8197F(x, v) (BIT_CLEAR_NCO_THRS_8197F(x) | BIT_NCO_THRS_8197F(v)) - +#define BIT_GET_NCO_THRS_8197F(x) \ + (((x) >> BIT_SHIFT_NCO_THRS_8197F) & BIT_MASK_NCO_THRS_8197F) +#define BIT_SET_NCO_THRS_8197F(x, v) \ + (BIT_CLEAR_NCO_THRS_8197F(x) | BIT_NCO_THRS_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -3003,67 +3738,88 @@ #define BIT_SHIFT_C2HEVT_MSG_8197F 0 #define BIT_MASK_C2HEVT_MSG_8197F 0xffffffffffffffffffffffffffffffffL -#define BIT_C2HEVT_MSG_8197F(x) (((x) & BIT_MASK_C2HEVT_MSG_8197F) << BIT_SHIFT_C2HEVT_MSG_8197F) -#define BITS_C2HEVT_MSG_8197F (BIT_MASK_C2HEVT_MSG_8197F << BIT_SHIFT_C2HEVT_MSG_8197F) +#define BIT_C2HEVT_MSG_8197F(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_8197F) << BIT_SHIFT_C2HEVT_MSG_8197F) +#define BITS_C2HEVT_MSG_8197F \ + (BIT_MASK_C2HEVT_MSG_8197F << BIT_SHIFT_C2HEVT_MSG_8197F) #define BIT_CLEAR_C2HEVT_MSG_8197F(x) ((x) & (~BITS_C2HEVT_MSG_8197F)) -#define BIT_GET_C2HEVT_MSG_8197F(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_8197F) & BIT_MASK_C2HEVT_MSG_8197F) -#define BIT_SET_C2HEVT_MSG_8197F(x, v) (BIT_CLEAR_C2HEVT_MSG_8197F(x) | BIT_C2HEVT_MSG_8197F(v)) - +#define BIT_GET_C2HEVT_MSG_8197F(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_8197F) & BIT_MASK_C2HEVT_MSG_8197F) +#define BIT_SET_C2HEVT_MSG_8197F(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_8197F(x) | BIT_C2HEVT_MSG_8197F(v)) /* 2 REG_SW_DEFINED_PAGE1_8197F */ #define BIT_SHIFT_SW_DEFINED_PAGE1_8197F 0 #define BIT_MASK_SW_DEFINED_PAGE1_8197F 0xffffffffffffffffL -#define BIT_SW_DEFINED_PAGE1_8197F(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_8197F) << BIT_SHIFT_SW_DEFINED_PAGE1_8197F) -#define BITS_SW_DEFINED_PAGE1_8197F (BIT_MASK_SW_DEFINED_PAGE1_8197F << BIT_SHIFT_SW_DEFINED_PAGE1_8197F) -#define BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) ((x) & (~BITS_SW_DEFINED_PAGE1_8197F)) -#define BIT_GET_SW_DEFINED_PAGE1_8197F(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8197F) & BIT_MASK_SW_DEFINED_PAGE1_8197F) -#define BIT_SET_SW_DEFINED_PAGE1_8197F(x, v) (BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) | BIT_SW_DEFINED_PAGE1_8197F(v)) - +#define BIT_SW_DEFINED_PAGE1_8197F(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1_8197F) \ + << BIT_SHIFT_SW_DEFINED_PAGE1_8197F) +#define BITS_SW_DEFINED_PAGE1_8197F \ + (BIT_MASK_SW_DEFINED_PAGE1_8197F << BIT_SHIFT_SW_DEFINED_PAGE1_8197F) +#define BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE1_8197F)) +#define BIT_GET_SW_DEFINED_PAGE1_8197F(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8197F) & \ + BIT_MASK_SW_DEFINED_PAGE1_8197F) +#define BIT_SET_SW_DEFINED_PAGE1_8197F(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) | BIT_SW_DEFINED_PAGE1_8197F(v)) /* 2 REG_MCUTST_I_8197F */ #define BIT_SHIFT_MCUDMSG_I_8197F 0 #define BIT_MASK_MCUDMSG_I_8197F 0xffffffffL -#define BIT_MCUDMSG_I_8197F(x) (((x) & BIT_MASK_MCUDMSG_I_8197F) << BIT_SHIFT_MCUDMSG_I_8197F) -#define BITS_MCUDMSG_I_8197F (BIT_MASK_MCUDMSG_I_8197F << BIT_SHIFT_MCUDMSG_I_8197F) +#define BIT_MCUDMSG_I_8197F(x) \ + (((x) & BIT_MASK_MCUDMSG_I_8197F) << BIT_SHIFT_MCUDMSG_I_8197F) +#define BITS_MCUDMSG_I_8197F \ + (BIT_MASK_MCUDMSG_I_8197F << BIT_SHIFT_MCUDMSG_I_8197F) #define BIT_CLEAR_MCUDMSG_I_8197F(x) ((x) & (~BITS_MCUDMSG_I_8197F)) -#define BIT_GET_MCUDMSG_I_8197F(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8197F) & BIT_MASK_MCUDMSG_I_8197F) -#define BIT_SET_MCUDMSG_I_8197F(x, v) (BIT_CLEAR_MCUDMSG_I_8197F(x) | BIT_MCUDMSG_I_8197F(v)) - +#define BIT_GET_MCUDMSG_I_8197F(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_I_8197F) & BIT_MASK_MCUDMSG_I_8197F) +#define BIT_SET_MCUDMSG_I_8197F(x, v) \ + (BIT_CLEAR_MCUDMSG_I_8197F(x) | BIT_MCUDMSG_I_8197F(v)) /* 2 REG_MCUTST_II_8197F */ #define BIT_SHIFT_MCUDMSG_II_8197F 0 #define BIT_MASK_MCUDMSG_II_8197F 0xffffffffL -#define BIT_MCUDMSG_II_8197F(x) (((x) & BIT_MASK_MCUDMSG_II_8197F) << BIT_SHIFT_MCUDMSG_II_8197F) -#define BITS_MCUDMSG_II_8197F (BIT_MASK_MCUDMSG_II_8197F << BIT_SHIFT_MCUDMSG_II_8197F) +#define BIT_MCUDMSG_II_8197F(x) \ + (((x) & BIT_MASK_MCUDMSG_II_8197F) << BIT_SHIFT_MCUDMSG_II_8197F) +#define BITS_MCUDMSG_II_8197F \ + (BIT_MASK_MCUDMSG_II_8197F << BIT_SHIFT_MCUDMSG_II_8197F) #define BIT_CLEAR_MCUDMSG_II_8197F(x) ((x) & (~BITS_MCUDMSG_II_8197F)) -#define BIT_GET_MCUDMSG_II_8197F(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8197F) & BIT_MASK_MCUDMSG_II_8197F) -#define BIT_SET_MCUDMSG_II_8197F(x, v) (BIT_CLEAR_MCUDMSG_II_8197F(x) | BIT_MCUDMSG_II_8197F(v)) - +#define BIT_GET_MCUDMSG_II_8197F(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_II_8197F) & BIT_MASK_MCUDMSG_II_8197F) +#define BIT_SET_MCUDMSG_II_8197F(x, v) \ + (BIT_CLEAR_MCUDMSG_II_8197F(x) | BIT_MCUDMSG_II_8197F(v)) /* 2 REG_FMETHR_8197F */ #define BIT_FMSG_INT_8197F BIT(31) #define BIT_SHIFT_FW_MSG_8197F 0 #define BIT_MASK_FW_MSG_8197F 0xffffffffL -#define BIT_FW_MSG_8197F(x) (((x) & BIT_MASK_FW_MSG_8197F) << BIT_SHIFT_FW_MSG_8197F) +#define BIT_FW_MSG_8197F(x) \ + (((x) & BIT_MASK_FW_MSG_8197F) << BIT_SHIFT_FW_MSG_8197F) #define BITS_FW_MSG_8197F (BIT_MASK_FW_MSG_8197F << BIT_SHIFT_FW_MSG_8197F) #define BIT_CLEAR_FW_MSG_8197F(x) ((x) & (~BITS_FW_MSG_8197F)) -#define BIT_GET_FW_MSG_8197F(x) (((x) >> BIT_SHIFT_FW_MSG_8197F) & BIT_MASK_FW_MSG_8197F) -#define BIT_SET_FW_MSG_8197F(x, v) (BIT_CLEAR_FW_MSG_8197F(x) | BIT_FW_MSG_8197F(v)) - +#define BIT_GET_FW_MSG_8197F(x) \ + (((x) >> BIT_SHIFT_FW_MSG_8197F) & BIT_MASK_FW_MSG_8197F) +#define BIT_SET_FW_MSG_8197F(x, v) \ + (BIT_CLEAR_FW_MSG_8197F(x) | BIT_FW_MSG_8197F(v)) /* 2 REG_HMETFR_8197F */ #define BIT_SHIFT_HRCV_MSG_8197F 24 #define BIT_MASK_HRCV_MSG_8197F 0xff -#define BIT_HRCV_MSG_8197F(x) (((x) & BIT_MASK_HRCV_MSG_8197F) << BIT_SHIFT_HRCV_MSG_8197F) -#define BITS_HRCV_MSG_8197F (BIT_MASK_HRCV_MSG_8197F << BIT_SHIFT_HRCV_MSG_8197F) +#define BIT_HRCV_MSG_8197F(x) \ + (((x) & BIT_MASK_HRCV_MSG_8197F) << BIT_SHIFT_HRCV_MSG_8197F) +#define BITS_HRCV_MSG_8197F \ + (BIT_MASK_HRCV_MSG_8197F << BIT_SHIFT_HRCV_MSG_8197F) #define BIT_CLEAR_HRCV_MSG_8197F(x) ((x) & (~BITS_HRCV_MSG_8197F)) -#define BIT_GET_HRCV_MSG_8197F(x) (((x) >> BIT_SHIFT_HRCV_MSG_8197F) & BIT_MASK_HRCV_MSG_8197F) -#define BIT_SET_HRCV_MSG_8197F(x, v) (BIT_CLEAR_HRCV_MSG_8197F(x) | BIT_HRCV_MSG_8197F(v)) +#define BIT_GET_HRCV_MSG_8197F(x) \ + (((x) >> BIT_SHIFT_HRCV_MSG_8197F) & BIT_MASK_HRCV_MSG_8197F) +#define BIT_SET_HRCV_MSG_8197F(x, v) \ + (BIT_CLEAR_HRCV_MSG_8197F(x) | BIT_HRCV_MSG_8197F(v)) #define BIT_INT_BOX3_8197F BIT(3) #define BIT_INT_BOX2_8197F BIT(2) @@ -3074,113 +3830,155 @@ #define BIT_SHIFT_HOST_MSG_0_8197F 0 #define BIT_MASK_HOST_MSG_0_8197F 0xffffffffL -#define BIT_HOST_MSG_0_8197F(x) (((x) & BIT_MASK_HOST_MSG_0_8197F) << BIT_SHIFT_HOST_MSG_0_8197F) -#define BITS_HOST_MSG_0_8197F (BIT_MASK_HOST_MSG_0_8197F << BIT_SHIFT_HOST_MSG_0_8197F) +#define BIT_HOST_MSG_0_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_0_8197F) << BIT_SHIFT_HOST_MSG_0_8197F) +#define BITS_HOST_MSG_0_8197F \ + (BIT_MASK_HOST_MSG_0_8197F << BIT_SHIFT_HOST_MSG_0_8197F) #define BIT_CLEAR_HOST_MSG_0_8197F(x) ((x) & (~BITS_HOST_MSG_0_8197F)) -#define BIT_GET_HOST_MSG_0_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8197F) & BIT_MASK_HOST_MSG_0_8197F) -#define BIT_SET_HOST_MSG_0_8197F(x, v) (BIT_CLEAR_HOST_MSG_0_8197F(x) | BIT_HOST_MSG_0_8197F(v)) - +#define BIT_GET_HOST_MSG_0_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_0_8197F) & BIT_MASK_HOST_MSG_0_8197F) +#define BIT_SET_HOST_MSG_0_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_0_8197F(x) | BIT_HOST_MSG_0_8197F(v)) /* 2 REG_HMEBOX1_8197F */ #define BIT_SHIFT_HOST_MSG_1_8197F 0 #define BIT_MASK_HOST_MSG_1_8197F 0xffffffffL -#define BIT_HOST_MSG_1_8197F(x) (((x) & BIT_MASK_HOST_MSG_1_8197F) << BIT_SHIFT_HOST_MSG_1_8197F) -#define BITS_HOST_MSG_1_8197F (BIT_MASK_HOST_MSG_1_8197F << BIT_SHIFT_HOST_MSG_1_8197F) +#define BIT_HOST_MSG_1_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_1_8197F) << BIT_SHIFT_HOST_MSG_1_8197F) +#define BITS_HOST_MSG_1_8197F \ + (BIT_MASK_HOST_MSG_1_8197F << BIT_SHIFT_HOST_MSG_1_8197F) #define BIT_CLEAR_HOST_MSG_1_8197F(x) ((x) & (~BITS_HOST_MSG_1_8197F)) -#define BIT_GET_HOST_MSG_1_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8197F) & BIT_MASK_HOST_MSG_1_8197F) -#define BIT_SET_HOST_MSG_1_8197F(x, v) (BIT_CLEAR_HOST_MSG_1_8197F(x) | BIT_HOST_MSG_1_8197F(v)) - +#define BIT_GET_HOST_MSG_1_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_1_8197F) & BIT_MASK_HOST_MSG_1_8197F) +#define BIT_SET_HOST_MSG_1_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_1_8197F(x) | BIT_HOST_MSG_1_8197F(v)) /* 2 REG_HMEBOX2_8197F */ #define BIT_SHIFT_HOST_MSG_2_8197F 0 #define BIT_MASK_HOST_MSG_2_8197F 0xffffffffL -#define BIT_HOST_MSG_2_8197F(x) (((x) & BIT_MASK_HOST_MSG_2_8197F) << BIT_SHIFT_HOST_MSG_2_8197F) -#define BITS_HOST_MSG_2_8197F (BIT_MASK_HOST_MSG_2_8197F << BIT_SHIFT_HOST_MSG_2_8197F) +#define BIT_HOST_MSG_2_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_2_8197F) << BIT_SHIFT_HOST_MSG_2_8197F) +#define BITS_HOST_MSG_2_8197F \ + (BIT_MASK_HOST_MSG_2_8197F << BIT_SHIFT_HOST_MSG_2_8197F) #define BIT_CLEAR_HOST_MSG_2_8197F(x) ((x) & (~BITS_HOST_MSG_2_8197F)) -#define BIT_GET_HOST_MSG_2_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8197F) & BIT_MASK_HOST_MSG_2_8197F) -#define BIT_SET_HOST_MSG_2_8197F(x, v) (BIT_CLEAR_HOST_MSG_2_8197F(x) | BIT_HOST_MSG_2_8197F(v)) - +#define BIT_GET_HOST_MSG_2_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_2_8197F) & BIT_MASK_HOST_MSG_2_8197F) +#define BIT_SET_HOST_MSG_2_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_2_8197F(x) | BIT_HOST_MSG_2_8197F(v)) /* 2 REG_HMEBOX3_8197F */ #define BIT_SHIFT_HOST_MSG_3_8197F 0 #define BIT_MASK_HOST_MSG_3_8197F 0xffffffffL -#define BIT_HOST_MSG_3_8197F(x) (((x) & BIT_MASK_HOST_MSG_3_8197F) << BIT_SHIFT_HOST_MSG_3_8197F) -#define BITS_HOST_MSG_3_8197F (BIT_MASK_HOST_MSG_3_8197F << BIT_SHIFT_HOST_MSG_3_8197F) +#define BIT_HOST_MSG_3_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_3_8197F) << BIT_SHIFT_HOST_MSG_3_8197F) +#define BITS_HOST_MSG_3_8197F \ + (BIT_MASK_HOST_MSG_3_8197F << BIT_SHIFT_HOST_MSG_3_8197F) #define BIT_CLEAR_HOST_MSG_3_8197F(x) ((x) & (~BITS_HOST_MSG_3_8197F)) -#define BIT_GET_HOST_MSG_3_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8197F) & BIT_MASK_HOST_MSG_3_8197F) -#define BIT_SET_HOST_MSG_3_8197F(x, v) (BIT_CLEAR_HOST_MSG_3_8197F(x) | BIT_HOST_MSG_3_8197F(v)) - +#define BIT_GET_HOST_MSG_3_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_3_8197F) & BIT_MASK_HOST_MSG_3_8197F) +#define BIT_SET_HOST_MSG_3_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_3_8197F(x) | BIT_HOST_MSG_3_8197F(v)) /* 2 REG_LLT_INIT_8197F */ #define BIT_SHIFT_LLTE_RWM_8197F 30 #define BIT_MASK_LLTE_RWM_8197F 0x3 -#define BIT_LLTE_RWM_8197F(x) (((x) & BIT_MASK_LLTE_RWM_8197F) << BIT_SHIFT_LLTE_RWM_8197F) -#define BITS_LLTE_RWM_8197F (BIT_MASK_LLTE_RWM_8197F << BIT_SHIFT_LLTE_RWM_8197F) +#define BIT_LLTE_RWM_8197F(x) \ + (((x) & BIT_MASK_LLTE_RWM_8197F) << BIT_SHIFT_LLTE_RWM_8197F) +#define BITS_LLTE_RWM_8197F \ + (BIT_MASK_LLTE_RWM_8197F << BIT_SHIFT_LLTE_RWM_8197F) #define BIT_CLEAR_LLTE_RWM_8197F(x) ((x) & (~BITS_LLTE_RWM_8197F)) -#define BIT_GET_LLTE_RWM_8197F(x) (((x) >> BIT_SHIFT_LLTE_RWM_8197F) & BIT_MASK_LLTE_RWM_8197F) -#define BIT_SET_LLTE_RWM_8197F(x, v) (BIT_CLEAR_LLTE_RWM_8197F(x) | BIT_LLTE_RWM_8197F(v)) - +#define BIT_GET_LLTE_RWM_8197F(x) \ + (((x) >> BIT_SHIFT_LLTE_RWM_8197F) & BIT_MASK_LLTE_RWM_8197F) +#define BIT_SET_LLTE_RWM_8197F(x, v) \ + (BIT_CLEAR_LLTE_RWM_8197F(x) | BIT_LLTE_RWM_8197F(v)) #define BIT_SHIFT_LLTINI_PDATA_V1_8197F 16 #define BIT_MASK_LLTINI_PDATA_V1_8197F 0xfff -#define BIT_LLTINI_PDATA_V1_8197F(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8197F) << BIT_SHIFT_LLTINI_PDATA_V1_8197F) -#define BITS_LLTINI_PDATA_V1_8197F (BIT_MASK_LLTINI_PDATA_V1_8197F << BIT_SHIFT_LLTINI_PDATA_V1_8197F) +#define BIT_LLTINI_PDATA_V1_8197F(x) \ + (((x) & BIT_MASK_LLTINI_PDATA_V1_8197F) \ + << BIT_SHIFT_LLTINI_PDATA_V1_8197F) +#define BITS_LLTINI_PDATA_V1_8197F \ + (BIT_MASK_LLTINI_PDATA_V1_8197F << BIT_SHIFT_LLTINI_PDATA_V1_8197F) #define BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) ((x) & (~BITS_LLTINI_PDATA_V1_8197F)) -#define BIT_GET_LLTINI_PDATA_V1_8197F(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8197F) & BIT_MASK_LLTINI_PDATA_V1_8197F) -#define BIT_SET_LLTINI_PDATA_V1_8197F(x, v) (BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) | BIT_LLTINI_PDATA_V1_8197F(v)) - +#define BIT_GET_LLTINI_PDATA_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8197F) & \ + BIT_MASK_LLTINI_PDATA_V1_8197F) +#define BIT_SET_LLTINI_PDATA_V1_8197F(x, v) \ + (BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) | BIT_LLTINI_PDATA_V1_8197F(v)) #define BIT_SHIFT_LLTINI_HDATA_V1_8197F 0 #define BIT_MASK_LLTINI_HDATA_V1_8197F 0xfff -#define BIT_LLTINI_HDATA_V1_8197F(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8197F) << BIT_SHIFT_LLTINI_HDATA_V1_8197F) -#define BITS_LLTINI_HDATA_V1_8197F (BIT_MASK_LLTINI_HDATA_V1_8197F << BIT_SHIFT_LLTINI_HDATA_V1_8197F) +#define BIT_LLTINI_HDATA_V1_8197F(x) \ + (((x) & BIT_MASK_LLTINI_HDATA_V1_8197F) \ + << BIT_SHIFT_LLTINI_HDATA_V1_8197F) +#define BITS_LLTINI_HDATA_V1_8197F \ + (BIT_MASK_LLTINI_HDATA_V1_8197F << BIT_SHIFT_LLTINI_HDATA_V1_8197F) #define BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) ((x) & (~BITS_LLTINI_HDATA_V1_8197F)) -#define BIT_GET_LLTINI_HDATA_V1_8197F(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8197F) & BIT_MASK_LLTINI_HDATA_V1_8197F) -#define BIT_SET_LLTINI_HDATA_V1_8197F(x, v) (BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) | BIT_LLTINI_HDATA_V1_8197F(v)) - +#define BIT_GET_LLTINI_HDATA_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8197F) & \ + BIT_MASK_LLTINI_HDATA_V1_8197F) +#define BIT_SET_LLTINI_HDATA_V1_8197F(x, v) \ + (BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) | BIT_LLTINI_HDATA_V1_8197F(v)) /* 2 REG_LLT_INIT_ADDR_8197F */ #define BIT_SHIFT_LLTINI_ADDR_V1_8197F 0 #define BIT_MASK_LLTINI_ADDR_V1_8197F 0xfff -#define BIT_LLTINI_ADDR_V1_8197F(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8197F) << BIT_SHIFT_LLTINI_ADDR_V1_8197F) -#define BITS_LLTINI_ADDR_V1_8197F (BIT_MASK_LLTINI_ADDR_V1_8197F << BIT_SHIFT_LLTINI_ADDR_V1_8197F) +#define BIT_LLTINI_ADDR_V1_8197F(x) \ + (((x) & BIT_MASK_LLTINI_ADDR_V1_8197F) \ + << BIT_SHIFT_LLTINI_ADDR_V1_8197F) +#define BITS_LLTINI_ADDR_V1_8197F \ + (BIT_MASK_LLTINI_ADDR_V1_8197F << BIT_SHIFT_LLTINI_ADDR_V1_8197F) #define BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) ((x) & (~BITS_LLTINI_ADDR_V1_8197F)) -#define BIT_GET_LLTINI_ADDR_V1_8197F(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8197F) & BIT_MASK_LLTINI_ADDR_V1_8197F) -#define BIT_SET_LLTINI_ADDR_V1_8197F(x, v) (BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) | BIT_LLTINI_ADDR_V1_8197F(v)) - +#define BIT_GET_LLTINI_ADDR_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8197F) & \ + BIT_MASK_LLTINI_ADDR_V1_8197F) +#define BIT_SET_LLTINI_ADDR_V1_8197F(x, v) \ + (BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) | BIT_LLTINI_ADDR_V1_8197F(v)) /* 2 REG_BB_ACCESS_CTRL_8197F */ #define BIT_SHIFT_BB_WRITE_READ_8197F 30 #define BIT_MASK_BB_WRITE_READ_8197F 0x3 -#define BIT_BB_WRITE_READ_8197F(x) (((x) & BIT_MASK_BB_WRITE_READ_8197F) << BIT_SHIFT_BB_WRITE_READ_8197F) -#define BITS_BB_WRITE_READ_8197F (BIT_MASK_BB_WRITE_READ_8197F << BIT_SHIFT_BB_WRITE_READ_8197F) +#define BIT_BB_WRITE_READ_8197F(x) \ + (((x) & BIT_MASK_BB_WRITE_READ_8197F) << BIT_SHIFT_BB_WRITE_READ_8197F) +#define BITS_BB_WRITE_READ_8197F \ + (BIT_MASK_BB_WRITE_READ_8197F << BIT_SHIFT_BB_WRITE_READ_8197F) #define BIT_CLEAR_BB_WRITE_READ_8197F(x) ((x) & (~BITS_BB_WRITE_READ_8197F)) -#define BIT_GET_BB_WRITE_READ_8197F(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8197F) & BIT_MASK_BB_WRITE_READ_8197F) -#define BIT_SET_BB_WRITE_READ_8197F(x, v) (BIT_CLEAR_BB_WRITE_READ_8197F(x) | BIT_BB_WRITE_READ_8197F(v)) - +#define BIT_GET_BB_WRITE_READ_8197F(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_READ_8197F) & BIT_MASK_BB_WRITE_READ_8197F) +#define BIT_SET_BB_WRITE_READ_8197F(x, v) \ + (BIT_CLEAR_BB_WRITE_READ_8197F(x) | BIT_BB_WRITE_READ_8197F(v)) #define BIT_SHIFT_BB_WRITE_EN_V1_8197F 16 #define BIT_MASK_BB_WRITE_EN_V1_8197F 0xf -#define BIT_BB_WRITE_EN_V1_8197F(x) (((x) & BIT_MASK_BB_WRITE_EN_V1_8197F) << BIT_SHIFT_BB_WRITE_EN_V1_8197F) -#define BITS_BB_WRITE_EN_V1_8197F (BIT_MASK_BB_WRITE_EN_V1_8197F << BIT_SHIFT_BB_WRITE_EN_V1_8197F) +#define BIT_BB_WRITE_EN_V1_8197F(x) \ + (((x) & BIT_MASK_BB_WRITE_EN_V1_8197F) \ + << BIT_SHIFT_BB_WRITE_EN_V1_8197F) +#define BITS_BB_WRITE_EN_V1_8197F \ + (BIT_MASK_BB_WRITE_EN_V1_8197F << BIT_SHIFT_BB_WRITE_EN_V1_8197F) #define BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) ((x) & (~BITS_BB_WRITE_EN_V1_8197F)) -#define BIT_GET_BB_WRITE_EN_V1_8197F(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_V1_8197F) & BIT_MASK_BB_WRITE_EN_V1_8197F) -#define BIT_SET_BB_WRITE_EN_V1_8197F(x, v) (BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) | BIT_BB_WRITE_EN_V1_8197F(v)) - +#define BIT_GET_BB_WRITE_EN_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN_V1_8197F) & \ + BIT_MASK_BB_WRITE_EN_V1_8197F) +#define BIT_SET_BB_WRITE_EN_V1_8197F(x, v) \ + (BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) | BIT_BB_WRITE_EN_V1_8197F(v)) #define BIT_SHIFT_BB_ADDR_V1_8197F 2 #define BIT_MASK_BB_ADDR_V1_8197F 0xfff -#define BIT_BB_ADDR_V1_8197F(x) (((x) & BIT_MASK_BB_ADDR_V1_8197F) << BIT_SHIFT_BB_ADDR_V1_8197F) -#define BITS_BB_ADDR_V1_8197F (BIT_MASK_BB_ADDR_V1_8197F << BIT_SHIFT_BB_ADDR_V1_8197F) +#define BIT_BB_ADDR_V1_8197F(x) \ + (((x) & BIT_MASK_BB_ADDR_V1_8197F) << BIT_SHIFT_BB_ADDR_V1_8197F) +#define BITS_BB_ADDR_V1_8197F \ + (BIT_MASK_BB_ADDR_V1_8197F << BIT_SHIFT_BB_ADDR_V1_8197F) #define BIT_CLEAR_BB_ADDR_V1_8197F(x) ((x) & (~BITS_BB_ADDR_V1_8197F)) -#define BIT_GET_BB_ADDR_V1_8197F(x) (((x) >> BIT_SHIFT_BB_ADDR_V1_8197F) & BIT_MASK_BB_ADDR_V1_8197F) -#define BIT_SET_BB_ADDR_V1_8197F(x, v) (BIT_CLEAR_BB_ADDR_V1_8197F(x) | BIT_BB_ADDR_V1_8197F(v)) +#define BIT_GET_BB_ADDR_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BB_ADDR_V1_8197F) & BIT_MASK_BB_ADDR_V1_8197F) +#define BIT_SET_BB_ADDR_V1_8197F(x, v) \ + (BIT_CLEAR_BB_ADDR_V1_8197F(x) | BIT_BB_ADDR_V1_8197F(v)) #define BIT_BB_ERRACC_8197F BIT(0) @@ -3188,56 +3986,70 @@ #define BIT_SHIFT_BB_DATA_8197F 0 #define BIT_MASK_BB_DATA_8197F 0xffffffffL -#define BIT_BB_DATA_8197F(x) (((x) & BIT_MASK_BB_DATA_8197F) << BIT_SHIFT_BB_DATA_8197F) +#define BIT_BB_DATA_8197F(x) \ + (((x) & BIT_MASK_BB_DATA_8197F) << BIT_SHIFT_BB_DATA_8197F) #define BITS_BB_DATA_8197F (BIT_MASK_BB_DATA_8197F << BIT_SHIFT_BB_DATA_8197F) #define BIT_CLEAR_BB_DATA_8197F(x) ((x) & (~BITS_BB_DATA_8197F)) -#define BIT_GET_BB_DATA_8197F(x) (((x) >> BIT_SHIFT_BB_DATA_8197F) & BIT_MASK_BB_DATA_8197F) -#define BIT_SET_BB_DATA_8197F(x, v) (BIT_CLEAR_BB_DATA_8197F(x) | BIT_BB_DATA_8197F(v)) - +#define BIT_GET_BB_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_BB_DATA_8197F) & BIT_MASK_BB_DATA_8197F) +#define BIT_SET_BB_DATA_8197F(x, v) \ + (BIT_CLEAR_BB_DATA_8197F(x) | BIT_BB_DATA_8197F(v)) /* 2 REG_HMEBOX_E0_8197F */ #define BIT_SHIFT_HMEBOX_E0_8197F 0 #define BIT_MASK_HMEBOX_E0_8197F 0xffffffffL -#define BIT_HMEBOX_E0_8197F(x) (((x) & BIT_MASK_HMEBOX_E0_8197F) << BIT_SHIFT_HMEBOX_E0_8197F) -#define BITS_HMEBOX_E0_8197F (BIT_MASK_HMEBOX_E0_8197F << BIT_SHIFT_HMEBOX_E0_8197F) +#define BIT_HMEBOX_E0_8197F(x) \ + (((x) & BIT_MASK_HMEBOX_E0_8197F) << BIT_SHIFT_HMEBOX_E0_8197F) +#define BITS_HMEBOX_E0_8197F \ + (BIT_MASK_HMEBOX_E0_8197F << BIT_SHIFT_HMEBOX_E0_8197F) #define BIT_CLEAR_HMEBOX_E0_8197F(x) ((x) & (~BITS_HMEBOX_E0_8197F)) -#define BIT_GET_HMEBOX_E0_8197F(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8197F) & BIT_MASK_HMEBOX_E0_8197F) -#define BIT_SET_HMEBOX_E0_8197F(x, v) (BIT_CLEAR_HMEBOX_E0_8197F(x) | BIT_HMEBOX_E0_8197F(v)) - +#define BIT_GET_HMEBOX_E0_8197F(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E0_8197F) & BIT_MASK_HMEBOX_E0_8197F) +#define BIT_SET_HMEBOX_E0_8197F(x, v) \ + (BIT_CLEAR_HMEBOX_E0_8197F(x) | BIT_HMEBOX_E0_8197F(v)) /* 2 REG_HMEBOX_E1_8197F */ #define BIT_SHIFT_HMEBOX_E1_8197F 0 #define BIT_MASK_HMEBOX_E1_8197F 0xffffffffL -#define BIT_HMEBOX_E1_8197F(x) (((x) & BIT_MASK_HMEBOX_E1_8197F) << BIT_SHIFT_HMEBOX_E1_8197F) -#define BITS_HMEBOX_E1_8197F (BIT_MASK_HMEBOX_E1_8197F << BIT_SHIFT_HMEBOX_E1_8197F) +#define BIT_HMEBOX_E1_8197F(x) \ + (((x) & BIT_MASK_HMEBOX_E1_8197F) << BIT_SHIFT_HMEBOX_E1_8197F) +#define BITS_HMEBOX_E1_8197F \ + (BIT_MASK_HMEBOX_E1_8197F << BIT_SHIFT_HMEBOX_E1_8197F) #define BIT_CLEAR_HMEBOX_E1_8197F(x) ((x) & (~BITS_HMEBOX_E1_8197F)) -#define BIT_GET_HMEBOX_E1_8197F(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8197F) & BIT_MASK_HMEBOX_E1_8197F) -#define BIT_SET_HMEBOX_E1_8197F(x, v) (BIT_CLEAR_HMEBOX_E1_8197F(x) | BIT_HMEBOX_E1_8197F(v)) - +#define BIT_GET_HMEBOX_E1_8197F(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E1_8197F) & BIT_MASK_HMEBOX_E1_8197F) +#define BIT_SET_HMEBOX_E1_8197F(x, v) \ + (BIT_CLEAR_HMEBOX_E1_8197F(x) | BIT_HMEBOX_E1_8197F(v)) /* 2 REG_HMEBOX_E2_8197F */ #define BIT_SHIFT_HMEBOX_E2_8197F 0 #define BIT_MASK_HMEBOX_E2_8197F 0xffffffffL -#define BIT_HMEBOX_E2_8197F(x) (((x) & BIT_MASK_HMEBOX_E2_8197F) << BIT_SHIFT_HMEBOX_E2_8197F) -#define BITS_HMEBOX_E2_8197F (BIT_MASK_HMEBOX_E2_8197F << BIT_SHIFT_HMEBOX_E2_8197F) +#define BIT_HMEBOX_E2_8197F(x) \ + (((x) & BIT_MASK_HMEBOX_E2_8197F) << BIT_SHIFT_HMEBOX_E2_8197F) +#define BITS_HMEBOX_E2_8197F \ + (BIT_MASK_HMEBOX_E2_8197F << BIT_SHIFT_HMEBOX_E2_8197F) #define BIT_CLEAR_HMEBOX_E2_8197F(x) ((x) & (~BITS_HMEBOX_E2_8197F)) -#define BIT_GET_HMEBOX_E2_8197F(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8197F) & BIT_MASK_HMEBOX_E2_8197F) -#define BIT_SET_HMEBOX_E2_8197F(x, v) (BIT_CLEAR_HMEBOX_E2_8197F(x) | BIT_HMEBOX_E2_8197F(v)) - +#define BIT_GET_HMEBOX_E2_8197F(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E2_8197F) & BIT_MASK_HMEBOX_E2_8197F) +#define BIT_SET_HMEBOX_E2_8197F(x, v) \ + (BIT_CLEAR_HMEBOX_E2_8197F(x) | BIT_HMEBOX_E2_8197F(v)) /* 2 REG_HMEBOX_E3_8197F */ #define BIT_SHIFT_HMEBOX_E3_8197F 0 #define BIT_MASK_HMEBOX_E3_8197F 0xffffffffL -#define BIT_HMEBOX_E3_8197F(x) (((x) & BIT_MASK_HMEBOX_E3_8197F) << BIT_SHIFT_HMEBOX_E3_8197F) -#define BITS_HMEBOX_E3_8197F (BIT_MASK_HMEBOX_E3_8197F << BIT_SHIFT_HMEBOX_E3_8197F) +#define BIT_HMEBOX_E3_8197F(x) \ + (((x) & BIT_MASK_HMEBOX_E3_8197F) << BIT_SHIFT_HMEBOX_E3_8197F) +#define BITS_HMEBOX_E3_8197F \ + (BIT_MASK_HMEBOX_E3_8197F << BIT_SHIFT_HMEBOX_E3_8197F) #define BIT_CLEAR_HMEBOX_E3_8197F(x) ((x) & (~BITS_HMEBOX_E3_8197F)) -#define BIT_GET_HMEBOX_E3_8197F(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8197F) & BIT_MASK_HMEBOX_E3_8197F) -#define BIT_SET_HMEBOX_E3_8197F(x, v) (BIT_CLEAR_HMEBOX_E3_8197F(x) | BIT_HMEBOX_E3_8197F(v)) - +#define BIT_GET_HMEBOX_E3_8197F(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E3_8197F) & BIT_MASK_HMEBOX_E3_8197F) +#define BIT_SET_HMEBOX_E3_8197F(x, v) \ + (BIT_CLEAR_HMEBOX_E3_8197F(x) | BIT_HMEBOX_E3_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -3245,69 +4057,88 @@ #define BIT_SHIFT_PHY_REQ_DELAY_8197F 24 #define BIT_MASK_PHY_REQ_DELAY_8197F 0xf -#define BIT_PHY_REQ_DELAY_8197F(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8197F) << BIT_SHIFT_PHY_REQ_DELAY_8197F) -#define BITS_PHY_REQ_DELAY_8197F (BIT_MASK_PHY_REQ_DELAY_8197F << BIT_SHIFT_PHY_REQ_DELAY_8197F) +#define BIT_PHY_REQ_DELAY_8197F(x) \ + (((x) & BIT_MASK_PHY_REQ_DELAY_8197F) << BIT_SHIFT_PHY_REQ_DELAY_8197F) +#define BITS_PHY_REQ_DELAY_8197F \ + (BIT_MASK_PHY_REQ_DELAY_8197F << BIT_SHIFT_PHY_REQ_DELAY_8197F) #define BIT_CLEAR_PHY_REQ_DELAY_8197F(x) ((x) & (~BITS_PHY_REQ_DELAY_8197F)) -#define BIT_GET_PHY_REQ_DELAY_8197F(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8197F) & BIT_MASK_PHY_REQ_DELAY_8197F) -#define BIT_SET_PHY_REQ_DELAY_8197F(x, v) (BIT_CLEAR_PHY_REQ_DELAY_8197F(x) | BIT_PHY_REQ_DELAY_8197F(v)) +#define BIT_GET_PHY_REQ_DELAY_8197F(x) \ + (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8197F) & BIT_MASK_PHY_REQ_DELAY_8197F) +#define BIT_SET_PHY_REQ_DELAY_8197F(x, v) \ + (BIT_CLEAR_PHY_REQ_DELAY_8197F(x) | BIT_PHY_REQ_DELAY_8197F(v)) #define BIT_SPD_DOWN_8197F BIT(16) #define BIT_SHIFT_NETYPE4_8197F 4 #define BIT_MASK_NETYPE4_8197F 0x3 -#define BIT_NETYPE4_8197F(x) (((x) & BIT_MASK_NETYPE4_8197F) << BIT_SHIFT_NETYPE4_8197F) +#define BIT_NETYPE4_8197F(x) \ + (((x) & BIT_MASK_NETYPE4_8197F) << BIT_SHIFT_NETYPE4_8197F) #define BITS_NETYPE4_8197F (BIT_MASK_NETYPE4_8197F << BIT_SHIFT_NETYPE4_8197F) #define BIT_CLEAR_NETYPE4_8197F(x) ((x) & (~BITS_NETYPE4_8197F)) -#define BIT_GET_NETYPE4_8197F(x) (((x) >> BIT_SHIFT_NETYPE4_8197F) & BIT_MASK_NETYPE4_8197F) -#define BIT_SET_NETYPE4_8197F(x, v) (BIT_CLEAR_NETYPE4_8197F(x) | BIT_NETYPE4_8197F(v)) - +#define BIT_GET_NETYPE4_8197F(x) \ + (((x) >> BIT_SHIFT_NETYPE4_8197F) & BIT_MASK_NETYPE4_8197F) +#define BIT_SET_NETYPE4_8197F(x, v) \ + (BIT_CLEAR_NETYPE4_8197F(x) | BIT_NETYPE4_8197F(v)) #define BIT_SHIFT_NETYPE3_8197F 2 #define BIT_MASK_NETYPE3_8197F 0x3 -#define BIT_NETYPE3_8197F(x) (((x) & BIT_MASK_NETYPE3_8197F) << BIT_SHIFT_NETYPE3_8197F) +#define BIT_NETYPE3_8197F(x) \ + (((x) & BIT_MASK_NETYPE3_8197F) << BIT_SHIFT_NETYPE3_8197F) #define BITS_NETYPE3_8197F (BIT_MASK_NETYPE3_8197F << BIT_SHIFT_NETYPE3_8197F) #define BIT_CLEAR_NETYPE3_8197F(x) ((x) & (~BITS_NETYPE3_8197F)) -#define BIT_GET_NETYPE3_8197F(x) (((x) >> BIT_SHIFT_NETYPE3_8197F) & BIT_MASK_NETYPE3_8197F) -#define BIT_SET_NETYPE3_8197F(x, v) (BIT_CLEAR_NETYPE3_8197F(x) | BIT_NETYPE3_8197F(v)) - +#define BIT_GET_NETYPE3_8197F(x) \ + (((x) >> BIT_SHIFT_NETYPE3_8197F) & BIT_MASK_NETYPE3_8197F) +#define BIT_SET_NETYPE3_8197F(x, v) \ + (BIT_CLEAR_NETYPE3_8197F(x) | BIT_NETYPE3_8197F(v)) #define BIT_SHIFT_NETYPE2_8197F 0 #define BIT_MASK_NETYPE2_8197F 0x3 -#define BIT_NETYPE2_8197F(x) (((x) & BIT_MASK_NETYPE2_8197F) << BIT_SHIFT_NETYPE2_8197F) +#define BIT_NETYPE2_8197F(x) \ + (((x) & BIT_MASK_NETYPE2_8197F) << BIT_SHIFT_NETYPE2_8197F) #define BITS_NETYPE2_8197F (BIT_MASK_NETYPE2_8197F << BIT_SHIFT_NETYPE2_8197F) #define BIT_CLEAR_NETYPE2_8197F(x) ((x) & (~BITS_NETYPE2_8197F)) -#define BIT_GET_NETYPE2_8197F(x) (((x) >> BIT_SHIFT_NETYPE2_8197F) & BIT_MASK_NETYPE2_8197F) -#define BIT_SET_NETYPE2_8197F(x, v) (BIT_CLEAR_NETYPE2_8197F(x) | BIT_NETYPE2_8197F(v)) - +#define BIT_GET_NETYPE2_8197F(x) \ + (((x) >> BIT_SHIFT_NETYPE2_8197F) & BIT_MASK_NETYPE2_8197F) +#define BIT_SET_NETYPE2_8197F(x, v) \ + (BIT_CLEAR_NETYPE2_8197F(x) | BIT_NETYPE2_8197F(v)) /* 2 REG_FWFF_8197F */ #define BIT_SHIFT_PKTNUM_TH_8197F 24 #define BIT_MASK_PKTNUM_TH_8197F 0xff -#define BIT_PKTNUM_TH_8197F(x) (((x) & BIT_MASK_PKTNUM_TH_8197F) << BIT_SHIFT_PKTNUM_TH_8197F) -#define BITS_PKTNUM_TH_8197F (BIT_MASK_PKTNUM_TH_8197F << BIT_SHIFT_PKTNUM_TH_8197F) +#define BIT_PKTNUM_TH_8197F(x) \ + (((x) & BIT_MASK_PKTNUM_TH_8197F) << BIT_SHIFT_PKTNUM_TH_8197F) +#define BITS_PKTNUM_TH_8197F \ + (BIT_MASK_PKTNUM_TH_8197F << BIT_SHIFT_PKTNUM_TH_8197F) #define BIT_CLEAR_PKTNUM_TH_8197F(x) ((x) & (~BITS_PKTNUM_TH_8197F)) -#define BIT_GET_PKTNUM_TH_8197F(x) (((x) >> BIT_SHIFT_PKTNUM_TH_8197F) & BIT_MASK_PKTNUM_TH_8197F) -#define BIT_SET_PKTNUM_TH_8197F(x, v) (BIT_CLEAR_PKTNUM_TH_8197F(x) | BIT_PKTNUM_TH_8197F(v)) - +#define BIT_GET_PKTNUM_TH_8197F(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_8197F) & BIT_MASK_PKTNUM_TH_8197F) +#define BIT_SET_PKTNUM_TH_8197F(x, v) \ + (BIT_CLEAR_PKTNUM_TH_8197F(x) | BIT_PKTNUM_TH_8197F(v)) #define BIT_SHIFT_TIMER_TH_8197F 16 #define BIT_MASK_TIMER_TH_8197F 0xff -#define BIT_TIMER_TH_8197F(x) (((x) & BIT_MASK_TIMER_TH_8197F) << BIT_SHIFT_TIMER_TH_8197F) -#define BITS_TIMER_TH_8197F (BIT_MASK_TIMER_TH_8197F << BIT_SHIFT_TIMER_TH_8197F) +#define BIT_TIMER_TH_8197F(x) \ + (((x) & BIT_MASK_TIMER_TH_8197F) << BIT_SHIFT_TIMER_TH_8197F) +#define BITS_TIMER_TH_8197F \ + (BIT_MASK_TIMER_TH_8197F << BIT_SHIFT_TIMER_TH_8197F) #define BIT_CLEAR_TIMER_TH_8197F(x) ((x) & (~BITS_TIMER_TH_8197F)) -#define BIT_GET_TIMER_TH_8197F(x) (((x) >> BIT_SHIFT_TIMER_TH_8197F) & BIT_MASK_TIMER_TH_8197F) -#define BIT_SET_TIMER_TH_8197F(x, v) (BIT_CLEAR_TIMER_TH_8197F(x) | BIT_TIMER_TH_8197F(v)) - +#define BIT_GET_TIMER_TH_8197F(x) \ + (((x) >> BIT_SHIFT_TIMER_TH_8197F) & BIT_MASK_TIMER_TH_8197F) +#define BIT_SET_TIMER_TH_8197F(x, v) \ + (BIT_CLEAR_TIMER_TH_8197F(x) | BIT_TIMER_TH_8197F(v)) #define BIT_SHIFT_RXPKT1ENADDR_8197F 0 #define BIT_MASK_RXPKT1ENADDR_8197F 0xffff -#define BIT_RXPKT1ENADDR_8197F(x) (((x) & BIT_MASK_RXPKT1ENADDR_8197F) << BIT_SHIFT_RXPKT1ENADDR_8197F) -#define BITS_RXPKT1ENADDR_8197F (BIT_MASK_RXPKT1ENADDR_8197F << BIT_SHIFT_RXPKT1ENADDR_8197F) +#define BIT_RXPKT1ENADDR_8197F(x) \ + (((x) & BIT_MASK_RXPKT1ENADDR_8197F) << BIT_SHIFT_RXPKT1ENADDR_8197F) +#define BITS_RXPKT1ENADDR_8197F \ + (BIT_MASK_RXPKT1ENADDR_8197F << BIT_SHIFT_RXPKT1ENADDR_8197F) #define BIT_CLEAR_RXPKT1ENADDR_8197F(x) ((x) & (~BITS_RXPKT1ENADDR_8197F)) -#define BIT_GET_RXPKT1ENADDR_8197F(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8197F) & BIT_MASK_RXPKT1ENADDR_8197F) -#define BIT_SET_RXPKT1ENADDR_8197F(x, v) (BIT_CLEAR_RXPKT1ENADDR_8197F(x) | BIT_RXPKT1ENADDR_8197F(v)) - +#define BIT_GET_RXPKT1ENADDR_8197F(x) \ + (((x) >> BIT_SHIFT_RXPKT1ENADDR_8197F) & BIT_MASK_RXPKT1ENADDR_8197F) +#define BIT_SET_RXPKT1ENADDR_8197F(x, v) \ + (BIT_CLEAR_RXPKT1ENADDR_8197F(x) | BIT_RXPKT1ENADDR_8197F(v)) /* 2 REG_RXFF_PTR_V1_8197F */ @@ -3315,12 +4146,17 @@ #define BIT_SHIFT_RXFF0_RDPTR_V2_8197F 0 #define BIT_MASK_RXFF0_RDPTR_V2_8197F 0x3ffff -#define BIT_RXFF0_RDPTR_V2_8197F(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8197F) << BIT_SHIFT_RXFF0_RDPTR_V2_8197F) -#define BITS_RXFF0_RDPTR_V2_8197F (BIT_MASK_RXFF0_RDPTR_V2_8197F << BIT_SHIFT_RXFF0_RDPTR_V2_8197F) +#define BIT_RXFF0_RDPTR_V2_8197F(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V2_8197F) \ + << BIT_SHIFT_RXFF0_RDPTR_V2_8197F) +#define BITS_RXFF0_RDPTR_V2_8197F \ + (BIT_MASK_RXFF0_RDPTR_V2_8197F << BIT_SHIFT_RXFF0_RDPTR_V2_8197F) #define BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8197F)) -#define BIT_GET_RXFF0_RDPTR_V2_8197F(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8197F) & BIT_MASK_RXFF0_RDPTR_V2_8197F) -#define BIT_SET_RXFF0_RDPTR_V2_8197F(x, v) (BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) | BIT_RXFF0_RDPTR_V2_8197F(v)) - +#define BIT_GET_RXFF0_RDPTR_V2_8197F(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8197F) & \ + BIT_MASK_RXFF0_RDPTR_V2_8197F) +#define BIT_SET_RXFF0_RDPTR_V2_8197F(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) | BIT_RXFF0_RDPTR_V2_8197F(v)) /* 2 REG_RXFF_WTR_V1_8197F */ @@ -3328,12 +4164,17 @@ #define BIT_SHIFT_RXFF0_WTPTR_V2_8197F 0 #define BIT_MASK_RXFF0_WTPTR_V2_8197F 0x3ffff -#define BIT_RXFF0_WTPTR_V2_8197F(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8197F) << BIT_SHIFT_RXFF0_WTPTR_V2_8197F) -#define BITS_RXFF0_WTPTR_V2_8197F (BIT_MASK_RXFF0_WTPTR_V2_8197F << BIT_SHIFT_RXFF0_WTPTR_V2_8197F) +#define BIT_RXFF0_WTPTR_V2_8197F(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V2_8197F) \ + << BIT_SHIFT_RXFF0_WTPTR_V2_8197F) +#define BITS_RXFF0_WTPTR_V2_8197F \ + (BIT_MASK_RXFF0_WTPTR_V2_8197F << BIT_SHIFT_RXFF0_WTPTR_V2_8197F) #define BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8197F)) -#define BIT_GET_RXFF0_WTPTR_V2_8197F(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8197F) & BIT_MASK_RXFF0_WTPTR_V2_8197F) -#define BIT_SET_RXFF0_WTPTR_V2_8197F(x, v) (BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) | BIT_RXFF0_WTPTR_V2_8197F(v)) - +#define BIT_GET_RXFF0_WTPTR_V2_8197F(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8197F) & \ + BIT_MASK_RXFF0_WTPTR_V2_8197F) +#define BIT_SET_RXFF0_WTPTR_V2_8197F(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) | BIT_RXFF0_WTPTR_V2_8197F(v)) /* 2 REG_FE2IMR_8197F */ #define BIT_FS_TXSC_DESC_DONE_INT_EN_8197F BIT(28) @@ -3565,65 +4406,82 @@ #define BIT_SHIFT_MID_31TO0_8197F 0 #define BIT_MASK_MID_31TO0_8197F 0xffffffffL -#define BIT_MID_31TO0_8197F(x) (((x) & BIT_MASK_MID_31TO0_8197F) << BIT_SHIFT_MID_31TO0_8197F) -#define BITS_MID_31TO0_8197F (BIT_MASK_MID_31TO0_8197F << BIT_SHIFT_MID_31TO0_8197F) +#define BIT_MID_31TO0_8197F(x) \ + (((x) & BIT_MASK_MID_31TO0_8197F) << BIT_SHIFT_MID_31TO0_8197F) +#define BITS_MID_31TO0_8197F \ + (BIT_MASK_MID_31TO0_8197F << BIT_SHIFT_MID_31TO0_8197F) #define BIT_CLEAR_MID_31TO0_8197F(x) ((x) & (~BITS_MID_31TO0_8197F)) -#define BIT_GET_MID_31TO0_8197F(x) (((x) >> BIT_SHIFT_MID_31TO0_8197F) & BIT_MASK_MID_31TO0_8197F) -#define BIT_SET_MID_31TO0_8197F(x, v) (BIT_CLEAR_MID_31TO0_8197F(x) | BIT_MID_31TO0_8197F(v)) - +#define BIT_GET_MID_31TO0_8197F(x) \ + (((x) >> BIT_SHIFT_MID_31TO0_8197F) & BIT_MASK_MID_31TO0_8197F) +#define BIT_SET_MID_31TO0_8197F(x, v) \ + (BIT_CLEAR_MID_31TO0_8197F(x) | BIT_MID_31TO0_8197F(v)) /* 2 REG_SPWR1_8197F */ #define BIT_SHIFT_MID_63TO32_8197F 0 #define BIT_MASK_MID_63TO32_8197F 0xffffffffL -#define BIT_MID_63TO32_8197F(x) (((x) & BIT_MASK_MID_63TO32_8197F) << BIT_SHIFT_MID_63TO32_8197F) -#define BITS_MID_63TO32_8197F (BIT_MASK_MID_63TO32_8197F << BIT_SHIFT_MID_63TO32_8197F) +#define BIT_MID_63TO32_8197F(x) \ + (((x) & BIT_MASK_MID_63TO32_8197F) << BIT_SHIFT_MID_63TO32_8197F) +#define BITS_MID_63TO32_8197F \ + (BIT_MASK_MID_63TO32_8197F << BIT_SHIFT_MID_63TO32_8197F) #define BIT_CLEAR_MID_63TO32_8197F(x) ((x) & (~BITS_MID_63TO32_8197F)) -#define BIT_GET_MID_63TO32_8197F(x) (((x) >> BIT_SHIFT_MID_63TO32_8197F) & BIT_MASK_MID_63TO32_8197F) -#define BIT_SET_MID_63TO32_8197F(x, v) (BIT_CLEAR_MID_63TO32_8197F(x) | BIT_MID_63TO32_8197F(v)) - +#define BIT_GET_MID_63TO32_8197F(x) \ + (((x) >> BIT_SHIFT_MID_63TO32_8197F) & BIT_MASK_MID_63TO32_8197F) +#define BIT_SET_MID_63TO32_8197F(x, v) \ + (BIT_CLEAR_MID_63TO32_8197F(x) | BIT_MID_63TO32_8197F(v)) /* 2 REG_SPWR2_8197F */ #define BIT_SHIFT_MID_95O64_8197F 0 #define BIT_MASK_MID_95O64_8197F 0xffffffffL -#define BIT_MID_95O64_8197F(x) (((x) & BIT_MASK_MID_95O64_8197F) << BIT_SHIFT_MID_95O64_8197F) -#define BITS_MID_95O64_8197F (BIT_MASK_MID_95O64_8197F << BIT_SHIFT_MID_95O64_8197F) +#define BIT_MID_95O64_8197F(x) \ + (((x) & BIT_MASK_MID_95O64_8197F) << BIT_SHIFT_MID_95O64_8197F) +#define BITS_MID_95O64_8197F \ + (BIT_MASK_MID_95O64_8197F << BIT_SHIFT_MID_95O64_8197F) #define BIT_CLEAR_MID_95O64_8197F(x) ((x) & (~BITS_MID_95O64_8197F)) -#define BIT_GET_MID_95O64_8197F(x) (((x) >> BIT_SHIFT_MID_95O64_8197F) & BIT_MASK_MID_95O64_8197F) -#define BIT_SET_MID_95O64_8197F(x, v) (BIT_CLEAR_MID_95O64_8197F(x) | BIT_MID_95O64_8197F(v)) - +#define BIT_GET_MID_95O64_8197F(x) \ + (((x) >> BIT_SHIFT_MID_95O64_8197F) & BIT_MASK_MID_95O64_8197F) +#define BIT_SET_MID_95O64_8197F(x, v) \ + (BIT_CLEAR_MID_95O64_8197F(x) | BIT_MID_95O64_8197F(v)) /* 2 REG_SPWR3_8197F */ #define BIT_SHIFT_MID_127TO96_8197F 0 #define BIT_MASK_MID_127TO96_8197F 0xffffffffL -#define BIT_MID_127TO96_8197F(x) (((x) & BIT_MASK_MID_127TO96_8197F) << BIT_SHIFT_MID_127TO96_8197F) -#define BITS_MID_127TO96_8197F (BIT_MASK_MID_127TO96_8197F << BIT_SHIFT_MID_127TO96_8197F) +#define BIT_MID_127TO96_8197F(x) \ + (((x) & BIT_MASK_MID_127TO96_8197F) << BIT_SHIFT_MID_127TO96_8197F) +#define BITS_MID_127TO96_8197F \ + (BIT_MASK_MID_127TO96_8197F << BIT_SHIFT_MID_127TO96_8197F) #define BIT_CLEAR_MID_127TO96_8197F(x) ((x) & (~BITS_MID_127TO96_8197F)) -#define BIT_GET_MID_127TO96_8197F(x) (((x) >> BIT_SHIFT_MID_127TO96_8197F) & BIT_MASK_MID_127TO96_8197F) -#define BIT_SET_MID_127TO96_8197F(x, v) (BIT_CLEAR_MID_127TO96_8197F(x) | BIT_MID_127TO96_8197F(v)) - +#define BIT_GET_MID_127TO96_8197F(x) \ + (((x) >> BIT_SHIFT_MID_127TO96_8197F) & BIT_MASK_MID_127TO96_8197F) +#define BIT_SET_MID_127TO96_8197F(x, v) \ + (BIT_CLEAR_MID_127TO96_8197F(x) | BIT_MID_127TO96_8197F(v)) /* 2 REG_POWSEQ_8197F */ #define BIT_SHIFT_SEQNUM_MID_8197F 16 #define BIT_MASK_SEQNUM_MID_8197F 0xffff -#define BIT_SEQNUM_MID_8197F(x) (((x) & BIT_MASK_SEQNUM_MID_8197F) << BIT_SHIFT_SEQNUM_MID_8197F) -#define BITS_SEQNUM_MID_8197F (BIT_MASK_SEQNUM_MID_8197F << BIT_SHIFT_SEQNUM_MID_8197F) +#define BIT_SEQNUM_MID_8197F(x) \ + (((x) & BIT_MASK_SEQNUM_MID_8197F) << BIT_SHIFT_SEQNUM_MID_8197F) +#define BITS_SEQNUM_MID_8197F \ + (BIT_MASK_SEQNUM_MID_8197F << BIT_SHIFT_SEQNUM_MID_8197F) #define BIT_CLEAR_SEQNUM_MID_8197F(x) ((x) & (~BITS_SEQNUM_MID_8197F)) -#define BIT_GET_SEQNUM_MID_8197F(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8197F) & BIT_MASK_SEQNUM_MID_8197F) -#define BIT_SET_SEQNUM_MID_8197F(x, v) (BIT_CLEAR_SEQNUM_MID_8197F(x) | BIT_SEQNUM_MID_8197F(v)) - +#define BIT_GET_SEQNUM_MID_8197F(x) \ + (((x) >> BIT_SHIFT_SEQNUM_MID_8197F) & BIT_MASK_SEQNUM_MID_8197F) +#define BIT_SET_SEQNUM_MID_8197F(x, v) \ + (BIT_CLEAR_SEQNUM_MID_8197F(x) | BIT_SEQNUM_MID_8197F(v)) #define BIT_SHIFT_REF_MID_8197F 0 #define BIT_MASK_REF_MID_8197F 0x7f -#define BIT_REF_MID_8197F(x) (((x) & BIT_MASK_REF_MID_8197F) << BIT_SHIFT_REF_MID_8197F) +#define BIT_REF_MID_8197F(x) \ + (((x) & BIT_MASK_REF_MID_8197F) << BIT_SHIFT_REF_MID_8197F) #define BITS_REF_MID_8197F (BIT_MASK_REF_MID_8197F << BIT_SHIFT_REF_MID_8197F) #define BIT_CLEAR_REF_MID_8197F(x) ((x) & (~BITS_REF_MID_8197F)) -#define BIT_GET_REF_MID_8197F(x) (((x) >> BIT_SHIFT_REF_MID_8197F) & BIT_MASK_REF_MID_8197F) -#define BIT_SET_REF_MID_8197F(x, v) (BIT_CLEAR_REF_MID_8197F(x) | BIT_REF_MID_8197F(v)) - +#define BIT_GET_REF_MID_8197F(x) \ + (((x) >> BIT_SHIFT_REF_MID_8197F) & BIT_MASK_REF_MID_8197F) +#define BIT_SET_REF_MID_8197F(x, v) \ + (BIT_CLEAR_REF_MID_8197F(x) | BIT_REF_MID_8197F(v)) /* 2 REG_TC7_CTRL_V1_8197F */ #define BIT_TC7INT_EN_8197F BIT(26) @@ -3632,12 +4490,14 @@ #define BIT_SHIFT_TC7DATA_8197F 0 #define BIT_MASK_TC7DATA_8197F 0xffffff -#define BIT_TC7DATA_8197F(x) (((x) & BIT_MASK_TC7DATA_8197F) << BIT_SHIFT_TC7DATA_8197F) +#define BIT_TC7DATA_8197F(x) \ + (((x) & BIT_MASK_TC7DATA_8197F) << BIT_SHIFT_TC7DATA_8197F) #define BITS_TC7DATA_8197F (BIT_MASK_TC7DATA_8197F << BIT_SHIFT_TC7DATA_8197F) #define BIT_CLEAR_TC7DATA_8197F(x) ((x) & (~BITS_TC7DATA_8197F)) -#define BIT_GET_TC7DATA_8197F(x) (((x) >> BIT_SHIFT_TC7DATA_8197F) & BIT_MASK_TC7DATA_8197F) -#define BIT_SET_TC7DATA_8197F(x, v) (BIT_CLEAR_TC7DATA_8197F(x) | BIT_TC7DATA_8197F(v)) - +#define BIT_GET_TC7DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC7DATA_8197F) & BIT_MASK_TC7DATA_8197F) +#define BIT_SET_TC7DATA_8197F(x, v) \ + (BIT_CLEAR_TC7DATA_8197F(x) | BIT_TC7DATA_8197F(v)) /* 2 REG_TC8_CTRL_V1_8197F */ #define BIT_TC8INT_EN_8197F BIT(26) @@ -3646,12 +4506,14 @@ #define BIT_SHIFT_TC8DATA_8197F 0 #define BIT_MASK_TC8DATA_8197F 0xffffff -#define BIT_TC8DATA_8197F(x) (((x) & BIT_MASK_TC8DATA_8197F) << BIT_SHIFT_TC8DATA_8197F) +#define BIT_TC8DATA_8197F(x) \ + (((x) & BIT_MASK_TC8DATA_8197F) << BIT_SHIFT_TC8DATA_8197F) #define BITS_TC8DATA_8197F (BIT_MASK_TC8DATA_8197F << BIT_SHIFT_TC8DATA_8197F) #define BIT_CLEAR_TC8DATA_8197F(x) ((x) & (~BITS_TC8DATA_8197F)) -#define BIT_GET_TC8DATA_8197F(x) (((x) >> BIT_SHIFT_TC8DATA_8197F) & BIT_MASK_TC8DATA_8197F) -#define BIT_SET_TC8DATA_8197F(x, v) (BIT_CLEAR_TC8DATA_8197F(x) | BIT_TC8DATA_8197F(v)) - +#define BIT_GET_TC8DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC8DATA_8197F) & BIT_MASK_TC8DATA_8197F) +#define BIT_SET_TC8DATA_8197F(x, v) \ + (BIT_CLEAR_TC8DATA_8197F(x) | BIT_TC8DATA_8197F(v)) /* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F */ @@ -3661,22 +4523,32 @@ #define BIT_SHIFT_PCIE_PRIORITY_SEL_8197F 0 #define BIT_MASK_PCIE_PRIORITY_SEL_8197F 0x3 -#define BIT_PCIE_PRIORITY_SEL_8197F(x) (((x) & BIT_MASK_PCIE_PRIORITY_SEL_8197F) << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) -#define BITS_PCIE_PRIORITY_SEL_8197F (BIT_MASK_PCIE_PRIORITY_SEL_8197F << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) -#define BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) ((x) & (~BITS_PCIE_PRIORITY_SEL_8197F)) -#define BIT_GET_PCIE_PRIORITY_SEL_8197F(x) (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) & BIT_MASK_PCIE_PRIORITY_SEL_8197F) -#define BIT_SET_PCIE_PRIORITY_SEL_8197F(x, v) (BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) | BIT_PCIE_PRIORITY_SEL_8197F(v)) - +#define BIT_PCIE_PRIORITY_SEL_8197F(x) \ + (((x) & BIT_MASK_PCIE_PRIORITY_SEL_8197F) \ + << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) +#define BITS_PCIE_PRIORITY_SEL_8197F \ + (BIT_MASK_PCIE_PRIORITY_SEL_8197F << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) +#define BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) \ + ((x) & (~BITS_PCIE_PRIORITY_SEL_8197F)) +#define BIT_GET_PCIE_PRIORITY_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) & \ + BIT_MASK_PCIE_PRIORITY_SEL_8197F) +#define BIT_SET_PCIE_PRIORITY_SEL_8197F(x, v) \ + (BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) | BIT_PCIE_PRIORITY_SEL_8197F(v)) /* 2 REG_COUNTER_CONTROL_8197F */ #define BIT_SHIFT_COUNTER_BASE_8197F 16 #define BIT_MASK_COUNTER_BASE_8197F 0x1fff -#define BIT_COUNTER_BASE_8197F(x) (((x) & BIT_MASK_COUNTER_BASE_8197F) << BIT_SHIFT_COUNTER_BASE_8197F) -#define BITS_COUNTER_BASE_8197F (BIT_MASK_COUNTER_BASE_8197F << BIT_SHIFT_COUNTER_BASE_8197F) +#define BIT_COUNTER_BASE_8197F(x) \ + (((x) & BIT_MASK_COUNTER_BASE_8197F) << BIT_SHIFT_COUNTER_BASE_8197F) +#define BITS_COUNTER_BASE_8197F \ + (BIT_MASK_COUNTER_BASE_8197F << BIT_SHIFT_COUNTER_BASE_8197F) #define BIT_CLEAR_COUNTER_BASE_8197F(x) ((x) & (~BITS_COUNTER_BASE_8197F)) -#define BIT_GET_COUNTER_BASE_8197F(x) (((x) >> BIT_SHIFT_COUNTER_BASE_8197F) & BIT_MASK_COUNTER_BASE_8197F) -#define BIT_SET_COUNTER_BASE_8197F(x, v) (BIT_CLEAR_COUNTER_BASE_8197F(x) | BIT_COUNTER_BASE_8197F(v)) +#define BIT_GET_COUNTER_BASE_8197F(x) \ + (((x) >> BIT_SHIFT_COUNTER_BASE_8197F) & BIT_MASK_COUNTER_BASE_8197F) +#define BIT_SET_COUNTER_BASE_8197F(x, v) \ + (BIT_CLEAR_COUNTER_BASE_8197F(x) | BIT_COUNTER_BASE_8197F(v)) #define BIT_EN_RTS_REQ_8197F BIT(9) #define BIT_EN_EDCA_REQ_8197F BIT(8) @@ -3694,39 +4566,51 @@ #define BIT_SHIFT_CNT_MACID_8197F 24 #define BIT_MASK_CNT_MACID_8197F 0x7f -#define BIT_CNT_MACID_8197F(x) (((x) & BIT_MASK_CNT_MACID_8197F) << BIT_SHIFT_CNT_MACID_8197F) -#define BITS_CNT_MACID_8197F (BIT_MASK_CNT_MACID_8197F << BIT_SHIFT_CNT_MACID_8197F) +#define BIT_CNT_MACID_8197F(x) \ + (((x) & BIT_MASK_CNT_MACID_8197F) << BIT_SHIFT_CNT_MACID_8197F) +#define BITS_CNT_MACID_8197F \ + (BIT_MASK_CNT_MACID_8197F << BIT_SHIFT_CNT_MACID_8197F) #define BIT_CLEAR_CNT_MACID_8197F(x) ((x) & (~BITS_CNT_MACID_8197F)) -#define BIT_GET_CNT_MACID_8197F(x) (((x) >> BIT_SHIFT_CNT_MACID_8197F) & BIT_MASK_CNT_MACID_8197F) -#define BIT_SET_CNT_MACID_8197F(x, v) (BIT_CLEAR_CNT_MACID_8197F(x) | BIT_CNT_MACID_8197F(v)) - +#define BIT_GET_CNT_MACID_8197F(x) \ + (((x) >> BIT_SHIFT_CNT_MACID_8197F) & BIT_MASK_CNT_MACID_8197F) +#define BIT_SET_CNT_MACID_8197F(x, v) \ + (BIT_CLEAR_CNT_MACID_8197F(x) | BIT_CNT_MACID_8197F(v)) #define BIT_SHIFT_AGG_VALUE2_8197F 16 #define BIT_MASK_AGG_VALUE2_8197F 0x7f -#define BIT_AGG_VALUE2_8197F(x) (((x) & BIT_MASK_AGG_VALUE2_8197F) << BIT_SHIFT_AGG_VALUE2_8197F) -#define BITS_AGG_VALUE2_8197F (BIT_MASK_AGG_VALUE2_8197F << BIT_SHIFT_AGG_VALUE2_8197F) +#define BIT_AGG_VALUE2_8197F(x) \ + (((x) & BIT_MASK_AGG_VALUE2_8197F) << BIT_SHIFT_AGG_VALUE2_8197F) +#define BITS_AGG_VALUE2_8197F \ + (BIT_MASK_AGG_VALUE2_8197F << BIT_SHIFT_AGG_VALUE2_8197F) #define BIT_CLEAR_AGG_VALUE2_8197F(x) ((x) & (~BITS_AGG_VALUE2_8197F)) -#define BIT_GET_AGG_VALUE2_8197F(x) (((x) >> BIT_SHIFT_AGG_VALUE2_8197F) & BIT_MASK_AGG_VALUE2_8197F) -#define BIT_SET_AGG_VALUE2_8197F(x, v) (BIT_CLEAR_AGG_VALUE2_8197F(x) | BIT_AGG_VALUE2_8197F(v)) - +#define BIT_GET_AGG_VALUE2_8197F(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE2_8197F) & BIT_MASK_AGG_VALUE2_8197F) +#define BIT_SET_AGG_VALUE2_8197F(x, v) \ + (BIT_CLEAR_AGG_VALUE2_8197F(x) | BIT_AGG_VALUE2_8197F(v)) #define BIT_SHIFT_AGG_VALUE1_8197F 8 #define BIT_MASK_AGG_VALUE1_8197F 0x7f -#define BIT_AGG_VALUE1_8197F(x) (((x) & BIT_MASK_AGG_VALUE1_8197F) << BIT_SHIFT_AGG_VALUE1_8197F) -#define BITS_AGG_VALUE1_8197F (BIT_MASK_AGG_VALUE1_8197F << BIT_SHIFT_AGG_VALUE1_8197F) +#define BIT_AGG_VALUE1_8197F(x) \ + (((x) & BIT_MASK_AGG_VALUE1_8197F) << BIT_SHIFT_AGG_VALUE1_8197F) +#define BITS_AGG_VALUE1_8197F \ + (BIT_MASK_AGG_VALUE1_8197F << BIT_SHIFT_AGG_VALUE1_8197F) #define BIT_CLEAR_AGG_VALUE1_8197F(x) ((x) & (~BITS_AGG_VALUE1_8197F)) -#define BIT_GET_AGG_VALUE1_8197F(x) (((x) >> BIT_SHIFT_AGG_VALUE1_8197F) & BIT_MASK_AGG_VALUE1_8197F) -#define BIT_SET_AGG_VALUE1_8197F(x, v) (BIT_CLEAR_AGG_VALUE1_8197F(x) | BIT_AGG_VALUE1_8197F(v)) - +#define BIT_GET_AGG_VALUE1_8197F(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE1_8197F) & BIT_MASK_AGG_VALUE1_8197F) +#define BIT_SET_AGG_VALUE1_8197F(x, v) \ + (BIT_CLEAR_AGG_VALUE1_8197F(x) | BIT_AGG_VALUE1_8197F(v)) #define BIT_SHIFT_AGG_VALUE0_8197F 0 #define BIT_MASK_AGG_VALUE0_8197F 0x7f -#define BIT_AGG_VALUE0_8197F(x) (((x) & BIT_MASK_AGG_VALUE0_8197F) << BIT_SHIFT_AGG_VALUE0_8197F) -#define BITS_AGG_VALUE0_8197F (BIT_MASK_AGG_VALUE0_8197F << BIT_SHIFT_AGG_VALUE0_8197F) +#define BIT_AGG_VALUE0_8197F(x) \ + (((x) & BIT_MASK_AGG_VALUE0_8197F) << BIT_SHIFT_AGG_VALUE0_8197F) +#define BITS_AGG_VALUE0_8197F \ + (BIT_MASK_AGG_VALUE0_8197F << BIT_SHIFT_AGG_VALUE0_8197F) #define BIT_CLEAR_AGG_VALUE0_8197F(x) ((x) & (~BITS_AGG_VALUE0_8197F)) -#define BIT_GET_AGG_VALUE0_8197F(x) (((x) >> BIT_SHIFT_AGG_VALUE0_8197F) & BIT_MASK_AGG_VALUE0_8197F) -#define BIT_SET_AGG_VALUE0_8197F(x, v) (BIT_CLEAR_AGG_VALUE0_8197F(x) | BIT_AGG_VALUE0_8197F(v)) - +#define BIT_GET_AGG_VALUE0_8197F(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE0_8197F) & BIT_MASK_AGG_VALUE0_8197F) +#define BIT_SET_AGG_VALUE0_8197F(x, v) \ + (BIT_CLEAR_AGG_VALUE0_8197F(x) | BIT_AGG_VALUE0_8197F(v)) /* 2 REG_COUNTER_SET_8197F */ #define BIT_RTS_RST_8197F BIT(24) @@ -3763,61 +4647,89 @@ #define BIT_SHIFT_TXDMA_LEN_TH0_8197F 16 #define BIT_MASK_TXDMA_LEN_TH0_8197F 0xffff -#define BIT_TXDMA_LEN_TH0_8197F(x) (((x) & BIT_MASK_TXDMA_LEN_TH0_8197F) << BIT_SHIFT_TXDMA_LEN_TH0_8197F) -#define BITS_TXDMA_LEN_TH0_8197F (BIT_MASK_TXDMA_LEN_TH0_8197F << BIT_SHIFT_TXDMA_LEN_TH0_8197F) +#define BIT_TXDMA_LEN_TH0_8197F(x) \ + (((x) & BIT_MASK_TXDMA_LEN_TH0_8197F) << BIT_SHIFT_TXDMA_LEN_TH0_8197F) +#define BITS_TXDMA_LEN_TH0_8197F \ + (BIT_MASK_TXDMA_LEN_TH0_8197F << BIT_SHIFT_TXDMA_LEN_TH0_8197F) #define BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) ((x) & (~BITS_TXDMA_LEN_TH0_8197F)) -#define BIT_GET_TXDMA_LEN_TH0_8197F(x) (((x) >> BIT_SHIFT_TXDMA_LEN_TH0_8197F) & BIT_MASK_TXDMA_LEN_TH0_8197F) -#define BIT_SET_TXDMA_LEN_TH0_8197F(x, v) (BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) | BIT_TXDMA_LEN_TH0_8197F(v)) - +#define BIT_GET_TXDMA_LEN_TH0_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_LEN_TH0_8197F) & BIT_MASK_TXDMA_LEN_TH0_8197F) +#define BIT_SET_TXDMA_LEN_TH0_8197F(x, v) \ + (BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) | BIT_TXDMA_LEN_TH0_8197F(v)) #define BIT_SHIFT_TXDMA_LEN_TH1_8197F 0 #define BIT_MASK_TXDMA_LEN_TH1_8197F 0xffff -#define BIT_TXDMA_LEN_TH1_8197F(x) (((x) & BIT_MASK_TXDMA_LEN_TH1_8197F) << BIT_SHIFT_TXDMA_LEN_TH1_8197F) -#define BITS_TXDMA_LEN_TH1_8197F (BIT_MASK_TXDMA_LEN_TH1_8197F << BIT_SHIFT_TXDMA_LEN_TH1_8197F) +#define BIT_TXDMA_LEN_TH1_8197F(x) \ + (((x) & BIT_MASK_TXDMA_LEN_TH1_8197F) << BIT_SHIFT_TXDMA_LEN_TH1_8197F) +#define BITS_TXDMA_LEN_TH1_8197F \ + (BIT_MASK_TXDMA_LEN_TH1_8197F << BIT_SHIFT_TXDMA_LEN_TH1_8197F) #define BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) ((x) & (~BITS_TXDMA_LEN_TH1_8197F)) -#define BIT_GET_TXDMA_LEN_TH1_8197F(x) (((x) >> BIT_SHIFT_TXDMA_LEN_TH1_8197F) & BIT_MASK_TXDMA_LEN_TH1_8197F) -#define BIT_SET_TXDMA_LEN_TH1_8197F(x, v) (BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) | BIT_TXDMA_LEN_TH1_8197F(v)) - +#define BIT_GET_TXDMA_LEN_TH1_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_LEN_TH1_8197F) & BIT_MASK_TXDMA_LEN_TH1_8197F) +#define BIT_SET_TXDMA_LEN_TH1_8197F(x, v) \ + (BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) | BIT_TXDMA_LEN_TH1_8197F(v)) /* 2 REG_RDE_LEN_TH_8197F */ #define BIT_SHIFT_RXDMA_LEN_TH0_8197F 16 #define BIT_MASK_RXDMA_LEN_TH0_8197F 0xffff -#define BIT_RXDMA_LEN_TH0_8197F(x) (((x) & BIT_MASK_RXDMA_LEN_TH0_8197F) << BIT_SHIFT_RXDMA_LEN_TH0_8197F) -#define BITS_RXDMA_LEN_TH0_8197F (BIT_MASK_RXDMA_LEN_TH0_8197F << BIT_SHIFT_RXDMA_LEN_TH0_8197F) +#define BIT_RXDMA_LEN_TH0_8197F(x) \ + (((x) & BIT_MASK_RXDMA_LEN_TH0_8197F) << BIT_SHIFT_RXDMA_LEN_TH0_8197F) +#define BITS_RXDMA_LEN_TH0_8197F \ + (BIT_MASK_RXDMA_LEN_TH0_8197F << BIT_SHIFT_RXDMA_LEN_TH0_8197F) #define BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) ((x) & (~BITS_RXDMA_LEN_TH0_8197F)) -#define BIT_GET_RXDMA_LEN_TH0_8197F(x) (((x) >> BIT_SHIFT_RXDMA_LEN_TH0_8197F) & BIT_MASK_RXDMA_LEN_TH0_8197F) -#define BIT_SET_RXDMA_LEN_TH0_8197F(x, v) (BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) | BIT_RXDMA_LEN_TH0_8197F(v)) - +#define BIT_GET_RXDMA_LEN_TH0_8197F(x) \ + (((x) >> BIT_SHIFT_RXDMA_LEN_TH0_8197F) & BIT_MASK_RXDMA_LEN_TH0_8197F) +#define BIT_SET_RXDMA_LEN_TH0_8197F(x, v) \ + (BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) | BIT_RXDMA_LEN_TH0_8197F(v)) #define BIT_SHIFT_RXDMA_LEN_TH1_8197F 0 #define BIT_MASK_RXDMA_LEN_TH1_8197F 0xffff -#define BIT_RXDMA_LEN_TH1_8197F(x) (((x) & BIT_MASK_RXDMA_LEN_TH1_8197F) << BIT_SHIFT_RXDMA_LEN_TH1_8197F) -#define BITS_RXDMA_LEN_TH1_8197F (BIT_MASK_RXDMA_LEN_TH1_8197F << BIT_SHIFT_RXDMA_LEN_TH1_8197F) +#define BIT_RXDMA_LEN_TH1_8197F(x) \ + (((x) & BIT_MASK_RXDMA_LEN_TH1_8197F) << BIT_SHIFT_RXDMA_LEN_TH1_8197F) +#define BITS_RXDMA_LEN_TH1_8197F \ + (BIT_MASK_RXDMA_LEN_TH1_8197F << BIT_SHIFT_RXDMA_LEN_TH1_8197F) #define BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) ((x) & (~BITS_RXDMA_LEN_TH1_8197F)) -#define BIT_GET_RXDMA_LEN_TH1_8197F(x) (((x) >> BIT_SHIFT_RXDMA_LEN_TH1_8197F) & BIT_MASK_RXDMA_LEN_TH1_8197F) -#define BIT_SET_RXDMA_LEN_TH1_8197F(x, v) (BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) | BIT_RXDMA_LEN_TH1_8197F(v)) - +#define BIT_GET_RXDMA_LEN_TH1_8197F(x) \ + (((x) >> BIT_SHIFT_RXDMA_LEN_TH1_8197F) & BIT_MASK_RXDMA_LEN_TH1_8197F) +#define BIT_SET_RXDMA_LEN_TH1_8197F(x, v) \ + (BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) | BIT_RXDMA_LEN_TH1_8197F(v)) /* 2 REG_PCIE_EXEC_TIME_8197F */ #define BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F 16 #define BIT_MASK_COUNTER_INTERVAL_SEL_8197F 0x3 -#define BIT_COUNTER_INTERVAL_SEL_8197F(x) (((x) & BIT_MASK_COUNTER_INTERVAL_SEL_8197F) << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) -#define BITS_COUNTER_INTERVAL_SEL_8197F (BIT_MASK_COUNTER_INTERVAL_SEL_8197F << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) -#define BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) ((x) & (~BITS_COUNTER_INTERVAL_SEL_8197F)) -#define BIT_GET_COUNTER_INTERVAL_SEL_8197F(x) (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) & BIT_MASK_COUNTER_INTERVAL_SEL_8197F) -#define BIT_SET_COUNTER_INTERVAL_SEL_8197F(x, v) (BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) | BIT_COUNTER_INTERVAL_SEL_8197F(v)) - +#define BIT_COUNTER_INTERVAL_SEL_8197F(x) \ + (((x) & BIT_MASK_COUNTER_INTERVAL_SEL_8197F) \ + << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) +#define BITS_COUNTER_INTERVAL_SEL_8197F \ + (BIT_MASK_COUNTER_INTERVAL_SEL_8197F \ + << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) +#define BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) \ + ((x) & (~BITS_COUNTER_INTERVAL_SEL_8197F)) +#define BIT_GET_COUNTER_INTERVAL_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) & \ + BIT_MASK_COUNTER_INTERVAL_SEL_8197F) +#define BIT_SET_COUNTER_INTERVAL_SEL_8197F(x, v) \ + (BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) | \ + BIT_COUNTER_INTERVAL_SEL_8197F(v)) #define BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F 0 #define BIT_MASK_PCIE_TRANS_DATA_TH1_8197F 0xffff -#define BIT_PCIE_TRANS_DATA_TH1_8197F(x) (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1_8197F) << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) -#define BITS_PCIE_TRANS_DATA_TH1_8197F (BIT_MASK_PCIE_TRANS_DATA_TH1_8197F << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) -#define BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) ((x) & (~BITS_PCIE_TRANS_DATA_TH1_8197F)) -#define BIT_GET_PCIE_TRANS_DATA_TH1_8197F(x) (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) & BIT_MASK_PCIE_TRANS_DATA_TH1_8197F) -#define BIT_SET_PCIE_TRANS_DATA_TH1_8197F(x, v) (BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) | BIT_PCIE_TRANS_DATA_TH1_8197F(v)) - +#define BIT_PCIE_TRANS_DATA_TH1_8197F(x) \ + (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1_8197F) \ + << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) +#define BITS_PCIE_TRANS_DATA_TH1_8197F \ + (BIT_MASK_PCIE_TRANS_DATA_TH1_8197F \ + << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) +#define BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) \ + ((x) & (~BITS_PCIE_TRANS_DATA_TH1_8197F)) +#define BIT_GET_PCIE_TRANS_DATA_TH1_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) & \ + BIT_MASK_PCIE_TRANS_DATA_TH1_8197F) +#define BIT_SET_PCIE_TRANS_DATA_TH1_8197F(x, v) \ + (BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) | \ + BIT_PCIE_TRANS_DATA_TH1_8197F(v)) /* 2 REG_FT2IMR_8197F */ #define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(31) @@ -3879,45 +4791,53 @@ #define BIT_SHIFT_FW_MSG2_8197F 0 #define BIT_MASK_FW_MSG2_8197F 0xffffffffL -#define BIT_FW_MSG2_8197F(x) (((x) & BIT_MASK_FW_MSG2_8197F) << BIT_SHIFT_FW_MSG2_8197F) +#define BIT_FW_MSG2_8197F(x) \ + (((x) & BIT_MASK_FW_MSG2_8197F) << BIT_SHIFT_FW_MSG2_8197F) #define BITS_FW_MSG2_8197F (BIT_MASK_FW_MSG2_8197F << BIT_SHIFT_FW_MSG2_8197F) #define BIT_CLEAR_FW_MSG2_8197F(x) ((x) & (~BITS_FW_MSG2_8197F)) -#define BIT_GET_FW_MSG2_8197F(x) (((x) >> BIT_SHIFT_FW_MSG2_8197F) & BIT_MASK_FW_MSG2_8197F) -#define BIT_SET_FW_MSG2_8197F(x, v) (BIT_CLEAR_FW_MSG2_8197F(x) | BIT_FW_MSG2_8197F(v)) - +#define BIT_GET_FW_MSG2_8197F(x) \ + (((x) >> BIT_SHIFT_FW_MSG2_8197F) & BIT_MASK_FW_MSG2_8197F) +#define BIT_SET_FW_MSG2_8197F(x, v) \ + (BIT_CLEAR_FW_MSG2_8197F(x) | BIT_FW_MSG2_8197F(v)) /* 2 REG_MSG3_8197F */ #define BIT_SHIFT_FW_MSG3_8197F 0 #define BIT_MASK_FW_MSG3_8197F 0xffffffffL -#define BIT_FW_MSG3_8197F(x) (((x) & BIT_MASK_FW_MSG3_8197F) << BIT_SHIFT_FW_MSG3_8197F) +#define BIT_FW_MSG3_8197F(x) \ + (((x) & BIT_MASK_FW_MSG3_8197F) << BIT_SHIFT_FW_MSG3_8197F) #define BITS_FW_MSG3_8197F (BIT_MASK_FW_MSG3_8197F << BIT_SHIFT_FW_MSG3_8197F) #define BIT_CLEAR_FW_MSG3_8197F(x) ((x) & (~BITS_FW_MSG3_8197F)) -#define BIT_GET_FW_MSG3_8197F(x) (((x) >> BIT_SHIFT_FW_MSG3_8197F) & BIT_MASK_FW_MSG3_8197F) -#define BIT_SET_FW_MSG3_8197F(x, v) (BIT_CLEAR_FW_MSG3_8197F(x) | BIT_FW_MSG3_8197F(v)) - +#define BIT_GET_FW_MSG3_8197F(x) \ + (((x) >> BIT_SHIFT_FW_MSG3_8197F) & BIT_MASK_FW_MSG3_8197F) +#define BIT_SET_FW_MSG3_8197F(x, v) \ + (BIT_CLEAR_FW_MSG3_8197F(x) | BIT_FW_MSG3_8197F(v)) /* 2 REG_MSG4_8197F */ #define BIT_SHIFT_FW_MSG4_8197F 0 #define BIT_MASK_FW_MSG4_8197F 0xffffffffL -#define BIT_FW_MSG4_8197F(x) (((x) & BIT_MASK_FW_MSG4_8197F) << BIT_SHIFT_FW_MSG4_8197F) +#define BIT_FW_MSG4_8197F(x) \ + (((x) & BIT_MASK_FW_MSG4_8197F) << BIT_SHIFT_FW_MSG4_8197F) #define BITS_FW_MSG4_8197F (BIT_MASK_FW_MSG4_8197F << BIT_SHIFT_FW_MSG4_8197F) #define BIT_CLEAR_FW_MSG4_8197F(x) ((x) & (~BITS_FW_MSG4_8197F)) -#define BIT_GET_FW_MSG4_8197F(x) (((x) >> BIT_SHIFT_FW_MSG4_8197F) & BIT_MASK_FW_MSG4_8197F) -#define BIT_SET_FW_MSG4_8197F(x, v) (BIT_CLEAR_FW_MSG4_8197F(x) | BIT_FW_MSG4_8197F(v)) - +#define BIT_GET_FW_MSG4_8197F(x) \ + (((x) >> BIT_SHIFT_FW_MSG4_8197F) & BIT_MASK_FW_MSG4_8197F) +#define BIT_SET_FW_MSG4_8197F(x, v) \ + (BIT_CLEAR_FW_MSG4_8197F(x) | BIT_FW_MSG4_8197F(v)) /* 2 REG_MSG5_8197F */ #define BIT_SHIFT_FW_MSG5_8197F 0 #define BIT_MASK_FW_MSG5_8197F 0xffffffffL -#define BIT_FW_MSG5_8197F(x) (((x) & BIT_MASK_FW_MSG5_8197F) << BIT_SHIFT_FW_MSG5_8197F) +#define BIT_FW_MSG5_8197F(x) \ + (((x) & BIT_MASK_FW_MSG5_8197F) << BIT_SHIFT_FW_MSG5_8197F) #define BITS_FW_MSG5_8197F (BIT_MASK_FW_MSG5_8197F << BIT_SHIFT_FW_MSG5_8197F) #define BIT_CLEAR_FW_MSG5_8197F(x) ((x) & (~BITS_FW_MSG5_8197F)) -#define BIT_GET_FW_MSG5_8197F(x) (((x) >> BIT_SHIFT_FW_MSG5_8197F) & BIT_MASK_FW_MSG5_8197F) -#define BIT_SET_FW_MSG5_8197F(x, v) (BIT_CLEAR_FW_MSG5_8197F(x) | BIT_FW_MSG5_8197F(v)) - +#define BIT_GET_FW_MSG5_8197F(x) \ + (((x) >> BIT_SHIFT_FW_MSG5_8197F) & BIT_MASK_FW_MSG5_8197F) +#define BIT_SET_FW_MSG5_8197F(x, v) \ + (BIT_CLEAR_FW_MSG5_8197F(x) | BIT_FW_MSG5_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -3925,71 +4845,112 @@ #define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F 16 #define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F 0xff -#define BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) -#define BITS_TX_OQT_HE_FREE_SPACE_V1_8197F (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) -#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8197F)) -#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8197F(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F) -#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8197F(x, v) (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) | BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(v)) - +#define BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(x) \ + (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F) \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) +#define BITS_TX_OQT_HE_FREE_SPACE_V1_8197F \ + (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) \ + ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8197F)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) & \ + BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F) +#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8197F(x, v) \ + (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) | \ + BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(v)) #define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F 0 #define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F 0xff -#define BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) -#define BITS_TX_OQT_NL_FREE_SPACE_V1_8197F (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) -#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8197F)) -#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8197F(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F) -#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8197F(x, v) (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) | BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(v)) - +#define BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(x) \ + (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F) \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) +#define BITS_TX_OQT_NL_FREE_SPACE_V1_8197F \ + (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) \ + ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8197F)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) & \ + BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F) +#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8197F(x, v) \ + (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) | \ + BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(v)) /* 2 REG_FIFOPAGE_CTRL_2_8197F */ #define BIT_BCN_VALID_1_V1_8197F BIT(31) #define BIT_SHIFT_BCN_HEAD_1_V1_8197F 16 #define BIT_MASK_BCN_HEAD_1_V1_8197F 0xfff -#define BIT_BCN_HEAD_1_V1_8197F(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8197F) << BIT_SHIFT_BCN_HEAD_1_V1_8197F) -#define BITS_BCN_HEAD_1_V1_8197F (BIT_MASK_BCN_HEAD_1_V1_8197F << BIT_SHIFT_BCN_HEAD_1_V1_8197F) +#define BIT_BCN_HEAD_1_V1_8197F(x) \ + (((x) & BIT_MASK_BCN_HEAD_1_V1_8197F) << BIT_SHIFT_BCN_HEAD_1_V1_8197F) +#define BITS_BCN_HEAD_1_V1_8197F \ + (BIT_MASK_BCN_HEAD_1_V1_8197F << BIT_SHIFT_BCN_HEAD_1_V1_8197F) #define BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) ((x) & (~BITS_BCN_HEAD_1_V1_8197F)) -#define BIT_GET_BCN_HEAD_1_V1_8197F(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8197F) & BIT_MASK_BCN_HEAD_1_V1_8197F) -#define BIT_SET_BCN_HEAD_1_V1_8197F(x, v) (BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) | BIT_BCN_HEAD_1_V1_8197F(v)) +#define BIT_GET_BCN_HEAD_1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8197F) & BIT_MASK_BCN_HEAD_1_V1_8197F) +#define BIT_SET_BCN_HEAD_1_V1_8197F(x, v) \ + (BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) | BIT_BCN_HEAD_1_V1_8197F(v)) #define BIT_BCN_VALID_V1_8197F BIT(15) #define BIT_SHIFT_BCN_HEAD_V1_8197F 0 #define BIT_MASK_BCN_HEAD_V1_8197F 0xfff -#define BIT_BCN_HEAD_V1_8197F(x) (((x) & BIT_MASK_BCN_HEAD_V1_8197F) << BIT_SHIFT_BCN_HEAD_V1_8197F) -#define BITS_BCN_HEAD_V1_8197F (BIT_MASK_BCN_HEAD_V1_8197F << BIT_SHIFT_BCN_HEAD_V1_8197F) +#define BIT_BCN_HEAD_V1_8197F(x) \ + (((x) & BIT_MASK_BCN_HEAD_V1_8197F) << BIT_SHIFT_BCN_HEAD_V1_8197F) +#define BITS_BCN_HEAD_V1_8197F \ + (BIT_MASK_BCN_HEAD_V1_8197F << BIT_SHIFT_BCN_HEAD_V1_8197F) #define BIT_CLEAR_BCN_HEAD_V1_8197F(x) ((x) & (~BITS_BCN_HEAD_V1_8197F)) -#define BIT_GET_BCN_HEAD_V1_8197F(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8197F) & BIT_MASK_BCN_HEAD_V1_8197F) -#define BIT_SET_BCN_HEAD_V1_8197F(x, v) (BIT_CLEAR_BCN_HEAD_V1_8197F(x) | BIT_BCN_HEAD_V1_8197F(v)) - +#define BIT_GET_BCN_HEAD_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_V1_8197F) & BIT_MASK_BCN_HEAD_V1_8197F) +#define BIT_SET_BCN_HEAD_V1_8197F(x, v) \ + (BIT_CLEAR_BCN_HEAD_V1_8197F(x) | BIT_BCN_HEAD_V1_8197F(v)) /* 2 REG_AUTO_LLT_V1_8197F */ #define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F 24 #define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F 0xff -#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) -#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) -#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)) -#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) -#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x, v) (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) | BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(v)) - +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) +#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F \ + (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) +#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) \ + ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) & \ + BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) +#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) | \ + BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(v)) #define BIT_SHIFT_LLT_FREE_PAGE_V1_8197F 8 #define BIT_MASK_LLT_FREE_PAGE_V1_8197F 0xffff -#define BIT_LLT_FREE_PAGE_V1_8197F(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8197F) << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) -#define BITS_LLT_FREE_PAGE_V1_8197F (BIT_MASK_LLT_FREE_PAGE_V1_8197F << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) -#define BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) ((x) & (~BITS_LLT_FREE_PAGE_V1_8197F)) -#define BIT_GET_LLT_FREE_PAGE_V1_8197F(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) & BIT_MASK_LLT_FREE_PAGE_V1_8197F) -#define BIT_SET_LLT_FREE_PAGE_V1_8197F(x, v) (BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) | BIT_LLT_FREE_PAGE_V1_8197F(v)) - +#define BIT_LLT_FREE_PAGE_V1_8197F(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8197F) \ + << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) +#define BITS_LLT_FREE_PAGE_V1_8197F \ + (BIT_MASK_LLT_FREE_PAGE_V1_8197F << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) +#define BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) \ + ((x) & (~BITS_LLT_FREE_PAGE_V1_8197F)) +#define BIT_GET_LLT_FREE_PAGE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) & \ + BIT_MASK_LLT_FREE_PAGE_V1_8197F) +#define BIT_SET_LLT_FREE_PAGE_V1_8197F(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) | BIT_LLT_FREE_PAGE_V1_8197F(v)) #define BIT_SHIFT_BLK_DESC_NUM_8197F 4 #define BIT_MASK_BLK_DESC_NUM_8197F 0xf -#define BIT_BLK_DESC_NUM_8197F(x) (((x) & BIT_MASK_BLK_DESC_NUM_8197F) << BIT_SHIFT_BLK_DESC_NUM_8197F) -#define BITS_BLK_DESC_NUM_8197F (BIT_MASK_BLK_DESC_NUM_8197F << BIT_SHIFT_BLK_DESC_NUM_8197F) +#define BIT_BLK_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_BLK_DESC_NUM_8197F) << BIT_SHIFT_BLK_DESC_NUM_8197F) +#define BITS_BLK_DESC_NUM_8197F \ + (BIT_MASK_BLK_DESC_NUM_8197F << BIT_SHIFT_BLK_DESC_NUM_8197F) #define BIT_CLEAR_BLK_DESC_NUM_8197F(x) ((x) & (~BITS_BLK_DESC_NUM_8197F)) -#define BIT_GET_BLK_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8197F) & BIT_MASK_BLK_DESC_NUM_8197F) -#define BIT_SET_BLK_DESC_NUM_8197F(x, v) (BIT_CLEAR_BLK_DESC_NUM_8197F(x) | BIT_BLK_DESC_NUM_8197F(v)) +#define BIT_GET_BLK_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_BLK_DESC_NUM_8197F) & BIT_MASK_BLK_DESC_NUM_8197F) +#define BIT_SET_BLK_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_BLK_DESC_NUM_8197F(x) | BIT_BLK_DESC_NUM_8197F(v)) #define BIT_R_BCN_HEAD_SEL_8197F BIT(3) #define BIT_R_EN_BCN_SW_HEAD_SEL_8197F BIT(2) @@ -4004,11 +4965,17 @@ #define BIT_SHIFT_PG_UNDER_TH_V1_8197F 16 #define BIT_MASK_PG_UNDER_TH_V1_8197F 0xfff -#define BIT_PG_UNDER_TH_V1_8197F(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8197F) << BIT_SHIFT_PG_UNDER_TH_V1_8197F) -#define BITS_PG_UNDER_TH_V1_8197F (BIT_MASK_PG_UNDER_TH_V1_8197F << BIT_SHIFT_PG_UNDER_TH_V1_8197F) +#define BIT_PG_UNDER_TH_V1_8197F(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V1_8197F) \ + << BIT_SHIFT_PG_UNDER_TH_V1_8197F) +#define BITS_PG_UNDER_TH_V1_8197F \ + (BIT_MASK_PG_UNDER_TH_V1_8197F << BIT_SHIFT_PG_UNDER_TH_V1_8197F) #define BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) ((x) & (~BITS_PG_UNDER_TH_V1_8197F)) -#define BIT_GET_PG_UNDER_TH_V1_8197F(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8197F) & BIT_MASK_PG_UNDER_TH_V1_8197F) -#define BIT_SET_PG_UNDER_TH_V1_8197F(x, v) (BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) | BIT_PG_UNDER_TH_V1_8197F(v)) +#define BIT_GET_PG_UNDER_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8197F) & \ + BIT_MASK_PG_UNDER_TH_V1_8197F) +#define BIT_SET_PG_UNDER_TH_V1_8197F(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) | BIT_PG_UNDER_TH_V1_8197F(v)) #define BIT_EN_RESET_RESTORE_H2C_8197F BIT(15) #define BIT_SDIO_TDE_FINISH_8197F BIT(14) @@ -4021,12 +4988,15 @@ #define BIT_SHIFT_CHECK_OFFSET_8197F 0 #define BIT_MASK_CHECK_OFFSET_8197F 0xff -#define BIT_CHECK_OFFSET_8197F(x) (((x) & BIT_MASK_CHECK_OFFSET_8197F) << BIT_SHIFT_CHECK_OFFSET_8197F) -#define BITS_CHECK_OFFSET_8197F (BIT_MASK_CHECK_OFFSET_8197F << BIT_SHIFT_CHECK_OFFSET_8197F) +#define BIT_CHECK_OFFSET_8197F(x) \ + (((x) & BIT_MASK_CHECK_OFFSET_8197F) << BIT_SHIFT_CHECK_OFFSET_8197F) +#define BITS_CHECK_OFFSET_8197F \ + (BIT_MASK_CHECK_OFFSET_8197F << BIT_SHIFT_CHECK_OFFSET_8197F) #define BIT_CLEAR_CHECK_OFFSET_8197F(x) ((x) & (~BITS_CHECK_OFFSET_8197F)) -#define BIT_GET_CHECK_OFFSET_8197F(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8197F) & BIT_MASK_CHECK_OFFSET_8197F) -#define BIT_SET_CHECK_OFFSET_8197F(x, v) (BIT_CLEAR_CHECK_OFFSET_8197F(x) | BIT_CHECK_OFFSET_8197F(v)) - +#define BIT_GET_CHECK_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_CHECK_OFFSET_8197F) & BIT_MASK_CHECK_OFFSET_8197F) +#define BIT_SET_CHECK_OFFSET_8197F(x, v) \ + (BIT_CLEAR_CHECK_OFFSET_8197F(x) | BIT_CHECK_OFFSET_8197F(v)) /* 2 REG_TXDMA_STATUS_8197F */ #define BIT_HI_OQT_UDN_8197F BIT(17) @@ -4054,101 +5024,139 @@ #define BIT_SHIFT_HPQ_HIGH_TH_V1_8197F 16 #define BIT_MASK_HPQ_HIGH_TH_V1_8197F 0xfff -#define BIT_HPQ_HIGH_TH_V1_8197F(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8197F) << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) -#define BITS_HPQ_HIGH_TH_V1_8197F (BIT_MASK_HPQ_HIGH_TH_V1_8197F << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) +#define BIT_HPQ_HIGH_TH_V1_8197F(x) \ + (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8197F) \ + << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) +#define BITS_HPQ_HIGH_TH_V1_8197F \ + (BIT_MASK_HPQ_HIGH_TH_V1_8197F << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) #define BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8197F)) -#define BIT_GET_HPQ_HIGH_TH_V1_8197F(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) & BIT_MASK_HPQ_HIGH_TH_V1_8197F) -#define BIT_SET_HPQ_HIGH_TH_V1_8197F(x, v) (BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) | BIT_HPQ_HIGH_TH_V1_8197F(v)) - +#define BIT_GET_HPQ_HIGH_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) & \ + BIT_MASK_HPQ_HIGH_TH_V1_8197F) +#define BIT_SET_HPQ_HIGH_TH_V1_8197F(x, v) \ + (BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) | BIT_HPQ_HIGH_TH_V1_8197F(v)) #define BIT_SHIFT_HPQ_LOW_TH_V1_8197F 0 #define BIT_MASK_HPQ_LOW_TH_V1_8197F 0xfff -#define BIT_HPQ_LOW_TH_V1_8197F(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8197F) << BIT_SHIFT_HPQ_LOW_TH_V1_8197F) -#define BITS_HPQ_LOW_TH_V1_8197F (BIT_MASK_HPQ_LOW_TH_V1_8197F << BIT_SHIFT_HPQ_LOW_TH_V1_8197F) +#define BIT_HPQ_LOW_TH_V1_8197F(x) \ + (((x) & BIT_MASK_HPQ_LOW_TH_V1_8197F) << BIT_SHIFT_HPQ_LOW_TH_V1_8197F) +#define BITS_HPQ_LOW_TH_V1_8197F \ + (BIT_MASK_HPQ_LOW_TH_V1_8197F << BIT_SHIFT_HPQ_LOW_TH_V1_8197F) #define BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8197F)) -#define BIT_GET_HPQ_LOW_TH_V1_8197F(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8197F) & BIT_MASK_HPQ_LOW_TH_V1_8197F) -#define BIT_SET_HPQ_LOW_TH_V1_8197F(x, v) (BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) | BIT_HPQ_LOW_TH_V1_8197F(v)) - +#define BIT_GET_HPQ_LOW_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8197F) & BIT_MASK_HPQ_LOW_TH_V1_8197F) +#define BIT_SET_HPQ_LOW_TH_V1_8197F(x, v) \ + (BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) | BIT_HPQ_LOW_TH_V1_8197F(v)) /* 2 REG_TQPNT2_8197F */ #define BIT_SHIFT_NPQ_HIGH_TH_V1_8197F 16 #define BIT_MASK_NPQ_HIGH_TH_V1_8197F 0xfff -#define BIT_NPQ_HIGH_TH_V1_8197F(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8197F) << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) -#define BITS_NPQ_HIGH_TH_V1_8197F (BIT_MASK_NPQ_HIGH_TH_V1_8197F << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) +#define BIT_NPQ_HIGH_TH_V1_8197F(x) \ + (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8197F) \ + << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) +#define BITS_NPQ_HIGH_TH_V1_8197F \ + (BIT_MASK_NPQ_HIGH_TH_V1_8197F << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) #define BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8197F)) -#define BIT_GET_NPQ_HIGH_TH_V1_8197F(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) & BIT_MASK_NPQ_HIGH_TH_V1_8197F) -#define BIT_SET_NPQ_HIGH_TH_V1_8197F(x, v) (BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) | BIT_NPQ_HIGH_TH_V1_8197F(v)) - +#define BIT_GET_NPQ_HIGH_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) & \ + BIT_MASK_NPQ_HIGH_TH_V1_8197F) +#define BIT_SET_NPQ_HIGH_TH_V1_8197F(x, v) \ + (BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) | BIT_NPQ_HIGH_TH_V1_8197F(v)) #define BIT_SHIFT_NPQ_LOW_TH_V1_8197F 0 #define BIT_MASK_NPQ_LOW_TH_V1_8197F 0xfff -#define BIT_NPQ_LOW_TH_V1_8197F(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8197F) << BIT_SHIFT_NPQ_LOW_TH_V1_8197F) -#define BITS_NPQ_LOW_TH_V1_8197F (BIT_MASK_NPQ_LOW_TH_V1_8197F << BIT_SHIFT_NPQ_LOW_TH_V1_8197F) +#define BIT_NPQ_LOW_TH_V1_8197F(x) \ + (((x) & BIT_MASK_NPQ_LOW_TH_V1_8197F) << BIT_SHIFT_NPQ_LOW_TH_V1_8197F) +#define BITS_NPQ_LOW_TH_V1_8197F \ + (BIT_MASK_NPQ_LOW_TH_V1_8197F << BIT_SHIFT_NPQ_LOW_TH_V1_8197F) #define BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8197F)) -#define BIT_GET_NPQ_LOW_TH_V1_8197F(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8197F) & BIT_MASK_NPQ_LOW_TH_V1_8197F) -#define BIT_SET_NPQ_LOW_TH_V1_8197F(x, v) (BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) | BIT_NPQ_LOW_TH_V1_8197F(v)) - +#define BIT_GET_NPQ_LOW_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8197F) & BIT_MASK_NPQ_LOW_TH_V1_8197F) +#define BIT_SET_NPQ_LOW_TH_V1_8197F(x, v) \ + (BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) | BIT_NPQ_LOW_TH_V1_8197F(v)) /* 2 REG_TQPNT3_8197F */ #define BIT_SHIFT_LPQ_HIGH_TH_V1_8197F 16 #define BIT_MASK_LPQ_HIGH_TH_V1_8197F 0xfff -#define BIT_LPQ_HIGH_TH_V1_8197F(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8197F) << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) -#define BITS_LPQ_HIGH_TH_V1_8197F (BIT_MASK_LPQ_HIGH_TH_V1_8197F << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) +#define BIT_LPQ_HIGH_TH_V1_8197F(x) \ + (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8197F) \ + << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) +#define BITS_LPQ_HIGH_TH_V1_8197F \ + (BIT_MASK_LPQ_HIGH_TH_V1_8197F << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) #define BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8197F)) -#define BIT_GET_LPQ_HIGH_TH_V1_8197F(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) & BIT_MASK_LPQ_HIGH_TH_V1_8197F) -#define BIT_SET_LPQ_HIGH_TH_V1_8197F(x, v) (BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) | BIT_LPQ_HIGH_TH_V1_8197F(v)) - +#define BIT_GET_LPQ_HIGH_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) & \ + BIT_MASK_LPQ_HIGH_TH_V1_8197F) +#define BIT_SET_LPQ_HIGH_TH_V1_8197F(x, v) \ + (BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) | BIT_LPQ_HIGH_TH_V1_8197F(v)) #define BIT_SHIFT_LPQ_LOW_TH_V1_8197F 0 #define BIT_MASK_LPQ_LOW_TH_V1_8197F 0xfff -#define BIT_LPQ_LOW_TH_V1_8197F(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8197F) << BIT_SHIFT_LPQ_LOW_TH_V1_8197F) -#define BITS_LPQ_LOW_TH_V1_8197F (BIT_MASK_LPQ_LOW_TH_V1_8197F << BIT_SHIFT_LPQ_LOW_TH_V1_8197F) +#define BIT_LPQ_LOW_TH_V1_8197F(x) \ + (((x) & BIT_MASK_LPQ_LOW_TH_V1_8197F) << BIT_SHIFT_LPQ_LOW_TH_V1_8197F) +#define BITS_LPQ_LOW_TH_V1_8197F \ + (BIT_MASK_LPQ_LOW_TH_V1_8197F << BIT_SHIFT_LPQ_LOW_TH_V1_8197F) #define BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8197F)) -#define BIT_GET_LPQ_LOW_TH_V1_8197F(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8197F) & BIT_MASK_LPQ_LOW_TH_V1_8197F) -#define BIT_SET_LPQ_LOW_TH_V1_8197F(x, v) (BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) | BIT_LPQ_LOW_TH_V1_8197F(v)) - +#define BIT_GET_LPQ_LOW_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8197F) & BIT_MASK_LPQ_LOW_TH_V1_8197F) +#define BIT_SET_LPQ_LOW_TH_V1_8197F(x, v) \ + (BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) | BIT_LPQ_LOW_TH_V1_8197F(v)) /* 2 REG_TQPNT4_8197F */ #define BIT_SHIFT_EXQ_HIGH_TH_V1_8197F 16 #define BIT_MASK_EXQ_HIGH_TH_V1_8197F 0xfff -#define BIT_EXQ_HIGH_TH_V1_8197F(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8197F) << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) -#define BITS_EXQ_HIGH_TH_V1_8197F (BIT_MASK_EXQ_HIGH_TH_V1_8197F << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) +#define BIT_EXQ_HIGH_TH_V1_8197F(x) \ + (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8197F) \ + << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) +#define BITS_EXQ_HIGH_TH_V1_8197F \ + (BIT_MASK_EXQ_HIGH_TH_V1_8197F << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) #define BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8197F)) -#define BIT_GET_EXQ_HIGH_TH_V1_8197F(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) & BIT_MASK_EXQ_HIGH_TH_V1_8197F) -#define BIT_SET_EXQ_HIGH_TH_V1_8197F(x, v) (BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) | BIT_EXQ_HIGH_TH_V1_8197F(v)) - +#define BIT_GET_EXQ_HIGH_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) & \ + BIT_MASK_EXQ_HIGH_TH_V1_8197F) +#define BIT_SET_EXQ_HIGH_TH_V1_8197F(x, v) \ + (BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) | BIT_EXQ_HIGH_TH_V1_8197F(v)) #define BIT_SHIFT_EXQ_LOW_TH_V1_8197F 0 #define BIT_MASK_EXQ_LOW_TH_V1_8197F 0xfff -#define BIT_EXQ_LOW_TH_V1_8197F(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8197F) << BIT_SHIFT_EXQ_LOW_TH_V1_8197F) -#define BITS_EXQ_LOW_TH_V1_8197F (BIT_MASK_EXQ_LOW_TH_V1_8197F << BIT_SHIFT_EXQ_LOW_TH_V1_8197F) +#define BIT_EXQ_LOW_TH_V1_8197F(x) \ + (((x) & BIT_MASK_EXQ_LOW_TH_V1_8197F) << BIT_SHIFT_EXQ_LOW_TH_V1_8197F) +#define BITS_EXQ_LOW_TH_V1_8197F \ + (BIT_MASK_EXQ_LOW_TH_V1_8197F << BIT_SHIFT_EXQ_LOW_TH_V1_8197F) #define BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8197F)) -#define BIT_GET_EXQ_LOW_TH_V1_8197F(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8197F) & BIT_MASK_EXQ_LOW_TH_V1_8197F) -#define BIT_SET_EXQ_LOW_TH_V1_8197F(x, v) (BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) | BIT_EXQ_LOW_TH_V1_8197F(v)) - +#define BIT_GET_EXQ_LOW_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8197F) & BIT_MASK_EXQ_LOW_TH_V1_8197F) +#define BIT_SET_EXQ_LOW_TH_V1_8197F(x, v) \ + (BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) | BIT_EXQ_LOW_TH_V1_8197F(v)) /* 2 REG_RQPN_CTRL_1_8197F */ #define BIT_SHIFT_TXPKTNUM_H_8197F 16 #define BIT_MASK_TXPKTNUM_H_8197F 0xffff -#define BIT_TXPKTNUM_H_8197F(x) (((x) & BIT_MASK_TXPKTNUM_H_8197F) << BIT_SHIFT_TXPKTNUM_H_8197F) -#define BITS_TXPKTNUM_H_8197F (BIT_MASK_TXPKTNUM_H_8197F << BIT_SHIFT_TXPKTNUM_H_8197F) +#define BIT_TXPKTNUM_H_8197F(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_8197F) << BIT_SHIFT_TXPKTNUM_H_8197F) +#define BITS_TXPKTNUM_H_8197F \ + (BIT_MASK_TXPKTNUM_H_8197F << BIT_SHIFT_TXPKTNUM_H_8197F) #define BIT_CLEAR_TXPKTNUM_H_8197F(x) ((x) & (~BITS_TXPKTNUM_H_8197F)) -#define BIT_GET_TXPKTNUM_H_8197F(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8197F) & BIT_MASK_TXPKTNUM_H_8197F) -#define BIT_SET_TXPKTNUM_H_8197F(x, v) (BIT_CLEAR_TXPKTNUM_H_8197F(x) | BIT_TXPKTNUM_H_8197F(v)) - +#define BIT_GET_TXPKTNUM_H_8197F(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_8197F) & BIT_MASK_TXPKTNUM_H_8197F) +#define BIT_SET_TXPKTNUM_H_8197F(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_8197F(x) | BIT_TXPKTNUM_H_8197F(v)) #define BIT_SHIFT_TXPKTNUM_H_V1_8197F 0 #define BIT_MASK_TXPKTNUM_H_V1_8197F 0xffff -#define BIT_TXPKTNUM_H_V1_8197F(x) (((x) & BIT_MASK_TXPKTNUM_H_V1_8197F) << BIT_SHIFT_TXPKTNUM_H_V1_8197F) -#define BITS_TXPKTNUM_H_V1_8197F (BIT_MASK_TXPKTNUM_H_V1_8197F << BIT_SHIFT_TXPKTNUM_H_V1_8197F) +#define BIT_TXPKTNUM_H_V1_8197F(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_V1_8197F) << BIT_SHIFT_TXPKTNUM_H_V1_8197F) +#define BITS_TXPKTNUM_H_V1_8197F \ + (BIT_MASK_TXPKTNUM_H_V1_8197F << BIT_SHIFT_TXPKTNUM_H_V1_8197F) #define BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) ((x) & (~BITS_TXPKTNUM_H_V1_8197F)) -#define BIT_GET_TXPKTNUM_H_V1_8197F(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_V1_8197F) & BIT_MASK_TXPKTNUM_H_V1_8197F) -#define BIT_SET_TXPKTNUM_H_V1_8197F(x, v) (BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) | BIT_TXPKTNUM_H_V1_8197F(v)) - +#define BIT_GET_TXPKTNUM_H_V1_8197F(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_V1_8197F) & BIT_MASK_TXPKTNUM_H_V1_8197F) +#define BIT_SET_TXPKTNUM_H_V1_8197F(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) | BIT_TXPKTNUM_H_V1_8197F(v)) /* 2 REG_RQPN_CTRL_2_8197F */ #define BIT_LD_RQPN_8197F BIT(31) @@ -4161,145 +5169,192 @@ #define BIT_SHIFT_HPQ_AVAL_PG_V1_8197F 16 #define BIT_MASK_HPQ_AVAL_PG_V1_8197F 0xfff -#define BIT_HPQ_AVAL_PG_V1_8197F(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8197F) << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) -#define BITS_HPQ_AVAL_PG_V1_8197F (BIT_MASK_HPQ_AVAL_PG_V1_8197F << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) +#define BIT_HPQ_AVAL_PG_V1_8197F(x) \ + (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8197F) \ + << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) +#define BITS_HPQ_AVAL_PG_V1_8197F \ + (BIT_MASK_HPQ_AVAL_PG_V1_8197F << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) #define BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8197F)) -#define BIT_GET_HPQ_AVAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) & BIT_MASK_HPQ_AVAL_PG_V1_8197F) -#define BIT_SET_HPQ_AVAL_PG_V1_8197F(x, v) (BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) | BIT_HPQ_AVAL_PG_V1_8197F(v)) - +#define BIT_GET_HPQ_AVAL_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) & \ + BIT_MASK_HPQ_AVAL_PG_V1_8197F) +#define BIT_SET_HPQ_AVAL_PG_V1_8197F(x, v) \ + (BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) | BIT_HPQ_AVAL_PG_V1_8197F(v)) #define BIT_SHIFT_HPQ_V1_8197F 0 #define BIT_MASK_HPQ_V1_8197F 0xfff -#define BIT_HPQ_V1_8197F(x) (((x) & BIT_MASK_HPQ_V1_8197F) << BIT_SHIFT_HPQ_V1_8197F) +#define BIT_HPQ_V1_8197F(x) \ + (((x) & BIT_MASK_HPQ_V1_8197F) << BIT_SHIFT_HPQ_V1_8197F) #define BITS_HPQ_V1_8197F (BIT_MASK_HPQ_V1_8197F << BIT_SHIFT_HPQ_V1_8197F) #define BIT_CLEAR_HPQ_V1_8197F(x) ((x) & (~BITS_HPQ_V1_8197F)) -#define BIT_GET_HPQ_V1_8197F(x) (((x) >> BIT_SHIFT_HPQ_V1_8197F) & BIT_MASK_HPQ_V1_8197F) -#define BIT_SET_HPQ_V1_8197F(x, v) (BIT_CLEAR_HPQ_V1_8197F(x) | BIT_HPQ_V1_8197F(v)) - +#define BIT_GET_HPQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HPQ_V1_8197F) & BIT_MASK_HPQ_V1_8197F) +#define BIT_SET_HPQ_V1_8197F(x, v) \ + (BIT_CLEAR_HPQ_V1_8197F(x) | BIT_HPQ_V1_8197F(v)) /* 2 REG_FIFOPAGE_INFO_2_8197F */ #define BIT_SHIFT_LPQ_AVAL_PG_V1_8197F 16 #define BIT_MASK_LPQ_AVAL_PG_V1_8197F 0xfff -#define BIT_LPQ_AVAL_PG_V1_8197F(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8197F) << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) -#define BITS_LPQ_AVAL_PG_V1_8197F (BIT_MASK_LPQ_AVAL_PG_V1_8197F << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) +#define BIT_LPQ_AVAL_PG_V1_8197F(x) \ + (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8197F) \ + << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) +#define BITS_LPQ_AVAL_PG_V1_8197F \ + (BIT_MASK_LPQ_AVAL_PG_V1_8197F << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) #define BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8197F)) -#define BIT_GET_LPQ_AVAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) & BIT_MASK_LPQ_AVAL_PG_V1_8197F) -#define BIT_SET_LPQ_AVAL_PG_V1_8197F(x, v) (BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) | BIT_LPQ_AVAL_PG_V1_8197F(v)) - +#define BIT_GET_LPQ_AVAL_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) & \ + BIT_MASK_LPQ_AVAL_PG_V1_8197F) +#define BIT_SET_LPQ_AVAL_PG_V1_8197F(x, v) \ + (BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) | BIT_LPQ_AVAL_PG_V1_8197F(v)) #define BIT_SHIFT_LPQ_V1_8197F 0 #define BIT_MASK_LPQ_V1_8197F 0xfff -#define BIT_LPQ_V1_8197F(x) (((x) & BIT_MASK_LPQ_V1_8197F) << BIT_SHIFT_LPQ_V1_8197F) +#define BIT_LPQ_V1_8197F(x) \ + (((x) & BIT_MASK_LPQ_V1_8197F) << BIT_SHIFT_LPQ_V1_8197F) #define BITS_LPQ_V1_8197F (BIT_MASK_LPQ_V1_8197F << BIT_SHIFT_LPQ_V1_8197F) #define BIT_CLEAR_LPQ_V1_8197F(x) ((x) & (~BITS_LPQ_V1_8197F)) -#define BIT_GET_LPQ_V1_8197F(x) (((x) >> BIT_SHIFT_LPQ_V1_8197F) & BIT_MASK_LPQ_V1_8197F) -#define BIT_SET_LPQ_V1_8197F(x, v) (BIT_CLEAR_LPQ_V1_8197F(x) | BIT_LPQ_V1_8197F(v)) - +#define BIT_GET_LPQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LPQ_V1_8197F) & BIT_MASK_LPQ_V1_8197F) +#define BIT_SET_LPQ_V1_8197F(x, v) \ + (BIT_CLEAR_LPQ_V1_8197F(x) | BIT_LPQ_V1_8197F(v)) /* 2 REG_FIFOPAGE_INFO_3_8197F */ -#define BIT_SHIFT_NPQ_AVAL_PG_8197F 8 -#define BIT_MASK_NPQ_AVAL_PG_8197F 0xff -#define BIT_NPQ_AVAL_PG_8197F(x) (((x) & BIT_MASK_NPQ_AVAL_PG_8197F) << BIT_SHIFT_NPQ_AVAL_PG_8197F) -#define BITS_NPQ_AVAL_PG_8197F (BIT_MASK_NPQ_AVAL_PG_8197F << BIT_SHIFT_NPQ_AVAL_PG_8197F) -#define BIT_CLEAR_NPQ_AVAL_PG_8197F(x) ((x) & (~BITS_NPQ_AVAL_PG_8197F)) -#define BIT_GET_NPQ_AVAL_PG_8197F(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_8197F) & BIT_MASK_NPQ_AVAL_PG_8197F) -#define BIT_SET_NPQ_AVAL_PG_8197F(x, v) (BIT_CLEAR_NPQ_AVAL_PG_8197F(x) | BIT_NPQ_AVAL_PG_8197F(v)) - +#define BIT_SHIFT_NPQ_AVAL_PG_V1_8197F 16 +#define BIT_MASK_NPQ_AVAL_PG_V1_8197F 0xfff +#define BIT_NPQ_AVAL_PG_V1_8197F(x) \ + (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8197F) \ + << BIT_SHIFT_NPQ_AVAL_PG_V1_8197F) +#define BITS_NPQ_AVAL_PG_V1_8197F \ + (BIT_MASK_NPQ_AVAL_PG_V1_8197F << BIT_SHIFT_NPQ_AVAL_PG_V1_8197F) +#define BIT_CLEAR_NPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8197F)) +#define BIT_GET_NPQ_AVAL_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8197F) & \ + BIT_MASK_NPQ_AVAL_PG_V1_8197F) +#define BIT_SET_NPQ_AVAL_PG_V1_8197F(x, v) \ + (BIT_CLEAR_NPQ_AVAL_PG_V1_8197F(x) | BIT_NPQ_AVAL_PG_V1_8197F(v)) #define BIT_SHIFT_NPQ_V1_8197F 0 #define BIT_MASK_NPQ_V1_8197F 0xfff -#define BIT_NPQ_V1_8197F(x) (((x) & BIT_MASK_NPQ_V1_8197F) << BIT_SHIFT_NPQ_V1_8197F) +#define BIT_NPQ_V1_8197F(x) \ + (((x) & BIT_MASK_NPQ_V1_8197F) << BIT_SHIFT_NPQ_V1_8197F) #define BITS_NPQ_V1_8197F (BIT_MASK_NPQ_V1_8197F << BIT_SHIFT_NPQ_V1_8197F) #define BIT_CLEAR_NPQ_V1_8197F(x) ((x) & (~BITS_NPQ_V1_8197F)) -#define BIT_GET_NPQ_V1_8197F(x) (((x) >> BIT_SHIFT_NPQ_V1_8197F) & BIT_MASK_NPQ_V1_8197F) -#define BIT_SET_NPQ_V1_8197F(x, v) (BIT_CLEAR_NPQ_V1_8197F(x) | BIT_NPQ_V1_8197F(v)) - +#define BIT_GET_NPQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_NPQ_V1_8197F) & BIT_MASK_NPQ_V1_8197F) +#define BIT_SET_NPQ_V1_8197F(x, v) \ + (BIT_CLEAR_NPQ_V1_8197F(x) | BIT_NPQ_V1_8197F(v)) /* 2 REG_FIFOPAGE_INFO_4_8197F */ #define BIT_SHIFT_EXQ_AVAL_PG_V1_8197F 16 #define BIT_MASK_EXQ_AVAL_PG_V1_8197F 0xfff -#define BIT_EXQ_AVAL_PG_V1_8197F(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8197F) << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) -#define BITS_EXQ_AVAL_PG_V1_8197F (BIT_MASK_EXQ_AVAL_PG_V1_8197F << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) +#define BIT_EXQ_AVAL_PG_V1_8197F(x) \ + (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8197F) \ + << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) +#define BITS_EXQ_AVAL_PG_V1_8197F \ + (BIT_MASK_EXQ_AVAL_PG_V1_8197F << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) #define BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8197F)) -#define BIT_GET_EXQ_AVAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) & BIT_MASK_EXQ_AVAL_PG_V1_8197F) -#define BIT_SET_EXQ_AVAL_PG_V1_8197F(x, v) (BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) | BIT_EXQ_AVAL_PG_V1_8197F(v)) - +#define BIT_GET_EXQ_AVAL_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) & \ + BIT_MASK_EXQ_AVAL_PG_V1_8197F) +#define BIT_SET_EXQ_AVAL_PG_V1_8197F(x, v) \ + (BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) | BIT_EXQ_AVAL_PG_V1_8197F(v)) #define BIT_SHIFT_EXQ_V1_8197F 0 #define BIT_MASK_EXQ_V1_8197F 0xfff -#define BIT_EXQ_V1_8197F(x) (((x) & BIT_MASK_EXQ_V1_8197F) << BIT_SHIFT_EXQ_V1_8197F) +#define BIT_EXQ_V1_8197F(x) \ + (((x) & BIT_MASK_EXQ_V1_8197F) << BIT_SHIFT_EXQ_V1_8197F) #define BITS_EXQ_V1_8197F (BIT_MASK_EXQ_V1_8197F << BIT_SHIFT_EXQ_V1_8197F) #define BIT_CLEAR_EXQ_V1_8197F(x) ((x) & (~BITS_EXQ_V1_8197F)) -#define BIT_GET_EXQ_V1_8197F(x) (((x) >> BIT_SHIFT_EXQ_V1_8197F) & BIT_MASK_EXQ_V1_8197F) -#define BIT_SET_EXQ_V1_8197F(x, v) (BIT_CLEAR_EXQ_V1_8197F(x) | BIT_EXQ_V1_8197F(v)) - +#define BIT_GET_EXQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_EXQ_V1_8197F) & BIT_MASK_EXQ_V1_8197F) +#define BIT_SET_EXQ_V1_8197F(x, v) \ + (BIT_CLEAR_EXQ_V1_8197F(x) | BIT_EXQ_V1_8197F(v)) /* 2 REG_FIFOPAGE_INFO_5_8197F */ #define BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F 16 #define BIT_MASK_PUBQ_AVAL_PG_V1_8197F 0xfff -#define BIT_PUBQ_AVAL_PG_V1_8197F(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8197F) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) -#define BITS_PUBQ_AVAL_PG_V1_8197F (BIT_MASK_PUBQ_AVAL_PG_V1_8197F << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) +#define BIT_PUBQ_AVAL_PG_V1_8197F(x) \ + (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8197F) \ + << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) +#define BITS_PUBQ_AVAL_PG_V1_8197F \ + (BIT_MASK_PUBQ_AVAL_PG_V1_8197F << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) #define BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8197F)) -#define BIT_GET_PUBQ_AVAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) & BIT_MASK_PUBQ_AVAL_PG_V1_8197F) -#define BIT_SET_PUBQ_AVAL_PG_V1_8197F(x, v) (BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) | BIT_PUBQ_AVAL_PG_V1_8197F(v)) - +#define BIT_GET_PUBQ_AVAL_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) & \ + BIT_MASK_PUBQ_AVAL_PG_V1_8197F) +#define BIT_SET_PUBQ_AVAL_PG_V1_8197F(x, v) \ + (BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) | BIT_PUBQ_AVAL_PG_V1_8197F(v)) #define BIT_SHIFT_PUBQ_V1_8197F 0 #define BIT_MASK_PUBQ_V1_8197F 0xfff -#define BIT_PUBQ_V1_8197F(x) (((x) & BIT_MASK_PUBQ_V1_8197F) << BIT_SHIFT_PUBQ_V1_8197F) +#define BIT_PUBQ_V1_8197F(x) \ + (((x) & BIT_MASK_PUBQ_V1_8197F) << BIT_SHIFT_PUBQ_V1_8197F) #define BITS_PUBQ_V1_8197F (BIT_MASK_PUBQ_V1_8197F << BIT_SHIFT_PUBQ_V1_8197F) #define BIT_CLEAR_PUBQ_V1_8197F(x) ((x) & (~BITS_PUBQ_V1_8197F)) -#define BIT_GET_PUBQ_V1_8197F(x) (((x) >> BIT_SHIFT_PUBQ_V1_8197F) & BIT_MASK_PUBQ_V1_8197F) -#define BIT_SET_PUBQ_V1_8197F(x, v) (BIT_CLEAR_PUBQ_V1_8197F(x) | BIT_PUBQ_V1_8197F(v)) - +#define BIT_GET_PUBQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PUBQ_V1_8197F) & BIT_MASK_PUBQ_V1_8197F) +#define BIT_SET_PUBQ_V1_8197F(x, v) \ + (BIT_CLEAR_PUBQ_V1_8197F(x) | BIT_PUBQ_V1_8197F(v)) /* 2 REG_H2C_HEAD_8197F */ #define BIT_SHIFT_H2C_HEAD_8197F 0 #define BIT_MASK_H2C_HEAD_8197F 0x3ffff -#define BIT_H2C_HEAD_8197F(x) (((x) & BIT_MASK_H2C_HEAD_8197F) << BIT_SHIFT_H2C_HEAD_8197F) -#define BITS_H2C_HEAD_8197F (BIT_MASK_H2C_HEAD_8197F << BIT_SHIFT_H2C_HEAD_8197F) +#define BIT_H2C_HEAD_8197F(x) \ + (((x) & BIT_MASK_H2C_HEAD_8197F) << BIT_SHIFT_H2C_HEAD_8197F) +#define BITS_H2C_HEAD_8197F \ + (BIT_MASK_H2C_HEAD_8197F << BIT_SHIFT_H2C_HEAD_8197F) #define BIT_CLEAR_H2C_HEAD_8197F(x) ((x) & (~BITS_H2C_HEAD_8197F)) -#define BIT_GET_H2C_HEAD_8197F(x) (((x) >> BIT_SHIFT_H2C_HEAD_8197F) & BIT_MASK_H2C_HEAD_8197F) -#define BIT_SET_H2C_HEAD_8197F(x, v) (BIT_CLEAR_H2C_HEAD_8197F(x) | BIT_H2C_HEAD_8197F(v)) - +#define BIT_GET_H2C_HEAD_8197F(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_8197F) & BIT_MASK_H2C_HEAD_8197F) +#define BIT_SET_H2C_HEAD_8197F(x, v) \ + (BIT_CLEAR_H2C_HEAD_8197F(x) | BIT_H2C_HEAD_8197F(v)) /* 2 REG_H2C_TAIL_8197F */ #define BIT_SHIFT_H2C_TAIL_8197F 0 #define BIT_MASK_H2C_TAIL_8197F 0x3ffff -#define BIT_H2C_TAIL_8197F(x) (((x) & BIT_MASK_H2C_TAIL_8197F) << BIT_SHIFT_H2C_TAIL_8197F) -#define BITS_H2C_TAIL_8197F (BIT_MASK_H2C_TAIL_8197F << BIT_SHIFT_H2C_TAIL_8197F) +#define BIT_H2C_TAIL_8197F(x) \ + (((x) & BIT_MASK_H2C_TAIL_8197F) << BIT_SHIFT_H2C_TAIL_8197F) +#define BITS_H2C_TAIL_8197F \ + (BIT_MASK_H2C_TAIL_8197F << BIT_SHIFT_H2C_TAIL_8197F) #define BIT_CLEAR_H2C_TAIL_8197F(x) ((x) & (~BITS_H2C_TAIL_8197F)) -#define BIT_GET_H2C_TAIL_8197F(x) (((x) >> BIT_SHIFT_H2C_TAIL_8197F) & BIT_MASK_H2C_TAIL_8197F) -#define BIT_SET_H2C_TAIL_8197F(x, v) (BIT_CLEAR_H2C_TAIL_8197F(x) | BIT_H2C_TAIL_8197F(v)) - +#define BIT_GET_H2C_TAIL_8197F(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_8197F) & BIT_MASK_H2C_TAIL_8197F) +#define BIT_SET_H2C_TAIL_8197F(x, v) \ + (BIT_CLEAR_H2C_TAIL_8197F(x) | BIT_H2C_TAIL_8197F(v)) /* 2 REG_H2C_READ_ADDR_8197F */ #define BIT_SHIFT_H2C_READ_ADDR_8197F 0 #define BIT_MASK_H2C_READ_ADDR_8197F 0x3ffff -#define BIT_H2C_READ_ADDR_8197F(x) (((x) & BIT_MASK_H2C_READ_ADDR_8197F) << BIT_SHIFT_H2C_READ_ADDR_8197F) -#define BITS_H2C_READ_ADDR_8197F (BIT_MASK_H2C_READ_ADDR_8197F << BIT_SHIFT_H2C_READ_ADDR_8197F) +#define BIT_H2C_READ_ADDR_8197F(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_8197F) << BIT_SHIFT_H2C_READ_ADDR_8197F) +#define BITS_H2C_READ_ADDR_8197F \ + (BIT_MASK_H2C_READ_ADDR_8197F << BIT_SHIFT_H2C_READ_ADDR_8197F) #define BIT_CLEAR_H2C_READ_ADDR_8197F(x) ((x) & (~BITS_H2C_READ_ADDR_8197F)) -#define BIT_GET_H2C_READ_ADDR_8197F(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8197F) & BIT_MASK_H2C_READ_ADDR_8197F) -#define BIT_SET_H2C_READ_ADDR_8197F(x, v) (BIT_CLEAR_H2C_READ_ADDR_8197F(x) | BIT_H2C_READ_ADDR_8197F(v)) - +#define BIT_GET_H2C_READ_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_8197F) & BIT_MASK_H2C_READ_ADDR_8197F) +#define BIT_SET_H2C_READ_ADDR_8197F(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_8197F(x) | BIT_H2C_READ_ADDR_8197F(v)) /* 2 REG_H2C_WR_ADDR_8197F */ #define BIT_SHIFT_H2C_WR_ADDR_8197F 0 #define BIT_MASK_H2C_WR_ADDR_8197F 0x3ffff -#define BIT_H2C_WR_ADDR_8197F(x) (((x) & BIT_MASK_H2C_WR_ADDR_8197F) << BIT_SHIFT_H2C_WR_ADDR_8197F) -#define BITS_H2C_WR_ADDR_8197F (BIT_MASK_H2C_WR_ADDR_8197F << BIT_SHIFT_H2C_WR_ADDR_8197F) +#define BIT_H2C_WR_ADDR_8197F(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_8197F) << BIT_SHIFT_H2C_WR_ADDR_8197F) +#define BITS_H2C_WR_ADDR_8197F \ + (BIT_MASK_H2C_WR_ADDR_8197F << BIT_SHIFT_H2C_WR_ADDR_8197F) #define BIT_CLEAR_H2C_WR_ADDR_8197F(x) ((x) & (~BITS_H2C_WR_ADDR_8197F)) -#define BIT_GET_H2C_WR_ADDR_8197F(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8197F) & BIT_MASK_H2C_WR_ADDR_8197F) -#define BIT_SET_H2C_WR_ADDR_8197F(x, v) (BIT_CLEAR_H2C_WR_ADDR_8197F(x) | BIT_H2C_WR_ADDR_8197F(v)) - +#define BIT_GET_H2C_WR_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_8197F) & BIT_MASK_H2C_WR_ADDR_8197F) +#define BIT_SET_H2C_WR_ADDR_8197F(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_8197F(x) | BIT_H2C_WR_ADDR_8197F(v)) /* 2 REG_H2C_INFO_8197F */ #define BIT_EXQ_EN_PUBLIC_LIMIT_8197F BIT(11) @@ -4311,48 +5366,63 @@ #define BIT_SHIFT_H2C_LEN_SEL_8197F 0 #define BIT_MASK_H2C_LEN_SEL_8197F 0x3 -#define BIT_H2C_LEN_SEL_8197F(x) (((x) & BIT_MASK_H2C_LEN_SEL_8197F) << BIT_SHIFT_H2C_LEN_SEL_8197F) -#define BITS_H2C_LEN_SEL_8197F (BIT_MASK_H2C_LEN_SEL_8197F << BIT_SHIFT_H2C_LEN_SEL_8197F) +#define BIT_H2C_LEN_SEL_8197F(x) \ + (((x) & BIT_MASK_H2C_LEN_SEL_8197F) << BIT_SHIFT_H2C_LEN_SEL_8197F) +#define BITS_H2C_LEN_SEL_8197F \ + (BIT_MASK_H2C_LEN_SEL_8197F << BIT_SHIFT_H2C_LEN_SEL_8197F) #define BIT_CLEAR_H2C_LEN_SEL_8197F(x) ((x) & (~BITS_H2C_LEN_SEL_8197F)) -#define BIT_GET_H2C_LEN_SEL_8197F(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8197F) & BIT_MASK_H2C_LEN_SEL_8197F) -#define BIT_SET_H2C_LEN_SEL_8197F(x, v) (BIT_CLEAR_H2C_LEN_SEL_8197F(x) | BIT_H2C_LEN_SEL_8197F(v)) - +#define BIT_GET_H2C_LEN_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_H2C_LEN_SEL_8197F) & BIT_MASK_H2C_LEN_SEL_8197F) +#define BIT_SET_H2C_LEN_SEL_8197F(x, v) \ + (BIT_CLEAR_H2C_LEN_SEL_8197F(x) | BIT_H2C_LEN_SEL_8197F(v)) #define BIT_SHIFT_VI_PUB_LIMIT_8197F 16 #define BIT_MASK_VI_PUB_LIMIT_8197F 0xfff -#define BIT_VI_PUB_LIMIT_8197F(x) (((x) & BIT_MASK_VI_PUB_LIMIT_8197F) << BIT_SHIFT_VI_PUB_LIMIT_8197F) -#define BITS_VI_PUB_LIMIT_8197F (BIT_MASK_VI_PUB_LIMIT_8197F << BIT_SHIFT_VI_PUB_LIMIT_8197F) +#define BIT_VI_PUB_LIMIT_8197F(x) \ + (((x) & BIT_MASK_VI_PUB_LIMIT_8197F) << BIT_SHIFT_VI_PUB_LIMIT_8197F) +#define BITS_VI_PUB_LIMIT_8197F \ + (BIT_MASK_VI_PUB_LIMIT_8197F << BIT_SHIFT_VI_PUB_LIMIT_8197F) #define BIT_CLEAR_VI_PUB_LIMIT_8197F(x) ((x) & (~BITS_VI_PUB_LIMIT_8197F)) -#define BIT_GET_VI_PUB_LIMIT_8197F(x) (((x) >> BIT_SHIFT_VI_PUB_LIMIT_8197F) & BIT_MASK_VI_PUB_LIMIT_8197F) -#define BIT_SET_VI_PUB_LIMIT_8197F(x, v) (BIT_CLEAR_VI_PUB_LIMIT_8197F(x) | BIT_VI_PUB_LIMIT_8197F(v)) - +#define BIT_GET_VI_PUB_LIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_VI_PUB_LIMIT_8197F) & BIT_MASK_VI_PUB_LIMIT_8197F) +#define BIT_SET_VI_PUB_LIMIT_8197F(x, v) \ + (BIT_CLEAR_VI_PUB_LIMIT_8197F(x) | BIT_VI_PUB_LIMIT_8197F(v)) #define BIT_SHIFT_VO_PUB_LIMIT_8197F 0 #define BIT_MASK_VO_PUB_LIMIT_8197F 0xfff -#define BIT_VO_PUB_LIMIT_8197F(x) (((x) & BIT_MASK_VO_PUB_LIMIT_8197F) << BIT_SHIFT_VO_PUB_LIMIT_8197F) -#define BITS_VO_PUB_LIMIT_8197F (BIT_MASK_VO_PUB_LIMIT_8197F << BIT_SHIFT_VO_PUB_LIMIT_8197F) +#define BIT_VO_PUB_LIMIT_8197F(x) \ + (((x) & BIT_MASK_VO_PUB_LIMIT_8197F) << BIT_SHIFT_VO_PUB_LIMIT_8197F) +#define BITS_VO_PUB_LIMIT_8197F \ + (BIT_MASK_VO_PUB_LIMIT_8197F << BIT_SHIFT_VO_PUB_LIMIT_8197F) #define BIT_CLEAR_VO_PUB_LIMIT_8197F(x) ((x) & (~BITS_VO_PUB_LIMIT_8197F)) -#define BIT_GET_VO_PUB_LIMIT_8197F(x) (((x) >> BIT_SHIFT_VO_PUB_LIMIT_8197F) & BIT_MASK_VO_PUB_LIMIT_8197F) -#define BIT_SET_VO_PUB_LIMIT_8197F(x, v) (BIT_CLEAR_VO_PUB_LIMIT_8197F(x) | BIT_VO_PUB_LIMIT_8197F(v)) - +#define BIT_GET_VO_PUB_LIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_VO_PUB_LIMIT_8197F) & BIT_MASK_VO_PUB_LIMIT_8197F) +#define BIT_SET_VO_PUB_LIMIT_8197F(x, v) \ + (BIT_CLEAR_VO_PUB_LIMIT_8197F(x) | BIT_VO_PUB_LIMIT_8197F(v)) #define BIT_SHIFT_BK_PUB_LIMIT_8197F 16 #define BIT_MASK_BK_PUB_LIMIT_8197F 0xfff -#define BIT_BK_PUB_LIMIT_8197F(x) (((x) & BIT_MASK_BK_PUB_LIMIT_8197F) << BIT_SHIFT_BK_PUB_LIMIT_8197F) -#define BITS_BK_PUB_LIMIT_8197F (BIT_MASK_BK_PUB_LIMIT_8197F << BIT_SHIFT_BK_PUB_LIMIT_8197F) +#define BIT_BK_PUB_LIMIT_8197F(x) \ + (((x) & BIT_MASK_BK_PUB_LIMIT_8197F) << BIT_SHIFT_BK_PUB_LIMIT_8197F) +#define BITS_BK_PUB_LIMIT_8197F \ + (BIT_MASK_BK_PUB_LIMIT_8197F << BIT_SHIFT_BK_PUB_LIMIT_8197F) #define BIT_CLEAR_BK_PUB_LIMIT_8197F(x) ((x) & (~BITS_BK_PUB_LIMIT_8197F)) -#define BIT_GET_BK_PUB_LIMIT_8197F(x) (((x) >> BIT_SHIFT_BK_PUB_LIMIT_8197F) & BIT_MASK_BK_PUB_LIMIT_8197F) -#define BIT_SET_BK_PUB_LIMIT_8197F(x, v) (BIT_CLEAR_BK_PUB_LIMIT_8197F(x) | BIT_BK_PUB_LIMIT_8197F(v)) - +#define BIT_GET_BK_PUB_LIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_BK_PUB_LIMIT_8197F) & BIT_MASK_BK_PUB_LIMIT_8197F) +#define BIT_SET_BK_PUB_LIMIT_8197F(x, v) \ + (BIT_CLEAR_BK_PUB_LIMIT_8197F(x) | BIT_BK_PUB_LIMIT_8197F(v)) #define BIT_SHIFT_BE_PUB_LIMIT_8197F 0 #define BIT_MASK_BE_PUB_LIMIT_8197F 0xfff -#define BIT_BE_PUB_LIMIT_8197F(x) (((x) & BIT_MASK_BE_PUB_LIMIT_8197F) << BIT_SHIFT_BE_PUB_LIMIT_8197F) -#define BITS_BE_PUB_LIMIT_8197F (BIT_MASK_BE_PUB_LIMIT_8197F << BIT_SHIFT_BE_PUB_LIMIT_8197F) +#define BIT_BE_PUB_LIMIT_8197F(x) \ + (((x) & BIT_MASK_BE_PUB_LIMIT_8197F) << BIT_SHIFT_BE_PUB_LIMIT_8197F) +#define BITS_BE_PUB_LIMIT_8197F \ + (BIT_MASK_BE_PUB_LIMIT_8197F << BIT_SHIFT_BE_PUB_LIMIT_8197F) #define BIT_CLEAR_BE_PUB_LIMIT_8197F(x) ((x) & (~BITS_BE_PUB_LIMIT_8197F)) -#define BIT_GET_BE_PUB_LIMIT_8197F(x) (((x) >> BIT_SHIFT_BE_PUB_LIMIT_8197F) & BIT_MASK_BE_PUB_LIMIT_8197F) -#define BIT_SET_BE_PUB_LIMIT_8197F(x, v) (BIT_CLEAR_BE_PUB_LIMIT_8197F(x) | BIT_BE_PUB_LIMIT_8197F(v)) - +#define BIT_GET_BE_PUB_LIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_BE_PUB_LIMIT_8197F) & BIT_MASK_BE_PUB_LIMIT_8197F) +#define BIT_SET_BE_PUB_LIMIT_8197F(x, v) \ + (BIT_CLEAR_BE_PUB_LIMIT_8197F(x) | BIT_BE_PUB_LIMIT_8197F(v)) /* 2 REG_RXDMA_AGG_PG_TH_8197F */ #define BIT_DMA_STORE_MODE_8197F BIT(31) @@ -4362,49 +5432,72 @@ #define BIT_SHIFT_PKT_NUM_WOL_8197F 16 #define BIT_MASK_PKT_NUM_WOL_8197F 0xff -#define BIT_PKT_NUM_WOL_8197F(x) (((x) & BIT_MASK_PKT_NUM_WOL_8197F) << BIT_SHIFT_PKT_NUM_WOL_8197F) -#define BITS_PKT_NUM_WOL_8197F (BIT_MASK_PKT_NUM_WOL_8197F << BIT_SHIFT_PKT_NUM_WOL_8197F) +#define BIT_PKT_NUM_WOL_8197F(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL_8197F) << BIT_SHIFT_PKT_NUM_WOL_8197F) +#define BITS_PKT_NUM_WOL_8197F \ + (BIT_MASK_PKT_NUM_WOL_8197F << BIT_SHIFT_PKT_NUM_WOL_8197F) #define BIT_CLEAR_PKT_NUM_WOL_8197F(x) ((x) & (~BITS_PKT_NUM_WOL_8197F)) -#define BIT_GET_PKT_NUM_WOL_8197F(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8197F) & BIT_MASK_PKT_NUM_WOL_8197F) -#define BIT_SET_PKT_NUM_WOL_8197F(x, v) (BIT_CLEAR_PKT_NUM_WOL_8197F(x) | BIT_PKT_NUM_WOL_8197F(v)) - - -#define BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH_8197F 8 -#define BIT_MASK_RXDMA_AGG_TIMEOUT_TH_8197F 0xff -#define BIT_RXDMA_AGG_TIMEOUT_TH_8197F(x) (((x) & BIT_MASK_RXDMA_AGG_TIMEOUT_TH_8197F) << BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH_8197F) -#define BITS_RXDMA_AGG_TIMEOUT_TH_8197F (BIT_MASK_RXDMA_AGG_TIMEOUT_TH_8197F << BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH_8197F) -#define BIT_CLEAR_RXDMA_AGG_TIMEOUT_TH_8197F(x) ((x) & (~BITS_RXDMA_AGG_TIMEOUT_TH_8197F)) -#define BIT_GET_RXDMA_AGG_TIMEOUT_TH_8197F(x) (((x) >> BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH_8197F) & BIT_MASK_RXDMA_AGG_TIMEOUT_TH_8197F) -#define BIT_SET_RXDMA_AGG_TIMEOUT_TH_8197F(x, v) (BIT_CLEAR_RXDMA_AGG_TIMEOUT_TH_8197F(x) | BIT_RXDMA_AGG_TIMEOUT_TH_8197F(v)) - +#define BIT_GET_PKT_NUM_WOL_8197F(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL_8197F) & BIT_MASK_PKT_NUM_WOL_8197F) +#define BIT_SET_PKT_NUM_WOL_8197F(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL_8197F(x) | BIT_PKT_NUM_WOL_8197F(v)) + +#define BIT_SHIFT_DMA_AGG_TO_V1_8197F 8 +#define BIT_MASK_DMA_AGG_TO_V1_8197F 0xff +#define BIT_DMA_AGG_TO_V1_8197F(x) \ + (((x) & BIT_MASK_DMA_AGG_TO_V1_8197F) << BIT_SHIFT_DMA_AGG_TO_V1_8197F) +#define BITS_DMA_AGG_TO_V1_8197F \ + (BIT_MASK_DMA_AGG_TO_V1_8197F << BIT_SHIFT_DMA_AGG_TO_V1_8197F) +#define BIT_CLEAR_DMA_AGG_TO_V1_8197F(x) ((x) & (~BITS_DMA_AGG_TO_V1_8197F)) +#define BIT_GET_DMA_AGG_TO_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8197F) & BIT_MASK_DMA_AGG_TO_V1_8197F) +#define BIT_SET_DMA_AGG_TO_V1_8197F(x, v) \ + (BIT_CLEAR_DMA_AGG_TO_V1_8197F(x) | BIT_DMA_AGG_TO_V1_8197F(v)) #define BIT_SHIFT_RXDMA_AGG_PG_TH_8197F 0 #define BIT_MASK_RXDMA_AGG_PG_TH_8197F 0xff -#define BIT_RXDMA_AGG_PG_TH_8197F(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8197F) << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) -#define BITS_RXDMA_AGG_PG_TH_8197F (BIT_MASK_RXDMA_AGG_PG_TH_8197F << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) +#define BIT_RXDMA_AGG_PG_TH_8197F(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8197F) \ + << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) +#define BITS_RXDMA_AGG_PG_TH_8197F \ + (BIT_MASK_RXDMA_AGG_PG_TH_8197F << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) #define BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8197F)) -#define BIT_GET_RXDMA_AGG_PG_TH_8197F(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) & BIT_MASK_RXDMA_AGG_PG_TH_8197F) -#define BIT_SET_RXDMA_AGG_PG_TH_8197F(x, v) (BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) | BIT_RXDMA_AGG_PG_TH_8197F(v)) - +#define BIT_GET_RXDMA_AGG_PG_TH_8197F(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) & \ + BIT_MASK_RXDMA_AGG_PG_TH_8197F) +#define BIT_SET_RXDMA_AGG_PG_TH_8197F(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) | BIT_RXDMA_AGG_PG_TH_8197F(v)) /* 2 REG_RXPKT_NUM_8197F */ #define BIT_SHIFT_RXPKT_NUM_8197F 24 #define BIT_MASK_RXPKT_NUM_8197F 0xff -#define BIT_RXPKT_NUM_8197F(x) (((x) & BIT_MASK_RXPKT_NUM_8197F) << BIT_SHIFT_RXPKT_NUM_8197F) -#define BITS_RXPKT_NUM_8197F (BIT_MASK_RXPKT_NUM_8197F << BIT_SHIFT_RXPKT_NUM_8197F) +#define BIT_RXPKT_NUM_8197F(x) \ + (((x) & BIT_MASK_RXPKT_NUM_8197F) << BIT_SHIFT_RXPKT_NUM_8197F) +#define BITS_RXPKT_NUM_8197F \ + (BIT_MASK_RXPKT_NUM_8197F << BIT_SHIFT_RXPKT_NUM_8197F) #define BIT_CLEAR_RXPKT_NUM_8197F(x) ((x) & (~BITS_RXPKT_NUM_8197F)) -#define BIT_GET_RXPKT_NUM_8197F(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8197F) & BIT_MASK_RXPKT_NUM_8197F) -#define BIT_SET_RXPKT_NUM_8197F(x, v) (BIT_CLEAR_RXPKT_NUM_8197F(x) | BIT_RXPKT_NUM_8197F(v)) - +#define BIT_GET_RXPKT_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_8197F) & BIT_MASK_RXPKT_NUM_8197F) +#define BIT_SET_RXPKT_NUM_8197F(x, v) \ + (BIT_CLEAR_RXPKT_NUM_8197F(x) | BIT_RXPKT_NUM_8197F(v)) #define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F 20 #define BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F 0xf -#define BIT_FW_UPD_RDPTR19_TO_16_8197F(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) -#define BITS_FW_UPD_RDPTR19_TO_16_8197F (BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) -#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8197F)) -#define BIT_GET_FW_UPD_RDPTR19_TO_16_8197F(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F) -#define BIT_SET_FW_UPD_RDPTR19_TO_16_8197F(x, v) (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) | BIT_FW_UPD_RDPTR19_TO_16_8197F(v)) +#define BIT_FW_UPD_RDPTR19_TO_16_8197F(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F) \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) +#define BITS_FW_UPD_RDPTR19_TO_16_8197F \ + (BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) \ + ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8197F)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8197F(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) & \ + BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F) +#define BIT_SET_FW_UPD_RDPTR19_TO_16_8197F(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) | \ + BIT_FW_UPD_RDPTR19_TO_16_8197F(v)) #define BIT_RXDMA_REQ_8197F BIT(19) #define BIT_RW_RELEASE_EN_8197F BIT(18) @@ -4413,12 +5506,15 @@ #define BIT_SHIFT_FW_UPD_RDPTR_8197F 0 #define BIT_MASK_FW_UPD_RDPTR_8197F 0xffff -#define BIT_FW_UPD_RDPTR_8197F(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8197F) << BIT_SHIFT_FW_UPD_RDPTR_8197F) -#define BITS_FW_UPD_RDPTR_8197F (BIT_MASK_FW_UPD_RDPTR_8197F << BIT_SHIFT_FW_UPD_RDPTR_8197F) +#define BIT_FW_UPD_RDPTR_8197F(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR_8197F) << BIT_SHIFT_FW_UPD_RDPTR_8197F) +#define BITS_FW_UPD_RDPTR_8197F \ + (BIT_MASK_FW_UPD_RDPTR_8197F << BIT_SHIFT_FW_UPD_RDPTR_8197F) #define BIT_CLEAR_FW_UPD_RDPTR_8197F(x) ((x) & (~BITS_FW_UPD_RDPTR_8197F)) -#define BIT_GET_FW_UPD_RDPTR_8197F(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8197F) & BIT_MASK_FW_UPD_RDPTR_8197F) -#define BIT_SET_FW_UPD_RDPTR_8197F(x, v) (BIT_CLEAR_FW_UPD_RDPTR_8197F(x) | BIT_FW_UPD_RDPTR_8197F(v)) - +#define BIT_GET_FW_UPD_RDPTR_8197F(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8197F) & BIT_MASK_FW_UPD_RDPTR_8197F) +#define BIT_SET_FW_UPD_RDPTR_8197F(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR_8197F(x) | BIT_FW_UPD_RDPTR_8197F(v)) /* 2 REG_RXDMA_STATUS_8197F */ #define BIT_FC2H_PKT_OVERFLOW_8197F BIT(8) @@ -4434,12 +5530,15 @@ #define BIT_SHIFT_RDE_DEBUG_8197F 0 #define BIT_MASK_RDE_DEBUG_8197F 0xffffffffL -#define BIT_RDE_DEBUG_8197F(x) (((x) & BIT_MASK_RDE_DEBUG_8197F) << BIT_SHIFT_RDE_DEBUG_8197F) -#define BITS_RDE_DEBUG_8197F (BIT_MASK_RDE_DEBUG_8197F << BIT_SHIFT_RDE_DEBUG_8197F) +#define BIT_RDE_DEBUG_8197F(x) \ + (((x) & BIT_MASK_RDE_DEBUG_8197F) << BIT_SHIFT_RDE_DEBUG_8197F) +#define BITS_RDE_DEBUG_8197F \ + (BIT_MASK_RDE_DEBUG_8197F << BIT_SHIFT_RDE_DEBUG_8197F) #define BIT_CLEAR_RDE_DEBUG_8197F(x) ((x) & (~BITS_RDE_DEBUG_8197F)) -#define BIT_GET_RDE_DEBUG_8197F(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8197F) & BIT_MASK_RDE_DEBUG_8197F) -#define BIT_SET_RDE_DEBUG_8197F(x, v) (BIT_CLEAR_RDE_DEBUG_8197F(x) | BIT_RDE_DEBUG_8197F(v)) - +#define BIT_GET_RDE_DEBUG_8197F(x) \ + (((x) >> BIT_SHIFT_RDE_DEBUG_8197F) & BIT_MASK_RDE_DEBUG_8197F) +#define BIT_SET_RDE_DEBUG_8197F(x, v) \ + (BIT_CLEAR_RDE_DEBUG_8197F(x) | BIT_RDE_DEBUG_8197F(v)) /* 2 REG_RXDMA_MODE_8197F */ @@ -4452,20 +5551,27 @@ #define BIT_SHIFT_BURST_SIZE_8197F 4 #define BIT_MASK_BURST_SIZE_8197F 0x3 -#define BIT_BURST_SIZE_8197F(x) (((x) & BIT_MASK_BURST_SIZE_8197F) << BIT_SHIFT_BURST_SIZE_8197F) -#define BITS_BURST_SIZE_8197F (BIT_MASK_BURST_SIZE_8197F << BIT_SHIFT_BURST_SIZE_8197F) +#define BIT_BURST_SIZE_8197F(x) \ + (((x) & BIT_MASK_BURST_SIZE_8197F) << BIT_SHIFT_BURST_SIZE_8197F) +#define BITS_BURST_SIZE_8197F \ + (BIT_MASK_BURST_SIZE_8197F << BIT_SHIFT_BURST_SIZE_8197F) #define BIT_CLEAR_BURST_SIZE_8197F(x) ((x) & (~BITS_BURST_SIZE_8197F)) -#define BIT_GET_BURST_SIZE_8197F(x) (((x) >> BIT_SHIFT_BURST_SIZE_8197F) & BIT_MASK_BURST_SIZE_8197F) -#define BIT_SET_BURST_SIZE_8197F(x, v) (BIT_CLEAR_BURST_SIZE_8197F(x) | BIT_BURST_SIZE_8197F(v)) - +#define BIT_GET_BURST_SIZE_8197F(x) \ + (((x) >> BIT_SHIFT_BURST_SIZE_8197F) & BIT_MASK_BURST_SIZE_8197F) +#define BIT_SET_BURST_SIZE_8197F(x, v) \ + (BIT_CLEAR_BURST_SIZE_8197F(x) | BIT_BURST_SIZE_8197F(v)) #define BIT_SHIFT_BURST_CNT_8197F 2 #define BIT_MASK_BURST_CNT_8197F 0x3 -#define BIT_BURST_CNT_8197F(x) (((x) & BIT_MASK_BURST_CNT_8197F) << BIT_SHIFT_BURST_CNT_8197F) -#define BITS_BURST_CNT_8197F (BIT_MASK_BURST_CNT_8197F << BIT_SHIFT_BURST_CNT_8197F) +#define BIT_BURST_CNT_8197F(x) \ + (((x) & BIT_MASK_BURST_CNT_8197F) << BIT_SHIFT_BURST_CNT_8197F) +#define BITS_BURST_CNT_8197F \ + (BIT_MASK_BURST_CNT_8197F << BIT_SHIFT_BURST_CNT_8197F) #define BIT_CLEAR_BURST_CNT_8197F(x) ((x) & (~BITS_BURST_CNT_8197F)) -#define BIT_GET_BURST_CNT_8197F(x) (((x) >> BIT_SHIFT_BURST_CNT_8197F) & BIT_MASK_BURST_CNT_8197F) -#define BIT_SET_BURST_CNT_8197F(x, v) (BIT_CLEAR_BURST_CNT_8197F(x) | BIT_BURST_CNT_8197F(v)) +#define BIT_GET_BURST_CNT_8197F(x) \ + (((x) >> BIT_SHIFT_BURST_CNT_8197F) & BIT_MASK_BURST_CNT_8197F) +#define BIT_SET_BURST_CNT_8197F(x, v) \ + (BIT_CLEAR_BURST_CNT_8197F(x) | BIT_BURST_CNT_8197F(v)) #define BIT_DMA_MODE_8197F BIT(1) @@ -4473,86 +5579,126 @@ #define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F 24 #define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F 0xf -#define BIT_R_C2H_STR_ADDR_16_TO_19_8197F(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) -#define BITS_R_C2H_STR_ADDR_16_TO_19_8197F (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) -#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8197F)) -#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8197F(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F) -#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8197F(x, v) (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) | BIT_R_C2H_STR_ADDR_16_TO_19_8197F(v)) +#define BIT_R_C2H_STR_ADDR_16_TO_19_8197F(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F) \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) +#define BITS_R_C2H_STR_ADDR_16_TO_19_8197F \ + (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) \ + ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8197F)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8197F(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) & \ + BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8197F(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) | \ + BIT_R_C2H_STR_ADDR_16_TO_19_8197F(v)) #define BIT_R_C2H_PKT_REQ_8197F BIT(16) #define BIT_SHIFT_R_C2H_STR_ADDR_8197F 0 #define BIT_MASK_R_C2H_STR_ADDR_8197F 0xffff -#define BIT_R_C2H_STR_ADDR_8197F(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8197F) << BIT_SHIFT_R_C2H_STR_ADDR_8197F) -#define BITS_R_C2H_STR_ADDR_8197F (BIT_MASK_R_C2H_STR_ADDR_8197F << BIT_SHIFT_R_C2H_STR_ADDR_8197F) +#define BIT_R_C2H_STR_ADDR_8197F(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_8197F) \ + << BIT_SHIFT_R_C2H_STR_ADDR_8197F) +#define BITS_R_C2H_STR_ADDR_8197F \ + (BIT_MASK_R_C2H_STR_ADDR_8197F << BIT_SHIFT_R_C2H_STR_ADDR_8197F) #define BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) ((x) & (~BITS_R_C2H_STR_ADDR_8197F)) -#define BIT_GET_R_C2H_STR_ADDR_8197F(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8197F) & BIT_MASK_R_C2H_STR_ADDR_8197F) -#define BIT_SET_R_C2H_STR_ADDR_8197F(x, v) (BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) | BIT_R_C2H_STR_ADDR_8197F(v)) - +#define BIT_GET_R_C2H_STR_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8197F) & \ + BIT_MASK_R_C2H_STR_ADDR_8197F) +#define BIT_SET_R_C2H_STR_ADDR_8197F(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) | BIT_R_C2H_STR_ADDR_8197F(v)) /* 2 REG_FWFF_C2H_8197F */ #define BIT_SHIFT_C2H_DMA_ADDR_8197F 0 #define BIT_MASK_C2H_DMA_ADDR_8197F 0x3ffff -#define BIT_C2H_DMA_ADDR_8197F(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8197F) << BIT_SHIFT_C2H_DMA_ADDR_8197F) -#define BITS_C2H_DMA_ADDR_8197F (BIT_MASK_C2H_DMA_ADDR_8197F << BIT_SHIFT_C2H_DMA_ADDR_8197F) +#define BIT_C2H_DMA_ADDR_8197F(x) \ + (((x) & BIT_MASK_C2H_DMA_ADDR_8197F) << BIT_SHIFT_C2H_DMA_ADDR_8197F) +#define BITS_C2H_DMA_ADDR_8197F \ + (BIT_MASK_C2H_DMA_ADDR_8197F << BIT_SHIFT_C2H_DMA_ADDR_8197F) #define BIT_CLEAR_C2H_DMA_ADDR_8197F(x) ((x) & (~BITS_C2H_DMA_ADDR_8197F)) -#define BIT_GET_C2H_DMA_ADDR_8197F(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8197F) & BIT_MASK_C2H_DMA_ADDR_8197F) -#define BIT_SET_C2H_DMA_ADDR_8197F(x, v) (BIT_CLEAR_C2H_DMA_ADDR_8197F(x) | BIT_C2H_DMA_ADDR_8197F(v)) - +#define BIT_GET_C2H_DMA_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8197F) & BIT_MASK_C2H_DMA_ADDR_8197F) +#define BIT_SET_C2H_DMA_ADDR_8197F(x, v) \ + (BIT_CLEAR_C2H_DMA_ADDR_8197F(x) | BIT_C2H_DMA_ADDR_8197F(v)) /* 2 REG_FWFF_CTRL_8197F */ #define BIT_FWFF_DMAPKT_REQ_8197F BIT(31) #define BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F 16 #define BIT_MASK_FWFF_DMA_PKT_NUM_8197F 0xff -#define BIT_FWFF_DMA_PKT_NUM_8197F(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8197F) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) -#define BITS_FWFF_DMA_PKT_NUM_8197F (BIT_MASK_FWFF_DMA_PKT_NUM_8197F << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) -#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM_8197F)) -#define BIT_GET_FWFF_DMA_PKT_NUM_8197F(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) & BIT_MASK_FWFF_DMA_PKT_NUM_8197F) -#define BIT_SET_FWFF_DMA_PKT_NUM_8197F(x, v) (BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) | BIT_FWFF_DMA_PKT_NUM_8197F(v)) - +#define BIT_FWFF_DMA_PKT_NUM_8197F(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8197F) \ + << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) +#define BITS_FWFF_DMA_PKT_NUM_8197F \ + (BIT_MASK_FWFF_DMA_PKT_NUM_8197F << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) \ + ((x) & (~BITS_FWFF_DMA_PKT_NUM_8197F)) +#define BIT_GET_FWFF_DMA_PKT_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) & \ + BIT_MASK_FWFF_DMA_PKT_NUM_8197F) +#define BIT_SET_FWFF_DMA_PKT_NUM_8197F(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) | BIT_FWFF_DMA_PKT_NUM_8197F(v)) #define BIT_SHIFT_FWFF_STR_ADDR_8197F 0 #define BIT_MASK_FWFF_STR_ADDR_8197F 0xffff -#define BIT_FWFF_STR_ADDR_8197F(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8197F) << BIT_SHIFT_FWFF_STR_ADDR_8197F) -#define BITS_FWFF_STR_ADDR_8197F (BIT_MASK_FWFF_STR_ADDR_8197F << BIT_SHIFT_FWFF_STR_ADDR_8197F) +#define BIT_FWFF_STR_ADDR_8197F(x) \ + (((x) & BIT_MASK_FWFF_STR_ADDR_8197F) << BIT_SHIFT_FWFF_STR_ADDR_8197F) +#define BITS_FWFF_STR_ADDR_8197F \ + (BIT_MASK_FWFF_STR_ADDR_8197F << BIT_SHIFT_FWFF_STR_ADDR_8197F) #define BIT_CLEAR_FWFF_STR_ADDR_8197F(x) ((x) & (~BITS_FWFF_STR_ADDR_8197F)) -#define BIT_GET_FWFF_STR_ADDR_8197F(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8197F) & BIT_MASK_FWFF_STR_ADDR_8197F) -#define BIT_SET_FWFF_STR_ADDR_8197F(x, v) (BIT_CLEAR_FWFF_STR_ADDR_8197F(x) | BIT_FWFF_STR_ADDR_8197F(v)) - +#define BIT_GET_FWFF_STR_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8197F) & BIT_MASK_FWFF_STR_ADDR_8197F) +#define BIT_SET_FWFF_STR_ADDR_8197F(x, v) \ + (BIT_CLEAR_FWFF_STR_ADDR_8197F(x) | BIT_FWFF_STR_ADDR_8197F(v)) /* 2 REG_FWFF_PKT_INFO_8197F */ #define BIT_SHIFT_FWFF_PKT_QUEUED_8197F 16 #define BIT_MASK_FWFF_PKT_QUEUED_8197F 0xff -#define BIT_FWFF_PKT_QUEUED_8197F(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8197F) << BIT_SHIFT_FWFF_PKT_QUEUED_8197F) -#define BITS_FWFF_PKT_QUEUED_8197F (BIT_MASK_FWFF_PKT_QUEUED_8197F << BIT_SHIFT_FWFF_PKT_QUEUED_8197F) +#define BIT_FWFF_PKT_QUEUED_8197F(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED_8197F) \ + << BIT_SHIFT_FWFF_PKT_QUEUED_8197F) +#define BITS_FWFF_PKT_QUEUED_8197F \ + (BIT_MASK_FWFF_PKT_QUEUED_8197F << BIT_SHIFT_FWFF_PKT_QUEUED_8197F) #define BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8197F)) -#define BIT_GET_FWFF_PKT_QUEUED_8197F(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8197F) & BIT_MASK_FWFF_PKT_QUEUED_8197F) -#define BIT_SET_FWFF_PKT_QUEUED_8197F(x, v) (BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) | BIT_FWFF_PKT_QUEUED_8197F(v)) - +#define BIT_GET_FWFF_PKT_QUEUED_8197F(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8197F) & \ + BIT_MASK_FWFF_PKT_QUEUED_8197F) +#define BIT_SET_FWFF_PKT_QUEUED_8197F(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) | BIT_FWFF_PKT_QUEUED_8197F(v)) #define BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F 0 #define BIT_MASK_FWFF_PKT_STR_ADDR_8197F 0xffff -#define BIT_FWFF_PKT_STR_ADDR_8197F(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8197F) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) -#define BITS_FWFF_PKT_STR_ADDR_8197F (BIT_MASK_FWFF_PKT_STR_ADDR_8197F << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) -#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_8197F)) -#define BIT_GET_FWFF_PKT_STR_ADDR_8197F(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) & BIT_MASK_FWFF_PKT_STR_ADDR_8197F) -#define BIT_SET_FWFF_PKT_STR_ADDR_8197F(x, v) (BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) | BIT_FWFF_PKT_STR_ADDR_8197F(v)) - +#define BIT_FWFF_PKT_STR_ADDR_8197F(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8197F) \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) +#define BITS_FWFF_PKT_STR_ADDR_8197F \ + (BIT_MASK_FWFF_PKT_STR_ADDR_8197F << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) \ + ((x) & (~BITS_FWFF_PKT_STR_ADDR_8197F)) +#define BIT_GET_FWFF_PKT_STR_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) & \ + BIT_MASK_FWFF_PKT_STR_ADDR_8197F) +#define BIT_SET_FWFF_PKT_STR_ADDR_8197F(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) | BIT_FWFF_PKT_STR_ADDR_8197F(v)) /* 2 REG_FC2H_INFO_8197F */ #define BIT_FC2H_PKT_REQ_8197F BIT(16) -#define BIT_SHIFT_FC2H_STR_ADDR_8197F 17 -#define BIT_MASK_FC2H_STR_ADDR_8197F 0x7fff -#define BIT_FC2H_STR_ADDR_8197F(x) (((x) & BIT_MASK_FC2H_STR_ADDR_8197F) << BIT_SHIFT_FC2H_STR_ADDR_8197F) -#define BITS_FC2H_STR_ADDR_8197F (BIT_MASK_FC2H_STR_ADDR_8197F << BIT_SHIFT_FC2H_STR_ADDR_8197F) +#define BIT_SHIFT_FC2H_STR_ADDR_8197F 0 +#define BIT_MASK_FC2H_STR_ADDR_8197F 0xffff +#define BIT_FC2H_STR_ADDR_8197F(x) \ + (((x) & BIT_MASK_FC2H_STR_ADDR_8197F) << BIT_SHIFT_FC2H_STR_ADDR_8197F) +#define BITS_FC2H_STR_ADDR_8197F \ + (BIT_MASK_FC2H_STR_ADDR_8197F << BIT_SHIFT_FC2H_STR_ADDR_8197F) #define BIT_CLEAR_FC2H_STR_ADDR_8197F(x) ((x) & (~BITS_FC2H_STR_ADDR_8197F)) -#define BIT_GET_FC2H_STR_ADDR_8197F(x) (((x) >> BIT_SHIFT_FC2H_STR_ADDR_8197F) & BIT_MASK_FC2H_STR_ADDR_8197F) -#define BIT_SET_FC2H_STR_ADDR_8197F(x, v) (BIT_CLEAR_FC2H_STR_ADDR_8197F(x) | BIT_FC2H_STR_ADDR_8197F(v)) - +#define BIT_GET_FC2H_STR_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_FC2H_STR_ADDR_8197F) & BIT_MASK_FC2H_STR_ADDR_8197F) +#define BIT_SET_FC2H_STR_ADDR_8197F(x, v) \ + (BIT_CLEAR_FC2H_STR_ADDR_8197F(x) | BIT_FC2H_STR_ADDR_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -4560,23 +5706,29 @@ #define BIT_SHIFT_DDMACH0_SA_8197F 0 #define BIT_MASK_DDMACH0_SA_8197F 0xffffffffL -#define BIT_DDMACH0_SA_8197F(x) (((x) & BIT_MASK_DDMACH0_SA_8197F) << BIT_SHIFT_DDMACH0_SA_8197F) -#define BITS_DDMACH0_SA_8197F (BIT_MASK_DDMACH0_SA_8197F << BIT_SHIFT_DDMACH0_SA_8197F) +#define BIT_DDMACH0_SA_8197F(x) \ + (((x) & BIT_MASK_DDMACH0_SA_8197F) << BIT_SHIFT_DDMACH0_SA_8197F) +#define BITS_DDMACH0_SA_8197F \ + (BIT_MASK_DDMACH0_SA_8197F << BIT_SHIFT_DDMACH0_SA_8197F) #define BIT_CLEAR_DDMACH0_SA_8197F(x) ((x) & (~BITS_DDMACH0_SA_8197F)) -#define BIT_GET_DDMACH0_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8197F) & BIT_MASK_DDMACH0_SA_8197F) -#define BIT_SET_DDMACH0_SA_8197F(x, v) (BIT_CLEAR_DDMACH0_SA_8197F(x) | BIT_DDMACH0_SA_8197F(v)) - +#define BIT_GET_DDMACH0_SA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH0_SA_8197F) & BIT_MASK_DDMACH0_SA_8197F) +#define BIT_SET_DDMACH0_SA_8197F(x, v) \ + (BIT_CLEAR_DDMACH0_SA_8197F(x) | BIT_DDMACH0_SA_8197F(v)) /* 2 REG_DDMA_CH0DA_8197F */ #define BIT_SHIFT_DDMACH0_DA_8197F 0 #define BIT_MASK_DDMACH0_DA_8197F 0xffffffffL -#define BIT_DDMACH0_DA_8197F(x) (((x) & BIT_MASK_DDMACH0_DA_8197F) << BIT_SHIFT_DDMACH0_DA_8197F) -#define BITS_DDMACH0_DA_8197F (BIT_MASK_DDMACH0_DA_8197F << BIT_SHIFT_DDMACH0_DA_8197F) +#define BIT_DDMACH0_DA_8197F(x) \ + (((x) & BIT_MASK_DDMACH0_DA_8197F) << BIT_SHIFT_DDMACH0_DA_8197F) +#define BITS_DDMACH0_DA_8197F \ + (BIT_MASK_DDMACH0_DA_8197F << BIT_SHIFT_DDMACH0_DA_8197F) #define BIT_CLEAR_DDMACH0_DA_8197F(x) ((x) & (~BITS_DDMACH0_DA_8197F)) -#define BIT_GET_DDMACH0_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8197F) & BIT_MASK_DDMACH0_DA_8197F) -#define BIT_SET_DDMACH0_DA_8197F(x, v) (BIT_CLEAR_DDMACH0_DA_8197F(x) | BIT_DDMACH0_DA_8197F(v)) - +#define BIT_GET_DDMACH0_DA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DA_8197F) & BIT_MASK_DDMACH0_DA_8197F) +#define BIT_SET_DDMACH0_DA_8197F(x, v) \ + (BIT_CLEAR_DDMACH0_DA_8197F(x) | BIT_DDMACH0_DA_8197F(v)) /* 2 REG_DDMA_CH0CTRL_8197F */ #define BIT_DDMACH0_OWN_8197F BIT(31) @@ -4589,34 +5741,43 @@ #define BIT_SHIFT_DDMACH0_DLEN_8197F 0 #define BIT_MASK_DDMACH0_DLEN_8197F 0x3ffff -#define BIT_DDMACH0_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH0_DLEN_8197F) << BIT_SHIFT_DDMACH0_DLEN_8197F) -#define BITS_DDMACH0_DLEN_8197F (BIT_MASK_DDMACH0_DLEN_8197F << BIT_SHIFT_DDMACH0_DLEN_8197F) +#define BIT_DDMACH0_DLEN_8197F(x) \ + (((x) & BIT_MASK_DDMACH0_DLEN_8197F) << BIT_SHIFT_DDMACH0_DLEN_8197F) +#define BITS_DDMACH0_DLEN_8197F \ + (BIT_MASK_DDMACH0_DLEN_8197F << BIT_SHIFT_DDMACH0_DLEN_8197F) #define BIT_CLEAR_DDMACH0_DLEN_8197F(x) ((x) & (~BITS_DDMACH0_DLEN_8197F)) -#define BIT_GET_DDMACH0_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8197F) & BIT_MASK_DDMACH0_DLEN_8197F) -#define BIT_SET_DDMACH0_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH0_DLEN_8197F(x) | BIT_DDMACH0_DLEN_8197F(v)) - +#define BIT_GET_DDMACH0_DLEN_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DLEN_8197F) & BIT_MASK_DDMACH0_DLEN_8197F) +#define BIT_SET_DDMACH0_DLEN_8197F(x, v) \ + (BIT_CLEAR_DDMACH0_DLEN_8197F(x) | BIT_DDMACH0_DLEN_8197F(v)) /* 2 REG_DDMA_CH1SA_8197F */ #define BIT_SHIFT_DDMACH1_SA_8197F 0 #define BIT_MASK_DDMACH1_SA_8197F 0xffffffffL -#define BIT_DDMACH1_SA_8197F(x) (((x) & BIT_MASK_DDMACH1_SA_8197F) << BIT_SHIFT_DDMACH1_SA_8197F) -#define BITS_DDMACH1_SA_8197F (BIT_MASK_DDMACH1_SA_8197F << BIT_SHIFT_DDMACH1_SA_8197F) +#define BIT_DDMACH1_SA_8197F(x) \ + (((x) & BIT_MASK_DDMACH1_SA_8197F) << BIT_SHIFT_DDMACH1_SA_8197F) +#define BITS_DDMACH1_SA_8197F \ + (BIT_MASK_DDMACH1_SA_8197F << BIT_SHIFT_DDMACH1_SA_8197F) #define BIT_CLEAR_DDMACH1_SA_8197F(x) ((x) & (~BITS_DDMACH1_SA_8197F)) -#define BIT_GET_DDMACH1_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8197F) & BIT_MASK_DDMACH1_SA_8197F) -#define BIT_SET_DDMACH1_SA_8197F(x, v) (BIT_CLEAR_DDMACH1_SA_8197F(x) | BIT_DDMACH1_SA_8197F(v)) - +#define BIT_GET_DDMACH1_SA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH1_SA_8197F) & BIT_MASK_DDMACH1_SA_8197F) +#define BIT_SET_DDMACH1_SA_8197F(x, v) \ + (BIT_CLEAR_DDMACH1_SA_8197F(x) | BIT_DDMACH1_SA_8197F(v)) /* 2 REG_DDMA_CH1DA_8197F */ #define BIT_SHIFT_DDMACH1_DA_8197F 0 #define BIT_MASK_DDMACH1_DA_8197F 0xffffffffL -#define BIT_DDMACH1_DA_8197F(x) (((x) & BIT_MASK_DDMACH1_DA_8197F) << BIT_SHIFT_DDMACH1_DA_8197F) -#define BITS_DDMACH1_DA_8197F (BIT_MASK_DDMACH1_DA_8197F << BIT_SHIFT_DDMACH1_DA_8197F) +#define BIT_DDMACH1_DA_8197F(x) \ + (((x) & BIT_MASK_DDMACH1_DA_8197F) << BIT_SHIFT_DDMACH1_DA_8197F) +#define BITS_DDMACH1_DA_8197F \ + (BIT_MASK_DDMACH1_DA_8197F << BIT_SHIFT_DDMACH1_DA_8197F) #define BIT_CLEAR_DDMACH1_DA_8197F(x) ((x) & (~BITS_DDMACH1_DA_8197F)) -#define BIT_GET_DDMACH1_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8197F) & BIT_MASK_DDMACH1_DA_8197F) -#define BIT_SET_DDMACH1_DA_8197F(x, v) (BIT_CLEAR_DDMACH1_DA_8197F(x) | BIT_DDMACH1_DA_8197F(v)) - +#define BIT_GET_DDMACH1_DA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DA_8197F) & BIT_MASK_DDMACH1_DA_8197F) +#define BIT_SET_DDMACH1_DA_8197F(x, v) \ + (BIT_CLEAR_DDMACH1_DA_8197F(x) | BIT_DDMACH1_DA_8197F(v)) /* 2 REG_DDMA_CH1CTRL_8197F */ #define BIT_DDMACH1_OWN_8197F BIT(31) @@ -4629,34 +5790,43 @@ #define BIT_SHIFT_DDMACH1_DLEN_8197F 0 #define BIT_MASK_DDMACH1_DLEN_8197F 0x3ffff -#define BIT_DDMACH1_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH1_DLEN_8197F) << BIT_SHIFT_DDMACH1_DLEN_8197F) -#define BITS_DDMACH1_DLEN_8197F (BIT_MASK_DDMACH1_DLEN_8197F << BIT_SHIFT_DDMACH1_DLEN_8197F) +#define BIT_DDMACH1_DLEN_8197F(x) \ + (((x) & BIT_MASK_DDMACH1_DLEN_8197F) << BIT_SHIFT_DDMACH1_DLEN_8197F) +#define BITS_DDMACH1_DLEN_8197F \ + (BIT_MASK_DDMACH1_DLEN_8197F << BIT_SHIFT_DDMACH1_DLEN_8197F) #define BIT_CLEAR_DDMACH1_DLEN_8197F(x) ((x) & (~BITS_DDMACH1_DLEN_8197F)) -#define BIT_GET_DDMACH1_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8197F) & BIT_MASK_DDMACH1_DLEN_8197F) -#define BIT_SET_DDMACH1_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH1_DLEN_8197F(x) | BIT_DDMACH1_DLEN_8197F(v)) - +#define BIT_GET_DDMACH1_DLEN_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DLEN_8197F) & BIT_MASK_DDMACH1_DLEN_8197F) +#define BIT_SET_DDMACH1_DLEN_8197F(x, v) \ + (BIT_CLEAR_DDMACH1_DLEN_8197F(x) | BIT_DDMACH1_DLEN_8197F(v)) /* 2 REG_DDMA_CH2SA_8197F */ #define BIT_SHIFT_DDMACH2_SA_8197F 0 #define BIT_MASK_DDMACH2_SA_8197F 0xffffffffL -#define BIT_DDMACH2_SA_8197F(x) (((x) & BIT_MASK_DDMACH2_SA_8197F) << BIT_SHIFT_DDMACH2_SA_8197F) -#define BITS_DDMACH2_SA_8197F (BIT_MASK_DDMACH2_SA_8197F << BIT_SHIFT_DDMACH2_SA_8197F) +#define BIT_DDMACH2_SA_8197F(x) \ + (((x) & BIT_MASK_DDMACH2_SA_8197F) << BIT_SHIFT_DDMACH2_SA_8197F) +#define BITS_DDMACH2_SA_8197F \ + (BIT_MASK_DDMACH2_SA_8197F << BIT_SHIFT_DDMACH2_SA_8197F) #define BIT_CLEAR_DDMACH2_SA_8197F(x) ((x) & (~BITS_DDMACH2_SA_8197F)) -#define BIT_GET_DDMACH2_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8197F) & BIT_MASK_DDMACH2_SA_8197F) -#define BIT_SET_DDMACH2_SA_8197F(x, v) (BIT_CLEAR_DDMACH2_SA_8197F(x) | BIT_DDMACH2_SA_8197F(v)) - +#define BIT_GET_DDMACH2_SA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH2_SA_8197F) & BIT_MASK_DDMACH2_SA_8197F) +#define BIT_SET_DDMACH2_SA_8197F(x, v) \ + (BIT_CLEAR_DDMACH2_SA_8197F(x) | BIT_DDMACH2_SA_8197F(v)) /* 2 REG_DDMA_CH2DA_8197F */ #define BIT_SHIFT_DDMACH2_DA_8197F 0 #define BIT_MASK_DDMACH2_DA_8197F 0xffffffffL -#define BIT_DDMACH2_DA_8197F(x) (((x) & BIT_MASK_DDMACH2_DA_8197F) << BIT_SHIFT_DDMACH2_DA_8197F) -#define BITS_DDMACH2_DA_8197F (BIT_MASK_DDMACH2_DA_8197F << BIT_SHIFT_DDMACH2_DA_8197F) +#define BIT_DDMACH2_DA_8197F(x) \ + (((x) & BIT_MASK_DDMACH2_DA_8197F) << BIT_SHIFT_DDMACH2_DA_8197F) +#define BITS_DDMACH2_DA_8197F \ + (BIT_MASK_DDMACH2_DA_8197F << BIT_SHIFT_DDMACH2_DA_8197F) #define BIT_CLEAR_DDMACH2_DA_8197F(x) ((x) & (~BITS_DDMACH2_DA_8197F)) -#define BIT_GET_DDMACH2_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8197F) & BIT_MASK_DDMACH2_DA_8197F) -#define BIT_SET_DDMACH2_DA_8197F(x, v) (BIT_CLEAR_DDMACH2_DA_8197F(x) | BIT_DDMACH2_DA_8197F(v)) - +#define BIT_GET_DDMACH2_DA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DA_8197F) & BIT_MASK_DDMACH2_DA_8197F) +#define BIT_SET_DDMACH2_DA_8197F(x, v) \ + (BIT_CLEAR_DDMACH2_DA_8197F(x) | BIT_DDMACH2_DA_8197F(v)) /* 2 REG_DDMA_CH2CTRL_8197F */ #define BIT_DDMACH2_OWN_8197F BIT(31) @@ -4669,34 +5839,43 @@ #define BIT_SHIFT_DDMACH2_DLEN_8197F 0 #define BIT_MASK_DDMACH2_DLEN_8197F 0x3ffff -#define BIT_DDMACH2_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH2_DLEN_8197F) << BIT_SHIFT_DDMACH2_DLEN_8197F) -#define BITS_DDMACH2_DLEN_8197F (BIT_MASK_DDMACH2_DLEN_8197F << BIT_SHIFT_DDMACH2_DLEN_8197F) +#define BIT_DDMACH2_DLEN_8197F(x) \ + (((x) & BIT_MASK_DDMACH2_DLEN_8197F) << BIT_SHIFT_DDMACH2_DLEN_8197F) +#define BITS_DDMACH2_DLEN_8197F \ + (BIT_MASK_DDMACH2_DLEN_8197F << BIT_SHIFT_DDMACH2_DLEN_8197F) #define BIT_CLEAR_DDMACH2_DLEN_8197F(x) ((x) & (~BITS_DDMACH2_DLEN_8197F)) -#define BIT_GET_DDMACH2_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8197F) & BIT_MASK_DDMACH2_DLEN_8197F) -#define BIT_SET_DDMACH2_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH2_DLEN_8197F(x) | BIT_DDMACH2_DLEN_8197F(v)) - +#define BIT_GET_DDMACH2_DLEN_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DLEN_8197F) & BIT_MASK_DDMACH2_DLEN_8197F) +#define BIT_SET_DDMACH2_DLEN_8197F(x, v) \ + (BIT_CLEAR_DDMACH2_DLEN_8197F(x) | BIT_DDMACH2_DLEN_8197F(v)) /* 2 REG_DDMA_CH3SA_8197F */ #define BIT_SHIFT_DDMACH3_SA_8197F 0 #define BIT_MASK_DDMACH3_SA_8197F 0xffffffffL -#define BIT_DDMACH3_SA_8197F(x) (((x) & BIT_MASK_DDMACH3_SA_8197F) << BIT_SHIFT_DDMACH3_SA_8197F) -#define BITS_DDMACH3_SA_8197F (BIT_MASK_DDMACH3_SA_8197F << BIT_SHIFT_DDMACH3_SA_8197F) +#define BIT_DDMACH3_SA_8197F(x) \ + (((x) & BIT_MASK_DDMACH3_SA_8197F) << BIT_SHIFT_DDMACH3_SA_8197F) +#define BITS_DDMACH3_SA_8197F \ + (BIT_MASK_DDMACH3_SA_8197F << BIT_SHIFT_DDMACH3_SA_8197F) #define BIT_CLEAR_DDMACH3_SA_8197F(x) ((x) & (~BITS_DDMACH3_SA_8197F)) -#define BIT_GET_DDMACH3_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8197F) & BIT_MASK_DDMACH3_SA_8197F) -#define BIT_SET_DDMACH3_SA_8197F(x, v) (BIT_CLEAR_DDMACH3_SA_8197F(x) | BIT_DDMACH3_SA_8197F(v)) - +#define BIT_GET_DDMACH3_SA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH3_SA_8197F) & BIT_MASK_DDMACH3_SA_8197F) +#define BIT_SET_DDMACH3_SA_8197F(x, v) \ + (BIT_CLEAR_DDMACH3_SA_8197F(x) | BIT_DDMACH3_SA_8197F(v)) /* 2 REG_DDMA_CH3DA_8197F */ #define BIT_SHIFT_DDMACH3_DA_8197F 0 #define BIT_MASK_DDMACH3_DA_8197F 0xffffffffL -#define BIT_DDMACH3_DA_8197F(x) (((x) & BIT_MASK_DDMACH3_DA_8197F) << BIT_SHIFT_DDMACH3_DA_8197F) -#define BITS_DDMACH3_DA_8197F (BIT_MASK_DDMACH3_DA_8197F << BIT_SHIFT_DDMACH3_DA_8197F) +#define BIT_DDMACH3_DA_8197F(x) \ + (((x) & BIT_MASK_DDMACH3_DA_8197F) << BIT_SHIFT_DDMACH3_DA_8197F) +#define BITS_DDMACH3_DA_8197F \ + (BIT_MASK_DDMACH3_DA_8197F << BIT_SHIFT_DDMACH3_DA_8197F) #define BIT_CLEAR_DDMACH3_DA_8197F(x) ((x) & (~BITS_DDMACH3_DA_8197F)) -#define BIT_GET_DDMACH3_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8197F) & BIT_MASK_DDMACH3_DA_8197F) -#define BIT_SET_DDMACH3_DA_8197F(x, v) (BIT_CLEAR_DDMACH3_DA_8197F(x) | BIT_DDMACH3_DA_8197F(v)) - +#define BIT_GET_DDMACH3_DA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DA_8197F) & BIT_MASK_DDMACH3_DA_8197F) +#define BIT_SET_DDMACH3_DA_8197F(x, v) \ + (BIT_CLEAR_DDMACH3_DA_8197F(x) | BIT_DDMACH3_DA_8197F(v)) /* 2 REG_DDMA_CH3CTRL_8197F */ #define BIT_DDMACH3_OWN_8197F BIT(31) @@ -4709,34 +5888,43 @@ #define BIT_SHIFT_DDMACH3_DLEN_8197F 0 #define BIT_MASK_DDMACH3_DLEN_8197F 0x3ffff -#define BIT_DDMACH3_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH3_DLEN_8197F) << BIT_SHIFT_DDMACH3_DLEN_8197F) -#define BITS_DDMACH3_DLEN_8197F (BIT_MASK_DDMACH3_DLEN_8197F << BIT_SHIFT_DDMACH3_DLEN_8197F) +#define BIT_DDMACH3_DLEN_8197F(x) \ + (((x) & BIT_MASK_DDMACH3_DLEN_8197F) << BIT_SHIFT_DDMACH3_DLEN_8197F) +#define BITS_DDMACH3_DLEN_8197F \ + (BIT_MASK_DDMACH3_DLEN_8197F << BIT_SHIFT_DDMACH3_DLEN_8197F) #define BIT_CLEAR_DDMACH3_DLEN_8197F(x) ((x) & (~BITS_DDMACH3_DLEN_8197F)) -#define BIT_GET_DDMACH3_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8197F) & BIT_MASK_DDMACH3_DLEN_8197F) -#define BIT_SET_DDMACH3_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH3_DLEN_8197F(x) | BIT_DDMACH3_DLEN_8197F(v)) - +#define BIT_GET_DDMACH3_DLEN_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DLEN_8197F) & BIT_MASK_DDMACH3_DLEN_8197F) +#define BIT_SET_DDMACH3_DLEN_8197F(x, v) \ + (BIT_CLEAR_DDMACH3_DLEN_8197F(x) | BIT_DDMACH3_DLEN_8197F(v)) /* 2 REG_DDMA_CH4SA_8197F */ #define BIT_SHIFT_DDMACH4_SA_8197F 0 #define BIT_MASK_DDMACH4_SA_8197F 0xffffffffL -#define BIT_DDMACH4_SA_8197F(x) (((x) & BIT_MASK_DDMACH4_SA_8197F) << BIT_SHIFT_DDMACH4_SA_8197F) -#define BITS_DDMACH4_SA_8197F (BIT_MASK_DDMACH4_SA_8197F << BIT_SHIFT_DDMACH4_SA_8197F) +#define BIT_DDMACH4_SA_8197F(x) \ + (((x) & BIT_MASK_DDMACH4_SA_8197F) << BIT_SHIFT_DDMACH4_SA_8197F) +#define BITS_DDMACH4_SA_8197F \ + (BIT_MASK_DDMACH4_SA_8197F << BIT_SHIFT_DDMACH4_SA_8197F) #define BIT_CLEAR_DDMACH4_SA_8197F(x) ((x) & (~BITS_DDMACH4_SA_8197F)) -#define BIT_GET_DDMACH4_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8197F) & BIT_MASK_DDMACH4_SA_8197F) -#define BIT_SET_DDMACH4_SA_8197F(x, v) (BIT_CLEAR_DDMACH4_SA_8197F(x) | BIT_DDMACH4_SA_8197F(v)) - +#define BIT_GET_DDMACH4_SA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH4_SA_8197F) & BIT_MASK_DDMACH4_SA_8197F) +#define BIT_SET_DDMACH4_SA_8197F(x, v) \ + (BIT_CLEAR_DDMACH4_SA_8197F(x) | BIT_DDMACH4_SA_8197F(v)) /* 2 REG_DDMA_CH4DA_8197F */ #define BIT_SHIFT_DDMACH4_DA_8197F 0 #define BIT_MASK_DDMACH4_DA_8197F 0xffffffffL -#define BIT_DDMACH4_DA_8197F(x) (((x) & BIT_MASK_DDMACH4_DA_8197F) << BIT_SHIFT_DDMACH4_DA_8197F) -#define BITS_DDMACH4_DA_8197F (BIT_MASK_DDMACH4_DA_8197F << BIT_SHIFT_DDMACH4_DA_8197F) +#define BIT_DDMACH4_DA_8197F(x) \ + (((x) & BIT_MASK_DDMACH4_DA_8197F) << BIT_SHIFT_DDMACH4_DA_8197F) +#define BITS_DDMACH4_DA_8197F \ + (BIT_MASK_DDMACH4_DA_8197F << BIT_SHIFT_DDMACH4_DA_8197F) #define BIT_CLEAR_DDMACH4_DA_8197F(x) ((x) & (~BITS_DDMACH4_DA_8197F)) -#define BIT_GET_DDMACH4_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8197F) & BIT_MASK_DDMACH4_DA_8197F) -#define BIT_SET_DDMACH4_DA_8197F(x, v) (BIT_CLEAR_DDMACH4_DA_8197F(x) | BIT_DDMACH4_DA_8197F(v)) - +#define BIT_GET_DDMACH4_DA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DA_8197F) & BIT_MASK_DDMACH4_DA_8197F) +#define BIT_SET_DDMACH4_DA_8197F(x, v) \ + (BIT_CLEAR_DDMACH4_DA_8197F(x) | BIT_DDMACH4_DA_8197F(v)) /* 2 REG_DDMA_CH4CTRL_8197F */ #define BIT_DDMACH4_OWN_8197F BIT(31) @@ -4749,34 +5937,43 @@ #define BIT_SHIFT_DDMACH4_DLEN_8197F 0 #define BIT_MASK_DDMACH4_DLEN_8197F 0x3ffff -#define BIT_DDMACH4_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH4_DLEN_8197F) << BIT_SHIFT_DDMACH4_DLEN_8197F) -#define BITS_DDMACH4_DLEN_8197F (BIT_MASK_DDMACH4_DLEN_8197F << BIT_SHIFT_DDMACH4_DLEN_8197F) +#define BIT_DDMACH4_DLEN_8197F(x) \ + (((x) & BIT_MASK_DDMACH4_DLEN_8197F) << BIT_SHIFT_DDMACH4_DLEN_8197F) +#define BITS_DDMACH4_DLEN_8197F \ + (BIT_MASK_DDMACH4_DLEN_8197F << BIT_SHIFT_DDMACH4_DLEN_8197F) #define BIT_CLEAR_DDMACH4_DLEN_8197F(x) ((x) & (~BITS_DDMACH4_DLEN_8197F)) -#define BIT_GET_DDMACH4_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8197F) & BIT_MASK_DDMACH4_DLEN_8197F) -#define BIT_SET_DDMACH4_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH4_DLEN_8197F(x) | BIT_DDMACH4_DLEN_8197F(v)) - +#define BIT_GET_DDMACH4_DLEN_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DLEN_8197F) & BIT_MASK_DDMACH4_DLEN_8197F) +#define BIT_SET_DDMACH4_DLEN_8197F(x, v) \ + (BIT_CLEAR_DDMACH4_DLEN_8197F(x) | BIT_DDMACH4_DLEN_8197F(v)) /* 2 REG_DDMA_CH5SA_8197F */ #define BIT_SHIFT_DDMACH5_SA_8197F 0 #define BIT_MASK_DDMACH5_SA_8197F 0xffffffffL -#define BIT_DDMACH5_SA_8197F(x) (((x) & BIT_MASK_DDMACH5_SA_8197F) << BIT_SHIFT_DDMACH5_SA_8197F) -#define BITS_DDMACH5_SA_8197F (BIT_MASK_DDMACH5_SA_8197F << BIT_SHIFT_DDMACH5_SA_8197F) +#define BIT_DDMACH5_SA_8197F(x) \ + (((x) & BIT_MASK_DDMACH5_SA_8197F) << BIT_SHIFT_DDMACH5_SA_8197F) +#define BITS_DDMACH5_SA_8197F \ + (BIT_MASK_DDMACH5_SA_8197F << BIT_SHIFT_DDMACH5_SA_8197F) #define BIT_CLEAR_DDMACH5_SA_8197F(x) ((x) & (~BITS_DDMACH5_SA_8197F)) -#define BIT_GET_DDMACH5_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8197F) & BIT_MASK_DDMACH5_SA_8197F) -#define BIT_SET_DDMACH5_SA_8197F(x, v) (BIT_CLEAR_DDMACH5_SA_8197F(x) | BIT_DDMACH5_SA_8197F(v)) - +#define BIT_GET_DDMACH5_SA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH5_SA_8197F) & BIT_MASK_DDMACH5_SA_8197F) +#define BIT_SET_DDMACH5_SA_8197F(x, v) \ + (BIT_CLEAR_DDMACH5_SA_8197F(x) | BIT_DDMACH5_SA_8197F(v)) /* 2 REG_DDMA_CH5DA_8197F */ #define BIT_SHIFT_DDMACH5_DA_8197F 0 #define BIT_MASK_DDMACH5_DA_8197F 0xffffffffL -#define BIT_DDMACH5_DA_8197F(x) (((x) & BIT_MASK_DDMACH5_DA_8197F) << BIT_SHIFT_DDMACH5_DA_8197F) -#define BITS_DDMACH5_DA_8197F (BIT_MASK_DDMACH5_DA_8197F << BIT_SHIFT_DDMACH5_DA_8197F) +#define BIT_DDMACH5_DA_8197F(x) \ + (((x) & BIT_MASK_DDMACH5_DA_8197F) << BIT_SHIFT_DDMACH5_DA_8197F) +#define BITS_DDMACH5_DA_8197F \ + (BIT_MASK_DDMACH5_DA_8197F << BIT_SHIFT_DDMACH5_DA_8197F) #define BIT_CLEAR_DDMACH5_DA_8197F(x) ((x) & (~BITS_DDMACH5_DA_8197F)) -#define BIT_GET_DDMACH5_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8197F) & BIT_MASK_DDMACH5_DA_8197F) -#define BIT_SET_DDMACH5_DA_8197F(x, v) (BIT_CLEAR_DDMACH5_DA_8197F(x) | BIT_DDMACH5_DA_8197F(v)) - +#define BIT_GET_DDMACH5_DA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DA_8197F) & BIT_MASK_DDMACH5_DA_8197F) +#define BIT_SET_DDMACH5_DA_8197F(x, v) \ + (BIT_CLEAR_DDMACH5_DA_8197F(x) | BIT_DDMACH5_DA_8197F(v)) /* 2 REG_REG_DDMA_CH5CTRL_8197F */ #define BIT_DDMACH5_OWN_8197F BIT(31) @@ -4789,12 +5986,15 @@ #define BIT_SHIFT_DDMACH5_DLEN_8197F 0 #define BIT_MASK_DDMACH5_DLEN_8197F 0x3ffff -#define BIT_DDMACH5_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH5_DLEN_8197F) << BIT_SHIFT_DDMACH5_DLEN_8197F) -#define BITS_DDMACH5_DLEN_8197F (BIT_MASK_DDMACH5_DLEN_8197F << BIT_SHIFT_DDMACH5_DLEN_8197F) +#define BIT_DDMACH5_DLEN_8197F(x) \ + (((x) & BIT_MASK_DDMACH5_DLEN_8197F) << BIT_SHIFT_DDMACH5_DLEN_8197F) +#define BITS_DDMACH5_DLEN_8197F \ + (BIT_MASK_DDMACH5_DLEN_8197F << BIT_SHIFT_DDMACH5_DLEN_8197F) #define BIT_CLEAR_DDMACH5_DLEN_8197F(x) ((x) & (~BITS_DDMACH5_DLEN_8197F)) -#define BIT_GET_DDMACH5_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8197F) & BIT_MASK_DDMACH5_DLEN_8197F) -#define BIT_SET_DDMACH5_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH5_DLEN_8197F(x) | BIT_DDMACH5_DLEN_8197F(v)) - +#define BIT_GET_DDMACH5_DLEN_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DLEN_8197F) & BIT_MASK_DDMACH5_DLEN_8197F) +#define BIT_SET_DDMACH5_DLEN_8197F(x, v) \ + (BIT_CLEAR_DDMACH5_DLEN_8197F(x) | BIT_DDMACH5_DLEN_8197F(v)) /* 2 REG_DDMA_INT_MSK_8197F */ #define BIT_DDMACH5_MSK_8197F BIT(5) @@ -4816,12 +6016,15 @@ #define BIT_SHIFT_IDDMA0_CHKSUM_8197F 0 #define BIT_MASK_IDDMA0_CHKSUM_8197F 0xffff -#define BIT_IDDMA0_CHKSUM_8197F(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8197F) << BIT_SHIFT_IDDMA0_CHKSUM_8197F) -#define BITS_IDDMA0_CHKSUM_8197F (BIT_MASK_IDDMA0_CHKSUM_8197F << BIT_SHIFT_IDDMA0_CHKSUM_8197F) +#define BIT_IDDMA0_CHKSUM_8197F(x) \ + (((x) & BIT_MASK_IDDMA0_CHKSUM_8197F) << BIT_SHIFT_IDDMA0_CHKSUM_8197F) +#define BITS_IDDMA0_CHKSUM_8197F \ + (BIT_MASK_IDDMA0_CHKSUM_8197F << BIT_SHIFT_IDDMA0_CHKSUM_8197F) #define BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) ((x) & (~BITS_IDDMA0_CHKSUM_8197F)) -#define BIT_GET_IDDMA0_CHKSUM_8197F(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8197F) & BIT_MASK_IDDMA0_CHKSUM_8197F) -#define BIT_SET_IDDMA0_CHKSUM_8197F(x, v) (BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) | BIT_IDDMA0_CHKSUM_8197F(v)) - +#define BIT_GET_IDDMA0_CHKSUM_8197F(x) \ + (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8197F) & BIT_MASK_IDDMA0_CHKSUM_8197F) +#define BIT_SET_IDDMA0_CHKSUM_8197F(x, v) \ + (BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) | BIT_IDDMA0_CHKSUM_8197F(v)) /* 2 REG_DDMA_MONITOR_8197F */ #define BIT_IDDMA0_PERMU_UNDERFLOW_8197F BIT(14) @@ -4841,21 +6044,29 @@ #define BIT_SHIFT_HCI_MAX_RXDMA_8197F 28 #define BIT_MASK_HCI_MAX_RXDMA_8197F 0x7 -#define BIT_HCI_MAX_RXDMA_8197F(x) (((x) & BIT_MASK_HCI_MAX_RXDMA_8197F) << BIT_SHIFT_HCI_MAX_RXDMA_8197F) -#define BITS_HCI_MAX_RXDMA_8197F (BIT_MASK_HCI_MAX_RXDMA_8197F << BIT_SHIFT_HCI_MAX_RXDMA_8197F) +#define BIT_HCI_MAX_RXDMA_8197F(x) \ + (((x) & BIT_MASK_HCI_MAX_RXDMA_8197F) << BIT_SHIFT_HCI_MAX_RXDMA_8197F) +#define BITS_HCI_MAX_RXDMA_8197F \ + (BIT_MASK_HCI_MAX_RXDMA_8197F << BIT_SHIFT_HCI_MAX_RXDMA_8197F) #define BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) ((x) & (~BITS_HCI_MAX_RXDMA_8197F)) -#define BIT_GET_HCI_MAX_RXDMA_8197F(x) (((x) >> BIT_SHIFT_HCI_MAX_RXDMA_8197F) & BIT_MASK_HCI_MAX_RXDMA_8197F) -#define BIT_SET_HCI_MAX_RXDMA_8197F(x, v) (BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) | BIT_HCI_MAX_RXDMA_8197F(v)) +#define BIT_GET_HCI_MAX_RXDMA_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_MAX_RXDMA_8197F) & BIT_MASK_HCI_MAX_RXDMA_8197F) +#define BIT_SET_HCI_MAX_RXDMA_8197F(x, v) \ + (BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) | BIT_HCI_MAX_RXDMA_8197F(v)) #define BIT_MULRW_8197F BIT(27) #define BIT_SHIFT_HCI_MAX_TXDMA_8197F 24 #define BIT_MASK_HCI_MAX_TXDMA_8197F 0x7 -#define BIT_HCI_MAX_TXDMA_8197F(x) (((x) & BIT_MASK_HCI_MAX_TXDMA_8197F) << BIT_SHIFT_HCI_MAX_TXDMA_8197F) -#define BITS_HCI_MAX_TXDMA_8197F (BIT_MASK_HCI_MAX_TXDMA_8197F << BIT_SHIFT_HCI_MAX_TXDMA_8197F) +#define BIT_HCI_MAX_TXDMA_8197F(x) \ + (((x) & BIT_MASK_HCI_MAX_TXDMA_8197F) << BIT_SHIFT_HCI_MAX_TXDMA_8197F) +#define BITS_HCI_MAX_TXDMA_8197F \ + (BIT_MASK_HCI_MAX_TXDMA_8197F << BIT_SHIFT_HCI_MAX_TXDMA_8197F) #define BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) ((x) & (~BITS_HCI_MAX_TXDMA_8197F)) -#define BIT_GET_HCI_MAX_TXDMA_8197F(x) (((x) >> BIT_SHIFT_HCI_MAX_TXDMA_8197F) & BIT_MASK_HCI_MAX_TXDMA_8197F) -#define BIT_SET_HCI_MAX_TXDMA_8197F(x, v) (BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) | BIT_HCI_MAX_TXDMA_8197F(v)) +#define BIT_GET_HCI_MAX_TXDMA_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_MAX_TXDMA_8197F) & BIT_MASK_HCI_MAX_TXDMA_8197F) +#define BIT_SET_HCI_MAX_TXDMA_8197F(x, v) \ + (BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) | BIT_HCI_MAX_TXDMA_8197F(v)) #define BIT_EN_CPL_TIMEOUT_PS_8197F BIT(22) #define BIT_REG_TXDMA_FAIL_PS_8197F BIT(21) @@ -4885,528 +6096,729 @@ #define BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F 28 #define BIT_MASK_TXTTIMER_MATCH_NUM_8197F 0xf -#define BIT_TXTTIMER_MATCH_NUM_8197F(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8197F) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) -#define BITS_TXTTIMER_MATCH_NUM_8197F (BIT_MASK_TXTTIMER_MATCH_NUM_8197F << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) -#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) ((x) & (~BITS_TXTTIMER_MATCH_NUM_8197F)) -#define BIT_GET_TXTTIMER_MATCH_NUM_8197F(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) & BIT_MASK_TXTTIMER_MATCH_NUM_8197F) -#define BIT_SET_TXTTIMER_MATCH_NUM_8197F(x, v) (BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) | BIT_TXTTIMER_MATCH_NUM_8197F(v)) - +#define BIT_TXTTIMER_MATCH_NUM_8197F(x) \ + (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8197F) \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) +#define BITS_TXTTIMER_MATCH_NUM_8197F \ + (BIT_MASK_TXTTIMER_MATCH_NUM_8197F \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) +#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) \ + ((x) & (~BITS_TXTTIMER_MATCH_NUM_8197F)) +#define BIT_GET_TXTTIMER_MATCH_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) & \ + BIT_MASK_TXTTIMER_MATCH_NUM_8197F) +#define BIT_SET_TXTTIMER_MATCH_NUM_8197F(x, v) \ + (BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) | \ + BIT_TXTTIMER_MATCH_NUM_8197F(v)) #define BIT_SHIFT_TXPKT_NUM_MATCH_8197F 24 #define BIT_MASK_TXPKT_NUM_MATCH_8197F 0xf -#define BIT_TXPKT_NUM_MATCH_8197F(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8197F) << BIT_SHIFT_TXPKT_NUM_MATCH_8197F) -#define BITS_TXPKT_NUM_MATCH_8197F (BIT_MASK_TXPKT_NUM_MATCH_8197F << BIT_SHIFT_TXPKT_NUM_MATCH_8197F) +#define BIT_TXPKT_NUM_MATCH_8197F(x) \ + (((x) & BIT_MASK_TXPKT_NUM_MATCH_8197F) \ + << BIT_SHIFT_TXPKT_NUM_MATCH_8197F) +#define BITS_TXPKT_NUM_MATCH_8197F \ + (BIT_MASK_TXPKT_NUM_MATCH_8197F << BIT_SHIFT_TXPKT_NUM_MATCH_8197F) #define BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8197F)) -#define BIT_GET_TXPKT_NUM_MATCH_8197F(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8197F) & BIT_MASK_TXPKT_NUM_MATCH_8197F) -#define BIT_SET_TXPKT_NUM_MATCH_8197F(x, v) (BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) | BIT_TXPKT_NUM_MATCH_8197F(v)) - +#define BIT_GET_TXPKT_NUM_MATCH_8197F(x) \ + (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8197F) & \ + BIT_MASK_TXPKT_NUM_MATCH_8197F) +#define BIT_SET_TXPKT_NUM_MATCH_8197F(x, v) \ + (BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) | BIT_TXPKT_NUM_MATCH_8197F(v)) #define BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F 20 #define BIT_MASK_RXTTIMER_MATCH_NUM_8197F 0xf -#define BIT_RXTTIMER_MATCH_NUM_8197F(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8197F) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) -#define BITS_RXTTIMER_MATCH_NUM_8197F (BIT_MASK_RXTTIMER_MATCH_NUM_8197F << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) -#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) ((x) & (~BITS_RXTTIMER_MATCH_NUM_8197F)) -#define BIT_GET_RXTTIMER_MATCH_NUM_8197F(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) & BIT_MASK_RXTTIMER_MATCH_NUM_8197F) -#define BIT_SET_RXTTIMER_MATCH_NUM_8197F(x, v) (BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) | BIT_RXTTIMER_MATCH_NUM_8197F(v)) - +#define BIT_RXTTIMER_MATCH_NUM_8197F(x) \ + (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8197F) \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) +#define BITS_RXTTIMER_MATCH_NUM_8197F \ + (BIT_MASK_RXTTIMER_MATCH_NUM_8197F \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) +#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) \ + ((x) & (~BITS_RXTTIMER_MATCH_NUM_8197F)) +#define BIT_GET_RXTTIMER_MATCH_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) & \ + BIT_MASK_RXTTIMER_MATCH_NUM_8197F) +#define BIT_SET_RXTTIMER_MATCH_NUM_8197F(x, v) \ + (BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) | \ + BIT_RXTTIMER_MATCH_NUM_8197F(v)) #define BIT_SHIFT_RXPKT_NUM_MATCH_8197F 16 #define BIT_MASK_RXPKT_NUM_MATCH_8197F 0xf -#define BIT_RXPKT_NUM_MATCH_8197F(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8197F) << BIT_SHIFT_RXPKT_NUM_MATCH_8197F) -#define BITS_RXPKT_NUM_MATCH_8197F (BIT_MASK_RXPKT_NUM_MATCH_8197F << BIT_SHIFT_RXPKT_NUM_MATCH_8197F) +#define BIT_RXPKT_NUM_MATCH_8197F(x) \ + (((x) & BIT_MASK_RXPKT_NUM_MATCH_8197F) \ + << BIT_SHIFT_RXPKT_NUM_MATCH_8197F) +#define BITS_RXPKT_NUM_MATCH_8197F \ + (BIT_MASK_RXPKT_NUM_MATCH_8197F << BIT_SHIFT_RXPKT_NUM_MATCH_8197F) #define BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8197F)) -#define BIT_GET_RXPKT_NUM_MATCH_8197F(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8197F) & BIT_MASK_RXPKT_NUM_MATCH_8197F) -#define BIT_SET_RXPKT_NUM_MATCH_8197F(x, v) (BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) | BIT_RXPKT_NUM_MATCH_8197F(v)) - +#define BIT_GET_RXPKT_NUM_MATCH_8197F(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8197F) & \ + BIT_MASK_RXPKT_NUM_MATCH_8197F) +#define BIT_SET_RXPKT_NUM_MATCH_8197F(x, v) \ + (BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) | BIT_RXPKT_NUM_MATCH_8197F(v)) #define BIT_SHIFT_MIGRATE_TIMER_8197F 0 #define BIT_MASK_MIGRATE_TIMER_8197F 0xffff -#define BIT_MIGRATE_TIMER_8197F(x) (((x) & BIT_MASK_MIGRATE_TIMER_8197F) << BIT_SHIFT_MIGRATE_TIMER_8197F) -#define BITS_MIGRATE_TIMER_8197F (BIT_MASK_MIGRATE_TIMER_8197F << BIT_SHIFT_MIGRATE_TIMER_8197F) +#define BIT_MIGRATE_TIMER_8197F(x) \ + (((x) & BIT_MASK_MIGRATE_TIMER_8197F) << BIT_SHIFT_MIGRATE_TIMER_8197F) +#define BITS_MIGRATE_TIMER_8197F \ + (BIT_MASK_MIGRATE_TIMER_8197F << BIT_SHIFT_MIGRATE_TIMER_8197F) #define BIT_CLEAR_MIGRATE_TIMER_8197F(x) ((x) & (~BITS_MIGRATE_TIMER_8197F)) -#define BIT_GET_MIGRATE_TIMER_8197F(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8197F) & BIT_MASK_MIGRATE_TIMER_8197F) -#define BIT_SET_MIGRATE_TIMER_8197F(x, v) (BIT_CLEAR_MIGRATE_TIMER_8197F(x) | BIT_MIGRATE_TIMER_8197F(v)) - +#define BIT_GET_MIGRATE_TIMER_8197F(x) \ + (((x) >> BIT_SHIFT_MIGRATE_TIMER_8197F) & BIT_MASK_MIGRATE_TIMER_8197F) +#define BIT_SET_MIGRATE_TIMER_8197F(x, v) \ + (BIT_CLEAR_MIGRATE_TIMER_8197F(x) | BIT_MIGRATE_TIMER_8197F(v)) /* 2 REG_BCNQ_TXBD_DESA_8197F */ #define BIT_SHIFT_BCNQ_TXBD_DESA_8197F 0 #define BIT_MASK_BCNQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_BCNQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8197F) << BIT_SHIFT_BCNQ_TXBD_DESA_8197F) -#define BITS_BCNQ_TXBD_DESA_8197F (BIT_MASK_BCNQ_TXBD_DESA_8197F << BIT_SHIFT_BCNQ_TXBD_DESA_8197F) +#define BIT_BCNQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_BCNQ_TXBD_DESA_8197F) \ + << BIT_SHIFT_BCNQ_TXBD_DESA_8197F) +#define BITS_BCNQ_TXBD_DESA_8197F \ + (BIT_MASK_BCNQ_TXBD_DESA_8197F << BIT_SHIFT_BCNQ_TXBD_DESA_8197F) #define BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8197F)) -#define BIT_GET_BCNQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8197F) & BIT_MASK_BCNQ_TXBD_DESA_8197F) -#define BIT_SET_BCNQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) | BIT_BCNQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_BCNQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8197F) & \ + BIT_MASK_BCNQ_TXBD_DESA_8197F) +#define BIT_SET_BCNQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) | BIT_BCNQ_TXBD_DESA_8197F(v)) /* 2 REG_MGQ_TXBD_DESA_8197F */ #define BIT_SHIFT_MGQ_TXBD_DESA_8197F 0 #define BIT_MASK_MGQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_MGQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8197F) << BIT_SHIFT_MGQ_TXBD_DESA_8197F) -#define BITS_MGQ_TXBD_DESA_8197F (BIT_MASK_MGQ_TXBD_DESA_8197F << BIT_SHIFT_MGQ_TXBD_DESA_8197F) +#define BIT_MGQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_MGQ_TXBD_DESA_8197F) << BIT_SHIFT_MGQ_TXBD_DESA_8197F) +#define BITS_MGQ_TXBD_DESA_8197F \ + (BIT_MASK_MGQ_TXBD_DESA_8197F << BIT_SHIFT_MGQ_TXBD_DESA_8197F) #define BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) ((x) & (~BITS_MGQ_TXBD_DESA_8197F)) -#define BIT_GET_MGQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8197F) & BIT_MASK_MGQ_TXBD_DESA_8197F) -#define BIT_SET_MGQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) | BIT_MGQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_MGQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8197F) & BIT_MASK_MGQ_TXBD_DESA_8197F) +#define BIT_SET_MGQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) | BIT_MGQ_TXBD_DESA_8197F(v)) /* 2 REG_VOQ_TXBD_DESA_8197F */ #define BIT_SHIFT_VOQ_TXBD_DESA_8197F 0 #define BIT_MASK_VOQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_VOQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8197F) << BIT_SHIFT_VOQ_TXBD_DESA_8197F) -#define BITS_VOQ_TXBD_DESA_8197F (BIT_MASK_VOQ_TXBD_DESA_8197F << BIT_SHIFT_VOQ_TXBD_DESA_8197F) +#define BIT_VOQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_VOQ_TXBD_DESA_8197F) << BIT_SHIFT_VOQ_TXBD_DESA_8197F) +#define BITS_VOQ_TXBD_DESA_8197F \ + (BIT_MASK_VOQ_TXBD_DESA_8197F << BIT_SHIFT_VOQ_TXBD_DESA_8197F) #define BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) ((x) & (~BITS_VOQ_TXBD_DESA_8197F)) -#define BIT_GET_VOQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8197F) & BIT_MASK_VOQ_TXBD_DESA_8197F) -#define BIT_SET_VOQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) | BIT_VOQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_VOQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8197F) & BIT_MASK_VOQ_TXBD_DESA_8197F) +#define BIT_SET_VOQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) | BIT_VOQ_TXBD_DESA_8197F(v)) /* 2 REG_VIQ_TXBD_DESA_8197F */ #define BIT_SHIFT_VIQ_TXBD_DESA_8197F 0 #define BIT_MASK_VIQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_VIQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8197F) << BIT_SHIFT_VIQ_TXBD_DESA_8197F) -#define BITS_VIQ_TXBD_DESA_8197F (BIT_MASK_VIQ_TXBD_DESA_8197F << BIT_SHIFT_VIQ_TXBD_DESA_8197F) +#define BIT_VIQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_VIQ_TXBD_DESA_8197F) << BIT_SHIFT_VIQ_TXBD_DESA_8197F) +#define BITS_VIQ_TXBD_DESA_8197F \ + (BIT_MASK_VIQ_TXBD_DESA_8197F << BIT_SHIFT_VIQ_TXBD_DESA_8197F) #define BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) ((x) & (~BITS_VIQ_TXBD_DESA_8197F)) -#define BIT_GET_VIQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8197F) & BIT_MASK_VIQ_TXBD_DESA_8197F) -#define BIT_SET_VIQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) | BIT_VIQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_VIQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8197F) & BIT_MASK_VIQ_TXBD_DESA_8197F) +#define BIT_SET_VIQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) | BIT_VIQ_TXBD_DESA_8197F(v)) /* 2 REG_BEQ_TXBD_DESA_8197F */ #define BIT_SHIFT_BEQ_TXBD_DESA_8197F 0 #define BIT_MASK_BEQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_BEQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8197F) << BIT_SHIFT_BEQ_TXBD_DESA_8197F) -#define BITS_BEQ_TXBD_DESA_8197F (BIT_MASK_BEQ_TXBD_DESA_8197F << BIT_SHIFT_BEQ_TXBD_DESA_8197F) +#define BIT_BEQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_BEQ_TXBD_DESA_8197F) << BIT_SHIFT_BEQ_TXBD_DESA_8197F) +#define BITS_BEQ_TXBD_DESA_8197F \ + (BIT_MASK_BEQ_TXBD_DESA_8197F << BIT_SHIFT_BEQ_TXBD_DESA_8197F) #define BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BEQ_TXBD_DESA_8197F)) -#define BIT_GET_BEQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8197F) & BIT_MASK_BEQ_TXBD_DESA_8197F) -#define BIT_SET_BEQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) | BIT_BEQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_BEQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8197F) & BIT_MASK_BEQ_TXBD_DESA_8197F) +#define BIT_SET_BEQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) | BIT_BEQ_TXBD_DESA_8197F(v)) /* 2 REG_BKQ_TXBD_DESA_8197F */ #define BIT_SHIFT_BKQ_TXBD_DESA_8197F 0 #define BIT_MASK_BKQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_BKQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8197F) << BIT_SHIFT_BKQ_TXBD_DESA_8197F) -#define BITS_BKQ_TXBD_DESA_8197F (BIT_MASK_BKQ_TXBD_DESA_8197F << BIT_SHIFT_BKQ_TXBD_DESA_8197F) +#define BIT_BKQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_BKQ_TXBD_DESA_8197F) << BIT_SHIFT_BKQ_TXBD_DESA_8197F) +#define BITS_BKQ_TXBD_DESA_8197F \ + (BIT_MASK_BKQ_TXBD_DESA_8197F << BIT_SHIFT_BKQ_TXBD_DESA_8197F) #define BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BKQ_TXBD_DESA_8197F)) -#define BIT_GET_BKQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8197F) & BIT_MASK_BKQ_TXBD_DESA_8197F) -#define BIT_SET_BKQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) | BIT_BKQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_BKQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8197F) & BIT_MASK_BKQ_TXBD_DESA_8197F) +#define BIT_SET_BKQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) | BIT_BKQ_TXBD_DESA_8197F(v)) /* 2 REG_RXQ_RXBD_DESA_8197F */ #define BIT_SHIFT_RXQ_RXBD_DESA_8197F 0 #define BIT_MASK_RXQ_RXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_RXQ_RXBD_DESA_8197F(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8197F) << BIT_SHIFT_RXQ_RXBD_DESA_8197F) -#define BITS_RXQ_RXBD_DESA_8197F (BIT_MASK_RXQ_RXBD_DESA_8197F << BIT_SHIFT_RXQ_RXBD_DESA_8197F) +#define BIT_RXQ_RXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_RXQ_RXBD_DESA_8197F) << BIT_SHIFT_RXQ_RXBD_DESA_8197F) +#define BITS_RXQ_RXBD_DESA_8197F \ + (BIT_MASK_RXQ_RXBD_DESA_8197F << BIT_SHIFT_RXQ_RXBD_DESA_8197F) #define BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) ((x) & (~BITS_RXQ_RXBD_DESA_8197F)) -#define BIT_GET_RXQ_RXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8197F) & BIT_MASK_RXQ_RXBD_DESA_8197F) -#define BIT_SET_RXQ_RXBD_DESA_8197F(x, v) (BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) | BIT_RXQ_RXBD_DESA_8197F(v)) - +#define BIT_GET_RXQ_RXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8197F) & BIT_MASK_RXQ_RXBD_DESA_8197F) +#define BIT_SET_RXQ_RXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) | BIT_RXQ_RXBD_DESA_8197F(v)) /* 2 REG_HI0Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI0Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI0Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI0Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8197F) << BIT_SHIFT_HI0Q_TXBD_DESA_8197F) -#define BITS_HI0Q_TXBD_DESA_8197F (BIT_MASK_HI0Q_TXBD_DESA_8197F << BIT_SHIFT_HI0Q_TXBD_DESA_8197F) +#define BIT_HI0Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI0Q_TXBD_DESA_8197F) +#define BITS_HI0Q_TXBD_DESA_8197F \ + (BIT_MASK_HI0Q_TXBD_DESA_8197F << BIT_SHIFT_HI0Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8197F)) -#define BIT_GET_HI0Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8197F) & BIT_MASK_HI0Q_TXBD_DESA_8197F) -#define BIT_SET_HI0Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) | BIT_HI0Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI0Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI0Q_TXBD_DESA_8197F) +#define BIT_SET_HI0Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) | BIT_HI0Q_TXBD_DESA_8197F(v)) /* 2 REG_HI1Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI1Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI1Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI1Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8197F) << BIT_SHIFT_HI1Q_TXBD_DESA_8197F) -#define BITS_HI1Q_TXBD_DESA_8197F (BIT_MASK_HI1Q_TXBD_DESA_8197F << BIT_SHIFT_HI1Q_TXBD_DESA_8197F) +#define BIT_HI1Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI1Q_TXBD_DESA_8197F) +#define BITS_HI1Q_TXBD_DESA_8197F \ + (BIT_MASK_HI1Q_TXBD_DESA_8197F << BIT_SHIFT_HI1Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8197F)) -#define BIT_GET_HI1Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8197F) & BIT_MASK_HI1Q_TXBD_DESA_8197F) -#define BIT_SET_HI1Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) | BIT_HI1Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI1Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI1Q_TXBD_DESA_8197F) +#define BIT_SET_HI1Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) | BIT_HI1Q_TXBD_DESA_8197F(v)) /* 2 REG_HI2Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI2Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI2Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI2Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8197F) << BIT_SHIFT_HI2Q_TXBD_DESA_8197F) -#define BITS_HI2Q_TXBD_DESA_8197F (BIT_MASK_HI2Q_TXBD_DESA_8197F << BIT_SHIFT_HI2Q_TXBD_DESA_8197F) +#define BIT_HI2Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI2Q_TXBD_DESA_8197F) +#define BITS_HI2Q_TXBD_DESA_8197F \ + (BIT_MASK_HI2Q_TXBD_DESA_8197F << BIT_SHIFT_HI2Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8197F)) -#define BIT_GET_HI2Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8197F) & BIT_MASK_HI2Q_TXBD_DESA_8197F) -#define BIT_SET_HI2Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) | BIT_HI2Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI2Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI2Q_TXBD_DESA_8197F) +#define BIT_SET_HI2Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) | BIT_HI2Q_TXBD_DESA_8197F(v)) /* 2 REG_HI3Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI3Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI3Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI3Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8197F) << BIT_SHIFT_HI3Q_TXBD_DESA_8197F) -#define BITS_HI3Q_TXBD_DESA_8197F (BIT_MASK_HI3Q_TXBD_DESA_8197F << BIT_SHIFT_HI3Q_TXBD_DESA_8197F) +#define BIT_HI3Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI3Q_TXBD_DESA_8197F) +#define BITS_HI3Q_TXBD_DESA_8197F \ + (BIT_MASK_HI3Q_TXBD_DESA_8197F << BIT_SHIFT_HI3Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8197F)) -#define BIT_GET_HI3Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8197F) & BIT_MASK_HI3Q_TXBD_DESA_8197F) -#define BIT_SET_HI3Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) | BIT_HI3Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI3Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI3Q_TXBD_DESA_8197F) +#define BIT_SET_HI3Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) | BIT_HI3Q_TXBD_DESA_8197F(v)) /* 2 REG_HI4Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI4Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI4Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI4Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8197F) << BIT_SHIFT_HI4Q_TXBD_DESA_8197F) -#define BITS_HI4Q_TXBD_DESA_8197F (BIT_MASK_HI4Q_TXBD_DESA_8197F << BIT_SHIFT_HI4Q_TXBD_DESA_8197F) +#define BIT_HI4Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI4Q_TXBD_DESA_8197F) +#define BITS_HI4Q_TXBD_DESA_8197F \ + (BIT_MASK_HI4Q_TXBD_DESA_8197F << BIT_SHIFT_HI4Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8197F)) -#define BIT_GET_HI4Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8197F) & BIT_MASK_HI4Q_TXBD_DESA_8197F) -#define BIT_SET_HI4Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) | BIT_HI4Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI4Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI4Q_TXBD_DESA_8197F) +#define BIT_SET_HI4Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) | BIT_HI4Q_TXBD_DESA_8197F(v)) /* 2 REG_HI5Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI5Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI5Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI5Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8197F) << BIT_SHIFT_HI5Q_TXBD_DESA_8197F) -#define BITS_HI5Q_TXBD_DESA_8197F (BIT_MASK_HI5Q_TXBD_DESA_8197F << BIT_SHIFT_HI5Q_TXBD_DESA_8197F) +#define BIT_HI5Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI5Q_TXBD_DESA_8197F) +#define BITS_HI5Q_TXBD_DESA_8197F \ + (BIT_MASK_HI5Q_TXBD_DESA_8197F << BIT_SHIFT_HI5Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8197F)) -#define BIT_GET_HI5Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8197F) & BIT_MASK_HI5Q_TXBD_DESA_8197F) -#define BIT_SET_HI5Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) | BIT_HI5Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI5Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI5Q_TXBD_DESA_8197F) +#define BIT_SET_HI5Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) | BIT_HI5Q_TXBD_DESA_8197F(v)) /* 2 REG_HI6Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI6Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI6Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI6Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8197F) << BIT_SHIFT_HI6Q_TXBD_DESA_8197F) -#define BITS_HI6Q_TXBD_DESA_8197F (BIT_MASK_HI6Q_TXBD_DESA_8197F << BIT_SHIFT_HI6Q_TXBD_DESA_8197F) +#define BIT_HI6Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI6Q_TXBD_DESA_8197F) +#define BITS_HI6Q_TXBD_DESA_8197F \ + (BIT_MASK_HI6Q_TXBD_DESA_8197F << BIT_SHIFT_HI6Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8197F)) -#define BIT_GET_HI6Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8197F) & BIT_MASK_HI6Q_TXBD_DESA_8197F) -#define BIT_SET_HI6Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) | BIT_HI6Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI6Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI6Q_TXBD_DESA_8197F) +#define BIT_SET_HI6Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) | BIT_HI6Q_TXBD_DESA_8197F(v)) /* 2 REG_HI7Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI7Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI7Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI7Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8197F) << BIT_SHIFT_HI7Q_TXBD_DESA_8197F) -#define BITS_HI7Q_TXBD_DESA_8197F (BIT_MASK_HI7Q_TXBD_DESA_8197F << BIT_SHIFT_HI7Q_TXBD_DESA_8197F) +#define BIT_HI7Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI7Q_TXBD_DESA_8197F) +#define BITS_HI7Q_TXBD_DESA_8197F \ + (BIT_MASK_HI7Q_TXBD_DESA_8197F << BIT_SHIFT_HI7Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8197F)) -#define BIT_GET_HI7Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8197F) & BIT_MASK_HI7Q_TXBD_DESA_8197F) -#define BIT_SET_HI7Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) | BIT_HI7Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI7Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI7Q_TXBD_DESA_8197F) +#define BIT_SET_HI7Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) | BIT_HI7Q_TXBD_DESA_8197F(v)) /* 2 REG_MGQ_TXBD_NUM_8197F */ #define BIT_HCI_MGQ_FLAG_8197F BIT(14) #define BIT_SHIFT_MGQ_DESC_MODE_8197F 12 #define BIT_MASK_MGQ_DESC_MODE_8197F 0x3 -#define BIT_MGQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8197F) << BIT_SHIFT_MGQ_DESC_MODE_8197F) -#define BITS_MGQ_DESC_MODE_8197F (BIT_MASK_MGQ_DESC_MODE_8197F << BIT_SHIFT_MGQ_DESC_MODE_8197F) +#define BIT_MGQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_MGQ_DESC_MODE_8197F) << BIT_SHIFT_MGQ_DESC_MODE_8197F) +#define BITS_MGQ_DESC_MODE_8197F \ + (BIT_MASK_MGQ_DESC_MODE_8197F << BIT_SHIFT_MGQ_DESC_MODE_8197F) #define BIT_CLEAR_MGQ_DESC_MODE_8197F(x) ((x) & (~BITS_MGQ_DESC_MODE_8197F)) -#define BIT_GET_MGQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8197F) & BIT_MASK_MGQ_DESC_MODE_8197F) -#define BIT_SET_MGQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_MGQ_DESC_MODE_8197F(x) | BIT_MGQ_DESC_MODE_8197F(v)) - +#define BIT_GET_MGQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8197F) & BIT_MASK_MGQ_DESC_MODE_8197F) +#define BIT_SET_MGQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_MGQ_DESC_MODE_8197F(x) | BIT_MGQ_DESC_MODE_8197F(v)) #define BIT_SHIFT_MGQ_DESC_NUM_8197F 0 #define BIT_MASK_MGQ_DESC_NUM_8197F 0xfff -#define BIT_MGQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8197F) << BIT_SHIFT_MGQ_DESC_NUM_8197F) -#define BITS_MGQ_DESC_NUM_8197F (BIT_MASK_MGQ_DESC_NUM_8197F << BIT_SHIFT_MGQ_DESC_NUM_8197F) +#define BIT_MGQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_MGQ_DESC_NUM_8197F) << BIT_SHIFT_MGQ_DESC_NUM_8197F) +#define BITS_MGQ_DESC_NUM_8197F \ + (BIT_MASK_MGQ_DESC_NUM_8197F << BIT_SHIFT_MGQ_DESC_NUM_8197F) #define BIT_CLEAR_MGQ_DESC_NUM_8197F(x) ((x) & (~BITS_MGQ_DESC_NUM_8197F)) -#define BIT_GET_MGQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8197F) & BIT_MASK_MGQ_DESC_NUM_8197F) -#define BIT_SET_MGQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_MGQ_DESC_NUM_8197F(x) | BIT_MGQ_DESC_NUM_8197F(v)) - +#define BIT_GET_MGQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8197F) & BIT_MASK_MGQ_DESC_NUM_8197F) +#define BIT_SET_MGQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_MGQ_DESC_NUM_8197F(x) | BIT_MGQ_DESC_NUM_8197F(v)) /* 2 REG_RX_RXBD_NUM_8197F */ #define BIT_SYS_32_64_8197F BIT(15) #define BIT_SHIFT_BCNQ_DESC_MODE_8197F 13 #define BIT_MASK_BCNQ_DESC_MODE_8197F 0x3 -#define BIT_BCNQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8197F) << BIT_SHIFT_BCNQ_DESC_MODE_8197F) -#define BITS_BCNQ_DESC_MODE_8197F (BIT_MASK_BCNQ_DESC_MODE_8197F << BIT_SHIFT_BCNQ_DESC_MODE_8197F) +#define BIT_BCNQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_BCNQ_DESC_MODE_8197F) \ + << BIT_SHIFT_BCNQ_DESC_MODE_8197F) +#define BITS_BCNQ_DESC_MODE_8197F \ + (BIT_MASK_BCNQ_DESC_MODE_8197F << BIT_SHIFT_BCNQ_DESC_MODE_8197F) #define BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) ((x) & (~BITS_BCNQ_DESC_MODE_8197F)) -#define BIT_GET_BCNQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8197F) & BIT_MASK_BCNQ_DESC_MODE_8197F) -#define BIT_SET_BCNQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) | BIT_BCNQ_DESC_MODE_8197F(v)) +#define BIT_GET_BCNQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8197F) & \ + BIT_MASK_BCNQ_DESC_MODE_8197F) +#define BIT_SET_BCNQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) | BIT_BCNQ_DESC_MODE_8197F(v)) #define BIT_HCI_BCNQ_FLAG_8197F BIT(12) #define BIT_SHIFT_RXQ_DESC_NUM_8197F 0 #define BIT_MASK_RXQ_DESC_NUM_8197F 0xfff -#define BIT_RXQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8197F) << BIT_SHIFT_RXQ_DESC_NUM_8197F) -#define BITS_RXQ_DESC_NUM_8197F (BIT_MASK_RXQ_DESC_NUM_8197F << BIT_SHIFT_RXQ_DESC_NUM_8197F) +#define BIT_RXQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_RXQ_DESC_NUM_8197F) << BIT_SHIFT_RXQ_DESC_NUM_8197F) +#define BITS_RXQ_DESC_NUM_8197F \ + (BIT_MASK_RXQ_DESC_NUM_8197F << BIT_SHIFT_RXQ_DESC_NUM_8197F) #define BIT_CLEAR_RXQ_DESC_NUM_8197F(x) ((x) & (~BITS_RXQ_DESC_NUM_8197F)) -#define BIT_GET_RXQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8197F) & BIT_MASK_RXQ_DESC_NUM_8197F) -#define BIT_SET_RXQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_RXQ_DESC_NUM_8197F(x) | BIT_RXQ_DESC_NUM_8197F(v)) - +#define BIT_GET_RXQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8197F) & BIT_MASK_RXQ_DESC_NUM_8197F) +#define BIT_SET_RXQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_RXQ_DESC_NUM_8197F(x) | BIT_RXQ_DESC_NUM_8197F(v)) /* 2 REG_VOQ_TXBD_NUM_8197F */ #define BIT_HCI_VOQ_FLAG_8197F BIT(14) #define BIT_SHIFT_VOQ_DESC_MODE_8197F 12 #define BIT_MASK_VOQ_DESC_MODE_8197F 0x3 -#define BIT_VOQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8197F) << BIT_SHIFT_VOQ_DESC_MODE_8197F) -#define BITS_VOQ_DESC_MODE_8197F (BIT_MASK_VOQ_DESC_MODE_8197F << BIT_SHIFT_VOQ_DESC_MODE_8197F) +#define BIT_VOQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_VOQ_DESC_MODE_8197F) << BIT_SHIFT_VOQ_DESC_MODE_8197F) +#define BITS_VOQ_DESC_MODE_8197F \ + (BIT_MASK_VOQ_DESC_MODE_8197F << BIT_SHIFT_VOQ_DESC_MODE_8197F) #define BIT_CLEAR_VOQ_DESC_MODE_8197F(x) ((x) & (~BITS_VOQ_DESC_MODE_8197F)) -#define BIT_GET_VOQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8197F) & BIT_MASK_VOQ_DESC_MODE_8197F) -#define BIT_SET_VOQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_VOQ_DESC_MODE_8197F(x) | BIT_VOQ_DESC_MODE_8197F(v)) - +#define BIT_GET_VOQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8197F) & BIT_MASK_VOQ_DESC_MODE_8197F) +#define BIT_SET_VOQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_VOQ_DESC_MODE_8197F(x) | BIT_VOQ_DESC_MODE_8197F(v)) #define BIT_SHIFT_VOQ_DESC_NUM_8197F 0 #define BIT_MASK_VOQ_DESC_NUM_8197F 0xfff -#define BIT_VOQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8197F) << BIT_SHIFT_VOQ_DESC_NUM_8197F) -#define BITS_VOQ_DESC_NUM_8197F (BIT_MASK_VOQ_DESC_NUM_8197F << BIT_SHIFT_VOQ_DESC_NUM_8197F) +#define BIT_VOQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_VOQ_DESC_NUM_8197F) << BIT_SHIFT_VOQ_DESC_NUM_8197F) +#define BITS_VOQ_DESC_NUM_8197F \ + (BIT_MASK_VOQ_DESC_NUM_8197F << BIT_SHIFT_VOQ_DESC_NUM_8197F) #define BIT_CLEAR_VOQ_DESC_NUM_8197F(x) ((x) & (~BITS_VOQ_DESC_NUM_8197F)) -#define BIT_GET_VOQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8197F) & BIT_MASK_VOQ_DESC_NUM_8197F) -#define BIT_SET_VOQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_VOQ_DESC_NUM_8197F(x) | BIT_VOQ_DESC_NUM_8197F(v)) - +#define BIT_GET_VOQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8197F) & BIT_MASK_VOQ_DESC_NUM_8197F) +#define BIT_SET_VOQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_VOQ_DESC_NUM_8197F(x) | BIT_VOQ_DESC_NUM_8197F(v)) /* 2 REG_VIQ_TXBD_NUM_8197F */ #define BIT_HCI_VIQ_FLAG_8197F BIT(14) #define BIT_SHIFT_VIQ_DESC_MODE_8197F 12 #define BIT_MASK_VIQ_DESC_MODE_8197F 0x3 -#define BIT_VIQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8197F) << BIT_SHIFT_VIQ_DESC_MODE_8197F) -#define BITS_VIQ_DESC_MODE_8197F (BIT_MASK_VIQ_DESC_MODE_8197F << BIT_SHIFT_VIQ_DESC_MODE_8197F) +#define BIT_VIQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_VIQ_DESC_MODE_8197F) << BIT_SHIFT_VIQ_DESC_MODE_8197F) +#define BITS_VIQ_DESC_MODE_8197F \ + (BIT_MASK_VIQ_DESC_MODE_8197F << BIT_SHIFT_VIQ_DESC_MODE_8197F) #define BIT_CLEAR_VIQ_DESC_MODE_8197F(x) ((x) & (~BITS_VIQ_DESC_MODE_8197F)) -#define BIT_GET_VIQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8197F) & BIT_MASK_VIQ_DESC_MODE_8197F) -#define BIT_SET_VIQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_VIQ_DESC_MODE_8197F(x) | BIT_VIQ_DESC_MODE_8197F(v)) - +#define BIT_GET_VIQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8197F) & BIT_MASK_VIQ_DESC_MODE_8197F) +#define BIT_SET_VIQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_VIQ_DESC_MODE_8197F(x) | BIT_VIQ_DESC_MODE_8197F(v)) #define BIT_SHIFT_VIQ_DESC_NUM_8197F 0 #define BIT_MASK_VIQ_DESC_NUM_8197F 0xfff -#define BIT_VIQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8197F) << BIT_SHIFT_VIQ_DESC_NUM_8197F) -#define BITS_VIQ_DESC_NUM_8197F (BIT_MASK_VIQ_DESC_NUM_8197F << BIT_SHIFT_VIQ_DESC_NUM_8197F) +#define BIT_VIQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_VIQ_DESC_NUM_8197F) << BIT_SHIFT_VIQ_DESC_NUM_8197F) +#define BITS_VIQ_DESC_NUM_8197F \ + (BIT_MASK_VIQ_DESC_NUM_8197F << BIT_SHIFT_VIQ_DESC_NUM_8197F) #define BIT_CLEAR_VIQ_DESC_NUM_8197F(x) ((x) & (~BITS_VIQ_DESC_NUM_8197F)) -#define BIT_GET_VIQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8197F) & BIT_MASK_VIQ_DESC_NUM_8197F) -#define BIT_SET_VIQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_VIQ_DESC_NUM_8197F(x) | BIT_VIQ_DESC_NUM_8197F(v)) - +#define BIT_GET_VIQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8197F) & BIT_MASK_VIQ_DESC_NUM_8197F) +#define BIT_SET_VIQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_VIQ_DESC_NUM_8197F(x) | BIT_VIQ_DESC_NUM_8197F(v)) /* 2 REG_BEQ_TXBD_NUM_8197F */ #define BIT_HCI_BEQ_FLAG_8197F BIT(14) #define BIT_SHIFT_BEQ_DESC_MODE_8197F 12 #define BIT_MASK_BEQ_DESC_MODE_8197F 0x3 -#define BIT_BEQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8197F) << BIT_SHIFT_BEQ_DESC_MODE_8197F) -#define BITS_BEQ_DESC_MODE_8197F (BIT_MASK_BEQ_DESC_MODE_8197F << BIT_SHIFT_BEQ_DESC_MODE_8197F) +#define BIT_BEQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_BEQ_DESC_MODE_8197F) << BIT_SHIFT_BEQ_DESC_MODE_8197F) +#define BITS_BEQ_DESC_MODE_8197F \ + (BIT_MASK_BEQ_DESC_MODE_8197F << BIT_SHIFT_BEQ_DESC_MODE_8197F) #define BIT_CLEAR_BEQ_DESC_MODE_8197F(x) ((x) & (~BITS_BEQ_DESC_MODE_8197F)) -#define BIT_GET_BEQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8197F) & BIT_MASK_BEQ_DESC_MODE_8197F) -#define BIT_SET_BEQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_BEQ_DESC_MODE_8197F(x) | BIT_BEQ_DESC_MODE_8197F(v)) - +#define BIT_GET_BEQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8197F) & BIT_MASK_BEQ_DESC_MODE_8197F) +#define BIT_SET_BEQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_BEQ_DESC_MODE_8197F(x) | BIT_BEQ_DESC_MODE_8197F(v)) #define BIT_SHIFT_BEQ_DESC_NUM_8197F 0 #define BIT_MASK_BEQ_DESC_NUM_8197F 0xfff -#define BIT_BEQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8197F) << BIT_SHIFT_BEQ_DESC_NUM_8197F) -#define BITS_BEQ_DESC_NUM_8197F (BIT_MASK_BEQ_DESC_NUM_8197F << BIT_SHIFT_BEQ_DESC_NUM_8197F) +#define BIT_BEQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_BEQ_DESC_NUM_8197F) << BIT_SHIFT_BEQ_DESC_NUM_8197F) +#define BITS_BEQ_DESC_NUM_8197F \ + (BIT_MASK_BEQ_DESC_NUM_8197F << BIT_SHIFT_BEQ_DESC_NUM_8197F) #define BIT_CLEAR_BEQ_DESC_NUM_8197F(x) ((x) & (~BITS_BEQ_DESC_NUM_8197F)) -#define BIT_GET_BEQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8197F) & BIT_MASK_BEQ_DESC_NUM_8197F) -#define BIT_SET_BEQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_BEQ_DESC_NUM_8197F(x) | BIT_BEQ_DESC_NUM_8197F(v)) - +#define BIT_GET_BEQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8197F) & BIT_MASK_BEQ_DESC_NUM_8197F) +#define BIT_SET_BEQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_BEQ_DESC_NUM_8197F(x) | BIT_BEQ_DESC_NUM_8197F(v)) /* 2 REG_BKQ_TXBD_NUM_8197F */ #define BIT_HCI_BKQ_FLAG_8197F BIT(14) #define BIT_SHIFT_BKQ_DESC_MODE_8197F 12 #define BIT_MASK_BKQ_DESC_MODE_8197F 0x3 -#define BIT_BKQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8197F) << BIT_SHIFT_BKQ_DESC_MODE_8197F) -#define BITS_BKQ_DESC_MODE_8197F (BIT_MASK_BKQ_DESC_MODE_8197F << BIT_SHIFT_BKQ_DESC_MODE_8197F) +#define BIT_BKQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_BKQ_DESC_MODE_8197F) << BIT_SHIFT_BKQ_DESC_MODE_8197F) +#define BITS_BKQ_DESC_MODE_8197F \ + (BIT_MASK_BKQ_DESC_MODE_8197F << BIT_SHIFT_BKQ_DESC_MODE_8197F) #define BIT_CLEAR_BKQ_DESC_MODE_8197F(x) ((x) & (~BITS_BKQ_DESC_MODE_8197F)) -#define BIT_GET_BKQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8197F) & BIT_MASK_BKQ_DESC_MODE_8197F) -#define BIT_SET_BKQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_BKQ_DESC_MODE_8197F(x) | BIT_BKQ_DESC_MODE_8197F(v)) - +#define BIT_GET_BKQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8197F) & BIT_MASK_BKQ_DESC_MODE_8197F) +#define BIT_SET_BKQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_BKQ_DESC_MODE_8197F(x) | BIT_BKQ_DESC_MODE_8197F(v)) #define BIT_SHIFT_BKQ_DESC_NUM_8197F 0 #define BIT_MASK_BKQ_DESC_NUM_8197F 0xfff -#define BIT_BKQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8197F) << BIT_SHIFT_BKQ_DESC_NUM_8197F) -#define BITS_BKQ_DESC_NUM_8197F (BIT_MASK_BKQ_DESC_NUM_8197F << BIT_SHIFT_BKQ_DESC_NUM_8197F) +#define BIT_BKQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_BKQ_DESC_NUM_8197F) << BIT_SHIFT_BKQ_DESC_NUM_8197F) +#define BITS_BKQ_DESC_NUM_8197F \ + (BIT_MASK_BKQ_DESC_NUM_8197F << BIT_SHIFT_BKQ_DESC_NUM_8197F) #define BIT_CLEAR_BKQ_DESC_NUM_8197F(x) ((x) & (~BITS_BKQ_DESC_NUM_8197F)) -#define BIT_GET_BKQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8197F) & BIT_MASK_BKQ_DESC_NUM_8197F) -#define BIT_SET_BKQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_BKQ_DESC_NUM_8197F(x) | BIT_BKQ_DESC_NUM_8197F(v)) - +#define BIT_GET_BKQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8197F) & BIT_MASK_BKQ_DESC_NUM_8197F) +#define BIT_SET_BKQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_BKQ_DESC_NUM_8197F(x) | BIT_BKQ_DESC_NUM_8197F(v)) /* 2 REG_HI0Q_TXBD_NUM_8197F */ #define BIT_HI0Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI0Q_DESC_MODE_8197F 12 #define BIT_MASK_HI0Q_DESC_MODE_8197F 0x3 -#define BIT_HI0Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8197F) << BIT_SHIFT_HI0Q_DESC_MODE_8197F) -#define BITS_HI0Q_DESC_MODE_8197F (BIT_MASK_HI0Q_DESC_MODE_8197F << BIT_SHIFT_HI0Q_DESC_MODE_8197F) +#define BIT_HI0Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI0Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI0Q_DESC_MODE_8197F) +#define BITS_HI0Q_DESC_MODE_8197F \ + (BIT_MASK_HI0Q_DESC_MODE_8197F << BIT_SHIFT_HI0Q_DESC_MODE_8197F) #define BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI0Q_DESC_MODE_8197F)) -#define BIT_GET_HI0Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8197F) & BIT_MASK_HI0Q_DESC_MODE_8197F) -#define BIT_SET_HI0Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) | BIT_HI0Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI0Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8197F) & \ + BIT_MASK_HI0Q_DESC_MODE_8197F) +#define BIT_SET_HI0Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) | BIT_HI0Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI0Q_DESC_NUM_8197F 0 #define BIT_MASK_HI0Q_DESC_NUM_8197F 0xfff -#define BIT_HI0Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8197F) << BIT_SHIFT_HI0Q_DESC_NUM_8197F) -#define BITS_HI0Q_DESC_NUM_8197F (BIT_MASK_HI0Q_DESC_NUM_8197F << BIT_SHIFT_HI0Q_DESC_NUM_8197F) +#define BIT_HI0Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI0Q_DESC_NUM_8197F) << BIT_SHIFT_HI0Q_DESC_NUM_8197F) +#define BITS_HI0Q_DESC_NUM_8197F \ + (BIT_MASK_HI0Q_DESC_NUM_8197F << BIT_SHIFT_HI0Q_DESC_NUM_8197F) #define BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI0Q_DESC_NUM_8197F)) -#define BIT_GET_HI0Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8197F) & BIT_MASK_HI0Q_DESC_NUM_8197F) -#define BIT_SET_HI0Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) | BIT_HI0Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI0Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8197F) & BIT_MASK_HI0Q_DESC_NUM_8197F) +#define BIT_SET_HI0Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) | BIT_HI0Q_DESC_NUM_8197F(v)) /* 2 REG_HI1Q_TXBD_NUM_8197F */ #define BIT_HI1Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI1Q_DESC_MODE_8197F 12 #define BIT_MASK_HI1Q_DESC_MODE_8197F 0x3 -#define BIT_HI1Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8197F) << BIT_SHIFT_HI1Q_DESC_MODE_8197F) -#define BITS_HI1Q_DESC_MODE_8197F (BIT_MASK_HI1Q_DESC_MODE_8197F << BIT_SHIFT_HI1Q_DESC_MODE_8197F) +#define BIT_HI1Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI1Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI1Q_DESC_MODE_8197F) +#define BITS_HI1Q_DESC_MODE_8197F \ + (BIT_MASK_HI1Q_DESC_MODE_8197F << BIT_SHIFT_HI1Q_DESC_MODE_8197F) #define BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI1Q_DESC_MODE_8197F)) -#define BIT_GET_HI1Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8197F) & BIT_MASK_HI1Q_DESC_MODE_8197F) -#define BIT_SET_HI1Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) | BIT_HI1Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI1Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8197F) & \ + BIT_MASK_HI1Q_DESC_MODE_8197F) +#define BIT_SET_HI1Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) | BIT_HI1Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI1Q_DESC_NUM_8197F 0 #define BIT_MASK_HI1Q_DESC_NUM_8197F 0xfff -#define BIT_HI1Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8197F) << BIT_SHIFT_HI1Q_DESC_NUM_8197F) -#define BITS_HI1Q_DESC_NUM_8197F (BIT_MASK_HI1Q_DESC_NUM_8197F << BIT_SHIFT_HI1Q_DESC_NUM_8197F) +#define BIT_HI1Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI1Q_DESC_NUM_8197F) << BIT_SHIFT_HI1Q_DESC_NUM_8197F) +#define BITS_HI1Q_DESC_NUM_8197F \ + (BIT_MASK_HI1Q_DESC_NUM_8197F << BIT_SHIFT_HI1Q_DESC_NUM_8197F) #define BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI1Q_DESC_NUM_8197F)) -#define BIT_GET_HI1Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8197F) & BIT_MASK_HI1Q_DESC_NUM_8197F) -#define BIT_SET_HI1Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) | BIT_HI1Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI1Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8197F) & BIT_MASK_HI1Q_DESC_NUM_8197F) +#define BIT_SET_HI1Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) | BIT_HI1Q_DESC_NUM_8197F(v)) /* 2 REG_HI2Q_TXBD_NUM_8197F */ #define BIT_HI2Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI2Q_DESC_MODE_8197F 12 #define BIT_MASK_HI2Q_DESC_MODE_8197F 0x3 -#define BIT_HI2Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8197F) << BIT_SHIFT_HI2Q_DESC_MODE_8197F) -#define BITS_HI2Q_DESC_MODE_8197F (BIT_MASK_HI2Q_DESC_MODE_8197F << BIT_SHIFT_HI2Q_DESC_MODE_8197F) +#define BIT_HI2Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI2Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI2Q_DESC_MODE_8197F) +#define BITS_HI2Q_DESC_MODE_8197F \ + (BIT_MASK_HI2Q_DESC_MODE_8197F << BIT_SHIFT_HI2Q_DESC_MODE_8197F) #define BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI2Q_DESC_MODE_8197F)) -#define BIT_GET_HI2Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8197F) & BIT_MASK_HI2Q_DESC_MODE_8197F) -#define BIT_SET_HI2Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) | BIT_HI2Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI2Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8197F) & \ + BIT_MASK_HI2Q_DESC_MODE_8197F) +#define BIT_SET_HI2Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) | BIT_HI2Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI2Q_DESC_NUM_8197F 0 #define BIT_MASK_HI2Q_DESC_NUM_8197F 0xfff -#define BIT_HI2Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8197F) << BIT_SHIFT_HI2Q_DESC_NUM_8197F) -#define BITS_HI2Q_DESC_NUM_8197F (BIT_MASK_HI2Q_DESC_NUM_8197F << BIT_SHIFT_HI2Q_DESC_NUM_8197F) +#define BIT_HI2Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI2Q_DESC_NUM_8197F) << BIT_SHIFT_HI2Q_DESC_NUM_8197F) +#define BITS_HI2Q_DESC_NUM_8197F \ + (BIT_MASK_HI2Q_DESC_NUM_8197F << BIT_SHIFT_HI2Q_DESC_NUM_8197F) #define BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI2Q_DESC_NUM_8197F)) -#define BIT_GET_HI2Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8197F) & BIT_MASK_HI2Q_DESC_NUM_8197F) -#define BIT_SET_HI2Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) | BIT_HI2Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI2Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8197F) & BIT_MASK_HI2Q_DESC_NUM_8197F) +#define BIT_SET_HI2Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) | BIT_HI2Q_DESC_NUM_8197F(v)) /* 2 REG_HI3Q_TXBD_NUM_8197F */ #define BIT_HI3Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI3Q_DESC_MODE_8197F 12 #define BIT_MASK_HI3Q_DESC_MODE_8197F 0x3 -#define BIT_HI3Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8197F) << BIT_SHIFT_HI3Q_DESC_MODE_8197F) -#define BITS_HI3Q_DESC_MODE_8197F (BIT_MASK_HI3Q_DESC_MODE_8197F << BIT_SHIFT_HI3Q_DESC_MODE_8197F) +#define BIT_HI3Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI3Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI3Q_DESC_MODE_8197F) +#define BITS_HI3Q_DESC_MODE_8197F \ + (BIT_MASK_HI3Q_DESC_MODE_8197F << BIT_SHIFT_HI3Q_DESC_MODE_8197F) #define BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI3Q_DESC_MODE_8197F)) -#define BIT_GET_HI3Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8197F) & BIT_MASK_HI3Q_DESC_MODE_8197F) -#define BIT_SET_HI3Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) | BIT_HI3Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI3Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8197F) & \ + BIT_MASK_HI3Q_DESC_MODE_8197F) +#define BIT_SET_HI3Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) | BIT_HI3Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI3Q_DESC_NUM_8197F 0 #define BIT_MASK_HI3Q_DESC_NUM_8197F 0xfff -#define BIT_HI3Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8197F) << BIT_SHIFT_HI3Q_DESC_NUM_8197F) -#define BITS_HI3Q_DESC_NUM_8197F (BIT_MASK_HI3Q_DESC_NUM_8197F << BIT_SHIFT_HI3Q_DESC_NUM_8197F) +#define BIT_HI3Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI3Q_DESC_NUM_8197F) << BIT_SHIFT_HI3Q_DESC_NUM_8197F) +#define BITS_HI3Q_DESC_NUM_8197F \ + (BIT_MASK_HI3Q_DESC_NUM_8197F << BIT_SHIFT_HI3Q_DESC_NUM_8197F) #define BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI3Q_DESC_NUM_8197F)) -#define BIT_GET_HI3Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8197F) & BIT_MASK_HI3Q_DESC_NUM_8197F) -#define BIT_SET_HI3Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) | BIT_HI3Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI3Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8197F) & BIT_MASK_HI3Q_DESC_NUM_8197F) +#define BIT_SET_HI3Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) | BIT_HI3Q_DESC_NUM_8197F(v)) /* 2 REG_HI4Q_TXBD_NUM_8197F */ #define BIT_HI4Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI4Q_DESC_MODE_8197F 12 #define BIT_MASK_HI4Q_DESC_MODE_8197F 0x3 -#define BIT_HI4Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8197F) << BIT_SHIFT_HI4Q_DESC_MODE_8197F) -#define BITS_HI4Q_DESC_MODE_8197F (BIT_MASK_HI4Q_DESC_MODE_8197F << BIT_SHIFT_HI4Q_DESC_MODE_8197F) +#define BIT_HI4Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI4Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI4Q_DESC_MODE_8197F) +#define BITS_HI4Q_DESC_MODE_8197F \ + (BIT_MASK_HI4Q_DESC_MODE_8197F << BIT_SHIFT_HI4Q_DESC_MODE_8197F) #define BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI4Q_DESC_MODE_8197F)) -#define BIT_GET_HI4Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8197F) & BIT_MASK_HI4Q_DESC_MODE_8197F) -#define BIT_SET_HI4Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) | BIT_HI4Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI4Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8197F) & \ + BIT_MASK_HI4Q_DESC_MODE_8197F) +#define BIT_SET_HI4Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) | BIT_HI4Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI4Q_DESC_NUM_8197F 0 #define BIT_MASK_HI4Q_DESC_NUM_8197F 0xfff -#define BIT_HI4Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8197F) << BIT_SHIFT_HI4Q_DESC_NUM_8197F) -#define BITS_HI4Q_DESC_NUM_8197F (BIT_MASK_HI4Q_DESC_NUM_8197F << BIT_SHIFT_HI4Q_DESC_NUM_8197F) +#define BIT_HI4Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI4Q_DESC_NUM_8197F) << BIT_SHIFT_HI4Q_DESC_NUM_8197F) +#define BITS_HI4Q_DESC_NUM_8197F \ + (BIT_MASK_HI4Q_DESC_NUM_8197F << BIT_SHIFT_HI4Q_DESC_NUM_8197F) #define BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI4Q_DESC_NUM_8197F)) -#define BIT_GET_HI4Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8197F) & BIT_MASK_HI4Q_DESC_NUM_8197F) -#define BIT_SET_HI4Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) | BIT_HI4Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI4Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8197F) & BIT_MASK_HI4Q_DESC_NUM_8197F) +#define BIT_SET_HI4Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) | BIT_HI4Q_DESC_NUM_8197F(v)) /* 2 REG_HI5Q_TXBD_NUM_8197F */ #define BIT_HI5Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI5Q_DESC_MODE_8197F 12 #define BIT_MASK_HI5Q_DESC_MODE_8197F 0x3 -#define BIT_HI5Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8197F) << BIT_SHIFT_HI5Q_DESC_MODE_8197F) -#define BITS_HI5Q_DESC_MODE_8197F (BIT_MASK_HI5Q_DESC_MODE_8197F << BIT_SHIFT_HI5Q_DESC_MODE_8197F) +#define BIT_HI5Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI5Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI5Q_DESC_MODE_8197F) +#define BITS_HI5Q_DESC_MODE_8197F \ + (BIT_MASK_HI5Q_DESC_MODE_8197F << BIT_SHIFT_HI5Q_DESC_MODE_8197F) #define BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI5Q_DESC_MODE_8197F)) -#define BIT_GET_HI5Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8197F) & BIT_MASK_HI5Q_DESC_MODE_8197F) -#define BIT_SET_HI5Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) | BIT_HI5Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI5Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8197F) & \ + BIT_MASK_HI5Q_DESC_MODE_8197F) +#define BIT_SET_HI5Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) | BIT_HI5Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI5Q_DESC_NUM_8197F 0 #define BIT_MASK_HI5Q_DESC_NUM_8197F 0xfff -#define BIT_HI5Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8197F) << BIT_SHIFT_HI5Q_DESC_NUM_8197F) -#define BITS_HI5Q_DESC_NUM_8197F (BIT_MASK_HI5Q_DESC_NUM_8197F << BIT_SHIFT_HI5Q_DESC_NUM_8197F) +#define BIT_HI5Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI5Q_DESC_NUM_8197F) << BIT_SHIFT_HI5Q_DESC_NUM_8197F) +#define BITS_HI5Q_DESC_NUM_8197F \ + (BIT_MASK_HI5Q_DESC_NUM_8197F << BIT_SHIFT_HI5Q_DESC_NUM_8197F) #define BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI5Q_DESC_NUM_8197F)) -#define BIT_GET_HI5Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8197F) & BIT_MASK_HI5Q_DESC_NUM_8197F) -#define BIT_SET_HI5Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) | BIT_HI5Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI5Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8197F) & BIT_MASK_HI5Q_DESC_NUM_8197F) +#define BIT_SET_HI5Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) | BIT_HI5Q_DESC_NUM_8197F(v)) /* 2 REG_HI6Q_TXBD_NUM_8197F */ #define BIT_HI6Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI6Q_DESC_MODE_8197F 12 #define BIT_MASK_HI6Q_DESC_MODE_8197F 0x3 -#define BIT_HI6Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8197F) << BIT_SHIFT_HI6Q_DESC_MODE_8197F) -#define BITS_HI6Q_DESC_MODE_8197F (BIT_MASK_HI6Q_DESC_MODE_8197F << BIT_SHIFT_HI6Q_DESC_MODE_8197F) +#define BIT_HI6Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI6Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI6Q_DESC_MODE_8197F) +#define BITS_HI6Q_DESC_MODE_8197F \ + (BIT_MASK_HI6Q_DESC_MODE_8197F << BIT_SHIFT_HI6Q_DESC_MODE_8197F) #define BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI6Q_DESC_MODE_8197F)) -#define BIT_GET_HI6Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8197F) & BIT_MASK_HI6Q_DESC_MODE_8197F) -#define BIT_SET_HI6Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) | BIT_HI6Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI6Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8197F) & \ + BIT_MASK_HI6Q_DESC_MODE_8197F) +#define BIT_SET_HI6Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) | BIT_HI6Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI6Q_DESC_NUM_8197F 0 #define BIT_MASK_HI6Q_DESC_NUM_8197F 0xfff -#define BIT_HI6Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8197F) << BIT_SHIFT_HI6Q_DESC_NUM_8197F) -#define BITS_HI6Q_DESC_NUM_8197F (BIT_MASK_HI6Q_DESC_NUM_8197F << BIT_SHIFT_HI6Q_DESC_NUM_8197F) +#define BIT_HI6Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI6Q_DESC_NUM_8197F) << BIT_SHIFT_HI6Q_DESC_NUM_8197F) +#define BITS_HI6Q_DESC_NUM_8197F \ + (BIT_MASK_HI6Q_DESC_NUM_8197F << BIT_SHIFT_HI6Q_DESC_NUM_8197F) #define BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI6Q_DESC_NUM_8197F)) -#define BIT_GET_HI6Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8197F) & BIT_MASK_HI6Q_DESC_NUM_8197F) -#define BIT_SET_HI6Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) | BIT_HI6Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI6Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8197F) & BIT_MASK_HI6Q_DESC_NUM_8197F) +#define BIT_SET_HI6Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) | BIT_HI6Q_DESC_NUM_8197F(v)) /* 2 REG_HI7Q_TXBD_NUM_8197F */ #define BIT_HI7Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI7Q_DESC_MODE_8197F 12 #define BIT_MASK_HI7Q_DESC_MODE_8197F 0x3 -#define BIT_HI7Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8197F) << BIT_SHIFT_HI7Q_DESC_MODE_8197F) -#define BITS_HI7Q_DESC_MODE_8197F (BIT_MASK_HI7Q_DESC_MODE_8197F << BIT_SHIFT_HI7Q_DESC_MODE_8197F) +#define BIT_HI7Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI7Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI7Q_DESC_MODE_8197F) +#define BITS_HI7Q_DESC_MODE_8197F \ + (BIT_MASK_HI7Q_DESC_MODE_8197F << BIT_SHIFT_HI7Q_DESC_MODE_8197F) #define BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI7Q_DESC_MODE_8197F)) -#define BIT_GET_HI7Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8197F) & BIT_MASK_HI7Q_DESC_MODE_8197F) -#define BIT_SET_HI7Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) | BIT_HI7Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI7Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8197F) & \ + BIT_MASK_HI7Q_DESC_MODE_8197F) +#define BIT_SET_HI7Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) | BIT_HI7Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI7Q_DESC_NUM_8197F 0 #define BIT_MASK_HI7Q_DESC_NUM_8197F 0xfff -#define BIT_HI7Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8197F) << BIT_SHIFT_HI7Q_DESC_NUM_8197F) -#define BITS_HI7Q_DESC_NUM_8197F (BIT_MASK_HI7Q_DESC_NUM_8197F << BIT_SHIFT_HI7Q_DESC_NUM_8197F) +#define BIT_HI7Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI7Q_DESC_NUM_8197F) << BIT_SHIFT_HI7Q_DESC_NUM_8197F) +#define BITS_HI7Q_DESC_NUM_8197F \ + (BIT_MASK_HI7Q_DESC_NUM_8197F << BIT_SHIFT_HI7Q_DESC_NUM_8197F) #define BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI7Q_DESC_NUM_8197F)) -#define BIT_GET_HI7Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8197F) & BIT_MASK_HI7Q_DESC_NUM_8197F) -#define BIT_SET_HI7Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) | BIT_HI7Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI7Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8197F) & BIT_MASK_HI7Q_DESC_NUM_8197F) +#define BIT_SET_HI7Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) | BIT_HI7Q_DESC_NUM_8197F(v)) /* 2 REG_TSFTIMER_HCI_8197F */ #define BIT_SHIFT_TSFT2_HCI_8197F 16 #define BIT_MASK_TSFT2_HCI_8197F 0xffff -#define BIT_TSFT2_HCI_8197F(x) (((x) & BIT_MASK_TSFT2_HCI_8197F) << BIT_SHIFT_TSFT2_HCI_8197F) -#define BITS_TSFT2_HCI_8197F (BIT_MASK_TSFT2_HCI_8197F << BIT_SHIFT_TSFT2_HCI_8197F) +#define BIT_TSFT2_HCI_8197F(x) \ + (((x) & BIT_MASK_TSFT2_HCI_8197F) << BIT_SHIFT_TSFT2_HCI_8197F) +#define BITS_TSFT2_HCI_8197F \ + (BIT_MASK_TSFT2_HCI_8197F << BIT_SHIFT_TSFT2_HCI_8197F) #define BIT_CLEAR_TSFT2_HCI_8197F(x) ((x) & (~BITS_TSFT2_HCI_8197F)) -#define BIT_GET_TSFT2_HCI_8197F(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8197F) & BIT_MASK_TSFT2_HCI_8197F) -#define BIT_SET_TSFT2_HCI_8197F(x, v) (BIT_CLEAR_TSFT2_HCI_8197F(x) | BIT_TSFT2_HCI_8197F(v)) - +#define BIT_GET_TSFT2_HCI_8197F(x) \ + (((x) >> BIT_SHIFT_TSFT2_HCI_8197F) & BIT_MASK_TSFT2_HCI_8197F) +#define BIT_SET_TSFT2_HCI_8197F(x, v) \ + (BIT_CLEAR_TSFT2_HCI_8197F(x) | BIT_TSFT2_HCI_8197F(v)) #define BIT_SHIFT_TSFT1_HCI_8197F 0 #define BIT_MASK_TSFT1_HCI_8197F 0xffff -#define BIT_TSFT1_HCI_8197F(x) (((x) & BIT_MASK_TSFT1_HCI_8197F) << BIT_SHIFT_TSFT1_HCI_8197F) -#define BITS_TSFT1_HCI_8197F (BIT_MASK_TSFT1_HCI_8197F << BIT_SHIFT_TSFT1_HCI_8197F) +#define BIT_TSFT1_HCI_8197F(x) \ + (((x) & BIT_MASK_TSFT1_HCI_8197F) << BIT_SHIFT_TSFT1_HCI_8197F) +#define BITS_TSFT1_HCI_8197F \ + (BIT_MASK_TSFT1_HCI_8197F << BIT_SHIFT_TSFT1_HCI_8197F) #define BIT_CLEAR_TSFT1_HCI_8197F(x) ((x) & (~BITS_TSFT1_HCI_8197F)) -#define BIT_GET_TSFT1_HCI_8197F(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8197F) & BIT_MASK_TSFT1_HCI_8197F) -#define BIT_SET_TSFT1_HCI_8197F(x, v) (BIT_CLEAR_TSFT1_HCI_8197F(x) | BIT_TSFT1_HCI_8197F(v)) - +#define BIT_GET_TSFT1_HCI_8197F(x) \ + (((x) >> BIT_SHIFT_TSFT1_HCI_8197F) & BIT_MASK_TSFT1_HCI_8197F) +#define BIT_SET_TSFT1_HCI_8197F(x, v) \ + (BIT_CLEAR_TSFT1_HCI_8197F(x) | BIT_TSFT1_HCI_8197F(v)) /* 2 REG_BD_RWPTR_CLR_8197F */ #define BIT_CLR_HI7Q_HW_IDX_8197F BIT(29) @@ -5442,314 +6854,406 @@ #define BIT_SHIFT_VOQ_HW_IDX_8197F 16 #define BIT_MASK_VOQ_HW_IDX_8197F 0xfff -#define BIT_VOQ_HW_IDX_8197F(x) (((x) & BIT_MASK_VOQ_HW_IDX_8197F) << BIT_SHIFT_VOQ_HW_IDX_8197F) -#define BITS_VOQ_HW_IDX_8197F (BIT_MASK_VOQ_HW_IDX_8197F << BIT_SHIFT_VOQ_HW_IDX_8197F) +#define BIT_VOQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_VOQ_HW_IDX_8197F) << BIT_SHIFT_VOQ_HW_IDX_8197F) +#define BITS_VOQ_HW_IDX_8197F \ + (BIT_MASK_VOQ_HW_IDX_8197F << BIT_SHIFT_VOQ_HW_IDX_8197F) #define BIT_CLEAR_VOQ_HW_IDX_8197F(x) ((x) & (~BITS_VOQ_HW_IDX_8197F)) -#define BIT_GET_VOQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8197F) & BIT_MASK_VOQ_HW_IDX_8197F) -#define BIT_SET_VOQ_HW_IDX_8197F(x, v) (BIT_CLEAR_VOQ_HW_IDX_8197F(x) | BIT_VOQ_HW_IDX_8197F(v)) - +#define BIT_GET_VOQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_VOQ_HW_IDX_8197F) & BIT_MASK_VOQ_HW_IDX_8197F) +#define BIT_SET_VOQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_VOQ_HW_IDX_8197F(x) | BIT_VOQ_HW_IDX_8197F(v)) #define BIT_SHIFT_VOQ_HOST_IDX_8197F 0 #define BIT_MASK_VOQ_HOST_IDX_8197F 0xfff -#define BIT_VOQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8197F) << BIT_SHIFT_VOQ_HOST_IDX_8197F) -#define BITS_VOQ_HOST_IDX_8197F (BIT_MASK_VOQ_HOST_IDX_8197F << BIT_SHIFT_VOQ_HOST_IDX_8197F) +#define BIT_VOQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_VOQ_HOST_IDX_8197F) << BIT_SHIFT_VOQ_HOST_IDX_8197F) +#define BITS_VOQ_HOST_IDX_8197F \ + (BIT_MASK_VOQ_HOST_IDX_8197F << BIT_SHIFT_VOQ_HOST_IDX_8197F) #define BIT_CLEAR_VOQ_HOST_IDX_8197F(x) ((x) & (~BITS_VOQ_HOST_IDX_8197F)) -#define BIT_GET_VOQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8197F) & BIT_MASK_VOQ_HOST_IDX_8197F) -#define BIT_SET_VOQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_VOQ_HOST_IDX_8197F(x) | BIT_VOQ_HOST_IDX_8197F(v)) - +#define BIT_GET_VOQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8197F) & BIT_MASK_VOQ_HOST_IDX_8197F) +#define BIT_SET_VOQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_VOQ_HOST_IDX_8197F(x) | BIT_VOQ_HOST_IDX_8197F(v)) /* 2 REG_VIQ_TXBD_IDX_8197F */ #define BIT_SHIFT_VIQ_HW_IDX_8197F 16 #define BIT_MASK_VIQ_HW_IDX_8197F 0xfff -#define BIT_VIQ_HW_IDX_8197F(x) (((x) & BIT_MASK_VIQ_HW_IDX_8197F) << BIT_SHIFT_VIQ_HW_IDX_8197F) -#define BITS_VIQ_HW_IDX_8197F (BIT_MASK_VIQ_HW_IDX_8197F << BIT_SHIFT_VIQ_HW_IDX_8197F) +#define BIT_VIQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_VIQ_HW_IDX_8197F) << BIT_SHIFT_VIQ_HW_IDX_8197F) +#define BITS_VIQ_HW_IDX_8197F \ + (BIT_MASK_VIQ_HW_IDX_8197F << BIT_SHIFT_VIQ_HW_IDX_8197F) #define BIT_CLEAR_VIQ_HW_IDX_8197F(x) ((x) & (~BITS_VIQ_HW_IDX_8197F)) -#define BIT_GET_VIQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8197F) & BIT_MASK_VIQ_HW_IDX_8197F) -#define BIT_SET_VIQ_HW_IDX_8197F(x, v) (BIT_CLEAR_VIQ_HW_IDX_8197F(x) | BIT_VIQ_HW_IDX_8197F(v)) - +#define BIT_GET_VIQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_VIQ_HW_IDX_8197F) & BIT_MASK_VIQ_HW_IDX_8197F) +#define BIT_SET_VIQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_VIQ_HW_IDX_8197F(x) | BIT_VIQ_HW_IDX_8197F(v)) #define BIT_SHIFT_VIQ_HOST_IDX_8197F 0 #define BIT_MASK_VIQ_HOST_IDX_8197F 0xfff -#define BIT_VIQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8197F) << BIT_SHIFT_VIQ_HOST_IDX_8197F) -#define BITS_VIQ_HOST_IDX_8197F (BIT_MASK_VIQ_HOST_IDX_8197F << BIT_SHIFT_VIQ_HOST_IDX_8197F) +#define BIT_VIQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_VIQ_HOST_IDX_8197F) << BIT_SHIFT_VIQ_HOST_IDX_8197F) +#define BITS_VIQ_HOST_IDX_8197F \ + (BIT_MASK_VIQ_HOST_IDX_8197F << BIT_SHIFT_VIQ_HOST_IDX_8197F) #define BIT_CLEAR_VIQ_HOST_IDX_8197F(x) ((x) & (~BITS_VIQ_HOST_IDX_8197F)) -#define BIT_GET_VIQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8197F) & BIT_MASK_VIQ_HOST_IDX_8197F) -#define BIT_SET_VIQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_VIQ_HOST_IDX_8197F(x) | BIT_VIQ_HOST_IDX_8197F(v)) - +#define BIT_GET_VIQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8197F) & BIT_MASK_VIQ_HOST_IDX_8197F) +#define BIT_SET_VIQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_VIQ_HOST_IDX_8197F(x) | BIT_VIQ_HOST_IDX_8197F(v)) /* 2 REG_BEQ_TXBD_IDX_8197F */ #define BIT_SHIFT_BEQ_HW_IDX_8197F 16 #define BIT_MASK_BEQ_HW_IDX_8197F 0xfff -#define BIT_BEQ_HW_IDX_8197F(x) (((x) & BIT_MASK_BEQ_HW_IDX_8197F) << BIT_SHIFT_BEQ_HW_IDX_8197F) -#define BITS_BEQ_HW_IDX_8197F (BIT_MASK_BEQ_HW_IDX_8197F << BIT_SHIFT_BEQ_HW_IDX_8197F) +#define BIT_BEQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_BEQ_HW_IDX_8197F) << BIT_SHIFT_BEQ_HW_IDX_8197F) +#define BITS_BEQ_HW_IDX_8197F \ + (BIT_MASK_BEQ_HW_IDX_8197F << BIT_SHIFT_BEQ_HW_IDX_8197F) #define BIT_CLEAR_BEQ_HW_IDX_8197F(x) ((x) & (~BITS_BEQ_HW_IDX_8197F)) -#define BIT_GET_BEQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8197F) & BIT_MASK_BEQ_HW_IDX_8197F) -#define BIT_SET_BEQ_HW_IDX_8197F(x, v) (BIT_CLEAR_BEQ_HW_IDX_8197F(x) | BIT_BEQ_HW_IDX_8197F(v)) - +#define BIT_GET_BEQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_BEQ_HW_IDX_8197F) & BIT_MASK_BEQ_HW_IDX_8197F) +#define BIT_SET_BEQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_BEQ_HW_IDX_8197F(x) | BIT_BEQ_HW_IDX_8197F(v)) #define BIT_SHIFT_BEQ_HOST_IDX_8197F 0 #define BIT_MASK_BEQ_HOST_IDX_8197F 0xfff -#define BIT_BEQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8197F) << BIT_SHIFT_BEQ_HOST_IDX_8197F) -#define BITS_BEQ_HOST_IDX_8197F (BIT_MASK_BEQ_HOST_IDX_8197F << BIT_SHIFT_BEQ_HOST_IDX_8197F) +#define BIT_BEQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_BEQ_HOST_IDX_8197F) << BIT_SHIFT_BEQ_HOST_IDX_8197F) +#define BITS_BEQ_HOST_IDX_8197F \ + (BIT_MASK_BEQ_HOST_IDX_8197F << BIT_SHIFT_BEQ_HOST_IDX_8197F) #define BIT_CLEAR_BEQ_HOST_IDX_8197F(x) ((x) & (~BITS_BEQ_HOST_IDX_8197F)) -#define BIT_GET_BEQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8197F) & BIT_MASK_BEQ_HOST_IDX_8197F) -#define BIT_SET_BEQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_BEQ_HOST_IDX_8197F(x) | BIT_BEQ_HOST_IDX_8197F(v)) - +#define BIT_GET_BEQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8197F) & BIT_MASK_BEQ_HOST_IDX_8197F) +#define BIT_SET_BEQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_BEQ_HOST_IDX_8197F(x) | BIT_BEQ_HOST_IDX_8197F(v)) /* 2 REG_BKQ_TXBD_IDX_8197F */ #define BIT_SHIFT_BKQ_HW_IDX_8197F 16 #define BIT_MASK_BKQ_HW_IDX_8197F 0xfff -#define BIT_BKQ_HW_IDX_8197F(x) (((x) & BIT_MASK_BKQ_HW_IDX_8197F) << BIT_SHIFT_BKQ_HW_IDX_8197F) -#define BITS_BKQ_HW_IDX_8197F (BIT_MASK_BKQ_HW_IDX_8197F << BIT_SHIFT_BKQ_HW_IDX_8197F) +#define BIT_BKQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_BKQ_HW_IDX_8197F) << BIT_SHIFT_BKQ_HW_IDX_8197F) +#define BITS_BKQ_HW_IDX_8197F \ + (BIT_MASK_BKQ_HW_IDX_8197F << BIT_SHIFT_BKQ_HW_IDX_8197F) #define BIT_CLEAR_BKQ_HW_IDX_8197F(x) ((x) & (~BITS_BKQ_HW_IDX_8197F)) -#define BIT_GET_BKQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8197F) & BIT_MASK_BKQ_HW_IDX_8197F) -#define BIT_SET_BKQ_HW_IDX_8197F(x, v) (BIT_CLEAR_BKQ_HW_IDX_8197F(x) | BIT_BKQ_HW_IDX_8197F(v)) - +#define BIT_GET_BKQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_BKQ_HW_IDX_8197F) & BIT_MASK_BKQ_HW_IDX_8197F) +#define BIT_SET_BKQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_BKQ_HW_IDX_8197F(x) | BIT_BKQ_HW_IDX_8197F(v)) #define BIT_SHIFT_BKQ_HOST_IDX_8197F 0 #define BIT_MASK_BKQ_HOST_IDX_8197F 0xfff -#define BIT_BKQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8197F) << BIT_SHIFT_BKQ_HOST_IDX_8197F) -#define BITS_BKQ_HOST_IDX_8197F (BIT_MASK_BKQ_HOST_IDX_8197F << BIT_SHIFT_BKQ_HOST_IDX_8197F) +#define BIT_BKQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_BKQ_HOST_IDX_8197F) << BIT_SHIFT_BKQ_HOST_IDX_8197F) +#define BITS_BKQ_HOST_IDX_8197F \ + (BIT_MASK_BKQ_HOST_IDX_8197F << BIT_SHIFT_BKQ_HOST_IDX_8197F) #define BIT_CLEAR_BKQ_HOST_IDX_8197F(x) ((x) & (~BITS_BKQ_HOST_IDX_8197F)) -#define BIT_GET_BKQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8197F) & BIT_MASK_BKQ_HOST_IDX_8197F) -#define BIT_SET_BKQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_BKQ_HOST_IDX_8197F(x) | BIT_BKQ_HOST_IDX_8197F(v)) - +#define BIT_GET_BKQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8197F) & BIT_MASK_BKQ_HOST_IDX_8197F) +#define BIT_SET_BKQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_BKQ_HOST_IDX_8197F(x) | BIT_BKQ_HOST_IDX_8197F(v)) /* 2 REG_MGQ_TXBD_IDX_8197F */ #define BIT_SHIFT_MGQ_HW_IDX_8197F 16 #define BIT_MASK_MGQ_HW_IDX_8197F 0xfff -#define BIT_MGQ_HW_IDX_8197F(x) (((x) & BIT_MASK_MGQ_HW_IDX_8197F) << BIT_SHIFT_MGQ_HW_IDX_8197F) -#define BITS_MGQ_HW_IDX_8197F (BIT_MASK_MGQ_HW_IDX_8197F << BIT_SHIFT_MGQ_HW_IDX_8197F) +#define BIT_MGQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_MGQ_HW_IDX_8197F) << BIT_SHIFT_MGQ_HW_IDX_8197F) +#define BITS_MGQ_HW_IDX_8197F \ + (BIT_MASK_MGQ_HW_IDX_8197F << BIT_SHIFT_MGQ_HW_IDX_8197F) #define BIT_CLEAR_MGQ_HW_IDX_8197F(x) ((x) & (~BITS_MGQ_HW_IDX_8197F)) -#define BIT_GET_MGQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8197F) & BIT_MASK_MGQ_HW_IDX_8197F) -#define BIT_SET_MGQ_HW_IDX_8197F(x, v) (BIT_CLEAR_MGQ_HW_IDX_8197F(x) | BIT_MGQ_HW_IDX_8197F(v)) - +#define BIT_GET_MGQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_HW_IDX_8197F) & BIT_MASK_MGQ_HW_IDX_8197F) +#define BIT_SET_MGQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_MGQ_HW_IDX_8197F(x) | BIT_MGQ_HW_IDX_8197F(v)) #define BIT_SHIFT_MGQ_HOST_IDX_8197F 0 #define BIT_MASK_MGQ_HOST_IDX_8197F 0xfff -#define BIT_MGQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8197F) << BIT_SHIFT_MGQ_HOST_IDX_8197F) -#define BITS_MGQ_HOST_IDX_8197F (BIT_MASK_MGQ_HOST_IDX_8197F << BIT_SHIFT_MGQ_HOST_IDX_8197F) +#define BIT_MGQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_MGQ_HOST_IDX_8197F) << BIT_SHIFT_MGQ_HOST_IDX_8197F) +#define BITS_MGQ_HOST_IDX_8197F \ + (BIT_MASK_MGQ_HOST_IDX_8197F << BIT_SHIFT_MGQ_HOST_IDX_8197F) #define BIT_CLEAR_MGQ_HOST_IDX_8197F(x) ((x) & (~BITS_MGQ_HOST_IDX_8197F)) -#define BIT_GET_MGQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8197F) & BIT_MASK_MGQ_HOST_IDX_8197F) -#define BIT_SET_MGQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_MGQ_HOST_IDX_8197F(x) | BIT_MGQ_HOST_IDX_8197F(v)) - +#define BIT_GET_MGQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8197F) & BIT_MASK_MGQ_HOST_IDX_8197F) +#define BIT_SET_MGQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_MGQ_HOST_IDX_8197F(x) | BIT_MGQ_HOST_IDX_8197F(v)) /* 2 REG_RXQ_RXBD_IDX_8197F */ #define BIT_SHIFT_RXQ_HW_IDX_8197F 16 #define BIT_MASK_RXQ_HW_IDX_8197F 0xfff -#define BIT_RXQ_HW_IDX_8197F(x) (((x) & BIT_MASK_RXQ_HW_IDX_8197F) << BIT_SHIFT_RXQ_HW_IDX_8197F) -#define BITS_RXQ_HW_IDX_8197F (BIT_MASK_RXQ_HW_IDX_8197F << BIT_SHIFT_RXQ_HW_IDX_8197F) +#define BIT_RXQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_RXQ_HW_IDX_8197F) << BIT_SHIFT_RXQ_HW_IDX_8197F) +#define BITS_RXQ_HW_IDX_8197F \ + (BIT_MASK_RXQ_HW_IDX_8197F << BIT_SHIFT_RXQ_HW_IDX_8197F) #define BIT_CLEAR_RXQ_HW_IDX_8197F(x) ((x) & (~BITS_RXQ_HW_IDX_8197F)) -#define BIT_GET_RXQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8197F) & BIT_MASK_RXQ_HW_IDX_8197F) -#define BIT_SET_RXQ_HW_IDX_8197F(x, v) (BIT_CLEAR_RXQ_HW_IDX_8197F(x) | BIT_RXQ_HW_IDX_8197F(v)) - +#define BIT_GET_RXQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RXQ_HW_IDX_8197F) & BIT_MASK_RXQ_HW_IDX_8197F) +#define BIT_SET_RXQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_RXQ_HW_IDX_8197F(x) | BIT_RXQ_HW_IDX_8197F(v)) #define BIT_SHIFT_RXQ_HOST_IDX_8197F 0 #define BIT_MASK_RXQ_HOST_IDX_8197F 0xfff -#define BIT_RXQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8197F) << BIT_SHIFT_RXQ_HOST_IDX_8197F) -#define BITS_RXQ_HOST_IDX_8197F (BIT_MASK_RXQ_HOST_IDX_8197F << BIT_SHIFT_RXQ_HOST_IDX_8197F) +#define BIT_RXQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_RXQ_HOST_IDX_8197F) << BIT_SHIFT_RXQ_HOST_IDX_8197F) +#define BITS_RXQ_HOST_IDX_8197F \ + (BIT_MASK_RXQ_HOST_IDX_8197F << BIT_SHIFT_RXQ_HOST_IDX_8197F) #define BIT_CLEAR_RXQ_HOST_IDX_8197F(x) ((x) & (~BITS_RXQ_HOST_IDX_8197F)) -#define BIT_GET_RXQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8197F) & BIT_MASK_RXQ_HOST_IDX_8197F) -#define BIT_SET_RXQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_RXQ_HOST_IDX_8197F(x) | BIT_RXQ_HOST_IDX_8197F(v)) - +#define BIT_GET_RXQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8197F) & BIT_MASK_RXQ_HOST_IDX_8197F) +#define BIT_SET_RXQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_RXQ_HOST_IDX_8197F(x) | BIT_RXQ_HOST_IDX_8197F(v)) /* 2 REG_HI0Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI0Q_HW_IDX_8197F 16 #define BIT_MASK_HI0Q_HW_IDX_8197F 0xfff -#define BIT_HI0Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8197F) << BIT_SHIFT_HI0Q_HW_IDX_8197F) -#define BITS_HI0Q_HW_IDX_8197F (BIT_MASK_HI0Q_HW_IDX_8197F << BIT_SHIFT_HI0Q_HW_IDX_8197F) +#define BIT_HI0Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI0Q_HW_IDX_8197F) << BIT_SHIFT_HI0Q_HW_IDX_8197F) +#define BITS_HI0Q_HW_IDX_8197F \ + (BIT_MASK_HI0Q_HW_IDX_8197F << BIT_SHIFT_HI0Q_HW_IDX_8197F) #define BIT_CLEAR_HI0Q_HW_IDX_8197F(x) ((x) & (~BITS_HI0Q_HW_IDX_8197F)) -#define BIT_GET_HI0Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8197F) & BIT_MASK_HI0Q_HW_IDX_8197F) -#define BIT_SET_HI0Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI0Q_HW_IDX_8197F(x) | BIT_HI0Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI0Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8197F) & BIT_MASK_HI0Q_HW_IDX_8197F) +#define BIT_SET_HI0Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI0Q_HW_IDX_8197F(x) | BIT_HI0Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI0Q_HOST_IDX_8197F 0 #define BIT_MASK_HI0Q_HOST_IDX_8197F 0xfff -#define BIT_HI0Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8197F) << BIT_SHIFT_HI0Q_HOST_IDX_8197F) -#define BITS_HI0Q_HOST_IDX_8197F (BIT_MASK_HI0Q_HOST_IDX_8197F << BIT_SHIFT_HI0Q_HOST_IDX_8197F) +#define BIT_HI0Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI0Q_HOST_IDX_8197F) << BIT_SHIFT_HI0Q_HOST_IDX_8197F) +#define BITS_HI0Q_HOST_IDX_8197F \ + (BIT_MASK_HI0Q_HOST_IDX_8197F << BIT_SHIFT_HI0Q_HOST_IDX_8197F) #define BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI0Q_HOST_IDX_8197F)) -#define BIT_GET_HI0Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8197F) & BIT_MASK_HI0Q_HOST_IDX_8197F) -#define BIT_SET_HI0Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) | BIT_HI0Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI0Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8197F) & BIT_MASK_HI0Q_HOST_IDX_8197F) +#define BIT_SET_HI0Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) | BIT_HI0Q_HOST_IDX_8197F(v)) /* 2 REG_HI1Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI1Q_HW_IDX_8197F 16 #define BIT_MASK_HI1Q_HW_IDX_8197F 0xfff -#define BIT_HI1Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8197F) << BIT_SHIFT_HI1Q_HW_IDX_8197F) -#define BITS_HI1Q_HW_IDX_8197F (BIT_MASK_HI1Q_HW_IDX_8197F << BIT_SHIFT_HI1Q_HW_IDX_8197F) +#define BIT_HI1Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI1Q_HW_IDX_8197F) << BIT_SHIFT_HI1Q_HW_IDX_8197F) +#define BITS_HI1Q_HW_IDX_8197F \ + (BIT_MASK_HI1Q_HW_IDX_8197F << BIT_SHIFT_HI1Q_HW_IDX_8197F) #define BIT_CLEAR_HI1Q_HW_IDX_8197F(x) ((x) & (~BITS_HI1Q_HW_IDX_8197F)) -#define BIT_GET_HI1Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8197F) & BIT_MASK_HI1Q_HW_IDX_8197F) -#define BIT_SET_HI1Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI1Q_HW_IDX_8197F(x) | BIT_HI1Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI1Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8197F) & BIT_MASK_HI1Q_HW_IDX_8197F) +#define BIT_SET_HI1Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI1Q_HW_IDX_8197F(x) | BIT_HI1Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI1Q_HOST_IDX_8197F 0 #define BIT_MASK_HI1Q_HOST_IDX_8197F 0xfff -#define BIT_HI1Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8197F) << BIT_SHIFT_HI1Q_HOST_IDX_8197F) -#define BITS_HI1Q_HOST_IDX_8197F (BIT_MASK_HI1Q_HOST_IDX_8197F << BIT_SHIFT_HI1Q_HOST_IDX_8197F) +#define BIT_HI1Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI1Q_HOST_IDX_8197F) << BIT_SHIFT_HI1Q_HOST_IDX_8197F) +#define BITS_HI1Q_HOST_IDX_8197F \ + (BIT_MASK_HI1Q_HOST_IDX_8197F << BIT_SHIFT_HI1Q_HOST_IDX_8197F) #define BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI1Q_HOST_IDX_8197F)) -#define BIT_GET_HI1Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8197F) & BIT_MASK_HI1Q_HOST_IDX_8197F) -#define BIT_SET_HI1Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) | BIT_HI1Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI1Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8197F) & BIT_MASK_HI1Q_HOST_IDX_8197F) +#define BIT_SET_HI1Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) | BIT_HI1Q_HOST_IDX_8197F(v)) /* 2 REG_HI2Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI2Q_HW_IDX_8197F 16 #define BIT_MASK_HI2Q_HW_IDX_8197F 0xfff -#define BIT_HI2Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8197F) << BIT_SHIFT_HI2Q_HW_IDX_8197F) -#define BITS_HI2Q_HW_IDX_8197F (BIT_MASK_HI2Q_HW_IDX_8197F << BIT_SHIFT_HI2Q_HW_IDX_8197F) +#define BIT_HI2Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI2Q_HW_IDX_8197F) << BIT_SHIFT_HI2Q_HW_IDX_8197F) +#define BITS_HI2Q_HW_IDX_8197F \ + (BIT_MASK_HI2Q_HW_IDX_8197F << BIT_SHIFT_HI2Q_HW_IDX_8197F) #define BIT_CLEAR_HI2Q_HW_IDX_8197F(x) ((x) & (~BITS_HI2Q_HW_IDX_8197F)) -#define BIT_GET_HI2Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8197F) & BIT_MASK_HI2Q_HW_IDX_8197F) -#define BIT_SET_HI2Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI2Q_HW_IDX_8197F(x) | BIT_HI2Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI2Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8197F) & BIT_MASK_HI2Q_HW_IDX_8197F) +#define BIT_SET_HI2Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI2Q_HW_IDX_8197F(x) | BIT_HI2Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI2Q_HOST_IDX_8197F 0 #define BIT_MASK_HI2Q_HOST_IDX_8197F 0xfff -#define BIT_HI2Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8197F) << BIT_SHIFT_HI2Q_HOST_IDX_8197F) -#define BITS_HI2Q_HOST_IDX_8197F (BIT_MASK_HI2Q_HOST_IDX_8197F << BIT_SHIFT_HI2Q_HOST_IDX_8197F) +#define BIT_HI2Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI2Q_HOST_IDX_8197F) << BIT_SHIFT_HI2Q_HOST_IDX_8197F) +#define BITS_HI2Q_HOST_IDX_8197F \ + (BIT_MASK_HI2Q_HOST_IDX_8197F << BIT_SHIFT_HI2Q_HOST_IDX_8197F) #define BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI2Q_HOST_IDX_8197F)) -#define BIT_GET_HI2Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8197F) & BIT_MASK_HI2Q_HOST_IDX_8197F) -#define BIT_SET_HI2Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) | BIT_HI2Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI2Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8197F) & BIT_MASK_HI2Q_HOST_IDX_8197F) +#define BIT_SET_HI2Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) | BIT_HI2Q_HOST_IDX_8197F(v)) /* 2 REG_HI3Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI3Q_HW_IDX_8197F 16 #define BIT_MASK_HI3Q_HW_IDX_8197F 0xfff -#define BIT_HI3Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8197F) << BIT_SHIFT_HI3Q_HW_IDX_8197F) -#define BITS_HI3Q_HW_IDX_8197F (BIT_MASK_HI3Q_HW_IDX_8197F << BIT_SHIFT_HI3Q_HW_IDX_8197F) +#define BIT_HI3Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI3Q_HW_IDX_8197F) << BIT_SHIFT_HI3Q_HW_IDX_8197F) +#define BITS_HI3Q_HW_IDX_8197F \ + (BIT_MASK_HI3Q_HW_IDX_8197F << BIT_SHIFT_HI3Q_HW_IDX_8197F) #define BIT_CLEAR_HI3Q_HW_IDX_8197F(x) ((x) & (~BITS_HI3Q_HW_IDX_8197F)) -#define BIT_GET_HI3Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8197F) & BIT_MASK_HI3Q_HW_IDX_8197F) -#define BIT_SET_HI3Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI3Q_HW_IDX_8197F(x) | BIT_HI3Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI3Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8197F) & BIT_MASK_HI3Q_HW_IDX_8197F) +#define BIT_SET_HI3Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI3Q_HW_IDX_8197F(x) | BIT_HI3Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI3Q_HOST_IDX_8197F 0 #define BIT_MASK_HI3Q_HOST_IDX_8197F 0xfff -#define BIT_HI3Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8197F) << BIT_SHIFT_HI3Q_HOST_IDX_8197F) -#define BITS_HI3Q_HOST_IDX_8197F (BIT_MASK_HI3Q_HOST_IDX_8197F << BIT_SHIFT_HI3Q_HOST_IDX_8197F) +#define BIT_HI3Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI3Q_HOST_IDX_8197F) << BIT_SHIFT_HI3Q_HOST_IDX_8197F) +#define BITS_HI3Q_HOST_IDX_8197F \ + (BIT_MASK_HI3Q_HOST_IDX_8197F << BIT_SHIFT_HI3Q_HOST_IDX_8197F) #define BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI3Q_HOST_IDX_8197F)) -#define BIT_GET_HI3Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8197F) & BIT_MASK_HI3Q_HOST_IDX_8197F) -#define BIT_SET_HI3Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) | BIT_HI3Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI3Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8197F) & BIT_MASK_HI3Q_HOST_IDX_8197F) +#define BIT_SET_HI3Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) | BIT_HI3Q_HOST_IDX_8197F(v)) /* 2 REG_HI4Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI4Q_HW_IDX_8197F 16 #define BIT_MASK_HI4Q_HW_IDX_8197F 0xfff -#define BIT_HI4Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8197F) << BIT_SHIFT_HI4Q_HW_IDX_8197F) -#define BITS_HI4Q_HW_IDX_8197F (BIT_MASK_HI4Q_HW_IDX_8197F << BIT_SHIFT_HI4Q_HW_IDX_8197F) +#define BIT_HI4Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI4Q_HW_IDX_8197F) << BIT_SHIFT_HI4Q_HW_IDX_8197F) +#define BITS_HI4Q_HW_IDX_8197F \ + (BIT_MASK_HI4Q_HW_IDX_8197F << BIT_SHIFT_HI4Q_HW_IDX_8197F) #define BIT_CLEAR_HI4Q_HW_IDX_8197F(x) ((x) & (~BITS_HI4Q_HW_IDX_8197F)) -#define BIT_GET_HI4Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8197F) & BIT_MASK_HI4Q_HW_IDX_8197F) -#define BIT_SET_HI4Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI4Q_HW_IDX_8197F(x) | BIT_HI4Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI4Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8197F) & BIT_MASK_HI4Q_HW_IDX_8197F) +#define BIT_SET_HI4Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI4Q_HW_IDX_8197F(x) | BIT_HI4Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI4Q_HOST_IDX_8197F 0 #define BIT_MASK_HI4Q_HOST_IDX_8197F 0xfff -#define BIT_HI4Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8197F) << BIT_SHIFT_HI4Q_HOST_IDX_8197F) -#define BITS_HI4Q_HOST_IDX_8197F (BIT_MASK_HI4Q_HOST_IDX_8197F << BIT_SHIFT_HI4Q_HOST_IDX_8197F) +#define BIT_HI4Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI4Q_HOST_IDX_8197F) << BIT_SHIFT_HI4Q_HOST_IDX_8197F) +#define BITS_HI4Q_HOST_IDX_8197F \ + (BIT_MASK_HI4Q_HOST_IDX_8197F << BIT_SHIFT_HI4Q_HOST_IDX_8197F) #define BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI4Q_HOST_IDX_8197F)) -#define BIT_GET_HI4Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8197F) & BIT_MASK_HI4Q_HOST_IDX_8197F) -#define BIT_SET_HI4Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) | BIT_HI4Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI4Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8197F) & BIT_MASK_HI4Q_HOST_IDX_8197F) +#define BIT_SET_HI4Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) | BIT_HI4Q_HOST_IDX_8197F(v)) /* 2 REG_HI5Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI5Q_HW_IDX_8197F 16 #define BIT_MASK_HI5Q_HW_IDX_8197F 0xfff -#define BIT_HI5Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8197F) << BIT_SHIFT_HI5Q_HW_IDX_8197F) -#define BITS_HI5Q_HW_IDX_8197F (BIT_MASK_HI5Q_HW_IDX_8197F << BIT_SHIFT_HI5Q_HW_IDX_8197F) +#define BIT_HI5Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI5Q_HW_IDX_8197F) << BIT_SHIFT_HI5Q_HW_IDX_8197F) +#define BITS_HI5Q_HW_IDX_8197F \ + (BIT_MASK_HI5Q_HW_IDX_8197F << BIT_SHIFT_HI5Q_HW_IDX_8197F) #define BIT_CLEAR_HI5Q_HW_IDX_8197F(x) ((x) & (~BITS_HI5Q_HW_IDX_8197F)) -#define BIT_GET_HI5Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8197F) & BIT_MASK_HI5Q_HW_IDX_8197F) -#define BIT_SET_HI5Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI5Q_HW_IDX_8197F(x) | BIT_HI5Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI5Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8197F) & BIT_MASK_HI5Q_HW_IDX_8197F) +#define BIT_SET_HI5Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI5Q_HW_IDX_8197F(x) | BIT_HI5Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI5Q_HOST_IDX_8197F 0 #define BIT_MASK_HI5Q_HOST_IDX_8197F 0xfff -#define BIT_HI5Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8197F) << BIT_SHIFT_HI5Q_HOST_IDX_8197F) -#define BITS_HI5Q_HOST_IDX_8197F (BIT_MASK_HI5Q_HOST_IDX_8197F << BIT_SHIFT_HI5Q_HOST_IDX_8197F) +#define BIT_HI5Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI5Q_HOST_IDX_8197F) << BIT_SHIFT_HI5Q_HOST_IDX_8197F) +#define BITS_HI5Q_HOST_IDX_8197F \ + (BIT_MASK_HI5Q_HOST_IDX_8197F << BIT_SHIFT_HI5Q_HOST_IDX_8197F) #define BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI5Q_HOST_IDX_8197F)) -#define BIT_GET_HI5Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8197F) & BIT_MASK_HI5Q_HOST_IDX_8197F) -#define BIT_SET_HI5Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) | BIT_HI5Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI5Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8197F) & BIT_MASK_HI5Q_HOST_IDX_8197F) +#define BIT_SET_HI5Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) | BIT_HI5Q_HOST_IDX_8197F(v)) /* 2 REG_HI6Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI6Q_HW_IDX_8197F 16 #define BIT_MASK_HI6Q_HW_IDX_8197F 0xfff -#define BIT_HI6Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8197F) << BIT_SHIFT_HI6Q_HW_IDX_8197F) -#define BITS_HI6Q_HW_IDX_8197F (BIT_MASK_HI6Q_HW_IDX_8197F << BIT_SHIFT_HI6Q_HW_IDX_8197F) +#define BIT_HI6Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI6Q_HW_IDX_8197F) << BIT_SHIFT_HI6Q_HW_IDX_8197F) +#define BITS_HI6Q_HW_IDX_8197F \ + (BIT_MASK_HI6Q_HW_IDX_8197F << BIT_SHIFT_HI6Q_HW_IDX_8197F) #define BIT_CLEAR_HI6Q_HW_IDX_8197F(x) ((x) & (~BITS_HI6Q_HW_IDX_8197F)) -#define BIT_GET_HI6Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8197F) & BIT_MASK_HI6Q_HW_IDX_8197F) -#define BIT_SET_HI6Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI6Q_HW_IDX_8197F(x) | BIT_HI6Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI6Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8197F) & BIT_MASK_HI6Q_HW_IDX_8197F) +#define BIT_SET_HI6Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI6Q_HW_IDX_8197F(x) | BIT_HI6Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI6Q_HOST_IDX_8197F 0 #define BIT_MASK_HI6Q_HOST_IDX_8197F 0xfff -#define BIT_HI6Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8197F) << BIT_SHIFT_HI6Q_HOST_IDX_8197F) -#define BITS_HI6Q_HOST_IDX_8197F (BIT_MASK_HI6Q_HOST_IDX_8197F << BIT_SHIFT_HI6Q_HOST_IDX_8197F) +#define BIT_HI6Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI6Q_HOST_IDX_8197F) << BIT_SHIFT_HI6Q_HOST_IDX_8197F) +#define BITS_HI6Q_HOST_IDX_8197F \ + (BIT_MASK_HI6Q_HOST_IDX_8197F << BIT_SHIFT_HI6Q_HOST_IDX_8197F) #define BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI6Q_HOST_IDX_8197F)) -#define BIT_GET_HI6Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8197F) & BIT_MASK_HI6Q_HOST_IDX_8197F) -#define BIT_SET_HI6Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) | BIT_HI6Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI6Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8197F) & BIT_MASK_HI6Q_HOST_IDX_8197F) +#define BIT_SET_HI6Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) | BIT_HI6Q_HOST_IDX_8197F(v)) /* 2 REG_HI7Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI7Q_HW_IDX_8197F 16 #define BIT_MASK_HI7Q_HW_IDX_8197F 0xfff -#define BIT_HI7Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8197F) << BIT_SHIFT_HI7Q_HW_IDX_8197F) -#define BITS_HI7Q_HW_IDX_8197F (BIT_MASK_HI7Q_HW_IDX_8197F << BIT_SHIFT_HI7Q_HW_IDX_8197F) +#define BIT_HI7Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI7Q_HW_IDX_8197F) << BIT_SHIFT_HI7Q_HW_IDX_8197F) +#define BITS_HI7Q_HW_IDX_8197F \ + (BIT_MASK_HI7Q_HW_IDX_8197F << BIT_SHIFT_HI7Q_HW_IDX_8197F) #define BIT_CLEAR_HI7Q_HW_IDX_8197F(x) ((x) & (~BITS_HI7Q_HW_IDX_8197F)) -#define BIT_GET_HI7Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8197F) & BIT_MASK_HI7Q_HW_IDX_8197F) -#define BIT_SET_HI7Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI7Q_HW_IDX_8197F(x) | BIT_HI7Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI7Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8197F) & BIT_MASK_HI7Q_HW_IDX_8197F) +#define BIT_SET_HI7Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI7Q_HW_IDX_8197F(x) | BIT_HI7Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI7Q_HOST_IDX_8197F 0 #define BIT_MASK_HI7Q_HOST_IDX_8197F 0xfff -#define BIT_HI7Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8197F) << BIT_SHIFT_HI7Q_HOST_IDX_8197F) -#define BITS_HI7Q_HOST_IDX_8197F (BIT_MASK_HI7Q_HOST_IDX_8197F << BIT_SHIFT_HI7Q_HOST_IDX_8197F) +#define BIT_HI7Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI7Q_HOST_IDX_8197F) << BIT_SHIFT_HI7Q_HOST_IDX_8197F) +#define BITS_HI7Q_HOST_IDX_8197F \ + (BIT_MASK_HI7Q_HOST_IDX_8197F << BIT_SHIFT_HI7Q_HOST_IDX_8197F) #define BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI7Q_HOST_IDX_8197F)) -#define BIT_GET_HI7Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8197F) & BIT_MASK_HI7Q_HOST_IDX_8197F) -#define BIT_SET_HI7Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) | BIT_HI7Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI7Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8197F) & BIT_MASK_HI7Q_HOST_IDX_8197F) +#define BIT_SET_HI7Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) | BIT_HI7Q_HOST_IDX_8197F(v)) /* 2 REG_DBG_SEL_V1_8197F */ #define BIT_SHIFT_DBG_SEL_8197F 0 #define BIT_MASK_DBG_SEL_8197F 0xff -#define BIT_DBG_SEL_8197F(x) (((x) & BIT_MASK_DBG_SEL_8197F) << BIT_SHIFT_DBG_SEL_8197F) +#define BIT_DBG_SEL_8197F(x) \ + (((x) & BIT_MASK_DBG_SEL_8197F) << BIT_SHIFT_DBG_SEL_8197F) #define BITS_DBG_SEL_8197F (BIT_MASK_DBG_SEL_8197F << BIT_SHIFT_DBG_SEL_8197F) #define BIT_CLEAR_DBG_SEL_8197F(x) ((x) & (~BITS_DBG_SEL_8197F)) -#define BIT_GET_DBG_SEL_8197F(x) (((x) >> BIT_SHIFT_DBG_SEL_8197F) & BIT_MASK_DBG_SEL_8197F) -#define BIT_SET_DBG_SEL_8197F(x, v) (BIT_CLEAR_DBG_SEL_8197F(x) | BIT_DBG_SEL_8197F(v)) - +#define BIT_GET_DBG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_8197F) & BIT_MASK_DBG_SEL_8197F) +#define BIT_SET_DBG_SEL_8197F(x, v) \ + (BIT_CLEAR_DBG_SEL_8197F(x) | BIT_DBG_SEL_8197F(v)) /* 2 REG_HCI_HRPWM1_V1_8197F */ #define BIT_SHIFT_HCI_HRPWM_8197F 0 #define BIT_MASK_HCI_HRPWM_8197F 0xff -#define BIT_HCI_HRPWM_8197F(x) (((x) & BIT_MASK_HCI_HRPWM_8197F) << BIT_SHIFT_HCI_HRPWM_8197F) -#define BITS_HCI_HRPWM_8197F (BIT_MASK_HCI_HRPWM_8197F << BIT_SHIFT_HCI_HRPWM_8197F) +#define BIT_HCI_HRPWM_8197F(x) \ + (((x) & BIT_MASK_HCI_HRPWM_8197F) << BIT_SHIFT_HCI_HRPWM_8197F) +#define BITS_HCI_HRPWM_8197F \ + (BIT_MASK_HCI_HRPWM_8197F << BIT_SHIFT_HCI_HRPWM_8197F) #define BIT_CLEAR_HCI_HRPWM_8197F(x) ((x) & (~BITS_HCI_HRPWM_8197F)) -#define BIT_GET_HCI_HRPWM_8197F(x) (((x) >> BIT_SHIFT_HCI_HRPWM_8197F) & BIT_MASK_HCI_HRPWM_8197F) -#define BIT_SET_HCI_HRPWM_8197F(x, v) (BIT_CLEAR_HCI_HRPWM_8197F(x) | BIT_HCI_HRPWM_8197F(v)) - +#define BIT_GET_HCI_HRPWM_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_HRPWM_8197F) & BIT_MASK_HCI_HRPWM_8197F) +#define BIT_SET_HCI_HRPWM_8197F(x, v) \ + (BIT_CLEAR_HCI_HRPWM_8197F(x) | BIT_HCI_HRPWM_8197F(v)) /* 2 REG_HCI_HCPWM1_V1_8197F */ #define BIT_SHIFT_HCI_HCPWM_8197F 0 #define BIT_MASK_HCI_HCPWM_8197F 0xff -#define BIT_HCI_HCPWM_8197F(x) (((x) & BIT_MASK_HCI_HCPWM_8197F) << BIT_SHIFT_HCI_HCPWM_8197F) -#define BITS_HCI_HCPWM_8197F (BIT_MASK_HCI_HCPWM_8197F << BIT_SHIFT_HCI_HCPWM_8197F) +#define BIT_HCI_HCPWM_8197F(x) \ + (((x) & BIT_MASK_HCI_HCPWM_8197F) << BIT_SHIFT_HCI_HCPWM_8197F) +#define BITS_HCI_HCPWM_8197F \ + (BIT_MASK_HCI_HCPWM_8197F << BIT_SHIFT_HCI_HCPWM_8197F) #define BIT_CLEAR_HCI_HCPWM_8197F(x) ((x) & (~BITS_HCI_HCPWM_8197F)) -#define BIT_GET_HCI_HCPWM_8197F(x) (((x) >> BIT_SHIFT_HCI_HCPWM_8197F) & BIT_MASK_HCI_HCPWM_8197F) -#define BIT_SET_HCI_HCPWM_8197F(x, v) (BIT_CLEAR_HCI_HCPWM_8197F(x) | BIT_HCI_HCPWM_8197F(v)) - +#define BIT_GET_HCI_HCPWM_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_HCPWM_8197F) & BIT_MASK_HCI_HCPWM_8197F) +#define BIT_SET_HCI_HCPWM_8197F(x, v) \ + (BIT_CLEAR_HCI_HCPWM_8197F(x) | BIT_HCI_HCPWM_8197F(v)) /* 2 REG_HCI_CTRL2_8197F */ #define BIT_DIS_TXDMA_PRE_8197F BIT(7) @@ -5757,11 +7261,15 @@ #define BIT_SHIFT_HPS_CLKR_HCI_8197F 4 #define BIT_MASK_HPS_CLKR_HCI_8197F 0x3 -#define BIT_HPS_CLKR_HCI_8197F(x) (((x) & BIT_MASK_HPS_CLKR_HCI_8197F) << BIT_SHIFT_HPS_CLKR_HCI_8197F) -#define BITS_HPS_CLKR_HCI_8197F (BIT_MASK_HPS_CLKR_HCI_8197F << BIT_SHIFT_HPS_CLKR_HCI_8197F) +#define BIT_HPS_CLKR_HCI_8197F(x) \ + (((x) & BIT_MASK_HPS_CLKR_HCI_8197F) << BIT_SHIFT_HPS_CLKR_HCI_8197F) +#define BITS_HPS_CLKR_HCI_8197F \ + (BIT_MASK_HPS_CLKR_HCI_8197F << BIT_SHIFT_HPS_CLKR_HCI_8197F) #define BIT_CLEAR_HPS_CLKR_HCI_8197F(x) ((x) & (~BITS_HPS_CLKR_HCI_8197F)) -#define BIT_GET_HPS_CLKR_HCI_8197F(x) (((x) >> BIT_SHIFT_HPS_CLKR_HCI_8197F) & BIT_MASK_HPS_CLKR_HCI_8197F) -#define BIT_SET_HPS_CLKR_HCI_8197F(x, v) (BIT_CLEAR_HPS_CLKR_HCI_8197F(x) | BIT_HPS_CLKR_HCI_8197F(v)) +#define BIT_GET_HPS_CLKR_HCI_8197F(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_HCI_8197F) & BIT_MASK_HPS_CLKR_HCI_8197F) +#define BIT_SET_HPS_CLKR_HCI_8197F(x, v) \ + (BIT_CLEAR_HPS_CLKR_HCI_8197F(x) | BIT_HPS_CLKR_HCI_8197F(v)) #define BIT_HCI_INT_8197F BIT(3) #define BIT_TXFLAG_EXIT_L1_EN_8197F BIT(2) @@ -5772,67 +7280,85 @@ #define BIT_SHIFT_HCI_HRPWM2_8197F 0 #define BIT_MASK_HCI_HRPWM2_8197F 0xffff -#define BIT_HCI_HRPWM2_8197F(x) (((x) & BIT_MASK_HCI_HRPWM2_8197F) << BIT_SHIFT_HCI_HRPWM2_8197F) -#define BITS_HCI_HRPWM2_8197F (BIT_MASK_HCI_HRPWM2_8197F << BIT_SHIFT_HCI_HRPWM2_8197F) +#define BIT_HCI_HRPWM2_8197F(x) \ + (((x) & BIT_MASK_HCI_HRPWM2_8197F) << BIT_SHIFT_HCI_HRPWM2_8197F) +#define BITS_HCI_HRPWM2_8197F \ + (BIT_MASK_HCI_HRPWM2_8197F << BIT_SHIFT_HCI_HRPWM2_8197F) #define BIT_CLEAR_HCI_HRPWM2_8197F(x) ((x) & (~BITS_HCI_HRPWM2_8197F)) -#define BIT_GET_HCI_HRPWM2_8197F(x) (((x) >> BIT_SHIFT_HCI_HRPWM2_8197F) & BIT_MASK_HCI_HRPWM2_8197F) -#define BIT_SET_HCI_HRPWM2_8197F(x, v) (BIT_CLEAR_HCI_HRPWM2_8197F(x) | BIT_HCI_HRPWM2_8197F(v)) - +#define BIT_GET_HCI_HRPWM2_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_HRPWM2_8197F) & BIT_MASK_HCI_HRPWM2_8197F) +#define BIT_SET_HCI_HRPWM2_8197F(x, v) \ + (BIT_CLEAR_HCI_HRPWM2_8197F(x) | BIT_HCI_HRPWM2_8197F(v)) /* 2 REG_HCI_HCPWM2_V1_8197F */ #define BIT_SHIFT_HCI_HCPWM2_8197F 0 #define BIT_MASK_HCI_HCPWM2_8197F 0xffff -#define BIT_HCI_HCPWM2_8197F(x) (((x) & BIT_MASK_HCI_HCPWM2_8197F) << BIT_SHIFT_HCI_HCPWM2_8197F) -#define BITS_HCI_HCPWM2_8197F (BIT_MASK_HCI_HCPWM2_8197F << BIT_SHIFT_HCI_HCPWM2_8197F) +#define BIT_HCI_HCPWM2_8197F(x) \ + (((x) & BIT_MASK_HCI_HCPWM2_8197F) << BIT_SHIFT_HCI_HCPWM2_8197F) +#define BITS_HCI_HCPWM2_8197F \ + (BIT_MASK_HCI_HCPWM2_8197F << BIT_SHIFT_HCI_HCPWM2_8197F) #define BIT_CLEAR_HCI_HCPWM2_8197F(x) ((x) & (~BITS_HCI_HCPWM2_8197F)) -#define BIT_GET_HCI_HCPWM2_8197F(x) (((x) >> BIT_SHIFT_HCI_HCPWM2_8197F) & BIT_MASK_HCI_HCPWM2_8197F) -#define BIT_SET_HCI_HCPWM2_8197F(x, v) (BIT_CLEAR_HCI_HCPWM2_8197F(x) | BIT_HCI_HCPWM2_8197F(v)) - +#define BIT_GET_HCI_HCPWM2_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_HCPWM2_8197F) & BIT_MASK_HCI_HCPWM2_8197F) +#define BIT_SET_HCI_HCPWM2_8197F(x, v) \ + (BIT_CLEAR_HCI_HCPWM2_8197F(x) | BIT_HCI_HCPWM2_8197F(v)) /* 2 REG_HCI_H2C_MSG_V1_8197F */ #define BIT_SHIFT_DRV2FW_INFO_8197F 0 #define BIT_MASK_DRV2FW_INFO_8197F 0xffffffffL -#define BIT_DRV2FW_INFO_8197F(x) (((x) & BIT_MASK_DRV2FW_INFO_8197F) << BIT_SHIFT_DRV2FW_INFO_8197F) -#define BITS_DRV2FW_INFO_8197F (BIT_MASK_DRV2FW_INFO_8197F << BIT_SHIFT_DRV2FW_INFO_8197F) +#define BIT_DRV2FW_INFO_8197F(x) \ + (((x) & BIT_MASK_DRV2FW_INFO_8197F) << BIT_SHIFT_DRV2FW_INFO_8197F) +#define BITS_DRV2FW_INFO_8197F \ + (BIT_MASK_DRV2FW_INFO_8197F << BIT_SHIFT_DRV2FW_INFO_8197F) #define BIT_CLEAR_DRV2FW_INFO_8197F(x) ((x) & (~BITS_DRV2FW_INFO_8197F)) -#define BIT_GET_DRV2FW_INFO_8197F(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8197F) & BIT_MASK_DRV2FW_INFO_8197F) -#define BIT_SET_DRV2FW_INFO_8197F(x, v) (BIT_CLEAR_DRV2FW_INFO_8197F(x) | BIT_DRV2FW_INFO_8197F(v)) - +#define BIT_GET_DRV2FW_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_DRV2FW_INFO_8197F) & BIT_MASK_DRV2FW_INFO_8197F) +#define BIT_SET_DRV2FW_INFO_8197F(x, v) \ + (BIT_CLEAR_DRV2FW_INFO_8197F(x) | BIT_DRV2FW_INFO_8197F(v)) /* 2 REG_HCI_C2H_MSG_V1_8197F */ #define BIT_SHIFT_HCI_C2H_MSG_8197F 0 #define BIT_MASK_HCI_C2H_MSG_8197F 0xffffffffL -#define BIT_HCI_C2H_MSG_8197F(x) (((x) & BIT_MASK_HCI_C2H_MSG_8197F) << BIT_SHIFT_HCI_C2H_MSG_8197F) -#define BITS_HCI_C2H_MSG_8197F (BIT_MASK_HCI_C2H_MSG_8197F << BIT_SHIFT_HCI_C2H_MSG_8197F) +#define BIT_HCI_C2H_MSG_8197F(x) \ + (((x) & BIT_MASK_HCI_C2H_MSG_8197F) << BIT_SHIFT_HCI_C2H_MSG_8197F) +#define BITS_HCI_C2H_MSG_8197F \ + (BIT_MASK_HCI_C2H_MSG_8197F << BIT_SHIFT_HCI_C2H_MSG_8197F) #define BIT_CLEAR_HCI_C2H_MSG_8197F(x) ((x) & (~BITS_HCI_C2H_MSG_8197F)) -#define BIT_GET_HCI_C2H_MSG_8197F(x) (((x) >> BIT_SHIFT_HCI_C2H_MSG_8197F) & BIT_MASK_HCI_C2H_MSG_8197F) -#define BIT_SET_HCI_C2H_MSG_8197F(x, v) (BIT_CLEAR_HCI_C2H_MSG_8197F(x) | BIT_HCI_C2H_MSG_8197F(v)) - +#define BIT_GET_HCI_C2H_MSG_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_C2H_MSG_8197F) & BIT_MASK_HCI_C2H_MSG_8197F) +#define BIT_SET_HCI_C2H_MSG_8197F(x, v) \ + (BIT_CLEAR_HCI_C2H_MSG_8197F(x) | BIT_HCI_C2H_MSG_8197F(v)) /* 2 REG_DBI_WDATA_V1_8197F */ #define BIT_SHIFT_DBI_WDATA_8197F 0 #define BIT_MASK_DBI_WDATA_8197F 0xffffffffL -#define BIT_DBI_WDATA_8197F(x) (((x) & BIT_MASK_DBI_WDATA_8197F) << BIT_SHIFT_DBI_WDATA_8197F) -#define BITS_DBI_WDATA_8197F (BIT_MASK_DBI_WDATA_8197F << BIT_SHIFT_DBI_WDATA_8197F) +#define BIT_DBI_WDATA_8197F(x) \ + (((x) & BIT_MASK_DBI_WDATA_8197F) << BIT_SHIFT_DBI_WDATA_8197F) +#define BITS_DBI_WDATA_8197F \ + (BIT_MASK_DBI_WDATA_8197F << BIT_SHIFT_DBI_WDATA_8197F) #define BIT_CLEAR_DBI_WDATA_8197F(x) ((x) & (~BITS_DBI_WDATA_8197F)) -#define BIT_GET_DBI_WDATA_8197F(x) (((x) >> BIT_SHIFT_DBI_WDATA_8197F) & BIT_MASK_DBI_WDATA_8197F) -#define BIT_SET_DBI_WDATA_8197F(x, v) (BIT_CLEAR_DBI_WDATA_8197F(x) | BIT_DBI_WDATA_8197F(v)) - +#define BIT_GET_DBI_WDATA_8197F(x) \ + (((x) >> BIT_SHIFT_DBI_WDATA_8197F) & BIT_MASK_DBI_WDATA_8197F) +#define BIT_SET_DBI_WDATA_8197F(x, v) \ + (BIT_CLEAR_DBI_WDATA_8197F(x) | BIT_DBI_WDATA_8197F(v)) /* 2 REG_DBI_RDATA_V1_8197F */ #define BIT_SHIFT_DBI_RDATA_8197F 0 #define BIT_MASK_DBI_RDATA_8197F 0xffffffffL -#define BIT_DBI_RDATA_8197F(x) (((x) & BIT_MASK_DBI_RDATA_8197F) << BIT_SHIFT_DBI_RDATA_8197F) -#define BITS_DBI_RDATA_8197F (BIT_MASK_DBI_RDATA_8197F << BIT_SHIFT_DBI_RDATA_8197F) +#define BIT_DBI_RDATA_8197F(x) \ + (((x) & BIT_MASK_DBI_RDATA_8197F) << BIT_SHIFT_DBI_RDATA_8197F) +#define BITS_DBI_RDATA_8197F \ + (BIT_MASK_DBI_RDATA_8197F << BIT_SHIFT_DBI_RDATA_8197F) #define BIT_CLEAR_DBI_RDATA_8197F(x) ((x) & (~BITS_DBI_RDATA_8197F)) -#define BIT_GET_DBI_RDATA_8197F(x) (((x) >> BIT_SHIFT_DBI_RDATA_8197F) & BIT_MASK_DBI_RDATA_8197F) -#define BIT_SET_DBI_RDATA_8197F(x, v) (BIT_CLEAR_DBI_RDATA_8197F(x) | BIT_DBI_RDATA_8197F(v)) - +#define BIT_GET_DBI_RDATA_8197F(x) \ + (((x) >> BIT_SHIFT_DBI_RDATA_8197F) & BIT_MASK_DBI_RDATA_8197F) +#define BIT_SET_DBI_RDATA_8197F(x, v) \ + (BIT_CLEAR_DBI_RDATA_8197F(x) | BIT_DBI_RDATA_8197F(v)) /* 2 REG_STUCK_FLAG_V1_8197F */ #define BIT_EN_STUCK_DBG_8197F BIT(26) @@ -5843,60 +7369,84 @@ #define BIT_SHIFT_DBI_WREN_8197F 12 #define BIT_MASK_DBI_WREN_8197F 0xf -#define BIT_DBI_WREN_8197F(x) (((x) & BIT_MASK_DBI_WREN_8197F) << BIT_SHIFT_DBI_WREN_8197F) -#define BITS_DBI_WREN_8197F (BIT_MASK_DBI_WREN_8197F << BIT_SHIFT_DBI_WREN_8197F) +#define BIT_DBI_WREN_8197F(x) \ + (((x) & BIT_MASK_DBI_WREN_8197F) << BIT_SHIFT_DBI_WREN_8197F) +#define BITS_DBI_WREN_8197F \ + (BIT_MASK_DBI_WREN_8197F << BIT_SHIFT_DBI_WREN_8197F) #define BIT_CLEAR_DBI_WREN_8197F(x) ((x) & (~BITS_DBI_WREN_8197F)) -#define BIT_GET_DBI_WREN_8197F(x) (((x) >> BIT_SHIFT_DBI_WREN_8197F) & BIT_MASK_DBI_WREN_8197F) -#define BIT_SET_DBI_WREN_8197F(x, v) (BIT_CLEAR_DBI_WREN_8197F(x) | BIT_DBI_WREN_8197F(v)) - +#define BIT_GET_DBI_WREN_8197F(x) \ + (((x) >> BIT_SHIFT_DBI_WREN_8197F) & BIT_MASK_DBI_WREN_8197F) +#define BIT_SET_DBI_WREN_8197F(x, v) \ + (BIT_CLEAR_DBI_WREN_8197F(x) | BIT_DBI_WREN_8197F(v)) #define BIT_SHIFT_DBI_ADDR_8197F 0 #define BIT_MASK_DBI_ADDR_8197F 0xfff -#define BIT_DBI_ADDR_8197F(x) (((x) & BIT_MASK_DBI_ADDR_8197F) << BIT_SHIFT_DBI_ADDR_8197F) -#define BITS_DBI_ADDR_8197F (BIT_MASK_DBI_ADDR_8197F << BIT_SHIFT_DBI_ADDR_8197F) +#define BIT_DBI_ADDR_8197F(x) \ + (((x) & BIT_MASK_DBI_ADDR_8197F) << BIT_SHIFT_DBI_ADDR_8197F) +#define BITS_DBI_ADDR_8197F \ + (BIT_MASK_DBI_ADDR_8197F << BIT_SHIFT_DBI_ADDR_8197F) #define BIT_CLEAR_DBI_ADDR_8197F(x) ((x) & (~BITS_DBI_ADDR_8197F)) -#define BIT_GET_DBI_ADDR_8197F(x) (((x) >> BIT_SHIFT_DBI_ADDR_8197F) & BIT_MASK_DBI_ADDR_8197F) -#define BIT_SET_DBI_ADDR_8197F(x, v) (BIT_CLEAR_DBI_ADDR_8197F(x) | BIT_DBI_ADDR_8197F(v)) - +#define BIT_GET_DBI_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_DBI_ADDR_8197F) & BIT_MASK_DBI_ADDR_8197F) +#define BIT_SET_DBI_ADDR_8197F(x, v) \ + (BIT_CLEAR_DBI_ADDR_8197F(x) | BIT_DBI_ADDR_8197F(v)) /* 2 REG_MDIO_V1_8197F */ #define BIT_SHIFT_MDIO_RDATA_8197F 16 #define BIT_MASK_MDIO_RDATA_8197F 0xffff -#define BIT_MDIO_RDATA_8197F(x) (((x) & BIT_MASK_MDIO_RDATA_8197F) << BIT_SHIFT_MDIO_RDATA_8197F) -#define BITS_MDIO_RDATA_8197F (BIT_MASK_MDIO_RDATA_8197F << BIT_SHIFT_MDIO_RDATA_8197F) +#define BIT_MDIO_RDATA_8197F(x) \ + (((x) & BIT_MASK_MDIO_RDATA_8197F) << BIT_SHIFT_MDIO_RDATA_8197F) +#define BITS_MDIO_RDATA_8197F \ + (BIT_MASK_MDIO_RDATA_8197F << BIT_SHIFT_MDIO_RDATA_8197F) #define BIT_CLEAR_MDIO_RDATA_8197F(x) ((x) & (~BITS_MDIO_RDATA_8197F)) -#define BIT_GET_MDIO_RDATA_8197F(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8197F) & BIT_MASK_MDIO_RDATA_8197F) -#define BIT_SET_MDIO_RDATA_8197F(x, v) (BIT_CLEAR_MDIO_RDATA_8197F(x) | BIT_MDIO_RDATA_8197F(v)) - +#define BIT_GET_MDIO_RDATA_8197F(x) \ + (((x) >> BIT_SHIFT_MDIO_RDATA_8197F) & BIT_MASK_MDIO_RDATA_8197F) +#define BIT_SET_MDIO_RDATA_8197F(x, v) \ + (BIT_CLEAR_MDIO_RDATA_8197F(x) | BIT_MDIO_RDATA_8197F(v)) #define BIT_SHIFT_MDIO_WDATA_8197F 0 #define BIT_MASK_MDIO_WDATA_8197F 0xffff -#define BIT_MDIO_WDATA_8197F(x) (((x) & BIT_MASK_MDIO_WDATA_8197F) << BIT_SHIFT_MDIO_WDATA_8197F) -#define BITS_MDIO_WDATA_8197F (BIT_MASK_MDIO_WDATA_8197F << BIT_SHIFT_MDIO_WDATA_8197F) +#define BIT_MDIO_WDATA_8197F(x) \ + (((x) & BIT_MASK_MDIO_WDATA_8197F) << BIT_SHIFT_MDIO_WDATA_8197F) +#define BITS_MDIO_WDATA_8197F \ + (BIT_MASK_MDIO_WDATA_8197F << BIT_SHIFT_MDIO_WDATA_8197F) #define BIT_CLEAR_MDIO_WDATA_8197F(x) ((x) & (~BITS_MDIO_WDATA_8197F)) -#define BIT_GET_MDIO_WDATA_8197F(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8197F) & BIT_MASK_MDIO_WDATA_8197F) -#define BIT_SET_MDIO_WDATA_8197F(x, v) (BIT_CLEAR_MDIO_WDATA_8197F(x) | BIT_MDIO_WDATA_8197F(v)) - +#define BIT_GET_MDIO_WDATA_8197F(x) \ + (((x) >> BIT_SHIFT_MDIO_WDATA_8197F) & BIT_MASK_MDIO_WDATA_8197F) +#define BIT_SET_MDIO_WDATA_8197F(x, v) \ + (BIT_CLEAR_MDIO_WDATA_8197F(x) | BIT_MDIO_WDATA_8197F(v)) /* 2 REG_WDT_CFG_8197F */ #define BIT_SHIFT_MDIO_PHY_ADDR_8197F 24 #define BIT_MASK_MDIO_PHY_ADDR_8197F 0x1f -#define BIT_MDIO_PHY_ADDR_8197F(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8197F) << BIT_SHIFT_MDIO_PHY_ADDR_8197F) -#define BITS_MDIO_PHY_ADDR_8197F (BIT_MASK_MDIO_PHY_ADDR_8197F << BIT_SHIFT_MDIO_PHY_ADDR_8197F) +#define BIT_MDIO_PHY_ADDR_8197F(x) \ + (((x) & BIT_MASK_MDIO_PHY_ADDR_8197F) << BIT_SHIFT_MDIO_PHY_ADDR_8197F) +#define BITS_MDIO_PHY_ADDR_8197F \ + (BIT_MASK_MDIO_PHY_ADDR_8197F << BIT_SHIFT_MDIO_PHY_ADDR_8197F) #define BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) ((x) & (~BITS_MDIO_PHY_ADDR_8197F)) -#define BIT_GET_MDIO_PHY_ADDR_8197F(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8197F) & BIT_MASK_MDIO_PHY_ADDR_8197F) -#define BIT_SET_MDIO_PHY_ADDR_8197F(x, v) (BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) | BIT_MDIO_PHY_ADDR_8197F(v)) - +#define BIT_GET_MDIO_PHY_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8197F) & BIT_MASK_MDIO_PHY_ADDR_8197F) +#define BIT_SET_MDIO_PHY_ADDR_8197F(x, v) \ + (BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) | BIT_MDIO_PHY_ADDR_8197F(v)) #define BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F 10 #define BIT_MASK_WATCH_DOG_RECORD_V1_8197F 0x3fff -#define BIT_WATCH_DOG_RECORD_V1_8197F(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8197F) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) -#define BITS_WATCH_DOG_RECORD_V1_8197F (BIT_MASK_WATCH_DOG_RECORD_V1_8197F << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) -#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) ((x) & (~BITS_WATCH_DOG_RECORD_V1_8197F)) -#define BIT_GET_WATCH_DOG_RECORD_V1_8197F(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) & BIT_MASK_WATCH_DOG_RECORD_V1_8197F) -#define BIT_SET_WATCH_DOG_RECORD_V1_8197F(x, v) (BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) | BIT_WATCH_DOG_RECORD_V1_8197F(v)) +#define BIT_WATCH_DOG_RECORD_V1_8197F(x) \ + (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8197F) \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) +#define BITS_WATCH_DOG_RECORD_V1_8197F \ + (BIT_MASK_WATCH_DOG_RECORD_V1_8197F \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) \ + ((x) & (~BITS_WATCH_DOG_RECORD_V1_8197F)) +#define BIT_GET_WATCH_DOG_RECORD_V1_8197F(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) & \ + BIT_MASK_WATCH_DOG_RECORD_V1_8197F) +#define BIT_SET_WATCH_DOG_RECORD_V1_8197F(x, v) \ + (BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) | \ + BIT_WATCH_DOG_RECORD_V1_8197F(v)) #define BIT_R_IO_TIMEOUT_FLAG_V1_8197F BIT(9) #define BIT_EN_WATCH_DOG_V1_8197F BIT(8) @@ -5906,12 +7456,15 @@ #define BIT_SHIFT_MDIO_REG_ADDR_8197F 0 #define BIT_MASK_MDIO_REG_ADDR_8197F 0x1f -#define BIT_MDIO_REG_ADDR_8197F(x) (((x) & BIT_MASK_MDIO_REG_ADDR_8197F) << BIT_SHIFT_MDIO_REG_ADDR_8197F) -#define BITS_MDIO_REG_ADDR_8197F (BIT_MASK_MDIO_REG_ADDR_8197F << BIT_SHIFT_MDIO_REG_ADDR_8197F) +#define BIT_MDIO_REG_ADDR_8197F(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR_8197F) << BIT_SHIFT_MDIO_REG_ADDR_8197F) +#define BITS_MDIO_REG_ADDR_8197F \ + (BIT_MASK_MDIO_REG_ADDR_8197F << BIT_SHIFT_MDIO_REG_ADDR_8197F) #define BIT_CLEAR_MDIO_REG_ADDR_8197F(x) ((x) & (~BITS_MDIO_REG_ADDR_8197F)) -#define BIT_GET_MDIO_REG_ADDR_8197F(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_8197F) & BIT_MASK_MDIO_REG_ADDR_8197F) -#define BIT_SET_MDIO_REG_ADDR_8197F(x, v) (BIT_CLEAR_MDIO_REG_ADDR_8197F(x) | BIT_MDIO_REG_ADDR_8197F(v)) - +#define BIT_GET_MDIO_REG_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR_8197F) & BIT_MASK_MDIO_REG_ADDR_8197F) +#define BIT_SET_MDIO_REG_ADDR_8197F(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR_8197F(x) | BIT_MDIO_REG_ADDR_8197F(v)) /* 2 REG_HCI_MIX_CFG_8197F */ #define BIT_RXRST_BACKDOOR_8197F BIT(31) @@ -5927,30 +7480,48 @@ #define BIT_SHIFT_TXDMA_ERR_FLAG_8197F 16 #define BIT_MASK_TXDMA_ERR_FLAG_8197F 0xf -#define BIT_TXDMA_ERR_FLAG_8197F(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8197F) << BIT_SHIFT_TXDMA_ERR_FLAG_8197F) -#define BITS_TXDMA_ERR_FLAG_8197F (BIT_MASK_TXDMA_ERR_FLAG_8197F << BIT_SHIFT_TXDMA_ERR_FLAG_8197F) +#define BIT_TXDMA_ERR_FLAG_8197F(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG_8197F) \ + << BIT_SHIFT_TXDMA_ERR_FLAG_8197F) +#define BITS_TXDMA_ERR_FLAG_8197F \ + (BIT_MASK_TXDMA_ERR_FLAG_8197F << BIT_SHIFT_TXDMA_ERR_FLAG_8197F) #define BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8197F)) -#define BIT_GET_TXDMA_ERR_FLAG_8197F(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8197F) & BIT_MASK_TXDMA_ERR_FLAG_8197F) -#define BIT_SET_TXDMA_ERR_FLAG_8197F(x, v) (BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) | BIT_TXDMA_ERR_FLAG_8197F(v)) - +#define BIT_GET_TXDMA_ERR_FLAG_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8197F) & \ + BIT_MASK_TXDMA_ERR_FLAG_8197F) +#define BIT_SET_TXDMA_ERR_FLAG_8197F(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) | BIT_TXDMA_ERR_FLAG_8197F(v)) #define BIT_SHIFT_EARLY_MODE_SEL_8197F 12 #define BIT_MASK_EARLY_MODE_SEL_8197F 0xf -#define BIT_EARLY_MODE_SEL_8197F(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8197F) << BIT_SHIFT_EARLY_MODE_SEL_8197F) -#define BITS_EARLY_MODE_SEL_8197F (BIT_MASK_EARLY_MODE_SEL_8197F << BIT_SHIFT_EARLY_MODE_SEL_8197F) +#define BIT_EARLY_MODE_SEL_8197F(x) \ + (((x) & BIT_MASK_EARLY_MODE_SEL_8197F) \ + << BIT_SHIFT_EARLY_MODE_SEL_8197F) +#define BITS_EARLY_MODE_SEL_8197F \ + (BIT_MASK_EARLY_MODE_SEL_8197F << BIT_SHIFT_EARLY_MODE_SEL_8197F) #define BIT_CLEAR_EARLY_MODE_SEL_8197F(x) ((x) & (~BITS_EARLY_MODE_SEL_8197F)) -#define BIT_GET_EARLY_MODE_SEL_8197F(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8197F) & BIT_MASK_EARLY_MODE_SEL_8197F) -#define BIT_SET_EARLY_MODE_SEL_8197F(x, v) (BIT_CLEAR_EARLY_MODE_SEL_8197F(x) | BIT_EARLY_MODE_SEL_8197F(v)) +#define BIT_GET_EARLY_MODE_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8197F) & \ + BIT_MASK_EARLY_MODE_SEL_8197F) +#define BIT_SET_EARLY_MODE_SEL_8197F(x, v) \ + (BIT_CLEAR_EARLY_MODE_SEL_8197F(x) | BIT_EARLY_MODE_SEL_8197F(v)) #define BIT_EPHY_RX50_EN_8197F BIT(11) #define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F 8 #define BIT_MASK_MSI_TIMEOUT_ID_V1_8197F 0x7 -#define BIT_MSI_TIMEOUT_ID_V1_8197F(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8197F) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) -#define BITS_MSI_TIMEOUT_ID_V1_8197F (BIT_MASK_MSI_TIMEOUT_ID_V1_8197F << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) -#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8197F)) -#define BIT_GET_MSI_TIMEOUT_ID_V1_8197F(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) & BIT_MASK_MSI_TIMEOUT_ID_V1_8197F) -#define BIT_SET_MSI_TIMEOUT_ID_V1_8197F(x, v) (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) | BIT_MSI_TIMEOUT_ID_V1_8197F(v)) +#define BIT_MSI_TIMEOUT_ID_V1_8197F(x) \ + (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8197F) \ + << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) +#define BITS_MSI_TIMEOUT_ID_V1_8197F \ + (BIT_MASK_MSI_TIMEOUT_ID_V1_8197F << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) \ + ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8197F)) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) & \ + BIT_MASK_MSI_TIMEOUT_ID_V1_8197F) +#define BIT_SET_MSI_TIMEOUT_ID_V1_8197F(x, v) \ + (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) | BIT_MSI_TIMEOUT_ID_V1_8197F(v)) #define BIT_RADDR_RD_8197F BIT(7) #define BIT_EN_MUL_TAG_8197F BIT(6) @@ -5963,51 +7534,77 @@ #define BIT_SHIFT_STC_INT_FLAG_8197F 16 #define BIT_MASK_STC_INT_FLAG_8197F 0xff -#define BIT_STC_INT_FLAG_8197F(x) (((x) & BIT_MASK_STC_INT_FLAG_8197F) << BIT_SHIFT_STC_INT_FLAG_8197F) -#define BITS_STC_INT_FLAG_8197F (BIT_MASK_STC_INT_FLAG_8197F << BIT_SHIFT_STC_INT_FLAG_8197F) +#define BIT_STC_INT_FLAG_8197F(x) \ + (((x) & BIT_MASK_STC_INT_FLAG_8197F) << BIT_SHIFT_STC_INT_FLAG_8197F) +#define BITS_STC_INT_FLAG_8197F \ + (BIT_MASK_STC_INT_FLAG_8197F << BIT_SHIFT_STC_INT_FLAG_8197F) #define BIT_CLEAR_STC_INT_FLAG_8197F(x) ((x) & (~BITS_STC_INT_FLAG_8197F)) -#define BIT_GET_STC_INT_FLAG_8197F(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8197F) & BIT_MASK_STC_INT_FLAG_8197F) -#define BIT_SET_STC_INT_FLAG_8197F(x, v) (BIT_CLEAR_STC_INT_FLAG_8197F(x) | BIT_STC_INT_FLAG_8197F(v)) - +#define BIT_GET_STC_INT_FLAG_8197F(x) \ + (((x) >> BIT_SHIFT_STC_INT_FLAG_8197F) & BIT_MASK_STC_INT_FLAG_8197F) +#define BIT_SET_STC_INT_FLAG_8197F(x, v) \ + (BIT_CLEAR_STC_INT_FLAG_8197F(x) | BIT_STC_INT_FLAG_8197F(v)) #define BIT_SHIFT_STC_INT_IDX_8197F 8 #define BIT_MASK_STC_INT_IDX_8197F 0x7 -#define BIT_STC_INT_IDX_8197F(x) (((x) & BIT_MASK_STC_INT_IDX_8197F) << BIT_SHIFT_STC_INT_IDX_8197F) -#define BITS_STC_INT_IDX_8197F (BIT_MASK_STC_INT_IDX_8197F << BIT_SHIFT_STC_INT_IDX_8197F) +#define BIT_STC_INT_IDX_8197F(x) \ + (((x) & BIT_MASK_STC_INT_IDX_8197F) << BIT_SHIFT_STC_INT_IDX_8197F) +#define BITS_STC_INT_IDX_8197F \ + (BIT_MASK_STC_INT_IDX_8197F << BIT_SHIFT_STC_INT_IDX_8197F) #define BIT_CLEAR_STC_INT_IDX_8197F(x) ((x) & (~BITS_STC_INT_IDX_8197F)) -#define BIT_GET_STC_INT_IDX_8197F(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8197F) & BIT_MASK_STC_INT_IDX_8197F) -#define BIT_SET_STC_INT_IDX_8197F(x, v) (BIT_CLEAR_STC_INT_IDX_8197F(x) | BIT_STC_INT_IDX_8197F(v)) - +#define BIT_GET_STC_INT_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_STC_INT_IDX_8197F) & BIT_MASK_STC_INT_IDX_8197F) +#define BIT_SET_STC_INT_IDX_8197F(x, v) \ + (BIT_CLEAR_STC_INT_IDX_8197F(x) | BIT_STC_INT_IDX_8197F(v)) #define BIT_SHIFT_STC_INT_REALTIME_CS_8197F 0 #define BIT_MASK_STC_INT_REALTIME_CS_8197F 0x3f -#define BIT_STC_INT_REALTIME_CS_8197F(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8197F) << BIT_SHIFT_STC_INT_REALTIME_CS_8197F) -#define BITS_STC_INT_REALTIME_CS_8197F (BIT_MASK_STC_INT_REALTIME_CS_8197F << BIT_SHIFT_STC_INT_REALTIME_CS_8197F) -#define BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) ((x) & (~BITS_STC_INT_REALTIME_CS_8197F)) -#define BIT_GET_STC_INT_REALTIME_CS_8197F(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8197F) & BIT_MASK_STC_INT_REALTIME_CS_8197F) -#define BIT_SET_STC_INT_REALTIME_CS_8197F(x, v) (BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) | BIT_STC_INT_REALTIME_CS_8197F(v)) - +#define BIT_STC_INT_REALTIME_CS_8197F(x) \ + (((x) & BIT_MASK_STC_INT_REALTIME_CS_8197F) \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8197F) +#define BITS_STC_INT_REALTIME_CS_8197F \ + (BIT_MASK_STC_INT_REALTIME_CS_8197F \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8197F) +#define BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) \ + ((x) & (~BITS_STC_INT_REALTIME_CS_8197F)) +#define BIT_GET_STC_INT_REALTIME_CS_8197F(x) \ + (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8197F) & \ + BIT_MASK_STC_INT_REALTIME_CS_8197F) +#define BIT_SET_STC_INT_REALTIME_CS_8197F(x, v) \ + (BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) | \ + BIT_STC_INT_REALTIME_CS_8197F(v)) /* 2 REG_ST_INT_CFG_8197F(HCI STATE CHANGE INTERRUPT CONFIGURATION) */ #define BIT_STC_INT_GRP_EN_8197F BIT(31) #define BIT_SHIFT_STC_INT_EXPECT_LS_8197F 8 #define BIT_MASK_STC_INT_EXPECT_LS_8197F 0x3f -#define BIT_STC_INT_EXPECT_LS_8197F(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8197F) << BIT_SHIFT_STC_INT_EXPECT_LS_8197F) -#define BITS_STC_INT_EXPECT_LS_8197F (BIT_MASK_STC_INT_EXPECT_LS_8197F << BIT_SHIFT_STC_INT_EXPECT_LS_8197F) -#define BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) ((x) & (~BITS_STC_INT_EXPECT_LS_8197F)) -#define BIT_GET_STC_INT_EXPECT_LS_8197F(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8197F) & BIT_MASK_STC_INT_EXPECT_LS_8197F) -#define BIT_SET_STC_INT_EXPECT_LS_8197F(x, v) (BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) | BIT_STC_INT_EXPECT_LS_8197F(v)) - +#define BIT_STC_INT_EXPECT_LS_8197F(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_LS_8197F) \ + << BIT_SHIFT_STC_INT_EXPECT_LS_8197F) +#define BITS_STC_INT_EXPECT_LS_8197F \ + (BIT_MASK_STC_INT_EXPECT_LS_8197F << BIT_SHIFT_STC_INT_EXPECT_LS_8197F) +#define BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) \ + ((x) & (~BITS_STC_INT_EXPECT_LS_8197F)) +#define BIT_GET_STC_INT_EXPECT_LS_8197F(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8197F) & \ + BIT_MASK_STC_INT_EXPECT_LS_8197F) +#define BIT_SET_STC_INT_EXPECT_LS_8197F(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) | BIT_STC_INT_EXPECT_LS_8197F(v)) #define BIT_SHIFT_STC_INT_EXPECT_CS_8197F 0 #define BIT_MASK_STC_INT_EXPECT_CS_8197F 0x3f -#define BIT_STC_INT_EXPECT_CS_8197F(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8197F) << BIT_SHIFT_STC_INT_EXPECT_CS_8197F) -#define BITS_STC_INT_EXPECT_CS_8197F (BIT_MASK_STC_INT_EXPECT_CS_8197F << BIT_SHIFT_STC_INT_EXPECT_CS_8197F) -#define BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) ((x) & (~BITS_STC_INT_EXPECT_CS_8197F)) -#define BIT_GET_STC_INT_EXPECT_CS_8197F(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8197F) & BIT_MASK_STC_INT_EXPECT_CS_8197F) -#define BIT_SET_STC_INT_EXPECT_CS_8197F(x, v) (BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) | BIT_STC_INT_EXPECT_CS_8197F(v)) - +#define BIT_STC_INT_EXPECT_CS_8197F(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_CS_8197F) \ + << BIT_SHIFT_STC_INT_EXPECT_CS_8197F) +#define BITS_STC_INT_EXPECT_CS_8197F \ + (BIT_MASK_STC_INT_EXPECT_CS_8197F << BIT_SHIFT_STC_INT_EXPECT_CS_8197F) +#define BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) \ + ((x) & (~BITS_STC_INT_EXPECT_CS_8197F)) +#define BIT_GET_STC_INT_EXPECT_CS_8197F(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8197F) & \ + BIT_MASK_STC_INT_EXPECT_CS_8197F) +#define BIT_SET_STC_INT_EXPECT_CS_8197F(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) | BIT_STC_INT_EXPECT_CS_8197F(v)) /* 2 REG_CMU_DLY_CTRL_8197F(HCI PHY CLOCK MGT UNIT DELAY CONTROL ) */ #define BIT_CMU_DLY_EN_8197F BIT(31) @@ -6015,102 +7612,147 @@ #define BIT_SHIFT_CMU_DLY_PRE_DIV_8197F 0 #define BIT_MASK_CMU_DLY_PRE_DIV_8197F 0xff -#define BIT_CMU_DLY_PRE_DIV_8197F(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8197F) << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) -#define BITS_CMU_DLY_PRE_DIV_8197F (BIT_MASK_CMU_DLY_PRE_DIV_8197F << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) +#define BIT_CMU_DLY_PRE_DIV_8197F(x) \ + (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8197F) \ + << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) +#define BITS_CMU_DLY_PRE_DIV_8197F \ + (BIT_MASK_CMU_DLY_PRE_DIV_8197F << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) #define BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8197F)) -#define BIT_GET_CMU_DLY_PRE_DIV_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) & BIT_MASK_CMU_DLY_PRE_DIV_8197F) -#define BIT_SET_CMU_DLY_PRE_DIV_8197F(x, v) (BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) | BIT_CMU_DLY_PRE_DIV_8197F(v)) - +#define BIT_GET_CMU_DLY_PRE_DIV_8197F(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) & \ + BIT_MASK_CMU_DLY_PRE_DIV_8197F) +#define BIT_SET_CMU_DLY_PRE_DIV_8197F(x, v) \ + (BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) | BIT_CMU_DLY_PRE_DIV_8197F(v)) /* 2 REG_CMU_DLY_CFG_8197F(HCI PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ #define BIT_SHIFT_CMU_DLY_LTR_A2I_8197F 24 #define BIT_MASK_CMU_DLY_LTR_A2I_8197F 0xff -#define BIT_CMU_DLY_LTR_A2I_8197F(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8197F) << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) -#define BITS_CMU_DLY_LTR_A2I_8197F (BIT_MASK_CMU_DLY_LTR_A2I_8197F << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) +#define BIT_CMU_DLY_LTR_A2I_8197F(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8197F) \ + << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) +#define BITS_CMU_DLY_LTR_A2I_8197F \ + (BIT_MASK_CMU_DLY_LTR_A2I_8197F << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) #define BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8197F)) -#define BIT_GET_CMU_DLY_LTR_A2I_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) & BIT_MASK_CMU_DLY_LTR_A2I_8197F) -#define BIT_SET_CMU_DLY_LTR_A2I_8197F(x, v) (BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) | BIT_CMU_DLY_LTR_A2I_8197F(v)) - +#define BIT_GET_CMU_DLY_LTR_A2I_8197F(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) & \ + BIT_MASK_CMU_DLY_LTR_A2I_8197F) +#define BIT_SET_CMU_DLY_LTR_A2I_8197F(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) | BIT_CMU_DLY_LTR_A2I_8197F(v)) #define BIT_SHIFT_CMU_DLY_LTR_I2A_8197F 16 #define BIT_MASK_CMU_DLY_LTR_I2A_8197F 0xff -#define BIT_CMU_DLY_LTR_I2A_8197F(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8197F) << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) -#define BITS_CMU_DLY_LTR_I2A_8197F (BIT_MASK_CMU_DLY_LTR_I2A_8197F << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) +#define BIT_CMU_DLY_LTR_I2A_8197F(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8197F) \ + << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) +#define BITS_CMU_DLY_LTR_I2A_8197F \ + (BIT_MASK_CMU_DLY_LTR_I2A_8197F << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) #define BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8197F)) -#define BIT_GET_CMU_DLY_LTR_I2A_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) & BIT_MASK_CMU_DLY_LTR_I2A_8197F) -#define BIT_SET_CMU_DLY_LTR_I2A_8197F(x, v) (BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) | BIT_CMU_DLY_LTR_I2A_8197F(v)) - +#define BIT_GET_CMU_DLY_LTR_I2A_8197F(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) & \ + BIT_MASK_CMU_DLY_LTR_I2A_8197F) +#define BIT_SET_CMU_DLY_LTR_I2A_8197F(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) | BIT_CMU_DLY_LTR_I2A_8197F(v)) #define BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F 8 #define BIT_MASK_CMU_DLY_LTR_IDLE_8197F 0xff -#define BIT_CMU_DLY_LTR_IDLE_8197F(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8197F) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) -#define BITS_CMU_DLY_LTR_IDLE_8197F (BIT_MASK_CMU_DLY_LTR_IDLE_8197F << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) -#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_IDLE_8197F)) -#define BIT_GET_CMU_DLY_LTR_IDLE_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) & BIT_MASK_CMU_DLY_LTR_IDLE_8197F) -#define BIT_SET_CMU_DLY_LTR_IDLE_8197F(x, v) (BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) | BIT_CMU_DLY_LTR_IDLE_8197F(v)) - +#define BIT_CMU_DLY_LTR_IDLE_8197F(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8197F) \ + << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) +#define BITS_CMU_DLY_LTR_IDLE_8197F \ + (BIT_MASK_CMU_DLY_LTR_IDLE_8197F << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) +#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) \ + ((x) & (~BITS_CMU_DLY_LTR_IDLE_8197F)) +#define BIT_GET_CMU_DLY_LTR_IDLE_8197F(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) & \ + BIT_MASK_CMU_DLY_LTR_IDLE_8197F) +#define BIT_SET_CMU_DLY_LTR_IDLE_8197F(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) | BIT_CMU_DLY_LTR_IDLE_8197F(v)) #define BIT_SHIFT_CMU_DLY_LTR_ACT_8197F 0 #define BIT_MASK_CMU_DLY_LTR_ACT_8197F 0xff -#define BIT_CMU_DLY_LTR_ACT_8197F(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8197F) << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) -#define BITS_CMU_DLY_LTR_ACT_8197F (BIT_MASK_CMU_DLY_LTR_ACT_8197F << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) +#define BIT_CMU_DLY_LTR_ACT_8197F(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8197F) \ + << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) +#define BITS_CMU_DLY_LTR_ACT_8197F \ + (BIT_MASK_CMU_DLY_LTR_ACT_8197F << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) #define BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8197F)) -#define BIT_GET_CMU_DLY_LTR_ACT_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) & BIT_MASK_CMU_DLY_LTR_ACT_8197F) -#define BIT_SET_CMU_DLY_LTR_ACT_8197F(x, v) (BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) | BIT_CMU_DLY_LTR_ACT_8197F(v)) - +#define BIT_GET_CMU_DLY_LTR_ACT_8197F(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) & \ + BIT_MASK_CMU_DLY_LTR_ACT_8197F) +#define BIT_SET_CMU_DLY_LTR_ACT_8197F(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) | BIT_CMU_DLY_LTR_ACT_8197F(v)) /* 2 REG_H2CQ_TXBD_DESA_8197F */ #define BIT_SHIFT_H2CQ_TXBD_DESA_8197F 0 #define BIT_MASK_H2CQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_H2CQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8197F) << BIT_SHIFT_H2CQ_TXBD_DESA_8197F) -#define BITS_H2CQ_TXBD_DESA_8197F (BIT_MASK_H2CQ_TXBD_DESA_8197F << BIT_SHIFT_H2CQ_TXBD_DESA_8197F) +#define BIT_H2CQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_8197F) \ + << BIT_SHIFT_H2CQ_TXBD_DESA_8197F) +#define BITS_H2CQ_TXBD_DESA_8197F \ + (BIT_MASK_H2CQ_TXBD_DESA_8197F << BIT_SHIFT_H2CQ_TXBD_DESA_8197F) #define BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8197F)) -#define BIT_GET_H2CQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8197F) & BIT_MASK_H2CQ_TXBD_DESA_8197F) -#define BIT_SET_H2CQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) | BIT_H2CQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_H2CQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8197F) & \ + BIT_MASK_H2CQ_TXBD_DESA_8197F) +#define BIT_SET_H2CQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) | BIT_H2CQ_TXBD_DESA_8197F(v)) /* 2 REG_H2CQ_TXBD_NUM_8197F */ #define BIT_HCI_H2CQ_FLAG_8197F BIT(14) #define BIT_SHIFT_H2CQ_DESC_MODE_8197F 12 #define BIT_MASK_H2CQ_DESC_MODE_8197F 0x3 -#define BIT_H2CQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8197F) << BIT_SHIFT_H2CQ_DESC_MODE_8197F) -#define BITS_H2CQ_DESC_MODE_8197F (BIT_MASK_H2CQ_DESC_MODE_8197F << BIT_SHIFT_H2CQ_DESC_MODE_8197F) +#define BIT_H2CQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_H2CQ_DESC_MODE_8197F) \ + << BIT_SHIFT_H2CQ_DESC_MODE_8197F) +#define BITS_H2CQ_DESC_MODE_8197F \ + (BIT_MASK_H2CQ_DESC_MODE_8197F << BIT_SHIFT_H2CQ_DESC_MODE_8197F) #define BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) ((x) & (~BITS_H2CQ_DESC_MODE_8197F)) -#define BIT_GET_H2CQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8197F) & BIT_MASK_H2CQ_DESC_MODE_8197F) -#define BIT_SET_H2CQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) | BIT_H2CQ_DESC_MODE_8197F(v)) - +#define BIT_GET_H2CQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8197F) & \ + BIT_MASK_H2CQ_DESC_MODE_8197F) +#define BIT_SET_H2CQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) | BIT_H2CQ_DESC_MODE_8197F(v)) #define BIT_SHIFT_H2CQ_DESC_NUM_8197F 0 #define BIT_MASK_H2CQ_DESC_NUM_8197F 0xfff -#define BIT_H2CQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8197F) << BIT_SHIFT_H2CQ_DESC_NUM_8197F) -#define BITS_H2CQ_DESC_NUM_8197F (BIT_MASK_H2CQ_DESC_NUM_8197F << BIT_SHIFT_H2CQ_DESC_NUM_8197F) +#define BIT_H2CQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_H2CQ_DESC_NUM_8197F) << BIT_SHIFT_H2CQ_DESC_NUM_8197F) +#define BITS_H2CQ_DESC_NUM_8197F \ + (BIT_MASK_H2CQ_DESC_NUM_8197F << BIT_SHIFT_H2CQ_DESC_NUM_8197F) #define BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) ((x) & (~BITS_H2CQ_DESC_NUM_8197F)) -#define BIT_GET_H2CQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8197F) & BIT_MASK_H2CQ_DESC_NUM_8197F) -#define BIT_SET_H2CQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) | BIT_H2CQ_DESC_NUM_8197F(v)) - +#define BIT_GET_H2CQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8197F) & BIT_MASK_H2CQ_DESC_NUM_8197F) +#define BIT_SET_H2CQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) | BIT_H2CQ_DESC_NUM_8197F(v)) /* 2 REG_H2CQ_TXBD_IDX_8197F */ #define BIT_SHIFT_H2CQ_HW_IDX_8197F 16 #define BIT_MASK_H2CQ_HW_IDX_8197F 0xfff -#define BIT_H2CQ_HW_IDX_8197F(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8197F) << BIT_SHIFT_H2CQ_HW_IDX_8197F) -#define BITS_H2CQ_HW_IDX_8197F (BIT_MASK_H2CQ_HW_IDX_8197F << BIT_SHIFT_H2CQ_HW_IDX_8197F) +#define BIT_H2CQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_H2CQ_HW_IDX_8197F) << BIT_SHIFT_H2CQ_HW_IDX_8197F) +#define BITS_H2CQ_HW_IDX_8197F \ + (BIT_MASK_H2CQ_HW_IDX_8197F << BIT_SHIFT_H2CQ_HW_IDX_8197F) #define BIT_CLEAR_H2CQ_HW_IDX_8197F(x) ((x) & (~BITS_H2CQ_HW_IDX_8197F)) -#define BIT_GET_H2CQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8197F) & BIT_MASK_H2CQ_HW_IDX_8197F) -#define BIT_SET_H2CQ_HW_IDX_8197F(x, v) (BIT_CLEAR_H2CQ_HW_IDX_8197F(x) | BIT_H2CQ_HW_IDX_8197F(v)) - +#define BIT_GET_H2CQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8197F) & BIT_MASK_H2CQ_HW_IDX_8197F) +#define BIT_SET_H2CQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_H2CQ_HW_IDX_8197F(x) | BIT_H2CQ_HW_IDX_8197F(v)) #define BIT_SHIFT_H2CQ_HOST_IDX_8197F 0 #define BIT_MASK_H2CQ_HOST_IDX_8197F 0xfff -#define BIT_H2CQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8197F) << BIT_SHIFT_H2CQ_HOST_IDX_8197F) -#define BITS_H2CQ_HOST_IDX_8197F (BIT_MASK_H2CQ_HOST_IDX_8197F << BIT_SHIFT_H2CQ_HOST_IDX_8197F) +#define BIT_H2CQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_H2CQ_HOST_IDX_8197F) << BIT_SHIFT_H2CQ_HOST_IDX_8197F) +#define BITS_H2CQ_HOST_IDX_8197F \ + (BIT_MASK_H2CQ_HOST_IDX_8197F << BIT_SHIFT_H2CQ_HOST_IDX_8197F) #define BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) ((x) & (~BITS_H2CQ_HOST_IDX_8197F)) -#define BIT_GET_H2CQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8197F) & BIT_MASK_H2CQ_HOST_IDX_8197F) -#define BIT_SET_H2CQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) | BIT_H2CQ_HOST_IDX_8197F(v)) - +#define BIT_GET_H2CQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8197F) & BIT_MASK_H2CQ_HOST_IDX_8197F) +#define BIT_SET_H2CQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) | BIT_H2CQ_HOST_IDX_8197F(v)) /* 2 REG_H2CQ_CSR_8197F[31:0] (H2CQ CONTROL AND STATUS) */ #define BIT_H2CQ_FULL_8197F BIT(31) @@ -6142,275 +7784,426 @@ #define BIT_SHIFT_AXI_RECOVERY_TIME_8197F 24 #define BIT_MASK_AXI_RECOVERY_TIME_8197F 0xff -#define BIT_AXI_RECOVERY_TIME_8197F(x) (((x) & BIT_MASK_AXI_RECOVERY_TIME_8197F) << BIT_SHIFT_AXI_RECOVERY_TIME_8197F) -#define BITS_AXI_RECOVERY_TIME_8197F (BIT_MASK_AXI_RECOVERY_TIME_8197F << BIT_SHIFT_AXI_RECOVERY_TIME_8197F) -#define BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) ((x) & (~BITS_AXI_RECOVERY_TIME_8197F)) -#define BIT_GET_AXI_RECOVERY_TIME_8197F(x) (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME_8197F) & BIT_MASK_AXI_RECOVERY_TIME_8197F) -#define BIT_SET_AXI_RECOVERY_TIME_8197F(x, v) (BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) | BIT_AXI_RECOVERY_TIME_8197F(v)) - +#define BIT_AXI_RECOVERY_TIME_8197F(x) \ + (((x) & BIT_MASK_AXI_RECOVERY_TIME_8197F) \ + << BIT_SHIFT_AXI_RECOVERY_TIME_8197F) +#define BITS_AXI_RECOVERY_TIME_8197F \ + (BIT_MASK_AXI_RECOVERY_TIME_8197F << BIT_SHIFT_AXI_RECOVERY_TIME_8197F) +#define BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) \ + ((x) & (~BITS_AXI_RECOVERY_TIME_8197F)) +#define BIT_GET_AXI_RECOVERY_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME_8197F) & \ + BIT_MASK_AXI_RECOVERY_TIME_8197F) +#define BIT_SET_AXI_RECOVERY_TIME_8197F(x, v) \ + (BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) | BIT_AXI_RECOVERY_TIME_8197F(v)) #define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F 12 #define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F 0xfff -#define BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(x) (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F) << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) -#define BITS_AXI_RXDMA_TIMEOUT_VAL_8197F (BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) -#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) ((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL_8197F)) -#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL_8197F(x) (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F) -#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL_8197F(x, v) (BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) | BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(v)) - +#define BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(x) \ + (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F) \ + << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) +#define BITS_AXI_RXDMA_TIMEOUT_VAL_8197F \ + (BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F \ + << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) +#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) \ + ((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL_8197F)) +#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL_8197F(x) \ + (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) & \ + BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F) +#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL_8197F(x, v) \ + (BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) | \ + BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(v)) #define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F 0 #define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F 0xfff -#define BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(x) (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F) << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) -#define BITS_AXI_TXDMA_TIMEOUT_VAL_8197F (BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) -#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) ((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL_8197F)) -#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL_8197F(x) (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F) -#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL_8197F(x, v) (BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) | BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(v)) - +#define BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(x) \ + (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F) \ + << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) +#define BITS_AXI_TXDMA_TIMEOUT_VAL_8197F \ + (BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F \ + << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) +#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) \ + ((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL_8197F)) +#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL_8197F(x) \ + (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) & \ + BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F) +#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL_8197F(x, v) \ + (BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) | \ + BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(v)) /* 2 REG_Q0_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q0_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q0_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q0_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) -#define BITS_QUEUEMACID_Q0_V1_8197F (BIT_MASK_QUEUEMACID_Q0_V1_8197F << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q0_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q0_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) & BIT_MASK_QUEUEMACID_Q0_V1_8197F) -#define BIT_SET_QUEUEMACID_Q0_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) | BIT_QUEUEMACID_Q0_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q0_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) +#define BITS_QUEUEMACID_Q0_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q0_V1_8197F << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q0_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q0_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q0_V1_8197F) +#define BIT_SET_QUEUEMACID_Q0_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) | BIT_QUEUEMACID_Q0_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q0_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q0_V1_8197F 0x3 -#define BIT_QUEUEAC_Q0_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8197F) << BIT_SHIFT_QUEUEAC_Q0_V1_8197F) -#define BITS_QUEUEAC_Q0_V1_8197F (BIT_MASK_QUEUEAC_Q0_V1_8197F << BIT_SHIFT_QUEUEAC_Q0_V1_8197F) +#define BIT_QUEUEAC_Q0_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q0_V1_8197F) << BIT_SHIFT_QUEUEAC_Q0_V1_8197F) +#define BITS_QUEUEAC_Q0_V1_8197F \ + (BIT_MASK_QUEUEAC_Q0_V1_8197F << BIT_SHIFT_QUEUEAC_Q0_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8197F)) -#define BIT_GET_QUEUEAC_Q0_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8197F) & BIT_MASK_QUEUEAC_Q0_V1_8197F) -#define BIT_SET_QUEUEAC_Q0_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) | BIT_QUEUEAC_Q0_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q0_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8197F) & BIT_MASK_QUEUEAC_Q0_V1_8197F) +#define BIT_SET_QUEUEAC_Q0_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) | BIT_QUEUEAC_Q0_V1_8197F(v)) #define BIT_TIDEMPTY_Q0_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q0_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q0_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q0_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) -#define BITS_TAIL_PKT_Q0_V2_8197F (BIT_MASK_TAIL_PKT_Q0_V2_8197F << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) +#define BIT_TAIL_PKT_Q0_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) +#define BITS_TAIL_PKT_Q0_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q0_V2_8197F << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q0_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) & BIT_MASK_TAIL_PKT_Q0_V2_8197F) -#define BIT_SET_TAIL_PKT_Q0_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) | BIT_TAIL_PKT_Q0_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q0_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q0_V2_8197F) +#define BIT_SET_TAIL_PKT_Q0_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) | BIT_TAIL_PKT_Q0_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q0_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q0_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q0_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) -#define BITS_HEAD_PKT_Q0_V1_8197F (BIT_MASK_HEAD_PKT_Q0_V1_8197F << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) +#define BIT_HEAD_PKT_Q0_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) +#define BITS_HEAD_PKT_Q0_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q0_V1_8197F << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q0_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) & BIT_MASK_HEAD_PKT_Q0_V1_8197F) -#define BIT_SET_HEAD_PKT_Q0_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) | BIT_HEAD_PKT_Q0_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q0_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q0_V1_8197F) +#define BIT_SET_HEAD_PKT_Q0_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) | BIT_HEAD_PKT_Q0_V1_8197F(v)) /* 2 REG_Q1_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q1_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q1_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q1_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) -#define BITS_QUEUEMACID_Q1_V1_8197F (BIT_MASK_QUEUEMACID_Q1_V1_8197F << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q1_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q1_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) & BIT_MASK_QUEUEMACID_Q1_V1_8197F) -#define BIT_SET_QUEUEMACID_Q1_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) | BIT_QUEUEMACID_Q1_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q1_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) +#define BITS_QUEUEMACID_Q1_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q1_V1_8197F << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q1_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q1_V1_8197F) +#define BIT_SET_QUEUEMACID_Q1_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) | BIT_QUEUEMACID_Q1_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q1_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q1_V1_8197F 0x3 -#define BIT_QUEUEAC_Q1_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8197F) << BIT_SHIFT_QUEUEAC_Q1_V1_8197F) -#define BITS_QUEUEAC_Q1_V1_8197F (BIT_MASK_QUEUEAC_Q1_V1_8197F << BIT_SHIFT_QUEUEAC_Q1_V1_8197F) +#define BIT_QUEUEAC_Q1_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q1_V1_8197F) << BIT_SHIFT_QUEUEAC_Q1_V1_8197F) +#define BITS_QUEUEAC_Q1_V1_8197F \ + (BIT_MASK_QUEUEAC_Q1_V1_8197F << BIT_SHIFT_QUEUEAC_Q1_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8197F)) -#define BIT_GET_QUEUEAC_Q1_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8197F) & BIT_MASK_QUEUEAC_Q1_V1_8197F) -#define BIT_SET_QUEUEAC_Q1_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) | BIT_QUEUEAC_Q1_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8197F) & BIT_MASK_QUEUEAC_Q1_V1_8197F) +#define BIT_SET_QUEUEAC_Q1_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) | BIT_QUEUEAC_Q1_V1_8197F(v)) #define BIT_TIDEMPTY_Q1_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q1_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q1_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q1_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) -#define BITS_TAIL_PKT_Q1_V2_8197F (BIT_MASK_TAIL_PKT_Q1_V2_8197F << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) +#define BIT_TAIL_PKT_Q1_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) +#define BITS_TAIL_PKT_Q1_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q1_V2_8197F << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q1_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) & BIT_MASK_TAIL_PKT_Q1_V2_8197F) -#define BIT_SET_TAIL_PKT_Q1_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) | BIT_TAIL_PKT_Q1_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q1_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q1_V2_8197F) +#define BIT_SET_TAIL_PKT_Q1_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) | BIT_TAIL_PKT_Q1_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q1_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q1_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q1_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) -#define BITS_HEAD_PKT_Q1_V1_8197F (BIT_MASK_HEAD_PKT_Q1_V1_8197F << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) +#define BIT_HEAD_PKT_Q1_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) +#define BITS_HEAD_PKT_Q1_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q1_V1_8197F << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q1_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) & BIT_MASK_HEAD_PKT_Q1_V1_8197F) -#define BIT_SET_HEAD_PKT_Q1_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) | BIT_HEAD_PKT_Q1_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q1_V1_8197F) +#define BIT_SET_HEAD_PKT_Q1_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) | BIT_HEAD_PKT_Q1_V1_8197F(v)) /* 2 REG_Q2_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q2_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q2_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q2_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) -#define BITS_QUEUEMACID_Q2_V1_8197F (BIT_MASK_QUEUEMACID_Q2_V1_8197F << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q2_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q2_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) & BIT_MASK_QUEUEMACID_Q2_V1_8197F) -#define BIT_SET_QUEUEMACID_Q2_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) | BIT_QUEUEMACID_Q2_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q2_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) +#define BITS_QUEUEMACID_Q2_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q2_V1_8197F << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q2_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q2_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q2_V1_8197F) +#define BIT_SET_QUEUEMACID_Q2_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) | BIT_QUEUEMACID_Q2_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q2_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q2_V1_8197F 0x3 -#define BIT_QUEUEAC_Q2_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8197F) << BIT_SHIFT_QUEUEAC_Q2_V1_8197F) -#define BITS_QUEUEAC_Q2_V1_8197F (BIT_MASK_QUEUEAC_Q2_V1_8197F << BIT_SHIFT_QUEUEAC_Q2_V1_8197F) +#define BIT_QUEUEAC_Q2_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q2_V1_8197F) << BIT_SHIFT_QUEUEAC_Q2_V1_8197F) +#define BITS_QUEUEAC_Q2_V1_8197F \ + (BIT_MASK_QUEUEAC_Q2_V1_8197F << BIT_SHIFT_QUEUEAC_Q2_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8197F)) -#define BIT_GET_QUEUEAC_Q2_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8197F) & BIT_MASK_QUEUEAC_Q2_V1_8197F) -#define BIT_SET_QUEUEAC_Q2_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) | BIT_QUEUEAC_Q2_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q2_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8197F) & BIT_MASK_QUEUEAC_Q2_V1_8197F) +#define BIT_SET_QUEUEAC_Q2_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) | BIT_QUEUEAC_Q2_V1_8197F(v)) #define BIT_TIDEMPTY_Q2_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q2_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q2_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q2_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) -#define BITS_TAIL_PKT_Q2_V2_8197F (BIT_MASK_TAIL_PKT_Q2_V2_8197F << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) +#define BIT_TAIL_PKT_Q2_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) +#define BITS_TAIL_PKT_Q2_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q2_V2_8197F << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q2_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) & BIT_MASK_TAIL_PKT_Q2_V2_8197F) -#define BIT_SET_TAIL_PKT_Q2_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) | BIT_TAIL_PKT_Q2_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q2_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q2_V2_8197F) +#define BIT_SET_TAIL_PKT_Q2_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) | BIT_TAIL_PKT_Q2_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q2_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q2_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q2_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) -#define BITS_HEAD_PKT_Q2_V1_8197F (BIT_MASK_HEAD_PKT_Q2_V1_8197F << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) +#define BIT_HEAD_PKT_Q2_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) +#define BITS_HEAD_PKT_Q2_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q2_V1_8197F << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q2_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) & BIT_MASK_HEAD_PKT_Q2_V1_8197F) -#define BIT_SET_HEAD_PKT_Q2_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) | BIT_HEAD_PKT_Q2_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q2_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q2_V1_8197F) +#define BIT_SET_HEAD_PKT_Q2_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) | BIT_HEAD_PKT_Q2_V1_8197F(v)) /* 2 REG_Q3_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q3_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q3_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q3_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) -#define BITS_QUEUEMACID_Q3_V1_8197F (BIT_MASK_QUEUEMACID_Q3_V1_8197F << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q3_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q3_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) & BIT_MASK_QUEUEMACID_Q3_V1_8197F) -#define BIT_SET_QUEUEMACID_Q3_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) | BIT_QUEUEMACID_Q3_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q3_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) +#define BITS_QUEUEMACID_Q3_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q3_V1_8197F << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q3_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q3_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q3_V1_8197F) +#define BIT_SET_QUEUEMACID_Q3_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) | BIT_QUEUEMACID_Q3_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q3_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q3_V1_8197F 0x3 -#define BIT_QUEUEAC_Q3_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8197F) << BIT_SHIFT_QUEUEAC_Q3_V1_8197F) -#define BITS_QUEUEAC_Q3_V1_8197F (BIT_MASK_QUEUEAC_Q3_V1_8197F << BIT_SHIFT_QUEUEAC_Q3_V1_8197F) +#define BIT_QUEUEAC_Q3_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q3_V1_8197F) << BIT_SHIFT_QUEUEAC_Q3_V1_8197F) +#define BITS_QUEUEAC_Q3_V1_8197F \ + (BIT_MASK_QUEUEAC_Q3_V1_8197F << BIT_SHIFT_QUEUEAC_Q3_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8197F)) -#define BIT_GET_QUEUEAC_Q3_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8197F) & BIT_MASK_QUEUEAC_Q3_V1_8197F) -#define BIT_SET_QUEUEAC_Q3_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) | BIT_QUEUEAC_Q3_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q3_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8197F) & BIT_MASK_QUEUEAC_Q3_V1_8197F) +#define BIT_SET_QUEUEAC_Q3_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) | BIT_QUEUEAC_Q3_V1_8197F(v)) #define BIT_TIDEMPTY_Q3_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q3_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q3_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q3_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) -#define BITS_TAIL_PKT_Q3_V2_8197F (BIT_MASK_TAIL_PKT_Q3_V2_8197F << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) +#define BIT_TAIL_PKT_Q3_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) +#define BITS_TAIL_PKT_Q3_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q3_V2_8197F << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q3_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) & BIT_MASK_TAIL_PKT_Q3_V2_8197F) -#define BIT_SET_TAIL_PKT_Q3_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) | BIT_TAIL_PKT_Q3_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q3_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q3_V2_8197F) +#define BIT_SET_TAIL_PKT_Q3_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) | BIT_TAIL_PKT_Q3_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q3_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q3_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q3_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) -#define BITS_HEAD_PKT_Q3_V1_8197F (BIT_MASK_HEAD_PKT_Q3_V1_8197F << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) +#define BIT_HEAD_PKT_Q3_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) +#define BITS_HEAD_PKT_Q3_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q3_V1_8197F << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q3_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) & BIT_MASK_HEAD_PKT_Q3_V1_8197F) -#define BIT_SET_HEAD_PKT_Q3_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) | BIT_HEAD_PKT_Q3_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q3_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q3_V1_8197F) +#define BIT_SET_HEAD_PKT_Q3_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) | BIT_HEAD_PKT_Q3_V1_8197F(v)) /* 2 REG_MGQ_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F 25 #define BIT_MASK_QUEUEMACID_MGQ_V1_8197F 0x7f -#define BIT_QUEUEMACID_MGQ_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8197F) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) -#define BITS_QUEUEMACID_MGQ_V1_8197F (BIT_MASK_QUEUEMACID_MGQ_V1_8197F << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_MGQ_V1_8197F)) -#define BIT_GET_QUEUEMACID_MGQ_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) & BIT_MASK_QUEUEMACID_MGQ_V1_8197F) -#define BIT_SET_QUEUEMACID_MGQ_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) | BIT_QUEUEMACID_MGQ_V1_8197F(v)) - +#define BIT_QUEUEMACID_MGQ_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) +#define BITS_QUEUEMACID_MGQ_V1_8197F \ + (BIT_MASK_QUEUEMACID_MGQ_V1_8197F << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_MGQ_V1_8197F)) +#define BIT_GET_QUEUEMACID_MGQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) & \ + BIT_MASK_QUEUEMACID_MGQ_V1_8197F) +#define BIT_SET_QUEUEMACID_MGQ_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) | BIT_QUEUEMACID_MGQ_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_MGQ_V1_8197F 23 #define BIT_MASK_QUEUEAC_MGQ_V1_8197F 0x3 -#define BIT_QUEUEAC_MGQ_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8197F) << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) -#define BITS_QUEUEAC_MGQ_V1_8197F (BIT_MASK_QUEUEAC_MGQ_V1_8197F << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) +#define BIT_QUEUEAC_MGQ_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8197F) \ + << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) +#define BITS_QUEUEAC_MGQ_V1_8197F \ + (BIT_MASK_QUEUEAC_MGQ_V1_8197F << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) #define BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8197F)) -#define BIT_GET_QUEUEAC_MGQ_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) & BIT_MASK_QUEUEAC_MGQ_V1_8197F) -#define BIT_SET_QUEUEAC_MGQ_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) | BIT_QUEUEAC_MGQ_V1_8197F(v)) +#define BIT_GET_QUEUEAC_MGQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) & \ + BIT_MASK_QUEUEAC_MGQ_V1_8197F) +#define BIT_SET_QUEUEAC_MGQ_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) | BIT_QUEUEAC_MGQ_V1_8197F(v)) #define BIT_TIDEMPTY_MGQ_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F 11 #define BIT_MASK_TAIL_PKT_MGQ_V2_8197F 0x7ff -#define BIT_TAIL_PKT_MGQ_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8197F) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) -#define BITS_TAIL_PKT_MGQ_V2_8197F (BIT_MASK_TAIL_PKT_MGQ_V2_8197F << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) +#define BIT_TAIL_PKT_MGQ_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) +#define BITS_TAIL_PKT_MGQ_V2_8197F \ + (BIT_MASK_TAIL_PKT_MGQ_V2_8197F << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) #define BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8197F)) -#define BIT_GET_TAIL_PKT_MGQ_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) & BIT_MASK_TAIL_PKT_MGQ_V2_8197F) -#define BIT_SET_TAIL_PKT_MGQ_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) | BIT_TAIL_PKT_MGQ_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_MGQ_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) & \ + BIT_MASK_TAIL_PKT_MGQ_V2_8197F) +#define BIT_SET_TAIL_PKT_MGQ_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) | BIT_TAIL_PKT_MGQ_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F 0 #define BIT_MASK_HEAD_PKT_MGQ_V1_8197F 0x7ff -#define BIT_HEAD_PKT_MGQ_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8197F) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) -#define BITS_HEAD_PKT_MGQ_V1_8197F (BIT_MASK_HEAD_PKT_MGQ_V1_8197F << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) +#define BIT_HEAD_PKT_MGQ_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) +#define BITS_HEAD_PKT_MGQ_V1_8197F \ + (BIT_MASK_HEAD_PKT_MGQ_V1_8197F << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) #define BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8197F)) -#define BIT_GET_HEAD_PKT_MGQ_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) & BIT_MASK_HEAD_PKT_MGQ_V1_8197F) -#define BIT_SET_HEAD_PKT_MGQ_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) | BIT_HEAD_PKT_MGQ_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_MGQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) & \ + BIT_MASK_HEAD_PKT_MGQ_V1_8197F) +#define BIT_SET_HEAD_PKT_MGQ_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) | BIT_HEAD_PKT_MGQ_V1_8197F(v)) /* 2 REG_HIQ_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F 25 #define BIT_MASK_QUEUEMACID_HIQ_V1_8197F 0x7f -#define BIT_QUEUEMACID_HIQ_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8197F) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) -#define BITS_QUEUEMACID_HIQ_V1_8197F (BIT_MASK_QUEUEMACID_HIQ_V1_8197F << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_HIQ_V1_8197F)) -#define BIT_GET_QUEUEMACID_HIQ_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) & BIT_MASK_QUEUEMACID_HIQ_V1_8197F) -#define BIT_SET_QUEUEMACID_HIQ_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) | BIT_QUEUEMACID_HIQ_V1_8197F(v)) - +#define BIT_QUEUEMACID_HIQ_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) +#define BITS_QUEUEMACID_HIQ_V1_8197F \ + (BIT_MASK_QUEUEMACID_HIQ_V1_8197F << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_HIQ_V1_8197F)) +#define BIT_GET_QUEUEMACID_HIQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) & \ + BIT_MASK_QUEUEMACID_HIQ_V1_8197F) +#define BIT_SET_QUEUEMACID_HIQ_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) | BIT_QUEUEMACID_HIQ_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_HIQ_V1_8197F 23 #define BIT_MASK_QUEUEAC_HIQ_V1_8197F 0x3 -#define BIT_QUEUEAC_HIQ_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8197F) << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) -#define BITS_QUEUEAC_HIQ_V1_8197F (BIT_MASK_QUEUEAC_HIQ_V1_8197F << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) +#define BIT_QUEUEAC_HIQ_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8197F) \ + << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) +#define BITS_QUEUEAC_HIQ_V1_8197F \ + (BIT_MASK_QUEUEAC_HIQ_V1_8197F << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) #define BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8197F)) -#define BIT_GET_QUEUEAC_HIQ_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) & BIT_MASK_QUEUEAC_HIQ_V1_8197F) -#define BIT_SET_QUEUEAC_HIQ_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) | BIT_QUEUEAC_HIQ_V1_8197F(v)) +#define BIT_GET_QUEUEAC_HIQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) & \ + BIT_MASK_QUEUEAC_HIQ_V1_8197F) +#define BIT_SET_QUEUEAC_HIQ_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) | BIT_QUEUEAC_HIQ_V1_8197F(v)) #define BIT_TIDEMPTY_HIQ_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F 11 #define BIT_MASK_TAIL_PKT_HIQ_V2_8197F 0x7ff -#define BIT_TAIL_PKT_HIQ_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8197F) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) -#define BITS_TAIL_PKT_HIQ_V2_8197F (BIT_MASK_TAIL_PKT_HIQ_V2_8197F << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) +#define BIT_TAIL_PKT_HIQ_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) +#define BITS_TAIL_PKT_HIQ_V2_8197F \ + (BIT_MASK_TAIL_PKT_HIQ_V2_8197F << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) #define BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8197F)) -#define BIT_GET_TAIL_PKT_HIQ_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) & BIT_MASK_TAIL_PKT_HIQ_V2_8197F) -#define BIT_SET_TAIL_PKT_HIQ_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) | BIT_TAIL_PKT_HIQ_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_HIQ_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) & \ + BIT_MASK_TAIL_PKT_HIQ_V2_8197F) +#define BIT_SET_TAIL_PKT_HIQ_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) | BIT_TAIL_PKT_HIQ_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F 0 #define BIT_MASK_HEAD_PKT_HIQ_V1_8197F 0x7ff -#define BIT_HEAD_PKT_HIQ_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8197F) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) -#define BITS_HEAD_PKT_HIQ_V1_8197F (BIT_MASK_HEAD_PKT_HIQ_V1_8197F << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) +#define BIT_HEAD_PKT_HIQ_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) +#define BITS_HEAD_PKT_HIQ_V1_8197F \ + (BIT_MASK_HEAD_PKT_HIQ_V1_8197F << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) #define BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8197F)) -#define BIT_GET_HEAD_PKT_HIQ_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) & BIT_MASK_HEAD_PKT_HIQ_V1_8197F) -#define BIT_SET_HEAD_PKT_HIQ_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) | BIT_HEAD_PKT_HIQ_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_HIQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) & \ + BIT_MASK_HEAD_PKT_HIQ_V1_8197F) +#define BIT_SET_HEAD_PKT_HIQ_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) | BIT_HEAD_PKT_HIQ_V1_8197F(v)) /* 2 REG_BCNQ_INFO_8197F */ #define BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F 0 #define BIT_MASK_BCNQ_HEAD_PG_V1_8197F 0xfff -#define BIT_BCNQ_HEAD_PG_V1_8197F(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8197F) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) -#define BITS_BCNQ_HEAD_PG_V1_8197F (BIT_MASK_BCNQ_HEAD_PG_V1_8197F << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) +#define BIT_BCNQ_HEAD_PG_V1_8197F(x) \ + (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8197F) \ + << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) +#define BITS_BCNQ_HEAD_PG_V1_8197F \ + (BIT_MASK_BCNQ_HEAD_PG_V1_8197F << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) #define BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8197F)) -#define BIT_GET_BCNQ_HEAD_PG_V1_8197F(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) & BIT_MASK_BCNQ_HEAD_PG_V1_8197F) -#define BIT_SET_BCNQ_HEAD_PG_V1_8197F(x, v) (BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) | BIT_BCNQ_HEAD_PG_V1_8197F(v)) - +#define BIT_GET_BCNQ_HEAD_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) & \ + BIT_MASK_BCNQ_HEAD_PG_V1_8197F) +#define BIT_SET_BCNQ_HEAD_PG_V1_8197F(x, v) \ + (BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) | BIT_BCNQ_HEAD_PG_V1_8197F(v)) /* 2 REG_TXPKT_EMPTY_8197F */ #define BIT_BCNQ_EMPTY_8197F BIT(11) @@ -6434,12 +8227,17 @@ #define BIT_SHIFT_FW_FREE_TAIL_V1_8197F 0 #define BIT_MASK_FW_FREE_TAIL_V1_8197F 0xfff -#define BIT_FW_FREE_TAIL_V1_8197F(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8197F) << BIT_SHIFT_FW_FREE_TAIL_V1_8197F) -#define BITS_FW_FREE_TAIL_V1_8197F (BIT_MASK_FW_FREE_TAIL_V1_8197F << BIT_SHIFT_FW_FREE_TAIL_V1_8197F) +#define BIT_FW_FREE_TAIL_V1_8197F(x) \ + (((x) & BIT_MASK_FW_FREE_TAIL_V1_8197F) \ + << BIT_SHIFT_FW_FREE_TAIL_V1_8197F) +#define BITS_FW_FREE_TAIL_V1_8197F \ + (BIT_MASK_FW_FREE_TAIL_V1_8197F << BIT_SHIFT_FW_FREE_TAIL_V1_8197F) #define BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8197F)) -#define BIT_GET_FW_FREE_TAIL_V1_8197F(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8197F) & BIT_MASK_FW_FREE_TAIL_V1_8197F) -#define BIT_SET_FW_FREE_TAIL_V1_8197F(x, v) (BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) | BIT_FW_FREE_TAIL_V1_8197F(v)) - +#define BIT_GET_FW_FREE_TAIL_V1_8197F(x) \ + (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8197F) & \ + BIT_MASK_FW_FREE_TAIL_V1_8197F) +#define BIT_SET_FW_FREE_TAIL_V1_8197F(x, v) \ + (BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) | BIT_FW_FREE_TAIL_V1_8197F(v)) /* 2 REG_FWHW_TXQ_CTRL_8197F */ #define BIT_RTS_LIMIT_IN_OFDM_8197F BIT(23) @@ -6449,11 +8247,15 @@ #define BIT_SHIFT_EN_QUEUE_RPT_8197F 8 #define BIT_MASK_EN_QUEUE_RPT_8197F 0xff -#define BIT_EN_QUEUE_RPT_8197F(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8197F) << BIT_SHIFT_EN_QUEUE_RPT_8197F) -#define BITS_EN_QUEUE_RPT_8197F (BIT_MASK_EN_QUEUE_RPT_8197F << BIT_SHIFT_EN_QUEUE_RPT_8197F) +#define BIT_EN_QUEUE_RPT_8197F(x) \ + (((x) & BIT_MASK_EN_QUEUE_RPT_8197F) << BIT_SHIFT_EN_QUEUE_RPT_8197F) +#define BITS_EN_QUEUE_RPT_8197F \ + (BIT_MASK_EN_QUEUE_RPT_8197F << BIT_SHIFT_EN_QUEUE_RPT_8197F) #define BIT_CLEAR_EN_QUEUE_RPT_8197F(x) ((x) & (~BITS_EN_QUEUE_RPT_8197F)) -#define BIT_GET_EN_QUEUE_RPT_8197F(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8197F) & BIT_MASK_EN_QUEUE_RPT_8197F) -#define BIT_SET_EN_QUEUE_RPT_8197F(x, v) (BIT_CLEAR_EN_QUEUE_RPT_8197F(x) | BIT_EN_QUEUE_RPT_8197F(v)) +#define BIT_GET_EN_QUEUE_RPT_8197F(x) \ + (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8197F) & BIT_MASK_EN_QUEUE_RPT_8197F) +#define BIT_SET_EN_QUEUE_RPT_8197F(x, v) \ + (BIT_CLEAR_EN_QUEUE_RPT_8197F(x) | BIT_EN_QUEUE_RPT_8197F(v)) #define BIT_EN_RTY_BK_8197F BIT(7) #define BIT_EN_USE_INI_RAT_8197F BIT(6) @@ -6469,23 +8271,36 @@ #define BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F 0 #define BIT_MASK__R_DATA_FALLBACK_SEL_8197F 0x3 -#define BIT__R_DATA_FALLBACK_SEL_8197F(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8197F) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) -#define BITS__R_DATA_FALLBACK_SEL_8197F (BIT_MASK__R_DATA_FALLBACK_SEL_8197F << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) -#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) ((x) & (~BITS__R_DATA_FALLBACK_SEL_8197F)) -#define BIT_GET__R_DATA_FALLBACK_SEL_8197F(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) & BIT_MASK__R_DATA_FALLBACK_SEL_8197F) -#define BIT_SET__R_DATA_FALLBACK_SEL_8197F(x, v) (BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) | BIT__R_DATA_FALLBACK_SEL_8197F(v)) - +#define BIT__R_DATA_FALLBACK_SEL_8197F(x) \ + (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8197F) \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) +#define BITS__R_DATA_FALLBACK_SEL_8197F \ + (BIT_MASK__R_DATA_FALLBACK_SEL_8197F \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) +#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) \ + ((x) & (~BITS__R_DATA_FALLBACK_SEL_8197F)) +#define BIT_GET__R_DATA_FALLBACK_SEL_8197F(x) \ + (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) & \ + BIT_MASK__R_DATA_FALLBACK_SEL_8197F) +#define BIT_SET__R_DATA_FALLBACK_SEL_8197F(x, v) \ + (BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) | \ + BIT__R_DATA_FALLBACK_SEL_8197F(v)) /* 2 REG_BCNQ_BDNY_V1_8197F */ #define BIT_SHIFT_BCNQ_PGBNDY_V1_8197F 0 #define BIT_MASK_BCNQ_PGBNDY_V1_8197F 0xfff -#define BIT_BCNQ_PGBNDY_V1_8197F(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8197F) << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) -#define BITS_BCNQ_PGBNDY_V1_8197F (BIT_MASK_BCNQ_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) +#define BIT_BCNQ_PGBNDY_V1_8197F(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8197F) \ + << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) +#define BITS_BCNQ_PGBNDY_V1_8197F \ + (BIT_MASK_BCNQ_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) #define BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8197F)) -#define BIT_GET_BCNQ_PGBNDY_V1_8197F(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) & BIT_MASK_BCNQ_PGBNDY_V1_8197F) -#define BIT_SET_BCNQ_PGBNDY_V1_8197F(x, v) (BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) | BIT_BCNQ_PGBNDY_V1_8197F(v)) - +#define BIT_GET_BCNQ_PGBNDY_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) & \ + BIT_MASK_BCNQ_PGBNDY_V1_8197F) +#define BIT_SET_BCNQ_PGBNDY_V1_8197F(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) | BIT_BCNQ_PGBNDY_V1_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -6504,21 +8319,37 @@ #define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F 8 #define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F 0xff -#define BIT_SPEC_SIFS_OFDM_PTCL_8197F(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) -#define BITS_SPEC_SIFS_OFDM_PTCL_8197F (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) -#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8197F)) -#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8197F(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F) -#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8197F(x, v) (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) | BIT_SPEC_SIFS_OFDM_PTCL_8197F(v)) - +#define BIT_SPEC_SIFS_OFDM_PTCL_8197F(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) +#define BITS_SPEC_SIFS_OFDM_PTCL_8197F \ + (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) \ + ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8197F)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8197F(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) & \ + BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8197F(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) | \ + BIT_SPEC_SIFS_OFDM_PTCL_8197F(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F 0 #define BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F 0xff -#define BIT_SPEC_SIFS_CCK_PTCL_8197F(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) -#define BITS_SPEC_SIFS_CCK_PTCL_8197F (BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) -#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8197F)) -#define BIT_GET_SPEC_SIFS_CCK_PTCL_8197F(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F) -#define BIT_SET_SPEC_SIFS_CCK_PTCL_8197F(x, v) (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) | BIT_SPEC_SIFS_CCK_PTCL_8197F(v)) - +#define BIT_SPEC_SIFS_CCK_PTCL_8197F(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F) \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) +#define BITS_SPEC_SIFS_CCK_PTCL_8197F \ + (BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) \ + ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8197F)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8197F(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) & \ + BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F) +#define BIT_SET_SPEC_SIFS_CCK_PTCL_8197F(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) | \ + BIT_SPEC_SIFS_CCK_PTCL_8197F(v)) /* 2 REG_RETRY_LIMIT_8197F */ @@ -6530,7 +8361,6 @@ #define BIT_GET_SRL_8197F(x) (((x) >> BIT_SHIFT_SRL_8197F) & BIT_MASK_SRL_8197F) #define BIT_SET_SRL_8197F(x, v) (BIT_CLEAR_SRL_8197F(x) | BIT_SRL_8197F(v)) - #define BIT_SHIFT_LRL_8197F 0 #define BIT_MASK_LRL_8197F 0x3f #define BIT_LRL_8197F(x) (((x) & BIT_MASK_LRL_8197F) << BIT_SHIFT_LRL_8197F) @@ -6539,7 +8369,6 @@ #define BIT_GET_LRL_8197F(x) (((x) >> BIT_SHIFT_LRL_8197F) & BIT_MASK_LRL_8197F) #define BIT_SET_LRL_8197F(x, v) (BIT_CLEAR_LRL_8197F(x) | BIT_LRL_8197F(v)) - /* 2 REG_TXBF_CTRL_8197F */ #define BIT_R_ENABLE_NDPA_8197F BIT(31) #define BIT_USE_NDPA_PARAMETER_8197F BIT(30) @@ -6551,11 +8380,15 @@ #define BIT_SHIFT_R_TXBF1_AID_8197F 16 #define BIT_MASK_R_TXBF1_AID_8197F 0x1ff -#define BIT_R_TXBF1_AID_8197F(x) (((x) & BIT_MASK_R_TXBF1_AID_8197F) << BIT_SHIFT_R_TXBF1_AID_8197F) -#define BITS_R_TXBF1_AID_8197F (BIT_MASK_R_TXBF1_AID_8197F << BIT_SHIFT_R_TXBF1_AID_8197F) +#define BIT_R_TXBF1_AID_8197F(x) \ + (((x) & BIT_MASK_R_TXBF1_AID_8197F) << BIT_SHIFT_R_TXBF1_AID_8197F) +#define BITS_R_TXBF1_AID_8197F \ + (BIT_MASK_R_TXBF1_AID_8197F << BIT_SHIFT_R_TXBF1_AID_8197F) #define BIT_CLEAR_R_TXBF1_AID_8197F(x) ((x) & (~BITS_R_TXBF1_AID_8197F)) -#define BIT_GET_R_TXBF1_AID_8197F(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8197F) & BIT_MASK_R_TXBF1_AID_8197F) -#define BIT_SET_R_TXBF1_AID_8197F(x, v) (BIT_CLEAR_R_TXBF1_AID_8197F(x) | BIT_R_TXBF1_AID_8197F(v)) +#define BIT_GET_R_TXBF1_AID_8197F(x) \ + (((x) >> BIT_SHIFT_R_TXBF1_AID_8197F) & BIT_MASK_R_TXBF1_AID_8197F) +#define BIT_SET_R_TXBF1_AID_8197F(x, v) \ + (BIT_CLEAR_R_TXBF1_AID_8197F(x) | BIT_R_TXBF1_AID_8197F(v)) #define BIT_DIS_NDP_BFEN_8197F BIT(15) #define BIT_R_TXBCN_NOBLOCK_NDP_8197F BIT(14) @@ -6565,160 +8398,211 @@ #define BIT_SHIFT_R_TXBF0_AID_8197F 0 #define BIT_MASK_R_TXBF0_AID_8197F 0x1ff -#define BIT_R_TXBF0_AID_8197F(x) (((x) & BIT_MASK_R_TXBF0_AID_8197F) << BIT_SHIFT_R_TXBF0_AID_8197F) -#define BITS_R_TXBF0_AID_8197F (BIT_MASK_R_TXBF0_AID_8197F << BIT_SHIFT_R_TXBF0_AID_8197F) +#define BIT_R_TXBF0_AID_8197F(x) \ + (((x) & BIT_MASK_R_TXBF0_AID_8197F) << BIT_SHIFT_R_TXBF0_AID_8197F) +#define BITS_R_TXBF0_AID_8197F \ + (BIT_MASK_R_TXBF0_AID_8197F << BIT_SHIFT_R_TXBF0_AID_8197F) #define BIT_CLEAR_R_TXBF0_AID_8197F(x) ((x) & (~BITS_R_TXBF0_AID_8197F)) -#define BIT_GET_R_TXBF0_AID_8197F(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8197F) & BIT_MASK_R_TXBF0_AID_8197F) -#define BIT_SET_R_TXBF0_AID_8197F(x, v) (BIT_CLEAR_R_TXBF0_AID_8197F(x) | BIT_R_TXBF0_AID_8197F(v)) - +#define BIT_GET_R_TXBF0_AID_8197F(x) \ + (((x) >> BIT_SHIFT_R_TXBF0_AID_8197F) & BIT_MASK_R_TXBF0_AID_8197F) +#define BIT_SET_R_TXBF0_AID_8197F(x, v) \ + (BIT_CLEAR_R_TXBF0_AID_8197F(x) | BIT_R_TXBF0_AID_8197F(v)) /* 2 REG_DARFRC_8197F */ -#define BIT_SHIFT_DARF_RC8_8197F (56 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC8_8197F 0x1f -#define BIT_DARF_RC8_8197F(x) (((x) & BIT_MASK_DARF_RC8_8197F) << BIT_SHIFT_DARF_RC8_8197F) -#define BITS_DARF_RC8_8197F (BIT_MASK_DARF_RC8_8197F << BIT_SHIFT_DARF_RC8_8197F) -#define BIT_CLEAR_DARF_RC8_8197F(x) ((x) & (~BITS_DARF_RC8_8197F)) -#define BIT_GET_DARF_RC8_8197F(x) (((x) >> BIT_SHIFT_DARF_RC8_8197F) & BIT_MASK_DARF_RC8_8197F) -#define BIT_SET_DARF_RC8_8197F(x, v) (BIT_CLEAR_DARF_RC8_8197F(x) | BIT_DARF_RC8_8197F(v)) - - -#define BIT_SHIFT_DARF_RC7_8197F (48 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC7_8197F 0x1f -#define BIT_DARF_RC7_8197F(x) (((x) & BIT_MASK_DARF_RC7_8197F) << BIT_SHIFT_DARF_RC7_8197F) -#define BITS_DARF_RC7_8197F (BIT_MASK_DARF_RC7_8197F << BIT_SHIFT_DARF_RC7_8197F) -#define BIT_CLEAR_DARF_RC7_8197F(x) ((x) & (~BITS_DARF_RC7_8197F)) -#define BIT_GET_DARF_RC7_8197F(x) (((x) >> BIT_SHIFT_DARF_RC7_8197F) & BIT_MASK_DARF_RC7_8197F) -#define BIT_SET_DARF_RC7_8197F(x, v) (BIT_CLEAR_DARF_RC7_8197F(x) | BIT_DARF_RC7_8197F(v)) - - -#define BIT_SHIFT_DARF_RC6_8197F (40 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC6_8197F 0x1f -#define BIT_DARF_RC6_8197F(x) (((x) & BIT_MASK_DARF_RC6_8197F) << BIT_SHIFT_DARF_RC6_8197F) -#define BITS_DARF_RC6_8197F (BIT_MASK_DARF_RC6_8197F << BIT_SHIFT_DARF_RC6_8197F) -#define BIT_CLEAR_DARF_RC6_8197F(x) ((x) & (~BITS_DARF_RC6_8197F)) -#define BIT_GET_DARF_RC6_8197F(x) (((x) >> BIT_SHIFT_DARF_RC6_8197F) & BIT_MASK_DARF_RC6_8197F) -#define BIT_SET_DARF_RC6_8197F(x, v) (BIT_CLEAR_DARF_RC6_8197F(x) | BIT_DARF_RC6_8197F(v)) - - -#define BIT_SHIFT_DARF_RC5_8197F (32 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC5_8197F 0x1f -#define BIT_DARF_RC5_8197F(x) (((x) & BIT_MASK_DARF_RC5_8197F) << BIT_SHIFT_DARF_RC5_8197F) -#define BITS_DARF_RC5_8197F (BIT_MASK_DARF_RC5_8197F << BIT_SHIFT_DARF_RC5_8197F) -#define BIT_CLEAR_DARF_RC5_8197F(x) ((x) & (~BITS_DARF_RC5_8197F)) -#define BIT_GET_DARF_RC5_8197F(x) (((x) >> BIT_SHIFT_DARF_RC5_8197F) & BIT_MASK_DARF_RC5_8197F) -#define BIT_SET_DARF_RC5_8197F(x, v) (BIT_CLEAR_DARF_RC5_8197F(x) | BIT_DARF_RC5_8197F(v)) - - -#define BIT_SHIFT_DARF_RC4_8197F 24 -#define BIT_MASK_DARF_RC4_8197F 0x1f -#define BIT_DARF_RC4_8197F(x) (((x) & BIT_MASK_DARF_RC4_8197F) << BIT_SHIFT_DARF_RC4_8197F) -#define BITS_DARF_RC4_8197F (BIT_MASK_DARF_RC4_8197F << BIT_SHIFT_DARF_RC4_8197F) -#define BIT_CLEAR_DARF_RC4_8197F(x) ((x) & (~BITS_DARF_RC4_8197F)) -#define BIT_GET_DARF_RC4_8197F(x) (((x) >> BIT_SHIFT_DARF_RC4_8197F) & BIT_MASK_DARF_RC4_8197F) -#define BIT_SET_DARF_RC4_8197F(x, v) (BIT_CLEAR_DARF_RC4_8197F(x) | BIT_DARF_RC4_8197F(v)) - - -#define BIT_SHIFT_DARF_RC3_8197F 16 -#define BIT_MASK_DARF_RC3_8197F 0x1f -#define BIT_DARF_RC3_8197F(x) (((x) & BIT_MASK_DARF_RC3_8197F) << BIT_SHIFT_DARF_RC3_8197F) -#define BITS_DARF_RC3_8197F (BIT_MASK_DARF_RC3_8197F << BIT_SHIFT_DARF_RC3_8197F) -#define BIT_CLEAR_DARF_RC3_8197F(x) ((x) & (~BITS_DARF_RC3_8197F)) -#define BIT_GET_DARF_RC3_8197F(x) (((x) >> BIT_SHIFT_DARF_RC3_8197F) & BIT_MASK_DARF_RC3_8197F) -#define BIT_SET_DARF_RC3_8197F(x, v) (BIT_CLEAR_DARF_RC3_8197F(x) | BIT_DARF_RC3_8197F(v)) - - -#define BIT_SHIFT_DARF_RC2_8197F 8 -#define BIT_MASK_DARF_RC2_8197F 0x1f -#define BIT_DARF_RC2_8197F(x) (((x) & BIT_MASK_DARF_RC2_8197F) << BIT_SHIFT_DARF_RC2_8197F) -#define BITS_DARF_RC2_8197F (BIT_MASK_DARF_RC2_8197F << BIT_SHIFT_DARF_RC2_8197F) -#define BIT_CLEAR_DARF_RC2_8197F(x) ((x) & (~BITS_DARF_RC2_8197F)) -#define BIT_GET_DARF_RC2_8197F(x) (((x) >> BIT_SHIFT_DARF_RC2_8197F) & BIT_MASK_DARF_RC2_8197F) -#define BIT_SET_DARF_RC2_8197F(x, v) (BIT_CLEAR_DARF_RC2_8197F(x) | BIT_DARF_RC2_8197F(v)) - - -#define BIT_SHIFT_DARF_RC1_8197F 0 -#define BIT_MASK_DARF_RC1_8197F 0x1f -#define BIT_DARF_RC1_8197F(x) (((x) & BIT_MASK_DARF_RC1_8197F) << BIT_SHIFT_DARF_RC1_8197F) -#define BITS_DARF_RC1_8197F (BIT_MASK_DARF_RC1_8197F << BIT_SHIFT_DARF_RC1_8197F) -#define BIT_CLEAR_DARF_RC1_8197F(x) ((x) & (~BITS_DARF_RC1_8197F)) -#define BIT_GET_DARF_RC1_8197F(x) (((x) >> BIT_SHIFT_DARF_RC1_8197F) & BIT_MASK_DARF_RC1_8197F) -#define BIT_SET_DARF_RC1_8197F(x, v) (BIT_CLEAR_DARF_RC1_8197F(x) | BIT_DARF_RC1_8197F(v)) - +#define BIT_SHIFT_DARF_RC8_V2_8197F (56 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC8_V2_8197F 0x3f +#define BIT_DARF_RC8_V2_8197F(x) \ + (((x) & BIT_MASK_DARF_RC8_V2_8197F) << BIT_SHIFT_DARF_RC8_V2_8197F) +#define BITS_DARF_RC8_V2_8197F \ + (BIT_MASK_DARF_RC8_V2_8197F << BIT_SHIFT_DARF_RC8_V2_8197F) +#define BIT_CLEAR_DARF_RC8_V2_8197F(x) ((x) & (~BITS_DARF_RC8_V2_8197F)) +#define BIT_GET_DARF_RC8_V2_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_V2_8197F) & BIT_MASK_DARF_RC8_V2_8197F) +#define BIT_SET_DARF_RC8_V2_8197F(x, v) \ + (BIT_CLEAR_DARF_RC8_V2_8197F(x) | BIT_DARF_RC8_V2_8197F(v)) + +#define BIT_SHIFT_DARF_RC7_V2_8197F (48 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC7_V2_8197F 0x3f +#define BIT_DARF_RC7_V2_8197F(x) \ + (((x) & BIT_MASK_DARF_RC7_V2_8197F) << BIT_SHIFT_DARF_RC7_V2_8197F) +#define BITS_DARF_RC7_V2_8197F \ + (BIT_MASK_DARF_RC7_V2_8197F << BIT_SHIFT_DARF_RC7_V2_8197F) +#define BIT_CLEAR_DARF_RC7_V2_8197F(x) ((x) & (~BITS_DARF_RC7_V2_8197F)) +#define BIT_GET_DARF_RC7_V2_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_V2_8197F) & BIT_MASK_DARF_RC7_V2_8197F) +#define BIT_SET_DARF_RC7_V2_8197F(x, v) \ + (BIT_CLEAR_DARF_RC7_V2_8197F(x) | BIT_DARF_RC7_V2_8197F(v)) + +#define BIT_SHIFT_DARF_RC6_V2_8197F (40 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC6_V2_8197F 0x3f +#define BIT_DARF_RC6_V2_8197F(x) \ + (((x) & BIT_MASK_DARF_RC6_V2_8197F) << BIT_SHIFT_DARF_RC6_V2_8197F) +#define BITS_DARF_RC6_V2_8197F \ + (BIT_MASK_DARF_RC6_V2_8197F << BIT_SHIFT_DARF_RC6_V2_8197F) +#define BIT_CLEAR_DARF_RC6_V2_8197F(x) ((x) & (~BITS_DARF_RC6_V2_8197F)) +#define BIT_GET_DARF_RC6_V2_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_V2_8197F) & BIT_MASK_DARF_RC6_V2_8197F) +#define BIT_SET_DARF_RC6_V2_8197F(x, v) \ + (BIT_CLEAR_DARF_RC6_V2_8197F(x) | BIT_DARF_RC6_V2_8197F(v)) + +#define BIT_SHIFT_DARF_RC5_V2_8197F (32 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC5_V2_8197F 0x3f +#define BIT_DARF_RC5_V2_8197F(x) \ + (((x) & BIT_MASK_DARF_RC5_V2_8197F) << BIT_SHIFT_DARF_RC5_V2_8197F) +#define BITS_DARF_RC5_V2_8197F \ + (BIT_MASK_DARF_RC5_V2_8197F << BIT_SHIFT_DARF_RC5_V2_8197F) +#define BIT_CLEAR_DARF_RC5_V2_8197F(x) ((x) & (~BITS_DARF_RC5_V2_8197F)) +#define BIT_GET_DARF_RC5_V2_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_V2_8197F) & BIT_MASK_DARF_RC5_V2_8197F) +#define BIT_SET_DARF_RC5_V2_8197F(x, v) \ + (BIT_CLEAR_DARF_RC5_V2_8197F(x) | BIT_DARF_RC5_V2_8197F(v)) + +#define BIT_SHIFT_DARF_RC4_V1_8197F 24 +#define BIT_MASK_DARF_RC4_V1_8197F 0x3f +#define BIT_DARF_RC4_V1_8197F(x) \ + (((x) & BIT_MASK_DARF_RC4_V1_8197F) << BIT_SHIFT_DARF_RC4_V1_8197F) +#define BITS_DARF_RC4_V1_8197F \ + (BIT_MASK_DARF_RC4_V1_8197F << BIT_SHIFT_DARF_RC4_V1_8197F) +#define BIT_CLEAR_DARF_RC4_V1_8197F(x) ((x) & (~BITS_DARF_RC4_V1_8197F)) +#define BIT_GET_DARF_RC4_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_V1_8197F) & BIT_MASK_DARF_RC4_V1_8197F) +#define BIT_SET_DARF_RC4_V1_8197F(x, v) \ + (BIT_CLEAR_DARF_RC4_V1_8197F(x) | BIT_DARF_RC4_V1_8197F(v)) + +#define BIT_SHIFT_DARF_RC3_V1_8197F 16 +#define BIT_MASK_DARF_RC3_V1_8197F 0x3f +#define BIT_DARF_RC3_V1_8197F(x) \ + (((x) & BIT_MASK_DARF_RC3_V1_8197F) << BIT_SHIFT_DARF_RC3_V1_8197F) +#define BITS_DARF_RC3_V1_8197F \ + (BIT_MASK_DARF_RC3_V1_8197F << BIT_SHIFT_DARF_RC3_V1_8197F) +#define BIT_CLEAR_DARF_RC3_V1_8197F(x) ((x) & (~BITS_DARF_RC3_V1_8197F)) +#define BIT_GET_DARF_RC3_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_V1_8197F) & BIT_MASK_DARF_RC3_V1_8197F) +#define BIT_SET_DARF_RC3_V1_8197F(x, v) \ + (BIT_CLEAR_DARF_RC3_V1_8197F(x) | BIT_DARF_RC3_V1_8197F(v)) + +#define BIT_SHIFT_DARF_RC2_V1_8197F 8 +#define BIT_MASK_DARF_RC2_V1_8197F 0x3f +#define BIT_DARF_RC2_V1_8197F(x) \ + (((x) & BIT_MASK_DARF_RC2_V1_8197F) << BIT_SHIFT_DARF_RC2_V1_8197F) +#define BITS_DARF_RC2_V1_8197F \ + (BIT_MASK_DARF_RC2_V1_8197F << BIT_SHIFT_DARF_RC2_V1_8197F) +#define BIT_CLEAR_DARF_RC2_V1_8197F(x) ((x) & (~BITS_DARF_RC2_V1_8197F)) +#define BIT_GET_DARF_RC2_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_V1_8197F) & BIT_MASK_DARF_RC2_V1_8197F) +#define BIT_SET_DARF_RC2_V1_8197F(x, v) \ + (BIT_CLEAR_DARF_RC2_V1_8197F(x) | BIT_DARF_RC2_V1_8197F(v)) + +#define BIT_SHIFT_DARF_RC1_V1_8197F 0 +#define BIT_MASK_DARF_RC1_V1_8197F 0x3f +#define BIT_DARF_RC1_V1_8197F(x) \ + (((x) & BIT_MASK_DARF_RC1_V1_8197F) << BIT_SHIFT_DARF_RC1_V1_8197F) +#define BITS_DARF_RC1_V1_8197F \ + (BIT_MASK_DARF_RC1_V1_8197F << BIT_SHIFT_DARF_RC1_V1_8197F) +#define BIT_CLEAR_DARF_RC1_V1_8197F(x) ((x) & (~BITS_DARF_RC1_V1_8197F)) +#define BIT_GET_DARF_RC1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_V1_8197F) & BIT_MASK_DARF_RC1_V1_8197F) +#define BIT_SET_DARF_RC1_V1_8197F(x, v) \ + (BIT_CLEAR_DARF_RC1_V1_8197F(x) | BIT_DARF_RC1_V1_8197F(v)) /* 2 REG_RARFRC_8197F */ #define BIT_SHIFT_RARF_RC8_8197F (56 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC8_8197F 0x1f -#define BIT_RARF_RC8_8197F(x) (((x) & BIT_MASK_RARF_RC8_8197F) << BIT_SHIFT_RARF_RC8_8197F) -#define BITS_RARF_RC8_8197F (BIT_MASK_RARF_RC8_8197F << BIT_SHIFT_RARF_RC8_8197F) +#define BIT_RARF_RC8_8197F(x) \ + (((x) & BIT_MASK_RARF_RC8_8197F) << BIT_SHIFT_RARF_RC8_8197F) +#define BITS_RARF_RC8_8197F \ + (BIT_MASK_RARF_RC8_8197F << BIT_SHIFT_RARF_RC8_8197F) #define BIT_CLEAR_RARF_RC8_8197F(x) ((x) & (~BITS_RARF_RC8_8197F)) -#define BIT_GET_RARF_RC8_8197F(x) (((x) >> BIT_SHIFT_RARF_RC8_8197F) & BIT_MASK_RARF_RC8_8197F) -#define BIT_SET_RARF_RC8_8197F(x, v) (BIT_CLEAR_RARF_RC8_8197F(x) | BIT_RARF_RC8_8197F(v)) - +#define BIT_GET_RARF_RC8_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC8_8197F) & BIT_MASK_RARF_RC8_8197F) +#define BIT_SET_RARF_RC8_8197F(x, v) \ + (BIT_CLEAR_RARF_RC8_8197F(x) | BIT_RARF_RC8_8197F(v)) #define BIT_SHIFT_RARF_RC7_8197F (48 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC7_8197F 0x1f -#define BIT_RARF_RC7_8197F(x) (((x) & BIT_MASK_RARF_RC7_8197F) << BIT_SHIFT_RARF_RC7_8197F) -#define BITS_RARF_RC7_8197F (BIT_MASK_RARF_RC7_8197F << BIT_SHIFT_RARF_RC7_8197F) +#define BIT_RARF_RC7_8197F(x) \ + (((x) & BIT_MASK_RARF_RC7_8197F) << BIT_SHIFT_RARF_RC7_8197F) +#define BITS_RARF_RC7_8197F \ + (BIT_MASK_RARF_RC7_8197F << BIT_SHIFT_RARF_RC7_8197F) #define BIT_CLEAR_RARF_RC7_8197F(x) ((x) & (~BITS_RARF_RC7_8197F)) -#define BIT_GET_RARF_RC7_8197F(x) (((x) >> BIT_SHIFT_RARF_RC7_8197F) & BIT_MASK_RARF_RC7_8197F) -#define BIT_SET_RARF_RC7_8197F(x, v) (BIT_CLEAR_RARF_RC7_8197F(x) | BIT_RARF_RC7_8197F(v)) - +#define BIT_GET_RARF_RC7_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC7_8197F) & BIT_MASK_RARF_RC7_8197F) +#define BIT_SET_RARF_RC7_8197F(x, v) \ + (BIT_CLEAR_RARF_RC7_8197F(x) | BIT_RARF_RC7_8197F(v)) #define BIT_SHIFT_RARF_RC6_8197F (40 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC6_8197F 0x1f -#define BIT_RARF_RC6_8197F(x) (((x) & BIT_MASK_RARF_RC6_8197F) << BIT_SHIFT_RARF_RC6_8197F) -#define BITS_RARF_RC6_8197F (BIT_MASK_RARF_RC6_8197F << BIT_SHIFT_RARF_RC6_8197F) +#define BIT_RARF_RC6_8197F(x) \ + (((x) & BIT_MASK_RARF_RC6_8197F) << BIT_SHIFT_RARF_RC6_8197F) +#define BITS_RARF_RC6_8197F \ + (BIT_MASK_RARF_RC6_8197F << BIT_SHIFT_RARF_RC6_8197F) #define BIT_CLEAR_RARF_RC6_8197F(x) ((x) & (~BITS_RARF_RC6_8197F)) -#define BIT_GET_RARF_RC6_8197F(x) (((x) >> BIT_SHIFT_RARF_RC6_8197F) & BIT_MASK_RARF_RC6_8197F) -#define BIT_SET_RARF_RC6_8197F(x, v) (BIT_CLEAR_RARF_RC6_8197F(x) | BIT_RARF_RC6_8197F(v)) - +#define BIT_GET_RARF_RC6_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC6_8197F) & BIT_MASK_RARF_RC6_8197F) +#define BIT_SET_RARF_RC6_8197F(x, v) \ + (BIT_CLEAR_RARF_RC6_8197F(x) | BIT_RARF_RC6_8197F(v)) #define BIT_SHIFT_RARF_RC5_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC5_8197F 0x1f -#define BIT_RARF_RC5_8197F(x) (((x) & BIT_MASK_RARF_RC5_8197F) << BIT_SHIFT_RARF_RC5_8197F) -#define BITS_RARF_RC5_8197F (BIT_MASK_RARF_RC5_8197F << BIT_SHIFT_RARF_RC5_8197F) +#define BIT_RARF_RC5_8197F(x) \ + (((x) & BIT_MASK_RARF_RC5_8197F) << BIT_SHIFT_RARF_RC5_8197F) +#define BITS_RARF_RC5_8197F \ + (BIT_MASK_RARF_RC5_8197F << BIT_SHIFT_RARF_RC5_8197F) #define BIT_CLEAR_RARF_RC5_8197F(x) ((x) & (~BITS_RARF_RC5_8197F)) -#define BIT_GET_RARF_RC5_8197F(x) (((x) >> BIT_SHIFT_RARF_RC5_8197F) & BIT_MASK_RARF_RC5_8197F) -#define BIT_SET_RARF_RC5_8197F(x, v) (BIT_CLEAR_RARF_RC5_8197F(x) | BIT_RARF_RC5_8197F(v)) - +#define BIT_GET_RARF_RC5_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC5_8197F) & BIT_MASK_RARF_RC5_8197F) +#define BIT_SET_RARF_RC5_8197F(x, v) \ + (BIT_CLEAR_RARF_RC5_8197F(x) | BIT_RARF_RC5_8197F(v)) #define BIT_SHIFT_RARF_RC4_8197F 24 #define BIT_MASK_RARF_RC4_8197F 0x1f -#define BIT_RARF_RC4_8197F(x) (((x) & BIT_MASK_RARF_RC4_8197F) << BIT_SHIFT_RARF_RC4_8197F) -#define BITS_RARF_RC4_8197F (BIT_MASK_RARF_RC4_8197F << BIT_SHIFT_RARF_RC4_8197F) +#define BIT_RARF_RC4_8197F(x) \ + (((x) & BIT_MASK_RARF_RC4_8197F) << BIT_SHIFT_RARF_RC4_8197F) +#define BITS_RARF_RC4_8197F \ + (BIT_MASK_RARF_RC4_8197F << BIT_SHIFT_RARF_RC4_8197F) #define BIT_CLEAR_RARF_RC4_8197F(x) ((x) & (~BITS_RARF_RC4_8197F)) -#define BIT_GET_RARF_RC4_8197F(x) (((x) >> BIT_SHIFT_RARF_RC4_8197F) & BIT_MASK_RARF_RC4_8197F) -#define BIT_SET_RARF_RC4_8197F(x, v) (BIT_CLEAR_RARF_RC4_8197F(x) | BIT_RARF_RC4_8197F(v)) - +#define BIT_GET_RARF_RC4_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC4_8197F) & BIT_MASK_RARF_RC4_8197F) +#define BIT_SET_RARF_RC4_8197F(x, v) \ + (BIT_CLEAR_RARF_RC4_8197F(x) | BIT_RARF_RC4_8197F(v)) #define BIT_SHIFT_RARF_RC3_8197F 16 #define BIT_MASK_RARF_RC3_8197F 0x1f -#define BIT_RARF_RC3_8197F(x) (((x) & BIT_MASK_RARF_RC3_8197F) << BIT_SHIFT_RARF_RC3_8197F) -#define BITS_RARF_RC3_8197F (BIT_MASK_RARF_RC3_8197F << BIT_SHIFT_RARF_RC3_8197F) +#define BIT_RARF_RC3_8197F(x) \ + (((x) & BIT_MASK_RARF_RC3_8197F) << BIT_SHIFT_RARF_RC3_8197F) +#define BITS_RARF_RC3_8197F \ + (BIT_MASK_RARF_RC3_8197F << BIT_SHIFT_RARF_RC3_8197F) #define BIT_CLEAR_RARF_RC3_8197F(x) ((x) & (~BITS_RARF_RC3_8197F)) -#define BIT_GET_RARF_RC3_8197F(x) (((x) >> BIT_SHIFT_RARF_RC3_8197F) & BIT_MASK_RARF_RC3_8197F) -#define BIT_SET_RARF_RC3_8197F(x, v) (BIT_CLEAR_RARF_RC3_8197F(x) | BIT_RARF_RC3_8197F(v)) - +#define BIT_GET_RARF_RC3_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC3_8197F) & BIT_MASK_RARF_RC3_8197F) +#define BIT_SET_RARF_RC3_8197F(x, v) \ + (BIT_CLEAR_RARF_RC3_8197F(x) | BIT_RARF_RC3_8197F(v)) #define BIT_SHIFT_RARF_RC2_8197F 8 #define BIT_MASK_RARF_RC2_8197F 0x1f -#define BIT_RARF_RC2_8197F(x) (((x) & BIT_MASK_RARF_RC2_8197F) << BIT_SHIFT_RARF_RC2_8197F) -#define BITS_RARF_RC2_8197F (BIT_MASK_RARF_RC2_8197F << BIT_SHIFT_RARF_RC2_8197F) +#define BIT_RARF_RC2_8197F(x) \ + (((x) & BIT_MASK_RARF_RC2_8197F) << BIT_SHIFT_RARF_RC2_8197F) +#define BITS_RARF_RC2_8197F \ + (BIT_MASK_RARF_RC2_8197F << BIT_SHIFT_RARF_RC2_8197F) #define BIT_CLEAR_RARF_RC2_8197F(x) ((x) & (~BITS_RARF_RC2_8197F)) -#define BIT_GET_RARF_RC2_8197F(x) (((x) >> BIT_SHIFT_RARF_RC2_8197F) & BIT_MASK_RARF_RC2_8197F) -#define BIT_SET_RARF_RC2_8197F(x, v) (BIT_CLEAR_RARF_RC2_8197F(x) | BIT_RARF_RC2_8197F(v)) - +#define BIT_GET_RARF_RC2_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC2_8197F) & BIT_MASK_RARF_RC2_8197F) +#define BIT_SET_RARF_RC2_8197F(x, v) \ + (BIT_CLEAR_RARF_RC2_8197F(x) | BIT_RARF_RC2_8197F(v)) #define BIT_SHIFT_RARF_RC1_8197F 0 #define BIT_MASK_RARF_RC1_8197F 0x1f -#define BIT_RARF_RC1_8197F(x) (((x) & BIT_MASK_RARF_RC1_8197F) << BIT_SHIFT_RARF_RC1_8197F) -#define BITS_RARF_RC1_8197F (BIT_MASK_RARF_RC1_8197F << BIT_SHIFT_RARF_RC1_8197F) +#define BIT_RARF_RC1_8197F(x) \ + (((x) & BIT_MASK_RARF_RC1_8197F) << BIT_SHIFT_RARF_RC1_8197F) +#define BITS_RARF_RC1_8197F \ + (BIT_MASK_RARF_RC1_8197F << BIT_SHIFT_RARF_RC1_8197F) #define BIT_CLEAR_RARF_RC1_8197F(x) ((x) & (~BITS_RARF_RC1_8197F)) -#define BIT_GET_RARF_RC1_8197F(x) (((x) >> BIT_SHIFT_RARF_RC1_8197F) & BIT_MASK_RARF_RC1_8197F) -#define BIT_SET_RARF_RC1_8197F(x, v) (BIT_CLEAR_RARF_RC1_8197F(x) | BIT_RARF_RC1_8197F(v)) - +#define BIT_GET_RARF_RC1_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC1_8197F) & BIT_MASK_RARF_RC1_8197F) +#define BIT_SET_RARF_RC1_8197F(x, v) \ + (BIT_CLEAR_RARF_RC1_8197F(x) | BIT_RARF_RC1_8197F(v)) /* 2 REG_RRSR_8197F */ #define BIT_EN_VHTBW_FALL_8197F BIT(31) @@ -6726,44 +8610,57 @@ #define BIT_SHIFT_RRSR_RSC_8197F 21 #define BIT_MASK_RRSR_RSC_8197F 0x3 -#define BIT_RRSR_RSC_8197F(x) (((x) & BIT_MASK_RRSR_RSC_8197F) << BIT_SHIFT_RRSR_RSC_8197F) -#define BITS_RRSR_RSC_8197F (BIT_MASK_RRSR_RSC_8197F << BIT_SHIFT_RRSR_RSC_8197F) +#define BIT_RRSR_RSC_8197F(x) \ + (((x) & BIT_MASK_RRSR_RSC_8197F) << BIT_SHIFT_RRSR_RSC_8197F) +#define BITS_RRSR_RSC_8197F \ + (BIT_MASK_RRSR_RSC_8197F << BIT_SHIFT_RRSR_RSC_8197F) #define BIT_CLEAR_RRSR_RSC_8197F(x) ((x) & (~BITS_RRSR_RSC_8197F)) -#define BIT_GET_RRSR_RSC_8197F(x) (((x) >> BIT_SHIFT_RRSR_RSC_8197F) & BIT_MASK_RRSR_RSC_8197F) -#define BIT_SET_RRSR_RSC_8197F(x, v) (BIT_CLEAR_RRSR_RSC_8197F(x) | BIT_RRSR_RSC_8197F(v)) +#define BIT_GET_RRSR_RSC_8197F(x) \ + (((x) >> BIT_SHIFT_RRSR_RSC_8197F) & BIT_MASK_RRSR_RSC_8197F) +#define BIT_SET_RRSR_RSC_8197F(x, v) \ + (BIT_CLEAR_RRSR_RSC_8197F(x) | BIT_RRSR_RSC_8197F(v)) #define BIT_RRSR_BW_8197F BIT(20) #define BIT_SHIFT_RRSC_BITMAP_8197F 0 #define BIT_MASK_RRSC_BITMAP_8197F 0xfffff -#define BIT_RRSC_BITMAP_8197F(x) (((x) & BIT_MASK_RRSC_BITMAP_8197F) << BIT_SHIFT_RRSC_BITMAP_8197F) -#define BITS_RRSC_BITMAP_8197F (BIT_MASK_RRSC_BITMAP_8197F << BIT_SHIFT_RRSC_BITMAP_8197F) +#define BIT_RRSC_BITMAP_8197F(x) \ + (((x) & BIT_MASK_RRSC_BITMAP_8197F) << BIT_SHIFT_RRSC_BITMAP_8197F) +#define BITS_RRSC_BITMAP_8197F \ + (BIT_MASK_RRSC_BITMAP_8197F << BIT_SHIFT_RRSC_BITMAP_8197F) #define BIT_CLEAR_RRSC_BITMAP_8197F(x) ((x) & (~BITS_RRSC_BITMAP_8197F)) -#define BIT_GET_RRSC_BITMAP_8197F(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8197F) & BIT_MASK_RRSC_BITMAP_8197F) -#define BIT_SET_RRSC_BITMAP_8197F(x, v) (BIT_CLEAR_RRSC_BITMAP_8197F(x) | BIT_RRSC_BITMAP_8197F(v)) - +#define BIT_GET_RRSC_BITMAP_8197F(x) \ + (((x) >> BIT_SHIFT_RRSC_BITMAP_8197F) & BIT_MASK_RRSC_BITMAP_8197F) +#define BIT_SET_RRSC_BITMAP_8197F(x, v) \ + (BIT_CLEAR_RRSC_BITMAP_8197F(x) | BIT_RRSC_BITMAP_8197F(v)) /* 2 REG_ARFR0_8197F */ #define BIT_SHIFT_ARFR0_V1_8197F 0 #define BIT_MASK_ARFR0_V1_8197F 0xffffffffffffffffL -#define BIT_ARFR0_V1_8197F(x) (((x) & BIT_MASK_ARFR0_V1_8197F) << BIT_SHIFT_ARFR0_V1_8197F) -#define BITS_ARFR0_V1_8197F (BIT_MASK_ARFR0_V1_8197F << BIT_SHIFT_ARFR0_V1_8197F) +#define BIT_ARFR0_V1_8197F(x) \ + (((x) & BIT_MASK_ARFR0_V1_8197F) << BIT_SHIFT_ARFR0_V1_8197F) +#define BITS_ARFR0_V1_8197F \ + (BIT_MASK_ARFR0_V1_8197F << BIT_SHIFT_ARFR0_V1_8197F) #define BIT_CLEAR_ARFR0_V1_8197F(x) ((x) & (~BITS_ARFR0_V1_8197F)) -#define BIT_GET_ARFR0_V1_8197F(x) (((x) >> BIT_SHIFT_ARFR0_V1_8197F) & BIT_MASK_ARFR0_V1_8197F) -#define BIT_SET_ARFR0_V1_8197F(x, v) (BIT_CLEAR_ARFR0_V1_8197F(x) | BIT_ARFR0_V1_8197F(v)) - +#define BIT_GET_ARFR0_V1_8197F(x) \ + (((x) >> BIT_SHIFT_ARFR0_V1_8197F) & BIT_MASK_ARFR0_V1_8197F) +#define BIT_SET_ARFR0_V1_8197F(x, v) \ + (BIT_CLEAR_ARFR0_V1_8197F(x) | BIT_ARFR0_V1_8197F(v)) /* 2 REG_ARFR1_V1_8197F */ #define BIT_SHIFT_ARFR1_V1_8197F 0 #define BIT_MASK_ARFR1_V1_8197F 0xffffffffffffffffL -#define BIT_ARFR1_V1_8197F(x) (((x) & BIT_MASK_ARFR1_V1_8197F) << BIT_SHIFT_ARFR1_V1_8197F) -#define BITS_ARFR1_V1_8197F (BIT_MASK_ARFR1_V1_8197F << BIT_SHIFT_ARFR1_V1_8197F) +#define BIT_ARFR1_V1_8197F(x) \ + (((x) & BIT_MASK_ARFR1_V1_8197F) << BIT_SHIFT_ARFR1_V1_8197F) +#define BITS_ARFR1_V1_8197F \ + (BIT_MASK_ARFR1_V1_8197F << BIT_SHIFT_ARFR1_V1_8197F) #define BIT_CLEAR_ARFR1_V1_8197F(x) ((x) & (~BITS_ARFR1_V1_8197F)) -#define BIT_GET_ARFR1_V1_8197F(x) (((x) >> BIT_SHIFT_ARFR1_V1_8197F) & BIT_MASK_ARFR1_V1_8197F) -#define BIT_SET_ARFR1_V1_8197F(x, v) (BIT_CLEAR_ARFR1_V1_8197F(x) | BIT_ARFR1_V1_8197F(v)) - +#define BIT_GET_ARFR1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_ARFR1_V1_8197F) & BIT_MASK_ARFR1_V1_8197F) +#define BIT_SET_ARFR1_V1_8197F(x, v) \ + (BIT_CLEAR_ARFR1_V1_8197F(x) | BIT_ARFR1_V1_8197F(v)) /* 2 REG_CCK_CHECK_8197F */ #define BIT_CHECK_CCK_EN_8197F BIT(7) @@ -6779,34 +8676,50 @@ #define BIT_SHIFT_AMPDU_MAX_TIME_8197F 0 #define BIT_MASK_AMPDU_MAX_TIME_8197F 0xff -#define BIT_AMPDU_MAX_TIME_8197F(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8197F) << BIT_SHIFT_AMPDU_MAX_TIME_8197F) -#define BITS_AMPDU_MAX_TIME_8197F (BIT_MASK_AMPDU_MAX_TIME_8197F << BIT_SHIFT_AMPDU_MAX_TIME_8197F) +#define BIT_AMPDU_MAX_TIME_8197F(x) \ + (((x) & BIT_MASK_AMPDU_MAX_TIME_8197F) \ + << BIT_SHIFT_AMPDU_MAX_TIME_8197F) +#define BITS_AMPDU_MAX_TIME_8197F \ + (BIT_MASK_AMPDU_MAX_TIME_8197F << BIT_SHIFT_AMPDU_MAX_TIME_8197F) #define BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) ((x) & (~BITS_AMPDU_MAX_TIME_8197F)) -#define BIT_GET_AMPDU_MAX_TIME_8197F(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8197F) & BIT_MASK_AMPDU_MAX_TIME_8197F) -#define BIT_SET_AMPDU_MAX_TIME_8197F(x, v) (BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) | BIT_AMPDU_MAX_TIME_8197F(v)) - +#define BIT_GET_AMPDU_MAX_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8197F) & \ + BIT_MASK_AMPDU_MAX_TIME_8197F) +#define BIT_SET_AMPDU_MAX_TIME_8197F(x, v) \ + (BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) | BIT_AMPDU_MAX_TIME_8197F(v)) /* 2 REG_BCNQ1_BDNY_V1_8197F */ #define BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F 0 #define BIT_MASK_BCNQ1_PGBNDY_V1_8197F 0xfff -#define BIT_BCNQ1_PGBNDY_V1_8197F(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8197F) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) -#define BITS_BCNQ1_PGBNDY_V1_8197F (BIT_MASK_BCNQ1_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) +#define BIT_BCNQ1_PGBNDY_V1_8197F(x) \ + (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8197F) \ + << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) +#define BITS_BCNQ1_PGBNDY_V1_8197F \ + (BIT_MASK_BCNQ1_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) #define BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8197F)) -#define BIT_GET_BCNQ1_PGBNDY_V1_8197F(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) & BIT_MASK_BCNQ1_PGBNDY_V1_8197F) -#define BIT_SET_BCNQ1_PGBNDY_V1_8197F(x, v) (BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) | BIT_BCNQ1_PGBNDY_V1_8197F(v)) - +#define BIT_GET_BCNQ1_PGBNDY_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) & \ + BIT_MASK_BCNQ1_PGBNDY_V1_8197F) +#define BIT_SET_BCNQ1_PGBNDY_V1_8197F(x, v) \ + (BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) | BIT_BCNQ1_PGBNDY_V1_8197F(v)) /* 2 REG_AMPDU_MAX_LENGTH_8197F */ #define BIT_SHIFT_AMPDU_MAX_LENGTH_8197F 0 #define BIT_MASK_AMPDU_MAX_LENGTH_8197F 0xffffffffL -#define BIT_AMPDU_MAX_LENGTH_8197F(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8197F) << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) -#define BITS_AMPDU_MAX_LENGTH_8197F (BIT_MASK_AMPDU_MAX_LENGTH_8197F << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) -#define BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_8197F)) -#define BIT_GET_AMPDU_MAX_LENGTH_8197F(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) & BIT_MASK_AMPDU_MAX_LENGTH_8197F) -#define BIT_SET_AMPDU_MAX_LENGTH_8197F(x, v) (BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) | BIT_AMPDU_MAX_LENGTH_8197F(v)) - +#define BIT_AMPDU_MAX_LENGTH_8197F(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8197F) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) +#define BITS_AMPDU_MAX_LENGTH_8197F \ + (BIT_MASK_AMPDU_MAX_LENGTH_8197F << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_8197F)) +#define BIT_GET_AMPDU_MAX_LENGTH_8197F(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) & \ + BIT_MASK_AMPDU_MAX_LENGTH_8197F) +#define BIT_SET_AMPDU_MAX_LENGTH_8197F(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) | BIT_AMPDU_MAX_LENGTH_8197F(v)) /* 2 REG_ACQ_STOP_8197F */ #define BIT_AC7Q_STOP_8197F BIT(7) @@ -6822,12 +8735,17 @@ #define BIT_SHIFT_R_NDPA_RATE_V1_8197F 0 #define BIT_MASK_R_NDPA_RATE_V1_8197F 0xff -#define BIT_R_NDPA_RATE_V1_8197F(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8197F) << BIT_SHIFT_R_NDPA_RATE_V1_8197F) -#define BITS_R_NDPA_RATE_V1_8197F (BIT_MASK_R_NDPA_RATE_V1_8197F << BIT_SHIFT_R_NDPA_RATE_V1_8197F) +#define BIT_R_NDPA_RATE_V1_8197F(x) \ + (((x) & BIT_MASK_R_NDPA_RATE_V1_8197F) \ + << BIT_SHIFT_R_NDPA_RATE_V1_8197F) +#define BITS_R_NDPA_RATE_V1_8197F \ + (BIT_MASK_R_NDPA_RATE_V1_8197F << BIT_SHIFT_R_NDPA_RATE_V1_8197F) #define BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) ((x) & (~BITS_R_NDPA_RATE_V1_8197F)) -#define BIT_GET_R_NDPA_RATE_V1_8197F(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8197F) & BIT_MASK_R_NDPA_RATE_V1_8197F) -#define BIT_SET_R_NDPA_RATE_V1_8197F(x, v) (BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) | BIT_R_NDPA_RATE_V1_8197F(v)) - +#define BIT_GET_R_NDPA_RATE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8197F) & \ + BIT_MASK_R_NDPA_RATE_V1_8197F) +#define BIT_SET_R_NDPA_RATE_V1_8197F(x, v) \ + (BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) | BIT_R_NDPA_RATE_V1_8197F(v)) /* 2 REG_TX_HANG_CTRL_8197F */ #define BIT_R_EN_GNT_BT_AWAKE_8197F BIT(3) @@ -6840,22 +8758,29 @@ #define BIT_SHIFT_BW_SIGTA_8197F 3 #define BIT_MASK_BW_SIGTA_8197F 0x3 -#define BIT_BW_SIGTA_8197F(x) (((x) & BIT_MASK_BW_SIGTA_8197F) << BIT_SHIFT_BW_SIGTA_8197F) -#define BITS_BW_SIGTA_8197F (BIT_MASK_BW_SIGTA_8197F << BIT_SHIFT_BW_SIGTA_8197F) +#define BIT_BW_SIGTA_8197F(x) \ + (((x) & BIT_MASK_BW_SIGTA_8197F) << BIT_SHIFT_BW_SIGTA_8197F) +#define BITS_BW_SIGTA_8197F \ + (BIT_MASK_BW_SIGTA_8197F << BIT_SHIFT_BW_SIGTA_8197F) #define BIT_CLEAR_BW_SIGTA_8197F(x) ((x) & (~BITS_BW_SIGTA_8197F)) -#define BIT_GET_BW_SIGTA_8197F(x) (((x) >> BIT_SHIFT_BW_SIGTA_8197F) & BIT_MASK_BW_SIGTA_8197F) -#define BIT_SET_BW_SIGTA_8197F(x, v) (BIT_CLEAR_BW_SIGTA_8197F(x) | BIT_BW_SIGTA_8197F(v)) +#define BIT_GET_BW_SIGTA_8197F(x) \ + (((x) >> BIT_SHIFT_BW_SIGTA_8197F) & BIT_MASK_BW_SIGTA_8197F) +#define BIT_SET_BW_SIGTA_8197F(x, v) \ + (BIT_CLEAR_BW_SIGTA_8197F(x) | BIT_BW_SIGTA_8197F(v)) #define BIT_EN_BAR_SIGTA_8197F BIT(2) #define BIT_SHIFT_R_NDPA_BW_8197F 0 #define BIT_MASK_R_NDPA_BW_8197F 0x3 -#define BIT_R_NDPA_BW_8197F(x) (((x) & BIT_MASK_R_NDPA_BW_8197F) << BIT_SHIFT_R_NDPA_BW_8197F) -#define BITS_R_NDPA_BW_8197F (BIT_MASK_R_NDPA_BW_8197F << BIT_SHIFT_R_NDPA_BW_8197F) +#define BIT_R_NDPA_BW_8197F(x) \ + (((x) & BIT_MASK_R_NDPA_BW_8197F) << BIT_SHIFT_R_NDPA_BW_8197F) +#define BITS_R_NDPA_BW_8197F \ + (BIT_MASK_R_NDPA_BW_8197F << BIT_SHIFT_R_NDPA_BW_8197F) #define BIT_CLEAR_R_NDPA_BW_8197F(x) ((x) & (~BITS_R_NDPA_BW_8197F)) -#define BIT_GET_R_NDPA_BW_8197F(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8197F) & BIT_MASK_R_NDPA_BW_8197F) -#define BIT_SET_R_NDPA_BW_8197F(x, v) (BIT_CLEAR_R_NDPA_BW_8197F(x) | BIT_R_NDPA_BW_8197F(v)) - +#define BIT_GET_R_NDPA_BW_8197F(x) \ + (((x) >> BIT_SHIFT_R_NDPA_BW_8197F) & BIT_MASK_R_NDPA_BW_8197F) +#define BIT_SET_R_NDPA_BW_8197F(x, v) \ + (BIT_CLEAR_R_NDPA_BW_8197F(x) | BIT_R_NDPA_BW_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -6865,258 +8790,389 @@ #define BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F 0 #define BIT_MASK_RD_RESP_PKT_TH_V1_8197F 0x3f -#define BIT_RD_RESP_PKT_TH_V1_8197F(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8197F) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) -#define BITS_RD_RESP_PKT_TH_V1_8197F (BIT_MASK_RD_RESP_PKT_TH_V1_8197F << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) -#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) ((x) & (~BITS_RD_RESP_PKT_TH_V1_8197F)) -#define BIT_GET_RD_RESP_PKT_TH_V1_8197F(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) & BIT_MASK_RD_RESP_PKT_TH_V1_8197F) -#define BIT_SET_RD_RESP_PKT_TH_V1_8197F(x, v) (BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) | BIT_RD_RESP_PKT_TH_V1_8197F(v)) - +#define BIT_RD_RESP_PKT_TH_V1_8197F(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8197F) \ + << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) +#define BITS_RD_RESP_PKT_TH_V1_8197F \ + (BIT_MASK_RD_RESP_PKT_TH_V1_8197F << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) \ + ((x) & (~BITS_RD_RESP_PKT_TH_V1_8197F)) +#define BIT_GET_RD_RESP_PKT_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) & \ + BIT_MASK_RD_RESP_PKT_TH_V1_8197F) +#define BIT_SET_RD_RESP_PKT_TH_V1_8197F(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) | BIT_RD_RESP_PKT_TH_V1_8197F(v)) /* 2 REG_CMDQ_INFO_8197F */ #define BIT_SHIFT_PKT_NUM_8197F 23 #define BIT_MASK_PKT_NUM_8197F 0x1ff -#define BIT_PKT_NUM_8197F(x) (((x) & BIT_MASK_PKT_NUM_8197F) << BIT_SHIFT_PKT_NUM_8197F) +#define BIT_PKT_NUM_8197F(x) \ + (((x) & BIT_MASK_PKT_NUM_8197F) << BIT_SHIFT_PKT_NUM_8197F) #define BITS_PKT_NUM_8197F (BIT_MASK_PKT_NUM_8197F << BIT_SHIFT_PKT_NUM_8197F) #define BIT_CLEAR_PKT_NUM_8197F(x) ((x) & (~BITS_PKT_NUM_8197F)) -#define BIT_GET_PKT_NUM_8197F(x) (((x) >> BIT_SHIFT_PKT_NUM_8197F) & BIT_MASK_PKT_NUM_8197F) -#define BIT_SET_PKT_NUM_8197F(x, v) (BIT_CLEAR_PKT_NUM_8197F(x) | BIT_PKT_NUM_8197F(v)) +#define BIT_GET_PKT_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_8197F) & BIT_MASK_PKT_NUM_8197F) +#define BIT_SET_PKT_NUM_8197F(x, v) \ + (BIT_CLEAR_PKT_NUM_8197F(x) | BIT_PKT_NUM_8197F(v)) #define BIT_TIDEMPTY_CMDQ_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F 11 #define BIT_MASK_TAIL_PKT_CMDQ_V2_8197F 0x7ff -#define BIT_TAIL_PKT_CMDQ_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8197F) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) -#define BITS_TAIL_PKT_CMDQ_V2_8197F (BIT_MASK_TAIL_PKT_CMDQ_V2_8197F << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) -#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_CMDQ_V2_8197F)) -#define BIT_GET_TAIL_PKT_CMDQ_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) & BIT_MASK_TAIL_PKT_CMDQ_V2_8197F) -#define BIT_SET_TAIL_PKT_CMDQ_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) | BIT_TAIL_PKT_CMDQ_V2_8197F(v)) - +#define BIT_TAIL_PKT_CMDQ_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) +#define BITS_TAIL_PKT_CMDQ_V2_8197F \ + (BIT_MASK_TAIL_PKT_CMDQ_V2_8197F << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) \ + ((x) & (~BITS_TAIL_PKT_CMDQ_V2_8197F)) +#define BIT_GET_TAIL_PKT_CMDQ_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) & \ + BIT_MASK_TAIL_PKT_CMDQ_V2_8197F) +#define BIT_SET_TAIL_PKT_CMDQ_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) | BIT_TAIL_PKT_CMDQ_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F 0 #define BIT_MASK_HEAD_PKT_CMDQ_V1_8197F 0x7ff -#define BIT_HEAD_PKT_CMDQ_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8197F) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) -#define BITS_HEAD_PKT_CMDQ_V1_8197F (BIT_MASK_HEAD_PKT_CMDQ_V1_8197F << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) -#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8197F)) -#define BIT_GET_HEAD_PKT_CMDQ_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) & BIT_MASK_HEAD_PKT_CMDQ_V1_8197F) -#define BIT_SET_HEAD_PKT_CMDQ_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) | BIT_HEAD_PKT_CMDQ_V1_8197F(v)) - +#define BIT_HEAD_PKT_CMDQ_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) +#define BITS_HEAD_PKT_CMDQ_V1_8197F \ + (BIT_MASK_HEAD_PKT_CMDQ_V1_8197F << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) \ + ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8197F)) +#define BIT_GET_HEAD_PKT_CMDQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) & \ + BIT_MASK_HEAD_PKT_CMDQ_V1_8197F) +#define BIT_SET_HEAD_PKT_CMDQ_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) | BIT_HEAD_PKT_CMDQ_V1_8197F(v)) /* 2 REG_Q4_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q4_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q4_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q4_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) -#define BITS_QUEUEMACID_Q4_V1_8197F (BIT_MASK_QUEUEMACID_Q4_V1_8197F << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q4_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q4_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) & BIT_MASK_QUEUEMACID_Q4_V1_8197F) -#define BIT_SET_QUEUEMACID_Q4_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) | BIT_QUEUEMACID_Q4_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q4_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) +#define BITS_QUEUEMACID_Q4_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q4_V1_8197F << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q4_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q4_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q4_V1_8197F) +#define BIT_SET_QUEUEMACID_Q4_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) | BIT_QUEUEMACID_Q4_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q4_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q4_V1_8197F 0x3 -#define BIT_QUEUEAC_Q4_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8197F) << BIT_SHIFT_QUEUEAC_Q4_V1_8197F) -#define BITS_QUEUEAC_Q4_V1_8197F (BIT_MASK_QUEUEAC_Q4_V1_8197F << BIT_SHIFT_QUEUEAC_Q4_V1_8197F) +#define BIT_QUEUEAC_Q4_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q4_V1_8197F) << BIT_SHIFT_QUEUEAC_Q4_V1_8197F) +#define BITS_QUEUEAC_Q4_V1_8197F \ + (BIT_MASK_QUEUEAC_Q4_V1_8197F << BIT_SHIFT_QUEUEAC_Q4_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8197F)) -#define BIT_GET_QUEUEAC_Q4_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8197F) & BIT_MASK_QUEUEAC_Q4_V1_8197F) -#define BIT_SET_QUEUEAC_Q4_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) | BIT_QUEUEAC_Q4_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q4_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8197F) & BIT_MASK_QUEUEAC_Q4_V1_8197F) +#define BIT_SET_QUEUEAC_Q4_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) | BIT_QUEUEAC_Q4_V1_8197F(v)) #define BIT_TIDEMPTY_Q4_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q4_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q4_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q4_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) -#define BITS_TAIL_PKT_Q4_V2_8197F (BIT_MASK_TAIL_PKT_Q4_V2_8197F << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) +#define BIT_TAIL_PKT_Q4_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) +#define BITS_TAIL_PKT_Q4_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q4_V2_8197F << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q4_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) & BIT_MASK_TAIL_PKT_Q4_V2_8197F) -#define BIT_SET_TAIL_PKT_Q4_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) | BIT_TAIL_PKT_Q4_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q4_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q4_V2_8197F) +#define BIT_SET_TAIL_PKT_Q4_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) | BIT_TAIL_PKT_Q4_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q4_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q4_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q4_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) -#define BITS_HEAD_PKT_Q4_V1_8197F (BIT_MASK_HEAD_PKT_Q4_V1_8197F << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) +#define BIT_HEAD_PKT_Q4_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) +#define BITS_HEAD_PKT_Q4_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q4_V1_8197F << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q4_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) & BIT_MASK_HEAD_PKT_Q4_V1_8197F) -#define BIT_SET_HEAD_PKT_Q4_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) | BIT_HEAD_PKT_Q4_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q4_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q4_V1_8197F) +#define BIT_SET_HEAD_PKT_Q4_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) | BIT_HEAD_PKT_Q4_V1_8197F(v)) /* 2 REG_Q5_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q5_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q5_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q5_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) -#define BITS_QUEUEMACID_Q5_V1_8197F (BIT_MASK_QUEUEMACID_Q5_V1_8197F << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q5_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q5_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) & BIT_MASK_QUEUEMACID_Q5_V1_8197F) -#define BIT_SET_QUEUEMACID_Q5_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) | BIT_QUEUEMACID_Q5_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q5_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) +#define BITS_QUEUEMACID_Q5_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q5_V1_8197F << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q5_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q5_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q5_V1_8197F) +#define BIT_SET_QUEUEMACID_Q5_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) | BIT_QUEUEMACID_Q5_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q5_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q5_V1_8197F 0x3 -#define BIT_QUEUEAC_Q5_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8197F) << BIT_SHIFT_QUEUEAC_Q5_V1_8197F) -#define BITS_QUEUEAC_Q5_V1_8197F (BIT_MASK_QUEUEAC_Q5_V1_8197F << BIT_SHIFT_QUEUEAC_Q5_V1_8197F) +#define BIT_QUEUEAC_Q5_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q5_V1_8197F) << BIT_SHIFT_QUEUEAC_Q5_V1_8197F) +#define BITS_QUEUEAC_Q5_V1_8197F \ + (BIT_MASK_QUEUEAC_Q5_V1_8197F << BIT_SHIFT_QUEUEAC_Q5_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8197F)) -#define BIT_GET_QUEUEAC_Q5_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8197F) & BIT_MASK_QUEUEAC_Q5_V1_8197F) -#define BIT_SET_QUEUEAC_Q5_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) | BIT_QUEUEAC_Q5_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q5_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8197F) & BIT_MASK_QUEUEAC_Q5_V1_8197F) +#define BIT_SET_QUEUEAC_Q5_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) | BIT_QUEUEAC_Q5_V1_8197F(v)) #define BIT_TIDEMPTY_Q5_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q5_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q5_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q5_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) -#define BITS_TAIL_PKT_Q5_V2_8197F (BIT_MASK_TAIL_PKT_Q5_V2_8197F << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) +#define BIT_TAIL_PKT_Q5_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) +#define BITS_TAIL_PKT_Q5_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q5_V2_8197F << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q5_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) & BIT_MASK_TAIL_PKT_Q5_V2_8197F) -#define BIT_SET_TAIL_PKT_Q5_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) | BIT_TAIL_PKT_Q5_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q5_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q5_V2_8197F) +#define BIT_SET_TAIL_PKT_Q5_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) | BIT_TAIL_PKT_Q5_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q5_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q5_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q5_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) -#define BITS_HEAD_PKT_Q5_V1_8197F (BIT_MASK_HEAD_PKT_Q5_V1_8197F << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) +#define BIT_HEAD_PKT_Q5_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) +#define BITS_HEAD_PKT_Q5_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q5_V1_8197F << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q5_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) & BIT_MASK_HEAD_PKT_Q5_V1_8197F) -#define BIT_SET_HEAD_PKT_Q5_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) | BIT_HEAD_PKT_Q5_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q5_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q5_V1_8197F) +#define BIT_SET_HEAD_PKT_Q5_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) | BIT_HEAD_PKT_Q5_V1_8197F(v)) /* 2 REG_Q6_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q6_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q6_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q6_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) -#define BITS_QUEUEMACID_Q6_V1_8197F (BIT_MASK_QUEUEMACID_Q6_V1_8197F << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q6_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q6_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) & BIT_MASK_QUEUEMACID_Q6_V1_8197F) -#define BIT_SET_QUEUEMACID_Q6_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) | BIT_QUEUEMACID_Q6_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q6_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) +#define BITS_QUEUEMACID_Q6_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q6_V1_8197F << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q6_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q6_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q6_V1_8197F) +#define BIT_SET_QUEUEMACID_Q6_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) | BIT_QUEUEMACID_Q6_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q6_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q6_V1_8197F 0x3 -#define BIT_QUEUEAC_Q6_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8197F) << BIT_SHIFT_QUEUEAC_Q6_V1_8197F) -#define BITS_QUEUEAC_Q6_V1_8197F (BIT_MASK_QUEUEAC_Q6_V1_8197F << BIT_SHIFT_QUEUEAC_Q6_V1_8197F) +#define BIT_QUEUEAC_Q6_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q6_V1_8197F) << BIT_SHIFT_QUEUEAC_Q6_V1_8197F) +#define BITS_QUEUEAC_Q6_V1_8197F \ + (BIT_MASK_QUEUEAC_Q6_V1_8197F << BIT_SHIFT_QUEUEAC_Q6_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8197F)) -#define BIT_GET_QUEUEAC_Q6_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8197F) & BIT_MASK_QUEUEAC_Q6_V1_8197F) -#define BIT_SET_QUEUEAC_Q6_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) | BIT_QUEUEAC_Q6_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q6_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8197F) & BIT_MASK_QUEUEAC_Q6_V1_8197F) +#define BIT_SET_QUEUEAC_Q6_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) | BIT_QUEUEAC_Q6_V1_8197F(v)) #define BIT_TIDEMPTY_Q6_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q6_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q6_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q6_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) -#define BITS_TAIL_PKT_Q6_V2_8197F (BIT_MASK_TAIL_PKT_Q6_V2_8197F << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) +#define BIT_TAIL_PKT_Q6_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) +#define BITS_TAIL_PKT_Q6_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q6_V2_8197F << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q6_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) & BIT_MASK_TAIL_PKT_Q6_V2_8197F) -#define BIT_SET_TAIL_PKT_Q6_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) | BIT_TAIL_PKT_Q6_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q6_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q6_V2_8197F) +#define BIT_SET_TAIL_PKT_Q6_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) | BIT_TAIL_PKT_Q6_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q6_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q6_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q6_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) -#define BITS_HEAD_PKT_Q6_V1_8197F (BIT_MASK_HEAD_PKT_Q6_V1_8197F << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) +#define BIT_HEAD_PKT_Q6_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) +#define BITS_HEAD_PKT_Q6_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q6_V1_8197F << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q6_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) & BIT_MASK_HEAD_PKT_Q6_V1_8197F) -#define BIT_SET_HEAD_PKT_Q6_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) | BIT_HEAD_PKT_Q6_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q6_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q6_V1_8197F) +#define BIT_SET_HEAD_PKT_Q6_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) | BIT_HEAD_PKT_Q6_V1_8197F(v)) /* 2 REG_Q7_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q7_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q7_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q7_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) -#define BITS_QUEUEMACID_Q7_V1_8197F (BIT_MASK_QUEUEMACID_Q7_V1_8197F << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q7_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q7_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) & BIT_MASK_QUEUEMACID_Q7_V1_8197F) -#define BIT_SET_QUEUEMACID_Q7_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) | BIT_QUEUEMACID_Q7_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q7_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) +#define BITS_QUEUEMACID_Q7_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q7_V1_8197F << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q7_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q7_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q7_V1_8197F) +#define BIT_SET_QUEUEMACID_Q7_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) | BIT_QUEUEMACID_Q7_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q7_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q7_V1_8197F 0x3 -#define BIT_QUEUEAC_Q7_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8197F) << BIT_SHIFT_QUEUEAC_Q7_V1_8197F) -#define BITS_QUEUEAC_Q7_V1_8197F (BIT_MASK_QUEUEAC_Q7_V1_8197F << BIT_SHIFT_QUEUEAC_Q7_V1_8197F) +#define BIT_QUEUEAC_Q7_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q7_V1_8197F) << BIT_SHIFT_QUEUEAC_Q7_V1_8197F) +#define BITS_QUEUEAC_Q7_V1_8197F \ + (BIT_MASK_QUEUEAC_Q7_V1_8197F << BIT_SHIFT_QUEUEAC_Q7_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8197F)) -#define BIT_GET_QUEUEAC_Q7_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8197F) & BIT_MASK_QUEUEAC_Q7_V1_8197F) -#define BIT_SET_QUEUEAC_Q7_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) | BIT_QUEUEAC_Q7_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q7_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8197F) & BIT_MASK_QUEUEAC_Q7_V1_8197F) +#define BIT_SET_QUEUEAC_Q7_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) | BIT_QUEUEAC_Q7_V1_8197F(v)) #define BIT_TIDEMPTY_Q7_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q7_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q7_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q7_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) -#define BITS_TAIL_PKT_Q7_V2_8197F (BIT_MASK_TAIL_PKT_Q7_V2_8197F << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) +#define BIT_TAIL_PKT_Q7_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) +#define BITS_TAIL_PKT_Q7_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q7_V2_8197F << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q7_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) & BIT_MASK_TAIL_PKT_Q7_V2_8197F) -#define BIT_SET_TAIL_PKT_Q7_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) | BIT_TAIL_PKT_Q7_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q7_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q7_V2_8197F) +#define BIT_SET_TAIL_PKT_Q7_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) | BIT_TAIL_PKT_Q7_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q7_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q7_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q7_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) -#define BITS_HEAD_PKT_Q7_V1_8197F (BIT_MASK_HEAD_PKT_Q7_V1_8197F << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) +#define BIT_HEAD_PKT_Q7_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) +#define BITS_HEAD_PKT_Q7_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q7_V1_8197F << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q7_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) & BIT_MASK_HEAD_PKT_Q7_V1_8197F) -#define BIT_SET_HEAD_PKT_Q7_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) | BIT_HEAD_PKT_Q7_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q7_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q7_V1_8197F) +#define BIT_SET_HEAD_PKT_Q7_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) | BIT_HEAD_PKT_Q7_V1_8197F(v)) /* 2 REG_WMAC_LBK_BUF_HD_V1_8197F */ #define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F 0 #define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F 0xfff -#define BIT_WMAC_LBK_BUF_HEAD_V1_8197F(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) -#define BITS_WMAC_LBK_BUF_HEAD_V1_8197F (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) -#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8197F)) -#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8197F(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F) -#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8197F(x, v) (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) | BIT_WMAC_LBK_BUF_HEAD_V1_8197F(v)) - +#define BIT_WMAC_LBK_BUF_HEAD_V1_8197F(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F) \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) +#define BITS_WMAC_LBK_BUF_HEAD_V1_8197F \ + (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) \ + ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8197F)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) & \ + BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8197F(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) | \ + BIT_WMAC_LBK_BUF_HEAD_V1_8197F(v)) /* 2 REG_MGQ_BDNY_V1_8197F */ #define BIT_SHIFT_MGQ_PGBNDY_V1_8197F 0 #define BIT_MASK_MGQ_PGBNDY_V1_8197F 0xfff -#define BIT_MGQ_PGBNDY_V1_8197F(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8197F) << BIT_SHIFT_MGQ_PGBNDY_V1_8197F) -#define BITS_MGQ_PGBNDY_V1_8197F (BIT_MASK_MGQ_PGBNDY_V1_8197F << BIT_SHIFT_MGQ_PGBNDY_V1_8197F) +#define BIT_MGQ_PGBNDY_V1_8197F(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V1_8197F) << BIT_SHIFT_MGQ_PGBNDY_V1_8197F) +#define BITS_MGQ_PGBNDY_V1_8197F \ + (BIT_MASK_MGQ_PGBNDY_V1_8197F << BIT_SHIFT_MGQ_PGBNDY_V1_8197F) #define BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8197F)) -#define BIT_GET_MGQ_PGBNDY_V1_8197F(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8197F) & BIT_MASK_MGQ_PGBNDY_V1_8197F) -#define BIT_SET_MGQ_PGBNDY_V1_8197F(x, v) (BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) | BIT_MGQ_PGBNDY_V1_8197F(v)) - +#define BIT_GET_MGQ_PGBNDY_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8197F) & BIT_MASK_MGQ_PGBNDY_V1_8197F) +#define BIT_SET_MGQ_PGBNDY_V1_8197F(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) | BIT_MGQ_PGBNDY_V1_8197F(v)) /* 2 REG_TXRPT_CTRL_8197F */ #define BIT_SHIFT_TRXRPT_TIMER_TH_8197F 24 #define BIT_MASK_TRXRPT_TIMER_TH_8197F 0xff -#define BIT_TRXRPT_TIMER_TH_8197F(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8197F) << BIT_SHIFT_TRXRPT_TIMER_TH_8197F) -#define BITS_TRXRPT_TIMER_TH_8197F (BIT_MASK_TRXRPT_TIMER_TH_8197F << BIT_SHIFT_TRXRPT_TIMER_TH_8197F) +#define BIT_TRXRPT_TIMER_TH_8197F(x) \ + (((x) & BIT_MASK_TRXRPT_TIMER_TH_8197F) \ + << BIT_SHIFT_TRXRPT_TIMER_TH_8197F) +#define BITS_TRXRPT_TIMER_TH_8197F \ + (BIT_MASK_TRXRPT_TIMER_TH_8197F << BIT_SHIFT_TRXRPT_TIMER_TH_8197F) #define BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8197F)) -#define BIT_GET_TRXRPT_TIMER_TH_8197F(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8197F) & BIT_MASK_TRXRPT_TIMER_TH_8197F) -#define BIT_SET_TRXRPT_TIMER_TH_8197F(x, v) (BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) | BIT_TRXRPT_TIMER_TH_8197F(v)) - +#define BIT_GET_TRXRPT_TIMER_TH_8197F(x) \ + (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8197F) & \ + BIT_MASK_TRXRPT_TIMER_TH_8197F) +#define BIT_SET_TRXRPT_TIMER_TH_8197F(x, v) \ + (BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) | BIT_TRXRPT_TIMER_TH_8197F(v)) #define BIT_SHIFT_TRXRPT_LEN_TH_8197F 16 #define BIT_MASK_TRXRPT_LEN_TH_8197F 0xff -#define BIT_TRXRPT_LEN_TH_8197F(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8197F) << BIT_SHIFT_TRXRPT_LEN_TH_8197F) -#define BITS_TRXRPT_LEN_TH_8197F (BIT_MASK_TRXRPT_LEN_TH_8197F << BIT_SHIFT_TRXRPT_LEN_TH_8197F) +#define BIT_TRXRPT_LEN_TH_8197F(x) \ + (((x) & BIT_MASK_TRXRPT_LEN_TH_8197F) << BIT_SHIFT_TRXRPT_LEN_TH_8197F) +#define BITS_TRXRPT_LEN_TH_8197F \ + (BIT_MASK_TRXRPT_LEN_TH_8197F << BIT_SHIFT_TRXRPT_LEN_TH_8197F) #define BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) ((x) & (~BITS_TRXRPT_LEN_TH_8197F)) -#define BIT_GET_TRXRPT_LEN_TH_8197F(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8197F) & BIT_MASK_TRXRPT_LEN_TH_8197F) -#define BIT_SET_TRXRPT_LEN_TH_8197F(x, v) (BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) | BIT_TRXRPT_LEN_TH_8197F(v)) - +#define BIT_GET_TRXRPT_LEN_TH_8197F(x) \ + (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8197F) & BIT_MASK_TRXRPT_LEN_TH_8197F) +#define BIT_SET_TRXRPT_LEN_TH_8197F(x, v) \ + (BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) | BIT_TRXRPT_LEN_TH_8197F(v)) #define BIT_SHIFT_TRXRPT_READ_PTR_8197F 8 #define BIT_MASK_TRXRPT_READ_PTR_8197F 0xff -#define BIT_TRXRPT_READ_PTR_8197F(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8197F) << BIT_SHIFT_TRXRPT_READ_PTR_8197F) -#define BITS_TRXRPT_READ_PTR_8197F (BIT_MASK_TRXRPT_READ_PTR_8197F << BIT_SHIFT_TRXRPT_READ_PTR_8197F) +#define BIT_TRXRPT_READ_PTR_8197F(x) \ + (((x) & BIT_MASK_TRXRPT_READ_PTR_8197F) \ + << BIT_SHIFT_TRXRPT_READ_PTR_8197F) +#define BITS_TRXRPT_READ_PTR_8197F \ + (BIT_MASK_TRXRPT_READ_PTR_8197F << BIT_SHIFT_TRXRPT_READ_PTR_8197F) #define BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) ((x) & (~BITS_TRXRPT_READ_PTR_8197F)) -#define BIT_GET_TRXRPT_READ_PTR_8197F(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8197F) & BIT_MASK_TRXRPT_READ_PTR_8197F) -#define BIT_SET_TRXRPT_READ_PTR_8197F(x, v) (BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) | BIT_TRXRPT_READ_PTR_8197F(v)) - +#define BIT_GET_TRXRPT_READ_PTR_8197F(x) \ + (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8197F) & \ + BIT_MASK_TRXRPT_READ_PTR_8197F) +#define BIT_SET_TRXRPT_READ_PTR_8197F(x, v) \ + (BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) | BIT_TRXRPT_READ_PTR_8197F(v)) #define BIT_SHIFT_TRXRPT_WRITE_PTR_8197F 0 #define BIT_MASK_TRXRPT_WRITE_PTR_8197F 0xff -#define BIT_TRXRPT_WRITE_PTR_8197F(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8197F) << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) -#define BITS_TRXRPT_WRITE_PTR_8197F (BIT_MASK_TRXRPT_WRITE_PTR_8197F << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) -#define BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) ((x) & (~BITS_TRXRPT_WRITE_PTR_8197F)) -#define BIT_GET_TRXRPT_WRITE_PTR_8197F(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) & BIT_MASK_TRXRPT_WRITE_PTR_8197F) -#define BIT_SET_TRXRPT_WRITE_PTR_8197F(x, v) (BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) | BIT_TRXRPT_WRITE_PTR_8197F(v)) - +#define BIT_TRXRPT_WRITE_PTR_8197F(x) \ + (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8197F) \ + << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) +#define BITS_TRXRPT_WRITE_PTR_8197F \ + (BIT_MASK_TRXRPT_WRITE_PTR_8197F << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) +#define BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) \ + ((x) & (~BITS_TRXRPT_WRITE_PTR_8197F)) +#define BIT_GET_TRXRPT_WRITE_PTR_8197F(x) \ + (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) & \ + BIT_MASK_TRXRPT_WRITE_PTR_8197F) +#define BIT_SET_TRXRPT_WRITE_PTR_8197F(x, v) \ + (BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) | BIT_TRXRPT_WRITE_PTR_8197F(v)) /* 2 REG_INIRTS_RATE_SEL_8197F */ #define BIT_LEAG_RTS_BW_DUP_8197F BIT(5) @@ -7125,109 +9181,152 @@ #define BIT_SHIFT_BASIC_CFEND_RATE_8197F 0 #define BIT_MASK_BASIC_CFEND_RATE_8197F 0x1f -#define BIT_BASIC_CFEND_RATE_8197F(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8197F) << BIT_SHIFT_BASIC_CFEND_RATE_8197F) -#define BITS_BASIC_CFEND_RATE_8197F (BIT_MASK_BASIC_CFEND_RATE_8197F << BIT_SHIFT_BASIC_CFEND_RATE_8197F) -#define BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) ((x) & (~BITS_BASIC_CFEND_RATE_8197F)) -#define BIT_GET_BASIC_CFEND_RATE_8197F(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8197F) & BIT_MASK_BASIC_CFEND_RATE_8197F) -#define BIT_SET_BASIC_CFEND_RATE_8197F(x, v) (BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) | BIT_BASIC_CFEND_RATE_8197F(v)) - +#define BIT_BASIC_CFEND_RATE_8197F(x) \ + (((x) & BIT_MASK_BASIC_CFEND_RATE_8197F) \ + << BIT_SHIFT_BASIC_CFEND_RATE_8197F) +#define BITS_BASIC_CFEND_RATE_8197F \ + (BIT_MASK_BASIC_CFEND_RATE_8197F << BIT_SHIFT_BASIC_CFEND_RATE_8197F) +#define BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) \ + ((x) & (~BITS_BASIC_CFEND_RATE_8197F)) +#define BIT_GET_BASIC_CFEND_RATE_8197F(x) \ + (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8197F) & \ + BIT_MASK_BASIC_CFEND_RATE_8197F) +#define BIT_SET_BASIC_CFEND_RATE_8197F(x, v) \ + (BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) | BIT_BASIC_CFEND_RATE_8197F(v)) /* 2 REG_STBC_CFEND_RATE_8197F */ #define BIT_SHIFT_STBC_CFEND_RATE_8197F 0 #define BIT_MASK_STBC_CFEND_RATE_8197F 0x1f -#define BIT_STBC_CFEND_RATE_8197F(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8197F) << BIT_SHIFT_STBC_CFEND_RATE_8197F) -#define BITS_STBC_CFEND_RATE_8197F (BIT_MASK_STBC_CFEND_RATE_8197F << BIT_SHIFT_STBC_CFEND_RATE_8197F) +#define BIT_STBC_CFEND_RATE_8197F(x) \ + (((x) & BIT_MASK_STBC_CFEND_RATE_8197F) \ + << BIT_SHIFT_STBC_CFEND_RATE_8197F) +#define BITS_STBC_CFEND_RATE_8197F \ + (BIT_MASK_STBC_CFEND_RATE_8197F << BIT_SHIFT_STBC_CFEND_RATE_8197F) #define BIT_CLEAR_STBC_CFEND_RATE_8197F(x) ((x) & (~BITS_STBC_CFEND_RATE_8197F)) -#define BIT_GET_STBC_CFEND_RATE_8197F(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8197F) & BIT_MASK_STBC_CFEND_RATE_8197F) -#define BIT_SET_STBC_CFEND_RATE_8197F(x, v) (BIT_CLEAR_STBC_CFEND_RATE_8197F(x) | BIT_STBC_CFEND_RATE_8197F(v)) - +#define BIT_GET_STBC_CFEND_RATE_8197F(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8197F) & \ + BIT_MASK_STBC_CFEND_RATE_8197F) +#define BIT_SET_STBC_CFEND_RATE_8197F(x, v) \ + (BIT_CLEAR_STBC_CFEND_RATE_8197F(x) | BIT_STBC_CFEND_RATE_8197F(v)) /* 2 REG_DATA_SC_8197F */ #define BIT_SHIFT_TXSC_40M_8197F 4 #define BIT_MASK_TXSC_40M_8197F 0xf -#define BIT_TXSC_40M_8197F(x) (((x) & BIT_MASK_TXSC_40M_8197F) << BIT_SHIFT_TXSC_40M_8197F) -#define BITS_TXSC_40M_8197F (BIT_MASK_TXSC_40M_8197F << BIT_SHIFT_TXSC_40M_8197F) +#define BIT_TXSC_40M_8197F(x) \ + (((x) & BIT_MASK_TXSC_40M_8197F) << BIT_SHIFT_TXSC_40M_8197F) +#define BITS_TXSC_40M_8197F \ + (BIT_MASK_TXSC_40M_8197F << BIT_SHIFT_TXSC_40M_8197F) #define BIT_CLEAR_TXSC_40M_8197F(x) ((x) & (~BITS_TXSC_40M_8197F)) -#define BIT_GET_TXSC_40M_8197F(x) (((x) >> BIT_SHIFT_TXSC_40M_8197F) & BIT_MASK_TXSC_40M_8197F) -#define BIT_SET_TXSC_40M_8197F(x, v) (BIT_CLEAR_TXSC_40M_8197F(x) | BIT_TXSC_40M_8197F(v)) - +#define BIT_GET_TXSC_40M_8197F(x) \ + (((x) >> BIT_SHIFT_TXSC_40M_8197F) & BIT_MASK_TXSC_40M_8197F) +#define BIT_SET_TXSC_40M_8197F(x, v) \ + (BIT_CLEAR_TXSC_40M_8197F(x) | BIT_TXSC_40M_8197F(v)) #define BIT_SHIFT_TXSC_20M_8197F 0 #define BIT_MASK_TXSC_20M_8197F 0xf -#define BIT_TXSC_20M_8197F(x) (((x) & BIT_MASK_TXSC_20M_8197F) << BIT_SHIFT_TXSC_20M_8197F) -#define BITS_TXSC_20M_8197F (BIT_MASK_TXSC_20M_8197F << BIT_SHIFT_TXSC_20M_8197F) +#define BIT_TXSC_20M_8197F(x) \ + (((x) & BIT_MASK_TXSC_20M_8197F) << BIT_SHIFT_TXSC_20M_8197F) +#define BITS_TXSC_20M_8197F \ + (BIT_MASK_TXSC_20M_8197F << BIT_SHIFT_TXSC_20M_8197F) #define BIT_CLEAR_TXSC_20M_8197F(x) ((x) & (~BITS_TXSC_20M_8197F)) -#define BIT_GET_TXSC_20M_8197F(x) (((x) >> BIT_SHIFT_TXSC_20M_8197F) & BIT_MASK_TXSC_20M_8197F) -#define BIT_SET_TXSC_20M_8197F(x, v) (BIT_CLEAR_TXSC_20M_8197F(x) | BIT_TXSC_20M_8197F(v)) - +#define BIT_GET_TXSC_20M_8197F(x) \ + (((x) >> BIT_SHIFT_TXSC_20M_8197F) & BIT_MASK_TXSC_20M_8197F) +#define BIT_SET_TXSC_20M_8197F(x, v) \ + (BIT_CLEAR_TXSC_20M_8197F(x) | BIT_TXSC_20M_8197F(v)) /* 2 REG_MACID_SLEEP3_8197F */ #define BIT_SHIFT_MACID127_96_PKTSLEEP_8197F 0 #define BIT_MASK_MACID127_96_PKTSLEEP_8197F 0xffffffffL -#define BIT_MACID127_96_PKTSLEEP_8197F(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8197F) << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) -#define BITS_MACID127_96_PKTSLEEP_8197F (BIT_MASK_MACID127_96_PKTSLEEP_8197F << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) -#define BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) ((x) & (~BITS_MACID127_96_PKTSLEEP_8197F)) -#define BIT_GET_MACID127_96_PKTSLEEP_8197F(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) & BIT_MASK_MACID127_96_PKTSLEEP_8197F) -#define BIT_SET_MACID127_96_PKTSLEEP_8197F(x, v) (BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) | BIT_MACID127_96_PKTSLEEP_8197F(v)) - +#define BIT_MACID127_96_PKTSLEEP_8197F(x) \ + (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8197F) \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) +#define BITS_MACID127_96_PKTSLEEP_8197F \ + (BIT_MASK_MACID127_96_PKTSLEEP_8197F \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) +#define BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) \ + ((x) & (~BITS_MACID127_96_PKTSLEEP_8197F)) +#define BIT_GET_MACID127_96_PKTSLEEP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) & \ + BIT_MASK_MACID127_96_PKTSLEEP_8197F) +#define BIT_SET_MACID127_96_PKTSLEEP_8197F(x, v) \ + (BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) | \ + BIT_MACID127_96_PKTSLEEP_8197F(v)) /* 2 REG_MACID_SLEEP1_8197F */ #define BIT_SHIFT_MACID63_32_PKTSLEEP_8197F 0 #define BIT_MASK_MACID63_32_PKTSLEEP_8197F 0xffffffffL -#define BIT_MACID63_32_PKTSLEEP_8197F(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8197F) << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) -#define BITS_MACID63_32_PKTSLEEP_8197F (BIT_MASK_MACID63_32_PKTSLEEP_8197F << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) -#define BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) ((x) & (~BITS_MACID63_32_PKTSLEEP_8197F)) -#define BIT_GET_MACID63_32_PKTSLEEP_8197F(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) & BIT_MASK_MACID63_32_PKTSLEEP_8197F) -#define BIT_SET_MACID63_32_PKTSLEEP_8197F(x, v) (BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) | BIT_MACID63_32_PKTSLEEP_8197F(v)) - +#define BIT_MACID63_32_PKTSLEEP_8197F(x) \ + (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8197F) \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) +#define BITS_MACID63_32_PKTSLEEP_8197F \ + (BIT_MASK_MACID63_32_PKTSLEEP_8197F \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) +#define BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) \ + ((x) & (~BITS_MACID63_32_PKTSLEEP_8197F)) +#define BIT_GET_MACID63_32_PKTSLEEP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) & \ + BIT_MASK_MACID63_32_PKTSLEEP_8197F) +#define BIT_SET_MACID63_32_PKTSLEEP_8197F(x, v) \ + (BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) | \ + BIT_MACID63_32_PKTSLEEP_8197F(v)) /* 2 REG_ARFR2_V1_8197F */ #define BIT_SHIFT_ARFR2_V1_8197F 0 #define BIT_MASK_ARFR2_V1_8197F 0xffffffffffffffffL -#define BIT_ARFR2_V1_8197F(x) (((x) & BIT_MASK_ARFR2_V1_8197F) << BIT_SHIFT_ARFR2_V1_8197F) -#define BITS_ARFR2_V1_8197F (BIT_MASK_ARFR2_V1_8197F << BIT_SHIFT_ARFR2_V1_8197F) +#define BIT_ARFR2_V1_8197F(x) \ + (((x) & BIT_MASK_ARFR2_V1_8197F) << BIT_SHIFT_ARFR2_V1_8197F) +#define BITS_ARFR2_V1_8197F \ + (BIT_MASK_ARFR2_V1_8197F << BIT_SHIFT_ARFR2_V1_8197F) #define BIT_CLEAR_ARFR2_V1_8197F(x) ((x) & (~BITS_ARFR2_V1_8197F)) -#define BIT_GET_ARFR2_V1_8197F(x) (((x) >> BIT_SHIFT_ARFR2_V1_8197F) & BIT_MASK_ARFR2_V1_8197F) -#define BIT_SET_ARFR2_V1_8197F(x, v) (BIT_CLEAR_ARFR2_V1_8197F(x) | BIT_ARFR2_V1_8197F(v)) - +#define BIT_GET_ARFR2_V1_8197F(x) \ + (((x) >> BIT_SHIFT_ARFR2_V1_8197F) & BIT_MASK_ARFR2_V1_8197F) +#define BIT_SET_ARFR2_V1_8197F(x, v) \ + (BIT_CLEAR_ARFR2_V1_8197F(x) | BIT_ARFR2_V1_8197F(v)) /* 2 REG_ARFR3_V1_8197F */ #define BIT_SHIFT_ARFR3_V1_8197F 0 #define BIT_MASK_ARFR3_V1_8197F 0xffffffffffffffffL -#define BIT_ARFR3_V1_8197F(x) (((x) & BIT_MASK_ARFR3_V1_8197F) << BIT_SHIFT_ARFR3_V1_8197F) -#define BITS_ARFR3_V1_8197F (BIT_MASK_ARFR3_V1_8197F << BIT_SHIFT_ARFR3_V1_8197F) +#define BIT_ARFR3_V1_8197F(x) \ + (((x) & BIT_MASK_ARFR3_V1_8197F) << BIT_SHIFT_ARFR3_V1_8197F) +#define BITS_ARFR3_V1_8197F \ + (BIT_MASK_ARFR3_V1_8197F << BIT_SHIFT_ARFR3_V1_8197F) #define BIT_CLEAR_ARFR3_V1_8197F(x) ((x) & (~BITS_ARFR3_V1_8197F)) -#define BIT_GET_ARFR3_V1_8197F(x) (((x) >> BIT_SHIFT_ARFR3_V1_8197F) & BIT_MASK_ARFR3_V1_8197F) -#define BIT_SET_ARFR3_V1_8197F(x, v) (BIT_CLEAR_ARFR3_V1_8197F(x) | BIT_ARFR3_V1_8197F(v)) - +#define BIT_GET_ARFR3_V1_8197F(x) \ + (((x) >> BIT_SHIFT_ARFR3_V1_8197F) & BIT_MASK_ARFR3_V1_8197F) +#define BIT_SET_ARFR3_V1_8197F(x, v) \ + (BIT_CLEAR_ARFR3_V1_8197F(x) | BIT_ARFR3_V1_8197F(v)) /* 2 REG_ARFR4_8197F */ #define BIT_SHIFT_ARFR4_8197F 0 #define BIT_MASK_ARFR4_8197F 0xffffffffffffffffL -#define BIT_ARFR4_8197F(x) (((x) & BIT_MASK_ARFR4_8197F) << BIT_SHIFT_ARFR4_8197F) +#define BIT_ARFR4_8197F(x) \ + (((x) & BIT_MASK_ARFR4_8197F) << BIT_SHIFT_ARFR4_8197F) #define BITS_ARFR4_8197F (BIT_MASK_ARFR4_8197F << BIT_SHIFT_ARFR4_8197F) #define BIT_CLEAR_ARFR4_8197F(x) ((x) & (~BITS_ARFR4_8197F)) -#define BIT_GET_ARFR4_8197F(x) (((x) >> BIT_SHIFT_ARFR4_8197F) & BIT_MASK_ARFR4_8197F) -#define BIT_SET_ARFR4_8197F(x, v) (BIT_CLEAR_ARFR4_8197F(x) | BIT_ARFR4_8197F(v)) - +#define BIT_GET_ARFR4_8197F(x) \ + (((x) >> BIT_SHIFT_ARFR4_8197F) & BIT_MASK_ARFR4_8197F) +#define BIT_SET_ARFR4_8197F(x, v) \ + (BIT_CLEAR_ARFR4_8197F(x) | BIT_ARFR4_8197F(v)) /* 2 REG_ARFR5_8197F */ #define BIT_SHIFT_ARFR5_8197F 0 #define BIT_MASK_ARFR5_8197F 0xffffffffffffffffL -#define BIT_ARFR5_8197F(x) (((x) & BIT_MASK_ARFR5_8197F) << BIT_SHIFT_ARFR5_8197F) +#define BIT_ARFR5_8197F(x) \ + (((x) & BIT_MASK_ARFR5_8197F) << BIT_SHIFT_ARFR5_8197F) #define BITS_ARFR5_8197F (BIT_MASK_ARFR5_8197F << BIT_SHIFT_ARFR5_8197F) #define BIT_CLEAR_ARFR5_8197F(x) ((x) & (~BITS_ARFR5_8197F)) -#define BIT_GET_ARFR5_8197F(x) (((x) >> BIT_SHIFT_ARFR5_8197F) & BIT_MASK_ARFR5_8197F) -#define BIT_SET_ARFR5_8197F(x, v) (BIT_CLEAR_ARFR5_8197F(x) | BIT_ARFR5_8197F(v)) - +#define BIT_GET_ARFR5_8197F(x) \ + (((x) >> BIT_SHIFT_ARFR5_8197F) & BIT_MASK_ARFR5_8197F) +#define BIT_SET_ARFR5_8197F(x, v) \ + (BIT_CLEAR_ARFR5_8197F(x) | BIT_ARFR5_8197F(v)) /* 2 REG_TXRPT_START_OFFSET_8197F */ #define BIT_SHCUT_PARSE_DASA_8197F BIT(25) @@ -7236,21 +9335,35 @@ #define BIT_SHIFT_MACID_CTRL_OFFSET_8197F 8 #define BIT_MASK_MACID_CTRL_OFFSET_8197F 0xff -#define BIT_MACID_CTRL_OFFSET_8197F(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8197F) << BIT_SHIFT_MACID_CTRL_OFFSET_8197F) -#define BITS_MACID_CTRL_OFFSET_8197F (BIT_MASK_MACID_CTRL_OFFSET_8197F << BIT_SHIFT_MACID_CTRL_OFFSET_8197F) -#define BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) ((x) & (~BITS_MACID_CTRL_OFFSET_8197F)) -#define BIT_GET_MACID_CTRL_OFFSET_8197F(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8197F) & BIT_MASK_MACID_CTRL_OFFSET_8197F) -#define BIT_SET_MACID_CTRL_OFFSET_8197F(x, v) (BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) | BIT_MACID_CTRL_OFFSET_8197F(v)) - +#define BIT_MACID_CTRL_OFFSET_8197F(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET_8197F) \ + << BIT_SHIFT_MACID_CTRL_OFFSET_8197F) +#define BITS_MACID_CTRL_OFFSET_8197F \ + (BIT_MASK_MACID_CTRL_OFFSET_8197F << BIT_SHIFT_MACID_CTRL_OFFSET_8197F) +#define BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) \ + ((x) & (~BITS_MACID_CTRL_OFFSET_8197F)) +#define BIT_GET_MACID_CTRL_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8197F) & \ + BIT_MASK_MACID_CTRL_OFFSET_8197F) +#define BIT_SET_MACID_CTRL_OFFSET_8197F(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) | BIT_MACID_CTRL_OFFSET_8197F(v)) #define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F 0 #define BIT_MASK_AMPDU_TXRPT_OFFSET_8197F 0xff -#define BIT_AMPDU_TXRPT_OFFSET_8197F(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8197F) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) -#define BITS_AMPDU_TXRPT_OFFSET_8197F (BIT_MASK_AMPDU_TXRPT_OFFSET_8197F << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) -#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8197F)) -#define BIT_GET_AMPDU_TXRPT_OFFSET_8197F(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) & BIT_MASK_AMPDU_TXRPT_OFFSET_8197F) -#define BIT_SET_AMPDU_TXRPT_OFFSET_8197F(x, v) (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) | BIT_AMPDU_TXRPT_OFFSET_8197F(v)) - +#define BIT_AMPDU_TXRPT_OFFSET_8197F(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8197F) \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) +#define BITS_AMPDU_TXRPT_OFFSET_8197F \ + (BIT_MASK_AMPDU_TXRPT_OFFSET_8197F \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) \ + ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8197F)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) & \ + BIT_MASK_AMPDU_TXRPT_OFFSET_8197F) +#define BIT_SET_AMPDU_TXRPT_OFFSET_8197F(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) | \ + BIT_AMPDU_TXRPT_OFFSET_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -7266,34 +9379,44 @@ #define BIT_SHIFT_POWER_STAGE1_8197F 0 #define BIT_MASK_POWER_STAGE1_8197F 0xffffff -#define BIT_POWER_STAGE1_8197F(x) (((x) & BIT_MASK_POWER_STAGE1_8197F) << BIT_SHIFT_POWER_STAGE1_8197F) -#define BITS_POWER_STAGE1_8197F (BIT_MASK_POWER_STAGE1_8197F << BIT_SHIFT_POWER_STAGE1_8197F) +#define BIT_POWER_STAGE1_8197F(x) \ + (((x) & BIT_MASK_POWER_STAGE1_8197F) << BIT_SHIFT_POWER_STAGE1_8197F) +#define BITS_POWER_STAGE1_8197F \ + (BIT_MASK_POWER_STAGE1_8197F << BIT_SHIFT_POWER_STAGE1_8197F) #define BIT_CLEAR_POWER_STAGE1_8197F(x) ((x) & (~BITS_POWER_STAGE1_8197F)) -#define BIT_GET_POWER_STAGE1_8197F(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8197F) & BIT_MASK_POWER_STAGE1_8197F) -#define BIT_SET_POWER_STAGE1_8197F(x, v) (BIT_CLEAR_POWER_STAGE1_8197F(x) | BIT_POWER_STAGE1_8197F(v)) - +#define BIT_GET_POWER_STAGE1_8197F(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1_8197F) & BIT_MASK_POWER_STAGE1_8197F) +#define BIT_SET_POWER_STAGE1_8197F(x, v) \ + (BIT_CLEAR_POWER_STAGE1_8197F(x) | BIT_POWER_STAGE1_8197F(v)) /* 2 REG_POWER_STAGE2_8197F */ #define BIT__R_CTRL_PKT_POW_ADJ_8197F BIT(24) #define BIT_SHIFT_POWER_STAGE2_8197F 0 #define BIT_MASK_POWER_STAGE2_8197F 0xffffff -#define BIT_POWER_STAGE2_8197F(x) (((x) & BIT_MASK_POWER_STAGE2_8197F) << BIT_SHIFT_POWER_STAGE2_8197F) -#define BITS_POWER_STAGE2_8197F (BIT_MASK_POWER_STAGE2_8197F << BIT_SHIFT_POWER_STAGE2_8197F) +#define BIT_POWER_STAGE2_8197F(x) \ + (((x) & BIT_MASK_POWER_STAGE2_8197F) << BIT_SHIFT_POWER_STAGE2_8197F) +#define BITS_POWER_STAGE2_8197F \ + (BIT_MASK_POWER_STAGE2_8197F << BIT_SHIFT_POWER_STAGE2_8197F) #define BIT_CLEAR_POWER_STAGE2_8197F(x) ((x) & (~BITS_POWER_STAGE2_8197F)) -#define BIT_GET_POWER_STAGE2_8197F(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8197F) & BIT_MASK_POWER_STAGE2_8197F) -#define BIT_SET_POWER_STAGE2_8197F(x, v) (BIT_CLEAR_POWER_STAGE2_8197F(x) | BIT_POWER_STAGE2_8197F(v)) - +#define BIT_GET_POWER_STAGE2_8197F(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2_8197F) & BIT_MASK_POWER_STAGE2_8197F) +#define BIT_SET_POWER_STAGE2_8197F(x, v) \ + (BIT_CLEAR_POWER_STAGE2_8197F(x) | BIT_POWER_STAGE2_8197F(v)) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8197F */ #define BIT_SHIFT_PAD_NUM_THRES_8197F 24 #define BIT_MASK_PAD_NUM_THRES_8197F 0x3f -#define BIT_PAD_NUM_THRES_8197F(x) (((x) & BIT_MASK_PAD_NUM_THRES_8197F) << BIT_SHIFT_PAD_NUM_THRES_8197F) -#define BITS_PAD_NUM_THRES_8197F (BIT_MASK_PAD_NUM_THRES_8197F << BIT_SHIFT_PAD_NUM_THRES_8197F) +#define BIT_PAD_NUM_THRES_8197F(x) \ + (((x) & BIT_MASK_PAD_NUM_THRES_8197F) << BIT_SHIFT_PAD_NUM_THRES_8197F) +#define BITS_PAD_NUM_THRES_8197F \ + (BIT_MASK_PAD_NUM_THRES_8197F << BIT_SHIFT_PAD_NUM_THRES_8197F) #define BIT_CLEAR_PAD_NUM_THRES_8197F(x) ((x) & (~BITS_PAD_NUM_THRES_8197F)) -#define BIT_GET_PAD_NUM_THRES_8197F(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8197F) & BIT_MASK_PAD_NUM_THRES_8197F) -#define BIT_SET_PAD_NUM_THRES_8197F(x, v) (BIT_CLEAR_PAD_NUM_THRES_8197F(x) | BIT_PAD_NUM_THRES_8197F(v)) +#define BIT_GET_PAD_NUM_THRES_8197F(x) \ + (((x) >> BIT_SHIFT_PAD_NUM_THRES_8197F) & BIT_MASK_PAD_NUM_THRES_8197F) +#define BIT_SET_PAD_NUM_THRES_8197F(x, v) \ + (BIT_CLEAR_PAD_NUM_THRES_8197F(x) | BIT_PAD_NUM_THRES_8197F(v)) #define BIT_R_DMA_THIS_QUEUE_BK_8197F BIT(23) #define BIT_R_DMA_THIS_QUEUE_BE_8197F BIT(22) @@ -7302,22 +9425,32 @@ #define BIT_SHIFT_R_TOTAL_LEN_TH_8197F 8 #define BIT_MASK_R_TOTAL_LEN_TH_8197F 0xfff -#define BIT_R_TOTAL_LEN_TH_8197F(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8197F) << BIT_SHIFT_R_TOTAL_LEN_TH_8197F) -#define BITS_R_TOTAL_LEN_TH_8197F (BIT_MASK_R_TOTAL_LEN_TH_8197F << BIT_SHIFT_R_TOTAL_LEN_TH_8197F) +#define BIT_R_TOTAL_LEN_TH_8197F(x) \ + (((x) & BIT_MASK_R_TOTAL_LEN_TH_8197F) \ + << BIT_SHIFT_R_TOTAL_LEN_TH_8197F) +#define BITS_R_TOTAL_LEN_TH_8197F \ + (BIT_MASK_R_TOTAL_LEN_TH_8197F << BIT_SHIFT_R_TOTAL_LEN_TH_8197F) #define BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8197F)) -#define BIT_GET_R_TOTAL_LEN_TH_8197F(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8197F) & BIT_MASK_R_TOTAL_LEN_TH_8197F) -#define BIT_SET_R_TOTAL_LEN_TH_8197F(x, v) (BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) | BIT_R_TOTAL_LEN_TH_8197F(v)) +#define BIT_GET_R_TOTAL_LEN_TH_8197F(x) \ + (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8197F) & \ + BIT_MASK_R_TOTAL_LEN_TH_8197F) +#define BIT_SET_R_TOTAL_LEN_TH_8197F(x, v) \ + (BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) | BIT_R_TOTAL_LEN_TH_8197F(v)) #define BIT_EN_NEW_EARLY_8197F BIT(7) #define BIT_PRE_TX_CMD_8197F BIT(6) #define BIT_SHIFT_NUM_SCL_EN_8197F 4 #define BIT_MASK_NUM_SCL_EN_8197F 0x3 -#define BIT_NUM_SCL_EN_8197F(x) (((x) & BIT_MASK_NUM_SCL_EN_8197F) << BIT_SHIFT_NUM_SCL_EN_8197F) -#define BITS_NUM_SCL_EN_8197F (BIT_MASK_NUM_SCL_EN_8197F << BIT_SHIFT_NUM_SCL_EN_8197F) +#define BIT_NUM_SCL_EN_8197F(x) \ + (((x) & BIT_MASK_NUM_SCL_EN_8197F) << BIT_SHIFT_NUM_SCL_EN_8197F) +#define BITS_NUM_SCL_EN_8197F \ + (BIT_MASK_NUM_SCL_EN_8197F << BIT_SHIFT_NUM_SCL_EN_8197F) #define BIT_CLEAR_NUM_SCL_EN_8197F(x) ((x) & (~BITS_NUM_SCL_EN_8197F)) -#define BIT_GET_NUM_SCL_EN_8197F(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8197F) & BIT_MASK_NUM_SCL_EN_8197F) -#define BIT_SET_NUM_SCL_EN_8197F(x, v) (BIT_CLEAR_NUM_SCL_EN_8197F(x) | BIT_NUM_SCL_EN_8197F(v)) +#define BIT_GET_NUM_SCL_EN_8197F(x) \ + (((x) >> BIT_SHIFT_NUM_SCL_EN_8197F) & BIT_MASK_NUM_SCL_EN_8197F) +#define BIT_SET_NUM_SCL_EN_8197F(x, v) \ + (BIT_CLEAR_NUM_SCL_EN_8197F(x) | BIT_NUM_SCL_EN_8197F(v)) #define BIT_BK_EN_8197F BIT(3) #define BIT_BE_EN_8197F BIT(2) @@ -7328,61 +9461,86 @@ #define BIT_SHIFT_PKT_LIFTIME_BEBK_8197F 16 #define BIT_MASK_PKT_LIFTIME_BEBK_8197F 0xffff -#define BIT_PKT_LIFTIME_BEBK_8197F(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8197F) << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) -#define BITS_PKT_LIFTIME_BEBK_8197F (BIT_MASK_PKT_LIFTIME_BEBK_8197F << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) -#define BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) ((x) & (~BITS_PKT_LIFTIME_BEBK_8197F)) -#define BIT_GET_PKT_LIFTIME_BEBK_8197F(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) & BIT_MASK_PKT_LIFTIME_BEBK_8197F) -#define BIT_SET_PKT_LIFTIME_BEBK_8197F(x, v) (BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) | BIT_PKT_LIFTIME_BEBK_8197F(v)) - +#define BIT_PKT_LIFTIME_BEBK_8197F(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8197F) \ + << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) +#define BITS_PKT_LIFTIME_BEBK_8197F \ + (BIT_MASK_PKT_LIFTIME_BEBK_8197F << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) +#define BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) \ + ((x) & (~BITS_PKT_LIFTIME_BEBK_8197F)) +#define BIT_GET_PKT_LIFTIME_BEBK_8197F(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) & \ + BIT_MASK_PKT_LIFTIME_BEBK_8197F) +#define BIT_SET_PKT_LIFTIME_BEBK_8197F(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) | BIT_PKT_LIFTIME_BEBK_8197F(v)) #define BIT_SHIFT_PKT_LIFTIME_VOVI_8197F 0 #define BIT_MASK_PKT_LIFTIME_VOVI_8197F 0xffff -#define BIT_PKT_LIFTIME_VOVI_8197F(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8197F) << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) -#define BITS_PKT_LIFTIME_VOVI_8197F (BIT_MASK_PKT_LIFTIME_VOVI_8197F << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) -#define BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) ((x) & (~BITS_PKT_LIFTIME_VOVI_8197F)) -#define BIT_GET_PKT_LIFTIME_VOVI_8197F(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) & BIT_MASK_PKT_LIFTIME_VOVI_8197F) -#define BIT_SET_PKT_LIFTIME_VOVI_8197F(x, v) (BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) | BIT_PKT_LIFTIME_VOVI_8197F(v)) - +#define BIT_PKT_LIFTIME_VOVI_8197F(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8197F) \ + << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) +#define BITS_PKT_LIFTIME_VOVI_8197F \ + (BIT_MASK_PKT_LIFTIME_VOVI_8197F << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) +#define BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) \ + ((x) & (~BITS_PKT_LIFTIME_VOVI_8197F)) +#define BIT_GET_PKT_LIFTIME_VOVI_8197F(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) & \ + BIT_MASK_PKT_LIFTIME_VOVI_8197F) +#define BIT_SET_PKT_LIFTIME_VOVI_8197F(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) | BIT_PKT_LIFTIME_VOVI_8197F(v)) /* 2 REG_STBC_SETTING_8197F */ #define BIT_SHIFT_CDEND_TXTIME_L_8197F 4 #define BIT_MASK_CDEND_TXTIME_L_8197F 0xf -#define BIT_CDEND_TXTIME_L_8197F(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8197F) << BIT_SHIFT_CDEND_TXTIME_L_8197F) -#define BITS_CDEND_TXTIME_L_8197F (BIT_MASK_CDEND_TXTIME_L_8197F << BIT_SHIFT_CDEND_TXTIME_L_8197F) +#define BIT_CDEND_TXTIME_L_8197F(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_L_8197F) \ + << BIT_SHIFT_CDEND_TXTIME_L_8197F) +#define BITS_CDEND_TXTIME_L_8197F \ + (BIT_MASK_CDEND_TXTIME_L_8197F << BIT_SHIFT_CDEND_TXTIME_L_8197F) #define BIT_CLEAR_CDEND_TXTIME_L_8197F(x) ((x) & (~BITS_CDEND_TXTIME_L_8197F)) -#define BIT_GET_CDEND_TXTIME_L_8197F(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8197F) & BIT_MASK_CDEND_TXTIME_L_8197F) -#define BIT_SET_CDEND_TXTIME_L_8197F(x, v) (BIT_CLEAR_CDEND_TXTIME_L_8197F(x) | BIT_CDEND_TXTIME_L_8197F(v)) - +#define BIT_GET_CDEND_TXTIME_L_8197F(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8197F) & \ + BIT_MASK_CDEND_TXTIME_L_8197F) +#define BIT_SET_CDEND_TXTIME_L_8197F(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_L_8197F(x) | BIT_CDEND_TXTIME_L_8197F(v)) #define BIT_SHIFT_NESS_8197F 2 #define BIT_MASK_NESS_8197F 0x3 #define BIT_NESS_8197F(x) (((x) & BIT_MASK_NESS_8197F) << BIT_SHIFT_NESS_8197F) #define BITS_NESS_8197F (BIT_MASK_NESS_8197F << BIT_SHIFT_NESS_8197F) #define BIT_CLEAR_NESS_8197F(x) ((x) & (~BITS_NESS_8197F)) -#define BIT_GET_NESS_8197F(x) (((x) >> BIT_SHIFT_NESS_8197F) & BIT_MASK_NESS_8197F) +#define BIT_GET_NESS_8197F(x) \ + (((x) >> BIT_SHIFT_NESS_8197F) & BIT_MASK_NESS_8197F) #define BIT_SET_NESS_8197F(x, v) (BIT_CLEAR_NESS_8197F(x) | BIT_NESS_8197F(v)) - #define BIT_SHIFT_STBC_CFEND_8197F 0 #define BIT_MASK_STBC_CFEND_8197F 0x3 -#define BIT_STBC_CFEND_8197F(x) (((x) & BIT_MASK_STBC_CFEND_8197F) << BIT_SHIFT_STBC_CFEND_8197F) -#define BITS_STBC_CFEND_8197F (BIT_MASK_STBC_CFEND_8197F << BIT_SHIFT_STBC_CFEND_8197F) +#define BIT_STBC_CFEND_8197F(x) \ + (((x) & BIT_MASK_STBC_CFEND_8197F) << BIT_SHIFT_STBC_CFEND_8197F) +#define BITS_STBC_CFEND_8197F \ + (BIT_MASK_STBC_CFEND_8197F << BIT_SHIFT_STBC_CFEND_8197F) #define BIT_CLEAR_STBC_CFEND_8197F(x) ((x) & (~BITS_STBC_CFEND_8197F)) -#define BIT_GET_STBC_CFEND_8197F(x) (((x) >> BIT_SHIFT_STBC_CFEND_8197F) & BIT_MASK_STBC_CFEND_8197F) -#define BIT_SET_STBC_CFEND_8197F(x, v) (BIT_CLEAR_STBC_CFEND_8197F(x) | BIT_STBC_CFEND_8197F(v)) - +#define BIT_GET_STBC_CFEND_8197F(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_8197F) & BIT_MASK_STBC_CFEND_8197F) +#define BIT_SET_STBC_CFEND_8197F(x, v) \ + (BIT_CLEAR_STBC_CFEND_8197F(x) | BIT_STBC_CFEND_8197F(v)) /* 2 REG_STBC_SETTING2_8197F */ #define BIT_SHIFT_CDEND_TXTIME_H_8197F 0 #define BIT_MASK_CDEND_TXTIME_H_8197F 0x1f -#define BIT_CDEND_TXTIME_H_8197F(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8197F) << BIT_SHIFT_CDEND_TXTIME_H_8197F) -#define BITS_CDEND_TXTIME_H_8197F (BIT_MASK_CDEND_TXTIME_H_8197F << BIT_SHIFT_CDEND_TXTIME_H_8197F) +#define BIT_CDEND_TXTIME_H_8197F(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_H_8197F) \ + << BIT_SHIFT_CDEND_TXTIME_H_8197F) +#define BITS_CDEND_TXTIME_H_8197F \ + (BIT_MASK_CDEND_TXTIME_H_8197F << BIT_SHIFT_CDEND_TXTIME_H_8197F) #define BIT_CLEAR_CDEND_TXTIME_H_8197F(x) ((x) & (~BITS_CDEND_TXTIME_H_8197F)) -#define BIT_GET_CDEND_TXTIME_H_8197F(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8197F) & BIT_MASK_CDEND_TXTIME_H_8197F) -#define BIT_SET_CDEND_TXTIME_H_8197F(x, v) (BIT_CLEAR_CDEND_TXTIME_H_8197F(x) | BIT_CDEND_TXTIME_H_8197F(v)) - +#define BIT_GET_CDEND_TXTIME_H_8197F(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8197F) & \ + BIT_MASK_CDEND_TXTIME_H_8197F) +#define BIT_SET_CDEND_TXTIME_H_8197F(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_H_8197F(x) | BIT_CDEND_TXTIME_H_8197F(v)) /* 2 REG_QUEUE_CTRL_8197F */ #define BIT_PTA_EDCCA_EN_8197F BIT(5) @@ -7399,165 +9557,241 @@ #define BIT_SHIFT_RTS_MAX_AGG_NUM_8197F 24 #define BIT_MASK_RTS_MAX_AGG_NUM_8197F 0x3f -#define BIT_RTS_MAX_AGG_NUM_8197F(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8197F) << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) -#define BITS_RTS_MAX_AGG_NUM_8197F (BIT_MASK_RTS_MAX_AGG_NUM_8197F << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) +#define BIT_RTS_MAX_AGG_NUM_8197F(x) \ + (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8197F) \ + << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) +#define BITS_RTS_MAX_AGG_NUM_8197F \ + (BIT_MASK_RTS_MAX_AGG_NUM_8197F << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) #define BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8197F)) -#define BIT_GET_RTS_MAX_AGG_NUM_8197F(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) & BIT_MASK_RTS_MAX_AGG_NUM_8197F) -#define BIT_SET_RTS_MAX_AGG_NUM_8197F(x, v) (BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) | BIT_RTS_MAX_AGG_NUM_8197F(v)) - +#define BIT_GET_RTS_MAX_AGG_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) & \ + BIT_MASK_RTS_MAX_AGG_NUM_8197F) +#define BIT_SET_RTS_MAX_AGG_NUM_8197F(x, v) \ + (BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) | BIT_RTS_MAX_AGG_NUM_8197F(v)) #define BIT_SHIFT_MAX_AGG_NUM_8197F 16 #define BIT_MASK_MAX_AGG_NUM_8197F 0x3f -#define BIT_MAX_AGG_NUM_8197F(x) (((x) & BIT_MASK_MAX_AGG_NUM_8197F) << BIT_SHIFT_MAX_AGG_NUM_8197F) -#define BITS_MAX_AGG_NUM_8197F (BIT_MASK_MAX_AGG_NUM_8197F << BIT_SHIFT_MAX_AGG_NUM_8197F) +#define BIT_MAX_AGG_NUM_8197F(x) \ + (((x) & BIT_MASK_MAX_AGG_NUM_8197F) << BIT_SHIFT_MAX_AGG_NUM_8197F) +#define BITS_MAX_AGG_NUM_8197F \ + (BIT_MASK_MAX_AGG_NUM_8197F << BIT_SHIFT_MAX_AGG_NUM_8197F) #define BIT_CLEAR_MAX_AGG_NUM_8197F(x) ((x) & (~BITS_MAX_AGG_NUM_8197F)) -#define BIT_GET_MAX_AGG_NUM_8197F(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8197F) & BIT_MASK_MAX_AGG_NUM_8197F) -#define BIT_SET_MAX_AGG_NUM_8197F(x, v) (BIT_CLEAR_MAX_AGG_NUM_8197F(x) | BIT_MAX_AGG_NUM_8197F(v)) - +#define BIT_GET_MAX_AGG_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_MAX_AGG_NUM_8197F) & BIT_MASK_MAX_AGG_NUM_8197F) +#define BIT_SET_MAX_AGG_NUM_8197F(x, v) \ + (BIT_CLEAR_MAX_AGG_NUM_8197F(x) | BIT_MAX_AGG_NUM_8197F(v)) #define BIT_SHIFT_RTS_TXTIME_TH_8197F 8 #define BIT_MASK_RTS_TXTIME_TH_8197F 0xff -#define BIT_RTS_TXTIME_TH_8197F(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8197F) << BIT_SHIFT_RTS_TXTIME_TH_8197F) -#define BITS_RTS_TXTIME_TH_8197F (BIT_MASK_RTS_TXTIME_TH_8197F << BIT_SHIFT_RTS_TXTIME_TH_8197F) +#define BIT_RTS_TXTIME_TH_8197F(x) \ + (((x) & BIT_MASK_RTS_TXTIME_TH_8197F) << BIT_SHIFT_RTS_TXTIME_TH_8197F) +#define BITS_RTS_TXTIME_TH_8197F \ + (BIT_MASK_RTS_TXTIME_TH_8197F << BIT_SHIFT_RTS_TXTIME_TH_8197F) #define BIT_CLEAR_RTS_TXTIME_TH_8197F(x) ((x) & (~BITS_RTS_TXTIME_TH_8197F)) -#define BIT_GET_RTS_TXTIME_TH_8197F(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8197F) & BIT_MASK_RTS_TXTIME_TH_8197F) -#define BIT_SET_RTS_TXTIME_TH_8197F(x, v) (BIT_CLEAR_RTS_TXTIME_TH_8197F(x) | BIT_RTS_TXTIME_TH_8197F(v)) - +#define BIT_GET_RTS_TXTIME_TH_8197F(x) \ + (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8197F) & BIT_MASK_RTS_TXTIME_TH_8197F) +#define BIT_SET_RTS_TXTIME_TH_8197F(x, v) \ + (BIT_CLEAR_RTS_TXTIME_TH_8197F(x) | BIT_RTS_TXTIME_TH_8197F(v)) #define BIT_SHIFT_RTS_LEN_TH_8197F 0 #define BIT_MASK_RTS_LEN_TH_8197F 0xff -#define BIT_RTS_LEN_TH_8197F(x) (((x) & BIT_MASK_RTS_LEN_TH_8197F) << BIT_SHIFT_RTS_LEN_TH_8197F) -#define BITS_RTS_LEN_TH_8197F (BIT_MASK_RTS_LEN_TH_8197F << BIT_SHIFT_RTS_LEN_TH_8197F) +#define BIT_RTS_LEN_TH_8197F(x) \ + (((x) & BIT_MASK_RTS_LEN_TH_8197F) << BIT_SHIFT_RTS_LEN_TH_8197F) +#define BITS_RTS_LEN_TH_8197F \ + (BIT_MASK_RTS_LEN_TH_8197F << BIT_SHIFT_RTS_LEN_TH_8197F) #define BIT_CLEAR_RTS_LEN_TH_8197F(x) ((x) & (~BITS_RTS_LEN_TH_8197F)) -#define BIT_GET_RTS_LEN_TH_8197F(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8197F) & BIT_MASK_RTS_LEN_TH_8197F) -#define BIT_SET_RTS_LEN_TH_8197F(x, v) (BIT_CLEAR_RTS_LEN_TH_8197F(x) | BIT_RTS_LEN_TH_8197F(v)) - +#define BIT_GET_RTS_LEN_TH_8197F(x) \ + (((x) >> BIT_SHIFT_RTS_LEN_TH_8197F) & BIT_MASK_RTS_LEN_TH_8197F) +#define BIT_SET_RTS_LEN_TH_8197F(x, v) \ + (BIT_CLEAR_RTS_LEN_TH_8197F(x) | BIT_RTS_LEN_TH_8197F(v)) /* 2 REG_BAR_MODE_CTRL_8197F */ #define BIT_SHIFT_BAR_RTY_LMT_8197F 16 #define BIT_MASK_BAR_RTY_LMT_8197F 0x3 -#define BIT_BAR_RTY_LMT_8197F(x) (((x) & BIT_MASK_BAR_RTY_LMT_8197F) << BIT_SHIFT_BAR_RTY_LMT_8197F) -#define BITS_BAR_RTY_LMT_8197F (BIT_MASK_BAR_RTY_LMT_8197F << BIT_SHIFT_BAR_RTY_LMT_8197F) +#define BIT_BAR_RTY_LMT_8197F(x) \ + (((x) & BIT_MASK_BAR_RTY_LMT_8197F) << BIT_SHIFT_BAR_RTY_LMT_8197F) +#define BITS_BAR_RTY_LMT_8197F \ + (BIT_MASK_BAR_RTY_LMT_8197F << BIT_SHIFT_BAR_RTY_LMT_8197F) #define BIT_CLEAR_BAR_RTY_LMT_8197F(x) ((x) & (~BITS_BAR_RTY_LMT_8197F)) -#define BIT_GET_BAR_RTY_LMT_8197F(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8197F) & BIT_MASK_BAR_RTY_LMT_8197F) -#define BIT_SET_BAR_RTY_LMT_8197F(x, v) (BIT_CLEAR_BAR_RTY_LMT_8197F(x) | BIT_BAR_RTY_LMT_8197F(v)) - +#define BIT_GET_BAR_RTY_LMT_8197F(x) \ + (((x) >> BIT_SHIFT_BAR_RTY_LMT_8197F) & BIT_MASK_BAR_RTY_LMT_8197F) +#define BIT_SET_BAR_RTY_LMT_8197F(x, v) \ + (BIT_CLEAR_BAR_RTY_LMT_8197F(x) | BIT_BAR_RTY_LMT_8197F(v)) #define BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F 8 #define BIT_MASK_BAR_PKT_TXTIME_TH_8197F 0xff -#define BIT_BAR_PKT_TXTIME_TH_8197F(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8197F) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) -#define BITS_BAR_PKT_TXTIME_TH_8197F (BIT_MASK_BAR_PKT_TXTIME_TH_8197F << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) -#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) ((x) & (~BITS_BAR_PKT_TXTIME_TH_8197F)) -#define BIT_GET_BAR_PKT_TXTIME_TH_8197F(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) & BIT_MASK_BAR_PKT_TXTIME_TH_8197F) -#define BIT_SET_BAR_PKT_TXTIME_TH_8197F(x, v) (BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) | BIT_BAR_PKT_TXTIME_TH_8197F(v)) +#define BIT_BAR_PKT_TXTIME_TH_8197F(x) \ + (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8197F) \ + << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) +#define BITS_BAR_PKT_TXTIME_TH_8197F \ + (BIT_MASK_BAR_PKT_TXTIME_TH_8197F << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) \ + ((x) & (~BITS_BAR_PKT_TXTIME_TH_8197F)) +#define BIT_GET_BAR_PKT_TXTIME_TH_8197F(x) \ + (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) & \ + BIT_MASK_BAR_PKT_TXTIME_TH_8197F) +#define BIT_SET_BAR_PKT_TXTIME_TH_8197F(x, v) \ + (BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) | BIT_BAR_PKT_TXTIME_TH_8197F(v)) #define BIT_BAR_EN_V1_8197F BIT(6) #define BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F 0 #define BIT_MASK_BAR_PKTNUM_TH_V1_8197F 0x3f -#define BIT_BAR_PKTNUM_TH_V1_8197F(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8197F) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) -#define BITS_BAR_PKTNUM_TH_V1_8197F (BIT_MASK_BAR_PKTNUM_TH_V1_8197F << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) -#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) ((x) & (~BITS_BAR_PKTNUM_TH_V1_8197F)) -#define BIT_GET_BAR_PKTNUM_TH_V1_8197F(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) & BIT_MASK_BAR_PKTNUM_TH_V1_8197F) -#define BIT_SET_BAR_PKTNUM_TH_V1_8197F(x, v) (BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) | BIT_BAR_PKTNUM_TH_V1_8197F(v)) - +#define BIT_BAR_PKTNUM_TH_V1_8197F(x) \ + (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8197F) \ + << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) +#define BITS_BAR_PKTNUM_TH_V1_8197F \ + (BIT_MASK_BAR_PKTNUM_TH_V1_8197F << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) \ + ((x) & (~BITS_BAR_PKTNUM_TH_V1_8197F)) +#define BIT_GET_BAR_PKTNUM_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) & \ + BIT_MASK_BAR_PKTNUM_TH_V1_8197F) +#define BIT_SET_BAR_PKTNUM_TH_V1_8197F(x, v) \ + (BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) | BIT_BAR_PKTNUM_TH_V1_8197F(v)) /* 2 REG_RA_TRY_RATE_AGG_LMT_8197F */ #define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F 0 #define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F 0x3f -#define BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) -#define BITS_RA_TRY_RATE_AGG_LMT_V1_8197F (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) -#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8197F)) -#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8197F(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F) -#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8197F(x, v) (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) | BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(v)) - +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F) \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) +#define BITS_RA_TRY_RATE_AGG_LMT_V1_8197F \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) \ + ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8197F)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8197F(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) & \ + BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8197F(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) | \ + BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(v)) /* 2 REG_MACID_SLEEP2_8197F */ #define BIT_SHIFT_MACID95_64PKTSLEEP_8197F 0 #define BIT_MASK_MACID95_64PKTSLEEP_8197F 0xffffffffL -#define BIT_MACID95_64PKTSLEEP_8197F(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8197F) << BIT_SHIFT_MACID95_64PKTSLEEP_8197F) -#define BITS_MACID95_64PKTSLEEP_8197F (BIT_MASK_MACID95_64PKTSLEEP_8197F << BIT_SHIFT_MACID95_64PKTSLEEP_8197F) -#define BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) ((x) & (~BITS_MACID95_64PKTSLEEP_8197F)) -#define BIT_GET_MACID95_64PKTSLEEP_8197F(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8197F) & BIT_MASK_MACID95_64PKTSLEEP_8197F) -#define BIT_SET_MACID95_64PKTSLEEP_8197F(x, v) (BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) | BIT_MACID95_64PKTSLEEP_8197F(v)) - +#define BIT_MACID95_64PKTSLEEP_8197F(x) \ + (((x) & BIT_MASK_MACID95_64PKTSLEEP_8197F) \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8197F) +#define BITS_MACID95_64PKTSLEEP_8197F \ + (BIT_MASK_MACID95_64PKTSLEEP_8197F \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8197F) +#define BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) \ + ((x) & (~BITS_MACID95_64PKTSLEEP_8197F)) +#define BIT_GET_MACID95_64PKTSLEEP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8197F) & \ + BIT_MASK_MACID95_64PKTSLEEP_8197F) +#define BIT_SET_MACID95_64PKTSLEEP_8197F(x, v) \ + (BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) | \ + BIT_MACID95_64PKTSLEEP_8197F(v)) /* 2 REG_MACID_SLEEP_8197F */ #define BIT_SHIFT_MACID31_0_PKTSLEEP_8197F 0 #define BIT_MASK_MACID31_0_PKTSLEEP_8197F 0xffffffffL -#define BIT_MACID31_0_PKTSLEEP_8197F(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8197F) << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) -#define BITS_MACID31_0_PKTSLEEP_8197F (BIT_MASK_MACID31_0_PKTSLEEP_8197F << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) -#define BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) ((x) & (~BITS_MACID31_0_PKTSLEEP_8197F)) -#define BIT_GET_MACID31_0_PKTSLEEP_8197F(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) & BIT_MASK_MACID31_0_PKTSLEEP_8197F) -#define BIT_SET_MACID31_0_PKTSLEEP_8197F(x, v) (BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) | BIT_MACID31_0_PKTSLEEP_8197F(v)) - +#define BIT_MACID31_0_PKTSLEEP_8197F(x) \ + (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8197F) \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) +#define BITS_MACID31_0_PKTSLEEP_8197F \ + (BIT_MASK_MACID31_0_PKTSLEEP_8197F \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) +#define BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) \ + ((x) & (~BITS_MACID31_0_PKTSLEEP_8197F)) +#define BIT_GET_MACID31_0_PKTSLEEP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) & \ + BIT_MASK_MACID31_0_PKTSLEEP_8197F) +#define BIT_SET_MACID31_0_PKTSLEEP_8197F(x, v) \ + (BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) | \ + BIT_MACID31_0_PKTSLEEP_8197F(v)) /* 2 REG_HW_SEQ0_8197F */ #define BIT_SHIFT_HW_SSN_SEQ0_8197F 0 #define BIT_MASK_HW_SSN_SEQ0_8197F 0xfff -#define BIT_HW_SSN_SEQ0_8197F(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8197F) << BIT_SHIFT_HW_SSN_SEQ0_8197F) -#define BITS_HW_SSN_SEQ0_8197F (BIT_MASK_HW_SSN_SEQ0_8197F << BIT_SHIFT_HW_SSN_SEQ0_8197F) +#define BIT_HW_SSN_SEQ0_8197F(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ0_8197F) << BIT_SHIFT_HW_SSN_SEQ0_8197F) +#define BITS_HW_SSN_SEQ0_8197F \ + (BIT_MASK_HW_SSN_SEQ0_8197F << BIT_SHIFT_HW_SSN_SEQ0_8197F) #define BIT_CLEAR_HW_SSN_SEQ0_8197F(x) ((x) & (~BITS_HW_SSN_SEQ0_8197F)) -#define BIT_GET_HW_SSN_SEQ0_8197F(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8197F) & BIT_MASK_HW_SSN_SEQ0_8197F) -#define BIT_SET_HW_SSN_SEQ0_8197F(x, v) (BIT_CLEAR_HW_SSN_SEQ0_8197F(x) | BIT_HW_SSN_SEQ0_8197F(v)) - +#define BIT_GET_HW_SSN_SEQ0_8197F(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8197F) & BIT_MASK_HW_SSN_SEQ0_8197F) +#define BIT_SET_HW_SSN_SEQ0_8197F(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ0_8197F(x) | BIT_HW_SSN_SEQ0_8197F(v)) /* 2 REG_HW_SEQ1_8197F */ #define BIT_SHIFT_HW_SSN_SEQ1_8197F 0 #define BIT_MASK_HW_SSN_SEQ1_8197F 0xfff -#define BIT_HW_SSN_SEQ1_8197F(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8197F) << BIT_SHIFT_HW_SSN_SEQ1_8197F) -#define BITS_HW_SSN_SEQ1_8197F (BIT_MASK_HW_SSN_SEQ1_8197F << BIT_SHIFT_HW_SSN_SEQ1_8197F) +#define BIT_HW_SSN_SEQ1_8197F(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ1_8197F) << BIT_SHIFT_HW_SSN_SEQ1_8197F) +#define BITS_HW_SSN_SEQ1_8197F \ + (BIT_MASK_HW_SSN_SEQ1_8197F << BIT_SHIFT_HW_SSN_SEQ1_8197F) #define BIT_CLEAR_HW_SSN_SEQ1_8197F(x) ((x) & (~BITS_HW_SSN_SEQ1_8197F)) -#define BIT_GET_HW_SSN_SEQ1_8197F(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8197F) & BIT_MASK_HW_SSN_SEQ1_8197F) -#define BIT_SET_HW_SSN_SEQ1_8197F(x, v) (BIT_CLEAR_HW_SSN_SEQ1_8197F(x) | BIT_HW_SSN_SEQ1_8197F(v)) - +#define BIT_GET_HW_SSN_SEQ1_8197F(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8197F) & BIT_MASK_HW_SSN_SEQ1_8197F) +#define BIT_SET_HW_SSN_SEQ1_8197F(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ1_8197F(x) | BIT_HW_SSN_SEQ1_8197F(v)) /* 2 REG_HW_SEQ2_8197F */ #define BIT_SHIFT_HW_SSN_SEQ2_8197F 0 #define BIT_MASK_HW_SSN_SEQ2_8197F 0xfff -#define BIT_HW_SSN_SEQ2_8197F(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8197F) << BIT_SHIFT_HW_SSN_SEQ2_8197F) -#define BITS_HW_SSN_SEQ2_8197F (BIT_MASK_HW_SSN_SEQ2_8197F << BIT_SHIFT_HW_SSN_SEQ2_8197F) +#define BIT_HW_SSN_SEQ2_8197F(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ2_8197F) << BIT_SHIFT_HW_SSN_SEQ2_8197F) +#define BITS_HW_SSN_SEQ2_8197F \ + (BIT_MASK_HW_SSN_SEQ2_8197F << BIT_SHIFT_HW_SSN_SEQ2_8197F) #define BIT_CLEAR_HW_SSN_SEQ2_8197F(x) ((x) & (~BITS_HW_SSN_SEQ2_8197F)) -#define BIT_GET_HW_SSN_SEQ2_8197F(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8197F) & BIT_MASK_HW_SSN_SEQ2_8197F) -#define BIT_SET_HW_SSN_SEQ2_8197F(x, v) (BIT_CLEAR_HW_SSN_SEQ2_8197F(x) | BIT_HW_SSN_SEQ2_8197F(v)) - +#define BIT_GET_HW_SSN_SEQ2_8197F(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8197F) & BIT_MASK_HW_SSN_SEQ2_8197F) +#define BIT_SET_HW_SSN_SEQ2_8197F(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ2_8197F(x) | BIT_HW_SSN_SEQ2_8197F(v)) /* 2 REG_HW_SEQ3_8197F */ #define BIT_SHIFT_CSI_HWSSN_SEL_8197F 12 #define BIT_MASK_CSI_HWSSN_SEL_8197F 0x3 -#define BIT_CSI_HWSSN_SEL_8197F(x) (((x) & BIT_MASK_CSI_HWSSN_SEL_8197F) << BIT_SHIFT_CSI_HWSSN_SEL_8197F) -#define BITS_CSI_HWSSN_SEL_8197F (BIT_MASK_CSI_HWSSN_SEL_8197F << BIT_SHIFT_CSI_HWSSN_SEL_8197F) +#define BIT_CSI_HWSSN_SEL_8197F(x) \ + (((x) & BIT_MASK_CSI_HWSSN_SEL_8197F) << BIT_SHIFT_CSI_HWSSN_SEL_8197F) +#define BITS_CSI_HWSSN_SEL_8197F \ + (BIT_MASK_CSI_HWSSN_SEL_8197F << BIT_SHIFT_CSI_HWSSN_SEL_8197F) #define BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) ((x) & (~BITS_CSI_HWSSN_SEL_8197F)) -#define BIT_GET_CSI_HWSSN_SEL_8197F(x) (((x) >> BIT_SHIFT_CSI_HWSSN_SEL_8197F) & BIT_MASK_CSI_HWSSN_SEL_8197F) -#define BIT_SET_CSI_HWSSN_SEL_8197F(x, v) (BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) | BIT_CSI_HWSSN_SEL_8197F(v)) - +#define BIT_GET_CSI_HWSSN_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_CSI_HWSSN_SEL_8197F) & BIT_MASK_CSI_HWSSN_SEL_8197F) +#define BIT_SET_CSI_HWSSN_SEL_8197F(x, v) \ + (BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) | BIT_CSI_HWSSN_SEL_8197F(v)) #define BIT_SHIFT_HW_SSN_SEQ3_8197F 0 #define BIT_MASK_HW_SSN_SEQ3_8197F 0xfff -#define BIT_HW_SSN_SEQ3_8197F(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8197F) << BIT_SHIFT_HW_SSN_SEQ3_8197F) -#define BITS_HW_SSN_SEQ3_8197F (BIT_MASK_HW_SSN_SEQ3_8197F << BIT_SHIFT_HW_SSN_SEQ3_8197F) +#define BIT_HW_SSN_SEQ3_8197F(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ3_8197F) << BIT_SHIFT_HW_SSN_SEQ3_8197F) +#define BITS_HW_SSN_SEQ3_8197F \ + (BIT_MASK_HW_SSN_SEQ3_8197F << BIT_SHIFT_HW_SSN_SEQ3_8197F) #define BIT_CLEAR_HW_SSN_SEQ3_8197F(x) ((x) & (~BITS_HW_SSN_SEQ3_8197F)) -#define BIT_GET_HW_SSN_SEQ3_8197F(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8197F) & BIT_MASK_HW_SSN_SEQ3_8197F) -#define BIT_SET_HW_SSN_SEQ3_8197F(x, v) (BIT_CLEAR_HW_SSN_SEQ3_8197F(x) | BIT_HW_SSN_SEQ3_8197F(v)) - +#define BIT_GET_HW_SSN_SEQ3_8197F(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8197F) & BIT_MASK_HW_SSN_SEQ3_8197F) +#define BIT_SET_HW_SSN_SEQ3_8197F(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ3_8197F(x) | BIT_HW_SSN_SEQ3_8197F(v)) /* 2 REG_NULL_PKT_STATUS_V1_8197F */ #define BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F 2 #define BIT_MASK_PTCL_TOTAL_PG_V1_8197F 0x1fff -#define BIT_PTCL_TOTAL_PG_V1_8197F(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V1_8197F) << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) -#define BITS_PTCL_TOTAL_PG_V1_8197F (BIT_MASK_PTCL_TOTAL_PG_V1_8197F << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) -#define BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) ((x) & (~BITS_PTCL_TOTAL_PG_V1_8197F)) -#define BIT_GET_PTCL_TOTAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) & BIT_MASK_PTCL_TOTAL_PG_V1_8197F) -#define BIT_SET_PTCL_TOTAL_PG_V1_8197F(x, v) (BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) | BIT_PTCL_TOTAL_PG_V1_8197F(v)) +#define BIT_PTCL_TOTAL_PG_V1_8197F(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V1_8197F) \ + << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) +#define BITS_PTCL_TOTAL_PG_V1_8197F \ + (BIT_MASK_PTCL_TOTAL_PG_V1_8197F << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) +#define BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) \ + ((x) & (~BITS_PTCL_TOTAL_PG_V1_8197F)) +#define BIT_GET_PTCL_TOTAL_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) & \ + BIT_MASK_PTCL_TOTAL_PG_V1_8197F) +#define BIT_SET_PTCL_TOTAL_PG_V1_8197F(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) | BIT_PTCL_TOTAL_PG_V1_8197F(v)) #define BIT_TX_NULL_1_8197F BIT(1) #define BIT_TX_NULL_0_8197F BIT(0) @@ -7590,12 +9824,20 @@ #define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F 0 #define BIT_MASK_BT_POLLUTE_PKT_CNT_8197F 0xffff -#define BIT_BT_POLLUTE_PKT_CNT_8197F(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8197F) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) -#define BITS_BT_POLLUTE_PKT_CNT_8197F (BIT_MASK_BT_POLLUTE_PKT_CNT_8197F << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) -#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8197F)) -#define BIT_GET_BT_POLLUTE_PKT_CNT_8197F(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) & BIT_MASK_BT_POLLUTE_PKT_CNT_8197F) -#define BIT_SET_BT_POLLUTE_PKT_CNT_8197F(x, v) (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) | BIT_BT_POLLUTE_PKT_CNT_8197F(v)) - +#define BIT_BT_POLLUTE_PKT_CNT_8197F(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8197F) \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) +#define BITS_BT_POLLUTE_PKT_CNT_8197F \ + (BIT_MASK_BT_POLLUTE_PKT_CNT_8197F \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) +#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) \ + ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8197F)) +#define BIT_GET_BT_POLLUTE_PKT_CNT_8197F(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) & \ + BIT_MASK_BT_POLLUTE_PKT_CNT_8197F) +#define BIT_SET_BT_POLLUTE_PKT_CNT_8197F(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) | \ + BIT_BT_POLLUTE_PKT_CNT_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -7603,12 +9845,15 @@ #define BIT_SHIFT_PTCL_DBG_8197F 0 #define BIT_MASK_PTCL_DBG_8197F 0xffffffffL -#define BIT_PTCL_DBG_8197F(x) (((x) & BIT_MASK_PTCL_DBG_8197F) << BIT_SHIFT_PTCL_DBG_8197F) -#define BITS_PTCL_DBG_8197F (BIT_MASK_PTCL_DBG_8197F << BIT_SHIFT_PTCL_DBG_8197F) +#define BIT_PTCL_DBG_8197F(x) \ + (((x) & BIT_MASK_PTCL_DBG_8197F) << BIT_SHIFT_PTCL_DBG_8197F) +#define BITS_PTCL_DBG_8197F \ + (BIT_MASK_PTCL_DBG_8197F << BIT_SHIFT_PTCL_DBG_8197F) #define BIT_CLEAR_PTCL_DBG_8197F(x) ((x) & (~BITS_PTCL_DBG_8197F)) -#define BIT_GET_PTCL_DBG_8197F(x) (((x) >> BIT_SHIFT_PTCL_DBG_8197F) & BIT_MASK_PTCL_DBG_8197F) -#define BIT_SET_PTCL_DBG_8197F(x, v) (BIT_CLEAR_PTCL_DBG_8197F(x) | BIT_PTCL_DBG_8197F(v)) - +#define BIT_GET_PTCL_DBG_8197F(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_8197F) & BIT_MASK_PTCL_DBG_8197F) +#define BIT_SET_PTCL_DBG_8197F(x, v) \ + (BIT_CLEAR_PTCL_DBG_8197F(x) | BIT_PTCL_DBG_8197F(v)) /* 2 REG_TXOP_EXTRA_CTRL_8197F */ #define BIT_TXOP_EFFICIENCY_EN_8197F BIT(0) @@ -7619,22 +9864,28 @@ #define BIT_SHIFT_TRI_HEAD_ADDR_8197F 16 #define BIT_MASK_TRI_HEAD_ADDR_8197F 0xfff -#define BIT_TRI_HEAD_ADDR_8197F(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8197F) << BIT_SHIFT_TRI_HEAD_ADDR_8197F) -#define BITS_TRI_HEAD_ADDR_8197F (BIT_MASK_TRI_HEAD_ADDR_8197F << BIT_SHIFT_TRI_HEAD_ADDR_8197F) +#define BIT_TRI_HEAD_ADDR_8197F(x) \ + (((x) & BIT_MASK_TRI_HEAD_ADDR_8197F) << BIT_SHIFT_TRI_HEAD_ADDR_8197F) +#define BITS_TRI_HEAD_ADDR_8197F \ + (BIT_MASK_TRI_HEAD_ADDR_8197F << BIT_SHIFT_TRI_HEAD_ADDR_8197F) #define BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) ((x) & (~BITS_TRI_HEAD_ADDR_8197F)) -#define BIT_GET_TRI_HEAD_ADDR_8197F(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8197F) & BIT_MASK_TRI_HEAD_ADDR_8197F) -#define BIT_SET_TRI_HEAD_ADDR_8197F(x, v) (BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) | BIT_TRI_HEAD_ADDR_8197F(v)) +#define BIT_GET_TRI_HEAD_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8197F) & BIT_MASK_TRI_HEAD_ADDR_8197F) +#define BIT_SET_TRI_HEAD_ADDR_8197F(x, v) \ + (BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) | BIT_TRI_HEAD_ADDR_8197F(v)) #define BIT_DROP_TH_EN_8197F BIT(8) #define BIT_SHIFT_DROP_TH_8197F 0 #define BIT_MASK_DROP_TH_8197F 0xff -#define BIT_DROP_TH_8197F(x) (((x) & BIT_MASK_DROP_TH_8197F) << BIT_SHIFT_DROP_TH_8197F) +#define BIT_DROP_TH_8197F(x) \ + (((x) & BIT_MASK_DROP_TH_8197F) << BIT_SHIFT_DROP_TH_8197F) #define BITS_DROP_TH_8197F (BIT_MASK_DROP_TH_8197F << BIT_SHIFT_DROP_TH_8197F) #define BIT_CLEAR_DROP_TH_8197F(x) ((x) & (~BITS_DROP_TH_8197F)) -#define BIT_GET_DROP_TH_8197F(x) (((x) >> BIT_SHIFT_DROP_TH_8197F) & BIT_MASK_DROP_TH_8197F) -#define BIT_SET_DROP_TH_8197F(x, v) (BIT_CLEAR_DROP_TH_8197F(x) | BIT_DROP_TH_8197F(v)) - +#define BIT_GET_DROP_TH_8197F(x) \ + (((x) >> BIT_SHIFT_DROP_TH_8197F) & BIT_MASK_DROP_TH_8197F) +#define BIT_SET_DROP_TH_8197F(x, v) \ + (BIT_CLEAR_DROP_TH_8197F(x) | BIT_DROP_TH_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -7650,220 +9901,293 @@ #define BIT_SHIFT_GTAB_ID_8197F 28 #define BIT_MASK_GTAB_ID_8197F 0x7 -#define BIT_GTAB_ID_8197F(x) (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) +#define BIT_GTAB_ID_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) #define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F) #define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F)) -#define BIT_GET_GTAB_ID_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) -#define BIT_SET_GTAB_ID_8197F(x, v) (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) - +#define BIT_GET_GTAB_ID_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) +#define BIT_SET_GTAB_ID_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) #define BIT_SHIFT_AC1_PKT_INFO_8197F 16 #define BIT_MASK_AC1_PKT_INFO_8197F 0xfff -#define BIT_AC1_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC1_PKT_INFO_8197F) << BIT_SHIFT_AC1_PKT_INFO_8197F) -#define BITS_AC1_PKT_INFO_8197F (BIT_MASK_AC1_PKT_INFO_8197F << BIT_SHIFT_AC1_PKT_INFO_8197F) +#define BIT_AC1_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC1_PKT_INFO_8197F) << BIT_SHIFT_AC1_PKT_INFO_8197F) +#define BITS_AC1_PKT_INFO_8197F \ + (BIT_MASK_AC1_PKT_INFO_8197F << BIT_SHIFT_AC1_PKT_INFO_8197F) #define BIT_CLEAR_AC1_PKT_INFO_8197F(x) ((x) & (~BITS_AC1_PKT_INFO_8197F)) -#define BIT_GET_AC1_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8197F) & BIT_MASK_AC1_PKT_INFO_8197F) -#define BIT_SET_AC1_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC1_PKT_INFO_8197F(x) | BIT_AC1_PKT_INFO_8197F(v)) +#define BIT_GET_AC1_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC1_PKT_INFO_8197F) & BIT_MASK_AC1_PKT_INFO_8197F) +#define BIT_SET_AC1_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC1_PKT_INFO_8197F(x) | BIT_AC1_PKT_INFO_8197F(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8197F 12 #define BIT_MASK_GTAB_ID_V1_8197F 0x7 -#define BIT_GTAB_ID_V1_8197F(x) (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) -#define BITS_GTAB_ID_V1_8197F (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BIT_GTAB_ID_V1_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BITS_GTAB_ID_V1_8197F \ + (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) #define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F)) -#define BIT_GET_GTAB_ID_V1_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) -#define BIT_SET_GTAB_ID_V1_8197F(x, v) (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) - +#define BIT_GET_GTAB_ID_V1_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) +#define BIT_SET_GTAB_ID_V1_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) #define BIT_SHIFT_AC0_PKT_INFO_8197F 0 #define BIT_MASK_AC0_PKT_INFO_8197F 0xfff -#define BIT_AC0_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC0_PKT_INFO_8197F) << BIT_SHIFT_AC0_PKT_INFO_8197F) -#define BITS_AC0_PKT_INFO_8197F (BIT_MASK_AC0_PKT_INFO_8197F << BIT_SHIFT_AC0_PKT_INFO_8197F) +#define BIT_AC0_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC0_PKT_INFO_8197F) << BIT_SHIFT_AC0_PKT_INFO_8197F) +#define BITS_AC0_PKT_INFO_8197F \ + (BIT_MASK_AC0_PKT_INFO_8197F << BIT_SHIFT_AC0_PKT_INFO_8197F) #define BIT_CLEAR_AC0_PKT_INFO_8197F(x) ((x) & (~BITS_AC0_PKT_INFO_8197F)) -#define BIT_GET_AC0_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8197F) & BIT_MASK_AC0_PKT_INFO_8197F) -#define BIT_SET_AC0_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC0_PKT_INFO_8197F(x) | BIT_AC0_PKT_INFO_8197F(v)) - +#define BIT_GET_AC0_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC0_PKT_INFO_8197F) & BIT_MASK_AC0_PKT_INFO_8197F) +#define BIT_SET_AC0_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC0_PKT_INFO_8197F(x) | BIT_AC0_PKT_INFO_8197F(v)) /* 2 REG_Q2_Q3_INFO_8197F */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31) #define BIT_SHIFT_GTAB_ID_8197F 28 #define BIT_MASK_GTAB_ID_8197F 0x7 -#define BIT_GTAB_ID_8197F(x) (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) +#define BIT_GTAB_ID_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) #define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F) #define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F)) -#define BIT_GET_GTAB_ID_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) -#define BIT_SET_GTAB_ID_8197F(x, v) (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) - +#define BIT_GET_GTAB_ID_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) +#define BIT_SET_GTAB_ID_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) #define BIT_SHIFT_AC3_PKT_INFO_8197F 16 #define BIT_MASK_AC3_PKT_INFO_8197F 0xfff -#define BIT_AC3_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC3_PKT_INFO_8197F) << BIT_SHIFT_AC3_PKT_INFO_8197F) -#define BITS_AC3_PKT_INFO_8197F (BIT_MASK_AC3_PKT_INFO_8197F << BIT_SHIFT_AC3_PKT_INFO_8197F) +#define BIT_AC3_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC3_PKT_INFO_8197F) << BIT_SHIFT_AC3_PKT_INFO_8197F) +#define BITS_AC3_PKT_INFO_8197F \ + (BIT_MASK_AC3_PKT_INFO_8197F << BIT_SHIFT_AC3_PKT_INFO_8197F) #define BIT_CLEAR_AC3_PKT_INFO_8197F(x) ((x) & (~BITS_AC3_PKT_INFO_8197F)) -#define BIT_GET_AC3_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8197F) & BIT_MASK_AC3_PKT_INFO_8197F) -#define BIT_SET_AC3_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC3_PKT_INFO_8197F(x) | BIT_AC3_PKT_INFO_8197F(v)) +#define BIT_GET_AC3_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC3_PKT_INFO_8197F) & BIT_MASK_AC3_PKT_INFO_8197F) +#define BIT_SET_AC3_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC3_PKT_INFO_8197F(x) | BIT_AC3_PKT_INFO_8197F(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8197F 12 #define BIT_MASK_GTAB_ID_V1_8197F 0x7 -#define BIT_GTAB_ID_V1_8197F(x) (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) -#define BITS_GTAB_ID_V1_8197F (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BIT_GTAB_ID_V1_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BITS_GTAB_ID_V1_8197F \ + (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) #define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F)) -#define BIT_GET_GTAB_ID_V1_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) -#define BIT_SET_GTAB_ID_V1_8197F(x, v) (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) - +#define BIT_GET_GTAB_ID_V1_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) +#define BIT_SET_GTAB_ID_V1_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) #define BIT_SHIFT_AC2_PKT_INFO_8197F 0 #define BIT_MASK_AC2_PKT_INFO_8197F 0xfff -#define BIT_AC2_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC2_PKT_INFO_8197F) << BIT_SHIFT_AC2_PKT_INFO_8197F) -#define BITS_AC2_PKT_INFO_8197F (BIT_MASK_AC2_PKT_INFO_8197F << BIT_SHIFT_AC2_PKT_INFO_8197F) +#define BIT_AC2_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC2_PKT_INFO_8197F) << BIT_SHIFT_AC2_PKT_INFO_8197F) +#define BITS_AC2_PKT_INFO_8197F \ + (BIT_MASK_AC2_PKT_INFO_8197F << BIT_SHIFT_AC2_PKT_INFO_8197F) #define BIT_CLEAR_AC2_PKT_INFO_8197F(x) ((x) & (~BITS_AC2_PKT_INFO_8197F)) -#define BIT_GET_AC2_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8197F) & BIT_MASK_AC2_PKT_INFO_8197F) -#define BIT_SET_AC2_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC2_PKT_INFO_8197F(x) | BIT_AC2_PKT_INFO_8197F(v)) - +#define BIT_GET_AC2_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC2_PKT_INFO_8197F) & BIT_MASK_AC2_PKT_INFO_8197F) +#define BIT_SET_AC2_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC2_PKT_INFO_8197F(x) | BIT_AC2_PKT_INFO_8197F(v)) /* 2 REG_Q4_Q5_INFO_8197F */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31) #define BIT_SHIFT_GTAB_ID_8197F 28 #define BIT_MASK_GTAB_ID_8197F 0x7 -#define BIT_GTAB_ID_8197F(x) (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) +#define BIT_GTAB_ID_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) #define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F) #define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F)) -#define BIT_GET_GTAB_ID_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) -#define BIT_SET_GTAB_ID_8197F(x, v) (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) - +#define BIT_GET_GTAB_ID_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) +#define BIT_SET_GTAB_ID_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) #define BIT_SHIFT_AC5_PKT_INFO_8197F 16 #define BIT_MASK_AC5_PKT_INFO_8197F 0xfff -#define BIT_AC5_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC5_PKT_INFO_8197F) << BIT_SHIFT_AC5_PKT_INFO_8197F) -#define BITS_AC5_PKT_INFO_8197F (BIT_MASK_AC5_PKT_INFO_8197F << BIT_SHIFT_AC5_PKT_INFO_8197F) +#define BIT_AC5_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC5_PKT_INFO_8197F) << BIT_SHIFT_AC5_PKT_INFO_8197F) +#define BITS_AC5_PKT_INFO_8197F \ + (BIT_MASK_AC5_PKT_INFO_8197F << BIT_SHIFT_AC5_PKT_INFO_8197F) #define BIT_CLEAR_AC5_PKT_INFO_8197F(x) ((x) & (~BITS_AC5_PKT_INFO_8197F)) -#define BIT_GET_AC5_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8197F) & BIT_MASK_AC5_PKT_INFO_8197F) -#define BIT_SET_AC5_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC5_PKT_INFO_8197F(x) | BIT_AC5_PKT_INFO_8197F(v)) +#define BIT_GET_AC5_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC5_PKT_INFO_8197F) & BIT_MASK_AC5_PKT_INFO_8197F) +#define BIT_SET_AC5_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC5_PKT_INFO_8197F(x) | BIT_AC5_PKT_INFO_8197F(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8197F 12 #define BIT_MASK_GTAB_ID_V1_8197F 0x7 -#define BIT_GTAB_ID_V1_8197F(x) (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) -#define BITS_GTAB_ID_V1_8197F (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BIT_GTAB_ID_V1_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BITS_GTAB_ID_V1_8197F \ + (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) #define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F)) -#define BIT_GET_GTAB_ID_V1_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) -#define BIT_SET_GTAB_ID_V1_8197F(x, v) (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) - +#define BIT_GET_GTAB_ID_V1_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) +#define BIT_SET_GTAB_ID_V1_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) #define BIT_SHIFT_AC4_PKT_INFO_8197F 0 #define BIT_MASK_AC4_PKT_INFO_8197F 0xfff -#define BIT_AC4_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC4_PKT_INFO_8197F) << BIT_SHIFT_AC4_PKT_INFO_8197F) -#define BITS_AC4_PKT_INFO_8197F (BIT_MASK_AC4_PKT_INFO_8197F << BIT_SHIFT_AC4_PKT_INFO_8197F) +#define BIT_AC4_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC4_PKT_INFO_8197F) << BIT_SHIFT_AC4_PKT_INFO_8197F) +#define BITS_AC4_PKT_INFO_8197F \ + (BIT_MASK_AC4_PKT_INFO_8197F << BIT_SHIFT_AC4_PKT_INFO_8197F) #define BIT_CLEAR_AC4_PKT_INFO_8197F(x) ((x) & (~BITS_AC4_PKT_INFO_8197F)) -#define BIT_GET_AC4_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8197F) & BIT_MASK_AC4_PKT_INFO_8197F) -#define BIT_SET_AC4_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC4_PKT_INFO_8197F(x) | BIT_AC4_PKT_INFO_8197F(v)) - +#define BIT_GET_AC4_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC4_PKT_INFO_8197F) & BIT_MASK_AC4_PKT_INFO_8197F) +#define BIT_SET_AC4_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC4_PKT_INFO_8197F(x) | BIT_AC4_PKT_INFO_8197F(v)) /* 2 REG_Q6_Q7_INFO_8197F */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31) #define BIT_SHIFT_GTAB_ID_8197F 28 #define BIT_MASK_GTAB_ID_8197F 0x7 -#define BIT_GTAB_ID_8197F(x) (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) +#define BIT_GTAB_ID_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) #define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F) #define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F)) -#define BIT_GET_GTAB_ID_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) -#define BIT_SET_GTAB_ID_8197F(x, v) (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) - +#define BIT_GET_GTAB_ID_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) +#define BIT_SET_GTAB_ID_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) #define BIT_SHIFT_AC7_PKT_INFO_8197F 16 #define BIT_MASK_AC7_PKT_INFO_8197F 0xfff -#define BIT_AC7_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC7_PKT_INFO_8197F) << BIT_SHIFT_AC7_PKT_INFO_8197F) -#define BITS_AC7_PKT_INFO_8197F (BIT_MASK_AC7_PKT_INFO_8197F << BIT_SHIFT_AC7_PKT_INFO_8197F) +#define BIT_AC7_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC7_PKT_INFO_8197F) << BIT_SHIFT_AC7_PKT_INFO_8197F) +#define BITS_AC7_PKT_INFO_8197F \ + (BIT_MASK_AC7_PKT_INFO_8197F << BIT_SHIFT_AC7_PKT_INFO_8197F) #define BIT_CLEAR_AC7_PKT_INFO_8197F(x) ((x) & (~BITS_AC7_PKT_INFO_8197F)) -#define BIT_GET_AC7_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8197F) & BIT_MASK_AC7_PKT_INFO_8197F) -#define BIT_SET_AC7_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC7_PKT_INFO_8197F(x) | BIT_AC7_PKT_INFO_8197F(v)) +#define BIT_GET_AC7_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC7_PKT_INFO_8197F) & BIT_MASK_AC7_PKT_INFO_8197F) +#define BIT_SET_AC7_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC7_PKT_INFO_8197F(x) | BIT_AC7_PKT_INFO_8197F(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8197F 12 #define BIT_MASK_GTAB_ID_V1_8197F 0x7 -#define BIT_GTAB_ID_V1_8197F(x) (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) -#define BITS_GTAB_ID_V1_8197F (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BIT_GTAB_ID_V1_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BITS_GTAB_ID_V1_8197F \ + (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) #define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F)) -#define BIT_GET_GTAB_ID_V1_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) -#define BIT_SET_GTAB_ID_V1_8197F(x, v) (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) - +#define BIT_GET_GTAB_ID_V1_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) +#define BIT_SET_GTAB_ID_V1_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) #define BIT_SHIFT_AC6_PKT_INFO_8197F 0 #define BIT_MASK_AC6_PKT_INFO_8197F 0xfff -#define BIT_AC6_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC6_PKT_INFO_8197F) << BIT_SHIFT_AC6_PKT_INFO_8197F) -#define BITS_AC6_PKT_INFO_8197F (BIT_MASK_AC6_PKT_INFO_8197F << BIT_SHIFT_AC6_PKT_INFO_8197F) +#define BIT_AC6_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC6_PKT_INFO_8197F) << BIT_SHIFT_AC6_PKT_INFO_8197F) +#define BITS_AC6_PKT_INFO_8197F \ + (BIT_MASK_AC6_PKT_INFO_8197F << BIT_SHIFT_AC6_PKT_INFO_8197F) #define BIT_CLEAR_AC6_PKT_INFO_8197F(x) ((x) & (~BITS_AC6_PKT_INFO_8197F)) -#define BIT_GET_AC6_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8197F) & BIT_MASK_AC6_PKT_INFO_8197F) -#define BIT_SET_AC6_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC6_PKT_INFO_8197F(x) | BIT_AC6_PKT_INFO_8197F(v)) - +#define BIT_GET_AC6_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC6_PKT_INFO_8197F) & BIT_MASK_AC6_PKT_INFO_8197F) +#define BIT_SET_AC6_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC6_PKT_INFO_8197F(x) | BIT_AC6_PKT_INFO_8197F(v)) /* 2 REG_MGQ_HIQ_INFO_8197F */ #define BIT_SHIFT_HIQ_PKT_INFO_8197F 16 #define BIT_MASK_HIQ_PKT_INFO_8197F 0xfff -#define BIT_HIQ_PKT_INFO_8197F(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8197F) << BIT_SHIFT_HIQ_PKT_INFO_8197F) -#define BITS_HIQ_PKT_INFO_8197F (BIT_MASK_HIQ_PKT_INFO_8197F << BIT_SHIFT_HIQ_PKT_INFO_8197F) +#define BIT_HIQ_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_HIQ_PKT_INFO_8197F) << BIT_SHIFT_HIQ_PKT_INFO_8197F) +#define BITS_HIQ_PKT_INFO_8197F \ + (BIT_MASK_HIQ_PKT_INFO_8197F << BIT_SHIFT_HIQ_PKT_INFO_8197F) #define BIT_CLEAR_HIQ_PKT_INFO_8197F(x) ((x) & (~BITS_HIQ_PKT_INFO_8197F)) -#define BIT_GET_HIQ_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8197F) & BIT_MASK_HIQ_PKT_INFO_8197F) -#define BIT_SET_HIQ_PKT_INFO_8197F(x, v) (BIT_CLEAR_HIQ_PKT_INFO_8197F(x) | BIT_HIQ_PKT_INFO_8197F(v)) - +#define BIT_GET_HIQ_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8197F) & BIT_MASK_HIQ_PKT_INFO_8197F) +#define BIT_SET_HIQ_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_HIQ_PKT_INFO_8197F(x) | BIT_HIQ_PKT_INFO_8197F(v)) #define BIT_SHIFT_MGQ_PKT_INFO_8197F 0 #define BIT_MASK_MGQ_PKT_INFO_8197F 0xfff -#define BIT_MGQ_PKT_INFO_8197F(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8197F) << BIT_SHIFT_MGQ_PKT_INFO_8197F) -#define BITS_MGQ_PKT_INFO_8197F (BIT_MASK_MGQ_PKT_INFO_8197F << BIT_SHIFT_MGQ_PKT_INFO_8197F) +#define BIT_MGQ_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_MGQ_PKT_INFO_8197F) << BIT_SHIFT_MGQ_PKT_INFO_8197F) +#define BITS_MGQ_PKT_INFO_8197F \ + (BIT_MASK_MGQ_PKT_INFO_8197F << BIT_SHIFT_MGQ_PKT_INFO_8197F) #define BIT_CLEAR_MGQ_PKT_INFO_8197F(x) ((x) & (~BITS_MGQ_PKT_INFO_8197F)) -#define BIT_GET_MGQ_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8197F) & BIT_MASK_MGQ_PKT_INFO_8197F) -#define BIT_SET_MGQ_PKT_INFO_8197F(x, v) (BIT_CLEAR_MGQ_PKT_INFO_8197F(x) | BIT_MGQ_PKT_INFO_8197F(v)) - +#define BIT_GET_MGQ_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8197F) & BIT_MASK_MGQ_PKT_INFO_8197F) +#define BIT_SET_MGQ_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_MGQ_PKT_INFO_8197F(x) | BIT_MGQ_PKT_INFO_8197F(v)) /* 2 REG_CMDQ_BCNQ_INFO_8197F */ #define BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F 16 #define BIT_MASK_BCNQ_PKT_INFO_V1_8197F 0xfff -#define BIT_BCNQ_PKT_INFO_V1_8197F(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_V1_8197F) << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) -#define BITS_BCNQ_PKT_INFO_V1_8197F (BIT_MASK_BCNQ_PKT_INFO_V1_8197F << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) -#define BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) ((x) & (~BITS_BCNQ_PKT_INFO_V1_8197F)) -#define BIT_GET_BCNQ_PKT_INFO_V1_8197F(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) & BIT_MASK_BCNQ_PKT_INFO_V1_8197F) -#define BIT_SET_BCNQ_PKT_INFO_V1_8197F(x, v) (BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) | BIT_BCNQ_PKT_INFO_V1_8197F(v)) - +#define BIT_BCNQ_PKT_INFO_V1_8197F(x) \ + (((x) & BIT_MASK_BCNQ_PKT_INFO_V1_8197F) \ + << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) +#define BITS_BCNQ_PKT_INFO_V1_8197F \ + (BIT_MASK_BCNQ_PKT_INFO_V1_8197F << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) +#define BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) \ + ((x) & (~BITS_BCNQ_PKT_INFO_V1_8197F)) +#define BIT_GET_BCNQ_PKT_INFO_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) & \ + BIT_MASK_BCNQ_PKT_INFO_V1_8197F) +#define BIT_SET_BCNQ_PKT_INFO_V1_8197F(x, v) \ + (BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) | BIT_BCNQ_PKT_INFO_V1_8197F(v)) #define BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F 0 #define BIT_MASK_CMDQ_PKT_INFO_V1_8197F 0xfff -#define BIT_CMDQ_PKT_INFO_V1_8197F(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_V1_8197F) << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) -#define BITS_CMDQ_PKT_INFO_V1_8197F (BIT_MASK_CMDQ_PKT_INFO_V1_8197F << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) -#define BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) ((x) & (~BITS_CMDQ_PKT_INFO_V1_8197F)) -#define BIT_GET_CMDQ_PKT_INFO_V1_8197F(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) & BIT_MASK_CMDQ_PKT_INFO_V1_8197F) -#define BIT_SET_CMDQ_PKT_INFO_V1_8197F(x, v) (BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) | BIT_CMDQ_PKT_INFO_V1_8197F(v)) - +#define BIT_CMDQ_PKT_INFO_V1_8197F(x) \ + (((x) & BIT_MASK_CMDQ_PKT_INFO_V1_8197F) \ + << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) +#define BITS_CMDQ_PKT_INFO_V1_8197F \ + (BIT_MASK_CMDQ_PKT_INFO_V1_8197F << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) +#define BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) \ + ((x) & (~BITS_CMDQ_PKT_INFO_V1_8197F)) +#define BIT_GET_CMDQ_PKT_INFO_V1_8197F(x) \ + (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) & \ + BIT_MASK_CMDQ_PKT_INFO_V1_8197F) +#define BIT_SET_CMDQ_PKT_INFO_V1_8197F(x, v) \ + (BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) | BIT_CMDQ_PKT_INFO_V1_8197F(v)) /* 2 REG_USEREG_SETTING_8197F */ #define BIT_NDPA_USEREG_8197F BIT(21) #define BIT_SHIFT_RETRY_USEREG_8197F 19 #define BIT_MASK_RETRY_USEREG_8197F 0x3 -#define BIT_RETRY_USEREG_8197F(x) (((x) & BIT_MASK_RETRY_USEREG_8197F) << BIT_SHIFT_RETRY_USEREG_8197F) -#define BITS_RETRY_USEREG_8197F (BIT_MASK_RETRY_USEREG_8197F << BIT_SHIFT_RETRY_USEREG_8197F) +#define BIT_RETRY_USEREG_8197F(x) \ + (((x) & BIT_MASK_RETRY_USEREG_8197F) << BIT_SHIFT_RETRY_USEREG_8197F) +#define BITS_RETRY_USEREG_8197F \ + (BIT_MASK_RETRY_USEREG_8197F << BIT_SHIFT_RETRY_USEREG_8197F) #define BIT_CLEAR_RETRY_USEREG_8197F(x) ((x) & (~BITS_RETRY_USEREG_8197F)) -#define BIT_GET_RETRY_USEREG_8197F(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8197F) & BIT_MASK_RETRY_USEREG_8197F) -#define BIT_SET_RETRY_USEREG_8197F(x, v) (BIT_CLEAR_RETRY_USEREG_8197F(x) | BIT_RETRY_USEREG_8197F(v)) - +#define BIT_GET_RETRY_USEREG_8197F(x) \ + (((x) >> BIT_SHIFT_RETRY_USEREG_8197F) & BIT_MASK_RETRY_USEREG_8197F) +#define BIT_SET_RETRY_USEREG_8197F(x, v) \ + (BIT_CLEAR_RETRY_USEREG_8197F(x) | BIT_RETRY_USEREG_8197F(v)) #define BIT_SHIFT_TRYPKT_USEREG_8197F 17 #define BIT_MASK_TRYPKT_USEREG_8197F 0x3 -#define BIT_TRYPKT_USEREG_8197F(x) (((x) & BIT_MASK_TRYPKT_USEREG_8197F) << BIT_SHIFT_TRYPKT_USEREG_8197F) -#define BITS_TRYPKT_USEREG_8197F (BIT_MASK_TRYPKT_USEREG_8197F << BIT_SHIFT_TRYPKT_USEREG_8197F) +#define BIT_TRYPKT_USEREG_8197F(x) \ + (((x) & BIT_MASK_TRYPKT_USEREG_8197F) << BIT_SHIFT_TRYPKT_USEREG_8197F) +#define BITS_TRYPKT_USEREG_8197F \ + (BIT_MASK_TRYPKT_USEREG_8197F << BIT_SHIFT_TRYPKT_USEREG_8197F) #define BIT_CLEAR_TRYPKT_USEREG_8197F(x) ((x) & (~BITS_TRYPKT_USEREG_8197F)) -#define BIT_GET_TRYPKT_USEREG_8197F(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8197F) & BIT_MASK_TRYPKT_USEREG_8197F) -#define BIT_SET_TRYPKT_USEREG_8197F(x, v) (BIT_CLEAR_TRYPKT_USEREG_8197F(x) | BIT_TRYPKT_USEREG_8197F(v)) +#define BIT_GET_TRYPKT_USEREG_8197F(x) \ + (((x) >> BIT_SHIFT_TRYPKT_USEREG_8197F) & BIT_MASK_TRYPKT_USEREG_8197F) +#define BIT_SET_TRYPKT_USEREG_8197F(x, v) \ + (BIT_CLEAR_TRYPKT_USEREG_8197F(x) | BIT_TRYPKT_USEREG_8197F(v)) #define BIT_CTLPKT_USEREG_8197F BIT(16) @@ -7871,12 +10195,15 @@ #define BIT_SHIFT_AESIV_OFFSET_8197F 0 #define BIT_MASK_AESIV_OFFSET_8197F 0xfff -#define BIT_AESIV_OFFSET_8197F(x) (((x) & BIT_MASK_AESIV_OFFSET_8197F) << BIT_SHIFT_AESIV_OFFSET_8197F) -#define BITS_AESIV_OFFSET_8197F (BIT_MASK_AESIV_OFFSET_8197F << BIT_SHIFT_AESIV_OFFSET_8197F) +#define BIT_AESIV_OFFSET_8197F(x) \ + (((x) & BIT_MASK_AESIV_OFFSET_8197F) << BIT_SHIFT_AESIV_OFFSET_8197F) +#define BITS_AESIV_OFFSET_8197F \ + (BIT_MASK_AESIV_OFFSET_8197F << BIT_SHIFT_AESIV_OFFSET_8197F) #define BIT_CLEAR_AESIV_OFFSET_8197F(x) ((x) & (~BITS_AESIV_OFFSET_8197F)) -#define BIT_GET_AESIV_OFFSET_8197F(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8197F) & BIT_MASK_AESIV_OFFSET_8197F) -#define BIT_SET_AESIV_OFFSET_8197F(x, v) (BIT_CLEAR_AESIV_OFFSET_8197F(x) | BIT_AESIV_OFFSET_8197F(v)) - +#define BIT_GET_AESIV_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_AESIV_OFFSET_8197F) & BIT_MASK_AESIV_OFFSET_8197F) +#define BIT_SET_AESIV_OFFSET_8197F(x, v) \ + (BIT_CLEAR_AESIV_OFFSET_8197F(x) | BIT_AESIV_OFFSET_8197F(v)) /* 2 REG_BF0_TIME_SETTING_8197F */ #define BIT_BF0_TIMER_SET_8197F BIT(31) @@ -7886,21 +10213,30 @@ #define BIT_SHIFT_BF0_PRETIME_OVER_8197F 16 #define BIT_MASK_BF0_PRETIME_OVER_8197F 0xfff -#define BIT_BF0_PRETIME_OVER_8197F(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8197F) << BIT_SHIFT_BF0_PRETIME_OVER_8197F) -#define BITS_BF0_PRETIME_OVER_8197F (BIT_MASK_BF0_PRETIME_OVER_8197F << BIT_SHIFT_BF0_PRETIME_OVER_8197F) -#define BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) ((x) & (~BITS_BF0_PRETIME_OVER_8197F)) -#define BIT_GET_BF0_PRETIME_OVER_8197F(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8197F) & BIT_MASK_BF0_PRETIME_OVER_8197F) -#define BIT_SET_BF0_PRETIME_OVER_8197F(x, v) (BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) | BIT_BF0_PRETIME_OVER_8197F(v)) - +#define BIT_BF0_PRETIME_OVER_8197F(x) \ + (((x) & BIT_MASK_BF0_PRETIME_OVER_8197F) \ + << BIT_SHIFT_BF0_PRETIME_OVER_8197F) +#define BITS_BF0_PRETIME_OVER_8197F \ + (BIT_MASK_BF0_PRETIME_OVER_8197F << BIT_SHIFT_BF0_PRETIME_OVER_8197F) +#define BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) \ + ((x) & (~BITS_BF0_PRETIME_OVER_8197F)) +#define BIT_GET_BF0_PRETIME_OVER_8197F(x) \ + (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8197F) & \ + BIT_MASK_BF0_PRETIME_OVER_8197F) +#define BIT_SET_BF0_PRETIME_OVER_8197F(x, v) \ + (BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) | BIT_BF0_PRETIME_OVER_8197F(v)) #define BIT_SHIFT_BF0_LIFETIME_8197F 0 #define BIT_MASK_BF0_LIFETIME_8197F 0xffff -#define BIT_BF0_LIFETIME_8197F(x) (((x) & BIT_MASK_BF0_LIFETIME_8197F) << BIT_SHIFT_BF0_LIFETIME_8197F) -#define BITS_BF0_LIFETIME_8197F (BIT_MASK_BF0_LIFETIME_8197F << BIT_SHIFT_BF0_LIFETIME_8197F) +#define BIT_BF0_LIFETIME_8197F(x) \ + (((x) & BIT_MASK_BF0_LIFETIME_8197F) << BIT_SHIFT_BF0_LIFETIME_8197F) +#define BITS_BF0_LIFETIME_8197F \ + (BIT_MASK_BF0_LIFETIME_8197F << BIT_SHIFT_BF0_LIFETIME_8197F) #define BIT_CLEAR_BF0_LIFETIME_8197F(x) ((x) & (~BITS_BF0_LIFETIME_8197F)) -#define BIT_GET_BF0_LIFETIME_8197F(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8197F) & BIT_MASK_BF0_LIFETIME_8197F) -#define BIT_SET_BF0_LIFETIME_8197F(x, v) (BIT_CLEAR_BF0_LIFETIME_8197F(x) | BIT_BF0_LIFETIME_8197F(v)) - +#define BIT_GET_BF0_LIFETIME_8197F(x) \ + (((x) >> BIT_SHIFT_BF0_LIFETIME_8197F) & BIT_MASK_BF0_LIFETIME_8197F) +#define BIT_SET_BF0_LIFETIME_8197F(x, v) \ + (BIT_CLEAR_BF0_LIFETIME_8197F(x) | BIT_BF0_LIFETIME_8197F(v)) /* 2 REG_BF1_TIME_SETTING_8197F */ #define BIT_BF1_TIMER_SET_8197F BIT(31) @@ -7910,21 +10246,30 @@ #define BIT_SHIFT_BF1_PRETIME_OVER_8197F 16 #define BIT_MASK_BF1_PRETIME_OVER_8197F 0xfff -#define BIT_BF1_PRETIME_OVER_8197F(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8197F) << BIT_SHIFT_BF1_PRETIME_OVER_8197F) -#define BITS_BF1_PRETIME_OVER_8197F (BIT_MASK_BF1_PRETIME_OVER_8197F << BIT_SHIFT_BF1_PRETIME_OVER_8197F) -#define BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) ((x) & (~BITS_BF1_PRETIME_OVER_8197F)) -#define BIT_GET_BF1_PRETIME_OVER_8197F(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8197F) & BIT_MASK_BF1_PRETIME_OVER_8197F) -#define BIT_SET_BF1_PRETIME_OVER_8197F(x, v) (BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) | BIT_BF1_PRETIME_OVER_8197F(v)) - +#define BIT_BF1_PRETIME_OVER_8197F(x) \ + (((x) & BIT_MASK_BF1_PRETIME_OVER_8197F) \ + << BIT_SHIFT_BF1_PRETIME_OVER_8197F) +#define BITS_BF1_PRETIME_OVER_8197F \ + (BIT_MASK_BF1_PRETIME_OVER_8197F << BIT_SHIFT_BF1_PRETIME_OVER_8197F) +#define BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) \ + ((x) & (~BITS_BF1_PRETIME_OVER_8197F)) +#define BIT_GET_BF1_PRETIME_OVER_8197F(x) \ + (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8197F) & \ + BIT_MASK_BF1_PRETIME_OVER_8197F) +#define BIT_SET_BF1_PRETIME_OVER_8197F(x, v) \ + (BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) | BIT_BF1_PRETIME_OVER_8197F(v)) #define BIT_SHIFT_BF1_LIFETIME_8197F 0 #define BIT_MASK_BF1_LIFETIME_8197F 0xffff -#define BIT_BF1_LIFETIME_8197F(x) (((x) & BIT_MASK_BF1_LIFETIME_8197F) << BIT_SHIFT_BF1_LIFETIME_8197F) -#define BITS_BF1_LIFETIME_8197F (BIT_MASK_BF1_LIFETIME_8197F << BIT_SHIFT_BF1_LIFETIME_8197F) +#define BIT_BF1_LIFETIME_8197F(x) \ + (((x) & BIT_MASK_BF1_LIFETIME_8197F) << BIT_SHIFT_BF1_LIFETIME_8197F) +#define BITS_BF1_LIFETIME_8197F \ + (BIT_MASK_BF1_LIFETIME_8197F << BIT_SHIFT_BF1_LIFETIME_8197F) #define BIT_CLEAR_BF1_LIFETIME_8197F(x) ((x) & (~BITS_BF1_LIFETIME_8197F)) -#define BIT_GET_BF1_LIFETIME_8197F(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8197F) & BIT_MASK_BF1_LIFETIME_8197F) -#define BIT_SET_BF1_LIFETIME_8197F(x, v) (BIT_CLEAR_BF1_LIFETIME_8197F(x) | BIT_BF1_LIFETIME_8197F(v)) - +#define BIT_GET_BF1_LIFETIME_8197F(x) \ + (((x) >> BIT_SHIFT_BF1_LIFETIME_8197F) & BIT_MASK_BF1_LIFETIME_8197F) +#define BIT_SET_BF1_LIFETIME_8197F(x, v) \ + (BIT_CLEAR_BF1_LIFETIME_8197F(x) | BIT_BF1_LIFETIME_8197F(v)) /* 2 REG_BF_TIMEOUT_EN_8197F */ #define BIT_EN_VHT_LDPC_8197F BIT(9) @@ -7936,264 +10281,434 @@ #define BIT_SHIFT_MACID31_0_RELEASE_8197F 0 #define BIT_MASK_MACID31_0_RELEASE_8197F 0xffffffffL -#define BIT_MACID31_0_RELEASE_8197F(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8197F) << BIT_SHIFT_MACID31_0_RELEASE_8197F) -#define BITS_MACID31_0_RELEASE_8197F (BIT_MASK_MACID31_0_RELEASE_8197F << BIT_SHIFT_MACID31_0_RELEASE_8197F) -#define BIT_CLEAR_MACID31_0_RELEASE_8197F(x) ((x) & (~BITS_MACID31_0_RELEASE_8197F)) -#define BIT_GET_MACID31_0_RELEASE_8197F(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8197F) & BIT_MASK_MACID31_0_RELEASE_8197F) -#define BIT_SET_MACID31_0_RELEASE_8197F(x, v) (BIT_CLEAR_MACID31_0_RELEASE_8197F(x) | BIT_MACID31_0_RELEASE_8197F(v)) - +#define BIT_MACID31_0_RELEASE_8197F(x) \ + (((x) & BIT_MASK_MACID31_0_RELEASE_8197F) \ + << BIT_SHIFT_MACID31_0_RELEASE_8197F) +#define BITS_MACID31_0_RELEASE_8197F \ + (BIT_MASK_MACID31_0_RELEASE_8197F << BIT_SHIFT_MACID31_0_RELEASE_8197F) +#define BIT_CLEAR_MACID31_0_RELEASE_8197F(x) \ + ((x) & (~BITS_MACID31_0_RELEASE_8197F)) +#define BIT_GET_MACID31_0_RELEASE_8197F(x) \ + (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8197F) & \ + BIT_MASK_MACID31_0_RELEASE_8197F) +#define BIT_SET_MACID31_0_RELEASE_8197F(x, v) \ + (BIT_CLEAR_MACID31_0_RELEASE_8197F(x) | BIT_MACID31_0_RELEASE_8197F(v)) /* 2 REG_MACID_RELEASE1_8197F */ #define BIT_SHIFT_MACID63_32_RELEASE_8197F 0 #define BIT_MASK_MACID63_32_RELEASE_8197F 0xffffffffL -#define BIT_MACID63_32_RELEASE_8197F(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8197F) << BIT_SHIFT_MACID63_32_RELEASE_8197F) -#define BITS_MACID63_32_RELEASE_8197F (BIT_MASK_MACID63_32_RELEASE_8197F << BIT_SHIFT_MACID63_32_RELEASE_8197F) -#define BIT_CLEAR_MACID63_32_RELEASE_8197F(x) ((x) & (~BITS_MACID63_32_RELEASE_8197F)) -#define BIT_GET_MACID63_32_RELEASE_8197F(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8197F) & BIT_MASK_MACID63_32_RELEASE_8197F) -#define BIT_SET_MACID63_32_RELEASE_8197F(x, v) (BIT_CLEAR_MACID63_32_RELEASE_8197F(x) | BIT_MACID63_32_RELEASE_8197F(v)) - +#define BIT_MACID63_32_RELEASE_8197F(x) \ + (((x) & BIT_MASK_MACID63_32_RELEASE_8197F) \ + << BIT_SHIFT_MACID63_32_RELEASE_8197F) +#define BITS_MACID63_32_RELEASE_8197F \ + (BIT_MASK_MACID63_32_RELEASE_8197F \ + << BIT_SHIFT_MACID63_32_RELEASE_8197F) +#define BIT_CLEAR_MACID63_32_RELEASE_8197F(x) \ + ((x) & (~BITS_MACID63_32_RELEASE_8197F)) +#define BIT_GET_MACID63_32_RELEASE_8197F(x) \ + (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8197F) & \ + BIT_MASK_MACID63_32_RELEASE_8197F) +#define BIT_SET_MACID63_32_RELEASE_8197F(x, v) \ + (BIT_CLEAR_MACID63_32_RELEASE_8197F(x) | \ + BIT_MACID63_32_RELEASE_8197F(v)) /* 2 REG_MACID_RELEASE2_8197F */ #define BIT_SHIFT_MACID95_64_RELEASE_8197F 0 #define BIT_MASK_MACID95_64_RELEASE_8197F 0xffffffffL -#define BIT_MACID95_64_RELEASE_8197F(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8197F) << BIT_SHIFT_MACID95_64_RELEASE_8197F) -#define BITS_MACID95_64_RELEASE_8197F (BIT_MASK_MACID95_64_RELEASE_8197F << BIT_SHIFT_MACID95_64_RELEASE_8197F) -#define BIT_CLEAR_MACID95_64_RELEASE_8197F(x) ((x) & (~BITS_MACID95_64_RELEASE_8197F)) -#define BIT_GET_MACID95_64_RELEASE_8197F(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8197F) & BIT_MASK_MACID95_64_RELEASE_8197F) -#define BIT_SET_MACID95_64_RELEASE_8197F(x, v) (BIT_CLEAR_MACID95_64_RELEASE_8197F(x) | BIT_MACID95_64_RELEASE_8197F(v)) - +#define BIT_MACID95_64_RELEASE_8197F(x) \ + (((x) & BIT_MASK_MACID95_64_RELEASE_8197F) \ + << BIT_SHIFT_MACID95_64_RELEASE_8197F) +#define BITS_MACID95_64_RELEASE_8197F \ + (BIT_MASK_MACID95_64_RELEASE_8197F \ + << BIT_SHIFT_MACID95_64_RELEASE_8197F) +#define BIT_CLEAR_MACID95_64_RELEASE_8197F(x) \ + ((x) & (~BITS_MACID95_64_RELEASE_8197F)) +#define BIT_GET_MACID95_64_RELEASE_8197F(x) \ + (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8197F) & \ + BIT_MASK_MACID95_64_RELEASE_8197F) +#define BIT_SET_MACID95_64_RELEASE_8197F(x, v) \ + (BIT_CLEAR_MACID95_64_RELEASE_8197F(x) | \ + BIT_MACID95_64_RELEASE_8197F(v)) /* 2 REG_MACID_RELEASE3_8197F */ #define BIT_SHIFT_MACID127_96_RELEASE_8197F 0 #define BIT_MASK_MACID127_96_RELEASE_8197F 0xffffffffL -#define BIT_MACID127_96_RELEASE_8197F(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8197F) << BIT_SHIFT_MACID127_96_RELEASE_8197F) -#define BITS_MACID127_96_RELEASE_8197F (BIT_MASK_MACID127_96_RELEASE_8197F << BIT_SHIFT_MACID127_96_RELEASE_8197F) -#define BIT_CLEAR_MACID127_96_RELEASE_8197F(x) ((x) & (~BITS_MACID127_96_RELEASE_8197F)) -#define BIT_GET_MACID127_96_RELEASE_8197F(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8197F) & BIT_MASK_MACID127_96_RELEASE_8197F) -#define BIT_SET_MACID127_96_RELEASE_8197F(x, v) (BIT_CLEAR_MACID127_96_RELEASE_8197F(x) | BIT_MACID127_96_RELEASE_8197F(v)) - +#define BIT_MACID127_96_RELEASE_8197F(x) \ + (((x) & BIT_MASK_MACID127_96_RELEASE_8197F) \ + << BIT_SHIFT_MACID127_96_RELEASE_8197F) +#define BITS_MACID127_96_RELEASE_8197F \ + (BIT_MASK_MACID127_96_RELEASE_8197F \ + << BIT_SHIFT_MACID127_96_RELEASE_8197F) +#define BIT_CLEAR_MACID127_96_RELEASE_8197F(x) \ + ((x) & (~BITS_MACID127_96_RELEASE_8197F)) +#define BIT_GET_MACID127_96_RELEASE_8197F(x) \ + (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8197F) & \ + BIT_MASK_MACID127_96_RELEASE_8197F) +#define BIT_SET_MACID127_96_RELEASE_8197F(x, v) \ + (BIT_CLEAR_MACID127_96_RELEASE_8197F(x) | \ + BIT_MACID127_96_RELEASE_8197F(v)) /* 2 REG_MACID_RELEASE_SETTING_8197F */ #define BIT_MACID_VALUE_8197F BIT(7) #define BIT_SHIFT_MACID_OFFSET_8197F 0 #define BIT_MASK_MACID_OFFSET_8197F 0x7f -#define BIT_MACID_OFFSET_8197F(x) (((x) & BIT_MASK_MACID_OFFSET_8197F) << BIT_SHIFT_MACID_OFFSET_8197F) -#define BITS_MACID_OFFSET_8197F (BIT_MASK_MACID_OFFSET_8197F << BIT_SHIFT_MACID_OFFSET_8197F) +#define BIT_MACID_OFFSET_8197F(x) \ + (((x) & BIT_MASK_MACID_OFFSET_8197F) << BIT_SHIFT_MACID_OFFSET_8197F) +#define BITS_MACID_OFFSET_8197F \ + (BIT_MASK_MACID_OFFSET_8197F << BIT_SHIFT_MACID_OFFSET_8197F) #define BIT_CLEAR_MACID_OFFSET_8197F(x) ((x) & (~BITS_MACID_OFFSET_8197F)) -#define BIT_GET_MACID_OFFSET_8197F(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8197F) & BIT_MASK_MACID_OFFSET_8197F) -#define BIT_SET_MACID_OFFSET_8197F(x, v) (BIT_CLEAR_MACID_OFFSET_8197F(x) | BIT_MACID_OFFSET_8197F(v)) - +#define BIT_GET_MACID_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_MACID_OFFSET_8197F) & BIT_MASK_MACID_OFFSET_8197F) +#define BIT_SET_MACID_OFFSET_8197F(x, v) \ + (BIT_CLEAR_MACID_OFFSET_8197F(x) | BIT_MACID_OFFSET_8197F(v)) /* 2 REG_FAST_EDCA_VOVI_SETTING_8197F */ #define BIT_SHIFT_VI_FAST_EDCA_TO_8197F 24 #define BIT_MASK_VI_FAST_EDCA_TO_8197F 0xff -#define BIT_VI_FAST_EDCA_TO_8197F(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8197F) << BIT_SHIFT_VI_FAST_EDCA_TO_8197F) -#define BITS_VI_FAST_EDCA_TO_8197F (BIT_MASK_VI_FAST_EDCA_TO_8197F << BIT_SHIFT_VI_FAST_EDCA_TO_8197F) +#define BIT_VI_FAST_EDCA_TO_8197F(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_TO_8197F) \ + << BIT_SHIFT_VI_FAST_EDCA_TO_8197F) +#define BITS_VI_FAST_EDCA_TO_8197F \ + (BIT_MASK_VI_FAST_EDCA_TO_8197F << BIT_SHIFT_VI_FAST_EDCA_TO_8197F) #define BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8197F)) -#define BIT_GET_VI_FAST_EDCA_TO_8197F(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8197F) & BIT_MASK_VI_FAST_EDCA_TO_8197F) -#define BIT_SET_VI_FAST_EDCA_TO_8197F(x, v) (BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) | BIT_VI_FAST_EDCA_TO_8197F(v)) +#define BIT_GET_VI_FAST_EDCA_TO_8197F(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8197F) & \ + BIT_MASK_VI_FAST_EDCA_TO_8197F) +#define BIT_SET_VI_FAST_EDCA_TO_8197F(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) | BIT_VI_FAST_EDCA_TO_8197F(v)) #define BIT_VI_THRESHOLD_SEL_8197F BIT(23) #define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F 16 #define BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F 0x7f -#define BIT_VI_FAST_EDCA_PKT_TH_8197F(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) -#define BITS_VI_FAST_EDCA_PKT_TH_8197F (BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) -#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8197F)) -#define BIT_GET_VI_FAST_EDCA_PKT_TH_8197F(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F) -#define BIT_SET_VI_FAST_EDCA_PKT_TH_8197F(x, v) (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) | BIT_VI_FAST_EDCA_PKT_TH_8197F(v)) - +#define BIT_VI_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F) \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) +#define BITS_VI_FAST_EDCA_PKT_TH_8197F \ + (BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) \ + ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8197F)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) & \ + BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F) +#define BIT_SET_VI_FAST_EDCA_PKT_TH_8197F(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) | \ + BIT_VI_FAST_EDCA_PKT_TH_8197F(v)) #define BIT_SHIFT_VO_FAST_EDCA_TO_8197F 8 #define BIT_MASK_VO_FAST_EDCA_TO_8197F 0xff -#define BIT_VO_FAST_EDCA_TO_8197F(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8197F) << BIT_SHIFT_VO_FAST_EDCA_TO_8197F) -#define BITS_VO_FAST_EDCA_TO_8197F (BIT_MASK_VO_FAST_EDCA_TO_8197F << BIT_SHIFT_VO_FAST_EDCA_TO_8197F) +#define BIT_VO_FAST_EDCA_TO_8197F(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO_8197F) \ + << BIT_SHIFT_VO_FAST_EDCA_TO_8197F) +#define BITS_VO_FAST_EDCA_TO_8197F \ + (BIT_MASK_VO_FAST_EDCA_TO_8197F << BIT_SHIFT_VO_FAST_EDCA_TO_8197F) #define BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8197F)) -#define BIT_GET_VO_FAST_EDCA_TO_8197F(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8197F) & BIT_MASK_VO_FAST_EDCA_TO_8197F) -#define BIT_SET_VO_FAST_EDCA_TO_8197F(x, v) (BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) | BIT_VO_FAST_EDCA_TO_8197F(v)) +#define BIT_GET_VO_FAST_EDCA_TO_8197F(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8197F) & \ + BIT_MASK_VO_FAST_EDCA_TO_8197F) +#define BIT_SET_VO_FAST_EDCA_TO_8197F(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) | BIT_VO_FAST_EDCA_TO_8197F(v)) #define BIT_VO_THRESHOLD_SEL_8197F BIT(7) #define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F 0 #define BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F 0x7f -#define BIT_VO_FAST_EDCA_PKT_TH_8197F(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) -#define BITS_VO_FAST_EDCA_PKT_TH_8197F (BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) -#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8197F)) -#define BIT_GET_VO_FAST_EDCA_PKT_TH_8197F(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F) -#define BIT_SET_VO_FAST_EDCA_PKT_TH_8197F(x, v) (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) | BIT_VO_FAST_EDCA_PKT_TH_8197F(v)) - +#define BIT_VO_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F) \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) +#define BITS_VO_FAST_EDCA_PKT_TH_8197F \ + (BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) \ + ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8197F)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) & \ + BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F) +#define BIT_SET_VO_FAST_EDCA_PKT_TH_8197F(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) | \ + BIT_VO_FAST_EDCA_PKT_TH_8197F(v)) /* 2 REG_FAST_EDCA_BEBK_SETTING_8197F */ #define BIT_SHIFT_BK_FAST_EDCA_TO_8197F 24 #define BIT_MASK_BK_FAST_EDCA_TO_8197F 0xff -#define BIT_BK_FAST_EDCA_TO_8197F(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8197F) << BIT_SHIFT_BK_FAST_EDCA_TO_8197F) -#define BITS_BK_FAST_EDCA_TO_8197F (BIT_MASK_BK_FAST_EDCA_TO_8197F << BIT_SHIFT_BK_FAST_EDCA_TO_8197F) +#define BIT_BK_FAST_EDCA_TO_8197F(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_TO_8197F) \ + << BIT_SHIFT_BK_FAST_EDCA_TO_8197F) +#define BITS_BK_FAST_EDCA_TO_8197F \ + (BIT_MASK_BK_FAST_EDCA_TO_8197F << BIT_SHIFT_BK_FAST_EDCA_TO_8197F) #define BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8197F)) -#define BIT_GET_BK_FAST_EDCA_TO_8197F(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8197F) & BIT_MASK_BK_FAST_EDCA_TO_8197F) -#define BIT_SET_BK_FAST_EDCA_TO_8197F(x, v) (BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) | BIT_BK_FAST_EDCA_TO_8197F(v)) +#define BIT_GET_BK_FAST_EDCA_TO_8197F(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8197F) & \ + BIT_MASK_BK_FAST_EDCA_TO_8197F) +#define BIT_SET_BK_FAST_EDCA_TO_8197F(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) | BIT_BK_FAST_EDCA_TO_8197F(v)) #define BIT_BK_THRESHOLD_SEL_8197F BIT(23) #define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F 16 #define BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F 0x7f -#define BIT_BK_FAST_EDCA_PKT_TH_8197F(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) -#define BITS_BK_FAST_EDCA_PKT_TH_8197F (BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) -#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8197F)) -#define BIT_GET_BK_FAST_EDCA_PKT_TH_8197F(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F) -#define BIT_SET_BK_FAST_EDCA_PKT_TH_8197F(x, v) (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) | BIT_BK_FAST_EDCA_PKT_TH_8197F(v)) - +#define BIT_BK_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F) \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) +#define BITS_BK_FAST_EDCA_PKT_TH_8197F \ + (BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) \ + ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8197F)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) & \ + BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F) +#define BIT_SET_BK_FAST_EDCA_PKT_TH_8197F(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) | \ + BIT_BK_FAST_EDCA_PKT_TH_8197F(v)) #define BIT_SHIFT_BE_FAST_EDCA_TO_8197F 8 #define BIT_MASK_BE_FAST_EDCA_TO_8197F 0xff -#define BIT_BE_FAST_EDCA_TO_8197F(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8197F) << BIT_SHIFT_BE_FAST_EDCA_TO_8197F) -#define BITS_BE_FAST_EDCA_TO_8197F (BIT_MASK_BE_FAST_EDCA_TO_8197F << BIT_SHIFT_BE_FAST_EDCA_TO_8197F) +#define BIT_BE_FAST_EDCA_TO_8197F(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO_8197F) \ + << BIT_SHIFT_BE_FAST_EDCA_TO_8197F) +#define BITS_BE_FAST_EDCA_TO_8197F \ + (BIT_MASK_BE_FAST_EDCA_TO_8197F << BIT_SHIFT_BE_FAST_EDCA_TO_8197F) #define BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8197F)) -#define BIT_GET_BE_FAST_EDCA_TO_8197F(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8197F) & BIT_MASK_BE_FAST_EDCA_TO_8197F) -#define BIT_SET_BE_FAST_EDCA_TO_8197F(x, v) (BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) | BIT_BE_FAST_EDCA_TO_8197F(v)) +#define BIT_GET_BE_FAST_EDCA_TO_8197F(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8197F) & \ + BIT_MASK_BE_FAST_EDCA_TO_8197F) +#define BIT_SET_BE_FAST_EDCA_TO_8197F(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) | BIT_BE_FAST_EDCA_TO_8197F(v)) #define BIT_BE_THRESHOLD_SEL_8197F BIT(7) #define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F 0 #define BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F 0x7f -#define BIT_BE_FAST_EDCA_PKT_TH_8197F(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) -#define BITS_BE_FAST_EDCA_PKT_TH_8197F (BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) -#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8197F)) -#define BIT_GET_BE_FAST_EDCA_PKT_TH_8197F(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F) -#define BIT_SET_BE_FAST_EDCA_PKT_TH_8197F(x, v) (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) | BIT_BE_FAST_EDCA_PKT_TH_8197F(v)) - +#define BIT_BE_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F) \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) +#define BITS_BE_FAST_EDCA_PKT_TH_8197F \ + (BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) \ + ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8197F)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) & \ + BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F) +#define BIT_SET_BE_FAST_EDCA_PKT_TH_8197F(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) | \ + BIT_BE_FAST_EDCA_PKT_TH_8197F(v)) /* 2 REG_MACID_DROP0_8197F */ #define BIT_SHIFT_MACID31_0_DROP_8197F 0 #define BIT_MASK_MACID31_0_DROP_8197F 0xffffffffL -#define BIT_MACID31_0_DROP_8197F(x) (((x) & BIT_MASK_MACID31_0_DROP_8197F) << BIT_SHIFT_MACID31_0_DROP_8197F) -#define BITS_MACID31_0_DROP_8197F (BIT_MASK_MACID31_0_DROP_8197F << BIT_SHIFT_MACID31_0_DROP_8197F) +#define BIT_MACID31_0_DROP_8197F(x) \ + (((x) & BIT_MASK_MACID31_0_DROP_8197F) \ + << BIT_SHIFT_MACID31_0_DROP_8197F) +#define BITS_MACID31_0_DROP_8197F \ + (BIT_MASK_MACID31_0_DROP_8197F << BIT_SHIFT_MACID31_0_DROP_8197F) #define BIT_CLEAR_MACID31_0_DROP_8197F(x) ((x) & (~BITS_MACID31_0_DROP_8197F)) -#define BIT_GET_MACID31_0_DROP_8197F(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8197F) & BIT_MASK_MACID31_0_DROP_8197F) -#define BIT_SET_MACID31_0_DROP_8197F(x, v) (BIT_CLEAR_MACID31_0_DROP_8197F(x) | BIT_MACID31_0_DROP_8197F(v)) - +#define BIT_GET_MACID31_0_DROP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID31_0_DROP_8197F) & \ + BIT_MASK_MACID31_0_DROP_8197F) +#define BIT_SET_MACID31_0_DROP_8197F(x, v) \ + (BIT_CLEAR_MACID31_0_DROP_8197F(x) | BIT_MACID31_0_DROP_8197F(v)) /* 2 REG_MACID_DROP1_8197F */ #define BIT_SHIFT_MACID63_32_DROP_8197F 0 #define BIT_MASK_MACID63_32_DROP_8197F 0xffffffffL -#define BIT_MACID63_32_DROP_8197F(x) (((x) & BIT_MASK_MACID63_32_DROP_8197F) << BIT_SHIFT_MACID63_32_DROP_8197F) -#define BITS_MACID63_32_DROP_8197F (BIT_MASK_MACID63_32_DROP_8197F << BIT_SHIFT_MACID63_32_DROP_8197F) +#define BIT_MACID63_32_DROP_8197F(x) \ + (((x) & BIT_MASK_MACID63_32_DROP_8197F) \ + << BIT_SHIFT_MACID63_32_DROP_8197F) +#define BITS_MACID63_32_DROP_8197F \ + (BIT_MASK_MACID63_32_DROP_8197F << BIT_SHIFT_MACID63_32_DROP_8197F) #define BIT_CLEAR_MACID63_32_DROP_8197F(x) ((x) & (~BITS_MACID63_32_DROP_8197F)) -#define BIT_GET_MACID63_32_DROP_8197F(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8197F) & BIT_MASK_MACID63_32_DROP_8197F) -#define BIT_SET_MACID63_32_DROP_8197F(x, v) (BIT_CLEAR_MACID63_32_DROP_8197F(x) | BIT_MACID63_32_DROP_8197F(v)) - +#define BIT_GET_MACID63_32_DROP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID63_32_DROP_8197F) & \ + BIT_MASK_MACID63_32_DROP_8197F) +#define BIT_SET_MACID63_32_DROP_8197F(x, v) \ + (BIT_CLEAR_MACID63_32_DROP_8197F(x) | BIT_MACID63_32_DROP_8197F(v)) /* 2 REG_MACID_DROP2_8197F */ #define BIT_SHIFT_MACID95_64_DROP_8197F 0 #define BIT_MASK_MACID95_64_DROP_8197F 0xffffffffL -#define BIT_MACID95_64_DROP_8197F(x) (((x) & BIT_MASK_MACID95_64_DROP_8197F) << BIT_SHIFT_MACID95_64_DROP_8197F) -#define BITS_MACID95_64_DROP_8197F (BIT_MASK_MACID95_64_DROP_8197F << BIT_SHIFT_MACID95_64_DROP_8197F) +#define BIT_MACID95_64_DROP_8197F(x) \ + (((x) & BIT_MASK_MACID95_64_DROP_8197F) \ + << BIT_SHIFT_MACID95_64_DROP_8197F) +#define BITS_MACID95_64_DROP_8197F \ + (BIT_MASK_MACID95_64_DROP_8197F << BIT_SHIFT_MACID95_64_DROP_8197F) #define BIT_CLEAR_MACID95_64_DROP_8197F(x) ((x) & (~BITS_MACID95_64_DROP_8197F)) -#define BIT_GET_MACID95_64_DROP_8197F(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8197F) & BIT_MASK_MACID95_64_DROP_8197F) -#define BIT_SET_MACID95_64_DROP_8197F(x, v) (BIT_CLEAR_MACID95_64_DROP_8197F(x) | BIT_MACID95_64_DROP_8197F(v)) - +#define BIT_GET_MACID95_64_DROP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID95_64_DROP_8197F) & \ + BIT_MASK_MACID95_64_DROP_8197F) +#define BIT_SET_MACID95_64_DROP_8197F(x, v) \ + (BIT_CLEAR_MACID95_64_DROP_8197F(x) | BIT_MACID95_64_DROP_8197F(v)) /* 2 REG_MACID_DROP3_8197F */ #define BIT_SHIFT_MACID127_96_DROP_8197F 0 #define BIT_MASK_MACID127_96_DROP_8197F 0xffffffffL -#define BIT_MACID127_96_DROP_8197F(x) (((x) & BIT_MASK_MACID127_96_DROP_8197F) << BIT_SHIFT_MACID127_96_DROP_8197F) -#define BITS_MACID127_96_DROP_8197F (BIT_MASK_MACID127_96_DROP_8197F << BIT_SHIFT_MACID127_96_DROP_8197F) -#define BIT_CLEAR_MACID127_96_DROP_8197F(x) ((x) & (~BITS_MACID127_96_DROP_8197F)) -#define BIT_GET_MACID127_96_DROP_8197F(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8197F) & BIT_MASK_MACID127_96_DROP_8197F) -#define BIT_SET_MACID127_96_DROP_8197F(x, v) (BIT_CLEAR_MACID127_96_DROP_8197F(x) | BIT_MACID127_96_DROP_8197F(v)) - +#define BIT_MACID127_96_DROP_8197F(x) \ + (((x) & BIT_MASK_MACID127_96_DROP_8197F) \ + << BIT_SHIFT_MACID127_96_DROP_8197F) +#define BITS_MACID127_96_DROP_8197F \ + (BIT_MASK_MACID127_96_DROP_8197F << BIT_SHIFT_MACID127_96_DROP_8197F) +#define BIT_CLEAR_MACID127_96_DROP_8197F(x) \ + ((x) & (~BITS_MACID127_96_DROP_8197F)) +#define BIT_GET_MACID127_96_DROP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID127_96_DROP_8197F) & \ + BIT_MASK_MACID127_96_DROP_8197F) +#define BIT_SET_MACID127_96_DROP_8197F(x, v) \ + (BIT_CLEAR_MACID127_96_DROP_8197F(x) | BIT_MACID127_96_DROP_8197F(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_0_8197F */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_0_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) -#define BITS_R_MACID_RELEASE_SUCCESS_0_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) -#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8197F)) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F) -#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_0_8197F(v)) - +#define BIT_R_MACID_RELEASE_SUCCESS_0_8197F(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_0_8197F \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8197F(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8197F(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_0_8197F(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_1_8197F */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_1_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) -#define BITS_R_MACID_RELEASE_SUCCESS_1_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) -#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8197F)) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F) -#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_1_8197F(v)) - +#define BIT_R_MACID_RELEASE_SUCCESS_1_8197F(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_1_8197F \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8197F(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8197F(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_1_8197F(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_2_8197F */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_2_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) -#define BITS_R_MACID_RELEASE_SUCCESS_2_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) -#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8197F)) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F) -#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_2_8197F(v)) - +#define BIT_R_MACID_RELEASE_SUCCESS_2_8197F(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_2_8197F \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8197F(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8197F(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_2_8197F(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_3_8197F */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_3_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) -#define BITS_R_MACID_RELEASE_SUCCESS_3_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) -#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8197F)) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F) -#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_3_8197F(v)) - +#define BIT_R_MACID_RELEASE_SUCCESS_3_8197F(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_3_8197F \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8197F(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8197F(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_3_8197F(v)) /* 2 REG_MGG_FIFO_CRTL_8197F */ #define BIT_R_MGG_FIFO_EN_8197F BIT(31) #define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F 28 #define BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F 0x7 -#define BIT_R_MGG_FIFO_PG_SIZE_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) -#define BITS_R_MGG_FIFO_PG_SIZE_8197F (BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) -#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) ((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8197F)) -#define BIT_GET_R_MGG_FIFO_PG_SIZE_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F) -#define BIT_SET_R_MGG_FIFO_PG_SIZE_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) | BIT_R_MGG_FIFO_PG_SIZE_8197F(v)) - +#define BIT_R_MGG_FIFO_PG_SIZE_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) +#define BITS_R_MGG_FIFO_PG_SIZE_8197F \ + (BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F \ + << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) +#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) \ + ((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8197F)) +#define BIT_GET_R_MGG_FIFO_PG_SIZE_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) & \ + BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F) +#define BIT_SET_R_MGG_FIFO_PG_SIZE_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) | \ + BIT_R_MGG_FIFO_PG_SIZE_8197F(v)) #define BIT_SHIFT_R_MGG_FIFO_START_PG_8197F 16 #define BIT_MASK_R_MGG_FIFO_START_PG_8197F 0xfff -#define BIT_R_MGG_FIFO_START_PG_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8197F) << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) -#define BITS_R_MGG_FIFO_START_PG_8197F (BIT_MASK_R_MGG_FIFO_START_PG_8197F << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) -#define BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) ((x) & (~BITS_R_MGG_FIFO_START_PG_8197F)) -#define BIT_GET_R_MGG_FIFO_START_PG_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) & BIT_MASK_R_MGG_FIFO_START_PG_8197F) -#define BIT_SET_R_MGG_FIFO_START_PG_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) | BIT_R_MGG_FIFO_START_PG_8197F(v)) - +#define BIT_R_MGG_FIFO_START_PG_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) +#define BITS_R_MGG_FIFO_START_PG_8197F \ + (BIT_MASK_R_MGG_FIFO_START_PG_8197F \ + << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) +#define BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) \ + ((x) & (~BITS_R_MGG_FIFO_START_PG_8197F)) +#define BIT_GET_R_MGG_FIFO_START_PG_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) & \ + BIT_MASK_R_MGG_FIFO_START_PG_8197F) +#define BIT_SET_R_MGG_FIFO_START_PG_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) | \ + BIT_R_MGG_FIFO_START_PG_8197F(v)) #define BIT_SHIFT_R_MGG_FIFO_SIZE_8197F 14 #define BIT_MASK_R_MGG_FIFO_SIZE_8197F 0x3 -#define BIT_R_MGG_FIFO_SIZE_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8197F) << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) -#define BITS_R_MGG_FIFO_SIZE_8197F (BIT_MASK_R_MGG_FIFO_SIZE_8197F << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) +#define BIT_R_MGG_FIFO_SIZE_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) +#define BITS_R_MGG_FIFO_SIZE_8197F \ + (BIT_MASK_R_MGG_FIFO_SIZE_8197F << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) #define BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) ((x) & (~BITS_R_MGG_FIFO_SIZE_8197F)) -#define BIT_GET_R_MGG_FIFO_SIZE_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) & BIT_MASK_R_MGG_FIFO_SIZE_8197F) -#define BIT_SET_R_MGG_FIFO_SIZE_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) | BIT_R_MGG_FIFO_SIZE_8197F(v)) +#define BIT_GET_R_MGG_FIFO_SIZE_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) & \ + BIT_MASK_R_MGG_FIFO_SIZE_8197F) +#define BIT_SET_R_MGG_FIFO_SIZE_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) | BIT_R_MGG_FIFO_SIZE_8197F(v)) #define BIT_R_MGG_FIFO_PAUSE_8197F BIT(13) #define BIT_SHIFT_R_MGG_FIFO_RPTR_8197F 8 #define BIT_MASK_R_MGG_FIFO_RPTR_8197F 0x1f -#define BIT_R_MGG_FIFO_RPTR_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8197F) << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) -#define BITS_R_MGG_FIFO_RPTR_8197F (BIT_MASK_R_MGG_FIFO_RPTR_8197F << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) +#define BIT_R_MGG_FIFO_RPTR_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) +#define BITS_R_MGG_FIFO_RPTR_8197F \ + (BIT_MASK_R_MGG_FIFO_RPTR_8197F << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) #define BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) ((x) & (~BITS_R_MGG_FIFO_RPTR_8197F)) -#define BIT_GET_R_MGG_FIFO_RPTR_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) & BIT_MASK_R_MGG_FIFO_RPTR_8197F) -#define BIT_SET_R_MGG_FIFO_RPTR_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) | BIT_R_MGG_FIFO_RPTR_8197F(v)) +#define BIT_GET_R_MGG_FIFO_RPTR_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) & \ + BIT_MASK_R_MGG_FIFO_RPTR_8197F) +#define BIT_SET_R_MGG_FIFO_RPTR_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) | BIT_R_MGG_FIFO_RPTR_8197F(v)) #define BIT_R_MGG_FIFO_OV_8197F BIT(7) #define BIT_R_MGG_FIFO_WPTR_ERROR_8197F BIT(6) @@ -8201,63 +10716,108 @@ #define BIT_SHIFT_R_MGG_FIFO_WPTR_8197F 0 #define BIT_MASK_R_MGG_FIFO_WPTR_8197F 0x1f -#define BIT_R_MGG_FIFO_WPTR_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8197F) << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) -#define BITS_R_MGG_FIFO_WPTR_8197F (BIT_MASK_R_MGG_FIFO_WPTR_8197F << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) +#define BIT_R_MGG_FIFO_WPTR_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) +#define BITS_R_MGG_FIFO_WPTR_8197F \ + (BIT_MASK_R_MGG_FIFO_WPTR_8197F << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) #define BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) ((x) & (~BITS_R_MGG_FIFO_WPTR_8197F)) -#define BIT_GET_R_MGG_FIFO_WPTR_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) & BIT_MASK_R_MGG_FIFO_WPTR_8197F) -#define BIT_SET_R_MGG_FIFO_WPTR_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) | BIT_R_MGG_FIFO_WPTR_8197F(v)) - +#define BIT_GET_R_MGG_FIFO_WPTR_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) & \ + BIT_MASK_R_MGG_FIFO_WPTR_8197F) +#define BIT_SET_R_MGG_FIFO_WPTR_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) | BIT_R_MGG_FIFO_WPTR_8197F(v)) /* 2 REG_MGG_FIFO_INT_8197F */ #define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F 16 #define BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F 0xffff -#define BIT_R_MGG_FIFO_INT_FLAG_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) -#define BITS_R_MGG_FIFO_INT_FLAG_8197F (BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) -#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) ((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8197F)) -#define BIT_GET_R_MGG_FIFO_INT_FLAG_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F) -#define BIT_SET_R_MGG_FIFO_INT_FLAG_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) | BIT_R_MGG_FIFO_INT_FLAG_8197F(v)) - +#define BIT_R_MGG_FIFO_INT_FLAG_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) +#define BITS_R_MGG_FIFO_INT_FLAG_8197F \ + (BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F \ + << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) +#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) \ + ((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8197F)) +#define BIT_GET_R_MGG_FIFO_INT_FLAG_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) & \ + BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F) +#define BIT_SET_R_MGG_FIFO_INT_FLAG_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) | \ + BIT_R_MGG_FIFO_INT_FLAG_8197F(v)) #define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F 0 #define BIT_MASK_R_MGG_FIFO_INT_MASK_8197F 0xffff -#define BIT_R_MGG_FIFO_INT_MASK_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8197F) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) -#define BITS_R_MGG_FIFO_INT_MASK_8197F (BIT_MASK_R_MGG_FIFO_INT_MASK_8197F << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) -#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) ((x) & (~BITS_R_MGG_FIFO_INT_MASK_8197F)) -#define BIT_GET_R_MGG_FIFO_INT_MASK_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) & BIT_MASK_R_MGG_FIFO_INT_MASK_8197F) -#define BIT_SET_R_MGG_FIFO_INT_MASK_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) | BIT_R_MGG_FIFO_INT_MASK_8197F(v)) - +#define BIT_R_MGG_FIFO_INT_MASK_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) +#define BITS_R_MGG_FIFO_INT_MASK_8197F \ + (BIT_MASK_R_MGG_FIFO_INT_MASK_8197F \ + << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) +#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) \ + ((x) & (~BITS_R_MGG_FIFO_INT_MASK_8197F)) +#define BIT_GET_R_MGG_FIFO_INT_MASK_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) & \ + BIT_MASK_R_MGG_FIFO_INT_MASK_8197F) +#define BIT_SET_R_MGG_FIFO_INT_MASK_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) | \ + BIT_R_MGG_FIFO_INT_MASK_8197F(v)) /* 2 REG_MGG_FIFO_LIFETIME_8197F */ #define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F 16 #define BIT_MASK_R_MGG_FIFO_LIFETIME_8197F 0xffff -#define BIT_R_MGG_FIFO_LIFETIME_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8197F) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) -#define BITS_R_MGG_FIFO_LIFETIME_8197F (BIT_MASK_R_MGG_FIFO_LIFETIME_8197F << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) -#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) ((x) & (~BITS_R_MGG_FIFO_LIFETIME_8197F)) -#define BIT_GET_R_MGG_FIFO_LIFETIME_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) & BIT_MASK_R_MGG_FIFO_LIFETIME_8197F) -#define BIT_SET_R_MGG_FIFO_LIFETIME_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) | BIT_R_MGG_FIFO_LIFETIME_8197F(v)) - +#define BIT_R_MGG_FIFO_LIFETIME_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) +#define BITS_R_MGG_FIFO_LIFETIME_8197F \ + (BIT_MASK_R_MGG_FIFO_LIFETIME_8197F \ + << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) +#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) \ + ((x) & (~BITS_R_MGG_FIFO_LIFETIME_8197F)) +#define BIT_GET_R_MGG_FIFO_LIFETIME_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) & \ + BIT_MASK_R_MGG_FIFO_LIFETIME_8197F) +#define BIT_SET_R_MGG_FIFO_LIFETIME_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) | \ + BIT_R_MGG_FIFO_LIFETIME_8197F(v)) #define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F 0 #define BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F 0xffff -#define BIT_R_MGG_FIFO_VALID_MAP_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) -#define BITS_R_MGG_FIFO_VALID_MAP_8197F (BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) -#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) ((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8197F)) -#define BIT_GET_R_MGG_FIFO_VALID_MAP_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F) -#define BIT_SET_R_MGG_FIFO_VALID_MAP_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) | BIT_R_MGG_FIFO_VALID_MAP_8197F(v)) - +#define BIT_R_MGG_FIFO_VALID_MAP_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) +#define BITS_R_MGG_FIFO_VALID_MAP_8197F \ + (BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F \ + << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) +#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) \ + ((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8197F)) +#define BIT_GET_R_MGG_FIFO_VALID_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) & \ + BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F) +#define BIT_SET_R_MGG_FIFO_VALID_MAP_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) | \ + BIT_R_MGG_FIFO_VALID_MAP_8197F(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x7f -#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) -#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) -#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) -#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(v)) - +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(v)) /* 2 REG_SHCUT_SETTING_8197F */ @@ -8317,7 +10877,7 @@ /* 2 REG_NOT_VALID_8197F */ -/* 2 REG_NOT_VALID_8197F */ +/* 2 REG_CHNL_INFO_CTRL_8197F */ #define BIT_CHNL_REF_RXNAV_8197F BIT(7) #define BIT_CHNL_REF_VBON_8197F BIT(6) #define BIT_CHNL_REF_EDCCA_8197F BIT(5) @@ -8326,27 +10886,37 @@ #define BIT_CHNL_INFO_RST_8197F BIT(1) #define BIT_ATM_AIRTIME_EN_8197F BIT(0) -/* 2 REG_NOT_VALID_8197F */ +/* 2 REG_CHNL_IDLE_TIME_8197F */ #define BIT_SHIFT_CHNL_IDLE_TIME_8197F 0 #define BIT_MASK_CHNL_IDLE_TIME_8197F 0xffffffffL -#define BIT_CHNL_IDLE_TIME_8197F(x) (((x) & BIT_MASK_CHNL_IDLE_TIME_8197F) << BIT_SHIFT_CHNL_IDLE_TIME_8197F) -#define BITS_CHNL_IDLE_TIME_8197F (BIT_MASK_CHNL_IDLE_TIME_8197F << BIT_SHIFT_CHNL_IDLE_TIME_8197F) +#define BIT_CHNL_IDLE_TIME_8197F(x) \ + (((x) & BIT_MASK_CHNL_IDLE_TIME_8197F) \ + << BIT_SHIFT_CHNL_IDLE_TIME_8197F) +#define BITS_CHNL_IDLE_TIME_8197F \ + (BIT_MASK_CHNL_IDLE_TIME_8197F << BIT_SHIFT_CHNL_IDLE_TIME_8197F) #define BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) ((x) & (~BITS_CHNL_IDLE_TIME_8197F)) -#define BIT_GET_CHNL_IDLE_TIME_8197F(x) (((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8197F) & BIT_MASK_CHNL_IDLE_TIME_8197F) -#define BIT_SET_CHNL_IDLE_TIME_8197F(x, v) (BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) | BIT_CHNL_IDLE_TIME_8197F(v)) - +#define BIT_GET_CHNL_IDLE_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8197F) & \ + BIT_MASK_CHNL_IDLE_TIME_8197F) +#define BIT_SET_CHNL_IDLE_TIME_8197F(x, v) \ + (BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) | BIT_CHNL_IDLE_TIME_8197F(v)) -/* 2 REG_NOT_VALID_8197F */ +/* 2 REG_CHNL_BUSY_TIME_8197F */ #define BIT_SHIFT_CHNL_BUSY_TIME_8197F 0 #define BIT_MASK_CHNL_BUSY_TIME_8197F 0xffffffffL -#define BIT_CHNL_BUSY_TIME_8197F(x) (((x) & BIT_MASK_CHNL_BUSY_TIME_8197F) << BIT_SHIFT_CHNL_BUSY_TIME_8197F) -#define BITS_CHNL_BUSY_TIME_8197F (BIT_MASK_CHNL_BUSY_TIME_8197F << BIT_SHIFT_CHNL_BUSY_TIME_8197F) +#define BIT_CHNL_BUSY_TIME_8197F(x) \ + (((x) & BIT_MASK_CHNL_BUSY_TIME_8197F) \ + << BIT_SHIFT_CHNL_BUSY_TIME_8197F) +#define BITS_CHNL_BUSY_TIME_8197F \ + (BIT_MASK_CHNL_BUSY_TIME_8197F << BIT_SHIFT_CHNL_BUSY_TIME_8197F) #define BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) ((x) & (~BITS_CHNL_BUSY_TIME_8197F)) -#define BIT_GET_CHNL_BUSY_TIME_8197F(x) (((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8197F) & BIT_MASK_CHNL_BUSY_TIME_8197F) -#define BIT_SET_CHNL_BUSY_TIME_8197F(x, v) (BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) | BIT_CHNL_BUSY_TIME_8197F(v)) - +#define BIT_GET_CHNL_BUSY_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8197F) & \ + BIT_MASK_CHNL_BUSY_TIME_8197F) +#define BIT_SET_CHNL_BUSY_TIME_8197F(x, v) \ + (BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) | BIT_CHNL_BUSY_TIME_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -8354,12 +10924,15 @@ #define BIT_SHIFT_TXOPLIMIT_8197F 16 #define BIT_MASK_TXOPLIMIT_8197F 0x7ff -#define BIT_TXOPLIMIT_8197F(x) (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) -#define BITS_TXOPLIMIT_8197F (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) +#define BIT_TXOPLIMIT_8197F(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) +#define BITS_TXOPLIMIT_8197F \ + (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) #define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F)) -#define BIT_GET_TXOPLIMIT_8197F(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) -#define BIT_SET_TXOPLIMIT_8197F(x, v) (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) - +#define BIT_GET_TXOPLIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) +#define BIT_SET_TXOPLIMIT_8197F(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) #define BIT_SHIFT_CW_8197F 8 #define BIT_MASK_CW_8197F 0xff @@ -8369,28 +10942,30 @@ #define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F) #define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v)) - #define BIT_SHIFT_AIFS_8197F 0 #define BIT_MASK_AIFS_8197F 0xff #define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F) #define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F) #define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F)) -#define BIT_GET_AIFS_8197F(x) (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) +#define BIT_GET_AIFS_8197F(x) \ + (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) #define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v)) - /* 2 REG_EDCA_VI_PARAM_8197F */ /* 2 REG_NOT_VALID_8197F */ #define BIT_SHIFT_TXOPLIMIT_8197F 16 #define BIT_MASK_TXOPLIMIT_8197F 0x7ff -#define BIT_TXOPLIMIT_8197F(x) (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) -#define BITS_TXOPLIMIT_8197F (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) +#define BIT_TXOPLIMIT_8197F(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) +#define BITS_TXOPLIMIT_8197F \ + (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) #define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F)) -#define BIT_GET_TXOPLIMIT_8197F(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) -#define BIT_SET_TXOPLIMIT_8197F(x, v) (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) - +#define BIT_GET_TXOPLIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) +#define BIT_SET_TXOPLIMIT_8197F(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) #define BIT_SHIFT_CW_8197F 8 #define BIT_MASK_CW_8197F 0xff @@ -8400,28 +10975,30 @@ #define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F) #define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v)) - #define BIT_SHIFT_AIFS_8197F 0 #define BIT_MASK_AIFS_8197F 0xff #define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F) #define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F) #define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F)) -#define BIT_GET_AIFS_8197F(x) (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) +#define BIT_GET_AIFS_8197F(x) \ + (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) #define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v)) - /* 2 REG_EDCA_BE_PARAM_8197F */ /* 2 REG_NOT_VALID_8197F */ #define BIT_SHIFT_TXOPLIMIT_8197F 16 #define BIT_MASK_TXOPLIMIT_8197F 0x7ff -#define BIT_TXOPLIMIT_8197F(x) (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) -#define BITS_TXOPLIMIT_8197F (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) +#define BIT_TXOPLIMIT_8197F(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) +#define BITS_TXOPLIMIT_8197F \ + (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) #define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F)) -#define BIT_GET_TXOPLIMIT_8197F(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) -#define BIT_SET_TXOPLIMIT_8197F(x, v) (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) - +#define BIT_GET_TXOPLIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) +#define BIT_SET_TXOPLIMIT_8197F(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) #define BIT_SHIFT_CW_8197F 8 #define BIT_MASK_CW_8197F 0xff @@ -8431,28 +11008,30 @@ #define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F) #define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v)) - #define BIT_SHIFT_AIFS_8197F 0 #define BIT_MASK_AIFS_8197F 0xff #define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F) #define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F) #define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F)) -#define BIT_GET_AIFS_8197F(x) (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) +#define BIT_GET_AIFS_8197F(x) \ + (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) #define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v)) - /* 2 REG_EDCA_BK_PARAM_8197F */ /* 2 REG_NOT_VALID_8197F */ #define BIT_SHIFT_TXOPLIMIT_8197F 16 #define BIT_MASK_TXOPLIMIT_8197F 0x7ff -#define BIT_TXOPLIMIT_8197F(x) (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) -#define BITS_TXOPLIMIT_8197F (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) +#define BIT_TXOPLIMIT_8197F(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) +#define BITS_TXOPLIMIT_8197F \ + (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) #define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F)) -#define BIT_GET_TXOPLIMIT_8197F(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) -#define BIT_SET_TXOPLIMIT_8197F(x, v) (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) - +#define BIT_GET_TXOPLIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) +#define BIT_SET_TXOPLIMIT_8197F(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) #define BIT_SHIFT_CW_8197F 8 #define BIT_MASK_CW_8197F 0xff @@ -8462,44 +11041,51 @@ #define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F) #define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v)) - #define BIT_SHIFT_AIFS_8197F 0 #define BIT_MASK_AIFS_8197F 0xff #define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F) #define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F) #define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F)) -#define BIT_GET_AIFS_8197F(x) (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) +#define BIT_GET_AIFS_8197F(x) \ + (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) #define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v)) - /* 2 REG_BCNTCFG_8197F */ #define BIT_SHIFT_BCNCW_MAX_8197F 12 #define BIT_MASK_BCNCW_MAX_8197F 0xf -#define BIT_BCNCW_MAX_8197F(x) (((x) & BIT_MASK_BCNCW_MAX_8197F) << BIT_SHIFT_BCNCW_MAX_8197F) -#define BITS_BCNCW_MAX_8197F (BIT_MASK_BCNCW_MAX_8197F << BIT_SHIFT_BCNCW_MAX_8197F) +#define BIT_BCNCW_MAX_8197F(x) \ + (((x) & BIT_MASK_BCNCW_MAX_8197F) << BIT_SHIFT_BCNCW_MAX_8197F) +#define BITS_BCNCW_MAX_8197F \ + (BIT_MASK_BCNCW_MAX_8197F << BIT_SHIFT_BCNCW_MAX_8197F) #define BIT_CLEAR_BCNCW_MAX_8197F(x) ((x) & (~BITS_BCNCW_MAX_8197F)) -#define BIT_GET_BCNCW_MAX_8197F(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8197F) & BIT_MASK_BCNCW_MAX_8197F) -#define BIT_SET_BCNCW_MAX_8197F(x, v) (BIT_CLEAR_BCNCW_MAX_8197F(x) | BIT_BCNCW_MAX_8197F(v)) - +#define BIT_GET_BCNCW_MAX_8197F(x) \ + (((x) >> BIT_SHIFT_BCNCW_MAX_8197F) & BIT_MASK_BCNCW_MAX_8197F) +#define BIT_SET_BCNCW_MAX_8197F(x, v) \ + (BIT_CLEAR_BCNCW_MAX_8197F(x) | BIT_BCNCW_MAX_8197F(v)) #define BIT_SHIFT_BCNCW_MIN_8197F 8 #define BIT_MASK_BCNCW_MIN_8197F 0xf -#define BIT_BCNCW_MIN_8197F(x) (((x) & BIT_MASK_BCNCW_MIN_8197F) << BIT_SHIFT_BCNCW_MIN_8197F) -#define BITS_BCNCW_MIN_8197F (BIT_MASK_BCNCW_MIN_8197F << BIT_SHIFT_BCNCW_MIN_8197F) +#define BIT_BCNCW_MIN_8197F(x) \ + (((x) & BIT_MASK_BCNCW_MIN_8197F) << BIT_SHIFT_BCNCW_MIN_8197F) +#define BITS_BCNCW_MIN_8197F \ + (BIT_MASK_BCNCW_MIN_8197F << BIT_SHIFT_BCNCW_MIN_8197F) #define BIT_CLEAR_BCNCW_MIN_8197F(x) ((x) & (~BITS_BCNCW_MIN_8197F)) -#define BIT_GET_BCNCW_MIN_8197F(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8197F) & BIT_MASK_BCNCW_MIN_8197F) -#define BIT_SET_BCNCW_MIN_8197F(x, v) (BIT_CLEAR_BCNCW_MIN_8197F(x) | BIT_BCNCW_MIN_8197F(v)) - +#define BIT_GET_BCNCW_MIN_8197F(x) \ + (((x) >> BIT_SHIFT_BCNCW_MIN_8197F) & BIT_MASK_BCNCW_MIN_8197F) +#define BIT_SET_BCNCW_MIN_8197F(x, v) \ + (BIT_CLEAR_BCNCW_MIN_8197F(x) | BIT_BCNCW_MIN_8197F(v)) #define BIT_SHIFT_BCNIFS_8197F 0 #define BIT_MASK_BCNIFS_8197F 0xff -#define BIT_BCNIFS_8197F(x) (((x) & BIT_MASK_BCNIFS_8197F) << BIT_SHIFT_BCNIFS_8197F) +#define BIT_BCNIFS_8197F(x) \ + (((x) & BIT_MASK_BCNIFS_8197F) << BIT_SHIFT_BCNIFS_8197F) #define BITS_BCNIFS_8197F (BIT_MASK_BCNIFS_8197F << BIT_SHIFT_BCNIFS_8197F) #define BIT_CLEAR_BCNIFS_8197F(x) ((x) & (~BITS_BCNIFS_8197F)) -#define BIT_GET_BCNIFS_8197F(x) (((x) >> BIT_SHIFT_BCNIFS_8197F) & BIT_MASK_BCNIFS_8197F) -#define BIT_SET_BCNIFS_8197F(x, v) (BIT_CLEAR_BCNIFS_8197F(x) | BIT_BCNIFS_8197F(v)) - +#define BIT_GET_BCNIFS_8197F(x) \ + (((x) >> BIT_SHIFT_BCNIFS_8197F) & BIT_MASK_BCNIFS_8197F) +#define BIT_SET_BCNIFS_8197F(x, v) \ + (BIT_CLEAR_BCNIFS_8197F(x) | BIT_BCNIFS_8197F(v)) /* 2 REG_PIFS_8197F */ @@ -8508,80 +11094,104 @@ #define BIT_PIFS_8197F(x) (((x) & BIT_MASK_PIFS_8197F) << BIT_SHIFT_PIFS_8197F) #define BITS_PIFS_8197F (BIT_MASK_PIFS_8197F << BIT_SHIFT_PIFS_8197F) #define BIT_CLEAR_PIFS_8197F(x) ((x) & (~BITS_PIFS_8197F)) -#define BIT_GET_PIFS_8197F(x) (((x) >> BIT_SHIFT_PIFS_8197F) & BIT_MASK_PIFS_8197F) +#define BIT_GET_PIFS_8197F(x) \ + (((x) >> BIT_SHIFT_PIFS_8197F) & BIT_MASK_PIFS_8197F) #define BIT_SET_PIFS_8197F(x, v) (BIT_CLEAR_PIFS_8197F(x) | BIT_PIFS_8197F(v)) - /* 2 REG_RDG_PIFS_8197F */ #define BIT_SHIFT_RDG_PIFS_8197F 0 #define BIT_MASK_RDG_PIFS_8197F 0xff -#define BIT_RDG_PIFS_8197F(x) (((x) & BIT_MASK_RDG_PIFS_8197F) << BIT_SHIFT_RDG_PIFS_8197F) -#define BITS_RDG_PIFS_8197F (BIT_MASK_RDG_PIFS_8197F << BIT_SHIFT_RDG_PIFS_8197F) +#define BIT_RDG_PIFS_8197F(x) \ + (((x) & BIT_MASK_RDG_PIFS_8197F) << BIT_SHIFT_RDG_PIFS_8197F) +#define BITS_RDG_PIFS_8197F \ + (BIT_MASK_RDG_PIFS_8197F << BIT_SHIFT_RDG_PIFS_8197F) #define BIT_CLEAR_RDG_PIFS_8197F(x) ((x) & (~BITS_RDG_PIFS_8197F)) -#define BIT_GET_RDG_PIFS_8197F(x) (((x) >> BIT_SHIFT_RDG_PIFS_8197F) & BIT_MASK_RDG_PIFS_8197F) -#define BIT_SET_RDG_PIFS_8197F(x, v) (BIT_CLEAR_RDG_PIFS_8197F(x) | BIT_RDG_PIFS_8197F(v)) - +#define BIT_GET_RDG_PIFS_8197F(x) \ + (((x) >> BIT_SHIFT_RDG_PIFS_8197F) & BIT_MASK_RDG_PIFS_8197F) +#define BIT_SET_RDG_PIFS_8197F(x, v) \ + (BIT_CLEAR_RDG_PIFS_8197F(x) | BIT_RDG_PIFS_8197F(v)) /* 2 REG_SIFS_8197F */ #define BIT_SHIFT_SIFS_OFDM_TRX_8197F 24 #define BIT_MASK_SIFS_OFDM_TRX_8197F 0xff -#define BIT_SIFS_OFDM_TRX_8197F(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8197F) << BIT_SHIFT_SIFS_OFDM_TRX_8197F) -#define BITS_SIFS_OFDM_TRX_8197F (BIT_MASK_SIFS_OFDM_TRX_8197F << BIT_SHIFT_SIFS_OFDM_TRX_8197F) +#define BIT_SIFS_OFDM_TRX_8197F(x) \ + (((x) & BIT_MASK_SIFS_OFDM_TRX_8197F) << BIT_SHIFT_SIFS_OFDM_TRX_8197F) +#define BITS_SIFS_OFDM_TRX_8197F \ + (BIT_MASK_SIFS_OFDM_TRX_8197F << BIT_SHIFT_SIFS_OFDM_TRX_8197F) #define BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) ((x) & (~BITS_SIFS_OFDM_TRX_8197F)) -#define BIT_GET_SIFS_OFDM_TRX_8197F(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8197F) & BIT_MASK_SIFS_OFDM_TRX_8197F) -#define BIT_SET_SIFS_OFDM_TRX_8197F(x, v) (BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) | BIT_SIFS_OFDM_TRX_8197F(v)) - +#define BIT_GET_SIFS_OFDM_TRX_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8197F) & BIT_MASK_SIFS_OFDM_TRX_8197F) +#define BIT_SET_SIFS_OFDM_TRX_8197F(x, v) \ + (BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) | BIT_SIFS_OFDM_TRX_8197F(v)) #define BIT_SHIFT_SIFS_CCK_TRX_8197F 16 #define BIT_MASK_SIFS_CCK_TRX_8197F 0xff -#define BIT_SIFS_CCK_TRX_8197F(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8197F) << BIT_SHIFT_SIFS_CCK_TRX_8197F) -#define BITS_SIFS_CCK_TRX_8197F (BIT_MASK_SIFS_CCK_TRX_8197F << BIT_SHIFT_SIFS_CCK_TRX_8197F) +#define BIT_SIFS_CCK_TRX_8197F(x) \ + (((x) & BIT_MASK_SIFS_CCK_TRX_8197F) << BIT_SHIFT_SIFS_CCK_TRX_8197F) +#define BITS_SIFS_CCK_TRX_8197F \ + (BIT_MASK_SIFS_CCK_TRX_8197F << BIT_SHIFT_SIFS_CCK_TRX_8197F) #define BIT_CLEAR_SIFS_CCK_TRX_8197F(x) ((x) & (~BITS_SIFS_CCK_TRX_8197F)) -#define BIT_GET_SIFS_CCK_TRX_8197F(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8197F) & BIT_MASK_SIFS_CCK_TRX_8197F) -#define BIT_SET_SIFS_CCK_TRX_8197F(x, v) (BIT_CLEAR_SIFS_CCK_TRX_8197F(x) | BIT_SIFS_CCK_TRX_8197F(v)) - +#define BIT_GET_SIFS_CCK_TRX_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8197F) & BIT_MASK_SIFS_CCK_TRX_8197F) +#define BIT_SET_SIFS_CCK_TRX_8197F(x, v) \ + (BIT_CLEAR_SIFS_CCK_TRX_8197F(x) | BIT_SIFS_CCK_TRX_8197F(v)) #define BIT_SHIFT_SIFS_OFDM_CTX_8197F 8 #define BIT_MASK_SIFS_OFDM_CTX_8197F 0xff -#define BIT_SIFS_OFDM_CTX_8197F(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8197F) << BIT_SHIFT_SIFS_OFDM_CTX_8197F) -#define BITS_SIFS_OFDM_CTX_8197F (BIT_MASK_SIFS_OFDM_CTX_8197F << BIT_SHIFT_SIFS_OFDM_CTX_8197F) +#define BIT_SIFS_OFDM_CTX_8197F(x) \ + (((x) & BIT_MASK_SIFS_OFDM_CTX_8197F) << BIT_SHIFT_SIFS_OFDM_CTX_8197F) +#define BITS_SIFS_OFDM_CTX_8197F \ + (BIT_MASK_SIFS_OFDM_CTX_8197F << BIT_SHIFT_SIFS_OFDM_CTX_8197F) #define BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) ((x) & (~BITS_SIFS_OFDM_CTX_8197F)) -#define BIT_GET_SIFS_OFDM_CTX_8197F(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8197F) & BIT_MASK_SIFS_OFDM_CTX_8197F) -#define BIT_SET_SIFS_OFDM_CTX_8197F(x, v) (BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) | BIT_SIFS_OFDM_CTX_8197F(v)) - +#define BIT_GET_SIFS_OFDM_CTX_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8197F) & BIT_MASK_SIFS_OFDM_CTX_8197F) +#define BIT_SET_SIFS_OFDM_CTX_8197F(x, v) \ + (BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) | BIT_SIFS_OFDM_CTX_8197F(v)) #define BIT_SHIFT_SIFS_CCK_CTX_8197F 0 #define BIT_MASK_SIFS_CCK_CTX_8197F 0xff -#define BIT_SIFS_CCK_CTX_8197F(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8197F) << BIT_SHIFT_SIFS_CCK_CTX_8197F) -#define BITS_SIFS_CCK_CTX_8197F (BIT_MASK_SIFS_CCK_CTX_8197F << BIT_SHIFT_SIFS_CCK_CTX_8197F) +#define BIT_SIFS_CCK_CTX_8197F(x) \ + (((x) & BIT_MASK_SIFS_CCK_CTX_8197F) << BIT_SHIFT_SIFS_CCK_CTX_8197F) +#define BITS_SIFS_CCK_CTX_8197F \ + (BIT_MASK_SIFS_CCK_CTX_8197F << BIT_SHIFT_SIFS_CCK_CTX_8197F) #define BIT_CLEAR_SIFS_CCK_CTX_8197F(x) ((x) & (~BITS_SIFS_CCK_CTX_8197F)) -#define BIT_GET_SIFS_CCK_CTX_8197F(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8197F) & BIT_MASK_SIFS_CCK_CTX_8197F) -#define BIT_SET_SIFS_CCK_CTX_8197F(x, v) (BIT_CLEAR_SIFS_CCK_CTX_8197F(x) | BIT_SIFS_CCK_CTX_8197F(v)) - +#define BIT_GET_SIFS_CCK_CTX_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8197F) & BIT_MASK_SIFS_CCK_CTX_8197F) +#define BIT_SET_SIFS_CCK_CTX_8197F(x, v) \ + (BIT_CLEAR_SIFS_CCK_CTX_8197F(x) | BIT_SIFS_CCK_CTX_8197F(v)) /* 2 REG_TSFTR_SYN_OFFSET_8197F */ #define BIT_SHIFT_TSFTR_SNC_OFFSET_8197F 0 #define BIT_MASK_TSFTR_SNC_OFFSET_8197F 0xffff -#define BIT_TSFTR_SNC_OFFSET_8197F(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8197F) << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) -#define BITS_TSFTR_SNC_OFFSET_8197F (BIT_MASK_TSFTR_SNC_OFFSET_8197F << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) -#define BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) ((x) & (~BITS_TSFTR_SNC_OFFSET_8197F)) -#define BIT_GET_TSFTR_SNC_OFFSET_8197F(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) & BIT_MASK_TSFTR_SNC_OFFSET_8197F) -#define BIT_SET_TSFTR_SNC_OFFSET_8197F(x, v) (BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) | BIT_TSFTR_SNC_OFFSET_8197F(v)) - +#define BIT_TSFTR_SNC_OFFSET_8197F(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8197F) \ + << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) +#define BITS_TSFTR_SNC_OFFSET_8197F \ + (BIT_MASK_TSFTR_SNC_OFFSET_8197F << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) \ + ((x) & (~BITS_TSFTR_SNC_OFFSET_8197F)) +#define BIT_GET_TSFTR_SNC_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) & \ + BIT_MASK_TSFTR_SNC_OFFSET_8197F) +#define BIT_SET_TSFTR_SNC_OFFSET_8197F(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) | BIT_TSFTR_SNC_OFFSET_8197F(v)) /* 2 REG_AGGR_BREAK_TIME_8197F */ #define BIT_SHIFT_AGGR_BK_TIME_8197F 0 #define BIT_MASK_AGGR_BK_TIME_8197F 0xff -#define BIT_AGGR_BK_TIME_8197F(x) (((x) & BIT_MASK_AGGR_BK_TIME_8197F) << BIT_SHIFT_AGGR_BK_TIME_8197F) -#define BITS_AGGR_BK_TIME_8197F (BIT_MASK_AGGR_BK_TIME_8197F << BIT_SHIFT_AGGR_BK_TIME_8197F) +#define BIT_AGGR_BK_TIME_8197F(x) \ + (((x) & BIT_MASK_AGGR_BK_TIME_8197F) << BIT_SHIFT_AGGR_BK_TIME_8197F) +#define BITS_AGGR_BK_TIME_8197F \ + (BIT_MASK_AGGR_BK_TIME_8197F << BIT_SHIFT_AGGR_BK_TIME_8197F) #define BIT_CLEAR_AGGR_BK_TIME_8197F(x) ((x) & (~BITS_AGGR_BK_TIME_8197F)) -#define BIT_GET_AGGR_BK_TIME_8197F(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8197F) & BIT_MASK_AGGR_BK_TIME_8197F) -#define BIT_SET_AGGR_BK_TIME_8197F(x, v) (BIT_CLEAR_AGGR_BK_TIME_8197F(x) | BIT_AGGR_BK_TIME_8197F(v)) - +#define BIT_GET_AGGR_BK_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_AGGR_BK_TIME_8197F) & BIT_MASK_AGGR_BK_TIME_8197F) +#define BIT_SET_AGGR_BK_TIME_8197F(x, v) \ + (BIT_CLEAR_AGGR_BK_TIME_8197F(x) | BIT_AGGR_BK_TIME_8197F(v)) /* 2 REG_SLOT_8197F */ @@ -8590,10 +11200,10 @@ #define BIT_SLOT_8197F(x) (((x) & BIT_MASK_SLOT_8197F) << BIT_SHIFT_SLOT_8197F) #define BITS_SLOT_8197F (BIT_MASK_SLOT_8197F << BIT_SHIFT_SLOT_8197F) #define BIT_CLEAR_SLOT_8197F(x) ((x) & (~BITS_SLOT_8197F)) -#define BIT_GET_SLOT_8197F(x) (((x) >> BIT_SHIFT_SLOT_8197F) & BIT_MASK_SLOT_8197F) +#define BIT_GET_SLOT_8197F(x) \ + (((x) >> BIT_SHIFT_SLOT_8197F) & BIT_MASK_SLOT_8197F) #define BIT_SET_SLOT_8197F(x, v) (BIT_CLEAR_SLOT_8197F(x) | BIT_SLOT_8197F(v)) - /* 2 REG_TX_PTCL_CTRL_8197F */ #define BIT_DIS_EDCCA_8197F BIT(15) #define BIT_DIS_CCA_8197F BIT(14) @@ -8602,11 +11212,15 @@ #define BIT_SHIFT_TXQ_NAV_MSK_8197F 8 #define BIT_MASK_TXQ_NAV_MSK_8197F 0xf -#define BIT_TXQ_NAV_MSK_8197F(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8197F) << BIT_SHIFT_TXQ_NAV_MSK_8197F) -#define BITS_TXQ_NAV_MSK_8197F (BIT_MASK_TXQ_NAV_MSK_8197F << BIT_SHIFT_TXQ_NAV_MSK_8197F) +#define BIT_TXQ_NAV_MSK_8197F(x) \ + (((x) & BIT_MASK_TXQ_NAV_MSK_8197F) << BIT_SHIFT_TXQ_NAV_MSK_8197F) +#define BITS_TXQ_NAV_MSK_8197F \ + (BIT_MASK_TXQ_NAV_MSK_8197F << BIT_SHIFT_TXQ_NAV_MSK_8197F) #define BIT_CLEAR_TXQ_NAV_MSK_8197F(x) ((x) & (~BITS_TXQ_NAV_MSK_8197F)) -#define BIT_GET_TXQ_NAV_MSK_8197F(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8197F) & BIT_MASK_TXQ_NAV_MSK_8197F) -#define BIT_SET_TXQ_NAV_MSK_8197F(x, v) (BIT_CLEAR_TXQ_NAV_MSK_8197F(x) | BIT_TXQ_NAV_MSK_8197F(v)) +#define BIT_GET_TXQ_NAV_MSK_8197F(x) \ + (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8197F) & BIT_MASK_TXQ_NAV_MSK_8197F) +#define BIT_SET_TXQ_NAV_MSK_8197F(x, v) \ + (BIT_CLEAR_TXQ_NAV_MSK_8197F(x) | BIT_TXQ_NAV_MSK_8197F(v)) #define BIT_DIS_CW_8197F BIT(7) #define BIT_NAV_END_TXOP_8197F BIT(6) @@ -8684,21 +11298,29 @@ #define BIT_SHIFT_CCA_FILTER_THRS_8197F 8 #define BIT_MASK_CCA_FILTER_THRS_8197F 0xff -#define BIT_CCA_FILTER_THRS_8197F(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8197F) << BIT_SHIFT_CCA_FILTER_THRS_8197F) -#define BITS_CCA_FILTER_THRS_8197F (BIT_MASK_CCA_FILTER_THRS_8197F << BIT_SHIFT_CCA_FILTER_THRS_8197F) +#define BIT_CCA_FILTER_THRS_8197F(x) \ + (((x) & BIT_MASK_CCA_FILTER_THRS_8197F) \ + << BIT_SHIFT_CCA_FILTER_THRS_8197F) +#define BITS_CCA_FILTER_THRS_8197F \ + (BIT_MASK_CCA_FILTER_THRS_8197F << BIT_SHIFT_CCA_FILTER_THRS_8197F) #define BIT_CLEAR_CCA_FILTER_THRS_8197F(x) ((x) & (~BITS_CCA_FILTER_THRS_8197F)) -#define BIT_GET_CCA_FILTER_THRS_8197F(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8197F) & BIT_MASK_CCA_FILTER_THRS_8197F) -#define BIT_SET_CCA_FILTER_THRS_8197F(x, v) (BIT_CLEAR_CCA_FILTER_THRS_8197F(x) | BIT_CCA_FILTER_THRS_8197F(v)) - +#define BIT_GET_CCA_FILTER_THRS_8197F(x) \ + (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8197F) & \ + BIT_MASK_CCA_FILTER_THRS_8197F) +#define BIT_SET_CCA_FILTER_THRS_8197F(x, v) \ + (BIT_CLEAR_CCA_FILTER_THRS_8197F(x) | BIT_CCA_FILTER_THRS_8197F(v)) #define BIT_SHIFT_EDCCA_THRS_8197F 0 #define BIT_MASK_EDCCA_THRS_8197F 0xff -#define BIT_EDCCA_THRS_8197F(x) (((x) & BIT_MASK_EDCCA_THRS_8197F) << BIT_SHIFT_EDCCA_THRS_8197F) -#define BITS_EDCCA_THRS_8197F (BIT_MASK_EDCCA_THRS_8197F << BIT_SHIFT_EDCCA_THRS_8197F) +#define BIT_EDCCA_THRS_8197F(x) \ + (((x) & BIT_MASK_EDCCA_THRS_8197F) << BIT_SHIFT_EDCCA_THRS_8197F) +#define BITS_EDCCA_THRS_8197F \ + (BIT_MASK_EDCCA_THRS_8197F << BIT_SHIFT_EDCCA_THRS_8197F) #define BIT_CLEAR_EDCCA_THRS_8197F(x) ((x) & (~BITS_EDCCA_THRS_8197F)) -#define BIT_GET_EDCCA_THRS_8197F(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8197F) & BIT_MASK_EDCCA_THRS_8197F) -#define BIT_SET_EDCCA_THRS_8197F(x, v) (BIT_CLEAR_EDCCA_THRS_8197F(x) | BIT_EDCCA_THRS_8197F(v)) - +#define BIT_GET_EDCCA_THRS_8197F(x) \ + (((x) >> BIT_SHIFT_EDCCA_THRS_8197F) & BIT_MASK_EDCCA_THRS_8197F) +#define BIT_SET_EDCCA_THRS_8197F(x, v) \ + (BIT_CLEAR_EDCCA_THRS_8197F(x) | BIT_EDCCA_THRS_8197F(v)) /* 2 REG_P2PPS_SPEC_STATE_8197F */ #define BIT_SPEC_POWER_STATE_8197F BIT(7) @@ -8714,109 +11336,163 @@ #define BIT_SHIFT_P2PON_DIS_TXTIME_8197F 0 #define BIT_MASK_P2PON_DIS_TXTIME_8197F 0xff -#define BIT_P2PON_DIS_TXTIME_8197F(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8197F) << BIT_SHIFT_P2PON_DIS_TXTIME_8197F) -#define BITS_P2PON_DIS_TXTIME_8197F (BIT_MASK_P2PON_DIS_TXTIME_8197F << BIT_SHIFT_P2PON_DIS_TXTIME_8197F) -#define BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) ((x) & (~BITS_P2PON_DIS_TXTIME_8197F)) -#define BIT_GET_P2PON_DIS_TXTIME_8197F(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8197F) & BIT_MASK_P2PON_DIS_TXTIME_8197F) -#define BIT_SET_P2PON_DIS_TXTIME_8197F(x, v) (BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) | BIT_P2PON_DIS_TXTIME_8197F(v)) - +#define BIT_P2PON_DIS_TXTIME_8197F(x) \ + (((x) & BIT_MASK_P2PON_DIS_TXTIME_8197F) \ + << BIT_SHIFT_P2PON_DIS_TXTIME_8197F) +#define BITS_P2PON_DIS_TXTIME_8197F \ + (BIT_MASK_P2PON_DIS_TXTIME_8197F << BIT_SHIFT_P2PON_DIS_TXTIME_8197F) +#define BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) \ + ((x) & (~BITS_P2PON_DIS_TXTIME_8197F)) +#define BIT_GET_P2PON_DIS_TXTIME_8197F(x) \ + (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8197F) & \ + BIT_MASK_P2PON_DIS_TXTIME_8197F) +#define BIT_SET_P2PON_DIS_TXTIME_8197F(x, v) \ + (BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) | BIT_P2PON_DIS_TXTIME_8197F(v)) /* 2 REG_QUEUE_INCOL_THR_8197F */ #define BIT_SHIFT_BK_QUEUE_THR_8197F 24 #define BIT_MASK_BK_QUEUE_THR_8197F 0xff -#define BIT_BK_QUEUE_THR_8197F(x) (((x) & BIT_MASK_BK_QUEUE_THR_8197F) << BIT_SHIFT_BK_QUEUE_THR_8197F) -#define BITS_BK_QUEUE_THR_8197F (BIT_MASK_BK_QUEUE_THR_8197F << BIT_SHIFT_BK_QUEUE_THR_8197F) +#define BIT_BK_QUEUE_THR_8197F(x) \ + (((x) & BIT_MASK_BK_QUEUE_THR_8197F) << BIT_SHIFT_BK_QUEUE_THR_8197F) +#define BITS_BK_QUEUE_THR_8197F \ + (BIT_MASK_BK_QUEUE_THR_8197F << BIT_SHIFT_BK_QUEUE_THR_8197F) #define BIT_CLEAR_BK_QUEUE_THR_8197F(x) ((x) & (~BITS_BK_QUEUE_THR_8197F)) -#define BIT_GET_BK_QUEUE_THR_8197F(x) (((x) >> BIT_SHIFT_BK_QUEUE_THR_8197F) & BIT_MASK_BK_QUEUE_THR_8197F) -#define BIT_SET_BK_QUEUE_THR_8197F(x, v) (BIT_CLEAR_BK_QUEUE_THR_8197F(x) | BIT_BK_QUEUE_THR_8197F(v)) - +#define BIT_GET_BK_QUEUE_THR_8197F(x) \ + (((x) >> BIT_SHIFT_BK_QUEUE_THR_8197F) & BIT_MASK_BK_QUEUE_THR_8197F) +#define BIT_SET_BK_QUEUE_THR_8197F(x, v) \ + (BIT_CLEAR_BK_QUEUE_THR_8197F(x) | BIT_BK_QUEUE_THR_8197F(v)) #define BIT_SHIFT_BE_QUEUE_THR_8197F 16 #define BIT_MASK_BE_QUEUE_THR_8197F 0xff -#define BIT_BE_QUEUE_THR_8197F(x) (((x) & BIT_MASK_BE_QUEUE_THR_8197F) << BIT_SHIFT_BE_QUEUE_THR_8197F) -#define BITS_BE_QUEUE_THR_8197F (BIT_MASK_BE_QUEUE_THR_8197F << BIT_SHIFT_BE_QUEUE_THR_8197F) +#define BIT_BE_QUEUE_THR_8197F(x) \ + (((x) & BIT_MASK_BE_QUEUE_THR_8197F) << BIT_SHIFT_BE_QUEUE_THR_8197F) +#define BITS_BE_QUEUE_THR_8197F \ + (BIT_MASK_BE_QUEUE_THR_8197F << BIT_SHIFT_BE_QUEUE_THR_8197F) #define BIT_CLEAR_BE_QUEUE_THR_8197F(x) ((x) & (~BITS_BE_QUEUE_THR_8197F)) -#define BIT_GET_BE_QUEUE_THR_8197F(x) (((x) >> BIT_SHIFT_BE_QUEUE_THR_8197F) & BIT_MASK_BE_QUEUE_THR_8197F) -#define BIT_SET_BE_QUEUE_THR_8197F(x, v) (BIT_CLEAR_BE_QUEUE_THR_8197F(x) | BIT_BE_QUEUE_THR_8197F(v)) - +#define BIT_GET_BE_QUEUE_THR_8197F(x) \ + (((x) >> BIT_SHIFT_BE_QUEUE_THR_8197F) & BIT_MASK_BE_QUEUE_THR_8197F) +#define BIT_SET_BE_QUEUE_THR_8197F(x, v) \ + (BIT_CLEAR_BE_QUEUE_THR_8197F(x) | BIT_BE_QUEUE_THR_8197F(v)) #define BIT_SHIFT_VI_QUEUE_THR_8197F 8 #define BIT_MASK_VI_QUEUE_THR_8197F 0xff -#define BIT_VI_QUEUE_THR_8197F(x) (((x) & BIT_MASK_VI_QUEUE_THR_8197F) << BIT_SHIFT_VI_QUEUE_THR_8197F) -#define BITS_VI_QUEUE_THR_8197F (BIT_MASK_VI_QUEUE_THR_8197F << BIT_SHIFT_VI_QUEUE_THR_8197F) +#define BIT_VI_QUEUE_THR_8197F(x) \ + (((x) & BIT_MASK_VI_QUEUE_THR_8197F) << BIT_SHIFT_VI_QUEUE_THR_8197F) +#define BITS_VI_QUEUE_THR_8197F \ + (BIT_MASK_VI_QUEUE_THR_8197F << BIT_SHIFT_VI_QUEUE_THR_8197F) #define BIT_CLEAR_VI_QUEUE_THR_8197F(x) ((x) & (~BITS_VI_QUEUE_THR_8197F)) -#define BIT_GET_VI_QUEUE_THR_8197F(x) (((x) >> BIT_SHIFT_VI_QUEUE_THR_8197F) & BIT_MASK_VI_QUEUE_THR_8197F) -#define BIT_SET_VI_QUEUE_THR_8197F(x, v) (BIT_CLEAR_VI_QUEUE_THR_8197F(x) | BIT_VI_QUEUE_THR_8197F(v)) - +#define BIT_GET_VI_QUEUE_THR_8197F(x) \ + (((x) >> BIT_SHIFT_VI_QUEUE_THR_8197F) & BIT_MASK_VI_QUEUE_THR_8197F) +#define BIT_SET_VI_QUEUE_THR_8197F(x, v) \ + (BIT_CLEAR_VI_QUEUE_THR_8197F(x) | BIT_VI_QUEUE_THR_8197F(v)) #define BIT_SHIFT_VO_QUEUE_THR_8197F 0 #define BIT_MASK_VO_QUEUE_THR_8197F 0xff -#define BIT_VO_QUEUE_THR_8197F(x) (((x) & BIT_MASK_VO_QUEUE_THR_8197F) << BIT_SHIFT_VO_QUEUE_THR_8197F) -#define BITS_VO_QUEUE_THR_8197F (BIT_MASK_VO_QUEUE_THR_8197F << BIT_SHIFT_VO_QUEUE_THR_8197F) +#define BIT_VO_QUEUE_THR_8197F(x) \ + (((x) & BIT_MASK_VO_QUEUE_THR_8197F) << BIT_SHIFT_VO_QUEUE_THR_8197F) +#define BITS_VO_QUEUE_THR_8197F \ + (BIT_MASK_VO_QUEUE_THR_8197F << BIT_SHIFT_VO_QUEUE_THR_8197F) #define BIT_CLEAR_VO_QUEUE_THR_8197F(x) ((x) & (~BITS_VO_QUEUE_THR_8197F)) -#define BIT_GET_VO_QUEUE_THR_8197F(x) (((x) >> BIT_SHIFT_VO_QUEUE_THR_8197F) & BIT_MASK_VO_QUEUE_THR_8197F) -#define BIT_SET_VO_QUEUE_THR_8197F(x, v) (BIT_CLEAR_VO_QUEUE_THR_8197F(x) | BIT_VO_QUEUE_THR_8197F(v)) - +#define BIT_GET_VO_QUEUE_THR_8197F(x) \ + (((x) >> BIT_SHIFT_VO_QUEUE_THR_8197F) & BIT_MASK_VO_QUEUE_THR_8197F) +#define BIT_SET_VO_QUEUE_THR_8197F(x, v) \ + (BIT_CLEAR_VO_QUEUE_THR_8197F(x) | BIT_VO_QUEUE_THR_8197F(v)) /* 2 REG_QUEUE_INCOL_EN_8197F */ #define BIT_QUEUE_INCOL_EN_8197F BIT(16) #define BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F 12 #define BIT_MASK_BK_TRIGGER_NUM_V1_8197F 0xf -#define BIT_BK_TRIGGER_NUM_V1_8197F(x) (((x) & BIT_MASK_BK_TRIGGER_NUM_V1_8197F) << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) -#define BITS_BK_TRIGGER_NUM_V1_8197F (BIT_MASK_BK_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) -#define BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) ((x) & (~BITS_BK_TRIGGER_NUM_V1_8197F)) -#define BIT_GET_BK_TRIGGER_NUM_V1_8197F(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) & BIT_MASK_BK_TRIGGER_NUM_V1_8197F) -#define BIT_SET_BK_TRIGGER_NUM_V1_8197F(x, v) (BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) | BIT_BK_TRIGGER_NUM_V1_8197F(v)) - +#define BIT_BK_TRIGGER_NUM_V1_8197F(x) \ + (((x) & BIT_MASK_BK_TRIGGER_NUM_V1_8197F) \ + << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) +#define BITS_BK_TRIGGER_NUM_V1_8197F \ + (BIT_MASK_BK_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) +#define BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) \ + ((x) & (~BITS_BK_TRIGGER_NUM_V1_8197F)) +#define BIT_GET_BK_TRIGGER_NUM_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) & \ + BIT_MASK_BK_TRIGGER_NUM_V1_8197F) +#define BIT_SET_BK_TRIGGER_NUM_V1_8197F(x, v) \ + (BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) | BIT_BK_TRIGGER_NUM_V1_8197F(v)) #define BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F 8 #define BIT_MASK_BE_TRIGGER_NUM_V1_8197F 0xf -#define BIT_BE_TRIGGER_NUM_V1_8197F(x) (((x) & BIT_MASK_BE_TRIGGER_NUM_V1_8197F) << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) -#define BITS_BE_TRIGGER_NUM_V1_8197F (BIT_MASK_BE_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) -#define BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) ((x) & (~BITS_BE_TRIGGER_NUM_V1_8197F)) -#define BIT_GET_BE_TRIGGER_NUM_V1_8197F(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) & BIT_MASK_BE_TRIGGER_NUM_V1_8197F) -#define BIT_SET_BE_TRIGGER_NUM_V1_8197F(x, v) (BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) | BIT_BE_TRIGGER_NUM_V1_8197F(v)) - +#define BIT_BE_TRIGGER_NUM_V1_8197F(x) \ + (((x) & BIT_MASK_BE_TRIGGER_NUM_V1_8197F) \ + << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) +#define BITS_BE_TRIGGER_NUM_V1_8197F \ + (BIT_MASK_BE_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) +#define BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) \ + ((x) & (~BITS_BE_TRIGGER_NUM_V1_8197F)) +#define BIT_GET_BE_TRIGGER_NUM_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) & \ + BIT_MASK_BE_TRIGGER_NUM_V1_8197F) +#define BIT_SET_BE_TRIGGER_NUM_V1_8197F(x, v) \ + (BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) | BIT_BE_TRIGGER_NUM_V1_8197F(v)) #define BIT_SHIFT_VI_TRIGGER_NUM_8197F 4 #define BIT_MASK_VI_TRIGGER_NUM_8197F 0xf -#define BIT_VI_TRIGGER_NUM_8197F(x) (((x) & BIT_MASK_VI_TRIGGER_NUM_8197F) << BIT_SHIFT_VI_TRIGGER_NUM_8197F) -#define BITS_VI_TRIGGER_NUM_8197F (BIT_MASK_VI_TRIGGER_NUM_8197F << BIT_SHIFT_VI_TRIGGER_NUM_8197F) +#define BIT_VI_TRIGGER_NUM_8197F(x) \ + (((x) & BIT_MASK_VI_TRIGGER_NUM_8197F) \ + << BIT_SHIFT_VI_TRIGGER_NUM_8197F) +#define BITS_VI_TRIGGER_NUM_8197F \ + (BIT_MASK_VI_TRIGGER_NUM_8197F << BIT_SHIFT_VI_TRIGGER_NUM_8197F) #define BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) ((x) & (~BITS_VI_TRIGGER_NUM_8197F)) -#define BIT_GET_VI_TRIGGER_NUM_8197F(x) (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8197F) & BIT_MASK_VI_TRIGGER_NUM_8197F) -#define BIT_SET_VI_TRIGGER_NUM_8197F(x, v) (BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) | BIT_VI_TRIGGER_NUM_8197F(v)) - +#define BIT_GET_VI_TRIGGER_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8197F) & \ + BIT_MASK_VI_TRIGGER_NUM_8197F) +#define BIT_SET_VI_TRIGGER_NUM_8197F(x, v) \ + (BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) | BIT_VI_TRIGGER_NUM_8197F(v)) #define BIT_SHIFT_VO_TRIGGER_NUM_8197F 0 #define BIT_MASK_VO_TRIGGER_NUM_8197F 0xf -#define BIT_VO_TRIGGER_NUM_8197F(x) (((x) & BIT_MASK_VO_TRIGGER_NUM_8197F) << BIT_SHIFT_VO_TRIGGER_NUM_8197F) -#define BITS_VO_TRIGGER_NUM_8197F (BIT_MASK_VO_TRIGGER_NUM_8197F << BIT_SHIFT_VO_TRIGGER_NUM_8197F) +#define BIT_VO_TRIGGER_NUM_8197F(x) \ + (((x) & BIT_MASK_VO_TRIGGER_NUM_8197F) \ + << BIT_SHIFT_VO_TRIGGER_NUM_8197F) +#define BITS_VO_TRIGGER_NUM_8197F \ + (BIT_MASK_VO_TRIGGER_NUM_8197F << BIT_SHIFT_VO_TRIGGER_NUM_8197F) #define BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) ((x) & (~BITS_VO_TRIGGER_NUM_8197F)) -#define BIT_GET_VO_TRIGGER_NUM_8197F(x) (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8197F) & BIT_MASK_VO_TRIGGER_NUM_8197F) -#define BIT_SET_VO_TRIGGER_NUM_8197F(x, v) (BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) | BIT_VO_TRIGGER_NUM_8197F(v)) - +#define BIT_GET_VO_TRIGGER_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8197F) & \ + BIT_MASK_VO_TRIGGER_NUM_8197F) +#define BIT_SET_VO_TRIGGER_NUM_8197F(x, v) \ + (BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) | BIT_VO_TRIGGER_NUM_8197F(v)) /* 2 REG_TBTT_PROHIBIT_8197F */ #define BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F 8 #define BIT_MASK_TBTT_HOLD_TIME_AP_8197F 0xfff -#define BIT_TBTT_HOLD_TIME_AP_8197F(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8197F) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) -#define BITS_TBTT_HOLD_TIME_AP_8197F (BIT_MASK_TBTT_HOLD_TIME_AP_8197F << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) -#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) ((x) & (~BITS_TBTT_HOLD_TIME_AP_8197F)) -#define BIT_GET_TBTT_HOLD_TIME_AP_8197F(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) & BIT_MASK_TBTT_HOLD_TIME_AP_8197F) -#define BIT_SET_TBTT_HOLD_TIME_AP_8197F(x, v) (BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) | BIT_TBTT_HOLD_TIME_AP_8197F(v)) - +#define BIT_TBTT_HOLD_TIME_AP_8197F(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8197F) \ + << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) +#define BITS_TBTT_HOLD_TIME_AP_8197F \ + (BIT_MASK_TBTT_HOLD_TIME_AP_8197F << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) +#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) \ + ((x) & (~BITS_TBTT_HOLD_TIME_AP_8197F)) +#define BIT_GET_TBTT_HOLD_TIME_AP_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) & \ + BIT_MASK_TBTT_HOLD_TIME_AP_8197F) +#define BIT_SET_TBTT_HOLD_TIME_AP_8197F(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) | BIT_TBTT_HOLD_TIME_AP_8197F(v)) #define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F 0 #define BIT_MASK_TBTT_PROHIBIT_SETUP_8197F 0xf -#define BIT_TBTT_PROHIBIT_SETUP_8197F(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8197F) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) -#define BITS_TBTT_PROHIBIT_SETUP_8197F (BIT_MASK_TBTT_PROHIBIT_SETUP_8197F << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) -#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8197F)) -#define BIT_GET_TBTT_PROHIBIT_SETUP_8197F(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) & BIT_MASK_TBTT_PROHIBIT_SETUP_8197F) -#define BIT_SET_TBTT_PROHIBIT_SETUP_8197F(x, v) (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) | BIT_TBTT_PROHIBIT_SETUP_8197F(v)) - +#define BIT_TBTT_PROHIBIT_SETUP_8197F(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8197F) \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) +#define BITS_TBTT_PROHIBIT_SETUP_8197F \ + (BIT_MASK_TBTT_PROHIBIT_SETUP_8197F \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8197F)) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) & \ + BIT_MASK_TBTT_PROHIBIT_SETUP_8197F) +#define BIT_SET_TBTT_PROHIBIT_SETUP_8197F(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) | \ + BIT_TBTT_PROHIBIT_SETUP_8197F(v)) /* 2 REG_P2PPS_STATE_8197F */ #define BIT_POWER_STATE_8197F BIT(7) @@ -8832,81 +11508,112 @@ #define BIT_SHIFT_RD_NAV_PROT_NXT_8197F 0 #define BIT_MASK_RD_NAV_PROT_NXT_8197F 0xffff -#define BIT_RD_NAV_PROT_NXT_8197F(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8197F) << BIT_SHIFT_RD_NAV_PROT_NXT_8197F) -#define BITS_RD_NAV_PROT_NXT_8197F (BIT_MASK_RD_NAV_PROT_NXT_8197F << BIT_SHIFT_RD_NAV_PROT_NXT_8197F) +#define BIT_RD_NAV_PROT_NXT_8197F(x) \ + (((x) & BIT_MASK_RD_NAV_PROT_NXT_8197F) \ + << BIT_SHIFT_RD_NAV_PROT_NXT_8197F) +#define BITS_RD_NAV_PROT_NXT_8197F \ + (BIT_MASK_RD_NAV_PROT_NXT_8197F << BIT_SHIFT_RD_NAV_PROT_NXT_8197F) #define BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8197F)) -#define BIT_GET_RD_NAV_PROT_NXT_8197F(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8197F) & BIT_MASK_RD_NAV_PROT_NXT_8197F) -#define BIT_SET_RD_NAV_PROT_NXT_8197F(x, v) (BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) | BIT_RD_NAV_PROT_NXT_8197F(v)) - +#define BIT_GET_RD_NAV_PROT_NXT_8197F(x) \ + (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8197F) & \ + BIT_MASK_RD_NAV_PROT_NXT_8197F) +#define BIT_SET_RD_NAV_PROT_NXT_8197F(x, v) \ + (BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) | BIT_RD_NAV_PROT_NXT_8197F(v)) /* 2 REG_NAV_PROT_LEN_8197F */ #define BIT_SHIFT_NAV_PROT_LEN_8197F 0 #define BIT_MASK_NAV_PROT_LEN_8197F 0xffff -#define BIT_NAV_PROT_LEN_8197F(x) (((x) & BIT_MASK_NAV_PROT_LEN_8197F) << BIT_SHIFT_NAV_PROT_LEN_8197F) -#define BITS_NAV_PROT_LEN_8197F (BIT_MASK_NAV_PROT_LEN_8197F << BIT_SHIFT_NAV_PROT_LEN_8197F) +#define BIT_NAV_PROT_LEN_8197F(x) \ + (((x) & BIT_MASK_NAV_PROT_LEN_8197F) << BIT_SHIFT_NAV_PROT_LEN_8197F) +#define BITS_NAV_PROT_LEN_8197F \ + (BIT_MASK_NAV_PROT_LEN_8197F << BIT_SHIFT_NAV_PROT_LEN_8197F) #define BIT_CLEAR_NAV_PROT_LEN_8197F(x) ((x) & (~BITS_NAV_PROT_LEN_8197F)) -#define BIT_GET_NAV_PROT_LEN_8197F(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8197F) & BIT_MASK_NAV_PROT_LEN_8197F) -#define BIT_SET_NAV_PROT_LEN_8197F(x, v) (BIT_CLEAR_NAV_PROT_LEN_8197F(x) | BIT_NAV_PROT_LEN_8197F(v)) - +#define BIT_GET_NAV_PROT_LEN_8197F(x) \ + (((x) >> BIT_SHIFT_NAV_PROT_LEN_8197F) & BIT_MASK_NAV_PROT_LEN_8197F) +#define BIT_SET_NAV_PROT_LEN_8197F(x, v) \ + (BIT_CLEAR_NAV_PROT_LEN_8197F(x) | BIT_NAV_PROT_LEN_8197F(v)) /* 2 REG_FTM_CTRL_8197F */ #define BIT_SHIFT_FTM_TSF_R2T_PORT_8197F 22 #define BIT_MASK_FTM_TSF_R2T_PORT_8197F 0x7 -#define BIT_FTM_TSF_R2T_PORT_8197F(x) (((x) & BIT_MASK_FTM_TSF_R2T_PORT_8197F) << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) -#define BITS_FTM_TSF_R2T_PORT_8197F (BIT_MASK_FTM_TSF_R2T_PORT_8197F << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) -#define BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) ((x) & (~BITS_FTM_TSF_R2T_PORT_8197F)) -#define BIT_GET_FTM_TSF_R2T_PORT_8197F(x) (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) & BIT_MASK_FTM_TSF_R2T_PORT_8197F) -#define BIT_SET_FTM_TSF_R2T_PORT_8197F(x, v) (BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) | BIT_FTM_TSF_R2T_PORT_8197F(v)) - +#define BIT_FTM_TSF_R2T_PORT_8197F(x) \ + (((x) & BIT_MASK_FTM_TSF_R2T_PORT_8197F) \ + << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) +#define BITS_FTM_TSF_R2T_PORT_8197F \ + (BIT_MASK_FTM_TSF_R2T_PORT_8197F << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) +#define BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) \ + ((x) & (~BITS_FTM_TSF_R2T_PORT_8197F)) +#define BIT_GET_FTM_TSF_R2T_PORT_8197F(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) & \ + BIT_MASK_FTM_TSF_R2T_PORT_8197F) +#define BIT_SET_FTM_TSF_R2T_PORT_8197F(x, v) \ + (BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) | BIT_FTM_TSF_R2T_PORT_8197F(v)) #define BIT_SHIFT_FTM_TSF_T2R_PORT_8197F 19 #define BIT_MASK_FTM_TSF_T2R_PORT_8197F 0x7 -#define BIT_FTM_TSF_T2R_PORT_8197F(x) (((x) & BIT_MASK_FTM_TSF_T2R_PORT_8197F) << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) -#define BITS_FTM_TSF_T2R_PORT_8197F (BIT_MASK_FTM_TSF_T2R_PORT_8197F << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) -#define BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) ((x) & (~BITS_FTM_TSF_T2R_PORT_8197F)) -#define BIT_GET_FTM_TSF_T2R_PORT_8197F(x) (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) & BIT_MASK_FTM_TSF_T2R_PORT_8197F) -#define BIT_SET_FTM_TSF_T2R_PORT_8197F(x, v) (BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) | BIT_FTM_TSF_T2R_PORT_8197F(v)) - +#define BIT_FTM_TSF_T2R_PORT_8197F(x) \ + (((x) & BIT_MASK_FTM_TSF_T2R_PORT_8197F) \ + << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) +#define BITS_FTM_TSF_T2R_PORT_8197F \ + (BIT_MASK_FTM_TSF_T2R_PORT_8197F << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) +#define BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) \ + ((x) & (~BITS_FTM_TSF_T2R_PORT_8197F)) +#define BIT_GET_FTM_TSF_T2R_PORT_8197F(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) & \ + BIT_MASK_FTM_TSF_T2R_PORT_8197F) +#define BIT_SET_FTM_TSF_T2R_PORT_8197F(x, v) \ + (BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) | BIT_FTM_TSF_T2R_PORT_8197F(v)) #define BIT_SHIFT_FTM_PTT_PORT_8197F 16 #define BIT_MASK_FTM_PTT_PORT_8197F 0x7 -#define BIT_FTM_PTT_PORT_8197F(x) (((x) & BIT_MASK_FTM_PTT_PORT_8197F) << BIT_SHIFT_FTM_PTT_PORT_8197F) -#define BITS_FTM_PTT_PORT_8197F (BIT_MASK_FTM_PTT_PORT_8197F << BIT_SHIFT_FTM_PTT_PORT_8197F) +#define BIT_FTM_PTT_PORT_8197F(x) \ + (((x) & BIT_MASK_FTM_PTT_PORT_8197F) << BIT_SHIFT_FTM_PTT_PORT_8197F) +#define BITS_FTM_PTT_PORT_8197F \ + (BIT_MASK_FTM_PTT_PORT_8197F << BIT_SHIFT_FTM_PTT_PORT_8197F) #define BIT_CLEAR_FTM_PTT_PORT_8197F(x) ((x) & (~BITS_FTM_PTT_PORT_8197F)) -#define BIT_GET_FTM_PTT_PORT_8197F(x) (((x) >> BIT_SHIFT_FTM_PTT_PORT_8197F) & BIT_MASK_FTM_PTT_PORT_8197F) -#define BIT_SET_FTM_PTT_PORT_8197F(x, v) (BIT_CLEAR_FTM_PTT_PORT_8197F(x) | BIT_FTM_PTT_PORT_8197F(v)) - +#define BIT_GET_FTM_PTT_PORT_8197F(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_PORT_8197F) & BIT_MASK_FTM_PTT_PORT_8197F) +#define BIT_SET_FTM_PTT_PORT_8197F(x, v) \ + (BIT_CLEAR_FTM_PTT_PORT_8197F(x) | BIT_FTM_PTT_PORT_8197F(v)) #define BIT_SHIFT_FTM_PTT_8197F 0 #define BIT_MASK_FTM_PTT_8197F 0xffff -#define BIT_FTM_PTT_8197F(x) (((x) & BIT_MASK_FTM_PTT_8197F) << BIT_SHIFT_FTM_PTT_8197F) +#define BIT_FTM_PTT_8197F(x) \ + (((x) & BIT_MASK_FTM_PTT_8197F) << BIT_SHIFT_FTM_PTT_8197F) #define BITS_FTM_PTT_8197F (BIT_MASK_FTM_PTT_8197F << BIT_SHIFT_FTM_PTT_8197F) #define BIT_CLEAR_FTM_PTT_8197F(x) ((x) & (~BITS_FTM_PTT_8197F)) -#define BIT_GET_FTM_PTT_8197F(x) (((x) >> BIT_SHIFT_FTM_PTT_8197F) & BIT_MASK_FTM_PTT_8197F) -#define BIT_SET_FTM_PTT_8197F(x, v) (BIT_CLEAR_FTM_PTT_8197F(x) | BIT_FTM_PTT_8197F(v)) - +#define BIT_GET_FTM_PTT_8197F(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_8197F) & BIT_MASK_FTM_PTT_8197F) +#define BIT_SET_FTM_PTT_8197F(x, v) \ + (BIT_CLEAR_FTM_PTT_8197F(x) | BIT_FTM_PTT_8197F(v)) /* 2 REG_FTM_TSF_CNT_8197F */ #define BIT_SHIFT_FTM_TSF_R2T_8197F 16 #define BIT_MASK_FTM_TSF_R2T_8197F 0xffff -#define BIT_FTM_TSF_R2T_8197F(x) (((x) & BIT_MASK_FTM_TSF_R2T_8197F) << BIT_SHIFT_FTM_TSF_R2T_8197F) -#define BITS_FTM_TSF_R2T_8197F (BIT_MASK_FTM_TSF_R2T_8197F << BIT_SHIFT_FTM_TSF_R2T_8197F) +#define BIT_FTM_TSF_R2T_8197F(x) \ + (((x) & BIT_MASK_FTM_TSF_R2T_8197F) << BIT_SHIFT_FTM_TSF_R2T_8197F) +#define BITS_FTM_TSF_R2T_8197F \ + (BIT_MASK_FTM_TSF_R2T_8197F << BIT_SHIFT_FTM_TSF_R2T_8197F) #define BIT_CLEAR_FTM_TSF_R2T_8197F(x) ((x) & (~BITS_FTM_TSF_R2T_8197F)) -#define BIT_GET_FTM_TSF_R2T_8197F(x) (((x) >> BIT_SHIFT_FTM_TSF_R2T_8197F) & BIT_MASK_FTM_TSF_R2T_8197F) -#define BIT_SET_FTM_TSF_R2T_8197F(x, v) (BIT_CLEAR_FTM_TSF_R2T_8197F(x) | BIT_FTM_TSF_R2T_8197F(v)) - +#define BIT_GET_FTM_TSF_R2T_8197F(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_R2T_8197F) & BIT_MASK_FTM_TSF_R2T_8197F) +#define BIT_SET_FTM_TSF_R2T_8197F(x, v) \ + (BIT_CLEAR_FTM_TSF_R2T_8197F(x) | BIT_FTM_TSF_R2T_8197F(v)) #define BIT_SHIFT_FTM_TSF_T2R_8197F 0 #define BIT_MASK_FTM_TSF_T2R_8197F 0xffff -#define BIT_FTM_TSF_T2R_8197F(x) (((x) & BIT_MASK_FTM_TSF_T2R_8197F) << BIT_SHIFT_FTM_TSF_T2R_8197F) -#define BITS_FTM_TSF_T2R_8197F (BIT_MASK_FTM_TSF_T2R_8197F << BIT_SHIFT_FTM_TSF_T2R_8197F) +#define BIT_FTM_TSF_T2R_8197F(x) \ + (((x) & BIT_MASK_FTM_TSF_T2R_8197F) << BIT_SHIFT_FTM_TSF_T2R_8197F) +#define BITS_FTM_TSF_T2R_8197F \ + (BIT_MASK_FTM_TSF_T2R_8197F << BIT_SHIFT_FTM_TSF_T2R_8197F) #define BIT_CLEAR_FTM_TSF_T2R_8197F(x) ((x) & (~BITS_FTM_TSF_T2R_8197F)) -#define BIT_GET_FTM_TSF_T2R_8197F(x) (((x) >> BIT_SHIFT_FTM_TSF_T2R_8197F) & BIT_MASK_FTM_TSF_T2R_8197F) -#define BIT_SET_FTM_TSF_T2R_8197F(x, v) (BIT_CLEAR_FTM_TSF_T2R_8197F(x) | BIT_FTM_TSF_T2R_8197F(v)) - +#define BIT_GET_FTM_TSF_T2R_8197F(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_T2R_8197F) & BIT_MASK_FTM_TSF_T2R_8197F) +#define BIT_SET_FTM_TSF_T2R_8197F(x, v) \ + (BIT_CLEAR_FTM_TSF_T2R_8197F(x) | BIT_FTM_TSF_T2R_8197F(v)) /* 2 REG_BCN_CTRL_8197F */ #define BIT_DIS_RX_BSSID_FIT_8197F BIT(6) @@ -8930,12 +11637,15 @@ #define BIT_SHIFT_MBID_BCN_NUM_8197F 0 #define BIT_MASK_MBID_BCN_NUM_8197F 0x7 -#define BIT_MBID_BCN_NUM_8197F(x) (((x) & BIT_MASK_MBID_BCN_NUM_8197F) << BIT_SHIFT_MBID_BCN_NUM_8197F) -#define BITS_MBID_BCN_NUM_8197F (BIT_MASK_MBID_BCN_NUM_8197F << BIT_SHIFT_MBID_BCN_NUM_8197F) +#define BIT_MBID_BCN_NUM_8197F(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_8197F) << BIT_SHIFT_MBID_BCN_NUM_8197F) +#define BITS_MBID_BCN_NUM_8197F \ + (BIT_MASK_MBID_BCN_NUM_8197F << BIT_SHIFT_MBID_BCN_NUM_8197F) #define BIT_CLEAR_MBID_BCN_NUM_8197F(x) ((x) & (~BITS_MBID_BCN_NUM_8197F)) -#define BIT_GET_MBID_BCN_NUM_8197F(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8197F) & BIT_MASK_MBID_BCN_NUM_8197F) -#define BIT_SET_MBID_BCN_NUM_8197F(x, v) (BIT_CLEAR_MBID_BCN_NUM_8197F(x) | BIT_MBID_BCN_NUM_8197F(v)) - +#define BIT_GET_MBID_BCN_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_8197F) & BIT_MASK_MBID_BCN_NUM_8197F) +#define BIT_SET_MBID_BCN_NUM_8197F(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_8197F(x) | BIT_MBID_BCN_NUM_8197F(v)) /* 2 REG_DUAL_TSF_RST_8197F */ #define BIT_FREECNT_RST_8197F BIT(5) @@ -8949,207 +11659,294 @@ #define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F 28 #define BIT_MASK_BCN_TIMER_SEL_FWRD_8197F 0x7 -#define BIT_BCN_TIMER_SEL_FWRD_8197F(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8197F) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) -#define BITS_BCN_TIMER_SEL_FWRD_8197F (BIT_MASK_BCN_TIMER_SEL_FWRD_8197F << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) -#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8197F)) -#define BIT_GET_BCN_TIMER_SEL_FWRD_8197F(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) & BIT_MASK_BCN_TIMER_SEL_FWRD_8197F) -#define BIT_SET_BCN_TIMER_SEL_FWRD_8197F(x, v) (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) | BIT_BCN_TIMER_SEL_FWRD_8197F(v)) - +#define BIT_BCN_TIMER_SEL_FWRD_8197F(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8197F) \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) +#define BITS_BCN_TIMER_SEL_FWRD_8197F \ + (BIT_MASK_BCN_TIMER_SEL_FWRD_8197F \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) \ + ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8197F)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) & \ + BIT_MASK_BCN_TIMER_SEL_FWRD_8197F) +#define BIT_SET_BCN_TIMER_SEL_FWRD_8197F(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) | \ + BIT_BCN_TIMER_SEL_FWRD_8197F(v)) #define BIT_SHIFT_BCN_SPACE_CLINT0_8197F 16 #define BIT_MASK_BCN_SPACE_CLINT0_8197F 0xfff -#define BIT_BCN_SPACE_CLINT0_8197F(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8197F) << BIT_SHIFT_BCN_SPACE_CLINT0_8197F) -#define BITS_BCN_SPACE_CLINT0_8197F (BIT_MASK_BCN_SPACE_CLINT0_8197F << BIT_SHIFT_BCN_SPACE_CLINT0_8197F) -#define BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) ((x) & (~BITS_BCN_SPACE_CLINT0_8197F)) -#define BIT_GET_BCN_SPACE_CLINT0_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8197F) & BIT_MASK_BCN_SPACE_CLINT0_8197F) -#define BIT_SET_BCN_SPACE_CLINT0_8197F(x, v) (BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) | BIT_BCN_SPACE_CLINT0_8197F(v)) - +#define BIT_BCN_SPACE_CLINT0_8197F(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT0_8197F) \ + << BIT_SHIFT_BCN_SPACE_CLINT0_8197F) +#define BITS_BCN_SPACE_CLINT0_8197F \ + (BIT_MASK_BCN_SPACE_CLINT0_8197F << BIT_SHIFT_BCN_SPACE_CLINT0_8197F) +#define BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT0_8197F)) +#define BIT_GET_BCN_SPACE_CLINT0_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8197F) & \ + BIT_MASK_BCN_SPACE_CLINT0_8197F) +#define BIT_SET_BCN_SPACE_CLINT0_8197F(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) | BIT_BCN_SPACE_CLINT0_8197F(v)) #define BIT_SHIFT_BCN_SPACE0_8197F 0 #define BIT_MASK_BCN_SPACE0_8197F 0xffff -#define BIT_BCN_SPACE0_8197F(x) (((x) & BIT_MASK_BCN_SPACE0_8197F) << BIT_SHIFT_BCN_SPACE0_8197F) -#define BITS_BCN_SPACE0_8197F (BIT_MASK_BCN_SPACE0_8197F << BIT_SHIFT_BCN_SPACE0_8197F) +#define BIT_BCN_SPACE0_8197F(x) \ + (((x) & BIT_MASK_BCN_SPACE0_8197F) << BIT_SHIFT_BCN_SPACE0_8197F) +#define BITS_BCN_SPACE0_8197F \ + (BIT_MASK_BCN_SPACE0_8197F << BIT_SHIFT_BCN_SPACE0_8197F) #define BIT_CLEAR_BCN_SPACE0_8197F(x) ((x) & (~BITS_BCN_SPACE0_8197F)) -#define BIT_GET_BCN_SPACE0_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8197F) & BIT_MASK_BCN_SPACE0_8197F) -#define BIT_SET_BCN_SPACE0_8197F(x, v) (BIT_CLEAR_BCN_SPACE0_8197F(x) | BIT_BCN_SPACE0_8197F(v)) - +#define BIT_GET_BCN_SPACE0_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE0_8197F) & BIT_MASK_BCN_SPACE0_8197F) +#define BIT_SET_BCN_SPACE0_8197F(x, v) \ + (BIT_CLEAR_BCN_SPACE0_8197F(x) | BIT_BCN_SPACE0_8197F(v)) /* 2 REG_DRVERLYINT_8197F */ #define BIT_SHIFT_DRVERLYITV_8197F 0 #define BIT_MASK_DRVERLYITV_8197F 0xff -#define BIT_DRVERLYITV_8197F(x) (((x) & BIT_MASK_DRVERLYITV_8197F) << BIT_SHIFT_DRVERLYITV_8197F) -#define BITS_DRVERLYITV_8197F (BIT_MASK_DRVERLYITV_8197F << BIT_SHIFT_DRVERLYITV_8197F) +#define BIT_DRVERLYITV_8197F(x) \ + (((x) & BIT_MASK_DRVERLYITV_8197F) << BIT_SHIFT_DRVERLYITV_8197F) +#define BITS_DRVERLYITV_8197F \ + (BIT_MASK_DRVERLYITV_8197F << BIT_SHIFT_DRVERLYITV_8197F) #define BIT_CLEAR_DRVERLYITV_8197F(x) ((x) & (~BITS_DRVERLYITV_8197F)) -#define BIT_GET_DRVERLYITV_8197F(x) (((x) >> BIT_SHIFT_DRVERLYITV_8197F) & BIT_MASK_DRVERLYITV_8197F) -#define BIT_SET_DRVERLYITV_8197F(x, v) (BIT_CLEAR_DRVERLYITV_8197F(x) | BIT_DRVERLYITV_8197F(v)) - +#define BIT_GET_DRVERLYITV_8197F(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV_8197F) & BIT_MASK_DRVERLYITV_8197F) +#define BIT_SET_DRVERLYITV_8197F(x, v) \ + (BIT_CLEAR_DRVERLYITV_8197F(x) | BIT_DRVERLYITV_8197F(v)) /* 2 REG_BCNDMATIM_8197F */ #define BIT_SHIFT_BCNDMATIM_8197F 0 #define BIT_MASK_BCNDMATIM_8197F 0xff -#define BIT_BCNDMATIM_8197F(x) (((x) & BIT_MASK_BCNDMATIM_8197F) << BIT_SHIFT_BCNDMATIM_8197F) -#define BITS_BCNDMATIM_8197F (BIT_MASK_BCNDMATIM_8197F << BIT_SHIFT_BCNDMATIM_8197F) +#define BIT_BCNDMATIM_8197F(x) \ + (((x) & BIT_MASK_BCNDMATIM_8197F) << BIT_SHIFT_BCNDMATIM_8197F) +#define BITS_BCNDMATIM_8197F \ + (BIT_MASK_BCNDMATIM_8197F << BIT_SHIFT_BCNDMATIM_8197F) #define BIT_CLEAR_BCNDMATIM_8197F(x) ((x) & (~BITS_BCNDMATIM_8197F)) -#define BIT_GET_BCNDMATIM_8197F(x) (((x) >> BIT_SHIFT_BCNDMATIM_8197F) & BIT_MASK_BCNDMATIM_8197F) -#define BIT_SET_BCNDMATIM_8197F(x, v) (BIT_CLEAR_BCNDMATIM_8197F(x) | BIT_BCNDMATIM_8197F(v)) - +#define BIT_GET_BCNDMATIM_8197F(x) \ + (((x) >> BIT_SHIFT_BCNDMATIM_8197F) & BIT_MASK_BCNDMATIM_8197F) +#define BIT_SET_BCNDMATIM_8197F(x, v) \ + (BIT_CLEAR_BCNDMATIM_8197F(x) | BIT_BCNDMATIM_8197F(v)) /* 2 REG_ATIMWND_8197F */ #define BIT_SHIFT_ATIMWND0_8197F 0 #define BIT_MASK_ATIMWND0_8197F 0xffff -#define BIT_ATIMWND0_8197F(x) (((x) & BIT_MASK_ATIMWND0_8197F) << BIT_SHIFT_ATIMWND0_8197F) -#define BITS_ATIMWND0_8197F (BIT_MASK_ATIMWND0_8197F << BIT_SHIFT_ATIMWND0_8197F) +#define BIT_ATIMWND0_8197F(x) \ + (((x) & BIT_MASK_ATIMWND0_8197F) << BIT_SHIFT_ATIMWND0_8197F) +#define BITS_ATIMWND0_8197F \ + (BIT_MASK_ATIMWND0_8197F << BIT_SHIFT_ATIMWND0_8197F) #define BIT_CLEAR_ATIMWND0_8197F(x) ((x) & (~BITS_ATIMWND0_8197F)) -#define BIT_GET_ATIMWND0_8197F(x) (((x) >> BIT_SHIFT_ATIMWND0_8197F) & BIT_MASK_ATIMWND0_8197F) -#define BIT_SET_ATIMWND0_8197F(x, v) (BIT_CLEAR_ATIMWND0_8197F(x) | BIT_ATIMWND0_8197F(v)) - +#define BIT_GET_ATIMWND0_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND0_8197F) & BIT_MASK_ATIMWND0_8197F) +#define BIT_SET_ATIMWND0_8197F(x, v) \ + (BIT_CLEAR_ATIMWND0_8197F(x) | BIT_ATIMWND0_8197F(v)) /* 2 REG_USTIME_TSF_8197F */ #define BIT_SHIFT_USTIME_TSF_V1_8197F 0 #define BIT_MASK_USTIME_TSF_V1_8197F 0xff -#define BIT_USTIME_TSF_V1_8197F(x) (((x) & BIT_MASK_USTIME_TSF_V1_8197F) << BIT_SHIFT_USTIME_TSF_V1_8197F) -#define BITS_USTIME_TSF_V1_8197F (BIT_MASK_USTIME_TSF_V1_8197F << BIT_SHIFT_USTIME_TSF_V1_8197F) +#define BIT_USTIME_TSF_V1_8197F(x) \ + (((x) & BIT_MASK_USTIME_TSF_V1_8197F) << BIT_SHIFT_USTIME_TSF_V1_8197F) +#define BITS_USTIME_TSF_V1_8197F \ + (BIT_MASK_USTIME_TSF_V1_8197F << BIT_SHIFT_USTIME_TSF_V1_8197F) #define BIT_CLEAR_USTIME_TSF_V1_8197F(x) ((x) & (~BITS_USTIME_TSF_V1_8197F)) -#define BIT_GET_USTIME_TSF_V1_8197F(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8197F) & BIT_MASK_USTIME_TSF_V1_8197F) -#define BIT_SET_USTIME_TSF_V1_8197F(x, v) (BIT_CLEAR_USTIME_TSF_V1_8197F(x) | BIT_USTIME_TSF_V1_8197F(v)) - +#define BIT_GET_USTIME_TSF_V1_8197F(x) \ + (((x) >> BIT_SHIFT_USTIME_TSF_V1_8197F) & BIT_MASK_USTIME_TSF_V1_8197F) +#define BIT_SET_USTIME_TSF_V1_8197F(x, v) \ + (BIT_CLEAR_USTIME_TSF_V1_8197F(x) | BIT_USTIME_TSF_V1_8197F(v)) /* 2 REG_BCN_MAX_ERR_8197F */ #define BIT_SHIFT_BCN_MAX_ERR_8197F 0 #define BIT_MASK_BCN_MAX_ERR_8197F 0xff -#define BIT_BCN_MAX_ERR_8197F(x) (((x) & BIT_MASK_BCN_MAX_ERR_8197F) << BIT_SHIFT_BCN_MAX_ERR_8197F) -#define BITS_BCN_MAX_ERR_8197F (BIT_MASK_BCN_MAX_ERR_8197F << BIT_SHIFT_BCN_MAX_ERR_8197F) +#define BIT_BCN_MAX_ERR_8197F(x) \ + (((x) & BIT_MASK_BCN_MAX_ERR_8197F) << BIT_SHIFT_BCN_MAX_ERR_8197F) +#define BITS_BCN_MAX_ERR_8197F \ + (BIT_MASK_BCN_MAX_ERR_8197F << BIT_SHIFT_BCN_MAX_ERR_8197F) #define BIT_CLEAR_BCN_MAX_ERR_8197F(x) ((x) & (~BITS_BCN_MAX_ERR_8197F)) -#define BIT_GET_BCN_MAX_ERR_8197F(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8197F) & BIT_MASK_BCN_MAX_ERR_8197F) -#define BIT_SET_BCN_MAX_ERR_8197F(x, v) (BIT_CLEAR_BCN_MAX_ERR_8197F(x) | BIT_BCN_MAX_ERR_8197F(v)) - +#define BIT_GET_BCN_MAX_ERR_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_MAX_ERR_8197F) & BIT_MASK_BCN_MAX_ERR_8197F) +#define BIT_SET_BCN_MAX_ERR_8197F(x, v) \ + (BIT_CLEAR_BCN_MAX_ERR_8197F(x) | BIT_BCN_MAX_ERR_8197F(v)) /* 2 REG_RXTSF_OFFSET_CCK_8197F */ #define BIT_SHIFT_CCK_RXTSF_OFFSET_8197F 0 #define BIT_MASK_CCK_RXTSF_OFFSET_8197F 0xff -#define BIT_CCK_RXTSF_OFFSET_8197F(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8197F) << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) -#define BITS_CCK_RXTSF_OFFSET_8197F (BIT_MASK_CCK_RXTSF_OFFSET_8197F << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) -#define BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) ((x) & (~BITS_CCK_RXTSF_OFFSET_8197F)) -#define BIT_GET_CCK_RXTSF_OFFSET_8197F(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) & BIT_MASK_CCK_RXTSF_OFFSET_8197F) -#define BIT_SET_CCK_RXTSF_OFFSET_8197F(x, v) (BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) | BIT_CCK_RXTSF_OFFSET_8197F(v)) - +#define BIT_CCK_RXTSF_OFFSET_8197F(x) \ + (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8197F) \ + << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) +#define BITS_CCK_RXTSF_OFFSET_8197F \ + (BIT_MASK_CCK_RXTSF_OFFSET_8197F << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) +#define BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) \ + ((x) & (~BITS_CCK_RXTSF_OFFSET_8197F)) +#define BIT_GET_CCK_RXTSF_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) & \ + BIT_MASK_CCK_RXTSF_OFFSET_8197F) +#define BIT_SET_CCK_RXTSF_OFFSET_8197F(x, v) \ + (BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) | BIT_CCK_RXTSF_OFFSET_8197F(v)) /* 2 REG_RXTSF_OFFSET_OFDM_8197F */ #define BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F 0 #define BIT_MASK_OFDM_RXTSF_OFFSET_8197F 0xff -#define BIT_OFDM_RXTSF_OFFSET_8197F(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8197F) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) -#define BITS_OFDM_RXTSF_OFFSET_8197F (BIT_MASK_OFDM_RXTSF_OFFSET_8197F << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) -#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) ((x) & (~BITS_OFDM_RXTSF_OFFSET_8197F)) -#define BIT_GET_OFDM_RXTSF_OFFSET_8197F(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) & BIT_MASK_OFDM_RXTSF_OFFSET_8197F) -#define BIT_SET_OFDM_RXTSF_OFFSET_8197F(x, v) (BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) | BIT_OFDM_RXTSF_OFFSET_8197F(v)) - +#define BIT_OFDM_RXTSF_OFFSET_8197F(x) \ + (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8197F) \ + << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) +#define BITS_OFDM_RXTSF_OFFSET_8197F \ + (BIT_MASK_OFDM_RXTSF_OFFSET_8197F << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) \ + ((x) & (~BITS_OFDM_RXTSF_OFFSET_8197F)) +#define BIT_GET_OFDM_RXTSF_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) & \ + BIT_MASK_OFDM_RXTSF_OFFSET_8197F) +#define BIT_SET_OFDM_RXTSF_OFFSET_8197F(x, v) \ + (BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) | BIT_OFDM_RXTSF_OFFSET_8197F(v)) /* 2 REG_TSFTR_8197F */ #define BIT_SHIFT_TSF_TIMER_8197F 0 #define BIT_MASK_TSF_TIMER_8197F 0xffffffffffffffffL -#define BIT_TSF_TIMER_8197F(x) (((x) & BIT_MASK_TSF_TIMER_8197F) << BIT_SHIFT_TSF_TIMER_8197F) -#define BITS_TSF_TIMER_8197F (BIT_MASK_TSF_TIMER_8197F << BIT_SHIFT_TSF_TIMER_8197F) +#define BIT_TSF_TIMER_8197F(x) \ + (((x) & BIT_MASK_TSF_TIMER_8197F) << BIT_SHIFT_TSF_TIMER_8197F) +#define BITS_TSF_TIMER_8197F \ + (BIT_MASK_TSF_TIMER_8197F << BIT_SHIFT_TSF_TIMER_8197F) #define BIT_CLEAR_TSF_TIMER_8197F(x) ((x) & (~BITS_TSF_TIMER_8197F)) -#define BIT_GET_TSF_TIMER_8197F(x) (((x) >> BIT_SHIFT_TSF_TIMER_8197F) & BIT_MASK_TSF_TIMER_8197F) -#define BIT_SET_TSF_TIMER_8197F(x, v) (BIT_CLEAR_TSF_TIMER_8197F(x) | BIT_TSF_TIMER_8197F(v)) - +#define BIT_GET_TSF_TIMER_8197F(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_8197F) & BIT_MASK_TSF_TIMER_8197F) +#define BIT_SET_TSF_TIMER_8197F(x, v) \ + (BIT_CLEAR_TSF_TIMER_8197F(x) | BIT_TSF_TIMER_8197F(v)) /* 2 REG_FREERUN_CNT_8197F */ #define BIT_SHIFT_FREERUN_CNT_8197F 0 #define BIT_MASK_FREERUN_CNT_8197F 0xffffffffffffffffL -#define BIT_FREERUN_CNT_8197F(x) (((x) & BIT_MASK_FREERUN_CNT_8197F) << BIT_SHIFT_FREERUN_CNT_8197F) -#define BITS_FREERUN_CNT_8197F (BIT_MASK_FREERUN_CNT_8197F << BIT_SHIFT_FREERUN_CNT_8197F) +#define BIT_FREERUN_CNT_8197F(x) \ + (((x) & BIT_MASK_FREERUN_CNT_8197F) << BIT_SHIFT_FREERUN_CNT_8197F) +#define BITS_FREERUN_CNT_8197F \ + (BIT_MASK_FREERUN_CNT_8197F << BIT_SHIFT_FREERUN_CNT_8197F) #define BIT_CLEAR_FREERUN_CNT_8197F(x) ((x) & (~BITS_FREERUN_CNT_8197F)) -#define BIT_GET_FREERUN_CNT_8197F(x) (((x) >> BIT_SHIFT_FREERUN_CNT_8197F) & BIT_MASK_FREERUN_CNT_8197F) -#define BIT_SET_FREERUN_CNT_8197F(x, v) (BIT_CLEAR_FREERUN_CNT_8197F(x) | BIT_FREERUN_CNT_8197F(v)) - +#define BIT_GET_FREERUN_CNT_8197F(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_8197F) & BIT_MASK_FREERUN_CNT_8197F) +#define BIT_SET_FREERUN_CNT_8197F(x, v) \ + (BIT_CLEAR_FREERUN_CNT_8197F(x) | BIT_FREERUN_CNT_8197F(v)) /* 2 REG_ATIMWND1_8197F */ #define BIT_SHIFT_ATIMWND1_V1_8197F 0 #define BIT_MASK_ATIMWND1_V1_8197F 0xff -#define BIT_ATIMWND1_V1_8197F(x) (((x) & BIT_MASK_ATIMWND1_V1_8197F) << BIT_SHIFT_ATIMWND1_V1_8197F) -#define BITS_ATIMWND1_V1_8197F (BIT_MASK_ATIMWND1_V1_8197F << BIT_SHIFT_ATIMWND1_V1_8197F) +#define BIT_ATIMWND1_V1_8197F(x) \ + (((x) & BIT_MASK_ATIMWND1_V1_8197F) << BIT_SHIFT_ATIMWND1_V1_8197F) +#define BITS_ATIMWND1_V1_8197F \ + (BIT_MASK_ATIMWND1_V1_8197F << BIT_SHIFT_ATIMWND1_V1_8197F) #define BIT_CLEAR_ATIMWND1_V1_8197F(x) ((x) & (~BITS_ATIMWND1_V1_8197F)) -#define BIT_GET_ATIMWND1_V1_8197F(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8197F) & BIT_MASK_ATIMWND1_V1_8197F) -#define BIT_SET_ATIMWND1_V1_8197F(x, v) (BIT_CLEAR_ATIMWND1_V1_8197F(x) | BIT_ATIMWND1_V1_8197F(v)) - +#define BIT_GET_ATIMWND1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND1_V1_8197F) & BIT_MASK_ATIMWND1_V1_8197F) +#define BIT_SET_ATIMWND1_V1_8197F(x, v) \ + (BIT_CLEAR_ATIMWND1_V1_8197F(x) | BIT_ATIMWND1_V1_8197F(v)) /* 2 REG_TBTT_PROHIBIT_INFRA_8197F */ #define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F 0 #define BIT_MASK_TBTT_PROHIBIT_INFRA_8197F 0xff -#define BIT_TBTT_PROHIBIT_INFRA_8197F(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8197F) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) -#define BITS_TBTT_PROHIBIT_INFRA_8197F (BIT_MASK_TBTT_PROHIBIT_INFRA_8197F << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) -#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8197F)) -#define BIT_GET_TBTT_PROHIBIT_INFRA_8197F(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) & BIT_MASK_TBTT_PROHIBIT_INFRA_8197F) -#define BIT_SET_TBTT_PROHIBIT_INFRA_8197F(x, v) (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) | BIT_TBTT_PROHIBIT_INFRA_8197F(v)) - +#define BIT_TBTT_PROHIBIT_INFRA_8197F(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8197F) \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) +#define BITS_TBTT_PROHIBIT_INFRA_8197F \ + (BIT_MASK_TBTT_PROHIBIT_INFRA_8197F \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) +#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8197F)) +#define BIT_GET_TBTT_PROHIBIT_INFRA_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) & \ + BIT_MASK_TBTT_PROHIBIT_INFRA_8197F) +#define BIT_SET_TBTT_PROHIBIT_INFRA_8197F(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) | \ + BIT_TBTT_PROHIBIT_INFRA_8197F(v)) /* 2 REG_CTWND_8197F */ #define BIT_SHIFT_CTWND_8197F 0 #define BIT_MASK_CTWND_8197F 0xff -#define BIT_CTWND_8197F(x) (((x) & BIT_MASK_CTWND_8197F) << BIT_SHIFT_CTWND_8197F) +#define BIT_CTWND_8197F(x) \ + (((x) & BIT_MASK_CTWND_8197F) << BIT_SHIFT_CTWND_8197F) #define BITS_CTWND_8197F (BIT_MASK_CTWND_8197F << BIT_SHIFT_CTWND_8197F) #define BIT_CLEAR_CTWND_8197F(x) ((x) & (~BITS_CTWND_8197F)) -#define BIT_GET_CTWND_8197F(x) (((x) >> BIT_SHIFT_CTWND_8197F) & BIT_MASK_CTWND_8197F) -#define BIT_SET_CTWND_8197F(x, v) (BIT_CLEAR_CTWND_8197F(x) | BIT_CTWND_8197F(v)) - +#define BIT_GET_CTWND_8197F(x) \ + (((x) >> BIT_SHIFT_CTWND_8197F) & BIT_MASK_CTWND_8197F) +#define BIT_SET_CTWND_8197F(x, v) \ + (BIT_CLEAR_CTWND_8197F(x) | BIT_CTWND_8197F(v)) /* 2 REG_BCNIVLCUNT_8197F */ #define BIT_SHIFT_BCNIVLCUNT_8197F 0 #define BIT_MASK_BCNIVLCUNT_8197F 0x7f -#define BIT_BCNIVLCUNT_8197F(x) (((x) & BIT_MASK_BCNIVLCUNT_8197F) << BIT_SHIFT_BCNIVLCUNT_8197F) -#define BITS_BCNIVLCUNT_8197F (BIT_MASK_BCNIVLCUNT_8197F << BIT_SHIFT_BCNIVLCUNT_8197F) +#define BIT_BCNIVLCUNT_8197F(x) \ + (((x) & BIT_MASK_BCNIVLCUNT_8197F) << BIT_SHIFT_BCNIVLCUNT_8197F) +#define BITS_BCNIVLCUNT_8197F \ + (BIT_MASK_BCNIVLCUNT_8197F << BIT_SHIFT_BCNIVLCUNT_8197F) #define BIT_CLEAR_BCNIVLCUNT_8197F(x) ((x) & (~BITS_BCNIVLCUNT_8197F)) -#define BIT_GET_BCNIVLCUNT_8197F(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8197F) & BIT_MASK_BCNIVLCUNT_8197F) -#define BIT_SET_BCNIVLCUNT_8197F(x, v) (BIT_CLEAR_BCNIVLCUNT_8197F(x) | BIT_BCNIVLCUNT_8197F(v)) - +#define BIT_GET_BCNIVLCUNT_8197F(x) \ + (((x) >> BIT_SHIFT_BCNIVLCUNT_8197F) & BIT_MASK_BCNIVLCUNT_8197F) +#define BIT_SET_BCNIVLCUNT_8197F(x, v) \ + (BIT_CLEAR_BCNIVLCUNT_8197F(x) | BIT_BCNIVLCUNT_8197F(v)) /* 2 REG_BCNDROPCTRL_8197F */ #define BIT_BEACON_DROP_EN_8197F BIT(7) #define BIT_SHIFT_BEACON_DROP_IVL_8197F 0 #define BIT_MASK_BEACON_DROP_IVL_8197F 0x7f -#define BIT_BEACON_DROP_IVL_8197F(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8197F) << BIT_SHIFT_BEACON_DROP_IVL_8197F) -#define BITS_BEACON_DROP_IVL_8197F (BIT_MASK_BEACON_DROP_IVL_8197F << BIT_SHIFT_BEACON_DROP_IVL_8197F) +#define BIT_BEACON_DROP_IVL_8197F(x) \ + (((x) & BIT_MASK_BEACON_DROP_IVL_8197F) \ + << BIT_SHIFT_BEACON_DROP_IVL_8197F) +#define BITS_BEACON_DROP_IVL_8197F \ + (BIT_MASK_BEACON_DROP_IVL_8197F << BIT_SHIFT_BEACON_DROP_IVL_8197F) #define BIT_CLEAR_BEACON_DROP_IVL_8197F(x) ((x) & (~BITS_BEACON_DROP_IVL_8197F)) -#define BIT_GET_BEACON_DROP_IVL_8197F(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8197F) & BIT_MASK_BEACON_DROP_IVL_8197F) -#define BIT_SET_BEACON_DROP_IVL_8197F(x, v) (BIT_CLEAR_BEACON_DROP_IVL_8197F(x) | BIT_BEACON_DROP_IVL_8197F(v)) - +#define BIT_GET_BEACON_DROP_IVL_8197F(x) \ + (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8197F) & \ + BIT_MASK_BEACON_DROP_IVL_8197F) +#define BIT_SET_BEACON_DROP_IVL_8197F(x, v) \ + (BIT_CLEAR_BEACON_DROP_IVL_8197F(x) | BIT_BEACON_DROP_IVL_8197F(v)) /* 2 REG_HGQ_TIMEOUT_PERIOD_8197F */ #define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F 0 #define BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F 0xff -#define BIT_HGQ_TIMEOUT_PERIOD_8197F(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) -#define BITS_HGQ_TIMEOUT_PERIOD_8197F (BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) -#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8197F)) -#define BIT_GET_HGQ_TIMEOUT_PERIOD_8197F(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F) -#define BIT_SET_HGQ_TIMEOUT_PERIOD_8197F(x, v) (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) | BIT_HGQ_TIMEOUT_PERIOD_8197F(v)) - +#define BIT_HGQ_TIMEOUT_PERIOD_8197F(x) \ + (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F) \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) +#define BITS_HGQ_TIMEOUT_PERIOD_8197F \ + (BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) \ + ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8197F)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8197F(x) \ + (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) & \ + BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F) +#define BIT_SET_HGQ_TIMEOUT_PERIOD_8197F(x, v) \ + (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) | \ + BIT_HGQ_TIMEOUT_PERIOD_8197F(v)) /* 2 REG_TXCMD_TIMEOUT_PERIOD_8197F */ #define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F 0 #define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F 0xff -#define BIT_TXCMD_TIMEOUT_PERIOD_8197F(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) -#define BITS_TXCMD_TIMEOUT_PERIOD_8197F (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) -#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8197F)) -#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8197F(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F) -#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8197F(x, v) (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) | BIT_TXCMD_TIMEOUT_PERIOD_8197F(v)) - +#define BIT_TXCMD_TIMEOUT_PERIOD_8197F(x) \ + (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F) \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) +#define BITS_TXCMD_TIMEOUT_PERIOD_8197F \ + (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) \ + ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8197F)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8197F(x) \ + (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) & \ + BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8197F(x, v) \ + (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) | \ + BIT_TXCMD_TIMEOUT_PERIOD_8197F(v)) /* 2 REG_MISC_CTRL_8197F */ #define BIT_DIS_MARK_TSF_US_8197F BIT(7) @@ -9161,12 +11958,18 @@ #define BIT_SHIFT_DIS_SECONDARY_CCA_8197F 0 #define BIT_MASK_DIS_SECONDARY_CCA_8197F 0x3 -#define BIT_DIS_SECONDARY_CCA_8197F(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8197F) << BIT_SHIFT_DIS_SECONDARY_CCA_8197F) -#define BITS_DIS_SECONDARY_CCA_8197F (BIT_MASK_DIS_SECONDARY_CCA_8197F << BIT_SHIFT_DIS_SECONDARY_CCA_8197F) -#define BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) ((x) & (~BITS_DIS_SECONDARY_CCA_8197F)) -#define BIT_GET_DIS_SECONDARY_CCA_8197F(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8197F) & BIT_MASK_DIS_SECONDARY_CCA_8197F) -#define BIT_SET_DIS_SECONDARY_CCA_8197F(x, v) (BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) | BIT_DIS_SECONDARY_CCA_8197F(v)) - +#define BIT_DIS_SECONDARY_CCA_8197F(x) \ + (((x) & BIT_MASK_DIS_SECONDARY_CCA_8197F) \ + << BIT_SHIFT_DIS_SECONDARY_CCA_8197F) +#define BITS_DIS_SECONDARY_CCA_8197F \ + (BIT_MASK_DIS_SECONDARY_CCA_8197F << BIT_SHIFT_DIS_SECONDARY_CCA_8197F) +#define BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) \ + ((x) & (~BITS_DIS_SECONDARY_CCA_8197F)) +#define BIT_GET_DIS_SECONDARY_CCA_8197F(x) \ + (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8197F) & \ + BIT_MASK_DIS_SECONDARY_CCA_8197F) +#define BIT_SET_DIS_SECONDARY_CCA_8197F(x, v) \ + (BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) | BIT_DIS_SECONDARY_CCA_8197F(v)) /* 2 REG_BCN_CTRL_CLINT1_8197F */ #define BIT_CLI1_DIS_RX_BSSID_FIT_8197F BIT(6) @@ -9198,12 +12001,15 @@ #define BIT_SHIFT_PORT_SEL_8197F 0 #define BIT_MASK_PORT_SEL_8197F 0x7 -#define BIT_PORT_SEL_8197F(x) (((x) & BIT_MASK_PORT_SEL_8197F) << BIT_SHIFT_PORT_SEL_8197F) -#define BITS_PORT_SEL_8197F (BIT_MASK_PORT_SEL_8197F << BIT_SHIFT_PORT_SEL_8197F) +#define BIT_PORT_SEL_8197F(x) \ + (((x) & BIT_MASK_PORT_SEL_8197F) << BIT_SHIFT_PORT_SEL_8197F) +#define BITS_PORT_SEL_8197F \ + (BIT_MASK_PORT_SEL_8197F << BIT_SHIFT_PORT_SEL_8197F) #define BIT_CLEAR_PORT_SEL_8197F(x) ((x) & (~BITS_PORT_SEL_8197F)) -#define BIT_GET_PORT_SEL_8197F(x) (((x) >> BIT_SHIFT_PORT_SEL_8197F) & BIT_MASK_PORT_SEL_8197F) -#define BIT_SET_PORT_SEL_8197F(x, v) (BIT_CLEAR_PORT_SEL_8197F(x) | BIT_PORT_SEL_8197F(v)) - +#define BIT_GET_PORT_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_PORT_SEL_8197F) & BIT_MASK_PORT_SEL_8197F) +#define BIT_SET_PORT_SEL_8197F(x, v) \ + (BIT_CLEAR_PORT_SEL_8197F(x) | BIT_PORT_SEL_8197F(v)) /* 2 REG_P2PPS1_SPEC_STATE_8197F */ #define BIT_P2P1_SPEC_POWER_STATE_8197F BIT(7) @@ -9249,56 +12055,71 @@ #define BIT_SHIFT_PSTIMER0_INT_8197F 5 #define BIT_MASK_PSTIMER0_INT_8197F 0x7ffffff -#define BIT_PSTIMER0_INT_8197F(x) (((x) & BIT_MASK_PSTIMER0_INT_8197F) << BIT_SHIFT_PSTIMER0_INT_8197F) -#define BITS_PSTIMER0_INT_8197F (BIT_MASK_PSTIMER0_INT_8197F << BIT_SHIFT_PSTIMER0_INT_8197F) +#define BIT_PSTIMER0_INT_8197F(x) \ + (((x) & BIT_MASK_PSTIMER0_INT_8197F) << BIT_SHIFT_PSTIMER0_INT_8197F) +#define BITS_PSTIMER0_INT_8197F \ + (BIT_MASK_PSTIMER0_INT_8197F << BIT_SHIFT_PSTIMER0_INT_8197F) #define BIT_CLEAR_PSTIMER0_INT_8197F(x) ((x) & (~BITS_PSTIMER0_INT_8197F)) -#define BIT_GET_PSTIMER0_INT_8197F(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8197F) & BIT_MASK_PSTIMER0_INT_8197F) -#define BIT_SET_PSTIMER0_INT_8197F(x, v) (BIT_CLEAR_PSTIMER0_INT_8197F(x) | BIT_PSTIMER0_INT_8197F(v)) - +#define BIT_GET_PSTIMER0_INT_8197F(x) \ + (((x) >> BIT_SHIFT_PSTIMER0_INT_8197F) & BIT_MASK_PSTIMER0_INT_8197F) +#define BIT_SET_PSTIMER0_INT_8197F(x, v) \ + (BIT_CLEAR_PSTIMER0_INT_8197F(x) | BIT_PSTIMER0_INT_8197F(v)) /* 2 REG_PS_TIMER1_8197F */ #define BIT_SHIFT_PSTIMER1_INT_8197F 5 #define BIT_MASK_PSTIMER1_INT_8197F 0x7ffffff -#define BIT_PSTIMER1_INT_8197F(x) (((x) & BIT_MASK_PSTIMER1_INT_8197F) << BIT_SHIFT_PSTIMER1_INT_8197F) -#define BITS_PSTIMER1_INT_8197F (BIT_MASK_PSTIMER1_INT_8197F << BIT_SHIFT_PSTIMER1_INT_8197F) +#define BIT_PSTIMER1_INT_8197F(x) \ + (((x) & BIT_MASK_PSTIMER1_INT_8197F) << BIT_SHIFT_PSTIMER1_INT_8197F) +#define BITS_PSTIMER1_INT_8197F \ + (BIT_MASK_PSTIMER1_INT_8197F << BIT_SHIFT_PSTIMER1_INT_8197F) #define BIT_CLEAR_PSTIMER1_INT_8197F(x) ((x) & (~BITS_PSTIMER1_INT_8197F)) -#define BIT_GET_PSTIMER1_INT_8197F(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8197F) & BIT_MASK_PSTIMER1_INT_8197F) -#define BIT_SET_PSTIMER1_INT_8197F(x, v) (BIT_CLEAR_PSTIMER1_INT_8197F(x) | BIT_PSTIMER1_INT_8197F(v)) - +#define BIT_GET_PSTIMER1_INT_8197F(x) \ + (((x) >> BIT_SHIFT_PSTIMER1_INT_8197F) & BIT_MASK_PSTIMER1_INT_8197F) +#define BIT_SET_PSTIMER1_INT_8197F(x, v) \ + (BIT_CLEAR_PSTIMER1_INT_8197F(x) | BIT_PSTIMER1_INT_8197F(v)) /* 2 REG_PS_TIMER2_8197F */ #define BIT_SHIFT_PSTIMER2_INT_8197F 5 #define BIT_MASK_PSTIMER2_INT_8197F 0x7ffffff -#define BIT_PSTIMER2_INT_8197F(x) (((x) & BIT_MASK_PSTIMER2_INT_8197F) << BIT_SHIFT_PSTIMER2_INT_8197F) -#define BITS_PSTIMER2_INT_8197F (BIT_MASK_PSTIMER2_INT_8197F << BIT_SHIFT_PSTIMER2_INT_8197F) +#define BIT_PSTIMER2_INT_8197F(x) \ + (((x) & BIT_MASK_PSTIMER2_INT_8197F) << BIT_SHIFT_PSTIMER2_INT_8197F) +#define BITS_PSTIMER2_INT_8197F \ + (BIT_MASK_PSTIMER2_INT_8197F << BIT_SHIFT_PSTIMER2_INT_8197F) #define BIT_CLEAR_PSTIMER2_INT_8197F(x) ((x) & (~BITS_PSTIMER2_INT_8197F)) -#define BIT_GET_PSTIMER2_INT_8197F(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8197F) & BIT_MASK_PSTIMER2_INT_8197F) -#define BIT_SET_PSTIMER2_INT_8197F(x, v) (BIT_CLEAR_PSTIMER2_INT_8197F(x) | BIT_PSTIMER2_INT_8197F(v)) - +#define BIT_GET_PSTIMER2_INT_8197F(x) \ + (((x) >> BIT_SHIFT_PSTIMER2_INT_8197F) & BIT_MASK_PSTIMER2_INT_8197F) +#define BIT_SET_PSTIMER2_INT_8197F(x, v) \ + (BIT_CLEAR_PSTIMER2_INT_8197F(x) | BIT_PSTIMER2_INT_8197F(v)) /* 2 REG_TBTT_CTN_AREA_8197F */ #define BIT_SHIFT_TBTT_CTN_AREA_8197F 0 #define BIT_MASK_TBTT_CTN_AREA_8197F 0xff -#define BIT_TBTT_CTN_AREA_8197F(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8197F) << BIT_SHIFT_TBTT_CTN_AREA_8197F) -#define BITS_TBTT_CTN_AREA_8197F (BIT_MASK_TBTT_CTN_AREA_8197F << BIT_SHIFT_TBTT_CTN_AREA_8197F) +#define BIT_TBTT_CTN_AREA_8197F(x) \ + (((x) & BIT_MASK_TBTT_CTN_AREA_8197F) << BIT_SHIFT_TBTT_CTN_AREA_8197F) +#define BITS_TBTT_CTN_AREA_8197F \ + (BIT_MASK_TBTT_CTN_AREA_8197F << BIT_SHIFT_TBTT_CTN_AREA_8197F) #define BIT_CLEAR_TBTT_CTN_AREA_8197F(x) ((x) & (~BITS_TBTT_CTN_AREA_8197F)) -#define BIT_GET_TBTT_CTN_AREA_8197F(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8197F) & BIT_MASK_TBTT_CTN_AREA_8197F) -#define BIT_SET_TBTT_CTN_AREA_8197F(x, v) (BIT_CLEAR_TBTT_CTN_AREA_8197F(x) | BIT_TBTT_CTN_AREA_8197F(v)) - +#define BIT_GET_TBTT_CTN_AREA_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8197F) & BIT_MASK_TBTT_CTN_AREA_8197F) +#define BIT_SET_TBTT_CTN_AREA_8197F(x, v) \ + (BIT_CLEAR_TBTT_CTN_AREA_8197F(x) | BIT_TBTT_CTN_AREA_8197F(v)) /* 2 REG_FORCE_BCN_IFS_8197F */ #define BIT_SHIFT_FORCE_BCN_IFS_8197F 0 #define BIT_MASK_FORCE_BCN_IFS_8197F 0xff -#define BIT_FORCE_BCN_IFS_8197F(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8197F) << BIT_SHIFT_FORCE_BCN_IFS_8197F) -#define BITS_FORCE_BCN_IFS_8197F (BIT_MASK_FORCE_BCN_IFS_8197F << BIT_SHIFT_FORCE_BCN_IFS_8197F) +#define BIT_FORCE_BCN_IFS_8197F(x) \ + (((x) & BIT_MASK_FORCE_BCN_IFS_8197F) << BIT_SHIFT_FORCE_BCN_IFS_8197F) +#define BITS_FORCE_BCN_IFS_8197F \ + (BIT_MASK_FORCE_BCN_IFS_8197F << BIT_SHIFT_FORCE_BCN_IFS_8197F) #define BIT_CLEAR_FORCE_BCN_IFS_8197F(x) ((x) & (~BITS_FORCE_BCN_IFS_8197F)) -#define BIT_GET_FORCE_BCN_IFS_8197F(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8197F) & BIT_MASK_FORCE_BCN_IFS_8197F) -#define BIT_SET_FORCE_BCN_IFS_8197F(x, v) (BIT_CLEAR_FORCE_BCN_IFS_8197F(x) | BIT_FORCE_BCN_IFS_8197F(v)) - +#define BIT_GET_FORCE_BCN_IFS_8197F(x) \ + (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8197F) & BIT_MASK_FORCE_BCN_IFS_8197F) +#define BIT_SET_FORCE_BCN_IFS_8197F(x, v) \ + (BIT_CLEAR_FORCE_BCN_IFS_8197F(x) | BIT_FORCE_BCN_IFS_8197F(v)) /* 2 REG_TXOP_MIN_8197F */ #define BIT_NAV_BLK_HGQ_8197F BIT(15) @@ -9306,23 +12127,29 @@ #define BIT_SHIFT_TXOP_MIN_8197F 0 #define BIT_MASK_TXOP_MIN_8197F 0x3fff -#define BIT_TXOP_MIN_8197F(x) (((x) & BIT_MASK_TXOP_MIN_8197F) << BIT_SHIFT_TXOP_MIN_8197F) -#define BITS_TXOP_MIN_8197F (BIT_MASK_TXOP_MIN_8197F << BIT_SHIFT_TXOP_MIN_8197F) +#define BIT_TXOP_MIN_8197F(x) \ + (((x) & BIT_MASK_TXOP_MIN_8197F) << BIT_SHIFT_TXOP_MIN_8197F) +#define BITS_TXOP_MIN_8197F \ + (BIT_MASK_TXOP_MIN_8197F << BIT_SHIFT_TXOP_MIN_8197F) #define BIT_CLEAR_TXOP_MIN_8197F(x) ((x) & (~BITS_TXOP_MIN_8197F)) -#define BIT_GET_TXOP_MIN_8197F(x) (((x) >> BIT_SHIFT_TXOP_MIN_8197F) & BIT_MASK_TXOP_MIN_8197F) -#define BIT_SET_TXOP_MIN_8197F(x, v) (BIT_CLEAR_TXOP_MIN_8197F(x) | BIT_TXOP_MIN_8197F(v)) - +#define BIT_GET_TXOP_MIN_8197F(x) \ + (((x) >> BIT_SHIFT_TXOP_MIN_8197F) & BIT_MASK_TXOP_MIN_8197F) +#define BIT_SET_TXOP_MIN_8197F(x, v) \ + (BIT_CLEAR_TXOP_MIN_8197F(x) | BIT_TXOP_MIN_8197F(v)) /* 2 REG_PRE_BKF_TIME_8197F */ #define BIT_SHIFT_PRE_BKF_TIME_8197F 0 #define BIT_MASK_PRE_BKF_TIME_8197F 0xff -#define BIT_PRE_BKF_TIME_8197F(x) (((x) & BIT_MASK_PRE_BKF_TIME_8197F) << BIT_SHIFT_PRE_BKF_TIME_8197F) -#define BITS_PRE_BKF_TIME_8197F (BIT_MASK_PRE_BKF_TIME_8197F << BIT_SHIFT_PRE_BKF_TIME_8197F) +#define BIT_PRE_BKF_TIME_8197F(x) \ + (((x) & BIT_MASK_PRE_BKF_TIME_8197F) << BIT_SHIFT_PRE_BKF_TIME_8197F) +#define BITS_PRE_BKF_TIME_8197F \ + (BIT_MASK_PRE_BKF_TIME_8197F << BIT_SHIFT_PRE_BKF_TIME_8197F) #define BIT_CLEAR_PRE_BKF_TIME_8197F(x) ((x) & (~BITS_PRE_BKF_TIME_8197F)) -#define BIT_GET_PRE_BKF_TIME_8197F(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8197F) & BIT_MASK_PRE_BKF_TIME_8197F) -#define BIT_SET_PRE_BKF_TIME_8197F(x, v) (BIT_CLEAR_PRE_BKF_TIME_8197F(x) | BIT_PRE_BKF_TIME_8197F(v)) - +#define BIT_GET_PRE_BKF_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_PRE_BKF_TIME_8197F) & BIT_MASK_PRE_BKF_TIME_8197F) +#define BIT_SET_PRE_BKF_TIME_8197F(x, v) \ + (BIT_CLEAR_PRE_BKF_TIME_8197F(x) | BIT_PRE_BKF_TIME_8197F(v)) /* 2 REG_CROSS_TXOP_CTRL_8197F */ #define BIT_DTIM_BYPASS_8197F BIT(2) @@ -9334,48 +12161,80 @@ #define BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F 0 #define BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F 0x7f -#define BIT_TBTT_INT_SHIFT_CLI0_8197F(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) -#define BITS_TBTT_INT_SHIFT_CLI0_8197F (BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) -#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI0_8197F)) -#define BIT_GET_TBTT_INT_SHIFT_CLI0_8197F(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) & BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F) -#define BIT_SET_TBTT_INT_SHIFT_CLI0_8197F(x, v) (BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) | BIT_TBTT_INT_SHIFT_CLI0_8197F(v)) - +#define BIT_TBTT_INT_SHIFT_CLI0_8197F(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F) \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) +#define BITS_TBTT_INT_SHIFT_CLI0_8197F \ + (BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) \ + ((x) & (~BITS_TBTT_INT_SHIFT_CLI0_8197F)) +#define BIT_GET_TBTT_INT_SHIFT_CLI0_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) & \ + BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F) +#define BIT_SET_TBTT_INT_SHIFT_CLI0_8197F(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) | \ + BIT_TBTT_INT_SHIFT_CLI0_8197F(v)) /* 2 REG_TBTT_INT_SHIFT_CLI1_8197F */ #define BIT_TBTT_INT_SHIFT_DIR_CLI1_8197F BIT(7) #define BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F 0 #define BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F 0x7f -#define BIT_TBTT_INT_SHIFT_CLI1_8197F(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) -#define BITS_TBTT_INT_SHIFT_CLI1_8197F (BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) -#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI1_8197F)) -#define BIT_GET_TBTT_INT_SHIFT_CLI1_8197F(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) & BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F) -#define BIT_SET_TBTT_INT_SHIFT_CLI1_8197F(x, v) (BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) | BIT_TBTT_INT_SHIFT_CLI1_8197F(v)) - +#define BIT_TBTT_INT_SHIFT_CLI1_8197F(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F) \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) +#define BITS_TBTT_INT_SHIFT_CLI1_8197F \ + (BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) \ + ((x) & (~BITS_TBTT_INT_SHIFT_CLI1_8197F)) +#define BIT_GET_TBTT_INT_SHIFT_CLI1_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) & \ + BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F) +#define BIT_SET_TBTT_INT_SHIFT_CLI1_8197F(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) | \ + BIT_TBTT_INT_SHIFT_CLI1_8197F(v)) /* 2 REG_TBTT_INT_SHIFT_CLI2_8197F */ #define BIT_TBTT_INT_SHIFT_DIR_CLI2_8197F BIT(7) #define BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F 0 #define BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F 0x7f -#define BIT_TBTT_INT_SHIFT_CLI2_8197F(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) -#define BITS_TBTT_INT_SHIFT_CLI2_8197F (BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) -#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI2_8197F)) -#define BIT_GET_TBTT_INT_SHIFT_CLI2_8197F(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) & BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F) -#define BIT_SET_TBTT_INT_SHIFT_CLI2_8197F(x, v) (BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) | BIT_TBTT_INT_SHIFT_CLI2_8197F(v)) - +#define BIT_TBTT_INT_SHIFT_CLI2_8197F(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F) \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) +#define BITS_TBTT_INT_SHIFT_CLI2_8197F \ + (BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) \ + ((x) & (~BITS_TBTT_INT_SHIFT_CLI2_8197F)) +#define BIT_GET_TBTT_INT_SHIFT_CLI2_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) & \ + BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F) +#define BIT_SET_TBTT_INT_SHIFT_CLI2_8197F(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) | \ + BIT_TBTT_INT_SHIFT_CLI2_8197F(v)) /* 2 REG_TBTT_INT_SHIFT_CLI3_8197F */ #define BIT_TBTT_INT_SHIFT_DIR_CLI3_8197F BIT(7) #define BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F 0 #define BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F 0x7f -#define BIT_TBTT_INT_SHIFT_CLI3_8197F(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) -#define BITS_TBTT_INT_SHIFT_CLI3_8197F (BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) -#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI3_8197F)) -#define BIT_GET_TBTT_INT_SHIFT_CLI3_8197F(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) & BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F) -#define BIT_SET_TBTT_INT_SHIFT_CLI3_8197F(x, v) (BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) | BIT_TBTT_INT_SHIFT_CLI3_8197F(v)) - +#define BIT_TBTT_INT_SHIFT_CLI3_8197F(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F) \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) +#define BITS_TBTT_INT_SHIFT_CLI3_8197F \ + (BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) \ + ((x) & (~BITS_TBTT_INT_SHIFT_CLI3_8197F)) +#define BIT_GET_TBTT_INT_SHIFT_CLI3_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) & \ + BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F) +#define BIT_SET_TBTT_INT_SHIFT_CLI3_8197F(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) | \ + BIT_TBTT_INT_SHIFT_CLI3_8197F(v)) /* 2 REG_TBTT_INT_SHIFT_ENABLE_8197F */ #define BIT_EN_TBTT_RTY_8197F BIT(1) @@ -9385,78 +12244,99 @@ #define BIT_SHIFT_ATIMWND2_8197F 0 #define BIT_MASK_ATIMWND2_8197F 0xff -#define BIT_ATIMWND2_8197F(x) (((x) & BIT_MASK_ATIMWND2_8197F) << BIT_SHIFT_ATIMWND2_8197F) -#define BITS_ATIMWND2_8197F (BIT_MASK_ATIMWND2_8197F << BIT_SHIFT_ATIMWND2_8197F) +#define BIT_ATIMWND2_8197F(x) \ + (((x) & BIT_MASK_ATIMWND2_8197F) << BIT_SHIFT_ATIMWND2_8197F) +#define BITS_ATIMWND2_8197F \ + (BIT_MASK_ATIMWND2_8197F << BIT_SHIFT_ATIMWND2_8197F) #define BIT_CLEAR_ATIMWND2_8197F(x) ((x) & (~BITS_ATIMWND2_8197F)) -#define BIT_GET_ATIMWND2_8197F(x) (((x) >> BIT_SHIFT_ATIMWND2_8197F) & BIT_MASK_ATIMWND2_8197F) -#define BIT_SET_ATIMWND2_8197F(x, v) (BIT_CLEAR_ATIMWND2_8197F(x) | BIT_ATIMWND2_8197F(v)) - +#define BIT_GET_ATIMWND2_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND2_8197F) & BIT_MASK_ATIMWND2_8197F) +#define BIT_SET_ATIMWND2_8197F(x, v) \ + (BIT_CLEAR_ATIMWND2_8197F(x) | BIT_ATIMWND2_8197F(v)) /* 2 REG_ATIMWND3_8197F */ #define BIT_SHIFT_ATIMWND3_8197F 0 #define BIT_MASK_ATIMWND3_8197F 0xff -#define BIT_ATIMWND3_8197F(x) (((x) & BIT_MASK_ATIMWND3_8197F) << BIT_SHIFT_ATIMWND3_8197F) -#define BITS_ATIMWND3_8197F (BIT_MASK_ATIMWND3_8197F << BIT_SHIFT_ATIMWND3_8197F) +#define BIT_ATIMWND3_8197F(x) \ + (((x) & BIT_MASK_ATIMWND3_8197F) << BIT_SHIFT_ATIMWND3_8197F) +#define BITS_ATIMWND3_8197F \ + (BIT_MASK_ATIMWND3_8197F << BIT_SHIFT_ATIMWND3_8197F) #define BIT_CLEAR_ATIMWND3_8197F(x) ((x) & (~BITS_ATIMWND3_8197F)) -#define BIT_GET_ATIMWND3_8197F(x) (((x) >> BIT_SHIFT_ATIMWND3_8197F) & BIT_MASK_ATIMWND3_8197F) -#define BIT_SET_ATIMWND3_8197F(x, v) (BIT_CLEAR_ATIMWND3_8197F(x) | BIT_ATIMWND3_8197F(v)) - +#define BIT_GET_ATIMWND3_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND3_8197F) & BIT_MASK_ATIMWND3_8197F) +#define BIT_SET_ATIMWND3_8197F(x, v) \ + (BIT_CLEAR_ATIMWND3_8197F(x) | BIT_ATIMWND3_8197F(v)) /* 2 REG_ATIMWND4_8197F */ #define BIT_SHIFT_ATIMWND4_8197F 0 #define BIT_MASK_ATIMWND4_8197F 0xff -#define BIT_ATIMWND4_8197F(x) (((x) & BIT_MASK_ATIMWND4_8197F) << BIT_SHIFT_ATIMWND4_8197F) -#define BITS_ATIMWND4_8197F (BIT_MASK_ATIMWND4_8197F << BIT_SHIFT_ATIMWND4_8197F) +#define BIT_ATIMWND4_8197F(x) \ + (((x) & BIT_MASK_ATIMWND4_8197F) << BIT_SHIFT_ATIMWND4_8197F) +#define BITS_ATIMWND4_8197F \ + (BIT_MASK_ATIMWND4_8197F << BIT_SHIFT_ATIMWND4_8197F) #define BIT_CLEAR_ATIMWND4_8197F(x) ((x) & (~BITS_ATIMWND4_8197F)) -#define BIT_GET_ATIMWND4_8197F(x) (((x) >> BIT_SHIFT_ATIMWND4_8197F) & BIT_MASK_ATIMWND4_8197F) -#define BIT_SET_ATIMWND4_8197F(x, v) (BIT_CLEAR_ATIMWND4_8197F(x) | BIT_ATIMWND4_8197F(v)) - +#define BIT_GET_ATIMWND4_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND4_8197F) & BIT_MASK_ATIMWND4_8197F) +#define BIT_SET_ATIMWND4_8197F(x, v) \ + (BIT_CLEAR_ATIMWND4_8197F(x) | BIT_ATIMWND4_8197F(v)) /* 2 REG_ATIMWND5_8197F */ #define BIT_SHIFT_ATIMWND5_8197F 0 #define BIT_MASK_ATIMWND5_8197F 0xff -#define BIT_ATIMWND5_8197F(x) (((x) & BIT_MASK_ATIMWND5_8197F) << BIT_SHIFT_ATIMWND5_8197F) -#define BITS_ATIMWND5_8197F (BIT_MASK_ATIMWND5_8197F << BIT_SHIFT_ATIMWND5_8197F) +#define BIT_ATIMWND5_8197F(x) \ + (((x) & BIT_MASK_ATIMWND5_8197F) << BIT_SHIFT_ATIMWND5_8197F) +#define BITS_ATIMWND5_8197F \ + (BIT_MASK_ATIMWND5_8197F << BIT_SHIFT_ATIMWND5_8197F) #define BIT_CLEAR_ATIMWND5_8197F(x) ((x) & (~BITS_ATIMWND5_8197F)) -#define BIT_GET_ATIMWND5_8197F(x) (((x) >> BIT_SHIFT_ATIMWND5_8197F) & BIT_MASK_ATIMWND5_8197F) -#define BIT_SET_ATIMWND5_8197F(x, v) (BIT_CLEAR_ATIMWND5_8197F(x) | BIT_ATIMWND5_8197F(v)) - +#define BIT_GET_ATIMWND5_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND5_8197F) & BIT_MASK_ATIMWND5_8197F) +#define BIT_SET_ATIMWND5_8197F(x, v) \ + (BIT_CLEAR_ATIMWND5_8197F(x) | BIT_ATIMWND5_8197F(v)) /* 2 REG_ATIMWND6_8197F */ #define BIT_SHIFT_ATIMWND6_8197F 0 #define BIT_MASK_ATIMWND6_8197F 0xff -#define BIT_ATIMWND6_8197F(x) (((x) & BIT_MASK_ATIMWND6_8197F) << BIT_SHIFT_ATIMWND6_8197F) -#define BITS_ATIMWND6_8197F (BIT_MASK_ATIMWND6_8197F << BIT_SHIFT_ATIMWND6_8197F) +#define BIT_ATIMWND6_8197F(x) \ + (((x) & BIT_MASK_ATIMWND6_8197F) << BIT_SHIFT_ATIMWND6_8197F) +#define BITS_ATIMWND6_8197F \ + (BIT_MASK_ATIMWND6_8197F << BIT_SHIFT_ATIMWND6_8197F) #define BIT_CLEAR_ATIMWND6_8197F(x) ((x) & (~BITS_ATIMWND6_8197F)) -#define BIT_GET_ATIMWND6_8197F(x) (((x) >> BIT_SHIFT_ATIMWND6_8197F) & BIT_MASK_ATIMWND6_8197F) -#define BIT_SET_ATIMWND6_8197F(x, v) (BIT_CLEAR_ATIMWND6_8197F(x) | BIT_ATIMWND6_8197F(v)) - +#define BIT_GET_ATIMWND6_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND6_8197F) & BIT_MASK_ATIMWND6_8197F) +#define BIT_SET_ATIMWND6_8197F(x, v) \ + (BIT_CLEAR_ATIMWND6_8197F(x) | BIT_ATIMWND6_8197F(v)) /* 2 REG_ATIMWND7_8197F */ #define BIT_SHIFT_ATIMWND7_8197F 0 #define BIT_MASK_ATIMWND7_8197F 0xff -#define BIT_ATIMWND7_8197F(x) (((x) & BIT_MASK_ATIMWND7_8197F) << BIT_SHIFT_ATIMWND7_8197F) -#define BITS_ATIMWND7_8197F (BIT_MASK_ATIMWND7_8197F << BIT_SHIFT_ATIMWND7_8197F) +#define BIT_ATIMWND7_8197F(x) \ + (((x) & BIT_MASK_ATIMWND7_8197F) << BIT_SHIFT_ATIMWND7_8197F) +#define BITS_ATIMWND7_8197F \ + (BIT_MASK_ATIMWND7_8197F << BIT_SHIFT_ATIMWND7_8197F) #define BIT_CLEAR_ATIMWND7_8197F(x) ((x) & (~BITS_ATIMWND7_8197F)) -#define BIT_GET_ATIMWND7_8197F(x) (((x) >> BIT_SHIFT_ATIMWND7_8197F) & BIT_MASK_ATIMWND7_8197F) -#define BIT_SET_ATIMWND7_8197F(x, v) (BIT_CLEAR_ATIMWND7_8197F(x) | BIT_ATIMWND7_8197F(v)) - +#define BIT_GET_ATIMWND7_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND7_8197F) & BIT_MASK_ATIMWND7_8197F) +#define BIT_SET_ATIMWND7_8197F(x, v) \ + (BIT_CLEAR_ATIMWND7_8197F(x) | BIT_ATIMWND7_8197F(v)) /* 2 REG_ATIMUGT_8197F */ #define BIT_SHIFT_ATIM_URGENT_8197F 0 #define BIT_MASK_ATIM_URGENT_8197F 0xff -#define BIT_ATIM_URGENT_8197F(x) (((x) & BIT_MASK_ATIM_URGENT_8197F) << BIT_SHIFT_ATIM_URGENT_8197F) -#define BITS_ATIM_URGENT_8197F (BIT_MASK_ATIM_URGENT_8197F << BIT_SHIFT_ATIM_URGENT_8197F) +#define BIT_ATIM_URGENT_8197F(x) \ + (((x) & BIT_MASK_ATIM_URGENT_8197F) << BIT_SHIFT_ATIM_URGENT_8197F) +#define BITS_ATIM_URGENT_8197F \ + (BIT_MASK_ATIM_URGENT_8197F << BIT_SHIFT_ATIM_URGENT_8197F) #define BIT_CLEAR_ATIM_URGENT_8197F(x) ((x) & (~BITS_ATIM_URGENT_8197F)) -#define BIT_GET_ATIM_URGENT_8197F(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8197F) & BIT_MASK_ATIM_URGENT_8197F) -#define BIT_SET_ATIM_URGENT_8197F(x, v) (BIT_CLEAR_ATIM_URGENT_8197F(x) | BIT_ATIM_URGENT_8197F(v)) - +#define BIT_GET_ATIM_URGENT_8197F(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT_8197F) & BIT_MASK_ATIM_URGENT_8197F) +#define BIT_SET_ATIM_URGENT_8197F(x, v) \ + (BIT_CLEAR_ATIM_URGENT_8197F(x) | BIT_ATIM_URGENT_8197F(v)) /* 2 REG_HIQ_NO_LMT_EN_8197F */ #define BIT_HIQ_NO_LMT_EN_VAP7_8197F BIT(7) @@ -9472,89 +12352,129 @@ #define BIT_SHIFT_DTIM_COUNT_ROOT_8197F 0 #define BIT_MASK_DTIM_COUNT_ROOT_8197F 0xff -#define BIT_DTIM_COUNT_ROOT_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8197F) << BIT_SHIFT_DTIM_COUNT_ROOT_8197F) -#define BITS_DTIM_COUNT_ROOT_8197F (BIT_MASK_DTIM_COUNT_ROOT_8197F << BIT_SHIFT_DTIM_COUNT_ROOT_8197F) +#define BIT_DTIM_COUNT_ROOT_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_ROOT_8197F) \ + << BIT_SHIFT_DTIM_COUNT_ROOT_8197F) +#define BITS_DTIM_COUNT_ROOT_8197F \ + (BIT_MASK_DTIM_COUNT_ROOT_8197F << BIT_SHIFT_DTIM_COUNT_ROOT_8197F) #define BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8197F)) -#define BIT_GET_DTIM_COUNT_ROOT_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8197F) & BIT_MASK_DTIM_COUNT_ROOT_8197F) -#define BIT_SET_DTIM_COUNT_ROOT_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) | BIT_DTIM_COUNT_ROOT_8197F(v)) - +#define BIT_GET_DTIM_COUNT_ROOT_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8197F) & \ + BIT_MASK_DTIM_COUNT_ROOT_8197F) +#define BIT_SET_DTIM_COUNT_ROOT_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) | BIT_DTIM_COUNT_ROOT_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP1_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP1_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP1_8197F 0xff -#define BIT_DTIM_COUNT_VAP1_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8197F) << BIT_SHIFT_DTIM_COUNT_VAP1_8197F) -#define BITS_DTIM_COUNT_VAP1_8197F (BIT_MASK_DTIM_COUNT_VAP1_8197F << BIT_SHIFT_DTIM_COUNT_VAP1_8197F) +#define BIT_DTIM_COUNT_VAP1_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP1_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP1_8197F) +#define BITS_DTIM_COUNT_VAP1_8197F \ + (BIT_MASK_DTIM_COUNT_VAP1_8197F << BIT_SHIFT_DTIM_COUNT_VAP1_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8197F)) -#define BIT_GET_DTIM_COUNT_VAP1_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8197F) & BIT_MASK_DTIM_COUNT_VAP1_8197F) -#define BIT_SET_DTIM_COUNT_VAP1_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) | BIT_DTIM_COUNT_VAP1_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP1_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP1_8197F) +#define BIT_SET_DTIM_COUNT_VAP1_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) | BIT_DTIM_COUNT_VAP1_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP2_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP2_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP2_8197F 0xff -#define BIT_DTIM_COUNT_VAP2_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8197F) << BIT_SHIFT_DTIM_COUNT_VAP2_8197F) -#define BITS_DTIM_COUNT_VAP2_8197F (BIT_MASK_DTIM_COUNT_VAP2_8197F << BIT_SHIFT_DTIM_COUNT_VAP2_8197F) +#define BIT_DTIM_COUNT_VAP2_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP2_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP2_8197F) +#define BITS_DTIM_COUNT_VAP2_8197F \ + (BIT_MASK_DTIM_COUNT_VAP2_8197F << BIT_SHIFT_DTIM_COUNT_VAP2_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8197F)) -#define BIT_GET_DTIM_COUNT_VAP2_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8197F) & BIT_MASK_DTIM_COUNT_VAP2_8197F) -#define BIT_SET_DTIM_COUNT_VAP2_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) | BIT_DTIM_COUNT_VAP2_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP2_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP2_8197F) +#define BIT_SET_DTIM_COUNT_VAP2_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) | BIT_DTIM_COUNT_VAP2_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP3_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP3_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP3_8197F 0xff -#define BIT_DTIM_COUNT_VAP3_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8197F) << BIT_SHIFT_DTIM_COUNT_VAP3_8197F) -#define BITS_DTIM_COUNT_VAP3_8197F (BIT_MASK_DTIM_COUNT_VAP3_8197F << BIT_SHIFT_DTIM_COUNT_VAP3_8197F) +#define BIT_DTIM_COUNT_VAP3_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP3_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP3_8197F) +#define BITS_DTIM_COUNT_VAP3_8197F \ + (BIT_MASK_DTIM_COUNT_VAP3_8197F << BIT_SHIFT_DTIM_COUNT_VAP3_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8197F)) -#define BIT_GET_DTIM_COUNT_VAP3_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8197F) & BIT_MASK_DTIM_COUNT_VAP3_8197F) -#define BIT_SET_DTIM_COUNT_VAP3_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) | BIT_DTIM_COUNT_VAP3_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP3_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP3_8197F) +#define BIT_SET_DTIM_COUNT_VAP3_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) | BIT_DTIM_COUNT_VAP3_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP4_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP4_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP4_8197F 0xff -#define BIT_DTIM_COUNT_VAP4_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8197F) << BIT_SHIFT_DTIM_COUNT_VAP4_8197F) -#define BITS_DTIM_COUNT_VAP4_8197F (BIT_MASK_DTIM_COUNT_VAP4_8197F << BIT_SHIFT_DTIM_COUNT_VAP4_8197F) +#define BIT_DTIM_COUNT_VAP4_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP4_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP4_8197F) +#define BITS_DTIM_COUNT_VAP4_8197F \ + (BIT_MASK_DTIM_COUNT_VAP4_8197F << BIT_SHIFT_DTIM_COUNT_VAP4_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8197F)) -#define BIT_GET_DTIM_COUNT_VAP4_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8197F) & BIT_MASK_DTIM_COUNT_VAP4_8197F) -#define BIT_SET_DTIM_COUNT_VAP4_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) | BIT_DTIM_COUNT_VAP4_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP4_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP4_8197F) +#define BIT_SET_DTIM_COUNT_VAP4_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) | BIT_DTIM_COUNT_VAP4_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP5_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP5_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP5_8197F 0xff -#define BIT_DTIM_COUNT_VAP5_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8197F) << BIT_SHIFT_DTIM_COUNT_VAP5_8197F) -#define BITS_DTIM_COUNT_VAP5_8197F (BIT_MASK_DTIM_COUNT_VAP5_8197F << BIT_SHIFT_DTIM_COUNT_VAP5_8197F) +#define BIT_DTIM_COUNT_VAP5_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP5_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP5_8197F) +#define BITS_DTIM_COUNT_VAP5_8197F \ + (BIT_MASK_DTIM_COUNT_VAP5_8197F << BIT_SHIFT_DTIM_COUNT_VAP5_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8197F)) -#define BIT_GET_DTIM_COUNT_VAP5_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8197F) & BIT_MASK_DTIM_COUNT_VAP5_8197F) -#define BIT_SET_DTIM_COUNT_VAP5_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) | BIT_DTIM_COUNT_VAP5_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP5_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP5_8197F) +#define BIT_SET_DTIM_COUNT_VAP5_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) | BIT_DTIM_COUNT_VAP5_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP6_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP6_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP6_8197F 0xff -#define BIT_DTIM_COUNT_VAP6_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8197F) << BIT_SHIFT_DTIM_COUNT_VAP6_8197F) -#define BITS_DTIM_COUNT_VAP6_8197F (BIT_MASK_DTIM_COUNT_VAP6_8197F << BIT_SHIFT_DTIM_COUNT_VAP6_8197F) +#define BIT_DTIM_COUNT_VAP6_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP6_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP6_8197F) +#define BITS_DTIM_COUNT_VAP6_8197F \ + (BIT_MASK_DTIM_COUNT_VAP6_8197F << BIT_SHIFT_DTIM_COUNT_VAP6_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8197F)) -#define BIT_GET_DTIM_COUNT_VAP6_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8197F) & BIT_MASK_DTIM_COUNT_VAP6_8197F) -#define BIT_SET_DTIM_COUNT_VAP6_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) | BIT_DTIM_COUNT_VAP6_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP6_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP6_8197F) +#define BIT_SET_DTIM_COUNT_VAP6_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) | BIT_DTIM_COUNT_VAP6_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP7_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP7_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP7_8197F 0xff -#define BIT_DTIM_COUNT_VAP7_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8197F) << BIT_SHIFT_DTIM_COUNT_VAP7_8197F) -#define BITS_DTIM_COUNT_VAP7_8197F (BIT_MASK_DTIM_COUNT_VAP7_8197F << BIT_SHIFT_DTIM_COUNT_VAP7_8197F) +#define BIT_DTIM_COUNT_VAP7_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP7_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP7_8197F) +#define BITS_DTIM_COUNT_VAP7_8197F \ + (BIT_MASK_DTIM_COUNT_VAP7_8197F << BIT_SHIFT_DTIM_COUNT_VAP7_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8197F)) -#define BIT_GET_DTIM_COUNT_VAP7_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8197F) & BIT_MASK_DTIM_COUNT_VAP7_8197F) -#define BIT_SET_DTIM_COUNT_VAP7_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) | BIT_DTIM_COUNT_VAP7_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP7_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP7_8197F) +#define BIT_SET_DTIM_COUNT_VAP7_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) | BIT_DTIM_COUNT_VAP7_8197F(v)) /* 2 REG_DIS_ATIM_8197F */ #define BIT_DIS_ATIM_VAP7_8197F BIT(7) @@ -9570,21 +12490,29 @@ #define BIT_SHIFT_TSFT_SEL_TIMER1_8197F 3 #define BIT_MASK_TSFT_SEL_TIMER1_8197F 0x7 -#define BIT_TSFT_SEL_TIMER1_8197F(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8197F) << BIT_SHIFT_TSFT_SEL_TIMER1_8197F) -#define BITS_TSFT_SEL_TIMER1_8197F (BIT_MASK_TSFT_SEL_TIMER1_8197F << BIT_SHIFT_TSFT_SEL_TIMER1_8197F) +#define BIT_TSFT_SEL_TIMER1_8197F(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER1_8197F) \ + << BIT_SHIFT_TSFT_SEL_TIMER1_8197F) +#define BITS_TSFT_SEL_TIMER1_8197F \ + (BIT_MASK_TSFT_SEL_TIMER1_8197F << BIT_SHIFT_TSFT_SEL_TIMER1_8197F) #define BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8197F)) -#define BIT_GET_TSFT_SEL_TIMER1_8197F(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8197F) & BIT_MASK_TSFT_SEL_TIMER1_8197F) -#define BIT_SET_TSFT_SEL_TIMER1_8197F(x, v) (BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) | BIT_TSFT_SEL_TIMER1_8197F(v)) - +#define BIT_GET_TSFT_SEL_TIMER1_8197F(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8197F) & \ + BIT_MASK_TSFT_SEL_TIMER1_8197F) +#define BIT_SET_TSFT_SEL_TIMER1_8197F(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) | BIT_TSFT_SEL_TIMER1_8197F(v)) #define BIT_SHIFT_EARLY_128US_8197F 0 #define BIT_MASK_EARLY_128US_8197F 0x7 -#define BIT_EARLY_128US_8197F(x) (((x) & BIT_MASK_EARLY_128US_8197F) << BIT_SHIFT_EARLY_128US_8197F) -#define BITS_EARLY_128US_8197F (BIT_MASK_EARLY_128US_8197F << BIT_SHIFT_EARLY_128US_8197F) +#define BIT_EARLY_128US_8197F(x) \ + (((x) & BIT_MASK_EARLY_128US_8197F) << BIT_SHIFT_EARLY_128US_8197F) +#define BITS_EARLY_128US_8197F \ + (BIT_MASK_EARLY_128US_8197F << BIT_SHIFT_EARLY_128US_8197F) #define BIT_CLEAR_EARLY_128US_8197F(x) ((x) & (~BITS_EARLY_128US_8197F)) -#define BIT_GET_EARLY_128US_8197F(x) (((x) >> BIT_SHIFT_EARLY_128US_8197F) & BIT_MASK_EARLY_128US_8197F) -#define BIT_SET_EARLY_128US_8197F(x, v) (BIT_CLEAR_EARLY_128US_8197F(x) | BIT_EARLY_128US_8197F(v)) - +#define BIT_GET_EARLY_128US_8197F(x) \ + (((x) >> BIT_SHIFT_EARLY_128US_8197F) & BIT_MASK_EARLY_128US_8197F) +#define BIT_SET_EARLY_128US_8197F(x, v) \ + (BIT_CLEAR_EARLY_128US_8197F(x) | BIT_EARLY_128US_8197F(v)) /* 2 REG_P2PPS1_CTRL_8197F */ #define BIT_P2P1_CTW_ALLSTASLEEP_8197F BIT(7) @@ -9604,101 +12532,145 @@ #define BIT_SHIFT_SYNC_CLI_SEL_8197F 4 #define BIT_MASK_SYNC_CLI_SEL_8197F 0x7 -#define BIT_SYNC_CLI_SEL_8197F(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8197F) << BIT_SHIFT_SYNC_CLI_SEL_8197F) -#define BITS_SYNC_CLI_SEL_8197F (BIT_MASK_SYNC_CLI_SEL_8197F << BIT_SHIFT_SYNC_CLI_SEL_8197F) +#define BIT_SYNC_CLI_SEL_8197F(x) \ + (((x) & BIT_MASK_SYNC_CLI_SEL_8197F) << BIT_SHIFT_SYNC_CLI_SEL_8197F) +#define BITS_SYNC_CLI_SEL_8197F \ + (BIT_MASK_SYNC_CLI_SEL_8197F << BIT_SHIFT_SYNC_CLI_SEL_8197F) #define BIT_CLEAR_SYNC_CLI_SEL_8197F(x) ((x) & (~BITS_SYNC_CLI_SEL_8197F)) -#define BIT_GET_SYNC_CLI_SEL_8197F(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8197F) & BIT_MASK_SYNC_CLI_SEL_8197F) -#define BIT_SET_SYNC_CLI_SEL_8197F(x, v) (BIT_CLEAR_SYNC_CLI_SEL_8197F(x) | BIT_SYNC_CLI_SEL_8197F(v)) - +#define BIT_GET_SYNC_CLI_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8197F) & BIT_MASK_SYNC_CLI_SEL_8197F) +#define BIT_SET_SYNC_CLI_SEL_8197F(x, v) \ + (BIT_CLEAR_SYNC_CLI_SEL_8197F(x) | BIT_SYNC_CLI_SEL_8197F(v)) #define BIT_SHIFT_TSFT_SEL_TIMER0_8197F 0 #define BIT_MASK_TSFT_SEL_TIMER0_8197F 0x7 -#define BIT_TSFT_SEL_TIMER0_8197F(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8197F) << BIT_SHIFT_TSFT_SEL_TIMER0_8197F) -#define BITS_TSFT_SEL_TIMER0_8197F (BIT_MASK_TSFT_SEL_TIMER0_8197F << BIT_SHIFT_TSFT_SEL_TIMER0_8197F) +#define BIT_TSFT_SEL_TIMER0_8197F(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER0_8197F) \ + << BIT_SHIFT_TSFT_SEL_TIMER0_8197F) +#define BITS_TSFT_SEL_TIMER0_8197F \ + (BIT_MASK_TSFT_SEL_TIMER0_8197F << BIT_SHIFT_TSFT_SEL_TIMER0_8197F) #define BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8197F)) -#define BIT_GET_TSFT_SEL_TIMER0_8197F(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8197F) & BIT_MASK_TSFT_SEL_TIMER0_8197F) -#define BIT_SET_TSFT_SEL_TIMER0_8197F(x, v) (BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) | BIT_TSFT_SEL_TIMER0_8197F(v)) - +#define BIT_GET_TSFT_SEL_TIMER0_8197F(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8197F) & \ + BIT_MASK_TSFT_SEL_TIMER0_8197F) +#define BIT_SET_TSFT_SEL_TIMER0_8197F(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) | BIT_TSFT_SEL_TIMER0_8197F(v)) /* 2 REG_NOA_UNIT_SEL_8197F */ #define BIT_SHIFT_NOA_UNIT2_SEL_8197F 8 #define BIT_MASK_NOA_UNIT2_SEL_8197F 0x7 -#define BIT_NOA_UNIT2_SEL_8197F(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8197F) << BIT_SHIFT_NOA_UNIT2_SEL_8197F) -#define BITS_NOA_UNIT2_SEL_8197F (BIT_MASK_NOA_UNIT2_SEL_8197F << BIT_SHIFT_NOA_UNIT2_SEL_8197F) +#define BIT_NOA_UNIT2_SEL_8197F(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL_8197F) << BIT_SHIFT_NOA_UNIT2_SEL_8197F) +#define BITS_NOA_UNIT2_SEL_8197F \ + (BIT_MASK_NOA_UNIT2_SEL_8197F << BIT_SHIFT_NOA_UNIT2_SEL_8197F) #define BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT2_SEL_8197F)) -#define BIT_GET_NOA_UNIT2_SEL_8197F(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8197F) & BIT_MASK_NOA_UNIT2_SEL_8197F) -#define BIT_SET_NOA_UNIT2_SEL_8197F(x, v) (BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) | BIT_NOA_UNIT2_SEL_8197F(v)) - +#define BIT_GET_NOA_UNIT2_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8197F) & BIT_MASK_NOA_UNIT2_SEL_8197F) +#define BIT_SET_NOA_UNIT2_SEL_8197F(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) | BIT_NOA_UNIT2_SEL_8197F(v)) #define BIT_SHIFT_NOA_UNIT1_SEL_8197F 4 #define BIT_MASK_NOA_UNIT1_SEL_8197F 0x7 -#define BIT_NOA_UNIT1_SEL_8197F(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8197F) << BIT_SHIFT_NOA_UNIT1_SEL_8197F) -#define BITS_NOA_UNIT1_SEL_8197F (BIT_MASK_NOA_UNIT1_SEL_8197F << BIT_SHIFT_NOA_UNIT1_SEL_8197F) +#define BIT_NOA_UNIT1_SEL_8197F(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL_8197F) << BIT_SHIFT_NOA_UNIT1_SEL_8197F) +#define BITS_NOA_UNIT1_SEL_8197F \ + (BIT_MASK_NOA_UNIT1_SEL_8197F << BIT_SHIFT_NOA_UNIT1_SEL_8197F) #define BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT1_SEL_8197F)) -#define BIT_GET_NOA_UNIT1_SEL_8197F(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8197F) & BIT_MASK_NOA_UNIT1_SEL_8197F) -#define BIT_SET_NOA_UNIT1_SEL_8197F(x, v) (BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) | BIT_NOA_UNIT1_SEL_8197F(v)) - +#define BIT_GET_NOA_UNIT1_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8197F) & BIT_MASK_NOA_UNIT1_SEL_8197F) +#define BIT_SET_NOA_UNIT1_SEL_8197F(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) | BIT_NOA_UNIT1_SEL_8197F(v)) #define BIT_SHIFT_NOA_UNIT0_SEL_8197F 0 #define BIT_MASK_NOA_UNIT0_SEL_8197F 0x7 -#define BIT_NOA_UNIT0_SEL_8197F(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8197F) << BIT_SHIFT_NOA_UNIT0_SEL_8197F) -#define BITS_NOA_UNIT0_SEL_8197F (BIT_MASK_NOA_UNIT0_SEL_8197F << BIT_SHIFT_NOA_UNIT0_SEL_8197F) +#define BIT_NOA_UNIT0_SEL_8197F(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL_8197F) << BIT_SHIFT_NOA_UNIT0_SEL_8197F) +#define BITS_NOA_UNIT0_SEL_8197F \ + (BIT_MASK_NOA_UNIT0_SEL_8197F << BIT_SHIFT_NOA_UNIT0_SEL_8197F) #define BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT0_SEL_8197F)) -#define BIT_GET_NOA_UNIT0_SEL_8197F(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8197F) & BIT_MASK_NOA_UNIT0_SEL_8197F) -#define BIT_SET_NOA_UNIT0_SEL_8197F(x, v) (BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) | BIT_NOA_UNIT0_SEL_8197F(v)) - +#define BIT_GET_NOA_UNIT0_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8197F) & BIT_MASK_NOA_UNIT0_SEL_8197F) +#define BIT_SET_NOA_UNIT0_SEL_8197F(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) | BIT_NOA_UNIT0_SEL_8197F(v)) /* 2 REG_P2POFF_DIS_TXTIME_8197F */ #define BIT_SHIFT_P2POFF_DIS_TXTIME_8197F 0 #define BIT_MASK_P2POFF_DIS_TXTIME_8197F 0xff -#define BIT_P2POFF_DIS_TXTIME_8197F(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8197F) << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) -#define BITS_P2POFF_DIS_TXTIME_8197F (BIT_MASK_P2POFF_DIS_TXTIME_8197F << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) -#define BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) ((x) & (~BITS_P2POFF_DIS_TXTIME_8197F)) -#define BIT_GET_P2POFF_DIS_TXTIME_8197F(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) & BIT_MASK_P2POFF_DIS_TXTIME_8197F) -#define BIT_SET_P2POFF_DIS_TXTIME_8197F(x, v) (BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) | BIT_P2POFF_DIS_TXTIME_8197F(v)) - +#define BIT_P2POFF_DIS_TXTIME_8197F(x) \ + (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8197F) \ + << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) +#define BITS_P2POFF_DIS_TXTIME_8197F \ + (BIT_MASK_P2POFF_DIS_TXTIME_8197F << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) +#define BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) \ + ((x) & (~BITS_P2POFF_DIS_TXTIME_8197F)) +#define BIT_GET_P2POFF_DIS_TXTIME_8197F(x) \ + (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) & \ + BIT_MASK_P2POFF_DIS_TXTIME_8197F) +#define BIT_SET_P2POFF_DIS_TXTIME_8197F(x, v) \ + (BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) | BIT_P2POFF_DIS_TXTIME_8197F(v)) /* 2 REG_MBSSID_BCN_SPACE2_8197F */ #define BIT_SHIFT_BCN_SPACE_CLINT2_8197F 16 #define BIT_MASK_BCN_SPACE_CLINT2_8197F 0xfff -#define BIT_BCN_SPACE_CLINT2_8197F(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8197F) << BIT_SHIFT_BCN_SPACE_CLINT2_8197F) -#define BITS_BCN_SPACE_CLINT2_8197F (BIT_MASK_BCN_SPACE_CLINT2_8197F << BIT_SHIFT_BCN_SPACE_CLINT2_8197F) -#define BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) ((x) & (~BITS_BCN_SPACE_CLINT2_8197F)) -#define BIT_GET_BCN_SPACE_CLINT2_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8197F) & BIT_MASK_BCN_SPACE_CLINT2_8197F) -#define BIT_SET_BCN_SPACE_CLINT2_8197F(x, v) (BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) | BIT_BCN_SPACE_CLINT2_8197F(v)) - +#define BIT_BCN_SPACE_CLINT2_8197F(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT2_8197F) \ + << BIT_SHIFT_BCN_SPACE_CLINT2_8197F) +#define BITS_BCN_SPACE_CLINT2_8197F \ + (BIT_MASK_BCN_SPACE_CLINT2_8197F << BIT_SHIFT_BCN_SPACE_CLINT2_8197F) +#define BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT2_8197F)) +#define BIT_GET_BCN_SPACE_CLINT2_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8197F) & \ + BIT_MASK_BCN_SPACE_CLINT2_8197F) +#define BIT_SET_BCN_SPACE_CLINT2_8197F(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) | BIT_BCN_SPACE_CLINT2_8197F(v)) #define BIT_SHIFT_BCN_SPACE_CLINT1_8197F 0 #define BIT_MASK_BCN_SPACE_CLINT1_8197F 0xfff -#define BIT_BCN_SPACE_CLINT1_8197F(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8197F) << BIT_SHIFT_BCN_SPACE_CLINT1_8197F) -#define BITS_BCN_SPACE_CLINT1_8197F (BIT_MASK_BCN_SPACE_CLINT1_8197F << BIT_SHIFT_BCN_SPACE_CLINT1_8197F) -#define BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) ((x) & (~BITS_BCN_SPACE_CLINT1_8197F)) -#define BIT_GET_BCN_SPACE_CLINT1_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8197F) & BIT_MASK_BCN_SPACE_CLINT1_8197F) -#define BIT_SET_BCN_SPACE_CLINT1_8197F(x, v) (BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) | BIT_BCN_SPACE_CLINT1_8197F(v)) - +#define BIT_BCN_SPACE_CLINT1_8197F(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT1_8197F) \ + << BIT_SHIFT_BCN_SPACE_CLINT1_8197F) +#define BITS_BCN_SPACE_CLINT1_8197F \ + (BIT_MASK_BCN_SPACE_CLINT1_8197F << BIT_SHIFT_BCN_SPACE_CLINT1_8197F) +#define BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT1_8197F)) +#define BIT_GET_BCN_SPACE_CLINT1_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8197F) & \ + BIT_MASK_BCN_SPACE_CLINT1_8197F) +#define BIT_SET_BCN_SPACE_CLINT1_8197F(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) | BIT_BCN_SPACE_CLINT1_8197F(v)) /* 2 REG_MBSSID_BCN_SPACE3_8197F */ -#define BIT_SHIFT_SUB_BCN_SPACE_V1_8197F 16 -#define BIT_MASK_SUB_BCN_SPACE_V1_8197F 0xfff -#define BIT_SUB_BCN_SPACE_V1_8197F(x) (((x) & BIT_MASK_SUB_BCN_SPACE_V1_8197F) << BIT_SHIFT_SUB_BCN_SPACE_V1_8197F) -#define BITS_SUB_BCN_SPACE_V1_8197F (BIT_MASK_SUB_BCN_SPACE_V1_8197F << BIT_SHIFT_SUB_BCN_SPACE_V1_8197F) -#define BIT_CLEAR_SUB_BCN_SPACE_V1_8197F(x) ((x) & (~BITS_SUB_BCN_SPACE_V1_8197F)) -#define BIT_GET_SUB_BCN_SPACE_V1_8197F(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V1_8197F) & BIT_MASK_SUB_BCN_SPACE_V1_8197F) -#define BIT_SET_SUB_BCN_SPACE_V1_8197F(x, v) (BIT_CLEAR_SUB_BCN_SPACE_V1_8197F(x) | BIT_SUB_BCN_SPACE_V1_8197F(v)) - +#define BIT_SHIFT_SUB_BCN_SPACE_8197F 16 +#define BIT_MASK_SUB_BCN_SPACE_8197F 0xff +#define BIT_SUB_BCN_SPACE_8197F(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE_8197F) << BIT_SHIFT_SUB_BCN_SPACE_8197F) +#define BITS_SUB_BCN_SPACE_8197F \ + (BIT_MASK_SUB_BCN_SPACE_8197F << BIT_SHIFT_SUB_BCN_SPACE_8197F) +#define BIT_CLEAR_SUB_BCN_SPACE_8197F(x) ((x) & (~BITS_SUB_BCN_SPACE_8197F)) +#define BIT_GET_SUB_BCN_SPACE_8197F(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8197F) & BIT_MASK_SUB_BCN_SPACE_8197F) +#define BIT_SET_SUB_BCN_SPACE_8197F(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE_8197F(x) | BIT_SUB_BCN_SPACE_8197F(v)) #define BIT_SHIFT_BCN_SPACE_CLINT3_8197F 0 #define BIT_MASK_BCN_SPACE_CLINT3_8197F 0xfff -#define BIT_BCN_SPACE_CLINT3_8197F(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8197F) << BIT_SHIFT_BCN_SPACE_CLINT3_8197F) -#define BITS_BCN_SPACE_CLINT3_8197F (BIT_MASK_BCN_SPACE_CLINT3_8197F << BIT_SHIFT_BCN_SPACE_CLINT3_8197F) -#define BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) ((x) & (~BITS_BCN_SPACE_CLINT3_8197F)) -#define BIT_GET_BCN_SPACE_CLINT3_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8197F) & BIT_MASK_BCN_SPACE_CLINT3_8197F) -#define BIT_SET_BCN_SPACE_CLINT3_8197F(x, v) (BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) | BIT_BCN_SPACE_CLINT3_8197F(v)) - +#define BIT_BCN_SPACE_CLINT3_8197F(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT3_8197F) \ + << BIT_SHIFT_BCN_SPACE_CLINT3_8197F) +#define BITS_BCN_SPACE_CLINT3_8197F \ + (BIT_MASK_BCN_SPACE_CLINT3_8197F << BIT_SHIFT_BCN_SPACE_CLINT3_8197F) +#define BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT3_8197F)) +#define BIT_GET_BCN_SPACE_CLINT3_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8197F) & \ + BIT_MASK_BCN_SPACE_CLINT3_8197F) +#define BIT_SET_BCN_SPACE_CLINT3_8197F(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) | BIT_BCN_SPACE_CLINT3_8197F(v)) /* 2 REG_ACMHWCTRL_8197F */ #define BIT_BEQ_ACM_STATUS_8197F BIT(7) @@ -9718,205 +12690,289 @@ #define BIT_SHIFT_AVGPERIOD_8197F 0 #define BIT_MASK_AVGPERIOD_8197F 0xffff -#define BIT_AVGPERIOD_8197F(x) (((x) & BIT_MASK_AVGPERIOD_8197F) << BIT_SHIFT_AVGPERIOD_8197F) -#define BITS_AVGPERIOD_8197F (BIT_MASK_AVGPERIOD_8197F << BIT_SHIFT_AVGPERIOD_8197F) +#define BIT_AVGPERIOD_8197F(x) \ + (((x) & BIT_MASK_AVGPERIOD_8197F) << BIT_SHIFT_AVGPERIOD_8197F) +#define BITS_AVGPERIOD_8197F \ + (BIT_MASK_AVGPERIOD_8197F << BIT_SHIFT_AVGPERIOD_8197F) #define BIT_CLEAR_AVGPERIOD_8197F(x) ((x) & (~BITS_AVGPERIOD_8197F)) -#define BIT_GET_AVGPERIOD_8197F(x) (((x) >> BIT_SHIFT_AVGPERIOD_8197F) & BIT_MASK_AVGPERIOD_8197F) -#define BIT_SET_AVGPERIOD_8197F(x, v) (BIT_CLEAR_AVGPERIOD_8197F(x) | BIT_AVGPERIOD_8197F(v)) - +#define BIT_GET_AVGPERIOD_8197F(x) \ + (((x) >> BIT_SHIFT_AVGPERIOD_8197F) & BIT_MASK_AVGPERIOD_8197F) +#define BIT_SET_AVGPERIOD_8197F(x, v) \ + (BIT_CLEAR_AVGPERIOD_8197F(x) | BIT_AVGPERIOD_8197F(v)) /* 2 REG_VO_ADMTIME_8197F */ #define BIT_SHIFT_VO_ADMITTED_TIME_8197F 0 #define BIT_MASK_VO_ADMITTED_TIME_8197F 0xffff -#define BIT_VO_ADMITTED_TIME_8197F(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8197F) << BIT_SHIFT_VO_ADMITTED_TIME_8197F) -#define BITS_VO_ADMITTED_TIME_8197F (BIT_MASK_VO_ADMITTED_TIME_8197F << BIT_SHIFT_VO_ADMITTED_TIME_8197F) -#define BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) ((x) & (~BITS_VO_ADMITTED_TIME_8197F)) -#define BIT_GET_VO_ADMITTED_TIME_8197F(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8197F) & BIT_MASK_VO_ADMITTED_TIME_8197F) -#define BIT_SET_VO_ADMITTED_TIME_8197F(x, v) (BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) | BIT_VO_ADMITTED_TIME_8197F(v)) - +#define BIT_VO_ADMITTED_TIME_8197F(x) \ + (((x) & BIT_MASK_VO_ADMITTED_TIME_8197F) \ + << BIT_SHIFT_VO_ADMITTED_TIME_8197F) +#define BITS_VO_ADMITTED_TIME_8197F \ + (BIT_MASK_VO_ADMITTED_TIME_8197F << BIT_SHIFT_VO_ADMITTED_TIME_8197F) +#define BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) \ + ((x) & (~BITS_VO_ADMITTED_TIME_8197F)) +#define BIT_GET_VO_ADMITTED_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8197F) & \ + BIT_MASK_VO_ADMITTED_TIME_8197F) +#define BIT_SET_VO_ADMITTED_TIME_8197F(x, v) \ + (BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) | BIT_VO_ADMITTED_TIME_8197F(v)) /* 2 REG_VI_ADMTIME_8197F */ #define BIT_SHIFT_VI_ADMITTED_TIME_8197F 0 #define BIT_MASK_VI_ADMITTED_TIME_8197F 0xffff -#define BIT_VI_ADMITTED_TIME_8197F(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8197F) << BIT_SHIFT_VI_ADMITTED_TIME_8197F) -#define BITS_VI_ADMITTED_TIME_8197F (BIT_MASK_VI_ADMITTED_TIME_8197F << BIT_SHIFT_VI_ADMITTED_TIME_8197F) -#define BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) ((x) & (~BITS_VI_ADMITTED_TIME_8197F)) -#define BIT_GET_VI_ADMITTED_TIME_8197F(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8197F) & BIT_MASK_VI_ADMITTED_TIME_8197F) -#define BIT_SET_VI_ADMITTED_TIME_8197F(x, v) (BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) | BIT_VI_ADMITTED_TIME_8197F(v)) - +#define BIT_VI_ADMITTED_TIME_8197F(x) \ + (((x) & BIT_MASK_VI_ADMITTED_TIME_8197F) \ + << BIT_SHIFT_VI_ADMITTED_TIME_8197F) +#define BITS_VI_ADMITTED_TIME_8197F \ + (BIT_MASK_VI_ADMITTED_TIME_8197F << BIT_SHIFT_VI_ADMITTED_TIME_8197F) +#define BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) \ + ((x) & (~BITS_VI_ADMITTED_TIME_8197F)) +#define BIT_GET_VI_ADMITTED_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8197F) & \ + BIT_MASK_VI_ADMITTED_TIME_8197F) +#define BIT_SET_VI_ADMITTED_TIME_8197F(x, v) \ + (BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) | BIT_VI_ADMITTED_TIME_8197F(v)) /* 2 REG_BE_ADMTIME_8197F */ #define BIT_SHIFT_BE_ADMITTED_TIME_8197F 0 #define BIT_MASK_BE_ADMITTED_TIME_8197F 0xffff -#define BIT_BE_ADMITTED_TIME_8197F(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8197F) << BIT_SHIFT_BE_ADMITTED_TIME_8197F) -#define BITS_BE_ADMITTED_TIME_8197F (BIT_MASK_BE_ADMITTED_TIME_8197F << BIT_SHIFT_BE_ADMITTED_TIME_8197F) -#define BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) ((x) & (~BITS_BE_ADMITTED_TIME_8197F)) -#define BIT_GET_BE_ADMITTED_TIME_8197F(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8197F) & BIT_MASK_BE_ADMITTED_TIME_8197F) -#define BIT_SET_BE_ADMITTED_TIME_8197F(x, v) (BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) | BIT_BE_ADMITTED_TIME_8197F(v)) - +#define BIT_BE_ADMITTED_TIME_8197F(x) \ + (((x) & BIT_MASK_BE_ADMITTED_TIME_8197F) \ + << BIT_SHIFT_BE_ADMITTED_TIME_8197F) +#define BITS_BE_ADMITTED_TIME_8197F \ + (BIT_MASK_BE_ADMITTED_TIME_8197F << BIT_SHIFT_BE_ADMITTED_TIME_8197F) +#define BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) \ + ((x) & (~BITS_BE_ADMITTED_TIME_8197F)) +#define BIT_GET_BE_ADMITTED_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8197F) & \ + BIT_MASK_BE_ADMITTED_TIME_8197F) +#define BIT_SET_BE_ADMITTED_TIME_8197F(x, v) \ + (BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) | BIT_BE_ADMITTED_TIME_8197F(v)) /* 2 REG_NOT_VALID_8197F */ -#define BIT_CHANGE_POW_BCN_AREA_8197F BIT(1) +#define BIT_CHANGE_POW_BCN_AREA_8197F BIT(9) /* 2 REG_EDCA_RANDOM_GEN_8197F */ #define BIT_SHIFT_RANDOM_GEN_8197F 0 #define BIT_MASK_RANDOM_GEN_8197F 0xffffff -#define BIT_RANDOM_GEN_8197F(x) (((x) & BIT_MASK_RANDOM_GEN_8197F) << BIT_SHIFT_RANDOM_GEN_8197F) -#define BITS_RANDOM_GEN_8197F (BIT_MASK_RANDOM_GEN_8197F << BIT_SHIFT_RANDOM_GEN_8197F) +#define BIT_RANDOM_GEN_8197F(x) \ + (((x) & BIT_MASK_RANDOM_GEN_8197F) << BIT_SHIFT_RANDOM_GEN_8197F) +#define BITS_RANDOM_GEN_8197F \ + (BIT_MASK_RANDOM_GEN_8197F << BIT_SHIFT_RANDOM_GEN_8197F) #define BIT_CLEAR_RANDOM_GEN_8197F(x) ((x) & (~BITS_RANDOM_GEN_8197F)) -#define BIT_GET_RANDOM_GEN_8197F(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8197F) & BIT_MASK_RANDOM_GEN_8197F) -#define BIT_SET_RANDOM_GEN_8197F(x, v) (BIT_CLEAR_RANDOM_GEN_8197F(x) | BIT_RANDOM_GEN_8197F(v)) - +#define BIT_GET_RANDOM_GEN_8197F(x) \ + (((x) >> BIT_SHIFT_RANDOM_GEN_8197F) & BIT_MASK_RANDOM_GEN_8197F) +#define BIT_SET_RANDOM_GEN_8197F(x, v) \ + (BIT_CLEAR_RANDOM_GEN_8197F(x) | BIT_RANDOM_GEN_8197F(v)) /* 2 REG_TXCMD_NOA_SEL_8197F */ -#define BIT_SHIFT_NOA_SEL_8197F 4 -#define BIT_MASK_NOA_SEL_8197F 0x7 -#define BIT_NOA_SEL_8197F(x) (((x) & BIT_MASK_NOA_SEL_8197F) << BIT_SHIFT_NOA_SEL_8197F) -#define BITS_NOA_SEL_8197F (BIT_MASK_NOA_SEL_8197F << BIT_SHIFT_NOA_SEL_8197F) -#define BIT_CLEAR_NOA_SEL_8197F(x) ((x) & (~BITS_NOA_SEL_8197F)) -#define BIT_GET_NOA_SEL_8197F(x) (((x) >> BIT_SHIFT_NOA_SEL_8197F) & BIT_MASK_NOA_SEL_8197F) -#define BIT_SET_NOA_SEL_8197F(x, v) (BIT_CLEAR_NOA_SEL_8197F(x) | BIT_NOA_SEL_8197F(v)) - +#define BIT_SHIFT_NOA_SEL_V2_8197F 4 +#define BIT_MASK_NOA_SEL_V2_8197F 0x7 +#define BIT_NOA_SEL_V2_8197F(x) \ + (((x) & BIT_MASK_NOA_SEL_V2_8197F) << BIT_SHIFT_NOA_SEL_V2_8197F) +#define BITS_NOA_SEL_V2_8197F \ + (BIT_MASK_NOA_SEL_V2_8197F << BIT_SHIFT_NOA_SEL_V2_8197F) +#define BIT_CLEAR_NOA_SEL_V2_8197F(x) ((x) & (~BITS_NOA_SEL_V2_8197F)) +#define BIT_GET_NOA_SEL_V2_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V2_8197F) & BIT_MASK_NOA_SEL_V2_8197F) +#define BIT_SET_NOA_SEL_V2_8197F(x, v) \ + (BIT_CLEAR_NOA_SEL_V2_8197F(x) | BIT_NOA_SEL_V2_8197F(v)) #define BIT_SHIFT_TXCMD_SEG_SEL_8197F 0 #define BIT_MASK_TXCMD_SEG_SEL_8197F 0xf -#define BIT_TXCMD_SEG_SEL_8197F(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8197F) << BIT_SHIFT_TXCMD_SEG_SEL_8197F) -#define BITS_TXCMD_SEG_SEL_8197F (BIT_MASK_TXCMD_SEG_SEL_8197F << BIT_SHIFT_TXCMD_SEG_SEL_8197F) +#define BIT_TXCMD_SEG_SEL_8197F(x) \ + (((x) & BIT_MASK_TXCMD_SEG_SEL_8197F) << BIT_SHIFT_TXCMD_SEG_SEL_8197F) +#define BITS_TXCMD_SEG_SEL_8197F \ + (BIT_MASK_TXCMD_SEG_SEL_8197F << BIT_SHIFT_TXCMD_SEG_SEL_8197F) #define BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) ((x) & (~BITS_TXCMD_SEG_SEL_8197F)) -#define BIT_GET_TXCMD_SEG_SEL_8197F(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8197F) & BIT_MASK_TXCMD_SEG_SEL_8197F) -#define BIT_SET_TXCMD_SEG_SEL_8197F(x, v) (BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) | BIT_TXCMD_SEG_SEL_8197F(v)) - +#define BIT_GET_TXCMD_SEG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8197F) & BIT_MASK_TXCMD_SEG_SEL_8197F) +#define BIT_SET_TXCMD_SEG_SEL_8197F(x, v) \ + (BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) | BIT_TXCMD_SEG_SEL_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_BCNERR_CNT_EN_8197F BIT(20) #define BIT_SHIFT_BCNERR_PORT_SEL_8197F 16 #define BIT_MASK_BCNERR_PORT_SEL_8197F 0x7 -#define BIT_BCNERR_PORT_SEL_8197F(x) (((x) & BIT_MASK_BCNERR_PORT_SEL_8197F) << BIT_SHIFT_BCNERR_PORT_SEL_8197F) -#define BITS_BCNERR_PORT_SEL_8197F (BIT_MASK_BCNERR_PORT_SEL_8197F << BIT_SHIFT_BCNERR_PORT_SEL_8197F) +#define BIT_BCNERR_PORT_SEL_8197F(x) \ + (((x) & BIT_MASK_BCNERR_PORT_SEL_8197F) \ + << BIT_SHIFT_BCNERR_PORT_SEL_8197F) +#define BITS_BCNERR_PORT_SEL_8197F \ + (BIT_MASK_BCNERR_PORT_SEL_8197F << BIT_SHIFT_BCNERR_PORT_SEL_8197F) #define BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) ((x) & (~BITS_BCNERR_PORT_SEL_8197F)) -#define BIT_GET_BCNERR_PORT_SEL_8197F(x) (((x) >> BIT_SHIFT_BCNERR_PORT_SEL_8197F) & BIT_MASK_BCNERR_PORT_SEL_8197F) -#define BIT_SET_BCNERR_PORT_SEL_8197F(x, v) (BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) | BIT_BCNERR_PORT_SEL_8197F(v)) - +#define BIT_GET_BCNERR_PORT_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_BCNERR_PORT_SEL_8197F) & \ + BIT_MASK_BCNERR_PORT_SEL_8197F) +#define BIT_SET_BCNERR_PORT_SEL_8197F(x, v) \ + (BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) | BIT_BCNERR_PORT_SEL_8197F(v)) #define BIT_SHIFT_TXPAUSE1_8197F 8 #define BIT_MASK_TXPAUSE1_8197F 0xff -#define BIT_TXPAUSE1_8197F(x) (((x) & BIT_MASK_TXPAUSE1_8197F) << BIT_SHIFT_TXPAUSE1_8197F) -#define BITS_TXPAUSE1_8197F (BIT_MASK_TXPAUSE1_8197F << BIT_SHIFT_TXPAUSE1_8197F) +#define BIT_TXPAUSE1_8197F(x) \ + (((x) & BIT_MASK_TXPAUSE1_8197F) << BIT_SHIFT_TXPAUSE1_8197F) +#define BITS_TXPAUSE1_8197F \ + (BIT_MASK_TXPAUSE1_8197F << BIT_SHIFT_TXPAUSE1_8197F) #define BIT_CLEAR_TXPAUSE1_8197F(x) ((x) & (~BITS_TXPAUSE1_8197F)) -#define BIT_GET_TXPAUSE1_8197F(x) (((x) >> BIT_SHIFT_TXPAUSE1_8197F) & BIT_MASK_TXPAUSE1_8197F) -#define BIT_SET_TXPAUSE1_8197F(x, v) (BIT_CLEAR_TXPAUSE1_8197F(x) | BIT_TXPAUSE1_8197F(v)) - +#define BIT_GET_TXPAUSE1_8197F(x) \ + (((x) >> BIT_SHIFT_TXPAUSE1_8197F) & BIT_MASK_TXPAUSE1_8197F) +#define BIT_SET_TXPAUSE1_8197F(x, v) \ + (BIT_CLEAR_TXPAUSE1_8197F(x) | BIT_TXPAUSE1_8197F(v)) #define BIT_SHIFT_BW_CFG_8197F 0 #define BIT_MASK_BW_CFG_8197F 0x3 -#define BIT_BW_CFG_8197F(x) (((x) & BIT_MASK_BW_CFG_8197F) << BIT_SHIFT_BW_CFG_8197F) +#define BIT_BW_CFG_8197F(x) \ + (((x) & BIT_MASK_BW_CFG_8197F) << BIT_SHIFT_BW_CFG_8197F) #define BITS_BW_CFG_8197F (BIT_MASK_BW_CFG_8197F << BIT_SHIFT_BW_CFG_8197F) #define BIT_CLEAR_BW_CFG_8197F(x) ((x) & (~BITS_BW_CFG_8197F)) -#define BIT_GET_BW_CFG_8197F(x) (((x) >> BIT_SHIFT_BW_CFG_8197F) & BIT_MASK_BW_CFG_8197F) -#define BIT_SET_BW_CFG_8197F(x, v) (BIT_CLEAR_BW_CFG_8197F(x) | BIT_BW_CFG_8197F(v)) - +#define BIT_GET_BW_CFG_8197F(x) \ + (((x) >> BIT_SHIFT_BW_CFG_8197F) & BIT_MASK_BW_CFG_8197F) +#define BIT_SET_BW_CFG_8197F(x, v) \ + (BIT_CLEAR_BW_CFG_8197F(x) | BIT_BW_CFG_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_SHIFT_RXBCN_TIMER_8197F 16 #define BIT_MASK_RXBCN_TIMER_8197F 0xffff -#define BIT_RXBCN_TIMER_8197F(x) (((x) & BIT_MASK_RXBCN_TIMER_8197F) << BIT_SHIFT_RXBCN_TIMER_8197F) -#define BITS_RXBCN_TIMER_8197F (BIT_MASK_RXBCN_TIMER_8197F << BIT_SHIFT_RXBCN_TIMER_8197F) +#define BIT_RXBCN_TIMER_8197F(x) \ + (((x) & BIT_MASK_RXBCN_TIMER_8197F) << BIT_SHIFT_RXBCN_TIMER_8197F) +#define BITS_RXBCN_TIMER_8197F \ + (BIT_MASK_RXBCN_TIMER_8197F << BIT_SHIFT_RXBCN_TIMER_8197F) #define BIT_CLEAR_RXBCN_TIMER_8197F(x) ((x) & (~BITS_RXBCN_TIMER_8197F)) -#define BIT_GET_RXBCN_TIMER_8197F(x) (((x) >> BIT_SHIFT_RXBCN_TIMER_8197F) & BIT_MASK_RXBCN_TIMER_8197F) -#define BIT_SET_RXBCN_TIMER_8197F(x, v) (BIT_CLEAR_RXBCN_TIMER_8197F(x) | BIT_RXBCN_TIMER_8197F(v)) - +#define BIT_GET_RXBCN_TIMER_8197F(x) \ + (((x) >> BIT_SHIFT_RXBCN_TIMER_8197F) & BIT_MASK_RXBCN_TIMER_8197F) +#define BIT_SET_RXBCN_TIMER_8197F(x, v) \ + (BIT_CLEAR_RXBCN_TIMER_8197F(x) | BIT_RXBCN_TIMER_8197F(v)) #define BIT_SHIFT_BCN_ELY_ADJ_8197F 0 #define BIT_MASK_BCN_ELY_ADJ_8197F 0xffff -#define BIT_BCN_ELY_ADJ_8197F(x) (((x) & BIT_MASK_BCN_ELY_ADJ_8197F) << BIT_SHIFT_BCN_ELY_ADJ_8197F) -#define BITS_BCN_ELY_ADJ_8197F (BIT_MASK_BCN_ELY_ADJ_8197F << BIT_SHIFT_BCN_ELY_ADJ_8197F) +#define BIT_BCN_ELY_ADJ_8197F(x) \ + (((x) & BIT_MASK_BCN_ELY_ADJ_8197F) << BIT_SHIFT_BCN_ELY_ADJ_8197F) +#define BITS_BCN_ELY_ADJ_8197F \ + (BIT_MASK_BCN_ELY_ADJ_8197F << BIT_SHIFT_BCN_ELY_ADJ_8197F) #define BIT_CLEAR_BCN_ELY_ADJ_8197F(x) ((x) & (~BITS_BCN_ELY_ADJ_8197F)) -#define BIT_GET_BCN_ELY_ADJ_8197F(x) (((x) >> BIT_SHIFT_BCN_ELY_ADJ_8197F) & BIT_MASK_BCN_ELY_ADJ_8197F) -#define BIT_SET_BCN_ELY_ADJ_8197F(x, v) (BIT_CLEAR_BCN_ELY_ADJ_8197F(x) | BIT_BCN_ELY_ADJ_8197F(v)) - +#define BIT_GET_BCN_ELY_ADJ_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_ELY_ADJ_8197F) & BIT_MASK_BCN_ELY_ADJ_8197F) +#define BIT_SET_BCN_ELY_ADJ_8197F(x, v) \ + (BIT_CLEAR_BCN_ELY_ADJ_8197F(x) | BIT_BCN_ELY_ADJ_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_SHIFT_BCNERR_CNT_OTHERS_8197F 24 #define BIT_MASK_BCNERR_CNT_OTHERS_8197F 0xff -#define BIT_BCNERR_CNT_OTHERS_8197F(x) (((x) & BIT_MASK_BCNERR_CNT_OTHERS_8197F) << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) -#define BITS_BCNERR_CNT_OTHERS_8197F (BIT_MASK_BCNERR_CNT_OTHERS_8197F << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) -#define BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) ((x) & (~BITS_BCNERR_CNT_OTHERS_8197F)) -#define BIT_GET_BCNERR_CNT_OTHERS_8197F(x) (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) & BIT_MASK_BCNERR_CNT_OTHERS_8197F) -#define BIT_SET_BCNERR_CNT_OTHERS_8197F(x, v) (BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) | BIT_BCNERR_CNT_OTHERS_8197F(v)) - +#define BIT_BCNERR_CNT_OTHERS_8197F(x) \ + (((x) & BIT_MASK_BCNERR_CNT_OTHERS_8197F) \ + << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) +#define BITS_BCNERR_CNT_OTHERS_8197F \ + (BIT_MASK_BCNERR_CNT_OTHERS_8197F << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) +#define BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) \ + ((x) & (~BITS_BCNERR_CNT_OTHERS_8197F)) +#define BIT_GET_BCNERR_CNT_OTHERS_8197F(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) & \ + BIT_MASK_BCNERR_CNT_OTHERS_8197F) +#define BIT_SET_BCNERR_CNT_OTHERS_8197F(x, v) \ + (BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) | BIT_BCNERR_CNT_OTHERS_8197F(v)) #define BIT_SHIFT_BCNERR_CNT_INVALID_8197F 16 #define BIT_MASK_BCNERR_CNT_INVALID_8197F 0xff -#define BIT_BCNERR_CNT_INVALID_8197F(x) (((x) & BIT_MASK_BCNERR_CNT_INVALID_8197F) << BIT_SHIFT_BCNERR_CNT_INVALID_8197F) -#define BITS_BCNERR_CNT_INVALID_8197F (BIT_MASK_BCNERR_CNT_INVALID_8197F << BIT_SHIFT_BCNERR_CNT_INVALID_8197F) -#define BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) ((x) & (~BITS_BCNERR_CNT_INVALID_8197F)) -#define BIT_GET_BCNERR_CNT_INVALID_8197F(x) (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8197F) & BIT_MASK_BCNERR_CNT_INVALID_8197F) -#define BIT_SET_BCNERR_CNT_INVALID_8197F(x, v) (BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) | BIT_BCNERR_CNT_INVALID_8197F(v)) - +#define BIT_BCNERR_CNT_INVALID_8197F(x) \ + (((x) & BIT_MASK_BCNERR_CNT_INVALID_8197F) \ + << BIT_SHIFT_BCNERR_CNT_INVALID_8197F) +#define BITS_BCNERR_CNT_INVALID_8197F \ + (BIT_MASK_BCNERR_CNT_INVALID_8197F \ + << BIT_SHIFT_BCNERR_CNT_INVALID_8197F) +#define BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) \ + ((x) & (~BITS_BCNERR_CNT_INVALID_8197F)) +#define BIT_GET_BCNERR_CNT_INVALID_8197F(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8197F) & \ + BIT_MASK_BCNERR_CNT_INVALID_8197F) +#define BIT_SET_BCNERR_CNT_INVALID_8197F(x, v) \ + (BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) | \ + BIT_BCNERR_CNT_INVALID_8197F(v)) #define BIT_SHIFT_BCNERR_CNT_MAC_8197F 8 #define BIT_MASK_BCNERR_CNT_MAC_8197F 0xff -#define BIT_BCNERR_CNT_MAC_8197F(x) (((x) & BIT_MASK_BCNERR_CNT_MAC_8197F) << BIT_SHIFT_BCNERR_CNT_MAC_8197F) -#define BITS_BCNERR_CNT_MAC_8197F (BIT_MASK_BCNERR_CNT_MAC_8197F << BIT_SHIFT_BCNERR_CNT_MAC_8197F) +#define BIT_BCNERR_CNT_MAC_8197F(x) \ + (((x) & BIT_MASK_BCNERR_CNT_MAC_8197F) \ + << BIT_SHIFT_BCNERR_CNT_MAC_8197F) +#define BITS_BCNERR_CNT_MAC_8197F \ + (BIT_MASK_BCNERR_CNT_MAC_8197F << BIT_SHIFT_BCNERR_CNT_MAC_8197F) #define BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) ((x) & (~BITS_BCNERR_CNT_MAC_8197F)) -#define BIT_GET_BCNERR_CNT_MAC_8197F(x) (((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8197F) & BIT_MASK_BCNERR_CNT_MAC_8197F) -#define BIT_SET_BCNERR_CNT_MAC_8197F(x, v) (BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) | BIT_BCNERR_CNT_MAC_8197F(v)) - +#define BIT_GET_BCNERR_CNT_MAC_8197F(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8197F) & \ + BIT_MASK_BCNERR_CNT_MAC_8197F) +#define BIT_SET_BCNERR_CNT_MAC_8197F(x, v) \ + (BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) | BIT_BCNERR_CNT_MAC_8197F(v)) #define BIT_SHIFT_BCNERR_CNT_CCA_8197F 0 #define BIT_MASK_BCNERR_CNT_CCA_8197F 0xff -#define BIT_BCNERR_CNT_CCA_8197F(x) (((x) & BIT_MASK_BCNERR_CNT_CCA_8197F) << BIT_SHIFT_BCNERR_CNT_CCA_8197F) -#define BITS_BCNERR_CNT_CCA_8197F (BIT_MASK_BCNERR_CNT_CCA_8197F << BIT_SHIFT_BCNERR_CNT_CCA_8197F) +#define BIT_BCNERR_CNT_CCA_8197F(x) \ + (((x) & BIT_MASK_BCNERR_CNT_CCA_8197F) \ + << BIT_SHIFT_BCNERR_CNT_CCA_8197F) +#define BITS_BCNERR_CNT_CCA_8197F \ + (BIT_MASK_BCNERR_CNT_CCA_8197F << BIT_SHIFT_BCNERR_CNT_CCA_8197F) #define BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) ((x) & (~BITS_BCNERR_CNT_CCA_8197F)) -#define BIT_GET_BCNERR_CNT_CCA_8197F(x) (((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8197F) & BIT_MASK_BCNERR_CNT_CCA_8197F) -#define BIT_SET_BCNERR_CNT_CCA_8197F(x, v) (BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) | BIT_BCNERR_CNT_CCA_8197F(v)) - +#define BIT_GET_BCNERR_CNT_CCA_8197F(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8197F) & \ + BIT_MASK_BCNERR_CNT_CCA_8197F) +#define BIT_SET_BCNERR_CNT_CCA_8197F(x, v) \ + (BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) | BIT_BCNERR_CNT_CCA_8197F(v)) /* 2 REG_NOA_PARAM_8197F */ #define BIT_SHIFT_NOA_COUNT_8197F (96 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_COUNT_8197F 0xff -#define BIT_NOA_COUNT_8197F(x) (((x) & BIT_MASK_NOA_COUNT_8197F) << BIT_SHIFT_NOA_COUNT_8197F) -#define BITS_NOA_COUNT_8197F (BIT_MASK_NOA_COUNT_8197F << BIT_SHIFT_NOA_COUNT_8197F) +#define BIT_NOA_COUNT_8197F(x) \ + (((x) & BIT_MASK_NOA_COUNT_8197F) << BIT_SHIFT_NOA_COUNT_8197F) +#define BITS_NOA_COUNT_8197F \ + (BIT_MASK_NOA_COUNT_8197F << BIT_SHIFT_NOA_COUNT_8197F) #define BIT_CLEAR_NOA_COUNT_8197F(x) ((x) & (~BITS_NOA_COUNT_8197F)) -#define BIT_GET_NOA_COUNT_8197F(x) (((x) >> BIT_SHIFT_NOA_COUNT_8197F) & BIT_MASK_NOA_COUNT_8197F) -#define BIT_SET_NOA_COUNT_8197F(x, v) (BIT_CLEAR_NOA_COUNT_8197F(x) | BIT_NOA_COUNT_8197F(v)) - +#define BIT_GET_NOA_COUNT_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_8197F) & BIT_MASK_NOA_COUNT_8197F) +#define BIT_SET_NOA_COUNT_8197F(x, v) \ + (BIT_CLEAR_NOA_COUNT_8197F(x) | BIT_NOA_COUNT_8197F(v)) #define BIT_SHIFT_NOA_START_TIME_8197F (64 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_START_TIME_8197F 0xffffffffL -#define BIT_NOA_START_TIME_8197F(x) (((x) & BIT_MASK_NOA_START_TIME_8197F) << BIT_SHIFT_NOA_START_TIME_8197F) -#define BITS_NOA_START_TIME_8197F (BIT_MASK_NOA_START_TIME_8197F << BIT_SHIFT_NOA_START_TIME_8197F) +#define BIT_NOA_START_TIME_8197F(x) \ + (((x) & BIT_MASK_NOA_START_TIME_8197F) \ + << BIT_SHIFT_NOA_START_TIME_8197F) +#define BITS_NOA_START_TIME_8197F \ + (BIT_MASK_NOA_START_TIME_8197F << BIT_SHIFT_NOA_START_TIME_8197F) #define BIT_CLEAR_NOA_START_TIME_8197F(x) ((x) & (~BITS_NOA_START_TIME_8197F)) -#define BIT_GET_NOA_START_TIME_8197F(x) (((x) >> BIT_SHIFT_NOA_START_TIME_8197F) & BIT_MASK_NOA_START_TIME_8197F) -#define BIT_SET_NOA_START_TIME_8197F(x, v) (BIT_CLEAR_NOA_START_TIME_8197F(x) | BIT_NOA_START_TIME_8197F(v)) - +#define BIT_GET_NOA_START_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_START_TIME_8197F) & \ + BIT_MASK_NOA_START_TIME_8197F) +#define BIT_SET_NOA_START_TIME_8197F(x, v) \ + (BIT_CLEAR_NOA_START_TIME_8197F(x) | BIT_NOA_START_TIME_8197F(v)) #define BIT_SHIFT_NOA_INTERVAL_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_INTERVAL_8197F 0xffffffffL -#define BIT_NOA_INTERVAL_8197F(x) (((x) & BIT_MASK_NOA_INTERVAL_8197F) << BIT_SHIFT_NOA_INTERVAL_8197F) -#define BITS_NOA_INTERVAL_8197F (BIT_MASK_NOA_INTERVAL_8197F << BIT_SHIFT_NOA_INTERVAL_8197F) +#define BIT_NOA_INTERVAL_8197F(x) \ + (((x) & BIT_MASK_NOA_INTERVAL_8197F) << BIT_SHIFT_NOA_INTERVAL_8197F) +#define BITS_NOA_INTERVAL_8197F \ + (BIT_MASK_NOA_INTERVAL_8197F << BIT_SHIFT_NOA_INTERVAL_8197F) #define BIT_CLEAR_NOA_INTERVAL_8197F(x) ((x) & (~BITS_NOA_INTERVAL_8197F)) -#define BIT_GET_NOA_INTERVAL_8197F(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_8197F) & BIT_MASK_NOA_INTERVAL_8197F) -#define BIT_SET_NOA_INTERVAL_8197F(x, v) (BIT_CLEAR_NOA_INTERVAL_8197F(x) | BIT_NOA_INTERVAL_8197F(v)) - +#define BIT_GET_NOA_INTERVAL_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_INTERVAL_8197F) & BIT_MASK_NOA_INTERVAL_8197F) +#define BIT_SET_NOA_INTERVAL_8197F(x, v) \ + (BIT_CLEAR_NOA_INTERVAL_8197F(x) | BIT_NOA_INTERVAL_8197F(v)) #define BIT_SHIFT_NOA_DURATION_8197F 0 #define BIT_MASK_NOA_DURATION_8197F 0xffffffffL -#define BIT_NOA_DURATION_8197F(x) (((x) & BIT_MASK_NOA_DURATION_8197F) << BIT_SHIFT_NOA_DURATION_8197F) -#define BITS_NOA_DURATION_8197F (BIT_MASK_NOA_DURATION_8197F << BIT_SHIFT_NOA_DURATION_8197F) +#define BIT_NOA_DURATION_8197F(x) \ + (((x) & BIT_MASK_NOA_DURATION_8197F) << BIT_SHIFT_NOA_DURATION_8197F) +#define BITS_NOA_DURATION_8197F \ + (BIT_MASK_NOA_DURATION_8197F << BIT_SHIFT_NOA_DURATION_8197F) #define BIT_CLEAR_NOA_DURATION_8197F(x) ((x) & (~BITS_NOA_DURATION_8197F)) -#define BIT_GET_NOA_DURATION_8197F(x) (((x) >> BIT_SHIFT_NOA_DURATION_8197F) & BIT_MASK_NOA_DURATION_8197F) -#define BIT_SET_NOA_DURATION_8197F(x, v) (BIT_CLEAR_NOA_DURATION_8197F(x) | BIT_NOA_DURATION_8197F(v)) - +#define BIT_GET_NOA_DURATION_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION_8197F) & BIT_MASK_NOA_DURATION_8197F) +#define BIT_SET_NOA_DURATION_8197F(x, v) \ + (BIT_CLEAR_NOA_DURATION_8197F(x) | BIT_NOA_DURATION_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -9937,12 +12993,15 @@ #define BIT_SHIFT_SCH_TXCMD_8197F 0 #define BIT_MASK_SCH_TXCMD_8197F 0xffffffffL -#define BIT_SCH_TXCMD_8197F(x) (((x) & BIT_MASK_SCH_TXCMD_8197F) << BIT_SHIFT_SCH_TXCMD_8197F) -#define BITS_SCH_TXCMD_8197F (BIT_MASK_SCH_TXCMD_8197F << BIT_SHIFT_SCH_TXCMD_8197F) +#define BIT_SCH_TXCMD_8197F(x) \ + (((x) & BIT_MASK_SCH_TXCMD_8197F) << BIT_SHIFT_SCH_TXCMD_8197F) +#define BITS_SCH_TXCMD_8197F \ + (BIT_MASK_SCH_TXCMD_8197F << BIT_SHIFT_SCH_TXCMD_8197F) #define BIT_CLEAR_SCH_TXCMD_8197F(x) ((x) & (~BITS_SCH_TXCMD_8197F)) -#define BIT_GET_SCH_TXCMD_8197F(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8197F) & BIT_MASK_SCH_TXCMD_8197F) -#define BIT_SET_SCH_TXCMD_8197F(x, v) (BIT_CLEAR_SCH_TXCMD_8197F(x) | BIT_SCH_TXCMD_8197F(v)) - +#define BIT_GET_SCH_TXCMD_8197F(x) \ + (((x) >> BIT_SHIFT_SCH_TXCMD_8197F) & BIT_MASK_SCH_TXCMD_8197F) +#define BIT_SET_SCH_TXCMD_8197F(x, v) \ + (BIT_CLEAR_SCH_TXCMD_8197F(x) | BIT_SCH_TXCMD_8197F(v)) /* 2 REG_PAGE5_DUMMY_8197F */ @@ -9950,45 +13009,62 @@ #define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F 0 #define BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F 0xffffffffL -#define BIT_CPUMGQ_TX_TIMER_V1_8197F(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) -#define BITS_CPUMGQ_TX_TIMER_V1_8197F (BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) -#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8197F)) -#define BIT_GET_CPUMGQ_TX_TIMER_V1_8197F(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F) -#define BIT_SET_CPUMGQ_TX_TIMER_V1_8197F(x, v) (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) | BIT_CPUMGQ_TX_TIMER_V1_8197F(v)) - +#define BIT_CPUMGQ_TX_TIMER_V1_8197F(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) +#define BITS_CPUMGQ_TX_TIMER_V1_8197F \ + (BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8197F)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8197F(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) & \ + BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F) +#define BIT_SET_CPUMGQ_TX_TIMER_V1_8197F(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) | \ + BIT_CPUMGQ_TX_TIMER_V1_8197F(v)) /* 2 REG_PS_TIMER_A_8197F */ #define BIT_SHIFT_PS_TIMER_A_V1_8197F 0 #define BIT_MASK_PS_TIMER_A_V1_8197F 0xffffffffL -#define BIT_PS_TIMER_A_V1_8197F(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8197F) << BIT_SHIFT_PS_TIMER_A_V1_8197F) -#define BITS_PS_TIMER_A_V1_8197F (BIT_MASK_PS_TIMER_A_V1_8197F << BIT_SHIFT_PS_TIMER_A_V1_8197F) +#define BIT_PS_TIMER_A_V1_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_A_V1_8197F) << BIT_SHIFT_PS_TIMER_A_V1_8197F) +#define BITS_PS_TIMER_A_V1_8197F \ + (BIT_MASK_PS_TIMER_A_V1_8197F << BIT_SHIFT_PS_TIMER_A_V1_8197F) #define BIT_CLEAR_PS_TIMER_A_V1_8197F(x) ((x) & (~BITS_PS_TIMER_A_V1_8197F)) -#define BIT_GET_PS_TIMER_A_V1_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8197F) & BIT_MASK_PS_TIMER_A_V1_8197F) -#define BIT_SET_PS_TIMER_A_V1_8197F(x, v) (BIT_CLEAR_PS_TIMER_A_V1_8197F(x) | BIT_PS_TIMER_A_V1_8197F(v)) - +#define BIT_GET_PS_TIMER_A_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8197F) & BIT_MASK_PS_TIMER_A_V1_8197F) +#define BIT_SET_PS_TIMER_A_V1_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_A_V1_8197F(x) | BIT_PS_TIMER_A_V1_8197F(v)) /* 2 REG_PS_TIMER_B_8197F */ #define BIT_SHIFT_PS_TIMER_B_V1_8197F 0 #define BIT_MASK_PS_TIMER_B_V1_8197F 0xffffffffL -#define BIT_PS_TIMER_B_V1_8197F(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8197F) << BIT_SHIFT_PS_TIMER_B_V1_8197F) -#define BITS_PS_TIMER_B_V1_8197F (BIT_MASK_PS_TIMER_B_V1_8197F << BIT_SHIFT_PS_TIMER_B_V1_8197F) +#define BIT_PS_TIMER_B_V1_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_B_V1_8197F) << BIT_SHIFT_PS_TIMER_B_V1_8197F) +#define BITS_PS_TIMER_B_V1_8197F \ + (BIT_MASK_PS_TIMER_B_V1_8197F << BIT_SHIFT_PS_TIMER_B_V1_8197F) #define BIT_CLEAR_PS_TIMER_B_V1_8197F(x) ((x) & (~BITS_PS_TIMER_B_V1_8197F)) -#define BIT_GET_PS_TIMER_B_V1_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8197F) & BIT_MASK_PS_TIMER_B_V1_8197F) -#define BIT_SET_PS_TIMER_B_V1_8197F(x, v) (BIT_CLEAR_PS_TIMER_B_V1_8197F(x) | BIT_PS_TIMER_B_V1_8197F(v)) - +#define BIT_GET_PS_TIMER_B_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8197F) & BIT_MASK_PS_TIMER_B_V1_8197F) +#define BIT_SET_PS_TIMER_B_V1_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_B_V1_8197F(x) | BIT_PS_TIMER_B_V1_8197F(v)) /* 2 REG_PS_TIMER_C_8197F */ #define BIT_SHIFT_PS_TIMER_C_V1_8197F 0 #define BIT_MASK_PS_TIMER_C_V1_8197F 0xffffffffL -#define BIT_PS_TIMER_C_V1_8197F(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8197F) << BIT_SHIFT_PS_TIMER_C_V1_8197F) -#define BITS_PS_TIMER_C_V1_8197F (BIT_MASK_PS_TIMER_C_V1_8197F << BIT_SHIFT_PS_TIMER_C_V1_8197F) +#define BIT_PS_TIMER_C_V1_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_C_V1_8197F) << BIT_SHIFT_PS_TIMER_C_V1_8197F) +#define BITS_PS_TIMER_C_V1_8197F \ + (BIT_MASK_PS_TIMER_C_V1_8197F << BIT_SHIFT_PS_TIMER_C_V1_8197F) #define BIT_CLEAR_PS_TIMER_C_V1_8197F(x) ((x) & (~BITS_PS_TIMER_C_V1_8197F)) -#define BIT_GET_PS_TIMER_C_V1_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8197F) & BIT_MASK_PS_TIMER_C_V1_8197F) -#define BIT_SET_PS_TIMER_C_V1_8197F(x, v) (BIT_CLEAR_PS_TIMER_C_V1_8197F(x) | BIT_PS_TIMER_C_V1_8197F(v)) - +#define BIT_GET_PS_TIMER_C_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8197F) & BIT_MASK_PS_TIMER_C_V1_8197F) +#define BIT_SET_PS_TIMER_C_V1_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_C_V1_8197F(x) | BIT_PS_TIMER_C_V1_8197F(v)) /* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F */ #define BIT_CPUMGQ_TIMER_EN_8197F BIT(31) @@ -9996,98 +13072,165 @@ #define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F 24 #define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F 0x7 -#define BIT_CPUMGQ_TIMER_TSF_SEL_8197F(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) -#define BITS_CPUMGQ_TIMER_TSF_SEL_8197F (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) -#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8197F)) -#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8197F(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F) -#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8197F(x, v) (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) | BIT_CPUMGQ_TIMER_TSF_SEL_8197F(v)) +#define BIT_CPUMGQ_TIMER_TSF_SEL_8197F(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) +#define BITS_CPUMGQ_TIMER_TSF_SEL_8197F \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) \ + ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8197F)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8197F(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) | \ + BIT_CPUMGQ_TIMER_TSF_SEL_8197F(v)) #define BIT_PS_TIMER_C_EN_8197F BIT(23) #define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F 16 #define BIT_MASK_PS_TIMER_C_TSF_SEL_8197F 0x7 -#define BIT_PS_TIMER_C_TSF_SEL_8197F(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8197F) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) -#define BITS_PS_TIMER_C_TSF_SEL_8197F (BIT_MASK_PS_TIMER_C_TSF_SEL_8197F << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) -#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8197F)) -#define BIT_GET_PS_TIMER_C_TSF_SEL_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) & BIT_MASK_PS_TIMER_C_TSF_SEL_8197F) -#define BIT_SET_PS_TIMER_C_TSF_SEL_8197F(x, v) (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) | BIT_PS_TIMER_C_TSF_SEL_8197F(v)) +#define BIT_PS_TIMER_C_TSF_SEL_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8197F) \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) +#define BITS_PS_TIMER_C_TSF_SEL_8197F \ + (BIT_MASK_PS_TIMER_C_TSF_SEL_8197F \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) +#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) \ + ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8197F)) +#define BIT_GET_PS_TIMER_C_TSF_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) & \ + BIT_MASK_PS_TIMER_C_TSF_SEL_8197F) +#define BIT_SET_PS_TIMER_C_TSF_SEL_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) | \ + BIT_PS_TIMER_C_TSF_SEL_8197F(v)) #define BIT_PS_TIMER_B_EN_8197F BIT(15) #define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F 8 #define BIT_MASK_PS_TIMER_B_TSF_SEL_8197F 0x7 -#define BIT_PS_TIMER_B_TSF_SEL_8197F(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8197F) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) -#define BITS_PS_TIMER_B_TSF_SEL_8197F (BIT_MASK_PS_TIMER_B_TSF_SEL_8197F << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) -#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8197F)) -#define BIT_GET_PS_TIMER_B_TSF_SEL_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) & BIT_MASK_PS_TIMER_B_TSF_SEL_8197F) -#define BIT_SET_PS_TIMER_B_TSF_SEL_8197F(x, v) (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) | BIT_PS_TIMER_B_TSF_SEL_8197F(v)) +#define BIT_PS_TIMER_B_TSF_SEL_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8197F) \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) +#define BITS_PS_TIMER_B_TSF_SEL_8197F \ + (BIT_MASK_PS_TIMER_B_TSF_SEL_8197F \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) +#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) \ + ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8197F)) +#define BIT_GET_PS_TIMER_B_TSF_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) & \ + BIT_MASK_PS_TIMER_B_TSF_SEL_8197F) +#define BIT_SET_PS_TIMER_B_TSF_SEL_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) | \ + BIT_PS_TIMER_B_TSF_SEL_8197F(v)) #define BIT_PS_TIMER_A_EN_8197F BIT(7) #define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F 0 #define BIT_MASK_PS_TIMER_A_TSF_SEL_8197F 0x7 -#define BIT_PS_TIMER_A_TSF_SEL_8197F(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8197F) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) -#define BITS_PS_TIMER_A_TSF_SEL_8197F (BIT_MASK_PS_TIMER_A_TSF_SEL_8197F << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) -#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8197F)) -#define BIT_GET_PS_TIMER_A_TSF_SEL_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) & BIT_MASK_PS_TIMER_A_TSF_SEL_8197F) -#define BIT_SET_PS_TIMER_A_TSF_SEL_8197F(x, v) (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) | BIT_PS_TIMER_A_TSF_SEL_8197F(v)) - +#define BIT_PS_TIMER_A_TSF_SEL_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8197F) \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) +#define BITS_PS_TIMER_A_TSF_SEL_8197F \ + (BIT_MASK_PS_TIMER_A_TSF_SEL_8197F \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) +#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) \ + ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8197F)) +#define BIT_GET_PS_TIMER_A_TSF_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) & \ + BIT_MASK_PS_TIMER_A_TSF_SEL_8197F) +#define BIT_SET_PS_TIMER_A_TSF_SEL_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) | \ + BIT_PS_TIMER_A_TSF_SEL_8197F(v)) /* 2 REG_CPUMGQ_TX_TIMER_EARLY_8197F */ #define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F 0 #define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F 0xff -#define BIT_CPUMGQ_TX_TIMER_EARLY_8197F(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) -#define BITS_CPUMGQ_TX_TIMER_EARLY_8197F (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) -#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8197F)) -#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8197F(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F) -#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8197F(x, v) (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) | BIT_CPUMGQ_TX_TIMER_EARLY_8197F(v)) - +#define BIT_CPUMGQ_TX_TIMER_EARLY_8197F(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) +#define BITS_CPUMGQ_TX_TIMER_EARLY_8197F \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8197F)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8197F(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8197F(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) | \ + BIT_CPUMGQ_TX_TIMER_EARLY_8197F(v)) /* 2 REG_PS_TIMER_A_EARLY_8197F */ #define BIT_SHIFT_PS_TIMER_A_EARLY_8197F 0 #define BIT_MASK_PS_TIMER_A_EARLY_8197F 0xff -#define BIT_PS_TIMER_A_EARLY_8197F(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8197F) << BIT_SHIFT_PS_TIMER_A_EARLY_8197F) -#define BITS_PS_TIMER_A_EARLY_8197F (BIT_MASK_PS_TIMER_A_EARLY_8197F << BIT_SHIFT_PS_TIMER_A_EARLY_8197F) -#define BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) ((x) & (~BITS_PS_TIMER_A_EARLY_8197F)) -#define BIT_GET_PS_TIMER_A_EARLY_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8197F) & BIT_MASK_PS_TIMER_A_EARLY_8197F) -#define BIT_SET_PS_TIMER_A_EARLY_8197F(x, v) (BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) | BIT_PS_TIMER_A_EARLY_8197F(v)) - +#define BIT_PS_TIMER_A_EARLY_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_A_EARLY_8197F) \ + << BIT_SHIFT_PS_TIMER_A_EARLY_8197F) +#define BITS_PS_TIMER_A_EARLY_8197F \ + (BIT_MASK_PS_TIMER_A_EARLY_8197F << BIT_SHIFT_PS_TIMER_A_EARLY_8197F) +#define BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) \ + ((x) & (~BITS_PS_TIMER_A_EARLY_8197F)) +#define BIT_GET_PS_TIMER_A_EARLY_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8197F) & \ + BIT_MASK_PS_TIMER_A_EARLY_8197F) +#define BIT_SET_PS_TIMER_A_EARLY_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) | BIT_PS_TIMER_A_EARLY_8197F(v)) /* 2 REG_PS_TIMER_B_EARLY_8197F */ #define BIT_SHIFT_PS_TIMER_B_EARLY_8197F 0 #define BIT_MASK_PS_TIMER_B_EARLY_8197F 0xff -#define BIT_PS_TIMER_B_EARLY_8197F(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8197F) << BIT_SHIFT_PS_TIMER_B_EARLY_8197F) -#define BITS_PS_TIMER_B_EARLY_8197F (BIT_MASK_PS_TIMER_B_EARLY_8197F << BIT_SHIFT_PS_TIMER_B_EARLY_8197F) -#define BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) ((x) & (~BITS_PS_TIMER_B_EARLY_8197F)) -#define BIT_GET_PS_TIMER_B_EARLY_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8197F) & BIT_MASK_PS_TIMER_B_EARLY_8197F) -#define BIT_SET_PS_TIMER_B_EARLY_8197F(x, v) (BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) | BIT_PS_TIMER_B_EARLY_8197F(v)) - +#define BIT_PS_TIMER_B_EARLY_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_B_EARLY_8197F) \ + << BIT_SHIFT_PS_TIMER_B_EARLY_8197F) +#define BITS_PS_TIMER_B_EARLY_8197F \ + (BIT_MASK_PS_TIMER_B_EARLY_8197F << BIT_SHIFT_PS_TIMER_B_EARLY_8197F) +#define BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) \ + ((x) & (~BITS_PS_TIMER_B_EARLY_8197F)) +#define BIT_GET_PS_TIMER_B_EARLY_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8197F) & \ + BIT_MASK_PS_TIMER_B_EARLY_8197F) +#define BIT_SET_PS_TIMER_B_EARLY_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) | BIT_PS_TIMER_B_EARLY_8197F(v)) /* 2 REG_PS_TIMER_C_EARLY_8197F */ #define BIT_SHIFT_PS_TIMER_C_EARLY_8197F 0 #define BIT_MASK_PS_TIMER_C_EARLY_8197F 0xff -#define BIT_PS_TIMER_C_EARLY_8197F(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8197F) << BIT_SHIFT_PS_TIMER_C_EARLY_8197F) -#define BITS_PS_TIMER_C_EARLY_8197F (BIT_MASK_PS_TIMER_C_EARLY_8197F << BIT_SHIFT_PS_TIMER_C_EARLY_8197F) -#define BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) ((x) & (~BITS_PS_TIMER_C_EARLY_8197F)) -#define BIT_GET_PS_TIMER_C_EARLY_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8197F) & BIT_MASK_PS_TIMER_C_EARLY_8197F) -#define BIT_SET_PS_TIMER_C_EARLY_8197F(x, v) (BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) | BIT_PS_TIMER_C_EARLY_8197F(v)) - +#define BIT_PS_TIMER_C_EARLY_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_C_EARLY_8197F) \ + << BIT_SHIFT_PS_TIMER_C_EARLY_8197F) +#define BITS_PS_TIMER_C_EARLY_8197F \ + (BIT_MASK_PS_TIMER_C_EARLY_8197F << BIT_SHIFT_PS_TIMER_C_EARLY_8197F) +#define BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) \ + ((x) & (~BITS_PS_TIMER_C_EARLY_8197F)) +#define BIT_GET_PS_TIMER_C_EARLY_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8197F) & \ + BIT_MASK_PS_TIMER_C_EARLY_8197F) +#define BIT_SET_PS_TIMER_C_EARLY_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) | BIT_PS_TIMER_C_EARLY_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_STOP_CPUMGQ_8197F BIT(16) #define BIT_SHIFT_CPUMGQ_PARAMETER_8197F 0 #define BIT_MASK_CPUMGQ_PARAMETER_8197F 0xffff -#define BIT_CPUMGQ_PARAMETER_8197F(x) (((x) & BIT_MASK_CPUMGQ_PARAMETER_8197F) << BIT_SHIFT_CPUMGQ_PARAMETER_8197F) -#define BITS_CPUMGQ_PARAMETER_8197F (BIT_MASK_CPUMGQ_PARAMETER_8197F << BIT_SHIFT_CPUMGQ_PARAMETER_8197F) -#define BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) ((x) & (~BITS_CPUMGQ_PARAMETER_8197F)) -#define BIT_GET_CPUMGQ_PARAMETER_8197F(x) (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER_8197F) & BIT_MASK_CPUMGQ_PARAMETER_8197F) -#define BIT_SET_CPUMGQ_PARAMETER_8197F(x, v) (BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) | BIT_CPUMGQ_PARAMETER_8197F(v)) - +#define BIT_CPUMGQ_PARAMETER_8197F(x) \ + (((x) & BIT_MASK_CPUMGQ_PARAMETER_8197F) \ + << BIT_SHIFT_CPUMGQ_PARAMETER_8197F) +#define BITS_CPUMGQ_PARAMETER_8197F \ + (BIT_MASK_CPUMGQ_PARAMETER_8197F << BIT_SHIFT_CPUMGQ_PARAMETER_8197F) +#define BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) \ + ((x) & (~BITS_CPUMGQ_PARAMETER_8197F)) +#define BIT_GET_CPUMGQ_PARAMETER_8197F(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER_8197F) & \ + BIT_MASK_CPUMGQ_PARAMETER_8197F) +#define BIT_SET_CPUMGQ_PARAMETER_8197F(x, v) \ + (BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) | BIT_CPUMGQ_PARAMETER_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -10101,12 +13244,17 @@ #define BIT_SHIFT_APPEND_MHDR_LEN_8197F 0 #define BIT_MASK_APPEND_MHDR_LEN_8197F 0x7 -#define BIT_APPEND_MHDR_LEN_8197F(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8197F) << BIT_SHIFT_APPEND_MHDR_LEN_8197F) -#define BITS_APPEND_MHDR_LEN_8197F (BIT_MASK_APPEND_MHDR_LEN_8197F << BIT_SHIFT_APPEND_MHDR_LEN_8197F) +#define BIT_APPEND_MHDR_LEN_8197F(x) \ + (((x) & BIT_MASK_APPEND_MHDR_LEN_8197F) \ + << BIT_SHIFT_APPEND_MHDR_LEN_8197F) +#define BITS_APPEND_MHDR_LEN_8197F \ + (BIT_MASK_APPEND_MHDR_LEN_8197F << BIT_SHIFT_APPEND_MHDR_LEN_8197F) #define BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) ((x) & (~BITS_APPEND_MHDR_LEN_8197F)) -#define BIT_GET_APPEND_MHDR_LEN_8197F(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8197F) & BIT_MASK_APPEND_MHDR_LEN_8197F) -#define BIT_SET_APPEND_MHDR_LEN_8197F(x, v) (BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) | BIT_APPEND_MHDR_LEN_8197F(v)) - +#define BIT_GET_APPEND_MHDR_LEN_8197F(x) \ + (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8197F) & \ + BIT_MASK_APPEND_MHDR_LEN_8197F) +#define BIT_SET_APPEND_MHDR_LEN_8197F(x, v) \ + (BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) | BIT_APPEND_MHDR_LEN_8197F(v)) /* 2 REG_WMAC_CR_8197F (WMAC CR AND APSD CONTROL REGISTER) */ #define BIT_APSDOFF_8197F BIT(6) @@ -10182,56 +13330,69 @@ #define BIT_SHIFT_DRVINFO_SZ_V1_8197F 0 #define BIT_MASK_DRVINFO_SZ_V1_8197F 0xf -#define BIT_DRVINFO_SZ_V1_8197F(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8197F) << BIT_SHIFT_DRVINFO_SZ_V1_8197F) -#define BITS_DRVINFO_SZ_V1_8197F (BIT_MASK_DRVINFO_SZ_V1_8197F << BIT_SHIFT_DRVINFO_SZ_V1_8197F) +#define BIT_DRVINFO_SZ_V1_8197F(x) \ + (((x) & BIT_MASK_DRVINFO_SZ_V1_8197F) << BIT_SHIFT_DRVINFO_SZ_V1_8197F) +#define BITS_DRVINFO_SZ_V1_8197F \ + (BIT_MASK_DRVINFO_SZ_V1_8197F << BIT_SHIFT_DRVINFO_SZ_V1_8197F) #define BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) ((x) & (~BITS_DRVINFO_SZ_V1_8197F)) -#define BIT_GET_DRVINFO_SZ_V1_8197F(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8197F) & BIT_MASK_DRVINFO_SZ_V1_8197F) -#define BIT_SET_DRVINFO_SZ_V1_8197F(x, v) (BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) | BIT_DRVINFO_SZ_V1_8197F(v)) - +#define BIT_GET_DRVINFO_SZ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8197F) & BIT_MASK_DRVINFO_SZ_V1_8197F) +#define BIT_SET_DRVINFO_SZ_V1_8197F(x, v) \ + (BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) | BIT_DRVINFO_SZ_V1_8197F(v)) /* 2 REG_RX_DLK_TIME_8197F (RX DEADLOCK TIME REGISTER) */ #define BIT_SHIFT_RX_DLK_TIME_8197F 0 #define BIT_MASK_RX_DLK_TIME_8197F 0xff -#define BIT_RX_DLK_TIME_8197F(x) (((x) & BIT_MASK_RX_DLK_TIME_8197F) << BIT_SHIFT_RX_DLK_TIME_8197F) -#define BITS_RX_DLK_TIME_8197F (BIT_MASK_RX_DLK_TIME_8197F << BIT_SHIFT_RX_DLK_TIME_8197F) +#define BIT_RX_DLK_TIME_8197F(x) \ + (((x) & BIT_MASK_RX_DLK_TIME_8197F) << BIT_SHIFT_RX_DLK_TIME_8197F) +#define BITS_RX_DLK_TIME_8197F \ + (BIT_MASK_RX_DLK_TIME_8197F << BIT_SHIFT_RX_DLK_TIME_8197F) #define BIT_CLEAR_RX_DLK_TIME_8197F(x) ((x) & (~BITS_RX_DLK_TIME_8197F)) -#define BIT_GET_RX_DLK_TIME_8197F(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8197F) & BIT_MASK_RX_DLK_TIME_8197F) -#define BIT_SET_RX_DLK_TIME_8197F(x, v) (BIT_CLEAR_RX_DLK_TIME_8197F(x) | BIT_RX_DLK_TIME_8197F(v)) - +#define BIT_GET_RX_DLK_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_RX_DLK_TIME_8197F) & BIT_MASK_RX_DLK_TIME_8197F) +#define BIT_SET_RX_DLK_TIME_8197F(x, v) \ + (BIT_CLEAR_RX_DLK_TIME_8197F(x) | BIT_RX_DLK_TIME_8197F(v)) /* 2 REG_RX_PKT_LIMIT_8197F (RX PACKET LENGTH LIMIT REGISTER) */ #define BIT_SHIFT_RXPKTLMT_8197F 0 #define BIT_MASK_RXPKTLMT_8197F 0x3f -#define BIT_RXPKTLMT_8197F(x) (((x) & BIT_MASK_RXPKTLMT_8197F) << BIT_SHIFT_RXPKTLMT_8197F) -#define BITS_RXPKTLMT_8197F (BIT_MASK_RXPKTLMT_8197F << BIT_SHIFT_RXPKTLMT_8197F) +#define BIT_RXPKTLMT_8197F(x) \ + (((x) & BIT_MASK_RXPKTLMT_8197F) << BIT_SHIFT_RXPKTLMT_8197F) +#define BITS_RXPKTLMT_8197F \ + (BIT_MASK_RXPKTLMT_8197F << BIT_SHIFT_RXPKTLMT_8197F) #define BIT_CLEAR_RXPKTLMT_8197F(x) ((x) & (~BITS_RXPKTLMT_8197F)) -#define BIT_GET_RXPKTLMT_8197F(x) (((x) >> BIT_SHIFT_RXPKTLMT_8197F) & BIT_MASK_RXPKTLMT_8197F) -#define BIT_SET_RXPKTLMT_8197F(x, v) (BIT_CLEAR_RXPKTLMT_8197F(x) | BIT_RXPKTLMT_8197F(v)) - +#define BIT_GET_RXPKTLMT_8197F(x) \ + (((x) >> BIT_SHIFT_RXPKTLMT_8197F) & BIT_MASK_RXPKTLMT_8197F) +#define BIT_SET_RXPKTLMT_8197F(x, v) \ + (BIT_CLEAR_RXPKTLMT_8197F(x) | BIT_RXPKTLMT_8197F(v)) /* 2 REG_MACID_8197F (MAC ID REGISTER) */ #define BIT_SHIFT_MACID_8197F 0 #define BIT_MASK_MACID_8197F 0xffffffffffffL -#define BIT_MACID_8197F(x) (((x) & BIT_MASK_MACID_8197F) << BIT_SHIFT_MACID_8197F) +#define BIT_MACID_8197F(x) \ + (((x) & BIT_MASK_MACID_8197F) << BIT_SHIFT_MACID_8197F) #define BITS_MACID_8197F (BIT_MASK_MACID_8197F << BIT_SHIFT_MACID_8197F) #define BIT_CLEAR_MACID_8197F(x) ((x) & (~BITS_MACID_8197F)) -#define BIT_GET_MACID_8197F(x) (((x) >> BIT_SHIFT_MACID_8197F) & BIT_MASK_MACID_8197F) -#define BIT_SET_MACID_8197F(x, v) (BIT_CLEAR_MACID_8197F(x) | BIT_MACID_8197F(v)) - +#define BIT_GET_MACID_8197F(x) \ + (((x) >> BIT_SHIFT_MACID_8197F) & BIT_MASK_MACID_8197F) +#define BIT_SET_MACID_8197F(x, v) \ + (BIT_CLEAR_MACID_8197F(x) | BIT_MACID_8197F(v)) /* 2 REG_BSSID_8197F (BSSID REGISTER) */ #define BIT_SHIFT_BSSID_8197F 0 #define BIT_MASK_BSSID_8197F 0xffffffffffffL -#define BIT_BSSID_8197F(x) (((x) & BIT_MASK_BSSID_8197F) << BIT_SHIFT_BSSID_8197F) +#define BIT_BSSID_8197F(x) \ + (((x) & BIT_MASK_BSSID_8197F) << BIT_SHIFT_BSSID_8197F) #define BITS_BSSID_8197F (BIT_MASK_BSSID_8197F << BIT_SHIFT_BSSID_8197F) #define BIT_CLEAR_BSSID_8197F(x) ((x) & (~BITS_BSSID_8197F)) -#define BIT_GET_BSSID_8197F(x) (((x) >> BIT_SHIFT_BSSID_8197F) & BIT_MASK_BSSID_8197F) -#define BIT_SET_BSSID_8197F(x, v) (BIT_CLEAR_BSSID_8197F(x) | BIT_BSSID_8197F(v)) - +#define BIT_GET_BSSID_8197F(x) \ + (((x) >> BIT_SHIFT_BSSID_8197F) & BIT_MASK_BSSID_8197F) +#define BIT_SET_BSSID_8197F(x, v) \ + (BIT_CLEAR_BSSID_8197F(x) | BIT_BSSID_8197F(v)) /* 2 REG_MAR_8197F (MULTICAST ADDRESS REGISTER) */ @@ -10243,29 +13404,40 @@ #define BIT_GET_MAR_8197F(x) (((x) >> BIT_SHIFT_MAR_8197F) & BIT_MASK_MAR_8197F) #define BIT_SET_MAR_8197F(x, v) (BIT_CLEAR_MAR_8197F(x) | BIT_MAR_8197F(v)) - /* 2 REG_MBIDCAMCFG_1_8197F (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_SHIFT_MBIDCAM_RWDATA_L_8197F 0 #define BIT_MASK_MBIDCAM_RWDATA_L_8197F 0xffffffffL -#define BIT_MBIDCAM_RWDATA_L_8197F(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8197F) << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) -#define BITS_MBIDCAM_RWDATA_L_8197F (BIT_MASK_MBIDCAM_RWDATA_L_8197F << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) -#define BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) ((x) & (~BITS_MBIDCAM_RWDATA_L_8197F)) -#define BIT_GET_MBIDCAM_RWDATA_L_8197F(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) & BIT_MASK_MBIDCAM_RWDATA_L_8197F) -#define BIT_SET_MBIDCAM_RWDATA_L_8197F(x, v) (BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) | BIT_MBIDCAM_RWDATA_L_8197F(v)) - +#define BIT_MBIDCAM_RWDATA_L_8197F(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8197F) \ + << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) +#define BITS_MBIDCAM_RWDATA_L_8197F \ + (BIT_MASK_MBIDCAM_RWDATA_L_8197F << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) +#define BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_L_8197F)) +#define BIT_GET_MBIDCAM_RWDATA_L_8197F(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) & \ + BIT_MASK_MBIDCAM_RWDATA_L_8197F) +#define BIT_SET_MBIDCAM_RWDATA_L_8197F(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) | BIT_MBIDCAM_RWDATA_L_8197F(v)) /* 2 REG_MBIDCAMCFG_2_8197F (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_MBIDCAM_POLL_8197F BIT(31) #define BIT_MBIDCAM_WT_EN_8197F BIT(30) -#define BIT_SHIFT_MBIDCAM_ADDR_8197F 24 -#define BIT_MASK_MBIDCAM_ADDR_8197F 0x1f -#define BIT_MBIDCAM_ADDR_8197F(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8197F) << BIT_SHIFT_MBIDCAM_ADDR_8197F) -#define BITS_MBIDCAM_ADDR_8197F (BIT_MASK_MBIDCAM_ADDR_8197F << BIT_SHIFT_MBIDCAM_ADDR_8197F) -#define BIT_CLEAR_MBIDCAM_ADDR_8197F(x) ((x) & (~BITS_MBIDCAM_ADDR_8197F)) -#define BIT_GET_MBIDCAM_ADDR_8197F(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8197F) & BIT_MASK_MBIDCAM_ADDR_8197F) -#define BIT_SET_MBIDCAM_ADDR_8197F(x, v) (BIT_CLEAR_MBIDCAM_ADDR_8197F(x) | BIT_MBIDCAM_ADDR_8197F(v)) +#define BIT_SHIFT_MBIDCAM_ADDR_V1_8197F 24 +#define BIT_MASK_MBIDCAM_ADDR_V1_8197F 0x3f +#define BIT_MBIDCAM_ADDR_V1_8197F(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR_V1_8197F) \ + << BIT_SHIFT_MBIDCAM_ADDR_V1_8197F) +#define BITS_MBIDCAM_ADDR_V1_8197F \ + (BIT_MASK_MBIDCAM_ADDR_V1_8197F << BIT_SHIFT_MBIDCAM_ADDR_V1_8197F) +#define BIT_CLEAR_MBIDCAM_ADDR_V1_8197F(x) ((x) & (~BITS_MBIDCAM_ADDR_V1_8197F)) +#define BIT_GET_MBIDCAM_ADDR_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1_8197F) & \ + BIT_MASK_MBIDCAM_ADDR_V1_8197F) +#define BIT_SET_MBIDCAM_ADDR_V1_8197F(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR_V1_8197F(x) | BIT_MBIDCAM_ADDR_V1_8197F(v)) #define BIT_MBIDCAM_VALID_8197F BIT(23) #define BIT_LSIC_TXOP_EN_8197F BIT(17) @@ -10273,149 +13445,200 @@ #define BIT_SHIFT_MBIDCAM_RWDATA_H_8197F 0 #define BIT_MASK_MBIDCAM_RWDATA_H_8197F 0xffff -#define BIT_MBIDCAM_RWDATA_H_8197F(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8197F) << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) -#define BITS_MBIDCAM_RWDATA_H_8197F (BIT_MASK_MBIDCAM_RWDATA_H_8197F << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) -#define BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) ((x) & (~BITS_MBIDCAM_RWDATA_H_8197F)) -#define BIT_GET_MBIDCAM_RWDATA_H_8197F(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) & BIT_MASK_MBIDCAM_RWDATA_H_8197F) -#define BIT_SET_MBIDCAM_RWDATA_H_8197F(x, v) (BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) | BIT_MBIDCAM_RWDATA_H_8197F(v)) - +#define BIT_MBIDCAM_RWDATA_H_8197F(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8197F) \ + << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) +#define BITS_MBIDCAM_RWDATA_H_8197F \ + (BIT_MASK_MBIDCAM_RWDATA_H_8197F << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) +#define BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_H_8197F)) +#define BIT_GET_MBIDCAM_RWDATA_H_8197F(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) & \ + BIT_MASK_MBIDCAM_RWDATA_H_8197F) +#define BIT_SET_MBIDCAM_RWDATA_H_8197F(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) | BIT_MBIDCAM_RWDATA_H_8197F(v)) /* 2 REG_ZLD_NUM_8197F */ #define BIT_SHIFT_ZLD_NUM_8197F 0 #define BIT_MASK_ZLD_NUM_8197F 0xff -#define BIT_ZLD_NUM_8197F(x) (((x) & BIT_MASK_ZLD_NUM_8197F) << BIT_SHIFT_ZLD_NUM_8197F) +#define BIT_ZLD_NUM_8197F(x) \ + (((x) & BIT_MASK_ZLD_NUM_8197F) << BIT_SHIFT_ZLD_NUM_8197F) #define BITS_ZLD_NUM_8197F (BIT_MASK_ZLD_NUM_8197F << BIT_SHIFT_ZLD_NUM_8197F) #define BIT_CLEAR_ZLD_NUM_8197F(x) ((x) & (~BITS_ZLD_NUM_8197F)) -#define BIT_GET_ZLD_NUM_8197F(x) (((x) >> BIT_SHIFT_ZLD_NUM_8197F) & BIT_MASK_ZLD_NUM_8197F) -#define BIT_SET_ZLD_NUM_8197F(x, v) (BIT_CLEAR_ZLD_NUM_8197F(x) | BIT_ZLD_NUM_8197F(v)) - +#define BIT_GET_ZLD_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_ZLD_NUM_8197F) & BIT_MASK_ZLD_NUM_8197F) +#define BIT_SET_ZLD_NUM_8197F(x, v) \ + (BIT_CLEAR_ZLD_NUM_8197F(x) | BIT_ZLD_NUM_8197F(v)) /* 2 REG_UDF_THSD_8197F */ #define BIT_SHIFT_UDF_THSD_8197F 0 #define BIT_MASK_UDF_THSD_8197F 0xff -#define BIT_UDF_THSD_8197F(x) (((x) & BIT_MASK_UDF_THSD_8197F) << BIT_SHIFT_UDF_THSD_8197F) -#define BITS_UDF_THSD_8197F (BIT_MASK_UDF_THSD_8197F << BIT_SHIFT_UDF_THSD_8197F) +#define BIT_UDF_THSD_8197F(x) \ + (((x) & BIT_MASK_UDF_THSD_8197F) << BIT_SHIFT_UDF_THSD_8197F) +#define BITS_UDF_THSD_8197F \ + (BIT_MASK_UDF_THSD_8197F << BIT_SHIFT_UDF_THSD_8197F) #define BIT_CLEAR_UDF_THSD_8197F(x) ((x) & (~BITS_UDF_THSD_8197F)) -#define BIT_GET_UDF_THSD_8197F(x) (((x) >> BIT_SHIFT_UDF_THSD_8197F) & BIT_MASK_UDF_THSD_8197F) -#define BIT_SET_UDF_THSD_8197F(x, v) (BIT_CLEAR_UDF_THSD_8197F(x) | BIT_UDF_THSD_8197F(v)) - +#define BIT_GET_UDF_THSD_8197F(x) \ + (((x) >> BIT_SHIFT_UDF_THSD_8197F) & BIT_MASK_UDF_THSD_8197F) +#define BIT_SET_UDF_THSD_8197F(x, v) \ + (BIT_CLEAR_UDF_THSD_8197F(x) | BIT_UDF_THSD_8197F(v)) /* 2 REG_WMAC_TCR_TSFT_OFS_8197F */ #define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F 0 #define BIT_MASK_WMAC_TCR_TSFT_OFS_8197F 0xffff -#define BIT_WMAC_TCR_TSFT_OFS_8197F(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8197F) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) -#define BITS_WMAC_TCR_TSFT_OFS_8197F (BIT_MASK_WMAC_TCR_TSFT_OFS_8197F << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) -#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8197F)) -#define BIT_GET_WMAC_TCR_TSFT_OFS_8197F(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) & BIT_MASK_WMAC_TCR_TSFT_OFS_8197F) -#define BIT_SET_WMAC_TCR_TSFT_OFS_8197F(x, v) (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) | BIT_WMAC_TCR_TSFT_OFS_8197F(v)) - +#define BIT_WMAC_TCR_TSFT_OFS_8197F(x) \ + (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8197F) \ + << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) +#define BITS_WMAC_TCR_TSFT_OFS_8197F \ + (BIT_MASK_WMAC_TCR_TSFT_OFS_8197F << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) \ + ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8197F)) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) & \ + BIT_MASK_WMAC_TCR_TSFT_OFS_8197F) +#define BIT_SET_WMAC_TCR_TSFT_OFS_8197F(x, v) \ + (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) | BIT_WMAC_TCR_TSFT_OFS_8197F(v)) /* 2 REG_MCU_TEST_2_V1_8197F */ #define BIT_SHIFT_MCU_RSVD_2_V1_8197F 0 #define BIT_MASK_MCU_RSVD_2_V1_8197F 0xffff -#define BIT_MCU_RSVD_2_V1_8197F(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8197F) << BIT_SHIFT_MCU_RSVD_2_V1_8197F) -#define BITS_MCU_RSVD_2_V1_8197F (BIT_MASK_MCU_RSVD_2_V1_8197F << BIT_SHIFT_MCU_RSVD_2_V1_8197F) +#define BIT_MCU_RSVD_2_V1_8197F(x) \ + (((x) & BIT_MASK_MCU_RSVD_2_V1_8197F) << BIT_SHIFT_MCU_RSVD_2_V1_8197F) +#define BITS_MCU_RSVD_2_V1_8197F \ + (BIT_MASK_MCU_RSVD_2_V1_8197F << BIT_SHIFT_MCU_RSVD_2_V1_8197F) #define BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) ((x) & (~BITS_MCU_RSVD_2_V1_8197F)) -#define BIT_GET_MCU_RSVD_2_V1_8197F(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8197F) & BIT_MASK_MCU_RSVD_2_V1_8197F) -#define BIT_SET_MCU_RSVD_2_V1_8197F(x, v) (BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) | BIT_MCU_RSVD_2_V1_8197F(v)) - +#define BIT_GET_MCU_RSVD_2_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8197F) & BIT_MASK_MCU_RSVD_2_V1_8197F) +#define BIT_SET_MCU_RSVD_2_V1_8197F(x, v) \ + (BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) | BIT_MCU_RSVD_2_V1_8197F(v)) /* 2 REG_WMAC_TXTIMEOUT_8197F */ #define BIT_SHIFT_WMAC_TXTIMEOUT_8197F 0 #define BIT_MASK_WMAC_TXTIMEOUT_8197F 0xff -#define BIT_WMAC_TXTIMEOUT_8197F(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8197F) << BIT_SHIFT_WMAC_TXTIMEOUT_8197F) -#define BITS_WMAC_TXTIMEOUT_8197F (BIT_MASK_WMAC_TXTIMEOUT_8197F << BIT_SHIFT_WMAC_TXTIMEOUT_8197F) +#define BIT_WMAC_TXTIMEOUT_8197F(x) \ + (((x) & BIT_MASK_WMAC_TXTIMEOUT_8197F) \ + << BIT_SHIFT_WMAC_TXTIMEOUT_8197F) +#define BITS_WMAC_TXTIMEOUT_8197F \ + (BIT_MASK_WMAC_TXTIMEOUT_8197F << BIT_SHIFT_WMAC_TXTIMEOUT_8197F) #define BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8197F)) -#define BIT_GET_WMAC_TXTIMEOUT_8197F(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8197F) & BIT_MASK_WMAC_TXTIMEOUT_8197F) -#define BIT_SET_WMAC_TXTIMEOUT_8197F(x, v) (BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) | BIT_WMAC_TXTIMEOUT_8197F(v)) - +#define BIT_GET_WMAC_TXTIMEOUT_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8197F) & \ + BIT_MASK_WMAC_TXTIMEOUT_8197F) +#define BIT_SET_WMAC_TXTIMEOUT_8197F(x, v) \ + (BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) | BIT_WMAC_TXTIMEOUT_8197F(v)) /* 2 REG_STMP_THSD_8197F */ #define BIT_SHIFT_STMP_THSD_8197F 0 #define BIT_MASK_STMP_THSD_8197F 0xff -#define BIT_STMP_THSD_8197F(x) (((x) & BIT_MASK_STMP_THSD_8197F) << BIT_SHIFT_STMP_THSD_8197F) -#define BITS_STMP_THSD_8197F (BIT_MASK_STMP_THSD_8197F << BIT_SHIFT_STMP_THSD_8197F) +#define BIT_STMP_THSD_8197F(x) \ + (((x) & BIT_MASK_STMP_THSD_8197F) << BIT_SHIFT_STMP_THSD_8197F) +#define BITS_STMP_THSD_8197F \ + (BIT_MASK_STMP_THSD_8197F << BIT_SHIFT_STMP_THSD_8197F) #define BIT_CLEAR_STMP_THSD_8197F(x) ((x) & (~BITS_STMP_THSD_8197F)) -#define BIT_GET_STMP_THSD_8197F(x) (((x) >> BIT_SHIFT_STMP_THSD_8197F) & BIT_MASK_STMP_THSD_8197F) -#define BIT_SET_STMP_THSD_8197F(x, v) (BIT_CLEAR_STMP_THSD_8197F(x) | BIT_STMP_THSD_8197F(v)) - +#define BIT_GET_STMP_THSD_8197F(x) \ + (((x) >> BIT_SHIFT_STMP_THSD_8197F) & BIT_MASK_STMP_THSD_8197F) +#define BIT_SET_STMP_THSD_8197F(x, v) \ + (BIT_CLEAR_STMP_THSD_8197F(x) | BIT_STMP_THSD_8197F(v)) /* 2 REG_MAC_SPEC_SIFS_8197F (SPECIFICATION SIFS REGISTER) */ #define BIT_SHIFT_SPEC_SIFS_OFDM_8197F 8 #define BIT_MASK_SPEC_SIFS_OFDM_8197F 0xff -#define BIT_SPEC_SIFS_OFDM_8197F(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8197F) << BIT_SHIFT_SPEC_SIFS_OFDM_8197F) -#define BITS_SPEC_SIFS_OFDM_8197F (BIT_MASK_SPEC_SIFS_OFDM_8197F << BIT_SHIFT_SPEC_SIFS_OFDM_8197F) +#define BIT_SPEC_SIFS_OFDM_8197F(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_8197F) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_8197F) +#define BITS_SPEC_SIFS_OFDM_8197F \ + (BIT_MASK_SPEC_SIFS_OFDM_8197F << BIT_SHIFT_SPEC_SIFS_OFDM_8197F) #define BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8197F)) -#define BIT_GET_SPEC_SIFS_OFDM_8197F(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8197F) & BIT_MASK_SPEC_SIFS_OFDM_8197F) -#define BIT_SET_SPEC_SIFS_OFDM_8197F(x, v) (BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) | BIT_SPEC_SIFS_OFDM_8197F(v)) - +#define BIT_GET_SPEC_SIFS_OFDM_8197F(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8197F) & \ + BIT_MASK_SPEC_SIFS_OFDM_8197F) +#define BIT_SET_SPEC_SIFS_OFDM_8197F(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) | BIT_SPEC_SIFS_OFDM_8197F(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_8197F 0 #define BIT_MASK_SPEC_SIFS_CCK_8197F 0xff -#define BIT_SPEC_SIFS_CCK_8197F(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8197F) << BIT_SHIFT_SPEC_SIFS_CCK_8197F) -#define BITS_SPEC_SIFS_CCK_8197F (BIT_MASK_SPEC_SIFS_CCK_8197F << BIT_SHIFT_SPEC_SIFS_CCK_8197F) +#define BIT_SPEC_SIFS_CCK_8197F(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_8197F) << BIT_SHIFT_SPEC_SIFS_CCK_8197F) +#define BITS_SPEC_SIFS_CCK_8197F \ + (BIT_MASK_SPEC_SIFS_CCK_8197F << BIT_SHIFT_SPEC_SIFS_CCK_8197F) #define BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) ((x) & (~BITS_SPEC_SIFS_CCK_8197F)) -#define BIT_GET_SPEC_SIFS_CCK_8197F(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8197F) & BIT_MASK_SPEC_SIFS_CCK_8197F) -#define BIT_SET_SPEC_SIFS_CCK_8197F(x, v) (BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) | BIT_SPEC_SIFS_CCK_8197F(v)) - +#define BIT_GET_SPEC_SIFS_CCK_8197F(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8197F) & BIT_MASK_SPEC_SIFS_CCK_8197F) +#define BIT_SET_SPEC_SIFS_CCK_8197F(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) | BIT_SPEC_SIFS_CCK_8197F(v)) /* 2 REG_USTIME_EDCA_8197F (US TIME TUNING FOR EDCA REGISTER) */ #define BIT_SHIFT_USTIME_EDCA_8197F 0 #define BIT_MASK_USTIME_EDCA_8197F 0xff -#define BIT_USTIME_EDCA_8197F(x) (((x) & BIT_MASK_USTIME_EDCA_8197F) << BIT_SHIFT_USTIME_EDCA_8197F) -#define BITS_USTIME_EDCA_8197F (BIT_MASK_USTIME_EDCA_8197F << BIT_SHIFT_USTIME_EDCA_8197F) +#define BIT_USTIME_EDCA_8197F(x) \ + (((x) & BIT_MASK_USTIME_EDCA_8197F) << BIT_SHIFT_USTIME_EDCA_8197F) +#define BITS_USTIME_EDCA_8197F \ + (BIT_MASK_USTIME_EDCA_8197F << BIT_SHIFT_USTIME_EDCA_8197F) #define BIT_CLEAR_USTIME_EDCA_8197F(x) ((x) & (~BITS_USTIME_EDCA_8197F)) -#define BIT_GET_USTIME_EDCA_8197F(x) (((x) >> BIT_SHIFT_USTIME_EDCA_8197F) & BIT_MASK_USTIME_EDCA_8197F) -#define BIT_SET_USTIME_EDCA_8197F(x, v) (BIT_CLEAR_USTIME_EDCA_8197F(x) | BIT_USTIME_EDCA_8197F(v)) - +#define BIT_GET_USTIME_EDCA_8197F(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA_8197F) & BIT_MASK_USTIME_EDCA_8197F) +#define BIT_SET_USTIME_EDCA_8197F(x, v) \ + (BIT_CLEAR_USTIME_EDCA_8197F(x) | BIT_USTIME_EDCA_8197F(v)) /* 2 REG_RESP_SIFS_OFDM_8197F (RESPONSE SIFS FOR OFDM REGISTER) */ #define BIT_SHIFT_SIFS_R2T_OFDM_8197F 8 #define BIT_MASK_SIFS_R2T_OFDM_8197F 0xff -#define BIT_SIFS_R2T_OFDM_8197F(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8197F) << BIT_SHIFT_SIFS_R2T_OFDM_8197F) -#define BITS_SIFS_R2T_OFDM_8197F (BIT_MASK_SIFS_R2T_OFDM_8197F << BIT_SHIFT_SIFS_R2T_OFDM_8197F) +#define BIT_SIFS_R2T_OFDM_8197F(x) \ + (((x) & BIT_MASK_SIFS_R2T_OFDM_8197F) << BIT_SHIFT_SIFS_R2T_OFDM_8197F) +#define BITS_SIFS_R2T_OFDM_8197F \ + (BIT_MASK_SIFS_R2T_OFDM_8197F << BIT_SHIFT_SIFS_R2T_OFDM_8197F) #define BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) ((x) & (~BITS_SIFS_R2T_OFDM_8197F)) -#define BIT_GET_SIFS_R2T_OFDM_8197F(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8197F) & BIT_MASK_SIFS_R2T_OFDM_8197F) -#define BIT_SET_SIFS_R2T_OFDM_8197F(x, v) (BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) | BIT_SIFS_R2T_OFDM_8197F(v)) - +#define BIT_GET_SIFS_R2T_OFDM_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8197F) & BIT_MASK_SIFS_R2T_OFDM_8197F) +#define BIT_SET_SIFS_R2T_OFDM_8197F(x, v) \ + (BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) | BIT_SIFS_R2T_OFDM_8197F(v)) #define BIT_SHIFT_SIFS_T2T_OFDM_8197F 0 #define BIT_MASK_SIFS_T2T_OFDM_8197F 0xff -#define BIT_SIFS_T2T_OFDM_8197F(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8197F) << BIT_SHIFT_SIFS_T2T_OFDM_8197F) -#define BITS_SIFS_T2T_OFDM_8197F (BIT_MASK_SIFS_T2T_OFDM_8197F << BIT_SHIFT_SIFS_T2T_OFDM_8197F) +#define BIT_SIFS_T2T_OFDM_8197F(x) \ + (((x) & BIT_MASK_SIFS_T2T_OFDM_8197F) << BIT_SHIFT_SIFS_T2T_OFDM_8197F) +#define BITS_SIFS_T2T_OFDM_8197F \ + (BIT_MASK_SIFS_T2T_OFDM_8197F << BIT_SHIFT_SIFS_T2T_OFDM_8197F) #define BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) ((x) & (~BITS_SIFS_T2T_OFDM_8197F)) -#define BIT_GET_SIFS_T2T_OFDM_8197F(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8197F) & BIT_MASK_SIFS_T2T_OFDM_8197F) -#define BIT_SET_SIFS_T2T_OFDM_8197F(x, v) (BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) | BIT_SIFS_T2T_OFDM_8197F(v)) - +#define BIT_GET_SIFS_T2T_OFDM_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8197F) & BIT_MASK_SIFS_T2T_OFDM_8197F) +#define BIT_SET_SIFS_T2T_OFDM_8197F(x, v) \ + (BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) | BIT_SIFS_T2T_OFDM_8197F(v)) /* 2 REG_RESP_SIFS_CCK_8197F (RESPONSE SIFS FOR CCK REGISTER) */ #define BIT_SHIFT_SIFS_R2T_CCK_8197F 8 #define BIT_MASK_SIFS_R2T_CCK_8197F 0xff -#define BIT_SIFS_R2T_CCK_8197F(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8197F) << BIT_SHIFT_SIFS_R2T_CCK_8197F) -#define BITS_SIFS_R2T_CCK_8197F (BIT_MASK_SIFS_R2T_CCK_8197F << BIT_SHIFT_SIFS_R2T_CCK_8197F) +#define BIT_SIFS_R2T_CCK_8197F(x) \ + (((x) & BIT_MASK_SIFS_R2T_CCK_8197F) << BIT_SHIFT_SIFS_R2T_CCK_8197F) +#define BITS_SIFS_R2T_CCK_8197F \ + (BIT_MASK_SIFS_R2T_CCK_8197F << BIT_SHIFT_SIFS_R2T_CCK_8197F) #define BIT_CLEAR_SIFS_R2T_CCK_8197F(x) ((x) & (~BITS_SIFS_R2T_CCK_8197F)) -#define BIT_GET_SIFS_R2T_CCK_8197F(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8197F) & BIT_MASK_SIFS_R2T_CCK_8197F) -#define BIT_SET_SIFS_R2T_CCK_8197F(x, v) (BIT_CLEAR_SIFS_R2T_CCK_8197F(x) | BIT_SIFS_R2T_CCK_8197F(v)) - +#define BIT_GET_SIFS_R2T_CCK_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8197F) & BIT_MASK_SIFS_R2T_CCK_8197F) +#define BIT_SET_SIFS_R2T_CCK_8197F(x, v) \ + (BIT_CLEAR_SIFS_R2T_CCK_8197F(x) | BIT_SIFS_R2T_CCK_8197F(v)) #define BIT_SHIFT_SIFS_T2T_CCK_8197F 0 #define BIT_MASK_SIFS_T2T_CCK_8197F 0xff -#define BIT_SIFS_T2T_CCK_8197F(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8197F) << BIT_SHIFT_SIFS_T2T_CCK_8197F) -#define BITS_SIFS_T2T_CCK_8197F (BIT_MASK_SIFS_T2T_CCK_8197F << BIT_SHIFT_SIFS_T2T_CCK_8197F) +#define BIT_SIFS_T2T_CCK_8197F(x) \ + (((x) & BIT_MASK_SIFS_T2T_CCK_8197F) << BIT_SHIFT_SIFS_T2T_CCK_8197F) +#define BITS_SIFS_T2T_CCK_8197F \ + (BIT_MASK_SIFS_T2T_CCK_8197F << BIT_SHIFT_SIFS_T2T_CCK_8197F) #define BIT_CLEAR_SIFS_T2T_CCK_8197F(x) ((x) & (~BITS_SIFS_T2T_CCK_8197F)) -#define BIT_GET_SIFS_T2T_CCK_8197F(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8197F) & BIT_MASK_SIFS_T2T_CCK_8197F) -#define BIT_SET_SIFS_T2T_CCK_8197F(x, v) (BIT_CLEAR_SIFS_T2T_CCK_8197F(x) | BIT_SIFS_T2T_CCK_8197F(v)) - +#define BIT_GET_SIFS_T2T_CCK_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8197F) & BIT_MASK_SIFS_T2T_CCK_8197F) +#define BIT_SET_SIFS_T2T_CCK_8197F(x, v) \ + (BIT_CLEAR_SIFS_T2T_CCK_8197F(x) | BIT_SIFS_T2T_CCK_8197F(v)) /* 2 REG_EIFS_8197F (EIFS REGISTER) */ @@ -10424,31 +13647,35 @@ #define BIT_EIFS_8197F(x) (((x) & BIT_MASK_EIFS_8197F) << BIT_SHIFT_EIFS_8197F) #define BITS_EIFS_8197F (BIT_MASK_EIFS_8197F << BIT_SHIFT_EIFS_8197F) #define BIT_CLEAR_EIFS_8197F(x) ((x) & (~BITS_EIFS_8197F)) -#define BIT_GET_EIFS_8197F(x) (((x) >> BIT_SHIFT_EIFS_8197F) & BIT_MASK_EIFS_8197F) +#define BIT_GET_EIFS_8197F(x) \ + (((x) >> BIT_SHIFT_EIFS_8197F) & BIT_MASK_EIFS_8197F) #define BIT_SET_EIFS_8197F(x, v) (BIT_CLEAR_EIFS_8197F(x) | BIT_EIFS_8197F(v)) - /* 2 REG_CTS2TO_8197F (CTS2 TIMEOUT REGISTER) */ #define BIT_SHIFT_CTS2TO_8197F 0 #define BIT_MASK_CTS2TO_8197F 0xff -#define BIT_CTS2TO_8197F(x) (((x) & BIT_MASK_CTS2TO_8197F) << BIT_SHIFT_CTS2TO_8197F) +#define BIT_CTS2TO_8197F(x) \ + (((x) & BIT_MASK_CTS2TO_8197F) << BIT_SHIFT_CTS2TO_8197F) #define BITS_CTS2TO_8197F (BIT_MASK_CTS2TO_8197F << BIT_SHIFT_CTS2TO_8197F) #define BIT_CLEAR_CTS2TO_8197F(x) ((x) & (~BITS_CTS2TO_8197F)) -#define BIT_GET_CTS2TO_8197F(x) (((x) >> BIT_SHIFT_CTS2TO_8197F) & BIT_MASK_CTS2TO_8197F) -#define BIT_SET_CTS2TO_8197F(x, v) (BIT_CLEAR_CTS2TO_8197F(x) | BIT_CTS2TO_8197F(v)) - +#define BIT_GET_CTS2TO_8197F(x) \ + (((x) >> BIT_SHIFT_CTS2TO_8197F) & BIT_MASK_CTS2TO_8197F) +#define BIT_SET_CTS2TO_8197F(x, v) \ + (BIT_CLEAR_CTS2TO_8197F(x) | BIT_CTS2TO_8197F(v)) /* 2 REG_ACKTO_8197F (ACK TIMEOUT REGISTER) */ #define BIT_SHIFT_ACKTO_8197F 0 #define BIT_MASK_ACKTO_8197F 0xff -#define BIT_ACKTO_8197F(x) (((x) & BIT_MASK_ACKTO_8197F) << BIT_SHIFT_ACKTO_8197F) +#define BIT_ACKTO_8197F(x) \ + (((x) & BIT_MASK_ACKTO_8197F) << BIT_SHIFT_ACKTO_8197F) #define BITS_ACKTO_8197F (BIT_MASK_ACKTO_8197F << BIT_SHIFT_ACKTO_8197F) #define BIT_CLEAR_ACKTO_8197F(x) ((x) & (~BITS_ACKTO_8197F)) -#define BIT_GET_ACKTO_8197F(x) (((x) >> BIT_SHIFT_ACKTO_8197F) & BIT_MASK_ACKTO_8197F) -#define BIT_SET_ACKTO_8197F(x, v) (BIT_CLEAR_ACKTO_8197F(x) | BIT_ACKTO_8197F(v)) - +#define BIT_GET_ACKTO_8197F(x) \ + (((x) >> BIT_SHIFT_ACKTO_8197F) & BIT_MASK_ACKTO_8197F) +#define BIT_SET_ACKTO_8197F(x, v) \ + (BIT_CLEAR_ACKTO_8197F(x) | BIT_ACKTO_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -10456,30 +13683,38 @@ #define BIT_SHIFT_NAV_UPPER_8197F 16 #define BIT_MASK_NAV_UPPER_8197F 0xff -#define BIT_NAV_UPPER_8197F(x) (((x) & BIT_MASK_NAV_UPPER_8197F) << BIT_SHIFT_NAV_UPPER_8197F) -#define BITS_NAV_UPPER_8197F (BIT_MASK_NAV_UPPER_8197F << BIT_SHIFT_NAV_UPPER_8197F) +#define BIT_NAV_UPPER_8197F(x) \ + (((x) & BIT_MASK_NAV_UPPER_8197F) << BIT_SHIFT_NAV_UPPER_8197F) +#define BITS_NAV_UPPER_8197F \ + (BIT_MASK_NAV_UPPER_8197F << BIT_SHIFT_NAV_UPPER_8197F) #define BIT_CLEAR_NAV_UPPER_8197F(x) ((x) & (~BITS_NAV_UPPER_8197F)) -#define BIT_GET_NAV_UPPER_8197F(x) (((x) >> BIT_SHIFT_NAV_UPPER_8197F) & BIT_MASK_NAV_UPPER_8197F) -#define BIT_SET_NAV_UPPER_8197F(x, v) (BIT_CLEAR_NAV_UPPER_8197F(x) | BIT_NAV_UPPER_8197F(v)) - +#define BIT_GET_NAV_UPPER_8197F(x) \ + (((x) >> BIT_SHIFT_NAV_UPPER_8197F) & BIT_MASK_NAV_UPPER_8197F) +#define BIT_SET_NAV_UPPER_8197F(x, v) \ + (BIT_CLEAR_NAV_UPPER_8197F(x) | BIT_NAV_UPPER_8197F(v)) #define BIT_SHIFT_RXMYRTS_NAV_8197F 8 #define BIT_MASK_RXMYRTS_NAV_8197F 0xf -#define BIT_RXMYRTS_NAV_8197F(x) (((x) & BIT_MASK_RXMYRTS_NAV_8197F) << BIT_SHIFT_RXMYRTS_NAV_8197F) -#define BITS_RXMYRTS_NAV_8197F (BIT_MASK_RXMYRTS_NAV_8197F << BIT_SHIFT_RXMYRTS_NAV_8197F) +#define BIT_RXMYRTS_NAV_8197F(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_8197F) << BIT_SHIFT_RXMYRTS_NAV_8197F) +#define BITS_RXMYRTS_NAV_8197F \ + (BIT_MASK_RXMYRTS_NAV_8197F << BIT_SHIFT_RXMYRTS_NAV_8197F) #define BIT_CLEAR_RXMYRTS_NAV_8197F(x) ((x) & (~BITS_RXMYRTS_NAV_8197F)) -#define BIT_GET_RXMYRTS_NAV_8197F(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8197F) & BIT_MASK_RXMYRTS_NAV_8197F) -#define BIT_SET_RXMYRTS_NAV_8197F(x, v) (BIT_CLEAR_RXMYRTS_NAV_8197F(x) | BIT_RXMYRTS_NAV_8197F(v)) - +#define BIT_GET_RXMYRTS_NAV_8197F(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_8197F) & BIT_MASK_RXMYRTS_NAV_8197F) +#define BIT_SET_RXMYRTS_NAV_8197F(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_8197F(x) | BIT_RXMYRTS_NAV_8197F(v)) #define BIT_SHIFT_RTSRST_8197F 0 #define BIT_MASK_RTSRST_8197F 0xff -#define BIT_RTSRST_8197F(x) (((x) & BIT_MASK_RTSRST_8197F) << BIT_SHIFT_RTSRST_8197F) +#define BIT_RTSRST_8197F(x) \ + (((x) & BIT_MASK_RTSRST_8197F) << BIT_SHIFT_RTSRST_8197F) #define BITS_RTSRST_8197F (BIT_MASK_RTSRST_8197F << BIT_SHIFT_RTSRST_8197F) #define BIT_CLEAR_RTSRST_8197F(x) ((x) & (~BITS_RTSRST_8197F)) -#define BIT_GET_RTSRST_8197F(x) (((x) >> BIT_SHIFT_RTSRST_8197F) & BIT_MASK_RTSRST_8197F) -#define BIT_SET_RTSRST_8197F(x, v) (BIT_CLEAR_RTSRST_8197F(x) | BIT_RTSRST_8197F(v)) - +#define BIT_GET_RTSRST_8197F(x) \ + (((x) >> BIT_SHIFT_RTSRST_8197F) & BIT_MASK_RTSRST_8197F) +#define BIT_SET_RTSRST_8197F(x, v) \ + (BIT_CLEAR_RTSRST_8197F(x) | BIT_RTSRST_8197F(v)) /* 2 REG_BACAMCMD_8197F (BLOCK ACK CAM COMMAND REGISTER) */ #define BIT_BACAM_POLL_8197F BIT(31) @@ -10488,41 +13723,52 @@ #define BIT_SHIFT_TXSBM_8197F 14 #define BIT_MASK_TXSBM_8197F 0x3 -#define BIT_TXSBM_8197F(x) (((x) & BIT_MASK_TXSBM_8197F) << BIT_SHIFT_TXSBM_8197F) +#define BIT_TXSBM_8197F(x) \ + (((x) & BIT_MASK_TXSBM_8197F) << BIT_SHIFT_TXSBM_8197F) #define BITS_TXSBM_8197F (BIT_MASK_TXSBM_8197F << BIT_SHIFT_TXSBM_8197F) #define BIT_CLEAR_TXSBM_8197F(x) ((x) & (~BITS_TXSBM_8197F)) -#define BIT_GET_TXSBM_8197F(x) (((x) >> BIT_SHIFT_TXSBM_8197F) & BIT_MASK_TXSBM_8197F) -#define BIT_SET_TXSBM_8197F(x, v) (BIT_CLEAR_TXSBM_8197F(x) | BIT_TXSBM_8197F(v)) - +#define BIT_GET_TXSBM_8197F(x) \ + (((x) >> BIT_SHIFT_TXSBM_8197F) & BIT_MASK_TXSBM_8197F) +#define BIT_SET_TXSBM_8197F(x, v) \ + (BIT_CLEAR_TXSBM_8197F(x) | BIT_TXSBM_8197F(v)) #define BIT_SHIFT_BACAM_ADDR_8197F 0 #define BIT_MASK_BACAM_ADDR_8197F 0x3f -#define BIT_BACAM_ADDR_8197F(x) (((x) & BIT_MASK_BACAM_ADDR_8197F) << BIT_SHIFT_BACAM_ADDR_8197F) -#define BITS_BACAM_ADDR_8197F (BIT_MASK_BACAM_ADDR_8197F << BIT_SHIFT_BACAM_ADDR_8197F) +#define BIT_BACAM_ADDR_8197F(x) \ + (((x) & BIT_MASK_BACAM_ADDR_8197F) << BIT_SHIFT_BACAM_ADDR_8197F) +#define BITS_BACAM_ADDR_8197F \ + (BIT_MASK_BACAM_ADDR_8197F << BIT_SHIFT_BACAM_ADDR_8197F) #define BIT_CLEAR_BACAM_ADDR_8197F(x) ((x) & (~BITS_BACAM_ADDR_8197F)) -#define BIT_GET_BACAM_ADDR_8197F(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8197F) & BIT_MASK_BACAM_ADDR_8197F) -#define BIT_SET_BACAM_ADDR_8197F(x, v) (BIT_CLEAR_BACAM_ADDR_8197F(x) | BIT_BACAM_ADDR_8197F(v)) - +#define BIT_GET_BACAM_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_BACAM_ADDR_8197F) & BIT_MASK_BACAM_ADDR_8197F) +#define BIT_SET_BACAM_ADDR_8197F(x, v) \ + (BIT_CLEAR_BACAM_ADDR_8197F(x) | BIT_BACAM_ADDR_8197F(v)) /* 2 REG_BACAMCONTENT_8197F (BLOCK ACK CAM CONTENT REGISTER) */ #define BIT_SHIFT_BA_CONTENT_H_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_BA_CONTENT_H_8197F 0xffffffffL -#define BIT_BA_CONTENT_H_8197F(x) (((x) & BIT_MASK_BA_CONTENT_H_8197F) << BIT_SHIFT_BA_CONTENT_H_8197F) -#define BITS_BA_CONTENT_H_8197F (BIT_MASK_BA_CONTENT_H_8197F << BIT_SHIFT_BA_CONTENT_H_8197F) +#define BIT_BA_CONTENT_H_8197F(x) \ + (((x) & BIT_MASK_BA_CONTENT_H_8197F) << BIT_SHIFT_BA_CONTENT_H_8197F) +#define BITS_BA_CONTENT_H_8197F \ + (BIT_MASK_BA_CONTENT_H_8197F << BIT_SHIFT_BA_CONTENT_H_8197F) #define BIT_CLEAR_BA_CONTENT_H_8197F(x) ((x) & (~BITS_BA_CONTENT_H_8197F)) -#define BIT_GET_BA_CONTENT_H_8197F(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8197F) & BIT_MASK_BA_CONTENT_H_8197F) -#define BIT_SET_BA_CONTENT_H_8197F(x, v) (BIT_CLEAR_BA_CONTENT_H_8197F(x) | BIT_BA_CONTENT_H_8197F(v)) - +#define BIT_GET_BA_CONTENT_H_8197F(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_H_8197F) & BIT_MASK_BA_CONTENT_H_8197F) +#define BIT_SET_BA_CONTENT_H_8197F(x, v) \ + (BIT_CLEAR_BA_CONTENT_H_8197F(x) | BIT_BA_CONTENT_H_8197F(v)) #define BIT_SHIFT_BA_CONTENT_L_8197F 0 #define BIT_MASK_BA_CONTENT_L_8197F 0xffffffffL -#define BIT_BA_CONTENT_L_8197F(x) (((x) & BIT_MASK_BA_CONTENT_L_8197F) << BIT_SHIFT_BA_CONTENT_L_8197F) -#define BITS_BA_CONTENT_L_8197F (BIT_MASK_BA_CONTENT_L_8197F << BIT_SHIFT_BA_CONTENT_L_8197F) +#define BIT_BA_CONTENT_L_8197F(x) \ + (((x) & BIT_MASK_BA_CONTENT_L_8197F) << BIT_SHIFT_BA_CONTENT_L_8197F) +#define BITS_BA_CONTENT_L_8197F \ + (BIT_MASK_BA_CONTENT_L_8197F << BIT_SHIFT_BA_CONTENT_L_8197F) #define BIT_CLEAR_BA_CONTENT_L_8197F(x) ((x) & (~BITS_BA_CONTENT_L_8197F)) -#define BIT_GET_BA_CONTENT_L_8197F(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8197F) & BIT_MASK_BA_CONTENT_L_8197F) -#define BIT_SET_BA_CONTENT_L_8197F(x, v) (BIT_CLEAR_BA_CONTENT_L_8197F(x) | BIT_BA_CONTENT_L_8197F(v)) - +#define BIT_GET_BA_CONTENT_L_8197F(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_L_8197F) & BIT_MASK_BA_CONTENT_L_8197F) +#define BIT_SET_BA_CONTENT_L_8197F(x, v) \ + (BIT_CLEAR_BA_CONTENT_L_8197F(x) | BIT_BA_CONTENT_L_8197F(v)) /* 2 REG_WMAC_BITMAP_CTL_8197F */ #define BIT_BITMAP_VO_8197F BIT(7) @@ -10532,11 +13778,18 @@ #define BIT_SHIFT_BITMAP_CONDITION_8197F 2 #define BIT_MASK_BITMAP_CONDITION_8197F 0x3 -#define BIT_BITMAP_CONDITION_8197F(x) (((x) & BIT_MASK_BITMAP_CONDITION_8197F) << BIT_SHIFT_BITMAP_CONDITION_8197F) -#define BITS_BITMAP_CONDITION_8197F (BIT_MASK_BITMAP_CONDITION_8197F << BIT_SHIFT_BITMAP_CONDITION_8197F) -#define BIT_CLEAR_BITMAP_CONDITION_8197F(x) ((x) & (~BITS_BITMAP_CONDITION_8197F)) -#define BIT_GET_BITMAP_CONDITION_8197F(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8197F) & BIT_MASK_BITMAP_CONDITION_8197F) -#define BIT_SET_BITMAP_CONDITION_8197F(x, v) (BIT_CLEAR_BITMAP_CONDITION_8197F(x) | BIT_BITMAP_CONDITION_8197F(v)) +#define BIT_BITMAP_CONDITION_8197F(x) \ + (((x) & BIT_MASK_BITMAP_CONDITION_8197F) \ + << BIT_SHIFT_BITMAP_CONDITION_8197F) +#define BITS_BITMAP_CONDITION_8197F \ + (BIT_MASK_BITMAP_CONDITION_8197F << BIT_SHIFT_BITMAP_CONDITION_8197F) +#define BIT_CLEAR_BITMAP_CONDITION_8197F(x) \ + ((x) & (~BITS_BITMAP_CONDITION_8197F)) +#define BIT_GET_BITMAP_CONDITION_8197F(x) \ + (((x) >> BIT_SHIFT_BITMAP_CONDITION_8197F) & \ + BIT_MASK_BITMAP_CONDITION_8197F) +#define BIT_SET_BITMAP_CONDITION_8197F(x, v) \ + (BIT_CLEAR_BITMAP_CONDITION_8197F(x) | BIT_BITMAP_CONDITION_8197F(v)) #define BIT_BITMAP_SSNBK_COUNTER_CLR_8197F BIT(1) #define BIT_BITMAP_FORCE_8197F BIT(0) @@ -10545,11 +13798,15 @@ #define BIT_SHIFT_RXPKT_TYPE_8197F 2 #define BIT_MASK_RXPKT_TYPE_8197F 0x3f -#define BIT_RXPKT_TYPE_8197F(x) (((x) & BIT_MASK_RXPKT_TYPE_8197F) << BIT_SHIFT_RXPKT_TYPE_8197F) -#define BITS_RXPKT_TYPE_8197F (BIT_MASK_RXPKT_TYPE_8197F << BIT_SHIFT_RXPKT_TYPE_8197F) +#define BIT_RXPKT_TYPE_8197F(x) \ + (((x) & BIT_MASK_RXPKT_TYPE_8197F) << BIT_SHIFT_RXPKT_TYPE_8197F) +#define BITS_RXPKT_TYPE_8197F \ + (BIT_MASK_RXPKT_TYPE_8197F << BIT_SHIFT_RXPKT_TYPE_8197F) #define BIT_CLEAR_RXPKT_TYPE_8197F(x) ((x) & (~BITS_RXPKT_TYPE_8197F)) -#define BIT_GET_RXPKT_TYPE_8197F(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8197F) & BIT_MASK_RXPKT_TYPE_8197F) -#define BIT_SET_RXPKT_TYPE_8197F(x, v) (BIT_CLEAR_RXPKT_TYPE_8197F(x) | BIT_RXPKT_TYPE_8197F(v)) +#define BIT_GET_RXPKT_TYPE_8197F(x) \ + (((x) >> BIT_SHIFT_RXPKT_TYPE_8197F) & BIT_MASK_RXPKT_TYPE_8197F) +#define BIT_SET_RXPKT_TYPE_8197F(x, v) \ + (BIT_CLEAR_RXPKT_TYPE_8197F(x) | BIT_RXPKT_TYPE_8197F(v)) #define BIT_TXACT_IND_8197F BIT(1) #define BIT_RXACT_IND_8197F BIT(0) @@ -10558,11 +13815,20 @@ #define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F 2 #define BIT_MASK_BITMAP_SSNBK_COUNTER_8197F 0x3f -#define BIT_BITMAP_SSNBK_COUNTER_8197F(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8197F) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) -#define BITS_BITMAP_SSNBK_COUNTER_8197F (BIT_MASK_BITMAP_SSNBK_COUNTER_8197F << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) -#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8197F)) -#define BIT_GET_BITMAP_SSNBK_COUNTER_8197F(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) & BIT_MASK_BITMAP_SSNBK_COUNTER_8197F) -#define BIT_SET_BITMAP_SSNBK_COUNTER_8197F(x, v) (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) | BIT_BITMAP_SSNBK_COUNTER_8197F(v)) +#define BIT_BITMAP_SSNBK_COUNTER_8197F(x) \ + (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8197F) \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) +#define BITS_BITMAP_SSNBK_COUNTER_8197F \ + (BIT_MASK_BITMAP_SSNBK_COUNTER_8197F \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) \ + ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8197F)) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8197F(x) \ + (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) & \ + BIT_MASK_BITMAP_SSNBK_COUNTER_8197F) +#define BIT_SET_BITMAP_SSNBK_COUNTER_8197F(x, v) \ + (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) | \ + BIT_BITMAP_SSNBK_COUNTER_8197F(v)) #define BIT_BITMAP_EN_8197F BIT(1) #define BIT_WMAC_BACAM_RPMEN_8197F BIT(0) @@ -10571,100 +13837,145 @@ #define BIT_SHIFT_LBDLY_8197F 0 #define BIT_MASK_LBDLY_8197F 0x1f -#define BIT_LBDLY_8197F(x) (((x) & BIT_MASK_LBDLY_8197F) << BIT_SHIFT_LBDLY_8197F) +#define BIT_LBDLY_8197F(x) \ + (((x) & BIT_MASK_LBDLY_8197F) << BIT_SHIFT_LBDLY_8197F) #define BITS_LBDLY_8197F (BIT_MASK_LBDLY_8197F << BIT_SHIFT_LBDLY_8197F) #define BIT_CLEAR_LBDLY_8197F(x) ((x) & (~BITS_LBDLY_8197F)) -#define BIT_GET_LBDLY_8197F(x) (((x) >> BIT_SHIFT_LBDLY_8197F) & BIT_MASK_LBDLY_8197F) -#define BIT_SET_LBDLY_8197F(x, v) (BIT_CLEAR_LBDLY_8197F(x) | BIT_LBDLY_8197F(v)) - +#define BIT_GET_LBDLY_8197F(x) \ + (((x) >> BIT_SHIFT_LBDLY_8197F) & BIT_MASK_LBDLY_8197F) +#define BIT_SET_LBDLY_8197F(x, v) \ + (BIT_CLEAR_LBDLY_8197F(x) | BIT_LBDLY_8197F(v)) /* 2 REG_RXERR_RPT_8197F (RX ERROR REPORT REGISTER) */ #define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F 28 #define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F 0xf -#define BIT_RXERR_RPT_SEL_V1_3_0_8197F(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) -#define BITS_RXERR_RPT_SEL_V1_3_0_8197F (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) -#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8197F)) -#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8197F(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F) -#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8197F(x, v) (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) | BIT_RXERR_RPT_SEL_V1_3_0_8197F(v)) +#define BIT_RXERR_RPT_SEL_V1_3_0_8197F(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F) \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) +#define BITS_RXERR_RPT_SEL_V1_3_0_8197F \ + (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) \ + ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8197F)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8197F(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) & \ + BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8197F(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) | \ + BIT_RXERR_RPT_SEL_V1_3_0_8197F(v)) #define BIT_RXERR_RPT_RST_8197F BIT(27) #define BIT_RXERR_RPT_SEL_V1_4_8197F BIT(26) #define BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F 24 #define BIT_MASK_UD_SELECT_BSSID_2_1_8197F 0x3 -#define BIT_UD_SELECT_BSSID_2_1_8197F(x) (((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8197F) << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) -#define BITS_UD_SELECT_BSSID_2_1_8197F (BIT_MASK_UD_SELECT_BSSID_2_1_8197F << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) -#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) ((x) & (~BITS_UD_SELECT_BSSID_2_1_8197F)) -#define BIT_GET_UD_SELECT_BSSID_2_1_8197F(x) (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) & BIT_MASK_UD_SELECT_BSSID_2_1_8197F) -#define BIT_SET_UD_SELECT_BSSID_2_1_8197F(x, v) (BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) | BIT_UD_SELECT_BSSID_2_1_8197F(v)) +#define BIT_UD_SELECT_BSSID_2_1_8197F(x) \ + (((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8197F) \ + << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) +#define BITS_UD_SELECT_BSSID_2_1_8197F \ + (BIT_MASK_UD_SELECT_BSSID_2_1_8197F \ + << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) +#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) \ + ((x) & (~BITS_UD_SELECT_BSSID_2_1_8197F)) +#define BIT_GET_UD_SELECT_BSSID_2_1_8197F(x) \ + (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) & \ + BIT_MASK_UD_SELECT_BSSID_2_1_8197F) +#define BIT_SET_UD_SELECT_BSSID_2_1_8197F(x, v) \ + (BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) | \ + BIT_UD_SELECT_BSSID_2_1_8197F(v)) #define BIT_W1S_8197F BIT(23) #define BIT_UD_SELECT_BSSID_0_8197F BIT(22) #define BIT_SHIFT_UD_SUB_TYPE_8197F 18 #define BIT_MASK_UD_SUB_TYPE_8197F 0xf -#define BIT_UD_SUB_TYPE_8197F(x) (((x) & BIT_MASK_UD_SUB_TYPE_8197F) << BIT_SHIFT_UD_SUB_TYPE_8197F) -#define BITS_UD_SUB_TYPE_8197F (BIT_MASK_UD_SUB_TYPE_8197F << BIT_SHIFT_UD_SUB_TYPE_8197F) +#define BIT_UD_SUB_TYPE_8197F(x) \ + (((x) & BIT_MASK_UD_SUB_TYPE_8197F) << BIT_SHIFT_UD_SUB_TYPE_8197F) +#define BITS_UD_SUB_TYPE_8197F \ + (BIT_MASK_UD_SUB_TYPE_8197F << BIT_SHIFT_UD_SUB_TYPE_8197F) #define BIT_CLEAR_UD_SUB_TYPE_8197F(x) ((x) & (~BITS_UD_SUB_TYPE_8197F)) -#define BIT_GET_UD_SUB_TYPE_8197F(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8197F) & BIT_MASK_UD_SUB_TYPE_8197F) -#define BIT_SET_UD_SUB_TYPE_8197F(x, v) (BIT_CLEAR_UD_SUB_TYPE_8197F(x) | BIT_UD_SUB_TYPE_8197F(v)) - +#define BIT_GET_UD_SUB_TYPE_8197F(x) \ + (((x) >> BIT_SHIFT_UD_SUB_TYPE_8197F) & BIT_MASK_UD_SUB_TYPE_8197F) +#define BIT_SET_UD_SUB_TYPE_8197F(x, v) \ + (BIT_CLEAR_UD_SUB_TYPE_8197F(x) | BIT_UD_SUB_TYPE_8197F(v)) #define BIT_SHIFT_UD_TYPE_8197F 16 #define BIT_MASK_UD_TYPE_8197F 0x3 -#define BIT_UD_TYPE_8197F(x) (((x) & BIT_MASK_UD_TYPE_8197F) << BIT_SHIFT_UD_TYPE_8197F) +#define BIT_UD_TYPE_8197F(x) \ + (((x) & BIT_MASK_UD_TYPE_8197F) << BIT_SHIFT_UD_TYPE_8197F) #define BITS_UD_TYPE_8197F (BIT_MASK_UD_TYPE_8197F << BIT_SHIFT_UD_TYPE_8197F) #define BIT_CLEAR_UD_TYPE_8197F(x) ((x) & (~BITS_UD_TYPE_8197F)) -#define BIT_GET_UD_TYPE_8197F(x) (((x) >> BIT_SHIFT_UD_TYPE_8197F) & BIT_MASK_UD_TYPE_8197F) -#define BIT_SET_UD_TYPE_8197F(x, v) (BIT_CLEAR_UD_TYPE_8197F(x) | BIT_UD_TYPE_8197F(v)) - +#define BIT_GET_UD_TYPE_8197F(x) \ + (((x) >> BIT_SHIFT_UD_TYPE_8197F) & BIT_MASK_UD_TYPE_8197F) +#define BIT_SET_UD_TYPE_8197F(x, v) \ + (BIT_CLEAR_UD_TYPE_8197F(x) | BIT_UD_TYPE_8197F(v)) #define BIT_SHIFT_RPT_COUNTER_8197F 0 #define BIT_MASK_RPT_COUNTER_8197F 0xffff -#define BIT_RPT_COUNTER_8197F(x) (((x) & BIT_MASK_RPT_COUNTER_8197F) << BIT_SHIFT_RPT_COUNTER_8197F) -#define BITS_RPT_COUNTER_8197F (BIT_MASK_RPT_COUNTER_8197F << BIT_SHIFT_RPT_COUNTER_8197F) +#define BIT_RPT_COUNTER_8197F(x) \ + (((x) & BIT_MASK_RPT_COUNTER_8197F) << BIT_SHIFT_RPT_COUNTER_8197F) +#define BITS_RPT_COUNTER_8197F \ + (BIT_MASK_RPT_COUNTER_8197F << BIT_SHIFT_RPT_COUNTER_8197F) #define BIT_CLEAR_RPT_COUNTER_8197F(x) ((x) & (~BITS_RPT_COUNTER_8197F)) -#define BIT_GET_RPT_COUNTER_8197F(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8197F) & BIT_MASK_RPT_COUNTER_8197F) -#define BIT_SET_RPT_COUNTER_8197F(x, v) (BIT_CLEAR_RPT_COUNTER_8197F(x) | BIT_RPT_COUNTER_8197F(v)) - +#define BIT_GET_RPT_COUNTER_8197F(x) \ + (((x) >> BIT_SHIFT_RPT_COUNTER_8197F) & BIT_MASK_RPT_COUNTER_8197F) +#define BIT_SET_RPT_COUNTER_8197F(x, v) \ + (BIT_CLEAR_RPT_COUNTER_8197F(x) | BIT_RPT_COUNTER_8197F(v)) /* 2 REG_WMAC_TRXPTCL_CTL_8197F (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ #define BIT_SHIFT_ACKBA_TYPSEL_8197F (60 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBA_TYPSEL_8197F 0xf -#define BIT_ACKBA_TYPSEL_8197F(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8197F) << BIT_SHIFT_ACKBA_TYPSEL_8197F) -#define BITS_ACKBA_TYPSEL_8197F (BIT_MASK_ACKBA_TYPSEL_8197F << BIT_SHIFT_ACKBA_TYPSEL_8197F) +#define BIT_ACKBA_TYPSEL_8197F(x) \ + (((x) & BIT_MASK_ACKBA_TYPSEL_8197F) << BIT_SHIFT_ACKBA_TYPSEL_8197F) +#define BITS_ACKBA_TYPSEL_8197F \ + (BIT_MASK_ACKBA_TYPSEL_8197F << BIT_SHIFT_ACKBA_TYPSEL_8197F) #define BIT_CLEAR_ACKBA_TYPSEL_8197F(x) ((x) & (~BITS_ACKBA_TYPSEL_8197F)) -#define BIT_GET_ACKBA_TYPSEL_8197F(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8197F) & BIT_MASK_ACKBA_TYPSEL_8197F) -#define BIT_SET_ACKBA_TYPSEL_8197F(x, v) (BIT_CLEAR_ACKBA_TYPSEL_8197F(x) | BIT_ACKBA_TYPSEL_8197F(v)) - +#define BIT_GET_ACKBA_TYPSEL_8197F(x) \ + (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8197F) & BIT_MASK_ACKBA_TYPSEL_8197F) +#define BIT_SET_ACKBA_TYPSEL_8197F(x, v) \ + (BIT_CLEAR_ACKBA_TYPSEL_8197F(x) | BIT_ACKBA_TYPSEL_8197F(v)) #define BIT_SHIFT_ACKBA_ACKPCHK_8197F (56 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBA_ACKPCHK_8197F 0xf -#define BIT_ACKBA_ACKPCHK_8197F(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8197F) << BIT_SHIFT_ACKBA_ACKPCHK_8197F) -#define BITS_ACKBA_ACKPCHK_8197F (BIT_MASK_ACKBA_ACKPCHK_8197F << BIT_SHIFT_ACKBA_ACKPCHK_8197F) +#define BIT_ACKBA_ACKPCHK_8197F(x) \ + (((x) & BIT_MASK_ACKBA_ACKPCHK_8197F) << BIT_SHIFT_ACKBA_ACKPCHK_8197F) +#define BITS_ACKBA_ACKPCHK_8197F \ + (BIT_MASK_ACKBA_ACKPCHK_8197F << BIT_SHIFT_ACKBA_ACKPCHK_8197F) #define BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) ((x) & (~BITS_ACKBA_ACKPCHK_8197F)) -#define BIT_GET_ACKBA_ACKPCHK_8197F(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8197F) & BIT_MASK_ACKBA_ACKPCHK_8197F) -#define BIT_SET_ACKBA_ACKPCHK_8197F(x, v) (BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) | BIT_ACKBA_ACKPCHK_8197F(v)) - +#define BIT_GET_ACKBA_ACKPCHK_8197F(x) \ + (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8197F) & BIT_MASK_ACKBA_ACKPCHK_8197F) +#define BIT_SET_ACKBA_ACKPCHK_8197F(x, v) \ + (BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) | BIT_ACKBA_ACKPCHK_8197F(v)) #define BIT_SHIFT_ACKBAR_TYPESEL_8197F (48 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBAR_TYPESEL_8197F 0xff -#define BIT_ACKBAR_TYPESEL_8197F(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8197F) << BIT_SHIFT_ACKBAR_TYPESEL_8197F) -#define BITS_ACKBAR_TYPESEL_8197F (BIT_MASK_ACKBAR_TYPESEL_8197F << BIT_SHIFT_ACKBAR_TYPESEL_8197F) +#define BIT_ACKBAR_TYPESEL_8197F(x) \ + (((x) & BIT_MASK_ACKBAR_TYPESEL_8197F) \ + << BIT_SHIFT_ACKBAR_TYPESEL_8197F) +#define BITS_ACKBAR_TYPESEL_8197F \ + (BIT_MASK_ACKBAR_TYPESEL_8197F << BIT_SHIFT_ACKBAR_TYPESEL_8197F) #define BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) ((x) & (~BITS_ACKBAR_TYPESEL_8197F)) -#define BIT_GET_ACKBAR_TYPESEL_8197F(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8197F) & BIT_MASK_ACKBAR_TYPESEL_8197F) -#define BIT_SET_ACKBAR_TYPESEL_8197F(x, v) (BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) | BIT_ACKBAR_TYPESEL_8197F(v)) - +#define BIT_GET_ACKBAR_TYPESEL_8197F(x) \ + (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8197F) & \ + BIT_MASK_ACKBAR_TYPESEL_8197F) +#define BIT_SET_ACKBAR_TYPESEL_8197F(x, v) \ + (BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) | BIT_ACKBAR_TYPESEL_8197F(v)) #define BIT_SHIFT_ACKBAR_ACKPCHK_8197F (44 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBAR_ACKPCHK_8197F 0xf -#define BIT_ACKBAR_ACKPCHK_8197F(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8197F) << BIT_SHIFT_ACKBAR_ACKPCHK_8197F) -#define BITS_ACKBAR_ACKPCHK_8197F (BIT_MASK_ACKBAR_ACKPCHK_8197F << BIT_SHIFT_ACKBAR_ACKPCHK_8197F) +#define BIT_ACKBAR_ACKPCHK_8197F(x) \ + (((x) & BIT_MASK_ACKBAR_ACKPCHK_8197F) \ + << BIT_SHIFT_ACKBAR_ACKPCHK_8197F) +#define BITS_ACKBAR_ACKPCHK_8197F \ + (BIT_MASK_ACKBAR_ACKPCHK_8197F << BIT_SHIFT_ACKBAR_ACKPCHK_8197F) #define BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8197F)) -#define BIT_GET_ACKBAR_ACKPCHK_8197F(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8197F) & BIT_MASK_ACKBAR_ACKPCHK_8197F) -#define BIT_SET_ACKBAR_ACKPCHK_8197F(x, v) (BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) | BIT_ACKBAR_ACKPCHK_8197F(v)) +#define BIT_GET_ACKBAR_ACKPCHK_8197F(x) \ + (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8197F) & \ + BIT_MASK_ACKBAR_ACKPCHK_8197F) +#define BIT_SET_ACKBAR_ACKPCHK_8197F(x, v) \ + (BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) | BIT_ACKBAR_ACKPCHK_8197F(v)) #define BIT_RXBA_IGNOREA2_8197F BIT(42) #define BIT_EN_SAVE_ALL_TXOPADDR_8197F BIT(41) @@ -10688,11 +13999,15 @@ #define BIT_SHIFT_RESP_CHNBUSY_8197F 20 #define BIT_MASK_RESP_CHNBUSY_8197F 0x3 -#define BIT_RESP_CHNBUSY_8197F(x) (((x) & BIT_MASK_RESP_CHNBUSY_8197F) << BIT_SHIFT_RESP_CHNBUSY_8197F) -#define BITS_RESP_CHNBUSY_8197F (BIT_MASK_RESP_CHNBUSY_8197F << BIT_SHIFT_RESP_CHNBUSY_8197F) +#define BIT_RESP_CHNBUSY_8197F(x) \ + (((x) & BIT_MASK_RESP_CHNBUSY_8197F) << BIT_SHIFT_RESP_CHNBUSY_8197F) +#define BITS_RESP_CHNBUSY_8197F \ + (BIT_MASK_RESP_CHNBUSY_8197F << BIT_SHIFT_RESP_CHNBUSY_8197F) #define BIT_CLEAR_RESP_CHNBUSY_8197F(x) ((x) & (~BITS_RESP_CHNBUSY_8197F)) -#define BIT_GET_RESP_CHNBUSY_8197F(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8197F) & BIT_MASK_RESP_CHNBUSY_8197F) -#define BIT_SET_RESP_CHNBUSY_8197F(x, v) (BIT_CLEAR_RESP_CHNBUSY_8197F(x) | BIT_RESP_CHNBUSY_8197F(v)) +#define BIT_GET_RESP_CHNBUSY_8197F(x) \ + (((x) >> BIT_SHIFT_RESP_CHNBUSY_8197F) & BIT_MASK_RESP_CHNBUSY_8197F) +#define BIT_SET_RESP_CHNBUSY_8197F(x, v) \ + (BIT_CLEAR_RESP_CHNBUSY_8197F(x) | BIT_RESP_CHNBUSY_8197F(v)) #define BIT_RESP_DCTS_EN_8197F BIT(19) #define BIT_RESP_DCFE_EN_8197F BIT(18) @@ -10704,41 +14019,63 @@ #define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F 10 #define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F 0x7 -#define BIT_R_WMAC_SECOND_CCA_TIMER_8197F(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) -#define BITS_R_WMAC_SECOND_CCA_TIMER_8197F (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) -#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8197F)) -#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F) -#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8197F(x, v) (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) | BIT_R_WMAC_SECOND_CCA_TIMER_8197F(v)) - +#define BIT_R_WMAC_SECOND_CCA_TIMER_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F) \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) +#define BITS_R_WMAC_SECOND_CCA_TIMER_8197F \ + (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) \ + ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8197F)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) & \ + BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) | \ + BIT_R_WMAC_SECOND_CCA_TIMER_8197F(v)) #define BIT_SHIFT_RFMOD_8197F 7 #define BIT_MASK_RFMOD_8197F 0x3 -#define BIT_RFMOD_8197F(x) (((x) & BIT_MASK_RFMOD_8197F) << BIT_SHIFT_RFMOD_8197F) +#define BIT_RFMOD_8197F(x) \ + (((x) & BIT_MASK_RFMOD_8197F) << BIT_SHIFT_RFMOD_8197F) #define BITS_RFMOD_8197F (BIT_MASK_RFMOD_8197F << BIT_SHIFT_RFMOD_8197F) #define BIT_CLEAR_RFMOD_8197F(x) ((x) & (~BITS_RFMOD_8197F)) -#define BIT_GET_RFMOD_8197F(x) (((x) >> BIT_SHIFT_RFMOD_8197F) & BIT_MASK_RFMOD_8197F) -#define BIT_SET_RFMOD_8197F(x, v) (BIT_CLEAR_RFMOD_8197F(x) | BIT_RFMOD_8197F(v)) - +#define BIT_GET_RFMOD_8197F(x) \ + (((x) >> BIT_SHIFT_RFMOD_8197F) & BIT_MASK_RFMOD_8197F) +#define BIT_SET_RFMOD_8197F(x, v) \ + (BIT_CLEAR_RFMOD_8197F(x) | BIT_RFMOD_8197F(v)) #define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F 5 #define BIT_MASK_RESP_CTS_DYNBW_SEL_8197F 0x3 -#define BIT_RESP_CTS_DYNBW_SEL_8197F(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8197F) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) -#define BITS_RESP_CTS_DYNBW_SEL_8197F (BIT_MASK_RESP_CTS_DYNBW_SEL_8197F << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) -#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8197F)) -#define BIT_GET_RESP_CTS_DYNBW_SEL_8197F(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) & BIT_MASK_RESP_CTS_DYNBW_SEL_8197F) -#define BIT_SET_RESP_CTS_DYNBW_SEL_8197F(x, v) (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) | BIT_RESP_CTS_DYNBW_SEL_8197F(v)) +#define BIT_RESP_CTS_DYNBW_SEL_8197F(x) \ + (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8197F) \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) +#define BITS_RESP_CTS_DYNBW_SEL_8197F \ + (BIT_MASK_RESP_CTS_DYNBW_SEL_8197F \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) \ + ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8197F)) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) & \ + BIT_MASK_RESP_CTS_DYNBW_SEL_8197F) +#define BIT_SET_RESP_CTS_DYNBW_SEL_8197F(x, v) \ + (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) | \ + BIT_RESP_CTS_DYNBW_SEL_8197F(v)) #define BIT_DLY_TX_WAIT_RXANTSEL_8197F BIT(4) #define BIT_TXRESP_BY_RXANTSEL_8197F BIT(3) #define BIT_SHIFT_ORIG_DCTS_CHK_8197F 0 #define BIT_MASK_ORIG_DCTS_CHK_8197F 0x3 -#define BIT_ORIG_DCTS_CHK_8197F(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8197F) << BIT_SHIFT_ORIG_DCTS_CHK_8197F) -#define BITS_ORIG_DCTS_CHK_8197F (BIT_MASK_ORIG_DCTS_CHK_8197F << BIT_SHIFT_ORIG_DCTS_CHK_8197F) +#define BIT_ORIG_DCTS_CHK_8197F(x) \ + (((x) & BIT_MASK_ORIG_DCTS_CHK_8197F) << BIT_SHIFT_ORIG_DCTS_CHK_8197F) +#define BITS_ORIG_DCTS_CHK_8197F \ + (BIT_MASK_ORIG_DCTS_CHK_8197F << BIT_SHIFT_ORIG_DCTS_CHK_8197F) #define BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) ((x) & (~BITS_ORIG_DCTS_CHK_8197F)) -#define BIT_GET_ORIG_DCTS_CHK_8197F(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8197F) & BIT_MASK_ORIG_DCTS_CHK_8197F) -#define BIT_SET_ORIG_DCTS_CHK_8197F(x, v) (BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) | BIT_ORIG_DCTS_CHK_8197F(v)) - +#define BIT_GET_ORIG_DCTS_CHK_8197F(x) \ + (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8197F) & BIT_MASK_ORIG_DCTS_CHK_8197F) +#define BIT_SET_ORIG_DCTS_CHK_8197F(x, v) \ + (BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) | BIT_ORIG_DCTS_CHK_8197F(v)) /* 2 REG_CAMCMD_8197F (CAM COMMAND REGISTER) */ #define BIT_SECCAM_POLLING_8197F BIT(31) @@ -10748,34 +14085,45 @@ #define BIT_SHIFT_SECCAM_ADDR_V2_8197F 0 #define BIT_MASK_SECCAM_ADDR_V2_8197F 0x3ff -#define BIT_SECCAM_ADDR_V2_8197F(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8197F) << BIT_SHIFT_SECCAM_ADDR_V2_8197F) -#define BITS_SECCAM_ADDR_V2_8197F (BIT_MASK_SECCAM_ADDR_V2_8197F << BIT_SHIFT_SECCAM_ADDR_V2_8197F) +#define BIT_SECCAM_ADDR_V2_8197F(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V2_8197F) \ + << BIT_SHIFT_SECCAM_ADDR_V2_8197F) +#define BITS_SECCAM_ADDR_V2_8197F \ + (BIT_MASK_SECCAM_ADDR_V2_8197F << BIT_SHIFT_SECCAM_ADDR_V2_8197F) #define BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) ((x) & (~BITS_SECCAM_ADDR_V2_8197F)) -#define BIT_GET_SECCAM_ADDR_V2_8197F(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8197F) & BIT_MASK_SECCAM_ADDR_V2_8197F) -#define BIT_SET_SECCAM_ADDR_V2_8197F(x, v) (BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) | BIT_SECCAM_ADDR_V2_8197F(v)) - +#define BIT_GET_SECCAM_ADDR_V2_8197F(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8197F) & \ + BIT_MASK_SECCAM_ADDR_V2_8197F) +#define BIT_SET_SECCAM_ADDR_V2_8197F(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) | BIT_SECCAM_ADDR_V2_8197F(v)) /* 2 REG_CAMWRITE_8197F (CAM WRITE REGISTER) */ #define BIT_SHIFT_CAMW_DATA_8197F 0 #define BIT_MASK_CAMW_DATA_8197F 0xffffffffL -#define BIT_CAMW_DATA_8197F(x) (((x) & BIT_MASK_CAMW_DATA_8197F) << BIT_SHIFT_CAMW_DATA_8197F) -#define BITS_CAMW_DATA_8197F (BIT_MASK_CAMW_DATA_8197F << BIT_SHIFT_CAMW_DATA_8197F) +#define BIT_CAMW_DATA_8197F(x) \ + (((x) & BIT_MASK_CAMW_DATA_8197F) << BIT_SHIFT_CAMW_DATA_8197F) +#define BITS_CAMW_DATA_8197F \ + (BIT_MASK_CAMW_DATA_8197F << BIT_SHIFT_CAMW_DATA_8197F) #define BIT_CLEAR_CAMW_DATA_8197F(x) ((x) & (~BITS_CAMW_DATA_8197F)) -#define BIT_GET_CAMW_DATA_8197F(x) (((x) >> BIT_SHIFT_CAMW_DATA_8197F) & BIT_MASK_CAMW_DATA_8197F) -#define BIT_SET_CAMW_DATA_8197F(x, v) (BIT_CLEAR_CAMW_DATA_8197F(x) | BIT_CAMW_DATA_8197F(v)) - +#define BIT_GET_CAMW_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_CAMW_DATA_8197F) & BIT_MASK_CAMW_DATA_8197F) +#define BIT_SET_CAMW_DATA_8197F(x, v) \ + (BIT_CLEAR_CAMW_DATA_8197F(x) | BIT_CAMW_DATA_8197F(v)) /* 2 REG_CAMREAD_8197F (CAM READ REGISTER) */ #define BIT_SHIFT_CAMR_DATA_8197F 0 #define BIT_MASK_CAMR_DATA_8197F 0xffffffffL -#define BIT_CAMR_DATA_8197F(x) (((x) & BIT_MASK_CAMR_DATA_8197F) << BIT_SHIFT_CAMR_DATA_8197F) -#define BITS_CAMR_DATA_8197F (BIT_MASK_CAMR_DATA_8197F << BIT_SHIFT_CAMR_DATA_8197F) +#define BIT_CAMR_DATA_8197F(x) \ + (((x) & BIT_MASK_CAMR_DATA_8197F) << BIT_SHIFT_CAMR_DATA_8197F) +#define BITS_CAMR_DATA_8197F \ + (BIT_MASK_CAMR_DATA_8197F << BIT_SHIFT_CAMR_DATA_8197F) #define BIT_CLEAR_CAMR_DATA_8197F(x) ((x) & (~BITS_CAMR_DATA_8197F)) -#define BIT_GET_CAMR_DATA_8197F(x) (((x) >> BIT_SHIFT_CAMR_DATA_8197F) & BIT_MASK_CAMR_DATA_8197F) -#define BIT_SET_CAMR_DATA_8197F(x, v) (BIT_CLEAR_CAMR_DATA_8197F(x) | BIT_CAMR_DATA_8197F(v)) - +#define BIT_GET_CAMR_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_CAMR_DATA_8197F) & BIT_MASK_CAMR_DATA_8197F) +#define BIT_SET_CAMR_DATA_8197F(x, v) \ + (BIT_CLEAR_CAMR_DATA_8197F(x) | BIT_CAMR_DATA_8197F(v)) /* 2 REG_CAMDBG_8197F (CAM DEBUG REGISTER) */ #define BIT_SECCAM_INFO_8197F BIT(31) @@ -10783,53 +14131,89 @@ #define BIT_SHIFT_CAMDBG_SEC_TYPE_8197F 12 #define BIT_MASK_CAMDBG_SEC_TYPE_8197F 0x7 -#define BIT_CAMDBG_SEC_TYPE_8197F(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8197F) << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) -#define BITS_CAMDBG_SEC_TYPE_8197F (BIT_MASK_CAMDBG_SEC_TYPE_8197F << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) +#define BIT_CAMDBG_SEC_TYPE_8197F(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8197F) \ + << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) +#define BITS_CAMDBG_SEC_TYPE_8197F \ + (BIT_MASK_CAMDBG_SEC_TYPE_8197F << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) #define BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8197F)) -#define BIT_GET_CAMDBG_SEC_TYPE_8197F(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) & BIT_MASK_CAMDBG_SEC_TYPE_8197F) -#define BIT_SET_CAMDBG_SEC_TYPE_8197F(x, v) (BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) | BIT_CAMDBG_SEC_TYPE_8197F(v)) +#define BIT_GET_CAMDBG_SEC_TYPE_8197F(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) & \ + BIT_MASK_CAMDBG_SEC_TYPE_8197F) +#define BIT_SET_CAMDBG_SEC_TYPE_8197F(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) | BIT_CAMDBG_SEC_TYPE_8197F(v)) #define BIT_CAMDBG_EXT_SEC_TYPE_8197F BIT(11) #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F 5 #define BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F 0x1f -#define BIT_CAMDBG_MIC_KEY_IDX_8197F(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) -#define BITS_CAMDBG_MIC_KEY_IDX_8197F (BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) -#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8197F)) -#define BIT_GET_CAMDBG_MIC_KEY_IDX_8197F(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F) -#define BIT_SET_CAMDBG_MIC_KEY_IDX_8197F(x, v) (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) | BIT_CAMDBG_MIC_KEY_IDX_8197F(v)) - +#define BIT_CAMDBG_MIC_KEY_IDX_8197F(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F) \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) +#define BITS_CAMDBG_MIC_KEY_IDX_8197F \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) \ + ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8197F)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) & \ + BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_8197F(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) | \ + BIT_CAMDBG_MIC_KEY_IDX_8197F(v)) #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F 0 #define BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F 0x1f -#define BIT_CAMDBG_SEC_KEY_IDX_8197F(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) -#define BITS_CAMDBG_SEC_KEY_IDX_8197F (BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) -#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8197F)) -#define BIT_GET_CAMDBG_SEC_KEY_IDX_8197F(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F) -#define BIT_SET_CAMDBG_SEC_KEY_IDX_8197F(x, v) (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) | BIT_CAMDBG_SEC_KEY_IDX_8197F(v)) - +#define BIT_CAMDBG_SEC_KEY_IDX_8197F(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F) \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) +#define BITS_CAMDBG_SEC_KEY_IDX_8197F \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) \ + ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8197F)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) & \ + BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_8197F(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) | \ + BIT_CAMDBG_SEC_KEY_IDX_8197F(v)) /* 2 REG_RXFILTER_ACTION_1_8197F */ #define BIT_SHIFT_RXFILTER_ACTION_1_8197F 0 #define BIT_MASK_RXFILTER_ACTION_1_8197F 0xff -#define BIT_RXFILTER_ACTION_1_8197F(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8197F) << BIT_SHIFT_RXFILTER_ACTION_1_8197F) -#define BITS_RXFILTER_ACTION_1_8197F (BIT_MASK_RXFILTER_ACTION_1_8197F << BIT_SHIFT_RXFILTER_ACTION_1_8197F) -#define BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) ((x) & (~BITS_RXFILTER_ACTION_1_8197F)) -#define BIT_GET_RXFILTER_ACTION_1_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8197F) & BIT_MASK_RXFILTER_ACTION_1_8197F) -#define BIT_SET_RXFILTER_ACTION_1_8197F(x, v) (BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) | BIT_RXFILTER_ACTION_1_8197F(v)) - +#define BIT_RXFILTER_ACTION_1_8197F(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_1_8197F) \ + << BIT_SHIFT_RXFILTER_ACTION_1_8197F) +#define BITS_RXFILTER_ACTION_1_8197F \ + (BIT_MASK_RXFILTER_ACTION_1_8197F << BIT_SHIFT_RXFILTER_ACTION_1_8197F) +#define BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) \ + ((x) & (~BITS_RXFILTER_ACTION_1_8197F)) +#define BIT_GET_RXFILTER_ACTION_1_8197F(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8197F) & \ + BIT_MASK_RXFILTER_ACTION_1_8197F) +#define BIT_SET_RXFILTER_ACTION_1_8197F(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) | BIT_RXFILTER_ACTION_1_8197F(v)) /* 2 REG_RXFILTER_CATEGORY_1_8197F */ #define BIT_SHIFT_RXFILTER_CATEGORY_1_8197F 0 #define BIT_MASK_RXFILTER_CATEGORY_1_8197F 0xff -#define BIT_RXFILTER_CATEGORY_1_8197F(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8197F) << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) -#define BITS_RXFILTER_CATEGORY_1_8197F (BIT_MASK_RXFILTER_CATEGORY_1_8197F << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) -#define BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) ((x) & (~BITS_RXFILTER_CATEGORY_1_8197F)) -#define BIT_GET_RXFILTER_CATEGORY_1_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) & BIT_MASK_RXFILTER_CATEGORY_1_8197F) -#define BIT_SET_RXFILTER_CATEGORY_1_8197F(x, v) (BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) | BIT_RXFILTER_CATEGORY_1_8197F(v)) - +#define BIT_RXFILTER_CATEGORY_1_8197F(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8197F) \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) +#define BITS_RXFILTER_CATEGORY_1_8197F \ + (BIT_MASK_RXFILTER_CATEGORY_1_8197F \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) +#define BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_1_8197F)) +#define BIT_GET_RXFILTER_CATEGORY_1_8197F(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) & \ + BIT_MASK_RXFILTER_CATEGORY_1_8197F) +#define BIT_SET_RXFILTER_CATEGORY_1_8197F(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) | \ + BIT_RXFILTER_CATEGORY_1_8197F(v)) /* 2 REG_SECCFG_8197F (SECURITY CONFIGURATION REGISTER) */ #define BIT_DIS_GCLK_WAPI_8197F BIT(15) @@ -10852,45 +14236,73 @@ #define BIT_SHIFT_RXFILTER_ACTION_3_8197F 0 #define BIT_MASK_RXFILTER_ACTION_3_8197F 0xff -#define BIT_RXFILTER_ACTION_3_8197F(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8197F) << BIT_SHIFT_RXFILTER_ACTION_3_8197F) -#define BITS_RXFILTER_ACTION_3_8197F (BIT_MASK_RXFILTER_ACTION_3_8197F << BIT_SHIFT_RXFILTER_ACTION_3_8197F) -#define BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) ((x) & (~BITS_RXFILTER_ACTION_3_8197F)) -#define BIT_GET_RXFILTER_ACTION_3_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8197F) & BIT_MASK_RXFILTER_ACTION_3_8197F) -#define BIT_SET_RXFILTER_ACTION_3_8197F(x, v) (BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) | BIT_RXFILTER_ACTION_3_8197F(v)) - +#define BIT_RXFILTER_ACTION_3_8197F(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_3_8197F) \ + << BIT_SHIFT_RXFILTER_ACTION_3_8197F) +#define BITS_RXFILTER_ACTION_3_8197F \ + (BIT_MASK_RXFILTER_ACTION_3_8197F << BIT_SHIFT_RXFILTER_ACTION_3_8197F) +#define BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) \ + ((x) & (~BITS_RXFILTER_ACTION_3_8197F)) +#define BIT_GET_RXFILTER_ACTION_3_8197F(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8197F) & \ + BIT_MASK_RXFILTER_ACTION_3_8197F) +#define BIT_SET_RXFILTER_ACTION_3_8197F(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) | BIT_RXFILTER_ACTION_3_8197F(v)) /* 2 REG_RXFILTER_CATEGORY_3_8197F */ #define BIT_SHIFT_RXFILTER_CATEGORY_3_8197F 0 #define BIT_MASK_RXFILTER_CATEGORY_3_8197F 0xff -#define BIT_RXFILTER_CATEGORY_3_8197F(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8197F) << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) -#define BITS_RXFILTER_CATEGORY_3_8197F (BIT_MASK_RXFILTER_CATEGORY_3_8197F << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) -#define BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) ((x) & (~BITS_RXFILTER_CATEGORY_3_8197F)) -#define BIT_GET_RXFILTER_CATEGORY_3_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) & BIT_MASK_RXFILTER_CATEGORY_3_8197F) -#define BIT_SET_RXFILTER_CATEGORY_3_8197F(x, v) (BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) | BIT_RXFILTER_CATEGORY_3_8197F(v)) - +#define BIT_RXFILTER_CATEGORY_3_8197F(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8197F) \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) +#define BITS_RXFILTER_CATEGORY_3_8197F \ + (BIT_MASK_RXFILTER_CATEGORY_3_8197F \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) +#define BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_3_8197F)) +#define BIT_GET_RXFILTER_CATEGORY_3_8197F(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) & \ + BIT_MASK_RXFILTER_CATEGORY_3_8197F) +#define BIT_SET_RXFILTER_CATEGORY_3_8197F(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) | \ + BIT_RXFILTER_CATEGORY_3_8197F(v)) /* 2 REG_RXFILTER_ACTION_2_8197F */ #define BIT_SHIFT_RXFILTER_ACTION_2_8197F 0 #define BIT_MASK_RXFILTER_ACTION_2_8197F 0xff -#define BIT_RXFILTER_ACTION_2_8197F(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8197F) << BIT_SHIFT_RXFILTER_ACTION_2_8197F) -#define BITS_RXFILTER_ACTION_2_8197F (BIT_MASK_RXFILTER_ACTION_2_8197F << BIT_SHIFT_RXFILTER_ACTION_2_8197F) -#define BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) ((x) & (~BITS_RXFILTER_ACTION_2_8197F)) -#define BIT_GET_RXFILTER_ACTION_2_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8197F) & BIT_MASK_RXFILTER_ACTION_2_8197F) -#define BIT_SET_RXFILTER_ACTION_2_8197F(x, v) (BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) | BIT_RXFILTER_ACTION_2_8197F(v)) - +#define BIT_RXFILTER_ACTION_2_8197F(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_2_8197F) \ + << BIT_SHIFT_RXFILTER_ACTION_2_8197F) +#define BITS_RXFILTER_ACTION_2_8197F \ + (BIT_MASK_RXFILTER_ACTION_2_8197F << BIT_SHIFT_RXFILTER_ACTION_2_8197F) +#define BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) \ + ((x) & (~BITS_RXFILTER_ACTION_2_8197F)) +#define BIT_GET_RXFILTER_ACTION_2_8197F(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8197F) & \ + BIT_MASK_RXFILTER_ACTION_2_8197F) +#define BIT_SET_RXFILTER_ACTION_2_8197F(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) | BIT_RXFILTER_ACTION_2_8197F(v)) /* 2 REG_RXFILTER_CATEGORY_2_8197F */ #define BIT_SHIFT_RXFILTER_CATEGORY_2_8197F 0 #define BIT_MASK_RXFILTER_CATEGORY_2_8197F 0xff -#define BIT_RXFILTER_CATEGORY_2_8197F(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8197F) << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) -#define BITS_RXFILTER_CATEGORY_2_8197F (BIT_MASK_RXFILTER_CATEGORY_2_8197F << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) -#define BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) ((x) & (~BITS_RXFILTER_CATEGORY_2_8197F)) -#define BIT_GET_RXFILTER_CATEGORY_2_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) & BIT_MASK_RXFILTER_CATEGORY_2_8197F) -#define BIT_SET_RXFILTER_CATEGORY_2_8197F(x, v) (BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) | BIT_RXFILTER_CATEGORY_2_8197F(v)) - +#define BIT_RXFILTER_CATEGORY_2_8197F(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8197F) \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) +#define BITS_RXFILTER_CATEGORY_2_8197F \ + (BIT_MASK_RXFILTER_CATEGORY_2_8197F \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) +#define BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_2_8197F)) +#define BIT_GET_RXFILTER_CATEGORY_2_8197F(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) & \ + BIT_MASK_RXFILTER_CATEGORY_2_8197F) +#define BIT_SET_RXFILTER_CATEGORY_2_8197F(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) | \ + BIT_RXFILTER_CATEGORY_2_8197F(v)) /* 2 REG_RXFLTMAP4_8197F (RX FILTER MAP GROUP 4) */ #define BIT_CTRLFLT15EN_FW_8197F BIT(15) @@ -10978,11 +14390,20 @@ #define BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F 5 #define BIT_MASK_PORTSEL__PS_RX_INFO_8197F 0x7 -#define BIT_PORTSEL__PS_RX_INFO_8197F(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8197F) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) -#define BITS_PORTSEL__PS_RX_INFO_8197F (BIT_MASK_PORTSEL__PS_RX_INFO_8197F << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) -#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) ((x) & (~BITS_PORTSEL__PS_RX_INFO_8197F)) -#define BIT_GET_PORTSEL__PS_RX_INFO_8197F(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) & BIT_MASK_PORTSEL__PS_RX_INFO_8197F) -#define BIT_SET_PORTSEL__PS_RX_INFO_8197F(x, v) (BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) | BIT_PORTSEL__PS_RX_INFO_8197F(v)) +#define BIT_PORTSEL__PS_RX_INFO_8197F(x) \ + (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8197F) \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) +#define BITS_PORTSEL__PS_RX_INFO_8197F \ + (BIT_MASK_PORTSEL__PS_RX_INFO_8197F \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) \ + ((x) & (~BITS_PORTSEL__PS_RX_INFO_8197F)) +#define BIT_GET_PORTSEL__PS_RX_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) & \ + BIT_MASK_PORTSEL__PS_RX_INFO_8197F) +#define BIT_SET_PORTSEL__PS_RX_INFO_8197F(x, v) \ + (BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) | \ + BIT_PORTSEL__PS_RX_INFO_8197F(v)) #define BIT_RXCTRLIN0_8197F BIT(4) #define BIT_RXMGTIN0_8197F BIT(3) @@ -10999,11 +14420,18 @@ #define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F 6 #define BIT_MASK_PSF_BSSIDSEL_B2B1_8197F 0x3 -#define BIT_PSF_BSSIDSEL_B2B1_8197F(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8197F) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) -#define BITS_PSF_BSSIDSEL_B2B1_8197F (BIT_MASK_PSF_BSSIDSEL_B2B1_8197F << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) -#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8197F)) -#define BIT_GET_PSF_BSSIDSEL_B2B1_8197F(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) & BIT_MASK_PSF_BSSIDSEL_B2B1_8197F) -#define BIT_SET_PSF_BSSIDSEL_B2B1_8197F(x, v) (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) | BIT_PSF_BSSIDSEL_B2B1_8197F(v)) +#define BIT_PSF_BSSIDSEL_B2B1_8197F(x) \ + (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8197F) \ + << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) +#define BITS_PSF_BSSIDSEL_B2B1_8197F \ + (BIT_MASK_PSF_BSSIDSEL_B2B1_8197F << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) \ + ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8197F)) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8197F(x) \ + (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) & \ + BIT_MASK_PSF_BSSIDSEL_B2B1_8197F) +#define BIT_SET_PSF_BSSIDSEL_B2B1_8197F(x, v) \ + (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) | BIT_PSF_BSSIDSEL_B2B1_8197F(v)) #define BIT_WOWHCI_8197F BIT(5) #define BIT_PSF_BSSIDSEL_B0_8197F BIT(4) @@ -11017,21 +14445,27 @@ #define BIT_SHIFT_LPNAV_EARLY_8197F 16 #define BIT_MASK_LPNAV_EARLY_8197F 0x7fff -#define BIT_LPNAV_EARLY_8197F(x) (((x) & BIT_MASK_LPNAV_EARLY_8197F) << BIT_SHIFT_LPNAV_EARLY_8197F) -#define BITS_LPNAV_EARLY_8197F (BIT_MASK_LPNAV_EARLY_8197F << BIT_SHIFT_LPNAV_EARLY_8197F) +#define BIT_LPNAV_EARLY_8197F(x) \ + (((x) & BIT_MASK_LPNAV_EARLY_8197F) << BIT_SHIFT_LPNAV_EARLY_8197F) +#define BITS_LPNAV_EARLY_8197F \ + (BIT_MASK_LPNAV_EARLY_8197F << BIT_SHIFT_LPNAV_EARLY_8197F) #define BIT_CLEAR_LPNAV_EARLY_8197F(x) ((x) & (~BITS_LPNAV_EARLY_8197F)) -#define BIT_GET_LPNAV_EARLY_8197F(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8197F) & BIT_MASK_LPNAV_EARLY_8197F) -#define BIT_SET_LPNAV_EARLY_8197F(x, v) (BIT_CLEAR_LPNAV_EARLY_8197F(x) | BIT_LPNAV_EARLY_8197F(v)) - +#define BIT_GET_LPNAV_EARLY_8197F(x) \ + (((x) >> BIT_SHIFT_LPNAV_EARLY_8197F) & BIT_MASK_LPNAV_EARLY_8197F) +#define BIT_SET_LPNAV_EARLY_8197F(x, v) \ + (BIT_CLEAR_LPNAV_EARLY_8197F(x) | BIT_LPNAV_EARLY_8197F(v)) #define BIT_SHIFT_LPNAV_TH_8197F 0 #define BIT_MASK_LPNAV_TH_8197F 0xffff -#define BIT_LPNAV_TH_8197F(x) (((x) & BIT_MASK_LPNAV_TH_8197F) << BIT_SHIFT_LPNAV_TH_8197F) -#define BITS_LPNAV_TH_8197F (BIT_MASK_LPNAV_TH_8197F << BIT_SHIFT_LPNAV_TH_8197F) +#define BIT_LPNAV_TH_8197F(x) \ + (((x) & BIT_MASK_LPNAV_TH_8197F) << BIT_SHIFT_LPNAV_TH_8197F) +#define BITS_LPNAV_TH_8197F \ + (BIT_MASK_LPNAV_TH_8197F << BIT_SHIFT_LPNAV_TH_8197F) #define BIT_CLEAR_LPNAV_TH_8197F(x) ((x) & (~BITS_LPNAV_TH_8197F)) -#define BIT_GET_LPNAV_TH_8197F(x) (((x) >> BIT_SHIFT_LPNAV_TH_8197F) & BIT_MASK_LPNAV_TH_8197F) -#define BIT_SET_LPNAV_TH_8197F(x, v) (BIT_CLEAR_LPNAV_TH_8197F(x) | BIT_LPNAV_TH_8197F(v)) - +#define BIT_GET_LPNAV_TH_8197F(x) \ + (((x) >> BIT_SHIFT_LPNAV_TH_8197F) & BIT_MASK_LPNAV_TH_8197F) +#define BIT_SET_LPNAV_TH_8197F(x, v) \ + (BIT_CLEAR_LPNAV_TH_8197F(x) | BIT_LPNAV_TH_8197F(v)) /* 2 REG_WKFMCAM_CMD_8197F (WAKEUP FRAME CAM COMMAND REGISTER) */ #define BIT_WKFCAM_POLLING_V1_8197F BIT(31) @@ -11040,32 +14474,46 @@ #define BIT_SHIFT_WKFCAM_ADDR_V2_8197F 8 #define BIT_MASK_WKFCAM_ADDR_V2_8197F 0xff -#define BIT_WKFCAM_ADDR_V2_8197F(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8197F) << BIT_SHIFT_WKFCAM_ADDR_V2_8197F) -#define BITS_WKFCAM_ADDR_V2_8197F (BIT_MASK_WKFCAM_ADDR_V2_8197F << BIT_SHIFT_WKFCAM_ADDR_V2_8197F) +#define BIT_WKFCAM_ADDR_V2_8197F(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR_V2_8197F) \ + << BIT_SHIFT_WKFCAM_ADDR_V2_8197F) +#define BITS_WKFCAM_ADDR_V2_8197F \ + (BIT_MASK_WKFCAM_ADDR_V2_8197F << BIT_SHIFT_WKFCAM_ADDR_V2_8197F) #define BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8197F)) -#define BIT_GET_WKFCAM_ADDR_V2_8197F(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8197F) & BIT_MASK_WKFCAM_ADDR_V2_8197F) -#define BIT_SET_WKFCAM_ADDR_V2_8197F(x, v) (BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) | BIT_WKFCAM_ADDR_V2_8197F(v)) - +#define BIT_GET_WKFCAM_ADDR_V2_8197F(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8197F) & \ + BIT_MASK_WKFCAM_ADDR_V2_8197F) +#define BIT_SET_WKFCAM_ADDR_V2_8197F(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) | BIT_WKFCAM_ADDR_V2_8197F(v)) #define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F 0 #define BIT_MASK_WKFCAM_CAM_NUM_V1_8197F 0xff -#define BIT_WKFCAM_CAM_NUM_V1_8197F(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8197F) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) -#define BITS_WKFCAM_CAM_NUM_V1_8197F (BIT_MASK_WKFCAM_CAM_NUM_V1_8197F << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) -#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8197F)) -#define BIT_GET_WKFCAM_CAM_NUM_V1_8197F(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) & BIT_MASK_WKFCAM_CAM_NUM_V1_8197F) -#define BIT_SET_WKFCAM_CAM_NUM_V1_8197F(x, v) (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) | BIT_WKFCAM_CAM_NUM_V1_8197F(v)) - +#define BIT_WKFCAM_CAM_NUM_V1_8197F(x) \ + (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8197F) \ + << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) +#define BITS_WKFCAM_CAM_NUM_V1_8197F \ + (BIT_MASK_WKFCAM_CAM_NUM_V1_8197F << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) \ + ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8197F)) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8197F(x) \ + (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) & \ + BIT_MASK_WKFCAM_CAM_NUM_V1_8197F) +#define BIT_SET_WKFCAM_CAM_NUM_V1_8197F(x, v) \ + (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) | BIT_WKFCAM_CAM_NUM_V1_8197F(v)) /* 2 REG_WKFMCAM_RWD_8197F (WAKEUP FRAME READ/WRITE DATA) */ #define BIT_SHIFT_WKFMCAM_RWD_8197F 0 #define BIT_MASK_WKFMCAM_RWD_8197F 0xffffffffL -#define BIT_WKFMCAM_RWD_8197F(x) (((x) & BIT_MASK_WKFMCAM_RWD_8197F) << BIT_SHIFT_WKFMCAM_RWD_8197F) -#define BITS_WKFMCAM_RWD_8197F (BIT_MASK_WKFMCAM_RWD_8197F << BIT_SHIFT_WKFMCAM_RWD_8197F) +#define BIT_WKFMCAM_RWD_8197F(x) \ + (((x) & BIT_MASK_WKFMCAM_RWD_8197F) << BIT_SHIFT_WKFMCAM_RWD_8197F) +#define BITS_WKFMCAM_RWD_8197F \ + (BIT_MASK_WKFMCAM_RWD_8197F << BIT_SHIFT_WKFMCAM_RWD_8197F) #define BIT_CLEAR_WKFMCAM_RWD_8197F(x) ((x) & (~BITS_WKFMCAM_RWD_8197F)) -#define BIT_GET_WKFMCAM_RWD_8197F(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8197F) & BIT_MASK_WKFMCAM_RWD_8197F) -#define BIT_SET_WKFMCAM_RWD_8197F(x, v) (BIT_CLEAR_WKFMCAM_RWD_8197F(x) | BIT_WKFMCAM_RWD_8197F(v)) - +#define BIT_GET_WKFMCAM_RWD_8197F(x) \ + (((x) >> BIT_SHIFT_WKFMCAM_RWD_8197F) & BIT_MASK_WKFMCAM_RWD_8197F) +#define BIT_SET_WKFMCAM_RWD_8197F(x, v) \ + (BIT_CLEAR_WKFMCAM_RWD_8197F(x) | BIT_WKFMCAM_RWD_8197F(v)) /* 2 REG_RXFLTMAP1_8197F (RX FILTER MAP GROUP 1) */ #define BIT_CTRLFLT15EN_8197F BIT(15) @@ -11127,32 +14575,42 @@ #define BIT_SHIFT_DTIM_CNT_8197F 24 #define BIT_MASK_DTIM_CNT_8197F 0xff -#define BIT_DTIM_CNT_8197F(x) (((x) & BIT_MASK_DTIM_CNT_8197F) << BIT_SHIFT_DTIM_CNT_8197F) -#define BITS_DTIM_CNT_8197F (BIT_MASK_DTIM_CNT_8197F << BIT_SHIFT_DTIM_CNT_8197F) +#define BIT_DTIM_CNT_8197F(x) \ + (((x) & BIT_MASK_DTIM_CNT_8197F) << BIT_SHIFT_DTIM_CNT_8197F) +#define BITS_DTIM_CNT_8197F \ + (BIT_MASK_DTIM_CNT_8197F << BIT_SHIFT_DTIM_CNT_8197F) #define BIT_CLEAR_DTIM_CNT_8197F(x) ((x) & (~BITS_DTIM_CNT_8197F)) -#define BIT_GET_DTIM_CNT_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT_8197F) & BIT_MASK_DTIM_CNT_8197F) -#define BIT_SET_DTIM_CNT_8197F(x, v) (BIT_CLEAR_DTIM_CNT_8197F(x) | BIT_DTIM_CNT_8197F(v)) - +#define BIT_GET_DTIM_CNT_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT_8197F) & BIT_MASK_DTIM_CNT_8197F) +#define BIT_SET_DTIM_CNT_8197F(x, v) \ + (BIT_CLEAR_DTIM_CNT_8197F(x) | BIT_DTIM_CNT_8197F(v)) #define BIT_SHIFT_DTIM_PERIOD_8197F 16 #define BIT_MASK_DTIM_PERIOD_8197F 0xff -#define BIT_DTIM_PERIOD_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD_8197F) << BIT_SHIFT_DTIM_PERIOD_8197F) -#define BITS_DTIM_PERIOD_8197F (BIT_MASK_DTIM_PERIOD_8197F << BIT_SHIFT_DTIM_PERIOD_8197F) +#define BIT_DTIM_PERIOD_8197F(x) \ + (((x) & BIT_MASK_DTIM_PERIOD_8197F) << BIT_SHIFT_DTIM_PERIOD_8197F) +#define BITS_DTIM_PERIOD_8197F \ + (BIT_MASK_DTIM_PERIOD_8197F << BIT_SHIFT_DTIM_PERIOD_8197F) #define BIT_CLEAR_DTIM_PERIOD_8197F(x) ((x) & (~BITS_DTIM_PERIOD_8197F)) -#define BIT_GET_DTIM_PERIOD_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8197F) & BIT_MASK_DTIM_PERIOD_8197F) -#define BIT_SET_DTIM_PERIOD_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD_8197F(x) | BIT_DTIM_PERIOD_8197F(v)) +#define BIT_GET_DTIM_PERIOD_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD_8197F) & BIT_MASK_DTIM_PERIOD_8197F) +#define BIT_SET_DTIM_PERIOD_8197F(x, v) \ + (BIT_CLEAR_DTIM_PERIOD_8197F(x) | BIT_DTIM_PERIOD_8197F(v)) #define BIT_DTIM_8197F BIT(15) #define BIT_TIM_8197F BIT(14) #define BIT_SHIFT_PS_AID_0_8197F 0 #define BIT_MASK_PS_AID_0_8197F 0x7ff -#define BIT_PS_AID_0_8197F(x) (((x) & BIT_MASK_PS_AID_0_8197F) << BIT_SHIFT_PS_AID_0_8197F) -#define BITS_PS_AID_0_8197F (BIT_MASK_PS_AID_0_8197F << BIT_SHIFT_PS_AID_0_8197F) +#define BIT_PS_AID_0_8197F(x) \ + (((x) & BIT_MASK_PS_AID_0_8197F) << BIT_SHIFT_PS_AID_0_8197F) +#define BITS_PS_AID_0_8197F \ + (BIT_MASK_PS_AID_0_8197F << BIT_SHIFT_PS_AID_0_8197F) #define BIT_CLEAR_PS_AID_0_8197F(x) ((x) & (~BITS_PS_AID_0_8197F)) -#define BIT_GET_PS_AID_0_8197F(x) (((x) >> BIT_SHIFT_PS_AID_0_8197F) & BIT_MASK_PS_AID_0_8197F) -#define BIT_SET_PS_AID_0_8197F(x, v) (BIT_CLEAR_PS_AID_0_8197F(x) | BIT_PS_AID_0_8197F(v)) - +#define BIT_GET_PS_AID_0_8197F(x) \ + (((x) >> BIT_SHIFT_PS_AID_0_8197F) & BIT_MASK_PS_AID_0_8197F) +#define BIT_SET_PS_AID_0_8197F(x, v) \ + (BIT_CLEAR_PS_AID_0_8197F(x) | BIT_PS_AID_0_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_FLC_RPCT_V1_8197F BIT(7) @@ -11160,12 +14618,14 @@ #define BIT_SHIFT_TRPCD_8197F 0 #define BIT_MASK_TRPCD_8197F 0x3f -#define BIT_TRPCD_8197F(x) (((x) & BIT_MASK_TRPCD_8197F) << BIT_SHIFT_TRPCD_8197F) +#define BIT_TRPCD_8197F(x) \ + (((x) & BIT_MASK_TRPCD_8197F) << BIT_SHIFT_TRPCD_8197F) #define BITS_TRPCD_8197F (BIT_MASK_TRPCD_8197F << BIT_SHIFT_TRPCD_8197F) #define BIT_CLEAR_TRPCD_8197F(x) ((x) & (~BITS_TRPCD_8197F)) -#define BIT_GET_TRPCD_8197F(x) (((x) >> BIT_SHIFT_TRPCD_8197F) & BIT_MASK_TRPCD_8197F) -#define BIT_SET_TRPCD_8197F(x, v) (BIT_CLEAR_TRPCD_8197F(x) | BIT_TRPCD_8197F(v)) - +#define BIT_GET_TRPCD_8197F(x) \ + (((x) >> BIT_SHIFT_TRPCD_8197F) & BIT_MASK_TRPCD_8197F) +#define BIT_SET_TRPCD_8197F(x, v) \ + (BIT_CLEAR_TRPCD_8197F(x) | BIT_TRPCD_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_CMF_8197F BIT(2) @@ -11176,60 +14636,78 @@ #define BIT_SHIFT_FLC_RPCT_8197F 0 #define BIT_MASK_FLC_RPCT_8197F 0xff -#define BIT_FLC_RPCT_8197F(x) (((x) & BIT_MASK_FLC_RPCT_8197F) << BIT_SHIFT_FLC_RPCT_8197F) -#define BITS_FLC_RPCT_8197F (BIT_MASK_FLC_RPCT_8197F << BIT_SHIFT_FLC_RPCT_8197F) +#define BIT_FLC_RPCT_8197F(x) \ + (((x) & BIT_MASK_FLC_RPCT_8197F) << BIT_SHIFT_FLC_RPCT_8197F) +#define BITS_FLC_RPCT_8197F \ + (BIT_MASK_FLC_RPCT_8197F << BIT_SHIFT_FLC_RPCT_8197F) #define BIT_CLEAR_FLC_RPCT_8197F(x) ((x) & (~BITS_FLC_RPCT_8197F)) -#define BIT_GET_FLC_RPCT_8197F(x) (((x) >> BIT_SHIFT_FLC_RPCT_8197F) & BIT_MASK_FLC_RPCT_8197F) -#define BIT_SET_FLC_RPCT_8197F(x, v) (BIT_CLEAR_FLC_RPCT_8197F(x) | BIT_FLC_RPCT_8197F(v)) - +#define BIT_GET_FLC_RPCT_8197F(x) \ + (((x) >> BIT_SHIFT_FLC_RPCT_8197F) & BIT_MASK_FLC_RPCT_8197F) +#define BIT_SET_FLC_RPCT_8197F(x, v) \ + (BIT_CLEAR_FLC_RPCT_8197F(x) | BIT_FLC_RPCT_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_SHIFT_FLC_RPC_8197F 0 #define BIT_MASK_FLC_RPC_8197F 0xff -#define BIT_FLC_RPC_8197F(x) (((x) & BIT_MASK_FLC_RPC_8197F) << BIT_SHIFT_FLC_RPC_8197F) +#define BIT_FLC_RPC_8197F(x) \ + (((x) & BIT_MASK_FLC_RPC_8197F) << BIT_SHIFT_FLC_RPC_8197F) #define BITS_FLC_RPC_8197F (BIT_MASK_FLC_RPC_8197F << BIT_SHIFT_FLC_RPC_8197F) #define BIT_CLEAR_FLC_RPC_8197F(x) ((x) & (~BITS_FLC_RPC_8197F)) -#define BIT_GET_FLC_RPC_8197F(x) (((x) >> BIT_SHIFT_FLC_RPC_8197F) & BIT_MASK_FLC_RPC_8197F) -#define BIT_SET_FLC_RPC_8197F(x, v) (BIT_CLEAR_FLC_RPC_8197F(x) | BIT_FLC_RPC_8197F(v)) - +#define BIT_GET_FLC_RPC_8197F(x) \ + (((x) >> BIT_SHIFT_FLC_RPC_8197F) & BIT_MASK_FLC_RPC_8197F) +#define BIT_SET_FLC_RPC_8197F(x, v) \ + (BIT_CLEAR_FLC_RPC_8197F(x) | BIT_FLC_RPC_8197F(v)) /* 2 REG_RXPKTMON_CTRL_8197F */ #define BIT_SHIFT_RXBKQPKT_SEQ_8197F 20 #define BIT_MASK_RXBKQPKT_SEQ_8197F 0xf -#define BIT_RXBKQPKT_SEQ_8197F(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8197F) << BIT_SHIFT_RXBKQPKT_SEQ_8197F) -#define BITS_RXBKQPKT_SEQ_8197F (BIT_MASK_RXBKQPKT_SEQ_8197F << BIT_SHIFT_RXBKQPKT_SEQ_8197F) +#define BIT_RXBKQPKT_SEQ_8197F(x) \ + (((x) & BIT_MASK_RXBKQPKT_SEQ_8197F) << BIT_SHIFT_RXBKQPKT_SEQ_8197F) +#define BITS_RXBKQPKT_SEQ_8197F \ + (BIT_MASK_RXBKQPKT_SEQ_8197F << BIT_SHIFT_RXBKQPKT_SEQ_8197F) #define BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) ((x) & (~BITS_RXBKQPKT_SEQ_8197F)) -#define BIT_GET_RXBKQPKT_SEQ_8197F(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8197F) & BIT_MASK_RXBKQPKT_SEQ_8197F) -#define BIT_SET_RXBKQPKT_SEQ_8197F(x, v) (BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) | BIT_RXBKQPKT_SEQ_8197F(v)) - +#define BIT_GET_RXBKQPKT_SEQ_8197F(x) \ + (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8197F) & BIT_MASK_RXBKQPKT_SEQ_8197F) +#define BIT_SET_RXBKQPKT_SEQ_8197F(x, v) \ + (BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) | BIT_RXBKQPKT_SEQ_8197F(v)) #define BIT_SHIFT_RXBEQPKT_SEQ_8197F 16 #define BIT_MASK_RXBEQPKT_SEQ_8197F 0xf -#define BIT_RXBEQPKT_SEQ_8197F(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8197F) << BIT_SHIFT_RXBEQPKT_SEQ_8197F) -#define BITS_RXBEQPKT_SEQ_8197F (BIT_MASK_RXBEQPKT_SEQ_8197F << BIT_SHIFT_RXBEQPKT_SEQ_8197F) +#define BIT_RXBEQPKT_SEQ_8197F(x) \ + (((x) & BIT_MASK_RXBEQPKT_SEQ_8197F) << BIT_SHIFT_RXBEQPKT_SEQ_8197F) +#define BITS_RXBEQPKT_SEQ_8197F \ + (BIT_MASK_RXBEQPKT_SEQ_8197F << BIT_SHIFT_RXBEQPKT_SEQ_8197F) #define BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) ((x) & (~BITS_RXBEQPKT_SEQ_8197F)) -#define BIT_GET_RXBEQPKT_SEQ_8197F(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8197F) & BIT_MASK_RXBEQPKT_SEQ_8197F) -#define BIT_SET_RXBEQPKT_SEQ_8197F(x, v) (BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) | BIT_RXBEQPKT_SEQ_8197F(v)) - +#define BIT_GET_RXBEQPKT_SEQ_8197F(x) \ + (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8197F) & BIT_MASK_RXBEQPKT_SEQ_8197F) +#define BIT_SET_RXBEQPKT_SEQ_8197F(x, v) \ + (BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) | BIT_RXBEQPKT_SEQ_8197F(v)) #define BIT_SHIFT_RXVIQPKT_SEQ_8197F 12 #define BIT_MASK_RXVIQPKT_SEQ_8197F 0xf -#define BIT_RXVIQPKT_SEQ_8197F(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8197F) << BIT_SHIFT_RXVIQPKT_SEQ_8197F) -#define BITS_RXVIQPKT_SEQ_8197F (BIT_MASK_RXVIQPKT_SEQ_8197F << BIT_SHIFT_RXVIQPKT_SEQ_8197F) +#define BIT_RXVIQPKT_SEQ_8197F(x) \ + (((x) & BIT_MASK_RXVIQPKT_SEQ_8197F) << BIT_SHIFT_RXVIQPKT_SEQ_8197F) +#define BITS_RXVIQPKT_SEQ_8197F \ + (BIT_MASK_RXVIQPKT_SEQ_8197F << BIT_SHIFT_RXVIQPKT_SEQ_8197F) #define BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) ((x) & (~BITS_RXVIQPKT_SEQ_8197F)) -#define BIT_GET_RXVIQPKT_SEQ_8197F(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8197F) & BIT_MASK_RXVIQPKT_SEQ_8197F) -#define BIT_SET_RXVIQPKT_SEQ_8197F(x, v) (BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) | BIT_RXVIQPKT_SEQ_8197F(v)) - +#define BIT_GET_RXVIQPKT_SEQ_8197F(x) \ + (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8197F) & BIT_MASK_RXVIQPKT_SEQ_8197F) +#define BIT_SET_RXVIQPKT_SEQ_8197F(x, v) \ + (BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) | BIT_RXVIQPKT_SEQ_8197F(v)) #define BIT_SHIFT_RXVOQPKT_SEQ_8197F 8 #define BIT_MASK_RXVOQPKT_SEQ_8197F 0xf -#define BIT_RXVOQPKT_SEQ_8197F(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8197F) << BIT_SHIFT_RXVOQPKT_SEQ_8197F) -#define BITS_RXVOQPKT_SEQ_8197F (BIT_MASK_RXVOQPKT_SEQ_8197F << BIT_SHIFT_RXVOQPKT_SEQ_8197F) +#define BIT_RXVOQPKT_SEQ_8197F(x) \ + (((x) & BIT_MASK_RXVOQPKT_SEQ_8197F) << BIT_SHIFT_RXVOQPKT_SEQ_8197F) +#define BITS_RXVOQPKT_SEQ_8197F \ + (BIT_MASK_RXVOQPKT_SEQ_8197F << BIT_SHIFT_RXVOQPKT_SEQ_8197F) #define BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) ((x) & (~BITS_RXVOQPKT_SEQ_8197F)) -#define BIT_GET_RXVOQPKT_SEQ_8197F(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8197F) & BIT_MASK_RXVOQPKT_SEQ_8197F) -#define BIT_SET_RXVOQPKT_SEQ_8197F(x, v) (BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) | BIT_RXVOQPKT_SEQ_8197F(v)) +#define BIT_GET_RXVOQPKT_SEQ_8197F(x) \ + (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8197F) & BIT_MASK_RXVOQPKT_SEQ_8197F) +#define BIT_SET_RXVOQPKT_SEQ_8197F(x, v) \ + (BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) | BIT_RXVOQPKT_SEQ_8197F(v)) #define BIT_RXBKQPKT_ERR_8197F BIT(7) #define BIT_RXBEQPKT_ERR_8197F BIT(6) @@ -11243,31 +14721,41 @@ #define BIT_SHIFT_STATE_SEL_8197F 24 #define BIT_MASK_STATE_SEL_8197F 0x1f -#define BIT_STATE_SEL_8197F(x) (((x) & BIT_MASK_STATE_SEL_8197F) << BIT_SHIFT_STATE_SEL_8197F) -#define BITS_STATE_SEL_8197F (BIT_MASK_STATE_SEL_8197F << BIT_SHIFT_STATE_SEL_8197F) +#define BIT_STATE_SEL_8197F(x) \ + (((x) & BIT_MASK_STATE_SEL_8197F) << BIT_SHIFT_STATE_SEL_8197F) +#define BITS_STATE_SEL_8197F \ + (BIT_MASK_STATE_SEL_8197F << BIT_SHIFT_STATE_SEL_8197F) #define BIT_CLEAR_STATE_SEL_8197F(x) ((x) & (~BITS_STATE_SEL_8197F)) -#define BIT_GET_STATE_SEL_8197F(x) (((x) >> BIT_SHIFT_STATE_SEL_8197F) & BIT_MASK_STATE_SEL_8197F) -#define BIT_SET_STATE_SEL_8197F(x, v) (BIT_CLEAR_STATE_SEL_8197F(x) | BIT_STATE_SEL_8197F(v)) - +#define BIT_GET_STATE_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_STATE_SEL_8197F) & BIT_MASK_STATE_SEL_8197F) +#define BIT_SET_STATE_SEL_8197F(x, v) \ + (BIT_CLEAR_STATE_SEL_8197F(x) | BIT_STATE_SEL_8197F(v)) #define BIT_SHIFT_STATE_INFO_8197F 8 #define BIT_MASK_STATE_INFO_8197F 0xff -#define BIT_STATE_INFO_8197F(x) (((x) & BIT_MASK_STATE_INFO_8197F) << BIT_SHIFT_STATE_INFO_8197F) -#define BITS_STATE_INFO_8197F (BIT_MASK_STATE_INFO_8197F << BIT_SHIFT_STATE_INFO_8197F) +#define BIT_STATE_INFO_8197F(x) \ + (((x) & BIT_MASK_STATE_INFO_8197F) << BIT_SHIFT_STATE_INFO_8197F) +#define BITS_STATE_INFO_8197F \ + (BIT_MASK_STATE_INFO_8197F << BIT_SHIFT_STATE_INFO_8197F) #define BIT_CLEAR_STATE_INFO_8197F(x) ((x) & (~BITS_STATE_INFO_8197F)) -#define BIT_GET_STATE_INFO_8197F(x) (((x) >> BIT_SHIFT_STATE_INFO_8197F) & BIT_MASK_STATE_INFO_8197F) -#define BIT_SET_STATE_INFO_8197F(x, v) (BIT_CLEAR_STATE_INFO_8197F(x) | BIT_STATE_INFO_8197F(v)) +#define BIT_GET_STATE_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_STATE_INFO_8197F) & BIT_MASK_STATE_INFO_8197F) +#define BIT_SET_STATE_INFO_8197F(x, v) \ + (BIT_CLEAR_STATE_INFO_8197F(x) | BIT_STATE_INFO_8197F(v)) #define BIT_UPD_NXT_STATE_8197F BIT(7) #define BIT_SHIFT_CUR_STATE_8197F 0 #define BIT_MASK_CUR_STATE_8197F 0x7f -#define BIT_CUR_STATE_8197F(x) (((x) & BIT_MASK_CUR_STATE_8197F) << BIT_SHIFT_CUR_STATE_8197F) -#define BITS_CUR_STATE_8197F (BIT_MASK_CUR_STATE_8197F << BIT_SHIFT_CUR_STATE_8197F) +#define BIT_CUR_STATE_8197F(x) \ + (((x) & BIT_MASK_CUR_STATE_8197F) << BIT_SHIFT_CUR_STATE_8197F) +#define BITS_CUR_STATE_8197F \ + (BIT_MASK_CUR_STATE_8197F << BIT_SHIFT_CUR_STATE_8197F) #define BIT_CLEAR_CUR_STATE_8197F(x) ((x) & (~BITS_CUR_STATE_8197F)) -#define BIT_GET_CUR_STATE_8197F(x) (((x) >> BIT_SHIFT_CUR_STATE_8197F) & BIT_MASK_CUR_STATE_8197F) -#define BIT_SET_CUR_STATE_8197F(x, v) (BIT_CLEAR_CUR_STATE_8197F(x) | BIT_CUR_STATE_8197F(v)) - +#define BIT_GET_CUR_STATE_8197F(x) \ + (((x) >> BIT_SHIFT_CUR_STATE_8197F) & BIT_MASK_CUR_STATE_8197F) +#define BIT_SET_CUR_STATE_8197F(x, v) \ + (BIT_CLEAR_CUR_STATE_8197F(x) | BIT_CUR_STATE_8197F(v)) /* 2 REG_ERROR_MON_8197F */ #define BIT_MACRX_ERR_1_8197F BIT(17) @@ -11282,23 +14770,36 @@ #define BIT_SHIFT_INFO_INDEX_OFFSET_8197F 16 #define BIT_MASK_INFO_INDEX_OFFSET_8197F 0x1fff -#define BIT_INFO_INDEX_OFFSET_8197F(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8197F) << BIT_SHIFT_INFO_INDEX_OFFSET_8197F) -#define BITS_INFO_INDEX_OFFSET_8197F (BIT_MASK_INFO_INDEX_OFFSET_8197F << BIT_SHIFT_INFO_INDEX_OFFSET_8197F) -#define BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) ((x) & (~BITS_INFO_INDEX_OFFSET_8197F)) -#define BIT_GET_INFO_INDEX_OFFSET_8197F(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8197F) & BIT_MASK_INFO_INDEX_OFFSET_8197F) -#define BIT_SET_INFO_INDEX_OFFSET_8197F(x, v) (BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) | BIT_INFO_INDEX_OFFSET_8197F(v)) +#define BIT_INFO_INDEX_OFFSET_8197F(x) \ + (((x) & BIT_MASK_INFO_INDEX_OFFSET_8197F) \ + << BIT_SHIFT_INFO_INDEX_OFFSET_8197F) +#define BITS_INFO_INDEX_OFFSET_8197F \ + (BIT_MASK_INFO_INDEX_OFFSET_8197F << BIT_SHIFT_INFO_INDEX_OFFSET_8197F) +#define BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) \ + ((x) & (~BITS_INFO_INDEX_OFFSET_8197F)) +#define BIT_GET_INFO_INDEX_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8197F) & \ + BIT_MASK_INFO_INDEX_OFFSET_8197F) +#define BIT_SET_INFO_INDEX_OFFSET_8197F(x, v) \ + (BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) | BIT_INFO_INDEX_OFFSET_8197F(v)) #define BIT_DIS_INFOSRCH_8197F BIT(14) #define BIT_DISABLE_B0_8197F BIT(13) #define BIT_SHIFT_INFO_ADDR_OFFSET_8197F 0 #define BIT_MASK_INFO_ADDR_OFFSET_8197F 0x1fff -#define BIT_INFO_ADDR_OFFSET_8197F(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8197F) << BIT_SHIFT_INFO_ADDR_OFFSET_8197F) -#define BITS_INFO_ADDR_OFFSET_8197F (BIT_MASK_INFO_ADDR_OFFSET_8197F << BIT_SHIFT_INFO_ADDR_OFFSET_8197F) -#define BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) ((x) & (~BITS_INFO_ADDR_OFFSET_8197F)) -#define BIT_GET_INFO_ADDR_OFFSET_8197F(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8197F) & BIT_MASK_INFO_ADDR_OFFSET_8197F) -#define BIT_SET_INFO_ADDR_OFFSET_8197F(x, v) (BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) | BIT_INFO_ADDR_OFFSET_8197F(v)) - +#define BIT_INFO_ADDR_OFFSET_8197F(x) \ + (((x) & BIT_MASK_INFO_ADDR_OFFSET_8197F) \ + << BIT_SHIFT_INFO_ADDR_OFFSET_8197F) +#define BITS_INFO_ADDR_OFFSET_8197F \ + (BIT_MASK_INFO_ADDR_OFFSET_8197F << BIT_SHIFT_INFO_ADDR_OFFSET_8197F) +#define BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) \ + ((x) & (~BITS_INFO_ADDR_OFFSET_8197F)) +#define BIT_GET_INFO_ADDR_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8197F) & \ + BIT_MASK_INFO_ADDR_OFFSET_8197F) +#define BIT_SET_INFO_ADDR_OFFSET_8197F(x, v) \ + (BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) | BIT_INFO_ADDR_OFFSET_8197F(v)) /* 2 REG_BT_COEX_TABLE_8197F (BT-COEXISTENCE CONTROL REGISTER) */ #define BIT_PRI_MASK_RX_RESP_8197F BIT(126) @@ -11307,20 +14808,27 @@ #define BIT_SHIFT_PRI_MASK_TXAC_8197F (117 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_TXAC_8197F 0x7f -#define BIT_PRI_MASK_TXAC_8197F(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8197F) << BIT_SHIFT_PRI_MASK_TXAC_8197F) -#define BITS_PRI_MASK_TXAC_8197F (BIT_MASK_PRI_MASK_TXAC_8197F << BIT_SHIFT_PRI_MASK_TXAC_8197F) +#define BIT_PRI_MASK_TXAC_8197F(x) \ + (((x) & BIT_MASK_PRI_MASK_TXAC_8197F) << BIT_SHIFT_PRI_MASK_TXAC_8197F) +#define BITS_PRI_MASK_TXAC_8197F \ + (BIT_MASK_PRI_MASK_TXAC_8197F << BIT_SHIFT_PRI_MASK_TXAC_8197F) #define BIT_CLEAR_PRI_MASK_TXAC_8197F(x) ((x) & (~BITS_PRI_MASK_TXAC_8197F)) -#define BIT_GET_PRI_MASK_TXAC_8197F(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8197F) & BIT_MASK_PRI_MASK_TXAC_8197F) -#define BIT_SET_PRI_MASK_TXAC_8197F(x, v) (BIT_CLEAR_PRI_MASK_TXAC_8197F(x) | BIT_PRI_MASK_TXAC_8197F(v)) - +#define BIT_GET_PRI_MASK_TXAC_8197F(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8197F) & BIT_MASK_PRI_MASK_TXAC_8197F) +#define BIT_SET_PRI_MASK_TXAC_8197F(x, v) \ + (BIT_CLEAR_PRI_MASK_TXAC_8197F(x) | BIT_PRI_MASK_TXAC_8197F(v)) #define BIT_SHIFT_PRI_MASK_NAV_8197F (109 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_NAV_8197F 0xff -#define BIT_PRI_MASK_NAV_8197F(x) (((x) & BIT_MASK_PRI_MASK_NAV_8197F) << BIT_SHIFT_PRI_MASK_NAV_8197F) -#define BITS_PRI_MASK_NAV_8197F (BIT_MASK_PRI_MASK_NAV_8197F << BIT_SHIFT_PRI_MASK_NAV_8197F) +#define BIT_PRI_MASK_NAV_8197F(x) \ + (((x) & BIT_MASK_PRI_MASK_NAV_8197F) << BIT_SHIFT_PRI_MASK_NAV_8197F) +#define BITS_PRI_MASK_NAV_8197F \ + (BIT_MASK_PRI_MASK_NAV_8197F << BIT_SHIFT_PRI_MASK_NAV_8197F) #define BIT_CLEAR_PRI_MASK_NAV_8197F(x) ((x) & (~BITS_PRI_MASK_NAV_8197F)) -#define BIT_GET_PRI_MASK_NAV_8197F(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8197F) & BIT_MASK_PRI_MASK_NAV_8197F) -#define BIT_SET_PRI_MASK_NAV_8197F(x, v) (BIT_CLEAR_PRI_MASK_NAV_8197F(x) | BIT_PRI_MASK_NAV_8197F(v)) +#define BIT_GET_PRI_MASK_NAV_8197F(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NAV_8197F) & BIT_MASK_PRI_MASK_NAV_8197F) +#define BIT_SET_PRI_MASK_NAV_8197F(x, v) \ + (BIT_CLEAR_PRI_MASK_NAV_8197F(x) | BIT_PRI_MASK_NAV_8197F(v)) #define BIT_PRI_MASK_CCK_8197F BIT(108) #define BIT_PRI_MASK_OFDM_8197F BIT(107) @@ -11328,82 +14836,107 @@ #define BIT_SHIFT_PRI_MASK_NUM_8197F (102 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_NUM_8197F 0xf -#define BIT_PRI_MASK_NUM_8197F(x) (((x) & BIT_MASK_PRI_MASK_NUM_8197F) << BIT_SHIFT_PRI_MASK_NUM_8197F) -#define BITS_PRI_MASK_NUM_8197F (BIT_MASK_PRI_MASK_NUM_8197F << BIT_SHIFT_PRI_MASK_NUM_8197F) +#define BIT_PRI_MASK_NUM_8197F(x) \ + (((x) & BIT_MASK_PRI_MASK_NUM_8197F) << BIT_SHIFT_PRI_MASK_NUM_8197F) +#define BITS_PRI_MASK_NUM_8197F \ + (BIT_MASK_PRI_MASK_NUM_8197F << BIT_SHIFT_PRI_MASK_NUM_8197F) #define BIT_CLEAR_PRI_MASK_NUM_8197F(x) ((x) & (~BITS_PRI_MASK_NUM_8197F)) -#define BIT_GET_PRI_MASK_NUM_8197F(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8197F) & BIT_MASK_PRI_MASK_NUM_8197F) -#define BIT_SET_PRI_MASK_NUM_8197F(x, v) (BIT_CLEAR_PRI_MASK_NUM_8197F(x) | BIT_PRI_MASK_NUM_8197F(v)) - +#define BIT_GET_PRI_MASK_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NUM_8197F) & BIT_MASK_PRI_MASK_NUM_8197F) +#define BIT_SET_PRI_MASK_NUM_8197F(x, v) \ + (BIT_CLEAR_PRI_MASK_NUM_8197F(x) | BIT_PRI_MASK_NUM_8197F(v)) #define BIT_SHIFT_PRI_MASK_TYPE_8197F (98 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_TYPE_8197F 0xf -#define BIT_PRI_MASK_TYPE_8197F(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8197F) << BIT_SHIFT_PRI_MASK_TYPE_8197F) -#define BITS_PRI_MASK_TYPE_8197F (BIT_MASK_PRI_MASK_TYPE_8197F << BIT_SHIFT_PRI_MASK_TYPE_8197F) +#define BIT_PRI_MASK_TYPE_8197F(x) \ + (((x) & BIT_MASK_PRI_MASK_TYPE_8197F) << BIT_SHIFT_PRI_MASK_TYPE_8197F) +#define BITS_PRI_MASK_TYPE_8197F \ + (BIT_MASK_PRI_MASK_TYPE_8197F << BIT_SHIFT_PRI_MASK_TYPE_8197F) #define BIT_CLEAR_PRI_MASK_TYPE_8197F(x) ((x) & (~BITS_PRI_MASK_TYPE_8197F)) -#define BIT_GET_PRI_MASK_TYPE_8197F(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8197F) & BIT_MASK_PRI_MASK_TYPE_8197F) -#define BIT_SET_PRI_MASK_TYPE_8197F(x, v) (BIT_CLEAR_PRI_MASK_TYPE_8197F(x) | BIT_PRI_MASK_TYPE_8197F(v)) +#define BIT_GET_PRI_MASK_TYPE_8197F(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8197F) & BIT_MASK_PRI_MASK_TYPE_8197F) +#define BIT_SET_PRI_MASK_TYPE_8197F(x, v) \ + (BIT_CLEAR_PRI_MASK_TYPE_8197F(x) | BIT_PRI_MASK_TYPE_8197F(v)) #define BIT_OOB_8197F BIT(97) #define BIT_ANT_SEL_8197F BIT(96) #define BIT_SHIFT_BREAK_TABLE_2_8197F (80 & CPU_OPT_WIDTH) #define BIT_MASK_BREAK_TABLE_2_8197F 0xffff -#define BIT_BREAK_TABLE_2_8197F(x) (((x) & BIT_MASK_BREAK_TABLE_2_8197F) << BIT_SHIFT_BREAK_TABLE_2_8197F) -#define BITS_BREAK_TABLE_2_8197F (BIT_MASK_BREAK_TABLE_2_8197F << BIT_SHIFT_BREAK_TABLE_2_8197F) +#define BIT_BREAK_TABLE_2_8197F(x) \ + (((x) & BIT_MASK_BREAK_TABLE_2_8197F) << BIT_SHIFT_BREAK_TABLE_2_8197F) +#define BITS_BREAK_TABLE_2_8197F \ + (BIT_MASK_BREAK_TABLE_2_8197F << BIT_SHIFT_BREAK_TABLE_2_8197F) #define BIT_CLEAR_BREAK_TABLE_2_8197F(x) ((x) & (~BITS_BREAK_TABLE_2_8197F)) -#define BIT_GET_BREAK_TABLE_2_8197F(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8197F) & BIT_MASK_BREAK_TABLE_2_8197F) -#define BIT_SET_BREAK_TABLE_2_8197F(x, v) (BIT_CLEAR_BREAK_TABLE_2_8197F(x) | BIT_BREAK_TABLE_2_8197F(v)) - +#define BIT_GET_BREAK_TABLE_2_8197F(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_2_8197F) & BIT_MASK_BREAK_TABLE_2_8197F) +#define BIT_SET_BREAK_TABLE_2_8197F(x, v) \ + (BIT_CLEAR_BREAK_TABLE_2_8197F(x) | BIT_BREAK_TABLE_2_8197F(v)) #define BIT_SHIFT_BREAK_TABLE_1_8197F (64 & CPU_OPT_WIDTH) #define BIT_MASK_BREAK_TABLE_1_8197F 0xffff -#define BIT_BREAK_TABLE_1_8197F(x) (((x) & BIT_MASK_BREAK_TABLE_1_8197F) << BIT_SHIFT_BREAK_TABLE_1_8197F) -#define BITS_BREAK_TABLE_1_8197F (BIT_MASK_BREAK_TABLE_1_8197F << BIT_SHIFT_BREAK_TABLE_1_8197F) +#define BIT_BREAK_TABLE_1_8197F(x) \ + (((x) & BIT_MASK_BREAK_TABLE_1_8197F) << BIT_SHIFT_BREAK_TABLE_1_8197F) +#define BITS_BREAK_TABLE_1_8197F \ + (BIT_MASK_BREAK_TABLE_1_8197F << BIT_SHIFT_BREAK_TABLE_1_8197F) #define BIT_CLEAR_BREAK_TABLE_1_8197F(x) ((x) & (~BITS_BREAK_TABLE_1_8197F)) -#define BIT_GET_BREAK_TABLE_1_8197F(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8197F) & BIT_MASK_BREAK_TABLE_1_8197F) -#define BIT_SET_BREAK_TABLE_1_8197F(x, v) (BIT_CLEAR_BREAK_TABLE_1_8197F(x) | BIT_BREAK_TABLE_1_8197F(v)) - +#define BIT_GET_BREAK_TABLE_1_8197F(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_1_8197F) & BIT_MASK_BREAK_TABLE_1_8197F) +#define BIT_SET_BREAK_TABLE_1_8197F(x, v) \ + (BIT_CLEAR_BREAK_TABLE_1_8197F(x) | BIT_BREAK_TABLE_1_8197F(v)) #define BIT_SHIFT_COEX_TABLE_2_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_COEX_TABLE_2_8197F 0xffffffffL -#define BIT_COEX_TABLE_2_8197F(x) (((x) & BIT_MASK_COEX_TABLE_2_8197F) << BIT_SHIFT_COEX_TABLE_2_8197F) -#define BITS_COEX_TABLE_2_8197F (BIT_MASK_COEX_TABLE_2_8197F << BIT_SHIFT_COEX_TABLE_2_8197F) +#define BIT_COEX_TABLE_2_8197F(x) \ + (((x) & BIT_MASK_COEX_TABLE_2_8197F) << BIT_SHIFT_COEX_TABLE_2_8197F) +#define BITS_COEX_TABLE_2_8197F \ + (BIT_MASK_COEX_TABLE_2_8197F << BIT_SHIFT_COEX_TABLE_2_8197F) #define BIT_CLEAR_COEX_TABLE_2_8197F(x) ((x) & (~BITS_COEX_TABLE_2_8197F)) -#define BIT_GET_COEX_TABLE_2_8197F(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8197F) & BIT_MASK_COEX_TABLE_2_8197F) -#define BIT_SET_COEX_TABLE_2_8197F(x, v) (BIT_CLEAR_COEX_TABLE_2_8197F(x) | BIT_COEX_TABLE_2_8197F(v)) - +#define BIT_GET_COEX_TABLE_2_8197F(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_2_8197F) & BIT_MASK_COEX_TABLE_2_8197F) +#define BIT_SET_COEX_TABLE_2_8197F(x, v) \ + (BIT_CLEAR_COEX_TABLE_2_8197F(x) | BIT_COEX_TABLE_2_8197F(v)) #define BIT_SHIFT_COEX_TABLE_1_8197F 0 #define BIT_MASK_COEX_TABLE_1_8197F 0xffffffffL -#define BIT_COEX_TABLE_1_8197F(x) (((x) & BIT_MASK_COEX_TABLE_1_8197F) << BIT_SHIFT_COEX_TABLE_1_8197F) -#define BITS_COEX_TABLE_1_8197F (BIT_MASK_COEX_TABLE_1_8197F << BIT_SHIFT_COEX_TABLE_1_8197F) +#define BIT_COEX_TABLE_1_8197F(x) \ + (((x) & BIT_MASK_COEX_TABLE_1_8197F) << BIT_SHIFT_COEX_TABLE_1_8197F) +#define BITS_COEX_TABLE_1_8197F \ + (BIT_MASK_COEX_TABLE_1_8197F << BIT_SHIFT_COEX_TABLE_1_8197F) #define BIT_CLEAR_COEX_TABLE_1_8197F(x) ((x) & (~BITS_COEX_TABLE_1_8197F)) -#define BIT_GET_COEX_TABLE_1_8197F(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8197F) & BIT_MASK_COEX_TABLE_1_8197F) -#define BIT_SET_COEX_TABLE_1_8197F(x, v) (BIT_CLEAR_COEX_TABLE_1_8197F(x) | BIT_COEX_TABLE_1_8197F(v)) - +#define BIT_GET_COEX_TABLE_1_8197F(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_1_8197F) & BIT_MASK_COEX_TABLE_1_8197F) +#define BIT_SET_COEX_TABLE_1_8197F(x, v) \ + (BIT_CLEAR_COEX_TABLE_1_8197F(x) | BIT_COEX_TABLE_1_8197F(v)) /* 2 REG_RXCMD_0_8197F */ #define BIT_RXCMD_EN_8197F BIT(31) #define BIT_SHIFT_RXCMD_INFO_8197F 0 #define BIT_MASK_RXCMD_INFO_8197F 0x7fffffffL -#define BIT_RXCMD_INFO_8197F(x) (((x) & BIT_MASK_RXCMD_INFO_8197F) << BIT_SHIFT_RXCMD_INFO_8197F) -#define BITS_RXCMD_INFO_8197F (BIT_MASK_RXCMD_INFO_8197F << BIT_SHIFT_RXCMD_INFO_8197F) +#define BIT_RXCMD_INFO_8197F(x) \ + (((x) & BIT_MASK_RXCMD_INFO_8197F) << BIT_SHIFT_RXCMD_INFO_8197F) +#define BITS_RXCMD_INFO_8197F \ + (BIT_MASK_RXCMD_INFO_8197F << BIT_SHIFT_RXCMD_INFO_8197F) #define BIT_CLEAR_RXCMD_INFO_8197F(x) ((x) & (~BITS_RXCMD_INFO_8197F)) -#define BIT_GET_RXCMD_INFO_8197F(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8197F) & BIT_MASK_RXCMD_INFO_8197F) -#define BIT_SET_RXCMD_INFO_8197F(x, v) (BIT_CLEAR_RXCMD_INFO_8197F(x) | BIT_RXCMD_INFO_8197F(v)) - +#define BIT_GET_RXCMD_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_RXCMD_INFO_8197F) & BIT_MASK_RXCMD_INFO_8197F) +#define BIT_SET_RXCMD_INFO_8197F(x, v) \ + (BIT_CLEAR_RXCMD_INFO_8197F(x) | BIT_RXCMD_INFO_8197F(v)) /* 2 REG_RXCMD_1_8197F */ #define BIT_SHIFT_RXCMD_PRD_8197F 0 #define BIT_MASK_RXCMD_PRD_8197F 0xffff -#define BIT_RXCMD_PRD_8197F(x) (((x) & BIT_MASK_RXCMD_PRD_8197F) << BIT_SHIFT_RXCMD_PRD_8197F) -#define BITS_RXCMD_PRD_8197F (BIT_MASK_RXCMD_PRD_8197F << BIT_SHIFT_RXCMD_PRD_8197F) +#define BIT_RXCMD_PRD_8197F(x) \ + (((x) & BIT_MASK_RXCMD_PRD_8197F) << BIT_SHIFT_RXCMD_PRD_8197F) +#define BITS_RXCMD_PRD_8197F \ + (BIT_MASK_RXCMD_PRD_8197F << BIT_SHIFT_RXCMD_PRD_8197F) #define BIT_CLEAR_RXCMD_PRD_8197F(x) ((x) & (~BITS_RXCMD_PRD_8197F)) -#define BIT_GET_RXCMD_PRD_8197F(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8197F) & BIT_MASK_RXCMD_PRD_8197F) -#define BIT_SET_RXCMD_PRD_8197F(x, v) (BIT_CLEAR_RXCMD_PRD_8197F(x) | BIT_RXCMD_PRD_8197F(v)) - +#define BIT_GET_RXCMD_PRD_8197F(x) \ + (((x) >> BIT_SHIFT_RXCMD_PRD_8197F) & BIT_MASK_RXCMD_PRD_8197F) +#define BIT_SET_RXCMD_PRD_8197F(x, v) \ + (BIT_CLEAR_RXCMD_PRD_8197F(x) | BIT_RXCMD_PRD_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -11411,48 +14944,74 @@ #define BIT_SHIFT_WMAC_RESP_MFB_8197F 25 #define BIT_MASK_WMAC_RESP_MFB_8197F 0x7f -#define BIT_WMAC_RESP_MFB_8197F(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8197F) << BIT_SHIFT_WMAC_RESP_MFB_8197F) -#define BITS_WMAC_RESP_MFB_8197F (BIT_MASK_WMAC_RESP_MFB_8197F << BIT_SHIFT_WMAC_RESP_MFB_8197F) +#define BIT_WMAC_RESP_MFB_8197F(x) \ + (((x) & BIT_MASK_WMAC_RESP_MFB_8197F) << BIT_SHIFT_WMAC_RESP_MFB_8197F) +#define BITS_WMAC_RESP_MFB_8197F \ + (BIT_MASK_WMAC_RESP_MFB_8197F << BIT_SHIFT_WMAC_RESP_MFB_8197F) #define BIT_CLEAR_WMAC_RESP_MFB_8197F(x) ((x) & (~BITS_WMAC_RESP_MFB_8197F)) -#define BIT_GET_WMAC_RESP_MFB_8197F(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8197F) & BIT_MASK_WMAC_RESP_MFB_8197F) -#define BIT_SET_WMAC_RESP_MFB_8197F(x, v) (BIT_CLEAR_WMAC_RESP_MFB_8197F(x) | BIT_WMAC_RESP_MFB_8197F(v)) - +#define BIT_GET_WMAC_RESP_MFB_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8197F) & BIT_MASK_WMAC_RESP_MFB_8197F) +#define BIT_SET_WMAC_RESP_MFB_8197F(x, v) \ + (BIT_CLEAR_WMAC_RESP_MFB_8197F(x) | BIT_WMAC_RESP_MFB_8197F(v)) #define BIT_SHIFT_WMAC_ANTINF_SEL_8197F 23 #define BIT_MASK_WMAC_ANTINF_SEL_8197F 0x3 -#define BIT_WMAC_ANTINF_SEL_8197F(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8197F) << BIT_SHIFT_WMAC_ANTINF_SEL_8197F) -#define BITS_WMAC_ANTINF_SEL_8197F (BIT_MASK_WMAC_ANTINF_SEL_8197F << BIT_SHIFT_WMAC_ANTINF_SEL_8197F) +#define BIT_WMAC_ANTINF_SEL_8197F(x) \ + (((x) & BIT_MASK_WMAC_ANTINF_SEL_8197F) \ + << BIT_SHIFT_WMAC_ANTINF_SEL_8197F) +#define BITS_WMAC_ANTINF_SEL_8197F \ + (BIT_MASK_WMAC_ANTINF_SEL_8197F << BIT_SHIFT_WMAC_ANTINF_SEL_8197F) #define BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8197F)) -#define BIT_GET_WMAC_ANTINF_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8197F) & BIT_MASK_WMAC_ANTINF_SEL_8197F) -#define BIT_SET_WMAC_ANTINF_SEL_8197F(x, v) (BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) | BIT_WMAC_ANTINF_SEL_8197F(v)) - +#define BIT_GET_WMAC_ANTINF_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8197F) & \ + BIT_MASK_WMAC_ANTINF_SEL_8197F) +#define BIT_SET_WMAC_ANTINF_SEL_8197F(x, v) \ + (BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) | BIT_WMAC_ANTINF_SEL_8197F(v)) #define BIT_SHIFT_WMAC_ANTSEL_SEL_8197F 21 #define BIT_MASK_WMAC_ANTSEL_SEL_8197F 0x3 -#define BIT_WMAC_ANTSEL_SEL_8197F(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8197F) << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) -#define BITS_WMAC_ANTSEL_SEL_8197F (BIT_MASK_WMAC_ANTSEL_SEL_8197F << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) +#define BIT_WMAC_ANTSEL_SEL_8197F(x) \ + (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8197F) \ + << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) +#define BITS_WMAC_ANTSEL_SEL_8197F \ + (BIT_MASK_WMAC_ANTSEL_SEL_8197F << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) #define BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8197F)) -#define BIT_GET_WMAC_ANTSEL_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) & BIT_MASK_WMAC_ANTSEL_SEL_8197F) -#define BIT_SET_WMAC_ANTSEL_SEL_8197F(x, v) (BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) | BIT_WMAC_ANTSEL_SEL_8197F(v)) - +#define BIT_GET_WMAC_ANTSEL_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) & \ + BIT_MASK_WMAC_ANTSEL_SEL_8197F) +#define BIT_SET_WMAC_ANTSEL_SEL_8197F(x, v) \ + (BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) | BIT_WMAC_ANTSEL_SEL_8197F(v)) #define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F 18 #define BIT_MASK_R_WMAC_RESP_TXPOWER_8197F 0x7 -#define BIT_R_WMAC_RESP_TXPOWER_8197F(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8197F) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) -#define BITS_R_WMAC_RESP_TXPOWER_8197F (BIT_MASK_R_WMAC_RESP_TXPOWER_8197F << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) -#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) ((x) & (~BITS_R_WMAC_RESP_TXPOWER_8197F)) -#define BIT_GET_R_WMAC_RESP_TXPOWER_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) & BIT_MASK_R_WMAC_RESP_TXPOWER_8197F) -#define BIT_SET_R_WMAC_RESP_TXPOWER_8197F(x, v) (BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) | BIT_R_WMAC_RESP_TXPOWER_8197F(v)) - +#define BIT_R_WMAC_RESP_TXPOWER_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8197F) \ + << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) +#define BITS_R_WMAC_RESP_TXPOWER_8197F \ + (BIT_MASK_R_WMAC_RESP_TXPOWER_8197F \ + << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) +#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) \ + ((x) & (~BITS_R_WMAC_RESP_TXPOWER_8197F)) +#define BIT_GET_R_WMAC_RESP_TXPOWER_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) & \ + BIT_MASK_R_WMAC_RESP_TXPOWER_8197F) +#define BIT_SET_R_WMAC_RESP_TXPOWER_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) | \ + BIT_R_WMAC_RESP_TXPOWER_8197F(v)) #define BIT_SHIFT_WMAC_RESP_TXANT_8197F 0 #define BIT_MASK_WMAC_RESP_TXANT_8197F 0x3ffff -#define BIT_WMAC_RESP_TXANT_8197F(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8197F) << BIT_SHIFT_WMAC_RESP_TXANT_8197F) -#define BITS_WMAC_RESP_TXANT_8197F (BIT_MASK_WMAC_RESP_TXANT_8197F << BIT_SHIFT_WMAC_RESP_TXANT_8197F) +#define BIT_WMAC_RESP_TXANT_8197F(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT_8197F) \ + << BIT_SHIFT_WMAC_RESP_TXANT_8197F) +#define BITS_WMAC_RESP_TXANT_8197F \ + (BIT_MASK_WMAC_RESP_TXANT_8197F << BIT_SHIFT_WMAC_RESP_TXANT_8197F) #define BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) ((x) & (~BITS_WMAC_RESP_TXANT_8197F)) -#define BIT_GET_WMAC_RESP_TXANT_8197F(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8197F) & BIT_MASK_WMAC_RESP_TXANT_8197F) -#define BIT_SET_WMAC_RESP_TXANT_8197F(x, v) (BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) | BIT_WMAC_RESP_TXANT_8197F(v)) - +#define BIT_GET_WMAC_RESP_TXANT_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8197F) & \ + BIT_MASK_WMAC_RESP_TXANT_8197F) +#define BIT_SET_WMAC_RESP_TXANT_8197F(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) | BIT_WMAC_RESP_TXANT_8197F(v)) /* 2 REG_BBPSF_CTRL_8197F */ #define BIT_CTL_IDLE_CLR_CSI_RPT_8197F BIT(31) @@ -11460,20 +15019,30 @@ #define BIT_SHIFT_WMAC_CSI_RATE_8197F 24 #define BIT_MASK_WMAC_CSI_RATE_8197F 0x3f -#define BIT_WMAC_CSI_RATE_8197F(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8197F) << BIT_SHIFT_WMAC_CSI_RATE_8197F) -#define BITS_WMAC_CSI_RATE_8197F (BIT_MASK_WMAC_CSI_RATE_8197F << BIT_SHIFT_WMAC_CSI_RATE_8197F) +#define BIT_WMAC_CSI_RATE_8197F(x) \ + (((x) & BIT_MASK_WMAC_CSI_RATE_8197F) << BIT_SHIFT_WMAC_CSI_RATE_8197F) +#define BITS_WMAC_CSI_RATE_8197F \ + (BIT_MASK_WMAC_CSI_RATE_8197F << BIT_SHIFT_WMAC_CSI_RATE_8197F) #define BIT_CLEAR_WMAC_CSI_RATE_8197F(x) ((x) & (~BITS_WMAC_CSI_RATE_8197F)) -#define BIT_GET_WMAC_CSI_RATE_8197F(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8197F) & BIT_MASK_WMAC_CSI_RATE_8197F) -#define BIT_SET_WMAC_CSI_RATE_8197F(x, v) (BIT_CLEAR_WMAC_CSI_RATE_8197F(x) | BIT_WMAC_CSI_RATE_8197F(v)) - +#define BIT_GET_WMAC_CSI_RATE_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8197F) & BIT_MASK_WMAC_CSI_RATE_8197F) +#define BIT_SET_WMAC_CSI_RATE_8197F(x, v) \ + (BIT_CLEAR_WMAC_CSI_RATE_8197F(x) | BIT_WMAC_CSI_RATE_8197F(v)) #define BIT_SHIFT_WMAC_RESP_TXRATE_8197F 16 #define BIT_MASK_WMAC_RESP_TXRATE_8197F 0xff -#define BIT_WMAC_RESP_TXRATE_8197F(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8197F) << BIT_SHIFT_WMAC_RESP_TXRATE_8197F) -#define BITS_WMAC_RESP_TXRATE_8197F (BIT_MASK_WMAC_RESP_TXRATE_8197F << BIT_SHIFT_WMAC_RESP_TXRATE_8197F) -#define BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) ((x) & (~BITS_WMAC_RESP_TXRATE_8197F)) -#define BIT_GET_WMAC_RESP_TXRATE_8197F(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8197F) & BIT_MASK_WMAC_RESP_TXRATE_8197F) -#define BIT_SET_WMAC_RESP_TXRATE_8197F(x, v) (BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) | BIT_WMAC_RESP_TXRATE_8197F(v)) +#define BIT_WMAC_RESP_TXRATE_8197F(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXRATE_8197F) \ + << BIT_SHIFT_WMAC_RESP_TXRATE_8197F) +#define BITS_WMAC_RESP_TXRATE_8197F \ + (BIT_MASK_WMAC_RESP_TXRATE_8197F << BIT_SHIFT_WMAC_RESP_TXRATE_8197F) +#define BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) \ + ((x) & (~BITS_WMAC_RESP_TXRATE_8197F)) +#define BIT_GET_WMAC_RESP_TXRATE_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8197F) & \ + BIT_MASK_WMAC_RESP_TXRATE_8197F) +#define BIT_SET_WMAC_RESP_TXRATE_8197F(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) | BIT_WMAC_RESP_TXRATE_8197F(v)) #define BIT_BBPSF_MPDUCHKEN_8197F BIT(5) #define BIT_BBPSF_MHCHKEN_8197F BIT(4) @@ -11481,75 +15050,112 @@ #define BIT_SHIFT_BBPSF_ERRTHR_8197F 0 #define BIT_MASK_BBPSF_ERRTHR_8197F 0x7 -#define BIT_BBPSF_ERRTHR_8197F(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8197F) << BIT_SHIFT_BBPSF_ERRTHR_8197F) -#define BITS_BBPSF_ERRTHR_8197F (BIT_MASK_BBPSF_ERRTHR_8197F << BIT_SHIFT_BBPSF_ERRTHR_8197F) +#define BIT_BBPSF_ERRTHR_8197F(x) \ + (((x) & BIT_MASK_BBPSF_ERRTHR_8197F) << BIT_SHIFT_BBPSF_ERRTHR_8197F) +#define BITS_BBPSF_ERRTHR_8197F \ + (BIT_MASK_BBPSF_ERRTHR_8197F << BIT_SHIFT_BBPSF_ERRTHR_8197F) #define BIT_CLEAR_BBPSF_ERRTHR_8197F(x) ((x) & (~BITS_BBPSF_ERRTHR_8197F)) -#define BIT_GET_BBPSF_ERRTHR_8197F(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8197F) & BIT_MASK_BBPSF_ERRTHR_8197F) -#define BIT_SET_BBPSF_ERRTHR_8197F(x, v) (BIT_CLEAR_BBPSF_ERRTHR_8197F(x) | BIT_BBPSF_ERRTHR_8197F(v)) - +#define BIT_GET_BBPSF_ERRTHR_8197F(x) \ + (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8197F) & BIT_MASK_BBPSF_ERRTHR_8197F) +#define BIT_SET_BBPSF_ERRTHR_8197F(x, v) \ + (BIT_CLEAR_BBPSF_ERRTHR_8197F(x) | BIT_BBPSF_ERRTHR_8197F(v)) /* 2 REG_NOT_VALID_8197F */ /* 2 REG_P2P_RX_BCN_NOA_8197F (P2P RX BEACON NOA REGISTER) */ #define BIT_NOA_PARSER_EN_8197F BIT(15) -#define BIT_SHIFT_BSSID_SEL_8197F 12 -#define BIT_MASK_BSSID_SEL_8197F 0x7 -#define BIT_BSSID_SEL_8197F(x) (((x) & BIT_MASK_BSSID_SEL_8197F) << BIT_SHIFT_BSSID_SEL_8197F) -#define BITS_BSSID_SEL_8197F (BIT_MASK_BSSID_SEL_8197F << BIT_SHIFT_BSSID_SEL_8197F) -#define BIT_CLEAR_BSSID_SEL_8197F(x) ((x) & (~BITS_BSSID_SEL_8197F)) -#define BIT_GET_BSSID_SEL_8197F(x) (((x) >> BIT_SHIFT_BSSID_SEL_8197F) & BIT_MASK_BSSID_SEL_8197F) -#define BIT_SET_BSSID_SEL_8197F(x, v) (BIT_CLEAR_BSSID_SEL_8197F(x) | BIT_BSSID_SEL_8197F(v)) - +#define BIT_SHIFT_BSSID_SEL_V1_8197F 12 +#define BIT_MASK_BSSID_SEL_V1_8197F 0x7 +#define BIT_BSSID_SEL_V1_8197F(x) \ + (((x) & BIT_MASK_BSSID_SEL_V1_8197F) << BIT_SHIFT_BSSID_SEL_V1_8197F) +#define BITS_BSSID_SEL_V1_8197F \ + (BIT_MASK_BSSID_SEL_V1_8197F << BIT_SHIFT_BSSID_SEL_V1_8197F) +#define BIT_CLEAR_BSSID_SEL_V1_8197F(x) ((x) & (~BITS_BSSID_SEL_V1_8197F)) +#define BIT_GET_BSSID_SEL_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BSSID_SEL_V1_8197F) & BIT_MASK_BSSID_SEL_V1_8197F) +#define BIT_SET_BSSID_SEL_V1_8197F(x, v) \ + (BIT_CLEAR_BSSID_SEL_V1_8197F(x) | BIT_BSSID_SEL_V1_8197F(v)) #define BIT_SHIFT_P2P_OUI_TYPE_8197F 0 #define BIT_MASK_P2P_OUI_TYPE_8197F 0xff -#define BIT_P2P_OUI_TYPE_8197F(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8197F) << BIT_SHIFT_P2P_OUI_TYPE_8197F) -#define BITS_P2P_OUI_TYPE_8197F (BIT_MASK_P2P_OUI_TYPE_8197F << BIT_SHIFT_P2P_OUI_TYPE_8197F) +#define BIT_P2P_OUI_TYPE_8197F(x) \ + (((x) & BIT_MASK_P2P_OUI_TYPE_8197F) << BIT_SHIFT_P2P_OUI_TYPE_8197F) +#define BITS_P2P_OUI_TYPE_8197F \ + (BIT_MASK_P2P_OUI_TYPE_8197F << BIT_SHIFT_P2P_OUI_TYPE_8197F) #define BIT_CLEAR_P2P_OUI_TYPE_8197F(x) ((x) & (~BITS_P2P_OUI_TYPE_8197F)) -#define BIT_GET_P2P_OUI_TYPE_8197F(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8197F) & BIT_MASK_P2P_OUI_TYPE_8197F) -#define BIT_SET_P2P_OUI_TYPE_8197F(x, v) (BIT_CLEAR_P2P_OUI_TYPE_8197F(x) | BIT_P2P_OUI_TYPE_8197F(v)) - +#define BIT_GET_P2P_OUI_TYPE_8197F(x) \ + (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8197F) & BIT_MASK_P2P_OUI_TYPE_8197F) +#define BIT_SET_P2P_OUI_TYPE_8197F(x, v) \ + (BIT_CLEAR_P2P_OUI_TYPE_8197F(x) | BIT_P2P_OUI_TYPE_8197F(v)) /* 2 REG_ASSOCIATED_BFMER0_INFO_8197F (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ #define BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F (48 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_TXCSI_AID0_8197F 0x1ff -#define BIT_R_WMAC_TXCSI_AID0_8197F(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8197F) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) -#define BITS_R_WMAC_TXCSI_AID0_8197F (BIT_MASK_R_WMAC_TXCSI_AID0_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) -#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) ((x) & (~BITS_R_WMAC_TXCSI_AID0_8197F)) -#define BIT_GET_R_WMAC_TXCSI_AID0_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) & BIT_MASK_R_WMAC_TXCSI_AID0_8197F) -#define BIT_SET_R_WMAC_TXCSI_AID0_8197F(x, v) (BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) | BIT_R_WMAC_TXCSI_AID0_8197F(v)) - +#define BIT_R_WMAC_TXCSI_AID0_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8197F) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) +#define BITS_R_WMAC_TXCSI_AID0_8197F \ + (BIT_MASK_R_WMAC_TXCSI_AID0_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) +#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID0_8197F)) +#define BIT_GET_R_WMAC_TXCSI_AID0_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) & \ + BIT_MASK_R_WMAC_TXCSI_AID0_8197F) +#define BIT_SET_R_WMAC_TXCSI_AID0_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) | BIT_R_WMAC_TXCSI_AID0_8197F(v)) #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) -#define BITS_R_WMAC_SOUNDING_RXADD_R0_8197F (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) -#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8197F)) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F) -#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8197F(x, v) (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) | BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(v)) - +#define BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_8197F \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8197F)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(v)) /* 2 REG_ASSOCIATED_BFMER1_INFO_8197F (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ #define BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F (48 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_TXCSI_AID1_8197F 0x1ff -#define BIT_R_WMAC_TXCSI_AID1_8197F(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8197F) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) -#define BITS_R_WMAC_TXCSI_AID1_8197F (BIT_MASK_R_WMAC_TXCSI_AID1_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) -#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) ((x) & (~BITS_R_WMAC_TXCSI_AID1_8197F)) -#define BIT_GET_R_WMAC_TXCSI_AID1_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) & BIT_MASK_R_WMAC_TXCSI_AID1_8197F) -#define BIT_SET_R_WMAC_TXCSI_AID1_8197F(x, v) (BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) | BIT_R_WMAC_TXCSI_AID1_8197F(v)) - +#define BIT_R_WMAC_TXCSI_AID1_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8197F) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) +#define BITS_R_WMAC_TXCSI_AID1_8197F \ + (BIT_MASK_R_WMAC_TXCSI_AID1_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) +#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID1_8197F)) +#define BIT_GET_R_WMAC_TXCSI_AID1_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) & \ + BIT_MASK_R_WMAC_TXCSI_AID1_8197F) +#define BIT_SET_R_WMAC_TXCSI_AID1_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) | BIT_R_WMAC_TXCSI_AID1_8197F(v)) #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) -#define BITS_R_WMAC_SOUNDING_RXADD_R1_8197F (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) -#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8197F)) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F) -#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8197F(x, v) (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) | BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(v)) - +#define BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_8197F \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8197F)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -11565,32 +15171,53 @@ #define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F 16 #define BIT_MASK_R_WMAC_BFINFO_20M_1_8197F 0xfff -#define BIT_R_WMAC_BFINFO_20M_1_8197F(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8197F) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) -#define BITS_R_WMAC_BFINFO_20M_1_8197F (BIT_MASK_R_WMAC_BFINFO_20M_1_8197F << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) -#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8197F)) -#define BIT_GET_R_WMAC_BFINFO_20M_1_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) & BIT_MASK_R_WMAC_BFINFO_20M_1_8197F) -#define BIT_SET_R_WMAC_BFINFO_20M_1_8197F(x, v) (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) | BIT_R_WMAC_BFINFO_20M_1_8197F(v)) - +#define BIT_R_WMAC_BFINFO_20M_1_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8197F) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) +#define BITS_R_WMAC_BFINFO_20M_1_8197F \ + (BIT_MASK_R_WMAC_BFINFO_20M_1_8197F \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8197F)) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) & \ + BIT_MASK_R_WMAC_BFINFO_20M_1_8197F) +#define BIT_SET_R_WMAC_BFINFO_20M_1_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) | \ + BIT_R_WMAC_BFINFO_20M_1_8197F(v)) #define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F 0 #define BIT_MASK_R_WMAC_BFINFO_20M_0_8197F 0xfff -#define BIT_R_WMAC_BFINFO_20M_0_8197F(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8197F) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) -#define BITS_R_WMAC_BFINFO_20M_0_8197F (BIT_MASK_R_WMAC_BFINFO_20M_0_8197F << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) -#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8197F)) -#define BIT_GET_R_WMAC_BFINFO_20M_0_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) & BIT_MASK_R_WMAC_BFINFO_20M_0_8197F) -#define BIT_SET_R_WMAC_BFINFO_20M_0_8197F(x, v) (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) | BIT_R_WMAC_BFINFO_20M_0_8197F(v)) - +#define BIT_R_WMAC_BFINFO_20M_0_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8197F) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) +#define BITS_R_WMAC_BFINFO_20M_0_8197F \ + (BIT_MASK_R_WMAC_BFINFO_20M_0_8197F \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8197F)) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) & \ + BIT_MASK_R_WMAC_BFINFO_20M_0_8197F) +#define BIT_SET_R_WMAC_BFINFO_20M_0_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) | \ + BIT_R_WMAC_BFINFO_20M_0_8197F(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW40_8197F (TX CSI REPORT PARAMETER_BW40 REGISTER) */ #define BIT_SHIFT_WMAC_RESP_ANTCD_8197F 0 #define BIT_MASK_WMAC_RESP_ANTCD_8197F 0xf -#define BIT_WMAC_RESP_ANTCD_8197F(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8197F) << BIT_SHIFT_WMAC_RESP_ANTCD_8197F) -#define BITS_WMAC_RESP_ANTCD_8197F (BIT_MASK_WMAC_RESP_ANTCD_8197F << BIT_SHIFT_WMAC_RESP_ANTCD_8197F) +#define BIT_WMAC_RESP_ANTCD_8197F(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTCD_8197F) \ + << BIT_SHIFT_WMAC_RESP_ANTCD_8197F) +#define BITS_WMAC_RESP_ANTCD_8197F \ + (BIT_MASK_WMAC_RESP_ANTCD_8197F << BIT_SHIFT_WMAC_RESP_ANTCD_8197F) #define BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8197F)) -#define BIT_GET_WMAC_RESP_ANTCD_8197F(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8197F) & BIT_MASK_WMAC_RESP_ANTCD_8197F) -#define BIT_SET_WMAC_RESP_ANTCD_8197F(x, v) (BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) | BIT_WMAC_RESP_ANTCD_8197F(v)) - +#define BIT_GET_WMAC_RESP_ANTCD_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8197F) & \ + BIT_MASK_WMAC_RESP_ANTCD_8197F) +#define BIT_SET_WMAC_RESP_ANTCD_8197F(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) | BIT_WMAC_RESP_ANTCD_8197F(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW80_8197F (TX CSI REPORT PARAMETER_BW80 REGISTER) */ @@ -11598,171 +15225,216 @@ #define BIT_SHIFT_DTIM_CNT2_8197F 24 #define BIT_MASK_DTIM_CNT2_8197F 0xff -#define BIT_DTIM_CNT2_8197F(x) (((x) & BIT_MASK_DTIM_CNT2_8197F) << BIT_SHIFT_DTIM_CNT2_8197F) -#define BITS_DTIM_CNT2_8197F (BIT_MASK_DTIM_CNT2_8197F << BIT_SHIFT_DTIM_CNT2_8197F) +#define BIT_DTIM_CNT2_8197F(x) \ + (((x) & BIT_MASK_DTIM_CNT2_8197F) << BIT_SHIFT_DTIM_CNT2_8197F) +#define BITS_DTIM_CNT2_8197F \ + (BIT_MASK_DTIM_CNT2_8197F << BIT_SHIFT_DTIM_CNT2_8197F) #define BIT_CLEAR_DTIM_CNT2_8197F(x) ((x) & (~BITS_DTIM_CNT2_8197F)) -#define BIT_GET_DTIM_CNT2_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8197F) & BIT_MASK_DTIM_CNT2_8197F) -#define BIT_SET_DTIM_CNT2_8197F(x, v) (BIT_CLEAR_DTIM_CNT2_8197F(x) | BIT_DTIM_CNT2_8197F(v)) - +#define BIT_GET_DTIM_CNT2_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT2_8197F) & BIT_MASK_DTIM_CNT2_8197F) +#define BIT_SET_DTIM_CNT2_8197F(x, v) \ + (BIT_CLEAR_DTIM_CNT2_8197F(x) | BIT_DTIM_CNT2_8197F(v)) #define BIT_SHIFT_DTIM_PERIOD2_8197F 16 #define BIT_MASK_DTIM_PERIOD2_8197F 0xff -#define BIT_DTIM_PERIOD2_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD2_8197F) << BIT_SHIFT_DTIM_PERIOD2_8197F) -#define BITS_DTIM_PERIOD2_8197F (BIT_MASK_DTIM_PERIOD2_8197F << BIT_SHIFT_DTIM_PERIOD2_8197F) +#define BIT_DTIM_PERIOD2_8197F(x) \ + (((x) & BIT_MASK_DTIM_PERIOD2_8197F) << BIT_SHIFT_DTIM_PERIOD2_8197F) +#define BITS_DTIM_PERIOD2_8197F \ + (BIT_MASK_DTIM_PERIOD2_8197F << BIT_SHIFT_DTIM_PERIOD2_8197F) #define BIT_CLEAR_DTIM_PERIOD2_8197F(x) ((x) & (~BITS_DTIM_PERIOD2_8197F)) -#define BIT_GET_DTIM_PERIOD2_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8197F) & BIT_MASK_DTIM_PERIOD2_8197F) -#define BIT_SET_DTIM_PERIOD2_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD2_8197F(x) | BIT_DTIM_PERIOD2_8197F(v)) +#define BIT_GET_DTIM_PERIOD2_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD2_8197F) & BIT_MASK_DTIM_PERIOD2_8197F) +#define BIT_SET_DTIM_PERIOD2_8197F(x, v) \ + (BIT_CLEAR_DTIM_PERIOD2_8197F(x) | BIT_DTIM_PERIOD2_8197F(v)) #define BIT_DTIM2_8197F BIT(15) #define BIT_TIM2_8197F BIT(14) #define BIT_SHIFT_PS_AID_2_8197F 0 #define BIT_MASK_PS_AID_2_8197F 0x7ff -#define BIT_PS_AID_2_8197F(x) (((x) & BIT_MASK_PS_AID_2_8197F) << BIT_SHIFT_PS_AID_2_8197F) -#define BITS_PS_AID_2_8197F (BIT_MASK_PS_AID_2_8197F << BIT_SHIFT_PS_AID_2_8197F) +#define BIT_PS_AID_2_8197F(x) \ + (((x) & BIT_MASK_PS_AID_2_8197F) << BIT_SHIFT_PS_AID_2_8197F) +#define BITS_PS_AID_2_8197F \ + (BIT_MASK_PS_AID_2_8197F << BIT_SHIFT_PS_AID_2_8197F) #define BIT_CLEAR_PS_AID_2_8197F(x) ((x) & (~BITS_PS_AID_2_8197F)) -#define BIT_GET_PS_AID_2_8197F(x) (((x) >> BIT_SHIFT_PS_AID_2_8197F) & BIT_MASK_PS_AID_2_8197F) -#define BIT_SET_PS_AID_2_8197F(x, v) (BIT_CLEAR_PS_AID_2_8197F(x) | BIT_PS_AID_2_8197F(v)) - +#define BIT_GET_PS_AID_2_8197F(x) \ + (((x) >> BIT_SHIFT_PS_AID_2_8197F) & BIT_MASK_PS_AID_2_8197F) +#define BIT_SET_PS_AID_2_8197F(x, v) \ + (BIT_CLEAR_PS_AID_2_8197F(x) | BIT_PS_AID_2_8197F(v)) /* 2 REG_BCN_PSR_RPT3_8197F (BEACON PARSER REPORT REGISTER3) */ #define BIT_SHIFT_DTIM_CNT3_8197F 24 #define BIT_MASK_DTIM_CNT3_8197F 0xff -#define BIT_DTIM_CNT3_8197F(x) (((x) & BIT_MASK_DTIM_CNT3_8197F) << BIT_SHIFT_DTIM_CNT3_8197F) -#define BITS_DTIM_CNT3_8197F (BIT_MASK_DTIM_CNT3_8197F << BIT_SHIFT_DTIM_CNT3_8197F) +#define BIT_DTIM_CNT3_8197F(x) \ + (((x) & BIT_MASK_DTIM_CNT3_8197F) << BIT_SHIFT_DTIM_CNT3_8197F) +#define BITS_DTIM_CNT3_8197F \ + (BIT_MASK_DTIM_CNT3_8197F << BIT_SHIFT_DTIM_CNT3_8197F) #define BIT_CLEAR_DTIM_CNT3_8197F(x) ((x) & (~BITS_DTIM_CNT3_8197F)) -#define BIT_GET_DTIM_CNT3_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8197F) & BIT_MASK_DTIM_CNT3_8197F) -#define BIT_SET_DTIM_CNT3_8197F(x, v) (BIT_CLEAR_DTIM_CNT3_8197F(x) | BIT_DTIM_CNT3_8197F(v)) - +#define BIT_GET_DTIM_CNT3_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT3_8197F) & BIT_MASK_DTIM_CNT3_8197F) +#define BIT_SET_DTIM_CNT3_8197F(x, v) \ + (BIT_CLEAR_DTIM_CNT3_8197F(x) | BIT_DTIM_CNT3_8197F(v)) #define BIT_SHIFT_DTIM_PERIOD3_8197F 16 #define BIT_MASK_DTIM_PERIOD3_8197F 0xff -#define BIT_DTIM_PERIOD3_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD3_8197F) << BIT_SHIFT_DTIM_PERIOD3_8197F) -#define BITS_DTIM_PERIOD3_8197F (BIT_MASK_DTIM_PERIOD3_8197F << BIT_SHIFT_DTIM_PERIOD3_8197F) +#define BIT_DTIM_PERIOD3_8197F(x) \ + (((x) & BIT_MASK_DTIM_PERIOD3_8197F) << BIT_SHIFT_DTIM_PERIOD3_8197F) +#define BITS_DTIM_PERIOD3_8197F \ + (BIT_MASK_DTIM_PERIOD3_8197F << BIT_SHIFT_DTIM_PERIOD3_8197F) #define BIT_CLEAR_DTIM_PERIOD3_8197F(x) ((x) & (~BITS_DTIM_PERIOD3_8197F)) -#define BIT_GET_DTIM_PERIOD3_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8197F) & BIT_MASK_DTIM_PERIOD3_8197F) -#define BIT_SET_DTIM_PERIOD3_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD3_8197F(x) | BIT_DTIM_PERIOD3_8197F(v)) +#define BIT_GET_DTIM_PERIOD3_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD3_8197F) & BIT_MASK_DTIM_PERIOD3_8197F) +#define BIT_SET_DTIM_PERIOD3_8197F(x, v) \ + (BIT_CLEAR_DTIM_PERIOD3_8197F(x) | BIT_DTIM_PERIOD3_8197F(v)) #define BIT_DTIM3_8197F BIT(15) #define BIT_TIM3_8197F BIT(14) #define BIT_SHIFT_PS_AID_3_8197F 0 #define BIT_MASK_PS_AID_3_8197F 0x7ff -#define BIT_PS_AID_3_8197F(x) (((x) & BIT_MASK_PS_AID_3_8197F) << BIT_SHIFT_PS_AID_3_8197F) -#define BITS_PS_AID_3_8197F (BIT_MASK_PS_AID_3_8197F << BIT_SHIFT_PS_AID_3_8197F) +#define BIT_PS_AID_3_8197F(x) \ + (((x) & BIT_MASK_PS_AID_3_8197F) << BIT_SHIFT_PS_AID_3_8197F) +#define BITS_PS_AID_3_8197F \ + (BIT_MASK_PS_AID_3_8197F << BIT_SHIFT_PS_AID_3_8197F) #define BIT_CLEAR_PS_AID_3_8197F(x) ((x) & (~BITS_PS_AID_3_8197F)) -#define BIT_GET_PS_AID_3_8197F(x) (((x) >> BIT_SHIFT_PS_AID_3_8197F) & BIT_MASK_PS_AID_3_8197F) -#define BIT_SET_PS_AID_3_8197F(x, v) (BIT_CLEAR_PS_AID_3_8197F(x) | BIT_PS_AID_3_8197F(v)) - +#define BIT_GET_PS_AID_3_8197F(x) \ + (((x) >> BIT_SHIFT_PS_AID_3_8197F) & BIT_MASK_PS_AID_3_8197F) +#define BIT_SET_PS_AID_3_8197F(x, v) \ + (BIT_CLEAR_PS_AID_3_8197F(x) | BIT_PS_AID_3_8197F(v)) /* 2 REG_BCN_PSR_RPT4_8197F (BEACON PARSER REPORT REGISTER4) */ #define BIT_SHIFT_DTIM_CNT4_8197F 24 #define BIT_MASK_DTIM_CNT4_8197F 0xff -#define BIT_DTIM_CNT4_8197F(x) (((x) & BIT_MASK_DTIM_CNT4_8197F) << BIT_SHIFT_DTIM_CNT4_8197F) -#define BITS_DTIM_CNT4_8197F (BIT_MASK_DTIM_CNT4_8197F << BIT_SHIFT_DTIM_CNT4_8197F) +#define BIT_DTIM_CNT4_8197F(x) \ + (((x) & BIT_MASK_DTIM_CNT4_8197F) << BIT_SHIFT_DTIM_CNT4_8197F) +#define BITS_DTIM_CNT4_8197F \ + (BIT_MASK_DTIM_CNT4_8197F << BIT_SHIFT_DTIM_CNT4_8197F) #define BIT_CLEAR_DTIM_CNT4_8197F(x) ((x) & (~BITS_DTIM_CNT4_8197F)) -#define BIT_GET_DTIM_CNT4_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8197F) & BIT_MASK_DTIM_CNT4_8197F) -#define BIT_SET_DTIM_CNT4_8197F(x, v) (BIT_CLEAR_DTIM_CNT4_8197F(x) | BIT_DTIM_CNT4_8197F(v)) - +#define BIT_GET_DTIM_CNT4_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT4_8197F) & BIT_MASK_DTIM_CNT4_8197F) +#define BIT_SET_DTIM_CNT4_8197F(x, v) \ + (BIT_CLEAR_DTIM_CNT4_8197F(x) | BIT_DTIM_CNT4_8197F(v)) #define BIT_SHIFT_DTIM_PERIOD4_8197F 16 #define BIT_MASK_DTIM_PERIOD4_8197F 0xff -#define BIT_DTIM_PERIOD4_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD4_8197F) << BIT_SHIFT_DTIM_PERIOD4_8197F) -#define BITS_DTIM_PERIOD4_8197F (BIT_MASK_DTIM_PERIOD4_8197F << BIT_SHIFT_DTIM_PERIOD4_8197F) +#define BIT_DTIM_PERIOD4_8197F(x) \ + (((x) & BIT_MASK_DTIM_PERIOD4_8197F) << BIT_SHIFT_DTIM_PERIOD4_8197F) +#define BITS_DTIM_PERIOD4_8197F \ + (BIT_MASK_DTIM_PERIOD4_8197F << BIT_SHIFT_DTIM_PERIOD4_8197F) #define BIT_CLEAR_DTIM_PERIOD4_8197F(x) ((x) & (~BITS_DTIM_PERIOD4_8197F)) -#define BIT_GET_DTIM_PERIOD4_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8197F) & BIT_MASK_DTIM_PERIOD4_8197F) -#define BIT_SET_DTIM_PERIOD4_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD4_8197F(x) | BIT_DTIM_PERIOD4_8197F(v)) +#define BIT_GET_DTIM_PERIOD4_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD4_8197F) & BIT_MASK_DTIM_PERIOD4_8197F) +#define BIT_SET_DTIM_PERIOD4_8197F(x, v) \ + (BIT_CLEAR_DTIM_PERIOD4_8197F(x) | BIT_DTIM_PERIOD4_8197F(v)) #define BIT_DTIM4_8197F BIT(15) #define BIT_TIM4_8197F BIT(14) #define BIT_SHIFT_PS_AID_4_8197F 0 #define BIT_MASK_PS_AID_4_8197F 0x7ff -#define BIT_PS_AID_4_8197F(x) (((x) & BIT_MASK_PS_AID_4_8197F) << BIT_SHIFT_PS_AID_4_8197F) -#define BITS_PS_AID_4_8197F (BIT_MASK_PS_AID_4_8197F << BIT_SHIFT_PS_AID_4_8197F) +#define BIT_PS_AID_4_8197F(x) \ + (((x) & BIT_MASK_PS_AID_4_8197F) << BIT_SHIFT_PS_AID_4_8197F) +#define BITS_PS_AID_4_8197F \ + (BIT_MASK_PS_AID_4_8197F << BIT_SHIFT_PS_AID_4_8197F) #define BIT_CLEAR_PS_AID_4_8197F(x) ((x) & (~BITS_PS_AID_4_8197F)) -#define BIT_GET_PS_AID_4_8197F(x) (((x) >> BIT_SHIFT_PS_AID_4_8197F) & BIT_MASK_PS_AID_4_8197F) -#define BIT_SET_PS_AID_4_8197F(x, v) (BIT_CLEAR_PS_AID_4_8197F(x) | BIT_PS_AID_4_8197F(v)) - +#define BIT_GET_PS_AID_4_8197F(x) \ + (((x) >> BIT_SHIFT_PS_AID_4_8197F) & BIT_MASK_PS_AID_4_8197F) +#define BIT_SET_PS_AID_4_8197F(x, v) \ + (BIT_CLEAR_PS_AID_4_8197F(x) | BIT_PS_AID_4_8197F(v)) /* 2 REG_A1_ADDR_MASK_8197F (A1 ADDR MASK REGISTER) */ #define BIT_SHIFT_A1_ADDR_MASK_8197F 0 #define BIT_MASK_A1_ADDR_MASK_8197F 0xffffffffL -#define BIT_A1_ADDR_MASK_8197F(x) (((x) & BIT_MASK_A1_ADDR_MASK_8197F) << BIT_SHIFT_A1_ADDR_MASK_8197F) -#define BITS_A1_ADDR_MASK_8197F (BIT_MASK_A1_ADDR_MASK_8197F << BIT_SHIFT_A1_ADDR_MASK_8197F) +#define BIT_A1_ADDR_MASK_8197F(x) \ + (((x) & BIT_MASK_A1_ADDR_MASK_8197F) << BIT_SHIFT_A1_ADDR_MASK_8197F) +#define BITS_A1_ADDR_MASK_8197F \ + (BIT_MASK_A1_ADDR_MASK_8197F << BIT_SHIFT_A1_ADDR_MASK_8197F) #define BIT_CLEAR_A1_ADDR_MASK_8197F(x) ((x) & (~BITS_A1_ADDR_MASK_8197F)) -#define BIT_GET_A1_ADDR_MASK_8197F(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8197F) & BIT_MASK_A1_ADDR_MASK_8197F) -#define BIT_SET_A1_ADDR_MASK_8197F(x, v) (BIT_CLEAR_A1_ADDR_MASK_8197F(x) | BIT_A1_ADDR_MASK_8197F(v)) - +#define BIT_GET_A1_ADDR_MASK_8197F(x) \ + (((x) >> BIT_SHIFT_A1_ADDR_MASK_8197F) & BIT_MASK_A1_ADDR_MASK_8197F) +#define BIT_SET_A1_ADDR_MASK_8197F(x, v) \ + (BIT_CLEAR_A1_ADDR_MASK_8197F(x) | BIT_A1_ADDR_MASK_8197F(v)) /* 2 REG_MACID2_8197F (MAC ID2 REGISTER) */ #define BIT_SHIFT_MACID2_8197F 0 #define BIT_MASK_MACID2_8197F 0xffffffffffffL -#define BIT_MACID2_8197F(x) (((x) & BIT_MASK_MACID2_8197F) << BIT_SHIFT_MACID2_8197F) +#define BIT_MACID2_8197F(x) \ + (((x) & BIT_MASK_MACID2_8197F) << BIT_SHIFT_MACID2_8197F) #define BITS_MACID2_8197F (BIT_MASK_MACID2_8197F << BIT_SHIFT_MACID2_8197F) #define BIT_CLEAR_MACID2_8197F(x) ((x) & (~BITS_MACID2_8197F)) -#define BIT_GET_MACID2_8197F(x) (((x) >> BIT_SHIFT_MACID2_8197F) & BIT_MASK_MACID2_8197F) -#define BIT_SET_MACID2_8197F(x, v) (BIT_CLEAR_MACID2_8197F(x) | BIT_MACID2_8197F(v)) - +#define BIT_GET_MACID2_8197F(x) \ + (((x) >> BIT_SHIFT_MACID2_8197F) & BIT_MASK_MACID2_8197F) +#define BIT_SET_MACID2_8197F(x, v) \ + (BIT_CLEAR_MACID2_8197F(x) | BIT_MACID2_8197F(v)) /* 2 REG_BSSID2_8197F (BSSID2 REGISTER) */ #define BIT_SHIFT_BSSID2_8197F 0 #define BIT_MASK_BSSID2_8197F 0xffffffffffffL -#define BIT_BSSID2_8197F(x) (((x) & BIT_MASK_BSSID2_8197F) << BIT_SHIFT_BSSID2_8197F) +#define BIT_BSSID2_8197F(x) \ + (((x) & BIT_MASK_BSSID2_8197F) << BIT_SHIFT_BSSID2_8197F) #define BITS_BSSID2_8197F (BIT_MASK_BSSID2_8197F << BIT_SHIFT_BSSID2_8197F) #define BIT_CLEAR_BSSID2_8197F(x) ((x) & (~BITS_BSSID2_8197F)) -#define BIT_GET_BSSID2_8197F(x) (((x) >> BIT_SHIFT_BSSID2_8197F) & BIT_MASK_BSSID2_8197F) -#define BIT_SET_BSSID2_8197F(x, v) (BIT_CLEAR_BSSID2_8197F(x) | BIT_BSSID2_8197F(v)) - +#define BIT_GET_BSSID2_8197F(x) \ + (((x) >> BIT_SHIFT_BSSID2_8197F) & BIT_MASK_BSSID2_8197F) +#define BIT_SET_BSSID2_8197F(x, v) \ + (BIT_CLEAR_BSSID2_8197F(x) | BIT_BSSID2_8197F(v)) /* 2 REG_MACID3_8197F (MAC ID3 REGISTER) */ #define BIT_SHIFT_MACID3_8197F 0 #define BIT_MASK_MACID3_8197F 0xffffffffffffL -#define BIT_MACID3_8197F(x) (((x) & BIT_MASK_MACID3_8197F) << BIT_SHIFT_MACID3_8197F) +#define BIT_MACID3_8197F(x) \ + (((x) & BIT_MASK_MACID3_8197F) << BIT_SHIFT_MACID3_8197F) #define BITS_MACID3_8197F (BIT_MASK_MACID3_8197F << BIT_SHIFT_MACID3_8197F) #define BIT_CLEAR_MACID3_8197F(x) ((x) & (~BITS_MACID3_8197F)) -#define BIT_GET_MACID3_8197F(x) (((x) >> BIT_SHIFT_MACID3_8197F) & BIT_MASK_MACID3_8197F) -#define BIT_SET_MACID3_8197F(x, v) (BIT_CLEAR_MACID3_8197F(x) | BIT_MACID3_8197F(v)) - +#define BIT_GET_MACID3_8197F(x) \ + (((x) >> BIT_SHIFT_MACID3_8197F) & BIT_MASK_MACID3_8197F) +#define BIT_SET_MACID3_8197F(x, v) \ + (BIT_CLEAR_MACID3_8197F(x) | BIT_MACID3_8197F(v)) /* 2 REG_BSSID3_8197F (BSSID3 REGISTER) */ #define BIT_SHIFT_BSSID3_8197F 0 #define BIT_MASK_BSSID3_8197F 0xffffffffffffL -#define BIT_BSSID3_8197F(x) (((x) & BIT_MASK_BSSID3_8197F) << BIT_SHIFT_BSSID3_8197F) +#define BIT_BSSID3_8197F(x) \ + (((x) & BIT_MASK_BSSID3_8197F) << BIT_SHIFT_BSSID3_8197F) #define BITS_BSSID3_8197F (BIT_MASK_BSSID3_8197F << BIT_SHIFT_BSSID3_8197F) #define BIT_CLEAR_BSSID3_8197F(x) ((x) & (~BITS_BSSID3_8197F)) -#define BIT_GET_BSSID3_8197F(x) (((x) >> BIT_SHIFT_BSSID3_8197F) & BIT_MASK_BSSID3_8197F) -#define BIT_SET_BSSID3_8197F(x, v) (BIT_CLEAR_BSSID3_8197F(x) | BIT_BSSID3_8197F(v)) - +#define BIT_GET_BSSID3_8197F(x) \ + (((x) >> BIT_SHIFT_BSSID3_8197F) & BIT_MASK_BSSID3_8197F) +#define BIT_SET_BSSID3_8197F(x, v) \ + (BIT_CLEAR_BSSID3_8197F(x) | BIT_BSSID3_8197F(v)) /* 2 REG_MACID4_8197F (MAC ID4 REGISTER) */ #define BIT_SHIFT_MACID4_8197F 0 #define BIT_MASK_MACID4_8197F 0xffffffffffffL -#define BIT_MACID4_8197F(x) (((x) & BIT_MASK_MACID4_8197F) << BIT_SHIFT_MACID4_8197F) +#define BIT_MACID4_8197F(x) \ + (((x) & BIT_MASK_MACID4_8197F) << BIT_SHIFT_MACID4_8197F) #define BITS_MACID4_8197F (BIT_MASK_MACID4_8197F << BIT_SHIFT_MACID4_8197F) #define BIT_CLEAR_MACID4_8197F(x) ((x) & (~BITS_MACID4_8197F)) -#define BIT_GET_MACID4_8197F(x) (((x) >> BIT_SHIFT_MACID4_8197F) & BIT_MASK_MACID4_8197F) -#define BIT_SET_MACID4_8197F(x, v) (BIT_CLEAR_MACID4_8197F(x) | BIT_MACID4_8197F(v)) - +#define BIT_GET_MACID4_8197F(x) \ + (((x) >> BIT_SHIFT_MACID4_8197F) & BIT_MASK_MACID4_8197F) +#define BIT_SET_MACID4_8197F(x, v) \ + (BIT_CLEAR_MACID4_8197F(x) | BIT_MACID4_8197F(v)) /* 2 REG_BSSID4_8197F (BSSID4 REGISTER) */ #define BIT_SHIFT_BSSID4_8197F 0 #define BIT_MASK_BSSID4_8197F 0xffffffffffffL -#define BIT_BSSID4_8197F(x) (((x) & BIT_MASK_BSSID4_8197F) << BIT_SHIFT_BSSID4_8197F) +#define BIT_BSSID4_8197F(x) \ + (((x) & BIT_MASK_BSSID4_8197F) << BIT_SHIFT_BSSID4_8197F) #define BITS_BSSID4_8197F (BIT_MASK_BSSID4_8197F << BIT_SHIFT_BSSID4_8197F) #define BIT_CLEAR_BSSID4_8197F(x) ((x) & (~BITS_BSSID4_8197F)) -#define BIT_GET_BSSID4_8197F(x) (((x) >> BIT_SHIFT_BSSID4_8197F) & BIT_MASK_BSSID4_8197F) -#define BIT_SET_BSSID4_8197F(x, v) (BIT_CLEAR_BSSID4_8197F(x) | BIT_BSSID4_8197F(v)) - +#define BIT_GET_BSSID4_8197F(x) \ + (((x) >> BIT_SHIFT_BSSID4_8197F) & BIT_MASK_BSSID4_8197F) +#define BIT_SET_BSSID4_8197F(x, v) \ + (BIT_CLEAR_BSSID4_8197F(x) | BIT_BSSID4_8197F(v)) /* 2 REG_NOA_REPORT_8197F */ @@ -11782,20 +15454,37 @@ #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F 4 #define BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F 0x3 -#define BIT_WMAC_TXMU_ACKPOLICY_8197F(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) -#define BITS_WMAC_TXMU_ACKPOLICY_8197F (BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) -#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8197F)) -#define BIT_GET_WMAC_TXMU_ACKPOLICY_8197F(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F) -#define BIT_SET_WMAC_TXMU_ACKPOLICY_8197F(x, v) (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) | BIT_WMAC_TXMU_ACKPOLICY_8197F(v)) - +#define BIT_WMAC_TXMU_ACKPOLICY_8197F(x) \ + (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F) \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) +#define BITS_WMAC_TXMU_ACKPOLICY_8197F \ + (BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) \ + ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8197F)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) & \ + BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F) +#define BIT_SET_WMAC_TXMU_ACKPOLICY_8197F(x, v) \ + (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) | \ + BIT_WMAC_TXMU_ACKPOLICY_8197F(v)) #define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F 1 #define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F 0x7 -#define BIT_WMAC_MU_BFEE_PORT_SEL_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) -#define BITS_WMAC_MU_BFEE_PORT_SEL_8197F (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8197F)) -#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F) -#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) | BIT_WMAC_MU_BFEE_PORT_SEL_8197F(v)) +#define BIT_WMAC_MU_BFEE_PORT_SEL_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) +#define BITS_WMAC_MU_BFEE_PORT_SEL_8197F \ + (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8197F)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) & \ + BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) | \ + BIT_WMAC_MU_BFEE_PORT_SEL_8197F(v)) #define BIT_WMAC_MU_BFEE_DIS_8197F BIT(0) @@ -11803,12 +15492,20 @@ #define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F 0 #define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F 0xff -#define BIT_WMAC_PAUSE_BB_CLR_TH_8197F(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) -#define BITS_WMAC_PAUSE_BB_CLR_TH_8197F (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) -#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8197F)) -#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8197F(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F) -#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8197F(x, v) (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) | BIT_WMAC_PAUSE_BB_CLR_TH_8197F(v)) - +#define BIT_WMAC_PAUSE_BB_CLR_TH_8197F(x) \ + (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F) \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) +#define BITS_WMAC_PAUSE_BB_CLR_TH_8197F \ + (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) \ + ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8197F)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) & \ + BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8197F(x, v) \ + (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) | \ + BIT_WMAC_PAUSE_BB_CLR_TH_8197F(v)) /* 2 REG_WMAC_MU_ARB_8197F */ #define BIT_WMAC_ARB_HW_ADAPT_EN_8197F BIT(7) @@ -11816,32 +15513,51 @@ #define BIT_SHIFT_WMAC_ARB_SW_STATE_8197F 0 #define BIT_MASK_WMAC_ARB_SW_STATE_8197F 0x3f -#define BIT_WMAC_ARB_SW_STATE_8197F(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8197F) << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) -#define BITS_WMAC_ARB_SW_STATE_8197F (BIT_MASK_WMAC_ARB_SW_STATE_8197F << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) -#define BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) ((x) & (~BITS_WMAC_ARB_SW_STATE_8197F)) -#define BIT_GET_WMAC_ARB_SW_STATE_8197F(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) & BIT_MASK_WMAC_ARB_SW_STATE_8197F) -#define BIT_SET_WMAC_ARB_SW_STATE_8197F(x, v) (BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) | BIT_WMAC_ARB_SW_STATE_8197F(v)) - +#define BIT_WMAC_ARB_SW_STATE_8197F(x) \ + (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8197F) \ + << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) +#define BITS_WMAC_ARB_SW_STATE_8197F \ + (BIT_MASK_WMAC_ARB_SW_STATE_8197F << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) +#define BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) \ + ((x) & (~BITS_WMAC_ARB_SW_STATE_8197F)) +#define BIT_GET_WMAC_ARB_SW_STATE_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) & \ + BIT_MASK_WMAC_ARB_SW_STATE_8197F) +#define BIT_SET_WMAC_ARB_SW_STATE_8197F(x, v) \ + (BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) | BIT_WMAC_ARB_SW_STATE_8197F(v)) /* 2 REG_WMAC_MU_OPTION_8197F */ #define BIT_SHIFT_WMAC_MU_DBGSEL_8197F 5 #define BIT_MASK_WMAC_MU_DBGSEL_8197F 0x3 -#define BIT_WMAC_MU_DBGSEL_8197F(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8197F) << BIT_SHIFT_WMAC_MU_DBGSEL_8197F) -#define BITS_WMAC_MU_DBGSEL_8197F (BIT_MASK_WMAC_MU_DBGSEL_8197F << BIT_SHIFT_WMAC_MU_DBGSEL_8197F) +#define BIT_WMAC_MU_DBGSEL_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_DBGSEL_8197F) \ + << BIT_SHIFT_WMAC_MU_DBGSEL_8197F) +#define BITS_WMAC_MU_DBGSEL_8197F \ + (BIT_MASK_WMAC_MU_DBGSEL_8197F << BIT_SHIFT_WMAC_MU_DBGSEL_8197F) #define BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8197F)) -#define BIT_GET_WMAC_MU_DBGSEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8197F) & BIT_MASK_WMAC_MU_DBGSEL_8197F) -#define BIT_SET_WMAC_MU_DBGSEL_8197F(x, v) (BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) | BIT_WMAC_MU_DBGSEL_8197F(v)) - +#define BIT_GET_WMAC_MU_DBGSEL_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8197F) & \ + BIT_MASK_WMAC_MU_DBGSEL_8197F) +#define BIT_SET_WMAC_MU_DBGSEL_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) | BIT_WMAC_MU_DBGSEL_8197F(v)) #define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F 0 #define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F 0x1f -#define BIT_WMAC_MU_CPRD_TIMEOUT_8197F(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) -#define BITS_WMAC_MU_CPRD_TIMEOUT_8197F (BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) -#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8197F)) -#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F) -#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8197F(x, v) (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) | BIT_WMAC_MU_CPRD_TIMEOUT_8197F(v)) - +#define BIT_WMAC_MU_CPRD_TIMEOUT_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F) \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) +#define BITS_WMAC_MU_CPRD_TIMEOUT_8197F \ + (BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) +#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) \ + ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8197F)) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) & \ + BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F) +#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) | \ + BIT_WMAC_MU_CPRD_TIMEOUT_8197F(v)) /* 2 REG_WMAC_MU_BF_CTL_8197F */ #define BIT_WMAC_INVLD_BFPRT_CHK_8197F BIT(15) @@ -11849,41 +15565,66 @@ #define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F 12 #define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F 0x3 -#define BIT_WMAC_MU_BFRPTSEG_SEL_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) -#define BITS_WMAC_MU_BFRPTSEG_SEL_8197F (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) -#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8197F)) -#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F) -#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) | BIT_WMAC_MU_BFRPTSEG_SEL_8197F(v)) - +#define BIT_WMAC_MU_BFRPTSEG_SEL_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F) \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) +#define BITS_WMAC_MU_BFRPTSEG_SEL_8197F \ + (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8197F)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) & \ + BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) | \ + BIT_WMAC_MU_BFRPTSEG_SEL_8197F(v)) #define BIT_SHIFT_WMAC_MU_BF_MYAID_8197F 0 #define BIT_MASK_WMAC_MU_BF_MYAID_8197F 0xfff -#define BIT_WMAC_MU_BF_MYAID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8197F) << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) -#define BITS_WMAC_MU_BF_MYAID_8197F (BIT_MASK_WMAC_MU_BF_MYAID_8197F << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) -#define BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) ((x) & (~BITS_WMAC_MU_BF_MYAID_8197F)) -#define BIT_GET_WMAC_MU_BF_MYAID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) & BIT_MASK_WMAC_MU_BF_MYAID_8197F) -#define BIT_SET_WMAC_MU_BF_MYAID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) | BIT_WMAC_MU_BF_MYAID_8197F(v)) - +#define BIT_WMAC_MU_BF_MYAID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8197F) \ + << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) +#define BITS_WMAC_MU_BF_MYAID_8197F \ + (BIT_MASK_WMAC_MU_BF_MYAID_8197F << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BF_MYAID_8197F)) +#define BIT_GET_WMAC_MU_BF_MYAID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) & \ + BIT_MASK_WMAC_MU_BF_MYAID_8197F) +#define BIT_SET_WMAC_MU_BF_MYAID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) | BIT_WMAC_MU_BF_MYAID_8197F(v)) /* 2 REG_WMAC_MU_BFRPT_PARA_8197F */ #define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F 12 #define BIT_MASK_BFRPT_PARA_USERID_SEL_8197F 0x7 -#define BIT_BFRPT_PARA_USERID_SEL_8197F(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8197F) << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) -#define BITS_BFRPT_PARA_USERID_SEL_8197F (BIT_MASK_BFRPT_PARA_USERID_SEL_8197F << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) -#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) ((x) & (~BITS_BFRPT_PARA_USERID_SEL_8197F)) -#define BIT_GET_BFRPT_PARA_USERID_SEL_8197F(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) & BIT_MASK_BFRPT_PARA_USERID_SEL_8197F) -#define BIT_SET_BFRPT_PARA_USERID_SEL_8197F(x, v) (BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) | BIT_BFRPT_PARA_USERID_SEL_8197F(v)) - +#define BIT_BFRPT_PARA_USERID_SEL_8197F(x) \ + (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8197F) \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) +#define BITS_BFRPT_PARA_USERID_SEL_8197F \ + (BIT_MASK_BFRPT_PARA_USERID_SEL_8197F \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) \ + ((x) & (~BITS_BFRPT_PARA_USERID_SEL_8197F)) +#define BIT_GET_BFRPT_PARA_USERID_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) & \ + BIT_MASK_BFRPT_PARA_USERID_SEL_8197F) +#define BIT_SET_BFRPT_PARA_USERID_SEL_8197F(x, v) \ + (BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) | \ + BIT_BFRPT_PARA_USERID_SEL_8197F(v)) #define BIT_SHIFT_BFRPT_PARA_8197F 0 #define BIT_MASK_BFRPT_PARA_8197F 0xfff -#define BIT_BFRPT_PARA_8197F(x) (((x) & BIT_MASK_BFRPT_PARA_8197F) << BIT_SHIFT_BFRPT_PARA_8197F) -#define BITS_BFRPT_PARA_8197F (BIT_MASK_BFRPT_PARA_8197F << BIT_SHIFT_BFRPT_PARA_8197F) +#define BIT_BFRPT_PARA_8197F(x) \ + (((x) & BIT_MASK_BFRPT_PARA_8197F) << BIT_SHIFT_BFRPT_PARA_8197F) +#define BITS_BFRPT_PARA_8197F \ + (BIT_MASK_BFRPT_PARA_8197F << BIT_SHIFT_BFRPT_PARA_8197F) #define BIT_CLEAR_BFRPT_PARA_8197F(x) ((x) & (~BITS_BFRPT_PARA_8197F)) -#define BIT_GET_BFRPT_PARA_8197F(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8197F) & BIT_MASK_BFRPT_PARA_8197F) -#define BIT_SET_BFRPT_PARA_8197F(x, v) (BIT_CLEAR_BFRPT_PARA_8197F(x) | BIT_BFRPT_PARA_8197F(v)) - +#define BIT_GET_BFRPT_PARA_8197F(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_8197F) & BIT_MASK_BFRPT_PARA_8197F) +#define BIT_SET_BFRPT_PARA_8197F(x, v) \ + (BIT_CLEAR_BFRPT_PARA_8197F(x) | BIT_BFRPT_PARA_8197F(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F */ #define BIT_STATUS_BFEE2_8197F BIT(10) @@ -11891,12 +15632,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F 0 #define BIT_MASK_WMAC_MU_BFEE2_AID_8197F 0x1ff -#define BIT_WMAC_MU_BFEE2_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) -#define BITS_WMAC_MU_BFEE2_AID_8197F (BIT_MASK_WMAC_MU_BFEE2_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE2_AID_8197F)) -#define BIT_GET_WMAC_MU_BFEE2_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) & BIT_MASK_WMAC_MU_BFEE2_AID_8197F) -#define BIT_SET_WMAC_MU_BFEE2_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) | BIT_WMAC_MU_BFEE2_AID_8197F(v)) - +#define BIT_WMAC_MU_BFEE2_AID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) +#define BITS_WMAC_MU_BFEE2_AID_8197F \ + (BIT_MASK_WMAC_MU_BFEE2_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE2_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE2_AID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) & \ + BIT_MASK_WMAC_MU_BFEE2_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE2_AID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) | BIT_WMAC_MU_BFEE2_AID_8197F(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F */ #define BIT_STATUS_BFEE3_8197F BIT(10) @@ -11904,12 +15651,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F 0 #define BIT_MASK_WMAC_MU_BFEE3_AID_8197F 0x1ff -#define BIT_WMAC_MU_BFEE3_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) -#define BITS_WMAC_MU_BFEE3_AID_8197F (BIT_MASK_WMAC_MU_BFEE3_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE3_AID_8197F)) -#define BIT_GET_WMAC_MU_BFEE3_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) & BIT_MASK_WMAC_MU_BFEE3_AID_8197F) -#define BIT_SET_WMAC_MU_BFEE3_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) | BIT_WMAC_MU_BFEE3_AID_8197F(v)) - +#define BIT_WMAC_MU_BFEE3_AID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) +#define BITS_WMAC_MU_BFEE3_AID_8197F \ + (BIT_MASK_WMAC_MU_BFEE3_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE3_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE3_AID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) & \ + BIT_MASK_WMAC_MU_BFEE3_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE3_AID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) | BIT_WMAC_MU_BFEE3_AID_8197F(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F */ #define BIT_STATUS_BFEE4_8197F BIT(10) @@ -11917,12 +15670,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F 0 #define BIT_MASK_WMAC_MU_BFEE4_AID_8197F 0x1ff -#define BIT_WMAC_MU_BFEE4_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) -#define BITS_WMAC_MU_BFEE4_AID_8197F (BIT_MASK_WMAC_MU_BFEE4_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE4_AID_8197F)) -#define BIT_GET_WMAC_MU_BFEE4_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) & BIT_MASK_WMAC_MU_BFEE4_AID_8197F) -#define BIT_SET_WMAC_MU_BFEE4_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) | BIT_WMAC_MU_BFEE4_AID_8197F(v)) - +#define BIT_WMAC_MU_BFEE4_AID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) +#define BITS_WMAC_MU_BFEE4_AID_8197F \ + (BIT_MASK_WMAC_MU_BFEE4_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE4_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE4_AID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) & \ + BIT_MASK_WMAC_MU_BFEE4_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE4_AID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) | BIT_WMAC_MU_BFEE4_AID_8197F(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F */ #define BIT_STATUS_BFEE5_8197F BIT(10) @@ -11930,12 +15689,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F 0 #define BIT_MASK_WMAC_MU_BFEE5_AID_8197F 0x1ff -#define BIT_WMAC_MU_BFEE5_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) -#define BITS_WMAC_MU_BFEE5_AID_8197F (BIT_MASK_WMAC_MU_BFEE5_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE5_AID_8197F)) -#define BIT_GET_WMAC_MU_BFEE5_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) & BIT_MASK_WMAC_MU_BFEE5_AID_8197F) -#define BIT_SET_WMAC_MU_BFEE5_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) | BIT_WMAC_MU_BFEE5_AID_8197F(v)) - +#define BIT_WMAC_MU_BFEE5_AID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) +#define BITS_WMAC_MU_BFEE5_AID_8197F \ + (BIT_MASK_WMAC_MU_BFEE5_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE5_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE5_AID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) & \ + BIT_MASK_WMAC_MU_BFEE5_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE5_AID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) | BIT_WMAC_MU_BFEE5_AID_8197F(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F */ #define BIT_STATUS_BFEE6_8197F BIT(10) @@ -11943,12 +15708,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F 0 #define BIT_MASK_WMAC_MU_BFEE6_AID_8197F 0x1ff -#define BIT_WMAC_MU_BFEE6_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) -#define BITS_WMAC_MU_BFEE6_AID_8197F (BIT_MASK_WMAC_MU_BFEE6_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE6_AID_8197F)) -#define BIT_GET_WMAC_MU_BFEE6_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) & BIT_MASK_WMAC_MU_BFEE6_AID_8197F) -#define BIT_SET_WMAC_MU_BFEE6_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) | BIT_WMAC_MU_BFEE6_AID_8197F(v)) - +#define BIT_WMAC_MU_BFEE6_AID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) +#define BITS_WMAC_MU_BFEE6_AID_8197F \ + (BIT_MASK_WMAC_MU_BFEE6_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE6_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE6_AID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) & \ + BIT_MASK_WMAC_MU_BFEE6_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE6_AID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) | BIT_WMAC_MU_BFEE6_AID_8197F(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F */ #define BIT_BIT_STATUS_BFEE4_8197F BIT(10) @@ -11956,72 +15727,118 @@ #define BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F 0 #define BIT_MASK_WMAC_MU_BFEE7_AID_8197F 0x1ff -#define BIT_WMAC_MU_BFEE7_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) -#define BITS_WMAC_MU_BFEE7_AID_8197F (BIT_MASK_WMAC_MU_BFEE7_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE7_AID_8197F)) -#define BIT_GET_WMAC_MU_BFEE7_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) & BIT_MASK_WMAC_MU_BFEE7_AID_8197F) -#define BIT_SET_WMAC_MU_BFEE7_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) | BIT_WMAC_MU_BFEE7_AID_8197F(v)) - +#define BIT_WMAC_MU_BFEE7_AID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) +#define BITS_WMAC_MU_BFEE7_AID_8197F \ + (BIT_MASK_WMAC_MU_BFEE7_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE7_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE7_AID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) & \ + BIT_MASK_WMAC_MU_BFEE7_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE7_AID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) | BIT_WMAC_MU_BFEE7_AID_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_RST_ALL_COUNTER_8197F BIT(31) #define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F 16 #define BIT_MASK_ABORT_RX_VBON_COUNTER_8197F 0xff -#define BIT_ABORT_RX_VBON_COUNTER_8197F(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8197F) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) -#define BITS_ABORT_RX_VBON_COUNTER_8197F (BIT_MASK_ABORT_RX_VBON_COUNTER_8197F << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) -#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8197F)) -#define BIT_GET_ABORT_RX_VBON_COUNTER_8197F(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) & BIT_MASK_ABORT_RX_VBON_COUNTER_8197F) -#define BIT_SET_ABORT_RX_VBON_COUNTER_8197F(x, v) (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) | BIT_ABORT_RX_VBON_COUNTER_8197F(v)) - +#define BIT_ABORT_RX_VBON_COUNTER_8197F(x) \ + (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8197F) \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) +#define BITS_ABORT_RX_VBON_COUNTER_8197F \ + (BIT_MASK_ABORT_RX_VBON_COUNTER_8197F \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) \ + ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8197F)) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8197F(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) & \ + BIT_MASK_ABORT_RX_VBON_COUNTER_8197F) +#define BIT_SET_ABORT_RX_VBON_COUNTER_8197F(x, v) \ + (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) | \ + BIT_ABORT_RX_VBON_COUNTER_8197F(v)) #define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F 8 #define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F 0xff -#define BIT_ABORT_RX_RDRDY_COUNTER_8197F(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) -#define BITS_ABORT_RX_RDRDY_COUNTER_8197F (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) -#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8197F)) -#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8197F(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F) -#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8197F(x, v) (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) | BIT_ABORT_RX_RDRDY_COUNTER_8197F(v)) - +#define BIT_ABORT_RX_RDRDY_COUNTER_8197F(x) \ + (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F) \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) +#define BITS_ABORT_RX_RDRDY_COUNTER_8197F \ + (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) \ + ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8197F)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8197F(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) & \ + BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8197F(x, v) \ + (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) | \ + BIT_ABORT_RX_RDRDY_COUNTER_8197F(v)) #define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F 0 #define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F 0xff -#define BIT_VBON_EARLY_FALLING_COUNTER_8197F(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) -#define BITS_VBON_EARLY_FALLING_COUNTER_8197F (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) -#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8197F)) -#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8197F(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F) -#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8197F(x, v) (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) | BIT_VBON_EARLY_FALLING_COUNTER_8197F(v)) - +#define BIT_VBON_EARLY_FALLING_COUNTER_8197F(x) \ + (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F) \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) +#define BITS_VBON_EARLY_FALLING_COUNTER_8197F \ + (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) \ + ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8197F)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8197F(x) \ + (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) & \ + BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8197F(x, v) \ + (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) | \ + BIT_VBON_EARLY_FALLING_COUNTER_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_WMAC_PLCP_TRX_SEL_8197F BIT(31) #define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F 28 #define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F 0x7 -#define BIT_WMAC_PLCP_RDSIG_SEL_8197F(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) -#define BITS_WMAC_PLCP_RDSIG_SEL_8197F (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) -#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8197F)) -#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F) -#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8197F(x, v) (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) | BIT_WMAC_PLCP_RDSIG_SEL_8197F(v)) - +#define BIT_WMAC_PLCP_RDSIG_SEL_8197F(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) +#define BITS_WMAC_PLCP_RDSIG_SEL_8197F \ + (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) \ + ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8197F)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) & \ + BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8197F(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) | \ + BIT_WMAC_PLCP_RDSIG_SEL_8197F(v)) #define BIT_SHIFT_WMAC_RATE_IDX_8197F 24 #define BIT_MASK_WMAC_RATE_IDX_8197F 0xf -#define BIT_WMAC_RATE_IDX_8197F(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8197F) << BIT_SHIFT_WMAC_RATE_IDX_8197F) -#define BITS_WMAC_RATE_IDX_8197F (BIT_MASK_WMAC_RATE_IDX_8197F << BIT_SHIFT_WMAC_RATE_IDX_8197F) +#define BIT_WMAC_RATE_IDX_8197F(x) \ + (((x) & BIT_MASK_WMAC_RATE_IDX_8197F) << BIT_SHIFT_WMAC_RATE_IDX_8197F) +#define BITS_WMAC_RATE_IDX_8197F \ + (BIT_MASK_WMAC_RATE_IDX_8197F << BIT_SHIFT_WMAC_RATE_IDX_8197F) #define BIT_CLEAR_WMAC_RATE_IDX_8197F(x) ((x) & (~BITS_WMAC_RATE_IDX_8197F)) -#define BIT_GET_WMAC_RATE_IDX_8197F(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8197F) & BIT_MASK_WMAC_RATE_IDX_8197F) -#define BIT_SET_WMAC_RATE_IDX_8197F(x, v) (BIT_CLEAR_WMAC_RATE_IDX_8197F(x) | BIT_WMAC_RATE_IDX_8197F(v)) - +#define BIT_GET_WMAC_RATE_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8197F) & BIT_MASK_WMAC_RATE_IDX_8197F) +#define BIT_SET_WMAC_RATE_IDX_8197F(x, v) \ + (BIT_CLEAR_WMAC_RATE_IDX_8197F(x) | BIT_WMAC_RATE_IDX_8197F(v)) #define BIT_SHIFT_WMAC_PLCP_RDSIG_8197F 0 #define BIT_MASK_WMAC_PLCP_RDSIG_8197F 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8197F(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8197F) << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) -#define BITS_WMAC_PLCP_RDSIG_8197F (BIT_MASK_WMAC_PLCP_RDSIG_8197F << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) +#define BIT_WMAC_PLCP_RDSIG_8197F(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8197F) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) +#define BITS_WMAC_PLCP_RDSIG_8197F \ + (BIT_MASK_WMAC_PLCP_RDSIG_8197F << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) #define BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8197F)) -#define BIT_GET_WMAC_PLCP_RDSIG_8197F(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) & BIT_MASK_WMAC_PLCP_RDSIG_8197F) -#define BIT_SET_WMAC_PLCP_RDSIG_8197F(x, v) (BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) | BIT_WMAC_PLCP_RDSIG_8197F(v)) - +#define BIT_GET_WMAC_PLCP_RDSIG_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8197F) +#define BIT_SET_WMAC_PLCP_RDSIG_8197F(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) | BIT_WMAC_PLCP_RDSIG_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -12043,7 +15860,6 @@ #define BIT_GET_TA0_8197F(x) (((x) >> BIT_SHIFT_TA0_8197F) & BIT_MASK_TA0_8197F) #define BIT_SET_TA0_8197F(x, v) (BIT_CLEAR_TA0_8197F(x) | BIT_TA0_8197F(v)) - /* 2 REG_TRANSMIT_ADDRSS_1_8197F (TA1 REGISTER) */ #define BIT_SHIFT_TA1_8197F 0 @@ -12054,7 +15870,6 @@ #define BIT_GET_TA1_8197F(x) (((x) >> BIT_SHIFT_TA1_8197F) & BIT_MASK_TA1_8197F) #define BIT_SET_TA1_8197F(x, v) (BIT_CLEAR_TA1_8197F(x) | BIT_TA1_8197F(v)) - /* 2 REG_TRANSMIT_ADDRSS_2_8197F (TA2 REGISTER) */ #define BIT_SHIFT_TA2_8197F 0 @@ -12065,7 +15880,6 @@ #define BIT_GET_TA2_8197F(x) (((x) >> BIT_SHIFT_TA2_8197F) & BIT_MASK_TA2_8197F) #define BIT_SET_TA2_8197F(x, v) (BIT_CLEAR_TA2_8197F(x) | BIT_TA2_8197F(v)) - /* 2 REG_TRANSMIT_ADDRSS_3_8197F (TA3 REGISTER) */ #define BIT_SHIFT_TA3_8197F 0 @@ -12076,7 +15890,6 @@ #define BIT_GET_TA3_8197F(x) (((x) >> BIT_SHIFT_TA3_8197F) & BIT_MASK_TA3_8197F) #define BIT_SET_TA3_8197F(x, v) (BIT_CLEAR_TA3_8197F(x) | BIT_TA3_8197F(v)) - /* 2 REG_TRANSMIT_ADDRSS_4_8197F (TA4 REGISTER) */ #define BIT_SHIFT_TA4_8197F 0 @@ -12087,61 +15900,74 @@ #define BIT_GET_TA4_8197F(x) (((x) >> BIT_SHIFT_TA4_8197F) & BIT_MASK_TA4_8197F) #define BIT_SET_TA4_8197F(x, v) (BIT_CLEAR_TA4_8197F(x) | BIT_TA4_8197F(v)) - /* 2 REG_NOT_VALID_8197F */ /* 2 REG_MACID1_8197F */ #define BIT_SHIFT_MACID1_8197F 0 #define BIT_MASK_MACID1_8197F 0xffffffffffffL -#define BIT_MACID1_8197F(x) (((x) & BIT_MASK_MACID1_8197F) << BIT_SHIFT_MACID1_8197F) +#define BIT_MACID1_8197F(x) \ + (((x) & BIT_MASK_MACID1_8197F) << BIT_SHIFT_MACID1_8197F) #define BITS_MACID1_8197F (BIT_MASK_MACID1_8197F << BIT_SHIFT_MACID1_8197F) #define BIT_CLEAR_MACID1_8197F(x) ((x) & (~BITS_MACID1_8197F)) -#define BIT_GET_MACID1_8197F(x) (((x) >> BIT_SHIFT_MACID1_8197F) & BIT_MASK_MACID1_8197F) -#define BIT_SET_MACID1_8197F(x, v) (BIT_CLEAR_MACID1_8197F(x) | BIT_MACID1_8197F(v)) - +#define BIT_GET_MACID1_8197F(x) \ + (((x) >> BIT_SHIFT_MACID1_8197F) & BIT_MASK_MACID1_8197F) +#define BIT_SET_MACID1_8197F(x, v) \ + (BIT_CLEAR_MACID1_8197F(x) | BIT_MACID1_8197F(v)) /* 2 REG_BSSID1_8197F */ #define BIT_SHIFT_BSSID1_8197F 0 #define BIT_MASK_BSSID1_8197F 0xffffffffffffL -#define BIT_BSSID1_8197F(x) (((x) & BIT_MASK_BSSID1_8197F) << BIT_SHIFT_BSSID1_8197F) +#define BIT_BSSID1_8197F(x) \ + (((x) & BIT_MASK_BSSID1_8197F) << BIT_SHIFT_BSSID1_8197F) #define BITS_BSSID1_8197F (BIT_MASK_BSSID1_8197F << BIT_SHIFT_BSSID1_8197F) #define BIT_CLEAR_BSSID1_8197F(x) ((x) & (~BITS_BSSID1_8197F)) -#define BIT_GET_BSSID1_8197F(x) (((x) >> BIT_SHIFT_BSSID1_8197F) & BIT_MASK_BSSID1_8197F) -#define BIT_SET_BSSID1_8197F(x, v) (BIT_CLEAR_BSSID1_8197F(x) | BIT_BSSID1_8197F(v)) - +#define BIT_GET_BSSID1_8197F(x) \ + (((x) >> BIT_SHIFT_BSSID1_8197F) & BIT_MASK_BSSID1_8197F) +#define BIT_SET_BSSID1_8197F(x, v) \ + (BIT_CLEAR_BSSID1_8197F(x) | BIT_BSSID1_8197F(v)) /* 2 REG_BCN_PSR_RPT1_8197F */ #define BIT_SHIFT_DTIM_CNT1_8197F 24 #define BIT_MASK_DTIM_CNT1_8197F 0xff -#define BIT_DTIM_CNT1_8197F(x) (((x) & BIT_MASK_DTIM_CNT1_8197F) << BIT_SHIFT_DTIM_CNT1_8197F) -#define BITS_DTIM_CNT1_8197F (BIT_MASK_DTIM_CNT1_8197F << BIT_SHIFT_DTIM_CNT1_8197F) +#define BIT_DTIM_CNT1_8197F(x) \ + (((x) & BIT_MASK_DTIM_CNT1_8197F) << BIT_SHIFT_DTIM_CNT1_8197F) +#define BITS_DTIM_CNT1_8197F \ + (BIT_MASK_DTIM_CNT1_8197F << BIT_SHIFT_DTIM_CNT1_8197F) #define BIT_CLEAR_DTIM_CNT1_8197F(x) ((x) & (~BITS_DTIM_CNT1_8197F)) -#define BIT_GET_DTIM_CNT1_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8197F) & BIT_MASK_DTIM_CNT1_8197F) -#define BIT_SET_DTIM_CNT1_8197F(x, v) (BIT_CLEAR_DTIM_CNT1_8197F(x) | BIT_DTIM_CNT1_8197F(v)) - +#define BIT_GET_DTIM_CNT1_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT1_8197F) & BIT_MASK_DTIM_CNT1_8197F) +#define BIT_SET_DTIM_CNT1_8197F(x, v) \ + (BIT_CLEAR_DTIM_CNT1_8197F(x) | BIT_DTIM_CNT1_8197F(v)) #define BIT_SHIFT_DTIM_PERIOD1_8197F 16 #define BIT_MASK_DTIM_PERIOD1_8197F 0xff -#define BIT_DTIM_PERIOD1_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD1_8197F) << BIT_SHIFT_DTIM_PERIOD1_8197F) -#define BITS_DTIM_PERIOD1_8197F (BIT_MASK_DTIM_PERIOD1_8197F << BIT_SHIFT_DTIM_PERIOD1_8197F) +#define BIT_DTIM_PERIOD1_8197F(x) \ + (((x) & BIT_MASK_DTIM_PERIOD1_8197F) << BIT_SHIFT_DTIM_PERIOD1_8197F) +#define BITS_DTIM_PERIOD1_8197F \ + (BIT_MASK_DTIM_PERIOD1_8197F << BIT_SHIFT_DTIM_PERIOD1_8197F) #define BIT_CLEAR_DTIM_PERIOD1_8197F(x) ((x) & (~BITS_DTIM_PERIOD1_8197F)) -#define BIT_GET_DTIM_PERIOD1_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8197F) & BIT_MASK_DTIM_PERIOD1_8197F) -#define BIT_SET_DTIM_PERIOD1_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD1_8197F(x) | BIT_DTIM_PERIOD1_8197F(v)) +#define BIT_GET_DTIM_PERIOD1_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD1_8197F) & BIT_MASK_DTIM_PERIOD1_8197F) +#define BIT_SET_DTIM_PERIOD1_8197F(x, v) \ + (BIT_CLEAR_DTIM_PERIOD1_8197F(x) | BIT_DTIM_PERIOD1_8197F(v)) #define BIT_DTIM1_8197F BIT(15) #define BIT_TIM1_8197F BIT(14) #define BIT_SHIFT_PS_AID_1_8197F 0 #define BIT_MASK_PS_AID_1_8197F 0x7ff -#define BIT_PS_AID_1_8197F(x) (((x) & BIT_MASK_PS_AID_1_8197F) << BIT_SHIFT_PS_AID_1_8197F) -#define BITS_PS_AID_1_8197F (BIT_MASK_PS_AID_1_8197F << BIT_SHIFT_PS_AID_1_8197F) +#define BIT_PS_AID_1_8197F(x) \ + (((x) & BIT_MASK_PS_AID_1_8197F) << BIT_SHIFT_PS_AID_1_8197F) +#define BITS_PS_AID_1_8197F \ + (BIT_MASK_PS_AID_1_8197F << BIT_SHIFT_PS_AID_1_8197F) #define BIT_CLEAR_PS_AID_1_8197F(x) ((x) & (~BITS_PS_AID_1_8197F)) -#define BIT_GET_PS_AID_1_8197F(x) (((x) >> BIT_SHIFT_PS_AID_1_8197F) & BIT_MASK_PS_AID_1_8197F) -#define BIT_SET_PS_AID_1_8197F(x, v) (BIT_CLEAR_PS_AID_1_8197F(x) | BIT_PS_AID_1_8197F(v)) - +#define BIT_GET_PS_AID_1_8197F(x) \ + (((x) >> BIT_SHIFT_PS_AID_1_8197F) & BIT_MASK_PS_AID_1_8197F) +#define BIT_SET_PS_AID_1_8197F(x, v) \ + (BIT_CLEAR_PS_AID_1_8197F(x) | BIT_PS_AID_1_8197F(v)) /* 2 REG_ASSOCIATED_BFMEE_SEL_8197F */ #define BIT_TXUSER_ID1_8197F BIT(25) @@ -12151,7 +15977,8 @@ #define BIT_AID1_8197F(x) (((x) & BIT_MASK_AID1_8197F) << BIT_SHIFT_AID1_8197F) #define BITS_AID1_8197F (BIT_MASK_AID1_8197F << BIT_SHIFT_AID1_8197F) #define BIT_CLEAR_AID1_8197F(x) ((x) & (~BITS_AID1_8197F)) -#define BIT_GET_AID1_8197F(x) (((x) >> BIT_SHIFT_AID1_8197F) & BIT_MASK_AID1_8197F) +#define BIT_GET_AID1_8197F(x) \ + (((x) >> BIT_SHIFT_AID1_8197F) & BIT_MASK_AID1_8197F) #define BIT_SET_AID1_8197F(x, v) (BIT_CLEAR_AID1_8197F(x) | BIT_AID1_8197F(v)) #define BIT_TXUSER_ID0_8197F BIT(9) @@ -12161,37 +15988,60 @@ #define BIT_AID0_8197F(x) (((x) & BIT_MASK_AID0_8197F) << BIT_SHIFT_AID0_8197F) #define BITS_AID0_8197F (BIT_MASK_AID0_8197F << BIT_SHIFT_AID0_8197F) #define BIT_CLEAR_AID0_8197F(x) ((x) & (~BITS_AID0_8197F)) -#define BIT_GET_AID0_8197F(x) (((x) >> BIT_SHIFT_AID0_8197F) & BIT_MASK_AID0_8197F) +#define BIT_GET_AID0_8197F(x) \ + (((x) >> BIT_SHIFT_AID0_8197F) & BIT_MASK_AID0_8197F) #define BIT_SET_AID0_8197F(x, v) (BIT_CLEAR_AID0_8197F(x) | BIT_AID0_8197F(v)) - /* 2 REG_SND_PTCL_CTRL_8197F */ #define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F 24 #define BIT_MASK_NDP_RX_STANDBY_TIMER_8197F 0xff -#define BIT_NDP_RX_STANDBY_TIMER_8197F(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8197F) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) -#define BITS_NDP_RX_STANDBY_TIMER_8197F (BIT_MASK_NDP_RX_STANDBY_TIMER_8197F << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) -#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8197F)) -#define BIT_GET_NDP_RX_STANDBY_TIMER_8197F(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) & BIT_MASK_NDP_RX_STANDBY_TIMER_8197F) -#define BIT_SET_NDP_RX_STANDBY_TIMER_8197F(x, v) (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) | BIT_NDP_RX_STANDBY_TIMER_8197F(v)) - +#define BIT_NDP_RX_STANDBY_TIMER_8197F(x) \ + (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8197F) \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) +#define BITS_NDP_RX_STANDBY_TIMER_8197F \ + (BIT_MASK_NDP_RX_STANDBY_TIMER_8197F \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) \ + ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8197F)) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8197F(x) \ + (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) & \ + BIT_MASK_NDP_RX_STANDBY_TIMER_8197F) +#define BIT_SET_NDP_RX_STANDBY_TIMER_8197F(x, v) \ + (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) | \ + BIT_NDP_RX_STANDBY_TIMER_8197F(v)) #define BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F 16 #define BIT_MASK_CSI_RPT_OFFSET_HT_8197F 0xff -#define BIT_CSI_RPT_OFFSET_HT_8197F(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8197F) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) -#define BITS_CSI_RPT_OFFSET_HT_8197F (BIT_MASK_CSI_RPT_OFFSET_HT_8197F << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) -#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT_8197F)) -#define BIT_GET_CSI_RPT_OFFSET_HT_8197F(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) & BIT_MASK_CSI_RPT_OFFSET_HT_8197F) -#define BIT_SET_CSI_RPT_OFFSET_HT_8197F(x, v) (BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) | BIT_CSI_RPT_OFFSET_HT_8197F(v)) - +#define BIT_CSI_RPT_OFFSET_HT_8197F(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8197F) \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) +#define BITS_CSI_RPT_OFFSET_HT_8197F \ + (BIT_MASK_CSI_RPT_OFFSET_HT_8197F << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) \ + ((x) & (~BITS_CSI_RPT_OFFSET_HT_8197F)) +#define BIT_GET_CSI_RPT_OFFSET_HT_8197F(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) & \ + BIT_MASK_CSI_RPT_OFFSET_HT_8197F) +#define BIT_SET_CSI_RPT_OFFSET_HT_8197F(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) | BIT_CSI_RPT_OFFSET_HT_8197F(v)) #define BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F 8 #define BIT_MASK_CSI_RPT_OFFSET_VHT_8197F 0xff -#define BIT_CSI_RPT_OFFSET_VHT_8197F(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_8197F) << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) -#define BITS_CSI_RPT_OFFSET_VHT_8197F (BIT_MASK_CSI_RPT_OFFSET_VHT_8197F << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) -#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT_8197F)) -#define BIT_GET_CSI_RPT_OFFSET_VHT_8197F(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) & BIT_MASK_CSI_RPT_OFFSET_VHT_8197F) -#define BIT_SET_CSI_RPT_OFFSET_VHT_8197F(x, v) (BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) | BIT_CSI_RPT_OFFSET_VHT_8197F(v)) +#define BIT_CSI_RPT_OFFSET_VHT_8197F(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_8197F) \ + << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) +#define BITS_CSI_RPT_OFFSET_VHT_8197F \ + (BIT_MASK_CSI_RPT_OFFSET_VHT_8197F \ + << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) +#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) \ + ((x) & (~BITS_CSI_RPT_OFFSET_VHT_8197F)) +#define BIT_GET_CSI_RPT_OFFSET_VHT_8197F(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) & \ + BIT_MASK_CSI_RPT_OFFSET_VHT_8197F) +#define BIT_SET_CSI_RPT_OFFSET_VHT_8197F(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) | \ + BIT_CSI_RPT_OFFSET_VHT_8197F(v)) #define BIT_R_WMAC_USE_NSTS_8197F BIT(7) #define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8197F BIT(6) @@ -12211,30 +16061,54 @@ #define BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F 6 #define BIT_MASK_R_WMAC_NSARP_MODEN_8197F 0x3 -#define BIT_R_WMAC_NSARP_MODEN_8197F(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8197F) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) -#define BITS_R_WMAC_NSARP_MODEN_8197F (BIT_MASK_R_WMAC_NSARP_MODEN_8197F << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) -#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) ((x) & (~BITS_R_WMAC_NSARP_MODEN_8197F)) -#define BIT_GET_R_WMAC_NSARP_MODEN_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) & BIT_MASK_R_WMAC_NSARP_MODEN_8197F) -#define BIT_SET_R_WMAC_NSARP_MODEN_8197F(x, v) (BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) | BIT_R_WMAC_NSARP_MODEN_8197F(v)) - +#define BIT_R_WMAC_NSARP_MODEN_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8197F) \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) +#define BITS_R_WMAC_NSARP_MODEN_8197F \ + (BIT_MASK_R_WMAC_NSARP_MODEN_8197F \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) \ + ((x) & (~BITS_R_WMAC_NSARP_MODEN_8197F)) +#define BIT_GET_R_WMAC_NSARP_MODEN_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) & \ + BIT_MASK_R_WMAC_NSARP_MODEN_8197F) +#define BIT_SET_R_WMAC_NSARP_MODEN_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) | \ + BIT_R_WMAC_NSARP_MODEN_8197F(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F 4 #define BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F 0x3 -#define BIT_R_WMAC_NSARP_RSPFTP_8197F(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) -#define BITS_R_WMAC_NSARP_RSPFTP_8197F (BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) -#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8197F)) -#define BIT_GET_R_WMAC_NSARP_RSPFTP_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F) -#define BIT_SET_R_WMAC_NSARP_RSPFTP_8197F(x, v) (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) | BIT_R_WMAC_NSARP_RSPFTP_8197F(v)) - +#define BIT_R_WMAC_NSARP_RSPFTP_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) +#define BITS_R_WMAC_NSARP_RSPFTP_8197F \ + (BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8197F)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) & \ + BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F) +#define BIT_SET_R_WMAC_NSARP_RSPFTP_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) | \ + BIT_R_WMAC_NSARP_RSPFTP_8197F(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F 0 #define BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F 0xf -#define BIT_R_WMAC_NSARP_RSPSEC_8197F(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) -#define BITS_R_WMAC_NSARP_RSPSEC_8197F (BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) -#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8197F)) -#define BIT_GET_R_WMAC_NSARP_RSPSEC_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F) -#define BIT_SET_R_WMAC_NSARP_RSPSEC_8197F(x, v) (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) | BIT_R_WMAC_NSARP_RSPSEC_8197F(v)) - +#define BIT_R_WMAC_NSARP_RSPSEC_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) +#define BITS_R_WMAC_NSARP_RSPSEC_8197F \ + (BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8197F)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) & \ + BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F) +#define BIT_SET_R_WMAC_NSARP_RSPSEC_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) | \ + BIT_R_WMAC_NSARP_RSPSEC_8197F(v)) /* 2 REG_NS_ARP_INFO_8197F */ @@ -12250,21 +16124,37 @@ #define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F 4 #define BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F 0xf -#define BIT_R_WMAC_CTX_SUBTYPE_8197F(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) -#define BITS_R_WMAC_CTX_SUBTYPE_8197F (BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) -#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8197F)) -#define BIT_GET_R_WMAC_CTX_SUBTYPE_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F) -#define BIT_SET_R_WMAC_CTX_SUBTYPE_8197F(x, v) (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) | BIT_R_WMAC_CTX_SUBTYPE_8197F(v)) - +#define BIT_R_WMAC_CTX_SUBTYPE_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F) \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) +#define BITS_R_WMAC_CTX_SUBTYPE_8197F \ + (BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) \ + ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8197F)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) & \ + BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F) +#define BIT_SET_R_WMAC_CTX_SUBTYPE_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) | \ + BIT_R_WMAC_CTX_SUBTYPE_8197F(v)) #define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F 0 #define BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F 0xf -#define BIT_R_WMAC_RTX_SUBTYPE_8197F(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) -#define BITS_R_WMAC_RTX_SUBTYPE_8197F (BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) -#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8197F)) -#define BIT_GET_R_WMAC_RTX_SUBTYPE_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F) -#define BIT_SET_R_WMAC_RTX_SUBTYPE_8197F(x, v) (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) | BIT_R_WMAC_RTX_SUBTYPE_8197F(v)) - +#define BIT_R_WMAC_RTX_SUBTYPE_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F) \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) +#define BITS_R_WMAC_RTX_SUBTYPE_8197F \ + (BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) \ + ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8197F)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) & \ + BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F) +#define BIT_SET_R_WMAC_RTX_SUBTYPE_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) | \ + BIT_R_WMAC_RTX_SUBTYPE_8197F(v)) /* 2 REG_WMAC_SWAES_CFG_8197F */ @@ -12274,12 +16164,14 @@ #define BIT_SHIFT_TIMER_8197F 0 #define BIT_MASK_TIMER_8197F 0xff -#define BIT_TIMER_8197F(x) (((x) & BIT_MASK_TIMER_8197F) << BIT_SHIFT_TIMER_8197F) +#define BIT_TIMER_8197F(x) \ + (((x) & BIT_MASK_TIMER_8197F) << BIT_SHIFT_TIMER_8197F) #define BITS_TIMER_8197F (BIT_MASK_TIMER_8197F << BIT_SHIFT_TIMER_8197F) #define BIT_CLEAR_TIMER_8197F(x) ((x) & (~BITS_TIMER_8197F)) -#define BIT_GET_TIMER_8197F(x) (((x) >> BIT_SHIFT_TIMER_8197F) & BIT_MASK_TIMER_8197F) -#define BIT_SET_TIMER_8197F(x, v) (BIT_CLEAR_TIMER_8197F(x) | BIT_TIMER_8197F(v)) - +#define BIT_GET_TIMER_8197F(x) \ + (((x) >> BIT_SHIFT_TIMER_8197F) & BIT_MASK_TIMER_8197F) +#define BIT_SET_TIMER_8197F(x, v) \ + (BIT_CLEAR_TIMER_8197F(x) | BIT_TIMER_8197F(v)) /* 2 REG_BT_COEX_8197F */ #define BIT_R_GNT_BT_RFC_SW_8197F BIT(12) @@ -12290,12 +16182,15 @@ #define BIT_SHIFT_R_BT_CNT_THR_8197F 0 #define BIT_MASK_R_BT_CNT_THR_8197F 0xff -#define BIT_R_BT_CNT_THR_8197F(x) (((x) & BIT_MASK_R_BT_CNT_THR_8197F) << BIT_SHIFT_R_BT_CNT_THR_8197F) -#define BITS_R_BT_CNT_THR_8197F (BIT_MASK_R_BT_CNT_THR_8197F << BIT_SHIFT_R_BT_CNT_THR_8197F) +#define BIT_R_BT_CNT_THR_8197F(x) \ + (((x) & BIT_MASK_R_BT_CNT_THR_8197F) << BIT_SHIFT_R_BT_CNT_THR_8197F) +#define BITS_R_BT_CNT_THR_8197F \ + (BIT_MASK_R_BT_CNT_THR_8197F << BIT_SHIFT_R_BT_CNT_THR_8197F) #define BIT_CLEAR_R_BT_CNT_THR_8197F(x) ((x) & (~BITS_R_BT_CNT_THR_8197F)) -#define BIT_GET_R_BT_CNT_THR_8197F(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8197F) & BIT_MASK_R_BT_CNT_THR_8197F) -#define BIT_SET_R_BT_CNT_THR_8197F(x, v) (BIT_CLEAR_R_BT_CNT_THR_8197F(x) | BIT_R_BT_CNT_THR_8197F(v)) - +#define BIT_GET_R_BT_CNT_THR_8197F(x) \ + (((x) >> BIT_SHIFT_R_BT_CNT_THR_8197F) & BIT_MASK_R_BT_CNT_THR_8197F) +#define BIT_SET_R_BT_CNT_THR_8197F(x, v) \ + (BIT_CLEAR_R_BT_CNT_THR_8197F(x) | BIT_R_BT_CNT_THR_8197F(v)) /* 2 REG_WLAN_ACT_MASK_CTRL_8197F */ #define BIT_WLRX_TER_BY_CTL_8197F BIT(43) @@ -12307,49 +16202,75 @@ #define BIT_SHIFT_RXMYRTS_NAV_V1_8197F 8 #define BIT_MASK_RXMYRTS_NAV_V1_8197F 0xff -#define BIT_RXMYRTS_NAV_V1_8197F(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8197F) << BIT_SHIFT_RXMYRTS_NAV_V1_8197F) -#define BITS_RXMYRTS_NAV_V1_8197F (BIT_MASK_RXMYRTS_NAV_V1_8197F << BIT_SHIFT_RXMYRTS_NAV_V1_8197F) +#define BIT_RXMYRTS_NAV_V1_8197F(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_V1_8197F) \ + << BIT_SHIFT_RXMYRTS_NAV_V1_8197F) +#define BITS_RXMYRTS_NAV_V1_8197F \ + (BIT_MASK_RXMYRTS_NAV_V1_8197F << BIT_SHIFT_RXMYRTS_NAV_V1_8197F) #define BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8197F)) -#define BIT_GET_RXMYRTS_NAV_V1_8197F(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8197F) & BIT_MASK_RXMYRTS_NAV_V1_8197F) -#define BIT_SET_RXMYRTS_NAV_V1_8197F(x, v) (BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) | BIT_RXMYRTS_NAV_V1_8197F(v)) - +#define BIT_GET_RXMYRTS_NAV_V1_8197F(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8197F) & \ + BIT_MASK_RXMYRTS_NAV_V1_8197F) +#define BIT_SET_RXMYRTS_NAV_V1_8197F(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) | BIT_RXMYRTS_NAV_V1_8197F(v)) #define BIT_SHIFT_RTSRST_V1_8197F 0 #define BIT_MASK_RTSRST_V1_8197F 0xff -#define BIT_RTSRST_V1_8197F(x) (((x) & BIT_MASK_RTSRST_V1_8197F) << BIT_SHIFT_RTSRST_V1_8197F) -#define BITS_RTSRST_V1_8197F (BIT_MASK_RTSRST_V1_8197F << BIT_SHIFT_RTSRST_V1_8197F) +#define BIT_RTSRST_V1_8197F(x) \ + (((x) & BIT_MASK_RTSRST_V1_8197F) << BIT_SHIFT_RTSRST_V1_8197F) +#define BITS_RTSRST_V1_8197F \ + (BIT_MASK_RTSRST_V1_8197F << BIT_SHIFT_RTSRST_V1_8197F) #define BIT_CLEAR_RTSRST_V1_8197F(x) ((x) & (~BITS_RTSRST_V1_8197F)) -#define BIT_GET_RTSRST_V1_8197F(x) (((x) >> BIT_SHIFT_RTSRST_V1_8197F) & BIT_MASK_RTSRST_V1_8197F) -#define BIT_SET_RTSRST_V1_8197F(x, v) (BIT_CLEAR_RTSRST_V1_8197F(x) | BIT_RTSRST_V1_8197F(v)) - +#define BIT_GET_RTSRST_V1_8197F(x) \ + (((x) >> BIT_SHIFT_RTSRST_V1_8197F) & BIT_MASK_RTSRST_V1_8197F) +#define BIT_SET_RTSRST_V1_8197F(x, v) \ + (BIT_CLEAR_RTSRST_V1_8197F(x) | BIT_RTSRST_V1_8197F(v)) /* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8197F */ #define BIT_SHIFT_BT_STAT_DELAY_8197F 12 #define BIT_MASK_BT_STAT_DELAY_8197F 0xf -#define BIT_BT_STAT_DELAY_8197F(x) (((x) & BIT_MASK_BT_STAT_DELAY_8197F) << BIT_SHIFT_BT_STAT_DELAY_8197F) -#define BITS_BT_STAT_DELAY_8197F (BIT_MASK_BT_STAT_DELAY_8197F << BIT_SHIFT_BT_STAT_DELAY_8197F) +#define BIT_BT_STAT_DELAY_8197F(x) \ + (((x) & BIT_MASK_BT_STAT_DELAY_8197F) << BIT_SHIFT_BT_STAT_DELAY_8197F) +#define BITS_BT_STAT_DELAY_8197F \ + (BIT_MASK_BT_STAT_DELAY_8197F << BIT_SHIFT_BT_STAT_DELAY_8197F) #define BIT_CLEAR_BT_STAT_DELAY_8197F(x) ((x) & (~BITS_BT_STAT_DELAY_8197F)) -#define BIT_GET_BT_STAT_DELAY_8197F(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8197F) & BIT_MASK_BT_STAT_DELAY_8197F) -#define BIT_SET_BT_STAT_DELAY_8197F(x, v) (BIT_CLEAR_BT_STAT_DELAY_8197F(x) | BIT_BT_STAT_DELAY_8197F(v)) - +#define BIT_GET_BT_STAT_DELAY_8197F(x) \ + (((x) >> BIT_SHIFT_BT_STAT_DELAY_8197F) & BIT_MASK_BT_STAT_DELAY_8197F) +#define BIT_SET_BT_STAT_DELAY_8197F(x, v) \ + (BIT_CLEAR_BT_STAT_DELAY_8197F(x) | BIT_BT_STAT_DELAY_8197F(v)) #define BIT_SHIFT_BT_TRX_INIT_DETECT_8197F 8 #define BIT_MASK_BT_TRX_INIT_DETECT_8197F 0xf -#define BIT_BT_TRX_INIT_DETECT_8197F(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8197F) << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) -#define BITS_BT_TRX_INIT_DETECT_8197F (BIT_MASK_BT_TRX_INIT_DETECT_8197F << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) -#define BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) ((x) & (~BITS_BT_TRX_INIT_DETECT_8197F)) -#define BIT_GET_BT_TRX_INIT_DETECT_8197F(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) & BIT_MASK_BT_TRX_INIT_DETECT_8197F) -#define BIT_SET_BT_TRX_INIT_DETECT_8197F(x, v) (BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) | BIT_BT_TRX_INIT_DETECT_8197F(v)) - +#define BIT_BT_TRX_INIT_DETECT_8197F(x) \ + (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8197F) \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) +#define BITS_BT_TRX_INIT_DETECT_8197F \ + (BIT_MASK_BT_TRX_INIT_DETECT_8197F \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) +#define BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) \ + ((x) & (~BITS_BT_TRX_INIT_DETECT_8197F)) +#define BIT_GET_BT_TRX_INIT_DETECT_8197F(x) \ + (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) & \ + BIT_MASK_BT_TRX_INIT_DETECT_8197F) +#define BIT_SET_BT_TRX_INIT_DETECT_8197F(x, v) \ + (BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) | \ + BIT_BT_TRX_INIT_DETECT_8197F(v)) #define BIT_SHIFT_BT_PRI_DETECT_TO_8197F 4 #define BIT_MASK_BT_PRI_DETECT_TO_8197F 0xf -#define BIT_BT_PRI_DETECT_TO_8197F(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8197F) << BIT_SHIFT_BT_PRI_DETECT_TO_8197F) -#define BITS_BT_PRI_DETECT_TO_8197F (BIT_MASK_BT_PRI_DETECT_TO_8197F << BIT_SHIFT_BT_PRI_DETECT_TO_8197F) -#define BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) ((x) & (~BITS_BT_PRI_DETECT_TO_8197F)) -#define BIT_GET_BT_PRI_DETECT_TO_8197F(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8197F) & BIT_MASK_BT_PRI_DETECT_TO_8197F) -#define BIT_SET_BT_PRI_DETECT_TO_8197F(x, v) (BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) | BIT_BT_PRI_DETECT_TO_8197F(v)) +#define BIT_BT_PRI_DETECT_TO_8197F(x) \ + (((x) & BIT_MASK_BT_PRI_DETECT_TO_8197F) \ + << BIT_SHIFT_BT_PRI_DETECT_TO_8197F) +#define BITS_BT_PRI_DETECT_TO_8197F \ + (BIT_MASK_BT_PRI_DETECT_TO_8197F << BIT_SHIFT_BT_PRI_DETECT_TO_8197F) +#define BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) \ + ((x) & (~BITS_BT_PRI_DETECT_TO_8197F)) +#define BIT_GET_BT_PRI_DETECT_TO_8197F(x) \ + (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8197F) & \ + BIT_MASK_BT_PRI_DETECT_TO_8197F) +#define BIT_SET_BT_PRI_DETECT_TO_8197F(x, v) \ + (BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) | BIT_BT_PRI_DETECT_TO_8197F(v)) #define BIT_R_GRANTALL_WLMASK_8197F BIT(3) #define BIT_STATIS_BT_EN_8197F BIT(2) @@ -12360,67 +16281,99 @@ #define BIT_SHIFT_STATIS_BT_LO_RX_8197F (48 & CPU_OPT_WIDTH) #define BIT_MASK_STATIS_BT_LO_RX_8197F 0xffff -#define BIT_STATIS_BT_LO_RX_8197F(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_8197F) << BIT_SHIFT_STATIS_BT_LO_RX_8197F) -#define BITS_STATIS_BT_LO_RX_8197F (BIT_MASK_STATIS_BT_LO_RX_8197F << BIT_SHIFT_STATIS_BT_LO_RX_8197F) +#define BIT_STATIS_BT_LO_RX_8197F(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX_8197F) \ + << BIT_SHIFT_STATIS_BT_LO_RX_8197F) +#define BITS_STATIS_BT_LO_RX_8197F \ + (BIT_MASK_STATIS_BT_LO_RX_8197F << BIT_SHIFT_STATIS_BT_LO_RX_8197F) #define BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) ((x) & (~BITS_STATIS_BT_LO_RX_8197F)) -#define BIT_GET_STATIS_BT_LO_RX_8197F(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8197F) & BIT_MASK_STATIS_BT_LO_RX_8197F) -#define BIT_SET_STATIS_BT_LO_RX_8197F(x, v) (BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) | BIT_STATIS_BT_LO_RX_8197F(v)) - +#define BIT_GET_STATIS_BT_LO_RX_8197F(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8197F) & \ + BIT_MASK_STATIS_BT_LO_RX_8197F) +#define BIT_SET_STATIS_BT_LO_RX_8197F(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) | BIT_STATIS_BT_LO_RX_8197F(v)) #define BIT_SHIFT_STATIS_BT_LO_TX_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_STATIS_BT_LO_TX_8197F 0xffff -#define BIT_STATIS_BT_LO_TX_8197F(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_8197F) << BIT_SHIFT_STATIS_BT_LO_TX_8197F) -#define BITS_STATIS_BT_LO_TX_8197F (BIT_MASK_STATIS_BT_LO_TX_8197F << BIT_SHIFT_STATIS_BT_LO_TX_8197F) +#define BIT_STATIS_BT_LO_TX_8197F(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX_8197F) \ + << BIT_SHIFT_STATIS_BT_LO_TX_8197F) +#define BITS_STATIS_BT_LO_TX_8197F \ + (BIT_MASK_STATIS_BT_LO_TX_8197F << BIT_SHIFT_STATIS_BT_LO_TX_8197F) #define BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) ((x) & (~BITS_STATIS_BT_LO_TX_8197F)) -#define BIT_GET_STATIS_BT_LO_TX_8197F(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8197F) & BIT_MASK_STATIS_BT_LO_TX_8197F) -#define BIT_SET_STATIS_BT_LO_TX_8197F(x, v) (BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) | BIT_STATIS_BT_LO_TX_8197F(v)) - +#define BIT_GET_STATIS_BT_LO_TX_8197F(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8197F) & \ + BIT_MASK_STATIS_BT_LO_TX_8197F) +#define BIT_SET_STATIS_BT_LO_TX_8197F(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) | BIT_STATIS_BT_LO_TX_8197F(v)) #define BIT_SHIFT_STATIS_BT_HI_RX_8197F 16 #define BIT_MASK_STATIS_BT_HI_RX_8197F 0xffff -#define BIT_STATIS_BT_HI_RX_8197F(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8197F) << BIT_SHIFT_STATIS_BT_HI_RX_8197F) -#define BITS_STATIS_BT_HI_RX_8197F (BIT_MASK_STATIS_BT_HI_RX_8197F << BIT_SHIFT_STATIS_BT_HI_RX_8197F) +#define BIT_STATIS_BT_HI_RX_8197F(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_RX_8197F) \ + << BIT_SHIFT_STATIS_BT_HI_RX_8197F) +#define BITS_STATIS_BT_HI_RX_8197F \ + (BIT_MASK_STATIS_BT_HI_RX_8197F << BIT_SHIFT_STATIS_BT_HI_RX_8197F) #define BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) ((x) & (~BITS_STATIS_BT_HI_RX_8197F)) -#define BIT_GET_STATIS_BT_HI_RX_8197F(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8197F) & BIT_MASK_STATIS_BT_HI_RX_8197F) -#define BIT_SET_STATIS_BT_HI_RX_8197F(x, v) (BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) | BIT_STATIS_BT_HI_RX_8197F(v)) - +#define BIT_GET_STATIS_BT_HI_RX_8197F(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8197F) & \ + BIT_MASK_STATIS_BT_HI_RX_8197F) +#define BIT_SET_STATIS_BT_HI_RX_8197F(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) | BIT_STATIS_BT_HI_RX_8197F(v)) #define BIT_SHIFT_STATIS_BT_HI_TX_8197F 0 #define BIT_MASK_STATIS_BT_HI_TX_8197F 0xffff -#define BIT_STATIS_BT_HI_TX_8197F(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8197F) << BIT_SHIFT_STATIS_BT_HI_TX_8197F) -#define BITS_STATIS_BT_HI_TX_8197F (BIT_MASK_STATIS_BT_HI_TX_8197F << BIT_SHIFT_STATIS_BT_HI_TX_8197F) +#define BIT_STATIS_BT_HI_TX_8197F(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_TX_8197F) \ + << BIT_SHIFT_STATIS_BT_HI_TX_8197F) +#define BITS_STATIS_BT_HI_TX_8197F \ + (BIT_MASK_STATIS_BT_HI_TX_8197F << BIT_SHIFT_STATIS_BT_HI_TX_8197F) #define BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) ((x) & (~BITS_STATIS_BT_HI_TX_8197F)) -#define BIT_GET_STATIS_BT_HI_TX_8197F(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8197F) & BIT_MASK_STATIS_BT_HI_TX_8197F) -#define BIT_SET_STATIS_BT_HI_TX_8197F(x, v) (BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) | BIT_STATIS_BT_HI_TX_8197F(v)) - +#define BIT_GET_STATIS_BT_HI_TX_8197F(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8197F) & \ + BIT_MASK_STATIS_BT_HI_TX_8197F) +#define BIT_SET_STATIS_BT_HI_TX_8197F(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) | BIT_STATIS_BT_HI_TX_8197F(v)) /* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8197F */ #define BIT_SHIFT_R_BT_CMD_RPT_8197F 16 #define BIT_MASK_R_BT_CMD_RPT_8197F 0xffff -#define BIT_R_BT_CMD_RPT_8197F(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8197F) << BIT_SHIFT_R_BT_CMD_RPT_8197F) -#define BITS_R_BT_CMD_RPT_8197F (BIT_MASK_R_BT_CMD_RPT_8197F << BIT_SHIFT_R_BT_CMD_RPT_8197F) +#define BIT_R_BT_CMD_RPT_8197F(x) \ + (((x) & BIT_MASK_R_BT_CMD_RPT_8197F) << BIT_SHIFT_R_BT_CMD_RPT_8197F) +#define BITS_R_BT_CMD_RPT_8197F \ + (BIT_MASK_R_BT_CMD_RPT_8197F << BIT_SHIFT_R_BT_CMD_RPT_8197F) #define BIT_CLEAR_R_BT_CMD_RPT_8197F(x) ((x) & (~BITS_R_BT_CMD_RPT_8197F)) -#define BIT_GET_R_BT_CMD_RPT_8197F(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8197F) & BIT_MASK_R_BT_CMD_RPT_8197F) -#define BIT_SET_R_BT_CMD_RPT_8197F(x, v) (BIT_CLEAR_R_BT_CMD_RPT_8197F(x) | BIT_R_BT_CMD_RPT_8197F(v)) - +#define BIT_GET_R_BT_CMD_RPT_8197F(x) \ + (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8197F) & BIT_MASK_R_BT_CMD_RPT_8197F) +#define BIT_SET_R_BT_CMD_RPT_8197F(x, v) \ + (BIT_CLEAR_R_BT_CMD_RPT_8197F(x) | BIT_R_BT_CMD_RPT_8197F(v)) #define BIT_SHIFT_R_RPT_FROM_BT_8197F 8 #define BIT_MASK_R_RPT_FROM_BT_8197F 0xff -#define BIT_R_RPT_FROM_BT_8197F(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8197F) << BIT_SHIFT_R_RPT_FROM_BT_8197F) -#define BITS_R_RPT_FROM_BT_8197F (BIT_MASK_R_RPT_FROM_BT_8197F << BIT_SHIFT_R_RPT_FROM_BT_8197F) +#define BIT_R_RPT_FROM_BT_8197F(x) \ + (((x) & BIT_MASK_R_RPT_FROM_BT_8197F) << BIT_SHIFT_R_RPT_FROM_BT_8197F) +#define BITS_R_RPT_FROM_BT_8197F \ + (BIT_MASK_R_RPT_FROM_BT_8197F << BIT_SHIFT_R_RPT_FROM_BT_8197F) #define BIT_CLEAR_R_RPT_FROM_BT_8197F(x) ((x) & (~BITS_R_RPT_FROM_BT_8197F)) -#define BIT_GET_R_RPT_FROM_BT_8197F(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8197F) & BIT_MASK_R_RPT_FROM_BT_8197F) -#define BIT_SET_R_RPT_FROM_BT_8197F(x, v) (BIT_CLEAR_R_RPT_FROM_BT_8197F(x) | BIT_R_RPT_FROM_BT_8197F(v)) - +#define BIT_GET_R_RPT_FROM_BT_8197F(x) \ + (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8197F) & BIT_MASK_R_RPT_FROM_BT_8197F) +#define BIT_SET_R_RPT_FROM_BT_8197F(x, v) \ + (BIT_CLEAR_R_RPT_FROM_BT_8197F(x) | BIT_R_RPT_FROM_BT_8197F(v)) #define BIT_SHIFT_BT_HID_ISR_SET_8197F 6 #define BIT_MASK_BT_HID_ISR_SET_8197F 0x3 -#define BIT_BT_HID_ISR_SET_8197F(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8197F) << BIT_SHIFT_BT_HID_ISR_SET_8197F) -#define BITS_BT_HID_ISR_SET_8197F (BIT_MASK_BT_HID_ISR_SET_8197F << BIT_SHIFT_BT_HID_ISR_SET_8197F) +#define BIT_BT_HID_ISR_SET_8197F(x) \ + (((x) & BIT_MASK_BT_HID_ISR_SET_8197F) \ + << BIT_SHIFT_BT_HID_ISR_SET_8197F) +#define BITS_BT_HID_ISR_SET_8197F \ + (BIT_MASK_BT_HID_ISR_SET_8197F << BIT_SHIFT_BT_HID_ISR_SET_8197F) #define BIT_CLEAR_BT_HID_ISR_SET_8197F(x) ((x) & (~BITS_BT_HID_ISR_SET_8197F)) -#define BIT_GET_BT_HID_ISR_SET_8197F(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8197F) & BIT_MASK_BT_HID_ISR_SET_8197F) -#define BIT_SET_BT_HID_ISR_SET_8197F(x, v) (BIT_CLEAR_BT_HID_ISR_SET_8197F(x) | BIT_BT_HID_ISR_SET_8197F(v)) +#define BIT_GET_BT_HID_ISR_SET_8197F(x) \ + (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8197F) & \ + BIT_MASK_BT_HID_ISR_SET_8197F) +#define BIT_SET_BT_HID_ISR_SET_8197F(x, v) \ + (BIT_CLEAR_BT_HID_ISR_SET_8197F(x) | BIT_BT_HID_ISR_SET_8197F(v)) #define BIT_TDMA_BT_START_NOTIFY_8197F BIT(5) #define BIT_ENABLE_TDMA_FW_MODE_8197F BIT(4) @@ -12433,39 +16386,54 @@ #define BIT_SHIFT_BT_PROFILE_8197F 24 #define BIT_MASK_BT_PROFILE_8197F 0xff -#define BIT_BT_PROFILE_8197F(x) (((x) & BIT_MASK_BT_PROFILE_8197F) << BIT_SHIFT_BT_PROFILE_8197F) -#define BITS_BT_PROFILE_8197F (BIT_MASK_BT_PROFILE_8197F << BIT_SHIFT_BT_PROFILE_8197F) +#define BIT_BT_PROFILE_8197F(x) \ + (((x) & BIT_MASK_BT_PROFILE_8197F) << BIT_SHIFT_BT_PROFILE_8197F) +#define BITS_BT_PROFILE_8197F \ + (BIT_MASK_BT_PROFILE_8197F << BIT_SHIFT_BT_PROFILE_8197F) #define BIT_CLEAR_BT_PROFILE_8197F(x) ((x) & (~BITS_BT_PROFILE_8197F)) -#define BIT_GET_BT_PROFILE_8197F(x) (((x) >> BIT_SHIFT_BT_PROFILE_8197F) & BIT_MASK_BT_PROFILE_8197F) -#define BIT_SET_BT_PROFILE_8197F(x, v) (BIT_CLEAR_BT_PROFILE_8197F(x) | BIT_BT_PROFILE_8197F(v)) - +#define BIT_GET_BT_PROFILE_8197F(x) \ + (((x) >> BIT_SHIFT_BT_PROFILE_8197F) & BIT_MASK_BT_PROFILE_8197F) +#define BIT_SET_BT_PROFILE_8197F(x, v) \ + (BIT_CLEAR_BT_PROFILE_8197F(x) | BIT_BT_PROFILE_8197F(v)) #define BIT_SHIFT_BT_POWER_8197F 16 #define BIT_MASK_BT_POWER_8197F 0xff -#define BIT_BT_POWER_8197F(x) (((x) & BIT_MASK_BT_POWER_8197F) << BIT_SHIFT_BT_POWER_8197F) -#define BITS_BT_POWER_8197F (BIT_MASK_BT_POWER_8197F << BIT_SHIFT_BT_POWER_8197F) +#define BIT_BT_POWER_8197F(x) \ + (((x) & BIT_MASK_BT_POWER_8197F) << BIT_SHIFT_BT_POWER_8197F) +#define BITS_BT_POWER_8197F \ + (BIT_MASK_BT_POWER_8197F << BIT_SHIFT_BT_POWER_8197F) #define BIT_CLEAR_BT_POWER_8197F(x) ((x) & (~BITS_BT_POWER_8197F)) -#define BIT_GET_BT_POWER_8197F(x) (((x) >> BIT_SHIFT_BT_POWER_8197F) & BIT_MASK_BT_POWER_8197F) -#define BIT_SET_BT_POWER_8197F(x, v) (BIT_CLEAR_BT_POWER_8197F(x) | BIT_BT_POWER_8197F(v)) - +#define BIT_GET_BT_POWER_8197F(x) \ + (((x) >> BIT_SHIFT_BT_POWER_8197F) & BIT_MASK_BT_POWER_8197F) +#define BIT_SET_BT_POWER_8197F(x, v) \ + (BIT_CLEAR_BT_POWER_8197F(x) | BIT_BT_POWER_8197F(v)) #define BIT_SHIFT_BT_PREDECT_STATUS_8197F 8 #define BIT_MASK_BT_PREDECT_STATUS_8197F 0xff -#define BIT_BT_PREDECT_STATUS_8197F(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8197F) << BIT_SHIFT_BT_PREDECT_STATUS_8197F) -#define BITS_BT_PREDECT_STATUS_8197F (BIT_MASK_BT_PREDECT_STATUS_8197F << BIT_SHIFT_BT_PREDECT_STATUS_8197F) -#define BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) ((x) & (~BITS_BT_PREDECT_STATUS_8197F)) -#define BIT_GET_BT_PREDECT_STATUS_8197F(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8197F) & BIT_MASK_BT_PREDECT_STATUS_8197F) -#define BIT_SET_BT_PREDECT_STATUS_8197F(x, v) (BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) | BIT_BT_PREDECT_STATUS_8197F(v)) - +#define BIT_BT_PREDECT_STATUS_8197F(x) \ + (((x) & BIT_MASK_BT_PREDECT_STATUS_8197F) \ + << BIT_SHIFT_BT_PREDECT_STATUS_8197F) +#define BITS_BT_PREDECT_STATUS_8197F \ + (BIT_MASK_BT_PREDECT_STATUS_8197F << BIT_SHIFT_BT_PREDECT_STATUS_8197F) +#define BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) \ + ((x) & (~BITS_BT_PREDECT_STATUS_8197F)) +#define BIT_GET_BT_PREDECT_STATUS_8197F(x) \ + (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8197F) & \ + BIT_MASK_BT_PREDECT_STATUS_8197F) +#define BIT_SET_BT_PREDECT_STATUS_8197F(x, v) \ + (BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) | BIT_BT_PREDECT_STATUS_8197F(v)) #define BIT_SHIFT_BT_CMD_INFO_8197F 0 #define BIT_MASK_BT_CMD_INFO_8197F 0xff -#define BIT_BT_CMD_INFO_8197F(x) (((x) & BIT_MASK_BT_CMD_INFO_8197F) << BIT_SHIFT_BT_CMD_INFO_8197F) -#define BITS_BT_CMD_INFO_8197F (BIT_MASK_BT_CMD_INFO_8197F << BIT_SHIFT_BT_CMD_INFO_8197F) +#define BIT_BT_CMD_INFO_8197F(x) \ + (((x) & BIT_MASK_BT_CMD_INFO_8197F) << BIT_SHIFT_BT_CMD_INFO_8197F) +#define BITS_BT_CMD_INFO_8197F \ + (BIT_MASK_BT_CMD_INFO_8197F << BIT_SHIFT_BT_CMD_INFO_8197F) #define BIT_CLEAR_BT_CMD_INFO_8197F(x) ((x) & (~BITS_BT_CMD_INFO_8197F)) -#define BIT_GET_BT_CMD_INFO_8197F(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8197F) & BIT_MASK_BT_CMD_INFO_8197F) -#define BIT_SET_BT_CMD_INFO_8197F(x, v) (BIT_CLEAR_BT_CMD_INFO_8197F(x) | BIT_BT_CMD_INFO_8197F(v)) - +#define BIT_GET_BT_CMD_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_BT_CMD_INFO_8197F) & BIT_MASK_BT_CMD_INFO_8197F) +#define BIT_SET_BT_CMD_INFO_8197F(x, v) \ + (BIT_CLEAR_BT_CMD_INFO_8197F(x) | BIT_BT_CMD_INFO_8197F(v)) /* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8197F */ #define BIT_EN_MAC_NULL_PKT_NOTIFY_8197F BIT(31) @@ -12479,51 +16447,65 @@ #define BIT_SHIFT_WLAN_RPT_DATA_8197F 16 #define BIT_MASK_WLAN_RPT_DATA_8197F 0xff -#define BIT_WLAN_RPT_DATA_8197F(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8197F) << BIT_SHIFT_WLAN_RPT_DATA_8197F) -#define BITS_WLAN_RPT_DATA_8197F (BIT_MASK_WLAN_RPT_DATA_8197F << BIT_SHIFT_WLAN_RPT_DATA_8197F) +#define BIT_WLAN_RPT_DATA_8197F(x) \ + (((x) & BIT_MASK_WLAN_RPT_DATA_8197F) << BIT_SHIFT_WLAN_RPT_DATA_8197F) +#define BITS_WLAN_RPT_DATA_8197F \ + (BIT_MASK_WLAN_RPT_DATA_8197F << BIT_SHIFT_WLAN_RPT_DATA_8197F) #define BIT_CLEAR_WLAN_RPT_DATA_8197F(x) ((x) & (~BITS_WLAN_RPT_DATA_8197F)) -#define BIT_GET_WLAN_RPT_DATA_8197F(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8197F) & BIT_MASK_WLAN_RPT_DATA_8197F) -#define BIT_SET_WLAN_RPT_DATA_8197F(x, v) (BIT_CLEAR_WLAN_RPT_DATA_8197F(x) | BIT_WLAN_RPT_DATA_8197F(v)) - +#define BIT_GET_WLAN_RPT_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8197F) & BIT_MASK_WLAN_RPT_DATA_8197F) +#define BIT_SET_WLAN_RPT_DATA_8197F(x, v) \ + (BIT_CLEAR_WLAN_RPT_DATA_8197F(x) | BIT_WLAN_RPT_DATA_8197F(v)) #define BIT_SHIFT_CMD_ID_8197F 8 #define BIT_MASK_CMD_ID_8197F 0xff -#define BIT_CMD_ID_8197F(x) (((x) & BIT_MASK_CMD_ID_8197F) << BIT_SHIFT_CMD_ID_8197F) +#define BIT_CMD_ID_8197F(x) \ + (((x) & BIT_MASK_CMD_ID_8197F) << BIT_SHIFT_CMD_ID_8197F) #define BITS_CMD_ID_8197F (BIT_MASK_CMD_ID_8197F << BIT_SHIFT_CMD_ID_8197F) #define BIT_CLEAR_CMD_ID_8197F(x) ((x) & (~BITS_CMD_ID_8197F)) -#define BIT_GET_CMD_ID_8197F(x) (((x) >> BIT_SHIFT_CMD_ID_8197F) & BIT_MASK_CMD_ID_8197F) -#define BIT_SET_CMD_ID_8197F(x, v) (BIT_CLEAR_CMD_ID_8197F(x) | BIT_CMD_ID_8197F(v)) - +#define BIT_GET_CMD_ID_8197F(x) \ + (((x) >> BIT_SHIFT_CMD_ID_8197F) & BIT_MASK_CMD_ID_8197F) +#define BIT_SET_CMD_ID_8197F(x, v) \ + (BIT_CLEAR_CMD_ID_8197F(x) | BIT_CMD_ID_8197F(v)) #define BIT_SHIFT_BT_DATA_8197F 0 #define BIT_MASK_BT_DATA_8197F 0xff -#define BIT_BT_DATA_8197F(x) (((x) & BIT_MASK_BT_DATA_8197F) << BIT_SHIFT_BT_DATA_8197F) +#define BIT_BT_DATA_8197F(x) \ + (((x) & BIT_MASK_BT_DATA_8197F) << BIT_SHIFT_BT_DATA_8197F) #define BITS_BT_DATA_8197F (BIT_MASK_BT_DATA_8197F << BIT_SHIFT_BT_DATA_8197F) #define BIT_CLEAR_BT_DATA_8197F(x) ((x) & (~BITS_BT_DATA_8197F)) -#define BIT_GET_BT_DATA_8197F(x) (((x) >> BIT_SHIFT_BT_DATA_8197F) & BIT_MASK_BT_DATA_8197F) -#define BIT_SET_BT_DATA_8197F(x, v) (BIT_CLEAR_BT_DATA_8197F(x) | BIT_BT_DATA_8197F(v)) - +#define BIT_GET_BT_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_BT_DATA_8197F) & BIT_MASK_BT_DATA_8197F) +#define BIT_SET_BT_DATA_8197F(x, v) \ + (BIT_CLEAR_BT_DATA_8197F(x) | BIT_BT_DATA_8197F(v)) /* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F */ #define BIT_SHIFT_WLAN_RPT_TO_8197F 0 #define BIT_MASK_WLAN_RPT_TO_8197F 0xff -#define BIT_WLAN_RPT_TO_8197F(x) (((x) & BIT_MASK_WLAN_RPT_TO_8197F) << BIT_SHIFT_WLAN_RPT_TO_8197F) -#define BITS_WLAN_RPT_TO_8197F (BIT_MASK_WLAN_RPT_TO_8197F << BIT_SHIFT_WLAN_RPT_TO_8197F) +#define BIT_WLAN_RPT_TO_8197F(x) \ + (((x) & BIT_MASK_WLAN_RPT_TO_8197F) << BIT_SHIFT_WLAN_RPT_TO_8197F) +#define BITS_WLAN_RPT_TO_8197F \ + (BIT_MASK_WLAN_RPT_TO_8197F << BIT_SHIFT_WLAN_RPT_TO_8197F) #define BIT_CLEAR_WLAN_RPT_TO_8197F(x) ((x) & (~BITS_WLAN_RPT_TO_8197F)) -#define BIT_GET_WLAN_RPT_TO_8197F(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8197F) & BIT_MASK_WLAN_RPT_TO_8197F) -#define BIT_SET_WLAN_RPT_TO_8197F(x, v) (BIT_CLEAR_WLAN_RPT_TO_8197F(x) | BIT_WLAN_RPT_TO_8197F(v)) - +#define BIT_GET_WLAN_RPT_TO_8197F(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_TO_8197F) & BIT_MASK_WLAN_RPT_TO_8197F) +#define BIT_SET_WLAN_RPT_TO_8197F(x, v) \ + (BIT_CLEAR_WLAN_RPT_TO_8197F(x) | BIT_WLAN_RPT_TO_8197F(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F */ #define BIT_SHIFT_ISOLATION_CHK_8197F 1 #define BIT_MASK_ISOLATION_CHK_8197F 0x7fffffffffffffffffffL -#define BIT_ISOLATION_CHK_8197F(x) (((x) & BIT_MASK_ISOLATION_CHK_8197F) << BIT_SHIFT_ISOLATION_CHK_8197F) -#define BITS_ISOLATION_CHK_8197F (BIT_MASK_ISOLATION_CHK_8197F << BIT_SHIFT_ISOLATION_CHK_8197F) +#define BIT_ISOLATION_CHK_8197F(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_8197F) << BIT_SHIFT_ISOLATION_CHK_8197F) +#define BITS_ISOLATION_CHK_8197F \ + (BIT_MASK_ISOLATION_CHK_8197F << BIT_SHIFT_ISOLATION_CHK_8197F) #define BIT_CLEAR_ISOLATION_CHK_8197F(x) ((x) & (~BITS_ISOLATION_CHK_8197F)) -#define BIT_GET_ISOLATION_CHK_8197F(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_8197F) & BIT_MASK_ISOLATION_CHK_8197F) -#define BIT_SET_ISOLATION_CHK_8197F(x, v) (BIT_CLEAR_ISOLATION_CHK_8197F(x) | BIT_ISOLATION_CHK_8197F(v)) +#define BIT_GET_ISOLATION_CHK_8197F(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_8197F) & BIT_MASK_ISOLATION_CHK_8197F) +#define BIT_SET_ISOLATION_CHK_8197F(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_8197F(x) | BIT_ISOLATION_CHK_8197F(v)) #define BIT_ISOLATION_EN_8197F BIT(0) @@ -12541,31 +16523,45 @@ #define BIT_SHIFT_BT_TIME_8197F 6 #define BIT_MASK_BT_TIME_8197F 0x3ffffff -#define BIT_BT_TIME_8197F(x) (((x) & BIT_MASK_BT_TIME_8197F) << BIT_SHIFT_BT_TIME_8197F) +#define BIT_BT_TIME_8197F(x) \ + (((x) & BIT_MASK_BT_TIME_8197F) << BIT_SHIFT_BT_TIME_8197F) #define BITS_BT_TIME_8197F (BIT_MASK_BT_TIME_8197F << BIT_SHIFT_BT_TIME_8197F) #define BIT_CLEAR_BT_TIME_8197F(x) ((x) & (~BITS_BT_TIME_8197F)) -#define BIT_GET_BT_TIME_8197F(x) (((x) >> BIT_SHIFT_BT_TIME_8197F) & BIT_MASK_BT_TIME_8197F) -#define BIT_SET_BT_TIME_8197F(x, v) (BIT_CLEAR_BT_TIME_8197F(x) | BIT_BT_TIME_8197F(v)) - +#define BIT_GET_BT_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_BT_TIME_8197F) & BIT_MASK_BT_TIME_8197F) +#define BIT_SET_BT_TIME_8197F(x, v) \ + (BIT_CLEAR_BT_TIME_8197F(x) | BIT_BT_TIME_8197F(v)) #define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F 0 #define BIT_MASK_BT_RPT_SAMPLE_RATE_8197F 0x3f -#define BIT_BT_RPT_SAMPLE_RATE_8197F(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8197F) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) -#define BITS_BT_RPT_SAMPLE_RATE_8197F (BIT_MASK_BT_RPT_SAMPLE_RATE_8197F << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) -#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8197F)) -#define BIT_GET_BT_RPT_SAMPLE_RATE_8197F(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) & BIT_MASK_BT_RPT_SAMPLE_RATE_8197F) -#define BIT_SET_BT_RPT_SAMPLE_RATE_8197F(x, v) (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) | BIT_BT_RPT_SAMPLE_RATE_8197F(v)) - +#define BIT_BT_RPT_SAMPLE_RATE_8197F(x) \ + (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8197F) \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) +#define BITS_BT_RPT_SAMPLE_RATE_8197F \ + (BIT_MASK_BT_RPT_SAMPLE_RATE_8197F \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) \ + ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8197F)) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8197F(x) \ + (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) & \ + BIT_MASK_BT_RPT_SAMPLE_RATE_8197F) +#define BIT_SET_BT_RPT_SAMPLE_RATE_8197F(x, v) \ + (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) | \ + BIT_BT_RPT_SAMPLE_RATE_8197F(v)) /* 2 REG_BT_ACT_REGISTER_8197F */ #define BIT_SHIFT_BT_EISR_EN_8197F 16 #define BIT_MASK_BT_EISR_EN_8197F 0xff -#define BIT_BT_EISR_EN_8197F(x) (((x) & BIT_MASK_BT_EISR_EN_8197F) << BIT_SHIFT_BT_EISR_EN_8197F) -#define BITS_BT_EISR_EN_8197F (BIT_MASK_BT_EISR_EN_8197F << BIT_SHIFT_BT_EISR_EN_8197F) +#define BIT_BT_EISR_EN_8197F(x) \ + (((x) & BIT_MASK_BT_EISR_EN_8197F) << BIT_SHIFT_BT_EISR_EN_8197F) +#define BITS_BT_EISR_EN_8197F \ + (BIT_MASK_BT_EISR_EN_8197F << BIT_SHIFT_BT_EISR_EN_8197F) #define BIT_CLEAR_BT_EISR_EN_8197F(x) ((x) & (~BITS_BT_EISR_EN_8197F)) -#define BIT_GET_BT_EISR_EN_8197F(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8197F) & BIT_MASK_BT_EISR_EN_8197F) -#define BIT_SET_BT_EISR_EN_8197F(x, v) (BIT_CLEAR_BT_EISR_EN_8197F(x) | BIT_BT_EISR_EN_8197F(v)) +#define BIT_GET_BT_EISR_EN_8197F(x) \ + (((x) >> BIT_SHIFT_BT_EISR_EN_8197F) & BIT_MASK_BT_EISR_EN_8197F) +#define BIT_SET_BT_EISR_EN_8197F(x, v) \ + (BIT_CLEAR_BT_EISR_EN_8197F(x) | BIT_BT_EISR_EN_8197F(v)) #define BIT_BT_ACT_FALLING_ISR_8197F BIT(10) #define BIT_BT_ACT_RISING_ISR_8197F BIT(9) @@ -12573,23 +16569,29 @@ #define BIT_SHIFT_BT_CH_8197F 0 #define BIT_MASK_BT_CH_8197F 0xff -#define BIT_BT_CH_8197F(x) (((x) & BIT_MASK_BT_CH_8197F) << BIT_SHIFT_BT_CH_8197F) +#define BIT_BT_CH_8197F(x) \ + (((x) & BIT_MASK_BT_CH_8197F) << BIT_SHIFT_BT_CH_8197F) #define BITS_BT_CH_8197F (BIT_MASK_BT_CH_8197F << BIT_SHIFT_BT_CH_8197F) #define BIT_CLEAR_BT_CH_8197F(x) ((x) & (~BITS_BT_CH_8197F)) -#define BIT_GET_BT_CH_8197F(x) (((x) >> BIT_SHIFT_BT_CH_8197F) & BIT_MASK_BT_CH_8197F) -#define BIT_SET_BT_CH_8197F(x, v) (BIT_CLEAR_BT_CH_8197F(x) | BIT_BT_CH_8197F(v)) - +#define BIT_GET_BT_CH_8197F(x) \ + (((x) >> BIT_SHIFT_BT_CH_8197F) & BIT_MASK_BT_CH_8197F) +#define BIT_SET_BT_CH_8197F(x, v) \ + (BIT_CLEAR_BT_CH_8197F(x) | BIT_BT_CH_8197F(v)) /* 2 REG_OBFF_CTRL_BASIC_8197F */ #define BIT_OBFF_EN_V1_8197F BIT(31) #define BIT_SHIFT_OBFF_STATE_V1_8197F 28 #define BIT_MASK_OBFF_STATE_V1_8197F 0x3 -#define BIT_OBFF_STATE_V1_8197F(x) (((x) & BIT_MASK_OBFF_STATE_V1_8197F) << BIT_SHIFT_OBFF_STATE_V1_8197F) -#define BITS_OBFF_STATE_V1_8197F (BIT_MASK_OBFF_STATE_V1_8197F << BIT_SHIFT_OBFF_STATE_V1_8197F) +#define BIT_OBFF_STATE_V1_8197F(x) \ + (((x) & BIT_MASK_OBFF_STATE_V1_8197F) << BIT_SHIFT_OBFF_STATE_V1_8197F) +#define BITS_OBFF_STATE_V1_8197F \ + (BIT_MASK_OBFF_STATE_V1_8197F << BIT_SHIFT_OBFF_STATE_V1_8197F) #define BIT_CLEAR_OBFF_STATE_V1_8197F(x) ((x) & (~BITS_OBFF_STATE_V1_8197F)) -#define BIT_GET_OBFF_STATE_V1_8197F(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8197F) & BIT_MASK_OBFF_STATE_V1_8197F) -#define BIT_SET_OBFF_STATE_V1_8197F(x, v) (BIT_CLEAR_OBFF_STATE_V1_8197F(x) | BIT_OBFF_STATE_V1_8197F(v)) +#define BIT_GET_OBFF_STATE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_OBFF_STATE_V1_8197F) & BIT_MASK_OBFF_STATE_V1_8197F) +#define BIT_SET_OBFF_STATE_V1_8197F(x, v) \ + (BIT_CLEAR_OBFF_STATE_V1_8197F(x) | BIT_OBFF_STATE_V1_8197F(v)) #define BIT_OBFF_ACT_RXDMA_EN_8197F BIT(27) #define BIT_OBFF_BLOCK_INT_EN_8197F BIT(26) @@ -12598,38 +16600,51 @@ #define BIT_SHIFT_WAKE_MAX_PLS_8197F 20 #define BIT_MASK_WAKE_MAX_PLS_8197F 0x7 -#define BIT_WAKE_MAX_PLS_8197F(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8197F) << BIT_SHIFT_WAKE_MAX_PLS_8197F) -#define BITS_WAKE_MAX_PLS_8197F (BIT_MASK_WAKE_MAX_PLS_8197F << BIT_SHIFT_WAKE_MAX_PLS_8197F) +#define BIT_WAKE_MAX_PLS_8197F(x) \ + (((x) & BIT_MASK_WAKE_MAX_PLS_8197F) << BIT_SHIFT_WAKE_MAX_PLS_8197F) +#define BITS_WAKE_MAX_PLS_8197F \ + (BIT_MASK_WAKE_MAX_PLS_8197F << BIT_SHIFT_WAKE_MAX_PLS_8197F) #define BIT_CLEAR_WAKE_MAX_PLS_8197F(x) ((x) & (~BITS_WAKE_MAX_PLS_8197F)) -#define BIT_GET_WAKE_MAX_PLS_8197F(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8197F) & BIT_MASK_WAKE_MAX_PLS_8197F) -#define BIT_SET_WAKE_MAX_PLS_8197F(x, v) (BIT_CLEAR_WAKE_MAX_PLS_8197F(x) | BIT_WAKE_MAX_PLS_8197F(v)) - +#define BIT_GET_WAKE_MAX_PLS_8197F(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8197F) & BIT_MASK_WAKE_MAX_PLS_8197F) +#define BIT_SET_WAKE_MAX_PLS_8197F(x, v) \ + (BIT_CLEAR_WAKE_MAX_PLS_8197F(x) | BIT_WAKE_MAX_PLS_8197F(v)) #define BIT_SHIFT_WAKE_MIN_PLS_8197F 16 #define BIT_MASK_WAKE_MIN_PLS_8197F 0x7 -#define BIT_WAKE_MIN_PLS_8197F(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8197F) << BIT_SHIFT_WAKE_MIN_PLS_8197F) -#define BITS_WAKE_MIN_PLS_8197F (BIT_MASK_WAKE_MIN_PLS_8197F << BIT_SHIFT_WAKE_MIN_PLS_8197F) +#define BIT_WAKE_MIN_PLS_8197F(x) \ + (((x) & BIT_MASK_WAKE_MIN_PLS_8197F) << BIT_SHIFT_WAKE_MIN_PLS_8197F) +#define BITS_WAKE_MIN_PLS_8197F \ + (BIT_MASK_WAKE_MIN_PLS_8197F << BIT_SHIFT_WAKE_MIN_PLS_8197F) #define BIT_CLEAR_WAKE_MIN_PLS_8197F(x) ((x) & (~BITS_WAKE_MIN_PLS_8197F)) -#define BIT_GET_WAKE_MIN_PLS_8197F(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8197F) & BIT_MASK_WAKE_MIN_PLS_8197F) -#define BIT_SET_WAKE_MIN_PLS_8197F(x, v) (BIT_CLEAR_WAKE_MIN_PLS_8197F(x) | BIT_WAKE_MIN_PLS_8197F(v)) - +#define BIT_GET_WAKE_MIN_PLS_8197F(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8197F) & BIT_MASK_WAKE_MIN_PLS_8197F) +#define BIT_SET_WAKE_MIN_PLS_8197F(x, v) \ + (BIT_CLEAR_WAKE_MIN_PLS_8197F(x) | BIT_WAKE_MIN_PLS_8197F(v)) #define BIT_SHIFT_WAKE_MAX_F2F_8197F 12 #define BIT_MASK_WAKE_MAX_F2F_8197F 0x7 -#define BIT_WAKE_MAX_F2F_8197F(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8197F) << BIT_SHIFT_WAKE_MAX_F2F_8197F) -#define BITS_WAKE_MAX_F2F_8197F (BIT_MASK_WAKE_MAX_F2F_8197F << BIT_SHIFT_WAKE_MAX_F2F_8197F) +#define BIT_WAKE_MAX_F2F_8197F(x) \ + (((x) & BIT_MASK_WAKE_MAX_F2F_8197F) << BIT_SHIFT_WAKE_MAX_F2F_8197F) +#define BITS_WAKE_MAX_F2F_8197F \ + (BIT_MASK_WAKE_MAX_F2F_8197F << BIT_SHIFT_WAKE_MAX_F2F_8197F) #define BIT_CLEAR_WAKE_MAX_F2F_8197F(x) ((x) & (~BITS_WAKE_MAX_F2F_8197F)) -#define BIT_GET_WAKE_MAX_F2F_8197F(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8197F) & BIT_MASK_WAKE_MAX_F2F_8197F) -#define BIT_SET_WAKE_MAX_F2F_8197F(x, v) (BIT_CLEAR_WAKE_MAX_F2F_8197F(x) | BIT_WAKE_MAX_F2F_8197F(v)) - +#define BIT_GET_WAKE_MAX_F2F_8197F(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8197F) & BIT_MASK_WAKE_MAX_F2F_8197F) +#define BIT_SET_WAKE_MAX_F2F_8197F(x, v) \ + (BIT_CLEAR_WAKE_MAX_F2F_8197F(x) | BIT_WAKE_MAX_F2F_8197F(v)) #define BIT_SHIFT_WAKE_MIN_F2F_8197F 8 #define BIT_MASK_WAKE_MIN_F2F_8197F 0x7 -#define BIT_WAKE_MIN_F2F_8197F(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8197F) << BIT_SHIFT_WAKE_MIN_F2F_8197F) -#define BITS_WAKE_MIN_F2F_8197F (BIT_MASK_WAKE_MIN_F2F_8197F << BIT_SHIFT_WAKE_MIN_F2F_8197F) +#define BIT_WAKE_MIN_F2F_8197F(x) \ + (((x) & BIT_MASK_WAKE_MIN_F2F_8197F) << BIT_SHIFT_WAKE_MIN_F2F_8197F) +#define BITS_WAKE_MIN_F2F_8197F \ + (BIT_MASK_WAKE_MIN_F2F_8197F << BIT_SHIFT_WAKE_MIN_F2F_8197F) #define BIT_CLEAR_WAKE_MIN_F2F_8197F(x) ((x) & (~BITS_WAKE_MIN_F2F_8197F)) -#define BIT_GET_WAKE_MIN_F2F_8197F(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8197F) & BIT_MASK_WAKE_MIN_F2F_8197F) -#define BIT_SET_WAKE_MIN_F2F_8197F(x, v) (BIT_CLEAR_WAKE_MIN_F2F_8197F(x) | BIT_WAKE_MIN_F2F_8197F(v)) +#define BIT_GET_WAKE_MIN_F2F_8197F(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8197F) & BIT_MASK_WAKE_MIN_F2F_8197F) +#define BIT_SET_WAKE_MIN_F2F_8197F(x, v) \ + (BIT_CLEAR_WAKE_MIN_F2F_8197F(x) | BIT_WAKE_MIN_F2F_8197F(v)) #define BIT_APP_CPU_ACT_V1_8197F BIT(3) #define BIT_APP_OBFF_V1_8197F BIT(2) @@ -12640,39 +16655,65 @@ #define BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F 24 #define BIT_MASK_RX_HIGH_TIMER_IDX_8197F 0x7 -#define BIT_RX_HIGH_TIMER_IDX_8197F(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8197F) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) -#define BITS_RX_HIGH_TIMER_IDX_8197F (BIT_MASK_RX_HIGH_TIMER_IDX_8197F << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) -#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) ((x) & (~BITS_RX_HIGH_TIMER_IDX_8197F)) -#define BIT_GET_RX_HIGH_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) & BIT_MASK_RX_HIGH_TIMER_IDX_8197F) -#define BIT_SET_RX_HIGH_TIMER_IDX_8197F(x, v) (BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) | BIT_RX_HIGH_TIMER_IDX_8197F(v)) - +#define BIT_RX_HIGH_TIMER_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8197F) \ + << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) +#define BITS_RX_HIGH_TIMER_IDX_8197F \ + (BIT_MASK_RX_HIGH_TIMER_IDX_8197F << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) \ + ((x) & (~BITS_RX_HIGH_TIMER_IDX_8197F)) +#define BIT_GET_RX_HIGH_TIMER_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) & \ + BIT_MASK_RX_HIGH_TIMER_IDX_8197F) +#define BIT_SET_RX_HIGH_TIMER_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) | BIT_RX_HIGH_TIMER_IDX_8197F(v)) #define BIT_SHIFT_RX_MED_TIMER_IDX_8197F 16 #define BIT_MASK_RX_MED_TIMER_IDX_8197F 0x7 -#define BIT_RX_MED_TIMER_IDX_8197F(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8197F) << BIT_SHIFT_RX_MED_TIMER_IDX_8197F) -#define BITS_RX_MED_TIMER_IDX_8197F (BIT_MASK_RX_MED_TIMER_IDX_8197F << BIT_SHIFT_RX_MED_TIMER_IDX_8197F) -#define BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) ((x) & (~BITS_RX_MED_TIMER_IDX_8197F)) -#define BIT_GET_RX_MED_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8197F) & BIT_MASK_RX_MED_TIMER_IDX_8197F) -#define BIT_SET_RX_MED_TIMER_IDX_8197F(x, v) (BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) | BIT_RX_MED_TIMER_IDX_8197F(v)) - +#define BIT_RX_MED_TIMER_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_MED_TIMER_IDX_8197F) \ + << BIT_SHIFT_RX_MED_TIMER_IDX_8197F) +#define BITS_RX_MED_TIMER_IDX_8197F \ + (BIT_MASK_RX_MED_TIMER_IDX_8197F << BIT_SHIFT_RX_MED_TIMER_IDX_8197F) +#define BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) \ + ((x) & (~BITS_RX_MED_TIMER_IDX_8197F)) +#define BIT_GET_RX_MED_TIMER_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8197F) & \ + BIT_MASK_RX_MED_TIMER_IDX_8197F) +#define BIT_SET_RX_MED_TIMER_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) | BIT_RX_MED_TIMER_IDX_8197F(v)) #define BIT_SHIFT_RX_LOW_TIMER_IDX_8197F 8 #define BIT_MASK_RX_LOW_TIMER_IDX_8197F 0x7 -#define BIT_RX_LOW_TIMER_IDX_8197F(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8197F) << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) -#define BITS_RX_LOW_TIMER_IDX_8197F (BIT_MASK_RX_LOW_TIMER_IDX_8197F << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) -#define BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) ((x) & (~BITS_RX_LOW_TIMER_IDX_8197F)) -#define BIT_GET_RX_LOW_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) & BIT_MASK_RX_LOW_TIMER_IDX_8197F) -#define BIT_SET_RX_LOW_TIMER_IDX_8197F(x, v) (BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) | BIT_RX_LOW_TIMER_IDX_8197F(v)) - +#define BIT_RX_LOW_TIMER_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8197F) \ + << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) +#define BITS_RX_LOW_TIMER_IDX_8197F \ + (BIT_MASK_RX_LOW_TIMER_IDX_8197F << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) +#define BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) \ + ((x) & (~BITS_RX_LOW_TIMER_IDX_8197F)) +#define BIT_GET_RX_LOW_TIMER_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) & \ + BIT_MASK_RX_LOW_TIMER_IDX_8197F) +#define BIT_SET_RX_LOW_TIMER_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) | BIT_RX_LOW_TIMER_IDX_8197F(v)) #define BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F 0 #define BIT_MASK_OBFF_INT_TIMER_IDX_8197F 0x7 -#define BIT_OBFF_INT_TIMER_IDX_8197F(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8197F) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) -#define BITS_OBFF_INT_TIMER_IDX_8197F (BIT_MASK_OBFF_INT_TIMER_IDX_8197F << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) -#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) ((x) & (~BITS_OBFF_INT_TIMER_IDX_8197F)) -#define BIT_GET_OBFF_INT_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) & BIT_MASK_OBFF_INT_TIMER_IDX_8197F) -#define BIT_SET_OBFF_INT_TIMER_IDX_8197F(x, v) (BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) | BIT_OBFF_INT_TIMER_IDX_8197F(v)) - +#define BIT_OBFF_INT_TIMER_IDX_8197F(x) \ + (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8197F) \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) +#define BITS_OBFF_INT_TIMER_IDX_8197F \ + (BIT_MASK_OBFF_INT_TIMER_IDX_8197F \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) \ + ((x) & (~BITS_OBFF_INT_TIMER_IDX_8197F)) +#define BIT_GET_OBFF_INT_TIMER_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) & \ + BIT_MASK_OBFF_INT_TIMER_IDX_8197F) +#define BIT_SET_OBFF_INT_TIMER_IDX_8197F(x, v) \ + (BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) | \ + BIT_OBFF_INT_TIMER_IDX_8197F(v)) /* 2 REG_LTR_CTRL_BASIC_8197F */ #define BIT_LTR_EN_V1_8197F BIT(31) @@ -12688,135 +16729,207 @@ #define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F 20 #define BIT_MASK_HIGH_RATE_TRIG_SEL_8197F 0x3 -#define BIT_HIGH_RATE_TRIG_SEL_8197F(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8197F) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) -#define BITS_HIGH_RATE_TRIG_SEL_8197F (BIT_MASK_HIGH_RATE_TRIG_SEL_8197F << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) -#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8197F)) -#define BIT_GET_HIGH_RATE_TRIG_SEL_8197F(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) & BIT_MASK_HIGH_RATE_TRIG_SEL_8197F) -#define BIT_SET_HIGH_RATE_TRIG_SEL_8197F(x, v) (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) | BIT_HIGH_RATE_TRIG_SEL_8197F(v)) - +#define BIT_HIGH_RATE_TRIG_SEL_8197F(x) \ + (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8197F) \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) +#define BITS_HIGH_RATE_TRIG_SEL_8197F \ + (BIT_MASK_HIGH_RATE_TRIG_SEL_8197F \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) \ + ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8197F)) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) & \ + BIT_MASK_HIGH_RATE_TRIG_SEL_8197F) +#define BIT_SET_HIGH_RATE_TRIG_SEL_8197F(x, v) \ + (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) | \ + BIT_HIGH_RATE_TRIG_SEL_8197F(v)) #define BIT_SHIFT_MED_RATE_TRIG_SEL_8197F 18 #define BIT_MASK_MED_RATE_TRIG_SEL_8197F 0x3 -#define BIT_MED_RATE_TRIG_SEL_8197F(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8197F) << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) -#define BITS_MED_RATE_TRIG_SEL_8197F (BIT_MASK_MED_RATE_TRIG_SEL_8197F << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) -#define BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) ((x) & (~BITS_MED_RATE_TRIG_SEL_8197F)) -#define BIT_GET_MED_RATE_TRIG_SEL_8197F(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) & BIT_MASK_MED_RATE_TRIG_SEL_8197F) -#define BIT_SET_MED_RATE_TRIG_SEL_8197F(x, v) (BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) | BIT_MED_RATE_TRIG_SEL_8197F(v)) - +#define BIT_MED_RATE_TRIG_SEL_8197F(x) \ + (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8197F) \ + << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) +#define BITS_MED_RATE_TRIG_SEL_8197F \ + (BIT_MASK_MED_RATE_TRIG_SEL_8197F << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) +#define BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) \ + ((x) & (~BITS_MED_RATE_TRIG_SEL_8197F)) +#define BIT_GET_MED_RATE_TRIG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) & \ + BIT_MASK_MED_RATE_TRIG_SEL_8197F) +#define BIT_SET_MED_RATE_TRIG_SEL_8197F(x, v) \ + (BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) | BIT_MED_RATE_TRIG_SEL_8197F(v)) #define BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F 16 #define BIT_MASK_LOW_RATE_TRIG_SEL_8197F 0x3 -#define BIT_LOW_RATE_TRIG_SEL_8197F(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8197F) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) -#define BITS_LOW_RATE_TRIG_SEL_8197F (BIT_MASK_LOW_RATE_TRIG_SEL_8197F << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) -#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) ((x) & (~BITS_LOW_RATE_TRIG_SEL_8197F)) -#define BIT_GET_LOW_RATE_TRIG_SEL_8197F(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) & BIT_MASK_LOW_RATE_TRIG_SEL_8197F) -#define BIT_SET_LOW_RATE_TRIG_SEL_8197F(x, v) (BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) | BIT_LOW_RATE_TRIG_SEL_8197F(v)) - +#define BIT_LOW_RATE_TRIG_SEL_8197F(x) \ + (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8197F) \ + << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) +#define BITS_LOW_RATE_TRIG_SEL_8197F \ + (BIT_MASK_LOW_RATE_TRIG_SEL_8197F << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) \ + ((x) & (~BITS_LOW_RATE_TRIG_SEL_8197F)) +#define BIT_GET_LOW_RATE_TRIG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) & \ + BIT_MASK_LOW_RATE_TRIG_SEL_8197F) +#define BIT_SET_LOW_RATE_TRIG_SEL_8197F(x, v) \ + (BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) | BIT_LOW_RATE_TRIG_SEL_8197F(v)) #define BIT_SHIFT_HIGH_RATE_BD_IDX_8197F 8 #define BIT_MASK_HIGH_RATE_BD_IDX_8197F 0x7f -#define BIT_HIGH_RATE_BD_IDX_8197F(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8197F) << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) -#define BITS_HIGH_RATE_BD_IDX_8197F (BIT_MASK_HIGH_RATE_BD_IDX_8197F << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) -#define BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) ((x) & (~BITS_HIGH_RATE_BD_IDX_8197F)) -#define BIT_GET_HIGH_RATE_BD_IDX_8197F(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) & BIT_MASK_HIGH_RATE_BD_IDX_8197F) -#define BIT_SET_HIGH_RATE_BD_IDX_8197F(x, v) (BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) | BIT_HIGH_RATE_BD_IDX_8197F(v)) - +#define BIT_HIGH_RATE_BD_IDX_8197F(x) \ + (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8197F) \ + << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) +#define BITS_HIGH_RATE_BD_IDX_8197F \ + (BIT_MASK_HIGH_RATE_BD_IDX_8197F << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) +#define BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) \ + ((x) & (~BITS_HIGH_RATE_BD_IDX_8197F)) +#define BIT_GET_HIGH_RATE_BD_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) & \ + BIT_MASK_HIGH_RATE_BD_IDX_8197F) +#define BIT_SET_HIGH_RATE_BD_IDX_8197F(x, v) \ + (BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) | BIT_HIGH_RATE_BD_IDX_8197F(v)) #define BIT_SHIFT_LOW_RATE_BD_IDX_8197F 0 #define BIT_MASK_LOW_RATE_BD_IDX_8197F 0x7f -#define BIT_LOW_RATE_BD_IDX_8197F(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8197F) << BIT_SHIFT_LOW_RATE_BD_IDX_8197F) -#define BITS_LOW_RATE_BD_IDX_8197F (BIT_MASK_LOW_RATE_BD_IDX_8197F << BIT_SHIFT_LOW_RATE_BD_IDX_8197F) +#define BIT_LOW_RATE_BD_IDX_8197F(x) \ + (((x) & BIT_MASK_LOW_RATE_BD_IDX_8197F) \ + << BIT_SHIFT_LOW_RATE_BD_IDX_8197F) +#define BITS_LOW_RATE_BD_IDX_8197F \ + (BIT_MASK_LOW_RATE_BD_IDX_8197F << BIT_SHIFT_LOW_RATE_BD_IDX_8197F) #define BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8197F)) -#define BIT_GET_LOW_RATE_BD_IDX_8197F(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8197F) & BIT_MASK_LOW_RATE_BD_IDX_8197F) -#define BIT_SET_LOW_RATE_BD_IDX_8197F(x, v) (BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) | BIT_LOW_RATE_BD_IDX_8197F(v)) - +#define BIT_GET_LOW_RATE_BD_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8197F) & \ + BIT_MASK_LOW_RATE_BD_IDX_8197F) +#define BIT_SET_LOW_RATE_BD_IDX_8197F(x, v) \ + (BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) | BIT_LOW_RATE_BD_IDX_8197F(v)) /* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8197F */ #define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F 24 #define BIT_MASK_RX_EMPTY_TIMER_IDX_8197F 0x7 -#define BIT_RX_EMPTY_TIMER_IDX_8197F(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8197F) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) -#define BITS_RX_EMPTY_TIMER_IDX_8197F (BIT_MASK_RX_EMPTY_TIMER_IDX_8197F << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) -#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8197F)) -#define BIT_GET_RX_EMPTY_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) & BIT_MASK_RX_EMPTY_TIMER_IDX_8197F) -#define BIT_SET_RX_EMPTY_TIMER_IDX_8197F(x, v) (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) | BIT_RX_EMPTY_TIMER_IDX_8197F(v)) - +#define BIT_RX_EMPTY_TIMER_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8197F) \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) +#define BITS_RX_EMPTY_TIMER_IDX_8197F \ + (BIT_MASK_RX_EMPTY_TIMER_IDX_8197F \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) \ + ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8197F)) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) & \ + BIT_MASK_RX_EMPTY_TIMER_IDX_8197F) +#define BIT_SET_RX_EMPTY_TIMER_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) | \ + BIT_RX_EMPTY_TIMER_IDX_8197F(v)) #define BIT_SHIFT_RX_AFULL_TH_IDX_8197F 20 #define BIT_MASK_RX_AFULL_TH_IDX_8197F 0x7 -#define BIT_RX_AFULL_TH_IDX_8197F(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8197F) << BIT_SHIFT_RX_AFULL_TH_IDX_8197F) -#define BITS_RX_AFULL_TH_IDX_8197F (BIT_MASK_RX_AFULL_TH_IDX_8197F << BIT_SHIFT_RX_AFULL_TH_IDX_8197F) +#define BIT_RX_AFULL_TH_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_AFULL_TH_IDX_8197F) \ + << BIT_SHIFT_RX_AFULL_TH_IDX_8197F) +#define BITS_RX_AFULL_TH_IDX_8197F \ + (BIT_MASK_RX_AFULL_TH_IDX_8197F << BIT_SHIFT_RX_AFULL_TH_IDX_8197F) #define BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8197F)) -#define BIT_GET_RX_AFULL_TH_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8197F) & BIT_MASK_RX_AFULL_TH_IDX_8197F) -#define BIT_SET_RX_AFULL_TH_IDX_8197F(x, v) (BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) | BIT_RX_AFULL_TH_IDX_8197F(v)) - +#define BIT_GET_RX_AFULL_TH_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8197F) & \ + BIT_MASK_RX_AFULL_TH_IDX_8197F) +#define BIT_SET_RX_AFULL_TH_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) | BIT_RX_AFULL_TH_IDX_8197F(v)) #define BIT_SHIFT_RX_HIGH_TH_IDX_8197F 16 #define BIT_MASK_RX_HIGH_TH_IDX_8197F 0x7 -#define BIT_RX_HIGH_TH_IDX_8197F(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8197F) << BIT_SHIFT_RX_HIGH_TH_IDX_8197F) -#define BITS_RX_HIGH_TH_IDX_8197F (BIT_MASK_RX_HIGH_TH_IDX_8197F << BIT_SHIFT_RX_HIGH_TH_IDX_8197F) +#define BIT_RX_HIGH_TH_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_HIGH_TH_IDX_8197F) \ + << BIT_SHIFT_RX_HIGH_TH_IDX_8197F) +#define BITS_RX_HIGH_TH_IDX_8197F \ + (BIT_MASK_RX_HIGH_TH_IDX_8197F << BIT_SHIFT_RX_HIGH_TH_IDX_8197F) #define BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8197F)) -#define BIT_GET_RX_HIGH_TH_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8197F) & BIT_MASK_RX_HIGH_TH_IDX_8197F) -#define BIT_SET_RX_HIGH_TH_IDX_8197F(x, v) (BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) | BIT_RX_HIGH_TH_IDX_8197F(v)) - +#define BIT_GET_RX_HIGH_TH_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8197F) & \ + BIT_MASK_RX_HIGH_TH_IDX_8197F) +#define BIT_SET_RX_HIGH_TH_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) | BIT_RX_HIGH_TH_IDX_8197F(v)) #define BIT_SHIFT_RX_MED_TH_IDX_8197F 12 #define BIT_MASK_RX_MED_TH_IDX_8197F 0x7 -#define BIT_RX_MED_TH_IDX_8197F(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8197F) << BIT_SHIFT_RX_MED_TH_IDX_8197F) -#define BITS_RX_MED_TH_IDX_8197F (BIT_MASK_RX_MED_TH_IDX_8197F << BIT_SHIFT_RX_MED_TH_IDX_8197F) +#define BIT_RX_MED_TH_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_MED_TH_IDX_8197F) << BIT_SHIFT_RX_MED_TH_IDX_8197F) +#define BITS_RX_MED_TH_IDX_8197F \ + (BIT_MASK_RX_MED_TH_IDX_8197F << BIT_SHIFT_RX_MED_TH_IDX_8197F) #define BIT_CLEAR_RX_MED_TH_IDX_8197F(x) ((x) & (~BITS_RX_MED_TH_IDX_8197F)) -#define BIT_GET_RX_MED_TH_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8197F) & BIT_MASK_RX_MED_TH_IDX_8197F) -#define BIT_SET_RX_MED_TH_IDX_8197F(x, v) (BIT_CLEAR_RX_MED_TH_IDX_8197F(x) | BIT_RX_MED_TH_IDX_8197F(v)) - +#define BIT_GET_RX_MED_TH_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8197F) & BIT_MASK_RX_MED_TH_IDX_8197F) +#define BIT_SET_RX_MED_TH_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_MED_TH_IDX_8197F(x) | BIT_RX_MED_TH_IDX_8197F(v)) #define BIT_SHIFT_RX_LOW_TH_IDX_8197F 8 #define BIT_MASK_RX_LOW_TH_IDX_8197F 0x7 -#define BIT_RX_LOW_TH_IDX_8197F(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8197F) << BIT_SHIFT_RX_LOW_TH_IDX_8197F) -#define BITS_RX_LOW_TH_IDX_8197F (BIT_MASK_RX_LOW_TH_IDX_8197F << BIT_SHIFT_RX_LOW_TH_IDX_8197F) +#define BIT_RX_LOW_TH_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_LOW_TH_IDX_8197F) << BIT_SHIFT_RX_LOW_TH_IDX_8197F) +#define BITS_RX_LOW_TH_IDX_8197F \ + (BIT_MASK_RX_LOW_TH_IDX_8197F << BIT_SHIFT_RX_LOW_TH_IDX_8197F) #define BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) ((x) & (~BITS_RX_LOW_TH_IDX_8197F)) -#define BIT_GET_RX_LOW_TH_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8197F) & BIT_MASK_RX_LOW_TH_IDX_8197F) -#define BIT_SET_RX_LOW_TH_IDX_8197F(x, v) (BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) | BIT_RX_LOW_TH_IDX_8197F(v)) - +#define BIT_GET_RX_LOW_TH_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8197F) & BIT_MASK_RX_LOW_TH_IDX_8197F) +#define BIT_SET_RX_LOW_TH_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) | BIT_RX_LOW_TH_IDX_8197F(v)) #define BIT_SHIFT_LTR_SPACE_IDX_8197F 4 #define BIT_MASK_LTR_SPACE_IDX_8197F 0x3 -#define BIT_LTR_SPACE_IDX_8197F(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8197F) << BIT_SHIFT_LTR_SPACE_IDX_8197F) -#define BITS_LTR_SPACE_IDX_8197F (BIT_MASK_LTR_SPACE_IDX_8197F << BIT_SHIFT_LTR_SPACE_IDX_8197F) +#define BIT_LTR_SPACE_IDX_8197F(x) \ + (((x) & BIT_MASK_LTR_SPACE_IDX_8197F) << BIT_SHIFT_LTR_SPACE_IDX_8197F) +#define BITS_LTR_SPACE_IDX_8197F \ + (BIT_MASK_LTR_SPACE_IDX_8197F << BIT_SHIFT_LTR_SPACE_IDX_8197F) #define BIT_CLEAR_LTR_SPACE_IDX_8197F(x) ((x) & (~BITS_LTR_SPACE_IDX_8197F)) -#define BIT_GET_LTR_SPACE_IDX_8197F(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8197F) & BIT_MASK_LTR_SPACE_IDX_8197F) -#define BIT_SET_LTR_SPACE_IDX_8197F(x, v) (BIT_CLEAR_LTR_SPACE_IDX_8197F(x) | BIT_LTR_SPACE_IDX_8197F(v)) - +#define BIT_GET_LTR_SPACE_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8197F) & BIT_MASK_LTR_SPACE_IDX_8197F) +#define BIT_SET_LTR_SPACE_IDX_8197F(x, v) \ + (BIT_CLEAR_LTR_SPACE_IDX_8197F(x) | BIT_LTR_SPACE_IDX_8197F(v)) #define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F 0 #define BIT_MASK_LTR_IDLE_TIMER_IDX_8197F 0x7 -#define BIT_LTR_IDLE_TIMER_IDX_8197F(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8197F) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) -#define BITS_LTR_IDLE_TIMER_IDX_8197F (BIT_MASK_LTR_IDLE_TIMER_IDX_8197F << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) -#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8197F)) -#define BIT_GET_LTR_IDLE_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) & BIT_MASK_LTR_IDLE_TIMER_IDX_8197F) -#define BIT_SET_LTR_IDLE_TIMER_IDX_8197F(x, v) (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) | BIT_LTR_IDLE_TIMER_IDX_8197F(v)) - +#define BIT_LTR_IDLE_TIMER_IDX_8197F(x) \ + (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8197F) \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) +#define BITS_LTR_IDLE_TIMER_IDX_8197F \ + (BIT_MASK_LTR_IDLE_TIMER_IDX_8197F \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) \ + ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8197F)) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) & \ + BIT_MASK_LTR_IDLE_TIMER_IDX_8197F) +#define BIT_SET_LTR_IDLE_TIMER_IDX_8197F(x, v) \ + (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) | \ + BIT_LTR_IDLE_TIMER_IDX_8197F(v)) /* 2 REG_LTR_IDLE_LATENCY_V1_8197F */ #define BIT_SHIFT_LTR_IDLE_L_8197F 0 #define BIT_MASK_LTR_IDLE_L_8197F 0xffffffffL -#define BIT_LTR_IDLE_L_8197F(x) (((x) & BIT_MASK_LTR_IDLE_L_8197F) << BIT_SHIFT_LTR_IDLE_L_8197F) -#define BITS_LTR_IDLE_L_8197F (BIT_MASK_LTR_IDLE_L_8197F << BIT_SHIFT_LTR_IDLE_L_8197F) +#define BIT_LTR_IDLE_L_8197F(x) \ + (((x) & BIT_MASK_LTR_IDLE_L_8197F) << BIT_SHIFT_LTR_IDLE_L_8197F) +#define BITS_LTR_IDLE_L_8197F \ + (BIT_MASK_LTR_IDLE_L_8197F << BIT_SHIFT_LTR_IDLE_L_8197F) #define BIT_CLEAR_LTR_IDLE_L_8197F(x) ((x) & (~BITS_LTR_IDLE_L_8197F)) -#define BIT_GET_LTR_IDLE_L_8197F(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8197F) & BIT_MASK_LTR_IDLE_L_8197F) -#define BIT_SET_LTR_IDLE_L_8197F(x, v) (BIT_CLEAR_LTR_IDLE_L_8197F(x) | BIT_LTR_IDLE_L_8197F(v)) - +#define BIT_GET_LTR_IDLE_L_8197F(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_L_8197F) & BIT_MASK_LTR_IDLE_L_8197F) +#define BIT_SET_LTR_IDLE_L_8197F(x, v) \ + (BIT_CLEAR_LTR_IDLE_L_8197F(x) | BIT_LTR_IDLE_L_8197F(v)) /* 2 REG_LTR_ACTIVE_LATENCY_V1_8197F */ #define BIT_SHIFT_LTR_ACT_L_8197F 0 #define BIT_MASK_LTR_ACT_L_8197F 0xffffffffL -#define BIT_LTR_ACT_L_8197F(x) (((x) & BIT_MASK_LTR_ACT_L_8197F) << BIT_SHIFT_LTR_ACT_L_8197F) -#define BITS_LTR_ACT_L_8197F (BIT_MASK_LTR_ACT_L_8197F << BIT_SHIFT_LTR_ACT_L_8197F) +#define BIT_LTR_ACT_L_8197F(x) \ + (((x) & BIT_MASK_LTR_ACT_L_8197F) << BIT_SHIFT_LTR_ACT_L_8197F) +#define BITS_LTR_ACT_L_8197F \ + (BIT_MASK_LTR_ACT_L_8197F << BIT_SHIFT_LTR_ACT_L_8197F) #define BIT_CLEAR_LTR_ACT_L_8197F(x) ((x) & (~BITS_LTR_ACT_L_8197F)) -#define BIT_GET_LTR_ACT_L_8197F(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8197F) & BIT_MASK_LTR_ACT_L_8197F) -#define BIT_SET_LTR_ACT_L_8197F(x, v) (BIT_CLEAR_LTR_ACT_L_8197F(x) | BIT_LTR_ACT_L_8197F(v)) - +#define BIT_GET_LTR_ACT_L_8197F(x) \ + (((x) >> BIT_SHIFT_LTR_ACT_L_8197F) & BIT_MASK_LTR_ACT_L_8197F) +#define BIT_SET_LTR_ACT_L_8197F(x, v) \ + (BIT_CLEAR_LTR_ACT_L_8197F(x) | BIT_LTR_ACT_L_8197F(v)) /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F */ #define BIT_APPEND_MACID_IN_RESP_EN_8197F BIT(50) @@ -12825,12 +16938,17 @@ #define BIT_SHIFT_TRAIN_STA_ADDR_8197F 0 #define BIT_MASK_TRAIN_STA_ADDR_8197F 0xffffffffffffL -#define BIT_TRAIN_STA_ADDR_8197F(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_8197F) << BIT_SHIFT_TRAIN_STA_ADDR_8197F) -#define BITS_TRAIN_STA_ADDR_8197F (BIT_MASK_TRAIN_STA_ADDR_8197F << BIT_SHIFT_TRAIN_STA_ADDR_8197F) +#define BIT_TRAIN_STA_ADDR_8197F(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_8197F) \ + << BIT_SHIFT_TRAIN_STA_ADDR_8197F) +#define BITS_TRAIN_STA_ADDR_8197F \ + (BIT_MASK_TRAIN_STA_ADDR_8197F << BIT_SHIFT_TRAIN_STA_ADDR_8197F) #define BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) ((x) & (~BITS_TRAIN_STA_ADDR_8197F)) -#define BIT_GET_TRAIN_STA_ADDR_8197F(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8197F) & BIT_MASK_TRAIN_STA_ADDR_8197F) -#define BIT_SET_TRAIN_STA_ADDR_8197F(x, v) (BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) | BIT_TRAIN_STA_ADDR_8197F(v)) - +#define BIT_GET_TRAIN_STA_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8197F) & \ + BIT_MASK_TRAIN_STA_ADDR_8197F) +#define BIT_SET_TRAIN_STA_ADDR_8197F(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) | BIT_TRAIN_STA_ADDR_8197F(v)) /* 2 REG_RSVD_0X7B4_8197F */ @@ -12838,11 +16956,17 @@ #define BIT_SHIFT_PKTCNT_BSSIDMAP_8197F 4 #define BIT_MASK_PKTCNT_BSSIDMAP_8197F 0xf -#define BIT_PKTCNT_BSSIDMAP_8197F(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8197F) << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) -#define BITS_PKTCNT_BSSIDMAP_8197F (BIT_MASK_PKTCNT_BSSIDMAP_8197F << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) +#define BIT_PKTCNT_BSSIDMAP_8197F(x) \ + (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8197F) \ + << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) +#define BITS_PKTCNT_BSSIDMAP_8197F \ + (BIT_MASK_PKTCNT_BSSIDMAP_8197F << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) #define BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8197F)) -#define BIT_GET_PKTCNT_BSSIDMAP_8197F(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) & BIT_MASK_PKTCNT_BSSIDMAP_8197F) -#define BIT_SET_PKTCNT_BSSIDMAP_8197F(x, v) (BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) | BIT_PKTCNT_BSSIDMAP_8197F(v)) +#define BIT_GET_PKTCNT_BSSIDMAP_8197F(x) \ + (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) & \ + BIT_MASK_PKTCNT_BSSIDMAP_8197F) +#define BIT_SET_PKTCNT_BSSIDMAP_8197F(x, v) \ + (BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) | BIT_PKTCNT_BSSIDMAP_8197F(v)) #define BIT_PKTCNT_CNTRST_8197F BIT(1) #define BIT_PKTCNT_CNTEN_8197F BIT(0) @@ -12853,68 +16977,111 @@ #define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F 0 #define BIT_MASK_WMAC_PKTCNT_CFGAD_8197F 0xff -#define BIT_WMAC_PKTCNT_CFGAD_8197F(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8197F) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) -#define BITS_WMAC_PKTCNT_CFGAD_8197F (BIT_MASK_WMAC_PKTCNT_CFGAD_8197F << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) -#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8197F)) -#define BIT_GET_WMAC_PKTCNT_CFGAD_8197F(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) & BIT_MASK_WMAC_PKTCNT_CFGAD_8197F) -#define BIT_SET_WMAC_PKTCNT_CFGAD_8197F(x, v) (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) | BIT_WMAC_PKTCNT_CFGAD_8197F(v)) - +#define BIT_WMAC_PKTCNT_CFGAD_8197F(x) \ + (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8197F) \ + << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) +#define BITS_WMAC_PKTCNT_CFGAD_8197F \ + (BIT_MASK_WMAC_PKTCNT_CFGAD_8197F << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) +#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) \ + ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8197F)) +#define BIT_GET_WMAC_PKTCNT_CFGAD_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) & \ + BIT_MASK_WMAC_PKTCNT_CFGAD_8197F) +#define BIT_SET_WMAC_PKTCNT_CFGAD_8197F(x, v) \ + (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) | BIT_WMAC_PKTCNT_CFGAD_8197F(v)) /* 2 REG_IQ_DUMP_8197F */ #define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F (64 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC_8197F(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) -#define BITS_R_WMAC_MATCH_REF_MAC_8197F (BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) -#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8197F)) -#define BIT_GET_R_WMAC_MATCH_REF_MAC_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F) -#define BIT_SET_R_WMAC_MATCH_REF_MAC_8197F(x, v) (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) | BIT_R_WMAC_MATCH_REF_MAC_8197F(v)) - +#define BIT_R_WMAC_MATCH_REF_MAC_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) +#define BITS_R_WMAC_MATCH_REF_MAC_8197F \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) \ + ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8197F)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) | \ + BIT_R_WMAC_MATCH_REF_MAC_8197F(v)) #define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_MASK_LA_MAC_8197F 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC_8197F(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8197F) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) -#define BITS_R_WMAC_MASK_LA_MAC_8197F (BIT_MASK_R_WMAC_MASK_LA_MAC_8197F << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) -#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC_8197F)) -#define BIT_GET_R_WMAC_MASK_LA_MAC_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) & BIT_MASK_R_WMAC_MASK_LA_MAC_8197F) -#define BIT_SET_R_WMAC_MASK_LA_MAC_8197F(x, v) (BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) | BIT_R_WMAC_MASK_LA_MAC_8197F(v)) - +#define BIT_R_WMAC_MASK_LA_MAC_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8197F) \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) +#define BITS_R_WMAC_MASK_LA_MAC_8197F \ + (BIT_MASK_R_WMAC_MASK_LA_MAC_8197F \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) \ + ((x) & (~BITS_R_WMAC_MASK_LA_MAC_8197F)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) & \ + BIT_MASK_R_WMAC_MASK_LA_MAC_8197F) +#define BIT_SET_R_WMAC_MASK_LA_MAC_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) | \ + BIT_R_WMAC_MASK_LA_MAC_8197F(v)) #define BIT_SHIFT_DUMP_OK_ADDR_8197F 16 #define BIT_MASK_DUMP_OK_ADDR_8197F 0xffff -#define BIT_DUMP_OK_ADDR_8197F(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8197F) << BIT_SHIFT_DUMP_OK_ADDR_8197F) -#define BITS_DUMP_OK_ADDR_8197F (BIT_MASK_DUMP_OK_ADDR_8197F << BIT_SHIFT_DUMP_OK_ADDR_8197F) +#define BIT_DUMP_OK_ADDR_8197F(x) \ + (((x) & BIT_MASK_DUMP_OK_ADDR_8197F) << BIT_SHIFT_DUMP_OK_ADDR_8197F) +#define BITS_DUMP_OK_ADDR_8197F \ + (BIT_MASK_DUMP_OK_ADDR_8197F << BIT_SHIFT_DUMP_OK_ADDR_8197F) #define BIT_CLEAR_DUMP_OK_ADDR_8197F(x) ((x) & (~BITS_DUMP_OK_ADDR_8197F)) -#define BIT_GET_DUMP_OK_ADDR_8197F(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8197F) & BIT_MASK_DUMP_OK_ADDR_8197F) -#define BIT_SET_DUMP_OK_ADDR_8197F(x, v) (BIT_CLEAR_DUMP_OK_ADDR_8197F(x) | BIT_DUMP_OK_ADDR_8197F(v)) - +#define BIT_GET_DUMP_OK_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8197F) & BIT_MASK_DUMP_OK_ADDR_8197F) +#define BIT_SET_DUMP_OK_ADDR_8197F(x, v) \ + (BIT_CLEAR_DUMP_OK_ADDR_8197F(x) | BIT_DUMP_OK_ADDR_8197F(v)) #define BIT_SHIFT_R_TRIG_TIME_SEL_8197F 8 #define BIT_MASK_R_TRIG_TIME_SEL_8197F 0x7f -#define BIT_R_TRIG_TIME_SEL_8197F(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8197F) << BIT_SHIFT_R_TRIG_TIME_SEL_8197F) -#define BITS_R_TRIG_TIME_SEL_8197F (BIT_MASK_R_TRIG_TIME_SEL_8197F << BIT_SHIFT_R_TRIG_TIME_SEL_8197F) +#define BIT_R_TRIG_TIME_SEL_8197F(x) \ + (((x) & BIT_MASK_R_TRIG_TIME_SEL_8197F) \ + << BIT_SHIFT_R_TRIG_TIME_SEL_8197F) +#define BITS_R_TRIG_TIME_SEL_8197F \ + (BIT_MASK_R_TRIG_TIME_SEL_8197F << BIT_SHIFT_R_TRIG_TIME_SEL_8197F) #define BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8197F)) -#define BIT_GET_R_TRIG_TIME_SEL_8197F(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8197F) & BIT_MASK_R_TRIG_TIME_SEL_8197F) -#define BIT_SET_R_TRIG_TIME_SEL_8197F(x, v) (BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) | BIT_R_TRIG_TIME_SEL_8197F(v)) - +#define BIT_GET_R_TRIG_TIME_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8197F) & \ + BIT_MASK_R_TRIG_TIME_SEL_8197F) +#define BIT_SET_R_TRIG_TIME_SEL_8197F(x, v) \ + (BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) | BIT_R_TRIG_TIME_SEL_8197F(v)) #define BIT_SHIFT_R_MAC_TRIG_SEL_8197F 6 #define BIT_MASK_R_MAC_TRIG_SEL_8197F 0x3 -#define BIT_R_MAC_TRIG_SEL_8197F(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8197F) << BIT_SHIFT_R_MAC_TRIG_SEL_8197F) -#define BITS_R_MAC_TRIG_SEL_8197F (BIT_MASK_R_MAC_TRIG_SEL_8197F << BIT_SHIFT_R_MAC_TRIG_SEL_8197F) +#define BIT_R_MAC_TRIG_SEL_8197F(x) \ + (((x) & BIT_MASK_R_MAC_TRIG_SEL_8197F) \ + << BIT_SHIFT_R_MAC_TRIG_SEL_8197F) +#define BITS_R_MAC_TRIG_SEL_8197F \ + (BIT_MASK_R_MAC_TRIG_SEL_8197F << BIT_SHIFT_R_MAC_TRIG_SEL_8197F) #define BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8197F)) -#define BIT_GET_R_MAC_TRIG_SEL_8197F(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8197F) & BIT_MASK_R_MAC_TRIG_SEL_8197F) -#define BIT_SET_R_MAC_TRIG_SEL_8197F(x, v) (BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) | BIT_R_MAC_TRIG_SEL_8197F(v)) +#define BIT_GET_R_MAC_TRIG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8197F) & \ + BIT_MASK_R_MAC_TRIG_SEL_8197F) +#define BIT_SET_R_MAC_TRIG_SEL_8197F(x, v) \ + (BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) | BIT_R_MAC_TRIG_SEL_8197F(v)) #define BIT_MAC_TRIG_REG_8197F BIT(5) #define BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F 3 #define BIT_MASK_R_LEVEL_PULSE_SEL_8197F 0x3 -#define BIT_R_LEVEL_PULSE_SEL_8197F(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8197F) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) -#define BITS_R_LEVEL_PULSE_SEL_8197F (BIT_MASK_R_LEVEL_PULSE_SEL_8197F << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) -#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) ((x) & (~BITS_R_LEVEL_PULSE_SEL_8197F)) -#define BIT_GET_R_LEVEL_PULSE_SEL_8197F(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) & BIT_MASK_R_LEVEL_PULSE_SEL_8197F) -#define BIT_SET_R_LEVEL_PULSE_SEL_8197F(x, v) (BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) | BIT_R_LEVEL_PULSE_SEL_8197F(v)) +#define BIT_R_LEVEL_PULSE_SEL_8197F(x) \ + (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8197F) \ + << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) +#define BITS_R_LEVEL_PULSE_SEL_8197F \ + (BIT_MASK_R_LEVEL_PULSE_SEL_8197F << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) \ + ((x) & (~BITS_R_LEVEL_PULSE_SEL_8197F)) +#define BIT_GET_R_LEVEL_PULSE_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) & \ + BIT_MASK_R_LEVEL_PULSE_SEL_8197F) +#define BIT_SET_R_LEVEL_PULSE_SEL_8197F(x, v) \ + (BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) | BIT_R_LEVEL_PULSE_SEL_8197F(v)) #define BIT_EN_LA_MAC_8197F BIT(2) #define BIT_R_EN_IQDUMP_8197F BIT(1) @@ -12932,31 +17099,51 @@ #define BIT_SHIFT_R_TIME_UNIT_SEL_8197F 0 #define BIT_MASK_R_TIME_UNIT_SEL_8197F 0x7 -#define BIT_R_TIME_UNIT_SEL_8197F(x) (((x) & BIT_MASK_R_TIME_UNIT_SEL_8197F) << BIT_SHIFT_R_TIME_UNIT_SEL_8197F) -#define BITS_R_TIME_UNIT_SEL_8197F (BIT_MASK_R_TIME_UNIT_SEL_8197F << BIT_SHIFT_R_TIME_UNIT_SEL_8197F) +#define BIT_R_TIME_UNIT_SEL_8197F(x) \ + (((x) & BIT_MASK_R_TIME_UNIT_SEL_8197F) \ + << BIT_SHIFT_R_TIME_UNIT_SEL_8197F) +#define BITS_R_TIME_UNIT_SEL_8197F \ + (BIT_MASK_R_TIME_UNIT_SEL_8197F << BIT_SHIFT_R_TIME_UNIT_SEL_8197F) #define BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) ((x) & (~BITS_R_TIME_UNIT_SEL_8197F)) -#define BIT_GET_R_TIME_UNIT_SEL_8197F(x) (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL_8197F) & BIT_MASK_R_TIME_UNIT_SEL_8197F) -#define BIT_SET_R_TIME_UNIT_SEL_8197F(x, v) (BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) | BIT_R_TIME_UNIT_SEL_8197F(v)) - +#define BIT_GET_R_TIME_UNIT_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL_8197F) & \ + BIT_MASK_R_TIME_UNIT_SEL_8197F) +#define BIT_SET_R_TIME_UNIT_SEL_8197F(x, v) \ + (BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) | BIT_R_TIME_UNIT_SEL_8197F(v)) /* 2 REG_OFDM_CCK_LEN_MASK_8197F */ #define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F (64 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_RX_FIL_LEN_8197F 0xffff -#define BIT_R_WMAC_RX_FIL_LEN_8197F(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8197F) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) -#define BITS_R_WMAC_RX_FIL_LEN_8197F (BIT_MASK_R_WMAC_RX_FIL_LEN_8197F << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) -#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) ((x) & (~BITS_R_WMAC_RX_FIL_LEN_8197F)) -#define BIT_GET_R_WMAC_RX_FIL_LEN_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) & BIT_MASK_R_WMAC_RX_FIL_LEN_8197F) -#define BIT_SET_R_WMAC_RX_FIL_LEN_8197F(x, v) (BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) | BIT_R_WMAC_RX_FIL_LEN_8197F(v)) - +#define BIT_R_WMAC_RX_FIL_LEN_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8197F) \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) +#define BITS_R_WMAC_RX_FIL_LEN_8197F \ + (BIT_MASK_R_WMAC_RX_FIL_LEN_8197F << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) \ + ((x) & (~BITS_R_WMAC_RX_FIL_LEN_8197F)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) & \ + BIT_MASK_R_WMAC_RX_FIL_LEN_8197F) +#define BIT_SET_R_WMAC_RX_FIL_LEN_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) | BIT_R_WMAC_RX_FIL_LEN_8197F(v)) #define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F (56 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH_8197F(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) -#define BITS_R_WMAC_RXFIFO_FULL_TH_8197F (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) -#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8197F)) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F) -#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8197F(x, v) (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) | BIT_R_WMAC_RXFIFO_FULL_TH_8197F(v)) +#define BIT_R_WMAC_RXFIFO_FULL_TH_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) +#define BITS_R_WMAC_RXFIFO_FULL_TH_8197F \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) \ + ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8197F)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) | \ + BIT_R_WMAC_RXFIFO_FULL_TH_8197F(v)) #define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8197F BIT(55) #define BIT_R_WMAC_RXRST_DLY_8197F BIT(54) @@ -12985,21 +17172,27 @@ #define BIT_SHIFT_R_OFDM_LEN_8197F 26 #define BIT_MASK_R_OFDM_LEN_8197F 0x3f -#define BIT_R_OFDM_LEN_8197F(x) (((x) & BIT_MASK_R_OFDM_LEN_8197F) << BIT_SHIFT_R_OFDM_LEN_8197F) -#define BITS_R_OFDM_LEN_8197F (BIT_MASK_R_OFDM_LEN_8197F << BIT_SHIFT_R_OFDM_LEN_8197F) +#define BIT_R_OFDM_LEN_8197F(x) \ + (((x) & BIT_MASK_R_OFDM_LEN_8197F) << BIT_SHIFT_R_OFDM_LEN_8197F) +#define BITS_R_OFDM_LEN_8197F \ + (BIT_MASK_R_OFDM_LEN_8197F << BIT_SHIFT_R_OFDM_LEN_8197F) #define BIT_CLEAR_R_OFDM_LEN_8197F(x) ((x) & (~BITS_R_OFDM_LEN_8197F)) -#define BIT_GET_R_OFDM_LEN_8197F(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8197F) & BIT_MASK_R_OFDM_LEN_8197F) -#define BIT_SET_R_OFDM_LEN_8197F(x, v) (BIT_CLEAR_R_OFDM_LEN_8197F(x) | BIT_R_OFDM_LEN_8197F(v)) - +#define BIT_GET_R_OFDM_LEN_8197F(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN_8197F) & BIT_MASK_R_OFDM_LEN_8197F) +#define BIT_SET_R_OFDM_LEN_8197F(x, v) \ + (BIT_CLEAR_R_OFDM_LEN_8197F(x) | BIT_R_OFDM_LEN_8197F(v)) #define BIT_SHIFT_R_CCK_LEN_8197F 0 #define BIT_MASK_R_CCK_LEN_8197F 0xffff -#define BIT_R_CCK_LEN_8197F(x) (((x) & BIT_MASK_R_CCK_LEN_8197F) << BIT_SHIFT_R_CCK_LEN_8197F) -#define BITS_R_CCK_LEN_8197F (BIT_MASK_R_CCK_LEN_8197F << BIT_SHIFT_R_CCK_LEN_8197F) +#define BIT_R_CCK_LEN_8197F(x) \ + (((x) & BIT_MASK_R_CCK_LEN_8197F) << BIT_SHIFT_R_CCK_LEN_8197F) +#define BITS_R_CCK_LEN_8197F \ + (BIT_MASK_R_CCK_LEN_8197F << BIT_SHIFT_R_CCK_LEN_8197F) #define BIT_CLEAR_R_CCK_LEN_8197F(x) ((x) & (~BITS_R_CCK_LEN_8197F)) -#define BIT_GET_R_CCK_LEN_8197F(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8197F) & BIT_MASK_R_CCK_LEN_8197F) -#define BIT_SET_R_CCK_LEN_8197F(x, v) (BIT_CLEAR_R_CCK_LEN_8197F(x) | BIT_R_CCK_LEN_8197F(v)) - +#define BIT_GET_R_CCK_LEN_8197F(x) \ + (((x) >> BIT_SHIFT_R_CCK_LEN_8197F) & BIT_MASK_R_CCK_LEN_8197F) +#define BIT_SET_R_CCK_LEN_8197F(x, v) \ + (BIT_CLEAR_R_CCK_LEN_8197F(x) | BIT_R_CCK_LEN_8197F(v)) /* 2 REG_RX_FILTER_FUNCTION_8197F */ #define BIT_R_WMAC_RXHANG_EN_8197F BIT(15) @@ -13023,41 +17216,58 @@ #define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F 0 #define BIT_MASK_R_WMAC_TXNDP_SIGB_8197F 0x1fffff -#define BIT_R_WMAC_TXNDP_SIGB_8197F(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8197F) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) -#define BITS_R_WMAC_TXNDP_SIGB_8197F (BIT_MASK_R_WMAC_TXNDP_SIGB_8197F << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) -#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8197F)) -#define BIT_GET_R_WMAC_TXNDP_SIGB_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) & BIT_MASK_R_WMAC_TXNDP_SIGB_8197F) -#define BIT_SET_R_WMAC_TXNDP_SIGB_8197F(x, v) (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) | BIT_R_WMAC_TXNDP_SIGB_8197F(v)) - +#define BIT_R_WMAC_TXNDP_SIGB_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8197F) \ + << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) +#define BITS_R_WMAC_TXNDP_SIGB_8197F \ + (BIT_MASK_R_WMAC_TXNDP_SIGB_8197F << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) \ + ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8197F)) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) & \ + BIT_MASK_R_WMAC_TXNDP_SIGB_8197F) +#define BIT_SET_R_WMAC_TXNDP_SIGB_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) | BIT_R_WMAC_TXNDP_SIGB_8197F(v)) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8197F */ #define BIT_SHIFT_R_MAC_DEBUG_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_R_MAC_DEBUG_8197F 0xffffffffL -#define BIT_R_MAC_DEBUG_8197F(x) (((x) & BIT_MASK_R_MAC_DEBUG_8197F) << BIT_SHIFT_R_MAC_DEBUG_8197F) -#define BITS_R_MAC_DEBUG_8197F (BIT_MASK_R_MAC_DEBUG_8197F << BIT_SHIFT_R_MAC_DEBUG_8197F) +#define BIT_R_MAC_DEBUG_8197F(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG_8197F) << BIT_SHIFT_R_MAC_DEBUG_8197F) +#define BITS_R_MAC_DEBUG_8197F \ + (BIT_MASK_R_MAC_DEBUG_8197F << BIT_SHIFT_R_MAC_DEBUG_8197F) #define BIT_CLEAR_R_MAC_DEBUG_8197F(x) ((x) & (~BITS_R_MAC_DEBUG_8197F)) -#define BIT_GET_R_MAC_DEBUG_8197F(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_8197F) & BIT_MASK_R_MAC_DEBUG_8197F) -#define BIT_SET_R_MAC_DEBUG_8197F(x, v) (BIT_CLEAR_R_MAC_DEBUG_8197F(x) | BIT_R_MAC_DEBUG_8197F(v)) - +#define BIT_GET_R_MAC_DEBUG_8197F(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG_8197F) & BIT_MASK_R_MAC_DEBUG_8197F) +#define BIT_SET_R_MAC_DEBUG_8197F(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG_8197F(x) | BIT_R_MAC_DEBUG_8197F(v)) #define BIT_SHIFT_R_MAC_DBG_SHIFT_8197F 8 #define BIT_MASK_R_MAC_DBG_SHIFT_8197F 0x7 -#define BIT_R_MAC_DBG_SHIFT_8197F(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8197F) << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) -#define BITS_R_MAC_DBG_SHIFT_8197F (BIT_MASK_R_MAC_DBG_SHIFT_8197F << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) +#define BIT_R_MAC_DBG_SHIFT_8197F(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8197F) \ + << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) +#define BITS_R_MAC_DBG_SHIFT_8197F \ + (BIT_MASK_R_MAC_DBG_SHIFT_8197F << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) #define BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8197F)) -#define BIT_GET_R_MAC_DBG_SHIFT_8197F(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) & BIT_MASK_R_MAC_DBG_SHIFT_8197F) -#define BIT_SET_R_MAC_DBG_SHIFT_8197F(x, v) (BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) | BIT_R_MAC_DBG_SHIFT_8197F(v)) - +#define BIT_GET_R_MAC_DBG_SHIFT_8197F(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) & \ + BIT_MASK_R_MAC_DBG_SHIFT_8197F) +#define BIT_SET_R_MAC_DBG_SHIFT_8197F(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) | BIT_R_MAC_DBG_SHIFT_8197F(v)) #define BIT_SHIFT_R_MAC_DBG_SEL_8197F 0 #define BIT_MASK_R_MAC_DBG_SEL_8197F 0x3 -#define BIT_R_MAC_DBG_SEL_8197F(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8197F) << BIT_SHIFT_R_MAC_DBG_SEL_8197F) -#define BITS_R_MAC_DBG_SEL_8197F (BIT_MASK_R_MAC_DBG_SEL_8197F << BIT_SHIFT_R_MAC_DBG_SEL_8197F) +#define BIT_R_MAC_DBG_SEL_8197F(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SEL_8197F) << BIT_SHIFT_R_MAC_DBG_SEL_8197F) +#define BITS_R_MAC_DBG_SEL_8197F \ + (BIT_MASK_R_MAC_DBG_SEL_8197F << BIT_SHIFT_R_MAC_DBG_SEL_8197F) #define BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) ((x) & (~BITS_R_MAC_DBG_SEL_8197F)) -#define BIT_GET_R_MAC_DBG_SEL_8197F(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8197F) & BIT_MASK_R_MAC_DBG_SEL_8197F) -#define BIT_SET_R_MAC_DBG_SEL_8197F(x, v) (BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) | BIT_R_MAC_DBG_SEL_8197F(v)) - +#define BIT_GET_R_MAC_DBG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8197F) & BIT_MASK_R_MAC_DBG_SEL_8197F) +#define BIT_SET_R_MAC_DBG_SEL_8197F(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) | BIT_R_MAC_DBG_SEL_8197F(v)) /* 2 REG_SEC_OPT_V2_8197F */ #define BIT_MASK_IV_8197F BIT(18) @@ -13066,12 +17276,15 @@ #define BIT_SHIFT_BT_TIME_CNT_8197F 0 #define BIT_MASK_BT_TIME_CNT_8197F 0xff -#define BIT_BT_TIME_CNT_8197F(x) (((x) & BIT_MASK_BT_TIME_CNT_8197F) << BIT_SHIFT_BT_TIME_CNT_8197F) -#define BITS_BT_TIME_CNT_8197F (BIT_MASK_BT_TIME_CNT_8197F << BIT_SHIFT_BT_TIME_CNT_8197F) +#define BIT_BT_TIME_CNT_8197F(x) \ + (((x) & BIT_MASK_BT_TIME_CNT_8197F) << BIT_SHIFT_BT_TIME_CNT_8197F) +#define BITS_BT_TIME_CNT_8197F \ + (BIT_MASK_BT_TIME_CNT_8197F << BIT_SHIFT_BT_TIME_CNT_8197F) #define BIT_CLEAR_BT_TIME_CNT_8197F(x) ((x) & (~BITS_BT_TIME_CNT_8197F)) -#define BIT_GET_BT_TIME_CNT_8197F(x) (((x) >> BIT_SHIFT_BT_TIME_CNT_8197F) & BIT_MASK_BT_TIME_CNT_8197F) -#define BIT_SET_BT_TIME_CNT_8197F(x, v) (BIT_CLEAR_BT_TIME_CNT_8197F(x) | BIT_BT_TIME_CNT_8197F(v)) - +#define BIT_GET_BT_TIME_CNT_8197F(x) \ + (((x) >> BIT_SHIFT_BT_TIME_CNT_8197F) & BIT_MASK_BT_TIME_CNT_8197F) +#define BIT_SET_BT_TIME_CNT_8197F(x, v) \ + (BIT_CLEAR_BT_TIME_CNT_8197F(x) | BIT_BT_TIME_CNT_8197F(v)) /* 2 REG_RTS_ADDRESS_0_8197F */ diff --git a/hal/halmac/halmac_bit_8814b.h b/hal/halmac/halmac_bit_8814b.h index 0db3a36..928e37e 100644 --- a/hal/halmac/halmac_bit_8814b.h +++ b/hal/halmac/halmac_bit_8814b.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -22,7 +22,8 @@ /* 2 REG_SYS_ISO_CTRL_8814B */ #define BIT_PWC_EV12V_8814B BIT(15) -#define BIT_PWC_EV25V_8814B BIT(14) + +/* 2 REG_NOT_VALID_8814B */ #define BIT_PA33V_EN_8814B BIT(13) #define BIT_PA12V_EN_8814B BIT(12) #define BIT_UA33V_EN_8814B BIT(11) @@ -41,7 +42,8 @@ /* 2 REG_SYS_FUNC_EN_8814B */ #define BIT_FEN_MREGEN_8814B BIT(15) #define BIT_FEN_HWPDN_8814B BIT(14) -#define BIT_EN_25_1_8814B BIT(13) + +/* 2 REG_NOT_VALID_8814B */ #define BIT_FEN_ELDR_8814B BIT(12) #define BIT_FEN_DCORE_8814B BIT(11) #define BIT_FEN_CPUEN_8814B BIT(10) @@ -78,14 +80,15 @@ #define BIT_APFN_ONMAC_8814B BIT(8) #define BIT_CHIP_PDN_EN_8814B BIT(7) #define BIT_RDY_MACDIS_8814B BIT(6) -#define BIT_RING_CLK_12M_EN_8814B BIT(4) + +/* 2 REG_NOT_VALID_8814B */ #define BIT_PFM_WOWL_8814B BIT(3) #define BIT_PFM_LDKP_8814B BIT(2) #define BIT_WL_HCI_ALD_8814B BIT(1) #define BIT_PFM_LDALL_8814B BIT(0) /* 2 REG_SYS_CLK_CTRL_8814B */ -#define BIT_LDO_DUMMY_8814B BIT(15) +#define BIT_DATA_CPU_CLK_EN_8814B BIT(15) #define BIT_CPU_CLK_EN_8814B BIT(14) #define BIT_SYMREG_CLK_EN_8814B BIT(13) #define BIT_HCI_CLK_EN_8814B BIT(12) @@ -99,23 +102,33 @@ #define BIT_MACSLP_8814B BIT(4) #define BIT_WAKEPAD_EN_8814B BIT(3) #define BIT_ROMD16V_EN_8814B BIT(2) -#define BIT_CKANA12M_EN_8814B BIT(1) + +/* 2 REG_NOT_VALID_8814B */ #define BIT_CNTD16V_EN_8814B BIT(0) /* 2 REG_SYS_EEPROM_CTRL_8814B */ #define BIT_SHIFT_VPDIDX_8814B 8 #define BIT_MASK_VPDIDX_8814B 0xff -#define BIT_VPDIDX_8814B(x) (((x) & BIT_MASK_VPDIDX_8814B) << BIT_SHIFT_VPDIDX_8814B) -#define BIT_GET_VPDIDX_8814B(x) (((x) >> BIT_SHIFT_VPDIDX_8814B) & BIT_MASK_VPDIDX_8814B) - - +#define BIT_VPDIDX_8814B(x) \ + (((x) & BIT_MASK_VPDIDX_8814B) << BIT_SHIFT_VPDIDX_8814B) +#define BITS_VPDIDX_8814B (BIT_MASK_VPDIDX_8814B << BIT_SHIFT_VPDIDX_8814B) +#define BIT_CLEAR_VPDIDX_8814B(x) ((x) & (~BITS_VPDIDX_8814B)) +#define BIT_GET_VPDIDX_8814B(x) \ + (((x) >> BIT_SHIFT_VPDIDX_8814B) & BIT_MASK_VPDIDX_8814B) +#define BIT_SET_VPDIDX_8814B(x, v) \ + (BIT_CLEAR_VPDIDX_8814B(x) | BIT_VPDIDX_8814B(v)) #define BIT_SHIFT_EEM1_0_8814B 6 #define BIT_MASK_EEM1_0_8814B 0x3 -#define BIT_EEM1_0_8814B(x) (((x) & BIT_MASK_EEM1_0_8814B) << BIT_SHIFT_EEM1_0_8814B) -#define BIT_GET_EEM1_0_8814B(x) (((x) >> BIT_SHIFT_EEM1_0_8814B) & BIT_MASK_EEM1_0_8814B) - +#define BIT_EEM1_0_8814B(x) \ + (((x) & BIT_MASK_EEM1_0_8814B) << BIT_SHIFT_EEM1_0_8814B) +#define BITS_EEM1_0_8814B (BIT_MASK_EEM1_0_8814B << BIT_SHIFT_EEM1_0_8814B) +#define BIT_CLEAR_EEM1_0_8814B(x) ((x) & (~BITS_EEM1_0_8814B)) +#define BIT_GET_EEM1_0_8814B(x) \ + (((x) >> BIT_SHIFT_EEM1_0_8814B) & BIT_MASK_EEM1_0_8814B) +#define BIT_SET_EEM1_0_8814B(x, v) \ + (BIT_CLEAR_EEM1_0_8814B(x) | BIT_EEM1_0_8814B(v)) #define BIT_AUTOLOAD_SUS_8814B BIT(5) #define BIT_EERPOMSEL_8814B BIT(4) @@ -128,150 +141,126 @@ #define BIT_SHIFT_VPD_DATA_8814B 0 #define BIT_MASK_VPD_DATA_8814B 0xffffffffL -#define BIT_VPD_DATA_8814B(x) (((x) & BIT_MASK_VPD_DATA_8814B) << BIT_SHIFT_VPD_DATA_8814B) -#define BIT_GET_VPD_DATA_8814B(x) (((x) >> BIT_SHIFT_VPD_DATA_8814B) & BIT_MASK_VPD_DATA_8814B) - - +#define BIT_VPD_DATA_8814B(x) \ + (((x) & BIT_MASK_VPD_DATA_8814B) << BIT_SHIFT_VPD_DATA_8814B) +#define BITS_VPD_DATA_8814B \ + (BIT_MASK_VPD_DATA_8814B << BIT_SHIFT_VPD_DATA_8814B) +#define BIT_CLEAR_VPD_DATA_8814B(x) ((x) & (~BITS_VPD_DATA_8814B)) +#define BIT_GET_VPD_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_VPD_DATA_8814B) & BIT_MASK_VPD_DATA_8814B) +#define BIT_SET_VPD_DATA_8814B(x, v) \ + (BIT_CLEAR_VPD_DATA_8814B(x) | BIT_VPD_DATA_8814B(v)) /* 2 REG_SYS_SWR_CTRL1_8814B */ -#define BIT_C2_L_BIT0_8814B BIT(31) - -#define BIT_SHIFT_C1_L_8814B 29 -#define BIT_MASK_C1_L_8814B 0x3 -#define BIT_C1_L_8814B(x) (((x) & BIT_MASK_C1_L_8814B) << BIT_SHIFT_C1_L_8814B) -#define BIT_GET_C1_L_8814B(x) (((x) >> BIT_SHIFT_C1_L_8814B) & BIT_MASK_C1_L_8814B) - +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG_FREQ_L_8814B 25 -#define BIT_MASK_REG_FREQ_L_8814B 0x7 -#define BIT_REG_FREQ_L_8814B(x) (((x) & BIT_MASK_REG_FREQ_L_8814B) << BIT_SHIFT_REG_FREQ_L_8814B) -#define BIT_GET_REG_FREQ_L_8814B(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8814B) & BIT_MASK_REG_FREQ_L_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_EN_DUTY_8814B BIT(24) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG_MODE_8814B 22 -#define BIT_MASK_REG_MODE_8814B 0x3 -#define BIT_REG_MODE_8814B(x) (((x) & BIT_MASK_REG_MODE_8814B) << BIT_SHIFT_REG_MODE_8814B) -#define BIT_GET_REG_MODE_8814B(x) (((x) >> BIT_SHIFT_REG_MODE_8814B) & BIT_MASK_REG_MODE_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_EN_SP_8814B BIT(21) -#define BIT_REG_AUTO_L_8814B BIT(20) -#define BIT_SW18_SELD_BIT0_8814B BIT(19) -#define BIT_SW18_POWOCP_8814B BIT(18) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_OCP_L1_8814B 15 -#define BIT_MASK_OCP_L1_8814B 0x7 -#define BIT_OCP_L1_8814B(x) (((x) & BIT_MASK_OCP_L1_8814B) << BIT_SHIFT_OCP_L1_8814B) -#define BIT_GET_OCP_L1_8814B(x) (((x) >> BIT_SHIFT_OCP_L1_8814B) & BIT_MASK_OCP_L1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CF_L_8814B 13 -#define BIT_MASK_CF_L_8814B 0x3 -#define BIT_CF_L_8814B(x) (((x) & BIT_MASK_CF_L_8814B) << BIT_SHIFT_CF_L_8814B) -#define BIT_GET_CF_L_8814B(x) (((x) >> BIT_SHIFT_CF_L_8814B) & BIT_MASK_CF_L_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CTRL_SPS_PWM_FREQ_8814B BIT(10) -#define BIT_SW18_FPWM_8814B BIT(11) -#define BIT_SW18_SWEN_8814B BIT(9) -#define BIT_SW18_LDEN_8814B BIT(8) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_DISABLE_OPEN_SPS_LDO_8814B BIT(8) #define BIT_MAC_ID_EN_8814B BIT(7) -#define BIT_AFE_BGEN_8814B BIT(0) - -/* 2 REG_SYS_SWR_CTRL2_8814B */ -#define BIT_POW_ZCD_L_8814B BIT(31) -#define BIT_AUTOZCD_L_8814B BIT(30) - -#define BIT_SHIFT_REG_DELAY_8814B 28 -#define BIT_MASK_REG_DELAY_8814B 0x3 -#define BIT_REG_DELAY_8814B(x) (((x) & BIT_MASK_REG_DELAY_8814B) << BIT_SHIFT_REG_DELAY_8814B) -#define BIT_GET_REG_DELAY_8814B(x) (((x) >> BIT_SHIFT_REG_DELAY_8814B) & BIT_MASK_REG_DELAY_8814B) - - - -#define BIT_SHIFT_V15ADJ_L1_V1_8814B 24 -#define BIT_MASK_V15ADJ_L1_V1_8814B 0x7 -#define BIT_V15ADJ_L1_V1_8814B(x) (((x) & BIT_MASK_V15ADJ_L1_V1_8814B) << BIT_SHIFT_V15ADJ_L1_V1_8814B) -#define BIT_GET_V15ADJ_L1_V1_8814B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8814B) & BIT_MASK_V15ADJ_L1_V1_8814B) - - - -#define BIT_SHIFT_VOL_L1_V1_8814B 20 -#define BIT_MASK_VOL_L1_V1_8814B 0xf -#define BIT_VOL_L1_V1_8814B(x) (((x) & BIT_MASK_VOL_L1_V1_8814B) << BIT_SHIFT_VOL_L1_V1_8814B) -#define BIT_GET_VOL_L1_V1_8814B(x) (((x) >> BIT_SHIFT_VOL_L1_V1_8814B) & BIT_MASK_VOL_L1_V1_8814B) - - - -#define BIT_SHIFT_IN_L1_V1_8814B 17 -#define BIT_MASK_IN_L1_V1_8814B 0x7 -#define BIT_IN_L1_V1_8814B(x) (((x) & BIT_MASK_IN_L1_V1_8814B) << BIT_SHIFT_IN_L1_V1_8814B) -#define BIT_GET_IN_L1_V1_8814B(x) (((x) >> BIT_SHIFT_IN_L1_V1_8814B) & BIT_MASK_IN_L1_V1_8814B) +#define BIT_WL_CTRL_XTAL_CADJ_8814B BIT(6) +#define BIT_AFE_BGEN_PCIE_OP_8814B BIT(2) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_SYS_SWR_CTRL2_8814B */ -#define BIT_SHIFT_TBOX_L1_8814B 15 -#define BIT_MASK_TBOX_L1_8814B 0x3 -#define BIT_TBOX_L1_8814B(x) (((x) & BIT_MASK_TBOX_L1_8814B) << BIT_SHIFT_TBOX_L1_8814B) -#define BIT_GET_TBOX_L1_8814B(x) (((x) >> BIT_SHIFT_TBOX_L1_8814B) & BIT_MASK_TBOX_L1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SW18_SEL_8814B BIT(13) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SW18_SD_8814B BIT(10) -#define BIT_SHIFT_R3_L_8814B 7 -#define BIT_MASK_R3_L_8814B 0x3 -#define BIT_R3_L_8814B(x) (((x) & BIT_MASK_R3_L_8814B) << BIT_SHIFT_R3_L_8814B) -#define BIT_GET_R3_L_8814B(x) (((x) >> BIT_SHIFT_R3_L_8814B) & BIT_MASK_R3_L_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SW18_R2_8814B 5 -#define BIT_MASK_SW18_R2_8814B 0x3 -#define BIT_SW18_R2_8814B(x) (((x) & BIT_MASK_SW18_R2_8814B) << BIT_SHIFT_SW18_R2_8814B) -#define BIT_GET_SW18_R2_8814B(x) (((x) >> BIT_SHIFT_SW18_R2_8814B) & BIT_MASK_SW18_R2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SW18_R1_8814B 3 -#define BIT_MASK_SW18_R1_8814B 0x3 -#define BIT_SW18_R1_8814B(x) (((x) & BIT_MASK_SW18_R1_8814B) << BIT_SHIFT_SW18_R1_8814B) -#define BIT_GET_SW18_R1_8814B(x) (((x) >> BIT_SHIFT_SW18_R1_8814B) & BIT_MASK_SW18_R1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_C3_L_C3_8814B 1 -#define BIT_MASK_C3_L_C3_8814B 0x3 -#define BIT_C3_L_C3_8814B(x) (((x) & BIT_MASK_C3_L_C3_8814B) << BIT_SHIFT_C3_L_C3_8814B) -#define BIT_GET_C3_L_C3_8814B(x) (((x) >> BIT_SHIFT_C3_L_C3_8814B) & BIT_MASK_C3_L_C3_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_C2_L_BIT1_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_SYS_SWR_CTRL3_8814B */ #define BIT_SPS18_OCP_DIS_8814B BIT(31) #define BIT_SHIFT_SPS18_OCP_TH_8814B 16 #define BIT_MASK_SPS18_OCP_TH_8814B 0x7fff -#define BIT_SPS18_OCP_TH_8814B(x) (((x) & BIT_MASK_SPS18_OCP_TH_8814B) << BIT_SHIFT_SPS18_OCP_TH_8814B) -#define BIT_GET_SPS18_OCP_TH_8814B(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8814B) & BIT_MASK_SPS18_OCP_TH_8814B) - - +#define BIT_SPS18_OCP_TH_8814B(x) \ + (((x) & BIT_MASK_SPS18_OCP_TH_8814B) << BIT_SHIFT_SPS18_OCP_TH_8814B) +#define BITS_SPS18_OCP_TH_8814B \ + (BIT_MASK_SPS18_OCP_TH_8814B << BIT_SHIFT_SPS18_OCP_TH_8814B) +#define BIT_CLEAR_SPS18_OCP_TH_8814B(x) ((x) & (~BITS_SPS18_OCP_TH_8814B)) +#define BIT_GET_SPS18_OCP_TH_8814B(x) \ + (((x) >> BIT_SHIFT_SPS18_OCP_TH_8814B) & BIT_MASK_SPS18_OCP_TH_8814B) +#define BIT_SET_SPS18_OCP_TH_8814B(x, v) \ + (BIT_CLEAR_SPS18_OCP_TH_8814B(x) | BIT_SPS18_OCP_TH_8814B(v)) #define BIT_SHIFT_OCP_WINDOW_8814B 0 #define BIT_MASK_OCP_WINDOW_8814B 0xffff -#define BIT_OCP_WINDOW_8814B(x) (((x) & BIT_MASK_OCP_WINDOW_8814B) << BIT_SHIFT_OCP_WINDOW_8814B) -#define BIT_GET_OCP_WINDOW_8814B(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8814B) & BIT_MASK_OCP_WINDOW_8814B) +#define BIT_OCP_WINDOW_8814B(x) \ + (((x) & BIT_MASK_OCP_WINDOW_8814B) << BIT_SHIFT_OCP_WINDOW_8814B) +#define BITS_OCP_WINDOW_8814B \ + (BIT_MASK_OCP_WINDOW_8814B << BIT_SHIFT_OCP_WINDOW_8814B) +#define BIT_CLEAR_OCP_WINDOW_8814B(x) ((x) & (~BITS_OCP_WINDOW_8814B)) +#define BIT_GET_OCP_WINDOW_8814B(x) \ + (((x) >> BIT_SHIFT_OCP_WINDOW_8814B) & BIT_MASK_OCP_WINDOW_8814B) +#define BIT_SET_OCP_WINDOW_8814B(x, v) \ + (BIT_CLEAR_OCP_WINDOW_8814B(x) | BIT_OCP_WINDOW_8814B(v)) +/* 2 REG_RSV_CTRL_8814B */ +#define BIT_SHIFT_HREG_DBG_V1_8814B 12 +#define BIT_MASK_HREG_DBG_V1_8814B 0xfff +#define BIT_HREG_DBG_V1_8814B(x) \ + (((x) & BIT_MASK_HREG_DBG_V1_8814B) << BIT_SHIFT_HREG_DBG_V1_8814B) +#define BITS_HREG_DBG_V1_8814B \ + (BIT_MASK_HREG_DBG_V1_8814B << BIT_SHIFT_HREG_DBG_V1_8814B) +#define BIT_CLEAR_HREG_DBG_V1_8814B(x) ((x) & (~BITS_HREG_DBG_V1_8814B)) +#define BIT_GET_HREG_DBG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_HREG_DBG_V1_8814B) & BIT_MASK_HREG_DBG_V1_8814B) +#define BIT_SET_HREG_DBG_V1_8814B(x, v) \ + (BIT_CLEAR_HREG_DBG_V1_8814B(x) | BIT_HREG_DBG_V1_8814B(v)) -/* 2 REG_RSV_CTRL_8814B */ -#define BIT_HREG_DBG_8814B BIT(23) #define BIT_WLMCUIOIF_8814B BIT(8) #define BIT_LOCK_ALL_EN_8814B BIT(7) #define BIT_R_DIS_PRST_8814B BIT(6) @@ -289,306 +278,298 @@ /* 2 REG_AFE_LDO_CTRL_8814B */ -#define BIT_SHIFT_LPLDH12_RSV_8814B 29 -#define BIT_MASK_LPLDH12_RSV_8814B 0x7 -#define BIT_LPLDH12_RSV_8814B(x) (((x) & BIT_MASK_LPLDH12_RSV_8814B) << BIT_SHIFT_LPLDH12_RSV_8814B) -#define BIT_GET_LPLDH12_RSV_8814B(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8814B) & BIT_MASK_LPLDH12_RSV_8814B) - - -#define BIT_LPLDH12_SLP_8814B BIT(28) - -#define BIT_SHIFT_LPLDH12_VADJ_8814B 24 -#define BIT_MASK_LPLDH12_VADJ_8814B 0xf -#define BIT_LPLDH12_VADJ_8814B(x) (((x) & BIT_MASK_LPLDH12_VADJ_8814B) << BIT_SHIFT_LPLDH12_VADJ_8814B) -#define BIT_GET_LPLDH12_VADJ_8814B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8814B) & BIT_MASK_LPLDH12_VADJ_8814B) - +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CPHY_LDO_CL_EN_8814B BIT(19) +#define BIT_CPHY_LDO_OK_8814B BIT(18) #define BIT_PCIE_CALIB_EN_8814B BIT(17) #define BIT_LDH12_EN_8814B BIT(16) +#define BIT_DATA_CPU_PWC_8814B BIT(15) #define BIT_WLBBOFF_BIG_PWC_EN_8814B BIT(14) #define BIT_WLBBOFF_SMALL_PWC_EN_8814B BIT(13) #define BIT_WLMACOFF_BIG_PWC_EN_8814B BIT(12) #define BIT_WLPON_PWC_EN_8814B BIT(11) -#define BIT_POW_REGU_P1_8814B BIT(10) -#define BIT_LDOV12W_EN_8814B BIT(8) -#define BIT_EX_XTAL_DRV_DIGI_8814B BIT(7) -#define BIT_EX_XTAL_DRV_USB_8814B BIT(6) -#define BIT_EX_XTAL_DRV_AFE_8814B BIT(5) -#define BIT_EX_XTAL_DRV_RF2_8814B BIT(4) -#define BIT_EX_XTAL_DRV_RF1_8814B BIT(3) -#define BIT_POW_REGU_P0_8814B BIT(2) /* 2 REG_NOT_VALID_8814B */ -#define BIT_POW_PLL_LDO_8814B BIT(0) - -/* 2 REG_AFE_CTRL1_8814B */ -#define BIT_AGPIO_GPE_8814B BIT(31) - -#define BIT_SHIFT_XTAL_CAP_XI_8814B 25 -#define BIT_MASK_XTAL_CAP_XI_8814B 0x3f -#define BIT_XTAL_CAP_XI_8814B(x) (((x) & BIT_MASK_XTAL_CAP_XI_8814B) << BIT_SHIFT_XTAL_CAP_XI_8814B) -#define BIT_GET_XTAL_CAP_XI_8814B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8814B) & BIT_MASK_XTAL_CAP_XI_8814B) - - - -#define BIT_SHIFT_XTAL_DRV_DIGI_8814B 23 -#define BIT_MASK_XTAL_DRV_DIGI_8814B 0x3 -#define BIT_XTAL_DRV_DIGI_8814B(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8814B) << BIT_SHIFT_XTAL_DRV_DIGI_8814B) -#define BIT_GET_XTAL_DRV_DIGI_8814B(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8814B) & BIT_MASK_XTAL_DRV_DIGI_8814B) - - -#define BIT_XTAL_DRV_USB_BIT1_8814B BIT(22) - -#define BIT_SHIFT_MAC_CLK_SEL_8814B 20 -#define BIT_MASK_MAC_CLK_SEL_8814B 0x3 -#define BIT_MAC_CLK_SEL_8814B(x) (((x) & BIT_MASK_MAC_CLK_SEL_8814B) << BIT_SHIFT_MAC_CLK_SEL_8814B) -#define BIT_GET_MAC_CLK_SEL_8814B(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8814B) & BIT_MASK_MAC_CLK_SEL_8814B) - - -#define BIT_XTAL_DRV_USB_BIT0_8814B BIT(19) - -#define BIT_SHIFT_XTAL_DRV_AFE_8814B 17 -#define BIT_MASK_XTAL_DRV_AFE_8814B 0x3 -#define BIT_XTAL_DRV_AFE_8814B(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8814B) << BIT_SHIFT_XTAL_DRV_AFE_8814B) -#define BIT_GET_XTAL_DRV_AFE_8814B(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8814B) & BIT_MASK_XTAL_DRV_AFE_8814B) +#define BIT_LDOV12W_EN_8814B BIT(8) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_XTAL_DRV_RF2_8814B 15 -#define BIT_MASK_XTAL_DRV_RF2_8814B 0x3 -#define BIT_XTAL_DRV_RF2_8814B(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8814B) << BIT_SHIFT_XTAL_DRV_RF2_8814B) -#define BIT_GET_XTAL_DRV_RF2_8814B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8814B) & BIT_MASK_XTAL_DRV_RF2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_XTAL_DRV_RF1_8814B 13 -#define BIT_MASK_XTAL_DRV_RF1_8814B 0x3 -#define BIT_XTAL_DRV_RF1_8814B(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8814B) << BIT_SHIFT_XTAL_DRV_RF1_8814B) -#define BIT_GET_XTAL_DRV_RF1_8814B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8814B) & BIT_MASK_XTAL_DRV_RF1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_XTAL_DELAY_DIGI_8814B BIT(12) -#define BIT_XTAL_DELAY_USB_8814B BIT(11) -#define BIT_XTAL_DELAY_AFE_8814B BIT(10) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_XTAL_LDO_VREF_8814B 7 -#define BIT_MASK_XTAL_LDO_VREF_8814B 0x7 -#define BIT_XTAL_LDO_VREF_8814B(x) (((x) & BIT_MASK_XTAL_LDO_VREF_8814B) << BIT_SHIFT_XTAL_LDO_VREF_8814B) -#define BIT_GET_XTAL_LDO_VREF_8814B(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8814B) & BIT_MASK_XTAL_LDO_VREF_8814B) +/* 2 REG_AFE_CTRL1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_XTAL_XQSEL_RF_8814B BIT(6) -#define BIT_XTAL_XQSEL_8814B BIT(5) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_XTAL_GMN_V2_8814B 3 -#define BIT_MASK_XTAL_GMN_V2_8814B 0x3 -#define BIT_XTAL_GMN_V2_8814B(x) (((x) & BIT_MASK_XTAL_GMN_V2_8814B) << BIT_SHIFT_XTAL_GMN_V2_8814B) -#define BIT_GET_XTAL_GMN_V2_8814B(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2_8814B) & BIT_MASK_XTAL_GMN_V2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_MAC_CLK_SEL_8814B 20 +#define BIT_MASK_MAC_CLK_SEL_8814B 0x3 +#define BIT_MAC_CLK_SEL_8814B(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL_8814B) << BIT_SHIFT_MAC_CLK_SEL_8814B) +#define BITS_MAC_CLK_SEL_8814B \ + (BIT_MASK_MAC_CLK_SEL_8814B << BIT_SHIFT_MAC_CLK_SEL_8814B) +#define BIT_CLEAR_MAC_CLK_SEL_8814B(x) ((x) & (~BITS_MAC_CLK_SEL_8814B)) +#define BIT_GET_MAC_CLK_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL_8814B) & BIT_MASK_MAC_CLK_SEL_8814B) +#define BIT_SET_MAC_CLK_SEL_8814B(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL_8814B(x) | BIT_MAC_CLK_SEL_8814B(v)) -#define BIT_SHIFT_XTAL_GMP_V2_8814B 1 -#define BIT_MASK_XTAL_GMP_V2_8814B 0x3 -#define BIT_XTAL_GMP_V2_8814B(x) (((x) & BIT_MASK_XTAL_GMP_V2_8814B) << BIT_SHIFT_XTAL_GMP_V2_8814B) -#define BIT_GET_XTAL_GMP_V2_8814B(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2_8814B) & BIT_MASK_XTAL_GMP_V2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_XTAL_EN_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_AFE_CTRL2_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG_C3_V4_8814B 30 -#define BIT_MASK_REG_C3_V4_8814B 0x3 -#define BIT_REG_C3_V4_8814B(x) (((x) & BIT_MASK_REG_C3_V4_8814B) << BIT_SHIFT_REG_C3_V4_8814B) -#define BIT_GET_REG_C3_V4_8814B(x) (((x) >> BIT_SHIFT_REG_C3_V4_8814B) & BIT_MASK_REG_C3_V4_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_CP_BIT1_8814B BIT(29) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG_RS_V4_8814B 26 -#define BIT_MASK_REG_RS_V4_8814B 0x7 -#define BIT_REG_RS_V4_8814B(x) (((x) & BIT_MASK_REG_RS_V4_8814B) << BIT_SHIFT_REG_RS_V4_8814B) -#define BIT_GET_REG_RS_V4_8814B(x) (((x) >> BIT_SHIFT_REG_RS_V4_8814B) & BIT_MASK_REG_RS_V4_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG__CS_8814B 24 -#define BIT_MASK_REG__CS_8814B 0x3 -#define BIT_REG__CS_8814B(x) (((x) & BIT_MASK_REG__CS_8814B) << BIT_SHIFT_REG__CS_8814B) -#define BIT_GET_REG__CS_8814B(x) (((x) >> BIT_SHIFT_REG__CS_8814B) & BIT_MASK_REG__CS_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_ANAPARSW_POW_MAC_8814B */ -#define BIT_SHIFT_REG_CP_OFFSET_8814B 21 -#define BIT_MASK_REG_CP_OFFSET_8814B 0x7 -#define BIT_REG_CP_OFFSET_8814B(x) (((x) & BIT_MASK_REG_CP_OFFSET_8814B) << BIT_SHIFT_REG_CP_OFFSET_8814B) -#define BIT_GET_REG_CP_OFFSET_8814B(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_8814B) & BIT_MASK_REG_CP_OFFSET_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CP_BIAS_8814B 18 -#define BIT_MASK_CP_BIAS_8814B 0x7 -#define BIT_CP_BIAS_8814B(x) (((x) & BIT_MASK_CP_BIAS_8814B) << BIT_SHIFT_CP_BIAS_8814B) -#define BIT_GET_CP_BIAS_8814B(x) (((x) >> BIT_SHIFT_CP_BIAS_8814B) & BIT_MASK_CP_BIAS_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_ENB_LDO_DIODE_L_8814B BIT(3) +#define BIT_POW_LDO15_8814B BIT(2) +#define BIT_POW_SW_8814B BIT(1) +#define BIT_POW_LDO14_8814B BIT(0) +/* 2 REG_ANAPARLDO_POW_MAC_8814B */ -#define BIT_REG_IDOUBLE_V2_8814B BIT(17) -#define BIT_EN_SYN_8814B BIT(16) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_MCCO_8814B 14 -#define BIT_MASK_MCCO_8814B 0x3 -#define BIT_MCCO_8814B(x) (((x) & BIT_MASK_MCCO_8814B) << BIT_SHIFT_MCCO_8814B) -#define BIT_GET_MCCO_8814B(x) (((x) >> BIT_SHIFT_MCCO_8814B) & BIT_MASK_MCCO_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG_LDO_SEL_8814B 12 -#define BIT_MASK_REG_LDO_SEL_8814B 0x3 -#define BIT_REG_LDO_SEL_8814B(x) (((x) & BIT_MASK_REG_LDO_SEL_8814B) << BIT_SHIFT_REG_LDO_SEL_8814B) -#define BIT_GET_REG_LDO_SEL_8814B(x) (((x) >> BIT_SHIFT_REG_LDO_SEL_8814B) & BIT_MASK_REG_LDO_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_KVCO_V2_8814B BIT(10) -#define BIT_AGPIO_GPO_8814B BIT(9) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_LDOE25_POW_L_8814B BIT(0) -#define BIT_SHIFT_AGPIO_DRV_8814B 7 -#define BIT_MASK_AGPIO_DRV_8814B 0x3 -#define BIT_AGPIO_DRV_8814B(x) (((x) & BIT_MASK_AGPIO_DRV_8814B) << BIT_SHIFT_AGPIO_DRV_8814B) -#define BIT_GET_AGPIO_DRV_8814B(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8814B) & BIT_MASK_AGPIO_DRV_8814B) +/* 2 REG_ANAPAR_POW_MAC_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_POW_PC_LDO3_8814B BIT(5) +#define BIT_POW_PC_LDO2_8814B BIT(4) +#define BIT_POW_PC_LDO1_8814B BIT(3) +#define BIT_POW_PC_LDO0_8814B BIT(2) +#define BIT_POW_PLL_V1_8814B BIT(1) +#define BIT_POW_POWER_CUT_8814B BIT(0) -#define BIT_SHIFT_XTAL_CAP_XO_8814B 1 -#define BIT_MASK_XTAL_CAP_XO_8814B 0x3f -#define BIT_XTAL_CAP_XO_8814B(x) (((x) & BIT_MASK_XTAL_CAP_XO_8814B) << BIT_SHIFT_XTAL_CAP_XO_8814B) -#define BIT_GET_XTAL_CAP_XO_8814B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8814B) & BIT_MASK_XTAL_CAP_XO_8814B) +/* 2 REG_ANAPAR_POW_XTAL_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_POW_PLL_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_AFE_CTRL3_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_8814B 7 -#define BIT_MASK_PS_8814B 0x7 -#define BIT_PS_8814B(x) (((x) & BIT_MASK_PS_8814B) << BIT_SHIFT_PS_8814B) -#define BIT_GET_PS_8814B(x) (((x) >> BIT_SHIFT_PS_8814B) & BIT_MASK_PS_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_PSEN_8814B BIT(6) -#define BIT_DOGENB_8814B BIT(5) -#define BIT_REG_MBIAS_8814B BIT(4) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_POW_XTAL_8814B BIT(1) +#define BIT_POW_BG_8814B BIT(0) -#define BIT_SHIFT_REG_R3_V4_8814B 1 -#define BIT_MASK_REG_R3_V4_8814B 0x7 -#define BIT_REG_R3_V4_8814B(x) (((x) & BIT_MASK_REG_R3_V4_8814B) << BIT_SHIFT_REG_R3_V4_8814B) -#define BIT_GET_REG_R3_V4_8814B(x) (((x) >> BIT_SHIFT_REG_R3_V4_8814B) & BIT_MASK_REG_R3_V4_8814B) +/* 2 REG_ANAPARLDO_MAC_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_CP_BIT0_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_EFUSE_CTRL_8814B */ #define BIT_EF_FLAG_8814B BIT(31) #define BIT_SHIFT_EF_PGPD_8814B 28 #define BIT_MASK_EF_PGPD_8814B 0x7 -#define BIT_EF_PGPD_8814B(x) (((x) & BIT_MASK_EF_PGPD_8814B) << BIT_SHIFT_EF_PGPD_8814B) -#define BIT_GET_EF_PGPD_8814B(x) (((x) >> BIT_SHIFT_EF_PGPD_8814B) & BIT_MASK_EF_PGPD_8814B) - - +#define BIT_EF_PGPD_8814B(x) \ + (((x) & BIT_MASK_EF_PGPD_8814B) << BIT_SHIFT_EF_PGPD_8814B) +#define BITS_EF_PGPD_8814B (BIT_MASK_EF_PGPD_8814B << BIT_SHIFT_EF_PGPD_8814B) +#define BIT_CLEAR_EF_PGPD_8814B(x) ((x) & (~BITS_EF_PGPD_8814B)) +#define BIT_GET_EF_PGPD_8814B(x) \ + (((x) >> BIT_SHIFT_EF_PGPD_8814B) & BIT_MASK_EF_PGPD_8814B) +#define BIT_SET_EF_PGPD_8814B(x, v) \ + (BIT_CLEAR_EF_PGPD_8814B(x) | BIT_EF_PGPD_8814B(v)) #define BIT_SHIFT_EF_RDT_8814B 24 #define BIT_MASK_EF_RDT_8814B 0xf -#define BIT_EF_RDT_8814B(x) (((x) & BIT_MASK_EF_RDT_8814B) << BIT_SHIFT_EF_RDT_8814B) -#define BIT_GET_EF_RDT_8814B(x) (((x) >> BIT_SHIFT_EF_RDT_8814B) & BIT_MASK_EF_RDT_8814B) - - +#define BIT_EF_RDT_8814B(x) \ + (((x) & BIT_MASK_EF_RDT_8814B) << BIT_SHIFT_EF_RDT_8814B) +#define BITS_EF_RDT_8814B (BIT_MASK_EF_RDT_8814B << BIT_SHIFT_EF_RDT_8814B) +#define BIT_CLEAR_EF_RDT_8814B(x) ((x) & (~BITS_EF_RDT_8814B)) +#define BIT_GET_EF_RDT_8814B(x) \ + (((x) >> BIT_SHIFT_EF_RDT_8814B) & BIT_MASK_EF_RDT_8814B) +#define BIT_SET_EF_RDT_8814B(x, v) \ + (BIT_CLEAR_EF_RDT_8814B(x) | BIT_EF_RDT_8814B(v)) #define BIT_SHIFT_EF_PGTS_8814B 20 #define BIT_MASK_EF_PGTS_8814B 0xf -#define BIT_EF_PGTS_8814B(x) (((x) & BIT_MASK_EF_PGTS_8814B) << BIT_SHIFT_EF_PGTS_8814B) -#define BIT_GET_EF_PGTS_8814B(x) (((x) >> BIT_SHIFT_EF_PGTS_8814B) & BIT_MASK_EF_PGTS_8814B) - +#define BIT_EF_PGTS_8814B(x) \ + (((x) & BIT_MASK_EF_PGTS_8814B) << BIT_SHIFT_EF_PGTS_8814B) +#define BITS_EF_PGTS_8814B (BIT_MASK_EF_PGTS_8814B << BIT_SHIFT_EF_PGTS_8814B) +#define BIT_CLEAR_EF_PGTS_8814B(x) ((x) & (~BITS_EF_PGTS_8814B)) +#define BIT_GET_EF_PGTS_8814B(x) \ + (((x) >> BIT_SHIFT_EF_PGTS_8814B) & BIT_MASK_EF_PGTS_8814B) +#define BIT_SET_EF_PGTS_8814B(x, v) \ + (BIT_CLEAR_EF_PGTS_8814B(x) | BIT_EF_PGTS_8814B(v)) #define BIT_EF_PDWN_8814B BIT(19) #define BIT_EF_ALDEN_8814B BIT(18) #define BIT_SHIFT_EF_ADDR_8814B 8 #define BIT_MASK_EF_ADDR_8814B 0x3ff -#define BIT_EF_ADDR_8814B(x) (((x) & BIT_MASK_EF_ADDR_8814B) << BIT_SHIFT_EF_ADDR_8814B) -#define BIT_GET_EF_ADDR_8814B(x) (((x) >> BIT_SHIFT_EF_ADDR_8814B) & BIT_MASK_EF_ADDR_8814B) - - +#define BIT_EF_ADDR_8814B(x) \ + (((x) & BIT_MASK_EF_ADDR_8814B) << BIT_SHIFT_EF_ADDR_8814B) +#define BITS_EF_ADDR_8814B (BIT_MASK_EF_ADDR_8814B << BIT_SHIFT_EF_ADDR_8814B) +#define BIT_CLEAR_EF_ADDR_8814B(x) ((x) & (~BITS_EF_ADDR_8814B)) +#define BIT_GET_EF_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_EF_ADDR_8814B) & BIT_MASK_EF_ADDR_8814B) +#define BIT_SET_EF_ADDR_8814B(x, v) \ + (BIT_CLEAR_EF_ADDR_8814B(x) | BIT_EF_ADDR_8814B(v)) #define BIT_SHIFT_EF_DATA_8814B 0 #define BIT_MASK_EF_DATA_8814B 0xff -#define BIT_EF_DATA_8814B(x) (((x) & BIT_MASK_EF_DATA_8814B) << BIT_SHIFT_EF_DATA_8814B) -#define BIT_GET_EF_DATA_8814B(x) (((x) >> BIT_SHIFT_EF_DATA_8814B) & BIT_MASK_EF_DATA_8814B) - - +#define BIT_EF_DATA_8814B(x) \ + (((x) & BIT_MASK_EF_DATA_8814B) << BIT_SHIFT_EF_DATA_8814B) +#define BITS_EF_DATA_8814B (BIT_MASK_EF_DATA_8814B << BIT_SHIFT_EF_DATA_8814B) +#define BIT_CLEAR_EF_DATA_8814B(x) ((x) & (~BITS_EF_DATA_8814B)) +#define BIT_GET_EF_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_EF_DATA_8814B) & BIT_MASK_EF_DATA_8814B) +#define BIT_SET_EF_DATA_8814B(x, v) \ + (BIT_CLEAR_EF_DATA_8814B(x) | BIT_EF_DATA_8814B(v)) /* 2 REG_LDO_EFUSE_CTRL_8814B */ -#define BIT_LDOE25_EN_8814B BIT(31) - -#define BIT_SHIFT_LDOE25_V12ADJ_L_8814B 27 -#define BIT_MASK_LDOE25_V12ADJ_L_8814B 0xf -#define BIT_LDOE25_V12ADJ_L_8814B(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8814B) << BIT_SHIFT_LDOE25_V12ADJ_L_8814B) -#define BIT_GET_LDOE25_V12ADJ_L_8814B(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8814B) & BIT_MASK_LDOE25_V12ADJ_L_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ #define BIT_EF_CRES_SEL_8814B BIT(26) #define BIT_SHIFT_EF_SCAN_START_V1_8814B 16 #define BIT_MASK_EF_SCAN_START_V1_8814B 0x3ff -#define BIT_EF_SCAN_START_V1_8814B(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8814B) << BIT_SHIFT_EF_SCAN_START_V1_8814B) -#define BIT_GET_EF_SCAN_START_V1_8814B(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8814B) & BIT_MASK_EF_SCAN_START_V1_8814B) - - +#define BIT_EF_SCAN_START_V1_8814B(x) \ + (((x) & BIT_MASK_EF_SCAN_START_V1_8814B) \ + << BIT_SHIFT_EF_SCAN_START_V1_8814B) +#define BITS_EF_SCAN_START_V1_8814B \ + (BIT_MASK_EF_SCAN_START_V1_8814B << BIT_SHIFT_EF_SCAN_START_V1_8814B) +#define BIT_CLEAR_EF_SCAN_START_V1_8814B(x) \ + ((x) & (~BITS_EF_SCAN_START_V1_8814B)) +#define BIT_GET_EF_SCAN_START_V1_8814B(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8814B) & \ + BIT_MASK_EF_SCAN_START_V1_8814B) +#define BIT_SET_EF_SCAN_START_V1_8814B(x, v) \ + (BIT_CLEAR_EF_SCAN_START_V1_8814B(x) | BIT_EF_SCAN_START_V1_8814B(v)) #define BIT_SHIFT_EF_SCAN_END_8814B 12 #define BIT_MASK_EF_SCAN_END_8814B 0xf -#define BIT_EF_SCAN_END_8814B(x) (((x) & BIT_MASK_EF_SCAN_END_8814B) << BIT_SHIFT_EF_SCAN_END_8814B) -#define BIT_GET_EF_SCAN_END_8814B(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8814B) & BIT_MASK_EF_SCAN_END_8814B) - +#define BIT_EF_SCAN_END_8814B(x) \ + (((x) & BIT_MASK_EF_SCAN_END_8814B) << BIT_SHIFT_EF_SCAN_END_8814B) +#define BITS_EF_SCAN_END_8814B \ + (BIT_MASK_EF_SCAN_END_8814B << BIT_SHIFT_EF_SCAN_END_8814B) +#define BIT_CLEAR_EF_SCAN_END_8814B(x) ((x) & (~BITS_EF_SCAN_END_8814B)) +#define BIT_GET_EF_SCAN_END_8814B(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_END_8814B) & BIT_MASK_EF_SCAN_END_8814B) +#define BIT_SET_EF_SCAN_END_8814B(x, v) \ + (BIT_CLEAR_EF_SCAN_END_8814B(x) | BIT_EF_SCAN_END_8814B(v)) #define BIT_EF_PD_DIS_8814B BIT(11) #define BIT_SHIFT_EF_CELL_SEL_8814B 8 #define BIT_MASK_EF_CELL_SEL_8814B 0x3 -#define BIT_EF_CELL_SEL_8814B(x) (((x) & BIT_MASK_EF_CELL_SEL_8814B) << BIT_SHIFT_EF_CELL_SEL_8814B) -#define BIT_GET_EF_CELL_SEL_8814B(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8814B) & BIT_MASK_EF_CELL_SEL_8814B) - +#define BIT_EF_CELL_SEL_8814B(x) \ + (((x) & BIT_MASK_EF_CELL_SEL_8814B) << BIT_SHIFT_EF_CELL_SEL_8814B) +#define BITS_EF_CELL_SEL_8814B \ + (BIT_MASK_EF_CELL_SEL_8814B << BIT_SHIFT_EF_CELL_SEL_8814B) +#define BIT_CLEAR_EF_CELL_SEL_8814B(x) ((x) & (~BITS_EF_CELL_SEL_8814B)) +#define BIT_GET_EF_CELL_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_EF_CELL_SEL_8814B) & BIT_MASK_EF_CELL_SEL_8814B) +#define BIT_SET_EF_CELL_SEL_8814B(x, v) \ + (BIT_CLEAR_EF_CELL_SEL_8814B(x) | BIT_EF_CELL_SEL_8814B(v)) #define BIT_EF_TRPT_8814B BIT(7) #define BIT_SHIFT_EF_TTHD_8814B 0 #define BIT_MASK_EF_TTHD_8814B 0x7f -#define BIT_EF_TTHD_8814B(x) (((x) & BIT_MASK_EF_TTHD_8814B) << BIT_SHIFT_EF_TTHD_8814B) -#define BIT_GET_EF_TTHD_8814B(x) (((x) >> BIT_SHIFT_EF_TTHD_8814B) & BIT_MASK_EF_TTHD_8814B) - - +#define BIT_EF_TTHD_8814B(x) \ + (((x) & BIT_MASK_EF_TTHD_8814B) << BIT_SHIFT_EF_TTHD_8814B) +#define BITS_EF_TTHD_8814B (BIT_MASK_EF_TTHD_8814B << BIT_SHIFT_EF_TTHD_8814B) +#define BIT_CLEAR_EF_TTHD_8814B(x) ((x) & (~BITS_EF_TTHD_8814B)) +#define BIT_GET_EF_TTHD_8814B(x) \ + (((x) >> BIT_SHIFT_EF_TTHD_8814B) & BIT_MASK_EF_TTHD_8814B) +#define BIT_SET_EF_TTHD_8814B(x, v) \ + (BIT_CLEAR_EF_TTHD_8814B(x) | BIT_EF_TTHD_8814B(v)) /* 2 REG_PWR_OPTION_CTRL_8814B */ #define BIT_SHIFT_DBG_SEL_V1_8814B 16 #define BIT_MASK_DBG_SEL_V1_8814B 0xff -#define BIT_DBG_SEL_V1_8814B(x) (((x) & BIT_MASK_DBG_SEL_V1_8814B) << BIT_SHIFT_DBG_SEL_V1_8814B) -#define BIT_GET_DBG_SEL_V1_8814B(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8814B) & BIT_MASK_DBG_SEL_V1_8814B) - - +#define BIT_DBG_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_DBG_SEL_V1_8814B) << BIT_SHIFT_DBG_SEL_V1_8814B) +#define BITS_DBG_SEL_V1_8814B \ + (BIT_MASK_DBG_SEL_V1_8814B << BIT_SHIFT_DBG_SEL_V1_8814B) +#define BIT_CLEAR_DBG_SEL_V1_8814B(x) ((x) & (~BITS_DBG_SEL_V1_8814B)) +#define BIT_GET_DBG_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_V1_8814B) & BIT_MASK_DBG_SEL_V1_8814B) +#define BIT_SET_DBG_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_DBG_SEL_V1_8814B(x) | BIT_DBG_SEL_V1_8814B(v)) #define BIT_SHIFT_DBG_SEL_BYTE_8814B 14 #define BIT_MASK_DBG_SEL_BYTE_8814B 0x3 -#define BIT_DBG_SEL_BYTE_8814B(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8814B) << BIT_SHIFT_DBG_SEL_BYTE_8814B) -#define BIT_GET_DBG_SEL_BYTE_8814B(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8814B) & BIT_MASK_DBG_SEL_BYTE_8814B) - - - -#define BIT_SHIFT_STD_L1_V1_8814B 12 -#define BIT_MASK_STD_L1_V1_8814B 0x3 -#define BIT_STD_L1_V1_8814B(x) (((x) & BIT_MASK_STD_L1_V1_8814B) << BIT_SHIFT_STD_L1_V1_8814B) -#define BIT_GET_STD_L1_V1_8814B(x) (((x) >> BIT_SHIFT_STD_L1_V1_8814B) & BIT_MASK_STD_L1_V1_8814B) - +#define BIT_DBG_SEL_BYTE_8814B(x) \ + (((x) & BIT_MASK_DBG_SEL_BYTE_8814B) << BIT_SHIFT_DBG_SEL_BYTE_8814B) +#define BITS_DBG_SEL_BYTE_8814B \ + (BIT_MASK_DBG_SEL_BYTE_8814B << BIT_SHIFT_DBG_SEL_BYTE_8814B) +#define BIT_CLEAR_DBG_SEL_BYTE_8814B(x) ((x) & (~BITS_DBG_SEL_BYTE_8814B)) +#define BIT_GET_DBG_SEL_BYTE_8814B(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8814B) & BIT_MASK_DBG_SEL_BYTE_8814B) +#define BIT_SET_DBG_SEL_BYTE_8814B(x, v) \ + (BIT_CLEAR_DBG_SEL_BYTE_8814B(x) | BIT_DBG_SEL_BYTE_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ #define BIT_SYSON_DBG_PAD_E2_8814B BIT(11) #define BIT_SYSON_LED_PAD_E2_8814B BIT(10) #define BIT_SYSON_GPEE_PAD_E2_8814B BIT(9) @@ -597,60 +578,110 @@ #define BIT_SHIFT_SYSON_SPS0WWV_WT_8814B 4 #define BIT_MASK_SYSON_SPS0WWV_WT_8814B 0x3 -#define BIT_SYSON_SPS0WWV_WT_8814B(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8814B) << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) -#define BIT_GET_SYSON_SPS0WWV_WT_8814B(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) & BIT_MASK_SYSON_SPS0WWV_WT_8814B) - - +#define BIT_SYSON_SPS0WWV_WT_8814B(x) \ + (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8814B) \ + << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) +#define BITS_SYSON_SPS0WWV_WT_8814B \ + (BIT_MASK_SYSON_SPS0WWV_WT_8814B << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) +#define BIT_CLEAR_SYSON_SPS0WWV_WT_8814B(x) \ + ((x) & (~BITS_SYSON_SPS0WWV_WT_8814B)) +#define BIT_GET_SYSON_SPS0WWV_WT_8814B(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) & \ + BIT_MASK_SYSON_SPS0WWV_WT_8814B) +#define BIT_SET_SYSON_SPS0WWV_WT_8814B(x, v) \ + (BIT_CLEAR_SYSON_SPS0WWV_WT_8814B(x) | BIT_SYSON_SPS0WWV_WT_8814B(v)) #define BIT_SHIFT_SYSON_SPS0LDO_WT_8814B 2 #define BIT_MASK_SYSON_SPS0LDO_WT_8814B 0x3 -#define BIT_SYSON_SPS0LDO_WT_8814B(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8814B) << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) -#define BIT_GET_SYSON_SPS0LDO_WT_8814B(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) & BIT_MASK_SYSON_SPS0LDO_WT_8814B) - - +#define BIT_SYSON_SPS0LDO_WT_8814B(x) \ + (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8814B) \ + << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) +#define BITS_SYSON_SPS0LDO_WT_8814B \ + (BIT_MASK_SYSON_SPS0LDO_WT_8814B << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) +#define BIT_CLEAR_SYSON_SPS0LDO_WT_8814B(x) \ + ((x) & (~BITS_SYSON_SPS0LDO_WT_8814B)) +#define BIT_GET_SYSON_SPS0LDO_WT_8814B(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) & \ + BIT_MASK_SYSON_SPS0LDO_WT_8814B) +#define BIT_SET_SYSON_SPS0LDO_WT_8814B(x, v) \ + (BIT_CLEAR_SYSON_SPS0LDO_WT_8814B(x) | BIT_SYSON_SPS0LDO_WT_8814B(v)) #define BIT_SHIFT_SYSON_RCLK_SCALE_8814B 0 #define BIT_MASK_SYSON_RCLK_SCALE_8814B 0x3 -#define BIT_SYSON_RCLK_SCALE_8814B(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8814B) << BIT_SHIFT_SYSON_RCLK_SCALE_8814B) -#define BIT_GET_SYSON_RCLK_SCALE_8814B(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8814B) & BIT_MASK_SYSON_RCLK_SCALE_8814B) - - +#define BIT_SYSON_RCLK_SCALE_8814B(x) \ + (((x) & BIT_MASK_SYSON_RCLK_SCALE_8814B) \ + << BIT_SHIFT_SYSON_RCLK_SCALE_8814B) +#define BITS_SYSON_RCLK_SCALE_8814B \ + (BIT_MASK_SYSON_RCLK_SCALE_8814B << BIT_SHIFT_SYSON_RCLK_SCALE_8814B) +#define BIT_CLEAR_SYSON_RCLK_SCALE_8814B(x) \ + ((x) & (~BITS_SYSON_RCLK_SCALE_8814B)) +#define BIT_GET_SYSON_RCLK_SCALE_8814B(x) \ + (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8814B) & \ + BIT_MASK_SYSON_RCLK_SCALE_8814B) +#define BIT_SET_SYSON_RCLK_SCALE_8814B(x, v) \ + (BIT_CLEAR_SYSON_RCLK_SCALE_8814B(x) | BIT_SYSON_RCLK_SCALE_8814B(v)) /* 2 REG_CAL_TIMER_8814B */ #define BIT_SHIFT_MATCH_CNT_8814B 8 #define BIT_MASK_MATCH_CNT_8814B 0xff -#define BIT_MATCH_CNT_8814B(x) (((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B) -#define BIT_GET_MATCH_CNT_8814B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B) - - +#define BIT_MATCH_CNT_8814B(x) \ + (((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B) +#define BITS_MATCH_CNT_8814B \ + (BIT_MASK_MATCH_CNT_8814B << BIT_SHIFT_MATCH_CNT_8814B) +#define BIT_CLEAR_MATCH_CNT_8814B(x) ((x) & (~BITS_MATCH_CNT_8814B)) +#define BIT_GET_MATCH_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B) +#define BIT_SET_MATCH_CNT_8814B(x, v) \ + (BIT_CLEAR_MATCH_CNT_8814B(x) | BIT_MATCH_CNT_8814B(v)) #define BIT_SHIFT_CAL_SCAL_8814B 0 #define BIT_MASK_CAL_SCAL_8814B 0xff -#define BIT_CAL_SCAL_8814B(x) (((x) & BIT_MASK_CAL_SCAL_8814B) << BIT_SHIFT_CAL_SCAL_8814B) -#define BIT_GET_CAL_SCAL_8814B(x) (((x) >> BIT_SHIFT_CAL_SCAL_8814B) & BIT_MASK_CAL_SCAL_8814B) - - +#define BIT_CAL_SCAL_8814B(x) \ + (((x) & BIT_MASK_CAL_SCAL_8814B) << BIT_SHIFT_CAL_SCAL_8814B) +#define BITS_CAL_SCAL_8814B \ + (BIT_MASK_CAL_SCAL_8814B << BIT_SHIFT_CAL_SCAL_8814B) +#define BIT_CLEAR_CAL_SCAL_8814B(x) ((x) & (~BITS_CAL_SCAL_8814B)) +#define BIT_GET_CAL_SCAL_8814B(x) \ + (((x) >> BIT_SHIFT_CAL_SCAL_8814B) & BIT_MASK_CAL_SCAL_8814B) +#define BIT_SET_CAL_SCAL_8814B(x, v) \ + (BIT_CLEAR_CAL_SCAL_8814B(x) | BIT_CAL_SCAL_8814B(v)) /* 2 REG_ACLK_MON_8814B */ #define BIT_SHIFT_RCLK_MON_8814B 5 #define BIT_MASK_RCLK_MON_8814B 0x7ff -#define BIT_RCLK_MON_8814B(x) (((x) & BIT_MASK_RCLK_MON_8814B) << BIT_SHIFT_RCLK_MON_8814B) -#define BIT_GET_RCLK_MON_8814B(x) (((x) >> BIT_SHIFT_RCLK_MON_8814B) & BIT_MASK_RCLK_MON_8814B) - +#define BIT_RCLK_MON_8814B(x) \ + (((x) & BIT_MASK_RCLK_MON_8814B) << BIT_SHIFT_RCLK_MON_8814B) +#define BITS_RCLK_MON_8814B \ + (BIT_MASK_RCLK_MON_8814B << BIT_SHIFT_RCLK_MON_8814B) +#define BIT_CLEAR_RCLK_MON_8814B(x) ((x) & (~BITS_RCLK_MON_8814B)) +#define BIT_GET_RCLK_MON_8814B(x) \ + (((x) >> BIT_SHIFT_RCLK_MON_8814B) & BIT_MASK_RCLK_MON_8814B) +#define BIT_SET_RCLK_MON_8814B(x, v) \ + (BIT_CLEAR_RCLK_MON_8814B(x) | BIT_RCLK_MON_8814B(v)) #define BIT_CAL_EN_8814B BIT(4) #define BIT_SHIFT_DPSTU_8814B 2 #define BIT_MASK_DPSTU_8814B 0x3 -#define BIT_DPSTU_8814B(x) (((x) & BIT_MASK_DPSTU_8814B) << BIT_SHIFT_DPSTU_8814B) -#define BIT_GET_DPSTU_8814B(x) (((x) >> BIT_SHIFT_DPSTU_8814B) & BIT_MASK_DPSTU_8814B) - +#define BIT_DPSTU_8814B(x) \ + (((x) & BIT_MASK_DPSTU_8814B) << BIT_SHIFT_DPSTU_8814B) +#define BITS_DPSTU_8814B (BIT_MASK_DPSTU_8814B << BIT_SHIFT_DPSTU_8814B) +#define BIT_CLEAR_DPSTU_8814B(x) ((x) & (~BITS_DPSTU_8814B)) +#define BIT_GET_DPSTU_8814B(x) \ + (((x) >> BIT_SHIFT_DPSTU_8814B) & BIT_MASK_DPSTU_8814B) +#define BIT_SET_DPSTU_8814B(x, v) \ + (BIT_CLEAR_DPSTU_8814B(x) | BIT_DPSTU_8814B(v)) #define BIT_SUS_16X_8814B BIT(1) /* 2 REG_GPIO_MUXCFG_8814B */ +#define BIT_EN_DATACPU_GPIO2_8814B BIT(24) +#define BIT_EN_DATACPU_GPIO_8814B BIT(23) +#define BIT_EN_DATACPU_UART_8814B BIT(22) +#define BIT_DATACPU_FSPI_EN_8814B BIT(21) +#define BIT_EN_GPIO8_UART_OUT_8814B BIT(20) #define BIT_FSPI_EN_8814B BIT(19) #define BIT_WL_RTS_EXT_32K_SEL_8814B BIT(18) #define BIT_WLGP_SPI_EN_8814B BIT(16) @@ -664,9 +695,14 @@ #define BIT_SHIFT_BTMODE_8814B 6 #define BIT_MASK_BTMODE_8814B 0x3 -#define BIT_BTMODE_8814B(x) (((x) & BIT_MASK_BTMODE_8814B) << BIT_SHIFT_BTMODE_8814B) -#define BIT_GET_BTMODE_8814B(x) (((x) >> BIT_SHIFT_BTMODE_8814B) & BIT_MASK_BTMODE_8814B) - +#define BIT_BTMODE_8814B(x) \ + (((x) & BIT_MASK_BTMODE_8814B) << BIT_SHIFT_BTMODE_8814B) +#define BITS_BTMODE_8814B (BIT_MASK_BTMODE_8814B << BIT_SHIFT_BTMODE_8814B) +#define BIT_CLEAR_BTMODE_8814B(x) ((x) & (~BITS_BTMODE_8814B)) +#define BIT_GET_BTMODE_8814B(x) \ + (((x) >> BIT_SHIFT_BTMODE_8814B) & BIT_MASK_BTMODE_8814B) +#define BIT_SET_BTMODE_8814B(x, v) \ + (BIT_CLEAR_BTMODE_8814B(x) | BIT_BTMODE_8814B(v)) #define BIT_ENBT_8814B BIT(5) #define BIT_EROM_EN_8814B BIT(4) @@ -675,48 +711,89 @@ #define BIT_SHIFT_GPIOSEL_8814B 0 #define BIT_MASK_GPIOSEL_8814B 0x3 -#define BIT_GPIOSEL_8814B(x) (((x) & BIT_MASK_GPIOSEL_8814B) << BIT_SHIFT_GPIOSEL_8814B) -#define BIT_GET_GPIOSEL_8814B(x) (((x) >> BIT_SHIFT_GPIOSEL_8814B) & BIT_MASK_GPIOSEL_8814B) - - +#define BIT_GPIOSEL_8814B(x) \ + (((x) & BIT_MASK_GPIOSEL_8814B) << BIT_SHIFT_GPIOSEL_8814B) +#define BITS_GPIOSEL_8814B (BIT_MASK_GPIOSEL_8814B << BIT_SHIFT_GPIOSEL_8814B) +#define BIT_CLEAR_GPIOSEL_8814B(x) ((x) & (~BITS_GPIOSEL_8814B)) +#define BIT_GET_GPIOSEL_8814B(x) \ + (((x) >> BIT_SHIFT_GPIOSEL_8814B) & BIT_MASK_GPIOSEL_8814B) +#define BIT_SET_GPIOSEL_8814B(x, v) \ + (BIT_CLEAR_GPIOSEL_8814B(x) | BIT_GPIOSEL_8814B(v)) /* 2 REG_GPIO_PIN_CTRL_8814B */ #define BIT_SHIFT_GPIO_MOD_7_TO_0_8814B 24 #define BIT_MASK_GPIO_MOD_7_TO_0_8814B 0xff -#define BIT_GPIO_MOD_7_TO_0_8814B(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8814B) << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) -#define BIT_GET_GPIO_MOD_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) & BIT_MASK_GPIO_MOD_7_TO_0_8814B) - - +#define BIT_GPIO_MOD_7_TO_0_8814B(x) \ + (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8814B) \ + << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) +#define BITS_GPIO_MOD_7_TO_0_8814B \ + (BIT_MASK_GPIO_MOD_7_TO_0_8814B << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) +#define BIT_CLEAR_GPIO_MOD_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8814B)) +#define BIT_GET_GPIO_MOD_7_TO_0_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) & \ + BIT_MASK_GPIO_MOD_7_TO_0_8814B) +#define BIT_SET_GPIO_MOD_7_TO_0_8814B(x, v) \ + (BIT_CLEAR_GPIO_MOD_7_TO_0_8814B(x) | BIT_GPIO_MOD_7_TO_0_8814B(v)) #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B 16 #define BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B 0xff -#define BIT_GPIO_IO_SEL_7_TO_0_8814B(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) -#define BIT_GET_GPIO_IO_SEL_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B) - - +#define BIT_GPIO_IO_SEL_7_TO_0_8814B(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B) \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) +#define BITS_GPIO_IO_SEL_7_TO_0_8814B \ + (BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8814B(x) \ + ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8814B)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) & \ + BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B) +#define BIT_SET_GPIO_IO_SEL_7_TO_0_8814B(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8814B(x) | \ + BIT_GPIO_IO_SEL_7_TO_0_8814B(v)) #define BIT_SHIFT_GPIO_OUT_7_TO_0_8814B 8 #define BIT_MASK_GPIO_OUT_7_TO_0_8814B 0xff -#define BIT_GPIO_OUT_7_TO_0_8814B(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8814B) << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) -#define BIT_GET_GPIO_OUT_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) & BIT_MASK_GPIO_OUT_7_TO_0_8814B) - - +#define BIT_GPIO_OUT_7_TO_0_8814B(x) \ + (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8814B) \ + << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) +#define BITS_GPIO_OUT_7_TO_0_8814B \ + (BIT_MASK_GPIO_OUT_7_TO_0_8814B << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) +#define BIT_CLEAR_GPIO_OUT_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8814B)) +#define BIT_GET_GPIO_OUT_7_TO_0_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) & \ + BIT_MASK_GPIO_OUT_7_TO_0_8814B) +#define BIT_SET_GPIO_OUT_7_TO_0_8814B(x, v) \ + (BIT_CLEAR_GPIO_OUT_7_TO_0_8814B(x) | BIT_GPIO_OUT_7_TO_0_8814B(v)) #define BIT_SHIFT_GPIO_IN_7_TO_0_8814B 0 #define BIT_MASK_GPIO_IN_7_TO_0_8814B 0xff -#define BIT_GPIO_IN_7_TO_0_8814B(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8814B) << BIT_SHIFT_GPIO_IN_7_TO_0_8814B) -#define BIT_GET_GPIO_IN_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8814B) & BIT_MASK_GPIO_IN_7_TO_0_8814B) - - +#define BIT_GPIO_IN_7_TO_0_8814B(x) \ + (((x) & BIT_MASK_GPIO_IN_7_TO_0_8814B) \ + << BIT_SHIFT_GPIO_IN_7_TO_0_8814B) +#define BITS_GPIO_IN_7_TO_0_8814B \ + (BIT_MASK_GPIO_IN_7_TO_0_8814B << BIT_SHIFT_GPIO_IN_7_TO_0_8814B) +#define BIT_CLEAR_GPIO_IN_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8814B)) +#define BIT_GET_GPIO_IN_7_TO_0_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8814B) & \ + BIT_MASK_GPIO_IN_7_TO_0_8814B) +#define BIT_SET_GPIO_IN_7_TO_0_8814B(x, v) \ + (BIT_CLEAR_GPIO_IN_7_TO_0_8814B(x) | BIT_GPIO_IN_7_TO_0_8814B(v)) /* 2 REG_GPIO_INTM_8814B */ #define BIT_SHIFT_MUXDBG_SEL_8814B 30 #define BIT_MASK_MUXDBG_SEL_8814B 0x3 -#define BIT_MUXDBG_SEL_8814B(x) (((x) & BIT_MASK_MUXDBG_SEL_8814B) << BIT_SHIFT_MUXDBG_SEL_8814B) -#define BIT_GET_MUXDBG_SEL_8814B(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8814B) & BIT_MASK_MUXDBG_SEL_8814B) - +#define BIT_MUXDBG_SEL_8814B(x) \ + (((x) & BIT_MASK_MUXDBG_SEL_8814B) << BIT_SHIFT_MUXDBG_SEL_8814B) +#define BITS_MUXDBG_SEL_8814B \ + (BIT_MASK_MUXDBG_SEL_8814B << BIT_SHIFT_MUXDBG_SEL_8814B) +#define BIT_CLEAR_MUXDBG_SEL_8814B(x) ((x) & (~BITS_MUXDBG_SEL_8814B)) +#define BIT_GET_MUXDBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL_8814B) & BIT_MASK_MUXDBG_SEL_8814B) +#define BIT_SET_MUXDBG_SEL_8814B(x, v) \ + (BIT_CLEAR_MUXDBG_SEL_8814B(x) | BIT_MUXDBG_SEL_8814B(v)) #define BIT_EXTWOL_SEL_8814B BIT(17) #define BIT_EXTWOL_EN_8814B BIT(16) @@ -747,16 +824,20 @@ #define BIT_DPDT_WLBT_SEL_8814B BIT(24) #define BIT_DPDT_SEL_EN_8814B BIT(23) #define BIT_GPIO13_14_WL_CTRL_EN_8814B BIT(22) -#define BIT_GPIO13_14_WL_CTRL_EN_8814B BIT(22) #define BIT_LED2DIS_8814B BIT(21) #define BIT_LED2PL_8814B BIT(20) #define BIT_LED2SV_8814B BIT(19) #define BIT_SHIFT_LED2CM_8814B 16 #define BIT_MASK_LED2CM_8814B 0x7 -#define BIT_LED2CM_8814B(x) (((x) & BIT_MASK_LED2CM_8814B) << BIT_SHIFT_LED2CM_8814B) -#define BIT_GET_LED2CM_8814B(x) (((x) >> BIT_SHIFT_LED2CM_8814B) & BIT_MASK_LED2CM_8814B) - +#define BIT_LED2CM_8814B(x) \ + (((x) & BIT_MASK_LED2CM_8814B) << BIT_SHIFT_LED2CM_8814B) +#define BITS_LED2CM_8814B (BIT_MASK_LED2CM_8814B << BIT_SHIFT_LED2CM_8814B) +#define BIT_CLEAR_LED2CM_8814B(x) ((x) & (~BITS_LED2CM_8814B)) +#define BIT_GET_LED2CM_8814B(x) \ + (((x) >> BIT_SHIFT_LED2CM_8814B) & BIT_MASK_LED2CM_8814B) +#define BIT_SET_LED2CM_8814B(x, v) \ + (BIT_CLEAR_LED2CM_8814B(x) | BIT_LED2CM_8814B(v)) #define BIT_LED1DIS_8814B BIT(15) #define BIT_LED1PL_8814B BIT(12) @@ -764,27 +845,45 @@ #define BIT_SHIFT_LED1CM_8814B 8 #define BIT_MASK_LED1CM_8814B 0x7 -#define BIT_LED1CM_8814B(x) (((x) & BIT_MASK_LED1CM_8814B) << BIT_SHIFT_LED1CM_8814B) -#define BIT_GET_LED1CM_8814B(x) (((x) >> BIT_SHIFT_LED1CM_8814B) & BIT_MASK_LED1CM_8814B) - +#define BIT_LED1CM_8814B(x) \ + (((x) & BIT_MASK_LED1CM_8814B) << BIT_SHIFT_LED1CM_8814B) +#define BITS_LED1CM_8814B (BIT_MASK_LED1CM_8814B << BIT_SHIFT_LED1CM_8814B) +#define BIT_CLEAR_LED1CM_8814B(x) ((x) & (~BITS_LED1CM_8814B)) +#define BIT_GET_LED1CM_8814B(x) \ + (((x) >> BIT_SHIFT_LED1CM_8814B) & BIT_MASK_LED1CM_8814B) +#define BIT_SET_LED1CM_8814B(x, v) \ + (BIT_CLEAR_LED1CM_8814B(x) | BIT_LED1CM_8814B(v)) #define BIT_LED0DIS_8814B BIT(7) #define BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B 5 #define BIT_MASK_AFE_LDO_SWR_CHECK_8814B 0x3 -#define BIT_AFE_LDO_SWR_CHECK_8814B(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8814B) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) -#define BIT_GET_AFE_LDO_SWR_CHECK_8814B(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) & BIT_MASK_AFE_LDO_SWR_CHECK_8814B) - +#define BIT_AFE_LDO_SWR_CHECK_8814B(x) \ + (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8814B) \ + << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) +#define BITS_AFE_LDO_SWR_CHECK_8814B \ + (BIT_MASK_AFE_LDO_SWR_CHECK_8814B << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8814B(x) \ + ((x) & (~BITS_AFE_LDO_SWR_CHECK_8814B)) +#define BIT_GET_AFE_LDO_SWR_CHECK_8814B(x) \ + (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) & \ + BIT_MASK_AFE_LDO_SWR_CHECK_8814B) +#define BIT_SET_AFE_LDO_SWR_CHECK_8814B(x, v) \ + (BIT_CLEAR_AFE_LDO_SWR_CHECK_8814B(x) | BIT_AFE_LDO_SWR_CHECK_8814B(v)) #define BIT_LED0PL_8814B BIT(4) #define BIT_LED0SV_8814B BIT(3) #define BIT_SHIFT_LED0CM_8814B 0 #define BIT_MASK_LED0CM_8814B 0x7 -#define BIT_LED0CM_8814B(x) (((x) & BIT_MASK_LED0CM_8814B) << BIT_SHIFT_LED0CM_8814B) -#define BIT_GET_LED0CM_8814B(x) (((x) >> BIT_SHIFT_LED0CM_8814B) & BIT_MASK_LED0CM_8814B) - - +#define BIT_LED0CM_8814B(x) \ + (((x) & BIT_MASK_LED0CM_8814B) << BIT_SHIFT_LED0CM_8814B) +#define BITS_LED0CM_8814B (BIT_MASK_LED0CM_8814B << BIT_SHIFT_LED0CM_8814B) +#define BIT_CLEAR_LED0CM_8814B(x) ((x) & (~BITS_LED0CM_8814B)) +#define BIT_GET_LED0CM_8814B(x) \ + (((x) >> BIT_SHIFT_LED0CM_8814B) & BIT_MASK_LED0CM_8814B) +#define BIT_SET_LED0CM_8814B(x, v) \ + (BIT_CLEAR_LED0CM_8814B(x) | BIT_LED0CM_8814B(v)) /* 2 REG_FSIMR_8814B */ #define BIT_FS_PDNINT_EN_8814B BIT(31) @@ -844,6 +943,7 @@ #define BIT_FS_HCI_RES_INT_8814B BIT(10) #define BIT_FS_HCI_RESET_INT_8814B BIT(9) #define BIT_USB_SCSI_CMD_INT_8814B BIT(8) +#define BIT_FS_BTON_STS_UPDATE_INT_8814B BIT(7) #define BIT_ACT2RECOVERY_8814B BIT(6) #define BIT_GEN1GEN2_SWITCH_8814B BIT(5) #define BIT_HCI_TXDMA_REQ_HISR_8814B BIT(4) @@ -866,7 +966,7 @@ #define BIT_GPIO5_INT_EN_8814B BIT(21) #define BIT_GPIO4_INT_EN_8814B BIT(20) #define BIT_GPIO3_INT_EN_8814B BIT(19) -#define BIT_GPIO2_INT_EN_V1_8814B BIT(16) +#define BIT_GPIO2_INT_EN_V1_8814B BIT(18) #define BIT_GPIO1_INT_EN_8814B BIT(17) #define BIT_GPIO0_INT_EN_8814B BIT(16) #define BIT_PDNINT_EN_8814B BIT(7) @@ -888,7 +988,7 @@ #define BIT_GPIO5_INT_8814B BIT(21) #define BIT_GPIO4_INT_8814B BIT(20) #define BIT_GPIO3_INT_8814B BIT(19) -#define BIT_GPIO2_INT_V1_8814B BIT(16) +#define BIT_GPIO2_INT_V1_8814B BIT(18) #define BIT_GPIO1_INT_8814B BIT(17) #define BIT_GPIO0_INT_8814B BIT(16) #define BIT_PDNINT_8814B BIT(7) @@ -900,33 +1000,67 @@ #define BIT_SHIFT_GPIO_MOD_15_TO_8_8814B 24 #define BIT_MASK_GPIO_MOD_15_TO_8_8814B 0xff -#define BIT_GPIO_MOD_15_TO_8_8814B(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8814B) << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) -#define BIT_GET_GPIO_MOD_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) & BIT_MASK_GPIO_MOD_15_TO_8_8814B) - - +#define BIT_GPIO_MOD_15_TO_8_8814B(x) \ + (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8814B) \ + << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) +#define BITS_GPIO_MOD_15_TO_8_8814B \ + (BIT_MASK_GPIO_MOD_15_TO_8_8814B << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) +#define BIT_CLEAR_GPIO_MOD_15_TO_8_8814B(x) \ + ((x) & (~BITS_GPIO_MOD_15_TO_8_8814B)) +#define BIT_GET_GPIO_MOD_15_TO_8_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) & \ + BIT_MASK_GPIO_MOD_15_TO_8_8814B) +#define BIT_SET_GPIO_MOD_15_TO_8_8814B(x, v) \ + (BIT_CLEAR_GPIO_MOD_15_TO_8_8814B(x) | BIT_GPIO_MOD_15_TO_8_8814B(v)) #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B 16 #define BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B 0xff -#define BIT_GPIO_IO_SEL_15_TO_8_8814B(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) -#define BIT_GET_GPIO_IO_SEL_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B) - - +#define BIT_GPIO_IO_SEL_15_TO_8_8814B(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B) \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) +#define BITS_GPIO_IO_SEL_15_TO_8_8814B \ + (BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8814B(x) \ + ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8814B)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) & \ + BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B) +#define BIT_SET_GPIO_IO_SEL_15_TO_8_8814B(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8814B(x) | \ + BIT_GPIO_IO_SEL_15_TO_8_8814B(v)) #define BIT_SHIFT_GPIO_OUT_15_TO_8_8814B 8 #define BIT_MASK_GPIO_OUT_15_TO_8_8814B 0xff -#define BIT_GPIO_OUT_15_TO_8_8814B(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8814B) << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) -#define BIT_GET_GPIO_OUT_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) & BIT_MASK_GPIO_OUT_15_TO_8_8814B) - - +#define BIT_GPIO_OUT_15_TO_8_8814B(x) \ + (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8814B) \ + << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) +#define BITS_GPIO_OUT_15_TO_8_8814B \ + (BIT_MASK_GPIO_OUT_15_TO_8_8814B << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) +#define BIT_CLEAR_GPIO_OUT_15_TO_8_8814B(x) \ + ((x) & (~BITS_GPIO_OUT_15_TO_8_8814B)) +#define BIT_GET_GPIO_OUT_15_TO_8_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) & \ + BIT_MASK_GPIO_OUT_15_TO_8_8814B) +#define BIT_SET_GPIO_OUT_15_TO_8_8814B(x, v) \ + (BIT_CLEAR_GPIO_OUT_15_TO_8_8814B(x) | BIT_GPIO_OUT_15_TO_8_8814B(v)) #define BIT_SHIFT_GPIO_IN_15_TO_8_8814B 0 #define BIT_MASK_GPIO_IN_15_TO_8_8814B 0xff -#define BIT_GPIO_IN_15_TO_8_8814B(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8814B) << BIT_SHIFT_GPIO_IN_15_TO_8_8814B) -#define BIT_GET_GPIO_IN_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8814B) & BIT_MASK_GPIO_IN_15_TO_8_8814B) - - +#define BIT_GPIO_IN_15_TO_8_8814B(x) \ + (((x) & BIT_MASK_GPIO_IN_15_TO_8_8814B) \ + << BIT_SHIFT_GPIO_IN_15_TO_8_8814B) +#define BITS_GPIO_IN_15_TO_8_8814B \ + (BIT_MASK_GPIO_IN_15_TO_8_8814B << BIT_SHIFT_GPIO_IN_15_TO_8_8814B) +#define BIT_CLEAR_GPIO_IN_15_TO_8_8814B(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8814B)) +#define BIT_GET_GPIO_IN_15_TO_8_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8814B) & \ + BIT_MASK_GPIO_IN_15_TO_8_8814B) +#define BIT_SET_GPIO_IN_15_TO_8_8814B(x, v) \ + (BIT_CLEAR_GPIO_IN_15_TO_8_8814B(x) | BIT_GPIO_IN_15_TO_8_8814B(v)) /* 2 REG_PAD_CTRL1_8814B */ +#define BIT_DATA_CPU_JTAG_8814B BIT(30) #define BIT_PAPE_WLBT_SEL_8814B BIT(29) #define BIT_LNAON_WLBT_SEL_8814B BIT(28) #define BIT_BTGP_GPG3_FEN_8814B BIT(26) @@ -941,24 +1075,25 @@ #define BIT_SHIFT_BTGP_GPIO_SL_8814B 16 #define BIT_MASK_BTGP_GPIO_SL_8814B 0x3 -#define BIT_BTGP_GPIO_SL_8814B(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8814B) << BIT_SHIFT_BTGP_GPIO_SL_8814B) -#define BIT_GET_BTGP_GPIO_SL_8814B(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8814B) & BIT_MASK_BTGP_GPIO_SL_8814B) - - +#define BIT_BTGP_GPIO_SL_8814B(x) \ + (((x) & BIT_MASK_BTGP_GPIO_SL_8814B) << BIT_SHIFT_BTGP_GPIO_SL_8814B) +#define BITS_BTGP_GPIO_SL_8814B \ + (BIT_MASK_BTGP_GPIO_SL_8814B << BIT_SHIFT_BTGP_GPIO_SL_8814B) +#define BIT_CLEAR_BTGP_GPIO_SL_8814B(x) ((x) & (~BITS_BTGP_GPIO_SL_8814B)) +#define BIT_GET_BTGP_GPIO_SL_8814B(x) \ + (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8814B) & BIT_MASK_BTGP_GPIO_SL_8814B) +#define BIT_SET_BTGP_GPIO_SL_8814B(x, v) \ + (BIT_CLEAR_BTGP_GPIO_SL_8814B(x) | BIT_BTGP_GPIO_SL_8814B(v)) + +#define BIT_WL_JTAG_8814B BIT(15) #define BIT_PAD_SDIO_SR_8814B BIT(14) #define BIT_GPIO14_OUTPUT_PL_8814B BIT(13) #define BIT_HOST_WAKE_PAD_PULL_EN_8814B BIT(12) #define BIT_HOST_WAKE_PAD_SL_8814B BIT(11) -#define BIT_PAD_LNAON_SR_8814B BIT(10) -#define BIT_PAD_LNAON_E2_8814B BIT(9) #define BIT_SW_LNAON_G_SEL_DATA_8814B BIT(8) #define BIT_SW_LNAON_A_SEL_DATA_8814B BIT(7) -#define BIT_PAD_PAPE_SR_8814B BIT(6) -#define BIT_PAD_PAPE_E2_8814B BIT(5) #define BIT_SW_PAPE_G_SEL_DATA_8814B BIT(4) #define BIT_SW_PAPE_A_SEL_DATA_8814B BIT(3) -#define BIT_PAD_DPDT_SR_8814B BIT(2) -#define BIT_PAD_DPDT_PAD_E2_8814B BIT(1) #define BIT_SW_DPDT_SEL_DATA_8814B BIT(0) /* 2 REG_WL_BT_PWR_CTRL_8814B */ @@ -968,9 +1103,12 @@ #define BIT_FEN_BTGPS_8814B BIT(28) #define BIT_BTCPU_BOOTSEL_8814B BIT(27) #define BIT_SPI_SPEEDUP_8814B BIT(26) +#define BIT_BT_SUS_8814B BIT(25) #define BIT_DEVWAKE_PAD_TYPE_SEL_8814B BIT(24) #define BIT_CLKREQ_PAD_TYPE_SEL_8814B BIT(23) #define BIT_ISO_BTPON2PP_8814B BIT(22) +#define BIT_BTCOEX_CMD_8814B BIT(21) +#define BIT_BT_UART_INTF_8814B BIT(20) #define BIT_BT_HWROF_EN_8814B BIT(19) #define BIT_BT_FUNC_EN_8814B BIT(18) #define BIT_BT_HWPDN_SL_8814B BIT(17) @@ -983,6 +1121,8 @@ #define BIT_BT_AFE_LDO_EN_8814B BIT(10) #define BIT_BT_AFE_PLL_EN_8814B BIT(9) #define BIT_BT_DIG_CLK_EN_8814B BIT(8) +#define BIT_UART_BRIDGE_8814B BIT(7) +#define BIT_OSC32K_CTRL_SEL_8814B BIT(6) #define BIT_WL_DRV_EXIST_IDX_8814B BIT(5) #define BIT_DOP_EHPAD_8814B BIT(4) #define BIT_WL_HWROF_EN_8814B BIT(3) @@ -991,13 +1131,22 @@ #define BIT_WL_HWPDN_EN_8814B BIT(0) /* 2 REG_SDM_DEBUG_8814B */ +#define BIT_BT_WAKE_DEV_EN_V1_8814B BIT(19) +#define BIT_BT_WAKE_HST_EN_V1_8814B BIT(18) +#define BIT_BT_WAKE_HST_PL_V1_8814B BIT(17) +#define BIT_BT_CLKREQ_EN_V1_8814B BIT(16) #define BIT_SHIFT_WLCLK_PHASE_8814B 0 #define BIT_MASK_WLCLK_PHASE_8814B 0x1f -#define BIT_WLCLK_PHASE_8814B(x) (((x) & BIT_MASK_WLCLK_PHASE_8814B) << BIT_SHIFT_WLCLK_PHASE_8814B) -#define BIT_GET_WLCLK_PHASE_8814B(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8814B) & BIT_MASK_WLCLK_PHASE_8814B) - - +#define BIT_WLCLK_PHASE_8814B(x) \ + (((x) & BIT_MASK_WLCLK_PHASE_8814B) << BIT_SHIFT_WLCLK_PHASE_8814B) +#define BITS_WLCLK_PHASE_8814B \ + (BIT_MASK_WLCLK_PHASE_8814B << BIT_SHIFT_WLCLK_PHASE_8814B) +#define BIT_CLEAR_WLCLK_PHASE_8814B(x) ((x) & (~BITS_WLCLK_PHASE_8814B)) +#define BIT_GET_WLCLK_PHASE_8814B(x) \ + (((x) >> BIT_SHIFT_WLCLK_PHASE_8814B) & BIT_MASK_WLCLK_PHASE_8814B) +#define BIT_SET_WLCLK_PHASE_8814B(x, v) \ + (BIT_CLEAR_WLCLK_PHASE_8814B(x) | BIT_WLCLK_PHASE_8814B(v)) /* 2 REG_SYS_SDIO_CTRL_8814B */ #define BIT_DBG_GNT_WL_BT_8814B BIT(27) @@ -1011,6 +1160,36 @@ #define BIT_PCIE_WAIT_TIMEOUT_EVENT_8814B BIT(10) #define BIT_PCIE_WAIT_TIME_8814B BIT(9) #define BIT_MPCIE_REFCLK_XTAL_SEL_8814B BIT(8) +#define BIT_BT_CLKREQ_EN_8814B BIT(6) + +#define BIT_SHIFT_USB_CKREF_CML_R_8814B 4 +#define BIT_MASK_USB_CKREF_CML_R_8814B 0x3 +#define BIT_USB_CKREF_CML_R_8814B(x) \ + (((x) & BIT_MASK_USB_CKREF_CML_R_8814B) \ + << BIT_SHIFT_USB_CKREF_CML_R_8814B) +#define BITS_USB_CKREF_CML_R_8814B \ + (BIT_MASK_USB_CKREF_CML_R_8814B << BIT_SHIFT_USB_CKREF_CML_R_8814B) +#define BIT_CLEAR_USB_CKREF_CML_R_8814B(x) ((x) & (~BITS_USB_CKREF_CML_R_8814B)) +#define BIT_GET_USB_CKREF_CML_R_8814B(x) \ + (((x) >> BIT_SHIFT_USB_CKREF_CML_R_8814B) & \ + BIT_MASK_USB_CKREF_CML_R_8814B) +#define BIT_SET_USB_CKREF_CML_R_8814B(x, v) \ + (BIT_CLEAR_USB_CKREF_CML_R_8814B(x) | BIT_USB_CKREF_CML_R_8814B(v)) + +#define BIT_SHIFT_USB_CKREF_D2S_I_8814B 2 +#define BIT_MASK_USB_CKREF_D2S_I_8814B 0x3 +#define BIT_USB_CKREF_D2S_I_8814B(x) \ + (((x) & BIT_MASK_USB_CKREF_D2S_I_8814B) \ + << BIT_SHIFT_USB_CKREF_D2S_I_8814B) +#define BITS_USB_CKREF_D2S_I_8814B \ + (BIT_MASK_USB_CKREF_D2S_I_8814B << BIT_SHIFT_USB_CKREF_D2S_I_8814B) +#define BIT_CLEAR_USB_CKREF_D2S_I_8814B(x) ((x) & (~BITS_USB_CKREF_D2S_I_8814B)) +#define BIT_GET_USB_CKREF_D2S_I_8814B(x) \ + (((x) >> BIT_SHIFT_USB_CKREF_D2S_I_8814B) & \ + BIT_MASK_USB_CKREF_D2S_I_8814B) +#define BIT_SET_USB_CKREF_D2S_I_8814B(x, v) \ + (BIT_CLEAR_USB_CKREF_D2S_I_8814B(x) | BIT_USB_CKREF_D2S_I_8814B(v)) + #define BIT_RES_USB_MASS_STORAGE_DESC_8814B BIT(1) #define BIT_USB_WAIT_TIME_8814B BIT(0) @@ -1018,10 +1197,17 @@ #define BIT_SHIFT_TSFT_SEL_8814B 29 #define BIT_MASK_TSFT_SEL_8814B 0x7 -#define BIT_TSFT_SEL_8814B(x) (((x) & BIT_MASK_TSFT_SEL_8814B) << BIT_SHIFT_TSFT_SEL_8814B) -#define BIT_GET_TSFT_SEL_8814B(x) (((x) >> BIT_SHIFT_TSFT_SEL_8814B) & BIT_MASK_TSFT_SEL_8814B) - - +#define BIT_TSFT_SEL_8814B(x) \ + (((x) & BIT_MASK_TSFT_SEL_8814B) << BIT_SHIFT_TSFT_SEL_8814B) +#define BITS_TSFT_SEL_8814B \ + (BIT_MASK_TSFT_SEL_8814B << BIT_SHIFT_TSFT_SEL_8814B) +#define BIT_CLEAR_TSFT_SEL_8814B(x) ((x) & (~BITS_TSFT_SEL_8814B)) +#define BIT_GET_TSFT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_8814B) & BIT_MASK_TSFT_SEL_8814B) +#define BIT_SET_TSFT_SEL_8814B(x, v) \ + (BIT_CLEAR_TSFT_SEL_8814B(x) | BIT_TSFT_SEL_8814B(v)) + +#define BIT_TSFT_BAND_SEL_8814B BIT(28) #define BIT_USB_HOST_PWR_OFF_EN_8814B BIT(12) #define BIT_SYM_LPS_BLOCK_EN_8814B BIT(11) #define BIT_USB_LPM_ACT_EN_8814B BIT(10) @@ -1030,9 +1216,15 @@ #define BIT_SHIFT_SDIO_PAD_E_8814B 5 #define BIT_MASK_SDIO_PAD_E_8814B 0x7 -#define BIT_SDIO_PAD_E_8814B(x) (((x) & BIT_MASK_SDIO_PAD_E_8814B) << BIT_SHIFT_SDIO_PAD_E_8814B) -#define BIT_GET_SDIO_PAD_E_8814B(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8814B) & BIT_MASK_SDIO_PAD_E_8814B) - +#define BIT_SDIO_PAD_E_8814B(x) \ + (((x) & BIT_MASK_SDIO_PAD_E_8814B) << BIT_SHIFT_SDIO_PAD_E_8814B) +#define BITS_SDIO_PAD_E_8814B \ + (BIT_MASK_SDIO_PAD_E_8814B << BIT_SHIFT_SDIO_PAD_E_8814B) +#define BIT_CLEAR_SDIO_PAD_E_8814B(x) ((x) & (~BITS_SDIO_PAD_E_8814B)) +#define BIT_GET_SDIO_PAD_E_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_PAD_E_8814B) & BIT_MASK_SDIO_PAD_E_8814B) +#define BIT_SET_SDIO_PAD_E_8814B(x, v) \ + (BIT_CLEAR_SDIO_PAD_E_8814B(x) | BIT_SDIO_PAD_E_8814B(v)) #define BIT_USB_LPPLL_EN_8814B BIT(4) #define BIT_ROP_SW15_8814B BIT(2) @@ -1041,71 +1233,63 @@ /* 2 REG_AFE_CTRL4_8814B */ +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + /* 2 REG_LDO_SWR_CTRL_8814B */ #define BIT_ZCD_HW_AUTO_EN_8814B BIT(27) #define BIT_ZCD_REGSEL_8814B BIT(26) #define BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B 21 #define BIT_MASK_AUTO_ZCD_IN_CODE_8814B 0x1f -#define BIT_AUTO_ZCD_IN_CODE_8814B(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8814B) << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) -#define BIT_GET_AUTO_ZCD_IN_CODE_8814B(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) & BIT_MASK_AUTO_ZCD_IN_CODE_8814B) - - +#define BIT_AUTO_ZCD_IN_CODE_8814B(x) \ + (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8814B) \ + << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) +#define BITS_AUTO_ZCD_IN_CODE_8814B \ + (BIT_MASK_AUTO_ZCD_IN_CODE_8814B << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) +#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8814B(x) \ + ((x) & (~BITS_AUTO_ZCD_IN_CODE_8814B)) +#define BIT_GET_AUTO_ZCD_IN_CODE_8814B(x) \ + (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) & \ + BIT_MASK_AUTO_ZCD_IN_CODE_8814B) +#define BIT_SET_AUTO_ZCD_IN_CODE_8814B(x, v) \ + (BIT_CLEAR_AUTO_ZCD_IN_CODE_8814B(x) | BIT_AUTO_ZCD_IN_CODE_8814B(v)) #define BIT_SHIFT_ZCD_CODE_IN_L_8814B 16 #define BIT_MASK_ZCD_CODE_IN_L_8814B 0x1f -#define BIT_ZCD_CODE_IN_L_8814B(x) (((x) & BIT_MASK_ZCD_CODE_IN_L_8814B) << BIT_SHIFT_ZCD_CODE_IN_L_8814B) -#define BIT_GET_ZCD_CODE_IN_L_8814B(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8814B) & BIT_MASK_ZCD_CODE_IN_L_8814B) +#define BIT_ZCD_CODE_IN_L_8814B(x) \ + (((x) & BIT_MASK_ZCD_CODE_IN_L_8814B) << BIT_SHIFT_ZCD_CODE_IN_L_8814B) +#define BITS_ZCD_CODE_IN_L_8814B \ + (BIT_MASK_ZCD_CODE_IN_L_8814B << BIT_SHIFT_ZCD_CODE_IN_L_8814B) +#define BIT_CLEAR_ZCD_CODE_IN_L_8814B(x) ((x) & (~BITS_ZCD_CODE_IN_L_8814B)) +#define BIT_GET_ZCD_CODE_IN_L_8814B(x) \ + (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8814B) & BIT_MASK_ZCD_CODE_IN_L_8814B) +#define BIT_SET_ZCD_CODE_IN_L_8814B(x, v) \ + (BIT_CLEAR_ZCD_CODE_IN_L_8814B(x) | BIT_ZCD_CODE_IN_L_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_LDO_HV5_DUMMY_8814B 14 -#define BIT_MASK_LDO_HV5_DUMMY_8814B 0x3 -#define BIT_LDO_HV5_DUMMY_8814B(x) (((x) & BIT_MASK_LDO_HV5_DUMMY_8814B) << BIT_SHIFT_LDO_HV5_DUMMY_8814B) -#define BIT_GET_LDO_HV5_DUMMY_8814B(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8814B) & BIT_MASK_LDO_HV5_DUMMY_8814B) - - - -#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8814B 12 -#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8814B 0x3 -#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8814B(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8814B) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8814B) -#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8814B(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8814B) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8814B) - - - -#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8814B 10 -#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8814B 0x3 -#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8814B(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8814B) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8814B) -#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8814B(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8814B) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8814B) - - - -#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8814B 8 -#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8814B 0x3 -#define BIT_REG_LOAD33_BIT0_TO_BIT1_8814B(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8814B) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8814B) -#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8814B(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8814B) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8814B) - - -#define BIT_REG_BYPASS_L_8814B BIT(7) -#define BIT_REG_LDOF_L_8814B BIT(6) -#define BIT_REG_OCPS_L_8814B BIT(5) -#define BIT_ARENB_L_8814B BIT(3) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CFC_L_8814B 1 -#define BIT_MASK_CFC_L_8814B 0x3 -#define BIT_CFC_L_8814B(x) (((x) & BIT_MASK_CFC_L_8814B) << BIT_SHIFT_CFC_L_8814B) -#define BIT_GET_CFC_L_8814B(x) (((x) >> BIT_SHIFT_CFC_L_8814B) & BIT_MASK_CFC_L_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_TYPE_L_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_MCUFW_CTRL_8814B */ #define BIT_SHIFT_RPWM_8814B 24 #define BIT_MASK_RPWM_8814B 0xff #define BIT_RPWM_8814B(x) (((x) & BIT_MASK_RPWM_8814B) << BIT_SHIFT_RPWM_8814B) -#define BIT_GET_RPWM_8814B(x) (((x) >> BIT_SHIFT_RPWM_8814B) & BIT_MASK_RPWM_8814B) - +#define BITS_RPWM_8814B (BIT_MASK_RPWM_8814B << BIT_SHIFT_RPWM_8814B) +#define BIT_CLEAR_RPWM_8814B(x) ((x) & (~BITS_RPWM_8814B)) +#define BIT_GET_RPWM_8814B(x) \ + (((x) >> BIT_SHIFT_RPWM_8814B) & BIT_MASK_RPWM_8814B) +#define BIT_SET_RPWM_8814B(x, v) (BIT_CLEAR_RPWM_8814B(x) | BIT_RPWM_8814B(v)) #define BIT_ANA_PORT_EN_8814B BIT(22) #define BIT_MAC_PORT_EN_8814B BIT(21) @@ -1114,18 +1298,29 @@ #define BIT_SHIFT_ROM_PGE_8814B 16 #define BIT_MASK_ROM_PGE_8814B 0x7 -#define BIT_ROM_PGE_8814B(x) (((x) & BIT_MASK_ROM_PGE_8814B) << BIT_SHIFT_ROM_PGE_8814B) -#define BIT_GET_ROM_PGE_8814B(x) (((x) >> BIT_SHIFT_ROM_PGE_8814B) & BIT_MASK_ROM_PGE_8814B) - +#define BIT_ROM_PGE_8814B(x) \ + (((x) & BIT_MASK_ROM_PGE_8814B) << BIT_SHIFT_ROM_PGE_8814B) +#define BITS_ROM_PGE_8814B (BIT_MASK_ROM_PGE_8814B << BIT_SHIFT_ROM_PGE_8814B) +#define BIT_CLEAR_ROM_PGE_8814B(x) ((x) & (~BITS_ROM_PGE_8814B)) +#define BIT_GET_ROM_PGE_8814B(x) \ + (((x) >> BIT_SHIFT_ROM_PGE_8814B) & BIT_MASK_ROM_PGE_8814B) +#define BIT_SET_ROM_PGE_8814B(x, v) \ + (BIT_CLEAR_ROM_PGE_8814B(x) | BIT_ROM_PGE_8814B(v)) #define BIT_FW_INIT_RDY_8814B BIT(15) #define BIT_FW_DW_RDY_8814B BIT(14) #define BIT_SHIFT_CPU_CLK_SEL_8814B 12 #define BIT_MASK_CPU_CLK_SEL_8814B 0x3 -#define BIT_CPU_CLK_SEL_8814B(x) (((x) & BIT_MASK_CPU_CLK_SEL_8814B) << BIT_SHIFT_CPU_CLK_SEL_8814B) -#define BIT_GET_CPU_CLK_SEL_8814B(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8814B) & BIT_MASK_CPU_CLK_SEL_8814B) - +#define BIT_CPU_CLK_SEL_8814B(x) \ + (((x) & BIT_MASK_CPU_CLK_SEL_8814B) << BIT_SHIFT_CPU_CLK_SEL_8814B) +#define BITS_CPU_CLK_SEL_8814B \ + (BIT_MASK_CPU_CLK_SEL_8814B << BIT_SHIFT_CPU_CLK_SEL_8814B) +#define BIT_CLEAR_CPU_CLK_SEL_8814B(x) ((x) & (~BITS_CPU_CLK_SEL_8814B)) +#define BIT_GET_CPU_CLK_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_CPU_CLK_SEL_8814B) & BIT_MASK_CPU_CLK_SEL_8814B) +#define BIT_SET_CPU_CLK_SEL_8814B(x, v) \ + (BIT_CLEAR_CPU_CLK_SEL_8814B(x) | BIT_CPU_CLK_SEL_8814B(v)) #define BIT_CCLK_CHG_MASK_8814B BIT(11) #define BIT_EMEM__TXBUF_CHKSUM_OK_8814B BIT(10) @@ -1142,44 +1337,68 @@ /* 2 REG_MCU_TST_CFG_8814B */ -#define BIT_SHIFT_LBKTST_8814B 0 -#define BIT_MASK_LBKTST_8814B 0xffff -#define BIT_LBKTST_8814B(x) (((x) & BIT_MASK_LBKTST_8814B) << BIT_SHIFT_LBKTST_8814B) -#define BIT_GET_LBKTST_8814B(x) (((x) >> BIT_SHIFT_LBKTST_8814B) & BIT_MASK_LBKTST_8814B) - - +#define BIT_SHIFT_C2H_MSG_8814B 0 +#define BIT_MASK_C2H_MSG_8814B 0xffff +#define BIT_C2H_MSG_8814B(x) \ + (((x) & BIT_MASK_C2H_MSG_8814B) << BIT_SHIFT_C2H_MSG_8814B) +#define BITS_C2H_MSG_8814B (BIT_MASK_C2H_MSG_8814B << BIT_SHIFT_C2H_MSG_8814B) +#define BIT_CLEAR_C2H_MSG_8814B(x) ((x) & (~BITS_C2H_MSG_8814B)) +#define BIT_GET_C2H_MSG_8814B(x) \ + (((x) >> BIT_SHIFT_C2H_MSG_8814B) & BIT_MASK_C2H_MSG_8814B) +#define BIT_SET_C2H_MSG_8814B(x, v) \ + (BIT_CLEAR_C2H_MSG_8814B(x) | BIT_C2H_MSG_8814B(v)) /* 2 REG_HMEBOX_E0_E1_8814B */ #define BIT_SHIFT_HOST_MSG_E1_8814B 16 #define BIT_MASK_HOST_MSG_E1_8814B 0xffff -#define BIT_HOST_MSG_E1_8814B(x) (((x) & BIT_MASK_HOST_MSG_E1_8814B) << BIT_SHIFT_HOST_MSG_E1_8814B) -#define BIT_GET_HOST_MSG_E1_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8814B) & BIT_MASK_HOST_MSG_E1_8814B) - - +#define BIT_HOST_MSG_E1_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_E1_8814B) << BIT_SHIFT_HOST_MSG_E1_8814B) +#define BITS_HOST_MSG_E1_8814B \ + (BIT_MASK_HOST_MSG_E1_8814B << BIT_SHIFT_HOST_MSG_E1_8814B) +#define BIT_CLEAR_HOST_MSG_E1_8814B(x) ((x) & (~BITS_HOST_MSG_E1_8814B)) +#define BIT_GET_HOST_MSG_E1_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E1_8814B) & BIT_MASK_HOST_MSG_E1_8814B) +#define BIT_SET_HOST_MSG_E1_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_E1_8814B(x) | BIT_HOST_MSG_E1_8814B(v)) #define BIT_SHIFT_HOST_MSG_E0_8814B 0 #define BIT_MASK_HOST_MSG_E0_8814B 0xffff -#define BIT_HOST_MSG_E0_8814B(x) (((x) & BIT_MASK_HOST_MSG_E0_8814B) << BIT_SHIFT_HOST_MSG_E0_8814B) -#define BIT_GET_HOST_MSG_E0_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8814B) & BIT_MASK_HOST_MSG_E0_8814B) - - +#define BIT_HOST_MSG_E0_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_E0_8814B) << BIT_SHIFT_HOST_MSG_E0_8814B) +#define BITS_HOST_MSG_E0_8814B \ + (BIT_MASK_HOST_MSG_E0_8814B << BIT_SHIFT_HOST_MSG_E0_8814B) +#define BIT_CLEAR_HOST_MSG_E0_8814B(x) ((x) & (~BITS_HOST_MSG_E0_8814B)) +#define BIT_GET_HOST_MSG_E0_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E0_8814B) & BIT_MASK_HOST_MSG_E0_8814B) +#define BIT_SET_HOST_MSG_E0_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_E0_8814B(x) | BIT_HOST_MSG_E0_8814B(v)) /* 2 REG_HMEBOX_E2_E3_8814B */ #define BIT_SHIFT_HOST_MSG_E3_8814B 16 #define BIT_MASK_HOST_MSG_E3_8814B 0xffff -#define BIT_HOST_MSG_E3_8814B(x) (((x) & BIT_MASK_HOST_MSG_E3_8814B) << BIT_SHIFT_HOST_MSG_E3_8814B) -#define BIT_GET_HOST_MSG_E3_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8814B) & BIT_MASK_HOST_MSG_E3_8814B) - - +#define BIT_HOST_MSG_E3_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_E3_8814B) << BIT_SHIFT_HOST_MSG_E3_8814B) +#define BITS_HOST_MSG_E3_8814B \ + (BIT_MASK_HOST_MSG_E3_8814B << BIT_SHIFT_HOST_MSG_E3_8814B) +#define BIT_CLEAR_HOST_MSG_E3_8814B(x) ((x) & (~BITS_HOST_MSG_E3_8814B)) +#define BIT_GET_HOST_MSG_E3_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E3_8814B) & BIT_MASK_HOST_MSG_E3_8814B) +#define BIT_SET_HOST_MSG_E3_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_E3_8814B(x) | BIT_HOST_MSG_E3_8814B(v)) #define BIT_SHIFT_HOST_MSG_E2_8814B 0 #define BIT_MASK_HOST_MSG_E2_8814B 0xffff -#define BIT_HOST_MSG_E2_8814B(x) (((x) & BIT_MASK_HOST_MSG_E2_8814B) << BIT_SHIFT_HOST_MSG_E2_8814B) -#define BIT_GET_HOST_MSG_E2_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8814B) & BIT_MASK_HOST_MSG_E2_8814B) - - +#define BIT_HOST_MSG_E2_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_E2_8814B) << BIT_SHIFT_HOST_MSG_E2_8814B) +#define BITS_HOST_MSG_E2_8814B \ + (BIT_MASK_HOST_MSG_E2_8814B << BIT_SHIFT_HOST_MSG_E2_8814B) +#define BIT_CLEAR_HOST_MSG_E2_8814B(x) ((x) & (~BITS_HOST_MSG_E2_8814B)) +#define BIT_GET_HOST_MSG_E2_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E2_8814B) & BIT_MASK_HOST_MSG_E2_8814B) +#define BIT_SET_HOST_MSG_E2_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_E2_8814B(x) | BIT_HOST_MSG_E2_8814B(v)) /* 2 REG_WLLPS_CTRL_8814B */ #define BIT_WLLPSOP_EABM_8814B BIT(31) @@ -1196,205 +1415,267 @@ #define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B 12 #define BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B 0xf -#define BIT_LPLDH12_VADJ_STEP_DN_8814B(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) -#define BIT_GET_LPLDH12_VADJ_STEP_DN_8814B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B) - - +#define BIT_LPLDH12_VADJ_STEP_DN_8814B(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B) \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) +#define BITS_LPLDH12_VADJ_STEP_DN_8814B \ + (BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) +#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8814B(x) \ + ((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8814B)) +#define BIT_GET_LPLDH12_VADJ_STEP_DN_8814B(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) & \ + BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B) +#define BIT_SET_LPLDH12_VADJ_STEP_DN_8814B(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8814B(x) | \ + BIT_LPLDH12_VADJ_STEP_DN_8814B(v)) #define BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B 8 #define BIT_MASK_V15ADJ_L1_STEP_DN_8814B 0x7 -#define BIT_V15ADJ_L1_STEP_DN_8814B(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8814B) << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) -#define BIT_GET_V15ADJ_L1_STEP_DN_8814B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) & BIT_MASK_V15ADJ_L1_STEP_DN_8814B) - +#define BIT_V15ADJ_L1_STEP_DN_8814B(x) \ + (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8814B) \ + << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) +#define BITS_V15ADJ_L1_STEP_DN_8814B \ + (BIT_MASK_V15ADJ_L1_STEP_DN_8814B << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) +#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8814B(x) \ + ((x) & (~BITS_V15ADJ_L1_STEP_DN_8814B)) +#define BIT_GET_V15ADJ_L1_STEP_DN_8814B(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) & \ + BIT_MASK_V15ADJ_L1_STEP_DN_8814B) +#define BIT_SET_V15ADJ_L1_STEP_DN_8814B(x, v) \ + (BIT_CLEAR_V15ADJ_L1_STEP_DN_8814B(x) | BIT_V15ADJ_L1_STEP_DN_8814B(v)) #define BIT_REGU_32K_CLK_EN_8814B BIT(1) #define BIT_WL_LPS_EN_8814B BIT(0) /* 2 REG_AFE_CTRL5_8814B */ -#define BIT_BB_DBG_SEL_AFE_SDM_BIT0_8814B BIT(31) -#define BIT_ORDER_SDM_8814B BIT(30) -#define BIT_RFE_SEL_SDM_8814B BIT(29) - -#define BIT_SHIFT_REF_SEL_8814B 25 -#define BIT_MASK_REF_SEL_8814B 0xf -#define BIT_REF_SEL_8814B(x) (((x) & BIT_MASK_REF_SEL_8814B) << BIT_SHIFT_REF_SEL_8814B) -#define BIT_GET_REF_SEL_8814B(x) (((x) >> BIT_SHIFT_REF_SEL_8814B) & BIT_MASK_REF_SEL_8814B) - - -#define BIT_SHIFT_F0F_SDM_8814B 12 -#define BIT_MASK_F0F_SDM_8814B 0x1fff -#define BIT_F0F_SDM_8814B(x) (((x) & BIT_MASK_F0F_SDM_8814B) << BIT_SHIFT_F0F_SDM_8814B) -#define BIT_GET_F0F_SDM_8814B(x) (((x) >> BIT_SHIFT_F0F_SDM_8814B) & BIT_MASK_F0F_SDM_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_F0N_SDM_8814B 9 -#define BIT_MASK_F0N_SDM_8814B 0x7 -#define BIT_F0N_SDM_8814B(x) (((x) & BIT_MASK_F0N_SDM_8814B) << BIT_SHIFT_F0N_SDM_8814B) -#define BIT_GET_F0N_SDM_8814B(x) (((x) >> BIT_SHIFT_F0N_SDM_8814B) & BIT_MASK_F0N_SDM_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DIVN_SDM_8814B 3 -#define BIT_MASK_DIVN_SDM_8814B 0x3f -#define BIT_DIVN_SDM_8814B(x) (((x) & BIT_MASK_DIVN_SDM_8814B) << BIT_SHIFT_DIVN_SDM_8814B) -#define BIT_GET_DIVN_SDM_8814B(x) (((x) >> BIT_SHIFT_DIVN_SDM_8814B) & BIT_MASK_DIVN_SDM_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_GPIO_DEBOUNCE_CTRL_8814B */ #define BIT_WLGP_DBC1EN_8814B BIT(15) #define BIT_SHIFT_WLGP_DBC1_8814B 8 #define BIT_MASK_WLGP_DBC1_8814B 0xf -#define BIT_WLGP_DBC1_8814B(x) (((x) & BIT_MASK_WLGP_DBC1_8814B) << BIT_SHIFT_WLGP_DBC1_8814B) -#define BIT_GET_WLGP_DBC1_8814B(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8814B) & BIT_MASK_WLGP_DBC1_8814B) - +#define BIT_WLGP_DBC1_8814B(x) \ + (((x) & BIT_MASK_WLGP_DBC1_8814B) << BIT_SHIFT_WLGP_DBC1_8814B) +#define BITS_WLGP_DBC1_8814B \ + (BIT_MASK_WLGP_DBC1_8814B << BIT_SHIFT_WLGP_DBC1_8814B) +#define BIT_CLEAR_WLGP_DBC1_8814B(x) ((x) & (~BITS_WLGP_DBC1_8814B)) +#define BIT_GET_WLGP_DBC1_8814B(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC1_8814B) & BIT_MASK_WLGP_DBC1_8814B) +#define BIT_SET_WLGP_DBC1_8814B(x, v) \ + (BIT_CLEAR_WLGP_DBC1_8814B(x) | BIT_WLGP_DBC1_8814B(v)) #define BIT_WLGP_DBC0EN_8814B BIT(7) #define BIT_SHIFT_WLGP_DBC0_8814B 0 #define BIT_MASK_WLGP_DBC0_8814B 0xf -#define BIT_WLGP_DBC0_8814B(x) (((x) & BIT_MASK_WLGP_DBC0_8814B) << BIT_SHIFT_WLGP_DBC0_8814B) -#define BIT_GET_WLGP_DBC0_8814B(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8814B) & BIT_MASK_WLGP_DBC0_8814B) - - +#define BIT_WLGP_DBC0_8814B(x) \ + (((x) & BIT_MASK_WLGP_DBC0_8814B) << BIT_SHIFT_WLGP_DBC0_8814B) +#define BITS_WLGP_DBC0_8814B \ + (BIT_MASK_WLGP_DBC0_8814B << BIT_SHIFT_WLGP_DBC0_8814B) +#define BIT_CLEAR_WLGP_DBC0_8814B(x) ((x) & (~BITS_WLGP_DBC0_8814B)) +#define BIT_GET_WLGP_DBC0_8814B(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC0_8814B) & BIT_MASK_WLGP_DBC0_8814B) +#define BIT_SET_WLGP_DBC0_8814B(x, v) \ + (BIT_CLEAR_WLGP_DBC0_8814B(x) | BIT_WLGP_DBC0_8814B(v)) /* 2 REG_RPWM2_8814B */ #define BIT_SHIFT_RPWM2_8814B 16 #define BIT_MASK_RPWM2_8814B 0xffff -#define BIT_RPWM2_8814B(x) (((x) & BIT_MASK_RPWM2_8814B) << BIT_SHIFT_RPWM2_8814B) -#define BIT_GET_RPWM2_8814B(x) (((x) >> BIT_SHIFT_RPWM2_8814B) & BIT_MASK_RPWM2_8814B) - - +#define BIT_RPWM2_8814B(x) \ + (((x) & BIT_MASK_RPWM2_8814B) << BIT_SHIFT_RPWM2_8814B) +#define BITS_RPWM2_8814B (BIT_MASK_RPWM2_8814B << BIT_SHIFT_RPWM2_8814B) +#define BIT_CLEAR_RPWM2_8814B(x) ((x) & (~BITS_RPWM2_8814B)) +#define BIT_GET_RPWM2_8814B(x) \ + (((x) >> BIT_SHIFT_RPWM2_8814B) & BIT_MASK_RPWM2_8814B) +#define BIT_SET_RPWM2_8814B(x, v) \ + (BIT_CLEAR_RPWM2_8814B(x) | BIT_RPWM2_8814B(v)) /* 2 REG_SYSON_FSM_MON_8814B */ #define BIT_SHIFT_FSM_MON_SEL_8814B 24 #define BIT_MASK_FSM_MON_SEL_8814B 0x7 -#define BIT_FSM_MON_SEL_8814B(x) (((x) & BIT_MASK_FSM_MON_SEL_8814B) << BIT_SHIFT_FSM_MON_SEL_8814B) -#define BIT_GET_FSM_MON_SEL_8814B(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8814B) & BIT_MASK_FSM_MON_SEL_8814B) - +#define BIT_FSM_MON_SEL_8814B(x) \ + (((x) & BIT_MASK_FSM_MON_SEL_8814B) << BIT_SHIFT_FSM_MON_SEL_8814B) +#define BITS_FSM_MON_SEL_8814B \ + (BIT_MASK_FSM_MON_SEL_8814B << BIT_SHIFT_FSM_MON_SEL_8814B) +#define BIT_CLEAR_FSM_MON_SEL_8814B(x) ((x) & (~BITS_FSM_MON_SEL_8814B)) +#define BIT_GET_FSM_MON_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_FSM_MON_SEL_8814B) & BIT_MASK_FSM_MON_SEL_8814B) +#define BIT_SET_FSM_MON_SEL_8814B(x, v) \ + (BIT_CLEAR_FSM_MON_SEL_8814B(x) | BIT_FSM_MON_SEL_8814B(v)) #define BIT_DOP_ELDO_8814B BIT(23) #define BIT_FSM_MON_UPD_8814B BIT(15) #define BIT_SHIFT_FSM_PAR_8814B 0 #define BIT_MASK_FSM_PAR_8814B 0x7fff -#define BIT_FSM_PAR_8814B(x) (((x) & BIT_MASK_FSM_PAR_8814B) << BIT_SHIFT_FSM_PAR_8814B) -#define BIT_GET_FSM_PAR_8814B(x) (((x) >> BIT_SHIFT_FSM_PAR_8814B) & BIT_MASK_FSM_PAR_8814B) - - +#define BIT_FSM_PAR_8814B(x) \ + (((x) & BIT_MASK_FSM_PAR_8814B) << BIT_SHIFT_FSM_PAR_8814B) +#define BITS_FSM_PAR_8814B (BIT_MASK_FSM_PAR_8814B << BIT_SHIFT_FSM_PAR_8814B) +#define BIT_CLEAR_FSM_PAR_8814B(x) ((x) & (~BITS_FSM_PAR_8814B)) +#define BIT_GET_FSM_PAR_8814B(x) \ + (((x) >> BIT_SHIFT_FSM_PAR_8814B) & BIT_MASK_FSM_PAR_8814B) +#define BIT_SET_FSM_PAR_8814B(x, v) \ + (BIT_CLEAR_FSM_PAR_8814B(x) | BIT_FSM_PAR_8814B(v)) /* 2 REG_AFE_CTRL6_8814B */ -#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B 0 -#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B 0x7 -#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B) - +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_PMC_DBG_CTRL1_8814B */ #define BIT_BT_INT_EN_8814B BIT(31) #define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B 16 #define BIT_MASK_RD_WR_WIFI_BT_INFO_8814B 0x7fff -#define BIT_RD_WR_WIFI_BT_INFO_8814B(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8814B) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) -#define BIT_GET_RD_WR_WIFI_BT_INFO_8814B(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) & BIT_MASK_RD_WR_WIFI_BT_INFO_8814B) - +#define BIT_RD_WR_WIFI_BT_INFO_8814B(x) \ + (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8814B) \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) +#define BITS_RD_WR_WIFI_BT_INFO_8814B \ + (BIT_MASK_RD_WR_WIFI_BT_INFO_8814B \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8814B(x) \ + ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8814B)) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) & \ + BIT_MASK_RD_WR_WIFI_BT_INFO_8814B) +#define BIT_SET_RD_WR_WIFI_BT_INFO_8814B(x, v) \ + (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8814B(x) | \ + BIT_RD_WR_WIFI_BT_INFO_8814B(v)) #define BIT_PMC_WR_OVF_8814B BIT(8) #define BIT_SHIFT_WLPMC_ERRINT_8814B 0 #define BIT_MASK_WLPMC_ERRINT_8814B 0xff -#define BIT_WLPMC_ERRINT_8814B(x) (((x) & BIT_MASK_WLPMC_ERRINT_8814B) << BIT_SHIFT_WLPMC_ERRINT_8814B) -#define BIT_GET_WLPMC_ERRINT_8814B(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8814B) & BIT_MASK_WLPMC_ERRINT_8814B) +#define BIT_WLPMC_ERRINT_8814B(x) \ + (((x) & BIT_MASK_WLPMC_ERRINT_8814B) << BIT_SHIFT_WLPMC_ERRINT_8814B) +#define BITS_WLPMC_ERRINT_8814B \ + (BIT_MASK_WLPMC_ERRINT_8814B << BIT_SHIFT_WLPMC_ERRINT_8814B) +#define BIT_CLEAR_WLPMC_ERRINT_8814B(x) ((x) & (~BITS_WLPMC_ERRINT_8814B)) +#define BIT_GET_WLPMC_ERRINT_8814B(x) \ + (((x) >> BIT_SHIFT_WLPMC_ERRINT_8814B) & BIT_MASK_WLPMC_ERRINT_8814B) +#define BIT_SET_WLPMC_ERRINT_8814B(x, v) \ + (BIT_CLEAR_WLPMC_ERRINT_8814B(x) | BIT_WLPMC_ERRINT_8814B(v)) +/* 2 REG_AFE_CTRL7_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_AFE_CTRL7_8814B */ +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SEL_V_8814B 30 -#define BIT_MASK_SEL_V_8814B 0x3 -#define BIT_SEL_V_8814B(x) (((x) & BIT_MASK_SEL_V_8814B) << BIT_SHIFT_SEL_V_8814B) -#define BIT_GET_SEL_V_8814B(x) (((x) >> BIT_SHIFT_SEL_V_8814B) & BIT_MASK_SEL_V_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SEL_LDO_PC_8814B BIT(29) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CK_MON_SEL_8814B 26 -#define BIT_MASK_CK_MON_SEL_8814B 0x7 -#define BIT_CK_MON_SEL_8814B(x) (((x) & BIT_MASK_CK_MON_SEL_8814B) << BIT_SHIFT_CK_MON_SEL_8814B) -#define BIT_GET_CK_MON_SEL_8814B(x) (((x) >> BIT_SHIFT_CK_MON_SEL_8814B) & BIT_MASK_CK_MON_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_CK_MON_EN_8814B BIT(25) -#define BIT_FREF_EDGE_8814B BIT(24) -#define BIT_CK320M_EN_8814B BIT(23) -#define BIT_CK_5M_EN_8814B BIT(22) -#define BIT_TESTEN_8814B BIT(21) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_HIMR0_8814B */ -#define BIT_TIMEOUT_INTERRUPT2_MASK_8814B BIT(31) -#define BIT_TIMEOUT_INTERRUTP1_MASK_8814B BIT(30) -#define BIT_PSTIMEOUT_MSK_8814B BIT(29) +#define BIT_PSTIMER_2_MSK_8814B BIT(31) +#define BIT_PSTIMER_1_MSK_8814B BIT(30) +#define BIT_PSTIMER_0_MSK_8814B BIT(29) #define BIT_GTINT4_MSK_8814B BIT(28) #define BIT_GTINT3_MSK_8814B BIT(27) #define BIT_TXBCN0ERR_MSK_8814B BIT(26) #define BIT_TXBCN0OK_MSK_8814B BIT(25) #define BIT_TSF_BIT32_TOGGLE_MSK_8814B BIT(24) +#define BIT_TXDMA_START_INT_MSK_8814B BIT(23) +#define BIT_TXDMA_STOP_INT_MSK_8814B BIT(22) +#define BIT_HISR7_IND_MSK_8814B BIT(21) #define BIT_BCNDMAINT0_MSK_8814B BIT(20) +#define BIT_HISR6_IND_MSK_8814B BIT(19) +#define BIT_HISR5_IND_MSK_8814B BIT(18) +#define BIT_HISR4_IND_MSK_8814B BIT(17) #define BIT_BCNDERR0_MSK_8814B BIT(16) #define BIT_HSISR_IND_ON_INT_MSK_8814B BIT(15) -#define BIT_BCNDMAINT_E_MSK_8814B BIT(14) -#define BIT_CTWEND_MSK_8814B BIT(12) +#define BIT_HISR3_IND_MSK_8814B BIT(14) +#define BIT_HISR2_IND_MSK_8814B BIT(13) + +/* 2 REG_NOT_VALID_8814B */ #define BIT_HISR1_IND_MSK_8814B BIT(11) #define BIT_C2HCMD_MSK_8814B BIT(10) #define BIT_CPWM2_MSK_8814B BIT(9) #define BIT_CPWM_MSK_8814B BIT(8) -#define BIT_HIGHDOK_MSK_8814B BIT(7) -#define BIT_MGTDOK_MSK_8814B BIT(6) -#define BIT_BKDOK_MSK_8814B BIT(5) -#define BIT_BEDOK_MSK_8814B BIT(4) -#define BIT_VIDOK_MSK_8814B BIT(3) -#define BIT_VODOK_MSK_8814B BIT(2) +#define BIT_TXDMAOK_CHANNEL15_MSK_8814B BIT(7) +#define BIT_TXDMAOK_CHANNEL14_MSK_8814B BIT(6) +#define BIT_TXDMAOK_CHANNEL3_MSK_8814B BIT(5) +#define BIT_TXDMAOK_CHANNEL2_MSK_8814B BIT(4) +#define BIT_TXDMAOK_CHANNEL1_MSK_8814B BIT(3) +#define BIT_TXDMAOK_CHANNEL0_MSK_8814B BIT(2) #define BIT_RDU_MSK_8814B BIT(1) #define BIT_RXOK_MSK_8814B BIT(0) /* 2 REG_HISR0_8814B */ -#define BIT_TIMEOUT_INTERRUPT2_8814B BIT(31) -#define BIT_TIMEOUT_INTERRUTP1_8814B BIT(30) -#define BIT_PSTIMEOUT_8814B BIT(29) +#define BIT_PSTIMER_2_8814B BIT(31) +#define BIT_PSTIMER_1_8814B BIT(30) +#define BIT_PSTIMER_0_8814B BIT(29) #define BIT_GTINT4_8814B BIT(28) #define BIT_GTINT3_8814B BIT(27) #define BIT_TXBCN0ERR_8814B BIT(26) #define BIT_TXBCN0OK_8814B BIT(25) #define BIT_TSF_BIT32_TOGGLE_8814B BIT(24) +#define BIT_TXDMA_START_INT_8814B BIT(23) +#define BIT_TXDMA_STOP_INT_8814B BIT(22) +#define BIT_HISR7_IND_8814B BIT(21) #define BIT_BCNDMAINT0_8814B BIT(20) +#define BIT_HISR6_IND_8814B BIT(19) +#define BIT_HISR5_IND_8814B BIT(18) +#define BIT_HISR4_IND_8814B BIT(17) #define BIT_BCNDERR0_8814B BIT(16) #define BIT_HSISR_IND_ON_INT_8814B BIT(15) -#define BIT_BCNDMAINT_E_8814B BIT(14) -#define BIT_CTWEND_8814B BIT(12) -#define BIT_HISR1_IND_INT_8814B BIT(11) +#define BIT_HISR3_IND_8814B BIT(14) +#define BIT_HISR2_IND_8814B BIT(13) + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_HISR1_IND_8814B BIT(11) #define BIT_C2HCMD_8814B BIT(10) #define BIT_CPWM2_8814B BIT(9) #define BIT_CPWM_8814B BIT(8) -#define BIT_HIGHDOK_8814B BIT(7) -#define BIT_MGTDOK_8814B BIT(6) -#define BIT_BKDOK_8814B BIT(5) -#define BIT_BEDOK_8814B BIT(4) -#define BIT_VIDOK_8814B BIT(3) -#define BIT_VODOK_8814B BIT(2) +#define BIT_TXDMAOK_CHANNEL15_8814B BIT(7) +#define BIT_TXDMAOK_CHANNEL14_8814B BIT(6) +#define BIT_TXDMAOK_CHANNEL3_8814B BIT(5) +#define BIT_TXDMAOK_CHANNEL2_8814B BIT(4) +#define BIT_TXDMAOK_CHANNEL1_8814B BIT(3) +#define BIT_TXDMAOK_CHANNEL0_8814B BIT(2) #define BIT_RDU_8814B BIT(1) #define BIT_RXOK_8814B BIT(0) /* 2 REG_HIMR1_8814B */ +#define BIT_PRE_TX_ERR_INT_MSK_8814B BIT(31) #define BIT_TXFIFO_TH_INT_8814B BIT(30) #define BIT_BTON_STS_UPDATE_MASK_8814B BIT(29) -#define BIT_MCU_ERR_MASK_8814B BIT(28) #define BIT_BCNDMAINT7__MSK_8814B BIT(27) #define BIT_BCNDMAINT6__MSK_8814B BIT(26) #define BIT_BCNDMAINT5__MSK_8814B BIT(25) @@ -1409,22 +1690,23 @@ #define BIT_BCNDERR3_MSK_8814B BIT(16) #define BIT_BCNDERR2_MSK_8814B BIT(15) #define BIT_BCNDERR1_MSK_8814B BIT(14) -#define BIT_ATIMEND_E_MSK_8814B BIT(13) #define BIT_ATIMEND__MSK_8814B BIT(12) #define BIT_TXERR_MSK_8814B BIT(11) #define BIT_RXERR_MSK_8814B BIT(10) #define BIT_TXFOVW_MSK_8814B BIT(9) #define BIT_FOVW_MSK_8814B BIT(8) +#define BIT_CPU_MGQ_EARLY_INT_MSK_8814B BIT(6) #define BIT_CPU_MGQ_TXDONE_MSK_8814B BIT(5) -#define BIT_PS_TIMER_C_MSK_8814B BIT(4) -#define BIT_PS_TIMER_B_MSK_8814B BIT(3) -#define BIT_PS_TIMER_A_MSK_8814B BIT(2) +#define BIT_PSTIMER_5_MSK_8814B BIT(4) +#define BIT_PSTIMER_4_MSK_8814B BIT(3) +#define BIT_PSTIMER_3_MSK_8814B BIT(2) #define BIT_CPUMGQ_TX_TIMER_MSK_8814B BIT(1) +#define BIT_BB_STOPRX_INT_MSK_8814B BIT(0) /* 2 REG_HISR1_8814B */ +#define BIT_PRE_TX_ERR_INT_8814B BIT(31) #define BIT_TXFIFO_TH_INT_8814B BIT(30) #define BIT_BTON_STS_UPDATE_INT_8814B BIT(29) -#define BIT_MCU_ERR_8814B BIT(28) #define BIT_BCNDMAINT7_8814B BIT(27) #define BIT_BCNDMAINT6_8814B BIT(26) #define BIT_BCNDMAINT5_8814B BIT(25) @@ -1439,7 +1721,6 @@ #define BIT_BCNDERR3_8814B BIT(16) #define BIT_BCNDERR2_8814B BIT(15) #define BIT_BCNDERR1_8814B BIT(14) -#define BIT_ATIMEND_E_8814B BIT(13) #define BIT_ATIMEND_8814B BIT(12) #define BIT_TXERR_INT_8814B BIT(11) #define BIT_RXERR_INT_8814B BIT(10) @@ -1447,38 +1728,60 @@ #define BIT_FOVW_8814B BIT(8) /* 2 REG_NOT_VALID_8814B */ +#define BIT_CPU_MGQ_EARLY_INT_8814B BIT(6) #define BIT_CPU_MGQ_TXDONE_8814B BIT(5) -#define BIT_PS_TIMER_C_8814B BIT(4) -#define BIT_PS_TIMER_B_8814B BIT(3) -#define BIT_PS_TIMER_A_8814B BIT(2) +#define BIT_PSTIMER_5_8814B BIT(4) +#define BIT_PSTIMER_4_8814B BIT(3) +#define BIT_PSTIMER_3_8814B BIT(2) #define BIT_CPUMGQ_TX_TIMER_8814B BIT(1) +#define BIT_BB_STOPRX_INT_8814B BIT(0) /* 2 REG_DBG_PORT_SEL_8814B */ #define BIT_SHIFT_DEBUG_ST_8814B 0 #define BIT_MASK_DEBUG_ST_8814B 0xffffffffL -#define BIT_DEBUG_ST_8814B(x) (((x) & BIT_MASK_DEBUG_ST_8814B) << BIT_SHIFT_DEBUG_ST_8814B) -#define BIT_GET_DEBUG_ST_8814B(x) (((x) >> BIT_SHIFT_DEBUG_ST_8814B) & BIT_MASK_DEBUG_ST_8814B) - - +#define BIT_DEBUG_ST_8814B(x) \ + (((x) & BIT_MASK_DEBUG_ST_8814B) << BIT_SHIFT_DEBUG_ST_8814B) +#define BITS_DEBUG_ST_8814B \ + (BIT_MASK_DEBUG_ST_8814B << BIT_SHIFT_DEBUG_ST_8814B) +#define BIT_CLEAR_DEBUG_ST_8814B(x) ((x) & (~BITS_DEBUG_ST_8814B)) +#define BIT_GET_DEBUG_ST_8814B(x) \ + (((x) >> BIT_SHIFT_DEBUG_ST_8814B) & BIT_MASK_DEBUG_ST_8814B) +#define BIT_SET_DEBUG_ST_8814B(x, v) \ + (BIT_CLEAR_DEBUG_ST_8814B(x) | BIT_DEBUG_ST_8814B(v)) /* 2 REG_PAD_CTRL2_8814B */ #define BIT_USB3_USB2_TRANSITION_8814B BIT(20) #define BIT_SHIFT_USB23_SW_MODE_V1_8814B 18 #define BIT_MASK_USB23_SW_MODE_V1_8814B 0x3 -#define BIT_USB23_SW_MODE_V1_8814B(x) (((x) & BIT_MASK_USB23_SW_MODE_V1_8814B) << BIT_SHIFT_USB23_SW_MODE_V1_8814B) -#define BIT_GET_USB23_SW_MODE_V1_8814B(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8814B) & BIT_MASK_USB23_SW_MODE_V1_8814B) - +#define BIT_USB23_SW_MODE_V1_8814B(x) \ + (((x) & BIT_MASK_USB23_SW_MODE_V1_8814B) \ + << BIT_SHIFT_USB23_SW_MODE_V1_8814B) +#define BITS_USB23_SW_MODE_V1_8814B \ + (BIT_MASK_USB23_SW_MODE_V1_8814B << BIT_SHIFT_USB23_SW_MODE_V1_8814B) +#define BIT_CLEAR_USB23_SW_MODE_V1_8814B(x) \ + ((x) & (~BITS_USB23_SW_MODE_V1_8814B)) +#define BIT_GET_USB23_SW_MODE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8814B) & \ + BIT_MASK_USB23_SW_MODE_V1_8814B) +#define BIT_SET_USB23_SW_MODE_V1_8814B(x, v) \ + (BIT_CLEAR_USB23_SW_MODE_V1_8814B(x) | BIT_USB23_SW_MODE_V1_8814B(v)) #define BIT_NO_PDN_CHIPOFF_V1_8814B BIT(17) #define BIT_RSM_EN_V1_8814B BIT(16) #define BIT_SHIFT_MATCH_CNT_8814B 8 #define BIT_MASK_MATCH_CNT_8814B 0xff -#define BIT_MATCH_CNT_8814B(x) (((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B) -#define BIT_GET_MATCH_CNT_8814B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B) - +#define BIT_MATCH_CNT_8814B(x) \ + (((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B) +#define BITS_MATCH_CNT_8814B \ + (BIT_MASK_MATCH_CNT_8814B << BIT_SHIFT_MATCH_CNT_8814B) +#define BIT_CLEAR_MATCH_CNT_8814B(x) ((x) & (~BITS_MATCH_CNT_8814B)) +#define BIT_GET_MATCH_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B) +#define BIT_SET_MATCH_CNT_8814B(x, v) \ + (BIT_CLEAR_MATCH_CNT_8814B(x) | BIT_MATCH_CNT_8814B(v)) #define BIT_LD_B12V_EN_8814B BIT(7) #define BIT_EECS_IOSEL_V1_8814B BIT(6) @@ -1494,9 +1797,17 @@ #define BIT_SHIFT_EFUSE_BURN_GNT_8814B 24 #define BIT_MASK_EFUSE_BURN_GNT_8814B 0xff -#define BIT_EFUSE_BURN_GNT_8814B(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8814B) << BIT_SHIFT_EFUSE_BURN_GNT_8814B) -#define BIT_GET_EFUSE_BURN_GNT_8814B(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8814B) & BIT_MASK_EFUSE_BURN_GNT_8814B) - +#define BIT_EFUSE_BURN_GNT_8814B(x) \ + (((x) & BIT_MASK_EFUSE_BURN_GNT_8814B) \ + << BIT_SHIFT_EFUSE_BURN_GNT_8814B) +#define BITS_EFUSE_BURN_GNT_8814B \ + (BIT_MASK_EFUSE_BURN_GNT_8814B << BIT_SHIFT_EFUSE_BURN_GNT_8814B) +#define BIT_CLEAR_EFUSE_BURN_GNT_8814B(x) ((x) & (~BITS_EFUSE_BURN_GNT_8814B)) +#define BIT_GET_EFUSE_BURN_GNT_8814B(x) \ + (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8814B) & \ + BIT_MASK_EFUSE_BURN_GNT_8814B) +#define BIT_SET_EFUSE_BURN_GNT_8814B(x, v) \ + (BIT_CLEAR_EFUSE_BURN_GNT_8814B(x) | BIT_EFUSE_BURN_GNT_8814B(v)) #define BIT_STOP_WL_PMC_8814B BIT(9) #define BIT_STOP_SYM_PMC_8814B BIT(8) @@ -1508,101 +1819,130 @@ #define BIT_SHIFT_SYSON_REG_ARB_8814B 0 #define BIT_MASK_SYSON_REG_ARB_8814B 0x3 -#define BIT_SYSON_REG_ARB_8814B(x) (((x) & BIT_MASK_SYSON_REG_ARB_8814B) << BIT_SHIFT_SYSON_REG_ARB_8814B) -#define BIT_GET_SYSON_REG_ARB_8814B(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8814B) & BIT_MASK_SYSON_REG_ARB_8814B) - - - -/* 2 REG_BIST_CTRL_8814B */ -#define BIT_BIST_USB_DIS_8814B BIT(27) -#define BIT_BIST_PCI_DIS_8814B BIT(26) -#define BIT_BIST_BT_DIS_8814B BIT(25) -#define BIT_BIST_WL_DIS_8814B BIT(24) - -#define BIT_SHIFT_BIST_RPT_SEL_8814B 16 -#define BIT_MASK_BIST_RPT_SEL_8814B 0xf -#define BIT_BIST_RPT_SEL_8814B(x) (((x) & BIT_MASK_BIST_RPT_SEL_8814B) << BIT_SHIFT_BIST_RPT_SEL_8814B) -#define BIT_GET_BIST_RPT_SEL_8814B(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8814B) & BIT_MASK_BIST_RPT_SEL_8814B) - - -#define BIT_BIST_RESUME_PS_8814B BIT(4) -#define BIT_BIST_RESUME_8814B BIT(3) -#define BIT_BIST_NORMAL_8814B BIT(2) -#define BIT_BIST_RSTN_8814B BIT(1) -#define BIT_BIST_CLK_EN_8814B BIT(0) - -/* 2 REG_BIST_RPT_8814B */ - -#define BIT_SHIFT_MBIST_REPORT_8814B 0 -#define BIT_MASK_MBIST_REPORT_8814B 0xffffffffL -#define BIT_MBIST_REPORT_8814B(x) (((x) & BIT_MASK_MBIST_REPORT_8814B) << BIT_SHIFT_MBIST_REPORT_8814B) -#define BIT_GET_MBIST_REPORT_8814B(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8814B) & BIT_MASK_MBIST_REPORT_8814B) +#define BIT_SYSON_REG_ARB_8814B(x) \ + (((x) & BIT_MASK_SYSON_REG_ARB_8814B) << BIT_SHIFT_SYSON_REG_ARB_8814B) +#define BITS_SYSON_REG_ARB_8814B \ + (BIT_MASK_SYSON_REG_ARB_8814B << BIT_SHIFT_SYSON_REG_ARB_8814B) +#define BIT_CLEAR_SYSON_REG_ARB_8814B(x) ((x) & (~BITS_SYSON_REG_ARB_8814B)) +#define BIT_GET_SYSON_REG_ARB_8814B(x) \ + (((x) >> BIT_SHIFT_SYSON_REG_ARB_8814B) & BIT_MASK_SYSON_REG_ARB_8814B) +#define BIT_SET_SYSON_REG_ARB_8814B(x, v) \ + (BIT_CLEAR_SYSON_REG_ARB_8814B(x) | BIT_SYSON_REG_ARB_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_MEM_CTRL_8814B */ #define BIT_UMEM_RME_8814B BIT(31) #define BIT_SHIFT_BT_SPRAM_8814B 28 #define BIT_MASK_BT_SPRAM_8814B 0x3 -#define BIT_BT_SPRAM_8814B(x) (((x) & BIT_MASK_BT_SPRAM_8814B) << BIT_SHIFT_BT_SPRAM_8814B) -#define BIT_GET_BT_SPRAM_8814B(x) (((x) >> BIT_SHIFT_BT_SPRAM_8814B) & BIT_MASK_BT_SPRAM_8814B) - - +#define BIT_BT_SPRAM_8814B(x) \ + (((x) & BIT_MASK_BT_SPRAM_8814B) << BIT_SHIFT_BT_SPRAM_8814B) +#define BITS_BT_SPRAM_8814B \ + (BIT_MASK_BT_SPRAM_8814B << BIT_SHIFT_BT_SPRAM_8814B) +#define BIT_CLEAR_BT_SPRAM_8814B(x) ((x) & (~BITS_BT_SPRAM_8814B)) +#define BIT_GET_BT_SPRAM_8814B(x) \ + (((x) >> BIT_SHIFT_BT_SPRAM_8814B) & BIT_MASK_BT_SPRAM_8814B) +#define BIT_SET_BT_SPRAM_8814B(x, v) \ + (BIT_CLEAR_BT_SPRAM_8814B(x) | BIT_BT_SPRAM_8814B(v)) #define BIT_SHIFT_BT_ROM_8814B 24 #define BIT_MASK_BT_ROM_8814B 0xf -#define BIT_BT_ROM_8814B(x) (((x) & BIT_MASK_BT_ROM_8814B) << BIT_SHIFT_BT_ROM_8814B) -#define BIT_GET_BT_ROM_8814B(x) (((x) >> BIT_SHIFT_BT_ROM_8814B) & BIT_MASK_BT_ROM_8814B) - - +#define BIT_BT_ROM_8814B(x) \ + (((x) & BIT_MASK_BT_ROM_8814B) << BIT_SHIFT_BT_ROM_8814B) +#define BITS_BT_ROM_8814B (BIT_MASK_BT_ROM_8814B << BIT_SHIFT_BT_ROM_8814B) +#define BIT_CLEAR_BT_ROM_8814B(x) ((x) & (~BITS_BT_ROM_8814B)) +#define BIT_GET_BT_ROM_8814B(x) \ + (((x) >> BIT_SHIFT_BT_ROM_8814B) & BIT_MASK_BT_ROM_8814B) +#define BIT_SET_BT_ROM_8814B(x, v) \ + (BIT_CLEAR_BT_ROM_8814B(x) | BIT_BT_ROM_8814B(v)) #define BIT_SHIFT_PCI_DPRAM_8814B 10 #define BIT_MASK_PCI_DPRAM_8814B 0x3 -#define BIT_PCI_DPRAM_8814B(x) (((x) & BIT_MASK_PCI_DPRAM_8814B) << BIT_SHIFT_PCI_DPRAM_8814B) -#define BIT_GET_PCI_DPRAM_8814B(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8814B) & BIT_MASK_PCI_DPRAM_8814B) - - +#define BIT_PCI_DPRAM_8814B(x) \ + (((x) & BIT_MASK_PCI_DPRAM_8814B) << BIT_SHIFT_PCI_DPRAM_8814B) +#define BITS_PCI_DPRAM_8814B \ + (BIT_MASK_PCI_DPRAM_8814B << BIT_SHIFT_PCI_DPRAM_8814B) +#define BIT_CLEAR_PCI_DPRAM_8814B(x) ((x) & (~BITS_PCI_DPRAM_8814B)) +#define BIT_GET_PCI_DPRAM_8814B(x) \ + (((x) >> BIT_SHIFT_PCI_DPRAM_8814B) & BIT_MASK_PCI_DPRAM_8814B) +#define BIT_SET_PCI_DPRAM_8814B(x, v) \ + (BIT_CLEAR_PCI_DPRAM_8814B(x) | BIT_PCI_DPRAM_8814B(v)) #define BIT_SHIFT_PCI_SPRAM_8814B 8 #define BIT_MASK_PCI_SPRAM_8814B 0x3 -#define BIT_PCI_SPRAM_8814B(x) (((x) & BIT_MASK_PCI_SPRAM_8814B) << BIT_SHIFT_PCI_SPRAM_8814B) -#define BIT_GET_PCI_SPRAM_8814B(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8814B) & BIT_MASK_PCI_SPRAM_8814B) - - +#define BIT_PCI_SPRAM_8814B(x) \ + (((x) & BIT_MASK_PCI_SPRAM_8814B) << BIT_SHIFT_PCI_SPRAM_8814B) +#define BITS_PCI_SPRAM_8814B \ + (BIT_MASK_PCI_SPRAM_8814B << BIT_SHIFT_PCI_SPRAM_8814B) +#define BIT_CLEAR_PCI_SPRAM_8814B(x) ((x) & (~BITS_PCI_SPRAM_8814B)) +#define BIT_GET_PCI_SPRAM_8814B(x) \ + (((x) >> BIT_SHIFT_PCI_SPRAM_8814B) & BIT_MASK_PCI_SPRAM_8814B) +#define BIT_SET_PCI_SPRAM_8814B(x, v) \ + (BIT_CLEAR_PCI_SPRAM_8814B(x) | BIT_PCI_SPRAM_8814B(v)) #define BIT_SHIFT_USB_SPRAM_8814B 6 #define BIT_MASK_USB_SPRAM_8814B 0x3 -#define BIT_USB_SPRAM_8814B(x) (((x) & BIT_MASK_USB_SPRAM_8814B) << BIT_SHIFT_USB_SPRAM_8814B) -#define BIT_GET_USB_SPRAM_8814B(x) (((x) >> BIT_SHIFT_USB_SPRAM_8814B) & BIT_MASK_USB_SPRAM_8814B) - - +#define BIT_USB_SPRAM_8814B(x) \ + (((x) & BIT_MASK_USB_SPRAM_8814B) << BIT_SHIFT_USB_SPRAM_8814B) +#define BITS_USB_SPRAM_8814B \ + (BIT_MASK_USB_SPRAM_8814B << BIT_SHIFT_USB_SPRAM_8814B) +#define BIT_CLEAR_USB_SPRAM_8814B(x) ((x) & (~BITS_USB_SPRAM_8814B)) +#define BIT_GET_USB_SPRAM_8814B(x) \ + (((x) >> BIT_SHIFT_USB_SPRAM_8814B) & BIT_MASK_USB_SPRAM_8814B) +#define BIT_SET_USB_SPRAM_8814B(x, v) \ + (BIT_CLEAR_USB_SPRAM_8814B(x) | BIT_USB_SPRAM_8814B(v)) #define BIT_SHIFT_USB_SPRF_8814B 4 #define BIT_MASK_USB_SPRF_8814B 0x3 -#define BIT_USB_SPRF_8814B(x) (((x) & BIT_MASK_USB_SPRF_8814B) << BIT_SHIFT_USB_SPRF_8814B) -#define BIT_GET_USB_SPRF_8814B(x) (((x) >> BIT_SHIFT_USB_SPRF_8814B) & BIT_MASK_USB_SPRF_8814B) - - +#define BIT_USB_SPRF_8814B(x) \ + (((x) & BIT_MASK_USB_SPRF_8814B) << BIT_SHIFT_USB_SPRF_8814B) +#define BITS_USB_SPRF_8814B \ + (BIT_MASK_USB_SPRF_8814B << BIT_SHIFT_USB_SPRF_8814B) +#define BIT_CLEAR_USB_SPRF_8814B(x) ((x) & (~BITS_USB_SPRF_8814B)) +#define BIT_GET_USB_SPRF_8814B(x) \ + (((x) >> BIT_SHIFT_USB_SPRF_8814B) & BIT_MASK_USB_SPRF_8814B) +#define BIT_SET_USB_SPRF_8814B(x, v) \ + (BIT_CLEAR_USB_SPRF_8814B(x) | BIT_USB_SPRF_8814B(v)) #define BIT_SHIFT_MCU_ROM_8814B 0 #define BIT_MASK_MCU_ROM_8814B 0xf -#define BIT_MCU_ROM_8814B(x) (((x) & BIT_MASK_MCU_ROM_8814B) << BIT_SHIFT_MCU_ROM_8814B) -#define BIT_GET_MCU_ROM_8814B(x) (((x) >> BIT_SHIFT_MCU_ROM_8814B) & BIT_MASK_MCU_ROM_8814B) - - - -/* 2 REG_AFE_CTRL8_8814B */ -#define BIT_SYN_AGPIO_8814B BIT(20) -#define BIT_XTAL_LP_8814B BIT(4) -#define BIT_XTAL_GM_SEP_8814B BIT(3) - -#define BIT_SHIFT_XTAL_SEL_TOK_8814B 0 -#define BIT_MASK_XTAL_SEL_TOK_8814B 0x7 -#define BIT_XTAL_SEL_TOK_8814B(x) (((x) & BIT_MASK_XTAL_SEL_TOK_8814B) << BIT_SHIFT_XTAL_SEL_TOK_8814B) -#define BIT_GET_XTAL_SEL_TOK_8814B(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8814B) & BIT_MASK_XTAL_SEL_TOK_8814B) - - +#define BIT_MCU_ROM_8814B(x) \ + (((x) & BIT_MASK_MCU_ROM_8814B) << BIT_SHIFT_MCU_ROM_8814B) +#define BITS_MCU_ROM_8814B (BIT_MASK_MCU_ROM_8814B << BIT_SHIFT_MCU_ROM_8814B) +#define BIT_CLEAR_MCU_ROM_8814B(x) ((x) & (~BITS_MCU_ROM_8814B)) +#define BIT_GET_MCU_ROM_8814B(x) \ + (((x) >> BIT_SHIFT_MCU_ROM_8814B) & BIT_MASK_MCU_ROM_8814B) +#define BIT_SET_MCU_ROM_8814B(x, v) \ + (BIT_CLEAR_MCU_ROM_8814B(x) | BIT_MCU_ROM_8814B(v)) + +/* 2 REG_SYN_RFC_CTRL_8814B */ + +#define BIT_SHIFT_SYN_RF1_CTRL_8814B 8 +#define BIT_MASK_SYN_RF1_CTRL_8814B 0xff +#define BIT_SYN_RF1_CTRL_8814B(x) \ + (((x) & BIT_MASK_SYN_RF1_CTRL_8814B) << BIT_SHIFT_SYN_RF1_CTRL_8814B) +#define BITS_SYN_RF1_CTRL_8814B \ + (BIT_MASK_SYN_RF1_CTRL_8814B << BIT_SHIFT_SYN_RF1_CTRL_8814B) +#define BIT_CLEAR_SYN_RF1_CTRL_8814B(x) ((x) & (~BITS_SYN_RF1_CTRL_8814B)) +#define BIT_GET_SYN_RF1_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_SYN_RF1_CTRL_8814B) & BIT_MASK_SYN_RF1_CTRL_8814B) +#define BIT_SET_SYN_RF1_CTRL_8814B(x, v) \ + (BIT_CLEAR_SYN_RF1_CTRL_8814B(x) | BIT_SYN_RF1_CTRL_8814B(v)) + +#define BIT_SHIFT_SYN_RF0_CTRL_8814B 0 +#define BIT_MASK_SYN_RF0_CTRL_8814B 0xff +#define BIT_SYN_RF0_CTRL_8814B(x) \ + (((x) & BIT_MASK_SYN_RF0_CTRL_8814B) << BIT_SHIFT_SYN_RF0_CTRL_8814B) +#define BITS_SYN_RF0_CTRL_8814B \ + (BIT_MASK_SYN_RF0_CTRL_8814B << BIT_SHIFT_SYN_RF0_CTRL_8814B) +#define BIT_CLEAR_SYN_RF0_CTRL_8814B(x) ((x) & (~BITS_SYN_RF0_CTRL_8814B)) +#define BIT_GET_SYN_RF0_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_SYN_RF0_CTRL_8814B) & BIT_MASK_SYN_RF0_CTRL_8814B) +#define BIT_SET_SYN_RF0_CTRL_8814B(x, v) \ + (BIT_CLEAR_SYN_RF0_CTRL_8814B(x) | BIT_SYN_RF0_CTRL_8814B(v)) /* 2 REG_USB_SIE_INTF_8814B */ #define BIT_RD_SEL_8814B BIT(31) @@ -1612,68 +1952,160 @@ #define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B 16 #define BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B 0x1ff -#define BIT_USB_SIE_INTF_ADDR_V1_8814B(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) -#define BIT_GET_USB_SIE_INTF_ADDR_V1_8814B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B) - - +#define BIT_USB_SIE_INTF_ADDR_V1_8814B(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B) \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) +#define BITS_USB_SIE_INTF_ADDR_V1_8814B \ + (BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) +#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8814B(x) \ + ((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8814B)) +#define BIT_GET_USB_SIE_INTF_ADDR_V1_8814B(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) & \ + BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B) +#define BIT_SET_USB_SIE_INTF_ADDR_V1_8814B(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8814B(x) | \ + BIT_USB_SIE_INTF_ADDR_V1_8814B(v)) #define BIT_SHIFT_USB_SIE_INTF_RD_8814B 8 #define BIT_MASK_USB_SIE_INTF_RD_8814B 0xff -#define BIT_USB_SIE_INTF_RD_8814B(x) (((x) & BIT_MASK_USB_SIE_INTF_RD_8814B) << BIT_SHIFT_USB_SIE_INTF_RD_8814B) -#define BIT_GET_USB_SIE_INTF_RD_8814B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8814B) & BIT_MASK_USB_SIE_INTF_RD_8814B) - - +#define BIT_USB_SIE_INTF_RD_8814B(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_RD_8814B) \ + << BIT_SHIFT_USB_SIE_INTF_RD_8814B) +#define BITS_USB_SIE_INTF_RD_8814B \ + (BIT_MASK_USB_SIE_INTF_RD_8814B << BIT_SHIFT_USB_SIE_INTF_RD_8814B) +#define BIT_CLEAR_USB_SIE_INTF_RD_8814B(x) ((x) & (~BITS_USB_SIE_INTF_RD_8814B)) +#define BIT_GET_USB_SIE_INTF_RD_8814B(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8814B) & \ + BIT_MASK_USB_SIE_INTF_RD_8814B) +#define BIT_SET_USB_SIE_INTF_RD_8814B(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_RD_8814B(x) | BIT_USB_SIE_INTF_RD_8814B(v)) #define BIT_SHIFT_USB_SIE_INTF_WD_8814B 0 #define BIT_MASK_USB_SIE_INTF_WD_8814B 0xff -#define BIT_USB_SIE_INTF_WD_8814B(x) (((x) & BIT_MASK_USB_SIE_INTF_WD_8814B) << BIT_SHIFT_USB_SIE_INTF_WD_8814B) -#define BIT_GET_USB_SIE_INTF_WD_8814B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8814B) & BIT_MASK_USB_SIE_INTF_WD_8814B) +#define BIT_USB_SIE_INTF_WD_8814B(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_WD_8814B) \ + << BIT_SHIFT_USB_SIE_INTF_WD_8814B) +#define BITS_USB_SIE_INTF_WD_8814B \ + (BIT_MASK_USB_SIE_INTF_WD_8814B << BIT_SHIFT_USB_SIE_INTF_WD_8814B) +#define BIT_CLEAR_USB_SIE_INTF_WD_8814B(x) ((x) & (~BITS_USB_SIE_INTF_WD_8814B)) +#define BIT_GET_USB_SIE_INTF_WD_8814B(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8814B) & \ + BIT_MASK_USB_SIE_INTF_WD_8814B) +#define BIT_SET_USB_SIE_INTF_WD_8814B(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_WD_8814B(x) | BIT_USB_SIE_INTF_WD_8814B(v)) +/* 2 REG_PCIE_MIO_INTF_8814B */ +#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B 16 +#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B 0x3 +#define BIT_PCIE_MIO_ADDR_PAGE_8814B(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B) \ + << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B) +#define BITS_PCIE_MIO_ADDR_PAGE_8814B \ + (BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B \ + << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B) +#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8814B(x) \ + ((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8814B)) +#define BIT_GET_PCIE_MIO_ADDR_PAGE_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B) & \ + BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B) +#define BIT_SET_PCIE_MIO_ADDR_PAGE_8814B(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8814B(x) | \ + BIT_PCIE_MIO_ADDR_PAGE_8814B(v)) -/* 2 REG_PCIE_MIO_INTF_8814B */ #define BIT_PCIE_MIO_BYIOREG_8814B BIT(13) #define BIT_PCIE_MIO_RE_8814B BIT(12) #define BIT_SHIFT_PCIE_MIO_WE_8814B 8 #define BIT_MASK_PCIE_MIO_WE_8814B 0xf -#define BIT_PCIE_MIO_WE_8814B(x) (((x) & BIT_MASK_PCIE_MIO_WE_8814B) << BIT_SHIFT_PCIE_MIO_WE_8814B) -#define BIT_GET_PCIE_MIO_WE_8814B(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8814B) & BIT_MASK_PCIE_MIO_WE_8814B) - - +#define BIT_PCIE_MIO_WE_8814B(x) \ + (((x) & BIT_MASK_PCIE_MIO_WE_8814B) << BIT_SHIFT_PCIE_MIO_WE_8814B) +#define BITS_PCIE_MIO_WE_8814B \ + (BIT_MASK_PCIE_MIO_WE_8814B << BIT_SHIFT_PCIE_MIO_WE_8814B) +#define BIT_CLEAR_PCIE_MIO_WE_8814B(x) ((x) & (~BITS_PCIE_MIO_WE_8814B)) +#define BIT_GET_PCIE_MIO_WE_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_WE_8814B) & BIT_MASK_PCIE_MIO_WE_8814B) +#define BIT_SET_PCIE_MIO_WE_8814B(x, v) \ + (BIT_CLEAR_PCIE_MIO_WE_8814B(x) | BIT_PCIE_MIO_WE_8814B(v)) #define BIT_SHIFT_PCIE_MIO_ADDR_8814B 0 #define BIT_MASK_PCIE_MIO_ADDR_8814B 0xff -#define BIT_PCIE_MIO_ADDR_8814B(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8814B) << BIT_SHIFT_PCIE_MIO_ADDR_8814B) -#define BIT_GET_PCIE_MIO_ADDR_8814B(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8814B) & BIT_MASK_PCIE_MIO_ADDR_8814B) - - +#define BIT_PCIE_MIO_ADDR_8814B(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_8814B) << BIT_SHIFT_PCIE_MIO_ADDR_8814B) +#define BITS_PCIE_MIO_ADDR_8814B \ + (BIT_MASK_PCIE_MIO_ADDR_8814B << BIT_SHIFT_PCIE_MIO_ADDR_8814B) +#define BIT_CLEAR_PCIE_MIO_ADDR_8814B(x) ((x) & (~BITS_PCIE_MIO_ADDR_8814B)) +#define BIT_GET_PCIE_MIO_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8814B) & BIT_MASK_PCIE_MIO_ADDR_8814B) +#define BIT_SET_PCIE_MIO_ADDR_8814B(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_8814B(x) | BIT_PCIE_MIO_ADDR_8814B(v)) /* 2 REG_PCIE_MIO_INTD_8814B */ #define BIT_SHIFT_PCIE_MIO_DATA_8814B 0 #define BIT_MASK_PCIE_MIO_DATA_8814B 0xffffffffL -#define BIT_PCIE_MIO_DATA_8814B(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8814B) << BIT_SHIFT_PCIE_MIO_DATA_8814B) -#define BIT_GET_PCIE_MIO_DATA_8814B(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8814B) & BIT_MASK_PCIE_MIO_DATA_8814B) - - +#define BIT_PCIE_MIO_DATA_8814B(x) \ + (((x) & BIT_MASK_PCIE_MIO_DATA_8814B) << BIT_SHIFT_PCIE_MIO_DATA_8814B) +#define BITS_PCIE_MIO_DATA_8814B \ + (BIT_MASK_PCIE_MIO_DATA_8814B << BIT_SHIFT_PCIE_MIO_DATA_8814B) +#define BIT_CLEAR_PCIE_MIO_DATA_8814B(x) ((x) & (~BITS_PCIE_MIO_DATA_8814B)) +#define BIT_GET_PCIE_MIO_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8814B) & BIT_MASK_PCIE_MIO_DATA_8814B) +#define BIT_SET_PCIE_MIO_DATA_8814B(x, v) \ + (BIT_CLEAR_PCIE_MIO_DATA_8814B(x) | BIT_PCIE_MIO_DATA_8814B(v)) /* 2 REG_WLRF1_8814B */ #define BIT_SHIFT_WLRF1_CTRL_8814B 24 #define BIT_MASK_WLRF1_CTRL_8814B 0xff -#define BIT_WLRF1_CTRL_8814B(x) (((x) & BIT_MASK_WLRF1_CTRL_8814B) << BIT_SHIFT_WLRF1_CTRL_8814B) -#define BIT_GET_WLRF1_CTRL_8814B(x) (((x) >> BIT_SHIFT_WLRF1_CTRL_8814B) & BIT_MASK_WLRF1_CTRL_8814B) - - +#define BIT_WLRF1_CTRL_8814B(x) \ + (((x) & BIT_MASK_WLRF1_CTRL_8814B) << BIT_SHIFT_WLRF1_CTRL_8814B) +#define BITS_WLRF1_CTRL_8814B \ + (BIT_MASK_WLRF1_CTRL_8814B << BIT_SHIFT_WLRF1_CTRL_8814B) +#define BIT_CLEAR_WLRF1_CTRL_8814B(x) ((x) & (~BITS_WLRF1_CTRL_8814B)) +#define BIT_GET_WLRF1_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_WLRF1_CTRL_8814B) & BIT_MASK_WLRF1_CTRL_8814B) +#define BIT_SET_WLRF1_CTRL_8814B(x, v) \ + (BIT_CLEAR_WLRF1_CTRL_8814B(x) | BIT_WLRF1_CTRL_8814B(v)) + +#define BIT_SHIFT_WLRF2_CTRL_8814B 16 +#define BIT_MASK_WLRF2_CTRL_8814B 0xff +#define BIT_WLRF2_CTRL_8814B(x) \ + (((x) & BIT_MASK_WLRF2_CTRL_8814B) << BIT_SHIFT_WLRF2_CTRL_8814B) +#define BITS_WLRF2_CTRL_8814B \ + (BIT_MASK_WLRF2_CTRL_8814B << BIT_SHIFT_WLRF2_CTRL_8814B) +#define BIT_CLEAR_WLRF2_CTRL_8814B(x) ((x) & (~BITS_WLRF2_CTRL_8814B)) +#define BIT_GET_WLRF2_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_WLRF2_CTRL_8814B) & BIT_MASK_WLRF2_CTRL_8814B) +#define BIT_SET_WLRF2_CTRL_8814B(x, v) \ + (BIT_CLEAR_WLRF2_CTRL_8814B(x) | BIT_WLRF2_CTRL_8814B(v)) + +#define BIT_SHIFT_WLRF3_CTRL_8814B 8 +#define BIT_MASK_WLRF3_CTRL_8814B 0xff +#define BIT_WLRF3_CTRL_8814B(x) \ + (((x) & BIT_MASK_WLRF3_CTRL_8814B) << BIT_SHIFT_WLRF3_CTRL_8814B) +#define BITS_WLRF3_CTRL_8814B \ + (BIT_MASK_WLRF3_CTRL_8814B << BIT_SHIFT_WLRF3_CTRL_8814B) +#define BIT_CLEAR_WLRF3_CTRL_8814B(x) ((x) & (~BITS_WLRF3_CTRL_8814B)) +#define BIT_GET_WLRF3_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_WLRF3_CTRL_8814B) & BIT_MASK_WLRF3_CTRL_8814B) +#define BIT_SET_WLRF3_CTRL_8814B(x, v) \ + (BIT_CLEAR_WLRF3_CTRL_8814B(x) | BIT_WLRF3_CTRL_8814B(v)) /* 2 REG_SYS_CFG1_8814B */ #define BIT_SHIFT_TRP_ICFG_8814B 28 #define BIT_MASK_TRP_ICFG_8814B 0xf -#define BIT_TRP_ICFG_8814B(x) (((x) & BIT_MASK_TRP_ICFG_8814B) << BIT_SHIFT_TRP_ICFG_8814B) -#define BIT_GET_TRP_ICFG_8814B(x) (((x) >> BIT_SHIFT_TRP_ICFG_8814B) & BIT_MASK_TRP_ICFG_8814B) - +#define BIT_TRP_ICFG_8814B(x) \ + (((x) & BIT_MASK_TRP_ICFG_8814B) << BIT_SHIFT_TRP_ICFG_8814B) +#define BITS_TRP_ICFG_8814B \ + (BIT_MASK_TRP_ICFG_8814B << BIT_SHIFT_TRP_ICFG_8814B) +#define BIT_CLEAR_TRP_ICFG_8814B(x) ((x) & (~BITS_TRP_ICFG_8814B)) +#define BIT_GET_TRP_ICFG_8814B(x) \ + (((x) >> BIT_SHIFT_TRP_ICFG_8814B) & BIT_MASK_TRP_ICFG_8814B) +#define BIT_SET_TRP_ICFG_8814B(x, v) \ + (BIT_CLEAR_TRP_ICFG_8814B(x) | BIT_TRP_ICFG_8814B(v)) #define BIT_RF_TYPE_ID_8814B BIT(27) #define BIT_BD_HCI_SEL_8814B BIT(26) @@ -1685,16 +2117,27 @@ #define BIT_SHIFT_VENDOR_ID_8814B 16 #define BIT_MASK_VENDOR_ID_8814B 0xf -#define BIT_VENDOR_ID_8814B(x) (((x) & BIT_MASK_VENDOR_ID_8814B) << BIT_SHIFT_VENDOR_ID_8814B) -#define BIT_GET_VENDOR_ID_8814B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8814B) & BIT_MASK_VENDOR_ID_8814B) - - +#define BIT_VENDOR_ID_8814B(x) \ + (((x) & BIT_MASK_VENDOR_ID_8814B) << BIT_SHIFT_VENDOR_ID_8814B) +#define BITS_VENDOR_ID_8814B \ + (BIT_MASK_VENDOR_ID_8814B << BIT_SHIFT_VENDOR_ID_8814B) +#define BIT_CLEAR_VENDOR_ID_8814B(x) ((x) & (~BITS_VENDOR_ID_8814B)) +#define BIT_GET_VENDOR_ID_8814B(x) \ + (((x) >> BIT_SHIFT_VENDOR_ID_8814B) & BIT_MASK_VENDOR_ID_8814B) +#define BIT_SET_VENDOR_ID_8814B(x, v) \ + (BIT_CLEAR_VENDOR_ID_8814B(x) | BIT_VENDOR_ID_8814B(v)) #define BIT_SHIFT_CHIP_VER_8814B 12 #define BIT_MASK_CHIP_VER_8814B 0xf -#define BIT_CHIP_VER_8814B(x) (((x) & BIT_MASK_CHIP_VER_8814B) << BIT_SHIFT_CHIP_VER_8814B) -#define BIT_GET_CHIP_VER_8814B(x) (((x) >> BIT_SHIFT_CHIP_VER_8814B) & BIT_MASK_CHIP_VER_8814B) - +#define BIT_CHIP_VER_8814B(x) \ + (((x) & BIT_MASK_CHIP_VER_8814B) << BIT_SHIFT_CHIP_VER_8814B) +#define BITS_CHIP_VER_8814B \ + (BIT_MASK_CHIP_VER_8814B << BIT_SHIFT_CHIP_VER_8814B) +#define BIT_CLEAR_CHIP_VER_8814B(x) ((x) & (~BITS_CHIP_VER_8814B)) +#define BIT_GET_CHIP_VER_8814B(x) \ + (((x) >> BIT_SHIFT_CHIP_VER_8814B) & BIT_MASK_CHIP_VER_8814B) +#define BIT_SET_CHIP_VER_8814B(x, v) \ + (BIT_CLEAR_CHIP_VER_8814B(x) | BIT_CHIP_VER_8814B(v)) #define BIT_BD_MAC3_8814B BIT(11) #define BIT_BD_MAC1_8814B BIT(10) @@ -1713,17 +2156,55 @@ #define BIT_SHIFT_RF_RL_ID_8814B 28 #define BIT_MASK_RF_RL_ID_8814B 0xf -#define BIT_RF_RL_ID_8814B(x) (((x) & BIT_MASK_RF_RL_ID_8814B) << BIT_SHIFT_RF_RL_ID_8814B) -#define BIT_GET_RF_RL_ID_8814B(x) (((x) >> BIT_SHIFT_RF_RL_ID_8814B) & BIT_MASK_RF_RL_ID_8814B) +#define BIT_RF_RL_ID_8814B(x) \ + (((x) & BIT_MASK_RF_RL_ID_8814B) << BIT_SHIFT_RF_RL_ID_8814B) +#define BITS_RF_RL_ID_8814B \ + (BIT_MASK_RF_RL_ID_8814B << BIT_SHIFT_RF_RL_ID_8814B) +#define BIT_CLEAR_RF_RL_ID_8814B(x) ((x) & (~BITS_RF_RL_ID_8814B)) +#define BIT_GET_RF_RL_ID_8814B(x) \ + (((x) >> BIT_SHIFT_RF_RL_ID_8814B) & BIT_MASK_RF_RL_ID_8814B) +#define BIT_SET_RF_RL_ID_8814B(x, v) \ + (BIT_CLEAR_RF_RL_ID_8814B(x) | BIT_RF_RL_ID_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_XTAL_SEL_8814B 25 +#define BIT_MASK_XTAL_SEL_8814B 0x3 +#define BIT_XTAL_SEL_8814B(x) \ + (((x) & BIT_MASK_XTAL_SEL_8814B) << BIT_SHIFT_XTAL_SEL_8814B) +#define BITS_XTAL_SEL_8814B \ + (BIT_MASK_XTAL_SEL_8814B << BIT_SHIFT_XTAL_SEL_8814B) +#define BIT_CLEAR_XTAL_SEL_8814B(x) ((x) & (~BITS_XTAL_SEL_8814B)) +#define BIT_GET_XTAL_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_8814B) & BIT_MASK_XTAL_SEL_8814B) +#define BIT_SET_XTAL_SEL_8814B(x, v) \ + (BIT_CLEAR_XTAL_SEL_8814B(x) | BIT_XTAL_SEL_8814B(v)) #define BIT_HPHY_ICFG_8814B BIT(19) #define BIT_SHIFT_SEL_0XC0_8814B 16 #define BIT_MASK_SEL_0XC0_8814B 0x3 -#define BIT_SEL_0XC0_8814B(x) (((x) & BIT_MASK_SEL_0XC0_8814B) << BIT_SHIFT_SEL_0XC0_8814B) -#define BIT_GET_SEL_0XC0_8814B(x) (((x) >> BIT_SHIFT_SEL_0XC0_8814B) & BIT_MASK_SEL_0XC0_8814B) - +#define BIT_SEL_0XC0_8814B(x) \ + (((x) & BIT_MASK_SEL_0XC0_8814B) << BIT_SHIFT_SEL_0XC0_8814B) +#define BITS_SEL_0XC0_8814B \ + (BIT_MASK_SEL_0XC0_8814B << BIT_SHIFT_SEL_0XC0_8814B) +#define BIT_CLEAR_SEL_0XC0_8814B(x) ((x) & (~BITS_SEL_0XC0_8814B)) +#define BIT_GET_SEL_0XC0_8814B(x) \ + (((x) >> BIT_SHIFT_SEL_0XC0_8814B) & BIT_MASK_SEL_0XC0_8814B) +#define BIT_SET_SEL_0XC0_8814B(x, v) \ + (BIT_CLEAR_SEL_0XC0_8814B(x) | BIT_SEL_0XC0_8814B(v)) + +#define BIT_SHIFT_HCI_SEL_V4_8814B 12 +#define BIT_MASK_HCI_SEL_V4_8814B 0x3 +#define BIT_HCI_SEL_V4_8814B(x) \ + (((x) & BIT_MASK_HCI_SEL_V4_8814B) << BIT_SHIFT_HCI_SEL_V4_8814B) +#define BITS_HCI_SEL_V4_8814B \ + (BIT_MASK_HCI_SEL_V4_8814B << BIT_SHIFT_HCI_SEL_V4_8814B) +#define BIT_CLEAR_HCI_SEL_V4_8814B(x) ((x) & (~BITS_HCI_SEL_V4_8814B)) +#define BIT_GET_HCI_SEL_V4_8814B(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V4_8814B) & BIT_MASK_HCI_SEL_V4_8814B) +#define BIT_SET_HCI_SEL_V4_8814B(x, v) \ + (BIT_CLEAR_HCI_SEL_V4_8814B(x) | BIT_HCI_SEL_V4_8814B(v)) #define BIT_USB_OPERATION_MODE_8814B BIT(10) #define BIT_BT_PDN_8814B BIT(9) @@ -1731,26 +2212,31 @@ #define BIT_WL_MODE_8814B BIT(7) #define BIT_PKG_SEL_HCI_8814B BIT(6) -#define BIT_SHIFT_HCI_SEL_8814B 4 -#define BIT_MASK_HCI_SEL_8814B 0x3 -#define BIT_HCI_SEL_8814B(x) (((x) & BIT_MASK_HCI_SEL_8814B) << BIT_SHIFT_HCI_SEL_8814B) -#define BIT_GET_HCI_SEL_8814B(x) (((x) >> BIT_SHIFT_HCI_SEL_8814B) & BIT_MASK_HCI_SEL_8814B) - - - -#define BIT_SHIFT_PAD_HCI_SEL_8814B 2 -#define BIT_MASK_PAD_HCI_SEL_8814B 0x3 -#define BIT_PAD_HCI_SEL_8814B(x) (((x) & BIT_MASK_PAD_HCI_SEL_8814B) << BIT_SHIFT_PAD_HCI_SEL_8814B) -#define BIT_GET_PAD_HCI_SEL_8814B(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_8814B) & BIT_MASK_PAD_HCI_SEL_8814B) - - +#define BIT_SHIFT_PAD_HCI_SEL_V2_8814B 3 +#define BIT_MASK_PAD_HCI_SEL_V2_8814B 0x3 +#define BIT_PAD_HCI_SEL_V2_8814B(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_V2_8814B) \ + << BIT_SHIFT_PAD_HCI_SEL_V2_8814B) +#define BITS_PAD_HCI_SEL_V2_8814B \ + (BIT_MASK_PAD_HCI_SEL_V2_8814B << BIT_SHIFT_PAD_HCI_SEL_V2_8814B) +#define BIT_CLEAR_PAD_HCI_SEL_V2_8814B(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8814B)) +#define BIT_GET_PAD_HCI_SEL_V2_8814B(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8814B) & \ + BIT_MASK_PAD_HCI_SEL_V2_8814B) +#define BIT_SET_PAD_HCI_SEL_V2_8814B(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_V2_8814B(x) | BIT_PAD_HCI_SEL_V2_8814B(v)) #define BIT_SHIFT_EFS_HCI_SEL_8814B 0 #define BIT_MASK_EFS_HCI_SEL_8814B 0x3 -#define BIT_EFS_HCI_SEL_8814B(x) (((x) & BIT_MASK_EFS_HCI_SEL_8814B) << BIT_SHIFT_EFS_HCI_SEL_8814B) -#define BIT_GET_EFS_HCI_SEL_8814B(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_8814B) & BIT_MASK_EFS_HCI_SEL_8814B) - - +#define BIT_EFS_HCI_SEL_8814B(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL_8814B) << BIT_SHIFT_EFS_HCI_SEL_8814B) +#define BITS_EFS_HCI_SEL_8814B \ + (BIT_MASK_EFS_HCI_SEL_8814B << BIT_SHIFT_EFS_HCI_SEL_8814B) +#define BIT_CLEAR_EFS_HCI_SEL_8814B(x) ((x) & (~BITS_EFS_HCI_SEL_8814B)) +#define BIT_GET_EFS_HCI_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL_8814B) & BIT_MASK_EFS_HCI_SEL_8814B) +#define BIT_SET_EFS_HCI_SEL_8814B(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL_8814B(x) | BIT_EFS_HCI_SEL_8814B(v)) /* 2 REG_SYS_STATUS2_8814B */ #define BIT_SIO_ALDN_8814B BIT(19) @@ -1760,38 +2246,1214 @@ #define BIT_SHIFT_EPVID1_8814B 8 #define BIT_MASK_EPVID1_8814B 0xff -#define BIT_EPVID1_8814B(x) (((x) & BIT_MASK_EPVID1_8814B) << BIT_SHIFT_EPVID1_8814B) -#define BIT_GET_EPVID1_8814B(x) (((x) >> BIT_SHIFT_EPVID1_8814B) & BIT_MASK_EPVID1_8814B) - - +#define BIT_EPVID1_8814B(x) \ + (((x) & BIT_MASK_EPVID1_8814B) << BIT_SHIFT_EPVID1_8814B) +#define BITS_EPVID1_8814B (BIT_MASK_EPVID1_8814B << BIT_SHIFT_EPVID1_8814B) +#define BIT_CLEAR_EPVID1_8814B(x) ((x) & (~BITS_EPVID1_8814B)) +#define BIT_GET_EPVID1_8814B(x) \ + (((x) >> BIT_SHIFT_EPVID1_8814B) & BIT_MASK_EPVID1_8814B) +#define BIT_SET_EPVID1_8814B(x, v) \ + (BIT_CLEAR_EPVID1_8814B(x) | BIT_EPVID1_8814B(v)) #define BIT_SHIFT_EPVID0_8814B 0 #define BIT_MASK_EPVID0_8814B 0xff -#define BIT_EPVID0_8814B(x) (((x) & BIT_MASK_EPVID0_8814B) << BIT_SHIFT_EPVID0_8814B) -#define BIT_GET_EPVID0_8814B(x) (((x) >> BIT_SHIFT_EPVID0_8814B) & BIT_MASK_EPVID0_8814B) - - +#define BIT_EPVID0_8814B(x) \ + (((x) & BIT_MASK_EPVID0_8814B) << BIT_SHIFT_EPVID0_8814B) +#define BITS_EPVID0_8814B (BIT_MASK_EPVID0_8814B << BIT_SHIFT_EPVID0_8814B) +#define BIT_CLEAR_EPVID0_8814B(x) ((x) & (~BITS_EPVID0_8814B)) +#define BIT_GET_EPVID0_8814B(x) \ + (((x) >> BIT_SHIFT_EPVID0_8814B) & BIT_MASK_EPVID0_8814B) +#define BIT_SET_EPVID0_8814B(x, v) \ + (BIT_CLEAR_EPVID0_8814B(x) | BIT_EPVID0_8814B(v)) /* 2 REG_SYS_CFG2_8814B */ -#define BIT_HCI_SEL_EMBEDED_8814B BIT(8) +#define BIT_USB2_SEL_8814B BIT(31) +#define BIT_U3PHY_RST_V1_8814B BIT(30) +#define BIT_U3_TERM_DETECT_8814B BIT(29) #define BIT_SHIFT_HW_ID_8814B 0 #define BIT_MASK_HW_ID_8814B 0xff -#define BIT_HW_ID_8814B(x) (((x) & BIT_MASK_HW_ID_8814B) << BIT_SHIFT_HW_ID_8814B) -#define BIT_GET_HW_ID_8814B(x) (((x) >> BIT_SHIFT_HW_ID_8814B) & BIT_MASK_HW_ID_8814B) - - +#define BIT_HW_ID_8814B(x) \ + (((x) & BIT_MASK_HW_ID_8814B) << BIT_SHIFT_HW_ID_8814B) +#define BITS_HW_ID_8814B (BIT_MASK_HW_ID_8814B << BIT_SHIFT_HW_ID_8814B) +#define BIT_CLEAR_HW_ID_8814B(x) ((x) & (~BITS_HW_ID_8814B)) +#define BIT_GET_HW_ID_8814B(x) \ + (((x) >> BIT_SHIFT_HW_ID_8814B) & BIT_MASK_HW_ID_8814B) +#define BIT_SET_HW_ID_8814B(x, v) \ + (BIT_CLEAR_HW_ID_8814B(x) | BIT_HW_ID_8814B(v)) -/* 2 REG_SYS_CFG3_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_FEN_WLMAC_OFF_8814B BIT(31) #define BIT_PWC_MA33V_8814B BIT(15) #define BIT_PWC_MA12V_8814B BIT(14) #define BIT_PWC_MD12V_8814B BIT(13) #define BIT_PWC_PD12V_8814B BIT(12) #define BIT_PWC_UD12V_8814B BIT(11) +#define BIT_ISO_BB2PP_8814B BIT(7) +#define BIT_ISO_DENG2PP_8814B BIT(6) #define BIT_ISO_MA2MD_8814B BIT(1) #define BIT_ISO_MD2PP_8814B BIT(0) -/* 2 REG_SYS_CFG4_8814B */ +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_ANAPARSW_MAC_0_8814B */ +#define BIT_OCP_L_0_8814B BIT(31) +#define BIT_POWOCP_L_8814B BIT(30) + +#define BIT_SHIFT_CF_L_1_0_8814B 28 +#define BIT_MASK_CF_L_1_0_8814B 0x3 +#define BIT_CF_L_1_0_8814B(x) \ + (((x) & BIT_MASK_CF_L_1_0_8814B) << BIT_SHIFT_CF_L_1_0_8814B) +#define BITS_CF_L_1_0_8814B \ + (BIT_MASK_CF_L_1_0_8814B << BIT_SHIFT_CF_L_1_0_8814B) +#define BIT_CLEAR_CF_L_1_0_8814B(x) ((x) & (~BITS_CF_L_1_0_8814B)) +#define BIT_GET_CF_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_CF_L_1_0_8814B) & BIT_MASK_CF_L_1_0_8814B) +#define BIT_SET_CF_L_1_0_8814B(x, v) \ + (BIT_CLEAR_CF_L_1_0_8814B(x) | BIT_CF_L_1_0_8814B(v)) + +#define BIT_SHIFT_CFC_L_1_0_8814B 26 +#define BIT_MASK_CFC_L_1_0_8814B 0x3 +#define BIT_CFC_L_1_0_8814B(x) \ + (((x) & BIT_MASK_CFC_L_1_0_8814B) << BIT_SHIFT_CFC_L_1_0_8814B) +#define BITS_CFC_L_1_0_8814B \ + (BIT_MASK_CFC_L_1_0_8814B << BIT_SHIFT_CFC_L_1_0_8814B) +#define BIT_CLEAR_CFC_L_1_0_8814B(x) ((x) & (~BITS_CFC_L_1_0_8814B)) +#define BIT_GET_CFC_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_CFC_L_1_0_8814B) & BIT_MASK_CFC_L_1_0_8814B) +#define BIT_SET_CFC_L_1_0_8814B(x, v) \ + (BIT_CLEAR_CFC_L_1_0_8814B(x) | BIT_CFC_L_1_0_8814B(v)) + +#define BIT_SHIFT_R3_L_1_0_8814B 24 +#define BIT_MASK_R3_L_1_0_8814B 0x3 +#define BIT_R3_L_1_0_8814B(x) \ + (((x) & BIT_MASK_R3_L_1_0_8814B) << BIT_SHIFT_R3_L_1_0_8814B) +#define BITS_R3_L_1_0_8814B \ + (BIT_MASK_R3_L_1_0_8814B << BIT_SHIFT_R3_L_1_0_8814B) +#define BIT_CLEAR_R3_L_1_0_8814B(x) ((x) & (~BITS_R3_L_1_0_8814B)) +#define BIT_GET_R3_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_R3_L_1_0_8814B) & BIT_MASK_R3_L_1_0_8814B) +#define BIT_SET_R3_L_1_0_8814B(x, v) \ + (BIT_CLEAR_R3_L_1_0_8814B(x) | BIT_R3_L_1_0_8814B(v)) + +#define BIT_SHIFT_R2_L_1_0_8814B 22 +#define BIT_MASK_R2_L_1_0_8814B 0x3 +#define BIT_R2_L_1_0_8814B(x) \ + (((x) & BIT_MASK_R2_L_1_0_8814B) << BIT_SHIFT_R2_L_1_0_8814B) +#define BITS_R2_L_1_0_8814B \ + (BIT_MASK_R2_L_1_0_8814B << BIT_SHIFT_R2_L_1_0_8814B) +#define BIT_CLEAR_R2_L_1_0_8814B(x) ((x) & (~BITS_R2_L_1_0_8814B)) +#define BIT_GET_R2_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_R2_L_1_0_8814B) & BIT_MASK_R2_L_1_0_8814B) +#define BIT_SET_R2_L_1_0_8814B(x, v) \ + (BIT_CLEAR_R2_L_1_0_8814B(x) | BIT_R2_L_1_0_8814B(v)) + +#define BIT_SHIFT_R1_L_1_0_8814B 20 +#define BIT_MASK_R1_L_1_0_8814B 0x3 +#define BIT_R1_L_1_0_8814B(x) \ + (((x) & BIT_MASK_R1_L_1_0_8814B) << BIT_SHIFT_R1_L_1_0_8814B) +#define BITS_R1_L_1_0_8814B \ + (BIT_MASK_R1_L_1_0_8814B << BIT_SHIFT_R1_L_1_0_8814B) +#define BIT_CLEAR_R1_L_1_0_8814B(x) ((x) & (~BITS_R1_L_1_0_8814B)) +#define BIT_GET_R1_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_R1_L_1_0_8814B) & BIT_MASK_R1_L_1_0_8814B) +#define BIT_SET_R1_L_1_0_8814B(x, v) \ + (BIT_CLEAR_R1_L_1_0_8814B(x) | BIT_R1_L_1_0_8814B(v)) + +#define BIT_SHIFT_C3_L_1_0_8814B 18 +#define BIT_MASK_C3_L_1_0_8814B 0x3 +#define BIT_C3_L_1_0_8814B(x) \ + (((x) & BIT_MASK_C3_L_1_0_8814B) << BIT_SHIFT_C3_L_1_0_8814B) +#define BITS_C3_L_1_0_8814B \ + (BIT_MASK_C3_L_1_0_8814B << BIT_SHIFT_C3_L_1_0_8814B) +#define BIT_CLEAR_C3_L_1_0_8814B(x) ((x) & (~BITS_C3_L_1_0_8814B)) +#define BIT_GET_C3_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_C3_L_1_0_8814B) & BIT_MASK_C3_L_1_0_8814B) +#define BIT_SET_C3_L_1_0_8814B(x, v) \ + (BIT_CLEAR_C3_L_1_0_8814B(x) | BIT_C3_L_1_0_8814B(v)) + +#define BIT_SHIFT_C2_L_1_0_8814B 16 +#define BIT_MASK_C2_L_1_0_8814B 0x3 +#define BIT_C2_L_1_0_8814B(x) \ + (((x) & BIT_MASK_C2_L_1_0_8814B) << BIT_SHIFT_C2_L_1_0_8814B) +#define BITS_C2_L_1_0_8814B \ + (BIT_MASK_C2_L_1_0_8814B << BIT_SHIFT_C2_L_1_0_8814B) +#define BIT_CLEAR_C2_L_1_0_8814B(x) ((x) & (~BITS_C2_L_1_0_8814B)) +#define BIT_GET_C2_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_C2_L_1_0_8814B) & BIT_MASK_C2_L_1_0_8814B) +#define BIT_SET_C2_L_1_0_8814B(x, v) \ + (BIT_CLEAR_C2_L_1_0_8814B(x) | BIT_C2_L_1_0_8814B(v)) + +#define BIT_SHIFT_C1_L_1_0_8814B 14 +#define BIT_MASK_C1_L_1_0_8814B 0x3 +#define BIT_C1_L_1_0_8814B(x) \ + (((x) & BIT_MASK_C1_L_1_0_8814B) << BIT_SHIFT_C1_L_1_0_8814B) +#define BITS_C1_L_1_0_8814B \ + (BIT_MASK_C1_L_1_0_8814B << BIT_SHIFT_C1_L_1_0_8814B) +#define BIT_CLEAR_C1_L_1_0_8814B(x) ((x) & (~BITS_C1_L_1_0_8814B)) +#define BIT_GET_C1_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_C1_L_1_0_8814B) & BIT_MASK_C1_L_1_0_8814B) +#define BIT_SET_C1_L_1_0_8814B(x, v) \ + (BIT_CLEAR_C1_L_1_0_8814B(x) | BIT_C1_L_1_0_8814B(v)) + +#define BIT_REG_TYPE_L_V2_8814B BIT(13) +#define BIT_REG_PWM_L_8814B BIT(12) + +#define BIT_SHIFT_V15ADJ_L_2_0_8814B 9 +#define BIT_MASK_V15ADJ_L_2_0_8814B 0x7 +#define BIT_V15ADJ_L_2_0_8814B(x) \ + (((x) & BIT_MASK_V15ADJ_L_2_0_8814B) << BIT_SHIFT_V15ADJ_L_2_0_8814B) +#define BITS_V15ADJ_L_2_0_8814B \ + (BIT_MASK_V15ADJ_L_2_0_8814B << BIT_SHIFT_V15ADJ_L_2_0_8814B) +#define BIT_CLEAR_V15ADJ_L_2_0_8814B(x) ((x) & (~BITS_V15ADJ_L_2_0_8814B)) +#define BIT_GET_V15ADJ_L_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L_2_0_8814B) & BIT_MASK_V15ADJ_L_2_0_8814B) +#define BIT_SET_V15ADJ_L_2_0_8814B(x, v) \ + (BIT_CLEAR_V15ADJ_L_2_0_8814B(x) | BIT_V15ADJ_L_2_0_8814B(v)) + +#define BIT_SHIFT_IN_L_2_0_8814B 6 +#define BIT_MASK_IN_L_2_0_8814B 0x7 +#define BIT_IN_L_2_0_8814B(x) \ + (((x) & BIT_MASK_IN_L_2_0_8814B) << BIT_SHIFT_IN_L_2_0_8814B) +#define BITS_IN_L_2_0_8814B \ + (BIT_MASK_IN_L_2_0_8814B << BIT_SHIFT_IN_L_2_0_8814B) +#define BIT_CLEAR_IN_L_2_0_8814B(x) ((x) & (~BITS_IN_L_2_0_8814B)) +#define BIT_GET_IN_L_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_IN_L_2_0_8814B) & BIT_MASK_IN_L_2_0_8814B) +#define BIT_SET_IN_L_2_0_8814B(x, v) \ + (BIT_CLEAR_IN_L_2_0_8814B(x) | BIT_IN_L_2_0_8814B(v)) + +#define BIT_SHIFT_STD_L_1_0_8814B 4 +#define BIT_MASK_STD_L_1_0_8814B 0x3 +#define BIT_STD_L_1_0_8814B(x) \ + (((x) & BIT_MASK_STD_L_1_0_8814B) << BIT_SHIFT_STD_L_1_0_8814B) +#define BITS_STD_L_1_0_8814B \ + (BIT_MASK_STD_L_1_0_8814B << BIT_SHIFT_STD_L_1_0_8814B) +#define BIT_CLEAR_STD_L_1_0_8814B(x) ((x) & (~BITS_STD_L_1_0_8814B)) +#define BIT_GET_STD_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_STD_L_1_0_8814B) & BIT_MASK_STD_L_1_0_8814B) +#define BIT_SET_STD_L_1_0_8814B(x, v) \ + (BIT_CLEAR_STD_L_1_0_8814B(x) | BIT_STD_L_1_0_8814B(v)) + +#define BIT_SHIFT_VOL_L_3_0_8814B 0 +#define BIT_MASK_VOL_L_3_0_8814B 0xf +#define BIT_VOL_L_3_0_8814B(x) \ + (((x) & BIT_MASK_VOL_L_3_0_8814B) << BIT_SHIFT_VOL_L_3_0_8814B) +#define BITS_VOL_L_3_0_8814B \ + (BIT_MASK_VOL_L_3_0_8814B << BIT_SHIFT_VOL_L_3_0_8814B) +#define BIT_CLEAR_VOL_L_3_0_8814B(x) ((x) & (~BITS_VOL_L_3_0_8814B)) +#define BIT_GET_VOL_L_3_0_8814B(x) \ + (((x) >> BIT_SHIFT_VOL_L_3_0_8814B) & BIT_MASK_VOL_L_3_0_8814B) +#define BIT_SET_VOL_L_3_0_8814B(x, v) \ + (BIT_CLEAR_VOL_L_3_0_8814B(x) | BIT_VOL_L_3_0_8814B(v)) + +/* 2 REG_ANAPARSW_MAC_1_8814B */ + +#define BIT_SHIFT_REG_FREQ_L_V1_8814B 20 +#define BIT_MASK_REG_FREQ_L_V1_8814B 0x7 +#define BIT_REG_FREQ_L_V1_8814B(x) \ + (((x) & BIT_MASK_REG_FREQ_L_V1_8814B) << BIT_SHIFT_REG_FREQ_L_V1_8814B) +#define BITS_REG_FREQ_L_V1_8814B \ + (BIT_MASK_REG_FREQ_L_V1_8814B << BIT_SHIFT_REG_FREQ_L_V1_8814B) +#define BIT_CLEAR_REG_FREQ_L_V1_8814B(x) ((x) & (~BITS_REG_FREQ_L_V1_8814B)) +#define BIT_GET_REG_FREQ_L_V1_8814B(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L_V1_8814B) & BIT_MASK_REG_FREQ_L_V1_8814B) +#define BIT_SET_REG_FREQ_L_V1_8814B(x, v) \ + (BIT_CLEAR_REG_FREQ_L_V1_8814B(x) | BIT_REG_FREQ_L_V1_8814B(v)) + +#define BIT_EN_DUTY_8814B BIT(19) + +#define BIT_SHIFT_REG_MOS_HALF_8814B 17 +#define BIT_MASK_REG_MOS_HALF_8814B 0x3 +#define BIT_REG_MOS_HALF_8814B(x) \ + (((x) & BIT_MASK_REG_MOS_HALF_8814B) << BIT_SHIFT_REG_MOS_HALF_8814B) +#define BITS_REG_MOS_HALF_8814B \ + (BIT_MASK_REG_MOS_HALF_8814B << BIT_SHIFT_REG_MOS_HALF_8814B) +#define BIT_CLEAR_REG_MOS_HALF_8814B(x) ((x) & (~BITS_REG_MOS_HALF_8814B)) +#define BIT_GET_REG_MOS_HALF_8814B(x) \ + (((x) >> BIT_SHIFT_REG_MOS_HALF_8814B) & BIT_MASK_REG_MOS_HALF_8814B) +#define BIT_SET_REG_MOS_HALF_8814B(x, v) \ + (BIT_CLEAR_REG_MOS_HALF_8814B(x) | BIT_REG_MOS_HALF_8814B(v)) + +#define BIT_EN_SP_8814B BIT(16) +#define BIT_REG_AUTO_L_V1_8814B BIT(15) +#define BIT_REG_LDOF_L_V2_8814B BIT(14) +#define BIT_REG_OCPS_L_V2_8814B BIT(13) + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_ARENB_L_V1_8814B BIT(11) + +#define BIT_SHIFT_TBOX_L1_1_0_8814B 9 +#define BIT_MASK_TBOX_L1_1_0_8814B 0x3 +#define BIT_TBOX_L1_1_0_8814B(x) \ + (((x) & BIT_MASK_TBOX_L1_1_0_8814B) << BIT_SHIFT_TBOX_L1_1_0_8814B) +#define BITS_TBOX_L1_1_0_8814B \ + (BIT_MASK_TBOX_L1_1_0_8814B << BIT_SHIFT_TBOX_L1_1_0_8814B) +#define BIT_CLEAR_TBOX_L1_1_0_8814B(x) ((x) & (~BITS_TBOX_L1_1_0_8814B)) +#define BIT_GET_TBOX_L1_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_1_0_8814B) & BIT_MASK_TBOX_L1_1_0_8814B) +#define BIT_SET_TBOX_L1_1_0_8814B(x, v) \ + (BIT_CLEAR_TBOX_L1_1_0_8814B(x) | BIT_TBOX_L1_1_0_8814B(v)) + +#define BIT_SHIFT_REG_DELAY_L_1_0_8814B 7 +#define BIT_MASK_REG_DELAY_L_1_0_8814B 0x3 +#define BIT_REG_DELAY_L_1_0_8814B(x) \ + (((x) & BIT_MASK_REG_DELAY_L_1_0_8814B) \ + << BIT_SHIFT_REG_DELAY_L_1_0_8814B) +#define BITS_REG_DELAY_L_1_0_8814B \ + (BIT_MASK_REG_DELAY_L_1_0_8814B << BIT_SHIFT_REG_DELAY_L_1_0_8814B) +#define BIT_CLEAR_REG_DELAY_L_1_0_8814B(x) ((x) & (~BITS_REG_DELAY_L_1_0_8814B)) +#define BIT_GET_REG_DELAY_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_L_1_0_8814B) & \ + BIT_MASK_REG_DELAY_L_1_0_8814B) +#define BIT_SET_REG_DELAY_L_1_0_8814B(x, v) \ + (BIT_CLEAR_REG_DELAY_L_1_0_8814B(x) | BIT_REG_DELAY_L_1_0_8814B(v)) + +#define BIT_REG_CLAMP_D_L_8814B BIT(6) +#define BIT_REG_BYPASS_L_V1_8814B BIT(5) +#define BIT_REG_AUTOZCD_L_8814B BIT(4) +#define BIT_POW_ZCD_L_V1_8814B BIT(3) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_OCP_L_2_1_8814B 0 +#define BIT_MASK_OCP_L_2_1_8814B 0x3 +#define BIT_OCP_L_2_1_8814B(x) \ + (((x) & BIT_MASK_OCP_L_2_1_8814B) << BIT_SHIFT_OCP_L_2_1_8814B) +#define BITS_OCP_L_2_1_8814B \ + (BIT_MASK_OCP_L_2_1_8814B << BIT_SHIFT_OCP_L_2_1_8814B) +#define BIT_CLEAR_OCP_L_2_1_8814B(x) ((x) & (~BITS_OCP_L_2_1_8814B)) +#define BIT_GET_OCP_L_2_1_8814B(x) \ + (((x) >> BIT_SHIFT_OCP_L_2_1_8814B) & BIT_MASK_OCP_L_2_1_8814B) +#define BIT_SET_OCP_L_2_1_8814B(x, v) \ + (BIT_CLEAR_OCP_L_2_1_8814B(x) | BIT_OCP_L_2_1_8814B(v)) + +/* 2 REG_ANAPAR_MAC_0_8814B */ + +#define BIT_SHIFT_LPF_C2_1_0_8814B 30 +#define BIT_MASK_LPF_C2_1_0_8814B 0x3 +#define BIT_LPF_C2_1_0_8814B(x) \ + (((x) & BIT_MASK_LPF_C2_1_0_8814B) << BIT_SHIFT_LPF_C2_1_0_8814B) +#define BITS_LPF_C2_1_0_8814B \ + (BIT_MASK_LPF_C2_1_0_8814B << BIT_SHIFT_LPF_C2_1_0_8814B) +#define BIT_CLEAR_LPF_C2_1_0_8814B(x) ((x) & (~BITS_LPF_C2_1_0_8814B)) +#define BIT_GET_LPF_C2_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_C2_1_0_8814B) & BIT_MASK_LPF_C2_1_0_8814B) +#define BIT_SET_LPF_C2_1_0_8814B(x, v) \ + (BIT_CLEAR_LPF_C2_1_0_8814B(x) | BIT_LPF_C2_1_0_8814B(v)) + +#define BIT_SHIFT_LPF_C1_5_0_8814B 24 +#define BIT_MASK_LPF_C1_5_0_8814B 0x3f +#define BIT_LPF_C1_5_0_8814B(x) \ + (((x) & BIT_MASK_LPF_C1_5_0_8814B) << BIT_SHIFT_LPF_C1_5_0_8814B) +#define BITS_LPF_C1_5_0_8814B \ + (BIT_MASK_LPF_C1_5_0_8814B << BIT_SHIFT_LPF_C1_5_0_8814B) +#define BIT_CLEAR_LPF_C1_5_0_8814B(x) ((x) & (~BITS_LPF_C1_5_0_8814B)) +#define BIT_GET_LPF_C1_5_0_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_C1_5_0_8814B) & BIT_MASK_LPF_C1_5_0_8814B) +#define BIT_SET_LPF_C1_5_0_8814B(x, v) \ + (BIT_CLEAR_LPF_C1_5_0_8814B(x) | BIT_LPF_C1_5_0_8814B(v)) + +#define BIT_LPF_TIEL_8814B BIT(23) +#define BIT_LPF_TIEH_8814B BIT(22) + +#define BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B 20 +#define BIT_MASK_LOCKDET_VREF_L_1_0_8814B 0x3 +#define BIT_LOCKDET_VREF_L_1_0_8814B(x) \ + (((x) & BIT_MASK_LOCKDET_VREF_L_1_0_8814B) \ + << BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B) +#define BITS_LOCKDET_VREF_L_1_0_8814B \ + (BIT_MASK_LOCKDET_VREF_L_1_0_8814B \ + << BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B) +#define BIT_CLEAR_LOCKDET_VREF_L_1_0_8814B(x) \ + ((x) & (~BITS_LOCKDET_VREF_L_1_0_8814B)) +#define BIT_GET_LOCKDET_VREF_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B) & \ + BIT_MASK_LOCKDET_VREF_L_1_0_8814B) +#define BIT_SET_LOCKDET_VREF_L_1_0_8814B(x, v) \ + (BIT_CLEAR_LOCKDET_VREF_L_1_0_8814B(x) | \ + BIT_LOCKDET_VREF_L_1_0_8814B(v)) + +#define BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B 18 +#define BIT_MASK_LOCKDET_VREF_H_1_0_8814B 0x3 +#define BIT_LOCKDET_VREF_H_1_0_8814B(x) \ + (((x) & BIT_MASK_LOCKDET_VREF_H_1_0_8814B) \ + << BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B) +#define BITS_LOCKDET_VREF_H_1_0_8814B \ + (BIT_MASK_LOCKDET_VREF_H_1_0_8814B \ + << BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B) +#define BIT_CLEAR_LOCKDET_VREF_H_1_0_8814B(x) \ + ((x) & (~BITS_LOCKDET_VREF_H_1_0_8814B)) +#define BIT_GET_LOCKDET_VREF_H_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B) & \ + BIT_MASK_LOCKDET_VREF_H_1_0_8814B) +#define BIT_SET_LOCKDET_VREF_H_1_0_8814B(x, v) \ + (BIT_CLEAR_LOCKDET_VREF_H_1_0_8814B(x) | \ + BIT_LOCKDET_VREF_H_1_0_8814B(v)) + +#define BIT_SHIFT_LDO_SEL_1_0_8814B 16 +#define BIT_MASK_LDO_SEL_1_0_8814B 0x3 +#define BIT_LDO_SEL_1_0_8814B(x) \ + (((x) & BIT_MASK_LDO_SEL_1_0_8814B) << BIT_SHIFT_LDO_SEL_1_0_8814B) +#define BITS_LDO_SEL_1_0_8814B \ + (BIT_MASK_LDO_SEL_1_0_8814B << BIT_SHIFT_LDO_SEL_1_0_8814B) +#define BIT_CLEAR_LDO_SEL_1_0_8814B(x) ((x) & (~BITS_LDO_SEL_1_0_8814B)) +#define BIT_GET_LDO_SEL_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LDO_SEL_1_0_8814B) & BIT_MASK_LDO_SEL_1_0_8814B) +#define BIT_SET_LDO_SEL_1_0_8814B(x, v) \ + (BIT_CLEAR_LDO_SEL_1_0_8814B(x) | BIT_LDO_SEL_1_0_8814B(v)) + +#define BIT_SHIFT_IOFFSET_5_0_8814B 10 +#define BIT_MASK_IOFFSET_5_0_8814B 0x3f +#define BIT_IOFFSET_5_0_8814B(x) \ + (((x) & BIT_MASK_IOFFSET_5_0_8814B) << BIT_SHIFT_IOFFSET_5_0_8814B) +#define BITS_IOFFSET_5_0_8814B \ + (BIT_MASK_IOFFSET_5_0_8814B << BIT_SHIFT_IOFFSET_5_0_8814B) +#define BIT_CLEAR_IOFFSET_5_0_8814B(x) ((x) & (~BITS_IOFFSET_5_0_8814B)) +#define BIT_GET_IOFFSET_5_0_8814B(x) \ + (((x) >> BIT_SHIFT_IOFFSET_5_0_8814B) & BIT_MASK_IOFFSET_5_0_8814B) +#define BIT_SET_IOFFSET_5_0_8814B(x, v) \ + (BIT_CLEAR_IOFFSET_5_0_8814B(x) | BIT_IOFFSET_5_0_8814B(v)) + +#define BIT_CP_ICPX2_8814B BIT(9) + +#define BIT_SHIFT_CP_ICP_SEL_4_0_8814B 4 +#define BIT_MASK_CP_ICP_SEL_4_0_8814B 0x1f +#define BIT_CP_ICP_SEL_4_0_8814B(x) \ + (((x) & BIT_MASK_CP_ICP_SEL_4_0_8814B) \ + << BIT_SHIFT_CP_ICP_SEL_4_0_8814B) +#define BITS_CP_ICP_SEL_4_0_8814B \ + (BIT_MASK_CP_ICP_SEL_4_0_8814B << BIT_SHIFT_CP_ICP_SEL_4_0_8814B) +#define BIT_CLEAR_CP_ICP_SEL_4_0_8814B(x) ((x) & (~BITS_CP_ICP_SEL_4_0_8814B)) +#define BIT_GET_CP_ICP_SEL_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_CP_ICP_SEL_4_0_8814B) & \ + BIT_MASK_CP_ICP_SEL_4_0_8814B) +#define BIT_SET_CP_ICP_SEL_4_0_8814B(x, v) \ + (BIT_CLEAR_CP_ICP_SEL_4_0_8814B(x) | BIT_CP_ICP_SEL_4_0_8814B(v)) + +#define BIT_SHIFT_IB_PI_1_0_8814B 2 +#define BIT_MASK_IB_PI_1_0_8814B 0x3 +#define BIT_IB_PI_1_0_8814B(x) \ + (((x) & BIT_MASK_IB_PI_1_0_8814B) << BIT_SHIFT_IB_PI_1_0_8814B) +#define BITS_IB_PI_1_0_8814B \ + (BIT_MASK_IB_PI_1_0_8814B << BIT_SHIFT_IB_PI_1_0_8814B) +#define BIT_CLEAR_IB_PI_1_0_8814B(x) ((x) & (~BITS_IB_PI_1_0_8814B)) +#define BIT_GET_IB_PI_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_IB_PI_1_0_8814B) & BIT_MASK_IB_PI_1_0_8814B) +#define BIT_SET_IB_PI_1_0_8814B(x, v) \ + (BIT_CLEAR_IB_PI_1_0_8814B(x) | BIT_IB_PI_1_0_8814B(v)) + +#define BIT_SHIFT_LDO_VSEL_8814B 0 +#define BIT_MASK_LDO_VSEL_8814B 0x3 +#define BIT_LDO_VSEL_8814B(x) \ + (((x) & BIT_MASK_LDO_VSEL_8814B) << BIT_SHIFT_LDO_VSEL_8814B) +#define BITS_LDO_VSEL_8814B \ + (BIT_MASK_LDO_VSEL_8814B << BIT_SHIFT_LDO_VSEL_8814B) +#define BIT_CLEAR_LDO_VSEL_8814B(x) ((x) & (~BITS_LDO_VSEL_8814B)) +#define BIT_GET_LDO_VSEL_8814B(x) \ + (((x) >> BIT_SHIFT_LDO_VSEL_8814B) & BIT_MASK_LDO_VSEL_8814B) +#define BIT_SET_LDO_VSEL_8814B(x, v) \ + (BIT_CLEAR_LDO_VSEL_8814B(x) | BIT_LDO_VSEL_8814B(v)) + +/* 2 REG_ANAPAR_MAC_1_8814B */ + +#define BIT_SHIFT_CKX_USB_IB_SEL_8814B 29 +#define BIT_MASK_CKX_USB_IB_SEL_8814B 0x7 +#define BIT_CKX_USB_IB_SEL_8814B(x) \ + (((x) & BIT_MASK_CKX_USB_IB_SEL_8814B) \ + << BIT_SHIFT_CKX_USB_IB_SEL_8814B) +#define BITS_CKX_USB_IB_SEL_8814B \ + (BIT_MASK_CKX_USB_IB_SEL_8814B << BIT_SHIFT_CKX_USB_IB_SEL_8814B) +#define BIT_CLEAR_CKX_USB_IB_SEL_8814B(x) ((x) & (~BITS_CKX_USB_IB_SEL_8814B)) +#define BIT_GET_CKX_USB_IB_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_CKX_USB_IB_SEL_8814B) & \ + BIT_MASK_CKX_USB_IB_SEL_8814B) +#define BIT_SET_CKX_USB_IB_SEL_8814B(x, v) \ + (BIT_CLEAR_CKX_USB_IB_SEL_8814B(x) | BIT_CKX_USB_IB_SEL_8814B(v)) + +#define BIT_PFD_DN_GATED_8814B BIT(28) +#define BIT_PFD_UP_GATED_8814B BIT(27) +#define BIT_PFD_RESET_GATED_8814B BIT(26) + +#define BIT_SHIFT_PFD_OUT_DRV_1_0_8814B 24 +#define BIT_MASK_PFD_OUT_DRV_1_0_8814B 0x3 +#define BIT_PFD_OUT_DRV_1_0_8814B(x) \ + (((x) & BIT_MASK_PFD_OUT_DRV_1_0_8814B) \ + << BIT_SHIFT_PFD_OUT_DRV_1_0_8814B) +#define BITS_PFD_OUT_DRV_1_0_8814B \ + (BIT_MASK_PFD_OUT_DRV_1_0_8814B << BIT_SHIFT_PFD_OUT_DRV_1_0_8814B) +#define BIT_CLEAR_PFD_OUT_DRV_1_0_8814B(x) ((x) & (~BITS_PFD_OUT_DRV_1_0_8814B)) +#define BIT_GET_PFD_OUT_DRV_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_PFD_OUT_DRV_1_0_8814B) & \ + BIT_MASK_PFD_OUT_DRV_1_0_8814B) +#define BIT_SET_PFD_OUT_DRV_1_0_8814B(x, v) \ + (BIT_CLEAR_PFD_OUT_DRV_1_0_8814B(x) | BIT_PFD_OUT_DRV_1_0_8814B(v)) + +#define BIT_SHIFT_LPF_TIEMID_2_0_8814B 20 +#define BIT_MASK_LPF_TIEMID_2_0_8814B 0x7 +#define BIT_LPF_TIEMID_2_0_8814B(x) \ + (((x) & BIT_MASK_LPF_TIEMID_2_0_8814B) \ + << BIT_SHIFT_LPF_TIEMID_2_0_8814B) +#define BITS_LPF_TIEMID_2_0_8814B \ + (BIT_MASK_LPF_TIEMID_2_0_8814B << BIT_SHIFT_LPF_TIEMID_2_0_8814B) +#define BIT_CLEAR_LPF_TIEMID_2_0_8814B(x) ((x) & (~BITS_LPF_TIEMID_2_0_8814B)) +#define BIT_GET_LPF_TIEMID_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_TIEMID_2_0_8814B) & \ + BIT_MASK_LPF_TIEMID_2_0_8814B) +#define BIT_SET_LPF_TIEMID_2_0_8814B(x, v) \ + (BIT_CLEAR_LPF_TIEMID_2_0_8814B(x) | BIT_LPF_TIEMID_2_0_8814B(v)) + +#define BIT_SHIFT_LPF_R3_4_0_8814B 15 +#define BIT_MASK_LPF_R3_4_0_8814B 0x1f +#define BIT_LPF_R3_4_0_8814B(x) \ + (((x) & BIT_MASK_LPF_R3_4_0_8814B) << BIT_SHIFT_LPF_R3_4_0_8814B) +#define BITS_LPF_R3_4_0_8814B \ + (BIT_MASK_LPF_R3_4_0_8814B << BIT_SHIFT_LPF_R3_4_0_8814B) +#define BIT_CLEAR_LPF_R3_4_0_8814B(x) ((x) & (~BITS_LPF_R3_4_0_8814B)) +#define BIT_GET_LPF_R3_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_R3_4_0_8814B) & BIT_MASK_LPF_R3_4_0_8814B) +#define BIT_SET_LPF_R3_4_0_8814B(x, v) \ + (BIT_CLEAR_LPF_R3_4_0_8814B(x) | BIT_LPF_R3_4_0_8814B(v)) + +#define BIT_SHIFT_LPF_R2_4_0_8814B 10 +#define BIT_MASK_LPF_R2_4_0_8814B 0x1f +#define BIT_LPF_R2_4_0_8814B(x) \ + (((x) & BIT_MASK_LPF_R2_4_0_8814B) << BIT_SHIFT_LPF_R2_4_0_8814B) +#define BITS_LPF_R2_4_0_8814B \ + (BIT_MASK_LPF_R2_4_0_8814B << BIT_SHIFT_LPF_R2_4_0_8814B) +#define BIT_CLEAR_LPF_R2_4_0_8814B(x) ((x) & (~BITS_LPF_R2_4_0_8814B)) +#define BIT_GET_LPF_R2_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_R2_4_0_8814B) & BIT_MASK_LPF_R2_4_0_8814B) +#define BIT_SET_LPF_R2_4_0_8814B(x, v) \ + (BIT_CLEAR_LPF_R2_4_0_8814B(x) | BIT_LPF_R2_4_0_8814B(v)) + +#define BIT_SHIFT_LPF_C3_5_0_8814B 4 +#define BIT_MASK_LPF_C3_5_0_8814B 0x3f +#define BIT_LPF_C3_5_0_8814B(x) \ + (((x) & BIT_MASK_LPF_C3_5_0_8814B) << BIT_SHIFT_LPF_C3_5_0_8814B) +#define BITS_LPF_C3_5_0_8814B \ + (BIT_MASK_LPF_C3_5_0_8814B << BIT_SHIFT_LPF_C3_5_0_8814B) +#define BIT_CLEAR_LPF_C3_5_0_8814B(x) ((x) & (~BITS_LPF_C3_5_0_8814B)) +#define BIT_GET_LPF_C3_5_0_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_C3_5_0_8814B) & BIT_MASK_LPF_C3_5_0_8814B) +#define BIT_SET_LPF_C3_5_0_8814B(x, v) \ + (BIT_CLEAR_LPF_C3_5_0_8814B(x) | BIT_LPF_C3_5_0_8814B(v)) + +#define BIT_SHIFT_LPF_C2_5_2_8814B 0 +#define BIT_MASK_LPF_C2_5_2_8814B 0xf +#define BIT_LPF_C2_5_2_8814B(x) \ + (((x) & BIT_MASK_LPF_C2_5_2_8814B) << BIT_SHIFT_LPF_C2_5_2_8814B) +#define BITS_LPF_C2_5_2_8814B \ + (BIT_MASK_LPF_C2_5_2_8814B << BIT_SHIFT_LPF_C2_5_2_8814B) +#define BIT_CLEAR_LPF_C2_5_2_8814B(x) ((x) & (~BITS_LPF_C2_5_2_8814B)) +#define BIT_GET_LPF_C2_5_2_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_C2_5_2_8814B) & BIT_MASK_LPF_C2_5_2_8814B) +#define BIT_SET_LPF_C2_5_2_8814B(x, v) \ + (BIT_CLEAR_LPF_C2_5_2_8814B(x) | BIT_LPF_C2_5_2_8814B(v)) + +/* 2 REG_ANAPAR_MAC_2_8814B */ +#define BIT_CK_PHASE_SEL_8814B BIT(31) +#define BIT_CK960M_EN_8814B BIT(30) +#define BIT_CK640M_EN_8814B BIT(29) +#define BIT_CK240M_EN_8814B BIT(28) + +#define BIT_SHIFT_CK_MON_SEL_2_0_8814B 25 +#define BIT_MASK_CK_MON_SEL_2_0_8814B 0x7 +#define BIT_CK_MON_SEL_2_0_8814B(x) \ + (((x) & BIT_MASK_CK_MON_SEL_2_0_8814B) \ + << BIT_SHIFT_CK_MON_SEL_2_0_8814B) +#define BITS_CK_MON_SEL_2_0_8814B \ + (BIT_MASK_CK_MON_SEL_2_0_8814B << BIT_SHIFT_CK_MON_SEL_2_0_8814B) +#define BIT_CLEAR_CK_MON_SEL_2_0_8814B(x) ((x) & (~BITS_CK_MON_SEL_2_0_8814B)) +#define BIT_GET_CK_MON_SEL_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL_2_0_8814B) & \ + BIT_MASK_CK_MON_SEL_2_0_8814B) +#define BIT_SET_CK_MON_SEL_2_0_8814B(x, v) \ + (BIT_CLEAR_CK_MON_SEL_2_0_8814B(x) | BIT_CK_MON_SEL_2_0_8814B(v)) + +#define BIT_CK_MON_EN_V1_8814B BIT(24) +#define BIT_XTAL_SOURCE_SEL_8814B BIT(23) +#define BIT_XTAL_FREQ_SEL_8814B BIT(22) +#define BIT_XTAL_EDGE_SEL_8814B BIT(21) +#define BIT_XTAL_BUF_SEL_8814B BIT(20) + +#define BIT_SHIFT_VCO_CV_7_0_8814B 4 +#define BIT_MASK_VCO_CV_7_0_8814B 0xff +#define BIT_VCO_CV_7_0_8814B(x) \ + (((x) & BIT_MASK_VCO_CV_7_0_8814B) << BIT_SHIFT_VCO_CV_7_0_8814B) +#define BITS_VCO_CV_7_0_8814B \ + (BIT_MASK_VCO_CV_7_0_8814B << BIT_SHIFT_VCO_CV_7_0_8814B) +#define BIT_CLEAR_VCO_CV_7_0_8814B(x) ((x) & (~BITS_VCO_CV_7_0_8814B)) +#define BIT_GET_VCO_CV_7_0_8814B(x) \ + (((x) >> BIT_SHIFT_VCO_CV_7_0_8814B) & BIT_MASK_VCO_CV_7_0_8814B) +#define BIT_SET_VCO_CV_7_0_8814B(x, v) \ + (BIT_CLEAR_VCO_CV_7_0_8814B(x) | BIT_VCO_CV_7_0_8814B(v)) + +#define BIT_VCO_KVCO_8814B BIT(3) +#define BIT_SDM_EDGE_SEL_8814B BIT(2) +#define BIT_SDM_CK_SEL_8814B BIT(1) +#define BIT_SDM_CK_GATED_8814B BIT(0) + +/* 2 REG_ANAPAR_MAC_3_8814B */ + +#define BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B 28 +#define BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B 0x7 +#define BIT_LCK_WAIT_CYCLE_2_0_8814B(x) \ + (((x) & BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B) \ + << BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B) +#define BITS_LCK_WAIT_CYCLE_2_0_8814B \ + (BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B \ + << BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B) +#define BIT_CLEAR_LCK_WAIT_CYCLE_2_0_8814B(x) \ + ((x) & (~BITS_LCK_WAIT_CYCLE_2_0_8814B)) +#define BIT_GET_LCK_WAIT_CYCLE_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B) & \ + BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B) +#define BIT_SET_LCK_WAIT_CYCLE_2_0_8814B(x, v) \ + (BIT_CLEAR_LCK_WAIT_CYCLE_2_0_8814B(x) | \ + BIT_LCK_WAIT_CYCLE_2_0_8814B(v)) + +#define BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B 26 +#define BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B 0x3 +#define BIT_LCK_VCO_DIVISOR_1_0_8814B(x) \ + (((x) & BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B) \ + << BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B) +#define BITS_LCK_VCO_DIVISOR_1_0_8814B \ + (BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B \ + << BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B) +#define BIT_CLEAR_LCK_VCO_DIVISOR_1_0_8814B(x) \ + ((x) & (~BITS_LCK_VCO_DIVISOR_1_0_8814B)) +#define BIT_GET_LCK_VCO_DIVISOR_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B) & \ + BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B) +#define BIT_SET_LCK_VCO_DIVISOR_1_0_8814B(x, v) \ + (BIT_CLEAR_LCK_VCO_DIVISOR_1_0_8814B(x) | \ + BIT_LCK_VCO_DIVISOR_1_0_8814B(v)) + +#define BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B 24 +#define BIT_MASK_LCK_SEARCH_MODE_1_0_8814B 0x3 +#define BIT_LCK_SEARCH_MODE_1_0_8814B(x) \ + (((x) & BIT_MASK_LCK_SEARCH_MODE_1_0_8814B) \ + << BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B) +#define BITS_LCK_SEARCH_MODE_1_0_8814B \ + (BIT_MASK_LCK_SEARCH_MODE_1_0_8814B \ + << BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B) +#define BIT_CLEAR_LCK_SEARCH_MODE_1_0_8814B(x) \ + ((x) & (~BITS_LCK_SEARCH_MODE_1_0_8814B)) +#define BIT_GET_LCK_SEARCH_MODE_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B) & \ + BIT_MASK_LCK_SEARCH_MODE_1_0_8814B) +#define BIT_SET_LCK_SEARCH_MODE_1_0_8814B(x, v) \ + (BIT_CLEAR_LCK_SEARCH_MODE_1_0_8814B(x) | \ + BIT_LCK_SEARCH_MODE_1_0_8814B(v)) + +#define BIT_SHIFT_LS_CV_OFFSET_3_0_8814B 12 +#define BIT_MASK_LS_CV_OFFSET_3_0_8814B 0xf +#define BIT_LS_CV_OFFSET_3_0_8814B(x) \ + (((x) & BIT_MASK_LS_CV_OFFSET_3_0_8814B) \ + << BIT_SHIFT_LS_CV_OFFSET_3_0_8814B) +#define BITS_LS_CV_OFFSET_3_0_8814B \ + (BIT_MASK_LS_CV_OFFSET_3_0_8814B << BIT_SHIFT_LS_CV_OFFSET_3_0_8814B) +#define BIT_CLEAR_LS_CV_OFFSET_3_0_8814B(x) \ + ((x) & (~BITS_LS_CV_OFFSET_3_0_8814B)) +#define BIT_GET_LS_CV_OFFSET_3_0_8814B(x) \ + (((x) >> BIT_SHIFT_LS_CV_OFFSET_3_0_8814B) & \ + BIT_MASK_LS_CV_OFFSET_3_0_8814B) +#define BIT_SET_LS_CV_OFFSET_3_0_8814B(x, v) \ + (BIT_CLEAR_LS_CV_OFFSET_3_0_8814B(x) | BIT_LS_CV_OFFSET_3_0_8814B(v)) + +#define BIT_LS_EN_LC_CK40M_8814B BIT(11) +#define BIT_LS__CV_MANUAL_8814B BIT(10) +#define BIT_LS_PYPASS_PI_8814B BIT(9) +#define BIT_MBIASE_8814B BIT(4) + +/* 2 REG_ANAPAR_MAC_4_8814B */ +#define BIT_LS_TIE_MID_MODE_8814B BIT(28) + +#define BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B 26 +#define BIT_MASK_LS_SYNC_CYCLE_1_0_8814B 0x3 +#define BIT_LS_SYNC_CYCLE_1_0_8814B(x) \ + (((x) & BIT_MASK_LS_SYNC_CYCLE_1_0_8814B) \ + << BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B) +#define BITS_LS_SYNC_CYCLE_1_0_8814B \ + (BIT_MASK_LS_SYNC_CYCLE_1_0_8814B << BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B) +#define BIT_CLEAR_LS_SYNC_CYCLE_1_0_8814B(x) \ + ((x) & (~BITS_LS_SYNC_CYCLE_1_0_8814B)) +#define BIT_GET_LS_SYNC_CYCLE_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B) & \ + BIT_MASK_LS_SYNC_CYCLE_1_0_8814B) +#define BIT_SET_LS_SYNC_CYCLE_1_0_8814B(x, v) \ + (BIT_CLEAR_LS_SYNC_CYCLE_1_0_8814B(x) | BIT_LS_SYNC_CYCLE_1_0_8814B(v)) + +#define BIT_LS_SDM_ORDER_8814B BIT(25) +#define BIT_LS_RST_LC_CAL_8814B BIT(14) +#define BIT_LS_RSTB_8814B BIT(13) +#define BIT_LS_POW_LC_CAL_PREP_8814B BIT(11) + +#define BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B 0 +#define BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B 0x3 +#define BIT_LCK_XTAL_DIVISOR_1_0_8814B(x) \ + (((x) & BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B) \ + << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B) +#define BITS_LCK_XTAL_DIVISOR_1_0_8814B \ + (BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B \ + << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B) +#define BIT_CLEAR_LCK_XTAL_DIVISOR_1_0_8814B(x) \ + ((x) & (~BITS_LCK_XTAL_DIVISOR_1_0_8814B)) +#define BIT_GET_LCK_XTAL_DIVISOR_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B) & \ + BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B) +#define BIT_SET_LCK_XTAL_DIVISOR_1_0_8814B(x, v) \ + (BIT_CLEAR_LCK_XTAL_DIVISOR_1_0_8814B(x) | \ + BIT_LCK_XTAL_DIVISOR_1_0_8814B(v)) + +/* 2 REG_ANAPAR_MAC_5_8814B */ + +#define BIT_SHIFT_LS_XTAL_SEL_3_0_8814B 0 +#define BIT_MASK_LS_XTAL_SEL_3_0_8814B 0xf +#define BIT_LS_XTAL_SEL_3_0_8814B(x) \ + (((x) & BIT_MASK_LS_XTAL_SEL_3_0_8814B) \ + << BIT_SHIFT_LS_XTAL_SEL_3_0_8814B) +#define BITS_LS_XTAL_SEL_3_0_8814B \ + (BIT_MASK_LS_XTAL_SEL_3_0_8814B << BIT_SHIFT_LS_XTAL_SEL_3_0_8814B) +#define BIT_CLEAR_LS_XTAL_SEL_3_0_8814B(x) ((x) & (~BITS_LS_XTAL_SEL_3_0_8814B)) +#define BIT_GET_LS_XTAL_SEL_3_0_8814B(x) \ + (((x) >> BIT_SHIFT_LS_XTAL_SEL_3_0_8814B) & \ + BIT_MASK_LS_XTAL_SEL_3_0_8814B) +#define BIT_SET_LS_XTAL_SEL_3_0_8814B(x, v) \ + (BIT_CLEAR_LS_XTAL_SEL_3_0_8814B(x) | BIT_LS_XTAL_SEL_3_0_8814B(v)) + +/* 2 REG_ANAPAR_MAC_6_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_ANAPAR_MAC_7_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_ANAPAR_MAC_8_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_ANAPAR_XTAL_0_8814B */ +#define BIT_XTAL_DRV_RF1_0_8814B BIT(31) +#define BIT_XTAL_GATED_RF1N_8814B BIT(30) +#define BIT_XTAL_GATED_RF1P_8814B BIT(29) +#define BIT_XTAL_GM_SEP_V2_8814B BIT(28) + +#define BIT_SHIFT_XTAL_LDO_1_0_8814B 26 +#define BIT_MASK_XTAL_LDO_1_0_8814B 0x3 +#define BIT_XTAL_LDO_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_LDO_1_0_8814B) << BIT_SHIFT_XTAL_LDO_1_0_8814B) +#define BITS_XTAL_LDO_1_0_8814B \ + (BIT_MASK_XTAL_LDO_1_0_8814B << BIT_SHIFT_XTAL_LDO_1_0_8814B) +#define BIT_CLEAR_XTAL_LDO_1_0_8814B(x) ((x) & (~BITS_XTAL_LDO_1_0_8814B)) +#define BIT_GET_XTAL_LDO_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_1_0_8814B) & BIT_MASK_XTAL_LDO_1_0_8814B) +#define BIT_SET_XTAL_LDO_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_LDO_1_0_8814B(x) | BIT_XTAL_LDO_1_0_8814B(v)) + +#define BIT_XQSEL_V1_8814B BIT(25) +#define BIT_GATED_XTAL_OK0_8814B BIT(24) + +#define BIT_SHIFT_XTAL_SC_XO_6_0_8814B 17 +#define BIT_MASK_XTAL_SC_XO_6_0_8814B 0x7f +#define BIT_XTAL_SC_XO_6_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_SC_XO_6_0_8814B) \ + << BIT_SHIFT_XTAL_SC_XO_6_0_8814B) +#define BITS_XTAL_SC_XO_6_0_8814B \ + (BIT_MASK_XTAL_SC_XO_6_0_8814B << BIT_SHIFT_XTAL_SC_XO_6_0_8814B) +#define BIT_CLEAR_XTAL_SC_XO_6_0_8814B(x) ((x) & (~BITS_XTAL_SC_XO_6_0_8814B)) +#define BIT_GET_XTAL_SC_XO_6_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XO_6_0_8814B) & \ + BIT_MASK_XTAL_SC_XO_6_0_8814B) +#define BIT_SET_XTAL_SC_XO_6_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_SC_XO_6_0_8814B(x) | BIT_XTAL_SC_XO_6_0_8814B(v)) + +#define BIT_SHIFT_XTAL_SC_XI_6_0_8814B 10 +#define BIT_MASK_XTAL_SC_XI_6_0_8814B 0x7f +#define BIT_XTAL_SC_XI_6_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_SC_XI_6_0_8814B) \ + << BIT_SHIFT_XTAL_SC_XI_6_0_8814B) +#define BITS_XTAL_SC_XI_6_0_8814B \ + (BIT_MASK_XTAL_SC_XI_6_0_8814B << BIT_SHIFT_XTAL_SC_XI_6_0_8814B) +#define BIT_CLEAR_XTAL_SC_XI_6_0_8814B(x) ((x) & (~BITS_XTAL_SC_XI_6_0_8814B)) +#define BIT_GET_XTAL_SC_XI_6_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XI_6_0_8814B) & \ + BIT_MASK_XTAL_SC_XI_6_0_8814B) +#define BIT_SET_XTAL_SC_XI_6_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_SC_XI_6_0_8814B(x) | BIT_XTAL_SC_XI_6_0_8814B(v)) + +#define BIT_SHIFT_XTAL_GMN_4_0_8814B 5 +#define BIT_MASK_XTAL_GMN_4_0_8814B 0x1f +#define BIT_XTAL_GMN_4_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_GMN_4_0_8814B) << BIT_SHIFT_XTAL_GMN_4_0_8814B) +#define BITS_XTAL_GMN_4_0_8814B \ + (BIT_MASK_XTAL_GMN_4_0_8814B << BIT_SHIFT_XTAL_GMN_4_0_8814B) +#define BIT_CLEAR_XTAL_GMN_4_0_8814B(x) ((x) & (~BITS_XTAL_GMN_4_0_8814B)) +#define BIT_GET_XTAL_GMN_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_4_0_8814B) & BIT_MASK_XTAL_GMN_4_0_8814B) +#define BIT_SET_XTAL_GMN_4_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_GMN_4_0_8814B(x) | BIT_XTAL_GMN_4_0_8814B(v)) + +#define BIT_SHIFT_XTAL_GMP_4_0_8814B 0 +#define BIT_MASK_XTAL_GMP_4_0_8814B 0x1f +#define BIT_XTAL_GMP_4_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_GMP_4_0_8814B) << BIT_SHIFT_XTAL_GMP_4_0_8814B) +#define BITS_XTAL_GMP_4_0_8814B \ + (BIT_MASK_XTAL_GMP_4_0_8814B << BIT_SHIFT_XTAL_GMP_4_0_8814B) +#define BIT_CLEAR_XTAL_GMP_4_0_8814B(x) ((x) & (~BITS_XTAL_GMP_4_0_8814B)) +#define BIT_GET_XTAL_GMP_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_4_0_8814B) & BIT_MASK_XTAL_GMP_4_0_8814B) +#define BIT_SET_XTAL_GMP_4_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_GMP_4_0_8814B(x) | BIT_XTAL_GMP_4_0_8814B(v)) + +/* 2 REG_ANAPAR_XTAL_1_8814B */ + +#define BIT_SHIFT_XTAL_LDO_OK_1_0_8814B 30 +#define BIT_MASK_XTAL_LDO_OK_1_0_8814B 0x3 +#define BIT_XTAL_LDO_OK_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_LDO_OK_1_0_8814B) \ + << BIT_SHIFT_XTAL_LDO_OK_1_0_8814B) +#define BITS_XTAL_LDO_OK_1_0_8814B \ + (BIT_MASK_XTAL_LDO_OK_1_0_8814B << BIT_SHIFT_XTAL_LDO_OK_1_0_8814B) +#define BIT_CLEAR_XTAL_LDO_OK_1_0_8814B(x) ((x) & (~BITS_XTAL_LDO_OK_1_0_8814B)) +#define BIT_GET_XTAL_LDO_OK_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_OK_1_0_8814B) & \ + BIT_MASK_XTAL_LDO_OK_1_0_8814B) +#define BIT_SET_XTAL_LDO_OK_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_LDO_OK_1_0_8814B(x) | BIT_XTAL_LDO_OK_1_0_8814B(v)) + +#define BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B 27 +#define BIT_MASK_XTAL_XORES_SEL_2_0_8814B 0x7 +#define BIT_XTAL_XORES_SEL_2_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_XORES_SEL_2_0_8814B) \ + << BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B) +#define BITS_XTAL_XORES_SEL_2_0_8814B \ + (BIT_MASK_XTAL_XORES_SEL_2_0_8814B \ + << BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B) +#define BIT_CLEAR_XTAL_XORES_SEL_2_0_8814B(x) \ + ((x) & (~BITS_XTAL_XORES_SEL_2_0_8814B)) +#define BIT_GET_XTAL_XORES_SEL_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B) & \ + BIT_MASK_XTAL_XORES_SEL_2_0_8814B) +#define BIT_SET_XTAL_XORES_SEL_2_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_XORES_SEL_2_0_8814B(x) | \ + BIT_XTAL_XORES_SEL_2_0_8814B(v)) + +#define BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B 25 +#define BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B 0x3 +#define BIT_XTAL_AAC_PK_SEL_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B) \ + << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B) +#define BITS_XTAL_AAC_PK_SEL_1_0_8814B \ + (BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B \ + << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B) +#define BIT_CLEAR_XTAL_AAC_PK_SEL_1_0_8814B(x) \ + ((x) & (~BITS_XTAL_AAC_PK_SEL_1_0_8814B)) +#define BIT_GET_XTAL_AAC_PK_SEL_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B) & \ + BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B) +#define BIT_SET_XTAL_AAC_PK_SEL_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_AAC_PK_SEL_1_0_8814B(x) | \ + BIT_XTAL_AAC_PK_SEL_1_0_8814B(v)) + +#define BIT_EN_XTAL_AAC_PKDET_8814B BIT(24) +#define BIT_EN_XTAL_AAC_GM_8814B BIT(23) +#define BIT_XTAL_LPMODE_8814B BIT(22) + +#define BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B 19 +#define BIT_MASK_XTAL_SEL_TOK_2_0_8814B 0x7 +#define BIT_XTAL_SEL_TOK_2_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_2_0_8814B) \ + << BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B) +#define BITS_XTAL_SEL_TOK_2_0_8814B \ + (BIT_MASK_XTAL_SEL_TOK_2_0_8814B << BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B) +#define BIT_CLEAR_XTAL_SEL_TOK_2_0_8814B(x) \ + ((x) & (~BITS_XTAL_SEL_TOK_2_0_8814B)) +#define BIT_GET_XTAL_SEL_TOK_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B) & \ + BIT_MASK_XTAL_SEL_TOK_2_0_8814B) +#define BIT_SET_XTAL_SEL_TOK_2_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_2_0_8814B(x) | BIT_XTAL_SEL_TOK_2_0_8814B(v)) + +#define BIT_XQSEL_RF_AWAKE_V2_8814B BIT(18) +#define BIT_XQSEL_RF_INITIAL_V2_8814B BIT(17) +#define BIT_XTAL_DELAY_USB_V1_8814B BIT(16) +#define BIT_XTAL_DELAY_DIGI_V1_8814B BIT(15) +#define BIT_XTAL_DELAY_AFE_V1_8814B BIT(14) +#define BIT_XTAL_DRV_RF_LATCH_V3_8814B BIT(13) + +#define BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B 11 +#define BIT_MASK_XTAL_DRV_DIGI_1_0_8814B 0x3 +#define BIT_XTAL_DRV_DIGI_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_1_0_8814B) \ + << BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B) +#define BITS_XTAL_DRV_DIGI_1_0_8814B \ + (BIT_MASK_XTAL_DRV_DIGI_1_0_8814B << BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B) +#define BIT_CLEAR_XTAL_DRV_DIGI_1_0_8814B(x) \ + ((x) & (~BITS_XTAL_DRV_DIGI_1_0_8814B)) +#define BIT_GET_XTAL_DRV_DIGI_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B) & \ + BIT_MASK_XTAL_DRV_DIGI_1_0_8814B) +#define BIT_SET_XTAL_DRV_DIGI_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_1_0_8814B(x) | BIT_XTAL_DRV_DIGI_1_0_8814B(v)) + +#define BIT_XTAL_GATED_DIGIN_8814B BIT(10) +#define BIT_XTAL_GATED_DIGIP_8814B BIT(9) + +#define BIT_SHIFT_XTAL_DRV_USB_1_0_8814B 7 +#define BIT_MASK_XTAL_DRV_USB_1_0_8814B 0x3 +#define BIT_XTAL_DRV_USB_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_DRV_USB_1_0_8814B) \ + << BIT_SHIFT_XTAL_DRV_USB_1_0_8814B) +#define BITS_XTAL_DRV_USB_1_0_8814B \ + (BIT_MASK_XTAL_DRV_USB_1_0_8814B << BIT_SHIFT_XTAL_DRV_USB_1_0_8814B) +#define BIT_CLEAR_XTAL_DRV_USB_1_0_8814B(x) \ + ((x) & (~BITS_XTAL_DRV_USB_1_0_8814B)) +#define BIT_GET_XTAL_DRV_USB_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_USB_1_0_8814B) & \ + BIT_MASK_XTAL_DRV_USB_1_0_8814B) +#define BIT_SET_XTAL_DRV_USB_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_DRV_USB_1_0_8814B(x) | BIT_XTAL_DRV_USB_1_0_8814B(v)) + +#define BIT_XTAL_GATED_USBN_8814B BIT(6) +#define BIT_XTAL_GATED_USBP_8814B BIT(5) + +#define BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B 3 +#define BIT_MASK_XTAL_DRV_AFE_1_0_8814B 0x3 +#define BIT_XTAL_DRV_AFE_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_1_0_8814B) \ + << BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B) +#define BITS_XTAL_DRV_AFE_1_0_8814B \ + (BIT_MASK_XTAL_DRV_AFE_1_0_8814B << BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B) +#define BIT_CLEAR_XTAL_DRV_AFE_1_0_8814B(x) \ + ((x) & (~BITS_XTAL_DRV_AFE_1_0_8814B)) +#define BIT_GET_XTAL_DRV_AFE_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B) & \ + BIT_MASK_XTAL_DRV_AFE_1_0_8814B) +#define BIT_SET_XTAL_DRV_AFE_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_1_0_8814B(x) | BIT_XTAL_DRV_AFE_1_0_8814B(v)) + +#define BIT_XTAL_GATED_AFEN_8814B BIT(2) +#define BIT_XTAL_GATED_AFEP_8814B BIT(1) +#define BIT_XTAL_DRV_RF1_1_8814B BIT(0) + +/* 2 REG_ANAPAR_XTAL_2_8814B */ +#define BIT_XTAL_DRV_RF2_LATCH_8814B BIT(6) + +#define BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B 4 +#define BIT_MASK_XTAL_DRV_RF2_1_0_8814B 0x3 +#define BIT_XTAL_DRV_RF2_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_1_0_8814B) \ + << BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B) +#define BITS_XTAL_DRV_RF2_1_0_8814B \ + (BIT_MASK_XTAL_DRV_RF2_1_0_8814B << BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B) +#define BIT_CLEAR_XTAL_DRV_RF2_1_0_8814B(x) \ + ((x) & (~BITS_XTAL_DRV_RF2_1_0_8814B)) +#define BIT_GET_XTAL_DRV_RF2_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B) & \ + BIT_MASK_XTAL_DRV_RF2_1_0_8814B) +#define BIT_SET_XTAL_DRV_RF2_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_1_0_8814B(x) | BIT_XTAL_DRV_RF2_1_0_8814B(v)) + +#define BIT_XTAL_GATED_RF2N_8814B BIT(3) +#define BIT_XTAL_GATED_RF2P_8814B BIT(2) +#define BIT_XTAL_LDO_DI_8814B BIT(1) +#define BIT_XTAL_SEL_PWR_8814B BIT(0) + +/* 2 REG_ANAPAR_XTAL_AAC_8814B */ +#define BIT_EN_XTAL_AAC_TRIG_8814B BIT(28) +#define BIT_EN_XTAL_AAC_8814B BIT(27) +#define BIT_EN_XTAL_AAC_DIGI_8814B BIT(26) + +#define BIT_SHIFT_GM_MANUAL_4_0_8814B 21 +#define BIT_MASK_GM_MANUAL_4_0_8814B 0x1f +#define BIT_GM_MANUAL_4_0_8814B(x) \ + (((x) & BIT_MASK_GM_MANUAL_4_0_8814B) << BIT_SHIFT_GM_MANUAL_4_0_8814B) +#define BITS_GM_MANUAL_4_0_8814B \ + (BIT_MASK_GM_MANUAL_4_0_8814B << BIT_SHIFT_GM_MANUAL_4_0_8814B) +#define BIT_CLEAR_GM_MANUAL_4_0_8814B(x) ((x) & (~BITS_GM_MANUAL_4_0_8814B)) +#define BIT_GET_GM_MANUAL_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_GM_MANUAL_4_0_8814B) & BIT_MASK_GM_MANUAL_4_0_8814B) +#define BIT_SET_GM_MANUAL_4_0_8814B(x, v) \ + (BIT_CLEAR_GM_MANUAL_4_0_8814B(x) | BIT_GM_MANUAL_4_0_8814B(v)) + +#define BIT_SHIFT_GM_STUP_4_0_8814B 16 +#define BIT_MASK_GM_STUP_4_0_8814B 0x1f +#define BIT_GM_STUP_4_0_8814B(x) \ + (((x) & BIT_MASK_GM_STUP_4_0_8814B) << BIT_SHIFT_GM_STUP_4_0_8814B) +#define BITS_GM_STUP_4_0_8814B \ + (BIT_MASK_GM_STUP_4_0_8814B << BIT_SHIFT_GM_STUP_4_0_8814B) +#define BIT_CLEAR_GM_STUP_4_0_8814B(x) ((x) & (~BITS_GM_STUP_4_0_8814B)) +#define BIT_GET_GM_STUP_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_GM_STUP_4_0_8814B) & BIT_MASK_GM_STUP_4_0_8814B) +#define BIT_SET_GM_STUP_4_0_8814B(x, v) \ + (BIT_CLEAR_GM_STUP_4_0_8814B(x) | BIT_GM_STUP_4_0_8814B(v)) + +#define BIT_SHIFT_XTAL_CK_SET_2_0_8814B 13 +#define BIT_MASK_XTAL_CK_SET_2_0_8814B 0x7 +#define BIT_XTAL_CK_SET_2_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_CK_SET_2_0_8814B) \ + << BIT_SHIFT_XTAL_CK_SET_2_0_8814B) +#define BITS_XTAL_CK_SET_2_0_8814B \ + (BIT_MASK_XTAL_CK_SET_2_0_8814B << BIT_SHIFT_XTAL_CK_SET_2_0_8814B) +#define BIT_CLEAR_XTAL_CK_SET_2_0_8814B(x) ((x) & (~BITS_XTAL_CK_SET_2_0_8814B)) +#define BIT_GET_XTAL_CK_SET_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_CK_SET_2_0_8814B) & \ + BIT_MASK_XTAL_CK_SET_2_0_8814B) +#define BIT_SET_XTAL_CK_SET_2_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_CK_SET_2_0_8814B(x) | BIT_XTAL_CK_SET_2_0_8814B(v)) + +#define BIT_SHIFT_GM_INIT_4_0_8814B 8 +#define BIT_MASK_GM_INIT_4_0_8814B 0x1f +#define BIT_GM_INIT_4_0_8814B(x) \ + (((x) & BIT_MASK_GM_INIT_4_0_8814B) << BIT_SHIFT_GM_INIT_4_0_8814B) +#define BITS_GM_INIT_4_0_8814B \ + (BIT_MASK_GM_INIT_4_0_8814B << BIT_SHIFT_GM_INIT_4_0_8814B) +#define BIT_CLEAR_GM_INIT_4_0_8814B(x) ((x) & (~BITS_GM_INIT_4_0_8814B)) +#define BIT_GET_GM_INIT_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_GM_INIT_4_0_8814B) & BIT_MASK_GM_INIT_4_0_8814B) +#define BIT_SET_GM_INIT_4_0_8814B(x, v) \ + (BIT_CLEAR_GM_INIT_4_0_8814B(x) | BIT_GM_INIT_4_0_8814B(v)) + +#define BIT_GM_STEP_8814B BIT(7) + +#define BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B 2 +#define BIT_MASK_XAAC_GM_OFFSET_4_0_8814B 0x1f +#define BIT_XAAC_GM_OFFSET_4_0_8814B(x) \ + (((x) & BIT_MASK_XAAC_GM_OFFSET_4_0_8814B) \ + << BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B) +#define BITS_XAAC_GM_OFFSET_4_0_8814B \ + (BIT_MASK_XAAC_GM_OFFSET_4_0_8814B \ + << BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B) +#define BIT_CLEAR_XAAC_GM_OFFSET_4_0_8814B(x) \ + ((x) & (~BITS_XAAC_GM_OFFSET_4_0_8814B)) +#define BIT_GET_XAAC_GM_OFFSET_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B) & \ + BIT_MASK_XAAC_GM_OFFSET_4_0_8814B) +#define BIT_SET_XAAC_GM_OFFSET_4_0_8814B(x, v) \ + (BIT_CLEAR_XAAC_GM_OFFSET_4_0_8814B(x) | \ + BIT_XAAC_GM_OFFSET_4_0_8814B(v)) + +#define BIT_OFFSET_PLUS_8814B BIT(1) +#define BIT_RESET_N_8814B BIT(0) + +/* 2 REG_ANAPAR_XTAL_R_ONLY_8814B */ +#define BIT_XTAL_PKDET_OUT_8814B BIT(6) + +#define BIT_SHIFT_XTAL_GM_AAC_4_0_8814B 1 +#define BIT_MASK_XTAL_GM_AAC_4_0_8814B 0x1f +#define BIT_XTAL_GM_AAC_4_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_GM_AAC_4_0_8814B) \ + << BIT_SHIFT_XTAL_GM_AAC_4_0_8814B) +#define BITS_XTAL_GM_AAC_4_0_8814B \ + (BIT_MASK_XTAL_GM_AAC_4_0_8814B << BIT_SHIFT_XTAL_GM_AAC_4_0_8814B) +#define BIT_CLEAR_XTAL_GM_AAC_4_0_8814B(x) ((x) & (~BITS_XTAL_GM_AAC_4_0_8814B)) +#define BIT_GET_XTAL_GM_AAC_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_GM_AAC_4_0_8814B) & \ + BIT_MASK_XTAL_GM_AAC_4_0_8814B) +#define BIT_SET_XTAL_GM_AAC_4_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_GM_AAC_4_0_8814B(x) | BIT_XTAL_GM_AAC_4_0_8814B(v)) + +#define BIT_XAAC_READY_8814B BIT(0) + +/* 2 REG_CPHY_LDO_8814B */ + +#define BIT_SHIFT_CPHY_LDO_PD_8814B 12 +#define BIT_MASK_CPHY_LDO_PD_8814B 0x3 +#define BIT_CPHY_LDO_PD_8814B(x) \ + (((x) & BIT_MASK_CPHY_LDO_PD_8814B) << BIT_SHIFT_CPHY_LDO_PD_8814B) +#define BITS_CPHY_LDO_PD_8814B \ + (BIT_MASK_CPHY_LDO_PD_8814B << BIT_SHIFT_CPHY_LDO_PD_8814B) +#define BIT_CLEAR_CPHY_LDO_PD_8814B(x) ((x) & (~BITS_CPHY_LDO_PD_8814B)) +#define BIT_GET_CPHY_LDO_PD_8814B(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_PD_8814B) & BIT_MASK_CPHY_LDO_PD_8814B) +#define BIT_SET_CPHY_LDO_PD_8814B(x, v) \ + (BIT_CLEAR_CPHY_LDO_PD_8814B(x) | BIT_CPHY_LDO_PD_8814B(v)) + +#define BIT_SHIFT_CPHY_LDO_SR_8814B 10 +#define BIT_MASK_CPHY_LDO_SR_8814B 0x3 +#define BIT_CPHY_LDO_SR_8814B(x) \ + (((x) & BIT_MASK_CPHY_LDO_SR_8814B) << BIT_SHIFT_CPHY_LDO_SR_8814B) +#define BITS_CPHY_LDO_SR_8814B \ + (BIT_MASK_CPHY_LDO_SR_8814B << BIT_SHIFT_CPHY_LDO_SR_8814B) +#define BIT_CLEAR_CPHY_LDO_SR_8814B(x) ((x) & (~BITS_CPHY_LDO_SR_8814B)) +#define BIT_GET_CPHY_LDO_SR_8814B(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_SR_8814B) & BIT_MASK_CPHY_LDO_SR_8814B) +#define BIT_SET_CPHY_LDO_SR_8814B(x, v) \ + (BIT_CLEAR_CPHY_LDO_SR_8814B(x) | BIT_CPHY_LDO_SR_8814B(v)) + +#define BIT_SHIFT_CPHY_LDO_TUNEREF_8814B 8 +#define BIT_MASK_CPHY_LDO_TUNEREF_8814B 0x3 +#define BIT_CPHY_LDO_TUNEREF_8814B(x) \ + (((x) & BIT_MASK_CPHY_LDO_TUNEREF_8814B) \ + << BIT_SHIFT_CPHY_LDO_TUNEREF_8814B) +#define BITS_CPHY_LDO_TUNEREF_8814B \ + (BIT_MASK_CPHY_LDO_TUNEREF_8814B << BIT_SHIFT_CPHY_LDO_TUNEREF_8814B) +#define BIT_CLEAR_CPHY_LDO_TUNEREF_8814B(x) \ + ((x) & (~BITS_CPHY_LDO_TUNEREF_8814B)) +#define BIT_GET_CPHY_LDO_TUNEREF_8814B(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_TUNEREF_8814B) & \ + BIT_MASK_CPHY_LDO_TUNEREF_8814B) +#define BIT_SET_CPHY_LDO_TUNEREF_8814B(x, v) \ + (BIT_CLEAR_CPHY_LDO_TUNEREF_8814B(x) | BIT_CPHY_LDO_TUNEREF_8814B(v)) + +#define BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B 5 +#define BIT_MASK_CPHY_LDO_TUNE_VO_8814B 0x7 +#define BIT_CPHY_LDO_TUNE_VO_8814B(x) \ + (((x) & BIT_MASK_CPHY_LDO_TUNE_VO_8814B) \ + << BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B) +#define BITS_CPHY_LDO_TUNE_VO_8814B \ + (BIT_MASK_CPHY_LDO_TUNE_VO_8814B << BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B) +#define BIT_CLEAR_CPHY_LDO_TUNE_VO_8814B(x) \ + ((x) & (~BITS_CPHY_LDO_TUNE_VO_8814B)) +#define BIT_GET_CPHY_LDO_TUNE_VO_8814B(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B) & \ + BIT_MASK_CPHY_LDO_TUNE_VO_8814B) +#define BIT_SET_CPHY_LDO_TUNE_VO_8814B(x, v) \ + (BIT_CLEAR_CPHY_LDO_TUNE_VO_8814B(x) | BIT_CPHY_LDO_TUNE_VO_8814B(v)) + +#define BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B 2 +#define BIT_MASK_CPHY_LDO_OCP_VTH_8814B 0x7 +#define BIT_CPHY_LDO_OCP_VTH_8814B(x) \ + (((x) & BIT_MASK_CPHY_LDO_OCP_VTH_8814B) \ + << BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B) +#define BITS_CPHY_LDO_OCP_VTH_8814B \ + (BIT_MASK_CPHY_LDO_OCP_VTH_8814B << BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B) +#define BIT_CLEAR_CPHY_LDO_OCP_VTH_8814B(x) \ + ((x) & (~BITS_CPHY_LDO_OCP_VTH_8814B)) +#define BIT_GET_CPHY_LDO_OCP_VTH_8814B(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B) & \ + BIT_MASK_CPHY_LDO_OCP_VTH_8814B) +#define BIT_SET_CPHY_LDO_OCP_VTH_8814B(x, v) \ + (BIT_CLEAR_CPHY_LDO_OCP_VTH_8814B(x) | BIT_CPHY_LDO_OCP_VTH_8814B(v)) + +#define BIT_SHIFT_VREF_LDO_OK_8814B 0 +#define BIT_MASK_VREF_LDO_OK_8814B 0x3 +#define BIT_VREF_LDO_OK_8814B(x) \ + (((x) & BIT_MASK_VREF_LDO_OK_8814B) << BIT_SHIFT_VREF_LDO_OK_8814B) +#define BITS_VREF_LDO_OK_8814B \ + (BIT_MASK_VREF_LDO_OK_8814B << BIT_SHIFT_VREF_LDO_OK_8814B) +#define BIT_CLEAR_VREF_LDO_OK_8814B(x) ((x) & (~BITS_VREF_LDO_OK_8814B)) +#define BIT_GET_VREF_LDO_OK_8814B(x) \ + (((x) >> BIT_SHIFT_VREF_LDO_OK_8814B) & BIT_MASK_VREF_LDO_OK_8814B) +#define BIT_SET_VREF_LDO_OK_8814B(x, v) \ + (BIT_CLEAR_VREF_LDO_OK_8814B(x) | BIT_VREF_LDO_OK_8814B(v)) + +/* 2 REG_CPHY_BG_8814B */ + +#define BIT_SHIFT_BG_8814B 0 +#define BIT_MASK_BG_8814B 0x7 +#define BIT_BG_8814B(x) (((x) & BIT_MASK_BG_8814B) << BIT_SHIFT_BG_8814B) +#define BITS_BG_8814B (BIT_MASK_BG_8814B << BIT_SHIFT_BG_8814B) +#define BIT_CLEAR_BG_8814B(x) ((x) & (~BITS_BG_8814B)) +#define BIT_GET_BG_8814B(x) (((x) >> BIT_SHIFT_BG_8814B) & BIT_MASK_BG_8814B) +#define BIT_SET_BG_8814B(x, v) (BIT_CLEAR_BG_8814B(x) | BIT_BG_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_HIMR_4_8814B */ +#define BIT_TXBCN_OK_PORT4_8814B BIT(31) +#define BIT_TXBCN_OK_PORT3_8814B BIT(30) +#define BIT_TXBCN_OK_PORT2_8814B BIT(29) +#define BIT_TXBCN_OK_PORT1_8814B BIT(28) +#define BIT_TXBCN15OK_8814B BIT(23) +#define BIT_TXBCN14OK_8814B BIT(22) +#define BIT_TXBCN13OK_8814B BIT(21) +#define BIT_TXBCN12OK_8814B BIT(20) +#define BIT_TXBCN11OK_8814B BIT(19) +#define BIT_TXBCN10OK_8814B BIT(18) +#define BIT_TXBCN9OK_8814B BIT(17) +#define BIT_TXBCN8OK_8814B BIT(16) +#define BIT_BCNDERR_PORT4_8814B BIT(15) +#define BIT_BCNDERR_PORT3_8814B BIT(14) +#define BIT_BCNDERR_PORT2_8814B BIT(13) +#define BIT_BCNDERR_PORT1_8814B BIT(12) +#define BIT_TXBCN15ERR_8814B BIT(7) +#define BIT_TXBCN14ERR_8814B BIT(6) +#define BIT_TXBCN13ERR_8814B BIT(5) +#define BIT_TXBCN12ERR_8814B BIT(4) +#define BIT_TXBCN11ERR_8814B BIT(3) +#define BIT_TXBCN10ERR_8814B BIT(2) +#define BIT_TXBCN9ERR_8814B BIT(1) +#define BIT_TXBCN8ERR_8814B BIT(0) + +/* 2 REG_HISR_4_8814B */ +#define BIT_TXBCN_OK_PORT4_8814B BIT(31) +#define BIT_TXBCN_OK_PORT3_8814B BIT(30) +#define BIT_TXBCN_OK_PORT2_8814B BIT(29) +#define BIT_TXBCN_OK_PORT1_8814B BIT(28) +#define BIT_TXBCN15OK_8814B BIT(23) +#define BIT_TXBCN14OK_8814B BIT(22) +#define BIT_TXBCN13OK_8814B BIT(21) +#define BIT_TXBCN12OK_8814B BIT(20) +#define BIT_TXBCN11OK_8814B BIT(19) +#define BIT_TXBCN10OK_8814B BIT(18) +#define BIT_TXBCN9OK_8814B BIT(17) +#define BIT_TXBCN8OK_8814B BIT(16) +#define BIT_BCNDERR_PORT4_8814B BIT(15) +#define BIT_BCNDERR_PORT3_8814B BIT(14) +#define BIT_BCNDERR_PORT2_8814B BIT(13) +#define BIT_BCNDERR_PORT1_8814B BIT(12) +#define BIT_TXBCN15ERR_8814B BIT(7) +#define BIT_TXBCN14ERR_8814B BIT(6) +#define BIT_TXBCN13ERR_8814B BIT(5) +#define BIT_TXBCN12ERR_8814B BIT(4) +#define BIT_TXBCN11ERR_8814B BIT(3) +#define BIT_TXBCN10ERR_8814B BIT(2) +#define BIT_TXBCN9ERR_8814B BIT(1) +#define BIT_TXBCN8ERR_8814B BIT(0) + +/* 2 REG_HIMR_5_8814B */ +#define BIT_BCNDMAINT15_8814B BIT(23) +#define BIT_BCNDMAINT14_8814B BIT(22) +#define BIT_BCNDMAINT13_8814B BIT(21) +#define BIT_BCNDMAINT12_8814B BIT(20) +#define BIT_BCNDMAINT11_8814B BIT(19) +#define BIT_BCNDMAINT10_8814B BIT(18) +#define BIT_BCNDMAINT9_8814B BIT(17) +#define BIT_BCNDMAINT8_8814B BIT(16) +#define BIT_BCNDERR_PORT4_8814B BIT(15) +#define BIT_BCNDERR_PORT3_8814B BIT(14) +#define BIT_BCNDERR_PORT2_8814B BIT(13) +#define BIT_BCNDERR_PORT1_8814B BIT(12) +#define BIT_BCNDERR15_8814B BIT(7) +#define BIT_BCNDERR14_8814B BIT(6) +#define BIT_BCNDERR13_8814B BIT(5) +#define BIT_BCNDERR12_8814B BIT(4) +#define BIT_BCNDERR11_8814B BIT(3) +#define BIT_BCNDERR10_8814B BIT(2) +#define BIT_BCNDERR9_8814B BIT(1) +#define BIT_BCNDERR8_8814B BIT(0) + +/* 2 REG_HISR_5_8814B */ +#define BIT_BCNDMAINT15_8814B BIT(23) +#define BIT_BCNDMAINT14_8814B BIT(22) +#define BIT_BCNDMAINT13_8814B BIT(21) +#define BIT_BCNDMAINT12_8814B BIT(20) +#define BIT_BCNDMAINT11_8814B BIT(19) +#define BIT_BCNDMAINT10_8814B BIT(18) +#define BIT_BCNDMAINT9_8814B BIT(17) +#define BIT_BCNDMAINT8_8814B BIT(16) +#define BIT_BCNDERR_PORT4_8814B BIT(15) +#define BIT_BCNDERR_PORT3_8814B BIT(14) +#define BIT_BCNDERR_PORT2_8814B BIT(13) +#define BIT_BCNDERR_PORT1_8814B BIT(12) +#define BIT_BCNDERR15_8814B BIT(7) +#define BIT_BCNDERR14_8814B BIT(6) +#define BIT_BCNDERR13_8814B BIT(5) +#define BIT_BCNDERR12_8814B BIT(4) +#define BIT_BCNDERR11_8814B BIT(3) +#define BIT_BCNDERR10_8814B BIT(2) +#define BIT_BCNDERR9_8814B BIT(1) +#define BIT_BCNDERR8_8814B BIT(0) /* 2 REG_SYS_CFG5_8814B */ #define BIT_LPS_STATUS_8814B BIT(3) @@ -1799,6 +3461,48 @@ #define BIT_HCI_TXDMA_ALLOW_8814B BIT(1) #define BIT_FW_CTRL_HCI_TXDMA_EN_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_HIMR_6_8814B */ +#define BIT_ATIMEND_PORT4_8814B BIT(31) +#define BIT_ATIMEND_PORT3_8814B BIT(30) +#define BIT_ATIMEND_PORT2_8814B BIT(29) +#define BIT_ATIMEND_PORT1_8814B BIT(28) +#define BIT_ATIMEND15_8814B BIT(23) +#define BIT_ATIMEND14_8814B BIT(22) +#define BIT_ATIMEND13_8814B BIT(21) +#define BIT_ATIMEND12_8814B BIT(20) +#define BIT_ATIMEND11_8814B BIT(19) +#define BIT_ATIMEND10_8814B BIT(18) +#define BIT_ATIMEND9_8814B BIT(17) +#define BIT_ATIMEND8_8814B BIT(16) +#define BIT_PS_TIMER_EARLY_INT_5_8814B BIT(5) +#define BIT_PS_TIMER_EARLY_INT_4_8814B BIT(4) +#define BIT_PS_TIMER_EARLY_INT_3_8814B BIT(3) +#define BIT_PS_TIMER_EARLY_INT_2_8814B BIT(2) +#define BIT_PS_TIMER_EARLY_INT_1_8814B BIT(1) +#define BIT_PS_TIMER_EARLY_INT_0_8814B BIT(0) + +/* 2 REG_HISR_6_8814B */ +#define BIT_ATIMEND_PORT4_8814B BIT(31) +#define BIT_ATIMEND_PORT3_8814B BIT(30) +#define BIT_ATIMEND_PORT2_8814B BIT(29) +#define BIT_ATIMEND_PORT1_8814B BIT(28) +#define BIT_ATIMEND15_8814B BIT(23) +#define BIT_ATIMEND14_8814B BIT(22) +#define BIT_ATIMEND13_8814B BIT(21) +#define BIT_ATIMEND12_8814B BIT(20) +#define BIT_ATIMEND11_8814B BIT(19) +#define BIT_ATIMEND10_8814B BIT(18) +#define BIT_ATIMEND9_8814B BIT(17) +#define BIT_ATIMEND8_8814B BIT(16) +#define BIT_PS_TIMER_EARLY_INT_5_8814B BIT(5) +#define BIT_PS_TIMER_EARLY_INT_4_8814B BIT(4) +#define BIT_PS_TIMER_EARLY_INT_3_8814B BIT(3) +#define BIT_PS_TIMER_EARLY_INT_2_8814B BIT(2) +#define BIT_PS_TIMER_EARLY_INT_1_8814B BIT(1) +#define BIT_PS_TIMER_EARLY_INT_0_8814B BIT(0) + /* 2 REG_CPU_DMEM_CON_8814B */ #define BIT_WDT_AUTO_MODE_8814B BIT(22) #define BIT_WDT_PLATFORM_EN_8814B BIT(21) @@ -1808,22 +3512,146 @@ #define BIT_MAC_PORT_IDLE_8814B BIT(17) #define BIT_WL_PLATFORM_RST_8814B BIT(16) #define BIT_WL_SECURITY_CLK_8814B BIT(15) +#define BIT_DDMA_EN_8814B BIT(8) #define BIT_SHIFT_CPU_DMEM_CON_8814B 0 #define BIT_MASK_CPU_DMEM_CON_8814B 0xff -#define BIT_CPU_DMEM_CON_8814B(x) (((x) & BIT_MASK_CPU_DMEM_CON_8814B) << BIT_SHIFT_CPU_DMEM_CON_8814B) -#define BIT_GET_CPU_DMEM_CON_8814B(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8814B) & BIT_MASK_CPU_DMEM_CON_8814B) - +#define BIT_CPU_DMEM_CON_8814B(x) \ + (((x) & BIT_MASK_CPU_DMEM_CON_8814B) << BIT_SHIFT_CPU_DMEM_CON_8814B) +#define BITS_CPU_DMEM_CON_8814B \ + (BIT_MASK_CPU_DMEM_CON_8814B << BIT_SHIFT_CPU_DMEM_CON_8814B) +#define BIT_CLEAR_CPU_DMEM_CON_8814B(x) ((x) & (~BITS_CPU_DMEM_CON_8814B)) +#define BIT_GET_CPU_DMEM_CON_8814B(x) \ + (((x) >> BIT_SHIFT_CPU_DMEM_CON_8814B) & BIT_MASK_CPU_DMEM_CON_8814B) +#define BIT_SET_CPU_DMEM_CON_8814B(x, v) \ + (BIT_CLEAR_CPU_DMEM_CON_8814B(x) | BIT_CPU_DMEM_CON_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_BOOT_REASON_8814B */ -#define BIT_SHIFT_BOOT_REASON_8814B 0 -#define BIT_MASK_BOOT_REASON_8814B 0x7 -#define BIT_BOOT_REASON_8814B(x) (((x) & BIT_MASK_BOOT_REASON_8814B) << BIT_SHIFT_BOOT_REASON_8814B) -#define BIT_GET_BOOT_REASON_8814B(x) (((x) >> BIT_SHIFT_BOOT_REASON_8814B) & BIT_MASK_BOOT_REASON_8814B) +#define BIT_SHIFT_BOOT_REASON_V1_8814B 0 +#define BIT_MASK_BOOT_REASON_V1_8814B 0x7 +#define BIT_BOOT_REASON_V1_8814B(x) \ + (((x) & BIT_MASK_BOOT_REASON_V1_8814B) \ + << BIT_SHIFT_BOOT_REASON_V1_8814B) +#define BITS_BOOT_REASON_V1_8814B \ + (BIT_MASK_BOOT_REASON_V1_8814B << BIT_SHIFT_BOOT_REASON_V1_8814B) +#define BIT_CLEAR_BOOT_REASON_V1_8814B(x) ((x) & (~BITS_BOOT_REASON_V1_8814B)) +#define BIT_GET_BOOT_REASON_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BOOT_REASON_V1_8814B) & \ + BIT_MASK_BOOT_REASON_V1_8814B) +#define BIT_SET_BOOT_REASON_V1_8814B(x, v) \ + (BIT_CLEAR_BOOT_REASON_V1_8814B(x) | BIT_BOOT_REASON_V1_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_DATA_CPU_CTL0_8814B */ +#define BIT_DATA_FW_READY_8814B BIT(31) +#define BIT_WDT_SYS_RST_8814B BIT(13) +#define BIT_WDT_ENABLE_8814B BIT(12) + +#define BIT_SHIFT_BOOT_SEL_8814B 6 +#define BIT_MASK_BOOT_SEL_8814B 0x3 +#define BIT_BOOT_SEL_8814B(x) \ + (((x) & BIT_MASK_BOOT_SEL_8814B) << BIT_SHIFT_BOOT_SEL_8814B) +#define BITS_BOOT_SEL_8814B \ + (BIT_MASK_BOOT_SEL_8814B << BIT_SHIFT_BOOT_SEL_8814B) +#define BIT_CLEAR_BOOT_SEL_8814B(x) ((x) & (~BITS_BOOT_SEL_8814B)) +#define BIT_GET_BOOT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_BOOT_SEL_8814B) & BIT_MASK_BOOT_SEL_8814B) +#define BIT_SET_BOOT_SEL_8814B(x, v) \ + (BIT_CLEAR_BOOT_SEL_8814B(x) | BIT_BOOT_SEL_8814B(v)) + +#define BIT_CLK_SEL_8814B BIT(4) +#define BIT_DATA_PLATFORM_RST_8814B BIT(1) +#define BIT_DATA_CPU_RST_8814B BIT(0) + +/* 2 REG_DATA_CPU_CTL1_8814B */ +#define BIT_HOST_INTERFACE_IO_PATH_8814B BIT(7) +#define BIT_EN_TXDMA_OFLD_8814B BIT(6) +#define BIT_EN_RXDMA_OFLD_8814B BIT(5) +#define BIT_EN_HCI_DMA_TX_8814B BIT(4) +#define BIT_EN_HCI_DMA_RX_8814B BIT(3) +#define BIT_EN_AXI_DMA_TX_8814B BIT(2) +#define BIT_EN_AXI_DMA_RX_8814B BIT(1) +#define BIT_EN_PKT_ENG_8814B BIT(0) + +/* 2 REG_TXDMA_STOP_HIMR_8814B */ + +#define BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B 0 +#define BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B 0x1ffff +#define BIT_NTH_TXDMA_STOP_INT_MSK_8814B(x) \ + (((x) & BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B) \ + << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B) +#define BITS_NTH_TXDMA_STOP_INT_MSK_8814B \ + (BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B \ + << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B) +#define BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK_8814B(x) \ + ((x) & (~BITS_NTH_TXDMA_STOP_INT_MSK_8814B)) +#define BIT_GET_NTH_TXDMA_STOP_INT_MSK_8814B(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B) & \ + BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B) +#define BIT_SET_NTH_TXDMA_STOP_INT_MSK_8814B(x, v) \ + (BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK_8814B(x) | \ + BIT_NTH_TXDMA_STOP_INT_MSK_8814B(v)) + +/* 2 REG_TXDMA_STOP_HISR_8814B */ + +#define BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B 0 +#define BIT_MASK_NTH_TXDMA_STOP_INT_8814B 0x1ffff +#define BIT_NTH_TXDMA_STOP_INT_8814B(x) \ + (((x) & BIT_MASK_NTH_TXDMA_STOP_INT_8814B) \ + << BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B) +#define BITS_NTH_TXDMA_STOP_INT_8814B \ + (BIT_MASK_NTH_TXDMA_STOP_INT_8814B \ + << BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B) +#define BIT_CLEAR_NTH_TXDMA_STOP_INT_8814B(x) \ + ((x) & (~BITS_NTH_TXDMA_STOP_INT_8814B)) +#define BIT_GET_NTH_TXDMA_STOP_INT_8814B(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B) & \ + BIT_MASK_NTH_TXDMA_STOP_INT_8814B) +#define BIT_SET_NTH_TXDMA_STOP_INT_8814B(x, v) \ + (BIT_CLEAR_NTH_TXDMA_STOP_INT_8814B(x) | \ + BIT_NTH_TXDMA_STOP_INT_8814B(v)) + +/* 2 REG_TXDMA_START_HIMR_8814B */ + +#define BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B 0 +#define BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B 0x1ffff +#define BIT_NTH_TXDMA_START_INT_MSK_8814B(x) \ + (((x) & BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B) \ + << BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B) +#define BITS_NTH_TXDMA_START_INT_MSK_8814B \ + (BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B \ + << BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B) +#define BIT_CLEAR_NTH_TXDMA_START_INT_MSK_8814B(x) \ + ((x) & (~BITS_NTH_TXDMA_START_INT_MSK_8814B)) +#define BIT_GET_NTH_TXDMA_START_INT_MSK_8814B(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B) & \ + BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B) +#define BIT_SET_NTH_TXDMA_START_INT_MSK_8814B(x, v) \ + (BIT_CLEAR_NTH_TXDMA_START_INT_MSK_8814B(x) | \ + BIT_NTH_TXDMA_START_INT_MSK_8814B(v)) + +/* 2 REG_TXDMA_START_HISR_8814B */ + +#define BIT_SHIFT_NTH_TXDMA_START_INT_8814B 0 +#define BIT_MASK_NTH_TXDMA_START_INT_8814B 0x1ffff +#define BIT_NTH_TXDMA_START_INT_8814B(x) \ + (((x) & BIT_MASK_NTH_TXDMA_START_INT_8814B) \ + << BIT_SHIFT_NTH_TXDMA_START_INT_8814B) +#define BITS_NTH_TXDMA_START_INT_8814B \ + (BIT_MASK_NTH_TXDMA_START_INT_8814B \ + << BIT_SHIFT_NTH_TXDMA_START_INT_8814B) +#define BIT_CLEAR_NTH_TXDMA_START_INT_8814B(x) \ + ((x) & (~BITS_NTH_TXDMA_START_INT_8814B)) +#define BIT_GET_NTH_TXDMA_START_INT_8814B(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_8814B) & \ + BIT_MASK_NTH_TXDMA_START_INT_8814B) +#define BIT_SET_NTH_TXDMA_START_INT_8814B(x, v) \ + (BIT_CLEAR_NTH_TXDMA_START_INT_8814B(x) | \ + BIT_NTH_TXDMA_START_INT_8814B(v)) /* 2 REG_NFCPAD_CTRL_8814B */ #define BIT_PAD_SHUTDW_8814B BIT(18) @@ -1836,30 +3664,48 @@ #define BIT_SHIFT_NFCPAD_IO_SEL_8814B 8 #define BIT_MASK_NFCPAD_IO_SEL_8814B 0xf -#define BIT_NFCPAD_IO_SEL_8814B(x) (((x) & BIT_MASK_NFCPAD_IO_SEL_8814B) << BIT_SHIFT_NFCPAD_IO_SEL_8814B) -#define BIT_GET_NFCPAD_IO_SEL_8814B(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8814B) & BIT_MASK_NFCPAD_IO_SEL_8814B) - - +#define BIT_NFCPAD_IO_SEL_8814B(x) \ + (((x) & BIT_MASK_NFCPAD_IO_SEL_8814B) << BIT_SHIFT_NFCPAD_IO_SEL_8814B) +#define BITS_NFCPAD_IO_SEL_8814B \ + (BIT_MASK_NFCPAD_IO_SEL_8814B << BIT_SHIFT_NFCPAD_IO_SEL_8814B) +#define BIT_CLEAR_NFCPAD_IO_SEL_8814B(x) ((x) & (~BITS_NFCPAD_IO_SEL_8814B)) +#define BIT_GET_NFCPAD_IO_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8814B) & BIT_MASK_NFCPAD_IO_SEL_8814B) +#define BIT_SET_NFCPAD_IO_SEL_8814B(x, v) \ + (BIT_CLEAR_NFCPAD_IO_SEL_8814B(x) | BIT_NFCPAD_IO_SEL_8814B(v)) #define BIT_SHIFT_NFCPAD_OUT_8814B 4 #define BIT_MASK_NFCPAD_OUT_8814B 0xf -#define BIT_NFCPAD_OUT_8814B(x) (((x) & BIT_MASK_NFCPAD_OUT_8814B) << BIT_SHIFT_NFCPAD_OUT_8814B) -#define BIT_GET_NFCPAD_OUT_8814B(x) (((x) >> BIT_SHIFT_NFCPAD_OUT_8814B) & BIT_MASK_NFCPAD_OUT_8814B) - - +#define BIT_NFCPAD_OUT_8814B(x) \ + (((x) & BIT_MASK_NFCPAD_OUT_8814B) << BIT_SHIFT_NFCPAD_OUT_8814B) +#define BITS_NFCPAD_OUT_8814B \ + (BIT_MASK_NFCPAD_OUT_8814B << BIT_SHIFT_NFCPAD_OUT_8814B) +#define BIT_CLEAR_NFCPAD_OUT_8814B(x) ((x) & (~BITS_NFCPAD_OUT_8814B)) +#define BIT_GET_NFCPAD_OUT_8814B(x) \ + (((x) >> BIT_SHIFT_NFCPAD_OUT_8814B) & BIT_MASK_NFCPAD_OUT_8814B) +#define BIT_SET_NFCPAD_OUT_8814B(x, v) \ + (BIT_CLEAR_NFCPAD_OUT_8814B(x) | BIT_NFCPAD_OUT_8814B(v)) #define BIT_SHIFT_NFCPAD_IN_8814B 0 #define BIT_MASK_NFCPAD_IN_8814B 0xf -#define BIT_NFCPAD_IN_8814B(x) (((x) & BIT_MASK_NFCPAD_IN_8814B) << BIT_SHIFT_NFCPAD_IN_8814B) -#define BIT_GET_NFCPAD_IN_8814B(x) (((x) >> BIT_SHIFT_NFCPAD_IN_8814B) & BIT_MASK_NFCPAD_IN_8814B) - +#define BIT_NFCPAD_IN_8814B(x) \ + (((x) & BIT_MASK_NFCPAD_IN_8814B) << BIT_SHIFT_NFCPAD_IN_8814B) +#define BITS_NFCPAD_IN_8814B \ + (BIT_MASK_NFCPAD_IN_8814B << BIT_SHIFT_NFCPAD_IN_8814B) +#define BIT_CLEAR_NFCPAD_IN_8814B(x) ((x) & (~BITS_NFCPAD_IN_8814B)) +#define BIT_GET_NFCPAD_IN_8814B(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IN_8814B) & BIT_MASK_NFCPAD_IN_8814B) +#define BIT_SET_NFCPAD_IN_8814B(x, v) \ + (BIT_CLEAR_NFCPAD_IN_8814B(x) | BIT_NFCPAD_IN_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_HIMR2_8814B */ #define BIT_BCNDMAINT_P4_MSK_8814B BIT(31) #define BIT_BCNDMAINT_P3_MSK_8814B BIT(30) #define BIT_BCNDMAINT_P2_MSK_8814B BIT(29) #define BIT_BCNDMAINT_P1_MSK_8814B BIT(28) +#define BIT_SCH_PHY_TXOP_SIFS_INT_MSK_8814B BIT(23) #define BIT_ATIMEND7_MSK_8814B BIT(22) #define BIT_ATIMEND6_MSK_8814B BIT(21) #define BIT_ATIMEND5_MSK_8814B BIT(20) @@ -1887,6 +3733,7 @@ #define BIT_BCNDMAINT_P3_8814B BIT(30) #define BIT_BCNDMAINT_P2_8814B BIT(29) #define BIT_BCNDMAINT_P1_8814B BIT(28) +#define BIT_SCH_PHY_TXOP_SIFS_INT_8814B BIT(23) #define BIT_ATIMEND7_8814B BIT(22) #define BIT_ATIMEND6_8814B BIT(21) #define BIT_ATIMEND5_8814B BIT(20) @@ -1910,86 +3757,141 @@ #define BIT_TXBCN1ERR_8814B BIT(0) /* 2 REG_HIMR3_8814B */ +#define BIT_GTINT12_MSK_8814B BIT(24) +#define BIT_GTINT11_MSK_8814B BIT(23) +#define BIT_GTINT10_MSK_8814B BIT(22) +#define BIT_GTINT9_MSK_8814B BIT(21) +#define BIT_RX_DESC_BUF_FULL_MSK_8814B BIT(20) +#define BIT_CPHY_LDO_OCP_DET_INT_MSK_8814B BIT(19) #define BIT_WDT_PLATFORM_INT_MSK_8814B BIT(18) #define BIT_WDT_CPU_INT_MSK_8814B BIT(17) #define BIT_SETH2CDOK_MASK_8814B BIT(16) #define BIT_H2C_CMD_FULL_MASK_8814B BIT(15) -#define BIT_PWR_INT_127_MASK_8814B BIT(14) +#define BIT_PKT_TRANS_ERR_MASK_8814B BIT(14) #define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8814B BIT(13) #define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8814B BIT(12) #define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8814B BIT(11) #define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8814B BIT(10) #define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8814B BIT(9) -#define BIT_PWR_INT_127_MASK_V1_8814B BIT(8) -#define BIT_PWR_INT_126TO96_MASK_8814B BIT(7) +#define BIT_SEARCH_FAIL_MSK_8814B BIT(8) +#define BIT_PWR_INT_127TO96_MASK_8814B BIT(7) #define BIT_PWR_INT_95TO64_MASK_8814B BIT(6) #define BIT_PWR_INT_63TO32_MASK_8814B BIT(5) #define BIT_PWR_INT_31TO0_MASK_8814B BIT(4) +#define BIT_RX_DMA_STUCK_MSK_8814B BIT(3) +#define BIT_TX_DMA_STUCK_MSK_8814B BIT(2) #define BIT_DDMA0_LP_INT_MSK_8814B BIT(1) #define BIT_DDMA0_HP_INT_MSK_8814B BIT(0) /* 2 REG_HISR3_8814B */ +#define BIT_GTINT12_8814B BIT(24) +#define BIT_GTINT11_8814B BIT(23) +#define BIT_GTINT10_8814B BIT(22) +#define BIT_GTINT9_8814B BIT(21) +#define BIT_RX_DESC_BUF_FULL_8814B BIT(20) +#define BIT_CPHY_LDO_OCP_DET_INT_8814B BIT(19) #define BIT_WDT_PLATFORM_INT_8814B BIT(18) #define BIT_WDT_CPU_INT_8814B BIT(17) #define BIT_SETH2CDOK_8814B BIT(16) #define BIT_H2C_CMD_FULL_8814B BIT(15) -#define BIT_PWR_INT_127_8814B BIT(14) +#define BIT_PKT_TRANS_ERR_8814B BIT(14) #define BIT_TXSHORTCUT_TXDESUPDATEOK_8814B BIT(13) #define BIT_TXSHORTCUT_BKUPDATEOK_8814B BIT(12) #define BIT_TXSHORTCUT_BEUPDATEOK_8814B BIT(11) #define BIT_TXSHORTCUT_VIUPDATEOK_8814B BIT(10) #define BIT_TXSHORTCUT_VOUPDATEOK_8814B BIT(9) -#define BIT_PWR_INT_127_V1_8814B BIT(8) -#define BIT_PWR_INT_126TO96_8814B BIT(7) +#define BIT_SEARCH_FAIL_8814B BIT(8) +#define BIT_PWR_INT_127TO96_8814B BIT(7) #define BIT_PWR_INT_95TO64_8814B BIT(6) #define BIT_PWR_INT_63TO32_8814B BIT(5) #define BIT_PWR_INT_31TO0_8814B BIT(4) +#define BIT_RX_DMA_STUCK_8814B BIT(3) +#define BIT_TX_DMA_STUCK_8814B BIT(2) #define BIT_DDMA0_LP_INT_8814B BIT(1) #define BIT_DDMA0_HP_INT_8814B BIT(0) /* 2 REG_SW_MDIO_8814B */ #define BIT_DIS_TIMEOUT_IO_8814B BIT(24) -/* 2 REG_SW_FLUSH_8814B */ -#define BIT_FLUSH_HOLDN_EN_8814B BIT(25) -#define BIT_FLUSH_WR_EN_8814B BIT(24) -#define BIT_SW_FLASH_CONTROL_8814B BIT(23) -#define BIT_SW_FLASH_WEN_E_8814B BIT(19) -#define BIT_SW_FLASH_HOLDN_E_8814B BIT(18) -#define BIT_SW_FLASH_SO_E_8814B BIT(17) -#define BIT_SW_FLASH_SI_E_8814B BIT(16) -#define BIT_SW_FLASH_SK_O_8814B BIT(13) -#define BIT_SW_FLASH_CEN_O_8814B BIT(12) -#define BIT_SW_FLASH_WEN_O_8814B BIT(11) -#define BIT_SW_FLASH_HOLDN_O_8814B BIT(10) -#define BIT_SW_FLASH_SO_O_8814B BIT(9) -#define BIT_SW_FLASH_SI_O_8814B BIT(8) -#define BIT_SW_FLASH_WEN_I_8814B BIT(3) -#define BIT_SW_FLASH_HOLDN_I_8814B BIT(2) -#define BIT_SW_FLASH_SO_I_8814B BIT(1) -#define BIT_SW_FLASH_SI_I_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_HIMR_7_8814B */ +#define BIT_DATA_CPU_WDT_INT_MSK_8814B BIT(31) +#define BIT_OFLD_TXDMA_ERR_MSK_8814B BIT(30) +#define BIT_OFLD_TXDMA_FULL_MSK_8814B BIT(29) +#define BIT_OFLD_RXDMA_OVR_MSK_8814B BIT(28) +#define BIT_OFLD_RXDMA_ERR_MSK_8814B BIT(27) +#define BIT_OFLD_RXDMA_DES_UA_MSK_8814B BIT(26) +#define BIT_TXDMAOK_CHANNEL_16_MSK_8814B BIT(16) +#define BIT_TXDMAOK_CHANNEL_13_MSK_8814B BIT(13) +#define BIT_TXDMAOK_CHANNEL_12_MSK_8814B BIT(12) +#define BIT_TXDMAOK_CHANNEL_11_MSK_8814B BIT(11) +#define BIT_TXDMAOK_CHANNEL_10_MSK_8814B BIT(10) +#define BIT_TXDMAOK_CHANNEL_9_MSK_8814B BIT(9) +#define BIT_TXDMAOK_CHANNEL_8_MSK_8814B BIT(8) +#define BIT_TXDMAOK_CHANNEL_7_MSK_8814B BIT(7) +#define BIT_TXDMAOK_CHANNEL_6_MSK_8814B BIT(6) +#define BIT_TXDMAOK_CHANNEL_5_MSK_8814B BIT(5) +#define BIT_TXDMAOK_CHANNEL_4_MSK_8814B BIT(4) + +/* 2 REG_HISR_7_8814B */ +#define BIT_DATA_CPU_WDT_INT_8814B BIT(31) +#define BIT_OFLD_TXDMA_ERR_8814B BIT(30) +#define BIT_OFLD_TXDMA_FULL_8814B BIT(29) +#define BIT_OFLD_RXDMA_OVR_8814B BIT(28) +#define BIT_OFLD_RXDMA_ERR_8814B BIT(27) +#define BIT_OFLD_RXDMA_DES_UA_8814B BIT(26) +#define BIT_TXDMAOK_CHANNEL_16_8814B BIT(16) +#define BIT_TXDMAOK_CHANNEL_13_8814B BIT(13) +#define BIT_TXDMAOK_CHANNEL_12_8814B BIT(12) +#define BIT_TXDMAOK_CHANNEL_11_8814B BIT(11) +#define BIT_TXDMAOK_CHANNEL_10_8814B BIT(10) +#define BIT_TXDMAOK_CHANNEL_9_8814B BIT(9) +#define BIT_TXDMAOK_CHANNEL_8_8814B BIT(8) +#define BIT_TXDMAOK_CHANNEL_7_8814B BIT(7) +#define BIT_TXDMAOK_CHANNEL_6_8814B BIT(6) +#define BIT_TXDMAOK_CHANNEL_5_8814B BIT(5) +#define BIT_TXDMAOK_CHANNEL_4_8814B BIT(4) /* 2 REG_H2C_PKT_READADDR_8814B */ #define BIT_SHIFT_H2C_PKT_READADDR_8814B 0 #define BIT_MASK_H2C_PKT_READADDR_8814B 0x3ffff -#define BIT_H2C_PKT_READADDR_8814B(x) (((x) & BIT_MASK_H2C_PKT_READADDR_8814B) << BIT_SHIFT_H2C_PKT_READADDR_8814B) -#define BIT_GET_H2C_PKT_READADDR_8814B(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8814B) & BIT_MASK_H2C_PKT_READADDR_8814B) - - +#define BIT_H2C_PKT_READADDR_8814B(x) \ + (((x) & BIT_MASK_H2C_PKT_READADDR_8814B) \ + << BIT_SHIFT_H2C_PKT_READADDR_8814B) +#define BITS_H2C_PKT_READADDR_8814B \ + (BIT_MASK_H2C_PKT_READADDR_8814B << BIT_SHIFT_H2C_PKT_READADDR_8814B) +#define BIT_CLEAR_H2C_PKT_READADDR_8814B(x) \ + ((x) & (~BITS_H2C_PKT_READADDR_8814B)) +#define BIT_GET_H2C_PKT_READADDR_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8814B) & \ + BIT_MASK_H2C_PKT_READADDR_8814B) +#define BIT_SET_H2C_PKT_READADDR_8814B(x, v) \ + (BIT_CLEAR_H2C_PKT_READADDR_8814B(x) | BIT_H2C_PKT_READADDR_8814B(v)) /* 2 REG_H2C_PKT_WRITEADDR_8814B */ #define BIT_SHIFT_H2C_PKT_WRITEADDR_8814B 0 #define BIT_MASK_H2C_PKT_WRITEADDR_8814B 0x3ffff -#define BIT_H2C_PKT_WRITEADDR_8814B(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8814B) << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) -#define BIT_GET_H2C_PKT_WRITEADDR_8814B(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) & BIT_MASK_H2C_PKT_WRITEADDR_8814B) - - +#define BIT_H2C_PKT_WRITEADDR_8814B(x) \ + (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8814B) \ + << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) +#define BITS_H2C_PKT_WRITEADDR_8814B \ + (BIT_MASK_H2C_PKT_WRITEADDR_8814B << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) +#define BIT_CLEAR_H2C_PKT_WRITEADDR_8814B(x) \ + ((x) & (~BITS_H2C_PKT_WRITEADDR_8814B)) +#define BIT_GET_H2C_PKT_WRITEADDR_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) & \ + BIT_MASK_H2C_PKT_WRITEADDR_8814B) +#define BIT_SET_H2C_PKT_WRITEADDR_8814B(x, v) \ + (BIT_CLEAR_H2C_PKT_WRITEADDR_8814B(x) | BIT_H2C_PKT_WRITEADDR_8814B(v)) /* 2 REG_MEM_PWR_CRTL_8814B */ #define BIT_MEM_BB_SD_8814B BIT(17) #define BIT_MEM_BB_DS_8814B BIT(16) +#define BIT_MEM_DENG_LS_8814B BIT(13) +#define BIT_MEM_DENG_DS_8814B BIT(12) #define BIT_MEM_BT_DS_8814B BIT(10) #define BIT_MEM_SDIO_LS_8814B BIT(9) #define BIT_MEM_SDIO_DS_8814B BIT(8) @@ -2002,219 +3904,465 @@ #define BIT_MEM_WLMCU_LS_8814B BIT(1) #define BIT_MEM_WLMCU_DS_8814B BIT(0) +/* 2 REG_FW_DRV_HANDSHAKE_8814B */ + +#define BIT_SHIFT_FW_DRV_HANDSHAKE_8814B 0 +#define BIT_MASK_FW_DRV_HANDSHAKE_8814B 0xffffffffL +#define BIT_FW_DRV_HANDSHAKE_8814B(x) \ + (((x) & BIT_MASK_FW_DRV_HANDSHAKE_8814B) \ + << BIT_SHIFT_FW_DRV_HANDSHAKE_8814B) +#define BITS_FW_DRV_HANDSHAKE_8814B \ + (BIT_MASK_FW_DRV_HANDSHAKE_8814B << BIT_SHIFT_FW_DRV_HANDSHAKE_8814B) +#define BIT_CLEAR_FW_DRV_HANDSHAKE_8814B(x) \ + ((x) & (~BITS_FW_DRV_HANDSHAKE_8814B)) +#define BIT_GET_FW_DRV_HANDSHAKE_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DRV_HANDSHAKE_8814B) & \ + BIT_MASK_FW_DRV_HANDSHAKE_8814B) +#define BIT_SET_FW_DRV_HANDSHAKE_8814B(x, v) \ + (BIT_CLEAR_FW_DRV_HANDSHAKE_8814B(x) | BIT_FW_DRV_HANDSHAKE_8814B(v)) + /* 2 REG_FW_DBG0_8814B */ #define BIT_SHIFT_FW_DBG0_8814B 0 #define BIT_MASK_FW_DBG0_8814B 0xffffffffL -#define BIT_FW_DBG0_8814B(x) (((x) & BIT_MASK_FW_DBG0_8814B) << BIT_SHIFT_FW_DBG0_8814B) -#define BIT_GET_FW_DBG0_8814B(x) (((x) >> BIT_SHIFT_FW_DBG0_8814B) & BIT_MASK_FW_DBG0_8814B) - - +#define BIT_FW_DBG0_8814B(x) \ + (((x) & BIT_MASK_FW_DBG0_8814B) << BIT_SHIFT_FW_DBG0_8814B) +#define BITS_FW_DBG0_8814B (BIT_MASK_FW_DBG0_8814B << BIT_SHIFT_FW_DBG0_8814B) +#define BIT_CLEAR_FW_DBG0_8814B(x) ((x) & (~BITS_FW_DBG0_8814B)) +#define BIT_GET_FW_DBG0_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG0_8814B) & BIT_MASK_FW_DBG0_8814B) +#define BIT_SET_FW_DBG0_8814B(x, v) \ + (BIT_CLEAR_FW_DBG0_8814B(x) | BIT_FW_DBG0_8814B(v)) /* 2 REG_FW_DBG1_8814B */ #define BIT_SHIFT_FW_DBG1_8814B 0 #define BIT_MASK_FW_DBG1_8814B 0xffffffffL -#define BIT_FW_DBG1_8814B(x) (((x) & BIT_MASK_FW_DBG1_8814B) << BIT_SHIFT_FW_DBG1_8814B) -#define BIT_GET_FW_DBG1_8814B(x) (((x) >> BIT_SHIFT_FW_DBG1_8814B) & BIT_MASK_FW_DBG1_8814B) - - +#define BIT_FW_DBG1_8814B(x) \ + (((x) & BIT_MASK_FW_DBG1_8814B) << BIT_SHIFT_FW_DBG1_8814B) +#define BITS_FW_DBG1_8814B (BIT_MASK_FW_DBG1_8814B << BIT_SHIFT_FW_DBG1_8814B) +#define BIT_CLEAR_FW_DBG1_8814B(x) ((x) & (~BITS_FW_DBG1_8814B)) +#define BIT_GET_FW_DBG1_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG1_8814B) & BIT_MASK_FW_DBG1_8814B) +#define BIT_SET_FW_DBG1_8814B(x, v) \ + (BIT_CLEAR_FW_DBG1_8814B(x) | BIT_FW_DBG1_8814B(v)) /* 2 REG_FW_DBG2_8814B */ #define BIT_SHIFT_FW_DBG2_8814B 0 #define BIT_MASK_FW_DBG2_8814B 0xffffffffL -#define BIT_FW_DBG2_8814B(x) (((x) & BIT_MASK_FW_DBG2_8814B) << BIT_SHIFT_FW_DBG2_8814B) -#define BIT_GET_FW_DBG2_8814B(x) (((x) >> BIT_SHIFT_FW_DBG2_8814B) & BIT_MASK_FW_DBG2_8814B) - - +#define BIT_FW_DBG2_8814B(x) \ + (((x) & BIT_MASK_FW_DBG2_8814B) << BIT_SHIFT_FW_DBG2_8814B) +#define BITS_FW_DBG2_8814B (BIT_MASK_FW_DBG2_8814B << BIT_SHIFT_FW_DBG2_8814B) +#define BIT_CLEAR_FW_DBG2_8814B(x) ((x) & (~BITS_FW_DBG2_8814B)) +#define BIT_GET_FW_DBG2_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG2_8814B) & BIT_MASK_FW_DBG2_8814B) +#define BIT_SET_FW_DBG2_8814B(x, v) \ + (BIT_CLEAR_FW_DBG2_8814B(x) | BIT_FW_DBG2_8814B(v)) /* 2 REG_FW_DBG3_8814B */ #define BIT_SHIFT_FW_DBG3_8814B 0 #define BIT_MASK_FW_DBG3_8814B 0xffffffffL -#define BIT_FW_DBG3_8814B(x) (((x) & BIT_MASK_FW_DBG3_8814B) << BIT_SHIFT_FW_DBG3_8814B) -#define BIT_GET_FW_DBG3_8814B(x) (((x) >> BIT_SHIFT_FW_DBG3_8814B) & BIT_MASK_FW_DBG3_8814B) - - +#define BIT_FW_DBG3_8814B(x) \ + (((x) & BIT_MASK_FW_DBG3_8814B) << BIT_SHIFT_FW_DBG3_8814B) +#define BITS_FW_DBG3_8814B (BIT_MASK_FW_DBG3_8814B << BIT_SHIFT_FW_DBG3_8814B) +#define BIT_CLEAR_FW_DBG3_8814B(x) ((x) & (~BITS_FW_DBG3_8814B)) +#define BIT_GET_FW_DBG3_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG3_8814B) & BIT_MASK_FW_DBG3_8814B) +#define BIT_SET_FW_DBG3_8814B(x, v) \ + (BIT_CLEAR_FW_DBG3_8814B(x) | BIT_FW_DBG3_8814B(v)) /* 2 REG_FW_DBG4_8814B */ #define BIT_SHIFT_FW_DBG4_8814B 0 #define BIT_MASK_FW_DBG4_8814B 0xffffffffL -#define BIT_FW_DBG4_8814B(x) (((x) & BIT_MASK_FW_DBG4_8814B) << BIT_SHIFT_FW_DBG4_8814B) -#define BIT_GET_FW_DBG4_8814B(x) (((x) >> BIT_SHIFT_FW_DBG4_8814B) & BIT_MASK_FW_DBG4_8814B) - - +#define BIT_FW_DBG4_8814B(x) \ + (((x) & BIT_MASK_FW_DBG4_8814B) << BIT_SHIFT_FW_DBG4_8814B) +#define BITS_FW_DBG4_8814B (BIT_MASK_FW_DBG4_8814B << BIT_SHIFT_FW_DBG4_8814B) +#define BIT_CLEAR_FW_DBG4_8814B(x) ((x) & (~BITS_FW_DBG4_8814B)) +#define BIT_GET_FW_DBG4_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG4_8814B) & BIT_MASK_FW_DBG4_8814B) +#define BIT_SET_FW_DBG4_8814B(x, v) \ + (BIT_CLEAR_FW_DBG4_8814B(x) | BIT_FW_DBG4_8814B(v)) /* 2 REG_FW_DBG5_8814B */ #define BIT_SHIFT_FW_DBG5_8814B 0 #define BIT_MASK_FW_DBG5_8814B 0xffffffffL -#define BIT_FW_DBG5_8814B(x) (((x) & BIT_MASK_FW_DBG5_8814B) << BIT_SHIFT_FW_DBG5_8814B) -#define BIT_GET_FW_DBG5_8814B(x) (((x) >> BIT_SHIFT_FW_DBG5_8814B) & BIT_MASK_FW_DBG5_8814B) - - +#define BIT_FW_DBG5_8814B(x) \ + (((x) & BIT_MASK_FW_DBG5_8814B) << BIT_SHIFT_FW_DBG5_8814B) +#define BITS_FW_DBG5_8814B (BIT_MASK_FW_DBG5_8814B << BIT_SHIFT_FW_DBG5_8814B) +#define BIT_CLEAR_FW_DBG5_8814B(x) ((x) & (~BITS_FW_DBG5_8814B)) +#define BIT_GET_FW_DBG5_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG5_8814B) & BIT_MASK_FW_DBG5_8814B) +#define BIT_SET_FW_DBG5_8814B(x, v) \ + (BIT_CLEAR_FW_DBG5_8814B(x) | BIT_FW_DBG5_8814B(v)) /* 2 REG_FW_DBG6_8814B */ #define BIT_SHIFT_FW_DBG6_8814B 0 #define BIT_MASK_FW_DBG6_8814B 0xffffffffL -#define BIT_FW_DBG6_8814B(x) (((x) & BIT_MASK_FW_DBG6_8814B) << BIT_SHIFT_FW_DBG6_8814B) -#define BIT_GET_FW_DBG6_8814B(x) (((x) >> BIT_SHIFT_FW_DBG6_8814B) & BIT_MASK_FW_DBG6_8814B) - - +#define BIT_FW_DBG6_8814B(x) \ + (((x) & BIT_MASK_FW_DBG6_8814B) << BIT_SHIFT_FW_DBG6_8814B) +#define BITS_FW_DBG6_8814B (BIT_MASK_FW_DBG6_8814B << BIT_SHIFT_FW_DBG6_8814B) +#define BIT_CLEAR_FW_DBG6_8814B(x) ((x) & (~BITS_FW_DBG6_8814B)) +#define BIT_GET_FW_DBG6_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG6_8814B) & BIT_MASK_FW_DBG6_8814B) +#define BIT_SET_FW_DBG6_8814B(x, v) \ + (BIT_CLEAR_FW_DBG6_8814B(x) | BIT_FW_DBG6_8814B(v)) /* 2 REG_FW_DBG7_8814B */ #define BIT_SHIFT_FW_DBG7_8814B 0 #define BIT_MASK_FW_DBG7_8814B 0xffffffffL -#define BIT_FW_DBG7_8814B(x) (((x) & BIT_MASK_FW_DBG7_8814B) << BIT_SHIFT_FW_DBG7_8814B) -#define BIT_GET_FW_DBG7_8814B(x) (((x) >> BIT_SHIFT_FW_DBG7_8814B) & BIT_MASK_FW_DBG7_8814B) - - +#define BIT_FW_DBG7_8814B(x) \ + (((x) & BIT_MASK_FW_DBG7_8814B) << BIT_SHIFT_FW_DBG7_8814B) +#define BITS_FW_DBG7_8814B (BIT_MASK_FW_DBG7_8814B << BIT_SHIFT_FW_DBG7_8814B) +#define BIT_CLEAR_FW_DBG7_8814B(x) ((x) & (~BITS_FW_DBG7_8814B)) +#define BIT_GET_FW_DBG7_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG7_8814B) & BIT_MASK_FW_DBG7_8814B) +#define BIT_SET_FW_DBG7_8814B(x, v) \ + (BIT_CLEAR_FW_DBG7_8814B(x) | BIT_FW_DBG7_8814B(v)) /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_CR_8814B */ - -#define BIT_SHIFT_LBMODE_8814B 24 -#define BIT_MASK_LBMODE_8814B 0x1f -#define BIT_LBMODE_8814B(x) (((x) & BIT_MASK_LBMODE_8814B) << BIT_SHIFT_LBMODE_8814B) -#define BIT_GET_LBMODE_8814B(x) (((x) >> BIT_SHIFT_LBMODE_8814B) & BIT_MASK_LBMODE_8814B) - - - -#define BIT_SHIFT_NETYPE1_8814B 18 -#define BIT_MASK_NETYPE1_8814B 0x3 -#define BIT_NETYPE1_8814B(x) (((x) & BIT_MASK_NETYPE1_8814B) << BIT_SHIFT_NETYPE1_8814B) -#define BIT_GET_NETYPE1_8814B(x) (((x) >> BIT_SHIFT_NETYPE1_8814B) & BIT_MASK_NETYPE1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NETYPE0_8814B 16 -#define BIT_MASK_NETYPE0_8814B 0x3 -#define BIT_NETYPE0_8814B(x) (((x) & BIT_MASK_NETYPE0_8814B) << BIT_SHIFT_NETYPE0_8814B) -#define BIT_GET_NETYPE0_8814B(x) (((x) >> BIT_SHIFT_NETYPE0_8814B) & BIT_MASK_NETYPE0_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_I2C_MAILBOX_EN_8814B BIT(12) -#define BIT_SHCUT_EN_8814B BIT(11) -#define BIT_32K_CAL_TMR_EN_8814B BIT(10) -#define BIT_MAC_SEC_EN_8814B BIT(9) -#define BIT_ENSWBCN_8814B BIT(8) -#define BIT_MACRXEN_8814B BIT(7) -#define BIT_MACTXEN_8814B BIT(6) -#define BIT_SCHEDULE_EN_8814B BIT(5) -#define BIT_PROTOCOL_EN_8814B BIT(4) -#define BIT_RXDMA_EN_8814B BIT(3) -#define BIT_TXDMA_EN_8814B BIT(2) -#define BIT_HCI_RXDMA_EN_8814B BIT(1) -#define BIT_HCI_TXDMA_EN_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PKT_BUFF_ACCESS_CTRL_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B 0 -#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B 0xff -#define BIT_PKT_BUFF_ACCESS_CTRL_8814B(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) -#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8814B(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TSF_CLK_STATE_8814B */ -#define BIT_TSF_CLK_STABLE_8814B BIT(15) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TXDMA_PQ_MAP_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXDMA_HIQ_MAP_8814B 14 -#define BIT_MASK_TXDMA_HIQ_MAP_8814B 0x3 -#define BIT_TXDMA_HIQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8814B) << BIT_SHIFT_TXDMA_HIQ_MAP_8814B) -#define BIT_GET_TXDMA_HIQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8814B) & BIT_MASK_TXDMA_HIQ_MAP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXDMA_MGQ_MAP_8814B 12 -#define BIT_MASK_TXDMA_MGQ_MAP_8814B 0x3 -#define BIT_TXDMA_MGQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8814B) << BIT_SHIFT_TXDMA_MGQ_MAP_8814B) -#define BIT_GET_TXDMA_MGQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8814B) & BIT_MASK_TXDMA_MGQ_MAP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXDMA_BKQ_MAP_8814B 10 -#define BIT_MASK_TXDMA_BKQ_MAP_8814B 0x3 -#define BIT_TXDMA_BKQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8814B) << BIT_SHIFT_TXDMA_BKQ_MAP_8814B) -#define BIT_GET_TXDMA_BKQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8814B) & BIT_MASK_TXDMA_BKQ_MAP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXDMA_BEQ_MAP_8814B 8 -#define BIT_MASK_TXDMA_BEQ_MAP_8814B 0x3 -#define BIT_TXDMA_BEQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8814B) << BIT_SHIFT_TXDMA_BEQ_MAP_8814B) -#define BIT_GET_TXDMA_BEQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8814B) & BIT_MASK_TXDMA_BEQ_MAP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXDMA_VIQ_MAP_8814B 6 -#define BIT_MASK_TXDMA_VIQ_MAP_8814B 0x3 -#define BIT_TXDMA_VIQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8814B) << BIT_SHIFT_TXDMA_VIQ_MAP_8814B) -#define BIT_GET_TXDMA_VIQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8814B) & BIT_MASK_TXDMA_VIQ_MAP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXDMA_VOQ_MAP_8814B 4 -#define BIT_MASK_TXDMA_VOQ_MAP_8814B 0x3 -#define BIT_TXDMA_VOQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8814B) << BIT_SHIFT_TXDMA_VOQ_MAP_8814B) -#define BIT_GET_TXDMA_VOQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8814B) & BIT_MASK_TXDMA_VOQ_MAP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_RXDMA_AGG_EN_8814B BIT(2) -#define BIT_RXSHFT_EN_8814B BIT(1) -#define BIT_RXDMA_ARBBW_EN_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TRXFF_BNDY_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_RXFFOVFL_RSV_V2_8814B 8 -#define BIT_MASK_RXFFOVFL_RSV_V2_8814B 0xf -#define BIT_RXFFOVFL_RSV_V2_8814B(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8814B) << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) -#define BIT_GET_RXFFOVFL_RSV_V2_8814B(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) & BIT_MASK_RXFFOVFL_RSV_V2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXPKTBUF_PGBNDY_8814B 0 -#define BIT_MASK_TXPKTBUF_PGBNDY_8814B 0xff -#define BIT_TXPKTBUF_PGBNDY_8814B(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8814B) << BIT_SHIFT_TXPKTBUF_PGBNDY_8814B) -#define BIT_GET_TXPKTBUF_PGBNDY_8814B(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8814B) & BIT_MASK_TXPKTBUF_PGBNDY_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PTA_I2C_MBOX_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_I2C_M_STATUS_8814B 8 -#define BIT_MASK_I2C_M_STATUS_8814B 0xf -#define BIT_I2C_M_STATUS_8814B(x) (((x) & BIT_MASK_I2C_M_STATUS_8814B) << BIT_SHIFT_I2C_M_STATUS_8814B) -#define BIT_GET_I2C_M_STATUS_8814B(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8814B) & BIT_MASK_I2C_M_STATUS_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_CR_8814B */ -#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B 4 -#define BIT_MASK_I2C_M_BUS_GNT_FW_8814B 0x7 -#define BIT_I2C_M_BUS_GNT_FW_8814B(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8814B) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) -#define BIT_GET_I2C_M_BUS_GNT_FW_8814B(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) & BIT_MASK_I2C_M_BUS_GNT_FW_8814B) +#define BIT_SHIFT_LBMODE_8814B 24 +#define BIT_MASK_LBMODE_8814B 0x1f +#define BIT_LBMODE_8814B(x) \ + (((x) & BIT_MASK_LBMODE_8814B) << BIT_SHIFT_LBMODE_8814B) +#define BITS_LBMODE_8814B (BIT_MASK_LBMODE_8814B << BIT_SHIFT_LBMODE_8814B) +#define BIT_CLEAR_LBMODE_8814B(x) ((x) & (~BITS_LBMODE_8814B)) +#define BIT_GET_LBMODE_8814B(x) \ + (((x) >> BIT_SHIFT_LBMODE_8814B) & BIT_MASK_LBMODE_8814B) +#define BIT_SET_LBMODE_8814B(x, v) \ + (BIT_CLEAR_LBMODE_8814B(x) | BIT_LBMODE_8814B(v)) +#define BIT_SHIFT_NETYPE1_8814B 18 +#define BIT_MASK_NETYPE1_8814B 0x3 +#define BIT_NETYPE1_8814B(x) \ + (((x) & BIT_MASK_NETYPE1_8814B) << BIT_SHIFT_NETYPE1_8814B) +#define BITS_NETYPE1_8814B (BIT_MASK_NETYPE1_8814B << BIT_SHIFT_NETYPE1_8814B) +#define BIT_CLEAR_NETYPE1_8814B(x) ((x) & (~BITS_NETYPE1_8814B)) +#define BIT_GET_NETYPE1_8814B(x) \ + (((x) >> BIT_SHIFT_NETYPE1_8814B) & BIT_MASK_NETYPE1_8814B) +#define BIT_SET_NETYPE1_8814B(x, v) \ + (BIT_CLEAR_NETYPE1_8814B(x) | BIT_NETYPE1_8814B(v)) -#define BIT_I2C_M_GNT_FW_8814B BIT(3) +#define BIT_SHIFT_NETYPE0_8814B 16 +#define BIT_MASK_NETYPE0_8814B 0x3 +#define BIT_NETYPE0_8814B(x) \ + (((x) & BIT_MASK_NETYPE0_8814B) << BIT_SHIFT_NETYPE0_8814B) +#define BITS_NETYPE0_8814B (BIT_MASK_NETYPE0_8814B << BIT_SHIFT_NETYPE0_8814B) +#define BIT_CLEAR_NETYPE0_8814B(x) ((x) & (~BITS_NETYPE0_8814B)) +#define BIT_GET_NETYPE0_8814B(x) \ + (((x) >> BIT_SHIFT_NETYPE0_8814B) & BIT_MASK_NETYPE0_8814B) +#define BIT_SET_NETYPE0_8814B(x, v) \ + (BIT_CLEAR_NETYPE0_8814B(x) | BIT_NETYPE0_8814B(v)) + +#define BIT_COUNTER_STS_EN_8814B BIT(13) +#define BIT_I2C_MAILBOX_EN_8814B BIT(12) +#define BIT_SHCUT_EN_8814B BIT(11) +#define BIT_32K_CAL_TMR_EN_8814B BIT(10) +#define BIT_MAC_SEC_EN_8814B BIT(9) +#define BIT_ENSWBCN_8814B BIT(8) +#define BIT_MACRXEN_8814B BIT(7) +#define BIT_MACTXEN_8814B BIT(6) +#define BIT_SCHEDULE_EN_8814B BIT(5) +#define BIT_PROTOCOL_EN_8814B BIT(4) +#define BIT_RXDMA_EN_8814B BIT(3) +#define BIT_TXDMA_EN_8814B BIT(2) +#define BIT_HCI_RXDMA_EN_8814B BIT(1) +#define BIT_HCI_TXDMA_EN_8814B BIT(0) + +/* 2 REG_PG_SIZE_8814B */ + +#define BIT_SHIFT_DBG_FIFO_SEL_8814B 16 +#define BIT_MASK_DBG_FIFO_SEL_8814B 0xff +#define BIT_DBG_FIFO_SEL_8814B(x) \ + (((x) & BIT_MASK_DBG_FIFO_SEL_8814B) << BIT_SHIFT_DBG_FIFO_SEL_8814B) +#define BITS_DBG_FIFO_SEL_8814B \ + (BIT_MASK_DBG_FIFO_SEL_8814B << BIT_SHIFT_DBG_FIFO_SEL_8814B) +#define BIT_CLEAR_DBG_FIFO_SEL_8814B(x) ((x) & (~BITS_DBG_FIFO_SEL_8814B)) +#define BIT_GET_DBG_FIFO_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_DBG_FIFO_SEL_8814B) & BIT_MASK_DBG_FIFO_SEL_8814B) +#define BIT_SET_DBG_FIFO_SEL_8814B(x, v) \ + (BIT_CLEAR_DBG_FIFO_SEL_8814B(x) | BIT_DBG_FIFO_SEL_8814B(v)) + +/* 2 REG_PKT_BUFF_ACCESS_CTRL_8814B */ + +#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B 0 +#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B 0xff +#define BIT_PKT_BUFF_ACCESS_CTRL_8814B(x) \ + (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B) \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) +#define BITS_PKT_BUFF_ACCESS_CTRL_8814B \ + (BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) +#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8814B(x) \ + ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8814B)) +#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) & \ + BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B) +#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8814B(x, v) \ + (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8814B(x) | \ + BIT_PKT_BUFF_ACCESS_CTRL_8814B(v)) + +/* 2 REG_TSF_CLK_STATE_8814B */ +#define BIT_TSF_CLK_STABLE_8814B BIT(15) + +/* 2 REG_TXDMA_PQ_MAP_8814B */ + +#define BIT_SHIFT_TXDMA_H2C_MAP_8814B 16 +#define BIT_MASK_TXDMA_H2C_MAP_8814B 0x3 +#define BIT_TXDMA_H2C_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_H2C_MAP_8814B) << BIT_SHIFT_TXDMA_H2C_MAP_8814B) +#define BITS_TXDMA_H2C_MAP_8814B \ + (BIT_MASK_TXDMA_H2C_MAP_8814B << BIT_SHIFT_TXDMA_H2C_MAP_8814B) +#define BIT_CLEAR_TXDMA_H2C_MAP_8814B(x) ((x) & (~BITS_TXDMA_H2C_MAP_8814B)) +#define BIT_GET_TXDMA_H2C_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8814B) & BIT_MASK_TXDMA_H2C_MAP_8814B) +#define BIT_SET_TXDMA_H2C_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_H2C_MAP_8814B(x) | BIT_TXDMA_H2C_MAP_8814B(v)) + +#define BIT_SHIFT_TXDMA_HIQ_MAP_8814B 14 +#define BIT_MASK_TXDMA_HIQ_MAP_8814B 0x3 +#define BIT_TXDMA_HIQ_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP_8814B) << BIT_SHIFT_TXDMA_HIQ_MAP_8814B) +#define BITS_TXDMA_HIQ_MAP_8814B \ + (BIT_MASK_TXDMA_HIQ_MAP_8814B << BIT_SHIFT_TXDMA_HIQ_MAP_8814B) +#define BIT_CLEAR_TXDMA_HIQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8814B)) +#define BIT_GET_TXDMA_HIQ_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8814B) & BIT_MASK_TXDMA_HIQ_MAP_8814B) +#define BIT_SET_TXDMA_HIQ_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP_8814B(x) | BIT_TXDMA_HIQ_MAP_8814B(v)) + +#define BIT_SHIFT_TXDMA_MGQ_MAP_8814B 12 +#define BIT_MASK_TXDMA_MGQ_MAP_8814B 0x3 +#define BIT_TXDMA_MGQ_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP_8814B) << BIT_SHIFT_TXDMA_MGQ_MAP_8814B) +#define BITS_TXDMA_MGQ_MAP_8814B \ + (BIT_MASK_TXDMA_MGQ_MAP_8814B << BIT_SHIFT_TXDMA_MGQ_MAP_8814B) +#define BIT_CLEAR_TXDMA_MGQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8814B)) +#define BIT_GET_TXDMA_MGQ_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8814B) & BIT_MASK_TXDMA_MGQ_MAP_8814B) +#define BIT_SET_TXDMA_MGQ_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP_8814B(x) | BIT_TXDMA_MGQ_MAP_8814B(v)) + +#define BIT_SHIFT_TXDMA_BKQ_MAP_8814B 10 +#define BIT_MASK_TXDMA_BKQ_MAP_8814B 0x3 +#define BIT_TXDMA_BKQ_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP_8814B) << BIT_SHIFT_TXDMA_BKQ_MAP_8814B) +#define BITS_TXDMA_BKQ_MAP_8814B \ + (BIT_MASK_TXDMA_BKQ_MAP_8814B << BIT_SHIFT_TXDMA_BKQ_MAP_8814B) +#define BIT_CLEAR_TXDMA_BKQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8814B)) +#define BIT_GET_TXDMA_BKQ_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8814B) & BIT_MASK_TXDMA_BKQ_MAP_8814B) +#define BIT_SET_TXDMA_BKQ_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP_8814B(x) | BIT_TXDMA_BKQ_MAP_8814B(v)) + +#define BIT_SHIFT_TXDMA_BEQ_MAP_8814B 8 +#define BIT_MASK_TXDMA_BEQ_MAP_8814B 0x3 +#define BIT_TXDMA_BEQ_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP_8814B) << BIT_SHIFT_TXDMA_BEQ_MAP_8814B) +#define BITS_TXDMA_BEQ_MAP_8814B \ + (BIT_MASK_TXDMA_BEQ_MAP_8814B << BIT_SHIFT_TXDMA_BEQ_MAP_8814B) +#define BIT_CLEAR_TXDMA_BEQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8814B)) +#define BIT_GET_TXDMA_BEQ_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8814B) & BIT_MASK_TXDMA_BEQ_MAP_8814B) +#define BIT_SET_TXDMA_BEQ_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP_8814B(x) | BIT_TXDMA_BEQ_MAP_8814B(v)) + +#define BIT_SHIFT_TXDMA_VIQ_MAP_8814B 6 +#define BIT_MASK_TXDMA_VIQ_MAP_8814B 0x3 +#define BIT_TXDMA_VIQ_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP_8814B) << BIT_SHIFT_TXDMA_VIQ_MAP_8814B) +#define BITS_TXDMA_VIQ_MAP_8814B \ + (BIT_MASK_TXDMA_VIQ_MAP_8814B << BIT_SHIFT_TXDMA_VIQ_MAP_8814B) +#define BIT_CLEAR_TXDMA_VIQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8814B)) +#define BIT_GET_TXDMA_VIQ_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8814B) & BIT_MASK_TXDMA_VIQ_MAP_8814B) +#define BIT_SET_TXDMA_VIQ_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP_8814B(x) | BIT_TXDMA_VIQ_MAP_8814B(v)) + +#define BIT_SHIFT_TXDMA_VOQ_MAP_8814B 4 +#define BIT_MASK_TXDMA_VOQ_MAP_8814B 0x3 +#define BIT_TXDMA_VOQ_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP_8814B) << BIT_SHIFT_TXDMA_VOQ_MAP_8814B) +#define BITS_TXDMA_VOQ_MAP_8814B \ + (BIT_MASK_TXDMA_VOQ_MAP_8814B << BIT_SHIFT_TXDMA_VOQ_MAP_8814B) +#define BIT_CLEAR_TXDMA_VOQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8814B)) +#define BIT_GET_TXDMA_VOQ_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8814B) & BIT_MASK_TXDMA_VOQ_MAP_8814B) +#define BIT_SET_TXDMA_VOQ_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP_8814B(x) | BIT_TXDMA_VOQ_MAP_8814B(v)) + +#define BIT_RXDMA_AGG_EN_8814B BIT(2) +#define BIT_RXSHFT_EN_8814B BIT(1) +#define BIT_RXDMA_ARBBW_EN_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_TRXFF_BNDY_8814B */ + +#define BIT_SHIFT_FWFFOVFL_RSV_8814B 16 +#define BIT_MASK_FWFFOVFL_RSV_8814B 0xf +#define BIT_FWFFOVFL_RSV_8814B(x) \ + (((x) & BIT_MASK_FWFFOVFL_RSV_8814B) << BIT_SHIFT_FWFFOVFL_RSV_8814B) +#define BITS_FWFFOVFL_RSV_8814B \ + (BIT_MASK_FWFFOVFL_RSV_8814B << BIT_SHIFT_FWFFOVFL_RSV_8814B) +#define BIT_CLEAR_FWFFOVFL_RSV_8814B(x) ((x) & (~BITS_FWFFOVFL_RSV_8814B)) +#define BIT_GET_FWFFOVFL_RSV_8814B(x) \ + (((x) >> BIT_SHIFT_FWFFOVFL_RSV_8814B) & BIT_MASK_FWFFOVFL_RSV_8814B) +#define BIT_SET_FWFFOVFL_RSV_8814B(x, v) \ + (BIT_CLEAR_FWFFOVFL_RSV_8814B(x) | BIT_FWFFOVFL_RSV_8814B(v)) + +#define BIT_SHIFT_RXFFOVFL_RSV_V2_8814B 8 +#define BIT_MASK_RXFFOVFL_RSV_V2_8814B 0xf +#define BIT_RXFFOVFL_RSV_V2_8814B(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8814B) \ + << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) +#define BITS_RXFFOVFL_RSV_V2_8814B \ + (BIT_MASK_RXFFOVFL_RSV_V2_8814B << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) +#define BIT_CLEAR_RXFFOVFL_RSV_V2_8814B(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8814B)) +#define BIT_GET_RXFFOVFL_RSV_V2_8814B(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) & \ + BIT_MASK_RXFFOVFL_RSV_V2_8814B) +#define BIT_SET_RXFFOVFL_RSV_V2_8814B(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V2_8814B(x) | BIT_RXFFOVFL_RSV_V2_8814B(v)) + +/* 2 REG_PTA_I2C_MBOX_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_I2C_M_STATUS_8814B 8 +#define BIT_MASK_I2C_M_STATUS_8814B 0xf +#define BIT_I2C_M_STATUS_8814B(x) \ + (((x) & BIT_MASK_I2C_M_STATUS_8814B) << BIT_SHIFT_I2C_M_STATUS_8814B) +#define BITS_I2C_M_STATUS_8814B \ + (BIT_MASK_I2C_M_STATUS_8814B << BIT_SHIFT_I2C_M_STATUS_8814B) +#define BIT_CLEAR_I2C_M_STATUS_8814B(x) ((x) & (~BITS_I2C_M_STATUS_8814B)) +#define BIT_GET_I2C_M_STATUS_8814B(x) \ + (((x) >> BIT_SHIFT_I2C_M_STATUS_8814B) & BIT_MASK_I2C_M_STATUS_8814B) +#define BIT_SET_I2C_M_STATUS_8814B(x, v) \ + (BIT_CLEAR_I2C_M_STATUS_8814B(x) | BIT_I2C_M_STATUS_8814B(v)) + +#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B 4 +#define BIT_MASK_I2C_M_BUS_GNT_FW_8814B 0x7 +#define BIT_I2C_M_BUS_GNT_FW_8814B(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8814B) \ + << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) +#define BITS_I2C_M_BUS_GNT_FW_8814B \ + (BIT_MASK_I2C_M_BUS_GNT_FW_8814B << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8814B(x) \ + ((x) & (~BITS_I2C_M_BUS_GNT_FW_8814B)) +#define BIT_GET_I2C_M_BUS_GNT_FW_8814B(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) & \ + BIT_MASK_I2C_M_BUS_GNT_FW_8814B) +#define BIT_SET_I2C_M_BUS_GNT_FW_8814B(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT_FW_8814B(x) | BIT_I2C_M_BUS_GNT_FW_8814B(v)) + +#define BIT_I2C_M_GNT_FW_8814B BIT(3) #define BIT_SHIFT_I2C_M_SPEED_8814B 1 #define BIT_MASK_I2C_M_SPEED_8814B 0x3 -#define BIT_I2C_M_SPEED_8814B(x) (((x) & BIT_MASK_I2C_M_SPEED_8814B) << BIT_SHIFT_I2C_M_SPEED_8814B) -#define BIT_GET_I2C_M_SPEED_8814B(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8814B) & BIT_MASK_I2C_M_SPEED_8814B) - +#define BIT_I2C_M_SPEED_8814B(x) \ + (((x) & BIT_MASK_I2C_M_SPEED_8814B) << BIT_SHIFT_I2C_M_SPEED_8814B) +#define BITS_I2C_M_SPEED_8814B \ + (BIT_MASK_I2C_M_SPEED_8814B << BIT_SHIFT_I2C_M_SPEED_8814B) +#define BIT_CLEAR_I2C_M_SPEED_8814B(x) ((x) & (~BITS_I2C_M_SPEED_8814B)) +#define BIT_GET_I2C_M_SPEED_8814B(x) \ + (((x) >> BIT_SHIFT_I2C_M_SPEED_8814B) & BIT_MASK_I2C_M_SPEED_8814B) +#define BIT_SET_I2C_M_SPEED_8814B(x, v) \ + (BIT_CLEAR_I2C_M_SPEED_8814B(x) | BIT_I2C_M_SPEED_8814B(v)) #define BIT_I2C_M_UNLOCK_8814B BIT(0) @@ -2224,12 +4372,20 @@ #define BIT_SHIFT_RXFF0_BNDY_V2_8814B 0 #define BIT_MASK_RXFF0_BNDY_V2_8814B 0x3ffff -#define BIT_RXFF0_BNDY_V2_8814B(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8814B) << BIT_SHIFT_RXFF0_BNDY_V2_8814B) -#define BIT_GET_RXFF0_BNDY_V2_8814B(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8814B) & BIT_MASK_RXFF0_BNDY_V2_8814B) - - +#define BIT_RXFF0_BNDY_V2_8814B(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V2_8814B) << BIT_SHIFT_RXFF0_BNDY_V2_8814B) +#define BITS_RXFF0_BNDY_V2_8814B \ + (BIT_MASK_RXFF0_BNDY_V2_8814B << BIT_SHIFT_RXFF0_BNDY_V2_8814B) +#define BIT_CLEAR_RXFF0_BNDY_V2_8814B(x) ((x) & (~BITS_RXFF0_BNDY_V2_8814B)) +#define BIT_GET_RXFF0_BNDY_V2_8814B(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8814B) & BIT_MASK_RXFF0_BNDY_V2_8814B) +#define BIT_SET_RXFF0_BNDY_V2_8814B(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V2_8814B(x) | BIT_RXFF0_BNDY_V2_8814B(v)) /* 2 REG_FE1IMR_8814B */ +#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_EN_8814B BIT(31) +#define BIT_FWFF_FULL_INT_EN_8814B BIT(30) +#define BIT_BB_STOP_RX_INT_EN_8814B BIT(29) #define BIT_FS_RXDMA2_DONE_INT_EN_8814B BIT(28) #define BIT_FS_RXDONE3_INT_EN_8814B BIT(27) #define BIT_FS_RXDONE2_INT_EN_8814B BIT(26) @@ -2245,11 +4401,12 @@ #define BIT_FS_RXDONE_INT_EN_8814B BIT(16) #define BIT_FS_WWLAN_INT_EN_8814B BIT(15) #define BIT_FS_SOUND_DONE_INT_EN_8814B BIT(14) -#define BIT_FS_LP_STBY_INT_EN_8814B BIT(13) #define BIT_FS_TRL_MTR_INT_EN_8814B BIT(12) #define BIT_FS_BF1_PRETO_INT_EN_8814B BIT(11) #define BIT_FS_BF0_PRETO_INT_EN_8814B BIT(10) #define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8814B BIT(9) +#define BIT_PRETX_ERRHLD_INT_EN_8814B BIT(8) +#define BIT_FS_GTRD_INT_EN_8814B BIT(7) #define BIT_FS_LTE_COEX_EN_8814B BIT(6) #define BIT_FS_WLACTOFF_INT_EN_8814B BIT(5) #define BIT_FS_WLACTON_INT_EN_8814B BIT(4) @@ -2259,8 +4416,11 @@ #define BIT_FS_RPC_O_T_INT_EN_V1_8814B BIT(0) /* 2 REG_FE1ISR_8814B */ +#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_8814B BIT(31) +#define BIT_FWFF_FULL_INT_8814B BIT(30) +#define BIT_BB_STOP_RX_INT_8814B BIT(29) #define BIT_FS_RXDMA2_DONE_INT_8814B BIT(28) -#define BIT_FS_RXDONE3_INT_8814B BIT(27) +#define BIT_FS_RXDONE3_INT_INT_8814B BIT(27) #define BIT_FS_RXDONE2_INT_8814B BIT(26) #define BIT_FS_RX_BCN_P4_INT_8814B BIT(25) #define BIT_FS_RX_BCN_P3_INT_8814B BIT(24) @@ -2274,15 +4434,16 @@ #define BIT_FS_RXDONE_INT_8814B BIT(16) #define BIT_FS_WWLAN_INT_8814B BIT(15) #define BIT_FS_SOUND_DONE_INT_8814B BIT(14) -#define BIT_FS_LP_STBY_INT_8814B BIT(13) #define BIT_FS_TRL_MTR_INT_8814B BIT(12) #define BIT_FS_BF1_PRETO_INT_8814B BIT(11) #define BIT_FS_BF0_PRETO_INT_8814B BIT(10) #define BIT_FS_PTCL_RELEASE_MACID_INT_8814B BIT(9) +#define BIT_PRETX_ERRHLD_INT_8814B BIT(8) +#define BIT_SND_RDY_INT_8814B BIT(7) #define BIT_FS_LTE_COEX_INT_8814B BIT(6) #define BIT_FS_WLACTOFF_INT_8814B BIT(5) #define BIT_FS_WLACTON_INT_8814B BIT(4) -#define BIT_FS_BCN_RX_INT_INT_8814B BIT(3) +#define BIT_BT_CMD_INT_8814B BIT(3) #define BIT_FS_MAILBOX_TO_I2C_INT_8814B BIT(2) #define BIT_FS_TRPC_TO_INT_8814B BIT(1) #define BIT_FS_RPC_O_T_INT_8814B BIT(0) @@ -2294,10 +4455,15 @@ #define BIT_SHIFT_CPWM_MOD_8814B 24 #define BIT_MASK_CPWM_MOD_8814B 0x7f -#define BIT_CPWM_MOD_8814B(x) (((x) & BIT_MASK_CPWM_MOD_8814B) << BIT_SHIFT_CPWM_MOD_8814B) -#define BIT_GET_CPWM_MOD_8814B(x) (((x) >> BIT_SHIFT_CPWM_MOD_8814B) & BIT_MASK_CPWM_MOD_8814B) - - +#define BIT_CPWM_MOD_8814B(x) \ + (((x) & BIT_MASK_CPWM_MOD_8814B) << BIT_SHIFT_CPWM_MOD_8814B) +#define BITS_CPWM_MOD_8814B \ + (BIT_MASK_CPWM_MOD_8814B << BIT_SHIFT_CPWM_MOD_8814B) +#define BIT_CLEAR_CPWM_MOD_8814B(x) ((x) & (~BITS_CPWM_MOD_8814B)) +#define BIT_GET_CPWM_MOD_8814B(x) \ + (((x) >> BIT_SHIFT_CPWM_MOD_8814B) & BIT_MASK_CPWM_MOD_8814B) +#define BIT_SET_CPWM_MOD_8814B(x, v) \ + (BIT_CLEAR_CPWM_MOD_8814B(x) | BIT_CPWM_MOD_8814B(v)) /* 2 REG_FWIMR_8814B */ #define BIT_FS_TXBCNOK_MB7_INT_EN_8814B BIT(31) @@ -2320,8 +4486,7 @@ #define BIT_SIFS_OVERSPEC_INT_EN_8814B BIT(14) #define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8814B BIT(13) #define BIT_FS_MGNTQFF_TO_INT_EN_8814B BIT(12) -#define BIT_FS_DDMA1_LP_INT_EN_8814B BIT(11) -#define BIT_FS_DDMA1_HP_INT_EN_8814B BIT(10) +#define BIT_FS_CPUMGQ_ERR_INT_EN_8814B BIT(11) #define BIT_FS_DDMA0_LP_INT_EN_8814B BIT(9) #define BIT_FS_DDMA0_HP_INT_EN_8814B BIT(8) #define BIT_FS_TRXRPT_INT_EN_8814B BIT(7) @@ -2354,8 +4519,8 @@ #define BIT_SIFS_OVERSPEC_INT_8814B BIT(14) #define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8814B BIT(13) #define BIT_FS_MGNTQFF_TO_INT_8814B BIT(12) -#define BIT_FS_DDMA1_LP_INT_8814B BIT(11) -#define BIT_FS_DDMA1_HP_INT_8814B BIT(10) +#define BIT_FS_CPUMGQ_ERR_INT_8814B BIT(11) +#define BIT_FWCMD_PKTIN_INT_8814B BIT(10) #define BIT_FS_DDMA0_LP_INT_8814B BIT(9) #define BIT_FS_DDMA0_HP_INT_8814B BIT(8) #define BIT_FS_TRXRPT_INT_8814B BIT(7) @@ -2379,6 +4544,10 @@ #define BIT_FS_PS_TIMEOUT2_EN_8814B BIT(15) #define BIT_FS_PS_TIMEOUT1_EN_8814B BIT(14) #define BIT_FS_PS_TIMEOUT0_EN_8814B BIT(13) +#define BIT_FS_GTINT12_EN_8814B BIT(12) +#define BIT_FS_GTINT11_EN_8814B BIT(11) +#define BIT_FS_GTINT10_EN_8814B BIT(10) +#define BIT_FS_GTINT9_EN_8814B BIT(9) #define BIT_FS_GTINT8_EN_8814B BIT(8) #define BIT_FS_GTINT7_EN_8814B BIT(7) #define BIT_FS_GTINT6_EN_8814B BIT(6) @@ -2390,17 +4559,24 @@ #define BIT_FS_GTINT0_EN_8814B BIT(0) /* 2 REG_FTISR_8814B */ -#define BIT_PS_TIMER_C_EARLY__INT_8814B BIT(23) -#define BIT_PS_TIMER_B_EARLY__INT_8814B BIT(22) -#define BIT_PS_TIMER_A_EARLY__INT_8814B BIT(21) +#define BIT_PS_TIMER_5_EARLY__INT_8814B BIT(26) +#define BIT_PS_TIMER_4_EARLY__INT_8814B BIT(25) +#define BIT_PS_TIMER_3_EARLY__INT_8814B BIT(24) +#define BIT_PS_TIMER_2_EARLY__INT_8814B BIT(23) +#define BIT_PS_TIMER_1_EARLY__INT_8814B BIT(22) +#define BIT_PS_TIMER_0_EARLY__INT_8814B BIT(21) #define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8814B BIT(20) -#define BIT_PS_TIMER_C_INT_8814B BIT(19) -#define BIT_PS_TIMER_B_INT_8814B BIT(18) -#define BIT_PS_TIMER_A_INT_8814B BIT(17) +#define BIT_PS_TIMER_5_INT_8814B BIT(19) +#define BIT_PS_TIMER_4_INT_8814B BIT(18) +#define BIT_PS_TIMER_3_INT_8814B BIT(17) #define BIT_CPUMGQ_TX_TIMER_INT_8814B BIT(16) -#define BIT_FS_PS_TIMEOUT2_INT_8814B BIT(15) -#define BIT_FS_PS_TIMEOUT1_INT_8814B BIT(14) -#define BIT_FS_PS_TIMEOUT0_INT_8814B BIT(13) +#define BIT_PS_TIMER_2_INT_8814B BIT(15) +#define BIT_PS_TIMER_1_INT_8814B BIT(14) +#define BIT_PS_TIMER_0_INT_8814B BIT(13) +#define BIT_FS_GTINT12_INT_8814B BIT(12) +#define BIT_FS_GTINT11_INT_8814B BIT(11) +#define BIT_FS_GTINT10_INT_8814B BIT(10) +#define BIT_FS_GTINT9_INT_8814B BIT(9) #define BIT_FS_GTINT8_INT_8814B BIT(8) #define BIT_FS_GTINT7_INT_8814B BIT(7) #define BIT_FS_GTINT6_INT_8814B BIT(6) @@ -2415,9 +4591,17 @@ #define BIT_SHIFT_PKTBUF_WRITE_EN_8814B 24 #define BIT_MASK_PKTBUF_WRITE_EN_8814B 0xff -#define BIT_PKTBUF_WRITE_EN_8814B(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8814B) << BIT_SHIFT_PKTBUF_WRITE_EN_8814B) -#define BIT_GET_PKTBUF_WRITE_EN_8814B(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8814B) & BIT_MASK_PKTBUF_WRITE_EN_8814B) - +#define BIT_PKTBUF_WRITE_EN_8814B(x) \ + (((x) & BIT_MASK_PKTBUF_WRITE_EN_8814B) \ + << BIT_SHIFT_PKTBUF_WRITE_EN_8814B) +#define BITS_PKTBUF_WRITE_EN_8814B \ + (BIT_MASK_PKTBUF_WRITE_EN_8814B << BIT_SHIFT_PKTBUF_WRITE_EN_8814B) +#define BIT_CLEAR_PKTBUF_WRITE_EN_8814B(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8814B)) +#define BIT_GET_PKTBUF_WRITE_EN_8814B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8814B) & \ + BIT_MASK_PKTBUF_WRITE_EN_8814B) +#define BIT_SET_PKTBUF_WRITE_EN_8814B(x, v) \ + (BIT_CLEAR_PKTBUF_WRITE_EN_8814B(x) | BIT_PKTBUF_WRITE_EN_8814B(v)) #define BIT_TXRPTBUF_DBG_8814B BIT(23) @@ -2427,45 +4611,81 @@ #define BIT_SHIFT_PKTBUF_DBG_ADDR_8814B 0 #define BIT_MASK_PKTBUF_DBG_ADDR_8814B 0x1fff -#define BIT_PKTBUF_DBG_ADDR_8814B(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8814B) << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) -#define BIT_GET_PKTBUF_DBG_ADDR_8814B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) & BIT_MASK_PKTBUF_DBG_ADDR_8814B) - - +#define BIT_PKTBUF_DBG_ADDR_8814B(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8814B) \ + << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) +#define BITS_PKTBUF_DBG_ADDR_8814B \ + (BIT_MASK_PKTBUF_DBG_ADDR_8814B << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) +#define BIT_CLEAR_PKTBUF_DBG_ADDR_8814B(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8814B)) +#define BIT_GET_PKTBUF_DBG_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) & \ + BIT_MASK_PKTBUF_DBG_ADDR_8814B) +#define BIT_SET_PKTBUF_DBG_ADDR_8814B(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_ADDR_8814B(x) | BIT_PKTBUF_DBG_ADDR_8814B(v)) /* 2 REG_PKTBUF_DBG_DATA_L_8814B */ #define BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B 0 #define BIT_MASK_PKTBUF_DBG_DATA_L_8814B 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_L_8814B(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8814B) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) -#define BIT_GET_PKTBUF_DBG_DATA_L_8814B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) & BIT_MASK_PKTBUF_DBG_DATA_L_8814B) - - +#define BIT_PKTBUF_DBG_DATA_L_8814B(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8814B) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) +#define BITS_PKTBUF_DBG_DATA_L_8814B \ + (BIT_MASK_PKTBUF_DBG_DATA_L_8814B << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8814B(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_L_8814B)) +#define BIT_GET_PKTBUF_DBG_DATA_L_8814B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) & \ + BIT_MASK_PKTBUF_DBG_DATA_L_8814B) +#define BIT_SET_PKTBUF_DBG_DATA_L_8814B(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_L_8814B(x) | BIT_PKTBUF_DBG_DATA_L_8814B(v)) /* 2 REG_PKTBUF_DBG_DATA_H_8814B */ #define BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B 0 #define BIT_MASK_PKTBUF_DBG_DATA_H_8814B 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_H_8814B(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8814B) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) -#define BIT_GET_PKTBUF_DBG_DATA_H_8814B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) & BIT_MASK_PKTBUF_DBG_DATA_H_8814B) - - +#define BIT_PKTBUF_DBG_DATA_H_8814B(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8814B) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) +#define BITS_PKTBUF_DBG_DATA_H_8814B \ + (BIT_MASK_PKTBUF_DBG_DATA_H_8814B << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8814B(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_H_8814B)) +#define BIT_GET_PKTBUF_DBG_DATA_H_8814B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) & \ + BIT_MASK_PKTBUF_DBG_DATA_H_8814B) +#define BIT_SET_PKTBUF_DBG_DATA_H_8814B(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_H_8814B(x) | BIT_PKTBUF_DBG_DATA_H_8814B(v)) /* 2 REG_CPWM2_8814B */ #define BIT_SHIFT_L0S_TO_RCVY_NUM_8814B 16 #define BIT_MASK_L0S_TO_RCVY_NUM_8814B 0xff -#define BIT_L0S_TO_RCVY_NUM_8814B(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8814B) << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) -#define BIT_GET_L0S_TO_RCVY_NUM_8814B(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) & BIT_MASK_L0S_TO_RCVY_NUM_8814B) - +#define BIT_L0S_TO_RCVY_NUM_8814B(x) \ + (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8814B) \ + << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) +#define BITS_L0S_TO_RCVY_NUM_8814B \ + (BIT_MASK_L0S_TO_RCVY_NUM_8814B << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) +#define BIT_CLEAR_L0S_TO_RCVY_NUM_8814B(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8814B)) +#define BIT_GET_L0S_TO_RCVY_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) & \ + BIT_MASK_L0S_TO_RCVY_NUM_8814B) +#define BIT_SET_L0S_TO_RCVY_NUM_8814B(x, v) \ + (BIT_CLEAR_L0S_TO_RCVY_NUM_8814B(x) | BIT_L0S_TO_RCVY_NUM_8814B(v)) #define BIT_CPWM2_TOGGLING_8814B BIT(15) #define BIT_SHIFT_CPWM2_MOD_8814B 0 #define BIT_MASK_CPWM2_MOD_8814B 0x7fff -#define BIT_CPWM2_MOD_8814B(x) (((x) & BIT_MASK_CPWM2_MOD_8814B) << BIT_SHIFT_CPWM2_MOD_8814B) -#define BIT_GET_CPWM2_MOD_8814B(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8814B) & BIT_MASK_CPWM2_MOD_8814B) - - +#define BIT_CPWM2_MOD_8814B(x) \ + (((x) & BIT_MASK_CPWM2_MOD_8814B) << BIT_SHIFT_CPWM2_MOD_8814B) +#define BITS_CPWM2_MOD_8814B \ + (BIT_MASK_CPWM2_MOD_8814B << BIT_SHIFT_CPWM2_MOD_8814B) +#define BIT_CLEAR_CPWM2_MOD_8814B(x) ((x) & (~BITS_CPWM2_MOD_8814B)) +#define BIT_GET_CPWM2_MOD_8814B(x) \ + (((x) >> BIT_SHIFT_CPWM2_MOD_8814B) & BIT_MASK_CPWM2_MOD_8814B) +#define BIT_SET_CPWM2_MOD_8814B(x, v) \ + (BIT_CLEAR_CPWM2_MOD_8814B(x) | BIT_CPWM2_MOD_8814B(v)) /* 2 REG_TC0_CTRL_8814B */ #define BIT_TC0INT_EN_8814B BIT(26) @@ -2474,10 +4694,14 @@ #define BIT_SHIFT_TC0DATA_8814B 0 #define BIT_MASK_TC0DATA_8814B 0xffffff -#define BIT_TC0DATA_8814B(x) (((x) & BIT_MASK_TC0DATA_8814B) << BIT_SHIFT_TC0DATA_8814B) -#define BIT_GET_TC0DATA_8814B(x) (((x) >> BIT_SHIFT_TC0DATA_8814B) & BIT_MASK_TC0DATA_8814B) - - +#define BIT_TC0DATA_8814B(x) \ + (((x) & BIT_MASK_TC0DATA_8814B) << BIT_SHIFT_TC0DATA_8814B) +#define BITS_TC0DATA_8814B (BIT_MASK_TC0DATA_8814B << BIT_SHIFT_TC0DATA_8814B) +#define BIT_CLEAR_TC0DATA_8814B(x) ((x) & (~BITS_TC0DATA_8814B)) +#define BIT_GET_TC0DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC0DATA_8814B) & BIT_MASK_TC0DATA_8814B) +#define BIT_SET_TC0DATA_8814B(x, v) \ + (BIT_CLEAR_TC0DATA_8814B(x) | BIT_TC0DATA_8814B(v)) /* 2 REG_TC1_CTRL_8814B */ #define BIT_TC1INT_EN_8814B BIT(26) @@ -2486,10 +4710,14 @@ #define BIT_SHIFT_TC1DATA_8814B 0 #define BIT_MASK_TC1DATA_8814B 0xffffff -#define BIT_TC1DATA_8814B(x) (((x) & BIT_MASK_TC1DATA_8814B) << BIT_SHIFT_TC1DATA_8814B) -#define BIT_GET_TC1DATA_8814B(x) (((x) >> BIT_SHIFT_TC1DATA_8814B) & BIT_MASK_TC1DATA_8814B) - - +#define BIT_TC1DATA_8814B(x) \ + (((x) & BIT_MASK_TC1DATA_8814B) << BIT_SHIFT_TC1DATA_8814B) +#define BITS_TC1DATA_8814B (BIT_MASK_TC1DATA_8814B << BIT_SHIFT_TC1DATA_8814B) +#define BIT_CLEAR_TC1DATA_8814B(x) ((x) & (~BITS_TC1DATA_8814B)) +#define BIT_GET_TC1DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC1DATA_8814B) & BIT_MASK_TC1DATA_8814B) +#define BIT_SET_TC1DATA_8814B(x, v) \ + (BIT_CLEAR_TC1DATA_8814B(x) | BIT_TC1DATA_8814B(v)) /* 2 REG_TC2_CTRL_8814B */ #define BIT_TC2INT_EN_8814B BIT(26) @@ -2498,10 +4726,14 @@ #define BIT_SHIFT_TC2DATA_8814B 0 #define BIT_MASK_TC2DATA_8814B 0xffffff -#define BIT_TC2DATA_8814B(x) (((x) & BIT_MASK_TC2DATA_8814B) << BIT_SHIFT_TC2DATA_8814B) -#define BIT_GET_TC2DATA_8814B(x) (((x) >> BIT_SHIFT_TC2DATA_8814B) & BIT_MASK_TC2DATA_8814B) - - +#define BIT_TC2DATA_8814B(x) \ + (((x) & BIT_MASK_TC2DATA_8814B) << BIT_SHIFT_TC2DATA_8814B) +#define BITS_TC2DATA_8814B (BIT_MASK_TC2DATA_8814B << BIT_SHIFT_TC2DATA_8814B) +#define BIT_CLEAR_TC2DATA_8814B(x) ((x) & (~BITS_TC2DATA_8814B)) +#define BIT_GET_TC2DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC2DATA_8814B) & BIT_MASK_TC2DATA_8814B) +#define BIT_SET_TC2DATA_8814B(x, v) \ + (BIT_CLEAR_TC2DATA_8814B(x) | BIT_TC2DATA_8814B(v)) /* 2 REG_TC3_CTRL_8814B */ #define BIT_TC3INT_EN_8814B BIT(26) @@ -2510,10 +4742,14 @@ #define BIT_SHIFT_TC3DATA_8814B 0 #define BIT_MASK_TC3DATA_8814B 0xffffff -#define BIT_TC3DATA_8814B(x) (((x) & BIT_MASK_TC3DATA_8814B) << BIT_SHIFT_TC3DATA_8814B) -#define BIT_GET_TC3DATA_8814B(x) (((x) >> BIT_SHIFT_TC3DATA_8814B) & BIT_MASK_TC3DATA_8814B) - - +#define BIT_TC3DATA_8814B(x) \ + (((x) & BIT_MASK_TC3DATA_8814B) << BIT_SHIFT_TC3DATA_8814B) +#define BITS_TC3DATA_8814B (BIT_MASK_TC3DATA_8814B << BIT_SHIFT_TC3DATA_8814B) +#define BIT_CLEAR_TC3DATA_8814B(x) ((x) & (~BITS_TC3DATA_8814B)) +#define BIT_GET_TC3DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC3DATA_8814B) & BIT_MASK_TC3DATA_8814B) +#define BIT_SET_TC3DATA_8814B(x, v) \ + (BIT_CLEAR_TC3DATA_8814B(x) | BIT_TC3DATA_8814B(v)) /* 2 REG_TC4_CTRL_8814B */ #define BIT_TC4INT_EN_8814B BIT(26) @@ -2522,19 +4758,28 @@ #define BIT_SHIFT_TC4DATA_8814B 0 #define BIT_MASK_TC4DATA_8814B 0xffffff -#define BIT_TC4DATA_8814B(x) (((x) & BIT_MASK_TC4DATA_8814B) << BIT_SHIFT_TC4DATA_8814B) -#define BIT_GET_TC4DATA_8814B(x) (((x) >> BIT_SHIFT_TC4DATA_8814B) & BIT_MASK_TC4DATA_8814B) - - +#define BIT_TC4DATA_8814B(x) \ + (((x) & BIT_MASK_TC4DATA_8814B) << BIT_SHIFT_TC4DATA_8814B) +#define BITS_TC4DATA_8814B (BIT_MASK_TC4DATA_8814B << BIT_SHIFT_TC4DATA_8814B) +#define BIT_CLEAR_TC4DATA_8814B(x) ((x) & (~BITS_TC4DATA_8814B)) +#define BIT_GET_TC4DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC4DATA_8814B) & BIT_MASK_TC4DATA_8814B) +#define BIT_SET_TC4DATA_8814B(x, v) \ + (BIT_CLEAR_TC4DATA_8814B(x) | BIT_TC4DATA_8814B(v)) /* 2 REG_TCUNIT_BASE_8814B */ #define BIT_SHIFT_TCUNIT_BASE_8814B 0 #define BIT_MASK_TCUNIT_BASE_8814B 0x3fff -#define BIT_TCUNIT_BASE_8814B(x) (((x) & BIT_MASK_TCUNIT_BASE_8814B) << BIT_SHIFT_TCUNIT_BASE_8814B) -#define BIT_GET_TCUNIT_BASE_8814B(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8814B) & BIT_MASK_TCUNIT_BASE_8814B) - - +#define BIT_TCUNIT_BASE_8814B(x) \ + (((x) & BIT_MASK_TCUNIT_BASE_8814B) << BIT_SHIFT_TCUNIT_BASE_8814B) +#define BITS_TCUNIT_BASE_8814B \ + (BIT_MASK_TCUNIT_BASE_8814B << BIT_SHIFT_TCUNIT_BASE_8814B) +#define BIT_CLEAR_TCUNIT_BASE_8814B(x) ((x) & (~BITS_TCUNIT_BASE_8814B)) +#define BIT_GET_TCUNIT_BASE_8814B(x) \ + (((x) >> BIT_SHIFT_TCUNIT_BASE_8814B) & BIT_MASK_TCUNIT_BASE_8814B) +#define BIT_SET_TCUNIT_BASE_8814B(x, v) \ + (BIT_CLEAR_TCUNIT_BASE_8814B(x) | BIT_TCUNIT_BASE_8814B(v)) /* 2 REG_TC5_CTRL_8814B */ #define BIT_TC5INT_EN_8814B BIT(26) @@ -2543,10 +4788,14 @@ #define BIT_SHIFT_TC5DATA_8814B 0 #define BIT_MASK_TC5DATA_8814B 0xffffff -#define BIT_TC5DATA_8814B(x) (((x) & BIT_MASK_TC5DATA_8814B) << BIT_SHIFT_TC5DATA_8814B) -#define BIT_GET_TC5DATA_8814B(x) (((x) >> BIT_SHIFT_TC5DATA_8814B) & BIT_MASK_TC5DATA_8814B) - - +#define BIT_TC5DATA_8814B(x) \ + (((x) & BIT_MASK_TC5DATA_8814B) << BIT_SHIFT_TC5DATA_8814B) +#define BITS_TC5DATA_8814B (BIT_MASK_TC5DATA_8814B << BIT_SHIFT_TC5DATA_8814B) +#define BIT_CLEAR_TC5DATA_8814B(x) ((x) & (~BITS_TC5DATA_8814B)) +#define BIT_GET_TC5DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC5DATA_8814B) & BIT_MASK_TC5DATA_8814B) +#define BIT_SET_TC5DATA_8814B(x, v) \ + (BIT_CLEAR_TC5DATA_8814B(x) | BIT_TC5DATA_8814B(v)) /* 2 REG_TC6_CTRL_8814B */ #define BIT_TC6INT_EN_8814B BIT(26) @@ -2555,154 +4804,155 @@ #define BIT_SHIFT_TC6DATA_8814B 0 #define BIT_MASK_TC6DATA_8814B 0xffffff -#define BIT_TC6DATA_8814B(x) (((x) & BIT_MASK_TC6DATA_8814B) << BIT_SHIFT_TC6DATA_8814B) -#define BIT_GET_TC6DATA_8814B(x) (((x) >> BIT_SHIFT_TC6DATA_8814B) & BIT_MASK_TC6DATA_8814B) - - - -/* 2 REG_MBIST_FAIL_8814B */ - -#define BIT_SHIFT_8051_MBIST_FAIL_8814B 26 -#define BIT_MASK_8051_MBIST_FAIL_8814B 0x7 -#define BIT_8051_MBIST_FAIL_8814B(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8814B) << BIT_SHIFT_8051_MBIST_FAIL_8814B) -#define BIT_GET_8051_MBIST_FAIL_8814B(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8814B) & BIT_MASK_8051_MBIST_FAIL_8814B) - - - -#define BIT_SHIFT_USB_MBIST_FAIL_8814B 24 -#define BIT_MASK_USB_MBIST_FAIL_8814B 0x3 -#define BIT_USB_MBIST_FAIL_8814B(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8814B) << BIT_SHIFT_USB_MBIST_FAIL_8814B) -#define BIT_GET_USB_MBIST_FAIL_8814B(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8814B) & BIT_MASK_USB_MBIST_FAIL_8814B) - - - -#define BIT_SHIFT_PCIE_MBIST_FAIL_8814B 16 -#define BIT_MASK_PCIE_MBIST_FAIL_8814B 0x3f -#define BIT_PCIE_MBIST_FAIL_8814B(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8814B) << BIT_SHIFT_PCIE_MBIST_FAIL_8814B) -#define BIT_GET_PCIE_MBIST_FAIL_8814B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8814B) & BIT_MASK_PCIE_MBIST_FAIL_8814B) - - - -#define BIT_SHIFT_MAC_MBIST_FAIL_8814B 0 -#define BIT_MASK_MAC_MBIST_FAIL_8814B 0xfff -#define BIT_MAC_MBIST_FAIL_8814B(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_8814B) << BIT_SHIFT_MAC_MBIST_FAIL_8814B) -#define BIT_GET_MAC_MBIST_FAIL_8814B(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8814B) & BIT_MASK_MAC_MBIST_FAIL_8814B) - - - -/* 2 REG_MBIST_START_PAUSE_8814B */ - -#define BIT_SHIFT_8051_MBIST_START_PAUSE_8814B 26 -#define BIT_MASK_8051_MBIST_START_PAUSE_8814B 0x7 -#define BIT_8051_MBIST_START_PAUSE_8814B(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8814B) << BIT_SHIFT_8051_MBIST_START_PAUSE_8814B) -#define BIT_GET_8051_MBIST_START_PAUSE_8814B(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8814B) & BIT_MASK_8051_MBIST_START_PAUSE_8814B) - - - -#define BIT_SHIFT_USB_MBIST_START_PAUSE_8814B 24 -#define BIT_MASK_USB_MBIST_START_PAUSE_8814B 0x3 -#define BIT_USB_MBIST_START_PAUSE_8814B(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8814B) << BIT_SHIFT_USB_MBIST_START_PAUSE_8814B) -#define BIT_GET_USB_MBIST_START_PAUSE_8814B(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8814B) & BIT_MASK_USB_MBIST_START_PAUSE_8814B) - - - -#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8814B 16 -#define BIT_MASK_PCIE_MBIST_START_PAUSE_8814B 0x3f -#define BIT_PCIE_MBIST_START_PAUSE_8814B(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8814B) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8814B) -#define BIT_GET_PCIE_MBIST_START_PAUSE_8814B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8814B) & BIT_MASK_PCIE_MBIST_START_PAUSE_8814B) - - - -#define BIT_SHIFT_MAC_MBIST_START_PAUSE_8814B 0 -#define BIT_MASK_MAC_MBIST_START_PAUSE_8814B 0xfff -#define BIT_MAC_MBIST_START_PAUSE_8814B(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8814B) << BIT_SHIFT_MAC_MBIST_START_PAUSE_8814B) -#define BIT_GET_MAC_MBIST_START_PAUSE_8814B(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8814B) & BIT_MASK_MAC_MBIST_START_PAUSE_8814B) - - - -/* 2 REG_MBIST_DONE_8814B */ +#define BIT_TC6DATA_8814B(x) \ + (((x) & BIT_MASK_TC6DATA_8814B) << BIT_SHIFT_TC6DATA_8814B) +#define BITS_TC6DATA_8814B (BIT_MASK_TC6DATA_8814B << BIT_SHIFT_TC6DATA_8814B) +#define BIT_CLEAR_TC6DATA_8814B(x) ((x) & (~BITS_TC6DATA_8814B)) +#define BIT_GET_TC6DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC6DATA_8814B) & BIT_MASK_TC6DATA_8814B) +#define BIT_SET_TC6DATA_8814B(x, v) \ + (BIT_CLEAR_TC6DATA_8814B(x) | BIT_TC6DATA_8814B(v)) -#define BIT_SHIFT_8051_MBIST_DONE_8814B 26 -#define BIT_MASK_8051_MBIST_DONE_8814B 0x7 -#define BIT_8051_MBIST_DONE_8814B(x) (((x) & BIT_MASK_8051_MBIST_DONE_8814B) << BIT_SHIFT_8051_MBIST_DONE_8814B) -#define BIT_GET_8051_MBIST_DONE_8814B(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8814B) & BIT_MASK_8051_MBIST_DONE_8814B) - - - -#define BIT_SHIFT_USB_MBIST_DONE_8814B 24 -#define BIT_MASK_USB_MBIST_DONE_8814B 0x3 -#define BIT_USB_MBIST_DONE_8814B(x) (((x) & BIT_MASK_USB_MBIST_DONE_8814B) << BIT_SHIFT_USB_MBIST_DONE_8814B) -#define BIT_GET_USB_MBIST_DONE_8814B(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8814B) & BIT_MASK_USB_MBIST_DONE_8814B) - - - -#define BIT_SHIFT_PCIE_MBIST_DONE_8814B 16 -#define BIT_MASK_PCIE_MBIST_DONE_8814B 0x3f -#define BIT_PCIE_MBIST_DONE_8814B(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8814B) << BIT_SHIFT_PCIE_MBIST_DONE_8814B) -#define BIT_GET_PCIE_MBIST_DONE_8814B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8814B) & BIT_MASK_PCIE_MBIST_DONE_8814B) - - - -#define BIT_SHIFT_MAC_MBIST_DONE_8814B 0 -#define BIT_MASK_MAC_MBIST_DONE_8814B 0xfff -#define BIT_MAC_MBIST_DONE_8814B(x) (((x) & BIT_MASK_MAC_MBIST_DONE_8814B) << BIT_SHIFT_MAC_MBIST_DONE_8814B) -#define BIT_GET_MAC_MBIST_DONE_8814B(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8814B) & BIT_MASK_MAC_MBIST_DONE_8814B) - - - -/* 2 REG_MBIST_FAIL_NRML_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_MBIST_FAIL_NRML_8814B 0 -#define BIT_MASK_MBIST_FAIL_NRML_8814B 0xffffffffL -#define BIT_MBIST_FAIL_NRML_8814B(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_8814B) << BIT_SHIFT_MBIST_FAIL_NRML_8814B) -#define BIT_GET_MBIST_FAIL_NRML_8814B(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8814B) & BIT_MASK_MBIST_FAIL_NRML_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_AES_DECRPT_DATA_8814B */ #define BIT_SHIFT_IPS_CFG_ADDR_8814B 0 #define BIT_MASK_IPS_CFG_ADDR_8814B 0xff -#define BIT_IPS_CFG_ADDR_8814B(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8814B) << BIT_SHIFT_IPS_CFG_ADDR_8814B) -#define BIT_GET_IPS_CFG_ADDR_8814B(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8814B) & BIT_MASK_IPS_CFG_ADDR_8814B) - - +#define BIT_IPS_CFG_ADDR_8814B(x) \ + (((x) & BIT_MASK_IPS_CFG_ADDR_8814B) << BIT_SHIFT_IPS_CFG_ADDR_8814B) +#define BITS_IPS_CFG_ADDR_8814B \ + (BIT_MASK_IPS_CFG_ADDR_8814B << BIT_SHIFT_IPS_CFG_ADDR_8814B) +#define BIT_CLEAR_IPS_CFG_ADDR_8814B(x) ((x) & (~BITS_IPS_CFG_ADDR_8814B)) +#define BIT_GET_IPS_CFG_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8814B) & BIT_MASK_IPS_CFG_ADDR_8814B) +#define BIT_SET_IPS_CFG_ADDR_8814B(x, v) \ + (BIT_CLEAR_IPS_CFG_ADDR_8814B(x) | BIT_IPS_CFG_ADDR_8814B(v)) /* 2 REG_AES_DECRPT_CFG_8814B */ #define BIT_SHIFT_IPS_CFG_DATA_8814B 0 #define BIT_MASK_IPS_CFG_DATA_8814B 0xffffffffL -#define BIT_IPS_CFG_DATA_8814B(x) (((x) & BIT_MASK_IPS_CFG_DATA_8814B) << BIT_SHIFT_IPS_CFG_DATA_8814B) -#define BIT_GET_IPS_CFG_DATA_8814B(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8814B) & BIT_MASK_IPS_CFG_DATA_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_IPS_CFG_DATA_8814B(x) \ + (((x) & BIT_MASK_IPS_CFG_DATA_8814B) << BIT_SHIFT_IPS_CFG_DATA_8814B) +#define BITS_IPS_CFG_DATA_8814B \ + (BIT_MASK_IPS_CFG_DATA_8814B << BIT_SHIFT_IPS_CFG_DATA_8814B) +#define BIT_CLEAR_IPS_CFG_DATA_8814B(x) ((x) & (~BITS_IPS_CFG_DATA_8814B)) +#define BIT_GET_IPS_CFG_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_DATA_8814B) & BIT_MASK_IPS_CFG_DATA_8814B) +#define BIT_SET_IPS_CFG_DATA_8814B(x, v) \ + (BIT_CLEAR_IPS_CFG_DATA_8814B(x) | BIT_IPS_CFG_DATA_8814B(v)) + +/* 2 REG_HIOE_CTRL_8814B */ +#define BIT_HIOE_WRITE_REQ_8814B BIT(30) +#define BIT_HIOE_READ_REQ_8814B BIT(29) +#define BIT_INST_FORMAT_ERR_8814B BIT(25) +#define BIT_OP_TIMEOUT_ERR_8814B BIT(24) + +#define BIT_SHIFT_HIOE_OP_TIMEOUT_8814B 16 +#define BIT_MASK_HIOE_OP_TIMEOUT_8814B 0xff +#define BIT_HIOE_OP_TIMEOUT_8814B(x) \ + (((x) & BIT_MASK_HIOE_OP_TIMEOUT_8814B) \ + << BIT_SHIFT_HIOE_OP_TIMEOUT_8814B) +#define BITS_HIOE_OP_TIMEOUT_8814B \ + (BIT_MASK_HIOE_OP_TIMEOUT_8814B << BIT_SHIFT_HIOE_OP_TIMEOUT_8814B) +#define BIT_CLEAR_HIOE_OP_TIMEOUT_8814B(x) ((x) & (~BITS_HIOE_OP_TIMEOUT_8814B)) +#define BIT_GET_HIOE_OP_TIMEOUT_8814B(x) \ + (((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT_8814B) & \ + BIT_MASK_HIOE_OP_TIMEOUT_8814B) +#define BIT_SET_HIOE_OP_TIMEOUT_8814B(x, v) \ + (BIT_CLEAR_HIOE_OP_TIMEOUT_8814B(x) | BIT_HIOE_OP_TIMEOUT_8814B(v)) + +#define BIT_SHIFT_BITDATA_CHECKSUM_8814B 0 +#define BIT_MASK_BITDATA_CHECKSUM_8814B 0xffff +#define BIT_BITDATA_CHECKSUM_8814B(x) \ + (((x) & BIT_MASK_BITDATA_CHECKSUM_8814B) \ + << BIT_SHIFT_BITDATA_CHECKSUM_8814B) +#define BITS_BITDATA_CHECKSUM_8814B \ + (BIT_MASK_BITDATA_CHECKSUM_8814B << BIT_SHIFT_BITDATA_CHECKSUM_8814B) +#define BIT_CLEAR_BITDATA_CHECKSUM_8814B(x) \ + ((x) & (~BITS_BITDATA_CHECKSUM_8814B)) +#define BIT_GET_BITDATA_CHECKSUM_8814B(x) \ + (((x) >> BIT_SHIFT_BITDATA_CHECKSUM_8814B) & \ + BIT_MASK_BITDATA_CHECKSUM_8814B) +#define BIT_SET_BITDATA_CHECKSUM_8814B(x, v) \ + (BIT_CLEAR_BITDATA_CHECKSUM_8814B(x) | BIT_BITDATA_CHECKSUM_8814B(v)) + +/* 2 REG_HIOE_CFG_FILE_8814B */ + +#define BIT_SHIFT_TXBF_END_ADDR_8814B 16 +#define BIT_MASK_TXBF_END_ADDR_8814B 0xffff +#define BIT_TXBF_END_ADDR_8814B(x) \ + (((x) & BIT_MASK_TXBF_END_ADDR_8814B) << BIT_SHIFT_TXBF_END_ADDR_8814B) +#define BITS_TXBF_END_ADDR_8814B \ + (BIT_MASK_TXBF_END_ADDR_8814B << BIT_SHIFT_TXBF_END_ADDR_8814B) +#define BIT_CLEAR_TXBF_END_ADDR_8814B(x) ((x) & (~BITS_TXBF_END_ADDR_8814B)) +#define BIT_GET_TXBF_END_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_TXBF_END_ADDR_8814B) & BIT_MASK_TXBF_END_ADDR_8814B) +#define BIT_SET_TXBF_END_ADDR_8814B(x, v) \ + (BIT_CLEAR_TXBF_END_ADDR_8814B(x) | BIT_TXBF_END_ADDR_8814B(v)) + +#define BIT_SHIFT_TXBF_STR_ADDR_8814B 0 +#define BIT_MASK_TXBF_STR_ADDR_8814B 0xffff +#define BIT_TXBF_STR_ADDR_8814B(x) \ + (((x) & BIT_MASK_TXBF_STR_ADDR_8814B) << BIT_SHIFT_TXBF_STR_ADDR_8814B) +#define BITS_TXBF_STR_ADDR_8814B \ + (BIT_MASK_TXBF_STR_ADDR_8814B << BIT_SHIFT_TXBF_STR_ADDR_8814B) +#define BIT_CLEAR_TXBF_STR_ADDR_8814B(x) ((x) & (~BITS_TXBF_STR_ADDR_8814B)) +#define BIT_GET_TXBF_STR_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_TXBF_STR_ADDR_8814B) & BIT_MASK_TXBF_STR_ADDR_8814B) +#define BIT_SET_TXBF_STR_ADDR_8814B(x, v) \ + (BIT_CLEAR_TXBF_STR_ADDR_8814B(x) | BIT_TXBF_STR_ADDR_8814B(v)) /* 2 REG_TMETER_8814B */ #define BIT_TEMP_VALID_8814B BIT(31) #define BIT_SHIFT_TEMP_VALUE_8814B 24 #define BIT_MASK_TEMP_VALUE_8814B 0x3f -#define BIT_TEMP_VALUE_8814B(x) (((x) & BIT_MASK_TEMP_VALUE_8814B) << BIT_SHIFT_TEMP_VALUE_8814B) -#define BIT_GET_TEMP_VALUE_8814B(x) (((x) >> BIT_SHIFT_TEMP_VALUE_8814B) & BIT_MASK_TEMP_VALUE_8814B) - - +#define BIT_TEMP_VALUE_8814B(x) \ + (((x) & BIT_MASK_TEMP_VALUE_8814B) << BIT_SHIFT_TEMP_VALUE_8814B) +#define BITS_TEMP_VALUE_8814B \ + (BIT_MASK_TEMP_VALUE_8814B << BIT_SHIFT_TEMP_VALUE_8814B) +#define BIT_CLEAR_TEMP_VALUE_8814B(x) ((x) & (~BITS_TEMP_VALUE_8814B)) +#define BIT_GET_TEMP_VALUE_8814B(x) \ + (((x) >> BIT_SHIFT_TEMP_VALUE_8814B) & BIT_MASK_TEMP_VALUE_8814B) +#define BIT_SET_TEMP_VALUE_8814B(x, v) \ + (BIT_CLEAR_TEMP_VALUE_8814B(x) | BIT_TEMP_VALUE_8814B(v)) #define BIT_SHIFT_REG_TMETER_TIMER_8814B 8 #define BIT_MASK_REG_TMETER_TIMER_8814B 0xfff -#define BIT_REG_TMETER_TIMER_8814B(x) (((x) & BIT_MASK_REG_TMETER_TIMER_8814B) << BIT_SHIFT_REG_TMETER_TIMER_8814B) -#define BIT_GET_REG_TMETER_TIMER_8814B(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8814B) & BIT_MASK_REG_TMETER_TIMER_8814B) - - +#define BIT_REG_TMETER_TIMER_8814B(x) \ + (((x) & BIT_MASK_REG_TMETER_TIMER_8814B) \ + << BIT_SHIFT_REG_TMETER_TIMER_8814B) +#define BITS_REG_TMETER_TIMER_8814B \ + (BIT_MASK_REG_TMETER_TIMER_8814B << BIT_SHIFT_REG_TMETER_TIMER_8814B) +#define BIT_CLEAR_REG_TMETER_TIMER_8814B(x) \ + ((x) & (~BITS_REG_TMETER_TIMER_8814B)) +#define BIT_GET_REG_TMETER_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8814B) & \ + BIT_MASK_REG_TMETER_TIMER_8814B) +#define BIT_SET_REG_TMETER_TIMER_8814B(x, v) \ + (BIT_CLEAR_REG_TMETER_TIMER_8814B(x) | BIT_REG_TMETER_TIMER_8814B(v)) #define BIT_SHIFT_REG_TEMP_DELTA_8814B 2 #define BIT_MASK_REG_TEMP_DELTA_8814B 0x3f -#define BIT_REG_TEMP_DELTA_8814B(x) (((x) & BIT_MASK_REG_TEMP_DELTA_8814B) << BIT_SHIFT_REG_TEMP_DELTA_8814B) -#define BIT_GET_REG_TEMP_DELTA_8814B(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8814B) & BIT_MASK_REG_TEMP_DELTA_8814B) - +#define BIT_REG_TEMP_DELTA_8814B(x) \ + (((x) & BIT_MASK_REG_TEMP_DELTA_8814B) \ + << BIT_SHIFT_REG_TEMP_DELTA_8814B) +#define BITS_REG_TEMP_DELTA_8814B \ + (BIT_MASK_REG_TEMP_DELTA_8814B << BIT_SHIFT_REG_TEMP_DELTA_8814B) +#define BIT_CLEAR_REG_TEMP_DELTA_8814B(x) ((x) & (~BITS_REG_TEMP_DELTA_8814B)) +#define BIT_GET_REG_TEMP_DELTA_8814B(x) \ + (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8814B) & \ + BIT_MASK_REG_TEMP_DELTA_8814B) +#define BIT_SET_REG_TEMP_DELTA_8814B(x, v) \ + (BIT_CLEAR_REG_TEMP_DELTA_8814B(x) | BIT_REG_TEMP_DELTA_8814B(v)) #define BIT_REG_TMETER_EN_8814B BIT(0) @@ -2710,16 +4960,33 @@ #define BIT_SHIFT_OSC_32K_CLKGEN_0_8814B 16 #define BIT_MASK_OSC_32K_CLKGEN_0_8814B 0xffff -#define BIT_OSC_32K_CLKGEN_0_8814B(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8814B) << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) -#define BIT_GET_OSC_32K_CLKGEN_0_8814B(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) & BIT_MASK_OSC_32K_CLKGEN_0_8814B) - - +#define BIT_OSC_32K_CLKGEN_0_8814B(x) \ + (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8814B) \ + << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) +#define BITS_OSC_32K_CLKGEN_0_8814B \ + (BIT_MASK_OSC_32K_CLKGEN_0_8814B << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) +#define BIT_CLEAR_OSC_32K_CLKGEN_0_8814B(x) \ + ((x) & (~BITS_OSC_32K_CLKGEN_0_8814B)) +#define BIT_GET_OSC_32K_CLKGEN_0_8814B(x) \ + (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) & \ + BIT_MASK_OSC_32K_CLKGEN_0_8814B) +#define BIT_SET_OSC_32K_CLKGEN_0_8814B(x, v) \ + (BIT_CLEAR_OSC_32K_CLKGEN_0_8814B(x) | BIT_OSC_32K_CLKGEN_0_8814B(v)) #define BIT_SHIFT_OSC_32K_RES_COMP_8814B 4 #define BIT_MASK_OSC_32K_RES_COMP_8814B 0x3 -#define BIT_OSC_32K_RES_COMP_8814B(x) (((x) & BIT_MASK_OSC_32K_RES_COMP_8814B) << BIT_SHIFT_OSC_32K_RES_COMP_8814B) -#define BIT_GET_OSC_32K_RES_COMP_8814B(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8814B) & BIT_MASK_OSC_32K_RES_COMP_8814B) - +#define BIT_OSC_32K_RES_COMP_8814B(x) \ + (((x) & BIT_MASK_OSC_32K_RES_COMP_8814B) \ + << BIT_SHIFT_OSC_32K_RES_COMP_8814B) +#define BITS_OSC_32K_RES_COMP_8814B \ + (BIT_MASK_OSC_32K_RES_COMP_8814B << BIT_SHIFT_OSC_32K_RES_COMP_8814B) +#define BIT_CLEAR_OSC_32K_RES_COMP_8814B(x) \ + ((x) & (~BITS_OSC_32K_RES_COMP_8814B)) +#define BIT_GET_OSC_32K_RES_COMP_8814B(x) \ + (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8814B) & \ + BIT_MASK_OSC_32K_RES_COMP_8814B) +#define BIT_SET_OSC_32K_RES_COMP_8814B(x, v) \ + (BIT_CLEAR_OSC_32K_RES_COMP_8814B(x) | BIT_OSC_32K_RES_COMP_8814B(v)) #define BIT_OSC_32K_OUT_SEL_8814B BIT(3) #define BIT_ISO_WL_2_OSC_32K_8814B BIT(1) @@ -2731,17 +4998,33 @@ #define BIT_SHIFT_CAL_32K_REG_ADDR_8814B 16 #define BIT_MASK_CAL_32K_REG_ADDR_8814B 0x3f -#define BIT_CAL_32K_REG_ADDR_8814B(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR_8814B) << BIT_SHIFT_CAL_32K_REG_ADDR_8814B) -#define BIT_GET_CAL_32K_REG_ADDR_8814B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8814B) & BIT_MASK_CAL_32K_REG_ADDR_8814B) - - +#define BIT_CAL_32K_REG_ADDR_8814B(x) \ + (((x) & BIT_MASK_CAL_32K_REG_ADDR_8814B) \ + << BIT_SHIFT_CAL_32K_REG_ADDR_8814B) +#define BITS_CAL_32K_REG_ADDR_8814B \ + (BIT_MASK_CAL_32K_REG_ADDR_8814B << BIT_SHIFT_CAL_32K_REG_ADDR_8814B) +#define BIT_CLEAR_CAL_32K_REG_ADDR_8814B(x) \ + ((x) & (~BITS_CAL_32K_REG_ADDR_8814B)) +#define BIT_GET_CAL_32K_REG_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8814B) & \ + BIT_MASK_CAL_32K_REG_ADDR_8814B) +#define BIT_SET_CAL_32K_REG_ADDR_8814B(x, v) \ + (BIT_CLEAR_CAL_32K_REG_ADDR_8814B(x) | BIT_CAL_32K_REG_ADDR_8814B(v)) #define BIT_SHIFT_CAL_32K_REG_DATA_8814B 0 #define BIT_MASK_CAL_32K_REG_DATA_8814B 0xffff -#define BIT_CAL_32K_REG_DATA_8814B(x) (((x) & BIT_MASK_CAL_32K_REG_DATA_8814B) << BIT_SHIFT_CAL_32K_REG_DATA_8814B) -#define BIT_GET_CAL_32K_REG_DATA_8814B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8814B) & BIT_MASK_CAL_32K_REG_DATA_8814B) - - +#define BIT_CAL_32K_REG_DATA_8814B(x) \ + (((x) & BIT_MASK_CAL_32K_REG_DATA_8814B) \ + << BIT_SHIFT_CAL_32K_REG_DATA_8814B) +#define BITS_CAL_32K_REG_DATA_8814B \ + (BIT_MASK_CAL_32K_REG_DATA_8814B << BIT_SHIFT_CAL_32K_REG_DATA_8814B) +#define BIT_CLEAR_CAL_32K_REG_DATA_8814B(x) \ + ((x) & (~BITS_CAL_32K_REG_DATA_8814B)) +#define BIT_GET_CAL_32K_REG_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8814B) & \ + BIT_MASK_CAL_32K_REG_DATA_8814B) +#define BIT_SET_CAL_32K_REG_DATA_8814B(x, v) \ + (BIT_CLEAR_CAL_32K_REG_DATA_8814B(x) | BIT_CAL_32K_REG_DATA_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -2749,95 +5032,183 @@ #define BIT_SHIFT_C2HEVT_MSG_V1_8814B 0 #define BIT_MASK_C2HEVT_MSG_V1_8814B 0xffffffffL -#define BIT_C2HEVT_MSG_V1_8814B(x) (((x) & BIT_MASK_C2HEVT_MSG_V1_8814B) << BIT_SHIFT_C2HEVT_MSG_V1_8814B) -#define BIT_GET_C2HEVT_MSG_V1_8814B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8814B) & BIT_MASK_C2HEVT_MSG_V1_8814B) - - +#define BIT_C2HEVT_MSG_V1_8814B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_V1_8814B) << BIT_SHIFT_C2HEVT_MSG_V1_8814B) +#define BITS_C2HEVT_MSG_V1_8814B \ + (BIT_MASK_C2HEVT_MSG_V1_8814B << BIT_SHIFT_C2HEVT_MSG_V1_8814B) +#define BIT_CLEAR_C2HEVT_MSG_V1_8814B(x) ((x) & (~BITS_C2HEVT_MSG_V1_8814B)) +#define BIT_GET_C2HEVT_MSG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8814B) & BIT_MASK_C2HEVT_MSG_V1_8814B) +#define BIT_SET_C2HEVT_MSG_V1_8814B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_V1_8814B(x) | BIT_C2HEVT_MSG_V1_8814B(v)) /* 2 REG_C2HEVT_1_8814B */ #define BIT_SHIFT_C2HEVT_MSG_1_8814B 0 #define BIT_MASK_C2HEVT_MSG_1_8814B 0xffffffffL -#define BIT_C2HEVT_MSG_1_8814B(x) (((x) & BIT_MASK_C2HEVT_MSG_1_8814B) << BIT_SHIFT_C2HEVT_MSG_1_8814B) -#define BIT_GET_C2HEVT_MSG_1_8814B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8814B) & BIT_MASK_C2HEVT_MSG_1_8814B) - - +#define BIT_C2HEVT_MSG_1_8814B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_1_8814B) << BIT_SHIFT_C2HEVT_MSG_1_8814B) +#define BITS_C2HEVT_MSG_1_8814B \ + (BIT_MASK_C2HEVT_MSG_1_8814B << BIT_SHIFT_C2HEVT_MSG_1_8814B) +#define BIT_CLEAR_C2HEVT_MSG_1_8814B(x) ((x) & (~BITS_C2HEVT_MSG_1_8814B)) +#define BIT_GET_C2HEVT_MSG_1_8814B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8814B) & BIT_MASK_C2HEVT_MSG_1_8814B) +#define BIT_SET_C2HEVT_MSG_1_8814B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_1_8814B(x) | BIT_C2HEVT_MSG_1_8814B(v)) /* 2 REG_C2HEVT_2_8814B */ #define BIT_SHIFT_C2HEVT_MSG_2_8814B 0 #define BIT_MASK_C2HEVT_MSG_2_8814B 0xffffffffL -#define BIT_C2HEVT_MSG_2_8814B(x) (((x) & BIT_MASK_C2HEVT_MSG_2_8814B) << BIT_SHIFT_C2HEVT_MSG_2_8814B) -#define BIT_GET_C2HEVT_MSG_2_8814B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8814B) & BIT_MASK_C2HEVT_MSG_2_8814B) - - +#define BIT_C2HEVT_MSG_2_8814B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_2_8814B) << BIT_SHIFT_C2HEVT_MSG_2_8814B) +#define BITS_C2HEVT_MSG_2_8814B \ + (BIT_MASK_C2HEVT_MSG_2_8814B << BIT_SHIFT_C2HEVT_MSG_2_8814B) +#define BIT_CLEAR_C2HEVT_MSG_2_8814B(x) ((x) & (~BITS_C2HEVT_MSG_2_8814B)) +#define BIT_GET_C2HEVT_MSG_2_8814B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8814B) & BIT_MASK_C2HEVT_MSG_2_8814B) +#define BIT_SET_C2HEVT_MSG_2_8814B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_2_8814B(x) | BIT_C2HEVT_MSG_2_8814B(v)) /* 2 REG_C2HEVT_3_8814B */ #define BIT_SHIFT_C2HEVT_MSG_3_8814B 0 #define BIT_MASK_C2HEVT_MSG_3_8814B 0xffffffffL -#define BIT_C2HEVT_MSG_3_8814B(x) (((x) & BIT_MASK_C2HEVT_MSG_3_8814B) << BIT_SHIFT_C2HEVT_MSG_3_8814B) -#define BIT_GET_C2HEVT_MSG_3_8814B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8814B) & BIT_MASK_C2HEVT_MSG_3_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_C2HEVT_MSG_3_8814B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_3_8814B) << BIT_SHIFT_C2HEVT_MSG_3_8814B) +#define BITS_C2HEVT_MSG_3_8814B \ + (BIT_MASK_C2HEVT_MSG_3_8814B << BIT_SHIFT_C2HEVT_MSG_3_8814B) +#define BIT_CLEAR_C2HEVT_MSG_3_8814B(x) ((x) & (~BITS_C2HEVT_MSG_3_8814B)) +#define BIT_GET_C2HEVT_MSG_3_8814B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8814B) & BIT_MASK_C2HEVT_MSG_3_8814B) +#define BIT_SET_C2HEVT_MSG_3_8814B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_3_8814B(x) | BIT_C2HEVT_MSG_3_8814B(v)) + +/* 2 REG_RXDESC_BUFF_RPTR_8814B */ + +#define BIT_SHIFT_RXDESC_BUFF_RPTR_8814B 0 +#define BIT_MASK_RXDESC_BUFF_RPTR_8814B 0xffffffffL +#define BIT_RXDESC_BUFF_RPTR_8814B(x) \ + (((x) & BIT_MASK_RXDESC_BUFF_RPTR_8814B) \ + << BIT_SHIFT_RXDESC_BUFF_RPTR_8814B) +#define BITS_RXDESC_BUFF_RPTR_8814B \ + (BIT_MASK_RXDESC_BUFF_RPTR_8814B << BIT_SHIFT_RXDESC_BUFF_RPTR_8814B) +#define BIT_CLEAR_RXDESC_BUFF_RPTR_8814B(x) \ + ((x) & (~BITS_RXDESC_BUFF_RPTR_8814B)) +#define BIT_GET_RXDESC_BUFF_RPTR_8814B(x) \ + (((x) >> BIT_SHIFT_RXDESC_BUFF_RPTR_8814B) & \ + BIT_MASK_RXDESC_BUFF_RPTR_8814B) +#define BIT_SET_RXDESC_BUFF_RPTR_8814B(x, v) \ + (BIT_CLEAR_RXDESC_BUFF_RPTR_8814B(x) | BIT_RXDESC_BUFF_RPTR_8814B(v)) + +/* 2 REG_RXDESC_BUFF_WPTR_8814B */ + +#define BIT_SHIFT_RXDESC_BUFF_WPTR_8814B 0 +#define BIT_MASK_RXDESC_BUFF_WPTR_8814B 0xffffffffL +#define BIT_RXDESC_BUFF_WPTR_8814B(x) \ + (((x) & BIT_MASK_RXDESC_BUFF_WPTR_8814B) \ + << BIT_SHIFT_RXDESC_BUFF_WPTR_8814B) +#define BITS_RXDESC_BUFF_WPTR_8814B \ + (BIT_MASK_RXDESC_BUFF_WPTR_8814B << BIT_SHIFT_RXDESC_BUFF_WPTR_8814B) +#define BIT_CLEAR_RXDESC_BUFF_WPTR_8814B(x) \ + ((x) & (~BITS_RXDESC_BUFF_WPTR_8814B)) +#define BIT_GET_RXDESC_BUFF_WPTR_8814B(x) \ + (((x) >> BIT_SHIFT_RXDESC_BUFF_WPTR_8814B) & \ + BIT_MASK_RXDESC_BUFF_WPTR_8814B) +#define BIT_SET_RXDESC_BUFF_WPTR_8814B(x, v) \ + (BIT_CLEAR_RXDESC_BUFF_WPTR_8814B(x) | BIT_RXDESC_BUFF_WPTR_8814B(v)) /* 2 REG_SW_DEFINED_PAGE1_8814B */ #define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B 0 #define BIT_MASK_SW_DEFINED_PAGE1_V1_8814B 0xffffffffL -#define BIT_SW_DEFINED_PAGE1_V1_8814B(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8814B) << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) -#define BIT_GET_SW_DEFINED_PAGE1_V1_8814B(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) & BIT_MASK_SW_DEFINED_PAGE1_V1_8814B) - - +#define BIT_SW_DEFINED_PAGE1_V1_8814B(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8814B) \ + << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) +#define BITS_SW_DEFINED_PAGE1_V1_8814B \ + (BIT_MASK_SW_DEFINED_PAGE1_V1_8814B \ + << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) +#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8814B(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE1_V1_8814B)) +#define BIT_GET_SW_DEFINED_PAGE1_V1_8814B(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) & \ + BIT_MASK_SW_DEFINED_PAGE1_V1_8814B) +#define BIT_SET_SW_DEFINED_PAGE1_V1_8814B(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1_V1_8814B(x) | \ + BIT_SW_DEFINED_PAGE1_V1_8814B(v)) /* 2 REG_SW_DEFINED_PAGE2_8814B */ #define BIT_SHIFT_SW_DEFINED_PAGE2_8814B 0 #define BIT_MASK_SW_DEFINED_PAGE2_8814B 0xffffffffL -#define BIT_SW_DEFINED_PAGE2_8814B(x) (((x) & BIT_MASK_SW_DEFINED_PAGE2_8814B) << BIT_SHIFT_SW_DEFINED_PAGE2_8814B) -#define BIT_GET_SW_DEFINED_PAGE2_8814B(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8814B) & BIT_MASK_SW_DEFINED_PAGE2_8814B) - - +#define BIT_SW_DEFINED_PAGE2_8814B(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE2_8814B) \ + << BIT_SHIFT_SW_DEFINED_PAGE2_8814B) +#define BITS_SW_DEFINED_PAGE2_8814B \ + (BIT_MASK_SW_DEFINED_PAGE2_8814B << BIT_SHIFT_SW_DEFINED_PAGE2_8814B) +#define BIT_CLEAR_SW_DEFINED_PAGE2_8814B(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE2_8814B)) +#define BIT_GET_SW_DEFINED_PAGE2_8814B(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8814B) & \ + BIT_MASK_SW_DEFINED_PAGE2_8814B) +#define BIT_SET_SW_DEFINED_PAGE2_8814B(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE2_8814B(x) | BIT_SW_DEFINED_PAGE2_8814B(v)) /* 2 REG_MCUTST_I_8814B */ #define BIT_SHIFT_MCUDMSG_I_8814B 0 #define BIT_MASK_MCUDMSG_I_8814B 0xffffffffL -#define BIT_MCUDMSG_I_8814B(x) (((x) & BIT_MASK_MCUDMSG_I_8814B) << BIT_SHIFT_MCUDMSG_I_8814B) -#define BIT_GET_MCUDMSG_I_8814B(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8814B) & BIT_MASK_MCUDMSG_I_8814B) - - +#define BIT_MCUDMSG_I_8814B(x) \ + (((x) & BIT_MASK_MCUDMSG_I_8814B) << BIT_SHIFT_MCUDMSG_I_8814B) +#define BITS_MCUDMSG_I_8814B \ + (BIT_MASK_MCUDMSG_I_8814B << BIT_SHIFT_MCUDMSG_I_8814B) +#define BIT_CLEAR_MCUDMSG_I_8814B(x) ((x) & (~BITS_MCUDMSG_I_8814B)) +#define BIT_GET_MCUDMSG_I_8814B(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_I_8814B) & BIT_MASK_MCUDMSG_I_8814B) +#define BIT_SET_MCUDMSG_I_8814B(x, v) \ + (BIT_CLEAR_MCUDMSG_I_8814B(x) | BIT_MCUDMSG_I_8814B(v)) /* 2 REG_MCUTST_II_8814B */ #define BIT_SHIFT_MCUDMSG_II_8814B 0 #define BIT_MASK_MCUDMSG_II_8814B 0xffffffffL -#define BIT_MCUDMSG_II_8814B(x) (((x) & BIT_MASK_MCUDMSG_II_8814B) << BIT_SHIFT_MCUDMSG_II_8814B) -#define BIT_GET_MCUDMSG_II_8814B(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8814B) & BIT_MASK_MCUDMSG_II_8814B) - - +#define BIT_MCUDMSG_II_8814B(x) \ + (((x) & BIT_MASK_MCUDMSG_II_8814B) << BIT_SHIFT_MCUDMSG_II_8814B) +#define BITS_MCUDMSG_II_8814B \ + (BIT_MASK_MCUDMSG_II_8814B << BIT_SHIFT_MCUDMSG_II_8814B) +#define BIT_CLEAR_MCUDMSG_II_8814B(x) ((x) & (~BITS_MCUDMSG_II_8814B)) +#define BIT_GET_MCUDMSG_II_8814B(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_II_8814B) & BIT_MASK_MCUDMSG_II_8814B) +#define BIT_SET_MCUDMSG_II_8814B(x, v) \ + (BIT_CLEAR_MCUDMSG_II_8814B(x) | BIT_MCUDMSG_II_8814B(v)) /* 2 REG_FMETHR_8814B */ #define BIT_FMSG_INT_8814B BIT(31) #define BIT_SHIFT_FW_MSG_8814B 0 #define BIT_MASK_FW_MSG_8814B 0xffffffffL -#define BIT_FW_MSG_8814B(x) (((x) & BIT_MASK_FW_MSG_8814B) << BIT_SHIFT_FW_MSG_8814B) -#define BIT_GET_FW_MSG_8814B(x) (((x) >> BIT_SHIFT_FW_MSG_8814B) & BIT_MASK_FW_MSG_8814B) - - +#define BIT_FW_MSG_8814B(x) \ + (((x) & BIT_MASK_FW_MSG_8814B) << BIT_SHIFT_FW_MSG_8814B) +#define BITS_FW_MSG_8814B (BIT_MASK_FW_MSG_8814B << BIT_SHIFT_FW_MSG_8814B) +#define BIT_CLEAR_FW_MSG_8814B(x) ((x) & (~BITS_FW_MSG_8814B)) +#define BIT_GET_FW_MSG_8814B(x) \ + (((x) >> BIT_SHIFT_FW_MSG_8814B) & BIT_MASK_FW_MSG_8814B) +#define BIT_SET_FW_MSG_8814B(x, v) \ + (BIT_CLEAR_FW_MSG_8814B(x) | BIT_FW_MSG_8814B(v)) /* 2 REG_HMETFR_8814B */ #define BIT_SHIFT_HRCV_MSG_8814B 24 #define BIT_MASK_HRCV_MSG_8814B 0xff -#define BIT_HRCV_MSG_8814B(x) (((x) & BIT_MASK_HRCV_MSG_8814B) << BIT_SHIFT_HRCV_MSG_8814B) -#define BIT_GET_HRCV_MSG_8814B(x) (((x) >> BIT_SHIFT_HRCV_MSG_8814B) & BIT_MASK_HRCV_MSG_8814B) - +#define BIT_HRCV_MSG_8814B(x) \ + (((x) & BIT_MASK_HRCV_MSG_8814B) << BIT_SHIFT_HRCV_MSG_8814B) +#define BITS_HRCV_MSG_8814B \ + (BIT_MASK_HRCV_MSG_8814B << BIT_SHIFT_HRCV_MSG_8814B) +#define BIT_CLEAR_HRCV_MSG_8814B(x) ((x) & (~BITS_HRCV_MSG_8814B)) +#define BIT_GET_HRCV_MSG_8814B(x) \ + (((x) >> BIT_SHIFT_HRCV_MSG_8814B) & BIT_MASK_HRCV_MSG_8814B) +#define BIT_SET_HRCV_MSG_8814B(x, v) \ + (BIT_CLEAR_HRCV_MSG_8814B(x) | BIT_HRCV_MSG_8814B(v)) #define BIT_INT_BOX3_8814B BIT(3) #define BIT_INT_BOX2_8814B BIT(2) @@ -2848,91 +5219,113 @@ #define BIT_SHIFT_HOST_MSG_0_8814B 0 #define BIT_MASK_HOST_MSG_0_8814B 0xffffffffL -#define BIT_HOST_MSG_0_8814B(x) (((x) & BIT_MASK_HOST_MSG_0_8814B) << BIT_SHIFT_HOST_MSG_0_8814B) -#define BIT_GET_HOST_MSG_0_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8814B) & BIT_MASK_HOST_MSG_0_8814B) - - +#define BIT_HOST_MSG_0_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_0_8814B) << BIT_SHIFT_HOST_MSG_0_8814B) +#define BITS_HOST_MSG_0_8814B \ + (BIT_MASK_HOST_MSG_0_8814B << BIT_SHIFT_HOST_MSG_0_8814B) +#define BIT_CLEAR_HOST_MSG_0_8814B(x) ((x) & (~BITS_HOST_MSG_0_8814B)) +#define BIT_GET_HOST_MSG_0_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_0_8814B) & BIT_MASK_HOST_MSG_0_8814B) +#define BIT_SET_HOST_MSG_0_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_0_8814B(x) | BIT_HOST_MSG_0_8814B(v)) /* 2 REG_HMEBOX1_8814B */ #define BIT_SHIFT_HOST_MSG_1_8814B 0 #define BIT_MASK_HOST_MSG_1_8814B 0xffffffffL -#define BIT_HOST_MSG_1_8814B(x) (((x) & BIT_MASK_HOST_MSG_1_8814B) << BIT_SHIFT_HOST_MSG_1_8814B) -#define BIT_GET_HOST_MSG_1_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8814B) & BIT_MASK_HOST_MSG_1_8814B) - - +#define BIT_HOST_MSG_1_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_1_8814B) << BIT_SHIFT_HOST_MSG_1_8814B) +#define BITS_HOST_MSG_1_8814B \ + (BIT_MASK_HOST_MSG_1_8814B << BIT_SHIFT_HOST_MSG_1_8814B) +#define BIT_CLEAR_HOST_MSG_1_8814B(x) ((x) & (~BITS_HOST_MSG_1_8814B)) +#define BIT_GET_HOST_MSG_1_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_1_8814B) & BIT_MASK_HOST_MSG_1_8814B) +#define BIT_SET_HOST_MSG_1_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_1_8814B(x) | BIT_HOST_MSG_1_8814B(v)) /* 2 REG_HMEBOX2_8814B */ #define BIT_SHIFT_HOST_MSG_2_8814B 0 #define BIT_MASK_HOST_MSG_2_8814B 0xffffffffL -#define BIT_HOST_MSG_2_8814B(x) (((x) & BIT_MASK_HOST_MSG_2_8814B) << BIT_SHIFT_HOST_MSG_2_8814B) -#define BIT_GET_HOST_MSG_2_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8814B) & BIT_MASK_HOST_MSG_2_8814B) - - +#define BIT_HOST_MSG_2_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_2_8814B) << BIT_SHIFT_HOST_MSG_2_8814B) +#define BITS_HOST_MSG_2_8814B \ + (BIT_MASK_HOST_MSG_2_8814B << BIT_SHIFT_HOST_MSG_2_8814B) +#define BIT_CLEAR_HOST_MSG_2_8814B(x) ((x) & (~BITS_HOST_MSG_2_8814B)) +#define BIT_GET_HOST_MSG_2_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_2_8814B) & BIT_MASK_HOST_MSG_2_8814B) +#define BIT_SET_HOST_MSG_2_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_2_8814B(x) | BIT_HOST_MSG_2_8814B(v)) /* 2 REG_HMEBOX3_8814B */ #define BIT_SHIFT_HOST_MSG_3_8814B 0 #define BIT_MASK_HOST_MSG_3_8814B 0xffffffffL -#define BIT_HOST_MSG_3_8814B(x) (((x) & BIT_MASK_HOST_MSG_3_8814B) << BIT_SHIFT_HOST_MSG_3_8814B) -#define BIT_GET_HOST_MSG_3_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8814B) & BIT_MASK_HOST_MSG_3_8814B) - - - -/* 2 REG_LLT_INIT_8814B */ - -#define BIT_SHIFT_LLTE_RWM_8814B 30 -#define BIT_MASK_LLTE_RWM_8814B 0x3 -#define BIT_LLTE_RWM_8814B(x) (((x) & BIT_MASK_LLTE_RWM_8814B) << BIT_SHIFT_LLTE_RWM_8814B) -#define BIT_GET_LLTE_RWM_8814B(x) (((x) >> BIT_SHIFT_LLTE_RWM_8814B) & BIT_MASK_LLTE_RWM_8814B) - - - -#define BIT_SHIFT_LLTINI_PDATA_V1_8814B 16 -#define BIT_MASK_LLTINI_PDATA_V1_8814B 0xfff -#define BIT_LLTINI_PDATA_V1_8814B(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8814B) << BIT_SHIFT_LLTINI_PDATA_V1_8814B) -#define BIT_GET_LLTINI_PDATA_V1_8814B(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8814B) & BIT_MASK_LLTINI_PDATA_V1_8814B) - - - -#define BIT_SHIFT_LLTINI_HDATA_V1_8814B 0 -#define BIT_MASK_LLTINI_HDATA_V1_8814B 0xfff -#define BIT_LLTINI_HDATA_V1_8814B(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8814B) << BIT_SHIFT_LLTINI_HDATA_V1_8814B) -#define BIT_GET_LLTINI_HDATA_V1_8814B(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8814B) & BIT_MASK_LLTINI_HDATA_V1_8814B) - - - -/* 2 REG_LLT_INIT_ADDR_8814B */ - -#define BIT_SHIFT_LLTINI_ADDR_V1_8814B 0 -#define BIT_MASK_LLTINI_ADDR_V1_8814B 0xfff -#define BIT_LLTINI_ADDR_V1_8814B(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8814B) << BIT_SHIFT_LLTINI_ADDR_V1_8814B) -#define BIT_GET_LLTINI_ADDR_V1_8814B(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8814B) & BIT_MASK_LLTINI_ADDR_V1_8814B) - +#define BIT_HOST_MSG_3_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_3_8814B) << BIT_SHIFT_HOST_MSG_3_8814B) +#define BITS_HOST_MSG_3_8814B \ + (BIT_MASK_HOST_MSG_3_8814B << BIT_SHIFT_HOST_MSG_3_8814B) +#define BIT_CLEAR_HOST_MSG_3_8814B(x) ((x) & (~BITS_HOST_MSG_3_8814B)) +#define BIT_GET_HOST_MSG_3_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_3_8814B) & BIT_MASK_HOST_MSG_3_8814B) +#define BIT_SET_HOST_MSG_3_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_3_8814B(x) | BIT_HOST_MSG_3_8814B(v)) + +/* 2 REG_RXDESC_BUFF_BNDY_8814B */ + +#define BIT_SHIFT_RXDESC_BUFF_BNDY_8814B 0 +#define BIT_MASK_RXDESC_BUFF_BNDY_8814B 0xffffffffL +#define BIT_RXDESC_BUFF_BNDY_8814B(x) \ + (((x) & BIT_MASK_RXDESC_BUFF_BNDY_8814B) \ + << BIT_SHIFT_RXDESC_BUFF_BNDY_8814B) +#define BITS_RXDESC_BUFF_BNDY_8814B \ + (BIT_MASK_RXDESC_BUFF_BNDY_8814B << BIT_SHIFT_RXDESC_BUFF_BNDY_8814B) +#define BIT_CLEAR_RXDESC_BUFF_BNDY_8814B(x) \ + ((x) & (~BITS_RXDESC_BUFF_BNDY_8814B)) +#define BIT_GET_RXDESC_BUFF_BNDY_8814B(x) \ + (((x) >> BIT_SHIFT_RXDESC_BUFF_BNDY_8814B) & \ + BIT_MASK_RXDESC_BUFF_BNDY_8814B) +#define BIT_SET_RXDESC_BUFF_BNDY_8814B(x, v) \ + (BIT_CLEAR_RXDESC_BUFF_BNDY_8814B(x) | BIT_RXDESC_BUFF_BNDY_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_BB_ACCESS_CTRL_8814B */ #define BIT_SHIFT_BB_WRITE_READ_8814B 30 #define BIT_MASK_BB_WRITE_READ_8814B 0x3 -#define BIT_BB_WRITE_READ_8814B(x) (((x) & BIT_MASK_BB_WRITE_READ_8814B) << BIT_SHIFT_BB_WRITE_READ_8814B) -#define BIT_GET_BB_WRITE_READ_8814B(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8814B) & BIT_MASK_BB_WRITE_READ_8814B) - - +#define BIT_BB_WRITE_READ_8814B(x) \ + (((x) & BIT_MASK_BB_WRITE_READ_8814B) << BIT_SHIFT_BB_WRITE_READ_8814B) +#define BITS_BB_WRITE_READ_8814B \ + (BIT_MASK_BB_WRITE_READ_8814B << BIT_SHIFT_BB_WRITE_READ_8814B) +#define BIT_CLEAR_BB_WRITE_READ_8814B(x) ((x) & (~BITS_BB_WRITE_READ_8814B)) +#define BIT_GET_BB_WRITE_READ_8814B(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_READ_8814B) & BIT_MASK_BB_WRITE_READ_8814B) +#define BIT_SET_BB_WRITE_READ_8814B(x, v) \ + (BIT_CLEAR_BB_WRITE_READ_8814B(x) | BIT_BB_WRITE_READ_8814B(v)) #define BIT_SHIFT_BB_WRITE_EN_8814B 12 #define BIT_MASK_BB_WRITE_EN_8814B 0xf -#define BIT_BB_WRITE_EN_8814B(x) (((x) & BIT_MASK_BB_WRITE_EN_8814B) << BIT_SHIFT_BB_WRITE_EN_8814B) -#define BIT_GET_BB_WRITE_EN_8814B(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_8814B) & BIT_MASK_BB_WRITE_EN_8814B) - - +#define BIT_BB_WRITE_EN_8814B(x) \ + (((x) & BIT_MASK_BB_WRITE_EN_8814B) << BIT_SHIFT_BB_WRITE_EN_8814B) +#define BITS_BB_WRITE_EN_8814B \ + (BIT_MASK_BB_WRITE_EN_8814B << BIT_SHIFT_BB_WRITE_EN_8814B) +#define BIT_CLEAR_BB_WRITE_EN_8814B(x) ((x) & (~BITS_BB_WRITE_EN_8814B)) +#define BIT_GET_BB_WRITE_EN_8814B(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN_8814B) & BIT_MASK_BB_WRITE_EN_8814B) +#define BIT_SET_BB_WRITE_EN_8814B(x, v) \ + (BIT_CLEAR_BB_WRITE_EN_8814B(x) | BIT_BB_WRITE_EN_8814B(v)) #define BIT_SHIFT_BB_ADDR_8814B 2 #define BIT_MASK_BB_ADDR_8814B 0x1ff -#define BIT_BB_ADDR_8814B(x) (((x) & BIT_MASK_BB_ADDR_8814B) << BIT_SHIFT_BB_ADDR_8814B) -#define BIT_GET_BB_ADDR_8814B(x) (((x) >> BIT_SHIFT_BB_ADDR_8814B) & BIT_MASK_BB_ADDR_8814B) - +#define BIT_BB_ADDR_8814B(x) \ + (((x) & BIT_MASK_BB_ADDR_8814B) << BIT_SHIFT_BB_ADDR_8814B) +#define BITS_BB_ADDR_8814B (BIT_MASK_BB_ADDR_8814B << BIT_SHIFT_BB_ADDR_8814B) +#define BIT_CLEAR_BB_ADDR_8814B(x) ((x) & (~BITS_BB_ADDR_8814B)) +#define BIT_GET_BB_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_BB_ADDR_8814B) & BIT_MASK_BB_ADDR_8814B) +#define BIT_SET_BB_ADDR_8814B(x, v) \ + (BIT_CLEAR_BB_ADDR_8814B(x) | BIT_BB_ADDR_8814B(v)) #define BIT_BB_ERRACC_8814B BIT(0) @@ -2940,112 +5333,229 @@ #define BIT_SHIFT_BB_DATA_8814B 0 #define BIT_MASK_BB_DATA_8814B 0xffffffffL -#define BIT_BB_DATA_8814B(x) (((x) & BIT_MASK_BB_DATA_8814B) << BIT_SHIFT_BB_DATA_8814B) -#define BIT_GET_BB_DATA_8814B(x) (((x) >> BIT_SHIFT_BB_DATA_8814B) & BIT_MASK_BB_DATA_8814B) - - +#define BIT_BB_DATA_8814B(x) \ + (((x) & BIT_MASK_BB_DATA_8814B) << BIT_SHIFT_BB_DATA_8814B) +#define BITS_BB_DATA_8814B (BIT_MASK_BB_DATA_8814B << BIT_SHIFT_BB_DATA_8814B) +#define BIT_CLEAR_BB_DATA_8814B(x) ((x) & (~BITS_BB_DATA_8814B)) +#define BIT_GET_BB_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_BB_DATA_8814B) & BIT_MASK_BB_DATA_8814B) +#define BIT_SET_BB_DATA_8814B(x, v) \ + (BIT_CLEAR_BB_DATA_8814B(x) | BIT_BB_DATA_8814B(v)) /* 2 REG_HMEBOX_E0_8814B */ #define BIT_SHIFT_HMEBOX_E0_8814B 0 #define BIT_MASK_HMEBOX_E0_8814B 0xffffffffL -#define BIT_HMEBOX_E0_8814B(x) (((x) & BIT_MASK_HMEBOX_E0_8814B) << BIT_SHIFT_HMEBOX_E0_8814B) -#define BIT_GET_HMEBOX_E0_8814B(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8814B) & BIT_MASK_HMEBOX_E0_8814B) - - +#define BIT_HMEBOX_E0_8814B(x) \ + (((x) & BIT_MASK_HMEBOX_E0_8814B) << BIT_SHIFT_HMEBOX_E0_8814B) +#define BITS_HMEBOX_E0_8814B \ + (BIT_MASK_HMEBOX_E0_8814B << BIT_SHIFT_HMEBOX_E0_8814B) +#define BIT_CLEAR_HMEBOX_E0_8814B(x) ((x) & (~BITS_HMEBOX_E0_8814B)) +#define BIT_GET_HMEBOX_E0_8814B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E0_8814B) & BIT_MASK_HMEBOX_E0_8814B) +#define BIT_SET_HMEBOX_E0_8814B(x, v) \ + (BIT_CLEAR_HMEBOX_E0_8814B(x) | BIT_HMEBOX_E0_8814B(v)) /* 2 REG_HMEBOX_E1_8814B */ #define BIT_SHIFT_HMEBOX_E1_8814B 0 #define BIT_MASK_HMEBOX_E1_8814B 0xffffffffL -#define BIT_HMEBOX_E1_8814B(x) (((x) & BIT_MASK_HMEBOX_E1_8814B) << BIT_SHIFT_HMEBOX_E1_8814B) -#define BIT_GET_HMEBOX_E1_8814B(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8814B) & BIT_MASK_HMEBOX_E1_8814B) - - +#define BIT_HMEBOX_E1_8814B(x) \ + (((x) & BIT_MASK_HMEBOX_E1_8814B) << BIT_SHIFT_HMEBOX_E1_8814B) +#define BITS_HMEBOX_E1_8814B \ + (BIT_MASK_HMEBOX_E1_8814B << BIT_SHIFT_HMEBOX_E1_8814B) +#define BIT_CLEAR_HMEBOX_E1_8814B(x) ((x) & (~BITS_HMEBOX_E1_8814B)) +#define BIT_GET_HMEBOX_E1_8814B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E1_8814B) & BIT_MASK_HMEBOX_E1_8814B) +#define BIT_SET_HMEBOX_E1_8814B(x, v) \ + (BIT_CLEAR_HMEBOX_E1_8814B(x) | BIT_HMEBOX_E1_8814B(v)) /* 2 REG_HMEBOX_E2_8814B */ #define BIT_SHIFT_HMEBOX_E2_8814B 0 #define BIT_MASK_HMEBOX_E2_8814B 0xffffffffL -#define BIT_HMEBOX_E2_8814B(x) (((x) & BIT_MASK_HMEBOX_E2_8814B) << BIT_SHIFT_HMEBOX_E2_8814B) -#define BIT_GET_HMEBOX_E2_8814B(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8814B) & BIT_MASK_HMEBOX_E2_8814B) - - +#define BIT_HMEBOX_E2_8814B(x) \ + (((x) & BIT_MASK_HMEBOX_E2_8814B) << BIT_SHIFT_HMEBOX_E2_8814B) +#define BITS_HMEBOX_E2_8814B \ + (BIT_MASK_HMEBOX_E2_8814B << BIT_SHIFT_HMEBOX_E2_8814B) +#define BIT_CLEAR_HMEBOX_E2_8814B(x) ((x) & (~BITS_HMEBOX_E2_8814B)) +#define BIT_GET_HMEBOX_E2_8814B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E2_8814B) & BIT_MASK_HMEBOX_E2_8814B) +#define BIT_SET_HMEBOX_E2_8814B(x, v) \ + (BIT_CLEAR_HMEBOX_E2_8814B(x) | BIT_HMEBOX_E2_8814B(v)) /* 2 REG_HMEBOX_E3_8814B */ #define BIT_SHIFT_HMEBOX_E3_8814B 0 #define BIT_MASK_HMEBOX_E3_8814B 0xffffffffL -#define BIT_HMEBOX_E3_8814B(x) (((x) & BIT_MASK_HMEBOX_E3_8814B) << BIT_SHIFT_HMEBOX_E3_8814B) -#define BIT_GET_HMEBOX_E3_8814B(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8814B) & BIT_MASK_HMEBOX_E3_8814B) - - +#define BIT_HMEBOX_E3_8814B(x) \ + (((x) & BIT_MASK_HMEBOX_E3_8814B) << BIT_SHIFT_HMEBOX_E3_8814B) +#define BITS_HMEBOX_E3_8814B \ + (BIT_MASK_HMEBOX_E3_8814B << BIT_SHIFT_HMEBOX_E3_8814B) +#define BIT_CLEAR_HMEBOX_E3_8814B(x) ((x) & (~BITS_HMEBOX_E3_8814B)) +#define BIT_GET_HMEBOX_E3_8814B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E3_8814B) & BIT_MASK_HMEBOX_E3_8814B) +#define BIT_SET_HMEBOX_E3_8814B(x, v) \ + (BIT_CLEAR_HMEBOX_E3_8814B(x) | BIT_HMEBOX_E3_8814B(v)) /* 2 REG_CR_EXT_8814B */ #define BIT_SHIFT_PHY_REQ_DELAY_8814B 24 #define BIT_MASK_PHY_REQ_DELAY_8814B 0xf -#define BIT_PHY_REQ_DELAY_8814B(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8814B) << BIT_SHIFT_PHY_REQ_DELAY_8814B) -#define BIT_GET_PHY_REQ_DELAY_8814B(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8814B) & BIT_MASK_PHY_REQ_DELAY_8814B) - - +#define BIT_PHY_REQ_DELAY_8814B(x) \ + (((x) & BIT_MASK_PHY_REQ_DELAY_8814B) << BIT_SHIFT_PHY_REQ_DELAY_8814B) +#define BITS_PHY_REQ_DELAY_8814B \ + (BIT_MASK_PHY_REQ_DELAY_8814B << BIT_SHIFT_PHY_REQ_DELAY_8814B) +#define BIT_CLEAR_PHY_REQ_DELAY_8814B(x) ((x) & (~BITS_PHY_REQ_DELAY_8814B)) +#define BIT_GET_PHY_REQ_DELAY_8814B(x) \ + (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8814B) & BIT_MASK_PHY_REQ_DELAY_8814B) +#define BIT_SET_PHY_REQ_DELAY_8814B(x, v) \ + (BIT_CLEAR_PHY_REQ_DELAY_8814B(x) | BIT_PHY_REQ_DELAY_8814B(v)) /* 2 REG_NOT_VALID_8814B */ +#define BIT_FW_FIFO_PTR_RST_8814B BIT(18) +#define BIT_PHY_FIFO_PTR_RST_8814B BIT(17) #define BIT_SPD_DOWN_8814B BIT(16) /* 2 REG_NOT_VALID_8814B */ #define BIT_SHIFT_NETYPE4_8814B 4 #define BIT_MASK_NETYPE4_8814B 0x3 -#define BIT_NETYPE4_8814B(x) (((x) & BIT_MASK_NETYPE4_8814B) << BIT_SHIFT_NETYPE4_8814B) -#define BIT_GET_NETYPE4_8814B(x) (((x) >> BIT_SHIFT_NETYPE4_8814B) & BIT_MASK_NETYPE4_8814B) - - +#define BIT_NETYPE4_8814B(x) \ + (((x) & BIT_MASK_NETYPE4_8814B) << BIT_SHIFT_NETYPE4_8814B) +#define BITS_NETYPE4_8814B (BIT_MASK_NETYPE4_8814B << BIT_SHIFT_NETYPE4_8814B) +#define BIT_CLEAR_NETYPE4_8814B(x) ((x) & (~BITS_NETYPE4_8814B)) +#define BIT_GET_NETYPE4_8814B(x) \ + (((x) >> BIT_SHIFT_NETYPE4_8814B) & BIT_MASK_NETYPE4_8814B) +#define BIT_SET_NETYPE4_8814B(x, v) \ + (BIT_CLEAR_NETYPE4_8814B(x) | BIT_NETYPE4_8814B(v)) #define BIT_SHIFT_NETYPE3_8814B 2 #define BIT_MASK_NETYPE3_8814B 0x3 -#define BIT_NETYPE3_8814B(x) (((x) & BIT_MASK_NETYPE3_8814B) << BIT_SHIFT_NETYPE3_8814B) -#define BIT_GET_NETYPE3_8814B(x) (((x) >> BIT_SHIFT_NETYPE3_8814B) & BIT_MASK_NETYPE3_8814B) - - +#define BIT_NETYPE3_8814B(x) \ + (((x) & BIT_MASK_NETYPE3_8814B) << BIT_SHIFT_NETYPE3_8814B) +#define BITS_NETYPE3_8814B (BIT_MASK_NETYPE3_8814B << BIT_SHIFT_NETYPE3_8814B) +#define BIT_CLEAR_NETYPE3_8814B(x) ((x) & (~BITS_NETYPE3_8814B)) +#define BIT_GET_NETYPE3_8814B(x) \ + (((x) >> BIT_SHIFT_NETYPE3_8814B) & BIT_MASK_NETYPE3_8814B) +#define BIT_SET_NETYPE3_8814B(x, v) \ + (BIT_CLEAR_NETYPE3_8814B(x) | BIT_NETYPE3_8814B(v)) #define BIT_SHIFT_NETYPE2_8814B 0 #define BIT_MASK_NETYPE2_8814B 0x3 -#define BIT_NETYPE2_8814B(x) (((x) & BIT_MASK_NETYPE2_8814B) << BIT_SHIFT_NETYPE2_8814B) -#define BIT_GET_NETYPE2_8814B(x) (((x) >> BIT_SHIFT_NETYPE2_8814B) & BIT_MASK_NETYPE2_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_NETYPE2_8814B(x) \ + (((x) & BIT_MASK_NETYPE2_8814B) << BIT_SHIFT_NETYPE2_8814B) +#define BITS_NETYPE2_8814B (BIT_MASK_NETYPE2_8814B << BIT_SHIFT_NETYPE2_8814B) +#define BIT_CLEAR_NETYPE2_8814B(x) ((x) & (~BITS_NETYPE2_8814B)) +#define BIT_GET_NETYPE2_8814B(x) \ + (((x) >> BIT_SHIFT_NETYPE2_8814B) & BIT_MASK_NETYPE2_8814B) +#define BIT_SET_NETYPE2_8814B(x, v) \ + (BIT_CLEAR_NETYPE2_8814B(x) | BIT_NETYPE2_8814B(v)) + +/* 2 REG_TC9_CTRL_8814B */ +#define BIT_TC9INT_EN_8814B BIT(26) +#define BIT_TC9MODE_8814B BIT(25) +#define BIT_TC9EN_8814B BIT(24) + +#define BIT_SHIFT_TC9DATA_8814B 0 +#define BIT_MASK_TC9DATA_8814B 0xffffff +#define BIT_TC9DATA_8814B(x) \ + (((x) & BIT_MASK_TC9DATA_8814B) << BIT_SHIFT_TC9DATA_8814B) +#define BITS_TC9DATA_8814B (BIT_MASK_TC9DATA_8814B << BIT_SHIFT_TC9DATA_8814B) +#define BIT_CLEAR_TC9DATA_8814B(x) ((x) & (~BITS_TC9DATA_8814B)) +#define BIT_GET_TC9DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC9DATA_8814B) & BIT_MASK_TC9DATA_8814B) +#define BIT_SET_TC9DATA_8814B(x, v) \ + (BIT_CLEAR_TC9DATA_8814B(x) | BIT_TC9DATA_8814B(v)) + +/* 2 REG_TC10_CTRL_8814B */ +#define BIT_TC10INT_EN_8814B BIT(26) +#define BIT_TC10MODE_8814B BIT(25) +#define BIT_TC10EN_8814B BIT(24) + +#define BIT_SHIFT_TC10DATA_8814B 0 +#define BIT_MASK_TC10DATA_8814B 0xffffff +#define BIT_TC10DATA_8814B(x) \ + (((x) & BIT_MASK_TC10DATA_8814B) << BIT_SHIFT_TC10DATA_8814B) +#define BITS_TC10DATA_8814B \ + (BIT_MASK_TC10DATA_8814B << BIT_SHIFT_TC10DATA_8814B) +#define BIT_CLEAR_TC10DATA_8814B(x) ((x) & (~BITS_TC10DATA_8814B)) +#define BIT_GET_TC10DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC10DATA_8814B) & BIT_MASK_TC10DATA_8814B) +#define BIT_SET_TC10DATA_8814B(x, v) \ + (BIT_CLEAR_TC10DATA_8814B(x) | BIT_TC10DATA_8814B(v)) + +/* 2 REG_TC11_CTRL_8814B */ +#define BIT_TC11INT_EN_8814B BIT(26) +#define BIT_TC11MODE_8814B BIT(25) +#define BIT_TC11EN_8814B BIT(24) + +#define BIT_SHIFT_TC11DATA_8814B 0 +#define BIT_MASK_TC11DATA_8814B 0xffffff +#define BIT_TC11DATA_8814B(x) \ + (((x) & BIT_MASK_TC11DATA_8814B) << BIT_SHIFT_TC11DATA_8814B) +#define BITS_TC11DATA_8814B \ + (BIT_MASK_TC11DATA_8814B << BIT_SHIFT_TC11DATA_8814B) +#define BIT_CLEAR_TC11DATA_8814B(x) ((x) & (~BITS_TC11DATA_8814B)) +#define BIT_GET_TC11DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC11DATA_8814B) & BIT_MASK_TC11DATA_8814B) +#define BIT_SET_TC11DATA_8814B(x, v) \ + (BIT_CLEAR_TC11DATA_8814B(x) | BIT_TC11DATA_8814B(v)) + +/* 2 REG_TC12_CTRL_8814B */ +#define BIT_TC12INT_EN_8814B BIT(26) +#define BIT_TC12MODE_8814B BIT(25) +#define BIT_TC12EN_8814B BIT(24) + +#define BIT_SHIFT_TC12DATA_8814B 0 +#define BIT_MASK_TC12DATA_8814B 0xffffff +#define BIT_TC12DATA_8814B(x) \ + (((x) & BIT_MASK_TC12DATA_8814B) << BIT_SHIFT_TC12DATA_8814B) +#define BITS_TC12DATA_8814B \ + (BIT_MASK_TC12DATA_8814B << BIT_SHIFT_TC12DATA_8814B) +#define BIT_CLEAR_TC12DATA_8814B(x) ((x) & (~BITS_TC12DATA_8814B)) +#define BIT_GET_TC12DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC12DATA_8814B) & BIT_MASK_TC12DATA_8814B) +#define BIT_SET_TC12DATA_8814B(x, v) \ + (BIT_CLEAR_TC12DATA_8814B(x) | BIT_TC12DATA_8814B(v)) /* 2 REG_FWFF_8814B */ #define BIT_SHIFT_PKTNUM_TH_V1_8814B 24 #define BIT_MASK_PKTNUM_TH_V1_8814B 0xff -#define BIT_PKTNUM_TH_V1_8814B(x) (((x) & BIT_MASK_PKTNUM_TH_V1_8814B) << BIT_SHIFT_PKTNUM_TH_V1_8814B) -#define BIT_GET_PKTNUM_TH_V1_8814B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8814B) & BIT_MASK_PKTNUM_TH_V1_8814B) - - +#define BIT_PKTNUM_TH_V1_8814B(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V1_8814B) << BIT_SHIFT_PKTNUM_TH_V1_8814B) +#define BITS_PKTNUM_TH_V1_8814B \ + (BIT_MASK_PKTNUM_TH_V1_8814B << BIT_SHIFT_PKTNUM_TH_V1_8814B) +#define BIT_CLEAR_PKTNUM_TH_V1_8814B(x) ((x) & (~BITS_PKTNUM_TH_V1_8814B)) +#define BIT_GET_PKTNUM_TH_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8814B) & BIT_MASK_PKTNUM_TH_V1_8814B) +#define BIT_SET_PKTNUM_TH_V1_8814B(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V1_8814B(x) | BIT_PKTNUM_TH_V1_8814B(v)) #define BIT_SHIFT_TIMER_TH_8814B 16 #define BIT_MASK_TIMER_TH_8814B 0xff -#define BIT_TIMER_TH_8814B(x) (((x) & BIT_MASK_TIMER_TH_8814B) << BIT_SHIFT_TIMER_TH_8814B) -#define BIT_GET_TIMER_TH_8814B(x) (((x) >> BIT_SHIFT_TIMER_TH_8814B) & BIT_MASK_TIMER_TH_8814B) - - +#define BIT_TIMER_TH_8814B(x) \ + (((x) & BIT_MASK_TIMER_TH_8814B) << BIT_SHIFT_TIMER_TH_8814B) +#define BITS_TIMER_TH_8814B \ + (BIT_MASK_TIMER_TH_8814B << BIT_SHIFT_TIMER_TH_8814B) +#define BIT_CLEAR_TIMER_TH_8814B(x) ((x) & (~BITS_TIMER_TH_8814B)) +#define BIT_GET_TIMER_TH_8814B(x) \ + (((x) >> BIT_SHIFT_TIMER_TH_8814B) & BIT_MASK_TIMER_TH_8814B) +#define BIT_SET_TIMER_TH_8814B(x, v) \ + (BIT_CLEAR_TIMER_TH_8814B(x) | BIT_TIMER_TH_8814B(v)) #define BIT_SHIFT_RXPKT1ENADDR_8814B 0 #define BIT_MASK_RXPKT1ENADDR_8814B 0xffff -#define BIT_RXPKT1ENADDR_8814B(x) (((x) & BIT_MASK_RXPKT1ENADDR_8814B) << BIT_SHIFT_RXPKT1ENADDR_8814B) -#define BIT_GET_RXPKT1ENADDR_8814B(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8814B) & BIT_MASK_RXPKT1ENADDR_8814B) - - +#define BIT_RXPKT1ENADDR_8814B(x) \ + (((x) & BIT_MASK_RXPKT1ENADDR_8814B) << BIT_SHIFT_RXPKT1ENADDR_8814B) +#define BITS_RXPKT1ENADDR_8814B \ + (BIT_MASK_RXPKT1ENADDR_8814B << BIT_SHIFT_RXPKT1ENADDR_8814B) +#define BIT_CLEAR_RXPKT1ENADDR_8814B(x) ((x) & (~BITS_RXPKT1ENADDR_8814B)) +#define BIT_GET_RXPKT1ENADDR_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKT1ENADDR_8814B) & BIT_MASK_RXPKT1ENADDR_8814B) +#define BIT_SET_RXPKT1ENADDR_8814B(x, v) \ + (BIT_CLEAR_RXPKT1ENADDR_8814B(x) | BIT_RXPKT1ENADDR_8814B(v)) /* 2 REG_RXFF_PTR_V1_8814B */ @@ -3053,10 +5563,17 @@ #define BIT_SHIFT_RXFF0_RDPTR_V2_8814B 0 #define BIT_MASK_RXFF0_RDPTR_V2_8814B 0x3ffff -#define BIT_RXFF0_RDPTR_V2_8814B(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8814B) << BIT_SHIFT_RXFF0_RDPTR_V2_8814B) -#define BIT_GET_RXFF0_RDPTR_V2_8814B(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8814B) & BIT_MASK_RXFF0_RDPTR_V2_8814B) - - +#define BIT_RXFF0_RDPTR_V2_8814B(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V2_8814B) \ + << BIT_SHIFT_RXFF0_RDPTR_V2_8814B) +#define BITS_RXFF0_RDPTR_V2_8814B \ + (BIT_MASK_RXFF0_RDPTR_V2_8814B << BIT_SHIFT_RXFF0_RDPTR_V2_8814B) +#define BIT_CLEAR_RXFF0_RDPTR_V2_8814B(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8814B)) +#define BIT_GET_RXFF0_RDPTR_V2_8814B(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8814B) & \ + BIT_MASK_RXFF0_RDPTR_V2_8814B) +#define BIT_SET_RXFF0_RDPTR_V2_8814B(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V2_8814B(x) | BIT_RXFF0_RDPTR_V2_8814B(v)) /* 2 REG_RXFF_WTR_V1_8814B */ @@ -3064,10 +5581,17 @@ #define BIT_SHIFT_RXFF0_WTPTR_V2_8814B 0 #define BIT_MASK_RXFF0_WTPTR_V2_8814B 0x3ffff -#define BIT_RXFF0_WTPTR_V2_8814B(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8814B) << BIT_SHIFT_RXFF0_WTPTR_V2_8814B) -#define BIT_GET_RXFF0_WTPTR_V2_8814B(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8814B) & BIT_MASK_RXFF0_WTPTR_V2_8814B) - - +#define BIT_RXFF0_WTPTR_V2_8814B(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V2_8814B) \ + << BIT_SHIFT_RXFF0_WTPTR_V2_8814B) +#define BITS_RXFF0_WTPTR_V2_8814B \ + (BIT_MASK_RXFF0_WTPTR_V2_8814B << BIT_SHIFT_RXFF0_WTPTR_V2_8814B) +#define BIT_CLEAR_RXFF0_WTPTR_V2_8814B(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8814B)) +#define BIT_GET_RXFF0_WTPTR_V2_8814B(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8814B) & \ + BIT_MASK_RXFF0_WTPTR_V2_8814B) +#define BIT_SET_RXFF0_WTPTR_V2_8814B(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V2_8814B(x) | BIT_RXFF0_WTPTR_V2_8814B(v)) /* 2 REG_FE2IMR_8814B */ #define BIT__FE4ISR__IND_MSK_8814B BIT(29) @@ -3188,12 +5712,28 @@ #define BIT_FS_BCNERLY0_INT_8814B BIT(0) /* 2 REG_FE4IMR_8814B */ -#define BIT_FS_CLI3_TXPKTIN_INT_EN_8814B BIT(19) -#define BIT_FS_CLI2_TXPKTIN_INT_EN_8814B BIT(18) -#define BIT_FS_CLI1_TXPKTIN_INT_EN_8814B BIT(17) -#define BIT_FS_CLI0_TXPKTIN_INT_EN_8814B BIT(16) -#define BIT_FS_CLI3_RX_UMD0_INT_EN_8814B BIT(15) -#define BIT_FS_CLI3_RX_UMD1_INT_EN_8814B BIT(14) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_FS_CLI3_TXPKTIN_INT_EN_8814B BIT(19) +#define BIT_FS_CLI2_TXPKTIN_INT_EN_8814B BIT(18) +#define BIT_FS_CLI1_TXPKTIN_INT_EN_8814B BIT(17) +#define BIT_FS_CLI0_TXPKTIN_INT_EN_8814B BIT(16) +#define BIT_FS_CLI3_RX_UMD0_INT_EN_8814B BIT(15) +#define BIT_FS_CLI3_RX_UMD1_INT_EN_8814B BIT(14) #define BIT_FS_CLI3_RX_BMD0_INT_EN_8814B BIT(13) #define BIT_FS_CLI3_RX_BMD1_INT_EN_8814B BIT(12) #define BIT_FS_CLI2_RX_UMD0_INT_EN_8814B BIT(11) @@ -3210,6 +5750,25 @@ #define BIT_FS_CLI0_RX_BMD1_INT_EN_8814B BIT(0) /* 2 REG_FE4ISR_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_P2P_PWROFF_NOA2_ERLY_INT_8814B BIT(22) +#define BIT_P2P_PWROFF_NOA1_ERLY_INT_8814B BIT(21) +#define BIT_P2P_PWROFF_NOA0_ERLY_INT_8814B BIT(20) #define BIT_FS_CLI3_TXPKTIN_INT_8814B BIT(19) #define BIT_FS_CLI2_TXPKTIN_INT_8814B BIT(18) #define BIT_FS_CLI1_TXPKTIN_INT_8814B BIT(17) @@ -3239,8 +5798,7 @@ #define BIT_TXFTM_INT_EN_8814B BIT(26) #define BIT_FS_H2C_CMD_OK_INT_EN_8814B BIT(25) #define BIT_FS_H2C_CMD_FULL_INT_EN_8814B BIT(24) -#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8814B BIT(23) -#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8814B BIT(22) +#define BIT_FS_MACID_SEARCH_FAIL_INT_EN_8814B BIT(22) #define BIT_FS_MACID_PWRCHANGE3_INT_EN_8814B BIT(21) #define BIT_FS_MACID_PWRCHANGE2_INT_EN_8814B BIT(20) #define BIT_FS_MACID_PWRCHANGE1_INT_EN_8814B BIT(19) @@ -3272,8 +5830,7 @@ #define BIT_TXFTM_INT_8814B BIT(26) #define BIT_FS_H2C_CMD_OK_INT_8814B BIT(25) #define BIT_FS_H2C_CMD_FULL_INT_8814B BIT(24) -#define BIT_FS_MACID_PWRCHANGE5_INT_8814B BIT(23) -#define BIT_FS_MACID_PWRCHANGE4_INT_8814B BIT(22) +#define BIT_FS_MACID_SEARCH_FAIL_INT_8814B BIT(22) #define BIT_FS_MACID_PWRCHANGE3_INT_8814B BIT(21) #define BIT_FS_MACID_PWRCHANGE2_INT_8814B BIT(20) #define BIT_FS_MACID_PWRCHANGE1_INT_8814B BIT(19) @@ -3301,53 +5858,82 @@ #define BIT_SHIFT_MID_31TO0_8814B 0 #define BIT_MASK_MID_31TO0_8814B 0xffffffffL -#define BIT_MID_31TO0_8814B(x) (((x) & BIT_MASK_MID_31TO0_8814B) << BIT_SHIFT_MID_31TO0_8814B) -#define BIT_GET_MID_31TO0_8814B(x) (((x) >> BIT_SHIFT_MID_31TO0_8814B) & BIT_MASK_MID_31TO0_8814B) - - +#define BIT_MID_31TO0_8814B(x) \ + (((x) & BIT_MASK_MID_31TO0_8814B) << BIT_SHIFT_MID_31TO0_8814B) +#define BITS_MID_31TO0_8814B \ + (BIT_MASK_MID_31TO0_8814B << BIT_SHIFT_MID_31TO0_8814B) +#define BIT_CLEAR_MID_31TO0_8814B(x) ((x) & (~BITS_MID_31TO0_8814B)) +#define BIT_GET_MID_31TO0_8814B(x) \ + (((x) >> BIT_SHIFT_MID_31TO0_8814B) & BIT_MASK_MID_31TO0_8814B) +#define BIT_SET_MID_31TO0_8814B(x, v) \ + (BIT_CLEAR_MID_31TO0_8814B(x) | BIT_MID_31TO0_8814B(v)) /* 2 REG_SPWR1_8814B */ #define BIT_SHIFT_MID_63TO32_8814B 0 #define BIT_MASK_MID_63TO32_8814B 0xffffffffL -#define BIT_MID_63TO32_8814B(x) (((x) & BIT_MASK_MID_63TO32_8814B) << BIT_SHIFT_MID_63TO32_8814B) -#define BIT_GET_MID_63TO32_8814B(x) (((x) >> BIT_SHIFT_MID_63TO32_8814B) & BIT_MASK_MID_63TO32_8814B) - - +#define BIT_MID_63TO32_8814B(x) \ + (((x) & BIT_MASK_MID_63TO32_8814B) << BIT_SHIFT_MID_63TO32_8814B) +#define BITS_MID_63TO32_8814B \ + (BIT_MASK_MID_63TO32_8814B << BIT_SHIFT_MID_63TO32_8814B) +#define BIT_CLEAR_MID_63TO32_8814B(x) ((x) & (~BITS_MID_63TO32_8814B)) +#define BIT_GET_MID_63TO32_8814B(x) \ + (((x) >> BIT_SHIFT_MID_63TO32_8814B) & BIT_MASK_MID_63TO32_8814B) +#define BIT_SET_MID_63TO32_8814B(x, v) \ + (BIT_CLEAR_MID_63TO32_8814B(x) | BIT_MID_63TO32_8814B(v)) /* 2 REG_SPWR2_8814B */ #define BIT_SHIFT_MID_95O64_8814B 0 #define BIT_MASK_MID_95O64_8814B 0xffffffffL -#define BIT_MID_95O64_8814B(x) (((x) & BIT_MASK_MID_95O64_8814B) << BIT_SHIFT_MID_95O64_8814B) -#define BIT_GET_MID_95O64_8814B(x) (((x) >> BIT_SHIFT_MID_95O64_8814B) & BIT_MASK_MID_95O64_8814B) - - +#define BIT_MID_95O64_8814B(x) \ + (((x) & BIT_MASK_MID_95O64_8814B) << BIT_SHIFT_MID_95O64_8814B) +#define BITS_MID_95O64_8814B \ + (BIT_MASK_MID_95O64_8814B << BIT_SHIFT_MID_95O64_8814B) +#define BIT_CLEAR_MID_95O64_8814B(x) ((x) & (~BITS_MID_95O64_8814B)) +#define BIT_GET_MID_95O64_8814B(x) \ + (((x) >> BIT_SHIFT_MID_95O64_8814B) & BIT_MASK_MID_95O64_8814B) +#define BIT_SET_MID_95O64_8814B(x, v) \ + (BIT_CLEAR_MID_95O64_8814B(x) | BIT_MID_95O64_8814B(v)) /* 2 REG_SPWR3_8814B */ #define BIT_SHIFT_MID_127TO96_8814B 0 #define BIT_MASK_MID_127TO96_8814B 0xffffffffL -#define BIT_MID_127TO96_8814B(x) (((x) & BIT_MASK_MID_127TO96_8814B) << BIT_SHIFT_MID_127TO96_8814B) -#define BIT_GET_MID_127TO96_8814B(x) (((x) >> BIT_SHIFT_MID_127TO96_8814B) & BIT_MASK_MID_127TO96_8814B) - - +#define BIT_MID_127TO96_8814B(x) \ + (((x) & BIT_MASK_MID_127TO96_8814B) << BIT_SHIFT_MID_127TO96_8814B) +#define BITS_MID_127TO96_8814B \ + (BIT_MASK_MID_127TO96_8814B << BIT_SHIFT_MID_127TO96_8814B) +#define BIT_CLEAR_MID_127TO96_8814B(x) ((x) & (~BITS_MID_127TO96_8814B)) +#define BIT_GET_MID_127TO96_8814B(x) \ + (((x) >> BIT_SHIFT_MID_127TO96_8814B) & BIT_MASK_MID_127TO96_8814B) +#define BIT_SET_MID_127TO96_8814B(x, v) \ + (BIT_CLEAR_MID_127TO96_8814B(x) | BIT_MID_127TO96_8814B(v)) /* 2 REG_POWSEQ_8814B */ #define BIT_SHIFT_SEQNUM_MID_8814B 16 #define BIT_MASK_SEQNUM_MID_8814B 0xffff -#define BIT_SEQNUM_MID_8814B(x) (((x) & BIT_MASK_SEQNUM_MID_8814B) << BIT_SHIFT_SEQNUM_MID_8814B) -#define BIT_GET_SEQNUM_MID_8814B(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8814B) & BIT_MASK_SEQNUM_MID_8814B) - - +#define BIT_SEQNUM_MID_8814B(x) \ + (((x) & BIT_MASK_SEQNUM_MID_8814B) << BIT_SHIFT_SEQNUM_MID_8814B) +#define BITS_SEQNUM_MID_8814B \ + (BIT_MASK_SEQNUM_MID_8814B << BIT_SHIFT_SEQNUM_MID_8814B) +#define BIT_CLEAR_SEQNUM_MID_8814B(x) ((x) & (~BITS_SEQNUM_MID_8814B)) +#define BIT_GET_SEQNUM_MID_8814B(x) \ + (((x) >> BIT_SHIFT_SEQNUM_MID_8814B) & BIT_MASK_SEQNUM_MID_8814B) +#define BIT_SET_SEQNUM_MID_8814B(x, v) \ + (BIT_CLEAR_SEQNUM_MID_8814B(x) | BIT_SEQNUM_MID_8814B(v)) #define BIT_SHIFT_REF_MID_8814B 0 #define BIT_MASK_REF_MID_8814B 0x7f -#define BIT_REF_MID_8814B(x) (((x) & BIT_MASK_REF_MID_8814B) << BIT_SHIFT_REF_MID_8814B) -#define BIT_GET_REF_MID_8814B(x) (((x) >> BIT_SHIFT_REF_MID_8814B) & BIT_MASK_REF_MID_8814B) - - +#define BIT_REF_MID_8814B(x) \ + (((x) & BIT_MASK_REF_MID_8814B) << BIT_SHIFT_REF_MID_8814B) +#define BITS_REF_MID_8814B (BIT_MASK_REF_MID_8814B << BIT_SHIFT_REF_MID_8814B) +#define BIT_CLEAR_REF_MID_8814B(x) ((x) & (~BITS_REF_MID_8814B)) +#define BIT_GET_REF_MID_8814B(x) \ + (((x) >> BIT_SHIFT_REF_MID_8814B) & BIT_MASK_REF_MID_8814B) +#define BIT_SET_REF_MID_8814B(x, v) \ + (BIT_CLEAR_REF_MID_8814B(x) | BIT_REF_MID_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -3358,10 +5944,14 @@ #define BIT_SHIFT_TC7DATA_8814B 0 #define BIT_MASK_TC7DATA_8814B 0xffffff -#define BIT_TC7DATA_8814B(x) (((x) & BIT_MASK_TC7DATA_8814B) << BIT_SHIFT_TC7DATA_8814B) -#define BIT_GET_TC7DATA_8814B(x) (((x) >> BIT_SHIFT_TC7DATA_8814B) & BIT_MASK_TC7DATA_8814B) - - +#define BIT_TC7DATA_8814B(x) \ + (((x) & BIT_MASK_TC7DATA_8814B) << BIT_SHIFT_TC7DATA_8814B) +#define BITS_TC7DATA_8814B (BIT_MASK_TC7DATA_8814B << BIT_SHIFT_TC7DATA_8814B) +#define BIT_CLEAR_TC7DATA_8814B(x) ((x) & (~BITS_TC7DATA_8814B)) +#define BIT_GET_TC7DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC7DATA_8814B) & BIT_MASK_TC7DATA_8814B) +#define BIT_SET_TC7DATA_8814B(x, v) \ + (BIT_CLEAR_TC7DATA_8814B(x) | BIT_TC7DATA_8814B(v)) /* 2 REG_TC8_CTRL_V1_8814B */ #define BIT_TC8INT_EN_8814B BIT(26) @@ -3370,74 +5960,782 @@ #define BIT_SHIFT_TC8DATA_8814B 0 #define BIT_MASK_TC8DATA_8814B 0xffffff -#define BIT_TC8DATA_8814B(x) (((x) & BIT_MASK_TC8DATA_8814B) << BIT_SHIFT_TC8DATA_8814B) -#define BIT_GET_TC8DATA_8814B(x) (((x) >> BIT_SHIFT_TC8DATA_8814B) & BIT_MASK_TC8DATA_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_TC8DATA_8814B(x) \ + (((x) & BIT_MASK_TC8DATA_8814B) << BIT_SHIFT_TC8DATA_8814B) +#define BITS_TC8DATA_8814B (BIT_MASK_TC8DATA_8814B << BIT_SHIFT_TC8DATA_8814B) +#define BIT_CLEAR_TC8DATA_8814B(x) ((x) & (~BITS_TC8DATA_8814B)) +#define BIT_GET_TC8DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC8DATA_8814B) & BIT_MASK_TC8DATA_8814B) +#define BIT_SET_TC8DATA_8814B(x, v) \ + (BIT_CLEAR_TC8DATA_8814B(x) | BIT_TC8DATA_8814B(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL0_8814B */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B 24 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8814B \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8814B)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT2_8814B(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B 16 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8814B \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8814B)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT1_8814B(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B 8 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8814B \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8814B)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT0_8814B(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B 0xff +#define BIT_RX_BCN_TBTT_ITVL_PORT0_8814B(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B) +#define BITS_RX_BCN_TBTT_ITVL_PORT0_8814B \ + (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8814B(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8814B)) +#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8814B(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B) +#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8814B(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8814B(x) | \ + BIT_RX_BCN_TBTT_ITVL_PORT0_8814B(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL1_8814B */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8814B \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8814B)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT3_8814B(v)) + +/* 2 REG_FWIMR1_8814B */ +#define BIT_FS_ATIM_MB15_INT_EN_8814B BIT(31) +#define BIT_FS_ATIM_MB14_INT_EN_8814B BIT(30) +#define BIT_FS_ATIM_MB13_INT_EN_8814B BIT(29) +#define BIT_FS_ATIM_MB12_INT_EN_8814B BIT(28) +#define BIT_FS_ATIM_MB11_INT_EN_8814B BIT(27) +#define BIT_FS_ATIM_MB10_INT_EN_8814B BIT(26) +#define BIT_FS_ATIM_MB9_INT_EN_8814B BIT(25) +#define BIT_FS_ATIM_MB8_INT_EN_8814B BIT(24) +#define BIT_FS_TXBCNERR_MB15_INT_EN_8814B BIT(23) +#define BIT_FS_TXBCNERR_MB14_INT_EN_8814B BIT(22) +#define BIT_FS_TXBCNERR_MB13_INT_EN_8814B BIT(21) +#define BIT_FS_TXBCNERR_MB12_INT_EN_8814B BIT(20) +#define BIT_FS_TXBCNERR_MB11_INT_EN_8814B BIT(19) +#define BIT_FS_TXBCNERR_MB10_INT_EN_8814B BIT(18) +#define BIT_FS_TXBCNERR_MB9_INT_EN_8814B BIT(17) +#define BIT_FS_TXBCNERR_MB8_INT_EN_8814B BIT(16) +#define BIT_FS_TXBCNOK_MB15_INT_EN_8814B BIT(15) +#define BIT_FS_TXBCNOK_MB14_INT_EN_8814B BIT(14) +#define BIT_FS_TXBCNOK_MB13_INT_EN_8814B BIT(13) +#define BIT_FS_TXBCNOK_MB12_INT_EN_8814B BIT(12) +#define BIT_FS_TXBCNOK_MB11_INT_EN_8814B BIT(11) +#define BIT_FS_TXBCNOK_MB10_INT_EN_8814B BIT(10) +#define BIT_FS_TXBCNOK_MB9_INT_EN_8814B BIT(9) +#define BIT_FS_TXBCNOK_MB8_INT_EN_8814B BIT(8) +#define BIT_FS_BCNERLY0_MB15INT_EN_8814B BIT(7) +#define BIT_FS_BCNERLY0_MB14INT_EN_8814B BIT(6) +#define BIT_FS_BCNERLY0_MB13INT_EN_8814B BIT(5) +#define BIT_FS_BCNERLY0_MB12INT_EN_8814B BIT(4) +#define BIT_FS_BCNERLY0_MB11INT_EN_8814B BIT(3) +#define BIT_FS_BCNERLY0_MB10INT_EN_8814B BIT(2) +#define BIT_FS_BCNERLY0_MB9INT_EN_8814B BIT(1) +#define BIT_FS_BCNERLY0_MB8INT_EN_8814B BIT(0) + +/* 2 REG_FWISR1_8814B */ +#define BIT_FS_ATIM_MB15_INT_8814B BIT(31) +#define BIT_FS_ATIM_MB14_INT_8814B BIT(30) +#define BIT_FS_ATIM_MB13_INT_8814B BIT(29) +#define BIT_FS_ATIM_MB12_INT_8814B BIT(28) +#define BIT_FS_ATIM_MB11_INT_8814B BIT(27) +#define BIT_FS_ATIM_MB10_INT_8814B BIT(26) +#define BIT_FS_ATIM_MB9_INT_8814B BIT(25) +#define BIT_FS_ATIM_MB8_INT_8814B BIT(24) +#define BIT_FS_TXBCNERR_MB15_INT_8814B BIT(23) +#define BIT_FS_TXBCNERR_MB14_INT_8814B BIT(22) +#define BIT_FS_TXBCNERR_MB13_INT_8814B BIT(21) +#define BIT_FS_TXBCNERR_MB12_INT_8814B BIT(20) +#define BIT_FS_TXBCNERR_MB11_INT_8814B BIT(19) +#define BIT_FS_TXBCNERR_MB10_INT_8814B BIT(18) +#define BIT_FS_TXBCNERR_MB9_INT_8814B BIT(17) +#define BIT_FS_TXBCNERR_MB8_INT_8814B BIT(16) +#define BIT_FS_TXBCNOK_MB15_INT_8814B BIT(15) +#define BIT_FS_TXBCNOK_MB14_INT_8814B BIT(14) +#define BIT_FS_TXBCNOK_MB13_INT_8814B BIT(13) +#define BIT_FS_TXBCNOK_MB12_INT_8814B BIT(12) +#define BIT_FS_TXBCNOK_MB11_INT_8814B BIT(11) +#define BIT_FS_TXBCNOK_MB10_INT_8814B BIT(10) +#define BIT_FS_TXBCNOK_MB9_INT_8814B BIT(9) +#define BIT_FS_TXBCNOK_MB8_INT_8814B BIT(8) +#define BIT_FS_BCNERLY0_MB15INT_8814B BIT(7) +#define BIT_FS_BCNERLY0_MB14INT_8814B BIT(6) +#define BIT_FS_BCNERLY0_MB13INT_8814B BIT(5) +#define BIT_FS_BCNERLY0_MB12INT_8814B BIT(4) +#define BIT_FS_BCNERLY0_MB11INT_8814B BIT(3) +#define BIT_FS_BCNERLY0_MB10INT_8814B BIT(2) +#define BIT_FS_BCNERLY0_MB9INT_8814B BIT(1) +#define BIT_FS_BCNERLY0_MB8INT_8814B BIT(0) + +/* 2 REG_FWIMR2_8814B */ +#define BIT_FS_BCNDMA0_MB15_INT_EN_8814B BIT(15) +#define BIT_FS_BCNDMA0_MB14_INT_EN_8814B BIT(14) +#define BIT_FS_BCNDMA0_MB13_INT_EN_8814B BIT(13) +#define BIT_FS_BCNDMA0_MB12_INT_EN_8814B BIT(12) +#define BIT_FS_BCNDMA0_MB11_INT_EN_8814B BIT(11) +#define BIT_FS_BCNDMA0_MB10_INT_EN_8814B BIT(10) +#define BIT_FS_BCNDMA0_MB9_INT_EN_8814B BIT(9) +#define BIT_FS_BCNDMA0_MB8_INT_EN_8814B BIT(8) +#define BIT_FS_TBTT0_MB15INT_EN_8814B BIT(7) +#define BIT_FS_TBTT0_MB14INT_EN_8814B BIT(6) +#define BIT_FS_TBTT0_MB13INT_EN_8814B BIT(5) +#define BIT_FS_TBTT0_MB12INT_EN_8814B BIT(4) +#define BIT_FS_TBTT0_MB11INT_EN_8814B BIT(3) +#define BIT_FS_TBTT0_MB10INT_EN_8814B BIT(2) +#define BIT_FS_TBTT0_MB9INT_EN_8814B BIT(1) +#define BIT_FS_TBTT0_MB8INT_EN_8814B BIT(0) + +/* 2 REG_FWISR2_8814B */ +#define BIT_FS_BCNDMA0_MB15_INT_8814B BIT(15) +#define BIT_FS_BCNDMA0_MB14_INT_8814B BIT(14) +#define BIT_FS_BCNDMA0_MB13_INT_8814B BIT(13) +#define BIT_FS_BCNDMA0_MB12_INT_8814B BIT(12) +#define BIT_FS_BCNDMA0_MB11_INT_8814B BIT(11) +#define BIT_FS_BCNDMA0_MB10_INT_8814B BIT(10) +#define BIT_FS_BCNDMA0_MB9_INT_8814B BIT(9) +#define BIT_FS_BCNDMA0_MB8_INT_8814B BIT(8) +#define BIT_FS_TBTT0_MB15INT_8814B BIT(7) +#define BIT_FS_TBTT0_MB14INT_8814B BIT(6) +#define BIT_FS_TBTT0_MB13INT_8814B BIT(5) +#define BIT_FS_TBTT0_MB12INT_8814B BIT(4) +#define BIT_FS_TBTT0_MB11INT_8814B BIT(3) +#define BIT_FS_TBTT0_MB10INT_8814B BIT(2) +#define BIT_FS_TBTT0_MB9INT_8814B BIT(1) +#define BIT_FS_TBTT0_MB8INT_8814B BIT(0) + +/* 2 REG_FWIMR3_8814B */ /* 2 REG_NOT_VALID_8814B */ +#define BIT_FS_TXBCNOK_PORT4_INT_EN_8814B BIT(11) +#define BIT_FS_TXBCNOK_PORT3_INT_EN_8814B BIT(10) +#define BIT_FS_TXBCNOK_PORT2_INT_EN_8814B BIT(9) +#define BIT_FS_TXBCNOK_PORT1_INT_EN_8814B BIT(8) +#define BIT_FS_TXBCNERR_PORT4_INT_EN_8814B BIT(7) +#define BIT_FS_TXBCNERR_PORT3_INT_EN_8814B BIT(6) +#define BIT_FS_TXBCNERR_PORT2_INT_EN_8814B BIT(5) +#define BIT_FS_TXBCNERR_PORT1_INT_EN_8814B BIT(4) +#define BIT_FS_ATIM_PORT4_INT_EN_8814B BIT(3) +#define BIT_FS_ATIM_PORT3_INT_EN_8814B BIT(2) +#define BIT_FS_ATIM_PORT2_INT_EN_8814B BIT(1) +#define BIT_FS_ATIM_PORT1_INT_EN_8814B BIT(0) + +/* 2 REG_FWISR3_8814B */ +#define BIT_FS_TXBCNOK_PORT4_INT_8814B BIT(11) +#define BIT_FS_TXBCNOK_PORT3_INT_8814B BIT(10) +#define BIT_FS_TXBCNOK_PORT2_INT_8814B BIT(9) +#define BIT_FS_TXBCNOK_PORT1_INT_8814B BIT(8) +#define BIT_FS_TXBCNERR_PORT4_INT_8814B BIT(7) +#define BIT_FS_TXBCNERR_PORT3_INT_8814B BIT(6) +#define BIT_FS_TXBCNERR_PORT2_INT_8814B BIT(5) +#define BIT_FS_TXBCNERR_PORT1_INT_8814B BIT(4) +#define BIT_FS_ATIM_PORT4_INT_8814B BIT(3) +#define BIT_FS_ATIM_PORT3_INT_8814B BIT(2) +#define BIT_FS_ATIM_PORT2_INT_8814B BIT(1) +#define BIT_FS_ATIM_PORT1_INT_8814B BIT(0) + +/* 2 REG_SPEED_SENSOR_8814B */ +#define BIT_DSS_1_RST_N_8814B BIT(31) +#define BIT_DSS_1_SPEED_EN_8814B BIT(30) +#define BIT_DSS_1_WIRE_SEL_8814B BIT(29) +#define BIT_DSS_ENCLK_8814B BIT(28) + +#define BIT_SHIFT_DSS_1_RO_SEL_8814B 24 +#define BIT_MASK_DSS_1_RO_SEL_8814B 0x7 +#define BIT_DSS_1_RO_SEL_8814B(x) \ + (((x) & BIT_MASK_DSS_1_RO_SEL_8814B) << BIT_SHIFT_DSS_1_RO_SEL_8814B) +#define BITS_DSS_1_RO_SEL_8814B \ + (BIT_MASK_DSS_1_RO_SEL_8814B << BIT_SHIFT_DSS_1_RO_SEL_8814B) +#define BIT_CLEAR_DSS_1_RO_SEL_8814B(x) ((x) & (~BITS_DSS_1_RO_SEL_8814B)) +#define BIT_GET_DSS_1_RO_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_1_RO_SEL_8814B) & BIT_MASK_DSS_1_RO_SEL_8814B) +#define BIT_SET_DSS_1_RO_SEL_8814B(x, v) \ + (BIT_CLEAR_DSS_1_RO_SEL_8814B(x) | BIT_DSS_1_RO_SEL_8814B(v)) + +#define BIT_SHIFT_DSS_1_DATA_IN_8814B 0 +#define BIT_MASK_DSS_1_DATA_IN_8814B 0xfffff +#define BIT_DSS_1_DATA_IN_8814B(x) \ + (((x) & BIT_MASK_DSS_1_DATA_IN_8814B) << BIT_SHIFT_DSS_1_DATA_IN_8814B) +#define BITS_DSS_1_DATA_IN_8814B \ + (BIT_MASK_DSS_1_DATA_IN_8814B << BIT_SHIFT_DSS_1_DATA_IN_8814B) +#define BIT_CLEAR_DSS_1_DATA_IN_8814B(x) ((x) & (~BITS_DSS_1_DATA_IN_8814B)) +#define BIT_GET_DSS_1_DATA_IN_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_1_DATA_IN_8814B) & BIT_MASK_DSS_1_DATA_IN_8814B) +#define BIT_SET_DSS_1_DATA_IN_8814B(x, v) \ + (BIT_CLEAR_DSS_1_DATA_IN_8814B(x) | BIT_DSS_1_DATA_IN_8814B(v)) + +/* 2 REG_SPEED_SENSOR1_8814B */ +#define BIT_DSS_1_READY_8814B BIT(31) +#define BIT_DSS_1_WSORT_GO_8814B BIT(30) + +#define BIT_SHIFT_DSS_1_COUNT_OUT_8814B 0 +#define BIT_MASK_DSS_1_COUNT_OUT_8814B 0xfffff +#define BIT_DSS_1_COUNT_OUT_8814B(x) \ + (((x) & BIT_MASK_DSS_1_COUNT_OUT_8814B) \ + << BIT_SHIFT_DSS_1_COUNT_OUT_8814B) +#define BITS_DSS_1_COUNT_OUT_8814B \ + (BIT_MASK_DSS_1_COUNT_OUT_8814B << BIT_SHIFT_DSS_1_COUNT_OUT_8814B) +#define BIT_CLEAR_DSS_1_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8814B)) +#define BIT_GET_DSS_1_COUNT_OUT_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8814B) & \ + BIT_MASK_DSS_1_COUNT_OUT_8814B) +#define BIT_SET_DSS_1_COUNT_OUT_8814B(x, v) \ + (BIT_CLEAR_DSS_1_COUNT_OUT_8814B(x) | BIT_DSS_1_COUNT_OUT_8814B(v)) + +/* 2 REG_SPEED_SENSOR2_8814B */ +#define BIT_DSS_2_RST_N_8814B BIT(31) +#define BIT_DSS_2_SPEED_EN_8814B BIT(30) +#define BIT_DSS_2_WIRE_SEL_8814B BIT(29) +#define BIT_DSS_ENCLK_8814B BIT(28) + +#define BIT_SHIFT_DSS_2_RO_SEL_8814B 24 +#define BIT_MASK_DSS_2_RO_SEL_8814B 0x7 +#define BIT_DSS_2_RO_SEL_8814B(x) \ + (((x) & BIT_MASK_DSS_2_RO_SEL_8814B) << BIT_SHIFT_DSS_2_RO_SEL_8814B) +#define BITS_DSS_2_RO_SEL_8814B \ + (BIT_MASK_DSS_2_RO_SEL_8814B << BIT_SHIFT_DSS_2_RO_SEL_8814B) +#define BIT_CLEAR_DSS_2_RO_SEL_8814B(x) ((x) & (~BITS_DSS_2_RO_SEL_8814B)) +#define BIT_GET_DSS_2_RO_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_2_RO_SEL_8814B) & BIT_MASK_DSS_2_RO_SEL_8814B) +#define BIT_SET_DSS_2_RO_SEL_8814B(x, v) \ + (BIT_CLEAR_DSS_2_RO_SEL_8814B(x) | BIT_DSS_2_RO_SEL_8814B(v)) + +#define BIT_SHIFT_DSS_2_DATA_IN_8814B 0 +#define BIT_MASK_DSS_2_DATA_IN_8814B 0xfffff +#define BIT_DSS_2_DATA_IN_8814B(x) \ + (((x) & BIT_MASK_DSS_2_DATA_IN_8814B) << BIT_SHIFT_DSS_2_DATA_IN_8814B) +#define BITS_DSS_2_DATA_IN_8814B \ + (BIT_MASK_DSS_2_DATA_IN_8814B << BIT_SHIFT_DSS_2_DATA_IN_8814B) +#define BIT_CLEAR_DSS_2_DATA_IN_8814B(x) ((x) & (~BITS_DSS_2_DATA_IN_8814B)) +#define BIT_GET_DSS_2_DATA_IN_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_2_DATA_IN_8814B) & BIT_MASK_DSS_2_DATA_IN_8814B) +#define BIT_SET_DSS_2_DATA_IN_8814B(x, v) \ + (BIT_CLEAR_DSS_2_DATA_IN_8814B(x) | BIT_DSS_2_DATA_IN_8814B(v)) + +/* 2 REG_SPEED_SENSOR3_8814B */ +#define BIT_DSS_2_READY_8814B BIT(31) +#define BIT_DSS_2_WSORT_GO_8814B BIT(30) + +#define BIT_SHIFT_DSS_2_COUNT_OUT_8814B 0 +#define BIT_MASK_DSS_2_COUNT_OUT_8814B 0xfffff +#define BIT_DSS_2_COUNT_OUT_8814B(x) \ + (((x) & BIT_MASK_DSS_2_COUNT_OUT_8814B) \ + << BIT_SHIFT_DSS_2_COUNT_OUT_8814B) +#define BITS_DSS_2_COUNT_OUT_8814B \ + (BIT_MASK_DSS_2_COUNT_OUT_8814B << BIT_SHIFT_DSS_2_COUNT_OUT_8814B) +#define BIT_CLEAR_DSS_2_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8814B)) +#define BIT_GET_DSS_2_COUNT_OUT_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8814B) & \ + BIT_MASK_DSS_2_COUNT_OUT_8814B) +#define BIT_SET_DSS_2_COUNT_OUT_8814B(x, v) \ + (BIT_CLEAR_DSS_2_COUNT_OUT_8814B(x) | BIT_DSS_2_COUNT_OUT_8814B(v)) + +/* 2 REG_SPEED_SENSOR4_8814B */ +#define BIT_DSS_3_RST_N_8814B BIT(31) +#define BIT_DSS_3_SPEED_EN_8814B BIT(30) +#define BIT_DSS_3_WIRE_SEL_8814B BIT(29) +#define BIT_DSS_ENCLK_8814B BIT(28) + +#define BIT_SHIFT_DSS_3_RO_SEL_8814B 24 +#define BIT_MASK_DSS_3_RO_SEL_8814B 0x7 +#define BIT_DSS_3_RO_SEL_8814B(x) \ + (((x) & BIT_MASK_DSS_3_RO_SEL_8814B) << BIT_SHIFT_DSS_3_RO_SEL_8814B) +#define BITS_DSS_3_RO_SEL_8814B \ + (BIT_MASK_DSS_3_RO_SEL_8814B << BIT_SHIFT_DSS_3_RO_SEL_8814B) +#define BIT_CLEAR_DSS_3_RO_SEL_8814B(x) ((x) & (~BITS_DSS_3_RO_SEL_8814B)) +#define BIT_GET_DSS_3_RO_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_3_RO_SEL_8814B) & BIT_MASK_DSS_3_RO_SEL_8814B) +#define BIT_SET_DSS_3_RO_SEL_8814B(x, v) \ + (BIT_CLEAR_DSS_3_RO_SEL_8814B(x) | BIT_DSS_3_RO_SEL_8814B(v)) + +#define BIT_SHIFT_DSS_3_DATA_IN_8814B 0 +#define BIT_MASK_DSS_3_DATA_IN_8814B 0xfffff +#define BIT_DSS_3_DATA_IN_8814B(x) \ + (((x) & BIT_MASK_DSS_3_DATA_IN_8814B) << BIT_SHIFT_DSS_3_DATA_IN_8814B) +#define BITS_DSS_3_DATA_IN_8814B \ + (BIT_MASK_DSS_3_DATA_IN_8814B << BIT_SHIFT_DSS_3_DATA_IN_8814B) +#define BIT_CLEAR_DSS_3_DATA_IN_8814B(x) ((x) & (~BITS_DSS_3_DATA_IN_8814B)) +#define BIT_GET_DSS_3_DATA_IN_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_3_DATA_IN_8814B) & BIT_MASK_DSS_3_DATA_IN_8814B) +#define BIT_SET_DSS_3_DATA_IN_8814B(x, v) \ + (BIT_CLEAR_DSS_3_DATA_IN_8814B(x) | BIT_DSS_3_DATA_IN_8814B(v)) + +/* 2 REG_SPEED_SENSOR5_8814B */ +#define BIT_DSS_3_READY_8814B BIT(31) +#define BIT_DSS_3_WSORT_GO_8814B BIT(30) + +#define BIT_SHIFT_DSS_3_COUNT_OUT_8814B 0 +#define BIT_MASK_DSS_3_COUNT_OUT_8814B 0xfffff +#define BIT_DSS_3_COUNT_OUT_8814B(x) \ + (((x) & BIT_MASK_DSS_3_COUNT_OUT_8814B) \ + << BIT_SHIFT_DSS_3_COUNT_OUT_8814B) +#define BITS_DSS_3_COUNT_OUT_8814B \ + (BIT_MASK_DSS_3_COUNT_OUT_8814B << BIT_SHIFT_DSS_3_COUNT_OUT_8814B) +#define BIT_CLEAR_DSS_3_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8814B)) +#define BIT_GET_DSS_3_COUNT_OUT_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8814B) & \ + BIT_MASK_DSS_3_COUNT_OUT_8814B) +#define BIT_SET_DSS_3_COUNT_OUT_8814B(x, v) \ + (BIT_CLEAR_DSS_3_COUNT_OUT_8814B(x) | BIT_DSS_3_COUNT_OUT_8814B(v)) + +/* 2 REG_RXPKTBUF_1_MAX_ADDR_8814B */ + +#define BIT_SHIFT_RXPKTBUF_SIZE_8814B 30 +#define BIT_MASK_RXPKTBUF_SIZE_8814B 0x3 +#define BIT_RXPKTBUF_SIZE_8814B(x) \ + (((x) & BIT_MASK_RXPKTBUF_SIZE_8814B) << BIT_SHIFT_RXPKTBUF_SIZE_8814B) +#define BITS_RXPKTBUF_SIZE_8814B \ + (BIT_MASK_RXPKTBUF_SIZE_8814B << BIT_SHIFT_RXPKTBUF_SIZE_8814B) +#define BIT_CLEAR_RXPKTBUF_SIZE_8814B(x) ((x) & (~BITS_RXPKTBUF_SIZE_8814B)) +#define BIT_GET_RXPKTBUF_SIZE_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_SIZE_8814B) & BIT_MASK_RXPKTBUF_SIZE_8814B) +#define BIT_SET_RXPKTBUF_SIZE_8814B(x, v) \ + (BIT_CLEAR_RXPKTBUF_SIZE_8814B(x) | BIT_RXPKTBUF_SIZE_8814B(v)) + +#define BIT_RXPKTBUF_DBG_SEL_8814B BIT(29) + +#define BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B 0 +#define BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B 0x3ffff +#define BIT_RXPKTBUF_1_MAX_ADDR_8814B(x) \ + (((x) & BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B) \ + << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B) +#define BITS_RXPKTBUF_1_MAX_ADDR_8814B \ + (BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B \ + << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B) +#define BIT_CLEAR_RXPKTBUF_1_MAX_ADDR_8814B(x) \ + ((x) & (~BITS_RXPKTBUF_1_MAX_ADDR_8814B)) +#define BIT_GET_RXPKTBUF_1_MAX_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B) & \ + BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B) +#define BIT_SET_RXPKTBUF_1_MAX_ADDR_8814B(x, v) \ + (BIT_CLEAR_RXPKTBUF_1_MAX_ADDR_8814B(x) | \ + BIT_RXPKTBUF_1_MAX_ADDR_8814B(v)) + +/* 2 REG_RXFWBUF_1_MAX_ADDR_8814B */ + +#define BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B 0 +#define BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B 0xffff +#define BIT_RXFWBUF_1_MAX_ADDR_8814B(x) \ + (((x) & BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B) \ + << BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B) +#define BITS_RXFWBUF_1_MAX_ADDR_8814B \ + (BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B \ + << BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B) +#define BIT_CLEAR_RXFWBUF_1_MAX_ADDR_8814B(x) \ + ((x) & (~BITS_RXFWBUF_1_MAX_ADDR_8814B)) +#define BIT_GET_RXFWBUF_1_MAX_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B) & \ + BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B) +#define BIT_SET_RXFWBUF_1_MAX_ADDR_8814B(x, v) \ + (BIT_CLEAR_RXFWBUF_1_MAX_ADDR_8814B(x) | \ + BIT_RXFWBUF_1_MAX_ADDR_8814B(v)) + +/* 2 REG_IO_WRAP_ERR_FLAG_V1_8814B */ +#define BIT_IO_WRAP_ERR_8814B BIT(0) + +/* 2 REG_RXPKTBUF_1_READ_8814B */ + +#define BIT_SHIFT_RXPKTBUF_1_READ_8814B 0 +#define BIT_MASK_RXPKTBUF_1_READ_8814B 0x3ffff +#define BIT_RXPKTBUF_1_READ_8814B(x) \ + (((x) & BIT_MASK_RXPKTBUF_1_READ_8814B) \ + << BIT_SHIFT_RXPKTBUF_1_READ_8814B) +#define BITS_RXPKTBUF_1_READ_8814B \ + (BIT_MASK_RXPKTBUF_1_READ_8814B << BIT_SHIFT_RXPKTBUF_1_READ_8814B) +#define BIT_CLEAR_RXPKTBUF_1_READ_8814B(x) ((x) & (~BITS_RXPKTBUF_1_READ_8814B)) +#define BIT_GET_RXPKTBUF_1_READ_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_1_READ_8814B) & \ + BIT_MASK_RXPKTBUF_1_READ_8814B) +#define BIT_SET_RXPKTBUF_1_READ_8814B(x, v) \ + (BIT_CLEAR_RXPKTBUF_1_READ_8814B(x) | BIT_RXPKTBUF_1_READ_8814B(v)) + +/* 2 REG_RXPKTBUF_1_WRITE_8814B */ + +#define BIT_SHIFT_RXPKTBUF_1_WRITE_8814B 0 +#define BIT_MASK_RXPKTBUF_1_WRITE_8814B 0x3ffff +#define BIT_RXPKTBUF_1_WRITE_8814B(x) \ + (((x) & BIT_MASK_RXPKTBUF_1_WRITE_8814B) \ + << BIT_SHIFT_RXPKTBUF_1_WRITE_8814B) +#define BITS_RXPKTBUF_1_WRITE_8814B \ + (BIT_MASK_RXPKTBUF_1_WRITE_8814B << BIT_SHIFT_RXPKTBUF_1_WRITE_8814B) +#define BIT_CLEAR_RXPKTBUF_1_WRITE_8814B(x) \ + ((x) & (~BITS_RXPKTBUF_1_WRITE_8814B)) +#define BIT_GET_RXPKTBUF_1_WRITE_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_1_WRITE_8814B) & \ + BIT_MASK_RXPKTBUF_1_WRITE_8814B) +#define BIT_SET_RXPKTBUF_1_WRITE_8814B(x, v) \ + (BIT_CLEAR_RXPKTBUF_1_WRITE_8814B(x) | BIT_RXPKTBUF_1_WRITE_8814B(v)) + +/* 2 REG_BUFF_DBGUG_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_R_OQT_DBG_SEL_8814B 16 +#define BIT_MASK_R_OQT_DBG_SEL_8814B 0xff +#define BIT_R_OQT_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_R_OQT_DBG_SEL_8814B) << BIT_SHIFT_R_OQT_DBG_SEL_8814B) +#define BITS_R_OQT_DBG_SEL_8814B \ + (BIT_MASK_R_OQT_DBG_SEL_8814B << BIT_SHIFT_R_OQT_DBG_SEL_8814B) +#define BIT_CLEAR_R_OQT_DBG_SEL_8814B(x) ((x) & (~BITS_R_OQT_DBG_SEL_8814B)) +#define BIT_GET_R_OQT_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_OQT_DBG_SEL_8814B) & BIT_MASK_R_OQT_DBG_SEL_8814B) +#define BIT_SET_R_OQT_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_R_OQT_DBG_SEL_8814B(x) | BIT_R_OQT_DBG_SEL_8814B(v)) + +#define BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B 8 +#define BIT_MASK_R_TXPKTBF_DBG_SEL_8814B 0x7 +#define BIT_R_TXPKTBF_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_R_TXPKTBF_DBG_SEL_8814B) \ + << BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B) +#define BITS_R_TXPKTBF_DBG_SEL_8814B \ + (BIT_MASK_R_TXPKTBF_DBG_SEL_8814B << BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B) +#define BIT_CLEAR_R_TXPKTBF_DBG_SEL_8814B(x) \ + ((x) & (~BITS_R_TXPKTBF_DBG_SEL_8814B)) +#define BIT_GET_R_TXPKTBF_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B) & \ + BIT_MASK_R_TXPKTBF_DBG_SEL_8814B) +#define BIT_SET_R_TXPKTBF_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_R_TXPKTBF_DBG_SEL_8814B(x) | BIT_R_TXPKTBF_DBG_SEL_8814B(v)) + +#define BIT_SHIFT_R_RXPKT_DBG_SEL_8814B 6 +#define BIT_MASK_R_RXPKT_DBG_SEL_8814B 0x3 +#define BIT_R_RXPKT_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_R_RXPKT_DBG_SEL_8814B) \ + << BIT_SHIFT_R_RXPKT_DBG_SEL_8814B) +#define BITS_R_RXPKT_DBG_SEL_8814B \ + (BIT_MASK_R_RXPKT_DBG_SEL_8814B << BIT_SHIFT_R_RXPKT_DBG_SEL_8814B) +#define BIT_CLEAR_R_RXPKT_DBG_SEL_8814B(x) ((x) & (~BITS_R_RXPKT_DBG_SEL_8814B)) +#define BIT_GET_R_RXPKT_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_RXPKT_DBG_SEL_8814B) & \ + BIT_MASK_R_RXPKT_DBG_SEL_8814B) +#define BIT_SET_R_RXPKT_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_R_RXPKT_DBG_SEL_8814B(x) | BIT_R_RXPKT_DBG_SEL_8814B(v)) + +#define BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B 0 +#define BIT_MASK_R_RXPKTBF_DBG_SEL_8814B 0x3 +#define BIT_R_RXPKTBF_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_R_RXPKTBF_DBG_SEL_8814B) \ + << BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B) +#define BITS_R_RXPKTBF_DBG_SEL_8814B \ + (BIT_MASK_R_RXPKTBF_DBG_SEL_8814B << BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B) +#define BIT_CLEAR_R_RXPKTBF_DBG_SEL_8814B(x) \ + ((x) & (~BITS_R_RXPKTBF_DBG_SEL_8814B)) +#define BIT_GET_R_RXPKTBF_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B) & \ + BIT_MASK_R_RXPKTBF_DBG_SEL_8814B) +#define BIT_SET_R_RXPKTBF_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_R_RXPKTBF_DBG_SEL_8814B(x) | BIT_R_RXPKTBF_DBG_SEL_8814B(v)) + +/* 2 REG_RFE_CTRL_PAD_E2_8814B */ +#define BIT_RFE_CTRL_ANTSW_E2_8814B BIT(16) +#define BIT_RFE_CTRL_PIN15_E2_8814B BIT(15) +#define BIT_RFE_CTRL_PIN14_E2_8814B BIT(14) +#define BIT_RFE_CTRL_PIN13_E2_8814B BIT(13) +#define BIT_RFE_CTRL_PIN12_E2_8814B BIT(12) +#define BIT_RFE_CTRL_PIN11_E2_8814B BIT(11) +#define BIT_RFE_CTRL_PIN10_E2_8814B BIT(10) +#define BIT_RFE_CTRL_PIN9_E2_8814B BIT(9) +#define BIT_RFE_CTRL_PIN8_E2_8814B BIT(8) +#define BIT_RFE_CTRL_PIN7_E2_8814B BIT(7) +#define BIT_RFE_CTRL_PIN6_E2_8814B BIT(6) +#define BIT_RFE_CTRL_PIN5_E2_8814B BIT(5) +#define BIT_RFE_CTRL_PIN4_E2_8814B BIT(4) +#define BIT_RFE_CTRL_PIN3_E2_8814B BIT(3) +#define BIT_RFE_CTRL_PIN2_E2_8814B BIT(2) +#define BIT_RFE_CTRL_PIN1_E2_8814B BIT(1) +#define BIT_RFE_CTRL_PIN0_E2_8814B BIT(0) + +/* 2 REG_RFE_CTRL_PAD_SR_8814B */ +#define BIT_RFE_CTRL_ANTSW_SR_8814B BIT(16) +#define BIT_RFE_CTRL_PIN15_SR_8814B BIT(15) +#define BIT_RFE_CTRL_PIN14_SR_8814B BIT(14) +#define BIT_RFE_CTRL_PIN13_SR_8814B BIT(13) +#define BIT_RFE_CTRL_PIN12_SR_8814B BIT(12) +#define BIT_RFE_CTRL_PIN11_SR_8814B BIT(11) +#define BIT_RFE_CTRL_PIN10_SR_8814B BIT(10) +#define BIT_RFE_CTRL_PIN9_SR_8814B BIT(9) +#define BIT_RFE_CTRL_PIN8_SR_8814B BIT(8) +#define BIT_RFE_CTRL_PIN7_SR_8814B BIT(7) +#define BIT_RFE_CTRL_PIN6_SR_8814B BIT(6) +#define BIT_RFE_CTRL_PIN5_SR_8814B BIT(5) +#define BIT_RFE_CTRL_PIN4_SR_8814B BIT(4) +#define BIT_RFE_CTRL_PIN3_SR_8814B BIT(3) +#define BIT_RFE_CTRL_PIN2_SR_8814B BIT(2) +#define BIT_RFE_CTRL_PIN1_SR_8814B BIT(1) +#define BIT_RFE_CTRL_PIN0_SR_8814B BIT(0) /* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_H2C_PRIORITY_SEL_8814B */ + +#define BIT_SHIFT_H2C_PRIORITY_SEL_8814B 0 +#define BIT_MASK_H2C_PRIORITY_SEL_8814B 0x3 +#define BIT_H2C_PRIORITY_SEL_8814B(x) \ + (((x) & BIT_MASK_H2C_PRIORITY_SEL_8814B) \ + << BIT_SHIFT_H2C_PRIORITY_SEL_8814B) +#define BITS_H2C_PRIORITY_SEL_8814B \ + (BIT_MASK_H2C_PRIORITY_SEL_8814B << BIT_SHIFT_H2C_PRIORITY_SEL_8814B) +#define BIT_CLEAR_H2C_PRIORITY_SEL_8814B(x) \ + ((x) & (~BITS_H2C_PRIORITY_SEL_8814B)) +#define BIT_GET_H2C_PRIORITY_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_PRIORITY_SEL_8814B) & \ + BIT_MASK_H2C_PRIORITY_SEL_8814B) +#define BIT_SET_H2C_PRIORITY_SEL_8814B(x, v) \ + (BIT_CLEAR_H2C_PRIORITY_SEL_8814B(x) | BIT_H2C_PRIORITY_SEL_8814B(v)) + +/* 2 REG_COUNTER_CTRL_8814B */ + +#define BIT_SHIFT_COUNTER_BASE_8814B 16 +#define BIT_MASK_COUNTER_BASE_8814B 0x1fff +#define BIT_COUNTER_BASE_8814B(x) \ + (((x) & BIT_MASK_COUNTER_BASE_8814B) << BIT_SHIFT_COUNTER_BASE_8814B) +#define BITS_COUNTER_BASE_8814B \ + (BIT_MASK_COUNTER_BASE_8814B << BIT_SHIFT_COUNTER_BASE_8814B) +#define BIT_CLEAR_COUNTER_BASE_8814B(x) ((x) & (~BITS_COUNTER_BASE_8814B)) +#define BIT_GET_COUNTER_BASE_8814B(x) \ + (((x) >> BIT_SHIFT_COUNTER_BASE_8814B) & BIT_MASK_COUNTER_BASE_8814B) +#define BIT_SET_COUNTER_BASE_8814B(x, v) \ + (BIT_CLEAR_COUNTER_BASE_8814B(x) | BIT_COUNTER_BASE_8814B(v)) + +#define BIT_EN_RTS_REQ_8814B BIT(9) +#define BIT_EN_EDCA_REQ_8814B BIT(8) +#define BIT_EN_PTCL_REQ_8814B BIT(7) +#define BIT_EN_SCH_REQ_8814B BIT(6) +#define BIT_USB_COUNT_EN_8814B BIT(5) +#define BIT_PCIE_COUNT_EN_8814B BIT(4) +#define BIT_RQPN_COUNT_EN_8814B BIT(3) +#define BIT_RDE_COUNT_EN_8814B BIT(2) +#define BIT_TDE_COUNT_EN_8814B BIT(1) +#define BIT_DISABLE_COUNTER_8814B BIT(0) + +/* 2 REG_COUNTER_THRESHOLD_8814B */ +#define BIT_SEL_ALL_MACID_8814B BIT(31) + +#define BIT_SHIFT_COUNTER_MACID_8814B 24 +#define BIT_MASK_COUNTER_MACID_8814B 0x7f +#define BIT_COUNTER_MACID_8814B(x) \ + (((x) & BIT_MASK_COUNTER_MACID_8814B) << BIT_SHIFT_COUNTER_MACID_8814B) +#define BITS_COUNTER_MACID_8814B \ + (BIT_MASK_COUNTER_MACID_8814B << BIT_SHIFT_COUNTER_MACID_8814B) +#define BIT_CLEAR_COUNTER_MACID_8814B(x) ((x) & (~BITS_COUNTER_MACID_8814B)) +#define BIT_GET_COUNTER_MACID_8814B(x) \ + (((x) >> BIT_SHIFT_COUNTER_MACID_8814B) & BIT_MASK_COUNTER_MACID_8814B) +#define BIT_SET_COUNTER_MACID_8814B(x, v) \ + (BIT_CLEAR_COUNTER_MACID_8814B(x) | BIT_COUNTER_MACID_8814B(v)) + +#define BIT_SHIFT_AGG_VALUE2_8814B 16 +#define BIT_MASK_AGG_VALUE2_8814B 0x7f +#define BIT_AGG_VALUE2_8814B(x) \ + (((x) & BIT_MASK_AGG_VALUE2_8814B) << BIT_SHIFT_AGG_VALUE2_8814B) +#define BITS_AGG_VALUE2_8814B \ + (BIT_MASK_AGG_VALUE2_8814B << BIT_SHIFT_AGG_VALUE2_8814B) +#define BIT_CLEAR_AGG_VALUE2_8814B(x) ((x) & (~BITS_AGG_VALUE2_8814B)) +#define BIT_GET_AGG_VALUE2_8814B(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE2_8814B) & BIT_MASK_AGG_VALUE2_8814B) +#define BIT_SET_AGG_VALUE2_8814B(x, v) \ + (BIT_CLEAR_AGG_VALUE2_8814B(x) | BIT_AGG_VALUE2_8814B(v)) + +#define BIT_SHIFT_AGG_VALUE1_8814B 8 +#define BIT_MASK_AGG_VALUE1_8814B 0x7f +#define BIT_AGG_VALUE1_8814B(x) \ + (((x) & BIT_MASK_AGG_VALUE1_8814B) << BIT_SHIFT_AGG_VALUE1_8814B) +#define BITS_AGG_VALUE1_8814B \ + (BIT_MASK_AGG_VALUE1_8814B << BIT_SHIFT_AGG_VALUE1_8814B) +#define BIT_CLEAR_AGG_VALUE1_8814B(x) ((x) & (~BITS_AGG_VALUE1_8814B)) +#define BIT_GET_AGG_VALUE1_8814B(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE1_8814B) & BIT_MASK_AGG_VALUE1_8814B) +#define BIT_SET_AGG_VALUE1_8814B(x, v) \ + (BIT_CLEAR_AGG_VALUE1_8814B(x) | BIT_AGG_VALUE1_8814B(v)) + +#define BIT_SHIFT_AGG_VALUE0_8814B 0 +#define BIT_MASK_AGG_VALUE0_8814B 0x7f +#define BIT_AGG_VALUE0_8814B(x) \ + (((x) & BIT_MASK_AGG_VALUE0_8814B) << BIT_SHIFT_AGG_VALUE0_8814B) +#define BITS_AGG_VALUE0_8814B \ + (BIT_MASK_AGG_VALUE0_8814B << BIT_SHIFT_AGG_VALUE0_8814B) +#define BIT_CLEAR_AGG_VALUE0_8814B(x) ((x) & (~BITS_AGG_VALUE0_8814B)) +#define BIT_GET_AGG_VALUE0_8814B(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE0_8814B) & BIT_MASK_AGG_VALUE0_8814B) +#define BIT_SET_AGG_VALUE0_8814B(x, v) \ + (BIT_CLEAR_AGG_VALUE0_8814B(x) | BIT_AGG_VALUE0_8814B(v)) + +/* 2 REG_COUNTER_SET_8814B */ + +#define BIT_SHIFT_REQUEST_RESET_8814B 16 +#define BIT_MASK_REQUEST_RESET_8814B 0xffff +#define BIT_REQUEST_RESET_8814B(x) \ + (((x) & BIT_MASK_REQUEST_RESET_8814B) << BIT_SHIFT_REQUEST_RESET_8814B) +#define BITS_REQUEST_RESET_8814B \ + (BIT_MASK_REQUEST_RESET_8814B << BIT_SHIFT_REQUEST_RESET_8814B) +#define BIT_CLEAR_REQUEST_RESET_8814B(x) ((x) & (~BITS_REQUEST_RESET_8814B)) +#define BIT_GET_REQUEST_RESET_8814B(x) \ + (((x) >> BIT_SHIFT_REQUEST_RESET_8814B) & BIT_MASK_REQUEST_RESET_8814B) +#define BIT_SET_REQUEST_RESET_8814B(x, v) \ + (BIT_CLEAR_REQUEST_RESET_8814B(x) | BIT_REQUEST_RESET_8814B(v)) + +#define BIT_SHIFT_REQUEST_START_8814B 0 +#define BIT_MASK_REQUEST_START_8814B 0xffff +#define BIT_REQUEST_START_8814B(x) \ + (((x) & BIT_MASK_REQUEST_START_8814B) << BIT_SHIFT_REQUEST_START_8814B) +#define BITS_REQUEST_START_8814B \ + (BIT_MASK_REQUEST_START_8814B << BIT_SHIFT_REQUEST_START_8814B) +#define BIT_CLEAR_REQUEST_START_8814B(x) ((x) & (~BITS_REQUEST_START_8814B)) +#define BIT_GET_REQUEST_START_8814B(x) \ + (((x) >> BIT_SHIFT_REQUEST_START_8814B) & BIT_MASK_REQUEST_START_8814B) +#define BIT_SET_REQUEST_START_8814B(x, v) \ + (BIT_CLEAR_REQUEST_START_8814B(x) | BIT_REQUEST_START_8814B(v)) + +/* 2 REG_COUNTER_OVERFLOW_8814B */ + +#define BIT_SHIFT_CNT_OVF_REG_8814B 0 +#define BIT_MASK_CNT_OVF_REG_8814B 0xffff +#define BIT_CNT_OVF_REG_8814B(x) \ + (((x) & BIT_MASK_CNT_OVF_REG_8814B) << BIT_SHIFT_CNT_OVF_REG_8814B) +#define BITS_CNT_OVF_REG_8814B \ + (BIT_MASK_CNT_OVF_REG_8814B << BIT_SHIFT_CNT_OVF_REG_8814B) +#define BIT_CLEAR_CNT_OVF_REG_8814B(x) ((x) & (~BITS_CNT_OVF_REG_8814B)) +#define BIT_GET_CNT_OVF_REG_8814B(x) \ + (((x) >> BIT_SHIFT_CNT_OVF_REG_8814B) & BIT_MASK_CNT_OVF_REG_8814B) +#define BIT_SET_CNT_OVF_REG_8814B(x, v) \ + (BIT_CLEAR_CNT_OVF_REG_8814B(x) | BIT_CNT_OVF_REG_8814B(v)) + +/* 2 REG_TXDMA_LEN_THRESHOLD_8814B */ + +#define BIT_SHIFT_TDE_LEN_TH1_8814B 16 +#define BIT_MASK_TDE_LEN_TH1_8814B 0xffff +#define BIT_TDE_LEN_TH1_8814B(x) \ + (((x) & BIT_MASK_TDE_LEN_TH1_8814B) << BIT_SHIFT_TDE_LEN_TH1_8814B) +#define BITS_TDE_LEN_TH1_8814B \ + (BIT_MASK_TDE_LEN_TH1_8814B << BIT_SHIFT_TDE_LEN_TH1_8814B) +#define BIT_CLEAR_TDE_LEN_TH1_8814B(x) ((x) & (~BITS_TDE_LEN_TH1_8814B)) +#define BIT_GET_TDE_LEN_TH1_8814B(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH1_8814B) & BIT_MASK_TDE_LEN_TH1_8814B) +#define BIT_SET_TDE_LEN_TH1_8814B(x, v) \ + (BIT_CLEAR_TDE_LEN_TH1_8814B(x) | BIT_TDE_LEN_TH1_8814B(v)) + +#define BIT_SHIFT_TDE_LEN_TH0_8814B 0 +#define BIT_MASK_TDE_LEN_TH0_8814B 0xffff +#define BIT_TDE_LEN_TH0_8814B(x) \ + (((x) & BIT_MASK_TDE_LEN_TH0_8814B) << BIT_SHIFT_TDE_LEN_TH0_8814B) +#define BITS_TDE_LEN_TH0_8814B \ + (BIT_MASK_TDE_LEN_TH0_8814B << BIT_SHIFT_TDE_LEN_TH0_8814B) +#define BIT_CLEAR_TDE_LEN_TH0_8814B(x) ((x) & (~BITS_TDE_LEN_TH0_8814B)) +#define BIT_GET_TDE_LEN_TH0_8814B(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH0_8814B) & BIT_MASK_TDE_LEN_TH0_8814B) +#define BIT_SET_TDE_LEN_TH0_8814B(x, v) \ + (BIT_CLEAR_TDE_LEN_TH0_8814B(x) | BIT_TDE_LEN_TH0_8814B(v)) + +/* 2 REG_RXDMA_LEN_THRESHOLD_8814B */ + +#define BIT_SHIFT_RDE_LEN_TH1_8814B 16 +#define BIT_MASK_RDE_LEN_TH1_8814B 0xffff +#define BIT_RDE_LEN_TH1_8814B(x) \ + (((x) & BIT_MASK_RDE_LEN_TH1_8814B) << BIT_SHIFT_RDE_LEN_TH1_8814B) +#define BITS_RDE_LEN_TH1_8814B \ + (BIT_MASK_RDE_LEN_TH1_8814B << BIT_SHIFT_RDE_LEN_TH1_8814B) +#define BIT_CLEAR_RDE_LEN_TH1_8814B(x) ((x) & (~BITS_RDE_LEN_TH1_8814B)) +#define BIT_GET_RDE_LEN_TH1_8814B(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH1_8814B) & BIT_MASK_RDE_LEN_TH1_8814B) +#define BIT_SET_RDE_LEN_TH1_8814B(x, v) \ + (BIT_CLEAR_RDE_LEN_TH1_8814B(x) | BIT_RDE_LEN_TH1_8814B(v)) + +#define BIT_SHIFT_RDE_LEN_TH0_8814B 0 +#define BIT_MASK_RDE_LEN_TH0_8814B 0xffff +#define BIT_RDE_LEN_TH0_8814B(x) \ + (((x) & BIT_MASK_RDE_LEN_TH0_8814B) << BIT_SHIFT_RDE_LEN_TH0_8814B) +#define BITS_RDE_LEN_TH0_8814B \ + (BIT_MASK_RDE_LEN_TH0_8814B << BIT_SHIFT_RDE_LEN_TH0_8814B) +#define BIT_CLEAR_RDE_LEN_TH0_8814B(x) ((x) & (~BITS_RDE_LEN_TH0_8814B)) +#define BIT_GET_RDE_LEN_TH0_8814B(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH0_8814B) & BIT_MASK_RDE_LEN_TH0_8814B) +#define BIT_SET_RDE_LEN_TH0_8814B(x, v) \ + (BIT_CLEAR_RDE_LEN_TH0_8814B(x) | BIT_RDE_LEN_TH0_8814B(v)) + +/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8814B */ + +#define BIT_SHIFT_COUNT_INT_SEL_8814B 16 +#define BIT_MASK_COUNT_INT_SEL_8814B 0x3 +#define BIT_COUNT_INT_SEL_8814B(x) \ + (((x) & BIT_MASK_COUNT_INT_SEL_8814B) << BIT_SHIFT_COUNT_INT_SEL_8814B) +#define BITS_COUNT_INT_SEL_8814B \ + (BIT_MASK_COUNT_INT_SEL_8814B << BIT_SHIFT_COUNT_INT_SEL_8814B) +#define BIT_CLEAR_COUNT_INT_SEL_8814B(x) ((x) & (~BITS_COUNT_INT_SEL_8814B)) +#define BIT_GET_COUNT_INT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_COUNT_INT_SEL_8814B) & BIT_MASK_COUNT_INT_SEL_8814B) +#define BIT_SET_COUNT_INT_SEL_8814B(x, v) \ + (BIT_CLEAR_COUNT_INT_SEL_8814B(x) | BIT_COUNT_INT_SEL_8814B(v)) + +#define BIT_SHIFT_EXEC_TIME_TH_8814B 0 +#define BIT_MASK_EXEC_TIME_TH_8814B 0xffff +#define BIT_EXEC_TIME_TH_8814B(x) \ + (((x) & BIT_MASK_EXEC_TIME_TH_8814B) << BIT_SHIFT_EXEC_TIME_TH_8814B) +#define BITS_EXEC_TIME_TH_8814B \ + (BIT_MASK_EXEC_TIME_TH_8814B << BIT_SHIFT_EXEC_TIME_TH_8814B) +#define BIT_CLEAR_EXEC_TIME_TH_8814B(x) ((x) & (~BITS_EXEC_TIME_TH_8814B)) +#define BIT_GET_EXEC_TIME_TH_8814B(x) \ + (((x) >> BIT_SHIFT_EXEC_TIME_TH_8814B) & BIT_MASK_EXEC_TIME_TH_8814B) +#define BIT_SET_EXEC_TIME_TH_8814B(x, v) \ + (BIT_CLEAR_EXEC_TIME_TH_8814B(x) | BIT_EXEC_TIME_TH_8814B(v)) /* 2 REG_FT2IMR_8814B */ #define BIT_FS_CLI3_RX_UAPSDMD1_EN_8814B BIT(31) @@ -3503,426 +6801,1019 @@ #define BIT_SHIFT_FW_MSG2_8814B 0 #define BIT_MASK_FW_MSG2_8814B 0xffffffffL -#define BIT_FW_MSG2_8814B(x) (((x) & BIT_MASK_FW_MSG2_8814B) << BIT_SHIFT_FW_MSG2_8814B) -#define BIT_GET_FW_MSG2_8814B(x) (((x) >> BIT_SHIFT_FW_MSG2_8814B) & BIT_MASK_FW_MSG2_8814B) - - +#define BIT_FW_MSG2_8814B(x) \ + (((x) & BIT_MASK_FW_MSG2_8814B) << BIT_SHIFT_FW_MSG2_8814B) +#define BITS_FW_MSG2_8814B (BIT_MASK_FW_MSG2_8814B << BIT_SHIFT_FW_MSG2_8814B) +#define BIT_CLEAR_FW_MSG2_8814B(x) ((x) & (~BITS_FW_MSG2_8814B)) +#define BIT_GET_FW_MSG2_8814B(x) \ + (((x) >> BIT_SHIFT_FW_MSG2_8814B) & BIT_MASK_FW_MSG2_8814B) +#define BIT_SET_FW_MSG2_8814B(x, v) \ + (BIT_CLEAR_FW_MSG2_8814B(x) | BIT_FW_MSG2_8814B(v)) /* 2 REG_MSG3_8814B */ #define BIT_SHIFT_FW_MSG3_8814B 0 #define BIT_MASK_FW_MSG3_8814B 0xffffffffL -#define BIT_FW_MSG3_8814B(x) (((x) & BIT_MASK_FW_MSG3_8814B) << BIT_SHIFT_FW_MSG3_8814B) -#define BIT_GET_FW_MSG3_8814B(x) (((x) >> BIT_SHIFT_FW_MSG3_8814B) & BIT_MASK_FW_MSG3_8814B) - - +#define BIT_FW_MSG3_8814B(x) \ + (((x) & BIT_MASK_FW_MSG3_8814B) << BIT_SHIFT_FW_MSG3_8814B) +#define BITS_FW_MSG3_8814B (BIT_MASK_FW_MSG3_8814B << BIT_SHIFT_FW_MSG3_8814B) +#define BIT_CLEAR_FW_MSG3_8814B(x) ((x) & (~BITS_FW_MSG3_8814B)) +#define BIT_GET_FW_MSG3_8814B(x) \ + (((x) >> BIT_SHIFT_FW_MSG3_8814B) & BIT_MASK_FW_MSG3_8814B) +#define BIT_SET_FW_MSG3_8814B(x, v) \ + (BIT_CLEAR_FW_MSG3_8814B(x) | BIT_FW_MSG3_8814B(v)) /* 2 REG_MSG4_8814B */ #define BIT_SHIFT_FW_MSG4_8814B 0 #define BIT_MASK_FW_MSG4_8814B 0xffffffffL -#define BIT_FW_MSG4_8814B(x) (((x) & BIT_MASK_FW_MSG4_8814B) << BIT_SHIFT_FW_MSG4_8814B) -#define BIT_GET_FW_MSG4_8814B(x) (((x) >> BIT_SHIFT_FW_MSG4_8814B) & BIT_MASK_FW_MSG4_8814B) - - +#define BIT_FW_MSG4_8814B(x) \ + (((x) & BIT_MASK_FW_MSG4_8814B) << BIT_SHIFT_FW_MSG4_8814B) +#define BITS_FW_MSG4_8814B (BIT_MASK_FW_MSG4_8814B << BIT_SHIFT_FW_MSG4_8814B) +#define BIT_CLEAR_FW_MSG4_8814B(x) ((x) & (~BITS_FW_MSG4_8814B)) +#define BIT_GET_FW_MSG4_8814B(x) \ + (((x) >> BIT_SHIFT_FW_MSG4_8814B) & BIT_MASK_FW_MSG4_8814B) +#define BIT_SET_FW_MSG4_8814B(x, v) \ + (BIT_CLEAR_FW_MSG4_8814B(x) | BIT_FW_MSG4_8814B(v)) /* 2 REG_MSG5_8814B */ #define BIT_SHIFT_FW_MSG5_8814B 0 #define BIT_MASK_FW_MSG5_8814B 0xffffffffL -#define BIT_FW_MSG5_8814B(x) (((x) & BIT_MASK_FW_MSG5_8814B) << BIT_SHIFT_FW_MSG5_8814B) -#define BIT_GET_FW_MSG5_8814B(x) (((x) >> BIT_SHIFT_FW_MSG5_8814B) & BIT_MASK_FW_MSG5_8814B) - +#define BIT_FW_MSG5_8814B(x) \ + (((x) & BIT_MASK_FW_MSG5_8814B) << BIT_SHIFT_FW_MSG5_8814B) +#define BITS_FW_MSG5_8814B (BIT_MASK_FW_MSG5_8814B << BIT_SHIFT_FW_MSG5_8814B) +#define BIT_CLEAR_FW_MSG5_8814B(x) ((x) & (~BITS_FW_MSG5_8814B)) +#define BIT_GET_FW_MSG5_8814B(x) \ + (((x) >> BIT_SHIFT_FW_MSG5_8814B) & BIT_MASK_FW_MSG5_8814B) +#define BIT_SET_FW_MSG5_8814B(x, v) \ + (BIT_CLEAR_FW_MSG5_8814B(x) | BIT_FW_MSG5_8814B(v)) +/* 2 REG_BIST_RSTN0_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_CTRL_1_8814B */ +/* 2 REG_BIST_RSTN2_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8814B 16 -#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8814B 0xff -#define BIT_TX_OQT_HE_FREE_SPACE_V1_8814B(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8814B) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8814B) -#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8814B(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8814B) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8814B) +/* 2 REG_BIST_MODE_NRML0_8814B */ + +/* 2 REG_BIST_MODE_NRML1_8814B */ +/* 2 REG_BIST_MODE_NRML2_8814B */ +/* 2 REG_BIST_MODE_NRML3_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8814B 0 -#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8814B 0xff -#define BIT_TX_OQT_NL_FREE_SPACE_V1_8814B(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8814B) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8814B) -#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8814B(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8814B) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_CTRL_2_8814B */ -#define BIT_BCN_VALID_1_V1_8814B BIT(31) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_HEAD_1_V1_8814B 16 -#define BIT_MASK_BCN_HEAD_1_V1_8814B 0xfff -#define BIT_BCN_HEAD_1_V1_8814B(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8814B) << BIT_SHIFT_BCN_HEAD_1_V1_8814B) -#define BIT_GET_BCN_HEAD_1_V1_8814B(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8814B) & BIT_MASK_BCN_HEAD_1_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_BCN_VALID_V1_8814B BIT(15) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_HEAD_V1_8814B 0 -#define BIT_MASK_BCN_HEAD_V1_8814B 0xfff -#define BIT_BCN_HEAD_V1_8814B(x) (((x) & BIT_MASK_BCN_HEAD_V1_8814B) << BIT_SHIFT_BCN_HEAD_V1_8814B) -#define BIT_GET_BCN_HEAD_V1_8814B(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8814B) & BIT_MASK_BCN_HEAD_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_BIST_DONE_NRML_MAC_8814B */ -/* 2 REG_AUTO_LLT_V1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B 24 -#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B 0xff -#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B) -#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B) +/* 2 REG_BIST_DONE_NRML1_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_BIST_DONE_DRF_MAC_8814B */ -#define BIT_SHIFT_LLT_FREE_PAGE_V1_8814B 8 -#define BIT_MASK_LLT_FREE_PAGE_V1_8814B 0xffff -#define BIT_LLT_FREE_PAGE_V1_8814B(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8814B) << BIT_SHIFT_LLT_FREE_PAGE_V1_8814B) -#define BIT_GET_LLT_FREE_PAGE_V1_8814B(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8814B) & BIT_MASK_LLT_FREE_PAGE_V1_8814B) +/* 2 REG_BIST_DONE_DRF_8814B */ +/* 2 REG_BIST_DONE_DRF1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BLK_DESC_NUM_8814B 4 -#define BIT_MASK_BLK_DESC_NUM_8814B 0xf -#define BIT_BLK_DESC_NUM_8814B(x) (((x) & BIT_MASK_BLK_DESC_NUM_8814B) << BIT_SHIFT_BLK_DESC_NUM_8814B) -#define BIT_GET_BLK_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8814B) & BIT_MASK_BLK_DESC_NUM_8814B) +/* 2 REG_BIST_FAIL_NRML_MAC_8814B */ +/* 2 REG_BIST_FAIL_NRML_8814B */ -#define BIT_R_BCN_HEAD_SEL_8814B BIT(3) -#define BIT_R_EN_BCN_SW_HEAD_SEL_8814B BIT(2) -#define BIT_LLT_DBG_SEL_8814B BIT(1) -#define BIT_AUTO_INIT_LLT_V1_8814B BIT(0) +/* 2 REG_BIST_FAIL_NRML1_8814B */ -/* 2 REG_TXDMA_OFFSET_CHK_8814B */ -#define BIT_EM_CHKSUM_FIN_8814B BIT(31) -#define BIT_EMN_PCIE_DMA_MOD_8814B BIT(30) -#define BIT_EN_TXQUE_CLR_8814B BIT(29) -#define BIT_EN_PCIE_FIFO_MODE_8814B BIT(28) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PG_UNDER_TH_V1_8814B 16 -#define BIT_MASK_PG_UNDER_TH_V1_8814B 0xfff -#define BIT_PG_UNDER_TH_V1_8814B(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8814B) << BIT_SHIFT_PG_UNDER_TH_V1_8814B) -#define BIT_GET_PG_UNDER_TH_V1_8814B(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8814B) & BIT_MASK_PG_UNDER_TH_V1_8814B) +/* 2 REG_BIST_FAIL_NRML_MAC_V1_8814B */ +/* 2 REG_BIST_FAIL_NRML_V1_8814B */ +/* 2 REG_BIST_FAIL_NRML1_V1_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SDIO_TXDESC_CHKSUM_EN_8814B BIT(13) -#define BIT_RST_RDPTR_8814B BIT(12) -#define BIT_RST_WRPTR_8814B BIT(11) -#define BIT_CHK_PG_TH_EN_8814B BIT(10) -#define BIT_DROP_DATA_EN_8814B BIT(9) -#define BIT_CHECK_OFFSET_EN_8814B BIT(8) -#define BIT_SHIFT_CHECK_OFFSET_8814B 0 -#define BIT_MASK_CHECK_OFFSET_8814B 0xff -#define BIT_CHECK_OFFSET_8814B(x) (((x) & BIT_MASK_CHECK_OFFSET_8814B) << BIT_SHIFT_CHECK_OFFSET_8814B) -#define BIT_GET_CHECK_OFFSET_8814B(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8814B) & BIT_MASK_CHECK_OFFSET_8814B) +/* 2 REG_BIST_MISR_DATAOUT_8814B */ +/* 2 REG_BIST_MISR_DATAOUT1_8814B */ +/* 2 REG_BIST_MISR_DATAOUT_CPU_8814B */ -/* 2 REG_TXDMA_STATUS_8814B */ -#define BIT_TXPKTBUF_REQ_ERR_8814B BIT(18) -#define BIT_HI_OQT_UDN_8814B BIT(17) -#define BIT_HI_OQT_OVF_8814B BIT(16) -#define BIT_PAYLOAD_CHKSUM_ERR_8814B BIT(15) -#define BIT_PAYLOAD_UDN_8814B BIT(14) -#define BIT_PAYLOAD_OVF_8814B BIT(13) -#define BIT_DSC_CHKSUM_FAIL_8814B BIT(12) -#define BIT_UNKNOWN_QSEL_8814B BIT(11) -#define BIT_EP_QSEL_DIFF_8814B BIT(10) -#define BIT_TX_OFFS_UNMATCH_8814B BIT(9) -#define BIT_TXOQT_UDN_8814B BIT(8) -#define BIT_TXOQT_OVF_8814B BIT(7) -#define BIT_TXDMA_SFF_UDN_8814B BIT(6) -#define BIT_TXDMA_SFF_OVF_8814B BIT(5) -#define BIT_LLT_NULL_PG_8814B BIT(4) -#define BIT_PAGE_UDN_8814B BIT(3) -#define BIT_PAGE_OVF_8814B BIT(2) -#define BIT_TXFF_PG_UDN_8814B BIT(1) -#define BIT_TXFF_PG_OVF_8814B BIT(0) +/* 2 REG_BIST_MISR_DATAOUT_CPU1_8814B */ -/* 2 REG_TX_DMA_DBG_8814B */ +/* 2 REG_BIST_MISR_DATAOUT_CPU2_8814B */ -/* 2 REG_TQPNT1_8814B */ +/* 2 REG_BIST_MISR_DATOUT_CPU3_8814B */ -#define BIT_SHIFT_HPQ_HIGH_TH_V1_8814B 16 -#define BIT_MASK_HPQ_HIGH_TH_V1_8814B 0xfff -#define BIT_HPQ_HIGH_TH_V1_8814B(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8814B) << BIT_SHIFT_HPQ_HIGH_TH_V1_8814B) -#define BIT_GET_HPQ_HIGH_TH_V1_8814B(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8814B) & BIT_MASK_HPQ_HIGH_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_HPQ_LOW_TH_V1_8814B 0 -#define BIT_MASK_HPQ_LOW_TH_V1_8814B 0xfff -#define BIT_HPQ_LOW_TH_V1_8814B(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8814B) << BIT_SHIFT_HPQ_LOW_TH_V1_8814B) -#define BIT_GET_HPQ_LOW_TH_V1_8814B(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8814B) & BIT_MASK_HPQ_LOW_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TQPNT2_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NPQ_HIGH_TH_V1_8814B 16 -#define BIT_MASK_NPQ_HIGH_TH_V1_8814B 0xfff -#define BIT_NPQ_HIGH_TH_V1_8814B(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8814B) << BIT_SHIFT_NPQ_HIGH_TH_V1_8814B) -#define BIT_GET_NPQ_HIGH_TH_V1_8814B(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8814B) & BIT_MASK_NPQ_HIGH_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NPQ_LOW_TH_V1_8814B 0 -#define BIT_MASK_NPQ_LOW_TH_V1_8814B 0xfff -#define BIT_NPQ_LOW_TH_V1_8814B(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8814B) << BIT_SHIFT_NPQ_LOW_TH_V1_8814B) -#define BIT_GET_NPQ_LOW_TH_V1_8814B(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8814B) & BIT_MASK_NPQ_LOW_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TQPNT3_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_LPQ_HIGH_TH_V1_8814B 16 -#define BIT_MASK_LPQ_HIGH_TH_V1_8814B 0xfff -#define BIT_LPQ_HIGH_TH_V1_8814B(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8814B) << BIT_SHIFT_LPQ_HIGH_TH_V1_8814B) -#define BIT_GET_LPQ_HIGH_TH_V1_8814B(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8814B) & BIT_MASK_LPQ_HIGH_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_LPQ_LOW_TH_V1_8814B 0 -#define BIT_MASK_LPQ_LOW_TH_V1_8814B 0xfff -#define BIT_LPQ_LOW_TH_V1_8814B(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8814B) << BIT_SHIFT_LPQ_LOW_TH_V1_8814B) -#define BIT_GET_LPQ_LOW_TH_V1_8814B(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8814B) & BIT_MASK_LPQ_LOW_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TQPNT4_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_EXQ_HIGH_TH_V1_8814B 16 -#define BIT_MASK_EXQ_HIGH_TH_V1_8814B 0xfff -#define BIT_EXQ_HIGH_TH_V1_8814B(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8814B) << BIT_SHIFT_EXQ_HIGH_TH_V1_8814B) -#define BIT_GET_EXQ_HIGH_TH_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8814B) & BIT_MASK_EXQ_HIGH_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_EXQ_LOW_TH_V1_8814B 0 -#define BIT_MASK_EXQ_LOW_TH_V1_8814B 0xfff -#define BIT_EXQ_LOW_TH_V1_8814B(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8814B) << BIT_SHIFT_EXQ_LOW_TH_V1_8814B) -#define BIT_GET_EXQ_LOW_TH_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8814B) & BIT_MASK_EXQ_LOW_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RQPN_CTRL_1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXPKTNUM_H_8814B 16 -#define BIT_MASK_TXPKTNUM_H_8814B 0xffff -#define BIT_TXPKTNUM_H_8814B(x) (((x) & BIT_MASK_TXPKTNUM_H_8814B) << BIT_SHIFT_TXPKTNUM_H_8814B) -#define BIT_GET_TXPKTNUM_H_8814B(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8814B) & BIT_MASK_TXPKTNUM_H_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXPKTNUM_V2_8814B 0 -#define BIT_MASK_TXPKTNUM_V2_8814B 0xffff -#define BIT_TXPKTNUM_V2_8814B(x) (((x) & BIT_MASK_TXPKTNUM_V2_8814B) << BIT_SHIFT_TXPKTNUM_V2_8814B) -#define BIT_GET_TXPKTNUM_V2_8814B(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2_8814B) & BIT_MASK_TXPKTNUM_V2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RQPN_CTRL_2_8814B */ -#define BIT_LD_RQPN_8814B BIT(31) -#define BIT_EXQ_PUBLIC_DIS_V1_8814B BIT(19) -#define BIT_NPQ_PUBLIC_DIS_V1_8814B BIT(18) -#define BIT_LPQ_PUBLIC_DIS_V1_8814B BIT(17) -#define BIT_HPQ_PUBLIC_DIS_V1_8814B BIT(16) -#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_8814B BIT(15) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8814B 0 -#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8814B 0xfff -#define BIT_SDIO_TXAGG_ALIGN_SIZE_8814B(x) (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8814B) << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8814B) -#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8814B(x) (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8814B) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_INFO_1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_HPQ_AVAL_PG_V1_8814B 16 -#define BIT_MASK_HPQ_AVAL_PG_V1_8814B 0xfff -#define BIT_HPQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8814B) << BIT_SHIFT_HPQ_AVAL_PG_V1_8814B) -#define BIT_GET_HPQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8814B) & BIT_MASK_HPQ_AVAL_PG_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_HPQ_V1_8814B 0 -#define BIT_MASK_HPQ_V1_8814B 0xfff -#define BIT_HPQ_V1_8814B(x) (((x) & BIT_MASK_HPQ_V1_8814B) << BIT_SHIFT_HPQ_V1_8814B) -#define BIT_GET_HPQ_V1_8814B(x) (((x) >> BIT_SHIFT_HPQ_V1_8814B) & BIT_MASK_HPQ_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_INFO_2_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_LPQ_AVAL_PG_V1_8814B 16 -#define BIT_MASK_LPQ_AVAL_PG_V1_8814B 0xfff -#define BIT_LPQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8814B) << BIT_SHIFT_LPQ_AVAL_PG_V1_8814B) -#define BIT_GET_LPQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8814B) & BIT_MASK_LPQ_AVAL_PG_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_LPQ_V1_8814B 0 -#define BIT_MASK_LPQ_V1_8814B 0xfff -#define BIT_LPQ_V1_8814B(x) (((x) & BIT_MASK_LPQ_V1_8814B) << BIT_SHIFT_LPQ_V1_8814B) -#define BIT_GET_LPQ_V1_8814B(x) (((x) >> BIT_SHIFT_LPQ_V1_8814B) & BIT_MASK_LPQ_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_INFO_3_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NPQ_AVAL_PG_V1_8814B 16 -#define BIT_MASK_NPQ_AVAL_PG_V1_8814B 0xfff -#define BIT_NPQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8814B) << BIT_SHIFT_NPQ_AVAL_PG_V1_8814B) -#define BIT_GET_NPQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8814B) & BIT_MASK_NPQ_AVAL_PG_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NPQ_V1_8814B 0 -#define BIT_MASK_NPQ_V1_8814B 0xfff -#define BIT_NPQ_V1_8814B(x) (((x) & BIT_MASK_NPQ_V1_8814B) << BIT_SHIFT_NPQ_V1_8814B) -#define BIT_GET_NPQ_V1_8814B(x) (((x) >> BIT_SHIFT_NPQ_V1_8814B) & BIT_MASK_NPQ_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_INFO_4_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_EXQ_AVAL_PG_V1_8814B 16 -#define BIT_MASK_EXQ_AVAL_PG_V1_8814B 0xfff -#define BIT_EXQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8814B) << BIT_SHIFT_EXQ_AVAL_PG_V1_8814B) -#define BIT_GET_EXQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8814B) & BIT_MASK_EXQ_AVAL_PG_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_EXQ_V1_8814B 0 -#define BIT_MASK_EXQ_V1_8814B 0xfff -#define BIT_EXQ_V1_8814B(x) (((x) & BIT_MASK_EXQ_V1_8814B) << BIT_SHIFT_EXQ_V1_8814B) -#define BIT_GET_EXQ_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_V1_8814B) & BIT_MASK_EXQ_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_INFO_5_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8814B 16 -#define BIT_MASK_PUBQ_AVAL_PG_V1_8814B 0xfff -#define BIT_PUBQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8814B) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8814B) -#define BIT_GET_PUBQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8814B) & BIT_MASK_PUBQ_AVAL_PG_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PUBQ_V1_8814B 0 -#define BIT_MASK_PUBQ_V1_8814B 0xfff -#define BIT_PUBQ_V1_8814B(x) (((x) & BIT_MASK_PUBQ_V1_8814B) << BIT_SHIFT_PUBQ_V1_8814B) -#define BIT_GET_PUBQ_V1_8814B(x) (((x) >> BIT_SHIFT_PUBQ_V1_8814B) & BIT_MASK_PUBQ_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_H2C_HEAD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_H2C_HEAD_8814B 0 -#define BIT_MASK_H2C_HEAD_8814B 0x3ffff -#define BIT_H2C_HEAD_8814B(x) (((x) & BIT_MASK_H2C_HEAD_8814B) << BIT_SHIFT_H2C_HEAD_8814B) -#define BIT_GET_H2C_HEAD_8814B(x) (((x) >> BIT_SHIFT_H2C_HEAD_8814B) & BIT_MASK_H2C_HEAD_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_H2C_TAIL_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_H2C_TAIL_8814B 0 -#define BIT_MASK_H2C_TAIL_8814B 0x3ffff -#define BIT_H2C_TAIL_8814B(x) (((x) & BIT_MASK_H2C_TAIL_8814B) << BIT_SHIFT_H2C_TAIL_8814B) -#define BIT_GET_H2C_TAIL_8814B(x) (((x) >> BIT_SHIFT_H2C_TAIL_8814B) & BIT_MASK_H2C_TAIL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_H2C_READ_ADDR_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_H2C_READ_ADDR_8814B 0 -#define BIT_MASK_H2C_READ_ADDR_8814B 0x3ffff -#define BIT_H2C_READ_ADDR_8814B(x) (((x) & BIT_MASK_H2C_READ_ADDR_8814B) << BIT_SHIFT_H2C_READ_ADDR_8814B) -#define BIT_GET_H2C_READ_ADDR_8814B(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8814B) & BIT_MASK_H2C_READ_ADDR_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_H2C_WR_ADDR_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_H2C_WR_ADDR_8814B 0 -#define BIT_MASK_H2C_WR_ADDR_8814B 0x3ffff -#define BIT_H2C_WR_ADDR_8814B(x) (((x) & BIT_MASK_H2C_WR_ADDR_8814B) << BIT_SHIFT_H2C_WR_ADDR_8814B) -#define BIT_GET_H2C_WR_ADDR_8814B(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8814B) & BIT_MASK_H2C_WR_ADDR_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_BCN_CTRL_0_8814B */ +#define BIT_BCN1_VALID_8814B BIT(31) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_H2C_INFO_8814B */ -#define BIT_H2C_SPACE_VLD_8814B BIT(3) -#define BIT_H2C_WR_ADDR_RST_8814B BIT(2) +#define BIT_SHIFT_BCN1_HEAD_8814B 16 +#define BIT_MASK_BCN1_HEAD_8814B 0xfff +#define BIT_BCN1_HEAD_8814B(x) \ + (((x) & BIT_MASK_BCN1_HEAD_8814B) << BIT_SHIFT_BCN1_HEAD_8814B) +#define BITS_BCN1_HEAD_8814B \ + (BIT_MASK_BCN1_HEAD_8814B << BIT_SHIFT_BCN1_HEAD_8814B) +#define BIT_CLEAR_BCN1_HEAD_8814B(x) ((x) & (~BITS_BCN1_HEAD_8814B)) +#define BIT_GET_BCN1_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_BCN1_HEAD_8814B) & BIT_MASK_BCN1_HEAD_8814B) +#define BIT_SET_BCN1_HEAD_8814B(x, v) \ + (BIT_CLEAR_BCN1_HEAD_8814B(x) | BIT_BCN1_HEAD_8814B(v)) -#define BIT_SHIFT_H2C_LEN_SEL_8814B 0 -#define BIT_MASK_H2C_LEN_SEL_8814B 0x3 -#define BIT_H2C_LEN_SEL_8814B(x) (((x) & BIT_MASK_H2C_LEN_SEL_8814B) << BIT_SHIFT_H2C_LEN_SEL_8814B) -#define BIT_GET_H2C_LEN_SEL_8814B(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8814B) & BIT_MASK_H2C_LEN_SEL_8814B) +#define BIT_BCN0_VALID_8814B BIT(15) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_BCN0_HEAD_8814B 0 +#define BIT_MASK_BCN0_HEAD_8814B 0xfff +#define BIT_BCN0_HEAD_8814B(x) \ + (((x) & BIT_MASK_BCN0_HEAD_8814B) << BIT_SHIFT_BCN0_HEAD_8814B) +#define BITS_BCN0_HEAD_8814B \ + (BIT_MASK_BCN0_HEAD_8814B << BIT_SHIFT_BCN0_HEAD_8814B) +#define BIT_CLEAR_BCN0_HEAD_8814B(x) ((x) & (~BITS_BCN0_HEAD_8814B)) +#define BIT_GET_BCN0_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_BCN0_HEAD_8814B) & BIT_MASK_BCN0_HEAD_8814B) +#define BIT_SET_BCN0_HEAD_8814B(x, v) \ + (BIT_CLEAR_BCN0_HEAD_8814B(x) | BIT_BCN0_HEAD_8814B(v)) + +/* 2 REG_BCN_CTRL_1_8814B */ +#define BIT_BCN3_VALID_8814B BIT(31) -/* 2 REG_RXDMA_AGG_PG_TH_8814B */ +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_BCN3_HEAD_8814B 16 +#define BIT_MASK_BCN3_HEAD_8814B 0xfff +#define BIT_BCN3_HEAD_8814B(x) \ + (((x) & BIT_MASK_BCN3_HEAD_8814B) << BIT_SHIFT_BCN3_HEAD_8814B) +#define BITS_BCN3_HEAD_8814B \ + (BIT_MASK_BCN3_HEAD_8814B << BIT_SHIFT_BCN3_HEAD_8814B) +#define BIT_CLEAR_BCN3_HEAD_8814B(x) ((x) & (~BITS_BCN3_HEAD_8814B)) +#define BIT_GET_BCN3_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_BCN3_HEAD_8814B) & BIT_MASK_BCN3_HEAD_8814B) +#define BIT_SET_BCN3_HEAD_8814B(x, v) \ + (BIT_CLEAR_BCN3_HEAD_8814B(x) | BIT_BCN3_HEAD_8814B(v)) + +#define BIT_BCN2_VALID_8814B BIT(15) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_BCN2_HEAD_8814B 0 +#define BIT_MASK_BCN2_HEAD_8814B 0xfff +#define BIT_BCN2_HEAD_8814B(x) \ + (((x) & BIT_MASK_BCN2_HEAD_8814B) << BIT_SHIFT_BCN2_HEAD_8814B) +#define BITS_BCN2_HEAD_8814B \ + (BIT_MASK_BCN2_HEAD_8814B << BIT_SHIFT_BCN2_HEAD_8814B) +#define BIT_CLEAR_BCN2_HEAD_8814B(x) ((x) & (~BITS_BCN2_HEAD_8814B)) +#define BIT_GET_BCN2_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_BCN2_HEAD_8814B) & BIT_MASK_BCN2_HEAD_8814B) +#define BIT_SET_BCN2_HEAD_8814B(x, v) \ + (BIT_CLEAR_BCN2_HEAD_8814B(x) | BIT_BCN2_HEAD_8814B(v)) + +/* 2 REG_AUTO_LLT_V1_8814B */ + +#define BIT_SHIFT_MAX_TX_PKT_V1_8814B 24 +#define BIT_MASK_MAX_TX_PKT_V1_8814B 0xff +#define BIT_MAX_TX_PKT_V1_8814B(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_V1_8814B) << BIT_SHIFT_MAX_TX_PKT_V1_8814B) +#define BITS_MAX_TX_PKT_V1_8814B \ + (BIT_MASK_MAX_TX_PKT_V1_8814B << BIT_SHIFT_MAX_TX_PKT_V1_8814B) +#define BIT_CLEAR_MAX_TX_PKT_V1_8814B(x) ((x) & (~BITS_MAX_TX_PKT_V1_8814B)) +#define BIT_GET_MAX_TX_PKT_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_V1_8814B) & BIT_MASK_MAX_TX_PKT_V1_8814B) +#define BIT_SET_MAX_TX_PKT_V1_8814B(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_V1_8814B(x) | BIT_MAX_TX_PKT_V1_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B 20 +#define BIT_MASK_R_BCN_HEAD_SEL_V1_8814B 0x7 +#define BIT_R_BCN_HEAD_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_R_BCN_HEAD_SEL_V1_8814B) \ + << BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B) +#define BITS_R_BCN_HEAD_SEL_V1_8814B \ + (BIT_MASK_R_BCN_HEAD_SEL_V1_8814B << BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B) +#define BIT_CLEAR_R_BCN_HEAD_SEL_V1_8814B(x) \ + ((x) & (~BITS_R_BCN_HEAD_SEL_V1_8814B)) +#define BIT_GET_R_BCN_HEAD_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B) & \ + BIT_MASK_R_BCN_HEAD_SEL_V1_8814B) +#define BIT_SET_R_BCN_HEAD_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_R_BCN_HEAD_SEL_V1_8814B(x) | BIT_R_BCN_HEAD_SEL_V1_8814B(v)) + +#define BIT_SHIFT_LLT_FREE_PAGE_V2_8814B 8 +#define BIT_MASK_LLT_FREE_PAGE_V2_8814B 0xfff +#define BIT_LLT_FREE_PAGE_V2_8814B(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V2_8814B) \ + << BIT_SHIFT_LLT_FREE_PAGE_V2_8814B) +#define BITS_LLT_FREE_PAGE_V2_8814B \ + (BIT_MASK_LLT_FREE_PAGE_V2_8814B << BIT_SHIFT_LLT_FREE_PAGE_V2_8814B) +#define BIT_CLEAR_LLT_FREE_PAGE_V2_8814B(x) \ + ((x) & (~BITS_LLT_FREE_PAGE_V2_8814B)) +#define BIT_GET_LLT_FREE_PAGE_V2_8814B(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2_8814B) & \ + BIT_MASK_LLT_FREE_PAGE_V2_8814B) +#define BIT_SET_LLT_FREE_PAGE_V2_8814B(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V2_8814B(x) | BIT_LLT_FREE_PAGE_V2_8814B(v)) + +#define BIT_SHIFT_BLK_DESC_NUM_8814B 4 +#define BIT_MASK_BLK_DESC_NUM_8814B 0xf +#define BIT_BLK_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_BLK_DESC_NUM_8814B) << BIT_SHIFT_BLK_DESC_NUM_8814B) +#define BITS_BLK_DESC_NUM_8814B \ + (BIT_MASK_BLK_DESC_NUM_8814B << BIT_SHIFT_BLK_DESC_NUM_8814B) +#define BIT_CLEAR_BLK_DESC_NUM_8814B(x) ((x) & (~BITS_BLK_DESC_NUM_8814B)) +#define BIT_GET_BLK_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_BLK_DESC_NUM_8814B) & BIT_MASK_BLK_DESC_NUM_8814B) +#define BIT_SET_BLK_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_BLK_DESC_NUM_8814B(x) | BIT_BLK_DESC_NUM_8814B(v)) + +#define BIT_TDE_ERROR_STOP_8814B BIT(3) +#define BIT_R_EN_BCN_SW_HEAD_SEL_8814B BIT(2) +#define BIT_LLT_DBG_SEL_8814B BIT(1) +#define BIT_AUTO_INIT_LLT_V1_8814B BIT(0) + +/* 2 REG_TXDMA_OFFSET_CHK_8814B */ +#define BIT_EM_CHKSUM_FIN_8814B BIT(31) +#define BIT_EMN_PCIE_DMA_MOD_8814B BIT(30) +#define BIT_EN_TXQUE_CLR_8814B BIT(29) +#define BIT_EN_PCIE_FIFO_MODE_8814B BIT(28) + +#define BIT_SHIFT_PG_UNDER_TH_V1_8814B 16 +#define BIT_MASK_PG_UNDER_TH_V1_8814B 0xfff +#define BIT_PG_UNDER_TH_V1_8814B(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V1_8814B) \ + << BIT_SHIFT_PG_UNDER_TH_V1_8814B) +#define BITS_PG_UNDER_TH_V1_8814B \ + (BIT_MASK_PG_UNDER_TH_V1_8814B << BIT_SHIFT_PG_UNDER_TH_V1_8814B) +#define BIT_CLEAR_PG_UNDER_TH_V1_8814B(x) ((x) & (~BITS_PG_UNDER_TH_V1_8814B)) +#define BIT_GET_PG_UNDER_TH_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8814B) & \ + BIT_MASK_PG_UNDER_TH_V1_8814B) +#define BIT_SET_PG_UNDER_TH_V1_8814B(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V1_8814B(x) | BIT_PG_UNDER_TH_V1_8814B(v)) + +#define BIT_R_EN_RESET_RESTORE_H2C_8814B BIT(15) +#define BIT_SDIO_TDE_FINISH_8814B BIT(14) +#define BIT_SDIO_TXDESC_CHKSUM_EN_8814B BIT(13) +#define BIT_RST_RDPTR_8814B BIT(12) +#define BIT_RST_WRPTR_8814B BIT(11) +#define BIT_CHK_PG_TH_EN_8814B BIT(10) +#define BIT_DROP_DATA_EN_8814B BIT(9) +#define BIT_CHECK_OFFSET_EN_8814B BIT(8) + +#define BIT_SHIFT_CHECK_OFFSET_8814B 0 +#define BIT_MASK_CHECK_OFFSET_8814B 0xff +#define BIT_CHECK_OFFSET_8814B(x) \ + (((x) & BIT_MASK_CHECK_OFFSET_8814B) << BIT_SHIFT_CHECK_OFFSET_8814B) +#define BITS_CHECK_OFFSET_8814B \ + (BIT_MASK_CHECK_OFFSET_8814B << BIT_SHIFT_CHECK_OFFSET_8814B) +#define BIT_CLEAR_CHECK_OFFSET_8814B(x) ((x) & (~BITS_CHECK_OFFSET_8814B)) +#define BIT_GET_CHECK_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_CHECK_OFFSET_8814B) & BIT_MASK_CHECK_OFFSET_8814B) +#define BIT_SET_CHECK_OFFSET_8814B(x, v) \ + (BIT_CLEAR_CHECK_OFFSET_8814B(x) | BIT_CHECK_OFFSET_8814B(v)) + +/* 2 REG_TXDMA_STATUS_8814B */ +#define BIT_AMSDU_PKT_SIZE_ERR_8814B BIT(31) +#define BIT_AMSDU_EN_ERR_8814B BIT(30) +#define BIT_CHKSUM_AMSDU_EN_ERR_8814B BIT(29) +#define BIT_TXPKTBF_REQ_ERR_8814B BIT(28) +#define BIT_OQT_UDN_16_8814B BIT(27) +#define BIT_OQT_OVF_16_8814B BIT(26) +#define BIT_OQT_UDN_14_15_8814B BIT(25) +#define BIT_OQT_OVF_14_15_8814B BIT(24) +#define BIT_OQT_UDN_13_8814B BIT(23) +#define BIT_OQT_OVF_13_8814B BIT(22) +#define BIT_OQT_UDN_12_8814B BIT(21) +#define BIT_OQT_OVF_12_8814B BIT(20) +#define BIT_OQT_UDN_8_11_8814B BIT(19) +#define BIT_OQT_OVF_8_11_8814B BIT(18) +#define BIT_OQT_UDN_4_7_8814B BIT(17) +#define BIT_OQT_OVF_4_7_8814B BIT(16) +#define BIT_PAYLOAD_CHKSUM_ERR_8814B BIT(15) +#define BIT_PAYLOAD_UDN_8814B BIT(14) +#define BIT_PAYLOAD_OVF_8814B BIT(13) +#define BIT_DSC_CHKSUM_FAIL_8814B BIT(12) +#define BIT_EP_QSEL_DIFF_8814B BIT(10) +#define BIT_TX_OFFS_UNMATCH_8814B BIT(9) +#define BIT_TXOQT_UDN_0_3_8814B BIT(8) +#define BIT_TXOQT_OVF_0_3_8814B BIT(7) +#define BIT_TXDMA_SFF_UDN_8814B BIT(6) +#define BIT_TXDMA_SFF_OVF_8814B BIT(5) +#define BIT_LLT_NULL_PG_8814B BIT(4) +#define BIT_PAGE_UDN_8814B BIT(3) +#define BIT_PAGE_OVF_8814B BIT(2) +#define BIT_TXFF_PG_UDN_8814B BIT(1) +#define BIT_TXFF_PG_OVF_8814B BIT(0) + +/* 2 REG_TX_DMA_DBG_8814B */ + +/* 2 REG_DMA_RQPN_INFO_PUB_8814B */ + +#define BIT_SHIFT_PUB_AVAL_PG_8814B 16 +#define BIT_MASK_PUB_AVAL_PG_8814B 0xfff +#define BIT_PUB_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_PUB_AVAL_PG_8814B) << BIT_SHIFT_PUB_AVAL_PG_8814B) +#define BITS_PUB_AVAL_PG_8814B \ + (BIT_MASK_PUB_AVAL_PG_8814B << BIT_SHIFT_PUB_AVAL_PG_8814B) +#define BIT_CLEAR_PUB_AVAL_PG_8814B(x) ((x) & (~BITS_PUB_AVAL_PG_8814B)) +#define BIT_GET_PUB_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_PUB_AVAL_PG_8814B) & BIT_MASK_PUB_AVAL_PG_8814B) +#define BIT_SET_PUB_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_PUB_AVAL_PG_8814B(x) | BIT_PUB_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_PUB_RSVD_PG_8814B 0 +#define BIT_MASK_PUB_RSVD_PG_8814B 0xfff +#define BIT_PUB_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_PUB_RSVD_PG_8814B) << BIT_SHIFT_PUB_RSVD_PG_8814B) +#define BITS_PUB_RSVD_PG_8814B \ + (BIT_MASK_PUB_RSVD_PG_8814B << BIT_SHIFT_PUB_RSVD_PG_8814B) +#define BIT_CLEAR_PUB_RSVD_PG_8814B(x) ((x) & (~BITS_PUB_RSVD_PG_8814B)) +#define BIT_GET_PUB_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_PUB_RSVD_PG_8814B) & BIT_MASK_PUB_RSVD_PG_8814B) +#define BIT_SET_PUB_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_PUB_RSVD_PG_8814B(x) | BIT_PUB_RSVD_PG_8814B(v)) + +/* 2 REG_RQPN_CTRL_2_V1_8814B */ +#define BIT_LD_RQPN_V1_8814B BIT(31) + +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8814B 24 -#define BIT_MASK_RXDMA_AGG_OLD_MOD_8814B 0xff -#define BIT_RXDMA_AGG_OLD_MOD_8814B(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD_8814B) << BIT_SHIFT_RXDMA_AGG_OLD_MOD_8814B) -#define BIT_GET_RXDMA_AGG_OLD_MOD_8814B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8814B) & BIT_MASK_RXDMA_AGG_OLD_MOD_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CH16_PUBLIC_DIS_8814B BIT(16) +#define BIT_CH15_PUBLIC_DIS_8814B BIT(15) +#define BIT_CH14_PUBLIC_DIS_8814B BIT(14) +#define BIT_CH13_PUBLIC_DIS_8814B BIT(13) +#define BIT_CH12_PUBLIC_DIS_8814B BIT(12) +#define BIT_CH11_PUBLIC_DIS_8814B BIT(11) +#define BIT_CH10_PUBLIC_DIS_8814B BIT(10) +#define BIT_CH9_PUBLIC_DIS_8814B BIT(9) +#define BIT_CH8_PUBLIC_DIS_8814B BIT(8) +#define BIT_CH7_PUBLIC_DIS_8814B BIT(7) +#define BIT_CH6_PUBLIC_DIS_8814B BIT(6) +#define BIT_CH5_PUBLIC_DIS_8814B BIT(5) +#define BIT_CH4_PUBLIC_DIS_8814B BIT(4) +#define BIT_CH3_PUBLIC_DIS_8814B BIT(3) +#define BIT_CH2_PUBLIC_DIS_8814B BIT(2) +#define BIT_CH1_PUBLIC_DIS_8814B BIT(1) +#define BIT_CH0_PUBLIC_DIS_8814B BIT(0) + +/* 2 REG_BCN_CTRL_2_8814B */ +#define BIT_BCN0_EXT_VALID_8814B BIT(31) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_BCN0_EXT_HEAD_8814B 16 +#define BIT_MASK_BCN0_EXT_HEAD_8814B 0xfff +#define BIT_BCN0_EXT_HEAD_8814B(x) \ + (((x) & BIT_MASK_BCN0_EXT_HEAD_8814B) << BIT_SHIFT_BCN0_EXT_HEAD_8814B) +#define BITS_BCN0_EXT_HEAD_8814B \ + (BIT_MASK_BCN0_EXT_HEAD_8814B << BIT_SHIFT_BCN0_EXT_HEAD_8814B) +#define BIT_CLEAR_BCN0_EXT_HEAD_8814B(x) ((x) & (~BITS_BCN0_EXT_HEAD_8814B)) +#define BIT_GET_BCN0_EXT_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_BCN0_EXT_HEAD_8814B) & BIT_MASK_BCN0_EXT_HEAD_8814B) +#define BIT_SET_BCN0_EXT_HEAD_8814B(x, v) \ + (BIT_CLEAR_BCN0_EXT_HEAD_8814B(x) | BIT_BCN0_EXT_HEAD_8814B(v)) + +#define BIT_BCN4_VALID_8814B BIT(15) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_BCN4_HEAD_8814B 0 +#define BIT_MASK_BCN4_HEAD_8814B 0xfff +#define BIT_BCN4_HEAD_8814B(x) \ + (((x) & BIT_MASK_BCN4_HEAD_8814B) << BIT_SHIFT_BCN4_HEAD_8814B) +#define BITS_BCN4_HEAD_8814B \ + (BIT_MASK_BCN4_HEAD_8814B << BIT_SHIFT_BCN4_HEAD_8814B) +#define BIT_CLEAR_BCN4_HEAD_8814B(x) ((x) & (~BITS_BCN4_HEAD_8814B)) +#define BIT_GET_BCN4_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_BCN4_HEAD_8814B) & BIT_MASK_BCN4_HEAD_8814B) +#define BIT_SET_BCN4_HEAD_8814B(x, v) \ + (BIT_CLEAR_BCN4_HEAD_8814B(x) | BIT_BCN4_HEAD_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_TXPKTNUM_0_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH4_7_8814B 16 +#define BIT_MASK_TXPKTNUM_CH4_7_8814B 0xfff +#define BIT_TXPKTNUM_CH4_7_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH4_7_8814B) \ + << BIT_SHIFT_TXPKTNUM_CH4_7_8814B) +#define BITS_TXPKTNUM_CH4_7_8814B \ + (BIT_MASK_TXPKTNUM_CH4_7_8814B << BIT_SHIFT_TXPKTNUM_CH4_7_8814B) +#define BIT_CLEAR_TXPKTNUM_CH4_7_8814B(x) ((x) & (~BITS_TXPKTNUM_CH4_7_8814B)) +#define BIT_GET_TXPKTNUM_CH4_7_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH4_7_8814B) & \ + BIT_MASK_TXPKTNUM_CH4_7_8814B) +#define BIT_SET_TXPKTNUM_CH4_7_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH4_7_8814B(x) | BIT_TXPKTNUM_CH4_7_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH0_3_8814B 0 +#define BIT_MASK_TXPKTNUM_CH0_3_8814B 0xfff +#define BIT_TXPKTNUM_CH0_3_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH0_3_8814B) \ + << BIT_SHIFT_TXPKTNUM_CH0_3_8814B) +#define BITS_TXPKTNUM_CH0_3_8814B \ + (BIT_MASK_TXPKTNUM_CH0_3_8814B << BIT_SHIFT_TXPKTNUM_CH0_3_8814B) +#define BIT_CLEAR_TXPKTNUM_CH0_3_8814B(x) ((x) & (~BITS_TXPKTNUM_CH0_3_8814B)) +#define BIT_GET_TXPKTNUM_CH0_3_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH0_3_8814B) & \ + BIT_MASK_TXPKTNUM_CH0_3_8814B) +#define BIT_SET_TXPKTNUM_CH0_3_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH0_3_8814B(x) | BIT_TXPKTNUM_CH0_3_8814B(v)) + +/* 2 REG_TXPKTNUM_1_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH12_8814B 16 +#define BIT_MASK_TXPKTNUM_CH12_8814B 0xfff +#define BIT_TXPKTNUM_CH12_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH12_8814B) << BIT_SHIFT_TXPKTNUM_CH12_8814B) +#define BITS_TXPKTNUM_CH12_8814B \ + (BIT_MASK_TXPKTNUM_CH12_8814B << BIT_SHIFT_TXPKTNUM_CH12_8814B) +#define BIT_CLEAR_TXPKTNUM_CH12_8814B(x) ((x) & (~BITS_TXPKTNUM_CH12_8814B)) +#define BIT_GET_TXPKTNUM_CH12_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH12_8814B) & BIT_MASK_TXPKTNUM_CH12_8814B) +#define BIT_SET_TXPKTNUM_CH12_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH12_8814B(x) | BIT_TXPKTNUM_CH12_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH8_11_8814B 0 +#define BIT_MASK_TXPKTNUM_CH8_11_8814B 0xfff +#define BIT_TXPKTNUM_CH8_11_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH8_11_8814B) \ + << BIT_SHIFT_TXPKTNUM_CH8_11_8814B) +#define BITS_TXPKTNUM_CH8_11_8814B \ + (BIT_MASK_TXPKTNUM_CH8_11_8814B << BIT_SHIFT_TXPKTNUM_CH8_11_8814B) +#define BIT_CLEAR_TXPKTNUM_CH8_11_8814B(x) ((x) & (~BITS_TXPKTNUM_CH8_11_8814B)) +#define BIT_GET_TXPKTNUM_CH8_11_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH8_11_8814B) & \ + BIT_MASK_TXPKTNUM_CH8_11_8814B) +#define BIT_SET_TXPKTNUM_CH8_11_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH8_11_8814B(x) | BIT_TXPKTNUM_CH8_11_8814B(v)) + +/* 2 REG_TXPKTNUM_2_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH14_15_8814B 16 +#define BIT_MASK_TXPKTNUM_CH14_15_8814B 0xfff +#define BIT_TXPKTNUM_CH14_15_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH14_15_8814B) \ + << BIT_SHIFT_TXPKTNUM_CH14_15_8814B) +#define BITS_TXPKTNUM_CH14_15_8814B \ + (BIT_MASK_TXPKTNUM_CH14_15_8814B << BIT_SHIFT_TXPKTNUM_CH14_15_8814B) +#define BIT_CLEAR_TXPKTNUM_CH14_15_8814B(x) \ + ((x) & (~BITS_TXPKTNUM_CH14_15_8814B)) +#define BIT_GET_TXPKTNUM_CH14_15_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH14_15_8814B) & \ + BIT_MASK_TXPKTNUM_CH14_15_8814B) +#define BIT_SET_TXPKTNUM_CH14_15_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH14_15_8814B(x) | BIT_TXPKTNUM_CH14_15_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_TXPKTNUM_CH13_8814B 0 +#define BIT_MASK_TXPKTNUM_CH13_8814B 0xfff +#define BIT_TXPKTNUM_CH13_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH13_8814B) << BIT_SHIFT_TXPKTNUM_CH13_8814B) +#define BITS_TXPKTNUM_CH13_8814B \ + (BIT_MASK_TXPKTNUM_CH13_8814B << BIT_SHIFT_TXPKTNUM_CH13_8814B) +#define BIT_CLEAR_TXPKTNUM_CH13_8814B(x) ((x) & (~BITS_TXPKTNUM_CH13_8814B)) +#define BIT_GET_TXPKTNUM_CH13_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH13_8814B) & BIT_MASK_TXPKTNUM_CH13_8814B) +#define BIT_SET_TXPKTNUM_CH13_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH13_8814B(x) | BIT_TXPKTNUM_CH13_8814B(v)) +/* 2 REG_TXPKTNUM_3_8814B */ -#define BIT_SHIFT_PKT_NUM_WOL_8814B 16 -#define BIT_MASK_PKT_NUM_WOL_8814B 0xff -#define BIT_PKT_NUM_WOL_8814B(x) (((x) & BIT_MASK_PKT_NUM_WOL_8814B) << BIT_SHIFT_PKT_NUM_WOL_8814B) -#define BIT_GET_PKT_NUM_WOL_8814B(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8814B) & BIT_MASK_PKT_NUM_WOL_8814B) +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH16_8814B 0 +#define BIT_MASK_TXPKTNUM_CH16_8814B 0xfff +#define BIT_TXPKTNUM_CH16_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH16_8814B) << BIT_SHIFT_TXPKTNUM_CH16_8814B) +#define BITS_TXPKTNUM_CH16_8814B \ + (BIT_MASK_TXPKTNUM_CH16_8814B << BIT_SHIFT_TXPKTNUM_CH16_8814B) +#define BIT_CLEAR_TXPKTNUM_CH16_8814B(x) ((x) & (~BITS_TXPKTNUM_CH16_8814B)) +#define BIT_GET_TXPKTNUM_CH16_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH16_8814B) & BIT_MASK_TXPKTNUM_CH16_8814B) +#define BIT_SET_TXPKTNUM_CH16_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH16_8814B(x) | BIT_TXPKTNUM_CH16_8814B(v)) + +/* 2 REG_TX_AGG_ALIGN_8814B */ + +#define BIT_SHIFT_HW_FLOW_CTL_EN_8814B 16 +#define BIT_MASK_HW_FLOW_CTL_EN_8814B 0xffff +#define BIT_HW_FLOW_CTL_EN_8814B(x) \ + (((x) & BIT_MASK_HW_FLOW_CTL_EN_8814B) \ + << BIT_SHIFT_HW_FLOW_CTL_EN_8814B) +#define BITS_HW_FLOW_CTL_EN_8814B \ + (BIT_MASK_HW_FLOW_CTL_EN_8814B << BIT_SHIFT_HW_FLOW_CTL_EN_8814B) +#define BIT_CLEAR_HW_FLOW_CTL_EN_8814B(x) ((x) & (~BITS_HW_FLOW_CTL_EN_8814B)) +#define BIT_GET_HW_FLOW_CTL_EN_8814B(x) \ + (((x) >> BIT_SHIFT_HW_FLOW_CTL_EN_8814B) & \ + BIT_MASK_HW_FLOW_CTL_EN_8814B) +#define BIT_SET_HW_FLOW_CTL_EN_8814B(x, v) \ + (BIT_CLEAR_HW_FLOW_CTL_EN_8814B(x) | BIT_HW_FLOW_CTL_EN_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_V1_8814B BIT(15) + +#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B 0 +#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B 0xfff +#define BIT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) \ + (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) +#define BITS_SDIO_TXAGG_ALIGN_SIZE_V1_8814B \ + (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) +#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) \ + ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)) +#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) & \ + BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) +#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x, v) \ + (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) | \ + BIT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(v)) + +/* 2 REG_H2C_HEAD_8814B */ + +#define BIT_SHIFT_H2C_HEAD_V1_8814B 0 +#define BIT_MASK_H2C_HEAD_V1_8814B 0x7ffff +#define BIT_H2C_HEAD_V1_8814B(x) \ + (((x) & BIT_MASK_H2C_HEAD_V1_8814B) << BIT_SHIFT_H2C_HEAD_V1_8814B) +#define BITS_H2C_HEAD_V1_8814B \ + (BIT_MASK_H2C_HEAD_V1_8814B << BIT_SHIFT_H2C_HEAD_V1_8814B) +#define BIT_CLEAR_H2C_HEAD_V1_8814B(x) ((x) & (~BITS_H2C_HEAD_V1_8814B)) +#define BIT_GET_H2C_HEAD_V1_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_V1_8814B) & BIT_MASK_H2C_HEAD_V1_8814B) +#define BIT_SET_H2C_HEAD_V1_8814B(x, v) \ + (BIT_CLEAR_H2C_HEAD_V1_8814B(x) | BIT_H2C_HEAD_V1_8814B(v)) + +/* 2 REG_H2C_TAIL_8814B */ + +#define BIT_SHIFT_H2C_TAIL_V1_8814B 0 +#define BIT_MASK_H2C_TAIL_V1_8814B 0x7ffff +#define BIT_H2C_TAIL_V1_8814B(x) \ + (((x) & BIT_MASK_H2C_TAIL_V1_8814B) << BIT_SHIFT_H2C_TAIL_V1_8814B) +#define BITS_H2C_TAIL_V1_8814B \ + (BIT_MASK_H2C_TAIL_V1_8814B << BIT_SHIFT_H2C_TAIL_V1_8814B) +#define BIT_CLEAR_H2C_TAIL_V1_8814B(x) ((x) & (~BITS_H2C_TAIL_V1_8814B)) +#define BIT_GET_H2C_TAIL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_V1_8814B) & BIT_MASK_H2C_TAIL_V1_8814B) +#define BIT_SET_H2C_TAIL_V1_8814B(x, v) \ + (BIT_CLEAR_H2C_TAIL_V1_8814B(x) | BIT_H2C_TAIL_V1_8814B(v)) + +/* 2 REG_H2C_READ_ADDR_8814B */ +#define BIT_SHIFT_H2C_READ_ADDR_V1_8814B 0 +#define BIT_MASK_H2C_READ_ADDR_V1_8814B 0x7ffff +#define BIT_H2C_READ_ADDR_V1_8814B(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_V1_8814B) \ + << BIT_SHIFT_H2C_READ_ADDR_V1_8814B) +#define BITS_H2C_READ_ADDR_V1_8814B \ + (BIT_MASK_H2C_READ_ADDR_V1_8814B << BIT_SHIFT_H2C_READ_ADDR_V1_8814B) +#define BIT_CLEAR_H2C_READ_ADDR_V1_8814B(x) \ + ((x) & (~BITS_H2C_READ_ADDR_V1_8814B)) +#define BIT_GET_H2C_READ_ADDR_V1_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_V1_8814B) & \ + BIT_MASK_H2C_READ_ADDR_V1_8814B) +#define BIT_SET_H2C_READ_ADDR_V1_8814B(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_V1_8814B(x) | BIT_H2C_READ_ADDR_V1_8814B(v)) +/* 2 REG_H2C_WR_ADDR_8814B */ -#define BIT_SHIFT_DMA_AGG_TO_8814B 8 -#define BIT_MASK_DMA_AGG_TO_8814B 0xf -#define BIT_DMA_AGG_TO_8814B(x) (((x) & BIT_MASK_DMA_AGG_TO_8814B) << BIT_SHIFT_DMA_AGG_TO_8814B) -#define BIT_GET_DMA_AGG_TO_8814B(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_8814B) & BIT_MASK_DMA_AGG_TO_8814B) +#define BIT_SHIFT_H2C_WR_ADDR_V1_8814B 0 +#define BIT_MASK_H2C_WR_ADDR_V1_8814B 0x7ffff +#define BIT_H2C_WR_ADDR_V1_8814B(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_V1_8814B) \ + << BIT_SHIFT_H2C_WR_ADDR_V1_8814B) +#define BITS_H2C_WR_ADDR_V1_8814B \ + (BIT_MASK_H2C_WR_ADDR_V1_8814B << BIT_SHIFT_H2C_WR_ADDR_V1_8814B) +#define BIT_CLEAR_H2C_WR_ADDR_V1_8814B(x) ((x) & (~BITS_H2C_WR_ADDR_V1_8814B)) +#define BIT_GET_H2C_WR_ADDR_V1_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_V1_8814B) & \ + BIT_MASK_H2C_WR_ADDR_V1_8814B) +#define BIT_SET_H2C_WR_ADDR_V1_8814B(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_V1_8814B(x) | BIT_H2C_WR_ADDR_V1_8814B(v)) +/* 2 REG_H2C_INFO_8814B */ +#define BIT_H2C_SPACE_VLD_8814B BIT(3) +#define BIT_H2C_WR_ADDR_RST_8814B BIT(2) +#define BIT_SHIFT_H2C_LEN_SEL_8814B 0 +#define BIT_MASK_H2C_LEN_SEL_8814B 0x3 +#define BIT_H2C_LEN_SEL_8814B(x) \ + (((x) & BIT_MASK_H2C_LEN_SEL_8814B) << BIT_SHIFT_H2C_LEN_SEL_8814B) +#define BITS_H2C_LEN_SEL_8814B \ + (BIT_MASK_H2C_LEN_SEL_8814B << BIT_SHIFT_H2C_LEN_SEL_8814B) +#define BIT_CLEAR_H2C_LEN_SEL_8814B(x) ((x) & (~BITS_H2C_LEN_SEL_8814B)) +#define BIT_GET_H2C_LEN_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_LEN_SEL_8814B) & BIT_MASK_H2C_LEN_SEL_8814B) +#define BIT_SET_H2C_LEN_SEL_8814B(x, v) \ + (BIT_CLEAR_H2C_LEN_SEL_8814B(x) | BIT_H2C_LEN_SEL_8814B(v)) + +/* 2 REG_DMA_OQT_0_8814B */ + +#define BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B 24 +#define BIT_MASK_TX_OQT_12_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_12_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_12_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B) +#define BITS_TX_OQT_12_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_12_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_12_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_12_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_12_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_12_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_12_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_12_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_12_FREE_SPACE_8814B(v)) + +#define BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B 16 +#define BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_8_11_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B) +#define BITS_TX_OQT_8_11_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_8_11_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_8_11_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_8_11_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_8_11_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_8_11_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_8_11_FREE_SPACE_8814B(v)) + +#define BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B 8 +#define BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_4_7_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B) +#define BITS_TX_OQT_4_7_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_4_7_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_4_7_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_4_7_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_4_7_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_4_7_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_4_7_FREE_SPACE_8814B(v)) + +#define BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B 0 +#define BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_0_3_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B) +#define BITS_TX_OQT_0_3_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_0_3_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_0_3_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_0_3_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_0_3_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_0_3_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_0_3_FREE_SPACE_8814B(v)) + +/* 2 REG_DMA_OQT_1_8814B */ -#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8814B 0 -#define BIT_MASK_RXDMA_AGG_PG_TH_V1_8814B 0xf -#define BIT_RXDMA_AGG_PG_TH_V1_8814B(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8814B) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8814B) -#define BIT_GET_RXDMA_AGG_PG_TH_V1_8814B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8814B) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B 16 +#define BIT_MASK_TX_OQT_16_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_16_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_16_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B) +#define BITS_TX_OQT_16_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_16_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_16_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_16_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_16_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_16_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_16_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_16_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_16_FREE_SPACE_8814B(v)) + +#define BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B 8 +#define BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_14_15_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B) +#define BITS_TX_OQT_14_15_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_14_15_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_14_15_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_14_15_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_14_15_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_14_15_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_14_15_FREE_SPACE_8814B(v)) + +#define BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B 0 +#define BIT_MASK_TX_OQT_13_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_13_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_13_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B) +#define BITS_TX_OQT_13_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_13_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_13_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_13_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_13_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_13_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_13_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_13_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_13_FREE_SPACE_8814B(v)) +/* 2 REG_RXDMA_AGG_PG_TH_8814B */ +#define BIT_DMA_STORE_8814B BIT(31) -/* 2 REG_RXPKT_NUM_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_EN_PRE_CALC_8814B BIT(29) +#define BIT_RXAGG_SW_EN_8814B BIT(28) +#define BIT_RXAGG_SW_TRIG_8814B BIT(27) -#define BIT_SHIFT_RXPKT_NUM_8814B 24 -#define BIT_MASK_RXPKT_NUM_8814B 0xff -#define BIT_RXPKT_NUM_8814B(x) (((x) & BIT_MASK_RXPKT_NUM_8814B) << BIT_SHIFT_RXPKT_NUM_8814B) -#define BIT_GET_RXPKT_NUM_8814B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8814B) & BIT_MASK_RXPKT_NUM_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_DMA_AGG_TO_V1_8814B 8 +#define BIT_MASK_DMA_AGG_TO_V1_8814B 0xff +#define BIT_DMA_AGG_TO_V1_8814B(x) \ + (((x) & BIT_MASK_DMA_AGG_TO_V1_8814B) << BIT_SHIFT_DMA_AGG_TO_V1_8814B) +#define BITS_DMA_AGG_TO_V1_8814B \ + (BIT_MASK_DMA_AGG_TO_V1_8814B << BIT_SHIFT_DMA_AGG_TO_V1_8814B) +#define BIT_CLEAR_DMA_AGG_TO_V1_8814B(x) ((x) & (~BITS_DMA_AGG_TO_V1_8814B)) +#define BIT_GET_DMA_AGG_TO_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8814B) & BIT_MASK_DMA_AGG_TO_V1_8814B) +#define BIT_SET_DMA_AGG_TO_V1_8814B(x, v) \ + (BIT_CLEAR_DMA_AGG_TO_V1_8814B(x) | BIT_DMA_AGG_TO_V1_8814B(v)) + +#define BIT_SHIFT_RXDMA_AGG_PG_TH_8814B 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_8814B 0xff +#define BIT_RXDMA_AGG_PG_TH_8814B(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8814B) \ + << BIT_SHIFT_RXDMA_AGG_PG_TH_8814B) +#define BITS_RXDMA_AGG_PG_TH_8814B \ + (BIT_MASK_RXDMA_AGG_PG_TH_8814B << BIT_SHIFT_RXDMA_AGG_PG_TH_8814B) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_8814B(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8814B)) +#define BIT_GET_RXDMA_AGG_PG_TH_8814B(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8814B) & \ + BIT_MASK_RXDMA_AGG_PG_TH_8814B) +#define BIT_SET_RXDMA_AGG_PG_TH_8814B(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_8814B(x) | BIT_RXDMA_AGG_PG_TH_8814B(v)) + +/* 2 REG_RXDMA_CTRL_8814B */ +/* 2 REG_NOT_VALID_8814B */ #define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B 20 #define BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B 0xf -#define BIT_FW_UPD_RDPTR19_TO_16_8814B(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) -#define BIT_GET_FW_UPD_RDPTR19_TO_16_8814B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B) - +#define BIT_FW_UPD_RDPTR19_TO_16_8814B(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B) \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) +#define BITS_FW_UPD_RDPTR19_TO_16_8814B \ + (BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8814B(x) \ + ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8814B)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8814B(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) & \ + BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B) +#define BIT_SET_FW_UPD_RDPTR19_TO_16_8814B(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8814B(x) | \ + BIT_FW_UPD_RDPTR19_TO_16_8814B(v)) #define BIT_RXDMA_REQ_8814B BIT(19) #define BIT_RW_RELEASE_EN_8814B BIT(18) @@ -3931,12 +7822,19 @@ #define BIT_SHIFT_FW_UPD_RDPTR_8814B 0 #define BIT_MASK_FW_UPD_RDPTR_8814B 0xffff -#define BIT_FW_UPD_RDPTR_8814B(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8814B) << BIT_SHIFT_FW_UPD_RDPTR_8814B) -#define BIT_GET_FW_UPD_RDPTR_8814B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8814B) & BIT_MASK_FW_UPD_RDPTR_8814B) - - +#define BIT_FW_UPD_RDPTR_8814B(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR_8814B) << BIT_SHIFT_FW_UPD_RDPTR_8814B) +#define BITS_FW_UPD_RDPTR_8814B \ + (BIT_MASK_FW_UPD_RDPTR_8814B << BIT_SHIFT_FW_UPD_RDPTR_8814B) +#define BIT_CLEAR_FW_UPD_RDPTR_8814B(x) ((x) & (~BITS_FW_UPD_RDPTR_8814B)) +#define BIT_GET_FW_UPD_RDPTR_8814B(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8814B) & BIT_MASK_FW_UPD_RDPTR_8814B) +#define BIT_SET_FW_UPD_RDPTR_8814B(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR_8814B(x) | BIT_FW_UPD_RDPTR_8814B(v)) /* 2 REG_RXDMA_STATUS_8814B */ + +/* 2 REG_NOT_VALID_8814B */ #define BIT_C2H_PKT_OVF_8814B BIT(7) #define BIT_AGG_CONFGI_ISSUE_8814B BIT(6) #define BIT_FW_POLL_ISSUE_8814B BIT(5) @@ -3949,40 +7847,70 @@ #define BIT_SHIFT_RDE_DEBUG_8814B 0 #define BIT_MASK_RDE_DEBUG_8814B 0xffffffffL -#define BIT_RDE_DEBUG_8814B(x) (((x) & BIT_MASK_RDE_DEBUG_8814B) << BIT_SHIFT_RDE_DEBUG_8814B) -#define BIT_GET_RDE_DEBUG_8814B(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8814B) & BIT_MASK_RDE_DEBUG_8814B) - - +#define BIT_RDE_DEBUG_8814B(x) \ + (((x) & BIT_MASK_RDE_DEBUG_8814B) << BIT_SHIFT_RDE_DEBUG_8814B) +#define BITS_RDE_DEBUG_8814B \ + (BIT_MASK_RDE_DEBUG_8814B << BIT_SHIFT_RDE_DEBUG_8814B) +#define BIT_CLEAR_RDE_DEBUG_8814B(x) ((x) & (~BITS_RDE_DEBUG_8814B)) +#define BIT_GET_RDE_DEBUG_8814B(x) \ + (((x) >> BIT_SHIFT_RDE_DEBUG_8814B) & BIT_MASK_RDE_DEBUG_8814B) +#define BIT_SET_RDE_DEBUG_8814B(x, v) \ + (BIT_CLEAR_RDE_DEBUG_8814B(x) | BIT_RDE_DEBUG_8814B(v)) /* 2 REG_RXDMA_MODE_8814B */ #define BIT_SHIFT_PKTNUM_TH_V2_8814B 24 #define BIT_MASK_PKTNUM_TH_V2_8814B 0x1f -#define BIT_PKTNUM_TH_V2_8814B(x) (((x) & BIT_MASK_PKTNUM_TH_V2_8814B) << BIT_SHIFT_PKTNUM_TH_V2_8814B) -#define BIT_GET_PKTNUM_TH_V2_8814B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8814B) & BIT_MASK_PKTNUM_TH_V2_8814B) - +#define BIT_PKTNUM_TH_V2_8814B(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V2_8814B) << BIT_SHIFT_PKTNUM_TH_V2_8814B) +#define BITS_PKTNUM_TH_V2_8814B \ + (BIT_MASK_PKTNUM_TH_V2_8814B << BIT_SHIFT_PKTNUM_TH_V2_8814B) +#define BIT_CLEAR_PKTNUM_TH_V2_8814B(x) ((x) & (~BITS_PKTNUM_TH_V2_8814B)) +#define BIT_GET_PKTNUM_TH_V2_8814B(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8814B) & BIT_MASK_PKTNUM_TH_V2_8814B) +#define BIT_SET_PKTNUM_TH_V2_8814B(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V2_8814B(x) | BIT_PKTNUM_TH_V2_8814B(v)) #define BIT_TXBA_BREAK_USBAGG_8814B BIT(23) #define BIT_SHIFT_PKTLEN_PARA_8814B 16 #define BIT_MASK_PKTLEN_PARA_8814B 0x7 -#define BIT_PKTLEN_PARA_8814B(x) (((x) & BIT_MASK_PKTLEN_PARA_8814B) << BIT_SHIFT_PKTLEN_PARA_8814B) -#define BIT_GET_PKTLEN_PARA_8814B(x) (((x) >> BIT_SHIFT_PKTLEN_PARA_8814B) & BIT_MASK_PKTLEN_PARA_8814B) - - +#define BIT_PKTLEN_PARA_8814B(x) \ + (((x) & BIT_MASK_PKTLEN_PARA_8814B) << BIT_SHIFT_PKTLEN_PARA_8814B) +#define BITS_PKTLEN_PARA_8814B \ + (BIT_MASK_PKTLEN_PARA_8814B << BIT_SHIFT_PKTLEN_PARA_8814B) +#define BIT_CLEAR_PKTLEN_PARA_8814B(x) ((x) & (~BITS_PKTLEN_PARA_8814B)) +#define BIT_GET_PKTLEN_PARA_8814B(x) \ + (((x) >> BIT_SHIFT_PKTLEN_PARA_8814B) & BIT_MASK_PKTLEN_PARA_8814B) +#define BIT_SET_PKTLEN_PARA_8814B(x, v) \ + (BIT_CLEAR_PKTLEN_PARA_8814B(x) | BIT_PKTLEN_PARA_8814B(v)) + +#define BIT_RX_DBG_SEL_8814B BIT(7) +#define BIT_EN_SPD_8814B BIT(6) #define BIT_SHIFT_BURST_SIZE_8814B 4 #define BIT_MASK_BURST_SIZE_8814B 0x3 -#define BIT_BURST_SIZE_8814B(x) (((x) & BIT_MASK_BURST_SIZE_8814B) << BIT_SHIFT_BURST_SIZE_8814B) -#define BIT_GET_BURST_SIZE_8814B(x) (((x) >> BIT_SHIFT_BURST_SIZE_8814B) & BIT_MASK_BURST_SIZE_8814B) - - +#define BIT_BURST_SIZE_8814B(x) \ + (((x) & BIT_MASK_BURST_SIZE_8814B) << BIT_SHIFT_BURST_SIZE_8814B) +#define BITS_BURST_SIZE_8814B \ + (BIT_MASK_BURST_SIZE_8814B << BIT_SHIFT_BURST_SIZE_8814B) +#define BIT_CLEAR_BURST_SIZE_8814B(x) ((x) & (~BITS_BURST_SIZE_8814B)) +#define BIT_GET_BURST_SIZE_8814B(x) \ + (((x) >> BIT_SHIFT_BURST_SIZE_8814B) & BIT_MASK_BURST_SIZE_8814B) +#define BIT_SET_BURST_SIZE_8814B(x, v) \ + (BIT_CLEAR_BURST_SIZE_8814B(x) | BIT_BURST_SIZE_8814B(v)) #define BIT_SHIFT_BURST_CNT_8814B 2 #define BIT_MASK_BURST_CNT_8814B 0x3 -#define BIT_BURST_CNT_8814B(x) (((x) & BIT_MASK_BURST_CNT_8814B) << BIT_SHIFT_BURST_CNT_8814B) -#define BIT_GET_BURST_CNT_8814B(x) (((x) >> BIT_SHIFT_BURST_CNT_8814B) & BIT_MASK_BURST_CNT_8814B) - +#define BIT_BURST_CNT_8814B(x) \ + (((x) & BIT_MASK_BURST_CNT_8814B) << BIT_SHIFT_BURST_CNT_8814B) +#define BITS_BURST_CNT_8814B \ + (BIT_MASK_BURST_CNT_8814B << BIT_SHIFT_BURST_CNT_8814B) +#define BIT_CLEAR_BURST_CNT_8814B(x) ((x) & (~BITS_BURST_CNT_8814B)) +#define BIT_GET_BURST_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_BURST_CNT_8814B) & BIT_MASK_BURST_CNT_8814B) +#define BIT_SET_BURST_CNT_8814B(x, v) \ + (BIT_CLEAR_BURST_CNT_8814B(x) | BIT_BURST_CNT_8814B(v)) #define BIT_DMA_MODE_8814B BIT(1) @@ -3990,81 +7918,234 @@ #define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B 24 #define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B 0xf -#define BIT_R_C2H_STR_ADDR_16_TO_19_8814B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) -#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8814B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B) - +#define BIT_R_C2H_STR_ADDR_16_TO_19_8814B(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B) \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) +#define BITS_R_C2H_STR_ADDR_16_TO_19_8814B \ + (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8814B(x) \ + ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8814B)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8814B(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) & \ + BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8814B(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8814B(x) | \ + BIT_R_C2H_STR_ADDR_16_TO_19_8814B(v)) #define BIT_R_C2H_PKT_REQ_8814B BIT(16) #define BIT_SHIFT_R_C2H_STR_ADDR_8814B 0 #define BIT_MASK_R_C2H_STR_ADDR_8814B 0xffff -#define BIT_R_C2H_STR_ADDR_8814B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8814B) << BIT_SHIFT_R_C2H_STR_ADDR_8814B) -#define BIT_GET_R_C2H_STR_ADDR_8814B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8814B) & BIT_MASK_R_C2H_STR_ADDR_8814B) - - +#define BIT_R_C2H_STR_ADDR_8814B(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_8814B) \ + << BIT_SHIFT_R_C2H_STR_ADDR_8814B) +#define BITS_R_C2H_STR_ADDR_8814B \ + (BIT_MASK_R_C2H_STR_ADDR_8814B << BIT_SHIFT_R_C2H_STR_ADDR_8814B) +#define BIT_CLEAR_R_C2H_STR_ADDR_8814B(x) ((x) & (~BITS_R_C2H_STR_ADDR_8814B)) +#define BIT_GET_R_C2H_STR_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8814B) & \ + BIT_MASK_R_C2H_STR_ADDR_8814B) +#define BIT_SET_R_C2H_STR_ADDR_8814B(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_8814B(x) | BIT_R_C2H_STR_ADDR_8814B(v)) /* 2 REG_FWFF_C2H_8814B */ #define BIT_SHIFT_C2H_DMA_ADDR_8814B 0 #define BIT_MASK_C2H_DMA_ADDR_8814B 0x3ffff -#define BIT_C2H_DMA_ADDR_8814B(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8814B) << BIT_SHIFT_C2H_DMA_ADDR_8814B) -#define BIT_GET_C2H_DMA_ADDR_8814B(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8814B) & BIT_MASK_C2H_DMA_ADDR_8814B) - - +#define BIT_C2H_DMA_ADDR_8814B(x) \ + (((x) & BIT_MASK_C2H_DMA_ADDR_8814B) << BIT_SHIFT_C2H_DMA_ADDR_8814B) +#define BITS_C2H_DMA_ADDR_8814B \ + (BIT_MASK_C2H_DMA_ADDR_8814B << BIT_SHIFT_C2H_DMA_ADDR_8814B) +#define BIT_CLEAR_C2H_DMA_ADDR_8814B(x) ((x) & (~BITS_C2H_DMA_ADDR_8814B)) +#define BIT_GET_C2H_DMA_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8814B) & BIT_MASK_C2H_DMA_ADDR_8814B) +#define BIT_SET_C2H_DMA_ADDR_8814B(x, v) \ + (BIT_CLEAR_C2H_DMA_ADDR_8814B(x) | BIT_C2H_DMA_ADDR_8814B(v)) /* 2 REG_FWFF_CTRL_8814B */ #define BIT_FWFF_DMAPKT_REQ_8814B BIT(31) -#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8814B 16 -#define BIT_MASK_FWFF_DMA_PKT_NUM_8814B 0xff -#define BIT_FWFF_DMA_PKT_NUM_8814B(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8814B) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8814B) -#define BIT_GET_FWFF_DMA_PKT_NUM_8814B(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8814B) & BIT_MASK_FWFF_DMA_PKT_NUM_8814B) - - +#define BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B 16 +#define BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B 0x7fff +#define BIT_FWFF_DMA_PKT_NUM_V1_8814B(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B) \ + << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B) +#define BITS_FWFF_DMA_PKT_NUM_V1_8814B \ + (BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B \ + << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_V1_8814B(x) \ + ((x) & (~BITS_FWFF_DMA_PKT_NUM_V1_8814B)) +#define BIT_GET_FWFF_DMA_PKT_NUM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B) & \ + BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B) +#define BIT_SET_FWFF_DMA_PKT_NUM_V1_8814B(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM_V1_8814B(x) | \ + BIT_FWFF_DMA_PKT_NUM_V1_8814B(v)) #define BIT_SHIFT_FWFF_STR_ADDR_8814B 0 #define BIT_MASK_FWFF_STR_ADDR_8814B 0xffff -#define BIT_FWFF_STR_ADDR_8814B(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8814B) << BIT_SHIFT_FWFF_STR_ADDR_8814B) -#define BIT_GET_FWFF_STR_ADDR_8814B(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8814B) & BIT_MASK_FWFF_STR_ADDR_8814B) - - +#define BIT_FWFF_STR_ADDR_8814B(x) \ + (((x) & BIT_MASK_FWFF_STR_ADDR_8814B) << BIT_SHIFT_FWFF_STR_ADDR_8814B) +#define BITS_FWFF_STR_ADDR_8814B \ + (BIT_MASK_FWFF_STR_ADDR_8814B << BIT_SHIFT_FWFF_STR_ADDR_8814B) +#define BIT_CLEAR_FWFF_STR_ADDR_8814B(x) ((x) & (~BITS_FWFF_STR_ADDR_8814B)) +#define BIT_GET_FWFF_STR_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8814B) & BIT_MASK_FWFF_STR_ADDR_8814B) +#define BIT_SET_FWFF_STR_ADDR_8814B(x, v) \ + (BIT_CLEAR_FWFF_STR_ADDR_8814B(x) | BIT_FWFF_STR_ADDR_8814B(v)) /* 2 REG_FWFF_PKT_INFO_8814B */ -#define BIT_SHIFT_FWFF_PKT_QUEUED_8814B 16 -#define BIT_MASK_FWFF_PKT_QUEUED_8814B 0xff -#define BIT_FWFF_PKT_QUEUED_8814B(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8814B) << BIT_SHIFT_FWFF_PKT_QUEUED_8814B) -#define BIT_GET_FWFF_PKT_QUEUED_8814B(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8814B) & BIT_MASK_FWFF_PKT_QUEUED_8814B) +#define BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B 16 +#define BIT_MASK_FWFF_PKT_READ_ADDR_8814B 0xffff +#define BIT_FWFF_PKT_READ_ADDR_8814B(x) \ + (((x) & BIT_MASK_FWFF_PKT_READ_ADDR_8814B) \ + << BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B) +#define BITS_FWFF_PKT_READ_ADDR_8814B \ + (BIT_MASK_FWFF_PKT_READ_ADDR_8814B \ + << BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B) +#define BIT_CLEAR_FWFF_PKT_READ_ADDR_8814B(x) \ + ((x) & (~BITS_FWFF_PKT_READ_ADDR_8814B)) +#define BIT_GET_FWFF_PKT_READ_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B) & \ + BIT_MASK_FWFF_PKT_READ_ADDR_8814B) +#define BIT_SET_FWFF_PKT_READ_ADDR_8814B(x, v) \ + (BIT_CLEAR_FWFF_PKT_READ_ADDR_8814B(x) | \ + BIT_FWFF_PKT_READ_ADDR_8814B(v)) + +#define BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B 0 +#define BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B 0xffff +#define BIT_FWFF_PKT_WRITE_ADDR_8814B(x) \ + (((x) & BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B) \ + << BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B) +#define BITS_FWFF_PKT_WRITE_ADDR_8814B \ + (BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B \ + << BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B) +#define BIT_CLEAR_FWFF_PKT_WRITE_ADDR_8814B(x) \ + ((x) & (~BITS_FWFF_PKT_WRITE_ADDR_8814B)) +#define BIT_GET_FWFF_PKT_WRITE_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B) & \ + BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B) +#define BIT_SET_FWFF_PKT_WRITE_ADDR_8814B(x, v) \ + (BIT_CLEAR_FWFF_PKT_WRITE_ADDR_8814B(x) | \ + BIT_FWFF_PKT_WRITE_ADDR_8814B(v)) + +/* 2 REG_FWFF_PKT_INFO2_8814B */ + +#define BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B 0 +#define BIT_MASK_FWFF_PKT_QUEUED_V1_8814B 0xffff +#define BIT_FWFF_PKT_QUEUED_V1_8814B(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED_V1_8814B) \ + << BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B) +#define BITS_FWFF_PKT_QUEUED_V1_8814B \ + (BIT_MASK_FWFF_PKT_QUEUED_V1_8814B \ + << BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B) +#define BIT_CLEAR_FWFF_PKT_QUEUED_V1_8814B(x) \ + ((x) & (~BITS_FWFF_PKT_QUEUED_V1_8814B)) +#define BIT_GET_FWFF_PKT_QUEUED_V1_8814B(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B) & \ + BIT_MASK_FWFF_PKT_QUEUED_V1_8814B) +#define BIT_SET_FWFF_PKT_QUEUED_V1_8814B(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED_V1_8814B(x) | \ + BIT_FWFF_PKT_QUEUED_V1_8814B(v)) + +/* 2 REG_RXPKTNUM_8814B */ + +#define BIT_SHIFT_PKT_NUM_WOL_V1_8814B 16 +#define BIT_MASK_PKT_NUM_WOL_V1_8814B 0xffff +#define BIT_PKT_NUM_WOL_V1_8814B(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL_V1_8814B) \ + << BIT_SHIFT_PKT_NUM_WOL_V1_8814B) +#define BITS_PKT_NUM_WOL_V1_8814B \ + (BIT_MASK_PKT_NUM_WOL_V1_8814B << BIT_SHIFT_PKT_NUM_WOL_V1_8814B) +#define BIT_CLEAR_PKT_NUM_WOL_V1_8814B(x) ((x) & (~BITS_PKT_NUM_WOL_V1_8814B)) +#define BIT_GET_PKT_NUM_WOL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL_V1_8814B) & \ + BIT_MASK_PKT_NUM_WOL_V1_8814B) +#define BIT_SET_PKT_NUM_WOL_V1_8814B(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL_V1_8814B(x) | BIT_PKT_NUM_WOL_V1_8814B(v)) + +#define BIT_SHIFT_RXPKT_NUM_V1_8814B 0 +#define BIT_MASK_RXPKT_NUM_V1_8814B 0xffff +#define BIT_RXPKT_NUM_V1_8814B(x) \ + (((x) & BIT_MASK_RXPKT_NUM_V1_8814B) << BIT_SHIFT_RXPKT_NUM_V1_8814B) +#define BITS_RXPKT_NUM_V1_8814B \ + (BIT_MASK_RXPKT_NUM_V1_8814B << BIT_SHIFT_RXPKT_NUM_V1_8814B) +#define BIT_CLEAR_RXPKT_NUM_V1_8814B(x) ((x) & (~BITS_RXPKT_NUM_V1_8814B)) +#define BIT_GET_RXPKT_NUM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_V1_8814B) & BIT_MASK_RXPKT_NUM_V1_8814B) +#define BIT_SET_RXPKT_NUM_V1_8814B(x, v) \ + (BIT_CLEAR_RXPKT_NUM_V1_8814B(x) | BIT_RXPKT_NUM_V1_8814B(v)) + +/* 2 REG_RXPKTNUM_TH_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_RXPKT_NUM_TH_8814B 0 +#define BIT_MASK_RXPKT_NUM_TH_8814B 0xff +#define BIT_RXPKT_NUM_TH_8814B(x) \ + (((x) & BIT_MASK_RXPKT_NUM_TH_8814B) << BIT_SHIFT_RXPKT_NUM_TH_8814B) +#define BITS_RXPKT_NUM_TH_8814B \ + (BIT_MASK_RXPKT_NUM_TH_8814B << BIT_SHIFT_RXPKT_NUM_TH_8814B) +#define BIT_CLEAR_RXPKT_NUM_TH_8814B(x) ((x) & (~BITS_RXPKT_NUM_TH_8814B)) +#define BIT_GET_RXPKT_NUM_TH_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_TH_8814B) & BIT_MASK_RXPKT_NUM_TH_8814B) +#define BIT_SET_RXPKT_NUM_TH_8814B(x, v) \ + (BIT_CLEAR_RXPKT_NUM_TH_8814B(x) | BIT_RXPKT_NUM_TH_8814B(v)) -#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8814B 0 -#define BIT_MASK_FWFF_PKT_STR_ADDR_8814B 0xffff -#define BIT_FWFF_PKT_STR_ADDR_8814B(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8814B) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8814B) -#define BIT_GET_FWFF_PKT_STR_ADDR_8814B(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8814B) & BIT_MASK_FWFF_PKT_STR_ADDR_8814B) +/* 2 REG_FW_UPD_RXDES_RDPTR_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B 0 +#define BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B 0x3ffff +#define BIT_FW_UPD_RXDES_RD_PTR_8814B(x) \ + (((x) & BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B) \ + << BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B) +#define BITS_FW_UPD_RXDES_RD_PTR_8814B \ + (BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B \ + << BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B) +#define BIT_CLEAR_FW_UPD_RXDES_RD_PTR_8814B(x) \ + ((x) & (~BITS_FW_UPD_RXDES_RD_PTR_8814B)) +#define BIT_GET_FW_UPD_RXDES_RD_PTR_8814B(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B) & \ + BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B) +#define BIT_SET_FW_UPD_RXDES_RD_PTR_8814B(x, v) \ + (BIT_CLEAR_FW_UPD_RXDES_RD_PTR_8814B(x) | \ + BIT_FW_UPD_RXDES_RD_PTR_8814B(v)) /* 2 REG_DDMA_CH0SA_8814B */ #define BIT_SHIFT_DDMACH0_SA_8814B 0 #define BIT_MASK_DDMACH0_SA_8814B 0xffffffffL -#define BIT_DDMACH0_SA_8814B(x) (((x) & BIT_MASK_DDMACH0_SA_8814B) << BIT_SHIFT_DDMACH0_SA_8814B) -#define BIT_GET_DDMACH0_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8814B) & BIT_MASK_DDMACH0_SA_8814B) - - +#define BIT_DDMACH0_SA_8814B(x) \ + (((x) & BIT_MASK_DDMACH0_SA_8814B) << BIT_SHIFT_DDMACH0_SA_8814B) +#define BITS_DDMACH0_SA_8814B \ + (BIT_MASK_DDMACH0_SA_8814B << BIT_SHIFT_DDMACH0_SA_8814B) +#define BIT_CLEAR_DDMACH0_SA_8814B(x) ((x) & (~BITS_DDMACH0_SA_8814B)) +#define BIT_GET_DDMACH0_SA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH0_SA_8814B) & BIT_MASK_DDMACH0_SA_8814B) +#define BIT_SET_DDMACH0_SA_8814B(x, v) \ + (BIT_CLEAR_DDMACH0_SA_8814B(x) | BIT_DDMACH0_SA_8814B(v)) /* 2 REG_DDMA_CH0DA_8814B */ #define BIT_SHIFT_DDMACH0_DA_8814B 0 #define BIT_MASK_DDMACH0_DA_8814B 0xffffffffL -#define BIT_DDMACH0_DA_8814B(x) (((x) & BIT_MASK_DDMACH0_DA_8814B) << BIT_SHIFT_DDMACH0_DA_8814B) -#define BIT_GET_DDMACH0_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8814B) & BIT_MASK_DDMACH0_DA_8814B) - - +#define BIT_DDMACH0_DA_8814B(x) \ + (((x) & BIT_MASK_DDMACH0_DA_8814B) << BIT_SHIFT_DDMACH0_DA_8814B) +#define BITS_DDMACH0_DA_8814B \ + (BIT_MASK_DDMACH0_DA_8814B << BIT_SHIFT_DDMACH0_DA_8814B) +#define BIT_CLEAR_DDMACH0_DA_8814B(x) ((x) & (~BITS_DDMACH0_DA_8814B)) +#define BIT_GET_DDMACH0_DA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DA_8814B) & BIT_MASK_DDMACH0_DA_8814B) +#define BIT_SET_DDMACH0_DA_8814B(x, v) \ + (BIT_CLEAR_DDMACH0_DA_8814B(x) | BIT_DDMACH0_DA_8814B(v)) /* 2 REG_DDMA_CH0CTRL_8814B */ #define BIT_DDMACH0_OWN_8814B BIT(31) +#define BIT_DDMACH0_IDMEM_ERR_8814B BIT(30) #define BIT_DDMACH0_CHKSUM_EN_8814B BIT(29) #define BIT_DDMACH0_DA_W_DISABLE_8814B BIT(28) #define BIT_DDMACH0_CHKSUM_STS_8814B BIT(27) @@ -4074,31 +8155,47 @@ #define BIT_SHIFT_DDMACH0_DLEN_8814B 0 #define BIT_MASK_DDMACH0_DLEN_8814B 0x3ffff -#define BIT_DDMACH0_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH0_DLEN_8814B) << BIT_SHIFT_DDMACH0_DLEN_8814B) -#define BIT_GET_DDMACH0_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8814B) & BIT_MASK_DDMACH0_DLEN_8814B) - - +#define BIT_DDMACH0_DLEN_8814B(x) \ + (((x) & BIT_MASK_DDMACH0_DLEN_8814B) << BIT_SHIFT_DDMACH0_DLEN_8814B) +#define BITS_DDMACH0_DLEN_8814B \ + (BIT_MASK_DDMACH0_DLEN_8814B << BIT_SHIFT_DDMACH0_DLEN_8814B) +#define BIT_CLEAR_DDMACH0_DLEN_8814B(x) ((x) & (~BITS_DDMACH0_DLEN_8814B)) +#define BIT_GET_DDMACH0_DLEN_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DLEN_8814B) & BIT_MASK_DDMACH0_DLEN_8814B) +#define BIT_SET_DDMACH0_DLEN_8814B(x, v) \ + (BIT_CLEAR_DDMACH0_DLEN_8814B(x) | BIT_DDMACH0_DLEN_8814B(v)) /* 2 REG_DDMA_CH1SA_8814B */ #define BIT_SHIFT_DDMACH1_SA_8814B 0 #define BIT_MASK_DDMACH1_SA_8814B 0xffffffffL -#define BIT_DDMACH1_SA_8814B(x) (((x) & BIT_MASK_DDMACH1_SA_8814B) << BIT_SHIFT_DDMACH1_SA_8814B) -#define BIT_GET_DDMACH1_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8814B) & BIT_MASK_DDMACH1_SA_8814B) - - +#define BIT_DDMACH1_SA_8814B(x) \ + (((x) & BIT_MASK_DDMACH1_SA_8814B) << BIT_SHIFT_DDMACH1_SA_8814B) +#define BITS_DDMACH1_SA_8814B \ + (BIT_MASK_DDMACH1_SA_8814B << BIT_SHIFT_DDMACH1_SA_8814B) +#define BIT_CLEAR_DDMACH1_SA_8814B(x) ((x) & (~BITS_DDMACH1_SA_8814B)) +#define BIT_GET_DDMACH1_SA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH1_SA_8814B) & BIT_MASK_DDMACH1_SA_8814B) +#define BIT_SET_DDMACH1_SA_8814B(x, v) \ + (BIT_CLEAR_DDMACH1_SA_8814B(x) | BIT_DDMACH1_SA_8814B(v)) /* 2 REG_DDMA_CH1DA_8814B */ #define BIT_SHIFT_DDMACH1_DA_8814B 0 #define BIT_MASK_DDMACH1_DA_8814B 0xffffffffL -#define BIT_DDMACH1_DA_8814B(x) (((x) & BIT_MASK_DDMACH1_DA_8814B) << BIT_SHIFT_DDMACH1_DA_8814B) -#define BIT_GET_DDMACH1_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8814B) & BIT_MASK_DDMACH1_DA_8814B) - - +#define BIT_DDMACH1_DA_8814B(x) \ + (((x) & BIT_MASK_DDMACH1_DA_8814B) << BIT_SHIFT_DDMACH1_DA_8814B) +#define BITS_DDMACH1_DA_8814B \ + (BIT_MASK_DDMACH1_DA_8814B << BIT_SHIFT_DDMACH1_DA_8814B) +#define BIT_CLEAR_DDMACH1_DA_8814B(x) ((x) & (~BITS_DDMACH1_DA_8814B)) +#define BIT_GET_DDMACH1_DA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DA_8814B) & BIT_MASK_DDMACH1_DA_8814B) +#define BIT_SET_DDMACH1_DA_8814B(x, v) \ + (BIT_CLEAR_DDMACH1_DA_8814B(x) | BIT_DDMACH1_DA_8814B(v)) /* 2 REG_DDMA_CH1CTRL_8814B */ #define BIT_DDMACH1_OWN_8814B BIT(31) +#define BIT_DDMACH1_IDMEM_ERR_8814B BIT(30) #define BIT_DDMACH1_CHKSUM_EN_8814B BIT(29) #define BIT_DDMACH1_DA_W_DISABLE_8814B BIT(28) #define BIT_DDMACH1_CHKSUM_STS_8814B BIT(27) @@ -4108,31 +8205,47 @@ #define BIT_SHIFT_DDMACH1_DLEN_8814B 0 #define BIT_MASK_DDMACH1_DLEN_8814B 0x3ffff -#define BIT_DDMACH1_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH1_DLEN_8814B) << BIT_SHIFT_DDMACH1_DLEN_8814B) -#define BIT_GET_DDMACH1_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8814B) & BIT_MASK_DDMACH1_DLEN_8814B) - - +#define BIT_DDMACH1_DLEN_8814B(x) \ + (((x) & BIT_MASK_DDMACH1_DLEN_8814B) << BIT_SHIFT_DDMACH1_DLEN_8814B) +#define BITS_DDMACH1_DLEN_8814B \ + (BIT_MASK_DDMACH1_DLEN_8814B << BIT_SHIFT_DDMACH1_DLEN_8814B) +#define BIT_CLEAR_DDMACH1_DLEN_8814B(x) ((x) & (~BITS_DDMACH1_DLEN_8814B)) +#define BIT_GET_DDMACH1_DLEN_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DLEN_8814B) & BIT_MASK_DDMACH1_DLEN_8814B) +#define BIT_SET_DDMACH1_DLEN_8814B(x, v) \ + (BIT_CLEAR_DDMACH1_DLEN_8814B(x) | BIT_DDMACH1_DLEN_8814B(v)) /* 2 REG_DDMA_CH2SA_8814B */ #define BIT_SHIFT_DDMACH2_SA_8814B 0 #define BIT_MASK_DDMACH2_SA_8814B 0xffffffffL -#define BIT_DDMACH2_SA_8814B(x) (((x) & BIT_MASK_DDMACH2_SA_8814B) << BIT_SHIFT_DDMACH2_SA_8814B) -#define BIT_GET_DDMACH2_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8814B) & BIT_MASK_DDMACH2_SA_8814B) - - +#define BIT_DDMACH2_SA_8814B(x) \ + (((x) & BIT_MASK_DDMACH2_SA_8814B) << BIT_SHIFT_DDMACH2_SA_8814B) +#define BITS_DDMACH2_SA_8814B \ + (BIT_MASK_DDMACH2_SA_8814B << BIT_SHIFT_DDMACH2_SA_8814B) +#define BIT_CLEAR_DDMACH2_SA_8814B(x) ((x) & (~BITS_DDMACH2_SA_8814B)) +#define BIT_GET_DDMACH2_SA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH2_SA_8814B) & BIT_MASK_DDMACH2_SA_8814B) +#define BIT_SET_DDMACH2_SA_8814B(x, v) \ + (BIT_CLEAR_DDMACH2_SA_8814B(x) | BIT_DDMACH2_SA_8814B(v)) /* 2 REG_DDMA_CH2DA_8814B */ #define BIT_SHIFT_DDMACH2_DA_8814B 0 #define BIT_MASK_DDMACH2_DA_8814B 0xffffffffL -#define BIT_DDMACH2_DA_8814B(x) (((x) & BIT_MASK_DDMACH2_DA_8814B) << BIT_SHIFT_DDMACH2_DA_8814B) -#define BIT_GET_DDMACH2_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8814B) & BIT_MASK_DDMACH2_DA_8814B) - - +#define BIT_DDMACH2_DA_8814B(x) \ + (((x) & BIT_MASK_DDMACH2_DA_8814B) << BIT_SHIFT_DDMACH2_DA_8814B) +#define BITS_DDMACH2_DA_8814B \ + (BIT_MASK_DDMACH2_DA_8814B << BIT_SHIFT_DDMACH2_DA_8814B) +#define BIT_CLEAR_DDMACH2_DA_8814B(x) ((x) & (~BITS_DDMACH2_DA_8814B)) +#define BIT_GET_DDMACH2_DA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DA_8814B) & BIT_MASK_DDMACH2_DA_8814B) +#define BIT_SET_DDMACH2_DA_8814B(x, v) \ + (BIT_CLEAR_DDMACH2_DA_8814B(x) | BIT_DDMACH2_DA_8814B(v)) /* 2 REG_DDMA_CH2CTRL_8814B */ #define BIT_DDMACH2_OWN_8814B BIT(31) +#define BIT_DDMACH2_IDMEM_ERR_8814B BIT(30) #define BIT_DDMACH2_CHKSUM_EN_8814B BIT(29) #define BIT_DDMACH2_DA_W_DISABLE_8814B BIT(28) #define BIT_DDMACH2_CHKSUM_STS_8814B BIT(27) @@ -4142,31 +8255,47 @@ #define BIT_SHIFT_DDMACH2_DLEN_8814B 0 #define BIT_MASK_DDMACH2_DLEN_8814B 0x3ffff -#define BIT_DDMACH2_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH2_DLEN_8814B) << BIT_SHIFT_DDMACH2_DLEN_8814B) -#define BIT_GET_DDMACH2_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8814B) & BIT_MASK_DDMACH2_DLEN_8814B) - - +#define BIT_DDMACH2_DLEN_8814B(x) \ + (((x) & BIT_MASK_DDMACH2_DLEN_8814B) << BIT_SHIFT_DDMACH2_DLEN_8814B) +#define BITS_DDMACH2_DLEN_8814B \ + (BIT_MASK_DDMACH2_DLEN_8814B << BIT_SHIFT_DDMACH2_DLEN_8814B) +#define BIT_CLEAR_DDMACH2_DLEN_8814B(x) ((x) & (~BITS_DDMACH2_DLEN_8814B)) +#define BIT_GET_DDMACH2_DLEN_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DLEN_8814B) & BIT_MASK_DDMACH2_DLEN_8814B) +#define BIT_SET_DDMACH2_DLEN_8814B(x, v) \ + (BIT_CLEAR_DDMACH2_DLEN_8814B(x) | BIT_DDMACH2_DLEN_8814B(v)) /* 2 REG_DDMA_CH3SA_8814B */ #define BIT_SHIFT_DDMACH3_SA_8814B 0 #define BIT_MASK_DDMACH3_SA_8814B 0xffffffffL -#define BIT_DDMACH3_SA_8814B(x) (((x) & BIT_MASK_DDMACH3_SA_8814B) << BIT_SHIFT_DDMACH3_SA_8814B) -#define BIT_GET_DDMACH3_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8814B) & BIT_MASK_DDMACH3_SA_8814B) - - +#define BIT_DDMACH3_SA_8814B(x) \ + (((x) & BIT_MASK_DDMACH3_SA_8814B) << BIT_SHIFT_DDMACH3_SA_8814B) +#define BITS_DDMACH3_SA_8814B \ + (BIT_MASK_DDMACH3_SA_8814B << BIT_SHIFT_DDMACH3_SA_8814B) +#define BIT_CLEAR_DDMACH3_SA_8814B(x) ((x) & (~BITS_DDMACH3_SA_8814B)) +#define BIT_GET_DDMACH3_SA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH3_SA_8814B) & BIT_MASK_DDMACH3_SA_8814B) +#define BIT_SET_DDMACH3_SA_8814B(x, v) \ + (BIT_CLEAR_DDMACH3_SA_8814B(x) | BIT_DDMACH3_SA_8814B(v)) /* 2 REG_DDMA_CH3DA_8814B */ #define BIT_SHIFT_DDMACH3_DA_8814B 0 #define BIT_MASK_DDMACH3_DA_8814B 0xffffffffL -#define BIT_DDMACH3_DA_8814B(x) (((x) & BIT_MASK_DDMACH3_DA_8814B) << BIT_SHIFT_DDMACH3_DA_8814B) -#define BIT_GET_DDMACH3_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8814B) & BIT_MASK_DDMACH3_DA_8814B) - - +#define BIT_DDMACH3_DA_8814B(x) \ + (((x) & BIT_MASK_DDMACH3_DA_8814B) << BIT_SHIFT_DDMACH3_DA_8814B) +#define BITS_DDMACH3_DA_8814B \ + (BIT_MASK_DDMACH3_DA_8814B << BIT_SHIFT_DDMACH3_DA_8814B) +#define BIT_CLEAR_DDMACH3_DA_8814B(x) ((x) & (~BITS_DDMACH3_DA_8814B)) +#define BIT_GET_DDMACH3_DA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DA_8814B) & BIT_MASK_DDMACH3_DA_8814B) +#define BIT_SET_DDMACH3_DA_8814B(x, v) \ + (BIT_CLEAR_DDMACH3_DA_8814B(x) | BIT_DDMACH3_DA_8814B(v)) /* 2 REG_DDMA_CH3CTRL_8814B */ #define BIT_DDMACH3_OWN_8814B BIT(31) +#define BIT_DDMACH3_IDMEM_ERR_8814B BIT(30) #define BIT_DDMACH3_CHKSUM_EN_8814B BIT(29) #define BIT_DDMACH3_DA_W_DISABLE_8814B BIT(28) #define BIT_DDMACH3_CHKSUM_STS_8814B BIT(27) @@ -4176,31 +8305,47 @@ #define BIT_SHIFT_DDMACH3_DLEN_8814B 0 #define BIT_MASK_DDMACH3_DLEN_8814B 0x3ffff -#define BIT_DDMACH3_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH3_DLEN_8814B) << BIT_SHIFT_DDMACH3_DLEN_8814B) -#define BIT_GET_DDMACH3_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8814B) & BIT_MASK_DDMACH3_DLEN_8814B) - - +#define BIT_DDMACH3_DLEN_8814B(x) \ + (((x) & BIT_MASK_DDMACH3_DLEN_8814B) << BIT_SHIFT_DDMACH3_DLEN_8814B) +#define BITS_DDMACH3_DLEN_8814B \ + (BIT_MASK_DDMACH3_DLEN_8814B << BIT_SHIFT_DDMACH3_DLEN_8814B) +#define BIT_CLEAR_DDMACH3_DLEN_8814B(x) ((x) & (~BITS_DDMACH3_DLEN_8814B)) +#define BIT_GET_DDMACH3_DLEN_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DLEN_8814B) & BIT_MASK_DDMACH3_DLEN_8814B) +#define BIT_SET_DDMACH3_DLEN_8814B(x, v) \ + (BIT_CLEAR_DDMACH3_DLEN_8814B(x) | BIT_DDMACH3_DLEN_8814B(v)) /* 2 REG_DDMA_CH4SA_8814B */ #define BIT_SHIFT_DDMACH4_SA_8814B 0 #define BIT_MASK_DDMACH4_SA_8814B 0xffffffffL -#define BIT_DDMACH4_SA_8814B(x) (((x) & BIT_MASK_DDMACH4_SA_8814B) << BIT_SHIFT_DDMACH4_SA_8814B) -#define BIT_GET_DDMACH4_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8814B) & BIT_MASK_DDMACH4_SA_8814B) - - +#define BIT_DDMACH4_SA_8814B(x) \ + (((x) & BIT_MASK_DDMACH4_SA_8814B) << BIT_SHIFT_DDMACH4_SA_8814B) +#define BITS_DDMACH4_SA_8814B \ + (BIT_MASK_DDMACH4_SA_8814B << BIT_SHIFT_DDMACH4_SA_8814B) +#define BIT_CLEAR_DDMACH4_SA_8814B(x) ((x) & (~BITS_DDMACH4_SA_8814B)) +#define BIT_GET_DDMACH4_SA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH4_SA_8814B) & BIT_MASK_DDMACH4_SA_8814B) +#define BIT_SET_DDMACH4_SA_8814B(x, v) \ + (BIT_CLEAR_DDMACH4_SA_8814B(x) | BIT_DDMACH4_SA_8814B(v)) /* 2 REG_DDMA_CH4DA_8814B */ #define BIT_SHIFT_DDMACH4_DA_8814B 0 #define BIT_MASK_DDMACH4_DA_8814B 0xffffffffL -#define BIT_DDMACH4_DA_8814B(x) (((x) & BIT_MASK_DDMACH4_DA_8814B) << BIT_SHIFT_DDMACH4_DA_8814B) -#define BIT_GET_DDMACH4_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8814B) & BIT_MASK_DDMACH4_DA_8814B) - - +#define BIT_DDMACH4_DA_8814B(x) \ + (((x) & BIT_MASK_DDMACH4_DA_8814B) << BIT_SHIFT_DDMACH4_DA_8814B) +#define BITS_DDMACH4_DA_8814B \ + (BIT_MASK_DDMACH4_DA_8814B << BIT_SHIFT_DDMACH4_DA_8814B) +#define BIT_CLEAR_DDMACH4_DA_8814B(x) ((x) & (~BITS_DDMACH4_DA_8814B)) +#define BIT_GET_DDMACH4_DA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DA_8814B) & BIT_MASK_DDMACH4_DA_8814B) +#define BIT_SET_DDMACH4_DA_8814B(x, v) \ + (BIT_CLEAR_DDMACH4_DA_8814B(x) | BIT_DDMACH4_DA_8814B(v)) /* 2 REG_DDMA_CH4CTRL_8814B */ #define BIT_DDMACH4_OWN_8814B BIT(31) +#define BIT_DDMACH4_IDMEM_ERR_8814B BIT(30) #define BIT_DDMACH4_CHKSUM_EN_8814B BIT(29) #define BIT_DDMACH4_DA_W_DISABLE_8814B BIT(28) #define BIT_DDMACH4_CHKSUM_STS_8814B BIT(27) @@ -4210,31 +8355,47 @@ #define BIT_SHIFT_DDMACH4_DLEN_8814B 0 #define BIT_MASK_DDMACH4_DLEN_8814B 0x3ffff -#define BIT_DDMACH4_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH4_DLEN_8814B) << BIT_SHIFT_DDMACH4_DLEN_8814B) -#define BIT_GET_DDMACH4_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8814B) & BIT_MASK_DDMACH4_DLEN_8814B) - - +#define BIT_DDMACH4_DLEN_8814B(x) \ + (((x) & BIT_MASK_DDMACH4_DLEN_8814B) << BIT_SHIFT_DDMACH4_DLEN_8814B) +#define BITS_DDMACH4_DLEN_8814B \ + (BIT_MASK_DDMACH4_DLEN_8814B << BIT_SHIFT_DDMACH4_DLEN_8814B) +#define BIT_CLEAR_DDMACH4_DLEN_8814B(x) ((x) & (~BITS_DDMACH4_DLEN_8814B)) +#define BIT_GET_DDMACH4_DLEN_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DLEN_8814B) & BIT_MASK_DDMACH4_DLEN_8814B) +#define BIT_SET_DDMACH4_DLEN_8814B(x, v) \ + (BIT_CLEAR_DDMACH4_DLEN_8814B(x) | BIT_DDMACH4_DLEN_8814B(v)) /* 2 REG_DDMA_CH5SA_8814B */ #define BIT_SHIFT_DDMACH5_SA_8814B 0 #define BIT_MASK_DDMACH5_SA_8814B 0xffffffffL -#define BIT_DDMACH5_SA_8814B(x) (((x) & BIT_MASK_DDMACH5_SA_8814B) << BIT_SHIFT_DDMACH5_SA_8814B) -#define BIT_GET_DDMACH5_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8814B) & BIT_MASK_DDMACH5_SA_8814B) - - +#define BIT_DDMACH5_SA_8814B(x) \ + (((x) & BIT_MASK_DDMACH5_SA_8814B) << BIT_SHIFT_DDMACH5_SA_8814B) +#define BITS_DDMACH5_SA_8814B \ + (BIT_MASK_DDMACH5_SA_8814B << BIT_SHIFT_DDMACH5_SA_8814B) +#define BIT_CLEAR_DDMACH5_SA_8814B(x) ((x) & (~BITS_DDMACH5_SA_8814B)) +#define BIT_GET_DDMACH5_SA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH5_SA_8814B) & BIT_MASK_DDMACH5_SA_8814B) +#define BIT_SET_DDMACH5_SA_8814B(x, v) \ + (BIT_CLEAR_DDMACH5_SA_8814B(x) | BIT_DDMACH5_SA_8814B(v)) /* 2 REG_DDMA_CH5DA_8814B */ #define BIT_SHIFT_DDMACH5_DA_8814B 0 #define BIT_MASK_DDMACH5_DA_8814B 0xffffffffL -#define BIT_DDMACH5_DA_8814B(x) (((x) & BIT_MASK_DDMACH5_DA_8814B) << BIT_SHIFT_DDMACH5_DA_8814B) -#define BIT_GET_DDMACH5_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8814B) & BIT_MASK_DDMACH5_DA_8814B) - - +#define BIT_DDMACH5_DA_8814B(x) \ + (((x) & BIT_MASK_DDMACH5_DA_8814B) << BIT_SHIFT_DDMACH5_DA_8814B) +#define BITS_DDMACH5_DA_8814B \ + (BIT_MASK_DDMACH5_DA_8814B << BIT_SHIFT_DDMACH5_DA_8814B) +#define BIT_CLEAR_DDMACH5_DA_8814B(x) ((x) & (~BITS_DDMACH5_DA_8814B)) +#define BIT_GET_DDMACH5_DA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DA_8814B) & BIT_MASK_DDMACH5_DA_8814B) +#define BIT_SET_DDMACH5_DA_8814B(x, v) \ + (BIT_CLEAR_DDMACH5_DA_8814B(x) | BIT_DDMACH5_DA_8814B(v)) /* 2 REG_DDMA_CH5CTRL_8814B */ #define BIT_DDMACH5_OWN_8814B BIT(31) +#define BIT_DDMACH5_IDMEM_ERR_8814B BIT(30) #define BIT_DDMACH5_CHKSUM_EN_8814B BIT(29) #define BIT_DDMACH5_DA_W_DISABLE_8814B BIT(28) #define BIT_DDMACH5_CHKSUM_STS_8814B BIT(27) @@ -4244,10 +8405,15 @@ #define BIT_SHIFT_DDMACH5_DLEN_8814B 0 #define BIT_MASK_DDMACH5_DLEN_8814B 0x3ffff -#define BIT_DDMACH5_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH5_DLEN_8814B) << BIT_SHIFT_DDMACH5_DLEN_8814B) -#define BIT_GET_DDMACH5_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8814B) & BIT_MASK_DDMACH5_DLEN_8814B) - - +#define BIT_DDMACH5_DLEN_8814B(x) \ + (((x) & BIT_MASK_DDMACH5_DLEN_8814B) << BIT_SHIFT_DDMACH5_DLEN_8814B) +#define BITS_DDMACH5_DLEN_8814B \ + (BIT_MASK_DDMACH5_DLEN_8814B << BIT_SHIFT_DDMACH5_DLEN_8814B) +#define BIT_CLEAR_DDMACH5_DLEN_8814B(x) ((x) & (~BITS_DDMACH5_DLEN_8814B)) +#define BIT_GET_DDMACH5_DLEN_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DLEN_8814B) & BIT_MASK_DDMACH5_DLEN_8814B) +#define BIT_SET_DDMACH5_DLEN_8814B(x, v) \ + (BIT_CLEAR_DDMACH5_DLEN_8814B(x) | BIT_DDMACH5_DLEN_8814B(v)) /* 2 REG_DDMA_INT_MSK_8814B */ #define BIT_DDMACH5_MSK_8814B BIT(5) @@ -4269,10 +8435,15 @@ #define BIT_SHIFT_IDDMA0_CHKSUM_8814B 0 #define BIT_MASK_IDDMA0_CHKSUM_8814B 0xffff -#define BIT_IDDMA0_CHKSUM_8814B(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8814B) << BIT_SHIFT_IDDMA0_CHKSUM_8814B) -#define BIT_GET_IDDMA0_CHKSUM_8814B(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8814B) & BIT_MASK_IDDMA0_CHKSUM_8814B) - - +#define BIT_IDDMA0_CHKSUM_8814B(x) \ + (((x) & BIT_MASK_IDDMA0_CHKSUM_8814B) << BIT_SHIFT_IDDMA0_CHKSUM_8814B) +#define BITS_IDDMA0_CHKSUM_8814B \ + (BIT_MASK_IDDMA0_CHKSUM_8814B << BIT_SHIFT_IDDMA0_CHKSUM_8814B) +#define BIT_CLEAR_IDDMA0_CHKSUM_8814B(x) ((x) & (~BITS_IDDMA0_CHKSUM_8814B)) +#define BIT_GET_IDDMA0_CHKSUM_8814B(x) \ + (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8814B) & BIT_MASK_IDDMA0_CHKSUM_8814B) +#define BIT_SET_IDDMA0_CHKSUM_8814B(x, v) \ + (BIT_CLEAR_IDDMA0_CHKSUM_8814B(x) | BIT_IDDMA0_CHKSUM_8814B(v)) /* 2 REG_DDMA_MONITOR_8814B */ #define BIT_IDDMA0_PERMU_UNDERFLOW_8814B BIT(14) @@ -4285,6 +8456,970 @@ #define BIT_CH1_ERR_8814B BIT(1) #define BIT_CH0_ERR_8814B BIT(0) +/* 2 REG_DMA_RQPN_INFO_0_8814B */ + +#define BIT_SHIFT_CH0_AVAL_PG_8814B 16 +#define BIT_MASK_CH0_AVAL_PG_8814B 0xfff +#define BIT_CH0_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH0_AVAL_PG_8814B) << BIT_SHIFT_CH0_AVAL_PG_8814B) +#define BITS_CH0_AVAL_PG_8814B \ + (BIT_MASK_CH0_AVAL_PG_8814B << BIT_SHIFT_CH0_AVAL_PG_8814B) +#define BIT_CLEAR_CH0_AVAL_PG_8814B(x) ((x) & (~BITS_CH0_AVAL_PG_8814B)) +#define BIT_GET_CH0_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH0_AVAL_PG_8814B) & BIT_MASK_CH0_AVAL_PG_8814B) +#define BIT_SET_CH0_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH0_AVAL_PG_8814B(x) | BIT_CH0_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH0_RSVD_PG_8814B 0 +#define BIT_MASK_CH0_RSVD_PG_8814B 0xfff +#define BIT_CH0_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH0_RSVD_PG_8814B) << BIT_SHIFT_CH0_RSVD_PG_8814B) +#define BITS_CH0_RSVD_PG_8814B \ + (BIT_MASK_CH0_RSVD_PG_8814B << BIT_SHIFT_CH0_RSVD_PG_8814B) +#define BIT_CLEAR_CH0_RSVD_PG_8814B(x) ((x) & (~BITS_CH0_RSVD_PG_8814B)) +#define BIT_GET_CH0_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH0_RSVD_PG_8814B) & BIT_MASK_CH0_RSVD_PG_8814B) +#define BIT_SET_CH0_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH0_RSVD_PG_8814B(x) | BIT_CH0_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_1_8814B */ + +#define BIT_SHIFT_CH1_AVAL_PG_8814B 16 +#define BIT_MASK_CH1_AVAL_PG_8814B 0xfff +#define BIT_CH1_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH1_AVAL_PG_8814B) << BIT_SHIFT_CH1_AVAL_PG_8814B) +#define BITS_CH1_AVAL_PG_8814B \ + (BIT_MASK_CH1_AVAL_PG_8814B << BIT_SHIFT_CH1_AVAL_PG_8814B) +#define BIT_CLEAR_CH1_AVAL_PG_8814B(x) ((x) & (~BITS_CH1_AVAL_PG_8814B)) +#define BIT_GET_CH1_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH1_AVAL_PG_8814B) & BIT_MASK_CH1_AVAL_PG_8814B) +#define BIT_SET_CH1_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH1_AVAL_PG_8814B(x) | BIT_CH1_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH1_RSVD_PG_8814B 0 +#define BIT_MASK_CH1_RSVD_PG_8814B 0xfff +#define BIT_CH1_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH1_RSVD_PG_8814B) << BIT_SHIFT_CH1_RSVD_PG_8814B) +#define BITS_CH1_RSVD_PG_8814B \ + (BIT_MASK_CH1_RSVD_PG_8814B << BIT_SHIFT_CH1_RSVD_PG_8814B) +#define BIT_CLEAR_CH1_RSVD_PG_8814B(x) ((x) & (~BITS_CH1_RSVD_PG_8814B)) +#define BIT_GET_CH1_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH1_RSVD_PG_8814B) & BIT_MASK_CH1_RSVD_PG_8814B) +#define BIT_SET_CH1_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH1_RSVD_PG_8814B(x) | BIT_CH1_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_2_8814B */ + +#define BIT_SHIFT_CH2_AVAL_PG_8814B 16 +#define BIT_MASK_CH2_AVAL_PG_8814B 0xfff +#define BIT_CH2_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH2_AVAL_PG_8814B) << BIT_SHIFT_CH2_AVAL_PG_8814B) +#define BITS_CH2_AVAL_PG_8814B \ + (BIT_MASK_CH2_AVAL_PG_8814B << BIT_SHIFT_CH2_AVAL_PG_8814B) +#define BIT_CLEAR_CH2_AVAL_PG_8814B(x) ((x) & (~BITS_CH2_AVAL_PG_8814B)) +#define BIT_GET_CH2_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH2_AVAL_PG_8814B) & BIT_MASK_CH2_AVAL_PG_8814B) +#define BIT_SET_CH2_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH2_AVAL_PG_8814B(x) | BIT_CH2_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH2_RSVD_PG_8814B 0 +#define BIT_MASK_CH2_RSVD_PG_8814B 0xfff +#define BIT_CH2_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH2_RSVD_PG_8814B) << BIT_SHIFT_CH2_RSVD_PG_8814B) +#define BITS_CH2_RSVD_PG_8814B \ + (BIT_MASK_CH2_RSVD_PG_8814B << BIT_SHIFT_CH2_RSVD_PG_8814B) +#define BIT_CLEAR_CH2_RSVD_PG_8814B(x) ((x) & (~BITS_CH2_RSVD_PG_8814B)) +#define BIT_GET_CH2_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH2_RSVD_PG_8814B) & BIT_MASK_CH2_RSVD_PG_8814B) +#define BIT_SET_CH2_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH2_RSVD_PG_8814B(x) | BIT_CH2_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_3_8814B */ + +#define BIT_SHIFT_CH3_AVAL_PG_8814B 16 +#define BIT_MASK_CH3_AVAL_PG_8814B 0xfff +#define BIT_CH3_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH3_AVAL_PG_8814B) << BIT_SHIFT_CH3_AVAL_PG_8814B) +#define BITS_CH3_AVAL_PG_8814B \ + (BIT_MASK_CH3_AVAL_PG_8814B << BIT_SHIFT_CH3_AVAL_PG_8814B) +#define BIT_CLEAR_CH3_AVAL_PG_8814B(x) ((x) & (~BITS_CH3_AVAL_PG_8814B)) +#define BIT_GET_CH3_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH3_AVAL_PG_8814B) & BIT_MASK_CH3_AVAL_PG_8814B) +#define BIT_SET_CH3_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH3_AVAL_PG_8814B(x) | BIT_CH3_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH3_RSVD_PG_8814B 0 +#define BIT_MASK_CH3_RSVD_PG_8814B 0xfff +#define BIT_CH3_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH3_RSVD_PG_8814B) << BIT_SHIFT_CH3_RSVD_PG_8814B) +#define BITS_CH3_RSVD_PG_8814B \ + (BIT_MASK_CH3_RSVD_PG_8814B << BIT_SHIFT_CH3_RSVD_PG_8814B) +#define BIT_CLEAR_CH3_RSVD_PG_8814B(x) ((x) & (~BITS_CH3_RSVD_PG_8814B)) +#define BIT_GET_CH3_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH3_RSVD_PG_8814B) & BIT_MASK_CH3_RSVD_PG_8814B) +#define BIT_SET_CH3_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH3_RSVD_PG_8814B(x) | BIT_CH3_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_4_8814B */ + +#define BIT_SHIFT_CH4_AVAL_PG_8814B 16 +#define BIT_MASK_CH4_AVAL_PG_8814B 0xfff +#define BIT_CH4_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH4_AVAL_PG_8814B) << BIT_SHIFT_CH4_AVAL_PG_8814B) +#define BITS_CH4_AVAL_PG_8814B \ + (BIT_MASK_CH4_AVAL_PG_8814B << BIT_SHIFT_CH4_AVAL_PG_8814B) +#define BIT_CLEAR_CH4_AVAL_PG_8814B(x) ((x) & (~BITS_CH4_AVAL_PG_8814B)) +#define BIT_GET_CH4_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH4_AVAL_PG_8814B) & BIT_MASK_CH4_AVAL_PG_8814B) +#define BIT_SET_CH4_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH4_AVAL_PG_8814B(x) | BIT_CH4_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH4_RSVD_PG_8814B 0 +#define BIT_MASK_CH4_RSVD_PG_8814B 0xfff +#define BIT_CH4_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH4_RSVD_PG_8814B) << BIT_SHIFT_CH4_RSVD_PG_8814B) +#define BITS_CH4_RSVD_PG_8814B \ + (BIT_MASK_CH4_RSVD_PG_8814B << BIT_SHIFT_CH4_RSVD_PG_8814B) +#define BIT_CLEAR_CH4_RSVD_PG_8814B(x) ((x) & (~BITS_CH4_RSVD_PG_8814B)) +#define BIT_GET_CH4_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH4_RSVD_PG_8814B) & BIT_MASK_CH4_RSVD_PG_8814B) +#define BIT_SET_CH4_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH4_RSVD_PG_8814B(x) | BIT_CH4_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_5_8814B */ + +#define BIT_SHIFT_CH5_AVAL_PG_8814B 16 +#define BIT_MASK_CH5_AVAL_PG_8814B 0xfff +#define BIT_CH5_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH5_AVAL_PG_8814B) << BIT_SHIFT_CH5_AVAL_PG_8814B) +#define BITS_CH5_AVAL_PG_8814B \ + (BIT_MASK_CH5_AVAL_PG_8814B << BIT_SHIFT_CH5_AVAL_PG_8814B) +#define BIT_CLEAR_CH5_AVAL_PG_8814B(x) ((x) & (~BITS_CH5_AVAL_PG_8814B)) +#define BIT_GET_CH5_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH5_AVAL_PG_8814B) & BIT_MASK_CH5_AVAL_PG_8814B) +#define BIT_SET_CH5_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH5_AVAL_PG_8814B(x) | BIT_CH5_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH5_RSVD_PG_8814B 0 +#define BIT_MASK_CH5_RSVD_PG_8814B 0xfff +#define BIT_CH5_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH5_RSVD_PG_8814B) << BIT_SHIFT_CH5_RSVD_PG_8814B) +#define BITS_CH5_RSVD_PG_8814B \ + (BIT_MASK_CH5_RSVD_PG_8814B << BIT_SHIFT_CH5_RSVD_PG_8814B) +#define BIT_CLEAR_CH5_RSVD_PG_8814B(x) ((x) & (~BITS_CH5_RSVD_PG_8814B)) +#define BIT_GET_CH5_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH5_RSVD_PG_8814B) & BIT_MASK_CH5_RSVD_PG_8814B) +#define BIT_SET_CH5_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH5_RSVD_PG_8814B(x) | BIT_CH5_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_6_8814B */ + +#define BIT_SHIFT_CH6_AVAL_PG_8814B 16 +#define BIT_MASK_CH6_AVAL_PG_8814B 0xfff +#define BIT_CH6_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH6_AVAL_PG_8814B) << BIT_SHIFT_CH6_AVAL_PG_8814B) +#define BITS_CH6_AVAL_PG_8814B \ + (BIT_MASK_CH6_AVAL_PG_8814B << BIT_SHIFT_CH6_AVAL_PG_8814B) +#define BIT_CLEAR_CH6_AVAL_PG_8814B(x) ((x) & (~BITS_CH6_AVAL_PG_8814B)) +#define BIT_GET_CH6_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH6_AVAL_PG_8814B) & BIT_MASK_CH6_AVAL_PG_8814B) +#define BIT_SET_CH6_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH6_AVAL_PG_8814B(x) | BIT_CH6_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH6_RSVD_PG_8814B 0 +#define BIT_MASK_CH6_RSVD_PG_8814B 0xfff +#define BIT_CH6_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH6_RSVD_PG_8814B) << BIT_SHIFT_CH6_RSVD_PG_8814B) +#define BITS_CH6_RSVD_PG_8814B \ + (BIT_MASK_CH6_RSVD_PG_8814B << BIT_SHIFT_CH6_RSVD_PG_8814B) +#define BIT_CLEAR_CH6_RSVD_PG_8814B(x) ((x) & (~BITS_CH6_RSVD_PG_8814B)) +#define BIT_GET_CH6_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH6_RSVD_PG_8814B) & BIT_MASK_CH6_RSVD_PG_8814B) +#define BIT_SET_CH6_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH6_RSVD_PG_8814B(x) | BIT_CH6_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_7_8814B */ + +#define BIT_SHIFT_CH7_AVAL_PG_8814B 16 +#define BIT_MASK_CH7_AVAL_PG_8814B 0xfff +#define BIT_CH7_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH7_AVAL_PG_8814B) << BIT_SHIFT_CH7_AVAL_PG_8814B) +#define BITS_CH7_AVAL_PG_8814B \ + (BIT_MASK_CH7_AVAL_PG_8814B << BIT_SHIFT_CH7_AVAL_PG_8814B) +#define BIT_CLEAR_CH7_AVAL_PG_8814B(x) ((x) & (~BITS_CH7_AVAL_PG_8814B)) +#define BIT_GET_CH7_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH7_AVAL_PG_8814B) & BIT_MASK_CH7_AVAL_PG_8814B) +#define BIT_SET_CH7_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH7_AVAL_PG_8814B(x) | BIT_CH7_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH7_RSVD_PG_8814B 0 +#define BIT_MASK_CH7_RSVD_PG_8814B 0xfff +#define BIT_CH7_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH7_RSVD_PG_8814B) << BIT_SHIFT_CH7_RSVD_PG_8814B) +#define BITS_CH7_RSVD_PG_8814B \ + (BIT_MASK_CH7_RSVD_PG_8814B << BIT_SHIFT_CH7_RSVD_PG_8814B) +#define BIT_CLEAR_CH7_RSVD_PG_8814B(x) ((x) & (~BITS_CH7_RSVD_PG_8814B)) +#define BIT_GET_CH7_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH7_RSVD_PG_8814B) & BIT_MASK_CH7_RSVD_PG_8814B) +#define BIT_SET_CH7_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH7_RSVD_PG_8814B(x) | BIT_CH7_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_8_8814B */ + +#define BIT_SHIFT_CH8_AVAL_PG_8814B 16 +#define BIT_MASK_CH8_AVAL_PG_8814B 0xfff +#define BIT_CH8_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH8_AVAL_PG_8814B) << BIT_SHIFT_CH8_AVAL_PG_8814B) +#define BITS_CH8_AVAL_PG_8814B \ + (BIT_MASK_CH8_AVAL_PG_8814B << BIT_SHIFT_CH8_AVAL_PG_8814B) +#define BIT_CLEAR_CH8_AVAL_PG_8814B(x) ((x) & (~BITS_CH8_AVAL_PG_8814B)) +#define BIT_GET_CH8_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH8_AVAL_PG_8814B) & BIT_MASK_CH8_AVAL_PG_8814B) +#define BIT_SET_CH8_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH8_AVAL_PG_8814B(x) | BIT_CH8_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH8_RSVD_PG_8814B 0 +#define BIT_MASK_CH8_RSVD_PG_8814B 0xfff +#define BIT_CH8_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH8_RSVD_PG_8814B) << BIT_SHIFT_CH8_RSVD_PG_8814B) +#define BITS_CH8_RSVD_PG_8814B \ + (BIT_MASK_CH8_RSVD_PG_8814B << BIT_SHIFT_CH8_RSVD_PG_8814B) +#define BIT_CLEAR_CH8_RSVD_PG_8814B(x) ((x) & (~BITS_CH8_RSVD_PG_8814B)) +#define BIT_GET_CH8_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH8_RSVD_PG_8814B) & BIT_MASK_CH8_RSVD_PG_8814B) +#define BIT_SET_CH8_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH8_RSVD_PG_8814B(x) | BIT_CH8_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_9_8814B */ + +#define BIT_SHIFT_CH9_AVAL_PG_8814B 16 +#define BIT_MASK_CH9_AVAL_PG_8814B 0xfff +#define BIT_CH9_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH9_AVAL_PG_8814B) << BIT_SHIFT_CH9_AVAL_PG_8814B) +#define BITS_CH9_AVAL_PG_8814B \ + (BIT_MASK_CH9_AVAL_PG_8814B << BIT_SHIFT_CH9_AVAL_PG_8814B) +#define BIT_CLEAR_CH9_AVAL_PG_8814B(x) ((x) & (~BITS_CH9_AVAL_PG_8814B)) +#define BIT_GET_CH9_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH9_AVAL_PG_8814B) & BIT_MASK_CH9_AVAL_PG_8814B) +#define BIT_SET_CH9_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH9_AVAL_PG_8814B(x) | BIT_CH9_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH9_RSVD_PG_8814B 0 +#define BIT_MASK_CH9_RSVD_PG_8814B 0xfff +#define BIT_CH9_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH9_RSVD_PG_8814B) << BIT_SHIFT_CH9_RSVD_PG_8814B) +#define BITS_CH9_RSVD_PG_8814B \ + (BIT_MASK_CH9_RSVD_PG_8814B << BIT_SHIFT_CH9_RSVD_PG_8814B) +#define BIT_CLEAR_CH9_RSVD_PG_8814B(x) ((x) & (~BITS_CH9_RSVD_PG_8814B)) +#define BIT_GET_CH9_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH9_RSVD_PG_8814B) & BIT_MASK_CH9_RSVD_PG_8814B) +#define BIT_SET_CH9_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH9_RSVD_PG_8814B(x) | BIT_CH9_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_10_8814B */ + +#define BIT_SHIFT_CH10_AVAL_PG_8814B 16 +#define BIT_MASK_CH10_AVAL_PG_8814B 0xfff +#define BIT_CH10_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH10_AVAL_PG_8814B) << BIT_SHIFT_CH10_AVAL_PG_8814B) +#define BITS_CH10_AVAL_PG_8814B \ + (BIT_MASK_CH10_AVAL_PG_8814B << BIT_SHIFT_CH10_AVAL_PG_8814B) +#define BIT_CLEAR_CH10_AVAL_PG_8814B(x) ((x) & (~BITS_CH10_AVAL_PG_8814B)) +#define BIT_GET_CH10_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH10_AVAL_PG_8814B) & BIT_MASK_CH10_AVAL_PG_8814B) +#define BIT_SET_CH10_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH10_AVAL_PG_8814B(x) | BIT_CH10_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH10_RSVD_PG_8814B 0 +#define BIT_MASK_CH10_RSVD_PG_8814B 0xfff +#define BIT_CH10_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH10_RSVD_PG_8814B) << BIT_SHIFT_CH10_RSVD_PG_8814B) +#define BITS_CH10_RSVD_PG_8814B \ + (BIT_MASK_CH10_RSVD_PG_8814B << BIT_SHIFT_CH10_RSVD_PG_8814B) +#define BIT_CLEAR_CH10_RSVD_PG_8814B(x) ((x) & (~BITS_CH10_RSVD_PG_8814B)) +#define BIT_GET_CH10_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH10_RSVD_PG_8814B) & BIT_MASK_CH10_RSVD_PG_8814B) +#define BIT_SET_CH10_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH10_RSVD_PG_8814B(x) | BIT_CH10_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_11_8814B */ + +#define BIT_SHIFT_CH11_AVAL_PG_8814B 16 +#define BIT_MASK_CH11_AVAL_PG_8814B 0xfff +#define BIT_CH11_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH11_AVAL_PG_8814B) << BIT_SHIFT_CH11_AVAL_PG_8814B) +#define BITS_CH11_AVAL_PG_8814B \ + (BIT_MASK_CH11_AVAL_PG_8814B << BIT_SHIFT_CH11_AVAL_PG_8814B) +#define BIT_CLEAR_CH11_AVAL_PG_8814B(x) ((x) & (~BITS_CH11_AVAL_PG_8814B)) +#define BIT_GET_CH11_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH11_AVAL_PG_8814B) & BIT_MASK_CH11_AVAL_PG_8814B) +#define BIT_SET_CH11_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH11_AVAL_PG_8814B(x) | BIT_CH11_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH11_RSVD_PG_8814B 0 +#define BIT_MASK_CH11_RSVD_PG_8814B 0xfff +#define BIT_CH11_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH11_RSVD_PG_8814B) << BIT_SHIFT_CH11_RSVD_PG_8814B) +#define BITS_CH11_RSVD_PG_8814B \ + (BIT_MASK_CH11_RSVD_PG_8814B << BIT_SHIFT_CH11_RSVD_PG_8814B) +#define BIT_CLEAR_CH11_RSVD_PG_8814B(x) ((x) & (~BITS_CH11_RSVD_PG_8814B)) +#define BIT_GET_CH11_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH11_RSVD_PG_8814B) & BIT_MASK_CH11_RSVD_PG_8814B) +#define BIT_SET_CH11_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH11_RSVD_PG_8814B(x) | BIT_CH11_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_12_8814B */ + +#define BIT_SHIFT_CH12_AVAL_PG_8814B 16 +#define BIT_MASK_CH12_AVAL_PG_8814B 0xfff +#define BIT_CH12_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH12_AVAL_PG_8814B) << BIT_SHIFT_CH12_AVAL_PG_8814B) +#define BITS_CH12_AVAL_PG_8814B \ + (BIT_MASK_CH12_AVAL_PG_8814B << BIT_SHIFT_CH12_AVAL_PG_8814B) +#define BIT_CLEAR_CH12_AVAL_PG_8814B(x) ((x) & (~BITS_CH12_AVAL_PG_8814B)) +#define BIT_GET_CH12_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH12_AVAL_PG_8814B) & BIT_MASK_CH12_AVAL_PG_8814B) +#define BIT_SET_CH12_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH12_AVAL_PG_8814B(x) | BIT_CH12_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH12_RSVD_PG_8814B 0 +#define BIT_MASK_CH12_RSVD_PG_8814B 0xfff +#define BIT_CH12_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH12_RSVD_PG_8814B) << BIT_SHIFT_CH12_RSVD_PG_8814B) +#define BITS_CH12_RSVD_PG_8814B \ + (BIT_MASK_CH12_RSVD_PG_8814B << BIT_SHIFT_CH12_RSVD_PG_8814B) +#define BIT_CLEAR_CH12_RSVD_PG_8814B(x) ((x) & (~BITS_CH12_RSVD_PG_8814B)) +#define BIT_GET_CH12_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH12_RSVD_PG_8814B) & BIT_MASK_CH12_RSVD_PG_8814B) +#define BIT_SET_CH12_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH12_RSVD_PG_8814B(x) | BIT_CH12_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_13_8814B */ + +#define BIT_SHIFT_CH13_AVAL_PG_8814B 16 +#define BIT_MASK_CH13_AVAL_PG_8814B 0xfff +#define BIT_CH13_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH13_AVAL_PG_8814B) << BIT_SHIFT_CH13_AVAL_PG_8814B) +#define BITS_CH13_AVAL_PG_8814B \ + (BIT_MASK_CH13_AVAL_PG_8814B << BIT_SHIFT_CH13_AVAL_PG_8814B) +#define BIT_CLEAR_CH13_AVAL_PG_8814B(x) ((x) & (~BITS_CH13_AVAL_PG_8814B)) +#define BIT_GET_CH13_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH13_AVAL_PG_8814B) & BIT_MASK_CH13_AVAL_PG_8814B) +#define BIT_SET_CH13_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH13_AVAL_PG_8814B(x) | BIT_CH13_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH13_RSVD_PG_8814B 0 +#define BIT_MASK_CH13_RSVD_PG_8814B 0xfff +#define BIT_CH13_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH13_RSVD_PG_8814B) << BIT_SHIFT_CH13_RSVD_PG_8814B) +#define BITS_CH13_RSVD_PG_8814B \ + (BIT_MASK_CH13_RSVD_PG_8814B << BIT_SHIFT_CH13_RSVD_PG_8814B) +#define BIT_CLEAR_CH13_RSVD_PG_8814B(x) ((x) & (~BITS_CH13_RSVD_PG_8814B)) +#define BIT_GET_CH13_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH13_RSVD_PG_8814B) & BIT_MASK_CH13_RSVD_PG_8814B) +#define BIT_SET_CH13_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH13_RSVD_PG_8814B(x) | BIT_CH13_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_14_8814B */ + +#define BIT_SHIFT_CH14_AVAL_PG_8814B 16 +#define BIT_MASK_CH14_AVAL_PG_8814B 0xfff +#define BIT_CH14_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH14_AVAL_PG_8814B) << BIT_SHIFT_CH14_AVAL_PG_8814B) +#define BITS_CH14_AVAL_PG_8814B \ + (BIT_MASK_CH14_AVAL_PG_8814B << BIT_SHIFT_CH14_AVAL_PG_8814B) +#define BIT_CLEAR_CH14_AVAL_PG_8814B(x) ((x) & (~BITS_CH14_AVAL_PG_8814B)) +#define BIT_GET_CH14_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH14_AVAL_PG_8814B) & BIT_MASK_CH14_AVAL_PG_8814B) +#define BIT_SET_CH14_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH14_AVAL_PG_8814B(x) | BIT_CH14_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH14_RSVD_PG_8814B 0 +#define BIT_MASK_CH14_RSVD_PG_8814B 0xfff +#define BIT_CH14_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH14_RSVD_PG_8814B) << BIT_SHIFT_CH14_RSVD_PG_8814B) +#define BITS_CH14_RSVD_PG_8814B \ + (BIT_MASK_CH14_RSVD_PG_8814B << BIT_SHIFT_CH14_RSVD_PG_8814B) +#define BIT_CLEAR_CH14_RSVD_PG_8814B(x) ((x) & (~BITS_CH14_RSVD_PG_8814B)) +#define BIT_GET_CH14_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH14_RSVD_PG_8814B) & BIT_MASK_CH14_RSVD_PG_8814B) +#define BIT_SET_CH14_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH14_RSVD_PG_8814B(x) | BIT_CH14_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_15_8814B */ + +#define BIT_SHIFT_CH15_AVAL_PG_8814B 16 +#define BIT_MASK_CH15_AVAL_PG_8814B 0xfff +#define BIT_CH15_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH15_AVAL_PG_8814B) << BIT_SHIFT_CH15_AVAL_PG_8814B) +#define BITS_CH15_AVAL_PG_8814B \ + (BIT_MASK_CH15_AVAL_PG_8814B << BIT_SHIFT_CH15_AVAL_PG_8814B) +#define BIT_CLEAR_CH15_AVAL_PG_8814B(x) ((x) & (~BITS_CH15_AVAL_PG_8814B)) +#define BIT_GET_CH15_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH15_AVAL_PG_8814B) & BIT_MASK_CH15_AVAL_PG_8814B) +#define BIT_SET_CH15_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH15_AVAL_PG_8814B(x) | BIT_CH15_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH15_RSVD_PG_8814B 0 +#define BIT_MASK_CH15_RSVD_PG_8814B 0xfff +#define BIT_CH15_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH15_RSVD_PG_8814B) << BIT_SHIFT_CH15_RSVD_PG_8814B) +#define BITS_CH15_RSVD_PG_8814B \ + (BIT_MASK_CH15_RSVD_PG_8814B << BIT_SHIFT_CH15_RSVD_PG_8814B) +#define BIT_CLEAR_CH15_RSVD_PG_8814B(x) ((x) & (~BITS_CH15_RSVD_PG_8814B)) +#define BIT_GET_CH15_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH15_RSVD_PG_8814B) & BIT_MASK_CH15_RSVD_PG_8814B) +#define BIT_SET_CH15_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH15_RSVD_PG_8814B(x) | BIT_CH15_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_16_8814B */ + +#define BIT_SHIFT_CH16_AVAL_PG_8814B 16 +#define BIT_MASK_CH16_AVAL_PG_8814B 0xfff +#define BIT_CH16_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH16_AVAL_PG_8814B) << BIT_SHIFT_CH16_AVAL_PG_8814B) +#define BITS_CH16_AVAL_PG_8814B \ + (BIT_MASK_CH16_AVAL_PG_8814B << BIT_SHIFT_CH16_AVAL_PG_8814B) +#define BIT_CLEAR_CH16_AVAL_PG_8814B(x) ((x) & (~BITS_CH16_AVAL_PG_8814B)) +#define BIT_GET_CH16_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH16_AVAL_PG_8814B) & BIT_MASK_CH16_AVAL_PG_8814B) +#define BIT_SET_CH16_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH16_AVAL_PG_8814B(x) | BIT_CH16_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH16_RSVD_PG_8814B 0 +#define BIT_MASK_CH16_RSVD_PG_8814B 0xfff +#define BIT_CH16_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH16_RSVD_PG_8814B) << BIT_SHIFT_CH16_RSVD_PG_8814B) +#define BITS_CH16_RSVD_PG_8814B \ + (BIT_MASK_CH16_RSVD_PG_8814B << BIT_SHIFT_CH16_RSVD_PG_8814B) +#define BIT_CLEAR_CH16_RSVD_PG_8814B(x) ((x) & (~BITS_CH16_RSVD_PG_8814B)) +#define BIT_GET_CH16_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH16_RSVD_PG_8814B) & BIT_MASK_CH16_RSVD_PG_8814B) +#define BIT_SET_CH16_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH16_RSVD_PG_8814B(x) | BIT_CH16_RSVD_PG_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_HWAMSDU_CTL1_8814B */ + +#define BIT_SHIFT_HWAMSDU_PKTNUM_8814B 8 +#define BIT_MASK_HWAMSDU_PKTNUM_8814B 0x3f +#define BIT_HWAMSDU_PKTNUM_8814B(x) \ + (((x) & BIT_MASK_HWAMSDU_PKTNUM_8814B) \ + << BIT_SHIFT_HWAMSDU_PKTNUM_8814B) +#define BITS_HWAMSDU_PKTNUM_8814B \ + (BIT_MASK_HWAMSDU_PKTNUM_8814B << BIT_SHIFT_HWAMSDU_PKTNUM_8814B) +#define BIT_CLEAR_HWAMSDU_PKTNUM_8814B(x) ((x) & (~BITS_HWAMSDU_PKTNUM_8814B)) +#define BIT_GET_HWAMSDU_PKTNUM_8814B(x) \ + (((x) >> BIT_SHIFT_HWAMSDU_PKTNUM_8814B) & \ + BIT_MASK_HWAMSDU_PKTNUM_8814B) +#define BIT_SET_HWAMSDU_PKTNUM_8814B(x, v) \ + (BIT_CLEAR_HWAMSDU_PKTNUM_8814B(x) | BIT_HWAMSDU_PKTNUM_8814B(v)) + +#define BIT_HWAMSDU_BUSY_8814B BIT(7) +#define BIT_SINGLE_AMSDU_8814B BIT(2) +#define BIT_HWAMSDU_PADDING_MODE_8814B BIT(1) +#define BIT_HWAMSDU_EN_8814B BIT(0) + +/* 2 REG_HWAMSDU_CTL2_8814B */ + +#define BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B 16 +#define BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B 0xffff +#define BIT_HWAMSDU_AMSDU_TIMEOUT_8814B(x) \ + (((x) & BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B) \ + << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B) +#define BITS_HWAMSDU_AMSDU_TIMEOUT_8814B \ + (BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B \ + << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B) +#define BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT_8814B(x) \ + ((x) & (~BITS_HWAMSDU_AMSDU_TIMEOUT_8814B)) +#define BIT_GET_HWAMSDU_AMSDU_TIMEOUT_8814B(x) \ + (((x) >> BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B) & \ + BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B) +#define BIT_SET_HWAMSDU_AMSDU_TIMEOUT_8814B(x, v) \ + (BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT_8814B(x) | \ + BIT_HWAMSDU_AMSDU_TIMEOUT_8814B(v)) + +#define BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B 0 +#define BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B 0xffff +#define BIT_HWAMSDU_MSDU_TIMEOUT_8814B(x) \ + (((x) & BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B) \ + << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B) +#define BITS_HWAMSDU_MSDU_TIMEOUT_8814B \ + (BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B \ + << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B) +#define BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT_8814B(x) \ + ((x) & (~BITS_HWAMSDU_MSDU_TIMEOUT_8814B)) +#define BIT_GET_HWAMSDU_MSDU_TIMEOUT_8814B(x) \ + (((x) >> BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B) & \ + BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B) +#define BIT_SET_HWAMSDU_MSDU_TIMEOUT_8814B(x, v) \ + (BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT_8814B(x) | \ + BIT_HWAMSDU_MSDU_TIMEOUT_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_0_8814B */ +#define BIT_CH0_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH0_HIGH_TH_8814B 16 +#define BIT_MASK_CH0_HIGH_TH_8814B 0xfff +#define BIT_CH0_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH0_HIGH_TH_8814B) << BIT_SHIFT_CH0_HIGH_TH_8814B) +#define BITS_CH0_HIGH_TH_8814B \ + (BIT_MASK_CH0_HIGH_TH_8814B << BIT_SHIFT_CH0_HIGH_TH_8814B) +#define BIT_CLEAR_CH0_HIGH_TH_8814B(x) ((x) & (~BITS_CH0_HIGH_TH_8814B)) +#define BIT_GET_CH0_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH0_HIGH_TH_8814B) & BIT_MASK_CH0_HIGH_TH_8814B) +#define BIT_SET_CH0_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH0_HIGH_TH_8814B(x) | BIT_CH0_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH0_LOW_TH_8814B 0 +#define BIT_MASK_CH0_LOW_TH_8814B 0xfff +#define BIT_CH0_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH0_LOW_TH_8814B) << BIT_SHIFT_CH0_LOW_TH_8814B) +#define BITS_CH0_LOW_TH_8814B \ + (BIT_MASK_CH0_LOW_TH_8814B << BIT_SHIFT_CH0_LOW_TH_8814B) +#define BIT_CLEAR_CH0_LOW_TH_8814B(x) ((x) & (~BITS_CH0_LOW_TH_8814B)) +#define BIT_GET_CH0_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH0_LOW_TH_8814B) & BIT_MASK_CH0_LOW_TH_8814B) +#define BIT_SET_CH0_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH0_LOW_TH_8814B(x) | BIT_CH0_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_1_8814B */ +#define BIT_CH1_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH1_HIGH_TH_8814B 16 +#define BIT_MASK_CH1_HIGH_TH_8814B 0xfff +#define BIT_CH1_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH1_HIGH_TH_8814B) << BIT_SHIFT_CH1_HIGH_TH_8814B) +#define BITS_CH1_HIGH_TH_8814B \ + (BIT_MASK_CH1_HIGH_TH_8814B << BIT_SHIFT_CH1_HIGH_TH_8814B) +#define BIT_CLEAR_CH1_HIGH_TH_8814B(x) ((x) & (~BITS_CH1_HIGH_TH_8814B)) +#define BIT_GET_CH1_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH1_HIGH_TH_8814B) & BIT_MASK_CH1_HIGH_TH_8814B) +#define BIT_SET_CH1_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH1_HIGH_TH_8814B(x) | BIT_CH1_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH1_LOW_TH_8814B 0 +#define BIT_MASK_CH1_LOW_TH_8814B 0xfff +#define BIT_CH1_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH1_LOW_TH_8814B) << BIT_SHIFT_CH1_LOW_TH_8814B) +#define BITS_CH1_LOW_TH_8814B \ + (BIT_MASK_CH1_LOW_TH_8814B << BIT_SHIFT_CH1_LOW_TH_8814B) +#define BIT_CLEAR_CH1_LOW_TH_8814B(x) ((x) & (~BITS_CH1_LOW_TH_8814B)) +#define BIT_GET_CH1_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH1_LOW_TH_8814B) & BIT_MASK_CH1_LOW_TH_8814B) +#define BIT_SET_CH1_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH1_LOW_TH_8814B(x) | BIT_CH1_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_2_8814B */ +#define BIT_CH2_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH2_HIGH_TH_8814B 16 +#define BIT_MASK_CH2_HIGH_TH_8814B 0xfff +#define BIT_CH2_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH2_HIGH_TH_8814B) << BIT_SHIFT_CH2_HIGH_TH_8814B) +#define BITS_CH2_HIGH_TH_8814B \ + (BIT_MASK_CH2_HIGH_TH_8814B << BIT_SHIFT_CH2_HIGH_TH_8814B) +#define BIT_CLEAR_CH2_HIGH_TH_8814B(x) ((x) & (~BITS_CH2_HIGH_TH_8814B)) +#define BIT_GET_CH2_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH2_HIGH_TH_8814B) & BIT_MASK_CH2_HIGH_TH_8814B) +#define BIT_SET_CH2_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH2_HIGH_TH_8814B(x) | BIT_CH2_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH2_LOW_TH_8814B 0 +#define BIT_MASK_CH2_LOW_TH_8814B 0xfff +#define BIT_CH2_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH2_LOW_TH_8814B) << BIT_SHIFT_CH2_LOW_TH_8814B) +#define BITS_CH2_LOW_TH_8814B \ + (BIT_MASK_CH2_LOW_TH_8814B << BIT_SHIFT_CH2_LOW_TH_8814B) +#define BIT_CLEAR_CH2_LOW_TH_8814B(x) ((x) & (~BITS_CH2_LOW_TH_8814B)) +#define BIT_GET_CH2_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH2_LOW_TH_8814B) & BIT_MASK_CH2_LOW_TH_8814B) +#define BIT_SET_CH2_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH2_LOW_TH_8814B(x) | BIT_CH2_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_3_8814B */ +#define BIT_CH3_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH3_HIGH_TH_8814B 16 +#define BIT_MASK_CH3_HIGH_TH_8814B 0xfff +#define BIT_CH3_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH3_HIGH_TH_8814B) << BIT_SHIFT_CH3_HIGH_TH_8814B) +#define BITS_CH3_HIGH_TH_8814B \ + (BIT_MASK_CH3_HIGH_TH_8814B << BIT_SHIFT_CH3_HIGH_TH_8814B) +#define BIT_CLEAR_CH3_HIGH_TH_8814B(x) ((x) & (~BITS_CH3_HIGH_TH_8814B)) +#define BIT_GET_CH3_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH3_HIGH_TH_8814B) & BIT_MASK_CH3_HIGH_TH_8814B) +#define BIT_SET_CH3_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH3_HIGH_TH_8814B(x) | BIT_CH3_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH3_LOW_TH_8814B 0 +#define BIT_MASK_CH3_LOW_TH_8814B 0xfff +#define BIT_CH3_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH3_LOW_TH_8814B) << BIT_SHIFT_CH3_LOW_TH_8814B) +#define BITS_CH3_LOW_TH_8814B \ + (BIT_MASK_CH3_LOW_TH_8814B << BIT_SHIFT_CH3_LOW_TH_8814B) +#define BIT_CLEAR_CH3_LOW_TH_8814B(x) ((x) & (~BITS_CH3_LOW_TH_8814B)) +#define BIT_GET_CH3_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH3_LOW_TH_8814B) & BIT_MASK_CH3_LOW_TH_8814B) +#define BIT_SET_CH3_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH3_LOW_TH_8814B(x) | BIT_CH3_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_4_8814B */ +#define BIT_CH4_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH4_HIGH_TH_8814B 16 +#define BIT_MASK_CH4_HIGH_TH_8814B 0xfff +#define BIT_CH4_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH4_HIGH_TH_8814B) << BIT_SHIFT_CH4_HIGH_TH_8814B) +#define BITS_CH4_HIGH_TH_8814B \ + (BIT_MASK_CH4_HIGH_TH_8814B << BIT_SHIFT_CH4_HIGH_TH_8814B) +#define BIT_CLEAR_CH4_HIGH_TH_8814B(x) ((x) & (~BITS_CH4_HIGH_TH_8814B)) +#define BIT_GET_CH4_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH4_HIGH_TH_8814B) & BIT_MASK_CH4_HIGH_TH_8814B) +#define BIT_SET_CH4_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH4_HIGH_TH_8814B(x) | BIT_CH4_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH4_LOW_TH_8814B 0 +#define BIT_MASK_CH4_LOW_TH_8814B 0xfff +#define BIT_CH4_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH4_LOW_TH_8814B) << BIT_SHIFT_CH4_LOW_TH_8814B) +#define BITS_CH4_LOW_TH_8814B \ + (BIT_MASK_CH4_LOW_TH_8814B << BIT_SHIFT_CH4_LOW_TH_8814B) +#define BIT_CLEAR_CH4_LOW_TH_8814B(x) ((x) & (~BITS_CH4_LOW_TH_8814B)) +#define BIT_GET_CH4_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH4_LOW_TH_8814B) & BIT_MASK_CH4_LOW_TH_8814B) +#define BIT_SET_CH4_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH4_LOW_TH_8814B(x) | BIT_CH4_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_5_8814B */ +#define BIT_CH5_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH5_HIGH_TH_8814B 16 +#define BIT_MASK_CH5_HIGH_TH_8814B 0xfff +#define BIT_CH5_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH5_HIGH_TH_8814B) << BIT_SHIFT_CH5_HIGH_TH_8814B) +#define BITS_CH5_HIGH_TH_8814B \ + (BIT_MASK_CH5_HIGH_TH_8814B << BIT_SHIFT_CH5_HIGH_TH_8814B) +#define BIT_CLEAR_CH5_HIGH_TH_8814B(x) ((x) & (~BITS_CH5_HIGH_TH_8814B)) +#define BIT_GET_CH5_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH5_HIGH_TH_8814B) & BIT_MASK_CH5_HIGH_TH_8814B) +#define BIT_SET_CH5_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH5_HIGH_TH_8814B(x) | BIT_CH5_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH5_LOW_TH_8814B 0 +#define BIT_MASK_CH5_LOW_TH_8814B 0xfff +#define BIT_CH5_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH5_LOW_TH_8814B) << BIT_SHIFT_CH5_LOW_TH_8814B) +#define BITS_CH5_LOW_TH_8814B \ + (BIT_MASK_CH5_LOW_TH_8814B << BIT_SHIFT_CH5_LOW_TH_8814B) +#define BIT_CLEAR_CH5_LOW_TH_8814B(x) ((x) & (~BITS_CH5_LOW_TH_8814B)) +#define BIT_GET_CH5_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH5_LOW_TH_8814B) & BIT_MASK_CH5_LOW_TH_8814B) +#define BIT_SET_CH5_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH5_LOW_TH_8814B(x) | BIT_CH5_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_6_8814B */ +#define BIT_CH6_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH6_HIGH_TH_8814B 16 +#define BIT_MASK_CH6_HIGH_TH_8814B 0xfff +#define BIT_CH6_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH6_HIGH_TH_8814B) << BIT_SHIFT_CH6_HIGH_TH_8814B) +#define BITS_CH6_HIGH_TH_8814B \ + (BIT_MASK_CH6_HIGH_TH_8814B << BIT_SHIFT_CH6_HIGH_TH_8814B) +#define BIT_CLEAR_CH6_HIGH_TH_8814B(x) ((x) & (~BITS_CH6_HIGH_TH_8814B)) +#define BIT_GET_CH6_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH6_HIGH_TH_8814B) & BIT_MASK_CH6_HIGH_TH_8814B) +#define BIT_SET_CH6_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH6_HIGH_TH_8814B(x) | BIT_CH6_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH6_LOW_TH_8814B 0 +#define BIT_MASK_CH6_LOW_TH_8814B 0xfff +#define BIT_CH6_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH6_LOW_TH_8814B) << BIT_SHIFT_CH6_LOW_TH_8814B) +#define BITS_CH6_LOW_TH_8814B \ + (BIT_MASK_CH6_LOW_TH_8814B << BIT_SHIFT_CH6_LOW_TH_8814B) +#define BIT_CLEAR_CH6_LOW_TH_8814B(x) ((x) & (~BITS_CH6_LOW_TH_8814B)) +#define BIT_GET_CH6_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH6_LOW_TH_8814B) & BIT_MASK_CH6_LOW_TH_8814B) +#define BIT_SET_CH6_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH6_LOW_TH_8814B(x) | BIT_CH6_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_7_8814B */ +#define BIT_CH7_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH7_HIGH_TH_8814B 16 +#define BIT_MASK_CH7_HIGH_TH_8814B 0xfff +#define BIT_CH7_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH7_HIGH_TH_8814B) << BIT_SHIFT_CH7_HIGH_TH_8814B) +#define BITS_CH7_HIGH_TH_8814B \ + (BIT_MASK_CH7_HIGH_TH_8814B << BIT_SHIFT_CH7_HIGH_TH_8814B) +#define BIT_CLEAR_CH7_HIGH_TH_8814B(x) ((x) & (~BITS_CH7_HIGH_TH_8814B)) +#define BIT_GET_CH7_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH7_HIGH_TH_8814B) & BIT_MASK_CH7_HIGH_TH_8814B) +#define BIT_SET_CH7_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH7_HIGH_TH_8814B(x) | BIT_CH7_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH7_LOW_TH_8814B 0 +#define BIT_MASK_CH7_LOW_TH_8814B 0xfff +#define BIT_CH7_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH7_LOW_TH_8814B) << BIT_SHIFT_CH7_LOW_TH_8814B) +#define BITS_CH7_LOW_TH_8814B \ + (BIT_MASK_CH7_LOW_TH_8814B << BIT_SHIFT_CH7_LOW_TH_8814B) +#define BIT_CLEAR_CH7_LOW_TH_8814B(x) ((x) & (~BITS_CH7_LOW_TH_8814B)) +#define BIT_GET_CH7_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH7_LOW_TH_8814B) & BIT_MASK_CH7_LOW_TH_8814B) +#define BIT_SET_CH7_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH7_LOW_TH_8814B(x) | BIT_CH7_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_8_8814B */ +#define BIT_CH8_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH8_HIGH_TH_8814B 16 +#define BIT_MASK_CH8_HIGH_TH_8814B 0xfff +#define BIT_CH8_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH8_HIGH_TH_8814B) << BIT_SHIFT_CH8_HIGH_TH_8814B) +#define BITS_CH8_HIGH_TH_8814B \ + (BIT_MASK_CH8_HIGH_TH_8814B << BIT_SHIFT_CH8_HIGH_TH_8814B) +#define BIT_CLEAR_CH8_HIGH_TH_8814B(x) ((x) & (~BITS_CH8_HIGH_TH_8814B)) +#define BIT_GET_CH8_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH8_HIGH_TH_8814B) & BIT_MASK_CH8_HIGH_TH_8814B) +#define BIT_SET_CH8_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH8_HIGH_TH_8814B(x) | BIT_CH8_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH8_LOW_TH_8814B 0 +#define BIT_MASK_CH8_LOW_TH_8814B 0xfff +#define BIT_CH8_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH8_LOW_TH_8814B) << BIT_SHIFT_CH8_LOW_TH_8814B) +#define BITS_CH8_LOW_TH_8814B \ + (BIT_MASK_CH8_LOW_TH_8814B << BIT_SHIFT_CH8_LOW_TH_8814B) +#define BIT_CLEAR_CH8_LOW_TH_8814B(x) ((x) & (~BITS_CH8_LOW_TH_8814B)) +#define BIT_GET_CH8_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH8_LOW_TH_8814B) & BIT_MASK_CH8_LOW_TH_8814B) +#define BIT_SET_CH8_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH8_LOW_TH_8814B(x) | BIT_CH8_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_9_8814B */ +#define BIT_CH9_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH9_HIGH_TH_8814B 16 +#define BIT_MASK_CH9_HIGH_TH_8814B 0xfff +#define BIT_CH9_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH9_HIGH_TH_8814B) << BIT_SHIFT_CH9_HIGH_TH_8814B) +#define BITS_CH9_HIGH_TH_8814B \ + (BIT_MASK_CH9_HIGH_TH_8814B << BIT_SHIFT_CH9_HIGH_TH_8814B) +#define BIT_CLEAR_CH9_HIGH_TH_8814B(x) ((x) & (~BITS_CH9_HIGH_TH_8814B)) +#define BIT_GET_CH9_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH9_HIGH_TH_8814B) & BIT_MASK_CH9_HIGH_TH_8814B) +#define BIT_SET_CH9_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH9_HIGH_TH_8814B(x) | BIT_CH9_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH9_LOW_TH_8814B 0 +#define BIT_MASK_CH9_LOW_TH_8814B 0xfff +#define BIT_CH9_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH9_LOW_TH_8814B) << BIT_SHIFT_CH9_LOW_TH_8814B) +#define BITS_CH9_LOW_TH_8814B \ + (BIT_MASK_CH9_LOW_TH_8814B << BIT_SHIFT_CH9_LOW_TH_8814B) +#define BIT_CLEAR_CH9_LOW_TH_8814B(x) ((x) & (~BITS_CH9_LOW_TH_8814B)) +#define BIT_GET_CH9_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH9_LOW_TH_8814B) & BIT_MASK_CH9_LOW_TH_8814B) +#define BIT_SET_CH9_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH9_LOW_TH_8814B(x) | BIT_CH9_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_10_8814B */ +#define BIT_CH10_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH10_HIGH_TH_8814B 16 +#define BIT_MASK_CH10_HIGH_TH_8814B 0xfff +#define BIT_CH10_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH10_HIGH_TH_8814B) << BIT_SHIFT_CH10_HIGH_TH_8814B) +#define BITS_CH10_HIGH_TH_8814B \ + (BIT_MASK_CH10_HIGH_TH_8814B << BIT_SHIFT_CH10_HIGH_TH_8814B) +#define BIT_CLEAR_CH10_HIGH_TH_8814B(x) ((x) & (~BITS_CH10_HIGH_TH_8814B)) +#define BIT_GET_CH10_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH10_HIGH_TH_8814B) & BIT_MASK_CH10_HIGH_TH_8814B) +#define BIT_SET_CH10_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH10_HIGH_TH_8814B(x) | BIT_CH10_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH10_LOW_TH_8814B 0 +#define BIT_MASK_CH10_LOW_TH_8814B 0xfff +#define BIT_CH10_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH10_LOW_TH_8814B) << BIT_SHIFT_CH10_LOW_TH_8814B) +#define BITS_CH10_LOW_TH_8814B \ + (BIT_MASK_CH10_LOW_TH_8814B << BIT_SHIFT_CH10_LOW_TH_8814B) +#define BIT_CLEAR_CH10_LOW_TH_8814B(x) ((x) & (~BITS_CH10_LOW_TH_8814B)) +#define BIT_GET_CH10_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH10_LOW_TH_8814B) & BIT_MASK_CH10_LOW_TH_8814B) +#define BIT_SET_CH10_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH10_LOW_TH_8814B(x) | BIT_CH10_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_11_8814B */ +#define BIT_CH11_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH11_HIGH_TH_8814B 16 +#define BIT_MASK_CH11_HIGH_TH_8814B 0xfff +#define BIT_CH11_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH11_HIGH_TH_8814B) << BIT_SHIFT_CH11_HIGH_TH_8814B) +#define BITS_CH11_HIGH_TH_8814B \ + (BIT_MASK_CH11_HIGH_TH_8814B << BIT_SHIFT_CH11_HIGH_TH_8814B) +#define BIT_CLEAR_CH11_HIGH_TH_8814B(x) ((x) & (~BITS_CH11_HIGH_TH_8814B)) +#define BIT_GET_CH11_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH11_HIGH_TH_8814B) & BIT_MASK_CH11_HIGH_TH_8814B) +#define BIT_SET_CH11_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH11_HIGH_TH_8814B(x) | BIT_CH11_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH11_LOW_TH_8814B 0 +#define BIT_MASK_CH11_LOW_TH_8814B 0xfff +#define BIT_CH11_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH11_LOW_TH_8814B) << BIT_SHIFT_CH11_LOW_TH_8814B) +#define BITS_CH11_LOW_TH_8814B \ + (BIT_MASK_CH11_LOW_TH_8814B << BIT_SHIFT_CH11_LOW_TH_8814B) +#define BIT_CLEAR_CH11_LOW_TH_8814B(x) ((x) & (~BITS_CH11_LOW_TH_8814B)) +#define BIT_GET_CH11_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH11_LOW_TH_8814B) & BIT_MASK_CH11_LOW_TH_8814B) +#define BIT_SET_CH11_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH11_LOW_TH_8814B(x) | BIT_CH11_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_12_8814B */ +#define BIT_CH12_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH12_HIGH_TH_8814B 16 +#define BIT_MASK_CH12_HIGH_TH_8814B 0xfff +#define BIT_CH12_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH12_HIGH_TH_8814B) << BIT_SHIFT_CH12_HIGH_TH_8814B) +#define BITS_CH12_HIGH_TH_8814B \ + (BIT_MASK_CH12_HIGH_TH_8814B << BIT_SHIFT_CH12_HIGH_TH_8814B) +#define BIT_CLEAR_CH12_HIGH_TH_8814B(x) ((x) & (~BITS_CH12_HIGH_TH_8814B)) +#define BIT_GET_CH12_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH12_HIGH_TH_8814B) & BIT_MASK_CH12_HIGH_TH_8814B) +#define BIT_SET_CH12_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH12_HIGH_TH_8814B(x) | BIT_CH12_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH12_LOW_TH_8814B 0 +#define BIT_MASK_CH12_LOW_TH_8814B 0xfff +#define BIT_CH12_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH12_LOW_TH_8814B) << BIT_SHIFT_CH12_LOW_TH_8814B) +#define BITS_CH12_LOW_TH_8814B \ + (BIT_MASK_CH12_LOW_TH_8814B << BIT_SHIFT_CH12_LOW_TH_8814B) +#define BIT_CLEAR_CH12_LOW_TH_8814B(x) ((x) & (~BITS_CH12_LOW_TH_8814B)) +#define BIT_GET_CH12_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH12_LOW_TH_8814B) & BIT_MASK_CH12_LOW_TH_8814B) +#define BIT_SET_CH12_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH12_LOW_TH_8814B(x) | BIT_CH12_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_13_8814B */ +#define BIT_CH13_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH13_HIGH_TH_8814B 16 +#define BIT_MASK_CH13_HIGH_TH_8814B 0xfff +#define BIT_CH13_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH13_HIGH_TH_8814B) << BIT_SHIFT_CH13_HIGH_TH_8814B) +#define BITS_CH13_HIGH_TH_8814B \ + (BIT_MASK_CH13_HIGH_TH_8814B << BIT_SHIFT_CH13_HIGH_TH_8814B) +#define BIT_CLEAR_CH13_HIGH_TH_8814B(x) ((x) & (~BITS_CH13_HIGH_TH_8814B)) +#define BIT_GET_CH13_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH13_HIGH_TH_8814B) & BIT_MASK_CH13_HIGH_TH_8814B) +#define BIT_SET_CH13_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH13_HIGH_TH_8814B(x) | BIT_CH13_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH13_LOW_TH_8814B 0 +#define BIT_MASK_CH13_LOW_TH_8814B 0xfff +#define BIT_CH13_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH13_LOW_TH_8814B) << BIT_SHIFT_CH13_LOW_TH_8814B) +#define BITS_CH13_LOW_TH_8814B \ + (BIT_MASK_CH13_LOW_TH_8814B << BIT_SHIFT_CH13_LOW_TH_8814B) +#define BIT_CLEAR_CH13_LOW_TH_8814B(x) ((x) & (~BITS_CH13_LOW_TH_8814B)) +#define BIT_GET_CH13_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH13_LOW_TH_8814B) & BIT_MASK_CH13_LOW_TH_8814B) +#define BIT_SET_CH13_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH13_LOW_TH_8814B(x) | BIT_CH13_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_14_8814B */ +#define BIT_CH14_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH14_HIGH_TH_8814B 16 +#define BIT_MASK_CH14_HIGH_TH_8814B 0xfff +#define BIT_CH14_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH14_HIGH_TH_8814B) << BIT_SHIFT_CH14_HIGH_TH_8814B) +#define BITS_CH14_HIGH_TH_8814B \ + (BIT_MASK_CH14_HIGH_TH_8814B << BIT_SHIFT_CH14_HIGH_TH_8814B) +#define BIT_CLEAR_CH14_HIGH_TH_8814B(x) ((x) & (~BITS_CH14_HIGH_TH_8814B)) +#define BIT_GET_CH14_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH14_HIGH_TH_8814B) & BIT_MASK_CH14_HIGH_TH_8814B) +#define BIT_SET_CH14_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH14_HIGH_TH_8814B(x) | BIT_CH14_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH14_LOW_TH_8814B 0 +#define BIT_MASK_CH14_LOW_TH_8814B 0xfff +#define BIT_CH14_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH14_LOW_TH_8814B) << BIT_SHIFT_CH14_LOW_TH_8814B) +#define BITS_CH14_LOW_TH_8814B \ + (BIT_MASK_CH14_LOW_TH_8814B << BIT_SHIFT_CH14_LOW_TH_8814B) +#define BIT_CLEAR_CH14_LOW_TH_8814B(x) ((x) & (~BITS_CH14_LOW_TH_8814B)) +#define BIT_GET_CH14_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH14_LOW_TH_8814B) & BIT_MASK_CH14_LOW_TH_8814B) +#define BIT_SET_CH14_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH14_LOW_TH_8814B(x) | BIT_CH14_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_15_8814B */ +#define BIT_CH15_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH15_HIGH_TH_8814B 16 +#define BIT_MASK_CH15_HIGH_TH_8814B 0xfff +#define BIT_CH15_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH15_HIGH_TH_8814B) << BIT_SHIFT_CH15_HIGH_TH_8814B) +#define BITS_CH15_HIGH_TH_8814B \ + (BIT_MASK_CH15_HIGH_TH_8814B << BIT_SHIFT_CH15_HIGH_TH_8814B) +#define BIT_CLEAR_CH15_HIGH_TH_8814B(x) ((x) & (~BITS_CH15_HIGH_TH_8814B)) +#define BIT_GET_CH15_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH15_HIGH_TH_8814B) & BIT_MASK_CH15_HIGH_TH_8814B) +#define BIT_SET_CH15_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH15_HIGH_TH_8814B(x) | BIT_CH15_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH15_LOW_TH_8814B 0 +#define BIT_MASK_CH15_LOW_TH_8814B 0xfff +#define BIT_CH15_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH15_LOW_TH_8814B) << BIT_SHIFT_CH15_LOW_TH_8814B) +#define BITS_CH15_LOW_TH_8814B \ + (BIT_MASK_CH15_LOW_TH_8814B << BIT_SHIFT_CH15_LOW_TH_8814B) +#define BIT_CLEAR_CH15_LOW_TH_8814B(x) ((x) & (~BITS_CH15_LOW_TH_8814B)) +#define BIT_GET_CH15_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH15_LOW_TH_8814B) & BIT_MASK_CH15_LOW_TH_8814B) +#define BIT_SET_CH15_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH15_LOW_TH_8814B(x) | BIT_CH15_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_16_8814B */ +#define BIT_CH16_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH16_HIGH_TH_8814B 16 +#define BIT_MASK_CH16_HIGH_TH_8814B 0xfff +#define BIT_CH16_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH16_HIGH_TH_8814B) << BIT_SHIFT_CH16_HIGH_TH_8814B) +#define BITS_CH16_HIGH_TH_8814B \ + (BIT_MASK_CH16_HIGH_TH_8814B << BIT_SHIFT_CH16_HIGH_TH_8814B) +#define BIT_CLEAR_CH16_HIGH_TH_8814B(x) ((x) & (~BITS_CH16_HIGH_TH_8814B)) +#define BIT_GET_CH16_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH16_HIGH_TH_8814B) & BIT_MASK_CH16_HIGH_TH_8814B) +#define BIT_SET_CH16_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH16_HIGH_TH_8814B(x) | BIT_CH16_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH16_LOW_TH_8814B 0 +#define BIT_MASK_CH16_LOW_TH_8814B 0xfff +#define BIT_CH16_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH16_LOW_TH_8814B) << BIT_SHIFT_CH16_LOW_TH_8814B) +#define BITS_CH16_LOW_TH_8814B \ + (BIT_MASK_CH16_LOW_TH_8814B << BIT_SHIFT_CH16_LOW_TH_8814B) +#define BIT_CLEAR_CH16_LOW_TH_8814B(x) ((x) & (~BITS_CH16_LOW_TH_8814B)) +#define BIT_GET_CH16_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH16_LOW_TH_8814B) & BIT_MASK_CH16_LOW_TH_8814B) +#define BIT_SET_CH16_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH16_LOW_TH_8814B(x) | BIT_CH16_LOW_TH_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + /* 2 REG_NOT_VALID_8814B */ /* 2 REG_PCIE_CTRL_8814B */ @@ -4292,18 +9427,35 @@ #define BIT_SHIFT_PCIE_MAX_RXDMA_8814B 28 #define BIT_MASK_PCIE_MAX_RXDMA_8814B 0x7 -#define BIT_PCIE_MAX_RXDMA_8814B(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA_8814B) << BIT_SHIFT_PCIE_MAX_RXDMA_8814B) -#define BIT_GET_PCIE_MAX_RXDMA_8814B(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8814B) & BIT_MASK_PCIE_MAX_RXDMA_8814B) - +#define BIT_PCIE_MAX_RXDMA_8814B(x) \ + (((x) & BIT_MASK_PCIE_MAX_RXDMA_8814B) \ + << BIT_SHIFT_PCIE_MAX_RXDMA_8814B) +#define BITS_PCIE_MAX_RXDMA_8814B \ + (BIT_MASK_PCIE_MAX_RXDMA_8814B << BIT_SHIFT_PCIE_MAX_RXDMA_8814B) +#define BIT_CLEAR_PCIE_MAX_RXDMA_8814B(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8814B)) +#define BIT_GET_PCIE_MAX_RXDMA_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8814B) & \ + BIT_MASK_PCIE_MAX_RXDMA_8814B) +#define BIT_SET_PCIE_MAX_RXDMA_8814B(x, v) \ + (BIT_CLEAR_PCIE_MAX_RXDMA_8814B(x) | BIT_PCIE_MAX_RXDMA_8814B(v)) #define BIT_MULRW_8814B BIT(27) #define BIT_SHIFT_PCIE_MAX_TXDMA_8814B 24 #define BIT_MASK_PCIE_MAX_TXDMA_8814B 0x7 -#define BIT_PCIE_MAX_TXDMA_8814B(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA_8814B) << BIT_SHIFT_PCIE_MAX_TXDMA_8814B) -#define BIT_GET_PCIE_MAX_TXDMA_8814B(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8814B) & BIT_MASK_PCIE_MAX_TXDMA_8814B) - - +#define BIT_PCIE_MAX_TXDMA_8814B(x) \ + (((x) & BIT_MASK_PCIE_MAX_TXDMA_8814B) \ + << BIT_SHIFT_PCIE_MAX_TXDMA_8814B) +#define BITS_PCIE_MAX_TXDMA_8814B \ + (BIT_MASK_PCIE_MAX_TXDMA_8814B << BIT_SHIFT_PCIE_MAX_TXDMA_8814B) +#define BIT_CLEAR_PCIE_MAX_TXDMA_8814B(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8814B)) +#define BIT_GET_PCIE_MAX_TXDMA_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8814B) & \ + BIT_MASK_PCIE_MAX_TXDMA_8814B) +#define BIT_SET_PCIE_MAX_TXDMA_8814B(x, v) \ + (BIT_CLEAR_PCIE_MAX_TXDMA_8814B(x) | BIT_PCIE_MAX_TXDMA_8814B(v)) + +#define BIT_PWR_SCALE_START_PS_8814B BIT(23) #define BIT_EN_CPL_TIMEOUT_PS_8814B BIT(22) #define BIT_REG_TXDMA_FAIL_PS_8814B BIT(21) #define BIT_PCIE_RST_TRXDMA_INTF_8814B BIT(20) @@ -4311,2813 +9463,7679 @@ #define BIT_EN_ADV_CLKGATE_8814B BIT(18) #define BIT_PCIE_EN_SWENT_L23_8814B BIT(17) #define BIT_PCIE_EN_HWEXT_L1_8814B BIT(16) -#define BIT_RX_CLOSE_EN_8814B BIT(15) -#define BIT_STOP_BCNQ_8814B BIT(14) -#define BIT_STOP_MGQ_8814B BIT(13) -#define BIT_STOP_VOQ_8814B BIT(12) -#define BIT_STOP_VIQ_8814B BIT(11) -#define BIT_STOP_BEQ_8814B BIT(10) -#define BIT_STOP_BKQ_8814B BIT(9) -#define BIT_STOP_RXQ_8814B BIT(8) -#define BIT_STOP_HI7Q_8814B BIT(7) -#define BIT_STOP_HI6Q_8814B BIT(6) -#define BIT_STOP_HI5Q_8814B BIT(5) -#define BIT_STOP_HI4Q_8814B BIT(4) -#define BIT_STOP_HI3Q_8814B BIT(3) -#define BIT_STOP_HI2Q_8814B BIT(2) -#define BIT_STOP_HI1Q_8814B BIT(1) -#define BIT_STOP_HI0Q_8814B BIT(0) - -/* 2 REG_INT_MIG_8814B */ +#define BIT_STOP_P0_MPRT_BCNQ4_8814B BIT(6) +#define BIT_STOP_P0_MPRT_BCNQ3_8814B BIT(4) +#define BIT_STOP_P0_MPRT_BCNQ2_8814B BIT(2) +#define BIT_STOP_P0_MPRT_BCNQ1_8814B BIT(0) + +/* 2 REG_ACH_CTRL_8814B */ +#define BIT_STOP_P0HIQ19_8814B BIT(27) +#define BIT_STOP_P0HIQ18_8814B BIT(26) +#define BIT_STOP_P0HIQ17_8814B BIT(25) +#define BIT_STOP_P0HIQ16_8814B BIT(24) +#define BIT_RX_CLOSE_EN_V1_8814B BIT(21) +#define BIT_STOP_FWCMDQ_8814B BIT(20) +#define BIT_STOP_P0BCNQ_8814B BIT(18) +#define BIT_STOP_P0MGQ_8814B BIT(16) +#define BIT_STOP_ACH13_8814B BIT(15) +#define BIT_STOP_ACH12_8814B BIT(14) +#define BIT_STOP_ACH11_8814B BIT(13) +#define BIT_STOP_ACH10_8814B BIT(12) +#define BIT_STOP_ACH9_8814B BIT(11) +#define BIT_STOP_ACH8_8814B BIT(10) +#define BIT_STOP_ACH7_8814B BIT(9) +#define BIT_STOP_ACH6_8814B BIT(8) +#define BIT_STOP_ACH5_8814B BIT(7) +#define BIT_STOP_ACH4_8814B BIT(6) +#define BIT_STOP_ACH3_8814B BIT(5) +#define BIT_STOP_ACH2_8814B BIT(4) +#define BIT_STOP_ACH1_8814B BIT(3) +#define BIT_STOP_ACH0_8814B BIT(2) +#define BIT_STOP_P0RX_8814B BIT(0) + +/* 2 REG_HIQ_CTRL_8814B */ +#define BIT_STOP_P0HIQ15_8814B BIT(15) +#define BIT_STOP_P0HIQ14_8814B BIT(14) +#define BIT_STOP_P0HIQ13_8814B BIT(13) +#define BIT_STOP_P0HIQ12_8814B BIT(12) +#define BIT_STOP_P0HIQ11_8814B BIT(11) +#define BIT_STOP_P0HIQ10_8814B BIT(10) +#define BIT_STOP_P0HIQ9_8814B BIT(9) +#define BIT_STOP_P0HIQ8_8814B BIT(8) +#define BIT_STOP_P0HIQ7_8814B BIT(7) +#define BIT_STOP_P0HIQ6_8814B BIT(6) +#define BIT_STOP_P0HIQ5_8814B BIT(5) +#define BIT_STOP_P0HIQ4_8814B BIT(4) +#define BIT_STOP_P0HIQ3_8814B BIT(3) +#define BIT_STOP_P0HIQ2_8814B BIT(2) +#define BIT_STOP_P0HIQ1_8814B BIT(1) +#define BIT_STOP_P0HIQ0_8814B BIT(0) + +/* 2 REG_INT_MIG_V1_8814B */ #define BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B 28 #define BIT_MASK_TXTTIMER_MATCH_NUM_8814B 0xf -#define BIT_TXTTIMER_MATCH_NUM_8814B(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8814B) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) -#define BIT_GET_TXTTIMER_MATCH_NUM_8814B(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) & BIT_MASK_TXTTIMER_MATCH_NUM_8814B) - - +#define BIT_TXTTIMER_MATCH_NUM_8814B(x) \ + (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8814B) \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) +#define BITS_TXTTIMER_MATCH_NUM_8814B \ + (BIT_MASK_TXTTIMER_MATCH_NUM_8814B \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) +#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8814B(x) \ + ((x) & (~BITS_TXTTIMER_MATCH_NUM_8814B)) +#define BIT_GET_TXTTIMER_MATCH_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) & \ + BIT_MASK_TXTTIMER_MATCH_NUM_8814B) +#define BIT_SET_TXTTIMER_MATCH_NUM_8814B(x, v) \ + (BIT_CLEAR_TXTTIMER_MATCH_NUM_8814B(x) | \ + BIT_TXTTIMER_MATCH_NUM_8814B(v)) #define BIT_SHIFT_TXPKT_NUM_MATCH_8814B 24 #define BIT_MASK_TXPKT_NUM_MATCH_8814B 0xf -#define BIT_TXPKT_NUM_MATCH_8814B(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8814B) << BIT_SHIFT_TXPKT_NUM_MATCH_8814B) -#define BIT_GET_TXPKT_NUM_MATCH_8814B(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8814B) & BIT_MASK_TXPKT_NUM_MATCH_8814B) - - +#define BIT_TXPKT_NUM_MATCH_8814B(x) \ + (((x) & BIT_MASK_TXPKT_NUM_MATCH_8814B) \ + << BIT_SHIFT_TXPKT_NUM_MATCH_8814B) +#define BITS_TXPKT_NUM_MATCH_8814B \ + (BIT_MASK_TXPKT_NUM_MATCH_8814B << BIT_SHIFT_TXPKT_NUM_MATCH_8814B) +#define BIT_CLEAR_TXPKT_NUM_MATCH_8814B(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8814B)) +#define BIT_GET_TXPKT_NUM_MATCH_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8814B) & \ + BIT_MASK_TXPKT_NUM_MATCH_8814B) +#define BIT_SET_TXPKT_NUM_MATCH_8814B(x, v) \ + (BIT_CLEAR_TXPKT_NUM_MATCH_8814B(x) | BIT_TXPKT_NUM_MATCH_8814B(v)) #define BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B 20 #define BIT_MASK_RXTTIMER_MATCH_NUM_8814B 0xf -#define BIT_RXTTIMER_MATCH_NUM_8814B(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8814B) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) -#define BIT_GET_RXTTIMER_MATCH_NUM_8814B(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) & BIT_MASK_RXTTIMER_MATCH_NUM_8814B) - - +#define BIT_RXTTIMER_MATCH_NUM_8814B(x) \ + (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8814B) \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) +#define BITS_RXTTIMER_MATCH_NUM_8814B \ + (BIT_MASK_RXTTIMER_MATCH_NUM_8814B \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) +#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8814B(x) \ + ((x) & (~BITS_RXTTIMER_MATCH_NUM_8814B)) +#define BIT_GET_RXTTIMER_MATCH_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) & \ + BIT_MASK_RXTTIMER_MATCH_NUM_8814B) +#define BIT_SET_RXTTIMER_MATCH_NUM_8814B(x, v) \ + (BIT_CLEAR_RXTTIMER_MATCH_NUM_8814B(x) | \ + BIT_RXTTIMER_MATCH_NUM_8814B(v)) #define BIT_SHIFT_RXPKT_NUM_MATCH_8814B 16 #define BIT_MASK_RXPKT_NUM_MATCH_8814B 0xf -#define BIT_RXPKT_NUM_MATCH_8814B(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8814B) << BIT_SHIFT_RXPKT_NUM_MATCH_8814B) -#define BIT_GET_RXPKT_NUM_MATCH_8814B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8814B) & BIT_MASK_RXPKT_NUM_MATCH_8814B) - - +#define BIT_RXPKT_NUM_MATCH_8814B(x) \ + (((x) & BIT_MASK_RXPKT_NUM_MATCH_8814B) \ + << BIT_SHIFT_RXPKT_NUM_MATCH_8814B) +#define BITS_RXPKT_NUM_MATCH_8814B \ + (BIT_MASK_RXPKT_NUM_MATCH_8814B << BIT_SHIFT_RXPKT_NUM_MATCH_8814B) +#define BIT_CLEAR_RXPKT_NUM_MATCH_8814B(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8814B)) +#define BIT_GET_RXPKT_NUM_MATCH_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8814B) & \ + BIT_MASK_RXPKT_NUM_MATCH_8814B) +#define BIT_SET_RXPKT_NUM_MATCH_8814B(x, v) \ + (BIT_CLEAR_RXPKT_NUM_MATCH_8814B(x) | BIT_RXPKT_NUM_MATCH_8814B(v)) #define BIT_SHIFT_MIGRATE_TIMER_8814B 0 #define BIT_MASK_MIGRATE_TIMER_8814B 0xffff -#define BIT_MIGRATE_TIMER_8814B(x) (((x) & BIT_MASK_MIGRATE_TIMER_8814B) << BIT_SHIFT_MIGRATE_TIMER_8814B) -#define BIT_GET_MIGRATE_TIMER_8814B(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8814B) & BIT_MASK_MIGRATE_TIMER_8814B) +#define BIT_MIGRATE_TIMER_8814B(x) \ + (((x) & BIT_MASK_MIGRATE_TIMER_8814B) << BIT_SHIFT_MIGRATE_TIMER_8814B) +#define BITS_MIGRATE_TIMER_8814B \ + (BIT_MASK_MIGRATE_TIMER_8814B << BIT_SHIFT_MIGRATE_TIMER_8814B) +#define BIT_CLEAR_MIGRATE_TIMER_8814B(x) ((x) & (~BITS_MIGRATE_TIMER_8814B)) +#define BIT_GET_MIGRATE_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_MIGRATE_TIMER_8814B) & BIT_MASK_MIGRATE_TIMER_8814B) +#define BIT_SET_MIGRATE_TIMER_8814B(x, v) \ + (BIT_CLEAR_MIGRATE_TIMER_8814B(x) | BIT_MIGRATE_TIMER_8814B(v)) + +/* 2 REG_P0MGQ_TXBD_DESA_L_8814B */ + +/* 2 REG_P0MGQ_TXBD_DESA_H_8814B */ + +/* 2 REG_ACH0_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH0_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH0_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH0_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH0_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH0_TXBD_DESA_L_8814B) +#define BITS_ACH0_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH0_TXBD_DESA_L_8814B << BIT_SHIFT_ACH0_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH0_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH0_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH0_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH0_TXBD_DESA_L_8814B) +#define BIT_SET_ACH0_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH0_TXBD_DESA_L_8814B(x) | BIT_ACH0_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH0_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH0_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH0_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH0_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH0_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH0_TXBD_DESA_H_8814B) +#define BITS_ACH0_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH0_TXBD_DESA_H_8814B << BIT_SHIFT_ACH0_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH0_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH0_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH0_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH0_TXBD_DESA_H_8814B) +#define BIT_SET_ACH0_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH0_TXBD_DESA_H_8814B(x) | BIT_ACH0_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH1_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH1_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH1_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH1_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH1_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH1_TXBD_DESA_L_8814B) +#define BITS_ACH1_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH1_TXBD_DESA_L_8814B << BIT_SHIFT_ACH1_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH1_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH1_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH1_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH1_TXBD_DESA_L_8814B) +#define BIT_SET_ACH1_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH1_TXBD_DESA_L_8814B(x) | BIT_ACH1_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH1_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH1_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH1_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH1_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH1_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH1_TXBD_DESA_H_8814B) +#define BITS_ACH1_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH1_TXBD_DESA_H_8814B << BIT_SHIFT_ACH1_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH1_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH1_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH1_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH1_TXBD_DESA_H_8814B) +#define BIT_SET_ACH1_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH1_TXBD_DESA_H_8814B(x) | BIT_ACH1_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH2_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH2_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH2_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH2_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH2_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH2_TXBD_DESA_L_8814B) +#define BITS_ACH2_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH2_TXBD_DESA_L_8814B << BIT_SHIFT_ACH2_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH2_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH2_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH2_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH2_TXBD_DESA_L_8814B) +#define BIT_SET_ACH2_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH2_TXBD_DESA_L_8814B(x) | BIT_ACH2_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH2_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH2_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH2_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH2_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH2_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH2_TXBD_DESA_H_8814B) +#define BITS_ACH2_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH2_TXBD_DESA_H_8814B << BIT_SHIFT_ACH2_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH2_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH2_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH2_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH2_TXBD_DESA_H_8814B) +#define BIT_SET_ACH2_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH2_TXBD_DESA_H_8814B(x) | BIT_ACH2_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH3_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH3_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH3_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH3_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH3_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH3_TXBD_DESA_L_8814B) +#define BITS_ACH3_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH3_TXBD_DESA_L_8814B << BIT_SHIFT_ACH3_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH3_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH3_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH3_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH3_TXBD_DESA_L_8814B) +#define BIT_SET_ACH3_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH3_TXBD_DESA_L_8814B(x) | BIT_ACH3_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH3_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH3_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH3_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH3_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH3_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH3_TXBD_DESA_H_8814B) +#define BITS_ACH3_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH3_TXBD_DESA_H_8814B << BIT_SHIFT_ACH3_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH3_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH3_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH3_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH3_TXBD_DESA_H_8814B) +#define BIT_SET_ACH3_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH3_TXBD_DESA_H_8814B(x) | BIT_ACH3_TXBD_DESA_H_8814B(v)) + +/* 2 REG_P0RXQ_RXBD_DESA_L_8814B */ + +#define BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B 0 +#define BIT_MASK_P0RXQ_RXBD_DESA_L_8814B 0xffffffffL +#define BIT_P0RXQ_RXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_P0RXQ_RXBD_DESA_L_8814B) \ + << BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B) +#define BITS_P0RXQ_RXBD_DESA_L_8814B \ + (BIT_MASK_P0RXQ_RXBD_DESA_L_8814B << BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B) +#define BIT_CLEAR_P0RXQ_RXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_P0RXQ_RXBD_DESA_L_8814B)) +#define BIT_GET_P0RXQ_RXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B) & \ + BIT_MASK_P0RXQ_RXBD_DESA_L_8814B) +#define BIT_SET_P0RXQ_RXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_P0RXQ_RXBD_DESA_L_8814B(x) | BIT_P0RXQ_RXBD_DESA_L_8814B(v)) + +/* 2 REG_P0RXQ_RXBD_DESA_H_8814B */ + +#define BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B 0 +#define BIT_MASK_P0RXQ_RXBD_DESA_H_8814B 0xffffffffL +#define BIT_P0RXQ_RXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_P0RXQ_RXBD_DESA_H_8814B) \ + << BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B) +#define BITS_P0RXQ_RXBD_DESA_H_8814B \ + (BIT_MASK_P0RXQ_RXBD_DESA_H_8814B << BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B) +#define BIT_CLEAR_P0RXQ_RXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_P0RXQ_RXBD_DESA_H_8814B)) +#define BIT_GET_P0RXQ_RXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B) & \ + BIT_MASK_P0RXQ_RXBD_DESA_H_8814B) +#define BIT_SET_P0RXQ_RXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_P0RXQ_RXBD_DESA_H_8814B(x) | BIT_P0RXQ_RXBD_DESA_H_8814B(v)) + +/* 2 REG_P0BCNQ_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B 0 +#define BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_P0BCNQ_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B) +#define BITS_P0BCNQ_TXBD_DESA_L_8814B \ + (BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B \ + << BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B) +#define BIT_CLEAR_P0BCNQ_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_P0BCNQ_TXBD_DESA_L_8814B)) +#define BIT_GET_P0BCNQ_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B) & \ + BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B) +#define BIT_SET_P0BCNQ_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_P0BCNQ_TXBD_DESA_L_8814B(x) | \ + BIT_P0BCNQ_TXBD_DESA_L_8814B(v)) + +/* 2 REG_P0BCNQ_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B 0 +#define BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_P0BCNQ_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B) +#define BITS_P0BCNQ_TXBD_DESA_H_8814B \ + (BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B \ + << BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B) +#define BIT_CLEAR_P0BCNQ_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_P0BCNQ_TXBD_DESA_H_8814B)) +#define BIT_GET_P0BCNQ_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B) & \ + BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B) +#define BIT_SET_P0BCNQ_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_P0BCNQ_TXBD_DESA_H_8814B(x) | \ + BIT_P0BCNQ_TXBD_DESA_H_8814B(v)) + +/* 2 REG_FWCMDQ_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B 0 +#define BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_FWCMDQ_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B) +#define BITS_FWCMDQ_TXBD_DESA_L_8814B \ + (BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B \ + << BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B) +#define BIT_CLEAR_FWCMDQ_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_FWCMDQ_TXBD_DESA_L_8814B)) +#define BIT_GET_FWCMDQ_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B) & \ + BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B) +#define BIT_SET_FWCMDQ_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_TXBD_DESA_L_8814B(x) | \ + BIT_FWCMDQ_TXBD_DESA_L_8814B(v)) + +/* 2 REG_FWCMDQ_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B 0 +#define BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_FWCMDQ_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B) +#define BITS_FWCMDQ_TXBD_DESA_H_8814B \ + (BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B \ + << BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B) +#define BIT_CLEAR_FWCMDQ_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_FWCMDQ_TXBD_DESA_H_8814B)) +#define BIT_GET_FWCMDQ_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B) & \ + BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B) +#define BIT_SET_FWCMDQ_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_TXBD_DESA_H_8814B(x) | \ + BIT_FWCMDQ_TXBD_DESA_H_8814B(v)) + +/* 2 REG_PCIE_HRPWM1_HCPWM1_DCPU_8814B */ + +#define BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B 16 +#define BIT_MASK_PCIE_HCPWM1_DCPU_8814B 0xff +#define BIT_PCIE_HCPWM1_DCPU_8814B(x) \ + (((x) & BIT_MASK_PCIE_HCPWM1_DCPU_8814B) \ + << BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B) +#define BITS_PCIE_HCPWM1_DCPU_8814B \ + (BIT_MASK_PCIE_HCPWM1_DCPU_8814B << BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B) +#define BIT_CLEAR_PCIE_HCPWM1_DCPU_8814B(x) \ + ((x) & (~BITS_PCIE_HCPWM1_DCPU_8814B)) +#define BIT_GET_PCIE_HCPWM1_DCPU_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B) & \ + BIT_MASK_PCIE_HCPWM1_DCPU_8814B) +#define BIT_SET_PCIE_HCPWM1_DCPU_8814B(x, v) \ + (BIT_CLEAR_PCIE_HCPWM1_DCPU_8814B(x) | BIT_PCIE_HCPWM1_DCPU_8814B(v)) + +#define BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B 8 +#define BIT_MASK_PCIE_HRPWM1_DCPU_8814B 0xff +#define BIT_PCIE_HRPWM1_DCPU_8814B(x) \ + (((x) & BIT_MASK_PCIE_HRPWM1_DCPU_8814B) \ + << BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B) +#define BITS_PCIE_HRPWM1_DCPU_8814B \ + (BIT_MASK_PCIE_HRPWM1_DCPU_8814B << BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B) +#define BIT_CLEAR_PCIE_HRPWM1_DCPU_8814B(x) \ + ((x) & (~BITS_PCIE_HRPWM1_DCPU_8814B)) +#define BIT_GET_PCIE_HRPWM1_DCPU_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B) & \ + BIT_MASK_PCIE_HRPWM1_DCPU_8814B) +#define BIT_SET_PCIE_HRPWM1_DCPU_8814B(x, v) \ + (BIT_CLEAR_PCIE_HRPWM1_DCPU_8814B(x) | BIT_PCIE_HRPWM1_DCPU_8814B(v)) + +/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0 +#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) +#define BITS_P0_MPRT_BCNQ_TXBD_DESA_L_8814B \ + (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) +#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)) +#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) & \ + BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) +#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) | \ + BIT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(v)) + +/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0 +#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) +#define BITS_P0_MPRT_BCNQ_TXBD_DESA_H_8814B \ + (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) +#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)) +#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) & \ + BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) +#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) | \ + BIT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(v)) + +/* 2 REG_P0_MPRT_BCNQ_TXRXBD_NUM_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B 13 +#define BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B 0x3 +#define BIT_P0_MPRT_BCNQ_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B) \ + << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B) +#define BITS_P0_MPRT_BCNQ_DESC_MODE_8814B \ + (BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B \ + << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B) +#define BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0_MPRT_BCNQ_DESC_MODE_8814B)) +#define BIT_GET_P0_MPRT_BCNQ_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B) & \ + BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B) +#define BIT_SET_P0_MPRT_BCNQ_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE_8814B(x) | \ + BIT_P0_MPRT_BCNQ_DESC_MODE_8814B(v)) + +#define BIT_PCIE_P0MPRT_BCNQ4_FLAG_8814B BIT(11) +#define BIT_PCIE_P0MPRT_BCNQ3_FLAG_8814B BIT(10) +#define BIT_PCIE_P0MPRT_BCNQ2_FLAG_8814B BIT(9) +#define BIT_PCIE_P0MPRT_BCNQ1_FLAG_8814B BIT(8) +#define BIT_EPHY_CAL_DONE_8814B BIT(1) +#define BIT_RESET_APHY_8814B BIT(0) + +/* 2 REG_BD_RWPTR_CLR2_8814B */ -/* 2 REG_BCNQ_TXBD_DESA_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_ACH7_HW_IDX_8814B BIT(21) +#define BIT_CLR_ACH6_HW_IDX_8814B BIT(20) +#define BIT_CLR_ACH5_HW_IDX_8814B BIT(19) +#define BIT_CLR_ACH4_HW_IDX_8814B BIT(18) -#define BIT_SHIFT_BCNQ_TXBD_DESA_8814B 0 -#define BIT_MASK_BCNQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_BCNQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8814B) << BIT_SHIFT_BCNQ_TXBD_DESA_8814B) -#define BIT_GET_BCNQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8814B) & BIT_MASK_BCNQ_TXBD_DESA_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_ACH7_HOST_IDX_8814B BIT(5) +#define BIT_CLR_ACH6_HOST_IDX_8814B BIT(4) +#define BIT_CLR_ACH5_HOST_IDX_8814B BIT(3) +#define BIT_CLR_ACH4_HOST_IDX_8814B BIT(2) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_BD_RWPTR_CLR3_8814B */ -/* 2 REG_MGQ_TXBD_DESA_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_P0HI15Q_HW_IDX_8814B BIT(29) +#define BIT_CLR_P0HI14Q_HW_IDX_8814B BIT(28) +#define BIT_CLR_P0HI13Q_HW_IDX_8814B BIT(27) +#define BIT_CLR_P0HI12Q_HW_IDX_8814B BIT(26) +#define BIT_CLR_P0HI11Q_HW_IDX_8814B BIT(25) +#define BIT_CLR_P0HI10Q_HW_IDX_8814B BIT(24) +#define BIT_CLR_P0HI9Q_HW_IDX_8814B BIT(23) +#define BIT_CLR_P0HI8Q_HW_IDX_8814B BIT(22) +#define BIT_CLR_ACH13_HW_IDX_8814B BIT(21) +#define BIT_CLR_ACH12_HW_IDX_8814B BIT(20) +#define BIT_CLR_ACH11_HW_IDX_8814B BIT(19) +#define BIT_CLR_ACH10_HW_IDX_8814B BIT(18) +#define BIT_CLR_ACH9_HW_IDX_8814B BIT(17) +#define BIT_CLR_ACH8_HW_IDX_8814B BIT(16) -#define BIT_SHIFT_MGQ_TXBD_DESA_8814B 0 -#define BIT_MASK_MGQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_MGQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8814B) << BIT_SHIFT_MGQ_TXBD_DESA_8814B) -#define BIT_GET_MGQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8814B) & BIT_MASK_MGQ_TXBD_DESA_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_P0HI15Q_HOST_IDX_8814B BIT(13) +#define BIT_CLR_P0HI14Q_HOST_IDX_8814B BIT(12) +#define BIT_CLR_P0HI13Q_HOST_IDX_8814B BIT(11) +#define BIT_CLR_P0HI12Q_HOST_IDX_8814B BIT(10) +#define BIT_CLR_P0HI11Q_HOST_IDX_8814B BIT(9) +#define BIT_CLR_P0HI10Q_HOST_IDX_8814B BIT(8) +#define BIT_CLR_P0HI9Q_HOST_IDX_8814B BIT(7) +#define BIT_CLR_P0HI8Q_HOST_IDX_8814B BIT(6) +#define BIT_CLR_ACH13_HOST_IDX_8814B BIT(5) +#define BIT_CLR_ACH12_HOST_IDX_8814B BIT(4) +#define BIT_CLR_ACH11_HOST_IDX_8814B BIT(3) +#define BIT_CLR_ACH10_HOST_IDX_8814B BIT(2) +#define BIT_CLR_ACH9_HOST_IDX_8814B BIT(1) +#define BIT_CLR_ACH8_HOST_IDX_8814B BIT(0) + +/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM_8814B */ +#define BIT_SYS_32_64_V1_8814B BIT(31) + +#define BIT_SHIFT_P0BCNQ_DESC_MODE_8814B 29 +#define BIT_MASK_P0BCNQ_DESC_MODE_8814B 0x3 +#define BIT_P0BCNQ_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0BCNQ_DESC_MODE_8814B) \ + << BIT_SHIFT_P0BCNQ_DESC_MODE_8814B) +#define BITS_P0BCNQ_DESC_MODE_8814B \ + (BIT_MASK_P0BCNQ_DESC_MODE_8814B << BIT_SHIFT_P0BCNQ_DESC_MODE_8814B) +#define BIT_CLEAR_P0BCNQ_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0BCNQ_DESC_MODE_8814B)) +#define BIT_GET_P0BCNQ_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0BCNQ_DESC_MODE_8814B) & \ + BIT_MASK_P0BCNQ_DESC_MODE_8814B) +#define BIT_SET_P0BCNQ_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0BCNQ_DESC_MODE_8814B(x) | BIT_P0BCNQ_DESC_MODE_8814B(v)) + +#define BIT_PCIE_P0BCNQ_FLAG_8814B BIT(28) + +#define BIT_SHIFT_P0RXQ_DESC_NUM_8814B 16 +#define BIT_MASK_P0RXQ_DESC_NUM_8814B 0xfff +#define BIT_P0RXQ_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0RXQ_DESC_NUM_8814B) \ + << BIT_SHIFT_P0RXQ_DESC_NUM_8814B) +#define BITS_P0RXQ_DESC_NUM_8814B \ + (BIT_MASK_P0RXQ_DESC_NUM_8814B << BIT_SHIFT_P0RXQ_DESC_NUM_8814B) +#define BIT_CLEAR_P0RXQ_DESC_NUM_8814B(x) ((x) & (~BITS_P0RXQ_DESC_NUM_8814B)) +#define BIT_GET_P0RXQ_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0RXQ_DESC_NUM_8814B) & \ + BIT_MASK_P0RXQ_DESC_NUM_8814B) +#define BIT_SET_P0RXQ_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0RXQ_DESC_NUM_8814B(x) | BIT_P0RXQ_DESC_NUM_8814B(v)) + +#define BIT_PCIE_P0MGQ_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0MGQ_DESC_MODE_8814B 12 +#define BIT_MASK_P0MGQ_DESC_MODE_8814B 0x3 +#define BIT_P0MGQ_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0MGQ_DESC_MODE_8814B) \ + << BIT_SHIFT_P0MGQ_DESC_MODE_8814B) +#define BITS_P0MGQ_DESC_MODE_8814B \ + (BIT_MASK_P0MGQ_DESC_MODE_8814B << BIT_SHIFT_P0MGQ_DESC_MODE_8814B) +#define BIT_CLEAR_P0MGQ_DESC_MODE_8814B(x) ((x) & (~BITS_P0MGQ_DESC_MODE_8814B)) +#define BIT_GET_P0MGQ_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0MGQ_DESC_MODE_8814B) & \ + BIT_MASK_P0MGQ_DESC_MODE_8814B) +#define BIT_SET_P0MGQ_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0MGQ_DESC_MODE_8814B(x) | BIT_P0MGQ_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0MGQ_DESC_NUM_8814B 0 +#define BIT_MASK_P0MGQ_DESC_NUM_8814B 0xfff +#define BIT_P0MGQ_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0MGQ_DESC_NUM_8814B) \ + << BIT_SHIFT_P0MGQ_DESC_NUM_8814B) +#define BITS_P0MGQ_DESC_NUM_8814B \ + (BIT_MASK_P0MGQ_DESC_NUM_8814B << BIT_SHIFT_P0MGQ_DESC_NUM_8814B) +#define BIT_CLEAR_P0MGQ_DESC_NUM_8814B(x) ((x) & (~BITS_P0MGQ_DESC_NUM_8814B)) +#define BIT_GET_P0MGQ_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0MGQ_DESC_NUM_8814B) & \ + BIT_MASK_P0MGQ_DESC_NUM_8814B) +#define BIT_SET_P0MGQ_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0MGQ_DESC_NUM_8814B(x) | BIT_P0MGQ_DESC_NUM_8814B(v)) + +/* 2 REG_CHNL_DMA_CFG_8814B */ +#define BIT_TXHCI_EN_8814B BIT(26) +#define BIT_TXHCI_IDLE_8814B BIT(25) +#define BIT_DMA_PRI_EN_8814B BIT(24) + +/* 2 REG_FWCMDQ_TXBD_NUM_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_PCIE_FWCMDQ_FLAG_8814B BIT(14) + +#define BIT_SHIFT_FWCMDQ_DESC_MODE_8814B 12 +#define BIT_MASK_FWCMDQ_DESC_MODE_8814B 0x3 +#define BIT_FWCMDQ_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_DESC_MODE_8814B) \ + << BIT_SHIFT_FWCMDQ_DESC_MODE_8814B) +#define BITS_FWCMDQ_DESC_MODE_8814B \ + (BIT_MASK_FWCMDQ_DESC_MODE_8814B << BIT_SHIFT_FWCMDQ_DESC_MODE_8814B) +#define BIT_CLEAR_FWCMDQ_DESC_MODE_8814B(x) \ + ((x) & (~BITS_FWCMDQ_DESC_MODE_8814B)) +#define BIT_GET_FWCMDQ_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_DESC_MODE_8814B) & \ + BIT_MASK_FWCMDQ_DESC_MODE_8814B) +#define BIT_SET_FWCMDQ_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_DESC_MODE_8814B(x) | BIT_FWCMDQ_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_FWCMDQ_DESC_NUM_8814B 0 +#define BIT_MASK_FWCMDQ_DESC_NUM_8814B 0xfff +#define BIT_FWCMDQ_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_DESC_NUM_8814B) \ + << BIT_SHIFT_FWCMDQ_DESC_NUM_8814B) +#define BITS_FWCMDQ_DESC_NUM_8814B \ + (BIT_MASK_FWCMDQ_DESC_NUM_8814B << BIT_SHIFT_FWCMDQ_DESC_NUM_8814B) +#define BIT_CLEAR_FWCMDQ_DESC_NUM_8814B(x) ((x) & (~BITS_FWCMDQ_DESC_NUM_8814B)) +#define BIT_GET_FWCMDQ_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_DESC_NUM_8814B) & \ + BIT_MASK_FWCMDQ_DESC_NUM_8814B) +#define BIT_SET_FWCMDQ_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_DESC_NUM_8814B(x) | BIT_FWCMDQ_DESC_NUM_8814B(v)) + +/* 2 REG_ACH0_ACH1_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH1_FLAG_V1_8814B BIT(30) + +#define BIT_SHIFT_ACH1_DESC_MODE_V1_8814B 28 +#define BIT_MASK_ACH1_DESC_MODE_V1_8814B 0x3 +#define BIT_ACH1_DESC_MODE_V1_8814B(x) \ + (((x) & BIT_MASK_ACH1_DESC_MODE_V1_8814B) \ + << BIT_SHIFT_ACH1_DESC_MODE_V1_8814B) +#define BITS_ACH1_DESC_MODE_V1_8814B \ + (BIT_MASK_ACH1_DESC_MODE_V1_8814B << BIT_SHIFT_ACH1_DESC_MODE_V1_8814B) +#define BIT_CLEAR_ACH1_DESC_MODE_V1_8814B(x) \ + ((x) & (~BITS_ACH1_DESC_MODE_V1_8814B)) +#define BIT_GET_ACH1_DESC_MODE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_ACH1_DESC_MODE_V1_8814B) & \ + BIT_MASK_ACH1_DESC_MODE_V1_8814B) +#define BIT_SET_ACH1_DESC_MODE_V1_8814B(x, v) \ + (BIT_CLEAR_ACH1_DESC_MODE_V1_8814B(x) | BIT_ACH1_DESC_MODE_V1_8814B(v)) + +#define BIT_SHIFT_ACH1_DESC_NUM_V1_8814B 16 +#define BIT_MASK_ACH1_DESC_NUM_V1_8814B 0xfff +#define BIT_ACH1_DESC_NUM_V1_8814B(x) \ + (((x) & BIT_MASK_ACH1_DESC_NUM_V1_8814B) \ + << BIT_SHIFT_ACH1_DESC_NUM_V1_8814B) +#define BITS_ACH1_DESC_NUM_V1_8814B \ + (BIT_MASK_ACH1_DESC_NUM_V1_8814B << BIT_SHIFT_ACH1_DESC_NUM_V1_8814B) +#define BIT_CLEAR_ACH1_DESC_NUM_V1_8814B(x) \ + ((x) & (~BITS_ACH1_DESC_NUM_V1_8814B)) +#define BIT_GET_ACH1_DESC_NUM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_ACH1_DESC_NUM_V1_8814B) & \ + BIT_MASK_ACH1_DESC_NUM_V1_8814B) +#define BIT_SET_ACH1_DESC_NUM_V1_8814B(x, v) \ + (BIT_CLEAR_ACH1_DESC_NUM_V1_8814B(x) | BIT_ACH1_DESC_NUM_V1_8814B(v)) + +#define BIT_PCIE_ACH0_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH0_DESC_MODE_8814B 12 +#define BIT_MASK_ACH0_DESC_MODE_8814B 0x3 +#define BIT_ACH0_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH0_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH0_DESC_MODE_8814B) +#define BITS_ACH0_DESC_MODE_8814B \ + (BIT_MASK_ACH0_DESC_MODE_8814B << BIT_SHIFT_ACH0_DESC_MODE_8814B) +#define BIT_CLEAR_ACH0_DESC_MODE_8814B(x) ((x) & (~BITS_ACH0_DESC_MODE_8814B)) +#define BIT_GET_ACH0_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH0_DESC_MODE_8814B) & \ + BIT_MASK_ACH0_DESC_MODE_8814B) +#define BIT_SET_ACH0_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH0_DESC_MODE_8814B(x) | BIT_ACH0_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH0_DESC_NUM_8814B 0 +#define BIT_MASK_ACH0_DESC_NUM_8814B 0xfff +#define BIT_ACH0_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH0_DESC_NUM_8814B) << BIT_SHIFT_ACH0_DESC_NUM_8814B) +#define BITS_ACH0_DESC_NUM_8814B \ + (BIT_MASK_ACH0_DESC_NUM_8814B << BIT_SHIFT_ACH0_DESC_NUM_8814B) +#define BIT_CLEAR_ACH0_DESC_NUM_8814B(x) ((x) & (~BITS_ACH0_DESC_NUM_8814B)) +#define BIT_GET_ACH0_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH0_DESC_NUM_8814B) & BIT_MASK_ACH0_DESC_NUM_8814B) +#define BIT_SET_ACH0_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH0_DESC_NUM_8814B(x) | BIT_ACH0_DESC_NUM_8814B(v)) + +/* 2 REG_ACH2_ACH3_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH3_FLAG_V1_8814B BIT(30) + +#define BIT_SHIFT_ACH3_DESC_MODE_V1_8814B 28 +#define BIT_MASK_ACH3_DESC_MODE_V1_8814B 0x3 +#define BIT_ACH3_DESC_MODE_V1_8814B(x) \ + (((x) & BIT_MASK_ACH3_DESC_MODE_V1_8814B) \ + << BIT_SHIFT_ACH3_DESC_MODE_V1_8814B) +#define BITS_ACH3_DESC_MODE_V1_8814B \ + (BIT_MASK_ACH3_DESC_MODE_V1_8814B << BIT_SHIFT_ACH3_DESC_MODE_V1_8814B) +#define BIT_CLEAR_ACH3_DESC_MODE_V1_8814B(x) \ + ((x) & (~BITS_ACH3_DESC_MODE_V1_8814B)) +#define BIT_GET_ACH3_DESC_MODE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_ACH3_DESC_MODE_V1_8814B) & \ + BIT_MASK_ACH3_DESC_MODE_V1_8814B) +#define BIT_SET_ACH3_DESC_MODE_V1_8814B(x, v) \ + (BIT_CLEAR_ACH3_DESC_MODE_V1_8814B(x) | BIT_ACH3_DESC_MODE_V1_8814B(v)) + +#define BIT_SHIFT_ACH3_DESC_NUM_V1_8814B 16 +#define BIT_MASK_ACH3_DESC_NUM_V1_8814B 0xfff +#define BIT_ACH3_DESC_NUM_V1_8814B(x) \ + (((x) & BIT_MASK_ACH3_DESC_NUM_V1_8814B) \ + << BIT_SHIFT_ACH3_DESC_NUM_V1_8814B) +#define BITS_ACH3_DESC_NUM_V1_8814B \ + (BIT_MASK_ACH3_DESC_NUM_V1_8814B << BIT_SHIFT_ACH3_DESC_NUM_V1_8814B) +#define BIT_CLEAR_ACH3_DESC_NUM_V1_8814B(x) \ + ((x) & (~BITS_ACH3_DESC_NUM_V1_8814B)) +#define BIT_GET_ACH3_DESC_NUM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_ACH3_DESC_NUM_V1_8814B) & \ + BIT_MASK_ACH3_DESC_NUM_V1_8814B) +#define BIT_SET_ACH3_DESC_NUM_V1_8814B(x, v) \ + (BIT_CLEAR_ACH3_DESC_NUM_V1_8814B(x) | BIT_ACH3_DESC_NUM_V1_8814B(v)) + +#define BIT_PCIE_ACH2_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH2_DESC_MODE_8814B 12 +#define BIT_MASK_ACH2_DESC_MODE_8814B 0x3 +#define BIT_ACH2_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH2_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH2_DESC_MODE_8814B) +#define BITS_ACH2_DESC_MODE_8814B \ + (BIT_MASK_ACH2_DESC_MODE_8814B << BIT_SHIFT_ACH2_DESC_MODE_8814B) +#define BIT_CLEAR_ACH2_DESC_MODE_8814B(x) ((x) & (~BITS_ACH2_DESC_MODE_8814B)) +#define BIT_GET_ACH2_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH2_DESC_MODE_8814B) & \ + BIT_MASK_ACH2_DESC_MODE_8814B) +#define BIT_SET_ACH2_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH2_DESC_MODE_8814B(x) | BIT_ACH2_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH2_DESC_NUM_8814B 0 +#define BIT_MASK_ACH2_DESC_NUM_8814B 0xfff +#define BIT_ACH2_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH2_DESC_NUM_8814B) << BIT_SHIFT_ACH2_DESC_NUM_8814B) +#define BITS_ACH2_DESC_NUM_8814B \ + (BIT_MASK_ACH2_DESC_NUM_8814B << BIT_SHIFT_ACH2_DESC_NUM_8814B) +#define BIT_CLEAR_ACH2_DESC_NUM_8814B(x) ((x) & (~BITS_ACH2_DESC_NUM_8814B)) +#define BIT_GET_ACH2_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH2_DESC_NUM_8814B) & BIT_MASK_ACH2_DESC_NUM_8814B) +#define BIT_SET_ACH2_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH2_DESC_NUM_8814B(x) | BIT_ACH2_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM_8814B */ +#define BIT_P0HI1Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI1Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI1Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI1Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI1Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI1Q_DESC_MODE_8814B) +#define BITS_P0HI1Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI1Q_DESC_MODE_8814B << BIT_SHIFT_P0HI1Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI1Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI1Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI1Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI1Q_DESC_MODE_8814B) +#define BIT_SET_P0HI1Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI1Q_DESC_MODE_8814B(x) | BIT_P0HI1Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI1Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI1Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI1Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI1Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI1Q_DESC_NUM_8814B) +#define BITS_P0HI1Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI1Q_DESC_NUM_8814B << BIT_SHIFT_P0HI1Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI1Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI1Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI1Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI1Q_DESC_NUM_8814B) +#define BIT_SET_P0HI1Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI1Q_DESC_NUM_8814B(x) | BIT_P0HI1Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI0Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI0Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI0Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI0Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI0Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI0Q_DESC_MODE_8814B) +#define BITS_P0HI0Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI0Q_DESC_MODE_8814B << BIT_SHIFT_P0HI0Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI0Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI0Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI0Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI0Q_DESC_MODE_8814B) +#define BIT_SET_P0HI0Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI0Q_DESC_MODE_8814B(x) | BIT_P0HI0Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI0Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI0Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI0Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI0Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI0Q_DESC_NUM_8814B) +#define BITS_P0HI0Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI0Q_DESC_NUM_8814B << BIT_SHIFT_P0HI0Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI0Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI0Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI0Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI0Q_DESC_NUM_8814B) +#define BIT_SET_P0HI0Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI0Q_DESC_NUM_8814B(x) | BIT_P0HI0Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM_8814B */ +#define BIT_P0HI3Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI3Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI3Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI3Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI3Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI3Q_DESC_MODE_8814B) +#define BITS_P0HI3Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI3Q_DESC_MODE_8814B << BIT_SHIFT_P0HI3Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI3Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI3Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI3Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI3Q_DESC_MODE_8814B) +#define BIT_SET_P0HI3Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI3Q_DESC_MODE_8814B(x) | BIT_P0HI3Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI3Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI3Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI3Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI3Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI3Q_DESC_NUM_8814B) +#define BITS_P0HI3Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI3Q_DESC_NUM_8814B << BIT_SHIFT_P0HI3Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI3Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI3Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI3Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI3Q_DESC_NUM_8814B) +#define BIT_SET_P0HI3Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI3Q_DESC_NUM_8814B(x) | BIT_P0HI3Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI2Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI2Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI2Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI2Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI2Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI2Q_DESC_MODE_8814B) +#define BITS_P0HI2Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI2Q_DESC_MODE_8814B << BIT_SHIFT_P0HI2Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI2Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI2Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI2Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI2Q_DESC_MODE_8814B) +#define BIT_SET_P0HI2Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI2Q_DESC_MODE_8814B(x) | BIT_P0HI2Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI2Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI2Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI2Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI2Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI2Q_DESC_NUM_8814B) +#define BITS_P0HI2Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI2Q_DESC_NUM_8814B << BIT_SHIFT_P0HI2Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI2Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI2Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI2Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI2Q_DESC_NUM_8814B) +#define BIT_SET_P0HI2Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI2Q_DESC_NUM_8814B(x) | BIT_P0HI2Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM_8814B */ +#define BIT_P0HI5Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI5Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI5Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI5Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI5Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI5Q_DESC_MODE_8814B) +#define BITS_P0HI5Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI5Q_DESC_MODE_8814B << BIT_SHIFT_P0HI5Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI5Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI5Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI5Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI5Q_DESC_MODE_8814B) +#define BIT_SET_P0HI5Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI5Q_DESC_MODE_8814B(x) | BIT_P0HI5Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI5Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI5Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI5Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI5Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI5Q_DESC_NUM_8814B) +#define BITS_P0HI5Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI5Q_DESC_NUM_8814B << BIT_SHIFT_P0HI5Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI5Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI5Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI5Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI5Q_DESC_NUM_8814B) +#define BIT_SET_P0HI5Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI5Q_DESC_NUM_8814B(x) | BIT_P0HI5Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI4Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI4Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI4Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI4Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI4Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI4Q_DESC_MODE_8814B) +#define BITS_P0HI4Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI4Q_DESC_MODE_8814B << BIT_SHIFT_P0HI4Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI4Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI4Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI4Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI4Q_DESC_MODE_8814B) +#define BIT_SET_P0HI4Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI4Q_DESC_MODE_8814B(x) | BIT_P0HI4Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI4Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI4Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI4Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI4Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI4Q_DESC_NUM_8814B) +#define BITS_P0HI4Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI4Q_DESC_NUM_8814B << BIT_SHIFT_P0HI4Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI4Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI4Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI4Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI4Q_DESC_NUM_8814B) +#define BIT_SET_P0HI4Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI4Q_DESC_NUM_8814B(x) | BIT_P0HI4Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM_8814B */ +#define BIT_P0HI7Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI7Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI7Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI7Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI7Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI7Q_DESC_MODE_8814B) +#define BITS_P0HI7Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI7Q_DESC_MODE_8814B << BIT_SHIFT_P0HI7Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI7Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI7Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI7Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI7Q_DESC_MODE_8814B) +#define BIT_SET_P0HI7Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI7Q_DESC_MODE_8814B(x) | BIT_P0HI7Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI7Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI7Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI7Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI7Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI7Q_DESC_NUM_8814B) +#define BITS_P0HI7Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI7Q_DESC_NUM_8814B << BIT_SHIFT_P0HI7Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI7Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI7Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI7Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI7Q_DESC_NUM_8814B) +#define BIT_SET_P0HI7Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI7Q_DESC_NUM_8814B(x) | BIT_P0HI7Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI6Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI6Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI6Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI6Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI6Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI6Q_DESC_MODE_8814B) +#define BITS_P0HI6Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI6Q_DESC_MODE_8814B << BIT_SHIFT_P0HI6Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI6Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI6Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI6Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI6Q_DESC_MODE_8814B) +#define BIT_SET_P0HI6Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI6Q_DESC_MODE_8814B(x) | BIT_P0HI6Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI6Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI6Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI6Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI6Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI6Q_DESC_NUM_8814B) +#define BITS_P0HI6Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI6Q_DESC_NUM_8814B << BIT_SHIFT_P0HI6Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI6Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI6Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI6Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI6Q_DESC_NUM_8814B) +#define BIT_SET_P0HI6Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI6Q_DESC_NUM_8814B(x) | BIT_P0HI6Q_DESC_NUM_8814B(v)) + +/* 2 REG_BD_RWPTR_CLR1_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_FWCMDQ_HW_IDX_8814B BIT(30) +#define BIT_CLR_P0HI7Q_HW_IDX_8814B BIT(29) +#define BIT_CLR_P0HI6Q_HW_IDX_8814B BIT(28) +#define BIT_CLR_P0HI5Q_HW_IDX_8814B BIT(27) +#define BIT_CLR_P0HI4Q_HW_IDX_8814B BIT(26) +#define BIT_CLR_P0HI3Q_HW_IDX_8814B BIT(25) +#define BIT_CLR_P0HI2Q_HW_IDX_8814B BIT(24) +#define BIT_CLR_P0HI1Q_HW_IDX_8814B BIT(23) +#define BIT_CLR_P0HI0Q_HW_IDX_8814B BIT(22) +#define BIT_CLR_ACH3_HW_IDX_8814B BIT(21) +#define BIT_CLR_ACH2_HW_IDX_8814B BIT(20) +#define BIT_CLR_ACH1_HW_IDX_8814B BIT(19) +#define BIT_CLR_ACH0_HW_IDX_8814B BIT(18) +#define BIT_CLR_P0MGQ_HW_IDX_8814B BIT(17) +#define BIT_CLR_P0RXQ_HW_IDX_8814B BIT(16) -/* 2 REG_VOQ_TXBD_DESA_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_PFWCMDQ_HOST_IDX_8814B BIT(14) +#define BIT_CLR_P0HI7Q_HOST_IDX_8814B BIT(13) +#define BIT_CLR_P0HI6Q_HOST_IDX_8814B BIT(12) +#define BIT_CLR_P0HI5Q_HOST_IDX_8814B BIT(11) +#define BIT_CLR_P0HI4Q_HOST_IDX_8814B BIT(10) +#define BIT_CLR_P0HI3Q_HOST_IDX_8814B BIT(9) +#define BIT_CLR_P0HI2Q_HOST_IDX_8814B BIT(8) +#define BIT_CLR_P0HI1Q_HOST_IDX_8814B BIT(7) +#define BIT_CLR_P0HI0Q_HOST_IDX_8814B BIT(6) +#define BIT_CLR_ACH3_HOST_IDX_8814B BIT(5) +#define BIT_CLR_ACH2_HOST_IDX_8814B BIT(4) +#define BIT_CLR_ACH1_HOST_IDX_8814B BIT(3) +#define BIT_CLR_ACH0_HOST_IDX_8814B BIT(2) +#define BIT_CLR_P0MGQ_HOST_IDX_8814B BIT(1) +#define BIT_CLR_P0RXQ_HOST_IDX_8814B BIT(0) -#define BIT_SHIFT_VOQ_TXBD_DESA_8814B 0 -#define BIT_MASK_VOQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_VOQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8814B) << BIT_SHIFT_VOQ_TXBD_DESA_8814B) -#define BIT_GET_VOQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8814B) & BIT_MASK_VOQ_TXBD_DESA_8814B) +/* 2 REG_TSFTIMER_HCI_8814B */ +#define BIT_SHIFT_TSFT2_HCI_8814B 16 +#define BIT_MASK_TSFT2_HCI_8814B 0xffff +#define BIT_TSFT2_HCI_8814B(x) \ + (((x) & BIT_MASK_TSFT2_HCI_8814B) << BIT_SHIFT_TSFT2_HCI_8814B) +#define BITS_TSFT2_HCI_8814B \ + (BIT_MASK_TSFT2_HCI_8814B << BIT_SHIFT_TSFT2_HCI_8814B) +#define BIT_CLEAR_TSFT2_HCI_8814B(x) ((x) & (~BITS_TSFT2_HCI_8814B)) +#define BIT_GET_TSFT2_HCI_8814B(x) \ + (((x) >> BIT_SHIFT_TSFT2_HCI_8814B) & BIT_MASK_TSFT2_HCI_8814B) +#define BIT_SET_TSFT2_HCI_8814B(x, v) \ + (BIT_CLEAR_TSFT2_HCI_8814B(x) | BIT_TSFT2_HCI_8814B(v)) +#define BIT_SHIFT_TSFT1_HCI_8814B 0 +#define BIT_MASK_TSFT1_HCI_8814B 0xffff +#define BIT_TSFT1_HCI_8814B(x) \ + (((x) & BIT_MASK_TSFT1_HCI_8814B) << BIT_SHIFT_TSFT1_HCI_8814B) +#define BITS_TSFT1_HCI_8814B \ + (BIT_MASK_TSFT1_HCI_8814B << BIT_SHIFT_TSFT1_HCI_8814B) +#define BIT_CLEAR_TSFT1_HCI_8814B(x) ((x) & (~BITS_TSFT1_HCI_8814B)) +#define BIT_GET_TSFT1_HCI_8814B(x) \ + (((x) >> BIT_SHIFT_TSFT1_HCI_8814B) & BIT_MASK_TSFT1_HCI_8814B) +#define BIT_SET_TSFT1_HCI_8814B(x, v) \ + (BIT_CLEAR_TSFT1_HCI_8814B(x) | BIT_TSFT1_HCI_8814B(v)) + +/* 2 REG_ACH0_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH0_HW_IDX_8814B 16 +#define BIT_MASK_ACH0_HW_IDX_8814B 0xfff +#define BIT_ACH0_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH0_HW_IDX_8814B) << BIT_SHIFT_ACH0_HW_IDX_8814B) +#define BITS_ACH0_HW_IDX_8814B \ + (BIT_MASK_ACH0_HW_IDX_8814B << BIT_SHIFT_ACH0_HW_IDX_8814B) +#define BIT_CLEAR_ACH0_HW_IDX_8814B(x) ((x) & (~BITS_ACH0_HW_IDX_8814B)) +#define BIT_GET_ACH0_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH0_HW_IDX_8814B) & BIT_MASK_ACH0_HW_IDX_8814B) +#define BIT_SET_ACH0_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH0_HW_IDX_8814B(x) | BIT_ACH0_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH0_HOST_IDX_8814B 0 +#define BIT_MASK_ACH0_HOST_IDX_8814B 0xfff +#define BIT_ACH0_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH0_HOST_IDX_8814B) << BIT_SHIFT_ACH0_HOST_IDX_8814B) +#define BITS_ACH0_HOST_IDX_8814B \ + (BIT_MASK_ACH0_HOST_IDX_8814B << BIT_SHIFT_ACH0_HOST_IDX_8814B) +#define BIT_CLEAR_ACH0_HOST_IDX_8814B(x) ((x) & (~BITS_ACH0_HOST_IDX_8814B)) +#define BIT_GET_ACH0_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH0_HOST_IDX_8814B) & BIT_MASK_ACH0_HOST_IDX_8814B) +#define BIT_SET_ACH0_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH0_HOST_IDX_8814B(x) | BIT_ACH0_HOST_IDX_8814B(v)) + +/* 2 REG_ACH1_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH1_HW_IDX_8814B 16 +#define BIT_MASK_ACH1_HW_IDX_8814B 0xfff +#define BIT_ACH1_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH1_HW_IDX_8814B) << BIT_SHIFT_ACH1_HW_IDX_8814B) +#define BITS_ACH1_HW_IDX_8814B \ + (BIT_MASK_ACH1_HW_IDX_8814B << BIT_SHIFT_ACH1_HW_IDX_8814B) +#define BIT_CLEAR_ACH1_HW_IDX_8814B(x) ((x) & (~BITS_ACH1_HW_IDX_8814B)) +#define BIT_GET_ACH1_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH1_HW_IDX_8814B) & BIT_MASK_ACH1_HW_IDX_8814B) +#define BIT_SET_ACH1_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH1_HW_IDX_8814B(x) | BIT_ACH1_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH1_HOST_IDX_8814B 0 +#define BIT_MASK_ACH1_HOST_IDX_8814B 0xfff +#define BIT_ACH1_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH1_HOST_IDX_8814B) << BIT_SHIFT_ACH1_HOST_IDX_8814B) +#define BITS_ACH1_HOST_IDX_8814B \ + (BIT_MASK_ACH1_HOST_IDX_8814B << BIT_SHIFT_ACH1_HOST_IDX_8814B) +#define BIT_CLEAR_ACH1_HOST_IDX_8814B(x) ((x) & (~BITS_ACH1_HOST_IDX_8814B)) +#define BIT_GET_ACH1_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH1_HOST_IDX_8814B) & BIT_MASK_ACH1_HOST_IDX_8814B) +#define BIT_SET_ACH1_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH1_HOST_IDX_8814B(x) | BIT_ACH1_HOST_IDX_8814B(v)) + +/* 2 REG_ACH2_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH2_HW_IDX_8814B 16 +#define BIT_MASK_ACH2_HW_IDX_8814B 0xfff +#define BIT_ACH2_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH2_HW_IDX_8814B) << BIT_SHIFT_ACH2_HW_IDX_8814B) +#define BITS_ACH2_HW_IDX_8814B \ + (BIT_MASK_ACH2_HW_IDX_8814B << BIT_SHIFT_ACH2_HW_IDX_8814B) +#define BIT_CLEAR_ACH2_HW_IDX_8814B(x) ((x) & (~BITS_ACH2_HW_IDX_8814B)) +#define BIT_GET_ACH2_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH2_HW_IDX_8814B) & BIT_MASK_ACH2_HW_IDX_8814B) +#define BIT_SET_ACH2_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH2_HW_IDX_8814B(x) | BIT_ACH2_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH2_HOST_IDX_8814B 0 +#define BIT_MASK_ACH2_HOST_IDX_8814B 0xfff +#define BIT_ACH2_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH2_HOST_IDX_8814B) << BIT_SHIFT_ACH2_HOST_IDX_8814B) +#define BITS_ACH2_HOST_IDX_8814B \ + (BIT_MASK_ACH2_HOST_IDX_8814B << BIT_SHIFT_ACH2_HOST_IDX_8814B) +#define BIT_CLEAR_ACH2_HOST_IDX_8814B(x) ((x) & (~BITS_ACH2_HOST_IDX_8814B)) +#define BIT_GET_ACH2_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH2_HOST_IDX_8814B) & BIT_MASK_ACH2_HOST_IDX_8814B) +#define BIT_SET_ACH2_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH2_HOST_IDX_8814B(x) | BIT_ACH2_HOST_IDX_8814B(v)) + +/* 2 REG_ACH3_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH3_HW_IDX_8814B 16 +#define BIT_MASK_ACH3_HW_IDX_8814B 0xfff +#define BIT_ACH3_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH3_HW_IDX_8814B) << BIT_SHIFT_ACH3_HW_IDX_8814B) +#define BITS_ACH3_HW_IDX_8814B \ + (BIT_MASK_ACH3_HW_IDX_8814B << BIT_SHIFT_ACH3_HW_IDX_8814B) +#define BIT_CLEAR_ACH3_HW_IDX_8814B(x) ((x) & (~BITS_ACH3_HW_IDX_8814B)) +#define BIT_GET_ACH3_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH3_HW_IDX_8814B) & BIT_MASK_ACH3_HW_IDX_8814B) +#define BIT_SET_ACH3_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH3_HW_IDX_8814B(x) | BIT_ACH3_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH3_HOST_IDX_8814B 0 +#define BIT_MASK_ACH3_HOST_IDX_8814B 0xfff +#define BIT_ACH3_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH3_HOST_IDX_8814B) << BIT_SHIFT_ACH3_HOST_IDX_8814B) +#define BITS_ACH3_HOST_IDX_8814B \ + (BIT_MASK_ACH3_HOST_IDX_8814B << BIT_SHIFT_ACH3_HOST_IDX_8814B) +#define BIT_CLEAR_ACH3_HOST_IDX_8814B(x) ((x) & (~BITS_ACH3_HOST_IDX_8814B)) +#define BIT_GET_ACH3_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH3_HOST_IDX_8814B) & BIT_MASK_ACH3_HOST_IDX_8814B) +#define BIT_SET_ACH3_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH3_HOST_IDX_8814B(x) | BIT_ACH3_HOST_IDX_8814B(v)) + +/* 2 REG_P0MGQ_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0MGQ_HW_IDX_8814B 16 +#define BIT_MASK_P0MGQ_HW_IDX_8814B 0xfff +#define BIT_P0MGQ_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0MGQ_HW_IDX_8814B) << BIT_SHIFT_P0MGQ_HW_IDX_8814B) +#define BITS_P0MGQ_HW_IDX_8814B \ + (BIT_MASK_P0MGQ_HW_IDX_8814B << BIT_SHIFT_P0MGQ_HW_IDX_8814B) +#define BIT_CLEAR_P0MGQ_HW_IDX_8814B(x) ((x) & (~BITS_P0MGQ_HW_IDX_8814B)) +#define BIT_GET_P0MGQ_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0MGQ_HW_IDX_8814B) & BIT_MASK_P0MGQ_HW_IDX_8814B) +#define BIT_SET_P0MGQ_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0MGQ_HW_IDX_8814B(x) | BIT_P0MGQ_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0MGQ_HOST_IDX_8814B 0 +#define BIT_MASK_P0MGQ_HOST_IDX_8814B 0xfff +#define BIT_P0MGQ_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0MGQ_HOST_IDX_8814B) \ + << BIT_SHIFT_P0MGQ_HOST_IDX_8814B) +#define BITS_P0MGQ_HOST_IDX_8814B \ + (BIT_MASK_P0MGQ_HOST_IDX_8814B << BIT_SHIFT_P0MGQ_HOST_IDX_8814B) +#define BIT_CLEAR_P0MGQ_HOST_IDX_8814B(x) ((x) & (~BITS_P0MGQ_HOST_IDX_8814B)) +#define BIT_GET_P0MGQ_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0MGQ_HOST_IDX_8814B) & \ + BIT_MASK_P0MGQ_HOST_IDX_8814B) +#define BIT_SET_P0MGQ_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0MGQ_HOST_IDX_8814B(x) | BIT_P0MGQ_HOST_IDX_8814B(v)) + +/* 2 REG_P0RXQ_RXBD_IDX_8814B */ + +#define BIT_SHIFT_P0RXQ_HW_IDX_8814B 16 +#define BIT_MASK_P0RXQ_HW_IDX_8814B 0xfff +#define BIT_P0RXQ_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0RXQ_HW_IDX_8814B) << BIT_SHIFT_P0RXQ_HW_IDX_8814B) +#define BITS_P0RXQ_HW_IDX_8814B \ + (BIT_MASK_P0RXQ_HW_IDX_8814B << BIT_SHIFT_P0RXQ_HW_IDX_8814B) +#define BIT_CLEAR_P0RXQ_HW_IDX_8814B(x) ((x) & (~BITS_P0RXQ_HW_IDX_8814B)) +#define BIT_GET_P0RXQ_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0RXQ_HW_IDX_8814B) & BIT_MASK_P0RXQ_HW_IDX_8814B) +#define BIT_SET_P0RXQ_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0RXQ_HW_IDX_8814B(x) | BIT_P0RXQ_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0RXQ_HOST_IDX_8814B 0 +#define BIT_MASK_P0RXQ_HOST_IDX_8814B 0xfff +#define BIT_P0RXQ_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0RXQ_HOST_IDX_8814B) \ + << BIT_SHIFT_P0RXQ_HOST_IDX_8814B) +#define BITS_P0RXQ_HOST_IDX_8814B \ + (BIT_MASK_P0RXQ_HOST_IDX_8814B << BIT_SHIFT_P0RXQ_HOST_IDX_8814B) +#define BIT_CLEAR_P0RXQ_HOST_IDX_8814B(x) ((x) & (~BITS_P0RXQ_HOST_IDX_8814B)) +#define BIT_GET_P0RXQ_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0RXQ_HOST_IDX_8814B) & \ + BIT_MASK_P0RXQ_HOST_IDX_8814B) +#define BIT_SET_P0RXQ_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0RXQ_HOST_IDX_8814B(x) | BIT_P0RXQ_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI0Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI0Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI0Q_HW_IDX_8814B 0xfff +#define BIT_P0HI0Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI0Q_HW_IDX_8814B) << BIT_SHIFT_P0HI0Q_HW_IDX_8814B) +#define BITS_P0HI0Q_HW_IDX_8814B \ + (BIT_MASK_P0HI0Q_HW_IDX_8814B << BIT_SHIFT_P0HI0Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI0Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI0Q_HW_IDX_8814B)) +#define BIT_GET_P0HI0Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_HW_IDX_8814B) & BIT_MASK_P0HI0Q_HW_IDX_8814B) +#define BIT_SET_P0HI0Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI0Q_HW_IDX_8814B(x) | BIT_P0HI0Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI0Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI0Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI0Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI0Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI0Q_HOST_IDX_8814B) +#define BITS_P0HI0Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI0Q_HOST_IDX_8814B << BIT_SHIFT_P0HI0Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI0Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI0Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI0Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI0Q_HOST_IDX_8814B) +#define BIT_SET_P0HI0Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI0Q_HOST_IDX_8814B(x) | BIT_P0HI0Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI1Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI1Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI1Q_HW_IDX_8814B 0xfff +#define BIT_P0HI1Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI1Q_HW_IDX_8814B) << BIT_SHIFT_P0HI1Q_HW_IDX_8814B) +#define BITS_P0HI1Q_HW_IDX_8814B \ + (BIT_MASK_P0HI1Q_HW_IDX_8814B << BIT_SHIFT_P0HI1Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI1Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI1Q_HW_IDX_8814B)) +#define BIT_GET_P0HI1Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_HW_IDX_8814B) & BIT_MASK_P0HI1Q_HW_IDX_8814B) +#define BIT_SET_P0HI1Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI1Q_HW_IDX_8814B(x) | BIT_P0HI1Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI1Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI1Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI1Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI1Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI1Q_HOST_IDX_8814B) +#define BITS_P0HI1Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI1Q_HOST_IDX_8814B << BIT_SHIFT_P0HI1Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI1Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI1Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI1Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI1Q_HOST_IDX_8814B) +#define BIT_SET_P0HI1Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI1Q_HOST_IDX_8814B(x) | BIT_P0HI1Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI2Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI2Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI2Q_HW_IDX_8814B 0xfff +#define BIT_P0HI2Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI2Q_HW_IDX_8814B) << BIT_SHIFT_P0HI2Q_HW_IDX_8814B) +#define BITS_P0HI2Q_HW_IDX_8814B \ + (BIT_MASK_P0HI2Q_HW_IDX_8814B << BIT_SHIFT_P0HI2Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI2Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI2Q_HW_IDX_8814B)) +#define BIT_GET_P0HI2Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_HW_IDX_8814B) & BIT_MASK_P0HI2Q_HW_IDX_8814B) +#define BIT_SET_P0HI2Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI2Q_HW_IDX_8814B(x) | BIT_P0HI2Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI2Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI2Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI2Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI2Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI2Q_HOST_IDX_8814B) +#define BITS_P0HI2Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI2Q_HOST_IDX_8814B << BIT_SHIFT_P0HI2Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI2Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI2Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI2Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI2Q_HOST_IDX_8814B) +#define BIT_SET_P0HI2Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI2Q_HOST_IDX_8814B(x) | BIT_P0HI2Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI3Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI3Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI3Q_HW_IDX_8814B 0xfff +#define BIT_P0HI3Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI3Q_HW_IDX_8814B) << BIT_SHIFT_P0HI3Q_HW_IDX_8814B) +#define BITS_P0HI3Q_HW_IDX_8814B \ + (BIT_MASK_P0HI3Q_HW_IDX_8814B << BIT_SHIFT_P0HI3Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI3Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI3Q_HW_IDX_8814B)) +#define BIT_GET_P0HI3Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_HW_IDX_8814B) & BIT_MASK_P0HI3Q_HW_IDX_8814B) +#define BIT_SET_P0HI3Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI3Q_HW_IDX_8814B(x) | BIT_P0HI3Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI3Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI3Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI3Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI3Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI3Q_HOST_IDX_8814B) +#define BITS_P0HI3Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI3Q_HOST_IDX_8814B << BIT_SHIFT_P0HI3Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI3Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI3Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI3Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI3Q_HOST_IDX_8814B) +#define BIT_SET_P0HI3Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI3Q_HOST_IDX_8814B(x) | BIT_P0HI3Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI4Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI4Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI4Q_HW_IDX_8814B 0xfff +#define BIT_P0HI4Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI4Q_HW_IDX_8814B) << BIT_SHIFT_P0HI4Q_HW_IDX_8814B) +#define BITS_P0HI4Q_HW_IDX_8814B \ + (BIT_MASK_P0HI4Q_HW_IDX_8814B << BIT_SHIFT_P0HI4Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI4Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI4Q_HW_IDX_8814B)) +#define BIT_GET_P0HI4Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_HW_IDX_8814B) & BIT_MASK_P0HI4Q_HW_IDX_8814B) +#define BIT_SET_P0HI4Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI4Q_HW_IDX_8814B(x) | BIT_P0HI4Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI4Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI4Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI4Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI4Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI4Q_HOST_IDX_8814B) +#define BITS_P0HI4Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI4Q_HOST_IDX_8814B << BIT_SHIFT_P0HI4Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI4Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI4Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI4Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI4Q_HOST_IDX_8814B) +#define BIT_SET_P0HI4Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI4Q_HOST_IDX_8814B(x) | BIT_P0HI4Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI5Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI5Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI5Q_HW_IDX_8814B 0xfff +#define BIT_P0HI5Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI5Q_HW_IDX_8814B) << BIT_SHIFT_P0HI5Q_HW_IDX_8814B) +#define BITS_P0HI5Q_HW_IDX_8814B \ + (BIT_MASK_P0HI5Q_HW_IDX_8814B << BIT_SHIFT_P0HI5Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI5Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI5Q_HW_IDX_8814B)) +#define BIT_GET_P0HI5Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_HW_IDX_8814B) & BIT_MASK_P0HI5Q_HW_IDX_8814B) +#define BIT_SET_P0HI5Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI5Q_HW_IDX_8814B(x) | BIT_P0HI5Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI5Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI5Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI5Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI5Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI5Q_HOST_IDX_8814B) +#define BITS_P0HI5Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI5Q_HOST_IDX_8814B << BIT_SHIFT_P0HI5Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI5Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI5Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI5Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI5Q_HOST_IDX_8814B) +#define BIT_SET_P0HI5Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI5Q_HOST_IDX_8814B(x) | BIT_P0HI5Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI6Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI6Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI6Q_HW_IDX_8814B 0xfff +#define BIT_P0HI6Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI6Q_HW_IDX_8814B) << BIT_SHIFT_P0HI6Q_HW_IDX_8814B) +#define BITS_P0HI6Q_HW_IDX_8814B \ + (BIT_MASK_P0HI6Q_HW_IDX_8814B << BIT_SHIFT_P0HI6Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI6Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI6Q_HW_IDX_8814B)) +#define BIT_GET_P0HI6Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_HW_IDX_8814B) & BIT_MASK_P0HI6Q_HW_IDX_8814B) +#define BIT_SET_P0HI6Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI6Q_HW_IDX_8814B(x) | BIT_P0HI6Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI6Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI6Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI6Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI6Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI6Q_HOST_IDX_8814B) +#define BITS_P0HI6Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI6Q_HOST_IDX_8814B << BIT_SHIFT_P0HI6Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI6Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI6Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI6Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI6Q_HOST_IDX_8814B) +#define BIT_SET_P0HI6Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI6Q_HOST_IDX_8814B(x) | BIT_P0HI6Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI7Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI7Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI7Q_HW_IDX_8814B 0xfff +#define BIT_P0HI7Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI7Q_HW_IDX_8814B) << BIT_SHIFT_P0HI7Q_HW_IDX_8814B) +#define BITS_P0HI7Q_HW_IDX_8814B \ + (BIT_MASK_P0HI7Q_HW_IDX_8814B << BIT_SHIFT_P0HI7Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI7Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI7Q_HW_IDX_8814B)) +#define BIT_GET_P0HI7Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_HW_IDX_8814B) & BIT_MASK_P0HI7Q_HW_IDX_8814B) +#define BIT_SET_P0HI7Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI7Q_HW_IDX_8814B(x) | BIT_P0HI7Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI7Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI7Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI7Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI7Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI7Q_HOST_IDX_8814B) +#define BITS_P0HI7Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI7Q_HOST_IDX_8814B << BIT_SHIFT_P0HI7Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI7Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI7Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI7Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI7Q_HOST_IDX_8814B) +#define BIT_SET_P0HI7Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI7Q_HOST_IDX_8814B(x) | BIT_P0HI7Q_HOST_IDX_8814B(v)) + +/* 2 REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1_8814B */ +#define BIT_DIS_TXDMA_PRE_V1_8814B BIT(31) +#define BIT_DIS_RXDMA_PRE_V1_8814B BIT(30) + +#define BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B 28 +#define BIT_MASK_HPS_CLKR_PCIE_V1_8814B 0x3 +#define BIT_HPS_CLKR_PCIE_V1_8814B(x) \ + (((x) & BIT_MASK_HPS_CLKR_PCIE_V1_8814B) \ + << BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B) +#define BITS_HPS_CLKR_PCIE_V1_8814B \ + (BIT_MASK_HPS_CLKR_PCIE_V1_8814B << BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B) +#define BIT_CLEAR_HPS_CLKR_PCIE_V1_8814B(x) \ + ((x) & (~BITS_HPS_CLKR_PCIE_V1_8814B)) +#define BIT_GET_HPS_CLKR_PCIE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B) & \ + BIT_MASK_HPS_CLKR_PCIE_V1_8814B) +#define BIT_SET_HPS_CLKR_PCIE_V1_8814B(x, v) \ + (BIT_CLEAR_HPS_CLKR_PCIE_V1_8814B(x) | BIT_HPS_CLKR_PCIE_V1_8814B(v)) + +#define BIT_PCIE_INT_V1_8814B BIT(27) +#define BIT_TXFLAG_EXIT_L1_EN_V1_8814B BIT(26) +#define BIT_EN_RXDMA_ALIGN_V2_8814B BIT(25) +#define BIT_EN_TXDMA_ALIGN_V2_8814B BIT(24) + +#define BIT_SHIFT_PCIE_HCPWM_V1_8814B 16 +#define BIT_MASK_PCIE_HCPWM_V1_8814B 0xff +#define BIT_PCIE_HCPWM_V1_8814B(x) \ + (((x) & BIT_MASK_PCIE_HCPWM_V1_8814B) << BIT_SHIFT_PCIE_HCPWM_V1_8814B) +#define BITS_PCIE_HCPWM_V1_8814B \ + (BIT_MASK_PCIE_HCPWM_V1_8814B << BIT_SHIFT_PCIE_HCPWM_V1_8814B) +#define BIT_CLEAR_PCIE_HCPWM_V1_8814B(x) ((x) & (~BITS_PCIE_HCPWM_V1_8814B)) +#define BIT_GET_PCIE_HCPWM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM_V1_8814B) & BIT_MASK_PCIE_HCPWM_V1_8814B) +#define BIT_SET_PCIE_HCPWM_V1_8814B(x, v) \ + (BIT_CLEAR_PCIE_HCPWM_V1_8814B(x) | BIT_PCIE_HCPWM_V1_8814B(v)) + +#define BIT_SHIFT_PCIE_HRPWM_V1_8814B 8 +#define BIT_MASK_PCIE_HRPWM_V1_8814B 0xff +#define BIT_PCIE_HRPWM_V1_8814B(x) \ + (((x) & BIT_MASK_PCIE_HRPWM_V1_8814B) << BIT_SHIFT_PCIE_HRPWM_V1_8814B) +#define BITS_PCIE_HRPWM_V1_8814B \ + (BIT_MASK_PCIE_HRPWM_V1_8814B << BIT_SHIFT_PCIE_HRPWM_V1_8814B) +#define BIT_CLEAR_PCIE_HRPWM_V1_8814B(x) ((x) & (~BITS_PCIE_HRPWM_V1_8814B)) +#define BIT_GET_PCIE_HRPWM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM_V1_8814B) & BIT_MASK_PCIE_HRPWM_V1_8814B) +#define BIT_SET_PCIE_HRPWM_V1_8814B(x, v) \ + (BIT_CLEAR_PCIE_HRPWM_V1_8814B(x) | BIT_PCIE_HRPWM_V1_8814B(v)) -/* 2 REG_VIQ_TXBD_DESA_8814B */ +#define BIT_SHIFT_DBG_SEL_8814B 0 +#define BIT_MASK_DBG_SEL_8814B 0xff +#define BIT_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_DBG_SEL_8814B) << BIT_SHIFT_DBG_SEL_8814B) +#define BITS_DBG_SEL_8814B (BIT_MASK_DBG_SEL_8814B << BIT_SHIFT_DBG_SEL_8814B) +#define BIT_CLEAR_DBG_SEL_8814B(x) ((x) & (~BITS_DBG_SEL_8814B)) +#define BIT_GET_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_8814B) & BIT_MASK_DBG_SEL_8814B) +#define BIT_SET_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_DBG_SEL_8814B(x) | BIT_DBG_SEL_8814B(v)) + +/* 2 REG_PCIE_HRPWM2_HCPWM2_V1_8814B */ + +#define BIT_SHIFT_PCIE_HCPWM2_V1_8814B 16 +#define BIT_MASK_PCIE_HCPWM2_V1_8814B 0xffff +#define BIT_PCIE_HCPWM2_V1_8814B(x) \ + (((x) & BIT_MASK_PCIE_HCPWM2_V1_8814B) \ + << BIT_SHIFT_PCIE_HCPWM2_V1_8814B) +#define BITS_PCIE_HCPWM2_V1_8814B \ + (BIT_MASK_PCIE_HCPWM2_V1_8814B << BIT_SHIFT_PCIE_HCPWM2_V1_8814B) +#define BIT_CLEAR_PCIE_HCPWM2_V1_8814B(x) ((x) & (~BITS_PCIE_HCPWM2_V1_8814B)) +#define BIT_GET_PCIE_HCPWM2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM2_V1_8814B) & \ + BIT_MASK_PCIE_HCPWM2_V1_8814B) +#define BIT_SET_PCIE_HCPWM2_V1_8814B(x, v) \ + (BIT_CLEAR_PCIE_HCPWM2_V1_8814B(x) | BIT_PCIE_HCPWM2_V1_8814B(v)) -#define BIT_SHIFT_VIQ_TXBD_DESA_8814B 0 -#define BIT_MASK_VIQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_VIQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8814B) << BIT_SHIFT_VIQ_TXBD_DESA_8814B) -#define BIT_GET_VIQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8814B) & BIT_MASK_VIQ_TXBD_DESA_8814B) +#define BIT_SHIFT_PCIE_HRPWM2_8814B 0 +#define BIT_MASK_PCIE_HRPWM2_8814B 0xffff +#define BIT_PCIE_HRPWM2_8814B(x) \ + (((x) & BIT_MASK_PCIE_HRPWM2_8814B) << BIT_SHIFT_PCIE_HRPWM2_8814B) +#define BITS_PCIE_HRPWM2_8814B \ + (BIT_MASK_PCIE_HRPWM2_8814B << BIT_SHIFT_PCIE_HRPWM2_8814B) +#define BIT_CLEAR_PCIE_HRPWM2_8814B(x) ((x) & (~BITS_PCIE_HRPWM2_8814B)) +#define BIT_GET_PCIE_HRPWM2_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM2_8814B) & BIT_MASK_PCIE_HRPWM2_8814B) +#define BIT_SET_PCIE_HRPWM2_8814B(x, v) \ + (BIT_CLEAR_PCIE_HRPWM2_8814B(x) | BIT_PCIE_HRPWM2_8814B(v)) +/* 2 REG_PCIE_H2C_MSG_V1_8814B */ +#define BIT_SHIFT_DRV2FW_INFO_8814B 0 +#define BIT_MASK_DRV2FW_INFO_8814B 0xffffffffL +#define BIT_DRV2FW_INFO_8814B(x) \ + (((x) & BIT_MASK_DRV2FW_INFO_8814B) << BIT_SHIFT_DRV2FW_INFO_8814B) +#define BITS_DRV2FW_INFO_8814B \ + (BIT_MASK_DRV2FW_INFO_8814B << BIT_SHIFT_DRV2FW_INFO_8814B) +#define BIT_CLEAR_DRV2FW_INFO_8814B(x) ((x) & (~BITS_DRV2FW_INFO_8814B)) +#define BIT_GET_DRV2FW_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_DRV2FW_INFO_8814B) & BIT_MASK_DRV2FW_INFO_8814B) +#define BIT_SET_DRV2FW_INFO_8814B(x, v) \ + (BIT_CLEAR_DRV2FW_INFO_8814B(x) | BIT_DRV2FW_INFO_8814B(v)) -/* 2 REG_BEQ_TXBD_DESA_8814B */ +/* 2 REG_PCIE_C2H_MSG_V1_8814B */ -#define BIT_SHIFT_BEQ_TXBD_DESA_8814B 0 -#define BIT_MASK_BEQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_BEQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8814B) << BIT_SHIFT_BEQ_TXBD_DESA_8814B) -#define BIT_GET_BEQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8814B) & BIT_MASK_BEQ_TXBD_DESA_8814B) +#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B 0 +#define BIT_MASK_HCI_PCIE_C2H_MSG_8814B 0xffffffffL +#define BIT_HCI_PCIE_C2H_MSG_8814B(x) \ + (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8814B) \ + << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) +#define BITS_HCI_PCIE_C2H_MSG_8814B \ + (BIT_MASK_HCI_PCIE_C2H_MSG_8814B << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) +#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8814B(x) \ + ((x) & (~BITS_HCI_PCIE_C2H_MSG_8814B)) +#define BIT_GET_HCI_PCIE_C2H_MSG_8814B(x) \ + (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) & \ + BIT_MASK_HCI_PCIE_C2H_MSG_8814B) +#define BIT_SET_HCI_PCIE_C2H_MSG_8814B(x, v) \ + (BIT_CLEAR_HCI_PCIE_C2H_MSG_8814B(x) | BIT_HCI_PCIE_C2H_MSG_8814B(v)) +/* 2 REG_DBI_WDATA_V1_8814B */ +#define BIT_SHIFT_DBI_WDATA_8814B 0 +#define BIT_MASK_DBI_WDATA_8814B 0xffffffffL +#define BIT_DBI_WDATA_8814B(x) \ + (((x) & BIT_MASK_DBI_WDATA_8814B) << BIT_SHIFT_DBI_WDATA_8814B) +#define BITS_DBI_WDATA_8814B \ + (BIT_MASK_DBI_WDATA_8814B << BIT_SHIFT_DBI_WDATA_8814B) +#define BIT_CLEAR_DBI_WDATA_8814B(x) ((x) & (~BITS_DBI_WDATA_8814B)) +#define BIT_GET_DBI_WDATA_8814B(x) \ + (((x) >> BIT_SHIFT_DBI_WDATA_8814B) & BIT_MASK_DBI_WDATA_8814B) +#define BIT_SET_DBI_WDATA_8814B(x, v) \ + (BIT_CLEAR_DBI_WDATA_8814B(x) | BIT_DBI_WDATA_8814B(v)) -/* 2 REG_BKQ_TXBD_DESA_8814B */ +/* 2 REG_DBI_RDATA_V1_8814B */ -#define BIT_SHIFT_BKQ_TXBD_DESA_8814B 0 -#define BIT_MASK_BKQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_BKQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8814B) << BIT_SHIFT_BKQ_TXBD_DESA_8814B) -#define BIT_GET_BKQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8814B) & BIT_MASK_BKQ_TXBD_DESA_8814B) +#define BIT_SHIFT_DBI_RDATA_8814B 0 +#define BIT_MASK_DBI_RDATA_8814B 0xffffffffL +#define BIT_DBI_RDATA_8814B(x) \ + (((x) & BIT_MASK_DBI_RDATA_8814B) << BIT_SHIFT_DBI_RDATA_8814B) +#define BITS_DBI_RDATA_8814B \ + (BIT_MASK_DBI_RDATA_8814B << BIT_SHIFT_DBI_RDATA_8814B) +#define BIT_CLEAR_DBI_RDATA_8814B(x) ((x) & (~BITS_DBI_RDATA_8814B)) +#define BIT_GET_DBI_RDATA_8814B(x) \ + (((x) >> BIT_SHIFT_DBI_RDATA_8814B) & BIT_MASK_DBI_RDATA_8814B) +#define BIT_SET_DBI_RDATA_8814B(x, v) \ + (BIT_CLEAR_DBI_RDATA_8814B(x) | BIT_DBI_RDATA_8814B(v)) +/* 2 REG_DBI_FLAG_V1_8814B */ +#define BIT_SHIFT_LOOPBACK_DBG_SEL_8814B 28 +#define BIT_MASK_LOOPBACK_DBG_SEL_8814B 0xf +#define BIT_LOOPBACK_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_LOOPBACK_DBG_SEL_8814B) \ + << BIT_SHIFT_LOOPBACK_DBG_SEL_8814B) +#define BITS_LOOPBACK_DBG_SEL_8814B \ + (BIT_MASK_LOOPBACK_DBG_SEL_8814B << BIT_SHIFT_LOOPBACK_DBG_SEL_8814B) +#define BIT_CLEAR_LOOPBACK_DBG_SEL_8814B(x) \ + ((x) & (~BITS_LOOPBACK_DBG_SEL_8814B)) +#define BIT_GET_LOOPBACK_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_LOOPBACK_DBG_SEL_8814B) & \ + BIT_MASK_LOOPBACK_DBG_SEL_8814B) +#define BIT_SET_LOOPBACK_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_LOOPBACK_DBG_SEL_8814B(x) | BIT_LOOPBACK_DBG_SEL_8814B(v)) -/* 2 REG_RXQ_RXBD_DESA_8814B */ +#define BIT_EN_STUCK_DBG_8814B BIT(26) +#define BIT_RX_STUCK_8814B BIT(25) +#define BIT_TX_STUCK_8814B BIT(24) +#define BIT_DBI_RFLAG_8814B BIT(17) +#define BIT_DBI_WFLAG_8814B BIT(16) -#define BIT_SHIFT_RXQ_RXBD_DESA_8814B 0 -#define BIT_MASK_RXQ_RXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_RXQ_RXBD_DESA_8814B(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8814B) << BIT_SHIFT_RXQ_RXBD_DESA_8814B) -#define BIT_GET_RXQ_RXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8814B) & BIT_MASK_RXQ_RXBD_DESA_8814B) +#define BIT_SHIFT_DBI_WREN_8814B 12 +#define BIT_MASK_DBI_WREN_8814B 0xf +#define BIT_DBI_WREN_8814B(x) \ + (((x) & BIT_MASK_DBI_WREN_8814B) << BIT_SHIFT_DBI_WREN_8814B) +#define BITS_DBI_WREN_8814B \ + (BIT_MASK_DBI_WREN_8814B << BIT_SHIFT_DBI_WREN_8814B) +#define BIT_CLEAR_DBI_WREN_8814B(x) ((x) & (~BITS_DBI_WREN_8814B)) +#define BIT_GET_DBI_WREN_8814B(x) \ + (((x) >> BIT_SHIFT_DBI_WREN_8814B) & BIT_MASK_DBI_WREN_8814B) +#define BIT_SET_DBI_WREN_8814B(x, v) \ + (BIT_CLEAR_DBI_WREN_8814B(x) | BIT_DBI_WREN_8814B(v)) +#define BIT_SHIFT_DBI_ADDR_8814B 0 +#define BIT_MASK_DBI_ADDR_8814B 0xfff +#define BIT_DBI_ADDR_8814B(x) \ + (((x) & BIT_MASK_DBI_ADDR_8814B) << BIT_SHIFT_DBI_ADDR_8814B) +#define BITS_DBI_ADDR_8814B \ + (BIT_MASK_DBI_ADDR_8814B << BIT_SHIFT_DBI_ADDR_8814B) +#define BIT_CLEAR_DBI_ADDR_8814B(x) ((x) & (~BITS_DBI_ADDR_8814B)) +#define BIT_GET_DBI_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_DBI_ADDR_8814B) & BIT_MASK_DBI_ADDR_8814B) +#define BIT_SET_DBI_ADDR_8814B(x, v) \ + (BIT_CLEAR_DBI_ADDR_8814B(x) | BIT_DBI_ADDR_8814B(v)) +/* 2 REG_MDIO_V1_8814B */ -/* 2 REG_HI0Q_TXBD_DESA_8814B */ +#define BIT_SHIFT_MDIO_RDATA_8814B 16 +#define BIT_MASK_MDIO_RDATA_8814B 0xffff +#define BIT_MDIO_RDATA_8814B(x) \ + (((x) & BIT_MASK_MDIO_RDATA_8814B) << BIT_SHIFT_MDIO_RDATA_8814B) +#define BITS_MDIO_RDATA_8814B \ + (BIT_MASK_MDIO_RDATA_8814B << BIT_SHIFT_MDIO_RDATA_8814B) +#define BIT_CLEAR_MDIO_RDATA_8814B(x) ((x) & (~BITS_MDIO_RDATA_8814B)) +#define BIT_GET_MDIO_RDATA_8814B(x) \ + (((x) >> BIT_SHIFT_MDIO_RDATA_8814B) & BIT_MASK_MDIO_RDATA_8814B) +#define BIT_SET_MDIO_RDATA_8814B(x, v) \ + (BIT_CLEAR_MDIO_RDATA_8814B(x) | BIT_MDIO_RDATA_8814B(v)) -#define BIT_SHIFT_HI0Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI0Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI0Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8814B) << BIT_SHIFT_HI0Q_TXBD_DESA_8814B) -#define BIT_GET_HI0Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8814B) & BIT_MASK_HI0Q_TXBD_DESA_8814B) +#define BIT_SHIFT_MDIO_WDATA_8814B 0 +#define BIT_MASK_MDIO_WDATA_8814B 0xffff +#define BIT_MDIO_WDATA_8814B(x) \ + (((x) & BIT_MASK_MDIO_WDATA_8814B) << BIT_SHIFT_MDIO_WDATA_8814B) +#define BITS_MDIO_WDATA_8814B \ + (BIT_MASK_MDIO_WDATA_8814B << BIT_SHIFT_MDIO_WDATA_8814B) +#define BIT_CLEAR_MDIO_WDATA_8814B(x) ((x) & (~BITS_MDIO_WDATA_8814B)) +#define BIT_GET_MDIO_WDATA_8814B(x) \ + (((x) >> BIT_SHIFT_MDIO_WDATA_8814B) & BIT_MASK_MDIO_WDATA_8814B) +#define BIT_SET_MDIO_WDATA_8814B(x, v) \ + (BIT_CLEAR_MDIO_WDATA_8814B(x) | BIT_MDIO_WDATA_8814B(v)) +/* 2 REG_PCIE_MIX_CFG_8814B */ +#define BIT_SHIFT_MDIO_PHY_ADDR_8814B 24 +#define BIT_MASK_MDIO_PHY_ADDR_8814B 0x1f +#define BIT_MDIO_PHY_ADDR_8814B(x) \ + (((x) & BIT_MASK_MDIO_PHY_ADDR_8814B) << BIT_SHIFT_MDIO_PHY_ADDR_8814B) +#define BITS_MDIO_PHY_ADDR_8814B \ + (BIT_MASK_MDIO_PHY_ADDR_8814B << BIT_SHIFT_MDIO_PHY_ADDR_8814B) +#define BIT_CLEAR_MDIO_PHY_ADDR_8814B(x) ((x) & (~BITS_MDIO_PHY_ADDR_8814B)) +#define BIT_GET_MDIO_PHY_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8814B) & BIT_MASK_MDIO_PHY_ADDR_8814B) +#define BIT_SET_MDIO_PHY_ADDR_8814B(x, v) \ + (BIT_CLEAR_MDIO_PHY_ADDR_8814B(x) | BIT_MDIO_PHY_ADDR_8814B(v)) -/* 2 REG_HI1Q_TXBD_DESA_8814B */ - -#define BIT_SHIFT_HI1Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI1Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI1Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8814B) << BIT_SHIFT_HI1Q_TXBD_DESA_8814B) -#define BIT_GET_HI1Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8814B) & BIT_MASK_HI1Q_TXBD_DESA_8814B) - - - -/* 2 REG_HI2Q_TXBD_DESA_8814B */ - -#define BIT_SHIFT_HI2Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI2Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI2Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8814B) << BIT_SHIFT_HI2Q_TXBD_DESA_8814B) -#define BIT_GET_HI2Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8814B) & BIT_MASK_HI2Q_TXBD_DESA_8814B) +#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B 10 +#define BIT_MASK_WATCH_DOG_RECORD_V1_8814B 0x3fff +#define BIT_WATCH_DOG_RECORD_V1_8814B(x) \ + (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8814B) \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) +#define BITS_WATCH_DOG_RECORD_V1_8814B \ + (BIT_MASK_WATCH_DOG_RECORD_V1_8814B \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8814B(x) \ + ((x) & (~BITS_WATCH_DOG_RECORD_V1_8814B)) +#define BIT_GET_WATCH_DOG_RECORD_V1_8814B(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) & \ + BIT_MASK_WATCH_DOG_RECORD_V1_8814B) +#define BIT_SET_WATCH_DOG_RECORD_V1_8814B(x, v) \ + (BIT_CLEAR_WATCH_DOG_RECORD_V1_8814B(x) | \ + BIT_WATCH_DOG_RECORD_V1_8814B(v)) +#define BIT_R_IO_TIMEOUT_FLAG_V1_8814B BIT(9) +#define BIT_EN_WATCH_DOG_8814B BIT(8) +#define BIT_ECRC_EN_8814B BIT(7) +#define BIT_MDIO_RFLAG_8814B BIT(6) +#define BIT_MDIO_WFLAG_8814B BIT(5) + +#define BIT_SHIFT_MDIO_REG_ADDR_8814B 0 +#define BIT_MASK_MDIO_REG_ADDR_8814B 0x1f +#define BIT_MDIO_REG_ADDR_8814B(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR_8814B) << BIT_SHIFT_MDIO_REG_ADDR_8814B) +#define BITS_MDIO_REG_ADDR_8814B \ + (BIT_MASK_MDIO_REG_ADDR_8814B << BIT_SHIFT_MDIO_REG_ADDR_8814B) +#define BIT_CLEAR_MDIO_REG_ADDR_8814B(x) ((x) & (~BITS_MDIO_REG_ADDR_8814B)) +#define BIT_GET_MDIO_REG_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR_8814B) & BIT_MASK_MDIO_REG_ADDR_8814B) +#define BIT_SET_MDIO_REG_ADDR_8814B(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR_8814B(x) | BIT_MDIO_REG_ADDR_8814B(v)) +/* 2 REG_HCI_MIX_CFG_8814B */ +#define BIT_EN_ALIGN_MTU_8814B BIT(23) + +#define BIT_SHIFT_LATENCY_CONTROL_8814B 21 +#define BIT_MASK_LATENCY_CONTROL_8814B 0x3 +#define BIT_LATENCY_CONTROL_8814B(x) \ + (((x) & BIT_MASK_LATENCY_CONTROL_8814B) \ + << BIT_SHIFT_LATENCY_CONTROL_8814B) +#define BITS_LATENCY_CONTROL_8814B \ + (BIT_MASK_LATENCY_CONTROL_8814B << BIT_SHIFT_LATENCY_CONTROL_8814B) +#define BIT_CLEAR_LATENCY_CONTROL_8814B(x) ((x) & (~BITS_LATENCY_CONTROL_8814B)) +#define BIT_GET_LATENCY_CONTROL_8814B(x) \ + (((x) >> BIT_SHIFT_LATENCY_CONTROL_8814B) & \ + BIT_MASK_LATENCY_CONTROL_8814B) +#define BIT_SET_LATENCY_CONTROL_8814B(x, v) \ + (BIT_CLEAR_LATENCY_CONTROL_8814B(x) | BIT_LATENCY_CONTROL_8814B(v)) -/* 2 REG_HI3Q_TXBD_DESA_8814B */ +#define BIT_HOST_GEN2_SUPPORT_8814B BIT(20) -#define BIT_SHIFT_HI3Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI3Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI3Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8814B) << BIT_SHIFT_HI3Q_TXBD_DESA_8814B) -#define BIT_GET_HI3Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8814B) & BIT_MASK_HI3Q_TXBD_DESA_8814B) +#define BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B 15 +#define BIT_MASK_TXDMA_ERR_FLAG_V1_8814B 0x1f +#define BIT_TXDMA_ERR_FLAG_V1_8814B(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG_V1_8814B) \ + << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B) +#define BITS_TXDMA_ERR_FLAG_V1_8814B \ + (BIT_MASK_TXDMA_ERR_FLAG_V1_8814B << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B) +#define BIT_CLEAR_TXDMA_ERR_FLAG_V1_8814B(x) \ + ((x) & (~BITS_TXDMA_ERR_FLAG_V1_8814B)) +#define BIT_GET_TXDMA_ERR_FLAG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B) & \ + BIT_MASK_TXDMA_ERR_FLAG_V1_8814B) +#define BIT_SET_TXDMA_ERR_FLAG_V1_8814B(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG_V1_8814B(x) | BIT_TXDMA_ERR_FLAG_V1_8814B(v)) +#define BIT_EPHY_RX50_EN_8814B BIT(11) +#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B 8 +#define BIT_MASK_MSI_TIMEOUT_ID_V1_8814B 0x7 +#define BIT_MSI_TIMEOUT_ID_V1_8814B(x) \ + (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8814B) \ + << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) +#define BITS_MSI_TIMEOUT_ID_V1_8814B \ + (BIT_MASK_MSI_TIMEOUT_ID_V1_8814B << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8814B(x) \ + ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8814B)) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) & \ + BIT_MASK_MSI_TIMEOUT_ID_V1_8814B) +#define BIT_SET_MSI_TIMEOUT_ID_V1_8814B(x, v) \ + (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8814B(x) | BIT_MSI_TIMEOUT_ID_V1_8814B(v)) -/* 2 REG_HI4Q_TXBD_DESA_8814B */ +#define BIT_RADDR_RD_8814B BIT(7) +#define BIT_L0S_LINK_OFF_8814B BIT(4) +#define BIT_ACT_LINK_OFF_8814B BIT(3) +#define BIT_EN_SLOW_MAC_TX_8814B BIT(2) +#define BIT_EN_SLOW_MAC_RX_8814B BIT(1) +#define BIT_EN_SLOW_MAC_HW_8814B BIT(0) -#define BIT_SHIFT_HI4Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI4Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI4Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8814B) << BIT_SHIFT_HI4Q_TXBD_DESA_8814B) -#define BIT_GET_HI4Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8814B) & BIT_MASK_HI4Q_TXBD_DESA_8814B) +/* 2 REG_STC_INT_CS_8814B(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */ +#define BIT_STC_INT_EN_8814B BIT(31) +#define BIT_SHIFT_STC_INT_FLAG_8814B 16 +#define BIT_MASK_STC_INT_FLAG_8814B 0xff +#define BIT_STC_INT_FLAG_8814B(x) \ + (((x) & BIT_MASK_STC_INT_FLAG_8814B) << BIT_SHIFT_STC_INT_FLAG_8814B) +#define BITS_STC_INT_FLAG_8814B \ + (BIT_MASK_STC_INT_FLAG_8814B << BIT_SHIFT_STC_INT_FLAG_8814B) +#define BIT_CLEAR_STC_INT_FLAG_8814B(x) ((x) & (~BITS_STC_INT_FLAG_8814B)) +#define BIT_GET_STC_INT_FLAG_8814B(x) \ + (((x) >> BIT_SHIFT_STC_INT_FLAG_8814B) & BIT_MASK_STC_INT_FLAG_8814B) +#define BIT_SET_STC_INT_FLAG_8814B(x, v) \ + (BIT_CLEAR_STC_INT_FLAG_8814B(x) | BIT_STC_INT_FLAG_8814B(v)) +#define BIT_SHIFT_STC_INT_IDX_8814B 8 +#define BIT_MASK_STC_INT_IDX_8814B 0x7 +#define BIT_STC_INT_IDX_8814B(x) \ + (((x) & BIT_MASK_STC_INT_IDX_8814B) << BIT_SHIFT_STC_INT_IDX_8814B) +#define BITS_STC_INT_IDX_8814B \ + (BIT_MASK_STC_INT_IDX_8814B << BIT_SHIFT_STC_INT_IDX_8814B) +#define BIT_CLEAR_STC_INT_IDX_8814B(x) ((x) & (~BITS_STC_INT_IDX_8814B)) +#define BIT_GET_STC_INT_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_STC_INT_IDX_8814B) & BIT_MASK_STC_INT_IDX_8814B) +#define BIT_SET_STC_INT_IDX_8814B(x, v) \ + (BIT_CLEAR_STC_INT_IDX_8814B(x) | BIT_STC_INT_IDX_8814B(v)) -/* 2 REG_HI5Q_TXBD_DESA_8814B */ +#define BIT_SHIFT_STC_INT_REALTIME_CS_8814B 0 +#define BIT_MASK_STC_INT_REALTIME_CS_8814B 0x3f +#define BIT_STC_INT_REALTIME_CS_8814B(x) \ + (((x) & BIT_MASK_STC_INT_REALTIME_CS_8814B) \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8814B) +#define BITS_STC_INT_REALTIME_CS_8814B \ + (BIT_MASK_STC_INT_REALTIME_CS_8814B \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8814B) +#define BIT_CLEAR_STC_INT_REALTIME_CS_8814B(x) \ + ((x) & (~BITS_STC_INT_REALTIME_CS_8814B)) +#define BIT_GET_STC_INT_REALTIME_CS_8814B(x) \ + (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8814B) & \ + BIT_MASK_STC_INT_REALTIME_CS_8814B) +#define BIT_SET_STC_INT_REALTIME_CS_8814B(x, v) \ + (BIT_CLEAR_STC_INT_REALTIME_CS_8814B(x) | \ + BIT_STC_INT_REALTIME_CS_8814B(v)) -#define BIT_SHIFT_HI5Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI5Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI5Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8814B) << BIT_SHIFT_HI5Q_TXBD_DESA_8814B) -#define BIT_GET_HI5Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8814B) & BIT_MASK_HI5Q_TXBD_DESA_8814B) +/* 2 REG_ST_INT_CFG_8814B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */ +#define BIT_STC_INT_GRP_EN_8814B BIT(31) +#define BIT_SHIFT_STC_INT_EXPECT_LS_8814B 8 +#define BIT_MASK_STC_INT_EXPECT_LS_8814B 0x3f +#define BIT_STC_INT_EXPECT_LS_8814B(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_LS_8814B) \ + << BIT_SHIFT_STC_INT_EXPECT_LS_8814B) +#define BITS_STC_INT_EXPECT_LS_8814B \ + (BIT_MASK_STC_INT_EXPECT_LS_8814B << BIT_SHIFT_STC_INT_EXPECT_LS_8814B) +#define BIT_CLEAR_STC_INT_EXPECT_LS_8814B(x) \ + ((x) & (~BITS_STC_INT_EXPECT_LS_8814B)) +#define BIT_GET_STC_INT_EXPECT_LS_8814B(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8814B) & \ + BIT_MASK_STC_INT_EXPECT_LS_8814B) +#define BIT_SET_STC_INT_EXPECT_LS_8814B(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_LS_8814B(x) | BIT_STC_INT_EXPECT_LS_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_HI6Q_TXBD_DESA_8814B */ +#define BIT_SHIFT_STC_INT_EXPECT_CS_8814B 0 +#define BIT_MASK_STC_INT_EXPECT_CS_8814B 0x3f +#define BIT_STC_INT_EXPECT_CS_8814B(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_CS_8814B) \ + << BIT_SHIFT_STC_INT_EXPECT_CS_8814B) +#define BITS_STC_INT_EXPECT_CS_8814B \ + (BIT_MASK_STC_INT_EXPECT_CS_8814B << BIT_SHIFT_STC_INT_EXPECT_CS_8814B) +#define BIT_CLEAR_STC_INT_EXPECT_CS_8814B(x) \ + ((x) & (~BITS_STC_INT_EXPECT_CS_8814B)) +#define BIT_GET_STC_INT_EXPECT_CS_8814B(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8814B) & \ + BIT_MASK_STC_INT_EXPECT_CS_8814B) +#define BIT_SET_STC_INT_EXPECT_CS_8814B(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_CS_8814B(x) | BIT_STC_INT_EXPECT_CS_8814B(v)) + +/* 2 REG_ACH4_ACH5_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH5_FLAG_8814B BIT(30) + +#define BIT_SHIFT_ACH5_DESC_MODE_8814B 28 +#define BIT_MASK_ACH5_DESC_MODE_8814B 0x3 +#define BIT_ACH5_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH5_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH5_DESC_MODE_8814B) +#define BITS_ACH5_DESC_MODE_8814B \ + (BIT_MASK_ACH5_DESC_MODE_8814B << BIT_SHIFT_ACH5_DESC_MODE_8814B) +#define BIT_CLEAR_ACH5_DESC_MODE_8814B(x) ((x) & (~BITS_ACH5_DESC_MODE_8814B)) +#define BIT_GET_ACH5_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH5_DESC_MODE_8814B) & \ + BIT_MASK_ACH5_DESC_MODE_8814B) +#define BIT_SET_ACH5_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH5_DESC_MODE_8814B(x) | BIT_ACH5_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH5_DESC_NUM_8814B 16 +#define BIT_MASK_ACH5_DESC_NUM_8814B 0xfff +#define BIT_ACH5_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH5_DESC_NUM_8814B) << BIT_SHIFT_ACH5_DESC_NUM_8814B) +#define BITS_ACH5_DESC_NUM_8814B \ + (BIT_MASK_ACH5_DESC_NUM_8814B << BIT_SHIFT_ACH5_DESC_NUM_8814B) +#define BIT_CLEAR_ACH5_DESC_NUM_8814B(x) ((x) & (~BITS_ACH5_DESC_NUM_8814B)) +#define BIT_GET_ACH5_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH5_DESC_NUM_8814B) & BIT_MASK_ACH5_DESC_NUM_8814B) +#define BIT_SET_ACH5_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH5_DESC_NUM_8814B(x) | BIT_ACH5_DESC_NUM_8814B(v)) + +#define BIT_PCIE_ACH4_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH4_DESC_MODE_8814B 12 +#define BIT_MASK_ACH4_DESC_MODE_8814B 0x3 +#define BIT_ACH4_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH4_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH4_DESC_MODE_8814B) +#define BITS_ACH4_DESC_MODE_8814B \ + (BIT_MASK_ACH4_DESC_MODE_8814B << BIT_SHIFT_ACH4_DESC_MODE_8814B) +#define BIT_CLEAR_ACH4_DESC_MODE_8814B(x) ((x) & (~BITS_ACH4_DESC_MODE_8814B)) +#define BIT_GET_ACH4_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH4_DESC_MODE_8814B) & \ + BIT_MASK_ACH4_DESC_MODE_8814B) +#define BIT_SET_ACH4_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH4_DESC_MODE_8814B(x) | BIT_ACH4_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH4_DESC_NUM_8814B 0 +#define BIT_MASK_ACH4_DESC_NUM_8814B 0xfff +#define BIT_ACH4_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH4_DESC_NUM_8814B) << BIT_SHIFT_ACH4_DESC_NUM_8814B) +#define BITS_ACH4_DESC_NUM_8814B \ + (BIT_MASK_ACH4_DESC_NUM_8814B << BIT_SHIFT_ACH4_DESC_NUM_8814B) +#define BIT_CLEAR_ACH4_DESC_NUM_8814B(x) ((x) & (~BITS_ACH4_DESC_NUM_8814B)) +#define BIT_GET_ACH4_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH4_DESC_NUM_8814B) & BIT_MASK_ACH4_DESC_NUM_8814B) +#define BIT_SET_ACH4_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH4_DESC_NUM_8814B(x) | BIT_ACH4_DESC_NUM_8814B(v)) + +/* 2 REG_FWCMDQ_TXBD_IDX_8814B */ + +#define BIT_SHIFT_FWCMDQ_HW_IDX_8814B 16 +#define BIT_MASK_FWCMDQ_HW_IDX_8814B 0xfff +#define BIT_FWCMDQ_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_HW_IDX_8814B) << BIT_SHIFT_FWCMDQ_HW_IDX_8814B) +#define BITS_FWCMDQ_HW_IDX_8814B \ + (BIT_MASK_FWCMDQ_HW_IDX_8814B << BIT_SHIFT_FWCMDQ_HW_IDX_8814B) +#define BIT_CLEAR_FWCMDQ_HW_IDX_8814B(x) ((x) & (~BITS_FWCMDQ_HW_IDX_8814B)) +#define BIT_GET_FWCMDQ_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_HW_IDX_8814B) & BIT_MASK_FWCMDQ_HW_IDX_8814B) +#define BIT_SET_FWCMDQ_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_HW_IDX_8814B(x) | BIT_FWCMDQ_HW_IDX_8814B(v)) + +#define BIT_SHIFT_FWCMDQ_HOST_IDX_8814B 0 +#define BIT_MASK_FWCMDQ_HOST_IDX_8814B 0xfff +#define BIT_FWCMDQ_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_HOST_IDX_8814B) \ + << BIT_SHIFT_FWCMDQ_HOST_IDX_8814B) +#define BITS_FWCMDQ_HOST_IDX_8814B \ + (BIT_MASK_FWCMDQ_HOST_IDX_8814B << BIT_SHIFT_FWCMDQ_HOST_IDX_8814B) +#define BIT_CLEAR_FWCMDQ_HOST_IDX_8814B(x) ((x) & (~BITS_FWCMDQ_HOST_IDX_8814B)) +#define BIT_GET_FWCMDQ_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_HOST_IDX_8814B) & \ + BIT_MASK_FWCMDQ_HOST_IDX_8814B) +#define BIT_SET_FWCMDQ_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_HOST_IDX_8814B(x) | BIT_FWCMDQ_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI8Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI8Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI8Q_HW_IDX_8814B 0xfff +#define BIT_P0HI8Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI8Q_HW_IDX_8814B) << BIT_SHIFT_P0HI8Q_HW_IDX_8814B) +#define BITS_P0HI8Q_HW_IDX_8814B \ + (BIT_MASK_P0HI8Q_HW_IDX_8814B << BIT_SHIFT_P0HI8Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI8Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI8Q_HW_IDX_8814B)) +#define BIT_GET_P0HI8Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_HW_IDX_8814B) & BIT_MASK_P0HI8Q_HW_IDX_8814B) +#define BIT_SET_P0HI8Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI8Q_HW_IDX_8814B(x) | BIT_P0HI8Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI8Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI8Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI8Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI8Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI8Q_HOST_IDX_8814B) +#define BITS_P0HI8Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI8Q_HOST_IDX_8814B << BIT_SHIFT_P0HI8Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI8Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI8Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI8Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI8Q_HOST_IDX_8814B) +#define BIT_SET_P0HI8Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI8Q_HOST_IDX_8814B(x) | BIT_P0HI8Q_HOST_IDX_8814B(v)) + +/* 2 REG_H2CQ_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B 0 +#define BIT_MASK_H2CQ_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_H2CQ_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B) +#define BITS_H2CQ_TXBD_DESA_L_8814B \ + (BIT_MASK_H2CQ_TXBD_DESA_L_8814B << BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B) +#define BIT_CLEAR_H2CQ_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_H2CQ_TXBD_DESA_L_8814B)) +#define BIT_GET_H2CQ_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B) & \ + BIT_MASK_H2CQ_TXBD_DESA_L_8814B) +#define BIT_SET_H2CQ_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_L_8814B(x) | BIT_H2CQ_TXBD_DESA_L_8814B(v)) + +/* 2 REG_H2CQ_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B 0 +#define BIT_MASK_H2CQ_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_H2CQ_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B) +#define BITS_H2CQ_TXBD_DESA_H_8814B \ + (BIT_MASK_H2CQ_TXBD_DESA_H_8814B << BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B) +#define BIT_CLEAR_H2CQ_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_H2CQ_TXBD_DESA_H_8814B)) +#define BIT_GET_H2CQ_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B) & \ + BIT_MASK_H2CQ_TXBD_DESA_H_8814B) +#define BIT_SET_H2CQ_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_H_8814B(x) | BIT_H2CQ_TXBD_DESA_H_8814B(v)) -#define BIT_SHIFT_HI6Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI6Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI6Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8814B) << BIT_SHIFT_HI6Q_TXBD_DESA_8814B) -#define BIT_GET_HI6Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8814B) & BIT_MASK_HI6Q_TXBD_DESA_8814B) +/* 2 REG_H2CQ_TXBD_NUM_8814B */ +#define BIT_PCIE_H2CQ_FLAG_8814B BIT(14) +#define BIT_SHIFT_H2CQ_DESC_MODE_8814B 12 +#define BIT_MASK_H2CQ_DESC_MODE_8814B 0x3 +#define BIT_H2CQ_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_H2CQ_DESC_MODE_8814B) \ + << BIT_SHIFT_H2CQ_DESC_MODE_8814B) +#define BITS_H2CQ_DESC_MODE_8814B \ + (BIT_MASK_H2CQ_DESC_MODE_8814B << BIT_SHIFT_H2CQ_DESC_MODE_8814B) +#define BIT_CLEAR_H2CQ_DESC_MODE_8814B(x) ((x) & (~BITS_H2CQ_DESC_MODE_8814B)) +#define BIT_GET_H2CQ_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8814B) & \ + BIT_MASK_H2CQ_DESC_MODE_8814B) +#define BIT_SET_H2CQ_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_H2CQ_DESC_MODE_8814B(x) | BIT_H2CQ_DESC_MODE_8814B(v)) +#define BIT_SHIFT_H2CQ_DESC_NUM_8814B 0 +#define BIT_MASK_H2CQ_DESC_NUM_8814B 0xfff +#define BIT_H2CQ_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_H2CQ_DESC_NUM_8814B) << BIT_SHIFT_H2CQ_DESC_NUM_8814B) +#define BITS_H2CQ_DESC_NUM_8814B \ + (BIT_MASK_H2CQ_DESC_NUM_8814B << BIT_SHIFT_H2CQ_DESC_NUM_8814B) +#define BIT_CLEAR_H2CQ_DESC_NUM_8814B(x) ((x) & (~BITS_H2CQ_DESC_NUM_8814B)) +#define BIT_GET_H2CQ_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8814B) & BIT_MASK_H2CQ_DESC_NUM_8814B) +#define BIT_SET_H2CQ_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_H2CQ_DESC_NUM_8814B(x) | BIT_H2CQ_DESC_NUM_8814B(v)) -/* 2 REG_HI7Q_TXBD_DESA_8814B */ +/* 2 REG_H2CQ_TXBD_IDX_8814B */ -#define BIT_SHIFT_HI7Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI7Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI7Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8814B) << BIT_SHIFT_HI7Q_TXBD_DESA_8814B) -#define BIT_GET_HI7Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8814B) & BIT_MASK_HI7Q_TXBD_DESA_8814B) +#define BIT_SHIFT_H2CQ_HW_IDX_8814B 16 +#define BIT_MASK_H2CQ_HW_IDX_8814B 0xfff +#define BIT_H2CQ_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_H2CQ_HW_IDX_8814B) << BIT_SHIFT_H2CQ_HW_IDX_8814B) +#define BITS_H2CQ_HW_IDX_8814B \ + (BIT_MASK_H2CQ_HW_IDX_8814B << BIT_SHIFT_H2CQ_HW_IDX_8814B) +#define BIT_CLEAR_H2CQ_HW_IDX_8814B(x) ((x) & (~BITS_H2CQ_HW_IDX_8814B)) +#define BIT_GET_H2CQ_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8814B) & BIT_MASK_H2CQ_HW_IDX_8814B) +#define BIT_SET_H2CQ_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_H2CQ_HW_IDX_8814B(x) | BIT_H2CQ_HW_IDX_8814B(v)) +#define BIT_SHIFT_H2CQ_HOST_IDX_8814B 0 +#define BIT_MASK_H2CQ_HOST_IDX_8814B 0xfff +#define BIT_H2CQ_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_H2CQ_HOST_IDX_8814B) << BIT_SHIFT_H2CQ_HOST_IDX_8814B) +#define BITS_H2CQ_HOST_IDX_8814B \ + (BIT_MASK_H2CQ_HOST_IDX_8814B << BIT_SHIFT_H2CQ_HOST_IDX_8814B) +#define BIT_CLEAR_H2CQ_HOST_IDX_8814B(x) ((x) & (~BITS_H2CQ_HOST_IDX_8814B)) +#define BIT_GET_H2CQ_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8814B) & BIT_MASK_H2CQ_HOST_IDX_8814B) +#define BIT_SET_H2CQ_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_H2CQ_HOST_IDX_8814B(x) | BIT_H2CQ_HOST_IDX_8814B(v)) +/* 2 REG_H2CQ_CSR_8814B[31:0] (H2CQ CONTROL AND STATUS) */ +#define BIT_H2CQ_FULL_8814B BIT(31) +#define BIT_CLR_H2CQ_HOST_IDX_8814B BIT(16) +#define BIT_CLR_H2CQ_HW_IDX_8814B BIT(8) +#define BIT_STOP_H2CQ_8814B BIT(0) + +/* 2 REG_P0HI9Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI9Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI9Q_HW_IDX_8814B 0xfff +#define BIT_P0HI9Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI9Q_HW_IDX_8814B) << BIT_SHIFT_P0HI9Q_HW_IDX_8814B) +#define BITS_P0HI9Q_HW_IDX_8814B \ + (BIT_MASK_P0HI9Q_HW_IDX_8814B << BIT_SHIFT_P0HI9Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI9Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI9Q_HW_IDX_8814B)) +#define BIT_GET_P0HI9Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_HW_IDX_8814B) & BIT_MASK_P0HI9Q_HW_IDX_8814B) +#define BIT_SET_P0HI9Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI9Q_HW_IDX_8814B(x) | BIT_P0HI9Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI9Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI9Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI9Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI9Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI9Q_HOST_IDX_8814B) +#define BITS_P0HI9Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI9Q_HOST_IDX_8814B << BIT_SHIFT_P0HI9Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI9Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI9Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI9Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI9Q_HOST_IDX_8814B) +#define BIT_SET_P0HI9Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI9Q_HOST_IDX_8814B(x) | BIT_P0HI9Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI10Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI10Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI10Q_HW_IDX_8814B 0xfff +#define BIT_P0HI10Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI10Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI10Q_HW_IDX_8814B) +#define BITS_P0HI10Q_HW_IDX_8814B \ + (BIT_MASK_P0HI10Q_HW_IDX_8814B << BIT_SHIFT_P0HI10Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI10Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI10Q_HW_IDX_8814B)) +#define BIT_GET_P0HI10Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI10Q_HW_IDX_8814B) +#define BIT_SET_P0HI10Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI10Q_HW_IDX_8814B(x) | BIT_P0HI10Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI10Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI10Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI10Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI10Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI10Q_HOST_IDX_8814B) +#define BITS_P0HI10Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI10Q_HOST_IDX_8814B << BIT_SHIFT_P0HI10Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI10Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI10Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI10Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI10Q_HOST_IDX_8814B) +#define BIT_SET_P0HI10Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI10Q_HOST_IDX_8814B(x) | BIT_P0HI10Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI11Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI11Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI11Q_HW_IDX_8814B 0xfff +#define BIT_P0HI11Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI11Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI11Q_HW_IDX_8814B) +#define BITS_P0HI11Q_HW_IDX_8814B \ + (BIT_MASK_P0HI11Q_HW_IDX_8814B << BIT_SHIFT_P0HI11Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI11Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI11Q_HW_IDX_8814B)) +#define BIT_GET_P0HI11Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI11Q_HW_IDX_8814B) +#define BIT_SET_P0HI11Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI11Q_HW_IDX_8814B(x) | BIT_P0HI11Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI11Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI11Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI11Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI11Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI11Q_HOST_IDX_8814B) +#define BITS_P0HI11Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI11Q_HOST_IDX_8814B << BIT_SHIFT_P0HI11Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI11Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI11Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI11Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI11Q_HOST_IDX_8814B) +#define BIT_SET_P0HI11Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI11Q_HOST_IDX_8814B(x) | BIT_P0HI11Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI12Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI12Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI12Q_HW_IDX_8814B 0xfff +#define BIT_P0HI12Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI12Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI12Q_HW_IDX_8814B) +#define BITS_P0HI12Q_HW_IDX_8814B \ + (BIT_MASK_P0HI12Q_HW_IDX_8814B << BIT_SHIFT_P0HI12Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI12Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI12Q_HW_IDX_8814B)) +#define BIT_GET_P0HI12Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI12Q_HW_IDX_8814B) +#define BIT_SET_P0HI12Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI12Q_HW_IDX_8814B(x) | BIT_P0HI12Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI12Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI12Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI12Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI12Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI12Q_HOST_IDX_8814B) +#define BITS_P0HI12Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI12Q_HOST_IDX_8814B << BIT_SHIFT_P0HI12Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI12Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI12Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI12Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI12Q_HOST_IDX_8814B) +#define BIT_SET_P0HI12Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI12Q_HOST_IDX_8814B(x) | BIT_P0HI12Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI13Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI13Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI13Q_HW_IDX_8814B 0xfff +#define BIT_P0HI13Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI13Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI13Q_HW_IDX_8814B) +#define BITS_P0HI13Q_HW_IDX_8814B \ + (BIT_MASK_P0HI13Q_HW_IDX_8814B << BIT_SHIFT_P0HI13Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI13Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI13Q_HW_IDX_8814B)) +#define BIT_GET_P0HI13Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI13Q_HW_IDX_8814B) +#define BIT_SET_P0HI13Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI13Q_HW_IDX_8814B(x) | BIT_P0HI13Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI13Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI13Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI13Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI13Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI13Q_HOST_IDX_8814B) +#define BITS_P0HI13Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI13Q_HOST_IDX_8814B << BIT_SHIFT_P0HI13Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI13Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI13Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI13Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI13Q_HOST_IDX_8814B) +#define BIT_SET_P0HI13Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI13Q_HOST_IDX_8814B(x) | BIT_P0HI13Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI14Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI14Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI14Q_HW_IDX_8814B 0xfff +#define BIT_P0HI14Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI14Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI14Q_HW_IDX_8814B) +#define BITS_P0HI14Q_HW_IDX_8814B \ + (BIT_MASK_P0HI14Q_HW_IDX_8814B << BIT_SHIFT_P0HI14Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI14Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI14Q_HW_IDX_8814B)) +#define BIT_GET_P0HI14Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI14Q_HW_IDX_8814B) +#define BIT_SET_P0HI14Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI14Q_HW_IDX_8814B(x) | BIT_P0HI14Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI14Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI14Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI14Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI14Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI14Q_HOST_IDX_8814B) +#define BITS_P0HI14Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI14Q_HOST_IDX_8814B << BIT_SHIFT_P0HI14Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI14Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI14Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI14Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI14Q_HOST_IDX_8814B) +#define BIT_SET_P0HI14Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI14Q_HOST_IDX_8814B(x) | BIT_P0HI14Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI15Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI15Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI15Q_HW_IDX_8814B 0xfff +#define BIT_P0HI15Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI15Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI15Q_HW_IDX_8814B) +#define BITS_P0HI15Q_HW_IDX_8814B \ + (BIT_MASK_P0HI15Q_HW_IDX_8814B << BIT_SHIFT_P0HI15Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI15Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI15Q_HW_IDX_8814B)) +#define BIT_GET_P0HI15Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI15Q_HW_IDX_8814B) +#define BIT_SET_P0HI15Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI15Q_HW_IDX_8814B(x) | BIT_P0HI15Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI15Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI15Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI15Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI15Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI15Q_HOST_IDX_8814B) +#define BITS_P0HI15Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI15Q_HOST_IDX_8814B << BIT_SHIFT_P0HI15Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI15Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI15Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI15Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI15Q_HOST_IDX_8814B) +#define BIT_SET_P0HI15Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI15Q_HOST_IDX_8814B(x) | BIT_P0HI15Q_HOST_IDX_8814B(v)) + +/* 2 REG_CHANGE_PCIE_SPEED_8814B */ -/* 2 REG_MGQ_TXBD_NUM_8814B */ -#define BIT_PCIE_MGQ_FLAG_8814B BIT(14) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_MGQ_DESC_MODE_8814B 12 -#define BIT_MASK_MGQ_DESC_MODE_8814B 0x3 -#define BIT_MGQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8814B) << BIT_SHIFT_MGQ_DESC_MODE_8814B) -#define BIT_GET_MGQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8814B) & BIT_MASK_MGQ_DESC_MODE_8814B) +#define BIT_SHIFT_RXDMA_ERR_CNT_8814B 8 +#define BIT_MASK_RXDMA_ERR_CNT_8814B 0xff +#define BIT_RXDMA_ERR_CNT_8814B(x) \ + (((x) & BIT_MASK_RXDMA_ERR_CNT_8814B) << BIT_SHIFT_RXDMA_ERR_CNT_8814B) +#define BITS_RXDMA_ERR_CNT_8814B \ + (BIT_MASK_RXDMA_ERR_CNT_8814B << BIT_SHIFT_RXDMA_ERR_CNT_8814B) +#define BIT_CLEAR_RXDMA_ERR_CNT_8814B(x) ((x) & (~BITS_RXDMA_ERR_CNT_8814B)) +#define BIT_GET_RXDMA_ERR_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_RXDMA_ERR_CNT_8814B) & BIT_MASK_RXDMA_ERR_CNT_8814B) +#define BIT_SET_RXDMA_ERR_CNT_8814B(x, v) \ + (BIT_CLEAR_RXDMA_ERR_CNT_8814B(x) | BIT_RXDMA_ERR_CNT_8814B(v)) + +#define BIT_TXDMA_ERR_HANDLE_REQ_8814B BIT(7) +#define BIT_TXDMA_ERROR_PS_8814B BIT(6) +#define BIT_EN_TXDMA_STUCK_ERR_HANDLE_8814B BIT(5) +#define BIT_EN_TXDMA_RTN_ERR_HANDLE_8814B BIT(4) +#define BIT_RXDMA_ERR_HANDLE_REQ_8814B BIT(3) +#define BIT_RXDMA_ERROR_PS_8814B BIT(2) +#define BIT_EN_RXDMA_STUCK_ERR_HANDLE_8814B BIT(1) +#define BIT_EN_RXDMA_RTN_ERR_HANDLE_8814B BIT(0) + +/* 2 REG_DEBUG_STATE1_8814B */ + +#define BIT_SHIFT_DEBUG_STATE1_8814B 0 +#define BIT_MASK_DEBUG_STATE1_8814B 0xffffffffL +#define BIT_DEBUG_STATE1_8814B(x) \ + (((x) & BIT_MASK_DEBUG_STATE1_8814B) << BIT_SHIFT_DEBUG_STATE1_8814B) +#define BITS_DEBUG_STATE1_8814B \ + (BIT_MASK_DEBUG_STATE1_8814B << BIT_SHIFT_DEBUG_STATE1_8814B) +#define BIT_CLEAR_DEBUG_STATE1_8814B(x) ((x) & (~BITS_DEBUG_STATE1_8814B)) +#define BIT_GET_DEBUG_STATE1_8814B(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE1_8814B) & BIT_MASK_DEBUG_STATE1_8814B) +#define BIT_SET_DEBUG_STATE1_8814B(x, v) \ + (BIT_CLEAR_DEBUG_STATE1_8814B(x) | BIT_DEBUG_STATE1_8814B(v)) + +/* 2 REG_DEBUG_STATE2_8814B */ + +#define BIT_SHIFT_DEBUG_STATE2_8814B 0 +#define BIT_MASK_DEBUG_STATE2_8814B 0xffffffffL +#define BIT_DEBUG_STATE2_8814B(x) \ + (((x) & BIT_MASK_DEBUG_STATE2_8814B) << BIT_SHIFT_DEBUG_STATE2_8814B) +#define BITS_DEBUG_STATE2_8814B \ + (BIT_MASK_DEBUG_STATE2_8814B << BIT_SHIFT_DEBUG_STATE2_8814B) +#define BIT_CLEAR_DEBUG_STATE2_8814B(x) ((x) & (~BITS_DEBUG_STATE2_8814B)) +#define BIT_GET_DEBUG_STATE2_8814B(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE2_8814B) & BIT_MASK_DEBUG_STATE2_8814B) +#define BIT_SET_DEBUG_STATE2_8814B(x, v) \ + (BIT_CLEAR_DEBUG_STATE2_8814B(x) | BIT_DEBUG_STATE2_8814B(v)) + +/* 2 REG_DEBUG_STATE3_8814B */ + +#define BIT_SHIFT_DEBUG_STATE3_8814B 0 +#define BIT_MASK_DEBUG_STATE3_8814B 0xffffffffL +#define BIT_DEBUG_STATE3_8814B(x) \ + (((x) & BIT_MASK_DEBUG_STATE3_8814B) << BIT_SHIFT_DEBUG_STATE3_8814B) +#define BITS_DEBUG_STATE3_8814B \ + (BIT_MASK_DEBUG_STATE3_8814B << BIT_SHIFT_DEBUG_STATE3_8814B) +#define BIT_CLEAR_DEBUG_STATE3_8814B(x) ((x) & (~BITS_DEBUG_STATE3_8814B)) +#define BIT_GET_DEBUG_STATE3_8814B(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE3_8814B) & BIT_MASK_DEBUG_STATE3_8814B) +#define BIT_SET_DEBUG_STATE3_8814B(x, v) \ + (BIT_CLEAR_DEBUG_STATE3_8814B(x) | BIT_DEBUG_STATE3_8814B(v)) + +/* 2 REG_ACH5_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH5_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH5_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH5_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH5_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH5_TXBD_DESA_L_8814B) +#define BITS_ACH5_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH5_TXBD_DESA_L_8814B << BIT_SHIFT_ACH5_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH5_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH5_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH5_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH5_TXBD_DESA_L_8814B) +#define BIT_SET_ACH5_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH5_TXBD_DESA_L_8814B(x) | BIT_ACH5_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH5_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH5_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH5_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH5_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH5_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH5_TXBD_DESA_H_8814B) +#define BITS_ACH5_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH5_TXBD_DESA_H_8814B << BIT_SHIFT_ACH5_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH5_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH5_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH5_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH5_TXBD_DESA_H_8814B) +#define BIT_SET_ACH5_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH5_TXBD_DESA_H_8814B(x) | BIT_ACH5_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH6_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH6_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH6_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH6_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH6_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH6_TXBD_DESA_L_8814B) +#define BITS_ACH6_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH6_TXBD_DESA_L_8814B << BIT_SHIFT_ACH6_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH6_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH6_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH6_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH6_TXBD_DESA_L_8814B) +#define BIT_SET_ACH6_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH6_TXBD_DESA_L_8814B(x) | BIT_ACH6_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH6_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH6_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH6_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH6_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH6_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH6_TXBD_DESA_H_8814B) +#define BITS_ACH6_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH6_TXBD_DESA_H_8814B << BIT_SHIFT_ACH6_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH6_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH6_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH6_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH6_TXBD_DESA_H_8814B) +#define BIT_SET_ACH6_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH6_TXBD_DESA_H_8814B(x) | BIT_ACH6_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH7_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH7_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH7_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH7_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH7_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH7_TXBD_DESA_L_8814B) +#define BITS_ACH7_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH7_TXBD_DESA_L_8814B << BIT_SHIFT_ACH7_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH7_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH7_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH7_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH7_TXBD_DESA_L_8814B) +#define BIT_SET_ACH7_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH7_TXBD_DESA_L_8814B(x) | BIT_ACH7_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH7_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH7_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH7_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH7_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH7_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH7_TXBD_DESA_H_8814B) +#define BITS_ACH7_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH7_TXBD_DESA_H_8814B << BIT_SHIFT_ACH7_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH7_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH7_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH7_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH7_TXBD_DESA_H_8814B) +#define BIT_SET_ACH7_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH7_TXBD_DESA_H_8814B(x) | BIT_ACH7_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH8_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH8_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH8_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH8_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH8_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH8_TXBD_DESA_L_8814B) +#define BITS_ACH8_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH8_TXBD_DESA_L_8814B << BIT_SHIFT_ACH8_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH8_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH8_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH8_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH8_TXBD_DESA_L_8814B) +#define BIT_SET_ACH8_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH8_TXBD_DESA_L_8814B(x) | BIT_ACH8_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH8_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH8_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH8_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH8_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH8_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH8_TXBD_DESA_H_8814B) +#define BITS_ACH8_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH8_TXBD_DESA_H_8814B << BIT_SHIFT_ACH8_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH8_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH8_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH8_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH8_TXBD_DESA_H_8814B) +#define BIT_SET_ACH8_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH8_TXBD_DESA_H_8814B(x) | BIT_ACH8_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH9_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH9_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH9_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH9_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH9_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH9_TXBD_DESA_L_8814B) +#define BITS_ACH9_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH9_TXBD_DESA_L_8814B << BIT_SHIFT_ACH9_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH9_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH9_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH9_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH9_TXBD_DESA_L_8814B) +#define BIT_SET_ACH9_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH9_TXBD_DESA_L_8814B(x) | BIT_ACH9_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH9_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH9_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH9_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH9_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH9_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH9_TXBD_DESA_H_8814B) +#define BITS_ACH9_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH9_TXBD_DESA_H_8814B << BIT_SHIFT_ACH9_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH9_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH9_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH9_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH9_TXBD_DESA_H_8814B) +#define BIT_SET_ACH9_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH9_TXBD_DESA_H_8814B(x) | BIT_ACH9_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH10_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH10_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH10_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH10_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH10_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH10_TXBD_DESA_L_8814B) +#define BITS_ACH10_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH10_TXBD_DESA_L_8814B << BIT_SHIFT_ACH10_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH10_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH10_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH10_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH10_TXBD_DESA_L_8814B) +#define BIT_SET_ACH10_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH10_TXBD_DESA_L_8814B(x) | BIT_ACH10_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH10_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH10_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH10_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH10_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH10_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH10_TXBD_DESA_H_8814B) +#define BITS_ACH10_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH10_TXBD_DESA_H_8814B << BIT_SHIFT_ACH10_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH10_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH10_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH10_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH10_TXBD_DESA_H_8814B) +#define BIT_SET_ACH10_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH10_TXBD_DESA_H_8814B(x) | BIT_ACH10_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH11_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH11_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH11_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH11_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH11_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH11_TXBD_DESA_L_8814B) +#define BITS_ACH11_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH11_TXBD_DESA_L_8814B << BIT_SHIFT_ACH11_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH11_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH11_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH11_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH11_TXBD_DESA_L_8814B) +#define BIT_SET_ACH11_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH11_TXBD_DESA_L_8814B(x) | BIT_ACH11_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH11_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH11_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH11_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH11_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH11_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH11_TXBD_DESA_H_8814B) +#define BITS_ACH11_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH11_TXBD_DESA_H_8814B << BIT_SHIFT_ACH11_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH11_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH11_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH11_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH11_TXBD_DESA_H_8814B) +#define BIT_SET_ACH11_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH11_TXBD_DESA_H_8814B(x) | BIT_ACH11_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH12_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH12_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH12_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH12_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH12_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH12_TXBD_DESA_L_8814B) +#define BITS_ACH12_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH12_TXBD_DESA_L_8814B << BIT_SHIFT_ACH12_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH12_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH12_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH12_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH12_TXBD_DESA_L_8814B) +#define BIT_SET_ACH12_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH12_TXBD_DESA_L_8814B(x) | BIT_ACH12_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH12_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH12_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH12_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH12_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH12_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH12_TXBD_DESA_H_8814B) +#define BITS_ACH12_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH12_TXBD_DESA_H_8814B << BIT_SHIFT_ACH12_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH12_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH12_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH12_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH12_TXBD_DESA_H_8814B) +#define BIT_SET_ACH12_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH12_TXBD_DESA_H_8814B(x) | BIT_ACH12_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH13_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH13_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH13_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH13_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH13_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH13_TXBD_DESA_L_8814B) +#define BITS_ACH13_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH13_TXBD_DESA_L_8814B << BIT_SHIFT_ACH13_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH13_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH13_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH13_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH13_TXBD_DESA_L_8814B) +#define BIT_SET_ACH13_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH13_TXBD_DESA_L_8814B(x) | BIT_ACH13_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH13_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH13_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH13_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH13_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH13_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH13_TXBD_DESA_H_8814B) +#define BITS_ACH13_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH13_TXBD_DESA_H_8814B << BIT_SHIFT_ACH13_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH13_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH13_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH13_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH13_TXBD_DESA_H_8814B) +#define BIT_SET_ACH13_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH13_TXBD_DESA_H_8814B(x) | BIT_ACH13_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI0Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI0Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI0Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B) +#define BITS_HI0Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI0Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI0Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI0Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI0Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI0Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI0Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_L_8814B(x) | BIT_HI0Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI0Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI0Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI0Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B) +#define BITS_HI0Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI0Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI0Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI0Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI0Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI0Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI0Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_H_8814B(x) | BIT_HI0Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI1Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI1Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI1Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B) +#define BITS_HI1Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI1Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI1Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI1Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI1Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI1Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI1Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_L_8814B(x) | BIT_HI1Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI1Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI1Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI1Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B) +#define BITS_HI1Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI1Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI1Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI1Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI1Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI1Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI1Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_H_8814B(x) | BIT_HI1Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI2Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI2Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI2Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B) +#define BITS_HI2Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI2Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI2Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI2Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI2Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI2Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI2Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_L_8814B(x) | BIT_HI2Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI2Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI2Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI2Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B) +#define BITS_HI2Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI2Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI2Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI2Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI2Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI2Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI2Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_H_8814B(x) | BIT_HI2Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI3Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI3Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI3Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B) +#define BITS_HI3Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI3Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI3Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI3Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI3Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI3Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI3Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_L_8814B(x) | BIT_HI3Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI3Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI3Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI3Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B) +#define BITS_HI3Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI3Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI3Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI3Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI3Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI3Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI3Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_H_8814B(x) | BIT_HI3Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI4Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI4Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI4Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B) +#define BITS_HI4Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI4Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI4Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI4Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI4Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI4Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI4Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_L_8814B(x) | BIT_HI4Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI4Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI4Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI4Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B) +#define BITS_HI4Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI4Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI4Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI4Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI4Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI4Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI4Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_H_8814B(x) | BIT_HI4Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI5Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI5Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI5Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B) +#define BITS_HI5Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI5Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI5Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI5Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI5Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI5Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI5Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_L_8814B(x) | BIT_HI5Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI5Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI5Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI5Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B) +#define BITS_HI5Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI5Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI5Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI5Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI5Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI5Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI5Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_H_8814B(x) | BIT_HI5Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI6Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI6Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI6Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B) +#define BITS_HI6Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI6Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI6Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI6Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI6Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI6Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI6Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_L_8814B(x) | BIT_HI6Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI6Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI6Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI6Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B) +#define BITS_HI6Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI6Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI6Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI6Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI6Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI6Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI6Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_H_8814B(x) | BIT_HI6Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI7Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI7Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI7Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B) +#define BITS_HI7Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI7Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI7Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI7Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI7Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI7Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI7Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_L_8814B(x) | BIT_HI7Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI7Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI7Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI7Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B) +#define BITS_HI7Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI7Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI7Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI7Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI7Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI7Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI7Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_H_8814B(x) | BIT_HI7Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH8_ACH9_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH9_FLAG_8814B BIT(30) + +#define BIT_SHIFT_ACH9_DESC_MODE_8814B 28 +#define BIT_MASK_ACH9_DESC_MODE_8814B 0x3 +#define BIT_ACH9_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH9_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH9_DESC_MODE_8814B) +#define BITS_ACH9_DESC_MODE_8814B \ + (BIT_MASK_ACH9_DESC_MODE_8814B << BIT_SHIFT_ACH9_DESC_MODE_8814B) +#define BIT_CLEAR_ACH9_DESC_MODE_8814B(x) ((x) & (~BITS_ACH9_DESC_MODE_8814B)) +#define BIT_GET_ACH9_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH9_DESC_MODE_8814B) & \ + BIT_MASK_ACH9_DESC_MODE_8814B) +#define BIT_SET_ACH9_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH9_DESC_MODE_8814B(x) | BIT_ACH9_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH9_DESC_NUM_8814B 16 +#define BIT_MASK_ACH9_DESC_NUM_8814B 0xfff +#define BIT_ACH9_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH9_DESC_NUM_8814B) << BIT_SHIFT_ACH9_DESC_NUM_8814B) +#define BITS_ACH9_DESC_NUM_8814B \ + (BIT_MASK_ACH9_DESC_NUM_8814B << BIT_SHIFT_ACH9_DESC_NUM_8814B) +#define BIT_CLEAR_ACH9_DESC_NUM_8814B(x) ((x) & (~BITS_ACH9_DESC_NUM_8814B)) +#define BIT_GET_ACH9_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH9_DESC_NUM_8814B) & BIT_MASK_ACH9_DESC_NUM_8814B) +#define BIT_SET_ACH9_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH9_DESC_NUM_8814B(x) | BIT_ACH9_DESC_NUM_8814B(v)) + +#define BIT_PCIE_ACH8_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH8_DESC_MODE_8814B 12 +#define BIT_MASK_ACH8_DESC_MODE_8814B 0x3 +#define BIT_ACH8_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH8_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH8_DESC_MODE_8814B) +#define BITS_ACH8_DESC_MODE_8814B \ + (BIT_MASK_ACH8_DESC_MODE_8814B << BIT_SHIFT_ACH8_DESC_MODE_8814B) +#define BIT_CLEAR_ACH8_DESC_MODE_8814B(x) ((x) & (~BITS_ACH8_DESC_MODE_8814B)) +#define BIT_GET_ACH8_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH8_DESC_MODE_8814B) & \ + BIT_MASK_ACH8_DESC_MODE_8814B) +#define BIT_SET_ACH8_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH8_DESC_MODE_8814B(x) | BIT_ACH8_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH8_DESC_NUM_8814B 0 +#define BIT_MASK_ACH8_DESC_NUM_8814B 0xfff +#define BIT_ACH8_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH8_DESC_NUM_8814B) << BIT_SHIFT_ACH8_DESC_NUM_8814B) +#define BITS_ACH8_DESC_NUM_8814B \ + (BIT_MASK_ACH8_DESC_NUM_8814B << BIT_SHIFT_ACH8_DESC_NUM_8814B) +#define BIT_CLEAR_ACH8_DESC_NUM_8814B(x) ((x) & (~BITS_ACH8_DESC_NUM_8814B)) +#define BIT_GET_ACH8_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH8_DESC_NUM_8814B) & BIT_MASK_ACH8_DESC_NUM_8814B) +#define BIT_SET_ACH8_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH8_DESC_NUM_8814B(x) | BIT_ACH8_DESC_NUM_8814B(v)) + +/* 2 REG_ACH10_ACH11_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH11_FLAG_8814B BIT(30) + +#define BIT_SHIFT_ACH11_DESC_MODE_8814B 28 +#define BIT_MASK_ACH11_DESC_MODE_8814B 0x3 +#define BIT_ACH11_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH11_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH11_DESC_MODE_8814B) +#define BITS_ACH11_DESC_MODE_8814B \ + (BIT_MASK_ACH11_DESC_MODE_8814B << BIT_SHIFT_ACH11_DESC_MODE_8814B) +#define BIT_CLEAR_ACH11_DESC_MODE_8814B(x) ((x) & (~BITS_ACH11_DESC_MODE_8814B)) +#define BIT_GET_ACH11_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH11_DESC_MODE_8814B) & \ + BIT_MASK_ACH11_DESC_MODE_8814B) +#define BIT_SET_ACH11_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH11_DESC_MODE_8814B(x) | BIT_ACH11_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH11_DESC_NUM_8814B 16 +#define BIT_MASK_ACH11_DESC_NUM_8814B 0xfff +#define BIT_ACH11_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH11_DESC_NUM_8814B) \ + << BIT_SHIFT_ACH11_DESC_NUM_8814B) +#define BITS_ACH11_DESC_NUM_8814B \ + (BIT_MASK_ACH11_DESC_NUM_8814B << BIT_SHIFT_ACH11_DESC_NUM_8814B) +#define BIT_CLEAR_ACH11_DESC_NUM_8814B(x) ((x) & (~BITS_ACH11_DESC_NUM_8814B)) +#define BIT_GET_ACH11_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH11_DESC_NUM_8814B) & \ + BIT_MASK_ACH11_DESC_NUM_8814B) +#define BIT_SET_ACH11_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH11_DESC_NUM_8814B(x) | BIT_ACH11_DESC_NUM_8814B(v)) + +#define BIT_PCIE_ACH10_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH10_DESC_MODE_8814B 12 +#define BIT_MASK_ACH10_DESC_MODE_8814B 0x3 +#define BIT_ACH10_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH10_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH10_DESC_MODE_8814B) +#define BITS_ACH10_DESC_MODE_8814B \ + (BIT_MASK_ACH10_DESC_MODE_8814B << BIT_SHIFT_ACH10_DESC_MODE_8814B) +#define BIT_CLEAR_ACH10_DESC_MODE_8814B(x) ((x) & (~BITS_ACH10_DESC_MODE_8814B)) +#define BIT_GET_ACH10_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH10_DESC_MODE_8814B) & \ + BIT_MASK_ACH10_DESC_MODE_8814B) +#define BIT_SET_ACH10_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH10_DESC_MODE_8814B(x) | BIT_ACH10_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH10_DESC_NUM_8814B 0 +#define BIT_MASK_ACH10_DESC_NUM_8814B 0xfff +#define BIT_ACH10_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH10_DESC_NUM_8814B) \ + << BIT_SHIFT_ACH10_DESC_NUM_8814B) +#define BITS_ACH10_DESC_NUM_8814B \ + (BIT_MASK_ACH10_DESC_NUM_8814B << BIT_SHIFT_ACH10_DESC_NUM_8814B) +#define BIT_CLEAR_ACH10_DESC_NUM_8814B(x) ((x) & (~BITS_ACH10_DESC_NUM_8814B)) +#define BIT_GET_ACH10_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH10_DESC_NUM_8814B) & \ + BIT_MASK_ACH10_DESC_NUM_8814B) +#define BIT_SET_ACH10_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH10_DESC_NUM_8814B(x) | BIT_ACH10_DESC_NUM_8814B(v)) + +/* 2 REG_ACH12_ACH13_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH13_FLAG_8814B BIT(30) + +#define BIT_SHIFT_ACH13_DESC_MODE_8814B 28 +#define BIT_MASK_ACH13_DESC_MODE_8814B 0x3 +#define BIT_ACH13_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH13_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH13_DESC_MODE_8814B) +#define BITS_ACH13_DESC_MODE_8814B \ + (BIT_MASK_ACH13_DESC_MODE_8814B << BIT_SHIFT_ACH13_DESC_MODE_8814B) +#define BIT_CLEAR_ACH13_DESC_MODE_8814B(x) ((x) & (~BITS_ACH13_DESC_MODE_8814B)) +#define BIT_GET_ACH13_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH13_DESC_MODE_8814B) & \ + BIT_MASK_ACH13_DESC_MODE_8814B) +#define BIT_SET_ACH13_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH13_DESC_MODE_8814B(x) | BIT_ACH13_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH13_DESC_NUM_8814B 16 +#define BIT_MASK_ACH13_DESC_NUM_8814B 0xfff +#define BIT_ACH13_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH13_DESC_NUM_8814B) \ + << BIT_SHIFT_ACH13_DESC_NUM_8814B) +#define BITS_ACH13_DESC_NUM_8814B \ + (BIT_MASK_ACH13_DESC_NUM_8814B << BIT_SHIFT_ACH13_DESC_NUM_8814B) +#define BIT_CLEAR_ACH13_DESC_NUM_8814B(x) ((x) & (~BITS_ACH13_DESC_NUM_8814B)) +#define BIT_GET_ACH13_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH13_DESC_NUM_8814B) & \ + BIT_MASK_ACH13_DESC_NUM_8814B) +#define BIT_SET_ACH13_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH13_DESC_NUM_8814B(x) | BIT_ACH13_DESC_NUM_8814B(v)) + +#define BIT_PCIE_ACH12_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH12_DESC_MODE_8814B 12 +#define BIT_MASK_ACH12_DESC_MODE_8814B 0x3 +#define BIT_ACH12_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH12_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH12_DESC_MODE_8814B) +#define BITS_ACH12_DESC_MODE_8814B \ + (BIT_MASK_ACH12_DESC_MODE_8814B << BIT_SHIFT_ACH12_DESC_MODE_8814B) +#define BIT_CLEAR_ACH12_DESC_MODE_8814B(x) ((x) & (~BITS_ACH12_DESC_MODE_8814B)) +#define BIT_GET_ACH12_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH12_DESC_MODE_8814B) & \ + BIT_MASK_ACH12_DESC_MODE_8814B) +#define BIT_SET_ACH12_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH12_DESC_MODE_8814B(x) | BIT_ACH12_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH12_DESC_NUM_8814B 0 +#define BIT_MASK_ACH12_DESC_NUM_8814B 0xfff +#define BIT_ACH12_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH12_DESC_NUM_8814B) \ + << BIT_SHIFT_ACH12_DESC_NUM_8814B) +#define BITS_ACH12_DESC_NUM_8814B \ + (BIT_MASK_ACH12_DESC_NUM_8814B << BIT_SHIFT_ACH12_DESC_NUM_8814B) +#define BIT_CLEAR_ACH12_DESC_NUM_8814B(x) ((x) & (~BITS_ACH12_DESC_NUM_8814B)) +#define BIT_GET_ACH12_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH12_DESC_NUM_8814B) & \ + BIT_MASK_ACH12_DESC_NUM_8814B) +#define BIT_SET_ACH12_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH12_DESC_NUM_8814B(x) | BIT_ACH12_DESC_NUM_8814B(v)) + +/* 2 REG_OLD_DEHANG_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_OLD_DEHANG_8814B BIT(1) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_MGQ_DESC_NUM_8814B 0 -#define BIT_MASK_MGQ_DESC_NUM_8814B 0xfff -#define BIT_MGQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8814B) << BIT_SHIFT_MGQ_DESC_NUM_8814B) -#define BIT_GET_MGQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8814B) & BIT_MASK_MGQ_DESC_NUM_8814B) +/* 2 REG_ACH4_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH4_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH4_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH4_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH4_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH4_TXBD_DESA_L_8814B) +#define BITS_ACH4_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH4_TXBD_DESA_L_8814B << BIT_SHIFT_ACH4_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH4_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH4_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH4_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH4_TXBD_DESA_L_8814B) +#define BIT_SET_ACH4_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH4_TXBD_DESA_L_8814B(x) | BIT_ACH4_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH4_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH4_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH4_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH4_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH4_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH4_TXBD_DESA_H_8814B) +#define BITS_ACH4_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH4_TXBD_DESA_H_8814B << BIT_SHIFT_ACH4_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH4_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH4_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH4_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH4_TXBD_DESA_H_8814B) +#define BIT_SET_ACH4_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH4_TXBD_DESA_H_8814B(x) | BIT_ACH4_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI8Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI8Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI8Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI8Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B) +#define BITS_HI8Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI8Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI8Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI8Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI8Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI8Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI8Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI8Q_TXBD_DESA_L_8814B(x) | BIT_HI8Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI8Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI8Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI8Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI8Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B) +#define BITS_HI8Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI8Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI8Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI8Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI8Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI8Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI8Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI8Q_TXBD_DESA_H_8814B(x) | BIT_HI8Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI9Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI9Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI9Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI9Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B) +#define BITS_HI9Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI9Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI9Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI9Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI9Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI9Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI9Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI9Q_TXBD_DESA_L_8814B(x) | BIT_HI9Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI9Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI9Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI9Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI9Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B) +#define BITS_HI9Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI9Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI9Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI9Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI9Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI9Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI9Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI9Q_TXBD_DESA_H_8814B(x) | BIT_HI9Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI10Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI10Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI10Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI10Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B) +#define BITS_HI10Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI10Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI10Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI10Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI10Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI10Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI10Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI10Q_TXBD_DESA_L_8814B(x) | BIT_HI10Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI10Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI10Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI10Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI10Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B) +#define BITS_HI10Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI10Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI10Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI10Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI10Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI10Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI10Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI10Q_TXBD_DESA_H_8814B(x) | BIT_HI10Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI11Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI11Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI11Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI11Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B) +#define BITS_HI11Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI11Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI11Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI11Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI11Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI11Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI11Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI11Q_TXBD_DESA_L_8814B(x) | BIT_HI11Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI11Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI11Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI11Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI11Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B) +#define BITS_HI11Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI11Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI11Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI11Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI11Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI11Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI11Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI11Q_TXBD_DESA_H_8814B(x) | BIT_HI11Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI12Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI12Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI12Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI12Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B) +#define BITS_HI12Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI12Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI12Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI12Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI12Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI12Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI12Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI12Q_TXBD_DESA_L_8814B(x) | BIT_HI12Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI12Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI12Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI12Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI12Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B) +#define BITS_HI12Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI12Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI12Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI12Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI12Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI12Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI12Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI12Q_TXBD_DESA_H_8814B(x) | BIT_HI12Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI13Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI13Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI13Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI13Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B) +#define BITS_HI13Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI13Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI13Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI13Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI13Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI13Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI13Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI13Q_TXBD_DESA_L_8814B(x) | BIT_HI13Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI13Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI13Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI13Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI13Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B) +#define BITS_HI13Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI13Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI13Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI13Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI13Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI13Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI13Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI13Q_TXBD_DESA_H_8814B(x) | BIT_HI13Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI14Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI14Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI14Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI14Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B) +#define BITS_HI14Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI14Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI14Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI14Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI14Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI14Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI14Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI14Q_TXBD_DESA_L_8814B(x) | BIT_HI14Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI14Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI14Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI14Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI14Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B) +#define BITS_HI14Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI14Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI14Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI14Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI14Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI14Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI14Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI14Q_TXBD_DESA_H_8814B(x) | BIT_HI14Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI15Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI15Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI15Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI15Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B) +#define BITS_HI15Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI15Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI15Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI15Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI15Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI15Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI15Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI15Q_TXBD_DESA_L_8814B(x) | BIT_HI15Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI15Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI15Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI15Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI15Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B) +#define BITS_HI15Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI15Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI15Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI15Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI15Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI15Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI15Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI15Q_TXBD_DESA_H_8814B(x) | BIT_HI15Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI16Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI16Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI16Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI16Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B) +#define BITS_HI16Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI16Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI16Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI16Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI16Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI16Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI16Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI16Q_TXBD_DESA_L_8814B(x) | BIT_HI16Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI16Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI16Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI16Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI16Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B) +#define BITS_HI16Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI16Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI16Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI16Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI16Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI16Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI16Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI16Q_TXBD_DESA_H_8814B(x) | BIT_HI16Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI17Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI17Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI17Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI17Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B) +#define BITS_HI17Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI17Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI17Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI17Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI17Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI17Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI17Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI17Q_TXBD_DESA_L_8814B(x) | BIT_HI17Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI17Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI17Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI17Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI17Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B) +#define BITS_HI17Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI17Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI17Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI17Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI17Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI17Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI17Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI17Q_TXBD_DESA_H_8814B(x) | BIT_HI17Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI18Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI18Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI18Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI18Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B) +#define BITS_HI18Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI18Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI18Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI18Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI18Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI18Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI18Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI18Q_TXBD_DESA_L_8814B(x) | BIT_HI18Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI18Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI18Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI18Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI18Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B) +#define BITS_HI18Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI18Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI18Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI18Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI18Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI18Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI18Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI18Q_TXBD_DESA_H_8814B(x) | BIT_HI18Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI19Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI19Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI19Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI19Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B) +#define BITS_HI19Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI19Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI19Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI19Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI19Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI19Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI19Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI19Q_TXBD_DESA_L_8814B(x) | BIT_HI19Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI19Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI19Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI19Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI19Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B) +#define BITS_HI19Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI19Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI19Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI19Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI19Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI19Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI19Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI19Q_TXBD_DESA_H_8814B(x) | BIT_HI19Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_BD_RWPTR_CLR6_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_P0HI19Q_HW_IDX_8814B BIT(25) +#define BIT_CLR_P0HI18Q_HW_IDX_8814B BIT(24) +#define BIT_CLR_P0HI17Q_HW_IDX_8814B BIT(23) +#define BIT_CLR_P0HI16Q_HW_IDX_8814B BIT(22) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_P0HI19Q_HOST_IDX_8814B BIT(9) +#define BIT_CLR_P0HI18Q_HOST_IDX_8814B BIT(8) +#define BIT_CLR_P0HI17Q_HOST_IDX_8814B BIT(7) +#define BIT_CLR_P0HI16Q_HOST_IDX_8814B BIT(6) -/* 2 REG_RX_RXBD_NUM_8814B */ -#define BIT_SYS_32_64_8814B BIT(15) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCNQ_DESC_MODE_8814B 13 -#define BIT_MASK_BCNQ_DESC_MODE_8814B 0x3 -#define BIT_BCNQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8814B) << BIT_SHIFT_BCNQ_DESC_MODE_8814B) -#define BIT_GET_BCNQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8814B) & BIT_MASK_BCNQ_DESC_MODE_8814B) +/* 2 REG_P0HI16Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI16Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI16Q_HW_IDX_8814B 0xfff +#define BIT_P0HI16Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI16Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI16Q_HW_IDX_8814B) +#define BITS_P0HI16Q_HW_IDX_8814B \ + (BIT_MASK_P0HI16Q_HW_IDX_8814B << BIT_SHIFT_P0HI16Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI16Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI16Q_HW_IDX_8814B)) +#define BIT_GET_P0HI16Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI16Q_HW_IDX_8814B) +#define BIT_SET_P0HI16Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI16Q_HW_IDX_8814B(x) | BIT_P0HI16Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI16Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI16Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI16Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI16Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI16Q_HOST_IDX_8814B) +#define BITS_P0HI16Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI16Q_HOST_IDX_8814B << BIT_SHIFT_P0HI16Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI16Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI16Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI16Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI16Q_HOST_IDX_8814B) +#define BIT_SET_P0HI16Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI16Q_HOST_IDX_8814B(x) | BIT_P0HI16Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI17Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI17Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI17Q_HW_IDX_8814B 0xfff +#define BIT_P0HI17Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI17Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI17Q_HW_IDX_8814B) +#define BITS_P0HI17Q_HW_IDX_8814B \ + (BIT_MASK_P0HI17Q_HW_IDX_8814B << BIT_SHIFT_P0HI17Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI17Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI17Q_HW_IDX_8814B)) +#define BIT_GET_P0HI17Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI17Q_HW_IDX_8814B) +#define BIT_SET_P0HI17Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI17Q_HW_IDX_8814B(x) | BIT_P0HI17Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI17Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI17Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI17Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI17Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI17Q_HOST_IDX_8814B) +#define BITS_P0HI17Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI17Q_HOST_IDX_8814B << BIT_SHIFT_P0HI17Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI17Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI17Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI17Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI17Q_HOST_IDX_8814B) +#define BIT_SET_P0HI17Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI17Q_HOST_IDX_8814B(x) | BIT_P0HI17Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI18Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI18Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI18Q_HW_IDX_8814B 0xfff +#define BIT_P0HI18Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI18Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI18Q_HW_IDX_8814B) +#define BITS_P0HI18Q_HW_IDX_8814B \ + (BIT_MASK_P0HI18Q_HW_IDX_8814B << BIT_SHIFT_P0HI18Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI18Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI18Q_HW_IDX_8814B)) +#define BIT_GET_P0HI18Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI18Q_HW_IDX_8814B) +#define BIT_SET_P0HI18Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI18Q_HW_IDX_8814B(x) | BIT_P0HI18Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI18Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI18Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI18Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI18Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI18Q_HOST_IDX_8814B) +#define BITS_P0HI18Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI18Q_HOST_IDX_8814B << BIT_SHIFT_P0HI18Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI18Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI18Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI18Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI18Q_HOST_IDX_8814B) +#define BIT_SET_P0HI18Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI18Q_HOST_IDX_8814B(x) | BIT_P0HI18Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI19Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI19Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI19Q_HW_IDX_8814B 0xfff +#define BIT_P0HI19Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI19Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI19Q_HW_IDX_8814B) +#define BITS_P0HI19Q_HW_IDX_8814B \ + (BIT_MASK_P0HI19Q_HW_IDX_8814B << BIT_SHIFT_P0HI19Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI19Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI19Q_HW_IDX_8814B)) +#define BIT_GET_P0HI19Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI19Q_HW_IDX_8814B) +#define BIT_SET_P0HI19Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI19Q_HW_IDX_8814B(x) | BIT_P0HI19Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI19Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI19Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI19Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI19Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI19Q_HOST_IDX_8814B) +#define BITS_P0HI19Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI19Q_HOST_IDX_8814B << BIT_SHIFT_P0HI19Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI19Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI19Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI19Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI19Q_HOST_IDX_8814B) +#define BIT_SET_P0HI19Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI19Q_HOST_IDX_8814B(x) | BIT_P0HI19Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI16Q_HI17Q_TXBD_NUM_8814B */ +#define BIT_P0HI17Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI17Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI17Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI17Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI17Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI17Q_DESC_MODE_8814B) +#define BITS_P0HI17Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI17Q_DESC_MODE_8814B << BIT_SHIFT_P0HI17Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI17Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI17Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI17Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI17Q_DESC_MODE_8814B) +#define BIT_SET_P0HI17Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI17Q_DESC_MODE_8814B(x) | BIT_P0HI17Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI17Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI17Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI17Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI17Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI17Q_DESC_NUM_8814B) +#define BITS_P0HI17Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI17Q_DESC_NUM_8814B << BIT_SHIFT_P0HI17Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI17Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI17Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI17Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI17Q_DESC_NUM_8814B) +#define BIT_SET_P0HI17Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI17Q_DESC_NUM_8814B(x) | BIT_P0HI17Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI16Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI16Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI16Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI16Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI16Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI16Q_DESC_MODE_8814B) +#define BITS_P0HI16Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI16Q_DESC_MODE_8814B << BIT_SHIFT_P0HI16Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI16Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI16Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI16Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI16Q_DESC_MODE_8814B) +#define BIT_SET_P0HI16Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI16Q_DESC_MODE_8814B(x) | BIT_P0HI16Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI16Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI16Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI16Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI16Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI16Q_DESC_NUM_8814B) +#define BITS_P0HI16Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI16Q_DESC_NUM_8814B << BIT_SHIFT_P0HI16Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI16Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI16Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI16Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI16Q_DESC_NUM_8814B) +#define BIT_SET_P0HI16Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI16Q_DESC_NUM_8814B(x) | BIT_P0HI16Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI18Q_HI19Q_TXBD_NUM_8814B */ +#define BIT_P0HI19Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI19Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI19Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI19Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI19Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI19Q_DESC_MODE_8814B) +#define BITS_P0HI19Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI19Q_DESC_MODE_8814B << BIT_SHIFT_P0HI19Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI19Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI19Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI19Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI19Q_DESC_MODE_8814B) +#define BIT_SET_P0HI19Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI19Q_DESC_MODE_8814B(x) | BIT_P0HI19Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI19Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI19Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI19Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI19Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI19Q_DESC_NUM_8814B) +#define BITS_P0HI19Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI19Q_DESC_NUM_8814B << BIT_SHIFT_P0HI19Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI19Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI19Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI19Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI19Q_DESC_NUM_8814B) +#define BIT_SET_P0HI19Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI19Q_DESC_NUM_8814B(x) | BIT_P0HI19Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI18Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI18Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI18Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI18Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI18Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI18Q_DESC_MODE_8814B) +#define BITS_P0HI18Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI18Q_DESC_MODE_8814B << BIT_SHIFT_P0HI18Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI18Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI18Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI18Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI18Q_DESC_MODE_8814B) +#define BIT_SET_P0HI18Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI18Q_DESC_MODE_8814B(x) | BIT_P0HI18Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI18Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI18Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI18Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI18Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI18Q_DESC_NUM_8814B) +#define BITS_P0HI18Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI18Q_DESC_NUM_8814B << BIT_SHIFT_P0HI18Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI18Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI18Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI18Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI18Q_DESC_NUM_8814B) +#define BIT_SET_P0HI18Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI18Q_DESC_NUM_8814B(x) | BIT_P0HI18Q_DESC_NUM_8814B(v)) + +/* 2 REG_PCIE_HISR0_8814B */ +#define BIT_PSTIMER_2_8814B BIT(31) +#define BIT_PSTIMER_1_8814B BIT(30) +#define BIT_PSTIMER_0_8814B BIT(29) +#define BIT_GTINT4_8814B BIT(28) +#define BIT_GTINT3_8814B BIT(27) +#define BIT_TXBCN0ERR_8814B BIT(26) +#define BIT_TXBCN0OK_8814B BIT(25) +#define BIT_TSF_BIT32_TOGGLE_8814B BIT(24) +#define BIT_TXDMA_START_INT_8814B BIT(23) +#define BIT_TXDMA_STOP_INT_8814B BIT(22) +#define BIT_HISR7_IND_8814B BIT(21) +#define BIT_BCNDMAINT0_8814B BIT(20) +#define BIT_HISR6_IND_8814B BIT(19) +#define BIT_HISR5_IND_8814B BIT(18) +#define BIT_HISR4_IND_8814B BIT(17) +#define BIT_BCNDERR0_8814B BIT(16) +#define BIT_HSISR_IND_ON_INT_8814B BIT(15) +#define BIT_HISR3_IND_8814B BIT(14) +#define BIT_HISR2_IND_8814B BIT(13) +#define BIT_HISR1_IND_8814B BIT(11) +#define BIT_C2HCMD_8814B BIT(10) +#define BIT_CPWM2_8814B BIT(9) +#define BIT_CPWM_8814B BIT(8) +#define BIT_TXDMAOK_CHANNEL15_8814B BIT(7) +#define BIT_TXDMAOK_CHANNEL14_8814B BIT(6) +#define BIT_TXDMAOK_CHANNEL3_8814B BIT(5) +#define BIT_TXDMAOK_CHANNEL2_8814B BIT(4) +#define BIT_TXDMAOK_CHANNEL1_8814B BIT(3) +#define BIT_TXDMAOK_CHANNEL0_8814B BIT(2) +#define BIT_RDU_8814B BIT(1) +#define BIT_RXOK_8814B BIT(0) +/* 2 REG_PCIE_HISR1_8814B */ +#define BIT_PRE_TX_ERR_INT_8814B BIT(31) +#define BIT_TXFIFO_TH_INT_8814B BIT(30) +#define BIT_BTON_STS_UPDATE_INT_8814B BIT(29) +#define BIT_BCNDMAINT7_8814B BIT(27) +#define BIT_BCNDMAINT6_8814B BIT(26) +#define BIT_BCNDMAINT5_8814B BIT(25) +#define BIT_BCNDMAINT4_8814B BIT(24) +#define BIT_BCNDMAINT3_8814B BIT(23) +#define BIT_BCNDMAINT2_8814B BIT(22) +#define BIT_BCNDMAINT1_8814B BIT(21) +#define BIT_BCNDERR7_8814B BIT(20) +#define BIT_BCNDERR6_8814B BIT(19) +#define BIT_BCNDERR5_8814B BIT(18) +#define BIT_BCNDERR4_8814B BIT(17) +#define BIT_BCNDERR3_8814B BIT(16) +#define BIT_BCNDERR2_8814B BIT(15) +#define BIT_BCNDERR1_8814B BIT(14) +#define BIT_ATIMEND_8814B BIT(12) +#define BIT_TXERR_INT_8814B BIT(11) +#define BIT_RXERR_INT_8814B BIT(10) +#define BIT_TXFOVW_8814B BIT(9) +#define BIT_FOVW_8814B BIT(8) +#define BIT_CPU_MGQ_EARLY_INT_8814B BIT(6) +#define BIT_CPU_MGQ_TXDONE_8814B BIT(5) +#define BIT_PSTIMER_5_8814B BIT(4) +#define BIT_PSTIMER_4_8814B BIT(3) +#define BIT_PSTIMER_3_8814B BIT(2) +#define BIT_CPUMGQ_TX_TIMER_8814B BIT(1) +#define BIT_BB_STOPRX_INT_8814B BIT(0) + +/* 2 REG_P0HI8Q_HI9Q_TXBD_NUM_8814B */ +#define BIT_P0HI9Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI9Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI9Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI9Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI9Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI9Q_DESC_MODE_8814B) +#define BITS_P0HI9Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI9Q_DESC_MODE_8814B << BIT_SHIFT_P0HI9Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI9Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI9Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI9Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI9Q_DESC_MODE_8814B) +#define BIT_SET_P0HI9Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI9Q_DESC_MODE_8814B(x) | BIT_P0HI9Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI9Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI9Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI9Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI9Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI9Q_DESC_NUM_8814B) +#define BITS_P0HI9Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI9Q_DESC_NUM_8814B << BIT_SHIFT_P0HI9Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI9Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI9Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI9Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI9Q_DESC_NUM_8814B) +#define BIT_SET_P0HI9Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI9Q_DESC_NUM_8814B(x) | BIT_P0HI9Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI8Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI8Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI8Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI8Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI8Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI8Q_DESC_MODE_8814B) +#define BITS_P0HI8Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI8Q_DESC_MODE_8814B << BIT_SHIFT_P0HI8Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI8Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI8Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI8Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI8Q_DESC_MODE_8814B) +#define BIT_SET_P0HI8Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI8Q_DESC_MODE_8814B(x) | BIT_P0HI8Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI8Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI8Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI8Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI8Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI8Q_DESC_NUM_8814B) +#define BITS_P0HI8Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI8Q_DESC_NUM_8814B << BIT_SHIFT_P0HI8Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI8Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI8Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI8Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI8Q_DESC_NUM_8814B) +#define BIT_SET_P0HI8Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI8Q_DESC_NUM_8814B(x) | BIT_P0HI8Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI10Q_HI11Q_TXBD_NUM_8814B */ +#define BIT_P0HI11Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI11Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI11Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI11Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI11Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI11Q_DESC_MODE_8814B) +#define BITS_P0HI11Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI11Q_DESC_MODE_8814B << BIT_SHIFT_P0HI11Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI11Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI11Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI11Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI11Q_DESC_MODE_8814B) +#define BIT_SET_P0HI11Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI11Q_DESC_MODE_8814B(x) | BIT_P0HI11Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI11Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI11Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI11Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI11Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI11Q_DESC_NUM_8814B) +#define BITS_P0HI11Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI11Q_DESC_NUM_8814B << BIT_SHIFT_P0HI11Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI11Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI11Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI11Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI11Q_DESC_NUM_8814B) +#define BIT_SET_P0HI11Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI11Q_DESC_NUM_8814B(x) | BIT_P0HI11Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI10Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI10Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI10Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI10Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI10Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI10Q_DESC_MODE_8814B) +#define BITS_P0HI10Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI10Q_DESC_MODE_8814B << BIT_SHIFT_P0HI10Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI10Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI10Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI10Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI10Q_DESC_MODE_8814B) +#define BIT_SET_P0HI10Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI10Q_DESC_MODE_8814B(x) | BIT_P0HI10Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI10Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI10Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI10Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI10Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI10Q_DESC_NUM_8814B) +#define BITS_P0HI10Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI10Q_DESC_NUM_8814B << BIT_SHIFT_P0HI10Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI10Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI10Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI10Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI10Q_DESC_NUM_8814B) +#define BIT_SET_P0HI10Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI10Q_DESC_NUM_8814B(x) | BIT_P0HI10Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI12Q_HI13Q_TXBD_NUM_8814B */ +#define BIT_P0HI13Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI13Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI13Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI13Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI13Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI13Q_DESC_MODE_8814B) +#define BITS_P0HI13Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI13Q_DESC_MODE_8814B << BIT_SHIFT_P0HI13Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI13Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI13Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI13Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI13Q_DESC_MODE_8814B) +#define BIT_SET_P0HI13Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI13Q_DESC_MODE_8814B(x) | BIT_P0HI13Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI13Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI13Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI13Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI13Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI13Q_DESC_NUM_8814B) +#define BITS_P0HI13Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI13Q_DESC_NUM_8814B << BIT_SHIFT_P0HI13Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI13Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI13Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI13Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI13Q_DESC_NUM_8814B) +#define BIT_SET_P0HI13Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI13Q_DESC_NUM_8814B(x) | BIT_P0HI13Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI12Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI12Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI12Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI12Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI12Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI12Q_DESC_MODE_8814B) +#define BITS_P0HI12Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI12Q_DESC_MODE_8814B << BIT_SHIFT_P0HI12Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI12Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI12Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI12Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI12Q_DESC_MODE_8814B) +#define BIT_SET_P0HI12Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI12Q_DESC_MODE_8814B(x) | BIT_P0HI12Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI12Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI12Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI12Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI12Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI12Q_DESC_NUM_8814B) +#define BITS_P0HI12Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI12Q_DESC_NUM_8814B << BIT_SHIFT_P0HI12Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI12Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI12Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI12Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI12Q_DESC_NUM_8814B) +#define BIT_SET_P0HI12Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI12Q_DESC_NUM_8814B(x) | BIT_P0HI12Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI14Q_HI15Q_TXBD_NUM_8814B */ +#define BIT_P0HI15Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI15Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI15Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI15Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI15Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI15Q_DESC_MODE_8814B) +#define BITS_P0HI15Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI15Q_DESC_MODE_8814B << BIT_SHIFT_P0HI15Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI15Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI15Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI15Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI15Q_DESC_MODE_8814B) +#define BIT_SET_P0HI15Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI15Q_DESC_MODE_8814B(x) | BIT_P0HI15Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI15Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI15Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI15Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI15Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI15Q_DESC_NUM_8814B) +#define BITS_P0HI15Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI15Q_DESC_NUM_8814B << BIT_SHIFT_P0HI15Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI15Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI15Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI15Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI15Q_DESC_NUM_8814B) +#define BIT_SET_P0HI15Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI15Q_DESC_NUM_8814B(x) | BIT_P0HI15Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI14Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI14Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI14Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI14Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI14Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI14Q_DESC_MODE_8814B) +#define BITS_P0HI14Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI14Q_DESC_MODE_8814B << BIT_SHIFT_P0HI14Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI14Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI14Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI14Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI14Q_DESC_MODE_8814B) +#define BIT_SET_P0HI14Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI14Q_DESC_MODE_8814B(x) | BIT_P0HI14Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI14Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI14Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI14Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI14Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI14Q_DESC_NUM_8814B) +#define BITS_P0HI14Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI14Q_DESC_NUM_8814B << BIT_SHIFT_P0HI14Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI14Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI14Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI14Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI14Q_DESC_NUM_8814B) +#define BIT_SET_P0HI14Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI14Q_DESC_NUM_8814B(x) | BIT_P0HI14Q_DESC_NUM_8814B(v)) + +/* 2 REG_ACH6_ACH7_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH7_FLAG_8814B BIT(30) + +#define BIT_SHIFT_ACH7_DESC_MODE_8814B 28 +#define BIT_MASK_ACH7_DESC_MODE_8814B 0x3 +#define BIT_ACH7_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH7_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH7_DESC_MODE_8814B) +#define BITS_ACH7_DESC_MODE_8814B \ + (BIT_MASK_ACH7_DESC_MODE_8814B << BIT_SHIFT_ACH7_DESC_MODE_8814B) +#define BIT_CLEAR_ACH7_DESC_MODE_8814B(x) ((x) & (~BITS_ACH7_DESC_MODE_8814B)) +#define BIT_GET_ACH7_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH7_DESC_MODE_8814B) & \ + BIT_MASK_ACH7_DESC_MODE_8814B) +#define BIT_SET_ACH7_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH7_DESC_MODE_8814B(x) | BIT_ACH7_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH7_DESC_NUM_8814B 16 +#define BIT_MASK_ACH7_DESC_NUM_8814B 0xfff +#define BIT_ACH7_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH7_DESC_NUM_8814B) << BIT_SHIFT_ACH7_DESC_NUM_8814B) +#define BITS_ACH7_DESC_NUM_8814B \ + (BIT_MASK_ACH7_DESC_NUM_8814B << BIT_SHIFT_ACH7_DESC_NUM_8814B) +#define BIT_CLEAR_ACH7_DESC_NUM_8814B(x) ((x) & (~BITS_ACH7_DESC_NUM_8814B)) +#define BIT_GET_ACH7_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH7_DESC_NUM_8814B) & BIT_MASK_ACH7_DESC_NUM_8814B) +#define BIT_SET_ACH7_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH7_DESC_NUM_8814B(x) | BIT_ACH7_DESC_NUM_8814B(v)) + +#define BIT_PCIE_ACH6_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH6_DESC_MODE_8814B 12 +#define BIT_MASK_ACH6_DESC_MODE_8814B 0x3 +#define BIT_ACH6_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH6_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH6_DESC_MODE_8814B) +#define BITS_ACH6_DESC_MODE_8814B \ + (BIT_MASK_ACH6_DESC_MODE_8814B << BIT_SHIFT_ACH6_DESC_MODE_8814B) +#define BIT_CLEAR_ACH6_DESC_MODE_8814B(x) ((x) & (~BITS_ACH6_DESC_MODE_8814B)) +#define BIT_GET_ACH6_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH6_DESC_MODE_8814B) & \ + BIT_MASK_ACH6_DESC_MODE_8814B) +#define BIT_SET_ACH6_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH6_DESC_MODE_8814B(x) | BIT_ACH6_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH6_DESC_NUM_8814B 0 +#define BIT_MASK_ACH6_DESC_NUM_8814B 0xfff +#define BIT_ACH6_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH6_DESC_NUM_8814B) << BIT_SHIFT_ACH6_DESC_NUM_8814B) +#define BITS_ACH6_DESC_NUM_8814B \ + (BIT_MASK_ACH6_DESC_NUM_8814B << BIT_SHIFT_ACH6_DESC_NUM_8814B) +#define BIT_CLEAR_ACH6_DESC_NUM_8814B(x) ((x) & (~BITS_ACH6_DESC_NUM_8814B)) +#define BIT_GET_ACH6_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH6_DESC_NUM_8814B) & BIT_MASK_ACH6_DESC_NUM_8814B) +#define BIT_SET_ACH6_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH6_DESC_NUM_8814B(x) | BIT_ACH6_DESC_NUM_8814B(v)) + +/* 2 REG_ACH4_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH4_HW_IDX_8814B 16 +#define BIT_MASK_ACH4_HW_IDX_8814B 0xfff +#define BIT_ACH4_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH4_HW_IDX_8814B) << BIT_SHIFT_ACH4_HW_IDX_8814B) +#define BITS_ACH4_HW_IDX_8814B \ + (BIT_MASK_ACH4_HW_IDX_8814B << BIT_SHIFT_ACH4_HW_IDX_8814B) +#define BIT_CLEAR_ACH4_HW_IDX_8814B(x) ((x) & (~BITS_ACH4_HW_IDX_8814B)) +#define BIT_GET_ACH4_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH4_HW_IDX_8814B) & BIT_MASK_ACH4_HW_IDX_8814B) +#define BIT_SET_ACH4_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH4_HW_IDX_8814B(x) | BIT_ACH4_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH4_HOST_IDX_8814B 0 +#define BIT_MASK_ACH4_HOST_IDX_8814B 0xfff +#define BIT_ACH4_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH4_HOST_IDX_8814B) << BIT_SHIFT_ACH4_HOST_IDX_8814B) +#define BITS_ACH4_HOST_IDX_8814B \ + (BIT_MASK_ACH4_HOST_IDX_8814B << BIT_SHIFT_ACH4_HOST_IDX_8814B) +#define BIT_CLEAR_ACH4_HOST_IDX_8814B(x) ((x) & (~BITS_ACH4_HOST_IDX_8814B)) +#define BIT_GET_ACH4_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH4_HOST_IDX_8814B) & BIT_MASK_ACH4_HOST_IDX_8814B) +#define BIT_SET_ACH4_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH4_HOST_IDX_8814B(x) | BIT_ACH4_HOST_IDX_8814B(v)) + +/* 2 REG_ACH5_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH5_HW_IDX_8814B 16 +#define BIT_MASK_ACH5_HW_IDX_8814B 0xfff +#define BIT_ACH5_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH5_HW_IDX_8814B) << BIT_SHIFT_ACH5_HW_IDX_8814B) +#define BITS_ACH5_HW_IDX_8814B \ + (BIT_MASK_ACH5_HW_IDX_8814B << BIT_SHIFT_ACH5_HW_IDX_8814B) +#define BIT_CLEAR_ACH5_HW_IDX_8814B(x) ((x) & (~BITS_ACH5_HW_IDX_8814B)) +#define BIT_GET_ACH5_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH5_HW_IDX_8814B) & BIT_MASK_ACH5_HW_IDX_8814B) +#define BIT_SET_ACH5_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH5_HW_IDX_8814B(x) | BIT_ACH5_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH5_HOST_IDX_8814B 0 +#define BIT_MASK_ACH5_HOST_IDX_8814B 0xfff +#define BIT_ACH5_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH5_HOST_IDX_8814B) << BIT_SHIFT_ACH5_HOST_IDX_8814B) +#define BITS_ACH5_HOST_IDX_8814B \ + (BIT_MASK_ACH5_HOST_IDX_8814B << BIT_SHIFT_ACH5_HOST_IDX_8814B) +#define BIT_CLEAR_ACH5_HOST_IDX_8814B(x) ((x) & (~BITS_ACH5_HOST_IDX_8814B)) +#define BIT_GET_ACH5_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH5_HOST_IDX_8814B) & BIT_MASK_ACH5_HOST_IDX_8814B) +#define BIT_SET_ACH5_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH5_HOST_IDX_8814B(x) | BIT_ACH5_HOST_IDX_8814B(v)) + +/* 2 REG_ACH6_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH6_HW_IDX_8814B 16 +#define BIT_MASK_ACH6_HW_IDX_8814B 0xfff +#define BIT_ACH6_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH6_HW_IDX_8814B) << BIT_SHIFT_ACH6_HW_IDX_8814B) +#define BITS_ACH6_HW_IDX_8814B \ + (BIT_MASK_ACH6_HW_IDX_8814B << BIT_SHIFT_ACH6_HW_IDX_8814B) +#define BIT_CLEAR_ACH6_HW_IDX_8814B(x) ((x) & (~BITS_ACH6_HW_IDX_8814B)) +#define BIT_GET_ACH6_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH6_HW_IDX_8814B) & BIT_MASK_ACH6_HW_IDX_8814B) +#define BIT_SET_ACH6_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH6_HW_IDX_8814B(x) | BIT_ACH6_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH6_HOST_IDX_8814B 0 +#define BIT_MASK_ACH6_HOST_IDX_8814B 0xfff +#define BIT_ACH6_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH6_HOST_IDX_8814B) << BIT_SHIFT_ACH6_HOST_IDX_8814B) +#define BITS_ACH6_HOST_IDX_8814B \ + (BIT_MASK_ACH6_HOST_IDX_8814B << BIT_SHIFT_ACH6_HOST_IDX_8814B) +#define BIT_CLEAR_ACH6_HOST_IDX_8814B(x) ((x) & (~BITS_ACH6_HOST_IDX_8814B)) +#define BIT_GET_ACH6_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH6_HOST_IDX_8814B) & BIT_MASK_ACH6_HOST_IDX_8814B) +#define BIT_SET_ACH6_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH6_HOST_IDX_8814B(x) | BIT_ACH6_HOST_IDX_8814B(v)) + +/* 2 REG_ACH7_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH7_HW_IDX_8814B 16 +#define BIT_MASK_ACH7_HW_IDX_8814B 0xfff +#define BIT_ACH7_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH7_HW_IDX_8814B) << BIT_SHIFT_ACH7_HW_IDX_8814B) +#define BITS_ACH7_HW_IDX_8814B \ + (BIT_MASK_ACH7_HW_IDX_8814B << BIT_SHIFT_ACH7_HW_IDX_8814B) +#define BIT_CLEAR_ACH7_HW_IDX_8814B(x) ((x) & (~BITS_ACH7_HW_IDX_8814B)) +#define BIT_GET_ACH7_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH7_HW_IDX_8814B) & BIT_MASK_ACH7_HW_IDX_8814B) +#define BIT_SET_ACH7_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH7_HW_IDX_8814B(x) | BIT_ACH7_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH7_HOST_IDX_8814B 0 +#define BIT_MASK_ACH7_HOST_IDX_8814B 0xfff +#define BIT_ACH7_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH7_HOST_IDX_8814B) << BIT_SHIFT_ACH7_HOST_IDX_8814B) +#define BITS_ACH7_HOST_IDX_8814B \ + (BIT_MASK_ACH7_HOST_IDX_8814B << BIT_SHIFT_ACH7_HOST_IDX_8814B) +#define BIT_CLEAR_ACH7_HOST_IDX_8814B(x) ((x) & (~BITS_ACH7_HOST_IDX_8814B)) +#define BIT_GET_ACH7_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH7_HOST_IDX_8814B) & BIT_MASK_ACH7_HOST_IDX_8814B) +#define BIT_SET_ACH7_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH7_HOST_IDX_8814B(x) | BIT_ACH7_HOST_IDX_8814B(v)) + +/* 2 REG_ACH8_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH8_HW_IDX_8814B 16 +#define BIT_MASK_ACH8_HW_IDX_8814B 0xfff +#define BIT_ACH8_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH8_HW_IDX_8814B) << BIT_SHIFT_ACH8_HW_IDX_8814B) +#define BITS_ACH8_HW_IDX_8814B \ + (BIT_MASK_ACH8_HW_IDX_8814B << BIT_SHIFT_ACH8_HW_IDX_8814B) +#define BIT_CLEAR_ACH8_HW_IDX_8814B(x) ((x) & (~BITS_ACH8_HW_IDX_8814B)) +#define BIT_GET_ACH8_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH8_HW_IDX_8814B) & BIT_MASK_ACH8_HW_IDX_8814B) +#define BIT_SET_ACH8_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH8_HW_IDX_8814B(x) | BIT_ACH8_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH8_HOST_IDX_8814B 0 +#define BIT_MASK_ACH8_HOST_IDX_8814B 0xfff +#define BIT_ACH8_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH8_HOST_IDX_8814B) << BIT_SHIFT_ACH8_HOST_IDX_8814B) +#define BITS_ACH8_HOST_IDX_8814B \ + (BIT_MASK_ACH8_HOST_IDX_8814B << BIT_SHIFT_ACH8_HOST_IDX_8814B) +#define BIT_CLEAR_ACH8_HOST_IDX_8814B(x) ((x) & (~BITS_ACH8_HOST_IDX_8814B)) +#define BIT_GET_ACH8_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH8_HOST_IDX_8814B) & BIT_MASK_ACH8_HOST_IDX_8814B) +#define BIT_SET_ACH8_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH8_HOST_IDX_8814B(x) | BIT_ACH8_HOST_IDX_8814B(v)) + +/* 2 REG_ACH9_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH9_HW_IDX_8814B 16 +#define BIT_MASK_ACH9_HW_IDX_8814B 0xfff +#define BIT_ACH9_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH9_HW_IDX_8814B) << BIT_SHIFT_ACH9_HW_IDX_8814B) +#define BITS_ACH9_HW_IDX_8814B \ + (BIT_MASK_ACH9_HW_IDX_8814B << BIT_SHIFT_ACH9_HW_IDX_8814B) +#define BIT_CLEAR_ACH9_HW_IDX_8814B(x) ((x) & (~BITS_ACH9_HW_IDX_8814B)) +#define BIT_GET_ACH9_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH9_HW_IDX_8814B) & BIT_MASK_ACH9_HW_IDX_8814B) +#define BIT_SET_ACH9_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH9_HW_IDX_8814B(x) | BIT_ACH9_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH9_HOST_IDX_8814B 0 +#define BIT_MASK_ACH9_HOST_IDX_8814B 0xfff +#define BIT_ACH9_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH9_HOST_IDX_8814B) << BIT_SHIFT_ACH9_HOST_IDX_8814B) +#define BITS_ACH9_HOST_IDX_8814B \ + (BIT_MASK_ACH9_HOST_IDX_8814B << BIT_SHIFT_ACH9_HOST_IDX_8814B) +#define BIT_CLEAR_ACH9_HOST_IDX_8814B(x) ((x) & (~BITS_ACH9_HOST_IDX_8814B)) +#define BIT_GET_ACH9_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH9_HOST_IDX_8814B) & BIT_MASK_ACH9_HOST_IDX_8814B) +#define BIT_SET_ACH9_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH9_HOST_IDX_8814B(x) | BIT_ACH9_HOST_IDX_8814B(v)) + +/* 2 REG_ACH10_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH10_HW_IDX_8814B 16 +#define BIT_MASK_ACH10_HW_IDX_8814B 0xfff +#define BIT_ACH10_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH10_HW_IDX_8814B) << BIT_SHIFT_ACH10_HW_IDX_8814B) +#define BITS_ACH10_HW_IDX_8814B \ + (BIT_MASK_ACH10_HW_IDX_8814B << BIT_SHIFT_ACH10_HW_IDX_8814B) +#define BIT_CLEAR_ACH10_HW_IDX_8814B(x) ((x) & (~BITS_ACH10_HW_IDX_8814B)) +#define BIT_GET_ACH10_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH10_HW_IDX_8814B) & BIT_MASK_ACH10_HW_IDX_8814B) +#define BIT_SET_ACH10_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH10_HW_IDX_8814B(x) | BIT_ACH10_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH10_HOST_IDX_8814B 0 +#define BIT_MASK_ACH10_HOST_IDX_8814B 0xfff +#define BIT_ACH10_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH10_HOST_IDX_8814B) \ + << BIT_SHIFT_ACH10_HOST_IDX_8814B) +#define BITS_ACH10_HOST_IDX_8814B \ + (BIT_MASK_ACH10_HOST_IDX_8814B << BIT_SHIFT_ACH10_HOST_IDX_8814B) +#define BIT_CLEAR_ACH10_HOST_IDX_8814B(x) ((x) & (~BITS_ACH10_HOST_IDX_8814B)) +#define BIT_GET_ACH10_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH10_HOST_IDX_8814B) & \ + BIT_MASK_ACH10_HOST_IDX_8814B) +#define BIT_SET_ACH10_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH10_HOST_IDX_8814B(x) | BIT_ACH10_HOST_IDX_8814B(v)) + +/* 2 REG_ACH11_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH11_HW_IDX_8814B 16 +#define BIT_MASK_ACH11_HW_IDX_8814B 0xfff +#define BIT_ACH11_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH11_HW_IDX_8814B) << BIT_SHIFT_ACH11_HW_IDX_8814B) +#define BITS_ACH11_HW_IDX_8814B \ + (BIT_MASK_ACH11_HW_IDX_8814B << BIT_SHIFT_ACH11_HW_IDX_8814B) +#define BIT_CLEAR_ACH11_HW_IDX_8814B(x) ((x) & (~BITS_ACH11_HW_IDX_8814B)) +#define BIT_GET_ACH11_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH11_HW_IDX_8814B) & BIT_MASK_ACH11_HW_IDX_8814B) +#define BIT_SET_ACH11_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH11_HW_IDX_8814B(x) | BIT_ACH11_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH11_HOST_IDX_8814B 0 +#define BIT_MASK_ACH11_HOST_IDX_8814B 0xfff +#define BIT_ACH11_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH11_HOST_IDX_8814B) \ + << BIT_SHIFT_ACH11_HOST_IDX_8814B) +#define BITS_ACH11_HOST_IDX_8814B \ + (BIT_MASK_ACH11_HOST_IDX_8814B << BIT_SHIFT_ACH11_HOST_IDX_8814B) +#define BIT_CLEAR_ACH11_HOST_IDX_8814B(x) ((x) & (~BITS_ACH11_HOST_IDX_8814B)) +#define BIT_GET_ACH11_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH11_HOST_IDX_8814B) & \ + BIT_MASK_ACH11_HOST_IDX_8814B) +#define BIT_SET_ACH11_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH11_HOST_IDX_8814B(x) | BIT_ACH11_HOST_IDX_8814B(v)) + +/* 2 REG_ACH12_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH12_HW_IDX_8814B 16 +#define BIT_MASK_ACH12_HW_IDX_8814B 0xfff +#define BIT_ACH12_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH12_HW_IDX_8814B) << BIT_SHIFT_ACH12_HW_IDX_8814B) +#define BITS_ACH12_HW_IDX_8814B \ + (BIT_MASK_ACH12_HW_IDX_8814B << BIT_SHIFT_ACH12_HW_IDX_8814B) +#define BIT_CLEAR_ACH12_HW_IDX_8814B(x) ((x) & (~BITS_ACH12_HW_IDX_8814B)) +#define BIT_GET_ACH12_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH12_HW_IDX_8814B) & BIT_MASK_ACH12_HW_IDX_8814B) +#define BIT_SET_ACH12_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH12_HW_IDX_8814B(x) | BIT_ACH12_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH12_HOST_IDX_8814B 0 +#define BIT_MASK_ACH12_HOST_IDX_8814B 0xfff +#define BIT_ACH12_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH12_HOST_IDX_8814B) \ + << BIT_SHIFT_ACH12_HOST_IDX_8814B) +#define BITS_ACH12_HOST_IDX_8814B \ + (BIT_MASK_ACH12_HOST_IDX_8814B << BIT_SHIFT_ACH12_HOST_IDX_8814B) +#define BIT_CLEAR_ACH12_HOST_IDX_8814B(x) ((x) & (~BITS_ACH12_HOST_IDX_8814B)) +#define BIT_GET_ACH12_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH12_HOST_IDX_8814B) & \ + BIT_MASK_ACH12_HOST_IDX_8814B) +#define BIT_SET_ACH12_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH12_HOST_IDX_8814B(x) | BIT_ACH12_HOST_IDX_8814B(v)) + +/* 2 REG_ACH13_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH13_HW_IDX_8814B 16 +#define BIT_MASK_ACH13_HW_IDX_8814B 0xfff +#define BIT_ACH13_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH13_HW_IDX_8814B) << BIT_SHIFT_ACH13_HW_IDX_8814B) +#define BITS_ACH13_HW_IDX_8814B \ + (BIT_MASK_ACH13_HW_IDX_8814B << BIT_SHIFT_ACH13_HW_IDX_8814B) +#define BIT_CLEAR_ACH13_HW_IDX_8814B(x) ((x) & (~BITS_ACH13_HW_IDX_8814B)) +#define BIT_GET_ACH13_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH13_HW_IDX_8814B) & BIT_MASK_ACH13_HW_IDX_8814B) +#define BIT_SET_ACH13_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH13_HW_IDX_8814B(x) | BIT_ACH13_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH13_HOST_IDX_8814B 0 +#define BIT_MASK_ACH13_HOST_IDX_8814B 0xfff +#define BIT_ACH13_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH13_HOST_IDX_8814B) \ + << BIT_SHIFT_ACH13_HOST_IDX_8814B) +#define BITS_ACH13_HOST_IDX_8814B \ + (BIT_MASK_ACH13_HOST_IDX_8814B << BIT_SHIFT_ACH13_HOST_IDX_8814B) +#define BIT_CLEAR_ACH13_HOST_IDX_8814B(x) ((x) & (~BITS_ACH13_HOST_IDX_8814B)) +#define BIT_GET_ACH13_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH13_HOST_IDX_8814B) & \ + BIT_MASK_ACH13_HOST_IDX_8814B) +#define BIT_SET_ACH13_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH13_HOST_IDX_8814B(x) | BIT_ACH13_HOST_IDX_8814B(v)) + +/* 2 REG_AC_CHANNEL0_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL0_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL0_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL0_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B) +#define BITS_AC_CHANNEL0_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL0_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL0_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL0_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL0_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL0_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL0_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL0_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL0_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL1_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL1_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL1_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL1_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B) +#define BITS_AC_CHANNEL1_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL1_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL1_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL1_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL1_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL1_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL1_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL1_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL1_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL2_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL2_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL2_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL2_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B) +#define BITS_AC_CHANNEL2_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL2_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL2_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL2_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL2_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL2_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL2_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL2_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL2_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL3_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL3_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL3_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL3_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B) +#define BITS_AC_CHANNEL3_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL3_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL3_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL3_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL3_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL3_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL3_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL3_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL3_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL4_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL4_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL4_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL4_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B) +#define BITS_AC_CHANNEL4_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL4_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL4_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL4_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL4_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL4_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL4_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL4_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL4_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL5_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL5_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL5_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL5_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B) +#define BITS_AC_CHANNEL5_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL5_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL5_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL5_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL5_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL5_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL5_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL5_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL5_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL6_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL6_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL6_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL6_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B) +#define BITS_AC_CHANNEL6_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL6_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL6_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL6_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL6_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL6_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL6_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL6_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL6_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL7_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL7_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL7_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL7_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B) +#define BITS_AC_CHANNEL7_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL7_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL7_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL7_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL7_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL7_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL7_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL7_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL7_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL8_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL8_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL8_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL8_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B) +#define BITS_AC_CHANNEL8_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL8_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL8_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL8_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL8_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL8_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL8_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL8_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL8_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL9_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL9_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL9_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL9_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B) +#define BITS_AC_CHANNEL9_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL9_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL9_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL9_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL9_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL9_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL9_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL9_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL9_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL10_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL10_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL10_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL10_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B) +#define BITS_AC_CHANNEL10_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL10_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL10_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL10_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL10_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL10_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL10_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL10_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL10_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL11_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL11_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL11_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL11_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B) +#define BITS_AC_CHANNEL11_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL11_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL11_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL11_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL11_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL11_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL11_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL11_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL11_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL12_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL12_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL12_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL12_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B) +#define BITS_AC_CHANNEL12_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL12_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL12_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL12_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL12_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL12_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL12_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL12_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL12_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL13_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL13_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL13_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL13_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B) +#define BITS_AC_CHANNEL13_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL13_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL13_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL13_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL13_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL13_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL13_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL13_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL13_WEIGHT_8814B(v)) + +/* 2 REG_PCIE_HISR2_8814B */ +#define BIT_BCNDMAINT_P4_8814B BIT(31) +#define BIT_BCNDMAINT_P3_8814B BIT(30) +#define BIT_BCNDMAINT_P2_8814B BIT(29) +#define BIT_BCNDMAINT_P1_8814B BIT(28) +#define BIT_SCH_PHY_TXOP_SIFS_INT_8814B BIT(23) +#define BIT_ATIMEND7_8814B BIT(22) +#define BIT_ATIMEND6_8814B BIT(21) +#define BIT_ATIMEND5_8814B BIT(20) +#define BIT_ATIMEND4_8814B BIT(19) +#define BIT_ATIMEND3_8814B BIT(18) +#define BIT_ATIMEND2_8814B BIT(17) +#define BIT_ATIMEND1_8814B BIT(16) +#define BIT_TXBCN7OK_8814B BIT(14) +#define BIT_TXBCN6OK_8814B BIT(13) +#define BIT_TXBCN5OK_8814B BIT(12) +#define BIT_TXBCN4OK_8814B BIT(11) +#define BIT_TXBCN3OK_8814B BIT(10) +#define BIT_TXBCN2OK_8814B BIT(9) +#define BIT_TXBCN1OK_8814B BIT(8) +#define BIT_TXBCN7ERR_8814B BIT(6) +#define BIT_TXBCN6ERR_8814B BIT(5) +#define BIT_TXBCN5ERR_8814B BIT(4) +#define BIT_TXBCN4ERR_8814B BIT(3) +#define BIT_TXBCN3ERR_8814B BIT(2) +#define BIT_TXBCN2ERR_8814B BIT(1) +#define BIT_TXBCN1ERR_8814B BIT(0) -#define BIT_PCIE_BCNQ_FLAG_8814B BIT(12) +/* 2 REG_PCIE_HISR3_8814B */ +#define BIT_GTINT12_8814B BIT(24) +#define BIT_GTINT11_8814B BIT(23) +#define BIT_GTINT10_8814B BIT(22) +#define BIT_GTINT9_8814B BIT(21) +#define BIT_RX_DESC_BUF_FULL_8814B BIT(20) +#define BIT_CPHY_LDO_OCP_DET_INT_8814B BIT(19) +#define BIT_WDT_PLATFORM_INT_8814B BIT(18) +#define BIT_WDT_CPU_INT_8814B BIT(17) +#define BIT_SETH2CDOK_8814B BIT(16) +#define BIT_H2C_CMD_FULL_8814B BIT(15) +#define BIT_PKT_TRANS_ERR_8814B BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_8814B BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_8814B BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_8814B BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_8814B BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_8814B BIT(9) +#define BIT_SEARCH_FAIL_8814B BIT(8) +#define BIT_PWR_INT_127TO96_8814B BIT(7) +#define BIT_PWR_INT_95TO64_8814B BIT(6) +#define BIT_PWR_INT_63TO32_8814B BIT(5) +#define BIT_PWR_INT_31TO0_8814B BIT(4) +#define BIT_RX_DMA_STUCK_8814B BIT(3) +#define BIT_TX_DMA_STUCK_8814B BIT(2) +#define BIT_DDMA0_LP_INT_8814B BIT(1) +#define BIT_DDMA0_HP_INT_8814B BIT(0) -#define BIT_SHIFT_RXQ_DESC_NUM_8814B 0 -#define BIT_MASK_RXQ_DESC_NUM_8814B 0xfff -#define BIT_RXQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8814B) << BIT_SHIFT_RXQ_DESC_NUM_8814B) -#define BIT_GET_RXQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8814B) & BIT_MASK_RXQ_DESC_NUM_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_QUEUELIST_INFO0_8814B */ + +#define BIT_SHIFT_QINFO0_8814B 0 +#define BIT_MASK_QINFO0_8814B 0xffffffffL +#define BIT_QINFO0_8814B(x) \ + (((x) & BIT_MASK_QINFO0_8814B) << BIT_SHIFT_QINFO0_8814B) +#define BITS_QINFO0_8814B (BIT_MASK_QINFO0_8814B << BIT_SHIFT_QINFO0_8814B) +#define BIT_CLEAR_QINFO0_8814B(x) ((x) & (~BITS_QINFO0_8814B)) +#define BIT_GET_QINFO0_8814B(x) \ + (((x) >> BIT_SHIFT_QINFO0_8814B) & BIT_MASK_QINFO0_8814B) +#define BIT_SET_QINFO0_8814B(x, v) \ + (BIT_CLEAR_QINFO0_8814B(x) | BIT_QINFO0_8814B(v)) + +/* 2 REG_QUEUELIST_INFO1_8814B */ + +#define BIT_SHIFT_QINFO1_8814B 0 +#define BIT_MASK_QINFO1_8814B 0xffffffffL +#define BIT_QINFO1_8814B(x) \ + (((x) & BIT_MASK_QINFO1_8814B) << BIT_SHIFT_QINFO1_8814B) +#define BITS_QINFO1_8814B (BIT_MASK_QINFO1_8814B << BIT_SHIFT_QINFO1_8814B) +#define BIT_CLEAR_QINFO1_8814B(x) ((x) & (~BITS_QINFO1_8814B)) +#define BIT_GET_QINFO1_8814B(x) \ + (((x) >> BIT_SHIFT_QINFO1_8814B) & BIT_MASK_QINFO1_8814B) +#define BIT_SET_QINFO1_8814B(x, v) \ + (BIT_CLEAR_QINFO1_8814B(x) | BIT_QINFO1_8814B(v)) + +/* 2 REG_QUEUELIST_INFO2_8814B */ + +#define BIT_SHIFT_QINFO2_8814B 0 +#define BIT_MASK_QINFO2_8814B 0xffffffffL +#define BIT_QINFO2_8814B(x) \ + (((x) & BIT_MASK_QINFO2_8814B) << BIT_SHIFT_QINFO2_8814B) +#define BITS_QINFO2_8814B (BIT_MASK_QINFO2_8814B << BIT_SHIFT_QINFO2_8814B) +#define BIT_CLEAR_QINFO2_8814B(x) ((x) & (~BITS_QINFO2_8814B)) +#define BIT_GET_QINFO2_8814B(x) \ + (((x) >> BIT_SHIFT_QINFO2_8814B) & BIT_MASK_QINFO2_8814B) +#define BIT_SET_QINFO2_8814B(x, v) \ + (BIT_CLEAR_QINFO2_8814B(x) | BIT_QINFO2_8814B(v)) + +/* 2 REG_QUEUELIST_INFO3_8814B */ + +#define BIT_SHIFT_QINFO3_8814B 0 +#define BIT_MASK_QINFO3_8814B 0xffffffffL +#define BIT_QINFO3_8814B(x) \ + (((x) & BIT_MASK_QINFO3_8814B) << BIT_SHIFT_QINFO3_8814B) +#define BITS_QINFO3_8814B (BIT_MASK_QINFO3_8814B << BIT_SHIFT_QINFO3_8814B) +#define BIT_CLEAR_QINFO3_8814B(x) ((x) & (~BITS_QINFO3_8814B)) +#define BIT_GET_QINFO3_8814B(x) \ + (((x) >> BIT_SHIFT_QINFO3_8814B) & BIT_MASK_QINFO3_8814B) +#define BIT_SET_QINFO3_8814B(x, v) \ + (BIT_CLEAR_QINFO3_8814B(x) | BIT_QINFO3_8814B(v)) + +/* 2 REG_QUEUELIST_INFO_EMPTY_8814B */ +#define BIT_FWCMDQ_EMPTY_8814B BIT(31) +#define BIT_MGQ_CPU_EMPTY_V1_8814B BIT(30) +#define BIT_BCNQ_EMPTY_EXTP0_8814B BIT(29) +#define BIT_BCNQ_EMPTY_PORT4_8814B BIT(28) +#define BIT_BCNQ_EMPTY_PORT3_8814B BIT(27) +#define BIT_BCNQ_EMPTY_PORT2_8814B BIT(26) +#define BIT_BCNQ_EMPTY_PORT1_8814B BIT(25) +#define BIT_BCNQ_EMPTY_PORT0_8814B BIT(24) +#define BIT_HQQ_EMPTY_V1_8814B BIT(23) +#define BIT_MQQ_EMPTY_V2_8814B BIT(22) +#define BIT_S1_EMPTY_8814B BIT(21) +#define BIT_S0_EMPTY_8814B BIT(20) +#define BIT_AC19Q_EMPTY_8814B BIT(19) +#define BIT_AC18Q_EMPTY_8814B BIT(18) +#define BIT_AC17Q_EMPTY_8814B BIT(17) +#define BIT_AC16Q_EMPTY_8814B BIT(16) +#define BIT_AC15Q_EMPTY_8814B BIT(15) +#define BIT_AC14Q_EMPTY_8814B BIT(14) +#define BIT_AC13Q_EMPTY_8814B BIT(13) +#define BIT_AC12Q_EMPTY_8814B BIT(12) +#define BIT_AC11Q_EMPTY_8814B BIT(11) +#define BIT_AC10Q_EMPTY_8814B BIT(10) +#define BIT_AC9Q_EMPTY_8814B BIT(9) +#define BIT_AC8Q_EMPTY_8814B BIT(8) +#define BIT_AC7Q_EMPTY_8814B BIT(7) +#define BIT_AC6Q_EMPTY_8814B BIT(6) +#define BIT_AC5Q_EMPTY_8814B BIT(5) +#define BIT_AC4Q_EMPTY_8814B BIT(4) +#define BIT_AC3Q_EMPTY_8814B BIT(3) +#define BIT_AC2Q_EMPTY_8814B BIT(2) +#define BIT_AC1Q_EMPTY_8814B BIT(1) +#define BIT_AC0Q_EMPTY_8814B BIT(0) +/* 2 REG_QUEUELIST_ACQ_EN_8814B */ + +#define BIT_SHIFT_QINFO_CTRL_8814B 24 +#define BIT_MASK_QINFO_CTRL_8814B 0x3f +#define BIT_QINFO_CTRL_8814B(x) \ + (((x) & BIT_MASK_QINFO_CTRL_8814B) << BIT_SHIFT_QINFO_CTRL_8814B) +#define BITS_QINFO_CTRL_8814B \ + (BIT_MASK_QINFO_CTRL_8814B << BIT_SHIFT_QINFO_CTRL_8814B) +#define BIT_CLEAR_QINFO_CTRL_8814B(x) ((x) & (~BITS_QINFO_CTRL_8814B)) +#define BIT_GET_QINFO_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_QINFO_CTRL_8814B) & BIT_MASK_QINFO_CTRL_8814B) +#define BIT_SET_QINFO_CTRL_8814B(x, v) \ + (BIT_CLEAR_QINFO_CTRL_8814B(x) | BIT_QINFO_CTRL_8814B(v)) + +#define BIT_SHIFT_QINFO_MODE_BAND_8814B 20 +#define BIT_MASK_QINFO_MODE_BAND_8814B 0x7 +#define BIT_QINFO_MODE_BAND_8814B(x) \ + (((x) & BIT_MASK_QINFO_MODE_BAND_8814B) \ + << BIT_SHIFT_QINFO_MODE_BAND_8814B) +#define BITS_QINFO_MODE_BAND_8814B \ + (BIT_MASK_QINFO_MODE_BAND_8814B << BIT_SHIFT_QINFO_MODE_BAND_8814B) +#define BIT_CLEAR_QINFO_MODE_BAND_8814B(x) ((x) & (~BITS_QINFO_MODE_BAND_8814B)) +#define BIT_GET_QINFO_MODE_BAND_8814B(x) \ + (((x) >> BIT_SHIFT_QINFO_MODE_BAND_8814B) & \ + BIT_MASK_QINFO_MODE_BAND_8814B) +#define BIT_SET_QINFO_MODE_BAND_8814B(x, v) \ + (BIT_CLEAR_QINFO_MODE_BAND_8814B(x) | BIT_QINFO_MODE_BAND_8814B(v)) + +#define BIT_ACQ19_ENABLE_8814B BIT(19) +#define BIT_ACQ18_ENABLE_8814B BIT(18) +#define BIT_ACQ17_ENABLE_8814B BIT(17) +#define BIT_ACQ16_ENABLE_8814B BIT(16) +#define BIT_ACQ15_ENABLE_8814B BIT(15) +#define BIT_ACQ14_ENABLE_8814B BIT(14) +#define BIT_ACQ13_ENABLE_8814B BIT(13) +#define BIT_ACQ12_ENABLE_8814B BIT(12) +#define BIT_ACQ11_ENABLE_8814B BIT(11) +#define BIT_ACQ10_ENABLE_8814B BIT(10) +#define BIT_ACQ9_ENABLE_8814B BIT(9) +#define BIT_ACQ8_ENABLE_8814B BIT(8) +#define BIT_ACQ7_ENABLE_8814B BIT(7) +#define BIT_ACQ6_ENABLE_8814B BIT(6) +#define BIT_ACQ5_ENABLE_8814B BIT(5) +#define BIT_ACQ4_ENABLE_8814B BIT(4) +#define BIT_ACQ3_ENABLE_8814B BIT(3) +#define BIT_ACQ2_ENABLE_8814B BIT(2) +#define BIT_ACQ1_ENABLE_8814B BIT(1) +#define BIT_ACQ0_ENABLE_8814B BIT(0) + +/* 2 REG_BCNQ_BDNY_V2_8814B */ + +#define BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B 28 +#define BIT_MASK_BCNQ_PGBNDY_WSEL_8814B 0x7 +#define BIT_BCNQ_PGBNDY_WSEL_8814B(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_WSEL_8814B) \ + << BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B) +#define BITS_BCNQ_PGBNDY_WSEL_8814B \ + (BIT_MASK_BCNQ_PGBNDY_WSEL_8814B << BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B) +#define BIT_CLEAR_BCNQ_PGBNDY_WSEL_8814B(x) \ + ((x) & (~BITS_BCNQ_PGBNDY_WSEL_8814B)) +#define BIT_GET_BCNQ_PGBNDY_WSEL_8814B(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B) & \ + BIT_MASK_BCNQ_PGBNDY_WSEL_8814B) +#define BIT_SET_BCNQ_PGBNDY_WSEL_8814B(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_WSEL_8814B(x) | BIT_BCNQ_PGBNDY_WSEL_8814B(v)) + +#define BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B 12 +#define BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B 0xfff +#define BIT_BCNQ_PGBNDY_RCONTENT_8814B(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B) \ + << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B) +#define BITS_BCNQ_PGBNDY_RCONTENT_8814B \ + (BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B \ + << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B) +#define BIT_CLEAR_BCNQ_PGBNDY_RCONTENT_8814B(x) \ + ((x) & (~BITS_BCNQ_PGBNDY_RCONTENT_8814B)) +#define BIT_GET_BCNQ_PGBNDY_RCONTENT_8814B(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B) & \ + BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B) +#define BIT_SET_BCNQ_PGBNDY_RCONTENT_8814B(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_RCONTENT_8814B(x) | \ + BIT_BCNQ_PGBNDY_RCONTENT_8814B(v)) + +#define BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B 0 +#define BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B 0xfff +#define BIT_BCNQ_PGBNDY_WCONTENT_8814B(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B) \ + << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B) +#define BITS_BCNQ_PGBNDY_WCONTENT_8814B \ + (BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B \ + << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B) +#define BIT_CLEAR_BCNQ_PGBNDY_WCONTENT_8814B(x) \ + ((x) & (~BITS_BCNQ_PGBNDY_WCONTENT_8814B)) +#define BIT_GET_BCNQ_PGBNDY_WCONTENT_8814B(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B) & \ + BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B) +#define BIT_SET_BCNQ_PGBNDY_WCONTENT_8814B(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_WCONTENT_8814B(x) | \ + BIT_BCNQ_PGBNDY_WCONTENT_8814B(v)) -/* 2 REG_VOQ_TXBD_NUM_8814B */ -#define BIT_PCIE_VOQ_FLAG_8814B BIT(14) +/* 2 REG_CPU_MGQ_INFO_8814B */ +#define BIT_CPUMGT_CLR_V1_8814B BIT(30) +#define BIT_CPUMGT_POLL_8814B BIT(29) +#define BIT_BCN_EXT_POLL_8814B BIT(21) +#define BIT_BCN4_POLL_8814B BIT(20) +#define BIT_BCN3_POLL_8814B BIT(19) +#define BIT_BCN2_POLL_8814B BIT(18) +#define BIT_BCN1_POLL_V1_8814B BIT(17) +#define BIT_BCN_POLL_V1_8814B BIT(16) + +#define BIT_SHIFT_FREE_TAIL_PAGE_8814B 0 +#define BIT_MASK_FREE_TAIL_PAGE_8814B 0xfff +#define BIT_FREE_TAIL_PAGE_8814B(x) \ + (((x) & BIT_MASK_FREE_TAIL_PAGE_8814B) \ + << BIT_SHIFT_FREE_TAIL_PAGE_8814B) +#define BITS_FREE_TAIL_PAGE_8814B \ + (BIT_MASK_FREE_TAIL_PAGE_8814B << BIT_SHIFT_FREE_TAIL_PAGE_8814B) +#define BIT_CLEAR_FREE_TAIL_PAGE_8814B(x) ((x) & (~BITS_FREE_TAIL_PAGE_8814B)) +#define BIT_GET_FREE_TAIL_PAGE_8814B(x) \ + (((x) >> BIT_SHIFT_FREE_TAIL_PAGE_8814B) & \ + BIT_MASK_FREE_TAIL_PAGE_8814B) +#define BIT_SET_FREE_TAIL_PAGE_8814B(x, v) \ + (BIT_CLEAR_FREE_TAIL_PAGE_8814B(x) | BIT_FREE_TAIL_PAGE_8814B(v)) -#define BIT_SHIFT_VOQ_DESC_MODE_8814B 12 -#define BIT_MASK_VOQ_DESC_MODE_8814B 0x3 -#define BIT_VOQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8814B) << BIT_SHIFT_VOQ_DESC_MODE_8814B) -#define BIT_GET_VOQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8814B) & BIT_MASK_VOQ_DESC_MODE_8814B) +/* 2 REG_FWHW_TXQ_CTRL_8814B */ +#define BIT_RTS_LIMIT_IN_OFDM_8814B BIT(23) +#define BIT_EN_RD_RESP_NAV_BK_8814B BIT(21) +#define BIT_EN_WR_FREE_TAIL_8814B BIT(20) +#define BIT_NOTXRPT_USERATE_EN_8814B BIT(19) +#define BIT_DIS_TXFAIL_RPT_8814B BIT(18) +#define BIT_FTM_TIMEOUT_BYPASS_8814B BIT(16) +#define BIT_EN_BCNQ_DL5_8814B BIT(13) +#define BIT_EN_BCNQ_DL4_8814B BIT(12) +#define BIT_EN_BCNQ_DL3_8814B BIT(11) +#define BIT_EN_BCNQ_DL2_8814B BIT(10) +#define BIT_EN_BCNQ_DL1_8814B BIT(9) +#define BIT_EN_BCNQ_DL0_8814B BIT(8) +#define BIT_EN_RTY_BK_8814B BIT(7) +#define BIT_EN_USE_INI_RAT_8814B BIT(6) +#define BIT_EN_RTS_NAV_BK_8814B BIT(5) +#define BIT_DIS_SSN_CHECK_8814B BIT(4) +#define BIT_MACID_MATCH_RTS_8814B BIT(3) +#define BIT_EN_BCN_TRXRPT_V1_8814B BIT(2) +#define BIT_EN_FTMRPT_V1_8814B BIT(1) +#define BIT_BMC_NAV_PROTECT_8814B BIT(0) +/* 2 REG_DATAFB_SEL_8814B */ +#define BIT_BROADCAST_RTY_EN_8814B BIT(3) +#define BIT_EN_RTY_BK_COD_8814B BIT(2) + +#define BIT_SHIFT__DATA_FALLBACK_SEL_8814B 0 +#define BIT_MASK__DATA_FALLBACK_SEL_8814B 0x3 +#define BIT__DATA_FALLBACK_SEL_8814B(x) \ + (((x) & BIT_MASK__DATA_FALLBACK_SEL_8814B) \ + << BIT_SHIFT__DATA_FALLBACK_SEL_8814B) +#define BITS__DATA_FALLBACK_SEL_8814B \ + (BIT_MASK__DATA_FALLBACK_SEL_8814B \ + << BIT_SHIFT__DATA_FALLBACK_SEL_8814B) +#define BIT_CLEAR__DATA_FALLBACK_SEL_8814B(x) \ + ((x) & (~BITS__DATA_FALLBACK_SEL_8814B)) +#define BIT_GET__DATA_FALLBACK_SEL_8814B(x) \ + (((x) >> BIT_SHIFT__DATA_FALLBACK_SEL_8814B) & \ + BIT_MASK__DATA_FALLBACK_SEL_8814B) +#define BIT_SET__DATA_FALLBACK_SEL_8814B(x, v) \ + (BIT_CLEAR__DATA_FALLBACK_SEL_8814B(x) | \ + BIT__DATA_FALLBACK_SEL_8814B(v)) + +/* 2 REG_TXBDNY_8814B */ + +#define BIT_SHIFT_TXBNDY_8814B 0 +#define BIT_MASK_TXBNDY_8814B 0xfff +#define BIT_TXBNDY_8814B(x) \ + (((x) & BIT_MASK_TXBNDY_8814B) << BIT_SHIFT_TXBNDY_8814B) +#define BITS_TXBNDY_8814B (BIT_MASK_TXBNDY_8814B << BIT_SHIFT_TXBNDY_8814B) +#define BIT_CLEAR_TXBNDY_8814B(x) ((x) & (~BITS_TXBNDY_8814B)) +#define BIT_GET_TXBNDY_8814B(x) \ + (((x) >> BIT_SHIFT_TXBNDY_8814B) & BIT_MASK_TXBNDY_8814B) +#define BIT_SET_TXBNDY_8814B(x, v) \ + (BIT_CLEAR_TXBNDY_8814B(x) | BIT_TXBNDY_8814B(v)) +/* 2 REG_LIFETIME_EN_8814B */ +#define BIT_BT_INT_CPU_8814B BIT(7) +#define BIT_BT_INT_PTA_8814B BIT(6) +#define BIT_EN_CTRL_RTYBIT_8814B BIT(4) +#define BIT_LIFETIME_BK_EN_8814B BIT(3) +#define BIT_LIFETIME_BE_EN_8814B BIT(2) +#define BIT_LIFETIME_VI_EN_8814B BIT(1) +#define BIT_LIFETIME_VO_EN_8814B BIT(0) -#define BIT_SHIFT_VOQ_DESC_NUM_8814B 0 -#define BIT_MASK_VOQ_DESC_NUM_8814B 0xfff -#define BIT_VOQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8814B) << BIT_SHIFT_VOQ_DESC_NUM_8814B) -#define BIT_GET_VOQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8814B) & BIT_MASK_VOQ_DESC_NUM_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_SPEC_SIFS_8814B */ +#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B 8 +#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B 0xff +#define BIT_SPEC_SIFS_OFDM_PTCL_8814B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) +#define BITS_SPEC_SIFS_OFDM_PTCL_8814B \ + (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8814B(x) \ + ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8814B)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8814B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) & \ + BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8814B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8814B(x) | \ + BIT_SPEC_SIFS_OFDM_PTCL_8814B(v)) -/* 2 REG_VIQ_TXBD_NUM_8814B */ -#define BIT_PCIE_VIQ_FLAG_8814B BIT(14) +#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B 0 +#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B 0xff +#define BIT_SPEC_SIFS_CCK_PTCL_8814B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B) \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) +#define BITS_SPEC_SIFS_CCK_PTCL_8814B \ + (BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8814B(x) \ + ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8814B)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8814B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) & \ + BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B) +#define BIT_SET_SPEC_SIFS_CCK_PTCL_8814B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8814B(x) | \ + BIT_SPEC_SIFS_CCK_PTCL_8814B(v)) -#define BIT_SHIFT_VIQ_DESC_MODE_8814B 12 -#define BIT_MASK_VIQ_DESC_MODE_8814B 0x3 -#define BIT_VIQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8814B) << BIT_SHIFT_VIQ_DESC_MODE_8814B) -#define BIT_GET_VIQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8814B) & BIT_MASK_VIQ_DESC_MODE_8814B) +/* 2 REG_RETRY_LIMIT_8814B */ +#define BIT_SHIFT_SRL_8814B 8 +#define BIT_MASK_SRL_8814B 0x3f +#define BIT_SRL_8814B(x) (((x) & BIT_MASK_SRL_8814B) << BIT_SHIFT_SRL_8814B) +#define BITS_SRL_8814B (BIT_MASK_SRL_8814B << BIT_SHIFT_SRL_8814B) +#define BIT_CLEAR_SRL_8814B(x) ((x) & (~BITS_SRL_8814B)) +#define BIT_GET_SRL_8814B(x) (((x) >> BIT_SHIFT_SRL_8814B) & BIT_MASK_SRL_8814B) +#define BIT_SET_SRL_8814B(x, v) (BIT_CLEAR_SRL_8814B(x) | BIT_SRL_8814B(v)) +#define BIT_SHIFT_LRL_8814B 0 +#define BIT_MASK_LRL_8814B 0x3f +#define BIT_LRL_8814B(x) (((x) & BIT_MASK_LRL_8814B) << BIT_SHIFT_LRL_8814B) +#define BITS_LRL_8814B (BIT_MASK_LRL_8814B << BIT_SHIFT_LRL_8814B) +#define BIT_CLEAR_LRL_8814B(x) ((x) & (~BITS_LRL_8814B)) +#define BIT_GET_LRL_8814B(x) (((x) >> BIT_SHIFT_LRL_8814B) & BIT_MASK_LRL_8814B) +#define BIT_SET_LRL_8814B(x, v) (BIT_CLEAR_LRL_8814B(x) | BIT_LRL_8814B(v)) -#define BIT_SHIFT_VIQ_DESC_NUM_8814B 0 -#define BIT_MASK_VIQ_DESC_NUM_8814B 0xfff -#define BIT_VIQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8814B) << BIT_SHIFT_VIQ_DESC_NUM_8814B) -#define BIT_GET_VIQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8814B) & BIT_MASK_VIQ_DESC_NUM_8814B) +/* 2 REG_TXBF_CTRL_8814B */ +#define BIT_ENABLE_NDPA_8814B BIT(31) +#define BIT_NDPA_PARA_8814B BIT(30) +#define BIT_PROP_TXBF_8814B BIT(29) +#define BIT_EN_NDPA_INT_8814B BIT(28) +#define BIT_TXBF1_80M_160M_8814B BIT(27) +#define BIT_TXBF1_40M_8814B BIT(26) +#define BIT_TXBF1_20M_8814B BIT(25) + +#define BIT_SHIFT_TXBF1_AID_8814B 16 +#define BIT_MASK_TXBF1_AID_8814B 0x1ff +#define BIT_TXBF1_AID_8814B(x) \ + (((x) & BIT_MASK_TXBF1_AID_8814B) << BIT_SHIFT_TXBF1_AID_8814B) +#define BITS_TXBF1_AID_8814B \ + (BIT_MASK_TXBF1_AID_8814B << BIT_SHIFT_TXBF1_AID_8814B) +#define BIT_CLEAR_TXBF1_AID_8814B(x) ((x) & (~BITS_TXBF1_AID_8814B)) +#define BIT_GET_TXBF1_AID_8814B(x) \ + (((x) >> BIT_SHIFT_TXBF1_AID_8814B) & BIT_MASK_TXBF1_AID_8814B) +#define BIT_SET_TXBF1_AID_8814B(x, v) \ + (BIT_CLEAR_TXBF1_AID_8814B(x) | BIT_TXBF1_AID_8814B(v)) +#define BIT_DIS_NDP_BFEN_8814B BIT(15) +#define BIT_TXBCN_NOBLOCK_NDP_8814B BIT(14) +#define BIT_TXBF0_80M_160M_8814B BIT(11) +#define BIT_TXBF0_40M_8814B BIT(10) +#define BIT_TXBF0_20M_8814B BIT(9) + +#define BIT_SHIFT_TXBF0_AID_8814B 0 +#define BIT_MASK_TXBF0_AID_8814B 0x1ff +#define BIT_TXBF0_AID_8814B(x) \ + (((x) & BIT_MASK_TXBF0_AID_8814B) << BIT_SHIFT_TXBF0_AID_8814B) +#define BITS_TXBF0_AID_8814B \ + (BIT_MASK_TXBF0_AID_8814B << BIT_SHIFT_TXBF0_AID_8814B) +#define BIT_CLEAR_TXBF0_AID_8814B(x) ((x) & (~BITS_TXBF0_AID_8814B)) +#define BIT_GET_TXBF0_AID_8814B(x) \ + (((x) >> BIT_SHIFT_TXBF0_AID_8814B) & BIT_MASK_TXBF0_AID_8814B) +#define BIT_SET_TXBF0_AID_8814B(x, v) \ + (BIT_CLEAR_TXBF0_AID_8814B(x) | BIT_TXBF0_AID_8814B(v)) +/* 2 REG_DARFRC_8814B */ -/* 2 REG_BEQ_TXBD_NUM_8814B */ -#define BIT_PCIE_BEQ_FLAG_8814B BIT(14) +#define BIT_SHIFT_DARF_RC4_V1_8814B 24 +#define BIT_MASK_DARF_RC4_V1_8814B 0x3f +#define BIT_DARF_RC4_V1_8814B(x) \ + (((x) & BIT_MASK_DARF_RC4_V1_8814B) << BIT_SHIFT_DARF_RC4_V1_8814B) +#define BITS_DARF_RC4_V1_8814B \ + (BIT_MASK_DARF_RC4_V1_8814B << BIT_SHIFT_DARF_RC4_V1_8814B) +#define BIT_CLEAR_DARF_RC4_V1_8814B(x) ((x) & (~BITS_DARF_RC4_V1_8814B)) +#define BIT_GET_DARF_RC4_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_V1_8814B) & BIT_MASK_DARF_RC4_V1_8814B) +#define BIT_SET_DARF_RC4_V1_8814B(x, v) \ + (BIT_CLEAR_DARF_RC4_V1_8814B(x) | BIT_DARF_RC4_V1_8814B(v)) + +#define BIT_SHIFT_DARF_RC3_V1_8814B 16 +#define BIT_MASK_DARF_RC3_V1_8814B 0x3f +#define BIT_DARF_RC3_V1_8814B(x) \ + (((x) & BIT_MASK_DARF_RC3_V1_8814B) << BIT_SHIFT_DARF_RC3_V1_8814B) +#define BITS_DARF_RC3_V1_8814B \ + (BIT_MASK_DARF_RC3_V1_8814B << BIT_SHIFT_DARF_RC3_V1_8814B) +#define BIT_CLEAR_DARF_RC3_V1_8814B(x) ((x) & (~BITS_DARF_RC3_V1_8814B)) +#define BIT_GET_DARF_RC3_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_V1_8814B) & BIT_MASK_DARF_RC3_V1_8814B) +#define BIT_SET_DARF_RC3_V1_8814B(x, v) \ + (BIT_CLEAR_DARF_RC3_V1_8814B(x) | BIT_DARF_RC3_V1_8814B(v)) + +#define BIT_SHIFT_DARF_RC2_V1_8814B 8 +#define BIT_MASK_DARF_RC2_V1_8814B 0x3f +#define BIT_DARF_RC2_V1_8814B(x) \ + (((x) & BIT_MASK_DARF_RC2_V1_8814B) << BIT_SHIFT_DARF_RC2_V1_8814B) +#define BITS_DARF_RC2_V1_8814B \ + (BIT_MASK_DARF_RC2_V1_8814B << BIT_SHIFT_DARF_RC2_V1_8814B) +#define BIT_CLEAR_DARF_RC2_V1_8814B(x) ((x) & (~BITS_DARF_RC2_V1_8814B)) +#define BIT_GET_DARF_RC2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_V1_8814B) & BIT_MASK_DARF_RC2_V1_8814B) +#define BIT_SET_DARF_RC2_V1_8814B(x, v) \ + (BIT_CLEAR_DARF_RC2_V1_8814B(x) | BIT_DARF_RC2_V1_8814B(v)) + +#define BIT_SHIFT_DARF_RC1_V1_8814B 0 +#define BIT_MASK_DARF_RC1_V1_8814B 0x3f +#define BIT_DARF_RC1_V1_8814B(x) \ + (((x) & BIT_MASK_DARF_RC1_V1_8814B) << BIT_SHIFT_DARF_RC1_V1_8814B) +#define BITS_DARF_RC1_V1_8814B \ + (BIT_MASK_DARF_RC1_V1_8814B << BIT_SHIFT_DARF_RC1_V1_8814B) +#define BIT_CLEAR_DARF_RC1_V1_8814B(x) ((x) & (~BITS_DARF_RC1_V1_8814B)) +#define BIT_GET_DARF_RC1_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_V1_8814B) & BIT_MASK_DARF_RC1_V1_8814B) +#define BIT_SET_DARF_RC1_V1_8814B(x, v) \ + (BIT_CLEAR_DARF_RC1_V1_8814B(x) | BIT_DARF_RC1_V1_8814B(v)) + +/* 2 REG_DARFRCH_8814B */ + +#define BIT_SHIFT_DARF_RC8_V2_8814B 24 +#define BIT_MASK_DARF_RC8_V2_8814B 0x3f +#define BIT_DARF_RC8_V2_8814B(x) \ + (((x) & BIT_MASK_DARF_RC8_V2_8814B) << BIT_SHIFT_DARF_RC8_V2_8814B) +#define BITS_DARF_RC8_V2_8814B \ + (BIT_MASK_DARF_RC8_V2_8814B << BIT_SHIFT_DARF_RC8_V2_8814B) +#define BIT_CLEAR_DARF_RC8_V2_8814B(x) ((x) & (~BITS_DARF_RC8_V2_8814B)) +#define BIT_GET_DARF_RC8_V2_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_V2_8814B) & BIT_MASK_DARF_RC8_V2_8814B) +#define BIT_SET_DARF_RC8_V2_8814B(x, v) \ + (BIT_CLEAR_DARF_RC8_V2_8814B(x) | BIT_DARF_RC8_V2_8814B(v)) + +#define BIT_SHIFT_DARF_RC7_V2_8814B 16 +#define BIT_MASK_DARF_RC7_V2_8814B 0x3f +#define BIT_DARF_RC7_V2_8814B(x) \ + (((x) & BIT_MASK_DARF_RC7_V2_8814B) << BIT_SHIFT_DARF_RC7_V2_8814B) +#define BITS_DARF_RC7_V2_8814B \ + (BIT_MASK_DARF_RC7_V2_8814B << BIT_SHIFT_DARF_RC7_V2_8814B) +#define BIT_CLEAR_DARF_RC7_V2_8814B(x) ((x) & (~BITS_DARF_RC7_V2_8814B)) +#define BIT_GET_DARF_RC7_V2_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_V2_8814B) & BIT_MASK_DARF_RC7_V2_8814B) +#define BIT_SET_DARF_RC7_V2_8814B(x, v) \ + (BIT_CLEAR_DARF_RC7_V2_8814B(x) | BIT_DARF_RC7_V2_8814B(v)) + +#define BIT_SHIFT_DARF_RC6_V2_8814B 8 +#define BIT_MASK_DARF_RC6_V2_8814B 0x3f +#define BIT_DARF_RC6_V2_8814B(x) \ + (((x) & BIT_MASK_DARF_RC6_V2_8814B) << BIT_SHIFT_DARF_RC6_V2_8814B) +#define BITS_DARF_RC6_V2_8814B \ + (BIT_MASK_DARF_RC6_V2_8814B << BIT_SHIFT_DARF_RC6_V2_8814B) +#define BIT_CLEAR_DARF_RC6_V2_8814B(x) ((x) & (~BITS_DARF_RC6_V2_8814B)) +#define BIT_GET_DARF_RC6_V2_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_V2_8814B) & BIT_MASK_DARF_RC6_V2_8814B) +#define BIT_SET_DARF_RC6_V2_8814B(x, v) \ + (BIT_CLEAR_DARF_RC6_V2_8814B(x) | BIT_DARF_RC6_V2_8814B(v)) + +#define BIT_SHIFT_DARF_RC5_V2_8814B 0 +#define BIT_MASK_DARF_RC5_V2_8814B 0x3f +#define BIT_DARF_RC5_V2_8814B(x) \ + (((x) & BIT_MASK_DARF_RC5_V2_8814B) << BIT_SHIFT_DARF_RC5_V2_8814B) +#define BITS_DARF_RC5_V2_8814B \ + (BIT_MASK_DARF_RC5_V2_8814B << BIT_SHIFT_DARF_RC5_V2_8814B) +#define BIT_CLEAR_DARF_RC5_V2_8814B(x) ((x) & (~BITS_DARF_RC5_V2_8814B)) +#define BIT_GET_DARF_RC5_V2_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_V2_8814B) & BIT_MASK_DARF_RC5_V2_8814B) +#define BIT_SET_DARF_RC5_V2_8814B(x, v) \ + (BIT_CLEAR_DARF_RC5_V2_8814B(x) | BIT_DARF_RC5_V2_8814B(v)) -#define BIT_SHIFT_BEQ_DESC_MODE_8814B 12 -#define BIT_MASK_BEQ_DESC_MODE_8814B 0x3 -#define BIT_BEQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8814B) << BIT_SHIFT_BEQ_DESC_MODE_8814B) -#define BIT_GET_BEQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8814B) & BIT_MASK_BEQ_DESC_MODE_8814B) +/* 2 REG_RARFRC_8814B */ +#define BIT_SHIFT_RARF_RC4_8814B 24 +#define BIT_MASK_RARF_RC4_8814B 0x1f +#define BIT_RARF_RC4_8814B(x) \ + (((x) & BIT_MASK_RARF_RC4_8814B) << BIT_SHIFT_RARF_RC4_8814B) +#define BITS_RARF_RC4_8814B \ + (BIT_MASK_RARF_RC4_8814B << BIT_SHIFT_RARF_RC4_8814B) +#define BIT_CLEAR_RARF_RC4_8814B(x) ((x) & (~BITS_RARF_RC4_8814B)) +#define BIT_GET_RARF_RC4_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC4_8814B) & BIT_MASK_RARF_RC4_8814B) +#define BIT_SET_RARF_RC4_8814B(x, v) \ + (BIT_CLEAR_RARF_RC4_8814B(x) | BIT_RARF_RC4_8814B(v)) +#define BIT_SHIFT_RARF_RC3_8814B 16 +#define BIT_MASK_RARF_RC3_8814B 0x1f +#define BIT_RARF_RC3_8814B(x) \ + (((x) & BIT_MASK_RARF_RC3_8814B) << BIT_SHIFT_RARF_RC3_8814B) +#define BITS_RARF_RC3_8814B \ + (BIT_MASK_RARF_RC3_8814B << BIT_SHIFT_RARF_RC3_8814B) +#define BIT_CLEAR_RARF_RC3_8814B(x) ((x) & (~BITS_RARF_RC3_8814B)) +#define BIT_GET_RARF_RC3_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC3_8814B) & BIT_MASK_RARF_RC3_8814B) +#define BIT_SET_RARF_RC3_8814B(x, v) \ + (BIT_CLEAR_RARF_RC3_8814B(x) | BIT_RARF_RC3_8814B(v)) -#define BIT_SHIFT_BEQ_DESC_NUM_8814B 0 -#define BIT_MASK_BEQ_DESC_NUM_8814B 0xfff -#define BIT_BEQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8814B) << BIT_SHIFT_BEQ_DESC_NUM_8814B) -#define BIT_GET_BEQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8814B) & BIT_MASK_BEQ_DESC_NUM_8814B) +#define BIT_SHIFT_RARF_RC2_8814B 8 +#define BIT_MASK_RARF_RC2_8814B 0x1f +#define BIT_RARF_RC2_8814B(x) \ + (((x) & BIT_MASK_RARF_RC2_8814B) << BIT_SHIFT_RARF_RC2_8814B) +#define BITS_RARF_RC2_8814B \ + (BIT_MASK_RARF_RC2_8814B << BIT_SHIFT_RARF_RC2_8814B) +#define BIT_CLEAR_RARF_RC2_8814B(x) ((x) & (~BITS_RARF_RC2_8814B)) +#define BIT_GET_RARF_RC2_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC2_8814B) & BIT_MASK_RARF_RC2_8814B) +#define BIT_SET_RARF_RC2_8814B(x, v) \ + (BIT_CLEAR_RARF_RC2_8814B(x) | BIT_RARF_RC2_8814B(v)) +#define BIT_SHIFT_RARF_RC1_8814B 0 +#define BIT_MASK_RARF_RC1_8814B 0x1f +#define BIT_RARF_RC1_8814B(x) \ + (((x) & BIT_MASK_RARF_RC1_8814B) << BIT_SHIFT_RARF_RC1_8814B) +#define BITS_RARF_RC1_8814B \ + (BIT_MASK_RARF_RC1_8814B << BIT_SHIFT_RARF_RC1_8814B) +#define BIT_CLEAR_RARF_RC1_8814B(x) ((x) & (~BITS_RARF_RC1_8814B)) +#define BIT_GET_RARF_RC1_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC1_8814B) & BIT_MASK_RARF_RC1_8814B) +#define BIT_SET_RARF_RC1_8814B(x, v) \ + (BIT_CLEAR_RARF_RC1_8814B(x) | BIT_RARF_RC1_8814B(v)) + +/* 2 REG_RARFRCH_8814B */ + +#define BIT_SHIFT_RARF_RC8_V1_8814B 24 +#define BIT_MASK_RARF_RC8_V1_8814B 0x1f +#define BIT_RARF_RC8_V1_8814B(x) \ + (((x) & BIT_MASK_RARF_RC8_V1_8814B) << BIT_SHIFT_RARF_RC8_V1_8814B) +#define BITS_RARF_RC8_V1_8814B \ + (BIT_MASK_RARF_RC8_V1_8814B << BIT_SHIFT_RARF_RC8_V1_8814B) +#define BIT_CLEAR_RARF_RC8_V1_8814B(x) ((x) & (~BITS_RARF_RC8_V1_8814B)) +#define BIT_GET_RARF_RC8_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC8_V1_8814B) & BIT_MASK_RARF_RC8_V1_8814B) +#define BIT_SET_RARF_RC8_V1_8814B(x, v) \ + (BIT_CLEAR_RARF_RC8_V1_8814B(x) | BIT_RARF_RC8_V1_8814B(v)) + +#define BIT_SHIFT_RARF_RC7_V1_8814B 16 +#define BIT_MASK_RARF_RC7_V1_8814B 0x1f +#define BIT_RARF_RC7_V1_8814B(x) \ + (((x) & BIT_MASK_RARF_RC7_V1_8814B) << BIT_SHIFT_RARF_RC7_V1_8814B) +#define BITS_RARF_RC7_V1_8814B \ + (BIT_MASK_RARF_RC7_V1_8814B << BIT_SHIFT_RARF_RC7_V1_8814B) +#define BIT_CLEAR_RARF_RC7_V1_8814B(x) ((x) & (~BITS_RARF_RC7_V1_8814B)) +#define BIT_GET_RARF_RC7_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC7_V1_8814B) & BIT_MASK_RARF_RC7_V1_8814B) +#define BIT_SET_RARF_RC7_V1_8814B(x, v) \ + (BIT_CLEAR_RARF_RC7_V1_8814B(x) | BIT_RARF_RC7_V1_8814B(v)) + +#define BIT_SHIFT_RARF_RC6_V1_8814B 8 +#define BIT_MASK_RARF_RC6_V1_8814B 0x1f +#define BIT_RARF_RC6_V1_8814B(x) \ + (((x) & BIT_MASK_RARF_RC6_V1_8814B) << BIT_SHIFT_RARF_RC6_V1_8814B) +#define BITS_RARF_RC6_V1_8814B \ + (BIT_MASK_RARF_RC6_V1_8814B << BIT_SHIFT_RARF_RC6_V1_8814B) +#define BIT_CLEAR_RARF_RC6_V1_8814B(x) ((x) & (~BITS_RARF_RC6_V1_8814B)) +#define BIT_GET_RARF_RC6_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC6_V1_8814B) & BIT_MASK_RARF_RC6_V1_8814B) +#define BIT_SET_RARF_RC6_V1_8814B(x, v) \ + (BIT_CLEAR_RARF_RC6_V1_8814B(x) | BIT_RARF_RC6_V1_8814B(v)) + +#define BIT_SHIFT_RARF_RC5_V1_8814B 0 +#define BIT_MASK_RARF_RC5_V1_8814B 0x1f +#define BIT_RARF_RC5_V1_8814B(x) \ + (((x) & BIT_MASK_RARF_RC5_V1_8814B) << BIT_SHIFT_RARF_RC5_V1_8814B) +#define BITS_RARF_RC5_V1_8814B \ + (BIT_MASK_RARF_RC5_V1_8814B << BIT_SHIFT_RARF_RC5_V1_8814B) +#define BIT_CLEAR_RARF_RC5_V1_8814B(x) ((x) & (~BITS_RARF_RC5_V1_8814B)) +#define BIT_GET_RARF_RC5_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC5_V1_8814B) & BIT_MASK_RARF_RC5_V1_8814B) +#define BIT_SET_RARF_RC5_V1_8814B(x, v) \ + (BIT_CLEAR_RARF_RC5_V1_8814B(x) | BIT_RARF_RC5_V1_8814B(v)) +/* 2 REG_RRSR_8814B */ -/* 2 REG_BKQ_TXBD_NUM_8814B */ -#define BIT_PCIE_BKQ_FLAG_8814B BIT(14) +#define BIT_SHIFT_RRSR_RSC_8814B 21 +#define BIT_MASK_RRSR_RSC_8814B 0x3 +#define BIT_RRSR_RSC_8814B(x) \ + (((x) & BIT_MASK_RRSR_RSC_8814B) << BIT_SHIFT_RRSR_RSC_8814B) +#define BITS_RRSR_RSC_8814B \ + (BIT_MASK_RRSR_RSC_8814B << BIT_SHIFT_RRSR_RSC_8814B) +#define BIT_CLEAR_RRSR_RSC_8814B(x) ((x) & (~BITS_RRSR_RSC_8814B)) +#define BIT_GET_RRSR_RSC_8814B(x) \ + (((x) >> BIT_SHIFT_RRSR_RSC_8814B) & BIT_MASK_RRSR_RSC_8814B) +#define BIT_SET_RRSR_RSC_8814B(x, v) \ + (BIT_CLEAR_RRSR_RSC_8814B(x) | BIT_RRSR_RSC_8814B(v)) -#define BIT_SHIFT_BKQ_DESC_MODE_8814B 12 -#define BIT_MASK_BKQ_DESC_MODE_8814B 0x3 -#define BIT_BKQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8814B) << BIT_SHIFT_BKQ_DESC_MODE_8814B) -#define BIT_GET_BKQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8814B) & BIT_MASK_BKQ_DESC_MODE_8814B) +#define BIT_SHIFT_RRSC_BITMAP_8814B 0 +#define BIT_MASK_RRSC_BITMAP_8814B 0xfffff +#define BIT_RRSC_BITMAP_8814B(x) \ + (((x) & BIT_MASK_RRSC_BITMAP_8814B) << BIT_SHIFT_RRSC_BITMAP_8814B) +#define BITS_RRSC_BITMAP_8814B \ + (BIT_MASK_RRSC_BITMAP_8814B << BIT_SHIFT_RRSC_BITMAP_8814B) +#define BIT_CLEAR_RRSC_BITMAP_8814B(x) ((x) & (~BITS_RRSC_BITMAP_8814B)) +#define BIT_GET_RRSC_BITMAP_8814B(x) \ + (((x) >> BIT_SHIFT_RRSC_BITMAP_8814B) & BIT_MASK_RRSC_BITMAP_8814B) +#define BIT_SET_RRSC_BITMAP_8814B(x, v) \ + (BIT_CLEAR_RRSC_BITMAP_8814B(x) | BIT_RRSC_BITMAP_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_ARFR0_8814B */ -#define BIT_SHIFT_BKQ_DESC_NUM_8814B 0 -#define BIT_MASK_BKQ_DESC_NUM_8814B 0xfff -#define BIT_BKQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8814B) << BIT_SHIFT_BKQ_DESC_NUM_8814B) -#define BIT_GET_BKQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8814B) & BIT_MASK_BKQ_DESC_NUM_8814B) +#define BIT_SHIFT_ARFRL0_8814B 0 +#define BIT_MASK_ARFRL0_8814B 0xffffffffL +#define BIT_ARFRL0_8814B(x) \ + (((x) & BIT_MASK_ARFRL0_8814B) << BIT_SHIFT_ARFRL0_8814B) +#define BITS_ARFRL0_8814B (BIT_MASK_ARFRL0_8814B << BIT_SHIFT_ARFRL0_8814B) +#define BIT_CLEAR_ARFRL0_8814B(x) ((x) & (~BITS_ARFRL0_8814B)) +#define BIT_GET_ARFRL0_8814B(x) \ + (((x) >> BIT_SHIFT_ARFRL0_8814B) & BIT_MASK_ARFRL0_8814B) +#define BIT_SET_ARFRL0_8814B(x, v) \ + (BIT_CLEAR_ARFRL0_8814B(x) | BIT_ARFRL0_8814B(v)) + +/* 2 REG_ARFRH0_8814B */ + +#define BIT_SHIFT_ARFRH0_8814B 0 +#define BIT_MASK_ARFRH0_8814B 0xffffffffL +#define BIT_ARFRH0_8814B(x) \ + (((x) & BIT_MASK_ARFRH0_8814B) << BIT_SHIFT_ARFRH0_8814B) +#define BITS_ARFRH0_8814B (BIT_MASK_ARFRH0_8814B << BIT_SHIFT_ARFRH0_8814B) +#define BIT_CLEAR_ARFRH0_8814B(x) ((x) & (~BITS_ARFRH0_8814B)) +#define BIT_GET_ARFRH0_8814B(x) \ + (((x) >> BIT_SHIFT_ARFRH0_8814B) & BIT_MASK_ARFRH0_8814B) +#define BIT_SET_ARFRH0_8814B(x, v) \ + (BIT_CLEAR_ARFRH0_8814B(x) | BIT_ARFRH0_8814B(v)) + +/* 2 REG_REG_ARFR_WT0_8814B */ + +#define BIT_SHIFT_RATE7_WEIGHTING_8814B 28 +#define BIT_MASK_RATE7_WEIGHTING_8814B 0xf +#define BIT_RATE7_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE7_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE7_WEIGHTING_8814B) +#define BITS_RATE7_WEIGHTING_8814B \ + (BIT_MASK_RATE7_WEIGHTING_8814B << BIT_SHIFT_RATE7_WEIGHTING_8814B) +#define BIT_CLEAR_RATE7_WEIGHTING_8814B(x) ((x) & (~BITS_RATE7_WEIGHTING_8814B)) +#define BIT_GET_RATE7_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE7_WEIGHTING_8814B) & \ + BIT_MASK_RATE7_WEIGHTING_8814B) +#define BIT_SET_RATE7_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE7_WEIGHTING_8814B(x) | BIT_RATE7_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE6_WEIGHTING_8814B 24 +#define BIT_MASK_RATE6_WEIGHTING_8814B 0xf +#define BIT_RATE6_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE6_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE6_WEIGHTING_8814B) +#define BITS_RATE6_WEIGHTING_8814B \ + (BIT_MASK_RATE6_WEIGHTING_8814B << BIT_SHIFT_RATE6_WEIGHTING_8814B) +#define BIT_CLEAR_RATE6_WEIGHTING_8814B(x) ((x) & (~BITS_RATE6_WEIGHTING_8814B)) +#define BIT_GET_RATE6_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE6_WEIGHTING_8814B) & \ + BIT_MASK_RATE6_WEIGHTING_8814B) +#define BIT_SET_RATE6_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE6_WEIGHTING_8814B(x) | BIT_RATE6_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE5_WEIGHTING_8814B 20 +#define BIT_MASK_RATE5_WEIGHTING_8814B 0xf +#define BIT_RATE5_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE5_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE5_WEIGHTING_8814B) +#define BITS_RATE5_WEIGHTING_8814B \ + (BIT_MASK_RATE5_WEIGHTING_8814B << BIT_SHIFT_RATE5_WEIGHTING_8814B) +#define BIT_CLEAR_RATE5_WEIGHTING_8814B(x) ((x) & (~BITS_RATE5_WEIGHTING_8814B)) +#define BIT_GET_RATE5_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE5_WEIGHTING_8814B) & \ + BIT_MASK_RATE5_WEIGHTING_8814B) +#define BIT_SET_RATE5_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE5_WEIGHTING_8814B(x) | BIT_RATE5_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE4_WEIGHTING_8814B 16 +#define BIT_MASK_RATE4_WEIGHTING_8814B 0xf +#define BIT_RATE4_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE4_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE4_WEIGHTING_8814B) +#define BITS_RATE4_WEIGHTING_8814B \ + (BIT_MASK_RATE4_WEIGHTING_8814B << BIT_SHIFT_RATE4_WEIGHTING_8814B) +#define BIT_CLEAR_RATE4_WEIGHTING_8814B(x) ((x) & (~BITS_RATE4_WEIGHTING_8814B)) +#define BIT_GET_RATE4_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE4_WEIGHTING_8814B) & \ + BIT_MASK_RATE4_WEIGHTING_8814B) +#define BIT_SET_RATE4_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE4_WEIGHTING_8814B(x) | BIT_RATE4_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE3_WEIGHTING_8814B 12 +#define BIT_MASK_RATE3_WEIGHTING_8814B 0xf +#define BIT_RATE3_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE3_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE3_WEIGHTING_8814B) +#define BITS_RATE3_WEIGHTING_8814B \ + (BIT_MASK_RATE3_WEIGHTING_8814B << BIT_SHIFT_RATE3_WEIGHTING_8814B) +#define BIT_CLEAR_RATE3_WEIGHTING_8814B(x) ((x) & (~BITS_RATE3_WEIGHTING_8814B)) +#define BIT_GET_RATE3_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE3_WEIGHTING_8814B) & \ + BIT_MASK_RATE3_WEIGHTING_8814B) +#define BIT_SET_RATE3_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE3_WEIGHTING_8814B(x) | BIT_RATE3_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE2_WEIGHTING_8814B 8 +#define BIT_MASK_RATE2_WEIGHTING_8814B 0xf +#define BIT_RATE2_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE2_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE2_WEIGHTING_8814B) +#define BITS_RATE2_WEIGHTING_8814B \ + (BIT_MASK_RATE2_WEIGHTING_8814B << BIT_SHIFT_RATE2_WEIGHTING_8814B) +#define BIT_CLEAR_RATE2_WEIGHTING_8814B(x) ((x) & (~BITS_RATE2_WEIGHTING_8814B)) +#define BIT_GET_RATE2_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE2_WEIGHTING_8814B) & \ + BIT_MASK_RATE2_WEIGHTING_8814B) +#define BIT_SET_RATE2_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE2_WEIGHTING_8814B(x) | BIT_RATE2_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE1_WEIGHTING_8814B 4 +#define BIT_MASK_RATE1_WEIGHTING_8814B 0xf +#define BIT_RATE1_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE1_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE1_WEIGHTING_8814B) +#define BITS_RATE1_WEIGHTING_8814B \ + (BIT_MASK_RATE1_WEIGHTING_8814B << BIT_SHIFT_RATE1_WEIGHTING_8814B) +#define BIT_CLEAR_RATE1_WEIGHTING_8814B(x) ((x) & (~BITS_RATE1_WEIGHTING_8814B)) +#define BIT_GET_RATE1_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE1_WEIGHTING_8814B) & \ + BIT_MASK_RATE1_WEIGHTING_8814B) +#define BIT_SET_RATE1_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE1_WEIGHTING_8814B(x) | BIT_RATE1_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE0_WEIGHTING_8814B 0 +#define BIT_MASK_RATE0_WEIGHTING_8814B 0xf +#define BIT_RATE0_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE0_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE0_WEIGHTING_8814B) +#define BITS_RATE0_WEIGHTING_8814B \ + (BIT_MASK_RATE0_WEIGHTING_8814B << BIT_SHIFT_RATE0_WEIGHTING_8814B) +#define BIT_CLEAR_RATE0_WEIGHTING_8814B(x) ((x) & (~BITS_RATE0_WEIGHTING_8814B)) +#define BIT_GET_RATE0_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE0_WEIGHTING_8814B) & \ + BIT_MASK_RATE0_WEIGHTING_8814B) +#define BIT_SET_RATE0_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE0_WEIGHTING_8814B(x) | BIT_RATE0_WEIGHTING_8814B(v)) + +/* 2 REG_REG_ARFR_WT1_8814B */ + +#define BIT_SHIFT_RATE15_WEIGHTING_8814B 28 +#define BIT_MASK_RATE15_WEIGHTING_8814B 0xf +#define BIT_RATE15_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE15_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE15_WEIGHTING_8814B) +#define BITS_RATE15_WEIGHTING_8814B \ + (BIT_MASK_RATE15_WEIGHTING_8814B << BIT_SHIFT_RATE15_WEIGHTING_8814B) +#define BIT_CLEAR_RATE15_WEIGHTING_8814B(x) \ + ((x) & (~BITS_RATE15_WEIGHTING_8814B)) +#define BIT_GET_RATE15_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE15_WEIGHTING_8814B) & \ + BIT_MASK_RATE15_WEIGHTING_8814B) +#define BIT_SET_RATE15_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE15_WEIGHTING_8814B(x) | BIT_RATE15_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE14_WEIGHTING_8814B 24 +#define BIT_MASK_RATE14_WEIGHTING_8814B 0xf +#define BIT_RATE14_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE14_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE14_WEIGHTING_8814B) +#define BITS_RATE14_WEIGHTING_8814B \ + (BIT_MASK_RATE14_WEIGHTING_8814B << BIT_SHIFT_RATE14_WEIGHTING_8814B) +#define BIT_CLEAR_RATE14_WEIGHTING_8814B(x) \ + ((x) & (~BITS_RATE14_WEIGHTING_8814B)) +#define BIT_GET_RATE14_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE14_WEIGHTING_8814B) & \ + BIT_MASK_RATE14_WEIGHTING_8814B) +#define BIT_SET_RATE14_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE14_WEIGHTING_8814B(x) | BIT_RATE14_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE13_WEIGHTING_8814B 20 +#define BIT_MASK_RATE13_WEIGHTING_8814B 0xf +#define BIT_RATE13_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE13_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE13_WEIGHTING_8814B) +#define BITS_RATE13_WEIGHTING_8814B \ + (BIT_MASK_RATE13_WEIGHTING_8814B << BIT_SHIFT_RATE13_WEIGHTING_8814B) +#define BIT_CLEAR_RATE13_WEIGHTING_8814B(x) \ + ((x) & (~BITS_RATE13_WEIGHTING_8814B)) +#define BIT_GET_RATE13_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE13_WEIGHTING_8814B) & \ + BIT_MASK_RATE13_WEIGHTING_8814B) +#define BIT_SET_RATE13_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE13_WEIGHTING_8814B(x) | BIT_RATE13_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE12_WEIGHTING_8814B 16 +#define BIT_MASK_RATE12_WEIGHTING_8814B 0xf +#define BIT_RATE12_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE12_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE12_WEIGHTING_8814B) +#define BITS_RATE12_WEIGHTING_8814B \ + (BIT_MASK_RATE12_WEIGHTING_8814B << BIT_SHIFT_RATE12_WEIGHTING_8814B) +#define BIT_CLEAR_RATE12_WEIGHTING_8814B(x) \ + ((x) & (~BITS_RATE12_WEIGHTING_8814B)) +#define BIT_GET_RATE12_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE12_WEIGHTING_8814B) & \ + BIT_MASK_RATE12_WEIGHTING_8814B) +#define BIT_SET_RATE12_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE12_WEIGHTING_8814B(x) | BIT_RATE12_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE11_WEIGHTING_8814B 12 +#define BIT_MASK_RATE11_WEIGHTING_8814B 0xf +#define BIT_RATE11_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE11_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE11_WEIGHTING_8814B) +#define BITS_RATE11_WEIGHTING_8814B \ + (BIT_MASK_RATE11_WEIGHTING_8814B << BIT_SHIFT_RATE11_WEIGHTING_8814B) +#define BIT_CLEAR_RATE11_WEIGHTING_8814B(x) \ + ((x) & (~BITS_RATE11_WEIGHTING_8814B)) +#define BIT_GET_RATE11_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE11_WEIGHTING_8814B) & \ + BIT_MASK_RATE11_WEIGHTING_8814B) +#define BIT_SET_RATE11_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE11_WEIGHTING_8814B(x) | BIT_RATE11_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE10_WEIGHTING_8814B 8 +#define BIT_MASK_RATE10_WEIGHTING_8814B 0xf +#define BIT_RATE10_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE10_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE10_WEIGHTING_8814B) +#define BITS_RATE10_WEIGHTING_8814B \ + (BIT_MASK_RATE10_WEIGHTING_8814B << BIT_SHIFT_RATE10_WEIGHTING_8814B) +#define BIT_CLEAR_RATE10_WEIGHTING_8814B(x) \ + ((x) & (~BITS_RATE10_WEIGHTING_8814B)) +#define BIT_GET_RATE10_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE10_WEIGHTING_8814B) & \ + BIT_MASK_RATE10_WEIGHTING_8814B) +#define BIT_SET_RATE10_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE10_WEIGHTING_8814B(x) | BIT_RATE10_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE9_WEIGHTING_8814B 4 +#define BIT_MASK_RATE9_WEIGHTING_8814B 0xf +#define BIT_RATE9_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE9_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE9_WEIGHTING_8814B) +#define BITS_RATE9_WEIGHTING_8814B \ + (BIT_MASK_RATE9_WEIGHTING_8814B << BIT_SHIFT_RATE9_WEIGHTING_8814B) +#define BIT_CLEAR_RATE9_WEIGHTING_8814B(x) ((x) & (~BITS_RATE9_WEIGHTING_8814B)) +#define BIT_GET_RATE9_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE9_WEIGHTING_8814B) & \ + BIT_MASK_RATE9_WEIGHTING_8814B) +#define BIT_SET_RATE9_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE9_WEIGHTING_8814B(x) | BIT_RATE9_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE8_WEIGHTING_8814B 0 +#define BIT_MASK_RATE8_WEIGHTING_8814B 0xf +#define BIT_RATE8_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE8_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE8_WEIGHTING_8814B) +#define BITS_RATE8_WEIGHTING_8814B \ + (BIT_MASK_RATE8_WEIGHTING_8814B << BIT_SHIFT_RATE8_WEIGHTING_8814B) +#define BIT_CLEAR_RATE8_WEIGHTING_8814B(x) ((x) & (~BITS_RATE8_WEIGHTING_8814B)) +#define BIT_GET_RATE8_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE8_WEIGHTING_8814B) & \ + BIT_MASK_RATE8_WEIGHTING_8814B) +#define BIT_SET_RATE8_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE8_WEIGHTING_8814B(x) | BIT_RATE8_WEIGHTING_8814B(v)) +/* 2 REG_CCK_CHECK_8814B */ +#define BIT_CHECK_CCK_EN_8814B BIT(7) +#define BIT_EN_BCN_PKT_REL_P0_8814B BIT(6) +#define BIT_BCN_PORT_SEL_8814B BIT(5) +#define BIT_MOREDATA_BYPASS_8814B BIT(4) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P0_8814B BIT(3) +#define BIT_EN_SET_MOREDATA_8814B BIT(2) +#define BIT__R_DIS_CLEAR_MACID_RELEASE_8814B BIT(1) +#define BIT__R_MACID_RELEASE_EN_8814B BIT(0) +/* 2 REG_AMPDU_MAX_TIME_V1_8814B */ -/* 2 REG_HI0Q_TXBD_NUM_8814B */ -#define BIT_HI0Q_FLAG_8814B BIT(14) +#define BIT_SHIFT_AMPDU_MAX_TIME_8814B 0 +#define BIT_MASK_AMPDU_MAX_TIME_8814B 0xff +#define BIT_AMPDU_MAX_TIME_8814B(x) \ + (((x) & BIT_MASK_AMPDU_MAX_TIME_8814B) \ + << BIT_SHIFT_AMPDU_MAX_TIME_8814B) +#define BITS_AMPDU_MAX_TIME_8814B \ + (BIT_MASK_AMPDU_MAX_TIME_8814B << BIT_SHIFT_AMPDU_MAX_TIME_8814B) +#define BIT_CLEAR_AMPDU_MAX_TIME_8814B(x) ((x) & (~BITS_AMPDU_MAX_TIME_8814B)) +#define BIT_GET_AMPDU_MAX_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8814B) & \ + BIT_MASK_AMPDU_MAX_TIME_8814B) +#define BIT_SET_AMPDU_MAX_TIME_8814B(x, v) \ + (BIT_CLEAR_AMPDU_MAX_TIME_8814B(x) | BIT_AMPDU_MAX_TIME_8814B(v)) + +/* 2 REG_TAB_SEL_8814B */ + +#define BIT_SHIFT_RATE_SEL_8814B 0 +#define BIT_MASK_RATE_SEL_8814B 0xf +#define BIT_RATE_SEL_8814B(x) \ + (((x) & BIT_MASK_RATE_SEL_8814B) << BIT_SHIFT_RATE_SEL_8814B) +#define BITS_RATE_SEL_8814B \ + (BIT_MASK_RATE_SEL_8814B << BIT_SHIFT_RATE_SEL_8814B) +#define BIT_CLEAR_RATE_SEL_8814B(x) ((x) & (~BITS_RATE_SEL_8814B)) +#define BIT_GET_RATE_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_RATE_SEL_8814B) & BIT_MASK_RATE_SEL_8814B) +#define BIT_SET_RATE_SEL_8814B(x, v) \ + (BIT_CLEAR_RATE_SEL_8814B(x) | BIT_RATE_SEL_8814B(v)) + +/* 2 REG_BCN_INVALID_CTRL_8814B */ +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P4_8814B BIT(7) +#define BIT_EN_BCN_PKT_REL_P4_8814B BIT(6) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P3_8814B BIT(5) +#define BIT_EN_BCN_PKT_REL_P3_8814B BIT(4) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P2_8814B BIT(3) +#define BIT_EN_BCN_PKT_REL_P2_8814B BIT(2) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P1_8814B BIT(1) +#define BIT_EN_BCN_PKT_REL_P1_8814B BIT(0) + +/* 2 REG_AMPDU_MAX_LENGTH_HT_8814B */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B 0xffff +#define BIT_AMPDU_MAX_LENGTH_HT_8814B(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B) +#define BITS_AMPDU_MAX_LENGTH_HT_8814B \ + (BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8814B(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_HT_8814B)) +#define BIT_GET_AMPDU_MAX_LENGTH_HT_8814B(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B) & \ + BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B) +#define BIT_SET_AMPDU_MAX_LENGTH_HT_8814B(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8814B(x) | \ + BIT_AMPDU_MAX_LENGTH_HT_8814B(v)) -#define BIT_SHIFT_HI0Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI0Q_DESC_MODE_8814B 0x3 -#define BIT_HI0Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8814B) << BIT_SHIFT_HI0Q_DESC_MODE_8814B) -#define BIT_GET_HI0Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8814B) & BIT_MASK_HI0Q_DESC_MODE_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NDPA_RATE_8814B */ +#define BIT_SHIFT_R_NDPA_RATE_V1_8814B 0 +#define BIT_MASK_R_NDPA_RATE_V1_8814B 0xff +#define BIT_R_NDPA_RATE_V1_8814B(x) \ + (((x) & BIT_MASK_R_NDPA_RATE_V1_8814B) \ + << BIT_SHIFT_R_NDPA_RATE_V1_8814B) +#define BITS_R_NDPA_RATE_V1_8814B \ + (BIT_MASK_R_NDPA_RATE_V1_8814B << BIT_SHIFT_R_NDPA_RATE_V1_8814B) +#define BIT_CLEAR_R_NDPA_RATE_V1_8814B(x) ((x) & (~BITS_R_NDPA_RATE_V1_8814B)) +#define BIT_GET_R_NDPA_RATE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8814B) & \ + BIT_MASK_R_NDPA_RATE_V1_8814B) +#define BIT_SET_R_NDPA_RATE_V1_8814B(x, v) \ + (BIT_CLEAR_R_NDPA_RATE_V1_8814B(x) | BIT_R_NDPA_RATE_V1_8814B(v)) -#define BIT_SHIFT_HI0Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI0Q_DESC_NUM_8814B 0xfff -#define BIT_HI0Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8814B) << BIT_SHIFT_HI0Q_DESC_NUM_8814B) -#define BIT_GET_HI0Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8814B) & BIT_MASK_HI0Q_DESC_NUM_8814B) +/* 2 REG_TX_HANG_CTRL_8814B */ +#define BIT_EN_GNT_BT_AWAKE_8814B BIT(3) +#define BIT_EN_EOF_V1_8814B BIT(2) +#define BIT_DIS_OQT_BLOCK_8814B BIT(1) +#define BIT_SEARCH_QUEUE_EN_8814B BIT(0) +/* 2 REG_NDPA_OPT_CTRL_8814B */ +#define BIT_DIS_MACID_RELEASE_RTY_8814B BIT(5) +#define BIT_SHIFT_BW_SIGTA_8814B 3 +#define BIT_MASK_BW_SIGTA_8814B 0x3 +#define BIT_BW_SIGTA_8814B(x) \ + (((x) & BIT_MASK_BW_SIGTA_8814B) << BIT_SHIFT_BW_SIGTA_8814B) +#define BITS_BW_SIGTA_8814B \ + (BIT_MASK_BW_SIGTA_8814B << BIT_SHIFT_BW_SIGTA_8814B) +#define BIT_CLEAR_BW_SIGTA_8814B(x) ((x) & (~BITS_BW_SIGTA_8814B)) +#define BIT_GET_BW_SIGTA_8814B(x) \ + (((x) >> BIT_SHIFT_BW_SIGTA_8814B) & BIT_MASK_BW_SIGTA_8814B) +#define BIT_SET_BW_SIGTA_8814B(x, v) \ + (BIT_CLEAR_BW_SIGTA_8814B(x) | BIT_BW_SIGTA_8814B(v)) -/* 2 REG_HI1Q_TXBD_NUM_8814B */ -#define BIT_HI1Q_FLAG_8814B BIT(14) +#define BIT_EN_BAR_SIGTA_8814B BIT(2) -#define BIT_SHIFT_HI1Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI1Q_DESC_MODE_8814B 0x3 -#define BIT_HI1Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8814B) << BIT_SHIFT_HI1Q_DESC_MODE_8814B) -#define BIT_GET_HI1Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8814B) & BIT_MASK_HI1Q_DESC_MODE_8814B) +#define BIT_SHIFT_NDPA_BW_8814B 0 +#define BIT_MASK_NDPA_BW_8814B 0x3 +#define BIT_NDPA_BW_8814B(x) \ + (((x) & BIT_MASK_NDPA_BW_8814B) << BIT_SHIFT_NDPA_BW_8814B) +#define BITS_NDPA_BW_8814B (BIT_MASK_NDPA_BW_8814B << BIT_SHIFT_NDPA_BW_8814B) +#define BIT_CLEAR_NDPA_BW_8814B(x) ((x) & (~BITS_NDPA_BW_8814B)) +#define BIT_GET_NDPA_BW_8814B(x) \ + (((x) >> BIT_SHIFT_NDPA_BW_8814B) & BIT_MASK_NDPA_BW_8814B) +#define BIT_SET_NDPA_BW_8814B(x, v) \ + (BIT_CLEAR_NDPA_BW_8814B(x) | BIT_NDPA_BW_8814B(v)) + +/* 2 REG_AMPDU_MAX_LENGTH_VHT_8814B */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B 0x3ffff +#define BIT_AMPDU_MAX_LENGTH_VHT_8814B(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B) +#define BITS_AMPDU_MAX_LENGTH_VHT_8814B \ + (BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_8814B(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_8814B)) +#define BIT_GET_AMPDU_MAX_LENGTH_VHT_8814B(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B) & \ + BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B) +#define BIT_SET_AMPDU_MAX_LENGTH_VHT_8814B(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_8814B(x) | \ + BIT_AMPDU_MAX_LENGTH_VHT_8814B(v)) +/* 2 REG_RD_RESP_PKT_TH_8814B */ +#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B 0 +#define BIT_MASK_RD_RESP_PKT_TH_V1_8814B 0x3f +#define BIT_RD_RESP_PKT_TH_V1_8814B(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8814B) \ + << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) +#define BITS_RD_RESP_PKT_TH_V1_8814B \ + (BIT_MASK_RD_RESP_PKT_TH_V1_8814B << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8814B(x) \ + ((x) & (~BITS_RD_RESP_PKT_TH_V1_8814B)) +#define BIT_GET_RD_RESP_PKT_TH_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) & \ + BIT_MASK_RD_RESP_PKT_TH_V1_8814B) +#define BIT_SET_RD_RESP_PKT_TH_V1_8814B(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH_V1_8814B(x) | BIT_RD_RESP_PKT_TH_V1_8814B(v)) + +/* 2 REG_NEW_EDCA_CTRL_V1_8814B */ + +#define BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B 9 +#define BIT_MASK_RANDOM_VALUE_SHIFT_8814B 0x7 +#define BIT_RANDOM_VALUE_SHIFT_8814B(x) \ + (((x) & BIT_MASK_RANDOM_VALUE_SHIFT_8814B) \ + << BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B) +#define BITS_RANDOM_VALUE_SHIFT_8814B \ + (BIT_MASK_RANDOM_VALUE_SHIFT_8814B \ + << BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B) +#define BIT_CLEAR_RANDOM_VALUE_SHIFT_8814B(x) \ + ((x) & (~BITS_RANDOM_VALUE_SHIFT_8814B)) +#define BIT_GET_RANDOM_VALUE_SHIFT_8814B(x) \ + (((x) >> BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B) & \ + BIT_MASK_RANDOM_VALUE_SHIFT_8814B) +#define BIT_SET_RANDOM_VALUE_SHIFT_8814B(x, v) \ + (BIT_CLEAR_RANDOM_VALUE_SHIFT_8814B(x) | \ + BIT_RANDOM_VALUE_SHIFT_8814B(v)) + +#define BIT_ENABLE_NEW_EDCA_8814B BIT(8) + +#define BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B 0 +#define BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B 0xff +#define BIT_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) \ + (((x) & BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B) \ + << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B) +#define BITS_MEDIUM_HAS_IDKE_TRIGGER_8814B \ + (BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B \ + << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B) +#define BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) \ + ((x) & (~BITS_MEDIUM_HAS_IDKE_TRIGGER_8814B)) +#define BIT_GET_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) \ + (((x) >> BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B) & \ + BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B) +#define BIT_SET_MEDIUM_HAS_IDKE_TRIGGER_8814B(x, v) \ + (BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) | \ + BIT_MEDIUM_HAS_IDKE_TRIGGER_8814B(v)) + +/* 2 REG_ACQ_STOP_V2_8814B */ +#define BIT_AC19Q_STOP_8814B BIT(19) +#define BIT_AC18Q_STOP_8814B BIT(18) +#define BIT_AC17Q_STOP_8814B BIT(17) +#define BIT_AC16Q_STOP_8814B BIT(16) +#define BIT_AC15Q_STOP_8814B BIT(15) +#define BIT_AC14Q_STOP_8814B BIT(14) +#define BIT_AC13Q_STOP_8814B BIT(13) +#define BIT_AC12Q_STOP_8814B BIT(12) +#define BIT_AC11Q_STOP_8814B BIT(11) +#define BIT_AC10Q_STOP_8814B BIT(10) +#define BIT_AC9Q_STOP_8814B BIT(9) +#define BIT_AC8Q_STOP_8814B BIT(8) +#define BIT_AC7Q_STOP_8814B BIT(7) +#define BIT_AC6Q_STOP_8814B BIT(6) +#define BIT_AC5Q_STOP_8814B BIT(5) +#define BIT_AC4Q_STOP_8814B BIT(4) +#define BIT_AC3Q_STOP_8814B BIT(3) +#define BIT_AC2Q_STOP_8814B BIT(2) +#define BIT_AC1Q_STOP_8814B BIT(1) +#define BIT_AC0Q_STOP_8814B BIT(0) -#define BIT_SHIFT_HI1Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI1Q_DESC_NUM_8814B 0xfff -#define BIT_HI1Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8814B) << BIT_SHIFT_HI1Q_DESC_NUM_8814B) -#define BIT_GET_HI1Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8814B) & BIT_MASK_HI1Q_DESC_NUM_8814B) +/* 2 REG_WMAC_LBK_BUF_HD_V1_8814B */ +#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B 0 +#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B 0xfff +#define BIT_WMAC_LBK_BUF_HEAD_V1_8814B(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B) \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) +#define BITS_WMAC_LBK_BUF_HEAD_V1_8814B \ + (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8814B(x) \ + ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8814B)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) & \ + BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8814B(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8814B(x) | \ + BIT_WMAC_LBK_BUF_HEAD_V1_8814B(v)) +/* 2 REG_MGQ_BDNY_V1_8814B */ -/* 2 REG_HI2Q_TXBD_NUM_8814B */ -#define BIT_HI2Q_FLAG_8814B BIT(14) +#define BIT_SHIFT_MGQ_PGBNDY_V1_8814B 0 +#define BIT_MASK_MGQ_PGBNDY_V1_8814B 0xfff +#define BIT_MGQ_PGBNDY_V1_8814B(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V1_8814B) << BIT_SHIFT_MGQ_PGBNDY_V1_8814B) +#define BITS_MGQ_PGBNDY_V1_8814B \ + (BIT_MASK_MGQ_PGBNDY_V1_8814B << BIT_SHIFT_MGQ_PGBNDY_V1_8814B) +#define BIT_CLEAR_MGQ_PGBNDY_V1_8814B(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8814B)) +#define BIT_GET_MGQ_PGBNDY_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8814B) & BIT_MASK_MGQ_PGBNDY_V1_8814B) +#define BIT_SET_MGQ_PGBNDY_V1_8814B(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V1_8814B(x) | BIT_MGQ_PGBNDY_V1_8814B(v)) -#define BIT_SHIFT_HI2Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI2Q_DESC_MODE_8814B 0x3 -#define BIT_HI2Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8814B) << BIT_SHIFT_HI2Q_DESC_MODE_8814B) -#define BIT_GET_HI2Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8814B) & BIT_MASK_HI2Q_DESC_MODE_8814B) +/* 2 REG_TXRPT_CTRL_8814B */ +#define BIT_SHIFT_TRXRPT_TIMER_TH_8814B 24 +#define BIT_MASK_TRXRPT_TIMER_TH_8814B 0xff +#define BIT_TRXRPT_TIMER_TH_8814B(x) \ + (((x) & BIT_MASK_TRXRPT_TIMER_TH_8814B) \ + << BIT_SHIFT_TRXRPT_TIMER_TH_8814B) +#define BITS_TRXRPT_TIMER_TH_8814B \ + (BIT_MASK_TRXRPT_TIMER_TH_8814B << BIT_SHIFT_TRXRPT_TIMER_TH_8814B) +#define BIT_CLEAR_TRXRPT_TIMER_TH_8814B(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8814B)) +#define BIT_GET_TRXRPT_TIMER_TH_8814B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8814B) & \ + BIT_MASK_TRXRPT_TIMER_TH_8814B) +#define BIT_SET_TRXRPT_TIMER_TH_8814B(x, v) \ + (BIT_CLEAR_TRXRPT_TIMER_TH_8814B(x) | BIT_TRXRPT_TIMER_TH_8814B(v)) +#define BIT_SHIFT_TRXRPT_LEN_TH_8814B 16 +#define BIT_MASK_TRXRPT_LEN_TH_8814B 0xff +#define BIT_TRXRPT_LEN_TH_8814B(x) \ + (((x) & BIT_MASK_TRXRPT_LEN_TH_8814B) << BIT_SHIFT_TRXRPT_LEN_TH_8814B) +#define BITS_TRXRPT_LEN_TH_8814B \ + (BIT_MASK_TRXRPT_LEN_TH_8814B << BIT_SHIFT_TRXRPT_LEN_TH_8814B) +#define BIT_CLEAR_TRXRPT_LEN_TH_8814B(x) ((x) & (~BITS_TRXRPT_LEN_TH_8814B)) +#define BIT_GET_TRXRPT_LEN_TH_8814B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8814B) & BIT_MASK_TRXRPT_LEN_TH_8814B) +#define BIT_SET_TRXRPT_LEN_TH_8814B(x, v) \ + (BIT_CLEAR_TRXRPT_LEN_TH_8814B(x) | BIT_TRXRPT_LEN_TH_8814B(v)) -#define BIT_SHIFT_HI2Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI2Q_DESC_NUM_8814B 0xfff -#define BIT_HI2Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8814B) << BIT_SHIFT_HI2Q_DESC_NUM_8814B) -#define BIT_GET_HI2Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8814B) & BIT_MASK_HI2Q_DESC_NUM_8814B) +#define BIT_SHIFT_TRXRPT_READ_PTR_8814B 8 +#define BIT_MASK_TRXRPT_READ_PTR_8814B 0xff +#define BIT_TRXRPT_READ_PTR_8814B(x) \ + (((x) & BIT_MASK_TRXRPT_READ_PTR_8814B) \ + << BIT_SHIFT_TRXRPT_READ_PTR_8814B) +#define BITS_TRXRPT_READ_PTR_8814B \ + (BIT_MASK_TRXRPT_READ_PTR_8814B << BIT_SHIFT_TRXRPT_READ_PTR_8814B) +#define BIT_CLEAR_TRXRPT_READ_PTR_8814B(x) ((x) & (~BITS_TRXRPT_READ_PTR_8814B)) +#define BIT_GET_TRXRPT_READ_PTR_8814B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8814B) & \ + BIT_MASK_TRXRPT_READ_PTR_8814B) +#define BIT_SET_TRXRPT_READ_PTR_8814B(x, v) \ + (BIT_CLEAR_TRXRPT_READ_PTR_8814B(x) | BIT_TRXRPT_READ_PTR_8814B(v)) +#define BIT_SHIFT_TRXRPT_WRITE_PTR_8814B 0 +#define BIT_MASK_TRXRPT_WRITE_PTR_8814B 0xff +#define BIT_TRXRPT_WRITE_PTR_8814B(x) \ + (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8814B) \ + << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) +#define BITS_TRXRPT_WRITE_PTR_8814B \ + (BIT_MASK_TRXRPT_WRITE_PTR_8814B << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) +#define BIT_CLEAR_TRXRPT_WRITE_PTR_8814B(x) \ + ((x) & (~BITS_TRXRPT_WRITE_PTR_8814B)) +#define BIT_GET_TRXRPT_WRITE_PTR_8814B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) & \ + BIT_MASK_TRXRPT_WRITE_PTR_8814B) +#define BIT_SET_TRXRPT_WRITE_PTR_8814B(x, v) \ + (BIT_CLEAR_TRXRPT_WRITE_PTR_8814B(x) | BIT_TRXRPT_WRITE_PTR_8814B(v)) +/* 2 REG_INIRTS_RATE_SEL_8814B */ +#define BIT_LEAG_RTS_BW_DUP_8814B BIT(5) -/* 2 REG_HI3Q_TXBD_NUM_8814B */ -#define BIT_HI3Q_FLAG_8814B BIT(14) +/* 2 REG_BASIC_CFEND_RATE_8814B */ -#define BIT_SHIFT_HI3Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI3Q_DESC_MODE_8814B 0x3 -#define BIT_HI3Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8814B) << BIT_SHIFT_HI3Q_DESC_MODE_8814B) -#define BIT_GET_HI3Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8814B) & BIT_MASK_HI3Q_DESC_MODE_8814B) +#define BIT_SHIFT_BASIC_CFEND_RATE_8814B 0 +#define BIT_MASK_BASIC_CFEND_RATE_8814B 0x1f +#define BIT_BASIC_CFEND_RATE_8814B(x) \ + (((x) & BIT_MASK_BASIC_CFEND_RATE_8814B) \ + << BIT_SHIFT_BASIC_CFEND_RATE_8814B) +#define BITS_BASIC_CFEND_RATE_8814B \ + (BIT_MASK_BASIC_CFEND_RATE_8814B << BIT_SHIFT_BASIC_CFEND_RATE_8814B) +#define BIT_CLEAR_BASIC_CFEND_RATE_8814B(x) \ + ((x) & (~BITS_BASIC_CFEND_RATE_8814B)) +#define BIT_GET_BASIC_CFEND_RATE_8814B(x) \ + (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8814B) & \ + BIT_MASK_BASIC_CFEND_RATE_8814B) +#define BIT_SET_BASIC_CFEND_RATE_8814B(x, v) \ + (BIT_CLEAR_BASIC_CFEND_RATE_8814B(x) | BIT_BASIC_CFEND_RATE_8814B(v)) +/* 2 REG_STBC_CFEND_RATE_8814B */ +#define BIT_SHIFT_STBC_CFEND_RATE_8814B 0 +#define BIT_MASK_STBC_CFEND_RATE_8814B 0x1f +#define BIT_STBC_CFEND_RATE_8814B(x) \ + (((x) & BIT_MASK_STBC_CFEND_RATE_8814B) \ + << BIT_SHIFT_STBC_CFEND_RATE_8814B) +#define BITS_STBC_CFEND_RATE_8814B \ + (BIT_MASK_STBC_CFEND_RATE_8814B << BIT_SHIFT_STBC_CFEND_RATE_8814B) +#define BIT_CLEAR_STBC_CFEND_RATE_8814B(x) ((x) & (~BITS_STBC_CFEND_RATE_8814B)) +#define BIT_GET_STBC_CFEND_RATE_8814B(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8814B) & \ + BIT_MASK_STBC_CFEND_RATE_8814B) +#define BIT_SET_STBC_CFEND_RATE_8814B(x, v) \ + (BIT_CLEAR_STBC_CFEND_RATE_8814B(x) | BIT_STBC_CFEND_RATE_8814B(v)) -#define BIT_SHIFT_HI3Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI3Q_DESC_NUM_8814B 0xfff -#define BIT_HI3Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8814B) << BIT_SHIFT_HI3Q_DESC_NUM_8814B) -#define BIT_GET_HI3Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8814B) & BIT_MASK_HI3Q_DESC_NUM_8814B) +/* 2 REG_DATA_SC_8814B */ +#define BIT_SHIFT_TXSC_40M_8814B 4 +#define BIT_MASK_TXSC_40M_8814B 0xf +#define BIT_TXSC_40M_8814B(x) \ + (((x) & BIT_MASK_TXSC_40M_8814B) << BIT_SHIFT_TXSC_40M_8814B) +#define BITS_TXSC_40M_8814B \ + (BIT_MASK_TXSC_40M_8814B << BIT_SHIFT_TXSC_40M_8814B) +#define BIT_CLEAR_TXSC_40M_8814B(x) ((x) & (~BITS_TXSC_40M_8814B)) +#define BIT_GET_TXSC_40M_8814B(x) \ + (((x) >> BIT_SHIFT_TXSC_40M_8814B) & BIT_MASK_TXSC_40M_8814B) +#define BIT_SET_TXSC_40M_8814B(x, v) \ + (BIT_CLEAR_TXSC_40M_8814B(x) | BIT_TXSC_40M_8814B(v)) +#define BIT_SHIFT_TXSC_20M_8814B 0 +#define BIT_MASK_TXSC_20M_8814B 0xf +#define BIT_TXSC_20M_8814B(x) \ + (((x) & BIT_MASK_TXSC_20M_8814B) << BIT_SHIFT_TXSC_20M_8814B) +#define BITS_TXSC_20M_8814B \ + (BIT_MASK_TXSC_20M_8814B << BIT_SHIFT_TXSC_20M_8814B) +#define BIT_CLEAR_TXSC_20M_8814B(x) ((x) & (~BITS_TXSC_20M_8814B)) +#define BIT_GET_TXSC_20M_8814B(x) \ + (((x) >> BIT_SHIFT_TXSC_20M_8814B) & BIT_MASK_TXSC_20M_8814B) +#define BIT_SET_TXSC_20M_8814B(x, v) \ + (BIT_CLEAR_TXSC_20M_8814B(x) | BIT_TXSC_20M_8814B(v)) + +/* 2 REG_MOREDATA_V1_8814B */ +#define BIT_MOREDATA_CTRL2_EN_V1_8814B BIT(3) +#define BIT_MOREDATA_CTRL1_EN_V1_8814B BIT(2) +#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8814B BIT(0) -/* 2 REG_HI4Q_TXBD_NUM_8814B */ -#define BIT_HI4Q_FLAG_8814B BIT(14) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_HI4Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI4Q_DESC_MODE_8814B 0x3 -#define BIT_HI4Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8814B) << BIT_SHIFT_HI4Q_DESC_MODE_8814B) -#define BIT_GET_HI4Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8814B) & BIT_MASK_HI4Q_DESC_MODE_8814B) +/* 2 REG_DATA_SC1_8814B */ + +#define BIT_SHIFT_TXSC_160M_8814B 4 +#define BIT_MASK_TXSC_160M_8814B 0xf +#define BIT_TXSC_160M_8814B(x) \ + (((x) & BIT_MASK_TXSC_160M_8814B) << BIT_SHIFT_TXSC_160M_8814B) +#define BITS_TXSC_160M_8814B \ + (BIT_MASK_TXSC_160M_8814B << BIT_SHIFT_TXSC_160M_8814B) +#define BIT_CLEAR_TXSC_160M_8814B(x) ((x) & (~BITS_TXSC_160M_8814B)) +#define BIT_GET_TXSC_160M_8814B(x) \ + (((x) >> BIT_SHIFT_TXSC_160M_8814B) & BIT_MASK_TXSC_160M_8814B) +#define BIT_SET_TXSC_160M_8814B(x, v) \ + (BIT_CLEAR_TXSC_160M_8814B(x) | BIT_TXSC_160M_8814B(v)) + +#define BIT_SHIFT_TXSC_80M_8814B 0 +#define BIT_MASK_TXSC_80M_8814B 0xf +#define BIT_TXSC_80M_8814B(x) \ + (((x) & BIT_MASK_TXSC_80M_8814B) << BIT_SHIFT_TXSC_80M_8814B) +#define BITS_TXSC_80M_8814B \ + (BIT_MASK_TXSC_80M_8814B << BIT_SHIFT_TXSC_80M_8814B) +#define BIT_CLEAR_TXSC_80M_8814B(x) ((x) & (~BITS_TXSC_80M_8814B)) +#define BIT_GET_TXSC_80M_8814B(x) \ + (((x) >> BIT_SHIFT_TXSC_80M_8814B) & BIT_MASK_TXSC_80M_8814B) +#define BIT_SET_TXSC_80M_8814B(x, v) \ + (BIT_CLEAR_TXSC_80M_8814B(x) | BIT_TXSC_80M_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_TXRPT_START_OFFSET_8814B */ +#define BIT_RPTFIFO_RPTNUM_OPT_8814B BIT(31) + +#define BIT_SHIFT_MISSED_RPT_NUM_8814B 28 +#define BIT_MASK_MISSED_RPT_NUM_8814B 0x7 +#define BIT_MISSED_RPT_NUM_8814B(x) \ + (((x) & BIT_MASK_MISSED_RPT_NUM_8814B) \ + << BIT_SHIFT_MISSED_RPT_NUM_8814B) +#define BITS_MISSED_RPT_NUM_8814B \ + (BIT_MASK_MISSED_RPT_NUM_8814B << BIT_SHIFT_MISSED_RPT_NUM_8814B) +#define BIT_CLEAR_MISSED_RPT_NUM_8814B(x) ((x) & (~BITS_MISSED_RPT_NUM_8814B)) +#define BIT_GET_MISSED_RPT_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_MISSED_RPT_NUM_8814B) & \ + BIT_MASK_MISSED_RPT_NUM_8814B) +#define BIT_SET_MISSED_RPT_NUM_8814B(x, v) \ + (BIT_CLEAR_MISSED_RPT_NUM_8814B(x) | BIT_MISSED_RPT_NUM_8814B(v)) + +#define BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B 16 +#define BIT_MASK_MACID_CTRL_OFFSET_V1_8814B 0x1ff +#define BIT_MACID_CTRL_OFFSET_V1_8814B(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET_V1_8814B) \ + << BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B) +#define BITS_MACID_CTRL_OFFSET_V1_8814B \ + (BIT_MASK_MACID_CTRL_OFFSET_V1_8814B \ + << BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B) +#define BIT_CLEAR_MACID_CTRL_OFFSET_V1_8814B(x) \ + ((x) & (~BITS_MACID_CTRL_OFFSET_V1_8814B)) +#define BIT_GET_MACID_CTRL_OFFSET_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B) & \ + BIT_MASK_MACID_CTRL_OFFSET_V1_8814B) +#define BIT_SET_MACID_CTRL_OFFSET_V1_8814B(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET_V1_8814B(x) | \ + BIT_MACID_CTRL_OFFSET_V1_8814B(v)) + +#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B 0 +#define BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B 0x1ff +#define BIT_AMPDU_TXRPT_OFFSET_V1_8814B(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B) \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B) +#define BITS_AMPDU_TXRPT_OFFSET_V1_8814B \ + (BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1_8814B(x) \ + ((x) & (~BITS_AMPDU_TXRPT_OFFSET_V1_8814B)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_V1_8814B(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B) & \ + BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B) +#define BIT_SET_AMPDU_TXRPT_OFFSET_V1_8814B(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1_8814B(x) | \ + BIT_AMPDU_TXRPT_OFFSET_V1_8814B(v)) -#define BIT_SHIFT_HI4Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI4Q_DESC_NUM_8814B 0xfff -#define BIT_HI4Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8814B) << BIT_SHIFT_HI4Q_DESC_NUM_8814B) -#define BIT_GET_HI4Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8814B) & BIT_MASK_HI4Q_DESC_NUM_8814B) - - - -/* 2 REG_HI5Q_TXBD_NUM_8814B */ -#define BIT_HI5Q_FLAG_8814B BIT(14) - -#define BIT_SHIFT_HI5Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI5Q_DESC_MODE_8814B 0x3 -#define BIT_HI5Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8814B) << BIT_SHIFT_HI5Q_DESC_MODE_8814B) -#define BIT_GET_HI5Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8814B) & BIT_MASK_HI5Q_DESC_MODE_8814B) - - - -#define BIT_SHIFT_HI5Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI5Q_DESC_NUM_8814B 0xfff -#define BIT_HI5Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8814B) << BIT_SHIFT_HI5Q_DESC_NUM_8814B) -#define BIT_GET_HI5Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8814B) & BIT_MASK_HI5Q_DESC_NUM_8814B) - - - -/* 2 REG_HI6Q_TXBD_NUM_8814B */ -#define BIT_HI6Q_FLAG_8814B BIT(14) - -#define BIT_SHIFT_HI6Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI6Q_DESC_MODE_8814B 0x3 -#define BIT_HI6Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8814B) << BIT_SHIFT_HI6Q_DESC_MODE_8814B) -#define BIT_GET_HI6Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8814B) & BIT_MASK_HI6Q_DESC_MODE_8814B) - - - -#define BIT_SHIFT_HI6Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI6Q_DESC_NUM_8814B 0xfff -#define BIT_HI6Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8814B) << BIT_SHIFT_HI6Q_DESC_NUM_8814B) -#define BIT_GET_HI6Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8814B) & BIT_MASK_HI6Q_DESC_NUM_8814B) - - - -/* 2 REG_HI7Q_TXBD_NUM_8814B */ -#define BIT_HI7Q_FLAG_8814B BIT(14) - -#define BIT_SHIFT_HI7Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI7Q_DESC_MODE_8814B 0x3 -#define BIT_HI7Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8814B) << BIT_SHIFT_HI7Q_DESC_MODE_8814B) -#define BIT_GET_HI7Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8814B) & BIT_MASK_HI7Q_DESC_MODE_8814B) - - - -#define BIT_SHIFT_HI7Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI7Q_DESC_NUM_8814B 0xfff -#define BIT_HI7Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8814B) << BIT_SHIFT_HI7Q_DESC_NUM_8814B) -#define BIT_GET_HI7Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8814B) & BIT_MASK_HI7Q_DESC_NUM_8814B) - - - -/* 2 REG_TSFTIMER_HCI_8814B */ - -#define BIT_SHIFT_TSFT2_HCI_8814B 16 -#define BIT_MASK_TSFT2_HCI_8814B 0xffff -#define BIT_TSFT2_HCI_8814B(x) (((x) & BIT_MASK_TSFT2_HCI_8814B) << BIT_SHIFT_TSFT2_HCI_8814B) -#define BIT_GET_TSFT2_HCI_8814B(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8814B) & BIT_MASK_TSFT2_HCI_8814B) - - - -#define BIT_SHIFT_TSFT1_HCI_8814B 0 -#define BIT_MASK_TSFT1_HCI_8814B 0xffff -#define BIT_TSFT1_HCI_8814B(x) (((x) & BIT_MASK_TSFT1_HCI_8814B) << BIT_SHIFT_TSFT1_HCI_8814B) -#define BIT_GET_TSFT1_HCI_8814B(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8814B) & BIT_MASK_TSFT1_HCI_8814B) - - - -/* 2 REG_BD_RWPTR_CLR_8814B */ -#define BIT_CLR_HI7Q_HW_IDX_8814B BIT(29) -#define BIT_CLR_HI6Q_HW_IDX_8814B BIT(28) -#define BIT_CLR_HI5Q_HW_IDX_8814B BIT(27) -#define BIT_CLR_HI4Q_HW_IDX_8814B BIT(26) -#define BIT_CLR_HI3Q_HW_IDX_8814B BIT(25) -#define BIT_CLR_HI2Q_HW_IDX_8814B BIT(24) -#define BIT_CLR_HI1Q_HW_IDX_8814B BIT(23) -#define BIT_CLR_HI0Q_HW_IDX_8814B BIT(22) -#define BIT_CLR_BKQ_HW_IDX_8814B BIT(21) -#define BIT_CLR_BEQ_HW_IDX_8814B BIT(20) -#define BIT_CLR_VIQ_HW_IDX_8814B BIT(19) -#define BIT_CLR_VOQ_HW_IDX_8814B BIT(18) -#define BIT_CLR_MGQ_HW_IDX_8814B BIT(17) -#define BIT_CLR_RXQ_HW_IDX_8814B BIT(16) -#define BIT_CLR_HI7Q_HOST_IDX_8814B BIT(13) -#define BIT_CLR_HI6Q_HOST_IDX_8814B BIT(12) -#define BIT_CLR_HI5Q_HOST_IDX_8814B BIT(11) -#define BIT_CLR_HI4Q_HOST_IDX_8814B BIT(10) -#define BIT_CLR_HI3Q_HOST_IDX_8814B BIT(9) -#define BIT_CLR_HI2Q_HOST_IDX_8814B BIT(8) -#define BIT_CLR_HI1Q_HOST_IDX_8814B BIT(7) -#define BIT_CLR_HI0Q_HOST_IDX_8814B BIT(6) -#define BIT_CLR_BKQ_HOST_IDX_8814B BIT(5) -#define BIT_CLR_BEQ_HOST_IDX_8814B BIT(4) -#define BIT_CLR_VIQ_HOST_IDX_8814B BIT(3) -#define BIT_CLR_VOQ_HOST_IDX_8814B BIT(2) -#define BIT_CLR_MGQ_HOST_IDX_8814B BIT(1) -#define BIT_CLR_RXQ_HOST_IDX_8814B BIT(0) - -/* 2 REG_VOQ_TXBD_IDX_8814B */ - -#define BIT_SHIFT_VOQ_HW_IDX_8814B 16 -#define BIT_MASK_VOQ_HW_IDX_8814B 0xfff -#define BIT_VOQ_HW_IDX_8814B(x) (((x) & BIT_MASK_VOQ_HW_IDX_8814B) << BIT_SHIFT_VOQ_HW_IDX_8814B) -#define BIT_GET_VOQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8814B) & BIT_MASK_VOQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_VOQ_HOST_IDX_8814B 0 -#define BIT_MASK_VOQ_HOST_IDX_8814B 0xfff -#define BIT_VOQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8814B) << BIT_SHIFT_VOQ_HOST_IDX_8814B) -#define BIT_GET_VOQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8814B) & BIT_MASK_VOQ_HOST_IDX_8814B) - - - -/* 2 REG_VIQ_TXBD_IDX_8814B */ - -#define BIT_SHIFT_VIQ_HW_IDX_8814B 16 -#define BIT_MASK_VIQ_HW_IDX_8814B 0xfff -#define BIT_VIQ_HW_IDX_8814B(x) (((x) & BIT_MASK_VIQ_HW_IDX_8814B) << BIT_SHIFT_VIQ_HW_IDX_8814B) -#define BIT_GET_VIQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8814B) & BIT_MASK_VIQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_VIQ_HOST_IDX_8814B 0 -#define BIT_MASK_VIQ_HOST_IDX_8814B 0xfff -#define BIT_VIQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8814B) << BIT_SHIFT_VIQ_HOST_IDX_8814B) -#define BIT_GET_VIQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8814B) & BIT_MASK_VIQ_HOST_IDX_8814B) - - - -/* 2 REG_BEQ_TXBD_IDX_8814B */ - -#define BIT_SHIFT_BEQ_HW_IDX_8814B 16 -#define BIT_MASK_BEQ_HW_IDX_8814B 0xfff -#define BIT_BEQ_HW_IDX_8814B(x) (((x) & BIT_MASK_BEQ_HW_IDX_8814B) << BIT_SHIFT_BEQ_HW_IDX_8814B) -#define BIT_GET_BEQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8814B) & BIT_MASK_BEQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_BEQ_HOST_IDX_8814B 0 -#define BIT_MASK_BEQ_HOST_IDX_8814B 0xfff -#define BIT_BEQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8814B) << BIT_SHIFT_BEQ_HOST_IDX_8814B) -#define BIT_GET_BEQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8814B) & BIT_MASK_BEQ_HOST_IDX_8814B) - - - -/* 2 REG_BKQ_TXBD_IDX_8814B */ - -#define BIT_SHIFT_BKQ_HW_IDX_8814B 16 -#define BIT_MASK_BKQ_HW_IDX_8814B 0xfff -#define BIT_BKQ_HW_IDX_8814B(x) (((x) & BIT_MASK_BKQ_HW_IDX_8814B) << BIT_SHIFT_BKQ_HW_IDX_8814B) -#define BIT_GET_BKQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8814B) & BIT_MASK_BKQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_BKQ_HOST_IDX_8814B 0 -#define BIT_MASK_BKQ_HOST_IDX_8814B 0xfff -#define BIT_BKQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8814B) << BIT_SHIFT_BKQ_HOST_IDX_8814B) -#define BIT_GET_BKQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8814B) & BIT_MASK_BKQ_HOST_IDX_8814B) - - - -/* 2 REG_MGQ_TXBD_IDX_8814B */ - -#define BIT_SHIFT_MGQ_HW_IDX_8814B 16 -#define BIT_MASK_MGQ_HW_IDX_8814B 0xfff -#define BIT_MGQ_HW_IDX_8814B(x) (((x) & BIT_MASK_MGQ_HW_IDX_8814B) << BIT_SHIFT_MGQ_HW_IDX_8814B) -#define BIT_GET_MGQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8814B) & BIT_MASK_MGQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_MGQ_HOST_IDX_8814B 0 -#define BIT_MASK_MGQ_HOST_IDX_8814B 0xfff -#define BIT_MGQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8814B) << BIT_SHIFT_MGQ_HOST_IDX_8814B) -#define BIT_GET_MGQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8814B) & BIT_MASK_MGQ_HOST_IDX_8814B) - - - -/* 2 REG_RXQ_RXBD_IDX_8814B */ - -#define BIT_SHIFT_RXQ_HW_IDX_8814B 16 -#define BIT_MASK_RXQ_HW_IDX_8814B 0xfff -#define BIT_RXQ_HW_IDX_8814B(x) (((x) & BIT_MASK_RXQ_HW_IDX_8814B) << BIT_SHIFT_RXQ_HW_IDX_8814B) -#define BIT_GET_RXQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8814B) & BIT_MASK_RXQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_RXQ_HOST_IDX_8814B 0 -#define BIT_MASK_RXQ_HOST_IDX_8814B 0xfff -#define BIT_RXQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8814B) << BIT_SHIFT_RXQ_HOST_IDX_8814B) -#define BIT_GET_RXQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8814B) & BIT_MASK_RXQ_HOST_IDX_8814B) - - - -/* 2 REG_HI0Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI0Q_HW_IDX_8814B 16 -#define BIT_MASK_HI0Q_HW_IDX_8814B 0xfff -#define BIT_HI0Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8814B) << BIT_SHIFT_HI0Q_HW_IDX_8814B) -#define BIT_GET_HI0Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8814B) & BIT_MASK_HI0Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI0Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI0Q_HOST_IDX_8814B 0xfff -#define BIT_HI0Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8814B) << BIT_SHIFT_HI0Q_HOST_IDX_8814B) -#define BIT_GET_HI0Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8814B) & BIT_MASK_HI0Q_HOST_IDX_8814B) - - - -/* 2 REG_HI1Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI1Q_HW_IDX_8814B 16 -#define BIT_MASK_HI1Q_HW_IDX_8814B 0xfff -#define BIT_HI1Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8814B) << BIT_SHIFT_HI1Q_HW_IDX_8814B) -#define BIT_GET_HI1Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8814B) & BIT_MASK_HI1Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI1Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI1Q_HOST_IDX_8814B 0xfff -#define BIT_HI1Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8814B) << BIT_SHIFT_HI1Q_HOST_IDX_8814B) -#define BIT_GET_HI1Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8814B) & BIT_MASK_HI1Q_HOST_IDX_8814B) - - - -/* 2 REG_HI2Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI2Q_HW_IDX_8814B 16 -#define BIT_MASK_HI2Q_HW_IDX_8814B 0xfff -#define BIT_HI2Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8814B) << BIT_SHIFT_HI2Q_HW_IDX_8814B) -#define BIT_GET_HI2Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8814B) & BIT_MASK_HI2Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI2Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI2Q_HOST_IDX_8814B 0xfff -#define BIT_HI2Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8814B) << BIT_SHIFT_HI2Q_HOST_IDX_8814B) -#define BIT_GET_HI2Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8814B) & BIT_MASK_HI2Q_HOST_IDX_8814B) - - - -/* 2 REG_HI3Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI3Q_HW_IDX_8814B 16 -#define BIT_MASK_HI3Q_HW_IDX_8814B 0xfff -#define BIT_HI3Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8814B) << BIT_SHIFT_HI3Q_HW_IDX_8814B) -#define BIT_GET_HI3Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8814B) & BIT_MASK_HI3Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI3Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI3Q_HOST_IDX_8814B 0xfff -#define BIT_HI3Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8814B) << BIT_SHIFT_HI3Q_HOST_IDX_8814B) -#define BIT_GET_HI3Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8814B) & BIT_MASK_HI3Q_HOST_IDX_8814B) - - - -/* 2 REG_HI4Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI4Q_HW_IDX_8814B 16 -#define BIT_MASK_HI4Q_HW_IDX_8814B 0xfff -#define BIT_HI4Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8814B) << BIT_SHIFT_HI4Q_HW_IDX_8814B) -#define BIT_GET_HI4Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8814B) & BIT_MASK_HI4Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI4Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI4Q_HOST_IDX_8814B 0xfff -#define BIT_HI4Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8814B) << BIT_SHIFT_HI4Q_HOST_IDX_8814B) -#define BIT_GET_HI4Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8814B) & BIT_MASK_HI4Q_HOST_IDX_8814B) - - - -/* 2 REG_HI5Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI5Q_HW_IDX_8814B 16 -#define BIT_MASK_HI5Q_HW_IDX_8814B 0xfff -#define BIT_HI5Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8814B) << BIT_SHIFT_HI5Q_HW_IDX_8814B) -#define BIT_GET_HI5Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8814B) & BIT_MASK_HI5Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI5Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI5Q_HOST_IDX_8814B 0xfff -#define BIT_HI5Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8814B) << BIT_SHIFT_HI5Q_HOST_IDX_8814B) -#define BIT_GET_HI5Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8814B) & BIT_MASK_HI5Q_HOST_IDX_8814B) - - - -/* 2 REG_HI6Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI6Q_HW_IDX_8814B 16 -#define BIT_MASK_HI6Q_HW_IDX_8814B 0xfff -#define BIT_HI6Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8814B) << BIT_SHIFT_HI6Q_HW_IDX_8814B) -#define BIT_GET_HI6Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8814B) & BIT_MASK_HI6Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI6Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI6Q_HOST_IDX_8814B 0xfff -#define BIT_HI6Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8814B) << BIT_SHIFT_HI6Q_HOST_IDX_8814B) -#define BIT_GET_HI6Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8814B) & BIT_MASK_HI6Q_HOST_IDX_8814B) - - - -/* 2 REG_HI7Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI7Q_HW_IDX_8814B 16 -#define BIT_MASK_HI7Q_HW_IDX_8814B 0xfff -#define BIT_HI7Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8814B) << BIT_SHIFT_HI7Q_HW_IDX_8814B) -#define BIT_GET_HI7Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8814B) & BIT_MASK_HI7Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI7Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI7Q_HOST_IDX_8814B 0xfff -#define BIT_HI7Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8814B) << BIT_SHIFT_HI7Q_HOST_IDX_8814B) -#define BIT_GET_HI7Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8814B) & BIT_MASK_HI7Q_HOST_IDX_8814B) - - - -/* 2 REG_DBG_SEL_V1_8814B */ - -#define BIT_SHIFT_DBG_SEL_8814B 0 -#define BIT_MASK_DBG_SEL_8814B 0xff -#define BIT_DBG_SEL_8814B(x) (((x) & BIT_MASK_DBG_SEL_8814B) << BIT_SHIFT_DBG_SEL_8814B) -#define BIT_GET_DBG_SEL_8814B(x) (((x) >> BIT_SHIFT_DBG_SEL_8814B) & BIT_MASK_DBG_SEL_8814B) - - - -/* 2 REG_PCIE_HRPWM1_V1_8814B */ - -#define BIT_SHIFT_PCIE_HRPWM_8814B 0 -#define BIT_MASK_PCIE_HRPWM_8814B 0xff -#define BIT_PCIE_HRPWM_8814B(x) (((x) & BIT_MASK_PCIE_HRPWM_8814B) << BIT_SHIFT_PCIE_HRPWM_8814B) -#define BIT_GET_PCIE_HRPWM_8814B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM_8814B) & BIT_MASK_PCIE_HRPWM_8814B) - - - -/* 2 REG_PCIE_HCPWM1_V1_8814B */ - -#define BIT_SHIFT_PCIE_HCPWM_8814B 0 -#define BIT_MASK_PCIE_HCPWM_8814B 0xff -#define BIT_PCIE_HCPWM_8814B(x) (((x) & BIT_MASK_PCIE_HCPWM_8814B) << BIT_SHIFT_PCIE_HCPWM_8814B) -#define BIT_GET_PCIE_HCPWM_8814B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM_8814B) & BIT_MASK_PCIE_HCPWM_8814B) - - - -/* 2 REG_PCIE_CTRL2_8814B */ -#define BIT_DIS_TXDMA_PRE_8814B BIT(7) -#define BIT_DIS_RXDMA_PRE_8814B BIT(6) - -#define BIT_SHIFT_HPS_CLKR_PCIE_8814B 4 -#define BIT_MASK_HPS_CLKR_PCIE_8814B 0x3 -#define BIT_HPS_CLKR_PCIE_8814B(x) (((x) & BIT_MASK_HPS_CLKR_PCIE_8814B) << BIT_SHIFT_HPS_CLKR_PCIE_8814B) -#define BIT_GET_HPS_CLKR_PCIE_8814B(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8814B) & BIT_MASK_HPS_CLKR_PCIE_8814B) - - -#define BIT_PCIE_INT_8814B BIT(3) -#define BIT_TXFLAG_EXIT_L1_EN_8814B BIT(2) -#define BIT_EN_RXDMA_ALIGN_8814B BIT(1) -#define BIT_EN_TXDMA_ALIGN_8814B BIT(0) - -/* 2 REG_PCIE_HRPWM2_V1_8814B */ - -#define BIT_SHIFT_PCIE_HRPWM2_8814B 0 -#define BIT_MASK_PCIE_HRPWM2_8814B 0xffff -#define BIT_PCIE_HRPWM2_8814B(x) (((x) & BIT_MASK_PCIE_HRPWM2_8814B) << BIT_SHIFT_PCIE_HRPWM2_8814B) -#define BIT_GET_PCIE_HRPWM2_8814B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2_8814B) & BIT_MASK_PCIE_HRPWM2_8814B) - - - -/* 2 REG_PCIE_HCPWM2_V1_8814B */ - -#define BIT_SHIFT_PCIE_HCPWM2_8814B 0 -#define BIT_MASK_PCIE_HCPWM2_8814B 0xffff -#define BIT_PCIE_HCPWM2_8814B(x) (((x) & BIT_MASK_PCIE_HCPWM2_8814B) << BIT_SHIFT_PCIE_HCPWM2_8814B) -#define BIT_GET_PCIE_HCPWM2_8814B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2_8814B) & BIT_MASK_PCIE_HCPWM2_8814B) - - - -/* 2 REG_PCIE_H2C_MSG_V1_8814B */ - -#define BIT_SHIFT_DRV2FW_INFO_8814B 0 -#define BIT_MASK_DRV2FW_INFO_8814B 0xffffffffL -#define BIT_DRV2FW_INFO_8814B(x) (((x) & BIT_MASK_DRV2FW_INFO_8814B) << BIT_SHIFT_DRV2FW_INFO_8814B) -#define BIT_GET_DRV2FW_INFO_8814B(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8814B) & BIT_MASK_DRV2FW_INFO_8814B) - - - -/* 2 REG_PCIE_C2H_MSG_V1_8814B */ - -#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B 0 -#define BIT_MASK_HCI_PCIE_C2H_MSG_8814B 0xffffffffL -#define BIT_HCI_PCIE_C2H_MSG_8814B(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8814B) << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) -#define BIT_GET_HCI_PCIE_C2H_MSG_8814B(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) & BIT_MASK_HCI_PCIE_C2H_MSG_8814B) - - - -/* 2 REG_DBI_WDATA_V1_8814B */ - -#define BIT_SHIFT_DBI_WDATA_8814B 0 -#define BIT_MASK_DBI_WDATA_8814B 0xffffffffL -#define BIT_DBI_WDATA_8814B(x) (((x) & BIT_MASK_DBI_WDATA_8814B) << BIT_SHIFT_DBI_WDATA_8814B) -#define BIT_GET_DBI_WDATA_8814B(x) (((x) >> BIT_SHIFT_DBI_WDATA_8814B) & BIT_MASK_DBI_WDATA_8814B) - - - -/* 2 REG_DBI_RDATA_V1_8814B */ - -#define BIT_SHIFT_DBI_RDATA_8814B 0 -#define BIT_MASK_DBI_RDATA_8814B 0xffffffffL -#define BIT_DBI_RDATA_8814B(x) (((x) & BIT_MASK_DBI_RDATA_8814B) << BIT_SHIFT_DBI_RDATA_8814B) -#define BIT_GET_DBI_RDATA_8814B(x) (((x) >> BIT_SHIFT_DBI_RDATA_8814B) & BIT_MASK_DBI_RDATA_8814B) - - - -/* 2 REG_DBI_FLAG_V1_8814B */ -#define BIT_EN_STUCK_DBG_8814B BIT(26) -#define BIT_RX_STUCK_8814B BIT(25) -#define BIT_TX_STUCK_8814B BIT(24) -#define BIT_DBI_RFLAG_8814B BIT(17) -#define BIT_DBI_WFLAG_8814B BIT(16) - -#define BIT_SHIFT_DBI_WREN_8814B 12 -#define BIT_MASK_DBI_WREN_8814B 0xf -#define BIT_DBI_WREN_8814B(x) (((x) & BIT_MASK_DBI_WREN_8814B) << BIT_SHIFT_DBI_WREN_8814B) -#define BIT_GET_DBI_WREN_8814B(x) (((x) >> BIT_SHIFT_DBI_WREN_8814B) & BIT_MASK_DBI_WREN_8814B) - - - -#define BIT_SHIFT_DBI_ADDR_8814B 0 -#define BIT_MASK_DBI_ADDR_8814B 0xfff -#define BIT_DBI_ADDR_8814B(x) (((x) & BIT_MASK_DBI_ADDR_8814B) << BIT_SHIFT_DBI_ADDR_8814B) -#define BIT_GET_DBI_ADDR_8814B(x) (((x) >> BIT_SHIFT_DBI_ADDR_8814B) & BIT_MASK_DBI_ADDR_8814B) - - - -/* 2 REG_MDIO_V1_8814B */ - -#define BIT_SHIFT_MDIO_RDATA_8814B 16 -#define BIT_MASK_MDIO_RDATA_8814B 0xffff -#define BIT_MDIO_RDATA_8814B(x) (((x) & BIT_MASK_MDIO_RDATA_8814B) << BIT_SHIFT_MDIO_RDATA_8814B) -#define BIT_GET_MDIO_RDATA_8814B(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8814B) & BIT_MASK_MDIO_RDATA_8814B) - - - -#define BIT_SHIFT_MDIO_WDATA_8814B 0 -#define BIT_MASK_MDIO_WDATA_8814B 0xffff -#define BIT_MDIO_WDATA_8814B(x) (((x) & BIT_MASK_MDIO_WDATA_8814B) << BIT_SHIFT_MDIO_WDATA_8814B) -#define BIT_GET_MDIO_WDATA_8814B(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8814B) & BIT_MASK_MDIO_WDATA_8814B) - - - -/* 2 REG_PCIE_MIX_CFG_8814B */ - -#define BIT_SHIFT_MDIO_PHY_ADDR_8814B 24 -#define BIT_MASK_MDIO_PHY_ADDR_8814B 0x1f -#define BIT_MDIO_PHY_ADDR_8814B(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8814B) << BIT_SHIFT_MDIO_PHY_ADDR_8814B) -#define BIT_GET_MDIO_PHY_ADDR_8814B(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8814B) & BIT_MASK_MDIO_PHY_ADDR_8814B) - - - -#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B 10 -#define BIT_MASK_WATCH_DOG_RECORD_V1_8814B 0x3fff -#define BIT_WATCH_DOG_RECORD_V1_8814B(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8814B) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) -#define BIT_GET_WATCH_DOG_RECORD_V1_8814B(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) & BIT_MASK_WATCH_DOG_RECORD_V1_8814B) - - -#define BIT_R_IO_TIMEOUT_FLAG_V1_8814B BIT(9) -#define BIT_EN_WATCH_DOG_8814B BIT(8) -#define BIT_ECRC_EN_V1_8814B BIT(7) -#define BIT_MDIO_RFLAG_V1_8814B BIT(6) -#define BIT_MDIO_WFLAG_V1_8814B BIT(5) - -#define BIT_SHIFT_MDIO_REG_ADDR_V1_8814B 0 -#define BIT_MASK_MDIO_REG_ADDR_V1_8814B 0x1f -#define BIT_MDIO_REG_ADDR_V1_8814B(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8814B) << BIT_SHIFT_MDIO_REG_ADDR_V1_8814B) -#define BIT_GET_MDIO_REG_ADDR_V1_8814B(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8814B) & BIT_MASK_MDIO_REG_ADDR_V1_8814B) - - - -/* 2 REG_HCI_MIX_CFG_8814B */ -#define BIT_HOST_GEN2_SUPPORT_8814B BIT(20) - -#define BIT_SHIFT_TXDMA_ERR_FLAG_8814B 16 -#define BIT_MASK_TXDMA_ERR_FLAG_8814B 0xf -#define BIT_TXDMA_ERR_FLAG_8814B(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8814B) << BIT_SHIFT_TXDMA_ERR_FLAG_8814B) -#define BIT_GET_TXDMA_ERR_FLAG_8814B(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8814B) & BIT_MASK_TXDMA_ERR_FLAG_8814B) - - - -#define BIT_SHIFT_EARLY_MODE_SEL_8814B 12 -#define BIT_MASK_EARLY_MODE_SEL_8814B 0xf -#define BIT_EARLY_MODE_SEL_8814B(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8814B) << BIT_SHIFT_EARLY_MODE_SEL_8814B) -#define BIT_GET_EARLY_MODE_SEL_8814B(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8814B) & BIT_MASK_EARLY_MODE_SEL_8814B) - - -#define BIT_EPHY_RX50_EN_8814B BIT(11) - -#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B 8 -#define BIT_MASK_MSI_TIMEOUT_ID_V1_8814B 0x7 -#define BIT_MSI_TIMEOUT_ID_V1_8814B(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8814B) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) -#define BIT_GET_MSI_TIMEOUT_ID_V1_8814B(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) & BIT_MASK_MSI_TIMEOUT_ID_V1_8814B) - - -#define BIT_RADDR_RD_8814B BIT(7) -#define BIT_EN_MUL_TAG_8814B BIT(6) -#define BIT_EN_EARLY_MODE_8814B BIT(5) -#define BIT_L0S_LINK_OFF_8814B BIT(4) -#define BIT_ACT_LINK_OFF_8814B BIT(3) -#define BIT_EN_SLOW_MAC_TX_8814B BIT(2) -#define BIT_EN_SLOW_MAC_RX_8814B BIT(1) - -/* 2 REG_STC_INT_CS_8814B(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */ -#define BIT_STC_INT_EN_8814B BIT(31) - -#define BIT_SHIFT_STC_INT_FLAG_8814B 16 -#define BIT_MASK_STC_INT_FLAG_8814B 0xff -#define BIT_STC_INT_FLAG_8814B(x) (((x) & BIT_MASK_STC_INT_FLAG_8814B) << BIT_SHIFT_STC_INT_FLAG_8814B) -#define BIT_GET_STC_INT_FLAG_8814B(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8814B) & BIT_MASK_STC_INT_FLAG_8814B) - - - -#define BIT_SHIFT_STC_INT_IDX_8814B 8 -#define BIT_MASK_STC_INT_IDX_8814B 0x7 -#define BIT_STC_INT_IDX_8814B(x) (((x) & BIT_MASK_STC_INT_IDX_8814B) << BIT_SHIFT_STC_INT_IDX_8814B) -#define BIT_GET_STC_INT_IDX_8814B(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8814B) & BIT_MASK_STC_INT_IDX_8814B) - - - -#define BIT_SHIFT_STC_INT_REALTIME_CS_8814B 0 -#define BIT_MASK_STC_INT_REALTIME_CS_8814B 0x3f -#define BIT_STC_INT_REALTIME_CS_8814B(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8814B) << BIT_SHIFT_STC_INT_REALTIME_CS_8814B) -#define BIT_GET_STC_INT_REALTIME_CS_8814B(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8814B) & BIT_MASK_STC_INT_REALTIME_CS_8814B) - - - -/* 2 REG_ST_INT_CFG_8814B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */ -#define BIT_STC_INT_GRP_EN_8814B BIT(31) - -#define BIT_SHIFT_STC_INT_EXPECT_LS_8814B 8 -#define BIT_MASK_STC_INT_EXPECT_LS_8814B 0x3f -#define BIT_STC_INT_EXPECT_LS_8814B(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8814B) << BIT_SHIFT_STC_INT_EXPECT_LS_8814B) -#define BIT_GET_STC_INT_EXPECT_LS_8814B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8814B) & BIT_MASK_STC_INT_EXPECT_LS_8814B) - - - -#define BIT_SHIFT_STC_INT_EXPECT_CS_8814B 0 -#define BIT_MASK_STC_INT_EXPECT_CS_8814B 0x3f -#define BIT_STC_INT_EXPECT_CS_8814B(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8814B) << BIT_SHIFT_STC_INT_EXPECT_CS_8814B) -#define BIT_GET_STC_INT_EXPECT_CS_8814B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8814B) & BIT_MASK_STC_INT_EXPECT_CS_8814B) - - - -/* 2 REG_CMU_DLY_CTRL_8814B(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */ -#define BIT_CMU_DLY_EN_8814B BIT(31) -#define BIT_CMU_DLY_MODE_8814B BIT(30) - -#define BIT_SHIFT_CMU_DLY_PRE_DIV_8814B 0 -#define BIT_MASK_CMU_DLY_PRE_DIV_8814B 0xff -#define BIT_CMU_DLY_PRE_DIV_8814B(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8814B) << BIT_SHIFT_CMU_DLY_PRE_DIV_8814B) -#define BIT_GET_CMU_DLY_PRE_DIV_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8814B) & BIT_MASK_CMU_DLY_PRE_DIV_8814B) - - - -/* 2 REG_CMU_DLY_CFG_8814B(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ - -#define BIT_SHIFT_CMU_DLY_LTR_A2I_8814B 24 -#define BIT_MASK_CMU_DLY_LTR_A2I_8814B 0xff -#define BIT_CMU_DLY_LTR_A2I_8814B(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8814B) << BIT_SHIFT_CMU_DLY_LTR_A2I_8814B) -#define BIT_GET_CMU_DLY_LTR_A2I_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8814B) & BIT_MASK_CMU_DLY_LTR_A2I_8814B) - - - -#define BIT_SHIFT_CMU_DLY_LTR_I2A_8814B 16 -#define BIT_MASK_CMU_DLY_LTR_I2A_8814B 0xff -#define BIT_CMU_DLY_LTR_I2A_8814B(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8814B) << BIT_SHIFT_CMU_DLY_LTR_I2A_8814B) -#define BIT_GET_CMU_DLY_LTR_I2A_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8814B) & BIT_MASK_CMU_DLY_LTR_I2A_8814B) - - - -#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8814B 8 -#define BIT_MASK_CMU_DLY_LTR_IDLE_8814B 0xff -#define BIT_CMU_DLY_LTR_IDLE_8814B(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8814B) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8814B) -#define BIT_GET_CMU_DLY_LTR_IDLE_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8814B) & BIT_MASK_CMU_DLY_LTR_IDLE_8814B) - - - -#define BIT_SHIFT_CMU_DLY_LTR_ACT_8814B 0 -#define BIT_MASK_CMU_DLY_LTR_ACT_8814B 0xff -#define BIT_CMU_DLY_LTR_ACT_8814B(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8814B) << BIT_SHIFT_CMU_DLY_LTR_ACT_8814B) -#define BIT_GET_CMU_DLY_LTR_ACT_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8814B) & BIT_MASK_CMU_DLY_LTR_ACT_8814B) - - - -/* 2 REG_H2CQ_TXBD_DESA_8814B */ - -#define BIT_SHIFT_H2CQ_TXBD_DESA_8814B 0 -#define BIT_MASK_H2CQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_H2CQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8814B) << BIT_SHIFT_H2CQ_TXBD_DESA_8814B) -#define BIT_GET_H2CQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8814B) & BIT_MASK_H2CQ_TXBD_DESA_8814B) - - - -/* 2 REG_H2CQ_TXBD_NUM_8814B */ -#define BIT_PCIE_H2CQ_FLAG_8814B BIT(14) - -#define BIT_SHIFT_H2CQ_DESC_MODE_8814B 12 -#define BIT_MASK_H2CQ_DESC_MODE_8814B 0x3 -#define BIT_H2CQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8814B) << BIT_SHIFT_H2CQ_DESC_MODE_8814B) -#define BIT_GET_H2CQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8814B) & BIT_MASK_H2CQ_DESC_MODE_8814B) - - - -#define BIT_SHIFT_H2CQ_DESC_NUM_8814B 0 -#define BIT_MASK_H2CQ_DESC_NUM_8814B 0xfff -#define BIT_H2CQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8814B) << BIT_SHIFT_H2CQ_DESC_NUM_8814B) -#define BIT_GET_H2CQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8814B) & BIT_MASK_H2CQ_DESC_NUM_8814B) - - - -/* 2 REG_H2CQ_TXBD_IDX_8814B */ - -#define BIT_SHIFT_H2CQ_HW_IDX_8814B 16 -#define BIT_MASK_H2CQ_HW_IDX_8814B 0xfff -#define BIT_H2CQ_HW_IDX_8814B(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8814B) << BIT_SHIFT_H2CQ_HW_IDX_8814B) -#define BIT_GET_H2CQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8814B) & BIT_MASK_H2CQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_H2CQ_HOST_IDX_8814B 0 -#define BIT_MASK_H2CQ_HOST_IDX_8814B 0xfff -#define BIT_H2CQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8814B) << BIT_SHIFT_H2CQ_HOST_IDX_8814B) -#define BIT_GET_H2CQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8814B) & BIT_MASK_H2CQ_HOST_IDX_8814B) - - - -/* 2 REG_H2CQ_CSR_8814B[31:0] (H2CQ CONTROL AND STATUS) */ -#define BIT_H2CQ_FULL_8814B BIT(31) -#define BIT_CLR_H2CQ_HOST_IDX_8814B BIT(16) -#define BIT_CLR_H2CQ_HW_IDX_8814B BIT(8) - -/* 2 REG_Q0_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q0_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q0_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q0_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q0_V1_8814B) -#define BIT_GET_QUEUEMACID_Q0_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8814B) & BIT_MASK_QUEUEMACID_Q0_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q0_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q0_V1_8814B 0x3 -#define BIT_QUEUEAC_Q0_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8814B) << BIT_SHIFT_QUEUEAC_Q0_V1_8814B) -#define BIT_GET_QUEUEAC_Q0_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8814B) & BIT_MASK_QUEUEAC_Q0_V1_8814B) - - -#define BIT_TIDEMPTY_Q0_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q0_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q0_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q0_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q0_V2_8814B) -#define BIT_GET_TAIL_PKT_Q0_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8814B) & BIT_MASK_TAIL_PKT_Q0_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q0_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q0_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q0_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q0_V1_8814B) -#define BIT_GET_HEAD_PKT_Q0_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8814B) & BIT_MASK_HEAD_PKT_Q0_V1_8814B) - - - -/* 2 REG_Q1_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q1_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q1_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q1_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q1_V1_8814B) -#define BIT_GET_QUEUEMACID_Q1_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8814B) & BIT_MASK_QUEUEMACID_Q1_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q1_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q1_V1_8814B 0x3 -#define BIT_QUEUEAC_Q1_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8814B) << BIT_SHIFT_QUEUEAC_Q1_V1_8814B) -#define BIT_GET_QUEUEAC_Q1_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8814B) & BIT_MASK_QUEUEAC_Q1_V1_8814B) - - -#define BIT_TIDEMPTY_Q1_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q1_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q1_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q1_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q1_V2_8814B) -#define BIT_GET_TAIL_PKT_Q1_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8814B) & BIT_MASK_TAIL_PKT_Q1_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q1_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q1_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q1_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q1_V1_8814B) -#define BIT_GET_HEAD_PKT_Q1_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8814B) & BIT_MASK_HEAD_PKT_Q1_V1_8814B) - - - -/* 2 REG_Q2_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q2_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q2_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q2_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q2_V1_8814B) -#define BIT_GET_QUEUEMACID_Q2_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8814B) & BIT_MASK_QUEUEMACID_Q2_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q2_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q2_V1_8814B 0x3 -#define BIT_QUEUEAC_Q2_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8814B) << BIT_SHIFT_QUEUEAC_Q2_V1_8814B) -#define BIT_GET_QUEUEAC_Q2_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8814B) & BIT_MASK_QUEUEAC_Q2_V1_8814B) - - -#define BIT_TIDEMPTY_Q2_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q2_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q2_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q2_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q2_V2_8814B) -#define BIT_GET_TAIL_PKT_Q2_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8814B) & BIT_MASK_TAIL_PKT_Q2_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q2_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q2_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q2_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q2_V1_8814B) -#define BIT_GET_HEAD_PKT_Q2_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8814B) & BIT_MASK_HEAD_PKT_Q2_V1_8814B) - - - -/* 2 REG_Q3_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q3_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q3_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q3_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q3_V1_8814B) -#define BIT_GET_QUEUEMACID_Q3_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8814B) & BIT_MASK_QUEUEMACID_Q3_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q3_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q3_V1_8814B 0x3 -#define BIT_QUEUEAC_Q3_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8814B) << BIT_SHIFT_QUEUEAC_Q3_V1_8814B) -#define BIT_GET_QUEUEAC_Q3_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8814B) & BIT_MASK_QUEUEAC_Q3_V1_8814B) - - -#define BIT_TIDEMPTY_Q3_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q3_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q3_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q3_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q3_V2_8814B) -#define BIT_GET_TAIL_PKT_Q3_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8814B) & BIT_MASK_TAIL_PKT_Q3_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q3_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q3_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q3_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q3_V1_8814B) -#define BIT_GET_HEAD_PKT_Q3_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8814B) & BIT_MASK_HEAD_PKT_Q3_V1_8814B) - - - -/* 2 REG_MGQ_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_MGQ_V1_8814B 0x7f -#define BIT_QUEUEMACID_MGQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8814B) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8814B) -#define BIT_GET_QUEUEMACID_MGQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8814B) & BIT_MASK_QUEUEMACID_MGQ_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_MGQ_V1_8814B 23 -#define BIT_MASK_QUEUEAC_MGQ_V1_8814B 0x3 -#define BIT_QUEUEAC_MGQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8814B) << BIT_SHIFT_QUEUEAC_MGQ_V1_8814B) -#define BIT_GET_QUEUEAC_MGQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8814B) & BIT_MASK_QUEUEAC_MGQ_V1_8814B) - - -#define BIT_TIDEMPTY_MGQ_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_MGQ_V2_8814B 0x7ff -#define BIT_TAIL_PKT_MGQ_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8814B) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8814B) -#define BIT_GET_TAIL_PKT_MGQ_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8814B) & BIT_MASK_TAIL_PKT_MGQ_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_MGQ_V1_8814B 0x7ff -#define BIT_HEAD_PKT_MGQ_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8814B) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8814B) -#define BIT_GET_HEAD_PKT_MGQ_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8814B) & BIT_MASK_HEAD_PKT_MGQ_V1_8814B) - - - -/* 2 REG_HIQ_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_HIQ_V1_8814B 0x7f -#define BIT_QUEUEMACID_HIQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8814B) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8814B) -#define BIT_GET_QUEUEMACID_HIQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8814B) & BIT_MASK_QUEUEMACID_HIQ_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_HIQ_V1_8814B 23 -#define BIT_MASK_QUEUEAC_HIQ_V1_8814B 0x3 -#define BIT_QUEUEAC_HIQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8814B) << BIT_SHIFT_QUEUEAC_HIQ_V1_8814B) -#define BIT_GET_QUEUEAC_HIQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8814B) & BIT_MASK_QUEUEAC_HIQ_V1_8814B) - - -#define BIT_TIDEMPTY_HIQ_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_HIQ_V2_8814B 0x7ff -#define BIT_TAIL_PKT_HIQ_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8814B) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8814B) -#define BIT_GET_TAIL_PKT_HIQ_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8814B) & BIT_MASK_TAIL_PKT_HIQ_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_HIQ_V1_8814B 0x7ff -#define BIT_HEAD_PKT_HIQ_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8814B) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8814B) -#define BIT_GET_HEAD_PKT_HIQ_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8814B) & BIT_MASK_HEAD_PKT_HIQ_V1_8814B) - - - -/* 2 REG_BCNQ_INFO_8814B */ - -#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8814B 0 -#define BIT_MASK_BCNQ_HEAD_PG_V1_8814B 0xfff -#define BIT_BCNQ_HEAD_PG_V1_8814B(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8814B) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8814B) -#define BIT_GET_BCNQ_HEAD_PG_V1_8814B(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8814B) & BIT_MASK_BCNQ_HEAD_PG_V1_8814B) - - - -/* 2 REG_TXPKT_EMPTY_8814B */ -#define BIT_BCNQ_EMPTY_8814B BIT(11) -#define BIT_HQQ_EMPTY_8814B BIT(10) -#define BIT_MQQ_EMPTY_8814B BIT(9) -#define BIT_MGQ_CPU_EMPTY_8814B BIT(8) -#define BIT_AC7Q_EMPTY_8814B BIT(7) -#define BIT_AC6Q_EMPTY_8814B BIT(6) -#define BIT_AC5Q_EMPTY_8814B BIT(5) -#define BIT_AC4Q_EMPTY_8814B BIT(4) -#define BIT_AC3Q_EMPTY_8814B BIT(3) -#define BIT_AC2Q_EMPTY_8814B BIT(2) -#define BIT_AC1Q_EMPTY_8814B BIT(1) -#define BIT_AC0Q_EMPTY_8814B BIT(0) - -/* 2 REG_CPU_MGQ_INFO_8814B */ -#define BIT_BCN1_POLL_8814B BIT(30) -#define BIT_CPUMGT_POLL_8814B BIT(29) -#define BIT_BCN_POLL_8814B BIT(28) -#define BIT_CPUMGQ_FW_NUM_V1_8814B BIT(12) - -#define BIT_SHIFT_FW_FREE_TAIL_V1_8814B 0 -#define BIT_MASK_FW_FREE_TAIL_V1_8814B 0xfff -#define BIT_FW_FREE_TAIL_V1_8814B(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8814B) << BIT_SHIFT_FW_FREE_TAIL_V1_8814B) -#define BIT_GET_FW_FREE_TAIL_V1_8814B(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8814B) & BIT_MASK_FW_FREE_TAIL_V1_8814B) - - - -/* 2 REG_FWHW_TXQ_CTRL_8814B */ -#define BIT_RTS_LIMIT_IN_OFDM_8814B BIT(23) -#define BIT_EN_BCNQ_DL_8814B BIT(22) -#define BIT_EN_RD_RESP_NAV_BK_8814B BIT(21) -#define BIT_EN_WR_FREE_TAIL_8814B BIT(20) - -#define BIT_SHIFT_EN_QUEUE_RPT_8814B 8 -#define BIT_MASK_EN_QUEUE_RPT_8814B 0xff -#define BIT_EN_QUEUE_RPT_8814B(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8814B) << BIT_SHIFT_EN_QUEUE_RPT_8814B) -#define BIT_GET_EN_QUEUE_RPT_8814B(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8814B) & BIT_MASK_EN_QUEUE_RPT_8814B) - - -#define BIT_EN_RTY_BK_8814B BIT(7) -#define BIT_EN_USE_INI_RAT_8814B BIT(6) -#define BIT_EN_RTS_NAV_BK_8814B BIT(5) -#define BIT_DIS_SSN_CHECK_8814B BIT(4) -#define BIT_MACID_MATCH_RTS_8814B BIT(3) -#define BIT_EN_BCN_TRXRPT_V1_8814B BIT(2) -#define BIT_R_EN_FTMRPT_8814B BIT(1) -#define BIT_R_BMC_NAV_PROTECT_8814B BIT(0) - -/* 2 REG_DATAFB_SEL_8814B */ -#define BIT__R_EN_RTY_BK_COD_8814B BIT(2) - -#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8814B 0 -#define BIT_MASK__R_DATA_FALLBACK_SEL_8814B 0x3 -#define BIT__R_DATA_FALLBACK_SEL_8814B(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8814B) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8814B) -#define BIT_GET__R_DATA_FALLBACK_SEL_8814B(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8814B) & BIT_MASK__R_DATA_FALLBACK_SEL_8814B) - - - -/* 2 REG_BCNQ_BDNY_V1_8814B */ - -#define BIT_SHIFT_BCNQ_PGBNDY_V1_8814B 0 -#define BIT_MASK_BCNQ_PGBNDY_V1_8814B 0xfff -#define BIT_BCNQ_PGBNDY_V1_8814B(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8814B) << BIT_SHIFT_BCNQ_PGBNDY_V1_8814B) -#define BIT_GET_BCNQ_PGBNDY_V1_8814B(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8814B) & BIT_MASK_BCNQ_PGBNDY_V1_8814B) - - - -/* 2 REG_LIFETIME_EN_8814B */ -#define BIT_BT_INT_CPU_8814B BIT(7) -#define BIT_BT_INT_PTA_8814B BIT(6) -#define BIT_EN_CTRL_RTYBIT_8814B BIT(4) -#define BIT_LIFETIME_BK_EN_8814B BIT(3) -#define BIT_LIFETIME_BE_EN_8814B BIT(2) -#define BIT_LIFETIME_VI_EN_8814B BIT(1) -#define BIT_LIFETIME_VO_EN_8814B BIT(0) - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_SPEC_SIFS_8814B */ - -#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B 8 -#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B 0xff -#define BIT_SPEC_SIFS_OFDM_PTCL_8814B(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) -#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8814B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B) - - - -#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B 0 -#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B 0xff -#define BIT_SPEC_SIFS_CCK_PTCL_8814B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) -#define BIT_GET_SPEC_SIFS_CCK_PTCL_8814B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B) - - - -/* 2 REG_RETRY_LIMIT_8814B */ - -#define BIT_SHIFT_SRL_8814B 8 -#define BIT_MASK_SRL_8814B 0x3f -#define BIT_SRL_8814B(x) (((x) & BIT_MASK_SRL_8814B) << BIT_SHIFT_SRL_8814B) -#define BIT_GET_SRL_8814B(x) (((x) >> BIT_SHIFT_SRL_8814B) & BIT_MASK_SRL_8814B) - - - -#define BIT_SHIFT_LRL_8814B 0 -#define BIT_MASK_LRL_8814B 0x3f -#define BIT_LRL_8814B(x) (((x) & BIT_MASK_LRL_8814B) << BIT_SHIFT_LRL_8814B) -#define BIT_GET_LRL_8814B(x) (((x) >> BIT_SHIFT_LRL_8814B) & BIT_MASK_LRL_8814B) - - - -/* 2 REG_TXBF_CTRL_8814B */ -#define BIT_R_ENABLE_NDPA_8814B BIT(31) -#define BIT_USE_NDPA_PARAMETER_8814B BIT(30) -#define BIT_R_PROP_TXBF_8814B BIT(29) -#define BIT_R_EN_NDPA_INT_8814B BIT(28) -#define BIT_R_TXBF1_80M_8814B BIT(27) -#define BIT_R_TXBF1_40M_8814B BIT(26) -#define BIT_R_TXBF1_20M_8814B BIT(25) - -#define BIT_SHIFT_R_TXBF1_AID_8814B 16 -#define BIT_MASK_R_TXBF1_AID_8814B 0x1ff -#define BIT_R_TXBF1_AID_8814B(x) (((x) & BIT_MASK_R_TXBF1_AID_8814B) << BIT_SHIFT_R_TXBF1_AID_8814B) -#define BIT_GET_R_TXBF1_AID_8814B(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8814B) & BIT_MASK_R_TXBF1_AID_8814B) - - -#define BIT_DIS_NDP_BFEN_8814B BIT(15) -#define BIT_R_TXBCN_NOBLOCK_NDP_8814B BIT(14) -#define BIT_R_TXBF0_80M_8814B BIT(11) -#define BIT_R_TXBF0_40M_8814B BIT(10) -#define BIT_R_TXBF0_20M_8814B BIT(9) - -#define BIT_SHIFT_R_TXBF0_AID_8814B 0 -#define BIT_MASK_R_TXBF0_AID_8814B 0x1ff -#define BIT_R_TXBF0_AID_8814B(x) (((x) & BIT_MASK_R_TXBF0_AID_8814B) << BIT_SHIFT_R_TXBF0_AID_8814B) -#define BIT_GET_R_TXBF0_AID_8814B(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8814B) & BIT_MASK_R_TXBF0_AID_8814B) - - - -/* 2 REG_DARFRC_8814B */ - -#define BIT_SHIFT_DARF_RC8_8814B (56 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC8_8814B 0x1f -#define BIT_DARF_RC8_8814B(x) (((x) & BIT_MASK_DARF_RC8_8814B) << BIT_SHIFT_DARF_RC8_8814B) -#define BIT_GET_DARF_RC8_8814B(x) (((x) >> BIT_SHIFT_DARF_RC8_8814B) & BIT_MASK_DARF_RC8_8814B) - - - -#define BIT_SHIFT_DARF_RC7_8814B (48 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC7_8814B 0x1f -#define BIT_DARF_RC7_8814B(x) (((x) & BIT_MASK_DARF_RC7_8814B) << BIT_SHIFT_DARF_RC7_8814B) -#define BIT_GET_DARF_RC7_8814B(x) (((x) >> BIT_SHIFT_DARF_RC7_8814B) & BIT_MASK_DARF_RC7_8814B) - - - -#define BIT_SHIFT_DARF_RC6_8814B (40 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC6_8814B 0x1f -#define BIT_DARF_RC6_8814B(x) (((x) & BIT_MASK_DARF_RC6_8814B) << BIT_SHIFT_DARF_RC6_8814B) -#define BIT_GET_DARF_RC6_8814B(x) (((x) >> BIT_SHIFT_DARF_RC6_8814B) & BIT_MASK_DARF_RC6_8814B) - - - -#define BIT_SHIFT_DARF_RC5_8814B (32 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC5_8814B 0x1f -#define BIT_DARF_RC5_8814B(x) (((x) & BIT_MASK_DARF_RC5_8814B) << BIT_SHIFT_DARF_RC5_8814B) -#define BIT_GET_DARF_RC5_8814B(x) (((x) >> BIT_SHIFT_DARF_RC5_8814B) & BIT_MASK_DARF_RC5_8814B) - - - -#define BIT_SHIFT_DARF_RC4_8814B 24 -#define BIT_MASK_DARF_RC4_8814B 0x1f -#define BIT_DARF_RC4_8814B(x) (((x) & BIT_MASK_DARF_RC4_8814B) << BIT_SHIFT_DARF_RC4_8814B) -#define BIT_GET_DARF_RC4_8814B(x) (((x) >> BIT_SHIFT_DARF_RC4_8814B) & BIT_MASK_DARF_RC4_8814B) - - - -#define BIT_SHIFT_DARF_RC3_8814B 16 -#define BIT_MASK_DARF_RC3_8814B 0x1f -#define BIT_DARF_RC3_8814B(x) (((x) & BIT_MASK_DARF_RC3_8814B) << BIT_SHIFT_DARF_RC3_8814B) -#define BIT_GET_DARF_RC3_8814B(x) (((x) >> BIT_SHIFT_DARF_RC3_8814B) & BIT_MASK_DARF_RC3_8814B) - - - -#define BIT_SHIFT_DARF_RC2_8814B 8 -#define BIT_MASK_DARF_RC2_8814B 0x1f -#define BIT_DARF_RC2_8814B(x) (((x) & BIT_MASK_DARF_RC2_8814B) << BIT_SHIFT_DARF_RC2_8814B) -#define BIT_GET_DARF_RC2_8814B(x) (((x) >> BIT_SHIFT_DARF_RC2_8814B) & BIT_MASK_DARF_RC2_8814B) - - - -#define BIT_SHIFT_DARF_RC1_8814B 0 -#define BIT_MASK_DARF_RC1_8814B 0x1f -#define BIT_DARF_RC1_8814B(x) (((x) & BIT_MASK_DARF_RC1_8814B) << BIT_SHIFT_DARF_RC1_8814B) -#define BIT_GET_DARF_RC1_8814B(x) (((x) >> BIT_SHIFT_DARF_RC1_8814B) & BIT_MASK_DARF_RC1_8814B) - - - -/* 2 REG_RARFRC_8814B */ - -#define BIT_SHIFT_RARF_RC8_8814B (56 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC8_8814B 0x1f -#define BIT_RARF_RC8_8814B(x) (((x) & BIT_MASK_RARF_RC8_8814B) << BIT_SHIFT_RARF_RC8_8814B) -#define BIT_GET_RARF_RC8_8814B(x) (((x) >> BIT_SHIFT_RARF_RC8_8814B) & BIT_MASK_RARF_RC8_8814B) - - - -#define BIT_SHIFT_RARF_RC7_8814B (48 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC7_8814B 0x1f -#define BIT_RARF_RC7_8814B(x) (((x) & BIT_MASK_RARF_RC7_8814B) << BIT_SHIFT_RARF_RC7_8814B) -#define BIT_GET_RARF_RC7_8814B(x) (((x) >> BIT_SHIFT_RARF_RC7_8814B) & BIT_MASK_RARF_RC7_8814B) - - - -#define BIT_SHIFT_RARF_RC6_8814B (40 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC6_8814B 0x1f -#define BIT_RARF_RC6_8814B(x) (((x) & BIT_MASK_RARF_RC6_8814B) << BIT_SHIFT_RARF_RC6_8814B) -#define BIT_GET_RARF_RC6_8814B(x) (((x) >> BIT_SHIFT_RARF_RC6_8814B) & BIT_MASK_RARF_RC6_8814B) - - - -#define BIT_SHIFT_RARF_RC5_8814B (32 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC5_8814B 0x1f -#define BIT_RARF_RC5_8814B(x) (((x) & BIT_MASK_RARF_RC5_8814B) << BIT_SHIFT_RARF_RC5_8814B) -#define BIT_GET_RARF_RC5_8814B(x) (((x) >> BIT_SHIFT_RARF_RC5_8814B) & BIT_MASK_RARF_RC5_8814B) - - - -#define BIT_SHIFT_RARF_RC4_8814B 24 -#define BIT_MASK_RARF_RC4_8814B 0x1f -#define BIT_RARF_RC4_8814B(x) (((x) & BIT_MASK_RARF_RC4_8814B) << BIT_SHIFT_RARF_RC4_8814B) -#define BIT_GET_RARF_RC4_8814B(x) (((x) >> BIT_SHIFT_RARF_RC4_8814B) & BIT_MASK_RARF_RC4_8814B) - - - -#define BIT_SHIFT_RARF_RC3_8814B 16 -#define BIT_MASK_RARF_RC3_8814B 0x1f -#define BIT_RARF_RC3_8814B(x) (((x) & BIT_MASK_RARF_RC3_8814B) << BIT_SHIFT_RARF_RC3_8814B) -#define BIT_GET_RARF_RC3_8814B(x) (((x) >> BIT_SHIFT_RARF_RC3_8814B) & BIT_MASK_RARF_RC3_8814B) - - - -#define BIT_SHIFT_RARF_RC2_8814B 8 -#define BIT_MASK_RARF_RC2_8814B 0x1f -#define BIT_RARF_RC2_8814B(x) (((x) & BIT_MASK_RARF_RC2_8814B) << BIT_SHIFT_RARF_RC2_8814B) -#define BIT_GET_RARF_RC2_8814B(x) (((x) >> BIT_SHIFT_RARF_RC2_8814B) & BIT_MASK_RARF_RC2_8814B) - - - -#define BIT_SHIFT_RARF_RC1_8814B 0 -#define BIT_MASK_RARF_RC1_8814B 0x1f -#define BIT_RARF_RC1_8814B(x) (((x) & BIT_MASK_RARF_RC1_8814B) << BIT_SHIFT_RARF_RC1_8814B) -#define BIT_GET_RARF_RC1_8814B(x) (((x) >> BIT_SHIFT_RARF_RC1_8814B) & BIT_MASK_RARF_RC1_8814B) - - - -/* 2 REG_RRSR_8814B */ - -#define BIT_SHIFT_RRSR_RSC_8814B 21 -#define BIT_MASK_RRSR_RSC_8814B 0x3 -#define BIT_RRSR_RSC_8814B(x) (((x) & BIT_MASK_RRSR_RSC_8814B) << BIT_SHIFT_RRSR_RSC_8814B) -#define BIT_GET_RRSR_RSC_8814B(x) (((x) >> BIT_SHIFT_RRSR_RSC_8814B) & BIT_MASK_RRSR_RSC_8814B) - - -#define BIT_RRSR_BW_8814B BIT(20) - -#define BIT_SHIFT_RRSC_BITMAP_8814B 0 -#define BIT_MASK_RRSC_BITMAP_8814B 0xfffff -#define BIT_RRSC_BITMAP_8814B(x) (((x) & BIT_MASK_RRSC_BITMAP_8814B) << BIT_SHIFT_RRSC_BITMAP_8814B) -#define BIT_GET_RRSC_BITMAP_8814B(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8814B) & BIT_MASK_RRSC_BITMAP_8814B) - - - -/* 2 REG_ARFR0_8814B */ - -#define BIT_SHIFT_ARFR0_V1_8814B 0 -#define BIT_MASK_ARFR0_V1_8814B 0xffffffffffffffffL -#define BIT_ARFR0_V1_8814B(x) (((x) & BIT_MASK_ARFR0_V1_8814B) << BIT_SHIFT_ARFR0_V1_8814B) -#define BIT_GET_ARFR0_V1_8814B(x) (((x) >> BIT_SHIFT_ARFR0_V1_8814B) & BIT_MASK_ARFR0_V1_8814B) - - - -/* 2 REG_ARFR1_V1_8814B */ - -#define BIT_SHIFT_ARFR1_V1_8814B 0 -#define BIT_MASK_ARFR1_V1_8814B 0xffffffffffffffffL -#define BIT_ARFR1_V1_8814B(x) (((x) & BIT_MASK_ARFR1_V1_8814B) << BIT_SHIFT_ARFR1_V1_8814B) -#define BIT_GET_ARFR1_V1_8814B(x) (((x) >> BIT_SHIFT_ARFR1_V1_8814B) & BIT_MASK_ARFR1_V1_8814B) - - - -/* 2 REG_CCK_CHECK_8814B */ -#define BIT_CHECK_CCK_EN_8814B BIT(7) -#define BIT_EN_BCN_PKT_REL_8814B BIT(6) -#define BIT_BCN_PORT_SEL_8814B BIT(5) -#define BIT_MOREDATA_BYPASS_8814B BIT(4) -#define BIT_EN_CLR_CMD_REL_BCN_PKT_8814B BIT(3) -#define BIT_R_EN_SET_MOREDATA_8814B BIT(2) -#define BIT__R_DIS_CLEAR_MACID_RELEASE_8814B BIT(1) -#define BIT__R_MACID_RELEASE_EN_8814B BIT(0) - -/* 2 REG_AMPDU_MAX_TIME_V1_8814B */ - -#define BIT_SHIFT_AMPDU_MAX_TIME_8814B 0 -#define BIT_MASK_AMPDU_MAX_TIME_8814B 0xff -#define BIT_AMPDU_MAX_TIME_8814B(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8814B) << BIT_SHIFT_AMPDU_MAX_TIME_8814B) -#define BIT_GET_AMPDU_MAX_TIME_8814B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8814B) & BIT_MASK_AMPDU_MAX_TIME_8814B) - - - -/* 2 REG_BCNQ1_BDNY_V1_8814B */ - -#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8814B 0 -#define BIT_MASK_BCNQ1_PGBNDY_V1_8814B 0xfff -#define BIT_BCNQ1_PGBNDY_V1_8814B(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8814B) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8814B) -#define BIT_GET_BCNQ1_PGBNDY_V1_8814B(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8814B) & BIT_MASK_BCNQ1_PGBNDY_V1_8814B) - - - -/* 2 REG_AMPDU_MAX_LENGTH_8814B */ - -#define BIT_SHIFT_AMPDU_MAX_LENGTH_8814B 0 -#define BIT_MASK_AMPDU_MAX_LENGTH_8814B 0xffffffffL -#define BIT_AMPDU_MAX_LENGTH_8814B(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8814B) << BIT_SHIFT_AMPDU_MAX_LENGTH_8814B) -#define BIT_GET_AMPDU_MAX_LENGTH_8814B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8814B) & BIT_MASK_AMPDU_MAX_LENGTH_8814B) - - - -/* 2 REG_ACQ_STOP_8814B */ -#define BIT_AC7Q_STOP_8814B BIT(7) -#define BIT_AC6Q_STOP_8814B BIT(6) -#define BIT_AC5Q_STOP_8814B BIT(5) -#define BIT_AC4Q_STOP_8814B BIT(4) -#define BIT_AC3Q_STOP_8814B BIT(3) -#define BIT_AC2Q_STOP_8814B BIT(2) -#define BIT_AC1Q_STOP_8814B BIT(1) -#define BIT_AC0Q_STOP_8814B BIT(0) - -/* 2 REG_NDPA_RATE_8814B */ - -#define BIT_SHIFT_R_NDPA_RATE_V1_8814B 0 -#define BIT_MASK_R_NDPA_RATE_V1_8814B 0xff -#define BIT_R_NDPA_RATE_V1_8814B(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8814B) << BIT_SHIFT_R_NDPA_RATE_V1_8814B) -#define BIT_GET_R_NDPA_RATE_V1_8814B(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8814B) & BIT_MASK_R_NDPA_RATE_V1_8814B) - - - -/* 2 REG_TX_HANG_CTRL_8814B */ -#define BIT_R_EN_GNT_BT_AWAKE_8814B BIT(3) -#define BIT_EN_EOF_V1_8814B BIT(2) -#define BIT_DIS_OQT_BLOCK_8814B BIT(1) -#define BIT_SEARCH_QUEUE_EN_8814B BIT(0) - -/* 2 REG_NDPA_OPT_CTRL_8814B */ -#define BIT_R_DIS_MACID_RELEASE_RTY_8814B BIT(5) - -#define BIT_SHIFT_BW_SIGTA_8814B 3 -#define BIT_MASK_BW_SIGTA_8814B 0x3 -#define BIT_BW_SIGTA_8814B(x) (((x) & BIT_MASK_BW_SIGTA_8814B) << BIT_SHIFT_BW_SIGTA_8814B) -#define BIT_GET_BW_SIGTA_8814B(x) (((x) >> BIT_SHIFT_BW_SIGTA_8814B) & BIT_MASK_BW_SIGTA_8814B) - - -#define BIT_EN_BAR_SIGTA_8814B BIT(2) - -#define BIT_SHIFT_R_NDPA_BW_8814B 0 -#define BIT_MASK_R_NDPA_BW_8814B 0x3 -#define BIT_R_NDPA_BW_8814B(x) (((x) & BIT_MASK_R_NDPA_BW_8814B) << BIT_SHIFT_R_NDPA_BW_8814B) -#define BIT_GET_R_NDPA_BW_8814B(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8814B) & BIT_MASK_R_NDPA_BW_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_RD_RESP_PKT_TH_8814B */ - -#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B 0 -#define BIT_MASK_RD_RESP_PKT_TH_V1_8814B 0x3f -#define BIT_RD_RESP_PKT_TH_V1_8814B(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8814B) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) -#define BIT_GET_RD_RESP_PKT_TH_V1_8814B(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) & BIT_MASK_RD_RESP_PKT_TH_V1_8814B) - - - -/* 2 REG_CMDQ_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_CMDQ_V1_8814B 0x7f -#define BIT_QUEUEMACID_CMDQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8814B) << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8814B) -#define BIT_GET_QUEUEMACID_CMDQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8814B) & BIT_MASK_QUEUEMACID_CMDQ_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8814B 23 -#define BIT_MASK_QUEUEAC_CMDQ_V1_8814B 0x3 -#define BIT_QUEUEAC_CMDQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8814B) << BIT_SHIFT_QUEUEAC_CMDQ_V1_8814B) -#define BIT_GET_QUEUEAC_CMDQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8814B) & BIT_MASK_QUEUEAC_CMDQ_V1_8814B) - - -#define BIT_TIDEMPTY_CMDQ_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_CMDQ_V2_8814B 0x7ff -#define BIT_TAIL_PKT_CMDQ_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8814B) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8814B) -#define BIT_GET_TAIL_PKT_CMDQ_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8814B) & BIT_MASK_TAIL_PKT_CMDQ_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_CMDQ_V1_8814B 0x7ff -#define BIT_HEAD_PKT_CMDQ_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8814B) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8814B) -#define BIT_GET_HEAD_PKT_CMDQ_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8814B) & BIT_MASK_HEAD_PKT_CMDQ_V1_8814B) - - - -/* 2 REG_Q4_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q4_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q4_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q4_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q4_V1_8814B) -#define BIT_GET_QUEUEMACID_Q4_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8814B) & BIT_MASK_QUEUEMACID_Q4_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q4_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q4_V1_8814B 0x3 -#define BIT_QUEUEAC_Q4_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8814B) << BIT_SHIFT_QUEUEAC_Q4_V1_8814B) -#define BIT_GET_QUEUEAC_Q4_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8814B) & BIT_MASK_QUEUEAC_Q4_V1_8814B) - - -#define BIT_TIDEMPTY_Q4_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q4_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q4_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q4_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q4_V2_8814B) -#define BIT_GET_TAIL_PKT_Q4_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8814B) & BIT_MASK_TAIL_PKT_Q4_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q4_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q4_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q4_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q4_V1_8814B) -#define BIT_GET_HEAD_PKT_Q4_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8814B) & BIT_MASK_HEAD_PKT_Q4_V1_8814B) - - - -/* 2 REG_Q5_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q5_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q5_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q5_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q5_V1_8814B) -#define BIT_GET_QUEUEMACID_Q5_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8814B) & BIT_MASK_QUEUEMACID_Q5_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q5_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q5_V1_8814B 0x3 -#define BIT_QUEUEAC_Q5_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8814B) << BIT_SHIFT_QUEUEAC_Q5_V1_8814B) -#define BIT_GET_QUEUEAC_Q5_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8814B) & BIT_MASK_QUEUEAC_Q5_V1_8814B) - - -#define BIT_TIDEMPTY_Q5_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q5_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q5_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q5_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q5_V2_8814B) -#define BIT_GET_TAIL_PKT_Q5_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8814B) & BIT_MASK_TAIL_PKT_Q5_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q5_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q5_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q5_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q5_V1_8814B) -#define BIT_GET_HEAD_PKT_Q5_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8814B) & BIT_MASK_HEAD_PKT_Q5_V1_8814B) - - - -/* 2 REG_Q6_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q6_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q6_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q6_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q6_V1_8814B) -#define BIT_GET_QUEUEMACID_Q6_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8814B) & BIT_MASK_QUEUEMACID_Q6_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q6_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q6_V1_8814B 0x3 -#define BIT_QUEUEAC_Q6_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8814B) << BIT_SHIFT_QUEUEAC_Q6_V1_8814B) -#define BIT_GET_QUEUEAC_Q6_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8814B) & BIT_MASK_QUEUEAC_Q6_V1_8814B) - - -#define BIT_TIDEMPTY_Q6_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q6_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q6_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q6_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q6_V2_8814B) -#define BIT_GET_TAIL_PKT_Q6_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8814B) & BIT_MASK_TAIL_PKT_Q6_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q6_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q6_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q6_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q6_V1_8814B) -#define BIT_GET_HEAD_PKT_Q6_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8814B) & BIT_MASK_HEAD_PKT_Q6_V1_8814B) - - - -/* 2 REG_Q7_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q7_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q7_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q7_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q7_V1_8814B) -#define BIT_GET_QUEUEMACID_Q7_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8814B) & BIT_MASK_QUEUEMACID_Q7_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q7_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q7_V1_8814B 0x3 -#define BIT_QUEUEAC_Q7_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8814B) << BIT_SHIFT_QUEUEAC_Q7_V1_8814B) -#define BIT_GET_QUEUEAC_Q7_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8814B) & BIT_MASK_QUEUEAC_Q7_V1_8814B) - - -#define BIT_TIDEMPTY_Q7_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q7_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q7_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q7_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q7_V2_8814B) -#define BIT_GET_TAIL_PKT_Q7_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8814B) & BIT_MASK_TAIL_PKT_Q7_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q7_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q7_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q7_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q7_V1_8814B) -#define BIT_GET_HEAD_PKT_Q7_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8814B) & BIT_MASK_HEAD_PKT_Q7_V1_8814B) - - - -/* 2 REG_WMAC_LBK_BUF_HD_V1_8814B */ - -#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B 0 -#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B 0xfff -#define BIT_WMAC_LBK_BUF_HEAD_V1_8814B(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) -#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8814B(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B) - - - -/* 2 REG_MGQ_BDNY_V1_8814B */ - -#define BIT_SHIFT_MGQ_PGBNDY_V1_8814B 0 -#define BIT_MASK_MGQ_PGBNDY_V1_8814B 0xfff -#define BIT_MGQ_PGBNDY_V1_8814B(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8814B) << BIT_SHIFT_MGQ_PGBNDY_V1_8814B) -#define BIT_GET_MGQ_PGBNDY_V1_8814B(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8814B) & BIT_MASK_MGQ_PGBNDY_V1_8814B) - - - -/* 2 REG_TXRPT_CTRL_8814B */ - -#define BIT_SHIFT_TRXRPT_TIMER_TH_8814B 24 -#define BIT_MASK_TRXRPT_TIMER_TH_8814B 0xff -#define BIT_TRXRPT_TIMER_TH_8814B(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8814B) << BIT_SHIFT_TRXRPT_TIMER_TH_8814B) -#define BIT_GET_TRXRPT_TIMER_TH_8814B(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8814B) & BIT_MASK_TRXRPT_TIMER_TH_8814B) - - - -#define BIT_SHIFT_TRXRPT_LEN_TH_8814B 16 -#define BIT_MASK_TRXRPT_LEN_TH_8814B 0xff -#define BIT_TRXRPT_LEN_TH_8814B(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8814B) << BIT_SHIFT_TRXRPT_LEN_TH_8814B) -#define BIT_GET_TRXRPT_LEN_TH_8814B(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8814B) & BIT_MASK_TRXRPT_LEN_TH_8814B) - - - -#define BIT_SHIFT_TRXRPT_READ_PTR_8814B 8 -#define BIT_MASK_TRXRPT_READ_PTR_8814B 0xff -#define BIT_TRXRPT_READ_PTR_8814B(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8814B) << BIT_SHIFT_TRXRPT_READ_PTR_8814B) -#define BIT_GET_TRXRPT_READ_PTR_8814B(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8814B) & BIT_MASK_TRXRPT_READ_PTR_8814B) - - - -#define BIT_SHIFT_TRXRPT_WRITE_PTR_8814B 0 -#define BIT_MASK_TRXRPT_WRITE_PTR_8814B 0xff -#define BIT_TRXRPT_WRITE_PTR_8814B(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8814B) << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) -#define BIT_GET_TRXRPT_WRITE_PTR_8814B(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) & BIT_MASK_TRXRPT_WRITE_PTR_8814B) - - - -/* 2 REG_INIRTS_RATE_SEL_8814B */ -#define BIT_LEAG_RTS_BW_DUP_8814B BIT(5) - -/* 2 REG_BASIC_CFEND_RATE_8814B */ - -#define BIT_SHIFT_BASIC_CFEND_RATE_8814B 0 -#define BIT_MASK_BASIC_CFEND_RATE_8814B 0x1f -#define BIT_BASIC_CFEND_RATE_8814B(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8814B) << BIT_SHIFT_BASIC_CFEND_RATE_8814B) -#define BIT_GET_BASIC_CFEND_RATE_8814B(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8814B) & BIT_MASK_BASIC_CFEND_RATE_8814B) - - - -/* 2 REG_STBC_CFEND_RATE_8814B */ - -#define BIT_SHIFT_STBC_CFEND_RATE_8814B 0 -#define BIT_MASK_STBC_CFEND_RATE_8814B 0x1f -#define BIT_STBC_CFEND_RATE_8814B(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8814B) << BIT_SHIFT_STBC_CFEND_RATE_8814B) -#define BIT_GET_STBC_CFEND_RATE_8814B(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8814B) & BIT_MASK_STBC_CFEND_RATE_8814B) - - - -/* 2 REG_DATA_SC_8814B */ - -#define BIT_SHIFT_TXSC_40M_8814B 4 -#define BIT_MASK_TXSC_40M_8814B 0xf -#define BIT_TXSC_40M_8814B(x) (((x) & BIT_MASK_TXSC_40M_8814B) << BIT_SHIFT_TXSC_40M_8814B) -#define BIT_GET_TXSC_40M_8814B(x) (((x) >> BIT_SHIFT_TXSC_40M_8814B) & BIT_MASK_TXSC_40M_8814B) - - - -#define BIT_SHIFT_TXSC_20M_8814B 0 -#define BIT_MASK_TXSC_20M_8814B 0xf -#define BIT_TXSC_20M_8814B(x) (((x) & BIT_MASK_TXSC_20M_8814B) << BIT_SHIFT_TXSC_20M_8814B) -#define BIT_GET_TXSC_20M_8814B(x) (((x) >> BIT_SHIFT_TXSC_20M_8814B) & BIT_MASK_TXSC_20M_8814B) - - - -/* 2 REG_MACID_SLEEP3_8814B */ - -#define BIT_SHIFT_MACID127_96_PKTSLEEP_8814B 0 -#define BIT_MASK_MACID127_96_PKTSLEEP_8814B 0xffffffffL -#define BIT_MACID127_96_PKTSLEEP_8814B(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8814B) << BIT_SHIFT_MACID127_96_PKTSLEEP_8814B) -#define BIT_GET_MACID127_96_PKTSLEEP_8814B(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8814B) & BIT_MASK_MACID127_96_PKTSLEEP_8814B) - - - -/* 2 REG_MACID_SLEEP1_8814B */ - -#define BIT_SHIFT_MACID63_32_PKTSLEEP_8814B 0 -#define BIT_MASK_MACID63_32_PKTSLEEP_8814B 0xffffffffL -#define BIT_MACID63_32_PKTSLEEP_8814B(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8814B) << BIT_SHIFT_MACID63_32_PKTSLEEP_8814B) -#define BIT_GET_MACID63_32_PKTSLEEP_8814B(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8814B) & BIT_MASK_MACID63_32_PKTSLEEP_8814B) - - - -/* 2 REG_ARFR2_V1_8814B */ - -#define BIT_SHIFT_ARFR2_V1_8814B 0 -#define BIT_MASK_ARFR2_V1_8814B 0xffffffffffffffffL -#define BIT_ARFR2_V1_8814B(x) (((x) & BIT_MASK_ARFR2_V1_8814B) << BIT_SHIFT_ARFR2_V1_8814B) -#define BIT_GET_ARFR2_V1_8814B(x) (((x) >> BIT_SHIFT_ARFR2_V1_8814B) & BIT_MASK_ARFR2_V1_8814B) - - - -/* 2 REG_ARFR3_V1_8814B */ - -#define BIT_SHIFT_ARFR3_V1_8814B 0 -#define BIT_MASK_ARFR3_V1_8814B 0xffffffffffffffffL -#define BIT_ARFR3_V1_8814B(x) (((x) & BIT_MASK_ARFR3_V1_8814B) << BIT_SHIFT_ARFR3_V1_8814B) -#define BIT_GET_ARFR3_V1_8814B(x) (((x) >> BIT_SHIFT_ARFR3_V1_8814B) & BIT_MASK_ARFR3_V1_8814B) - - - -/* 2 REG_ARFR4_8814B */ - -#define BIT_SHIFT_ARFR4_8814B 0 -#define BIT_MASK_ARFR4_8814B 0xffffffffffffffffL -#define BIT_ARFR4_8814B(x) (((x) & BIT_MASK_ARFR4_8814B) << BIT_SHIFT_ARFR4_8814B) -#define BIT_GET_ARFR4_8814B(x) (((x) >> BIT_SHIFT_ARFR4_8814B) & BIT_MASK_ARFR4_8814B) - - - -/* 2 REG_ARFR5_8814B */ - -#define BIT_SHIFT_ARFR5_8814B 0 -#define BIT_MASK_ARFR5_8814B 0xffffffffffffffffL -#define BIT_ARFR5_8814B(x) (((x) & BIT_MASK_ARFR5_8814B) << BIT_SHIFT_ARFR5_8814B) -#define BIT_GET_ARFR5_8814B(x) (((x) >> BIT_SHIFT_ARFR5_8814B) & BIT_MASK_ARFR5_8814B) - - - -/* 2 REG_TXRPT_START_OFFSET_8814B */ - -#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8814B 24 -#define BIT_MASK_R_MUTAB_TXRPT_OFFSET_8814B 0xff -#define BIT_R_MUTAB_TXRPT_OFFSET_8814B(x) (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8814B) << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8814B) -#define BIT_GET_R_MUTAB_TXRPT_OFFSET_8814B(x) (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8814B) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8814B) - - -#define BIT__R_RPTFIFO_1K_8814B BIT(16) - -#define BIT_SHIFT_MACID_CTRL_OFFSET_8814B 8 -#define BIT_MASK_MACID_CTRL_OFFSET_8814B 0xff -#define BIT_MACID_CTRL_OFFSET_8814B(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8814B) << BIT_SHIFT_MACID_CTRL_OFFSET_8814B) -#define BIT_GET_MACID_CTRL_OFFSET_8814B(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8814B) & BIT_MASK_MACID_CTRL_OFFSET_8814B) - - - -#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8814B 0 -#define BIT_MASK_AMPDU_TXRPT_OFFSET_8814B 0xff -#define BIT_AMPDU_TXRPT_OFFSET_8814B(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8814B) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8814B) -#define BIT_GET_AMPDU_TXRPT_OFFSET_8814B(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8814B) & BIT_MASK_AMPDU_TXRPT_OFFSET_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_POWER_STAGE1_8814B */ -#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8814B BIT(31) -#define BIT_PTA_WL_PRI_MASK_BCNQ_8814B BIT(30) -#define BIT_PTA_WL_PRI_MASK_HIQ_8814B BIT(29) -#define BIT_PTA_WL_PRI_MASK_MGQ_8814B BIT(28) -#define BIT_PTA_WL_PRI_MASK_BK_8814B BIT(27) -#define BIT_PTA_WL_PRI_MASK_BE_8814B BIT(26) -#define BIT_PTA_WL_PRI_MASK_VI_8814B BIT(25) -#define BIT_PTA_WL_PRI_MASK_VO_8814B BIT(24) - -#define BIT_SHIFT_POWER_STAGE1_8814B 0 -#define BIT_MASK_POWER_STAGE1_8814B 0xffffff -#define BIT_POWER_STAGE1_8814B(x) (((x) & BIT_MASK_POWER_STAGE1_8814B) << BIT_SHIFT_POWER_STAGE1_8814B) -#define BIT_GET_POWER_STAGE1_8814B(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8814B) & BIT_MASK_POWER_STAGE1_8814B) - - - -/* 2 REG_POWER_STAGE2_8814B */ -#define BIT__R_CTRL_PKT_POW_ADJ_8814B BIT(24) - -#define BIT_SHIFT_POWER_STAGE2_8814B 0 -#define BIT_MASK_POWER_STAGE2_8814B 0xffffff -#define BIT_POWER_STAGE2_8814B(x) (((x) & BIT_MASK_POWER_STAGE2_8814B) << BIT_SHIFT_POWER_STAGE2_8814B) -#define BIT_GET_POWER_STAGE2_8814B(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8814B) & BIT_MASK_POWER_STAGE2_8814B) - - - -/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8814B */ - -#define BIT_SHIFT_PAD_NUM_THRES_8814B 24 -#define BIT_MASK_PAD_NUM_THRES_8814B 0x3f -#define BIT_PAD_NUM_THRES_8814B(x) (((x) & BIT_MASK_PAD_NUM_THRES_8814B) << BIT_SHIFT_PAD_NUM_THRES_8814B) -#define BIT_GET_PAD_NUM_THRES_8814B(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8814B) & BIT_MASK_PAD_NUM_THRES_8814B) - - -#define BIT_R_DMA_THIS_QUEUE_BK_8814B BIT(23) -#define BIT_R_DMA_THIS_QUEUE_BE_8814B BIT(22) -#define BIT_R_DMA_THIS_QUEUE_VI_8814B BIT(21) -#define BIT_R_DMA_THIS_QUEUE_VO_8814B BIT(20) - -#define BIT_SHIFT_R_TOTAL_LEN_TH_8814B 8 -#define BIT_MASK_R_TOTAL_LEN_TH_8814B 0xfff -#define BIT_R_TOTAL_LEN_TH_8814B(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8814B) << BIT_SHIFT_R_TOTAL_LEN_TH_8814B) -#define BIT_GET_R_TOTAL_LEN_TH_8814B(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8814B) & BIT_MASK_R_TOTAL_LEN_TH_8814B) - - -#define BIT_EN_NEW_EARLY_8814B BIT(7) -#define BIT_PRE_TX_CMD_8814B BIT(6) - -#define BIT_SHIFT_NUM_SCL_EN_8814B 4 -#define BIT_MASK_NUM_SCL_EN_8814B 0x3 -#define BIT_NUM_SCL_EN_8814B(x) (((x) & BIT_MASK_NUM_SCL_EN_8814B) << BIT_SHIFT_NUM_SCL_EN_8814B) -#define BIT_GET_NUM_SCL_EN_8814B(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8814B) & BIT_MASK_NUM_SCL_EN_8814B) - - -#define BIT_BK_EN_8814B BIT(3) -#define BIT_BE_EN_8814B BIT(2) -#define BIT_VI_EN_8814B BIT(1) -#define BIT_VO_EN_8814B BIT(0) - -/* 2 REG_PKT_LIFE_TIME_8814B */ - -#define BIT_SHIFT_PKT_LIFTIME_BEBK_8814B 16 -#define BIT_MASK_PKT_LIFTIME_BEBK_8814B 0xffff -#define BIT_PKT_LIFTIME_BEBK_8814B(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8814B) << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) -#define BIT_GET_PKT_LIFTIME_BEBK_8814B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) & BIT_MASK_PKT_LIFTIME_BEBK_8814B) - - - -#define BIT_SHIFT_PKT_LIFTIME_VOVI_8814B 0 -#define BIT_MASK_PKT_LIFTIME_VOVI_8814B 0xffff -#define BIT_PKT_LIFTIME_VOVI_8814B(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8814B) << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) -#define BIT_GET_PKT_LIFTIME_VOVI_8814B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) & BIT_MASK_PKT_LIFTIME_VOVI_8814B) - - - -/* 2 REG_STBC_SETTING_8814B */ - -#define BIT_SHIFT_CDEND_TXTIME_L_8814B 4 -#define BIT_MASK_CDEND_TXTIME_L_8814B 0xf -#define BIT_CDEND_TXTIME_L_8814B(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8814B) << BIT_SHIFT_CDEND_TXTIME_L_8814B) -#define BIT_GET_CDEND_TXTIME_L_8814B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8814B) & BIT_MASK_CDEND_TXTIME_L_8814B) - - - -#define BIT_SHIFT_NESS_8814B 2 -#define BIT_MASK_NESS_8814B 0x3 -#define BIT_NESS_8814B(x) (((x) & BIT_MASK_NESS_8814B) << BIT_SHIFT_NESS_8814B) -#define BIT_GET_NESS_8814B(x) (((x) >> BIT_SHIFT_NESS_8814B) & BIT_MASK_NESS_8814B) - - - -#define BIT_SHIFT_STBC_CFEND_8814B 0 -#define BIT_MASK_STBC_CFEND_8814B 0x3 -#define BIT_STBC_CFEND_8814B(x) (((x) & BIT_MASK_STBC_CFEND_8814B) << BIT_SHIFT_STBC_CFEND_8814B) -#define BIT_GET_STBC_CFEND_8814B(x) (((x) >> BIT_SHIFT_STBC_CFEND_8814B) & BIT_MASK_STBC_CFEND_8814B) - - - -/* 2 REG_STBC_SETTING2_8814B */ - -#define BIT_SHIFT_CDEND_TXTIME_H_8814B 0 -#define BIT_MASK_CDEND_TXTIME_H_8814B 0x1f -#define BIT_CDEND_TXTIME_H_8814B(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8814B) << BIT_SHIFT_CDEND_TXTIME_H_8814B) -#define BIT_GET_CDEND_TXTIME_H_8814B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8814B) & BIT_MASK_CDEND_TXTIME_H_8814B) - - - -/* 2 REG_QUEUE_CTRL_8814B */ -#define BIT_PTA_EDCCA_EN_8814B BIT(5) -#define BIT_PTA_WL_TX_EN_8814B BIT(4) -#define BIT_R_USE_DATA_BW_8814B BIT(3) -#define BIT_TRI_PKT_INT_MODE1_8814B BIT(2) -#define BIT_TRI_PKT_INT_MODE0_8814B BIT(1) -#define BIT_ACQ_MODE_SEL_8814B BIT(0) - -/* 2 REG_SINGLE_AMPDU_CTRL_8814B */ -#define BIT_EN_SINGLE_APMDU_8814B BIT(7) - -/* 2 REG_PROT_MODE_CTRL_8814B */ - -#define BIT_SHIFT_RTS_MAX_AGG_NUM_8814B 24 -#define BIT_MASK_RTS_MAX_AGG_NUM_8814B 0x3f -#define BIT_RTS_MAX_AGG_NUM_8814B(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8814B) << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) -#define BIT_GET_RTS_MAX_AGG_NUM_8814B(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) & BIT_MASK_RTS_MAX_AGG_NUM_8814B) - - - -#define BIT_SHIFT_MAX_AGG_NUM_8814B 16 -#define BIT_MASK_MAX_AGG_NUM_8814B 0x3f -#define BIT_MAX_AGG_NUM_8814B(x) (((x) & BIT_MASK_MAX_AGG_NUM_8814B) << BIT_SHIFT_MAX_AGG_NUM_8814B) -#define BIT_GET_MAX_AGG_NUM_8814B(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8814B) & BIT_MASK_MAX_AGG_NUM_8814B) - - - -#define BIT_SHIFT_RTS_TXTIME_TH_8814B 8 -#define BIT_MASK_RTS_TXTIME_TH_8814B 0xff -#define BIT_RTS_TXTIME_TH_8814B(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8814B) << BIT_SHIFT_RTS_TXTIME_TH_8814B) -#define BIT_GET_RTS_TXTIME_TH_8814B(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8814B) & BIT_MASK_RTS_TXTIME_TH_8814B) - - - -#define BIT_SHIFT_RTS_LEN_TH_8814B 0 -#define BIT_MASK_RTS_LEN_TH_8814B 0xff -#define BIT_RTS_LEN_TH_8814B(x) (((x) & BIT_MASK_RTS_LEN_TH_8814B) << BIT_SHIFT_RTS_LEN_TH_8814B) -#define BIT_GET_RTS_LEN_TH_8814B(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8814B) & BIT_MASK_RTS_LEN_TH_8814B) - - - -/* 2 REG_BAR_MODE_CTRL_8814B */ - -#define BIT_SHIFT_BAR_RTY_LMT_8814B 16 -#define BIT_MASK_BAR_RTY_LMT_8814B 0x3 -#define BIT_BAR_RTY_LMT_8814B(x) (((x) & BIT_MASK_BAR_RTY_LMT_8814B) << BIT_SHIFT_BAR_RTY_LMT_8814B) -#define BIT_GET_BAR_RTY_LMT_8814B(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8814B) & BIT_MASK_BAR_RTY_LMT_8814B) - - - -#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B 8 -#define BIT_MASK_BAR_PKT_TXTIME_TH_8814B 0xff -#define BIT_BAR_PKT_TXTIME_TH_8814B(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8814B) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) -#define BIT_GET_BAR_PKT_TXTIME_TH_8814B(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) & BIT_MASK_BAR_PKT_TXTIME_TH_8814B) - - -#define BIT_BAR_EN_V1_8814B BIT(6) - -#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B 0 -#define BIT_MASK_BAR_PKTNUM_TH_V1_8814B 0x3f -#define BIT_BAR_PKTNUM_TH_V1_8814B(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8814B) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) -#define BIT_GET_BAR_PKTNUM_TH_V1_8814B(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) & BIT_MASK_BAR_PKTNUM_TH_V1_8814B) - - - -/* 2 REG_RA_TRY_RATE_AGG_LMT_8814B */ - -#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B 0 -#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B 0x3f -#define BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) -#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8814B(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B) - - - -/* 2 REG_MACID_SLEEP2_8814B */ - -#define BIT_SHIFT_MACID95_64PKTSLEEP_8814B 0 -#define BIT_MASK_MACID95_64PKTSLEEP_8814B 0xffffffffL -#define BIT_MACID95_64PKTSLEEP_8814B(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8814B) << BIT_SHIFT_MACID95_64PKTSLEEP_8814B) -#define BIT_GET_MACID95_64PKTSLEEP_8814B(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8814B) & BIT_MASK_MACID95_64PKTSLEEP_8814B) - - - -/* 2 REG_MACID_SLEEP_8814B */ - -#define BIT_SHIFT_MACID31_0_PKTSLEEP_8814B 0 -#define BIT_MASK_MACID31_0_PKTSLEEP_8814B 0xffffffffL -#define BIT_MACID31_0_PKTSLEEP_8814B(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8814B) << BIT_SHIFT_MACID31_0_PKTSLEEP_8814B) -#define BIT_GET_MACID31_0_PKTSLEEP_8814B(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8814B) & BIT_MASK_MACID31_0_PKTSLEEP_8814B) - - - -/* 2 REG_HW_SEQ0_8814B */ - -#define BIT_SHIFT_HW_SSN_SEQ0_8814B 0 -#define BIT_MASK_HW_SSN_SEQ0_8814B 0xfff -#define BIT_HW_SSN_SEQ0_8814B(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8814B) << BIT_SHIFT_HW_SSN_SEQ0_8814B) -#define BIT_GET_HW_SSN_SEQ0_8814B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8814B) & BIT_MASK_HW_SSN_SEQ0_8814B) - - - -/* 2 REG_HW_SEQ1_8814B */ - -#define BIT_SHIFT_HW_SSN_SEQ1_8814B 0 -#define BIT_MASK_HW_SSN_SEQ1_8814B 0xfff -#define BIT_HW_SSN_SEQ1_8814B(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8814B) << BIT_SHIFT_HW_SSN_SEQ1_8814B) -#define BIT_GET_HW_SSN_SEQ1_8814B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8814B) & BIT_MASK_HW_SSN_SEQ1_8814B) - - - -/* 2 REG_HW_SEQ2_8814B */ - -#define BIT_SHIFT_HW_SSN_SEQ2_8814B 0 -#define BIT_MASK_HW_SSN_SEQ2_8814B 0xfff -#define BIT_HW_SSN_SEQ2_8814B(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8814B) << BIT_SHIFT_HW_SSN_SEQ2_8814B) -#define BIT_GET_HW_SSN_SEQ2_8814B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8814B) & BIT_MASK_HW_SSN_SEQ2_8814B) - - - -/* 2 REG_HW_SEQ3_8814B */ - -#define BIT_SHIFT_HW_SSN_SEQ3_8814B 0 -#define BIT_MASK_HW_SSN_SEQ3_8814B 0xfff -#define BIT_HW_SSN_SEQ3_8814B(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8814B) << BIT_SHIFT_HW_SSN_SEQ3_8814B) -#define BIT_GET_HW_SSN_SEQ3_8814B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8814B) & BIT_MASK_HW_SSN_SEQ3_8814B) - - - -/* 2 REG_NULL_PKT_STATUS_V1_8814B */ - -#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8814B 2 -#define BIT_MASK_PTCL_TOTAL_PG_V2_8814B 0x3fff -#define BIT_PTCL_TOTAL_PG_V2_8814B(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8814B) << BIT_SHIFT_PTCL_TOTAL_PG_V2_8814B) -#define BIT_GET_PTCL_TOTAL_PG_V2_8814B(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8814B) & BIT_MASK_PTCL_TOTAL_PG_V2_8814B) - - -#define BIT_TX_NULL_1_8814B BIT(1) -#define BIT_TX_NULL_0_8814B BIT(0) - -/* 2 REG_PTCL_ERR_STATUS_8814B */ -#define BIT_PTCL_RATE_TABLE_INVALID_8814B BIT(7) -#define BIT_FTM_T2R_ERROR_8814B BIT(6) -#define BIT_PTCL_ERR0_8814B BIT(5) -#define BIT_PTCL_ERR1_8814B BIT(4) -#define BIT_PTCL_ERR2_8814B BIT(3) -#define BIT_PTCL_ERR3_8814B BIT(2) -#define BIT_PTCL_ERR4_8814B BIT(1) -#define BIT_PTCL_ERR5_8814B BIT(0) - -/* 2 REG_NULL_PKT_STATUS_EXTEND_8814B */ -#define BIT_CLI3_TX_NULL_1_8814B BIT(7) -#define BIT_CLI3_TX_NULL_0_8814B BIT(6) -#define BIT_CLI2_TX_NULL_1_8814B BIT(5) -#define BIT_CLI2_TX_NULL_0_8814B BIT(4) -#define BIT_CLI1_TX_NULL_1_8814B BIT(3) -#define BIT_CLI1_TX_NULL_0_8814B BIT(2) -#define BIT_CLI0_TX_NULL_1_8814B BIT(1) -#define BIT_CLI0_TX_NULL_0_8814B BIT(0) - -/* 2 REG_VIDEO_ENHANCEMENT_FUN_8814B */ -#define BIT_VIDEO_JUST_DROP_8814B BIT(1) -#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8814B BIT(0) - -/* 2 REG_BT_POLLUTE_PKT_CNT_8814B */ - -#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8814B 0 -#define BIT_MASK_BT_POLLUTE_PKT_CNT_8814B 0xffff -#define BIT_BT_POLLUTE_PKT_CNT_8814B(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8814B) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8814B) -#define BIT_GET_BT_POLLUTE_PKT_CNT_8814B(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8814B) & BIT_MASK_BT_POLLUTE_PKT_CNT_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_PTCL_DBG_8814B */ - -#define BIT_SHIFT_PTCL_DBG_8814B 0 -#define BIT_MASK_PTCL_DBG_8814B 0xffffffffL -#define BIT_PTCL_DBG_8814B(x) (((x) & BIT_MASK_PTCL_DBG_8814B) << BIT_SHIFT_PTCL_DBG_8814B) -#define BIT_GET_PTCL_DBG_8814B(x) (((x) >> BIT_SHIFT_PTCL_DBG_8814B) & BIT_MASK_PTCL_DBG_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_CPUMGQ_TIMER_CTRL2_8814B */ - -#define BIT_SHIFT_TRI_HEAD_ADDR_8814B 16 -#define BIT_MASK_TRI_HEAD_ADDR_8814B 0xfff -#define BIT_TRI_HEAD_ADDR_8814B(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8814B) << BIT_SHIFT_TRI_HEAD_ADDR_8814B) -#define BIT_GET_TRI_HEAD_ADDR_8814B(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8814B) & BIT_MASK_TRI_HEAD_ADDR_8814B) - - -#define BIT_DROP_TH_EN_8814B BIT(8) - -#define BIT_SHIFT_DROP_TH_8814B 0 -#define BIT_MASK_DROP_TH_8814B 0xff -#define BIT_DROP_TH_8814B(x) (((x) & BIT_MASK_DROP_TH_8814B) << BIT_SHIFT_DROP_TH_8814B) -#define BIT_GET_DROP_TH_8814B(x) (((x) >> BIT_SHIFT_DROP_TH_8814B) & BIT_MASK_DROP_TH_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_DUMMY_PAGE4_V1_8814B */ - -/* 2 REG_MOREDATA_8814B */ -#define BIT_MOREDATA_CTRL2_EN_V1_8814B BIT(3) -#define BIT_MOREDATA_CTRL1_EN_V1_8814B BIT(2) -#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8814B BIT(0) - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_Q0_Q1_INFO_8814B */ -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8814B BIT(31) - -#define BIT_SHIFT_GTAB_ID_8814B 28 -#define BIT_MASK_GTAB_ID_8814B 0x7 -#define BIT_GTAB_ID_8814B(x) (((x) & BIT_MASK_GTAB_ID_8814B) << BIT_SHIFT_GTAB_ID_8814B) -#define BIT_GET_GTAB_ID_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_8814B) & BIT_MASK_GTAB_ID_8814B) - - - -#define BIT_SHIFT_AC1_PKT_INFO_8814B 16 -#define BIT_MASK_AC1_PKT_INFO_8814B 0xfff -#define BIT_AC1_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC1_PKT_INFO_8814B) << BIT_SHIFT_AC1_PKT_INFO_8814B) -#define BIT_GET_AC1_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8814B) & BIT_MASK_AC1_PKT_INFO_8814B) - - -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8814B BIT(15) - -#define BIT_SHIFT_GTAB_ID_V1_8814B 12 -#define BIT_MASK_GTAB_ID_V1_8814B 0x7 -#define BIT_GTAB_ID_V1_8814B(x) (((x) & BIT_MASK_GTAB_ID_V1_8814B) << BIT_SHIFT_GTAB_ID_V1_8814B) -#define BIT_GET_GTAB_ID_V1_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8814B) & BIT_MASK_GTAB_ID_V1_8814B) - - - -#define BIT_SHIFT_AC0_PKT_INFO_8814B 0 -#define BIT_MASK_AC0_PKT_INFO_8814B 0xfff -#define BIT_AC0_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC0_PKT_INFO_8814B) << BIT_SHIFT_AC0_PKT_INFO_8814B) -#define BIT_GET_AC0_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8814B) & BIT_MASK_AC0_PKT_INFO_8814B) - - - -/* 2 REG_Q2_Q3_INFO_8814B */ -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8814B BIT(31) - -#define BIT_SHIFT_GTAB_ID_8814B 28 -#define BIT_MASK_GTAB_ID_8814B 0x7 -#define BIT_GTAB_ID_8814B(x) (((x) & BIT_MASK_GTAB_ID_8814B) << BIT_SHIFT_GTAB_ID_8814B) -#define BIT_GET_GTAB_ID_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_8814B) & BIT_MASK_GTAB_ID_8814B) - - - -#define BIT_SHIFT_AC3_PKT_INFO_8814B 16 -#define BIT_MASK_AC3_PKT_INFO_8814B 0xfff -#define BIT_AC3_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC3_PKT_INFO_8814B) << BIT_SHIFT_AC3_PKT_INFO_8814B) -#define BIT_GET_AC3_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8814B) & BIT_MASK_AC3_PKT_INFO_8814B) - - -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8814B BIT(15) - -#define BIT_SHIFT_GTAB_ID_V1_8814B 12 -#define BIT_MASK_GTAB_ID_V1_8814B 0x7 -#define BIT_GTAB_ID_V1_8814B(x) (((x) & BIT_MASK_GTAB_ID_V1_8814B) << BIT_SHIFT_GTAB_ID_V1_8814B) -#define BIT_GET_GTAB_ID_V1_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8814B) & BIT_MASK_GTAB_ID_V1_8814B) - - - -#define BIT_SHIFT_AC2_PKT_INFO_8814B 0 -#define BIT_MASK_AC2_PKT_INFO_8814B 0xfff -#define BIT_AC2_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC2_PKT_INFO_8814B) << BIT_SHIFT_AC2_PKT_INFO_8814B) -#define BIT_GET_AC2_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8814B) & BIT_MASK_AC2_PKT_INFO_8814B) - - - -/* 2 REG_Q4_Q5_INFO_8814B */ -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8814B BIT(31) - -#define BIT_SHIFT_GTAB_ID_8814B 28 -#define BIT_MASK_GTAB_ID_8814B 0x7 -#define BIT_GTAB_ID_8814B(x) (((x) & BIT_MASK_GTAB_ID_8814B) << BIT_SHIFT_GTAB_ID_8814B) -#define BIT_GET_GTAB_ID_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_8814B) & BIT_MASK_GTAB_ID_8814B) - - - -#define BIT_SHIFT_AC5_PKT_INFO_8814B 16 -#define BIT_MASK_AC5_PKT_INFO_8814B 0xfff -#define BIT_AC5_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC5_PKT_INFO_8814B) << BIT_SHIFT_AC5_PKT_INFO_8814B) -#define BIT_GET_AC5_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8814B) & BIT_MASK_AC5_PKT_INFO_8814B) - - -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8814B BIT(15) - -#define BIT_SHIFT_GTAB_ID_V1_8814B 12 -#define BIT_MASK_GTAB_ID_V1_8814B 0x7 -#define BIT_GTAB_ID_V1_8814B(x) (((x) & BIT_MASK_GTAB_ID_V1_8814B) << BIT_SHIFT_GTAB_ID_V1_8814B) -#define BIT_GET_GTAB_ID_V1_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8814B) & BIT_MASK_GTAB_ID_V1_8814B) - - - -#define BIT_SHIFT_AC4_PKT_INFO_8814B 0 -#define BIT_MASK_AC4_PKT_INFO_8814B 0xfff -#define BIT_AC4_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC4_PKT_INFO_8814B) << BIT_SHIFT_AC4_PKT_INFO_8814B) -#define BIT_GET_AC4_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8814B) & BIT_MASK_AC4_PKT_INFO_8814B) - - - -/* 2 REG_Q6_Q7_INFO_8814B */ -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8814B BIT(31) - -#define BIT_SHIFT_GTAB_ID_8814B 28 -#define BIT_MASK_GTAB_ID_8814B 0x7 -#define BIT_GTAB_ID_8814B(x) (((x) & BIT_MASK_GTAB_ID_8814B) << BIT_SHIFT_GTAB_ID_8814B) -#define BIT_GET_GTAB_ID_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_8814B) & BIT_MASK_GTAB_ID_8814B) - - - -#define BIT_SHIFT_AC7_PKT_INFO_8814B 16 -#define BIT_MASK_AC7_PKT_INFO_8814B 0xfff -#define BIT_AC7_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC7_PKT_INFO_8814B) << BIT_SHIFT_AC7_PKT_INFO_8814B) -#define BIT_GET_AC7_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8814B) & BIT_MASK_AC7_PKT_INFO_8814B) - - -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8814B BIT(15) - -#define BIT_SHIFT_GTAB_ID_V1_8814B 12 -#define BIT_MASK_GTAB_ID_V1_8814B 0x7 -#define BIT_GTAB_ID_V1_8814B(x) (((x) & BIT_MASK_GTAB_ID_V1_8814B) << BIT_SHIFT_GTAB_ID_V1_8814B) -#define BIT_GET_GTAB_ID_V1_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8814B) & BIT_MASK_GTAB_ID_V1_8814B) - - - -#define BIT_SHIFT_AC6_PKT_INFO_8814B 0 -#define BIT_MASK_AC6_PKT_INFO_8814B 0xfff -#define BIT_AC6_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC6_PKT_INFO_8814B) << BIT_SHIFT_AC6_PKT_INFO_8814B) -#define BIT_GET_AC6_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8814B) & BIT_MASK_AC6_PKT_INFO_8814B) - - - -/* 2 REG_MGQ_HIQ_INFO_8814B */ - -#define BIT_SHIFT_HIQ_PKT_INFO_8814B 16 -#define BIT_MASK_HIQ_PKT_INFO_8814B 0xfff -#define BIT_HIQ_PKT_INFO_8814B(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8814B) << BIT_SHIFT_HIQ_PKT_INFO_8814B) -#define BIT_GET_HIQ_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8814B) & BIT_MASK_HIQ_PKT_INFO_8814B) - - - -#define BIT_SHIFT_MGQ_PKT_INFO_8814B 0 -#define BIT_MASK_MGQ_PKT_INFO_8814B 0xfff -#define BIT_MGQ_PKT_INFO_8814B(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8814B) << BIT_SHIFT_MGQ_PKT_INFO_8814B) -#define BIT_GET_MGQ_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8814B) & BIT_MASK_MGQ_PKT_INFO_8814B) - - - -/* 2 REG_CMDQ_BCNQ_INFO_8814B */ - -#define BIT_SHIFT_CMDQ_PKT_INFO_8814B 16 -#define BIT_MASK_CMDQ_PKT_INFO_8814B 0xfff -#define BIT_CMDQ_PKT_INFO_8814B(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_8814B) << BIT_SHIFT_CMDQ_PKT_INFO_8814B) -#define BIT_GET_CMDQ_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8814B) & BIT_MASK_CMDQ_PKT_INFO_8814B) - - - -#define BIT_SHIFT_BCNQ_PKT_INFO_8814B 0 -#define BIT_MASK_BCNQ_PKT_INFO_8814B 0xfff -#define BIT_BCNQ_PKT_INFO_8814B(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_8814B) << BIT_SHIFT_BCNQ_PKT_INFO_8814B) -#define BIT_GET_BCNQ_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8814B) & BIT_MASK_BCNQ_PKT_INFO_8814B) - - - -/* 2 REG_USEREG_SETTING_8814B */ -#define BIT_NDPA_USEREG_8814B BIT(21) - -#define BIT_SHIFT_RETRY_USEREG_8814B 19 -#define BIT_MASK_RETRY_USEREG_8814B 0x3 -#define BIT_RETRY_USEREG_8814B(x) (((x) & BIT_MASK_RETRY_USEREG_8814B) << BIT_SHIFT_RETRY_USEREG_8814B) -#define BIT_GET_RETRY_USEREG_8814B(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8814B) & BIT_MASK_RETRY_USEREG_8814B) - - - -#define BIT_SHIFT_TRYPKT_USEREG_8814B 17 -#define BIT_MASK_TRYPKT_USEREG_8814B 0x3 -#define BIT_TRYPKT_USEREG_8814B(x) (((x) & BIT_MASK_TRYPKT_USEREG_8814B) << BIT_SHIFT_TRYPKT_USEREG_8814B) -#define BIT_GET_TRYPKT_USEREG_8814B(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8814B) & BIT_MASK_TRYPKT_USEREG_8814B) - - -#define BIT_CTLPKT_USEREG_8814B BIT(16) - -/* 2 REG_AESIV_SETTING_8814B */ - -#define BIT_SHIFT_AESIV_OFFSET_8814B 0 -#define BIT_MASK_AESIV_OFFSET_8814B 0xfff -#define BIT_AESIV_OFFSET_8814B(x) (((x) & BIT_MASK_AESIV_OFFSET_8814B) << BIT_SHIFT_AESIV_OFFSET_8814B) -#define BIT_GET_AESIV_OFFSET_8814B(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8814B) & BIT_MASK_AESIV_OFFSET_8814B) - - - -/* 2 REG_BF0_TIME_SETTING_8814B */ -#define BIT_BF0_TIMER_SET_8814B BIT(31) -#define BIT_BF0_TIMER_CLR_8814B BIT(30) -#define BIT_BF0_UPDATE_EN_8814B BIT(29) -#define BIT_BF0_TIMER_EN_8814B BIT(28) - -#define BIT_SHIFT_BF0_PRETIME_OVER_8814B 16 -#define BIT_MASK_BF0_PRETIME_OVER_8814B 0xfff -#define BIT_BF0_PRETIME_OVER_8814B(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8814B) << BIT_SHIFT_BF0_PRETIME_OVER_8814B) -#define BIT_GET_BF0_PRETIME_OVER_8814B(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8814B) & BIT_MASK_BF0_PRETIME_OVER_8814B) - - - -#define BIT_SHIFT_BF0_LIFETIME_8814B 0 -#define BIT_MASK_BF0_LIFETIME_8814B 0xffff -#define BIT_BF0_LIFETIME_8814B(x) (((x) & BIT_MASK_BF0_LIFETIME_8814B) << BIT_SHIFT_BF0_LIFETIME_8814B) -#define BIT_GET_BF0_LIFETIME_8814B(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8814B) & BIT_MASK_BF0_LIFETIME_8814B) - - - -/* 2 REG_BF1_TIME_SETTING_8814B */ -#define BIT_BF1_TIMER_SET_8814B BIT(31) -#define BIT_BF1_TIMER_CLR_8814B BIT(30) -#define BIT_BF1_UPDATE_EN_8814B BIT(29) -#define BIT_BF1_TIMER_EN_8814B BIT(28) - -#define BIT_SHIFT_BF1_PRETIME_OVER_8814B 16 -#define BIT_MASK_BF1_PRETIME_OVER_8814B 0xfff -#define BIT_BF1_PRETIME_OVER_8814B(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8814B) << BIT_SHIFT_BF1_PRETIME_OVER_8814B) -#define BIT_GET_BF1_PRETIME_OVER_8814B(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8814B) & BIT_MASK_BF1_PRETIME_OVER_8814B) - - - -#define BIT_SHIFT_BF1_LIFETIME_8814B 0 -#define BIT_MASK_BF1_LIFETIME_8814B 0xffff -#define BIT_BF1_LIFETIME_8814B(x) (((x) & BIT_MASK_BF1_LIFETIME_8814B) << BIT_SHIFT_BF1_LIFETIME_8814B) -#define BIT_GET_BF1_LIFETIME_8814B(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8814B) & BIT_MASK_BF1_LIFETIME_8814B) - - - -/* 2 REG_BF_TIMEOUT_EN_8814B */ -#define BIT_EN_VHT_LDPC_8814B BIT(9) -#define BIT_EN_HT_LDPC_8814B BIT(8) -#define BIT_BF1_TIMEOUT_EN_8814B BIT(1) -#define BIT_BF0_TIMEOUT_EN_8814B BIT(0) - -/* 2 REG_MACID_RELEASE0_8814B */ - -#define BIT_SHIFT_MACID31_0_RELEASE_8814B 0 -#define BIT_MASK_MACID31_0_RELEASE_8814B 0xffffffffL -#define BIT_MACID31_0_RELEASE_8814B(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8814B) << BIT_SHIFT_MACID31_0_RELEASE_8814B) -#define BIT_GET_MACID31_0_RELEASE_8814B(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8814B) & BIT_MASK_MACID31_0_RELEASE_8814B) - - - -/* 2 REG_MACID_RELEASE1_8814B */ - -#define BIT_SHIFT_MACID63_32_RELEASE_8814B 0 -#define BIT_MASK_MACID63_32_RELEASE_8814B 0xffffffffL -#define BIT_MACID63_32_RELEASE_8814B(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8814B) << BIT_SHIFT_MACID63_32_RELEASE_8814B) -#define BIT_GET_MACID63_32_RELEASE_8814B(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8814B) & BIT_MASK_MACID63_32_RELEASE_8814B) - - - -/* 2 REG_MACID_RELEASE2_8814B */ - -#define BIT_SHIFT_MACID95_64_RELEASE_8814B 0 -#define BIT_MASK_MACID95_64_RELEASE_8814B 0xffffffffL -#define BIT_MACID95_64_RELEASE_8814B(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8814B) << BIT_SHIFT_MACID95_64_RELEASE_8814B) -#define BIT_GET_MACID95_64_RELEASE_8814B(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8814B) & BIT_MASK_MACID95_64_RELEASE_8814B) - - - -/* 2 REG_MACID_RELEASE3_8814B */ - -#define BIT_SHIFT_MACID127_96_RELEASE_8814B 0 -#define BIT_MASK_MACID127_96_RELEASE_8814B 0xffffffffL -#define BIT_MACID127_96_RELEASE_8814B(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8814B) << BIT_SHIFT_MACID127_96_RELEASE_8814B) -#define BIT_GET_MACID127_96_RELEASE_8814B(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8814B) & BIT_MASK_MACID127_96_RELEASE_8814B) - - - -/* 2 REG_MACID_RELEASE_SETTING_8814B */ -#define BIT_MACID_VALUE_8814B BIT(7) - -#define BIT_SHIFT_MACID_OFFSET_8814B 0 -#define BIT_MASK_MACID_OFFSET_8814B 0x7f -#define BIT_MACID_OFFSET_8814B(x) (((x) & BIT_MASK_MACID_OFFSET_8814B) << BIT_SHIFT_MACID_OFFSET_8814B) -#define BIT_GET_MACID_OFFSET_8814B(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8814B) & BIT_MASK_MACID_OFFSET_8814B) - - - -/* 2 REG_FAST_EDCA_VOVI_SETTING_8814B */ - -#define BIT_SHIFT_VI_FAST_EDCA_TO_8814B 24 -#define BIT_MASK_VI_FAST_EDCA_TO_8814B 0xff -#define BIT_VI_FAST_EDCA_TO_8814B(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8814B) << BIT_SHIFT_VI_FAST_EDCA_TO_8814B) -#define BIT_GET_VI_FAST_EDCA_TO_8814B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8814B) & BIT_MASK_VI_FAST_EDCA_TO_8814B) - - -#define BIT_VI_THRESHOLD_SEL_8814B BIT(23) - -#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B 16 -#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B 0x7f -#define BIT_VI_FAST_EDCA_PKT_TH_8814B(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) -#define BIT_GET_VI_FAST_EDCA_PKT_TH_8814B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B) - - - -#define BIT_SHIFT_VO_FAST_EDCA_TO_8814B 8 -#define BIT_MASK_VO_FAST_EDCA_TO_8814B 0xff -#define BIT_VO_FAST_EDCA_TO_8814B(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8814B) << BIT_SHIFT_VO_FAST_EDCA_TO_8814B) -#define BIT_GET_VO_FAST_EDCA_TO_8814B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8814B) & BIT_MASK_VO_FAST_EDCA_TO_8814B) - - -#define BIT_VO_THRESHOLD_SEL_8814B BIT(7) - -#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B 0 -#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B 0x7f -#define BIT_VO_FAST_EDCA_PKT_TH_8814B(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) -#define BIT_GET_VO_FAST_EDCA_PKT_TH_8814B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B) - - - -/* 2 REG_FAST_EDCA_BEBK_SETTING_8814B */ - -#define BIT_SHIFT_BK_FAST_EDCA_TO_8814B 24 -#define BIT_MASK_BK_FAST_EDCA_TO_8814B 0xff -#define BIT_BK_FAST_EDCA_TO_8814B(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8814B) << BIT_SHIFT_BK_FAST_EDCA_TO_8814B) -#define BIT_GET_BK_FAST_EDCA_TO_8814B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8814B) & BIT_MASK_BK_FAST_EDCA_TO_8814B) - - -#define BIT_BK_THRESHOLD_SEL_8814B BIT(23) - -#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B 16 -#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B 0x7f -#define BIT_BK_FAST_EDCA_PKT_TH_8814B(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) -#define BIT_GET_BK_FAST_EDCA_PKT_TH_8814B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B) - - - -#define BIT_SHIFT_BE_FAST_EDCA_TO_8814B 8 -#define BIT_MASK_BE_FAST_EDCA_TO_8814B 0xff -#define BIT_BE_FAST_EDCA_TO_8814B(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8814B) << BIT_SHIFT_BE_FAST_EDCA_TO_8814B) -#define BIT_GET_BE_FAST_EDCA_TO_8814B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8814B) & BIT_MASK_BE_FAST_EDCA_TO_8814B) - - -#define BIT_BE_THRESHOLD_SEL_8814B BIT(7) - -#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B 0 -#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B 0x7f -#define BIT_BE_FAST_EDCA_PKT_TH_8814B(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) -#define BIT_GET_BE_FAST_EDCA_PKT_TH_8814B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B) - - - -/* 2 REG_MACID_DROP0_8814B */ - -#define BIT_SHIFT_MACID31_0_DROP_8814B 0 -#define BIT_MASK_MACID31_0_DROP_8814B 0xffffffffL -#define BIT_MACID31_0_DROP_8814B(x) (((x) & BIT_MASK_MACID31_0_DROP_8814B) << BIT_SHIFT_MACID31_0_DROP_8814B) -#define BIT_GET_MACID31_0_DROP_8814B(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8814B) & BIT_MASK_MACID31_0_DROP_8814B) - - - -/* 2 REG_MACID_DROP1_8814B */ - -#define BIT_SHIFT_MACID63_32_DROP_8814B 0 -#define BIT_MASK_MACID63_32_DROP_8814B 0xffffffffL -#define BIT_MACID63_32_DROP_8814B(x) (((x) & BIT_MASK_MACID63_32_DROP_8814B) << BIT_SHIFT_MACID63_32_DROP_8814B) -#define BIT_GET_MACID63_32_DROP_8814B(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8814B) & BIT_MASK_MACID63_32_DROP_8814B) - - +/* 2 REG_POWER_STAGE1_8814B */ +#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8814B BIT(31) +#define BIT_PTA_WL_PRI_MASK_BCNQ_8814B BIT(30) +#define BIT_PTA_WL_PRI_MASK_HIQ_8814B BIT(29) +#define BIT_PTA_WL_PRI_MASK_MGQ_8814B BIT(28) +#define BIT_PTA_WL_PRI_MASK_BK_8814B BIT(27) +#define BIT_PTA_WL_PRI_MASK_BE_8814B BIT(26) +#define BIT_PTA_WL_PRI_MASK_VI_8814B BIT(25) +#define BIT_PTA_WL_PRI_MASK_VO_8814B BIT(24) -/* 2 REG_MACID_DROP2_8814B */ +#define BIT_SHIFT_POWER_STAGE1_8814B 0 +#define BIT_MASK_POWER_STAGE1_8814B 0xffffff +#define BIT_POWER_STAGE1_8814B(x) \ + (((x) & BIT_MASK_POWER_STAGE1_8814B) << BIT_SHIFT_POWER_STAGE1_8814B) +#define BITS_POWER_STAGE1_8814B \ + (BIT_MASK_POWER_STAGE1_8814B << BIT_SHIFT_POWER_STAGE1_8814B) +#define BIT_CLEAR_POWER_STAGE1_8814B(x) ((x) & (~BITS_POWER_STAGE1_8814B)) +#define BIT_GET_POWER_STAGE1_8814B(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1_8814B) & BIT_MASK_POWER_STAGE1_8814B) +#define BIT_SET_POWER_STAGE1_8814B(x, v) \ + (BIT_CLEAR_POWER_STAGE1_8814B(x) | BIT_POWER_STAGE1_8814B(v)) -#define BIT_SHIFT_MACID95_64_DROP_8814B 0 -#define BIT_MASK_MACID95_64_DROP_8814B 0xffffffffL -#define BIT_MACID95_64_DROP_8814B(x) (((x) & BIT_MASK_MACID95_64_DROP_8814B) << BIT_SHIFT_MACID95_64_DROP_8814B) -#define BIT_GET_MACID95_64_DROP_8814B(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8814B) & BIT_MASK_MACID95_64_DROP_8814B) +/* 2 REG_POWER_STAGE2_8814B */ +#define BIT__CTRL_PKT_POW_ADJ_8814B BIT(24) +#define BIT_SHIFT_POWER_STAGE2_8814B 0 +#define BIT_MASK_POWER_STAGE2_8814B 0xffffff +#define BIT_POWER_STAGE2_8814B(x) \ + (((x) & BIT_MASK_POWER_STAGE2_8814B) << BIT_SHIFT_POWER_STAGE2_8814B) +#define BITS_POWER_STAGE2_8814B \ + (BIT_MASK_POWER_STAGE2_8814B << BIT_SHIFT_POWER_STAGE2_8814B) +#define BIT_CLEAR_POWER_STAGE2_8814B(x) ((x) & (~BITS_POWER_STAGE2_8814B)) +#define BIT_GET_POWER_STAGE2_8814B(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2_8814B) & BIT_MASK_POWER_STAGE2_8814B) +#define BIT_SET_POWER_STAGE2_8814B(x, v) \ + (BIT_CLEAR_POWER_STAGE2_8814B(x) | BIT_POWER_STAGE2_8814B(v)) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8814B */ +#define BIT_DMA_THIS_QUEUE_BK_8814B BIT(23) +#define BIT_DMA_THIS_QUEUE_BE_8814B BIT(22) +#define BIT_DMA_THIS_QUEUE_VI_8814B BIT(21) +#define BIT_DMA_THIS_QUEUE_VO_8814B BIT(20) + +#define BIT_SHIFT_TOTAL_LEN_TH_8814B 8 +#define BIT_MASK_TOTAL_LEN_TH_8814B 0xfff +#define BIT_TOTAL_LEN_TH_8814B(x) \ + (((x) & BIT_MASK_TOTAL_LEN_TH_8814B) << BIT_SHIFT_TOTAL_LEN_TH_8814B) +#define BITS_TOTAL_LEN_TH_8814B \ + (BIT_MASK_TOTAL_LEN_TH_8814B << BIT_SHIFT_TOTAL_LEN_TH_8814B) +#define BIT_CLEAR_TOTAL_LEN_TH_8814B(x) ((x) & (~BITS_TOTAL_LEN_TH_8814B)) +#define BIT_GET_TOTAL_LEN_TH_8814B(x) \ + (((x) >> BIT_SHIFT_TOTAL_LEN_TH_8814B) & BIT_MASK_TOTAL_LEN_TH_8814B) +#define BIT_SET_TOTAL_LEN_TH_8814B(x, v) \ + (BIT_CLEAR_TOTAL_LEN_TH_8814B(x) | BIT_TOTAL_LEN_TH_8814B(v)) -/* 2 REG_MACID_DROP3_8814B */ +#define BIT_PRE_TX_CMD_8814B BIT(6) -#define BIT_SHIFT_MACID127_96_DROP_8814B 0 -#define BIT_MASK_MACID127_96_DROP_8814B 0xffffffffL -#define BIT_MACID127_96_DROP_8814B(x) (((x) & BIT_MASK_MACID127_96_DROP_8814B) << BIT_SHIFT_MACID127_96_DROP_8814B) -#define BIT_GET_MACID127_96_DROP_8814B(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8814B) & BIT_MASK_MACID127_96_DROP_8814B) +#define BIT_SHIFT_NUM_SCL_EN_8814B 4 +#define BIT_MASK_NUM_SCL_EN_8814B 0x3 +#define BIT_NUM_SCL_EN_8814B(x) \ + (((x) & BIT_MASK_NUM_SCL_EN_8814B) << BIT_SHIFT_NUM_SCL_EN_8814B) +#define BITS_NUM_SCL_EN_8814B \ + (BIT_MASK_NUM_SCL_EN_8814B << BIT_SHIFT_NUM_SCL_EN_8814B) +#define BIT_CLEAR_NUM_SCL_EN_8814B(x) ((x) & (~BITS_NUM_SCL_EN_8814B)) +#define BIT_GET_NUM_SCL_EN_8814B(x) \ + (((x) >> BIT_SHIFT_NUM_SCL_EN_8814B) & BIT_MASK_NUM_SCL_EN_8814B) +#define BIT_SET_NUM_SCL_EN_8814B(x, v) \ + (BIT_CLEAR_NUM_SCL_EN_8814B(x) | BIT_NUM_SCL_EN_8814B(v)) +#define BIT_BK_EN_8814B BIT(3) +#define BIT_BE_EN_8814B BIT(2) +#define BIT_VI_EN_8814B BIT(1) +#define BIT_VO_EN_8814B BIT(0) +/* 2 REG_PKT_LIFE_TIME_8814B */ -/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8814B */ +#define BIT_SHIFT_PKT_LIFTIME_BEBK_8814B 16 +#define BIT_MASK_PKT_LIFTIME_BEBK_8814B 0xffff +#define BIT_PKT_LIFTIME_BEBK_8814B(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8814B) \ + << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) +#define BITS_PKT_LIFTIME_BEBK_8814B \ + (BIT_MASK_PKT_LIFTIME_BEBK_8814B << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) +#define BIT_CLEAR_PKT_LIFTIME_BEBK_8814B(x) \ + ((x) & (~BITS_PKT_LIFTIME_BEBK_8814B)) +#define BIT_GET_PKT_LIFTIME_BEBK_8814B(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) & \ + BIT_MASK_PKT_LIFTIME_BEBK_8814B) +#define BIT_SET_PKT_LIFTIME_BEBK_8814B(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_BEBK_8814B(x) | BIT_PKT_LIFTIME_BEBK_8814B(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8814B 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8814B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_0_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8814B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8814B) +#define BIT_SHIFT_PKT_LIFTIME_VOVI_8814B 0 +#define BIT_MASK_PKT_LIFTIME_VOVI_8814B 0xffff +#define BIT_PKT_LIFTIME_VOVI_8814B(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8814B) \ + << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) +#define BITS_PKT_LIFTIME_VOVI_8814B \ + (BIT_MASK_PKT_LIFTIME_VOVI_8814B << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) +#define BIT_CLEAR_PKT_LIFTIME_VOVI_8814B(x) \ + ((x) & (~BITS_PKT_LIFTIME_VOVI_8814B)) +#define BIT_GET_PKT_LIFTIME_VOVI_8814B(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) & \ + BIT_MASK_PKT_LIFTIME_VOVI_8814B) +#define BIT_SET_PKT_LIFTIME_VOVI_8814B(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_VOVI_8814B(x) | BIT_PKT_LIFTIME_VOVI_8814B(v)) +/* 2 REG_STBC_SETTING_8814B */ +#define BIT_SHIFT_CDEND_TXTIME_L_8814B 4 +#define BIT_MASK_CDEND_TXTIME_L_8814B 0xf +#define BIT_CDEND_TXTIME_L_8814B(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_L_8814B) \ + << BIT_SHIFT_CDEND_TXTIME_L_8814B) +#define BITS_CDEND_TXTIME_L_8814B \ + (BIT_MASK_CDEND_TXTIME_L_8814B << BIT_SHIFT_CDEND_TXTIME_L_8814B) +#define BIT_CLEAR_CDEND_TXTIME_L_8814B(x) ((x) & (~BITS_CDEND_TXTIME_L_8814B)) +#define BIT_GET_CDEND_TXTIME_L_8814B(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8814B) & \ + BIT_MASK_CDEND_TXTIME_L_8814B) +#define BIT_SET_CDEND_TXTIME_L_8814B(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_L_8814B(x) | BIT_CDEND_TXTIME_L_8814B(v)) -/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8814B */ +#define BIT_SHIFT_NESS_8814B 2 +#define BIT_MASK_NESS_8814B 0x3 +#define BIT_NESS_8814B(x) (((x) & BIT_MASK_NESS_8814B) << BIT_SHIFT_NESS_8814B) +#define BITS_NESS_8814B (BIT_MASK_NESS_8814B << BIT_SHIFT_NESS_8814B) +#define BIT_CLEAR_NESS_8814B(x) ((x) & (~BITS_NESS_8814B)) +#define BIT_GET_NESS_8814B(x) \ + (((x) >> BIT_SHIFT_NESS_8814B) & BIT_MASK_NESS_8814B) +#define BIT_SET_NESS_8814B(x, v) (BIT_CLEAR_NESS_8814B(x) | BIT_NESS_8814B(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8814B 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8814B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_1_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8814B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8814B) +#define BIT_SHIFT_STBC_CFEND_8814B 0 +#define BIT_MASK_STBC_CFEND_8814B 0x3 +#define BIT_STBC_CFEND_8814B(x) \ + (((x) & BIT_MASK_STBC_CFEND_8814B) << BIT_SHIFT_STBC_CFEND_8814B) +#define BITS_STBC_CFEND_8814B \ + (BIT_MASK_STBC_CFEND_8814B << BIT_SHIFT_STBC_CFEND_8814B) +#define BIT_CLEAR_STBC_CFEND_8814B(x) ((x) & (~BITS_STBC_CFEND_8814B)) +#define BIT_GET_STBC_CFEND_8814B(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_8814B) & BIT_MASK_STBC_CFEND_8814B) +#define BIT_SET_STBC_CFEND_8814B(x, v) \ + (BIT_CLEAR_STBC_CFEND_8814B(x) | BIT_STBC_CFEND_8814B(v)) +/* 2 REG_STBC_SETTING2_8814B */ +#define BIT_SHIFT_CDEND_TXTIME_H_8814B 0 +#define BIT_MASK_CDEND_TXTIME_H_8814B 0x1f +#define BIT_CDEND_TXTIME_H_8814B(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_H_8814B) \ + << BIT_SHIFT_CDEND_TXTIME_H_8814B) +#define BITS_CDEND_TXTIME_H_8814B \ + (BIT_MASK_CDEND_TXTIME_H_8814B << BIT_SHIFT_CDEND_TXTIME_H_8814B) +#define BIT_CLEAR_CDEND_TXTIME_H_8814B(x) ((x) & (~BITS_CDEND_TXTIME_H_8814B)) +#define BIT_GET_CDEND_TXTIME_H_8814B(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8814B) & \ + BIT_MASK_CDEND_TXTIME_H_8814B) +#define BIT_SET_CDEND_TXTIME_H_8814B(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_H_8814B(x) | BIT_CDEND_TXTIME_H_8814B(v)) -/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8814B */ +/* 2 REG_QUEUE_CTRL_8814B */ +#define BIT_FORCE_RND_PRI_8814B BIT(6) +#define BIT_PTA_EDCCA_EN_8814B BIT(5) +#define BIT_PTA_WL_TX_EN_8814B BIT(4) +#define BIT_USE_DATA_BW_8814B BIT(3) +#define BIT_TRI_PKT_INT_MODE1_8814B BIT(2) +#define BIT_TRI_PKT_INT_MODE0_8814B BIT(1) +#define BIT_ACQ_MODE_SEL_8814B BIT(0) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8814B 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8814B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_2_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8814B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8814B) +/* 2 REG_SINGLE_AMPDU_CTRL_8814B */ +#define BIT_EN_SINGLE_APMDU_8814B BIT(7) +/* 2 REG_PROT_MODE_CTRL_8814B */ +#define BIT_SHIFT_RTS_MAX_AGG_NUM_8814B 24 +#define BIT_MASK_RTS_MAX_AGG_NUM_8814B 0x3f +#define BIT_RTS_MAX_AGG_NUM_8814B(x) \ + (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8814B) \ + << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) +#define BITS_RTS_MAX_AGG_NUM_8814B \ + (BIT_MASK_RTS_MAX_AGG_NUM_8814B << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) +#define BIT_CLEAR_RTS_MAX_AGG_NUM_8814B(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8814B)) +#define BIT_GET_RTS_MAX_AGG_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) & \ + BIT_MASK_RTS_MAX_AGG_NUM_8814B) +#define BIT_SET_RTS_MAX_AGG_NUM_8814B(x, v) \ + (BIT_CLEAR_RTS_MAX_AGG_NUM_8814B(x) | BIT_RTS_MAX_AGG_NUM_8814B(v)) -/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8814B */ +#define BIT_SHIFT_MAX_AGG_NUM_8814B 16 +#define BIT_MASK_MAX_AGG_NUM_8814B 0x3f +#define BIT_MAX_AGG_NUM_8814B(x) \ + (((x) & BIT_MASK_MAX_AGG_NUM_8814B) << BIT_SHIFT_MAX_AGG_NUM_8814B) +#define BITS_MAX_AGG_NUM_8814B \ + (BIT_MASK_MAX_AGG_NUM_8814B << BIT_SHIFT_MAX_AGG_NUM_8814B) +#define BIT_CLEAR_MAX_AGG_NUM_8814B(x) ((x) & (~BITS_MAX_AGG_NUM_8814B)) +#define BIT_GET_MAX_AGG_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_AGG_NUM_8814B) & BIT_MASK_MAX_AGG_NUM_8814B) +#define BIT_SET_MAX_AGG_NUM_8814B(x, v) \ + (BIT_CLEAR_MAX_AGG_NUM_8814B(x) | BIT_MAX_AGG_NUM_8814B(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8814B 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8814B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_3_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8814B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8814B) +#define BIT_SHIFT_RTS_TXTIME_TH_8814B 8 +#define BIT_MASK_RTS_TXTIME_TH_8814B 0xff +#define BIT_RTS_TXTIME_TH_8814B(x) \ + (((x) & BIT_MASK_RTS_TXTIME_TH_8814B) << BIT_SHIFT_RTS_TXTIME_TH_8814B) +#define BITS_RTS_TXTIME_TH_8814B \ + (BIT_MASK_RTS_TXTIME_TH_8814B << BIT_SHIFT_RTS_TXTIME_TH_8814B) +#define BIT_CLEAR_RTS_TXTIME_TH_8814B(x) ((x) & (~BITS_RTS_TXTIME_TH_8814B)) +#define BIT_GET_RTS_TXTIME_TH_8814B(x) \ + (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8814B) & BIT_MASK_RTS_TXTIME_TH_8814B) +#define BIT_SET_RTS_TXTIME_TH_8814B(x, v) \ + (BIT_CLEAR_RTS_TXTIME_TH_8814B(x) | BIT_RTS_TXTIME_TH_8814B(v)) +#define BIT_SHIFT_RTS_LEN_TH_8814B 0 +#define BIT_MASK_RTS_LEN_TH_8814B 0xff +#define BIT_RTS_LEN_TH_8814B(x) \ + (((x) & BIT_MASK_RTS_LEN_TH_8814B) << BIT_SHIFT_RTS_LEN_TH_8814B) +#define BITS_RTS_LEN_TH_8814B \ + (BIT_MASK_RTS_LEN_TH_8814B << BIT_SHIFT_RTS_LEN_TH_8814B) +#define BIT_CLEAR_RTS_LEN_TH_8814B(x) ((x) & (~BITS_RTS_LEN_TH_8814B)) +#define BIT_GET_RTS_LEN_TH_8814B(x) \ + (((x) >> BIT_SHIFT_RTS_LEN_TH_8814B) & BIT_MASK_RTS_LEN_TH_8814B) +#define BIT_SET_RTS_LEN_TH_8814B(x, v) \ + (BIT_CLEAR_RTS_LEN_TH_8814B(x) | BIT_RTS_LEN_TH_8814B(v)) +/* 2 REG_BAR_MODE_CTRL_8814B */ -/* 2 REG_MGG_FIFO_CRTL_8814B */ -#define BIT_R_MGG_FIFO_EN_8814B BIT(31) +#define BIT_SHIFT_BAR_RTY_LMT_8814B 16 +#define BIT_MASK_BAR_RTY_LMT_8814B 0x3 +#define BIT_BAR_RTY_LMT_8814B(x) \ + (((x) & BIT_MASK_BAR_RTY_LMT_8814B) << BIT_SHIFT_BAR_RTY_LMT_8814B) +#define BITS_BAR_RTY_LMT_8814B \ + (BIT_MASK_BAR_RTY_LMT_8814B << BIT_SHIFT_BAR_RTY_LMT_8814B) +#define BIT_CLEAR_BAR_RTY_LMT_8814B(x) ((x) & (~BITS_BAR_RTY_LMT_8814B)) +#define BIT_GET_BAR_RTY_LMT_8814B(x) \ + (((x) >> BIT_SHIFT_BAR_RTY_LMT_8814B) & BIT_MASK_BAR_RTY_LMT_8814B) +#define BIT_SET_BAR_RTY_LMT_8814B(x, v) \ + (BIT_CLEAR_BAR_RTY_LMT_8814B(x) | BIT_BAR_RTY_LMT_8814B(v)) -#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8814B 28 -#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8814B 0x7 -#define BIT_R_MGG_FIFO_PG_SIZE_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8814B) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8814B) -#define BIT_GET_R_MGG_FIFO_PG_SIZE_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8814B) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8814B) +#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B 8 +#define BIT_MASK_BAR_PKT_TXTIME_TH_8814B 0xff +#define BIT_BAR_PKT_TXTIME_TH_8814B(x) \ + (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8814B) \ + << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) +#define BITS_BAR_PKT_TXTIME_TH_8814B \ + (BIT_MASK_BAR_PKT_TXTIME_TH_8814B << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8814B(x) \ + ((x) & (~BITS_BAR_PKT_TXTIME_TH_8814B)) +#define BIT_GET_BAR_PKT_TXTIME_TH_8814B(x) \ + (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) & \ + BIT_MASK_BAR_PKT_TXTIME_TH_8814B) +#define BIT_SET_BAR_PKT_TXTIME_TH_8814B(x, v) \ + (BIT_CLEAR_BAR_PKT_TXTIME_TH_8814B(x) | BIT_BAR_PKT_TXTIME_TH_8814B(v)) +#define BIT_BAR_EN_V1_8814B BIT(6) +#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B 0 +#define BIT_MASK_BAR_PKTNUM_TH_V1_8814B 0x3f +#define BIT_BAR_PKTNUM_TH_V1_8814B(x) \ + (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8814B) \ + << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) +#define BITS_BAR_PKTNUM_TH_V1_8814B \ + (BIT_MASK_BAR_PKTNUM_TH_V1_8814B << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8814B(x) \ + ((x) & (~BITS_BAR_PKTNUM_TH_V1_8814B)) +#define BIT_GET_BAR_PKTNUM_TH_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) & \ + BIT_MASK_BAR_PKTNUM_TH_V1_8814B) +#define BIT_SET_BAR_PKTNUM_TH_V1_8814B(x, v) \ + (BIT_CLEAR_BAR_PKTNUM_TH_V1_8814B(x) | BIT_BAR_PKTNUM_TH_V1_8814B(v)) -#define BIT_SHIFT_R_MGG_FIFO_START_PG_8814B 16 -#define BIT_MASK_R_MGG_FIFO_START_PG_8814B 0xfff -#define BIT_R_MGG_FIFO_START_PG_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8814B) << BIT_SHIFT_R_MGG_FIFO_START_PG_8814B) -#define BIT_GET_R_MGG_FIFO_START_PG_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8814B) & BIT_MASK_R_MGG_FIFO_START_PG_8814B) +/* 2 REG_RA_TRY_RATE_AGG_LMT_8814B */ +#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B 0 +#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B 0x3f +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B) \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) +#define BITS_RA_TRY_RATE_AGG_LMT_V1_8814B \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8814B(x) \ + ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8814B)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) & \ + BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8814B(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8814B(x) | \ + BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(v)) + +/* 2 REG_MACID_SLEEP_CTRL_8814B */ + +#define BIT_SHIFT_DEBUG_PROTOCOL_8814B 24 +#define BIT_MASK_DEBUG_PROTOCOL_8814B 0xff +#define BIT_DEBUG_PROTOCOL_8814B(x) \ + (((x) & BIT_MASK_DEBUG_PROTOCOL_8814B) \ + << BIT_SHIFT_DEBUG_PROTOCOL_8814B) +#define BITS_DEBUG_PROTOCOL_8814B \ + (BIT_MASK_DEBUG_PROTOCOL_8814B << BIT_SHIFT_DEBUG_PROTOCOL_8814B) +#define BIT_CLEAR_DEBUG_PROTOCOL_8814B(x) ((x) & (~BITS_DEBUG_PROTOCOL_8814B)) +#define BIT_GET_DEBUG_PROTOCOL_8814B(x) \ + (((x) >> BIT_SHIFT_DEBUG_PROTOCOL_8814B) & \ + BIT_MASK_DEBUG_PROTOCOL_8814B) +#define BIT_SET_DEBUG_PROTOCOL_8814B(x, v) \ + (BIT_CLEAR_DEBUG_PROTOCOL_8814B(x) | BIT_DEBUG_PROTOCOL_8814B(v)) + +#define BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B 16 +#define BIT_MASK_BCNQ_PGBNDY_RSEL_8814B 0x7 +#define BIT_BCNQ_PGBNDY_RSEL_8814B(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_RSEL_8814B) \ + << BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B) +#define BITS_BCNQ_PGBNDY_RSEL_8814B \ + (BIT_MASK_BCNQ_PGBNDY_RSEL_8814B << BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B) +#define BIT_CLEAR_BCNQ_PGBNDY_RSEL_8814B(x) \ + ((x) & (~BITS_BCNQ_PGBNDY_RSEL_8814B)) +#define BIT_GET_BCNQ_PGBNDY_RSEL_8814B(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B) & \ + BIT_MASK_BCNQ_PGBNDY_RSEL_8814B) +#define BIT_SET_BCNQ_PGBNDY_RSEL_8814B(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_RSEL_8814B(x) | BIT_BCNQ_PGBNDY_RSEL_8814B(v)) + +#define BIT_SHIFT_MACID_SLEEP_SEL_8814B 0 +#define BIT_MASK_MACID_SLEEP_SEL_8814B 0x7 +#define BIT_MACID_SLEEP_SEL_8814B(x) \ + (((x) & BIT_MASK_MACID_SLEEP_SEL_8814B) \ + << BIT_SHIFT_MACID_SLEEP_SEL_8814B) +#define BITS_MACID_SLEEP_SEL_8814B \ + (BIT_MASK_MACID_SLEEP_SEL_8814B << BIT_SHIFT_MACID_SLEEP_SEL_8814B) +#define BIT_CLEAR_MACID_SLEEP_SEL_8814B(x) ((x) & (~BITS_MACID_SLEEP_SEL_8814B)) +#define BIT_GET_MACID_SLEEP_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_SLEEP_SEL_8814B) & \ + BIT_MASK_MACID_SLEEP_SEL_8814B) +#define BIT_SET_MACID_SLEEP_SEL_8814B(x, v) \ + (BIT_CLEAR_MACID_SLEEP_SEL_8814B(x) | BIT_MACID_SLEEP_SEL_8814B(v)) + +/* 2 REG_MACID_SLEEP_INFO_8814B */ + +#define BIT_SHIFT_MACID_SLEEP_INFO_8814B 0 +#define BIT_MASK_MACID_SLEEP_INFO_8814B 0xffffffffL +#define BIT_MACID_SLEEP_INFO_8814B(x) \ + (((x) & BIT_MASK_MACID_SLEEP_INFO_8814B) \ + << BIT_SHIFT_MACID_SLEEP_INFO_8814B) +#define BITS_MACID_SLEEP_INFO_8814B \ + (BIT_MASK_MACID_SLEEP_INFO_8814B << BIT_SHIFT_MACID_SLEEP_INFO_8814B) +#define BIT_CLEAR_MACID_SLEEP_INFO_8814B(x) \ + ((x) & (~BITS_MACID_SLEEP_INFO_8814B)) +#define BIT_GET_MACID_SLEEP_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_SLEEP_INFO_8814B) & \ + BIT_MASK_MACID_SLEEP_INFO_8814B) +#define BIT_SET_MACID_SLEEP_INFO_8814B(x, v) \ + (BIT_CLEAR_MACID_SLEEP_INFO_8814B(x) | BIT_MACID_SLEEP_INFO_8814B(v)) +/* 2 REG_HW_SEQ0_8814B */ -#define BIT_SHIFT_R_MGG_FIFO_SIZE_8814B 14 -#define BIT_MASK_R_MGG_FIFO_SIZE_8814B 0x3 -#define BIT_R_MGG_FIFO_SIZE_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8814B) << BIT_SHIFT_R_MGG_FIFO_SIZE_8814B) -#define BIT_GET_R_MGG_FIFO_SIZE_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8814B) & BIT_MASK_R_MGG_FIFO_SIZE_8814B) +#define BIT_SHIFT_HW_SSN_SEQ0_8814B 0 +#define BIT_MASK_HW_SSN_SEQ0_8814B 0xfff +#define BIT_HW_SSN_SEQ0_8814B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ0_8814B) << BIT_SHIFT_HW_SSN_SEQ0_8814B) +#define BITS_HW_SSN_SEQ0_8814B \ + (BIT_MASK_HW_SSN_SEQ0_8814B << BIT_SHIFT_HW_SSN_SEQ0_8814B) +#define BIT_CLEAR_HW_SSN_SEQ0_8814B(x) ((x) & (~BITS_HW_SSN_SEQ0_8814B)) +#define BIT_GET_HW_SSN_SEQ0_8814B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8814B) & BIT_MASK_HW_SSN_SEQ0_8814B) +#define BIT_SET_HW_SSN_SEQ0_8814B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ0_8814B(x) | BIT_HW_SSN_SEQ0_8814B(v)) +/* 2 REG_HW_SEQ1_8814B */ -#define BIT_R_MGG_FIFO_PAUSE_8814B BIT(13) +#define BIT_SHIFT_HW_SSN_SEQ1_8814B 0 +#define BIT_MASK_HW_SSN_SEQ1_8814B 0xfff +#define BIT_HW_SSN_SEQ1_8814B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ1_8814B) << BIT_SHIFT_HW_SSN_SEQ1_8814B) +#define BITS_HW_SSN_SEQ1_8814B \ + (BIT_MASK_HW_SSN_SEQ1_8814B << BIT_SHIFT_HW_SSN_SEQ1_8814B) +#define BIT_CLEAR_HW_SSN_SEQ1_8814B(x) ((x) & (~BITS_HW_SSN_SEQ1_8814B)) +#define BIT_GET_HW_SSN_SEQ1_8814B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8814B) & BIT_MASK_HW_SSN_SEQ1_8814B) +#define BIT_SET_HW_SSN_SEQ1_8814B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ1_8814B(x) | BIT_HW_SSN_SEQ1_8814B(v)) -#define BIT_SHIFT_R_MGG_FIFO_RPTR_8814B 8 -#define BIT_MASK_R_MGG_FIFO_RPTR_8814B 0x1f -#define BIT_R_MGG_FIFO_RPTR_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8814B) << BIT_SHIFT_R_MGG_FIFO_RPTR_8814B) -#define BIT_GET_R_MGG_FIFO_RPTR_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8814B) & BIT_MASK_R_MGG_FIFO_RPTR_8814B) +/* 2 REG_HW_SEQ2_8814B */ +#define BIT_SHIFT_HW_SSN_SEQ2_8814B 0 +#define BIT_MASK_HW_SSN_SEQ2_8814B 0xfff +#define BIT_HW_SSN_SEQ2_8814B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ2_8814B) << BIT_SHIFT_HW_SSN_SEQ2_8814B) +#define BITS_HW_SSN_SEQ2_8814B \ + (BIT_MASK_HW_SSN_SEQ2_8814B << BIT_SHIFT_HW_SSN_SEQ2_8814B) +#define BIT_CLEAR_HW_SSN_SEQ2_8814B(x) ((x) & (~BITS_HW_SSN_SEQ2_8814B)) +#define BIT_GET_HW_SSN_SEQ2_8814B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8814B) & BIT_MASK_HW_SSN_SEQ2_8814B) +#define BIT_SET_HW_SSN_SEQ2_8814B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ2_8814B(x) | BIT_HW_SSN_SEQ2_8814B(v)) -#define BIT_R_MGG_FIFO_OV_8814B BIT(7) -#define BIT_R_MGG_FIFO_WPTR_ERROR_8814B BIT(6) -#define BIT_R_EN_CPU_LIFETIME_8814B BIT(5) +/* 2 REG_HW_SEQ3_8814B */ -#define BIT_SHIFT_R_MGG_FIFO_WPTR_8814B 0 -#define BIT_MASK_R_MGG_FIFO_WPTR_8814B 0x1f -#define BIT_R_MGG_FIFO_WPTR_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8814B) << BIT_SHIFT_R_MGG_FIFO_WPTR_8814B) -#define BIT_GET_R_MGG_FIFO_WPTR_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8814B) & BIT_MASK_R_MGG_FIFO_WPTR_8814B) +#define BIT_SHIFT_CSI_HWSEQ_SEL_8814B 12 +#define BIT_MASK_CSI_HWSEQ_SEL_8814B 0x3 +#define BIT_CSI_HWSEQ_SEL_8814B(x) \ + (((x) & BIT_MASK_CSI_HWSEQ_SEL_8814B) << BIT_SHIFT_CSI_HWSEQ_SEL_8814B) +#define BITS_CSI_HWSEQ_SEL_8814B \ + (BIT_MASK_CSI_HWSEQ_SEL_8814B << BIT_SHIFT_CSI_HWSEQ_SEL_8814B) +#define BIT_CLEAR_CSI_HWSEQ_SEL_8814B(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8814B)) +#define BIT_GET_CSI_HWSEQ_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8814B) & BIT_MASK_CSI_HWSEQ_SEL_8814B) +#define BIT_SET_CSI_HWSEQ_SEL_8814B(x, v) \ + (BIT_CLEAR_CSI_HWSEQ_SEL_8814B(x) | BIT_CSI_HWSEQ_SEL_8814B(v)) +#define BIT_SHIFT_HW_SSN_SEQ3_8814B 0 +#define BIT_MASK_HW_SSN_SEQ3_8814B 0xfff +#define BIT_HW_SSN_SEQ3_8814B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ3_8814B) << BIT_SHIFT_HW_SSN_SEQ3_8814B) +#define BITS_HW_SSN_SEQ3_8814B \ + (BIT_MASK_HW_SSN_SEQ3_8814B << BIT_SHIFT_HW_SSN_SEQ3_8814B) +#define BIT_CLEAR_HW_SSN_SEQ3_8814B(x) ((x) & (~BITS_HW_SSN_SEQ3_8814B)) +#define BIT_GET_HW_SSN_SEQ3_8814B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8814B) & BIT_MASK_HW_SSN_SEQ3_8814B) +#define BIT_SET_HW_SSN_SEQ3_8814B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ3_8814B(x) | BIT_HW_SSN_SEQ3_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_MGG_FIFO_INT_8814B */ +#define BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B 0 +#define BIT_MASK_PTCL_TOTAL_PG_V3_8814B 0x1fff +#define BIT_PTCL_TOTAL_PG_V3_8814B(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V3_8814B) \ + << BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B) +#define BITS_PTCL_TOTAL_PG_V3_8814B \ + (BIT_MASK_PTCL_TOTAL_PG_V3_8814B << BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B) +#define BIT_CLEAR_PTCL_TOTAL_PG_V3_8814B(x) \ + ((x) & (~BITS_PTCL_TOTAL_PG_V3_8814B)) +#define BIT_GET_PTCL_TOTAL_PG_V3_8814B(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B) & \ + BIT_MASK_PTCL_TOTAL_PG_V3_8814B) +#define BIT_SET_PTCL_TOTAL_PG_V3_8814B(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V3_8814B(x) | BIT_PTCL_TOTAL_PG_V3_8814B(v)) + +/* 2 REG_PTCL_ERR_STATUS_V1_8814B */ +#define BIT_MUARB_SEARCH_ERR_8814B BIT(14) +#define BIT_MU_BFEN_ERR_8814B BIT(12) +#define BIT_NDPA_DROPNULL_ERR_8814B BIT(11) +#define BIT_NDPA_DROPPKT_ERR_8814B BIT(10) +#define BIT_PTCL_PKYIN_ERR_8814B BIT(9) +#define BIT_PTCL_QSELCNL_ERR_8814B BIT(8) +#define BIT_PTCL_RATE_TABLE_INVALID_8814B BIT(7) +#define BIT_FTM_T2R_ERROR_8814B BIT(6) +#define BIT_TXTIMEOUT_ERR_8814B BIT(5) +#define BIT_NULLPAGE_ERR_8814B BIT(4) +#define BIT_CONTENTION_ERR_8814B BIT(3) +#define BIT_HEADNULL_ERR_8814B BIT(2) +#define BIT_OVERFLOW_ERR_8814B BIT(1) +#define BIT_QUEUE_INDEX_ERR_8814B BIT(0) + +/* 2 REG_NULL_PKT_STATUS_V2_8814B */ +#define BIT_HIQ_DROP_8814B BIT(7) +#define BIT_MGQ_DROP_8814B BIT(6) +#define BIT_TX_NULL_1_V1_8814B BIT(1) +#define BIT_TX_NULL_0_V1_8814B BIT(0) + +/* 2 REG_PRECNT_CTRL_8814B */ +#define BIT_EN_PRECNT_8814B BIT(11) + +#define BIT_SHIFT_PRECNT_TH_8814B 0 +#define BIT_MASK_PRECNT_TH_8814B 0x7ff +#define BIT_PRECNT_TH_8814B(x) \ + (((x) & BIT_MASK_PRECNT_TH_8814B) << BIT_SHIFT_PRECNT_TH_8814B) +#define BITS_PRECNT_TH_8814B \ + (BIT_MASK_PRECNT_TH_8814B << BIT_SHIFT_PRECNT_TH_8814B) +#define BIT_CLEAR_PRECNT_TH_8814B(x) ((x) & (~BITS_PRECNT_TH_8814B)) +#define BIT_GET_PRECNT_TH_8814B(x) \ + (((x) >> BIT_SHIFT_PRECNT_TH_8814B) & BIT_MASK_PRECNT_TH_8814B) +#define BIT_SET_PRECNT_TH_8814B(x, v) \ + (BIT_CLEAR_PRECNT_TH_8814B(x) | BIT_PRECNT_TH_8814B(v)) + +/* 2 REG_NULL_PKT_STATUS_EXTEND_V1_8814B */ +#define BIT_CLI3_TX_NULL_1_V1_8814B BIT(7) +#define BIT_CLI3_TX_NULL_0_V1_8814B BIT(6) +#define BIT_CLI2_TX_NULL_1_V1_8814B BIT(5) +#define BIT_CLI2_TX_NULL_0_V1_8814B BIT(4) +#define BIT_CLI1_TX_NULL_1_V1_8814B BIT(3) +#define BIT_CLI1_TX_NULL_0_V1_8814B BIT(2) +#define BIT_CLI0_TX_NULL_1_V1_8814B BIT(1) +#define BIT_CLI0_TX_NULL_0_V1_8814B BIT(0) -#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8814B 16 -#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8814B 0xffff -#define BIT_R_MGG_FIFO_INT_FLAG_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8814B) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8814B) -#define BIT_GET_R_MGG_FIFO_INT_FLAG_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8814B) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_PTCL_DBG_V1_8814B */ -#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8814B 0 -#define BIT_MASK_R_MGG_FIFO_INT_MASK_8814B 0xffff -#define BIT_R_MGG_FIFO_INT_MASK_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8814B) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8814B) -#define BIT_GET_R_MGG_FIFO_INT_MASK_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8814B) & BIT_MASK_R_MGG_FIFO_INT_MASK_8814B) +#define BIT_SHIFT_PTCL_DBG_8814B 0 +#define BIT_MASK_PTCL_DBG_8814B 0xffffffffL +#define BIT_PTCL_DBG_8814B(x) \ + (((x) & BIT_MASK_PTCL_DBG_8814B) << BIT_SHIFT_PTCL_DBG_8814B) +#define BITS_PTCL_DBG_8814B \ + (BIT_MASK_PTCL_DBG_8814B << BIT_SHIFT_PTCL_DBG_8814B) +#define BIT_CLEAR_PTCL_DBG_8814B(x) ((x) & (~BITS_PTCL_DBG_8814B)) +#define BIT_GET_PTCL_DBG_8814B(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_8814B) & BIT_MASK_PTCL_DBG_8814B) +#define BIT_SET_PTCL_DBG_8814B(x, v) \ + (BIT_CLEAR_PTCL_DBG_8814B(x) | BIT_PTCL_DBG_8814B(v)) + +/* 2 REG_BT_POLLUTE_PKTCNT_8814B */ + +#define BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B 0 +#define BIT_MASK_BT_POLLUTE_PKTCNT_8814B 0xffff +#define BIT_BT_POLLUTE_PKTCNT_8814B(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKTCNT_8814B) \ + << BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B) +#define BITS_BT_POLLUTE_PKTCNT_8814B \ + (BIT_MASK_BT_POLLUTE_PKTCNT_8814B << BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B) +#define BIT_CLEAR_BT_POLLUTE_PKTCNT_8814B(x) \ + ((x) & (~BITS_BT_POLLUTE_PKTCNT_8814B)) +#define BIT_GET_BT_POLLUTE_PKTCNT_8814B(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B) & \ + BIT_MASK_BT_POLLUTE_PKTCNT_8814B) +#define BIT_SET_BT_POLLUTE_PKTCNT_8814B(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKTCNT_8814B(x) | BIT_BT_POLLUTE_PKTCNT_8814B(v)) +/* 2 REG_CPUMGQ_TIMER_CTRL2_8814B */ +#define BIT_SHIFT_TRI_HEAD_ADDR_8814B 16 +#define BIT_MASK_TRI_HEAD_ADDR_8814B 0xfff +#define BIT_TRI_HEAD_ADDR_8814B(x) \ + (((x) & BIT_MASK_TRI_HEAD_ADDR_8814B) << BIT_SHIFT_TRI_HEAD_ADDR_8814B) +#define BITS_TRI_HEAD_ADDR_8814B \ + (BIT_MASK_TRI_HEAD_ADDR_8814B << BIT_SHIFT_TRI_HEAD_ADDR_8814B) +#define BIT_CLEAR_TRI_HEAD_ADDR_8814B(x) ((x) & (~BITS_TRI_HEAD_ADDR_8814B)) +#define BIT_GET_TRI_HEAD_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8814B) & BIT_MASK_TRI_HEAD_ADDR_8814B) +#define BIT_SET_TRI_HEAD_ADDR_8814B(x, v) \ + (BIT_CLEAR_TRI_HEAD_ADDR_8814B(x) | BIT_TRI_HEAD_ADDR_8814B(v)) -/* 2 REG_MGG_FIFO_LIFETIME_8814B */ +#define BIT_DROP_TH_EN_8814B BIT(8) -#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8814B 16 -#define BIT_MASK_R_MGG_FIFO_LIFETIME_8814B 0xffff -#define BIT_R_MGG_FIFO_LIFETIME_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8814B) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8814B) -#define BIT_GET_R_MGG_FIFO_LIFETIME_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8814B) & BIT_MASK_R_MGG_FIFO_LIFETIME_8814B) +#define BIT_SHIFT_DROP_TH_8814B 0 +#define BIT_MASK_DROP_TH_8814B 0xff +#define BIT_DROP_TH_8814B(x) \ + (((x) & BIT_MASK_DROP_TH_8814B) << BIT_SHIFT_DROP_TH_8814B) +#define BITS_DROP_TH_8814B (BIT_MASK_DROP_TH_8814B << BIT_SHIFT_DROP_TH_8814B) +#define BIT_CLEAR_DROP_TH_8814B(x) ((x) & (~BITS_DROP_TH_8814B)) +#define BIT_GET_DROP_TH_8814B(x) \ + (((x) >> BIT_SHIFT_DROP_TH_8814B) & BIT_MASK_DROP_TH_8814B) +#define BIT_SET_DROP_TH_8814B(x, v) \ + (BIT_CLEAR_DROP_TH_8814B(x) | BIT_DROP_TH_8814B(v)) + +/* 2 REG_PTCL_DBG_OUT_8814B */ + +#define BIT_SHIFT_PTCL_DBG_OUT_8814B 0 +#define BIT_MASK_PTCL_DBG_OUT_8814B 0xffffffffL +#define BIT_PTCL_DBG_OUT_8814B(x) \ + (((x) & BIT_MASK_PTCL_DBG_OUT_8814B) << BIT_SHIFT_PTCL_DBG_OUT_8814B) +#define BITS_PTCL_DBG_OUT_8814B \ + (BIT_MASK_PTCL_DBG_OUT_8814B << BIT_SHIFT_PTCL_DBG_OUT_8814B) +#define BIT_CLEAR_PTCL_DBG_OUT_8814B(x) ((x) & (~BITS_PTCL_DBG_OUT_8814B)) +#define BIT_GET_PTCL_DBG_OUT_8814B(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_OUT_8814B) & BIT_MASK_PTCL_DBG_OUT_8814B) +#define BIT_SET_PTCL_DBG_OUT_8814B(x, v) \ + (BIT_CLEAR_PTCL_DBG_OUT_8814B(x) | BIT_PTCL_DBG_OUT_8814B(v)) +/* 2 REG_DUMMY_PAGE4_V1_8814B */ +/* 2 REG_DUMMY_PAGE4_1_8814B */ + +/* 2 REG_MU_OFFSET_8814B */ + +#define BIT_SHIFT_MU_RATETABLE_OFFSET_8814B 16 +#define BIT_MASK_MU_RATETABLE_OFFSET_8814B 0x1ff +#define BIT_MU_RATETABLE_OFFSET_8814B(x) \ + (((x) & BIT_MASK_MU_RATETABLE_OFFSET_8814B) \ + << BIT_SHIFT_MU_RATETABLE_OFFSET_8814B) +#define BITS_MU_RATETABLE_OFFSET_8814B \ + (BIT_MASK_MU_RATETABLE_OFFSET_8814B \ + << BIT_SHIFT_MU_RATETABLE_OFFSET_8814B) +#define BIT_CLEAR_MU_RATETABLE_OFFSET_8814B(x) \ + ((x) & (~BITS_MU_RATETABLE_OFFSET_8814B)) +#define BIT_GET_MU_RATETABLE_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_MU_RATETABLE_OFFSET_8814B) & \ + BIT_MASK_MU_RATETABLE_OFFSET_8814B) +#define BIT_SET_MU_RATETABLE_OFFSET_8814B(x, v) \ + (BIT_CLEAR_MU_RATETABLE_OFFSET_8814B(x) | \ + BIT_MU_RATETABLE_OFFSET_8814B(v)) + +#define BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B 0 +#define BIT_MASK_MU_SCORETABLE_OFFSET_8814B 0x1ff +#define BIT_MU_SCORETABLE_OFFSET_8814B(x) \ + (((x) & BIT_MASK_MU_SCORETABLE_OFFSET_8814B) \ + << BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B) +#define BITS_MU_SCORETABLE_OFFSET_8814B \ + (BIT_MASK_MU_SCORETABLE_OFFSET_8814B \ + << BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B) +#define BIT_CLEAR_MU_SCORETABLE_OFFSET_8814B(x) \ + ((x) & (~BITS_MU_SCORETABLE_OFFSET_8814B)) +#define BIT_GET_MU_SCORETABLE_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B) & \ + BIT_MASK_MU_SCORETABLE_OFFSET_8814B) +#define BIT_SET_MU_SCORETABLE_OFFSET_8814B(x, v) \ + (BIT_CLEAR_MU_SCORETABLE_OFFSET_8814B(x) | \ + BIT_MU_SCORETABLE_OFFSET_8814B(v)) -#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8814B 0 -#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8814B 0xffff -#define BIT_R_MGG_FIFO_VALID_MAP_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8814B) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8814B) -#define BIT_GET_R_MGG_FIFO_VALID_MAP_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8814B) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8814B) +/* 2 REG_USEREG_SETTING_8814B */ +/* 2 REG_BF0_TIME_SETTING_8814B */ +#define BIT_BF0_TIMER_SET_8814B BIT(31) +#define BIT_BF0_TIMER_CLR_8814B BIT(30) +#define BIT_BF0_UPDATE_EN_8814B BIT(29) +#define BIT_BF0_TIMER_EN_8814B BIT(28) +#define BIT_SHIFT_BF0_PRETIME_OVER_8814B 16 +#define BIT_MASK_BF0_PRETIME_OVER_8814B 0xfff +#define BIT_BF0_PRETIME_OVER_8814B(x) \ + (((x) & BIT_MASK_BF0_PRETIME_OVER_8814B) \ + << BIT_SHIFT_BF0_PRETIME_OVER_8814B) +#define BITS_BF0_PRETIME_OVER_8814B \ + (BIT_MASK_BF0_PRETIME_OVER_8814B << BIT_SHIFT_BF0_PRETIME_OVER_8814B) +#define BIT_CLEAR_BF0_PRETIME_OVER_8814B(x) \ + ((x) & (~BITS_BF0_PRETIME_OVER_8814B)) +#define BIT_GET_BF0_PRETIME_OVER_8814B(x) \ + (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8814B) & \ + BIT_MASK_BF0_PRETIME_OVER_8814B) +#define BIT_SET_BF0_PRETIME_OVER_8814B(x, v) \ + (BIT_CLEAR_BF0_PRETIME_OVER_8814B(x) | BIT_BF0_PRETIME_OVER_8814B(v)) -/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B */ +#define BIT_SHIFT_BF0_LIFETIME_8814B 0 +#define BIT_MASK_BF0_LIFETIME_8814B 0xffff +#define BIT_BF0_LIFETIME_8814B(x) \ + (((x) & BIT_MASK_BF0_LIFETIME_8814B) << BIT_SHIFT_BF0_LIFETIME_8814B) +#define BITS_BF0_LIFETIME_8814B \ + (BIT_MASK_BF0_LIFETIME_8814B << BIT_SHIFT_BF0_LIFETIME_8814B) +#define BIT_CLEAR_BF0_LIFETIME_8814B(x) ((x) & (~BITS_BF0_LIFETIME_8814B)) +#define BIT_GET_BF0_LIFETIME_8814B(x) \ + (((x) >> BIT_SHIFT_BF0_LIFETIME_8814B) & BIT_MASK_BF0_LIFETIME_8814B) +#define BIT_SET_BF0_LIFETIME_8814B(x, v) \ + (BIT_CLEAR_BF0_LIFETIME_8814B(x) | BIT_BF0_LIFETIME_8814B(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B 0x7f -#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B) +/* 2 REG_BF1_TIME_SETTING_8814B */ +#define BIT_BF1_TIMER_SET_8814B BIT(31) +#define BIT_BF1_TIMER_CLR_8814B BIT(30) +#define BIT_BF1_UPDATE_EN_8814B BIT(29) +#define BIT_BF1_TIMER_EN_8814B BIT(28) +#define BIT_SHIFT_BF1_PRETIME_OVER_8814B 16 +#define BIT_MASK_BF1_PRETIME_OVER_8814B 0xfff +#define BIT_BF1_PRETIME_OVER_8814B(x) \ + (((x) & BIT_MASK_BF1_PRETIME_OVER_8814B) \ + << BIT_SHIFT_BF1_PRETIME_OVER_8814B) +#define BITS_BF1_PRETIME_OVER_8814B \ + (BIT_MASK_BF1_PRETIME_OVER_8814B << BIT_SHIFT_BF1_PRETIME_OVER_8814B) +#define BIT_CLEAR_BF1_PRETIME_OVER_8814B(x) \ + ((x) & (~BITS_BF1_PRETIME_OVER_8814B)) +#define BIT_GET_BF1_PRETIME_OVER_8814B(x) \ + (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8814B) & \ + BIT_MASK_BF1_PRETIME_OVER_8814B) +#define BIT_SET_BF1_PRETIME_OVER_8814B(x, v) \ + (BIT_CLEAR_BF1_PRETIME_OVER_8814B(x) | BIT_BF1_PRETIME_OVER_8814B(v)) +#define BIT_SHIFT_BF1_LIFETIME_8814B 0 +#define BIT_MASK_BF1_LIFETIME_8814B 0xffff +#define BIT_BF1_LIFETIME_8814B(x) \ + (((x) & BIT_MASK_BF1_LIFETIME_8814B) << BIT_SHIFT_BF1_LIFETIME_8814B) +#define BITS_BF1_LIFETIME_8814B \ + (BIT_MASK_BF1_LIFETIME_8814B << BIT_SHIFT_BF1_LIFETIME_8814B) +#define BIT_CLEAR_BF1_LIFETIME_8814B(x) ((x) & (~BITS_BF1_LIFETIME_8814B)) +#define BIT_GET_BF1_LIFETIME_8814B(x) \ + (((x) >> BIT_SHIFT_BF1_LIFETIME_8814B) & BIT_MASK_BF1_LIFETIME_8814B) +#define BIT_SET_BF1_LIFETIME_8814B(x, v) \ + (BIT_CLEAR_BF1_LIFETIME_8814B(x) | BIT_BF1_LIFETIME_8814B(v)) -/* 2 REG_MU_TX_CTL_8814B (NOT SUPPORT) */ -#define BIT_R_FORCE_P1_RATEDOWN_8814B BIT(11) +/* 2 REG_BF_TIMEOUT_EN_8814B */ +#define BIT_EN_VHT_LDPC_8814B BIT(9) +#define BIT_EN_HT_LDPC_8814B BIT(8) +#define BIT_BF1_TIMEOUT_EN_8814B BIT(1) +#define BIT_BF0_TIMEOUT_EN_8814B BIT(0) -#define BIT_SHIFT_R_MU_TAB_SEL_8814B 8 -#define BIT_MASK_R_MU_TAB_SEL_8814B 0x7 -#define BIT_R_MU_TAB_SEL_8814B(x) (((x) & BIT_MASK_R_MU_TAB_SEL_8814B) << BIT_SHIFT_R_MU_TAB_SEL_8814B) -#define BIT_GET_R_MU_TAB_SEL_8814B(x) (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8814B) & BIT_MASK_R_MU_TAB_SEL_8814B) +/* 2 REG_MACID_RELEASE_INFO_8814B */ + +#define BIT_SHIFT_MACID_RELEASE_INFO_8814B 0 +#define BIT_MASK_MACID_RELEASE_INFO_8814B 0xffffffffL +#define BIT_MACID_RELEASE_INFO_8814B(x) \ + (((x) & BIT_MASK_MACID_RELEASE_INFO_8814B) \ + << BIT_SHIFT_MACID_RELEASE_INFO_8814B) +#define BITS_MACID_RELEASE_INFO_8814B \ + (BIT_MASK_MACID_RELEASE_INFO_8814B \ + << BIT_SHIFT_MACID_RELEASE_INFO_8814B) +#define BIT_CLEAR_MACID_RELEASE_INFO_8814B(x) \ + ((x) & (~BITS_MACID_RELEASE_INFO_8814B)) +#define BIT_GET_MACID_RELEASE_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_INFO_8814B) & \ + BIT_MASK_MACID_RELEASE_INFO_8814B) +#define BIT_SET_MACID_RELEASE_INFO_8814B(x, v) \ + (BIT_CLEAR_MACID_RELEASE_INFO_8814B(x) | \ + BIT_MACID_RELEASE_INFO_8814B(v)) + +/* 2 REG_MACID_RELEASE_SUCCESS_INFO_8814B */ + +#define BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B 0 +#define BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B 0xffffffffL +#define BIT_MACID_RELEASE_SUCCESS_INFO_8814B(x) \ + (((x) & BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B) \ + << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B) +#define BITS_MACID_RELEASE_SUCCESS_INFO_8814B \ + (BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B \ + << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B) +#define BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO_8814B(x) \ + ((x) & (~BITS_MACID_RELEASE_SUCCESS_INFO_8814B)) +#define BIT_GET_MACID_RELEASE_SUCCESS_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B) & \ + BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B) +#define BIT_SET_MACID_RELEASE_SUCCESS_INFO_8814B(x, v) \ + (BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO_8814B(x) | \ + BIT_MACID_RELEASE_SUCCESS_INFO_8814B(v)) + +/* 2 REG_MACID_RELEASE_CTRL_8814B */ + +#define BIT_SHIFT_MACID_RELEASE_SEL_8814B 24 +#define BIT_MASK_MACID_RELEASE_SEL_8814B 0x7 +#define BIT_MACID_RELEASE_SEL_8814B(x) \ + (((x) & BIT_MASK_MACID_RELEASE_SEL_8814B) \ + << BIT_SHIFT_MACID_RELEASE_SEL_8814B) +#define BITS_MACID_RELEASE_SEL_8814B \ + (BIT_MASK_MACID_RELEASE_SEL_8814B << BIT_SHIFT_MACID_RELEASE_SEL_8814B) +#define BIT_CLEAR_MACID_RELEASE_SEL_8814B(x) \ + ((x) & (~BITS_MACID_RELEASE_SEL_8814B)) +#define BIT_GET_MACID_RELEASE_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_SEL_8814B) & \ + BIT_MASK_MACID_RELEASE_SEL_8814B) +#define BIT_SET_MACID_RELEASE_SEL_8814B(x, v) \ + (BIT_CLEAR_MACID_RELEASE_SEL_8814B(x) | BIT_MACID_RELEASE_SEL_8814B(v)) + +#define BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B 16 +#define BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B 0xff +#define BIT_MACID_RELEASE_CLEAR_OFFSET_8814B(x) \ + (((x) & BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B) \ + << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B) +#define BITS_MACID_RELEASE_CLEAR_OFFSET_8814B \ + (BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B \ + << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B) +#define BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET_8814B(x) \ + ((x) & (~BITS_MACID_RELEASE_CLEAR_OFFSET_8814B)) +#define BIT_GET_MACID_RELEASE_CLEAR_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B) & \ + BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B) +#define BIT_SET_MACID_RELEASE_CLEAR_OFFSET_8814B(x, v) \ + (BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET_8814B(x) | \ + BIT_MACID_RELEASE_CLEAR_OFFSET_8814B(v)) + +#define BIT_MACID_RELEASE_VALUE_8814B BIT(8) + +#define BIT_SHIFT_MACID_RELEASE_OFFSET_8814B 0 +#define BIT_MASK_MACID_RELEASE_OFFSET_8814B 0xff +#define BIT_MACID_RELEASE_OFFSET_8814B(x) \ + (((x) & BIT_MASK_MACID_RELEASE_OFFSET_8814B) \ + << BIT_SHIFT_MACID_RELEASE_OFFSET_8814B) +#define BITS_MACID_RELEASE_OFFSET_8814B \ + (BIT_MASK_MACID_RELEASE_OFFSET_8814B \ + << BIT_SHIFT_MACID_RELEASE_OFFSET_8814B) +#define BIT_CLEAR_MACID_RELEASE_OFFSET_8814B(x) \ + ((x) & (~BITS_MACID_RELEASE_OFFSET_8814B)) +#define BIT_GET_MACID_RELEASE_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_OFFSET_8814B) & \ + BIT_MASK_MACID_RELEASE_OFFSET_8814B) +#define BIT_SET_MACID_RELEASE_OFFSET_8814B(x, v) \ + (BIT_CLEAR_MACID_RELEASE_OFFSET_8814B(x) | \ + BIT_MACID_RELEASE_OFFSET_8814B(v)) +/* 2 REG_FAST_EDCA_VOVI_SETTING_8814B */ -#define BIT_R_EN_MU_MIMO_8814B BIT(7) -#define BIT_R_EN_REVERS_GTAB_8814B BIT(6) +#define BIT_SHIFT_VI_FAST_EDCA_TO_8814B 24 +#define BIT_MASK_VI_FAST_EDCA_TO_8814B 0xff +#define BIT_VI_FAST_EDCA_TO_8814B(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_TO_8814B) \ + << BIT_SHIFT_VI_FAST_EDCA_TO_8814B) +#define BITS_VI_FAST_EDCA_TO_8814B \ + (BIT_MASK_VI_FAST_EDCA_TO_8814B << BIT_SHIFT_VI_FAST_EDCA_TO_8814B) +#define BIT_CLEAR_VI_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8814B)) +#define BIT_GET_VI_FAST_EDCA_TO_8814B(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8814B) & \ + BIT_MASK_VI_FAST_EDCA_TO_8814B) +#define BIT_SET_VI_FAST_EDCA_TO_8814B(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_TO_8814B(x) | BIT_VI_FAST_EDCA_TO_8814B(v)) -#define BIT_SHIFT_R_MU_TABLE_VALID_8814B 0 -#define BIT_MASK_R_MU_TABLE_VALID_8814B 0x3f -#define BIT_R_MU_TABLE_VALID_8814B(x) (((x) & BIT_MASK_R_MU_TABLE_VALID_8814B) << BIT_SHIFT_R_MU_TABLE_VALID_8814B) -#define BIT_GET_R_MU_TABLE_VALID_8814B(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8814B) & BIT_MASK_R_MU_TABLE_VALID_8814B) +#define BIT_VI_THRESHOLD_SEL_8814B BIT(23) +#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B 16 +#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B 0x7f +#define BIT_VI_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B) \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) +#define BITS_VI_FAST_EDCA_PKT_TH_8814B \ + (BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8814B(x) \ + ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8814B)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) & \ + BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B) +#define BIT_SET_VI_FAST_EDCA_PKT_TH_8814B(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8814B(x) | \ + BIT_VI_FAST_EDCA_PKT_TH_8814B(v)) +#define BIT_SHIFT_VO_FAST_EDCA_TO_8814B 8 +#define BIT_MASK_VO_FAST_EDCA_TO_8814B 0xff +#define BIT_VO_FAST_EDCA_TO_8814B(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO_8814B) \ + << BIT_SHIFT_VO_FAST_EDCA_TO_8814B) +#define BITS_VO_FAST_EDCA_TO_8814B \ + (BIT_MASK_VO_FAST_EDCA_TO_8814B << BIT_SHIFT_VO_FAST_EDCA_TO_8814B) +#define BIT_CLEAR_VO_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8814B)) +#define BIT_GET_VO_FAST_EDCA_TO_8814B(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8814B) & \ + BIT_MASK_VO_FAST_EDCA_TO_8814B) +#define BIT_SET_VO_FAST_EDCA_TO_8814B(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO_8814B(x) | BIT_VO_FAST_EDCA_TO_8814B(v)) -/* 2 REG_MU_STA_GID_VLD_8814B (NOT SUPPORT) */ +#define BIT_VO_THRESHOLD_SEL_8814B BIT(7) -/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B 0 +#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B 0x7f +#define BIT_VO_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B) \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) +#define BITS_VO_FAST_EDCA_PKT_TH_8814B \ + (BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8814B(x) \ + ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8814B)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) & \ + BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B) +#define BIT_SET_VO_FAST_EDCA_PKT_TH_8814B(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8814B(x) | \ + BIT_VO_FAST_EDCA_PKT_TH_8814B(v)) -#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B 0 -#define BIT_MASK_R_MU_STA_GTAB_VALID_8814B 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID_8814B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8814B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B) -#define BIT_GET_R_MU_STA_GTAB_VALID_8814B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B) & BIT_MASK_R_MU_STA_GTAB_VALID_8814B) +/* 2 REG_FAST_EDCA_BEBK_SETTING_8814B */ +#define BIT_SHIFT_BK_FAST_EDCA_TO_8814B 24 +#define BIT_MASK_BK_FAST_EDCA_TO_8814B 0xff +#define BIT_BK_FAST_EDCA_TO_8814B(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_TO_8814B) \ + << BIT_SHIFT_BK_FAST_EDCA_TO_8814B) +#define BITS_BK_FAST_EDCA_TO_8814B \ + (BIT_MASK_BK_FAST_EDCA_TO_8814B << BIT_SHIFT_BK_FAST_EDCA_TO_8814B) +#define BIT_CLEAR_BK_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8814B)) +#define BIT_GET_BK_FAST_EDCA_TO_8814B(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8814B) & \ + BIT_MASK_BK_FAST_EDCA_TO_8814B) +#define BIT_SET_BK_FAST_EDCA_TO_8814B(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_TO_8814B(x) | BIT_BK_FAST_EDCA_TO_8814B(v)) +#define BIT_BK_THRESHOLD_SEL_8814B BIT(23) -#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B 0 -#define BIT_MASK_R_MU_STA_GTAB_VALID_8814B 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID_8814B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8814B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B) -#define BIT_GET_R_MU_STA_GTAB_VALID_8814B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B) & BIT_MASK_R_MU_STA_GTAB_VALID_8814B) +#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B 16 +#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B 0x7f +#define BIT_BK_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B) \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) +#define BITS_BK_FAST_EDCA_PKT_TH_8814B \ + (BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8814B(x) \ + ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8814B)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) & \ + BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B) +#define BIT_SET_BK_FAST_EDCA_PKT_TH_8814B(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8814B(x) | \ + BIT_BK_FAST_EDCA_PKT_TH_8814B(v)) +#define BIT_SHIFT_BE_FAST_EDCA_TO_8814B 8 +#define BIT_MASK_BE_FAST_EDCA_TO_8814B 0xff +#define BIT_BE_FAST_EDCA_TO_8814B(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO_8814B) \ + << BIT_SHIFT_BE_FAST_EDCA_TO_8814B) +#define BITS_BE_FAST_EDCA_TO_8814B \ + (BIT_MASK_BE_FAST_EDCA_TO_8814B << BIT_SHIFT_BE_FAST_EDCA_TO_8814B) +#define BIT_CLEAR_BE_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8814B)) +#define BIT_GET_BE_FAST_EDCA_TO_8814B(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8814B) & \ + BIT_MASK_BE_FAST_EDCA_TO_8814B) +#define BIT_SET_BE_FAST_EDCA_TO_8814B(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO_8814B(x) | BIT_BE_FAST_EDCA_TO_8814B(v)) +#define BIT_BE_THRESHOLD_SEL_8814B BIT(7) -/* 2 REG_MU_STA_USER_POS_INFO_8814B (NOT SUPPORT) */ +#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B 0 +#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B 0x7f +#define BIT_BE_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B) \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) +#define BITS_BE_FAST_EDCA_PKT_TH_8814B \ + (BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8814B(x) \ + ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8814B)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) & \ + BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B) +#define BIT_SET_BE_FAST_EDCA_PKT_TH_8814B(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8814B(x) | \ + BIT_BE_FAST_EDCA_PKT_TH_8814B(v)) + +/* 2 REG_MACID_DROP_INFO_8814B */ + +#define BIT_SHIFT_MACID_DROP_INFO_8814B 0 +#define BIT_MASK_MACID_DROP_INFO_8814B 0xffffffffL +#define BIT_MACID_DROP_INFO_8814B(x) \ + (((x) & BIT_MASK_MACID_DROP_INFO_8814B) \ + << BIT_SHIFT_MACID_DROP_INFO_8814B) +#define BITS_MACID_DROP_INFO_8814B \ + (BIT_MASK_MACID_DROP_INFO_8814B << BIT_SHIFT_MACID_DROP_INFO_8814B) +#define BIT_CLEAR_MACID_DROP_INFO_8814B(x) ((x) & (~BITS_MACID_DROP_INFO_8814B)) +#define BIT_GET_MACID_DROP_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_DROP_INFO_8814B) & \ + BIT_MASK_MACID_DROP_INFO_8814B) +#define BIT_SET_MACID_DROP_INFO_8814B(x, v) \ + (BIT_CLEAR_MACID_DROP_INFO_8814B(x) | BIT_MACID_DROP_INFO_8814B(v)) + +/* 2 REG_MACID_DROP_CTRL_8814B */ + +#define BIT_SHIFT_MACID_DROP_SEL_8814B 0 +#define BIT_MASK_MACID_DROP_SEL_8814B 0x7 +#define BIT_MACID_DROP_SEL_8814B(x) \ + (((x) & BIT_MASK_MACID_DROP_SEL_8814B) \ + << BIT_SHIFT_MACID_DROP_SEL_8814B) +#define BITS_MACID_DROP_SEL_8814B \ + (BIT_MASK_MACID_DROP_SEL_8814B << BIT_SHIFT_MACID_DROP_SEL_8814B) +#define BIT_CLEAR_MACID_DROP_SEL_8814B(x) ((x) & (~BITS_MACID_DROP_SEL_8814B)) +#define BIT_GET_MACID_DROP_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_DROP_SEL_8814B) & \ + BIT_MASK_MACID_DROP_SEL_8814B) +#define BIT_SET_MACID_DROP_SEL_8814B(x, v) \ + (BIT_CLEAR_MACID_DROP_SEL_8814B(x) | BIT_MACID_DROP_SEL_8814B(v)) + +/* 2 REG_MGQ_FIFO_WRITE_POINTER_8814B */ +#define BIT_MGQ_FIFO_OV_8814B BIT(7) +#define BIT_MGQ_FIFO_WPTR_ERROR_8814B BIT(6) +#define BIT_EN_MGQ_FIFO_LIFETIME_8814B BIT(5) + +#define BIT_SHIFT_MGQ_FIFO_WPTR_8814B 0 +#define BIT_MASK_MGQ_FIFO_WPTR_8814B 0x1f +#define BIT_MGQ_FIFO_WPTR_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_WPTR_8814B) << BIT_SHIFT_MGQ_FIFO_WPTR_8814B) +#define BITS_MGQ_FIFO_WPTR_8814B \ + (BIT_MASK_MGQ_FIFO_WPTR_8814B << BIT_SHIFT_MGQ_FIFO_WPTR_8814B) +#define BIT_CLEAR_MGQ_FIFO_WPTR_8814B(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8814B)) +#define BIT_GET_MGQ_FIFO_WPTR_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8814B) & BIT_MASK_MGQ_FIFO_WPTR_8814B) +#define BIT_SET_MGQ_FIFO_WPTR_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_WPTR_8814B(x) | BIT_MGQ_FIFO_WPTR_8814B(v)) + +/* 2 REG_MGQ_FIFO_READ_POINTER_8814B */ + +#define BIT_SHIFT_MGQ_FIFO_SIZE_8814B 14 +#define BIT_MASK_MGQ_FIFO_SIZE_8814B 0x3 +#define BIT_MGQ_FIFO_SIZE_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_SIZE_8814B) << BIT_SHIFT_MGQ_FIFO_SIZE_8814B) +#define BITS_MGQ_FIFO_SIZE_8814B \ + (BIT_MASK_MGQ_FIFO_SIZE_8814B << BIT_SHIFT_MGQ_FIFO_SIZE_8814B) +#define BIT_CLEAR_MGQ_FIFO_SIZE_8814B(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8814B)) +#define BIT_GET_MGQ_FIFO_SIZE_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8814B) & BIT_MASK_MGQ_FIFO_SIZE_8814B) +#define BIT_SET_MGQ_FIFO_SIZE_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_SIZE_8814B(x) | BIT_MGQ_FIFO_SIZE_8814B(v)) + +#define BIT_MGQ_FIFO_PAUSE_8814B BIT(13) + +#define BIT_SHIFT_MGQ_FIFO_RPTR_8814B 8 +#define BIT_MASK_MGQ_FIFO_RPTR_8814B 0x1f +#define BIT_MGQ_FIFO_RPTR_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_RPTR_8814B) << BIT_SHIFT_MGQ_FIFO_RPTR_8814B) +#define BITS_MGQ_FIFO_RPTR_8814B \ + (BIT_MASK_MGQ_FIFO_RPTR_8814B << BIT_SHIFT_MGQ_FIFO_RPTR_8814B) +#define BIT_CLEAR_MGQ_FIFO_RPTR_8814B(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8814B)) +#define BIT_GET_MGQ_FIFO_RPTR_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8814B) & BIT_MASK_MGQ_FIFO_RPTR_8814B) +#define BIT_SET_MGQ_FIFO_RPTR_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_RPTR_8814B(x) | BIT_MGQ_FIFO_RPTR_8814B(v)) + +/* 2 REG_MGQ_FIFO_ENABLE_8814B */ +#define BIT_MGQ_FIFO_EN_V1_8814B BIT(15) + +#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B 12 +#define BIT_MASK_MGQ_FIFO_PG_SIZE_8814B 0x7 +#define BIT_MGQ_FIFO_PG_SIZE_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8814B) \ + << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B) +#define BITS_MGQ_FIFO_PG_SIZE_8814B \ + (BIT_MASK_MGQ_FIFO_PG_SIZE_8814B << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B) +#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8814B(x) \ + ((x) & (~BITS_MGQ_FIFO_PG_SIZE_8814B)) +#define BIT_GET_MGQ_FIFO_PG_SIZE_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B) & \ + BIT_MASK_MGQ_FIFO_PG_SIZE_8814B) +#define BIT_SET_MGQ_FIFO_PG_SIZE_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PG_SIZE_8814B(x) | BIT_MGQ_FIFO_PG_SIZE_8814B(v)) + +#define BIT_SHIFT_MGQ_FIFO_START_PG_8814B 0 +#define BIT_MASK_MGQ_FIFO_START_PG_8814B 0xfff +#define BIT_MGQ_FIFO_START_PG_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_START_PG_8814B) \ + << BIT_SHIFT_MGQ_FIFO_START_PG_8814B) +#define BITS_MGQ_FIFO_START_PG_8814B \ + (BIT_MASK_MGQ_FIFO_START_PG_8814B << BIT_SHIFT_MGQ_FIFO_START_PG_8814B) +#define BIT_CLEAR_MGQ_FIFO_START_PG_8814B(x) \ + ((x) & (~BITS_MGQ_FIFO_START_PG_8814B)) +#define BIT_GET_MGQ_FIFO_START_PG_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8814B) & \ + BIT_MASK_MGQ_FIFO_START_PG_8814B) +#define BIT_SET_MGQ_FIFO_START_PG_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_START_PG_8814B(x) | BIT_MGQ_FIFO_START_PG_8814B(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8814B */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B 0xffff +#define BIT_MGQ_FIFO_REL_INT_MASK_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B) +#define BITS_MGQ_FIFO_REL_INT_MASK_8814B \ + (BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8814B(x) \ + ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8814B)) +#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B) & \ + BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B) +#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8814B(x) | \ + BIT_MGQ_FIFO_REL_INT_MASK_8814B(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8814B */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B 0xffff +#define BIT_MGQ_FIFO_REL_INT_FLAG_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B) +#define BITS_MGQ_FIFO_REL_INT_FLAG_8814B \ + (BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8814B(x) \ + ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8814B)) +#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B) & \ + BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B) +#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8814B(x) | \ + BIT_MGQ_FIFO_REL_INT_FLAG_8814B(v)) + +/* 2 REG_MGQ_FIFO_VALID_MAP_8814B */ + +#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B 0 +#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B 0xffff +#define BIT_MGQ_FIFO_PKT_VALID_MAP_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B) \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B) +#define BITS_MGQ_FIFO_PKT_VALID_MAP_8814B \ + (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B) +#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8814B(x) \ + ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8814B)) +#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B) & \ + BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B) +#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8814B(x) | \ + BIT_MGQ_FIFO_PKT_VALID_MAP_8814B(v)) + +/* 2 REG_MGQ_FIFO_LIFETIME_8814B */ + +#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B 0 +#define BIT_MASK_MGQ_FIFO_LIFETIME_8814B 0xffff +#define BIT_MGQ_FIFO_LIFETIME_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8814B) \ + << BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B) +#define BITS_MGQ_FIFO_LIFETIME_8814B \ + (BIT_MASK_MGQ_FIFO_LIFETIME_8814B << BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B) +#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8814B(x) \ + ((x) & (~BITS_MGQ_FIFO_LIFETIME_8814B)) +#define BIT_GET_MGQ_FIFO_LIFETIME_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B) & \ + BIT_MASK_MGQ_FIFO_LIFETIME_8814B) +#define BIT_SET_MGQ_FIFO_LIFETIME_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_LIFETIME_8814B(x) | BIT_MGQ_FIFO_LIFETIME_8814B(v)) /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B 0 -#define BIT_MASK_R_MU_STA_GTAB_POSITION_8814B 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION_8814B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8814B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B) -#define BIT_GET_R_MU_STA_GTAB_POSITION_8814B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8814B) - - - -#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B 0 -#define BIT_MASK_R_MU_STA_GTAB_POSITION_8814B 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION_8814B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8814B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B) -#define BIT_GET_R_MU_STA_GTAB_POSITION_8814B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8814B) +/* 2 REG_PKT_TRANS_8814B */ + +#define BIT_SHIFT_IE_DESC_OFFSET_8814B 16 +#define BIT_MASK_IE_DESC_OFFSET_8814B 0x1ff +#define BIT_IE_DESC_OFFSET_8814B(x) \ + (((x) & BIT_MASK_IE_DESC_OFFSET_8814B) \ + << BIT_SHIFT_IE_DESC_OFFSET_8814B) +#define BITS_IE_DESC_OFFSET_8814B \ + (BIT_MASK_IE_DESC_OFFSET_8814B << BIT_SHIFT_IE_DESC_OFFSET_8814B) +#define BIT_CLEAR_IE_DESC_OFFSET_8814B(x) ((x) & (~BITS_IE_DESC_OFFSET_8814B)) +#define BIT_GET_IE_DESC_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_IE_DESC_OFFSET_8814B) & \ + BIT_MASK_IE_DESC_OFFSET_8814B) +#define BIT_SET_IE_DESC_OFFSET_8814B(x, v) \ + (BIT_CLEAR_IE_DESC_OFFSET_8814B(x) | BIT_IE_DESC_OFFSET_8814B(v)) + +#define BIT_DIS_FWCMD_PATH_ERRCHK_8814B BIT(13) +#define BIT_MAC_HDR_CONVERT_EN_8814B BIT(12) +#define BIT_TXDESC_TRANS_EN_8814B BIT(8) +#define BIT_PKT_TRANS_ERRINT_EN_8814B BIT(7) + +#define BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B 4 +#define BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B 0x3 +#define BIT_PKT_TRANS_ERR_MACID_SEL_8814B(x) \ + (((x) & BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B) \ + << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B) +#define BITS_PKT_TRANS_ERR_MACID_SEL_8814B \ + (BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B \ + << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B) +#define BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL_8814B(x) \ + ((x) & (~BITS_PKT_TRANS_ERR_MACID_SEL_8814B)) +#define BIT_GET_PKT_TRANS_ERR_MACID_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B) & \ + BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B) +#define BIT_SET_PKT_TRANS_ERR_MACID_SEL_8814B(x, v) \ + (BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL_8814B(x) | \ + BIT_PKT_TRANS_ERR_MACID_SEL_8814B(v)) + +#define BIT_PKT_TRANS_IEINIT_ERR_8814B BIT(3) +#define BIT_PKT_TRANS_IENUM_ERR_8814B BIT(2) +#define BIT_PKT_TRANS_IECNT_ERR1_8814B BIT(1) +#define BIT_PKT_TRANS_IECNT_ERR0_8814B BIT(0) + +/* 2 REG_SHCUT_LLC_ETH_TYPE0_8814B */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE1_8814B */ + +#define BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B 16 +#define BIT_MASK_SHCUT_MHDR_OFFSET_8814B 0x1ff +#define BIT_SHCUT_MHDR_OFFSET_8814B(x) \ + (((x) & BIT_MASK_SHCUT_MHDR_OFFSET_8814B) \ + << BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B) +#define BITS_SHCUT_MHDR_OFFSET_8814B \ + (BIT_MASK_SHCUT_MHDR_OFFSET_8814B << BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B) +#define BIT_CLEAR_SHCUT_MHDR_OFFSET_8814B(x) \ + ((x) & (~BITS_SHCUT_MHDR_OFFSET_8814B)) +#define BIT_GET_SHCUT_MHDR_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B) & \ + BIT_MASK_SHCUT_MHDR_OFFSET_8814B) +#define BIT_SET_SHCUT_MHDR_OFFSET_8814B(x, v) \ + (BIT_CLEAR_SHCUT_MHDR_OFFSET_8814B(x) | BIT_SHCUT_MHDR_OFFSET_8814B(v)) + +/* 2 REG_SHCUT_LLC_OUI0_8814B */ + +/* 2 REG_SHCUT_LLC_OUI1_8814B */ + +/* 2 REG_SHCUT_LLC_OUI2_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B 0 +#define BIT_MASK_PKT_TRANS_ERR_MACID_8814B 0xffffffffL +#define BIT_PKT_TRANS_ERR_MACID_8814B(x) \ + (((x) & BIT_MASK_PKT_TRANS_ERR_MACID_8814B) \ + << BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B) +#define BITS_PKT_TRANS_ERR_MACID_8814B \ + (BIT_MASK_PKT_TRANS_ERR_MACID_8814B \ + << BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B) +#define BIT_CLEAR_PKT_TRANS_ERR_MACID_8814B(x) \ + ((x) & (~BITS_PKT_TRANS_ERR_MACID_8814B)) +#define BIT_GET_PKT_TRANS_ERR_MACID_8814B(x) \ + (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B) & \ + BIT_MASK_PKT_TRANS_ERR_MACID_8814B) +#define BIT_SET_PKT_TRANS_ERR_MACID_8814B(x, v) \ + (BIT_CLEAR_PKT_TRANS_ERR_MACID_8814B(x) | \ + BIT_PKT_TRANS_ERR_MACID_8814B(v)) + +/* 2 REG_FWCMDQ_CTRL_8814B */ +#define BIT_FW_RELEASEPKT_POLLING_8814B BIT(31) + +#define BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B 16 +#define BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B 0xfff +#define BIT_FWCMDQ_RELEASE_HEAD_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B) \ + << BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B) +#define BITS_FWCMDQ_RELEASE_HEAD_8814B \ + (BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B \ + << BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B) +#define BIT_CLEAR_FWCMDQ_RELEASE_HEAD_8814B(x) \ + ((x) & (~BITS_FWCMDQ_RELEASE_HEAD_8814B)) +#define BIT_GET_FWCMDQ_RELEASE_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B) & \ + BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B) +#define BIT_SET_FWCMDQ_RELEASE_HEAD_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_RELEASE_HEAD_8814B(x) | \ + BIT_FWCMDQ_RELEASE_HEAD_8814B(v)) + +#define BIT_FW_GETPKTT_POLLING_8814B BIT(15) + +#define BIT_SHIFT_FWCMDQ_H_8814B 0 +#define BIT_MASK_FWCMDQ_H_8814B 0xfff +#define BIT_FWCMDQ_H_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_H_8814B) << BIT_SHIFT_FWCMDQ_H_8814B) +#define BITS_FWCMDQ_H_8814B \ + (BIT_MASK_FWCMDQ_H_8814B << BIT_SHIFT_FWCMDQ_H_8814B) +#define BIT_CLEAR_FWCMDQ_H_8814B(x) ((x) & (~BITS_FWCMDQ_H_8814B)) +#define BIT_GET_FWCMDQ_H_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_H_8814B) & BIT_MASK_FWCMDQ_H_8814B) +#define BIT_SET_FWCMDQ_H_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_H_8814B(x) | BIT_FWCMDQ_H_8814B(v)) + +/* 2 REG_FWCMDQ_PAGE_8814B */ + +#define BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B 16 +#define BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B 0xfff +#define BIT_FWCMDQ_TOTAL_PAGE_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B) \ + << BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B) +#define BITS_FWCMDQ_TOTAL_PAGE_8814B \ + (BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B << BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B) +#define BIT_CLEAR_FWCMDQ_TOTAL_PAGE_8814B(x) \ + ((x) & (~BITS_FWCMDQ_TOTAL_PAGE_8814B)) +#define BIT_GET_FWCMDQ_TOTAL_PAGE_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B) & \ + BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B) +#define BIT_SET_FWCMDQ_TOTAL_PAGE_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_TOTAL_PAGE_8814B(x) | BIT_FWCMDQ_TOTAL_PAGE_8814B(v)) + +#define BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B 0 +#define BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B 0xfff +#define BIT_FWCMDQ_QUEUE_PAGE_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B) \ + << BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B) +#define BITS_FWCMDQ_QUEUE_PAGE_8814B \ + (BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B << BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B) +#define BIT_CLEAR_FWCMDQ_QUEUE_PAGE_8814B(x) \ + ((x) & (~BITS_FWCMDQ_QUEUE_PAGE_8814B)) +#define BIT_GET_FWCMDQ_QUEUE_PAGE_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B) & \ + BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B) +#define BIT_SET_FWCMDQ_QUEUE_PAGE_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_QUEUE_PAGE_8814B(x) | BIT_FWCMDQ_QUEUE_PAGE_8814B(v)) + +/* 2 REG_FWCMDQ_INFO_8814B */ +#define BIT_FWCMD_READY_8814B BIT(31) +#define BIT_FWCMDQ_OVERFLOW_8814B BIT(30) +#define BIT_FWCMDQ_UNDERFLOW_8814B BIT(29) +#define BIT_FWCMDQ_RELEASE_MISS_8814B BIT(28) + +#define BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B 16 +#define BIT_MASK_FWCMDQ_TOTAL_PKT_8814B 0xfff +#define BIT_FWCMDQ_TOTAL_PKT_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_TOTAL_PKT_8814B) \ + << BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B) +#define BITS_FWCMDQ_TOTAL_PKT_8814B \ + (BIT_MASK_FWCMDQ_TOTAL_PKT_8814B << BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B) +#define BIT_CLEAR_FWCMDQ_TOTAL_PKT_8814B(x) \ + ((x) & (~BITS_FWCMDQ_TOTAL_PKT_8814B)) +#define BIT_GET_FWCMDQ_TOTAL_PKT_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B) & \ + BIT_MASK_FWCMDQ_TOTAL_PKT_8814B) +#define BIT_SET_FWCMDQ_TOTAL_PKT_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_TOTAL_PKT_8814B(x) | BIT_FWCMDQ_TOTAL_PKT_8814B(v)) + +#define BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B 0 +#define BIT_MASK_FWCMDQ_QUEUE_PKT_8814B 0xfff +#define BIT_FWCMDQ_QUEUE_PKT_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_QUEUE_PKT_8814B) \ + << BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B) +#define BITS_FWCMDQ_QUEUE_PKT_8814B \ + (BIT_MASK_FWCMDQ_QUEUE_PKT_8814B << BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B) +#define BIT_CLEAR_FWCMDQ_QUEUE_PKT_8814B(x) \ + ((x) & (~BITS_FWCMDQ_QUEUE_PKT_8814B)) +#define BIT_GET_FWCMDQ_QUEUE_PKT_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B) & \ + BIT_MASK_FWCMDQ_QUEUE_PKT_8814B) +#define BIT_SET_FWCMDQ_QUEUE_PKT_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_QUEUE_PKT_8814B(x) | BIT_FWCMDQ_QUEUE_PKT_8814B(v)) + +/* 2 REG_FWCMDQ_HOLD_PKTNUM_8814B */ + +#define BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B 0 +#define BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B 0xfff +#define BIT_FWCMDQ_HOLD__PKTNUM_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B) \ + << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B) +#define BITS_FWCMDQ_HOLD__PKTNUM_8814B \ + (BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B \ + << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B) +#define BIT_CLEAR_FWCMDQ_HOLD__PKTNUM_8814B(x) \ + ((x) & (~BITS_FWCMDQ_HOLD__PKTNUM_8814B)) +#define BIT_GET_FWCMDQ_HOLD__PKTNUM_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B) & \ + BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B) +#define BIT_SET_FWCMDQ_HOLD__PKTNUM_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_HOLD__PKTNUM_8814B(x) | \ + BIT_FWCMDQ_HOLD__PKTNUM_8814B(v)) + +/* 2 REG_MU_TX_CTRL_8814B */ +#define BIT_SEARCH_DONE_RDY_8814B BIT(31) +#define BIT_MU_EN_8814B BIT(30) +#define BIT_MU_SECONDARY_WAITMODE_EN_8814B BIT(29) +#define BIT_MU_BB_SCORE_EN_8814B BIT(28) +#define BIT_MU_SECONDARY_ANT_COUNT_EN_8814B BIT(27) +#define BIT_MUARB_SEARCH_ERR_EN_8814B BIT(26) + +#define BIT_SHIFT_DIS_SU_TXBF_8814B 16 +#define BIT_MASK_DIS_SU_TXBF_8814B 0x3f +#define BIT_DIS_SU_TXBF_8814B(x) \ + (((x) & BIT_MASK_DIS_SU_TXBF_8814B) << BIT_SHIFT_DIS_SU_TXBF_8814B) +#define BITS_DIS_SU_TXBF_8814B \ + (BIT_MASK_DIS_SU_TXBF_8814B << BIT_SHIFT_DIS_SU_TXBF_8814B) +#define BIT_CLEAR_DIS_SU_TXBF_8814B(x) ((x) & (~BITS_DIS_SU_TXBF_8814B)) +#define BIT_GET_DIS_SU_TXBF_8814B(x) \ + (((x) >> BIT_SHIFT_DIS_SU_TXBF_8814B) & BIT_MASK_DIS_SU_TXBF_8814B) +#define BIT_SET_DIS_SU_TXBF_8814B(x, v) \ + (BIT_CLEAR_DIS_SU_TXBF_8814B(x) | BIT_DIS_SU_TXBF_8814B(v)) + +#define BIT_SHIFT_MU_RL_8814B 12 +#define BIT_MASK_MU_RL_8814B 0xf +#define BIT_MU_RL_8814B(x) \ + (((x) & BIT_MASK_MU_RL_8814B) << BIT_SHIFT_MU_RL_8814B) +#define BITS_MU_RL_8814B (BIT_MASK_MU_RL_8814B << BIT_SHIFT_MU_RL_8814B) +#define BIT_CLEAR_MU_RL_8814B(x) ((x) & (~BITS_MU_RL_8814B)) +#define BIT_GET_MU_RL_8814B(x) \ + (((x) >> BIT_SHIFT_MU_RL_8814B) & BIT_MASK_MU_RL_8814B) +#define BIT_SET_MU_RL_8814B(x, v) \ + (BIT_CLEAR_MU_RL_8814B(x) | BIT_MU_RL_8814B(v)) + +#define BIT_SHIFT_MU_TAB_SEL_8814B 8 +#define BIT_MASK_MU_TAB_SEL_8814B 0xf +#define BIT_MU_TAB_SEL_8814B(x) \ + (((x) & BIT_MASK_MU_TAB_SEL_8814B) << BIT_SHIFT_MU_TAB_SEL_8814B) +#define BITS_MU_TAB_SEL_8814B \ + (BIT_MASK_MU_TAB_SEL_8814B << BIT_SHIFT_MU_TAB_SEL_8814B) +#define BIT_CLEAR_MU_TAB_SEL_8814B(x) ((x) & (~BITS_MU_TAB_SEL_8814B)) +#define BIT_GET_MU_TAB_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MU_TAB_SEL_8814B) & BIT_MASK_MU_TAB_SEL_8814B) +#define BIT_SET_MU_TAB_SEL_8814B(x, v) \ + (BIT_CLEAR_MU_TAB_SEL_8814B(x) | BIT_MU_TAB_SEL_8814B(v)) + +#define BIT_SHIFT_MU_TAB_VALID_8814B 0 +#define BIT_MASK_MU_TAB_VALID_8814B 0x3f +#define BIT_MU_TAB_VALID_8814B(x) \ + (((x) & BIT_MASK_MU_TAB_VALID_8814B) << BIT_SHIFT_MU_TAB_VALID_8814B) +#define BITS_MU_TAB_VALID_8814B \ + (BIT_MASK_MU_TAB_VALID_8814B << BIT_SHIFT_MU_TAB_VALID_8814B) +#define BIT_CLEAR_MU_TAB_VALID_8814B(x) ((x) & (~BITS_MU_TAB_VALID_8814B)) +#define BIT_GET_MU_TAB_VALID_8814B(x) \ + (((x) >> BIT_SHIFT_MU_TAB_VALID_8814B) & BIT_MASK_MU_TAB_VALID_8814B) +#define BIT_SET_MU_TAB_VALID_8814B(x, v) \ + (BIT_CLEAR_MU_TAB_VALID_8814B(x) | BIT_MU_TAB_VALID_8814B(v)) + +/* 2 REG_MU_STA_GID_VLD_8814B */ + +#define BIT_SHIFT_MU_STA_GTAB_VALID_8814B 0 +#define BIT_MASK_MU_STA_GTAB_VALID_8814B 0xffffffffL +#define BIT_MU_STA_GTAB_VALID_8814B(x) \ + (((x) & BIT_MASK_MU_STA_GTAB_VALID_8814B) \ + << BIT_SHIFT_MU_STA_GTAB_VALID_8814B) +#define BITS_MU_STA_GTAB_VALID_8814B \ + (BIT_MASK_MU_STA_GTAB_VALID_8814B << BIT_SHIFT_MU_STA_GTAB_VALID_8814B) +#define BIT_CLEAR_MU_STA_GTAB_VALID_8814B(x) \ + ((x) & (~BITS_MU_STA_GTAB_VALID_8814B)) +#define BIT_GET_MU_STA_GTAB_VALID_8814B(x) \ + (((x) >> BIT_SHIFT_MU_STA_GTAB_VALID_8814B) & \ + BIT_MASK_MU_STA_GTAB_VALID_8814B) +#define BIT_SET_MU_STA_GTAB_VALID_8814B(x, v) \ + (BIT_CLEAR_MU_STA_GTAB_VALID_8814B(x) | BIT_MU_STA_GTAB_VALID_8814B(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_8814B */ + +#define BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B 0 +#define BIT_MASK_MU_STA_GTAB_POSITION_L_8814B 0xffffffffL +#define BIT_MU_STA_GTAB_POSITION_L_8814B(x) \ + (((x) & BIT_MASK_MU_STA_GTAB_POSITION_L_8814B) \ + << BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B) +#define BITS_MU_STA_GTAB_POSITION_L_8814B \ + (BIT_MASK_MU_STA_GTAB_POSITION_L_8814B \ + << BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B) +#define BIT_CLEAR_MU_STA_GTAB_POSITION_L_8814B(x) \ + ((x) & (~BITS_MU_STA_GTAB_POSITION_L_8814B)) +#define BIT_GET_MU_STA_GTAB_POSITION_L_8814B(x) \ + (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B) & \ + BIT_MASK_MU_STA_GTAB_POSITION_L_8814B) +#define BIT_SET_MU_STA_GTAB_POSITION_L_8814B(x, v) \ + (BIT_CLEAR_MU_STA_GTAB_POSITION_L_8814B(x) | \ + BIT_MU_STA_GTAB_POSITION_L_8814B(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_H_8814B */ + +#define BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B 0 +#define BIT_MASK_MU_STA_GTAB_POSITION_H_8814B 0xffffffffL +#define BIT_MU_STA_GTAB_POSITION_H_8814B(x) \ + (((x) & BIT_MASK_MU_STA_GTAB_POSITION_H_8814B) \ + << BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B) +#define BITS_MU_STA_GTAB_POSITION_H_8814B \ + (BIT_MASK_MU_STA_GTAB_POSITION_H_8814B \ + << BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B) +#define BIT_CLEAR_MU_STA_GTAB_POSITION_H_8814B(x) \ + ((x) & (~BITS_MU_STA_GTAB_POSITION_H_8814B)) +#define BIT_GET_MU_STA_GTAB_POSITION_H_8814B(x) \ + (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B) & \ + BIT_MASK_MU_STA_GTAB_POSITION_H_8814B) +#define BIT_SET_MU_STA_GTAB_POSITION_H_8814B(x, v) \ + (BIT_CLEAR_MU_STA_GTAB_POSITION_H_8814B(x) | \ + BIT_MU_STA_GTAB_POSITION_H_8814B(v)) + +/* 2 REG_CHNL_INFO_CTRL_8814B */ +#define BIT_CHNL_REF_RXNAV_8814B BIT(7) +#define BIT_CHNL_REF_VBON_8814B BIT(6) +#define BIT_CHNL_REF_EDCA_8814B BIT(5) +#define BIT_CHNL_REF_CCA_8814B BIT(4) +#define BIT_RST_CHNL_BUSY_8814B BIT(3) +#define BIT_RST_CHNL_IDLE_8814B BIT(2) +#define BIT_CHNL_INFO_RST_8814B BIT(1) +#define BIT_ATM_AIRTIME_EN_8814B BIT(0) + +/* 2 REG_CHNL_IDLE_TIME_8814B */ + +#define BIT_SHIFT_CHNL_IDLE_TIME_8814B 0 +#define BIT_MASK_CHNL_IDLE_TIME_8814B 0xffffffffL +#define BIT_CHNL_IDLE_TIME_8814B(x) \ + (((x) & BIT_MASK_CHNL_IDLE_TIME_8814B) \ + << BIT_SHIFT_CHNL_IDLE_TIME_8814B) +#define BITS_CHNL_IDLE_TIME_8814B \ + (BIT_MASK_CHNL_IDLE_TIME_8814B << BIT_SHIFT_CHNL_IDLE_TIME_8814B) +#define BIT_CLEAR_CHNL_IDLE_TIME_8814B(x) ((x) & (~BITS_CHNL_IDLE_TIME_8814B)) +#define BIT_GET_CHNL_IDLE_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8814B) & \ + BIT_MASK_CHNL_IDLE_TIME_8814B) +#define BIT_SET_CHNL_IDLE_TIME_8814B(x, v) \ + (BIT_CLEAR_CHNL_IDLE_TIME_8814B(x) | BIT_CHNL_IDLE_TIME_8814B(v)) + +/* 2 REG_CHNL_BUSY_TIME_8814B */ + +#define BIT_SHIFT_CHNL_BUSY_TIME_8814B 0 +#define BIT_MASK_CHNL_BUSY_TIME_8814B 0xffffffffL +#define BIT_CHNL_BUSY_TIME_8814B(x) \ + (((x) & BIT_MASK_CHNL_BUSY_TIME_8814B) \ + << BIT_SHIFT_CHNL_BUSY_TIME_8814B) +#define BITS_CHNL_BUSY_TIME_8814B \ + (BIT_MASK_CHNL_BUSY_TIME_8814B << BIT_SHIFT_CHNL_BUSY_TIME_8814B) +#define BIT_CLEAR_CHNL_BUSY_TIME_8814B(x) ((x) & (~BITS_CHNL_BUSY_TIME_8814B)) +#define BIT_GET_CHNL_BUSY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8814B) & \ + BIT_MASK_CHNL_BUSY_TIME_8814B) +#define BIT_SET_CHNL_BUSY_TIME_8814B(x, v) \ + (BIT_CLEAR_CHNL_BUSY_TIME_8814B(x) | BIT_CHNL_BUSY_TIME_8814B(v)) + +/* 2 REG_MU_TRX_DBG_CNT_V1_8814B */ +#define BIT_FORCE_SND_STS_EN_8814B BIT(31) + +#define BIT_SHIFT_SND_STS_VALUE_8814B 24 +#define BIT_MASK_SND_STS_VALUE_8814B 0x3f +#define BIT_SND_STS_VALUE_8814B(x) \ + (((x) & BIT_MASK_SND_STS_VALUE_8814B) << BIT_SHIFT_SND_STS_VALUE_8814B) +#define BITS_SND_STS_VALUE_8814B \ + (BIT_MASK_SND_STS_VALUE_8814B << BIT_SHIFT_SND_STS_VALUE_8814B) +#define BIT_CLEAR_SND_STS_VALUE_8814B(x) ((x) & (~BITS_SND_STS_VALUE_8814B)) +#define BIT_GET_SND_STS_VALUE_8814B(x) \ + (((x) >> BIT_SHIFT_SND_STS_VALUE_8814B) & BIT_MASK_SND_STS_VALUE_8814B) +#define BIT_SET_SND_STS_VALUE_8814B(x, v) \ + (BIT_CLEAR_SND_STS_VALUE_8814B(x) | BIT_SND_STS_VALUE_8814B(v)) -/* 2 REG_MU_TRX_DBG_CNT_8814B (NOT SUPPORT) */ #define BIT_MU_DNGCNT_RST_8814B BIT(20) -#define BIT_SHIFT_MU_DBGCNT_SEL_8814B 16 -#define BIT_MASK_MU_DBGCNT_SEL_8814B 0xf -#define BIT_MU_DBGCNT_SEL_8814B(x) (((x) & BIT_MASK_MU_DBGCNT_SEL_8814B) << BIT_SHIFT_MU_DBGCNT_SEL_8814B) -#define BIT_GET_MU_DBGCNT_SEL_8814B(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8814B) & BIT_MASK_MU_DBGCNT_SEL_8814B) - - +#define BIT_SHIFT_MU_DNGCNT_SEL_8814B 16 +#define BIT_MASK_MU_DNGCNT_SEL_8814B 0xf +#define BIT_MU_DNGCNT_SEL_8814B(x) \ + (((x) & BIT_MASK_MU_DNGCNT_SEL_8814B) << BIT_SHIFT_MU_DNGCNT_SEL_8814B) +#define BITS_MU_DNGCNT_SEL_8814B \ + (BIT_MASK_MU_DNGCNT_SEL_8814B << BIT_SHIFT_MU_DNGCNT_SEL_8814B) +#define BIT_CLEAR_MU_DNGCNT_SEL_8814B(x) ((x) & (~BITS_MU_DNGCNT_SEL_8814B)) +#define BIT_GET_MU_DNGCNT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_SEL_8814B) & BIT_MASK_MU_DNGCNT_SEL_8814B) +#define BIT_SET_MU_DNGCNT_SEL_8814B(x, v) \ + (BIT_CLEAR_MU_DNGCNT_SEL_8814B(x) | BIT_MU_DNGCNT_SEL_8814B(v)) #define BIT_SHIFT_MU_DNGCNT_8814B 0 #define BIT_MASK_MU_DNGCNT_8814B 0xffff -#define BIT_MU_DNGCNT_8814B(x) (((x) & BIT_MASK_MU_DNGCNT_8814B) << BIT_SHIFT_MU_DNGCNT_8814B) -#define BIT_GET_MU_DNGCNT_8814B(x) (((x) >> BIT_SHIFT_MU_DNGCNT_8814B) & BIT_MASK_MU_DNGCNT_8814B) - - +#define BIT_MU_DNGCNT_8814B(x) \ + (((x) & BIT_MASK_MU_DNGCNT_8814B) << BIT_SHIFT_MU_DNGCNT_8814B) +#define BITS_MU_DNGCNT_8814B \ + (BIT_MASK_MU_DNGCNT_8814B << BIT_SHIFT_MU_DNGCNT_8814B) +#define BIT_CLEAR_MU_DNGCNT_8814B(x) ((x) & (~BITS_MU_DNGCNT_8814B)) +#define BIT_GET_MU_DNGCNT_8814B(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_8814B) & BIT_MASK_MU_DNGCNT_8814B) +#define BIT_SET_MU_DNGCNT_8814B(x, v) \ + (BIT_CLEAR_MU_DNGCNT_8814B(x) | BIT_MU_DNGCNT_8814B(v)) + +/* 2 REG_SWPS_CTRL_8814B */ + +#define BIT_SHIFT_SWPS_RPT_LENGTH_8814B 8 +#define BIT_MASK_SWPS_RPT_LENGTH_8814B 0x7f +#define BIT_SWPS_RPT_LENGTH_8814B(x) \ + (((x) & BIT_MASK_SWPS_RPT_LENGTH_8814B) \ + << BIT_SHIFT_SWPS_RPT_LENGTH_8814B) +#define BITS_SWPS_RPT_LENGTH_8814B \ + (BIT_MASK_SWPS_RPT_LENGTH_8814B << BIT_SHIFT_SWPS_RPT_LENGTH_8814B) +#define BIT_CLEAR_SWPS_RPT_LENGTH_8814B(x) ((x) & (~BITS_SWPS_RPT_LENGTH_8814B)) +#define BIT_GET_SWPS_RPT_LENGTH_8814B(x) \ + (((x) >> BIT_SHIFT_SWPS_RPT_LENGTH_8814B) & \ + BIT_MASK_SWPS_RPT_LENGTH_8814B) +#define BIT_SET_SWPS_RPT_LENGTH_8814B(x, v) \ + (BIT_CLEAR_SWPS_RPT_LENGTH_8814B(x) | BIT_SWPS_RPT_LENGTH_8814B(v)) + +#define BIT_SHIFT_MACID_SWPS_EN_SEL_8814B 2 +#define BIT_MASK_MACID_SWPS_EN_SEL_8814B 0x3 +#define BIT_MACID_SWPS_EN_SEL_8814B(x) \ + (((x) & BIT_MASK_MACID_SWPS_EN_SEL_8814B) \ + << BIT_SHIFT_MACID_SWPS_EN_SEL_8814B) +#define BITS_MACID_SWPS_EN_SEL_8814B \ + (BIT_MASK_MACID_SWPS_EN_SEL_8814B << BIT_SHIFT_MACID_SWPS_EN_SEL_8814B) +#define BIT_CLEAR_MACID_SWPS_EN_SEL_8814B(x) \ + ((x) & (~BITS_MACID_SWPS_EN_SEL_8814B)) +#define BIT_GET_MACID_SWPS_EN_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_SWPS_EN_SEL_8814B) & \ + BIT_MASK_MACID_SWPS_EN_SEL_8814B) +#define BIT_SET_MACID_SWPS_EN_SEL_8814B(x, v) \ + (BIT_CLEAR_MACID_SWPS_EN_SEL_8814B(x) | BIT_MACID_SWPS_EN_SEL_8814B(v)) + +#define BIT_SWPS_MANUALL_POLLING_8814B BIT(1) +#define BIT_SWPS_EN_8814B BIT(0) + +/* 2 REG_SWPS_PKT_TH_8814B */ + +#define BIT_SHIFT_SWPS_PKT_TH_8814B 0 +#define BIT_MASK_SWPS_PKT_TH_8814B 0xffff +#define BIT_SWPS_PKT_TH_8814B(x) \ + (((x) & BIT_MASK_SWPS_PKT_TH_8814B) << BIT_SHIFT_SWPS_PKT_TH_8814B) +#define BITS_SWPS_PKT_TH_8814B \ + (BIT_MASK_SWPS_PKT_TH_8814B << BIT_SHIFT_SWPS_PKT_TH_8814B) +#define BIT_CLEAR_SWPS_PKT_TH_8814B(x) ((x) & (~BITS_SWPS_PKT_TH_8814B)) +#define BIT_GET_SWPS_PKT_TH_8814B(x) \ + (((x) >> BIT_SHIFT_SWPS_PKT_TH_8814B) & BIT_MASK_SWPS_PKT_TH_8814B) +#define BIT_SET_SWPS_PKT_TH_8814B(x, v) \ + (BIT_CLEAR_SWPS_PKT_TH_8814B(x) | BIT_SWPS_PKT_TH_8814B(v)) + +/* 2 REG_SWPS_TIME_TH_8814B */ + +#define BIT_SHIFT_SWPS_PSTIME_TH_8814B 16 +#define BIT_MASK_SWPS_PSTIME_TH_8814B 0xffff +#define BIT_SWPS_PSTIME_TH_8814B(x) \ + (((x) & BIT_MASK_SWPS_PSTIME_TH_8814B) \ + << BIT_SHIFT_SWPS_PSTIME_TH_8814B) +#define BITS_SWPS_PSTIME_TH_8814B \ + (BIT_MASK_SWPS_PSTIME_TH_8814B << BIT_SHIFT_SWPS_PSTIME_TH_8814B) +#define BIT_CLEAR_SWPS_PSTIME_TH_8814B(x) ((x) & (~BITS_SWPS_PSTIME_TH_8814B)) +#define BIT_GET_SWPS_PSTIME_TH_8814B(x) \ + (((x) >> BIT_SHIFT_SWPS_PSTIME_TH_8814B) & \ + BIT_MASK_SWPS_PSTIME_TH_8814B) +#define BIT_SET_SWPS_PSTIME_TH_8814B(x, v) \ + (BIT_CLEAR_SWPS_PSTIME_TH_8814B(x) | BIT_SWPS_PSTIME_TH_8814B(v)) + +#define BIT_SHIFT_SWPS_TIME_TH_8814B 0 +#define BIT_MASK_SWPS_TIME_TH_8814B 0xffff +#define BIT_SWPS_TIME_TH_8814B(x) \ + (((x) & BIT_MASK_SWPS_TIME_TH_8814B) << BIT_SHIFT_SWPS_TIME_TH_8814B) +#define BITS_SWPS_TIME_TH_8814B \ + (BIT_MASK_SWPS_TIME_TH_8814B << BIT_SHIFT_SWPS_TIME_TH_8814B) +#define BIT_CLEAR_SWPS_TIME_TH_8814B(x) ((x) & (~BITS_SWPS_TIME_TH_8814B)) +#define BIT_GET_SWPS_TIME_TH_8814B(x) \ + (((x) >> BIT_SHIFT_SWPS_TIME_TH_8814B) & BIT_MASK_SWPS_TIME_TH_8814B) +#define BIT_SET_SWPS_TIME_TH_8814B(x, v) \ + (BIT_CLEAR_SWPS_TIME_TH_8814B(x) | BIT_SWPS_TIME_TH_8814B(v)) + +/* 2 REG_MACID_SWPS_EN_8814B */ + +#define BIT_SHIFT_MACID_SWPS_EN_8814B 0 +#define BIT_MASK_MACID_SWPS_EN_8814B 0xffffffffL +#define BIT_MACID_SWPS_EN_8814B(x) \ + (((x) & BIT_MASK_MACID_SWPS_EN_8814B) << BIT_SHIFT_MACID_SWPS_EN_8814B) +#define BITS_MACID_SWPS_EN_8814B \ + (BIT_MASK_MACID_SWPS_EN_8814B << BIT_SHIFT_MACID_SWPS_EN_8814B) +#define BIT_CLEAR_MACID_SWPS_EN_8814B(x) ((x) & (~BITS_MACID_SWPS_EN_8814B)) +#define BIT_GET_MACID_SWPS_EN_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_SWPS_EN_8814B) & BIT_MASK_MACID_SWPS_EN_8814B) +#define BIT_SET_MACID_SWPS_EN_8814B(x, v) \ + (BIT_CLEAR_MACID_SWPS_EN_8814B(x) | BIT_MACID_SWPS_EN_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -7125,24 +17143,32 @@ #define BIT_SHIFT_TXOPLIMIT_8814B 16 #define BIT_MASK_TXOPLIMIT_8814B 0x7ff -#define BIT_TXOPLIMIT_8814B(x) (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) -#define BIT_GET_TXOPLIMIT_8814B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) - - +#define BIT_TXOPLIMIT_8814B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) +#define BITS_TXOPLIMIT_8814B \ + (BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B) +#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B)) +#define BIT_GET_TXOPLIMIT_8814B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) +#define BIT_SET_TXOPLIMIT_8814B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v)) #define BIT_SHIFT_CW_8814B 8 #define BIT_MASK_CW_8814B 0xff #define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B) +#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B) +#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B)) #define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B) - - +#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v)) #define BIT_SHIFT_AIFS_8814B 0 #define BIT_MASK_AIFS_8814B 0xff #define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B) -#define BIT_GET_AIFS_8814B(x) (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) - - +#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B) +#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B)) +#define BIT_GET_AIFS_8814B(x) \ + (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) +#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v)) /* 2 REG_EDCA_VI_PARAM_8814B */ @@ -7150,24 +17176,32 @@ #define BIT_SHIFT_TXOPLIMIT_8814B 16 #define BIT_MASK_TXOPLIMIT_8814B 0x7ff -#define BIT_TXOPLIMIT_8814B(x) (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) -#define BIT_GET_TXOPLIMIT_8814B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) - - +#define BIT_TXOPLIMIT_8814B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) +#define BITS_TXOPLIMIT_8814B \ + (BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B) +#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B)) +#define BIT_GET_TXOPLIMIT_8814B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) +#define BIT_SET_TXOPLIMIT_8814B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v)) #define BIT_SHIFT_CW_8814B 8 #define BIT_MASK_CW_8814B 0xff #define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B) +#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B) +#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B)) #define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B) - - +#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v)) #define BIT_SHIFT_AIFS_8814B 0 #define BIT_MASK_AIFS_8814B 0xff #define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B) -#define BIT_GET_AIFS_8814B(x) (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) - - +#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B) +#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B)) +#define BIT_GET_AIFS_8814B(x) \ + (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) +#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v)) /* 2 REG_EDCA_BE_PARAM_8814B */ @@ -7175,24 +17209,32 @@ #define BIT_SHIFT_TXOPLIMIT_8814B 16 #define BIT_MASK_TXOPLIMIT_8814B 0x7ff -#define BIT_TXOPLIMIT_8814B(x) (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) -#define BIT_GET_TXOPLIMIT_8814B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) - - +#define BIT_TXOPLIMIT_8814B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) +#define BITS_TXOPLIMIT_8814B \ + (BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B) +#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B)) +#define BIT_GET_TXOPLIMIT_8814B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) +#define BIT_SET_TXOPLIMIT_8814B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v)) #define BIT_SHIFT_CW_8814B 8 #define BIT_MASK_CW_8814B 0xff #define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B) +#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B) +#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B)) #define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B) - - +#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v)) #define BIT_SHIFT_AIFS_8814B 0 #define BIT_MASK_AIFS_8814B 0xff #define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B) -#define BIT_GET_AIFS_8814B(x) (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) - - +#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B) +#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B)) +#define BIT_GET_AIFS_8814B(x) \ + (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) +#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v)) /* 2 REG_EDCA_BK_PARAM_8814B */ @@ -7200,124 +17242,212 @@ #define BIT_SHIFT_TXOPLIMIT_8814B 16 #define BIT_MASK_TXOPLIMIT_8814B 0x7ff -#define BIT_TXOPLIMIT_8814B(x) (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) -#define BIT_GET_TXOPLIMIT_8814B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) - - +#define BIT_TXOPLIMIT_8814B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) +#define BITS_TXOPLIMIT_8814B \ + (BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B) +#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B)) +#define BIT_GET_TXOPLIMIT_8814B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) +#define BIT_SET_TXOPLIMIT_8814B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v)) #define BIT_SHIFT_CW_8814B 8 #define BIT_MASK_CW_8814B 0xff #define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B) +#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B) +#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B)) #define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B) - - +#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v)) #define BIT_SHIFT_AIFS_8814B 0 #define BIT_MASK_AIFS_8814B 0xff #define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B) -#define BIT_GET_AIFS_8814B(x) (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) - - +#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B) +#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B)) +#define BIT_GET_AIFS_8814B(x) \ + (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) +#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v)) /* 2 REG_BCNTCFG_8814B */ #define BIT_SHIFT_BCNCW_MAX_8814B 12 #define BIT_MASK_BCNCW_MAX_8814B 0xf -#define BIT_BCNCW_MAX_8814B(x) (((x) & BIT_MASK_BCNCW_MAX_8814B) << BIT_SHIFT_BCNCW_MAX_8814B) -#define BIT_GET_BCNCW_MAX_8814B(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8814B) & BIT_MASK_BCNCW_MAX_8814B) - - +#define BIT_BCNCW_MAX_8814B(x) \ + (((x) & BIT_MASK_BCNCW_MAX_8814B) << BIT_SHIFT_BCNCW_MAX_8814B) +#define BITS_BCNCW_MAX_8814B \ + (BIT_MASK_BCNCW_MAX_8814B << BIT_SHIFT_BCNCW_MAX_8814B) +#define BIT_CLEAR_BCNCW_MAX_8814B(x) ((x) & (~BITS_BCNCW_MAX_8814B)) +#define BIT_GET_BCNCW_MAX_8814B(x) \ + (((x) >> BIT_SHIFT_BCNCW_MAX_8814B) & BIT_MASK_BCNCW_MAX_8814B) +#define BIT_SET_BCNCW_MAX_8814B(x, v) \ + (BIT_CLEAR_BCNCW_MAX_8814B(x) | BIT_BCNCW_MAX_8814B(v)) #define BIT_SHIFT_BCNCW_MIN_8814B 8 #define BIT_MASK_BCNCW_MIN_8814B 0xf -#define BIT_BCNCW_MIN_8814B(x) (((x) & BIT_MASK_BCNCW_MIN_8814B) << BIT_SHIFT_BCNCW_MIN_8814B) -#define BIT_GET_BCNCW_MIN_8814B(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8814B) & BIT_MASK_BCNCW_MIN_8814B) - - +#define BIT_BCNCW_MIN_8814B(x) \ + (((x) & BIT_MASK_BCNCW_MIN_8814B) << BIT_SHIFT_BCNCW_MIN_8814B) +#define BITS_BCNCW_MIN_8814B \ + (BIT_MASK_BCNCW_MIN_8814B << BIT_SHIFT_BCNCW_MIN_8814B) +#define BIT_CLEAR_BCNCW_MIN_8814B(x) ((x) & (~BITS_BCNCW_MIN_8814B)) +#define BIT_GET_BCNCW_MIN_8814B(x) \ + (((x) >> BIT_SHIFT_BCNCW_MIN_8814B) & BIT_MASK_BCNCW_MIN_8814B) +#define BIT_SET_BCNCW_MIN_8814B(x, v) \ + (BIT_CLEAR_BCNCW_MIN_8814B(x) | BIT_BCNCW_MIN_8814B(v)) #define BIT_SHIFT_BCNIFS_8814B 0 #define BIT_MASK_BCNIFS_8814B 0xff -#define BIT_BCNIFS_8814B(x) (((x) & BIT_MASK_BCNIFS_8814B) << BIT_SHIFT_BCNIFS_8814B) -#define BIT_GET_BCNIFS_8814B(x) (((x) >> BIT_SHIFT_BCNIFS_8814B) & BIT_MASK_BCNIFS_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_BCNIFS_8814B(x) \ + (((x) & BIT_MASK_BCNIFS_8814B) << BIT_SHIFT_BCNIFS_8814B) +#define BITS_BCNIFS_8814B (BIT_MASK_BCNIFS_8814B << BIT_SHIFT_BCNIFS_8814B) +#define BIT_CLEAR_BCNIFS_8814B(x) ((x) & (~BITS_BCNIFS_8814B)) +#define BIT_GET_BCNIFS_8814B(x) \ + (((x) >> BIT_SHIFT_BCNIFS_8814B) & BIT_MASK_BCNIFS_8814B) +#define BIT_SET_BCNIFS_8814B(x, v) \ + (BIT_CLEAR_BCNIFS_8814B(x) | BIT_BCNIFS_8814B(v)) /* 2 REG_PIFS_8814B */ #define BIT_SHIFT_PIFS_8814B 0 #define BIT_MASK_PIFS_8814B 0xff #define BIT_PIFS_8814B(x) (((x) & BIT_MASK_PIFS_8814B) << BIT_SHIFT_PIFS_8814B) -#define BIT_GET_PIFS_8814B(x) (((x) >> BIT_SHIFT_PIFS_8814B) & BIT_MASK_PIFS_8814B) - - +#define BITS_PIFS_8814B (BIT_MASK_PIFS_8814B << BIT_SHIFT_PIFS_8814B) +#define BIT_CLEAR_PIFS_8814B(x) ((x) & (~BITS_PIFS_8814B)) +#define BIT_GET_PIFS_8814B(x) \ + (((x) >> BIT_SHIFT_PIFS_8814B) & BIT_MASK_PIFS_8814B) +#define BIT_SET_PIFS_8814B(x, v) (BIT_CLEAR_PIFS_8814B(x) | BIT_PIFS_8814B(v)) /* 2 REG_RDG_PIFS_8814B */ #define BIT_SHIFT_RDG_PIFS_8814B 0 #define BIT_MASK_RDG_PIFS_8814B 0xff -#define BIT_RDG_PIFS_8814B(x) (((x) & BIT_MASK_RDG_PIFS_8814B) << BIT_SHIFT_RDG_PIFS_8814B) -#define BIT_GET_RDG_PIFS_8814B(x) (((x) >> BIT_SHIFT_RDG_PIFS_8814B) & BIT_MASK_RDG_PIFS_8814B) - - +#define BIT_RDG_PIFS_8814B(x) \ + (((x) & BIT_MASK_RDG_PIFS_8814B) << BIT_SHIFT_RDG_PIFS_8814B) +#define BITS_RDG_PIFS_8814B \ + (BIT_MASK_RDG_PIFS_8814B << BIT_SHIFT_RDG_PIFS_8814B) +#define BIT_CLEAR_RDG_PIFS_8814B(x) ((x) & (~BITS_RDG_PIFS_8814B)) +#define BIT_GET_RDG_PIFS_8814B(x) \ + (((x) >> BIT_SHIFT_RDG_PIFS_8814B) & BIT_MASK_RDG_PIFS_8814B) +#define BIT_SET_RDG_PIFS_8814B(x, v) \ + (BIT_CLEAR_RDG_PIFS_8814B(x) | BIT_RDG_PIFS_8814B(v)) /* 2 REG_SIFS_8814B */ #define BIT_SHIFT_SIFS_OFDM_TRX_8814B 24 #define BIT_MASK_SIFS_OFDM_TRX_8814B 0xff -#define BIT_SIFS_OFDM_TRX_8814B(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8814B) << BIT_SHIFT_SIFS_OFDM_TRX_8814B) -#define BIT_GET_SIFS_OFDM_TRX_8814B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8814B) & BIT_MASK_SIFS_OFDM_TRX_8814B) - - +#define BIT_SIFS_OFDM_TRX_8814B(x) \ + (((x) & BIT_MASK_SIFS_OFDM_TRX_8814B) << BIT_SHIFT_SIFS_OFDM_TRX_8814B) +#define BITS_SIFS_OFDM_TRX_8814B \ + (BIT_MASK_SIFS_OFDM_TRX_8814B << BIT_SHIFT_SIFS_OFDM_TRX_8814B) +#define BIT_CLEAR_SIFS_OFDM_TRX_8814B(x) ((x) & (~BITS_SIFS_OFDM_TRX_8814B)) +#define BIT_GET_SIFS_OFDM_TRX_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8814B) & BIT_MASK_SIFS_OFDM_TRX_8814B) +#define BIT_SET_SIFS_OFDM_TRX_8814B(x, v) \ + (BIT_CLEAR_SIFS_OFDM_TRX_8814B(x) | BIT_SIFS_OFDM_TRX_8814B(v)) #define BIT_SHIFT_SIFS_CCK_TRX_8814B 16 #define BIT_MASK_SIFS_CCK_TRX_8814B 0xff -#define BIT_SIFS_CCK_TRX_8814B(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8814B) << BIT_SHIFT_SIFS_CCK_TRX_8814B) -#define BIT_GET_SIFS_CCK_TRX_8814B(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8814B) & BIT_MASK_SIFS_CCK_TRX_8814B) - - +#define BIT_SIFS_CCK_TRX_8814B(x) \ + (((x) & BIT_MASK_SIFS_CCK_TRX_8814B) << BIT_SHIFT_SIFS_CCK_TRX_8814B) +#define BITS_SIFS_CCK_TRX_8814B \ + (BIT_MASK_SIFS_CCK_TRX_8814B << BIT_SHIFT_SIFS_CCK_TRX_8814B) +#define BIT_CLEAR_SIFS_CCK_TRX_8814B(x) ((x) & (~BITS_SIFS_CCK_TRX_8814B)) +#define BIT_GET_SIFS_CCK_TRX_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8814B) & BIT_MASK_SIFS_CCK_TRX_8814B) +#define BIT_SET_SIFS_CCK_TRX_8814B(x, v) \ + (BIT_CLEAR_SIFS_CCK_TRX_8814B(x) | BIT_SIFS_CCK_TRX_8814B(v)) #define BIT_SHIFT_SIFS_OFDM_CTX_8814B 8 #define BIT_MASK_SIFS_OFDM_CTX_8814B 0xff -#define BIT_SIFS_OFDM_CTX_8814B(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8814B) << BIT_SHIFT_SIFS_OFDM_CTX_8814B) -#define BIT_GET_SIFS_OFDM_CTX_8814B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8814B) & BIT_MASK_SIFS_OFDM_CTX_8814B) - - +#define BIT_SIFS_OFDM_CTX_8814B(x) \ + (((x) & BIT_MASK_SIFS_OFDM_CTX_8814B) << BIT_SHIFT_SIFS_OFDM_CTX_8814B) +#define BITS_SIFS_OFDM_CTX_8814B \ + (BIT_MASK_SIFS_OFDM_CTX_8814B << BIT_SHIFT_SIFS_OFDM_CTX_8814B) +#define BIT_CLEAR_SIFS_OFDM_CTX_8814B(x) ((x) & (~BITS_SIFS_OFDM_CTX_8814B)) +#define BIT_GET_SIFS_OFDM_CTX_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8814B) & BIT_MASK_SIFS_OFDM_CTX_8814B) +#define BIT_SET_SIFS_OFDM_CTX_8814B(x, v) \ + (BIT_CLEAR_SIFS_OFDM_CTX_8814B(x) | BIT_SIFS_OFDM_CTX_8814B(v)) #define BIT_SHIFT_SIFS_CCK_CTX_8814B 0 #define BIT_MASK_SIFS_CCK_CTX_8814B 0xff -#define BIT_SIFS_CCK_CTX_8814B(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8814B) << BIT_SHIFT_SIFS_CCK_CTX_8814B) -#define BIT_GET_SIFS_CCK_CTX_8814B(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8814B) & BIT_MASK_SIFS_CCK_CTX_8814B) - - - -/* 2 REG_TSFTR_SYN_OFFSET_8814B */ - -#define BIT_SHIFT_TSFTR_SNC_OFFSET_8814B 0 -#define BIT_MASK_TSFTR_SNC_OFFSET_8814B 0xffff -#define BIT_TSFTR_SNC_OFFSET_8814B(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8814B) << BIT_SHIFT_TSFTR_SNC_OFFSET_8814B) -#define BIT_GET_TSFTR_SNC_OFFSET_8814B(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8814B) & BIT_MASK_TSFTR_SNC_OFFSET_8814B) +#define BIT_SIFS_CCK_CTX_8814B(x) \ + (((x) & BIT_MASK_SIFS_CCK_CTX_8814B) << BIT_SHIFT_SIFS_CCK_CTX_8814B) +#define BITS_SIFS_CCK_CTX_8814B \ + (BIT_MASK_SIFS_CCK_CTX_8814B << BIT_SHIFT_SIFS_CCK_CTX_8814B) +#define BIT_CLEAR_SIFS_CCK_CTX_8814B(x) ((x) & (~BITS_SIFS_CCK_CTX_8814B)) +#define BIT_GET_SIFS_CCK_CTX_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8814B) & BIT_MASK_SIFS_CCK_CTX_8814B) +#define BIT_SET_SIFS_CCK_CTX_8814B(x, v) \ + (BIT_CLEAR_SIFS_CCK_CTX_8814B(x) | BIT_SIFS_CCK_CTX_8814B(v)) + +/* 2 REG_FORCE_BCN_IFS_V1_8814B */ +#define BIT_SHIFT_FORCE_BCN_IFS_8814B 0 +#define BIT_MASK_FORCE_BCN_IFS_8814B 0xff +#define BIT_FORCE_BCN_IFS_8814B(x) \ + (((x) & BIT_MASK_FORCE_BCN_IFS_8814B) << BIT_SHIFT_FORCE_BCN_IFS_8814B) +#define BITS_FORCE_BCN_IFS_8814B \ + (BIT_MASK_FORCE_BCN_IFS_8814B << BIT_SHIFT_FORCE_BCN_IFS_8814B) +#define BIT_CLEAR_FORCE_BCN_IFS_8814B(x) ((x) & (~BITS_FORCE_BCN_IFS_8814B)) +#define BIT_GET_FORCE_BCN_IFS_8814B(x) \ + (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8814B) & BIT_MASK_FORCE_BCN_IFS_8814B) +#define BIT_SET_FORCE_BCN_IFS_8814B(x, v) \ + (BIT_CLEAR_FORCE_BCN_IFS_8814B(x) | BIT_FORCE_BCN_IFS_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_AGGR_BREAK_TIME_8814B */ #define BIT_SHIFT_AGGR_BK_TIME_8814B 0 #define BIT_MASK_AGGR_BK_TIME_8814B 0xff -#define BIT_AGGR_BK_TIME_8814B(x) (((x) & BIT_MASK_AGGR_BK_TIME_8814B) << BIT_SHIFT_AGGR_BK_TIME_8814B) -#define BIT_GET_AGGR_BK_TIME_8814B(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8814B) & BIT_MASK_AGGR_BK_TIME_8814B) - - +#define BIT_AGGR_BK_TIME_8814B(x) \ + (((x) & BIT_MASK_AGGR_BK_TIME_8814B) << BIT_SHIFT_AGGR_BK_TIME_8814B) +#define BITS_AGGR_BK_TIME_8814B \ + (BIT_MASK_AGGR_BK_TIME_8814B << BIT_SHIFT_AGGR_BK_TIME_8814B) +#define BIT_CLEAR_AGGR_BK_TIME_8814B(x) ((x) & (~BITS_AGGR_BK_TIME_8814B)) +#define BIT_GET_AGGR_BK_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_AGGR_BK_TIME_8814B) & BIT_MASK_AGGR_BK_TIME_8814B) +#define BIT_SET_AGGR_BK_TIME_8814B(x, v) \ + (BIT_CLEAR_AGGR_BK_TIME_8814B(x) | BIT_AGGR_BK_TIME_8814B(v)) /* 2 REG_SLOT_8814B */ #define BIT_SHIFT_SLOT_8814B 0 #define BIT_MASK_SLOT_8814B 0xff #define BIT_SLOT_8814B(x) (((x) & BIT_MASK_SLOT_8814B) << BIT_SHIFT_SLOT_8814B) -#define BIT_GET_SLOT_8814B(x) (((x) >> BIT_SHIFT_SLOT_8814B) & BIT_MASK_SLOT_8814B) - - +#define BITS_SLOT_8814B (BIT_MASK_SLOT_8814B << BIT_SHIFT_SLOT_8814B) +#define BIT_CLEAR_SLOT_8814B(x) ((x) & (~BITS_SLOT_8814B)) +#define BIT_GET_SLOT_8814B(x) \ + (((x) >> BIT_SHIFT_SLOT_8814B) & BIT_MASK_SLOT_8814B) +#define BIT_SET_SLOT_8814B(x, v) (BIT_CLEAR_SLOT_8814B(x) | BIT_SLOT_8814B(v)) + +/* 2 REG_EDCA_CPUMGQ_PARAM_8814B */ + +#define BIT_SHIFT_CW_V1_8814B 8 +#define BIT_MASK_CW_V1_8814B 0xff +#define BIT_CW_V1_8814B(x) \ + (((x) & BIT_MASK_CW_V1_8814B) << BIT_SHIFT_CW_V1_8814B) +#define BITS_CW_V1_8814B (BIT_MASK_CW_V1_8814B << BIT_SHIFT_CW_V1_8814B) +#define BIT_CLEAR_CW_V1_8814B(x) ((x) & (~BITS_CW_V1_8814B)) +#define BIT_GET_CW_V1_8814B(x) \ + (((x) >> BIT_SHIFT_CW_V1_8814B) & BIT_MASK_CW_V1_8814B) +#define BIT_SET_CW_V1_8814B(x, v) \ + (BIT_CLEAR_CW_V1_8814B(x) | BIT_CW_V1_8814B(v)) + +#define BIT_SHIFT_AIFS_V1_8814B 0 +#define BIT_MASK_AIFS_V1_8814B 0xff +#define BIT_AIFS_V1_8814B(x) \ + (((x) & BIT_MASK_AIFS_V1_8814B) << BIT_SHIFT_AIFS_V1_8814B) +#define BITS_AIFS_V1_8814B (BIT_MASK_AIFS_V1_8814B << BIT_SHIFT_AIFS_V1_8814B) +#define BIT_CLEAR_AIFS_V1_8814B(x) ((x) & (~BITS_AIFS_V1_8814B)) +#define BIT_GET_AIFS_V1_8814B(x) \ + (((x) >> BIT_SHIFT_AIFS_V1_8814B) & BIT_MASK_AIFS_V1_8814B) +#define BIT_SET_AIFS_V1_8814B(x, v) \ + (BIT_CLEAR_AIFS_V1_8814B(x) | BIT_AIFS_V1_8814B(v)) + +/* 2 REG_CPUMGQ_PAUSE_8814B */ +#define BIT_MAC_STOP_CPUMGQ_V1_8814B BIT(0) /* 2 REG_NOT_VALID_8814B */ @@ -7329,9 +17459,15 @@ #define BIT_SHIFT_TXQ_NAV_MSK_8814B 8 #define BIT_MASK_TXQ_NAV_MSK_8814B 0xf -#define BIT_TXQ_NAV_MSK_8814B(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8814B) << BIT_SHIFT_TXQ_NAV_MSK_8814B) -#define BIT_GET_TXQ_NAV_MSK_8814B(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8814B) & BIT_MASK_TXQ_NAV_MSK_8814B) - +#define BIT_TXQ_NAV_MSK_8814B(x) \ + (((x) & BIT_MASK_TXQ_NAV_MSK_8814B) << BIT_SHIFT_TXQ_NAV_MSK_8814B) +#define BITS_TXQ_NAV_MSK_8814B \ + (BIT_MASK_TXQ_NAV_MSK_8814B << BIT_SHIFT_TXQ_NAV_MSK_8814B) +#define BIT_CLEAR_TXQ_NAV_MSK_8814B(x) ((x) & (~BITS_TXQ_NAV_MSK_8814B)) +#define BIT_GET_TXQ_NAV_MSK_8814B(x) \ + (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8814B) & BIT_MASK_TXQ_NAV_MSK_8814B) +#define BIT_SET_TXQ_NAV_MSK_8814B(x, v) \ + (BIT_CLEAR_TXQ_NAV_MSK_8814B(x) | BIT_TXQ_NAV_MSK_8814B(v)) #define BIT_DIS_CW_8814B BIT(7) #define BIT_NAV_END_TXOP_8814B BIT(6) @@ -7368,7 +17504,6 @@ #define BIT_EDCCA_MSK_CNTDOWN_EN_8814B BIT(11) #define BIT_DIS_TXOP_CFE_8814B BIT(10) #define BIT_DIS_LSIG_CFE_8814B BIT(9) -#define BIT_DIS_STBC_CFE_8814B BIT(8) #define BIT_BKQ_RD_INIT_EN_8814B BIT(7) #define BIT_BEQ_RD_INIT_EN_8814B BIT(6) #define BIT_VIQ_RD_INIT_EN_8814B BIT(5) @@ -7378,27 +17513,13 @@ #define BIT_VIQ_RD_RESP_EN_8814B BIT(1) #define BIT_VOQ_RD_RESP_EN_8814B BIT(0) -/* 2 REG_MBSSID_CTRL_8814B */ -#define BIT_MBID_BCNQ7_EN_8814B BIT(7) -#define BIT_MBID_BCNQ6_EN_8814B BIT(6) -#define BIT_MBID_BCNQ5_EN_8814B BIT(5) -#define BIT_MBID_BCNQ4_EN_8814B BIT(4) -#define BIT_MBID_BCNQ3_EN_8814B BIT(3) -#define BIT_MBID_BCNQ2_EN_8814B BIT(2) -#define BIT_MBID_BCNQ1_EN_8814B BIT(1) -#define BIT_MBID_BCNQ0_EN_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_P2PPS_CTRL_8814B */ -#define BIT_P2P_CTW_ALLSTASLEEP_8814B BIT(7) -#define BIT_P2P_OFF_DISTX_EN_8814B BIT(6) -#define BIT_PWR_MGT_EN_8814B BIT(5) -#define BIT_P2P_NOA1_EN_8814B BIT(2) -#define BIT_P2P_NOA0_EN_8814B BIT(1) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_PKT_LIFETIME_CTRL_8814B */ #define BIT_EN_P2P_CTWND1_8814B BIT(23) #define BIT_EN_BKF_CLR_TXREQ_8814B BIT(22) -#define BIT_EN_TSFBIT32_RST_P2P_8814B BIT(21) #define BIT_EN_BCN_TX_BTCCA_8814B BIT(20) #define BIT_DIS_PKT_TX_ATIM_8814B BIT(19) #define BIT_DIS_BCN_DIS_CTN_8814B BIT(18) @@ -7407,40 +17528,413 @@ #define BIT_SHIFT_CCA_FILTER_THRS_8814B 8 #define BIT_MASK_CCA_FILTER_THRS_8814B 0xff -#define BIT_CCA_FILTER_THRS_8814B(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8814B) << BIT_SHIFT_CCA_FILTER_THRS_8814B) -#define BIT_GET_CCA_FILTER_THRS_8814B(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8814B) & BIT_MASK_CCA_FILTER_THRS_8814B) - - +#define BIT_CCA_FILTER_THRS_8814B(x) \ + (((x) & BIT_MASK_CCA_FILTER_THRS_8814B) \ + << BIT_SHIFT_CCA_FILTER_THRS_8814B) +#define BITS_CCA_FILTER_THRS_8814B \ + (BIT_MASK_CCA_FILTER_THRS_8814B << BIT_SHIFT_CCA_FILTER_THRS_8814B) +#define BIT_CLEAR_CCA_FILTER_THRS_8814B(x) ((x) & (~BITS_CCA_FILTER_THRS_8814B)) +#define BIT_GET_CCA_FILTER_THRS_8814B(x) \ + (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8814B) & \ + BIT_MASK_CCA_FILTER_THRS_8814B) +#define BIT_SET_CCA_FILTER_THRS_8814B(x, v) \ + (BIT_CLEAR_CCA_FILTER_THRS_8814B(x) | BIT_CCA_FILTER_THRS_8814B(v)) #define BIT_SHIFT_EDCCA_THRS_8814B 0 #define BIT_MASK_EDCCA_THRS_8814B 0xff -#define BIT_EDCCA_THRS_8814B(x) (((x) & BIT_MASK_EDCCA_THRS_8814B) << BIT_SHIFT_EDCCA_THRS_8814B) -#define BIT_GET_EDCCA_THRS_8814B(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8814B) & BIT_MASK_EDCCA_THRS_8814B) +#define BIT_EDCCA_THRS_8814B(x) \ + (((x) & BIT_MASK_EDCCA_THRS_8814B) << BIT_SHIFT_EDCCA_THRS_8814B) +#define BITS_EDCCA_THRS_8814B \ + (BIT_MASK_EDCCA_THRS_8814B << BIT_SHIFT_EDCCA_THRS_8814B) +#define BIT_CLEAR_EDCCA_THRS_8814B(x) ((x) & (~BITS_EDCCA_THRS_8814B)) +#define BIT_GET_EDCCA_THRS_8814B(x) \ + (((x) >> BIT_SHIFT_EDCCA_THRS_8814B) & BIT_MASK_EDCCA_THRS_8814B) +#define BIT_SET_EDCCA_THRS_8814B(x, v) \ + (BIT_CLEAR_EDCCA_THRS_8814B(x) | BIT_EDCCA_THRS_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_TXOP_LIMIT_CTRL_8814B */ + +#define BIT_SHIFT_TXOP_TBTT_CNT_8814B 24 +#define BIT_MASK_TXOP_TBTT_CNT_8814B 0xff +#define BIT_TXOP_TBTT_CNT_8814B(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_8814B) << BIT_SHIFT_TXOP_TBTT_CNT_8814B) +#define BITS_TXOP_TBTT_CNT_8814B \ + (BIT_MASK_TXOP_TBTT_CNT_8814B << BIT_SHIFT_TXOP_TBTT_CNT_8814B) +#define BIT_CLEAR_TXOP_TBTT_CNT_8814B(x) ((x) & (~BITS_TXOP_TBTT_CNT_8814B)) +#define BIT_GET_TXOP_TBTT_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8814B) & BIT_MASK_TXOP_TBTT_CNT_8814B) +#define BIT_SET_TXOP_TBTT_CNT_8814B(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_8814B(x) | BIT_TXOP_TBTT_CNT_8814B(v)) + +#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B 20 +#define BIT_MASK_TXOP_TBTT_CNT_SEL_8814B 0xf +#define BIT_TXOP_TBTT_CNT_SEL_8814B(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8814B) \ + << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B) +#define BITS_TXOP_TBTT_CNT_SEL_8814B \ + (BIT_MASK_TXOP_TBTT_CNT_SEL_8814B << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B) +#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8814B(x) \ + ((x) & (~BITS_TXOP_TBTT_CNT_SEL_8814B)) +#define BIT_GET_TXOP_TBTT_CNT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B) & \ + BIT_MASK_TXOP_TBTT_CNT_SEL_8814B) +#define BIT_SET_TXOP_TBTT_CNT_SEL_8814B(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_SEL_8814B(x) | BIT_TXOP_TBTT_CNT_SEL_8814B(v)) + +#define BIT_SHIFT_TXOP_LMT_EN_8814B 16 +#define BIT_MASK_TXOP_LMT_EN_8814B 0xf +#define BIT_TXOP_LMT_EN_8814B(x) \ + (((x) & BIT_MASK_TXOP_LMT_EN_8814B) << BIT_SHIFT_TXOP_LMT_EN_8814B) +#define BITS_TXOP_LMT_EN_8814B \ + (BIT_MASK_TXOP_LMT_EN_8814B << BIT_SHIFT_TXOP_LMT_EN_8814B) +#define BIT_CLEAR_TXOP_LMT_EN_8814B(x) ((x) & (~BITS_TXOP_LMT_EN_8814B)) +#define BIT_GET_TXOP_LMT_EN_8814B(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_EN_8814B) & BIT_MASK_TXOP_LMT_EN_8814B) +#define BIT_SET_TXOP_LMT_EN_8814B(x, v) \ + (BIT_CLEAR_TXOP_LMT_EN_8814B(x) | BIT_TXOP_LMT_EN_8814B(v)) + +#define BIT_SHIFT_TXOP_LMT_TX_TIME_8814B 8 +#define BIT_MASK_TXOP_LMT_TX_TIME_8814B 0xff +#define BIT_TXOP_LMT_TX_TIME_8814B(x) \ + (((x) & BIT_MASK_TXOP_LMT_TX_TIME_8814B) \ + << BIT_SHIFT_TXOP_LMT_TX_TIME_8814B) +#define BITS_TXOP_LMT_TX_TIME_8814B \ + (BIT_MASK_TXOP_LMT_TX_TIME_8814B << BIT_SHIFT_TXOP_LMT_TX_TIME_8814B) +#define BIT_CLEAR_TXOP_LMT_TX_TIME_8814B(x) \ + ((x) & (~BITS_TXOP_LMT_TX_TIME_8814B)) +#define BIT_GET_TXOP_LMT_TX_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8814B) & \ + BIT_MASK_TXOP_LMT_TX_TIME_8814B) +#define BIT_SET_TXOP_LMT_TX_TIME_8814B(x, v) \ + (BIT_CLEAR_TXOP_LMT_TX_TIME_8814B(x) | BIT_TXOP_LMT_TX_TIME_8814B(v)) + +#define BIT_TXOP_CNT_TRIGGER_RESET_8814B BIT(7) + +#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B 0 +#define BIT_MASK_TXOP_LMT_PKT_NUM_8814B 0x3f +#define BIT_TXOP_LMT_PKT_NUM_8814B(x) \ + (((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8814B) \ + << BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B) +#define BITS_TXOP_LMT_PKT_NUM_8814B \ + (BIT_MASK_TXOP_LMT_PKT_NUM_8814B << BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B) +#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8814B(x) \ + ((x) & (~BITS_TXOP_LMT_PKT_NUM_8814B)) +#define BIT_GET_TXOP_LMT_PKT_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B) & \ + BIT_MASK_TXOP_LMT_PKT_NUM_8814B) +#define BIT_SET_TXOP_LMT_PKT_NUM_8814B(x, v) \ + (BIT_CLEAR_TXOP_LMT_PKT_NUM_8814B(x) | BIT_TXOP_LMT_PKT_NUM_8814B(v)) -/* 2 REG_P2PPS_SPEC_STATE_8814B */ -#define BIT_SPEC_POWER_STATE_8814B BIT(7) -#define BIT_SPEC_CTWINDOW_ON_8814B BIT(6) -#define BIT_SPEC_BEACON_AREA_ON_8814B BIT(5) -#define BIT_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4) -#define BIT_SPEC_NOA1_OFF_PERIOD_8814B BIT(3) -#define BIT_SPEC_FORCE_DOZE1_8814B BIT(2) -#define BIT_SPEC_NOA0_OFF_PERIOD_8814B BIT(1) -#define BIT_SPEC_FORCE_DOZE0_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BAR_TX_CTRL_8814B */ +/* 2 REG_CCA_TXEN_CNT_8814B */ +#define BIT_CCA_TXEN_CNT_SWITCH_8814B BIT(17) +#define BIT_CCA_TXEN_CNT_EN_8814B BIT(16) + +#define BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B 8 +#define BIT_MASK_CCA_TXEN_BIG_CNT_8814B 0xff +#define BIT_CCA_TXEN_BIG_CNT_8814B(x) \ + (((x) & BIT_MASK_CCA_TXEN_BIG_CNT_8814B) \ + << BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B) +#define BITS_CCA_TXEN_BIG_CNT_8814B \ + (BIT_MASK_CCA_TXEN_BIG_CNT_8814B << BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B) +#define BIT_CLEAR_CCA_TXEN_BIG_CNT_8814B(x) \ + ((x) & (~BITS_CCA_TXEN_BIG_CNT_8814B)) +#define BIT_GET_CCA_TXEN_BIG_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B) & \ + BIT_MASK_CCA_TXEN_BIG_CNT_8814B) +#define BIT_SET_CCA_TXEN_BIG_CNT_8814B(x, v) \ + (BIT_CLEAR_CCA_TXEN_BIG_CNT_8814B(x) | BIT_CCA_TXEN_BIG_CNT_8814B(v)) + +#define BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B 0 +#define BIT_MASK_CCA_TXEN_SMALL_CNT_8814B 0xff +#define BIT_CCA_TXEN_SMALL_CNT_8814B(x) \ + (((x) & BIT_MASK_CCA_TXEN_SMALL_CNT_8814B) \ + << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B) +#define BITS_CCA_TXEN_SMALL_CNT_8814B \ + (BIT_MASK_CCA_TXEN_SMALL_CNT_8814B \ + << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B) +#define BIT_CLEAR_CCA_TXEN_SMALL_CNT_8814B(x) \ + ((x) & (~BITS_CCA_TXEN_SMALL_CNT_8814B)) +#define BIT_GET_CCA_TXEN_SMALL_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B) & \ + BIT_MASK_CCA_TXEN_SMALL_CNT_8814B) +#define BIT_SET_CCA_TXEN_SMALL_CNT_8814B(x, v) \ + (BIT_CLEAR_CCA_TXEN_SMALL_CNT_8814B(x) | \ + BIT_CCA_TXEN_SMALL_CNT_8814B(v)) /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_P2PON_DIS_TXTIME_8814B 0 -#define BIT_MASK_P2PON_DIS_TXTIME_8814B 0xff -#define BIT_P2PON_DIS_TXTIME_8814B(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8814B) << BIT_SHIFT_P2PON_DIS_TXTIME_8814B) -#define BIT_GET_P2PON_DIS_TXTIME_8814B(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8814B) & BIT_MASK_P2PON_DIS_TXTIME_8814B) +/* 2 REG_MAX_INTER_COLLISION_8814B */ + +#define BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B 24 +#define BIT_MASK_MAX_INTER_COLLISION_BK_8814B 0xff +#define BIT_MAX_INTER_COLLISION_BK_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_BK_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B) +#define BITS_MAX_INTER_COLLISION_BK_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_BK_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_BK_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_BK_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_BK_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_BK_8814B) +#define BIT_SET_MAX_INTER_COLLISION_BK_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_BK_8814B(x) | \ + BIT_MAX_INTER_COLLISION_BK_8814B(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B 16 +#define BIT_MASK_MAX_INTER_COLLISION_BE_8814B 0xff +#define BIT_MAX_INTER_COLLISION_BE_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_BE_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B) +#define BITS_MAX_INTER_COLLISION_BE_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_BE_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_BE_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_BE_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_BE_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_BE_8814B) +#define BIT_SET_MAX_INTER_COLLISION_BE_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_BE_8814B(x) | \ + BIT_MAX_INTER_COLLISION_BE_8814B(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B 8 +#define BIT_MASK_MAX_INTER_COLLISION_VI_8814B 0xff +#define BIT_MAX_INTER_COLLISION_VI_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_VI_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B) +#define BITS_MAX_INTER_COLLISION_VI_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_VI_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_VI_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_VI_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_VI_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_VI_8814B) +#define BIT_SET_MAX_INTER_COLLISION_VI_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_VI_8814B(x) | \ + BIT_MAX_INTER_COLLISION_VI_8814B(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B 0 +#define BIT_MASK_MAX_INTER_COLLISION_VO_8814B 0xff +#define BIT_MAX_INTER_COLLISION_VO_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_VO_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B) +#define BITS_MAX_INTER_COLLISION_VO_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_VO_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_VO_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_VO_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_VO_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_VO_8814B) +#define BIT_SET_MAX_INTER_COLLISION_VO_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_VO_8814B(x) | \ + BIT_MAX_INTER_COLLISION_VO_8814B(v)) + +/* 2 REG_MAX_INTER_COLLISION_CNT_8814B */ +#define BIT_MAX_INTER_COLLISION_EN_8814B BIT(16) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B 12 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B 0xf +#define BIT_MAX_INTER_COLLISION_CNT_BK_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B) +#define BITS_MAX_INTER_COLLISION_CNT_BK_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_BK_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B) +#define BIT_SET_MAX_INTER_COLLISION_CNT_BK_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8814B(x) | \ + BIT_MAX_INTER_COLLISION_CNT_BK_8814B(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B 8 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B 0xf +#define BIT_MAX_INTER_COLLISION_CNT_BE_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B) +#define BITS_MAX_INTER_COLLISION_CNT_BE_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_BE_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B) +#define BIT_SET_MAX_INTER_COLLISION_CNT_BE_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8814B(x) | \ + BIT_MAX_INTER_COLLISION_CNT_BE_8814B(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B 4 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B 0xf +#define BIT_MAX_INTER_COLLISION_CNT_VI_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B) +#define BITS_MAX_INTER_COLLISION_CNT_VI_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_VI_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B) +#define BIT_SET_MAX_INTER_COLLISION_CNT_VI_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8814B(x) | \ + BIT_MAX_INTER_COLLISION_CNT_VI_8814B(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B 0 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B 0xf +#define BIT_MAX_INTER_COLLISION_CNT_VO_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B) +#define BITS_MAX_INTER_COLLISION_CNT_VO_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_VO_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B) +#define BIT_SET_MAX_INTER_COLLISION_CNT_VO_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8814B(x) | \ + BIT_MAX_INTER_COLLISION_CNT_VO_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_RD_NAV_NXT_8814B */ + +#define BIT_SHIFT_RD_NAV_PROT_NXT_8814B 0 +#define BIT_MASK_RD_NAV_PROT_NXT_8814B 0xffff +#define BIT_RD_NAV_PROT_NXT_8814B(x) \ + (((x) & BIT_MASK_RD_NAV_PROT_NXT_8814B) \ + << BIT_SHIFT_RD_NAV_PROT_NXT_8814B) +#define BITS_RD_NAV_PROT_NXT_8814B \ + (BIT_MASK_RD_NAV_PROT_NXT_8814B << BIT_SHIFT_RD_NAV_PROT_NXT_8814B) +#define BIT_CLEAR_RD_NAV_PROT_NXT_8814B(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8814B)) +#define BIT_GET_RD_NAV_PROT_NXT_8814B(x) \ + (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8814B) & \ + BIT_MASK_RD_NAV_PROT_NXT_8814B) +#define BIT_SET_RD_NAV_PROT_NXT_8814B(x, v) \ + (BIT_CLEAR_RD_NAV_PROT_NXT_8814B(x) | BIT_RD_NAV_PROT_NXT_8814B(v)) +/* 2 REG_NAV_PROT_LEN_8814B */ +#define BIT_SHIFT_NAV_PROT_LEN_8814B 0 +#define BIT_MASK_NAV_PROT_LEN_8814B 0xffff +#define BIT_NAV_PROT_LEN_8814B(x) \ + (((x) & BIT_MASK_NAV_PROT_LEN_8814B) << BIT_SHIFT_NAV_PROT_LEN_8814B) +#define BITS_NAV_PROT_LEN_8814B \ + (BIT_MASK_NAV_PROT_LEN_8814B << BIT_SHIFT_NAV_PROT_LEN_8814B) +#define BIT_CLEAR_NAV_PROT_LEN_8814B(x) ((x) & (~BITS_NAV_PROT_LEN_8814B)) +#define BIT_GET_NAV_PROT_LEN_8814B(x) \ + (((x) >> BIT_SHIFT_NAV_PROT_LEN_8814B) & BIT_MASK_NAV_PROT_LEN_8814B) +#define BIT_SET_NAV_PROT_LEN_8814B(x, v) \ + (BIT_CLEAR_NAV_PROT_LEN_8814B(x) | BIT_NAV_PROT_LEN_8814B(v)) + +/* 2 REG_FTM_PTT_8814B */ + +#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B 22 +#define BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B 0x7 +#define BIT_FTM_PTT_TSF_R2T_SEL_8814B(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B) \ + << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B) +#define BITS_FTM_PTT_TSF_R2T_SEL_8814B \ + (BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B \ + << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B) +#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8814B(x) \ + ((x) & (~BITS_FTM_PTT_TSF_R2T_SEL_8814B)) +#define BIT_GET_FTM_PTT_TSF_R2T_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B) & \ + BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B) +#define BIT_SET_FTM_PTT_TSF_R2T_SEL_8814B(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8814B(x) | \ + BIT_FTM_PTT_TSF_R2T_SEL_8814B(v)) + +#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B 19 +#define BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B 0x7 +#define BIT_FTM_PTT_TSF_T2R_SEL_8814B(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B) \ + << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B) +#define BITS_FTM_PTT_TSF_T2R_SEL_8814B \ + (BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B \ + << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B) +#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8814B(x) \ + ((x) & (~BITS_FTM_PTT_TSF_T2R_SEL_8814B)) +#define BIT_GET_FTM_PTT_TSF_T2R_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B) & \ + BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B) +#define BIT_SET_FTM_PTT_TSF_T2R_SEL_8814B(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8814B(x) | \ + BIT_FTM_PTT_TSF_T2R_SEL_8814B(v)) + +#define BIT_SHIFT_FTM_PTT_TSF_SEL_8814B 16 +#define BIT_MASK_FTM_PTT_TSF_SEL_8814B 0x7 +#define BIT_FTM_PTT_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_SEL_8814B) \ + << BIT_SHIFT_FTM_PTT_TSF_SEL_8814B) +#define BITS_FTM_PTT_TSF_SEL_8814B \ + (BIT_MASK_FTM_PTT_TSF_SEL_8814B << BIT_SHIFT_FTM_PTT_TSF_SEL_8814B) +#define BIT_CLEAR_FTM_PTT_TSF_SEL_8814B(x) ((x) & (~BITS_FTM_PTT_TSF_SEL_8814B)) +#define BIT_GET_FTM_PTT_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL_8814B) & \ + BIT_MASK_FTM_PTT_TSF_SEL_8814B) +#define BIT_SET_FTM_PTT_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_SEL_8814B(x) | BIT_FTM_PTT_TSF_SEL_8814B(v)) + +#define BIT_SHIFT_FTM_PTT_VALUE_8814B 0 +#define BIT_MASK_FTM_PTT_VALUE_8814B 0xffff +#define BIT_FTM_PTT_VALUE_8814B(x) \ + (((x) & BIT_MASK_FTM_PTT_VALUE_8814B) << BIT_SHIFT_FTM_PTT_VALUE_8814B) +#define BITS_FTM_PTT_VALUE_8814B \ + (BIT_MASK_FTM_PTT_VALUE_8814B << BIT_SHIFT_FTM_PTT_VALUE_8814B) +#define BIT_CLEAR_FTM_PTT_VALUE_8814B(x) ((x) & (~BITS_FTM_PTT_VALUE_8814B)) +#define BIT_GET_FTM_PTT_VALUE_8814B(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_VALUE_8814B) & BIT_MASK_FTM_PTT_VALUE_8814B) +#define BIT_SET_FTM_PTT_VALUE_8814B(x, v) \ + (BIT_CLEAR_FTM_PTT_VALUE_8814B(x) | BIT_FTM_PTT_VALUE_8814B(v)) + +/* 2 REG_FTM_TSF_8814B */ + +#define BIT_SHIFT_FTM_T2_TSF_8814B 16 +#define BIT_MASK_FTM_T2_TSF_8814B 0xffff +#define BIT_FTM_T2_TSF_8814B(x) \ + (((x) & BIT_MASK_FTM_T2_TSF_8814B) << BIT_SHIFT_FTM_T2_TSF_8814B) +#define BITS_FTM_T2_TSF_8814B \ + (BIT_MASK_FTM_T2_TSF_8814B << BIT_SHIFT_FTM_T2_TSF_8814B) +#define BIT_CLEAR_FTM_T2_TSF_8814B(x) ((x) & (~BITS_FTM_T2_TSF_8814B)) +#define BIT_GET_FTM_T2_TSF_8814B(x) \ + (((x) >> BIT_SHIFT_FTM_T2_TSF_8814B) & BIT_MASK_FTM_T2_TSF_8814B) +#define BIT_SET_FTM_T2_TSF_8814B(x, v) \ + (BIT_CLEAR_FTM_T2_TSF_8814B(x) | BIT_FTM_T2_TSF_8814B(v)) + +#define BIT_SHIFT_FTM_T1_TSF_8814B 0 +#define BIT_MASK_FTM_T1_TSF_8814B 0xffff +#define BIT_FTM_T1_TSF_8814B(x) \ + (((x) & BIT_MASK_FTM_T1_TSF_8814B) << BIT_SHIFT_FTM_T1_TSF_8814B) +#define BITS_FTM_T1_TSF_8814B \ + (BIT_MASK_FTM_T1_TSF_8814B << BIT_SHIFT_FTM_T1_TSF_8814B) +#define BIT_CLEAR_FTM_T1_TSF_8814B(x) ((x) & (~BITS_FTM_T1_TSF_8814B)) +#define BIT_GET_FTM_T1_TSF_8814B(x) \ + (((x) >> BIT_SHIFT_FTM_T1_TSF_8814B) & BIT_MASK_FTM_T1_TSF_8814B) +#define BIT_SET_FTM_T1_TSF_8814B(x, v) \ + (BIT_CLEAR_FTM_T1_TSF_8814B(x) | BIT_FTM_T1_TSF_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -7452,334 +17946,1189 @@ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TBTT_PROHIBIT_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8814B 8 -#define BIT_MASK_TBTT_HOLD_TIME_AP_8814B 0xfff -#define BIT_TBTT_HOLD_TIME_AP_8814B(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8814B) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8814B) -#define BIT_GET_TBTT_HOLD_TIME_AP_8814B(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8814B) & BIT_MASK_TBTT_HOLD_TIME_AP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B 0 -#define BIT_MASK_TBTT_PROHIBIT_SETUP_8814B 0xf -#define BIT_TBTT_PROHIBIT_SETUP_8814B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8814B) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) -#define BIT_GET_TBTT_PROHIBIT_SETUP_8814B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) & BIT_MASK_TBTT_PROHIBIT_SETUP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_P2PPS_STATE_8814B */ -#define BIT_POWER_STATE_8814B BIT(7) -#define BIT_CTWINDOW_ON_8814B BIT(6) -#define BIT_BEACON_AREA_ON_8814B BIT(5) -#define BIT_CTWIN_EARLY_DISTX_8814B BIT(4) -#define BIT_NOA1_OFF_PERIOD_8814B BIT(3) -#define BIT_FORCE_DOZE1_8814B BIT(2) -#define BIT_NOA0_OFF_PERIOD_8814B BIT(1) -#define BIT_FORCE_DOZE0_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_HGQ_TIMEOUT_PERIOD_8814B */ + +#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B 0 +#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B 0xff +#define BIT_HGQ_TIMEOUT_PERIOD_8814B(x) \ + (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B) \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) +#define BITS_HGQ_TIMEOUT_PERIOD_8814B \ + (BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8814B(x) \ + ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8814B)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8814B(x) \ + (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) & \ + BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B) +#define BIT_SET_HGQ_TIMEOUT_PERIOD_8814B(x, v) \ + (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8814B(x) | \ + BIT_HGQ_TIMEOUT_PERIOD_8814B(v)) + +/* 2 REG_TXCMD_TIMEOUT_PERIOD_8814B */ + +#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B 0 +#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B 0xff +#define BIT_TXCMD_TIMEOUT_PERIOD_8814B(x) \ + (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B) \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) +#define BITS_TXCMD_TIMEOUT_PERIOD_8814B \ + (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8814B(x) \ + ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8814B)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8814B(x) \ + (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) & \ + BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8814B(x, v) \ + (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8814B(x) | \ + BIT_TXCMD_TIMEOUT_PERIOD_8814B(v)) + +/* 2 REG_MISC_CTRL_8814B */ +#define BIT_DIS_SECONDARY_CCA_80M_8814B BIT(2) +#define BIT_DIS_SECONDARY_CCA_40M_8814B BIT(1) +#define BIT_DIS_SECONDARY_CCA_20M_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RD_NAV_NXT_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_RD_NAV_PROT_NXT_8814B 0 -#define BIT_MASK_RD_NAV_PROT_NXT_8814B 0xffff -#define BIT_RD_NAV_PROT_NXT_8814B(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8814B) << BIT_SHIFT_RD_NAV_PROT_NXT_8814B) -#define BIT_GET_RD_NAV_PROT_NXT_8814B(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8814B) & BIT_MASK_RD_NAV_PROT_NXT_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NAV_PROT_LEN_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NAV_PROT_LEN_8814B 0 -#define BIT_MASK_NAV_PROT_LEN_8814B 0xffff -#define BIT_NAV_PROT_LEN_8814B(x) (((x) & BIT_MASK_NAV_PROT_LEN_8814B) << BIT_SHIFT_NAV_PROT_LEN_8814B) -#define BIT_GET_NAV_PROT_LEN_8814B(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8814B) & BIT_MASK_NAV_PROT_LEN_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BCN_CTRL_8814B */ -#define BIT_DIS_RX_BSSID_FIT_8814B BIT(6) -#define BIT_P0_EN_TXBCN_RPT_8814B BIT(5) -#define BIT_DIS_TSF_UDT_8814B BIT(4) -#define BIT_EN_BCN_FUNCTION_8814B BIT(3) -#define BIT_P0_EN_RXBCN_RPT_8814B BIT(2) -#define BIT_EN_P2P_CTWINDOW_8814B BIT(1) -#define BIT_EN_P2P_BCNQ_AREA_8814B BIT(0) +/* 2 REG_TXOP_MIN_8814B */ +#define BIT_HIQ_NAV_BREAK_EN_8814B BIT(15) +#define BIT_MGQ_NAV_BREAK_EN_8814B BIT(14) -/* 2 REG_BCN_CTRL_CLINT0_8814B */ -#define BIT_CLI0_DIS_RX_BSSID_FIT_8814B BIT(6) -#define BIT_CLI0_DIS_TSF_UDT_8814B BIT(4) -#define BIT_CLI0_EN_BCN_FUNCTION_8814B BIT(3) -#define BIT_CLI0_EN_RXBCN_RPT_8814B BIT(2) -#define BIT_CLI0_ENP2P_CTWINDOW_8814B BIT(1) -#define BIT_CLI0_ENP2P_BCNQ_AREA_8814B BIT(0) +#define BIT_SHIFT_TXOP_MIN_8814B 0 +#define BIT_MASK_TXOP_MIN_8814B 0x3fff +#define BIT_TXOP_MIN_8814B(x) \ + (((x) & BIT_MASK_TXOP_MIN_8814B) << BIT_SHIFT_TXOP_MIN_8814B) +#define BITS_TXOP_MIN_8814B \ + (BIT_MASK_TXOP_MIN_8814B << BIT_SHIFT_TXOP_MIN_8814B) +#define BIT_CLEAR_TXOP_MIN_8814B(x) ((x) & (~BITS_TXOP_MIN_8814B)) +#define BIT_GET_TXOP_MIN_8814B(x) \ + (((x) >> BIT_SHIFT_TXOP_MIN_8814B) & BIT_MASK_TXOP_MIN_8814B) +#define BIT_SET_TXOP_MIN_8814B(x, v) \ + (BIT_CLEAR_TXOP_MIN_8814B(x) | BIT_TXOP_MIN_8814B(v)) -/* 2 REG_MBID_NUM_8814B */ -#define BIT_EN_PRE_DL_BEACON_8814B BIT(3) +/* 2 REG_PRE_BKF_TIME_8814B */ -#define BIT_SHIFT_MBID_BCN_NUM_8814B 0 -#define BIT_MASK_MBID_BCN_NUM_8814B 0x7 -#define BIT_MBID_BCN_NUM_8814B(x) (((x) & BIT_MASK_MBID_BCN_NUM_8814B) << BIT_SHIFT_MBID_BCN_NUM_8814B) -#define BIT_GET_MBID_BCN_NUM_8814B(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8814B) & BIT_MASK_MBID_BCN_NUM_8814B) +#define BIT_SHIFT_PRE_BKF_TIME_8814B 0 +#define BIT_MASK_PRE_BKF_TIME_8814B 0xff +#define BIT_PRE_BKF_TIME_8814B(x) \ + (((x) & BIT_MASK_PRE_BKF_TIME_8814B) << BIT_SHIFT_PRE_BKF_TIME_8814B) +#define BITS_PRE_BKF_TIME_8814B \ + (BIT_MASK_PRE_BKF_TIME_8814B << BIT_SHIFT_PRE_BKF_TIME_8814B) +#define BIT_CLEAR_PRE_BKF_TIME_8814B(x) ((x) & (~BITS_PRE_BKF_TIME_8814B)) +#define BIT_GET_PRE_BKF_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PRE_BKF_TIME_8814B) & BIT_MASK_PRE_BKF_TIME_8814B) +#define BIT_SET_PRE_BKF_TIME_8814B(x, v) \ + (BIT_CLEAR_PRE_BKF_TIME_8814B(x) | BIT_PRE_BKF_TIME_8814B(v)) +/* 2 REG_CROSS_TXOP_CTRL_8814B */ +#define BIT_TBTT_RETRY_8814B BIT(4) +#define BIT_TXFAIL_BREACK_TXOP_EN_8814B BIT(3) +#define BIT_RTS_NAV_TXOP_8814B BIT(1) +#define BIT_NOT_CROSS_TXOP_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DUAL_TSF_RST_8814B */ -#define BIT_FREECNT_RST_8814B BIT(5) -#define BIT_TSFTR_CLI3_RST_8814B BIT(4) -#define BIT_TSFTR_CLI2_RST_8814B BIT(3) -#define BIT_TSFTR_CLI1_RST_8814B BIT(2) -#define BIT_TSFTR_CLI0_RST_8814B BIT(1) -#define BIT_TSFTR_RST_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_MBSSID_BCN_SPACE_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8814B 28 -#define BIT_MASK_BCN_TIMER_SEL_FWRD_8814B 0x7 -#define BIT_BCN_TIMER_SEL_FWRD_8814B(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8814B) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8814B) -#define BIT_GET_BCN_TIMER_SEL_FWRD_8814B(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8814B) & BIT_MASK_BCN_TIMER_SEL_FWRD_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_SPACE_CLINT0_8814B 16 -#define BIT_MASK_BCN_SPACE_CLINT0_8814B 0xfff -#define BIT_BCN_SPACE_CLINT0_8814B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8814B) << BIT_SHIFT_BCN_SPACE_CLINT0_8814B) -#define BIT_GET_BCN_SPACE_CLINT0_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8814B) & BIT_MASK_BCN_SPACE_CLINT0_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_SPACE0_8814B 0 -#define BIT_MASK_BCN_SPACE0_8814B 0xffff -#define BIT_BCN_SPACE0_8814B(x) (((x) & BIT_MASK_BCN_SPACE0_8814B) << BIT_SHIFT_BCN_SPACE0_8814B) -#define BIT_GET_BCN_SPACE0_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8814B) & BIT_MASK_BCN_SPACE0_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DRVERLYINT_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DRVERLYITV_8814B 0 -#define BIT_MASK_DRVERLYITV_8814B 0xff -#define BIT_DRVERLYITV_8814B(x) (((x) & BIT_MASK_DRVERLYITV_8814B) << BIT_SHIFT_DRVERLYITV_8814B) -#define BIT_GET_DRVERLYITV_8814B(x) (((x) >> BIT_SHIFT_DRVERLYITV_8814B) & BIT_MASK_DRVERLYITV_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BCNDMATIM_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCNDMATIM_8814B 0 -#define BIT_MASK_BCNDMATIM_8814B 0xff -#define BIT_BCNDMATIM_8814B(x) (((x) & BIT_MASK_BCNDMATIM_8814B) << BIT_SHIFT_BCNDMATIM_8814B) -#define BIT_GET_BCNDMATIM_8814B(x) (((x) >> BIT_SHIFT_BCNDMATIM_8814B) & BIT_MASK_BCNDMATIM_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_ATIMWND_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_ATIMWND0_8814B 0 -#define BIT_MASK_ATIMWND0_8814B 0xffff -#define BIT_ATIMWND0_8814B(x) (((x) & BIT_MASK_ATIMWND0_8814B) << BIT_SHIFT_ATIMWND0_8814B) -#define BIT_GET_ATIMWND0_8814B(x) (((x) >> BIT_SHIFT_ATIMWND0_8814B) & BIT_MASK_ATIMWND0_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_USTIME_TSF_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_USTIME_TSF_V1_8814B 0 -#define BIT_MASK_USTIME_TSF_V1_8814B 0xff -#define BIT_USTIME_TSF_V1_8814B(x) (((x) & BIT_MASK_USTIME_TSF_V1_8814B) << BIT_SHIFT_USTIME_TSF_V1_8814B) -#define BIT_GET_USTIME_TSF_V1_8814B(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8814B) & BIT_MASK_USTIME_TSF_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BCN_MAX_ERR_8814B */ +/* 2 REG_ACMHWCTRL_8814B */ +#define BIT_BEQ_ACM_STATUS_8814B BIT(7) +#define BIT_VIQ_ACM_STATUS_8814B BIT(6) +#define BIT_VOQ_ACM_STATUS_8814B BIT(5) +#define BIT_BEQ_ACM_EN_8814B BIT(3) +#define BIT_VIQ_ACM_EN_8814B BIT(2) +#define BIT_VOQ_ACM_EN_8814B BIT(1) +#define BIT_ACMHWEN_8814B BIT(0) -#define BIT_SHIFT_BCN_MAX_ERR_8814B 0 -#define BIT_MASK_BCN_MAX_ERR_8814B 0xff -#define BIT_BCN_MAX_ERR_8814B(x) (((x) & BIT_MASK_BCN_MAX_ERR_8814B) << BIT_SHIFT_BCN_MAX_ERR_8814B) -#define BIT_GET_BCN_MAX_ERR_8814B(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8814B) & BIT_MASK_BCN_MAX_ERR_8814B) +/* 2 REG_ACMRSTCTRL_8814B */ +#define BIT_BE_ACM_RESET_USED_TIME_8814B BIT(2) +#define BIT_VI_ACM_RESET_USED_TIME_8814B BIT(1) +#define BIT_VO_ACM_RESET_USED_TIME_8814B BIT(0) +/* 2 REG_ACMAVG_8814B */ +#define BIT_SHIFT_AVGPERIOD_8814B 0 +#define BIT_MASK_AVGPERIOD_8814B 0xffff +#define BIT_AVGPERIOD_8814B(x) \ + (((x) & BIT_MASK_AVGPERIOD_8814B) << BIT_SHIFT_AVGPERIOD_8814B) +#define BITS_AVGPERIOD_8814B \ + (BIT_MASK_AVGPERIOD_8814B << BIT_SHIFT_AVGPERIOD_8814B) +#define BIT_CLEAR_AVGPERIOD_8814B(x) ((x) & (~BITS_AVGPERIOD_8814B)) +#define BIT_GET_AVGPERIOD_8814B(x) \ + (((x) >> BIT_SHIFT_AVGPERIOD_8814B) & BIT_MASK_AVGPERIOD_8814B) +#define BIT_SET_AVGPERIOD_8814B(x, v) \ + (BIT_CLEAR_AVGPERIOD_8814B(x) | BIT_AVGPERIOD_8814B(v)) -/* 2 REG_RXTSF_OFFSET_CCK_8814B */ +/* 2 REG_VO_ADMTIME_8814B */ -#define BIT_SHIFT_CCK_RXTSF_OFFSET_8814B 0 -#define BIT_MASK_CCK_RXTSF_OFFSET_8814B 0xff -#define BIT_CCK_RXTSF_OFFSET_8814B(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8814B) << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) -#define BIT_GET_CCK_RXTSF_OFFSET_8814B(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) & BIT_MASK_CCK_RXTSF_OFFSET_8814B) +#define BIT_SHIFT_VO_ADMITTED_TIME_8814B 0 +#define BIT_MASK_VO_ADMITTED_TIME_8814B 0xffff +#define BIT_VO_ADMITTED_TIME_8814B(x) \ + (((x) & BIT_MASK_VO_ADMITTED_TIME_8814B) \ + << BIT_SHIFT_VO_ADMITTED_TIME_8814B) +#define BITS_VO_ADMITTED_TIME_8814B \ + (BIT_MASK_VO_ADMITTED_TIME_8814B << BIT_SHIFT_VO_ADMITTED_TIME_8814B) +#define BIT_CLEAR_VO_ADMITTED_TIME_8814B(x) \ + ((x) & (~BITS_VO_ADMITTED_TIME_8814B)) +#define BIT_GET_VO_ADMITTED_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8814B) & \ + BIT_MASK_VO_ADMITTED_TIME_8814B) +#define BIT_SET_VO_ADMITTED_TIME_8814B(x, v) \ + (BIT_CLEAR_VO_ADMITTED_TIME_8814B(x) | BIT_VO_ADMITTED_TIME_8814B(v)) +/* 2 REG_VI_ADMTIME_8814B */ +#define BIT_SHIFT_VI_ADMITTED_TIME_8814B 0 +#define BIT_MASK_VI_ADMITTED_TIME_8814B 0xffff +#define BIT_VI_ADMITTED_TIME_8814B(x) \ + (((x) & BIT_MASK_VI_ADMITTED_TIME_8814B) \ + << BIT_SHIFT_VI_ADMITTED_TIME_8814B) +#define BITS_VI_ADMITTED_TIME_8814B \ + (BIT_MASK_VI_ADMITTED_TIME_8814B << BIT_SHIFT_VI_ADMITTED_TIME_8814B) +#define BIT_CLEAR_VI_ADMITTED_TIME_8814B(x) \ + ((x) & (~BITS_VI_ADMITTED_TIME_8814B)) +#define BIT_GET_VI_ADMITTED_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8814B) & \ + BIT_MASK_VI_ADMITTED_TIME_8814B) +#define BIT_SET_VI_ADMITTED_TIME_8814B(x, v) \ + (BIT_CLEAR_VI_ADMITTED_TIME_8814B(x) | BIT_VI_ADMITTED_TIME_8814B(v)) -/* 2 REG_RXTSF_OFFSET_OFDM_8814B */ +/* 2 REG_BE_ADMTIME_8814B */ -#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B 0 -#define BIT_MASK_OFDM_RXTSF_OFFSET_8814B 0xff -#define BIT_OFDM_RXTSF_OFFSET_8814B(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8814B) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) -#define BIT_GET_OFDM_RXTSF_OFFSET_8814B(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) & BIT_MASK_OFDM_RXTSF_OFFSET_8814B) +#define BIT_SHIFT_BE_ADMITTED_TIME_8814B 0 +#define BIT_MASK_BE_ADMITTED_TIME_8814B 0xffff +#define BIT_BE_ADMITTED_TIME_8814B(x) \ + (((x) & BIT_MASK_BE_ADMITTED_TIME_8814B) \ + << BIT_SHIFT_BE_ADMITTED_TIME_8814B) +#define BITS_BE_ADMITTED_TIME_8814B \ + (BIT_MASK_BE_ADMITTED_TIME_8814B << BIT_SHIFT_BE_ADMITTED_TIME_8814B) +#define BIT_CLEAR_BE_ADMITTED_TIME_8814B(x) \ + ((x) & (~BITS_BE_ADMITTED_TIME_8814B)) +#define BIT_GET_BE_ADMITTED_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8814B) & \ + BIT_MASK_BE_ADMITTED_TIME_8814B) +#define BIT_SET_BE_ADMITTED_TIME_8814B(x, v) \ + (BIT_CLEAR_BE_ADMITTED_TIME_8814B(x) | BIT_BE_ADMITTED_TIME_8814B(v)) + +/* 2 REG_MAC_HEADER_NAV_OFFSET_8814B */ + +#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B 0 +#define BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B 0xff +#define BIT_MAC_HEADER_NAV_OFFSET_8814B(x) \ + (((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B) \ + << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B) +#define BITS_MAC_HEADER_NAV_OFFSET_8814B \ + (BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B \ + << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B) +#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8814B(x) \ + ((x) & (~BITS_MAC_HEADER_NAV_OFFSET_8814B)) +#define BIT_GET_MAC_HEADER_NAV_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B) & \ + BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B) +#define BIT_SET_MAC_HEADER_NAV_OFFSET_8814B(x, v) \ + (BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8814B(x) | \ + BIT_MAC_HEADER_NAV_OFFSET_8814B(v)) + +/* 2 REG_DIS_NDPA_NAV_CHECK_8814B */ +#define BIT_DIS_NDPA_NAV_CHECK_8814B BIT(0) +/* 2 REG_EDCA_RANDOM_GEN_8814B */ +#define BIT_SHIFT_RANDOM_GEN_8814B 0 +#define BIT_MASK_RANDOM_GEN_8814B 0xffffff +#define BIT_RANDOM_GEN_8814B(x) \ + (((x) & BIT_MASK_RANDOM_GEN_8814B) << BIT_SHIFT_RANDOM_GEN_8814B) +#define BITS_RANDOM_GEN_8814B \ + (BIT_MASK_RANDOM_GEN_8814B << BIT_SHIFT_RANDOM_GEN_8814B) +#define BIT_CLEAR_RANDOM_GEN_8814B(x) ((x) & (~BITS_RANDOM_GEN_8814B)) +#define BIT_GET_RANDOM_GEN_8814B(x) \ + (((x) >> BIT_SHIFT_RANDOM_GEN_8814B) & BIT_MASK_RANDOM_GEN_8814B) +#define BIT_SET_RANDOM_GEN_8814B(x, v) \ + (BIT_CLEAR_RANDOM_GEN_8814B(x) | BIT_RANDOM_GEN_8814B(v)) + +/* 2 REG_TXCMD_SEL_8814B */ -/* 2 REG_TSFTR_8814B */ +#define BIT_SHIFT_TXCMD_SEG_SEL_8814B 0 +#define BIT_MASK_TXCMD_SEG_SEL_8814B 0xf +#define BIT_TXCMD_SEG_SEL_8814B(x) \ + (((x) & BIT_MASK_TXCMD_SEG_SEL_8814B) << BIT_SHIFT_TXCMD_SEG_SEL_8814B) +#define BITS_TXCMD_SEG_SEL_8814B \ + (BIT_MASK_TXCMD_SEG_SEL_8814B << BIT_SHIFT_TXCMD_SEG_SEL_8814B) +#define BIT_CLEAR_TXCMD_SEG_SEL_8814B(x) ((x) & (~BITS_TXCMD_SEG_SEL_8814B)) +#define BIT_GET_TXCMD_SEG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8814B) & BIT_MASK_TXCMD_SEG_SEL_8814B) +#define BIT_SET_TXCMD_SEG_SEL_8814B(x, v) \ + (BIT_CLEAR_TXCMD_SEG_SEL_8814B(x) | BIT_TXCMD_SEG_SEL_8814B(v)) -#define BIT_SHIFT_TSF_TIMER_V1_8814B 0 -#define BIT_MASK_TSF_TIMER_V1_8814B 0xffffffffL -#define BIT_TSF_TIMER_V1_8814B(x) (((x) & BIT_MASK_TSF_TIMER_V1_8814B) << BIT_SHIFT_TSF_TIMER_V1_8814B) -#define BIT_GET_TSF_TIMER_V1_8814B(x) (((x) >> BIT_SHIFT_TSF_TIMER_V1_8814B) & BIT_MASK_TSF_TIMER_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TSFTR_1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TSF_TIMER_V2_8814B 0 -#define BIT_MASK_TSF_TIMER_V2_8814B 0xffffffffL -#define BIT_TSF_TIMER_V2_8814B(x) (((x) & BIT_MASK_TSF_TIMER_V2_8814B) << BIT_SHIFT_TSF_TIMER_V2_8814B) -#define BIT_GET_TSF_TIMER_V2_8814B(x) (((x) >> BIT_SHIFT_TSF_TIMER_V2_8814B) & BIT_MASK_TSF_TIMER_V2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_MU_DBG_INFO_8814B */ + +#define BIT_SHIFT_MU_DBG_INFO_8814B 0 +#define BIT_MASK_MU_DBG_INFO_8814B 0xffffffffL +#define BIT_MU_DBG_INFO_8814B(x) \ + (((x) & BIT_MASK_MU_DBG_INFO_8814B) << BIT_SHIFT_MU_DBG_INFO_8814B) +#define BITS_MU_DBG_INFO_8814B \ + (BIT_MASK_MU_DBG_INFO_8814B << BIT_SHIFT_MU_DBG_INFO_8814B) +#define BIT_CLEAR_MU_DBG_INFO_8814B(x) ((x) & (~BITS_MU_DBG_INFO_8814B)) +#define BIT_GET_MU_DBG_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_MU_DBG_INFO_8814B) & BIT_MASK_MU_DBG_INFO_8814B) +#define BIT_SET_MU_DBG_INFO_8814B(x, v) \ + (BIT_CLEAR_MU_DBG_INFO_8814B(x) | BIT_MU_DBG_INFO_8814B(v)) + +/* 2 REG_MU_DBG_INFO_1_8814B */ + +#define BIT_SHIFT_MU_DBG_INFO_1_8814B 0 +#define BIT_MASK_MU_DBG_INFO_1_8814B 0xffffffffL +#define BIT_MU_DBG_INFO_1_8814B(x) \ + (((x) & BIT_MASK_MU_DBG_INFO_1_8814B) << BIT_SHIFT_MU_DBG_INFO_1_8814B) +#define BITS_MU_DBG_INFO_1_8814B \ + (BIT_MASK_MU_DBG_INFO_1_8814B << BIT_SHIFT_MU_DBG_INFO_1_8814B) +#define BIT_CLEAR_MU_DBG_INFO_1_8814B(x) ((x) & (~BITS_MU_DBG_INFO_1_8814B)) +#define BIT_GET_MU_DBG_INFO_1_8814B(x) \ + (((x) >> BIT_SHIFT_MU_DBG_INFO_1_8814B) & BIT_MASK_MU_DBG_INFO_1_8814B) +#define BIT_SET_MU_DBG_INFO_1_8814B(x, v) \ + (BIT_CLEAR_MU_DBG_INFO_1_8814B(x) | BIT_MU_DBG_INFO_1_8814B(v)) + +/* 2 REG_SCH_DBG_SEL_8814B */ + +#define BIT_SHIFT_SCH_DBG_SEL_8814B 0 +#define BIT_MASK_SCH_DBG_SEL_8814B 0xff +#define BIT_SCH_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_SCH_DBG_SEL_8814B) << BIT_SHIFT_SCH_DBG_SEL_8814B) +#define BITS_SCH_DBG_SEL_8814B \ + (BIT_MASK_SCH_DBG_SEL_8814B << BIT_SHIFT_SCH_DBG_SEL_8814B) +#define BIT_CLEAR_SCH_DBG_SEL_8814B(x) ((x) & (~BITS_SCH_DBG_SEL_8814B)) +#define BIT_GET_SCH_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_SCH_DBG_SEL_8814B) & BIT_MASK_SCH_DBG_SEL_8814B) +#define BIT_SET_SCH_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_SCH_DBG_SEL_8814B(x) | BIT_SCH_DBG_SEL_8814B(v)) -/* 2 REG_FREERUN_CNT_8814B */ +/* 2 REG_SCHEDULER_RST_8814B */ +#define BIT_SCHEDULER_RST_V1_8814B BIT(0) -#define BIT_SHIFT_FREERUN_CNT_V1_8814B 0 -#define BIT_MASK_FREERUN_CNT_V1_8814B 0xffffffffL -#define BIT_FREERUN_CNT_V1_8814B(x) (((x) & BIT_MASK_FREERUN_CNT_V1_8814B) << BIT_SHIFT_FREERUN_CNT_V1_8814B) -#define BIT_GET_FREERUN_CNT_V1_8814B(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8814B) & BIT_MASK_FREERUN_CNT_V1_8814B) +/* 2 REG_MU_DBG_ERR_FLAG_8814B */ +#define BIT_BCN_PORTID_ERR_8814B BIT(2) + +#define BIT_SHIFT_MU_DBG_ERR_FLAG_8814B 0 +#define BIT_MASK_MU_DBG_ERR_FLAG_8814B 0x3 +#define BIT_MU_DBG_ERR_FLAG_8814B(x) \ + (((x) & BIT_MASK_MU_DBG_ERR_FLAG_8814B) \ + << BIT_SHIFT_MU_DBG_ERR_FLAG_8814B) +#define BITS_MU_DBG_ERR_FLAG_8814B \ + (BIT_MASK_MU_DBG_ERR_FLAG_8814B << BIT_SHIFT_MU_DBG_ERR_FLAG_8814B) +#define BIT_CLEAR_MU_DBG_ERR_FLAG_8814B(x) ((x) & (~BITS_MU_DBG_ERR_FLAG_8814B)) +#define BIT_GET_MU_DBG_ERR_FLAG_8814B(x) \ + (((x) >> BIT_SHIFT_MU_DBG_ERR_FLAG_8814B) & \ + BIT_MASK_MU_DBG_ERR_FLAG_8814B) +#define BIT_SET_MU_DBG_ERR_FLAG_8814B(x, v) \ + (BIT_CLEAR_MU_DBG_ERR_FLAG_8814B(x) | BIT_MU_DBG_ERR_FLAG_8814B(v)) + +/* 2 REG_TX_ERR_RECOVERY_RST_8814B */ + +#define BIT_SHIFT_ERR_RECOVER_CNT_8814B 4 +#define BIT_MASK_ERR_RECOVER_CNT_8814B 0xf +#define BIT_ERR_RECOVER_CNT_8814B(x) \ + (((x) & BIT_MASK_ERR_RECOVER_CNT_8814B) \ + << BIT_SHIFT_ERR_RECOVER_CNT_8814B) +#define BITS_ERR_RECOVER_CNT_8814B \ + (BIT_MASK_ERR_RECOVER_CNT_8814B << BIT_SHIFT_ERR_RECOVER_CNT_8814B) +#define BIT_CLEAR_ERR_RECOVER_CNT_8814B(x) ((x) & (~BITS_ERR_RECOVER_CNT_8814B)) +#define BIT_GET_ERR_RECOVER_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_ERR_RECOVER_CNT_8814B) & \ + BIT_MASK_ERR_RECOVER_CNT_8814B) +#define BIT_SET_ERR_RECOVER_CNT_8814B(x, v) \ + (BIT_CLEAR_ERR_RECOVER_CNT_8814B(x) | BIT_ERR_RECOVER_CNT_8814B(v)) + +#define BIT_RX_HANG_ERR_8814B BIT(2) +#define BIT_TX_HANG_ERR_8814B BIT(1) +#define BIT_TX_ERR_RECOVERY_RST_8814B BIT(0) + +/* 2 REG_SCH_DBG_VALUE_8814B */ + +#define BIT_SHIFT_SCH_DBG_VALUE_8814B 0 +#define BIT_MASK_SCH_DBG_VALUE_8814B 0xffffffffL +#define BIT_SCH_DBG_VALUE_8814B(x) \ + (((x) & BIT_MASK_SCH_DBG_VALUE_8814B) << BIT_SHIFT_SCH_DBG_VALUE_8814B) +#define BITS_SCH_DBG_VALUE_8814B \ + (BIT_MASK_SCH_DBG_VALUE_8814B << BIT_SHIFT_SCH_DBG_VALUE_8814B) +#define BIT_CLEAR_SCH_DBG_VALUE_8814B(x) ((x) & (~BITS_SCH_DBG_VALUE_8814B)) +#define BIT_GET_SCH_DBG_VALUE_8814B(x) \ + (((x) >> BIT_SHIFT_SCH_DBG_VALUE_8814B) & BIT_MASK_SCH_DBG_VALUE_8814B) +#define BIT_SET_SCH_DBG_VALUE_8814B(x, v) \ + (BIT_CLEAR_SCH_DBG_VALUE_8814B(x) | BIT_SCH_DBG_VALUE_8814B(v)) +/* 2 REG_SCH_TXCMD_8814B */ +#define BIT_SHIFT_SCH_TXCMD_8814B 0 +#define BIT_MASK_SCH_TXCMD_8814B 0xffffffffL +#define BIT_SCH_TXCMD_8814B(x) \ + (((x) & BIT_MASK_SCH_TXCMD_8814B) << BIT_SHIFT_SCH_TXCMD_8814B) +#define BITS_SCH_TXCMD_8814B \ + (BIT_MASK_SCH_TXCMD_8814B << BIT_SHIFT_SCH_TXCMD_8814B) +#define BIT_CLEAR_SCH_TXCMD_8814B(x) ((x) & (~BITS_SCH_TXCMD_8814B)) +#define BIT_GET_SCH_TXCMD_8814B(x) \ + (((x) >> BIT_SHIFT_SCH_TXCMD_8814B) & BIT_MASK_SCH_TXCMD_8814B) +#define BIT_SET_SCH_TXCMD_8814B(x, v) \ + (BIT_CLEAR_SCH_TXCMD_8814B(x) | BIT_SCH_TXCMD_8814B(v)) -/* 2 REG_FREERUN_CNT_1_8814B */ +/* 2 REG_PAGE5_DUMMY_8814B */ -#define BIT_SHIFT_FREERUN_CNT_V2_8814B 0 -#define BIT_MASK_FREERUN_CNT_V2_8814B 0xffffffffL -#define BIT_FREERUN_CNT_V2_8814B(x) (((x) & BIT_MASK_FREERUN_CNT_V2_8814B) << BIT_SHIFT_FREERUN_CNT_V2_8814B) -#define BIT_GET_FREERUN_CNT_V2_8814B(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8814B) & BIT_MASK_FREERUN_CNT_V2_8814B) +/* 2 REG_PORT_CTRL_SEL_8814B */ + +#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B 4 +#define BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B 0x7 +#define BIT_BCN_TIMER_SEL_FWRD_V1_8814B(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B) \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B) +#define BITS_BCN_TIMER_SEL_FWRD_V1_8814B \ + (BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1_8814B(x) \ + ((x) & (~BITS_BCN_TIMER_SEL_FWRD_V1_8814B)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B) & \ + BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B) +#define BIT_SET_BCN_TIMER_SEL_FWRD_V1_8814B(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1_8814B(x) | \ + BIT_BCN_TIMER_SEL_FWRD_V1_8814B(v)) + +#define BIT_SHIFT_PORT_CTRL_SEL_8814B 0 +#define BIT_MASK_PORT_CTRL_SEL_8814B 0x7 +#define BIT_PORT_CTRL_SEL_8814B(x) \ + (((x) & BIT_MASK_PORT_CTRL_SEL_8814B) << BIT_SHIFT_PORT_CTRL_SEL_8814B) +#define BITS_PORT_CTRL_SEL_8814B \ + (BIT_MASK_PORT_CTRL_SEL_8814B << BIT_SHIFT_PORT_CTRL_SEL_8814B) +#define BIT_CLEAR_PORT_CTRL_SEL_8814B(x) ((x) & (~BITS_PORT_CTRL_SEL_8814B)) +#define BIT_GET_PORT_CTRL_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PORT_CTRL_SEL_8814B) & BIT_MASK_PORT_CTRL_SEL_8814B) +#define BIT_SET_PORT_CTRL_SEL_8814B(x, v) \ + (BIT_CLEAR_PORT_CTRL_SEL_8814B(x) | BIT_PORT_CTRL_SEL_8814B(v)) + +/* 2 REG_PORT_CTRL_CFG_8814B */ +#define BIT_BCNERR_CNT_EN_V1_8814B BIT(11) +#define BIT_DIS_TRX_CAL_BCN_V1_8814B BIT(10) +#define BIT_DIS_TX_CAL_TBTT_V1_8814B BIT(9) +#define BIT_BCN_AGGRESSION_V1_8814B BIT(8) +#define BIT_TSFTR_RST_V1_8814B BIT(7) +#define BIT_DIS_RX_BSSID_FIT_8814B BIT(6) +#define BIT_EN_TXBCN_RPT_V1_8814B BIT(5) +#define BIT_DIS_TSF_UDT_8814B BIT(4) +#define BIT_EN_PORT_FUNCTION_8814B BIT(3) +#define BIT_EN_RXBCN_RPT_8814B BIT(2) +#define BIT_EN_P2P_CTWINDOW_8814B BIT(1) +#define BIT_EN_P2P_BCNQ_AREA_8814B BIT(0) +/* 2 REG_TBTT_PROHIBIT_CFG_8814B */ +#define BIT_MASK_PROHIBIT_8814B BIT(23) + +#define BIT_SHIFT_TBTT_HOLD_TIME_8814B 8 +#define BIT_MASK_TBTT_HOLD_TIME_8814B 0xfff +#define BIT_TBTT_HOLD_TIME_8814B(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_8814B) \ + << BIT_SHIFT_TBTT_HOLD_TIME_8814B) +#define BITS_TBTT_HOLD_TIME_8814B \ + (BIT_MASK_TBTT_HOLD_TIME_8814B << BIT_SHIFT_TBTT_HOLD_TIME_8814B) +#define BIT_CLEAR_TBTT_HOLD_TIME_8814B(x) ((x) & (~BITS_TBTT_HOLD_TIME_8814B)) +#define BIT_GET_TBTT_HOLD_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_8814B) & \ + BIT_MASK_TBTT_HOLD_TIME_8814B) +#define BIT_SET_TBTT_HOLD_TIME_8814B(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_8814B(x) | BIT_TBTT_HOLD_TIME_8814B(v)) +#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B 0 +#define BIT_MASK_TBTT_PROHIBIT_SETUP_8814B 0xf +#define BIT_TBTT_PROHIBIT_SETUP_8814B(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8814B) \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) +#define BITS_TBTT_PROHIBIT_SETUP_8814B \ + (BIT_MASK_TBTT_PROHIBIT_SETUP_8814B \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8814B(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8814B)) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8814B(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) & \ + BIT_MASK_TBTT_PROHIBIT_SETUP_8814B) +#define BIT_SET_TBTT_PROHIBIT_SETUP_8814B(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8814B(x) | \ + BIT_TBTT_PROHIBIT_SETUP_8814B(v)) + +/* 2 REG_DRVERLYINT_CFG_8814B */ -/* 2 REG_ATIMWND1_V1_8814B */ +#define BIT_SHIFT_DRVERLYITV_8814B 0 +#define BIT_MASK_DRVERLYITV_8814B 0xff +#define BIT_DRVERLYITV_8814B(x) \ + (((x) & BIT_MASK_DRVERLYITV_8814B) << BIT_SHIFT_DRVERLYITV_8814B) +#define BITS_DRVERLYITV_8814B \ + (BIT_MASK_DRVERLYITV_8814B << BIT_SHIFT_DRVERLYITV_8814B) +#define BIT_CLEAR_DRVERLYITV_8814B(x) ((x) & (~BITS_DRVERLYITV_8814B)) +#define BIT_GET_DRVERLYITV_8814B(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV_8814B) & BIT_MASK_DRVERLYITV_8814B) +#define BIT_SET_DRVERLYITV_8814B(x, v) \ + (BIT_CLEAR_DRVERLYITV_8814B(x) | BIT_DRVERLYITV_8814B(v)) + +/* 2 REG_BCNDMATIM_CFG_8814B */ -#define BIT_SHIFT_ATIMWND1_V1_8814B 0 -#define BIT_MASK_ATIMWND1_V1_8814B 0xff -#define BIT_ATIMWND1_V1_8814B(x) (((x) & BIT_MASK_ATIMWND1_V1_8814B) << BIT_SHIFT_ATIMWND1_V1_8814B) -#define BIT_GET_ATIMWND1_V1_8814B(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8814B) & BIT_MASK_ATIMWND1_V1_8814B) +#define BIT_SHIFT_BCNDMATIM_8814B 0 +#define BIT_MASK_BCNDMATIM_8814B 0xff +#define BIT_BCNDMATIM_8814B(x) \ + (((x) & BIT_MASK_BCNDMATIM_8814B) << BIT_SHIFT_BCNDMATIM_8814B) +#define BITS_BCNDMATIM_8814B \ + (BIT_MASK_BCNDMATIM_8814B << BIT_SHIFT_BCNDMATIM_8814B) +#define BIT_CLEAR_BCNDMATIM_8814B(x) ((x) & (~BITS_BCNDMATIM_8814B)) +#define BIT_GET_BCNDMATIM_8814B(x) \ + (((x) >> BIT_SHIFT_BCNDMATIM_8814B) & BIT_MASK_BCNDMATIM_8814B) +#define BIT_SET_BCNDMATIM_8814B(x, v) \ + (BIT_CLEAR_BCNDMATIM_8814B(x) | BIT_BCNDMATIM_8814B(v)) + +/* 2 REG_CTWND_CFG_8814B */ +#define BIT_SHIFT_CTWND_8814B 0 +#define BIT_MASK_CTWND_8814B 0xff +#define BIT_CTWND_8814B(x) \ + (((x) & BIT_MASK_CTWND_8814B) << BIT_SHIFT_CTWND_8814B) +#define BITS_CTWND_8814B (BIT_MASK_CTWND_8814B << BIT_SHIFT_CTWND_8814B) +#define BIT_CLEAR_CTWND_8814B(x) ((x) & (~BITS_CTWND_8814B)) +#define BIT_GET_CTWND_8814B(x) \ + (((x) >> BIT_SHIFT_CTWND_8814B) & BIT_MASK_CTWND_8814B) +#define BIT_SET_CTWND_8814B(x, v) \ + (BIT_CLEAR_CTWND_8814B(x) | BIT_CTWND_8814B(v)) +/* 2 REG_BCNIVLCUNT_CFG_8814B */ -/* 2 REG_TBTT_PROHIBIT_INFRA_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8814B 0 -#define BIT_MASK_TBTT_PROHIBIT_INFRA_8814B 0xff -#define BIT_TBTT_PROHIBIT_INFRA_8814B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8814B) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8814B) -#define BIT_GET_TBTT_PROHIBIT_INFRA_8814B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8814B) & BIT_MASK_TBTT_PROHIBIT_INFRA_8814B) +#define BIT_SHIFT_BCNIVLCUNT_8814B 0 +#define BIT_MASK_BCNIVLCUNT_8814B 0x7f +#define BIT_BCNIVLCUNT_8814B(x) \ + (((x) & BIT_MASK_BCNIVLCUNT_8814B) << BIT_SHIFT_BCNIVLCUNT_8814B) +#define BITS_BCNIVLCUNT_8814B \ + (BIT_MASK_BCNIVLCUNT_8814B << BIT_SHIFT_BCNIVLCUNT_8814B) +#define BIT_CLEAR_BCNIVLCUNT_8814B(x) ((x) & (~BITS_BCNIVLCUNT_8814B)) +#define BIT_GET_BCNIVLCUNT_8814B(x) \ + (((x) >> BIT_SHIFT_BCNIVLCUNT_8814B) & BIT_MASK_BCNIVLCUNT_8814B) +#define BIT_SET_BCNIVLCUNT_8814B(x, v) \ + (BIT_CLEAR_BCNIVLCUNT_8814B(x) | BIT_BCNIVLCUNT_8814B(v)) + +/* 2 REG_EARLY_128US_CFG_8814B */ +#define BIT_SHIFT_EARLY_128US_8814B 0 +#define BIT_MASK_EARLY_128US_8814B 0x7 +#define BIT_EARLY_128US_8814B(x) \ + (((x) & BIT_MASK_EARLY_128US_8814B) << BIT_SHIFT_EARLY_128US_8814B) +#define BITS_EARLY_128US_8814B \ + (BIT_MASK_EARLY_128US_8814B << BIT_SHIFT_EARLY_128US_8814B) +#define BIT_CLEAR_EARLY_128US_8814B(x) ((x) & (~BITS_EARLY_128US_8814B)) +#define BIT_GET_EARLY_128US_8814B(x) \ + (((x) >> BIT_SHIFT_EARLY_128US_8814B) & BIT_MASK_EARLY_128US_8814B) +#define BIT_SET_EARLY_128US_8814B(x, v) \ + (BIT_CLEAR_EARLY_128US_8814B(x) | BIT_EARLY_128US_8814B(v)) + +/* 2 REG_TSFTR_SYNC_OFFSET_CFG_8814B */ + +#define BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B 0 +#define BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B 0xffffff +#define BIT_TSFTR_SNC_OFFSET_V1_8814B(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B) \ + << BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B) +#define BITS_TSFTR_SNC_OFFSET_V1_8814B \ + (BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B \ + << BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_V1_8814B(x) \ + ((x) & (~BITS_TSFTR_SNC_OFFSET_V1_8814B)) +#define BIT_GET_TSFTR_SNC_OFFSET_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B) & \ + BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B) +#define BIT_SET_TSFTR_SNC_OFFSET_V1_8814B(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET_V1_8814B(x) | \ + BIT_TSFTR_SNC_OFFSET_V1_8814B(v)) + +/* 2 REG_TSFTR_SYNC_CTRL_CFG_8814B */ +#define BIT_SYNC_TSF_NOW_V1_8814B BIT(5) +#define BIT_SYNC_TSF_ONCE_8814B BIT(4) +#define BIT_SYNC_TSF_AUTO_8814B BIT(3) + +#define BIT_SHIFT_SYNC_PORT_SEL_8814B 0 +#define BIT_MASK_SYNC_PORT_SEL_8814B 0x7 +#define BIT_SYNC_PORT_SEL_8814B(x) \ + (((x) & BIT_MASK_SYNC_PORT_SEL_8814B) << BIT_SHIFT_SYNC_PORT_SEL_8814B) +#define BITS_SYNC_PORT_SEL_8814B \ + (BIT_MASK_SYNC_PORT_SEL_8814B << BIT_SHIFT_SYNC_PORT_SEL_8814B) +#define BIT_CLEAR_SYNC_PORT_SEL_8814B(x) ((x) & (~BITS_SYNC_PORT_SEL_8814B)) +#define BIT_GET_SYNC_PORT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_SYNC_PORT_SEL_8814B) & BIT_MASK_SYNC_PORT_SEL_8814B) +#define BIT_SET_SYNC_PORT_SEL_8814B(x, v) \ + (BIT_CLEAR_SYNC_PORT_SEL_8814B(x) | BIT_SYNC_PORT_SEL_8814B(v)) + +/* 2 REG_BCN_SPACE_CFG_8814B */ + +#define BIT_SHIFT_BCN_SPACE_8814B 0 +#define BIT_MASK_BCN_SPACE_8814B 0xffff +#define BIT_BCN_SPACE_8814B(x) \ + (((x) & BIT_MASK_BCN_SPACE_8814B) << BIT_SHIFT_BCN_SPACE_8814B) +#define BITS_BCN_SPACE_8814B \ + (BIT_MASK_BCN_SPACE_8814B << BIT_SHIFT_BCN_SPACE_8814B) +#define BIT_CLEAR_BCN_SPACE_8814B(x) ((x) & (~BITS_BCN_SPACE_8814B)) +#define BIT_GET_BCN_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_8814B) & BIT_MASK_BCN_SPACE_8814B) +#define BIT_SET_BCN_SPACE_8814B(x, v) \ + (BIT_CLEAR_BCN_SPACE_8814B(x) | BIT_BCN_SPACE_8814B(v)) + +/* 2 REG_EARLY_INT_ADJUST_CFG_8814B */ + +#define BIT_SHIFT_EARLY_INT_ADJUST_8814B 0 +#define BIT_MASK_EARLY_INT_ADJUST_8814B 0xffff +#define BIT_EARLY_INT_ADJUST_8814B(x) \ + (((x) & BIT_MASK_EARLY_INT_ADJUST_8814B) \ + << BIT_SHIFT_EARLY_INT_ADJUST_8814B) +#define BITS_EARLY_INT_ADJUST_8814B \ + (BIT_MASK_EARLY_INT_ADJUST_8814B << BIT_SHIFT_EARLY_INT_ADJUST_8814B) +#define BIT_CLEAR_EARLY_INT_ADJUST_8814B(x) \ + ((x) & (~BITS_EARLY_INT_ADJUST_8814B)) +#define BIT_GET_EARLY_INT_ADJUST_8814B(x) \ + (((x) >> BIT_SHIFT_EARLY_INT_ADJUST_8814B) & \ + BIT_MASK_EARLY_INT_ADJUST_8814B) +#define BIT_SET_EARLY_INT_ADJUST_8814B(x, v) \ + (BIT_CLEAR_EARLY_INT_ADJUST_8814B(x) | BIT_EARLY_INT_ADJUST_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_CTWND_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CTWND_8814B 0 -#define BIT_MASK_CTWND_8814B 0xff -#define BIT_CTWND_8814B(x) (((x) & BIT_MASK_CTWND_8814B) << BIT_SHIFT_CTWND_8814B) -#define BIT_GET_CTWND_8814B(x) (((x) >> BIT_SHIFT_CTWND_8814B) & BIT_MASK_CTWND_8814B) +/* 2 REG_SW_TBTT_TSF_INFO_8814B */ + +#define BIT_SHIFT_SW_TBTT_TSF_INFO_8814B 0 +#define BIT_MASK_SW_TBTT_TSF_INFO_8814B 0xffffffffL +#define BIT_SW_TBTT_TSF_INFO_8814B(x) \ + (((x) & BIT_MASK_SW_TBTT_TSF_INFO_8814B) \ + << BIT_SHIFT_SW_TBTT_TSF_INFO_8814B) +#define BITS_SW_TBTT_TSF_INFO_8814B \ + (BIT_MASK_SW_TBTT_TSF_INFO_8814B << BIT_SHIFT_SW_TBTT_TSF_INFO_8814B) +#define BIT_CLEAR_SW_TBTT_TSF_INFO_8814B(x) \ + ((x) & (~BITS_SW_TBTT_TSF_INFO_8814B)) +#define BIT_GET_SW_TBTT_TSF_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_SW_TBTT_TSF_INFO_8814B) & \ + BIT_MASK_SW_TBTT_TSF_INFO_8814B) +#define BIT_SET_SW_TBTT_TSF_INFO_8814B(x, v) \ + (BIT_CLEAR_SW_TBTT_TSF_INFO_8814B(x) | BIT_SW_TBTT_TSF_INFO_8814B(v)) + +/* 2 REG_TSFTR_LOW_8814B */ + +#define BIT_SHIFT_TSF_TIMER_LOW_8814B 0 +#define BIT_MASK_TSF_TIMER_LOW_8814B 0xffffffffL +#define BIT_TSF_TIMER_LOW_8814B(x) \ + (((x) & BIT_MASK_TSF_TIMER_LOW_8814B) << BIT_SHIFT_TSF_TIMER_LOW_8814B) +#define BITS_TSF_TIMER_LOW_8814B \ + (BIT_MASK_TSF_TIMER_LOW_8814B << BIT_SHIFT_TSF_TIMER_LOW_8814B) +#define BIT_CLEAR_TSF_TIMER_LOW_8814B(x) ((x) & (~BITS_TSF_TIMER_LOW_8814B)) +#define BIT_GET_TSF_TIMER_LOW_8814B(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_LOW_8814B) & BIT_MASK_TSF_TIMER_LOW_8814B) +#define BIT_SET_TSF_TIMER_LOW_8814B(x, v) \ + (BIT_CLEAR_TSF_TIMER_LOW_8814B(x) | BIT_TSF_TIMER_LOW_8814B(v)) + +/* 2 REG_TSFTR_HIGH_8814B */ + +#define BIT_SHIFT_TSF_TIMER_HIGH_8814B 0 +#define BIT_MASK_TSF_TIMER_HIGH_8814B 0xffffffffL +#define BIT_TSF_TIMER_HIGH_8814B(x) \ + (((x) & BIT_MASK_TSF_TIMER_HIGH_8814B) \ + << BIT_SHIFT_TSF_TIMER_HIGH_8814B) +#define BITS_TSF_TIMER_HIGH_8814B \ + (BIT_MASK_TSF_TIMER_HIGH_8814B << BIT_SHIFT_TSF_TIMER_HIGH_8814B) +#define BIT_CLEAR_TSF_TIMER_HIGH_8814B(x) ((x) & (~BITS_TSF_TIMER_HIGH_8814B)) +#define BIT_GET_TSF_TIMER_HIGH_8814B(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_HIGH_8814B) & \ + BIT_MASK_TSF_TIMER_HIGH_8814B) +#define BIT_SET_TSF_TIMER_HIGH_8814B(x, v) \ + (BIT_CLEAR_TSF_TIMER_HIGH_8814B(x) | BIT_TSF_TIMER_HIGH_8814B(v)) + +/* 2 REG_BCN_ERR_CNT_MAC_8814B */ + +#define BIT_SHIFT_BCN_ERR_CNT_MAC_8814B 0 +#define BIT_MASK_BCN_ERR_CNT_MAC_8814B 0xff +#define BIT_BCN_ERR_CNT_MAC_8814B(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_MAC_8814B) \ + << BIT_SHIFT_BCN_ERR_CNT_MAC_8814B) +#define BITS_BCN_ERR_CNT_MAC_8814B \ + (BIT_MASK_BCN_ERR_CNT_MAC_8814B << BIT_SHIFT_BCN_ERR_CNT_MAC_8814B) +#define BIT_CLEAR_BCN_ERR_CNT_MAC_8814B(x) ((x) & (~BITS_BCN_ERR_CNT_MAC_8814B)) +#define BIT_GET_BCN_ERR_CNT_MAC_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_MAC_8814B) & \ + BIT_MASK_BCN_ERR_CNT_MAC_8814B) +#define BIT_SET_BCN_ERR_CNT_MAC_8814B(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_MAC_8814B(x) | BIT_BCN_ERR_CNT_MAC_8814B(v)) + +/* 2 REG_BCN_ERR_CNT_EDCCA_8814B */ + +#define BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B 0 +#define BIT_MASK_BCN_ERR_CNT_EDCCA_8814B 0xff +#define BIT_BCN_ERR_CNT_EDCCA_8814B(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_EDCCA_8814B) \ + << BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B) +#define BITS_BCN_ERR_CNT_EDCCA_8814B \ + (BIT_MASK_BCN_ERR_CNT_EDCCA_8814B << BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B) +#define BIT_CLEAR_BCN_ERR_CNT_EDCCA_8814B(x) \ + ((x) & (~BITS_BCN_ERR_CNT_EDCCA_8814B)) +#define BIT_GET_BCN_ERR_CNT_EDCCA_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B) & \ + BIT_MASK_BCN_ERR_CNT_EDCCA_8814B) +#define BIT_SET_BCN_ERR_CNT_EDCCA_8814B(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_EDCCA_8814B(x) | BIT_BCN_ERR_CNT_EDCCA_8814B(v)) + +/* 2 REG_BCN_ERR_CNT_CCA_8814B */ + +#define BIT_SHIFT_BCN_ERR_CNT_CCA_8814B 0 +#define BIT_MASK_BCN_ERR_CNT_CCA_8814B 0xff +#define BIT_BCN_ERR_CNT_CCA_8814B(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_CCA_8814B) \ + << BIT_SHIFT_BCN_ERR_CNT_CCA_8814B) +#define BITS_BCN_ERR_CNT_CCA_8814B \ + (BIT_MASK_BCN_ERR_CNT_CCA_8814B << BIT_SHIFT_BCN_ERR_CNT_CCA_8814B) +#define BIT_CLEAR_BCN_ERR_CNT_CCA_8814B(x) ((x) & (~BITS_BCN_ERR_CNT_CCA_8814B)) +#define BIT_GET_BCN_ERR_CNT_CCA_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_CCA_8814B) & \ + BIT_MASK_BCN_ERR_CNT_CCA_8814B) +#define BIT_SET_BCN_ERR_CNT_CCA_8814B(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_CCA_8814B(x) | BIT_BCN_ERR_CNT_CCA_8814B(v)) + +/* 2 REG_BCN_ERR_CNT_INVALID_8814B */ + +#define BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B 0 +#define BIT_MASK_BCN_ERR_CNT_INVALID_8814B 0xff +#define BIT_BCN_ERR_CNT_INVALID_8814B(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_INVALID_8814B) \ + << BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B) +#define BITS_BCN_ERR_CNT_INVALID_8814B \ + (BIT_MASK_BCN_ERR_CNT_INVALID_8814B \ + << BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B) +#define BIT_CLEAR_BCN_ERR_CNT_INVALID_8814B(x) \ + ((x) & (~BITS_BCN_ERR_CNT_INVALID_8814B)) +#define BIT_GET_BCN_ERR_CNT_INVALID_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B) & \ + BIT_MASK_BCN_ERR_CNT_INVALID_8814B) +#define BIT_SET_BCN_ERR_CNT_INVALID_8814B(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_INVALID_8814B(x) | \ + BIT_BCN_ERR_CNT_INVALID_8814B(v)) + +/* 2 REG_BCN_ERR_CNT_OTHERS_8814B */ + +#define BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B 0 +#define BIT_MASK_BCN_ERR_CNT_OTHERS_8814B 0xff +#define BIT_BCN_ERR_CNT_OTHERS_8814B(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_OTHERS_8814B) \ + << BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B) +#define BITS_BCN_ERR_CNT_OTHERS_8814B \ + (BIT_MASK_BCN_ERR_CNT_OTHERS_8814B \ + << BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B) +#define BIT_CLEAR_BCN_ERR_CNT_OTHERS_8814B(x) \ + ((x) & (~BITS_BCN_ERR_CNT_OTHERS_8814B)) +#define BIT_GET_BCN_ERR_CNT_OTHERS_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B) & \ + BIT_MASK_BCN_ERR_CNT_OTHERS_8814B) +#define BIT_SET_BCN_ERR_CNT_OTHERS_8814B(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_OTHERS_8814B(x) | \ + BIT_BCN_ERR_CNT_OTHERS_8814B(v)) + +/* 2 REG_RX_BCN_TIMER_8814B */ + +#define BIT_SHIFT_RX_BCN_TIMER_8814B 0 +#define BIT_MASK_RX_BCN_TIMER_8814B 0xffff +#define BIT_RX_BCN_TIMER_8814B(x) \ + (((x) & BIT_MASK_RX_BCN_TIMER_8814B) << BIT_SHIFT_RX_BCN_TIMER_8814B) +#define BITS_RX_BCN_TIMER_8814B \ + (BIT_MASK_RX_BCN_TIMER_8814B << BIT_SHIFT_RX_BCN_TIMER_8814B) +#define BIT_CLEAR_RX_BCN_TIMER_8814B(x) ((x) & (~BITS_RX_BCN_TIMER_8814B)) +#define BIT_GET_RX_BCN_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TIMER_8814B) & BIT_MASK_RX_BCN_TIMER_8814B) +#define BIT_SET_RX_BCN_TIMER_8814B(x, v) \ + (BIT_CLEAR_RX_BCN_TIMER_8814B(x) | BIT_RX_BCN_TIMER_8814B(v)) + +/* 2 REG_TBTT_CTN_AREA_V1_8814B */ +#define BIT_SHIFT_TBTT_CTN_AREA_8814B 0 +#define BIT_MASK_TBTT_CTN_AREA_8814B 0xff +#define BIT_TBTT_CTN_AREA_8814B(x) \ + (((x) & BIT_MASK_TBTT_CTN_AREA_8814B) << BIT_SHIFT_TBTT_CTN_AREA_8814B) +#define BITS_TBTT_CTN_AREA_8814B \ + (BIT_MASK_TBTT_CTN_AREA_8814B << BIT_SHIFT_TBTT_CTN_AREA_8814B) +#define BIT_CLEAR_TBTT_CTN_AREA_8814B(x) ((x) & (~BITS_TBTT_CTN_AREA_8814B)) +#define BIT_GET_TBTT_CTN_AREA_8814B(x) \ + (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8814B) & BIT_MASK_TBTT_CTN_AREA_8814B) +#define BIT_SET_TBTT_CTN_AREA_8814B(x, v) \ + (BIT_CLEAR_TBTT_CTN_AREA_8814B(x) | BIT_TBTT_CTN_AREA_8814B(v)) + +/* 2 REG_BCN_MAX_ERR_V1_8814B */ +#define BIT_SHIFT_BCN_MAX_ERR_8814B 0 +#define BIT_MASK_BCN_MAX_ERR_8814B 0xff +#define BIT_BCN_MAX_ERR_8814B(x) \ + (((x) & BIT_MASK_BCN_MAX_ERR_8814B) << BIT_SHIFT_BCN_MAX_ERR_8814B) +#define BITS_BCN_MAX_ERR_8814B \ + (BIT_MASK_BCN_MAX_ERR_8814B << BIT_SHIFT_BCN_MAX_ERR_8814B) +#define BIT_CLEAR_BCN_MAX_ERR_8814B(x) ((x) & (~BITS_BCN_MAX_ERR_8814B)) +#define BIT_GET_BCN_MAX_ERR_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_MAX_ERR_8814B) & BIT_MASK_BCN_MAX_ERR_8814B) +#define BIT_SET_BCN_MAX_ERR_8814B(x, v) \ + (BIT_CLEAR_BCN_MAX_ERR_8814B(x) | BIT_BCN_MAX_ERR_8814B(v)) + +/* 2 REG_RXTSF_OFFSET_CCK_V1_8814B */ -/* 2 REG_BCNIVLCUNT_8814B */ +#define BIT_SHIFT_CCK_RXTSF_OFFSET_8814B 0 +#define BIT_MASK_CCK_RXTSF_OFFSET_8814B 0xff +#define BIT_CCK_RXTSF_OFFSET_8814B(x) \ + (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8814B) \ + << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) +#define BITS_CCK_RXTSF_OFFSET_8814B \ + (BIT_MASK_CCK_RXTSF_OFFSET_8814B << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) +#define BIT_CLEAR_CCK_RXTSF_OFFSET_8814B(x) \ + ((x) & (~BITS_CCK_RXTSF_OFFSET_8814B)) +#define BIT_GET_CCK_RXTSF_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) & \ + BIT_MASK_CCK_RXTSF_OFFSET_8814B) +#define BIT_SET_CCK_RXTSF_OFFSET_8814B(x, v) \ + (BIT_CLEAR_CCK_RXTSF_OFFSET_8814B(x) | BIT_CCK_RXTSF_OFFSET_8814B(v)) + +/* 2 REG_RXTSF_OFFSET_OFDM_V1_8814B */ -#define BIT_SHIFT_BCNIVLCUNT_8814B 0 -#define BIT_MASK_BCNIVLCUNT_8814B 0x7f -#define BIT_BCNIVLCUNT_8814B(x) (((x) & BIT_MASK_BCNIVLCUNT_8814B) << BIT_SHIFT_BCNIVLCUNT_8814B) -#define BIT_GET_BCNIVLCUNT_8814B(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8814B) & BIT_MASK_BCNIVLCUNT_8814B) +#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B 0 +#define BIT_MASK_OFDM_RXTSF_OFFSET_8814B 0xff +#define BIT_OFDM_RXTSF_OFFSET_8814B(x) \ + (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8814B) \ + << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) +#define BITS_OFDM_RXTSF_OFFSET_8814B \ + (BIT_MASK_OFDM_RXTSF_OFFSET_8814B << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8814B(x) \ + ((x) & (~BITS_OFDM_RXTSF_OFFSET_8814B)) +#define BIT_GET_OFDM_RXTSF_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) & \ + BIT_MASK_OFDM_RXTSF_OFFSET_8814B) +#define BIT_SET_OFDM_RXTSF_OFFSET_8814B(x, v) \ + (BIT_CLEAR_OFDM_RXTSF_OFFSET_8814B(x) | BIT_OFDM_RXTSF_OFFSET_8814B(v)) + +/* 2 REG_SUB_BCN_SPACE_8814B */ + +#define BIT_SHIFT_SUB_BCN_SPACE_V2_8814B 0 +#define BIT_MASK_SUB_BCN_SPACE_V2_8814B 0xff +#define BIT_SUB_BCN_SPACE_V2_8814B(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE_V2_8814B) \ + << BIT_SHIFT_SUB_BCN_SPACE_V2_8814B) +#define BITS_SUB_BCN_SPACE_V2_8814B \ + (BIT_MASK_SUB_BCN_SPACE_V2_8814B << BIT_SHIFT_SUB_BCN_SPACE_V2_8814B) +#define BIT_CLEAR_SUB_BCN_SPACE_V2_8814B(x) \ + ((x) & (~BITS_SUB_BCN_SPACE_V2_8814B)) +#define BIT_GET_SUB_BCN_SPACE_V2_8814B(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V2_8814B) & \ + BIT_MASK_SUB_BCN_SPACE_V2_8814B) +#define BIT_SET_SUB_BCN_SPACE_V2_8814B(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE_V2_8814B(x) | BIT_SUB_BCN_SPACE_V2_8814B(v)) + +/* 2 REG_MBID_NUM_V1_8814B */ + +#define BIT_SHIFT_BCN_ERR_PORT_SEL_8814B 4 +#define BIT_MASK_BCN_ERR_PORT_SEL_8814B 0xf +#define BIT_BCN_ERR_PORT_SEL_8814B(x) \ + (((x) & BIT_MASK_BCN_ERR_PORT_SEL_8814B) \ + << BIT_SHIFT_BCN_ERR_PORT_SEL_8814B) +#define BITS_BCN_ERR_PORT_SEL_8814B \ + (BIT_MASK_BCN_ERR_PORT_SEL_8814B << BIT_SHIFT_BCN_ERR_PORT_SEL_8814B) +#define BIT_CLEAR_BCN_ERR_PORT_SEL_8814B(x) \ + ((x) & (~BITS_BCN_ERR_PORT_SEL_8814B)) +#define BIT_GET_BCN_ERR_PORT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_PORT_SEL_8814B) & \ + BIT_MASK_BCN_ERR_PORT_SEL_8814B) +#define BIT_SET_BCN_ERR_PORT_SEL_8814B(x, v) \ + (BIT_CLEAR_BCN_ERR_PORT_SEL_8814B(x) | BIT_BCN_ERR_PORT_SEL_8814B(v)) + +#define BIT_SHIFT_MBID_BCN_NUM_V1_8814B 0 +#define BIT_MASK_MBID_BCN_NUM_V1_8814B 0xf +#define BIT_MBID_BCN_NUM_V1_8814B(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_V1_8814B) \ + << BIT_SHIFT_MBID_BCN_NUM_V1_8814B) +#define BITS_MBID_BCN_NUM_V1_8814B \ + (BIT_MASK_MBID_BCN_NUM_V1_8814B << BIT_SHIFT_MBID_BCN_NUM_V1_8814B) +#define BIT_CLEAR_MBID_BCN_NUM_V1_8814B(x) ((x) & (~BITS_MBID_BCN_NUM_V1_8814B)) +#define BIT_GET_MBID_BCN_NUM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_V1_8814B) & \ + BIT_MASK_MBID_BCN_NUM_V1_8814B) +#define BIT_SET_MBID_BCN_NUM_V1_8814B(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_V1_8814B(x) | BIT_MBID_BCN_NUM_V1_8814B(v)) + +/* 2 REG_MBSSID_CTRL_V1_8814B */ +#define BIT_MBID_BCNQ15_EN_8814B BIT(15) +#define BIT_MBID_BCNQ14_EN_8814B BIT(14) +#define BIT_MBID_BCNQ13_EN_8814B BIT(13) +#define BIT_MBID_BCNQ12_EN_8814B BIT(12) +#define BIT_MBID_BCNQ11_EN_8814B BIT(11) +#define BIT_MBID_BCNQ10_EN_8814B BIT(10) +#define BIT_MBID_BCNQ9_EN_8814B BIT(9) +#define BIT_MBID_BCNQ8_EN_8814B BIT(8) +#define BIT_MBID_BCNQ7_EN_8814B BIT(7) +#define BIT_MBID_BCNQ6_EN_8814B BIT(6) +#define BIT_MBID_BCNQ5_EN_8814B BIT(5) +#define BIT_MBID_BCNQ4_EN_8814B BIT(4) +#define BIT_MBID_BCNQ3_EN_8814B BIT(3) +#define BIT_MBID_BCNQ2_EN_8814B BIT(2) +#define BIT_MBID_BCNQ1_EN_8814B BIT(1) +#define BIT_MBID_BCNQ0_EN_8814B BIT(0) +/* 2 REG_USTIME_TSF_V1_8814B */ +#define BIT_SHIFT_USTIME_TSF_V1_8814B 0 +#define BIT_MASK_USTIME_TSF_V1_8814B 0xff +#define BIT_USTIME_TSF_V1_8814B(x) \ + (((x) & BIT_MASK_USTIME_TSF_V1_8814B) << BIT_SHIFT_USTIME_TSF_V1_8814B) +#define BITS_USTIME_TSF_V1_8814B \ + (BIT_MASK_USTIME_TSF_V1_8814B << BIT_SHIFT_USTIME_TSF_V1_8814B) +#define BIT_CLEAR_USTIME_TSF_V1_8814B(x) ((x) & (~BITS_USTIME_TSF_V1_8814B)) +#define BIT_GET_USTIME_TSF_V1_8814B(x) \ + (((x) >> BIT_SHIFT_USTIME_TSF_V1_8814B) & BIT_MASK_USTIME_TSF_V1_8814B) +#define BIT_SET_USTIME_TSF_V1_8814B(x, v) \ + (BIT_CLEAR_USTIME_TSF_V1_8814B(x) | BIT_USTIME_TSF_V1_8814B(v)) + +/* 2 REG_BW_CFG_8814B */ +#define BIT_SLEEP_32K_EN_8814B BIT(3) +#define BIT_DIS_MARK_TSF_US_V1_8814B BIT(2) + +#define BIT_SHIFT_BW_CFG_8814B 0 +#define BIT_MASK_BW_CFG_8814B 0x3 +#define BIT_BW_CFG_8814B(x) \ + (((x) & BIT_MASK_BW_CFG_8814B) << BIT_SHIFT_BW_CFG_8814B) +#define BITS_BW_CFG_8814B (BIT_MASK_BW_CFG_8814B << BIT_SHIFT_BW_CFG_8814B) +#define BIT_CLEAR_BW_CFG_8814B(x) ((x) & (~BITS_BW_CFG_8814B)) +#define BIT_GET_BW_CFG_8814B(x) \ + (((x) >> BIT_SHIFT_BW_CFG_8814B) & BIT_MASK_BW_CFG_8814B) +#define BIT_SET_BW_CFG_8814B(x, v) \ + (BIT_CLEAR_BW_CFG_8814B(x) | BIT_BW_CFG_8814B(v)) + +/* 2 REG_ATIMWND_CFG_8814B */ + +#define BIT_SHIFT_ATIMWND_V1_8814B 0 +#define BIT_MASK_ATIMWND_V1_8814B 0xff +#define BIT_ATIMWND_V1_8814B(x) \ + (((x) & BIT_MASK_ATIMWND_V1_8814B) << BIT_SHIFT_ATIMWND_V1_8814B) +#define BITS_ATIMWND_V1_8814B \ + (BIT_MASK_ATIMWND_V1_8814B << BIT_SHIFT_ATIMWND_V1_8814B) +#define BIT_CLEAR_ATIMWND_V1_8814B(x) ((x) & (~BITS_ATIMWND_V1_8814B)) +#define BIT_GET_ATIMWND_V1_8814B(x) \ + (((x) >> BIT_SHIFT_ATIMWND_V1_8814B) & BIT_MASK_ATIMWND_V1_8814B) +#define BIT_SET_ATIMWND_V1_8814B(x, v) \ + (BIT_CLEAR_ATIMWND_V1_8814B(x) | BIT_ATIMWND_V1_8814B(v)) + +/* 2 REG_DTIM_COUNTER_CFG_8814B */ + +#define BIT_SHIFT_DTIM_COUNT_8814B 0 +#define BIT_MASK_DTIM_COUNT_8814B 0xff +#define BIT_DTIM_COUNT_8814B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_8814B) << BIT_SHIFT_DTIM_COUNT_8814B) +#define BITS_DTIM_COUNT_8814B \ + (BIT_MASK_DTIM_COUNT_8814B << BIT_SHIFT_DTIM_COUNT_8814B) +#define BIT_CLEAR_DTIM_COUNT_8814B(x) ((x) & (~BITS_DTIM_COUNT_8814B)) +#define BIT_GET_DTIM_COUNT_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_8814B) & BIT_MASK_DTIM_COUNT_8814B) +#define BIT_SET_DTIM_COUNT_8814B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_8814B(x) | BIT_DTIM_COUNT_8814B(v)) + +/* 2 REG_ATIM_DTIM_CTRL_SEL_8814B */ +#define BIT_DTIM_BYPASS_V1_8814B BIT(7) + +#define BIT_SHIFT_ATIM_DTIM_SEL_8814B 0 +#define BIT_MASK_ATIM_DTIM_SEL_8814B 0x1f +#define BIT_ATIM_DTIM_SEL_8814B(x) \ + (((x) & BIT_MASK_ATIM_DTIM_SEL_8814B) << BIT_SHIFT_ATIM_DTIM_SEL_8814B) +#define BITS_ATIM_DTIM_SEL_8814B \ + (BIT_MASK_ATIM_DTIM_SEL_8814B << BIT_SHIFT_ATIM_DTIM_SEL_8814B) +#define BIT_CLEAR_ATIM_DTIM_SEL_8814B(x) ((x) & (~BITS_ATIM_DTIM_SEL_8814B)) +#define BIT_GET_ATIM_DTIM_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_ATIM_DTIM_SEL_8814B) & BIT_MASK_ATIM_DTIM_SEL_8814B) +#define BIT_SET_ATIM_DTIM_SEL_8814B(x, v) \ + (BIT_CLEAR_ATIM_DTIM_SEL_8814B(x) | BIT_ATIM_DTIM_SEL_8814B(v)) + +/* 2 REG_ATIMUGT_V1_8814B */ -/* 2 REG_BCNDROPCTRL_8814B */ +#define BIT_SHIFT_ATIM_URGENT_8814B 0 +#define BIT_MASK_ATIM_URGENT_8814B 0xff +#define BIT_ATIM_URGENT_8814B(x) \ + (((x) & BIT_MASK_ATIM_URGENT_8814B) << BIT_SHIFT_ATIM_URGENT_8814B) +#define BITS_ATIM_URGENT_8814B \ + (BIT_MASK_ATIM_URGENT_8814B << BIT_SHIFT_ATIM_URGENT_8814B) +#define BIT_CLEAR_ATIM_URGENT_8814B(x) ((x) & (~BITS_ATIM_URGENT_8814B)) +#define BIT_GET_ATIM_URGENT_8814B(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT_8814B) & BIT_MASK_ATIM_URGENT_8814B) +#define BIT_SET_ATIM_URGENT_8814B(x, v) \ + (BIT_CLEAR_ATIM_URGENT_8814B(x) | BIT_ATIM_URGENT_8814B(v)) + +/* 2 REG_BCNDROPCTRL_V1_8814B */ #define BIT_BEACON_DROP_EN_8814B BIT(7) #define BIT_SHIFT_BEACON_DROP_IVL_8814B 0 #define BIT_MASK_BEACON_DROP_IVL_8814B 0x7f -#define BIT_BEACON_DROP_IVL_8814B(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8814B) << BIT_SHIFT_BEACON_DROP_IVL_8814B) -#define BIT_GET_BEACON_DROP_IVL_8814B(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8814B) & BIT_MASK_BEACON_DROP_IVL_8814B) - +#define BIT_BEACON_DROP_IVL_8814B(x) \ + (((x) & BIT_MASK_BEACON_DROP_IVL_8814B) \ + << BIT_SHIFT_BEACON_DROP_IVL_8814B) +#define BITS_BEACON_DROP_IVL_8814B \ + (BIT_MASK_BEACON_DROP_IVL_8814B << BIT_SHIFT_BEACON_DROP_IVL_8814B) +#define BIT_CLEAR_BEACON_DROP_IVL_8814B(x) ((x) & (~BITS_BEACON_DROP_IVL_8814B)) +#define BIT_GET_BEACON_DROP_IVL_8814B(x) \ + (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8814B) & \ + BIT_MASK_BEACON_DROP_IVL_8814B) +#define BIT_SET_BEACON_DROP_IVL_8814B(x, v) \ + (BIT_CLEAR_BEACON_DROP_IVL_8814B(x) | BIT_BEACON_DROP_IVL_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_HGQ_TIMEOUT_PERIOD_8814B */ - -#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B 0 -#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B 0xff -#define BIT_HGQ_TIMEOUT_PERIOD_8814B(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) -#define BIT_GET_HGQ_TIMEOUT_PERIOD_8814B(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B) +/* 2 REG_DIS_ATIM_V1_8814B */ +#define BIT_DIS_ATIM_P4_8814B BIT(19) +#define BIT_DIS_ATIM_P3_8814B BIT(18) +#define BIT_DIS_ATIM_P2_8814B BIT(17) +#define BIT_DIS_ATIM_P1_8814B BIT(16) +#define BIT_DIS_ATIM_VAP15_8814B BIT(15) +#define BIT_DIS_ATIM_VAP14_8814B BIT(14) +#define BIT_DIS_ATIM_VAP13_8814B BIT(13) +#define BIT_DIS_ATIM_VAP12_8814B BIT(12) +#define BIT_DIS_ATIM_VAP11_8814B BIT(11) +#define BIT_DIS_ATIM_VAP10_8814B BIT(10) +#define BIT_DIS_ATIM_VAP9_8814B BIT(9) +#define BIT_DIS_ATIM_VAP8_8814B BIT(8) +#define BIT_DIS_ATIM_VAP7_8814B BIT(7) +#define BIT_DIS_ATIM_VAP6_8814B BIT(6) +#define BIT_DIS_ATIM_VAP5_8814B BIT(5) +#define BIT_DIS_ATIM_VAP4_8814B BIT(4) +#define BIT_DIS_ATIM_VAP3_8814B BIT(3) +#define BIT_DIS_ATIM_VAP2_8814B BIT(2) +#define BIT_DIS_ATIM_VAP1_8814B BIT(1) +#define BIT_DIS_ATIM_ROOT_P0_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_HIQ_NO_LMT_EN_V1_8814B */ +#define BIT_HIQ_NO_LMT_EN_P4_8814B BIT(19) +#define BIT_HIQ_NO_LMT_EN_P3_8814B BIT(18) +#define BIT_HIQ_NO_LMT_EN_P2_8814B BIT(17) +#define BIT_HIQ_NO_LMT_EN_P1_8814B BIT(16) +#define BIT_HIQ_NO_LMT_EN_VAP15_8814B BIT(15) +#define BIT_HIQ_NO_LMT_EN_VAP14_8814B BIT(14) +#define BIT_HIQ_NO_LMT_EN_VAP13_8814B BIT(13) +#define BIT_HIQ_NO_LMT_EN_VAP12_8814B BIT(12) +#define BIT_HIQ_NO_LMT_EN_VAP11_8814B BIT(11) +#define BIT_HIQ_NO_LMT_EN_VAP10_8814B BIT(10) +#define BIT_HIQ_NO_LMT_EN_VAP9_8814B BIT(9) +#define BIT_HIQ_NO_LMT_EN_VAP8_8814B BIT(8) +#define BIT_HIQ_NO_LMT_EN_VAP7_8814B BIT(7) +#define BIT_HIQ_NO_LMT_EN_VAP6_8814B BIT(6) +#define BIT_HIQ_NO_LMT_EN_VAP5_8814B BIT(5) +#define BIT_HIQ_NO_LMT_EN_VAP4_8814B BIT(4) +#define BIT_HIQ_NO_LMT_EN_VAP3_8814B BIT(3) +#define BIT_HIQ_NO_LMT_EN_VAP2_8814B BIT(2) +#define BIT_HIQ_NO_LMT_EN_VAP1_8814B BIT(1) +#define BIT_HIQ_NO_LMT_EN_ROOT_P0_8814B BIT(0) -/* 2 REG_TXCMD_TIMEOUT_PERIOD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B 0 -#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B 0xff -#define BIT_TXCMD_TIMEOUT_PERIOD_8814B(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) -#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8814B(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B) +/* 2 REG_P2PPS_CTRL_V1_8814B */ +#define BIT_P2P_PWR_RST1_V2_8814B BIT(15) +#define BIT_P2P_PWR_RST0_V2_8814B BIT(14) +#define BIT_EN_TSFBIT32_RST_P2P_V1_8814B BIT(13) + +#define BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B 8 +#define BIT_MASK_NOA_UNIT0_SEL_V1_8814B 0x7 +#define BIT_NOA_UNIT0_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL_V1_8814B) \ + << BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B) +#define BITS_NOA_UNIT0_SEL_V1_8814B \ + (BIT_MASK_NOA_UNIT0_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B) +#define BIT_CLEAR_NOA_UNIT0_SEL_V1_8814B(x) \ + ((x) & (~BITS_NOA_UNIT0_SEL_V1_8814B)) +#define BIT_GET_NOA_UNIT0_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B) & \ + BIT_MASK_NOA_UNIT0_SEL_V1_8814B) +#define BIT_SET_NOA_UNIT0_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL_V1_8814B(x) | BIT_NOA_UNIT0_SEL_V1_8814B(v)) + +#define BIT_P2P_CTW_ALLSTASLEEP_V1_8814B BIT(7) +#define BIT_P2P_OFF_DISTX_EN_V1_8814B BIT(6) +#define BIT_PWR_MGT_EN_V1_8814B BIT(5) +#define BIT_P2P_NOA1_EN_V1_8814B BIT(2) +#define BIT_P2P_NOA0_EN_V1_8814B BIT(1) + +/* 2 REG_P2PPS_SPEC_STATE_V1_8814B */ +#define BIT_SPEC_POWER_STATE_8814B BIT(7) +#define BIT_SPEC_CTWINDOW_ON_8814B BIT(6) +#define BIT_SPEC_BEACON_AREA_ON_8814B BIT(5) +#define BIT_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4) +#define BIT_SPEC_NOA1_OFF_PERIOD_8814B BIT(3) +#define BIT_SPEC_FORCE_DOZE1_8814B BIT(2) +#define BIT_SPEC_NOA0_OFF_PERIOD_8814B BIT(1) +#define BIT_SPEC_FORCE_DOZE0_8814B BIT(0) +/* 2 REG_P2PPS_STATE_V1_8814B */ +#define BIT_POWER_STATE_8814B BIT(7) +#define BIT_CTWINDOW_ON_8814B BIT(6) +#define BIT_BEACON_AREA_ON_8814B BIT(5) +#define BIT_CTWIN_EARLY_DISTX_8814B BIT(4) +#define BIT_NOA1_OFF_PERIOD_8814B BIT(3) +#define BIT_FORCE_DOZE1_8814B BIT(2) +#define BIT_NOA0_OFF_PERIOD_8814B BIT(1) +#define BIT_FORCE_DOZE0_8814B BIT(0) +/* 2 REG_P2PPS1_CTRL_V1_8814B */ +#define BIT_P2P1_PWR_RST1_V2_8814B BIT(15) +#define BIT_P2P1_PWR_RST0_V2_8814B BIT(14) +#define BIT_EN_TSFBIT32_RST_P2P1_V1_8814B BIT(13) + +#define BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B 8 +#define BIT_MASK_NOA_UNIT1_SEL_V1_8814B 0x7 +#define BIT_NOA_UNIT1_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL_V1_8814B) \ + << BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B) +#define BITS_NOA_UNIT1_SEL_V1_8814B \ + (BIT_MASK_NOA_UNIT1_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B) +#define BIT_CLEAR_NOA_UNIT1_SEL_V1_8814B(x) \ + ((x) & (~BITS_NOA_UNIT1_SEL_V1_8814B)) +#define BIT_GET_NOA_UNIT1_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B) & \ + BIT_MASK_NOA_UNIT1_SEL_V1_8814B) +#define BIT_SET_NOA_UNIT1_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL_V1_8814B(x) | BIT_NOA_UNIT1_SEL_V1_8814B(v)) + +#define BIT_P2P1_CTW_ALLSTASLEEP_V1_8814B BIT(7) +#define BIT_P2P1_OFF_DISTX_EN_8814B BIT(6) +#define BIT_P2P1_PWR_MGT_EN_V1_8814B BIT(5) +#define BIT_P2P1_NOA1_EN_V1_8814B BIT(2) +#define BIT_P2P1_NOA0_EN_V1_8814B BIT(1) -/* 2 REG_MISC_CTRL_8814B */ -#define BIT_DIS_TRX_CAL_BCN_8814B BIT(5) -#define BIT_DIS_TX_CAL_TBTT_8814B BIT(4) -#define BIT_EN_FREECNT_8814B BIT(3) -#define BIT_BCN_AGGRESSION_8814B BIT(2) - -#define BIT_SHIFT_DIS_SECONDARY_CCA_8814B 0 -#define BIT_MASK_DIS_SECONDARY_CCA_8814B 0x3 -#define BIT_DIS_SECONDARY_CCA_8814B(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8814B) << BIT_SHIFT_DIS_SECONDARY_CCA_8814B) -#define BIT_GET_DIS_SECONDARY_CCA_8814B(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8814B) & BIT_MASK_DIS_SECONDARY_CCA_8814B) - - - -/* 2 REG_BCN_CTRL_CLINT1_8814B */ -#define BIT_CLI1_DIS_RX_BSSID_FIT_8814B BIT(6) -#define BIT_CLI1_DIS_TSF_UDT_8814B BIT(4) -#define BIT_CLI1_EN_BCN_FUNCTION_8814B BIT(3) -#define BIT_CLI1_EN_RXBCN_RPT_8814B BIT(2) -#define BIT_CLI1_ENP2P_CTWINDOW_8814B BIT(1) -#define BIT_CLI1_ENP2P_BCNQ_AREA_8814B BIT(0) - -/* 2 REG_BCN_CTRL_CLINT2_8814B */ -#define BIT_CLI2_DIS_RX_BSSID_FIT_8814B BIT(6) -#define BIT_CLI2_DIS_TSF_UDT_8814B BIT(4) -#define BIT_CLI2_EN_BCN_FUNCTION_8814B BIT(3) -#define BIT_CLI2_EN_RXBCN_RPT_8814B BIT(2) -#define BIT_CLI2_ENP2P_CTWINDOW_8814B BIT(1) -#define BIT_CLI2_ENP2P_BCNQ_AREA_8814B BIT(0) - -/* 2 REG_BCN_CTRL_CLINT3_8814B */ -#define BIT_CLI3_DIS_RX_BSSID_FIT_8814B BIT(6) -#define BIT_CLI3_DIS_TSF_UDT_8814B BIT(4) -#define BIT_CLI3_EN_BCN_FUNCTION_8814B BIT(3) -#define BIT_CLI3_EN_RXBCN_RPT_8814B BIT(2) -#define BIT_CLI3_ENP2P_CTWINDOW_8814B BIT(1) -#define BIT_CLI3_ENP2P_BCNQ_AREA_8814B BIT(0) - -/* 2 REG_EXTEND_CTRL_8814B */ -#define BIT_EN_TSFBIT32_RST_P2P2_8814B BIT(5) -#define BIT_EN_TSFBIT32_RST_P2P1_8814B BIT(4) - -#define BIT_SHIFT_PORT_SEL_8814B 0 -#define BIT_MASK_PORT_SEL_8814B 0x7 -#define BIT_PORT_SEL_8814B(x) (((x) & BIT_MASK_PORT_SEL_8814B) << BIT_SHIFT_PORT_SEL_8814B) -#define BIT_GET_PORT_SEL_8814B(x) (((x) >> BIT_SHIFT_PORT_SEL_8814B) & BIT_MASK_PORT_SEL_8814B) - - - -/* 2 REG_P2PPS1_SPEC_STATE_8814B */ -#define BIT_P2P1_SPEC_POWER_STATE_8814B BIT(7) +/* 2 REG_P2PPS1_SPEC_STATE_V1_8814B */ +#define BIT_P2P1_SPEC_POWER_STATEP_8814B BIT(7) #define BIT_P2P1_SPEC_CTWINDOW_ON_8814B BIT(6) -#define BIT_P2P1_SPEC_BCN_AREA_ON_8814B BIT(5) +#define BIT_P2P1_SPEC_BEACON_AREA_ON_8814B BIT(5) #define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4) #define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8814B BIT(3) #define BIT_P2P1_SPEC_FORCE_DOZE1_8814B BIT(2) #define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8814B BIT(1) #define BIT_P2P1_SPEC_FORCE_DOZE0_8814B BIT(0) -/* 2 REG_P2PPS1_STATE_8814B */ +/* 2 REG_P2PPS1_STATE_V1_8814B */ #define BIT_P2P1_POWER_STATE_8814B BIT(7) #define BIT_P2P1_CTWINDOW_ON_8814B BIT(6) #define BIT_P2P1_BEACON_AREA_ON_8814B BIT(5) @@ -7789,17 +19138,43 @@ #define BIT_P2P1_NOA0_OFF_PERIOD_8814B BIT(1) #define BIT_P2P1_FORCE_DOZE0_8814B BIT(0) -/* 2 REG_P2PPS2_SPEC_STATE_8814B */ -#define BIT_P2P2_SPEC_POWER_STATE_8814B BIT(7) +/* 2 REG_P2PPS2_CTRL_V1_8814B */ +#define BIT_P2P2_PWR_RST1_V2_8814B BIT(15) +#define BIT_P2P2_PWR_RST0_V2_8814B BIT(14) +#define BIT_EN_TSFBIT32_RST_P2P2_V1_8814B BIT(13) + +#define BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B 8 +#define BIT_MASK_NOA_UNIT2_SEL_V1_8814B 0x7 +#define BIT_NOA_UNIT2_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL_V1_8814B) \ + << BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B) +#define BITS_NOA_UNIT2_SEL_V1_8814B \ + (BIT_MASK_NOA_UNIT2_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B) +#define BIT_CLEAR_NOA_UNIT2_SEL_V1_8814B(x) \ + ((x) & (~BITS_NOA_UNIT2_SEL_V1_8814B)) +#define BIT_GET_NOA_UNIT2_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B) & \ + BIT_MASK_NOA_UNIT2_SEL_V1_8814B) +#define BIT_SET_NOA_UNIT2_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL_V1_8814B(x) | BIT_NOA_UNIT2_SEL_V1_8814B(v)) + +#define BIT_P2P2_CTW_ALLSTASLEEP_V1_8814B BIT(7) +#define BIT_P2P2_OFF_DISTX_EN_V1_8814B BIT(6) +#define BIT_P2P2_PWR_MGT_EN_V1_8814B BIT(5) +#define BIT_P2P2_NOA1_EN_V1_8814B BIT(2) +#define BIT_P2P2_NOA0_EN_V1_8814B BIT(1) + +/* 2 REG_P2PPS2_SPEC_STATE_V1_8814B */ +#define BIT_P2P2_SPEC_POWER_STATEP_8814B BIT(7) #define BIT_P2P2_SPEC_CTWINDOW_ON_8814B BIT(6) -#define BIT_P2P2_SPEC_BCN_AREA_ON_8814B BIT(5) +#define BIT_P2P2_SPEC_BEACON_AREA_ON_8814B BIT(5) #define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4) #define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8814B BIT(3) #define BIT_P2P2_SPEC_FORCE_DOZE1_8814B BIT(2) #define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8814B BIT(1) #define BIT_P2P2_SPEC_FORCE_DOZE0_8814B BIT(0) -/* 2 REG_P2PPS2_STATE_8814B */ +/* 2 REG_P2PPS2_STATE_V1_8814B */ #define BIT_P2P2_POWER_STATE_8814B BIT(7) #define BIT_P2P2_CTWINDOW_ON_8814B BIT(6) #define BIT_P2P2_BEACON_AREA_ON_8814B BIT(5) @@ -7809,428 +19184,1001 @@ #define BIT_P2P2_NOA0_OFF_PERIOD_8814B BIT(1) #define BIT_P2P2_FORCE_DOZE0_8814B BIT(0) -/* 2 REG_PS_TIMER0_8814B */ - -#define BIT_SHIFT_PSTIMER0_INT_8814B 5 -#define BIT_MASK_PSTIMER0_INT_8814B 0x7ffffff -#define BIT_PSTIMER0_INT_8814B(x) (((x) & BIT_MASK_PSTIMER0_INT_8814B) << BIT_SHIFT_PSTIMER0_INT_8814B) -#define BIT_GET_PSTIMER0_INT_8814B(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8814B) & BIT_MASK_PSTIMER0_INT_8814B) - - - -/* 2 REG_PS_TIMER1_8814B */ - -#define BIT_SHIFT_PSTIMER1_INT_8814B 5 -#define BIT_MASK_PSTIMER1_INT_8814B 0x7ffffff -#define BIT_PSTIMER1_INT_8814B(x) (((x) & BIT_MASK_PSTIMER1_INT_8814B) << BIT_SHIFT_PSTIMER1_INT_8814B) -#define BIT_GET_PSTIMER1_INT_8814B(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8814B) & BIT_MASK_PSTIMER1_INT_8814B) - - - -/* 2 REG_PS_TIMER2_8814B */ - -#define BIT_SHIFT_PSTIMER2_INT_8814B 5 -#define BIT_MASK_PSTIMER2_INT_8814B 0x7ffffff -#define BIT_PSTIMER2_INT_8814B(x) (((x) & BIT_MASK_PSTIMER2_INT_8814B) << BIT_SHIFT_PSTIMER2_INT_8814B) -#define BIT_GET_PSTIMER2_INT_8814B(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8814B) & BIT_MASK_PSTIMER2_INT_8814B) - - - -/* 2 REG_TBTT_CTN_AREA_8814B */ - -#define BIT_SHIFT_TBTT_CTN_AREA_8814B 0 -#define BIT_MASK_TBTT_CTN_AREA_8814B 0xff -#define BIT_TBTT_CTN_AREA_8814B(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8814B) << BIT_SHIFT_TBTT_CTN_AREA_8814B) -#define BIT_GET_TBTT_CTN_AREA_8814B(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8814B) & BIT_MASK_TBTT_CTN_AREA_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_FORCE_BCN_IFS_8814B */ - -#define BIT_SHIFT_FORCE_BCN_IFS_8814B 0 -#define BIT_MASK_FORCE_BCN_IFS_8814B 0xff -#define BIT_FORCE_BCN_IFS_8814B(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8814B) << BIT_SHIFT_FORCE_BCN_IFS_8814B) -#define BIT_GET_FORCE_BCN_IFS_8814B(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8814B) & BIT_MASK_FORCE_BCN_IFS_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_TXOP_MIN_8814B */ - -#define BIT_SHIFT_TXOP_MIN_8814B 0 -#define BIT_MASK_TXOP_MIN_8814B 0x3fff -#define BIT_TXOP_MIN_8814B(x) (((x) & BIT_MASK_TXOP_MIN_8814B) << BIT_SHIFT_TXOP_MIN_8814B) -#define BIT_GET_TXOP_MIN_8814B(x) (((x) >> BIT_SHIFT_TXOP_MIN_8814B) & BIT_MASK_TXOP_MIN_8814B) - - - -/* 2 REG_PRE_BKF_TIME_8814B */ - -#define BIT_SHIFT_PRE_BKF_TIME_8814B 0 -#define BIT_MASK_PRE_BKF_TIME_8814B 0xff -#define BIT_PRE_BKF_TIME_8814B(x) (((x) & BIT_MASK_PRE_BKF_TIME_8814B) << BIT_SHIFT_PRE_BKF_TIME_8814B) -#define BIT_GET_PRE_BKF_TIME_8814B(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8814B) & BIT_MASK_PRE_BKF_TIME_8814B) - - - -/* 2 REG_CROSS_TXOP_CTRL_8814B */ -#define BIT_TXFAIL_BREACK_TXOP_EN_8814B BIT(3) -#define BIT_DTIM_BYPASS_8814B BIT(2) -#define BIT_RTS_NAV_TXOP_8814B BIT(1) -#define BIT_NOT_CROSS_TXOP_8814B BIT(0) - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_P2PON_DIS_TXTIME_V1_8814B */ -/* 2 REG_ATIMWND2_8814B */ - -#define BIT_SHIFT_ATIMWND2_8814B 0 -#define BIT_MASK_ATIMWND2_8814B 0xff -#define BIT_ATIMWND2_8814B(x) (((x) & BIT_MASK_ATIMWND2_8814B) << BIT_SHIFT_ATIMWND2_8814B) -#define BIT_GET_ATIMWND2_8814B(x) (((x) >> BIT_SHIFT_ATIMWND2_8814B) & BIT_MASK_ATIMWND2_8814B) - - - -/* 2 REG_ATIMWND3_8814B */ +#define BIT_SHIFT_P2PON_DIS_TXTIME_8814B 0 +#define BIT_MASK_P2PON_DIS_TXTIME_8814B 0xff +#define BIT_P2PON_DIS_TXTIME_8814B(x) \ + (((x) & BIT_MASK_P2PON_DIS_TXTIME_8814B) \ + << BIT_SHIFT_P2PON_DIS_TXTIME_8814B) +#define BITS_P2PON_DIS_TXTIME_8814B \ + (BIT_MASK_P2PON_DIS_TXTIME_8814B << BIT_SHIFT_P2PON_DIS_TXTIME_8814B) +#define BIT_CLEAR_P2PON_DIS_TXTIME_8814B(x) \ + ((x) & (~BITS_P2PON_DIS_TXTIME_8814B)) +#define BIT_GET_P2PON_DIS_TXTIME_8814B(x) \ + (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8814B) & \ + BIT_MASK_P2PON_DIS_TXTIME_8814B) +#define BIT_SET_P2PON_DIS_TXTIME_8814B(x, v) \ + (BIT_CLEAR_P2PON_DIS_TXTIME_8814B(x) | BIT_P2PON_DIS_TXTIME_8814B(v)) + +/* 2 REG_P2POFF_DIS_TXTIME_V1_8814B */ -#define BIT_SHIFT_ATIMWND3_8814B 0 -#define BIT_MASK_ATIMWND3_8814B 0xff -#define BIT_ATIMWND3_8814B(x) (((x) & BIT_MASK_ATIMWND3_8814B) << BIT_SHIFT_ATIMWND3_8814B) -#define BIT_GET_ATIMWND3_8814B(x) (((x) >> BIT_SHIFT_ATIMWND3_8814B) & BIT_MASK_ATIMWND3_8814B) +#define BIT_SHIFT_P2POFF_DIS_TXTIME_8814B 0 +#define BIT_MASK_P2POFF_DIS_TXTIME_8814B 0xff +#define BIT_P2POFF_DIS_TXTIME_8814B(x) \ + (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8814B) \ + << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) +#define BITS_P2POFF_DIS_TXTIME_8814B \ + (BIT_MASK_P2POFF_DIS_TXTIME_8814B << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) +#define BIT_CLEAR_P2POFF_DIS_TXTIME_8814B(x) \ + ((x) & (~BITS_P2POFF_DIS_TXTIME_8814B)) +#define BIT_GET_P2POFF_DIS_TXTIME_8814B(x) \ + (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) & \ + BIT_MASK_P2POFF_DIS_TXTIME_8814B) +#define BIT_SET_P2POFF_DIS_TXTIME_8814B(x, v) \ + (BIT_CLEAR_P2POFF_DIS_TXTIME_8814B(x) | BIT_P2POFF_DIS_TXTIME_8814B(v)) + +/* 2 REG_CHG_POWER_BCN_AREA_8814B */ +#define BIT_CHG_POWER_BCN_AREA_8814B BIT(0) + +/* 2 REG_NOA_SEL_8814B */ + +#define BIT_SHIFT_NOA_SEL_V1_8814B 0 +#define BIT_MASK_NOA_SEL_V1_8814B 0x7 +#define BIT_NOA_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_NOA_SEL_V1_8814B) << BIT_SHIFT_NOA_SEL_V1_8814B) +#define BITS_NOA_SEL_V1_8814B \ + (BIT_MASK_NOA_SEL_V1_8814B << BIT_SHIFT_NOA_SEL_V1_8814B) +#define BIT_CLEAR_NOA_SEL_V1_8814B(x) ((x) & (~BITS_NOA_SEL_V1_8814B)) +#define BIT_GET_NOA_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V1_8814B) & BIT_MASK_NOA_SEL_V1_8814B) +#define BIT_SET_NOA_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_NOA_SEL_V1_8814B(x) | BIT_NOA_SEL_V1_8814B(v)) + +/* 2 REG_NOA_PARAM_V1_8814B */ + +#define BIT_SHIFT_NOA_DURATION_8814B 0 +#define BIT_MASK_NOA_DURATION_8814B 0xffffffffL +#define BIT_NOA_DURATION_8814B(x) \ + (((x) & BIT_MASK_NOA_DURATION_8814B) << BIT_SHIFT_NOA_DURATION_8814B) +#define BITS_NOA_DURATION_8814B \ + (BIT_MASK_NOA_DURATION_8814B << BIT_SHIFT_NOA_DURATION_8814B) +#define BIT_CLEAR_NOA_DURATION_8814B(x) ((x) & (~BITS_NOA_DURATION_8814B)) +#define BIT_GET_NOA_DURATION_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION_8814B) & BIT_MASK_NOA_DURATION_8814B) +#define BIT_SET_NOA_DURATION_8814B(x, v) \ + (BIT_CLEAR_NOA_DURATION_8814B(x) | BIT_NOA_DURATION_8814B(v)) + +/* 2 REG_NOA_PARAM_1_V1_8814B */ + +#define BIT_SHIFT_NOA_INTERVAL_8814B 0 +#define BIT_MASK_NOA_INTERVAL_8814B 0xffffffffL +#define BIT_NOA_INTERVAL_8814B(x) \ + (((x) & BIT_MASK_NOA_INTERVAL_8814B) << BIT_SHIFT_NOA_INTERVAL_8814B) +#define BITS_NOA_INTERVAL_8814B \ + (BIT_MASK_NOA_INTERVAL_8814B << BIT_SHIFT_NOA_INTERVAL_8814B) +#define BIT_CLEAR_NOA_INTERVAL_8814B(x) ((x) & (~BITS_NOA_INTERVAL_8814B)) +#define BIT_GET_NOA_INTERVAL_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_INTERVAL_8814B) & BIT_MASK_NOA_INTERVAL_8814B) +#define BIT_SET_NOA_INTERVAL_8814B(x, v) \ + (BIT_CLEAR_NOA_INTERVAL_8814B(x) | BIT_NOA_INTERVAL_8814B(v)) + +/* 2 REG_NOA_PARAM_2_V1_8814B */ + +#define BIT_SHIFT_NOA_START_TIME_8814B 0 +#define BIT_MASK_NOA_START_TIME_8814B 0xffffffffL +#define BIT_NOA_START_TIME_8814B(x) \ + (((x) & BIT_MASK_NOA_START_TIME_8814B) \ + << BIT_SHIFT_NOA_START_TIME_8814B) +#define BITS_NOA_START_TIME_8814B \ + (BIT_MASK_NOA_START_TIME_8814B << BIT_SHIFT_NOA_START_TIME_8814B) +#define BIT_CLEAR_NOA_START_TIME_8814B(x) ((x) & (~BITS_NOA_START_TIME_8814B)) +#define BIT_GET_NOA_START_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_START_TIME_8814B) & \ + BIT_MASK_NOA_START_TIME_8814B) +#define BIT_SET_NOA_START_TIME_8814B(x, v) \ + (BIT_CLEAR_NOA_START_TIME_8814B(x) | BIT_NOA_START_TIME_8814B(v)) + +/* 2 REG_NOA_PARAM_3_V1_8814B */ + +#define BIT_SHIFT_NOA_COUNT_V2_8814B 0 +#define BIT_MASK_NOA_COUNT_V2_8814B 0xffffffffL +#define BIT_NOA_COUNT_V2_8814B(x) \ + (((x) & BIT_MASK_NOA_COUNT_V2_8814B) << BIT_SHIFT_NOA_COUNT_V2_8814B) +#define BITS_NOA_COUNT_V2_8814B \ + (BIT_MASK_NOA_COUNT_V2_8814B << BIT_SHIFT_NOA_COUNT_V2_8814B) +#define BIT_CLEAR_NOA_COUNT_V2_8814B(x) ((x) & (~BITS_NOA_COUNT_V2_8814B)) +#define BIT_GET_NOA_COUNT_V2_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_V2_8814B) & BIT_MASK_NOA_COUNT_V2_8814B) +#define BIT_SET_NOA_COUNT_V2_8814B(x, v) \ + (BIT_CLEAR_NOA_COUNT_V2_8814B(x) | BIT_NOA_COUNT_V2_8814B(v)) + +/* 2 REG_NOA_ON_ERLY_TIME_V1_8814B */ + +#define BIT_SHIFT__NOA_ON_ERLY_TIME_8814B 0 +#define BIT_MASK__NOA_ON_ERLY_TIME_8814B 0xff +#define BIT__NOA_ON_ERLY_TIME_8814B(x) \ + (((x) & BIT_MASK__NOA_ON_ERLY_TIME_8814B) \ + << BIT_SHIFT__NOA_ON_ERLY_TIME_8814B) +#define BITS__NOA_ON_ERLY_TIME_8814B \ + (BIT_MASK__NOA_ON_ERLY_TIME_8814B << BIT_SHIFT__NOA_ON_ERLY_TIME_8814B) +#define BIT_CLEAR__NOA_ON_ERLY_TIME_8814B(x) \ + ((x) & (~BITS__NOA_ON_ERLY_TIME_8814B)) +#define BIT_GET__NOA_ON_ERLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8814B) & \ + BIT_MASK__NOA_ON_ERLY_TIME_8814B) +#define BIT_SET__NOA_ON_ERLY_TIME_8814B(x, v) \ + (BIT_CLEAR__NOA_ON_ERLY_TIME_8814B(x) | BIT__NOA_ON_ERLY_TIME_8814B(v)) + +/* 2 REG_NOA_OFF_ERLY_TIME_V1_8814B */ + +#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B 0 +#define BIT_MASK__NOA_OFF_ERLY_TIME_8814B 0xff +#define BIT__NOA_OFF_ERLY_TIME_8814B(x) \ + (((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8814B) \ + << BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B) +#define BITS__NOA_OFF_ERLY_TIME_8814B \ + (BIT_MASK__NOA_OFF_ERLY_TIME_8814B \ + << BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B) +#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8814B(x) \ + ((x) & (~BITS__NOA_OFF_ERLY_TIME_8814B)) +#define BIT_GET__NOA_OFF_ERLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B) & \ + BIT_MASK__NOA_OFF_ERLY_TIME_8814B) +#define BIT_SET__NOA_OFF_ERLY_TIME_8814B(x, v) \ + (BIT_CLEAR__NOA_OFF_ERLY_TIME_8814B(x) | \ + BIT__NOA_OFF_ERLY_TIME_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_ATIMWND4_8814B */ +/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL_8814B */ +#define BIT_P2PPS_NOA_STOP_TX_HANG_8814B BIT(31) +#define BIT_P2PPS_MACID_PAUSE_EN_8814B BIT(11) +#define BIT_P2PPS__MGQ_PAUSE_8814B BIT(10) +#define BIT_P2PPS__HIQ_PAUSE_8814B BIT(9) +#define BIT_P2PPS__BCNQ_PAUSE_8814B BIT(8) + +#define BIT_SHIFT_P2PPS_MACID_PAUSE_8814B 0 +#define BIT_MASK_P2PPS_MACID_PAUSE_8814B 0xff +#define BIT_P2PPS_MACID_PAUSE_8814B(x) \ + (((x) & BIT_MASK_P2PPS_MACID_PAUSE_8814B) \ + << BIT_SHIFT_P2PPS_MACID_PAUSE_8814B) +#define BITS_P2PPS_MACID_PAUSE_8814B \ + (BIT_MASK_P2PPS_MACID_PAUSE_8814B << BIT_SHIFT_P2PPS_MACID_PAUSE_8814B) +#define BIT_CLEAR_P2PPS_MACID_PAUSE_8814B(x) \ + ((x) & (~BITS_P2PPS_MACID_PAUSE_8814B)) +#define BIT_GET_P2PPS_MACID_PAUSE_8814B(x) \ + (((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE_8814B) & \ + BIT_MASK_P2PPS_MACID_PAUSE_8814B) +#define BIT_SET_P2PPS_MACID_PAUSE_8814B(x, v) \ + (BIT_CLEAR_P2PPS_MACID_PAUSE_8814B(x) | BIT_P2PPS_MACID_PAUSE_8814B(v)) + +/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8814B */ +#define BIT_P2PPS1_NOA_STOP_TX_HANG_8814B BIT(31) +#define BIT_P2PPS1_MACID_PAUSE_EN_8814B BIT(11) +#define BIT_P2PPS1__MGQ_PAUSE_8814B BIT(10) +#define BIT_P2PPS1__HIQ_PAUSE_8814B BIT(9) +#define BIT_P2PPS1__BCNQ_PAUSE_8814B BIT(8) + +#define BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B 0 +#define BIT_MASK_P2PPS1_MACID_PAUSE_8814B 0xff +#define BIT_P2PPS1_MACID_PAUSE_8814B(x) \ + (((x) & BIT_MASK_P2PPS1_MACID_PAUSE_8814B) \ + << BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B) +#define BITS_P2PPS1_MACID_PAUSE_8814B \ + (BIT_MASK_P2PPS1_MACID_PAUSE_8814B \ + << BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B) +#define BIT_CLEAR_P2PPS1_MACID_PAUSE_8814B(x) \ + ((x) & (~BITS_P2PPS1_MACID_PAUSE_8814B)) +#define BIT_GET_P2PPS1_MACID_PAUSE_8814B(x) \ + (((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B) & \ + BIT_MASK_P2PPS1_MACID_PAUSE_8814B) +#define BIT_SET_P2PPS1_MACID_PAUSE_8814B(x, v) \ + (BIT_CLEAR_P2PPS1_MACID_PAUSE_8814B(x) | \ + BIT_P2PPS1_MACID_PAUSE_8814B(v)) + +/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8814B */ +#define BIT_P2PPS2_NOA_STOP_TX_HANG_8814B BIT(31) +#define BIT_P2PPS2_MACID_PAUSE_EN_8814B BIT(11) +#define BIT_P2PPS2__MGQ_PAUSE_8814B BIT(10) +#define BIT_P2PPS2__HIQ_PAUSE_8814B BIT(9) +#define BIT_P2PPS2__BCNQ_PAUSE_8814B BIT(8) + +#define BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B 0 +#define BIT_MASK_P2PPS2_MACID_PAUSE_8814B 0xff +#define BIT_P2PPS2_MACID_PAUSE_8814B(x) \ + (((x) & BIT_MASK_P2PPS2_MACID_PAUSE_8814B) \ + << BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B) +#define BITS_P2PPS2_MACID_PAUSE_8814B \ + (BIT_MASK_P2PPS2_MACID_PAUSE_8814B \ + << BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B) +#define BIT_CLEAR_P2PPS2_MACID_PAUSE_8814B(x) \ + ((x) & (~BITS_P2PPS2_MACID_PAUSE_8814B)) +#define BIT_GET_P2PPS2_MACID_PAUSE_8814B(x) \ + (((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B) & \ + BIT_MASK_P2PPS2_MACID_PAUSE_8814B) +#define BIT_SET_P2PPS2_MACID_PAUSE_8814B(x, v) \ + (BIT_CLEAR_P2PPS2_MACID_PAUSE_8814B(x) | \ + BIT_P2PPS2_MACID_PAUSE_8814B(v)) + +/* 2 REG_RX_TBTT_SHIFT_8814B */ + +#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B 24 +#define BIT_MASK_RX_TBTT_SHIFT_SEL_8814B 0x7 +#define BIT_RX_TBTT_SHIFT_SEL_8814B(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_8814B) \ + << BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B) +#define BITS_RX_TBTT_SHIFT_SEL_8814B \ + (BIT_MASK_RX_TBTT_SHIFT_SEL_8814B << BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B) +#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_8814B(x) \ + ((x) & (~BITS_RX_TBTT_SHIFT_SEL_8814B)) +#define BIT_GET_RX_TBTT_SHIFT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B) & \ + BIT_MASK_RX_TBTT_SHIFT_SEL_8814B) +#define BIT_SET_RX_TBTT_SHIFT_SEL_8814B(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_SEL_8814B(x) | BIT_RX_TBTT_SHIFT_SEL_8814B(v)) + +#define BIT_RX_TBTT_SHIFT_RW_FLAG_8814B BIT(15) + +#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B 0 +#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B 0xfff +#define BIT_RX_TBTT_SHIFT_OFFSET_8814B(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B) \ + << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B) +#define BITS_RX_TBTT_SHIFT_OFFSET_8814B \ + (BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B \ + << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B) +#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_8814B(x) \ + ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_8814B)) +#define BIT_GET_RX_TBTT_SHIFT_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B) & \ + BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B) +#define BIT_SET_RX_TBTT_SHIFT_OFFSET_8814B(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_8814B(x) | \ + BIT_RX_TBTT_SHIFT_OFFSET_8814B(v)) -#define BIT_SHIFT_ATIMWND4_8814B 0 -#define BIT_MASK_ATIMWND4_8814B 0xff -#define BIT_ATIMWND4_8814B(x) (((x) & BIT_MASK_ATIMWND4_8814B) << BIT_SHIFT_ATIMWND4_8814B) -#define BIT_GET_ATIMWND4_8814B(x) (((x) >> BIT_SHIFT_ATIMWND4_8814B) & BIT_MASK_ATIMWND4_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_FREERUN_CNT_LOW_8814B */ + +#define BIT_SHIFT_FREERUN_CNT_LOW_8814B 0 +#define BIT_MASK_FREERUN_CNT_LOW_8814B 0xffffffffL +#define BIT_FREERUN_CNT_LOW_8814B(x) \ + (((x) & BIT_MASK_FREERUN_CNT_LOW_8814B) \ + << BIT_SHIFT_FREERUN_CNT_LOW_8814B) +#define BITS_FREERUN_CNT_LOW_8814B \ + (BIT_MASK_FREERUN_CNT_LOW_8814B << BIT_SHIFT_FREERUN_CNT_LOW_8814B) +#define BIT_CLEAR_FREERUN_CNT_LOW_8814B(x) ((x) & (~BITS_FREERUN_CNT_LOW_8814B)) +#define BIT_GET_FREERUN_CNT_LOW_8814B(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_LOW_8814B) & \ + BIT_MASK_FREERUN_CNT_LOW_8814B) +#define BIT_SET_FREERUN_CNT_LOW_8814B(x, v) \ + (BIT_CLEAR_FREERUN_CNT_LOW_8814B(x) | BIT_FREERUN_CNT_LOW_8814B(v)) + +/* 2 REG_FREERUN_CNT_HIGH_8814B */ + +#define BIT_SHIFT_FREERUN_CNT_HIGH_8814B 0 +#define BIT_MASK_FREERUN_CNT_HIGH_8814B 0xffffffffL +#define BIT_FREERUN_CNT_HIGH_8814B(x) \ + (((x) & BIT_MASK_FREERUN_CNT_HIGH_8814B) \ + << BIT_SHIFT_FREERUN_CNT_HIGH_8814B) +#define BITS_FREERUN_CNT_HIGH_8814B \ + (BIT_MASK_FREERUN_CNT_HIGH_8814B << BIT_SHIFT_FREERUN_CNT_HIGH_8814B) +#define BIT_CLEAR_FREERUN_CNT_HIGH_8814B(x) \ + ((x) & (~BITS_FREERUN_CNT_HIGH_8814B)) +#define BIT_GET_FREERUN_CNT_HIGH_8814B(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_HIGH_8814B) & \ + BIT_MASK_FREERUN_CNT_HIGH_8814B) +#define BIT_SET_FREERUN_CNT_HIGH_8814B(x, v) \ + (BIT_CLEAR_FREERUN_CNT_HIGH_8814B(x) | BIT_FREERUN_CNT_HIGH_8814B(v)) + +/* 2 REG_CPUMGQ_TX_TIMER_V1_8814B */ +#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B 0xffffffffL +#define BIT_CPUMGQ_TX_TIMER_V1_8814B(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) +#define BITS_CPUMGQ_TX_TIMER_V1_8814B \ + (BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8814B(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8814B)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8814B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) & \ + BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B) +#define BIT_SET_CPUMGQ_TX_TIMER_V1_8814B(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8814B(x) | \ + BIT_CPUMGQ_TX_TIMER_V1_8814B(v)) + +/* 2 REG_PS_TIMER_0_8814B */ + +#define BIT_SHIFT_PS_TIMER_0_8814B 0 +#define BIT_MASK_PS_TIMER_0_8814B 0xffffffffL +#define BIT_PS_TIMER_0_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_0_8814B) << BIT_SHIFT_PS_TIMER_0_8814B) +#define BITS_PS_TIMER_0_8814B \ + (BIT_MASK_PS_TIMER_0_8814B << BIT_SHIFT_PS_TIMER_0_8814B) +#define BIT_CLEAR_PS_TIMER_0_8814B(x) ((x) & (~BITS_PS_TIMER_0_8814B)) +#define BIT_GET_PS_TIMER_0_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_0_8814B) & BIT_MASK_PS_TIMER_0_8814B) +#define BIT_SET_PS_TIMER_0_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_0_8814B(x) | BIT_PS_TIMER_0_8814B(v)) + +/* 2 REG_PS_TIMER_1_8814B */ + +#define BIT_SHIFT_PS_TIMER_1_8814B 0 +#define BIT_MASK_PS_TIMER_1_8814B 0xffffffffL +#define BIT_PS_TIMER_1_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_1_8814B) << BIT_SHIFT_PS_TIMER_1_8814B) +#define BITS_PS_TIMER_1_8814B \ + (BIT_MASK_PS_TIMER_1_8814B << BIT_SHIFT_PS_TIMER_1_8814B) +#define BIT_CLEAR_PS_TIMER_1_8814B(x) ((x) & (~BITS_PS_TIMER_1_8814B)) +#define BIT_GET_PS_TIMER_1_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_1_8814B) & BIT_MASK_PS_TIMER_1_8814B) +#define BIT_SET_PS_TIMER_1_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_1_8814B(x) | BIT_PS_TIMER_1_8814B(v)) + +/* 2 REG_PS_TIMER_2_8814B */ + +#define BIT_SHIFT_PS_TIMER_2_8814B 0 +#define BIT_MASK_PS_TIMER_2_8814B 0xffffffffL +#define BIT_PS_TIMER_2_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_2_8814B) << BIT_SHIFT_PS_TIMER_2_8814B) +#define BITS_PS_TIMER_2_8814B \ + (BIT_MASK_PS_TIMER_2_8814B << BIT_SHIFT_PS_TIMER_2_8814B) +#define BIT_CLEAR_PS_TIMER_2_8814B(x) ((x) & (~BITS_PS_TIMER_2_8814B)) +#define BIT_GET_PS_TIMER_2_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_2_8814B) & BIT_MASK_PS_TIMER_2_8814B) +#define BIT_SET_PS_TIMER_2_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_2_8814B(x) | BIT_PS_TIMER_2_8814B(v)) + +/* 2 REG_PS_TIMER_3_8814B */ + +#define BIT_SHIFT_PS_TIMER_3_8814B 0 +#define BIT_MASK_PS_TIMER_3_8814B 0xffffffffL +#define BIT_PS_TIMER_3_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_3_8814B) << BIT_SHIFT_PS_TIMER_3_8814B) +#define BITS_PS_TIMER_3_8814B \ + (BIT_MASK_PS_TIMER_3_8814B << BIT_SHIFT_PS_TIMER_3_8814B) +#define BIT_CLEAR_PS_TIMER_3_8814B(x) ((x) & (~BITS_PS_TIMER_3_8814B)) +#define BIT_GET_PS_TIMER_3_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_3_8814B) & BIT_MASK_PS_TIMER_3_8814B) +#define BIT_SET_PS_TIMER_3_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_3_8814B(x) | BIT_PS_TIMER_3_8814B(v)) + +/* 2 REG_PS_TIMER_4_8814B */ + +#define BIT_SHIFT_PS_TIMER_4_8814B 0 +#define BIT_MASK_PS_TIMER_4_8814B 0xffffffffL +#define BIT_PS_TIMER_4_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_4_8814B) << BIT_SHIFT_PS_TIMER_4_8814B) +#define BITS_PS_TIMER_4_8814B \ + (BIT_MASK_PS_TIMER_4_8814B << BIT_SHIFT_PS_TIMER_4_8814B) +#define BIT_CLEAR_PS_TIMER_4_8814B(x) ((x) & (~BITS_PS_TIMER_4_8814B)) +#define BIT_GET_PS_TIMER_4_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_4_8814B) & BIT_MASK_PS_TIMER_4_8814B) +#define BIT_SET_PS_TIMER_4_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_4_8814B(x) | BIT_PS_TIMER_4_8814B(v)) + +/* 2 REG_PS_TIMER_5_8814B */ + +#define BIT_SHIFT_PS_TIMER_5_8814B 0 +#define BIT_MASK_PS_TIMER_5_8814B 0xffffffffL +#define BIT_PS_TIMER_5_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_5_8814B) << BIT_SHIFT_PS_TIMER_5_8814B) +#define BITS_PS_TIMER_5_8814B \ + (BIT_MASK_PS_TIMER_5_8814B << BIT_SHIFT_PS_TIMER_5_8814B) +#define BIT_CLEAR_PS_TIMER_5_8814B(x) ((x) & (~BITS_PS_TIMER_5_8814B)) +#define BIT_GET_PS_TIMER_5_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_5_8814B) & BIT_MASK_PS_TIMER_5_8814B) +#define BIT_SET_PS_TIMER_5_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_5_8814B(x) | BIT_PS_TIMER_5_8814B(v)) + +/* 2 REG_PS_TIMER_01_CTRL_8814B */ + +#define BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B 24 +#define BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B 0xff +#define BIT_PS_TIMER_1_EARLY_TIME_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B) \ + << BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B) +#define BITS_PS_TIMER_1_EARLY_TIME_8814B \ + (BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B \ + << BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B) +#define BIT_CLEAR_PS_TIMER_1_EARLY_TIME_8814B(x) \ + ((x) & (~BITS_PS_TIMER_1_EARLY_TIME_8814B)) +#define BIT_GET_PS_TIMER_1_EARLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B) & \ + BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B) +#define BIT_SET_PS_TIMER_1_EARLY_TIME_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_1_EARLY_TIME_8814B(x) | \ + BIT_PS_TIMER_1_EARLY_TIME_8814B(v)) + +#define BIT_PS_TIMER_1_EN_8814B BIT(23) + +#define BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B 16 +#define BIT_MASK_PS_TIMER_1_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_1_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_1_TSF_SEL_8814B) \ + << BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B) +#define BITS_PS_TIMER_1_TSF_SEL_8814B \ + (BIT_MASK_PS_TIMER_1_TSF_SEL_8814B \ + << BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B) +#define BIT_CLEAR_PS_TIMER_1_TSF_SEL_8814B(x) \ + ((x) & (~BITS_PS_TIMER_1_TSF_SEL_8814B)) +#define BIT_GET_PS_TIMER_1_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B) & \ + BIT_MASK_PS_TIMER_1_TSF_SEL_8814B) +#define BIT_SET_PS_TIMER_1_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_1_TSF_SEL_8814B(x) | \ + BIT_PS_TIMER_1_TSF_SEL_8814B(v)) + +#define BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B 8 +#define BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B 0xff +#define BIT_PS_TIMER_0_EARLY_TIME_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B) \ + << BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B) +#define BITS_PS_TIMER_0_EARLY_TIME_8814B \ + (BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B \ + << BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B) +#define BIT_CLEAR_PS_TIMER_0_EARLY_TIME_8814B(x) \ + ((x) & (~BITS_PS_TIMER_0_EARLY_TIME_8814B)) +#define BIT_GET_PS_TIMER_0_EARLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B) & \ + BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B) +#define BIT_SET_PS_TIMER_0_EARLY_TIME_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_0_EARLY_TIME_8814B(x) | \ + BIT_PS_TIMER_0_EARLY_TIME_8814B(v)) + +#define BIT_PS_TIMER_0_EN_8814B BIT(7) + +#define BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B 0 +#define BIT_MASK_PS_TIMER_0_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_0_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_0_TSF_SEL_8814B) \ + << BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B) +#define BITS_PS_TIMER_0_TSF_SEL_8814B \ + (BIT_MASK_PS_TIMER_0_TSF_SEL_8814B \ + << BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B) +#define BIT_CLEAR_PS_TIMER_0_TSF_SEL_8814B(x) \ + ((x) & (~BITS_PS_TIMER_0_TSF_SEL_8814B)) +#define BIT_GET_PS_TIMER_0_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B) & \ + BIT_MASK_PS_TIMER_0_TSF_SEL_8814B) +#define BIT_SET_PS_TIMER_0_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_0_TSF_SEL_8814B(x) | \ + BIT_PS_TIMER_0_TSF_SEL_8814B(v)) + +/* 2 REG_PS_TIMER_23_CTRL_8814B */ + +#define BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B 24 +#define BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B 0xff +#define BIT_PS_TIMER_3_EARLY_TIME_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B) \ + << BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B) +#define BITS_PS_TIMER_3_EARLY_TIME_8814B \ + (BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B \ + << BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B) +#define BIT_CLEAR_PS_TIMER_3_EARLY_TIME_8814B(x) \ + ((x) & (~BITS_PS_TIMER_3_EARLY_TIME_8814B)) +#define BIT_GET_PS_TIMER_3_EARLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B) & \ + BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B) +#define BIT_SET_PS_TIMER_3_EARLY_TIME_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_3_EARLY_TIME_8814B(x) | \ + BIT_PS_TIMER_3_EARLY_TIME_8814B(v)) + +#define BIT_PS_TIMER_3_EN_8814B BIT(23) + +#define BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B 16 +#define BIT_MASK_PS_TIMER_3_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_3_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_3_TSF_SEL_8814B) \ + << BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B) +#define BITS_PS_TIMER_3_TSF_SEL_8814B \ + (BIT_MASK_PS_TIMER_3_TSF_SEL_8814B \ + << BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B) +#define BIT_CLEAR_PS_TIMER_3_TSF_SEL_8814B(x) \ + ((x) & (~BITS_PS_TIMER_3_TSF_SEL_8814B)) +#define BIT_GET_PS_TIMER_3_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B) & \ + BIT_MASK_PS_TIMER_3_TSF_SEL_8814B) +#define BIT_SET_PS_TIMER_3_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_3_TSF_SEL_8814B(x) | \ + BIT_PS_TIMER_3_TSF_SEL_8814B(v)) + +#define BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B 8 +#define BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B 0xff +#define BIT_PS_TIMER_2_EARLY_TIME_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B) \ + << BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B) +#define BITS_PS_TIMER_2_EARLY_TIME_8814B \ + (BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B \ + << BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B) +#define BIT_CLEAR_PS_TIMER_2_EARLY_TIME_8814B(x) \ + ((x) & (~BITS_PS_TIMER_2_EARLY_TIME_8814B)) +#define BIT_GET_PS_TIMER_2_EARLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B) & \ + BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B) +#define BIT_SET_PS_TIMER_2_EARLY_TIME_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_2_EARLY_TIME_8814B(x) | \ + BIT_PS_TIMER_2_EARLY_TIME_8814B(v)) + +#define BIT_PS_TIMER_2_EN_8814B BIT(7) + +#define BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B 0 +#define BIT_MASK_PS_TIMER_2_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_2_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_2_TSF_SEL_8814B) \ + << BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B) +#define BITS_PS_TIMER_2_TSF_SEL_8814B \ + (BIT_MASK_PS_TIMER_2_TSF_SEL_8814B \ + << BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B) +#define BIT_CLEAR_PS_TIMER_2_TSF_SEL_8814B(x) \ + ((x) & (~BITS_PS_TIMER_2_TSF_SEL_8814B)) +#define BIT_GET_PS_TIMER_2_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B) & \ + BIT_MASK_PS_TIMER_2_TSF_SEL_8814B) +#define BIT_SET_PS_TIMER_2_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_2_TSF_SEL_8814B(x) | \ + BIT_PS_TIMER_2_TSF_SEL_8814B(v)) + +/* 2 REG_PS_TIMER_45_CTRL_8814B */ + +#define BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B 24 +#define BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B 0xff +#define BIT_PS_TIMER_5_EARLY_TIME_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B) \ + << BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B) +#define BITS_PS_TIMER_5_EARLY_TIME_8814B \ + (BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B \ + << BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B) +#define BIT_CLEAR_PS_TIMER_5_EARLY_TIME_8814B(x) \ + ((x) & (~BITS_PS_TIMER_5_EARLY_TIME_8814B)) +#define BIT_GET_PS_TIMER_5_EARLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B) & \ + BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B) +#define BIT_SET_PS_TIMER_5_EARLY_TIME_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_5_EARLY_TIME_8814B(x) | \ + BIT_PS_TIMER_5_EARLY_TIME_8814B(v)) + +#define BIT_PS_TIMER_5_EN_8814B BIT(23) + +#define BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B 16 +#define BIT_MASK_PS_TIMER_5_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_5_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_5_TSF_SEL_8814B) \ + << BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B) +#define BITS_PS_TIMER_5_TSF_SEL_8814B \ + (BIT_MASK_PS_TIMER_5_TSF_SEL_8814B \ + << BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B) +#define BIT_CLEAR_PS_TIMER_5_TSF_SEL_8814B(x) \ + ((x) & (~BITS_PS_TIMER_5_TSF_SEL_8814B)) +#define BIT_GET_PS_TIMER_5_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B) & \ + BIT_MASK_PS_TIMER_5_TSF_SEL_8814B) +#define BIT_SET_PS_TIMER_5_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_5_TSF_SEL_8814B(x) | \ + BIT_PS_TIMER_5_TSF_SEL_8814B(v)) + +#define BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B 8 +#define BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B 0xff +#define BIT_PS_TIMER_4_EARLY_TIME_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B) \ + << BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B) +#define BITS_PS_TIMER_4_EARLY_TIME_8814B \ + (BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B \ + << BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B) +#define BIT_CLEAR_PS_TIMER_4_EARLY_TIME_8814B(x) \ + ((x) & (~BITS_PS_TIMER_4_EARLY_TIME_8814B)) +#define BIT_GET_PS_TIMER_4_EARLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B) & \ + BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B) +#define BIT_SET_PS_TIMER_4_EARLY_TIME_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_4_EARLY_TIME_8814B(x) | \ + BIT_PS_TIMER_4_EARLY_TIME_8814B(v)) + +#define BIT_PS_TIMER_4_EN_8814B BIT(7) + +#define BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B 0 +#define BIT_MASK_PS_TIMER_4_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_4_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_4_TSF_SEL_8814B) \ + << BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B) +#define BITS_PS_TIMER_4_TSF_SEL_8814B \ + (BIT_MASK_PS_TIMER_4_TSF_SEL_8814B \ + << BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B) +#define BIT_CLEAR_PS_TIMER_4_TSF_SEL_8814B(x) \ + ((x) & (~BITS_PS_TIMER_4_TSF_SEL_8814B)) +#define BIT_GET_PS_TIMER_4_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B) & \ + BIT_MASK_PS_TIMER_4_TSF_SEL_8814B) +#define BIT_SET_PS_TIMER_4_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_4_TSF_SEL_8814B(x) | \ + BIT_PS_TIMER_4_TSF_SEL_8814B(v)) + +/* 2 REG_CPUMGQ_FREERUN_TIMER_CTRL_8814B */ +#define BIT_FREECNT_RST_V1_8814B BIT(23) +#define BIT_EN_FREECNT_V1_8814B BIT(16) + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B 8 +#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B 0xff +#define BIT_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B) +#define BITS_CPUMGQ_TX_TIMER_EARLY_V1_8814B \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_V1_8814B)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) | \ + BIT_CPUMGQ_TX_TIMER_EARLY_V1_8814B(v)) + +#define BIT_CPUMGQ_TIMER_EN_V1_8814B BIT(7) +#define BIT_CPUMGQ_DROP_BY_HOLDTIME_8814B BIT(5) +#define BIT_CPUMGQ_TX_EN_V1_8814B BIT(4) + +#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B 0 +#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B 0x7 +#define BIT_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B) +#define BITS_CPUMGQ_TIMER_TSF_SEL_V1_8814B \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) \ + ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_V1_8814B)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) | \ + BIT_CPUMGQ_TIMER_TSF_SEL_V1_8814B(v)) + +/* 2 REG_CPUMGQ_PROHIBIT_8814B */ + +#define BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B 8 +#define BIT_MASK_CPUMGQ_HOLD_TIME_8814B 0xfff +#define BIT_CPUMGQ_HOLD_TIME_8814B(x) \ + (((x) & BIT_MASK_CPUMGQ_HOLD_TIME_8814B) \ + << BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B) +#define BITS_CPUMGQ_HOLD_TIME_8814B \ + (BIT_MASK_CPUMGQ_HOLD_TIME_8814B << BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B) +#define BIT_CLEAR_CPUMGQ_HOLD_TIME_8814B(x) \ + ((x) & (~BITS_CPUMGQ_HOLD_TIME_8814B)) +#define BIT_GET_CPUMGQ_HOLD_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B) & \ + BIT_MASK_CPUMGQ_HOLD_TIME_8814B) +#define BIT_SET_CPUMGQ_HOLD_TIME_8814B(x, v) \ + (BIT_CLEAR_CPUMGQ_HOLD_TIME_8814B(x) | BIT_CPUMGQ_HOLD_TIME_8814B(v)) + +#define BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B 0 +#define BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B 0xf +#define BIT_CPUMGQ_PROHIBIT_SETUP_8814B(x) \ + (((x) & BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B) \ + << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B) +#define BITS_CPUMGQ_PROHIBIT_SETUP_8814B \ + (BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B \ + << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B) +#define BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP_8814B(x) \ + ((x) & (~BITS_CPUMGQ_PROHIBIT_SETUP_8814B)) +#define BIT_GET_CPUMGQ_PROHIBIT_SETUP_8814B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B) & \ + BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B) +#define BIT_SET_CPUMGQ_PROHIBIT_SETUP_8814B(x, v) \ + (BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP_8814B(x) | \ + BIT_CPUMGQ_PROHIBIT_SETUP_8814B(v)) -/* 2 REG_ATIMWND5_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_ATIMWND5_8814B 0 -#define BIT_MASK_ATIMWND5_8814B 0xff -#define BIT_ATIMWND5_8814B(x) (((x) & BIT_MASK_ATIMWND5_8814B) << BIT_SHIFT_ATIMWND5_8814B) -#define BIT_GET_ATIMWND5_8814B(x) (((x) >> BIT_SHIFT_ATIMWND5_8814B) & BIT_MASK_ATIMWND5_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_TIMER_COMPARE_8814B */ +#define BIT_COMP_TRIGGER_8814B BIT(7) + +#define BIT_SHIFT_Y_COMP_8814B 4 +#define BIT_MASK_Y_COMP_8814B 0x7 +#define BIT_Y_COMP_8814B(x) \ + (((x) & BIT_MASK_Y_COMP_8814B) << BIT_SHIFT_Y_COMP_8814B) +#define BITS_Y_COMP_8814B (BIT_MASK_Y_COMP_8814B << BIT_SHIFT_Y_COMP_8814B) +#define BIT_CLEAR_Y_COMP_8814B(x) ((x) & (~BITS_Y_COMP_8814B)) +#define BIT_GET_Y_COMP_8814B(x) \ + (((x) >> BIT_SHIFT_Y_COMP_8814B) & BIT_MASK_Y_COMP_8814B) +#define BIT_SET_Y_COMP_8814B(x, v) \ + (BIT_CLEAR_Y_COMP_8814B(x) | BIT_Y_COMP_8814B(v)) + +#define BIT_X_COMP_Y_OVERFLOW_8814B BIT(3) + +#define BIT_SHIFT_X_COMP_8814B 0 +#define BIT_MASK_X_COMP_8814B 0x7 +#define BIT_X_COMP_8814B(x) \ + (((x) & BIT_MASK_X_COMP_8814B) << BIT_SHIFT_X_COMP_8814B) +#define BITS_X_COMP_8814B (BIT_MASK_X_COMP_8814B << BIT_SHIFT_X_COMP_8814B) +#define BIT_CLEAR_X_COMP_8814B(x) ((x) & (~BITS_X_COMP_8814B)) +#define BIT_GET_X_COMP_8814B(x) \ + (((x) >> BIT_SHIFT_X_COMP_8814B) & BIT_MASK_X_COMP_8814B) +#define BIT_SET_X_COMP_8814B(x, v) \ + (BIT_CLEAR_X_COMP_8814B(x) | BIT_X_COMP_8814B(v)) -/* 2 REG_ATIMWND6_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_ATIMWND6_8814B 0 -#define BIT_MASK_ATIMWND6_8814B 0xff -#define BIT_ATIMWND6_8814B(x) (((x) & BIT_MASK_ATIMWND6_8814B) << BIT_SHIFT_ATIMWND6_8814B) -#define BIT_GET_ATIMWND6_8814B(x) (((x) >> BIT_SHIFT_ATIMWND6_8814B) & BIT_MASK_ATIMWND6_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_TIMER_COMPARE_VALUE_LOW_8814B */ + +#define BIT_SHIFT_COMP_VALUE_LOW_8814B 0 +#define BIT_MASK_COMP_VALUE_LOW_8814B 0xffffffffL +#define BIT_COMP_VALUE_LOW_8814B(x) \ + (((x) & BIT_MASK_COMP_VALUE_LOW_8814B) \ + << BIT_SHIFT_COMP_VALUE_LOW_8814B) +#define BITS_COMP_VALUE_LOW_8814B \ + (BIT_MASK_COMP_VALUE_LOW_8814B << BIT_SHIFT_COMP_VALUE_LOW_8814B) +#define BIT_CLEAR_COMP_VALUE_LOW_8814B(x) ((x) & (~BITS_COMP_VALUE_LOW_8814B)) +#define BIT_GET_COMP_VALUE_LOW_8814B(x) \ + (((x) >> BIT_SHIFT_COMP_VALUE_LOW_8814B) & \ + BIT_MASK_COMP_VALUE_LOW_8814B) +#define BIT_SET_COMP_VALUE_LOW_8814B(x, v) \ + (BIT_CLEAR_COMP_VALUE_LOW_8814B(x) | BIT_COMP_VALUE_LOW_8814B(v)) + +/* 2 REG_TIMER_COMPARE_VALUE_HIGH_8814B */ + +#define BIT_SHIFT_COMP_VALUE_HIGH_8814B 0 +#define BIT_MASK_COMP_VALUE_HIGH_8814B 0xffffffffL +#define BIT_COMP_VALUE_HIGH_8814B(x) \ + (((x) & BIT_MASK_COMP_VALUE_HIGH_8814B) \ + << BIT_SHIFT_COMP_VALUE_HIGH_8814B) +#define BITS_COMP_VALUE_HIGH_8814B \ + (BIT_MASK_COMP_VALUE_HIGH_8814B << BIT_SHIFT_COMP_VALUE_HIGH_8814B) +#define BIT_CLEAR_COMP_VALUE_HIGH_8814B(x) ((x) & (~BITS_COMP_VALUE_HIGH_8814B)) +#define BIT_GET_COMP_VALUE_HIGH_8814B(x) \ + (((x) >> BIT_SHIFT_COMP_VALUE_HIGH_8814B) & \ + BIT_MASK_COMP_VALUE_HIGH_8814B) +#define BIT_SET_COMP_VALUE_HIGH_8814B(x, v) \ + (BIT_CLEAR_COMP_VALUE_HIGH_8814B(x) | BIT_COMP_VALUE_HIGH_8814B(v)) -/* 2 REG_ATIMWND7_8814B */ +/* 2 REG_RSVD_8814B */ -#define BIT_SHIFT_ATIMWND7_8814B 0 -#define BIT_MASK_ATIMWND7_8814B 0xff -#define BIT_ATIMWND7_8814B(x) (((x) & BIT_MASK_ATIMWND7_8814B) << BIT_SHIFT_ATIMWND7_8814B) -#define BIT_GET_ATIMWND7_8814B(x) (((x) >> BIT_SHIFT_ATIMWND7_8814B) & BIT_MASK_ATIMWND7_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ -/* 2 REG_ATIMUGT_8814B */ +/* 2 REG_RSVD_8814B */ -#define BIT_SHIFT_ATIM_URGENT_8814B 0 -#define BIT_MASK_ATIM_URGENT_8814B 0xff -#define BIT_ATIM_URGENT_8814B(x) (((x) & BIT_MASK_ATIM_URGENT_8814B) << BIT_SHIFT_ATIM_URGENT_8814B) -#define BIT_GET_ATIM_URGENT_8814B(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8814B) & BIT_MASK_ATIM_URGENT_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ -/* 2 REG_HIQ_NO_LMT_EN_8814B */ -#define BIT_HIQ_NO_LMT_EN_VAP7_8814B BIT(7) -#define BIT_HIQ_NO_LMT_EN_VAP6_8814B BIT(6) -#define BIT_HIQ_NO_LMT_EN_VAP5_8814B BIT(5) -#define BIT_HIQ_NO_LMT_EN_VAP4_8814B BIT(4) -#define BIT_HIQ_NO_LMT_EN_VAP3_8814B BIT(3) -#define BIT_HIQ_NO_LMT_EN_VAP2_8814B BIT(2) -#define BIT_HIQ_NO_LMT_EN_VAP1_8814B BIT(1) -#define BIT_HIQ_NO_LMT_EN_ROOT_8814B BIT(0) +/* 2 REG_RSVD_8814B */ -/* 2 REG_DTIM_COUNTER_ROOT_8814B */ +/* 2 REG_RSVD_8814B */ -#define BIT_SHIFT_DTIM_COUNT_ROOT_8814B 0 -#define BIT_MASK_DTIM_COUNT_ROOT_8814B 0xff -#define BIT_DTIM_COUNT_ROOT_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8814B) << BIT_SHIFT_DTIM_COUNT_ROOT_8814B) -#define BIT_GET_DTIM_COUNT_ROOT_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8814B) & BIT_MASK_DTIM_COUNT_ROOT_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ -/* 2 REG_DTIM_COUNTER_VAP1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP1_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP1_8814B 0xff -#define BIT_DTIM_COUNT_VAP1_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8814B) << BIT_SHIFT_DTIM_COUNT_VAP1_8814B) -#define BIT_GET_DTIM_COUNT_VAP1_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8814B) & BIT_MASK_DTIM_COUNT_VAP1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DTIM_COUNTER_VAP2_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP2_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP2_8814B 0xff -#define BIT_DTIM_COUNT_VAP2_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8814B) << BIT_SHIFT_DTIM_COUNT_VAP2_8814B) -#define BIT_GET_DTIM_COUNT_VAP2_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8814B) & BIT_MASK_DTIM_COUNT_VAP2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DTIM_COUNTER_VAP3_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP3_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP3_8814B 0xff -#define BIT_DTIM_COUNT_VAP3_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8814B) << BIT_SHIFT_DTIM_COUNT_VAP3_8814B) -#define BIT_GET_DTIM_COUNT_VAP3_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8814B) & BIT_MASK_DTIM_COUNT_VAP3_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DTIM_COUNTER_VAP4_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP4_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP4_8814B 0xff -#define BIT_DTIM_COUNT_VAP4_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8814B) << BIT_SHIFT_DTIM_COUNT_VAP4_8814B) -#define BIT_GET_DTIM_COUNT_VAP4_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8814B) & BIT_MASK_DTIM_COUNT_VAP4_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DTIM_COUNTER_VAP5_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP5_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP5_8814B 0xff -#define BIT_DTIM_COUNT_VAP5_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8814B) << BIT_SHIFT_DTIM_COUNT_VAP5_8814B) -#define BIT_GET_DTIM_COUNT_VAP5_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8814B) & BIT_MASK_DTIM_COUNT_VAP5_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DTIM_COUNTER_VAP6_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP6_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP6_8814B 0xff -#define BIT_DTIM_COUNT_VAP6_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8814B) << BIT_SHIFT_DTIM_COUNT_VAP6_8814B) -#define BIT_GET_DTIM_COUNT_VAP6_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8814B) & BIT_MASK_DTIM_COUNT_VAP6_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DTIM_COUNTER_VAP7_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP7_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP7_8814B 0xff -#define BIT_DTIM_COUNT_VAP7_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8814B) << BIT_SHIFT_DTIM_COUNT_VAP7_8814B) -#define BIT_GET_DTIM_COUNT_VAP7_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8814B) & BIT_MASK_DTIM_COUNT_VAP7_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DIS_ATIM_8814B */ -#define BIT_DIS_ATIM_VAP7_8814B BIT(7) -#define BIT_DIS_ATIM_VAP6_8814B BIT(6) -#define BIT_DIS_ATIM_VAP5_8814B BIT(5) -#define BIT_DIS_ATIM_VAP4_8814B BIT(4) -#define BIT_DIS_ATIM_VAP3_8814B BIT(3) -#define BIT_DIS_ATIM_VAP2_8814B BIT(2) -#define BIT_DIS_ATIM_VAP1_8814B BIT(1) -#define BIT_DIS_ATIM_ROOT_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_EARLY_128US_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TSFT_SEL_TIMER1_8814B 3 -#define BIT_MASK_TSFT_SEL_TIMER1_8814B 0x7 -#define BIT_TSFT_SEL_TIMER1_8814B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8814B) << BIT_SHIFT_TSFT_SEL_TIMER1_8814B) -#define BIT_GET_TSFT_SEL_TIMER1_8814B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8814B) & BIT_MASK_TSFT_SEL_TIMER1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_EARLY_128US_8814B 0 -#define BIT_MASK_EARLY_128US_8814B 0x7 -#define BIT_EARLY_128US_8814B(x) (((x) & BIT_MASK_EARLY_128US_8814B) << BIT_SHIFT_EARLY_128US_8814B) -#define BIT_GET_EARLY_128US_8814B(x) (((x) >> BIT_SHIFT_EARLY_128US_8814B) & BIT_MASK_EARLY_128US_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_P2PPS1_CTRL_8814B */ -#define BIT_P2P1_CTW_ALLSTASLEEP_8814B BIT(7) -#define BIT_P2P1_OFF_DISTX_EN_8814B BIT(6) -#define BIT_P2P1_PWR_MGT_EN_8814B BIT(5) -#define BIT_P2P1_NOA1_EN_8814B BIT(2) -#define BIT_P2P1_NOA0_EN_8814B BIT(1) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_P2PPS2_CTRL_8814B */ -#define BIT_P2P2_CTW_ALLSTASLEEP_8814B BIT(7) -#define BIT_P2P2_OFF_DISTX_EN_8814B BIT(6) -#define BIT_P2P2_PWR_MGT_EN_8814B BIT(5) -#define BIT_P2P2_NOA1_EN_8814B BIT(2) -#define BIT_P2P2_NOA0_EN_8814B BIT(1) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TIMER0_SRC_SEL_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SYNC_CLI_SEL_8814B 4 -#define BIT_MASK_SYNC_CLI_SEL_8814B 0x7 -#define BIT_SYNC_CLI_SEL_8814B(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8814B) << BIT_SHIFT_SYNC_CLI_SEL_8814B) -#define BIT_GET_SYNC_CLI_SEL_8814B(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8814B) & BIT_MASK_SYNC_CLI_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TSFT_SEL_TIMER0_8814B 0 -#define BIT_MASK_TSFT_SEL_TIMER0_8814B 0x7 -#define BIT_TSFT_SEL_TIMER0_8814B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8814B) << BIT_SHIFT_TSFT_SEL_TIMER0_8814B) -#define BIT_GET_TSFT_SEL_TIMER0_8814B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8814B) & BIT_MASK_TSFT_SEL_TIMER0_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOA_UNIT_SEL_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_UNIT2_SEL_8814B 8 -#define BIT_MASK_NOA_UNIT2_SEL_8814B 0x7 -#define BIT_NOA_UNIT2_SEL_8814B(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8814B) << BIT_SHIFT_NOA_UNIT2_SEL_8814B) -#define BIT_GET_NOA_UNIT2_SEL_8814B(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8814B) & BIT_MASK_NOA_UNIT2_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_UNIT1_SEL_8814B 4 -#define BIT_MASK_NOA_UNIT1_SEL_8814B 0x7 -#define BIT_NOA_UNIT1_SEL_8814B(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8814B) << BIT_SHIFT_NOA_UNIT1_SEL_8814B) -#define BIT_GET_NOA_UNIT1_SEL_8814B(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8814B) & BIT_MASK_NOA_UNIT1_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_UNIT0_SEL_8814B 0 -#define BIT_MASK_NOA_UNIT0_SEL_8814B 0x7 -#define BIT_NOA_UNIT0_SEL_8814B(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8814B) << BIT_SHIFT_NOA_UNIT0_SEL_8814B) -#define BIT_GET_NOA_UNIT0_SEL_8814B(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8814B) & BIT_MASK_NOA_UNIT0_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_P2POFF_DIS_TXTIME_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_P2POFF_DIS_TXTIME_8814B 0 -#define BIT_MASK_P2POFF_DIS_TXTIME_8814B 0xff -#define BIT_P2POFF_DIS_TXTIME_8814B(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8814B) << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) -#define BIT_GET_P2POFF_DIS_TXTIME_8814B(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) & BIT_MASK_P2POFF_DIS_TXTIME_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_MBSSID_BCN_SPACE2_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_SPACE_CLINT2_8814B 16 -#define BIT_MASK_BCN_SPACE_CLINT2_8814B 0xfff -#define BIT_BCN_SPACE_CLINT2_8814B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8814B) << BIT_SHIFT_BCN_SPACE_CLINT2_8814B) -#define BIT_GET_BCN_SPACE_CLINT2_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8814B) & BIT_MASK_BCN_SPACE_CLINT2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_SPACE_CLINT1_8814B 0 -#define BIT_MASK_BCN_SPACE_CLINT1_8814B 0xfff -#define BIT_BCN_SPACE_CLINT1_8814B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8814B) << BIT_SHIFT_BCN_SPACE_CLINT1_8814B) -#define BIT_GET_BCN_SPACE_CLINT1_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8814B) & BIT_MASK_BCN_SPACE_CLINT1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_MBSSID_BCN_SPACE3_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SUB_BCN_SPACE_8814B 16 -#define BIT_MASK_SUB_BCN_SPACE_8814B 0xff -#define BIT_SUB_BCN_SPACE_8814B(x) (((x) & BIT_MASK_SUB_BCN_SPACE_8814B) << BIT_SHIFT_SUB_BCN_SPACE_8814B) -#define BIT_GET_SUB_BCN_SPACE_8814B(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8814B) & BIT_MASK_SUB_BCN_SPACE_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_SPACE_CLINT3_8814B 0 -#define BIT_MASK_BCN_SPACE_CLINT3_8814B 0xfff -#define BIT_BCN_SPACE_CLINT3_8814B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8814B) << BIT_SHIFT_BCN_SPACE_CLINT3_8814B) -#define BIT_GET_BCN_SPACE_CLINT3_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8814B) & BIT_MASK_BCN_SPACE_CLINT3_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_ACMHWCTRL_8814B */ -#define BIT_BEQ_ACM_STATUS_8814B BIT(7) -#define BIT_VIQ_ACM_STATUS_8814B BIT(6) -#define BIT_VOQ_ACM_STATUS_8814B BIT(5) -#define BIT_BEQ_ACM_EN_8814B BIT(3) -#define BIT_VIQ_ACM_EN_8814B BIT(2) -#define BIT_VOQ_ACM_EN_8814B BIT(1) -#define BIT_ACMHWEN_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_ACMRSTCTRL_8814B */ -#define BIT_BE_ACM_RESET_USED_TIME_8814B BIT(2) -#define BIT_VI_ACM_RESET_USED_TIME_8814B BIT(1) -#define BIT_VO_ACM_RESET_USED_TIME_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_ACMAVG_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_AVGPERIOD_8814B 0 -#define BIT_MASK_AVGPERIOD_8814B 0xffff -#define BIT_AVGPERIOD_8814B(x) (((x) & BIT_MASK_AVGPERIOD_8814B) << BIT_SHIFT_AVGPERIOD_8814B) -#define BIT_GET_AVGPERIOD_8814B(x) (((x) >> BIT_SHIFT_AVGPERIOD_8814B) & BIT_MASK_AVGPERIOD_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_VO_ADMTIME_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_VO_ADMITTED_TIME_8814B 0 -#define BIT_MASK_VO_ADMITTED_TIME_8814B 0xffff -#define BIT_VO_ADMITTED_TIME_8814B(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8814B) << BIT_SHIFT_VO_ADMITTED_TIME_8814B) -#define BIT_GET_VO_ADMITTED_TIME_8814B(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8814B) & BIT_MASK_VO_ADMITTED_TIME_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_VI_ADMTIME_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_VI_ADMITTED_TIME_8814B 0 -#define BIT_MASK_VI_ADMITTED_TIME_8814B 0xffff -#define BIT_VI_ADMITTED_TIME_8814B(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8814B) << BIT_SHIFT_VI_ADMITTED_TIME_8814B) -#define BIT_GET_VI_ADMITTED_TIME_8814B(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8814B) & BIT_MASK_VI_ADMITTED_TIME_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BE_ADMTIME_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BE_ADMITTED_TIME_8814B 0 -#define BIT_MASK_BE_ADMITTED_TIME_8814B 0xffff -#define BIT_BE_ADMITTED_TIME_8814B(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8814B) << BIT_SHIFT_BE_ADMITTED_TIME_8814B) -#define BIT_GET_BE_ADMITTED_TIME_8814B(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8814B) & BIT_MASK_BE_ADMITTED_TIME_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_EDCA_RANDOM_GEN_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_RANDOM_GEN_8814B 0 -#define BIT_MASK_RANDOM_GEN_8814B 0xffffff -#define BIT_RANDOM_GEN_8814B(x) (((x) & BIT_MASK_RANDOM_GEN_8814B) << BIT_SHIFT_RANDOM_GEN_8814B) -#define BIT_GET_RANDOM_GEN_8814B(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8814B) & BIT_MASK_RANDOM_GEN_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TXCMD_NOA_SEL_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_SEL_8814B 4 -#define BIT_MASK_NOA_SEL_8814B 0x7 -#define BIT_NOA_SEL_8814B(x) (((x) & BIT_MASK_NOA_SEL_8814B) << BIT_SHIFT_NOA_SEL_8814B) -#define BIT_GET_NOA_SEL_8814B(x) (((x) >> BIT_SHIFT_NOA_SEL_8814B) & BIT_MASK_NOA_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXCMD_SEG_SEL_8814B 0 -#define BIT_MASK_TXCMD_SEG_SEL_8814B 0xf -#define BIT_TXCMD_SEG_SEL_8814B(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8814B) << BIT_SHIFT_TXCMD_SEG_SEL_8814B) -#define BIT_GET_TXCMD_SEG_SEL_8814B(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8814B) & BIT_MASK_TXCMD_SEG_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ @@ -8240,53 +20188,41 @@ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOA_PARAM_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_DURATION_V1_8814B 0 -#define BIT_MASK_NOA_DURATION_V1_8814B 0xffffffffL -#define BIT_NOA_DURATION_V1_8814B(x) (((x) & BIT_MASK_NOA_DURATION_V1_8814B) << BIT_SHIFT_NOA_DURATION_V1_8814B) -#define BIT_GET_NOA_DURATION_V1_8814B(x) (((x) >> BIT_SHIFT_NOA_DURATION_V1_8814B) & BIT_MASK_NOA_DURATION_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOA_PARAM_1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_INTERVAL_V1_8814B 0 -#define BIT_MASK_NOA_INTERVAL_V1_8814B 0xffffffffL -#define BIT_NOA_INTERVAL_V1_8814B(x) (((x) & BIT_MASK_NOA_INTERVAL_V1_8814B) << BIT_SHIFT_NOA_INTERVAL_V1_8814B) -#define BIT_GET_NOA_INTERVAL_V1_8814B(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8814B) & BIT_MASK_NOA_INTERVAL_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOA_PARAM_2_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_START_TIME_V1_8814B 0 -#define BIT_MASK_NOA_START_TIME_V1_8814B 0xffffffffL -#define BIT_NOA_START_TIME_V1_8814B(x) (((x) & BIT_MASK_NOA_START_TIME_V1_8814B) << BIT_SHIFT_NOA_START_TIME_V1_8814B) -#define BIT_GET_NOA_START_TIME_V1_8814B(x) (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8814B) & BIT_MASK_NOA_START_TIME_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOA_PARAM_3_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_COUNT_V1_8814B 0 -#define BIT_MASK_NOA_COUNT_V1_8814B 0xffffffffL -#define BIT_NOA_COUNT_V1_8814B(x) (((x) & BIT_MASK_NOA_COUNT_V1_8814B) << BIT_SHIFT_NOA_COUNT_V1_8814B) -#define BIT_GET_NOA_COUNT_V1_8814B(x) (((x) >> BIT_SHIFT_NOA_COUNT_V1_8814B) & BIT_MASK_NOA_COUNT_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_P2P_RST_8814B */ -#define BIT_P2P2_PWR_RST1_8814B BIT(5) -#define BIT_P2P2_PWR_RST0_8814B BIT(4) -#define BIT_P2P1_PWR_RST1_8814B BIT(3) -#define BIT_P2P1_PWR_RST0_8814B BIT(2) -#define BIT_P2P_PWR_RST1_V1_8814B BIT(1) -#define BIT_P2P_PWR_RST0_V1_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_SCHEDULER_RST_8814B */ -#define BIT_SYNC_CLI_8814B BIT(1) -#define BIT_SCHEDULER_RST_V1_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ @@ -8294,123 +20230,105 @@ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_SCH_TXCMD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SCH_TXCMD_8814B 0 -#define BIT_MASK_SCH_TXCMD_8814B 0xffffffffL -#define BIT_SCH_TXCMD_8814B(x) (((x) & BIT_MASK_SCH_TXCMD_8814B) << BIT_SHIFT_SCH_TXCMD_8814B) -#define BIT_GET_SCH_TXCMD_8814B(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8814B) & BIT_MASK_SCH_TXCMD_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PAGE5_DUMMY_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_CPUMGQ_TX_TIMER_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B 0 -#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B 0xffffffffL -#define BIT_CPUMGQ_TX_TIMER_V1_8814B(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) -#define BIT_GET_CPUMGQ_TX_TIMER_V1_8814B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_A_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_A_V1_8814B 0 -#define BIT_MASK_PS_TIMER_A_V1_8814B 0xffffffffL -#define BIT_PS_TIMER_A_V1_8814B(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8814B) << BIT_SHIFT_PS_TIMER_A_V1_8814B) -#define BIT_GET_PS_TIMER_A_V1_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8814B) & BIT_MASK_PS_TIMER_A_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_B_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_B_V1_8814B 0 -#define BIT_MASK_PS_TIMER_B_V1_8814B 0xffffffffL -#define BIT_PS_TIMER_B_V1_8814B(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8814B) << BIT_SHIFT_PS_TIMER_B_V1_8814B) -#define BIT_GET_PS_TIMER_B_V1_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8814B) & BIT_MASK_PS_TIMER_B_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_C_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_C_V1_8814B 0 -#define BIT_MASK_PS_TIMER_C_V1_8814B 0xffffffffL -#define BIT_PS_TIMER_C_V1_8814B(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8814B) << BIT_SHIFT_PS_TIMER_C_V1_8814B) -#define BIT_GET_PS_TIMER_C_V1_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8814B) & BIT_MASK_PS_TIMER_C_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8814B */ -#define BIT_CPUMGQ_TIMER_EN_8814B BIT(31) -#define BIT_CPUMGQ_TX_EN_8814B BIT(28) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8814B 24 -#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8814B 0x7 -#define BIT_CPUMGQ_TIMER_TSF_SEL_8814B(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8814B) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8814B) -#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8814B(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8814B) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_PS_TIMER_C_EN_8814B BIT(23) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8814B 16 -#define BIT_MASK_PS_TIMER_C_TSF_SEL_8814B 0x7 -#define BIT_PS_TIMER_C_TSF_SEL_8814B(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8814B) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8814B) -#define BIT_GET_PS_TIMER_C_TSF_SEL_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8814B) & BIT_MASK_PS_TIMER_C_TSF_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_PS_TIMER_B_EN_8814B BIT(15) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8814B 8 -#define BIT_MASK_PS_TIMER_B_TSF_SEL_8814B 0x7 -#define BIT_PS_TIMER_B_TSF_SEL_8814B(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8814B) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8814B) -#define BIT_GET_PS_TIMER_B_TSF_SEL_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8814B) & BIT_MASK_PS_TIMER_B_TSF_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_PS_TIMER_A_EN_8814B BIT(7) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8814B 0 -#define BIT_MASK_PS_TIMER_A_TSF_SEL_8814B 0x7 -#define BIT_PS_TIMER_A_TSF_SEL_8814B(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8814B) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8814B) -#define BIT_GET_PS_TIMER_A_TSF_SEL_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8814B) & BIT_MASK_PS_TIMER_A_TSF_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8814B 0 -#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8814B 0xff -#define BIT_CPUMGQ_TX_TIMER_EARLY_8814B(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8814B) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8814B) -#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8814B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8814B) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_A_EARLY_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_A_EARLY_8814B 0 -#define BIT_MASK_PS_TIMER_A_EARLY_8814B 0xff -#define BIT_PS_TIMER_A_EARLY_8814B(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8814B) << BIT_SHIFT_PS_TIMER_A_EARLY_8814B) -#define BIT_GET_PS_TIMER_A_EARLY_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8814B) & BIT_MASK_PS_TIMER_A_EARLY_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_B_EARLY_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_B_EARLY_8814B 0 -#define BIT_MASK_PS_TIMER_B_EARLY_8814B 0xff -#define BIT_PS_TIMER_B_EARLY_8814B(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8814B) << BIT_SHIFT_PS_TIMER_B_EARLY_8814B) -#define BIT_GET_PS_TIMER_B_EARLY_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8814B) & BIT_MASK_PS_TIMER_B_EARLY_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_C_EARLY_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_C_EARLY_8814B 0 -#define BIT_MASK_PS_TIMER_C_EARLY_8814B 0xff -#define BIT_PS_TIMER_C_EARLY_8814B(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8814B) << BIT_SHIFT_PS_TIMER_C_EARLY_8814B) -#define BIT_GET_PS_TIMER_C_EARLY_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8814B) & BIT_MASK_PS_TIMER_C_EARLY_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ @@ -8438,120 +20356,128 @@ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BWOPMODE_8814B (BW OPERATION MODE REGISTER) */ +/* 2 REG_WMAC_CR_8814B (WMAC CR AND APSD CONTROL REGISTER) */ +#define BIT_IC_MACPHY_M_8814B BIT(0) /* 2 REG_WMAC_FWPKT_CR_8814B */ #define BIT_FWEN_8814B BIT(7) #define BIT_PHYSTS_PKT_CTRL_8814B BIT(6) +#define BIT_FWFULL_TO_RXFF_EN_8814B BIT(5) #define BIT_APPHDR_MIDSRCH_FAIL_8814B BIT(4) #define BIT_FWPARSING_EN_8814B BIT(3) #define BIT_SHIFT_APPEND_MHDR_LEN_8814B 0 #define BIT_MASK_APPEND_MHDR_LEN_8814B 0x7 -#define BIT_APPEND_MHDR_LEN_8814B(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8814B) << BIT_SHIFT_APPEND_MHDR_LEN_8814B) -#define BIT_GET_APPEND_MHDR_LEN_8814B(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8814B) & BIT_MASK_APPEND_MHDR_LEN_8814B) - - +#define BIT_APPEND_MHDR_LEN_8814B(x) \ + (((x) & BIT_MASK_APPEND_MHDR_LEN_8814B) \ + << BIT_SHIFT_APPEND_MHDR_LEN_8814B) +#define BITS_APPEND_MHDR_LEN_8814B \ + (BIT_MASK_APPEND_MHDR_LEN_8814B << BIT_SHIFT_APPEND_MHDR_LEN_8814B) +#define BIT_CLEAR_APPEND_MHDR_LEN_8814B(x) ((x) & (~BITS_APPEND_MHDR_LEN_8814B)) +#define BIT_GET_APPEND_MHDR_LEN_8814B(x) \ + (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8814B) & \ + BIT_MASK_APPEND_MHDR_LEN_8814B) +#define BIT_SET_APPEND_MHDR_LEN_8814B(x, v) \ + (BIT_CLEAR_APPEND_MHDR_LEN_8814B(x) | BIT_APPEND_MHDR_LEN_8814B(v)) /* 2 REG_FW_STS_FILTER_8814B */ #define BIT_DATA_FW_STS_FILTER_8814B BIT(2) #define BIT_CTRL_FW_STS_FILTER_8814B BIT(1) #define BIT_MGNT_FW_STS_FILTER_8814B BIT(0) -/* 2 REG_WMAC_CR_8814B (WMAC CR AND APSD CONTROL REGISTER) */ -#define BIT_IC_MACPHY_M_8814B BIT(0) +/* 2 REG_RSVD_8814B */ /* 2 REG_TCR_8814B (TRANSMISSION CONFIGURATION REGISTER) */ #define BIT_WMAC_EN_RTS_ADDR_8814B BIT(31) @@ -8560,9 +20486,10 @@ #define BIT_WMAC_NOTX_IN_RXNDP_8814B BIT(28) #define BIT_WMAC_EN_EOF_8814B BIT(27) #define BIT_WMAC_BF_SEL_8814B BIT(26) -#define BIT_WMAC_ANTMODE_SEL_8814B BIT(25) -#define BIT_WMAC_TCRPWRMGT_HWCTL_8814B BIT(24) +#define BIT_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(24) #define BIT_WMAC_SMOOTH_VAL_8814B BIT(23) +#define BIT_WMAC_EN_SCRAM_INC_8814B BIT(22) +#define BIT_UNDERFLOWEN_CMPLEN_SEL_8814B BIT(21) #define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8814B BIT(20) #define BIT_WMAC_TCR_EN_20MST_8814B BIT(19) #define BIT_WMAC_DIS_SIGTA_8814B BIT(18) @@ -8574,15 +20501,15 @@ #define BIT_WMAC_TCR_ERRSTEN_0_8814B BIT(12) #define BIT_WMAC_TCR_TXSK_PERPKT_8814B BIT(11) #define BIT_ICV_8814B BIT(10) -#define BIT_CFEND_FORMAT_8814B BIT(9) #define BIT_CRC_8814B BIT(8) -#define BIT_PWRBIT_OW_EN_8814B BIT(7) +#define BIT_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(7) #define BIT_PWR_ST_8814B BIT(6) #define BIT_WMAC_TCR_UPD_TIMIE_8814B BIT(5) #define BIT_WMAC_TCR_UPD_HGQMD_8814B BIT(4) #define BIT_VHTSIGA1_TXPS_8814B BIT(3) #define BIT_PAD_SEL_8814B BIT(2) #define BIT_DIS_GCLK_8814B BIT(1) +#define BIT_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(0) /* 2 REG_RCR_8814B (RECEIVE CONFIGURATION REGISTER) */ #define BIT_APP_FCS_8814B BIT(31) @@ -8592,16 +20519,18 @@ #define BIT_APP_BASSN_8814B BIT(27) #define BIT_VHT_DACK_8814B BIT(26) #define BIT_TCPOFLD_EN_8814B BIT(25) -#define BIT_ENMBID_8814B BIT(24) +#define BIT_ENADDRCAM_8814B BIT(24) #define BIT_LSIGEN_8814B BIT(23) #define BIT_MFBEN_8814B BIT(22) #define BIT_DISCHKPPDLLEN_8814B BIT(21) #define BIT_PKTCTL_DLEN_8814B BIT(20) +#define BIT_DISGCLK_8814B BIT(19) #define BIT_TIM_PARSER_EN_8814B BIT(18) #define BIT_BC_MD_EN_8814B BIT(17) #define BIT_UC_MD_EN_8814B BIT(16) #define BIT_RXSK_PERPKT_8814B BIT(15) #define BIT_HTC_LOC_CTRL_8814B BIT(14) +#define BIT_ACK_WITH_CBSSID_DATA_OPTION_8814B BIT(13) #define BIT_RPFM_CAM_ENABLE_8814B BIT(12) #define BIT_TA_BCN_8814B BIT(11) #define BIT_DISDECMYPKT_8814B BIT(10) @@ -8616,239 +20545,409 @@ #define BIT_APM_8814B BIT(1) #define BIT_AAP_8814B BIT(0) -/* 2 REG_RX_DRVINFO_SZ_8814B (RX DRIVER INFO SIZE REGISTER) */ -#define BIT_PHYSTS_PER_PKT_MODE_8814B BIT(7) - -#define BIT_SHIFT_DRVINFO_SZ_V1_8814B 0 -#define BIT_MASK_DRVINFO_SZ_V1_8814B 0xf -#define BIT_DRVINFO_SZ_V1_8814B(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8814B) << BIT_SHIFT_DRVINFO_SZ_V1_8814B) -#define BIT_GET_DRVINFO_SZ_V1_8814B(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8814B) & BIT_MASK_DRVINFO_SZ_V1_8814B) - - - -/* 2 REG_RX_DLK_TIME_8814B (RX DEADLOCK TIME REGISTER) */ - -#define BIT_SHIFT_RX_DLK_TIME_8814B 0 -#define BIT_MASK_RX_DLK_TIME_8814B 0xff -#define BIT_RX_DLK_TIME_8814B(x) (((x) & BIT_MASK_RX_DLK_TIME_8814B) << BIT_SHIFT_RX_DLK_TIME_8814B) -#define BIT_GET_RX_DLK_TIME_8814B(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8814B) & BIT_MASK_RX_DLK_TIME_8814B) - - - /* 2 REG_RX_PKT_LIMIT_8814B (RX PACKET LENGTH LIMIT REGISTER) */ #define BIT_SHIFT_RXPKTLMT_8814B 0 #define BIT_MASK_RXPKTLMT_8814B 0x3f -#define BIT_RXPKTLMT_8814B(x) (((x) & BIT_MASK_RXPKTLMT_8814B) << BIT_SHIFT_RXPKTLMT_8814B) -#define BIT_GET_RXPKTLMT_8814B(x) (((x) >> BIT_SHIFT_RXPKTLMT_8814B) & BIT_MASK_RXPKTLMT_8814B) - +#define BIT_RXPKTLMT_8814B(x) \ + (((x) & BIT_MASK_RXPKTLMT_8814B) << BIT_SHIFT_RXPKTLMT_8814B) +#define BITS_RXPKTLMT_8814B \ + (BIT_MASK_RXPKTLMT_8814B << BIT_SHIFT_RXPKTLMT_8814B) +#define BIT_CLEAR_RXPKTLMT_8814B(x) ((x) & (~BITS_RXPKTLMT_8814B)) +#define BIT_GET_RXPKTLMT_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKTLMT_8814B) & BIT_MASK_RXPKTLMT_8814B) +#define BIT_SET_RXPKTLMT_8814B(x, v) \ + (BIT_CLEAR_RXPKTLMT_8814B(x) | BIT_RXPKTLMT_8814B(v)) +/* 2 REG_RX_DLK_TIME_8814B (RX DEADLOCK TIME REGISTER) */ -/* 2 REG_MACID_8814B (MAC ID REGISTER) */ +#define BIT_SHIFT_RX_DLK_TIME_8814B 0 +#define BIT_MASK_RX_DLK_TIME_8814B 0xff +#define BIT_RX_DLK_TIME_8814B(x) \ + (((x) & BIT_MASK_RX_DLK_TIME_8814B) << BIT_SHIFT_RX_DLK_TIME_8814B) +#define BITS_RX_DLK_TIME_8814B \ + (BIT_MASK_RX_DLK_TIME_8814B << BIT_SHIFT_RX_DLK_TIME_8814B) +#define BIT_CLEAR_RX_DLK_TIME_8814B(x) ((x) & (~BITS_RX_DLK_TIME_8814B)) +#define BIT_GET_RX_DLK_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_RX_DLK_TIME_8814B) & BIT_MASK_RX_DLK_TIME_8814B) +#define BIT_SET_RX_DLK_TIME_8814B(x, v) \ + (BIT_CLEAR_RX_DLK_TIME_8814B(x) | BIT_RX_DLK_TIME_8814B(v)) -#define BIT_SHIFT_MACID_8814B 0 -#define BIT_MASK_MACID_8814B 0xffffffffffffL -#define BIT_MACID_8814B(x) (((x) & BIT_MASK_MACID_8814B) << BIT_SHIFT_MACID_8814B) -#define BIT_GET_MACID_8814B(x) (((x) >> BIT_SHIFT_MACID_8814B) & BIT_MASK_MACID_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RX_DRVINFO_SZ_8814B (RX DRIVER INFO SIZE REGISTER) */ +#define BIT_PHYSTS_PER_PKT_MODE_8814B BIT(7) +#define BIT_SHIFT_DRVINFO_SZ_V1_8814B 0 +#define BIT_MASK_DRVINFO_SZ_V1_8814B 0xf +#define BIT_DRVINFO_SZ_V1_8814B(x) \ + (((x) & BIT_MASK_DRVINFO_SZ_V1_8814B) << BIT_SHIFT_DRVINFO_SZ_V1_8814B) +#define BITS_DRVINFO_SZ_V1_8814B \ + (BIT_MASK_DRVINFO_SZ_V1_8814B << BIT_SHIFT_DRVINFO_SZ_V1_8814B) +#define BIT_CLEAR_DRVINFO_SZ_V1_8814B(x) ((x) & (~BITS_DRVINFO_SZ_V1_8814B)) +#define BIT_GET_DRVINFO_SZ_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8814B) & BIT_MASK_DRVINFO_SZ_V1_8814B) +#define BIT_SET_DRVINFO_SZ_V1_8814B(x, v) \ + (BIT_CLEAR_DRVINFO_SZ_V1_8814B(x) | BIT_DRVINFO_SZ_V1_8814B(v)) + +/* 2 REG_MACID_8814B (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_V1_8814B 0 +#define BIT_MASK_MACID_V1_8814B 0xffffffffL +#define BIT_MACID_V1_8814B(x) \ + (((x) & BIT_MASK_MACID_V1_8814B) << BIT_SHIFT_MACID_V1_8814B) +#define BITS_MACID_V1_8814B \ + (BIT_MASK_MACID_V1_8814B << BIT_SHIFT_MACID_V1_8814B) +#define BIT_CLEAR_MACID_V1_8814B(x) ((x) & (~BITS_MACID_V1_8814B)) +#define BIT_GET_MACID_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_V1_8814B) & BIT_MASK_MACID_V1_8814B) +#define BIT_SET_MACID_V1_8814B(x, v) \ + (BIT_CLEAR_MACID_V1_8814B(x) | BIT_MACID_V1_8814B(v)) + +/* 2 REG_MACID_H_8814B (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_H_V1_8814B 0 +#define BIT_MASK_MACID_H_V1_8814B 0xffff +#define BIT_MACID_H_V1_8814B(x) \ + (((x) & BIT_MASK_MACID_H_V1_8814B) << BIT_SHIFT_MACID_H_V1_8814B) +#define BITS_MACID_H_V1_8814B \ + (BIT_MASK_MACID_H_V1_8814B << BIT_SHIFT_MACID_H_V1_8814B) +#define BIT_CLEAR_MACID_H_V1_8814B(x) ((x) & (~BITS_MACID_H_V1_8814B)) +#define BIT_GET_MACID_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_H_V1_8814B) & BIT_MASK_MACID_H_V1_8814B) +#define BIT_SET_MACID_H_V1_8814B(x, v) \ + (BIT_CLEAR_MACID_H_V1_8814B(x) | BIT_MACID_H_V1_8814B(v)) /* 2 REG_BSSID_8814B (BSSID REGISTER) */ -#define BIT_SHIFT_BSSID_8814B 0 -#define BIT_MASK_BSSID_8814B 0xffffffffffffL -#define BIT_BSSID_8814B(x) (((x) & BIT_MASK_BSSID_8814B) << BIT_SHIFT_BSSID_8814B) -#define BIT_GET_BSSID_8814B(x) (((x) >> BIT_SHIFT_BSSID_8814B) & BIT_MASK_BSSID_8814B) - - - -/* 2 REG_MAR_8814B (MULTICAST ADDRESS REGISTER) */ - -#define BIT_SHIFT_MAR_8814B 0 -#define BIT_MASK_MAR_8814B 0xffffffffffffffffL -#define BIT_MAR_8814B(x) (((x) & BIT_MASK_MAR_8814B) << BIT_SHIFT_MAR_8814B) -#define BIT_GET_MAR_8814B(x) (((x) >> BIT_SHIFT_MAR_8814B) & BIT_MASK_MAR_8814B) - - - -/* 2 REG_MBIDCAMCFG_1_8814B (MBSSID CAM CONFIGURATION REGISTER) */ - -#define BIT_SHIFT_MBIDCAM_RWDATA_L_8814B 0 -#define BIT_MASK_MBIDCAM_RWDATA_L_8814B 0xffffffffL -#define BIT_MBIDCAM_RWDATA_L_8814B(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8814B) << BIT_SHIFT_MBIDCAM_RWDATA_L_8814B) -#define BIT_GET_MBIDCAM_RWDATA_L_8814B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8814B) & BIT_MASK_MBIDCAM_RWDATA_L_8814B) - - +#define BIT_SHIFT_BSSID_V1_8814B 0 +#define BIT_MASK_BSSID_V1_8814B 0xffffffffL +#define BIT_BSSID_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID_V1_8814B) << BIT_SHIFT_BSSID_V1_8814B) +#define BITS_BSSID_V1_8814B \ + (BIT_MASK_BSSID_V1_8814B << BIT_SHIFT_BSSID_V1_8814B) +#define BIT_CLEAR_BSSID_V1_8814B(x) ((x) & (~BITS_BSSID_V1_8814B)) +#define BIT_GET_BSSID_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID_V1_8814B) & BIT_MASK_BSSID_V1_8814B) +#define BIT_SET_BSSID_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID_V1_8814B(x) | BIT_BSSID_V1_8814B(v)) -/* 2 REG_MBIDCAMCFG_2_8814B (MBSSID CAM CONFIGURATION REGISTER) */ -#define BIT_MBIDCAM_POLL_8814B BIT(31) -#define BIT_MBIDCAM_WT_EN_8814B BIT(30) - -#define BIT_SHIFT_MBIDCAM_ADDR_8814B 24 -#define BIT_MASK_MBIDCAM_ADDR_8814B 0x1f -#define BIT_MBIDCAM_ADDR_8814B(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8814B) << BIT_SHIFT_MBIDCAM_ADDR_8814B) -#define BIT_GET_MBIDCAM_ADDR_8814B(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8814B) & BIT_MASK_MBIDCAM_ADDR_8814B) - - -#define BIT_MBIDCAM_VALID_8814B BIT(23) -#define BIT_LSIC_TXOP_EN_8814B BIT(17) -#define BIT_CTS_EN_8814B BIT(16) - -#define BIT_SHIFT_MBIDCAM_RWDATA_H_8814B 0 -#define BIT_MASK_MBIDCAM_RWDATA_H_8814B 0xffff -#define BIT_MBIDCAM_RWDATA_H_8814B(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8814B) << BIT_SHIFT_MBIDCAM_RWDATA_H_8814B) -#define BIT_GET_MBIDCAM_RWDATA_H_8814B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8814B) & BIT_MASK_MBIDCAM_RWDATA_H_8814B) - - - -/* 2 REG_ZLD_NUM_8814B */ - -#define BIT_SHIFT_ZLD_NUM_8814B 0 -#define BIT_MASK_ZLD_NUM_8814B 0xff -#define BIT_ZLD_NUM_8814B(x) (((x) & BIT_MASK_ZLD_NUM_8814B) << BIT_SHIFT_ZLD_NUM_8814B) -#define BIT_GET_ZLD_NUM_8814B(x) (((x) >> BIT_SHIFT_ZLD_NUM_8814B) & BIT_MASK_ZLD_NUM_8814B) +/* 2 REG_BSSID_H_8814B (BSSID REGISTER) */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_BSSID_H_V1_8814B 0 +#define BIT_MASK_BSSID_H_V1_8814B 0xffff +#define BIT_BSSID_H_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID_H_V1_8814B) << BIT_SHIFT_BSSID_H_V1_8814B) +#define BITS_BSSID_H_V1_8814B \ + (BIT_MASK_BSSID_H_V1_8814B << BIT_SHIFT_BSSID_H_V1_8814B) +#define BIT_CLEAR_BSSID_H_V1_8814B(x) ((x) & (~BITS_BSSID_H_V1_8814B)) +#define BIT_GET_BSSID_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID_H_V1_8814B) & BIT_MASK_BSSID_H_V1_8814B) +#define BIT_SET_BSSID_H_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID_H_V1_8814B(x) | BIT_BSSID_H_V1_8814B(v)) -/* 2 REG_UDF_THSD_8814B */ +/* 2 REG_MAR_8814B (MULTICAST ADDRESS REGISTER) */ -#define BIT_SHIFT_UDF_THSD_8814B 0 -#define BIT_MASK_UDF_THSD_8814B 0xff -#define BIT_UDF_THSD_8814B(x) (((x) & BIT_MASK_UDF_THSD_8814B) << BIT_SHIFT_UDF_THSD_8814B) -#define BIT_GET_UDF_THSD_8814B(x) (((x) >> BIT_SHIFT_UDF_THSD_8814B) & BIT_MASK_UDF_THSD_8814B) +#define BIT_SHIFT_MAR_V1_8814B 0 +#define BIT_MASK_MAR_V1_8814B 0xffffffffL +#define BIT_MAR_V1_8814B(x) \ + (((x) & BIT_MASK_MAR_V1_8814B) << BIT_SHIFT_MAR_V1_8814B) +#define BITS_MAR_V1_8814B (BIT_MASK_MAR_V1_8814B << BIT_SHIFT_MAR_V1_8814B) +#define BIT_CLEAR_MAR_V1_8814B(x) ((x) & (~BITS_MAR_V1_8814B)) +#define BIT_GET_MAR_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MAR_V1_8814B) & BIT_MASK_MAR_V1_8814B) +#define BIT_SET_MAR_V1_8814B(x, v) \ + (BIT_CLEAR_MAR_V1_8814B(x) | BIT_MAR_V1_8814B(v)) + +/* 2 REG_MAR_H_8814B (MULTICAST ADDRESS REGISTER) */ + +#define BIT_SHIFT_MAR_H_V1_8814B 0 +#define BIT_MASK_MAR_H_V1_8814B 0xffffffffL +#define BIT_MAR_H_V1_8814B(x) \ + (((x) & BIT_MASK_MAR_H_V1_8814B) << BIT_SHIFT_MAR_H_V1_8814B) +#define BITS_MAR_H_V1_8814B \ + (BIT_MASK_MAR_H_V1_8814B << BIT_SHIFT_MAR_H_V1_8814B) +#define BIT_CLEAR_MAR_H_V1_8814B(x) ((x) & (~BITS_MAR_H_V1_8814B)) +#define BIT_GET_MAR_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MAR_H_V1_8814B) & BIT_MASK_MAR_H_V1_8814B) +#define BIT_SET_MAR_H_V1_8814B(x, v) \ + (BIT_CLEAR_MAR_H_V1_8814B(x) | BIT_MAR_H_V1_8814B(v)) +/* 2 REG_RSVD_8814B */ +/* 2 REG_WMAC_DEBUG_SEL_8814B */ + +#define BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B 3 +#define BIT_MASK_WMAC_ARB_DBG_SEL_8814B 0x3 +#define BIT_WMAC_ARB_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_WMAC_ARB_DBG_SEL_8814B) \ + << BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B) +#define BITS_WMAC_ARB_DBG_SEL_8814B \ + (BIT_MASK_WMAC_ARB_DBG_SEL_8814B << BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B) +#define BIT_CLEAR_WMAC_ARB_DBG_SEL_8814B(x) \ + ((x) & (~BITS_WMAC_ARB_DBG_SEL_8814B)) +#define BIT_GET_WMAC_ARB_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B) & \ + BIT_MASK_WMAC_ARB_DBG_SEL_8814B) +#define BIT_SET_WMAC_ARB_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_WMAC_ARB_DBG_SEL_8814B(x) | BIT_WMAC_ARB_DBG_SEL_8814B(v)) + +#define BIT_WMAC_EXT_DBG_SEL_8814B BIT(2) + +#define BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B 0 +#define BIT_MASK_WMAC_MU_DBGSEL_V1_8814B 0x3 +#define BIT_WMAC_MU_DBGSEL_V1_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_DBGSEL_V1_8814B) \ + << BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B) +#define BITS_WMAC_MU_DBGSEL_V1_8814B \ + (BIT_MASK_WMAC_MU_DBGSEL_V1_8814B << BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B) +#define BIT_CLEAR_WMAC_MU_DBGSEL_V1_8814B(x) \ + ((x) & (~BITS_WMAC_MU_DBGSEL_V1_8814B)) +#define BIT_GET_WMAC_MU_DBGSEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B) & \ + BIT_MASK_WMAC_MU_DBGSEL_V1_8814B) +#define BIT_SET_WMAC_MU_DBGSEL_V1_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_DBGSEL_V1_8814B(x) | BIT_WMAC_MU_DBGSEL_V1_8814B(v)) /* 2 REG_WMAC_TCR_TSFT_OFS_8814B */ #define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B 0 #define BIT_MASK_WMAC_TCR_TSFT_OFS_8814B 0xffff -#define BIT_WMAC_TCR_TSFT_OFS_8814B(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8814B) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) -#define BIT_GET_WMAC_TCR_TSFT_OFS_8814B(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) & BIT_MASK_WMAC_TCR_TSFT_OFS_8814B) - +#define BIT_WMAC_TCR_TSFT_OFS_8814B(x) \ + (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8814B) \ + << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) +#define BITS_WMAC_TCR_TSFT_OFS_8814B \ + (BIT_MASK_WMAC_TCR_TSFT_OFS_8814B << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8814B(x) \ + ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8814B)) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) & \ + BIT_MASK_WMAC_TCR_TSFT_OFS_8814B) +#define BIT_SET_WMAC_TCR_TSFT_OFS_8814B(x, v) \ + (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8814B(x) | BIT_WMAC_TCR_TSFT_OFS_8814B(v)) +/* 2 REG_UDF_THSD_8814B */ +#define BIT_UDF_THSD_V1_8814B BIT(7) + +#define BIT_SHIFT_UDF_THSD_VALUE_8814B 0 +#define BIT_MASK_UDF_THSD_VALUE_8814B 0x7f +#define BIT_UDF_THSD_VALUE_8814B(x) \ + (((x) & BIT_MASK_UDF_THSD_VALUE_8814B) \ + << BIT_SHIFT_UDF_THSD_VALUE_8814B) +#define BITS_UDF_THSD_VALUE_8814B \ + (BIT_MASK_UDF_THSD_VALUE_8814B << BIT_SHIFT_UDF_THSD_VALUE_8814B) +#define BIT_CLEAR_UDF_THSD_VALUE_8814B(x) ((x) & (~BITS_UDF_THSD_VALUE_8814B)) +#define BIT_GET_UDF_THSD_VALUE_8814B(x) \ + (((x) >> BIT_SHIFT_UDF_THSD_VALUE_8814B) & \ + BIT_MASK_UDF_THSD_VALUE_8814B) +#define BIT_SET_UDF_THSD_VALUE_8814B(x, v) \ + (BIT_CLEAR_UDF_THSD_VALUE_8814B(x) | BIT_UDF_THSD_VALUE_8814B(v)) -/* 2 REG_MCU_TEST_2_V1_8814B */ +/* 2 REG_ZLD_NUM_8814B */ -#define BIT_SHIFT_MCU_RSVD_2_V1_8814B 0 -#define BIT_MASK_MCU_RSVD_2_V1_8814B 0xffff -#define BIT_MCU_RSVD_2_V1_8814B(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8814B) << BIT_SHIFT_MCU_RSVD_2_V1_8814B) -#define BIT_GET_MCU_RSVD_2_V1_8814B(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8814B) & BIT_MASK_MCU_RSVD_2_V1_8814B) +#define BIT_SHIFT_ZLD_NUM_8814B 0 +#define BIT_MASK_ZLD_NUM_8814B 0xff +#define BIT_ZLD_NUM_8814B(x) \ + (((x) & BIT_MASK_ZLD_NUM_8814B) << BIT_SHIFT_ZLD_NUM_8814B) +#define BITS_ZLD_NUM_8814B (BIT_MASK_ZLD_NUM_8814B << BIT_SHIFT_ZLD_NUM_8814B) +#define BIT_CLEAR_ZLD_NUM_8814B(x) ((x) & (~BITS_ZLD_NUM_8814B)) +#define BIT_GET_ZLD_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ZLD_NUM_8814B) & BIT_MASK_ZLD_NUM_8814B) +#define BIT_SET_ZLD_NUM_8814B(x, v) \ + (BIT_CLEAR_ZLD_NUM_8814B(x) | BIT_ZLD_NUM_8814B(v)) +/* 2 REG_STMP_THSD_8814B */ +#define BIT_SHIFT_STMP_THSD_8814B 0 +#define BIT_MASK_STMP_THSD_8814B 0xff +#define BIT_STMP_THSD_8814B(x) \ + (((x) & BIT_MASK_STMP_THSD_8814B) << BIT_SHIFT_STMP_THSD_8814B) +#define BITS_STMP_THSD_8814B \ + (BIT_MASK_STMP_THSD_8814B << BIT_SHIFT_STMP_THSD_8814B) +#define BIT_CLEAR_STMP_THSD_8814B(x) ((x) & (~BITS_STMP_THSD_8814B)) +#define BIT_GET_STMP_THSD_8814B(x) \ + (((x) >> BIT_SHIFT_STMP_THSD_8814B) & BIT_MASK_STMP_THSD_8814B) +#define BIT_SET_STMP_THSD_8814B(x, v) \ + (BIT_CLEAR_STMP_THSD_8814B(x) | BIT_STMP_THSD_8814B(v)) /* 2 REG_WMAC_TXTIMEOUT_8814B */ #define BIT_SHIFT_WMAC_TXTIMEOUT_8814B 0 #define BIT_MASK_WMAC_TXTIMEOUT_8814B 0xff -#define BIT_WMAC_TXTIMEOUT_8814B(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8814B) << BIT_SHIFT_WMAC_TXTIMEOUT_8814B) -#define BIT_GET_WMAC_TXTIMEOUT_8814B(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8814B) & BIT_MASK_WMAC_TXTIMEOUT_8814B) +#define BIT_WMAC_TXTIMEOUT_8814B(x) \ + (((x) & BIT_MASK_WMAC_TXTIMEOUT_8814B) \ + << BIT_SHIFT_WMAC_TXTIMEOUT_8814B) +#define BITS_WMAC_TXTIMEOUT_8814B \ + (BIT_MASK_WMAC_TXTIMEOUT_8814B << BIT_SHIFT_WMAC_TXTIMEOUT_8814B) +#define BIT_CLEAR_WMAC_TXTIMEOUT_8814B(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8814B)) +#define BIT_GET_WMAC_TXTIMEOUT_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8814B) & \ + BIT_MASK_WMAC_TXTIMEOUT_8814B) +#define BIT_SET_WMAC_TXTIMEOUT_8814B(x, v) \ + (BIT_CLEAR_WMAC_TXTIMEOUT_8814B(x) | BIT_WMAC_TXTIMEOUT_8814B(v)) +/* 2 REG_MCU_TEST_2_V1_8814B */ +#define BIT_SHIFT_MCU_RSVD_2_V1_8814B 0 +#define BIT_MASK_MCU_RSVD_2_V1_8814B 0xffff +#define BIT_MCU_RSVD_2_V1_8814B(x) \ + (((x) & BIT_MASK_MCU_RSVD_2_V1_8814B) << BIT_SHIFT_MCU_RSVD_2_V1_8814B) +#define BITS_MCU_RSVD_2_V1_8814B \ + (BIT_MASK_MCU_RSVD_2_V1_8814B << BIT_SHIFT_MCU_RSVD_2_V1_8814B) +#define BIT_CLEAR_MCU_RSVD_2_V1_8814B(x) ((x) & (~BITS_MCU_RSVD_2_V1_8814B)) +#define BIT_GET_MCU_RSVD_2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8814B) & BIT_MASK_MCU_RSVD_2_V1_8814B) +#define BIT_SET_MCU_RSVD_2_V1_8814B(x, v) \ + (BIT_CLEAR_MCU_RSVD_2_V1_8814B(x) | BIT_MCU_RSVD_2_V1_8814B(v)) -/* 2 REG_STMP_THSD_8814B */ +/* 2 REG_USTIME_EDCA_8814B (US TIME TUNING FOR EDCA REGISTER) */ -#define BIT_SHIFT_STMP_THSD_8814B 0 -#define BIT_MASK_STMP_THSD_8814B 0xff -#define BIT_STMP_THSD_8814B(x) (((x) & BIT_MASK_STMP_THSD_8814B) << BIT_SHIFT_STMP_THSD_8814B) -#define BIT_GET_STMP_THSD_8814B(x) (((x) >> BIT_SHIFT_STMP_THSD_8814B) & BIT_MASK_STMP_THSD_8814B) +#define BIT_SHIFT_USTIME_EDCA_8814B 0 +#define BIT_MASK_USTIME_EDCA_8814B 0xff +#define BIT_USTIME_EDCA_8814B(x) \ + (((x) & BIT_MASK_USTIME_EDCA_8814B) << BIT_SHIFT_USTIME_EDCA_8814B) +#define BITS_USTIME_EDCA_8814B \ + (BIT_MASK_USTIME_EDCA_8814B << BIT_SHIFT_USTIME_EDCA_8814B) +#define BIT_CLEAR_USTIME_EDCA_8814B(x) ((x) & (~BITS_USTIME_EDCA_8814B)) +#define BIT_GET_USTIME_EDCA_8814B(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA_8814B) & BIT_MASK_USTIME_EDCA_8814B) +#define BIT_SET_USTIME_EDCA_8814B(x, v) \ + (BIT_CLEAR_USTIME_EDCA_8814B(x) | BIT_USTIME_EDCA_8814B(v)) +/* 2 REG_ACKTO_CCK_8814B (ACK TIMEOUT REGISTER FOR CCK RATE) */ +#define BIT_SHIFT_ACKTO_CCK_8814B 0 +#define BIT_MASK_ACKTO_CCK_8814B 0xff +#define BIT_ACKTO_CCK_8814B(x) \ + (((x) & BIT_MASK_ACKTO_CCK_8814B) << BIT_SHIFT_ACKTO_CCK_8814B) +#define BITS_ACKTO_CCK_8814B \ + (BIT_MASK_ACKTO_CCK_8814B << BIT_SHIFT_ACKTO_CCK_8814B) +#define BIT_CLEAR_ACKTO_CCK_8814B(x) ((x) & (~BITS_ACKTO_CCK_8814B)) +#define BIT_GET_ACKTO_CCK_8814B(x) \ + (((x) >> BIT_SHIFT_ACKTO_CCK_8814B) & BIT_MASK_ACKTO_CCK_8814B) +#define BIT_SET_ACKTO_CCK_8814B(x, v) \ + (BIT_CLEAR_ACKTO_CCK_8814B(x) | BIT_ACKTO_CCK_8814B(v)) /* 2 REG_MAC_SPEC_SIFS_8814B (SPECIFICATION SIFS REGISTER) */ #define BIT_SHIFT_SPEC_SIFS_OFDM_8814B 8 #define BIT_MASK_SPEC_SIFS_OFDM_8814B 0xff -#define BIT_SPEC_SIFS_OFDM_8814B(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8814B) << BIT_SHIFT_SPEC_SIFS_OFDM_8814B) -#define BIT_GET_SPEC_SIFS_OFDM_8814B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8814B) & BIT_MASK_SPEC_SIFS_OFDM_8814B) - - +#define BIT_SPEC_SIFS_OFDM_8814B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_8814B) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_8814B) +#define BITS_SPEC_SIFS_OFDM_8814B \ + (BIT_MASK_SPEC_SIFS_OFDM_8814B << BIT_SHIFT_SPEC_SIFS_OFDM_8814B) +#define BIT_CLEAR_SPEC_SIFS_OFDM_8814B(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8814B)) +#define BIT_GET_SPEC_SIFS_OFDM_8814B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8814B) & \ + BIT_MASK_SPEC_SIFS_OFDM_8814B) +#define BIT_SET_SPEC_SIFS_OFDM_8814B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_8814B(x) | BIT_SPEC_SIFS_OFDM_8814B(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_8814B 0 #define BIT_MASK_SPEC_SIFS_CCK_8814B 0xff -#define BIT_SPEC_SIFS_CCK_8814B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8814B) << BIT_SHIFT_SPEC_SIFS_CCK_8814B) -#define BIT_GET_SPEC_SIFS_CCK_8814B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8814B) & BIT_MASK_SPEC_SIFS_CCK_8814B) - - - -/* 2 REG_ACKTO_CCK_8814B (ACK TIMEOUT REGISTER FOR CCK RATE) */ - -#define BIT_SHIFT_ACKTO_CCK_8814B 0 -#define BIT_MASK_ACKTO_CCK_8814B 0xff -#define BIT_ACKTO_CCK_8814B(x) (((x) & BIT_MASK_ACKTO_CCK_8814B) << BIT_SHIFT_ACKTO_CCK_8814B) -#define BIT_GET_ACKTO_CCK_8814B(x) (((x) >> BIT_SHIFT_ACKTO_CCK_8814B) & BIT_MASK_ACKTO_CCK_8814B) - - - -/* 2 REG_USTIME_EDCA_8814B (US TIME TUNING FOR EDCA REGISTER) */ +#define BIT_SPEC_SIFS_CCK_8814B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_8814B) << BIT_SHIFT_SPEC_SIFS_CCK_8814B) +#define BITS_SPEC_SIFS_CCK_8814B \ + (BIT_MASK_SPEC_SIFS_CCK_8814B << BIT_SHIFT_SPEC_SIFS_CCK_8814B) +#define BIT_CLEAR_SPEC_SIFS_CCK_8814B(x) ((x) & (~BITS_SPEC_SIFS_CCK_8814B)) +#define BIT_GET_SPEC_SIFS_CCK_8814B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8814B) & BIT_MASK_SPEC_SIFS_CCK_8814B) +#define BIT_SET_SPEC_SIFS_CCK_8814B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_8814B(x) | BIT_SPEC_SIFS_CCK_8814B(v)) -#define BIT_SHIFT_USTIME_EDCA_V1_8814B 0 -#define BIT_MASK_USTIME_EDCA_V1_8814B 0x1ff -#define BIT_USTIME_EDCA_V1_8814B(x) (((x) & BIT_MASK_USTIME_EDCA_V1_8814B) << BIT_SHIFT_USTIME_EDCA_V1_8814B) -#define BIT_GET_USTIME_EDCA_V1_8814B(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8814B) & BIT_MASK_USTIME_EDCA_V1_8814B) +/* 2 REG_RESP_SIFS_CCK_8814B (RESPONSE SIFS FOR CCK REGISTER) */ +#define BIT_SHIFT_SIFS_R2T_CCK_8814B 8 +#define BIT_MASK_SIFS_R2T_CCK_8814B 0xff +#define BIT_SIFS_R2T_CCK_8814B(x) \ + (((x) & BIT_MASK_SIFS_R2T_CCK_8814B) << BIT_SHIFT_SIFS_R2T_CCK_8814B) +#define BITS_SIFS_R2T_CCK_8814B \ + (BIT_MASK_SIFS_R2T_CCK_8814B << BIT_SHIFT_SIFS_R2T_CCK_8814B) +#define BIT_CLEAR_SIFS_R2T_CCK_8814B(x) ((x) & (~BITS_SIFS_R2T_CCK_8814B)) +#define BIT_GET_SIFS_R2T_CCK_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8814B) & BIT_MASK_SIFS_R2T_CCK_8814B) +#define BIT_SET_SIFS_R2T_CCK_8814B(x, v) \ + (BIT_CLEAR_SIFS_R2T_CCK_8814B(x) | BIT_SIFS_R2T_CCK_8814B(v)) +#define BIT_SHIFT_SIFS_T2T_CCK_8814B 0 +#define BIT_MASK_SIFS_T2T_CCK_8814B 0xff +#define BIT_SIFS_T2T_CCK_8814B(x) \ + (((x) & BIT_MASK_SIFS_T2T_CCK_8814B) << BIT_SHIFT_SIFS_T2T_CCK_8814B) +#define BITS_SIFS_T2T_CCK_8814B \ + (BIT_MASK_SIFS_T2T_CCK_8814B << BIT_SHIFT_SIFS_T2T_CCK_8814B) +#define BIT_CLEAR_SIFS_T2T_CCK_8814B(x) ((x) & (~BITS_SIFS_T2T_CCK_8814B)) +#define BIT_GET_SIFS_T2T_CCK_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8814B) & BIT_MASK_SIFS_T2T_CCK_8814B) +#define BIT_SET_SIFS_T2T_CCK_8814B(x, v) \ + (BIT_CLEAR_SIFS_T2T_CCK_8814B(x) | BIT_SIFS_T2T_CCK_8814B(v)) /* 2 REG_RESP_SIFS_OFDM_8814B (RESPONSE SIFS FOR OFDM REGISTER) */ #define BIT_SHIFT_SIFS_R2T_OFDM_8814B 8 #define BIT_MASK_SIFS_R2T_OFDM_8814B 0xff -#define BIT_SIFS_R2T_OFDM_8814B(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8814B) << BIT_SHIFT_SIFS_R2T_OFDM_8814B) -#define BIT_GET_SIFS_R2T_OFDM_8814B(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8814B) & BIT_MASK_SIFS_R2T_OFDM_8814B) - - +#define BIT_SIFS_R2T_OFDM_8814B(x) \ + (((x) & BIT_MASK_SIFS_R2T_OFDM_8814B) << BIT_SHIFT_SIFS_R2T_OFDM_8814B) +#define BITS_SIFS_R2T_OFDM_8814B \ + (BIT_MASK_SIFS_R2T_OFDM_8814B << BIT_SHIFT_SIFS_R2T_OFDM_8814B) +#define BIT_CLEAR_SIFS_R2T_OFDM_8814B(x) ((x) & (~BITS_SIFS_R2T_OFDM_8814B)) +#define BIT_GET_SIFS_R2T_OFDM_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8814B) & BIT_MASK_SIFS_R2T_OFDM_8814B) +#define BIT_SET_SIFS_R2T_OFDM_8814B(x, v) \ + (BIT_CLEAR_SIFS_R2T_OFDM_8814B(x) | BIT_SIFS_R2T_OFDM_8814B(v)) #define BIT_SHIFT_SIFS_T2T_OFDM_8814B 0 #define BIT_MASK_SIFS_T2T_OFDM_8814B 0xff -#define BIT_SIFS_T2T_OFDM_8814B(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8814B) << BIT_SHIFT_SIFS_T2T_OFDM_8814B) -#define BIT_GET_SIFS_T2T_OFDM_8814B(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8814B) & BIT_MASK_SIFS_T2T_OFDM_8814B) - - - -/* 2 REG_RESP_SIFS_CCK_8814B (RESPONSE SIFS FOR CCK REGISTER) */ - -#define BIT_SHIFT_SIFS_R2T_CCK_8814B 8 -#define BIT_MASK_SIFS_R2T_CCK_8814B 0xff -#define BIT_SIFS_R2T_CCK_8814B(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8814B) << BIT_SHIFT_SIFS_R2T_CCK_8814B) -#define BIT_GET_SIFS_R2T_CCK_8814B(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8814B) & BIT_MASK_SIFS_R2T_CCK_8814B) - +#define BIT_SIFS_T2T_OFDM_8814B(x) \ + (((x) & BIT_MASK_SIFS_T2T_OFDM_8814B) << BIT_SHIFT_SIFS_T2T_OFDM_8814B) +#define BITS_SIFS_T2T_OFDM_8814B \ + (BIT_MASK_SIFS_T2T_OFDM_8814B << BIT_SHIFT_SIFS_T2T_OFDM_8814B) +#define BIT_CLEAR_SIFS_T2T_OFDM_8814B(x) ((x) & (~BITS_SIFS_T2T_OFDM_8814B)) +#define BIT_GET_SIFS_T2T_OFDM_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8814B) & BIT_MASK_SIFS_T2T_OFDM_8814B) +#define BIT_SET_SIFS_T2T_OFDM_8814B(x, v) \ + (BIT_CLEAR_SIFS_T2T_OFDM_8814B(x) | BIT_SIFS_T2T_OFDM_8814B(v)) +/* 2 REG_ACKTO_8814B (ACK TIMEOUT REGISTER) */ -#define BIT_SHIFT_SIFS_T2T_CCK_8814B 0 -#define BIT_MASK_SIFS_T2T_CCK_8814B 0xff -#define BIT_SIFS_T2T_CCK_8814B(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8814B) << BIT_SHIFT_SIFS_T2T_CCK_8814B) -#define BIT_GET_SIFS_T2T_CCK_8814B(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8814B) & BIT_MASK_SIFS_T2T_CCK_8814B) +#define BIT_SHIFT_ACKTO_8814B 0 +#define BIT_MASK_ACKTO_8814B 0xff +#define BIT_ACKTO_8814B(x) \ + (((x) & BIT_MASK_ACKTO_8814B) << BIT_SHIFT_ACKTO_8814B) +#define BITS_ACKTO_8814B (BIT_MASK_ACKTO_8814B << BIT_SHIFT_ACKTO_8814B) +#define BIT_CLEAR_ACKTO_8814B(x) ((x) & (~BITS_ACKTO_8814B)) +#define BIT_GET_ACKTO_8814B(x) \ + (((x) >> BIT_SHIFT_ACKTO_8814B) & BIT_MASK_ACKTO_8814B) +#define BIT_SET_ACKTO_8814B(x, v) \ + (BIT_CLEAR_ACKTO_8814B(x) | BIT_ACKTO_8814B(v)) +/* 2 REG_CTS2TO_8814B (CTS2 TIMEOUT REGISTER) */ +#define BIT_SHIFT_CTS2TO_8814B 0 +#define BIT_MASK_CTS2TO_8814B 0xff +#define BIT_CTS2TO_8814B(x) \ + (((x) & BIT_MASK_CTS2TO_8814B) << BIT_SHIFT_CTS2TO_8814B) +#define BITS_CTS2TO_8814B (BIT_MASK_CTS2TO_8814B << BIT_SHIFT_CTS2TO_8814B) +#define BIT_CLEAR_CTS2TO_8814B(x) ((x) & (~BITS_CTS2TO_8814B)) +#define BIT_GET_CTS2TO_8814B(x) \ + (((x) >> BIT_SHIFT_CTS2TO_8814B) & BIT_MASK_CTS2TO_8814B) +#define BIT_SET_CTS2TO_8814B(x, v) \ + (BIT_CLEAR_CTS2TO_8814B(x) | BIT_CTS2TO_8814B(v)) /* 2 REG_EIFS_8814B (EIFS REGISTER) */ #define BIT_SHIFT_EIFS_8814B 0 #define BIT_MASK_EIFS_8814B 0xffff #define BIT_EIFS_8814B(x) (((x) & BIT_MASK_EIFS_8814B) << BIT_SHIFT_EIFS_8814B) -#define BIT_GET_EIFS_8814B(x) (((x) >> BIT_SHIFT_EIFS_8814B) & BIT_MASK_EIFS_8814B) - - - -/* 2 REG_CTS2TO_8814B (CTS2 TIMEOUT REGISTER) */ - -#define BIT_SHIFT_CTS2TO_8814B 0 -#define BIT_MASK_CTS2TO_8814B 0xff -#define BIT_CTS2TO_8814B(x) (((x) & BIT_MASK_CTS2TO_8814B) << BIT_SHIFT_CTS2TO_8814B) -#define BIT_GET_CTS2TO_8814B(x) (((x) >> BIT_SHIFT_CTS2TO_8814B) & BIT_MASK_CTS2TO_8814B) - +#define BITS_EIFS_8814B (BIT_MASK_EIFS_8814B << BIT_SHIFT_EIFS_8814B) +#define BIT_CLEAR_EIFS_8814B(x) ((x) & (~BITS_EIFS_8814B)) +#define BIT_GET_EIFS_8814B(x) \ + (((x) >> BIT_SHIFT_EIFS_8814B) & BIT_MASK_EIFS_8814B) +#define BIT_SET_EIFS_8814B(x, v) (BIT_CLEAR_EIFS_8814B(x) | BIT_EIFS_8814B(v)) - -/* 2 REG_ACKTO_8814B (ACK TIMEOUT REGISTER) */ - -#define BIT_SHIFT_ACKTO_8814B 0 -#define BIT_MASK_ACKTO_8814B 0xff -#define BIT_ACKTO_8814B(x) (((x) & BIT_MASK_ACKTO_8814B) << BIT_SHIFT_ACKTO_8814B) -#define BIT_GET_ACKTO_8814B(x) (((x) >> BIT_SHIFT_ACKTO_8814B) & BIT_MASK_ACKTO_8814B) - - - -/* 2 REG_RPFM_MAP0_8814B (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 0) */ +/* 2 REG_RPFM_MAP0_8814B */ #define BIT_MGT_RPFM15EN_8814B BIT(15) #define BIT_MGT_RPFM14EN_8814B BIT(14) #define BIT_MGT_RPFM13EN_8814B BIT(13) @@ -8866,7 +20965,7 @@ #define BIT_MGT_RPFM1EN_8814B BIT(1) #define BIT_MGT_RPFM0EN_8814B BIT(0) -/* 2 REG_RPFM_MAP1_8814B (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 1) */ +/* 2 REG_RPFM_MAP1_V1_8814B */ #define BIT_DATA_RPFM15EN_8814B BIT(15) #define BIT_DATA_RPFM14EN_8814B BIT(14) #define BIT_DATA_RPFM13EN_8814B BIT(13) @@ -8891,44 +20990,66 @@ #define BIT_SHIFT_RPFM_CAM_ADDR_8814B 0 #define BIT_MASK_RPFM_CAM_ADDR_8814B 0x7f -#define BIT_RPFM_CAM_ADDR_8814B(x) (((x) & BIT_MASK_RPFM_CAM_ADDR_8814B) << BIT_SHIFT_RPFM_CAM_ADDR_8814B) -#define BIT_GET_RPFM_CAM_ADDR_8814B(x) (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8814B) & BIT_MASK_RPFM_CAM_ADDR_8814B) - - +#define BIT_RPFM_CAM_ADDR_8814B(x) \ + (((x) & BIT_MASK_RPFM_CAM_ADDR_8814B) << BIT_SHIFT_RPFM_CAM_ADDR_8814B) +#define BITS_RPFM_CAM_ADDR_8814B \ + (BIT_MASK_RPFM_CAM_ADDR_8814B << BIT_SHIFT_RPFM_CAM_ADDR_8814B) +#define BIT_CLEAR_RPFM_CAM_ADDR_8814B(x) ((x) & (~BITS_RPFM_CAM_ADDR_8814B)) +#define BIT_GET_RPFM_CAM_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8814B) & BIT_MASK_RPFM_CAM_ADDR_8814B) +#define BIT_SET_RPFM_CAM_ADDR_8814B(x, v) \ + (BIT_CLEAR_RPFM_CAM_ADDR_8814B(x) | BIT_RPFM_CAM_ADDR_8814B(v)) /* 2 REG_RPFM_CAM_RWD_8814B (ACK TIMEOUT REGISTER) */ #define BIT_SHIFT_RPFM_CAM_RWD_8814B 0 #define BIT_MASK_RPFM_CAM_RWD_8814B 0xffffffffL -#define BIT_RPFM_CAM_RWD_8814B(x) (((x) & BIT_MASK_RPFM_CAM_RWD_8814B) << BIT_SHIFT_RPFM_CAM_RWD_8814B) -#define BIT_GET_RPFM_CAM_RWD_8814B(x) (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8814B) & BIT_MASK_RPFM_CAM_RWD_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_RPFM_CAM_RWD_8814B(x) \ + (((x) & BIT_MASK_RPFM_CAM_RWD_8814B) << BIT_SHIFT_RPFM_CAM_RWD_8814B) +#define BITS_RPFM_CAM_RWD_8814B \ + (BIT_MASK_RPFM_CAM_RWD_8814B << BIT_SHIFT_RPFM_CAM_RWD_8814B) +#define BIT_CLEAR_RPFM_CAM_RWD_8814B(x) ((x) & (~BITS_RPFM_CAM_RWD_8814B)) +#define BIT_GET_RPFM_CAM_RWD_8814B(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8814B) & BIT_MASK_RPFM_CAM_RWD_8814B) +#define BIT_SET_RPFM_CAM_RWD_8814B(x, v) \ + (BIT_CLEAR_RPFM_CAM_RWD_8814B(x) | BIT_RPFM_CAM_RWD_8814B(v)) /* 2 REG_NAV_CTRL_8814B (NAV CONTROL REGISTER) */ #define BIT_SHIFT_NAV_UPPER_8814B 16 #define BIT_MASK_NAV_UPPER_8814B 0xff -#define BIT_NAV_UPPER_8814B(x) (((x) & BIT_MASK_NAV_UPPER_8814B) << BIT_SHIFT_NAV_UPPER_8814B) -#define BIT_GET_NAV_UPPER_8814B(x) (((x) >> BIT_SHIFT_NAV_UPPER_8814B) & BIT_MASK_NAV_UPPER_8814B) - - +#define BIT_NAV_UPPER_8814B(x) \ + (((x) & BIT_MASK_NAV_UPPER_8814B) << BIT_SHIFT_NAV_UPPER_8814B) +#define BITS_NAV_UPPER_8814B \ + (BIT_MASK_NAV_UPPER_8814B << BIT_SHIFT_NAV_UPPER_8814B) +#define BIT_CLEAR_NAV_UPPER_8814B(x) ((x) & (~BITS_NAV_UPPER_8814B)) +#define BIT_GET_NAV_UPPER_8814B(x) \ + (((x) >> BIT_SHIFT_NAV_UPPER_8814B) & BIT_MASK_NAV_UPPER_8814B) +#define BIT_SET_NAV_UPPER_8814B(x, v) \ + (BIT_CLEAR_NAV_UPPER_8814B(x) | BIT_NAV_UPPER_8814B(v)) #define BIT_SHIFT_RXMYRTS_NAV_8814B 8 #define BIT_MASK_RXMYRTS_NAV_8814B 0xf -#define BIT_RXMYRTS_NAV_8814B(x) (((x) & BIT_MASK_RXMYRTS_NAV_8814B) << BIT_SHIFT_RXMYRTS_NAV_8814B) -#define BIT_GET_RXMYRTS_NAV_8814B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8814B) & BIT_MASK_RXMYRTS_NAV_8814B) - - +#define BIT_RXMYRTS_NAV_8814B(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_8814B) << BIT_SHIFT_RXMYRTS_NAV_8814B) +#define BITS_RXMYRTS_NAV_8814B \ + (BIT_MASK_RXMYRTS_NAV_8814B << BIT_SHIFT_RXMYRTS_NAV_8814B) +#define BIT_CLEAR_RXMYRTS_NAV_8814B(x) ((x) & (~BITS_RXMYRTS_NAV_8814B)) +#define BIT_GET_RXMYRTS_NAV_8814B(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_8814B) & BIT_MASK_RXMYRTS_NAV_8814B) +#define BIT_SET_RXMYRTS_NAV_8814B(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_8814B(x) | BIT_RXMYRTS_NAV_8814B(v)) #define BIT_SHIFT_RTSRST_8814B 0 #define BIT_MASK_RTSRST_8814B 0xff -#define BIT_RTSRST_8814B(x) (((x) & BIT_MASK_RTSRST_8814B) << BIT_SHIFT_RTSRST_8814B) -#define BIT_GET_RTSRST_8814B(x) (((x) >> BIT_SHIFT_RTSRST_8814B) & BIT_MASK_RTSRST_8814B) - - +#define BIT_RTSRST_8814B(x) \ + (((x) & BIT_MASK_RTSRST_8814B) << BIT_SHIFT_RTSRST_8814B) +#define BITS_RTSRST_8814B (BIT_MASK_RTSRST_8814B << BIT_SHIFT_RTSRST_8814B) +#define BIT_CLEAR_RTSRST_8814B(x) ((x) & (~BITS_RTSRST_8814B)) +#define BIT_GET_RTSRST_8814B(x) \ + (((x) >> BIT_SHIFT_RTSRST_8814B) & BIT_MASK_RTSRST_8814B) +#define BIT_SET_RTSRST_8814B(x, v) \ + (BIT_CLEAR_RTSRST_8814B(x) | BIT_RTSRST_8814B(v)) /* 2 REG_BACAMCMD_8814B (BLOCK ACK CAM COMMAND REGISTER) */ #define BIT_BACAM_POLL_8814B BIT(31) @@ -8937,87 +21058,149 @@ #define BIT_SHIFT_TXSBM_8814B 14 #define BIT_MASK_TXSBM_8814B 0x3 -#define BIT_TXSBM_8814B(x) (((x) & BIT_MASK_TXSBM_8814B) << BIT_SHIFT_TXSBM_8814B) -#define BIT_GET_TXSBM_8814B(x) (((x) >> BIT_SHIFT_TXSBM_8814B) & BIT_MASK_TXSBM_8814B) - - +#define BIT_TXSBM_8814B(x) \ + (((x) & BIT_MASK_TXSBM_8814B) << BIT_SHIFT_TXSBM_8814B) +#define BITS_TXSBM_8814B (BIT_MASK_TXSBM_8814B << BIT_SHIFT_TXSBM_8814B) +#define BIT_CLEAR_TXSBM_8814B(x) ((x) & (~BITS_TXSBM_8814B)) +#define BIT_GET_TXSBM_8814B(x) \ + (((x) >> BIT_SHIFT_TXSBM_8814B) & BIT_MASK_TXSBM_8814B) +#define BIT_SET_TXSBM_8814B(x, v) \ + (BIT_CLEAR_TXSBM_8814B(x) | BIT_TXSBM_8814B(v)) #define BIT_SHIFT_BACAM_ADDR_8814B 0 #define BIT_MASK_BACAM_ADDR_8814B 0x3f -#define BIT_BACAM_ADDR_8814B(x) (((x) & BIT_MASK_BACAM_ADDR_8814B) << BIT_SHIFT_BACAM_ADDR_8814B) -#define BIT_GET_BACAM_ADDR_8814B(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8814B) & BIT_MASK_BACAM_ADDR_8814B) - - +#define BIT_BACAM_ADDR_8814B(x) \ + (((x) & BIT_MASK_BACAM_ADDR_8814B) << BIT_SHIFT_BACAM_ADDR_8814B) +#define BITS_BACAM_ADDR_8814B \ + (BIT_MASK_BACAM_ADDR_8814B << BIT_SHIFT_BACAM_ADDR_8814B) +#define BIT_CLEAR_BACAM_ADDR_8814B(x) ((x) & (~BITS_BACAM_ADDR_8814B)) +#define BIT_GET_BACAM_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_BACAM_ADDR_8814B) & BIT_MASK_BACAM_ADDR_8814B) +#define BIT_SET_BACAM_ADDR_8814B(x, v) \ + (BIT_CLEAR_BACAM_ADDR_8814B(x) | BIT_BACAM_ADDR_8814B(v)) /* 2 REG_BACAMCONTENT_8814B (BLOCK ACK CAM CONTENT REGISTER) */ -#define BIT_SHIFT_BA_CONTENT_H_8814B (32 & CPU_OPT_WIDTH) -#define BIT_MASK_BA_CONTENT_H_8814B 0xffffffffL -#define BIT_BA_CONTENT_H_8814B(x) (((x) & BIT_MASK_BA_CONTENT_H_8814B) << BIT_SHIFT_BA_CONTENT_H_8814B) -#define BIT_GET_BA_CONTENT_H_8814B(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8814B) & BIT_MASK_BA_CONTENT_H_8814B) - - - #define BIT_SHIFT_BA_CONTENT_L_8814B 0 #define BIT_MASK_BA_CONTENT_L_8814B 0xffffffffL -#define BIT_BA_CONTENT_L_8814B(x) (((x) & BIT_MASK_BA_CONTENT_L_8814B) << BIT_SHIFT_BA_CONTENT_L_8814B) -#define BIT_GET_BA_CONTENT_L_8814B(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8814B) & BIT_MASK_BA_CONTENT_L_8814B) - - - -/* 2 REG_WMAC_BITMAP_CTL_8814B */ -#define BIT_BITMAP_VO_8814B BIT(7) -#define BIT_BITMAP_VI_8814B BIT(6) -#define BIT_BITMAP_BE_8814B BIT(5) -#define BIT_BITMAP_BK_8814B BIT(4) - -#define BIT_SHIFT_BITMAP_CONDITION_8814B 2 -#define BIT_MASK_BITMAP_CONDITION_8814B 0x3 -#define BIT_BITMAP_CONDITION_8814B(x) (((x) & BIT_MASK_BITMAP_CONDITION_8814B) << BIT_SHIFT_BITMAP_CONDITION_8814B) -#define BIT_GET_BITMAP_CONDITION_8814B(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8814B) & BIT_MASK_BITMAP_CONDITION_8814B) - - -#define BIT_BITMAP_SSNBK_COUNTER_CLR_8814B BIT(1) -#define BIT_BITMAP_FORCE_8814B BIT(0) - -/* 2 REG_TX_RX_8814B STATUS */ - -#define BIT_SHIFT_RXPKT_TYPE_8814B 2 -#define BIT_MASK_RXPKT_TYPE_8814B 0x3f -#define BIT_RXPKT_TYPE_8814B(x) (((x) & BIT_MASK_RXPKT_TYPE_8814B) << BIT_SHIFT_RXPKT_TYPE_8814B) -#define BIT_GET_RXPKT_TYPE_8814B(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8814B) & BIT_MASK_RXPKT_TYPE_8814B) +#define BIT_BA_CONTENT_L_8814B(x) \ + (((x) & BIT_MASK_BA_CONTENT_L_8814B) << BIT_SHIFT_BA_CONTENT_L_8814B) +#define BITS_BA_CONTENT_L_8814B \ + (BIT_MASK_BA_CONTENT_L_8814B << BIT_SHIFT_BA_CONTENT_L_8814B) +#define BIT_CLEAR_BA_CONTENT_L_8814B(x) ((x) & (~BITS_BA_CONTENT_L_8814B)) +#define BIT_GET_BA_CONTENT_L_8814B(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_L_8814B) & BIT_MASK_BA_CONTENT_L_8814B) +#define BIT_SET_BA_CONTENT_L_8814B(x, v) \ + (BIT_CLEAR_BA_CONTENT_L_8814B(x) | BIT_BA_CONTENT_L_8814B(v)) + +/* 2 REG_BACAMCONTENT_H_8814B (BLOCK ACK CAM CONTENT REGISTER) */ + +#define BIT_SHIFT_BA_CONTENT_H_8814B 0 +#define BIT_MASK_BA_CONTENT_H_8814B 0xffffffffL +#define BIT_BA_CONTENT_H_8814B(x) \ + (((x) & BIT_MASK_BA_CONTENT_H_8814B) << BIT_SHIFT_BA_CONTENT_H_8814B) +#define BITS_BA_CONTENT_H_8814B \ + (BIT_MASK_BA_CONTENT_H_8814B << BIT_SHIFT_BA_CONTENT_H_8814B) +#define BIT_CLEAR_BA_CONTENT_H_8814B(x) ((x) & (~BITS_BA_CONTENT_H_8814B)) +#define BIT_GET_BA_CONTENT_H_8814B(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_H_8814B) & BIT_MASK_BA_CONTENT_H_8814B) +#define BIT_SET_BA_CONTENT_H_8814B(x, v) \ + (BIT_CLEAR_BA_CONTENT_H_8814B(x) | BIT_BA_CONTENT_H_8814B(v)) +/* 2 REG_LBDLY_8814B (LOOPBACK DELAY REGISTER) */ -#define BIT_TXACT_IND_8814B BIT(1) -#define BIT_RXACT_IND_8814B BIT(0) +#define BIT_SHIFT_LBDLY_8814B 0 +#define BIT_MASK_LBDLY_8814B 0x1f +#define BIT_LBDLY_8814B(x) \ + (((x) & BIT_MASK_LBDLY_8814B) << BIT_SHIFT_LBDLY_8814B) +#define BITS_LBDLY_8814B (BIT_MASK_LBDLY_8814B << BIT_SHIFT_LBDLY_8814B) +#define BIT_CLEAR_LBDLY_8814B(x) ((x) & (~BITS_LBDLY_8814B)) +#define BIT_GET_LBDLY_8814B(x) \ + (((x) >> BIT_SHIFT_LBDLY_8814B) & BIT_MASK_LBDLY_8814B) +#define BIT_SET_LBDLY_8814B(x, v) \ + (BIT_CLEAR_LBDLY_8814B(x) | BIT_LBDLY_8814B(v)) /* 2 REG_WMAC_BACAM_RPMEN_8814B */ #define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B 2 #define BIT_MASK_BITMAP_SSNBK_COUNTER_8814B 0x3f -#define BIT_BITMAP_SSNBK_COUNTER_8814B(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8814B) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) -#define BIT_GET_BITMAP_SSNBK_COUNTER_8814B(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) & BIT_MASK_BITMAP_SSNBK_COUNTER_8814B) - +#define BIT_BITMAP_SSNBK_COUNTER_8814B(x) \ + (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8814B) \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) +#define BITS_BITMAP_SSNBK_COUNTER_8814B \ + (BIT_MASK_BITMAP_SSNBK_COUNTER_8814B \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8814B(x) \ + ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8814B)) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8814B(x) \ + (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) & \ + BIT_MASK_BITMAP_SSNBK_COUNTER_8814B) +#define BIT_SET_BITMAP_SSNBK_COUNTER_8814B(x, v) \ + (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8814B(x) | \ + BIT_BITMAP_SSNBK_COUNTER_8814B(v)) #define BIT_BITMAP_EN_8814B BIT(1) #define BIT_WMAC_BACAM_RPMEN_8814B BIT(0) -/* 2 REG_LBDLY_8814B (LOOPBACK DELAY REGISTER) */ +/* 2 REG_TX_RX_8814B STATUS */ -#define BIT_SHIFT_LBDLY_8814B 0 -#define BIT_MASK_LBDLY_8814B 0x1f -#define BIT_LBDLY_8814B(x) (((x) & BIT_MASK_LBDLY_8814B) << BIT_SHIFT_LBDLY_8814B) -#define BIT_GET_LBDLY_8814B(x) (((x) >> BIT_SHIFT_LBDLY_8814B) & BIT_MASK_LBDLY_8814B) +#define BIT_SHIFT_RXPKT_TYPE_8814B 2 +#define BIT_MASK_RXPKT_TYPE_8814B 0x3f +#define BIT_RXPKT_TYPE_8814B(x) \ + (((x) & BIT_MASK_RXPKT_TYPE_8814B) << BIT_SHIFT_RXPKT_TYPE_8814B) +#define BITS_RXPKT_TYPE_8814B \ + (BIT_MASK_RXPKT_TYPE_8814B << BIT_SHIFT_RXPKT_TYPE_8814B) +#define BIT_CLEAR_RXPKT_TYPE_8814B(x) ((x) & (~BITS_RXPKT_TYPE_8814B)) +#define BIT_GET_RXPKT_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKT_TYPE_8814B) & BIT_MASK_RXPKT_TYPE_8814B) +#define BIT_SET_RXPKT_TYPE_8814B(x, v) \ + (BIT_CLEAR_RXPKT_TYPE_8814B(x) | BIT_RXPKT_TYPE_8814B(v)) + +#define BIT_TXACT_IND_8814B BIT(1) +#define BIT_RXACT_IND_8814B BIT(0) +/* 2 REG_WMAC_BITMAP_CTL_8814B */ +#define BIT_BITMAP_VO_8814B BIT(7) +#define BIT_BITMAP_VI_8814B BIT(6) +#define BIT_BITMAP_BE_8814B BIT(5) +#define BIT_BITMAP_BK_8814B BIT(4) + +#define BIT_SHIFT_BITMAP_CONDITION_8814B 2 +#define BIT_MASK_BITMAP_CONDITION_8814B 0x3 +#define BIT_BITMAP_CONDITION_8814B(x) \ + (((x) & BIT_MASK_BITMAP_CONDITION_8814B) \ + << BIT_SHIFT_BITMAP_CONDITION_8814B) +#define BITS_BITMAP_CONDITION_8814B \ + (BIT_MASK_BITMAP_CONDITION_8814B << BIT_SHIFT_BITMAP_CONDITION_8814B) +#define BIT_CLEAR_BITMAP_CONDITION_8814B(x) \ + ((x) & (~BITS_BITMAP_CONDITION_8814B)) +#define BIT_GET_BITMAP_CONDITION_8814B(x) \ + (((x) >> BIT_SHIFT_BITMAP_CONDITION_8814B) & \ + BIT_MASK_BITMAP_CONDITION_8814B) +#define BIT_SET_BITMAP_CONDITION_8814B(x, v) \ + (BIT_CLEAR_BITMAP_CONDITION_8814B(x) | BIT_BITMAP_CONDITION_8814B(v)) +#define BIT_BITMAP_SSNBK_COUNTER_CLR_8814B BIT(1) +#define BIT_BITMAP_FORCE_8814B BIT(0) /* 2 REG_RXERR_RPT_8814B (RX ERROR REPORT REGISTER) */ #define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B 28 #define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B 0xf -#define BIT_RXERR_RPT_SEL_V1_3_0_8814B(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) -#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8814B(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B) - +#define BIT_RXERR_RPT_SEL_V1_3_0_8814B(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B) \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) +#define BITS_RXERR_RPT_SEL_V1_3_0_8814B \ + (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8814B(x) \ + ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8814B)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8814B(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) & \ + BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8814B(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8814B(x) | \ + BIT_RXERR_RPT_SEL_V1_3_0_8814B(v)) #define BIT_RXERR_RPT_RST_8814B BIT(27) #define BIT_RXERR_RPT_SEL_V1_4_8814B BIT(26) @@ -9026,64 +21209,40 @@ #define BIT_SHIFT_UD_SUB_TYPE_8814B 18 #define BIT_MASK_UD_SUB_TYPE_8814B 0xf -#define BIT_UD_SUB_TYPE_8814B(x) (((x) & BIT_MASK_UD_SUB_TYPE_8814B) << BIT_SHIFT_UD_SUB_TYPE_8814B) -#define BIT_GET_UD_SUB_TYPE_8814B(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8814B) & BIT_MASK_UD_SUB_TYPE_8814B) - - +#define BIT_UD_SUB_TYPE_8814B(x) \ + (((x) & BIT_MASK_UD_SUB_TYPE_8814B) << BIT_SHIFT_UD_SUB_TYPE_8814B) +#define BITS_UD_SUB_TYPE_8814B \ + (BIT_MASK_UD_SUB_TYPE_8814B << BIT_SHIFT_UD_SUB_TYPE_8814B) +#define BIT_CLEAR_UD_SUB_TYPE_8814B(x) ((x) & (~BITS_UD_SUB_TYPE_8814B)) +#define BIT_GET_UD_SUB_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_UD_SUB_TYPE_8814B) & BIT_MASK_UD_SUB_TYPE_8814B) +#define BIT_SET_UD_SUB_TYPE_8814B(x, v) \ + (BIT_CLEAR_UD_SUB_TYPE_8814B(x) | BIT_UD_SUB_TYPE_8814B(v)) #define BIT_SHIFT_UD_TYPE_8814B 16 #define BIT_MASK_UD_TYPE_8814B 0x3 -#define BIT_UD_TYPE_8814B(x) (((x) & BIT_MASK_UD_TYPE_8814B) << BIT_SHIFT_UD_TYPE_8814B) -#define BIT_GET_UD_TYPE_8814B(x) (((x) >> BIT_SHIFT_UD_TYPE_8814B) & BIT_MASK_UD_TYPE_8814B) - - +#define BIT_UD_TYPE_8814B(x) \ + (((x) & BIT_MASK_UD_TYPE_8814B) << BIT_SHIFT_UD_TYPE_8814B) +#define BITS_UD_TYPE_8814B (BIT_MASK_UD_TYPE_8814B << BIT_SHIFT_UD_TYPE_8814B) +#define BIT_CLEAR_UD_TYPE_8814B(x) ((x) & (~BITS_UD_TYPE_8814B)) +#define BIT_GET_UD_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_UD_TYPE_8814B) & BIT_MASK_UD_TYPE_8814B) +#define BIT_SET_UD_TYPE_8814B(x, v) \ + (BIT_CLEAR_UD_TYPE_8814B(x) | BIT_UD_TYPE_8814B(v)) #define BIT_SHIFT_RPT_COUNTER_8814B 0 #define BIT_MASK_RPT_COUNTER_8814B 0xffff -#define BIT_RPT_COUNTER_8814B(x) (((x) & BIT_MASK_RPT_COUNTER_8814B) << BIT_SHIFT_RPT_COUNTER_8814B) -#define BIT_GET_RPT_COUNTER_8814B(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8814B) & BIT_MASK_RPT_COUNTER_8814B) - - - -/* 2 REG_WMAC_TRXPTCL_CTL_8814B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ - -#define BIT_SHIFT_ACKBA_TYPSEL_8814B (60 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBA_TYPSEL_8814B 0xf -#define BIT_ACKBA_TYPSEL_8814B(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8814B) << BIT_SHIFT_ACKBA_TYPSEL_8814B) -#define BIT_GET_ACKBA_TYPSEL_8814B(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8814B) & BIT_MASK_ACKBA_TYPSEL_8814B) - - - -#define BIT_SHIFT_ACKBA_ACKPCHK_8814B (56 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBA_ACKPCHK_8814B 0xf -#define BIT_ACKBA_ACKPCHK_8814B(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8814B) << BIT_SHIFT_ACKBA_ACKPCHK_8814B) -#define BIT_GET_ACKBA_ACKPCHK_8814B(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8814B) & BIT_MASK_ACKBA_ACKPCHK_8814B) - - - -#define BIT_SHIFT_ACKBAR_TYPESEL_8814B (48 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBAR_TYPESEL_8814B 0xff -#define BIT_ACKBAR_TYPESEL_8814B(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8814B) << BIT_SHIFT_ACKBAR_TYPESEL_8814B) -#define BIT_GET_ACKBAR_TYPESEL_8814B(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8814B) & BIT_MASK_ACKBAR_TYPESEL_8814B) - - - -#define BIT_SHIFT_ACKBAR_ACKPCHK_8814B (44 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBAR_ACKPCHK_8814B 0xf -#define BIT_ACKBAR_ACKPCHK_8814B(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8814B) << BIT_SHIFT_ACKBAR_ACKPCHK_8814B) -#define BIT_GET_ACKBAR_ACKPCHK_8814B(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8814B) & BIT_MASK_ACKBAR_ACKPCHK_8814B) - - -#define BIT_RXBA_IGNOREA2_8814B BIT(42) -#define BIT_EN_SAVE_ALL_TXOPADDR_8814B BIT(41) -#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8814B BIT(40) -#define BIT_DIS_TXBA_AMPDUFCSERR_8814B BIT(39) -#define BIT_DIS_TXBA_RXBARINFULL_8814B BIT(38) -#define BIT_DIS_TXCFE_INFULL_8814B BIT(37) -#define BIT_DIS_TXCTS_INFULL_8814B BIT(36) -#define BIT_EN_TXACKBA_IN_TX_RDG_8814B BIT(35) -#define BIT_EN_TXACKBA_IN_TXOP_8814B BIT(34) -#define BIT_EN_TXCTS_IN_RXNAV_8814B BIT(33) +#define BIT_RPT_COUNTER_8814B(x) \ + (((x) & BIT_MASK_RPT_COUNTER_8814B) << BIT_SHIFT_RPT_COUNTER_8814B) +#define BITS_RPT_COUNTER_8814B \ + (BIT_MASK_RPT_COUNTER_8814B << BIT_SHIFT_RPT_COUNTER_8814B) +#define BIT_CLEAR_RPT_COUNTER_8814B(x) ((x) & (~BITS_RPT_COUNTER_8814B)) +#define BIT_GET_RPT_COUNTER_8814B(x) \ + (((x) >> BIT_SHIFT_RPT_COUNTER_8814B) & BIT_MASK_RPT_COUNTER_8814B) +#define BIT_SET_RPT_COUNTER_8814B(x, v) \ + (BIT_CLEAR_RPT_COUNTER_8814B(x) | BIT_RPT_COUNTER_8814B(v)) + +/* 2 REG_WMAC_TRXPTCL_CTL_8814B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ #define BIT_EN_TXCTS_INTXOP_8814B BIT(32) #define BIT_BLK_EDCA_BBSLP_8814B BIT(31) #define BIT_BLK_EDCA_BBSBY_8814B BIT(30) @@ -9096,9 +21255,15 @@ #define BIT_SHIFT_RESP_CHNBUSY_8814B 20 #define BIT_MASK_RESP_CHNBUSY_8814B 0x3 -#define BIT_RESP_CHNBUSY_8814B(x) (((x) & BIT_MASK_RESP_CHNBUSY_8814B) << BIT_SHIFT_RESP_CHNBUSY_8814B) -#define BIT_GET_RESP_CHNBUSY_8814B(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8814B) & BIT_MASK_RESP_CHNBUSY_8814B) - +#define BIT_RESP_CHNBUSY_8814B(x) \ + (((x) & BIT_MASK_RESP_CHNBUSY_8814B) << BIT_SHIFT_RESP_CHNBUSY_8814B) +#define BITS_RESP_CHNBUSY_8814B \ + (BIT_MASK_RESP_CHNBUSY_8814B << BIT_SHIFT_RESP_CHNBUSY_8814B) +#define BIT_CLEAR_RESP_CHNBUSY_8814B(x) ((x) & (~BITS_RESP_CHNBUSY_8814B)) +#define BIT_GET_RESP_CHNBUSY_8814B(x) \ + (((x) >> BIT_SHIFT_RESP_CHNBUSY_8814B) & BIT_MASK_RESP_CHNBUSY_8814B) +#define BIT_SET_RESP_CHNBUSY_8814B(x, v) \ + (BIT_CLEAR_RESP_CHNBUSY_8814B(x) | BIT_RESP_CHNBUSY_8814B(v)) #define BIT_RESP_DCTS_EN_8814B BIT(19) #define BIT_RESP_DCFE_EN_8814B BIT(18) @@ -9110,64 +21275,176 @@ #define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B 10 #define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B 0x7 -#define BIT_R_WMAC_SECOND_CCA_TIMER_8814B(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) -#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B) - - +#define BIT_R_WMAC_SECOND_CCA_TIMER_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B) \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) +#define BITS_R_WMAC_SECOND_CCA_TIMER_8814B \ + (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8814B(x) \ + ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8814B)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) & \ + BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8814B(x) | \ + BIT_R_WMAC_SECOND_CCA_TIMER_8814B(v)) #define BIT_SHIFT_RFMOD_8814B 7 #define BIT_MASK_RFMOD_8814B 0x3 -#define BIT_RFMOD_8814B(x) (((x) & BIT_MASK_RFMOD_8814B) << BIT_SHIFT_RFMOD_8814B) -#define BIT_GET_RFMOD_8814B(x) (((x) >> BIT_SHIFT_RFMOD_8814B) & BIT_MASK_RFMOD_8814B) - - +#define BIT_RFMOD_8814B(x) \ + (((x) & BIT_MASK_RFMOD_8814B) << BIT_SHIFT_RFMOD_8814B) +#define BITS_RFMOD_8814B (BIT_MASK_RFMOD_8814B << BIT_SHIFT_RFMOD_8814B) +#define BIT_CLEAR_RFMOD_8814B(x) ((x) & (~BITS_RFMOD_8814B)) +#define BIT_GET_RFMOD_8814B(x) \ + (((x) >> BIT_SHIFT_RFMOD_8814B) & BIT_MASK_RFMOD_8814B) +#define BIT_SET_RFMOD_8814B(x, v) \ + (BIT_CLEAR_RFMOD_8814B(x) | BIT_RFMOD_8814B(v)) #define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B 5 #define BIT_MASK_RESP_CTS_DYNBW_SEL_8814B 0x3 -#define BIT_RESP_CTS_DYNBW_SEL_8814B(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8814B) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) -#define BIT_GET_RESP_CTS_DYNBW_SEL_8814B(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) & BIT_MASK_RESP_CTS_DYNBW_SEL_8814B) - +#define BIT_RESP_CTS_DYNBW_SEL_8814B(x) \ + (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8814B) \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) +#define BITS_RESP_CTS_DYNBW_SEL_8814B \ + (BIT_MASK_RESP_CTS_DYNBW_SEL_8814B \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8814B(x) \ + ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8814B)) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) & \ + BIT_MASK_RESP_CTS_DYNBW_SEL_8814B) +#define BIT_SET_RESP_CTS_DYNBW_SEL_8814B(x, v) \ + (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8814B(x) | \ + BIT_RESP_CTS_DYNBW_SEL_8814B(v)) #define BIT_DLY_TX_WAIT_RXANTSEL_8814B BIT(4) #define BIT_TXRESP_BY_RXANTSEL_8814B BIT(3) #define BIT_SHIFT_ORIG_DCTS_CHK_8814B 0 #define BIT_MASK_ORIG_DCTS_CHK_8814B 0x3 -#define BIT_ORIG_DCTS_CHK_8814B(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8814B) << BIT_SHIFT_ORIG_DCTS_CHK_8814B) -#define BIT_GET_ORIG_DCTS_CHK_8814B(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8814B) & BIT_MASK_ORIG_DCTS_CHK_8814B) - - +#define BIT_ORIG_DCTS_CHK_8814B(x) \ + (((x) & BIT_MASK_ORIG_DCTS_CHK_8814B) << BIT_SHIFT_ORIG_DCTS_CHK_8814B) +#define BITS_ORIG_DCTS_CHK_8814B \ + (BIT_MASK_ORIG_DCTS_CHK_8814B << BIT_SHIFT_ORIG_DCTS_CHK_8814B) +#define BIT_CLEAR_ORIG_DCTS_CHK_8814B(x) ((x) & (~BITS_ORIG_DCTS_CHK_8814B)) +#define BIT_GET_ORIG_DCTS_CHK_8814B(x) \ + (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8814B) & BIT_MASK_ORIG_DCTS_CHK_8814B) +#define BIT_SET_ORIG_DCTS_CHK_8814B(x, v) \ + (BIT_CLEAR_ORIG_DCTS_CHK_8814B(x) | BIT_ORIG_DCTS_CHK_8814B(v)) + +/* 2 REG_WMAC_TRXPTCL_CTL_H_8814B */ + +#define BIT_SHIFT_ACKBA_TYPSEL_8814B 28 +#define BIT_MASK_ACKBA_TYPSEL_8814B 0xf +#define BIT_ACKBA_TYPSEL_8814B(x) \ + (((x) & BIT_MASK_ACKBA_TYPSEL_8814B) << BIT_SHIFT_ACKBA_TYPSEL_8814B) +#define BITS_ACKBA_TYPSEL_8814B \ + (BIT_MASK_ACKBA_TYPSEL_8814B << BIT_SHIFT_ACKBA_TYPSEL_8814B) +#define BIT_CLEAR_ACKBA_TYPSEL_8814B(x) ((x) & (~BITS_ACKBA_TYPSEL_8814B)) +#define BIT_GET_ACKBA_TYPSEL_8814B(x) \ + (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8814B) & BIT_MASK_ACKBA_TYPSEL_8814B) +#define BIT_SET_ACKBA_TYPSEL_8814B(x, v) \ + (BIT_CLEAR_ACKBA_TYPSEL_8814B(x) | BIT_ACKBA_TYPSEL_8814B(v)) + +#define BIT_SHIFT_ACKBA_ACKPCHK_8814B 24 +#define BIT_MASK_ACKBA_ACKPCHK_8814B 0xf +#define BIT_ACKBA_ACKPCHK_8814B(x) \ + (((x) & BIT_MASK_ACKBA_ACKPCHK_8814B) << BIT_SHIFT_ACKBA_ACKPCHK_8814B) +#define BITS_ACKBA_ACKPCHK_8814B \ + (BIT_MASK_ACKBA_ACKPCHK_8814B << BIT_SHIFT_ACKBA_ACKPCHK_8814B) +#define BIT_CLEAR_ACKBA_ACKPCHK_8814B(x) ((x) & (~BITS_ACKBA_ACKPCHK_8814B)) +#define BIT_GET_ACKBA_ACKPCHK_8814B(x) \ + (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8814B) & BIT_MASK_ACKBA_ACKPCHK_8814B) +#define BIT_SET_ACKBA_ACKPCHK_8814B(x, v) \ + (BIT_CLEAR_ACKBA_ACKPCHK_8814B(x) | BIT_ACKBA_ACKPCHK_8814B(v)) + +#define BIT_SHIFT_ACKBAR_TYPESEL_8814B 16 +#define BIT_MASK_ACKBAR_TYPESEL_8814B 0xff +#define BIT_ACKBAR_TYPESEL_8814B(x) \ + (((x) & BIT_MASK_ACKBAR_TYPESEL_8814B) \ + << BIT_SHIFT_ACKBAR_TYPESEL_8814B) +#define BITS_ACKBAR_TYPESEL_8814B \ + (BIT_MASK_ACKBAR_TYPESEL_8814B << BIT_SHIFT_ACKBAR_TYPESEL_8814B) +#define BIT_CLEAR_ACKBAR_TYPESEL_8814B(x) ((x) & (~BITS_ACKBAR_TYPESEL_8814B)) +#define BIT_GET_ACKBAR_TYPESEL_8814B(x) \ + (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8814B) & \ + BIT_MASK_ACKBAR_TYPESEL_8814B) +#define BIT_SET_ACKBAR_TYPESEL_8814B(x, v) \ + (BIT_CLEAR_ACKBAR_TYPESEL_8814B(x) | BIT_ACKBAR_TYPESEL_8814B(v)) + +#define BIT_SHIFT_ACKBAR_ACKPCHK_8814B 12 +#define BIT_MASK_ACKBAR_ACKPCHK_8814B 0xf +#define BIT_ACKBAR_ACKPCHK_8814B(x) \ + (((x) & BIT_MASK_ACKBAR_ACKPCHK_8814B) \ + << BIT_SHIFT_ACKBAR_ACKPCHK_8814B) +#define BITS_ACKBAR_ACKPCHK_8814B \ + (BIT_MASK_ACKBAR_ACKPCHK_8814B << BIT_SHIFT_ACKBAR_ACKPCHK_8814B) +#define BIT_CLEAR_ACKBAR_ACKPCHK_8814B(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8814B)) +#define BIT_GET_ACKBAR_ACKPCHK_8814B(x) \ + (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8814B) & \ + BIT_MASK_ACKBAR_ACKPCHK_8814B) +#define BIT_SET_ACKBAR_ACKPCHK_8814B(x, v) \ + (BIT_CLEAR_ACKBAR_ACKPCHK_8814B(x) | BIT_ACKBAR_ACKPCHK_8814B(v)) + +#define BIT_RXBA_IGNOREA2_V1_8814B BIT(10) +#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8814B BIT(9) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8814B BIT(8) +#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8814B BIT(7) +#define BIT_DIS_TXBA_RXBARINFULL_V1_8814B BIT(6) +#define BIT_DIS_TXCFE_INFULL_V1_8814B BIT(5) +#define BIT_DIS_TXCTS_INFULL_V1_8814B BIT(4) +#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8814B BIT(3) +#define BIT_EN_TXACKBA_IN_TXOP_V1_8814B BIT(2) +#define BIT_EN_TXCTS_IN_RXNAV_V1_8814B BIT(1) +#define BIT_EN_TXCTS_INTXOP_V1_8814B BIT(0) /* 2 REG_CAMCMD_8814B (CAM COMMAND REGISTER) */ #define BIT_SECCAM_POLLING_8814B BIT(31) #define BIT_SECCAM_CLR_8814B BIT(30) -#define BIT_MFBCAM_CLR_8814B BIT(29) #define BIT_SECCAM_WE_8814B BIT(16) #define BIT_SHIFT_SECCAM_ADDR_V2_8814B 0 #define BIT_MASK_SECCAM_ADDR_V2_8814B 0x3ff -#define BIT_SECCAM_ADDR_V2_8814B(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8814B) << BIT_SHIFT_SECCAM_ADDR_V2_8814B) -#define BIT_GET_SECCAM_ADDR_V2_8814B(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8814B) & BIT_MASK_SECCAM_ADDR_V2_8814B) - - +#define BIT_SECCAM_ADDR_V2_8814B(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V2_8814B) \ + << BIT_SHIFT_SECCAM_ADDR_V2_8814B) +#define BITS_SECCAM_ADDR_V2_8814B \ + (BIT_MASK_SECCAM_ADDR_V2_8814B << BIT_SHIFT_SECCAM_ADDR_V2_8814B) +#define BIT_CLEAR_SECCAM_ADDR_V2_8814B(x) ((x) & (~BITS_SECCAM_ADDR_V2_8814B)) +#define BIT_GET_SECCAM_ADDR_V2_8814B(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8814B) & \ + BIT_MASK_SECCAM_ADDR_V2_8814B) +#define BIT_SET_SECCAM_ADDR_V2_8814B(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V2_8814B(x) | BIT_SECCAM_ADDR_V2_8814B(v)) /* 2 REG_CAMWRITE_8814B (CAM WRITE REGISTER) */ #define BIT_SHIFT_CAMW_DATA_8814B 0 #define BIT_MASK_CAMW_DATA_8814B 0xffffffffL -#define BIT_CAMW_DATA_8814B(x) (((x) & BIT_MASK_CAMW_DATA_8814B) << BIT_SHIFT_CAMW_DATA_8814B) -#define BIT_GET_CAMW_DATA_8814B(x) (((x) >> BIT_SHIFT_CAMW_DATA_8814B) & BIT_MASK_CAMW_DATA_8814B) - - +#define BIT_CAMW_DATA_8814B(x) \ + (((x) & BIT_MASK_CAMW_DATA_8814B) << BIT_SHIFT_CAMW_DATA_8814B) +#define BITS_CAMW_DATA_8814B \ + (BIT_MASK_CAMW_DATA_8814B << BIT_SHIFT_CAMW_DATA_8814B) +#define BIT_CLEAR_CAMW_DATA_8814B(x) ((x) & (~BITS_CAMW_DATA_8814B)) +#define BIT_GET_CAMW_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_CAMW_DATA_8814B) & BIT_MASK_CAMW_DATA_8814B) +#define BIT_SET_CAMW_DATA_8814B(x, v) \ + (BIT_CLEAR_CAMW_DATA_8814B(x) | BIT_CAMW_DATA_8814B(v)) /* 2 REG_CAMREAD_8814B (CAM READ REGISTER) */ #define BIT_SHIFT_CAMR_DATA_8814B 0 #define BIT_MASK_CAMR_DATA_8814B 0xffffffffL -#define BIT_CAMR_DATA_8814B(x) (((x) & BIT_MASK_CAMR_DATA_8814B) << BIT_SHIFT_CAMR_DATA_8814B) -#define BIT_GET_CAMR_DATA_8814B(x) (((x) >> BIT_SHIFT_CAMR_DATA_8814B) & BIT_MASK_CAMR_DATA_8814B) - - +#define BIT_CAMR_DATA_8814B(x) \ + (((x) & BIT_MASK_CAMR_DATA_8814B) << BIT_SHIFT_CAMR_DATA_8814B) +#define BITS_CAMR_DATA_8814B \ + (BIT_MASK_CAMR_DATA_8814B << BIT_SHIFT_CAMR_DATA_8814B) +#define BIT_CLEAR_CAMR_DATA_8814B(x) ((x) & (~BITS_CAMR_DATA_8814B)) +#define BIT_GET_CAMR_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_CAMR_DATA_8814B) & BIT_MASK_CAMR_DATA_8814B) +#define BIT_SET_CAMR_DATA_8814B(x, v) \ + (BIT_CLEAR_CAMR_DATA_8814B(x) | BIT_CAMR_DATA_8814B(v)) /* 2 REG_CAMDBG_8814B (CAM DEBUG REGISTER) */ #define BIT_SECCAM_INFO_8814B BIT(31) @@ -9175,43 +21452,53 @@ #define BIT_SHIFT_CAMDBG_SEC_TYPE_8814B 12 #define BIT_MASK_CAMDBG_SEC_TYPE_8814B 0x7 -#define BIT_CAMDBG_SEC_TYPE_8814B(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8814B) << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) -#define BIT_GET_CAMDBG_SEC_TYPE_8814B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) & BIT_MASK_CAMDBG_SEC_TYPE_8814B) - +#define BIT_CAMDBG_SEC_TYPE_8814B(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8814B) \ + << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) +#define BITS_CAMDBG_SEC_TYPE_8814B \ + (BIT_MASK_CAMDBG_SEC_TYPE_8814B << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) +#define BIT_CLEAR_CAMDBG_SEC_TYPE_8814B(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8814B)) +#define BIT_GET_CAMDBG_SEC_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) & \ + BIT_MASK_CAMDBG_SEC_TYPE_8814B) +#define BIT_SET_CAMDBG_SEC_TYPE_8814B(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE_8814B(x) | BIT_CAMDBG_SEC_TYPE_8814B(v)) #define BIT_CAMDBG_EXT_SECTYPE_8814B BIT(11) #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B 5 #define BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B 0x1f -#define BIT_CAMDBG_MIC_KEY_IDX_8814B(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) -#define BIT_GET_CAMDBG_MIC_KEY_IDX_8814B(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B) - - +#define BIT_CAMDBG_MIC_KEY_IDX_8814B(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B) \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) +#define BITS_CAMDBG_MIC_KEY_IDX_8814B \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8814B(x) \ + ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8814B)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) & \ + BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_8814B(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8814B(x) | \ + BIT_CAMDBG_MIC_KEY_IDX_8814B(v)) #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B 0 #define BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B 0x1f -#define BIT_CAMDBG_SEC_KEY_IDX_8814B(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) -#define BIT_GET_CAMDBG_SEC_KEY_IDX_8814B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B) - - - -/* 2 REG_RXFILTER_ACTION_1_8814B */ - -#define BIT_SHIFT_RXFILTER_ACTION_1_8814B 0 -#define BIT_MASK_RXFILTER_ACTION_1_8814B 0xff -#define BIT_RXFILTER_ACTION_1_8814B(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8814B) << BIT_SHIFT_RXFILTER_ACTION_1_8814B) -#define BIT_GET_RXFILTER_ACTION_1_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8814B) & BIT_MASK_RXFILTER_ACTION_1_8814B) - - - -/* 2 REG_RXFILTER_CATEGORY_1_8814B */ - -#define BIT_SHIFT_RXFILTER_CATEGORY_1_8814B 0 -#define BIT_MASK_RXFILTER_CATEGORY_1_8814B 0xff -#define BIT_RXFILTER_CATEGORY_1_8814B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8814B) << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) -#define BIT_GET_RXFILTER_CATEGORY_1_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) & BIT_MASK_RXFILTER_CATEGORY_1_8814B) - - +#define BIT_CAMDBG_SEC_KEY_IDX_8814B(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B) \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) +#define BITS_CAMDBG_SEC_KEY_IDX_8814B \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8814B(x) \ + ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8814B)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) & \ + BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_8814B(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8814B(x) | \ + BIT_CAMDBG_SEC_KEY_IDX_8814B(v)) /* 2 REG_SECCFG_8814B (SECURITY CONFIGURATION REGISTER) */ #define BIT_DIS_GCLK_WAPI_8814B BIT(15) @@ -9230,59 +21517,113 @@ #define BIT_RXUHUSEDK_8814B BIT(1) #define BIT_TXUHUSEDK_8814B BIT(0) -/* 2 REG_RXFILTER_ACTION_3_8814B */ - -#define BIT_SHIFT_RXFILTER_ACTION_3_8814B 0 -#define BIT_MASK_RXFILTER_ACTION_3_8814B 0xff -#define BIT_RXFILTER_ACTION_3_8814B(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8814B) << BIT_SHIFT_RXFILTER_ACTION_3_8814B) -#define BIT_GET_RXFILTER_ACTION_3_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8814B) & BIT_MASK_RXFILTER_ACTION_3_8814B) - +/* 2 REG_RXFILTER_CATEGORY_1_8814B */ +#define BIT_SHIFT_RXFILTER_CATEGORY_1_8814B 0 +#define BIT_MASK_RXFILTER_CATEGORY_1_8814B 0xff +#define BIT_RXFILTER_CATEGORY_1_8814B(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8814B) \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) +#define BITS_RXFILTER_CATEGORY_1_8814B \ + (BIT_MASK_RXFILTER_CATEGORY_1_8814B \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) +#define BIT_CLEAR_RXFILTER_CATEGORY_1_8814B(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_1_8814B)) +#define BIT_GET_RXFILTER_CATEGORY_1_8814B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) & \ + BIT_MASK_RXFILTER_CATEGORY_1_8814B) +#define BIT_SET_RXFILTER_CATEGORY_1_8814B(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_1_8814B(x) | \ + BIT_RXFILTER_CATEGORY_1_8814B(v)) -/* 2 REG_RXFILTER_CATEGORY_3_8814B */ +/* 2 REG_RXFILTER_ACTION_1_8814B */ -#define BIT_SHIFT_RXFILTER_CATEGORY_3_8814B 0 -#define BIT_MASK_RXFILTER_CATEGORY_3_8814B 0xff -#define BIT_RXFILTER_CATEGORY_3_8814B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8814B) << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) -#define BIT_GET_RXFILTER_CATEGORY_3_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) & BIT_MASK_RXFILTER_CATEGORY_3_8814B) +#define BIT_SHIFT_RXFILTER_ACTION_1_8814B 0 +#define BIT_MASK_RXFILTER_ACTION_1_8814B 0xff +#define BIT_RXFILTER_ACTION_1_8814B(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_1_8814B) \ + << BIT_SHIFT_RXFILTER_ACTION_1_8814B) +#define BITS_RXFILTER_ACTION_1_8814B \ + (BIT_MASK_RXFILTER_ACTION_1_8814B << BIT_SHIFT_RXFILTER_ACTION_1_8814B) +#define BIT_CLEAR_RXFILTER_ACTION_1_8814B(x) \ + ((x) & (~BITS_RXFILTER_ACTION_1_8814B)) +#define BIT_GET_RXFILTER_ACTION_1_8814B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8814B) & \ + BIT_MASK_RXFILTER_ACTION_1_8814B) +#define BIT_SET_RXFILTER_ACTION_1_8814B(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_1_8814B(x) | BIT_RXFILTER_ACTION_1_8814B(v)) +/* 2 REG_RXFILTER_CATEGORY_2_8814B */ +#define BIT_SHIFT_RXFILTER_CATEGORY_2_8814B 0 +#define BIT_MASK_RXFILTER_CATEGORY_2_8814B 0xff +#define BIT_RXFILTER_CATEGORY_2_8814B(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8814B) \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) +#define BITS_RXFILTER_CATEGORY_2_8814B \ + (BIT_MASK_RXFILTER_CATEGORY_2_8814B \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) +#define BIT_CLEAR_RXFILTER_CATEGORY_2_8814B(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_2_8814B)) +#define BIT_GET_RXFILTER_CATEGORY_2_8814B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) & \ + BIT_MASK_RXFILTER_CATEGORY_2_8814B) +#define BIT_SET_RXFILTER_CATEGORY_2_8814B(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_2_8814B(x) | \ + BIT_RXFILTER_CATEGORY_2_8814B(v)) /* 2 REG_RXFILTER_ACTION_2_8814B */ #define BIT_SHIFT_RXFILTER_ACTION_2_8814B 0 #define BIT_MASK_RXFILTER_ACTION_2_8814B 0xff -#define BIT_RXFILTER_ACTION_2_8814B(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8814B) << BIT_SHIFT_RXFILTER_ACTION_2_8814B) -#define BIT_GET_RXFILTER_ACTION_2_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8814B) & BIT_MASK_RXFILTER_ACTION_2_8814B) - - +#define BIT_RXFILTER_ACTION_2_8814B(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_2_8814B) \ + << BIT_SHIFT_RXFILTER_ACTION_2_8814B) +#define BITS_RXFILTER_ACTION_2_8814B \ + (BIT_MASK_RXFILTER_ACTION_2_8814B << BIT_SHIFT_RXFILTER_ACTION_2_8814B) +#define BIT_CLEAR_RXFILTER_ACTION_2_8814B(x) \ + ((x) & (~BITS_RXFILTER_ACTION_2_8814B)) +#define BIT_GET_RXFILTER_ACTION_2_8814B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8814B) & \ + BIT_MASK_RXFILTER_ACTION_2_8814B) +#define BIT_SET_RXFILTER_ACTION_2_8814B(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_2_8814B(x) | BIT_RXFILTER_ACTION_2_8814B(v)) -/* 2 REG_RXFILTER_CATEGORY_2_8814B */ - -#define BIT_SHIFT_RXFILTER_CATEGORY_2_8814B 0 -#define BIT_MASK_RXFILTER_CATEGORY_2_8814B 0xff -#define BIT_RXFILTER_CATEGORY_2_8814B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8814B) << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) -#define BIT_GET_RXFILTER_CATEGORY_2_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) & BIT_MASK_RXFILTER_CATEGORY_2_8814B) +/* 2 REG_RXFILTER_CATEGORY_3_8814B */ +#define BIT_SHIFT_RXFILTER_CATEGORY_3_8814B 0 +#define BIT_MASK_RXFILTER_CATEGORY_3_8814B 0xff +#define BIT_RXFILTER_CATEGORY_3_8814B(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8814B) \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) +#define BITS_RXFILTER_CATEGORY_3_8814B \ + (BIT_MASK_RXFILTER_CATEGORY_3_8814B \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) +#define BIT_CLEAR_RXFILTER_CATEGORY_3_8814B(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_3_8814B)) +#define BIT_GET_RXFILTER_CATEGORY_3_8814B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) & \ + BIT_MASK_RXFILTER_CATEGORY_3_8814B) +#define BIT_SET_RXFILTER_CATEGORY_3_8814B(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_3_8814B(x) | \ + BIT_RXFILTER_CATEGORY_3_8814B(v)) +/* 2 REG_RXFILTER_ACTION_3_8814B */ -/* 2 REG_RXFLTMAP4_8814B (RX FILTER MAP GROUP 4) */ -#define BIT_CTRLFLT15EN_FW_8814B BIT(15) -#define BIT_CTRLFLT14EN_FW_8814B BIT(14) -#define BIT_CTRLFLT13EN_FW_8814B BIT(13) -#define BIT_CTRLFLT12EN_FW_8814B BIT(12) -#define BIT_CTRLFLT11EN_FW_8814B BIT(11) -#define BIT_CTRLFLT10EN_FW_8814B BIT(10) -#define BIT_CTRLFLT9EN_FW_8814B BIT(9) -#define BIT_CTRLFLT8EN_FW_8814B BIT(8) -#define BIT_CTRLFLT7EN_FW_8814B BIT(7) -#define BIT_CTRLFLT6EN_FW_8814B BIT(6) -#define BIT_CTRLFLT5EN_FW_8814B BIT(5) -#define BIT_CTRLFLT4EN_FW_8814B BIT(4) -#define BIT_CTRLFLT3EN_FW_8814B BIT(3) -#define BIT_CTRLFLT2EN_FW_8814B BIT(2) -#define BIT_CTRLFLT1EN_FW_8814B BIT(1) -#define BIT_CTRLFLT0EN_FW_8814B BIT(0) +#define BIT_SHIFT_RXFILTER_ACTION_3_8814B 0 +#define BIT_MASK_RXFILTER_ACTION_3_8814B 0xff +#define BIT_RXFILTER_ACTION_3_8814B(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_3_8814B) \ + << BIT_SHIFT_RXFILTER_ACTION_3_8814B) +#define BITS_RXFILTER_ACTION_3_8814B \ + (BIT_MASK_RXFILTER_ACTION_3_8814B << BIT_SHIFT_RXFILTER_ACTION_3_8814B) +#define BIT_CLEAR_RXFILTER_ACTION_3_8814B(x) \ + ((x) & (~BITS_RXFILTER_ACTION_3_8814B)) +#define BIT_GET_RXFILTER_ACTION_3_8814B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8814B) & \ + BIT_MASK_RXFILTER_ACTION_3_8814B) +#define BIT_SET_RXFILTER_ACTION_3_8814B(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_3_8814B(x) | BIT_RXFILTER_ACTION_3_8814B(v)) /* 2 REG_RXFLTMAP3_8814B (RX FILTER MAP GROUP 3) */ #define BIT_MGTFLT15EN_FW_8814B BIT(15) @@ -9302,25 +21643,25 @@ #define BIT_MGTFLT1EN_FW_8814B BIT(1) #define BIT_MGTFLT0EN_FW_8814B BIT(0) -/* 2 REG_RXFLTMAP6_8814B (RX FILTER MAP GROUP 3) */ -#define BIT_ACTIONFLT15EN_FW_8814B BIT(15) -#define BIT_ACTIONFLT14EN_FW_8814B BIT(14) -#define BIT_ACTIONFLT13EN_FW_8814B BIT(13) -#define BIT_ACTIONFLT12EN_FW_8814B BIT(12) -#define BIT_ACTIONFLT11EN_FW_8814B BIT(11) -#define BIT_ACTIONFLT10EN_FW_8814B BIT(10) -#define BIT_ACTIONFLT9EN_FW_8814B BIT(9) -#define BIT_ACTIONFLT8EN_FW_8814B BIT(8) -#define BIT_ACTIONFLT7EN_FW_8814B BIT(7) -#define BIT_ACTIONFLT6EN_FW_8814B BIT(6) -#define BIT_ACTIONFLT5EN_FW_8814B BIT(5) -#define BIT_ACTIONFLT4EN_FW_8814B BIT(4) -#define BIT_ACTIONFLT3EN_FW_8814B BIT(3) -#define BIT_ACTIONFLT2EN_FW_8814B BIT(2) -#define BIT_ACTIONFLT1EN_FW_8814B BIT(1) -#define BIT_ACTIONFLT0EN_FW_8814B BIT(0) +/* 2 REG_RXFLTMAP4_8814B (RX FILTER MAP GROUP 4) */ +#define BIT_CTRLFLT15EN_FW_8814B BIT(15) +#define BIT_CTRLFLT14EN_FW_8814B BIT(14) +#define BIT_CTRLFLT13EN_FW_8814B BIT(13) +#define BIT_CTRLFLT12EN_FW_8814B BIT(12) +#define BIT_CTRLFLT11EN_FW_8814B BIT(11) +#define BIT_CTRLFLT10EN_FW_8814B BIT(10) +#define BIT_CTRLFLT9EN_FW_8814B BIT(9) +#define BIT_CTRLFLT8EN_FW_8814B BIT(8) +#define BIT_CTRLFLT7EN_FW_8814B BIT(7) +#define BIT_CTRLFLT6EN_FW_8814B BIT(6) +#define BIT_CTRLFLT5EN_FW_8814B BIT(5) +#define BIT_CTRLFLT4EN_FW_8814B BIT(4) +#define BIT_CTRLFLT3EN_FW_8814B BIT(3) +#define BIT_CTRLFLT2EN_FW_8814B BIT(2) +#define BIT_CTRLFLT1EN_FW_8814B BIT(1) +#define BIT_CTRLFLT0EN_FW_8814B BIT(0) -/* 2 REG_RXFLTMAP5_8814B (RX FILTER MAP GROUP 3) */ +/* 2 REG_RXFLTMAP5_8814B (RX FILTER MAP GROUP 5) */ #define BIT_DATAFLT15EN_FW_8814B BIT(15) #define BIT_DATAFLT14EN_FW_8814B BIT(14) #define BIT_DATAFLT13EN_FW_8814B BIT(13) @@ -9338,42 +21679,40 @@ #define BIT_DATAFLT1EN_FW_8814B BIT(1) #define BIT_DATAFLT0EN_FW_8814B BIT(0) -/* 2 REG_WMMPS_UAPSD_TID_8814B (WMM POWER SAVE UAPSD TID REGISTER) */ -#define BIT_WMMPS_UAPSD_TID7_8814B BIT(7) -#define BIT_WMMPS_UAPSD_TID6_8814B BIT(6) -#define BIT_WMMPS_UAPSD_TID5_8814B BIT(5) -#define BIT_WMMPS_UAPSD_TID4_8814B BIT(4) -#define BIT_WMMPS_UAPSD_TID3_8814B BIT(3) -#define BIT_WMMPS_UAPSD_TID2_8814B BIT(2) -#define BIT_WMMPS_UAPSD_TID1_8814B BIT(1) -#define BIT_WMMPS_UAPSD_TID0_8814B BIT(0) - -/* 2 REG_PS_RX_INFO_8814B (POWER SAVE RX INFORMATION REGISTER) */ - -#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B 5 -#define BIT_MASK_PORTSEL__PS_RX_INFO_8814B 0x7 -#define BIT_PORTSEL__PS_RX_INFO_8814B(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8814B) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) -#define BIT_GET_PORTSEL__PS_RX_INFO_8814B(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) & BIT_MASK_PORTSEL__PS_RX_INFO_8814B) - - -#define BIT_RXCTRLIN0_8814B BIT(4) -#define BIT_RXMGTIN0_8814B BIT(3) -#define BIT_RXDATAIN2_8814B BIT(2) -#define BIT_RXDATAIN1_8814B BIT(1) -#define BIT_RXDATAIN0_8814B BIT(0) - -/* 2 REG_NAN_RX_TSF_FILTER_8814B(NAN_RX_TSF_ADDRESS_FILTER) */ -#define BIT_CHK_TSF_TA_8814B BIT(2) -#define BIT_CHK_TSF_CBSSID_8814B BIT(1) -#define BIT_CHK_TSF_EN_8814B BIT(0) +/* 2 REG_RXFLTMAP6_8814B (RX FILTER MAP GROUP 6) */ +#define BIT_ACTIONFLT15EN_FW_8814B BIT(15) +#define BIT_ACTIONFLT14EN_FW_8814B BIT(14) +#define BIT_ACTIONFLT13EN_FW_8814B BIT(13) +#define BIT_ACTIONFLT12EN_FW_8814B BIT(12) +#define BIT_ACTIONFLT11EN_FW_8814B BIT(11) +#define BIT_ACTIONFLT10EN_FW_8814B BIT(10) +#define BIT_ACTIONFLT9EN_FW_8814B BIT(9) +#define BIT_ACTIONFLT8EN_FW_8814B BIT(8) +#define BIT_ACTIONFLT7EN_FW_8814B BIT(7) +#define BIT_ACTIONFLT6EN_FW_8814B BIT(6) +#define BIT_ACTIONFLT5EN_FW_8814B BIT(5) +#define BIT_ACTIONFLT4EN_FW_8814B BIT(4) +#define BIT_ACTIONFLT3EN_FW_8814B BIT(3) +#define BIT_ACTIONFLT2EN_FW_8814B BIT(2) +#define BIT_ACTIONFLT1EN_FW_8814B BIT(1) +#define BIT_ACTIONFLT0EN_FW_8814B BIT(0) /* 2 REG_WOW_CTRL_8814B (WAKE ON WLAN CONTROL REGISTER) */ #define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B 6 #define BIT_MASK_PSF_BSSIDSEL_B2B1_8814B 0x3 -#define BIT_PSF_BSSIDSEL_B2B1_8814B(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8814B) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) -#define BIT_GET_PSF_BSSIDSEL_B2B1_8814B(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) & BIT_MASK_PSF_BSSIDSEL_B2B1_8814B) - +#define BIT_PSF_BSSIDSEL_B2B1_8814B(x) \ + (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8814B) \ + << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) +#define BITS_PSF_BSSIDSEL_B2B1_8814B \ + (BIT_MASK_PSF_BSSIDSEL_B2B1_8814B << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8814B(x) \ + ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8814B)) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8814B(x) \ + (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) & \ + BIT_MASK_PSF_BSSIDSEL_B2B1_8814B) +#define BIT_SET_PSF_BSSIDSEL_B2B1_8814B(x, v) \ + (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8814B(x) | BIT_PSF_BSSIDSEL_B2B1_8814B(v)) #define BIT_WOWHCI_8814B BIT(5) #define BIT_PSF_BSSIDSEL_B0_8814B BIT(4) @@ -9382,22 +21721,47 @@ #define BIT_WOWEN_8814B BIT(1) #define BIT_FORCE_WAKEUP_8814B BIT(0) -/* 2 REG_LPNAV_CTRL_8814B (LOW POWER NAV CONTROL REGISTER) */ -#define BIT_LPNAV_EN_8814B BIT(31) - -#define BIT_SHIFT_LPNAV_EARLY_8814B 16 -#define BIT_MASK_LPNAV_EARLY_8814B 0x7fff -#define BIT_LPNAV_EARLY_8814B(x) (((x) & BIT_MASK_LPNAV_EARLY_8814B) << BIT_SHIFT_LPNAV_EARLY_8814B) -#define BIT_GET_LPNAV_EARLY_8814B(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8814B) & BIT_MASK_LPNAV_EARLY_8814B) +/* 2 REG_NAN_RX_TSF_FILTER_8814B(NAN_RX_TSF_ADDRESS_FILTER) */ +#define BIT_CHK_TSF_TA_8814B BIT(2) +#define BIT_CHK_TSF_CBSSID_8814B BIT(1) +#define BIT_CHK_TSF_EN_8814B BIT(0) +/* 2 REG_PS_RX_INFO_8814B (POWER SAVE RX INFORMATION REGISTER) */ +#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B 5 +#define BIT_MASK_PORTSEL__PS_RX_INFO_8814B 0x7 +#define BIT_PORTSEL__PS_RX_INFO_8814B(x) \ + (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8814B) \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) +#define BITS_PORTSEL__PS_RX_INFO_8814B \ + (BIT_MASK_PORTSEL__PS_RX_INFO_8814B \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8814B(x) \ + ((x) & (~BITS_PORTSEL__PS_RX_INFO_8814B)) +#define BIT_GET_PORTSEL__PS_RX_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) & \ + BIT_MASK_PORTSEL__PS_RX_INFO_8814B) +#define BIT_SET_PORTSEL__PS_RX_INFO_8814B(x, v) \ + (BIT_CLEAR_PORTSEL__PS_RX_INFO_8814B(x) | \ + BIT_PORTSEL__PS_RX_INFO_8814B(v)) -#define BIT_SHIFT_LPNAV_TH_8814B 0 -#define BIT_MASK_LPNAV_TH_8814B 0xffff -#define BIT_LPNAV_TH_8814B(x) (((x) & BIT_MASK_LPNAV_TH_8814B) << BIT_SHIFT_LPNAV_TH_8814B) -#define BIT_GET_LPNAV_TH_8814B(x) (((x) >> BIT_SHIFT_LPNAV_TH_8814B) & BIT_MASK_LPNAV_TH_8814B) +#define BIT_RXCTRLIN0_8814B BIT(4) +#define BIT_RXMGTIN0_8814B BIT(3) +#define BIT_RXDATAIN2_8814B BIT(2) +#define BIT_RXDATAIN1_8814B BIT(1) +#define BIT_RXDATAIN0_8814B BIT(0) +/* 2 REG_WMMPS_UAPSD_TID_8814B (WMM POWER SAVE UAPSD TID REGISTER) */ +#define BIT_WMMPS_UAPSD_TID7_8814B BIT(7) +#define BIT_WMMPS_UAPSD_TID6_8814B BIT(6) +#define BIT_WMMPS_UAPSD_TID5_8814B BIT(5) +#define BIT_WMMPS_UAPSD_TID4_8814B BIT(4) +#define BIT_WMMPS_UAPSD_TID3_8814B BIT(3) +#define BIT_WMMPS_UAPSD_TID2_8814B BIT(2) +#define BIT_WMMPS_UAPSD_TID1_8814B BIT(1) +#define BIT_WMMPS_UAPSD_TID0_8814B BIT(0) +/* 2 REG_LPNAV_CTRL_8814B (LOW POWER NAV CONTROL REGISTER) */ /* 2 REG_WKFMCAM_CMD_8814B (WAKEUP FRAME CAM COMMAND REGISTER) */ #define BIT_WKFCAM_POLLING_V1_8814B BIT(31) @@ -9406,44 +21770,46 @@ #define BIT_SHIFT_WKFCAM_ADDR_V2_8814B 8 #define BIT_MASK_WKFCAM_ADDR_V2_8814B 0xff -#define BIT_WKFCAM_ADDR_V2_8814B(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8814B) << BIT_SHIFT_WKFCAM_ADDR_V2_8814B) -#define BIT_GET_WKFCAM_ADDR_V2_8814B(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8814B) & BIT_MASK_WKFCAM_ADDR_V2_8814B) - - +#define BIT_WKFCAM_ADDR_V2_8814B(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR_V2_8814B) \ + << BIT_SHIFT_WKFCAM_ADDR_V2_8814B) +#define BITS_WKFCAM_ADDR_V2_8814B \ + (BIT_MASK_WKFCAM_ADDR_V2_8814B << BIT_SHIFT_WKFCAM_ADDR_V2_8814B) +#define BIT_CLEAR_WKFCAM_ADDR_V2_8814B(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8814B)) +#define BIT_GET_WKFCAM_ADDR_V2_8814B(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8814B) & \ + BIT_MASK_WKFCAM_ADDR_V2_8814B) +#define BIT_SET_WKFCAM_ADDR_V2_8814B(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR_V2_8814B(x) | BIT_WKFCAM_ADDR_V2_8814B(v)) #define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B 0 #define BIT_MASK_WKFCAM_CAM_NUM_V1_8814B 0xff -#define BIT_WKFCAM_CAM_NUM_V1_8814B(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8814B) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) -#define BIT_GET_WKFCAM_CAM_NUM_V1_8814B(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) & BIT_MASK_WKFCAM_CAM_NUM_V1_8814B) - - +#define BIT_WKFCAM_CAM_NUM_V1_8814B(x) \ + (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8814B) \ + << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) +#define BITS_WKFCAM_CAM_NUM_V1_8814B \ + (BIT_MASK_WKFCAM_CAM_NUM_V1_8814B << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8814B(x) \ + ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8814B)) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) & \ + BIT_MASK_WKFCAM_CAM_NUM_V1_8814B) +#define BIT_SET_WKFCAM_CAM_NUM_V1_8814B(x, v) \ + (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8814B(x) | BIT_WKFCAM_CAM_NUM_V1_8814B(v)) /* 2 REG_WKFMCAM_RWD_8814B (WAKEUP FRAME READ/WRITE DATA) */ #define BIT_SHIFT_WKFMCAM_RWD_8814B 0 #define BIT_MASK_WKFMCAM_RWD_8814B 0xffffffffL -#define BIT_WKFMCAM_RWD_8814B(x) (((x) & BIT_MASK_WKFMCAM_RWD_8814B) << BIT_SHIFT_WKFMCAM_RWD_8814B) -#define BIT_GET_WKFMCAM_RWD_8814B(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8814B) & BIT_MASK_WKFMCAM_RWD_8814B) - - - -/* 2 REG_RXFLTMAP1_8814B (RX FILTER MAP GROUP 1) */ -#define BIT_CTRLFLT15EN_8814B BIT(15) -#define BIT_CTRLFLT14EN_8814B BIT(14) -#define BIT_CTRLFLT13EN_8814B BIT(13) -#define BIT_CTRLFLT12EN_8814B BIT(12) -#define BIT_CTRLFLT11EN_8814B BIT(11) -#define BIT_CTRLFLT10EN_8814B BIT(10) -#define BIT_CTRLFLT9EN_8814B BIT(9) -#define BIT_CTRLFLT8EN_8814B BIT(8) -#define BIT_CTRLFLT7EN_8814B BIT(7) -#define BIT_CTRLFLT6EN_8814B BIT(6) -#define BIT_CTRLFLT5EN_8814B BIT(5) -#define BIT_CTRLFLT4EN_8814B BIT(4) -#define BIT_CTRLFLT3EN_8814B BIT(3) -#define BIT_CTRLFLT2EN_8814B BIT(2) -#define BIT_CTRLFLT1EN_8814B BIT(1) -#define BIT_CTRLFLT0EN_8814B BIT(0) +#define BIT_WKFMCAM_RWD_8814B(x) \ + (((x) & BIT_MASK_WKFMCAM_RWD_8814B) << BIT_SHIFT_WKFMCAM_RWD_8814B) +#define BITS_WKFMCAM_RWD_8814B \ + (BIT_MASK_WKFMCAM_RWD_8814B << BIT_SHIFT_WKFMCAM_RWD_8814B) +#define BIT_CLEAR_WKFMCAM_RWD_8814B(x) ((x) & (~BITS_WKFMCAM_RWD_8814B)) +#define BIT_GET_WKFMCAM_RWD_8814B(x) \ + (((x) >> BIT_SHIFT_WKFMCAM_RWD_8814B) & BIT_MASK_WKFMCAM_RWD_8814B) +#define BIT_SET_WKFMCAM_RWD_8814B(x, v) \ + (BIT_CLEAR_WKFMCAM_RWD_8814B(x) | BIT_WKFMCAM_RWD_8814B(v)) /* 2 REG_RXFLTMAP0_8814B (RX FILTER MAP GROUP 0) */ #define BIT_MGTFLT15EN_8814B BIT(15) @@ -9463,9 +21829,25 @@ #define BIT_MGTFLT1EN_8814B BIT(1) #define BIT_MGTFLT0EN_8814B BIT(0) -/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_RXFLTMAP1_8814B (RX FILTER MAP GROUP 1) */ +#define BIT_CTRLFLT15EN_8814B BIT(15) +#define BIT_CTRLFLT14EN_8814B BIT(14) +#define BIT_CTRLFLT13EN_8814B BIT(13) +#define BIT_CTRLFLT12EN_8814B BIT(12) +#define BIT_CTRLFLT11EN_8814B BIT(11) +#define BIT_CTRLFLT10EN_8814B BIT(10) +#define BIT_CTRLFLT9EN_8814B BIT(9) +#define BIT_CTRLFLT8EN_8814B BIT(8) +#define BIT_CTRLFLT7EN_8814B BIT(7) +#define BIT_CTRLFLT6EN_8814B BIT(6) +#define BIT_CTRLFLT5EN_8814B BIT(5) +#define BIT_CTRLFLT4EN_8814B BIT(4) +#define BIT_CTRLFLT3EN_8814B BIT(3) +#define BIT_CTRLFLT2EN_8814B BIT(2) +#define BIT_CTRLFLT1EN_8814B BIT(1) +#define BIT_CTRLFLT0EN_8814B BIT(0) -/* 2 REG_RXFLTMAP_8814B (RX FILTER MAP GROUP 2) */ +/* 2 REG_RXFLTMAP2_8814B (RX FILTER MAP GROUP 2) */ #define BIT_DATAFLT15EN_8814B BIT(15) #define BIT_DATAFLT14EN_8814B BIT(14) #define BIT_DATAFLT13EN_8814B BIT(13) @@ -9483,93 +21865,146 @@ #define BIT_DATAFLT1EN_8814B BIT(1) #define BIT_DATAFLT0EN_8814B BIT(0) +/* 2 REG_RSVD_8814B */ + /* 2 REG_BCN_PSR_RPT_8814B (BEACON PARSER REPORT REGISTER) */ #define BIT_SHIFT_DTIM_CNT_8814B 24 #define BIT_MASK_DTIM_CNT_8814B 0xff -#define BIT_DTIM_CNT_8814B(x) (((x) & BIT_MASK_DTIM_CNT_8814B) << BIT_SHIFT_DTIM_CNT_8814B) -#define BIT_GET_DTIM_CNT_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT_8814B) & BIT_MASK_DTIM_CNT_8814B) - - +#define BIT_DTIM_CNT_8814B(x) \ + (((x) & BIT_MASK_DTIM_CNT_8814B) << BIT_SHIFT_DTIM_CNT_8814B) +#define BITS_DTIM_CNT_8814B \ + (BIT_MASK_DTIM_CNT_8814B << BIT_SHIFT_DTIM_CNT_8814B) +#define BIT_CLEAR_DTIM_CNT_8814B(x) ((x) & (~BITS_DTIM_CNT_8814B)) +#define BIT_GET_DTIM_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT_8814B) & BIT_MASK_DTIM_CNT_8814B) +#define BIT_SET_DTIM_CNT_8814B(x, v) \ + (BIT_CLEAR_DTIM_CNT_8814B(x) | BIT_DTIM_CNT_8814B(v)) #define BIT_SHIFT_DTIM_PERIOD_8814B 16 #define BIT_MASK_DTIM_PERIOD_8814B 0xff -#define BIT_DTIM_PERIOD_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD_8814B) << BIT_SHIFT_DTIM_PERIOD_8814B) -#define BIT_GET_DTIM_PERIOD_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8814B) & BIT_MASK_DTIM_PERIOD_8814B) - +#define BIT_DTIM_PERIOD_8814B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD_8814B) << BIT_SHIFT_DTIM_PERIOD_8814B) +#define BITS_DTIM_PERIOD_8814B \ + (BIT_MASK_DTIM_PERIOD_8814B << BIT_SHIFT_DTIM_PERIOD_8814B) +#define BIT_CLEAR_DTIM_PERIOD_8814B(x) ((x) & (~BITS_DTIM_PERIOD_8814B)) +#define BIT_GET_DTIM_PERIOD_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD_8814B) & BIT_MASK_DTIM_PERIOD_8814B) +#define BIT_SET_DTIM_PERIOD_8814B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD_8814B(x) | BIT_DTIM_PERIOD_8814B(v)) #define BIT_DTIM_8814B BIT(15) #define BIT_TIM_8814B BIT(14) +#define BIT_RPT_VALID_8814B BIT(13) #define BIT_SHIFT_PS_AID_0_8814B 0 #define BIT_MASK_PS_AID_0_8814B 0x7ff -#define BIT_PS_AID_0_8814B(x) (((x) & BIT_MASK_PS_AID_0_8814B) << BIT_SHIFT_PS_AID_0_8814B) -#define BIT_GET_PS_AID_0_8814B(x) (((x) >> BIT_SHIFT_PS_AID_0_8814B) & BIT_MASK_PS_AID_0_8814B) - - +#define BIT_PS_AID_0_8814B(x) \ + (((x) & BIT_MASK_PS_AID_0_8814B) << BIT_SHIFT_PS_AID_0_8814B) +#define BITS_PS_AID_0_8814B \ + (BIT_MASK_PS_AID_0_8814B << BIT_SHIFT_PS_AID_0_8814B) +#define BIT_CLEAR_PS_AID_0_8814B(x) ((x) & (~BITS_PS_AID_0_8814B)) +#define BIT_GET_PS_AID_0_8814B(x) \ + (((x) >> BIT_SHIFT_PS_AID_0_8814B) & BIT_MASK_PS_AID_0_8814B) +#define BIT_SET_PS_AID_0_8814B(x, v) \ + (BIT_CLEAR_PS_AID_0_8814B(x) | BIT_PS_AID_0_8814B(v)) -/* 2 REG_FLC_TRPC_8814B (TIMER OF FLC_RPC) */ -#define BIT_FLC_RPCT_V1_8814B BIT(7) -#define BIT_MODE_8814B BIT(6) +/* 2 REG_FLC_RPC_8814B (FW LPS CONDITION -- RX PKT COUNTER) */ -#define BIT_SHIFT_TRPCD_8814B 0 -#define BIT_MASK_TRPCD_8814B 0x3f -#define BIT_TRPCD_8814B(x) (((x) & BIT_MASK_TRPCD_8814B) << BIT_SHIFT_TRPCD_8814B) -#define BIT_GET_TRPCD_8814B(x) (((x) >> BIT_SHIFT_TRPCD_8814B) & BIT_MASK_TRPCD_8814B) +#define BIT_SHIFT_FLC_RPC_8814B 0 +#define BIT_MASK_FLC_RPC_8814B 0xff +#define BIT_FLC_RPC_8814B(x) \ + (((x) & BIT_MASK_FLC_RPC_8814B) << BIT_SHIFT_FLC_RPC_8814B) +#define BITS_FLC_RPC_8814B (BIT_MASK_FLC_RPC_8814B << BIT_SHIFT_FLC_RPC_8814B) +#define BIT_CLEAR_FLC_RPC_8814B(x) ((x) & (~BITS_FLC_RPC_8814B)) +#define BIT_GET_FLC_RPC_8814B(x) \ + (((x) >> BIT_SHIFT_FLC_RPC_8814B) & BIT_MASK_FLC_RPC_8814B) +#define BIT_SET_FLC_RPC_8814B(x, v) \ + (BIT_CLEAR_FLC_RPC_8814B(x) | BIT_FLC_RPC_8814B(v)) +/* 2 REG_FLC_RPCT_8814B (FLC_RPC THRESHOLD) */ +#define BIT_SHIFT_FLC_RPCT_8814B 0 +#define BIT_MASK_FLC_RPCT_8814B 0xff +#define BIT_FLC_RPCT_8814B(x) \ + (((x) & BIT_MASK_FLC_RPCT_8814B) << BIT_SHIFT_FLC_RPCT_8814B) +#define BITS_FLC_RPCT_8814B \ + (BIT_MASK_FLC_RPCT_8814B << BIT_SHIFT_FLC_RPCT_8814B) +#define BIT_CLEAR_FLC_RPCT_8814B(x) ((x) & (~BITS_FLC_RPCT_8814B)) +#define BIT_GET_FLC_RPCT_8814B(x) \ + (((x) >> BIT_SHIFT_FLC_RPCT_8814B) & BIT_MASK_FLC_RPCT_8814B) +#define BIT_SET_FLC_RPCT_8814B(x, v) \ + (BIT_CLEAR_FLC_RPCT_8814B(x) | BIT_FLC_RPCT_8814B(v)) /* 2 REG_FLC_PTS_8814B (PKT TYPE SELECTION OF FLC_RPC T) */ #define BIT_CMF_8814B BIT(2) #define BIT_CCF_8814B BIT(1) #define BIT_CDF_8814B BIT(0) -/* 2 REG_FLC_RPCT_8814B (FLC_RPC THRESHOLD) */ - -#define BIT_SHIFT_FLC_RPCT_8814B 0 -#define BIT_MASK_FLC_RPCT_8814B 0xff -#define BIT_FLC_RPCT_8814B(x) (((x) & BIT_MASK_FLC_RPCT_8814B) << BIT_SHIFT_FLC_RPCT_8814B) -#define BIT_GET_FLC_RPCT_8814B(x) (((x) >> BIT_SHIFT_FLC_RPCT_8814B) & BIT_MASK_FLC_RPCT_8814B) - - - -/* 2 REG_FLC_RPC_8814B (FW LPS CONDITION -- RX PKT COUNTER) */ - -#define BIT_SHIFT_FLC_RPC_8814B 0 -#define BIT_MASK_FLC_RPC_8814B 0xff -#define BIT_FLC_RPC_8814B(x) (((x) & BIT_MASK_FLC_RPC_8814B) << BIT_SHIFT_FLC_RPC_8814B) -#define BIT_GET_FLC_RPC_8814B(x) (((x) >> BIT_SHIFT_FLC_RPC_8814B) & BIT_MASK_FLC_RPC_8814B) - +/* 2 REG_FLC_TRPC_8814B (TIMER OF FLC_RPC) */ +#define BIT_FLC_RPCT_V1_8814B BIT(7) +#define BIT_MODE_8814B BIT(6) +#define BIT_SHIFT_TRPCD_8814B 0 +#define BIT_MASK_TRPCD_8814B 0x3f +#define BIT_TRPCD_8814B(x) \ + (((x) & BIT_MASK_TRPCD_8814B) << BIT_SHIFT_TRPCD_8814B) +#define BITS_TRPCD_8814B (BIT_MASK_TRPCD_8814B << BIT_SHIFT_TRPCD_8814B) +#define BIT_CLEAR_TRPCD_8814B(x) ((x) & (~BITS_TRPCD_8814B)) +#define BIT_GET_TRPCD_8814B(x) \ + (((x) >> BIT_SHIFT_TRPCD_8814B) & BIT_MASK_TRPCD_8814B) +#define BIT_SET_TRPCD_8814B(x, v) \ + (BIT_CLEAR_TRPCD_8814B(x) | BIT_TRPCD_8814B(v)) /* 2 REG_RXPKTMON_CTRL_8814B */ #define BIT_SHIFT_RXBKQPKT_SEQ_8814B 20 #define BIT_MASK_RXBKQPKT_SEQ_8814B 0xf -#define BIT_RXBKQPKT_SEQ_8814B(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8814B) << BIT_SHIFT_RXBKQPKT_SEQ_8814B) -#define BIT_GET_RXBKQPKT_SEQ_8814B(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8814B) & BIT_MASK_RXBKQPKT_SEQ_8814B) - - +#define BIT_RXBKQPKT_SEQ_8814B(x) \ + (((x) & BIT_MASK_RXBKQPKT_SEQ_8814B) << BIT_SHIFT_RXBKQPKT_SEQ_8814B) +#define BITS_RXBKQPKT_SEQ_8814B \ + (BIT_MASK_RXBKQPKT_SEQ_8814B << BIT_SHIFT_RXBKQPKT_SEQ_8814B) +#define BIT_CLEAR_RXBKQPKT_SEQ_8814B(x) ((x) & (~BITS_RXBKQPKT_SEQ_8814B)) +#define BIT_GET_RXBKQPKT_SEQ_8814B(x) \ + (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8814B) & BIT_MASK_RXBKQPKT_SEQ_8814B) +#define BIT_SET_RXBKQPKT_SEQ_8814B(x, v) \ + (BIT_CLEAR_RXBKQPKT_SEQ_8814B(x) | BIT_RXBKQPKT_SEQ_8814B(v)) #define BIT_SHIFT_RXBEQPKT_SEQ_8814B 16 #define BIT_MASK_RXBEQPKT_SEQ_8814B 0xf -#define BIT_RXBEQPKT_SEQ_8814B(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8814B) << BIT_SHIFT_RXBEQPKT_SEQ_8814B) -#define BIT_GET_RXBEQPKT_SEQ_8814B(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8814B) & BIT_MASK_RXBEQPKT_SEQ_8814B) - - +#define BIT_RXBEQPKT_SEQ_8814B(x) \ + (((x) & BIT_MASK_RXBEQPKT_SEQ_8814B) << BIT_SHIFT_RXBEQPKT_SEQ_8814B) +#define BITS_RXBEQPKT_SEQ_8814B \ + (BIT_MASK_RXBEQPKT_SEQ_8814B << BIT_SHIFT_RXBEQPKT_SEQ_8814B) +#define BIT_CLEAR_RXBEQPKT_SEQ_8814B(x) ((x) & (~BITS_RXBEQPKT_SEQ_8814B)) +#define BIT_GET_RXBEQPKT_SEQ_8814B(x) \ + (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8814B) & BIT_MASK_RXBEQPKT_SEQ_8814B) +#define BIT_SET_RXBEQPKT_SEQ_8814B(x, v) \ + (BIT_CLEAR_RXBEQPKT_SEQ_8814B(x) | BIT_RXBEQPKT_SEQ_8814B(v)) #define BIT_SHIFT_RXVIQPKT_SEQ_8814B 12 #define BIT_MASK_RXVIQPKT_SEQ_8814B 0xf -#define BIT_RXVIQPKT_SEQ_8814B(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8814B) << BIT_SHIFT_RXVIQPKT_SEQ_8814B) -#define BIT_GET_RXVIQPKT_SEQ_8814B(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8814B) & BIT_MASK_RXVIQPKT_SEQ_8814B) - - +#define BIT_RXVIQPKT_SEQ_8814B(x) \ + (((x) & BIT_MASK_RXVIQPKT_SEQ_8814B) << BIT_SHIFT_RXVIQPKT_SEQ_8814B) +#define BITS_RXVIQPKT_SEQ_8814B \ + (BIT_MASK_RXVIQPKT_SEQ_8814B << BIT_SHIFT_RXVIQPKT_SEQ_8814B) +#define BIT_CLEAR_RXVIQPKT_SEQ_8814B(x) ((x) & (~BITS_RXVIQPKT_SEQ_8814B)) +#define BIT_GET_RXVIQPKT_SEQ_8814B(x) \ + (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8814B) & BIT_MASK_RXVIQPKT_SEQ_8814B) +#define BIT_SET_RXVIQPKT_SEQ_8814B(x, v) \ + (BIT_CLEAR_RXVIQPKT_SEQ_8814B(x) | BIT_RXVIQPKT_SEQ_8814B(v)) #define BIT_SHIFT_RXVOQPKT_SEQ_8814B 8 #define BIT_MASK_RXVOQPKT_SEQ_8814B 0xf -#define BIT_RXVOQPKT_SEQ_8814B(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8814B) << BIT_SHIFT_RXVOQPKT_SEQ_8814B) -#define BIT_GET_RXVOQPKT_SEQ_8814B(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8814B) & BIT_MASK_RXVOQPKT_SEQ_8814B) - +#define BIT_RXVOQPKT_SEQ_8814B(x) \ + (((x) & BIT_MASK_RXVOQPKT_SEQ_8814B) << BIT_SHIFT_RXVOQPKT_SEQ_8814B) +#define BITS_RXVOQPKT_SEQ_8814B \ + (BIT_MASK_RXVOQPKT_SEQ_8814B << BIT_SHIFT_RXVOQPKT_SEQ_8814B) +#define BIT_CLEAR_RXVOQPKT_SEQ_8814B(x) ((x) & (~BITS_RXVOQPKT_SEQ_8814B)) +#define BIT_GET_RXVOQPKT_SEQ_8814B(x) \ + (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8814B) & BIT_MASK_RXVOQPKT_SEQ_8814B) +#define BIT_SET_RXVOQPKT_SEQ_8814B(x, v) \ + (BIT_CLEAR_RXVOQPKT_SEQ_8814B(x) | BIT_RXVOQPKT_SEQ_8814B(v)) #define BIT_RXBKQPKT_ERR_8814B BIT(7) #define BIT_RXBEQPKT_ERR_8814B BIT(6) @@ -9583,29 +22018,54 @@ #define BIT_SHIFT_STATE_SEL_8814B 24 #define BIT_MASK_STATE_SEL_8814B 0x1f -#define BIT_STATE_SEL_8814B(x) (((x) & BIT_MASK_STATE_SEL_8814B) << BIT_SHIFT_STATE_SEL_8814B) -#define BIT_GET_STATE_SEL_8814B(x) (((x) >> BIT_SHIFT_STATE_SEL_8814B) & BIT_MASK_STATE_SEL_8814B) - - +#define BIT_STATE_SEL_8814B(x) \ + (((x) & BIT_MASK_STATE_SEL_8814B) << BIT_SHIFT_STATE_SEL_8814B) +#define BITS_STATE_SEL_8814B \ + (BIT_MASK_STATE_SEL_8814B << BIT_SHIFT_STATE_SEL_8814B) +#define BIT_CLEAR_STATE_SEL_8814B(x) ((x) & (~BITS_STATE_SEL_8814B)) +#define BIT_GET_STATE_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_STATE_SEL_8814B) & BIT_MASK_STATE_SEL_8814B) +#define BIT_SET_STATE_SEL_8814B(x, v) \ + (BIT_CLEAR_STATE_SEL_8814B(x) | BIT_STATE_SEL_8814B(v)) #define BIT_SHIFT_STATE_INFO_8814B 8 #define BIT_MASK_STATE_INFO_8814B 0xff -#define BIT_STATE_INFO_8814B(x) (((x) & BIT_MASK_STATE_INFO_8814B) << BIT_SHIFT_STATE_INFO_8814B) -#define BIT_GET_STATE_INFO_8814B(x) (((x) >> BIT_SHIFT_STATE_INFO_8814B) & BIT_MASK_STATE_INFO_8814B) - +#define BIT_STATE_INFO_8814B(x) \ + (((x) & BIT_MASK_STATE_INFO_8814B) << BIT_SHIFT_STATE_INFO_8814B) +#define BITS_STATE_INFO_8814B \ + (BIT_MASK_STATE_INFO_8814B << BIT_SHIFT_STATE_INFO_8814B) +#define BIT_CLEAR_STATE_INFO_8814B(x) ((x) & (~BITS_STATE_INFO_8814B)) +#define BIT_GET_STATE_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_STATE_INFO_8814B) & BIT_MASK_STATE_INFO_8814B) +#define BIT_SET_STATE_INFO_8814B(x, v) \ + (BIT_CLEAR_STATE_INFO_8814B(x) | BIT_STATE_INFO_8814B(v)) #define BIT_UPD_NXT_STATE_8814B BIT(7) #define BIT_SHIFT_CUR_STATE_8814B 0 #define BIT_MASK_CUR_STATE_8814B 0x7f -#define BIT_CUR_STATE_8814B(x) (((x) & BIT_MASK_CUR_STATE_8814B) << BIT_SHIFT_CUR_STATE_8814B) -#define BIT_GET_CUR_STATE_8814B(x) (((x) >> BIT_SHIFT_CUR_STATE_8814B) & BIT_MASK_CUR_STATE_8814B) - - +#define BIT_CUR_STATE_8814B(x) \ + (((x) & BIT_MASK_CUR_STATE_8814B) << BIT_SHIFT_CUR_STATE_8814B) +#define BITS_CUR_STATE_8814B \ + (BIT_MASK_CUR_STATE_8814B << BIT_SHIFT_CUR_STATE_8814B) +#define BIT_CLEAR_CUR_STATE_8814B(x) ((x) & (~BITS_CUR_STATE_8814B)) +#define BIT_GET_CUR_STATE_8814B(x) \ + (((x) >> BIT_SHIFT_CUR_STATE_8814B) & BIT_MASK_CUR_STATE_8814B) +#define BIT_SET_CUR_STATE_8814B(x, v) \ + (BIT_CLEAR_CUR_STATE_8814B(x) | BIT_CUR_STATE_8814B(v)) /* 2 REG_ERROR_MON_8814B */ +#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC_8814B BIT(23) +#define BIT_CSI_CHKSUM_ERROR_8814B BIT(22) +#define BIT_MACRX_ERR_5_8814B BIT(21) +#define BIT_MACRX_ERR_4_8814B BIT(20) +#define BIT_MACRX_ERR_3_8814B BIT(19) +#define BIT_MACRX_ERR_2_8814B BIT(18) #define BIT_MACRX_ERR_1_8814B BIT(17) #define BIT_MACRX_ERR_0_8814B BIT(16) +#define BIT_WMAC_PRETX_ERRHDL_EN_8814B BIT(15) +#define BIT_MACTX_ERR_5_8814B BIT(5) +#define BIT_MACTX_ERR_4_8814B BIT(4) #define BIT_MACTX_ERR_3_8814B BIT(3) #define BIT_MACTX_ERR_2_8814B BIT(2) #define BIT_MACTX_ERR_1_8814B BIT(1) @@ -9613,147 +22073,271 @@ /* 2 REG_SEARCH_MACID_8814B */ #define BIT_EN_TXRPTBUF_CLK_8814B BIT(31) - -#define BIT_SHIFT_INFO_INDEX_OFFSET_8814B 16 -#define BIT_MASK_INFO_INDEX_OFFSET_8814B 0x1fff -#define BIT_INFO_INDEX_OFFSET_8814B(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8814B) << BIT_SHIFT_INFO_INDEX_OFFSET_8814B) -#define BIT_GET_INFO_INDEX_OFFSET_8814B(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8814B) & BIT_MASK_INFO_INDEX_OFFSET_8814B) - - #define BIT_WMAC_SRCH_FIFOFULL_8814B BIT(15) #define BIT_DIS_INFOSRCH_8814B BIT(14) #define BIT_DISABLE_B0_8814B BIT(13) #define BIT_SHIFT_INFO_ADDR_OFFSET_8814B 0 #define BIT_MASK_INFO_ADDR_OFFSET_8814B 0x1fff -#define BIT_INFO_ADDR_OFFSET_8814B(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8814B) << BIT_SHIFT_INFO_ADDR_OFFSET_8814B) -#define BIT_GET_INFO_ADDR_OFFSET_8814B(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8814B) & BIT_MASK_INFO_ADDR_OFFSET_8814B) - - +#define BIT_INFO_ADDR_OFFSET_8814B(x) \ + (((x) & BIT_MASK_INFO_ADDR_OFFSET_8814B) \ + << BIT_SHIFT_INFO_ADDR_OFFSET_8814B) +#define BITS_INFO_ADDR_OFFSET_8814B \ + (BIT_MASK_INFO_ADDR_OFFSET_8814B << BIT_SHIFT_INFO_ADDR_OFFSET_8814B) +#define BIT_CLEAR_INFO_ADDR_OFFSET_8814B(x) \ + ((x) & (~BITS_INFO_ADDR_OFFSET_8814B)) +#define BIT_GET_INFO_ADDR_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8814B) & \ + BIT_MASK_INFO_ADDR_OFFSET_8814B) +#define BIT_SET_INFO_ADDR_OFFSET_8814B(x, v) \ + (BIT_CLEAR_INFO_ADDR_OFFSET_8814B(x) | BIT_INFO_ADDR_OFFSET_8814B(v)) /* 2 REG_BT_COEX_TABLE_8814B (BT-COEXISTENCE CONTROL REGISTER) */ -#define BIT_PRI_MASK_RX_RESP_8814B BIT(126) -#define BIT_PRI_MASK_RXOFDM_8814B BIT(125) -#define BIT_PRI_MASK_RXCCK_8814B BIT(124) -#define BIT_SHIFT_PRI_MASK_TXAC_8814B (117 & CPU_OPT_WIDTH) +#define BIT_SHIFT_COEX_TABLE_1_8814B 0 +#define BIT_MASK_COEX_TABLE_1_8814B 0xffffffffL +#define BIT_COEX_TABLE_1_8814B(x) \ + (((x) & BIT_MASK_COEX_TABLE_1_8814B) << BIT_SHIFT_COEX_TABLE_1_8814B) +#define BITS_COEX_TABLE_1_8814B \ + (BIT_MASK_COEX_TABLE_1_8814B << BIT_SHIFT_COEX_TABLE_1_8814B) +#define BIT_CLEAR_COEX_TABLE_1_8814B(x) ((x) & (~BITS_COEX_TABLE_1_8814B)) +#define BIT_GET_COEX_TABLE_1_8814B(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_1_8814B) & BIT_MASK_COEX_TABLE_1_8814B) +#define BIT_SET_COEX_TABLE_1_8814B(x, v) \ + (BIT_CLEAR_COEX_TABLE_1_8814B(x) | BIT_COEX_TABLE_1_8814B(v)) + +/* 2 REG_BT_COEX_TABLE2_8814B (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_COEX_TABLE_2_8814B 0 +#define BIT_MASK_COEX_TABLE_2_8814B 0xffffffffL +#define BIT_COEX_TABLE_2_8814B(x) \ + (((x) & BIT_MASK_COEX_TABLE_2_8814B) << BIT_SHIFT_COEX_TABLE_2_8814B) +#define BITS_COEX_TABLE_2_8814B \ + (BIT_MASK_COEX_TABLE_2_8814B << BIT_SHIFT_COEX_TABLE_2_8814B) +#define BIT_CLEAR_COEX_TABLE_2_8814B(x) ((x) & (~BITS_COEX_TABLE_2_8814B)) +#define BIT_GET_COEX_TABLE_2_8814B(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_2_8814B) & BIT_MASK_COEX_TABLE_2_8814B) +#define BIT_SET_COEX_TABLE_2_8814B(x, v) \ + (BIT_CLEAR_COEX_TABLE_2_8814B(x) | BIT_COEX_TABLE_2_8814B(v)) + +/* 2 REG_BT_COEX_BREAK_TABLE_8814B (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_BREAK_TABLE_2_8814B 16 +#define BIT_MASK_BREAK_TABLE_2_8814B 0xffff +#define BIT_BREAK_TABLE_2_8814B(x) \ + (((x) & BIT_MASK_BREAK_TABLE_2_8814B) << BIT_SHIFT_BREAK_TABLE_2_8814B) +#define BITS_BREAK_TABLE_2_8814B \ + (BIT_MASK_BREAK_TABLE_2_8814B << BIT_SHIFT_BREAK_TABLE_2_8814B) +#define BIT_CLEAR_BREAK_TABLE_2_8814B(x) ((x) & (~BITS_BREAK_TABLE_2_8814B)) +#define BIT_GET_BREAK_TABLE_2_8814B(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_2_8814B) & BIT_MASK_BREAK_TABLE_2_8814B) +#define BIT_SET_BREAK_TABLE_2_8814B(x, v) \ + (BIT_CLEAR_BREAK_TABLE_2_8814B(x) | BIT_BREAK_TABLE_2_8814B(v)) + +#define BIT_SHIFT_BREAK_TABLE_1_8814B 0 +#define BIT_MASK_BREAK_TABLE_1_8814B 0xffff +#define BIT_BREAK_TABLE_1_8814B(x) \ + (((x) & BIT_MASK_BREAK_TABLE_1_8814B) << BIT_SHIFT_BREAK_TABLE_1_8814B) +#define BITS_BREAK_TABLE_1_8814B \ + (BIT_MASK_BREAK_TABLE_1_8814B << BIT_SHIFT_BREAK_TABLE_1_8814B) +#define BIT_CLEAR_BREAK_TABLE_1_8814B(x) ((x) & (~BITS_BREAK_TABLE_1_8814B)) +#define BIT_GET_BREAK_TABLE_1_8814B(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_1_8814B) & BIT_MASK_BREAK_TABLE_1_8814B) +#define BIT_SET_BREAK_TABLE_1_8814B(x, v) \ + (BIT_CLEAR_BREAK_TABLE_1_8814B(x) | BIT_BREAK_TABLE_1_8814B(v)) + +/* 2 REG_BT_COEX_TABLE_H_8814B (BT-COEXISTENCE CONTROL REGISTER) */ +#define BIT_PRI_MASK_RX_RESP_V1_8814B BIT(30) +#define BIT_PRI_MASK_RXOFDM_V1_8814B BIT(29) +#define BIT_PRI_MASK_RXCCK_V1_8814B BIT(28) + +#define BIT_SHIFT_PRI_MASK_TXAC_8814B 21 #define BIT_MASK_PRI_MASK_TXAC_8814B 0x7f -#define BIT_PRI_MASK_TXAC_8814B(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8814B) << BIT_SHIFT_PRI_MASK_TXAC_8814B) -#define BIT_GET_PRI_MASK_TXAC_8814B(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8814B) & BIT_MASK_PRI_MASK_TXAC_8814B) - - - -#define BIT_SHIFT_PRI_MASK_NAV_8814B (109 & CPU_OPT_WIDTH) +#define BIT_PRI_MASK_TXAC_8814B(x) \ + (((x) & BIT_MASK_PRI_MASK_TXAC_8814B) << BIT_SHIFT_PRI_MASK_TXAC_8814B) +#define BITS_PRI_MASK_TXAC_8814B \ + (BIT_MASK_PRI_MASK_TXAC_8814B << BIT_SHIFT_PRI_MASK_TXAC_8814B) +#define BIT_CLEAR_PRI_MASK_TXAC_8814B(x) ((x) & (~BITS_PRI_MASK_TXAC_8814B)) +#define BIT_GET_PRI_MASK_TXAC_8814B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8814B) & BIT_MASK_PRI_MASK_TXAC_8814B) +#define BIT_SET_PRI_MASK_TXAC_8814B(x, v) \ + (BIT_CLEAR_PRI_MASK_TXAC_8814B(x) | BIT_PRI_MASK_TXAC_8814B(v)) + +#define BIT_SHIFT_PRI_MASK_NAV_8814B 13 #define BIT_MASK_PRI_MASK_NAV_8814B 0xff -#define BIT_PRI_MASK_NAV_8814B(x) (((x) & BIT_MASK_PRI_MASK_NAV_8814B) << BIT_SHIFT_PRI_MASK_NAV_8814B) -#define BIT_GET_PRI_MASK_NAV_8814B(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8814B) & BIT_MASK_PRI_MASK_NAV_8814B) - - -#define BIT_PRI_MASK_CCK_8814B BIT(108) -#define BIT_PRI_MASK_OFDM_8814B BIT(107) -#define BIT_PRI_MASK_RTY_8814B BIT(106) - -#define BIT_SHIFT_PRI_MASK_NUM_8814B (102 & CPU_OPT_WIDTH) +#define BIT_PRI_MASK_NAV_8814B(x) \ + (((x) & BIT_MASK_PRI_MASK_NAV_8814B) << BIT_SHIFT_PRI_MASK_NAV_8814B) +#define BITS_PRI_MASK_NAV_8814B \ + (BIT_MASK_PRI_MASK_NAV_8814B << BIT_SHIFT_PRI_MASK_NAV_8814B) +#define BIT_CLEAR_PRI_MASK_NAV_8814B(x) ((x) & (~BITS_PRI_MASK_NAV_8814B)) +#define BIT_GET_PRI_MASK_NAV_8814B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NAV_8814B) & BIT_MASK_PRI_MASK_NAV_8814B) +#define BIT_SET_PRI_MASK_NAV_8814B(x, v) \ + (BIT_CLEAR_PRI_MASK_NAV_8814B(x) | BIT_PRI_MASK_NAV_8814B(v)) + +#define BIT_PRI_MASK_CCK_V1_8814B BIT(12) +#define BIT_PRI_MASK_OFDM_V1_8814B BIT(11) +#define BIT_PRI_MASK_RTY_V1_8814B BIT(10) + +#define BIT_SHIFT_PRI_MASK_NUM_8814B 6 #define BIT_MASK_PRI_MASK_NUM_8814B 0xf -#define BIT_PRI_MASK_NUM_8814B(x) (((x) & BIT_MASK_PRI_MASK_NUM_8814B) << BIT_SHIFT_PRI_MASK_NUM_8814B) -#define BIT_GET_PRI_MASK_NUM_8814B(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8814B) & BIT_MASK_PRI_MASK_NUM_8814B) - - - -#define BIT_SHIFT_PRI_MASK_TYPE_8814B (98 & CPU_OPT_WIDTH) +#define BIT_PRI_MASK_NUM_8814B(x) \ + (((x) & BIT_MASK_PRI_MASK_NUM_8814B) << BIT_SHIFT_PRI_MASK_NUM_8814B) +#define BITS_PRI_MASK_NUM_8814B \ + (BIT_MASK_PRI_MASK_NUM_8814B << BIT_SHIFT_PRI_MASK_NUM_8814B) +#define BIT_CLEAR_PRI_MASK_NUM_8814B(x) ((x) & (~BITS_PRI_MASK_NUM_8814B)) +#define BIT_GET_PRI_MASK_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NUM_8814B) & BIT_MASK_PRI_MASK_NUM_8814B) +#define BIT_SET_PRI_MASK_NUM_8814B(x, v) \ + (BIT_CLEAR_PRI_MASK_NUM_8814B(x) | BIT_PRI_MASK_NUM_8814B(v)) + +#define BIT_SHIFT_PRI_MASK_TYPE_8814B 2 #define BIT_MASK_PRI_MASK_TYPE_8814B 0xf -#define BIT_PRI_MASK_TYPE_8814B(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8814B) << BIT_SHIFT_PRI_MASK_TYPE_8814B) -#define BIT_GET_PRI_MASK_TYPE_8814B(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8814B) & BIT_MASK_PRI_MASK_TYPE_8814B) - - -#define BIT_OOB_8814B BIT(97) -#define BIT_ANT_SEL_8814B BIT(96) - -#define BIT_SHIFT_BREAK_TABLE_2_8814B (80 & CPU_OPT_WIDTH) -#define BIT_MASK_BREAK_TABLE_2_8814B 0xffff -#define BIT_BREAK_TABLE_2_8814B(x) (((x) & BIT_MASK_BREAK_TABLE_2_8814B) << BIT_SHIFT_BREAK_TABLE_2_8814B) -#define BIT_GET_BREAK_TABLE_2_8814B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8814B) & BIT_MASK_BREAK_TABLE_2_8814B) - - - -#define BIT_SHIFT_BREAK_TABLE_1_8814B (64 & CPU_OPT_WIDTH) -#define BIT_MASK_BREAK_TABLE_1_8814B 0xffff -#define BIT_BREAK_TABLE_1_8814B(x) (((x) & BIT_MASK_BREAK_TABLE_1_8814B) << BIT_SHIFT_BREAK_TABLE_1_8814B) -#define BIT_GET_BREAK_TABLE_1_8814B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8814B) & BIT_MASK_BREAK_TABLE_1_8814B) - - - -#define BIT_SHIFT_COEX_TABLE_2_8814B (32 & CPU_OPT_WIDTH) -#define BIT_MASK_COEX_TABLE_2_8814B 0xffffffffL -#define BIT_COEX_TABLE_2_8814B(x) (((x) & BIT_MASK_COEX_TABLE_2_8814B) << BIT_SHIFT_COEX_TABLE_2_8814B) -#define BIT_GET_COEX_TABLE_2_8814B(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8814B) & BIT_MASK_COEX_TABLE_2_8814B) - - - -#define BIT_SHIFT_COEX_TABLE_1_8814B 0 -#define BIT_MASK_COEX_TABLE_1_8814B 0xffffffffL -#define BIT_COEX_TABLE_1_8814B(x) (((x) & BIT_MASK_COEX_TABLE_1_8814B) << BIT_SHIFT_COEX_TABLE_1_8814B) -#define BIT_GET_COEX_TABLE_1_8814B(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8814B) & BIT_MASK_COEX_TABLE_1_8814B) - - +#define BIT_PRI_MASK_TYPE_8814B(x) \ + (((x) & BIT_MASK_PRI_MASK_TYPE_8814B) << BIT_SHIFT_PRI_MASK_TYPE_8814B) +#define BITS_PRI_MASK_TYPE_8814B \ + (BIT_MASK_PRI_MASK_TYPE_8814B << BIT_SHIFT_PRI_MASK_TYPE_8814B) +#define BIT_CLEAR_PRI_MASK_TYPE_8814B(x) ((x) & (~BITS_PRI_MASK_TYPE_8814B)) +#define BIT_GET_PRI_MASK_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8814B) & BIT_MASK_PRI_MASK_TYPE_8814B) +#define BIT_SET_PRI_MASK_TYPE_8814B(x, v) \ + (BIT_CLEAR_PRI_MASK_TYPE_8814B(x) | BIT_PRI_MASK_TYPE_8814B(v)) + +#define BIT_OOB_V1_8814B BIT(1) +#define BIT_ANT_SEL_V1_8814B BIT(0) /* 2 REG_RXCMD_0_8814B */ #define BIT_RXCMD_EN_8814B BIT(31) #define BIT_SHIFT_RXCMD_INFO_8814B 0 #define BIT_MASK_RXCMD_INFO_8814B 0x7fffffffL -#define BIT_RXCMD_INFO_8814B(x) (((x) & BIT_MASK_RXCMD_INFO_8814B) << BIT_SHIFT_RXCMD_INFO_8814B) -#define BIT_GET_RXCMD_INFO_8814B(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8814B) & BIT_MASK_RXCMD_INFO_8814B) - - +#define BIT_RXCMD_INFO_8814B(x) \ + (((x) & BIT_MASK_RXCMD_INFO_8814B) << BIT_SHIFT_RXCMD_INFO_8814B) +#define BITS_RXCMD_INFO_8814B \ + (BIT_MASK_RXCMD_INFO_8814B << BIT_SHIFT_RXCMD_INFO_8814B) +#define BIT_CLEAR_RXCMD_INFO_8814B(x) ((x) & (~BITS_RXCMD_INFO_8814B)) +#define BIT_GET_RXCMD_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_RXCMD_INFO_8814B) & BIT_MASK_RXCMD_INFO_8814B) +#define BIT_SET_RXCMD_INFO_8814B(x, v) \ + (BIT_CLEAR_RXCMD_INFO_8814B(x) | BIT_RXCMD_INFO_8814B(v)) /* 2 REG_RXCMD_1_8814B */ +#define BIT_SHIFT_CSI_RADDR_LATCH_8814B 24 +#define BIT_MASK_CSI_RADDR_LATCH_8814B 0xff +#define BIT_CSI_RADDR_LATCH_8814B(x) \ + (((x) & BIT_MASK_CSI_RADDR_LATCH_8814B) \ + << BIT_SHIFT_CSI_RADDR_LATCH_8814B) +#define BITS_CSI_RADDR_LATCH_8814B \ + (BIT_MASK_CSI_RADDR_LATCH_8814B << BIT_SHIFT_CSI_RADDR_LATCH_8814B) +#define BIT_CLEAR_CSI_RADDR_LATCH_8814B(x) ((x) & (~BITS_CSI_RADDR_LATCH_8814B)) +#define BIT_GET_CSI_RADDR_LATCH_8814B(x) \ + (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_8814B) & \ + BIT_MASK_CSI_RADDR_LATCH_8814B) +#define BIT_SET_CSI_RADDR_LATCH_8814B(x, v) \ + (BIT_CLEAR_CSI_RADDR_LATCH_8814B(x) | BIT_CSI_RADDR_LATCH_8814B(v)) + +#define BIT_SHIFT_CSI_WADDR_LATCH_8814B 16 +#define BIT_MASK_CSI_WADDR_LATCH_8814B 0xff +#define BIT_CSI_WADDR_LATCH_8814B(x) \ + (((x) & BIT_MASK_CSI_WADDR_LATCH_8814B) \ + << BIT_SHIFT_CSI_WADDR_LATCH_8814B) +#define BITS_CSI_WADDR_LATCH_8814B \ + (BIT_MASK_CSI_WADDR_LATCH_8814B << BIT_SHIFT_CSI_WADDR_LATCH_8814B) +#define BIT_CLEAR_CSI_WADDR_LATCH_8814B(x) ((x) & (~BITS_CSI_WADDR_LATCH_8814B)) +#define BIT_GET_CSI_WADDR_LATCH_8814B(x) \ + (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_8814B) & \ + BIT_MASK_CSI_WADDR_LATCH_8814B) +#define BIT_SET_CSI_WADDR_LATCH_8814B(x, v) \ + (BIT_CLEAR_CSI_WADDR_LATCH_8814B(x) | BIT_CSI_WADDR_LATCH_8814B(v)) + #define BIT_SHIFT_RXCMD_PRD_8814B 0 #define BIT_MASK_RXCMD_PRD_8814B 0xffff -#define BIT_RXCMD_PRD_8814B(x) (((x) & BIT_MASK_RXCMD_PRD_8814B) << BIT_SHIFT_RXCMD_PRD_8814B) -#define BIT_GET_RXCMD_PRD_8814B(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8814B) & BIT_MASK_RXCMD_PRD_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_RXCMD_PRD_8814B(x) \ + (((x) & BIT_MASK_RXCMD_PRD_8814B) << BIT_SHIFT_RXCMD_PRD_8814B) +#define BITS_RXCMD_PRD_8814B \ + (BIT_MASK_RXCMD_PRD_8814B << BIT_SHIFT_RXCMD_PRD_8814B) +#define BIT_CLEAR_RXCMD_PRD_8814B(x) ((x) & (~BITS_RXCMD_PRD_8814B)) +#define BIT_GET_RXCMD_PRD_8814B(x) \ + (((x) >> BIT_SHIFT_RXCMD_PRD_8814B) & BIT_MASK_RXCMD_PRD_8814B) +#define BIT_SET_RXCMD_PRD_8814B(x, v) \ + (BIT_CLEAR_RXCMD_PRD_8814B(x) | BIT_RXCMD_PRD_8814B(v)) /* 2 REG_WMAC_RESP_TXINFO_8814B (RESPONSE TXINFO REGISTER) */ #define BIT_SHIFT_WMAC_RESP_MFB_8814B 25 #define BIT_MASK_WMAC_RESP_MFB_8814B 0x7f -#define BIT_WMAC_RESP_MFB_8814B(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8814B) << BIT_SHIFT_WMAC_RESP_MFB_8814B) -#define BIT_GET_WMAC_RESP_MFB_8814B(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8814B) & BIT_MASK_WMAC_RESP_MFB_8814B) - - +#define BIT_WMAC_RESP_MFB_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_MFB_8814B) << BIT_SHIFT_WMAC_RESP_MFB_8814B) +#define BITS_WMAC_RESP_MFB_8814B \ + (BIT_MASK_WMAC_RESP_MFB_8814B << BIT_SHIFT_WMAC_RESP_MFB_8814B) +#define BIT_CLEAR_WMAC_RESP_MFB_8814B(x) ((x) & (~BITS_WMAC_RESP_MFB_8814B)) +#define BIT_GET_WMAC_RESP_MFB_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8814B) & BIT_MASK_WMAC_RESP_MFB_8814B) +#define BIT_SET_WMAC_RESP_MFB_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_MFB_8814B(x) | BIT_WMAC_RESP_MFB_8814B(v)) #define BIT_SHIFT_WMAC_ANTINF_SEL_8814B 23 #define BIT_MASK_WMAC_ANTINF_SEL_8814B 0x3 -#define BIT_WMAC_ANTINF_SEL_8814B(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8814B) << BIT_SHIFT_WMAC_ANTINF_SEL_8814B) -#define BIT_GET_WMAC_ANTINF_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8814B) & BIT_MASK_WMAC_ANTINF_SEL_8814B) - - +#define BIT_WMAC_ANTINF_SEL_8814B(x) \ + (((x) & BIT_MASK_WMAC_ANTINF_SEL_8814B) \ + << BIT_SHIFT_WMAC_ANTINF_SEL_8814B) +#define BITS_WMAC_ANTINF_SEL_8814B \ + (BIT_MASK_WMAC_ANTINF_SEL_8814B << BIT_SHIFT_WMAC_ANTINF_SEL_8814B) +#define BIT_CLEAR_WMAC_ANTINF_SEL_8814B(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8814B)) +#define BIT_GET_WMAC_ANTINF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8814B) & \ + BIT_MASK_WMAC_ANTINF_SEL_8814B) +#define BIT_SET_WMAC_ANTINF_SEL_8814B(x, v) \ + (BIT_CLEAR_WMAC_ANTINF_SEL_8814B(x) | BIT_WMAC_ANTINF_SEL_8814B(v)) #define BIT_SHIFT_WMAC_ANTSEL_SEL_8814B 21 #define BIT_MASK_WMAC_ANTSEL_SEL_8814B 0x3 -#define BIT_WMAC_ANTSEL_SEL_8814B(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8814B) << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) -#define BIT_GET_WMAC_ANTSEL_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) & BIT_MASK_WMAC_ANTSEL_SEL_8814B) - - - -#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8814B 18 -#define BIT_MASK_R_WMAC_RESP_TXPOWER_8814B 0x7 -#define BIT_R_WMAC_RESP_TXPOWER_8814B(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8814B) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8814B) -#define BIT_GET_R_WMAC_RESP_TXPOWER_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8814B) & BIT_MASK_R_WMAC_RESP_TXPOWER_8814B) - - - -#define BIT_SHIFT_WMAC_RESP_TXANT_8814B 0 -#define BIT_MASK_WMAC_RESP_TXANT_8814B 0x3ffff -#define BIT_WMAC_RESP_TXANT_8814B(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8814B) << BIT_SHIFT_WMAC_RESP_TXANT_8814B) -#define BIT_GET_WMAC_RESP_TXANT_8814B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8814B) & BIT_MASK_WMAC_RESP_TXANT_8814B) - - +#define BIT_WMAC_ANTSEL_SEL_8814B(x) \ + (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8814B) \ + << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) +#define BITS_WMAC_ANTSEL_SEL_8814B \ + (BIT_MASK_WMAC_ANTSEL_SEL_8814B << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) +#define BIT_CLEAR_WMAC_ANTSEL_SEL_8814B(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8814B)) +#define BIT_GET_WMAC_ANTSEL_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) & \ + BIT_MASK_WMAC_ANTSEL_SEL_8814B) +#define BIT_SET_WMAC_ANTSEL_SEL_8814B(x, v) \ + (BIT_CLEAR_WMAC_ANTSEL_SEL_8814B(x) | BIT_WMAC_ANTSEL_SEL_8814B(v)) + +#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B 18 +#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B 0x3 +#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) \ + << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) +#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B \ + (BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B \ + << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) +#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) \ + ((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)) +#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) & \ + BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) +#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) | \ + BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(v)) + +#define BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B 6 +#define BIT_MASK_WMAC_RESP_TXANT_V1_8814B 0xfff +#define BIT_WMAC_RESP_TXANT_V1_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT_V1_8814B) \ + << BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B) +#define BITS_WMAC_RESP_TXANT_V1_8814B \ + (BIT_MASK_WMAC_RESP_TXANT_V1_8814B \ + << BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B) +#define BIT_CLEAR_WMAC_RESP_TXANT_V1_8814B(x) \ + ((x) & (~BITS_WMAC_RESP_TXANT_V1_8814B)) +#define BIT_GET_WMAC_RESP_TXANT_V1_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B) & \ + BIT_MASK_WMAC_RESP_TXANT_V1_8814B) +#define BIT_SET_WMAC_RESP_TXANT_V1_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT_V1_8814B(x) | \ + BIT_WMAC_RESP_TXANT_V1_8814B(v)) /* 2 REG_BBPSF_CTRL_8814B */ #define BIT_CTL_IDLE_CLR_CSI_RPT_8814B BIT(31) @@ -9761,289 +22345,1016 @@ #define BIT_SHIFT_WMAC_CSI_RATE_8814B 24 #define BIT_MASK_WMAC_CSI_RATE_8814B 0x3f -#define BIT_WMAC_CSI_RATE_8814B(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8814B) << BIT_SHIFT_WMAC_CSI_RATE_8814B) -#define BIT_GET_WMAC_CSI_RATE_8814B(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8814B) & BIT_MASK_WMAC_CSI_RATE_8814B) - - +#define BIT_WMAC_CSI_RATE_8814B(x) \ + (((x) & BIT_MASK_WMAC_CSI_RATE_8814B) << BIT_SHIFT_WMAC_CSI_RATE_8814B) +#define BITS_WMAC_CSI_RATE_8814B \ + (BIT_MASK_WMAC_CSI_RATE_8814B << BIT_SHIFT_WMAC_CSI_RATE_8814B) +#define BIT_CLEAR_WMAC_CSI_RATE_8814B(x) ((x) & (~BITS_WMAC_CSI_RATE_8814B)) +#define BIT_GET_WMAC_CSI_RATE_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8814B) & BIT_MASK_WMAC_CSI_RATE_8814B) +#define BIT_SET_WMAC_CSI_RATE_8814B(x, v) \ + (BIT_CLEAR_WMAC_CSI_RATE_8814B(x) | BIT_WMAC_CSI_RATE_8814B(v)) #define BIT_SHIFT_WMAC_RESP_TXRATE_8814B 16 #define BIT_MASK_WMAC_RESP_TXRATE_8814B 0xff -#define BIT_WMAC_RESP_TXRATE_8814B(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8814B) << BIT_SHIFT_WMAC_RESP_TXRATE_8814B) -#define BIT_GET_WMAC_RESP_TXRATE_8814B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8814B) & BIT_MASK_WMAC_RESP_TXRATE_8814B) - +#define BIT_WMAC_RESP_TXRATE_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXRATE_8814B) \ + << BIT_SHIFT_WMAC_RESP_TXRATE_8814B) +#define BITS_WMAC_RESP_TXRATE_8814B \ + (BIT_MASK_WMAC_RESP_TXRATE_8814B << BIT_SHIFT_WMAC_RESP_TXRATE_8814B) +#define BIT_CLEAR_WMAC_RESP_TXRATE_8814B(x) \ + ((x) & (~BITS_WMAC_RESP_TXRATE_8814B)) +#define BIT_GET_WMAC_RESP_TXRATE_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8814B) & \ + BIT_MASK_WMAC_RESP_TXRATE_8814B) +#define BIT_SET_WMAC_RESP_TXRATE_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXRATE_8814B(x) | BIT_WMAC_RESP_TXRATE_8814B(v)) #define BIT_CSI_FORCE_RATE_EN_8814B BIT(15) #define BIT_SHIFT_CSI_RSC_8814B 13 #define BIT_MASK_CSI_RSC_8814B 0x3 -#define BIT_CSI_RSC_8814B(x) (((x) & BIT_MASK_CSI_RSC_8814B) << BIT_SHIFT_CSI_RSC_8814B) -#define BIT_GET_CSI_RSC_8814B(x) (((x) >> BIT_SHIFT_CSI_RSC_8814B) & BIT_MASK_CSI_RSC_8814B) - +#define BIT_CSI_RSC_8814B(x) \ + (((x) & BIT_MASK_CSI_RSC_8814B) << BIT_SHIFT_CSI_RSC_8814B) +#define BITS_CSI_RSC_8814B (BIT_MASK_CSI_RSC_8814B << BIT_SHIFT_CSI_RSC_8814B) +#define BIT_CLEAR_CSI_RSC_8814B(x) ((x) & (~BITS_CSI_RSC_8814B)) +#define BIT_GET_CSI_RSC_8814B(x) \ + (((x) >> BIT_SHIFT_CSI_RSC_8814B) & BIT_MASK_CSI_RSC_8814B) +#define BIT_SET_CSI_RSC_8814B(x, v) \ + (BIT_CLEAR_CSI_RSC_8814B(x) | BIT_CSI_RSC_8814B(v)) #define BIT_CSI_GID_SEL_8814B BIT(12) #define BIT_RDCSIMD_FLAG_TRIG_SEL_8814B BIT(11) -#define BIT_NDPVLD_POS_RST_FFPTR_DIS_8814B BIT(10) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1_8814B BIT(10) #define BIT_NDPVLD_PROTECT_RDRDY_DIS_8814B BIT(9) #define BIT_RDCSI_EMPTY_APPZERO_8814B BIT(8) -#define BIT_BBPSF_MPDUCHKEN_8814B BIT(5) -#define BIT_BBPSF_MHCHKEN_8814B BIT(4) -#define BIT_BBPSF_ERRCHKEN_8814B BIT(3) - -#define BIT_SHIFT_BBPSF_ERRTHR_8814B 0 -#define BIT_MASK_BBPSF_ERRTHR_8814B 0x7 -#define BIT_BBPSF_ERRTHR_8814B(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8814B) << BIT_SHIFT_BBPSF_ERRTHR_8814B) -#define BIT_GET_BBPSF_ERRTHR_8814B(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8814B) & BIT_MASK_BBPSF_ERRTHR_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_CSI_RATE_FB_EN_8814B BIT(7) +#define BIT_RXFIFO_WRPTR_WO_CHKSUM_8814B BIT(6) /* 2 REG_P2P_RX_BCN_NOA_8814B (P2P RX BEACON NOA REGISTER) */ #define BIT_NOA_PARSER_EN_8814B BIT(15) -#define BIT_BSSID_SEL_8814B BIT(14) + +#define BIT_SHIFT_BSSID_SEL_V1_8814B 12 +#define BIT_MASK_BSSID_SEL_V1_8814B 0x7 +#define BIT_BSSID_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID_SEL_V1_8814B) << BIT_SHIFT_BSSID_SEL_V1_8814B) +#define BITS_BSSID_SEL_V1_8814B \ + (BIT_MASK_BSSID_SEL_V1_8814B << BIT_SHIFT_BSSID_SEL_V1_8814B) +#define BIT_CLEAR_BSSID_SEL_V1_8814B(x) ((x) & (~BITS_BSSID_SEL_V1_8814B)) +#define BIT_GET_BSSID_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID_SEL_V1_8814B) & BIT_MASK_BSSID_SEL_V1_8814B) +#define BIT_SET_BSSID_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID_SEL_V1_8814B(x) | BIT_BSSID_SEL_V1_8814B(v)) #define BIT_SHIFT_P2P_OUI_TYPE_8814B 0 #define BIT_MASK_P2P_OUI_TYPE_8814B 0xff -#define BIT_P2P_OUI_TYPE_8814B(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8814B) << BIT_SHIFT_P2P_OUI_TYPE_8814B) -#define BIT_GET_P2P_OUI_TYPE_8814B(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8814B) & BIT_MASK_P2P_OUI_TYPE_8814B) - +#define BIT_P2P_OUI_TYPE_8814B(x) \ + (((x) & BIT_MASK_P2P_OUI_TYPE_8814B) << BIT_SHIFT_P2P_OUI_TYPE_8814B) +#define BITS_P2P_OUI_TYPE_8814B \ + (BIT_MASK_P2P_OUI_TYPE_8814B << BIT_SHIFT_P2P_OUI_TYPE_8814B) +#define BIT_CLEAR_P2P_OUI_TYPE_8814B(x) ((x) & (~BITS_P2P_OUI_TYPE_8814B)) +#define BIT_GET_P2P_OUI_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8814B) & BIT_MASK_P2P_OUI_TYPE_8814B) +#define BIT_SET_P2P_OUI_TYPE_8814B(x, v) \ + (BIT_CLEAR_P2P_OUI_TYPE_8814B(x) | BIT_P2P_OUI_TYPE_8814B(v)) +/* 2 REG_RSVD_8814B */ /* 2 REG_ASSOCIATED_BFMER0_INFO_8814B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ -#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B (48 & CPU_OPT_WIDTH) +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8814B \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(v)) + +/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8814B */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B 16 #define BIT_MASK_R_WMAC_TXCSI_AID0_8814B 0x1ff -#define BIT_R_WMAC_TXCSI_AID0_8814B(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8814B) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) -#define BIT_GET_R_WMAC_TXCSI_AID0_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) & BIT_MASK_R_WMAC_TXCSI_AID0_8814B) - - - -#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8814B 0 -#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8814B 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R0_8814B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8814B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8814B) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8814B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8814B) - - +#define BIT_R_WMAC_TXCSI_AID0_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8814B) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) +#define BITS_R_WMAC_TXCSI_AID0_8814B \ + (BIT_MASK_R_WMAC_TXCSI_AID0_8814B << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) +#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8814B(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID0_8814B)) +#define BIT_GET_R_WMAC_TXCSI_AID0_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) & \ + BIT_MASK_R_WMAC_TXCSI_AID0_8814B) +#define BIT_SET_R_WMAC_TXCSI_AID0_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID0_8814B(x) | BIT_R_WMAC_TXCSI_AID0_8814B(v)) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(v)) /* 2 REG_ASSOCIATED_BFMER1_INFO_8814B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ -#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B (48 & CPU_OPT_WIDTH) +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8814B \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(v)) + +/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8814B */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B 16 #define BIT_MASK_R_WMAC_TXCSI_AID1_8814B 0x1ff -#define BIT_R_WMAC_TXCSI_AID1_8814B(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8814B) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) -#define BIT_GET_R_WMAC_TXCSI_AID1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) & BIT_MASK_R_WMAC_TXCSI_AID1_8814B) - - - -#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8814B 0 -#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8814B 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R1_8814B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8814B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8814B) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8814B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_R_WMAC_TXCSI_AID1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8814B) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) +#define BITS_R_WMAC_TXCSI_AID1_8814B \ + (BIT_MASK_R_WMAC_TXCSI_AID1_8814B << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) +#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8814B(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID1_8814B)) +#define BIT_GET_R_WMAC_TXCSI_AID1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) & \ + BIT_MASK_R_WMAC_TXCSI_AID1_8814B) +#define BIT_SET_R_WMAC_TXCSI_AID1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID1_8814B(x) | BIT_R_WMAC_TXCSI_AID1_8814B(v)) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW20_8814B (TX CSI REPORT PARAMETER REGISTER) */ #define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B 16 #define BIT_MASK_R_WMAC_BFINFO_20M_1_8814B 0xfff -#define BIT_R_WMAC_BFINFO_20M_1_8814B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8814B) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) -#define BIT_GET_R_WMAC_BFINFO_20M_1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) & BIT_MASK_R_WMAC_BFINFO_20M_1_8814B) - - +#define BIT_R_WMAC_BFINFO_20M_1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8814B) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) +#define BITS_R_WMAC_BFINFO_20M_1_8814B \ + (BIT_MASK_R_WMAC_BFINFO_20M_1_8814B \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8814B(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8814B)) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) & \ + BIT_MASK_R_WMAC_BFINFO_20M_1_8814B) +#define BIT_SET_R_WMAC_BFINFO_20M_1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8814B(x) | \ + BIT_R_WMAC_BFINFO_20M_1_8814B(v)) #define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B 0 #define BIT_MASK_R_WMAC_BFINFO_20M_0_8814B 0xfff -#define BIT_R_WMAC_BFINFO_20M_0_8814B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8814B) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) -#define BIT_GET_R_WMAC_BFINFO_20M_0_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) & BIT_MASK_R_WMAC_BFINFO_20M_0_8814B) - - +#define BIT_R_WMAC_BFINFO_20M_0_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8814B) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) +#define BITS_R_WMAC_BFINFO_20M_0_8814B \ + (BIT_MASK_R_WMAC_BFINFO_20M_0_8814B \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8814B(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8814B)) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) & \ + BIT_MASK_R_WMAC_BFINFO_20M_0_8814B) +#define BIT_SET_R_WMAC_BFINFO_20M_0_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8814B(x) | \ + BIT_R_WMAC_BFINFO_20M_0_8814B(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW40_8814B (TX CSI REPORT PARAMETER_BW40 REGISTER) */ -#define BIT_SHIFT_WMAC_RESP_ANTCD_8814B 0 -#define BIT_MASK_WMAC_RESP_ANTCD_8814B 0xf -#define BIT_WMAC_RESP_ANTCD_8814B(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8814B) << BIT_SHIFT_WMAC_RESP_ANTCD_8814B) -#define BIT_GET_WMAC_RESP_ANTCD_8814B(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8814B) & BIT_MASK_WMAC_RESP_ANTCD_8814B) - +#define BIT_SHIFT_WMAC_RESP_ANTD_8814B 12 +#define BIT_MASK_WMAC_RESP_ANTD_8814B 0xf +#define BIT_WMAC_RESP_ANTD_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTD_8814B) \ + << BIT_SHIFT_WMAC_RESP_ANTD_8814B) +#define BITS_WMAC_RESP_ANTD_8814B \ + (BIT_MASK_WMAC_RESP_ANTD_8814B << BIT_SHIFT_WMAC_RESP_ANTD_8814B) +#define BIT_CLEAR_WMAC_RESP_ANTD_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTD_8814B)) +#define BIT_GET_WMAC_RESP_ANTD_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTD_8814B) & \ + BIT_MASK_WMAC_RESP_ANTD_8814B) +#define BIT_SET_WMAC_RESP_ANTD_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTD_8814B(x) | BIT_WMAC_RESP_ANTD_8814B(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTC_8814B 8 +#define BIT_MASK_WMAC_RESP_ANTC_8814B 0xf +#define BIT_WMAC_RESP_ANTC_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTC_8814B) \ + << BIT_SHIFT_WMAC_RESP_ANTC_8814B) +#define BITS_WMAC_RESP_ANTC_8814B \ + (BIT_MASK_WMAC_RESP_ANTC_8814B << BIT_SHIFT_WMAC_RESP_ANTC_8814B) +#define BIT_CLEAR_WMAC_RESP_ANTC_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTC_8814B)) +#define BIT_GET_WMAC_RESP_ANTC_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTC_8814B) & \ + BIT_MASK_WMAC_RESP_ANTC_8814B) +#define BIT_SET_WMAC_RESP_ANTC_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTC_8814B(x) | BIT_WMAC_RESP_ANTC_8814B(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTB_8814B 4 +#define BIT_MASK_WMAC_RESP_ANTB_8814B 0xf +#define BIT_WMAC_RESP_ANTB_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTB_8814B) \ + << BIT_SHIFT_WMAC_RESP_ANTB_8814B) +#define BITS_WMAC_RESP_ANTB_8814B \ + (BIT_MASK_WMAC_RESP_ANTB_8814B << BIT_SHIFT_WMAC_RESP_ANTB_8814B) +#define BIT_CLEAR_WMAC_RESP_ANTB_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTB_8814B)) +#define BIT_GET_WMAC_RESP_ANTB_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTB_8814B) & \ + BIT_MASK_WMAC_RESP_ANTB_8814B) +#define BIT_SET_WMAC_RESP_ANTB_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTB_8814B(x) | BIT_WMAC_RESP_ANTB_8814B(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTA_8814B 0 +#define BIT_MASK_WMAC_RESP_ANTA_8814B 0xf +#define BIT_WMAC_RESP_ANTA_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTA_8814B) \ + << BIT_SHIFT_WMAC_RESP_ANTA_8814B) +#define BITS_WMAC_RESP_ANTA_8814B \ + (BIT_MASK_WMAC_RESP_ANTA_8814B << BIT_SHIFT_WMAC_RESP_ANTA_8814B) +#define BIT_CLEAR_WMAC_RESP_ANTA_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTA_8814B)) +#define BIT_GET_WMAC_RESP_ANTA_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTA_8814B) & \ + BIT_MASK_WMAC_RESP_ANTA_8814B) +#define BIT_SET_WMAC_RESP_ANTA_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTA_8814B(x) | BIT_WMAC_RESP_ANTA_8814B(v)) - -/* 2 REG_TX_CSI_RPT_PARAM_BW80_8814B (TX CSI REPORT PARAMETER_BW80 REGISTER) */ +/* 2 REG_RSVD_8814B */ /* 2 REG_BCN_PSR_RPT2_8814B (BEACON PARSER REPORT REGISTER2) */ #define BIT_SHIFT_DTIM_CNT2_8814B 24 #define BIT_MASK_DTIM_CNT2_8814B 0xff -#define BIT_DTIM_CNT2_8814B(x) (((x) & BIT_MASK_DTIM_CNT2_8814B) << BIT_SHIFT_DTIM_CNT2_8814B) -#define BIT_GET_DTIM_CNT2_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8814B) & BIT_MASK_DTIM_CNT2_8814B) - - +#define BIT_DTIM_CNT2_8814B(x) \ + (((x) & BIT_MASK_DTIM_CNT2_8814B) << BIT_SHIFT_DTIM_CNT2_8814B) +#define BITS_DTIM_CNT2_8814B \ + (BIT_MASK_DTIM_CNT2_8814B << BIT_SHIFT_DTIM_CNT2_8814B) +#define BIT_CLEAR_DTIM_CNT2_8814B(x) ((x) & (~BITS_DTIM_CNT2_8814B)) +#define BIT_GET_DTIM_CNT2_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT2_8814B) & BIT_MASK_DTIM_CNT2_8814B) +#define BIT_SET_DTIM_CNT2_8814B(x, v) \ + (BIT_CLEAR_DTIM_CNT2_8814B(x) | BIT_DTIM_CNT2_8814B(v)) #define BIT_SHIFT_DTIM_PERIOD2_8814B 16 #define BIT_MASK_DTIM_PERIOD2_8814B 0xff -#define BIT_DTIM_PERIOD2_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD2_8814B) << BIT_SHIFT_DTIM_PERIOD2_8814B) -#define BIT_GET_DTIM_PERIOD2_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8814B) & BIT_MASK_DTIM_PERIOD2_8814B) - +#define BIT_DTIM_PERIOD2_8814B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD2_8814B) << BIT_SHIFT_DTIM_PERIOD2_8814B) +#define BITS_DTIM_PERIOD2_8814B \ + (BIT_MASK_DTIM_PERIOD2_8814B << BIT_SHIFT_DTIM_PERIOD2_8814B) +#define BIT_CLEAR_DTIM_PERIOD2_8814B(x) ((x) & (~BITS_DTIM_PERIOD2_8814B)) +#define BIT_GET_DTIM_PERIOD2_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD2_8814B) & BIT_MASK_DTIM_PERIOD2_8814B) +#define BIT_SET_DTIM_PERIOD2_8814B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD2_8814B(x) | BIT_DTIM_PERIOD2_8814B(v)) #define BIT_DTIM2_8814B BIT(15) #define BIT_TIM2_8814B BIT(14) +#define BIT_RPT_VALID_8814B BIT(13) #define BIT_SHIFT_PS_AID_2_8814B 0 #define BIT_MASK_PS_AID_2_8814B 0x7ff -#define BIT_PS_AID_2_8814B(x) (((x) & BIT_MASK_PS_AID_2_8814B) << BIT_SHIFT_PS_AID_2_8814B) -#define BIT_GET_PS_AID_2_8814B(x) (((x) >> BIT_SHIFT_PS_AID_2_8814B) & BIT_MASK_PS_AID_2_8814B) - - +#define BIT_PS_AID_2_8814B(x) \ + (((x) & BIT_MASK_PS_AID_2_8814B) << BIT_SHIFT_PS_AID_2_8814B) +#define BITS_PS_AID_2_8814B \ + (BIT_MASK_PS_AID_2_8814B << BIT_SHIFT_PS_AID_2_8814B) +#define BIT_CLEAR_PS_AID_2_8814B(x) ((x) & (~BITS_PS_AID_2_8814B)) +#define BIT_GET_PS_AID_2_8814B(x) \ + (((x) >> BIT_SHIFT_PS_AID_2_8814B) & BIT_MASK_PS_AID_2_8814B) +#define BIT_SET_PS_AID_2_8814B(x, v) \ + (BIT_CLEAR_PS_AID_2_8814B(x) | BIT_PS_AID_2_8814B(v)) /* 2 REG_BCN_PSR_RPT3_8814B (BEACON PARSER REPORT REGISTER3) */ #define BIT_SHIFT_DTIM_CNT3_8814B 24 #define BIT_MASK_DTIM_CNT3_8814B 0xff -#define BIT_DTIM_CNT3_8814B(x) (((x) & BIT_MASK_DTIM_CNT3_8814B) << BIT_SHIFT_DTIM_CNT3_8814B) -#define BIT_GET_DTIM_CNT3_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8814B) & BIT_MASK_DTIM_CNT3_8814B) - - +#define BIT_DTIM_CNT3_8814B(x) \ + (((x) & BIT_MASK_DTIM_CNT3_8814B) << BIT_SHIFT_DTIM_CNT3_8814B) +#define BITS_DTIM_CNT3_8814B \ + (BIT_MASK_DTIM_CNT3_8814B << BIT_SHIFT_DTIM_CNT3_8814B) +#define BIT_CLEAR_DTIM_CNT3_8814B(x) ((x) & (~BITS_DTIM_CNT3_8814B)) +#define BIT_GET_DTIM_CNT3_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT3_8814B) & BIT_MASK_DTIM_CNT3_8814B) +#define BIT_SET_DTIM_CNT3_8814B(x, v) \ + (BIT_CLEAR_DTIM_CNT3_8814B(x) | BIT_DTIM_CNT3_8814B(v)) #define BIT_SHIFT_DTIM_PERIOD3_8814B 16 #define BIT_MASK_DTIM_PERIOD3_8814B 0xff -#define BIT_DTIM_PERIOD3_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD3_8814B) << BIT_SHIFT_DTIM_PERIOD3_8814B) -#define BIT_GET_DTIM_PERIOD3_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8814B) & BIT_MASK_DTIM_PERIOD3_8814B) - +#define BIT_DTIM_PERIOD3_8814B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD3_8814B) << BIT_SHIFT_DTIM_PERIOD3_8814B) +#define BITS_DTIM_PERIOD3_8814B \ + (BIT_MASK_DTIM_PERIOD3_8814B << BIT_SHIFT_DTIM_PERIOD3_8814B) +#define BIT_CLEAR_DTIM_PERIOD3_8814B(x) ((x) & (~BITS_DTIM_PERIOD3_8814B)) +#define BIT_GET_DTIM_PERIOD3_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD3_8814B) & BIT_MASK_DTIM_PERIOD3_8814B) +#define BIT_SET_DTIM_PERIOD3_8814B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD3_8814B(x) | BIT_DTIM_PERIOD3_8814B(v)) #define BIT_DTIM3_8814B BIT(15) #define BIT_TIM3_8814B BIT(14) +#define BIT_RPT_VALID_8814B BIT(13) #define BIT_SHIFT_PS_AID_3_8814B 0 #define BIT_MASK_PS_AID_3_8814B 0x7ff -#define BIT_PS_AID_3_8814B(x) (((x) & BIT_MASK_PS_AID_3_8814B) << BIT_SHIFT_PS_AID_3_8814B) -#define BIT_GET_PS_AID_3_8814B(x) (((x) >> BIT_SHIFT_PS_AID_3_8814B) & BIT_MASK_PS_AID_3_8814B) - - +#define BIT_PS_AID_3_8814B(x) \ + (((x) & BIT_MASK_PS_AID_3_8814B) << BIT_SHIFT_PS_AID_3_8814B) +#define BITS_PS_AID_3_8814B \ + (BIT_MASK_PS_AID_3_8814B << BIT_SHIFT_PS_AID_3_8814B) +#define BIT_CLEAR_PS_AID_3_8814B(x) ((x) & (~BITS_PS_AID_3_8814B)) +#define BIT_GET_PS_AID_3_8814B(x) \ + (((x) >> BIT_SHIFT_PS_AID_3_8814B) & BIT_MASK_PS_AID_3_8814B) +#define BIT_SET_PS_AID_3_8814B(x, v) \ + (BIT_CLEAR_PS_AID_3_8814B(x) | BIT_PS_AID_3_8814B(v)) /* 2 REG_BCN_PSR_RPT4_8814B (BEACON PARSER REPORT REGISTER4) */ #define BIT_SHIFT_DTIM_CNT4_8814B 24 #define BIT_MASK_DTIM_CNT4_8814B 0xff -#define BIT_DTIM_CNT4_8814B(x) (((x) & BIT_MASK_DTIM_CNT4_8814B) << BIT_SHIFT_DTIM_CNT4_8814B) -#define BIT_GET_DTIM_CNT4_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8814B) & BIT_MASK_DTIM_CNT4_8814B) - - +#define BIT_DTIM_CNT4_8814B(x) \ + (((x) & BIT_MASK_DTIM_CNT4_8814B) << BIT_SHIFT_DTIM_CNT4_8814B) +#define BITS_DTIM_CNT4_8814B \ + (BIT_MASK_DTIM_CNT4_8814B << BIT_SHIFT_DTIM_CNT4_8814B) +#define BIT_CLEAR_DTIM_CNT4_8814B(x) ((x) & (~BITS_DTIM_CNT4_8814B)) +#define BIT_GET_DTIM_CNT4_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT4_8814B) & BIT_MASK_DTIM_CNT4_8814B) +#define BIT_SET_DTIM_CNT4_8814B(x, v) \ + (BIT_CLEAR_DTIM_CNT4_8814B(x) | BIT_DTIM_CNT4_8814B(v)) #define BIT_SHIFT_DTIM_PERIOD4_8814B 16 #define BIT_MASK_DTIM_PERIOD4_8814B 0xff -#define BIT_DTIM_PERIOD4_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD4_8814B) << BIT_SHIFT_DTIM_PERIOD4_8814B) -#define BIT_GET_DTIM_PERIOD4_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8814B) & BIT_MASK_DTIM_PERIOD4_8814B) - +#define BIT_DTIM_PERIOD4_8814B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD4_8814B) << BIT_SHIFT_DTIM_PERIOD4_8814B) +#define BITS_DTIM_PERIOD4_8814B \ + (BIT_MASK_DTIM_PERIOD4_8814B << BIT_SHIFT_DTIM_PERIOD4_8814B) +#define BIT_CLEAR_DTIM_PERIOD4_8814B(x) ((x) & (~BITS_DTIM_PERIOD4_8814B)) +#define BIT_GET_DTIM_PERIOD4_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD4_8814B) & BIT_MASK_DTIM_PERIOD4_8814B) +#define BIT_SET_DTIM_PERIOD4_8814B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD4_8814B(x) | BIT_DTIM_PERIOD4_8814B(v)) #define BIT_DTIM4_8814B BIT(15) #define BIT_TIM4_8814B BIT(14) +#define BIT_RPT_VALID_8814B BIT(13) #define BIT_SHIFT_PS_AID_4_8814B 0 #define BIT_MASK_PS_AID_4_8814B 0x7ff -#define BIT_PS_AID_4_8814B(x) (((x) & BIT_MASK_PS_AID_4_8814B) << BIT_SHIFT_PS_AID_4_8814B) -#define BIT_GET_PS_AID_4_8814B(x) (((x) >> BIT_SHIFT_PS_AID_4_8814B) & BIT_MASK_PS_AID_4_8814B) - - +#define BIT_PS_AID_4_8814B(x) \ + (((x) & BIT_MASK_PS_AID_4_8814B) << BIT_SHIFT_PS_AID_4_8814B) +#define BITS_PS_AID_4_8814B \ + (BIT_MASK_PS_AID_4_8814B << BIT_SHIFT_PS_AID_4_8814B) +#define BIT_CLEAR_PS_AID_4_8814B(x) ((x) & (~BITS_PS_AID_4_8814B)) +#define BIT_GET_PS_AID_4_8814B(x) \ + (((x) >> BIT_SHIFT_PS_AID_4_8814B) & BIT_MASK_PS_AID_4_8814B) +#define BIT_SET_PS_AID_4_8814B(x, v) \ + (BIT_CLEAR_PS_AID_4_8814B(x) | BIT_PS_AID_4_8814B(v)) /* 2 REG_A1_ADDR_MASK_8814B (A1 ADDR MASK REGISTER) */ #define BIT_SHIFT_A1_ADDR_MASK_8814B 0 #define BIT_MASK_A1_ADDR_MASK_8814B 0xffffffffL -#define BIT_A1_ADDR_MASK_8814B(x) (((x) & BIT_MASK_A1_ADDR_MASK_8814B) << BIT_SHIFT_A1_ADDR_MASK_8814B) -#define BIT_GET_A1_ADDR_MASK_8814B(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8814B) & BIT_MASK_A1_ADDR_MASK_8814B) - - +#define BIT_A1_ADDR_MASK_8814B(x) \ + (((x) & BIT_MASK_A1_ADDR_MASK_8814B) << BIT_SHIFT_A1_ADDR_MASK_8814B) +#define BITS_A1_ADDR_MASK_8814B \ + (BIT_MASK_A1_ADDR_MASK_8814B << BIT_SHIFT_A1_ADDR_MASK_8814B) +#define BIT_CLEAR_A1_ADDR_MASK_8814B(x) ((x) & (~BITS_A1_ADDR_MASK_8814B)) +#define BIT_GET_A1_ADDR_MASK_8814B(x) \ + (((x) >> BIT_SHIFT_A1_ADDR_MASK_8814B) & BIT_MASK_A1_ADDR_MASK_8814B) +#define BIT_SET_A1_ADDR_MASK_8814B(x, v) \ + (BIT_CLEAR_A1_ADDR_MASK_8814B(x) | BIT_A1_ADDR_MASK_8814B(v)) + +/* 2 REG_RXPSF_CTRL_8814B */ +#define BIT_RXGCK_FIFOTHR_EN_8814B BIT(28) + +#define BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B 26 +#define BIT_MASK_RXGCK_VHT_FIFOTHR_8814B 0x3 +#define BIT_RXGCK_VHT_FIFOTHR_8814B(x) \ + (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR_8814B) \ + << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B) +#define BITS_RXGCK_VHT_FIFOTHR_8814B \ + (BIT_MASK_RXGCK_VHT_FIFOTHR_8814B << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B) +#define BIT_CLEAR_RXGCK_VHT_FIFOTHR_8814B(x) \ + ((x) & (~BITS_RXGCK_VHT_FIFOTHR_8814B)) +#define BIT_GET_RXGCK_VHT_FIFOTHR_8814B(x) \ + (((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B) & \ + BIT_MASK_RXGCK_VHT_FIFOTHR_8814B) +#define BIT_SET_RXGCK_VHT_FIFOTHR_8814B(x, v) \ + (BIT_CLEAR_RXGCK_VHT_FIFOTHR_8814B(x) | BIT_RXGCK_VHT_FIFOTHR_8814B(v)) + +#define BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B 24 +#define BIT_MASK_RXGCK_HT_FIFOTHR_8814B 0x3 +#define BIT_RXGCK_HT_FIFOTHR_8814B(x) \ + (((x) & BIT_MASK_RXGCK_HT_FIFOTHR_8814B) \ + << BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B) +#define BITS_RXGCK_HT_FIFOTHR_8814B \ + (BIT_MASK_RXGCK_HT_FIFOTHR_8814B << BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B) +#define BIT_CLEAR_RXGCK_HT_FIFOTHR_8814B(x) \ + ((x) & (~BITS_RXGCK_HT_FIFOTHR_8814B)) +#define BIT_GET_RXGCK_HT_FIFOTHR_8814B(x) \ + (((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B) & \ + BIT_MASK_RXGCK_HT_FIFOTHR_8814B) +#define BIT_SET_RXGCK_HT_FIFOTHR_8814B(x, v) \ + (BIT_CLEAR_RXGCK_HT_FIFOTHR_8814B(x) | BIT_RXGCK_HT_FIFOTHR_8814B(v)) + +#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B 22 +#define BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B 0x3 +#define BIT_RXGCK_OFDM_FIFOTHR_8814B(x) \ + (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B) \ + << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B) +#define BITS_RXGCK_OFDM_FIFOTHR_8814B \ + (BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B \ + << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B) +#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8814B(x) \ + ((x) & (~BITS_RXGCK_OFDM_FIFOTHR_8814B)) +#define BIT_GET_RXGCK_OFDM_FIFOTHR_8814B(x) \ + (((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B) & \ + BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B) +#define BIT_SET_RXGCK_OFDM_FIFOTHR_8814B(x, v) \ + (BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8814B(x) | \ + BIT_RXGCK_OFDM_FIFOTHR_8814B(v)) + +#define BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B 20 +#define BIT_MASK_RXGCK_CCK_FIFOTHR_8814B 0x3 +#define BIT_RXGCK_CCK_FIFOTHR_8814B(x) \ + (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR_8814B) \ + << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B) +#define BITS_RXGCK_CCK_FIFOTHR_8814B \ + (BIT_MASK_RXGCK_CCK_FIFOTHR_8814B << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B) +#define BIT_CLEAR_RXGCK_CCK_FIFOTHR_8814B(x) \ + ((x) & (~BITS_RXGCK_CCK_FIFOTHR_8814B)) +#define BIT_GET_RXGCK_CCK_FIFOTHR_8814B(x) \ + (((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B) & \ + BIT_MASK_RXGCK_CCK_FIFOTHR_8814B) +#define BIT_SET_RXGCK_CCK_FIFOTHR_8814B(x, v) \ + (BIT_CLEAR_RXGCK_CCK_FIFOTHR_8814B(x) | BIT_RXGCK_CCK_FIFOTHR_8814B(v)) + +#define BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B 17 +#define BIT_MASK_RXGCK_ENTRY_DELAY_8814B 0x7 +#define BIT_RXGCK_ENTRY_DELAY_8814B(x) \ + (((x) & BIT_MASK_RXGCK_ENTRY_DELAY_8814B) \ + << BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B) +#define BITS_RXGCK_ENTRY_DELAY_8814B \ + (BIT_MASK_RXGCK_ENTRY_DELAY_8814B << BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B) +#define BIT_CLEAR_RXGCK_ENTRY_DELAY_8814B(x) \ + ((x) & (~BITS_RXGCK_ENTRY_DELAY_8814B)) +#define BIT_GET_RXGCK_ENTRY_DELAY_8814B(x) \ + (((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B) & \ + BIT_MASK_RXGCK_ENTRY_DELAY_8814B) +#define BIT_SET_RXGCK_ENTRY_DELAY_8814B(x, v) \ + (BIT_CLEAR_RXGCK_ENTRY_DELAY_8814B(x) | BIT_RXGCK_ENTRY_DELAY_8814B(v)) + +#define BIT_RXGCK_OFDMCCA_EN_8814B BIT(16) + +#define BIT_SHIFT_RXPSF_PKTLENTHR_8814B 13 +#define BIT_MASK_RXPSF_PKTLENTHR_8814B 0x7 +#define BIT_RXPSF_PKTLENTHR_8814B(x) \ + (((x) & BIT_MASK_RXPSF_PKTLENTHR_8814B) \ + << BIT_SHIFT_RXPSF_PKTLENTHR_8814B) +#define BITS_RXPSF_PKTLENTHR_8814B \ + (BIT_MASK_RXPSF_PKTLENTHR_8814B << BIT_SHIFT_RXPSF_PKTLENTHR_8814B) +#define BIT_CLEAR_RXPSF_PKTLENTHR_8814B(x) ((x) & (~BITS_RXPSF_PKTLENTHR_8814B)) +#define BIT_GET_RXPSF_PKTLENTHR_8814B(x) \ + (((x) >> BIT_SHIFT_RXPSF_PKTLENTHR_8814B) & \ + BIT_MASK_RXPSF_PKTLENTHR_8814B) +#define BIT_SET_RXPSF_PKTLENTHR_8814B(x, v) \ + (BIT_CLEAR_RXPSF_PKTLENTHR_8814B(x) | BIT_RXPSF_PKTLENTHR_8814B(v)) + +#define BIT_RXPSF_CTRLEN_8814B BIT(12) +#define BIT_RXPSF_VHTCHKEN_8814B BIT(11) +#define BIT_RXPSF_HTCHKEN_8814B BIT(10) +#define BIT_RXPSF_OFDMCHKEN_8814B BIT(9) +#define BIT_RXPSF_CCKCHKEN_8814B BIT(8) +#define BIT_RXPSF_OFDMRST_8814B BIT(7) +#define BIT_RXPSF_CCKRST_8814B BIT(6) +#define BIT_RXPSF_MHCHKEN_8814B BIT(5) +#define BIT_RXPSF_CONT_ERRCHKEN_8814B BIT(4) +#define BIT_RXPSF_ALL_ERRCHKEN_8814B BIT(3) + +#define BIT_SHIFT_RXPSF_ERRTHR_8814B 0 +#define BIT_MASK_RXPSF_ERRTHR_8814B 0x7 +#define BIT_RXPSF_ERRTHR_8814B(x) \ + (((x) & BIT_MASK_RXPSF_ERRTHR_8814B) << BIT_SHIFT_RXPSF_ERRTHR_8814B) +#define BITS_RXPSF_ERRTHR_8814B \ + (BIT_MASK_RXPSF_ERRTHR_8814B << BIT_SHIFT_RXPSF_ERRTHR_8814B) +#define BIT_CLEAR_RXPSF_ERRTHR_8814B(x) ((x) & (~BITS_RXPSF_ERRTHR_8814B)) +#define BIT_GET_RXPSF_ERRTHR_8814B(x) \ + (((x) >> BIT_SHIFT_RXPSF_ERRTHR_8814B) & BIT_MASK_RXPSF_ERRTHR_8814B) +#define BIT_SET_RXPSF_ERRTHR_8814B(x, v) \ + (BIT_CLEAR_RXPSF_ERRTHR_8814B(x) | BIT_RXPSF_ERRTHR_8814B(v)) + +/* 2 REG_RXPSF_TYPE_CTRL_8814B */ +#define BIT_RXPSF_DATA15EN_8814B BIT(31) +#define BIT_RXPSF_DATA14EN_8814B BIT(30) +#define BIT_RXPSF_DATA13EN_8814B BIT(29) +#define BIT_RXPSF_DATA12EN_8814B BIT(28) +#define BIT_RXPSF_DATA11EN_8814B BIT(27) +#define BIT_RXPSF_DATA10EN_8814B BIT(26) +#define BIT_RXPSF_DATA9EN_8814B BIT(25) +#define BIT_RXPSF_DATA8EN_8814B BIT(24) +#define BIT_RXPSF_DATA7EN_8814B BIT(23) +#define BIT_RXPSF_DATA6EN_8814B BIT(22) +#define BIT_RXPSF_DATA5EN_8814B BIT(21) +#define BIT_RXPSF_DATA4EN_8814B BIT(20) +#define BIT_RXPSF_DATA3EN_8814B BIT(19) +#define BIT_RXPSF_DATA2EN_8814B BIT(18) +#define BIT_RXPSF_DATA1EN_8814B BIT(17) +#define BIT_RXPSF_DATA0EN_8814B BIT(16) +#define BIT_RXPSF_MGT15EN_8814B BIT(15) +#define BIT_RXPSF_MGT14EN_8814B BIT(14) +#define BIT_RXPSF_MGT13EN_8814B BIT(13) +#define BIT_RXPSF_MGT12EN_8814B BIT(12) +#define BIT_RXPSF_MGT11EN_8814B BIT(11) +#define BIT_RXPSF_MGT10EN_8814B BIT(10) +#define BIT_RXPSF_MGT9EN_8814B BIT(9) +#define BIT_RXPSF_MGT8EN_8814B BIT(8) +#define BIT_RXPSF_MGT7EN_8814B BIT(7) +#define BIT_RXPSF_MGT6EN_8814B BIT(6) +#define BIT_RXPSF_MGT5EN_8814B BIT(5) +#define BIT_RXPSF_MGT4EN_8814B BIT(4) +#define BIT_RXPSF_MGT3EN_8814B BIT(3) +#define BIT_RXPSF_MGT2EN_8814B BIT(2) +#define BIT_RXPSF_MGT1EN_8814B BIT(1) +#define BIT_RXPSF_MGT0EN_8814B BIT(0) + +/* 2 REG_CAM_ACCESS_CTRL_8814B */ +#define BIT_INDIRECT_ERR_8814B BIT(6) +#define BIT_DIRECT_ERR_8814B BIT(5) +#define BIT_DIR_ACCESS_EN_RX_BA_8814B BIT(4) +#define BIT_DIR_ACCESS_EN_ADDRCAM_8814B BIT(3) +#define BIT_DIR_ACCESS_EN_KEY_8814B BIT(2) +#define BIT_DIR_ACCESS_EN_WOWLAN_8814B BIT(1) +#define BIT_DIR_ACCESS_EN_FW_FILTER_8814B BIT(0) + +/* 2 REG_CUT_AMSDU_CTRL_8814B */ +#define BIT__CUT_AMSDU_CHKLEN_EN_8814B BIT(31) +#define BIT_EN_CUT_AMSDU_8814B BIT(30) + +#define BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B 16 +#define BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B 0xff +#define BIT_CUT_AMSDU_CHKLEN_L_TH_8814B(x) \ + (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B) \ + << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B) +#define BITS_CUT_AMSDU_CHKLEN_L_TH_8814B \ + (BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B \ + << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B) +#define BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH_8814B(x) \ + ((x) & (~BITS_CUT_AMSDU_CHKLEN_L_TH_8814B)) +#define BIT_GET_CUT_AMSDU_CHKLEN_L_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B) & \ + BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B) +#define BIT_SET_CUT_AMSDU_CHKLEN_L_TH_8814B(x, v) \ + (BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH_8814B(x) | \ + BIT_CUT_AMSDU_CHKLEN_L_TH_8814B(v)) + +#define BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B 0 +#define BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B 0xffff +#define BIT_CUT_AMSDU_CHKLEN_H_TH_8814B(x) \ + (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B) \ + << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B) +#define BITS_CUT_AMSDU_CHKLEN_H_TH_8814B \ + (BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B \ + << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B) +#define BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH_8814B(x) \ + ((x) & (~BITS_CUT_AMSDU_CHKLEN_H_TH_8814B)) +#define BIT_GET_CUT_AMSDU_CHKLEN_H_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B) & \ + BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B) +#define BIT_SET_CUT_AMSDU_CHKLEN_H_TH_8814B(x, v) \ + (BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH_8814B(x) | \ + BIT_CUT_AMSDU_CHKLEN_H_TH_8814B(v)) /* 2 REG_MACID2_8814B (MAC ID2 REGISTER) */ -#define BIT_SHIFT_MACID2_8814B 0 -#define BIT_MASK_MACID2_8814B 0xffffffffffffL -#define BIT_MACID2_8814B(x) (((x) & BIT_MASK_MACID2_8814B) << BIT_SHIFT_MACID2_8814B) -#define BIT_GET_MACID2_8814B(x) (((x) >> BIT_SHIFT_MACID2_8814B) & BIT_MASK_MACID2_8814B) - - +#define BIT_SHIFT_MACID2_V1_8814B 0 +#define BIT_MASK_MACID2_V1_8814B 0xffffffffL +#define BIT_MACID2_V1_8814B(x) \ + (((x) & BIT_MASK_MACID2_V1_8814B) << BIT_SHIFT_MACID2_V1_8814B) +#define BITS_MACID2_V1_8814B \ + (BIT_MASK_MACID2_V1_8814B << BIT_SHIFT_MACID2_V1_8814B) +#define BIT_CLEAR_MACID2_V1_8814B(x) ((x) & (~BITS_MACID2_V1_8814B)) +#define BIT_GET_MACID2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID2_V1_8814B) & BIT_MASK_MACID2_V1_8814B) +#define BIT_SET_MACID2_V1_8814B(x, v) \ + (BIT_CLEAR_MACID2_V1_8814B(x) | BIT_MACID2_V1_8814B(v)) + +/* 2 REG_MACID2_H_8814B (MAC ID2 REGISTER) */ + +#define BIT_SHIFT_MACID2_H_V1_8814B 0 +#define BIT_MASK_MACID2_H_V1_8814B 0xffff +#define BIT_MACID2_H_V1_8814B(x) \ + (((x) & BIT_MASK_MACID2_H_V1_8814B) << BIT_SHIFT_MACID2_H_V1_8814B) +#define BITS_MACID2_H_V1_8814B \ + (BIT_MASK_MACID2_H_V1_8814B << BIT_SHIFT_MACID2_H_V1_8814B) +#define BIT_CLEAR_MACID2_H_V1_8814B(x) ((x) & (~BITS_MACID2_H_V1_8814B)) +#define BIT_GET_MACID2_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID2_H_V1_8814B) & BIT_MASK_MACID2_H_V1_8814B) +#define BIT_SET_MACID2_H_V1_8814B(x, v) \ + (BIT_CLEAR_MACID2_H_V1_8814B(x) | BIT_MACID2_H_V1_8814B(v)) /* 2 REG_BSSID2_8814B (BSSID2 REGISTER) */ -#define BIT_SHIFT_BSSID2_8814B 0 -#define BIT_MASK_BSSID2_8814B 0xffffffffffffL -#define BIT_BSSID2_8814B(x) (((x) & BIT_MASK_BSSID2_8814B) << BIT_SHIFT_BSSID2_8814B) -#define BIT_GET_BSSID2_8814B(x) (((x) >> BIT_SHIFT_BSSID2_8814B) & BIT_MASK_BSSID2_8814B) - - +#define BIT_SHIFT_BSSID2_V1_8814B 0 +#define BIT_MASK_BSSID2_V1_8814B 0xffffffffL +#define BIT_BSSID2_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID2_V1_8814B) << BIT_SHIFT_BSSID2_V1_8814B) +#define BITS_BSSID2_V1_8814B \ + (BIT_MASK_BSSID2_V1_8814B << BIT_SHIFT_BSSID2_V1_8814B) +#define BIT_CLEAR_BSSID2_V1_8814B(x) ((x) & (~BITS_BSSID2_V1_8814B)) +#define BIT_GET_BSSID2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID2_V1_8814B) & BIT_MASK_BSSID2_V1_8814B) +#define BIT_SET_BSSID2_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID2_V1_8814B(x) | BIT_BSSID2_V1_8814B(v)) + +/* 2 REG_BSSID2_H_8814B (BSSID2 REGISTER) */ + +#define BIT_SHIFT_BSSID2_H_V1_8814B 0 +#define BIT_MASK_BSSID2_H_V1_8814B 0xffff +#define BIT_BSSID2_H_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID2_H_V1_8814B) << BIT_SHIFT_BSSID2_H_V1_8814B) +#define BITS_BSSID2_H_V1_8814B \ + (BIT_MASK_BSSID2_H_V1_8814B << BIT_SHIFT_BSSID2_H_V1_8814B) +#define BIT_CLEAR_BSSID2_H_V1_8814B(x) ((x) & (~BITS_BSSID2_H_V1_8814B)) +#define BIT_GET_BSSID2_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID2_H_V1_8814B) & BIT_MASK_BSSID2_H_V1_8814B) +#define BIT_SET_BSSID2_H_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID2_H_V1_8814B(x) | BIT_BSSID2_H_V1_8814B(v)) /* 2 REG_MACID3_8814B (MAC ID3 REGISTER) */ -#define BIT_SHIFT_MACID3_8814B 0 -#define BIT_MASK_MACID3_8814B 0xffffffffffffL -#define BIT_MACID3_8814B(x) (((x) & BIT_MASK_MACID3_8814B) << BIT_SHIFT_MACID3_8814B) -#define BIT_GET_MACID3_8814B(x) (((x) >> BIT_SHIFT_MACID3_8814B) & BIT_MASK_MACID3_8814B) - - +#define BIT_SHIFT_MACID3_V1_8814B 0 +#define BIT_MASK_MACID3_V1_8814B 0xffffffffL +#define BIT_MACID3_V1_8814B(x) \ + (((x) & BIT_MASK_MACID3_V1_8814B) << BIT_SHIFT_MACID3_V1_8814B) +#define BITS_MACID3_V1_8814B \ + (BIT_MASK_MACID3_V1_8814B << BIT_SHIFT_MACID3_V1_8814B) +#define BIT_CLEAR_MACID3_V1_8814B(x) ((x) & (~BITS_MACID3_V1_8814B)) +#define BIT_GET_MACID3_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID3_V1_8814B) & BIT_MASK_MACID3_V1_8814B) +#define BIT_SET_MACID3_V1_8814B(x, v) \ + (BIT_CLEAR_MACID3_V1_8814B(x) | BIT_MACID3_V1_8814B(v)) + +/* 2 REG_MACID3_H_8814B (MAC ID3 REGISTER) */ + +#define BIT_SHIFT_MACID3_H_V1_8814B 0 +#define BIT_MASK_MACID3_H_V1_8814B 0xffff +#define BIT_MACID3_H_V1_8814B(x) \ + (((x) & BIT_MASK_MACID3_H_V1_8814B) << BIT_SHIFT_MACID3_H_V1_8814B) +#define BITS_MACID3_H_V1_8814B \ + (BIT_MASK_MACID3_H_V1_8814B << BIT_SHIFT_MACID3_H_V1_8814B) +#define BIT_CLEAR_MACID3_H_V1_8814B(x) ((x) & (~BITS_MACID3_H_V1_8814B)) +#define BIT_GET_MACID3_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID3_H_V1_8814B) & BIT_MASK_MACID3_H_V1_8814B) +#define BIT_SET_MACID3_H_V1_8814B(x, v) \ + (BIT_CLEAR_MACID3_H_V1_8814B(x) | BIT_MACID3_H_V1_8814B(v)) /* 2 REG_BSSID3_8814B (BSSID3 REGISTER) */ -#define BIT_SHIFT_BSSID3_8814B 0 -#define BIT_MASK_BSSID3_8814B 0xffffffffffffL -#define BIT_BSSID3_8814B(x) (((x) & BIT_MASK_BSSID3_8814B) << BIT_SHIFT_BSSID3_8814B) -#define BIT_GET_BSSID3_8814B(x) (((x) >> BIT_SHIFT_BSSID3_8814B) & BIT_MASK_BSSID3_8814B) - - +#define BIT_SHIFT_BSSID3_V1_8814B 0 +#define BIT_MASK_BSSID3_V1_8814B 0xffffffffL +#define BIT_BSSID3_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID3_V1_8814B) << BIT_SHIFT_BSSID3_V1_8814B) +#define BITS_BSSID3_V1_8814B \ + (BIT_MASK_BSSID3_V1_8814B << BIT_SHIFT_BSSID3_V1_8814B) +#define BIT_CLEAR_BSSID3_V1_8814B(x) ((x) & (~BITS_BSSID3_V1_8814B)) +#define BIT_GET_BSSID3_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID3_V1_8814B) & BIT_MASK_BSSID3_V1_8814B) +#define BIT_SET_BSSID3_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID3_V1_8814B(x) | BIT_BSSID3_V1_8814B(v)) + +/* 2 REG_BSSID3_H_8814B (BSSID3 REGISTER) */ + +#define BIT_SHIFT_BSSID3_H_V1_8814B 0 +#define BIT_MASK_BSSID3_H_V1_8814B 0xffff +#define BIT_BSSID3_H_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID3_H_V1_8814B) << BIT_SHIFT_BSSID3_H_V1_8814B) +#define BITS_BSSID3_H_V1_8814B \ + (BIT_MASK_BSSID3_H_V1_8814B << BIT_SHIFT_BSSID3_H_V1_8814B) +#define BIT_CLEAR_BSSID3_H_V1_8814B(x) ((x) & (~BITS_BSSID3_H_V1_8814B)) +#define BIT_GET_BSSID3_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID3_H_V1_8814B) & BIT_MASK_BSSID3_H_V1_8814B) +#define BIT_SET_BSSID3_H_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID3_H_V1_8814B(x) | BIT_BSSID3_H_V1_8814B(v)) /* 2 REG_MACID4_8814B (MAC ID4 REGISTER) */ -#define BIT_SHIFT_MACID4_8814B 0 -#define BIT_MASK_MACID4_8814B 0xffffffffffffL -#define BIT_MACID4_8814B(x) (((x) & BIT_MASK_MACID4_8814B) << BIT_SHIFT_MACID4_8814B) -#define BIT_GET_MACID4_8814B(x) (((x) >> BIT_SHIFT_MACID4_8814B) & BIT_MASK_MACID4_8814B) - - +#define BIT_SHIFT_MACID4_V1_8814B 0 +#define BIT_MASK_MACID4_V1_8814B 0xffffffffL +#define BIT_MACID4_V1_8814B(x) \ + (((x) & BIT_MASK_MACID4_V1_8814B) << BIT_SHIFT_MACID4_V1_8814B) +#define BITS_MACID4_V1_8814B \ + (BIT_MASK_MACID4_V1_8814B << BIT_SHIFT_MACID4_V1_8814B) +#define BIT_CLEAR_MACID4_V1_8814B(x) ((x) & (~BITS_MACID4_V1_8814B)) +#define BIT_GET_MACID4_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID4_V1_8814B) & BIT_MASK_MACID4_V1_8814B) +#define BIT_SET_MACID4_V1_8814B(x, v) \ + (BIT_CLEAR_MACID4_V1_8814B(x) | BIT_MACID4_V1_8814B(v)) + +/* 2 REG_MACID4_H_8814B (MAC ID4 REGISTER) */ + +#define BIT_SHIFT_MACID4_H_V1_8814B 0 +#define BIT_MASK_MACID4_H_V1_8814B 0xffff +#define BIT_MACID4_H_V1_8814B(x) \ + (((x) & BIT_MASK_MACID4_H_V1_8814B) << BIT_SHIFT_MACID4_H_V1_8814B) +#define BITS_MACID4_H_V1_8814B \ + (BIT_MASK_MACID4_H_V1_8814B << BIT_SHIFT_MACID4_H_V1_8814B) +#define BIT_CLEAR_MACID4_H_V1_8814B(x) ((x) & (~BITS_MACID4_H_V1_8814B)) +#define BIT_GET_MACID4_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID4_H_V1_8814B) & BIT_MASK_MACID4_H_V1_8814B) +#define BIT_SET_MACID4_H_V1_8814B(x, v) \ + (BIT_CLEAR_MACID4_H_V1_8814B(x) | BIT_MACID4_H_V1_8814B(v)) /* 2 REG_BSSID4_8814B (BSSID4 REGISTER) */ -#define BIT_SHIFT_BSSID4_8814B 0 -#define BIT_MASK_BSSID4_8814B 0xffffffffffffL -#define BIT_BSSID4_8814B(x) (((x) & BIT_MASK_BSSID4_8814B) << BIT_SHIFT_BSSID4_8814B) -#define BIT_GET_BSSID4_8814B(x) (((x) >> BIT_SHIFT_BSSID4_8814B) & BIT_MASK_BSSID4_8814B) - - +#define BIT_SHIFT_BSSID4_V1_8814B 0 +#define BIT_MASK_BSSID4_V1_8814B 0xffffffffL +#define BIT_BSSID4_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID4_V1_8814B) << BIT_SHIFT_BSSID4_V1_8814B) +#define BITS_BSSID4_V1_8814B \ + (BIT_MASK_BSSID4_V1_8814B << BIT_SHIFT_BSSID4_V1_8814B) +#define BIT_CLEAR_BSSID4_V1_8814B(x) ((x) & (~BITS_BSSID4_V1_8814B)) +#define BIT_GET_BSSID4_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID4_V1_8814B) & BIT_MASK_BSSID4_V1_8814B) +#define BIT_SET_BSSID4_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID4_V1_8814B(x) | BIT_BSSID4_V1_8814B(v)) + +/* 2 REG_BSSID4_H_8814B (BSSID4 REGISTER) */ + +#define BIT_SHIFT_BSSID4_H_V1_8814B 0 +#define BIT_MASK_BSSID4_H_V1_8814B 0xffff +#define BIT_BSSID4_H_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID4_H_V1_8814B) << BIT_SHIFT_BSSID4_H_V1_8814B) +#define BITS_BSSID4_H_V1_8814B \ + (BIT_MASK_BSSID4_H_V1_8814B << BIT_SHIFT_BSSID4_H_V1_8814B) +#define BIT_CLEAR_BSSID4_H_V1_8814B(x) ((x) & (~BITS_BSSID4_H_V1_8814B)) +#define BIT_GET_BSSID4_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID4_H_V1_8814B) & BIT_MASK_BSSID4_H_V1_8814B) +#define BIT_SET_BSSID4_H_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID4_H_V1_8814B(x) | BIT_BSSID4_H_V1_8814B(v)) /* 2 REG_NOA_REPORT_8814B */ +#define BIT_SHIFT_NOA_RPT_8814B 0 +#define BIT_MASK_NOA_RPT_8814B 0xffffffffL +#define BIT_NOA_RPT_8814B(x) \ + (((x) & BIT_MASK_NOA_RPT_8814B) << BIT_SHIFT_NOA_RPT_8814B) +#define BITS_NOA_RPT_8814B (BIT_MASK_NOA_RPT_8814B << BIT_SHIFT_NOA_RPT_8814B) +#define BIT_CLEAR_NOA_RPT_8814B(x) ((x) & (~BITS_NOA_RPT_8814B)) +#define BIT_GET_NOA_RPT_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_RPT_8814B) & BIT_MASK_NOA_RPT_8814B) +#define BIT_SET_NOA_RPT_8814B(x, v) \ + (BIT_CLEAR_NOA_RPT_8814B(x) | BIT_NOA_RPT_8814B(v)) + +/* 2 REG_NOA_REPORT_1_8814B */ + +#define BIT_SHIFT_NOA_RPT_1_8814B 0 +#define BIT_MASK_NOA_RPT_1_8814B 0xffffffffL +#define BIT_NOA_RPT_1_8814B(x) \ + (((x) & BIT_MASK_NOA_RPT_1_8814B) << BIT_SHIFT_NOA_RPT_1_8814B) +#define BITS_NOA_RPT_1_8814B \ + (BIT_MASK_NOA_RPT_1_8814B << BIT_SHIFT_NOA_RPT_1_8814B) +#define BIT_CLEAR_NOA_RPT_1_8814B(x) ((x) & (~BITS_NOA_RPT_1_8814B)) +#define BIT_GET_NOA_RPT_1_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_RPT_1_8814B) & BIT_MASK_NOA_RPT_1_8814B) +#define BIT_SET_NOA_RPT_1_8814B(x, v) \ + (BIT_CLEAR_NOA_RPT_1_8814B(x) | BIT_NOA_RPT_1_8814B(v)) + +/* 2 REG_NOA_REPORT_2_8814B */ + +#define BIT_SHIFT_NOA_RPT_2_8814B 0 +#define BIT_MASK_NOA_RPT_2_8814B 0xffffffffL +#define BIT_NOA_RPT_2_8814B(x) \ + (((x) & BIT_MASK_NOA_RPT_2_8814B) << BIT_SHIFT_NOA_RPT_2_8814B) +#define BITS_NOA_RPT_2_8814B \ + (BIT_MASK_NOA_RPT_2_8814B << BIT_SHIFT_NOA_RPT_2_8814B) +#define BIT_CLEAR_NOA_RPT_2_8814B(x) ((x) & (~BITS_NOA_RPT_2_8814B)) +#define BIT_GET_NOA_RPT_2_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_RPT_2_8814B) & BIT_MASK_NOA_RPT_2_8814B) +#define BIT_SET_NOA_RPT_2_8814B(x, v) \ + (BIT_CLEAR_NOA_RPT_2_8814B(x) | BIT_NOA_RPT_2_8814B(v)) + +/* 2 REG_NOA_REPORT_3_8814B */ + +#define BIT_SHIFT_NOA_RPT_3_8814B 0 +#define BIT_MASK_NOA_RPT_3_8814B 0xff +#define BIT_NOA_RPT_3_8814B(x) \ + (((x) & BIT_MASK_NOA_RPT_3_8814B) << BIT_SHIFT_NOA_RPT_3_8814B) +#define BITS_NOA_RPT_3_8814B \ + (BIT_MASK_NOA_RPT_3_8814B << BIT_SHIFT_NOA_RPT_3_8814B) +#define BIT_CLEAR_NOA_RPT_3_8814B(x) ((x) & (~BITS_NOA_RPT_3_8814B)) +#define BIT_GET_NOA_RPT_3_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_RPT_3_8814B) & BIT_MASK_NOA_RPT_3_8814B) +#define BIT_SET_NOA_RPT_3_8814B(x, v) \ + (BIT_CLEAR_NOA_RPT_3_8814B(x) | BIT_NOA_RPT_3_8814B(v)) + /* 2 REG_PWRBIT_SETTING_8814B */ -#define BIT_CLI3_PWRBIT_OW_EN_8814B BIT(7) -#define BIT_CLI3_PWR_ST_8814B BIT(6) -#define BIT_CLI2_PWRBIT_OW_EN_8814B BIT(5) -#define BIT_CLI2_PWR_ST_8814B BIT(4) -#define BIT_CLI1_PWRBIT_OW_EN_8814B BIT(3) -#define BIT_CLI1_PWR_ST_8814B BIT(2) -#define BIT_CLI0_PWRBIT_OW_EN_8814B BIT(1) -#define BIT_CLI0_PWR_ST_8814B BIT(0) - -/* 2 REG_WMAC_MU_BF_OPTION_8814B */ +#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(15) +#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(14) +#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(13) +#define BIT_CLI3_PWR_ST_V1_8814B BIT(12) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(11) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(10) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(9) +#define BIT_CLI2_PWR_ST_V1_8814B BIT(8) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(7) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(6) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(5) +#define BIT_CLI1_PWR_ST_V1_8814B BIT(4) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(3) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(2) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(1) +#define BIT_CLI0_PWR_ST_V1_8814B BIT(0) + +/* 2 REG_GENERAL_OPTION_8814B */ +#define BIT_PATTERN_MATCH_FIX_EN_8814B BIT(3) +#define BIT_TXSERV_FIELD_SEL_8814B BIT(2) +#define BIT_RXVHT_LEN_SEL_8814B BIT(1) +#define BIT_RXMIC_PROTECT_EN_8814B BIT(0) + +/* 2 REG_FWPHYFF_RCR_8814B */ +#define BIT_RCR2_AAMSDU_8814B BIT(25) +#define BIT_RCR2_CBSSID_BCN_8814B BIT(24) +#define BIT_RCR2_ACRC32_8814B BIT(23) +#define BIT_RCR2_TA_BCN_8814B BIT(22) +#define BIT_RCR2_CBSSID_DATA_8814B BIT(21) +#define BIT_RCR2_ADD3_8814B BIT(20) +#define BIT_RCR2_AB_8814B BIT(19) +#define BIT_RCR2_AM_8814B BIT(18) +#define BIT_RCR2_APM_8814B BIT(17) +#define BIT_RCR2_AAP_8814B BIT(16) +#define BIT_RCR1_AAMSDU_8814B BIT(9) +#define BIT_RCR1_CBSSID_BCN_8814B BIT(8) +#define BIT_RCR1_ACRC32_8814B BIT(7) +#define BIT_RCR1_TA_BCN_8814B BIT(6) +#define BIT_RCR1_CBSSID_DATA_8814B BIT(5) +#define BIT_RCR1_ADD3_8814B BIT(4) +#define BIT_RCR1_AB_8814B BIT(3) +#define BIT_RCR1_AM_8814B BIT(2) +#define BIT_RCR1_APM_8814B BIT(1) +#define BIT_RCR1_AAP_8814B BIT(0) + +/* 2 REG_ADDRCAM_WRITE_CONTENT_8814B */ + +#define BIT_SHIFT_ADDRCAM_WDATA_8814B 0 +#define BIT_MASK_ADDRCAM_WDATA_8814B 0xffffffffL +#define BIT_ADDRCAM_WDATA_8814B(x) \ + (((x) & BIT_MASK_ADDRCAM_WDATA_8814B) << BIT_SHIFT_ADDRCAM_WDATA_8814B) +#define BITS_ADDRCAM_WDATA_8814B \ + (BIT_MASK_ADDRCAM_WDATA_8814B << BIT_SHIFT_ADDRCAM_WDATA_8814B) +#define BIT_CLEAR_ADDRCAM_WDATA_8814B(x) ((x) & (~BITS_ADDRCAM_WDATA_8814B)) +#define BIT_GET_ADDRCAM_WDATA_8814B(x) \ + (((x) >> BIT_SHIFT_ADDRCAM_WDATA_8814B) & BIT_MASK_ADDRCAM_WDATA_8814B) +#define BIT_SET_ADDRCAM_WDATA_8814B(x, v) \ + (BIT_CLEAR_ADDRCAM_WDATA_8814B(x) | BIT_ADDRCAM_WDATA_8814B(v)) + +/* 2 REG_ADDRCAM_READ_CONTENT_8814B */ + +#define BIT_SHIFT_ADDRCAM_RDATA_8814B 0 +#define BIT_MASK_ADDRCAM_RDATA_8814B 0xffffffffL +#define BIT_ADDRCAM_RDATA_8814B(x) \ + (((x) & BIT_MASK_ADDRCAM_RDATA_8814B) << BIT_SHIFT_ADDRCAM_RDATA_8814B) +#define BITS_ADDRCAM_RDATA_8814B \ + (BIT_MASK_ADDRCAM_RDATA_8814B << BIT_SHIFT_ADDRCAM_RDATA_8814B) +#define BIT_CLEAR_ADDRCAM_RDATA_8814B(x) ((x) & (~BITS_ADDRCAM_RDATA_8814B)) +#define BIT_GET_ADDRCAM_RDATA_8814B(x) \ + (((x) >> BIT_SHIFT_ADDRCAM_RDATA_8814B) & BIT_MASK_ADDRCAM_RDATA_8814B) +#define BIT_SET_ADDRCAM_RDATA_8814B(x, v) \ + (BIT_CLEAR_ADDRCAM_RDATA_8814B(x) | BIT_ADDRCAM_RDATA_8814B(v)) + +/* 2 REG_ADDRCAM_CFG_8814B */ +#define BIT_ADDRCAM_POLL_8814B BIT(31) +#define BIT__ADDRCAM_WT_EN_8814B BIT(30) +#define BIT_CLRADDRCAM_8814B BIT(29) + +#define BIT_SHIFT__ADDRCAM_ADDR_8814B 8 +#define BIT_MASK__ADDRCAM_ADDR_8814B 0x3ff +#define BIT__ADDRCAM_ADDR_8814B(x) \ + (((x) & BIT_MASK__ADDRCAM_ADDR_8814B) << BIT_SHIFT__ADDRCAM_ADDR_8814B) +#define BITS__ADDRCAM_ADDR_8814B \ + (BIT_MASK__ADDRCAM_ADDR_8814B << BIT_SHIFT__ADDRCAM_ADDR_8814B) +#define BIT_CLEAR__ADDRCAM_ADDR_8814B(x) ((x) & (~BITS__ADDRCAM_ADDR_8814B)) +#define BIT_GET__ADDRCAM_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT__ADDRCAM_ADDR_8814B) & BIT_MASK__ADDRCAM_ADDR_8814B) +#define BIT_SET__ADDRCAM_ADDR_8814B(x, v) \ + (BIT_CLEAR__ADDRCAM_ADDR_8814B(x) | BIT__ADDRCAM_ADDR_8814B(v)) + +#define BIT_SHIFT_ADDRCAM_RANGE_8814B 0 +#define BIT_MASK_ADDRCAM_RANGE_8814B 0x7f +#define BIT_ADDRCAM_RANGE_8814B(x) \ + (((x) & BIT_MASK_ADDRCAM_RANGE_8814B) << BIT_SHIFT_ADDRCAM_RANGE_8814B) +#define BITS_ADDRCAM_RANGE_8814B \ + (BIT_MASK_ADDRCAM_RANGE_8814B << BIT_SHIFT_ADDRCAM_RANGE_8814B) +#define BIT_CLEAR_ADDRCAM_RANGE_8814B(x) ((x) & (~BITS_ADDRCAM_RANGE_8814B)) +#define BIT_GET_ADDRCAM_RANGE_8814B(x) \ + (((x) >> BIT_SHIFT_ADDRCAM_RANGE_8814B) & BIT_MASK_ADDRCAM_RANGE_8814B) +#define BIT_SET_ADDRCAM_RANGE_8814B(x, v) \ + (BIT_CLEAR_ADDRCAM_RANGE_8814B(x) | BIT_ADDRCAM_RANGE_8814B(v)) + +/* 2 REG_CSI_RRSR_8814B */ +#define BIT_CSI_LDPC_EN_8814B BIT(29) +#define BIT_CSI_STBC_EN_8814B BIT(28) + +#define BIT_SHIFT_CSI_RRSC_BITMAP_8814B 4 +#define BIT_MASK_CSI_RRSC_BITMAP_8814B 0xffffff +#define BIT_CSI_RRSC_BITMAP_8814B(x) \ + (((x) & BIT_MASK_CSI_RRSC_BITMAP_8814B) \ + << BIT_SHIFT_CSI_RRSC_BITMAP_8814B) +#define BITS_CSI_RRSC_BITMAP_8814B \ + (BIT_MASK_CSI_RRSC_BITMAP_8814B << BIT_SHIFT_CSI_RRSC_BITMAP_8814B) +#define BIT_CLEAR_CSI_RRSC_BITMAP_8814B(x) ((x) & (~BITS_CSI_RRSC_BITMAP_8814B)) +#define BIT_GET_CSI_RRSC_BITMAP_8814B(x) \ + (((x) >> BIT_SHIFT_CSI_RRSC_BITMAP_8814B) & \ + BIT_MASK_CSI_RRSC_BITMAP_8814B) +#define BIT_SET_CSI_RRSC_BITMAP_8814B(x, v) \ + (BIT_CLEAR_CSI_RRSC_BITMAP_8814B(x) | BIT_CSI_RRSC_BITMAP_8814B(v)) + +#define BIT_SHIFT_OFDM_LEN_TH_8814B 0 +#define BIT_MASK_OFDM_LEN_TH_8814B 0xf +#define BIT_OFDM_LEN_TH_8814B(x) \ + (((x) & BIT_MASK_OFDM_LEN_TH_8814B) << BIT_SHIFT_OFDM_LEN_TH_8814B) +#define BITS_OFDM_LEN_TH_8814B \ + (BIT_MASK_OFDM_LEN_TH_8814B << BIT_SHIFT_OFDM_LEN_TH_8814B) +#define BIT_CLEAR_OFDM_LEN_TH_8814B(x) ((x) & (~BITS_OFDM_LEN_TH_8814B)) +#define BIT_GET_OFDM_LEN_TH_8814B(x) \ + (((x) >> BIT_SHIFT_OFDM_LEN_TH_8814B) & BIT_MASK_OFDM_LEN_TH_8814B) +#define BIT_SET_OFDM_LEN_TH_8814B(x, v) \ + (BIT_CLEAR_OFDM_LEN_TH_8814B(x) | BIT_OFDM_LEN_TH_8814B(v)) + +/* 2 REG_MU_BF_OPTION_8814B */ #define BIT_WMAC_RESP_NONSTA1_DIS_8814B BIT(7) #define BIT_WMAC_TXMU_ACKPOLICY_EN_8814B BIT(6) #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B 4 #define BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B 0x3 -#define BIT_WMAC_TXMU_ACKPOLICY_8814B(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) -#define BIT_GET_WMAC_TXMU_ACKPOLICY_8814B(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B) - - +#define BIT_WMAC_TXMU_ACKPOLICY_8814B(x) \ + (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B) \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) +#define BITS_WMAC_TXMU_ACKPOLICY_8814B \ + (BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8814B(x) \ + ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8814B)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) & \ + BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B) +#define BIT_SET_WMAC_TXMU_ACKPOLICY_8814B(x, v) \ + (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8814B(x) | \ + BIT_WMAC_TXMU_ACKPOLICY_8814B(v)) #define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B 1 #define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B 0x7 -#define BIT_WMAC_MU_BFEE_PORT_SEL_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) -#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B) - +#define BIT_WMAC_MU_BFEE_PORT_SEL_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) +#define BITS_WMAC_MU_BFEE_PORT_SEL_8814B \ + (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8814B)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) & \ + BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8814B(x) | \ + BIT_WMAC_MU_BFEE_PORT_SEL_8814B(v)) #define BIT_WMAC_MU_BFEE_DIS_8814B BIT(0) @@ -10051,37 +23362,42 @@ #define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B 0 #define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B 0xff -#define BIT_WMAC_PAUSE_BB_CLR_TH_8814B(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) -#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8814B(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B) - - - -/* 2 REG_WMAC_MU_ARB_8814B */ -#define BIT_WMAC_ARB_HW_ADAPT_EN_8814B BIT(7) -#define BIT_WMAC_ARB_SW_EN_8814B BIT(6) - -#define BIT_SHIFT_WMAC_ARB_SW_STATE_8814B 0 -#define BIT_MASK_WMAC_ARB_SW_STATE_8814B 0x3f -#define BIT_WMAC_ARB_SW_STATE_8814B(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8814B) << BIT_SHIFT_WMAC_ARB_SW_STATE_8814B) -#define BIT_GET_WMAC_ARB_SW_STATE_8814B(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8814B) & BIT_MASK_WMAC_ARB_SW_STATE_8814B) - - +#define BIT_WMAC_PAUSE_BB_CLR_TH_8814B(x) \ + (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B) \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) +#define BITS_WMAC_PAUSE_BB_CLR_TH_8814B \ + (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8814B(x) \ + ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8814B)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) & \ + BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8814B(x, v) \ + (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8814B(x) | \ + BIT_WMAC_PAUSE_BB_CLR_TH_8814B(v)) + +/* 2 REG_WMAC_MULBK_BUF_8814B */ + +#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B 0 +#define BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B 0xff +#define BIT_WMAC_MULBK_PAGE_SIZE_8814B(x) \ + (((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B) \ + << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B) +#define BITS_WMAC_MULBK_PAGE_SIZE_8814B \ + (BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B \ + << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B) +#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8814B(x) \ + ((x) & (~BITS_WMAC_MULBK_PAGE_SIZE_8814B)) +#define BIT_GET_WMAC_MULBK_PAGE_SIZE_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B) & \ + BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B) +#define BIT_SET_WMAC_MULBK_PAGE_SIZE_8814B(x, v) \ + (BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8814B(x) | \ + BIT_WMAC_MULBK_PAGE_SIZE_8814B(v)) /* 2 REG_WMAC_MU_OPTION_8814B */ - -#define BIT_SHIFT_WMAC_MU_DBGSEL_8814B 5 -#define BIT_MASK_WMAC_MU_DBGSEL_8814B 0x3 -#define BIT_WMAC_MU_DBGSEL_8814B(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8814B) << BIT_SHIFT_WMAC_MU_DBGSEL_8814B) -#define BIT_GET_WMAC_MU_DBGSEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8814B) & BIT_MASK_WMAC_MU_DBGSEL_8814B) - - - -#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8814B 0 -#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8814B 0x1f -#define BIT_WMAC_MU_CPRD_TIMEOUT_8814B(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8814B) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8814B) -#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8814B) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8814B) - - +#define BIT_NOCHK_BFPOLL_BMP_8814B BIT(7) /* 2 REG_WMAC_MU_BF_CTL_8814B */ #define BIT_WMAC_INVLD_BFPRT_CHK_8814B BIT(15) @@ -10089,33 +23405,66 @@ #define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B 12 #define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B 0x3 -#define BIT_WMAC_MU_BFRPTSEG_SEL_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) -#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B) - - +#define BIT_WMAC_MU_BFRPTSEG_SEL_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B) \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) +#define BITS_WMAC_MU_BFRPTSEG_SEL_8814B \ + (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8814B)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) & \ + BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8814B(x) | \ + BIT_WMAC_MU_BFRPTSEG_SEL_8814B(v)) #define BIT_SHIFT_WMAC_MU_BF_MYAID_8814B 0 #define BIT_MASK_WMAC_MU_BF_MYAID_8814B 0xfff -#define BIT_WMAC_MU_BF_MYAID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8814B) << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) -#define BIT_GET_WMAC_MU_BF_MYAID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) & BIT_MASK_WMAC_MU_BF_MYAID_8814B) - - - -/* 2 REG_WMAC_MU_BIT_BFRPT_PARA_8814B */ - -#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8814B 12 -#define BIT_MASK_BFRPT_PARA_USERID_SEL_8814B 0x7 -#define BIT_BFRPT_PARA_USERID_SEL_8814B(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8814B) << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8814B) -#define BIT_GET_BFRPT_PARA_USERID_SEL_8814B(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8814B) & BIT_MASK_BFRPT_PARA_USERID_SEL_8814B) - - - -#define BIT_SHIFT_BFRPT_PARA_8814B 0 -#define BIT_MASK_BFRPT_PARA_8814B 0xfff -#define BIT_BFRPT_PARA_8814B(x) (((x) & BIT_MASK_BFRPT_PARA_8814B) << BIT_SHIFT_BFRPT_PARA_8814B) -#define BIT_GET_BFRPT_PARA_8814B(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8814B) & BIT_MASK_BFRPT_PARA_8814B) - - +#define BIT_WMAC_MU_BF_MYAID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8814B) \ + << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) +#define BITS_WMAC_MU_BF_MYAID_8814B \ + (BIT_MASK_WMAC_MU_BF_MYAID_8814B << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BF_MYAID_8814B)) +#define BIT_GET_WMAC_MU_BF_MYAID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) & \ + BIT_MASK_WMAC_MU_BF_MYAID_8814B) +#define BIT_SET_WMAC_MU_BF_MYAID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BF_MYAID_8814B(x) | BIT_WMAC_MU_BF_MYAID_8814B(v)) + +/* 2 REG_WMAC_MU_BFRPT_PARA_8814B */ + +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B 13 +#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B 0x7 +#define BIT_BFRPT_PARA_USERID_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B) \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B) +#define BITS_BFRPT_PARA_USERID_SEL_V1_8814B \ + (BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8814B(x) \ + ((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1_8814B)) +#define BIT_GET_BFRPT_PARA_USERID_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B) & \ + BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B) +#define BIT_SET_BFRPT_PARA_USERID_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8814B(x) | \ + BIT_BFRPT_PARA_USERID_SEL_V1_8814B(v)) + +#define BIT_SHIFT_BFRPT_PARA_V1_8814B 0 +#define BIT_MASK_BFRPT_PARA_V1_8814B 0x1fff +#define BIT_BFRPT_PARA_V1_8814B(x) \ + (((x) & BIT_MASK_BFRPT_PARA_V1_8814B) << BIT_SHIFT_BFRPT_PARA_V1_8814B) +#define BITS_BFRPT_PARA_V1_8814B \ + (BIT_MASK_BFRPT_PARA_V1_8814B << BIT_SHIFT_BFRPT_PARA_V1_8814B) +#define BIT_CLEAR_BFRPT_PARA_V1_8814B(x) ((x) & (~BITS_BFRPT_PARA_V1_8814B)) +#define BIT_GET_BFRPT_PARA_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_V1_8814B) & BIT_MASK_BFRPT_PARA_V1_8814B) +#define BIT_SET_BFRPT_PARA_V1_8814B(x, v) \ + (BIT_CLEAR_BFRPT_PARA_V1_8814B(x) | BIT_BFRPT_PARA_V1_8814B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B */ #define BIT_STATUS_BFEE2_8814B BIT(10) @@ -10123,10 +23472,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B 0 #define BIT_MASK_WMAC_MU_BFEE2_AID_8814B 0x1ff -#define BIT_WMAC_MU_BFEE2_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) -#define BIT_GET_WMAC_MU_BFEE2_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) & BIT_MASK_WMAC_MU_BFEE2_AID_8814B) - - +#define BIT_WMAC_MU_BFEE2_AID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) +#define BITS_WMAC_MU_BFEE2_AID_8814B \ + (BIT_MASK_WMAC_MU_BFEE2_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE2_AID_8814B)) +#define BIT_GET_WMAC_MU_BFEE2_AID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) & \ + BIT_MASK_WMAC_MU_BFEE2_AID_8814B) +#define BIT_SET_WMAC_MU_BFEE2_AID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE2_AID_8814B(x) | BIT_WMAC_MU_BFEE2_AID_8814B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B */ #define BIT_STATUS_BFEE3_8814B BIT(10) @@ -10134,10 +23491,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B 0 #define BIT_MASK_WMAC_MU_BFEE3_AID_8814B 0x1ff -#define BIT_WMAC_MU_BFEE3_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) -#define BIT_GET_WMAC_MU_BFEE3_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) & BIT_MASK_WMAC_MU_BFEE3_AID_8814B) - - +#define BIT_WMAC_MU_BFEE3_AID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) +#define BITS_WMAC_MU_BFEE3_AID_8814B \ + (BIT_MASK_WMAC_MU_BFEE3_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE3_AID_8814B)) +#define BIT_GET_WMAC_MU_BFEE3_AID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) & \ + BIT_MASK_WMAC_MU_BFEE3_AID_8814B) +#define BIT_SET_WMAC_MU_BFEE3_AID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE3_AID_8814B(x) | BIT_WMAC_MU_BFEE3_AID_8814B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B */ #define BIT_STATUS_BFEE4_8814B BIT(10) @@ -10145,10 +23510,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B 0 #define BIT_MASK_WMAC_MU_BFEE4_AID_8814B 0x1ff -#define BIT_WMAC_MU_BFEE4_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) -#define BIT_GET_WMAC_MU_BFEE4_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) & BIT_MASK_WMAC_MU_BFEE4_AID_8814B) - - +#define BIT_WMAC_MU_BFEE4_AID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) +#define BITS_WMAC_MU_BFEE4_AID_8814B \ + (BIT_MASK_WMAC_MU_BFEE4_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE4_AID_8814B)) +#define BIT_GET_WMAC_MU_BFEE4_AID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) & \ + BIT_MASK_WMAC_MU_BFEE4_AID_8814B) +#define BIT_SET_WMAC_MU_BFEE4_AID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE4_AID_8814B(x) | BIT_WMAC_MU_BFEE4_AID_8814B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8814B */ #define BIT_BIT_STATUS_BFEE5_8814B BIT(10) @@ -10156,10 +23529,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B 0 #define BIT_MASK_WMAC_MU_BFEE5_AID_8814B 0x1ff -#define BIT_WMAC_MU_BFEE5_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) -#define BIT_GET_WMAC_MU_BFEE5_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) & BIT_MASK_WMAC_MU_BFEE5_AID_8814B) - - +#define BIT_WMAC_MU_BFEE5_AID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) +#define BITS_WMAC_MU_BFEE5_AID_8814B \ + (BIT_MASK_WMAC_MU_BFEE5_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE5_AID_8814B)) +#define BIT_GET_WMAC_MU_BFEE5_AID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) & \ + BIT_MASK_WMAC_MU_BFEE5_AID_8814B) +#define BIT_SET_WMAC_MU_BFEE5_AID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE5_AID_8814B(x) | BIT_WMAC_MU_BFEE5_AID_8814B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8814B */ #define BIT_STATUS_BFEE6_8814B BIT(10) @@ -10167,124 +23548,318 @@ #define BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B 0 #define BIT_MASK_WMAC_MU_BFEE6_AID_8814B 0x1ff -#define BIT_WMAC_MU_BFEE6_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) -#define BIT_GET_WMAC_MU_BFEE6_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) & BIT_MASK_WMAC_MU_BFEE6_AID_8814B) - - +#define BIT_WMAC_MU_BFEE6_AID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) +#define BITS_WMAC_MU_BFEE6_AID_8814B \ + (BIT_MASK_WMAC_MU_BFEE6_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE6_AID_8814B)) +#define BIT_GET_WMAC_MU_BFEE6_AID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) & \ + BIT_MASK_WMAC_MU_BFEE6_AID_8814B) +#define BIT_SET_WMAC_MU_BFEE6_AID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE6_AID_8814B(x) | BIT_WMAC_MU_BFEE6_AID_8814B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B */ -#define BIT_BIT_STATUS_BFEE4_8814B BIT(10) +#define BIT_STATUS_BFEE7_8814B BIT(10) #define BIT_WMAC_MU_BFEE7_EN_8814B BIT(9) #define BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B 0 #define BIT_MASK_WMAC_MU_BFEE7_AID_8814B 0x1ff -#define BIT_WMAC_MU_BFEE7_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) -#define BIT_GET_WMAC_MU_BFEE7_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) & BIT_MASK_WMAC_MU_BFEE7_AID_8814B) - - +#define BIT_WMAC_MU_BFEE7_AID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) +#define BITS_WMAC_MU_BFEE7_AID_8814B \ + (BIT_MASK_WMAC_MU_BFEE7_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE7_AID_8814B)) +#define BIT_GET_WMAC_MU_BFEE7_AID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) & \ + BIT_MASK_WMAC_MU_BFEE7_AID_8814B) +#define BIT_SET_WMAC_MU_BFEE7_AID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE7_AID_8814B(x) | BIT_WMAC_MU_BFEE7_AID_8814B(v)) /* 2 REG_WMAC_BB_STOP_RX_COUNTER_8814B */ #define BIT_RST_ALL_COUNTER_8814B BIT(31) #define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B 16 #define BIT_MASK_ABORT_RX_VBON_COUNTER_8814B 0xff -#define BIT_ABORT_RX_VBON_COUNTER_8814B(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8814B) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) -#define BIT_GET_ABORT_RX_VBON_COUNTER_8814B(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) & BIT_MASK_ABORT_RX_VBON_COUNTER_8814B) - - +#define BIT_ABORT_RX_VBON_COUNTER_8814B(x) \ + (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8814B) \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) +#define BITS_ABORT_RX_VBON_COUNTER_8814B \ + (BIT_MASK_ABORT_RX_VBON_COUNTER_8814B \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8814B(x) \ + ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8814B)) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8814B(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) & \ + BIT_MASK_ABORT_RX_VBON_COUNTER_8814B) +#define BIT_SET_ABORT_RX_VBON_COUNTER_8814B(x, v) \ + (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8814B(x) | \ + BIT_ABORT_RX_VBON_COUNTER_8814B(v)) #define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B 8 #define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B 0xff -#define BIT_ABORT_RX_RDRDY_COUNTER_8814B(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) -#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8814B(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B) - - +#define BIT_ABORT_RX_RDRDY_COUNTER_8814B(x) \ + (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B) \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) +#define BITS_ABORT_RX_RDRDY_COUNTER_8814B \ + (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8814B(x) \ + ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8814B)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8814B(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) & \ + BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8814B(x, v) \ + (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8814B(x) | \ + BIT_ABORT_RX_RDRDY_COUNTER_8814B(v)) #define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B 0 #define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B 0xff -#define BIT_VBON_EARLY_FALLING_COUNTER_8814B(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) -#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8814B(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B) - - +#define BIT_VBON_EARLY_FALLING_COUNTER_8814B(x) \ + (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B) \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) +#define BITS_VBON_EARLY_FALLING_COUNTER_8814B \ + (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8814B(x) \ + ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8814B)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8814B(x) \ + (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) & \ + BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8814B(x, v) \ + (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8814B(x) | \ + BIT_VBON_EARLY_FALLING_COUNTER_8814B(v)) /* 2 REG_WMAC_PLCP_MONITOR_8814B */ #define BIT_WMAC_PLCP_TRX_SEL_8814B BIT(31) #define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B 28 #define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B 0x7 -#define BIT_WMAC_PLCP_RDSIG_SEL_8814B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) -#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B) - - +#define BIT_WMAC_PLCP_RDSIG_SEL_8814B(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) +#define BITS_WMAC_PLCP_RDSIG_SEL_8814B \ + (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8814B(x) \ + ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8814B)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) & \ + BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8814B(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8814B(x) | \ + BIT_WMAC_PLCP_RDSIG_SEL_8814B(v)) #define BIT_SHIFT_WMAC_RATE_IDX_8814B 24 #define BIT_MASK_WMAC_RATE_IDX_8814B 0xf -#define BIT_WMAC_RATE_IDX_8814B(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8814B) << BIT_SHIFT_WMAC_RATE_IDX_8814B) -#define BIT_GET_WMAC_RATE_IDX_8814B(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8814B) & BIT_MASK_WMAC_RATE_IDX_8814B) - - +#define BIT_WMAC_RATE_IDX_8814B(x) \ + (((x) & BIT_MASK_WMAC_RATE_IDX_8814B) << BIT_SHIFT_WMAC_RATE_IDX_8814B) +#define BITS_WMAC_RATE_IDX_8814B \ + (BIT_MASK_WMAC_RATE_IDX_8814B << BIT_SHIFT_WMAC_RATE_IDX_8814B) +#define BIT_CLEAR_WMAC_RATE_IDX_8814B(x) ((x) & (~BITS_WMAC_RATE_IDX_8814B)) +#define BIT_GET_WMAC_RATE_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8814B) & BIT_MASK_WMAC_RATE_IDX_8814B) +#define BIT_SET_WMAC_RATE_IDX_8814B(x, v) \ + (BIT_CLEAR_WMAC_RATE_IDX_8814B(x) | BIT_WMAC_RATE_IDX_8814B(v)) #define BIT_SHIFT_WMAC_PLCP_RDSIG_8814B 0 #define BIT_MASK_WMAC_PLCP_RDSIG_8814B 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8814B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) -#define BIT_GET_WMAC_PLCP_RDSIG_8814B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) - +#define BIT_WMAC_PLCP_RDSIG_8814B(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) +#define BITS_WMAC_PLCP_RDSIG_8814B \ + (BIT_MASK_WMAC_PLCP_RDSIG_8814B << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8814B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8814B)) +#define BIT_GET_WMAC_PLCP_RDSIG_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8814B) +#define BIT_SET_WMAC_PLCP_RDSIG_8814B(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8814B(x) | BIT_WMAC_PLCP_RDSIG_8814B(v)) + +/* 2 REG_WMAC_DEBUG_PORT_8814B */ + +#define BIT_SHIFT_WMAC_DEBUG_PORT_8814B 0 +#define BIT_MASK_WMAC_DEBUG_PORT_8814B 0xffffffffL +#define BIT_WMAC_DEBUG_PORT_8814B(x) \ + (((x) & BIT_MASK_WMAC_DEBUG_PORT_8814B) \ + << BIT_SHIFT_WMAC_DEBUG_PORT_8814B) +#define BITS_WMAC_DEBUG_PORT_8814B \ + (BIT_MASK_WMAC_DEBUG_PORT_8814B << BIT_SHIFT_WMAC_DEBUG_PORT_8814B) +#define BIT_CLEAR_WMAC_DEBUG_PORT_8814B(x) ((x) & (~BITS_WMAC_DEBUG_PORT_8814B)) +#define BIT_GET_WMAC_DEBUG_PORT_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_DEBUG_PORT_8814B) & \ + BIT_MASK_WMAC_DEBUG_PORT_8814B) +#define BIT_SET_WMAC_DEBUG_PORT_8814B(x, v) \ + (BIT_CLEAR_WMAC_DEBUG_PORT_8814B(x) | BIT_WMAC_DEBUG_PORT_8814B(v)) +/* 2 REG_RSVD_8814B */ -/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8814B */ -#define BIT_WMAC_MUTX_IDX_8814B BIT(24) +/* 2 REG_TRANSMIT_ADDRSS_0_8814B (TA0 REGISTER) */ -#define BIT_SHIFT_WMAC_PLCP_RDSIG_8814B 0 -#define BIT_MASK_WMAC_PLCP_RDSIG_8814B 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8814B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) -#define BIT_GET_WMAC_PLCP_RDSIG_8814B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) +#define BIT_SHIFT_TA0_V1_8814B 0 +#define BIT_MASK_TA0_V1_8814B 0xffffffffL +#define BIT_TA0_V1_8814B(x) \ + (((x) & BIT_MASK_TA0_V1_8814B) << BIT_SHIFT_TA0_V1_8814B) +#define BITS_TA0_V1_8814B (BIT_MASK_TA0_V1_8814B << BIT_SHIFT_TA0_V1_8814B) +#define BIT_CLEAR_TA0_V1_8814B(x) ((x) & (~BITS_TA0_V1_8814B)) +#define BIT_GET_TA0_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA0_V1_8814B) & BIT_MASK_TA0_V1_8814B) +#define BIT_SET_TA0_V1_8814B(x, v) \ + (BIT_CLEAR_TA0_V1_8814B(x) | BIT_TA0_V1_8814B(v)) + +/* 2 REG_TRANSMIT_ADDRSS_0_H_8814B (TA0 REGISTER) */ + +#define BIT_SHIFT_TA0_H_V1_8814B 0 +#define BIT_MASK_TA0_H_V1_8814B 0xffff +#define BIT_TA0_H_V1_8814B(x) \ + (((x) & BIT_MASK_TA0_H_V1_8814B) << BIT_SHIFT_TA0_H_V1_8814B) +#define BITS_TA0_H_V1_8814B \ + (BIT_MASK_TA0_H_V1_8814B << BIT_SHIFT_TA0_H_V1_8814B) +#define BIT_CLEAR_TA0_H_V1_8814B(x) ((x) & (~BITS_TA0_H_V1_8814B)) +#define BIT_GET_TA0_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA0_H_V1_8814B) & BIT_MASK_TA0_H_V1_8814B) +#define BIT_SET_TA0_H_V1_8814B(x, v) \ + (BIT_CLEAR_TA0_H_V1_8814B(x) | BIT_TA0_H_V1_8814B(v)) +/* 2 REG_TRANSMIT_ADDRSS_1_8814B (TA1 REGISTER) */ +#define BIT_SHIFT_TA1_V1_8814B 0 +#define BIT_MASK_TA1_V1_8814B 0xffffffffL +#define BIT_TA1_V1_8814B(x) \ + (((x) & BIT_MASK_TA1_V1_8814B) << BIT_SHIFT_TA1_V1_8814B) +#define BITS_TA1_V1_8814B (BIT_MASK_TA1_V1_8814B << BIT_SHIFT_TA1_V1_8814B) +#define BIT_CLEAR_TA1_V1_8814B(x) ((x) & (~BITS_TA1_V1_8814B)) +#define BIT_GET_TA1_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA1_V1_8814B) & BIT_MASK_TA1_V1_8814B) +#define BIT_SET_TA1_V1_8814B(x, v) \ + (BIT_CLEAR_TA1_V1_8814B(x) | BIT_TA1_V1_8814B(v)) + +/* 2 REG_TRANSMIT_ADDRSS_1_H_8814B (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_H_V1_8814B 0 +#define BIT_MASK_TA1_H_V1_8814B 0xffff +#define BIT_TA1_H_V1_8814B(x) \ + (((x) & BIT_MASK_TA1_H_V1_8814B) << BIT_SHIFT_TA1_H_V1_8814B) +#define BITS_TA1_H_V1_8814B \ + (BIT_MASK_TA1_H_V1_8814B << BIT_SHIFT_TA1_H_V1_8814B) +#define BIT_CLEAR_TA1_H_V1_8814B(x) ((x) & (~BITS_TA1_H_V1_8814B)) +#define BIT_GET_TA1_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA1_H_V1_8814B) & BIT_MASK_TA1_H_V1_8814B) +#define BIT_SET_TA1_H_V1_8814B(x, v) \ + (BIT_CLEAR_TA1_H_V1_8814B(x) | BIT_TA1_H_V1_8814B(v)) -/* 2 REG_TRANSMIT_ADDRSS_0_8814B (TA0 REGISTER) */ +/* 2 REG_TRANSMIT_ADDRSS_2_8814B (TA2 REGISTER) */ -#define BIT_SHIFT_TA0_8814B 0 -#define BIT_MASK_TA0_8814B 0xffffffffffffL -#define BIT_TA0_8814B(x) (((x) & BIT_MASK_TA0_8814B) << BIT_SHIFT_TA0_8814B) -#define BIT_GET_TA0_8814B(x) (((x) >> BIT_SHIFT_TA0_8814B) & BIT_MASK_TA0_8814B) +#define BIT_SHIFT_TA2_V1_8814B 0 +#define BIT_MASK_TA2_V1_8814B 0xffffffffL +#define BIT_TA2_V1_8814B(x) \ + (((x) & BIT_MASK_TA2_V1_8814B) << BIT_SHIFT_TA2_V1_8814B) +#define BITS_TA2_V1_8814B (BIT_MASK_TA2_V1_8814B << BIT_SHIFT_TA2_V1_8814B) +#define BIT_CLEAR_TA2_V1_8814B(x) ((x) & (~BITS_TA2_V1_8814B)) +#define BIT_GET_TA2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA2_V1_8814B) & BIT_MASK_TA2_V1_8814B) +#define BIT_SET_TA2_V1_8814B(x, v) \ + (BIT_CLEAR_TA2_V1_8814B(x) | BIT_TA2_V1_8814B(v)) + +/* 2 REG_TRANSMIT_ADDRSS_2_H_8814B (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_H_V1_8814B 0 +#define BIT_MASK_TA2_H_V1_8814B 0xffff +#define BIT_TA2_H_V1_8814B(x) \ + (((x) & BIT_MASK_TA2_H_V1_8814B) << BIT_SHIFT_TA2_H_V1_8814B) +#define BITS_TA2_H_V1_8814B \ + (BIT_MASK_TA2_H_V1_8814B << BIT_SHIFT_TA2_H_V1_8814B) +#define BIT_CLEAR_TA2_H_V1_8814B(x) ((x) & (~BITS_TA2_H_V1_8814B)) +#define BIT_GET_TA2_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA2_H_V1_8814B) & BIT_MASK_TA2_H_V1_8814B) +#define BIT_SET_TA2_H_V1_8814B(x, v) \ + (BIT_CLEAR_TA2_H_V1_8814B(x) | BIT_TA2_H_V1_8814B(v)) +/* 2 REG_TRANSMIT_ADDRSS_3_8814B (TA3 REGISTER) */ +#define BIT_SHIFT_TA2_V1_8814B 0 +#define BIT_MASK_TA2_V1_8814B 0xffffffffL +#define BIT_TA2_V1_8814B(x) \ + (((x) & BIT_MASK_TA2_V1_8814B) << BIT_SHIFT_TA2_V1_8814B) +#define BITS_TA2_V1_8814B (BIT_MASK_TA2_V1_8814B << BIT_SHIFT_TA2_V1_8814B) +#define BIT_CLEAR_TA2_V1_8814B(x) ((x) & (~BITS_TA2_V1_8814B)) +#define BIT_GET_TA2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA2_V1_8814B) & BIT_MASK_TA2_V1_8814B) +#define BIT_SET_TA2_V1_8814B(x, v) \ + (BIT_CLEAR_TA2_V1_8814B(x) | BIT_TA2_V1_8814B(v)) + +/* 2 REG_TRANSMIT_ADDRSS_3_H_8814B (TA3 REGISTER) */ + +#define BIT_SHIFT_TA3_H_V1_8814B 0 +#define BIT_MASK_TA3_H_V1_8814B 0xffff +#define BIT_TA3_H_V1_8814B(x) \ + (((x) & BIT_MASK_TA3_H_V1_8814B) << BIT_SHIFT_TA3_H_V1_8814B) +#define BITS_TA3_H_V1_8814B \ + (BIT_MASK_TA3_H_V1_8814B << BIT_SHIFT_TA3_H_V1_8814B) +#define BIT_CLEAR_TA3_H_V1_8814B(x) ((x) & (~BITS_TA3_H_V1_8814B)) +#define BIT_GET_TA3_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA3_H_V1_8814B) & BIT_MASK_TA3_H_V1_8814B) +#define BIT_SET_TA3_H_V1_8814B(x, v) \ + (BIT_CLEAR_TA3_H_V1_8814B(x) | BIT_TA3_H_V1_8814B(v)) -/* 2 REG_TRANSMIT_ADDRSS_1_8814B (TA1 REGISTER) */ +/* 2 REG_TRANSMIT_ADDRSS_4_8814B (TA4 REGISTER) */ -#define BIT_SHIFT_TA1_8814B 0 -#define BIT_MASK_TA1_8814B 0xffffffffffffL -#define BIT_TA1_8814B(x) (((x) & BIT_MASK_TA1_8814B) << BIT_SHIFT_TA1_8814B) -#define BIT_GET_TA1_8814B(x) (((x) >> BIT_SHIFT_TA1_8814B) & BIT_MASK_TA1_8814B) +#define BIT_SHIFT_TA4_V1_8814B 0 +#define BIT_MASK_TA4_V1_8814B 0xffffffffL +#define BIT_TA4_V1_8814B(x) \ + (((x) & BIT_MASK_TA4_V1_8814B) << BIT_SHIFT_TA4_V1_8814B) +#define BITS_TA4_V1_8814B (BIT_MASK_TA4_V1_8814B << BIT_SHIFT_TA4_V1_8814B) +#define BIT_CLEAR_TA4_V1_8814B(x) ((x) & (~BITS_TA4_V1_8814B)) +#define BIT_GET_TA4_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA4_V1_8814B) & BIT_MASK_TA4_V1_8814B) +#define BIT_SET_TA4_V1_8814B(x, v) \ + (BIT_CLEAR_TA4_V1_8814B(x) | BIT_TA4_V1_8814B(v)) + +/* 2 REG_TRANSMIT_ADDRSS_4_H_8814B (TA4 REGISTER) */ + +#define BIT_SHIFT_TA4_H_V1_8814B 0 +#define BIT_MASK_TA4_H_V1_8814B 0xffff +#define BIT_TA4_H_V1_8814B(x) \ + (((x) & BIT_MASK_TA4_H_V1_8814B) << BIT_SHIFT_TA4_H_V1_8814B) +#define BITS_TA4_H_V1_8814B \ + (BIT_MASK_TA4_H_V1_8814B << BIT_SHIFT_TA4_H_V1_8814B) +#define BIT_CLEAR_TA4_H_V1_8814B(x) ((x) & (~BITS_TA4_H_V1_8814B)) +#define BIT_GET_TA4_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA4_H_V1_8814B) & BIT_MASK_TA4_H_V1_8814B) +#define BIT_SET_TA4_H_V1_8814B(x, v) \ + (BIT_CLEAR_TA4_H_V1_8814B(x) | BIT_TA4_H_V1_8814B(v)) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ -/* 2 REG_TRANSMIT_ADDRSS_2_8814B (TA2 REGISTER) */ +/* 2 REG_RSVD_8814B */ -#define BIT_SHIFT_TA2_8814B 0 -#define BIT_MASK_TA2_8814B 0xffffffffffffL -#define BIT_TA2_8814B(x) (((x) & BIT_MASK_TA2_8814B) << BIT_SHIFT_TA2_8814B) -#define BIT_GET_TA2_8814B(x) (((x) >> BIT_SHIFT_TA2_8814B) & BIT_MASK_TA2_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ -/* 2 REG_TRANSMIT_ADDRSS_3_8814B (TA3 REGISTER) */ +/* 2 REG_RSVD_8814B */ -#define BIT_SHIFT_TA3_8814B 0 -#define BIT_MASK_TA3_8814B 0xffffffffffffL -#define BIT_TA3_8814B(x) (((x) & BIT_MASK_TA3_8814B) << BIT_SHIFT_TA3_8814B) -#define BIT_GET_TA3_8814B(x) (((x) >> BIT_SHIFT_TA3_8814B) & BIT_MASK_TA3_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ -/* 2 REG_TRANSMIT_ADDRSS_4_8814B (TA4 REGISTER) */ +/* 2 REG_RSVD_8814B */ -#define BIT_SHIFT_TA4_8814B 0 -#define BIT_MASK_TA4_8814B 0xffffffffffffL -#define BIT_TA4_8814B(x) (((x) & BIT_MASK_TA4_8814B) << BIT_SHIFT_TA4_8814B) -#define BIT_GET_TA4_8814B(x) (((x) >> BIT_SHIFT_TA4_8814B) & BIT_MASK_TA4_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ /* 2 REG_NOT_VALID_8814B */ @@ -10292,62 +23867,98 @@ #define BIT_SHIFT_MACID1_0_8814B 0 #define BIT_MASK_MACID1_0_8814B 0xffffffffL -#define BIT_MACID1_0_8814B(x) (((x) & BIT_MASK_MACID1_0_8814B) << BIT_SHIFT_MACID1_0_8814B) -#define BIT_GET_MACID1_0_8814B(x) (((x) >> BIT_SHIFT_MACID1_0_8814B) & BIT_MASK_MACID1_0_8814B) - - +#define BIT_MACID1_0_8814B(x) \ + (((x) & BIT_MASK_MACID1_0_8814B) << BIT_SHIFT_MACID1_0_8814B) +#define BITS_MACID1_0_8814B \ + (BIT_MASK_MACID1_0_8814B << BIT_SHIFT_MACID1_0_8814B) +#define BIT_CLEAR_MACID1_0_8814B(x) ((x) & (~BITS_MACID1_0_8814B)) +#define BIT_GET_MACID1_0_8814B(x) \ + (((x) >> BIT_SHIFT_MACID1_0_8814B) & BIT_MASK_MACID1_0_8814B) +#define BIT_SET_MACID1_0_8814B(x, v) \ + (BIT_CLEAR_MACID1_0_8814B(x) | BIT_MACID1_0_8814B(v)) /* 2 REG_MACID1_1_8814B */ #define BIT_SHIFT_MACID1_1_8814B 0 #define BIT_MASK_MACID1_1_8814B 0xffff -#define BIT_MACID1_1_8814B(x) (((x) & BIT_MASK_MACID1_1_8814B) << BIT_SHIFT_MACID1_1_8814B) -#define BIT_GET_MACID1_1_8814B(x) (((x) >> BIT_SHIFT_MACID1_1_8814B) & BIT_MASK_MACID1_1_8814B) - - +#define BIT_MACID1_1_8814B(x) \ + (((x) & BIT_MASK_MACID1_1_8814B) << BIT_SHIFT_MACID1_1_8814B) +#define BITS_MACID1_1_8814B \ + (BIT_MASK_MACID1_1_8814B << BIT_SHIFT_MACID1_1_8814B) +#define BIT_CLEAR_MACID1_1_8814B(x) ((x) & (~BITS_MACID1_1_8814B)) +#define BIT_GET_MACID1_1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID1_1_8814B) & BIT_MASK_MACID1_1_8814B) +#define BIT_SET_MACID1_1_8814B(x, v) \ + (BIT_CLEAR_MACID1_1_8814B(x) | BIT_MACID1_1_8814B(v)) /* 2 REG_BSSID1_8814B */ #define BIT_SHIFT_BSSID1_0_8814B 0 #define BIT_MASK_BSSID1_0_8814B 0xffffffffL -#define BIT_BSSID1_0_8814B(x) (((x) & BIT_MASK_BSSID1_0_8814B) << BIT_SHIFT_BSSID1_0_8814B) -#define BIT_GET_BSSID1_0_8814B(x) (((x) >> BIT_SHIFT_BSSID1_0_8814B) & BIT_MASK_BSSID1_0_8814B) - - +#define BIT_BSSID1_0_8814B(x) \ + (((x) & BIT_MASK_BSSID1_0_8814B) << BIT_SHIFT_BSSID1_0_8814B) +#define BITS_BSSID1_0_8814B \ + (BIT_MASK_BSSID1_0_8814B << BIT_SHIFT_BSSID1_0_8814B) +#define BIT_CLEAR_BSSID1_0_8814B(x) ((x) & (~BITS_BSSID1_0_8814B)) +#define BIT_GET_BSSID1_0_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID1_0_8814B) & BIT_MASK_BSSID1_0_8814B) +#define BIT_SET_BSSID1_0_8814B(x, v) \ + (BIT_CLEAR_BSSID1_0_8814B(x) | BIT_BSSID1_0_8814B(v)) /* 2 REG_BSSID1_1_8814B */ #define BIT_SHIFT_BSSID1_1_8814B 0 #define BIT_MASK_BSSID1_1_8814B 0xffff -#define BIT_BSSID1_1_8814B(x) (((x) & BIT_MASK_BSSID1_1_8814B) << BIT_SHIFT_BSSID1_1_8814B) -#define BIT_GET_BSSID1_1_8814B(x) (((x) >> BIT_SHIFT_BSSID1_1_8814B) & BIT_MASK_BSSID1_1_8814B) - - +#define BIT_BSSID1_1_8814B(x) \ + (((x) & BIT_MASK_BSSID1_1_8814B) << BIT_SHIFT_BSSID1_1_8814B) +#define BITS_BSSID1_1_8814B \ + (BIT_MASK_BSSID1_1_8814B << BIT_SHIFT_BSSID1_1_8814B) +#define BIT_CLEAR_BSSID1_1_8814B(x) ((x) & (~BITS_BSSID1_1_8814B)) +#define BIT_GET_BSSID1_1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID1_1_8814B) & BIT_MASK_BSSID1_1_8814B) +#define BIT_SET_BSSID1_1_8814B(x, v) \ + (BIT_CLEAR_BSSID1_1_8814B(x) | BIT_BSSID1_1_8814B(v)) /* 2 REG_BCN_PSR_RPT1_8814B */ #define BIT_SHIFT_DTIM_CNT1_8814B 24 #define BIT_MASK_DTIM_CNT1_8814B 0xff -#define BIT_DTIM_CNT1_8814B(x) (((x) & BIT_MASK_DTIM_CNT1_8814B) << BIT_SHIFT_DTIM_CNT1_8814B) -#define BIT_GET_DTIM_CNT1_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8814B) & BIT_MASK_DTIM_CNT1_8814B) - - +#define BIT_DTIM_CNT1_8814B(x) \ + (((x) & BIT_MASK_DTIM_CNT1_8814B) << BIT_SHIFT_DTIM_CNT1_8814B) +#define BITS_DTIM_CNT1_8814B \ + (BIT_MASK_DTIM_CNT1_8814B << BIT_SHIFT_DTIM_CNT1_8814B) +#define BIT_CLEAR_DTIM_CNT1_8814B(x) ((x) & (~BITS_DTIM_CNT1_8814B)) +#define BIT_GET_DTIM_CNT1_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT1_8814B) & BIT_MASK_DTIM_CNT1_8814B) +#define BIT_SET_DTIM_CNT1_8814B(x, v) \ + (BIT_CLEAR_DTIM_CNT1_8814B(x) | BIT_DTIM_CNT1_8814B(v)) #define BIT_SHIFT_DTIM_PERIOD1_8814B 16 #define BIT_MASK_DTIM_PERIOD1_8814B 0xff -#define BIT_DTIM_PERIOD1_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD1_8814B) << BIT_SHIFT_DTIM_PERIOD1_8814B) -#define BIT_GET_DTIM_PERIOD1_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8814B) & BIT_MASK_DTIM_PERIOD1_8814B) - +#define BIT_DTIM_PERIOD1_8814B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD1_8814B) << BIT_SHIFT_DTIM_PERIOD1_8814B) +#define BITS_DTIM_PERIOD1_8814B \ + (BIT_MASK_DTIM_PERIOD1_8814B << BIT_SHIFT_DTIM_PERIOD1_8814B) +#define BIT_CLEAR_DTIM_PERIOD1_8814B(x) ((x) & (~BITS_DTIM_PERIOD1_8814B)) +#define BIT_GET_DTIM_PERIOD1_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD1_8814B) & BIT_MASK_DTIM_PERIOD1_8814B) +#define BIT_SET_DTIM_PERIOD1_8814B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD1_8814B(x) | BIT_DTIM_PERIOD1_8814B(v)) #define BIT_DTIM1_8814B BIT(15) #define BIT_TIM1_8814B BIT(14) #define BIT_SHIFT_PS_AID_1_8814B 0 #define BIT_MASK_PS_AID_1_8814B 0x7ff -#define BIT_PS_AID_1_8814B(x) (((x) & BIT_MASK_PS_AID_1_8814B) << BIT_SHIFT_PS_AID_1_8814B) -#define BIT_GET_PS_AID_1_8814B(x) (((x) >> BIT_SHIFT_PS_AID_1_8814B) & BIT_MASK_PS_AID_1_8814B) - - +#define BIT_PS_AID_1_8814B(x) \ + (((x) & BIT_MASK_PS_AID_1_8814B) << BIT_SHIFT_PS_AID_1_8814B) +#define BITS_PS_AID_1_8814B \ + (BIT_MASK_PS_AID_1_8814B << BIT_SHIFT_PS_AID_1_8814B) +#define BIT_CLEAR_PS_AID_1_8814B(x) ((x) & (~BITS_PS_AID_1_8814B)) +#define BIT_GET_PS_AID_1_8814B(x) \ + (((x) >> BIT_SHIFT_PS_AID_1_8814B) & BIT_MASK_PS_AID_1_8814B) +#define BIT_SET_PS_AID_1_8814B(x, v) \ + (BIT_CLEAR_PS_AID_1_8814B(x) | BIT_PS_AID_1_8814B(v)) /* 2 REG_ASSOCIATED_BFMEE_SEL_8814B */ #define BIT_TXUSER_ID1_8814B BIT(25) @@ -10355,39 +23966,76 @@ #define BIT_SHIFT_AID1_8814B 16 #define BIT_MASK_AID1_8814B 0x1ff #define BIT_AID1_8814B(x) (((x) & BIT_MASK_AID1_8814B) << BIT_SHIFT_AID1_8814B) -#define BIT_GET_AID1_8814B(x) (((x) >> BIT_SHIFT_AID1_8814B) & BIT_MASK_AID1_8814B) - +#define BITS_AID1_8814B (BIT_MASK_AID1_8814B << BIT_SHIFT_AID1_8814B) +#define BIT_CLEAR_AID1_8814B(x) ((x) & (~BITS_AID1_8814B)) +#define BIT_GET_AID1_8814B(x) \ + (((x) >> BIT_SHIFT_AID1_8814B) & BIT_MASK_AID1_8814B) +#define BIT_SET_AID1_8814B(x, v) (BIT_CLEAR_AID1_8814B(x) | BIT_AID1_8814B(v)) #define BIT_TXUSER_ID0_8814B BIT(9) #define BIT_SHIFT_AID0_8814B 0 #define BIT_MASK_AID0_8814B 0x1ff #define BIT_AID0_8814B(x) (((x) & BIT_MASK_AID0_8814B) << BIT_SHIFT_AID0_8814B) -#define BIT_GET_AID0_8814B(x) (((x) >> BIT_SHIFT_AID0_8814B) & BIT_MASK_AID0_8814B) - - +#define BITS_AID0_8814B (BIT_MASK_AID0_8814B << BIT_SHIFT_AID0_8814B) +#define BIT_CLEAR_AID0_8814B(x) ((x) & (~BITS_AID0_8814B)) +#define BIT_GET_AID0_8814B(x) \ + (((x) >> BIT_SHIFT_AID0_8814B) & BIT_MASK_AID0_8814B) +#define BIT_SET_AID0_8814B(x, v) (BIT_CLEAR_AID0_8814B(x) | BIT_AID0_8814B(v)) /* 2 REG_SND_PTCL_CTRL_8814B */ #define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B 24 #define BIT_MASK_NDP_RX_STANDBY_TIMER_8814B 0xff -#define BIT_NDP_RX_STANDBY_TIMER_8814B(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8814B) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) -#define BIT_GET_NDP_RX_STANDBY_TIMER_8814B(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) & BIT_MASK_NDP_RX_STANDBY_TIMER_8814B) - - +#define BIT_NDP_RX_STANDBY_TIMER_8814B(x) \ + (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8814B) \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) +#define BITS_NDP_RX_STANDBY_TIMER_8814B \ + (BIT_MASK_NDP_RX_STANDBY_TIMER_8814B \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8814B(x) \ + ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8814B)) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) & \ + BIT_MASK_NDP_RX_STANDBY_TIMER_8814B) +#define BIT_SET_NDP_RX_STANDBY_TIMER_8814B(x, v) \ + (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8814B(x) | \ + BIT_NDP_RX_STANDBY_TIMER_8814B(v)) #define BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B 16 #define BIT_MASK_CSI_RPT_OFFSET_HT_8814B 0xff -#define BIT_CSI_RPT_OFFSET_HT_8814B(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8814B) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) -#define BIT_GET_CSI_RPT_OFFSET_HT_8814B(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) & BIT_MASK_CSI_RPT_OFFSET_HT_8814B) - - - -#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8814B 8 -#define BIT_MASK_R_WMAC_VHT_CATEGORY_8814B 0xff -#define BIT_R_WMAC_VHT_CATEGORY_8814B(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8814B) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8814B) -#define BIT_GET_R_WMAC_VHT_CATEGORY_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8814B) & BIT_MASK_R_WMAC_VHT_CATEGORY_8814B) - +#define BIT_CSI_RPT_OFFSET_HT_8814B(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8814B) \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) +#define BITS_CSI_RPT_OFFSET_HT_8814B \ + (BIT_MASK_CSI_RPT_OFFSET_HT_8814B << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8814B(x) \ + ((x) & (~BITS_CSI_RPT_OFFSET_HT_8814B)) +#define BIT_GET_CSI_RPT_OFFSET_HT_8814B(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) & \ + BIT_MASK_CSI_RPT_OFFSET_HT_8814B) +#define BIT_SET_CSI_RPT_OFFSET_HT_8814B(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT_8814B(x) | BIT_CSI_RPT_OFFSET_HT_8814B(v)) + +#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8814B BIT(15) +#define BIT_R_WMAC_CSI_CHKSUM_DIS_8814B BIT(14) + +#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B 8 +#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B 0x3f +#define BIT_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) \ + (((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B) \ + << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B) +#define BITS_R_CSI_RPT_OFFSET_VHT_V1_8814B \ + (BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B \ + << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B) +#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) \ + ((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1_8814B)) +#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B) & \ + BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B) +#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1_8814B(x, v) \ + (BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) | \ + BIT_R_CSI_RPT_OFFSET_VHT_V1_8814B(v)) #define BIT_R_WMAC_USE_NSTS_8814B BIT(7) #define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8814B BIT(6) @@ -10399,6 +24047,27 @@ #define BIT_R_WMAC_VHT_NDPA_EN_8814B BIT(0) /* 2 REG_RX_CSI_RPT_INFO_8814B */ +#define BIT_WRITE_ENABLE_8814B BIT(31) +#define BIT_WMAC_CHECK_SOUNDING_SEQ_8814B BIT(30) + +#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B 1 +#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B 0xffffff +#define BIT_VHTHT_MIMO_CTRL_FIELD_8814B(x) \ + (((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B) \ + << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B) +#define BITS_VHTHT_MIMO_CTRL_FIELD_8814B \ + (BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B \ + << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B) +#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8814B(x) \ + ((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD_8814B)) +#define BIT_GET_VHTHT_MIMO_CTRL_FIELD_8814B(x) \ + (((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B) & \ + BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B) +#define BIT_SET_VHTHT_MIMO_CTRL_FIELD_8814B(x, v) \ + (BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8814B(x) | \ + BIT_VHTHT_MIMO_CTRL_FIELD_8814B(v)) + +#define BIT_CSI_INTERRUPT_STATUS_8814B BIT(0) /* 2 REG_NS_ARP_CTRL_8814B */ #define BIT_R_WMAC_NSARP_RSPEN_8814B BIT(15) @@ -10407,24 +24076,54 @@ #define BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B 6 #define BIT_MASK_R_WMAC_NSARP_MODEN_8814B 0x3 -#define BIT_R_WMAC_NSARP_MODEN_8814B(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8814B) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) -#define BIT_GET_R_WMAC_NSARP_MODEN_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) & BIT_MASK_R_WMAC_NSARP_MODEN_8814B) - - +#define BIT_R_WMAC_NSARP_MODEN_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8814B) \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) +#define BITS_R_WMAC_NSARP_MODEN_8814B \ + (BIT_MASK_R_WMAC_NSARP_MODEN_8814B \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8814B(x) \ + ((x) & (~BITS_R_WMAC_NSARP_MODEN_8814B)) +#define BIT_GET_R_WMAC_NSARP_MODEN_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) & \ + BIT_MASK_R_WMAC_NSARP_MODEN_8814B) +#define BIT_SET_R_WMAC_NSARP_MODEN_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_MODEN_8814B(x) | \ + BIT_R_WMAC_NSARP_MODEN_8814B(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B 4 #define BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B 0x3 -#define BIT_R_WMAC_NSARP_RSPFTP_8814B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) -#define BIT_GET_R_WMAC_NSARP_RSPFTP_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B) - - +#define BIT_R_WMAC_NSARP_RSPFTP_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) +#define BITS_R_WMAC_NSARP_RSPFTP_8814B \ + (BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8814B(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8814B)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) & \ + BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B) +#define BIT_SET_R_WMAC_NSARP_RSPFTP_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8814B(x) | \ + BIT_R_WMAC_NSARP_RSPFTP_8814B(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B 0 #define BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B 0xf -#define BIT_R_WMAC_NSARP_RSPSEC_8814B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) -#define BIT_GET_R_WMAC_NSARP_RSPSEC_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B) - - +#define BIT_R_WMAC_NSARP_RSPSEC_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) +#define BITS_R_WMAC_NSARP_RSPSEC_8814B \ + (BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8814B(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8814B)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) & \ + BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B) +#define BIT_SET_R_WMAC_NSARP_RSPSEC_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8814B(x) | \ + BIT_R_WMAC_NSARP_RSPSEC_8814B(v)) /* 2 REG_NS_ARP_INFO_8814B */ #define BIT_REQ_IS_MCNS_8814B BIT(23) @@ -10435,78 +24134,158 @@ #define BIT_SHIFT_EXPRSP_SECTYPE_8814B 16 #define BIT_MASK_EXPRSP_SECTYPE_8814B 0x7 -#define BIT_EXPRSP_SECTYPE_8814B(x) (((x) & BIT_MASK_EXPRSP_SECTYPE_8814B) << BIT_SHIFT_EXPRSP_SECTYPE_8814B) -#define BIT_GET_EXPRSP_SECTYPE_8814B(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8814B) & BIT_MASK_EXPRSP_SECTYPE_8814B) - - +#define BIT_EXPRSP_SECTYPE_8814B(x) \ + (((x) & BIT_MASK_EXPRSP_SECTYPE_8814B) \ + << BIT_SHIFT_EXPRSP_SECTYPE_8814B) +#define BITS_EXPRSP_SECTYPE_8814B \ + (BIT_MASK_EXPRSP_SECTYPE_8814B << BIT_SHIFT_EXPRSP_SECTYPE_8814B) +#define BIT_CLEAR_EXPRSP_SECTYPE_8814B(x) ((x) & (~BITS_EXPRSP_SECTYPE_8814B)) +#define BIT_GET_EXPRSP_SECTYPE_8814B(x) \ + (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8814B) & \ + BIT_MASK_EXPRSP_SECTYPE_8814B) +#define BIT_SET_EXPRSP_SECTYPE_8814B(x, v) \ + (BIT_CLEAR_EXPRSP_SECTYPE_8814B(x) | BIT_EXPRSP_SECTYPE_8814B(v)) #define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B 8 #define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B 0xff -#define BIT_EXPRSP_CHKSM_7_TO_0_8814B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) -#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B) - - +#define BIT_EXPRSP_CHKSM_7_TO_0_8814B(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B) \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) +#define BITS_EXPRSP_CHKSM_7_TO_0_8814B \ + (BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) +#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8814B(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8814B)) +#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8814B(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) & \ + BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B) +#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8814B(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8814B(x) | \ + BIT_EXPRSP_CHKSM_7_TO_0_8814B(v)) #define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B 0 #define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B 0xff -#define BIT_EXPRSP_CHKSM_15_TO_8_8814B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) -#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B) - - +#define BIT_EXPRSP_CHKSM_15_TO_8_8814B(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B) \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) +#define BITS_EXPRSP_CHKSM_15_TO_8_8814B \ + (BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) +#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8814B(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8814B)) +#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8814B(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) & \ + BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B) +#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8814B(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8814B(x) | \ + BIT_EXPRSP_CHKSM_15_TO_8_8814B(v)) /* 2 REG_BEAMFORMING_INFO_NSARP_V1_8814B */ #define BIT_SHIFT_WMAC_ARPIP_8814B 0 #define BIT_MASK_WMAC_ARPIP_8814B 0xffffffffL -#define BIT_WMAC_ARPIP_8814B(x) (((x) & BIT_MASK_WMAC_ARPIP_8814B) << BIT_SHIFT_WMAC_ARPIP_8814B) -#define BIT_GET_WMAC_ARPIP_8814B(x) (((x) >> BIT_SHIFT_WMAC_ARPIP_8814B) & BIT_MASK_WMAC_ARPIP_8814B) - - +#define BIT_WMAC_ARPIP_8814B(x) \ + (((x) & BIT_MASK_WMAC_ARPIP_8814B) << BIT_SHIFT_WMAC_ARPIP_8814B) +#define BITS_WMAC_ARPIP_8814B \ + (BIT_MASK_WMAC_ARPIP_8814B << BIT_SHIFT_WMAC_ARPIP_8814B) +#define BIT_CLEAR_WMAC_ARPIP_8814B(x) ((x) & (~BITS_WMAC_ARPIP_8814B)) +#define BIT_GET_WMAC_ARPIP_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_ARPIP_8814B) & BIT_MASK_WMAC_ARPIP_8814B) +#define BIT_SET_WMAC_ARPIP_8814B(x, v) \ + (BIT_CLEAR_WMAC_ARPIP_8814B(x) | BIT_WMAC_ARPIP_8814B(v)) /* 2 REG_BEAMFORMING_INFO_NSARP_8814B */ #define BIT_SHIFT_BEAMFORMING_INFO_8814B 0 #define BIT_MASK_BEAMFORMING_INFO_8814B 0xffffffffL -#define BIT_BEAMFORMING_INFO_8814B(x) (((x) & BIT_MASK_BEAMFORMING_INFO_8814B) << BIT_SHIFT_BEAMFORMING_INFO_8814B) -#define BIT_GET_BEAMFORMING_INFO_8814B(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8814B) & BIT_MASK_BEAMFORMING_INFO_8814B) - - +#define BIT_BEAMFORMING_INFO_8814B(x) \ + (((x) & BIT_MASK_BEAMFORMING_INFO_8814B) \ + << BIT_SHIFT_BEAMFORMING_INFO_8814B) +#define BITS_BEAMFORMING_INFO_8814B \ + (BIT_MASK_BEAMFORMING_INFO_8814B << BIT_SHIFT_BEAMFORMING_INFO_8814B) +#define BIT_CLEAR_BEAMFORMING_INFO_8814B(x) \ + ((x) & (~BITS_BEAMFORMING_INFO_8814B)) +#define BIT_GET_BEAMFORMING_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8814B) & \ + BIT_MASK_BEAMFORMING_INFO_8814B) +#define BIT_SET_BEAMFORMING_INFO_8814B(x, v) \ + (BIT_CLEAR_BEAMFORMING_INFO_8814B(x) | BIT_BEAMFORMING_INFO_8814B(v)) /* 2 REG_IPV6_8814B */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_0_8814B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B) - - +#define BIT_R_WMAC_IPV6_MYIPAD_0_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) +#define BITS_R_WMAC_IPV6_MYIPAD_0_8814B \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8814B(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8814B)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8814B(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_0_8814B(v)) /* 2 REG_IPV6_1_8814B */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_1_8814B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B) - - +#define BIT_R_WMAC_IPV6_MYIPAD_1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) +#define BITS_R_WMAC_IPV6_MYIPAD_1_8814B \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8814B(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8814B)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8814B(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_1_8814B(v)) /* 2 REG_IPV6_2_8814B */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_2_8814B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B) - - +#define BIT_R_WMAC_IPV6_MYIPAD_2_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) +#define BITS_R_WMAC_IPV6_MYIPAD_2_8814B \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8814B(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8814B)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8814B(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_2_8814B(v)) /* 2 REG_IPV6_3_8814B */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_3_8814B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B) - - +#define BIT_R_WMAC_IPV6_MYIPAD_3_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) +#define BITS_R_WMAC_IPV6_MYIPAD_3_8814B \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8814B(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8814B)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8814B(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_3_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -10520,17 +24299,37 @@ #define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B 4 #define BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B 0xf -#define BIT_R_WMAC_CTX_SUBTYPE_8814B(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) -#define BIT_GET_R_WMAC_CTX_SUBTYPE_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B) - - +#define BIT_R_WMAC_CTX_SUBTYPE_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B) \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) +#define BITS_R_WMAC_CTX_SUBTYPE_8814B \ + (BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8814B(x) \ + ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8814B)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) & \ + BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B) +#define BIT_SET_R_WMAC_CTX_SUBTYPE_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8814B(x) | \ + BIT_R_WMAC_CTX_SUBTYPE_8814B(v)) #define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B 0 #define BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B 0xf -#define BIT_R_WMAC_RTX_SUBTYPE_8814B(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) -#define BIT_GET_R_WMAC_RTX_SUBTYPE_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B) - - +#define BIT_R_WMAC_RTX_SUBTYPE_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B) \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) +#define BITS_R_WMAC_RTX_SUBTYPE_8814B \ + (BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8814B(x) \ + ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8814B)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) & \ + BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B) +#define BIT_SET_R_WMAC_RTX_SUBTYPE_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8814B(x) | \ + BIT_R_WMAC_RTX_SUBTYPE_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -10546,10 +24345,14 @@ #define BIT_SHIFT_TIMER_8814B 0 #define BIT_MASK_TIMER_8814B 0xff -#define BIT_TIMER_8814B(x) (((x) & BIT_MASK_TIMER_8814B) << BIT_SHIFT_TIMER_8814B) -#define BIT_GET_TIMER_8814B(x) (((x) >> BIT_SHIFT_TIMER_8814B) & BIT_MASK_TIMER_8814B) - - +#define BIT_TIMER_8814B(x) \ + (((x) & BIT_MASK_TIMER_8814B) << BIT_SHIFT_TIMER_8814B) +#define BITS_TIMER_8814B (BIT_MASK_TIMER_8814B << BIT_SHIFT_TIMER_8814B) +#define BIT_CLEAR_TIMER_8814B(x) ((x) & (~BITS_TIMER_8814B)) +#define BIT_GET_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_TIMER_8814B) & BIT_MASK_TIMER_8814B) +#define BIT_SET_TIMER_8814B(x, v) \ + (BIT_CLEAR_TIMER_8814B(x) | BIT_TIMER_8814B(v)) /* 2 REG_BT_COEX_8814B */ #define BIT_R_GNT_BT_RFC_SW_8814B BIT(12) @@ -10560,26 +24363,43 @@ #define BIT_SHIFT_R_BT_CNT_THR_8814B 0 #define BIT_MASK_R_BT_CNT_THR_8814B 0xff -#define BIT_R_BT_CNT_THR_8814B(x) (((x) & BIT_MASK_R_BT_CNT_THR_8814B) << BIT_SHIFT_R_BT_CNT_THR_8814B) -#define BIT_GET_R_BT_CNT_THR_8814B(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8814B) & BIT_MASK_R_BT_CNT_THR_8814B) - - +#define BIT_R_BT_CNT_THR_8814B(x) \ + (((x) & BIT_MASK_R_BT_CNT_THR_8814B) << BIT_SHIFT_R_BT_CNT_THR_8814B) +#define BITS_R_BT_CNT_THR_8814B \ + (BIT_MASK_R_BT_CNT_THR_8814B << BIT_SHIFT_R_BT_CNT_THR_8814B) +#define BIT_CLEAR_R_BT_CNT_THR_8814B(x) ((x) & (~BITS_R_BT_CNT_THR_8814B)) +#define BIT_GET_R_BT_CNT_THR_8814B(x) \ + (((x) >> BIT_SHIFT_R_BT_CNT_THR_8814B) & BIT_MASK_R_BT_CNT_THR_8814B) +#define BIT_SET_R_BT_CNT_THR_8814B(x, v) \ + (BIT_CLEAR_R_BT_CNT_THR_8814B(x) | BIT_R_BT_CNT_THR_8814B(v)) /* 2 REG_WLAN_ACT_MASK_CTRL_8814B */ #define BIT_SHIFT_RXMYRTS_NAV_V1_8814B 8 #define BIT_MASK_RXMYRTS_NAV_V1_8814B 0xff -#define BIT_RXMYRTS_NAV_V1_8814B(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8814B) << BIT_SHIFT_RXMYRTS_NAV_V1_8814B) -#define BIT_GET_RXMYRTS_NAV_V1_8814B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8814B) & BIT_MASK_RXMYRTS_NAV_V1_8814B) - - +#define BIT_RXMYRTS_NAV_V1_8814B(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_V1_8814B) \ + << BIT_SHIFT_RXMYRTS_NAV_V1_8814B) +#define BITS_RXMYRTS_NAV_V1_8814B \ + (BIT_MASK_RXMYRTS_NAV_V1_8814B << BIT_SHIFT_RXMYRTS_NAV_V1_8814B) +#define BIT_CLEAR_RXMYRTS_NAV_V1_8814B(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8814B)) +#define BIT_GET_RXMYRTS_NAV_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8814B) & \ + BIT_MASK_RXMYRTS_NAV_V1_8814B) +#define BIT_SET_RXMYRTS_NAV_V1_8814B(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_V1_8814B(x) | BIT_RXMYRTS_NAV_V1_8814B(v)) #define BIT_SHIFT_RTSRST_V1_8814B 0 #define BIT_MASK_RTSRST_V1_8814B 0xff -#define BIT_RTSRST_V1_8814B(x) (((x) & BIT_MASK_RTSRST_V1_8814B) << BIT_SHIFT_RTSRST_V1_8814B) -#define BIT_GET_RTSRST_V1_8814B(x) (((x) >> BIT_SHIFT_RTSRST_V1_8814B) & BIT_MASK_RTSRST_V1_8814B) - - +#define BIT_RTSRST_V1_8814B(x) \ + (((x) & BIT_MASK_RTSRST_V1_8814B) << BIT_SHIFT_RTSRST_V1_8814B) +#define BITS_RTSRST_V1_8814B \ + (BIT_MASK_RTSRST_V1_8814B << BIT_SHIFT_RTSRST_V1_8814B) +#define BIT_CLEAR_RTSRST_V1_8814B(x) ((x) & (~BITS_RTSRST_V1_8814B)) +#define BIT_GET_RTSRST_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RTSRST_V1_8814B) & BIT_MASK_RTSRST_V1_8814B) +#define BIT_SET_RTSRST_V1_8814B(x, v) \ + (BIT_CLEAR_RTSRST_V1_8814B(x) | BIT_RTSRST_V1_8814B(v)) /* 2 REG_WLAN_ACT_MASK_CTRL_1_8814B */ #define BIT_WLRX_TER_BY_CTL_1_8814B BIT(11) @@ -10594,23 +24414,47 @@ #define BIT_SHIFT_BT_STAT_DELAY_8814B 12 #define BIT_MASK_BT_STAT_DELAY_8814B 0xf -#define BIT_BT_STAT_DELAY_8814B(x) (((x) & BIT_MASK_BT_STAT_DELAY_8814B) << BIT_SHIFT_BT_STAT_DELAY_8814B) -#define BIT_GET_BT_STAT_DELAY_8814B(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8814B) & BIT_MASK_BT_STAT_DELAY_8814B) - - +#define BIT_BT_STAT_DELAY_8814B(x) \ + (((x) & BIT_MASK_BT_STAT_DELAY_8814B) << BIT_SHIFT_BT_STAT_DELAY_8814B) +#define BITS_BT_STAT_DELAY_8814B \ + (BIT_MASK_BT_STAT_DELAY_8814B << BIT_SHIFT_BT_STAT_DELAY_8814B) +#define BIT_CLEAR_BT_STAT_DELAY_8814B(x) ((x) & (~BITS_BT_STAT_DELAY_8814B)) +#define BIT_GET_BT_STAT_DELAY_8814B(x) \ + (((x) >> BIT_SHIFT_BT_STAT_DELAY_8814B) & BIT_MASK_BT_STAT_DELAY_8814B) +#define BIT_SET_BT_STAT_DELAY_8814B(x, v) \ + (BIT_CLEAR_BT_STAT_DELAY_8814B(x) | BIT_BT_STAT_DELAY_8814B(v)) #define BIT_SHIFT_BT_TRX_INIT_DETECT_8814B 8 #define BIT_MASK_BT_TRX_INIT_DETECT_8814B 0xf -#define BIT_BT_TRX_INIT_DETECT_8814B(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8814B) << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) -#define BIT_GET_BT_TRX_INIT_DETECT_8814B(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) & BIT_MASK_BT_TRX_INIT_DETECT_8814B) - - +#define BIT_BT_TRX_INIT_DETECT_8814B(x) \ + (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8814B) \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) +#define BITS_BT_TRX_INIT_DETECT_8814B \ + (BIT_MASK_BT_TRX_INIT_DETECT_8814B \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) +#define BIT_CLEAR_BT_TRX_INIT_DETECT_8814B(x) \ + ((x) & (~BITS_BT_TRX_INIT_DETECT_8814B)) +#define BIT_GET_BT_TRX_INIT_DETECT_8814B(x) \ + (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) & \ + BIT_MASK_BT_TRX_INIT_DETECT_8814B) +#define BIT_SET_BT_TRX_INIT_DETECT_8814B(x, v) \ + (BIT_CLEAR_BT_TRX_INIT_DETECT_8814B(x) | \ + BIT_BT_TRX_INIT_DETECT_8814B(v)) #define BIT_SHIFT_BT_PRI_DETECT_TO_8814B 4 #define BIT_MASK_BT_PRI_DETECT_TO_8814B 0xf -#define BIT_BT_PRI_DETECT_TO_8814B(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8814B) << BIT_SHIFT_BT_PRI_DETECT_TO_8814B) -#define BIT_GET_BT_PRI_DETECT_TO_8814B(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8814B) & BIT_MASK_BT_PRI_DETECT_TO_8814B) - +#define BIT_BT_PRI_DETECT_TO_8814B(x) \ + (((x) & BIT_MASK_BT_PRI_DETECT_TO_8814B) \ + << BIT_SHIFT_BT_PRI_DETECT_TO_8814B) +#define BITS_BT_PRI_DETECT_TO_8814B \ + (BIT_MASK_BT_PRI_DETECT_TO_8814B << BIT_SHIFT_BT_PRI_DETECT_TO_8814B) +#define BIT_CLEAR_BT_PRI_DETECT_TO_8814B(x) \ + ((x) & (~BITS_BT_PRI_DETECT_TO_8814B)) +#define BIT_GET_BT_PRI_DETECT_TO_8814B(x) \ + (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8814B) & \ + BIT_MASK_BT_PRI_DETECT_TO_8814B) +#define BIT_SET_BT_PRI_DETECT_TO_8814B(x, v) \ + (BIT_CLEAR_BT_PRI_DETECT_TO_8814B(x) | BIT_BT_PRI_DETECT_TO_8814B(v)) #define BIT_R_GRANTALL_WLMASK_8814B BIT(3) #define BIT_STATIS_BT_EN_8814B BIT(2) @@ -10621,55 +24465,103 @@ #define BIT_SHIFT_STATIS_BT_HI_RX_8814B 16 #define BIT_MASK_STATIS_BT_HI_RX_8814B 0xffff -#define BIT_STATIS_BT_HI_RX_8814B(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8814B) << BIT_SHIFT_STATIS_BT_HI_RX_8814B) -#define BIT_GET_STATIS_BT_HI_RX_8814B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8814B) & BIT_MASK_STATIS_BT_HI_RX_8814B) - - +#define BIT_STATIS_BT_HI_RX_8814B(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_RX_8814B) \ + << BIT_SHIFT_STATIS_BT_HI_RX_8814B) +#define BITS_STATIS_BT_HI_RX_8814B \ + (BIT_MASK_STATIS_BT_HI_RX_8814B << BIT_SHIFT_STATIS_BT_HI_RX_8814B) +#define BIT_CLEAR_STATIS_BT_HI_RX_8814B(x) ((x) & (~BITS_STATIS_BT_HI_RX_8814B)) +#define BIT_GET_STATIS_BT_HI_RX_8814B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8814B) & \ + BIT_MASK_STATIS_BT_HI_RX_8814B) +#define BIT_SET_STATIS_BT_HI_RX_8814B(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_RX_8814B(x) | BIT_STATIS_BT_HI_RX_8814B(v)) #define BIT_SHIFT_STATIS_BT_HI_TX_8814B 0 #define BIT_MASK_STATIS_BT_HI_TX_8814B 0xffff -#define BIT_STATIS_BT_HI_TX_8814B(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8814B) << BIT_SHIFT_STATIS_BT_HI_TX_8814B) -#define BIT_GET_STATIS_BT_HI_TX_8814B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8814B) & BIT_MASK_STATIS_BT_HI_TX_8814B) - - +#define BIT_STATIS_BT_HI_TX_8814B(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_TX_8814B) \ + << BIT_SHIFT_STATIS_BT_HI_TX_8814B) +#define BITS_STATIS_BT_HI_TX_8814B \ + (BIT_MASK_STATIS_BT_HI_TX_8814B << BIT_SHIFT_STATIS_BT_HI_TX_8814B) +#define BIT_CLEAR_STATIS_BT_HI_TX_8814B(x) ((x) & (~BITS_STATIS_BT_HI_TX_8814B)) +#define BIT_GET_STATIS_BT_HI_TX_8814B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8814B) & \ + BIT_MASK_STATIS_BT_HI_TX_8814B) +#define BIT_SET_STATIS_BT_HI_TX_8814B(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_TX_8814B(x) | BIT_STATIS_BT_HI_TX_8814B(v)) /* 2 REG_BT_ACT_STATISTICS_1_8814B */ #define BIT_SHIFT_STATIS_BT_LO_RX_1_8814B 16 #define BIT_MASK_STATIS_BT_LO_RX_1_8814B 0xffff -#define BIT_STATIS_BT_LO_RX_1_8814B(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8814B) << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) -#define BIT_GET_STATIS_BT_LO_RX_1_8814B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) & BIT_MASK_STATIS_BT_LO_RX_1_8814B) - - +#define BIT_STATIS_BT_LO_RX_1_8814B(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8814B) \ + << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) +#define BITS_STATIS_BT_LO_RX_1_8814B \ + (BIT_MASK_STATIS_BT_LO_RX_1_8814B << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) +#define BIT_CLEAR_STATIS_BT_LO_RX_1_8814B(x) \ + ((x) & (~BITS_STATIS_BT_LO_RX_1_8814B)) +#define BIT_GET_STATIS_BT_LO_RX_1_8814B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) & \ + BIT_MASK_STATIS_BT_LO_RX_1_8814B) +#define BIT_SET_STATIS_BT_LO_RX_1_8814B(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX_1_8814B(x) | BIT_STATIS_BT_LO_RX_1_8814B(v)) #define BIT_SHIFT_STATIS_BT_LO_TX_1_8814B 0 #define BIT_MASK_STATIS_BT_LO_TX_1_8814B 0xffff -#define BIT_STATIS_BT_LO_TX_1_8814B(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8814B) << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) -#define BIT_GET_STATIS_BT_LO_TX_1_8814B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) & BIT_MASK_STATIS_BT_LO_TX_1_8814B) - - +#define BIT_STATIS_BT_LO_TX_1_8814B(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8814B) \ + << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) +#define BITS_STATIS_BT_LO_TX_1_8814B \ + (BIT_MASK_STATIS_BT_LO_TX_1_8814B << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) +#define BIT_CLEAR_STATIS_BT_LO_TX_1_8814B(x) \ + ((x) & (~BITS_STATIS_BT_LO_TX_1_8814B)) +#define BIT_GET_STATIS_BT_LO_TX_1_8814B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) & \ + BIT_MASK_STATIS_BT_LO_TX_1_8814B) +#define BIT_SET_STATIS_BT_LO_TX_1_8814B(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX_1_8814B(x) | BIT_STATIS_BT_LO_TX_1_8814B(v)) /* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8814B */ #define BIT_SHIFT_R_BT_CMD_RPT_8814B 16 #define BIT_MASK_R_BT_CMD_RPT_8814B 0xffff -#define BIT_R_BT_CMD_RPT_8814B(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8814B) << BIT_SHIFT_R_BT_CMD_RPT_8814B) -#define BIT_GET_R_BT_CMD_RPT_8814B(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8814B) & BIT_MASK_R_BT_CMD_RPT_8814B) - - +#define BIT_R_BT_CMD_RPT_8814B(x) \ + (((x) & BIT_MASK_R_BT_CMD_RPT_8814B) << BIT_SHIFT_R_BT_CMD_RPT_8814B) +#define BITS_R_BT_CMD_RPT_8814B \ + (BIT_MASK_R_BT_CMD_RPT_8814B << BIT_SHIFT_R_BT_CMD_RPT_8814B) +#define BIT_CLEAR_R_BT_CMD_RPT_8814B(x) ((x) & (~BITS_R_BT_CMD_RPT_8814B)) +#define BIT_GET_R_BT_CMD_RPT_8814B(x) \ + (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8814B) & BIT_MASK_R_BT_CMD_RPT_8814B) +#define BIT_SET_R_BT_CMD_RPT_8814B(x, v) \ + (BIT_CLEAR_R_BT_CMD_RPT_8814B(x) | BIT_R_BT_CMD_RPT_8814B(v)) #define BIT_SHIFT_R_RPT_FROM_BT_8814B 8 #define BIT_MASK_R_RPT_FROM_BT_8814B 0xff -#define BIT_R_RPT_FROM_BT_8814B(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8814B) << BIT_SHIFT_R_RPT_FROM_BT_8814B) -#define BIT_GET_R_RPT_FROM_BT_8814B(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8814B) & BIT_MASK_R_RPT_FROM_BT_8814B) - - +#define BIT_R_RPT_FROM_BT_8814B(x) \ + (((x) & BIT_MASK_R_RPT_FROM_BT_8814B) << BIT_SHIFT_R_RPT_FROM_BT_8814B) +#define BITS_R_RPT_FROM_BT_8814B \ + (BIT_MASK_R_RPT_FROM_BT_8814B << BIT_SHIFT_R_RPT_FROM_BT_8814B) +#define BIT_CLEAR_R_RPT_FROM_BT_8814B(x) ((x) & (~BITS_R_RPT_FROM_BT_8814B)) +#define BIT_GET_R_RPT_FROM_BT_8814B(x) \ + (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8814B) & BIT_MASK_R_RPT_FROM_BT_8814B) +#define BIT_SET_R_RPT_FROM_BT_8814B(x, v) \ + (BIT_CLEAR_R_RPT_FROM_BT_8814B(x) | BIT_R_RPT_FROM_BT_8814B(v)) #define BIT_SHIFT_BT_HID_ISR_SET_8814B 6 #define BIT_MASK_BT_HID_ISR_SET_8814B 0x3 -#define BIT_BT_HID_ISR_SET_8814B(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8814B) << BIT_SHIFT_BT_HID_ISR_SET_8814B) -#define BIT_GET_BT_HID_ISR_SET_8814B(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8814B) & BIT_MASK_BT_HID_ISR_SET_8814B) - +#define BIT_BT_HID_ISR_SET_8814B(x) \ + (((x) & BIT_MASK_BT_HID_ISR_SET_8814B) \ + << BIT_SHIFT_BT_HID_ISR_SET_8814B) +#define BITS_BT_HID_ISR_SET_8814B \ + (BIT_MASK_BT_HID_ISR_SET_8814B << BIT_SHIFT_BT_HID_ISR_SET_8814B) +#define BIT_CLEAR_BT_HID_ISR_SET_8814B(x) ((x) & (~BITS_BT_HID_ISR_SET_8814B)) +#define BIT_GET_BT_HID_ISR_SET_8814B(x) \ + (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8814B) & \ + BIT_MASK_BT_HID_ISR_SET_8814B) +#define BIT_SET_BT_HID_ISR_SET_8814B(x, v) \ + (BIT_CLEAR_BT_HID_ISR_SET_8814B(x) | BIT_BT_HID_ISR_SET_8814B(v)) #define BIT_TDMA_BT_START_NOTIFY_8814B BIT(5) #define BIT_ENABLE_TDMA_FW_MODE_8814B BIT(4) @@ -10682,31 +24574,54 @@ #define BIT_SHIFT_BT_PROFILE_8814B 24 #define BIT_MASK_BT_PROFILE_8814B 0xff -#define BIT_BT_PROFILE_8814B(x) (((x) & BIT_MASK_BT_PROFILE_8814B) << BIT_SHIFT_BT_PROFILE_8814B) -#define BIT_GET_BT_PROFILE_8814B(x) (((x) >> BIT_SHIFT_BT_PROFILE_8814B) & BIT_MASK_BT_PROFILE_8814B) - - +#define BIT_BT_PROFILE_8814B(x) \ + (((x) & BIT_MASK_BT_PROFILE_8814B) << BIT_SHIFT_BT_PROFILE_8814B) +#define BITS_BT_PROFILE_8814B \ + (BIT_MASK_BT_PROFILE_8814B << BIT_SHIFT_BT_PROFILE_8814B) +#define BIT_CLEAR_BT_PROFILE_8814B(x) ((x) & (~BITS_BT_PROFILE_8814B)) +#define BIT_GET_BT_PROFILE_8814B(x) \ + (((x) >> BIT_SHIFT_BT_PROFILE_8814B) & BIT_MASK_BT_PROFILE_8814B) +#define BIT_SET_BT_PROFILE_8814B(x, v) \ + (BIT_CLEAR_BT_PROFILE_8814B(x) | BIT_BT_PROFILE_8814B(v)) #define BIT_SHIFT_BT_POWER_8814B 16 #define BIT_MASK_BT_POWER_8814B 0xff -#define BIT_BT_POWER_8814B(x) (((x) & BIT_MASK_BT_POWER_8814B) << BIT_SHIFT_BT_POWER_8814B) -#define BIT_GET_BT_POWER_8814B(x) (((x) >> BIT_SHIFT_BT_POWER_8814B) & BIT_MASK_BT_POWER_8814B) - - +#define BIT_BT_POWER_8814B(x) \ + (((x) & BIT_MASK_BT_POWER_8814B) << BIT_SHIFT_BT_POWER_8814B) +#define BITS_BT_POWER_8814B \ + (BIT_MASK_BT_POWER_8814B << BIT_SHIFT_BT_POWER_8814B) +#define BIT_CLEAR_BT_POWER_8814B(x) ((x) & (~BITS_BT_POWER_8814B)) +#define BIT_GET_BT_POWER_8814B(x) \ + (((x) >> BIT_SHIFT_BT_POWER_8814B) & BIT_MASK_BT_POWER_8814B) +#define BIT_SET_BT_POWER_8814B(x, v) \ + (BIT_CLEAR_BT_POWER_8814B(x) | BIT_BT_POWER_8814B(v)) #define BIT_SHIFT_BT_PREDECT_STATUS_8814B 8 #define BIT_MASK_BT_PREDECT_STATUS_8814B 0xff -#define BIT_BT_PREDECT_STATUS_8814B(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8814B) << BIT_SHIFT_BT_PREDECT_STATUS_8814B) -#define BIT_GET_BT_PREDECT_STATUS_8814B(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8814B) & BIT_MASK_BT_PREDECT_STATUS_8814B) - - +#define BIT_BT_PREDECT_STATUS_8814B(x) \ + (((x) & BIT_MASK_BT_PREDECT_STATUS_8814B) \ + << BIT_SHIFT_BT_PREDECT_STATUS_8814B) +#define BITS_BT_PREDECT_STATUS_8814B \ + (BIT_MASK_BT_PREDECT_STATUS_8814B << BIT_SHIFT_BT_PREDECT_STATUS_8814B) +#define BIT_CLEAR_BT_PREDECT_STATUS_8814B(x) \ + ((x) & (~BITS_BT_PREDECT_STATUS_8814B)) +#define BIT_GET_BT_PREDECT_STATUS_8814B(x) \ + (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8814B) & \ + BIT_MASK_BT_PREDECT_STATUS_8814B) +#define BIT_SET_BT_PREDECT_STATUS_8814B(x, v) \ + (BIT_CLEAR_BT_PREDECT_STATUS_8814B(x) | BIT_BT_PREDECT_STATUS_8814B(v)) #define BIT_SHIFT_BT_CMD_INFO_8814B 0 #define BIT_MASK_BT_CMD_INFO_8814B 0xff -#define BIT_BT_CMD_INFO_8814B(x) (((x) & BIT_MASK_BT_CMD_INFO_8814B) << BIT_SHIFT_BT_CMD_INFO_8814B) -#define BIT_GET_BT_CMD_INFO_8814B(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8814B) & BIT_MASK_BT_CMD_INFO_8814B) - - +#define BIT_BT_CMD_INFO_8814B(x) \ + (((x) & BIT_MASK_BT_CMD_INFO_8814B) << BIT_SHIFT_BT_CMD_INFO_8814B) +#define BITS_BT_CMD_INFO_8814B \ + (BIT_MASK_BT_CMD_INFO_8814B << BIT_SHIFT_BT_CMD_INFO_8814B) +#define BIT_CLEAR_BT_CMD_INFO_8814B(x) ((x) & (~BITS_BT_CMD_INFO_8814B)) +#define BIT_GET_BT_CMD_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_BT_CMD_INFO_8814B) & BIT_MASK_BT_CMD_INFO_8814B) +#define BIT_SET_BT_CMD_INFO_8814B(x, v) \ + (BIT_CLEAR_BT_CMD_INFO_8814B(x) | BIT_BT_CMD_INFO_8814B(v)) /* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8814B */ #define BIT_EN_MAC_NULL_PKT_NOTIFY_8814B BIT(31) @@ -10720,41 +24635,67 @@ #define BIT_SHIFT_WLAN_RPT_DATA_8814B 16 #define BIT_MASK_WLAN_RPT_DATA_8814B 0xff -#define BIT_WLAN_RPT_DATA_8814B(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8814B) << BIT_SHIFT_WLAN_RPT_DATA_8814B) -#define BIT_GET_WLAN_RPT_DATA_8814B(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8814B) & BIT_MASK_WLAN_RPT_DATA_8814B) - - +#define BIT_WLAN_RPT_DATA_8814B(x) \ + (((x) & BIT_MASK_WLAN_RPT_DATA_8814B) << BIT_SHIFT_WLAN_RPT_DATA_8814B) +#define BITS_WLAN_RPT_DATA_8814B \ + (BIT_MASK_WLAN_RPT_DATA_8814B << BIT_SHIFT_WLAN_RPT_DATA_8814B) +#define BIT_CLEAR_WLAN_RPT_DATA_8814B(x) ((x) & (~BITS_WLAN_RPT_DATA_8814B)) +#define BIT_GET_WLAN_RPT_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8814B) & BIT_MASK_WLAN_RPT_DATA_8814B) +#define BIT_SET_WLAN_RPT_DATA_8814B(x, v) \ + (BIT_CLEAR_WLAN_RPT_DATA_8814B(x) | BIT_WLAN_RPT_DATA_8814B(v)) #define BIT_SHIFT_CMD_ID_8814B 8 #define BIT_MASK_CMD_ID_8814B 0xff -#define BIT_CMD_ID_8814B(x) (((x) & BIT_MASK_CMD_ID_8814B) << BIT_SHIFT_CMD_ID_8814B) -#define BIT_GET_CMD_ID_8814B(x) (((x) >> BIT_SHIFT_CMD_ID_8814B) & BIT_MASK_CMD_ID_8814B) - - +#define BIT_CMD_ID_8814B(x) \ + (((x) & BIT_MASK_CMD_ID_8814B) << BIT_SHIFT_CMD_ID_8814B) +#define BITS_CMD_ID_8814B (BIT_MASK_CMD_ID_8814B << BIT_SHIFT_CMD_ID_8814B) +#define BIT_CLEAR_CMD_ID_8814B(x) ((x) & (~BITS_CMD_ID_8814B)) +#define BIT_GET_CMD_ID_8814B(x) \ + (((x) >> BIT_SHIFT_CMD_ID_8814B) & BIT_MASK_CMD_ID_8814B) +#define BIT_SET_CMD_ID_8814B(x, v) \ + (BIT_CLEAR_CMD_ID_8814B(x) | BIT_CMD_ID_8814B(v)) #define BIT_SHIFT_BT_DATA_8814B 0 #define BIT_MASK_BT_DATA_8814B 0xff -#define BIT_BT_DATA_8814B(x) (((x) & BIT_MASK_BT_DATA_8814B) << BIT_SHIFT_BT_DATA_8814B) -#define BIT_GET_BT_DATA_8814B(x) (((x) >> BIT_SHIFT_BT_DATA_8814B) & BIT_MASK_BT_DATA_8814B) - - +#define BIT_BT_DATA_8814B(x) \ + (((x) & BIT_MASK_BT_DATA_8814B) << BIT_SHIFT_BT_DATA_8814B) +#define BITS_BT_DATA_8814B (BIT_MASK_BT_DATA_8814B << BIT_SHIFT_BT_DATA_8814B) +#define BIT_CLEAR_BT_DATA_8814B(x) ((x) & (~BITS_BT_DATA_8814B)) +#define BIT_GET_BT_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_BT_DATA_8814B) & BIT_MASK_BT_DATA_8814B) +#define BIT_SET_BT_DATA_8814B(x, v) \ + (BIT_CLEAR_BT_DATA_8814B(x) | BIT_BT_DATA_8814B(v)) /* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8814B */ #define BIT_SHIFT_WLAN_RPT_TO_8814B 0 #define BIT_MASK_WLAN_RPT_TO_8814B 0xff -#define BIT_WLAN_RPT_TO_8814B(x) (((x) & BIT_MASK_WLAN_RPT_TO_8814B) << BIT_SHIFT_WLAN_RPT_TO_8814B) -#define BIT_GET_WLAN_RPT_TO_8814B(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8814B) & BIT_MASK_WLAN_RPT_TO_8814B) - - +#define BIT_WLAN_RPT_TO_8814B(x) \ + (((x) & BIT_MASK_WLAN_RPT_TO_8814B) << BIT_SHIFT_WLAN_RPT_TO_8814B) +#define BITS_WLAN_RPT_TO_8814B \ + (BIT_MASK_WLAN_RPT_TO_8814B << BIT_SHIFT_WLAN_RPT_TO_8814B) +#define BIT_CLEAR_WLAN_RPT_TO_8814B(x) ((x) & (~BITS_WLAN_RPT_TO_8814B)) +#define BIT_GET_WLAN_RPT_TO_8814B(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_TO_8814B) & BIT_MASK_WLAN_RPT_TO_8814B) +#define BIT_SET_WLAN_RPT_TO_8814B(x, v) \ + (BIT_CLEAR_WLAN_RPT_TO_8814B(x) | BIT_WLAN_RPT_TO_8814B(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8814B */ #define BIT_SHIFT_ISOLATION_CHK_0_8814B 1 #define BIT_MASK_ISOLATION_CHK_0_8814B 0x7fffff -#define BIT_ISOLATION_CHK_0_8814B(x) (((x) & BIT_MASK_ISOLATION_CHK_0_8814B) << BIT_SHIFT_ISOLATION_CHK_0_8814B) -#define BIT_GET_ISOLATION_CHK_0_8814B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8814B) & BIT_MASK_ISOLATION_CHK_0_8814B) - +#define BIT_ISOLATION_CHK_0_8814B(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_0_8814B) \ + << BIT_SHIFT_ISOLATION_CHK_0_8814B) +#define BITS_ISOLATION_CHK_0_8814B \ + (BIT_MASK_ISOLATION_CHK_0_8814B << BIT_SHIFT_ISOLATION_CHK_0_8814B) +#define BIT_CLEAR_ISOLATION_CHK_0_8814B(x) ((x) & (~BITS_ISOLATION_CHK_0_8814B)) +#define BIT_GET_ISOLATION_CHK_0_8814B(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8814B) & \ + BIT_MASK_ISOLATION_CHK_0_8814B) +#define BIT_SET_ISOLATION_CHK_0_8814B(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_0_8814B(x) | BIT_ISOLATION_CHK_0_8814B(v)) #define BIT_ISOLATION_EN_8814B BIT(0) @@ -10762,19 +24703,33 @@ #define BIT_SHIFT_ISOLATION_CHK_1_8814B 0 #define BIT_MASK_ISOLATION_CHK_1_8814B 0xffffffffL -#define BIT_ISOLATION_CHK_1_8814B(x) (((x) & BIT_MASK_ISOLATION_CHK_1_8814B) << BIT_SHIFT_ISOLATION_CHK_1_8814B) -#define BIT_GET_ISOLATION_CHK_1_8814B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8814B) & BIT_MASK_ISOLATION_CHK_1_8814B) - - +#define BIT_ISOLATION_CHK_1_8814B(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_1_8814B) \ + << BIT_SHIFT_ISOLATION_CHK_1_8814B) +#define BITS_ISOLATION_CHK_1_8814B \ + (BIT_MASK_ISOLATION_CHK_1_8814B << BIT_SHIFT_ISOLATION_CHK_1_8814B) +#define BIT_CLEAR_ISOLATION_CHK_1_8814B(x) ((x) & (~BITS_ISOLATION_CHK_1_8814B)) +#define BIT_GET_ISOLATION_CHK_1_8814B(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8814B) & \ + BIT_MASK_ISOLATION_CHK_1_8814B) +#define BIT_SET_ISOLATION_CHK_1_8814B(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_1_8814B(x) | BIT_ISOLATION_CHK_1_8814B(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8814B */ #define BIT_SHIFT_ISOLATION_CHK_2_8814B 0 #define BIT_MASK_ISOLATION_CHK_2_8814B 0xffffff -#define BIT_ISOLATION_CHK_2_8814B(x) (((x) & BIT_MASK_ISOLATION_CHK_2_8814B) << BIT_SHIFT_ISOLATION_CHK_2_8814B) -#define BIT_GET_ISOLATION_CHK_2_8814B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8814B) & BIT_MASK_ISOLATION_CHK_2_8814B) - - +#define BIT_ISOLATION_CHK_2_8814B(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_2_8814B) \ + << BIT_SHIFT_ISOLATION_CHK_2_8814B) +#define BITS_ISOLATION_CHK_2_8814B \ + (BIT_MASK_ISOLATION_CHK_2_8814B << BIT_SHIFT_ISOLATION_CHK_2_8814B) +#define BIT_CLEAR_ISOLATION_CHK_2_8814B(x) ((x) & (~BITS_ISOLATION_CHK_2_8814B)) +#define BIT_GET_ISOLATION_CHK_2_8814B(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8814B) & \ + BIT_MASK_ISOLATION_CHK_2_8814B) +#define BIT_SET_ISOLATION_CHK_2_8814B(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_2_8814B(x) | BIT_ISOLATION_CHK_2_8814B(v)) /* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8814B */ #define BIT_BT_HID_ISR_8814B BIT(7) @@ -10790,25 +24745,45 @@ #define BIT_SHIFT_BT_TIME_8814B 6 #define BIT_MASK_BT_TIME_8814B 0x3ffffff -#define BIT_BT_TIME_8814B(x) (((x) & BIT_MASK_BT_TIME_8814B) << BIT_SHIFT_BT_TIME_8814B) -#define BIT_GET_BT_TIME_8814B(x) (((x) >> BIT_SHIFT_BT_TIME_8814B) & BIT_MASK_BT_TIME_8814B) - - +#define BIT_BT_TIME_8814B(x) \ + (((x) & BIT_MASK_BT_TIME_8814B) << BIT_SHIFT_BT_TIME_8814B) +#define BITS_BT_TIME_8814B (BIT_MASK_BT_TIME_8814B << BIT_SHIFT_BT_TIME_8814B) +#define BIT_CLEAR_BT_TIME_8814B(x) ((x) & (~BITS_BT_TIME_8814B)) +#define BIT_GET_BT_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_BT_TIME_8814B) & BIT_MASK_BT_TIME_8814B) +#define BIT_SET_BT_TIME_8814B(x, v) \ + (BIT_CLEAR_BT_TIME_8814B(x) | BIT_BT_TIME_8814B(v)) #define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B 0 #define BIT_MASK_BT_RPT_SAMPLE_RATE_8814B 0x3f -#define BIT_BT_RPT_SAMPLE_RATE_8814B(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8814B) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) -#define BIT_GET_BT_RPT_SAMPLE_RATE_8814B(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) & BIT_MASK_BT_RPT_SAMPLE_RATE_8814B) - - +#define BIT_BT_RPT_SAMPLE_RATE_8814B(x) \ + (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8814B) \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) +#define BITS_BT_RPT_SAMPLE_RATE_8814B \ + (BIT_MASK_BT_RPT_SAMPLE_RATE_8814B \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8814B(x) \ + ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8814B)) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8814B(x) \ + (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) & \ + BIT_MASK_BT_RPT_SAMPLE_RATE_8814B) +#define BIT_SET_BT_RPT_SAMPLE_RATE_8814B(x, v) \ + (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8814B(x) | \ + BIT_BT_RPT_SAMPLE_RATE_8814B(v)) /* 2 REG_BT_ACT_REGISTER_8814B */ #define BIT_SHIFT_BT_EISR_EN_8814B 16 #define BIT_MASK_BT_EISR_EN_8814B 0xff -#define BIT_BT_EISR_EN_8814B(x) (((x) & BIT_MASK_BT_EISR_EN_8814B) << BIT_SHIFT_BT_EISR_EN_8814B) -#define BIT_GET_BT_EISR_EN_8814B(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8814B) & BIT_MASK_BT_EISR_EN_8814B) - +#define BIT_BT_EISR_EN_8814B(x) \ + (((x) & BIT_MASK_BT_EISR_EN_8814B) << BIT_SHIFT_BT_EISR_EN_8814B) +#define BITS_BT_EISR_EN_8814B \ + (BIT_MASK_BT_EISR_EN_8814B << BIT_SHIFT_BT_EISR_EN_8814B) +#define BIT_CLEAR_BT_EISR_EN_8814B(x) ((x) & (~BITS_BT_EISR_EN_8814B)) +#define BIT_GET_BT_EISR_EN_8814B(x) \ + (((x) >> BIT_SHIFT_BT_EISR_EN_8814B) & BIT_MASK_BT_EISR_EN_8814B) +#define BIT_SET_BT_EISR_EN_8814B(x, v) \ + (BIT_CLEAR_BT_EISR_EN_8814B(x) | BIT_BT_EISR_EN_8814B(v)) #define BIT_BT_ACT_FALLING_ISR_8814B BIT(10) #define BIT_BT_ACT_RISING_ISR_8814B BIT(9) @@ -10816,19 +24791,29 @@ #define BIT_SHIFT_BT_CH_8814B 0 #define BIT_MASK_BT_CH_8814B 0xff -#define BIT_BT_CH_8814B(x) (((x) & BIT_MASK_BT_CH_8814B) << BIT_SHIFT_BT_CH_8814B) -#define BIT_GET_BT_CH_8814B(x) (((x) >> BIT_SHIFT_BT_CH_8814B) & BIT_MASK_BT_CH_8814B) - - +#define BIT_BT_CH_8814B(x) \ + (((x) & BIT_MASK_BT_CH_8814B) << BIT_SHIFT_BT_CH_8814B) +#define BITS_BT_CH_8814B (BIT_MASK_BT_CH_8814B << BIT_SHIFT_BT_CH_8814B) +#define BIT_CLEAR_BT_CH_8814B(x) ((x) & (~BITS_BT_CH_8814B)) +#define BIT_GET_BT_CH_8814B(x) \ + (((x) >> BIT_SHIFT_BT_CH_8814B) & BIT_MASK_BT_CH_8814B) +#define BIT_SET_BT_CH_8814B(x, v) \ + (BIT_CLEAR_BT_CH_8814B(x) | BIT_BT_CH_8814B(v)) /* 2 REG_OBFF_CTRL_BASIC_8814B */ #define BIT_OBFF_EN_V1_8814B BIT(31) #define BIT_SHIFT_OBFF_STATE_V1_8814B 28 #define BIT_MASK_OBFF_STATE_V1_8814B 0x3 -#define BIT_OBFF_STATE_V1_8814B(x) (((x) & BIT_MASK_OBFF_STATE_V1_8814B) << BIT_SHIFT_OBFF_STATE_V1_8814B) -#define BIT_GET_OBFF_STATE_V1_8814B(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8814B) & BIT_MASK_OBFF_STATE_V1_8814B) - +#define BIT_OBFF_STATE_V1_8814B(x) \ + (((x) & BIT_MASK_OBFF_STATE_V1_8814B) << BIT_SHIFT_OBFF_STATE_V1_8814B) +#define BITS_OBFF_STATE_V1_8814B \ + (BIT_MASK_OBFF_STATE_V1_8814B << BIT_SHIFT_OBFF_STATE_V1_8814B) +#define BIT_CLEAR_OBFF_STATE_V1_8814B(x) ((x) & (~BITS_OBFF_STATE_V1_8814B)) +#define BIT_GET_OBFF_STATE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_OBFF_STATE_V1_8814B) & BIT_MASK_OBFF_STATE_V1_8814B) +#define BIT_SET_OBFF_STATE_V1_8814B(x, v) \ + (BIT_CLEAR_OBFF_STATE_V1_8814B(x) | BIT_OBFF_STATE_V1_8814B(v)) #define BIT_OBFF_ACT_RXDMA_EN_8814B BIT(27) #define BIT_OBFF_BLOCK_INT_EN_8814B BIT(26) @@ -10837,30 +24822,51 @@ #define BIT_SHIFT_WAKE_MAX_PLS_8814B 20 #define BIT_MASK_WAKE_MAX_PLS_8814B 0x7 -#define BIT_WAKE_MAX_PLS_8814B(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8814B) << BIT_SHIFT_WAKE_MAX_PLS_8814B) -#define BIT_GET_WAKE_MAX_PLS_8814B(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8814B) & BIT_MASK_WAKE_MAX_PLS_8814B) - - +#define BIT_WAKE_MAX_PLS_8814B(x) \ + (((x) & BIT_MASK_WAKE_MAX_PLS_8814B) << BIT_SHIFT_WAKE_MAX_PLS_8814B) +#define BITS_WAKE_MAX_PLS_8814B \ + (BIT_MASK_WAKE_MAX_PLS_8814B << BIT_SHIFT_WAKE_MAX_PLS_8814B) +#define BIT_CLEAR_WAKE_MAX_PLS_8814B(x) ((x) & (~BITS_WAKE_MAX_PLS_8814B)) +#define BIT_GET_WAKE_MAX_PLS_8814B(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8814B) & BIT_MASK_WAKE_MAX_PLS_8814B) +#define BIT_SET_WAKE_MAX_PLS_8814B(x, v) \ + (BIT_CLEAR_WAKE_MAX_PLS_8814B(x) | BIT_WAKE_MAX_PLS_8814B(v)) #define BIT_SHIFT_WAKE_MIN_PLS_8814B 16 #define BIT_MASK_WAKE_MIN_PLS_8814B 0x7 -#define BIT_WAKE_MIN_PLS_8814B(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8814B) << BIT_SHIFT_WAKE_MIN_PLS_8814B) -#define BIT_GET_WAKE_MIN_PLS_8814B(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8814B) & BIT_MASK_WAKE_MIN_PLS_8814B) - - +#define BIT_WAKE_MIN_PLS_8814B(x) \ + (((x) & BIT_MASK_WAKE_MIN_PLS_8814B) << BIT_SHIFT_WAKE_MIN_PLS_8814B) +#define BITS_WAKE_MIN_PLS_8814B \ + (BIT_MASK_WAKE_MIN_PLS_8814B << BIT_SHIFT_WAKE_MIN_PLS_8814B) +#define BIT_CLEAR_WAKE_MIN_PLS_8814B(x) ((x) & (~BITS_WAKE_MIN_PLS_8814B)) +#define BIT_GET_WAKE_MIN_PLS_8814B(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8814B) & BIT_MASK_WAKE_MIN_PLS_8814B) +#define BIT_SET_WAKE_MIN_PLS_8814B(x, v) \ + (BIT_CLEAR_WAKE_MIN_PLS_8814B(x) | BIT_WAKE_MIN_PLS_8814B(v)) #define BIT_SHIFT_WAKE_MAX_F2F_8814B 12 #define BIT_MASK_WAKE_MAX_F2F_8814B 0x7 -#define BIT_WAKE_MAX_F2F_8814B(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8814B) << BIT_SHIFT_WAKE_MAX_F2F_8814B) -#define BIT_GET_WAKE_MAX_F2F_8814B(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8814B) & BIT_MASK_WAKE_MAX_F2F_8814B) - - +#define BIT_WAKE_MAX_F2F_8814B(x) \ + (((x) & BIT_MASK_WAKE_MAX_F2F_8814B) << BIT_SHIFT_WAKE_MAX_F2F_8814B) +#define BITS_WAKE_MAX_F2F_8814B \ + (BIT_MASK_WAKE_MAX_F2F_8814B << BIT_SHIFT_WAKE_MAX_F2F_8814B) +#define BIT_CLEAR_WAKE_MAX_F2F_8814B(x) ((x) & (~BITS_WAKE_MAX_F2F_8814B)) +#define BIT_GET_WAKE_MAX_F2F_8814B(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8814B) & BIT_MASK_WAKE_MAX_F2F_8814B) +#define BIT_SET_WAKE_MAX_F2F_8814B(x, v) \ + (BIT_CLEAR_WAKE_MAX_F2F_8814B(x) | BIT_WAKE_MAX_F2F_8814B(v)) #define BIT_SHIFT_WAKE_MIN_F2F_8814B 8 #define BIT_MASK_WAKE_MIN_F2F_8814B 0x7 -#define BIT_WAKE_MIN_F2F_8814B(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8814B) << BIT_SHIFT_WAKE_MIN_F2F_8814B) -#define BIT_GET_WAKE_MIN_F2F_8814B(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8814B) & BIT_MASK_WAKE_MIN_F2F_8814B) - +#define BIT_WAKE_MIN_F2F_8814B(x) \ + (((x) & BIT_MASK_WAKE_MIN_F2F_8814B) << BIT_SHIFT_WAKE_MIN_F2F_8814B) +#define BITS_WAKE_MIN_F2F_8814B \ + (BIT_MASK_WAKE_MIN_F2F_8814B << BIT_SHIFT_WAKE_MIN_F2F_8814B) +#define BIT_CLEAR_WAKE_MIN_F2F_8814B(x) ((x) & (~BITS_WAKE_MIN_F2F_8814B)) +#define BIT_GET_WAKE_MIN_F2F_8814B(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8814B) & BIT_MASK_WAKE_MIN_F2F_8814B) +#define BIT_SET_WAKE_MIN_F2F_8814B(x, v) \ + (BIT_CLEAR_WAKE_MIN_F2F_8814B(x) | BIT_WAKE_MIN_F2F_8814B(v)) #define BIT_APP_CPU_ACT_V1_8814B BIT(3) #define BIT_APP_OBFF_V1_8814B BIT(2) @@ -10871,31 +24877,65 @@ #define BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B 24 #define BIT_MASK_RX_HIGH_TIMER_IDX_8814B 0x7 -#define BIT_RX_HIGH_TIMER_IDX_8814B(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8814B) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) -#define BIT_GET_RX_HIGH_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) & BIT_MASK_RX_HIGH_TIMER_IDX_8814B) - - +#define BIT_RX_HIGH_TIMER_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8814B) \ + << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) +#define BITS_RX_HIGH_TIMER_IDX_8814B \ + (BIT_MASK_RX_HIGH_TIMER_IDX_8814B << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8814B(x) \ + ((x) & (~BITS_RX_HIGH_TIMER_IDX_8814B)) +#define BIT_GET_RX_HIGH_TIMER_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) & \ + BIT_MASK_RX_HIGH_TIMER_IDX_8814B) +#define BIT_SET_RX_HIGH_TIMER_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_HIGH_TIMER_IDX_8814B(x) | BIT_RX_HIGH_TIMER_IDX_8814B(v)) #define BIT_SHIFT_RX_MED_TIMER_IDX_8814B 16 #define BIT_MASK_RX_MED_TIMER_IDX_8814B 0x7 -#define BIT_RX_MED_TIMER_IDX_8814B(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8814B) << BIT_SHIFT_RX_MED_TIMER_IDX_8814B) -#define BIT_GET_RX_MED_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8814B) & BIT_MASK_RX_MED_TIMER_IDX_8814B) - - +#define BIT_RX_MED_TIMER_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_MED_TIMER_IDX_8814B) \ + << BIT_SHIFT_RX_MED_TIMER_IDX_8814B) +#define BITS_RX_MED_TIMER_IDX_8814B \ + (BIT_MASK_RX_MED_TIMER_IDX_8814B << BIT_SHIFT_RX_MED_TIMER_IDX_8814B) +#define BIT_CLEAR_RX_MED_TIMER_IDX_8814B(x) \ + ((x) & (~BITS_RX_MED_TIMER_IDX_8814B)) +#define BIT_GET_RX_MED_TIMER_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8814B) & \ + BIT_MASK_RX_MED_TIMER_IDX_8814B) +#define BIT_SET_RX_MED_TIMER_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_MED_TIMER_IDX_8814B(x) | BIT_RX_MED_TIMER_IDX_8814B(v)) #define BIT_SHIFT_RX_LOW_TIMER_IDX_8814B 8 #define BIT_MASK_RX_LOW_TIMER_IDX_8814B 0x7 -#define BIT_RX_LOW_TIMER_IDX_8814B(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8814B) << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) -#define BIT_GET_RX_LOW_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) & BIT_MASK_RX_LOW_TIMER_IDX_8814B) - - +#define BIT_RX_LOW_TIMER_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8814B) \ + << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) +#define BITS_RX_LOW_TIMER_IDX_8814B \ + (BIT_MASK_RX_LOW_TIMER_IDX_8814B << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) +#define BIT_CLEAR_RX_LOW_TIMER_IDX_8814B(x) \ + ((x) & (~BITS_RX_LOW_TIMER_IDX_8814B)) +#define BIT_GET_RX_LOW_TIMER_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) & \ + BIT_MASK_RX_LOW_TIMER_IDX_8814B) +#define BIT_SET_RX_LOW_TIMER_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_LOW_TIMER_IDX_8814B(x) | BIT_RX_LOW_TIMER_IDX_8814B(v)) #define BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B 0 #define BIT_MASK_OBFF_INT_TIMER_IDX_8814B 0x7 -#define BIT_OBFF_INT_TIMER_IDX_8814B(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8814B) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) -#define BIT_GET_OBFF_INT_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) & BIT_MASK_OBFF_INT_TIMER_IDX_8814B) - - +#define BIT_OBFF_INT_TIMER_IDX_8814B(x) \ + (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8814B) \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) +#define BITS_OBFF_INT_TIMER_IDX_8814B \ + (BIT_MASK_OBFF_INT_TIMER_IDX_8814B \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8814B(x) \ + ((x) & (~BITS_OBFF_INT_TIMER_IDX_8814B)) +#define BIT_GET_OBFF_INT_TIMER_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) & \ + BIT_MASK_OBFF_INT_TIMER_IDX_8814B) +#define BIT_SET_OBFF_INT_TIMER_IDX_8814B(x, v) \ + (BIT_CLEAR_OBFF_INT_TIMER_IDX_8814B(x) | \ + BIT_OBFF_INT_TIMER_IDX_8814B(v)) /* 2 REG_LTR_CTRL_BASIC_8814B */ #define BIT_LTR_EN_V1_8814B BIT(31) @@ -10911,180 +24951,340 @@ #define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B 20 #define BIT_MASK_HIGH_RATE_TRIG_SEL_8814B 0x3 -#define BIT_HIGH_RATE_TRIG_SEL_8814B(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8814B) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) -#define BIT_GET_HIGH_RATE_TRIG_SEL_8814B(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) & BIT_MASK_HIGH_RATE_TRIG_SEL_8814B) - - +#define BIT_HIGH_RATE_TRIG_SEL_8814B(x) \ + (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8814B) \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) +#define BITS_HIGH_RATE_TRIG_SEL_8814B \ + (BIT_MASK_HIGH_RATE_TRIG_SEL_8814B \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8814B(x) \ + ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8814B)) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) & \ + BIT_MASK_HIGH_RATE_TRIG_SEL_8814B) +#define BIT_SET_HIGH_RATE_TRIG_SEL_8814B(x, v) \ + (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8814B(x) | \ + BIT_HIGH_RATE_TRIG_SEL_8814B(v)) #define BIT_SHIFT_MED_RATE_TRIG_SEL_8814B 18 #define BIT_MASK_MED_RATE_TRIG_SEL_8814B 0x3 -#define BIT_MED_RATE_TRIG_SEL_8814B(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8814B) << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) -#define BIT_GET_MED_RATE_TRIG_SEL_8814B(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) & BIT_MASK_MED_RATE_TRIG_SEL_8814B) - - +#define BIT_MED_RATE_TRIG_SEL_8814B(x) \ + (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8814B) \ + << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) +#define BITS_MED_RATE_TRIG_SEL_8814B \ + (BIT_MASK_MED_RATE_TRIG_SEL_8814B << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) +#define BIT_CLEAR_MED_RATE_TRIG_SEL_8814B(x) \ + ((x) & (~BITS_MED_RATE_TRIG_SEL_8814B)) +#define BIT_GET_MED_RATE_TRIG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) & \ + BIT_MASK_MED_RATE_TRIG_SEL_8814B) +#define BIT_SET_MED_RATE_TRIG_SEL_8814B(x, v) \ + (BIT_CLEAR_MED_RATE_TRIG_SEL_8814B(x) | BIT_MED_RATE_TRIG_SEL_8814B(v)) #define BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B 16 #define BIT_MASK_LOW_RATE_TRIG_SEL_8814B 0x3 -#define BIT_LOW_RATE_TRIG_SEL_8814B(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8814B) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) -#define BIT_GET_LOW_RATE_TRIG_SEL_8814B(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) & BIT_MASK_LOW_RATE_TRIG_SEL_8814B) - - +#define BIT_LOW_RATE_TRIG_SEL_8814B(x) \ + (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8814B) \ + << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) +#define BITS_LOW_RATE_TRIG_SEL_8814B \ + (BIT_MASK_LOW_RATE_TRIG_SEL_8814B << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8814B(x) \ + ((x) & (~BITS_LOW_RATE_TRIG_SEL_8814B)) +#define BIT_GET_LOW_RATE_TRIG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) & \ + BIT_MASK_LOW_RATE_TRIG_SEL_8814B) +#define BIT_SET_LOW_RATE_TRIG_SEL_8814B(x, v) \ + (BIT_CLEAR_LOW_RATE_TRIG_SEL_8814B(x) | BIT_LOW_RATE_TRIG_SEL_8814B(v)) #define BIT_SHIFT_HIGH_RATE_BD_IDX_8814B 8 #define BIT_MASK_HIGH_RATE_BD_IDX_8814B 0x7f -#define BIT_HIGH_RATE_BD_IDX_8814B(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8814B) << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) -#define BIT_GET_HIGH_RATE_BD_IDX_8814B(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) & BIT_MASK_HIGH_RATE_BD_IDX_8814B) - - +#define BIT_HIGH_RATE_BD_IDX_8814B(x) \ + (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8814B) \ + << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) +#define BITS_HIGH_RATE_BD_IDX_8814B \ + (BIT_MASK_HIGH_RATE_BD_IDX_8814B << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) +#define BIT_CLEAR_HIGH_RATE_BD_IDX_8814B(x) \ + ((x) & (~BITS_HIGH_RATE_BD_IDX_8814B)) +#define BIT_GET_HIGH_RATE_BD_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) & \ + BIT_MASK_HIGH_RATE_BD_IDX_8814B) +#define BIT_SET_HIGH_RATE_BD_IDX_8814B(x, v) \ + (BIT_CLEAR_HIGH_RATE_BD_IDX_8814B(x) | BIT_HIGH_RATE_BD_IDX_8814B(v)) #define BIT_SHIFT_LOW_RATE_BD_IDX_8814B 0 #define BIT_MASK_LOW_RATE_BD_IDX_8814B 0x7f -#define BIT_LOW_RATE_BD_IDX_8814B(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8814B) << BIT_SHIFT_LOW_RATE_BD_IDX_8814B) -#define BIT_GET_LOW_RATE_BD_IDX_8814B(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8814B) & BIT_MASK_LOW_RATE_BD_IDX_8814B) - - +#define BIT_LOW_RATE_BD_IDX_8814B(x) \ + (((x) & BIT_MASK_LOW_RATE_BD_IDX_8814B) \ + << BIT_SHIFT_LOW_RATE_BD_IDX_8814B) +#define BITS_LOW_RATE_BD_IDX_8814B \ + (BIT_MASK_LOW_RATE_BD_IDX_8814B << BIT_SHIFT_LOW_RATE_BD_IDX_8814B) +#define BIT_CLEAR_LOW_RATE_BD_IDX_8814B(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8814B)) +#define BIT_GET_LOW_RATE_BD_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8814B) & \ + BIT_MASK_LOW_RATE_BD_IDX_8814B) +#define BIT_SET_LOW_RATE_BD_IDX_8814B(x, v) \ + (BIT_CLEAR_LOW_RATE_BD_IDX_8814B(x) | BIT_LOW_RATE_BD_IDX_8814B(v)) /* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8814B */ #define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B 24 #define BIT_MASK_RX_EMPTY_TIMER_IDX_8814B 0x7 -#define BIT_RX_EMPTY_TIMER_IDX_8814B(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8814B) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) -#define BIT_GET_RX_EMPTY_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) & BIT_MASK_RX_EMPTY_TIMER_IDX_8814B) - - +#define BIT_RX_EMPTY_TIMER_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8814B) \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) +#define BITS_RX_EMPTY_TIMER_IDX_8814B \ + (BIT_MASK_RX_EMPTY_TIMER_IDX_8814B \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8814B(x) \ + ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8814B)) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) & \ + BIT_MASK_RX_EMPTY_TIMER_IDX_8814B) +#define BIT_SET_RX_EMPTY_TIMER_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8814B(x) | \ + BIT_RX_EMPTY_TIMER_IDX_8814B(v)) #define BIT_SHIFT_RX_AFULL_TH_IDX_8814B 20 #define BIT_MASK_RX_AFULL_TH_IDX_8814B 0x7 -#define BIT_RX_AFULL_TH_IDX_8814B(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8814B) << BIT_SHIFT_RX_AFULL_TH_IDX_8814B) -#define BIT_GET_RX_AFULL_TH_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8814B) & BIT_MASK_RX_AFULL_TH_IDX_8814B) - - +#define BIT_RX_AFULL_TH_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_AFULL_TH_IDX_8814B) \ + << BIT_SHIFT_RX_AFULL_TH_IDX_8814B) +#define BITS_RX_AFULL_TH_IDX_8814B \ + (BIT_MASK_RX_AFULL_TH_IDX_8814B << BIT_SHIFT_RX_AFULL_TH_IDX_8814B) +#define BIT_CLEAR_RX_AFULL_TH_IDX_8814B(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8814B)) +#define BIT_GET_RX_AFULL_TH_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8814B) & \ + BIT_MASK_RX_AFULL_TH_IDX_8814B) +#define BIT_SET_RX_AFULL_TH_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_AFULL_TH_IDX_8814B(x) | BIT_RX_AFULL_TH_IDX_8814B(v)) #define BIT_SHIFT_RX_HIGH_TH_IDX_8814B 16 #define BIT_MASK_RX_HIGH_TH_IDX_8814B 0x7 -#define BIT_RX_HIGH_TH_IDX_8814B(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8814B) << BIT_SHIFT_RX_HIGH_TH_IDX_8814B) -#define BIT_GET_RX_HIGH_TH_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8814B) & BIT_MASK_RX_HIGH_TH_IDX_8814B) - - +#define BIT_RX_HIGH_TH_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_HIGH_TH_IDX_8814B) \ + << BIT_SHIFT_RX_HIGH_TH_IDX_8814B) +#define BITS_RX_HIGH_TH_IDX_8814B \ + (BIT_MASK_RX_HIGH_TH_IDX_8814B << BIT_SHIFT_RX_HIGH_TH_IDX_8814B) +#define BIT_CLEAR_RX_HIGH_TH_IDX_8814B(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8814B)) +#define BIT_GET_RX_HIGH_TH_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8814B) & \ + BIT_MASK_RX_HIGH_TH_IDX_8814B) +#define BIT_SET_RX_HIGH_TH_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_HIGH_TH_IDX_8814B(x) | BIT_RX_HIGH_TH_IDX_8814B(v)) #define BIT_SHIFT_RX_MED_TH_IDX_8814B 12 #define BIT_MASK_RX_MED_TH_IDX_8814B 0x7 -#define BIT_RX_MED_TH_IDX_8814B(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8814B) << BIT_SHIFT_RX_MED_TH_IDX_8814B) -#define BIT_GET_RX_MED_TH_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8814B) & BIT_MASK_RX_MED_TH_IDX_8814B) - - +#define BIT_RX_MED_TH_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_MED_TH_IDX_8814B) << BIT_SHIFT_RX_MED_TH_IDX_8814B) +#define BITS_RX_MED_TH_IDX_8814B \ + (BIT_MASK_RX_MED_TH_IDX_8814B << BIT_SHIFT_RX_MED_TH_IDX_8814B) +#define BIT_CLEAR_RX_MED_TH_IDX_8814B(x) ((x) & (~BITS_RX_MED_TH_IDX_8814B)) +#define BIT_GET_RX_MED_TH_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8814B) & BIT_MASK_RX_MED_TH_IDX_8814B) +#define BIT_SET_RX_MED_TH_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_MED_TH_IDX_8814B(x) | BIT_RX_MED_TH_IDX_8814B(v)) #define BIT_SHIFT_RX_LOW_TH_IDX_8814B 8 #define BIT_MASK_RX_LOW_TH_IDX_8814B 0x7 -#define BIT_RX_LOW_TH_IDX_8814B(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8814B) << BIT_SHIFT_RX_LOW_TH_IDX_8814B) -#define BIT_GET_RX_LOW_TH_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8814B) & BIT_MASK_RX_LOW_TH_IDX_8814B) - - +#define BIT_RX_LOW_TH_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_LOW_TH_IDX_8814B) << BIT_SHIFT_RX_LOW_TH_IDX_8814B) +#define BITS_RX_LOW_TH_IDX_8814B \ + (BIT_MASK_RX_LOW_TH_IDX_8814B << BIT_SHIFT_RX_LOW_TH_IDX_8814B) +#define BIT_CLEAR_RX_LOW_TH_IDX_8814B(x) ((x) & (~BITS_RX_LOW_TH_IDX_8814B)) +#define BIT_GET_RX_LOW_TH_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8814B) & BIT_MASK_RX_LOW_TH_IDX_8814B) +#define BIT_SET_RX_LOW_TH_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_LOW_TH_IDX_8814B(x) | BIT_RX_LOW_TH_IDX_8814B(v)) #define BIT_SHIFT_LTR_SPACE_IDX_8814B 4 #define BIT_MASK_LTR_SPACE_IDX_8814B 0x3 -#define BIT_LTR_SPACE_IDX_8814B(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8814B) << BIT_SHIFT_LTR_SPACE_IDX_8814B) -#define BIT_GET_LTR_SPACE_IDX_8814B(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8814B) & BIT_MASK_LTR_SPACE_IDX_8814B) - - +#define BIT_LTR_SPACE_IDX_8814B(x) \ + (((x) & BIT_MASK_LTR_SPACE_IDX_8814B) << BIT_SHIFT_LTR_SPACE_IDX_8814B) +#define BITS_LTR_SPACE_IDX_8814B \ + (BIT_MASK_LTR_SPACE_IDX_8814B << BIT_SHIFT_LTR_SPACE_IDX_8814B) +#define BIT_CLEAR_LTR_SPACE_IDX_8814B(x) ((x) & (~BITS_LTR_SPACE_IDX_8814B)) +#define BIT_GET_LTR_SPACE_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8814B) & BIT_MASK_LTR_SPACE_IDX_8814B) +#define BIT_SET_LTR_SPACE_IDX_8814B(x, v) \ + (BIT_CLEAR_LTR_SPACE_IDX_8814B(x) | BIT_LTR_SPACE_IDX_8814B(v)) #define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B 0 #define BIT_MASK_LTR_IDLE_TIMER_IDX_8814B 0x7 -#define BIT_LTR_IDLE_TIMER_IDX_8814B(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8814B) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) -#define BIT_GET_LTR_IDLE_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) & BIT_MASK_LTR_IDLE_TIMER_IDX_8814B) - - +#define BIT_LTR_IDLE_TIMER_IDX_8814B(x) \ + (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8814B) \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) +#define BITS_LTR_IDLE_TIMER_IDX_8814B \ + (BIT_MASK_LTR_IDLE_TIMER_IDX_8814B \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8814B(x) \ + ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8814B)) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) & \ + BIT_MASK_LTR_IDLE_TIMER_IDX_8814B) +#define BIT_SET_LTR_IDLE_TIMER_IDX_8814B(x, v) \ + (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8814B(x) | \ + BIT_LTR_IDLE_TIMER_IDX_8814B(v)) /* 2 REG_LTR_IDLE_LATENCY_V1_8814B */ #define BIT_SHIFT_LTR_IDLE_L_8814B 0 #define BIT_MASK_LTR_IDLE_L_8814B 0xffffffffL -#define BIT_LTR_IDLE_L_8814B(x) (((x) & BIT_MASK_LTR_IDLE_L_8814B) << BIT_SHIFT_LTR_IDLE_L_8814B) -#define BIT_GET_LTR_IDLE_L_8814B(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8814B) & BIT_MASK_LTR_IDLE_L_8814B) - - +#define BIT_LTR_IDLE_L_8814B(x) \ + (((x) & BIT_MASK_LTR_IDLE_L_8814B) << BIT_SHIFT_LTR_IDLE_L_8814B) +#define BITS_LTR_IDLE_L_8814B \ + (BIT_MASK_LTR_IDLE_L_8814B << BIT_SHIFT_LTR_IDLE_L_8814B) +#define BIT_CLEAR_LTR_IDLE_L_8814B(x) ((x) & (~BITS_LTR_IDLE_L_8814B)) +#define BIT_GET_LTR_IDLE_L_8814B(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_L_8814B) & BIT_MASK_LTR_IDLE_L_8814B) +#define BIT_SET_LTR_IDLE_L_8814B(x, v) \ + (BIT_CLEAR_LTR_IDLE_L_8814B(x) | BIT_LTR_IDLE_L_8814B(v)) /* 2 REG_LTR_ACTIVE_LATENCY_V1_8814B */ #define BIT_SHIFT_LTR_ACT_L_8814B 0 #define BIT_MASK_LTR_ACT_L_8814B 0xffffffffL -#define BIT_LTR_ACT_L_8814B(x) (((x) & BIT_MASK_LTR_ACT_L_8814B) << BIT_SHIFT_LTR_ACT_L_8814B) -#define BIT_GET_LTR_ACT_L_8814B(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8814B) & BIT_MASK_LTR_ACT_L_8814B) - - - -/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8814B */ - -#define BIT_SHIFT_TRAIN_STA_ADDR_0_8814B 0 -#define BIT_MASK_TRAIN_STA_ADDR_0_8814B 0xffffffffL -#define BIT_TRAIN_STA_ADDR_0_8814B(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8814B) << BIT_SHIFT_TRAIN_STA_ADDR_0_8814B) -#define BIT_GET_TRAIN_STA_ADDR_0_8814B(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8814B) & BIT_MASK_TRAIN_STA_ADDR_0_8814B) - - - -/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8814B */ +#define BIT_LTR_ACT_L_8814B(x) \ + (((x) & BIT_MASK_LTR_ACT_L_8814B) << BIT_SHIFT_LTR_ACT_L_8814B) +#define BITS_LTR_ACT_L_8814B \ + (BIT_MASK_LTR_ACT_L_8814B << BIT_SHIFT_LTR_ACT_L_8814B) +#define BIT_CLEAR_LTR_ACT_L_8814B(x) ((x) & (~BITS_LTR_ACT_L_8814B)) +#define BIT_GET_LTR_ACT_L_8814B(x) \ + (((x) >> BIT_SHIFT_LTR_ACT_L_8814B) & BIT_MASK_LTR_ACT_L_8814B) +#define BIT_SET_LTR_ACT_L_8814B(x, v) \ + (BIT_CLEAR_LTR_ACT_L_8814B(x) | BIT_LTR_ACT_L_8814B(v)) + +#define BIT_SHIFT_ANT_ADDR2_1_8814B 0 +#define BIT_MASK_ANT_ADDR2_1_8814B 0xffffffffL +#define BIT_ANT_ADDR2_1_8814B(x) \ + (((x) & BIT_MASK_ANT_ADDR2_1_8814B) << BIT_SHIFT_ANT_ADDR2_1_8814B) +#define BITS_ANT_ADDR2_1_8814B \ + (BIT_MASK_ANT_ADDR2_1_8814B << BIT_SHIFT_ANT_ADDR2_1_8814B) +#define BIT_CLEAR_ANT_ADDR2_1_8814B(x) ((x) & (~BITS_ANT_ADDR2_1_8814B)) +#define BIT_GET_ANT_ADDR2_1_8814B(x) \ + (((x) >> BIT_SHIFT_ANT_ADDR2_1_8814B) & BIT_MASK_ANT_ADDR2_1_8814B) +#define BIT_SET_ANT_ADDR2_1_8814B(x, v) \ + (BIT_CLEAR_ANT_ADDR2_1_8814B(x) | BIT_ANT_ADDR2_1_8814B(v)) + +/* 2 REG_SMART_ANT_CTRL_8814B */ +#define BIT_ANTTRN_SWITCH_8814B BIT(19) #define BIT_APPEND_MACID_IN_RESP_EN_1_8814B BIT(18) #define BIT_ADDR2_MATCH_EN_1_8814B BIT(17) #define BIT_ANTTRN_EN_1_8814B BIT(16) -#define BIT_SHIFT_TRAIN_STA_ADDR_1_8814B 0 -#define BIT_MASK_TRAIN_STA_ADDR_1_8814B 0xffff -#define BIT_TRAIN_STA_ADDR_1_8814B(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8814B) << BIT_SHIFT_TRAIN_STA_ADDR_1_8814B) -#define BIT_GET_TRAIN_STA_ADDR_1_8814B(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8814B) & BIT_MASK_TRAIN_STA_ADDR_1_8814B) - - - -/* 2 REG_WMAC_PKTCNT_RWD_8814B */ - -#define BIT_SHIFT_PKTCNT_BSSIDMAP_8814B 4 -#define BIT_MASK_PKTCNT_BSSIDMAP_8814B 0xf -#define BIT_PKTCNT_BSSIDMAP_8814B(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8814B) << BIT_SHIFT_PKTCNT_BSSIDMAP_8814B) -#define BIT_GET_PKTCNT_BSSIDMAP_8814B(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8814B) & BIT_MASK_PKTCNT_BSSIDMAP_8814B) - - -#define BIT_PKTCNT_CNTRST_8814B BIT(1) -#define BIT_PKTCNT_CNTEN_8814B BIT(0) - -/* 2 REG_WMAC_PKTCNT_CTRL_8814B */ -#define BIT_WMAC_PKTCNT_TRST_8814B BIT(9) -#define BIT_WMAC_PKTCNT_FEN_8814B BIT(8) - -#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8814B 0 -#define BIT_MASK_WMAC_PKTCNT_CFGAD_8814B 0xff -#define BIT_WMAC_PKTCNT_CFGAD_8814B(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8814B) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8814B) -#define BIT_GET_WMAC_PKTCNT_CFGAD_8814B(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8814B) & BIT_MASK_WMAC_PKTCNT_CFGAD_8814B) - - +#define BIT_SHIFT_ANT_ADDR2_2_8814B 0 +#define BIT_MASK_ANT_ADDR2_2_8814B 0xffff +#define BIT_ANT_ADDR2_2_8814B(x) \ + (((x) & BIT_MASK_ANT_ADDR2_2_8814B) << BIT_SHIFT_ANT_ADDR2_2_8814B) +#define BITS_ANT_ADDR2_2_8814B \ + (BIT_MASK_ANT_ADDR2_2_8814B << BIT_SHIFT_ANT_ADDR2_2_8814B) +#define BIT_CLEAR_ANT_ADDR2_2_8814B(x) ((x) & (~BITS_ANT_ADDR2_2_8814B)) +#define BIT_GET_ANT_ADDR2_2_8814B(x) \ + (((x) >> BIT_SHIFT_ANT_ADDR2_2_8814B) & BIT_MASK_ANT_ADDR2_2_8814B) +#define BIT_SET_ANT_ADDR2_2_8814B(x, v) \ + (BIT_CLEAR_ANT_ADDR2_2_8814B(x) | BIT_ANT_ADDR2_2_8814B(v)) + +/* 2 REG_CONTROL_FRAME_REPORT_8814B */ + +#define BIT_SHIFT_CONTROL_FRAME_REPORT_8814B 0 +#define BIT_MASK_CONTROL_FRAME_REPORT_8814B 0xffffffffL +#define BIT_CONTROL_FRAME_REPORT_8814B(x) \ + (((x) & BIT_MASK_CONTROL_FRAME_REPORT_8814B) \ + << BIT_SHIFT_CONTROL_FRAME_REPORT_8814B) +#define BITS_CONTROL_FRAME_REPORT_8814B \ + (BIT_MASK_CONTROL_FRAME_REPORT_8814B \ + << BIT_SHIFT_CONTROL_FRAME_REPORT_8814B) +#define BIT_CLEAR_CONTROL_FRAME_REPORT_8814B(x) \ + ((x) & (~BITS_CONTROL_FRAME_REPORT_8814B)) +#define BIT_GET_CONTROL_FRAME_REPORT_8814B(x) \ + (((x) >> BIT_SHIFT_CONTROL_FRAME_REPORT_8814B) & \ + BIT_MASK_CONTROL_FRAME_REPORT_8814B) +#define BIT_SET_CONTROL_FRAME_REPORT_8814B(x, v) \ + (BIT_CLEAR_CONTROL_FRAME_REPORT_8814B(x) | \ + BIT_CONTROL_FRAME_REPORT_8814B(v)) + +/* 2 REG_CONTROL_FRAME_CNT_CTRL_8814B */ +#define BIT_ALLCNTRST_8814B BIT(9) +#define BIT__ALLCNTEN_8814B BIT(8) + +#define BIT_SHIFT_ADDR_8814B 4 +#define BIT_MASK_ADDR_8814B 0xf +#define BIT_ADDR_8814B(x) (((x) & BIT_MASK_ADDR_8814B) << BIT_SHIFT_ADDR_8814B) +#define BITS_ADDR_8814B (BIT_MASK_ADDR_8814B << BIT_SHIFT_ADDR_8814B) +#define BIT_CLEAR_ADDR_8814B(x) ((x) & (~BITS_ADDR_8814B)) +#define BIT_GET_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_ADDR_8814B) & BIT_MASK_ADDR_8814B) +#define BIT_SET_ADDR_8814B(x, v) (BIT_CLEAR_ADDR_8814B(x) | BIT_ADDR_8814B(v)) + +#define BIT_SHIFT_CTRL_SEL_8814B 0 +#define BIT_MASK_CTRL_SEL_8814B 0xf +#define BIT_CTRL_SEL_8814B(x) \ + (((x) & BIT_MASK_CTRL_SEL_8814B) << BIT_SHIFT_CTRL_SEL_8814B) +#define BITS_CTRL_SEL_8814B \ + (BIT_MASK_CTRL_SEL_8814B << BIT_SHIFT_CTRL_SEL_8814B) +#define BIT_CLEAR_CTRL_SEL_8814B(x) ((x) & (~BITS_CTRL_SEL_8814B)) +#define BIT_GET_CTRL_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_CTRL_SEL_8814B) & BIT_MASK_CTRL_SEL_8814B) +#define BIT_SET_CTRL_SEL_8814B(x, v) \ + (BIT_CLEAR_CTRL_SEL_8814B(x) | BIT_CTRL_SEL_8814B(v)) /* 2 REG_IQ_DUMP_8814B */ -#define BIT_SHIFT_DUMP_OK_ADDR_8814B 15 -#define BIT_MASK_DUMP_OK_ADDR_8814B 0x1ffff -#define BIT_DUMP_OK_ADDR_8814B(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8814B) << BIT_SHIFT_DUMP_OK_ADDR_8814B) -#define BIT_GET_DUMP_OK_ADDR_8814B(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8814B) & BIT_MASK_DUMP_OK_ADDR_8814B) - - +#define BIT_SHIFT_DUMP_OK_ADDR_8814B 16 +#define BIT_MASK_DUMP_OK_ADDR_8814B 0xffff +#define BIT_DUMP_OK_ADDR_8814B(x) \ + (((x) & BIT_MASK_DUMP_OK_ADDR_8814B) << BIT_SHIFT_DUMP_OK_ADDR_8814B) +#define BITS_DUMP_OK_ADDR_8814B \ + (BIT_MASK_DUMP_OK_ADDR_8814B << BIT_SHIFT_DUMP_OK_ADDR_8814B) +#define BIT_CLEAR_DUMP_OK_ADDR_8814B(x) ((x) & (~BITS_DUMP_OK_ADDR_8814B)) +#define BIT_GET_DUMP_OK_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8814B) & BIT_MASK_DUMP_OK_ADDR_8814B) +#define BIT_SET_DUMP_OK_ADDR_8814B(x, v) \ + (BIT_CLEAR_DUMP_OK_ADDR_8814B(x) | BIT_DUMP_OK_ADDR_8814B(v)) #define BIT_SHIFT_R_TRIG_TIME_SEL_8814B 8 #define BIT_MASK_R_TRIG_TIME_SEL_8814B 0x7f -#define BIT_R_TRIG_TIME_SEL_8814B(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8814B) << BIT_SHIFT_R_TRIG_TIME_SEL_8814B) -#define BIT_GET_R_TRIG_TIME_SEL_8814B(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8814B) & BIT_MASK_R_TRIG_TIME_SEL_8814B) - - +#define BIT_R_TRIG_TIME_SEL_8814B(x) \ + (((x) & BIT_MASK_R_TRIG_TIME_SEL_8814B) \ + << BIT_SHIFT_R_TRIG_TIME_SEL_8814B) +#define BITS_R_TRIG_TIME_SEL_8814B \ + (BIT_MASK_R_TRIG_TIME_SEL_8814B << BIT_SHIFT_R_TRIG_TIME_SEL_8814B) +#define BIT_CLEAR_R_TRIG_TIME_SEL_8814B(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8814B)) +#define BIT_GET_R_TRIG_TIME_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8814B) & \ + BIT_MASK_R_TRIG_TIME_SEL_8814B) +#define BIT_SET_R_TRIG_TIME_SEL_8814B(x, v) \ + (BIT_CLEAR_R_TRIG_TIME_SEL_8814B(x) | BIT_R_TRIG_TIME_SEL_8814B(v)) #define BIT_SHIFT_R_MAC_TRIG_SEL_8814B 6 #define BIT_MASK_R_MAC_TRIG_SEL_8814B 0x3 -#define BIT_R_MAC_TRIG_SEL_8814B(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8814B) << BIT_SHIFT_R_MAC_TRIG_SEL_8814B) -#define BIT_GET_R_MAC_TRIG_SEL_8814B(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8814B) & BIT_MASK_R_MAC_TRIG_SEL_8814B) - +#define BIT_R_MAC_TRIG_SEL_8814B(x) \ + (((x) & BIT_MASK_R_MAC_TRIG_SEL_8814B) \ + << BIT_SHIFT_R_MAC_TRIG_SEL_8814B) +#define BITS_R_MAC_TRIG_SEL_8814B \ + (BIT_MASK_R_MAC_TRIG_SEL_8814B << BIT_SHIFT_R_MAC_TRIG_SEL_8814B) +#define BIT_CLEAR_R_MAC_TRIG_SEL_8814B(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8814B)) +#define BIT_GET_R_MAC_TRIG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8814B) & \ + BIT_MASK_R_MAC_TRIG_SEL_8814B) +#define BIT_SET_R_MAC_TRIG_SEL_8814B(x, v) \ + (BIT_CLEAR_R_MAC_TRIG_SEL_8814B(x) | BIT_R_MAC_TRIG_SEL_8814B(v)) #define BIT_MAC_TRIG_REG_8814B BIT(5) #define BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B 3 #define BIT_MASK_R_LEVEL_PULSE_SEL_8814B 0x3 -#define BIT_R_LEVEL_PULSE_SEL_8814B(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8814B) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) -#define BIT_GET_R_LEVEL_PULSE_SEL_8814B(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) & BIT_MASK_R_LEVEL_PULSE_SEL_8814B) - +#define BIT_R_LEVEL_PULSE_SEL_8814B(x) \ + (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8814B) \ + << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) +#define BITS_R_LEVEL_PULSE_SEL_8814B \ + (BIT_MASK_R_LEVEL_PULSE_SEL_8814B << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8814B(x) \ + ((x) & (~BITS_R_LEVEL_PULSE_SEL_8814B)) +#define BIT_GET_R_LEVEL_PULSE_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) & \ + BIT_MASK_R_LEVEL_PULSE_SEL_8814B) +#define BIT_SET_R_LEVEL_PULSE_SEL_8814B(x, v) \ + (BIT_CLEAR_R_LEVEL_PULSE_SEL_8814B(x) | BIT_R_LEVEL_PULSE_SEL_8814B(v)) #define BIT_EN_LA_MAC_8814B BIT(2) #define BIT_R_EN_IQDUMP_8814B BIT(1) @@ -11094,19 +25294,39 @@ #define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B 0 #define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC_1_8814B(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) -#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B) - - +#define BIT_R_WMAC_MASK_LA_MAC_1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B) \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) +#define BITS_R_WMAC_MASK_LA_MAC_1_8814B \ + (BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8814B(x) \ + ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8814B)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) & \ + BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B) +#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8814B(x) | \ + BIT_R_WMAC_MASK_LA_MAC_1_8814B(v)) /* 2 REG_IQ_DUMP_2_8814B */ #define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B 0 #define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC_2_8814B(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) -#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B) - - +#define BIT_R_WMAC_MATCH_REF_MAC_2_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) +#define BITS_R_WMAC_MATCH_REF_MAC_2_8814B \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8814B(x) \ + ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8814B)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8814B(x) | \ + BIT_R_WMAC_MATCH_REF_MAC_2_8814B(v)) /* 2 REG_WMAC_FTM_CTL_8814B */ #define BIT_RXFTM_TXACK_SC_8814B BIT(6) @@ -11122,25 +25342,46 @@ #define BIT_SHIFT_R_OFDM_LEN_8814B 26 #define BIT_MASK_R_OFDM_LEN_8814B 0x3f -#define BIT_R_OFDM_LEN_8814B(x) (((x) & BIT_MASK_R_OFDM_LEN_8814B) << BIT_SHIFT_R_OFDM_LEN_8814B) -#define BIT_GET_R_OFDM_LEN_8814B(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8814B) & BIT_MASK_R_OFDM_LEN_8814B) - - +#define BIT_R_OFDM_LEN_8814B(x) \ + (((x) & BIT_MASK_R_OFDM_LEN_8814B) << BIT_SHIFT_R_OFDM_LEN_8814B) +#define BITS_R_OFDM_LEN_8814B \ + (BIT_MASK_R_OFDM_LEN_8814B << BIT_SHIFT_R_OFDM_LEN_8814B) +#define BIT_CLEAR_R_OFDM_LEN_8814B(x) ((x) & (~BITS_R_OFDM_LEN_8814B)) +#define BIT_GET_R_OFDM_LEN_8814B(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN_8814B) & BIT_MASK_R_OFDM_LEN_8814B) +#define BIT_SET_R_OFDM_LEN_8814B(x, v) \ + (BIT_CLEAR_R_OFDM_LEN_8814B(x) | BIT_R_OFDM_LEN_8814B(v)) #define BIT_SHIFT_R_CCK_LEN_8814B 0 #define BIT_MASK_R_CCK_LEN_8814B 0xffff -#define BIT_R_CCK_LEN_8814B(x) (((x) & BIT_MASK_R_CCK_LEN_8814B) << BIT_SHIFT_R_CCK_LEN_8814B) -#define BIT_GET_R_CCK_LEN_8814B(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8814B) & BIT_MASK_R_CCK_LEN_8814B) - - +#define BIT_R_CCK_LEN_8814B(x) \ + (((x) & BIT_MASK_R_CCK_LEN_8814B) << BIT_SHIFT_R_CCK_LEN_8814B) +#define BITS_R_CCK_LEN_8814B \ + (BIT_MASK_R_CCK_LEN_8814B << BIT_SHIFT_R_CCK_LEN_8814B) +#define BIT_CLEAR_R_CCK_LEN_8814B(x) ((x) & (~BITS_R_CCK_LEN_8814B)) +#define BIT_GET_R_CCK_LEN_8814B(x) \ + (((x) >> BIT_SHIFT_R_CCK_LEN_8814B) & BIT_MASK_R_CCK_LEN_8814B) +#define BIT_SET_R_CCK_LEN_8814B(x, v) \ + (BIT_CLEAR_R_CCK_LEN_8814B(x) | BIT_R_CCK_LEN_8814B(v)) /* 2 REG_WMAC_OPTION_FUNCTION_1_8814B */ #define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B 24 #define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B) - +#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) +#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8814B \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) \ + ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8814B)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) | \ + BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(v)) #define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8814B BIT(23) #define BIT_R_WMAC_RXRST_DLY_1_8814B BIT(22) @@ -11171,10 +25412,20 @@ #define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B 0 #define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B 0xffff -#define BIT_R_WMAC_RX_FIL_LEN_2_8814B(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) -#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B) - - +#define BIT_R_WMAC_RX_FIL_LEN_2_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B) \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) +#define BITS_R_WMAC_RX_FIL_LEN_2_8814B \ + (BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8814B(x) \ + ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8814B)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) & \ + BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B) +#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8814B(x) | \ + BIT_R_WMAC_RX_FIL_LEN_2_8814B(v)) /* 2 REG_RX_FILTER_FUNCTION_8814B */ #define BIT_R_WMAC_MHRDDY_LATCH_8814B BIT(14) @@ -11199,35 +25450,60 @@ #define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B 0 #define BIT_MASK_R_WMAC_TXNDP_SIGB_8814B 0x1fffff -#define BIT_R_WMAC_TXNDP_SIGB_8814B(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8814B) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) -#define BIT_GET_R_WMAC_TXNDP_SIGB_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) & BIT_MASK_R_WMAC_TXNDP_SIGB_8814B) - - +#define BIT_R_WMAC_TXNDP_SIGB_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8814B) \ + << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) +#define BITS_R_WMAC_TXNDP_SIGB_8814B \ + (BIT_MASK_R_WMAC_TXNDP_SIGB_8814B << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8814B(x) \ + ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8814B)) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) & \ + BIT_MASK_R_WMAC_TXNDP_SIGB_8814B) +#define BIT_SET_R_WMAC_TXNDP_SIGB_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8814B(x) | BIT_R_WMAC_TXNDP_SIGB_8814B(v)) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8814B */ #define BIT_SHIFT_R_MAC_DBG_SHIFT_8814B 8 #define BIT_MASK_R_MAC_DBG_SHIFT_8814B 0x7 -#define BIT_R_MAC_DBG_SHIFT_8814B(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8814B) << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) -#define BIT_GET_R_MAC_DBG_SHIFT_8814B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) & BIT_MASK_R_MAC_DBG_SHIFT_8814B) - - +#define BIT_R_MAC_DBG_SHIFT_8814B(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8814B) \ + << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) +#define BITS_R_MAC_DBG_SHIFT_8814B \ + (BIT_MASK_R_MAC_DBG_SHIFT_8814B << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) +#define BIT_CLEAR_R_MAC_DBG_SHIFT_8814B(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8814B)) +#define BIT_GET_R_MAC_DBG_SHIFT_8814B(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) & \ + BIT_MASK_R_MAC_DBG_SHIFT_8814B) +#define BIT_SET_R_MAC_DBG_SHIFT_8814B(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SHIFT_8814B(x) | BIT_R_MAC_DBG_SHIFT_8814B(v)) #define BIT_SHIFT_R_MAC_DBG_SEL_8814B 0 #define BIT_MASK_R_MAC_DBG_SEL_8814B 0x3 -#define BIT_R_MAC_DBG_SEL_8814B(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8814B) << BIT_SHIFT_R_MAC_DBG_SEL_8814B) -#define BIT_GET_R_MAC_DBG_SEL_8814B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8814B) & BIT_MASK_R_MAC_DBG_SEL_8814B) - - +#define BIT_R_MAC_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SEL_8814B) << BIT_SHIFT_R_MAC_DBG_SEL_8814B) +#define BITS_R_MAC_DBG_SEL_8814B \ + (BIT_MASK_R_MAC_DBG_SEL_8814B << BIT_SHIFT_R_MAC_DBG_SEL_8814B) +#define BIT_CLEAR_R_MAC_DBG_SEL_8814B(x) ((x) & (~BITS_R_MAC_DBG_SEL_8814B)) +#define BIT_GET_R_MAC_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8814B) & BIT_MASK_R_MAC_DBG_SEL_8814B) +#define BIT_SET_R_MAC_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SEL_8814B(x) | BIT_R_MAC_DBG_SEL_8814B(v)) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8814B */ #define BIT_SHIFT_R_MAC_DEBUG_1_8814B 0 #define BIT_MASK_R_MAC_DEBUG_1_8814B 0xffffffffL -#define BIT_R_MAC_DEBUG_1_8814B(x) (((x) & BIT_MASK_R_MAC_DEBUG_1_8814B) << BIT_SHIFT_R_MAC_DEBUG_1_8814B) -#define BIT_GET_R_MAC_DEBUG_1_8814B(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8814B) & BIT_MASK_R_MAC_DEBUG_1_8814B) - - +#define BIT_R_MAC_DEBUG_1_8814B(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG_1_8814B) << BIT_SHIFT_R_MAC_DEBUG_1_8814B) +#define BITS_R_MAC_DEBUG_1_8814B \ + (BIT_MASK_R_MAC_DEBUG_1_8814B << BIT_SHIFT_R_MAC_DEBUG_1_8814B) +#define BIT_CLEAR_R_MAC_DEBUG_1_8814B(x) ((x) & (~BITS_R_MAC_DEBUG_1_8814B)) +#define BIT_GET_R_MAC_DEBUG_1_8814B(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8814B) & BIT_MASK_R_MAC_DEBUG_1_8814B) +#define BIT_SET_R_MAC_DEBUG_1_8814B(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG_1_8814B(x) | BIT_R_MAC_DEBUG_1_8814B(v)) /* 2 REG_WSEC_OPTION_8814B */ #define BIT_RXDEC_BM_MGNT_8814B BIT(22) @@ -11250,35 +25526,69 @@ #define BIT_SHIFT_WRITE_BYTE_EN_V1_8814B 16 #define BIT_MASK_WRITE_BYTE_EN_V1_8814B 0xf -#define BIT_WRITE_BYTE_EN_V1_8814B(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8814B) << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) -#define BIT_GET_WRITE_BYTE_EN_V1_8814B(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) & BIT_MASK_WRITE_BYTE_EN_V1_8814B) - - +#define BIT_WRITE_BYTE_EN_V1_8814B(x) \ + (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8814B) \ + << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) +#define BITS_WRITE_BYTE_EN_V1_8814B \ + (BIT_MASK_WRITE_BYTE_EN_V1_8814B << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) +#define BIT_CLEAR_WRITE_BYTE_EN_V1_8814B(x) \ + ((x) & (~BITS_WRITE_BYTE_EN_V1_8814B)) +#define BIT_GET_WRITE_BYTE_EN_V1_8814B(x) \ + (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) & \ + BIT_MASK_WRITE_BYTE_EN_V1_8814B) +#define BIT_SET_WRITE_BYTE_EN_V1_8814B(x, v) \ + (BIT_CLEAR_WRITE_BYTE_EN_V1_8814B(x) | BIT_WRITE_BYTE_EN_V1_8814B(v)) #define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B 0 #define BIT_MASK_LTECOEX_REG_ADDR_V1_8814B 0xffff -#define BIT_LTECOEX_REG_ADDR_V1_8814B(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8814B) << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) -#define BIT_GET_LTECOEX_REG_ADDR_V1_8814B(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) & BIT_MASK_LTECOEX_REG_ADDR_V1_8814B) - - +#define BIT_LTECOEX_REG_ADDR_V1_8814B(x) \ + (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8814B) \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) +#define BITS_LTECOEX_REG_ADDR_V1_8814B \ + (BIT_MASK_LTECOEX_REG_ADDR_V1_8814B \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) +#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8814B(x) \ + ((x) & (~BITS_LTECOEX_REG_ADDR_V1_8814B)) +#define BIT_GET_LTECOEX_REG_ADDR_V1_8814B(x) \ + (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) & \ + BIT_MASK_LTECOEX_REG_ADDR_V1_8814B) +#define BIT_SET_LTECOEX_REG_ADDR_V1_8814B(x, v) \ + (BIT_CLEAR_LTECOEX_REG_ADDR_V1_8814B(x) | \ + BIT_LTECOEX_REG_ADDR_V1_8814B(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B */ #define BIT_SHIFT_LTECOEX_W_DATA_V1_8814B 0 #define BIT_MASK_LTECOEX_W_DATA_V1_8814B 0xffffffffL -#define BIT_LTECOEX_W_DATA_V1_8814B(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8814B) << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) -#define BIT_GET_LTECOEX_W_DATA_V1_8814B(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) & BIT_MASK_LTECOEX_W_DATA_V1_8814B) - - +#define BIT_LTECOEX_W_DATA_V1_8814B(x) \ + (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8814B) \ + << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) +#define BITS_LTECOEX_W_DATA_V1_8814B \ + (BIT_MASK_LTECOEX_W_DATA_V1_8814B << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) +#define BIT_CLEAR_LTECOEX_W_DATA_V1_8814B(x) \ + ((x) & (~BITS_LTECOEX_W_DATA_V1_8814B)) +#define BIT_GET_LTECOEX_W_DATA_V1_8814B(x) \ + (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) & \ + BIT_MASK_LTECOEX_W_DATA_V1_8814B) +#define BIT_SET_LTECOEX_W_DATA_V1_8814B(x, v) \ + (BIT_CLEAR_LTECOEX_W_DATA_V1_8814B(x) | BIT_LTECOEX_W_DATA_V1_8814B(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B */ #define BIT_SHIFT_LTECOEX_R_DATA_V1_8814B 0 #define BIT_MASK_LTECOEX_R_DATA_V1_8814B 0xffffffffL -#define BIT_LTECOEX_R_DATA_V1_8814B(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8814B) << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) -#define BIT_GET_LTECOEX_R_DATA_V1_8814B(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) & BIT_MASK_LTECOEX_R_DATA_V1_8814B) - - +#define BIT_LTECOEX_R_DATA_V1_8814B(x) \ + (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8814B) \ + << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) +#define BITS_LTECOEX_R_DATA_V1_8814B \ + (BIT_MASK_LTECOEX_R_DATA_V1_8814B << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) +#define BIT_CLEAR_LTECOEX_R_DATA_V1_8814B(x) \ + ((x) & (~BITS_LTECOEX_R_DATA_V1_8814B)) +#define BIT_GET_LTECOEX_R_DATA_V1_8814B(x) \ + (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) & \ + BIT_MASK_LTECOEX_R_DATA_V1_8814B) +#define BIT_SET_LTECOEX_R_DATA_V1_8814B(x, v) \ + (BIT_CLEAR_LTECOEX_R_DATA_V1_8814B(x) | BIT_LTECOEX_R_DATA_V1_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -11402,20 +25712,311 @@ /* 2 REG_NOT_VALID_8814B */ +/* 2 REG_PCIE_CFG_FORCE_LINK_L_8814B */ +#define BIT_PCIE_CFG_FORCE_EN_8814B BIT(7) + +/* 2 REG_PCIE_CFG_FORCE_LINK_H_8814B */ +#define BIT_PCIE_CFG_TRXACT_DIS_IDLE_TIMER_8814B BIT(6) + +#define BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B 0 +#define BIT_MASK_PCIE_CFG_LINK_STATE_8814B 0x3f +#define BIT_PCIE_CFG_LINK_STATE_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_LINK_STATE_8814B) \ + << BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B) +#define BITS_PCIE_CFG_LINK_STATE_8814B \ + (BIT_MASK_PCIE_CFG_LINK_STATE_8814B \ + << BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B) +#define BIT_CLEAR_PCIE_CFG_LINK_STATE_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_LINK_STATE_8814B)) +#define BIT_GET_PCIE_CFG_LINK_STATE_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B) & \ + BIT_MASK_PCIE_CFG_LINK_STATE_8814B) +#define BIT_SET_PCIE_CFG_LINK_STATE_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_LINK_STATE_8814B(x) | \ + BIT_PCIE_CFG_LINK_STATE_8814B(v)) + +/* 2 REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B */ + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0 +#define BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0xff +#define BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) +#define BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B \ + (BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)) +#define BIT_GET_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) & \ + BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) +#define BIT_SET_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) | \ + BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(v)) + +/* 2 REG_PCIE_CFG_CX_NFTS_8814B */ + +#define BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B 0 +#define BIT_MASK_PCIE_CFG_CX_NFTS_8814B 0xff +#define BIT_PCIE_CFG_CX_NFTS_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_CX_NFTS_8814B) \ + << BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B) +#define BITS_PCIE_CFG_CX_NFTS_8814B \ + (BIT_MASK_PCIE_CFG_CX_NFTS_8814B << BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B) +#define BIT_CLEAR_PCIE_CFG_CX_NFTS_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_CX_NFTS_8814B)) +#define BIT_GET_PCIE_CFG_CX_NFTS_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B) & \ + BIT_MASK_PCIE_CFG_CX_NFTS_8814B) +#define BIT_SET_PCIE_CFG_CX_NFTS_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_CX_NFTS_8814B(x) | BIT_PCIE_CFG_CX_NFTS_8814B(v)) + +/* 2 REG_PCIE_CFG_DEFAULT_ENTR_LATENCY_8814B */ +#define BIT_PCIE_CFG_REAL_EN_L0S_8814B BIT(7) +#define BIT_PCIE_CFG_ENTER_ASPM_8814B BIT(6) + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B 3 +#define BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B 0x7 +#define BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) +#define BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B \ + (BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)) +#define BIT_GET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) & \ + BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) +#define BIT_SET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) | \ + BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(v)) + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B 0 +#define BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B 0x7 +#define BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) +#define BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B \ + (BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)) +#define BIT_GET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) & \ + BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) +#define BIT_SET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) | \ + BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(v)) + +/* 2 REG_PCIE_CFG_L1_MISC_SEL_8814B */ +#define BIT_PCIE_CFG_L1_RIDLE_SEL_8814B BIT(6) +#define BIT_PCIE_CFG_L1_TIMEOUT_SEL_8814B BIT(5) +#define BIT_PCIE_CFG_L1_EIDLE_SEL_8814B BIT(4) + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B 0 +#define BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B 0xf +#define BIT_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B) +#define BITS_PCIE_CFG_DEFAULT_LINK_RATE_8814B \ + (BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_LINK_RATE_8814B)) +#define BIT_GET_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B) & \ + BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B) +#define BIT_SET_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) | \ + BIT_PCIE_CFG_DEFAULT_LINK_RATE_8814B(v)) + +/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF_8814B */ +#define BIT_PCIE_CFG_REAL_PTM_ENABLE_8814B BIT(6) +#define BIT_PCIE_CFG_REAL_EN_L1SUB_8814B BIT(5) + +#define BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B 0 +#define BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B 0x7 +#define BIT_PCIE_CFG_MAX_FUNC_NUM_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B) \ + << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B) +#define BITS_PCIE_CFG_MAX_FUNC_NUM_8814B \ + (BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B \ + << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B) +#define BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_MAX_FUNC_NUM_8814B)) +#define BIT_GET_PCIE_CFG_MAX_FUNC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B) & \ + BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B) +#define BIT_SET_PCIE_CFG_MAX_FUNC_NUM_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM_8814B(x) | \ + BIT_PCIE_CFG_MAX_FUNC_NUM_8814B(v)) + +/* 2 REG_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B */ +#define BIT_PCIE_CFG_REAL_EN_64BITS_8814B BIT(5) +#define BIT_PCIE_CFG_REAL_EN_CLKREQ_8814B BIT(4) +#define BIT_PCIE_CFG_REAL_EN_L1_8814B BIT(3) +#define BIT_PCIE_CFG_WAKE_N_EN_8814B BIT(2) +#define BIT_PCIE_CFG_BYPASS_LTR_OPTION_8814B BIT(1) +#define BIT_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B BIT(0) + +/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY_8814B */ + +#define BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B 0 +#define BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B 0xff +#define BIT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) \ + << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) +#define BITS_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B \ + (BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B \ + << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) +#define BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)) +#define BIT_GET_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) & \ + BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) +#define BIT_SET_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) | \ + BIT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(v)) + +/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG_8814B */ +#define BIT_PCIE_CFG_BYPASS_L1_SUBSTATE_OPTION_8814B BIT(7) + +#define BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B 5 +#define BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B 0x3 +#define BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) \ + << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) +#define BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B \ + (BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B \ + << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) +#define BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)) +#define BIT_GET_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) & \ + BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) +#define BIT_SET_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) | \ + BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(v)) + +#define BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B 0 +#define BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B 0x1f +#define BIT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) \ + << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) +#define BITS_PCIE_CFG_UPDATE_FREQ_TIMER_8814B \ + (BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B \ + << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) +#define BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)) +#define BIT_GET_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) & \ + BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) +#define BIT_SET_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) | \ + BIT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(v)) + +/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B */ + +#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0 +#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0xff +#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) +#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B \ + (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) +#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)) +#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) & \ + BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) +#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) | \ + BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(v)) + +/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B */ +#define BIT_PCIE_CFG_DISABLE_FC_WATCHDOG_TIMER_8814B BIT(7) + +#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0 +#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0x7 +#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) +#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B \ + (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) +#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)) +#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) & \ + BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) +#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) | \ + BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(v)) + +/* 2 REG_PCIE_CFG_L1_UNIT_SEL_8814B */ + +#define BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B 0 +#define BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B 0xff +#define BIT_PCIE_CFG_L1_UNIT_SEL_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B) \ + << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B) +#define BITS_PCIE_CFG_L1_UNIT_SEL_8814B \ + (BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B \ + << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B) +#define BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_L1_UNIT_SEL_8814B)) +#define BIT_GET_PCIE_CFG_L1_UNIT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B) & \ + BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B) +#define BIT_SET_PCIE_CFG_L1_UNIT_SEL_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL_8814B(x) | \ + BIT_PCIE_CFG_L1_UNIT_SEL_8814B(v)) + +/* 2 REG_PCIE_CFG_MIN_CLKREQ_SEL_8814B */ + +#define BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0 +#define BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0xf +#define BIT_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B) \ + << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B) +#define BITS_PCIE_CFG_MIN_CLKREQ_SEL_8814B \ + (BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B \ + << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B) +#define BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_MIN_CLKREQ_SEL_8814B)) +#define BIT_GET_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B) & \ + BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B) +#define BIT_SET_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) | \ + BIT_PCIE_CFG_MIN_CLKREQ_SEL_8814B(v)) + /* 2 REG_SDIO_TX_CTRL_8814B */ #define BIT_SHIFT_SDIO_INT_TIMEOUT_8814B 16 #define BIT_MASK_SDIO_INT_TIMEOUT_8814B 0xffff -#define BIT_SDIO_INT_TIMEOUT_8814B(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8814B) << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) -#define BIT_GET_SDIO_INT_TIMEOUT_8814B(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) & BIT_MASK_SDIO_INT_TIMEOUT_8814B) - +#define BIT_SDIO_INT_TIMEOUT_8814B(x) \ + (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8814B) \ + << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) +#define BITS_SDIO_INT_TIMEOUT_8814B \ + (BIT_MASK_SDIO_INT_TIMEOUT_8814B << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) +#define BIT_CLEAR_SDIO_INT_TIMEOUT_8814B(x) \ + ((x) & (~BITS_SDIO_INT_TIMEOUT_8814B)) +#define BIT_GET_SDIO_INT_TIMEOUT_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) & \ + BIT_MASK_SDIO_INT_TIMEOUT_8814B) +#define BIT_SET_SDIO_INT_TIMEOUT_8814B(x, v) \ + (BIT_CLEAR_SDIO_INT_TIMEOUT_8814B(x) | BIT_SDIO_INT_TIMEOUT_8814B(v)) #define BIT_IO_ERR_STATUS_8814B BIT(15) #define BIT_REPLY_ERRCRC_IN_DATA_8814B BIT(9) #define BIT_EN_CMD53_OVERLAP_8814B BIT(8) #define BIT_REPLY_ERR_IN_R5_8814B BIT(7) #define BIT_R18A_EN_8814B BIT(6) -#define BIT_INIT_CMD_EN_8814B BIT(5) +#define BIT_SDIO_CMD_FORCE_VLD_8814B BIT(5) +#define BIT_INIT_CMD_EN_8814B BIT(4) #define BIT_EN_RXDMA_MASK_INT_8814B BIT(2) #define BIT_EN_MASK_TIMER_8814B BIT(1) #define BIT_CMD_ERR_STOP_INT_EN_8814B BIT(0) @@ -11476,95 +26077,155 @@ #define BIT_SHIFT_RX_REQ_LEN_V1_8814B 0 #define BIT_MASK_RX_REQ_LEN_V1_8814B 0x3ffff -#define BIT_RX_REQ_LEN_V1_8814B(x) (((x) & BIT_MASK_RX_REQ_LEN_V1_8814B) << BIT_SHIFT_RX_REQ_LEN_V1_8814B) -#define BIT_GET_RX_REQ_LEN_V1_8814B(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8814B) & BIT_MASK_RX_REQ_LEN_V1_8814B) - - +#define BIT_RX_REQ_LEN_V1_8814B(x) \ + (((x) & BIT_MASK_RX_REQ_LEN_V1_8814B) << BIT_SHIFT_RX_REQ_LEN_V1_8814B) +#define BITS_RX_REQ_LEN_V1_8814B \ + (BIT_MASK_RX_REQ_LEN_V1_8814B << BIT_SHIFT_RX_REQ_LEN_V1_8814B) +#define BIT_CLEAR_RX_REQ_LEN_V1_8814B(x) ((x) & (~BITS_RX_REQ_LEN_V1_8814B)) +#define BIT_GET_RX_REQ_LEN_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8814B) & BIT_MASK_RX_REQ_LEN_V1_8814B) +#define BIT_SET_RX_REQ_LEN_V1_8814B(x, v) \ + (BIT_CLEAR_RX_REQ_LEN_V1_8814B(x) | BIT_RX_REQ_LEN_V1_8814B(v)) /* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8814B */ #define BIT_SHIFT_FREE_TXPG_SEQ_8814B 0 #define BIT_MASK_FREE_TXPG_SEQ_8814B 0xff -#define BIT_FREE_TXPG_SEQ_8814B(x) (((x) & BIT_MASK_FREE_TXPG_SEQ_8814B) << BIT_SHIFT_FREE_TXPG_SEQ_8814B) -#define BIT_GET_FREE_TXPG_SEQ_8814B(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8814B) & BIT_MASK_FREE_TXPG_SEQ_8814B) - - +#define BIT_FREE_TXPG_SEQ_8814B(x) \ + (((x) & BIT_MASK_FREE_TXPG_SEQ_8814B) << BIT_SHIFT_FREE_TXPG_SEQ_8814B) +#define BITS_FREE_TXPG_SEQ_8814B \ + (BIT_MASK_FREE_TXPG_SEQ_8814B << BIT_SHIFT_FREE_TXPG_SEQ_8814B) +#define BIT_CLEAR_FREE_TXPG_SEQ_8814B(x) ((x) & (~BITS_FREE_TXPG_SEQ_8814B)) +#define BIT_GET_FREE_TXPG_SEQ_8814B(x) \ + (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8814B) & BIT_MASK_FREE_TXPG_SEQ_8814B) +#define BIT_SET_FREE_TXPG_SEQ_8814B(x, v) \ + (BIT_CLEAR_FREE_TXPG_SEQ_8814B(x) | BIT_FREE_TXPG_SEQ_8814B(v)) /* 2 REG_SDIO_FREE_TXPG_8814B */ #define BIT_SHIFT_MID_FREEPG_V1_8814B 16 #define BIT_MASK_MID_FREEPG_V1_8814B 0xfff -#define BIT_MID_FREEPG_V1_8814B(x) (((x) & BIT_MASK_MID_FREEPG_V1_8814B) << BIT_SHIFT_MID_FREEPG_V1_8814B) -#define BIT_GET_MID_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1_8814B) & BIT_MASK_MID_FREEPG_V1_8814B) - - +#define BIT_MID_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_MID_FREEPG_V1_8814B) << BIT_SHIFT_MID_FREEPG_V1_8814B) +#define BITS_MID_FREEPG_V1_8814B \ + (BIT_MASK_MID_FREEPG_V1_8814B << BIT_SHIFT_MID_FREEPG_V1_8814B) +#define BIT_CLEAR_MID_FREEPG_V1_8814B(x) ((x) & (~BITS_MID_FREEPG_V1_8814B)) +#define BIT_GET_MID_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MID_FREEPG_V1_8814B) & BIT_MASK_MID_FREEPG_V1_8814B) +#define BIT_SET_MID_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_MID_FREEPG_V1_8814B(x) | BIT_MID_FREEPG_V1_8814B(v)) #define BIT_SHIFT_HIQ_FREEPG_V1_8814B 0 #define BIT_MASK_HIQ_FREEPG_V1_8814B 0xfff -#define BIT_HIQ_FREEPG_V1_8814B(x) (((x) & BIT_MASK_HIQ_FREEPG_V1_8814B) << BIT_SHIFT_HIQ_FREEPG_V1_8814B) -#define BIT_GET_HIQ_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8814B) & BIT_MASK_HIQ_FREEPG_V1_8814B) - - +#define BIT_HIQ_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_HIQ_FREEPG_V1_8814B) << BIT_SHIFT_HIQ_FREEPG_V1_8814B) +#define BITS_HIQ_FREEPG_V1_8814B \ + (BIT_MASK_HIQ_FREEPG_V1_8814B << BIT_SHIFT_HIQ_FREEPG_V1_8814B) +#define BIT_CLEAR_HIQ_FREEPG_V1_8814B(x) ((x) & (~BITS_HIQ_FREEPG_V1_8814B)) +#define BIT_GET_HIQ_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8814B) & BIT_MASK_HIQ_FREEPG_V1_8814B) +#define BIT_SET_HIQ_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_HIQ_FREEPG_V1_8814B(x) | BIT_HIQ_FREEPG_V1_8814B(v)) /* 2 REG_SDIO_FREE_TXPG2_8814B */ #define BIT_SHIFT_PUB_FREEPG_V1_8814B 16 #define BIT_MASK_PUB_FREEPG_V1_8814B 0xfff -#define BIT_PUB_FREEPG_V1_8814B(x) (((x) & BIT_MASK_PUB_FREEPG_V1_8814B) << BIT_SHIFT_PUB_FREEPG_V1_8814B) -#define BIT_GET_PUB_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8814B) & BIT_MASK_PUB_FREEPG_V1_8814B) - - +#define BIT_PUB_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_PUB_FREEPG_V1_8814B) << BIT_SHIFT_PUB_FREEPG_V1_8814B) +#define BITS_PUB_FREEPG_V1_8814B \ + (BIT_MASK_PUB_FREEPG_V1_8814B << BIT_SHIFT_PUB_FREEPG_V1_8814B) +#define BIT_CLEAR_PUB_FREEPG_V1_8814B(x) ((x) & (~BITS_PUB_FREEPG_V1_8814B)) +#define BIT_GET_PUB_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8814B) & BIT_MASK_PUB_FREEPG_V1_8814B) +#define BIT_SET_PUB_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_PUB_FREEPG_V1_8814B(x) | BIT_PUB_FREEPG_V1_8814B(v)) #define BIT_SHIFT_LOW_FREEPG_V1_8814B 0 #define BIT_MASK_LOW_FREEPG_V1_8814B 0xfff -#define BIT_LOW_FREEPG_V1_8814B(x) (((x) & BIT_MASK_LOW_FREEPG_V1_8814B) << BIT_SHIFT_LOW_FREEPG_V1_8814B) -#define BIT_GET_LOW_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8814B) & BIT_MASK_LOW_FREEPG_V1_8814B) - - +#define BIT_LOW_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_LOW_FREEPG_V1_8814B) << BIT_SHIFT_LOW_FREEPG_V1_8814B) +#define BITS_LOW_FREEPG_V1_8814B \ + (BIT_MASK_LOW_FREEPG_V1_8814B << BIT_SHIFT_LOW_FREEPG_V1_8814B) +#define BIT_CLEAR_LOW_FREEPG_V1_8814B(x) ((x) & (~BITS_LOW_FREEPG_V1_8814B)) +#define BIT_GET_LOW_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8814B) & BIT_MASK_LOW_FREEPG_V1_8814B) +#define BIT_SET_LOW_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_LOW_FREEPG_V1_8814B(x) | BIT_LOW_FREEPG_V1_8814B(v)) /* 2 REG_SDIO_OQT_FREE_TXPG_V1_8814B */ #define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B 24 #define BIT_MASK_NOAC_OQT_FREEPG_V1_8814B 0xff -#define BIT_NOAC_OQT_FREEPG_V1_8814B(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8814B) << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) -#define BIT_GET_NOAC_OQT_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) & BIT_MASK_NOAC_OQT_FREEPG_V1_8814B) - - +#define BIT_NOAC_OQT_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8814B) \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) +#define BITS_NOAC_OQT_FREEPG_V1_8814B \ + (BIT_MASK_NOAC_OQT_FREEPG_V1_8814B \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) +#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8814B(x) \ + ((x) & (~BITS_NOAC_OQT_FREEPG_V1_8814B)) +#define BIT_GET_NOAC_OQT_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) & \ + BIT_MASK_NOAC_OQT_FREEPG_V1_8814B) +#define BIT_SET_NOAC_OQT_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_NOAC_OQT_FREEPG_V1_8814B(x) | \ + BIT_NOAC_OQT_FREEPG_V1_8814B(v)) #define BIT_SHIFT_AC_OQT_FREEPG_V1_8814B 16 #define BIT_MASK_AC_OQT_FREEPG_V1_8814B 0xff -#define BIT_AC_OQT_FREEPG_V1_8814B(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8814B) << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) -#define BIT_GET_AC_OQT_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) & BIT_MASK_AC_OQT_FREEPG_V1_8814B) - - +#define BIT_AC_OQT_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8814B) \ + << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) +#define BITS_AC_OQT_FREEPG_V1_8814B \ + (BIT_MASK_AC_OQT_FREEPG_V1_8814B << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) +#define BIT_CLEAR_AC_OQT_FREEPG_V1_8814B(x) \ + ((x) & (~BITS_AC_OQT_FREEPG_V1_8814B)) +#define BIT_GET_AC_OQT_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) & \ + BIT_MASK_AC_OQT_FREEPG_V1_8814B) +#define BIT_SET_AC_OQT_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_AC_OQT_FREEPG_V1_8814B(x) | BIT_AC_OQT_FREEPG_V1_8814B(v)) #define BIT_SHIFT_EXQ_FREEPG_V1_8814B 0 #define BIT_MASK_EXQ_FREEPG_V1_8814B 0xfff -#define BIT_EXQ_FREEPG_V1_8814B(x) (((x) & BIT_MASK_EXQ_FREEPG_V1_8814B) << BIT_SHIFT_EXQ_FREEPG_V1_8814B) -#define BIT_GET_EXQ_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8814B) & BIT_MASK_EXQ_FREEPG_V1_8814B) - - +#define BIT_EXQ_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_EXQ_FREEPG_V1_8814B) << BIT_SHIFT_EXQ_FREEPG_V1_8814B) +#define BITS_EXQ_FREEPG_V1_8814B \ + (BIT_MASK_EXQ_FREEPG_V1_8814B << BIT_SHIFT_EXQ_FREEPG_V1_8814B) +#define BIT_CLEAR_EXQ_FREEPG_V1_8814B(x) ((x) & (~BITS_EXQ_FREEPG_V1_8814B)) +#define BIT_GET_EXQ_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8814B) & BIT_MASK_EXQ_FREEPG_V1_8814B) +#define BIT_SET_EXQ_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_EXQ_FREEPG_V1_8814B(x) | BIT_EXQ_FREEPG_V1_8814B(v)) /* 2 REG_SDIO_HTSFR_INFO_8814B */ #define BIT_SHIFT_HTSFR1_8814B 16 #define BIT_MASK_HTSFR1_8814B 0xffff -#define BIT_HTSFR1_8814B(x) (((x) & BIT_MASK_HTSFR1_8814B) << BIT_SHIFT_HTSFR1_8814B) -#define BIT_GET_HTSFR1_8814B(x) (((x) >> BIT_SHIFT_HTSFR1_8814B) & BIT_MASK_HTSFR1_8814B) - - +#define BIT_HTSFR1_8814B(x) \ + (((x) & BIT_MASK_HTSFR1_8814B) << BIT_SHIFT_HTSFR1_8814B) +#define BITS_HTSFR1_8814B (BIT_MASK_HTSFR1_8814B << BIT_SHIFT_HTSFR1_8814B) +#define BIT_CLEAR_HTSFR1_8814B(x) ((x) & (~BITS_HTSFR1_8814B)) +#define BIT_GET_HTSFR1_8814B(x) \ + (((x) >> BIT_SHIFT_HTSFR1_8814B) & BIT_MASK_HTSFR1_8814B) +#define BIT_SET_HTSFR1_8814B(x, v) \ + (BIT_CLEAR_HTSFR1_8814B(x) | BIT_HTSFR1_8814B(v)) #define BIT_SHIFT_HTSFR0_8814B 0 #define BIT_MASK_HTSFR0_8814B 0xffff -#define BIT_HTSFR0_8814B(x) (((x) & BIT_MASK_HTSFR0_8814B) << BIT_SHIFT_HTSFR0_8814B) -#define BIT_GET_HTSFR0_8814B(x) (((x) >> BIT_SHIFT_HTSFR0_8814B) & BIT_MASK_HTSFR0_8814B) - - +#define BIT_HTSFR0_8814B(x) \ + (((x) & BIT_MASK_HTSFR0_8814B) << BIT_SHIFT_HTSFR0_8814B) +#define BITS_HTSFR0_8814B (BIT_MASK_HTSFR0_8814B << BIT_SHIFT_HTSFR0_8814B) +#define BIT_CLEAR_HTSFR0_8814B(x) ((x) & (~BITS_HTSFR0_8814B)) +#define BIT_GET_HTSFR0_8814B(x) \ + (((x) >> BIT_SHIFT_HTSFR0_8814B) & BIT_MASK_HTSFR0_8814B) +#define BIT_SET_HTSFR0_8814B(x, v) \ + (BIT_CLEAR_HTSFR0_8814B(x) | BIT_HTSFR0_8814B(v)) /* 2 REG_SDIO_HCPWM1_V2_8814B */ -#define BIT_TOGGLING_8814B BIT(7) -#define BIT_ACK_8814B BIT(6) -#define BIT_SYS_CLK_8814B BIT(0) +#define BIT_TOGGLE_8814B BIT(7) +#define BIT_CUR_PS_8814B BIT(0) /* 2 REG_SDIO_HCPWM2_V2_8814B */ @@ -11575,49 +26236,83 @@ #define BIT_SHIFT_INDIRECT_REG_SIZE_8814B 16 #define BIT_MASK_INDIRECT_REG_SIZE_8814B 0x3 -#define BIT_INDIRECT_REG_SIZE_8814B(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE_8814B) << BIT_SHIFT_INDIRECT_REG_SIZE_8814B) -#define BIT_GET_INDIRECT_REG_SIZE_8814B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8814B) & BIT_MASK_INDIRECT_REG_SIZE_8814B) - - +#define BIT_INDIRECT_REG_SIZE_8814B(x) \ + (((x) & BIT_MASK_INDIRECT_REG_SIZE_8814B) \ + << BIT_SHIFT_INDIRECT_REG_SIZE_8814B) +#define BITS_INDIRECT_REG_SIZE_8814B \ + (BIT_MASK_INDIRECT_REG_SIZE_8814B << BIT_SHIFT_INDIRECT_REG_SIZE_8814B) +#define BIT_CLEAR_INDIRECT_REG_SIZE_8814B(x) \ + ((x) & (~BITS_INDIRECT_REG_SIZE_8814B)) +#define BIT_GET_INDIRECT_REG_SIZE_8814B(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8814B) & \ + BIT_MASK_INDIRECT_REG_SIZE_8814B) +#define BIT_SET_INDIRECT_REG_SIZE_8814B(x, v) \ + (BIT_CLEAR_INDIRECT_REG_SIZE_8814B(x) | BIT_INDIRECT_REG_SIZE_8814B(v)) #define BIT_SHIFT_INDIRECT_REG_ADDR_8814B 0 #define BIT_MASK_INDIRECT_REG_ADDR_8814B 0xffff -#define BIT_INDIRECT_REG_ADDR_8814B(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR_8814B) << BIT_SHIFT_INDIRECT_REG_ADDR_8814B) -#define BIT_GET_INDIRECT_REG_ADDR_8814B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8814B) & BIT_MASK_INDIRECT_REG_ADDR_8814B) - - +#define BIT_INDIRECT_REG_ADDR_8814B(x) \ + (((x) & BIT_MASK_INDIRECT_REG_ADDR_8814B) \ + << BIT_SHIFT_INDIRECT_REG_ADDR_8814B) +#define BITS_INDIRECT_REG_ADDR_8814B \ + (BIT_MASK_INDIRECT_REG_ADDR_8814B << BIT_SHIFT_INDIRECT_REG_ADDR_8814B) +#define BIT_CLEAR_INDIRECT_REG_ADDR_8814B(x) \ + ((x) & (~BITS_INDIRECT_REG_ADDR_8814B)) +#define BIT_GET_INDIRECT_REG_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8814B) & \ + BIT_MASK_INDIRECT_REG_ADDR_8814B) +#define BIT_SET_INDIRECT_REG_ADDR_8814B(x, v) \ + (BIT_CLEAR_INDIRECT_REG_ADDR_8814B(x) | BIT_INDIRECT_REG_ADDR_8814B(v)) /* 2 REG_SDIO_INDIRECT_REG_DATA_8814B */ #define BIT_SHIFT_INDIRECT_REG_DATA_8814B 0 #define BIT_MASK_INDIRECT_REG_DATA_8814B 0xffffffffL -#define BIT_INDIRECT_REG_DATA_8814B(x) (((x) & BIT_MASK_INDIRECT_REG_DATA_8814B) << BIT_SHIFT_INDIRECT_REG_DATA_8814B) -#define BIT_GET_INDIRECT_REG_DATA_8814B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8814B) & BIT_MASK_INDIRECT_REG_DATA_8814B) - - +#define BIT_INDIRECT_REG_DATA_8814B(x) \ + (((x) & BIT_MASK_INDIRECT_REG_DATA_8814B) \ + << BIT_SHIFT_INDIRECT_REG_DATA_8814B) +#define BITS_INDIRECT_REG_DATA_8814B \ + (BIT_MASK_INDIRECT_REG_DATA_8814B << BIT_SHIFT_INDIRECT_REG_DATA_8814B) +#define BIT_CLEAR_INDIRECT_REG_DATA_8814B(x) \ + ((x) & (~BITS_INDIRECT_REG_DATA_8814B)) +#define BIT_GET_INDIRECT_REG_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8814B) & \ + BIT_MASK_INDIRECT_REG_DATA_8814B) +#define BIT_SET_INDIRECT_REG_DATA_8814B(x, v) \ + (BIT_CLEAR_INDIRECT_REG_DATA_8814B(x) | BIT_INDIRECT_REG_DATA_8814B(v)) /* 2 REG_SDIO_H2C_8814B */ #define BIT_SHIFT_SDIO_H2C_MSG_8814B 0 #define BIT_MASK_SDIO_H2C_MSG_8814B 0xffffffffL -#define BIT_SDIO_H2C_MSG_8814B(x) (((x) & BIT_MASK_SDIO_H2C_MSG_8814B) << BIT_SHIFT_SDIO_H2C_MSG_8814B) -#define BIT_GET_SDIO_H2C_MSG_8814B(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8814B) & BIT_MASK_SDIO_H2C_MSG_8814B) - - +#define BIT_SDIO_H2C_MSG_8814B(x) \ + (((x) & BIT_MASK_SDIO_H2C_MSG_8814B) << BIT_SHIFT_SDIO_H2C_MSG_8814B) +#define BITS_SDIO_H2C_MSG_8814B \ + (BIT_MASK_SDIO_H2C_MSG_8814B << BIT_SHIFT_SDIO_H2C_MSG_8814B) +#define BIT_CLEAR_SDIO_H2C_MSG_8814B(x) ((x) & (~BITS_SDIO_H2C_MSG_8814B)) +#define BIT_GET_SDIO_H2C_MSG_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8814B) & BIT_MASK_SDIO_H2C_MSG_8814B) +#define BIT_SET_SDIO_H2C_MSG_8814B(x, v) \ + (BIT_CLEAR_SDIO_H2C_MSG_8814B(x) | BIT_SDIO_H2C_MSG_8814B(v)) /* 2 REG_SDIO_C2H_8814B */ #define BIT_SHIFT_SDIO_C2H_MSG_8814B 0 #define BIT_MASK_SDIO_C2H_MSG_8814B 0xffffffffL -#define BIT_SDIO_C2H_MSG_8814B(x) (((x) & BIT_MASK_SDIO_C2H_MSG_8814B) << BIT_SHIFT_SDIO_C2H_MSG_8814B) -#define BIT_GET_SDIO_C2H_MSG_8814B(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8814B) & BIT_MASK_SDIO_C2H_MSG_8814B) - - +#define BIT_SDIO_C2H_MSG_8814B(x) \ + (((x) & BIT_MASK_SDIO_C2H_MSG_8814B) << BIT_SHIFT_SDIO_C2H_MSG_8814B) +#define BITS_SDIO_C2H_MSG_8814B \ + (BIT_MASK_SDIO_C2H_MSG_8814B << BIT_SHIFT_SDIO_C2H_MSG_8814B) +#define BIT_CLEAR_SDIO_C2H_MSG_8814B(x) ((x) & (~BITS_SDIO_C2H_MSG_8814B)) +#define BIT_GET_SDIO_C2H_MSG_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8814B) & BIT_MASK_SDIO_C2H_MSG_8814B) +#define BIT_SET_SDIO_C2H_MSG_8814B(x, v) \ + (BIT_CLEAR_SDIO_C2H_MSG_8814B(x) | BIT_SDIO_C2H_MSG_8814B(v)) /* 2 REG_SDIO_HRPWM1_8814B */ -#define BIT_TOGGLING_8814B BIT(7) +#define BIT_TOGGLE_8814B BIT(7) #define BIT_ACK_8814B BIT(6) -#define BIT_32K_PERMISSION_8814B BIT(0) +#define BIT_REQ_PS_8814B BIT(0) /* 2 REG_SDIO_HRPWM2_8814B */ @@ -11640,27 +26335,39 @@ #define BIT_SHIFT_CMDIN_2RESP_TIMER_8814B 0 #define BIT_MASK_CMDIN_2RESP_TIMER_8814B 0xffff -#define BIT_CMDIN_2RESP_TIMER_8814B(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8814B) << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) -#define BIT_GET_CMDIN_2RESP_TIMER_8814B(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) & BIT_MASK_CMDIN_2RESP_TIMER_8814B) - - +#define BIT_CMDIN_2RESP_TIMER_8814B(x) \ + (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8814B) \ + << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) +#define BITS_CMDIN_2RESP_TIMER_8814B \ + (BIT_MASK_CMDIN_2RESP_TIMER_8814B << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) +#define BIT_CLEAR_CMDIN_2RESP_TIMER_8814B(x) \ + ((x) & (~BITS_CMDIN_2RESP_TIMER_8814B)) +#define BIT_GET_CMDIN_2RESP_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) & \ + BIT_MASK_CMDIN_2RESP_TIMER_8814B) +#define BIT_SET_CMDIN_2RESP_TIMER_8814B(x, v) \ + (BIT_CLEAR_CMDIN_2RESP_TIMER_8814B(x) | BIT_CMDIN_2RESP_TIMER_8814B(v)) /* 2 REG_SDIO_CMD_CRC_8814B */ #define BIT_SHIFT_SDIO_CMD_CRC_V1_8814B 0 #define BIT_MASK_SDIO_CMD_CRC_V1_8814B 0xff -#define BIT_SDIO_CMD_CRC_V1_8814B(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8814B) << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) -#define BIT_GET_SDIO_CMD_CRC_V1_8814B(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) & BIT_MASK_SDIO_CMD_CRC_V1_8814B) - - +#define BIT_SDIO_CMD_CRC_V1_8814B(x) \ + (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8814B) \ + << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) +#define BITS_SDIO_CMD_CRC_V1_8814B \ + (BIT_MASK_SDIO_CMD_CRC_V1_8814B << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) +#define BIT_CLEAR_SDIO_CMD_CRC_V1_8814B(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8814B)) +#define BIT_GET_SDIO_CMD_CRC_V1_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) & \ + BIT_MASK_SDIO_CMD_CRC_V1_8814B) +#define BIT_SET_SDIO_CMD_CRC_V1_8814B(x, v) \ + (BIT_CLEAR_SDIO_CMD_CRC_V1_8814B(x) | BIT_SDIO_CMD_CRC_V1_8814B(v)) /* 2 REG_SDIO_HSISR_8814B */ #define BIT_DRV_WLAN_INT_CLR_8814B BIT(1) #define BIT_DRV_WLAN_INT_8814B BIT(0) -/* 2 REG_SDIO_HSIMR_8814B */ -#define BIT_HISR_MASK_8814B BIT(0) - /* 2 REG_SDIO_ERR_RPT_8814B */ #define BIT_HR_FF_OVF_8814B BIT(6) #define BIT_HR_FF_UDN_8814B BIT(5) @@ -11674,28 +26381,53 @@ #define BIT_SHIFT_CMD_CRC_ERR_CNT_8814B 0 #define BIT_MASK_CMD_CRC_ERR_CNT_8814B 0xff -#define BIT_CMD_CRC_ERR_CNT_8814B(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8814B) << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) -#define BIT_GET_CMD_CRC_ERR_CNT_8814B(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) & BIT_MASK_CMD_CRC_ERR_CNT_8814B) - - +#define BIT_CMD_CRC_ERR_CNT_8814B(x) \ + (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8814B) \ + << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) +#define BITS_CMD_CRC_ERR_CNT_8814B \ + (BIT_MASK_CMD_CRC_ERR_CNT_8814B << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) +#define BIT_CLEAR_CMD_CRC_ERR_CNT_8814B(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8814B)) +#define BIT_GET_CMD_CRC_ERR_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) & \ + BIT_MASK_CMD_CRC_ERR_CNT_8814B) +#define BIT_SET_CMD_CRC_ERR_CNT_8814B(x, v) \ + (BIT_CLEAR_CMD_CRC_ERR_CNT_8814B(x) | BIT_CMD_CRC_ERR_CNT_8814B(v)) /* 2 REG_SDIO_DATA_ERRCNT_8814B */ #define BIT_SHIFT_DATA_CRC_ERR_CNT_8814B 0 #define BIT_MASK_DATA_CRC_ERR_CNT_8814B 0xff -#define BIT_DATA_CRC_ERR_CNT_8814B(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8814B) << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) -#define BIT_GET_DATA_CRC_ERR_CNT_8814B(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) & BIT_MASK_DATA_CRC_ERR_CNT_8814B) - - +#define BIT_DATA_CRC_ERR_CNT_8814B(x) \ + (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8814B) \ + << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) +#define BITS_DATA_CRC_ERR_CNT_8814B \ + (BIT_MASK_DATA_CRC_ERR_CNT_8814B << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) +#define BIT_CLEAR_DATA_CRC_ERR_CNT_8814B(x) \ + ((x) & (~BITS_DATA_CRC_ERR_CNT_8814B)) +#define BIT_GET_DATA_CRC_ERR_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) & \ + BIT_MASK_DATA_CRC_ERR_CNT_8814B) +#define BIT_SET_DATA_CRC_ERR_CNT_8814B(x, v) \ + (BIT_CLEAR_DATA_CRC_ERR_CNT_8814B(x) | BIT_DATA_CRC_ERR_CNT_8814B(v)) /* 2 REG_SDIO_CMD_ERR_CONTENT_8814B */ #define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B 0 #define BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B 0xffffffffffL -#define BIT_SDIO_CMD_ERR_CONTENT_8814B(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) -#define BIT_GET_SDIO_CMD_ERR_CONTENT_8814B(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B) - - +#define BIT_SDIO_CMD_ERR_CONTENT_8814B(x) \ + (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B) \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) +#define BITS_SDIO_CMD_ERR_CONTENT_8814B \ + (BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) +#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8814B(x) \ + ((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8814B)) +#define BIT_GET_SDIO_CMD_ERR_CONTENT_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) & \ + BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B) +#define BIT_SET_SDIO_CMD_ERR_CONTENT_8814B(x, v) \ + (BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8814B(x) | \ + BIT_SDIO_CMD_ERR_CONTENT_8814B(v)) /* 2 REG_SDIO_CRC_ERR_IDX_8814B */ #define BIT_D3_CRC_ERR_8814B BIT(4) @@ -11707,19 +26439,34 @@ /* 2 REG_SDIO_DATA_CRC_8814B */ #define BIT_SHIFT_SDIO_DATA_CRC_8814B 0 -#define BIT_MASK_SDIO_DATA_CRC_8814B 0xff -#define BIT_SDIO_DATA_CRC_8814B(x) (((x) & BIT_MASK_SDIO_DATA_CRC_8814B) << BIT_SHIFT_SDIO_DATA_CRC_8814B) -#define BIT_GET_SDIO_DATA_CRC_8814B(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8814B) & BIT_MASK_SDIO_DATA_CRC_8814B) - - +#define BIT_MASK_SDIO_DATA_CRC_8814B 0xffff +#define BIT_SDIO_DATA_CRC_8814B(x) \ + (((x) & BIT_MASK_SDIO_DATA_CRC_8814B) << BIT_SHIFT_SDIO_DATA_CRC_8814B) +#define BITS_SDIO_DATA_CRC_8814B \ + (BIT_MASK_SDIO_DATA_CRC_8814B << BIT_SHIFT_SDIO_DATA_CRC_8814B) +#define BIT_CLEAR_SDIO_DATA_CRC_8814B(x) ((x) & (~BITS_SDIO_DATA_CRC_8814B)) +#define BIT_GET_SDIO_DATA_CRC_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8814B) & BIT_MASK_SDIO_DATA_CRC_8814B) +#define BIT_SET_SDIO_DATA_CRC_8814B(x, v) \ + (BIT_CLEAR_SDIO_DATA_CRC_8814B(x) | BIT_SDIO_DATA_CRC_8814B(v)) /* 2 REG_SDIO_DATA_REPLY_TIME_8814B */ #define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B 0 #define BIT_MASK_SDIO_DATA_REPLY_TIME_8814B 0x7 -#define BIT_SDIO_DATA_REPLY_TIME_8814B(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8814B) << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) -#define BIT_GET_SDIO_DATA_REPLY_TIME_8814B(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) & BIT_MASK_SDIO_DATA_REPLY_TIME_8814B) - - +#define BIT_SDIO_DATA_REPLY_TIME_8814B(x) \ + (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8814B) \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) +#define BITS_SDIO_DATA_REPLY_TIME_8814B \ + (BIT_MASK_SDIO_DATA_REPLY_TIME_8814B \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) +#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8814B(x) \ + ((x) & (~BITS_SDIO_DATA_REPLY_TIME_8814B)) +#define BIT_GET_SDIO_DATA_REPLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) & \ + BIT_MASK_SDIO_DATA_REPLY_TIME_8814B) +#define BIT_SET_SDIO_DATA_REPLY_TIME_8814B(x, v) \ + (BIT_CLEAR_SDIO_DATA_REPLY_TIME_8814B(x) | \ + BIT_SDIO_DATA_REPLY_TIME_8814B(v)) #endif diff --git a/hal/halmac/halmac_bit_8821c.h b/hal/halmac/halmac_bit_8821c.h index 880146b..7538125 100644 --- a/hal/halmac/halmac_bit_8821c.h +++ b/hal/halmac/halmac_bit_8821c.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -106,16 +106,25 @@ #define BIT_SHIFT_VPDIDX_8821C 8 #define BIT_MASK_VPDIDX_8821C 0xff -#define BIT_VPDIDX_8821C(x) (((x) & BIT_MASK_VPDIDX_8821C) << BIT_SHIFT_VPDIDX_8821C) -#define BIT_GET_VPDIDX_8821C(x) (((x) >> BIT_SHIFT_VPDIDX_8821C) & BIT_MASK_VPDIDX_8821C) - - +#define BIT_VPDIDX_8821C(x) \ + (((x) & BIT_MASK_VPDIDX_8821C) << BIT_SHIFT_VPDIDX_8821C) +#define BITS_VPDIDX_8821C (BIT_MASK_VPDIDX_8821C << BIT_SHIFT_VPDIDX_8821C) +#define BIT_CLEAR_VPDIDX_8821C(x) ((x) & (~BITS_VPDIDX_8821C)) +#define BIT_GET_VPDIDX_8821C(x) \ + (((x) >> BIT_SHIFT_VPDIDX_8821C) & BIT_MASK_VPDIDX_8821C) +#define BIT_SET_VPDIDX_8821C(x, v) \ + (BIT_CLEAR_VPDIDX_8821C(x) | BIT_VPDIDX_8821C(v)) #define BIT_SHIFT_EEM1_0_8821C 6 #define BIT_MASK_EEM1_0_8821C 0x3 -#define BIT_EEM1_0_8821C(x) (((x) & BIT_MASK_EEM1_0_8821C) << BIT_SHIFT_EEM1_0_8821C) -#define BIT_GET_EEM1_0_8821C(x) (((x) >> BIT_SHIFT_EEM1_0_8821C) & BIT_MASK_EEM1_0_8821C) - +#define BIT_EEM1_0_8821C(x) \ + (((x) & BIT_MASK_EEM1_0_8821C) << BIT_SHIFT_EEM1_0_8821C) +#define BITS_EEM1_0_8821C (BIT_MASK_EEM1_0_8821C << BIT_SHIFT_EEM1_0_8821C) +#define BIT_CLEAR_EEM1_0_8821C(x) ((x) & (~BITS_EEM1_0_8821C)) +#define BIT_GET_EEM1_0_8821C(x) \ + (((x) >> BIT_SHIFT_EEM1_0_8821C) & BIT_MASK_EEM1_0_8821C) +#define BIT_SET_EEM1_0_8821C(x, v) \ + (BIT_CLEAR_EEM1_0_8821C(x) | BIT_EEM1_0_8821C(v)) #define BIT_AUTOLOAD_SUS_8821C BIT(5) #define BIT_EERPOMSEL_8821C BIT(4) @@ -128,10 +137,15 @@ #define BIT_SHIFT_VPD_DATA_8821C 0 #define BIT_MASK_VPD_DATA_8821C 0xffffffffL -#define BIT_VPD_DATA_8821C(x) (((x) & BIT_MASK_VPD_DATA_8821C) << BIT_SHIFT_VPD_DATA_8821C) -#define BIT_GET_VPD_DATA_8821C(x) (((x) >> BIT_SHIFT_VPD_DATA_8821C) & BIT_MASK_VPD_DATA_8821C) - - +#define BIT_VPD_DATA_8821C(x) \ + (((x) & BIT_MASK_VPD_DATA_8821C) << BIT_SHIFT_VPD_DATA_8821C) +#define BITS_VPD_DATA_8821C \ + (BIT_MASK_VPD_DATA_8821C << BIT_SHIFT_VPD_DATA_8821C) +#define BIT_CLEAR_VPD_DATA_8821C(x) ((x) & (~BITS_VPD_DATA_8821C)) +#define BIT_GET_VPD_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_VPD_DATA_8821C) & BIT_MASK_VPD_DATA_8821C) +#define BIT_SET_VPD_DATA_8821C(x, v) \ + (BIT_CLEAR_VPD_DATA_8821C(x) | BIT_VPD_DATA_8821C(v)) /* 2 REG_SYS_SWR_CTRL1_8821C */ #define BIT_C2_L_BIT0_8821C BIT(31) @@ -139,23 +153,37 @@ #define BIT_SHIFT_C1_L_8821C 29 #define BIT_MASK_C1_L_8821C 0x3 #define BIT_C1_L_8821C(x) (((x) & BIT_MASK_C1_L_8821C) << BIT_SHIFT_C1_L_8821C) -#define BIT_GET_C1_L_8821C(x) (((x) >> BIT_SHIFT_C1_L_8821C) & BIT_MASK_C1_L_8821C) - - +#define BITS_C1_L_8821C (BIT_MASK_C1_L_8821C << BIT_SHIFT_C1_L_8821C) +#define BIT_CLEAR_C1_L_8821C(x) ((x) & (~BITS_C1_L_8821C)) +#define BIT_GET_C1_L_8821C(x) \ + (((x) >> BIT_SHIFT_C1_L_8821C) & BIT_MASK_C1_L_8821C) +#define BIT_SET_C1_L_8821C(x, v) (BIT_CLEAR_C1_L_8821C(x) | BIT_C1_L_8821C(v)) #define BIT_SHIFT_REG_FREQ_L_8821C 25 #define BIT_MASK_REG_FREQ_L_8821C 0x7 -#define BIT_REG_FREQ_L_8821C(x) (((x) & BIT_MASK_REG_FREQ_L_8821C) << BIT_SHIFT_REG_FREQ_L_8821C) -#define BIT_GET_REG_FREQ_L_8821C(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8821C) & BIT_MASK_REG_FREQ_L_8821C) - +#define BIT_REG_FREQ_L_8821C(x) \ + (((x) & BIT_MASK_REG_FREQ_L_8821C) << BIT_SHIFT_REG_FREQ_L_8821C) +#define BITS_REG_FREQ_L_8821C \ + (BIT_MASK_REG_FREQ_L_8821C << BIT_SHIFT_REG_FREQ_L_8821C) +#define BIT_CLEAR_REG_FREQ_L_8821C(x) ((x) & (~BITS_REG_FREQ_L_8821C)) +#define BIT_GET_REG_FREQ_L_8821C(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L_8821C) & BIT_MASK_REG_FREQ_L_8821C) +#define BIT_SET_REG_FREQ_L_8821C(x, v) \ + (BIT_CLEAR_REG_FREQ_L_8821C(x) | BIT_REG_FREQ_L_8821C(v)) #define BIT_REG_EN_DUTY_8821C BIT(24) #define BIT_SHIFT_REG_MODE_8821C 22 #define BIT_MASK_REG_MODE_8821C 0x3 -#define BIT_REG_MODE_8821C(x) (((x) & BIT_MASK_REG_MODE_8821C) << BIT_SHIFT_REG_MODE_8821C) -#define BIT_GET_REG_MODE_8821C(x) (((x) >> BIT_SHIFT_REG_MODE_8821C) & BIT_MASK_REG_MODE_8821C) - +#define BIT_REG_MODE_8821C(x) \ + (((x) & BIT_MASK_REG_MODE_8821C) << BIT_SHIFT_REG_MODE_8821C) +#define BITS_REG_MODE_8821C \ + (BIT_MASK_REG_MODE_8821C << BIT_SHIFT_REG_MODE_8821C) +#define BIT_CLEAR_REG_MODE_8821C(x) ((x) & (~BITS_REG_MODE_8821C)) +#define BIT_GET_REG_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_REG_MODE_8821C) & BIT_MASK_REG_MODE_8821C) +#define BIT_SET_REG_MODE_8821C(x, v) \ + (BIT_CLEAR_REG_MODE_8821C(x) | BIT_REG_MODE_8821C(v)) #define BIT_REG_EN_SP_8821C BIT(21) #define BIT_REG_AUTO_L_8821C BIT(20) @@ -164,16 +192,23 @@ #define BIT_SHIFT_OCP_L1_8821C 15 #define BIT_MASK_OCP_L1_8821C 0x7 -#define BIT_OCP_L1_8821C(x) (((x) & BIT_MASK_OCP_L1_8821C) << BIT_SHIFT_OCP_L1_8821C) -#define BIT_GET_OCP_L1_8821C(x) (((x) >> BIT_SHIFT_OCP_L1_8821C) & BIT_MASK_OCP_L1_8821C) - - +#define BIT_OCP_L1_8821C(x) \ + (((x) & BIT_MASK_OCP_L1_8821C) << BIT_SHIFT_OCP_L1_8821C) +#define BITS_OCP_L1_8821C (BIT_MASK_OCP_L1_8821C << BIT_SHIFT_OCP_L1_8821C) +#define BIT_CLEAR_OCP_L1_8821C(x) ((x) & (~BITS_OCP_L1_8821C)) +#define BIT_GET_OCP_L1_8821C(x) \ + (((x) >> BIT_SHIFT_OCP_L1_8821C) & BIT_MASK_OCP_L1_8821C) +#define BIT_SET_OCP_L1_8821C(x, v) \ + (BIT_CLEAR_OCP_L1_8821C(x) | BIT_OCP_L1_8821C(v)) #define BIT_SHIFT_CF_L_8821C 13 #define BIT_MASK_CF_L_8821C 0x3 #define BIT_CF_L_8821C(x) (((x) & BIT_MASK_CF_L_8821C) << BIT_SHIFT_CF_L_8821C) -#define BIT_GET_CF_L_8821C(x) (((x) >> BIT_SHIFT_CF_L_8821C) & BIT_MASK_CF_L_8821C) - +#define BITS_CF_L_8821C (BIT_MASK_CF_L_8821C << BIT_SHIFT_CF_L_8821C) +#define BIT_CLEAR_CF_L_8821C(x) ((x) & (~BITS_CF_L_8821C)) +#define BIT_GET_CF_L_8821C(x) \ + (((x) >> BIT_SHIFT_CF_L_8821C) & BIT_MASK_CF_L_8821C) +#define BIT_SET_CF_L_8821C(x, v) (BIT_CLEAR_CF_L_8821C(x) | BIT_CF_L_8821C(v)) #define BIT_SW18_FPWM_8821C BIT(11) #define BIT_SW18_SWEN_8821C BIT(9) @@ -187,37 +222,62 @@ #define BIT_SHIFT_REG_DELAY_8821C 28 #define BIT_MASK_REG_DELAY_8821C 0x3 -#define BIT_REG_DELAY_8821C(x) (((x) & BIT_MASK_REG_DELAY_8821C) << BIT_SHIFT_REG_DELAY_8821C) -#define BIT_GET_REG_DELAY_8821C(x) (((x) >> BIT_SHIFT_REG_DELAY_8821C) & BIT_MASK_REG_DELAY_8821C) - - +#define BIT_REG_DELAY_8821C(x) \ + (((x) & BIT_MASK_REG_DELAY_8821C) << BIT_SHIFT_REG_DELAY_8821C) +#define BITS_REG_DELAY_8821C \ + (BIT_MASK_REG_DELAY_8821C << BIT_SHIFT_REG_DELAY_8821C) +#define BIT_CLEAR_REG_DELAY_8821C(x) ((x) & (~BITS_REG_DELAY_8821C)) +#define BIT_GET_REG_DELAY_8821C(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_8821C) & BIT_MASK_REG_DELAY_8821C) +#define BIT_SET_REG_DELAY_8821C(x, v) \ + (BIT_CLEAR_REG_DELAY_8821C(x) | BIT_REG_DELAY_8821C(v)) #define BIT_SHIFT_V15ADJ_L1_V1_8821C 24 #define BIT_MASK_V15ADJ_L1_V1_8821C 0x7 -#define BIT_V15ADJ_L1_V1_8821C(x) (((x) & BIT_MASK_V15ADJ_L1_V1_8821C) << BIT_SHIFT_V15ADJ_L1_V1_8821C) -#define BIT_GET_V15ADJ_L1_V1_8821C(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8821C) & BIT_MASK_V15ADJ_L1_V1_8821C) - - +#define BIT_V15ADJ_L1_V1_8821C(x) \ + (((x) & BIT_MASK_V15ADJ_L1_V1_8821C) << BIT_SHIFT_V15ADJ_L1_V1_8821C) +#define BITS_V15ADJ_L1_V1_8821C \ + (BIT_MASK_V15ADJ_L1_V1_8821C << BIT_SHIFT_V15ADJ_L1_V1_8821C) +#define BIT_CLEAR_V15ADJ_L1_V1_8821C(x) ((x) & (~BITS_V15ADJ_L1_V1_8821C)) +#define BIT_GET_V15ADJ_L1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8821C) & BIT_MASK_V15ADJ_L1_V1_8821C) +#define BIT_SET_V15ADJ_L1_V1_8821C(x, v) \ + (BIT_CLEAR_V15ADJ_L1_V1_8821C(x) | BIT_V15ADJ_L1_V1_8821C(v)) #define BIT_SHIFT_VOL_L1_V1_8821C 20 #define BIT_MASK_VOL_L1_V1_8821C 0xf -#define BIT_VOL_L1_V1_8821C(x) (((x) & BIT_MASK_VOL_L1_V1_8821C) << BIT_SHIFT_VOL_L1_V1_8821C) -#define BIT_GET_VOL_L1_V1_8821C(x) (((x) >> BIT_SHIFT_VOL_L1_V1_8821C) & BIT_MASK_VOL_L1_V1_8821C) - - +#define BIT_VOL_L1_V1_8821C(x) \ + (((x) & BIT_MASK_VOL_L1_V1_8821C) << BIT_SHIFT_VOL_L1_V1_8821C) +#define BITS_VOL_L1_V1_8821C \ + (BIT_MASK_VOL_L1_V1_8821C << BIT_SHIFT_VOL_L1_V1_8821C) +#define BIT_CLEAR_VOL_L1_V1_8821C(x) ((x) & (~BITS_VOL_L1_V1_8821C)) +#define BIT_GET_VOL_L1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_VOL_L1_V1_8821C) & BIT_MASK_VOL_L1_V1_8821C) +#define BIT_SET_VOL_L1_V1_8821C(x, v) \ + (BIT_CLEAR_VOL_L1_V1_8821C(x) | BIT_VOL_L1_V1_8821C(v)) #define BIT_SHIFT_IN_L1_V1_8821C 17 #define BIT_MASK_IN_L1_V1_8821C 0x7 -#define BIT_IN_L1_V1_8821C(x) (((x) & BIT_MASK_IN_L1_V1_8821C) << BIT_SHIFT_IN_L1_V1_8821C) -#define BIT_GET_IN_L1_V1_8821C(x) (((x) >> BIT_SHIFT_IN_L1_V1_8821C) & BIT_MASK_IN_L1_V1_8821C) - - +#define BIT_IN_L1_V1_8821C(x) \ + (((x) & BIT_MASK_IN_L1_V1_8821C) << BIT_SHIFT_IN_L1_V1_8821C) +#define BITS_IN_L1_V1_8821C \ + (BIT_MASK_IN_L1_V1_8821C << BIT_SHIFT_IN_L1_V1_8821C) +#define BIT_CLEAR_IN_L1_V1_8821C(x) ((x) & (~BITS_IN_L1_V1_8821C)) +#define BIT_GET_IN_L1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_IN_L1_V1_8821C) & BIT_MASK_IN_L1_V1_8821C) +#define BIT_SET_IN_L1_V1_8821C(x, v) \ + (BIT_CLEAR_IN_L1_V1_8821C(x) | BIT_IN_L1_V1_8821C(v)) #define BIT_SHIFT_TBOX_L1_8821C 15 #define BIT_MASK_TBOX_L1_8821C 0x3 -#define BIT_TBOX_L1_8821C(x) (((x) & BIT_MASK_TBOX_L1_8821C) << BIT_SHIFT_TBOX_L1_8821C) -#define BIT_GET_TBOX_L1_8821C(x) (((x) >> BIT_SHIFT_TBOX_L1_8821C) & BIT_MASK_TBOX_L1_8821C) - +#define BIT_TBOX_L1_8821C(x) \ + (((x) & BIT_MASK_TBOX_L1_8821C) << BIT_SHIFT_TBOX_L1_8821C) +#define BITS_TBOX_L1_8821C (BIT_MASK_TBOX_L1_8821C << BIT_SHIFT_TBOX_L1_8821C) +#define BIT_CLEAR_TBOX_L1_8821C(x) ((x) & (~BITS_TBOX_L1_8821C)) +#define BIT_GET_TBOX_L1_8821C(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_8821C) & BIT_MASK_TBOX_L1_8821C) +#define BIT_SET_TBOX_L1_8821C(x, v) \ + (BIT_CLEAR_TBOX_L1_8821C(x) | BIT_TBOX_L1_8821C(v)) #define BIT_SW18_SEL_8821C BIT(13) @@ -227,29 +287,44 @@ #define BIT_SHIFT_R3_L_8821C 7 #define BIT_MASK_R3_L_8821C 0x3 #define BIT_R3_L_8821C(x) (((x) & BIT_MASK_R3_L_8821C) << BIT_SHIFT_R3_L_8821C) -#define BIT_GET_R3_L_8821C(x) (((x) >> BIT_SHIFT_R3_L_8821C) & BIT_MASK_R3_L_8821C) - - +#define BITS_R3_L_8821C (BIT_MASK_R3_L_8821C << BIT_SHIFT_R3_L_8821C) +#define BIT_CLEAR_R3_L_8821C(x) ((x) & (~BITS_R3_L_8821C)) +#define BIT_GET_R3_L_8821C(x) \ + (((x) >> BIT_SHIFT_R3_L_8821C) & BIT_MASK_R3_L_8821C) +#define BIT_SET_R3_L_8821C(x, v) (BIT_CLEAR_R3_L_8821C(x) | BIT_R3_L_8821C(v)) #define BIT_SHIFT_SW18_R2_8821C 5 #define BIT_MASK_SW18_R2_8821C 0x3 -#define BIT_SW18_R2_8821C(x) (((x) & BIT_MASK_SW18_R2_8821C) << BIT_SHIFT_SW18_R2_8821C) -#define BIT_GET_SW18_R2_8821C(x) (((x) >> BIT_SHIFT_SW18_R2_8821C) & BIT_MASK_SW18_R2_8821C) - - +#define BIT_SW18_R2_8821C(x) \ + (((x) & BIT_MASK_SW18_R2_8821C) << BIT_SHIFT_SW18_R2_8821C) +#define BITS_SW18_R2_8821C (BIT_MASK_SW18_R2_8821C << BIT_SHIFT_SW18_R2_8821C) +#define BIT_CLEAR_SW18_R2_8821C(x) ((x) & (~BITS_SW18_R2_8821C)) +#define BIT_GET_SW18_R2_8821C(x) \ + (((x) >> BIT_SHIFT_SW18_R2_8821C) & BIT_MASK_SW18_R2_8821C) +#define BIT_SET_SW18_R2_8821C(x, v) \ + (BIT_CLEAR_SW18_R2_8821C(x) | BIT_SW18_R2_8821C(v)) #define BIT_SHIFT_SW18_R1_8821C 3 #define BIT_MASK_SW18_R1_8821C 0x3 -#define BIT_SW18_R1_8821C(x) (((x) & BIT_MASK_SW18_R1_8821C) << BIT_SHIFT_SW18_R1_8821C) -#define BIT_GET_SW18_R1_8821C(x) (((x) >> BIT_SHIFT_SW18_R1_8821C) & BIT_MASK_SW18_R1_8821C) - - +#define BIT_SW18_R1_8821C(x) \ + (((x) & BIT_MASK_SW18_R1_8821C) << BIT_SHIFT_SW18_R1_8821C) +#define BITS_SW18_R1_8821C (BIT_MASK_SW18_R1_8821C << BIT_SHIFT_SW18_R1_8821C) +#define BIT_CLEAR_SW18_R1_8821C(x) ((x) & (~BITS_SW18_R1_8821C)) +#define BIT_GET_SW18_R1_8821C(x) \ + (((x) >> BIT_SHIFT_SW18_R1_8821C) & BIT_MASK_SW18_R1_8821C) +#define BIT_SET_SW18_R1_8821C(x, v) \ + (BIT_CLEAR_SW18_R1_8821C(x) | BIT_SW18_R1_8821C(v)) #define BIT_SHIFT_C3_L_C3_8821C 1 #define BIT_MASK_C3_L_C3_8821C 0x3 -#define BIT_C3_L_C3_8821C(x) (((x) & BIT_MASK_C3_L_C3_8821C) << BIT_SHIFT_C3_L_C3_8821C) -#define BIT_GET_C3_L_C3_8821C(x) (((x) >> BIT_SHIFT_C3_L_C3_8821C) & BIT_MASK_C3_L_C3_8821C) - +#define BIT_C3_L_C3_8821C(x) \ + (((x) & BIT_MASK_C3_L_C3_8821C) << BIT_SHIFT_C3_L_C3_8821C) +#define BITS_C3_L_C3_8821C (BIT_MASK_C3_L_C3_8821C << BIT_SHIFT_C3_L_C3_8821C) +#define BIT_CLEAR_C3_L_C3_8821C(x) ((x) & (~BITS_C3_L_C3_8821C)) +#define BIT_GET_C3_L_C3_8821C(x) \ + (((x) >> BIT_SHIFT_C3_L_C3_8821C) & BIT_MASK_C3_L_C3_8821C) +#define BIT_SET_C3_L_C3_8821C(x, v) \ + (BIT_CLEAR_C3_L_C3_8821C(x) | BIT_C3_L_C3_8821C(v)) #define BIT_C2_L_BIT1_8821C BIT(0) @@ -258,17 +333,27 @@ #define BIT_SHIFT_SPS18_OCP_TH_8821C 16 #define BIT_MASK_SPS18_OCP_TH_8821C 0x7fff -#define BIT_SPS18_OCP_TH_8821C(x) (((x) & BIT_MASK_SPS18_OCP_TH_8821C) << BIT_SHIFT_SPS18_OCP_TH_8821C) -#define BIT_GET_SPS18_OCP_TH_8821C(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8821C) & BIT_MASK_SPS18_OCP_TH_8821C) - - +#define BIT_SPS18_OCP_TH_8821C(x) \ + (((x) & BIT_MASK_SPS18_OCP_TH_8821C) << BIT_SHIFT_SPS18_OCP_TH_8821C) +#define BITS_SPS18_OCP_TH_8821C \ + (BIT_MASK_SPS18_OCP_TH_8821C << BIT_SHIFT_SPS18_OCP_TH_8821C) +#define BIT_CLEAR_SPS18_OCP_TH_8821C(x) ((x) & (~BITS_SPS18_OCP_TH_8821C)) +#define BIT_GET_SPS18_OCP_TH_8821C(x) \ + (((x) >> BIT_SHIFT_SPS18_OCP_TH_8821C) & BIT_MASK_SPS18_OCP_TH_8821C) +#define BIT_SET_SPS18_OCP_TH_8821C(x, v) \ + (BIT_CLEAR_SPS18_OCP_TH_8821C(x) | BIT_SPS18_OCP_TH_8821C(v)) #define BIT_SHIFT_OCP_WINDOW_8821C 0 #define BIT_MASK_OCP_WINDOW_8821C 0xffff -#define BIT_OCP_WINDOW_8821C(x) (((x) & BIT_MASK_OCP_WINDOW_8821C) << BIT_SHIFT_OCP_WINDOW_8821C) -#define BIT_GET_OCP_WINDOW_8821C(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8821C) & BIT_MASK_OCP_WINDOW_8821C) - - +#define BIT_OCP_WINDOW_8821C(x) \ + (((x) & BIT_MASK_OCP_WINDOW_8821C) << BIT_SHIFT_OCP_WINDOW_8821C) +#define BITS_OCP_WINDOW_8821C \ + (BIT_MASK_OCP_WINDOW_8821C << BIT_SHIFT_OCP_WINDOW_8821C) +#define BIT_CLEAR_OCP_WINDOW_8821C(x) ((x) & (~BITS_OCP_WINDOW_8821C)) +#define BIT_GET_OCP_WINDOW_8821C(x) \ + (((x) >> BIT_SHIFT_OCP_WINDOW_8821C) & BIT_MASK_OCP_WINDOW_8821C) +#define BIT_SET_OCP_WINDOW_8821C(x, v) \ + (BIT_CLEAR_OCP_WINDOW_8821C(x) | BIT_OCP_WINDOW_8821C(v)) /* 2 REG_RSV_CTRL_8821C */ #define BIT_HREG_DBG_8821C BIT(23) @@ -291,17 +376,29 @@ #define BIT_SHIFT_LPLDH12_RSV_8821C 29 #define BIT_MASK_LPLDH12_RSV_8821C 0x7 -#define BIT_LPLDH12_RSV_8821C(x) (((x) & BIT_MASK_LPLDH12_RSV_8821C) << BIT_SHIFT_LPLDH12_RSV_8821C) -#define BIT_GET_LPLDH12_RSV_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8821C) & BIT_MASK_LPLDH12_RSV_8821C) - +#define BIT_LPLDH12_RSV_8821C(x) \ + (((x) & BIT_MASK_LPLDH12_RSV_8821C) << BIT_SHIFT_LPLDH12_RSV_8821C) +#define BITS_LPLDH12_RSV_8821C \ + (BIT_MASK_LPLDH12_RSV_8821C << BIT_SHIFT_LPLDH12_RSV_8821C) +#define BIT_CLEAR_LPLDH12_RSV_8821C(x) ((x) & (~BITS_LPLDH12_RSV_8821C)) +#define BIT_GET_LPLDH12_RSV_8821C(x) \ + (((x) >> BIT_SHIFT_LPLDH12_RSV_8821C) & BIT_MASK_LPLDH12_RSV_8821C) +#define BIT_SET_LPLDH12_RSV_8821C(x, v) \ + (BIT_CLEAR_LPLDH12_RSV_8821C(x) | BIT_LPLDH12_RSV_8821C(v)) #define BIT_LPLDH12_SLP_8821C BIT(28) #define BIT_SHIFT_LPLDH12_VADJ_8821C 24 #define BIT_MASK_LPLDH12_VADJ_8821C 0xf -#define BIT_LPLDH12_VADJ_8821C(x) (((x) & BIT_MASK_LPLDH12_VADJ_8821C) << BIT_SHIFT_LPLDH12_VADJ_8821C) -#define BIT_GET_LPLDH12_VADJ_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8821C) & BIT_MASK_LPLDH12_VADJ_8821C) - +#define BIT_LPLDH12_VADJ_8821C(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_8821C) << BIT_SHIFT_LPLDH12_VADJ_8821C) +#define BITS_LPLDH12_VADJ_8821C \ + (BIT_MASK_LPLDH12_VADJ_8821C << BIT_SHIFT_LPLDH12_VADJ_8821C) +#define BIT_CLEAR_LPLDH12_VADJ_8821C(x) ((x) & (~BITS_LPLDH12_VADJ_8821C)) +#define BIT_GET_LPLDH12_VADJ_8821C(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_8821C) & BIT_MASK_LPLDH12_VADJ_8821C) +#define BIT_SET_LPLDH12_VADJ_8821C(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_8821C(x) | BIT_LPLDH12_VADJ_8821C(v)) #define BIT_PCIE_CALIB_EN_8821C BIT(17) #define BIT_LDH12_EN_8821C BIT(16) @@ -326,46 +423,79 @@ #define BIT_SHIFT_XTAL_CAP_XI_8821C 25 #define BIT_MASK_XTAL_CAP_XI_8821C 0x3f -#define BIT_XTAL_CAP_XI_8821C(x) (((x) & BIT_MASK_XTAL_CAP_XI_8821C) << BIT_SHIFT_XTAL_CAP_XI_8821C) -#define BIT_GET_XTAL_CAP_XI_8821C(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8821C) & BIT_MASK_XTAL_CAP_XI_8821C) - - +#define BIT_XTAL_CAP_XI_8821C(x) \ + (((x) & BIT_MASK_XTAL_CAP_XI_8821C) << BIT_SHIFT_XTAL_CAP_XI_8821C) +#define BITS_XTAL_CAP_XI_8821C \ + (BIT_MASK_XTAL_CAP_XI_8821C << BIT_SHIFT_XTAL_CAP_XI_8821C) +#define BIT_CLEAR_XTAL_CAP_XI_8821C(x) ((x) & (~BITS_XTAL_CAP_XI_8821C)) +#define BIT_GET_XTAL_CAP_XI_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XI_8821C) & BIT_MASK_XTAL_CAP_XI_8821C) +#define BIT_SET_XTAL_CAP_XI_8821C(x, v) \ + (BIT_CLEAR_XTAL_CAP_XI_8821C(x) | BIT_XTAL_CAP_XI_8821C(v)) #define BIT_SHIFT_XTAL_DRV_DIGI_8821C 23 #define BIT_MASK_XTAL_DRV_DIGI_8821C 0x3 -#define BIT_XTAL_DRV_DIGI_8821C(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8821C) << BIT_SHIFT_XTAL_DRV_DIGI_8821C) -#define BIT_GET_XTAL_DRV_DIGI_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8821C) & BIT_MASK_XTAL_DRV_DIGI_8821C) - +#define BIT_XTAL_DRV_DIGI_8821C(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_8821C) << BIT_SHIFT_XTAL_DRV_DIGI_8821C) +#define BITS_XTAL_DRV_DIGI_8821C \ + (BIT_MASK_XTAL_DRV_DIGI_8821C << BIT_SHIFT_XTAL_DRV_DIGI_8821C) +#define BIT_CLEAR_XTAL_DRV_DIGI_8821C(x) ((x) & (~BITS_XTAL_DRV_DIGI_8821C)) +#define BIT_GET_XTAL_DRV_DIGI_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8821C) & BIT_MASK_XTAL_DRV_DIGI_8821C) +#define BIT_SET_XTAL_DRV_DIGI_8821C(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_8821C(x) | BIT_XTAL_DRV_DIGI_8821C(v)) #define BIT_XTAL_DRV_USB_BIT1_8821C BIT(22) #define BIT_SHIFT_MAC_CLK_SEL_8821C 20 #define BIT_MASK_MAC_CLK_SEL_8821C 0x3 -#define BIT_MAC_CLK_SEL_8821C(x) (((x) & BIT_MASK_MAC_CLK_SEL_8821C) << BIT_SHIFT_MAC_CLK_SEL_8821C) -#define BIT_GET_MAC_CLK_SEL_8821C(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8821C) & BIT_MASK_MAC_CLK_SEL_8821C) - +#define BIT_MAC_CLK_SEL_8821C(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL_8821C) << BIT_SHIFT_MAC_CLK_SEL_8821C) +#define BITS_MAC_CLK_SEL_8821C \ + (BIT_MASK_MAC_CLK_SEL_8821C << BIT_SHIFT_MAC_CLK_SEL_8821C) +#define BIT_CLEAR_MAC_CLK_SEL_8821C(x) ((x) & (~BITS_MAC_CLK_SEL_8821C)) +#define BIT_GET_MAC_CLK_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL_8821C) & BIT_MASK_MAC_CLK_SEL_8821C) +#define BIT_SET_MAC_CLK_SEL_8821C(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL_8821C(x) | BIT_MAC_CLK_SEL_8821C(v)) #define BIT_XTAL_DRV_USB_BIT0_8821C BIT(19) #define BIT_SHIFT_XTAL_DRV_AFE_8821C 17 #define BIT_MASK_XTAL_DRV_AFE_8821C 0x3 -#define BIT_XTAL_DRV_AFE_8821C(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8821C) << BIT_SHIFT_XTAL_DRV_AFE_8821C) -#define BIT_GET_XTAL_DRV_AFE_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8821C) & BIT_MASK_XTAL_DRV_AFE_8821C) - - +#define BIT_XTAL_DRV_AFE_8821C(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_8821C) << BIT_SHIFT_XTAL_DRV_AFE_8821C) +#define BITS_XTAL_DRV_AFE_8821C \ + (BIT_MASK_XTAL_DRV_AFE_8821C << BIT_SHIFT_XTAL_DRV_AFE_8821C) +#define BIT_CLEAR_XTAL_DRV_AFE_8821C(x) ((x) & (~BITS_XTAL_DRV_AFE_8821C)) +#define BIT_GET_XTAL_DRV_AFE_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8821C) & BIT_MASK_XTAL_DRV_AFE_8821C) +#define BIT_SET_XTAL_DRV_AFE_8821C(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_8821C(x) | BIT_XTAL_DRV_AFE_8821C(v)) #define BIT_SHIFT_XTAL_DRV_RF2_8821C 15 #define BIT_MASK_XTAL_DRV_RF2_8821C 0x3 -#define BIT_XTAL_DRV_RF2_8821C(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8821C) << BIT_SHIFT_XTAL_DRV_RF2_8821C) -#define BIT_GET_XTAL_DRV_RF2_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8821C) & BIT_MASK_XTAL_DRV_RF2_8821C) - - +#define BIT_XTAL_DRV_RF2_8821C(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_8821C) << BIT_SHIFT_XTAL_DRV_RF2_8821C) +#define BITS_XTAL_DRV_RF2_8821C \ + (BIT_MASK_XTAL_DRV_RF2_8821C << BIT_SHIFT_XTAL_DRV_RF2_8821C) +#define BIT_CLEAR_XTAL_DRV_RF2_8821C(x) ((x) & (~BITS_XTAL_DRV_RF2_8821C)) +#define BIT_GET_XTAL_DRV_RF2_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8821C) & BIT_MASK_XTAL_DRV_RF2_8821C) +#define BIT_SET_XTAL_DRV_RF2_8821C(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_8821C(x) | BIT_XTAL_DRV_RF2_8821C(v)) #define BIT_SHIFT_XTAL_DRV_RF1_8821C 13 #define BIT_MASK_XTAL_DRV_RF1_8821C 0x3 -#define BIT_XTAL_DRV_RF1_8821C(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8821C) << BIT_SHIFT_XTAL_DRV_RF1_8821C) -#define BIT_GET_XTAL_DRV_RF1_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8821C) & BIT_MASK_XTAL_DRV_RF1_8821C) - +#define BIT_XTAL_DRV_RF1_8821C(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF1_8821C) << BIT_SHIFT_XTAL_DRV_RF1_8821C) +#define BITS_XTAL_DRV_RF1_8821C \ + (BIT_MASK_XTAL_DRV_RF1_8821C << BIT_SHIFT_XTAL_DRV_RF1_8821C) +#define BIT_CLEAR_XTAL_DRV_RF1_8821C(x) ((x) & (~BITS_XTAL_DRV_RF1_8821C)) +#define BIT_GET_XTAL_DRV_RF1_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8821C) & BIT_MASK_XTAL_DRV_RF1_8821C) +#define BIT_SET_XTAL_DRV_RF1_8821C(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF1_8821C(x) | BIT_XTAL_DRV_RF1_8821C(v)) #define BIT_XTAL_DELAY_DIGI_8821C BIT(12) #define BIT_XTAL_DELAY_USB_8821C BIT(11) @@ -373,25 +503,42 @@ #define BIT_SHIFT_XTAL_LDO_VREF_8821C 7 #define BIT_MASK_XTAL_LDO_VREF_8821C 0x7 -#define BIT_XTAL_LDO_VREF_8821C(x) (((x) & BIT_MASK_XTAL_LDO_VREF_8821C) << BIT_SHIFT_XTAL_LDO_VREF_8821C) -#define BIT_GET_XTAL_LDO_VREF_8821C(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8821C) & BIT_MASK_XTAL_LDO_VREF_8821C) - +#define BIT_XTAL_LDO_VREF_8821C(x) \ + (((x) & BIT_MASK_XTAL_LDO_VREF_8821C) << BIT_SHIFT_XTAL_LDO_VREF_8821C) +#define BITS_XTAL_LDO_VREF_8821C \ + (BIT_MASK_XTAL_LDO_VREF_8821C << BIT_SHIFT_XTAL_LDO_VREF_8821C) +#define BIT_CLEAR_XTAL_LDO_VREF_8821C(x) ((x) & (~BITS_XTAL_LDO_VREF_8821C)) +#define BIT_GET_XTAL_LDO_VREF_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8821C) & BIT_MASK_XTAL_LDO_VREF_8821C) +#define BIT_SET_XTAL_LDO_VREF_8821C(x, v) \ + (BIT_CLEAR_XTAL_LDO_VREF_8821C(x) | BIT_XTAL_LDO_VREF_8821C(v)) #define BIT_XTAL_XQSEL_RF_8821C BIT(6) #define BIT_XTAL_XQSEL_8821C BIT(5) #define BIT_SHIFT_XTAL_GMN_V2_8821C 3 #define BIT_MASK_XTAL_GMN_V2_8821C 0x3 -#define BIT_XTAL_GMN_V2_8821C(x) (((x) & BIT_MASK_XTAL_GMN_V2_8821C) << BIT_SHIFT_XTAL_GMN_V2_8821C) -#define BIT_GET_XTAL_GMN_V2_8821C(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2_8821C) & BIT_MASK_XTAL_GMN_V2_8821C) - - +#define BIT_XTAL_GMN_V2_8821C(x) \ + (((x) & BIT_MASK_XTAL_GMN_V2_8821C) << BIT_SHIFT_XTAL_GMN_V2_8821C) +#define BITS_XTAL_GMN_V2_8821C \ + (BIT_MASK_XTAL_GMN_V2_8821C << BIT_SHIFT_XTAL_GMN_V2_8821C) +#define BIT_CLEAR_XTAL_GMN_V2_8821C(x) ((x) & (~BITS_XTAL_GMN_V2_8821C)) +#define BIT_GET_XTAL_GMN_V2_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V2_8821C) & BIT_MASK_XTAL_GMN_V2_8821C) +#define BIT_SET_XTAL_GMN_V2_8821C(x, v) \ + (BIT_CLEAR_XTAL_GMN_V2_8821C(x) | BIT_XTAL_GMN_V2_8821C(v)) #define BIT_SHIFT_XTAL_GMP_V2_8821C 1 #define BIT_MASK_XTAL_GMP_V2_8821C 0x3 -#define BIT_XTAL_GMP_V2_8821C(x) (((x) & BIT_MASK_XTAL_GMP_V2_8821C) << BIT_SHIFT_XTAL_GMP_V2_8821C) -#define BIT_GET_XTAL_GMP_V2_8821C(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2_8821C) & BIT_MASK_XTAL_GMP_V2_8821C) - +#define BIT_XTAL_GMP_V2_8821C(x) \ + (((x) & BIT_MASK_XTAL_GMP_V2_8821C) << BIT_SHIFT_XTAL_GMP_V2_8821C) +#define BITS_XTAL_GMP_V2_8821C \ + (BIT_MASK_XTAL_GMP_V2_8821C << BIT_SHIFT_XTAL_GMP_V2_8821C) +#define BIT_CLEAR_XTAL_GMP_V2_8821C(x) ((x) & (~BITS_XTAL_GMP_V2_8821C)) +#define BIT_GET_XTAL_GMP_V2_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V2_8821C) & BIT_MASK_XTAL_GMP_V2_8821C) +#define BIT_SET_XTAL_GMP_V2_8821C(x, v) \ + (BIT_CLEAR_XTAL_GMP_V2_8821C(x) | BIT_XTAL_GMP_V2_8821C(v)) #define BIT_XTAL_EN_8821C BIT(0) @@ -399,38 +546,63 @@ #define BIT_SHIFT_REG_C3_V4_8821C 30 #define BIT_MASK_REG_C3_V4_8821C 0x3 -#define BIT_REG_C3_V4_8821C(x) (((x) & BIT_MASK_REG_C3_V4_8821C) << BIT_SHIFT_REG_C3_V4_8821C) -#define BIT_GET_REG_C3_V4_8821C(x) (((x) >> BIT_SHIFT_REG_C3_V4_8821C) & BIT_MASK_REG_C3_V4_8821C) - +#define BIT_REG_C3_V4_8821C(x) \ + (((x) & BIT_MASK_REG_C3_V4_8821C) << BIT_SHIFT_REG_C3_V4_8821C) +#define BITS_REG_C3_V4_8821C \ + (BIT_MASK_REG_C3_V4_8821C << BIT_SHIFT_REG_C3_V4_8821C) +#define BIT_CLEAR_REG_C3_V4_8821C(x) ((x) & (~BITS_REG_C3_V4_8821C)) +#define BIT_GET_REG_C3_V4_8821C(x) \ + (((x) >> BIT_SHIFT_REG_C3_V4_8821C) & BIT_MASK_REG_C3_V4_8821C) +#define BIT_SET_REG_C3_V4_8821C(x, v) \ + (BIT_CLEAR_REG_C3_V4_8821C(x) | BIT_REG_C3_V4_8821C(v)) #define BIT_REG_CP_BIT1_8821C BIT(29) #define BIT_SHIFT_REG_RS_V4_8821C 26 #define BIT_MASK_REG_RS_V4_8821C 0x7 -#define BIT_REG_RS_V4_8821C(x) (((x) & BIT_MASK_REG_RS_V4_8821C) << BIT_SHIFT_REG_RS_V4_8821C) -#define BIT_GET_REG_RS_V4_8821C(x) (((x) >> BIT_SHIFT_REG_RS_V4_8821C) & BIT_MASK_REG_RS_V4_8821C) - - +#define BIT_REG_RS_V4_8821C(x) \ + (((x) & BIT_MASK_REG_RS_V4_8821C) << BIT_SHIFT_REG_RS_V4_8821C) +#define BITS_REG_RS_V4_8821C \ + (BIT_MASK_REG_RS_V4_8821C << BIT_SHIFT_REG_RS_V4_8821C) +#define BIT_CLEAR_REG_RS_V4_8821C(x) ((x) & (~BITS_REG_RS_V4_8821C)) +#define BIT_GET_REG_RS_V4_8821C(x) \ + (((x) >> BIT_SHIFT_REG_RS_V4_8821C) & BIT_MASK_REG_RS_V4_8821C) +#define BIT_SET_REG_RS_V4_8821C(x, v) \ + (BIT_CLEAR_REG_RS_V4_8821C(x) | BIT_REG_RS_V4_8821C(v)) #define BIT_SHIFT_REG__CS_8821C 24 #define BIT_MASK_REG__CS_8821C 0x3 -#define BIT_REG__CS_8821C(x) (((x) & BIT_MASK_REG__CS_8821C) << BIT_SHIFT_REG__CS_8821C) -#define BIT_GET_REG__CS_8821C(x) (((x) >> BIT_SHIFT_REG__CS_8821C) & BIT_MASK_REG__CS_8821C) - - +#define BIT_REG__CS_8821C(x) \ + (((x) & BIT_MASK_REG__CS_8821C) << BIT_SHIFT_REG__CS_8821C) +#define BITS_REG__CS_8821C (BIT_MASK_REG__CS_8821C << BIT_SHIFT_REG__CS_8821C) +#define BIT_CLEAR_REG__CS_8821C(x) ((x) & (~BITS_REG__CS_8821C)) +#define BIT_GET_REG__CS_8821C(x) \ + (((x) >> BIT_SHIFT_REG__CS_8821C) & BIT_MASK_REG__CS_8821C) +#define BIT_SET_REG__CS_8821C(x, v) \ + (BIT_CLEAR_REG__CS_8821C(x) | BIT_REG__CS_8821C(v)) #define BIT_SHIFT_REG_CP_OFFSET_8821C 21 #define BIT_MASK_REG_CP_OFFSET_8821C 0x7 -#define BIT_REG_CP_OFFSET_8821C(x) (((x) & BIT_MASK_REG_CP_OFFSET_8821C) << BIT_SHIFT_REG_CP_OFFSET_8821C) -#define BIT_GET_REG_CP_OFFSET_8821C(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_8821C) & BIT_MASK_REG_CP_OFFSET_8821C) - - +#define BIT_REG_CP_OFFSET_8821C(x) \ + (((x) & BIT_MASK_REG_CP_OFFSET_8821C) << BIT_SHIFT_REG_CP_OFFSET_8821C) +#define BITS_REG_CP_OFFSET_8821C \ + (BIT_MASK_REG_CP_OFFSET_8821C << BIT_SHIFT_REG_CP_OFFSET_8821C) +#define BIT_CLEAR_REG_CP_OFFSET_8821C(x) ((x) & (~BITS_REG_CP_OFFSET_8821C)) +#define BIT_GET_REG_CP_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_REG_CP_OFFSET_8821C) & BIT_MASK_REG_CP_OFFSET_8821C) +#define BIT_SET_REG_CP_OFFSET_8821C(x, v) \ + (BIT_CLEAR_REG_CP_OFFSET_8821C(x) | BIT_REG_CP_OFFSET_8821C(v)) #define BIT_SHIFT_CP_BIAS_8821C 18 #define BIT_MASK_CP_BIAS_8821C 0x7 -#define BIT_CP_BIAS_8821C(x) (((x) & BIT_MASK_CP_BIAS_8821C) << BIT_SHIFT_CP_BIAS_8821C) -#define BIT_GET_CP_BIAS_8821C(x) (((x) >> BIT_SHIFT_CP_BIAS_8821C) & BIT_MASK_CP_BIAS_8821C) - +#define BIT_CP_BIAS_8821C(x) \ + (((x) & BIT_MASK_CP_BIAS_8821C) << BIT_SHIFT_CP_BIAS_8821C) +#define BITS_CP_BIAS_8821C (BIT_MASK_CP_BIAS_8821C << BIT_SHIFT_CP_BIAS_8821C) +#define BIT_CLEAR_CP_BIAS_8821C(x) ((x) & (~BITS_CP_BIAS_8821C)) +#define BIT_GET_CP_BIAS_8821C(x) \ + (((x) >> BIT_SHIFT_CP_BIAS_8821C) & BIT_MASK_CP_BIAS_8821C) +#define BIT_SET_CP_BIAS_8821C(x, v) \ + (BIT_CLEAR_CP_BIAS_8821C(x) | BIT_CP_BIAS_8821C(v)) #define BIT_REG_IDOUBLE_V2_8821C BIT(17) #define BIT_EN_SYN_8821C BIT(16) @@ -438,31 +610,50 @@ #define BIT_SHIFT_MCCO_8821C 14 #define BIT_MASK_MCCO_8821C 0x3 #define BIT_MCCO_8821C(x) (((x) & BIT_MASK_MCCO_8821C) << BIT_SHIFT_MCCO_8821C) -#define BIT_GET_MCCO_8821C(x) (((x) >> BIT_SHIFT_MCCO_8821C) & BIT_MASK_MCCO_8821C) - - +#define BITS_MCCO_8821C (BIT_MASK_MCCO_8821C << BIT_SHIFT_MCCO_8821C) +#define BIT_CLEAR_MCCO_8821C(x) ((x) & (~BITS_MCCO_8821C)) +#define BIT_GET_MCCO_8821C(x) \ + (((x) >> BIT_SHIFT_MCCO_8821C) & BIT_MASK_MCCO_8821C) +#define BIT_SET_MCCO_8821C(x, v) (BIT_CLEAR_MCCO_8821C(x) | BIT_MCCO_8821C(v)) #define BIT_SHIFT_REG_LDO_SEL_8821C 12 #define BIT_MASK_REG_LDO_SEL_8821C 0x3 -#define BIT_REG_LDO_SEL_8821C(x) (((x) & BIT_MASK_REG_LDO_SEL_8821C) << BIT_SHIFT_REG_LDO_SEL_8821C) -#define BIT_GET_REG_LDO_SEL_8821C(x) (((x) >> BIT_SHIFT_REG_LDO_SEL_8821C) & BIT_MASK_REG_LDO_SEL_8821C) - +#define BIT_REG_LDO_SEL_8821C(x) \ + (((x) & BIT_MASK_REG_LDO_SEL_8821C) << BIT_SHIFT_REG_LDO_SEL_8821C) +#define BITS_REG_LDO_SEL_8821C \ + (BIT_MASK_REG_LDO_SEL_8821C << BIT_SHIFT_REG_LDO_SEL_8821C) +#define BIT_CLEAR_REG_LDO_SEL_8821C(x) ((x) & (~BITS_REG_LDO_SEL_8821C)) +#define BIT_GET_REG_LDO_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_REG_LDO_SEL_8821C) & BIT_MASK_REG_LDO_SEL_8821C) +#define BIT_SET_REG_LDO_SEL_8821C(x, v) \ + (BIT_CLEAR_REG_LDO_SEL_8821C(x) | BIT_REG_LDO_SEL_8821C(v)) #define BIT_REG_KVCO_V2_8821C BIT(10) #define BIT_AGPIO_GPO_8821C BIT(9) #define BIT_SHIFT_AGPIO_DRV_8821C 7 #define BIT_MASK_AGPIO_DRV_8821C 0x3 -#define BIT_AGPIO_DRV_8821C(x) (((x) & BIT_MASK_AGPIO_DRV_8821C) << BIT_SHIFT_AGPIO_DRV_8821C) -#define BIT_GET_AGPIO_DRV_8821C(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8821C) & BIT_MASK_AGPIO_DRV_8821C) - - +#define BIT_AGPIO_DRV_8821C(x) \ + (((x) & BIT_MASK_AGPIO_DRV_8821C) << BIT_SHIFT_AGPIO_DRV_8821C) +#define BITS_AGPIO_DRV_8821C \ + (BIT_MASK_AGPIO_DRV_8821C << BIT_SHIFT_AGPIO_DRV_8821C) +#define BIT_CLEAR_AGPIO_DRV_8821C(x) ((x) & (~BITS_AGPIO_DRV_8821C)) +#define BIT_GET_AGPIO_DRV_8821C(x) \ + (((x) >> BIT_SHIFT_AGPIO_DRV_8821C) & BIT_MASK_AGPIO_DRV_8821C) +#define BIT_SET_AGPIO_DRV_8821C(x, v) \ + (BIT_CLEAR_AGPIO_DRV_8821C(x) | BIT_AGPIO_DRV_8821C(v)) #define BIT_SHIFT_XTAL_CAP_XO_8821C 1 #define BIT_MASK_XTAL_CAP_XO_8821C 0x3f -#define BIT_XTAL_CAP_XO_8821C(x) (((x) & BIT_MASK_XTAL_CAP_XO_8821C) << BIT_SHIFT_XTAL_CAP_XO_8821C) -#define BIT_GET_XTAL_CAP_XO_8821C(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8821C) & BIT_MASK_XTAL_CAP_XO_8821C) - +#define BIT_XTAL_CAP_XO_8821C(x) \ + (((x) & BIT_MASK_XTAL_CAP_XO_8821C) << BIT_SHIFT_XTAL_CAP_XO_8821C) +#define BITS_XTAL_CAP_XO_8821C \ + (BIT_MASK_XTAL_CAP_XO_8821C << BIT_SHIFT_XTAL_CAP_XO_8821C) +#define BIT_CLEAR_XTAL_CAP_XO_8821C(x) ((x) & (~BITS_XTAL_CAP_XO_8821C)) +#define BIT_GET_XTAL_CAP_XO_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XO_8821C) & BIT_MASK_XTAL_CAP_XO_8821C) +#define BIT_SET_XTAL_CAP_XO_8821C(x, v) \ + (BIT_CLEAR_XTAL_CAP_XO_8821C(x) | BIT_XTAL_CAP_XO_8821C(v)) #define BIT_POW_PLL_8821C BIT(0) @@ -471,8 +662,10 @@ #define BIT_SHIFT_PS_8821C 7 #define BIT_MASK_PS_8821C 0x7 #define BIT_PS_8821C(x) (((x) & BIT_MASK_PS_8821C) << BIT_SHIFT_PS_8821C) +#define BITS_PS_8821C (BIT_MASK_PS_8821C << BIT_SHIFT_PS_8821C) +#define BIT_CLEAR_PS_8821C(x) ((x) & (~BITS_PS_8821C)) #define BIT_GET_PS_8821C(x) (((x) >> BIT_SHIFT_PS_8821C) & BIT_MASK_PS_8821C) - +#define BIT_SET_PS_8821C(x, v) (BIT_CLEAR_PS_8821C(x) | BIT_PS_8821C(v)) #define BIT_PSEN_8821C BIT(6) #define BIT_DOGENB_8821C BIT(5) @@ -480,9 +673,15 @@ #define BIT_SHIFT_REG_R3_V4_8821C 1 #define BIT_MASK_REG_R3_V4_8821C 0x7 -#define BIT_REG_R3_V4_8821C(x) (((x) & BIT_MASK_REG_R3_V4_8821C) << BIT_SHIFT_REG_R3_V4_8821C) -#define BIT_GET_REG_R3_V4_8821C(x) (((x) >> BIT_SHIFT_REG_R3_V4_8821C) & BIT_MASK_REG_R3_V4_8821C) - +#define BIT_REG_R3_V4_8821C(x) \ + (((x) & BIT_MASK_REG_R3_V4_8821C) << BIT_SHIFT_REG_R3_V4_8821C) +#define BITS_REG_R3_V4_8821C \ + (BIT_MASK_REG_R3_V4_8821C << BIT_SHIFT_REG_R3_V4_8821C) +#define BIT_CLEAR_REG_R3_V4_8821C(x) ((x) & (~BITS_REG_R3_V4_8821C)) +#define BIT_GET_REG_R3_V4_8821C(x) \ + (((x) >> BIT_SHIFT_REG_R3_V4_8821C) & BIT_MASK_REG_R3_V4_8821C) +#define BIT_SET_REG_R3_V4_8821C(x, v) \ + (BIT_CLEAR_REG_R3_V4_8821C(x) | BIT_REG_R3_V4_8821C(v)) #define BIT_REG_CP_BIT0_8821C BIT(0) @@ -491,103 +690,172 @@ #define BIT_SHIFT_EF_PGPD_8821C 28 #define BIT_MASK_EF_PGPD_8821C 0x7 -#define BIT_EF_PGPD_8821C(x) (((x) & BIT_MASK_EF_PGPD_8821C) << BIT_SHIFT_EF_PGPD_8821C) -#define BIT_GET_EF_PGPD_8821C(x) (((x) >> BIT_SHIFT_EF_PGPD_8821C) & BIT_MASK_EF_PGPD_8821C) - - +#define BIT_EF_PGPD_8821C(x) \ + (((x) & BIT_MASK_EF_PGPD_8821C) << BIT_SHIFT_EF_PGPD_8821C) +#define BITS_EF_PGPD_8821C (BIT_MASK_EF_PGPD_8821C << BIT_SHIFT_EF_PGPD_8821C) +#define BIT_CLEAR_EF_PGPD_8821C(x) ((x) & (~BITS_EF_PGPD_8821C)) +#define BIT_GET_EF_PGPD_8821C(x) \ + (((x) >> BIT_SHIFT_EF_PGPD_8821C) & BIT_MASK_EF_PGPD_8821C) +#define BIT_SET_EF_PGPD_8821C(x, v) \ + (BIT_CLEAR_EF_PGPD_8821C(x) | BIT_EF_PGPD_8821C(v)) #define BIT_SHIFT_EF_RDT_8821C 24 #define BIT_MASK_EF_RDT_8821C 0xf -#define BIT_EF_RDT_8821C(x) (((x) & BIT_MASK_EF_RDT_8821C) << BIT_SHIFT_EF_RDT_8821C) -#define BIT_GET_EF_RDT_8821C(x) (((x) >> BIT_SHIFT_EF_RDT_8821C) & BIT_MASK_EF_RDT_8821C) - - +#define BIT_EF_RDT_8821C(x) \ + (((x) & BIT_MASK_EF_RDT_8821C) << BIT_SHIFT_EF_RDT_8821C) +#define BITS_EF_RDT_8821C (BIT_MASK_EF_RDT_8821C << BIT_SHIFT_EF_RDT_8821C) +#define BIT_CLEAR_EF_RDT_8821C(x) ((x) & (~BITS_EF_RDT_8821C)) +#define BIT_GET_EF_RDT_8821C(x) \ + (((x) >> BIT_SHIFT_EF_RDT_8821C) & BIT_MASK_EF_RDT_8821C) +#define BIT_SET_EF_RDT_8821C(x, v) \ + (BIT_CLEAR_EF_RDT_8821C(x) | BIT_EF_RDT_8821C(v)) #define BIT_SHIFT_EF_PGTS_8821C 20 #define BIT_MASK_EF_PGTS_8821C 0xf -#define BIT_EF_PGTS_8821C(x) (((x) & BIT_MASK_EF_PGTS_8821C) << BIT_SHIFT_EF_PGTS_8821C) -#define BIT_GET_EF_PGTS_8821C(x) (((x) >> BIT_SHIFT_EF_PGTS_8821C) & BIT_MASK_EF_PGTS_8821C) - +#define BIT_EF_PGTS_8821C(x) \ + (((x) & BIT_MASK_EF_PGTS_8821C) << BIT_SHIFT_EF_PGTS_8821C) +#define BITS_EF_PGTS_8821C (BIT_MASK_EF_PGTS_8821C << BIT_SHIFT_EF_PGTS_8821C) +#define BIT_CLEAR_EF_PGTS_8821C(x) ((x) & (~BITS_EF_PGTS_8821C)) +#define BIT_GET_EF_PGTS_8821C(x) \ + (((x) >> BIT_SHIFT_EF_PGTS_8821C) & BIT_MASK_EF_PGTS_8821C) +#define BIT_SET_EF_PGTS_8821C(x, v) \ + (BIT_CLEAR_EF_PGTS_8821C(x) | BIT_EF_PGTS_8821C(v)) #define BIT_EF_PDWN_8821C BIT(19) #define BIT_EF_ALDEN_8821C BIT(18) #define BIT_SHIFT_EF_ADDR_8821C 8 #define BIT_MASK_EF_ADDR_8821C 0x3ff -#define BIT_EF_ADDR_8821C(x) (((x) & BIT_MASK_EF_ADDR_8821C) << BIT_SHIFT_EF_ADDR_8821C) -#define BIT_GET_EF_ADDR_8821C(x) (((x) >> BIT_SHIFT_EF_ADDR_8821C) & BIT_MASK_EF_ADDR_8821C) - - +#define BIT_EF_ADDR_8821C(x) \ + (((x) & BIT_MASK_EF_ADDR_8821C) << BIT_SHIFT_EF_ADDR_8821C) +#define BITS_EF_ADDR_8821C (BIT_MASK_EF_ADDR_8821C << BIT_SHIFT_EF_ADDR_8821C) +#define BIT_CLEAR_EF_ADDR_8821C(x) ((x) & (~BITS_EF_ADDR_8821C)) +#define BIT_GET_EF_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_EF_ADDR_8821C) & BIT_MASK_EF_ADDR_8821C) +#define BIT_SET_EF_ADDR_8821C(x, v) \ + (BIT_CLEAR_EF_ADDR_8821C(x) | BIT_EF_ADDR_8821C(v)) #define BIT_SHIFT_EF_DATA_8821C 0 #define BIT_MASK_EF_DATA_8821C 0xff -#define BIT_EF_DATA_8821C(x) (((x) & BIT_MASK_EF_DATA_8821C) << BIT_SHIFT_EF_DATA_8821C) -#define BIT_GET_EF_DATA_8821C(x) (((x) >> BIT_SHIFT_EF_DATA_8821C) & BIT_MASK_EF_DATA_8821C) - - +#define BIT_EF_DATA_8821C(x) \ + (((x) & BIT_MASK_EF_DATA_8821C) << BIT_SHIFT_EF_DATA_8821C) +#define BITS_EF_DATA_8821C (BIT_MASK_EF_DATA_8821C << BIT_SHIFT_EF_DATA_8821C) +#define BIT_CLEAR_EF_DATA_8821C(x) ((x) & (~BITS_EF_DATA_8821C)) +#define BIT_GET_EF_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_EF_DATA_8821C) & BIT_MASK_EF_DATA_8821C) +#define BIT_SET_EF_DATA_8821C(x, v) \ + (BIT_CLEAR_EF_DATA_8821C(x) | BIT_EF_DATA_8821C(v)) /* 2 REG_LDO_EFUSE_CTRL_8821C */ #define BIT_LDOE25_EN_8821C BIT(31) #define BIT_SHIFT_LDOE25_V12ADJ_L_8821C 27 #define BIT_MASK_LDOE25_V12ADJ_L_8821C 0xf -#define BIT_LDOE25_V12ADJ_L_8821C(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8821C) << BIT_SHIFT_LDOE25_V12ADJ_L_8821C) -#define BIT_GET_LDOE25_V12ADJ_L_8821C(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8821C) & BIT_MASK_LDOE25_V12ADJ_L_8821C) - +#define BIT_LDOE25_V12ADJ_L_8821C(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L_8821C) \ + << BIT_SHIFT_LDOE25_V12ADJ_L_8821C) +#define BITS_LDOE25_V12ADJ_L_8821C \ + (BIT_MASK_LDOE25_V12ADJ_L_8821C << BIT_SHIFT_LDOE25_V12ADJ_L_8821C) +#define BIT_CLEAR_LDOE25_V12ADJ_L_8821C(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8821C)) +#define BIT_GET_LDOE25_V12ADJ_L_8821C(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8821C) & \ + BIT_MASK_LDOE25_V12ADJ_L_8821C) +#define BIT_SET_LDOE25_V12ADJ_L_8821C(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L_8821C(x) | BIT_LDOE25_V12ADJ_L_8821C(v)) #define BIT_EF_CRES_SEL_8821C BIT(26) #define BIT_SHIFT_EF_SCAN_START_V1_8821C 16 #define BIT_MASK_EF_SCAN_START_V1_8821C 0x3ff -#define BIT_EF_SCAN_START_V1_8821C(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8821C) << BIT_SHIFT_EF_SCAN_START_V1_8821C) -#define BIT_GET_EF_SCAN_START_V1_8821C(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8821C) & BIT_MASK_EF_SCAN_START_V1_8821C) - - +#define BIT_EF_SCAN_START_V1_8821C(x) \ + (((x) & BIT_MASK_EF_SCAN_START_V1_8821C) \ + << BIT_SHIFT_EF_SCAN_START_V1_8821C) +#define BITS_EF_SCAN_START_V1_8821C \ + (BIT_MASK_EF_SCAN_START_V1_8821C << BIT_SHIFT_EF_SCAN_START_V1_8821C) +#define BIT_CLEAR_EF_SCAN_START_V1_8821C(x) \ + ((x) & (~BITS_EF_SCAN_START_V1_8821C)) +#define BIT_GET_EF_SCAN_START_V1_8821C(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8821C) & \ + BIT_MASK_EF_SCAN_START_V1_8821C) +#define BIT_SET_EF_SCAN_START_V1_8821C(x, v) \ + (BIT_CLEAR_EF_SCAN_START_V1_8821C(x) | BIT_EF_SCAN_START_V1_8821C(v)) #define BIT_SHIFT_EF_SCAN_END_8821C 12 #define BIT_MASK_EF_SCAN_END_8821C 0xf -#define BIT_EF_SCAN_END_8821C(x) (((x) & BIT_MASK_EF_SCAN_END_8821C) << BIT_SHIFT_EF_SCAN_END_8821C) -#define BIT_GET_EF_SCAN_END_8821C(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8821C) & BIT_MASK_EF_SCAN_END_8821C) - +#define BIT_EF_SCAN_END_8821C(x) \ + (((x) & BIT_MASK_EF_SCAN_END_8821C) << BIT_SHIFT_EF_SCAN_END_8821C) +#define BITS_EF_SCAN_END_8821C \ + (BIT_MASK_EF_SCAN_END_8821C << BIT_SHIFT_EF_SCAN_END_8821C) +#define BIT_CLEAR_EF_SCAN_END_8821C(x) ((x) & (~BITS_EF_SCAN_END_8821C)) +#define BIT_GET_EF_SCAN_END_8821C(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_END_8821C) & BIT_MASK_EF_SCAN_END_8821C) +#define BIT_SET_EF_SCAN_END_8821C(x, v) \ + (BIT_CLEAR_EF_SCAN_END_8821C(x) | BIT_EF_SCAN_END_8821C(v)) #define BIT_EF_PD_DIS_8821C BIT(11) #define BIT_SHIFT_EF_CELL_SEL_8821C 8 #define BIT_MASK_EF_CELL_SEL_8821C 0x3 -#define BIT_EF_CELL_SEL_8821C(x) (((x) & BIT_MASK_EF_CELL_SEL_8821C) << BIT_SHIFT_EF_CELL_SEL_8821C) -#define BIT_GET_EF_CELL_SEL_8821C(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8821C) & BIT_MASK_EF_CELL_SEL_8821C) - +#define BIT_EF_CELL_SEL_8821C(x) \ + (((x) & BIT_MASK_EF_CELL_SEL_8821C) << BIT_SHIFT_EF_CELL_SEL_8821C) +#define BITS_EF_CELL_SEL_8821C \ + (BIT_MASK_EF_CELL_SEL_8821C << BIT_SHIFT_EF_CELL_SEL_8821C) +#define BIT_CLEAR_EF_CELL_SEL_8821C(x) ((x) & (~BITS_EF_CELL_SEL_8821C)) +#define BIT_GET_EF_CELL_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_EF_CELL_SEL_8821C) & BIT_MASK_EF_CELL_SEL_8821C) +#define BIT_SET_EF_CELL_SEL_8821C(x, v) \ + (BIT_CLEAR_EF_CELL_SEL_8821C(x) | BIT_EF_CELL_SEL_8821C(v)) #define BIT_EF_TRPT_8821C BIT(7) #define BIT_SHIFT_EF_TTHD_8821C 0 #define BIT_MASK_EF_TTHD_8821C 0x7f -#define BIT_EF_TTHD_8821C(x) (((x) & BIT_MASK_EF_TTHD_8821C) << BIT_SHIFT_EF_TTHD_8821C) -#define BIT_GET_EF_TTHD_8821C(x) (((x) >> BIT_SHIFT_EF_TTHD_8821C) & BIT_MASK_EF_TTHD_8821C) - - +#define BIT_EF_TTHD_8821C(x) \ + (((x) & BIT_MASK_EF_TTHD_8821C) << BIT_SHIFT_EF_TTHD_8821C) +#define BITS_EF_TTHD_8821C (BIT_MASK_EF_TTHD_8821C << BIT_SHIFT_EF_TTHD_8821C) +#define BIT_CLEAR_EF_TTHD_8821C(x) ((x) & (~BITS_EF_TTHD_8821C)) +#define BIT_GET_EF_TTHD_8821C(x) \ + (((x) >> BIT_SHIFT_EF_TTHD_8821C) & BIT_MASK_EF_TTHD_8821C) +#define BIT_SET_EF_TTHD_8821C(x, v) \ + (BIT_CLEAR_EF_TTHD_8821C(x) | BIT_EF_TTHD_8821C(v)) /* 2 REG_PWR_OPTION_CTRL_8821C */ #define BIT_SHIFT_DBG_SEL_V1_8821C 16 #define BIT_MASK_DBG_SEL_V1_8821C 0xff -#define BIT_DBG_SEL_V1_8821C(x) (((x) & BIT_MASK_DBG_SEL_V1_8821C) << BIT_SHIFT_DBG_SEL_V1_8821C) -#define BIT_GET_DBG_SEL_V1_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8821C) & BIT_MASK_DBG_SEL_V1_8821C) - - +#define BIT_DBG_SEL_V1_8821C(x) \ + (((x) & BIT_MASK_DBG_SEL_V1_8821C) << BIT_SHIFT_DBG_SEL_V1_8821C) +#define BITS_DBG_SEL_V1_8821C \ + (BIT_MASK_DBG_SEL_V1_8821C << BIT_SHIFT_DBG_SEL_V1_8821C) +#define BIT_CLEAR_DBG_SEL_V1_8821C(x) ((x) & (~BITS_DBG_SEL_V1_8821C)) +#define BIT_GET_DBG_SEL_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_V1_8821C) & BIT_MASK_DBG_SEL_V1_8821C) +#define BIT_SET_DBG_SEL_V1_8821C(x, v) \ + (BIT_CLEAR_DBG_SEL_V1_8821C(x) | BIT_DBG_SEL_V1_8821C(v)) #define BIT_SHIFT_DBG_SEL_BYTE_8821C 14 #define BIT_MASK_DBG_SEL_BYTE_8821C 0x3 -#define BIT_DBG_SEL_BYTE_8821C(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8821C) << BIT_SHIFT_DBG_SEL_BYTE_8821C) -#define BIT_GET_DBG_SEL_BYTE_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8821C) & BIT_MASK_DBG_SEL_BYTE_8821C) - - +#define BIT_DBG_SEL_BYTE_8821C(x) \ + (((x) & BIT_MASK_DBG_SEL_BYTE_8821C) << BIT_SHIFT_DBG_SEL_BYTE_8821C) +#define BITS_DBG_SEL_BYTE_8821C \ + (BIT_MASK_DBG_SEL_BYTE_8821C << BIT_SHIFT_DBG_SEL_BYTE_8821C) +#define BIT_CLEAR_DBG_SEL_BYTE_8821C(x) ((x) & (~BITS_DBG_SEL_BYTE_8821C)) +#define BIT_GET_DBG_SEL_BYTE_8821C(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8821C) & BIT_MASK_DBG_SEL_BYTE_8821C) +#define BIT_SET_DBG_SEL_BYTE_8821C(x, v) \ + (BIT_CLEAR_DBG_SEL_BYTE_8821C(x) | BIT_DBG_SEL_BYTE_8821C(v)) #define BIT_SHIFT_STD_L1_V1_8821C 12 #define BIT_MASK_STD_L1_V1_8821C 0x3 -#define BIT_STD_L1_V1_8821C(x) (((x) & BIT_MASK_STD_L1_V1_8821C) << BIT_SHIFT_STD_L1_V1_8821C) -#define BIT_GET_STD_L1_V1_8821C(x) (((x) >> BIT_SHIFT_STD_L1_V1_8821C) & BIT_MASK_STD_L1_V1_8821C) - +#define BIT_STD_L1_V1_8821C(x) \ + (((x) & BIT_MASK_STD_L1_V1_8821C) << BIT_SHIFT_STD_L1_V1_8821C) +#define BITS_STD_L1_V1_8821C \ + (BIT_MASK_STD_L1_V1_8821C << BIT_SHIFT_STD_L1_V1_8821C) +#define BIT_CLEAR_STD_L1_V1_8821C(x) ((x) & (~BITS_STD_L1_V1_8821C)) +#define BIT_GET_STD_L1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_STD_L1_V1_8821C) & BIT_MASK_STD_L1_V1_8821C) +#define BIT_SET_STD_L1_V1_8821C(x, v) \ + (BIT_CLEAR_STD_L1_V1_8821C(x) | BIT_STD_L1_V1_8821C(v)) #define BIT_SYSON_DBG_PAD_E2_8821C BIT(11) #define BIT_SYSON_LED_PAD_E2_8821C BIT(10) @@ -597,56 +865,101 @@ #define BIT_SHIFT_SYSON_SPS0WWV_WT_8821C 4 #define BIT_MASK_SYSON_SPS0WWV_WT_8821C 0x3 -#define BIT_SYSON_SPS0WWV_WT_8821C(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8821C) << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) -#define BIT_GET_SYSON_SPS0WWV_WT_8821C(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) & BIT_MASK_SYSON_SPS0WWV_WT_8821C) - - +#define BIT_SYSON_SPS0WWV_WT_8821C(x) \ + (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8821C) \ + << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) +#define BITS_SYSON_SPS0WWV_WT_8821C \ + (BIT_MASK_SYSON_SPS0WWV_WT_8821C << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) +#define BIT_CLEAR_SYSON_SPS0WWV_WT_8821C(x) \ + ((x) & (~BITS_SYSON_SPS0WWV_WT_8821C)) +#define BIT_GET_SYSON_SPS0WWV_WT_8821C(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) & \ + BIT_MASK_SYSON_SPS0WWV_WT_8821C) +#define BIT_SET_SYSON_SPS0WWV_WT_8821C(x, v) \ + (BIT_CLEAR_SYSON_SPS0WWV_WT_8821C(x) | BIT_SYSON_SPS0WWV_WT_8821C(v)) #define BIT_SHIFT_SYSON_SPS0LDO_WT_8821C 2 #define BIT_MASK_SYSON_SPS0LDO_WT_8821C 0x3 -#define BIT_SYSON_SPS0LDO_WT_8821C(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8821C) << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) -#define BIT_GET_SYSON_SPS0LDO_WT_8821C(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) & BIT_MASK_SYSON_SPS0LDO_WT_8821C) - - +#define BIT_SYSON_SPS0LDO_WT_8821C(x) \ + (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8821C) \ + << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) +#define BITS_SYSON_SPS0LDO_WT_8821C \ + (BIT_MASK_SYSON_SPS0LDO_WT_8821C << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) +#define BIT_CLEAR_SYSON_SPS0LDO_WT_8821C(x) \ + ((x) & (~BITS_SYSON_SPS0LDO_WT_8821C)) +#define BIT_GET_SYSON_SPS0LDO_WT_8821C(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) & \ + BIT_MASK_SYSON_SPS0LDO_WT_8821C) +#define BIT_SET_SYSON_SPS0LDO_WT_8821C(x, v) \ + (BIT_CLEAR_SYSON_SPS0LDO_WT_8821C(x) | BIT_SYSON_SPS0LDO_WT_8821C(v)) #define BIT_SHIFT_SYSON_RCLK_SCALE_8821C 0 #define BIT_MASK_SYSON_RCLK_SCALE_8821C 0x3 -#define BIT_SYSON_RCLK_SCALE_8821C(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8821C) << BIT_SHIFT_SYSON_RCLK_SCALE_8821C) -#define BIT_GET_SYSON_RCLK_SCALE_8821C(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8821C) & BIT_MASK_SYSON_RCLK_SCALE_8821C) - - +#define BIT_SYSON_RCLK_SCALE_8821C(x) \ + (((x) & BIT_MASK_SYSON_RCLK_SCALE_8821C) \ + << BIT_SHIFT_SYSON_RCLK_SCALE_8821C) +#define BITS_SYSON_RCLK_SCALE_8821C \ + (BIT_MASK_SYSON_RCLK_SCALE_8821C << BIT_SHIFT_SYSON_RCLK_SCALE_8821C) +#define BIT_CLEAR_SYSON_RCLK_SCALE_8821C(x) \ + ((x) & (~BITS_SYSON_RCLK_SCALE_8821C)) +#define BIT_GET_SYSON_RCLK_SCALE_8821C(x) \ + (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8821C) & \ + BIT_MASK_SYSON_RCLK_SCALE_8821C) +#define BIT_SET_SYSON_RCLK_SCALE_8821C(x, v) \ + (BIT_CLEAR_SYSON_RCLK_SCALE_8821C(x) | BIT_SYSON_RCLK_SCALE_8821C(v)) /* 2 REG_CAL_TIMER_8821C */ #define BIT_SHIFT_MATCH_CNT_8821C 8 #define BIT_MASK_MATCH_CNT_8821C 0xff -#define BIT_MATCH_CNT_8821C(x) (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C) -#define BIT_GET_MATCH_CNT_8821C(x) (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C) - - +#define BIT_MATCH_CNT_8821C(x) \ + (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C) +#define BITS_MATCH_CNT_8821C \ + (BIT_MASK_MATCH_CNT_8821C << BIT_SHIFT_MATCH_CNT_8821C) +#define BIT_CLEAR_MATCH_CNT_8821C(x) ((x) & (~BITS_MATCH_CNT_8821C)) +#define BIT_GET_MATCH_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C) +#define BIT_SET_MATCH_CNT_8821C(x, v) \ + (BIT_CLEAR_MATCH_CNT_8821C(x) | BIT_MATCH_CNT_8821C(v)) #define BIT_SHIFT_CAL_SCAL_8821C 0 #define BIT_MASK_CAL_SCAL_8821C 0xff -#define BIT_CAL_SCAL_8821C(x) (((x) & BIT_MASK_CAL_SCAL_8821C) << BIT_SHIFT_CAL_SCAL_8821C) -#define BIT_GET_CAL_SCAL_8821C(x) (((x) >> BIT_SHIFT_CAL_SCAL_8821C) & BIT_MASK_CAL_SCAL_8821C) - - +#define BIT_CAL_SCAL_8821C(x) \ + (((x) & BIT_MASK_CAL_SCAL_8821C) << BIT_SHIFT_CAL_SCAL_8821C) +#define BITS_CAL_SCAL_8821C \ + (BIT_MASK_CAL_SCAL_8821C << BIT_SHIFT_CAL_SCAL_8821C) +#define BIT_CLEAR_CAL_SCAL_8821C(x) ((x) & (~BITS_CAL_SCAL_8821C)) +#define BIT_GET_CAL_SCAL_8821C(x) \ + (((x) >> BIT_SHIFT_CAL_SCAL_8821C) & BIT_MASK_CAL_SCAL_8821C) +#define BIT_SET_CAL_SCAL_8821C(x, v) \ + (BIT_CLEAR_CAL_SCAL_8821C(x) | BIT_CAL_SCAL_8821C(v)) /* 2 REG_ACLK_MON_8821C */ #define BIT_SHIFT_RCLK_MON_8821C 5 #define BIT_MASK_RCLK_MON_8821C 0x7ff -#define BIT_RCLK_MON_8821C(x) (((x) & BIT_MASK_RCLK_MON_8821C) << BIT_SHIFT_RCLK_MON_8821C) -#define BIT_GET_RCLK_MON_8821C(x) (((x) >> BIT_SHIFT_RCLK_MON_8821C) & BIT_MASK_RCLK_MON_8821C) - +#define BIT_RCLK_MON_8821C(x) \ + (((x) & BIT_MASK_RCLK_MON_8821C) << BIT_SHIFT_RCLK_MON_8821C) +#define BITS_RCLK_MON_8821C \ + (BIT_MASK_RCLK_MON_8821C << BIT_SHIFT_RCLK_MON_8821C) +#define BIT_CLEAR_RCLK_MON_8821C(x) ((x) & (~BITS_RCLK_MON_8821C)) +#define BIT_GET_RCLK_MON_8821C(x) \ + (((x) >> BIT_SHIFT_RCLK_MON_8821C) & BIT_MASK_RCLK_MON_8821C) +#define BIT_SET_RCLK_MON_8821C(x, v) \ + (BIT_CLEAR_RCLK_MON_8821C(x) | BIT_RCLK_MON_8821C(v)) #define BIT_CAL_EN_8821C BIT(4) #define BIT_SHIFT_DPSTU_8821C 2 #define BIT_MASK_DPSTU_8821C 0x3 -#define BIT_DPSTU_8821C(x) (((x) & BIT_MASK_DPSTU_8821C) << BIT_SHIFT_DPSTU_8821C) -#define BIT_GET_DPSTU_8821C(x) (((x) >> BIT_SHIFT_DPSTU_8821C) & BIT_MASK_DPSTU_8821C) - +#define BIT_DPSTU_8821C(x) \ + (((x) & BIT_MASK_DPSTU_8821C) << BIT_SHIFT_DPSTU_8821C) +#define BITS_DPSTU_8821C (BIT_MASK_DPSTU_8821C << BIT_SHIFT_DPSTU_8821C) +#define BIT_CLEAR_DPSTU_8821C(x) ((x) & (~BITS_DPSTU_8821C)) +#define BIT_GET_DPSTU_8821C(x) \ + (((x) >> BIT_SHIFT_DPSTU_8821C) & BIT_MASK_DPSTU_8821C) +#define BIT_SET_DPSTU_8821C(x, v) \ + (BIT_CLEAR_DPSTU_8821C(x) | BIT_DPSTU_8821C(v)) #define BIT_SUS_16X_8821C BIT(1) @@ -664,9 +977,14 @@ #define BIT_SHIFT_BTMODE_8821C 6 #define BIT_MASK_BTMODE_8821C 0x3 -#define BIT_BTMODE_8821C(x) (((x) & BIT_MASK_BTMODE_8821C) << BIT_SHIFT_BTMODE_8821C) -#define BIT_GET_BTMODE_8821C(x) (((x) >> BIT_SHIFT_BTMODE_8821C) & BIT_MASK_BTMODE_8821C) - +#define BIT_BTMODE_8821C(x) \ + (((x) & BIT_MASK_BTMODE_8821C) << BIT_SHIFT_BTMODE_8821C) +#define BITS_BTMODE_8821C (BIT_MASK_BTMODE_8821C << BIT_SHIFT_BTMODE_8821C) +#define BIT_CLEAR_BTMODE_8821C(x) ((x) & (~BITS_BTMODE_8821C)) +#define BIT_GET_BTMODE_8821C(x) \ + (((x) >> BIT_SHIFT_BTMODE_8821C) & BIT_MASK_BTMODE_8821C) +#define BIT_SET_BTMODE_8821C(x, v) \ + (BIT_CLEAR_BTMODE_8821C(x) | BIT_BTMODE_8821C(v)) #define BIT_ENBT_8821C BIT(5) #define BIT_EROM_EN_8821C BIT(4) @@ -675,48 +993,89 @@ #define BIT_SHIFT_GPIOSEL_8821C 0 #define BIT_MASK_GPIOSEL_8821C 0x3 -#define BIT_GPIOSEL_8821C(x) (((x) & BIT_MASK_GPIOSEL_8821C) << BIT_SHIFT_GPIOSEL_8821C) -#define BIT_GET_GPIOSEL_8821C(x) (((x) >> BIT_SHIFT_GPIOSEL_8821C) & BIT_MASK_GPIOSEL_8821C) - - +#define BIT_GPIOSEL_8821C(x) \ + (((x) & BIT_MASK_GPIOSEL_8821C) << BIT_SHIFT_GPIOSEL_8821C) +#define BITS_GPIOSEL_8821C (BIT_MASK_GPIOSEL_8821C << BIT_SHIFT_GPIOSEL_8821C) +#define BIT_CLEAR_GPIOSEL_8821C(x) ((x) & (~BITS_GPIOSEL_8821C)) +#define BIT_GET_GPIOSEL_8821C(x) \ + (((x) >> BIT_SHIFT_GPIOSEL_8821C) & BIT_MASK_GPIOSEL_8821C) +#define BIT_SET_GPIOSEL_8821C(x, v) \ + (BIT_CLEAR_GPIOSEL_8821C(x) | BIT_GPIOSEL_8821C(v)) /* 2 REG_GPIO_PIN_CTRL_8821C */ #define BIT_SHIFT_GPIO_MOD_7_TO_0_8821C 24 #define BIT_MASK_GPIO_MOD_7_TO_0_8821C 0xff -#define BIT_GPIO_MOD_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8821C) << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) -#define BIT_GET_GPIO_MOD_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) & BIT_MASK_GPIO_MOD_7_TO_0_8821C) - - +#define BIT_GPIO_MOD_7_TO_0_8821C(x) \ + (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8821C) \ + << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) +#define BITS_GPIO_MOD_7_TO_0_8821C \ + (BIT_MASK_GPIO_MOD_7_TO_0_8821C << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) +#define BIT_CLEAR_GPIO_MOD_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8821C)) +#define BIT_GET_GPIO_MOD_7_TO_0_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) & \ + BIT_MASK_GPIO_MOD_7_TO_0_8821C) +#define BIT_SET_GPIO_MOD_7_TO_0_8821C(x, v) \ + (BIT_CLEAR_GPIO_MOD_7_TO_0_8821C(x) | BIT_GPIO_MOD_7_TO_0_8821C(v)) #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C 16 #define BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C 0xff -#define BIT_GPIO_IO_SEL_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) -#define BIT_GET_GPIO_IO_SEL_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) - - +#define BIT_GPIO_IO_SEL_7_TO_0_8821C(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) +#define BITS_GPIO_IO_SEL_7_TO_0_8821C \ + (BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8821C(x) \ + ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8821C)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) & \ + BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) +#define BIT_SET_GPIO_IO_SEL_7_TO_0_8821C(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8821C(x) | \ + BIT_GPIO_IO_SEL_7_TO_0_8821C(v)) #define BIT_SHIFT_GPIO_OUT_7_TO_0_8821C 8 #define BIT_MASK_GPIO_OUT_7_TO_0_8821C 0xff -#define BIT_GPIO_OUT_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8821C) << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) -#define BIT_GET_GPIO_OUT_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) & BIT_MASK_GPIO_OUT_7_TO_0_8821C) - - +#define BIT_GPIO_OUT_7_TO_0_8821C(x) \ + (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8821C) \ + << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) +#define BITS_GPIO_OUT_7_TO_0_8821C \ + (BIT_MASK_GPIO_OUT_7_TO_0_8821C << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) +#define BIT_CLEAR_GPIO_OUT_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8821C)) +#define BIT_GET_GPIO_OUT_7_TO_0_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) & \ + BIT_MASK_GPIO_OUT_7_TO_0_8821C) +#define BIT_SET_GPIO_OUT_7_TO_0_8821C(x, v) \ + (BIT_CLEAR_GPIO_OUT_7_TO_0_8821C(x) | BIT_GPIO_OUT_7_TO_0_8821C(v)) #define BIT_SHIFT_GPIO_IN_7_TO_0_8821C 0 #define BIT_MASK_GPIO_IN_7_TO_0_8821C 0xff -#define BIT_GPIO_IN_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8821C) << BIT_SHIFT_GPIO_IN_7_TO_0_8821C) -#define BIT_GET_GPIO_IN_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8821C) & BIT_MASK_GPIO_IN_7_TO_0_8821C) - - +#define BIT_GPIO_IN_7_TO_0_8821C(x) \ + (((x) & BIT_MASK_GPIO_IN_7_TO_0_8821C) \ + << BIT_SHIFT_GPIO_IN_7_TO_0_8821C) +#define BITS_GPIO_IN_7_TO_0_8821C \ + (BIT_MASK_GPIO_IN_7_TO_0_8821C << BIT_SHIFT_GPIO_IN_7_TO_0_8821C) +#define BIT_CLEAR_GPIO_IN_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8821C)) +#define BIT_GET_GPIO_IN_7_TO_0_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8821C) & \ + BIT_MASK_GPIO_IN_7_TO_0_8821C) +#define BIT_SET_GPIO_IN_7_TO_0_8821C(x, v) \ + (BIT_CLEAR_GPIO_IN_7_TO_0_8821C(x) | BIT_GPIO_IN_7_TO_0_8821C(v)) /* 2 REG_GPIO_INTM_8821C */ #define BIT_SHIFT_MUXDBG_SEL_8821C 30 #define BIT_MASK_MUXDBG_SEL_8821C 0x3 -#define BIT_MUXDBG_SEL_8821C(x) (((x) & BIT_MASK_MUXDBG_SEL_8821C) << BIT_SHIFT_MUXDBG_SEL_8821C) -#define BIT_GET_MUXDBG_SEL_8821C(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8821C) & BIT_MASK_MUXDBG_SEL_8821C) - +#define BIT_MUXDBG_SEL_8821C(x) \ + (((x) & BIT_MASK_MUXDBG_SEL_8821C) << BIT_SHIFT_MUXDBG_SEL_8821C) +#define BITS_MUXDBG_SEL_8821C \ + (BIT_MASK_MUXDBG_SEL_8821C << BIT_SHIFT_MUXDBG_SEL_8821C) +#define BIT_CLEAR_MUXDBG_SEL_8821C(x) ((x) & (~BITS_MUXDBG_SEL_8821C)) +#define BIT_GET_MUXDBG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL_8821C) & BIT_MASK_MUXDBG_SEL_8821C) +#define BIT_SET_MUXDBG_SEL_8821C(x, v) \ + (BIT_CLEAR_MUXDBG_SEL_8821C(x) | BIT_MUXDBG_SEL_8821C(v)) #define BIT_EXTWOL_SEL_8821C BIT(17) #define BIT_EXTWOL_EN_8821C BIT(16) @@ -747,16 +1106,20 @@ #define BIT_DPDT_WLBT_SEL_8821C BIT(24) #define BIT_DPDT_SEL_EN_8821C BIT(23) #define BIT_GPIO13_14_WL_CTRL_EN_8821C BIT(22) -#define BIT_GPIO13_14_WL_CTRL_EN_8821C BIT(22) #define BIT_LED2DIS_8821C BIT(21) #define BIT_LED2PL_8821C BIT(20) #define BIT_LED2SV_8821C BIT(19) #define BIT_SHIFT_LED2CM_8821C 16 #define BIT_MASK_LED2CM_8821C 0x7 -#define BIT_LED2CM_8821C(x) (((x) & BIT_MASK_LED2CM_8821C) << BIT_SHIFT_LED2CM_8821C) -#define BIT_GET_LED2CM_8821C(x) (((x) >> BIT_SHIFT_LED2CM_8821C) & BIT_MASK_LED2CM_8821C) - +#define BIT_LED2CM_8821C(x) \ + (((x) & BIT_MASK_LED2CM_8821C) << BIT_SHIFT_LED2CM_8821C) +#define BITS_LED2CM_8821C (BIT_MASK_LED2CM_8821C << BIT_SHIFT_LED2CM_8821C) +#define BIT_CLEAR_LED2CM_8821C(x) ((x) & (~BITS_LED2CM_8821C)) +#define BIT_GET_LED2CM_8821C(x) \ + (((x) >> BIT_SHIFT_LED2CM_8821C) & BIT_MASK_LED2CM_8821C) +#define BIT_SET_LED2CM_8821C(x, v) \ + (BIT_CLEAR_LED2CM_8821C(x) | BIT_LED2CM_8821C(v)) #define BIT_LED1DIS_8821C BIT(15) #define BIT_LED1PL_8821C BIT(12) @@ -764,27 +1127,45 @@ #define BIT_SHIFT_LED1CM_8821C 8 #define BIT_MASK_LED1CM_8821C 0x7 -#define BIT_LED1CM_8821C(x) (((x) & BIT_MASK_LED1CM_8821C) << BIT_SHIFT_LED1CM_8821C) -#define BIT_GET_LED1CM_8821C(x) (((x) >> BIT_SHIFT_LED1CM_8821C) & BIT_MASK_LED1CM_8821C) - +#define BIT_LED1CM_8821C(x) \ + (((x) & BIT_MASK_LED1CM_8821C) << BIT_SHIFT_LED1CM_8821C) +#define BITS_LED1CM_8821C (BIT_MASK_LED1CM_8821C << BIT_SHIFT_LED1CM_8821C) +#define BIT_CLEAR_LED1CM_8821C(x) ((x) & (~BITS_LED1CM_8821C)) +#define BIT_GET_LED1CM_8821C(x) \ + (((x) >> BIT_SHIFT_LED1CM_8821C) & BIT_MASK_LED1CM_8821C) +#define BIT_SET_LED1CM_8821C(x, v) \ + (BIT_CLEAR_LED1CM_8821C(x) | BIT_LED1CM_8821C(v)) #define BIT_LED0DIS_8821C BIT(7) #define BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C 5 #define BIT_MASK_AFE_LDO_SWR_CHECK_8821C 0x3 -#define BIT_AFE_LDO_SWR_CHECK_8821C(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) -#define BIT_GET_AFE_LDO_SWR_CHECK_8821C(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C) - +#define BIT_AFE_LDO_SWR_CHECK_8821C(x) \ + (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C) \ + << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) +#define BITS_AFE_LDO_SWR_CHECK_8821C \ + (BIT_MASK_AFE_LDO_SWR_CHECK_8821C << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8821C(x) \ + ((x) & (~BITS_AFE_LDO_SWR_CHECK_8821C)) +#define BIT_GET_AFE_LDO_SWR_CHECK_8821C(x) \ + (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) & \ + BIT_MASK_AFE_LDO_SWR_CHECK_8821C) +#define BIT_SET_AFE_LDO_SWR_CHECK_8821C(x, v) \ + (BIT_CLEAR_AFE_LDO_SWR_CHECK_8821C(x) | BIT_AFE_LDO_SWR_CHECK_8821C(v)) #define BIT_LED0PL_8821C BIT(4) #define BIT_LED0SV_8821C BIT(3) #define BIT_SHIFT_LED0CM_8821C 0 #define BIT_MASK_LED0CM_8821C 0x7 -#define BIT_LED0CM_8821C(x) (((x) & BIT_MASK_LED0CM_8821C) << BIT_SHIFT_LED0CM_8821C) -#define BIT_GET_LED0CM_8821C(x) (((x) >> BIT_SHIFT_LED0CM_8821C) & BIT_MASK_LED0CM_8821C) - - +#define BIT_LED0CM_8821C(x) \ + (((x) & BIT_MASK_LED0CM_8821C) << BIT_SHIFT_LED0CM_8821C) +#define BITS_LED0CM_8821C (BIT_MASK_LED0CM_8821C << BIT_SHIFT_LED0CM_8821C) +#define BIT_CLEAR_LED0CM_8821C(x) ((x) & (~BITS_LED0CM_8821C)) +#define BIT_GET_LED0CM_8821C(x) \ + (((x) >> BIT_SHIFT_LED0CM_8821C) & BIT_MASK_LED0CM_8821C) +#define BIT_SET_LED0CM_8821C(x, v) \ + (BIT_CLEAR_LED0CM_8821C(x) | BIT_LED0CM_8821C(v)) /* 2 REG_FSIMR_8821C */ #define BIT_FS_PDNINT_EN_8821C BIT(31) @@ -866,7 +1247,7 @@ #define BIT_GPIO5_INT_EN_8821C BIT(21) #define BIT_GPIO4_INT_EN_8821C BIT(20) #define BIT_GPIO3_INT_EN_8821C BIT(19) -#define BIT_GPIO2_INT_EN_V1_8821C BIT(16) +#define BIT_GPIO2_INT_EN_V1_8821C BIT(18) #define BIT_GPIO1_INT_EN_8821C BIT(17) #define BIT_GPIO0_INT_EN_8821C BIT(16) #define BIT_PDNINT_EN_8821C BIT(7) @@ -888,7 +1269,7 @@ #define BIT_GPIO5_INT_8821C BIT(21) #define BIT_GPIO4_INT_8821C BIT(20) #define BIT_GPIO3_INT_8821C BIT(19) -#define BIT_GPIO2_INT_V1_8821C BIT(16) +#define BIT_GPIO2_INT_V1_8821C BIT(18) #define BIT_GPIO1_INT_8821C BIT(17) #define BIT_GPIO0_INT_8821C BIT(16) #define BIT_PDNINT_8821C BIT(7) @@ -900,31 +1281,64 @@ #define BIT_SHIFT_GPIO_MOD_15_TO_8_8821C 24 #define BIT_MASK_GPIO_MOD_15_TO_8_8821C 0xff -#define BIT_GPIO_MOD_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8821C) << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) -#define BIT_GET_GPIO_MOD_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) & BIT_MASK_GPIO_MOD_15_TO_8_8821C) - - +#define BIT_GPIO_MOD_15_TO_8_8821C(x) \ + (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8821C) \ + << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) +#define BITS_GPIO_MOD_15_TO_8_8821C \ + (BIT_MASK_GPIO_MOD_15_TO_8_8821C << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) +#define BIT_CLEAR_GPIO_MOD_15_TO_8_8821C(x) \ + ((x) & (~BITS_GPIO_MOD_15_TO_8_8821C)) +#define BIT_GET_GPIO_MOD_15_TO_8_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) & \ + BIT_MASK_GPIO_MOD_15_TO_8_8821C) +#define BIT_SET_GPIO_MOD_15_TO_8_8821C(x, v) \ + (BIT_CLEAR_GPIO_MOD_15_TO_8_8821C(x) | BIT_GPIO_MOD_15_TO_8_8821C(v)) #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C 16 #define BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C 0xff -#define BIT_GPIO_IO_SEL_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) -#define BIT_GET_GPIO_IO_SEL_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) - - +#define BIT_GPIO_IO_SEL_15_TO_8_8821C(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) +#define BITS_GPIO_IO_SEL_15_TO_8_8821C \ + (BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8821C(x) \ + ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8821C)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) & \ + BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) +#define BIT_SET_GPIO_IO_SEL_15_TO_8_8821C(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8821C(x) | \ + BIT_GPIO_IO_SEL_15_TO_8_8821C(v)) #define BIT_SHIFT_GPIO_OUT_15_TO_8_8821C 8 #define BIT_MASK_GPIO_OUT_15_TO_8_8821C 0xff -#define BIT_GPIO_OUT_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8821C) << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) -#define BIT_GET_GPIO_OUT_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) & BIT_MASK_GPIO_OUT_15_TO_8_8821C) - - +#define BIT_GPIO_OUT_15_TO_8_8821C(x) \ + (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8821C) \ + << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) +#define BITS_GPIO_OUT_15_TO_8_8821C \ + (BIT_MASK_GPIO_OUT_15_TO_8_8821C << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) +#define BIT_CLEAR_GPIO_OUT_15_TO_8_8821C(x) \ + ((x) & (~BITS_GPIO_OUT_15_TO_8_8821C)) +#define BIT_GET_GPIO_OUT_15_TO_8_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) & \ + BIT_MASK_GPIO_OUT_15_TO_8_8821C) +#define BIT_SET_GPIO_OUT_15_TO_8_8821C(x, v) \ + (BIT_CLEAR_GPIO_OUT_15_TO_8_8821C(x) | BIT_GPIO_OUT_15_TO_8_8821C(v)) #define BIT_SHIFT_GPIO_IN_15_TO_8_8821C 0 #define BIT_MASK_GPIO_IN_15_TO_8_8821C 0xff -#define BIT_GPIO_IN_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8821C) << BIT_SHIFT_GPIO_IN_15_TO_8_8821C) -#define BIT_GET_GPIO_IN_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8821C) & BIT_MASK_GPIO_IN_15_TO_8_8821C) - - +#define BIT_GPIO_IN_15_TO_8_8821C(x) \ + (((x) & BIT_MASK_GPIO_IN_15_TO_8_8821C) \ + << BIT_SHIFT_GPIO_IN_15_TO_8_8821C) +#define BITS_GPIO_IN_15_TO_8_8821C \ + (BIT_MASK_GPIO_IN_15_TO_8_8821C << BIT_SHIFT_GPIO_IN_15_TO_8_8821C) +#define BIT_CLEAR_GPIO_IN_15_TO_8_8821C(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8821C)) +#define BIT_GET_GPIO_IN_15_TO_8_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8821C) & \ + BIT_MASK_GPIO_IN_15_TO_8_8821C) +#define BIT_SET_GPIO_IN_15_TO_8_8821C(x, v) \ + (BIT_CLEAR_GPIO_IN_15_TO_8_8821C(x) | BIT_GPIO_IN_15_TO_8_8821C(v)) /* 2 REG_PAD_CTRL1_8821C */ #define BIT_PAPE_WLBT_SEL_8821C BIT(29) @@ -941,9 +1355,15 @@ #define BIT_SHIFT_BTGP_GPIO_SL_8821C 16 #define BIT_MASK_BTGP_GPIO_SL_8821C 0x3 -#define BIT_BTGP_GPIO_SL_8821C(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8821C) << BIT_SHIFT_BTGP_GPIO_SL_8821C) -#define BIT_GET_BTGP_GPIO_SL_8821C(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8821C) & BIT_MASK_BTGP_GPIO_SL_8821C) - +#define BIT_BTGP_GPIO_SL_8821C(x) \ + (((x) & BIT_MASK_BTGP_GPIO_SL_8821C) << BIT_SHIFT_BTGP_GPIO_SL_8821C) +#define BITS_BTGP_GPIO_SL_8821C \ + (BIT_MASK_BTGP_GPIO_SL_8821C << BIT_SHIFT_BTGP_GPIO_SL_8821C) +#define BIT_CLEAR_BTGP_GPIO_SL_8821C(x) ((x) & (~BITS_BTGP_GPIO_SL_8821C)) +#define BIT_GET_BTGP_GPIO_SL_8821C(x) \ + (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8821C) & BIT_MASK_BTGP_GPIO_SL_8821C) +#define BIT_SET_BTGP_GPIO_SL_8821C(x, v) \ + (BIT_CLEAR_BTGP_GPIO_SL_8821C(x) | BIT_BTGP_GPIO_SL_8821C(v)) #define BIT_PAD_SDIO_SR_8821C BIT(14) #define BIT_GPIO14_OUTPUT_PL_8821C BIT(13) @@ -994,10 +1414,15 @@ #define BIT_SHIFT_WLCLK_PHASE_8821C 0 #define BIT_MASK_WLCLK_PHASE_8821C 0x1f -#define BIT_WLCLK_PHASE_8821C(x) (((x) & BIT_MASK_WLCLK_PHASE_8821C) << BIT_SHIFT_WLCLK_PHASE_8821C) -#define BIT_GET_WLCLK_PHASE_8821C(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8821C) & BIT_MASK_WLCLK_PHASE_8821C) - - +#define BIT_WLCLK_PHASE_8821C(x) \ + (((x) & BIT_MASK_WLCLK_PHASE_8821C) << BIT_SHIFT_WLCLK_PHASE_8821C) +#define BITS_WLCLK_PHASE_8821C \ + (BIT_MASK_WLCLK_PHASE_8821C << BIT_SHIFT_WLCLK_PHASE_8821C) +#define BIT_CLEAR_WLCLK_PHASE_8821C(x) ((x) & (~BITS_WLCLK_PHASE_8821C)) +#define BIT_GET_WLCLK_PHASE_8821C(x) \ + (((x) >> BIT_SHIFT_WLCLK_PHASE_8821C) & BIT_MASK_WLCLK_PHASE_8821C) +#define BIT_SET_WLCLK_PHASE_8821C(x, v) \ + (BIT_CLEAR_WLCLK_PHASE_8821C(x) | BIT_WLCLK_PHASE_8821C(v)) /* 2 REG_SYS_SDIO_CTRL_8821C */ #define BIT_DBG_GNT_WL_BT_8821C BIT(27) @@ -1018,10 +1443,17 @@ #define BIT_SHIFT_TSFT_SEL_8821C 29 #define BIT_MASK_TSFT_SEL_8821C 0x7 -#define BIT_TSFT_SEL_8821C(x) (((x) & BIT_MASK_TSFT_SEL_8821C) << BIT_SHIFT_TSFT_SEL_8821C) -#define BIT_GET_TSFT_SEL_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_8821C) & BIT_MASK_TSFT_SEL_8821C) - - +#define BIT_TSFT_SEL_8821C(x) \ + (((x) & BIT_MASK_TSFT_SEL_8821C) << BIT_SHIFT_TSFT_SEL_8821C) +#define BITS_TSFT_SEL_8821C \ + (BIT_MASK_TSFT_SEL_8821C << BIT_SHIFT_TSFT_SEL_8821C) +#define BIT_CLEAR_TSFT_SEL_8821C(x) ((x) & (~BITS_TSFT_SEL_8821C)) +#define BIT_GET_TSFT_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_8821C) & BIT_MASK_TSFT_SEL_8821C) +#define BIT_SET_TSFT_SEL_8821C(x, v) \ + (BIT_CLEAR_TSFT_SEL_8821C(x) | BIT_TSFT_SEL_8821C(v)) + +#define BIT_SDIO_PAD_E5_8821C BIT(18) #define BIT_USB_HOST_PWR_OFF_EN_8821C BIT(12) #define BIT_SYM_LPS_BLOCK_EN_8821C BIT(11) #define BIT_USB_LPM_ACT_EN_8821C BIT(10) @@ -1030,9 +1462,15 @@ #define BIT_SHIFT_SDIO_PAD_E_8821C 5 #define BIT_MASK_SDIO_PAD_E_8821C 0x7 -#define BIT_SDIO_PAD_E_8821C(x) (((x) & BIT_MASK_SDIO_PAD_E_8821C) << BIT_SHIFT_SDIO_PAD_E_8821C) -#define BIT_GET_SDIO_PAD_E_8821C(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8821C) & BIT_MASK_SDIO_PAD_E_8821C) - +#define BIT_SDIO_PAD_E_8821C(x) \ + (((x) & BIT_MASK_SDIO_PAD_E_8821C) << BIT_SHIFT_SDIO_PAD_E_8821C) +#define BITS_SDIO_PAD_E_8821C \ + (BIT_MASK_SDIO_PAD_E_8821C << BIT_SHIFT_SDIO_PAD_E_8821C) +#define BIT_CLEAR_SDIO_PAD_E_8821C(x) ((x) & (~BITS_SDIO_PAD_E_8821C)) +#define BIT_GET_SDIO_PAD_E_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_PAD_E_8821C) & BIT_MASK_SDIO_PAD_E_8821C) +#define BIT_SET_SDIO_PAD_E_8821C(x, v) \ + (BIT_CLEAR_SDIO_PAD_E_8821C(x) | BIT_SDIO_PAD_E_8821C(v)) #define BIT_USB_LPPLL_EN_8821C BIT(4) #define BIT_ROP_SW15_8821C BIT(2) @@ -1047,44 +1485,93 @@ #define BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C 21 #define BIT_MASK_AUTO_ZCD_IN_CODE_8821C 0x1f -#define BIT_AUTO_ZCD_IN_CODE_8821C(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C) << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) -#define BIT_GET_AUTO_ZCD_IN_CODE_8821C(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C) - - +#define BIT_AUTO_ZCD_IN_CODE_8821C(x) \ + (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C) \ + << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) +#define BITS_AUTO_ZCD_IN_CODE_8821C \ + (BIT_MASK_AUTO_ZCD_IN_CODE_8821C << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) +#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8821C(x) \ + ((x) & (~BITS_AUTO_ZCD_IN_CODE_8821C)) +#define BIT_GET_AUTO_ZCD_IN_CODE_8821C(x) \ + (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) & \ + BIT_MASK_AUTO_ZCD_IN_CODE_8821C) +#define BIT_SET_AUTO_ZCD_IN_CODE_8821C(x, v) \ + (BIT_CLEAR_AUTO_ZCD_IN_CODE_8821C(x) | BIT_AUTO_ZCD_IN_CODE_8821C(v)) #define BIT_SHIFT_ZCD_CODE_IN_L_8821C 16 #define BIT_MASK_ZCD_CODE_IN_L_8821C 0x1f -#define BIT_ZCD_CODE_IN_L_8821C(x) (((x) & BIT_MASK_ZCD_CODE_IN_L_8821C) << BIT_SHIFT_ZCD_CODE_IN_L_8821C) -#define BIT_GET_ZCD_CODE_IN_L_8821C(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8821C) & BIT_MASK_ZCD_CODE_IN_L_8821C) - - +#define BIT_ZCD_CODE_IN_L_8821C(x) \ + (((x) & BIT_MASK_ZCD_CODE_IN_L_8821C) << BIT_SHIFT_ZCD_CODE_IN_L_8821C) +#define BITS_ZCD_CODE_IN_L_8821C \ + (BIT_MASK_ZCD_CODE_IN_L_8821C << BIT_SHIFT_ZCD_CODE_IN_L_8821C) +#define BIT_CLEAR_ZCD_CODE_IN_L_8821C(x) ((x) & (~BITS_ZCD_CODE_IN_L_8821C)) +#define BIT_GET_ZCD_CODE_IN_L_8821C(x) \ + (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8821C) & BIT_MASK_ZCD_CODE_IN_L_8821C) +#define BIT_SET_ZCD_CODE_IN_L_8821C(x, v) \ + (BIT_CLEAR_ZCD_CODE_IN_L_8821C(x) | BIT_ZCD_CODE_IN_L_8821C(v)) #define BIT_SHIFT_LDO_HV5_DUMMY_8821C 14 #define BIT_MASK_LDO_HV5_DUMMY_8821C 0x3 -#define BIT_LDO_HV5_DUMMY_8821C(x) (((x) & BIT_MASK_LDO_HV5_DUMMY_8821C) << BIT_SHIFT_LDO_HV5_DUMMY_8821C) -#define BIT_GET_LDO_HV5_DUMMY_8821C(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8821C) & BIT_MASK_LDO_HV5_DUMMY_8821C) - - +#define BIT_LDO_HV5_DUMMY_8821C(x) \ + (((x) & BIT_MASK_LDO_HV5_DUMMY_8821C) << BIT_SHIFT_LDO_HV5_DUMMY_8821C) +#define BITS_LDO_HV5_DUMMY_8821C \ + (BIT_MASK_LDO_HV5_DUMMY_8821C << BIT_SHIFT_LDO_HV5_DUMMY_8821C) +#define BIT_CLEAR_LDO_HV5_DUMMY_8821C(x) ((x) & (~BITS_LDO_HV5_DUMMY_8821C)) +#define BIT_GET_LDO_HV5_DUMMY_8821C(x) \ + (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8821C) & BIT_MASK_LDO_HV5_DUMMY_8821C) +#define BIT_SET_LDO_HV5_DUMMY_8821C(x, v) \ + (BIT_CLEAR_LDO_HV5_DUMMY_8821C(x) | BIT_LDO_HV5_DUMMY_8821C(v)) #define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C 12 #define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C 0x3 -#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) -#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) - - +#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) \ + (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) \ + << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) +#define BITS_REG_VTUNE33_BIT0_TO_BIT1_8821C \ + (BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C \ + << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) +#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) \ + ((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1_8821C)) +#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) \ + (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) & \ + BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) +#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x, v) \ + (BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) | \ + BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(v)) #define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C 10 #define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C 0x3 -#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) -#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) - - +#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) \ + (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) \ + << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) +#define BITS_REG_STANDBY33_BIT0_TO_BIT1_8821C \ + (BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C \ + << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) +#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) \ + ((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1_8821C)) +#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) \ + (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) & \ + BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) +#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x, v) \ + (BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) | \ + BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(v)) #define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C 8 #define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C 0x3 -#define BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) -#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) - +#define BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(x) \ + (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) \ + << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) +#define BITS_REG_LOAD33_BIT0_TO_BIT1_8821C \ + (BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C \ + << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) +#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8821C(x) \ + ((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1_8821C)) +#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8821C(x) \ + (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) & \ + BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) +#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1_8821C(x, v) \ + (BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8821C(x) | \ + BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(v)) #define BIT_REG_BYPASS_L_8821C BIT(7) #define BIT_REG_LDOF_L_8821C BIT(6) @@ -1093,9 +1580,14 @@ #define BIT_SHIFT_CFC_L_8821C 1 #define BIT_MASK_CFC_L_8821C 0x3 -#define BIT_CFC_L_8821C(x) (((x) & BIT_MASK_CFC_L_8821C) << BIT_SHIFT_CFC_L_8821C) -#define BIT_GET_CFC_L_8821C(x) (((x) >> BIT_SHIFT_CFC_L_8821C) & BIT_MASK_CFC_L_8821C) - +#define BIT_CFC_L_8821C(x) \ + (((x) & BIT_MASK_CFC_L_8821C) << BIT_SHIFT_CFC_L_8821C) +#define BITS_CFC_L_8821C (BIT_MASK_CFC_L_8821C << BIT_SHIFT_CFC_L_8821C) +#define BIT_CLEAR_CFC_L_8821C(x) ((x) & (~BITS_CFC_L_8821C)) +#define BIT_GET_CFC_L_8821C(x) \ + (((x) >> BIT_SHIFT_CFC_L_8821C) & BIT_MASK_CFC_L_8821C) +#define BIT_SET_CFC_L_8821C(x, v) \ + (BIT_CLEAR_CFC_L_8821C(x) | BIT_CFC_L_8821C(v)) #define BIT_REG_TYPE_L_8821C BIT(0) @@ -1104,8 +1596,11 @@ #define BIT_SHIFT_RPWM_8821C 24 #define BIT_MASK_RPWM_8821C 0xff #define BIT_RPWM_8821C(x) (((x) & BIT_MASK_RPWM_8821C) << BIT_SHIFT_RPWM_8821C) -#define BIT_GET_RPWM_8821C(x) (((x) >> BIT_SHIFT_RPWM_8821C) & BIT_MASK_RPWM_8821C) - +#define BITS_RPWM_8821C (BIT_MASK_RPWM_8821C << BIT_SHIFT_RPWM_8821C) +#define BIT_CLEAR_RPWM_8821C(x) ((x) & (~BITS_RPWM_8821C)) +#define BIT_GET_RPWM_8821C(x) \ + (((x) >> BIT_SHIFT_RPWM_8821C) & BIT_MASK_RPWM_8821C) +#define BIT_SET_RPWM_8821C(x, v) (BIT_CLEAR_RPWM_8821C(x) | BIT_RPWM_8821C(v)) #define BIT_ANA_PORT_EN_8821C BIT(22) #define BIT_MAC_PORT_EN_8821C BIT(21) @@ -1114,18 +1609,29 @@ #define BIT_SHIFT_ROM_PGE_8821C 16 #define BIT_MASK_ROM_PGE_8821C 0x7 -#define BIT_ROM_PGE_8821C(x) (((x) & BIT_MASK_ROM_PGE_8821C) << BIT_SHIFT_ROM_PGE_8821C) -#define BIT_GET_ROM_PGE_8821C(x) (((x) >> BIT_SHIFT_ROM_PGE_8821C) & BIT_MASK_ROM_PGE_8821C) - +#define BIT_ROM_PGE_8821C(x) \ + (((x) & BIT_MASK_ROM_PGE_8821C) << BIT_SHIFT_ROM_PGE_8821C) +#define BITS_ROM_PGE_8821C (BIT_MASK_ROM_PGE_8821C << BIT_SHIFT_ROM_PGE_8821C) +#define BIT_CLEAR_ROM_PGE_8821C(x) ((x) & (~BITS_ROM_PGE_8821C)) +#define BIT_GET_ROM_PGE_8821C(x) \ + (((x) >> BIT_SHIFT_ROM_PGE_8821C) & BIT_MASK_ROM_PGE_8821C) +#define BIT_SET_ROM_PGE_8821C(x, v) \ + (BIT_CLEAR_ROM_PGE_8821C(x) | BIT_ROM_PGE_8821C(v)) #define BIT_FW_INIT_RDY_8821C BIT(15) #define BIT_FW_DW_RDY_8821C BIT(14) #define BIT_SHIFT_CPU_CLK_SEL_8821C 12 #define BIT_MASK_CPU_CLK_SEL_8821C 0x3 -#define BIT_CPU_CLK_SEL_8821C(x) (((x) & BIT_MASK_CPU_CLK_SEL_8821C) << BIT_SHIFT_CPU_CLK_SEL_8821C) -#define BIT_GET_CPU_CLK_SEL_8821C(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8821C) & BIT_MASK_CPU_CLK_SEL_8821C) - +#define BIT_CPU_CLK_SEL_8821C(x) \ + (((x) & BIT_MASK_CPU_CLK_SEL_8821C) << BIT_SHIFT_CPU_CLK_SEL_8821C) +#define BITS_CPU_CLK_SEL_8821C \ + (BIT_MASK_CPU_CLK_SEL_8821C << BIT_SHIFT_CPU_CLK_SEL_8821C) +#define BIT_CLEAR_CPU_CLK_SEL_8821C(x) ((x) & (~BITS_CPU_CLK_SEL_8821C)) +#define BIT_GET_CPU_CLK_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_CPU_CLK_SEL_8821C) & BIT_MASK_CPU_CLK_SEL_8821C) +#define BIT_SET_CPU_CLK_SEL_8821C(x, v) \ + (BIT_CLEAR_CPU_CLK_SEL_8821C(x) | BIT_CPU_CLK_SEL_8821C(v)) #define BIT_CCLK_CHG_MASK_8821C BIT(11) #define BIT_EMEM__TXBUF_CHKSUM_OK_8821C BIT(10) @@ -1142,44 +1648,68 @@ /* 2 REG_MCU_TST_CFG_8821C */ -#define BIT_SHIFT_LBKTST_8821C 0 -#define BIT_MASK_LBKTST_8821C 0xffff -#define BIT_LBKTST_8821C(x) (((x) & BIT_MASK_LBKTST_8821C) << BIT_SHIFT_LBKTST_8821C) -#define BIT_GET_LBKTST_8821C(x) (((x) >> BIT_SHIFT_LBKTST_8821C) & BIT_MASK_LBKTST_8821C) - - +#define BIT_SHIFT_C2H_MSG_8821C 0 +#define BIT_MASK_C2H_MSG_8821C 0xffff +#define BIT_C2H_MSG_8821C(x) \ + (((x) & BIT_MASK_C2H_MSG_8821C) << BIT_SHIFT_C2H_MSG_8821C) +#define BITS_C2H_MSG_8821C (BIT_MASK_C2H_MSG_8821C << BIT_SHIFT_C2H_MSG_8821C) +#define BIT_CLEAR_C2H_MSG_8821C(x) ((x) & (~BITS_C2H_MSG_8821C)) +#define BIT_GET_C2H_MSG_8821C(x) \ + (((x) >> BIT_SHIFT_C2H_MSG_8821C) & BIT_MASK_C2H_MSG_8821C) +#define BIT_SET_C2H_MSG_8821C(x, v) \ + (BIT_CLEAR_C2H_MSG_8821C(x) | BIT_C2H_MSG_8821C(v)) /* 2 REG_HMEBOX_E0_E1_8821C */ #define BIT_SHIFT_HOST_MSG_E1_8821C 16 #define BIT_MASK_HOST_MSG_E1_8821C 0xffff -#define BIT_HOST_MSG_E1_8821C(x) (((x) & BIT_MASK_HOST_MSG_E1_8821C) << BIT_SHIFT_HOST_MSG_E1_8821C) -#define BIT_GET_HOST_MSG_E1_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8821C) & BIT_MASK_HOST_MSG_E1_8821C) - - +#define BIT_HOST_MSG_E1_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_E1_8821C) << BIT_SHIFT_HOST_MSG_E1_8821C) +#define BITS_HOST_MSG_E1_8821C \ + (BIT_MASK_HOST_MSG_E1_8821C << BIT_SHIFT_HOST_MSG_E1_8821C) +#define BIT_CLEAR_HOST_MSG_E1_8821C(x) ((x) & (~BITS_HOST_MSG_E1_8821C)) +#define BIT_GET_HOST_MSG_E1_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E1_8821C) & BIT_MASK_HOST_MSG_E1_8821C) +#define BIT_SET_HOST_MSG_E1_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_E1_8821C(x) | BIT_HOST_MSG_E1_8821C(v)) #define BIT_SHIFT_HOST_MSG_E0_8821C 0 #define BIT_MASK_HOST_MSG_E0_8821C 0xffff -#define BIT_HOST_MSG_E0_8821C(x) (((x) & BIT_MASK_HOST_MSG_E0_8821C) << BIT_SHIFT_HOST_MSG_E0_8821C) -#define BIT_GET_HOST_MSG_E0_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8821C) & BIT_MASK_HOST_MSG_E0_8821C) - - +#define BIT_HOST_MSG_E0_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_E0_8821C) << BIT_SHIFT_HOST_MSG_E0_8821C) +#define BITS_HOST_MSG_E0_8821C \ + (BIT_MASK_HOST_MSG_E0_8821C << BIT_SHIFT_HOST_MSG_E0_8821C) +#define BIT_CLEAR_HOST_MSG_E0_8821C(x) ((x) & (~BITS_HOST_MSG_E0_8821C)) +#define BIT_GET_HOST_MSG_E0_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E0_8821C) & BIT_MASK_HOST_MSG_E0_8821C) +#define BIT_SET_HOST_MSG_E0_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_E0_8821C(x) | BIT_HOST_MSG_E0_8821C(v)) /* 2 REG_HMEBOX_E2_E3_8821C */ #define BIT_SHIFT_HOST_MSG_E3_8821C 16 #define BIT_MASK_HOST_MSG_E3_8821C 0xffff -#define BIT_HOST_MSG_E3_8821C(x) (((x) & BIT_MASK_HOST_MSG_E3_8821C) << BIT_SHIFT_HOST_MSG_E3_8821C) -#define BIT_GET_HOST_MSG_E3_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8821C) & BIT_MASK_HOST_MSG_E3_8821C) - - +#define BIT_HOST_MSG_E3_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_E3_8821C) << BIT_SHIFT_HOST_MSG_E3_8821C) +#define BITS_HOST_MSG_E3_8821C \ + (BIT_MASK_HOST_MSG_E3_8821C << BIT_SHIFT_HOST_MSG_E3_8821C) +#define BIT_CLEAR_HOST_MSG_E3_8821C(x) ((x) & (~BITS_HOST_MSG_E3_8821C)) +#define BIT_GET_HOST_MSG_E3_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E3_8821C) & BIT_MASK_HOST_MSG_E3_8821C) +#define BIT_SET_HOST_MSG_E3_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_E3_8821C(x) | BIT_HOST_MSG_E3_8821C(v)) #define BIT_SHIFT_HOST_MSG_E2_8821C 0 #define BIT_MASK_HOST_MSG_E2_8821C 0xffff -#define BIT_HOST_MSG_E2_8821C(x) (((x) & BIT_MASK_HOST_MSG_E2_8821C) << BIT_SHIFT_HOST_MSG_E2_8821C) -#define BIT_GET_HOST_MSG_E2_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8821C) & BIT_MASK_HOST_MSG_E2_8821C) - - +#define BIT_HOST_MSG_E2_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_E2_8821C) << BIT_SHIFT_HOST_MSG_E2_8821C) +#define BITS_HOST_MSG_E2_8821C \ + (BIT_MASK_HOST_MSG_E2_8821C << BIT_SHIFT_HOST_MSG_E2_8821C) +#define BIT_CLEAR_HOST_MSG_E2_8821C(x) ((x) & (~BITS_HOST_MSG_E2_8821C)) +#define BIT_GET_HOST_MSG_E2_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E2_8821C) & BIT_MASK_HOST_MSG_E2_8821C) +#define BIT_SET_HOST_MSG_E2_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_E2_8821C(x) | BIT_HOST_MSG_E2_8821C(v)) /* 2 REG_WLLPS_CTRL_8821C */ #define BIT_WLLPSOP_EABM_8821C BIT(31) @@ -1196,16 +1726,35 @@ #define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C 12 #define BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C 0xf -#define BIT_LPLDH12_VADJ_STEP_DN_8821C(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) -#define BIT_GET_LPLDH12_VADJ_STEP_DN_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) - - +#define BIT_LPLDH12_VADJ_STEP_DN_8821C(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) +#define BITS_LPLDH12_VADJ_STEP_DN_8821C \ + (BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) +#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8821C(x) \ + ((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8821C)) +#define BIT_GET_LPLDH12_VADJ_STEP_DN_8821C(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) & \ + BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) +#define BIT_SET_LPLDH12_VADJ_STEP_DN_8821C(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8821C(x) | \ + BIT_LPLDH12_VADJ_STEP_DN_8821C(v)) #define BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C 8 #define BIT_MASK_V15ADJ_L1_STEP_DN_8821C 0x7 -#define BIT_V15ADJ_L1_STEP_DN_8821C(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C) << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) -#define BIT_GET_V15ADJ_L1_STEP_DN_8821C(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C) - +#define BIT_V15ADJ_L1_STEP_DN_8821C(x) \ + (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C) \ + << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) +#define BITS_V15ADJ_L1_STEP_DN_8821C \ + (BIT_MASK_V15ADJ_L1_STEP_DN_8821C << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) +#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8821C(x) \ + ((x) & (~BITS_V15ADJ_L1_STEP_DN_8821C)) +#define BIT_GET_V15ADJ_L1_STEP_DN_8821C(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) & \ + BIT_MASK_V15ADJ_L1_STEP_DN_8821C) +#define BIT_SET_V15ADJ_L1_STEP_DN_8821C(x, v) \ + (BIT_CLEAR_V15ADJ_L1_STEP_DN_8821C(x) | BIT_V15ADJ_L1_STEP_DN_8821C(v)) #define BIT_REGU_32K_CLK_EN_8821C BIT(1) #define BIT_WL_LPS_EN_8821C BIT(0) @@ -1217,119 +1766,198 @@ #define BIT_SHIFT_REF_SEL_8821C 25 #define BIT_MASK_REF_SEL_8821C 0xf -#define BIT_REF_SEL_8821C(x) (((x) & BIT_MASK_REF_SEL_8821C) << BIT_SHIFT_REF_SEL_8821C) -#define BIT_GET_REF_SEL_8821C(x) (((x) >> BIT_SHIFT_REF_SEL_8821C) & BIT_MASK_REF_SEL_8821C) - - +#define BIT_REF_SEL_8821C(x) \ + (((x) & BIT_MASK_REF_SEL_8821C) << BIT_SHIFT_REF_SEL_8821C) +#define BITS_REF_SEL_8821C (BIT_MASK_REF_SEL_8821C << BIT_SHIFT_REF_SEL_8821C) +#define BIT_CLEAR_REF_SEL_8821C(x) ((x) & (~BITS_REF_SEL_8821C)) +#define BIT_GET_REF_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_REF_SEL_8821C) & BIT_MASK_REF_SEL_8821C) +#define BIT_SET_REF_SEL_8821C(x, v) \ + (BIT_CLEAR_REF_SEL_8821C(x) | BIT_REF_SEL_8821C(v)) #define BIT_SHIFT_F0F_SDM_8821C 12 #define BIT_MASK_F0F_SDM_8821C 0x1fff -#define BIT_F0F_SDM_8821C(x) (((x) & BIT_MASK_F0F_SDM_8821C) << BIT_SHIFT_F0F_SDM_8821C) -#define BIT_GET_F0F_SDM_8821C(x) (((x) >> BIT_SHIFT_F0F_SDM_8821C) & BIT_MASK_F0F_SDM_8821C) - - +#define BIT_F0F_SDM_8821C(x) \ + (((x) & BIT_MASK_F0F_SDM_8821C) << BIT_SHIFT_F0F_SDM_8821C) +#define BITS_F0F_SDM_8821C (BIT_MASK_F0F_SDM_8821C << BIT_SHIFT_F0F_SDM_8821C) +#define BIT_CLEAR_F0F_SDM_8821C(x) ((x) & (~BITS_F0F_SDM_8821C)) +#define BIT_GET_F0F_SDM_8821C(x) \ + (((x) >> BIT_SHIFT_F0F_SDM_8821C) & BIT_MASK_F0F_SDM_8821C) +#define BIT_SET_F0F_SDM_8821C(x, v) \ + (BIT_CLEAR_F0F_SDM_8821C(x) | BIT_F0F_SDM_8821C(v)) #define BIT_SHIFT_F0N_SDM_8821C 9 #define BIT_MASK_F0N_SDM_8821C 0x7 -#define BIT_F0N_SDM_8821C(x) (((x) & BIT_MASK_F0N_SDM_8821C) << BIT_SHIFT_F0N_SDM_8821C) -#define BIT_GET_F0N_SDM_8821C(x) (((x) >> BIT_SHIFT_F0N_SDM_8821C) & BIT_MASK_F0N_SDM_8821C) - - +#define BIT_F0N_SDM_8821C(x) \ + (((x) & BIT_MASK_F0N_SDM_8821C) << BIT_SHIFT_F0N_SDM_8821C) +#define BITS_F0N_SDM_8821C (BIT_MASK_F0N_SDM_8821C << BIT_SHIFT_F0N_SDM_8821C) +#define BIT_CLEAR_F0N_SDM_8821C(x) ((x) & (~BITS_F0N_SDM_8821C)) +#define BIT_GET_F0N_SDM_8821C(x) \ + (((x) >> BIT_SHIFT_F0N_SDM_8821C) & BIT_MASK_F0N_SDM_8821C) +#define BIT_SET_F0N_SDM_8821C(x, v) \ + (BIT_CLEAR_F0N_SDM_8821C(x) | BIT_F0N_SDM_8821C(v)) #define BIT_SHIFT_DIVN_SDM_8821C 3 #define BIT_MASK_DIVN_SDM_8821C 0x3f -#define BIT_DIVN_SDM_8821C(x) (((x) & BIT_MASK_DIVN_SDM_8821C) << BIT_SHIFT_DIVN_SDM_8821C) -#define BIT_GET_DIVN_SDM_8821C(x) (((x) >> BIT_SHIFT_DIVN_SDM_8821C) & BIT_MASK_DIVN_SDM_8821C) - - +#define BIT_DIVN_SDM_8821C(x) \ + (((x) & BIT_MASK_DIVN_SDM_8821C) << BIT_SHIFT_DIVN_SDM_8821C) +#define BITS_DIVN_SDM_8821C \ + (BIT_MASK_DIVN_SDM_8821C << BIT_SHIFT_DIVN_SDM_8821C) +#define BIT_CLEAR_DIVN_SDM_8821C(x) ((x) & (~BITS_DIVN_SDM_8821C)) +#define BIT_GET_DIVN_SDM_8821C(x) \ + (((x) >> BIT_SHIFT_DIVN_SDM_8821C) & BIT_MASK_DIVN_SDM_8821C) +#define BIT_SET_DIVN_SDM_8821C(x, v) \ + (BIT_CLEAR_DIVN_SDM_8821C(x) | BIT_DIVN_SDM_8821C(v)) /* 2 REG_GPIO_DEBOUNCE_CTRL_8821C */ #define BIT_WLGP_DBC1EN_8821C BIT(15) #define BIT_SHIFT_WLGP_DBC1_8821C 8 #define BIT_MASK_WLGP_DBC1_8821C 0xf -#define BIT_WLGP_DBC1_8821C(x) (((x) & BIT_MASK_WLGP_DBC1_8821C) << BIT_SHIFT_WLGP_DBC1_8821C) -#define BIT_GET_WLGP_DBC1_8821C(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8821C) & BIT_MASK_WLGP_DBC1_8821C) - +#define BIT_WLGP_DBC1_8821C(x) \ + (((x) & BIT_MASK_WLGP_DBC1_8821C) << BIT_SHIFT_WLGP_DBC1_8821C) +#define BITS_WLGP_DBC1_8821C \ + (BIT_MASK_WLGP_DBC1_8821C << BIT_SHIFT_WLGP_DBC1_8821C) +#define BIT_CLEAR_WLGP_DBC1_8821C(x) ((x) & (~BITS_WLGP_DBC1_8821C)) +#define BIT_GET_WLGP_DBC1_8821C(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC1_8821C) & BIT_MASK_WLGP_DBC1_8821C) +#define BIT_SET_WLGP_DBC1_8821C(x, v) \ + (BIT_CLEAR_WLGP_DBC1_8821C(x) | BIT_WLGP_DBC1_8821C(v)) #define BIT_WLGP_DBC0EN_8821C BIT(7) #define BIT_SHIFT_WLGP_DBC0_8821C 0 #define BIT_MASK_WLGP_DBC0_8821C 0xf -#define BIT_WLGP_DBC0_8821C(x) (((x) & BIT_MASK_WLGP_DBC0_8821C) << BIT_SHIFT_WLGP_DBC0_8821C) -#define BIT_GET_WLGP_DBC0_8821C(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8821C) & BIT_MASK_WLGP_DBC0_8821C) - - +#define BIT_WLGP_DBC0_8821C(x) \ + (((x) & BIT_MASK_WLGP_DBC0_8821C) << BIT_SHIFT_WLGP_DBC0_8821C) +#define BITS_WLGP_DBC0_8821C \ + (BIT_MASK_WLGP_DBC0_8821C << BIT_SHIFT_WLGP_DBC0_8821C) +#define BIT_CLEAR_WLGP_DBC0_8821C(x) ((x) & (~BITS_WLGP_DBC0_8821C)) +#define BIT_GET_WLGP_DBC0_8821C(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC0_8821C) & BIT_MASK_WLGP_DBC0_8821C) +#define BIT_SET_WLGP_DBC0_8821C(x, v) \ + (BIT_CLEAR_WLGP_DBC0_8821C(x) | BIT_WLGP_DBC0_8821C(v)) /* 2 REG_RPWM2_8821C */ #define BIT_SHIFT_RPWM2_8821C 16 #define BIT_MASK_RPWM2_8821C 0xffff -#define BIT_RPWM2_8821C(x) (((x) & BIT_MASK_RPWM2_8821C) << BIT_SHIFT_RPWM2_8821C) -#define BIT_GET_RPWM2_8821C(x) (((x) >> BIT_SHIFT_RPWM2_8821C) & BIT_MASK_RPWM2_8821C) - - +#define BIT_RPWM2_8821C(x) \ + (((x) & BIT_MASK_RPWM2_8821C) << BIT_SHIFT_RPWM2_8821C) +#define BITS_RPWM2_8821C (BIT_MASK_RPWM2_8821C << BIT_SHIFT_RPWM2_8821C) +#define BIT_CLEAR_RPWM2_8821C(x) ((x) & (~BITS_RPWM2_8821C)) +#define BIT_GET_RPWM2_8821C(x) \ + (((x) >> BIT_SHIFT_RPWM2_8821C) & BIT_MASK_RPWM2_8821C) +#define BIT_SET_RPWM2_8821C(x, v) \ + (BIT_CLEAR_RPWM2_8821C(x) | BIT_RPWM2_8821C(v)) /* 2 REG_SYSON_FSM_MON_8821C */ #define BIT_SHIFT_FSM_MON_SEL_8821C 24 #define BIT_MASK_FSM_MON_SEL_8821C 0x7 -#define BIT_FSM_MON_SEL_8821C(x) (((x) & BIT_MASK_FSM_MON_SEL_8821C) << BIT_SHIFT_FSM_MON_SEL_8821C) -#define BIT_GET_FSM_MON_SEL_8821C(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8821C) & BIT_MASK_FSM_MON_SEL_8821C) - +#define BIT_FSM_MON_SEL_8821C(x) \ + (((x) & BIT_MASK_FSM_MON_SEL_8821C) << BIT_SHIFT_FSM_MON_SEL_8821C) +#define BITS_FSM_MON_SEL_8821C \ + (BIT_MASK_FSM_MON_SEL_8821C << BIT_SHIFT_FSM_MON_SEL_8821C) +#define BIT_CLEAR_FSM_MON_SEL_8821C(x) ((x) & (~BITS_FSM_MON_SEL_8821C)) +#define BIT_GET_FSM_MON_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_FSM_MON_SEL_8821C) & BIT_MASK_FSM_MON_SEL_8821C) +#define BIT_SET_FSM_MON_SEL_8821C(x, v) \ + (BIT_CLEAR_FSM_MON_SEL_8821C(x) | BIT_FSM_MON_SEL_8821C(v)) #define BIT_DOP_ELDO_8821C BIT(23) #define BIT_FSM_MON_UPD_8821C BIT(15) #define BIT_SHIFT_FSM_PAR_8821C 0 #define BIT_MASK_FSM_PAR_8821C 0x7fff -#define BIT_FSM_PAR_8821C(x) (((x) & BIT_MASK_FSM_PAR_8821C) << BIT_SHIFT_FSM_PAR_8821C) -#define BIT_GET_FSM_PAR_8821C(x) (((x) >> BIT_SHIFT_FSM_PAR_8821C) & BIT_MASK_FSM_PAR_8821C) - - +#define BIT_FSM_PAR_8821C(x) \ + (((x) & BIT_MASK_FSM_PAR_8821C) << BIT_SHIFT_FSM_PAR_8821C) +#define BITS_FSM_PAR_8821C (BIT_MASK_FSM_PAR_8821C << BIT_SHIFT_FSM_PAR_8821C) +#define BIT_CLEAR_FSM_PAR_8821C(x) ((x) & (~BITS_FSM_PAR_8821C)) +#define BIT_GET_FSM_PAR_8821C(x) \ + (((x) >> BIT_SHIFT_FSM_PAR_8821C) & BIT_MASK_FSM_PAR_8821C) +#define BIT_SET_FSM_PAR_8821C(x, v) \ + (BIT_CLEAR_FSM_PAR_8821C(x) | BIT_FSM_PAR_8821C(v)) /* 2 REG_AFE_CTRL6_8821C */ #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0 #define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0x7 -#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) - - +#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) +#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) \ + ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) & \ + BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) | \ + BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(v)) /* 2 REG_PMC_DBG_CTRL1_8821C */ #define BIT_BT_INT_EN_8821C BIT(31) #define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C 16 #define BIT_MASK_RD_WR_WIFI_BT_INFO_8821C 0x7fff -#define BIT_RD_WR_WIFI_BT_INFO_8821C(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) -#define BIT_GET_RD_WR_WIFI_BT_INFO_8821C(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) - +#define BIT_RD_WR_WIFI_BT_INFO_8821C(x) \ + (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) +#define BITS_RD_WR_WIFI_BT_INFO_8821C \ + (BIT_MASK_RD_WR_WIFI_BT_INFO_8821C \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8821C(x) \ + ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8821C)) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) & \ + BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) +#define BIT_SET_RD_WR_WIFI_BT_INFO_8821C(x, v) \ + (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8821C(x) | \ + BIT_RD_WR_WIFI_BT_INFO_8821C(v)) #define BIT_PMC_WR_OVF_8821C BIT(8) #define BIT_SHIFT_WLPMC_ERRINT_8821C 0 #define BIT_MASK_WLPMC_ERRINT_8821C 0xff -#define BIT_WLPMC_ERRINT_8821C(x) (((x) & BIT_MASK_WLPMC_ERRINT_8821C) << BIT_SHIFT_WLPMC_ERRINT_8821C) -#define BIT_GET_WLPMC_ERRINT_8821C(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8821C) & BIT_MASK_WLPMC_ERRINT_8821C) - - +#define BIT_WLPMC_ERRINT_8821C(x) \ + (((x) & BIT_MASK_WLPMC_ERRINT_8821C) << BIT_SHIFT_WLPMC_ERRINT_8821C) +#define BITS_WLPMC_ERRINT_8821C \ + (BIT_MASK_WLPMC_ERRINT_8821C << BIT_SHIFT_WLPMC_ERRINT_8821C) +#define BIT_CLEAR_WLPMC_ERRINT_8821C(x) ((x) & (~BITS_WLPMC_ERRINT_8821C)) +#define BIT_GET_WLPMC_ERRINT_8821C(x) \ + (((x) >> BIT_SHIFT_WLPMC_ERRINT_8821C) & BIT_MASK_WLPMC_ERRINT_8821C) +#define BIT_SET_WLPMC_ERRINT_8821C(x, v) \ + (BIT_CLEAR_WLPMC_ERRINT_8821C(x) | BIT_WLPMC_ERRINT_8821C(v)) /* 2 REG_AFE_CTRL7_8821C */ #define BIT_SHIFT_SEL_V_8821C 30 #define BIT_MASK_SEL_V_8821C 0x3 -#define BIT_SEL_V_8821C(x) (((x) & BIT_MASK_SEL_V_8821C) << BIT_SHIFT_SEL_V_8821C) -#define BIT_GET_SEL_V_8821C(x) (((x) >> BIT_SHIFT_SEL_V_8821C) & BIT_MASK_SEL_V_8821C) - +#define BIT_SEL_V_8821C(x) \ + (((x) & BIT_MASK_SEL_V_8821C) << BIT_SHIFT_SEL_V_8821C) +#define BITS_SEL_V_8821C (BIT_MASK_SEL_V_8821C << BIT_SHIFT_SEL_V_8821C) +#define BIT_CLEAR_SEL_V_8821C(x) ((x) & (~BITS_SEL_V_8821C)) +#define BIT_GET_SEL_V_8821C(x) \ + (((x) >> BIT_SHIFT_SEL_V_8821C) & BIT_MASK_SEL_V_8821C) +#define BIT_SET_SEL_V_8821C(x, v) \ + (BIT_CLEAR_SEL_V_8821C(x) | BIT_SEL_V_8821C(v)) #define BIT_SEL_LDO_PC_8821C BIT(29) #define BIT_SHIFT_CK_MON_SEL_8821C 26 #define BIT_MASK_CK_MON_SEL_8821C 0x7 -#define BIT_CK_MON_SEL_8821C(x) (((x) & BIT_MASK_CK_MON_SEL_8821C) << BIT_SHIFT_CK_MON_SEL_8821C) -#define BIT_GET_CK_MON_SEL_8821C(x) (((x) >> BIT_SHIFT_CK_MON_SEL_8821C) & BIT_MASK_CK_MON_SEL_8821C) - +#define BIT_CK_MON_SEL_8821C(x) \ + (((x) & BIT_MASK_CK_MON_SEL_8821C) << BIT_SHIFT_CK_MON_SEL_8821C) +#define BITS_CK_MON_SEL_8821C \ + (BIT_MASK_CK_MON_SEL_8821C << BIT_SHIFT_CK_MON_SEL_8821C) +#define BIT_CLEAR_CK_MON_SEL_8821C(x) ((x) & (~BITS_CK_MON_SEL_8821C)) +#define BIT_GET_CK_MON_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL_8821C) & BIT_MASK_CK_MON_SEL_8821C) +#define BIT_SET_CK_MON_SEL_8821C(x, v) \ + (BIT_CLEAR_CK_MON_SEL_8821C(x) | BIT_CK_MON_SEL_8821C(v)) #define BIT_CK_MON_EN_8821C BIT(25) #define BIT_FREF_EDGE_8821C BIT(24) @@ -1365,8 +1993,8 @@ #define BIT_RXOK_MSK_8821C BIT(0) /* 2 REG_HISR0_8821C */ -#define BIT_TIMEOUT_INTERRUPT2_8821C BIT(31) -#define BIT_TIMEOUT_INTERRUTP1_8821C BIT(30) +#define BIT_PSTIMEOUT2_8821C BIT(31) +#define BIT_PSTIMEOUT1_8821C BIT(30) #define BIT_PSTIMEOUT_8821C BIT(29) #define BIT_GTINT4_8821C BIT(28) #define BIT_GTINT3_8821C BIT(27) @@ -1457,28 +2085,48 @@ #define BIT_SHIFT_DEBUG_ST_8821C 0 #define BIT_MASK_DEBUG_ST_8821C 0xffffffffL -#define BIT_DEBUG_ST_8821C(x) (((x) & BIT_MASK_DEBUG_ST_8821C) << BIT_SHIFT_DEBUG_ST_8821C) -#define BIT_GET_DEBUG_ST_8821C(x) (((x) >> BIT_SHIFT_DEBUG_ST_8821C) & BIT_MASK_DEBUG_ST_8821C) - - +#define BIT_DEBUG_ST_8821C(x) \ + (((x) & BIT_MASK_DEBUG_ST_8821C) << BIT_SHIFT_DEBUG_ST_8821C) +#define BITS_DEBUG_ST_8821C \ + (BIT_MASK_DEBUG_ST_8821C << BIT_SHIFT_DEBUG_ST_8821C) +#define BIT_CLEAR_DEBUG_ST_8821C(x) ((x) & (~BITS_DEBUG_ST_8821C)) +#define BIT_GET_DEBUG_ST_8821C(x) \ + (((x) >> BIT_SHIFT_DEBUG_ST_8821C) & BIT_MASK_DEBUG_ST_8821C) +#define BIT_SET_DEBUG_ST_8821C(x, v) \ + (BIT_CLEAR_DEBUG_ST_8821C(x) | BIT_DEBUG_ST_8821C(v)) /* 2 REG_PAD_CTRL2_8821C */ #define BIT_USB3_USB2_TRANSITION_8821C BIT(20) #define BIT_SHIFT_USB23_SW_MODE_V1_8821C 18 #define BIT_MASK_USB23_SW_MODE_V1_8821C 0x3 -#define BIT_USB23_SW_MODE_V1_8821C(x) (((x) & BIT_MASK_USB23_SW_MODE_V1_8821C) << BIT_SHIFT_USB23_SW_MODE_V1_8821C) -#define BIT_GET_USB23_SW_MODE_V1_8821C(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8821C) & BIT_MASK_USB23_SW_MODE_V1_8821C) - +#define BIT_USB23_SW_MODE_V1_8821C(x) \ + (((x) & BIT_MASK_USB23_SW_MODE_V1_8821C) \ + << BIT_SHIFT_USB23_SW_MODE_V1_8821C) +#define BITS_USB23_SW_MODE_V1_8821C \ + (BIT_MASK_USB23_SW_MODE_V1_8821C << BIT_SHIFT_USB23_SW_MODE_V1_8821C) +#define BIT_CLEAR_USB23_SW_MODE_V1_8821C(x) \ + ((x) & (~BITS_USB23_SW_MODE_V1_8821C)) +#define BIT_GET_USB23_SW_MODE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8821C) & \ + BIT_MASK_USB23_SW_MODE_V1_8821C) +#define BIT_SET_USB23_SW_MODE_V1_8821C(x, v) \ + (BIT_CLEAR_USB23_SW_MODE_V1_8821C(x) | BIT_USB23_SW_MODE_V1_8821C(v)) #define BIT_NO_PDN_CHIPOFF_V1_8821C BIT(17) #define BIT_RSM_EN_V1_8821C BIT(16) #define BIT_SHIFT_MATCH_CNT_8821C 8 #define BIT_MASK_MATCH_CNT_8821C 0xff -#define BIT_MATCH_CNT_8821C(x) (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C) -#define BIT_GET_MATCH_CNT_8821C(x) (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C) - +#define BIT_MATCH_CNT_8821C(x) \ + (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C) +#define BITS_MATCH_CNT_8821C \ + (BIT_MASK_MATCH_CNT_8821C << BIT_SHIFT_MATCH_CNT_8821C) +#define BIT_CLEAR_MATCH_CNT_8821C(x) ((x) & (~BITS_MATCH_CNT_8821C)) +#define BIT_GET_MATCH_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C) +#define BIT_SET_MATCH_CNT_8821C(x, v) \ + (BIT_CLEAR_MATCH_CNT_8821C(x) | BIT_MATCH_CNT_8821C(v)) #define BIT_LD_B12V_EN_8821C BIT(7) #define BIT_EECS_IOSEL_V1_8821C BIT(6) @@ -1494,9 +2142,17 @@ #define BIT_SHIFT_EFUSE_BURN_GNT_8821C 24 #define BIT_MASK_EFUSE_BURN_GNT_8821C 0xff -#define BIT_EFUSE_BURN_GNT_8821C(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8821C) << BIT_SHIFT_EFUSE_BURN_GNT_8821C) -#define BIT_GET_EFUSE_BURN_GNT_8821C(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8821C) & BIT_MASK_EFUSE_BURN_GNT_8821C) - +#define BIT_EFUSE_BURN_GNT_8821C(x) \ + (((x) & BIT_MASK_EFUSE_BURN_GNT_8821C) \ + << BIT_SHIFT_EFUSE_BURN_GNT_8821C) +#define BITS_EFUSE_BURN_GNT_8821C \ + (BIT_MASK_EFUSE_BURN_GNT_8821C << BIT_SHIFT_EFUSE_BURN_GNT_8821C) +#define BIT_CLEAR_EFUSE_BURN_GNT_8821C(x) ((x) & (~BITS_EFUSE_BURN_GNT_8821C)) +#define BIT_GET_EFUSE_BURN_GNT_8821C(x) \ + (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8821C) & \ + BIT_MASK_EFUSE_BURN_GNT_8821C) +#define BIT_SET_EFUSE_BURN_GNT_8821C(x, v) \ + (BIT_CLEAR_EFUSE_BURN_GNT_8821C(x) | BIT_EFUSE_BURN_GNT_8821C(v)) #define BIT_STOP_WL_PMC_8821C BIT(9) #define BIT_STOP_SYM_PMC_8821C BIT(8) @@ -1508,10 +2164,15 @@ #define BIT_SHIFT_SYSON_REG_ARB_8821C 0 #define BIT_MASK_SYSON_REG_ARB_8821C 0x3 -#define BIT_SYSON_REG_ARB_8821C(x) (((x) & BIT_MASK_SYSON_REG_ARB_8821C) << BIT_SHIFT_SYSON_REG_ARB_8821C) -#define BIT_GET_SYSON_REG_ARB_8821C(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8821C) & BIT_MASK_SYSON_REG_ARB_8821C) - - +#define BIT_SYSON_REG_ARB_8821C(x) \ + (((x) & BIT_MASK_SYSON_REG_ARB_8821C) << BIT_SHIFT_SYSON_REG_ARB_8821C) +#define BITS_SYSON_REG_ARB_8821C \ + (BIT_MASK_SYSON_REG_ARB_8821C << BIT_SHIFT_SYSON_REG_ARB_8821C) +#define BIT_CLEAR_SYSON_REG_ARB_8821C(x) ((x) & (~BITS_SYSON_REG_ARB_8821C)) +#define BIT_GET_SYSON_REG_ARB_8821C(x) \ + (((x) >> BIT_SHIFT_SYSON_REG_ARB_8821C) & BIT_MASK_SYSON_REG_ARB_8821C) +#define BIT_SET_SYSON_REG_ARB_8821C(x, v) \ + (BIT_CLEAR_SYSON_REG_ARB_8821C(x) | BIT_SYSON_REG_ARB_8821C(v)) /* 2 REG_BIST_CTRL_8821C */ #define BIT_BIST_USB_DIS_8821C BIT(27) @@ -1521,9 +2182,15 @@ #define BIT_SHIFT_BIST_RPT_SEL_8821C 16 #define BIT_MASK_BIST_RPT_SEL_8821C 0xf -#define BIT_BIST_RPT_SEL_8821C(x) (((x) & BIT_MASK_BIST_RPT_SEL_8821C) << BIT_SHIFT_BIST_RPT_SEL_8821C) -#define BIT_GET_BIST_RPT_SEL_8821C(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8821C) & BIT_MASK_BIST_RPT_SEL_8821C) - +#define BIT_BIST_RPT_SEL_8821C(x) \ + (((x) & BIT_MASK_BIST_RPT_SEL_8821C) << BIT_SHIFT_BIST_RPT_SEL_8821C) +#define BITS_BIST_RPT_SEL_8821C \ + (BIT_MASK_BIST_RPT_SEL_8821C << BIT_SHIFT_BIST_RPT_SEL_8821C) +#define BIT_CLEAR_BIST_RPT_SEL_8821C(x) ((x) & (~BITS_BIST_RPT_SEL_8821C)) +#define BIT_GET_BIST_RPT_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_BIST_RPT_SEL_8821C) & BIT_MASK_BIST_RPT_SEL_8821C) +#define BIT_SET_BIST_RPT_SEL_8821C(x, v) \ + (BIT_CLEAR_BIST_RPT_SEL_8821C(x) | BIT_BIST_RPT_SEL_8821C(v)) #define BIT_BIST_RESUME_PS_8821C BIT(4) #define BIT_BIST_RESUME_8821C BIT(3) @@ -1535,62 +2202,100 @@ #define BIT_SHIFT_MBIST_REPORT_8821C 0 #define BIT_MASK_MBIST_REPORT_8821C 0xffffffffL -#define BIT_MBIST_REPORT_8821C(x) (((x) & BIT_MASK_MBIST_REPORT_8821C) << BIT_SHIFT_MBIST_REPORT_8821C) -#define BIT_GET_MBIST_REPORT_8821C(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8821C) & BIT_MASK_MBIST_REPORT_8821C) - - +#define BIT_MBIST_REPORT_8821C(x) \ + (((x) & BIT_MASK_MBIST_REPORT_8821C) << BIT_SHIFT_MBIST_REPORT_8821C) +#define BITS_MBIST_REPORT_8821C \ + (BIT_MASK_MBIST_REPORT_8821C << BIT_SHIFT_MBIST_REPORT_8821C) +#define BIT_CLEAR_MBIST_REPORT_8821C(x) ((x) & (~BITS_MBIST_REPORT_8821C)) +#define BIT_GET_MBIST_REPORT_8821C(x) \ + (((x) >> BIT_SHIFT_MBIST_REPORT_8821C) & BIT_MASK_MBIST_REPORT_8821C) +#define BIT_SET_MBIST_REPORT_8821C(x, v) \ + (BIT_CLEAR_MBIST_REPORT_8821C(x) | BIT_MBIST_REPORT_8821C(v)) /* 2 REG_MEM_CTRL_8821C */ #define BIT_UMEM_RME_8821C BIT(31) #define BIT_SHIFT_BT_SPRAM_8821C 28 #define BIT_MASK_BT_SPRAM_8821C 0x3 -#define BIT_BT_SPRAM_8821C(x) (((x) & BIT_MASK_BT_SPRAM_8821C) << BIT_SHIFT_BT_SPRAM_8821C) -#define BIT_GET_BT_SPRAM_8821C(x) (((x) >> BIT_SHIFT_BT_SPRAM_8821C) & BIT_MASK_BT_SPRAM_8821C) - - +#define BIT_BT_SPRAM_8821C(x) \ + (((x) & BIT_MASK_BT_SPRAM_8821C) << BIT_SHIFT_BT_SPRAM_8821C) +#define BITS_BT_SPRAM_8821C \ + (BIT_MASK_BT_SPRAM_8821C << BIT_SHIFT_BT_SPRAM_8821C) +#define BIT_CLEAR_BT_SPRAM_8821C(x) ((x) & (~BITS_BT_SPRAM_8821C)) +#define BIT_GET_BT_SPRAM_8821C(x) \ + (((x) >> BIT_SHIFT_BT_SPRAM_8821C) & BIT_MASK_BT_SPRAM_8821C) +#define BIT_SET_BT_SPRAM_8821C(x, v) \ + (BIT_CLEAR_BT_SPRAM_8821C(x) | BIT_BT_SPRAM_8821C(v)) #define BIT_SHIFT_BT_ROM_8821C 24 #define BIT_MASK_BT_ROM_8821C 0xf -#define BIT_BT_ROM_8821C(x) (((x) & BIT_MASK_BT_ROM_8821C) << BIT_SHIFT_BT_ROM_8821C) -#define BIT_GET_BT_ROM_8821C(x) (((x) >> BIT_SHIFT_BT_ROM_8821C) & BIT_MASK_BT_ROM_8821C) - - +#define BIT_BT_ROM_8821C(x) \ + (((x) & BIT_MASK_BT_ROM_8821C) << BIT_SHIFT_BT_ROM_8821C) +#define BITS_BT_ROM_8821C (BIT_MASK_BT_ROM_8821C << BIT_SHIFT_BT_ROM_8821C) +#define BIT_CLEAR_BT_ROM_8821C(x) ((x) & (~BITS_BT_ROM_8821C)) +#define BIT_GET_BT_ROM_8821C(x) \ + (((x) >> BIT_SHIFT_BT_ROM_8821C) & BIT_MASK_BT_ROM_8821C) +#define BIT_SET_BT_ROM_8821C(x, v) \ + (BIT_CLEAR_BT_ROM_8821C(x) | BIT_BT_ROM_8821C(v)) #define BIT_SHIFT_PCI_DPRAM_8821C 10 #define BIT_MASK_PCI_DPRAM_8821C 0x3 -#define BIT_PCI_DPRAM_8821C(x) (((x) & BIT_MASK_PCI_DPRAM_8821C) << BIT_SHIFT_PCI_DPRAM_8821C) -#define BIT_GET_PCI_DPRAM_8821C(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8821C) & BIT_MASK_PCI_DPRAM_8821C) - - +#define BIT_PCI_DPRAM_8821C(x) \ + (((x) & BIT_MASK_PCI_DPRAM_8821C) << BIT_SHIFT_PCI_DPRAM_8821C) +#define BITS_PCI_DPRAM_8821C \ + (BIT_MASK_PCI_DPRAM_8821C << BIT_SHIFT_PCI_DPRAM_8821C) +#define BIT_CLEAR_PCI_DPRAM_8821C(x) ((x) & (~BITS_PCI_DPRAM_8821C)) +#define BIT_GET_PCI_DPRAM_8821C(x) \ + (((x) >> BIT_SHIFT_PCI_DPRAM_8821C) & BIT_MASK_PCI_DPRAM_8821C) +#define BIT_SET_PCI_DPRAM_8821C(x, v) \ + (BIT_CLEAR_PCI_DPRAM_8821C(x) | BIT_PCI_DPRAM_8821C(v)) #define BIT_SHIFT_PCI_SPRAM_8821C 8 #define BIT_MASK_PCI_SPRAM_8821C 0x3 -#define BIT_PCI_SPRAM_8821C(x) (((x) & BIT_MASK_PCI_SPRAM_8821C) << BIT_SHIFT_PCI_SPRAM_8821C) -#define BIT_GET_PCI_SPRAM_8821C(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8821C) & BIT_MASK_PCI_SPRAM_8821C) - - +#define BIT_PCI_SPRAM_8821C(x) \ + (((x) & BIT_MASK_PCI_SPRAM_8821C) << BIT_SHIFT_PCI_SPRAM_8821C) +#define BITS_PCI_SPRAM_8821C \ + (BIT_MASK_PCI_SPRAM_8821C << BIT_SHIFT_PCI_SPRAM_8821C) +#define BIT_CLEAR_PCI_SPRAM_8821C(x) ((x) & (~BITS_PCI_SPRAM_8821C)) +#define BIT_GET_PCI_SPRAM_8821C(x) \ + (((x) >> BIT_SHIFT_PCI_SPRAM_8821C) & BIT_MASK_PCI_SPRAM_8821C) +#define BIT_SET_PCI_SPRAM_8821C(x, v) \ + (BIT_CLEAR_PCI_SPRAM_8821C(x) | BIT_PCI_SPRAM_8821C(v)) #define BIT_SHIFT_USB_SPRAM_8821C 6 #define BIT_MASK_USB_SPRAM_8821C 0x3 -#define BIT_USB_SPRAM_8821C(x) (((x) & BIT_MASK_USB_SPRAM_8821C) << BIT_SHIFT_USB_SPRAM_8821C) -#define BIT_GET_USB_SPRAM_8821C(x) (((x) >> BIT_SHIFT_USB_SPRAM_8821C) & BIT_MASK_USB_SPRAM_8821C) - - +#define BIT_USB_SPRAM_8821C(x) \ + (((x) & BIT_MASK_USB_SPRAM_8821C) << BIT_SHIFT_USB_SPRAM_8821C) +#define BITS_USB_SPRAM_8821C \ + (BIT_MASK_USB_SPRAM_8821C << BIT_SHIFT_USB_SPRAM_8821C) +#define BIT_CLEAR_USB_SPRAM_8821C(x) ((x) & (~BITS_USB_SPRAM_8821C)) +#define BIT_GET_USB_SPRAM_8821C(x) \ + (((x) >> BIT_SHIFT_USB_SPRAM_8821C) & BIT_MASK_USB_SPRAM_8821C) +#define BIT_SET_USB_SPRAM_8821C(x, v) \ + (BIT_CLEAR_USB_SPRAM_8821C(x) | BIT_USB_SPRAM_8821C(v)) #define BIT_SHIFT_USB_SPRF_8821C 4 #define BIT_MASK_USB_SPRF_8821C 0x3 -#define BIT_USB_SPRF_8821C(x) (((x) & BIT_MASK_USB_SPRF_8821C) << BIT_SHIFT_USB_SPRF_8821C) -#define BIT_GET_USB_SPRF_8821C(x) (((x) >> BIT_SHIFT_USB_SPRF_8821C) & BIT_MASK_USB_SPRF_8821C) - - +#define BIT_USB_SPRF_8821C(x) \ + (((x) & BIT_MASK_USB_SPRF_8821C) << BIT_SHIFT_USB_SPRF_8821C) +#define BITS_USB_SPRF_8821C \ + (BIT_MASK_USB_SPRF_8821C << BIT_SHIFT_USB_SPRF_8821C) +#define BIT_CLEAR_USB_SPRF_8821C(x) ((x) & (~BITS_USB_SPRF_8821C)) +#define BIT_GET_USB_SPRF_8821C(x) \ + (((x) >> BIT_SHIFT_USB_SPRF_8821C) & BIT_MASK_USB_SPRF_8821C) +#define BIT_SET_USB_SPRF_8821C(x, v) \ + (BIT_CLEAR_USB_SPRF_8821C(x) | BIT_USB_SPRF_8821C(v)) #define BIT_SHIFT_MCU_ROM_8821C 0 #define BIT_MASK_MCU_ROM_8821C 0xf -#define BIT_MCU_ROM_8821C(x) (((x) & BIT_MASK_MCU_ROM_8821C) << BIT_SHIFT_MCU_ROM_8821C) -#define BIT_GET_MCU_ROM_8821C(x) (((x) >> BIT_SHIFT_MCU_ROM_8821C) & BIT_MASK_MCU_ROM_8821C) - - +#define BIT_MCU_ROM_8821C(x) \ + (((x) & BIT_MASK_MCU_ROM_8821C) << BIT_SHIFT_MCU_ROM_8821C) +#define BITS_MCU_ROM_8821C (BIT_MASK_MCU_ROM_8821C << BIT_SHIFT_MCU_ROM_8821C) +#define BIT_CLEAR_MCU_ROM_8821C(x) ((x) & (~BITS_MCU_ROM_8821C)) +#define BIT_GET_MCU_ROM_8821C(x) \ + (((x) >> BIT_SHIFT_MCU_ROM_8821C) & BIT_MASK_MCU_ROM_8821C) +#define BIT_SET_MCU_ROM_8821C(x, v) \ + (BIT_CLEAR_MCU_ROM_8821C(x) | BIT_MCU_ROM_8821C(v)) /* 2 REG_AFE_CTRL8_8821C */ #define BIT_SYN_AGPIO_8821C BIT(20) @@ -1599,10 +2304,15 @@ #define BIT_SHIFT_XTAL_SEL_TOK_8821C 0 #define BIT_MASK_XTAL_SEL_TOK_8821C 0x7 -#define BIT_XTAL_SEL_TOK_8821C(x) (((x) & BIT_MASK_XTAL_SEL_TOK_8821C) << BIT_SHIFT_XTAL_SEL_TOK_8821C) -#define BIT_GET_XTAL_SEL_TOK_8821C(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8821C) & BIT_MASK_XTAL_SEL_TOK_8821C) - - +#define BIT_XTAL_SEL_TOK_8821C(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_8821C) << BIT_SHIFT_XTAL_SEL_TOK_8821C) +#define BITS_XTAL_SEL_TOK_8821C \ + (BIT_MASK_XTAL_SEL_TOK_8821C << BIT_SHIFT_XTAL_SEL_TOK_8821C) +#define BIT_CLEAR_XTAL_SEL_TOK_8821C(x) ((x) & (~BITS_XTAL_SEL_TOK_8821C)) +#define BIT_GET_XTAL_SEL_TOK_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8821C) & BIT_MASK_XTAL_SEL_TOK_8821C) +#define BIT_SET_XTAL_SEL_TOK_8821C(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_8821C(x) | BIT_XTAL_SEL_TOK_8821C(v)) /* 2 REG_USB_SIE_INTF_8821C */ #define BIT_RD_SEL_8821C BIT(31) @@ -1612,68 +2322,136 @@ #define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C 16 #define BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C 0x1ff -#define BIT_USB_SIE_INTF_ADDR_V1_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) -#define BIT_GET_USB_SIE_INTF_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) - - +#define BIT_USB_SIE_INTF_ADDR_V1_8821C(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) +#define BITS_USB_SIE_INTF_ADDR_V1_8821C \ + (BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) +#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8821C(x) \ + ((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8821C)) +#define BIT_GET_USB_SIE_INTF_ADDR_V1_8821C(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) & \ + BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) +#define BIT_SET_USB_SIE_INTF_ADDR_V1_8821C(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8821C(x) | \ + BIT_USB_SIE_INTF_ADDR_V1_8821C(v)) #define BIT_SHIFT_USB_SIE_INTF_RD_8821C 8 #define BIT_MASK_USB_SIE_INTF_RD_8821C 0xff -#define BIT_USB_SIE_INTF_RD_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_RD_8821C) << BIT_SHIFT_USB_SIE_INTF_RD_8821C) -#define BIT_GET_USB_SIE_INTF_RD_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8821C) & BIT_MASK_USB_SIE_INTF_RD_8821C) - - +#define BIT_USB_SIE_INTF_RD_8821C(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_RD_8821C) \ + << BIT_SHIFT_USB_SIE_INTF_RD_8821C) +#define BITS_USB_SIE_INTF_RD_8821C \ + (BIT_MASK_USB_SIE_INTF_RD_8821C << BIT_SHIFT_USB_SIE_INTF_RD_8821C) +#define BIT_CLEAR_USB_SIE_INTF_RD_8821C(x) ((x) & (~BITS_USB_SIE_INTF_RD_8821C)) +#define BIT_GET_USB_SIE_INTF_RD_8821C(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8821C) & \ + BIT_MASK_USB_SIE_INTF_RD_8821C) +#define BIT_SET_USB_SIE_INTF_RD_8821C(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_RD_8821C(x) | BIT_USB_SIE_INTF_RD_8821C(v)) #define BIT_SHIFT_USB_SIE_INTF_WD_8821C 0 #define BIT_MASK_USB_SIE_INTF_WD_8821C 0xff -#define BIT_USB_SIE_INTF_WD_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_WD_8821C) << BIT_SHIFT_USB_SIE_INTF_WD_8821C) -#define BIT_GET_USB_SIE_INTF_WD_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8821C) & BIT_MASK_USB_SIE_INTF_WD_8821C) +#define BIT_USB_SIE_INTF_WD_8821C(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_WD_8821C) \ + << BIT_SHIFT_USB_SIE_INTF_WD_8821C) +#define BITS_USB_SIE_INTF_WD_8821C \ + (BIT_MASK_USB_SIE_INTF_WD_8821C << BIT_SHIFT_USB_SIE_INTF_WD_8821C) +#define BIT_CLEAR_USB_SIE_INTF_WD_8821C(x) ((x) & (~BITS_USB_SIE_INTF_WD_8821C)) +#define BIT_GET_USB_SIE_INTF_WD_8821C(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8821C) & \ + BIT_MASK_USB_SIE_INTF_WD_8821C) +#define BIT_SET_USB_SIE_INTF_WD_8821C(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_WD_8821C(x) | BIT_USB_SIE_INTF_WD_8821C(v)) +/* 2 REG_PCIE_MIO_INTF_8821C */ +#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C 16 +#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C 0x3 +#define BIT_PCIE_MIO_ADDR_PAGE_8821C(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C) \ + << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C) +#define BITS_PCIE_MIO_ADDR_PAGE_8821C \ + (BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C \ + << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C) +#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8821C(x) \ + ((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8821C)) +#define BIT_GET_PCIE_MIO_ADDR_PAGE_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C) & \ + BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C) +#define BIT_SET_PCIE_MIO_ADDR_PAGE_8821C(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8821C(x) | \ + BIT_PCIE_MIO_ADDR_PAGE_8821C(v)) -/* 2 REG_PCIE_MIO_INTF_8821C */ #define BIT_PCIE_MIO_BYIOREG_8821C BIT(13) #define BIT_PCIE_MIO_RE_8821C BIT(12) #define BIT_SHIFT_PCIE_MIO_WE_8821C 8 #define BIT_MASK_PCIE_MIO_WE_8821C 0xf -#define BIT_PCIE_MIO_WE_8821C(x) (((x) & BIT_MASK_PCIE_MIO_WE_8821C) << BIT_SHIFT_PCIE_MIO_WE_8821C) -#define BIT_GET_PCIE_MIO_WE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8821C) & BIT_MASK_PCIE_MIO_WE_8821C) - - +#define BIT_PCIE_MIO_WE_8821C(x) \ + (((x) & BIT_MASK_PCIE_MIO_WE_8821C) << BIT_SHIFT_PCIE_MIO_WE_8821C) +#define BITS_PCIE_MIO_WE_8821C \ + (BIT_MASK_PCIE_MIO_WE_8821C << BIT_SHIFT_PCIE_MIO_WE_8821C) +#define BIT_CLEAR_PCIE_MIO_WE_8821C(x) ((x) & (~BITS_PCIE_MIO_WE_8821C)) +#define BIT_GET_PCIE_MIO_WE_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_WE_8821C) & BIT_MASK_PCIE_MIO_WE_8821C) +#define BIT_SET_PCIE_MIO_WE_8821C(x, v) \ + (BIT_CLEAR_PCIE_MIO_WE_8821C(x) | BIT_PCIE_MIO_WE_8821C(v)) #define BIT_SHIFT_PCIE_MIO_ADDR_8821C 0 #define BIT_MASK_PCIE_MIO_ADDR_8821C 0xff -#define BIT_PCIE_MIO_ADDR_8821C(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8821C) << BIT_SHIFT_PCIE_MIO_ADDR_8821C) -#define BIT_GET_PCIE_MIO_ADDR_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8821C) & BIT_MASK_PCIE_MIO_ADDR_8821C) - - +#define BIT_PCIE_MIO_ADDR_8821C(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_8821C) << BIT_SHIFT_PCIE_MIO_ADDR_8821C) +#define BITS_PCIE_MIO_ADDR_8821C \ + (BIT_MASK_PCIE_MIO_ADDR_8821C << BIT_SHIFT_PCIE_MIO_ADDR_8821C) +#define BIT_CLEAR_PCIE_MIO_ADDR_8821C(x) ((x) & (~BITS_PCIE_MIO_ADDR_8821C)) +#define BIT_GET_PCIE_MIO_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8821C) & BIT_MASK_PCIE_MIO_ADDR_8821C) +#define BIT_SET_PCIE_MIO_ADDR_8821C(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_8821C(x) | BIT_PCIE_MIO_ADDR_8821C(v)) /* 2 REG_PCIE_MIO_INTD_8821C */ #define BIT_SHIFT_PCIE_MIO_DATA_8821C 0 #define BIT_MASK_PCIE_MIO_DATA_8821C 0xffffffffL -#define BIT_PCIE_MIO_DATA_8821C(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8821C) << BIT_SHIFT_PCIE_MIO_DATA_8821C) -#define BIT_GET_PCIE_MIO_DATA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8821C) & BIT_MASK_PCIE_MIO_DATA_8821C) - - +#define BIT_PCIE_MIO_DATA_8821C(x) \ + (((x) & BIT_MASK_PCIE_MIO_DATA_8821C) << BIT_SHIFT_PCIE_MIO_DATA_8821C) +#define BITS_PCIE_MIO_DATA_8821C \ + (BIT_MASK_PCIE_MIO_DATA_8821C << BIT_SHIFT_PCIE_MIO_DATA_8821C) +#define BIT_CLEAR_PCIE_MIO_DATA_8821C(x) ((x) & (~BITS_PCIE_MIO_DATA_8821C)) +#define BIT_GET_PCIE_MIO_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8821C) & BIT_MASK_PCIE_MIO_DATA_8821C) +#define BIT_SET_PCIE_MIO_DATA_8821C(x, v) \ + (BIT_CLEAR_PCIE_MIO_DATA_8821C(x) | BIT_PCIE_MIO_DATA_8821C(v)) /* 2 REG_WLRF1_8821C */ #define BIT_SHIFT_WLRF1_CTRL_8821C 24 #define BIT_MASK_WLRF1_CTRL_8821C 0xff -#define BIT_WLRF1_CTRL_8821C(x) (((x) & BIT_MASK_WLRF1_CTRL_8821C) << BIT_SHIFT_WLRF1_CTRL_8821C) -#define BIT_GET_WLRF1_CTRL_8821C(x) (((x) >> BIT_SHIFT_WLRF1_CTRL_8821C) & BIT_MASK_WLRF1_CTRL_8821C) - - +#define BIT_WLRF1_CTRL_8821C(x) \ + (((x) & BIT_MASK_WLRF1_CTRL_8821C) << BIT_SHIFT_WLRF1_CTRL_8821C) +#define BITS_WLRF1_CTRL_8821C \ + (BIT_MASK_WLRF1_CTRL_8821C << BIT_SHIFT_WLRF1_CTRL_8821C) +#define BIT_CLEAR_WLRF1_CTRL_8821C(x) ((x) & (~BITS_WLRF1_CTRL_8821C)) +#define BIT_GET_WLRF1_CTRL_8821C(x) \ + (((x) >> BIT_SHIFT_WLRF1_CTRL_8821C) & BIT_MASK_WLRF1_CTRL_8821C) +#define BIT_SET_WLRF1_CTRL_8821C(x, v) \ + (BIT_CLEAR_WLRF1_CTRL_8821C(x) | BIT_WLRF1_CTRL_8821C(v)) /* 2 REG_SYS_CFG1_8821C */ #define BIT_SHIFT_TRP_ICFG_8821C 28 #define BIT_MASK_TRP_ICFG_8821C 0xf -#define BIT_TRP_ICFG_8821C(x) (((x) & BIT_MASK_TRP_ICFG_8821C) << BIT_SHIFT_TRP_ICFG_8821C) -#define BIT_GET_TRP_ICFG_8821C(x) (((x) >> BIT_SHIFT_TRP_ICFG_8821C) & BIT_MASK_TRP_ICFG_8821C) - +#define BIT_TRP_ICFG_8821C(x) \ + (((x) & BIT_MASK_TRP_ICFG_8821C) << BIT_SHIFT_TRP_ICFG_8821C) +#define BITS_TRP_ICFG_8821C \ + (BIT_MASK_TRP_ICFG_8821C << BIT_SHIFT_TRP_ICFG_8821C) +#define BIT_CLEAR_TRP_ICFG_8821C(x) ((x) & (~BITS_TRP_ICFG_8821C)) +#define BIT_GET_TRP_ICFG_8821C(x) \ + (((x) >> BIT_SHIFT_TRP_ICFG_8821C) & BIT_MASK_TRP_ICFG_8821C) +#define BIT_SET_TRP_ICFG_8821C(x, v) \ + (BIT_CLEAR_TRP_ICFG_8821C(x) | BIT_TRP_ICFG_8821C(v)) #define BIT_RF_TYPE_ID_8821C BIT(27) #define BIT_BD_HCI_SEL_8821C BIT(26) @@ -1685,16 +2463,27 @@ #define BIT_SHIFT_VENDOR_ID_8821C 16 #define BIT_MASK_VENDOR_ID_8821C 0xf -#define BIT_VENDOR_ID_8821C(x) (((x) & BIT_MASK_VENDOR_ID_8821C) << BIT_SHIFT_VENDOR_ID_8821C) -#define BIT_GET_VENDOR_ID_8821C(x) (((x) >> BIT_SHIFT_VENDOR_ID_8821C) & BIT_MASK_VENDOR_ID_8821C) - - +#define BIT_VENDOR_ID_8821C(x) \ + (((x) & BIT_MASK_VENDOR_ID_8821C) << BIT_SHIFT_VENDOR_ID_8821C) +#define BITS_VENDOR_ID_8821C \ + (BIT_MASK_VENDOR_ID_8821C << BIT_SHIFT_VENDOR_ID_8821C) +#define BIT_CLEAR_VENDOR_ID_8821C(x) ((x) & (~BITS_VENDOR_ID_8821C)) +#define BIT_GET_VENDOR_ID_8821C(x) \ + (((x) >> BIT_SHIFT_VENDOR_ID_8821C) & BIT_MASK_VENDOR_ID_8821C) +#define BIT_SET_VENDOR_ID_8821C(x, v) \ + (BIT_CLEAR_VENDOR_ID_8821C(x) | BIT_VENDOR_ID_8821C(v)) #define BIT_SHIFT_CHIP_VER_8821C 12 #define BIT_MASK_CHIP_VER_8821C 0xf -#define BIT_CHIP_VER_8821C(x) (((x) & BIT_MASK_CHIP_VER_8821C) << BIT_SHIFT_CHIP_VER_8821C) -#define BIT_GET_CHIP_VER_8821C(x) (((x) >> BIT_SHIFT_CHIP_VER_8821C) & BIT_MASK_CHIP_VER_8821C) - +#define BIT_CHIP_VER_8821C(x) \ + (((x) & BIT_MASK_CHIP_VER_8821C) << BIT_SHIFT_CHIP_VER_8821C) +#define BITS_CHIP_VER_8821C \ + (BIT_MASK_CHIP_VER_8821C << BIT_SHIFT_CHIP_VER_8821C) +#define BIT_CLEAR_CHIP_VER_8821C(x) ((x) & (~BITS_CHIP_VER_8821C)) +#define BIT_GET_CHIP_VER_8821C(x) \ + (((x) >> BIT_SHIFT_CHIP_VER_8821C) & BIT_MASK_CHIP_VER_8821C) +#define BIT_SET_CHIP_VER_8821C(x, v) \ + (BIT_CLEAR_CHIP_VER_8821C(x) | BIT_CHIP_VER_8821C(v)) #define BIT_BD_MAC3_8821C BIT(11) #define BIT_BD_MAC1_8821C BIT(10) @@ -1713,17 +2502,41 @@ #define BIT_SHIFT_RF_RL_ID_8821C 28 #define BIT_MASK_RF_RL_ID_8821C 0xf -#define BIT_RF_RL_ID_8821C(x) (((x) & BIT_MASK_RF_RL_ID_8821C) << BIT_SHIFT_RF_RL_ID_8821C) -#define BIT_GET_RF_RL_ID_8821C(x) (((x) >> BIT_SHIFT_RF_RL_ID_8821C) & BIT_MASK_RF_RL_ID_8821C) - +#define BIT_RF_RL_ID_8821C(x) \ + (((x) & BIT_MASK_RF_RL_ID_8821C) << BIT_SHIFT_RF_RL_ID_8821C) +#define BITS_RF_RL_ID_8821C \ + (BIT_MASK_RF_RL_ID_8821C << BIT_SHIFT_RF_RL_ID_8821C) +#define BIT_CLEAR_RF_RL_ID_8821C(x) ((x) & (~BITS_RF_RL_ID_8821C)) +#define BIT_GET_RF_RL_ID_8821C(x) \ + (((x) >> BIT_SHIFT_RF_RL_ID_8821C) & BIT_MASK_RF_RL_ID_8821C) +#define BIT_SET_RF_RL_ID_8821C(x, v) \ + (BIT_CLEAR_RF_RL_ID_8821C(x) | BIT_RF_RL_ID_8821C(v)) #define BIT_HPHY_ICFG_8821C BIT(19) #define BIT_SHIFT_SEL_0XC0_8821C 16 #define BIT_MASK_SEL_0XC0_8821C 0x3 -#define BIT_SEL_0XC0_8821C(x) (((x) & BIT_MASK_SEL_0XC0_8821C) << BIT_SHIFT_SEL_0XC0_8821C) -#define BIT_GET_SEL_0XC0_8821C(x) (((x) >> BIT_SHIFT_SEL_0XC0_8821C) & BIT_MASK_SEL_0XC0_8821C) - +#define BIT_SEL_0XC0_8821C(x) \ + (((x) & BIT_MASK_SEL_0XC0_8821C) << BIT_SHIFT_SEL_0XC0_8821C) +#define BITS_SEL_0XC0_8821C \ + (BIT_MASK_SEL_0XC0_8821C << BIT_SHIFT_SEL_0XC0_8821C) +#define BIT_CLEAR_SEL_0XC0_8821C(x) ((x) & (~BITS_SEL_0XC0_8821C)) +#define BIT_GET_SEL_0XC0_8821C(x) \ + (((x) >> BIT_SHIFT_SEL_0XC0_8821C) & BIT_MASK_SEL_0XC0_8821C) +#define BIT_SET_SEL_0XC0_8821C(x, v) \ + (BIT_CLEAR_SEL_0XC0_8821C(x) | BIT_SEL_0XC0_8821C(v)) + +#define BIT_SHIFT_HCI_SEL_V4_8821C 12 +#define BIT_MASK_HCI_SEL_V4_8821C 0x3 +#define BIT_HCI_SEL_V4_8821C(x) \ + (((x) & BIT_MASK_HCI_SEL_V4_8821C) << BIT_SHIFT_HCI_SEL_V4_8821C) +#define BITS_HCI_SEL_V4_8821C \ + (BIT_MASK_HCI_SEL_V4_8821C << BIT_SHIFT_HCI_SEL_V4_8821C) +#define BIT_CLEAR_HCI_SEL_V4_8821C(x) ((x) & (~BITS_HCI_SEL_V4_8821C)) +#define BIT_GET_HCI_SEL_V4_8821C(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V4_8821C) & BIT_MASK_HCI_SEL_V4_8821C) +#define BIT_SET_HCI_SEL_V4_8821C(x, v) \ + (BIT_CLEAR_HCI_SEL_V4_8821C(x) | BIT_HCI_SEL_V4_8821C(v)) #define BIT_USB_OPERATION_MODE_8821C BIT(10) #define BIT_BT_PDN_8821C BIT(9) @@ -1731,26 +2544,31 @@ #define BIT_WL_MODE_8821C BIT(7) #define BIT_PKG_SEL_HCI_8821C BIT(6) -#define BIT_SHIFT_HCI_SEL_8821C 4 -#define BIT_MASK_HCI_SEL_8821C 0x3 -#define BIT_HCI_SEL_8821C(x) (((x) & BIT_MASK_HCI_SEL_8821C) << BIT_SHIFT_HCI_SEL_8821C) -#define BIT_GET_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_HCI_SEL_8821C) & BIT_MASK_HCI_SEL_8821C) - - - -#define BIT_SHIFT_PAD_HCI_SEL_8821C 2 -#define BIT_MASK_PAD_HCI_SEL_8821C 0x3 -#define BIT_PAD_HCI_SEL_8821C(x) (((x) & BIT_MASK_PAD_HCI_SEL_8821C) << BIT_SHIFT_PAD_HCI_SEL_8821C) -#define BIT_GET_PAD_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_8821C) & BIT_MASK_PAD_HCI_SEL_8821C) - - +#define BIT_SHIFT_PAD_HCI_SEL_V2_8821C 3 +#define BIT_MASK_PAD_HCI_SEL_V2_8821C 0x3 +#define BIT_PAD_HCI_SEL_V2_8821C(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_V2_8821C) \ + << BIT_SHIFT_PAD_HCI_SEL_V2_8821C) +#define BITS_PAD_HCI_SEL_V2_8821C \ + (BIT_MASK_PAD_HCI_SEL_V2_8821C << BIT_SHIFT_PAD_HCI_SEL_V2_8821C) +#define BIT_CLEAR_PAD_HCI_SEL_V2_8821C(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8821C)) +#define BIT_GET_PAD_HCI_SEL_V2_8821C(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8821C) & \ + BIT_MASK_PAD_HCI_SEL_V2_8821C) +#define BIT_SET_PAD_HCI_SEL_V2_8821C(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_V2_8821C(x) | BIT_PAD_HCI_SEL_V2_8821C(v)) #define BIT_SHIFT_EFS_HCI_SEL_8821C 0 #define BIT_MASK_EFS_HCI_SEL_8821C 0x3 -#define BIT_EFS_HCI_SEL_8821C(x) (((x) & BIT_MASK_EFS_HCI_SEL_8821C) << BIT_SHIFT_EFS_HCI_SEL_8821C) -#define BIT_GET_EFS_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_8821C) & BIT_MASK_EFS_HCI_SEL_8821C) - - +#define BIT_EFS_HCI_SEL_8821C(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL_8821C) << BIT_SHIFT_EFS_HCI_SEL_8821C) +#define BITS_EFS_HCI_SEL_8821C \ + (BIT_MASK_EFS_HCI_SEL_8821C << BIT_SHIFT_EFS_HCI_SEL_8821C) +#define BIT_CLEAR_EFS_HCI_SEL_8821C(x) ((x) & (~BITS_EFS_HCI_SEL_8821C)) +#define BIT_GET_EFS_HCI_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL_8821C) & BIT_MASK_EFS_HCI_SEL_8821C) +#define BIT_SET_EFS_HCI_SEL_8821C(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL_8821C(x) | BIT_EFS_HCI_SEL_8821C(v)) /* 2 REG_SYS_STATUS2_8821C */ #define BIT_SIO_ALDN_8821C BIT(19) @@ -1760,70 +2578,161 @@ #define BIT_SHIFT_EPVID1_8821C 8 #define BIT_MASK_EPVID1_8821C 0xff -#define BIT_EPVID1_8821C(x) (((x) & BIT_MASK_EPVID1_8821C) << BIT_SHIFT_EPVID1_8821C) -#define BIT_GET_EPVID1_8821C(x) (((x) >> BIT_SHIFT_EPVID1_8821C) & BIT_MASK_EPVID1_8821C) - - +#define BIT_EPVID1_8821C(x) \ + (((x) & BIT_MASK_EPVID1_8821C) << BIT_SHIFT_EPVID1_8821C) +#define BITS_EPVID1_8821C (BIT_MASK_EPVID1_8821C << BIT_SHIFT_EPVID1_8821C) +#define BIT_CLEAR_EPVID1_8821C(x) ((x) & (~BITS_EPVID1_8821C)) +#define BIT_GET_EPVID1_8821C(x) \ + (((x) >> BIT_SHIFT_EPVID1_8821C) & BIT_MASK_EPVID1_8821C) +#define BIT_SET_EPVID1_8821C(x, v) \ + (BIT_CLEAR_EPVID1_8821C(x) | BIT_EPVID1_8821C(v)) #define BIT_SHIFT_EPVID0_8821C 0 #define BIT_MASK_EPVID0_8821C 0xff -#define BIT_EPVID0_8821C(x) (((x) & BIT_MASK_EPVID0_8821C) << BIT_SHIFT_EPVID0_8821C) -#define BIT_GET_EPVID0_8821C(x) (((x) >> BIT_SHIFT_EPVID0_8821C) & BIT_MASK_EPVID0_8821C) - - +#define BIT_EPVID0_8821C(x) \ + (((x) & BIT_MASK_EPVID0_8821C) << BIT_SHIFT_EPVID0_8821C) +#define BITS_EPVID0_8821C (BIT_MASK_EPVID0_8821C << BIT_SHIFT_EPVID0_8821C) +#define BIT_CLEAR_EPVID0_8821C(x) ((x) & (~BITS_EPVID0_8821C)) +#define BIT_GET_EPVID0_8821C(x) \ + (((x) >> BIT_SHIFT_EPVID0_8821C) & BIT_MASK_EPVID0_8821C) +#define BIT_SET_EPVID0_8821C(x, v) \ + (BIT_CLEAR_EPVID0_8821C(x) | BIT_EPVID0_8821C(v)) /* 2 REG_SYS_CFG2_8821C */ -#define BIT_HCI_SEL_EMBEDED_8821C BIT(8) +#define BIT_HCI_SEL_EMBEDDED_8821C BIT(8) #define BIT_SHIFT_HW_ID_8821C 0 #define BIT_MASK_HW_ID_8821C 0xff -#define BIT_HW_ID_8821C(x) (((x) & BIT_MASK_HW_ID_8821C) << BIT_SHIFT_HW_ID_8821C) -#define BIT_GET_HW_ID_8821C(x) (((x) >> BIT_SHIFT_HW_ID_8821C) & BIT_MASK_HW_ID_8821C) - - +#define BIT_HW_ID_8821C(x) \ + (((x) & BIT_MASK_HW_ID_8821C) << BIT_SHIFT_HW_ID_8821C) +#define BITS_HW_ID_8821C (BIT_MASK_HW_ID_8821C << BIT_SHIFT_HW_ID_8821C) +#define BIT_CLEAR_HW_ID_8821C(x) ((x) & (~BITS_HW_ID_8821C)) +#define BIT_GET_HW_ID_8821C(x) \ + (((x) >> BIT_SHIFT_HW_ID_8821C) & BIT_MASK_HW_ID_8821C) +#define BIT_SET_HW_ID_8821C(x, v) \ + (BIT_CLEAR_HW_ID_8821C(x) | BIT_HW_ID_8821C(v)) /* 2 REG_SYS_CFG3_8821C */ -#define BIT_PWC_MA33V_8821C BIT(15) -#define BIT_PWC_MA12V_8821C BIT(14) -#define BIT_PWC_MD12V_8821C BIT(13) -#define BIT_PWC_PD12V_8821C BIT(12) -#define BIT_PWC_UD12V_8821C BIT(11) -#define BIT_ISO_MA2MD_8821C BIT(1) -#define BIT_ISO_MD2PP_8821C BIT(0) -/* 2 REG_SYS_CFG4_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_SYS_CFG5_8821C */ -#define BIT_LPS_STATUS_8821C BIT(3) -#define BIT_HCI_TXDMA_BUSY_8821C BIT(2) -#define BIT_HCI_TXDMA_ALLOW_8821C BIT(1) -#define BIT_FW_CTRL_HCI_TXDMA_EN_8821C BIT(0) +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_CPU_DMEM_CON_8821C */ -#define BIT_WDT_AUTO_MODE_8821C BIT(22) -#define BIT_WDT_PLATFORM_EN_8821C BIT(21) -#define BIT_WDT_CPU_EN_8821C BIT(20) -#define BIT_WDT_OPT_IOWRAPPER_8821C BIT(19) -#define BIT_ANA_PORT_IDLE_8821C BIT(18) -#define BIT_MAC_PORT_IDLE_8821C BIT(17) -#define BIT_WL_PLATFORM_RST_8821C BIT(16) -#define BIT_WL_SECURITY_CLK_8821C BIT(15) +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_CPU_DMEM_CON_8821C 0 -#define BIT_MASK_CPU_DMEM_CON_8821C 0xff -#define BIT_CPU_DMEM_CON_8821C(x) (((x) & BIT_MASK_CPU_DMEM_CON_8821C) << BIT_SHIFT_CPU_DMEM_CON_8821C) -#define BIT_GET_CPU_DMEM_CON_8821C(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8821C) & BIT_MASK_CPU_DMEM_CON_8821C) +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_SYS_CFG5_8821C */ +#define BIT_LPS_STATUS_8821C BIT(3) +#define BIT_HCI_TXDMA_BUSY_8821C BIT(2) +#define BIT_HCI_TXDMA_ALLOW_8821C BIT(1) +#define BIT_FW_CTRL_HCI_TXDMA_EN_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_CPU_DMEM_CON_8821C */ +#define BIT_WDT_AUTO_MODE_8821C BIT(22) +#define BIT_WDT_PLATFORM_EN_8821C BIT(21) +#define BIT_WDT_CPU_EN_8821C BIT(20) +#define BIT_WDT_OPT_IOWRAPPER_8821C BIT(19) +#define BIT_ANA_PORT_IDLE_8821C BIT(18) +#define BIT_MAC_PORT_IDLE_8821C BIT(17) +#define BIT_WL_PLATFORM_RST_8821C BIT(16) +#define BIT_WL_SECURITY_CLK_8821C BIT(15) +#define BIT_SHIFT_CPU_DMEM_CON_8821C 0 +#define BIT_MASK_CPU_DMEM_CON_8821C 0xff +#define BIT_CPU_DMEM_CON_8821C(x) \ + (((x) & BIT_MASK_CPU_DMEM_CON_8821C) << BIT_SHIFT_CPU_DMEM_CON_8821C) +#define BITS_CPU_DMEM_CON_8821C \ + (BIT_MASK_CPU_DMEM_CON_8821C << BIT_SHIFT_CPU_DMEM_CON_8821C) +#define BIT_CLEAR_CPU_DMEM_CON_8821C(x) ((x) & (~BITS_CPU_DMEM_CON_8821C)) +#define BIT_GET_CPU_DMEM_CON_8821C(x) \ + (((x) >> BIT_SHIFT_CPU_DMEM_CON_8821C) & BIT_MASK_CPU_DMEM_CON_8821C) +#define BIT_SET_CPU_DMEM_CON_8821C(x, v) \ + (BIT_CLEAR_CPU_DMEM_CON_8821C(x) | BIT_CPU_DMEM_CON_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_BOOT_REASON_8821C */ -#define BIT_SHIFT_BOOT_REASON_8821C 0 -#define BIT_MASK_BOOT_REASON_8821C 0x7 -#define BIT_BOOT_REASON_8821C(x) (((x) & BIT_MASK_BOOT_REASON_8821C) << BIT_SHIFT_BOOT_REASON_8821C) -#define BIT_GET_BOOT_REASON_8821C(x) (((x) >> BIT_SHIFT_BOOT_REASON_8821C) & BIT_MASK_BOOT_REASON_8821C) +#define BIT_SHIFT_BOOT_REASON_V1_8821C 0 +#define BIT_MASK_BOOT_REASON_V1_8821C 0x7 +#define BIT_BOOT_REASON_V1_8821C(x) \ + (((x) & BIT_MASK_BOOT_REASON_V1_8821C) \ + << BIT_SHIFT_BOOT_REASON_V1_8821C) +#define BITS_BOOT_REASON_V1_8821C \ + (BIT_MASK_BOOT_REASON_V1_8821C << BIT_SHIFT_BOOT_REASON_V1_8821C) +#define BIT_CLEAR_BOOT_REASON_V1_8821C(x) ((x) & (~BITS_BOOT_REASON_V1_8821C)) +#define BIT_GET_BOOT_REASON_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BOOT_REASON_V1_8821C) & \ + BIT_MASK_BOOT_REASON_V1_8821C) +#define BIT_SET_BOOT_REASON_V1_8821C(x, v) \ + (BIT_CLEAR_BOOT_REASON_V1_8821C(x) | BIT_BOOT_REASON_V1_8821C(v)) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NFCPAD_CTRL_8821C */ #define BIT_PAD_SHUTDW_8821C BIT(18) @@ -1836,24 +2745,41 @@ #define BIT_SHIFT_NFCPAD_IO_SEL_8821C 8 #define BIT_MASK_NFCPAD_IO_SEL_8821C 0xf -#define BIT_NFCPAD_IO_SEL_8821C(x) (((x) & BIT_MASK_NFCPAD_IO_SEL_8821C) << BIT_SHIFT_NFCPAD_IO_SEL_8821C) -#define BIT_GET_NFCPAD_IO_SEL_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8821C) & BIT_MASK_NFCPAD_IO_SEL_8821C) - - +#define BIT_NFCPAD_IO_SEL_8821C(x) \ + (((x) & BIT_MASK_NFCPAD_IO_SEL_8821C) << BIT_SHIFT_NFCPAD_IO_SEL_8821C) +#define BITS_NFCPAD_IO_SEL_8821C \ + (BIT_MASK_NFCPAD_IO_SEL_8821C << BIT_SHIFT_NFCPAD_IO_SEL_8821C) +#define BIT_CLEAR_NFCPAD_IO_SEL_8821C(x) ((x) & (~BITS_NFCPAD_IO_SEL_8821C)) +#define BIT_GET_NFCPAD_IO_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8821C) & BIT_MASK_NFCPAD_IO_SEL_8821C) +#define BIT_SET_NFCPAD_IO_SEL_8821C(x, v) \ + (BIT_CLEAR_NFCPAD_IO_SEL_8821C(x) | BIT_NFCPAD_IO_SEL_8821C(v)) #define BIT_SHIFT_NFCPAD_OUT_8821C 4 #define BIT_MASK_NFCPAD_OUT_8821C 0xf -#define BIT_NFCPAD_OUT_8821C(x) (((x) & BIT_MASK_NFCPAD_OUT_8821C) << BIT_SHIFT_NFCPAD_OUT_8821C) -#define BIT_GET_NFCPAD_OUT_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_OUT_8821C) & BIT_MASK_NFCPAD_OUT_8821C) - - +#define BIT_NFCPAD_OUT_8821C(x) \ + (((x) & BIT_MASK_NFCPAD_OUT_8821C) << BIT_SHIFT_NFCPAD_OUT_8821C) +#define BITS_NFCPAD_OUT_8821C \ + (BIT_MASK_NFCPAD_OUT_8821C << BIT_SHIFT_NFCPAD_OUT_8821C) +#define BIT_CLEAR_NFCPAD_OUT_8821C(x) ((x) & (~BITS_NFCPAD_OUT_8821C)) +#define BIT_GET_NFCPAD_OUT_8821C(x) \ + (((x) >> BIT_SHIFT_NFCPAD_OUT_8821C) & BIT_MASK_NFCPAD_OUT_8821C) +#define BIT_SET_NFCPAD_OUT_8821C(x, v) \ + (BIT_CLEAR_NFCPAD_OUT_8821C(x) | BIT_NFCPAD_OUT_8821C(v)) #define BIT_SHIFT_NFCPAD_IN_8821C 0 #define BIT_MASK_NFCPAD_IN_8821C 0xf -#define BIT_NFCPAD_IN_8821C(x) (((x) & BIT_MASK_NFCPAD_IN_8821C) << BIT_SHIFT_NFCPAD_IN_8821C) -#define BIT_GET_NFCPAD_IN_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_IN_8821C) & BIT_MASK_NFCPAD_IN_8821C) - +#define BIT_NFCPAD_IN_8821C(x) \ + (((x) & BIT_MASK_NFCPAD_IN_8821C) << BIT_SHIFT_NFCPAD_IN_8821C) +#define BITS_NFCPAD_IN_8821C \ + (BIT_MASK_NFCPAD_IN_8821C << BIT_SHIFT_NFCPAD_IN_8821C) +#define BIT_CLEAR_NFCPAD_IN_8821C(x) ((x) & (~BITS_NFCPAD_IN_8821C)) +#define BIT_GET_NFCPAD_IN_8821C(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IN_8821C) & BIT_MASK_NFCPAD_IN_8821C) +#define BIT_SET_NFCPAD_IN_8821C(x, v) \ + (BIT_CLEAR_NFCPAD_IN_8821C(x) | BIT_NFCPAD_IN_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_HIMR2_8821C */ #define BIT_BCNDMAINT_P4_MSK_8821C BIT(31) @@ -1950,42 +2876,45 @@ /* 2 REG_SW_MDIO_8821C */ #define BIT_DIS_TIMEOUT_IO_8821C BIT(24) -/* 2 REG_SW_FLUSH_8821C */ -#define BIT_FLUSH_HOLDN_EN_8821C BIT(25) -#define BIT_FLUSH_WR_EN_8821C BIT(24) -#define BIT_SW_FLASH_CONTROL_8821C BIT(23) -#define BIT_SW_FLASH_WEN_E_8821C BIT(19) -#define BIT_SW_FLASH_HOLDN_E_8821C BIT(18) -#define BIT_SW_FLASH_SO_E_8821C BIT(17) -#define BIT_SW_FLASH_SI_E_8821C BIT(16) -#define BIT_SW_FLASH_SK_O_8821C BIT(13) -#define BIT_SW_FLASH_CEN_O_8821C BIT(12) -#define BIT_SW_FLASH_WEN_O_8821C BIT(11) -#define BIT_SW_FLASH_HOLDN_O_8821C BIT(10) -#define BIT_SW_FLASH_SO_O_8821C BIT(9) -#define BIT_SW_FLASH_SI_O_8821C BIT(8) -#define BIT_SW_FLASH_WEN_I_8821C BIT(3) -#define BIT_SW_FLASH_HOLDN_I_8821C BIT(2) -#define BIT_SW_FLASH_SO_I_8821C BIT(1) -#define BIT_SW_FLASH_SI_I_8821C BIT(0) +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_H2C_PKT_READADDR_8821C */ #define BIT_SHIFT_H2C_PKT_READADDR_8821C 0 #define BIT_MASK_H2C_PKT_READADDR_8821C 0x3ffff -#define BIT_H2C_PKT_READADDR_8821C(x) (((x) & BIT_MASK_H2C_PKT_READADDR_8821C) << BIT_SHIFT_H2C_PKT_READADDR_8821C) -#define BIT_GET_H2C_PKT_READADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8821C) & BIT_MASK_H2C_PKT_READADDR_8821C) - - +#define BIT_H2C_PKT_READADDR_8821C(x) \ + (((x) & BIT_MASK_H2C_PKT_READADDR_8821C) \ + << BIT_SHIFT_H2C_PKT_READADDR_8821C) +#define BITS_H2C_PKT_READADDR_8821C \ + (BIT_MASK_H2C_PKT_READADDR_8821C << BIT_SHIFT_H2C_PKT_READADDR_8821C) +#define BIT_CLEAR_H2C_PKT_READADDR_8821C(x) \ + ((x) & (~BITS_H2C_PKT_READADDR_8821C)) +#define BIT_GET_H2C_PKT_READADDR_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8821C) & \ + BIT_MASK_H2C_PKT_READADDR_8821C) +#define BIT_SET_H2C_PKT_READADDR_8821C(x, v) \ + (BIT_CLEAR_H2C_PKT_READADDR_8821C(x) | BIT_H2C_PKT_READADDR_8821C(v)) /* 2 REG_H2C_PKT_WRITEADDR_8821C */ #define BIT_SHIFT_H2C_PKT_WRITEADDR_8821C 0 #define BIT_MASK_H2C_PKT_WRITEADDR_8821C 0x3ffff -#define BIT_H2C_PKT_WRITEADDR_8821C(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8821C) << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) -#define BIT_GET_H2C_PKT_WRITEADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) & BIT_MASK_H2C_PKT_WRITEADDR_8821C) - - +#define BIT_H2C_PKT_WRITEADDR_8821C(x) \ + (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8821C) \ + << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) +#define BITS_H2C_PKT_WRITEADDR_8821C \ + (BIT_MASK_H2C_PKT_WRITEADDR_8821C << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) +#define BIT_CLEAR_H2C_PKT_WRITEADDR_8821C(x) \ + ((x) & (~BITS_H2C_PKT_WRITEADDR_8821C)) +#define BIT_GET_H2C_PKT_WRITEADDR_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) & \ + BIT_MASK_H2C_PKT_WRITEADDR_8821C) +#define BIT_SET_H2C_PKT_WRITEADDR_8821C(x, v) \ + (BIT_CLEAR_H2C_PKT_WRITEADDR_8821C(x) | BIT_H2C_PKT_WRITEADDR_8821C(v)) /* 2 REG_MEM_PWR_CRTL_8821C */ #define BIT_MEM_BB_SD_8821C BIT(17) @@ -2002,77 +2931,173 @@ #define BIT_MEM_WLMCU_LS_8821C BIT(1) #define BIT_MEM_WLMCU_DS_8821C BIT(0) -/* 2 REG_FW_DBG0_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG0_8821C 0 -#define BIT_MASK_FW_DBG0_8821C 0xffffffffL -#define BIT_FW_DBG0_8821C(x) (((x) & BIT_MASK_FW_DBG0_8821C) << BIT_SHIFT_FW_DBG0_8821C) -#define BIT_GET_FW_DBG0_8821C(x) (((x) >> BIT_SHIFT_FW_DBG0_8821C) & BIT_MASK_FW_DBG0_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FW_DBG1_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG1_8821C 0 -#define BIT_MASK_FW_DBG1_8821C 0xffffffffL -#define BIT_FW_DBG1_8821C(x) (((x) & BIT_MASK_FW_DBG1_8821C) << BIT_SHIFT_FW_DBG1_8821C) -#define BIT_GET_FW_DBG1_8821C(x) (((x) >> BIT_SHIFT_FW_DBG1_8821C) & BIT_MASK_FW_DBG1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_FW_DBG6_8821C */ -/* 2 REG_FW_DBG2_8821C */ +#define BIT_SHIFT_FW_DBG6_8821C 0 +#define BIT_MASK_FW_DBG6_8821C 0xffffffffL +#define BIT_FW_DBG6_8821C(x) \ + (((x) & BIT_MASK_FW_DBG6_8821C) << BIT_SHIFT_FW_DBG6_8821C) +#define BITS_FW_DBG6_8821C (BIT_MASK_FW_DBG6_8821C << BIT_SHIFT_FW_DBG6_8821C) +#define BIT_CLEAR_FW_DBG6_8821C(x) ((x) & (~BITS_FW_DBG6_8821C)) +#define BIT_GET_FW_DBG6_8821C(x) \ + (((x) >> BIT_SHIFT_FW_DBG6_8821C) & BIT_MASK_FW_DBG6_8821C) +#define BIT_SET_FW_DBG6_8821C(x, v) \ + (BIT_CLEAR_FW_DBG6_8821C(x) | BIT_FW_DBG6_8821C(v)) -#define BIT_SHIFT_FW_DBG2_8821C 0 -#define BIT_MASK_FW_DBG2_8821C 0xffffffffL -#define BIT_FW_DBG2_8821C(x) (((x) & BIT_MASK_FW_DBG2_8821C) << BIT_SHIFT_FW_DBG2_8821C) -#define BIT_GET_FW_DBG2_8821C(x) (((x) >> BIT_SHIFT_FW_DBG2_8821C) & BIT_MASK_FW_DBG2_8821C) +/* 2 REG_FW_DBG7_8821C */ +#define BIT_SHIFT_FW_DBG7_8821C 0 +#define BIT_MASK_FW_DBG7_8821C 0xffffffffL +#define BIT_FW_DBG7_8821C(x) \ + (((x) & BIT_MASK_FW_DBG7_8821C) << BIT_SHIFT_FW_DBG7_8821C) +#define BITS_FW_DBG7_8821C (BIT_MASK_FW_DBG7_8821C << BIT_SHIFT_FW_DBG7_8821C) +#define BIT_CLEAR_FW_DBG7_8821C(x) ((x) & (~BITS_FW_DBG7_8821C)) +#define BIT_GET_FW_DBG7_8821C(x) \ + (((x) >> BIT_SHIFT_FW_DBG7_8821C) & BIT_MASK_FW_DBG7_8821C) +#define BIT_SET_FW_DBG7_8821C(x, v) \ + (BIT_CLEAR_FW_DBG7_8821C(x) | BIT_FW_DBG7_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FW_DBG3_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG3_8821C 0 -#define BIT_MASK_FW_DBG3_8821C 0xffffffffL -#define BIT_FW_DBG3_8821C(x) (((x) & BIT_MASK_FW_DBG3_8821C) << BIT_SHIFT_FW_DBG3_8821C) -#define BIT_GET_FW_DBG3_8821C(x) (((x) >> BIT_SHIFT_FW_DBG3_8821C) & BIT_MASK_FW_DBG3_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FW_DBG4_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG4_8821C 0 -#define BIT_MASK_FW_DBG4_8821C 0xffffffffL -#define BIT_FW_DBG4_8821C(x) (((x) & BIT_MASK_FW_DBG4_8821C) << BIT_SHIFT_FW_DBG4_8821C) -#define BIT_GET_FW_DBG4_8821C(x) (((x) >> BIT_SHIFT_FW_DBG4_8821C) & BIT_MASK_FW_DBG4_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FW_DBG5_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG5_8821C 0 -#define BIT_MASK_FW_DBG5_8821C 0xffffffffL -#define BIT_FW_DBG5_8821C(x) (((x) & BIT_MASK_FW_DBG5_8821C) << BIT_SHIFT_FW_DBG5_8821C) -#define BIT_GET_FW_DBG5_8821C(x) (((x) >> BIT_SHIFT_FW_DBG5_8821C) & BIT_MASK_FW_DBG5_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FW_DBG6_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG6_8821C 0 -#define BIT_MASK_FW_DBG6_8821C 0xffffffffL -#define BIT_FW_DBG6_8821C(x) (((x) & BIT_MASK_FW_DBG6_8821C) << BIT_SHIFT_FW_DBG6_8821C) -#define BIT_GET_FW_DBG6_8821C(x) (((x) >> BIT_SHIFT_FW_DBG6_8821C) & BIT_MASK_FW_DBG6_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FW_DBG7_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG7_8821C 0 -#define BIT_MASK_FW_DBG7_8821C 0xffffffffL -#define BIT_FW_DBG7_8821C(x) (((x) & BIT_MASK_FW_DBG7_8821C) << BIT_SHIFT_FW_DBG7_8821C) -#define BIT_GET_FW_DBG7_8821C(x) (((x) >> BIT_SHIFT_FW_DBG7_8821C) & BIT_MASK_FW_DBG7_8821C) +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -2080,24 +3105,38 @@ #define BIT_SHIFT_LBMODE_8821C 24 #define BIT_MASK_LBMODE_8821C 0x1f -#define BIT_LBMODE_8821C(x) (((x) & BIT_MASK_LBMODE_8821C) << BIT_SHIFT_LBMODE_8821C) -#define BIT_GET_LBMODE_8821C(x) (((x) >> BIT_SHIFT_LBMODE_8821C) & BIT_MASK_LBMODE_8821C) - - +#define BIT_LBMODE_8821C(x) \ + (((x) & BIT_MASK_LBMODE_8821C) << BIT_SHIFT_LBMODE_8821C) +#define BITS_LBMODE_8821C (BIT_MASK_LBMODE_8821C << BIT_SHIFT_LBMODE_8821C) +#define BIT_CLEAR_LBMODE_8821C(x) ((x) & (~BITS_LBMODE_8821C)) +#define BIT_GET_LBMODE_8821C(x) \ + (((x) >> BIT_SHIFT_LBMODE_8821C) & BIT_MASK_LBMODE_8821C) +#define BIT_SET_LBMODE_8821C(x, v) \ + (BIT_CLEAR_LBMODE_8821C(x) | BIT_LBMODE_8821C(v)) #define BIT_SHIFT_NETYPE1_8821C 18 #define BIT_MASK_NETYPE1_8821C 0x3 -#define BIT_NETYPE1_8821C(x) (((x) & BIT_MASK_NETYPE1_8821C) << BIT_SHIFT_NETYPE1_8821C) -#define BIT_GET_NETYPE1_8821C(x) (((x) >> BIT_SHIFT_NETYPE1_8821C) & BIT_MASK_NETYPE1_8821C) - - +#define BIT_NETYPE1_8821C(x) \ + (((x) & BIT_MASK_NETYPE1_8821C) << BIT_SHIFT_NETYPE1_8821C) +#define BITS_NETYPE1_8821C (BIT_MASK_NETYPE1_8821C << BIT_SHIFT_NETYPE1_8821C) +#define BIT_CLEAR_NETYPE1_8821C(x) ((x) & (~BITS_NETYPE1_8821C)) +#define BIT_GET_NETYPE1_8821C(x) \ + (((x) >> BIT_SHIFT_NETYPE1_8821C) & BIT_MASK_NETYPE1_8821C) +#define BIT_SET_NETYPE1_8821C(x, v) \ + (BIT_CLEAR_NETYPE1_8821C(x) | BIT_NETYPE1_8821C(v)) #define BIT_SHIFT_NETYPE0_8821C 16 #define BIT_MASK_NETYPE0_8821C 0x3 -#define BIT_NETYPE0_8821C(x) (((x) & BIT_MASK_NETYPE0_8821C) << BIT_SHIFT_NETYPE0_8821C) -#define BIT_GET_NETYPE0_8821C(x) (((x) >> BIT_SHIFT_NETYPE0_8821C) & BIT_MASK_NETYPE0_8821C) - - +#define BIT_NETYPE0_8821C(x) \ + (((x) & BIT_MASK_NETYPE0_8821C) << BIT_SHIFT_NETYPE0_8821C) +#define BITS_NETYPE0_8821C (BIT_MASK_NETYPE0_8821C << BIT_SHIFT_NETYPE0_8821C) +#define BIT_CLEAR_NETYPE0_8821C(x) ((x) & (~BITS_NETYPE0_8821C)) +#define BIT_GET_NETYPE0_8821C(x) \ + (((x) >> BIT_SHIFT_NETYPE0_8821C) & BIT_MASK_NETYPE0_8821C) +#define BIT_SET_NETYPE0_8821C(x, v) \ + (BIT_CLEAR_NETYPE0_8821C(x) | BIT_NETYPE0_8821C(v)) + +#define BIT_COUNTER_STS_EN_8821C BIT(13) #define BIT_I2C_MAILBOX_EN_8821C BIT(12) #define BIT_SHCUT_EN_8821C BIT(11) #define BIT_32K_CAL_TMR_EN_8821C BIT(10) @@ -2112,62 +3151,127 @@ #define BIT_HCI_RXDMA_EN_8821C BIT(1) #define BIT_HCI_TXDMA_EN_8821C BIT(0) -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_PG_SIZE_8821C */ + +#define BIT_SHIFT_DBG_FIFO_SEL_8821C 16 +#define BIT_MASK_DBG_FIFO_SEL_8821C 0xff +#define BIT_DBG_FIFO_SEL_8821C(x) \ + (((x) & BIT_MASK_DBG_FIFO_SEL_8821C) << BIT_SHIFT_DBG_FIFO_SEL_8821C) +#define BITS_DBG_FIFO_SEL_8821C \ + (BIT_MASK_DBG_FIFO_SEL_8821C << BIT_SHIFT_DBG_FIFO_SEL_8821C) +#define BIT_CLEAR_DBG_FIFO_SEL_8821C(x) ((x) & (~BITS_DBG_FIFO_SEL_8821C)) +#define BIT_GET_DBG_FIFO_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_DBG_FIFO_SEL_8821C) & BIT_MASK_DBG_FIFO_SEL_8821C) +#define BIT_SET_DBG_FIFO_SEL_8821C(x, v) \ + (BIT_CLEAR_DBG_FIFO_SEL_8821C(x) | BIT_DBG_FIFO_SEL_8821C(v)) /* 2 REG_PKT_BUFF_ACCESS_CTRL_8821C */ #define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C 0 #define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C 0xff -#define BIT_PKT_BUFF_ACCESS_CTRL_8821C(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) -#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8821C(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) - - +#define BIT_PKT_BUFF_ACCESS_CTRL_8821C(x) \ + (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) +#define BITS_PKT_BUFF_ACCESS_CTRL_8821C \ + (BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) +#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8821C(x) \ + ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8821C)) +#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8821C(x) \ + (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) & \ + BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) +#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8821C(x, v) \ + (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8821C(x) | \ + BIT_PKT_BUFF_ACCESS_CTRL_8821C(v)) /* 2 REG_TSF_CLK_STATE_8821C */ #define BIT_TSF_CLK_STABLE_8821C BIT(15) /* 2 REG_TXDMA_PQ_MAP_8821C */ +#define BIT_SHIFT_TXDMA_H2C_MAP_8821C 16 +#define BIT_MASK_TXDMA_H2C_MAP_8821C 0x3 +#define BIT_TXDMA_H2C_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_H2C_MAP_8821C) << BIT_SHIFT_TXDMA_H2C_MAP_8821C) +#define BITS_TXDMA_H2C_MAP_8821C \ + (BIT_MASK_TXDMA_H2C_MAP_8821C << BIT_SHIFT_TXDMA_H2C_MAP_8821C) +#define BIT_CLEAR_TXDMA_H2C_MAP_8821C(x) ((x) & (~BITS_TXDMA_H2C_MAP_8821C)) +#define BIT_GET_TXDMA_H2C_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8821C) & BIT_MASK_TXDMA_H2C_MAP_8821C) +#define BIT_SET_TXDMA_H2C_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_H2C_MAP_8821C(x) | BIT_TXDMA_H2C_MAP_8821C(v)) + #define BIT_SHIFT_TXDMA_HIQ_MAP_8821C 14 #define BIT_MASK_TXDMA_HIQ_MAP_8821C 0x3 -#define BIT_TXDMA_HIQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8821C) << BIT_SHIFT_TXDMA_HIQ_MAP_8821C) -#define BIT_GET_TXDMA_HIQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8821C) & BIT_MASK_TXDMA_HIQ_MAP_8821C) - - +#define BIT_TXDMA_HIQ_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP_8821C) << BIT_SHIFT_TXDMA_HIQ_MAP_8821C) +#define BITS_TXDMA_HIQ_MAP_8821C \ + (BIT_MASK_TXDMA_HIQ_MAP_8821C << BIT_SHIFT_TXDMA_HIQ_MAP_8821C) +#define BIT_CLEAR_TXDMA_HIQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8821C)) +#define BIT_GET_TXDMA_HIQ_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8821C) & BIT_MASK_TXDMA_HIQ_MAP_8821C) +#define BIT_SET_TXDMA_HIQ_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP_8821C(x) | BIT_TXDMA_HIQ_MAP_8821C(v)) #define BIT_SHIFT_TXDMA_MGQ_MAP_8821C 12 #define BIT_MASK_TXDMA_MGQ_MAP_8821C 0x3 -#define BIT_TXDMA_MGQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8821C) << BIT_SHIFT_TXDMA_MGQ_MAP_8821C) -#define BIT_GET_TXDMA_MGQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8821C) & BIT_MASK_TXDMA_MGQ_MAP_8821C) - - +#define BIT_TXDMA_MGQ_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP_8821C) << BIT_SHIFT_TXDMA_MGQ_MAP_8821C) +#define BITS_TXDMA_MGQ_MAP_8821C \ + (BIT_MASK_TXDMA_MGQ_MAP_8821C << BIT_SHIFT_TXDMA_MGQ_MAP_8821C) +#define BIT_CLEAR_TXDMA_MGQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8821C)) +#define BIT_GET_TXDMA_MGQ_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8821C) & BIT_MASK_TXDMA_MGQ_MAP_8821C) +#define BIT_SET_TXDMA_MGQ_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP_8821C(x) | BIT_TXDMA_MGQ_MAP_8821C(v)) #define BIT_SHIFT_TXDMA_BKQ_MAP_8821C 10 #define BIT_MASK_TXDMA_BKQ_MAP_8821C 0x3 -#define BIT_TXDMA_BKQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8821C) << BIT_SHIFT_TXDMA_BKQ_MAP_8821C) -#define BIT_GET_TXDMA_BKQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8821C) & BIT_MASK_TXDMA_BKQ_MAP_8821C) - - +#define BIT_TXDMA_BKQ_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP_8821C) << BIT_SHIFT_TXDMA_BKQ_MAP_8821C) +#define BITS_TXDMA_BKQ_MAP_8821C \ + (BIT_MASK_TXDMA_BKQ_MAP_8821C << BIT_SHIFT_TXDMA_BKQ_MAP_8821C) +#define BIT_CLEAR_TXDMA_BKQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8821C)) +#define BIT_GET_TXDMA_BKQ_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8821C) & BIT_MASK_TXDMA_BKQ_MAP_8821C) +#define BIT_SET_TXDMA_BKQ_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP_8821C(x) | BIT_TXDMA_BKQ_MAP_8821C(v)) #define BIT_SHIFT_TXDMA_BEQ_MAP_8821C 8 #define BIT_MASK_TXDMA_BEQ_MAP_8821C 0x3 -#define BIT_TXDMA_BEQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8821C) << BIT_SHIFT_TXDMA_BEQ_MAP_8821C) -#define BIT_GET_TXDMA_BEQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8821C) & BIT_MASK_TXDMA_BEQ_MAP_8821C) - - +#define BIT_TXDMA_BEQ_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP_8821C) << BIT_SHIFT_TXDMA_BEQ_MAP_8821C) +#define BITS_TXDMA_BEQ_MAP_8821C \ + (BIT_MASK_TXDMA_BEQ_MAP_8821C << BIT_SHIFT_TXDMA_BEQ_MAP_8821C) +#define BIT_CLEAR_TXDMA_BEQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8821C)) +#define BIT_GET_TXDMA_BEQ_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8821C) & BIT_MASK_TXDMA_BEQ_MAP_8821C) +#define BIT_SET_TXDMA_BEQ_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP_8821C(x) | BIT_TXDMA_BEQ_MAP_8821C(v)) #define BIT_SHIFT_TXDMA_VIQ_MAP_8821C 6 #define BIT_MASK_TXDMA_VIQ_MAP_8821C 0x3 -#define BIT_TXDMA_VIQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8821C) << BIT_SHIFT_TXDMA_VIQ_MAP_8821C) -#define BIT_GET_TXDMA_VIQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8821C) & BIT_MASK_TXDMA_VIQ_MAP_8821C) - - +#define BIT_TXDMA_VIQ_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP_8821C) << BIT_SHIFT_TXDMA_VIQ_MAP_8821C) +#define BITS_TXDMA_VIQ_MAP_8821C \ + (BIT_MASK_TXDMA_VIQ_MAP_8821C << BIT_SHIFT_TXDMA_VIQ_MAP_8821C) +#define BIT_CLEAR_TXDMA_VIQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8821C)) +#define BIT_GET_TXDMA_VIQ_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8821C) & BIT_MASK_TXDMA_VIQ_MAP_8821C) +#define BIT_SET_TXDMA_VIQ_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP_8821C(x) | BIT_TXDMA_VIQ_MAP_8821C(v)) #define BIT_SHIFT_TXDMA_VOQ_MAP_8821C 4 #define BIT_MASK_TXDMA_VOQ_MAP_8821C 0x3 -#define BIT_TXDMA_VOQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8821C) << BIT_SHIFT_TXDMA_VOQ_MAP_8821C) -#define BIT_GET_TXDMA_VOQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8821C) & BIT_MASK_TXDMA_VOQ_MAP_8821C) - +#define BIT_TXDMA_VOQ_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP_8821C) << BIT_SHIFT_TXDMA_VOQ_MAP_8821C) +#define BITS_TXDMA_VOQ_MAP_8821C \ + (BIT_MASK_TXDMA_VOQ_MAP_8821C << BIT_SHIFT_TXDMA_VOQ_MAP_8821C) +#define BIT_CLEAR_TXDMA_VOQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8821C)) +#define BIT_GET_TXDMA_VOQ_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8821C) & BIT_MASK_TXDMA_VOQ_MAP_8821C) +#define BIT_SET_TXDMA_VOQ_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP_8821C(x) | BIT_TXDMA_VOQ_MAP_8821C(v)) #define BIT_RXDMA_AGG_EN_8821C BIT(2) #define BIT_RXSHFT_EN_8821C BIT(1) @@ -2179,17 +3283,17 @@ #define BIT_SHIFT_RXFFOVFL_RSV_V2_8821C 8 #define BIT_MASK_RXFFOVFL_RSV_V2_8821C 0xf -#define BIT_RXFFOVFL_RSV_V2_8821C(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8821C) << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) -#define BIT_GET_RXFFOVFL_RSV_V2_8821C(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) & BIT_MASK_RXFFOVFL_RSV_V2_8821C) - - - -#define BIT_SHIFT_TXPKTBUF_PGBNDY_8821C 0 -#define BIT_MASK_TXPKTBUF_PGBNDY_8821C 0xff -#define BIT_TXPKTBUF_PGBNDY_8821C(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8821C) << BIT_SHIFT_TXPKTBUF_PGBNDY_8821C) -#define BIT_GET_TXPKTBUF_PGBNDY_8821C(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8821C) & BIT_MASK_TXPKTBUF_PGBNDY_8821C) - - +#define BIT_RXFFOVFL_RSV_V2_8821C(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8821C) \ + << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) +#define BITS_RXFFOVFL_RSV_V2_8821C \ + (BIT_MASK_RXFFOVFL_RSV_V2_8821C << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) +#define BIT_CLEAR_RXFFOVFL_RSV_V2_8821C(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8821C)) +#define BIT_GET_RXFFOVFL_RSV_V2_8821C(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) & \ + BIT_MASK_RXFFOVFL_RSV_V2_8821C) +#define BIT_SET_RXFFOVFL_RSV_V2_8821C(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V2_8821C(x) | BIT_RXFFOVFL_RSV_V2_8821C(v)) /* 2 REG_PTA_I2C_MBOX_8821C */ @@ -2197,24 +3301,44 @@ #define BIT_SHIFT_I2C_M_STATUS_8821C 8 #define BIT_MASK_I2C_M_STATUS_8821C 0xf -#define BIT_I2C_M_STATUS_8821C(x) (((x) & BIT_MASK_I2C_M_STATUS_8821C) << BIT_SHIFT_I2C_M_STATUS_8821C) -#define BIT_GET_I2C_M_STATUS_8821C(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8821C) & BIT_MASK_I2C_M_STATUS_8821C) - - +#define BIT_I2C_M_STATUS_8821C(x) \ + (((x) & BIT_MASK_I2C_M_STATUS_8821C) << BIT_SHIFT_I2C_M_STATUS_8821C) +#define BITS_I2C_M_STATUS_8821C \ + (BIT_MASK_I2C_M_STATUS_8821C << BIT_SHIFT_I2C_M_STATUS_8821C) +#define BIT_CLEAR_I2C_M_STATUS_8821C(x) ((x) & (~BITS_I2C_M_STATUS_8821C)) +#define BIT_GET_I2C_M_STATUS_8821C(x) \ + (((x) >> BIT_SHIFT_I2C_M_STATUS_8821C) & BIT_MASK_I2C_M_STATUS_8821C) +#define BIT_SET_I2C_M_STATUS_8821C(x, v) \ + (BIT_CLEAR_I2C_M_STATUS_8821C(x) | BIT_I2C_M_STATUS_8821C(v)) #define BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C 4 #define BIT_MASK_I2C_M_BUS_GNT_FW_8821C 0x7 -#define BIT_I2C_M_BUS_GNT_FW_8821C(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) -#define BIT_GET_I2C_M_BUS_GNT_FW_8821C(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C) - +#define BIT_I2C_M_BUS_GNT_FW_8821C(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C) \ + << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) +#define BITS_I2C_M_BUS_GNT_FW_8821C \ + (BIT_MASK_I2C_M_BUS_GNT_FW_8821C << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8821C(x) \ + ((x) & (~BITS_I2C_M_BUS_GNT_FW_8821C)) +#define BIT_GET_I2C_M_BUS_GNT_FW_8821C(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) & \ + BIT_MASK_I2C_M_BUS_GNT_FW_8821C) +#define BIT_SET_I2C_M_BUS_GNT_FW_8821C(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT_FW_8821C(x) | BIT_I2C_M_BUS_GNT_FW_8821C(v)) #define BIT_I2C_M_GNT_FW_8821C BIT(3) #define BIT_SHIFT_I2C_M_SPEED_8821C 1 #define BIT_MASK_I2C_M_SPEED_8821C 0x3 -#define BIT_I2C_M_SPEED_8821C(x) (((x) & BIT_MASK_I2C_M_SPEED_8821C) << BIT_SHIFT_I2C_M_SPEED_8821C) -#define BIT_GET_I2C_M_SPEED_8821C(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8821C) & BIT_MASK_I2C_M_SPEED_8821C) - +#define BIT_I2C_M_SPEED_8821C(x) \ + (((x) & BIT_MASK_I2C_M_SPEED_8821C) << BIT_SHIFT_I2C_M_SPEED_8821C) +#define BITS_I2C_M_SPEED_8821C \ + (BIT_MASK_I2C_M_SPEED_8821C << BIT_SHIFT_I2C_M_SPEED_8821C) +#define BIT_CLEAR_I2C_M_SPEED_8821C(x) ((x) & (~BITS_I2C_M_SPEED_8821C)) +#define BIT_GET_I2C_M_SPEED_8821C(x) \ + (((x) >> BIT_SHIFT_I2C_M_SPEED_8821C) & BIT_MASK_I2C_M_SPEED_8821C) +#define BIT_SET_I2C_M_SPEED_8821C(x, v) \ + (BIT_CLEAR_I2C_M_SPEED_8821C(x) | BIT_I2C_M_SPEED_8821C(v)) #define BIT_I2C_M_UNLOCK_8821C BIT(0) @@ -2224,10 +3348,15 @@ #define BIT_SHIFT_RXFF0_BNDY_V2_8821C 0 #define BIT_MASK_RXFF0_BNDY_V2_8821C 0x3ffff -#define BIT_RXFF0_BNDY_V2_8821C(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8821C) << BIT_SHIFT_RXFF0_BNDY_V2_8821C) -#define BIT_GET_RXFF0_BNDY_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8821C) & BIT_MASK_RXFF0_BNDY_V2_8821C) - - +#define BIT_RXFF0_BNDY_V2_8821C(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V2_8821C) << BIT_SHIFT_RXFF0_BNDY_V2_8821C) +#define BITS_RXFF0_BNDY_V2_8821C \ + (BIT_MASK_RXFF0_BNDY_V2_8821C << BIT_SHIFT_RXFF0_BNDY_V2_8821C) +#define BIT_CLEAR_RXFF0_BNDY_V2_8821C(x) ((x) & (~BITS_RXFF0_BNDY_V2_8821C)) +#define BIT_GET_RXFF0_BNDY_V2_8821C(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8821C) & BIT_MASK_RXFF0_BNDY_V2_8821C) +#define BIT_SET_RXFF0_BNDY_V2_8821C(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V2_8821C(x) | BIT_RXFF0_BNDY_V2_8821C(v)) /* 2 REG_FE1IMR_8821C */ #define BIT_FS_RXDMA2_DONE_INT_EN_8821C BIT(28) @@ -2294,10 +3423,15 @@ #define BIT_SHIFT_CPWM_MOD_8821C 24 #define BIT_MASK_CPWM_MOD_8821C 0x7f -#define BIT_CPWM_MOD_8821C(x) (((x) & BIT_MASK_CPWM_MOD_8821C) << BIT_SHIFT_CPWM_MOD_8821C) -#define BIT_GET_CPWM_MOD_8821C(x) (((x) >> BIT_SHIFT_CPWM_MOD_8821C) & BIT_MASK_CPWM_MOD_8821C) - - +#define BIT_CPWM_MOD_8821C(x) \ + (((x) & BIT_MASK_CPWM_MOD_8821C) << BIT_SHIFT_CPWM_MOD_8821C) +#define BITS_CPWM_MOD_8821C \ + (BIT_MASK_CPWM_MOD_8821C << BIT_SHIFT_CPWM_MOD_8821C) +#define BIT_CLEAR_CPWM_MOD_8821C(x) ((x) & (~BITS_CPWM_MOD_8821C)) +#define BIT_GET_CPWM_MOD_8821C(x) \ + (((x) >> BIT_SHIFT_CPWM_MOD_8821C) & BIT_MASK_CPWM_MOD_8821C) +#define BIT_SET_CPWM_MOD_8821C(x, v) \ + (BIT_CLEAR_CPWM_MOD_8821C(x) | BIT_CPWM_MOD_8821C(v)) /* 2 REG_FWIMR_8821C */ #define BIT_FS_TXBCNOK_MB7_INT_EN_8821C BIT(31) @@ -2415,9 +3549,17 @@ #define BIT_SHIFT_PKTBUF_WRITE_EN_8821C 24 #define BIT_MASK_PKTBUF_WRITE_EN_8821C 0xff -#define BIT_PKTBUF_WRITE_EN_8821C(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8821C) << BIT_SHIFT_PKTBUF_WRITE_EN_8821C) -#define BIT_GET_PKTBUF_WRITE_EN_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8821C) & BIT_MASK_PKTBUF_WRITE_EN_8821C) - +#define BIT_PKTBUF_WRITE_EN_8821C(x) \ + (((x) & BIT_MASK_PKTBUF_WRITE_EN_8821C) \ + << BIT_SHIFT_PKTBUF_WRITE_EN_8821C) +#define BITS_PKTBUF_WRITE_EN_8821C \ + (BIT_MASK_PKTBUF_WRITE_EN_8821C << BIT_SHIFT_PKTBUF_WRITE_EN_8821C) +#define BIT_CLEAR_PKTBUF_WRITE_EN_8821C(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8821C)) +#define BIT_GET_PKTBUF_WRITE_EN_8821C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8821C) & \ + BIT_MASK_PKTBUF_WRITE_EN_8821C) +#define BIT_SET_PKTBUF_WRITE_EN_8821C(x, v) \ + (BIT_CLEAR_PKTBUF_WRITE_EN_8821C(x) | BIT_PKTBUF_WRITE_EN_8821C(v)) #define BIT_TXRPTBUF_DBG_8821C BIT(23) @@ -2427,45 +3569,81 @@ #define BIT_SHIFT_PKTBUF_DBG_ADDR_8821C 0 #define BIT_MASK_PKTBUF_DBG_ADDR_8821C 0x1fff -#define BIT_PKTBUF_DBG_ADDR_8821C(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8821C) << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) -#define BIT_GET_PKTBUF_DBG_ADDR_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) & BIT_MASK_PKTBUF_DBG_ADDR_8821C) - - +#define BIT_PKTBUF_DBG_ADDR_8821C(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8821C) \ + << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) +#define BITS_PKTBUF_DBG_ADDR_8821C \ + (BIT_MASK_PKTBUF_DBG_ADDR_8821C << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) +#define BIT_CLEAR_PKTBUF_DBG_ADDR_8821C(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8821C)) +#define BIT_GET_PKTBUF_DBG_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) & \ + BIT_MASK_PKTBUF_DBG_ADDR_8821C) +#define BIT_SET_PKTBUF_DBG_ADDR_8821C(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_ADDR_8821C(x) | BIT_PKTBUF_DBG_ADDR_8821C(v)) /* 2 REG_PKTBUF_DBG_DATA_L_8821C */ #define BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C 0 #define BIT_MASK_PKTBUF_DBG_DATA_L_8821C 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_L_8821C(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) -#define BIT_GET_PKTBUF_DBG_DATA_L_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C) - - +#define BIT_PKTBUF_DBG_DATA_L_8821C(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) +#define BITS_PKTBUF_DBG_DATA_L_8821C \ + (BIT_MASK_PKTBUF_DBG_DATA_L_8821C << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8821C(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_L_8821C)) +#define BIT_GET_PKTBUF_DBG_DATA_L_8821C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) & \ + BIT_MASK_PKTBUF_DBG_DATA_L_8821C) +#define BIT_SET_PKTBUF_DBG_DATA_L_8821C(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_L_8821C(x) | BIT_PKTBUF_DBG_DATA_L_8821C(v)) /* 2 REG_PKTBUF_DBG_DATA_H_8821C */ #define BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C 0 #define BIT_MASK_PKTBUF_DBG_DATA_H_8821C 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_H_8821C(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) -#define BIT_GET_PKTBUF_DBG_DATA_H_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C) - - +#define BIT_PKTBUF_DBG_DATA_H_8821C(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) +#define BITS_PKTBUF_DBG_DATA_H_8821C \ + (BIT_MASK_PKTBUF_DBG_DATA_H_8821C << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8821C(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_H_8821C)) +#define BIT_GET_PKTBUF_DBG_DATA_H_8821C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) & \ + BIT_MASK_PKTBUF_DBG_DATA_H_8821C) +#define BIT_SET_PKTBUF_DBG_DATA_H_8821C(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_H_8821C(x) | BIT_PKTBUF_DBG_DATA_H_8821C(v)) /* 2 REG_CPWM2_8821C */ #define BIT_SHIFT_L0S_TO_RCVY_NUM_8821C 16 #define BIT_MASK_L0S_TO_RCVY_NUM_8821C 0xff -#define BIT_L0S_TO_RCVY_NUM_8821C(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8821C) << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) -#define BIT_GET_L0S_TO_RCVY_NUM_8821C(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) & BIT_MASK_L0S_TO_RCVY_NUM_8821C) - +#define BIT_L0S_TO_RCVY_NUM_8821C(x) \ + (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8821C) \ + << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) +#define BITS_L0S_TO_RCVY_NUM_8821C \ + (BIT_MASK_L0S_TO_RCVY_NUM_8821C << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) +#define BIT_CLEAR_L0S_TO_RCVY_NUM_8821C(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8821C)) +#define BIT_GET_L0S_TO_RCVY_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) & \ + BIT_MASK_L0S_TO_RCVY_NUM_8821C) +#define BIT_SET_L0S_TO_RCVY_NUM_8821C(x, v) \ + (BIT_CLEAR_L0S_TO_RCVY_NUM_8821C(x) | BIT_L0S_TO_RCVY_NUM_8821C(v)) #define BIT_CPWM2_TOGGLING_8821C BIT(15) #define BIT_SHIFT_CPWM2_MOD_8821C 0 #define BIT_MASK_CPWM2_MOD_8821C 0x7fff -#define BIT_CPWM2_MOD_8821C(x) (((x) & BIT_MASK_CPWM2_MOD_8821C) << BIT_SHIFT_CPWM2_MOD_8821C) -#define BIT_GET_CPWM2_MOD_8821C(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8821C) & BIT_MASK_CPWM2_MOD_8821C) - - +#define BIT_CPWM2_MOD_8821C(x) \ + (((x) & BIT_MASK_CPWM2_MOD_8821C) << BIT_SHIFT_CPWM2_MOD_8821C) +#define BITS_CPWM2_MOD_8821C \ + (BIT_MASK_CPWM2_MOD_8821C << BIT_SHIFT_CPWM2_MOD_8821C) +#define BIT_CLEAR_CPWM2_MOD_8821C(x) ((x) & (~BITS_CPWM2_MOD_8821C)) +#define BIT_GET_CPWM2_MOD_8821C(x) \ + (((x) >> BIT_SHIFT_CPWM2_MOD_8821C) & BIT_MASK_CPWM2_MOD_8821C) +#define BIT_SET_CPWM2_MOD_8821C(x, v) \ + (BIT_CLEAR_CPWM2_MOD_8821C(x) | BIT_CPWM2_MOD_8821C(v)) /* 2 REG_TC0_CTRL_8821C */ #define BIT_TC0INT_EN_8821C BIT(26) @@ -2474,10 +3652,14 @@ #define BIT_SHIFT_TC0DATA_8821C 0 #define BIT_MASK_TC0DATA_8821C 0xffffff -#define BIT_TC0DATA_8821C(x) (((x) & BIT_MASK_TC0DATA_8821C) << BIT_SHIFT_TC0DATA_8821C) -#define BIT_GET_TC0DATA_8821C(x) (((x) >> BIT_SHIFT_TC0DATA_8821C) & BIT_MASK_TC0DATA_8821C) - - +#define BIT_TC0DATA_8821C(x) \ + (((x) & BIT_MASK_TC0DATA_8821C) << BIT_SHIFT_TC0DATA_8821C) +#define BITS_TC0DATA_8821C (BIT_MASK_TC0DATA_8821C << BIT_SHIFT_TC0DATA_8821C) +#define BIT_CLEAR_TC0DATA_8821C(x) ((x) & (~BITS_TC0DATA_8821C)) +#define BIT_GET_TC0DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC0DATA_8821C) & BIT_MASK_TC0DATA_8821C) +#define BIT_SET_TC0DATA_8821C(x, v) \ + (BIT_CLEAR_TC0DATA_8821C(x) | BIT_TC0DATA_8821C(v)) /* 2 REG_TC1_CTRL_8821C */ #define BIT_TC1INT_EN_8821C BIT(26) @@ -2486,10 +3668,14 @@ #define BIT_SHIFT_TC1DATA_8821C 0 #define BIT_MASK_TC1DATA_8821C 0xffffff -#define BIT_TC1DATA_8821C(x) (((x) & BIT_MASK_TC1DATA_8821C) << BIT_SHIFT_TC1DATA_8821C) -#define BIT_GET_TC1DATA_8821C(x) (((x) >> BIT_SHIFT_TC1DATA_8821C) & BIT_MASK_TC1DATA_8821C) - - +#define BIT_TC1DATA_8821C(x) \ + (((x) & BIT_MASK_TC1DATA_8821C) << BIT_SHIFT_TC1DATA_8821C) +#define BITS_TC1DATA_8821C (BIT_MASK_TC1DATA_8821C << BIT_SHIFT_TC1DATA_8821C) +#define BIT_CLEAR_TC1DATA_8821C(x) ((x) & (~BITS_TC1DATA_8821C)) +#define BIT_GET_TC1DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC1DATA_8821C) & BIT_MASK_TC1DATA_8821C) +#define BIT_SET_TC1DATA_8821C(x, v) \ + (BIT_CLEAR_TC1DATA_8821C(x) | BIT_TC1DATA_8821C(v)) /* 2 REG_TC2_CTRL_8821C */ #define BIT_TC2INT_EN_8821C BIT(26) @@ -2498,10 +3684,14 @@ #define BIT_SHIFT_TC2DATA_8821C 0 #define BIT_MASK_TC2DATA_8821C 0xffffff -#define BIT_TC2DATA_8821C(x) (((x) & BIT_MASK_TC2DATA_8821C) << BIT_SHIFT_TC2DATA_8821C) -#define BIT_GET_TC2DATA_8821C(x) (((x) >> BIT_SHIFT_TC2DATA_8821C) & BIT_MASK_TC2DATA_8821C) - - +#define BIT_TC2DATA_8821C(x) \ + (((x) & BIT_MASK_TC2DATA_8821C) << BIT_SHIFT_TC2DATA_8821C) +#define BITS_TC2DATA_8821C (BIT_MASK_TC2DATA_8821C << BIT_SHIFT_TC2DATA_8821C) +#define BIT_CLEAR_TC2DATA_8821C(x) ((x) & (~BITS_TC2DATA_8821C)) +#define BIT_GET_TC2DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC2DATA_8821C) & BIT_MASK_TC2DATA_8821C) +#define BIT_SET_TC2DATA_8821C(x, v) \ + (BIT_CLEAR_TC2DATA_8821C(x) | BIT_TC2DATA_8821C(v)) /* 2 REG_TC3_CTRL_8821C */ #define BIT_TC3INT_EN_8821C BIT(26) @@ -2510,10 +3700,14 @@ #define BIT_SHIFT_TC3DATA_8821C 0 #define BIT_MASK_TC3DATA_8821C 0xffffff -#define BIT_TC3DATA_8821C(x) (((x) & BIT_MASK_TC3DATA_8821C) << BIT_SHIFT_TC3DATA_8821C) -#define BIT_GET_TC3DATA_8821C(x) (((x) >> BIT_SHIFT_TC3DATA_8821C) & BIT_MASK_TC3DATA_8821C) - - +#define BIT_TC3DATA_8821C(x) \ + (((x) & BIT_MASK_TC3DATA_8821C) << BIT_SHIFT_TC3DATA_8821C) +#define BITS_TC3DATA_8821C (BIT_MASK_TC3DATA_8821C << BIT_SHIFT_TC3DATA_8821C) +#define BIT_CLEAR_TC3DATA_8821C(x) ((x) & (~BITS_TC3DATA_8821C)) +#define BIT_GET_TC3DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC3DATA_8821C) & BIT_MASK_TC3DATA_8821C) +#define BIT_SET_TC3DATA_8821C(x, v) \ + (BIT_CLEAR_TC3DATA_8821C(x) | BIT_TC3DATA_8821C(v)) /* 2 REG_TC4_CTRL_8821C */ #define BIT_TC4INT_EN_8821C BIT(26) @@ -2522,19 +3716,28 @@ #define BIT_SHIFT_TC4DATA_8821C 0 #define BIT_MASK_TC4DATA_8821C 0xffffff -#define BIT_TC4DATA_8821C(x) (((x) & BIT_MASK_TC4DATA_8821C) << BIT_SHIFT_TC4DATA_8821C) -#define BIT_GET_TC4DATA_8821C(x) (((x) >> BIT_SHIFT_TC4DATA_8821C) & BIT_MASK_TC4DATA_8821C) - - +#define BIT_TC4DATA_8821C(x) \ + (((x) & BIT_MASK_TC4DATA_8821C) << BIT_SHIFT_TC4DATA_8821C) +#define BITS_TC4DATA_8821C (BIT_MASK_TC4DATA_8821C << BIT_SHIFT_TC4DATA_8821C) +#define BIT_CLEAR_TC4DATA_8821C(x) ((x) & (~BITS_TC4DATA_8821C)) +#define BIT_GET_TC4DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC4DATA_8821C) & BIT_MASK_TC4DATA_8821C) +#define BIT_SET_TC4DATA_8821C(x, v) \ + (BIT_CLEAR_TC4DATA_8821C(x) | BIT_TC4DATA_8821C(v)) /* 2 REG_TCUNIT_BASE_8821C */ #define BIT_SHIFT_TCUNIT_BASE_8821C 0 #define BIT_MASK_TCUNIT_BASE_8821C 0x3fff -#define BIT_TCUNIT_BASE_8821C(x) (((x) & BIT_MASK_TCUNIT_BASE_8821C) << BIT_SHIFT_TCUNIT_BASE_8821C) -#define BIT_GET_TCUNIT_BASE_8821C(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8821C) & BIT_MASK_TCUNIT_BASE_8821C) - - +#define BIT_TCUNIT_BASE_8821C(x) \ + (((x) & BIT_MASK_TCUNIT_BASE_8821C) << BIT_SHIFT_TCUNIT_BASE_8821C) +#define BITS_TCUNIT_BASE_8821C \ + (BIT_MASK_TCUNIT_BASE_8821C << BIT_SHIFT_TCUNIT_BASE_8821C) +#define BIT_CLEAR_TCUNIT_BASE_8821C(x) ((x) & (~BITS_TCUNIT_BASE_8821C)) +#define BIT_GET_TCUNIT_BASE_8821C(x) \ + (((x) >> BIT_SHIFT_TCUNIT_BASE_8821C) & BIT_MASK_TCUNIT_BASE_8821C) +#define BIT_SET_TCUNIT_BASE_8821C(x, v) \ + (BIT_CLEAR_TCUNIT_BASE_8821C(x) | BIT_TCUNIT_BASE_8821C(v)) /* 2 REG_TC5_CTRL_8821C */ #define BIT_TC5INT_EN_8821C BIT(26) @@ -2543,10 +3746,14 @@ #define BIT_SHIFT_TC5DATA_8821C 0 #define BIT_MASK_TC5DATA_8821C 0xffffff -#define BIT_TC5DATA_8821C(x) (((x) & BIT_MASK_TC5DATA_8821C) << BIT_SHIFT_TC5DATA_8821C) -#define BIT_GET_TC5DATA_8821C(x) (((x) >> BIT_SHIFT_TC5DATA_8821C) & BIT_MASK_TC5DATA_8821C) - - +#define BIT_TC5DATA_8821C(x) \ + (((x) & BIT_MASK_TC5DATA_8821C) << BIT_SHIFT_TC5DATA_8821C) +#define BITS_TC5DATA_8821C (BIT_MASK_TC5DATA_8821C << BIT_SHIFT_TC5DATA_8821C) +#define BIT_CLEAR_TC5DATA_8821C(x) ((x) & (~BITS_TC5DATA_8821C)) +#define BIT_GET_TC5DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC5DATA_8821C) & BIT_MASK_TC5DATA_8821C) +#define BIT_SET_TC5DATA_8821C(x, v) \ + (BIT_CLEAR_TC5DATA_8821C(x) | BIT_TC5DATA_8821C(v)) /* 2 REG_TC6_CTRL_8821C */ #define BIT_TC6INT_EN_8821C BIT(26) @@ -2555,127 +3762,267 @@ #define BIT_SHIFT_TC6DATA_8821C 0 #define BIT_MASK_TC6DATA_8821C 0xffffff -#define BIT_TC6DATA_8821C(x) (((x) & BIT_MASK_TC6DATA_8821C) << BIT_SHIFT_TC6DATA_8821C) -#define BIT_GET_TC6DATA_8821C(x) (((x) >> BIT_SHIFT_TC6DATA_8821C) & BIT_MASK_TC6DATA_8821C) - - - -/* 2 REG_MBIST_FAIL_8821C */ - -#define BIT_SHIFT_8051_MBIST_FAIL_8821C 26 -#define BIT_MASK_8051_MBIST_FAIL_8821C 0x7 -#define BIT_8051_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8821C) << BIT_SHIFT_8051_MBIST_FAIL_8821C) -#define BIT_GET_8051_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8821C) & BIT_MASK_8051_MBIST_FAIL_8821C) - - - -#define BIT_SHIFT_USB_MBIST_FAIL_8821C 24 -#define BIT_MASK_USB_MBIST_FAIL_8821C 0x3 -#define BIT_USB_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8821C) << BIT_SHIFT_USB_MBIST_FAIL_8821C) -#define BIT_GET_USB_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8821C) & BIT_MASK_USB_MBIST_FAIL_8821C) - - - -#define BIT_SHIFT_PCIE_MBIST_FAIL_8821C 16 -#define BIT_MASK_PCIE_MBIST_FAIL_8821C 0x3f -#define BIT_PCIE_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8821C) << BIT_SHIFT_PCIE_MBIST_FAIL_8821C) -#define BIT_GET_PCIE_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8821C) & BIT_MASK_PCIE_MBIST_FAIL_8821C) - - - -#define BIT_SHIFT_MAC_MBIST_FAIL_8821C 0 -#define BIT_MASK_MAC_MBIST_FAIL_8821C 0xfff -#define BIT_MAC_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_8821C) << BIT_SHIFT_MAC_MBIST_FAIL_8821C) -#define BIT_GET_MAC_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8821C) & BIT_MASK_MAC_MBIST_FAIL_8821C) - - +#define BIT_TC6DATA_8821C(x) \ + (((x) & BIT_MASK_TC6DATA_8821C) << BIT_SHIFT_TC6DATA_8821C) +#define BITS_TC6DATA_8821C (BIT_MASK_TC6DATA_8821C << BIT_SHIFT_TC6DATA_8821C) +#define BIT_CLEAR_TC6DATA_8821C(x) ((x) & (~BITS_TC6DATA_8821C)) +#define BIT_GET_TC6DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC6DATA_8821C) & BIT_MASK_TC6DATA_8821C) +#define BIT_SET_TC6DATA_8821C(x, v) \ + (BIT_CLEAR_TC6DATA_8821C(x) | BIT_TC6DATA_8821C(v)) + +/* 2 REG_MBIST_DRF_FAIL_8821C */ + +#define BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C 26 +#define BIT_MASK_8051_MBIST_DRF_FAIL_8821C 0x3f +#define BIT_8051_MBIST_DRF_FAIL_8821C(x) \ + (((x) & BIT_MASK_8051_MBIST_DRF_FAIL_8821C) \ + << BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C) +#define BITS_8051_MBIST_DRF_FAIL_8821C \ + (BIT_MASK_8051_MBIST_DRF_FAIL_8821C \ + << BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C) +#define BIT_CLEAR_8051_MBIST_DRF_FAIL_8821C(x) \ + ((x) & (~BITS_8051_MBIST_DRF_FAIL_8821C)) +#define BIT_GET_8051_MBIST_DRF_FAIL_8821C(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C) & \ + BIT_MASK_8051_MBIST_DRF_FAIL_8821C) +#define BIT_SET_8051_MBIST_DRF_FAIL_8821C(x, v) \ + (BIT_CLEAR_8051_MBIST_DRF_FAIL_8821C(x) | \ + BIT_8051_MBIST_DRF_FAIL_8821C(v)) + +#define BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C 24 +#define BIT_MASK_USB_MBIST_DRF_FAIL_8821C 0x3 +#define BIT_USB_MBIST_DRF_FAIL_8821C(x) \ + (((x) & BIT_MASK_USB_MBIST_DRF_FAIL_8821C) \ + << BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C) +#define BITS_USB_MBIST_DRF_FAIL_8821C \ + (BIT_MASK_USB_MBIST_DRF_FAIL_8821C \ + << BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C) +#define BIT_CLEAR_USB_MBIST_DRF_FAIL_8821C(x) \ + ((x) & (~BITS_USB_MBIST_DRF_FAIL_8821C)) +#define BIT_GET_USB_MBIST_DRF_FAIL_8821C(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C) & \ + BIT_MASK_USB_MBIST_DRF_FAIL_8821C) +#define BIT_SET_USB_MBIST_DRF_FAIL_8821C(x, v) \ + (BIT_CLEAR_USB_MBIST_DRF_FAIL_8821C(x) | \ + BIT_USB_MBIST_DRF_FAIL_8821C(v)) + +#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C 18 +#define BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C 0x3f +#define BIT_PCIE_MBIST_DRF_FAIL_8821C(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C) \ + << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C) +#define BITS_PCIE_MBIST_DRF_FAIL_8821C \ + (BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C \ + << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C) +#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8821C(x) \ + ((x) & (~BITS_PCIE_MBIST_DRF_FAIL_8821C)) +#define BIT_GET_PCIE_MBIST_DRF_FAIL_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C) & \ + BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C) +#define BIT_SET_PCIE_MBIST_DRF_FAIL_8821C(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8821C(x) | \ + BIT_PCIE_MBIST_DRF_FAIL_8821C(v)) + +#define BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C 0 +#define BIT_MASK_MAC_MBIST_DRF_FAIL_8821C 0x3ffff +#define BIT_MAC_MBIST_DRF_FAIL_8821C(x) \ + (((x) & BIT_MASK_MAC_MBIST_DRF_FAIL_8821C) \ + << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C) +#define BITS_MAC_MBIST_DRF_FAIL_8821C \ + (BIT_MASK_MAC_MBIST_DRF_FAIL_8821C \ + << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C) +#define BIT_CLEAR_MAC_MBIST_DRF_FAIL_8821C(x) \ + ((x) & (~BITS_MAC_MBIST_DRF_FAIL_8821C)) +#define BIT_GET_MAC_MBIST_DRF_FAIL_8821C(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C) & \ + BIT_MASK_MAC_MBIST_DRF_FAIL_8821C) +#define BIT_SET_MAC_MBIST_DRF_FAIL_8821C(x, v) \ + (BIT_CLEAR_MAC_MBIST_DRF_FAIL_8821C(x) | \ + BIT_MAC_MBIST_DRF_FAIL_8821C(v)) /* 2 REG_MBIST_START_PAUSE_8821C */ -#define BIT_SHIFT_8051_MBIST_START_PAUSE_8821C 26 -#define BIT_MASK_8051_MBIST_START_PAUSE_8821C 0x7 -#define BIT_8051_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8821C) << BIT_SHIFT_8051_MBIST_START_PAUSE_8821C) -#define BIT_GET_8051_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8821C) & BIT_MASK_8051_MBIST_START_PAUSE_8821C) - - - -#define BIT_SHIFT_USB_MBIST_START_PAUSE_8821C 24 -#define BIT_MASK_USB_MBIST_START_PAUSE_8821C 0x3 -#define BIT_USB_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8821C) << BIT_SHIFT_USB_MBIST_START_PAUSE_8821C) -#define BIT_GET_USB_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8821C) & BIT_MASK_USB_MBIST_START_PAUSE_8821C) - - - -#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C 16 -#define BIT_MASK_PCIE_MBIST_START_PAUSE_8821C 0x3f -#define BIT_PCIE_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8821C) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C) -#define BIT_GET_PCIE_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C) & BIT_MASK_PCIE_MBIST_START_PAUSE_8821C) - - - -#define BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C 0 -#define BIT_MASK_MAC_MBIST_START_PAUSE_8821C 0xfff -#define BIT_MAC_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8821C) << BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C) -#define BIT_GET_MAC_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C) & BIT_MASK_MAC_MBIST_START_PAUSE_8821C) - - +#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C 26 +#define BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C 0x3f +#define BIT_8051_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C) \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C) +#define BITS_8051_MBIST_START_PAUSE_V1_8821C \ + (BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C) +#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8821C(x) \ + ((x) & (~BITS_8051_MBIST_START_PAUSE_V1_8821C)) +#define BIT_GET_8051_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C) & \ + BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C) +#define BIT_SET_8051_MBIST_START_PAUSE_V1_8821C(x, v) \ + (BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8821C(x) | \ + BIT_8051_MBIST_START_PAUSE_V1_8821C(v)) + +#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C 24 +#define BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C 0x3 +#define BIT_USB_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C) +#define BITS_USB_MBIST_START_PAUSE_V1_8821C \ + (BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C) +#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8821C(x) \ + ((x) & (~BITS_USB_MBIST_START_PAUSE_V1_8821C)) +#define BIT_GET_USB_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C) & \ + BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C) +#define BIT_SET_USB_MBIST_START_PAUSE_V1_8821C(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8821C(x) | \ + BIT_USB_MBIST_START_PAUSE_V1_8821C(v)) + +#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C 18 +#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C 0x3f +#define BIT_PCIE_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C) +#define BITS_PCIE_MBIST_START_PAUSE_V1_8821C \ + (BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8821C(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1_8821C)) +#define BIT_GET_PCIE_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C) +#define BIT_SET_PCIE_MBIST_START_PAUSE_V1_8821C(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8821C(x) | \ + BIT_PCIE_MBIST_START_PAUSE_V1_8821C(v)) + +#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C 0 +#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C 0x3ffff +#define BIT_MAC_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C) \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C) +#define BITS_MAC_MBIST_START_PAUSE_V1_8821C \ + (BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8821C(x) \ + ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8821C)) +#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C) & \ + BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C) +#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8821C(x, v) \ + (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8821C(x) | \ + BIT_MAC_MBIST_START_PAUSE_V1_8821C(v)) /* 2 REG_MBIST_DONE_8821C */ -#define BIT_SHIFT_8051_MBIST_DONE_8821C 26 -#define BIT_MASK_8051_MBIST_DONE_8821C 0x7 -#define BIT_8051_MBIST_DONE_8821C(x) (((x) & BIT_MASK_8051_MBIST_DONE_8821C) << BIT_SHIFT_8051_MBIST_DONE_8821C) -#define BIT_GET_8051_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8821C) & BIT_MASK_8051_MBIST_DONE_8821C) - - - -#define BIT_SHIFT_USB_MBIST_DONE_8821C 24 -#define BIT_MASK_USB_MBIST_DONE_8821C 0x3 -#define BIT_USB_MBIST_DONE_8821C(x) (((x) & BIT_MASK_USB_MBIST_DONE_8821C) << BIT_SHIFT_USB_MBIST_DONE_8821C) -#define BIT_GET_USB_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8821C) & BIT_MASK_USB_MBIST_DONE_8821C) - - - -#define BIT_SHIFT_PCIE_MBIST_DONE_8821C 16 -#define BIT_MASK_PCIE_MBIST_DONE_8821C 0x3f -#define BIT_PCIE_MBIST_DONE_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8821C) << BIT_SHIFT_PCIE_MBIST_DONE_8821C) -#define BIT_GET_PCIE_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8821C) & BIT_MASK_PCIE_MBIST_DONE_8821C) - - - -#define BIT_SHIFT_MAC_MBIST_DONE_8821C 0 -#define BIT_MASK_MAC_MBIST_DONE_8821C 0xfff -#define BIT_MAC_MBIST_DONE_8821C(x) (((x) & BIT_MASK_MAC_MBIST_DONE_8821C) << BIT_SHIFT_MAC_MBIST_DONE_8821C) -#define BIT_GET_MAC_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8821C) & BIT_MASK_MAC_MBIST_DONE_8821C) - - - -/* 2 REG_MBIST_FAIL_NRML_8821C */ - -#define BIT_SHIFT_MBIST_FAIL_NRML_8821C 0 -#define BIT_MASK_MBIST_FAIL_NRML_8821C 0xffffffffL -#define BIT_MBIST_FAIL_NRML_8821C(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_8821C) << BIT_SHIFT_MBIST_FAIL_NRML_8821C) -#define BIT_GET_MBIST_FAIL_NRML_8821C(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8821C) & BIT_MASK_MBIST_FAIL_NRML_8821C) - - +#define BIT_SHIFT_8051_MBIST_DONE_V1_8821C 26 +#define BIT_MASK_8051_MBIST_DONE_V1_8821C 0x3f +#define BIT_8051_MBIST_DONE_V1_8821C(x) \ + (((x) & BIT_MASK_8051_MBIST_DONE_V1_8821C) \ + << BIT_SHIFT_8051_MBIST_DONE_V1_8821C) +#define BITS_8051_MBIST_DONE_V1_8821C \ + (BIT_MASK_8051_MBIST_DONE_V1_8821C \ + << BIT_SHIFT_8051_MBIST_DONE_V1_8821C) +#define BIT_CLEAR_8051_MBIST_DONE_V1_8821C(x) \ + ((x) & (~BITS_8051_MBIST_DONE_V1_8821C)) +#define BIT_GET_8051_MBIST_DONE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DONE_V1_8821C) & \ + BIT_MASK_8051_MBIST_DONE_V1_8821C) +#define BIT_SET_8051_MBIST_DONE_V1_8821C(x, v) \ + (BIT_CLEAR_8051_MBIST_DONE_V1_8821C(x) | \ + BIT_8051_MBIST_DONE_V1_8821C(v)) + +#define BIT_SHIFT_USB_MBIST_DONE_V1_8821C 24 +#define BIT_MASK_USB_MBIST_DONE_V1_8821C 0x3 +#define BIT_USB_MBIST_DONE_V1_8821C(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE_V1_8821C) \ + << BIT_SHIFT_USB_MBIST_DONE_V1_8821C) +#define BITS_USB_MBIST_DONE_V1_8821C \ + (BIT_MASK_USB_MBIST_DONE_V1_8821C << BIT_SHIFT_USB_MBIST_DONE_V1_8821C) +#define BIT_CLEAR_USB_MBIST_DONE_V1_8821C(x) \ + ((x) & (~BITS_USB_MBIST_DONE_V1_8821C)) +#define BIT_GET_USB_MBIST_DONE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE_V1_8821C) & \ + BIT_MASK_USB_MBIST_DONE_V1_8821C) +#define BIT_SET_USB_MBIST_DONE_V1_8821C(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE_V1_8821C(x) | BIT_USB_MBIST_DONE_V1_8821C(v)) + +#define BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C 18 +#define BIT_MASK_PCIE_MBIST_DONE_V1_8821C 0x3f +#define BIT_PCIE_MBIST_DONE_V1_8821C(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE_V1_8821C) \ + << BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C) +#define BITS_PCIE_MBIST_DONE_V1_8821C \ + (BIT_MASK_PCIE_MBIST_DONE_V1_8821C \ + << BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C) +#define BIT_CLEAR_PCIE_MBIST_DONE_V1_8821C(x) \ + ((x) & (~BITS_PCIE_MBIST_DONE_V1_8821C)) +#define BIT_GET_PCIE_MBIST_DONE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C) & \ + BIT_MASK_PCIE_MBIST_DONE_V1_8821C) +#define BIT_SET_PCIE_MBIST_DONE_V1_8821C(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE_V1_8821C(x) | \ + BIT_PCIE_MBIST_DONE_V1_8821C(v)) + +#define BIT_SHIFT_MAC_MBIST_DONE_V1_8821C 0 +#define BIT_MASK_MAC_MBIST_DONE_V1_8821C 0x3ffff +#define BIT_MAC_MBIST_DONE_V1_8821C(x) \ + (((x) & BIT_MASK_MAC_MBIST_DONE_V1_8821C) \ + << BIT_SHIFT_MAC_MBIST_DONE_V1_8821C) +#define BITS_MAC_MBIST_DONE_V1_8821C \ + (BIT_MASK_MAC_MBIST_DONE_V1_8821C << BIT_SHIFT_MAC_MBIST_DONE_V1_8821C) +#define BIT_CLEAR_MAC_MBIST_DONE_V1_8821C(x) \ + ((x) & (~BITS_MAC_MBIST_DONE_V1_8821C)) +#define BIT_GET_MAC_MBIST_DONE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8821C) & \ + BIT_MASK_MAC_MBIST_DONE_V1_8821C) +#define BIT_SET_MAC_MBIST_DONE_V1_8821C(x, v) \ + (BIT_CLEAR_MAC_MBIST_DONE_V1_8821C(x) | BIT_MAC_MBIST_DONE_V1_8821C(v)) + +/* 2 REG_MBIST_READ_BIST_RPT_8821C */ + +#define BIT_SHIFT_MBIST_READ_BIST_RPT_8821C 0 +#define BIT_MASK_MBIST_READ_BIST_RPT_8821C 0xffffffffL +#define BIT_MBIST_READ_BIST_RPT_8821C(x) \ + (((x) & BIT_MASK_MBIST_READ_BIST_RPT_8821C) \ + << BIT_SHIFT_MBIST_READ_BIST_RPT_8821C) +#define BITS_MBIST_READ_BIST_RPT_8821C \ + (BIT_MASK_MBIST_READ_BIST_RPT_8821C \ + << BIT_SHIFT_MBIST_READ_BIST_RPT_8821C) +#define BIT_CLEAR_MBIST_READ_BIST_RPT_8821C(x) \ + ((x) & (~BITS_MBIST_READ_BIST_RPT_8821C)) +#define BIT_GET_MBIST_READ_BIST_RPT_8821C(x) \ + (((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT_8821C) & \ + BIT_MASK_MBIST_READ_BIST_RPT_8821C) +#define BIT_SET_MBIST_READ_BIST_RPT_8821C(x, v) \ + (BIT_CLEAR_MBIST_READ_BIST_RPT_8821C(x) | \ + BIT_MBIST_READ_BIST_RPT_8821C(v)) /* 2 REG_AES_DECRPT_DATA_8821C */ #define BIT_SHIFT_IPS_CFG_ADDR_8821C 0 #define BIT_MASK_IPS_CFG_ADDR_8821C 0xff -#define BIT_IPS_CFG_ADDR_8821C(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8821C) << BIT_SHIFT_IPS_CFG_ADDR_8821C) -#define BIT_GET_IPS_CFG_ADDR_8821C(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8821C) & BIT_MASK_IPS_CFG_ADDR_8821C) - - +#define BIT_IPS_CFG_ADDR_8821C(x) \ + (((x) & BIT_MASK_IPS_CFG_ADDR_8821C) << BIT_SHIFT_IPS_CFG_ADDR_8821C) +#define BITS_IPS_CFG_ADDR_8821C \ + (BIT_MASK_IPS_CFG_ADDR_8821C << BIT_SHIFT_IPS_CFG_ADDR_8821C) +#define BIT_CLEAR_IPS_CFG_ADDR_8821C(x) ((x) & (~BITS_IPS_CFG_ADDR_8821C)) +#define BIT_GET_IPS_CFG_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8821C) & BIT_MASK_IPS_CFG_ADDR_8821C) +#define BIT_SET_IPS_CFG_ADDR_8821C(x, v) \ + (BIT_CLEAR_IPS_CFG_ADDR_8821C(x) | BIT_IPS_CFG_ADDR_8821C(v)) /* 2 REG_AES_DECRPT_CFG_8821C */ #define BIT_SHIFT_IPS_CFG_DATA_8821C 0 #define BIT_MASK_IPS_CFG_DATA_8821C 0xffffffffL -#define BIT_IPS_CFG_DATA_8821C(x) (((x) & BIT_MASK_IPS_CFG_DATA_8821C) << BIT_SHIFT_IPS_CFG_DATA_8821C) -#define BIT_GET_IPS_CFG_DATA_8821C(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8821C) & BIT_MASK_IPS_CFG_DATA_8821C) - - +#define BIT_IPS_CFG_DATA_8821C(x) \ + (((x) & BIT_MASK_IPS_CFG_DATA_8821C) << BIT_SHIFT_IPS_CFG_DATA_8821C) +#define BITS_IPS_CFG_DATA_8821C \ + (BIT_MASK_IPS_CFG_DATA_8821C << BIT_SHIFT_IPS_CFG_DATA_8821C) +#define BIT_CLEAR_IPS_CFG_DATA_8821C(x) ((x) & (~BITS_IPS_CFG_DATA_8821C)) +#define BIT_GET_IPS_CFG_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_DATA_8821C) & BIT_MASK_IPS_CFG_DATA_8821C) +#define BIT_SET_IPS_CFG_DATA_8821C(x, v) \ + (BIT_CLEAR_IPS_CFG_DATA_8821C(x) | BIT_IPS_CFG_DATA_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -2686,23 +4033,44 @@ #define BIT_SHIFT_TEMP_VALUE_8821C 24 #define BIT_MASK_TEMP_VALUE_8821C 0x3f -#define BIT_TEMP_VALUE_8821C(x) (((x) & BIT_MASK_TEMP_VALUE_8821C) << BIT_SHIFT_TEMP_VALUE_8821C) -#define BIT_GET_TEMP_VALUE_8821C(x) (((x) >> BIT_SHIFT_TEMP_VALUE_8821C) & BIT_MASK_TEMP_VALUE_8821C) - - +#define BIT_TEMP_VALUE_8821C(x) \ + (((x) & BIT_MASK_TEMP_VALUE_8821C) << BIT_SHIFT_TEMP_VALUE_8821C) +#define BITS_TEMP_VALUE_8821C \ + (BIT_MASK_TEMP_VALUE_8821C << BIT_SHIFT_TEMP_VALUE_8821C) +#define BIT_CLEAR_TEMP_VALUE_8821C(x) ((x) & (~BITS_TEMP_VALUE_8821C)) +#define BIT_GET_TEMP_VALUE_8821C(x) \ + (((x) >> BIT_SHIFT_TEMP_VALUE_8821C) & BIT_MASK_TEMP_VALUE_8821C) +#define BIT_SET_TEMP_VALUE_8821C(x, v) \ + (BIT_CLEAR_TEMP_VALUE_8821C(x) | BIT_TEMP_VALUE_8821C(v)) #define BIT_SHIFT_REG_TMETER_TIMER_8821C 8 #define BIT_MASK_REG_TMETER_TIMER_8821C 0xfff -#define BIT_REG_TMETER_TIMER_8821C(x) (((x) & BIT_MASK_REG_TMETER_TIMER_8821C) << BIT_SHIFT_REG_TMETER_TIMER_8821C) -#define BIT_GET_REG_TMETER_TIMER_8821C(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8821C) & BIT_MASK_REG_TMETER_TIMER_8821C) - - +#define BIT_REG_TMETER_TIMER_8821C(x) \ + (((x) & BIT_MASK_REG_TMETER_TIMER_8821C) \ + << BIT_SHIFT_REG_TMETER_TIMER_8821C) +#define BITS_REG_TMETER_TIMER_8821C \ + (BIT_MASK_REG_TMETER_TIMER_8821C << BIT_SHIFT_REG_TMETER_TIMER_8821C) +#define BIT_CLEAR_REG_TMETER_TIMER_8821C(x) \ + ((x) & (~BITS_REG_TMETER_TIMER_8821C)) +#define BIT_GET_REG_TMETER_TIMER_8821C(x) \ + (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8821C) & \ + BIT_MASK_REG_TMETER_TIMER_8821C) +#define BIT_SET_REG_TMETER_TIMER_8821C(x, v) \ + (BIT_CLEAR_REG_TMETER_TIMER_8821C(x) | BIT_REG_TMETER_TIMER_8821C(v)) #define BIT_SHIFT_REG_TEMP_DELTA_8821C 2 #define BIT_MASK_REG_TEMP_DELTA_8821C 0x3f -#define BIT_REG_TEMP_DELTA_8821C(x) (((x) & BIT_MASK_REG_TEMP_DELTA_8821C) << BIT_SHIFT_REG_TEMP_DELTA_8821C) -#define BIT_GET_REG_TEMP_DELTA_8821C(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8821C) & BIT_MASK_REG_TEMP_DELTA_8821C) - +#define BIT_REG_TEMP_DELTA_8821C(x) \ + (((x) & BIT_MASK_REG_TEMP_DELTA_8821C) \ + << BIT_SHIFT_REG_TEMP_DELTA_8821C) +#define BITS_REG_TEMP_DELTA_8821C \ + (BIT_MASK_REG_TEMP_DELTA_8821C << BIT_SHIFT_REG_TEMP_DELTA_8821C) +#define BIT_CLEAR_REG_TEMP_DELTA_8821C(x) ((x) & (~BITS_REG_TEMP_DELTA_8821C)) +#define BIT_GET_REG_TEMP_DELTA_8821C(x) \ + (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8821C) & \ + BIT_MASK_REG_TEMP_DELTA_8821C) +#define BIT_SET_REG_TEMP_DELTA_8821C(x, v) \ + (BIT_CLEAR_REG_TEMP_DELTA_8821C(x) | BIT_REG_TEMP_DELTA_8821C(v)) #define BIT_REG_TMETER_EN_8821C BIT(0) @@ -2710,16 +4078,33 @@ #define BIT_SHIFT_OSC_32K_CLKGEN_0_8821C 16 #define BIT_MASK_OSC_32K_CLKGEN_0_8821C 0xffff -#define BIT_OSC_32K_CLKGEN_0_8821C(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8821C) << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) -#define BIT_GET_OSC_32K_CLKGEN_0_8821C(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) & BIT_MASK_OSC_32K_CLKGEN_0_8821C) - - +#define BIT_OSC_32K_CLKGEN_0_8821C(x) \ + (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8821C) \ + << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) +#define BITS_OSC_32K_CLKGEN_0_8821C \ + (BIT_MASK_OSC_32K_CLKGEN_0_8821C << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) +#define BIT_CLEAR_OSC_32K_CLKGEN_0_8821C(x) \ + ((x) & (~BITS_OSC_32K_CLKGEN_0_8821C)) +#define BIT_GET_OSC_32K_CLKGEN_0_8821C(x) \ + (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) & \ + BIT_MASK_OSC_32K_CLKGEN_0_8821C) +#define BIT_SET_OSC_32K_CLKGEN_0_8821C(x, v) \ + (BIT_CLEAR_OSC_32K_CLKGEN_0_8821C(x) | BIT_OSC_32K_CLKGEN_0_8821C(v)) #define BIT_SHIFT_OSC_32K_RES_COMP_8821C 4 #define BIT_MASK_OSC_32K_RES_COMP_8821C 0x3 -#define BIT_OSC_32K_RES_COMP_8821C(x) (((x) & BIT_MASK_OSC_32K_RES_COMP_8821C) << BIT_SHIFT_OSC_32K_RES_COMP_8821C) -#define BIT_GET_OSC_32K_RES_COMP_8821C(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8821C) & BIT_MASK_OSC_32K_RES_COMP_8821C) - +#define BIT_OSC_32K_RES_COMP_8821C(x) \ + (((x) & BIT_MASK_OSC_32K_RES_COMP_8821C) \ + << BIT_SHIFT_OSC_32K_RES_COMP_8821C) +#define BITS_OSC_32K_RES_COMP_8821C \ + (BIT_MASK_OSC_32K_RES_COMP_8821C << BIT_SHIFT_OSC_32K_RES_COMP_8821C) +#define BIT_CLEAR_OSC_32K_RES_COMP_8821C(x) \ + ((x) & (~BITS_OSC_32K_RES_COMP_8821C)) +#define BIT_GET_OSC_32K_RES_COMP_8821C(x) \ + (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8821C) & \ + BIT_MASK_OSC_32K_RES_COMP_8821C) +#define BIT_SET_OSC_32K_RES_COMP_8821C(x, v) \ + (BIT_CLEAR_OSC_32K_RES_COMP_8821C(x) | BIT_OSC_32K_RES_COMP_8821C(v)) #define BIT_OSC_32K_OUT_SEL_8821C BIT(3) #define BIT_ISO_WL_2_OSC_32K_8821C BIT(1) @@ -2731,17 +4116,33 @@ #define BIT_SHIFT_CAL_32K_REG_ADDR_8821C 16 #define BIT_MASK_CAL_32K_REG_ADDR_8821C 0x3f -#define BIT_CAL_32K_REG_ADDR_8821C(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR_8821C) << BIT_SHIFT_CAL_32K_REG_ADDR_8821C) -#define BIT_GET_CAL_32K_REG_ADDR_8821C(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8821C) & BIT_MASK_CAL_32K_REG_ADDR_8821C) - - +#define BIT_CAL_32K_REG_ADDR_8821C(x) \ + (((x) & BIT_MASK_CAL_32K_REG_ADDR_8821C) \ + << BIT_SHIFT_CAL_32K_REG_ADDR_8821C) +#define BITS_CAL_32K_REG_ADDR_8821C \ + (BIT_MASK_CAL_32K_REG_ADDR_8821C << BIT_SHIFT_CAL_32K_REG_ADDR_8821C) +#define BIT_CLEAR_CAL_32K_REG_ADDR_8821C(x) \ + ((x) & (~BITS_CAL_32K_REG_ADDR_8821C)) +#define BIT_GET_CAL_32K_REG_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8821C) & \ + BIT_MASK_CAL_32K_REG_ADDR_8821C) +#define BIT_SET_CAL_32K_REG_ADDR_8821C(x, v) \ + (BIT_CLEAR_CAL_32K_REG_ADDR_8821C(x) | BIT_CAL_32K_REG_ADDR_8821C(v)) #define BIT_SHIFT_CAL_32K_REG_DATA_8821C 0 #define BIT_MASK_CAL_32K_REG_DATA_8821C 0xffff -#define BIT_CAL_32K_REG_DATA_8821C(x) (((x) & BIT_MASK_CAL_32K_REG_DATA_8821C) << BIT_SHIFT_CAL_32K_REG_DATA_8821C) -#define BIT_GET_CAL_32K_REG_DATA_8821C(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8821C) & BIT_MASK_CAL_32K_REG_DATA_8821C) - - +#define BIT_CAL_32K_REG_DATA_8821C(x) \ + (((x) & BIT_MASK_CAL_32K_REG_DATA_8821C) \ + << BIT_SHIFT_CAL_32K_REG_DATA_8821C) +#define BITS_CAL_32K_REG_DATA_8821C \ + (BIT_MASK_CAL_32K_REG_DATA_8821C << BIT_SHIFT_CAL_32K_REG_DATA_8821C) +#define BIT_CLEAR_CAL_32K_REG_DATA_8821C(x) \ + ((x) & (~BITS_CAL_32K_REG_DATA_8821C)) +#define BIT_GET_CAL_32K_REG_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8821C) & \ + BIT_MASK_CAL_32K_REG_DATA_8821C) +#define BIT_SET_CAL_32K_REG_DATA_8821C(x, v) \ + (BIT_CLEAR_CAL_32K_REG_DATA_8821C(x) | BIT_CAL_32K_REG_DATA_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -2749,37 +4150,57 @@ #define BIT_SHIFT_C2HEVT_MSG_V1_8821C 0 #define BIT_MASK_C2HEVT_MSG_V1_8821C 0xffffffffL -#define BIT_C2HEVT_MSG_V1_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_V1_8821C) << BIT_SHIFT_C2HEVT_MSG_V1_8821C) -#define BIT_GET_C2HEVT_MSG_V1_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8821C) & BIT_MASK_C2HEVT_MSG_V1_8821C) - - +#define BIT_C2HEVT_MSG_V1_8821C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_V1_8821C) << BIT_SHIFT_C2HEVT_MSG_V1_8821C) +#define BITS_C2HEVT_MSG_V1_8821C \ + (BIT_MASK_C2HEVT_MSG_V1_8821C << BIT_SHIFT_C2HEVT_MSG_V1_8821C) +#define BIT_CLEAR_C2HEVT_MSG_V1_8821C(x) ((x) & (~BITS_C2HEVT_MSG_V1_8821C)) +#define BIT_GET_C2HEVT_MSG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8821C) & BIT_MASK_C2HEVT_MSG_V1_8821C) +#define BIT_SET_C2HEVT_MSG_V1_8821C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_V1_8821C(x) | BIT_C2HEVT_MSG_V1_8821C(v)) /* 2 REG_C2HEVT_1_8821C */ #define BIT_SHIFT_C2HEVT_MSG_1_8821C 0 #define BIT_MASK_C2HEVT_MSG_1_8821C 0xffffffffL -#define BIT_C2HEVT_MSG_1_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_1_8821C) << BIT_SHIFT_C2HEVT_MSG_1_8821C) -#define BIT_GET_C2HEVT_MSG_1_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8821C) & BIT_MASK_C2HEVT_MSG_1_8821C) - - +#define BIT_C2HEVT_MSG_1_8821C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_1_8821C) << BIT_SHIFT_C2HEVT_MSG_1_8821C) +#define BITS_C2HEVT_MSG_1_8821C \ + (BIT_MASK_C2HEVT_MSG_1_8821C << BIT_SHIFT_C2HEVT_MSG_1_8821C) +#define BIT_CLEAR_C2HEVT_MSG_1_8821C(x) ((x) & (~BITS_C2HEVT_MSG_1_8821C)) +#define BIT_GET_C2HEVT_MSG_1_8821C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8821C) & BIT_MASK_C2HEVT_MSG_1_8821C) +#define BIT_SET_C2HEVT_MSG_1_8821C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_1_8821C(x) | BIT_C2HEVT_MSG_1_8821C(v)) /* 2 REG_C2HEVT_2_8821C */ #define BIT_SHIFT_C2HEVT_MSG_2_8821C 0 #define BIT_MASK_C2HEVT_MSG_2_8821C 0xffffffffL -#define BIT_C2HEVT_MSG_2_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_2_8821C) << BIT_SHIFT_C2HEVT_MSG_2_8821C) -#define BIT_GET_C2HEVT_MSG_2_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8821C) & BIT_MASK_C2HEVT_MSG_2_8821C) - - +#define BIT_C2HEVT_MSG_2_8821C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_2_8821C) << BIT_SHIFT_C2HEVT_MSG_2_8821C) +#define BITS_C2HEVT_MSG_2_8821C \ + (BIT_MASK_C2HEVT_MSG_2_8821C << BIT_SHIFT_C2HEVT_MSG_2_8821C) +#define BIT_CLEAR_C2HEVT_MSG_2_8821C(x) ((x) & (~BITS_C2HEVT_MSG_2_8821C)) +#define BIT_GET_C2HEVT_MSG_2_8821C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8821C) & BIT_MASK_C2HEVT_MSG_2_8821C) +#define BIT_SET_C2HEVT_MSG_2_8821C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_2_8821C(x) | BIT_C2HEVT_MSG_2_8821C(v)) /* 2 REG_C2HEVT_3_8821C */ #define BIT_SHIFT_C2HEVT_MSG_3_8821C 0 #define BIT_MASK_C2HEVT_MSG_3_8821C 0xffffffffL -#define BIT_C2HEVT_MSG_3_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_3_8821C) << BIT_SHIFT_C2HEVT_MSG_3_8821C) -#define BIT_GET_C2HEVT_MSG_3_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8821C) & BIT_MASK_C2HEVT_MSG_3_8821C) - - +#define BIT_C2HEVT_MSG_3_8821C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_3_8821C) << BIT_SHIFT_C2HEVT_MSG_3_8821C) +#define BITS_C2HEVT_MSG_3_8821C \ + (BIT_MASK_C2HEVT_MSG_3_8821C << BIT_SHIFT_C2HEVT_MSG_3_8821C) +#define BIT_CLEAR_C2HEVT_MSG_3_8821C(x) ((x) & (~BITS_C2HEVT_MSG_3_8821C)) +#define BIT_GET_C2HEVT_MSG_3_8821C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8821C) & BIT_MASK_C2HEVT_MSG_3_8821C) +#define BIT_SET_C2HEVT_MSG_3_8821C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_3_8821C(x) | BIT_C2HEVT_MSG_3_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -2789,55 +4210,93 @@ #define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C 0 #define BIT_MASK_SW_DEFINED_PAGE1_V1_8821C 0xffffffffL -#define BIT_SW_DEFINED_PAGE1_V1_8821C(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) -#define BIT_GET_SW_DEFINED_PAGE1_V1_8821C(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) - - +#define BIT_SW_DEFINED_PAGE1_V1_8821C(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) \ + << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) +#define BITS_SW_DEFINED_PAGE1_V1_8821C \ + (BIT_MASK_SW_DEFINED_PAGE1_V1_8821C \ + << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) +#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8821C(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE1_V1_8821C)) +#define BIT_GET_SW_DEFINED_PAGE1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) & \ + BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) +#define BIT_SET_SW_DEFINED_PAGE1_V1_8821C(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1_V1_8821C(x) | \ + BIT_SW_DEFINED_PAGE1_V1_8821C(v)) /* 2 REG_SW_DEFINED_PAGE2_8821C */ #define BIT_SHIFT_SW_DEFINED_PAGE2_8821C 0 #define BIT_MASK_SW_DEFINED_PAGE2_8821C 0xffffffffL -#define BIT_SW_DEFINED_PAGE2_8821C(x) (((x) & BIT_MASK_SW_DEFINED_PAGE2_8821C) << BIT_SHIFT_SW_DEFINED_PAGE2_8821C) -#define BIT_GET_SW_DEFINED_PAGE2_8821C(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8821C) & BIT_MASK_SW_DEFINED_PAGE2_8821C) - - +#define BIT_SW_DEFINED_PAGE2_8821C(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE2_8821C) \ + << BIT_SHIFT_SW_DEFINED_PAGE2_8821C) +#define BITS_SW_DEFINED_PAGE2_8821C \ + (BIT_MASK_SW_DEFINED_PAGE2_8821C << BIT_SHIFT_SW_DEFINED_PAGE2_8821C) +#define BIT_CLEAR_SW_DEFINED_PAGE2_8821C(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE2_8821C)) +#define BIT_GET_SW_DEFINED_PAGE2_8821C(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8821C) & \ + BIT_MASK_SW_DEFINED_PAGE2_8821C) +#define BIT_SET_SW_DEFINED_PAGE2_8821C(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE2_8821C(x) | BIT_SW_DEFINED_PAGE2_8821C(v)) /* 2 REG_MCUTST_I_8821C */ #define BIT_SHIFT_MCUDMSG_I_8821C 0 #define BIT_MASK_MCUDMSG_I_8821C 0xffffffffL -#define BIT_MCUDMSG_I_8821C(x) (((x) & BIT_MASK_MCUDMSG_I_8821C) << BIT_SHIFT_MCUDMSG_I_8821C) -#define BIT_GET_MCUDMSG_I_8821C(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8821C) & BIT_MASK_MCUDMSG_I_8821C) - - +#define BIT_MCUDMSG_I_8821C(x) \ + (((x) & BIT_MASK_MCUDMSG_I_8821C) << BIT_SHIFT_MCUDMSG_I_8821C) +#define BITS_MCUDMSG_I_8821C \ + (BIT_MASK_MCUDMSG_I_8821C << BIT_SHIFT_MCUDMSG_I_8821C) +#define BIT_CLEAR_MCUDMSG_I_8821C(x) ((x) & (~BITS_MCUDMSG_I_8821C)) +#define BIT_GET_MCUDMSG_I_8821C(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_I_8821C) & BIT_MASK_MCUDMSG_I_8821C) +#define BIT_SET_MCUDMSG_I_8821C(x, v) \ + (BIT_CLEAR_MCUDMSG_I_8821C(x) | BIT_MCUDMSG_I_8821C(v)) /* 2 REG_MCUTST_II_8821C */ #define BIT_SHIFT_MCUDMSG_II_8821C 0 #define BIT_MASK_MCUDMSG_II_8821C 0xffffffffL -#define BIT_MCUDMSG_II_8821C(x) (((x) & BIT_MASK_MCUDMSG_II_8821C) << BIT_SHIFT_MCUDMSG_II_8821C) -#define BIT_GET_MCUDMSG_II_8821C(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8821C) & BIT_MASK_MCUDMSG_II_8821C) - - +#define BIT_MCUDMSG_II_8821C(x) \ + (((x) & BIT_MASK_MCUDMSG_II_8821C) << BIT_SHIFT_MCUDMSG_II_8821C) +#define BITS_MCUDMSG_II_8821C \ + (BIT_MASK_MCUDMSG_II_8821C << BIT_SHIFT_MCUDMSG_II_8821C) +#define BIT_CLEAR_MCUDMSG_II_8821C(x) ((x) & (~BITS_MCUDMSG_II_8821C)) +#define BIT_GET_MCUDMSG_II_8821C(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_II_8821C) & BIT_MASK_MCUDMSG_II_8821C) +#define BIT_SET_MCUDMSG_II_8821C(x, v) \ + (BIT_CLEAR_MCUDMSG_II_8821C(x) | BIT_MCUDMSG_II_8821C(v)) /* 2 REG_FMETHR_8821C */ #define BIT_FMSG_INT_8821C BIT(31) #define BIT_SHIFT_FW_MSG_8821C 0 #define BIT_MASK_FW_MSG_8821C 0xffffffffL -#define BIT_FW_MSG_8821C(x) (((x) & BIT_MASK_FW_MSG_8821C) << BIT_SHIFT_FW_MSG_8821C) -#define BIT_GET_FW_MSG_8821C(x) (((x) >> BIT_SHIFT_FW_MSG_8821C) & BIT_MASK_FW_MSG_8821C) - - +#define BIT_FW_MSG_8821C(x) \ + (((x) & BIT_MASK_FW_MSG_8821C) << BIT_SHIFT_FW_MSG_8821C) +#define BITS_FW_MSG_8821C (BIT_MASK_FW_MSG_8821C << BIT_SHIFT_FW_MSG_8821C) +#define BIT_CLEAR_FW_MSG_8821C(x) ((x) & (~BITS_FW_MSG_8821C)) +#define BIT_GET_FW_MSG_8821C(x) \ + (((x) >> BIT_SHIFT_FW_MSG_8821C) & BIT_MASK_FW_MSG_8821C) +#define BIT_SET_FW_MSG_8821C(x, v) \ + (BIT_CLEAR_FW_MSG_8821C(x) | BIT_FW_MSG_8821C(v)) /* 2 REG_HMETFR_8821C */ #define BIT_SHIFT_HRCV_MSG_8821C 24 #define BIT_MASK_HRCV_MSG_8821C 0xff -#define BIT_HRCV_MSG_8821C(x) (((x) & BIT_MASK_HRCV_MSG_8821C) << BIT_SHIFT_HRCV_MSG_8821C) -#define BIT_GET_HRCV_MSG_8821C(x) (((x) >> BIT_SHIFT_HRCV_MSG_8821C) & BIT_MASK_HRCV_MSG_8821C) - +#define BIT_HRCV_MSG_8821C(x) \ + (((x) & BIT_MASK_HRCV_MSG_8821C) << BIT_SHIFT_HRCV_MSG_8821C) +#define BITS_HRCV_MSG_8821C \ + (BIT_MASK_HRCV_MSG_8821C << BIT_SHIFT_HRCV_MSG_8821C) +#define BIT_CLEAR_HRCV_MSG_8821C(x) ((x) & (~BITS_HRCV_MSG_8821C)) +#define BIT_GET_HRCV_MSG_8821C(x) \ + (((x) >> BIT_SHIFT_HRCV_MSG_8821C) & BIT_MASK_HRCV_MSG_8821C) +#define BIT_SET_HRCV_MSG_8821C(x, v) \ + (BIT_CLEAR_HRCV_MSG_8821C(x) | BIT_HRCV_MSG_8821C(v)) #define BIT_INT_BOX3_8821C BIT(3) #define BIT_INT_BOX2_8821C BIT(2) @@ -2848,91 +4307,98 @@ #define BIT_SHIFT_HOST_MSG_0_8821C 0 #define BIT_MASK_HOST_MSG_0_8821C 0xffffffffL -#define BIT_HOST_MSG_0_8821C(x) (((x) & BIT_MASK_HOST_MSG_0_8821C) << BIT_SHIFT_HOST_MSG_0_8821C) -#define BIT_GET_HOST_MSG_0_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8821C) & BIT_MASK_HOST_MSG_0_8821C) - - +#define BIT_HOST_MSG_0_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_0_8821C) << BIT_SHIFT_HOST_MSG_0_8821C) +#define BITS_HOST_MSG_0_8821C \ + (BIT_MASK_HOST_MSG_0_8821C << BIT_SHIFT_HOST_MSG_0_8821C) +#define BIT_CLEAR_HOST_MSG_0_8821C(x) ((x) & (~BITS_HOST_MSG_0_8821C)) +#define BIT_GET_HOST_MSG_0_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_0_8821C) & BIT_MASK_HOST_MSG_0_8821C) +#define BIT_SET_HOST_MSG_0_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_0_8821C(x) | BIT_HOST_MSG_0_8821C(v)) /* 2 REG_HMEBOX1_8821C */ #define BIT_SHIFT_HOST_MSG_1_8821C 0 #define BIT_MASK_HOST_MSG_1_8821C 0xffffffffL -#define BIT_HOST_MSG_1_8821C(x) (((x) & BIT_MASK_HOST_MSG_1_8821C) << BIT_SHIFT_HOST_MSG_1_8821C) -#define BIT_GET_HOST_MSG_1_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8821C) & BIT_MASK_HOST_MSG_1_8821C) - - +#define BIT_HOST_MSG_1_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_1_8821C) << BIT_SHIFT_HOST_MSG_1_8821C) +#define BITS_HOST_MSG_1_8821C \ + (BIT_MASK_HOST_MSG_1_8821C << BIT_SHIFT_HOST_MSG_1_8821C) +#define BIT_CLEAR_HOST_MSG_1_8821C(x) ((x) & (~BITS_HOST_MSG_1_8821C)) +#define BIT_GET_HOST_MSG_1_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_1_8821C) & BIT_MASK_HOST_MSG_1_8821C) +#define BIT_SET_HOST_MSG_1_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_1_8821C(x) | BIT_HOST_MSG_1_8821C(v)) /* 2 REG_HMEBOX2_8821C */ #define BIT_SHIFT_HOST_MSG_2_8821C 0 #define BIT_MASK_HOST_MSG_2_8821C 0xffffffffL -#define BIT_HOST_MSG_2_8821C(x) (((x) & BIT_MASK_HOST_MSG_2_8821C) << BIT_SHIFT_HOST_MSG_2_8821C) -#define BIT_GET_HOST_MSG_2_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8821C) & BIT_MASK_HOST_MSG_2_8821C) - - +#define BIT_HOST_MSG_2_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_2_8821C) << BIT_SHIFT_HOST_MSG_2_8821C) +#define BITS_HOST_MSG_2_8821C \ + (BIT_MASK_HOST_MSG_2_8821C << BIT_SHIFT_HOST_MSG_2_8821C) +#define BIT_CLEAR_HOST_MSG_2_8821C(x) ((x) & (~BITS_HOST_MSG_2_8821C)) +#define BIT_GET_HOST_MSG_2_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_2_8821C) & BIT_MASK_HOST_MSG_2_8821C) +#define BIT_SET_HOST_MSG_2_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_2_8821C(x) | BIT_HOST_MSG_2_8821C(v)) /* 2 REG_HMEBOX3_8821C */ #define BIT_SHIFT_HOST_MSG_3_8821C 0 #define BIT_MASK_HOST_MSG_3_8821C 0xffffffffL -#define BIT_HOST_MSG_3_8821C(x) (((x) & BIT_MASK_HOST_MSG_3_8821C) << BIT_SHIFT_HOST_MSG_3_8821C) -#define BIT_GET_HOST_MSG_3_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8821C) & BIT_MASK_HOST_MSG_3_8821C) - - - -/* 2 REG_LLT_INIT_8821C */ - -#define BIT_SHIFT_LLTE_RWM_8821C 30 -#define BIT_MASK_LLTE_RWM_8821C 0x3 -#define BIT_LLTE_RWM_8821C(x) (((x) & BIT_MASK_LLTE_RWM_8821C) << BIT_SHIFT_LLTE_RWM_8821C) -#define BIT_GET_LLTE_RWM_8821C(x) (((x) >> BIT_SHIFT_LLTE_RWM_8821C) & BIT_MASK_LLTE_RWM_8821C) - - - -#define BIT_SHIFT_LLTINI_PDATA_V1_8821C 16 -#define BIT_MASK_LLTINI_PDATA_V1_8821C 0xfff -#define BIT_LLTINI_PDATA_V1_8821C(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8821C) << BIT_SHIFT_LLTINI_PDATA_V1_8821C) -#define BIT_GET_LLTINI_PDATA_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8821C) & BIT_MASK_LLTINI_PDATA_V1_8821C) - - - -#define BIT_SHIFT_LLTINI_HDATA_V1_8821C 0 -#define BIT_MASK_LLTINI_HDATA_V1_8821C 0xfff -#define BIT_LLTINI_HDATA_V1_8821C(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8821C) << BIT_SHIFT_LLTINI_HDATA_V1_8821C) -#define BIT_GET_LLTINI_HDATA_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8821C) & BIT_MASK_LLTINI_HDATA_V1_8821C) - - - -/* 2 REG_LLT_INIT_ADDR_8821C */ - -#define BIT_SHIFT_LLTINI_ADDR_V1_8821C 0 -#define BIT_MASK_LLTINI_ADDR_V1_8821C 0xfff -#define BIT_LLTINI_ADDR_V1_8821C(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8821C) << BIT_SHIFT_LLTINI_ADDR_V1_8821C) -#define BIT_GET_LLTINI_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8821C) & BIT_MASK_LLTINI_ADDR_V1_8821C) +#define BIT_HOST_MSG_3_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_3_8821C) << BIT_SHIFT_HOST_MSG_3_8821C) +#define BITS_HOST_MSG_3_8821C \ + (BIT_MASK_HOST_MSG_3_8821C << BIT_SHIFT_HOST_MSG_3_8821C) +#define BIT_CLEAR_HOST_MSG_3_8821C(x) ((x) & (~BITS_HOST_MSG_3_8821C)) +#define BIT_GET_HOST_MSG_3_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_3_8821C) & BIT_MASK_HOST_MSG_3_8821C) +#define BIT_SET_HOST_MSG_3_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_3_8821C(x) | BIT_HOST_MSG_3_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_BB_ACCESS_CTRL_8821C */ #define BIT_SHIFT_BB_WRITE_READ_8821C 30 #define BIT_MASK_BB_WRITE_READ_8821C 0x3 -#define BIT_BB_WRITE_READ_8821C(x) (((x) & BIT_MASK_BB_WRITE_READ_8821C) << BIT_SHIFT_BB_WRITE_READ_8821C) -#define BIT_GET_BB_WRITE_READ_8821C(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8821C) & BIT_MASK_BB_WRITE_READ_8821C) - - +#define BIT_BB_WRITE_READ_8821C(x) \ + (((x) & BIT_MASK_BB_WRITE_READ_8821C) << BIT_SHIFT_BB_WRITE_READ_8821C) +#define BITS_BB_WRITE_READ_8821C \ + (BIT_MASK_BB_WRITE_READ_8821C << BIT_SHIFT_BB_WRITE_READ_8821C) +#define BIT_CLEAR_BB_WRITE_READ_8821C(x) ((x) & (~BITS_BB_WRITE_READ_8821C)) +#define BIT_GET_BB_WRITE_READ_8821C(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_READ_8821C) & BIT_MASK_BB_WRITE_READ_8821C) +#define BIT_SET_BB_WRITE_READ_8821C(x, v) \ + (BIT_CLEAR_BB_WRITE_READ_8821C(x) | BIT_BB_WRITE_READ_8821C(v)) #define BIT_SHIFT_BB_WRITE_EN_8821C 12 #define BIT_MASK_BB_WRITE_EN_8821C 0xf -#define BIT_BB_WRITE_EN_8821C(x) (((x) & BIT_MASK_BB_WRITE_EN_8821C) << BIT_SHIFT_BB_WRITE_EN_8821C) -#define BIT_GET_BB_WRITE_EN_8821C(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_8821C) & BIT_MASK_BB_WRITE_EN_8821C) - - +#define BIT_BB_WRITE_EN_8821C(x) \ + (((x) & BIT_MASK_BB_WRITE_EN_8821C) << BIT_SHIFT_BB_WRITE_EN_8821C) +#define BITS_BB_WRITE_EN_8821C \ + (BIT_MASK_BB_WRITE_EN_8821C << BIT_SHIFT_BB_WRITE_EN_8821C) +#define BIT_CLEAR_BB_WRITE_EN_8821C(x) ((x) & (~BITS_BB_WRITE_EN_8821C)) +#define BIT_GET_BB_WRITE_EN_8821C(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN_8821C) & BIT_MASK_BB_WRITE_EN_8821C) +#define BIT_SET_BB_WRITE_EN_8821C(x, v) \ + (BIT_CLEAR_BB_WRITE_EN_8821C(x) | BIT_BB_WRITE_EN_8821C(v)) #define BIT_SHIFT_BB_ADDR_8821C 2 #define BIT_MASK_BB_ADDR_8821C 0x1ff -#define BIT_BB_ADDR_8821C(x) (((x) & BIT_MASK_BB_ADDR_8821C) << BIT_SHIFT_BB_ADDR_8821C) -#define BIT_GET_BB_ADDR_8821C(x) (((x) >> BIT_SHIFT_BB_ADDR_8821C) & BIT_MASK_BB_ADDR_8821C) - +#define BIT_BB_ADDR_8821C(x) \ + (((x) & BIT_MASK_BB_ADDR_8821C) << BIT_SHIFT_BB_ADDR_8821C) +#define BITS_BB_ADDR_8821C (BIT_MASK_BB_ADDR_8821C << BIT_SHIFT_BB_ADDR_8821C) +#define BIT_CLEAR_BB_ADDR_8821C(x) ((x) & (~BITS_BB_ADDR_8821C)) +#define BIT_GET_BB_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_BB_ADDR_8821C) & BIT_MASK_BB_ADDR_8821C) +#define BIT_SET_BB_ADDR_8821C(x, v) \ + (BIT_CLEAR_BB_ADDR_8821C(x) | BIT_BB_ADDR_8821C(v)) #define BIT_BB_ERRACC_8821C BIT(0) @@ -2940,55 +4406,84 @@ #define BIT_SHIFT_BB_DATA_8821C 0 #define BIT_MASK_BB_DATA_8821C 0xffffffffL -#define BIT_BB_DATA_8821C(x) (((x) & BIT_MASK_BB_DATA_8821C) << BIT_SHIFT_BB_DATA_8821C) -#define BIT_GET_BB_DATA_8821C(x) (((x) >> BIT_SHIFT_BB_DATA_8821C) & BIT_MASK_BB_DATA_8821C) - - +#define BIT_BB_DATA_8821C(x) \ + (((x) & BIT_MASK_BB_DATA_8821C) << BIT_SHIFT_BB_DATA_8821C) +#define BITS_BB_DATA_8821C (BIT_MASK_BB_DATA_8821C << BIT_SHIFT_BB_DATA_8821C) +#define BIT_CLEAR_BB_DATA_8821C(x) ((x) & (~BITS_BB_DATA_8821C)) +#define BIT_GET_BB_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_BB_DATA_8821C) & BIT_MASK_BB_DATA_8821C) +#define BIT_SET_BB_DATA_8821C(x, v) \ + (BIT_CLEAR_BB_DATA_8821C(x) | BIT_BB_DATA_8821C(v)) /* 2 REG_HMEBOX_E0_8821C */ #define BIT_SHIFT_HMEBOX_E0_8821C 0 #define BIT_MASK_HMEBOX_E0_8821C 0xffffffffL -#define BIT_HMEBOX_E0_8821C(x) (((x) & BIT_MASK_HMEBOX_E0_8821C) << BIT_SHIFT_HMEBOX_E0_8821C) -#define BIT_GET_HMEBOX_E0_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8821C) & BIT_MASK_HMEBOX_E0_8821C) - - +#define BIT_HMEBOX_E0_8821C(x) \ + (((x) & BIT_MASK_HMEBOX_E0_8821C) << BIT_SHIFT_HMEBOX_E0_8821C) +#define BITS_HMEBOX_E0_8821C \ + (BIT_MASK_HMEBOX_E0_8821C << BIT_SHIFT_HMEBOX_E0_8821C) +#define BIT_CLEAR_HMEBOX_E0_8821C(x) ((x) & (~BITS_HMEBOX_E0_8821C)) +#define BIT_GET_HMEBOX_E0_8821C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E0_8821C) & BIT_MASK_HMEBOX_E0_8821C) +#define BIT_SET_HMEBOX_E0_8821C(x, v) \ + (BIT_CLEAR_HMEBOX_E0_8821C(x) | BIT_HMEBOX_E0_8821C(v)) /* 2 REG_HMEBOX_E1_8821C */ #define BIT_SHIFT_HMEBOX_E1_8821C 0 #define BIT_MASK_HMEBOX_E1_8821C 0xffffffffL -#define BIT_HMEBOX_E1_8821C(x) (((x) & BIT_MASK_HMEBOX_E1_8821C) << BIT_SHIFT_HMEBOX_E1_8821C) -#define BIT_GET_HMEBOX_E1_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8821C) & BIT_MASK_HMEBOX_E1_8821C) - - +#define BIT_HMEBOX_E1_8821C(x) \ + (((x) & BIT_MASK_HMEBOX_E1_8821C) << BIT_SHIFT_HMEBOX_E1_8821C) +#define BITS_HMEBOX_E1_8821C \ + (BIT_MASK_HMEBOX_E1_8821C << BIT_SHIFT_HMEBOX_E1_8821C) +#define BIT_CLEAR_HMEBOX_E1_8821C(x) ((x) & (~BITS_HMEBOX_E1_8821C)) +#define BIT_GET_HMEBOX_E1_8821C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E1_8821C) & BIT_MASK_HMEBOX_E1_8821C) +#define BIT_SET_HMEBOX_E1_8821C(x, v) \ + (BIT_CLEAR_HMEBOX_E1_8821C(x) | BIT_HMEBOX_E1_8821C(v)) /* 2 REG_HMEBOX_E2_8821C */ #define BIT_SHIFT_HMEBOX_E2_8821C 0 #define BIT_MASK_HMEBOX_E2_8821C 0xffffffffL -#define BIT_HMEBOX_E2_8821C(x) (((x) & BIT_MASK_HMEBOX_E2_8821C) << BIT_SHIFT_HMEBOX_E2_8821C) -#define BIT_GET_HMEBOX_E2_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8821C) & BIT_MASK_HMEBOX_E2_8821C) - - +#define BIT_HMEBOX_E2_8821C(x) \ + (((x) & BIT_MASK_HMEBOX_E2_8821C) << BIT_SHIFT_HMEBOX_E2_8821C) +#define BITS_HMEBOX_E2_8821C \ + (BIT_MASK_HMEBOX_E2_8821C << BIT_SHIFT_HMEBOX_E2_8821C) +#define BIT_CLEAR_HMEBOX_E2_8821C(x) ((x) & (~BITS_HMEBOX_E2_8821C)) +#define BIT_GET_HMEBOX_E2_8821C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E2_8821C) & BIT_MASK_HMEBOX_E2_8821C) +#define BIT_SET_HMEBOX_E2_8821C(x, v) \ + (BIT_CLEAR_HMEBOX_E2_8821C(x) | BIT_HMEBOX_E2_8821C(v)) /* 2 REG_HMEBOX_E3_8821C */ #define BIT_SHIFT_HMEBOX_E3_8821C 0 #define BIT_MASK_HMEBOX_E3_8821C 0xffffffffL -#define BIT_HMEBOX_E3_8821C(x) (((x) & BIT_MASK_HMEBOX_E3_8821C) << BIT_SHIFT_HMEBOX_E3_8821C) -#define BIT_GET_HMEBOX_E3_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8821C) & BIT_MASK_HMEBOX_E3_8821C) - - +#define BIT_HMEBOX_E3_8821C(x) \ + (((x) & BIT_MASK_HMEBOX_E3_8821C) << BIT_SHIFT_HMEBOX_E3_8821C) +#define BITS_HMEBOX_E3_8821C \ + (BIT_MASK_HMEBOX_E3_8821C << BIT_SHIFT_HMEBOX_E3_8821C) +#define BIT_CLEAR_HMEBOX_E3_8821C(x) ((x) & (~BITS_HMEBOX_E3_8821C)) +#define BIT_GET_HMEBOX_E3_8821C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E3_8821C) & BIT_MASK_HMEBOX_E3_8821C) +#define BIT_SET_HMEBOX_E3_8821C(x, v) \ + (BIT_CLEAR_HMEBOX_E3_8821C(x) | BIT_HMEBOX_E3_8821C(v)) /* 2 REG_CR_EXT_8821C */ #define BIT_SHIFT_PHY_REQ_DELAY_8821C 24 #define BIT_MASK_PHY_REQ_DELAY_8821C 0xf -#define BIT_PHY_REQ_DELAY_8821C(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8821C) << BIT_SHIFT_PHY_REQ_DELAY_8821C) -#define BIT_GET_PHY_REQ_DELAY_8821C(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8821C) & BIT_MASK_PHY_REQ_DELAY_8821C) - - +#define BIT_PHY_REQ_DELAY_8821C(x) \ + (((x) & BIT_MASK_PHY_REQ_DELAY_8821C) << BIT_SHIFT_PHY_REQ_DELAY_8821C) +#define BITS_PHY_REQ_DELAY_8821C \ + (BIT_MASK_PHY_REQ_DELAY_8821C << BIT_SHIFT_PHY_REQ_DELAY_8821C) +#define BIT_CLEAR_PHY_REQ_DELAY_8821C(x) ((x) & (~BITS_PHY_REQ_DELAY_8821C)) +#define BIT_GET_PHY_REQ_DELAY_8821C(x) \ + (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8821C) & BIT_MASK_PHY_REQ_DELAY_8821C) +#define BIT_SET_PHY_REQ_DELAY_8821C(x, v) \ + (BIT_CLEAR_PHY_REQ_DELAY_8821C(x) | BIT_PHY_REQ_DELAY_8821C(v)) /* 2 REG_NOT_VALID_8821C */ #define BIT_SPD_DOWN_8821C BIT(16) @@ -2997,24 +4492,36 @@ #define BIT_SHIFT_NETYPE4_8821C 4 #define BIT_MASK_NETYPE4_8821C 0x3 -#define BIT_NETYPE4_8821C(x) (((x) & BIT_MASK_NETYPE4_8821C) << BIT_SHIFT_NETYPE4_8821C) -#define BIT_GET_NETYPE4_8821C(x) (((x) >> BIT_SHIFT_NETYPE4_8821C) & BIT_MASK_NETYPE4_8821C) - - +#define BIT_NETYPE4_8821C(x) \ + (((x) & BIT_MASK_NETYPE4_8821C) << BIT_SHIFT_NETYPE4_8821C) +#define BITS_NETYPE4_8821C (BIT_MASK_NETYPE4_8821C << BIT_SHIFT_NETYPE4_8821C) +#define BIT_CLEAR_NETYPE4_8821C(x) ((x) & (~BITS_NETYPE4_8821C)) +#define BIT_GET_NETYPE4_8821C(x) \ + (((x) >> BIT_SHIFT_NETYPE4_8821C) & BIT_MASK_NETYPE4_8821C) +#define BIT_SET_NETYPE4_8821C(x, v) \ + (BIT_CLEAR_NETYPE4_8821C(x) | BIT_NETYPE4_8821C(v)) #define BIT_SHIFT_NETYPE3_8821C 2 #define BIT_MASK_NETYPE3_8821C 0x3 -#define BIT_NETYPE3_8821C(x) (((x) & BIT_MASK_NETYPE3_8821C) << BIT_SHIFT_NETYPE3_8821C) -#define BIT_GET_NETYPE3_8821C(x) (((x) >> BIT_SHIFT_NETYPE3_8821C) & BIT_MASK_NETYPE3_8821C) - - +#define BIT_NETYPE3_8821C(x) \ + (((x) & BIT_MASK_NETYPE3_8821C) << BIT_SHIFT_NETYPE3_8821C) +#define BITS_NETYPE3_8821C (BIT_MASK_NETYPE3_8821C << BIT_SHIFT_NETYPE3_8821C) +#define BIT_CLEAR_NETYPE3_8821C(x) ((x) & (~BITS_NETYPE3_8821C)) +#define BIT_GET_NETYPE3_8821C(x) \ + (((x) >> BIT_SHIFT_NETYPE3_8821C) & BIT_MASK_NETYPE3_8821C) +#define BIT_SET_NETYPE3_8821C(x, v) \ + (BIT_CLEAR_NETYPE3_8821C(x) | BIT_NETYPE3_8821C(v)) #define BIT_SHIFT_NETYPE2_8821C 0 #define BIT_MASK_NETYPE2_8821C 0x3 -#define BIT_NETYPE2_8821C(x) (((x) & BIT_MASK_NETYPE2_8821C) << BIT_SHIFT_NETYPE2_8821C) -#define BIT_GET_NETYPE2_8821C(x) (((x) >> BIT_SHIFT_NETYPE2_8821C) & BIT_MASK_NETYPE2_8821C) - - +#define BIT_NETYPE2_8821C(x) \ + (((x) & BIT_MASK_NETYPE2_8821C) << BIT_SHIFT_NETYPE2_8821C) +#define BITS_NETYPE2_8821C (BIT_MASK_NETYPE2_8821C << BIT_SHIFT_NETYPE2_8821C) +#define BIT_CLEAR_NETYPE2_8821C(x) ((x) & (~BITS_NETYPE2_8821C)) +#define BIT_GET_NETYPE2_8821C(x) \ + (((x) >> BIT_SHIFT_NETYPE2_8821C) & BIT_MASK_NETYPE2_8821C) +#define BIT_SET_NETYPE2_8821C(x, v) \ + (BIT_CLEAR_NETYPE2_8821C(x) | BIT_NETYPE2_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -3028,24 +4535,39 @@ #define BIT_SHIFT_PKTNUM_TH_V1_8821C 24 #define BIT_MASK_PKTNUM_TH_V1_8821C 0xff -#define BIT_PKTNUM_TH_V1_8821C(x) (((x) & BIT_MASK_PKTNUM_TH_V1_8821C) << BIT_SHIFT_PKTNUM_TH_V1_8821C) -#define BIT_GET_PKTNUM_TH_V1_8821C(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8821C) & BIT_MASK_PKTNUM_TH_V1_8821C) - - +#define BIT_PKTNUM_TH_V1_8821C(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V1_8821C) << BIT_SHIFT_PKTNUM_TH_V1_8821C) +#define BITS_PKTNUM_TH_V1_8821C \ + (BIT_MASK_PKTNUM_TH_V1_8821C << BIT_SHIFT_PKTNUM_TH_V1_8821C) +#define BIT_CLEAR_PKTNUM_TH_V1_8821C(x) ((x) & (~BITS_PKTNUM_TH_V1_8821C)) +#define BIT_GET_PKTNUM_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8821C) & BIT_MASK_PKTNUM_TH_V1_8821C) +#define BIT_SET_PKTNUM_TH_V1_8821C(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V1_8821C(x) | BIT_PKTNUM_TH_V1_8821C(v)) #define BIT_SHIFT_TIMER_TH_8821C 16 #define BIT_MASK_TIMER_TH_8821C 0xff -#define BIT_TIMER_TH_8821C(x) (((x) & BIT_MASK_TIMER_TH_8821C) << BIT_SHIFT_TIMER_TH_8821C) -#define BIT_GET_TIMER_TH_8821C(x) (((x) >> BIT_SHIFT_TIMER_TH_8821C) & BIT_MASK_TIMER_TH_8821C) - - +#define BIT_TIMER_TH_8821C(x) \ + (((x) & BIT_MASK_TIMER_TH_8821C) << BIT_SHIFT_TIMER_TH_8821C) +#define BITS_TIMER_TH_8821C \ + (BIT_MASK_TIMER_TH_8821C << BIT_SHIFT_TIMER_TH_8821C) +#define BIT_CLEAR_TIMER_TH_8821C(x) ((x) & (~BITS_TIMER_TH_8821C)) +#define BIT_GET_TIMER_TH_8821C(x) \ + (((x) >> BIT_SHIFT_TIMER_TH_8821C) & BIT_MASK_TIMER_TH_8821C) +#define BIT_SET_TIMER_TH_8821C(x, v) \ + (BIT_CLEAR_TIMER_TH_8821C(x) | BIT_TIMER_TH_8821C(v)) #define BIT_SHIFT_RXPKT1ENADDR_8821C 0 #define BIT_MASK_RXPKT1ENADDR_8821C 0xffff -#define BIT_RXPKT1ENADDR_8821C(x) (((x) & BIT_MASK_RXPKT1ENADDR_8821C) << BIT_SHIFT_RXPKT1ENADDR_8821C) -#define BIT_GET_RXPKT1ENADDR_8821C(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8821C) & BIT_MASK_RXPKT1ENADDR_8821C) - - +#define BIT_RXPKT1ENADDR_8821C(x) \ + (((x) & BIT_MASK_RXPKT1ENADDR_8821C) << BIT_SHIFT_RXPKT1ENADDR_8821C) +#define BITS_RXPKT1ENADDR_8821C \ + (BIT_MASK_RXPKT1ENADDR_8821C << BIT_SHIFT_RXPKT1ENADDR_8821C) +#define BIT_CLEAR_RXPKT1ENADDR_8821C(x) ((x) & (~BITS_RXPKT1ENADDR_8821C)) +#define BIT_GET_RXPKT1ENADDR_8821C(x) \ + (((x) >> BIT_SHIFT_RXPKT1ENADDR_8821C) & BIT_MASK_RXPKT1ENADDR_8821C) +#define BIT_SET_RXPKT1ENADDR_8821C(x, v) \ + (BIT_CLEAR_RXPKT1ENADDR_8821C(x) | BIT_RXPKT1ENADDR_8821C(v)) /* 2 REG_RXFF_PTR_V1_8821C */ @@ -3053,10 +4575,17 @@ #define BIT_SHIFT_RXFF0_RDPTR_V2_8821C 0 #define BIT_MASK_RXFF0_RDPTR_V2_8821C 0x3ffff -#define BIT_RXFF0_RDPTR_V2_8821C(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8821C) << BIT_SHIFT_RXFF0_RDPTR_V2_8821C) -#define BIT_GET_RXFF0_RDPTR_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8821C) & BIT_MASK_RXFF0_RDPTR_V2_8821C) - - +#define BIT_RXFF0_RDPTR_V2_8821C(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V2_8821C) \ + << BIT_SHIFT_RXFF0_RDPTR_V2_8821C) +#define BITS_RXFF0_RDPTR_V2_8821C \ + (BIT_MASK_RXFF0_RDPTR_V2_8821C << BIT_SHIFT_RXFF0_RDPTR_V2_8821C) +#define BIT_CLEAR_RXFF0_RDPTR_V2_8821C(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8821C)) +#define BIT_GET_RXFF0_RDPTR_V2_8821C(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8821C) & \ + BIT_MASK_RXFF0_RDPTR_V2_8821C) +#define BIT_SET_RXFF0_RDPTR_V2_8821C(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V2_8821C(x) | BIT_RXFF0_RDPTR_V2_8821C(v)) /* 2 REG_RXFF_WTR_V1_8821C */ @@ -3064,10 +4593,17 @@ #define BIT_SHIFT_RXFF0_WTPTR_V2_8821C 0 #define BIT_MASK_RXFF0_WTPTR_V2_8821C 0x3ffff -#define BIT_RXFF0_WTPTR_V2_8821C(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8821C) << BIT_SHIFT_RXFF0_WTPTR_V2_8821C) -#define BIT_GET_RXFF0_WTPTR_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8821C) & BIT_MASK_RXFF0_WTPTR_V2_8821C) - - +#define BIT_RXFF0_WTPTR_V2_8821C(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V2_8821C) \ + << BIT_SHIFT_RXFF0_WTPTR_V2_8821C) +#define BITS_RXFF0_WTPTR_V2_8821C \ + (BIT_MASK_RXFF0_WTPTR_V2_8821C << BIT_SHIFT_RXFF0_WTPTR_V2_8821C) +#define BIT_CLEAR_RXFF0_WTPTR_V2_8821C(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8821C)) +#define BIT_GET_RXFF0_WTPTR_V2_8821C(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8821C) & \ + BIT_MASK_RXFF0_WTPTR_V2_8821C) +#define BIT_SET_RXFF0_WTPTR_V2_8821C(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V2_8821C(x) | BIT_RXFF0_WTPTR_V2_8821C(v)) /* 2 REG_FE2IMR_8821C */ #define BIT__FE4ISR__IND_MSK_8821C BIT(29) @@ -3301,53 +4837,82 @@ #define BIT_SHIFT_MID_31TO0_8821C 0 #define BIT_MASK_MID_31TO0_8821C 0xffffffffL -#define BIT_MID_31TO0_8821C(x) (((x) & BIT_MASK_MID_31TO0_8821C) << BIT_SHIFT_MID_31TO0_8821C) -#define BIT_GET_MID_31TO0_8821C(x) (((x) >> BIT_SHIFT_MID_31TO0_8821C) & BIT_MASK_MID_31TO0_8821C) - - +#define BIT_MID_31TO0_8821C(x) \ + (((x) & BIT_MASK_MID_31TO0_8821C) << BIT_SHIFT_MID_31TO0_8821C) +#define BITS_MID_31TO0_8821C \ + (BIT_MASK_MID_31TO0_8821C << BIT_SHIFT_MID_31TO0_8821C) +#define BIT_CLEAR_MID_31TO0_8821C(x) ((x) & (~BITS_MID_31TO0_8821C)) +#define BIT_GET_MID_31TO0_8821C(x) \ + (((x) >> BIT_SHIFT_MID_31TO0_8821C) & BIT_MASK_MID_31TO0_8821C) +#define BIT_SET_MID_31TO0_8821C(x, v) \ + (BIT_CLEAR_MID_31TO0_8821C(x) | BIT_MID_31TO0_8821C(v)) /* 2 REG_SPWR1_8821C */ #define BIT_SHIFT_MID_63TO32_8821C 0 #define BIT_MASK_MID_63TO32_8821C 0xffffffffL -#define BIT_MID_63TO32_8821C(x) (((x) & BIT_MASK_MID_63TO32_8821C) << BIT_SHIFT_MID_63TO32_8821C) -#define BIT_GET_MID_63TO32_8821C(x) (((x) >> BIT_SHIFT_MID_63TO32_8821C) & BIT_MASK_MID_63TO32_8821C) - - +#define BIT_MID_63TO32_8821C(x) \ + (((x) & BIT_MASK_MID_63TO32_8821C) << BIT_SHIFT_MID_63TO32_8821C) +#define BITS_MID_63TO32_8821C \ + (BIT_MASK_MID_63TO32_8821C << BIT_SHIFT_MID_63TO32_8821C) +#define BIT_CLEAR_MID_63TO32_8821C(x) ((x) & (~BITS_MID_63TO32_8821C)) +#define BIT_GET_MID_63TO32_8821C(x) \ + (((x) >> BIT_SHIFT_MID_63TO32_8821C) & BIT_MASK_MID_63TO32_8821C) +#define BIT_SET_MID_63TO32_8821C(x, v) \ + (BIT_CLEAR_MID_63TO32_8821C(x) | BIT_MID_63TO32_8821C(v)) /* 2 REG_SPWR2_8821C */ #define BIT_SHIFT_MID_95O64_8821C 0 #define BIT_MASK_MID_95O64_8821C 0xffffffffL -#define BIT_MID_95O64_8821C(x) (((x) & BIT_MASK_MID_95O64_8821C) << BIT_SHIFT_MID_95O64_8821C) -#define BIT_GET_MID_95O64_8821C(x) (((x) >> BIT_SHIFT_MID_95O64_8821C) & BIT_MASK_MID_95O64_8821C) - - +#define BIT_MID_95O64_8821C(x) \ + (((x) & BIT_MASK_MID_95O64_8821C) << BIT_SHIFT_MID_95O64_8821C) +#define BITS_MID_95O64_8821C \ + (BIT_MASK_MID_95O64_8821C << BIT_SHIFT_MID_95O64_8821C) +#define BIT_CLEAR_MID_95O64_8821C(x) ((x) & (~BITS_MID_95O64_8821C)) +#define BIT_GET_MID_95O64_8821C(x) \ + (((x) >> BIT_SHIFT_MID_95O64_8821C) & BIT_MASK_MID_95O64_8821C) +#define BIT_SET_MID_95O64_8821C(x, v) \ + (BIT_CLEAR_MID_95O64_8821C(x) | BIT_MID_95O64_8821C(v)) /* 2 REG_SPWR3_8821C */ #define BIT_SHIFT_MID_127TO96_8821C 0 #define BIT_MASK_MID_127TO96_8821C 0xffffffffL -#define BIT_MID_127TO96_8821C(x) (((x) & BIT_MASK_MID_127TO96_8821C) << BIT_SHIFT_MID_127TO96_8821C) -#define BIT_GET_MID_127TO96_8821C(x) (((x) >> BIT_SHIFT_MID_127TO96_8821C) & BIT_MASK_MID_127TO96_8821C) - - +#define BIT_MID_127TO96_8821C(x) \ + (((x) & BIT_MASK_MID_127TO96_8821C) << BIT_SHIFT_MID_127TO96_8821C) +#define BITS_MID_127TO96_8821C \ + (BIT_MASK_MID_127TO96_8821C << BIT_SHIFT_MID_127TO96_8821C) +#define BIT_CLEAR_MID_127TO96_8821C(x) ((x) & (~BITS_MID_127TO96_8821C)) +#define BIT_GET_MID_127TO96_8821C(x) \ + (((x) >> BIT_SHIFT_MID_127TO96_8821C) & BIT_MASK_MID_127TO96_8821C) +#define BIT_SET_MID_127TO96_8821C(x, v) \ + (BIT_CLEAR_MID_127TO96_8821C(x) | BIT_MID_127TO96_8821C(v)) /* 2 REG_POWSEQ_8821C */ #define BIT_SHIFT_SEQNUM_MID_8821C 16 #define BIT_MASK_SEQNUM_MID_8821C 0xffff -#define BIT_SEQNUM_MID_8821C(x) (((x) & BIT_MASK_SEQNUM_MID_8821C) << BIT_SHIFT_SEQNUM_MID_8821C) -#define BIT_GET_SEQNUM_MID_8821C(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8821C) & BIT_MASK_SEQNUM_MID_8821C) - - +#define BIT_SEQNUM_MID_8821C(x) \ + (((x) & BIT_MASK_SEQNUM_MID_8821C) << BIT_SHIFT_SEQNUM_MID_8821C) +#define BITS_SEQNUM_MID_8821C \ + (BIT_MASK_SEQNUM_MID_8821C << BIT_SHIFT_SEQNUM_MID_8821C) +#define BIT_CLEAR_SEQNUM_MID_8821C(x) ((x) & (~BITS_SEQNUM_MID_8821C)) +#define BIT_GET_SEQNUM_MID_8821C(x) \ + (((x) >> BIT_SHIFT_SEQNUM_MID_8821C) & BIT_MASK_SEQNUM_MID_8821C) +#define BIT_SET_SEQNUM_MID_8821C(x, v) \ + (BIT_CLEAR_SEQNUM_MID_8821C(x) | BIT_SEQNUM_MID_8821C(v)) #define BIT_SHIFT_REF_MID_8821C 0 #define BIT_MASK_REF_MID_8821C 0x7f -#define BIT_REF_MID_8821C(x) (((x) & BIT_MASK_REF_MID_8821C) << BIT_SHIFT_REF_MID_8821C) -#define BIT_GET_REF_MID_8821C(x) (((x) >> BIT_SHIFT_REF_MID_8821C) & BIT_MASK_REF_MID_8821C) - - +#define BIT_REF_MID_8821C(x) \ + (((x) & BIT_MASK_REF_MID_8821C) << BIT_SHIFT_REF_MID_8821C) +#define BITS_REF_MID_8821C (BIT_MASK_REF_MID_8821C << BIT_SHIFT_REF_MID_8821C) +#define BIT_CLEAR_REF_MID_8821C(x) ((x) & (~BITS_REF_MID_8821C)) +#define BIT_GET_REF_MID_8821C(x) \ + (((x) >> BIT_SHIFT_REF_MID_8821C) & BIT_MASK_REF_MID_8821C) +#define BIT_SET_REF_MID_8821C(x, v) \ + (BIT_CLEAR_REF_MID_8821C(x) | BIT_REF_MID_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -3358,10 +4923,14 @@ #define BIT_SHIFT_TC7DATA_8821C 0 #define BIT_MASK_TC7DATA_8821C 0xffffff -#define BIT_TC7DATA_8821C(x) (((x) & BIT_MASK_TC7DATA_8821C) << BIT_SHIFT_TC7DATA_8821C) -#define BIT_GET_TC7DATA_8821C(x) (((x) >> BIT_SHIFT_TC7DATA_8821C) & BIT_MASK_TC7DATA_8821C) - - +#define BIT_TC7DATA_8821C(x) \ + (((x) & BIT_MASK_TC7DATA_8821C) << BIT_SHIFT_TC7DATA_8821C) +#define BITS_TC7DATA_8821C (BIT_MASK_TC7DATA_8821C << BIT_SHIFT_TC7DATA_8821C) +#define BIT_CLEAR_TC7DATA_8821C(x) ((x) & (~BITS_TC7DATA_8821C)) +#define BIT_GET_TC7DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC7DATA_8821C) & BIT_MASK_TC7DATA_8821C) +#define BIT_SET_TC7DATA_8821C(x, v) \ + (BIT_CLEAR_TC7DATA_8821C(x) | BIT_TC7DATA_8821C(v)) /* 2 REG_TC8_CTRL_V1_8821C */ #define BIT_TC8INT_EN_8821C BIT(26) @@ -3370,42 +4939,110 @@ #define BIT_SHIFT_TC8DATA_8821C 0 #define BIT_MASK_TC8DATA_8821C 0xffffff -#define BIT_TC8DATA_8821C(x) (((x) & BIT_MASK_TC8DATA_8821C) << BIT_SHIFT_TC8DATA_8821C) -#define BIT_GET_TC8DATA_8821C(x) (((x) >> BIT_SHIFT_TC8DATA_8821C) & BIT_MASK_TC8DATA_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_TC8DATA_8821C(x) \ + (((x) & BIT_MASK_TC8DATA_8821C) << BIT_SHIFT_TC8DATA_8821C) +#define BITS_TC8DATA_8821C (BIT_MASK_TC8DATA_8821C << BIT_SHIFT_TC8DATA_8821C) +#define BIT_CLEAR_TC8DATA_8821C(x) ((x) & (~BITS_TC8DATA_8821C)) +#define BIT_GET_TC8DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC8DATA_8821C) & BIT_MASK_TC8DATA_8821C) +#define BIT_SET_TC8DATA_8821C(x, v) \ + (BIT_CLEAR_TC8DATA_8821C(x) | BIT_TC8DATA_8821C(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL0_8821C */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C 24 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8821C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8821C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT2_8821C(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C 16 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8821C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8821C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT1_8821C(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C 8 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8821C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8821C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT0_8821C(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C 0xff +#define BIT_RX_BCN_TBTT_ITVL_PORT0_8821C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C) +#define BITS_RX_BCN_TBTT_ITVL_PORT0_8821C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8821C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8821C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8821C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C) +#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8821C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8821C(x) | \ + BIT_RX_BCN_TBTT_ITVL_PORT0_8821C(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL1_8821C */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8821C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8821C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT3_8821C(v)) /* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_IO_WRAP_ERR_FLAG_8821C */ +#define BIT_IO_WRAP_ERR_8821C BIT(0) /* 2 REG_NOT_VALID_8821C */ @@ -3413,7 +5050,149 @@ /* 2 REG_NOT_VALID_8821C */ -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_SPEED_SENSOR_8821C */ +#define BIT_DSS_1_RST_N_8821C BIT(31) +#define BIT_DSS_1_SPEED_EN_8821C BIT(30) +#define BIT_DSS_1_WIRE_SEL_8821C BIT(29) +#define BIT_DSS_ENCLK_8821C BIT(28) + +#define BIT_SHIFT_DSS_1_RO_SEL_8821C 24 +#define BIT_MASK_DSS_1_RO_SEL_8821C 0x7 +#define BIT_DSS_1_RO_SEL_8821C(x) \ + (((x) & BIT_MASK_DSS_1_RO_SEL_8821C) << BIT_SHIFT_DSS_1_RO_SEL_8821C) +#define BITS_DSS_1_RO_SEL_8821C \ + (BIT_MASK_DSS_1_RO_SEL_8821C << BIT_SHIFT_DSS_1_RO_SEL_8821C) +#define BIT_CLEAR_DSS_1_RO_SEL_8821C(x) ((x) & (~BITS_DSS_1_RO_SEL_8821C)) +#define BIT_GET_DSS_1_RO_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_1_RO_SEL_8821C) & BIT_MASK_DSS_1_RO_SEL_8821C) +#define BIT_SET_DSS_1_RO_SEL_8821C(x, v) \ + (BIT_CLEAR_DSS_1_RO_SEL_8821C(x) | BIT_DSS_1_RO_SEL_8821C(v)) + +#define BIT_SHIFT_DSS_1_DATA_IN_8821C 0 +#define BIT_MASK_DSS_1_DATA_IN_8821C 0xfffff +#define BIT_DSS_1_DATA_IN_8821C(x) \ + (((x) & BIT_MASK_DSS_1_DATA_IN_8821C) << BIT_SHIFT_DSS_1_DATA_IN_8821C) +#define BITS_DSS_1_DATA_IN_8821C \ + (BIT_MASK_DSS_1_DATA_IN_8821C << BIT_SHIFT_DSS_1_DATA_IN_8821C) +#define BIT_CLEAR_DSS_1_DATA_IN_8821C(x) ((x) & (~BITS_DSS_1_DATA_IN_8821C)) +#define BIT_GET_DSS_1_DATA_IN_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_1_DATA_IN_8821C) & BIT_MASK_DSS_1_DATA_IN_8821C) +#define BIT_SET_DSS_1_DATA_IN_8821C(x, v) \ + (BIT_CLEAR_DSS_1_DATA_IN_8821C(x) | BIT_DSS_1_DATA_IN_8821C(v)) + +/* 2 REG_SPEED_SENSOR1_8821C */ +#define BIT_DSS_1_READY_8821C BIT(31) +#define BIT_DSS_1_WSORT_GO_8821C BIT(30) + +#define BIT_SHIFT_DSS_1_COUNT_OUT_8821C 0 +#define BIT_MASK_DSS_1_COUNT_OUT_8821C 0xfffff +#define BIT_DSS_1_COUNT_OUT_8821C(x) \ + (((x) & BIT_MASK_DSS_1_COUNT_OUT_8821C) \ + << BIT_SHIFT_DSS_1_COUNT_OUT_8821C) +#define BITS_DSS_1_COUNT_OUT_8821C \ + (BIT_MASK_DSS_1_COUNT_OUT_8821C << BIT_SHIFT_DSS_1_COUNT_OUT_8821C) +#define BIT_CLEAR_DSS_1_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8821C)) +#define BIT_GET_DSS_1_COUNT_OUT_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8821C) & \ + BIT_MASK_DSS_1_COUNT_OUT_8821C) +#define BIT_SET_DSS_1_COUNT_OUT_8821C(x, v) \ + (BIT_CLEAR_DSS_1_COUNT_OUT_8821C(x) | BIT_DSS_1_COUNT_OUT_8821C(v)) + +/* 2 REG_SPEED_SENSOR2_8821C */ +#define BIT_DSS_2_RST_N_8821C BIT(31) +#define BIT_DSS_2_SPEED_EN_8821C BIT(30) +#define BIT_DSS_2_WIRE_SEL_8821C BIT(29) +#define BIT_DSS_ENCLK_8821C BIT(28) + +#define BIT_SHIFT_DSS_2_RO_SEL_8821C 24 +#define BIT_MASK_DSS_2_RO_SEL_8821C 0x7 +#define BIT_DSS_2_RO_SEL_8821C(x) \ + (((x) & BIT_MASK_DSS_2_RO_SEL_8821C) << BIT_SHIFT_DSS_2_RO_SEL_8821C) +#define BITS_DSS_2_RO_SEL_8821C \ + (BIT_MASK_DSS_2_RO_SEL_8821C << BIT_SHIFT_DSS_2_RO_SEL_8821C) +#define BIT_CLEAR_DSS_2_RO_SEL_8821C(x) ((x) & (~BITS_DSS_2_RO_SEL_8821C)) +#define BIT_GET_DSS_2_RO_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_2_RO_SEL_8821C) & BIT_MASK_DSS_2_RO_SEL_8821C) +#define BIT_SET_DSS_2_RO_SEL_8821C(x, v) \ + (BIT_CLEAR_DSS_2_RO_SEL_8821C(x) | BIT_DSS_2_RO_SEL_8821C(v)) + +#define BIT_SHIFT_DSS_2_DATA_IN_8821C 0 +#define BIT_MASK_DSS_2_DATA_IN_8821C 0xfffff +#define BIT_DSS_2_DATA_IN_8821C(x) \ + (((x) & BIT_MASK_DSS_2_DATA_IN_8821C) << BIT_SHIFT_DSS_2_DATA_IN_8821C) +#define BITS_DSS_2_DATA_IN_8821C \ + (BIT_MASK_DSS_2_DATA_IN_8821C << BIT_SHIFT_DSS_2_DATA_IN_8821C) +#define BIT_CLEAR_DSS_2_DATA_IN_8821C(x) ((x) & (~BITS_DSS_2_DATA_IN_8821C)) +#define BIT_GET_DSS_2_DATA_IN_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_2_DATA_IN_8821C) & BIT_MASK_DSS_2_DATA_IN_8821C) +#define BIT_SET_DSS_2_DATA_IN_8821C(x, v) \ + (BIT_CLEAR_DSS_2_DATA_IN_8821C(x) | BIT_DSS_2_DATA_IN_8821C(v)) + +/* 2 REG_SPEED_SENSOR3_8821C */ +#define BIT_DSS_2_READY_8821C BIT(31) +#define BIT_DSS_2_WSORT_GO_8821C BIT(30) + +#define BIT_SHIFT_DSS_2_COUNT_OUT_8821C 0 +#define BIT_MASK_DSS_2_COUNT_OUT_8821C 0xfffff +#define BIT_DSS_2_COUNT_OUT_8821C(x) \ + (((x) & BIT_MASK_DSS_2_COUNT_OUT_8821C) \ + << BIT_SHIFT_DSS_2_COUNT_OUT_8821C) +#define BITS_DSS_2_COUNT_OUT_8821C \ + (BIT_MASK_DSS_2_COUNT_OUT_8821C << BIT_SHIFT_DSS_2_COUNT_OUT_8821C) +#define BIT_CLEAR_DSS_2_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8821C)) +#define BIT_GET_DSS_2_COUNT_OUT_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8821C) & \ + BIT_MASK_DSS_2_COUNT_OUT_8821C) +#define BIT_SET_DSS_2_COUNT_OUT_8821C(x, v) \ + (BIT_CLEAR_DSS_2_COUNT_OUT_8821C(x) | BIT_DSS_2_COUNT_OUT_8821C(v)) + +/* 2 REG_SPEED_SENSOR4_8821C */ +#define BIT_DSS_3_RST_N_8821C BIT(31) +#define BIT_DSS_3_SPEED_EN_8821C BIT(30) +#define BIT_DSS_3_WIRE_SEL_8821C BIT(29) +#define BIT_DSS_ENCLK_8821C BIT(28) + +#define BIT_SHIFT_DSS_3_RO_SEL_8821C 24 +#define BIT_MASK_DSS_3_RO_SEL_8821C 0x7 +#define BIT_DSS_3_RO_SEL_8821C(x) \ + (((x) & BIT_MASK_DSS_3_RO_SEL_8821C) << BIT_SHIFT_DSS_3_RO_SEL_8821C) +#define BITS_DSS_3_RO_SEL_8821C \ + (BIT_MASK_DSS_3_RO_SEL_8821C << BIT_SHIFT_DSS_3_RO_SEL_8821C) +#define BIT_CLEAR_DSS_3_RO_SEL_8821C(x) ((x) & (~BITS_DSS_3_RO_SEL_8821C)) +#define BIT_GET_DSS_3_RO_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_3_RO_SEL_8821C) & BIT_MASK_DSS_3_RO_SEL_8821C) +#define BIT_SET_DSS_3_RO_SEL_8821C(x, v) \ + (BIT_CLEAR_DSS_3_RO_SEL_8821C(x) | BIT_DSS_3_RO_SEL_8821C(v)) + +#define BIT_SHIFT_DSS_3_DATA_IN_8821C 0 +#define BIT_MASK_DSS_3_DATA_IN_8821C 0xfffff +#define BIT_DSS_3_DATA_IN_8821C(x) \ + (((x) & BIT_MASK_DSS_3_DATA_IN_8821C) << BIT_SHIFT_DSS_3_DATA_IN_8821C) +#define BITS_DSS_3_DATA_IN_8821C \ + (BIT_MASK_DSS_3_DATA_IN_8821C << BIT_SHIFT_DSS_3_DATA_IN_8821C) +#define BIT_CLEAR_DSS_3_DATA_IN_8821C(x) ((x) & (~BITS_DSS_3_DATA_IN_8821C)) +#define BIT_GET_DSS_3_DATA_IN_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_3_DATA_IN_8821C) & BIT_MASK_DSS_3_DATA_IN_8821C) +#define BIT_SET_DSS_3_DATA_IN_8821C(x, v) \ + (BIT_CLEAR_DSS_3_DATA_IN_8821C(x) | BIT_DSS_3_DATA_IN_8821C(v)) + +/* 2 REG_SPEED_SENSOR5_8821C */ +#define BIT_DSS_3_READY_8821C BIT(31) +#define BIT_DSS_3_WSORT_GO_8821C BIT(30) + +#define BIT_SHIFT_DSS_3_COUNT_OUT_8821C 0 +#define BIT_MASK_DSS_3_COUNT_OUT_8821C 0xfffff +#define BIT_DSS_3_COUNT_OUT_8821C(x) \ + (((x) & BIT_MASK_DSS_3_COUNT_OUT_8821C) \ + << BIT_SHIFT_DSS_3_COUNT_OUT_8821C) +#define BITS_DSS_3_COUNT_OUT_8821C \ + (BIT_MASK_DSS_3_COUNT_OUT_8821C << BIT_SHIFT_DSS_3_COUNT_OUT_8821C) +#define BIT_CLEAR_DSS_3_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8821C)) +#define BIT_GET_DSS_3_COUNT_OUT_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8821C) & \ + BIT_MASK_DSS_3_COUNT_OUT_8821C) +#define BIT_SET_DSS_3_COUNT_OUT_8821C(x, v) \ + (BIT_CLEAR_DSS_3_COUNT_OUT_8821C(x) | BIT_DSS_3_COUNT_OUT_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -3437,7 +5216,199 @@ /* 2 REG_NOT_VALID_8821C */ -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_COUNTER_CTRL_8821C */ + +#define BIT_SHIFT_COUNTER_BASE_8821C 16 +#define BIT_MASK_COUNTER_BASE_8821C 0x1fff +#define BIT_COUNTER_BASE_8821C(x) \ + (((x) & BIT_MASK_COUNTER_BASE_8821C) << BIT_SHIFT_COUNTER_BASE_8821C) +#define BITS_COUNTER_BASE_8821C \ + (BIT_MASK_COUNTER_BASE_8821C << BIT_SHIFT_COUNTER_BASE_8821C) +#define BIT_CLEAR_COUNTER_BASE_8821C(x) ((x) & (~BITS_COUNTER_BASE_8821C)) +#define BIT_GET_COUNTER_BASE_8821C(x) \ + (((x) >> BIT_SHIFT_COUNTER_BASE_8821C) & BIT_MASK_COUNTER_BASE_8821C) +#define BIT_SET_COUNTER_BASE_8821C(x, v) \ + (BIT_CLEAR_COUNTER_BASE_8821C(x) | BIT_COUNTER_BASE_8821C(v)) + +#define BIT_EN_RTS_REQ_8821C BIT(9) +#define BIT_EN_EDCA_REQ_8821C BIT(8) +#define BIT_EN_PTCL_REQ_8821C BIT(7) +#define BIT_EN_SCH_REQ_8821C BIT(6) +#define BIT_USB_COUNT_EN_8821C BIT(5) +#define BIT_PCIE_COUNT_EN_8821C BIT(4) +#define BIT_RQPN_COUNT_EN_8821C BIT(3) +#define BIT_RDE_COUNT_EN_8821C BIT(2) +#define BIT_TDE_COUNT_EN_8821C BIT(1) +#define BIT_DISABLE_COUNTER_8821C BIT(0) + +/* 2 REG_COUNTER_THRESHOLD_8821C */ +#define BIT_SEL_ALL_MACID_8821C BIT(31) + +#define BIT_SHIFT_COUNTER_MACID_8821C 24 +#define BIT_MASK_COUNTER_MACID_8821C 0x7f +#define BIT_COUNTER_MACID_8821C(x) \ + (((x) & BIT_MASK_COUNTER_MACID_8821C) << BIT_SHIFT_COUNTER_MACID_8821C) +#define BITS_COUNTER_MACID_8821C \ + (BIT_MASK_COUNTER_MACID_8821C << BIT_SHIFT_COUNTER_MACID_8821C) +#define BIT_CLEAR_COUNTER_MACID_8821C(x) ((x) & (~BITS_COUNTER_MACID_8821C)) +#define BIT_GET_COUNTER_MACID_8821C(x) \ + (((x) >> BIT_SHIFT_COUNTER_MACID_8821C) & BIT_MASK_COUNTER_MACID_8821C) +#define BIT_SET_COUNTER_MACID_8821C(x, v) \ + (BIT_CLEAR_COUNTER_MACID_8821C(x) | BIT_COUNTER_MACID_8821C(v)) + +#define BIT_SHIFT_AGG_VALUE2_8821C 16 +#define BIT_MASK_AGG_VALUE2_8821C 0x7f +#define BIT_AGG_VALUE2_8821C(x) \ + (((x) & BIT_MASK_AGG_VALUE2_8821C) << BIT_SHIFT_AGG_VALUE2_8821C) +#define BITS_AGG_VALUE2_8821C \ + (BIT_MASK_AGG_VALUE2_8821C << BIT_SHIFT_AGG_VALUE2_8821C) +#define BIT_CLEAR_AGG_VALUE2_8821C(x) ((x) & (~BITS_AGG_VALUE2_8821C)) +#define BIT_GET_AGG_VALUE2_8821C(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE2_8821C) & BIT_MASK_AGG_VALUE2_8821C) +#define BIT_SET_AGG_VALUE2_8821C(x, v) \ + (BIT_CLEAR_AGG_VALUE2_8821C(x) | BIT_AGG_VALUE2_8821C(v)) + +#define BIT_SHIFT_AGG_VALUE1_8821C 8 +#define BIT_MASK_AGG_VALUE1_8821C 0x7f +#define BIT_AGG_VALUE1_8821C(x) \ + (((x) & BIT_MASK_AGG_VALUE1_8821C) << BIT_SHIFT_AGG_VALUE1_8821C) +#define BITS_AGG_VALUE1_8821C \ + (BIT_MASK_AGG_VALUE1_8821C << BIT_SHIFT_AGG_VALUE1_8821C) +#define BIT_CLEAR_AGG_VALUE1_8821C(x) ((x) & (~BITS_AGG_VALUE1_8821C)) +#define BIT_GET_AGG_VALUE1_8821C(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE1_8821C) & BIT_MASK_AGG_VALUE1_8821C) +#define BIT_SET_AGG_VALUE1_8821C(x, v) \ + (BIT_CLEAR_AGG_VALUE1_8821C(x) | BIT_AGG_VALUE1_8821C(v)) + +#define BIT_SHIFT_AGG_VALUE0_8821C 0 +#define BIT_MASK_AGG_VALUE0_8821C 0x7f +#define BIT_AGG_VALUE0_8821C(x) \ + (((x) & BIT_MASK_AGG_VALUE0_8821C) << BIT_SHIFT_AGG_VALUE0_8821C) +#define BITS_AGG_VALUE0_8821C \ + (BIT_MASK_AGG_VALUE0_8821C << BIT_SHIFT_AGG_VALUE0_8821C) +#define BIT_CLEAR_AGG_VALUE0_8821C(x) ((x) & (~BITS_AGG_VALUE0_8821C)) +#define BIT_GET_AGG_VALUE0_8821C(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE0_8821C) & BIT_MASK_AGG_VALUE0_8821C) +#define BIT_SET_AGG_VALUE0_8821C(x, v) \ + (BIT_CLEAR_AGG_VALUE0_8821C(x) | BIT_AGG_VALUE0_8821C(v)) + +/* 2 REG_COUNTER_SET_8821C */ + +#define BIT_SHIFT_REQUEST_RESET_8821C 16 +#define BIT_MASK_REQUEST_RESET_8821C 0xffff +#define BIT_REQUEST_RESET_8821C(x) \ + (((x) & BIT_MASK_REQUEST_RESET_8821C) << BIT_SHIFT_REQUEST_RESET_8821C) +#define BITS_REQUEST_RESET_8821C \ + (BIT_MASK_REQUEST_RESET_8821C << BIT_SHIFT_REQUEST_RESET_8821C) +#define BIT_CLEAR_REQUEST_RESET_8821C(x) ((x) & (~BITS_REQUEST_RESET_8821C)) +#define BIT_GET_REQUEST_RESET_8821C(x) \ + (((x) >> BIT_SHIFT_REQUEST_RESET_8821C) & BIT_MASK_REQUEST_RESET_8821C) +#define BIT_SET_REQUEST_RESET_8821C(x, v) \ + (BIT_CLEAR_REQUEST_RESET_8821C(x) | BIT_REQUEST_RESET_8821C(v)) + +#define BIT_SHIFT_REQUEST_START_8821C 0 +#define BIT_MASK_REQUEST_START_8821C 0xffff +#define BIT_REQUEST_START_8821C(x) \ + (((x) & BIT_MASK_REQUEST_START_8821C) << BIT_SHIFT_REQUEST_START_8821C) +#define BITS_REQUEST_START_8821C \ + (BIT_MASK_REQUEST_START_8821C << BIT_SHIFT_REQUEST_START_8821C) +#define BIT_CLEAR_REQUEST_START_8821C(x) ((x) & (~BITS_REQUEST_START_8821C)) +#define BIT_GET_REQUEST_START_8821C(x) \ + (((x) >> BIT_SHIFT_REQUEST_START_8821C) & BIT_MASK_REQUEST_START_8821C) +#define BIT_SET_REQUEST_START_8821C(x, v) \ + (BIT_CLEAR_REQUEST_START_8821C(x) | BIT_REQUEST_START_8821C(v)) + +/* 2 REG_COUNTER_OVERFLOW_8821C */ + +#define BIT_SHIFT_CNT_OVF_REG_8821C 0 +#define BIT_MASK_CNT_OVF_REG_8821C 0xffff +#define BIT_CNT_OVF_REG_8821C(x) \ + (((x) & BIT_MASK_CNT_OVF_REG_8821C) << BIT_SHIFT_CNT_OVF_REG_8821C) +#define BITS_CNT_OVF_REG_8821C \ + (BIT_MASK_CNT_OVF_REG_8821C << BIT_SHIFT_CNT_OVF_REG_8821C) +#define BIT_CLEAR_CNT_OVF_REG_8821C(x) ((x) & (~BITS_CNT_OVF_REG_8821C)) +#define BIT_GET_CNT_OVF_REG_8821C(x) \ + (((x) >> BIT_SHIFT_CNT_OVF_REG_8821C) & BIT_MASK_CNT_OVF_REG_8821C) +#define BIT_SET_CNT_OVF_REG_8821C(x, v) \ + (BIT_CLEAR_CNT_OVF_REG_8821C(x) | BIT_CNT_OVF_REG_8821C(v)) + +/* 2 REG_TXDMA_LEN_THRESHOLD_8821C */ + +#define BIT_SHIFT_TDE_LEN_TH1_8821C 16 +#define BIT_MASK_TDE_LEN_TH1_8821C 0xffff +#define BIT_TDE_LEN_TH1_8821C(x) \ + (((x) & BIT_MASK_TDE_LEN_TH1_8821C) << BIT_SHIFT_TDE_LEN_TH1_8821C) +#define BITS_TDE_LEN_TH1_8821C \ + (BIT_MASK_TDE_LEN_TH1_8821C << BIT_SHIFT_TDE_LEN_TH1_8821C) +#define BIT_CLEAR_TDE_LEN_TH1_8821C(x) ((x) & (~BITS_TDE_LEN_TH1_8821C)) +#define BIT_GET_TDE_LEN_TH1_8821C(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH1_8821C) & BIT_MASK_TDE_LEN_TH1_8821C) +#define BIT_SET_TDE_LEN_TH1_8821C(x, v) \ + (BIT_CLEAR_TDE_LEN_TH1_8821C(x) | BIT_TDE_LEN_TH1_8821C(v)) + +#define BIT_SHIFT_TDE_LEN_TH0_8821C 0 +#define BIT_MASK_TDE_LEN_TH0_8821C 0xffff +#define BIT_TDE_LEN_TH0_8821C(x) \ + (((x) & BIT_MASK_TDE_LEN_TH0_8821C) << BIT_SHIFT_TDE_LEN_TH0_8821C) +#define BITS_TDE_LEN_TH0_8821C \ + (BIT_MASK_TDE_LEN_TH0_8821C << BIT_SHIFT_TDE_LEN_TH0_8821C) +#define BIT_CLEAR_TDE_LEN_TH0_8821C(x) ((x) & (~BITS_TDE_LEN_TH0_8821C)) +#define BIT_GET_TDE_LEN_TH0_8821C(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH0_8821C) & BIT_MASK_TDE_LEN_TH0_8821C) +#define BIT_SET_TDE_LEN_TH0_8821C(x, v) \ + (BIT_CLEAR_TDE_LEN_TH0_8821C(x) | BIT_TDE_LEN_TH0_8821C(v)) + +/* 2 REG_RXDMA_LEN_THRESHOLD_8821C */ + +#define BIT_SHIFT_RDE_LEN_TH1_8821C 16 +#define BIT_MASK_RDE_LEN_TH1_8821C 0xffff +#define BIT_RDE_LEN_TH1_8821C(x) \ + (((x) & BIT_MASK_RDE_LEN_TH1_8821C) << BIT_SHIFT_RDE_LEN_TH1_8821C) +#define BITS_RDE_LEN_TH1_8821C \ + (BIT_MASK_RDE_LEN_TH1_8821C << BIT_SHIFT_RDE_LEN_TH1_8821C) +#define BIT_CLEAR_RDE_LEN_TH1_8821C(x) ((x) & (~BITS_RDE_LEN_TH1_8821C)) +#define BIT_GET_RDE_LEN_TH1_8821C(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH1_8821C) & BIT_MASK_RDE_LEN_TH1_8821C) +#define BIT_SET_RDE_LEN_TH1_8821C(x, v) \ + (BIT_CLEAR_RDE_LEN_TH1_8821C(x) | BIT_RDE_LEN_TH1_8821C(v)) + +#define BIT_SHIFT_RDE_LEN_TH0_8821C 0 +#define BIT_MASK_RDE_LEN_TH0_8821C 0xffff +#define BIT_RDE_LEN_TH0_8821C(x) \ + (((x) & BIT_MASK_RDE_LEN_TH0_8821C) << BIT_SHIFT_RDE_LEN_TH0_8821C) +#define BITS_RDE_LEN_TH0_8821C \ + (BIT_MASK_RDE_LEN_TH0_8821C << BIT_SHIFT_RDE_LEN_TH0_8821C) +#define BIT_CLEAR_RDE_LEN_TH0_8821C(x) ((x) & (~BITS_RDE_LEN_TH0_8821C)) +#define BIT_GET_RDE_LEN_TH0_8821C(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH0_8821C) & BIT_MASK_RDE_LEN_TH0_8821C) +#define BIT_SET_RDE_LEN_TH0_8821C(x, v) \ + (BIT_CLEAR_RDE_LEN_TH0_8821C(x) | BIT_RDE_LEN_TH0_8821C(v)) + +/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8821C */ + +#define BIT_SHIFT_COUNT_INT_SEL_8821C 16 +#define BIT_MASK_COUNT_INT_SEL_8821C 0x3 +#define BIT_COUNT_INT_SEL_8821C(x) \ + (((x) & BIT_MASK_COUNT_INT_SEL_8821C) << BIT_SHIFT_COUNT_INT_SEL_8821C) +#define BITS_COUNT_INT_SEL_8821C \ + (BIT_MASK_COUNT_INT_SEL_8821C << BIT_SHIFT_COUNT_INT_SEL_8821C) +#define BIT_CLEAR_COUNT_INT_SEL_8821C(x) ((x) & (~BITS_COUNT_INT_SEL_8821C)) +#define BIT_GET_COUNT_INT_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_COUNT_INT_SEL_8821C) & BIT_MASK_COUNT_INT_SEL_8821C) +#define BIT_SET_COUNT_INT_SEL_8821C(x, v) \ + (BIT_CLEAR_COUNT_INT_SEL_8821C(x) | BIT_COUNT_INT_SEL_8821C(v)) + +#define BIT_SHIFT_EXEC_TIME_TH_8821C 0 +#define BIT_MASK_EXEC_TIME_TH_8821C 0xffff +#define BIT_EXEC_TIME_TH_8821C(x) \ + (((x) & BIT_MASK_EXEC_TIME_TH_8821C) << BIT_SHIFT_EXEC_TIME_TH_8821C) +#define BITS_EXEC_TIME_TH_8821C \ + (BIT_MASK_EXEC_TIME_TH_8821C << BIT_SHIFT_EXEC_TIME_TH_8821C) +#define BIT_CLEAR_EXEC_TIME_TH_8821C(x) ((x) & (~BITS_EXEC_TIME_TH_8821C)) +#define BIT_GET_EXEC_TIME_TH_8821C(x) \ + (((x) >> BIT_SHIFT_EXEC_TIME_TH_8821C) & BIT_MASK_EXEC_TIME_TH_8821C) +#define BIT_SET_EXEC_TIME_TH_8821C(x, v) \ + (BIT_CLEAR_EXEC_TIME_TH_8821C(x) | BIT_EXEC_TIME_TH_8821C(v)) /* 2 REG_FT2IMR_8821C */ #define BIT_FS_CLI3_RX_UAPSDMD1_EN_8821C BIT(31) @@ -3503,105 +5474,432 @@ #define BIT_SHIFT_FW_MSG2_8821C 0 #define BIT_MASK_FW_MSG2_8821C 0xffffffffL -#define BIT_FW_MSG2_8821C(x) (((x) & BIT_MASK_FW_MSG2_8821C) << BIT_SHIFT_FW_MSG2_8821C) -#define BIT_GET_FW_MSG2_8821C(x) (((x) >> BIT_SHIFT_FW_MSG2_8821C) & BIT_MASK_FW_MSG2_8821C) - - +#define BIT_FW_MSG2_8821C(x) \ + (((x) & BIT_MASK_FW_MSG2_8821C) << BIT_SHIFT_FW_MSG2_8821C) +#define BITS_FW_MSG2_8821C (BIT_MASK_FW_MSG2_8821C << BIT_SHIFT_FW_MSG2_8821C) +#define BIT_CLEAR_FW_MSG2_8821C(x) ((x) & (~BITS_FW_MSG2_8821C)) +#define BIT_GET_FW_MSG2_8821C(x) \ + (((x) >> BIT_SHIFT_FW_MSG2_8821C) & BIT_MASK_FW_MSG2_8821C) +#define BIT_SET_FW_MSG2_8821C(x, v) \ + (BIT_CLEAR_FW_MSG2_8821C(x) | BIT_FW_MSG2_8821C(v)) /* 2 REG_MSG3_8821C */ #define BIT_SHIFT_FW_MSG3_8821C 0 #define BIT_MASK_FW_MSG3_8821C 0xffffffffL -#define BIT_FW_MSG3_8821C(x) (((x) & BIT_MASK_FW_MSG3_8821C) << BIT_SHIFT_FW_MSG3_8821C) -#define BIT_GET_FW_MSG3_8821C(x) (((x) >> BIT_SHIFT_FW_MSG3_8821C) & BIT_MASK_FW_MSG3_8821C) - - +#define BIT_FW_MSG3_8821C(x) \ + (((x) & BIT_MASK_FW_MSG3_8821C) << BIT_SHIFT_FW_MSG3_8821C) +#define BITS_FW_MSG3_8821C (BIT_MASK_FW_MSG3_8821C << BIT_SHIFT_FW_MSG3_8821C) +#define BIT_CLEAR_FW_MSG3_8821C(x) ((x) & (~BITS_FW_MSG3_8821C)) +#define BIT_GET_FW_MSG3_8821C(x) \ + (((x) >> BIT_SHIFT_FW_MSG3_8821C) & BIT_MASK_FW_MSG3_8821C) +#define BIT_SET_FW_MSG3_8821C(x, v) \ + (BIT_CLEAR_FW_MSG3_8821C(x) | BIT_FW_MSG3_8821C(v)) /* 2 REG_MSG4_8821C */ #define BIT_SHIFT_FW_MSG4_8821C 0 #define BIT_MASK_FW_MSG4_8821C 0xffffffffL -#define BIT_FW_MSG4_8821C(x) (((x) & BIT_MASK_FW_MSG4_8821C) << BIT_SHIFT_FW_MSG4_8821C) -#define BIT_GET_FW_MSG4_8821C(x) (((x) >> BIT_SHIFT_FW_MSG4_8821C) & BIT_MASK_FW_MSG4_8821C) - - +#define BIT_FW_MSG4_8821C(x) \ + (((x) & BIT_MASK_FW_MSG4_8821C) << BIT_SHIFT_FW_MSG4_8821C) +#define BITS_FW_MSG4_8821C (BIT_MASK_FW_MSG4_8821C << BIT_SHIFT_FW_MSG4_8821C) +#define BIT_CLEAR_FW_MSG4_8821C(x) ((x) & (~BITS_FW_MSG4_8821C)) +#define BIT_GET_FW_MSG4_8821C(x) \ + (((x) >> BIT_SHIFT_FW_MSG4_8821C) & BIT_MASK_FW_MSG4_8821C) +#define BIT_SET_FW_MSG4_8821C(x, v) \ + (BIT_CLEAR_FW_MSG4_8821C(x) | BIT_FW_MSG4_8821C(v)) /* 2 REG_MSG5_8821C */ #define BIT_SHIFT_FW_MSG5_8821C 0 #define BIT_MASK_FW_MSG5_8821C 0xffffffffL -#define BIT_FW_MSG5_8821C(x) (((x) & BIT_MASK_FW_MSG5_8821C) << BIT_SHIFT_FW_MSG5_8821C) -#define BIT_GET_FW_MSG5_8821C(x) (((x) >> BIT_SHIFT_FW_MSG5_8821C) & BIT_MASK_FW_MSG5_8821C) +#define BIT_FW_MSG5_8821C(x) \ + (((x) & BIT_MASK_FW_MSG5_8821C) << BIT_SHIFT_FW_MSG5_8821C) +#define BITS_FW_MSG5_8821C (BIT_MASK_FW_MSG5_8821C << BIT_SHIFT_FW_MSG5_8821C) +#define BIT_CLEAR_FW_MSG5_8821C(x) ((x) & (~BITS_FW_MSG5_8821C)) +#define BIT_GET_FW_MSG5_8821C(x) \ + (((x) >> BIT_SHIFT_FW_MSG5_8821C) & BIT_MASK_FW_MSG5_8821C) +#define BIT_SET_FW_MSG5_8821C(x, v) \ + (BIT_CLEAR_FW_MSG5_8821C(x) | BIT_FW_MSG5_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FIFOPAGE_CTRL_1_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C 16 -#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C 0xff -#define BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) -#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8821C(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C 0 -#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C 0xff -#define BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) -#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8821C(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FIFOPAGE_CTRL_2_8821C */ -#define BIT_BCN_VALID_1_V1_8821C BIT(31) +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_BCN_HEAD_1_V1_8821C 16 -#define BIT_MASK_BCN_HEAD_1_V1_8821C 0xfff -#define BIT_BCN_HEAD_1_V1_8821C(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8821C) << BIT_SHIFT_BCN_HEAD_1_V1_8821C) -#define BIT_GET_BCN_HEAD_1_V1_8821C(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8821C) & BIT_MASK_BCN_HEAD_1_V1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_BCN_VALID_V1_8821C BIT(15) +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_BCN_HEAD_V1_8821C 0 -#define BIT_MASK_BCN_HEAD_V1_8821C 0xfff -#define BIT_BCN_HEAD_V1_8821C(x) (((x) & BIT_MASK_BCN_HEAD_V1_8821C) << BIT_SHIFT_BCN_HEAD_V1_8821C) -#define BIT_GET_BCN_HEAD_V1_8821C(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8821C) & BIT_MASK_BCN_HEAD_V1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_AUTO_LLT_V1_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 24 -#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 0xff -#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) -#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_LLT_FREE_PAGE_V1_8821C 8 -#define BIT_MASK_LLT_FREE_PAGE_V1_8821C 0xffff -#define BIT_LLT_FREE_PAGE_V1_8821C(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8821C) << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) -#define BIT_GET_LLT_FREE_PAGE_V1_8821C(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) & BIT_MASK_LLT_FREE_PAGE_V1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_BLK_DESC_NUM_8821C 4 -#define BIT_MASK_BLK_DESC_NUM_8821C 0xf -#define BIT_BLK_DESC_NUM_8821C(x) (((x) & BIT_MASK_BLK_DESC_NUM_8821C) << BIT_SHIFT_BLK_DESC_NUM_8821C) -#define BIT_GET_BLK_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8821C) & BIT_MASK_BLK_DESC_NUM_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_R_BCN_HEAD_SEL_8821C BIT(3) +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_FIFOPAGE_CTRL_1_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C 16 +#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C 0xff +#define BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(x) \ + (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) +#define BITS_TX_OQT_HE_FREE_SPACE_V1_8821C \ + (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8821C(x) \ + ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8821C)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) & \ + BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) +#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8821C(x, v) \ + (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8821C(x) | \ + BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(v)) + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C 0 +#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C 0xff +#define BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(x) \ + (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) +#define BITS_TX_OQT_NL_FREE_SPACE_V1_8821C \ + (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8821C(x) \ + ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8821C)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) & \ + BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) +#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8821C(x, v) \ + (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8821C(x) | \ + BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(v)) + +/* 2 REG_FIFOPAGE_CTRL_2_8821C */ +#define BIT_BCN_VALID_1_V1_8821C BIT(31) + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_BCN_HEAD_1_V1_8821C 16 +#define BIT_MASK_BCN_HEAD_1_V1_8821C 0xfff +#define BIT_BCN_HEAD_1_V1_8821C(x) \ + (((x) & BIT_MASK_BCN_HEAD_1_V1_8821C) << BIT_SHIFT_BCN_HEAD_1_V1_8821C) +#define BITS_BCN_HEAD_1_V1_8821C \ + (BIT_MASK_BCN_HEAD_1_V1_8821C << BIT_SHIFT_BCN_HEAD_1_V1_8821C) +#define BIT_CLEAR_BCN_HEAD_1_V1_8821C(x) ((x) & (~BITS_BCN_HEAD_1_V1_8821C)) +#define BIT_GET_BCN_HEAD_1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8821C) & BIT_MASK_BCN_HEAD_1_V1_8821C) +#define BIT_SET_BCN_HEAD_1_V1_8821C(x, v) \ + (BIT_CLEAR_BCN_HEAD_1_V1_8821C(x) | BIT_BCN_HEAD_1_V1_8821C(v)) + +#define BIT_BCN_VALID_V1_8821C BIT(15) + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_BCN_HEAD_V1_8821C 0 +#define BIT_MASK_BCN_HEAD_V1_8821C 0xfff +#define BIT_BCN_HEAD_V1_8821C(x) \ + (((x) & BIT_MASK_BCN_HEAD_V1_8821C) << BIT_SHIFT_BCN_HEAD_V1_8821C) +#define BITS_BCN_HEAD_V1_8821C \ + (BIT_MASK_BCN_HEAD_V1_8821C << BIT_SHIFT_BCN_HEAD_V1_8821C) +#define BIT_CLEAR_BCN_HEAD_V1_8821C(x) ((x) & (~BITS_BCN_HEAD_V1_8821C)) +#define BIT_GET_BCN_HEAD_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_V1_8821C) & BIT_MASK_BCN_HEAD_V1_8821C) +#define BIT_SET_BCN_HEAD_V1_8821C(x, v) \ + (BIT_CLEAR_BCN_HEAD_V1_8821C(x) | BIT_BCN_HEAD_V1_8821C(v)) + +/* 2 REG_AUTO_LLT_V1_8821C */ + +#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 24 +#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 0xff +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) +#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C \ + (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) +#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) \ + ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) & \ + BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) +#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) | \ + BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(v)) + +#define BIT_SHIFT_LLT_FREE_PAGE_V1_8821C 8 +#define BIT_MASK_LLT_FREE_PAGE_V1_8821C 0xffff +#define BIT_LLT_FREE_PAGE_V1_8821C(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8821C) \ + << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) +#define BITS_LLT_FREE_PAGE_V1_8821C \ + (BIT_MASK_LLT_FREE_PAGE_V1_8821C << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) +#define BIT_CLEAR_LLT_FREE_PAGE_V1_8821C(x) \ + ((x) & (~BITS_LLT_FREE_PAGE_V1_8821C)) +#define BIT_GET_LLT_FREE_PAGE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) & \ + BIT_MASK_LLT_FREE_PAGE_V1_8821C) +#define BIT_SET_LLT_FREE_PAGE_V1_8821C(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V1_8821C(x) | BIT_LLT_FREE_PAGE_V1_8821C(v)) + +#define BIT_SHIFT_BLK_DESC_NUM_8821C 4 +#define BIT_MASK_BLK_DESC_NUM_8821C 0xf +#define BIT_BLK_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_BLK_DESC_NUM_8821C) << BIT_SHIFT_BLK_DESC_NUM_8821C) +#define BITS_BLK_DESC_NUM_8821C \ + (BIT_MASK_BLK_DESC_NUM_8821C << BIT_SHIFT_BLK_DESC_NUM_8821C) +#define BIT_CLEAR_BLK_DESC_NUM_8821C(x) ((x) & (~BITS_BLK_DESC_NUM_8821C)) +#define BIT_GET_BLK_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_BLK_DESC_NUM_8821C) & BIT_MASK_BLK_DESC_NUM_8821C) +#define BIT_SET_BLK_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_BLK_DESC_NUM_8821C(x) | BIT_BLK_DESC_NUM_8821C(v)) + +#define BIT_R_BCN_HEAD_SEL_8821C BIT(3) #define BIT_R_EN_BCN_SW_HEAD_SEL_8821C BIT(2) #define BIT_LLT_DBG_SEL_8821C BIT(1) #define BIT_AUTO_INIT_LLT_V1_8821C BIT(0) @@ -3614,10 +5912,17 @@ #define BIT_SHIFT_PG_UNDER_TH_V1_8821C 16 #define BIT_MASK_PG_UNDER_TH_V1_8821C 0xfff -#define BIT_PG_UNDER_TH_V1_8821C(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8821C) << BIT_SHIFT_PG_UNDER_TH_V1_8821C) -#define BIT_GET_PG_UNDER_TH_V1_8821C(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8821C) & BIT_MASK_PG_UNDER_TH_V1_8821C) - - +#define BIT_PG_UNDER_TH_V1_8821C(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V1_8821C) \ + << BIT_SHIFT_PG_UNDER_TH_V1_8821C) +#define BITS_PG_UNDER_TH_V1_8821C \ + (BIT_MASK_PG_UNDER_TH_V1_8821C << BIT_SHIFT_PG_UNDER_TH_V1_8821C) +#define BIT_CLEAR_PG_UNDER_TH_V1_8821C(x) ((x) & (~BITS_PG_UNDER_TH_V1_8821C)) +#define BIT_GET_PG_UNDER_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8821C) & \ + BIT_MASK_PG_UNDER_TH_V1_8821C) +#define BIT_SET_PG_UNDER_TH_V1_8821C(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V1_8821C(x) | BIT_PG_UNDER_TH_V1_8821C(v)) /* 2 REG_NOT_VALID_8821C */ #define BIT_SDIO_TXDESC_CHKSUM_EN_8821C BIT(13) @@ -3629,10 +5934,15 @@ #define BIT_SHIFT_CHECK_OFFSET_8821C 0 #define BIT_MASK_CHECK_OFFSET_8821C 0xff -#define BIT_CHECK_OFFSET_8821C(x) (((x) & BIT_MASK_CHECK_OFFSET_8821C) << BIT_SHIFT_CHECK_OFFSET_8821C) -#define BIT_GET_CHECK_OFFSET_8821C(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8821C) & BIT_MASK_CHECK_OFFSET_8821C) - - +#define BIT_CHECK_OFFSET_8821C(x) \ + (((x) & BIT_MASK_CHECK_OFFSET_8821C) << BIT_SHIFT_CHECK_OFFSET_8821C) +#define BITS_CHECK_OFFSET_8821C \ + (BIT_MASK_CHECK_OFFSET_8821C << BIT_SHIFT_CHECK_OFFSET_8821C) +#define BIT_CLEAR_CHECK_OFFSET_8821C(x) ((x) & (~BITS_CHECK_OFFSET_8821C)) +#define BIT_GET_CHECK_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_CHECK_OFFSET_8821C) & BIT_MASK_CHECK_OFFSET_8821C) +#define BIT_SET_CHECK_OFFSET_8821C(x, v) \ + (BIT_CLEAR_CHECK_OFFSET_8821C(x) | BIT_CHECK_OFFSET_8821C(v)) /* 2 REG_TXDMA_STATUS_8821C */ #define BIT_TXPKTBUF_REQ_ERR_8821C BIT(18) @@ -3658,84 +5968,146 @@ /* 2 REG_TX_DMA_DBG_8821C */ /* 2 REG_TQPNT1_8821C */ +#define BIT_HPQ_INT_EN_8821C BIT(31) #define BIT_SHIFT_HPQ_HIGH_TH_V1_8821C 16 #define BIT_MASK_HPQ_HIGH_TH_V1_8821C 0xfff -#define BIT_HPQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8821C) << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) -#define BIT_GET_HPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) & BIT_MASK_HPQ_HIGH_TH_V1_8821C) - - +#define BIT_HPQ_HIGH_TH_V1_8821C(x) \ + (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8821C) \ + << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) +#define BITS_HPQ_HIGH_TH_V1_8821C \ + (BIT_MASK_HPQ_HIGH_TH_V1_8821C << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) +#define BIT_CLEAR_HPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8821C)) +#define BIT_GET_HPQ_HIGH_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) & \ + BIT_MASK_HPQ_HIGH_TH_V1_8821C) +#define BIT_SET_HPQ_HIGH_TH_V1_8821C(x, v) \ + (BIT_CLEAR_HPQ_HIGH_TH_V1_8821C(x) | BIT_HPQ_HIGH_TH_V1_8821C(v)) #define BIT_SHIFT_HPQ_LOW_TH_V1_8821C 0 #define BIT_MASK_HPQ_LOW_TH_V1_8821C 0xfff -#define BIT_HPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8821C) << BIT_SHIFT_HPQ_LOW_TH_V1_8821C) -#define BIT_GET_HPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8821C) & BIT_MASK_HPQ_LOW_TH_V1_8821C) - - +#define BIT_HPQ_LOW_TH_V1_8821C(x) \ + (((x) & BIT_MASK_HPQ_LOW_TH_V1_8821C) << BIT_SHIFT_HPQ_LOW_TH_V1_8821C) +#define BITS_HPQ_LOW_TH_V1_8821C \ + (BIT_MASK_HPQ_LOW_TH_V1_8821C << BIT_SHIFT_HPQ_LOW_TH_V1_8821C) +#define BIT_CLEAR_HPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8821C)) +#define BIT_GET_HPQ_LOW_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8821C) & BIT_MASK_HPQ_LOW_TH_V1_8821C) +#define BIT_SET_HPQ_LOW_TH_V1_8821C(x, v) \ + (BIT_CLEAR_HPQ_LOW_TH_V1_8821C(x) | BIT_HPQ_LOW_TH_V1_8821C(v)) /* 2 REG_TQPNT2_8821C */ +#define BIT_NPQ_INT_EN_8821C BIT(31) #define BIT_SHIFT_NPQ_HIGH_TH_V1_8821C 16 #define BIT_MASK_NPQ_HIGH_TH_V1_8821C 0xfff -#define BIT_NPQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8821C) << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) -#define BIT_GET_NPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) & BIT_MASK_NPQ_HIGH_TH_V1_8821C) - - +#define BIT_NPQ_HIGH_TH_V1_8821C(x) \ + (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8821C) \ + << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) +#define BITS_NPQ_HIGH_TH_V1_8821C \ + (BIT_MASK_NPQ_HIGH_TH_V1_8821C << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) +#define BIT_CLEAR_NPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8821C)) +#define BIT_GET_NPQ_HIGH_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) & \ + BIT_MASK_NPQ_HIGH_TH_V1_8821C) +#define BIT_SET_NPQ_HIGH_TH_V1_8821C(x, v) \ + (BIT_CLEAR_NPQ_HIGH_TH_V1_8821C(x) | BIT_NPQ_HIGH_TH_V1_8821C(v)) #define BIT_SHIFT_NPQ_LOW_TH_V1_8821C 0 #define BIT_MASK_NPQ_LOW_TH_V1_8821C 0xfff -#define BIT_NPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8821C) << BIT_SHIFT_NPQ_LOW_TH_V1_8821C) -#define BIT_GET_NPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8821C) & BIT_MASK_NPQ_LOW_TH_V1_8821C) - - +#define BIT_NPQ_LOW_TH_V1_8821C(x) \ + (((x) & BIT_MASK_NPQ_LOW_TH_V1_8821C) << BIT_SHIFT_NPQ_LOW_TH_V1_8821C) +#define BITS_NPQ_LOW_TH_V1_8821C \ + (BIT_MASK_NPQ_LOW_TH_V1_8821C << BIT_SHIFT_NPQ_LOW_TH_V1_8821C) +#define BIT_CLEAR_NPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8821C)) +#define BIT_GET_NPQ_LOW_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8821C) & BIT_MASK_NPQ_LOW_TH_V1_8821C) +#define BIT_SET_NPQ_LOW_TH_V1_8821C(x, v) \ + (BIT_CLEAR_NPQ_LOW_TH_V1_8821C(x) | BIT_NPQ_LOW_TH_V1_8821C(v)) /* 2 REG_TQPNT3_8821C */ +#define BIT_LPQ_INT_EN_8821C BIT(31) #define BIT_SHIFT_LPQ_HIGH_TH_V1_8821C 16 #define BIT_MASK_LPQ_HIGH_TH_V1_8821C 0xfff -#define BIT_LPQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8821C) << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) -#define BIT_GET_LPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) & BIT_MASK_LPQ_HIGH_TH_V1_8821C) - - +#define BIT_LPQ_HIGH_TH_V1_8821C(x) \ + (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8821C) \ + << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) +#define BITS_LPQ_HIGH_TH_V1_8821C \ + (BIT_MASK_LPQ_HIGH_TH_V1_8821C << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) +#define BIT_CLEAR_LPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8821C)) +#define BIT_GET_LPQ_HIGH_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) & \ + BIT_MASK_LPQ_HIGH_TH_V1_8821C) +#define BIT_SET_LPQ_HIGH_TH_V1_8821C(x, v) \ + (BIT_CLEAR_LPQ_HIGH_TH_V1_8821C(x) | BIT_LPQ_HIGH_TH_V1_8821C(v)) #define BIT_SHIFT_LPQ_LOW_TH_V1_8821C 0 #define BIT_MASK_LPQ_LOW_TH_V1_8821C 0xfff -#define BIT_LPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8821C) << BIT_SHIFT_LPQ_LOW_TH_V1_8821C) -#define BIT_GET_LPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8821C) & BIT_MASK_LPQ_LOW_TH_V1_8821C) - - +#define BIT_LPQ_LOW_TH_V1_8821C(x) \ + (((x) & BIT_MASK_LPQ_LOW_TH_V1_8821C) << BIT_SHIFT_LPQ_LOW_TH_V1_8821C) +#define BITS_LPQ_LOW_TH_V1_8821C \ + (BIT_MASK_LPQ_LOW_TH_V1_8821C << BIT_SHIFT_LPQ_LOW_TH_V1_8821C) +#define BIT_CLEAR_LPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8821C)) +#define BIT_GET_LPQ_LOW_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8821C) & BIT_MASK_LPQ_LOW_TH_V1_8821C) +#define BIT_SET_LPQ_LOW_TH_V1_8821C(x, v) \ + (BIT_CLEAR_LPQ_LOW_TH_V1_8821C(x) | BIT_LPQ_LOW_TH_V1_8821C(v)) /* 2 REG_TQPNT4_8821C */ +#define BIT_EXQ_INT_EN_8821C BIT(31) #define BIT_SHIFT_EXQ_HIGH_TH_V1_8821C 16 #define BIT_MASK_EXQ_HIGH_TH_V1_8821C 0xfff -#define BIT_EXQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8821C) << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) -#define BIT_GET_EXQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) & BIT_MASK_EXQ_HIGH_TH_V1_8821C) - - +#define BIT_EXQ_HIGH_TH_V1_8821C(x) \ + (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8821C) \ + << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) +#define BITS_EXQ_HIGH_TH_V1_8821C \ + (BIT_MASK_EXQ_HIGH_TH_V1_8821C << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) +#define BIT_CLEAR_EXQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8821C)) +#define BIT_GET_EXQ_HIGH_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) & \ + BIT_MASK_EXQ_HIGH_TH_V1_8821C) +#define BIT_SET_EXQ_HIGH_TH_V1_8821C(x, v) \ + (BIT_CLEAR_EXQ_HIGH_TH_V1_8821C(x) | BIT_EXQ_HIGH_TH_V1_8821C(v)) #define BIT_SHIFT_EXQ_LOW_TH_V1_8821C 0 #define BIT_MASK_EXQ_LOW_TH_V1_8821C 0xfff -#define BIT_EXQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8821C) << BIT_SHIFT_EXQ_LOW_TH_V1_8821C) -#define BIT_GET_EXQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8821C) & BIT_MASK_EXQ_LOW_TH_V1_8821C) - - +#define BIT_EXQ_LOW_TH_V1_8821C(x) \ + (((x) & BIT_MASK_EXQ_LOW_TH_V1_8821C) << BIT_SHIFT_EXQ_LOW_TH_V1_8821C) +#define BITS_EXQ_LOW_TH_V1_8821C \ + (BIT_MASK_EXQ_LOW_TH_V1_8821C << BIT_SHIFT_EXQ_LOW_TH_V1_8821C) +#define BIT_CLEAR_EXQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8821C)) +#define BIT_GET_EXQ_LOW_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8821C) & BIT_MASK_EXQ_LOW_TH_V1_8821C) +#define BIT_SET_EXQ_LOW_TH_V1_8821C(x, v) \ + (BIT_CLEAR_EXQ_LOW_TH_V1_8821C(x) | BIT_EXQ_LOW_TH_V1_8821C(v)) /* 2 REG_RQPN_CTRL_1_8821C */ #define BIT_SHIFT_TXPKTNUM_H_8821C 16 #define BIT_MASK_TXPKTNUM_H_8821C 0xffff -#define BIT_TXPKTNUM_H_8821C(x) (((x) & BIT_MASK_TXPKTNUM_H_8821C) << BIT_SHIFT_TXPKTNUM_H_8821C) -#define BIT_GET_TXPKTNUM_H_8821C(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8821C) & BIT_MASK_TXPKTNUM_H_8821C) - - +#define BIT_TXPKTNUM_H_8821C(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_8821C) << BIT_SHIFT_TXPKTNUM_H_8821C) +#define BITS_TXPKTNUM_H_8821C \ + (BIT_MASK_TXPKTNUM_H_8821C << BIT_SHIFT_TXPKTNUM_H_8821C) +#define BIT_CLEAR_TXPKTNUM_H_8821C(x) ((x) & (~BITS_TXPKTNUM_H_8821C)) +#define BIT_GET_TXPKTNUM_H_8821C(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_8821C) & BIT_MASK_TXPKTNUM_H_8821C) +#define BIT_SET_TXPKTNUM_H_8821C(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_8821C(x) | BIT_TXPKTNUM_H_8821C(v)) #define BIT_SHIFT_TXPKTNUM_V2_8821C 0 #define BIT_MASK_TXPKTNUM_V2_8821C 0xffff -#define BIT_TXPKTNUM_V2_8821C(x) (((x) & BIT_MASK_TXPKTNUM_V2_8821C) << BIT_SHIFT_TXPKTNUM_V2_8821C) -#define BIT_GET_TXPKTNUM_V2_8821C(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2_8821C) & BIT_MASK_TXPKTNUM_V2_8821C) - - +#define BIT_TXPKTNUM_V2_8821C(x) \ + (((x) & BIT_MASK_TXPKTNUM_V2_8821C) << BIT_SHIFT_TXPKTNUM_V2_8821C) +#define BITS_TXPKTNUM_V2_8821C \ + (BIT_MASK_TXPKTNUM_V2_8821C << BIT_SHIFT_TXPKTNUM_V2_8821C) +#define BIT_CLEAR_TXPKTNUM_V2_8821C(x) ((x) & (~BITS_TXPKTNUM_V2_8821C)) +#define BIT_GET_TXPKTNUM_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_V2_8821C) & BIT_MASK_TXPKTNUM_V2_8821C) +#define BIT_SET_TXPKTNUM_V2_8821C(x, v) \ + (BIT_CLEAR_TXPKTNUM_V2_8821C(x) | BIT_TXPKTNUM_V2_8821C(v)) /* 2 REG_RQPN_CTRL_2_8821C */ #define BIT_LD_RQPN_8821C BIT(31) @@ -3747,126 +6119,211 @@ #define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C 0 #define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C 0xfff -#define BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(x) (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) -#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8821C(x) (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) - - +#define BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(x) \ + (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) +#define BITS_SDIO_TXAGG_ALIGN_SIZE_8821C \ + (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) +#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8821C(x) \ + ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_8821C)) +#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) & \ + BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) +#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_8821C(x, v) \ + (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8821C(x) | \ + BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(v)) /* 2 REG_FIFOPAGE_INFO_1_8821C */ #define BIT_SHIFT_HPQ_AVAL_PG_V1_8821C 16 #define BIT_MASK_HPQ_AVAL_PG_V1_8821C 0xfff -#define BIT_HPQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8821C) << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) -#define BIT_GET_HPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) & BIT_MASK_HPQ_AVAL_PG_V1_8821C) - - +#define BIT_HPQ_AVAL_PG_V1_8821C(x) \ + (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8821C) \ + << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) +#define BITS_HPQ_AVAL_PG_V1_8821C \ + (BIT_MASK_HPQ_AVAL_PG_V1_8821C << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) +#define BIT_CLEAR_HPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8821C)) +#define BIT_GET_HPQ_AVAL_PG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) & \ + BIT_MASK_HPQ_AVAL_PG_V1_8821C) +#define BIT_SET_HPQ_AVAL_PG_V1_8821C(x, v) \ + (BIT_CLEAR_HPQ_AVAL_PG_V1_8821C(x) | BIT_HPQ_AVAL_PG_V1_8821C(v)) #define BIT_SHIFT_HPQ_V1_8821C 0 #define BIT_MASK_HPQ_V1_8821C 0xfff -#define BIT_HPQ_V1_8821C(x) (((x) & BIT_MASK_HPQ_V1_8821C) << BIT_SHIFT_HPQ_V1_8821C) -#define BIT_GET_HPQ_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_V1_8821C) & BIT_MASK_HPQ_V1_8821C) - - +#define BIT_HPQ_V1_8821C(x) \ + (((x) & BIT_MASK_HPQ_V1_8821C) << BIT_SHIFT_HPQ_V1_8821C) +#define BITS_HPQ_V1_8821C (BIT_MASK_HPQ_V1_8821C << BIT_SHIFT_HPQ_V1_8821C) +#define BIT_CLEAR_HPQ_V1_8821C(x) ((x) & (~BITS_HPQ_V1_8821C)) +#define BIT_GET_HPQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HPQ_V1_8821C) & BIT_MASK_HPQ_V1_8821C) +#define BIT_SET_HPQ_V1_8821C(x, v) \ + (BIT_CLEAR_HPQ_V1_8821C(x) | BIT_HPQ_V1_8821C(v)) /* 2 REG_FIFOPAGE_INFO_2_8821C */ #define BIT_SHIFT_LPQ_AVAL_PG_V1_8821C 16 #define BIT_MASK_LPQ_AVAL_PG_V1_8821C 0xfff -#define BIT_LPQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8821C) << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) -#define BIT_GET_LPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) & BIT_MASK_LPQ_AVAL_PG_V1_8821C) - - +#define BIT_LPQ_AVAL_PG_V1_8821C(x) \ + (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8821C) \ + << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) +#define BITS_LPQ_AVAL_PG_V1_8821C \ + (BIT_MASK_LPQ_AVAL_PG_V1_8821C << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) +#define BIT_CLEAR_LPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8821C)) +#define BIT_GET_LPQ_AVAL_PG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) & \ + BIT_MASK_LPQ_AVAL_PG_V1_8821C) +#define BIT_SET_LPQ_AVAL_PG_V1_8821C(x, v) \ + (BIT_CLEAR_LPQ_AVAL_PG_V1_8821C(x) | BIT_LPQ_AVAL_PG_V1_8821C(v)) #define BIT_SHIFT_LPQ_V1_8821C 0 #define BIT_MASK_LPQ_V1_8821C 0xfff -#define BIT_LPQ_V1_8821C(x) (((x) & BIT_MASK_LPQ_V1_8821C) << BIT_SHIFT_LPQ_V1_8821C) -#define BIT_GET_LPQ_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_V1_8821C) & BIT_MASK_LPQ_V1_8821C) - - +#define BIT_LPQ_V1_8821C(x) \ + (((x) & BIT_MASK_LPQ_V1_8821C) << BIT_SHIFT_LPQ_V1_8821C) +#define BITS_LPQ_V1_8821C (BIT_MASK_LPQ_V1_8821C << BIT_SHIFT_LPQ_V1_8821C) +#define BIT_CLEAR_LPQ_V1_8821C(x) ((x) & (~BITS_LPQ_V1_8821C)) +#define BIT_GET_LPQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LPQ_V1_8821C) & BIT_MASK_LPQ_V1_8821C) +#define BIT_SET_LPQ_V1_8821C(x, v) \ + (BIT_CLEAR_LPQ_V1_8821C(x) | BIT_LPQ_V1_8821C(v)) /* 2 REG_FIFOPAGE_INFO_3_8821C */ #define BIT_SHIFT_NPQ_AVAL_PG_V1_8821C 16 #define BIT_MASK_NPQ_AVAL_PG_V1_8821C 0xfff -#define BIT_NPQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8821C) << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) -#define BIT_GET_NPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) & BIT_MASK_NPQ_AVAL_PG_V1_8821C) - - +#define BIT_NPQ_AVAL_PG_V1_8821C(x) \ + (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8821C) \ + << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) +#define BITS_NPQ_AVAL_PG_V1_8821C \ + (BIT_MASK_NPQ_AVAL_PG_V1_8821C << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) +#define BIT_CLEAR_NPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8821C)) +#define BIT_GET_NPQ_AVAL_PG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) & \ + BIT_MASK_NPQ_AVAL_PG_V1_8821C) +#define BIT_SET_NPQ_AVAL_PG_V1_8821C(x, v) \ + (BIT_CLEAR_NPQ_AVAL_PG_V1_8821C(x) | BIT_NPQ_AVAL_PG_V1_8821C(v)) #define BIT_SHIFT_NPQ_V1_8821C 0 #define BIT_MASK_NPQ_V1_8821C 0xfff -#define BIT_NPQ_V1_8821C(x) (((x) & BIT_MASK_NPQ_V1_8821C) << BIT_SHIFT_NPQ_V1_8821C) -#define BIT_GET_NPQ_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_V1_8821C) & BIT_MASK_NPQ_V1_8821C) - - +#define BIT_NPQ_V1_8821C(x) \ + (((x) & BIT_MASK_NPQ_V1_8821C) << BIT_SHIFT_NPQ_V1_8821C) +#define BITS_NPQ_V1_8821C (BIT_MASK_NPQ_V1_8821C << BIT_SHIFT_NPQ_V1_8821C) +#define BIT_CLEAR_NPQ_V1_8821C(x) ((x) & (~BITS_NPQ_V1_8821C)) +#define BIT_GET_NPQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NPQ_V1_8821C) & BIT_MASK_NPQ_V1_8821C) +#define BIT_SET_NPQ_V1_8821C(x, v) \ + (BIT_CLEAR_NPQ_V1_8821C(x) | BIT_NPQ_V1_8821C(v)) /* 2 REG_FIFOPAGE_INFO_4_8821C */ #define BIT_SHIFT_EXQ_AVAL_PG_V1_8821C 16 #define BIT_MASK_EXQ_AVAL_PG_V1_8821C 0xfff -#define BIT_EXQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8821C) << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) -#define BIT_GET_EXQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) & BIT_MASK_EXQ_AVAL_PG_V1_8821C) - - +#define BIT_EXQ_AVAL_PG_V1_8821C(x) \ + (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8821C) \ + << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) +#define BITS_EXQ_AVAL_PG_V1_8821C \ + (BIT_MASK_EXQ_AVAL_PG_V1_8821C << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) +#define BIT_CLEAR_EXQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8821C)) +#define BIT_GET_EXQ_AVAL_PG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) & \ + BIT_MASK_EXQ_AVAL_PG_V1_8821C) +#define BIT_SET_EXQ_AVAL_PG_V1_8821C(x, v) \ + (BIT_CLEAR_EXQ_AVAL_PG_V1_8821C(x) | BIT_EXQ_AVAL_PG_V1_8821C(v)) #define BIT_SHIFT_EXQ_V1_8821C 0 #define BIT_MASK_EXQ_V1_8821C 0xfff -#define BIT_EXQ_V1_8821C(x) (((x) & BIT_MASK_EXQ_V1_8821C) << BIT_SHIFT_EXQ_V1_8821C) -#define BIT_GET_EXQ_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_V1_8821C) & BIT_MASK_EXQ_V1_8821C) - - +#define BIT_EXQ_V1_8821C(x) \ + (((x) & BIT_MASK_EXQ_V1_8821C) << BIT_SHIFT_EXQ_V1_8821C) +#define BITS_EXQ_V1_8821C (BIT_MASK_EXQ_V1_8821C << BIT_SHIFT_EXQ_V1_8821C) +#define BIT_CLEAR_EXQ_V1_8821C(x) ((x) & (~BITS_EXQ_V1_8821C)) +#define BIT_GET_EXQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_EXQ_V1_8821C) & BIT_MASK_EXQ_V1_8821C) +#define BIT_SET_EXQ_V1_8821C(x, v) \ + (BIT_CLEAR_EXQ_V1_8821C(x) | BIT_EXQ_V1_8821C(v)) /* 2 REG_FIFOPAGE_INFO_5_8821C */ #define BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C 16 #define BIT_MASK_PUBQ_AVAL_PG_V1_8821C 0xfff -#define BIT_PUBQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) -#define BIT_GET_PUBQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C) - - +#define BIT_PUBQ_AVAL_PG_V1_8821C(x) \ + (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C) \ + << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) +#define BITS_PUBQ_AVAL_PG_V1_8821C \ + (BIT_MASK_PUBQ_AVAL_PG_V1_8821C << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) +#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8821C)) +#define BIT_GET_PUBQ_AVAL_PG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) & \ + BIT_MASK_PUBQ_AVAL_PG_V1_8821C) +#define BIT_SET_PUBQ_AVAL_PG_V1_8821C(x, v) \ + (BIT_CLEAR_PUBQ_AVAL_PG_V1_8821C(x) | BIT_PUBQ_AVAL_PG_V1_8821C(v)) #define BIT_SHIFT_PUBQ_V1_8821C 0 #define BIT_MASK_PUBQ_V1_8821C 0xfff -#define BIT_PUBQ_V1_8821C(x) (((x) & BIT_MASK_PUBQ_V1_8821C) << BIT_SHIFT_PUBQ_V1_8821C) -#define BIT_GET_PUBQ_V1_8821C(x) (((x) >> BIT_SHIFT_PUBQ_V1_8821C) & BIT_MASK_PUBQ_V1_8821C) - - +#define BIT_PUBQ_V1_8821C(x) \ + (((x) & BIT_MASK_PUBQ_V1_8821C) << BIT_SHIFT_PUBQ_V1_8821C) +#define BITS_PUBQ_V1_8821C (BIT_MASK_PUBQ_V1_8821C << BIT_SHIFT_PUBQ_V1_8821C) +#define BIT_CLEAR_PUBQ_V1_8821C(x) ((x) & (~BITS_PUBQ_V1_8821C)) +#define BIT_GET_PUBQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PUBQ_V1_8821C) & BIT_MASK_PUBQ_V1_8821C) +#define BIT_SET_PUBQ_V1_8821C(x, v) \ + (BIT_CLEAR_PUBQ_V1_8821C(x) | BIT_PUBQ_V1_8821C(v)) /* 2 REG_H2C_HEAD_8821C */ #define BIT_SHIFT_H2C_HEAD_8821C 0 #define BIT_MASK_H2C_HEAD_8821C 0x3ffff -#define BIT_H2C_HEAD_8821C(x) (((x) & BIT_MASK_H2C_HEAD_8821C) << BIT_SHIFT_H2C_HEAD_8821C) -#define BIT_GET_H2C_HEAD_8821C(x) (((x) >> BIT_SHIFT_H2C_HEAD_8821C) & BIT_MASK_H2C_HEAD_8821C) - - +#define BIT_H2C_HEAD_8821C(x) \ + (((x) & BIT_MASK_H2C_HEAD_8821C) << BIT_SHIFT_H2C_HEAD_8821C) +#define BITS_H2C_HEAD_8821C \ + (BIT_MASK_H2C_HEAD_8821C << BIT_SHIFT_H2C_HEAD_8821C) +#define BIT_CLEAR_H2C_HEAD_8821C(x) ((x) & (~BITS_H2C_HEAD_8821C)) +#define BIT_GET_H2C_HEAD_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_8821C) & BIT_MASK_H2C_HEAD_8821C) +#define BIT_SET_H2C_HEAD_8821C(x, v) \ + (BIT_CLEAR_H2C_HEAD_8821C(x) | BIT_H2C_HEAD_8821C(v)) /* 2 REG_H2C_TAIL_8821C */ #define BIT_SHIFT_H2C_TAIL_8821C 0 #define BIT_MASK_H2C_TAIL_8821C 0x3ffff -#define BIT_H2C_TAIL_8821C(x) (((x) & BIT_MASK_H2C_TAIL_8821C) << BIT_SHIFT_H2C_TAIL_8821C) -#define BIT_GET_H2C_TAIL_8821C(x) (((x) >> BIT_SHIFT_H2C_TAIL_8821C) & BIT_MASK_H2C_TAIL_8821C) - - +#define BIT_H2C_TAIL_8821C(x) \ + (((x) & BIT_MASK_H2C_TAIL_8821C) << BIT_SHIFT_H2C_TAIL_8821C) +#define BITS_H2C_TAIL_8821C \ + (BIT_MASK_H2C_TAIL_8821C << BIT_SHIFT_H2C_TAIL_8821C) +#define BIT_CLEAR_H2C_TAIL_8821C(x) ((x) & (~BITS_H2C_TAIL_8821C)) +#define BIT_GET_H2C_TAIL_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_8821C) & BIT_MASK_H2C_TAIL_8821C) +#define BIT_SET_H2C_TAIL_8821C(x, v) \ + (BIT_CLEAR_H2C_TAIL_8821C(x) | BIT_H2C_TAIL_8821C(v)) /* 2 REG_H2C_READ_ADDR_8821C */ #define BIT_SHIFT_H2C_READ_ADDR_8821C 0 #define BIT_MASK_H2C_READ_ADDR_8821C 0x3ffff -#define BIT_H2C_READ_ADDR_8821C(x) (((x) & BIT_MASK_H2C_READ_ADDR_8821C) << BIT_SHIFT_H2C_READ_ADDR_8821C) -#define BIT_GET_H2C_READ_ADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8821C) & BIT_MASK_H2C_READ_ADDR_8821C) - - +#define BIT_H2C_READ_ADDR_8821C(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_8821C) << BIT_SHIFT_H2C_READ_ADDR_8821C) +#define BITS_H2C_READ_ADDR_8821C \ + (BIT_MASK_H2C_READ_ADDR_8821C << BIT_SHIFT_H2C_READ_ADDR_8821C) +#define BIT_CLEAR_H2C_READ_ADDR_8821C(x) ((x) & (~BITS_H2C_READ_ADDR_8821C)) +#define BIT_GET_H2C_READ_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_8821C) & BIT_MASK_H2C_READ_ADDR_8821C) +#define BIT_SET_H2C_READ_ADDR_8821C(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_8821C(x) | BIT_H2C_READ_ADDR_8821C(v)) /* 2 REG_H2C_WR_ADDR_8821C */ #define BIT_SHIFT_H2C_WR_ADDR_8821C 0 #define BIT_MASK_H2C_WR_ADDR_8821C 0x3ffff -#define BIT_H2C_WR_ADDR_8821C(x) (((x) & BIT_MASK_H2C_WR_ADDR_8821C) << BIT_SHIFT_H2C_WR_ADDR_8821C) -#define BIT_GET_H2C_WR_ADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8821C) & BIT_MASK_H2C_WR_ADDR_8821C) - - +#define BIT_H2C_WR_ADDR_8821C(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_8821C) << BIT_SHIFT_H2C_WR_ADDR_8821C) +#define BITS_H2C_WR_ADDR_8821C \ + (BIT_MASK_H2C_WR_ADDR_8821C << BIT_SHIFT_H2C_WR_ADDR_8821C) +#define BIT_CLEAR_H2C_WR_ADDR_8821C(x) ((x) & (~BITS_H2C_WR_ADDR_8821C)) +#define BIT_GET_H2C_WR_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_8821C) & BIT_MASK_H2C_WR_ADDR_8821C) +#define BIT_SET_H2C_WR_ADDR_8821C(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_8821C(x) | BIT_H2C_WR_ADDR_8821C(v)) /* 2 REG_H2C_INFO_8821C */ #define BIT_H2C_SPACE_VLD_8821C BIT(3) @@ -3874,55 +6331,92 @@ #define BIT_SHIFT_H2C_LEN_SEL_8821C 0 #define BIT_MASK_H2C_LEN_SEL_8821C 0x3 -#define BIT_H2C_LEN_SEL_8821C(x) (((x) & BIT_MASK_H2C_LEN_SEL_8821C) << BIT_SHIFT_H2C_LEN_SEL_8821C) -#define BIT_GET_H2C_LEN_SEL_8821C(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8821C) & BIT_MASK_H2C_LEN_SEL_8821C) - - +#define BIT_H2C_LEN_SEL_8821C(x) \ + (((x) & BIT_MASK_H2C_LEN_SEL_8821C) << BIT_SHIFT_H2C_LEN_SEL_8821C) +#define BITS_H2C_LEN_SEL_8821C \ + (BIT_MASK_H2C_LEN_SEL_8821C << BIT_SHIFT_H2C_LEN_SEL_8821C) +#define BIT_CLEAR_H2C_LEN_SEL_8821C(x) ((x) & (~BITS_H2C_LEN_SEL_8821C)) +#define BIT_GET_H2C_LEN_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_LEN_SEL_8821C) & BIT_MASK_H2C_LEN_SEL_8821C) +#define BIT_SET_H2C_LEN_SEL_8821C(x, v) \ + (BIT_CLEAR_H2C_LEN_SEL_8821C(x) | BIT_H2C_LEN_SEL_8821C(v)) /* 2 REG_RXDMA_AGG_PG_TH_8821C */ +#define BIT_USB_RXDMA_AGG_EN_8821C BIT(31) +#define BIT_EN_PRE_CALC_8821C BIT(29) +#define BIT_RXAGG_SW_EN_8821C BIT(28) +#define BIT_RXAGG_SW_TRIG_8821C BIT(27) -#define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C 24 -#define BIT_MASK_RXDMA_AGG_OLD_MOD_8821C 0xff -#define BIT_RXDMA_AGG_OLD_MOD_8821C(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD_8821C) << BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C) -#define BIT_GET_RXDMA_AGG_OLD_MOD_8821C(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C) & BIT_MASK_RXDMA_AGG_OLD_MOD_8821C) - - +/* 2 REG_NOT_VALID_8821C */ #define BIT_SHIFT_PKT_NUM_WOL_8821C 16 #define BIT_MASK_PKT_NUM_WOL_8821C 0xff -#define BIT_PKT_NUM_WOL_8821C(x) (((x) & BIT_MASK_PKT_NUM_WOL_8821C) << BIT_SHIFT_PKT_NUM_WOL_8821C) -#define BIT_GET_PKT_NUM_WOL_8821C(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8821C) & BIT_MASK_PKT_NUM_WOL_8821C) - - - -#define BIT_SHIFT_DMA_AGG_TO_8821C 8 -#define BIT_MASK_DMA_AGG_TO_8821C 0xf -#define BIT_DMA_AGG_TO_8821C(x) (((x) & BIT_MASK_DMA_AGG_TO_8821C) << BIT_SHIFT_DMA_AGG_TO_8821C) -#define BIT_GET_DMA_AGG_TO_8821C(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_8821C) & BIT_MASK_DMA_AGG_TO_8821C) - - - -#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C 0 -#define BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C 0xf -#define BIT_RXDMA_AGG_PG_TH_V1_8821C(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C) -#define BIT_GET_RXDMA_AGG_PG_TH_V1_8821C(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C) - - +#define BIT_PKT_NUM_WOL_8821C(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL_8821C) << BIT_SHIFT_PKT_NUM_WOL_8821C) +#define BITS_PKT_NUM_WOL_8821C \ + (BIT_MASK_PKT_NUM_WOL_8821C << BIT_SHIFT_PKT_NUM_WOL_8821C) +#define BIT_CLEAR_PKT_NUM_WOL_8821C(x) ((x) & (~BITS_PKT_NUM_WOL_8821C)) +#define BIT_GET_PKT_NUM_WOL_8821C(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL_8821C) & BIT_MASK_PKT_NUM_WOL_8821C) +#define BIT_SET_PKT_NUM_WOL_8821C(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL_8821C(x) | BIT_PKT_NUM_WOL_8821C(v)) + +#define BIT_SHIFT_DMA_AGG_TO_V1_8821C 8 +#define BIT_MASK_DMA_AGG_TO_V1_8821C 0xff +#define BIT_DMA_AGG_TO_V1_8821C(x) \ + (((x) & BIT_MASK_DMA_AGG_TO_V1_8821C) << BIT_SHIFT_DMA_AGG_TO_V1_8821C) +#define BITS_DMA_AGG_TO_V1_8821C \ + (BIT_MASK_DMA_AGG_TO_V1_8821C << BIT_SHIFT_DMA_AGG_TO_V1_8821C) +#define BIT_CLEAR_DMA_AGG_TO_V1_8821C(x) ((x) & (~BITS_DMA_AGG_TO_V1_8821C)) +#define BIT_GET_DMA_AGG_TO_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8821C) & BIT_MASK_DMA_AGG_TO_V1_8821C) +#define BIT_SET_DMA_AGG_TO_V1_8821C(x, v) \ + (BIT_CLEAR_DMA_AGG_TO_V1_8821C(x) | BIT_DMA_AGG_TO_V1_8821C(v)) + +#define BIT_SHIFT_RXDMA_AGG_PG_TH_8821C 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_8821C 0xff +#define BIT_RXDMA_AGG_PG_TH_8821C(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8821C) \ + << BIT_SHIFT_RXDMA_AGG_PG_TH_8821C) +#define BITS_RXDMA_AGG_PG_TH_8821C \ + (BIT_MASK_RXDMA_AGG_PG_TH_8821C << BIT_SHIFT_RXDMA_AGG_PG_TH_8821C) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_8821C(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8821C)) +#define BIT_GET_RXDMA_AGG_PG_TH_8821C(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8821C) & \ + BIT_MASK_RXDMA_AGG_PG_TH_8821C) +#define BIT_SET_RXDMA_AGG_PG_TH_8821C(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_8821C(x) | BIT_RXDMA_AGG_PG_TH_8821C(v)) /* 2 REG_RXPKT_NUM_8821C */ #define BIT_SHIFT_RXPKT_NUM_8821C 24 #define BIT_MASK_RXPKT_NUM_8821C 0xff -#define BIT_RXPKT_NUM_8821C(x) (((x) & BIT_MASK_RXPKT_NUM_8821C) << BIT_SHIFT_RXPKT_NUM_8821C) -#define BIT_GET_RXPKT_NUM_8821C(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8821C) & BIT_MASK_RXPKT_NUM_8821C) - - +#define BIT_RXPKT_NUM_8821C(x) \ + (((x) & BIT_MASK_RXPKT_NUM_8821C) << BIT_SHIFT_RXPKT_NUM_8821C) +#define BITS_RXPKT_NUM_8821C \ + (BIT_MASK_RXPKT_NUM_8821C << BIT_SHIFT_RXPKT_NUM_8821C) +#define BIT_CLEAR_RXPKT_NUM_8821C(x) ((x) & (~BITS_RXPKT_NUM_8821C)) +#define BIT_GET_RXPKT_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_8821C) & BIT_MASK_RXPKT_NUM_8821C) +#define BIT_SET_RXPKT_NUM_8821C(x, v) \ + (BIT_CLEAR_RXPKT_NUM_8821C(x) | BIT_RXPKT_NUM_8821C(v)) #define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C 20 #define BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C 0xf -#define BIT_FW_UPD_RDPTR19_TO_16_8821C(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) -#define BIT_GET_FW_UPD_RDPTR19_TO_16_8821C(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) - +#define BIT_FW_UPD_RDPTR19_TO_16_8821C(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) +#define BITS_FW_UPD_RDPTR19_TO_16_8821C \ + (BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8821C(x) \ + ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8821C)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8821C(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) & \ + BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) +#define BIT_SET_FW_UPD_RDPTR19_TO_16_8821C(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8821C(x) | \ + BIT_FW_UPD_RDPTR19_TO_16_8821C(v)) #define BIT_RXDMA_REQ_8821C BIT(19) #define BIT_RW_RELEASE_EN_8821C BIT(18) @@ -3931,10 +6425,15 @@ #define BIT_SHIFT_FW_UPD_RDPTR_8821C 0 #define BIT_MASK_FW_UPD_RDPTR_8821C 0xffff -#define BIT_FW_UPD_RDPTR_8821C(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8821C) << BIT_SHIFT_FW_UPD_RDPTR_8821C) -#define BIT_GET_FW_UPD_RDPTR_8821C(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8821C) & BIT_MASK_FW_UPD_RDPTR_8821C) - - +#define BIT_FW_UPD_RDPTR_8821C(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR_8821C) << BIT_SHIFT_FW_UPD_RDPTR_8821C) +#define BITS_FW_UPD_RDPTR_8821C \ + (BIT_MASK_FW_UPD_RDPTR_8821C << BIT_SHIFT_FW_UPD_RDPTR_8821C) +#define BIT_CLEAR_FW_UPD_RDPTR_8821C(x) ((x) & (~BITS_FW_UPD_RDPTR_8821C)) +#define BIT_GET_FW_UPD_RDPTR_8821C(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8821C) & BIT_MASK_FW_UPD_RDPTR_8821C) +#define BIT_SET_FW_UPD_RDPTR_8821C(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR_8821C(x) | BIT_FW_UPD_RDPTR_8821C(v)) /* 2 REG_RXDMA_STATUS_8821C */ #define BIT_C2H_PKT_OVF_8821C BIT(7) @@ -3949,40 +6448,67 @@ #define BIT_SHIFT_RDE_DEBUG_8821C 0 #define BIT_MASK_RDE_DEBUG_8821C 0xffffffffL -#define BIT_RDE_DEBUG_8821C(x) (((x) & BIT_MASK_RDE_DEBUG_8821C) << BIT_SHIFT_RDE_DEBUG_8821C) -#define BIT_GET_RDE_DEBUG_8821C(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8821C) & BIT_MASK_RDE_DEBUG_8821C) - - +#define BIT_RDE_DEBUG_8821C(x) \ + (((x) & BIT_MASK_RDE_DEBUG_8821C) << BIT_SHIFT_RDE_DEBUG_8821C) +#define BITS_RDE_DEBUG_8821C \ + (BIT_MASK_RDE_DEBUG_8821C << BIT_SHIFT_RDE_DEBUG_8821C) +#define BIT_CLEAR_RDE_DEBUG_8821C(x) ((x) & (~BITS_RDE_DEBUG_8821C)) +#define BIT_GET_RDE_DEBUG_8821C(x) \ + (((x) >> BIT_SHIFT_RDE_DEBUG_8821C) & BIT_MASK_RDE_DEBUG_8821C) +#define BIT_SET_RDE_DEBUG_8821C(x, v) \ + (BIT_CLEAR_RDE_DEBUG_8821C(x) | BIT_RDE_DEBUG_8821C(v)) /* 2 REG_RXDMA_MODE_8821C */ #define BIT_SHIFT_PKTNUM_TH_V2_8821C 24 #define BIT_MASK_PKTNUM_TH_V2_8821C 0x1f -#define BIT_PKTNUM_TH_V2_8821C(x) (((x) & BIT_MASK_PKTNUM_TH_V2_8821C) << BIT_SHIFT_PKTNUM_TH_V2_8821C) -#define BIT_GET_PKTNUM_TH_V2_8821C(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8821C) & BIT_MASK_PKTNUM_TH_V2_8821C) - +#define BIT_PKTNUM_TH_V2_8821C(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V2_8821C) << BIT_SHIFT_PKTNUM_TH_V2_8821C) +#define BITS_PKTNUM_TH_V2_8821C \ + (BIT_MASK_PKTNUM_TH_V2_8821C << BIT_SHIFT_PKTNUM_TH_V2_8821C) +#define BIT_CLEAR_PKTNUM_TH_V2_8821C(x) ((x) & (~BITS_PKTNUM_TH_V2_8821C)) +#define BIT_GET_PKTNUM_TH_V2_8821C(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8821C) & BIT_MASK_PKTNUM_TH_V2_8821C) +#define BIT_SET_PKTNUM_TH_V2_8821C(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V2_8821C(x) | BIT_PKTNUM_TH_V2_8821C(v)) #define BIT_TXBA_BREAK_USBAGG_8821C BIT(23) #define BIT_SHIFT_PKTLEN_PARA_8821C 16 #define BIT_MASK_PKTLEN_PARA_8821C 0x7 -#define BIT_PKTLEN_PARA_8821C(x) (((x) & BIT_MASK_PKTLEN_PARA_8821C) << BIT_SHIFT_PKTLEN_PARA_8821C) -#define BIT_GET_PKTLEN_PARA_8821C(x) (((x) >> BIT_SHIFT_PKTLEN_PARA_8821C) & BIT_MASK_PKTLEN_PARA_8821C) - - +#define BIT_PKTLEN_PARA_8821C(x) \ + (((x) & BIT_MASK_PKTLEN_PARA_8821C) << BIT_SHIFT_PKTLEN_PARA_8821C) +#define BITS_PKTLEN_PARA_8821C \ + (BIT_MASK_PKTLEN_PARA_8821C << BIT_SHIFT_PKTLEN_PARA_8821C) +#define BIT_CLEAR_PKTLEN_PARA_8821C(x) ((x) & (~BITS_PKTLEN_PARA_8821C)) +#define BIT_GET_PKTLEN_PARA_8821C(x) \ + (((x) >> BIT_SHIFT_PKTLEN_PARA_8821C) & BIT_MASK_PKTLEN_PARA_8821C) +#define BIT_SET_PKTLEN_PARA_8821C(x, v) \ + (BIT_CLEAR_PKTLEN_PARA_8821C(x) | BIT_PKTLEN_PARA_8821C(v)) #define BIT_SHIFT_BURST_SIZE_8821C 4 #define BIT_MASK_BURST_SIZE_8821C 0x3 -#define BIT_BURST_SIZE_8821C(x) (((x) & BIT_MASK_BURST_SIZE_8821C) << BIT_SHIFT_BURST_SIZE_8821C) -#define BIT_GET_BURST_SIZE_8821C(x) (((x) >> BIT_SHIFT_BURST_SIZE_8821C) & BIT_MASK_BURST_SIZE_8821C) - - +#define BIT_BURST_SIZE_8821C(x) \ + (((x) & BIT_MASK_BURST_SIZE_8821C) << BIT_SHIFT_BURST_SIZE_8821C) +#define BITS_BURST_SIZE_8821C \ + (BIT_MASK_BURST_SIZE_8821C << BIT_SHIFT_BURST_SIZE_8821C) +#define BIT_CLEAR_BURST_SIZE_8821C(x) ((x) & (~BITS_BURST_SIZE_8821C)) +#define BIT_GET_BURST_SIZE_8821C(x) \ + (((x) >> BIT_SHIFT_BURST_SIZE_8821C) & BIT_MASK_BURST_SIZE_8821C) +#define BIT_SET_BURST_SIZE_8821C(x, v) \ + (BIT_CLEAR_BURST_SIZE_8821C(x) | BIT_BURST_SIZE_8821C(v)) #define BIT_SHIFT_BURST_CNT_8821C 2 #define BIT_MASK_BURST_CNT_8821C 0x3 -#define BIT_BURST_CNT_8821C(x) (((x) & BIT_MASK_BURST_CNT_8821C) << BIT_SHIFT_BURST_CNT_8821C) -#define BIT_GET_BURST_CNT_8821C(x) (((x) >> BIT_SHIFT_BURST_CNT_8821C) & BIT_MASK_BURST_CNT_8821C) - +#define BIT_BURST_CNT_8821C(x) \ + (((x) & BIT_MASK_BURST_CNT_8821C) << BIT_SHIFT_BURST_CNT_8821C) +#define BITS_BURST_CNT_8821C \ + (BIT_MASK_BURST_CNT_8821C << BIT_SHIFT_BURST_CNT_8821C) +#define BIT_CLEAR_BURST_CNT_8821C(x) ((x) & (~BITS_BURST_CNT_8821C)) +#define BIT_GET_BURST_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_BURST_CNT_8821C) & BIT_MASK_BURST_CNT_8821C) +#define BIT_SET_BURST_CNT_8821C(x, v) \ + (BIT_CLEAR_BURST_CNT_8821C(x) | BIT_BURST_CNT_8821C(v)) #define BIT_DMA_MODE_8821C BIT(1) @@ -3990,81 +6516,143 @@ #define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C 24 #define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C 0xf -#define BIT_R_C2H_STR_ADDR_16_TO_19_8821C(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) -#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8821C(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) - +#define BIT_R_C2H_STR_ADDR_16_TO_19_8821C(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) +#define BITS_R_C2H_STR_ADDR_16_TO_19_8821C \ + (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8821C(x) \ + ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8821C)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8821C(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) & \ + BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8821C(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8821C(x) | \ + BIT_R_C2H_STR_ADDR_16_TO_19_8821C(v)) #define BIT_R_C2H_PKT_REQ_8821C BIT(16) #define BIT_SHIFT_R_C2H_STR_ADDR_8821C 0 #define BIT_MASK_R_C2H_STR_ADDR_8821C 0xffff -#define BIT_R_C2H_STR_ADDR_8821C(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8821C) << BIT_SHIFT_R_C2H_STR_ADDR_8821C) -#define BIT_GET_R_C2H_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8821C) & BIT_MASK_R_C2H_STR_ADDR_8821C) - - +#define BIT_R_C2H_STR_ADDR_8821C(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_8821C) \ + << BIT_SHIFT_R_C2H_STR_ADDR_8821C) +#define BITS_R_C2H_STR_ADDR_8821C \ + (BIT_MASK_R_C2H_STR_ADDR_8821C << BIT_SHIFT_R_C2H_STR_ADDR_8821C) +#define BIT_CLEAR_R_C2H_STR_ADDR_8821C(x) ((x) & (~BITS_R_C2H_STR_ADDR_8821C)) +#define BIT_GET_R_C2H_STR_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8821C) & \ + BIT_MASK_R_C2H_STR_ADDR_8821C) +#define BIT_SET_R_C2H_STR_ADDR_8821C(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_8821C(x) | BIT_R_C2H_STR_ADDR_8821C(v)) /* 2 REG_FWFF_C2H_8821C */ #define BIT_SHIFT_C2H_DMA_ADDR_8821C 0 #define BIT_MASK_C2H_DMA_ADDR_8821C 0x3ffff -#define BIT_C2H_DMA_ADDR_8821C(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8821C) << BIT_SHIFT_C2H_DMA_ADDR_8821C) -#define BIT_GET_C2H_DMA_ADDR_8821C(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8821C) & BIT_MASK_C2H_DMA_ADDR_8821C) - - +#define BIT_C2H_DMA_ADDR_8821C(x) \ + (((x) & BIT_MASK_C2H_DMA_ADDR_8821C) << BIT_SHIFT_C2H_DMA_ADDR_8821C) +#define BITS_C2H_DMA_ADDR_8821C \ + (BIT_MASK_C2H_DMA_ADDR_8821C << BIT_SHIFT_C2H_DMA_ADDR_8821C) +#define BIT_CLEAR_C2H_DMA_ADDR_8821C(x) ((x) & (~BITS_C2H_DMA_ADDR_8821C)) +#define BIT_GET_C2H_DMA_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8821C) & BIT_MASK_C2H_DMA_ADDR_8821C) +#define BIT_SET_C2H_DMA_ADDR_8821C(x, v) \ + (BIT_CLEAR_C2H_DMA_ADDR_8821C(x) | BIT_C2H_DMA_ADDR_8821C(v)) /* 2 REG_FWFF_CTRL_8821C */ #define BIT_FWFF_DMAPKT_REQ_8821C BIT(31) #define BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C 16 #define BIT_MASK_FWFF_DMA_PKT_NUM_8821C 0xff -#define BIT_FWFF_DMA_PKT_NUM_8821C(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) -#define BIT_GET_FWFF_DMA_PKT_NUM_8821C(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C) - - +#define BIT_FWFF_DMA_PKT_NUM_8821C(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C) \ + << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) +#define BITS_FWFF_DMA_PKT_NUM_8821C \ + (BIT_MASK_FWFF_DMA_PKT_NUM_8821C << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8821C(x) \ + ((x) & (~BITS_FWFF_DMA_PKT_NUM_8821C)) +#define BIT_GET_FWFF_DMA_PKT_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) & \ + BIT_MASK_FWFF_DMA_PKT_NUM_8821C) +#define BIT_SET_FWFF_DMA_PKT_NUM_8821C(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM_8821C(x) | BIT_FWFF_DMA_PKT_NUM_8821C(v)) #define BIT_SHIFT_FWFF_STR_ADDR_8821C 0 #define BIT_MASK_FWFF_STR_ADDR_8821C 0xffff -#define BIT_FWFF_STR_ADDR_8821C(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8821C) << BIT_SHIFT_FWFF_STR_ADDR_8821C) -#define BIT_GET_FWFF_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8821C) & BIT_MASK_FWFF_STR_ADDR_8821C) - - +#define BIT_FWFF_STR_ADDR_8821C(x) \ + (((x) & BIT_MASK_FWFF_STR_ADDR_8821C) << BIT_SHIFT_FWFF_STR_ADDR_8821C) +#define BITS_FWFF_STR_ADDR_8821C \ + (BIT_MASK_FWFF_STR_ADDR_8821C << BIT_SHIFT_FWFF_STR_ADDR_8821C) +#define BIT_CLEAR_FWFF_STR_ADDR_8821C(x) ((x) & (~BITS_FWFF_STR_ADDR_8821C)) +#define BIT_GET_FWFF_STR_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8821C) & BIT_MASK_FWFF_STR_ADDR_8821C) +#define BIT_SET_FWFF_STR_ADDR_8821C(x, v) \ + (BIT_CLEAR_FWFF_STR_ADDR_8821C(x) | BIT_FWFF_STR_ADDR_8821C(v)) /* 2 REG_FWFF_PKT_INFO_8821C */ #define BIT_SHIFT_FWFF_PKT_QUEUED_8821C 16 #define BIT_MASK_FWFF_PKT_QUEUED_8821C 0xff -#define BIT_FWFF_PKT_QUEUED_8821C(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8821C) << BIT_SHIFT_FWFF_PKT_QUEUED_8821C) -#define BIT_GET_FWFF_PKT_QUEUED_8821C(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8821C) & BIT_MASK_FWFF_PKT_QUEUED_8821C) - - +#define BIT_FWFF_PKT_QUEUED_8821C(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED_8821C) \ + << BIT_SHIFT_FWFF_PKT_QUEUED_8821C) +#define BITS_FWFF_PKT_QUEUED_8821C \ + (BIT_MASK_FWFF_PKT_QUEUED_8821C << BIT_SHIFT_FWFF_PKT_QUEUED_8821C) +#define BIT_CLEAR_FWFF_PKT_QUEUED_8821C(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8821C)) +#define BIT_GET_FWFF_PKT_QUEUED_8821C(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8821C) & \ + BIT_MASK_FWFF_PKT_QUEUED_8821C) +#define BIT_SET_FWFF_PKT_QUEUED_8821C(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED_8821C(x) | BIT_FWFF_PKT_QUEUED_8821C(v)) #define BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C 0 #define BIT_MASK_FWFF_PKT_STR_ADDR_8821C 0xffff -#define BIT_FWFF_PKT_STR_ADDR_8821C(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) -#define BIT_GET_FWFF_PKT_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C) - - +#define BIT_FWFF_PKT_STR_ADDR_8821C(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C) \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) +#define BITS_FWFF_PKT_STR_ADDR_8821C \ + (BIT_MASK_FWFF_PKT_STR_ADDR_8821C << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8821C(x) \ + ((x) & (~BITS_FWFF_PKT_STR_ADDR_8821C)) +#define BIT_GET_FWFF_PKT_STR_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) & \ + BIT_MASK_FWFF_PKT_STR_ADDR_8821C) +#define BIT_SET_FWFF_PKT_STR_ADDR_8821C(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR_8821C(x) | BIT_FWFF_PKT_STR_ADDR_8821C(v)) /* 2 REG_DDMA_CH0SA_8821C */ #define BIT_SHIFT_DDMACH0_SA_8821C 0 #define BIT_MASK_DDMACH0_SA_8821C 0xffffffffL -#define BIT_DDMACH0_SA_8821C(x) (((x) & BIT_MASK_DDMACH0_SA_8821C) << BIT_SHIFT_DDMACH0_SA_8821C) -#define BIT_GET_DDMACH0_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8821C) & BIT_MASK_DDMACH0_SA_8821C) - - +#define BIT_DDMACH0_SA_8821C(x) \ + (((x) & BIT_MASK_DDMACH0_SA_8821C) << BIT_SHIFT_DDMACH0_SA_8821C) +#define BITS_DDMACH0_SA_8821C \ + (BIT_MASK_DDMACH0_SA_8821C << BIT_SHIFT_DDMACH0_SA_8821C) +#define BIT_CLEAR_DDMACH0_SA_8821C(x) ((x) & (~BITS_DDMACH0_SA_8821C)) +#define BIT_GET_DDMACH0_SA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH0_SA_8821C) & BIT_MASK_DDMACH0_SA_8821C) +#define BIT_SET_DDMACH0_SA_8821C(x, v) \ + (BIT_CLEAR_DDMACH0_SA_8821C(x) | BIT_DDMACH0_SA_8821C(v)) /* 2 REG_DDMA_CH0DA_8821C */ #define BIT_SHIFT_DDMACH0_DA_8821C 0 #define BIT_MASK_DDMACH0_DA_8821C 0xffffffffL -#define BIT_DDMACH0_DA_8821C(x) (((x) & BIT_MASK_DDMACH0_DA_8821C) << BIT_SHIFT_DDMACH0_DA_8821C) -#define BIT_GET_DDMACH0_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8821C) & BIT_MASK_DDMACH0_DA_8821C) - - +#define BIT_DDMACH0_DA_8821C(x) \ + (((x) & BIT_MASK_DDMACH0_DA_8821C) << BIT_SHIFT_DDMACH0_DA_8821C) +#define BITS_DDMACH0_DA_8821C \ + (BIT_MASK_DDMACH0_DA_8821C << BIT_SHIFT_DDMACH0_DA_8821C) +#define BIT_CLEAR_DDMACH0_DA_8821C(x) ((x) & (~BITS_DDMACH0_DA_8821C)) +#define BIT_GET_DDMACH0_DA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DA_8821C) & BIT_MASK_DDMACH0_DA_8821C) +#define BIT_SET_DDMACH0_DA_8821C(x, v) \ + (BIT_CLEAR_DDMACH0_DA_8821C(x) | BIT_DDMACH0_DA_8821C(v)) /* 2 REG_DDMA_CH0CTRL_8821C */ #define BIT_DDMACH0_OWN_8821C BIT(31) +#define BIT_DDMACH0_IDMEM_ERR_8821C BIT(30) #define BIT_DDMACH0_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH0_DA_W_DISABLE_8821C BIT(28) #define BIT_DDMACH0_CHKSUM_STS_8821C BIT(27) @@ -4074,31 +6662,47 @@ #define BIT_SHIFT_DDMACH0_DLEN_8821C 0 #define BIT_MASK_DDMACH0_DLEN_8821C 0x3ffff -#define BIT_DDMACH0_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH0_DLEN_8821C) << BIT_SHIFT_DDMACH0_DLEN_8821C) -#define BIT_GET_DDMACH0_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8821C) & BIT_MASK_DDMACH0_DLEN_8821C) - - +#define BIT_DDMACH0_DLEN_8821C(x) \ + (((x) & BIT_MASK_DDMACH0_DLEN_8821C) << BIT_SHIFT_DDMACH0_DLEN_8821C) +#define BITS_DDMACH0_DLEN_8821C \ + (BIT_MASK_DDMACH0_DLEN_8821C << BIT_SHIFT_DDMACH0_DLEN_8821C) +#define BIT_CLEAR_DDMACH0_DLEN_8821C(x) ((x) & (~BITS_DDMACH0_DLEN_8821C)) +#define BIT_GET_DDMACH0_DLEN_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DLEN_8821C) & BIT_MASK_DDMACH0_DLEN_8821C) +#define BIT_SET_DDMACH0_DLEN_8821C(x, v) \ + (BIT_CLEAR_DDMACH0_DLEN_8821C(x) | BIT_DDMACH0_DLEN_8821C(v)) /* 2 REG_DDMA_CH1SA_8821C */ #define BIT_SHIFT_DDMACH1_SA_8821C 0 #define BIT_MASK_DDMACH1_SA_8821C 0xffffffffL -#define BIT_DDMACH1_SA_8821C(x) (((x) & BIT_MASK_DDMACH1_SA_8821C) << BIT_SHIFT_DDMACH1_SA_8821C) -#define BIT_GET_DDMACH1_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8821C) & BIT_MASK_DDMACH1_SA_8821C) - - +#define BIT_DDMACH1_SA_8821C(x) \ + (((x) & BIT_MASK_DDMACH1_SA_8821C) << BIT_SHIFT_DDMACH1_SA_8821C) +#define BITS_DDMACH1_SA_8821C \ + (BIT_MASK_DDMACH1_SA_8821C << BIT_SHIFT_DDMACH1_SA_8821C) +#define BIT_CLEAR_DDMACH1_SA_8821C(x) ((x) & (~BITS_DDMACH1_SA_8821C)) +#define BIT_GET_DDMACH1_SA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH1_SA_8821C) & BIT_MASK_DDMACH1_SA_8821C) +#define BIT_SET_DDMACH1_SA_8821C(x, v) \ + (BIT_CLEAR_DDMACH1_SA_8821C(x) | BIT_DDMACH1_SA_8821C(v)) /* 2 REG_DDMA_CH1DA_8821C */ #define BIT_SHIFT_DDMACH1_DA_8821C 0 #define BIT_MASK_DDMACH1_DA_8821C 0xffffffffL -#define BIT_DDMACH1_DA_8821C(x) (((x) & BIT_MASK_DDMACH1_DA_8821C) << BIT_SHIFT_DDMACH1_DA_8821C) -#define BIT_GET_DDMACH1_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8821C) & BIT_MASK_DDMACH1_DA_8821C) - - +#define BIT_DDMACH1_DA_8821C(x) \ + (((x) & BIT_MASK_DDMACH1_DA_8821C) << BIT_SHIFT_DDMACH1_DA_8821C) +#define BITS_DDMACH1_DA_8821C \ + (BIT_MASK_DDMACH1_DA_8821C << BIT_SHIFT_DDMACH1_DA_8821C) +#define BIT_CLEAR_DDMACH1_DA_8821C(x) ((x) & (~BITS_DDMACH1_DA_8821C)) +#define BIT_GET_DDMACH1_DA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DA_8821C) & BIT_MASK_DDMACH1_DA_8821C) +#define BIT_SET_DDMACH1_DA_8821C(x, v) \ + (BIT_CLEAR_DDMACH1_DA_8821C(x) | BIT_DDMACH1_DA_8821C(v)) /* 2 REG_DDMA_CH1CTRL_8821C */ #define BIT_DDMACH1_OWN_8821C BIT(31) +#define BIT_DDMACH1_IDMEM_ERR_8821C BIT(30) #define BIT_DDMACH1_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH1_DA_W_DISABLE_8821C BIT(28) #define BIT_DDMACH1_CHKSUM_STS_8821C BIT(27) @@ -4108,31 +6712,47 @@ #define BIT_SHIFT_DDMACH1_DLEN_8821C 0 #define BIT_MASK_DDMACH1_DLEN_8821C 0x3ffff -#define BIT_DDMACH1_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH1_DLEN_8821C) << BIT_SHIFT_DDMACH1_DLEN_8821C) -#define BIT_GET_DDMACH1_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8821C) & BIT_MASK_DDMACH1_DLEN_8821C) - - +#define BIT_DDMACH1_DLEN_8821C(x) \ + (((x) & BIT_MASK_DDMACH1_DLEN_8821C) << BIT_SHIFT_DDMACH1_DLEN_8821C) +#define BITS_DDMACH1_DLEN_8821C \ + (BIT_MASK_DDMACH1_DLEN_8821C << BIT_SHIFT_DDMACH1_DLEN_8821C) +#define BIT_CLEAR_DDMACH1_DLEN_8821C(x) ((x) & (~BITS_DDMACH1_DLEN_8821C)) +#define BIT_GET_DDMACH1_DLEN_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DLEN_8821C) & BIT_MASK_DDMACH1_DLEN_8821C) +#define BIT_SET_DDMACH1_DLEN_8821C(x, v) \ + (BIT_CLEAR_DDMACH1_DLEN_8821C(x) | BIT_DDMACH1_DLEN_8821C(v)) /* 2 REG_DDMA_CH2SA_8821C */ #define BIT_SHIFT_DDMACH2_SA_8821C 0 #define BIT_MASK_DDMACH2_SA_8821C 0xffffffffL -#define BIT_DDMACH2_SA_8821C(x) (((x) & BIT_MASK_DDMACH2_SA_8821C) << BIT_SHIFT_DDMACH2_SA_8821C) -#define BIT_GET_DDMACH2_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8821C) & BIT_MASK_DDMACH2_SA_8821C) - - +#define BIT_DDMACH2_SA_8821C(x) \ + (((x) & BIT_MASK_DDMACH2_SA_8821C) << BIT_SHIFT_DDMACH2_SA_8821C) +#define BITS_DDMACH2_SA_8821C \ + (BIT_MASK_DDMACH2_SA_8821C << BIT_SHIFT_DDMACH2_SA_8821C) +#define BIT_CLEAR_DDMACH2_SA_8821C(x) ((x) & (~BITS_DDMACH2_SA_8821C)) +#define BIT_GET_DDMACH2_SA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH2_SA_8821C) & BIT_MASK_DDMACH2_SA_8821C) +#define BIT_SET_DDMACH2_SA_8821C(x, v) \ + (BIT_CLEAR_DDMACH2_SA_8821C(x) | BIT_DDMACH2_SA_8821C(v)) /* 2 REG_DDMA_CH2DA_8821C */ #define BIT_SHIFT_DDMACH2_DA_8821C 0 #define BIT_MASK_DDMACH2_DA_8821C 0xffffffffL -#define BIT_DDMACH2_DA_8821C(x) (((x) & BIT_MASK_DDMACH2_DA_8821C) << BIT_SHIFT_DDMACH2_DA_8821C) -#define BIT_GET_DDMACH2_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8821C) & BIT_MASK_DDMACH2_DA_8821C) - - +#define BIT_DDMACH2_DA_8821C(x) \ + (((x) & BIT_MASK_DDMACH2_DA_8821C) << BIT_SHIFT_DDMACH2_DA_8821C) +#define BITS_DDMACH2_DA_8821C \ + (BIT_MASK_DDMACH2_DA_8821C << BIT_SHIFT_DDMACH2_DA_8821C) +#define BIT_CLEAR_DDMACH2_DA_8821C(x) ((x) & (~BITS_DDMACH2_DA_8821C)) +#define BIT_GET_DDMACH2_DA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DA_8821C) & BIT_MASK_DDMACH2_DA_8821C) +#define BIT_SET_DDMACH2_DA_8821C(x, v) \ + (BIT_CLEAR_DDMACH2_DA_8821C(x) | BIT_DDMACH2_DA_8821C(v)) /* 2 REG_DDMA_CH2CTRL_8821C */ #define BIT_DDMACH2_OWN_8821C BIT(31) +#define BIT_DDMACH2_IDMEM_ERR_8821C BIT(30) #define BIT_DDMACH2_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH2_DA_W_DISABLE_8821C BIT(28) #define BIT_DDMACH2_CHKSUM_STS_8821C BIT(27) @@ -4142,31 +6762,47 @@ #define BIT_SHIFT_DDMACH2_DLEN_8821C 0 #define BIT_MASK_DDMACH2_DLEN_8821C 0x3ffff -#define BIT_DDMACH2_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH2_DLEN_8821C) << BIT_SHIFT_DDMACH2_DLEN_8821C) -#define BIT_GET_DDMACH2_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8821C) & BIT_MASK_DDMACH2_DLEN_8821C) - - +#define BIT_DDMACH2_DLEN_8821C(x) \ + (((x) & BIT_MASK_DDMACH2_DLEN_8821C) << BIT_SHIFT_DDMACH2_DLEN_8821C) +#define BITS_DDMACH2_DLEN_8821C \ + (BIT_MASK_DDMACH2_DLEN_8821C << BIT_SHIFT_DDMACH2_DLEN_8821C) +#define BIT_CLEAR_DDMACH2_DLEN_8821C(x) ((x) & (~BITS_DDMACH2_DLEN_8821C)) +#define BIT_GET_DDMACH2_DLEN_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DLEN_8821C) & BIT_MASK_DDMACH2_DLEN_8821C) +#define BIT_SET_DDMACH2_DLEN_8821C(x, v) \ + (BIT_CLEAR_DDMACH2_DLEN_8821C(x) | BIT_DDMACH2_DLEN_8821C(v)) /* 2 REG_DDMA_CH3SA_8821C */ #define BIT_SHIFT_DDMACH3_SA_8821C 0 #define BIT_MASK_DDMACH3_SA_8821C 0xffffffffL -#define BIT_DDMACH3_SA_8821C(x) (((x) & BIT_MASK_DDMACH3_SA_8821C) << BIT_SHIFT_DDMACH3_SA_8821C) -#define BIT_GET_DDMACH3_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8821C) & BIT_MASK_DDMACH3_SA_8821C) - - +#define BIT_DDMACH3_SA_8821C(x) \ + (((x) & BIT_MASK_DDMACH3_SA_8821C) << BIT_SHIFT_DDMACH3_SA_8821C) +#define BITS_DDMACH3_SA_8821C \ + (BIT_MASK_DDMACH3_SA_8821C << BIT_SHIFT_DDMACH3_SA_8821C) +#define BIT_CLEAR_DDMACH3_SA_8821C(x) ((x) & (~BITS_DDMACH3_SA_8821C)) +#define BIT_GET_DDMACH3_SA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH3_SA_8821C) & BIT_MASK_DDMACH3_SA_8821C) +#define BIT_SET_DDMACH3_SA_8821C(x, v) \ + (BIT_CLEAR_DDMACH3_SA_8821C(x) | BIT_DDMACH3_SA_8821C(v)) /* 2 REG_DDMA_CH3DA_8821C */ #define BIT_SHIFT_DDMACH3_DA_8821C 0 #define BIT_MASK_DDMACH3_DA_8821C 0xffffffffL -#define BIT_DDMACH3_DA_8821C(x) (((x) & BIT_MASK_DDMACH3_DA_8821C) << BIT_SHIFT_DDMACH3_DA_8821C) -#define BIT_GET_DDMACH3_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8821C) & BIT_MASK_DDMACH3_DA_8821C) - - +#define BIT_DDMACH3_DA_8821C(x) \ + (((x) & BIT_MASK_DDMACH3_DA_8821C) << BIT_SHIFT_DDMACH3_DA_8821C) +#define BITS_DDMACH3_DA_8821C \ + (BIT_MASK_DDMACH3_DA_8821C << BIT_SHIFT_DDMACH3_DA_8821C) +#define BIT_CLEAR_DDMACH3_DA_8821C(x) ((x) & (~BITS_DDMACH3_DA_8821C)) +#define BIT_GET_DDMACH3_DA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DA_8821C) & BIT_MASK_DDMACH3_DA_8821C) +#define BIT_SET_DDMACH3_DA_8821C(x, v) \ + (BIT_CLEAR_DDMACH3_DA_8821C(x) | BIT_DDMACH3_DA_8821C(v)) /* 2 REG_DDMA_CH3CTRL_8821C */ #define BIT_DDMACH3_OWN_8821C BIT(31) +#define BIT_DDMACH3_IDMEM_ERR_8821C BIT(30) #define BIT_DDMACH3_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH3_DA_W_DISABLE_8821C BIT(28) #define BIT_DDMACH3_CHKSUM_STS_8821C BIT(27) @@ -4176,31 +6812,47 @@ #define BIT_SHIFT_DDMACH3_DLEN_8821C 0 #define BIT_MASK_DDMACH3_DLEN_8821C 0x3ffff -#define BIT_DDMACH3_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH3_DLEN_8821C) << BIT_SHIFT_DDMACH3_DLEN_8821C) -#define BIT_GET_DDMACH3_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8821C) & BIT_MASK_DDMACH3_DLEN_8821C) - - +#define BIT_DDMACH3_DLEN_8821C(x) \ + (((x) & BIT_MASK_DDMACH3_DLEN_8821C) << BIT_SHIFT_DDMACH3_DLEN_8821C) +#define BITS_DDMACH3_DLEN_8821C \ + (BIT_MASK_DDMACH3_DLEN_8821C << BIT_SHIFT_DDMACH3_DLEN_8821C) +#define BIT_CLEAR_DDMACH3_DLEN_8821C(x) ((x) & (~BITS_DDMACH3_DLEN_8821C)) +#define BIT_GET_DDMACH3_DLEN_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DLEN_8821C) & BIT_MASK_DDMACH3_DLEN_8821C) +#define BIT_SET_DDMACH3_DLEN_8821C(x, v) \ + (BIT_CLEAR_DDMACH3_DLEN_8821C(x) | BIT_DDMACH3_DLEN_8821C(v)) /* 2 REG_DDMA_CH4SA_8821C */ #define BIT_SHIFT_DDMACH4_SA_8821C 0 #define BIT_MASK_DDMACH4_SA_8821C 0xffffffffL -#define BIT_DDMACH4_SA_8821C(x) (((x) & BIT_MASK_DDMACH4_SA_8821C) << BIT_SHIFT_DDMACH4_SA_8821C) -#define BIT_GET_DDMACH4_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8821C) & BIT_MASK_DDMACH4_SA_8821C) - - +#define BIT_DDMACH4_SA_8821C(x) \ + (((x) & BIT_MASK_DDMACH4_SA_8821C) << BIT_SHIFT_DDMACH4_SA_8821C) +#define BITS_DDMACH4_SA_8821C \ + (BIT_MASK_DDMACH4_SA_8821C << BIT_SHIFT_DDMACH4_SA_8821C) +#define BIT_CLEAR_DDMACH4_SA_8821C(x) ((x) & (~BITS_DDMACH4_SA_8821C)) +#define BIT_GET_DDMACH4_SA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH4_SA_8821C) & BIT_MASK_DDMACH4_SA_8821C) +#define BIT_SET_DDMACH4_SA_8821C(x, v) \ + (BIT_CLEAR_DDMACH4_SA_8821C(x) | BIT_DDMACH4_SA_8821C(v)) /* 2 REG_DDMA_CH4DA_8821C */ #define BIT_SHIFT_DDMACH4_DA_8821C 0 #define BIT_MASK_DDMACH4_DA_8821C 0xffffffffL -#define BIT_DDMACH4_DA_8821C(x) (((x) & BIT_MASK_DDMACH4_DA_8821C) << BIT_SHIFT_DDMACH4_DA_8821C) -#define BIT_GET_DDMACH4_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8821C) & BIT_MASK_DDMACH4_DA_8821C) - - +#define BIT_DDMACH4_DA_8821C(x) \ + (((x) & BIT_MASK_DDMACH4_DA_8821C) << BIT_SHIFT_DDMACH4_DA_8821C) +#define BITS_DDMACH4_DA_8821C \ + (BIT_MASK_DDMACH4_DA_8821C << BIT_SHIFT_DDMACH4_DA_8821C) +#define BIT_CLEAR_DDMACH4_DA_8821C(x) ((x) & (~BITS_DDMACH4_DA_8821C)) +#define BIT_GET_DDMACH4_DA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DA_8821C) & BIT_MASK_DDMACH4_DA_8821C) +#define BIT_SET_DDMACH4_DA_8821C(x, v) \ + (BIT_CLEAR_DDMACH4_DA_8821C(x) | BIT_DDMACH4_DA_8821C(v)) /* 2 REG_DDMA_CH4CTRL_8821C */ #define BIT_DDMACH4_OWN_8821C BIT(31) +#define BIT_DDMACH4_IDMEM_ERR_8821C BIT(30) #define BIT_DDMACH4_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH4_DA_W_DISABLE_8821C BIT(28) #define BIT_DDMACH4_CHKSUM_STS_8821C BIT(27) @@ -4210,31 +6862,47 @@ #define BIT_SHIFT_DDMACH4_DLEN_8821C 0 #define BIT_MASK_DDMACH4_DLEN_8821C 0x3ffff -#define BIT_DDMACH4_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH4_DLEN_8821C) << BIT_SHIFT_DDMACH4_DLEN_8821C) -#define BIT_GET_DDMACH4_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8821C) & BIT_MASK_DDMACH4_DLEN_8821C) - - +#define BIT_DDMACH4_DLEN_8821C(x) \ + (((x) & BIT_MASK_DDMACH4_DLEN_8821C) << BIT_SHIFT_DDMACH4_DLEN_8821C) +#define BITS_DDMACH4_DLEN_8821C \ + (BIT_MASK_DDMACH4_DLEN_8821C << BIT_SHIFT_DDMACH4_DLEN_8821C) +#define BIT_CLEAR_DDMACH4_DLEN_8821C(x) ((x) & (~BITS_DDMACH4_DLEN_8821C)) +#define BIT_GET_DDMACH4_DLEN_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DLEN_8821C) & BIT_MASK_DDMACH4_DLEN_8821C) +#define BIT_SET_DDMACH4_DLEN_8821C(x, v) \ + (BIT_CLEAR_DDMACH4_DLEN_8821C(x) | BIT_DDMACH4_DLEN_8821C(v)) /* 2 REG_DDMA_CH5SA_8821C */ #define BIT_SHIFT_DDMACH5_SA_8821C 0 #define BIT_MASK_DDMACH5_SA_8821C 0xffffffffL -#define BIT_DDMACH5_SA_8821C(x) (((x) & BIT_MASK_DDMACH5_SA_8821C) << BIT_SHIFT_DDMACH5_SA_8821C) -#define BIT_GET_DDMACH5_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8821C) & BIT_MASK_DDMACH5_SA_8821C) - - +#define BIT_DDMACH5_SA_8821C(x) \ + (((x) & BIT_MASK_DDMACH5_SA_8821C) << BIT_SHIFT_DDMACH5_SA_8821C) +#define BITS_DDMACH5_SA_8821C \ + (BIT_MASK_DDMACH5_SA_8821C << BIT_SHIFT_DDMACH5_SA_8821C) +#define BIT_CLEAR_DDMACH5_SA_8821C(x) ((x) & (~BITS_DDMACH5_SA_8821C)) +#define BIT_GET_DDMACH5_SA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH5_SA_8821C) & BIT_MASK_DDMACH5_SA_8821C) +#define BIT_SET_DDMACH5_SA_8821C(x, v) \ + (BIT_CLEAR_DDMACH5_SA_8821C(x) | BIT_DDMACH5_SA_8821C(v)) /* 2 REG_DDMA_CH5DA_8821C */ #define BIT_SHIFT_DDMACH5_DA_8821C 0 #define BIT_MASK_DDMACH5_DA_8821C 0xffffffffL -#define BIT_DDMACH5_DA_8821C(x) (((x) & BIT_MASK_DDMACH5_DA_8821C) << BIT_SHIFT_DDMACH5_DA_8821C) -#define BIT_GET_DDMACH5_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8821C) & BIT_MASK_DDMACH5_DA_8821C) - - +#define BIT_DDMACH5_DA_8821C(x) \ + (((x) & BIT_MASK_DDMACH5_DA_8821C) << BIT_SHIFT_DDMACH5_DA_8821C) +#define BITS_DDMACH5_DA_8821C \ + (BIT_MASK_DDMACH5_DA_8821C << BIT_SHIFT_DDMACH5_DA_8821C) +#define BIT_CLEAR_DDMACH5_DA_8821C(x) ((x) & (~BITS_DDMACH5_DA_8821C)) +#define BIT_GET_DDMACH5_DA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DA_8821C) & BIT_MASK_DDMACH5_DA_8821C) +#define BIT_SET_DDMACH5_DA_8821C(x, v) \ + (BIT_CLEAR_DDMACH5_DA_8821C(x) | BIT_DDMACH5_DA_8821C(v)) /* 2 REG_DDMA_CH5CTRL_8821C */ #define BIT_DDMACH5_OWN_8821C BIT(31) +#define BIT_DDMACH5_IDMEM_ERR_8821C BIT(30) #define BIT_DDMACH5_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH5_DA_W_DISABLE_8821C BIT(28) #define BIT_DDMACH5_CHKSUM_STS_8821C BIT(27) @@ -4244,10 +6912,15 @@ #define BIT_SHIFT_DDMACH5_DLEN_8821C 0 #define BIT_MASK_DDMACH5_DLEN_8821C 0x3ffff -#define BIT_DDMACH5_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH5_DLEN_8821C) << BIT_SHIFT_DDMACH5_DLEN_8821C) -#define BIT_GET_DDMACH5_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8821C) & BIT_MASK_DDMACH5_DLEN_8821C) - - +#define BIT_DDMACH5_DLEN_8821C(x) \ + (((x) & BIT_MASK_DDMACH5_DLEN_8821C) << BIT_SHIFT_DDMACH5_DLEN_8821C) +#define BITS_DDMACH5_DLEN_8821C \ + (BIT_MASK_DDMACH5_DLEN_8821C << BIT_SHIFT_DDMACH5_DLEN_8821C) +#define BIT_CLEAR_DDMACH5_DLEN_8821C(x) ((x) & (~BITS_DDMACH5_DLEN_8821C)) +#define BIT_GET_DDMACH5_DLEN_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DLEN_8821C) & BIT_MASK_DDMACH5_DLEN_8821C) +#define BIT_SET_DDMACH5_DLEN_8821C(x, v) \ + (BIT_CLEAR_DDMACH5_DLEN_8821C(x) | BIT_DDMACH5_DLEN_8821C(v)) /* 2 REG_DDMA_INT_MSK_8821C */ #define BIT_DDMACH5_MSK_8821C BIT(5) @@ -4269,10 +6942,15 @@ #define BIT_SHIFT_IDDMA0_CHKSUM_8821C 0 #define BIT_MASK_IDDMA0_CHKSUM_8821C 0xffff -#define BIT_IDDMA0_CHKSUM_8821C(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8821C) << BIT_SHIFT_IDDMA0_CHKSUM_8821C) -#define BIT_GET_IDDMA0_CHKSUM_8821C(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8821C) & BIT_MASK_IDDMA0_CHKSUM_8821C) - - +#define BIT_IDDMA0_CHKSUM_8821C(x) \ + (((x) & BIT_MASK_IDDMA0_CHKSUM_8821C) << BIT_SHIFT_IDDMA0_CHKSUM_8821C) +#define BITS_IDDMA0_CHKSUM_8821C \ + (BIT_MASK_IDDMA0_CHKSUM_8821C << BIT_SHIFT_IDDMA0_CHKSUM_8821C) +#define BIT_CLEAR_IDDMA0_CHKSUM_8821C(x) ((x) & (~BITS_IDDMA0_CHKSUM_8821C)) +#define BIT_GET_IDDMA0_CHKSUM_8821C(x) \ + (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8821C) & BIT_MASK_IDDMA0_CHKSUM_8821C) +#define BIT_SET_IDDMA0_CHKSUM_8821C(x, v) \ + (BIT_CLEAR_IDDMA0_CHKSUM_8821C(x) | BIT_IDDMA0_CHKSUM_8821C(v)) /* 2 REG_DDMA_MONITOR_8821C */ #define BIT_IDDMA0_PERMU_UNDERFLOW_8821C BIT(14) @@ -4292,17 +6970,33 @@ #define BIT_SHIFT_PCIE_MAX_RXDMA_8821C 28 #define BIT_MASK_PCIE_MAX_RXDMA_8821C 0x7 -#define BIT_PCIE_MAX_RXDMA_8821C(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA_8821C) << BIT_SHIFT_PCIE_MAX_RXDMA_8821C) -#define BIT_GET_PCIE_MAX_RXDMA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8821C) & BIT_MASK_PCIE_MAX_RXDMA_8821C) - +#define BIT_PCIE_MAX_RXDMA_8821C(x) \ + (((x) & BIT_MASK_PCIE_MAX_RXDMA_8821C) \ + << BIT_SHIFT_PCIE_MAX_RXDMA_8821C) +#define BITS_PCIE_MAX_RXDMA_8821C \ + (BIT_MASK_PCIE_MAX_RXDMA_8821C << BIT_SHIFT_PCIE_MAX_RXDMA_8821C) +#define BIT_CLEAR_PCIE_MAX_RXDMA_8821C(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8821C)) +#define BIT_GET_PCIE_MAX_RXDMA_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8821C) & \ + BIT_MASK_PCIE_MAX_RXDMA_8821C) +#define BIT_SET_PCIE_MAX_RXDMA_8821C(x, v) \ + (BIT_CLEAR_PCIE_MAX_RXDMA_8821C(x) | BIT_PCIE_MAX_RXDMA_8821C(v)) #define BIT_MULRW_8821C BIT(27) #define BIT_SHIFT_PCIE_MAX_TXDMA_8821C 24 #define BIT_MASK_PCIE_MAX_TXDMA_8821C 0x7 -#define BIT_PCIE_MAX_TXDMA_8821C(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA_8821C) << BIT_SHIFT_PCIE_MAX_TXDMA_8821C) -#define BIT_GET_PCIE_MAX_TXDMA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8821C) & BIT_MASK_PCIE_MAX_TXDMA_8821C) - +#define BIT_PCIE_MAX_TXDMA_8821C(x) \ + (((x) & BIT_MASK_PCIE_MAX_TXDMA_8821C) \ + << BIT_SHIFT_PCIE_MAX_TXDMA_8821C) +#define BITS_PCIE_MAX_TXDMA_8821C \ + (BIT_MASK_PCIE_MAX_TXDMA_8821C << BIT_SHIFT_PCIE_MAX_TXDMA_8821C) +#define BIT_CLEAR_PCIE_MAX_TXDMA_8821C(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8821C)) +#define BIT_GET_PCIE_MAX_TXDMA_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8821C) & \ + BIT_MASK_PCIE_MAX_TXDMA_8821C) +#define BIT_SET_PCIE_MAX_TXDMA_8821C(x, v) \ + (BIT_CLEAR_PCIE_MAX_TXDMA_8821C(x) | BIT_PCIE_MAX_TXDMA_8821C(v)) #define BIT_EN_CPL_TIMEOUT_PS_8821C BIT(22) #define BIT_REG_TXDMA_FAIL_PS_8821C BIT(21) @@ -4332,428 +7026,729 @@ #define BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C 28 #define BIT_MASK_TXTTIMER_MATCH_NUM_8821C 0xf -#define BIT_TXTTIMER_MATCH_NUM_8821C(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) -#define BIT_GET_TXTTIMER_MATCH_NUM_8821C(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C) - - +#define BIT_TXTTIMER_MATCH_NUM_8821C(x) \ + (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C) \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) +#define BITS_TXTTIMER_MATCH_NUM_8821C \ + (BIT_MASK_TXTTIMER_MATCH_NUM_8821C \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) +#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8821C(x) \ + ((x) & (~BITS_TXTTIMER_MATCH_NUM_8821C)) +#define BIT_GET_TXTTIMER_MATCH_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) & \ + BIT_MASK_TXTTIMER_MATCH_NUM_8821C) +#define BIT_SET_TXTTIMER_MATCH_NUM_8821C(x, v) \ + (BIT_CLEAR_TXTTIMER_MATCH_NUM_8821C(x) | \ + BIT_TXTTIMER_MATCH_NUM_8821C(v)) #define BIT_SHIFT_TXPKT_NUM_MATCH_8821C 24 #define BIT_MASK_TXPKT_NUM_MATCH_8821C 0xf -#define BIT_TXPKT_NUM_MATCH_8821C(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8821C) << BIT_SHIFT_TXPKT_NUM_MATCH_8821C) -#define BIT_GET_TXPKT_NUM_MATCH_8821C(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8821C) & BIT_MASK_TXPKT_NUM_MATCH_8821C) - - +#define BIT_TXPKT_NUM_MATCH_8821C(x) \ + (((x) & BIT_MASK_TXPKT_NUM_MATCH_8821C) \ + << BIT_SHIFT_TXPKT_NUM_MATCH_8821C) +#define BITS_TXPKT_NUM_MATCH_8821C \ + (BIT_MASK_TXPKT_NUM_MATCH_8821C << BIT_SHIFT_TXPKT_NUM_MATCH_8821C) +#define BIT_CLEAR_TXPKT_NUM_MATCH_8821C(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8821C)) +#define BIT_GET_TXPKT_NUM_MATCH_8821C(x) \ + (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8821C) & \ + BIT_MASK_TXPKT_NUM_MATCH_8821C) +#define BIT_SET_TXPKT_NUM_MATCH_8821C(x, v) \ + (BIT_CLEAR_TXPKT_NUM_MATCH_8821C(x) | BIT_TXPKT_NUM_MATCH_8821C(v)) #define BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C 20 #define BIT_MASK_RXTTIMER_MATCH_NUM_8821C 0xf -#define BIT_RXTTIMER_MATCH_NUM_8821C(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) -#define BIT_GET_RXTTIMER_MATCH_NUM_8821C(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C) - - +#define BIT_RXTTIMER_MATCH_NUM_8821C(x) \ + (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C) \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) +#define BITS_RXTTIMER_MATCH_NUM_8821C \ + (BIT_MASK_RXTTIMER_MATCH_NUM_8821C \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) +#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8821C(x) \ + ((x) & (~BITS_RXTTIMER_MATCH_NUM_8821C)) +#define BIT_GET_RXTTIMER_MATCH_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) & \ + BIT_MASK_RXTTIMER_MATCH_NUM_8821C) +#define BIT_SET_RXTTIMER_MATCH_NUM_8821C(x, v) \ + (BIT_CLEAR_RXTTIMER_MATCH_NUM_8821C(x) | \ + BIT_RXTTIMER_MATCH_NUM_8821C(v)) #define BIT_SHIFT_RXPKT_NUM_MATCH_8821C 16 #define BIT_MASK_RXPKT_NUM_MATCH_8821C 0xf -#define BIT_RXPKT_NUM_MATCH_8821C(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8821C) << BIT_SHIFT_RXPKT_NUM_MATCH_8821C) -#define BIT_GET_RXPKT_NUM_MATCH_8821C(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8821C) & BIT_MASK_RXPKT_NUM_MATCH_8821C) - - +#define BIT_RXPKT_NUM_MATCH_8821C(x) \ + (((x) & BIT_MASK_RXPKT_NUM_MATCH_8821C) \ + << BIT_SHIFT_RXPKT_NUM_MATCH_8821C) +#define BITS_RXPKT_NUM_MATCH_8821C \ + (BIT_MASK_RXPKT_NUM_MATCH_8821C << BIT_SHIFT_RXPKT_NUM_MATCH_8821C) +#define BIT_CLEAR_RXPKT_NUM_MATCH_8821C(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8821C)) +#define BIT_GET_RXPKT_NUM_MATCH_8821C(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8821C) & \ + BIT_MASK_RXPKT_NUM_MATCH_8821C) +#define BIT_SET_RXPKT_NUM_MATCH_8821C(x, v) \ + (BIT_CLEAR_RXPKT_NUM_MATCH_8821C(x) | BIT_RXPKT_NUM_MATCH_8821C(v)) #define BIT_SHIFT_MIGRATE_TIMER_8821C 0 #define BIT_MASK_MIGRATE_TIMER_8821C 0xffff -#define BIT_MIGRATE_TIMER_8821C(x) (((x) & BIT_MASK_MIGRATE_TIMER_8821C) << BIT_SHIFT_MIGRATE_TIMER_8821C) -#define BIT_GET_MIGRATE_TIMER_8821C(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8821C) & BIT_MASK_MIGRATE_TIMER_8821C) - - +#define BIT_MIGRATE_TIMER_8821C(x) \ + (((x) & BIT_MASK_MIGRATE_TIMER_8821C) << BIT_SHIFT_MIGRATE_TIMER_8821C) +#define BITS_MIGRATE_TIMER_8821C \ + (BIT_MASK_MIGRATE_TIMER_8821C << BIT_SHIFT_MIGRATE_TIMER_8821C) +#define BIT_CLEAR_MIGRATE_TIMER_8821C(x) ((x) & (~BITS_MIGRATE_TIMER_8821C)) +#define BIT_GET_MIGRATE_TIMER_8821C(x) \ + (((x) >> BIT_SHIFT_MIGRATE_TIMER_8821C) & BIT_MASK_MIGRATE_TIMER_8821C) +#define BIT_SET_MIGRATE_TIMER_8821C(x, v) \ + (BIT_CLEAR_MIGRATE_TIMER_8821C(x) | BIT_MIGRATE_TIMER_8821C(v)) /* 2 REG_BCNQ_TXBD_DESA_8821C */ #define BIT_SHIFT_BCNQ_TXBD_DESA_8821C 0 #define BIT_MASK_BCNQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_BCNQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8821C) << BIT_SHIFT_BCNQ_TXBD_DESA_8821C) -#define BIT_GET_BCNQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8821C) & BIT_MASK_BCNQ_TXBD_DESA_8821C) - - +#define BIT_BCNQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_BCNQ_TXBD_DESA_8821C) \ + << BIT_SHIFT_BCNQ_TXBD_DESA_8821C) +#define BITS_BCNQ_TXBD_DESA_8821C \ + (BIT_MASK_BCNQ_TXBD_DESA_8821C << BIT_SHIFT_BCNQ_TXBD_DESA_8821C) +#define BIT_CLEAR_BCNQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8821C)) +#define BIT_GET_BCNQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8821C) & \ + BIT_MASK_BCNQ_TXBD_DESA_8821C) +#define BIT_SET_BCNQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_BCNQ_TXBD_DESA_8821C(x) | BIT_BCNQ_TXBD_DESA_8821C(v)) /* 2 REG_MGQ_TXBD_DESA_8821C */ #define BIT_SHIFT_MGQ_TXBD_DESA_8821C 0 #define BIT_MASK_MGQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_MGQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8821C) << BIT_SHIFT_MGQ_TXBD_DESA_8821C) -#define BIT_GET_MGQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8821C) & BIT_MASK_MGQ_TXBD_DESA_8821C) - - +#define BIT_MGQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_MGQ_TXBD_DESA_8821C) << BIT_SHIFT_MGQ_TXBD_DESA_8821C) +#define BITS_MGQ_TXBD_DESA_8821C \ + (BIT_MASK_MGQ_TXBD_DESA_8821C << BIT_SHIFT_MGQ_TXBD_DESA_8821C) +#define BIT_CLEAR_MGQ_TXBD_DESA_8821C(x) ((x) & (~BITS_MGQ_TXBD_DESA_8821C)) +#define BIT_GET_MGQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8821C) & BIT_MASK_MGQ_TXBD_DESA_8821C) +#define BIT_SET_MGQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_MGQ_TXBD_DESA_8821C(x) | BIT_MGQ_TXBD_DESA_8821C(v)) /* 2 REG_VOQ_TXBD_DESA_8821C */ #define BIT_SHIFT_VOQ_TXBD_DESA_8821C 0 #define BIT_MASK_VOQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_VOQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8821C) << BIT_SHIFT_VOQ_TXBD_DESA_8821C) -#define BIT_GET_VOQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8821C) & BIT_MASK_VOQ_TXBD_DESA_8821C) - - +#define BIT_VOQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_VOQ_TXBD_DESA_8821C) << BIT_SHIFT_VOQ_TXBD_DESA_8821C) +#define BITS_VOQ_TXBD_DESA_8821C \ + (BIT_MASK_VOQ_TXBD_DESA_8821C << BIT_SHIFT_VOQ_TXBD_DESA_8821C) +#define BIT_CLEAR_VOQ_TXBD_DESA_8821C(x) ((x) & (~BITS_VOQ_TXBD_DESA_8821C)) +#define BIT_GET_VOQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8821C) & BIT_MASK_VOQ_TXBD_DESA_8821C) +#define BIT_SET_VOQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_VOQ_TXBD_DESA_8821C(x) | BIT_VOQ_TXBD_DESA_8821C(v)) /* 2 REG_VIQ_TXBD_DESA_8821C */ #define BIT_SHIFT_VIQ_TXBD_DESA_8821C 0 #define BIT_MASK_VIQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_VIQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8821C) << BIT_SHIFT_VIQ_TXBD_DESA_8821C) -#define BIT_GET_VIQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8821C) & BIT_MASK_VIQ_TXBD_DESA_8821C) - - +#define BIT_VIQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_VIQ_TXBD_DESA_8821C) << BIT_SHIFT_VIQ_TXBD_DESA_8821C) +#define BITS_VIQ_TXBD_DESA_8821C \ + (BIT_MASK_VIQ_TXBD_DESA_8821C << BIT_SHIFT_VIQ_TXBD_DESA_8821C) +#define BIT_CLEAR_VIQ_TXBD_DESA_8821C(x) ((x) & (~BITS_VIQ_TXBD_DESA_8821C)) +#define BIT_GET_VIQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8821C) & BIT_MASK_VIQ_TXBD_DESA_8821C) +#define BIT_SET_VIQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_VIQ_TXBD_DESA_8821C(x) | BIT_VIQ_TXBD_DESA_8821C(v)) /* 2 REG_BEQ_TXBD_DESA_8821C */ #define BIT_SHIFT_BEQ_TXBD_DESA_8821C 0 #define BIT_MASK_BEQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_BEQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8821C) << BIT_SHIFT_BEQ_TXBD_DESA_8821C) -#define BIT_GET_BEQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8821C) & BIT_MASK_BEQ_TXBD_DESA_8821C) - - +#define BIT_BEQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_BEQ_TXBD_DESA_8821C) << BIT_SHIFT_BEQ_TXBD_DESA_8821C) +#define BITS_BEQ_TXBD_DESA_8821C \ + (BIT_MASK_BEQ_TXBD_DESA_8821C << BIT_SHIFT_BEQ_TXBD_DESA_8821C) +#define BIT_CLEAR_BEQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BEQ_TXBD_DESA_8821C)) +#define BIT_GET_BEQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8821C) & BIT_MASK_BEQ_TXBD_DESA_8821C) +#define BIT_SET_BEQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_BEQ_TXBD_DESA_8821C(x) | BIT_BEQ_TXBD_DESA_8821C(v)) /* 2 REG_BKQ_TXBD_DESA_8821C */ #define BIT_SHIFT_BKQ_TXBD_DESA_8821C 0 #define BIT_MASK_BKQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_BKQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8821C) << BIT_SHIFT_BKQ_TXBD_DESA_8821C) -#define BIT_GET_BKQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8821C) & BIT_MASK_BKQ_TXBD_DESA_8821C) - - +#define BIT_BKQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_BKQ_TXBD_DESA_8821C) << BIT_SHIFT_BKQ_TXBD_DESA_8821C) +#define BITS_BKQ_TXBD_DESA_8821C \ + (BIT_MASK_BKQ_TXBD_DESA_8821C << BIT_SHIFT_BKQ_TXBD_DESA_8821C) +#define BIT_CLEAR_BKQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BKQ_TXBD_DESA_8821C)) +#define BIT_GET_BKQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8821C) & BIT_MASK_BKQ_TXBD_DESA_8821C) +#define BIT_SET_BKQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_BKQ_TXBD_DESA_8821C(x) | BIT_BKQ_TXBD_DESA_8821C(v)) /* 2 REG_RXQ_RXBD_DESA_8821C */ #define BIT_SHIFT_RXQ_RXBD_DESA_8821C 0 #define BIT_MASK_RXQ_RXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_RXQ_RXBD_DESA_8821C(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8821C) << BIT_SHIFT_RXQ_RXBD_DESA_8821C) -#define BIT_GET_RXQ_RXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8821C) & BIT_MASK_RXQ_RXBD_DESA_8821C) - - +#define BIT_RXQ_RXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_RXQ_RXBD_DESA_8821C) << BIT_SHIFT_RXQ_RXBD_DESA_8821C) +#define BITS_RXQ_RXBD_DESA_8821C \ + (BIT_MASK_RXQ_RXBD_DESA_8821C << BIT_SHIFT_RXQ_RXBD_DESA_8821C) +#define BIT_CLEAR_RXQ_RXBD_DESA_8821C(x) ((x) & (~BITS_RXQ_RXBD_DESA_8821C)) +#define BIT_GET_RXQ_RXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8821C) & BIT_MASK_RXQ_RXBD_DESA_8821C) +#define BIT_SET_RXQ_RXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_RXQ_RXBD_DESA_8821C(x) | BIT_RXQ_RXBD_DESA_8821C(v)) /* 2 REG_HI0Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI0Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI0Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI0Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8821C) << BIT_SHIFT_HI0Q_TXBD_DESA_8821C) -#define BIT_GET_HI0Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8821C) & BIT_MASK_HI0Q_TXBD_DESA_8821C) - - +#define BIT_HI0Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI0Q_TXBD_DESA_8821C) +#define BITS_HI0Q_TXBD_DESA_8821C \ + (BIT_MASK_HI0Q_TXBD_DESA_8821C << BIT_SHIFT_HI0Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI0Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8821C)) +#define BIT_GET_HI0Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI0Q_TXBD_DESA_8821C) +#define BIT_SET_HI0Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_8821C(x) | BIT_HI0Q_TXBD_DESA_8821C(v)) /* 2 REG_HI1Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI1Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI1Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI1Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8821C) << BIT_SHIFT_HI1Q_TXBD_DESA_8821C) -#define BIT_GET_HI1Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8821C) & BIT_MASK_HI1Q_TXBD_DESA_8821C) - - +#define BIT_HI1Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI1Q_TXBD_DESA_8821C) +#define BITS_HI1Q_TXBD_DESA_8821C \ + (BIT_MASK_HI1Q_TXBD_DESA_8821C << BIT_SHIFT_HI1Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI1Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8821C)) +#define BIT_GET_HI1Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI1Q_TXBD_DESA_8821C) +#define BIT_SET_HI1Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_8821C(x) | BIT_HI1Q_TXBD_DESA_8821C(v)) /* 2 REG_HI2Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI2Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI2Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI2Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8821C) << BIT_SHIFT_HI2Q_TXBD_DESA_8821C) -#define BIT_GET_HI2Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8821C) & BIT_MASK_HI2Q_TXBD_DESA_8821C) - - +#define BIT_HI2Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI2Q_TXBD_DESA_8821C) +#define BITS_HI2Q_TXBD_DESA_8821C \ + (BIT_MASK_HI2Q_TXBD_DESA_8821C << BIT_SHIFT_HI2Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI2Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8821C)) +#define BIT_GET_HI2Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI2Q_TXBD_DESA_8821C) +#define BIT_SET_HI2Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_8821C(x) | BIT_HI2Q_TXBD_DESA_8821C(v)) /* 2 REG_HI3Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI3Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI3Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI3Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8821C) << BIT_SHIFT_HI3Q_TXBD_DESA_8821C) -#define BIT_GET_HI3Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8821C) & BIT_MASK_HI3Q_TXBD_DESA_8821C) - - +#define BIT_HI3Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI3Q_TXBD_DESA_8821C) +#define BITS_HI3Q_TXBD_DESA_8821C \ + (BIT_MASK_HI3Q_TXBD_DESA_8821C << BIT_SHIFT_HI3Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI3Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8821C)) +#define BIT_GET_HI3Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI3Q_TXBD_DESA_8821C) +#define BIT_SET_HI3Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_8821C(x) | BIT_HI3Q_TXBD_DESA_8821C(v)) /* 2 REG_HI4Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI4Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI4Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI4Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8821C) << BIT_SHIFT_HI4Q_TXBD_DESA_8821C) -#define BIT_GET_HI4Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8821C) & BIT_MASK_HI4Q_TXBD_DESA_8821C) - - +#define BIT_HI4Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI4Q_TXBD_DESA_8821C) +#define BITS_HI4Q_TXBD_DESA_8821C \ + (BIT_MASK_HI4Q_TXBD_DESA_8821C << BIT_SHIFT_HI4Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI4Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8821C)) +#define BIT_GET_HI4Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI4Q_TXBD_DESA_8821C) +#define BIT_SET_HI4Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_8821C(x) | BIT_HI4Q_TXBD_DESA_8821C(v)) /* 2 REG_HI5Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI5Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI5Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI5Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8821C) << BIT_SHIFT_HI5Q_TXBD_DESA_8821C) -#define BIT_GET_HI5Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8821C) & BIT_MASK_HI5Q_TXBD_DESA_8821C) - - +#define BIT_HI5Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI5Q_TXBD_DESA_8821C) +#define BITS_HI5Q_TXBD_DESA_8821C \ + (BIT_MASK_HI5Q_TXBD_DESA_8821C << BIT_SHIFT_HI5Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI5Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8821C)) +#define BIT_GET_HI5Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI5Q_TXBD_DESA_8821C) +#define BIT_SET_HI5Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_8821C(x) | BIT_HI5Q_TXBD_DESA_8821C(v)) /* 2 REG_HI6Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI6Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI6Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI6Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8821C) << BIT_SHIFT_HI6Q_TXBD_DESA_8821C) -#define BIT_GET_HI6Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8821C) & BIT_MASK_HI6Q_TXBD_DESA_8821C) - - +#define BIT_HI6Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI6Q_TXBD_DESA_8821C) +#define BITS_HI6Q_TXBD_DESA_8821C \ + (BIT_MASK_HI6Q_TXBD_DESA_8821C << BIT_SHIFT_HI6Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI6Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8821C)) +#define BIT_GET_HI6Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI6Q_TXBD_DESA_8821C) +#define BIT_SET_HI6Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_8821C(x) | BIT_HI6Q_TXBD_DESA_8821C(v)) /* 2 REG_HI7Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI7Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI7Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI7Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8821C) << BIT_SHIFT_HI7Q_TXBD_DESA_8821C) -#define BIT_GET_HI7Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8821C) & BIT_MASK_HI7Q_TXBD_DESA_8821C) - - +#define BIT_HI7Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI7Q_TXBD_DESA_8821C) +#define BITS_HI7Q_TXBD_DESA_8821C \ + (BIT_MASK_HI7Q_TXBD_DESA_8821C << BIT_SHIFT_HI7Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI7Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8821C)) +#define BIT_GET_HI7Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI7Q_TXBD_DESA_8821C) +#define BIT_SET_HI7Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_8821C(x) | BIT_HI7Q_TXBD_DESA_8821C(v)) /* 2 REG_MGQ_TXBD_NUM_8821C */ #define BIT_PCIE_MGQ_FLAG_8821C BIT(14) #define BIT_SHIFT_MGQ_DESC_MODE_8821C 12 #define BIT_MASK_MGQ_DESC_MODE_8821C 0x3 -#define BIT_MGQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8821C) << BIT_SHIFT_MGQ_DESC_MODE_8821C) -#define BIT_GET_MGQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8821C) & BIT_MASK_MGQ_DESC_MODE_8821C) - - +#define BIT_MGQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_MGQ_DESC_MODE_8821C) << BIT_SHIFT_MGQ_DESC_MODE_8821C) +#define BITS_MGQ_DESC_MODE_8821C \ + (BIT_MASK_MGQ_DESC_MODE_8821C << BIT_SHIFT_MGQ_DESC_MODE_8821C) +#define BIT_CLEAR_MGQ_DESC_MODE_8821C(x) ((x) & (~BITS_MGQ_DESC_MODE_8821C)) +#define BIT_GET_MGQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8821C) & BIT_MASK_MGQ_DESC_MODE_8821C) +#define BIT_SET_MGQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_MGQ_DESC_MODE_8821C(x) | BIT_MGQ_DESC_MODE_8821C(v)) #define BIT_SHIFT_MGQ_DESC_NUM_8821C 0 #define BIT_MASK_MGQ_DESC_NUM_8821C 0xfff -#define BIT_MGQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8821C) << BIT_SHIFT_MGQ_DESC_NUM_8821C) -#define BIT_GET_MGQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8821C) & BIT_MASK_MGQ_DESC_NUM_8821C) - - +#define BIT_MGQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_MGQ_DESC_NUM_8821C) << BIT_SHIFT_MGQ_DESC_NUM_8821C) +#define BITS_MGQ_DESC_NUM_8821C \ + (BIT_MASK_MGQ_DESC_NUM_8821C << BIT_SHIFT_MGQ_DESC_NUM_8821C) +#define BIT_CLEAR_MGQ_DESC_NUM_8821C(x) ((x) & (~BITS_MGQ_DESC_NUM_8821C)) +#define BIT_GET_MGQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8821C) & BIT_MASK_MGQ_DESC_NUM_8821C) +#define BIT_SET_MGQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_MGQ_DESC_NUM_8821C(x) | BIT_MGQ_DESC_NUM_8821C(v)) /* 2 REG_RX_RXBD_NUM_8821C */ #define BIT_SYS_32_64_8821C BIT(15) #define BIT_SHIFT_BCNQ_DESC_MODE_8821C 13 #define BIT_MASK_BCNQ_DESC_MODE_8821C 0x3 -#define BIT_BCNQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8821C) << BIT_SHIFT_BCNQ_DESC_MODE_8821C) -#define BIT_GET_BCNQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8821C) & BIT_MASK_BCNQ_DESC_MODE_8821C) - +#define BIT_BCNQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_BCNQ_DESC_MODE_8821C) \ + << BIT_SHIFT_BCNQ_DESC_MODE_8821C) +#define BITS_BCNQ_DESC_MODE_8821C \ + (BIT_MASK_BCNQ_DESC_MODE_8821C << BIT_SHIFT_BCNQ_DESC_MODE_8821C) +#define BIT_CLEAR_BCNQ_DESC_MODE_8821C(x) ((x) & (~BITS_BCNQ_DESC_MODE_8821C)) +#define BIT_GET_BCNQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8821C) & \ + BIT_MASK_BCNQ_DESC_MODE_8821C) +#define BIT_SET_BCNQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_BCNQ_DESC_MODE_8821C(x) | BIT_BCNQ_DESC_MODE_8821C(v)) #define BIT_PCIE_BCNQ_FLAG_8821C BIT(12) #define BIT_SHIFT_RXQ_DESC_NUM_8821C 0 #define BIT_MASK_RXQ_DESC_NUM_8821C 0xfff -#define BIT_RXQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8821C) << BIT_SHIFT_RXQ_DESC_NUM_8821C) -#define BIT_GET_RXQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8821C) & BIT_MASK_RXQ_DESC_NUM_8821C) - - +#define BIT_RXQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_RXQ_DESC_NUM_8821C) << BIT_SHIFT_RXQ_DESC_NUM_8821C) +#define BITS_RXQ_DESC_NUM_8821C \ + (BIT_MASK_RXQ_DESC_NUM_8821C << BIT_SHIFT_RXQ_DESC_NUM_8821C) +#define BIT_CLEAR_RXQ_DESC_NUM_8821C(x) ((x) & (~BITS_RXQ_DESC_NUM_8821C)) +#define BIT_GET_RXQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8821C) & BIT_MASK_RXQ_DESC_NUM_8821C) +#define BIT_SET_RXQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_RXQ_DESC_NUM_8821C(x) | BIT_RXQ_DESC_NUM_8821C(v)) /* 2 REG_VOQ_TXBD_NUM_8821C */ #define BIT_PCIE_VOQ_FLAG_8821C BIT(14) #define BIT_SHIFT_VOQ_DESC_MODE_8821C 12 #define BIT_MASK_VOQ_DESC_MODE_8821C 0x3 -#define BIT_VOQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8821C) << BIT_SHIFT_VOQ_DESC_MODE_8821C) -#define BIT_GET_VOQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8821C) & BIT_MASK_VOQ_DESC_MODE_8821C) - - +#define BIT_VOQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_VOQ_DESC_MODE_8821C) << BIT_SHIFT_VOQ_DESC_MODE_8821C) +#define BITS_VOQ_DESC_MODE_8821C \ + (BIT_MASK_VOQ_DESC_MODE_8821C << BIT_SHIFT_VOQ_DESC_MODE_8821C) +#define BIT_CLEAR_VOQ_DESC_MODE_8821C(x) ((x) & (~BITS_VOQ_DESC_MODE_8821C)) +#define BIT_GET_VOQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8821C) & BIT_MASK_VOQ_DESC_MODE_8821C) +#define BIT_SET_VOQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_VOQ_DESC_MODE_8821C(x) | BIT_VOQ_DESC_MODE_8821C(v)) #define BIT_SHIFT_VOQ_DESC_NUM_8821C 0 #define BIT_MASK_VOQ_DESC_NUM_8821C 0xfff -#define BIT_VOQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8821C) << BIT_SHIFT_VOQ_DESC_NUM_8821C) -#define BIT_GET_VOQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8821C) & BIT_MASK_VOQ_DESC_NUM_8821C) - - +#define BIT_VOQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_VOQ_DESC_NUM_8821C) << BIT_SHIFT_VOQ_DESC_NUM_8821C) +#define BITS_VOQ_DESC_NUM_8821C \ + (BIT_MASK_VOQ_DESC_NUM_8821C << BIT_SHIFT_VOQ_DESC_NUM_8821C) +#define BIT_CLEAR_VOQ_DESC_NUM_8821C(x) ((x) & (~BITS_VOQ_DESC_NUM_8821C)) +#define BIT_GET_VOQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8821C) & BIT_MASK_VOQ_DESC_NUM_8821C) +#define BIT_SET_VOQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_VOQ_DESC_NUM_8821C(x) | BIT_VOQ_DESC_NUM_8821C(v)) /* 2 REG_VIQ_TXBD_NUM_8821C */ #define BIT_PCIE_VIQ_FLAG_8821C BIT(14) #define BIT_SHIFT_VIQ_DESC_MODE_8821C 12 #define BIT_MASK_VIQ_DESC_MODE_8821C 0x3 -#define BIT_VIQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8821C) << BIT_SHIFT_VIQ_DESC_MODE_8821C) -#define BIT_GET_VIQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8821C) & BIT_MASK_VIQ_DESC_MODE_8821C) - - +#define BIT_VIQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_VIQ_DESC_MODE_8821C) << BIT_SHIFT_VIQ_DESC_MODE_8821C) +#define BITS_VIQ_DESC_MODE_8821C \ + (BIT_MASK_VIQ_DESC_MODE_8821C << BIT_SHIFT_VIQ_DESC_MODE_8821C) +#define BIT_CLEAR_VIQ_DESC_MODE_8821C(x) ((x) & (~BITS_VIQ_DESC_MODE_8821C)) +#define BIT_GET_VIQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8821C) & BIT_MASK_VIQ_DESC_MODE_8821C) +#define BIT_SET_VIQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_VIQ_DESC_MODE_8821C(x) | BIT_VIQ_DESC_MODE_8821C(v)) #define BIT_SHIFT_VIQ_DESC_NUM_8821C 0 #define BIT_MASK_VIQ_DESC_NUM_8821C 0xfff -#define BIT_VIQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8821C) << BIT_SHIFT_VIQ_DESC_NUM_8821C) -#define BIT_GET_VIQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8821C) & BIT_MASK_VIQ_DESC_NUM_8821C) - - +#define BIT_VIQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_VIQ_DESC_NUM_8821C) << BIT_SHIFT_VIQ_DESC_NUM_8821C) +#define BITS_VIQ_DESC_NUM_8821C \ + (BIT_MASK_VIQ_DESC_NUM_8821C << BIT_SHIFT_VIQ_DESC_NUM_8821C) +#define BIT_CLEAR_VIQ_DESC_NUM_8821C(x) ((x) & (~BITS_VIQ_DESC_NUM_8821C)) +#define BIT_GET_VIQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8821C) & BIT_MASK_VIQ_DESC_NUM_8821C) +#define BIT_SET_VIQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_VIQ_DESC_NUM_8821C(x) | BIT_VIQ_DESC_NUM_8821C(v)) /* 2 REG_BEQ_TXBD_NUM_8821C */ #define BIT_PCIE_BEQ_FLAG_8821C BIT(14) #define BIT_SHIFT_BEQ_DESC_MODE_8821C 12 #define BIT_MASK_BEQ_DESC_MODE_8821C 0x3 -#define BIT_BEQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8821C) << BIT_SHIFT_BEQ_DESC_MODE_8821C) -#define BIT_GET_BEQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8821C) & BIT_MASK_BEQ_DESC_MODE_8821C) - - +#define BIT_BEQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_BEQ_DESC_MODE_8821C) << BIT_SHIFT_BEQ_DESC_MODE_8821C) +#define BITS_BEQ_DESC_MODE_8821C \ + (BIT_MASK_BEQ_DESC_MODE_8821C << BIT_SHIFT_BEQ_DESC_MODE_8821C) +#define BIT_CLEAR_BEQ_DESC_MODE_8821C(x) ((x) & (~BITS_BEQ_DESC_MODE_8821C)) +#define BIT_GET_BEQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8821C) & BIT_MASK_BEQ_DESC_MODE_8821C) +#define BIT_SET_BEQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_BEQ_DESC_MODE_8821C(x) | BIT_BEQ_DESC_MODE_8821C(v)) #define BIT_SHIFT_BEQ_DESC_NUM_8821C 0 #define BIT_MASK_BEQ_DESC_NUM_8821C 0xfff -#define BIT_BEQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8821C) << BIT_SHIFT_BEQ_DESC_NUM_8821C) -#define BIT_GET_BEQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8821C) & BIT_MASK_BEQ_DESC_NUM_8821C) - - +#define BIT_BEQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_BEQ_DESC_NUM_8821C) << BIT_SHIFT_BEQ_DESC_NUM_8821C) +#define BITS_BEQ_DESC_NUM_8821C \ + (BIT_MASK_BEQ_DESC_NUM_8821C << BIT_SHIFT_BEQ_DESC_NUM_8821C) +#define BIT_CLEAR_BEQ_DESC_NUM_8821C(x) ((x) & (~BITS_BEQ_DESC_NUM_8821C)) +#define BIT_GET_BEQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8821C) & BIT_MASK_BEQ_DESC_NUM_8821C) +#define BIT_SET_BEQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_BEQ_DESC_NUM_8821C(x) | BIT_BEQ_DESC_NUM_8821C(v)) /* 2 REG_BKQ_TXBD_NUM_8821C */ #define BIT_PCIE_BKQ_FLAG_8821C BIT(14) #define BIT_SHIFT_BKQ_DESC_MODE_8821C 12 #define BIT_MASK_BKQ_DESC_MODE_8821C 0x3 -#define BIT_BKQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8821C) << BIT_SHIFT_BKQ_DESC_MODE_8821C) -#define BIT_GET_BKQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8821C) & BIT_MASK_BKQ_DESC_MODE_8821C) - - +#define BIT_BKQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_BKQ_DESC_MODE_8821C) << BIT_SHIFT_BKQ_DESC_MODE_8821C) +#define BITS_BKQ_DESC_MODE_8821C \ + (BIT_MASK_BKQ_DESC_MODE_8821C << BIT_SHIFT_BKQ_DESC_MODE_8821C) +#define BIT_CLEAR_BKQ_DESC_MODE_8821C(x) ((x) & (~BITS_BKQ_DESC_MODE_8821C)) +#define BIT_GET_BKQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8821C) & BIT_MASK_BKQ_DESC_MODE_8821C) +#define BIT_SET_BKQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_BKQ_DESC_MODE_8821C(x) | BIT_BKQ_DESC_MODE_8821C(v)) #define BIT_SHIFT_BKQ_DESC_NUM_8821C 0 #define BIT_MASK_BKQ_DESC_NUM_8821C 0xfff -#define BIT_BKQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8821C) << BIT_SHIFT_BKQ_DESC_NUM_8821C) -#define BIT_GET_BKQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8821C) & BIT_MASK_BKQ_DESC_NUM_8821C) - - +#define BIT_BKQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_BKQ_DESC_NUM_8821C) << BIT_SHIFT_BKQ_DESC_NUM_8821C) +#define BITS_BKQ_DESC_NUM_8821C \ + (BIT_MASK_BKQ_DESC_NUM_8821C << BIT_SHIFT_BKQ_DESC_NUM_8821C) +#define BIT_CLEAR_BKQ_DESC_NUM_8821C(x) ((x) & (~BITS_BKQ_DESC_NUM_8821C)) +#define BIT_GET_BKQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8821C) & BIT_MASK_BKQ_DESC_NUM_8821C) +#define BIT_SET_BKQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_BKQ_DESC_NUM_8821C(x) | BIT_BKQ_DESC_NUM_8821C(v)) /* 2 REG_HI0Q_TXBD_NUM_8821C */ #define BIT_HI0Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI0Q_DESC_MODE_8821C 12 #define BIT_MASK_HI0Q_DESC_MODE_8821C 0x3 -#define BIT_HI0Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8821C) << BIT_SHIFT_HI0Q_DESC_MODE_8821C) -#define BIT_GET_HI0Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8821C) & BIT_MASK_HI0Q_DESC_MODE_8821C) - - +#define BIT_HI0Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI0Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI0Q_DESC_MODE_8821C) +#define BITS_HI0Q_DESC_MODE_8821C \ + (BIT_MASK_HI0Q_DESC_MODE_8821C << BIT_SHIFT_HI0Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI0Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI0Q_DESC_MODE_8821C)) +#define BIT_GET_HI0Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8821C) & \ + BIT_MASK_HI0Q_DESC_MODE_8821C) +#define BIT_SET_HI0Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI0Q_DESC_MODE_8821C(x) | BIT_HI0Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI0Q_DESC_NUM_8821C 0 #define BIT_MASK_HI0Q_DESC_NUM_8821C 0xfff -#define BIT_HI0Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8821C) << BIT_SHIFT_HI0Q_DESC_NUM_8821C) -#define BIT_GET_HI0Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8821C) & BIT_MASK_HI0Q_DESC_NUM_8821C) - - +#define BIT_HI0Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI0Q_DESC_NUM_8821C) << BIT_SHIFT_HI0Q_DESC_NUM_8821C) +#define BITS_HI0Q_DESC_NUM_8821C \ + (BIT_MASK_HI0Q_DESC_NUM_8821C << BIT_SHIFT_HI0Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI0Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI0Q_DESC_NUM_8821C)) +#define BIT_GET_HI0Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8821C) & BIT_MASK_HI0Q_DESC_NUM_8821C) +#define BIT_SET_HI0Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI0Q_DESC_NUM_8821C(x) | BIT_HI0Q_DESC_NUM_8821C(v)) /* 2 REG_HI1Q_TXBD_NUM_8821C */ #define BIT_HI1Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI1Q_DESC_MODE_8821C 12 #define BIT_MASK_HI1Q_DESC_MODE_8821C 0x3 -#define BIT_HI1Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8821C) << BIT_SHIFT_HI1Q_DESC_MODE_8821C) -#define BIT_GET_HI1Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8821C) & BIT_MASK_HI1Q_DESC_MODE_8821C) - - +#define BIT_HI1Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI1Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI1Q_DESC_MODE_8821C) +#define BITS_HI1Q_DESC_MODE_8821C \ + (BIT_MASK_HI1Q_DESC_MODE_8821C << BIT_SHIFT_HI1Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI1Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI1Q_DESC_MODE_8821C)) +#define BIT_GET_HI1Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8821C) & \ + BIT_MASK_HI1Q_DESC_MODE_8821C) +#define BIT_SET_HI1Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI1Q_DESC_MODE_8821C(x) | BIT_HI1Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI1Q_DESC_NUM_8821C 0 #define BIT_MASK_HI1Q_DESC_NUM_8821C 0xfff -#define BIT_HI1Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8821C) << BIT_SHIFT_HI1Q_DESC_NUM_8821C) -#define BIT_GET_HI1Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8821C) & BIT_MASK_HI1Q_DESC_NUM_8821C) - - +#define BIT_HI1Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI1Q_DESC_NUM_8821C) << BIT_SHIFT_HI1Q_DESC_NUM_8821C) +#define BITS_HI1Q_DESC_NUM_8821C \ + (BIT_MASK_HI1Q_DESC_NUM_8821C << BIT_SHIFT_HI1Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI1Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI1Q_DESC_NUM_8821C)) +#define BIT_GET_HI1Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8821C) & BIT_MASK_HI1Q_DESC_NUM_8821C) +#define BIT_SET_HI1Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI1Q_DESC_NUM_8821C(x) | BIT_HI1Q_DESC_NUM_8821C(v)) /* 2 REG_HI2Q_TXBD_NUM_8821C */ #define BIT_HI2Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI2Q_DESC_MODE_8821C 12 #define BIT_MASK_HI2Q_DESC_MODE_8821C 0x3 -#define BIT_HI2Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8821C) << BIT_SHIFT_HI2Q_DESC_MODE_8821C) -#define BIT_GET_HI2Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8821C) & BIT_MASK_HI2Q_DESC_MODE_8821C) - - +#define BIT_HI2Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI2Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI2Q_DESC_MODE_8821C) +#define BITS_HI2Q_DESC_MODE_8821C \ + (BIT_MASK_HI2Q_DESC_MODE_8821C << BIT_SHIFT_HI2Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI2Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI2Q_DESC_MODE_8821C)) +#define BIT_GET_HI2Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8821C) & \ + BIT_MASK_HI2Q_DESC_MODE_8821C) +#define BIT_SET_HI2Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI2Q_DESC_MODE_8821C(x) | BIT_HI2Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI2Q_DESC_NUM_8821C 0 #define BIT_MASK_HI2Q_DESC_NUM_8821C 0xfff -#define BIT_HI2Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8821C) << BIT_SHIFT_HI2Q_DESC_NUM_8821C) -#define BIT_GET_HI2Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8821C) & BIT_MASK_HI2Q_DESC_NUM_8821C) - - +#define BIT_HI2Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI2Q_DESC_NUM_8821C) << BIT_SHIFT_HI2Q_DESC_NUM_8821C) +#define BITS_HI2Q_DESC_NUM_8821C \ + (BIT_MASK_HI2Q_DESC_NUM_8821C << BIT_SHIFT_HI2Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI2Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI2Q_DESC_NUM_8821C)) +#define BIT_GET_HI2Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8821C) & BIT_MASK_HI2Q_DESC_NUM_8821C) +#define BIT_SET_HI2Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI2Q_DESC_NUM_8821C(x) | BIT_HI2Q_DESC_NUM_8821C(v)) /* 2 REG_HI3Q_TXBD_NUM_8821C */ #define BIT_HI3Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI3Q_DESC_MODE_8821C 12 #define BIT_MASK_HI3Q_DESC_MODE_8821C 0x3 -#define BIT_HI3Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8821C) << BIT_SHIFT_HI3Q_DESC_MODE_8821C) -#define BIT_GET_HI3Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8821C) & BIT_MASK_HI3Q_DESC_MODE_8821C) - - +#define BIT_HI3Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI3Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI3Q_DESC_MODE_8821C) +#define BITS_HI3Q_DESC_MODE_8821C \ + (BIT_MASK_HI3Q_DESC_MODE_8821C << BIT_SHIFT_HI3Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI3Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI3Q_DESC_MODE_8821C)) +#define BIT_GET_HI3Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8821C) & \ + BIT_MASK_HI3Q_DESC_MODE_8821C) +#define BIT_SET_HI3Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI3Q_DESC_MODE_8821C(x) | BIT_HI3Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI3Q_DESC_NUM_8821C 0 #define BIT_MASK_HI3Q_DESC_NUM_8821C 0xfff -#define BIT_HI3Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8821C) << BIT_SHIFT_HI3Q_DESC_NUM_8821C) -#define BIT_GET_HI3Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8821C) & BIT_MASK_HI3Q_DESC_NUM_8821C) - - +#define BIT_HI3Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI3Q_DESC_NUM_8821C) << BIT_SHIFT_HI3Q_DESC_NUM_8821C) +#define BITS_HI3Q_DESC_NUM_8821C \ + (BIT_MASK_HI3Q_DESC_NUM_8821C << BIT_SHIFT_HI3Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI3Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI3Q_DESC_NUM_8821C)) +#define BIT_GET_HI3Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8821C) & BIT_MASK_HI3Q_DESC_NUM_8821C) +#define BIT_SET_HI3Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI3Q_DESC_NUM_8821C(x) | BIT_HI3Q_DESC_NUM_8821C(v)) /* 2 REG_HI4Q_TXBD_NUM_8821C */ #define BIT_HI4Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI4Q_DESC_MODE_8821C 12 #define BIT_MASK_HI4Q_DESC_MODE_8821C 0x3 -#define BIT_HI4Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8821C) << BIT_SHIFT_HI4Q_DESC_MODE_8821C) -#define BIT_GET_HI4Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8821C) & BIT_MASK_HI4Q_DESC_MODE_8821C) - - +#define BIT_HI4Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI4Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI4Q_DESC_MODE_8821C) +#define BITS_HI4Q_DESC_MODE_8821C \ + (BIT_MASK_HI4Q_DESC_MODE_8821C << BIT_SHIFT_HI4Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI4Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI4Q_DESC_MODE_8821C)) +#define BIT_GET_HI4Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8821C) & \ + BIT_MASK_HI4Q_DESC_MODE_8821C) +#define BIT_SET_HI4Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI4Q_DESC_MODE_8821C(x) | BIT_HI4Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI4Q_DESC_NUM_8821C 0 #define BIT_MASK_HI4Q_DESC_NUM_8821C 0xfff -#define BIT_HI4Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8821C) << BIT_SHIFT_HI4Q_DESC_NUM_8821C) -#define BIT_GET_HI4Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8821C) & BIT_MASK_HI4Q_DESC_NUM_8821C) - - +#define BIT_HI4Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI4Q_DESC_NUM_8821C) << BIT_SHIFT_HI4Q_DESC_NUM_8821C) +#define BITS_HI4Q_DESC_NUM_8821C \ + (BIT_MASK_HI4Q_DESC_NUM_8821C << BIT_SHIFT_HI4Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI4Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI4Q_DESC_NUM_8821C)) +#define BIT_GET_HI4Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8821C) & BIT_MASK_HI4Q_DESC_NUM_8821C) +#define BIT_SET_HI4Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI4Q_DESC_NUM_8821C(x) | BIT_HI4Q_DESC_NUM_8821C(v)) /* 2 REG_HI5Q_TXBD_NUM_8821C */ #define BIT_HI5Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI5Q_DESC_MODE_8821C 12 #define BIT_MASK_HI5Q_DESC_MODE_8821C 0x3 -#define BIT_HI5Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8821C) << BIT_SHIFT_HI5Q_DESC_MODE_8821C) -#define BIT_GET_HI5Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8821C) & BIT_MASK_HI5Q_DESC_MODE_8821C) - - +#define BIT_HI5Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI5Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI5Q_DESC_MODE_8821C) +#define BITS_HI5Q_DESC_MODE_8821C \ + (BIT_MASK_HI5Q_DESC_MODE_8821C << BIT_SHIFT_HI5Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI5Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI5Q_DESC_MODE_8821C)) +#define BIT_GET_HI5Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8821C) & \ + BIT_MASK_HI5Q_DESC_MODE_8821C) +#define BIT_SET_HI5Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI5Q_DESC_MODE_8821C(x) | BIT_HI5Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI5Q_DESC_NUM_8821C 0 #define BIT_MASK_HI5Q_DESC_NUM_8821C 0xfff -#define BIT_HI5Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8821C) << BIT_SHIFT_HI5Q_DESC_NUM_8821C) -#define BIT_GET_HI5Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8821C) & BIT_MASK_HI5Q_DESC_NUM_8821C) - - +#define BIT_HI5Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI5Q_DESC_NUM_8821C) << BIT_SHIFT_HI5Q_DESC_NUM_8821C) +#define BITS_HI5Q_DESC_NUM_8821C \ + (BIT_MASK_HI5Q_DESC_NUM_8821C << BIT_SHIFT_HI5Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI5Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI5Q_DESC_NUM_8821C)) +#define BIT_GET_HI5Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8821C) & BIT_MASK_HI5Q_DESC_NUM_8821C) +#define BIT_SET_HI5Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI5Q_DESC_NUM_8821C(x) | BIT_HI5Q_DESC_NUM_8821C(v)) /* 2 REG_HI6Q_TXBD_NUM_8821C */ #define BIT_HI6Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI6Q_DESC_MODE_8821C 12 #define BIT_MASK_HI6Q_DESC_MODE_8821C 0x3 -#define BIT_HI6Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8821C) << BIT_SHIFT_HI6Q_DESC_MODE_8821C) -#define BIT_GET_HI6Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8821C) & BIT_MASK_HI6Q_DESC_MODE_8821C) - - +#define BIT_HI6Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI6Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI6Q_DESC_MODE_8821C) +#define BITS_HI6Q_DESC_MODE_8821C \ + (BIT_MASK_HI6Q_DESC_MODE_8821C << BIT_SHIFT_HI6Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI6Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI6Q_DESC_MODE_8821C)) +#define BIT_GET_HI6Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8821C) & \ + BIT_MASK_HI6Q_DESC_MODE_8821C) +#define BIT_SET_HI6Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI6Q_DESC_MODE_8821C(x) | BIT_HI6Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI6Q_DESC_NUM_8821C 0 #define BIT_MASK_HI6Q_DESC_NUM_8821C 0xfff -#define BIT_HI6Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8821C) << BIT_SHIFT_HI6Q_DESC_NUM_8821C) -#define BIT_GET_HI6Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8821C) & BIT_MASK_HI6Q_DESC_NUM_8821C) - - +#define BIT_HI6Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI6Q_DESC_NUM_8821C) << BIT_SHIFT_HI6Q_DESC_NUM_8821C) +#define BITS_HI6Q_DESC_NUM_8821C \ + (BIT_MASK_HI6Q_DESC_NUM_8821C << BIT_SHIFT_HI6Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI6Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI6Q_DESC_NUM_8821C)) +#define BIT_GET_HI6Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8821C) & BIT_MASK_HI6Q_DESC_NUM_8821C) +#define BIT_SET_HI6Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI6Q_DESC_NUM_8821C(x) | BIT_HI6Q_DESC_NUM_8821C(v)) /* 2 REG_HI7Q_TXBD_NUM_8821C */ #define BIT_HI7Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI7Q_DESC_MODE_8821C 12 #define BIT_MASK_HI7Q_DESC_MODE_8821C 0x3 -#define BIT_HI7Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8821C) << BIT_SHIFT_HI7Q_DESC_MODE_8821C) -#define BIT_GET_HI7Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8821C) & BIT_MASK_HI7Q_DESC_MODE_8821C) - - +#define BIT_HI7Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI7Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI7Q_DESC_MODE_8821C) +#define BITS_HI7Q_DESC_MODE_8821C \ + (BIT_MASK_HI7Q_DESC_MODE_8821C << BIT_SHIFT_HI7Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI7Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI7Q_DESC_MODE_8821C)) +#define BIT_GET_HI7Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8821C) & \ + BIT_MASK_HI7Q_DESC_MODE_8821C) +#define BIT_SET_HI7Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI7Q_DESC_MODE_8821C(x) | BIT_HI7Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI7Q_DESC_NUM_8821C 0 #define BIT_MASK_HI7Q_DESC_NUM_8821C 0xfff -#define BIT_HI7Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8821C) << BIT_SHIFT_HI7Q_DESC_NUM_8821C) -#define BIT_GET_HI7Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8821C) & BIT_MASK_HI7Q_DESC_NUM_8821C) - - +#define BIT_HI7Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI7Q_DESC_NUM_8821C) << BIT_SHIFT_HI7Q_DESC_NUM_8821C) +#define BITS_HI7Q_DESC_NUM_8821C \ + (BIT_MASK_HI7Q_DESC_NUM_8821C << BIT_SHIFT_HI7Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI7Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI7Q_DESC_NUM_8821C)) +#define BIT_GET_HI7Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8821C) & BIT_MASK_HI7Q_DESC_NUM_8821C) +#define BIT_SET_HI7Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI7Q_DESC_NUM_8821C(x) | BIT_HI7Q_DESC_NUM_8821C(v)) /* 2 REG_TSFTIMER_HCI_8821C */ #define BIT_SHIFT_TSFT2_HCI_8821C 16 #define BIT_MASK_TSFT2_HCI_8821C 0xffff -#define BIT_TSFT2_HCI_8821C(x) (((x) & BIT_MASK_TSFT2_HCI_8821C) << BIT_SHIFT_TSFT2_HCI_8821C) -#define BIT_GET_TSFT2_HCI_8821C(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8821C) & BIT_MASK_TSFT2_HCI_8821C) - - +#define BIT_TSFT2_HCI_8821C(x) \ + (((x) & BIT_MASK_TSFT2_HCI_8821C) << BIT_SHIFT_TSFT2_HCI_8821C) +#define BITS_TSFT2_HCI_8821C \ + (BIT_MASK_TSFT2_HCI_8821C << BIT_SHIFT_TSFT2_HCI_8821C) +#define BIT_CLEAR_TSFT2_HCI_8821C(x) ((x) & (~BITS_TSFT2_HCI_8821C)) +#define BIT_GET_TSFT2_HCI_8821C(x) \ + (((x) >> BIT_SHIFT_TSFT2_HCI_8821C) & BIT_MASK_TSFT2_HCI_8821C) +#define BIT_SET_TSFT2_HCI_8821C(x, v) \ + (BIT_CLEAR_TSFT2_HCI_8821C(x) | BIT_TSFT2_HCI_8821C(v)) #define BIT_SHIFT_TSFT1_HCI_8821C 0 #define BIT_MASK_TSFT1_HCI_8821C 0xffff -#define BIT_TSFT1_HCI_8821C(x) (((x) & BIT_MASK_TSFT1_HCI_8821C) << BIT_SHIFT_TSFT1_HCI_8821C) -#define BIT_GET_TSFT1_HCI_8821C(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8821C) & BIT_MASK_TSFT1_HCI_8821C) - - +#define BIT_TSFT1_HCI_8821C(x) \ + (((x) & BIT_MASK_TSFT1_HCI_8821C) << BIT_SHIFT_TSFT1_HCI_8821C) +#define BITS_TSFT1_HCI_8821C \ + (BIT_MASK_TSFT1_HCI_8821C << BIT_SHIFT_TSFT1_HCI_8821C) +#define BIT_CLEAR_TSFT1_HCI_8821C(x) ((x) & (~BITS_TSFT1_HCI_8821C)) +#define BIT_GET_TSFT1_HCI_8821C(x) \ + (((x) >> BIT_SHIFT_TSFT1_HCI_8821C) & BIT_MASK_TSFT1_HCI_8821C) +#define BIT_SET_TSFT1_HCI_8821C(x, v) \ + (BIT_CLEAR_TSFT1_HCI_8821C(x) | BIT_TSFT1_HCI_8821C(v)) /* 2 REG_BD_RWPTR_CLR_8821C */ #define BIT_CLR_HI7Q_HW_IDX_8821C BIT(29) @@ -4789,252 +7784,406 @@ #define BIT_SHIFT_VOQ_HW_IDX_8821C 16 #define BIT_MASK_VOQ_HW_IDX_8821C 0xfff -#define BIT_VOQ_HW_IDX_8821C(x) (((x) & BIT_MASK_VOQ_HW_IDX_8821C) << BIT_SHIFT_VOQ_HW_IDX_8821C) -#define BIT_GET_VOQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8821C) & BIT_MASK_VOQ_HW_IDX_8821C) - - +#define BIT_VOQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_VOQ_HW_IDX_8821C) << BIT_SHIFT_VOQ_HW_IDX_8821C) +#define BITS_VOQ_HW_IDX_8821C \ + (BIT_MASK_VOQ_HW_IDX_8821C << BIT_SHIFT_VOQ_HW_IDX_8821C) +#define BIT_CLEAR_VOQ_HW_IDX_8821C(x) ((x) & (~BITS_VOQ_HW_IDX_8821C)) +#define BIT_GET_VOQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_VOQ_HW_IDX_8821C) & BIT_MASK_VOQ_HW_IDX_8821C) +#define BIT_SET_VOQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_VOQ_HW_IDX_8821C(x) | BIT_VOQ_HW_IDX_8821C(v)) #define BIT_SHIFT_VOQ_HOST_IDX_8821C 0 #define BIT_MASK_VOQ_HOST_IDX_8821C 0xfff -#define BIT_VOQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8821C) << BIT_SHIFT_VOQ_HOST_IDX_8821C) -#define BIT_GET_VOQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8821C) & BIT_MASK_VOQ_HOST_IDX_8821C) - - +#define BIT_VOQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_VOQ_HOST_IDX_8821C) << BIT_SHIFT_VOQ_HOST_IDX_8821C) +#define BITS_VOQ_HOST_IDX_8821C \ + (BIT_MASK_VOQ_HOST_IDX_8821C << BIT_SHIFT_VOQ_HOST_IDX_8821C) +#define BIT_CLEAR_VOQ_HOST_IDX_8821C(x) ((x) & (~BITS_VOQ_HOST_IDX_8821C)) +#define BIT_GET_VOQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8821C) & BIT_MASK_VOQ_HOST_IDX_8821C) +#define BIT_SET_VOQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_VOQ_HOST_IDX_8821C(x) | BIT_VOQ_HOST_IDX_8821C(v)) /* 2 REG_VIQ_TXBD_IDX_8821C */ #define BIT_SHIFT_VIQ_HW_IDX_8821C 16 #define BIT_MASK_VIQ_HW_IDX_8821C 0xfff -#define BIT_VIQ_HW_IDX_8821C(x) (((x) & BIT_MASK_VIQ_HW_IDX_8821C) << BIT_SHIFT_VIQ_HW_IDX_8821C) -#define BIT_GET_VIQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8821C) & BIT_MASK_VIQ_HW_IDX_8821C) - - +#define BIT_VIQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_VIQ_HW_IDX_8821C) << BIT_SHIFT_VIQ_HW_IDX_8821C) +#define BITS_VIQ_HW_IDX_8821C \ + (BIT_MASK_VIQ_HW_IDX_8821C << BIT_SHIFT_VIQ_HW_IDX_8821C) +#define BIT_CLEAR_VIQ_HW_IDX_8821C(x) ((x) & (~BITS_VIQ_HW_IDX_8821C)) +#define BIT_GET_VIQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_VIQ_HW_IDX_8821C) & BIT_MASK_VIQ_HW_IDX_8821C) +#define BIT_SET_VIQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_VIQ_HW_IDX_8821C(x) | BIT_VIQ_HW_IDX_8821C(v)) #define BIT_SHIFT_VIQ_HOST_IDX_8821C 0 #define BIT_MASK_VIQ_HOST_IDX_8821C 0xfff -#define BIT_VIQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8821C) << BIT_SHIFT_VIQ_HOST_IDX_8821C) -#define BIT_GET_VIQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8821C) & BIT_MASK_VIQ_HOST_IDX_8821C) - - +#define BIT_VIQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_VIQ_HOST_IDX_8821C) << BIT_SHIFT_VIQ_HOST_IDX_8821C) +#define BITS_VIQ_HOST_IDX_8821C \ + (BIT_MASK_VIQ_HOST_IDX_8821C << BIT_SHIFT_VIQ_HOST_IDX_8821C) +#define BIT_CLEAR_VIQ_HOST_IDX_8821C(x) ((x) & (~BITS_VIQ_HOST_IDX_8821C)) +#define BIT_GET_VIQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8821C) & BIT_MASK_VIQ_HOST_IDX_8821C) +#define BIT_SET_VIQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_VIQ_HOST_IDX_8821C(x) | BIT_VIQ_HOST_IDX_8821C(v)) /* 2 REG_BEQ_TXBD_IDX_8821C */ #define BIT_SHIFT_BEQ_HW_IDX_8821C 16 #define BIT_MASK_BEQ_HW_IDX_8821C 0xfff -#define BIT_BEQ_HW_IDX_8821C(x) (((x) & BIT_MASK_BEQ_HW_IDX_8821C) << BIT_SHIFT_BEQ_HW_IDX_8821C) -#define BIT_GET_BEQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8821C) & BIT_MASK_BEQ_HW_IDX_8821C) - - +#define BIT_BEQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_BEQ_HW_IDX_8821C) << BIT_SHIFT_BEQ_HW_IDX_8821C) +#define BITS_BEQ_HW_IDX_8821C \ + (BIT_MASK_BEQ_HW_IDX_8821C << BIT_SHIFT_BEQ_HW_IDX_8821C) +#define BIT_CLEAR_BEQ_HW_IDX_8821C(x) ((x) & (~BITS_BEQ_HW_IDX_8821C)) +#define BIT_GET_BEQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_BEQ_HW_IDX_8821C) & BIT_MASK_BEQ_HW_IDX_8821C) +#define BIT_SET_BEQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_BEQ_HW_IDX_8821C(x) | BIT_BEQ_HW_IDX_8821C(v)) #define BIT_SHIFT_BEQ_HOST_IDX_8821C 0 #define BIT_MASK_BEQ_HOST_IDX_8821C 0xfff -#define BIT_BEQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8821C) << BIT_SHIFT_BEQ_HOST_IDX_8821C) -#define BIT_GET_BEQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8821C) & BIT_MASK_BEQ_HOST_IDX_8821C) - - +#define BIT_BEQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_BEQ_HOST_IDX_8821C) << BIT_SHIFT_BEQ_HOST_IDX_8821C) +#define BITS_BEQ_HOST_IDX_8821C \ + (BIT_MASK_BEQ_HOST_IDX_8821C << BIT_SHIFT_BEQ_HOST_IDX_8821C) +#define BIT_CLEAR_BEQ_HOST_IDX_8821C(x) ((x) & (~BITS_BEQ_HOST_IDX_8821C)) +#define BIT_GET_BEQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8821C) & BIT_MASK_BEQ_HOST_IDX_8821C) +#define BIT_SET_BEQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_BEQ_HOST_IDX_8821C(x) | BIT_BEQ_HOST_IDX_8821C(v)) /* 2 REG_BKQ_TXBD_IDX_8821C */ #define BIT_SHIFT_BKQ_HW_IDX_8821C 16 #define BIT_MASK_BKQ_HW_IDX_8821C 0xfff -#define BIT_BKQ_HW_IDX_8821C(x) (((x) & BIT_MASK_BKQ_HW_IDX_8821C) << BIT_SHIFT_BKQ_HW_IDX_8821C) -#define BIT_GET_BKQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8821C) & BIT_MASK_BKQ_HW_IDX_8821C) - - +#define BIT_BKQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_BKQ_HW_IDX_8821C) << BIT_SHIFT_BKQ_HW_IDX_8821C) +#define BITS_BKQ_HW_IDX_8821C \ + (BIT_MASK_BKQ_HW_IDX_8821C << BIT_SHIFT_BKQ_HW_IDX_8821C) +#define BIT_CLEAR_BKQ_HW_IDX_8821C(x) ((x) & (~BITS_BKQ_HW_IDX_8821C)) +#define BIT_GET_BKQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_BKQ_HW_IDX_8821C) & BIT_MASK_BKQ_HW_IDX_8821C) +#define BIT_SET_BKQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_BKQ_HW_IDX_8821C(x) | BIT_BKQ_HW_IDX_8821C(v)) #define BIT_SHIFT_BKQ_HOST_IDX_8821C 0 #define BIT_MASK_BKQ_HOST_IDX_8821C 0xfff -#define BIT_BKQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8821C) << BIT_SHIFT_BKQ_HOST_IDX_8821C) -#define BIT_GET_BKQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8821C) & BIT_MASK_BKQ_HOST_IDX_8821C) - - +#define BIT_BKQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_BKQ_HOST_IDX_8821C) << BIT_SHIFT_BKQ_HOST_IDX_8821C) +#define BITS_BKQ_HOST_IDX_8821C \ + (BIT_MASK_BKQ_HOST_IDX_8821C << BIT_SHIFT_BKQ_HOST_IDX_8821C) +#define BIT_CLEAR_BKQ_HOST_IDX_8821C(x) ((x) & (~BITS_BKQ_HOST_IDX_8821C)) +#define BIT_GET_BKQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8821C) & BIT_MASK_BKQ_HOST_IDX_8821C) +#define BIT_SET_BKQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_BKQ_HOST_IDX_8821C(x) | BIT_BKQ_HOST_IDX_8821C(v)) /* 2 REG_MGQ_TXBD_IDX_8821C */ #define BIT_SHIFT_MGQ_HW_IDX_8821C 16 #define BIT_MASK_MGQ_HW_IDX_8821C 0xfff -#define BIT_MGQ_HW_IDX_8821C(x) (((x) & BIT_MASK_MGQ_HW_IDX_8821C) << BIT_SHIFT_MGQ_HW_IDX_8821C) -#define BIT_GET_MGQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8821C) & BIT_MASK_MGQ_HW_IDX_8821C) - - +#define BIT_MGQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_MGQ_HW_IDX_8821C) << BIT_SHIFT_MGQ_HW_IDX_8821C) +#define BITS_MGQ_HW_IDX_8821C \ + (BIT_MASK_MGQ_HW_IDX_8821C << BIT_SHIFT_MGQ_HW_IDX_8821C) +#define BIT_CLEAR_MGQ_HW_IDX_8821C(x) ((x) & (~BITS_MGQ_HW_IDX_8821C)) +#define BIT_GET_MGQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_HW_IDX_8821C) & BIT_MASK_MGQ_HW_IDX_8821C) +#define BIT_SET_MGQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_MGQ_HW_IDX_8821C(x) | BIT_MGQ_HW_IDX_8821C(v)) #define BIT_SHIFT_MGQ_HOST_IDX_8821C 0 #define BIT_MASK_MGQ_HOST_IDX_8821C 0xfff -#define BIT_MGQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8821C) << BIT_SHIFT_MGQ_HOST_IDX_8821C) -#define BIT_GET_MGQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8821C) & BIT_MASK_MGQ_HOST_IDX_8821C) - - +#define BIT_MGQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_MGQ_HOST_IDX_8821C) << BIT_SHIFT_MGQ_HOST_IDX_8821C) +#define BITS_MGQ_HOST_IDX_8821C \ + (BIT_MASK_MGQ_HOST_IDX_8821C << BIT_SHIFT_MGQ_HOST_IDX_8821C) +#define BIT_CLEAR_MGQ_HOST_IDX_8821C(x) ((x) & (~BITS_MGQ_HOST_IDX_8821C)) +#define BIT_GET_MGQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8821C) & BIT_MASK_MGQ_HOST_IDX_8821C) +#define BIT_SET_MGQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_MGQ_HOST_IDX_8821C(x) | BIT_MGQ_HOST_IDX_8821C(v)) /* 2 REG_RXQ_RXBD_IDX_8821C */ #define BIT_SHIFT_RXQ_HW_IDX_8821C 16 #define BIT_MASK_RXQ_HW_IDX_8821C 0xfff -#define BIT_RXQ_HW_IDX_8821C(x) (((x) & BIT_MASK_RXQ_HW_IDX_8821C) << BIT_SHIFT_RXQ_HW_IDX_8821C) -#define BIT_GET_RXQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8821C) & BIT_MASK_RXQ_HW_IDX_8821C) - - +#define BIT_RXQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_RXQ_HW_IDX_8821C) << BIT_SHIFT_RXQ_HW_IDX_8821C) +#define BITS_RXQ_HW_IDX_8821C \ + (BIT_MASK_RXQ_HW_IDX_8821C << BIT_SHIFT_RXQ_HW_IDX_8821C) +#define BIT_CLEAR_RXQ_HW_IDX_8821C(x) ((x) & (~BITS_RXQ_HW_IDX_8821C)) +#define BIT_GET_RXQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RXQ_HW_IDX_8821C) & BIT_MASK_RXQ_HW_IDX_8821C) +#define BIT_SET_RXQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_RXQ_HW_IDX_8821C(x) | BIT_RXQ_HW_IDX_8821C(v)) #define BIT_SHIFT_RXQ_HOST_IDX_8821C 0 #define BIT_MASK_RXQ_HOST_IDX_8821C 0xfff -#define BIT_RXQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8821C) << BIT_SHIFT_RXQ_HOST_IDX_8821C) -#define BIT_GET_RXQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8821C) & BIT_MASK_RXQ_HOST_IDX_8821C) - - +#define BIT_RXQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_RXQ_HOST_IDX_8821C) << BIT_SHIFT_RXQ_HOST_IDX_8821C) +#define BITS_RXQ_HOST_IDX_8821C \ + (BIT_MASK_RXQ_HOST_IDX_8821C << BIT_SHIFT_RXQ_HOST_IDX_8821C) +#define BIT_CLEAR_RXQ_HOST_IDX_8821C(x) ((x) & (~BITS_RXQ_HOST_IDX_8821C)) +#define BIT_GET_RXQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8821C) & BIT_MASK_RXQ_HOST_IDX_8821C) +#define BIT_SET_RXQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_RXQ_HOST_IDX_8821C(x) | BIT_RXQ_HOST_IDX_8821C(v)) /* 2 REG_HI0Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI0Q_HW_IDX_8821C 16 #define BIT_MASK_HI0Q_HW_IDX_8821C 0xfff -#define BIT_HI0Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8821C) << BIT_SHIFT_HI0Q_HW_IDX_8821C) -#define BIT_GET_HI0Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8821C) & BIT_MASK_HI0Q_HW_IDX_8821C) - - +#define BIT_HI0Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI0Q_HW_IDX_8821C) << BIT_SHIFT_HI0Q_HW_IDX_8821C) +#define BITS_HI0Q_HW_IDX_8821C \ + (BIT_MASK_HI0Q_HW_IDX_8821C << BIT_SHIFT_HI0Q_HW_IDX_8821C) +#define BIT_CLEAR_HI0Q_HW_IDX_8821C(x) ((x) & (~BITS_HI0Q_HW_IDX_8821C)) +#define BIT_GET_HI0Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8821C) & BIT_MASK_HI0Q_HW_IDX_8821C) +#define BIT_SET_HI0Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI0Q_HW_IDX_8821C(x) | BIT_HI0Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI0Q_HOST_IDX_8821C 0 #define BIT_MASK_HI0Q_HOST_IDX_8821C 0xfff -#define BIT_HI0Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8821C) << BIT_SHIFT_HI0Q_HOST_IDX_8821C) -#define BIT_GET_HI0Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8821C) & BIT_MASK_HI0Q_HOST_IDX_8821C) - - +#define BIT_HI0Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI0Q_HOST_IDX_8821C) << BIT_SHIFT_HI0Q_HOST_IDX_8821C) +#define BITS_HI0Q_HOST_IDX_8821C \ + (BIT_MASK_HI0Q_HOST_IDX_8821C << BIT_SHIFT_HI0Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI0Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI0Q_HOST_IDX_8821C)) +#define BIT_GET_HI0Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8821C) & BIT_MASK_HI0Q_HOST_IDX_8821C) +#define BIT_SET_HI0Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI0Q_HOST_IDX_8821C(x) | BIT_HI0Q_HOST_IDX_8821C(v)) /* 2 REG_HI1Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI1Q_HW_IDX_8821C 16 #define BIT_MASK_HI1Q_HW_IDX_8821C 0xfff -#define BIT_HI1Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8821C) << BIT_SHIFT_HI1Q_HW_IDX_8821C) -#define BIT_GET_HI1Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8821C) & BIT_MASK_HI1Q_HW_IDX_8821C) - - +#define BIT_HI1Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI1Q_HW_IDX_8821C) << BIT_SHIFT_HI1Q_HW_IDX_8821C) +#define BITS_HI1Q_HW_IDX_8821C \ + (BIT_MASK_HI1Q_HW_IDX_8821C << BIT_SHIFT_HI1Q_HW_IDX_8821C) +#define BIT_CLEAR_HI1Q_HW_IDX_8821C(x) ((x) & (~BITS_HI1Q_HW_IDX_8821C)) +#define BIT_GET_HI1Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8821C) & BIT_MASK_HI1Q_HW_IDX_8821C) +#define BIT_SET_HI1Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI1Q_HW_IDX_8821C(x) | BIT_HI1Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI1Q_HOST_IDX_8821C 0 #define BIT_MASK_HI1Q_HOST_IDX_8821C 0xfff -#define BIT_HI1Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8821C) << BIT_SHIFT_HI1Q_HOST_IDX_8821C) -#define BIT_GET_HI1Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8821C) & BIT_MASK_HI1Q_HOST_IDX_8821C) - - +#define BIT_HI1Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI1Q_HOST_IDX_8821C) << BIT_SHIFT_HI1Q_HOST_IDX_8821C) +#define BITS_HI1Q_HOST_IDX_8821C \ + (BIT_MASK_HI1Q_HOST_IDX_8821C << BIT_SHIFT_HI1Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI1Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI1Q_HOST_IDX_8821C)) +#define BIT_GET_HI1Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8821C) & BIT_MASK_HI1Q_HOST_IDX_8821C) +#define BIT_SET_HI1Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI1Q_HOST_IDX_8821C(x) | BIT_HI1Q_HOST_IDX_8821C(v)) /* 2 REG_HI2Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI2Q_HW_IDX_8821C 16 #define BIT_MASK_HI2Q_HW_IDX_8821C 0xfff -#define BIT_HI2Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8821C) << BIT_SHIFT_HI2Q_HW_IDX_8821C) -#define BIT_GET_HI2Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8821C) & BIT_MASK_HI2Q_HW_IDX_8821C) - - +#define BIT_HI2Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI2Q_HW_IDX_8821C) << BIT_SHIFT_HI2Q_HW_IDX_8821C) +#define BITS_HI2Q_HW_IDX_8821C \ + (BIT_MASK_HI2Q_HW_IDX_8821C << BIT_SHIFT_HI2Q_HW_IDX_8821C) +#define BIT_CLEAR_HI2Q_HW_IDX_8821C(x) ((x) & (~BITS_HI2Q_HW_IDX_8821C)) +#define BIT_GET_HI2Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8821C) & BIT_MASK_HI2Q_HW_IDX_8821C) +#define BIT_SET_HI2Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI2Q_HW_IDX_8821C(x) | BIT_HI2Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI2Q_HOST_IDX_8821C 0 #define BIT_MASK_HI2Q_HOST_IDX_8821C 0xfff -#define BIT_HI2Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8821C) << BIT_SHIFT_HI2Q_HOST_IDX_8821C) -#define BIT_GET_HI2Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8821C) & BIT_MASK_HI2Q_HOST_IDX_8821C) - - +#define BIT_HI2Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI2Q_HOST_IDX_8821C) << BIT_SHIFT_HI2Q_HOST_IDX_8821C) +#define BITS_HI2Q_HOST_IDX_8821C \ + (BIT_MASK_HI2Q_HOST_IDX_8821C << BIT_SHIFT_HI2Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI2Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI2Q_HOST_IDX_8821C)) +#define BIT_GET_HI2Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8821C) & BIT_MASK_HI2Q_HOST_IDX_8821C) +#define BIT_SET_HI2Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI2Q_HOST_IDX_8821C(x) | BIT_HI2Q_HOST_IDX_8821C(v)) /* 2 REG_HI3Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI3Q_HW_IDX_8821C 16 #define BIT_MASK_HI3Q_HW_IDX_8821C 0xfff -#define BIT_HI3Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8821C) << BIT_SHIFT_HI3Q_HW_IDX_8821C) -#define BIT_GET_HI3Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8821C) & BIT_MASK_HI3Q_HW_IDX_8821C) - - +#define BIT_HI3Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI3Q_HW_IDX_8821C) << BIT_SHIFT_HI3Q_HW_IDX_8821C) +#define BITS_HI3Q_HW_IDX_8821C \ + (BIT_MASK_HI3Q_HW_IDX_8821C << BIT_SHIFT_HI3Q_HW_IDX_8821C) +#define BIT_CLEAR_HI3Q_HW_IDX_8821C(x) ((x) & (~BITS_HI3Q_HW_IDX_8821C)) +#define BIT_GET_HI3Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8821C) & BIT_MASK_HI3Q_HW_IDX_8821C) +#define BIT_SET_HI3Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI3Q_HW_IDX_8821C(x) | BIT_HI3Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI3Q_HOST_IDX_8821C 0 #define BIT_MASK_HI3Q_HOST_IDX_8821C 0xfff -#define BIT_HI3Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8821C) << BIT_SHIFT_HI3Q_HOST_IDX_8821C) -#define BIT_GET_HI3Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8821C) & BIT_MASK_HI3Q_HOST_IDX_8821C) - - +#define BIT_HI3Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI3Q_HOST_IDX_8821C) << BIT_SHIFT_HI3Q_HOST_IDX_8821C) +#define BITS_HI3Q_HOST_IDX_8821C \ + (BIT_MASK_HI3Q_HOST_IDX_8821C << BIT_SHIFT_HI3Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI3Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI3Q_HOST_IDX_8821C)) +#define BIT_GET_HI3Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8821C) & BIT_MASK_HI3Q_HOST_IDX_8821C) +#define BIT_SET_HI3Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI3Q_HOST_IDX_8821C(x) | BIT_HI3Q_HOST_IDX_8821C(v)) /* 2 REG_HI4Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI4Q_HW_IDX_8821C 16 #define BIT_MASK_HI4Q_HW_IDX_8821C 0xfff -#define BIT_HI4Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8821C) << BIT_SHIFT_HI4Q_HW_IDX_8821C) -#define BIT_GET_HI4Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8821C) & BIT_MASK_HI4Q_HW_IDX_8821C) - - +#define BIT_HI4Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI4Q_HW_IDX_8821C) << BIT_SHIFT_HI4Q_HW_IDX_8821C) +#define BITS_HI4Q_HW_IDX_8821C \ + (BIT_MASK_HI4Q_HW_IDX_8821C << BIT_SHIFT_HI4Q_HW_IDX_8821C) +#define BIT_CLEAR_HI4Q_HW_IDX_8821C(x) ((x) & (~BITS_HI4Q_HW_IDX_8821C)) +#define BIT_GET_HI4Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8821C) & BIT_MASK_HI4Q_HW_IDX_8821C) +#define BIT_SET_HI4Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI4Q_HW_IDX_8821C(x) | BIT_HI4Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI4Q_HOST_IDX_8821C 0 #define BIT_MASK_HI4Q_HOST_IDX_8821C 0xfff -#define BIT_HI4Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8821C) << BIT_SHIFT_HI4Q_HOST_IDX_8821C) -#define BIT_GET_HI4Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8821C) & BIT_MASK_HI4Q_HOST_IDX_8821C) - - +#define BIT_HI4Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI4Q_HOST_IDX_8821C) << BIT_SHIFT_HI4Q_HOST_IDX_8821C) +#define BITS_HI4Q_HOST_IDX_8821C \ + (BIT_MASK_HI4Q_HOST_IDX_8821C << BIT_SHIFT_HI4Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI4Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI4Q_HOST_IDX_8821C)) +#define BIT_GET_HI4Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8821C) & BIT_MASK_HI4Q_HOST_IDX_8821C) +#define BIT_SET_HI4Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI4Q_HOST_IDX_8821C(x) | BIT_HI4Q_HOST_IDX_8821C(v)) /* 2 REG_HI5Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI5Q_HW_IDX_8821C 16 #define BIT_MASK_HI5Q_HW_IDX_8821C 0xfff -#define BIT_HI5Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8821C) << BIT_SHIFT_HI5Q_HW_IDX_8821C) -#define BIT_GET_HI5Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8821C) & BIT_MASK_HI5Q_HW_IDX_8821C) - - +#define BIT_HI5Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI5Q_HW_IDX_8821C) << BIT_SHIFT_HI5Q_HW_IDX_8821C) +#define BITS_HI5Q_HW_IDX_8821C \ + (BIT_MASK_HI5Q_HW_IDX_8821C << BIT_SHIFT_HI5Q_HW_IDX_8821C) +#define BIT_CLEAR_HI5Q_HW_IDX_8821C(x) ((x) & (~BITS_HI5Q_HW_IDX_8821C)) +#define BIT_GET_HI5Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8821C) & BIT_MASK_HI5Q_HW_IDX_8821C) +#define BIT_SET_HI5Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI5Q_HW_IDX_8821C(x) | BIT_HI5Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI5Q_HOST_IDX_8821C 0 #define BIT_MASK_HI5Q_HOST_IDX_8821C 0xfff -#define BIT_HI5Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8821C) << BIT_SHIFT_HI5Q_HOST_IDX_8821C) -#define BIT_GET_HI5Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8821C) & BIT_MASK_HI5Q_HOST_IDX_8821C) - - +#define BIT_HI5Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI5Q_HOST_IDX_8821C) << BIT_SHIFT_HI5Q_HOST_IDX_8821C) +#define BITS_HI5Q_HOST_IDX_8821C \ + (BIT_MASK_HI5Q_HOST_IDX_8821C << BIT_SHIFT_HI5Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI5Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI5Q_HOST_IDX_8821C)) +#define BIT_GET_HI5Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8821C) & BIT_MASK_HI5Q_HOST_IDX_8821C) +#define BIT_SET_HI5Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI5Q_HOST_IDX_8821C(x) | BIT_HI5Q_HOST_IDX_8821C(v)) /* 2 REG_HI6Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI6Q_HW_IDX_8821C 16 #define BIT_MASK_HI6Q_HW_IDX_8821C 0xfff -#define BIT_HI6Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8821C) << BIT_SHIFT_HI6Q_HW_IDX_8821C) -#define BIT_GET_HI6Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8821C) & BIT_MASK_HI6Q_HW_IDX_8821C) - - +#define BIT_HI6Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI6Q_HW_IDX_8821C) << BIT_SHIFT_HI6Q_HW_IDX_8821C) +#define BITS_HI6Q_HW_IDX_8821C \ + (BIT_MASK_HI6Q_HW_IDX_8821C << BIT_SHIFT_HI6Q_HW_IDX_8821C) +#define BIT_CLEAR_HI6Q_HW_IDX_8821C(x) ((x) & (~BITS_HI6Q_HW_IDX_8821C)) +#define BIT_GET_HI6Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8821C) & BIT_MASK_HI6Q_HW_IDX_8821C) +#define BIT_SET_HI6Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI6Q_HW_IDX_8821C(x) | BIT_HI6Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI6Q_HOST_IDX_8821C 0 #define BIT_MASK_HI6Q_HOST_IDX_8821C 0xfff -#define BIT_HI6Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8821C) << BIT_SHIFT_HI6Q_HOST_IDX_8821C) -#define BIT_GET_HI6Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8821C) & BIT_MASK_HI6Q_HOST_IDX_8821C) - - +#define BIT_HI6Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI6Q_HOST_IDX_8821C) << BIT_SHIFT_HI6Q_HOST_IDX_8821C) +#define BITS_HI6Q_HOST_IDX_8821C \ + (BIT_MASK_HI6Q_HOST_IDX_8821C << BIT_SHIFT_HI6Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI6Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI6Q_HOST_IDX_8821C)) +#define BIT_GET_HI6Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8821C) & BIT_MASK_HI6Q_HOST_IDX_8821C) +#define BIT_SET_HI6Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI6Q_HOST_IDX_8821C(x) | BIT_HI6Q_HOST_IDX_8821C(v)) /* 2 REG_HI7Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI7Q_HW_IDX_8821C 16 #define BIT_MASK_HI7Q_HW_IDX_8821C 0xfff -#define BIT_HI7Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8821C) << BIT_SHIFT_HI7Q_HW_IDX_8821C) -#define BIT_GET_HI7Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8821C) & BIT_MASK_HI7Q_HW_IDX_8821C) - - +#define BIT_HI7Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI7Q_HW_IDX_8821C) << BIT_SHIFT_HI7Q_HW_IDX_8821C) +#define BITS_HI7Q_HW_IDX_8821C \ + (BIT_MASK_HI7Q_HW_IDX_8821C << BIT_SHIFT_HI7Q_HW_IDX_8821C) +#define BIT_CLEAR_HI7Q_HW_IDX_8821C(x) ((x) & (~BITS_HI7Q_HW_IDX_8821C)) +#define BIT_GET_HI7Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8821C) & BIT_MASK_HI7Q_HW_IDX_8821C) +#define BIT_SET_HI7Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI7Q_HW_IDX_8821C(x) | BIT_HI7Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI7Q_HOST_IDX_8821C 0 #define BIT_MASK_HI7Q_HOST_IDX_8821C 0xfff -#define BIT_HI7Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8821C) << BIT_SHIFT_HI7Q_HOST_IDX_8821C) -#define BIT_GET_HI7Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8821C) & BIT_MASK_HI7Q_HOST_IDX_8821C) - - +#define BIT_HI7Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI7Q_HOST_IDX_8821C) << BIT_SHIFT_HI7Q_HOST_IDX_8821C) +#define BITS_HI7Q_HOST_IDX_8821C \ + (BIT_MASK_HI7Q_HOST_IDX_8821C << BIT_SHIFT_HI7Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI7Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI7Q_HOST_IDX_8821C)) +#define BIT_GET_HI7Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8821C) & BIT_MASK_HI7Q_HOST_IDX_8821C) +#define BIT_SET_HI7Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI7Q_HOST_IDX_8821C(x) | BIT_HI7Q_HOST_IDX_8821C(v)) /* 2 REG_DBG_SEL_V1_8821C */ #define BIT_SHIFT_DBG_SEL_8821C 0 #define BIT_MASK_DBG_SEL_8821C 0xff -#define BIT_DBG_SEL_8821C(x) (((x) & BIT_MASK_DBG_SEL_8821C) << BIT_SHIFT_DBG_SEL_8821C) -#define BIT_GET_DBG_SEL_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_8821C) & BIT_MASK_DBG_SEL_8821C) - - +#define BIT_DBG_SEL_8821C(x) \ + (((x) & BIT_MASK_DBG_SEL_8821C) << BIT_SHIFT_DBG_SEL_8821C) +#define BITS_DBG_SEL_8821C (BIT_MASK_DBG_SEL_8821C << BIT_SHIFT_DBG_SEL_8821C) +#define BIT_CLEAR_DBG_SEL_8821C(x) ((x) & (~BITS_DBG_SEL_8821C)) +#define BIT_GET_DBG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_8821C) & BIT_MASK_DBG_SEL_8821C) +#define BIT_SET_DBG_SEL_8821C(x, v) \ + (BIT_CLEAR_DBG_SEL_8821C(x) | BIT_DBG_SEL_8821C(v)) /* 2 REG_PCIE_HRPWM1_V1_8821C */ #define BIT_SHIFT_PCIE_HRPWM_8821C 0 #define BIT_MASK_PCIE_HRPWM_8821C 0xff -#define BIT_PCIE_HRPWM_8821C(x) (((x) & BIT_MASK_PCIE_HRPWM_8821C) << BIT_SHIFT_PCIE_HRPWM_8821C) -#define BIT_GET_PCIE_HRPWM_8821C(x) (((x) >> BIT_SHIFT_PCIE_HRPWM_8821C) & BIT_MASK_PCIE_HRPWM_8821C) - - +#define BIT_PCIE_HRPWM_8821C(x) \ + (((x) & BIT_MASK_PCIE_HRPWM_8821C) << BIT_SHIFT_PCIE_HRPWM_8821C) +#define BITS_PCIE_HRPWM_8821C \ + (BIT_MASK_PCIE_HRPWM_8821C << BIT_SHIFT_PCIE_HRPWM_8821C) +#define BIT_CLEAR_PCIE_HRPWM_8821C(x) ((x) & (~BITS_PCIE_HRPWM_8821C)) +#define BIT_GET_PCIE_HRPWM_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM_8821C) & BIT_MASK_PCIE_HRPWM_8821C) +#define BIT_SET_PCIE_HRPWM_8821C(x, v) \ + (BIT_CLEAR_PCIE_HRPWM_8821C(x) | BIT_PCIE_HRPWM_8821C(v)) /* 2 REG_PCIE_HCPWM1_V1_8821C */ #define BIT_SHIFT_PCIE_HCPWM_8821C 0 #define BIT_MASK_PCIE_HCPWM_8821C 0xff -#define BIT_PCIE_HCPWM_8821C(x) (((x) & BIT_MASK_PCIE_HCPWM_8821C) << BIT_SHIFT_PCIE_HCPWM_8821C) -#define BIT_GET_PCIE_HCPWM_8821C(x) (((x) >> BIT_SHIFT_PCIE_HCPWM_8821C) & BIT_MASK_PCIE_HCPWM_8821C) - - +#define BIT_PCIE_HCPWM_8821C(x) \ + (((x) & BIT_MASK_PCIE_HCPWM_8821C) << BIT_SHIFT_PCIE_HCPWM_8821C) +#define BITS_PCIE_HCPWM_8821C \ + (BIT_MASK_PCIE_HCPWM_8821C << BIT_SHIFT_PCIE_HCPWM_8821C) +#define BIT_CLEAR_PCIE_HCPWM_8821C(x) ((x) & (~BITS_PCIE_HCPWM_8821C)) +#define BIT_GET_PCIE_HCPWM_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM_8821C) & BIT_MASK_PCIE_HCPWM_8821C) +#define BIT_SET_PCIE_HCPWM_8821C(x, v) \ + (BIT_CLEAR_PCIE_HCPWM_8821C(x) | BIT_PCIE_HCPWM_8821C(v)) /* 2 REG_PCIE_CTRL2_8821C */ #define BIT_DIS_TXDMA_PRE_8821C BIT(7) @@ -5042,9 +8191,15 @@ #define BIT_SHIFT_HPS_CLKR_PCIE_8821C 4 #define BIT_MASK_HPS_CLKR_PCIE_8821C 0x3 -#define BIT_HPS_CLKR_PCIE_8821C(x) (((x) & BIT_MASK_HPS_CLKR_PCIE_8821C) << BIT_SHIFT_HPS_CLKR_PCIE_8821C) -#define BIT_GET_HPS_CLKR_PCIE_8821C(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8821C) & BIT_MASK_HPS_CLKR_PCIE_8821C) - +#define BIT_HPS_CLKR_PCIE_8821C(x) \ + (((x) & BIT_MASK_HPS_CLKR_PCIE_8821C) << BIT_SHIFT_HPS_CLKR_PCIE_8821C) +#define BITS_HPS_CLKR_PCIE_8821C \ + (BIT_MASK_HPS_CLKR_PCIE_8821C << BIT_SHIFT_HPS_CLKR_PCIE_8821C) +#define BIT_CLEAR_HPS_CLKR_PCIE_8821C(x) ((x) & (~BITS_HPS_CLKR_PCIE_8821C)) +#define BIT_GET_HPS_CLKR_PCIE_8821C(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8821C) & BIT_MASK_HPS_CLKR_PCIE_8821C) +#define BIT_SET_HPS_CLKR_PCIE_8821C(x, v) \ + (BIT_CLEAR_HPS_CLKR_PCIE_8821C(x) | BIT_HPS_CLKR_PCIE_8821C(v)) #define BIT_PCIE_INT_8821C BIT(3) #define BIT_TXFLAG_EXIT_L1_EN_8821C BIT(2) @@ -5055,55 +8210,88 @@ #define BIT_SHIFT_PCIE_HRPWM2_8821C 0 #define BIT_MASK_PCIE_HRPWM2_8821C 0xffff -#define BIT_PCIE_HRPWM2_8821C(x) (((x) & BIT_MASK_PCIE_HRPWM2_8821C) << BIT_SHIFT_PCIE_HRPWM2_8821C) -#define BIT_GET_PCIE_HRPWM2_8821C(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2_8821C) & BIT_MASK_PCIE_HRPWM2_8821C) - - +#define BIT_PCIE_HRPWM2_8821C(x) \ + (((x) & BIT_MASK_PCIE_HRPWM2_8821C) << BIT_SHIFT_PCIE_HRPWM2_8821C) +#define BITS_PCIE_HRPWM2_8821C \ + (BIT_MASK_PCIE_HRPWM2_8821C << BIT_SHIFT_PCIE_HRPWM2_8821C) +#define BIT_CLEAR_PCIE_HRPWM2_8821C(x) ((x) & (~BITS_PCIE_HRPWM2_8821C)) +#define BIT_GET_PCIE_HRPWM2_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM2_8821C) & BIT_MASK_PCIE_HRPWM2_8821C) +#define BIT_SET_PCIE_HRPWM2_8821C(x, v) \ + (BIT_CLEAR_PCIE_HRPWM2_8821C(x) | BIT_PCIE_HRPWM2_8821C(v)) /* 2 REG_PCIE_HCPWM2_V1_8821C */ #define BIT_SHIFT_PCIE_HCPWM2_8821C 0 #define BIT_MASK_PCIE_HCPWM2_8821C 0xffff -#define BIT_PCIE_HCPWM2_8821C(x) (((x) & BIT_MASK_PCIE_HCPWM2_8821C) << BIT_SHIFT_PCIE_HCPWM2_8821C) -#define BIT_GET_PCIE_HCPWM2_8821C(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2_8821C) & BIT_MASK_PCIE_HCPWM2_8821C) - - +#define BIT_PCIE_HCPWM2_8821C(x) \ + (((x) & BIT_MASK_PCIE_HCPWM2_8821C) << BIT_SHIFT_PCIE_HCPWM2_8821C) +#define BITS_PCIE_HCPWM2_8821C \ + (BIT_MASK_PCIE_HCPWM2_8821C << BIT_SHIFT_PCIE_HCPWM2_8821C) +#define BIT_CLEAR_PCIE_HCPWM2_8821C(x) ((x) & (~BITS_PCIE_HCPWM2_8821C)) +#define BIT_GET_PCIE_HCPWM2_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM2_8821C) & BIT_MASK_PCIE_HCPWM2_8821C) +#define BIT_SET_PCIE_HCPWM2_8821C(x, v) \ + (BIT_CLEAR_PCIE_HCPWM2_8821C(x) | BIT_PCIE_HCPWM2_8821C(v)) /* 2 REG_PCIE_H2C_MSG_V1_8821C */ #define BIT_SHIFT_DRV2FW_INFO_8821C 0 #define BIT_MASK_DRV2FW_INFO_8821C 0xffffffffL -#define BIT_DRV2FW_INFO_8821C(x) (((x) & BIT_MASK_DRV2FW_INFO_8821C) << BIT_SHIFT_DRV2FW_INFO_8821C) -#define BIT_GET_DRV2FW_INFO_8821C(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8821C) & BIT_MASK_DRV2FW_INFO_8821C) - - +#define BIT_DRV2FW_INFO_8821C(x) \ + (((x) & BIT_MASK_DRV2FW_INFO_8821C) << BIT_SHIFT_DRV2FW_INFO_8821C) +#define BITS_DRV2FW_INFO_8821C \ + (BIT_MASK_DRV2FW_INFO_8821C << BIT_SHIFT_DRV2FW_INFO_8821C) +#define BIT_CLEAR_DRV2FW_INFO_8821C(x) ((x) & (~BITS_DRV2FW_INFO_8821C)) +#define BIT_GET_DRV2FW_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_DRV2FW_INFO_8821C) & BIT_MASK_DRV2FW_INFO_8821C) +#define BIT_SET_DRV2FW_INFO_8821C(x, v) \ + (BIT_CLEAR_DRV2FW_INFO_8821C(x) | BIT_DRV2FW_INFO_8821C(v)) /* 2 REG_PCIE_C2H_MSG_V1_8821C */ #define BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C 0 #define BIT_MASK_HCI_PCIE_C2H_MSG_8821C 0xffffffffL -#define BIT_HCI_PCIE_C2H_MSG_8821C(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C) << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) -#define BIT_GET_HCI_PCIE_C2H_MSG_8821C(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C) - - +#define BIT_HCI_PCIE_C2H_MSG_8821C(x) \ + (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C) \ + << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) +#define BITS_HCI_PCIE_C2H_MSG_8821C \ + (BIT_MASK_HCI_PCIE_C2H_MSG_8821C << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) +#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8821C(x) \ + ((x) & (~BITS_HCI_PCIE_C2H_MSG_8821C)) +#define BIT_GET_HCI_PCIE_C2H_MSG_8821C(x) \ + (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) & \ + BIT_MASK_HCI_PCIE_C2H_MSG_8821C) +#define BIT_SET_HCI_PCIE_C2H_MSG_8821C(x, v) \ + (BIT_CLEAR_HCI_PCIE_C2H_MSG_8821C(x) | BIT_HCI_PCIE_C2H_MSG_8821C(v)) /* 2 REG_DBI_WDATA_V1_8821C */ #define BIT_SHIFT_DBI_WDATA_8821C 0 #define BIT_MASK_DBI_WDATA_8821C 0xffffffffL -#define BIT_DBI_WDATA_8821C(x) (((x) & BIT_MASK_DBI_WDATA_8821C) << BIT_SHIFT_DBI_WDATA_8821C) -#define BIT_GET_DBI_WDATA_8821C(x) (((x) >> BIT_SHIFT_DBI_WDATA_8821C) & BIT_MASK_DBI_WDATA_8821C) - - +#define BIT_DBI_WDATA_8821C(x) \ + (((x) & BIT_MASK_DBI_WDATA_8821C) << BIT_SHIFT_DBI_WDATA_8821C) +#define BITS_DBI_WDATA_8821C \ + (BIT_MASK_DBI_WDATA_8821C << BIT_SHIFT_DBI_WDATA_8821C) +#define BIT_CLEAR_DBI_WDATA_8821C(x) ((x) & (~BITS_DBI_WDATA_8821C)) +#define BIT_GET_DBI_WDATA_8821C(x) \ + (((x) >> BIT_SHIFT_DBI_WDATA_8821C) & BIT_MASK_DBI_WDATA_8821C) +#define BIT_SET_DBI_WDATA_8821C(x, v) \ + (BIT_CLEAR_DBI_WDATA_8821C(x) | BIT_DBI_WDATA_8821C(v)) /* 2 REG_DBI_RDATA_V1_8821C */ #define BIT_SHIFT_DBI_RDATA_8821C 0 #define BIT_MASK_DBI_RDATA_8821C 0xffffffffL -#define BIT_DBI_RDATA_8821C(x) (((x) & BIT_MASK_DBI_RDATA_8821C) << BIT_SHIFT_DBI_RDATA_8821C) -#define BIT_GET_DBI_RDATA_8821C(x) (((x) >> BIT_SHIFT_DBI_RDATA_8821C) & BIT_MASK_DBI_RDATA_8821C) - - +#define BIT_DBI_RDATA_8821C(x) \ + (((x) & BIT_MASK_DBI_RDATA_8821C) << BIT_SHIFT_DBI_RDATA_8821C) +#define BITS_DBI_RDATA_8821C \ + (BIT_MASK_DBI_RDATA_8821C << BIT_SHIFT_DBI_RDATA_8821C) +#define BIT_CLEAR_DBI_RDATA_8821C(x) ((x) & (~BITS_DBI_RDATA_8821C)) +#define BIT_GET_DBI_RDATA_8821C(x) \ + (((x) >> BIT_SHIFT_DBI_RDATA_8821C) & BIT_MASK_DBI_RDATA_8821C) +#define BIT_SET_DBI_RDATA_8821C(x, v) \ + (BIT_CLEAR_DBI_RDATA_8821C(x) | BIT_DBI_RDATA_8821C(v)) /* 2 REG_DBI_FLAG_V1_8821C */ #define BIT_EN_STUCK_DBG_8821C BIT(26) @@ -5114,48 +8302,84 @@ #define BIT_SHIFT_DBI_WREN_8821C 12 #define BIT_MASK_DBI_WREN_8821C 0xf -#define BIT_DBI_WREN_8821C(x) (((x) & BIT_MASK_DBI_WREN_8821C) << BIT_SHIFT_DBI_WREN_8821C) -#define BIT_GET_DBI_WREN_8821C(x) (((x) >> BIT_SHIFT_DBI_WREN_8821C) & BIT_MASK_DBI_WREN_8821C) - - +#define BIT_DBI_WREN_8821C(x) \ + (((x) & BIT_MASK_DBI_WREN_8821C) << BIT_SHIFT_DBI_WREN_8821C) +#define BITS_DBI_WREN_8821C \ + (BIT_MASK_DBI_WREN_8821C << BIT_SHIFT_DBI_WREN_8821C) +#define BIT_CLEAR_DBI_WREN_8821C(x) ((x) & (~BITS_DBI_WREN_8821C)) +#define BIT_GET_DBI_WREN_8821C(x) \ + (((x) >> BIT_SHIFT_DBI_WREN_8821C) & BIT_MASK_DBI_WREN_8821C) +#define BIT_SET_DBI_WREN_8821C(x, v) \ + (BIT_CLEAR_DBI_WREN_8821C(x) | BIT_DBI_WREN_8821C(v)) #define BIT_SHIFT_DBI_ADDR_8821C 0 #define BIT_MASK_DBI_ADDR_8821C 0xfff -#define BIT_DBI_ADDR_8821C(x) (((x) & BIT_MASK_DBI_ADDR_8821C) << BIT_SHIFT_DBI_ADDR_8821C) -#define BIT_GET_DBI_ADDR_8821C(x) (((x) >> BIT_SHIFT_DBI_ADDR_8821C) & BIT_MASK_DBI_ADDR_8821C) - - +#define BIT_DBI_ADDR_8821C(x) \ + (((x) & BIT_MASK_DBI_ADDR_8821C) << BIT_SHIFT_DBI_ADDR_8821C) +#define BITS_DBI_ADDR_8821C \ + (BIT_MASK_DBI_ADDR_8821C << BIT_SHIFT_DBI_ADDR_8821C) +#define BIT_CLEAR_DBI_ADDR_8821C(x) ((x) & (~BITS_DBI_ADDR_8821C)) +#define BIT_GET_DBI_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_DBI_ADDR_8821C) & BIT_MASK_DBI_ADDR_8821C) +#define BIT_SET_DBI_ADDR_8821C(x, v) \ + (BIT_CLEAR_DBI_ADDR_8821C(x) | BIT_DBI_ADDR_8821C(v)) /* 2 REG_MDIO_V1_8821C */ #define BIT_SHIFT_MDIO_RDATA_8821C 16 #define BIT_MASK_MDIO_RDATA_8821C 0xffff -#define BIT_MDIO_RDATA_8821C(x) (((x) & BIT_MASK_MDIO_RDATA_8821C) << BIT_SHIFT_MDIO_RDATA_8821C) -#define BIT_GET_MDIO_RDATA_8821C(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8821C) & BIT_MASK_MDIO_RDATA_8821C) - - +#define BIT_MDIO_RDATA_8821C(x) \ + (((x) & BIT_MASK_MDIO_RDATA_8821C) << BIT_SHIFT_MDIO_RDATA_8821C) +#define BITS_MDIO_RDATA_8821C \ + (BIT_MASK_MDIO_RDATA_8821C << BIT_SHIFT_MDIO_RDATA_8821C) +#define BIT_CLEAR_MDIO_RDATA_8821C(x) ((x) & (~BITS_MDIO_RDATA_8821C)) +#define BIT_GET_MDIO_RDATA_8821C(x) \ + (((x) >> BIT_SHIFT_MDIO_RDATA_8821C) & BIT_MASK_MDIO_RDATA_8821C) +#define BIT_SET_MDIO_RDATA_8821C(x, v) \ + (BIT_CLEAR_MDIO_RDATA_8821C(x) | BIT_MDIO_RDATA_8821C(v)) #define BIT_SHIFT_MDIO_WDATA_8821C 0 #define BIT_MASK_MDIO_WDATA_8821C 0xffff -#define BIT_MDIO_WDATA_8821C(x) (((x) & BIT_MASK_MDIO_WDATA_8821C) << BIT_SHIFT_MDIO_WDATA_8821C) -#define BIT_GET_MDIO_WDATA_8821C(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8821C) & BIT_MASK_MDIO_WDATA_8821C) - - +#define BIT_MDIO_WDATA_8821C(x) \ + (((x) & BIT_MASK_MDIO_WDATA_8821C) << BIT_SHIFT_MDIO_WDATA_8821C) +#define BITS_MDIO_WDATA_8821C \ + (BIT_MASK_MDIO_WDATA_8821C << BIT_SHIFT_MDIO_WDATA_8821C) +#define BIT_CLEAR_MDIO_WDATA_8821C(x) ((x) & (~BITS_MDIO_WDATA_8821C)) +#define BIT_GET_MDIO_WDATA_8821C(x) \ + (((x) >> BIT_SHIFT_MDIO_WDATA_8821C) & BIT_MASK_MDIO_WDATA_8821C) +#define BIT_SET_MDIO_WDATA_8821C(x, v) \ + (BIT_CLEAR_MDIO_WDATA_8821C(x) | BIT_MDIO_WDATA_8821C(v)) /* 2 REG_PCIE_MIX_CFG_8821C */ #define BIT_SHIFT_MDIO_PHY_ADDR_8821C 24 #define BIT_MASK_MDIO_PHY_ADDR_8821C 0x1f -#define BIT_MDIO_PHY_ADDR_8821C(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8821C) << BIT_SHIFT_MDIO_PHY_ADDR_8821C) -#define BIT_GET_MDIO_PHY_ADDR_8821C(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8821C) & BIT_MASK_MDIO_PHY_ADDR_8821C) - - +#define BIT_MDIO_PHY_ADDR_8821C(x) \ + (((x) & BIT_MASK_MDIO_PHY_ADDR_8821C) << BIT_SHIFT_MDIO_PHY_ADDR_8821C) +#define BITS_MDIO_PHY_ADDR_8821C \ + (BIT_MASK_MDIO_PHY_ADDR_8821C << BIT_SHIFT_MDIO_PHY_ADDR_8821C) +#define BIT_CLEAR_MDIO_PHY_ADDR_8821C(x) ((x) & (~BITS_MDIO_PHY_ADDR_8821C)) +#define BIT_GET_MDIO_PHY_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8821C) & BIT_MASK_MDIO_PHY_ADDR_8821C) +#define BIT_SET_MDIO_PHY_ADDR_8821C(x, v) \ + (BIT_CLEAR_MDIO_PHY_ADDR_8821C(x) | BIT_MDIO_PHY_ADDR_8821C(v)) #define BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C 10 #define BIT_MASK_WATCH_DOG_RECORD_V1_8821C 0x3fff -#define BIT_WATCH_DOG_RECORD_V1_8821C(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) -#define BIT_GET_WATCH_DOG_RECORD_V1_8821C(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C) - +#define BIT_WATCH_DOG_RECORD_V1_8821C(x) \ + (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C) \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) +#define BITS_WATCH_DOG_RECORD_V1_8821C \ + (BIT_MASK_WATCH_DOG_RECORD_V1_8821C \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8821C(x) \ + ((x) & (~BITS_WATCH_DOG_RECORD_V1_8821C)) +#define BIT_GET_WATCH_DOG_RECORD_V1_8821C(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) & \ + BIT_MASK_WATCH_DOG_RECORD_V1_8821C) +#define BIT_SET_WATCH_DOG_RECORD_V1_8821C(x, v) \ + (BIT_CLEAR_WATCH_DOG_RECORD_V1_8821C(x) | \ + BIT_WATCH_DOG_RECORD_V1_8821C(v)) #define BIT_R_IO_TIMEOUT_FLAG_V1_8821C BIT(9) #define BIT_EN_WATCH_DOG_8821C BIT(8) @@ -5165,34 +8389,66 @@ #define BIT_SHIFT_MDIO_REG_ADDR_V1_8821C 0 #define BIT_MASK_MDIO_REG_ADDR_V1_8821C 0x1f -#define BIT_MDIO_REG_ADDR_V1_8821C(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8821C) << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) -#define BIT_GET_MDIO_REG_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) & BIT_MASK_MDIO_REG_ADDR_V1_8821C) - - +#define BIT_MDIO_REG_ADDR_V1_8821C(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8821C) \ + << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) +#define BITS_MDIO_REG_ADDR_V1_8821C \ + (BIT_MASK_MDIO_REG_ADDR_V1_8821C << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) +#define BIT_CLEAR_MDIO_REG_ADDR_V1_8821C(x) \ + ((x) & (~BITS_MDIO_REG_ADDR_V1_8821C)) +#define BIT_GET_MDIO_REG_ADDR_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) & \ + BIT_MASK_MDIO_REG_ADDR_V1_8821C) +#define BIT_SET_MDIO_REG_ADDR_V1_8821C(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR_V1_8821C(x) | BIT_MDIO_REG_ADDR_V1_8821C(v)) /* 2 REG_HCI_MIX_CFG_8821C */ #define BIT_HOST_GEN2_SUPPORT_8821C BIT(20) #define BIT_SHIFT_TXDMA_ERR_FLAG_8821C 16 #define BIT_MASK_TXDMA_ERR_FLAG_8821C 0xf -#define BIT_TXDMA_ERR_FLAG_8821C(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8821C) << BIT_SHIFT_TXDMA_ERR_FLAG_8821C) -#define BIT_GET_TXDMA_ERR_FLAG_8821C(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8821C) & BIT_MASK_TXDMA_ERR_FLAG_8821C) - - +#define BIT_TXDMA_ERR_FLAG_8821C(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG_8821C) \ + << BIT_SHIFT_TXDMA_ERR_FLAG_8821C) +#define BITS_TXDMA_ERR_FLAG_8821C \ + (BIT_MASK_TXDMA_ERR_FLAG_8821C << BIT_SHIFT_TXDMA_ERR_FLAG_8821C) +#define BIT_CLEAR_TXDMA_ERR_FLAG_8821C(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8821C)) +#define BIT_GET_TXDMA_ERR_FLAG_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8821C) & \ + BIT_MASK_TXDMA_ERR_FLAG_8821C) +#define BIT_SET_TXDMA_ERR_FLAG_8821C(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG_8821C(x) | BIT_TXDMA_ERR_FLAG_8821C(v)) #define BIT_SHIFT_EARLY_MODE_SEL_8821C 12 #define BIT_MASK_EARLY_MODE_SEL_8821C 0xf -#define BIT_EARLY_MODE_SEL_8821C(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8821C) << BIT_SHIFT_EARLY_MODE_SEL_8821C) -#define BIT_GET_EARLY_MODE_SEL_8821C(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8821C) & BIT_MASK_EARLY_MODE_SEL_8821C) - +#define BIT_EARLY_MODE_SEL_8821C(x) \ + (((x) & BIT_MASK_EARLY_MODE_SEL_8821C) \ + << BIT_SHIFT_EARLY_MODE_SEL_8821C) +#define BITS_EARLY_MODE_SEL_8821C \ + (BIT_MASK_EARLY_MODE_SEL_8821C << BIT_SHIFT_EARLY_MODE_SEL_8821C) +#define BIT_CLEAR_EARLY_MODE_SEL_8821C(x) ((x) & (~BITS_EARLY_MODE_SEL_8821C)) +#define BIT_GET_EARLY_MODE_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8821C) & \ + BIT_MASK_EARLY_MODE_SEL_8821C) +#define BIT_SET_EARLY_MODE_SEL_8821C(x, v) \ + (BIT_CLEAR_EARLY_MODE_SEL_8821C(x) | BIT_EARLY_MODE_SEL_8821C(v)) #define BIT_EPHY_RX50_EN_8821C BIT(11) #define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C 8 #define BIT_MASK_MSI_TIMEOUT_ID_V1_8821C 0x7 -#define BIT_MSI_TIMEOUT_ID_V1_8821C(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) -#define BIT_GET_MSI_TIMEOUT_ID_V1_8821C(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) - +#define BIT_MSI_TIMEOUT_ID_V1_8821C(x) \ + (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) \ + << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) +#define BITS_MSI_TIMEOUT_ID_V1_8821C \ + (BIT_MASK_MSI_TIMEOUT_ID_V1_8821C << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8821C(x) \ + ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8821C)) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) & \ + BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) +#define BIT_SET_MSI_TIMEOUT_ID_V1_8821C(x, v) \ + (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8821C(x) | BIT_MSI_TIMEOUT_ID_V1_8821C(v)) #define BIT_RADDR_RD_8821C BIT(7) #define BIT_EN_MUL_TAG_8821C BIT(6) @@ -5207,41 +8463,77 @@ #define BIT_SHIFT_STC_INT_FLAG_8821C 16 #define BIT_MASK_STC_INT_FLAG_8821C 0xff -#define BIT_STC_INT_FLAG_8821C(x) (((x) & BIT_MASK_STC_INT_FLAG_8821C) << BIT_SHIFT_STC_INT_FLAG_8821C) -#define BIT_GET_STC_INT_FLAG_8821C(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8821C) & BIT_MASK_STC_INT_FLAG_8821C) - - +#define BIT_STC_INT_FLAG_8821C(x) \ + (((x) & BIT_MASK_STC_INT_FLAG_8821C) << BIT_SHIFT_STC_INT_FLAG_8821C) +#define BITS_STC_INT_FLAG_8821C \ + (BIT_MASK_STC_INT_FLAG_8821C << BIT_SHIFT_STC_INT_FLAG_8821C) +#define BIT_CLEAR_STC_INT_FLAG_8821C(x) ((x) & (~BITS_STC_INT_FLAG_8821C)) +#define BIT_GET_STC_INT_FLAG_8821C(x) \ + (((x) >> BIT_SHIFT_STC_INT_FLAG_8821C) & BIT_MASK_STC_INT_FLAG_8821C) +#define BIT_SET_STC_INT_FLAG_8821C(x, v) \ + (BIT_CLEAR_STC_INT_FLAG_8821C(x) | BIT_STC_INT_FLAG_8821C(v)) #define BIT_SHIFT_STC_INT_IDX_8821C 8 #define BIT_MASK_STC_INT_IDX_8821C 0x7 -#define BIT_STC_INT_IDX_8821C(x) (((x) & BIT_MASK_STC_INT_IDX_8821C) << BIT_SHIFT_STC_INT_IDX_8821C) -#define BIT_GET_STC_INT_IDX_8821C(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8821C) & BIT_MASK_STC_INT_IDX_8821C) - - +#define BIT_STC_INT_IDX_8821C(x) \ + (((x) & BIT_MASK_STC_INT_IDX_8821C) << BIT_SHIFT_STC_INT_IDX_8821C) +#define BITS_STC_INT_IDX_8821C \ + (BIT_MASK_STC_INT_IDX_8821C << BIT_SHIFT_STC_INT_IDX_8821C) +#define BIT_CLEAR_STC_INT_IDX_8821C(x) ((x) & (~BITS_STC_INT_IDX_8821C)) +#define BIT_GET_STC_INT_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_STC_INT_IDX_8821C) & BIT_MASK_STC_INT_IDX_8821C) +#define BIT_SET_STC_INT_IDX_8821C(x, v) \ + (BIT_CLEAR_STC_INT_IDX_8821C(x) | BIT_STC_INT_IDX_8821C(v)) #define BIT_SHIFT_STC_INT_REALTIME_CS_8821C 0 #define BIT_MASK_STC_INT_REALTIME_CS_8821C 0x3f -#define BIT_STC_INT_REALTIME_CS_8821C(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8821C) << BIT_SHIFT_STC_INT_REALTIME_CS_8821C) -#define BIT_GET_STC_INT_REALTIME_CS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8821C) & BIT_MASK_STC_INT_REALTIME_CS_8821C) - - +#define BIT_STC_INT_REALTIME_CS_8821C(x) \ + (((x) & BIT_MASK_STC_INT_REALTIME_CS_8821C) \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8821C) +#define BITS_STC_INT_REALTIME_CS_8821C \ + (BIT_MASK_STC_INT_REALTIME_CS_8821C \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8821C) +#define BIT_CLEAR_STC_INT_REALTIME_CS_8821C(x) \ + ((x) & (~BITS_STC_INT_REALTIME_CS_8821C)) +#define BIT_GET_STC_INT_REALTIME_CS_8821C(x) \ + (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8821C) & \ + BIT_MASK_STC_INT_REALTIME_CS_8821C) +#define BIT_SET_STC_INT_REALTIME_CS_8821C(x, v) \ + (BIT_CLEAR_STC_INT_REALTIME_CS_8821C(x) | \ + BIT_STC_INT_REALTIME_CS_8821C(v)) /* 2 REG_ST_INT_CFG_8821C(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */ #define BIT_STC_INT_GRP_EN_8821C BIT(31) #define BIT_SHIFT_STC_INT_EXPECT_LS_8821C 8 #define BIT_MASK_STC_INT_EXPECT_LS_8821C 0x3f -#define BIT_STC_INT_EXPECT_LS_8821C(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8821C) << BIT_SHIFT_STC_INT_EXPECT_LS_8821C) -#define BIT_GET_STC_INT_EXPECT_LS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8821C) & BIT_MASK_STC_INT_EXPECT_LS_8821C) - - +#define BIT_STC_INT_EXPECT_LS_8821C(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_LS_8821C) \ + << BIT_SHIFT_STC_INT_EXPECT_LS_8821C) +#define BITS_STC_INT_EXPECT_LS_8821C \ + (BIT_MASK_STC_INT_EXPECT_LS_8821C << BIT_SHIFT_STC_INT_EXPECT_LS_8821C) +#define BIT_CLEAR_STC_INT_EXPECT_LS_8821C(x) \ + ((x) & (~BITS_STC_INT_EXPECT_LS_8821C)) +#define BIT_GET_STC_INT_EXPECT_LS_8821C(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8821C) & \ + BIT_MASK_STC_INT_EXPECT_LS_8821C) +#define BIT_SET_STC_INT_EXPECT_LS_8821C(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_LS_8821C(x) | BIT_STC_INT_EXPECT_LS_8821C(v)) #define BIT_SHIFT_STC_INT_EXPECT_CS_8821C 0 #define BIT_MASK_STC_INT_EXPECT_CS_8821C 0x3f -#define BIT_STC_INT_EXPECT_CS_8821C(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8821C) << BIT_SHIFT_STC_INT_EXPECT_CS_8821C) -#define BIT_GET_STC_INT_EXPECT_CS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8821C) & BIT_MASK_STC_INT_EXPECT_CS_8821C) - - +#define BIT_STC_INT_EXPECT_CS_8821C(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_CS_8821C) \ + << BIT_SHIFT_STC_INT_EXPECT_CS_8821C) +#define BITS_STC_INT_EXPECT_CS_8821C \ + (BIT_MASK_STC_INT_EXPECT_CS_8821C << BIT_SHIFT_STC_INT_EXPECT_CS_8821C) +#define BIT_CLEAR_STC_INT_EXPECT_CS_8821C(x) \ + ((x) & (~BITS_STC_INT_EXPECT_CS_8821C)) +#define BIT_GET_STC_INT_EXPECT_CS_8821C(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8821C) & \ + BIT_MASK_STC_INT_EXPECT_CS_8821C) +#define BIT_SET_STC_INT_EXPECT_CS_8821C(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_CS_8821C(x) | BIT_STC_INT_EXPECT_CS_8821C(v)) /* 2 REG_CMU_DLY_CTRL_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */ #define BIT_CMU_DLY_EN_8821C BIT(31) @@ -5249,282 +8541,529 @@ #define BIT_SHIFT_CMU_DLY_PRE_DIV_8821C 0 #define BIT_MASK_CMU_DLY_PRE_DIV_8821C 0xff -#define BIT_CMU_DLY_PRE_DIV_8821C(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8821C) << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) -#define BIT_GET_CMU_DLY_PRE_DIV_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) & BIT_MASK_CMU_DLY_PRE_DIV_8821C) - - +#define BIT_CMU_DLY_PRE_DIV_8821C(x) \ + (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8821C) \ + << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) +#define BITS_CMU_DLY_PRE_DIV_8821C \ + (BIT_MASK_CMU_DLY_PRE_DIV_8821C << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) +#define BIT_CLEAR_CMU_DLY_PRE_DIV_8821C(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8821C)) +#define BIT_GET_CMU_DLY_PRE_DIV_8821C(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) & \ + BIT_MASK_CMU_DLY_PRE_DIV_8821C) +#define BIT_SET_CMU_DLY_PRE_DIV_8821C(x, v) \ + (BIT_CLEAR_CMU_DLY_PRE_DIV_8821C(x) | BIT_CMU_DLY_PRE_DIV_8821C(v)) /* 2 REG_CMU_DLY_CFG_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ #define BIT_SHIFT_CMU_DLY_LTR_A2I_8821C 24 #define BIT_MASK_CMU_DLY_LTR_A2I_8821C 0xff -#define BIT_CMU_DLY_LTR_A2I_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8821C) << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) -#define BIT_GET_CMU_DLY_LTR_A2I_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) & BIT_MASK_CMU_DLY_LTR_A2I_8821C) - - +#define BIT_CMU_DLY_LTR_A2I_8821C(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8821C) \ + << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) +#define BITS_CMU_DLY_LTR_A2I_8821C \ + (BIT_MASK_CMU_DLY_LTR_A2I_8821C << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) +#define BIT_CLEAR_CMU_DLY_LTR_A2I_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8821C)) +#define BIT_GET_CMU_DLY_LTR_A2I_8821C(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) & \ + BIT_MASK_CMU_DLY_LTR_A2I_8821C) +#define BIT_SET_CMU_DLY_LTR_A2I_8821C(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_A2I_8821C(x) | BIT_CMU_DLY_LTR_A2I_8821C(v)) #define BIT_SHIFT_CMU_DLY_LTR_I2A_8821C 16 #define BIT_MASK_CMU_DLY_LTR_I2A_8821C 0xff -#define BIT_CMU_DLY_LTR_I2A_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8821C) << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) -#define BIT_GET_CMU_DLY_LTR_I2A_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) & BIT_MASK_CMU_DLY_LTR_I2A_8821C) - - +#define BIT_CMU_DLY_LTR_I2A_8821C(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8821C) \ + << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) +#define BITS_CMU_DLY_LTR_I2A_8821C \ + (BIT_MASK_CMU_DLY_LTR_I2A_8821C << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) +#define BIT_CLEAR_CMU_DLY_LTR_I2A_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8821C)) +#define BIT_GET_CMU_DLY_LTR_I2A_8821C(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) & \ + BIT_MASK_CMU_DLY_LTR_I2A_8821C) +#define BIT_SET_CMU_DLY_LTR_I2A_8821C(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_I2A_8821C(x) | BIT_CMU_DLY_LTR_I2A_8821C(v)) #define BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C 8 #define BIT_MASK_CMU_DLY_LTR_IDLE_8821C 0xff -#define BIT_CMU_DLY_LTR_IDLE_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) -#define BIT_GET_CMU_DLY_LTR_IDLE_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C) - - +#define BIT_CMU_DLY_LTR_IDLE_8821C(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C) \ + << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) +#define BITS_CMU_DLY_LTR_IDLE_8821C \ + (BIT_MASK_CMU_DLY_LTR_IDLE_8821C << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) +#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8821C(x) \ + ((x) & (~BITS_CMU_DLY_LTR_IDLE_8821C)) +#define BIT_GET_CMU_DLY_LTR_IDLE_8821C(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) & \ + BIT_MASK_CMU_DLY_LTR_IDLE_8821C) +#define BIT_SET_CMU_DLY_LTR_IDLE_8821C(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_IDLE_8821C(x) | BIT_CMU_DLY_LTR_IDLE_8821C(v)) #define BIT_SHIFT_CMU_DLY_LTR_ACT_8821C 0 #define BIT_MASK_CMU_DLY_LTR_ACT_8821C 0xff -#define BIT_CMU_DLY_LTR_ACT_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8821C) << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) -#define BIT_GET_CMU_DLY_LTR_ACT_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) & BIT_MASK_CMU_DLY_LTR_ACT_8821C) - - +#define BIT_CMU_DLY_LTR_ACT_8821C(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8821C) \ + << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) +#define BITS_CMU_DLY_LTR_ACT_8821C \ + (BIT_MASK_CMU_DLY_LTR_ACT_8821C << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) +#define BIT_CLEAR_CMU_DLY_LTR_ACT_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8821C)) +#define BIT_GET_CMU_DLY_LTR_ACT_8821C(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) & \ + BIT_MASK_CMU_DLY_LTR_ACT_8821C) +#define BIT_SET_CMU_DLY_LTR_ACT_8821C(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_ACT_8821C(x) | BIT_CMU_DLY_LTR_ACT_8821C(v)) /* 2 REG_H2CQ_TXBD_DESA_8821C */ #define BIT_SHIFT_H2CQ_TXBD_DESA_8821C 0 #define BIT_MASK_H2CQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_H2CQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8821C) << BIT_SHIFT_H2CQ_TXBD_DESA_8821C) -#define BIT_GET_H2CQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8821C) & BIT_MASK_H2CQ_TXBD_DESA_8821C) - - +#define BIT_H2CQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_8821C) \ + << BIT_SHIFT_H2CQ_TXBD_DESA_8821C) +#define BITS_H2CQ_TXBD_DESA_8821C \ + (BIT_MASK_H2CQ_TXBD_DESA_8821C << BIT_SHIFT_H2CQ_TXBD_DESA_8821C) +#define BIT_CLEAR_H2CQ_TXBD_DESA_8821C(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8821C)) +#define BIT_GET_H2CQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8821C) & \ + BIT_MASK_H2CQ_TXBD_DESA_8821C) +#define BIT_SET_H2CQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_8821C(x) | BIT_H2CQ_TXBD_DESA_8821C(v)) /* 2 REG_H2CQ_TXBD_NUM_8821C */ #define BIT_PCIE_H2CQ_FLAG_8821C BIT(14) #define BIT_SHIFT_H2CQ_DESC_MODE_8821C 12 #define BIT_MASK_H2CQ_DESC_MODE_8821C 0x3 -#define BIT_H2CQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8821C) << BIT_SHIFT_H2CQ_DESC_MODE_8821C) -#define BIT_GET_H2CQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8821C) & BIT_MASK_H2CQ_DESC_MODE_8821C) - - +#define BIT_H2CQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_H2CQ_DESC_MODE_8821C) \ + << BIT_SHIFT_H2CQ_DESC_MODE_8821C) +#define BITS_H2CQ_DESC_MODE_8821C \ + (BIT_MASK_H2CQ_DESC_MODE_8821C << BIT_SHIFT_H2CQ_DESC_MODE_8821C) +#define BIT_CLEAR_H2CQ_DESC_MODE_8821C(x) ((x) & (~BITS_H2CQ_DESC_MODE_8821C)) +#define BIT_GET_H2CQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8821C) & \ + BIT_MASK_H2CQ_DESC_MODE_8821C) +#define BIT_SET_H2CQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_H2CQ_DESC_MODE_8821C(x) | BIT_H2CQ_DESC_MODE_8821C(v)) #define BIT_SHIFT_H2CQ_DESC_NUM_8821C 0 #define BIT_MASK_H2CQ_DESC_NUM_8821C 0xfff -#define BIT_H2CQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8821C) << BIT_SHIFT_H2CQ_DESC_NUM_8821C) -#define BIT_GET_H2CQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8821C) & BIT_MASK_H2CQ_DESC_NUM_8821C) - - +#define BIT_H2CQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_H2CQ_DESC_NUM_8821C) << BIT_SHIFT_H2CQ_DESC_NUM_8821C) +#define BITS_H2CQ_DESC_NUM_8821C \ + (BIT_MASK_H2CQ_DESC_NUM_8821C << BIT_SHIFT_H2CQ_DESC_NUM_8821C) +#define BIT_CLEAR_H2CQ_DESC_NUM_8821C(x) ((x) & (~BITS_H2CQ_DESC_NUM_8821C)) +#define BIT_GET_H2CQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8821C) & BIT_MASK_H2CQ_DESC_NUM_8821C) +#define BIT_SET_H2CQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_H2CQ_DESC_NUM_8821C(x) | BIT_H2CQ_DESC_NUM_8821C(v)) /* 2 REG_H2CQ_TXBD_IDX_8821C */ #define BIT_SHIFT_H2CQ_HW_IDX_8821C 16 #define BIT_MASK_H2CQ_HW_IDX_8821C 0xfff -#define BIT_H2CQ_HW_IDX_8821C(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8821C) << BIT_SHIFT_H2CQ_HW_IDX_8821C) -#define BIT_GET_H2CQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8821C) & BIT_MASK_H2CQ_HW_IDX_8821C) - - +#define BIT_H2CQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_H2CQ_HW_IDX_8821C) << BIT_SHIFT_H2CQ_HW_IDX_8821C) +#define BITS_H2CQ_HW_IDX_8821C \ + (BIT_MASK_H2CQ_HW_IDX_8821C << BIT_SHIFT_H2CQ_HW_IDX_8821C) +#define BIT_CLEAR_H2CQ_HW_IDX_8821C(x) ((x) & (~BITS_H2CQ_HW_IDX_8821C)) +#define BIT_GET_H2CQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8821C) & BIT_MASK_H2CQ_HW_IDX_8821C) +#define BIT_SET_H2CQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_H2CQ_HW_IDX_8821C(x) | BIT_H2CQ_HW_IDX_8821C(v)) #define BIT_SHIFT_H2CQ_HOST_IDX_8821C 0 #define BIT_MASK_H2CQ_HOST_IDX_8821C 0xfff -#define BIT_H2CQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8821C) << BIT_SHIFT_H2CQ_HOST_IDX_8821C) -#define BIT_GET_H2CQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8821C) & BIT_MASK_H2CQ_HOST_IDX_8821C) - - +#define BIT_H2CQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_H2CQ_HOST_IDX_8821C) << BIT_SHIFT_H2CQ_HOST_IDX_8821C) +#define BITS_H2CQ_HOST_IDX_8821C \ + (BIT_MASK_H2CQ_HOST_IDX_8821C << BIT_SHIFT_H2CQ_HOST_IDX_8821C) +#define BIT_CLEAR_H2CQ_HOST_IDX_8821C(x) ((x) & (~BITS_H2CQ_HOST_IDX_8821C)) +#define BIT_GET_H2CQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8821C) & BIT_MASK_H2CQ_HOST_IDX_8821C) +#define BIT_SET_H2CQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_H2CQ_HOST_IDX_8821C(x) | BIT_H2CQ_HOST_IDX_8821C(v)) /* 2 REG_H2CQ_CSR_8821C[31:0] (H2CQ CONTROL AND STATUS) */ #define BIT_H2CQ_FULL_8821C BIT(31) #define BIT_CLR_H2CQ_HOST_IDX_8821C BIT(16) #define BIT_CLR_H2CQ_HW_IDX_8821C BIT(8) +#define BIT_STOP_H2CQ_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_Q0_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q0_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q0_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q0_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) -#define BIT_GET_QUEUEMACID_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) & BIT_MASK_QUEUEMACID_Q0_V1_8821C) - - +#define BIT_QUEUEMACID_Q0_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) +#define BITS_QUEUEMACID_Q0_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q0_V1_8821C << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q0_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q0_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q0_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q0_V1_8821C) +#define BIT_SET_QUEUEMACID_Q0_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q0_V1_8821C(x) | BIT_QUEUEMACID_Q0_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q0_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q0_V1_8821C 0x3 -#define BIT_QUEUEAC_Q0_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8821C) << BIT_SHIFT_QUEUEAC_Q0_V1_8821C) -#define BIT_GET_QUEUEAC_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8821C) & BIT_MASK_QUEUEAC_Q0_V1_8821C) - +#define BIT_QUEUEAC_Q0_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q0_V1_8821C) << BIT_SHIFT_QUEUEAC_Q0_V1_8821C) +#define BITS_QUEUEAC_Q0_V1_8821C \ + (BIT_MASK_QUEUEAC_Q0_V1_8821C << BIT_SHIFT_QUEUEAC_Q0_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q0_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8821C)) +#define BIT_GET_QUEUEAC_Q0_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8821C) & BIT_MASK_QUEUEAC_Q0_V1_8821C) +#define BIT_SET_QUEUEAC_Q0_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q0_V1_8821C(x) | BIT_QUEUEAC_Q0_V1_8821C(v)) #define BIT_TIDEMPTY_Q0_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q0_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q0_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q0_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) -#define BIT_GET_TAIL_PKT_Q0_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) & BIT_MASK_TAIL_PKT_Q0_V2_8821C) - - +#define BIT_TAIL_PKT_Q0_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) +#define BITS_TAIL_PKT_Q0_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q0_V2_8821C << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q0_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q0_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q0_V2_8821C) +#define BIT_SET_TAIL_PKT_Q0_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q0_V2_8821C(x) | BIT_TAIL_PKT_Q0_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q0_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q0_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q0_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) -#define BIT_GET_HEAD_PKT_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) & BIT_MASK_HEAD_PKT_Q0_V1_8821C) - - +#define BIT_HEAD_PKT_Q0_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) +#define BITS_HEAD_PKT_Q0_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q0_V1_8821C << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q0_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q0_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q0_V1_8821C) +#define BIT_SET_HEAD_PKT_Q0_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q0_V1_8821C(x) | BIT_HEAD_PKT_Q0_V1_8821C(v)) /* 2 REG_Q1_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q1_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q1_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q1_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) -#define BIT_GET_QUEUEMACID_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) & BIT_MASK_QUEUEMACID_Q1_V1_8821C) - - +#define BIT_QUEUEMACID_Q1_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) +#define BITS_QUEUEMACID_Q1_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q1_V1_8821C << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q1_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q1_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q1_V1_8821C) +#define BIT_SET_QUEUEMACID_Q1_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q1_V1_8821C(x) | BIT_QUEUEMACID_Q1_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q1_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q1_V1_8821C 0x3 -#define BIT_QUEUEAC_Q1_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8821C) << BIT_SHIFT_QUEUEAC_Q1_V1_8821C) -#define BIT_GET_QUEUEAC_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8821C) & BIT_MASK_QUEUEAC_Q1_V1_8821C) - +#define BIT_QUEUEAC_Q1_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q1_V1_8821C) << BIT_SHIFT_QUEUEAC_Q1_V1_8821C) +#define BITS_QUEUEAC_Q1_V1_8821C \ + (BIT_MASK_QUEUEAC_Q1_V1_8821C << BIT_SHIFT_QUEUEAC_Q1_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q1_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8821C)) +#define BIT_GET_QUEUEAC_Q1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8821C) & BIT_MASK_QUEUEAC_Q1_V1_8821C) +#define BIT_SET_QUEUEAC_Q1_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q1_V1_8821C(x) | BIT_QUEUEAC_Q1_V1_8821C(v)) #define BIT_TIDEMPTY_Q1_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q1_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q1_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q1_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) -#define BIT_GET_TAIL_PKT_Q1_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) & BIT_MASK_TAIL_PKT_Q1_V2_8821C) - - +#define BIT_TAIL_PKT_Q1_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) +#define BITS_TAIL_PKT_Q1_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q1_V2_8821C << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q1_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q1_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q1_V2_8821C) +#define BIT_SET_TAIL_PKT_Q1_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q1_V2_8821C(x) | BIT_TAIL_PKT_Q1_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q1_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q1_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q1_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) -#define BIT_GET_HEAD_PKT_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) & BIT_MASK_HEAD_PKT_Q1_V1_8821C) - - +#define BIT_HEAD_PKT_Q1_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) +#define BITS_HEAD_PKT_Q1_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q1_V1_8821C << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q1_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q1_V1_8821C) +#define BIT_SET_HEAD_PKT_Q1_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q1_V1_8821C(x) | BIT_HEAD_PKT_Q1_V1_8821C(v)) /* 2 REG_Q2_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q2_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q2_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q2_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) -#define BIT_GET_QUEUEMACID_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) & BIT_MASK_QUEUEMACID_Q2_V1_8821C) - - +#define BIT_QUEUEMACID_Q2_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) +#define BITS_QUEUEMACID_Q2_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q2_V1_8821C << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q2_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q2_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q2_V1_8821C) +#define BIT_SET_QUEUEMACID_Q2_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q2_V1_8821C(x) | BIT_QUEUEMACID_Q2_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q2_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q2_V1_8821C 0x3 -#define BIT_QUEUEAC_Q2_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8821C) << BIT_SHIFT_QUEUEAC_Q2_V1_8821C) -#define BIT_GET_QUEUEAC_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8821C) & BIT_MASK_QUEUEAC_Q2_V1_8821C) - +#define BIT_QUEUEAC_Q2_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q2_V1_8821C) << BIT_SHIFT_QUEUEAC_Q2_V1_8821C) +#define BITS_QUEUEAC_Q2_V1_8821C \ + (BIT_MASK_QUEUEAC_Q2_V1_8821C << BIT_SHIFT_QUEUEAC_Q2_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q2_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8821C)) +#define BIT_GET_QUEUEAC_Q2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8821C) & BIT_MASK_QUEUEAC_Q2_V1_8821C) +#define BIT_SET_QUEUEAC_Q2_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q2_V1_8821C(x) | BIT_QUEUEAC_Q2_V1_8821C(v)) #define BIT_TIDEMPTY_Q2_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q2_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q2_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q2_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) -#define BIT_GET_TAIL_PKT_Q2_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) & BIT_MASK_TAIL_PKT_Q2_V2_8821C) - - +#define BIT_TAIL_PKT_Q2_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) +#define BITS_TAIL_PKT_Q2_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q2_V2_8821C << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q2_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q2_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q2_V2_8821C) +#define BIT_SET_TAIL_PKT_Q2_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q2_V2_8821C(x) | BIT_TAIL_PKT_Q2_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q2_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q2_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q2_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) -#define BIT_GET_HEAD_PKT_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) & BIT_MASK_HEAD_PKT_Q2_V1_8821C) - - +#define BIT_HEAD_PKT_Q2_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) +#define BITS_HEAD_PKT_Q2_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q2_V1_8821C << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q2_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q2_V1_8821C) +#define BIT_SET_HEAD_PKT_Q2_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q2_V1_8821C(x) | BIT_HEAD_PKT_Q2_V1_8821C(v)) /* 2 REG_Q3_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q3_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q3_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q3_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) -#define BIT_GET_QUEUEMACID_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) & BIT_MASK_QUEUEMACID_Q3_V1_8821C) - - +#define BIT_QUEUEMACID_Q3_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) +#define BITS_QUEUEMACID_Q3_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q3_V1_8821C << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q3_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q3_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q3_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q3_V1_8821C) +#define BIT_SET_QUEUEMACID_Q3_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q3_V1_8821C(x) | BIT_QUEUEMACID_Q3_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q3_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q3_V1_8821C 0x3 -#define BIT_QUEUEAC_Q3_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8821C) << BIT_SHIFT_QUEUEAC_Q3_V1_8821C) -#define BIT_GET_QUEUEAC_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8821C) & BIT_MASK_QUEUEAC_Q3_V1_8821C) - +#define BIT_QUEUEAC_Q3_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q3_V1_8821C) << BIT_SHIFT_QUEUEAC_Q3_V1_8821C) +#define BITS_QUEUEAC_Q3_V1_8821C \ + (BIT_MASK_QUEUEAC_Q3_V1_8821C << BIT_SHIFT_QUEUEAC_Q3_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q3_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8821C)) +#define BIT_GET_QUEUEAC_Q3_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8821C) & BIT_MASK_QUEUEAC_Q3_V1_8821C) +#define BIT_SET_QUEUEAC_Q3_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q3_V1_8821C(x) | BIT_QUEUEAC_Q3_V1_8821C(v)) #define BIT_TIDEMPTY_Q3_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q3_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q3_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q3_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) -#define BIT_GET_TAIL_PKT_Q3_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) & BIT_MASK_TAIL_PKT_Q3_V2_8821C) - - +#define BIT_TAIL_PKT_Q3_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) +#define BITS_TAIL_PKT_Q3_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q3_V2_8821C << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q3_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q3_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q3_V2_8821C) +#define BIT_SET_TAIL_PKT_Q3_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q3_V2_8821C(x) | BIT_TAIL_PKT_Q3_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q3_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q3_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q3_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) -#define BIT_GET_HEAD_PKT_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) & BIT_MASK_HEAD_PKT_Q3_V1_8821C) - - +#define BIT_HEAD_PKT_Q3_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) +#define BITS_HEAD_PKT_Q3_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q3_V1_8821C << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q3_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q3_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q3_V1_8821C) +#define BIT_SET_HEAD_PKT_Q3_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q3_V1_8821C(x) | BIT_HEAD_PKT_Q3_V1_8821C(v)) /* 2 REG_MGQ_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C 25 #define BIT_MASK_QUEUEMACID_MGQ_V1_8821C 0x7f -#define BIT_QUEUEMACID_MGQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) -#define BIT_GET_QUEUEMACID_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C) - - +#define BIT_QUEUEMACID_MGQ_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) +#define BITS_QUEUEMACID_MGQ_V1_8821C \ + (BIT_MASK_QUEUEMACID_MGQ_V1_8821C << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_MGQ_V1_8821C)) +#define BIT_GET_QUEUEMACID_MGQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) & \ + BIT_MASK_QUEUEMACID_MGQ_V1_8821C) +#define BIT_SET_QUEUEMACID_MGQ_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_MGQ_V1_8821C(x) | BIT_QUEUEMACID_MGQ_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_MGQ_V1_8821C 23 #define BIT_MASK_QUEUEAC_MGQ_V1_8821C 0x3 -#define BIT_QUEUEAC_MGQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8821C) << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) -#define BIT_GET_QUEUEAC_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) & BIT_MASK_QUEUEAC_MGQ_V1_8821C) - +#define BIT_QUEUEAC_MGQ_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8821C) \ + << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) +#define BITS_QUEUEAC_MGQ_V1_8821C \ + (BIT_MASK_QUEUEAC_MGQ_V1_8821C << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) +#define BIT_CLEAR_QUEUEAC_MGQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8821C)) +#define BIT_GET_QUEUEAC_MGQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) & \ + BIT_MASK_QUEUEAC_MGQ_V1_8821C) +#define BIT_SET_QUEUEAC_MGQ_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_MGQ_V1_8821C(x) | BIT_QUEUEAC_MGQ_V1_8821C(v)) #define BIT_TIDEMPTY_MGQ_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C 11 #define BIT_MASK_TAIL_PKT_MGQ_V2_8821C 0x7ff -#define BIT_TAIL_PKT_MGQ_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) -#define BIT_GET_TAIL_PKT_MGQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C) - - +#define BIT_TAIL_PKT_MGQ_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) +#define BITS_TAIL_PKT_MGQ_V2_8821C \ + (BIT_MASK_TAIL_PKT_MGQ_V2_8821C << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8821C)) +#define BIT_GET_TAIL_PKT_MGQ_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) & \ + BIT_MASK_TAIL_PKT_MGQ_V2_8821C) +#define BIT_SET_TAIL_PKT_MGQ_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_MGQ_V2_8821C(x) | BIT_TAIL_PKT_MGQ_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C 0 #define BIT_MASK_HEAD_PKT_MGQ_V1_8821C 0x7ff -#define BIT_HEAD_PKT_MGQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) -#define BIT_GET_HEAD_PKT_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C) - - +#define BIT_HEAD_PKT_MGQ_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) +#define BITS_HEAD_PKT_MGQ_V1_8821C \ + (BIT_MASK_HEAD_PKT_MGQ_V1_8821C << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8821C)) +#define BIT_GET_HEAD_PKT_MGQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) & \ + BIT_MASK_HEAD_PKT_MGQ_V1_8821C) +#define BIT_SET_HEAD_PKT_MGQ_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_MGQ_V1_8821C(x) | BIT_HEAD_PKT_MGQ_V1_8821C(v)) /* 2 REG_HIQ_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C 25 #define BIT_MASK_QUEUEMACID_HIQ_V1_8821C 0x7f -#define BIT_QUEUEMACID_HIQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) -#define BIT_GET_QUEUEMACID_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C) - - +#define BIT_QUEUEMACID_HIQ_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) +#define BITS_QUEUEMACID_HIQ_V1_8821C \ + (BIT_MASK_QUEUEMACID_HIQ_V1_8821C << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_HIQ_V1_8821C)) +#define BIT_GET_QUEUEMACID_HIQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) & \ + BIT_MASK_QUEUEMACID_HIQ_V1_8821C) +#define BIT_SET_QUEUEMACID_HIQ_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_HIQ_V1_8821C(x) | BIT_QUEUEMACID_HIQ_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_HIQ_V1_8821C 23 #define BIT_MASK_QUEUEAC_HIQ_V1_8821C 0x3 -#define BIT_QUEUEAC_HIQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8821C) << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) -#define BIT_GET_QUEUEAC_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) & BIT_MASK_QUEUEAC_HIQ_V1_8821C) - +#define BIT_QUEUEAC_HIQ_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8821C) \ + << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) +#define BITS_QUEUEAC_HIQ_V1_8821C \ + (BIT_MASK_QUEUEAC_HIQ_V1_8821C << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) +#define BIT_CLEAR_QUEUEAC_HIQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8821C)) +#define BIT_GET_QUEUEAC_HIQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) & \ + BIT_MASK_QUEUEAC_HIQ_V1_8821C) +#define BIT_SET_QUEUEAC_HIQ_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_HIQ_V1_8821C(x) | BIT_QUEUEAC_HIQ_V1_8821C(v)) #define BIT_TIDEMPTY_HIQ_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C 11 #define BIT_MASK_TAIL_PKT_HIQ_V2_8821C 0x7ff -#define BIT_TAIL_PKT_HIQ_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) -#define BIT_GET_TAIL_PKT_HIQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C) - - +#define BIT_TAIL_PKT_HIQ_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) +#define BITS_TAIL_PKT_HIQ_V2_8821C \ + (BIT_MASK_TAIL_PKT_HIQ_V2_8821C << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8821C)) +#define BIT_GET_TAIL_PKT_HIQ_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) & \ + BIT_MASK_TAIL_PKT_HIQ_V2_8821C) +#define BIT_SET_TAIL_PKT_HIQ_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_HIQ_V2_8821C(x) | BIT_TAIL_PKT_HIQ_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C 0 #define BIT_MASK_HEAD_PKT_HIQ_V1_8821C 0x7ff -#define BIT_HEAD_PKT_HIQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) -#define BIT_GET_HEAD_PKT_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C) - - +#define BIT_HEAD_PKT_HIQ_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) +#define BITS_HEAD_PKT_HIQ_V1_8821C \ + (BIT_MASK_HEAD_PKT_HIQ_V1_8821C << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8821C)) +#define BIT_GET_HEAD_PKT_HIQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) & \ + BIT_MASK_HEAD_PKT_HIQ_V1_8821C) +#define BIT_SET_HEAD_PKT_HIQ_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_HIQ_V1_8821C(x) | BIT_HEAD_PKT_HIQ_V1_8821C(v)) /* 2 REG_BCNQ_INFO_8821C */ #define BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C 0 #define BIT_MASK_BCNQ_HEAD_PG_V1_8821C 0xfff -#define BIT_BCNQ_HEAD_PG_V1_8821C(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) -#define BIT_GET_BCNQ_HEAD_PG_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C) - - +#define BIT_BCNQ_HEAD_PG_V1_8821C(x) \ + (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C) \ + << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) +#define BITS_BCNQ_HEAD_PG_V1_8821C \ + (BIT_MASK_BCNQ_HEAD_PG_V1_8821C << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) +#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8821C(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8821C)) +#define BIT_GET_BCNQ_HEAD_PG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) & \ + BIT_MASK_BCNQ_HEAD_PG_V1_8821C) +#define BIT_SET_BCNQ_HEAD_PG_V1_8821C(x, v) \ + (BIT_CLEAR_BCNQ_HEAD_PG_V1_8821C(x) | BIT_BCNQ_HEAD_PG_V1_8821C(v)) /* 2 REG_TXPKT_EMPTY_8821C */ #define BIT_BCNQ_EMPTY_8821C BIT(11) @@ -5548,10 +9087,17 @@ #define BIT_SHIFT_FW_FREE_TAIL_V1_8821C 0 #define BIT_MASK_FW_FREE_TAIL_V1_8821C 0xfff -#define BIT_FW_FREE_TAIL_V1_8821C(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8821C) << BIT_SHIFT_FW_FREE_TAIL_V1_8821C) -#define BIT_GET_FW_FREE_TAIL_V1_8821C(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8821C) & BIT_MASK_FW_FREE_TAIL_V1_8821C) - - +#define BIT_FW_FREE_TAIL_V1_8821C(x) \ + (((x) & BIT_MASK_FW_FREE_TAIL_V1_8821C) \ + << BIT_SHIFT_FW_FREE_TAIL_V1_8821C) +#define BITS_FW_FREE_TAIL_V1_8821C \ + (BIT_MASK_FW_FREE_TAIL_V1_8821C << BIT_SHIFT_FW_FREE_TAIL_V1_8821C) +#define BIT_CLEAR_FW_FREE_TAIL_V1_8821C(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8821C)) +#define BIT_GET_FW_FREE_TAIL_V1_8821C(x) \ + (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8821C) & \ + BIT_MASK_FW_FREE_TAIL_V1_8821C) +#define BIT_SET_FW_FREE_TAIL_V1_8821C(x, v) \ + (BIT_CLEAR_FW_FREE_TAIL_V1_8821C(x) | BIT_FW_FREE_TAIL_V1_8821C(v)) /* 2 REG_FWHW_TXQ_CTRL_8821C */ #define BIT_RTS_LIMIT_IN_OFDM_8821C BIT(23) @@ -5561,9 +9107,15 @@ #define BIT_SHIFT_EN_QUEUE_RPT_8821C 8 #define BIT_MASK_EN_QUEUE_RPT_8821C 0xff -#define BIT_EN_QUEUE_RPT_8821C(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8821C) << BIT_SHIFT_EN_QUEUE_RPT_8821C) -#define BIT_GET_EN_QUEUE_RPT_8821C(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8821C) & BIT_MASK_EN_QUEUE_RPT_8821C) - +#define BIT_EN_QUEUE_RPT_8821C(x) \ + (((x) & BIT_MASK_EN_QUEUE_RPT_8821C) << BIT_SHIFT_EN_QUEUE_RPT_8821C) +#define BITS_EN_QUEUE_RPT_8821C \ + (BIT_MASK_EN_QUEUE_RPT_8821C << BIT_SHIFT_EN_QUEUE_RPT_8821C) +#define BIT_CLEAR_EN_QUEUE_RPT_8821C(x) ((x) & (~BITS_EN_QUEUE_RPT_8821C)) +#define BIT_GET_EN_QUEUE_RPT_8821C(x) \ + (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8821C) & BIT_MASK_EN_QUEUE_RPT_8821C) +#define BIT_SET_EN_QUEUE_RPT_8821C(x, v) \ + (BIT_CLEAR_EN_QUEUE_RPT_8821C(x) | BIT_EN_QUEUE_RPT_8821C(v)) #define BIT_EN_RTY_BK_8821C BIT(7) #define BIT_EN_USE_INI_RAT_8821C BIT(6) @@ -5571,27 +9123,45 @@ #define BIT_DIS_SSN_CHECK_8821C BIT(4) #define BIT_MACID_MATCH_RTS_8821C BIT(3) #define BIT_EN_BCN_TRXRPT_V1_8821C BIT(2) -#define BIT_R_EN_FTMRPT_8821C BIT(1) +#define BIT_R_EN_FTMRPT_V1_8821C BIT(1) #define BIT_R_BMC_NAV_PROTECT_8821C BIT(0) /* 2 REG_DATAFB_SEL_8821C */ -#define BIT__R_EN_RTY_BK_COD_8821C BIT(2) +#define BIT_BROADCAST_RTY_EN_8821C BIT(3) +#define BIT_EN_RTY_BK_COD_8821C BIT(2) #define BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C 0 #define BIT_MASK__R_DATA_FALLBACK_SEL_8821C 0x3 -#define BIT__R_DATA_FALLBACK_SEL_8821C(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) -#define BIT_GET__R_DATA_FALLBACK_SEL_8821C(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C) - - +#define BIT__R_DATA_FALLBACK_SEL_8821C(x) \ + (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C) \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) +#define BITS__R_DATA_FALLBACK_SEL_8821C \ + (BIT_MASK__R_DATA_FALLBACK_SEL_8821C \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) +#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8821C(x) \ + ((x) & (~BITS__R_DATA_FALLBACK_SEL_8821C)) +#define BIT_GET__R_DATA_FALLBACK_SEL_8821C(x) \ + (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) & \ + BIT_MASK__R_DATA_FALLBACK_SEL_8821C) +#define BIT_SET__R_DATA_FALLBACK_SEL_8821C(x, v) \ + (BIT_CLEAR__R_DATA_FALLBACK_SEL_8821C(x) | \ + BIT__R_DATA_FALLBACK_SEL_8821C(v)) /* 2 REG_BCNQ_BDNY_V1_8821C */ #define BIT_SHIFT_BCNQ_PGBNDY_V1_8821C 0 #define BIT_MASK_BCNQ_PGBNDY_V1_8821C 0xfff -#define BIT_BCNQ_PGBNDY_V1_8821C(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8821C) << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) -#define BIT_GET_BCNQ_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) & BIT_MASK_BCNQ_PGBNDY_V1_8821C) - - +#define BIT_BCNQ_PGBNDY_V1_8821C(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8821C) \ + << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) +#define BITS_BCNQ_PGBNDY_V1_8821C \ + (BIT_MASK_BCNQ_PGBNDY_V1_8821C << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) +#define BIT_CLEAR_BCNQ_PGBNDY_V1_8821C(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8821C)) +#define BIT_GET_BCNQ_PGBNDY_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) & \ + BIT_MASK_BCNQ_PGBNDY_V1_8821C) +#define BIT_SET_BCNQ_PGBNDY_V1_8821C(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_V1_8821C(x) | BIT_BCNQ_PGBNDY_V1_8821C(v)) /* 2 REG_LIFETIME_EN_8821C */ #define BIT_BT_INT_CPU_8821C BIT(7) @@ -5608,33 +9178,55 @@ #define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C 8 #define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C 0xff -#define BIT_SPEC_SIFS_OFDM_PTCL_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) -#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) - - +#define BIT_SPEC_SIFS_OFDM_PTCL_8821C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) +#define BITS_SPEC_SIFS_OFDM_PTCL_8821C \ + (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8821C(x) \ + ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8821C)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8821C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) & \ + BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8821C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8821C(x) | \ + BIT_SPEC_SIFS_OFDM_PTCL_8821C(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C 0 #define BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C 0xff -#define BIT_SPEC_SIFS_CCK_PTCL_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) -#define BIT_GET_SPEC_SIFS_CCK_PTCL_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) - - +#define BIT_SPEC_SIFS_CCK_PTCL_8821C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) +#define BITS_SPEC_SIFS_CCK_PTCL_8821C \ + (BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8821C(x) \ + ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8821C)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8821C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) & \ + BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) +#define BIT_SET_SPEC_SIFS_CCK_PTCL_8821C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8821C(x) | \ + BIT_SPEC_SIFS_CCK_PTCL_8821C(v)) /* 2 REG_RETRY_LIMIT_8821C */ #define BIT_SHIFT_SRL_8821C 8 #define BIT_MASK_SRL_8821C 0x3f #define BIT_SRL_8821C(x) (((x) & BIT_MASK_SRL_8821C) << BIT_SHIFT_SRL_8821C) +#define BITS_SRL_8821C (BIT_MASK_SRL_8821C << BIT_SHIFT_SRL_8821C) +#define BIT_CLEAR_SRL_8821C(x) ((x) & (~BITS_SRL_8821C)) #define BIT_GET_SRL_8821C(x) (((x) >> BIT_SHIFT_SRL_8821C) & BIT_MASK_SRL_8821C) - - +#define BIT_SET_SRL_8821C(x, v) (BIT_CLEAR_SRL_8821C(x) | BIT_SRL_8821C(v)) #define BIT_SHIFT_LRL_8821C 0 #define BIT_MASK_LRL_8821C 0x3f #define BIT_LRL_8821C(x) (((x) & BIT_MASK_LRL_8821C) << BIT_SHIFT_LRL_8821C) +#define BITS_LRL_8821C (BIT_MASK_LRL_8821C << BIT_SHIFT_LRL_8821C) +#define BIT_CLEAR_LRL_8821C(x) ((x) & (~BITS_LRL_8821C)) #define BIT_GET_LRL_8821C(x) (((x) >> BIT_SHIFT_LRL_8821C) & BIT_MASK_LRL_8821C) - - +#define BIT_SET_LRL_8821C(x, v) (BIT_CLEAR_LRL_8821C(x) | BIT_LRL_8821C(v)) /* 2 REG_TXBF_CTRL_8821C */ #define BIT_R_ENABLE_NDPA_8821C BIT(31) @@ -5647,9 +9239,15 @@ #define BIT_SHIFT_R_TXBF1_AID_8821C 16 #define BIT_MASK_R_TXBF1_AID_8821C 0x1ff -#define BIT_R_TXBF1_AID_8821C(x) (((x) & BIT_MASK_R_TXBF1_AID_8821C) << BIT_SHIFT_R_TXBF1_AID_8821C) -#define BIT_GET_R_TXBF1_AID_8821C(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8821C) & BIT_MASK_R_TXBF1_AID_8821C) - +#define BIT_R_TXBF1_AID_8821C(x) \ + (((x) & BIT_MASK_R_TXBF1_AID_8821C) << BIT_SHIFT_R_TXBF1_AID_8821C) +#define BITS_R_TXBF1_AID_8821C \ + (BIT_MASK_R_TXBF1_AID_8821C << BIT_SHIFT_R_TXBF1_AID_8821C) +#define BIT_CLEAR_R_TXBF1_AID_8821C(x) ((x) & (~BITS_R_TXBF1_AID_8821C)) +#define BIT_GET_R_TXBF1_AID_8821C(x) \ + (((x) >> BIT_SHIFT_R_TXBF1_AID_8821C) & BIT_MASK_R_TXBF1_AID_8821C) +#define BIT_SET_R_TXBF1_AID_8821C(x, v) \ + (BIT_CLEAR_R_TXBF1_AID_8821C(x) | BIT_R_TXBF1_AID_8821C(v)) #define BIT_DIS_NDP_BFEN_8821C BIT(15) #define BIT_R_TXBCN_NOBLOCK_NDP_8821C BIT(14) @@ -5659,161 +9257,295 @@ #define BIT_SHIFT_R_TXBF0_AID_8821C 0 #define BIT_MASK_R_TXBF0_AID_8821C 0x1ff -#define BIT_R_TXBF0_AID_8821C(x) (((x) & BIT_MASK_R_TXBF0_AID_8821C) << BIT_SHIFT_R_TXBF0_AID_8821C) -#define BIT_GET_R_TXBF0_AID_8821C(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8821C) & BIT_MASK_R_TXBF0_AID_8821C) - - +#define BIT_R_TXBF0_AID_8821C(x) \ + (((x) & BIT_MASK_R_TXBF0_AID_8821C) << BIT_SHIFT_R_TXBF0_AID_8821C) +#define BITS_R_TXBF0_AID_8821C \ + (BIT_MASK_R_TXBF0_AID_8821C << BIT_SHIFT_R_TXBF0_AID_8821C) +#define BIT_CLEAR_R_TXBF0_AID_8821C(x) ((x) & (~BITS_R_TXBF0_AID_8821C)) +#define BIT_GET_R_TXBF0_AID_8821C(x) \ + (((x) >> BIT_SHIFT_R_TXBF0_AID_8821C) & BIT_MASK_R_TXBF0_AID_8821C) +#define BIT_SET_R_TXBF0_AID_8821C(x, v) \ + (BIT_CLEAR_R_TXBF0_AID_8821C(x) | BIT_R_TXBF0_AID_8821C(v)) /* 2 REG_DARFRC_8821C */ -#define BIT_SHIFT_DARF_RC8_8821C (56 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC8_8821C 0x1f -#define BIT_DARF_RC8_8821C(x) (((x) & BIT_MASK_DARF_RC8_8821C) << BIT_SHIFT_DARF_RC8_8821C) -#define BIT_GET_DARF_RC8_8821C(x) (((x) >> BIT_SHIFT_DARF_RC8_8821C) & BIT_MASK_DARF_RC8_8821C) - - - -#define BIT_SHIFT_DARF_RC7_8821C (48 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC7_8821C 0x1f -#define BIT_DARF_RC7_8821C(x) (((x) & BIT_MASK_DARF_RC7_8821C) << BIT_SHIFT_DARF_RC7_8821C) -#define BIT_GET_DARF_RC7_8821C(x) (((x) >> BIT_SHIFT_DARF_RC7_8821C) & BIT_MASK_DARF_RC7_8821C) - - - -#define BIT_SHIFT_DARF_RC6_8821C (40 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC6_8821C 0x1f -#define BIT_DARF_RC6_8821C(x) (((x) & BIT_MASK_DARF_RC6_8821C) << BIT_SHIFT_DARF_RC6_8821C) -#define BIT_GET_DARF_RC6_8821C(x) (((x) >> BIT_SHIFT_DARF_RC6_8821C) & BIT_MASK_DARF_RC6_8821C) - - - -#define BIT_SHIFT_DARF_RC5_8821C (32 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC5_8821C 0x1f -#define BIT_DARF_RC5_8821C(x) (((x) & BIT_MASK_DARF_RC5_8821C) << BIT_SHIFT_DARF_RC5_8821C) -#define BIT_GET_DARF_RC5_8821C(x) (((x) >> BIT_SHIFT_DARF_RC5_8821C) & BIT_MASK_DARF_RC5_8821C) - - - #define BIT_SHIFT_DARF_RC4_8821C 24 #define BIT_MASK_DARF_RC4_8821C 0x1f -#define BIT_DARF_RC4_8821C(x) (((x) & BIT_MASK_DARF_RC4_8821C) << BIT_SHIFT_DARF_RC4_8821C) -#define BIT_GET_DARF_RC4_8821C(x) (((x) >> BIT_SHIFT_DARF_RC4_8821C) & BIT_MASK_DARF_RC4_8821C) - - +#define BIT_DARF_RC4_8821C(x) \ + (((x) & BIT_MASK_DARF_RC4_8821C) << BIT_SHIFT_DARF_RC4_8821C) +#define BITS_DARF_RC4_8821C \ + (BIT_MASK_DARF_RC4_8821C << BIT_SHIFT_DARF_RC4_8821C) +#define BIT_CLEAR_DARF_RC4_8821C(x) ((x) & (~BITS_DARF_RC4_8821C)) +#define BIT_GET_DARF_RC4_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_8821C) & BIT_MASK_DARF_RC4_8821C) +#define BIT_SET_DARF_RC4_8821C(x, v) \ + (BIT_CLEAR_DARF_RC4_8821C(x) | BIT_DARF_RC4_8821C(v)) #define BIT_SHIFT_DARF_RC3_8821C 16 #define BIT_MASK_DARF_RC3_8821C 0x1f -#define BIT_DARF_RC3_8821C(x) (((x) & BIT_MASK_DARF_RC3_8821C) << BIT_SHIFT_DARF_RC3_8821C) -#define BIT_GET_DARF_RC3_8821C(x) (((x) >> BIT_SHIFT_DARF_RC3_8821C) & BIT_MASK_DARF_RC3_8821C) - - +#define BIT_DARF_RC3_8821C(x) \ + (((x) & BIT_MASK_DARF_RC3_8821C) << BIT_SHIFT_DARF_RC3_8821C) +#define BITS_DARF_RC3_8821C \ + (BIT_MASK_DARF_RC3_8821C << BIT_SHIFT_DARF_RC3_8821C) +#define BIT_CLEAR_DARF_RC3_8821C(x) ((x) & (~BITS_DARF_RC3_8821C)) +#define BIT_GET_DARF_RC3_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_8821C) & BIT_MASK_DARF_RC3_8821C) +#define BIT_SET_DARF_RC3_8821C(x, v) \ + (BIT_CLEAR_DARF_RC3_8821C(x) | BIT_DARF_RC3_8821C(v)) #define BIT_SHIFT_DARF_RC2_8821C 8 #define BIT_MASK_DARF_RC2_8821C 0x1f -#define BIT_DARF_RC2_8821C(x) (((x) & BIT_MASK_DARF_RC2_8821C) << BIT_SHIFT_DARF_RC2_8821C) -#define BIT_GET_DARF_RC2_8821C(x) (((x) >> BIT_SHIFT_DARF_RC2_8821C) & BIT_MASK_DARF_RC2_8821C) - - +#define BIT_DARF_RC2_8821C(x) \ + (((x) & BIT_MASK_DARF_RC2_8821C) << BIT_SHIFT_DARF_RC2_8821C) +#define BITS_DARF_RC2_8821C \ + (BIT_MASK_DARF_RC2_8821C << BIT_SHIFT_DARF_RC2_8821C) +#define BIT_CLEAR_DARF_RC2_8821C(x) ((x) & (~BITS_DARF_RC2_8821C)) +#define BIT_GET_DARF_RC2_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_8821C) & BIT_MASK_DARF_RC2_8821C) +#define BIT_SET_DARF_RC2_8821C(x, v) \ + (BIT_CLEAR_DARF_RC2_8821C(x) | BIT_DARF_RC2_8821C(v)) #define BIT_SHIFT_DARF_RC1_8821C 0 #define BIT_MASK_DARF_RC1_8821C 0x1f -#define BIT_DARF_RC1_8821C(x) (((x) & BIT_MASK_DARF_RC1_8821C) << BIT_SHIFT_DARF_RC1_8821C) -#define BIT_GET_DARF_RC1_8821C(x) (((x) >> BIT_SHIFT_DARF_RC1_8821C) & BIT_MASK_DARF_RC1_8821C) - - +#define BIT_DARF_RC1_8821C(x) \ + (((x) & BIT_MASK_DARF_RC1_8821C) << BIT_SHIFT_DARF_RC1_8821C) +#define BITS_DARF_RC1_8821C \ + (BIT_MASK_DARF_RC1_8821C << BIT_SHIFT_DARF_RC1_8821C) +#define BIT_CLEAR_DARF_RC1_8821C(x) ((x) & (~BITS_DARF_RC1_8821C)) +#define BIT_GET_DARF_RC1_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_8821C) & BIT_MASK_DARF_RC1_8821C) +#define BIT_SET_DARF_RC1_8821C(x, v) \ + (BIT_CLEAR_DARF_RC1_8821C(x) | BIT_DARF_RC1_8821C(v)) + +/* 2 REG_DARFRCH_8821C */ + +#define BIT_SHIFT_DARF_RC8_V1_8821C 24 +#define BIT_MASK_DARF_RC8_V1_8821C 0x1f +#define BIT_DARF_RC8_V1_8821C(x) \ + (((x) & BIT_MASK_DARF_RC8_V1_8821C) << BIT_SHIFT_DARF_RC8_V1_8821C) +#define BITS_DARF_RC8_V1_8821C \ + (BIT_MASK_DARF_RC8_V1_8821C << BIT_SHIFT_DARF_RC8_V1_8821C) +#define BIT_CLEAR_DARF_RC8_V1_8821C(x) ((x) & (~BITS_DARF_RC8_V1_8821C)) +#define BIT_GET_DARF_RC8_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_V1_8821C) & BIT_MASK_DARF_RC8_V1_8821C) +#define BIT_SET_DARF_RC8_V1_8821C(x, v) \ + (BIT_CLEAR_DARF_RC8_V1_8821C(x) | BIT_DARF_RC8_V1_8821C(v)) + +#define BIT_SHIFT_DARF_RC7_V1_8821C 16 +#define BIT_MASK_DARF_RC7_V1_8821C 0x1f +#define BIT_DARF_RC7_V1_8821C(x) \ + (((x) & BIT_MASK_DARF_RC7_V1_8821C) << BIT_SHIFT_DARF_RC7_V1_8821C) +#define BITS_DARF_RC7_V1_8821C \ + (BIT_MASK_DARF_RC7_V1_8821C << BIT_SHIFT_DARF_RC7_V1_8821C) +#define BIT_CLEAR_DARF_RC7_V1_8821C(x) ((x) & (~BITS_DARF_RC7_V1_8821C)) +#define BIT_GET_DARF_RC7_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_V1_8821C) & BIT_MASK_DARF_RC7_V1_8821C) +#define BIT_SET_DARF_RC7_V1_8821C(x, v) \ + (BIT_CLEAR_DARF_RC7_V1_8821C(x) | BIT_DARF_RC7_V1_8821C(v)) + +#define BIT_SHIFT_DARF_RC6_V1_8821C 8 +#define BIT_MASK_DARF_RC6_V1_8821C 0x1f +#define BIT_DARF_RC6_V1_8821C(x) \ + (((x) & BIT_MASK_DARF_RC6_V1_8821C) << BIT_SHIFT_DARF_RC6_V1_8821C) +#define BITS_DARF_RC6_V1_8821C \ + (BIT_MASK_DARF_RC6_V1_8821C << BIT_SHIFT_DARF_RC6_V1_8821C) +#define BIT_CLEAR_DARF_RC6_V1_8821C(x) ((x) & (~BITS_DARF_RC6_V1_8821C)) +#define BIT_GET_DARF_RC6_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_V1_8821C) & BIT_MASK_DARF_RC6_V1_8821C) +#define BIT_SET_DARF_RC6_V1_8821C(x, v) \ + (BIT_CLEAR_DARF_RC6_V1_8821C(x) | BIT_DARF_RC6_V1_8821C(v)) + +#define BIT_SHIFT_DARF_RC5_V1_8821C 0 +#define BIT_MASK_DARF_RC5_V1_8821C 0x1f +#define BIT_DARF_RC5_V1_8821C(x) \ + (((x) & BIT_MASK_DARF_RC5_V1_8821C) << BIT_SHIFT_DARF_RC5_V1_8821C) +#define BITS_DARF_RC5_V1_8821C \ + (BIT_MASK_DARF_RC5_V1_8821C << BIT_SHIFT_DARF_RC5_V1_8821C) +#define BIT_CLEAR_DARF_RC5_V1_8821C(x) ((x) & (~BITS_DARF_RC5_V1_8821C)) +#define BIT_GET_DARF_RC5_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_V1_8821C) & BIT_MASK_DARF_RC5_V1_8821C) +#define BIT_SET_DARF_RC5_V1_8821C(x, v) \ + (BIT_CLEAR_DARF_RC5_V1_8821C(x) | BIT_DARF_RC5_V1_8821C(v)) /* 2 REG_RARFRC_8821C */ -#define BIT_SHIFT_RARF_RC8_8821C (56 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC8_8821C 0x1f -#define BIT_RARF_RC8_8821C(x) (((x) & BIT_MASK_RARF_RC8_8821C) << BIT_SHIFT_RARF_RC8_8821C) -#define BIT_GET_RARF_RC8_8821C(x) (((x) >> BIT_SHIFT_RARF_RC8_8821C) & BIT_MASK_RARF_RC8_8821C) - - - -#define BIT_SHIFT_RARF_RC7_8821C (48 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC7_8821C 0x1f -#define BIT_RARF_RC7_8821C(x) (((x) & BIT_MASK_RARF_RC7_8821C) << BIT_SHIFT_RARF_RC7_8821C) -#define BIT_GET_RARF_RC7_8821C(x) (((x) >> BIT_SHIFT_RARF_RC7_8821C) & BIT_MASK_RARF_RC7_8821C) - - - -#define BIT_SHIFT_RARF_RC6_8821C (40 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC6_8821C 0x1f -#define BIT_RARF_RC6_8821C(x) (((x) & BIT_MASK_RARF_RC6_8821C) << BIT_SHIFT_RARF_RC6_8821C) -#define BIT_GET_RARF_RC6_8821C(x) (((x) >> BIT_SHIFT_RARF_RC6_8821C) & BIT_MASK_RARF_RC6_8821C) - - - -#define BIT_SHIFT_RARF_RC5_8821C (32 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC5_8821C 0x1f -#define BIT_RARF_RC5_8821C(x) (((x) & BIT_MASK_RARF_RC5_8821C) << BIT_SHIFT_RARF_RC5_8821C) -#define BIT_GET_RARF_RC5_8821C(x) (((x) >> BIT_SHIFT_RARF_RC5_8821C) & BIT_MASK_RARF_RC5_8821C) - - - #define BIT_SHIFT_RARF_RC4_8821C 24 #define BIT_MASK_RARF_RC4_8821C 0x1f -#define BIT_RARF_RC4_8821C(x) (((x) & BIT_MASK_RARF_RC4_8821C) << BIT_SHIFT_RARF_RC4_8821C) -#define BIT_GET_RARF_RC4_8821C(x) (((x) >> BIT_SHIFT_RARF_RC4_8821C) & BIT_MASK_RARF_RC4_8821C) - - +#define BIT_RARF_RC4_8821C(x) \ + (((x) & BIT_MASK_RARF_RC4_8821C) << BIT_SHIFT_RARF_RC4_8821C) +#define BITS_RARF_RC4_8821C \ + (BIT_MASK_RARF_RC4_8821C << BIT_SHIFT_RARF_RC4_8821C) +#define BIT_CLEAR_RARF_RC4_8821C(x) ((x) & (~BITS_RARF_RC4_8821C)) +#define BIT_GET_RARF_RC4_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC4_8821C) & BIT_MASK_RARF_RC4_8821C) +#define BIT_SET_RARF_RC4_8821C(x, v) \ + (BIT_CLEAR_RARF_RC4_8821C(x) | BIT_RARF_RC4_8821C(v)) #define BIT_SHIFT_RARF_RC3_8821C 16 #define BIT_MASK_RARF_RC3_8821C 0x1f -#define BIT_RARF_RC3_8821C(x) (((x) & BIT_MASK_RARF_RC3_8821C) << BIT_SHIFT_RARF_RC3_8821C) -#define BIT_GET_RARF_RC3_8821C(x) (((x) >> BIT_SHIFT_RARF_RC3_8821C) & BIT_MASK_RARF_RC3_8821C) - - +#define BIT_RARF_RC3_8821C(x) \ + (((x) & BIT_MASK_RARF_RC3_8821C) << BIT_SHIFT_RARF_RC3_8821C) +#define BITS_RARF_RC3_8821C \ + (BIT_MASK_RARF_RC3_8821C << BIT_SHIFT_RARF_RC3_8821C) +#define BIT_CLEAR_RARF_RC3_8821C(x) ((x) & (~BITS_RARF_RC3_8821C)) +#define BIT_GET_RARF_RC3_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC3_8821C) & BIT_MASK_RARF_RC3_8821C) +#define BIT_SET_RARF_RC3_8821C(x, v) \ + (BIT_CLEAR_RARF_RC3_8821C(x) | BIT_RARF_RC3_8821C(v)) #define BIT_SHIFT_RARF_RC2_8821C 8 #define BIT_MASK_RARF_RC2_8821C 0x1f -#define BIT_RARF_RC2_8821C(x) (((x) & BIT_MASK_RARF_RC2_8821C) << BIT_SHIFT_RARF_RC2_8821C) -#define BIT_GET_RARF_RC2_8821C(x) (((x) >> BIT_SHIFT_RARF_RC2_8821C) & BIT_MASK_RARF_RC2_8821C) - - +#define BIT_RARF_RC2_8821C(x) \ + (((x) & BIT_MASK_RARF_RC2_8821C) << BIT_SHIFT_RARF_RC2_8821C) +#define BITS_RARF_RC2_8821C \ + (BIT_MASK_RARF_RC2_8821C << BIT_SHIFT_RARF_RC2_8821C) +#define BIT_CLEAR_RARF_RC2_8821C(x) ((x) & (~BITS_RARF_RC2_8821C)) +#define BIT_GET_RARF_RC2_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC2_8821C) & BIT_MASK_RARF_RC2_8821C) +#define BIT_SET_RARF_RC2_8821C(x, v) \ + (BIT_CLEAR_RARF_RC2_8821C(x) | BIT_RARF_RC2_8821C(v)) #define BIT_SHIFT_RARF_RC1_8821C 0 #define BIT_MASK_RARF_RC1_8821C 0x1f -#define BIT_RARF_RC1_8821C(x) (((x) & BIT_MASK_RARF_RC1_8821C) << BIT_SHIFT_RARF_RC1_8821C) -#define BIT_GET_RARF_RC1_8821C(x) (((x) >> BIT_SHIFT_RARF_RC1_8821C) & BIT_MASK_RARF_RC1_8821C) - - +#define BIT_RARF_RC1_8821C(x) \ + (((x) & BIT_MASK_RARF_RC1_8821C) << BIT_SHIFT_RARF_RC1_8821C) +#define BITS_RARF_RC1_8821C \ + (BIT_MASK_RARF_RC1_8821C << BIT_SHIFT_RARF_RC1_8821C) +#define BIT_CLEAR_RARF_RC1_8821C(x) ((x) & (~BITS_RARF_RC1_8821C)) +#define BIT_GET_RARF_RC1_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC1_8821C) & BIT_MASK_RARF_RC1_8821C) +#define BIT_SET_RARF_RC1_8821C(x, v) \ + (BIT_CLEAR_RARF_RC1_8821C(x) | BIT_RARF_RC1_8821C(v)) + +/* 2 REG_RARFRCH_8821C */ + +#define BIT_SHIFT_RARF_RC8_V1_8821C 24 +#define BIT_MASK_RARF_RC8_V1_8821C 0x1f +#define BIT_RARF_RC8_V1_8821C(x) \ + (((x) & BIT_MASK_RARF_RC8_V1_8821C) << BIT_SHIFT_RARF_RC8_V1_8821C) +#define BITS_RARF_RC8_V1_8821C \ + (BIT_MASK_RARF_RC8_V1_8821C << BIT_SHIFT_RARF_RC8_V1_8821C) +#define BIT_CLEAR_RARF_RC8_V1_8821C(x) ((x) & (~BITS_RARF_RC8_V1_8821C)) +#define BIT_GET_RARF_RC8_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC8_V1_8821C) & BIT_MASK_RARF_RC8_V1_8821C) +#define BIT_SET_RARF_RC8_V1_8821C(x, v) \ + (BIT_CLEAR_RARF_RC8_V1_8821C(x) | BIT_RARF_RC8_V1_8821C(v)) + +#define BIT_SHIFT_RARF_RC7_V1_8821C 16 +#define BIT_MASK_RARF_RC7_V1_8821C 0x1f +#define BIT_RARF_RC7_V1_8821C(x) \ + (((x) & BIT_MASK_RARF_RC7_V1_8821C) << BIT_SHIFT_RARF_RC7_V1_8821C) +#define BITS_RARF_RC7_V1_8821C \ + (BIT_MASK_RARF_RC7_V1_8821C << BIT_SHIFT_RARF_RC7_V1_8821C) +#define BIT_CLEAR_RARF_RC7_V1_8821C(x) ((x) & (~BITS_RARF_RC7_V1_8821C)) +#define BIT_GET_RARF_RC7_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC7_V1_8821C) & BIT_MASK_RARF_RC7_V1_8821C) +#define BIT_SET_RARF_RC7_V1_8821C(x, v) \ + (BIT_CLEAR_RARF_RC7_V1_8821C(x) | BIT_RARF_RC7_V1_8821C(v)) + +#define BIT_SHIFT_RARF_RC6_V1_8821C 8 +#define BIT_MASK_RARF_RC6_V1_8821C 0x1f +#define BIT_RARF_RC6_V1_8821C(x) \ + (((x) & BIT_MASK_RARF_RC6_V1_8821C) << BIT_SHIFT_RARF_RC6_V1_8821C) +#define BITS_RARF_RC6_V1_8821C \ + (BIT_MASK_RARF_RC6_V1_8821C << BIT_SHIFT_RARF_RC6_V1_8821C) +#define BIT_CLEAR_RARF_RC6_V1_8821C(x) ((x) & (~BITS_RARF_RC6_V1_8821C)) +#define BIT_GET_RARF_RC6_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC6_V1_8821C) & BIT_MASK_RARF_RC6_V1_8821C) +#define BIT_SET_RARF_RC6_V1_8821C(x, v) \ + (BIT_CLEAR_RARF_RC6_V1_8821C(x) | BIT_RARF_RC6_V1_8821C(v)) + +#define BIT_SHIFT_RARF_RC5_V1_8821C 0 +#define BIT_MASK_RARF_RC5_V1_8821C 0x1f +#define BIT_RARF_RC5_V1_8821C(x) \ + (((x) & BIT_MASK_RARF_RC5_V1_8821C) << BIT_SHIFT_RARF_RC5_V1_8821C) +#define BITS_RARF_RC5_V1_8821C \ + (BIT_MASK_RARF_RC5_V1_8821C << BIT_SHIFT_RARF_RC5_V1_8821C) +#define BIT_CLEAR_RARF_RC5_V1_8821C(x) ((x) & (~BITS_RARF_RC5_V1_8821C)) +#define BIT_GET_RARF_RC5_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC5_V1_8821C) & BIT_MASK_RARF_RC5_V1_8821C) +#define BIT_SET_RARF_RC5_V1_8821C(x, v) \ + (BIT_CLEAR_RARF_RC5_V1_8821C(x) | BIT_RARF_RC5_V1_8821C(v)) /* 2 REG_RRSR_8821C */ #define BIT_SHIFT_RRSR_RSC_8821C 21 #define BIT_MASK_RRSR_RSC_8821C 0x3 -#define BIT_RRSR_RSC_8821C(x) (((x) & BIT_MASK_RRSR_RSC_8821C) << BIT_SHIFT_RRSR_RSC_8821C) -#define BIT_GET_RRSR_RSC_8821C(x) (((x) >> BIT_SHIFT_RRSR_RSC_8821C) & BIT_MASK_RRSR_RSC_8821C) - - -#define BIT_RRSR_BW_8821C BIT(20) +#define BIT_RRSR_RSC_8821C(x) \ + (((x) & BIT_MASK_RRSR_RSC_8821C) << BIT_SHIFT_RRSR_RSC_8821C) +#define BITS_RRSR_RSC_8821C \ + (BIT_MASK_RRSR_RSC_8821C << BIT_SHIFT_RRSR_RSC_8821C) +#define BIT_CLEAR_RRSR_RSC_8821C(x) ((x) & (~BITS_RRSR_RSC_8821C)) +#define BIT_GET_RRSR_RSC_8821C(x) \ + (((x) >> BIT_SHIFT_RRSR_RSC_8821C) & BIT_MASK_RRSR_RSC_8821C) +#define BIT_SET_RRSR_RSC_8821C(x, v) \ + (BIT_CLEAR_RRSR_RSC_8821C(x) | BIT_RRSR_RSC_8821C(v)) #define BIT_SHIFT_RRSC_BITMAP_8821C 0 #define BIT_MASK_RRSC_BITMAP_8821C 0xfffff -#define BIT_RRSC_BITMAP_8821C(x) (((x) & BIT_MASK_RRSC_BITMAP_8821C) << BIT_SHIFT_RRSC_BITMAP_8821C) -#define BIT_GET_RRSC_BITMAP_8821C(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8821C) & BIT_MASK_RRSC_BITMAP_8821C) - +#define BIT_RRSC_BITMAP_8821C(x) \ + (((x) & BIT_MASK_RRSC_BITMAP_8821C) << BIT_SHIFT_RRSC_BITMAP_8821C) +#define BITS_RRSC_BITMAP_8821C \ + (BIT_MASK_RRSC_BITMAP_8821C << BIT_SHIFT_RRSC_BITMAP_8821C) +#define BIT_CLEAR_RRSC_BITMAP_8821C(x) ((x) & (~BITS_RRSC_BITMAP_8821C)) +#define BIT_GET_RRSC_BITMAP_8821C(x) \ + (((x) >> BIT_SHIFT_RRSC_BITMAP_8821C) & BIT_MASK_RRSC_BITMAP_8821C) +#define BIT_SET_RRSC_BITMAP_8821C(x, v) \ + (BIT_CLEAR_RRSC_BITMAP_8821C(x) | BIT_RRSC_BITMAP_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_ARFR0_8821C */ -#define BIT_SHIFT_ARFR0_V1_8821C 0 -#define BIT_MASK_ARFR0_V1_8821C 0xffffffffffffffffL -#define BIT_ARFR0_V1_8821C(x) (((x) & BIT_MASK_ARFR0_V1_8821C) << BIT_SHIFT_ARFR0_V1_8821C) -#define BIT_GET_ARFR0_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR0_V1_8821C) & BIT_MASK_ARFR0_V1_8821C) - - +#define BIT_SHIFT_ARFRL0_8821C 0 +#define BIT_MASK_ARFRL0_8821C 0xffffffffL +#define BIT_ARFRL0_8821C(x) \ + (((x) & BIT_MASK_ARFRL0_8821C) << BIT_SHIFT_ARFRL0_8821C) +#define BITS_ARFRL0_8821C (BIT_MASK_ARFRL0_8821C << BIT_SHIFT_ARFRL0_8821C) +#define BIT_CLEAR_ARFRL0_8821C(x) ((x) & (~BITS_ARFRL0_8821C)) +#define BIT_GET_ARFRL0_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRL0_8821C) & BIT_MASK_ARFRL0_8821C) +#define BIT_SET_ARFRL0_8821C(x, v) \ + (BIT_CLEAR_ARFRL0_8821C(x) | BIT_ARFRL0_8821C(v)) + +/* 2 REG_ARFRH0_8821C */ + +#define BIT_SHIFT_ARFRH0_8821C 0 +#define BIT_MASK_ARFRH0_8821C 0xffffffffL +#define BIT_ARFRH0_8821C(x) \ + (((x) & BIT_MASK_ARFRH0_8821C) << BIT_SHIFT_ARFRH0_8821C) +#define BITS_ARFRH0_8821C (BIT_MASK_ARFRH0_8821C << BIT_SHIFT_ARFRH0_8821C) +#define BIT_CLEAR_ARFRH0_8821C(x) ((x) & (~BITS_ARFRH0_8821C)) +#define BIT_GET_ARFRH0_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRH0_8821C) & BIT_MASK_ARFRH0_8821C) +#define BIT_SET_ARFRH0_8821C(x, v) \ + (BIT_CLEAR_ARFRH0_8821C(x) | BIT_ARFRH0_8821C(v)) /* 2 REG_ARFR1_V1_8821C */ -#define BIT_SHIFT_ARFR1_V1_8821C 0 -#define BIT_MASK_ARFR1_V1_8821C 0xffffffffffffffffL -#define BIT_ARFR1_V1_8821C(x) (((x) & BIT_MASK_ARFR1_V1_8821C) << BIT_SHIFT_ARFR1_V1_8821C) -#define BIT_GET_ARFR1_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR1_V1_8821C) & BIT_MASK_ARFR1_V1_8821C) - - +#define BIT_SHIFT_ARFRL1_8821C 0 +#define BIT_MASK_ARFRL1_8821C 0xffffffffL +#define BIT_ARFRL1_8821C(x) \ + (((x) & BIT_MASK_ARFRL1_8821C) << BIT_SHIFT_ARFRL1_8821C) +#define BITS_ARFRL1_8821C (BIT_MASK_ARFRL1_8821C << BIT_SHIFT_ARFRL1_8821C) +#define BIT_CLEAR_ARFRL1_8821C(x) ((x) & (~BITS_ARFRL1_8821C)) +#define BIT_GET_ARFRL1_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRL1_8821C) & BIT_MASK_ARFRL1_8821C) +#define BIT_SET_ARFRL1_8821C(x, v) \ + (BIT_CLEAR_ARFRL1_8821C(x) | BIT_ARFRL1_8821C(v)) + +/* 2 REG_ARFRH1_V1_8821C */ + +#define BIT_SHIFT_ARFRH1_8821C 0 +#define BIT_MASK_ARFRH1_8821C 0xffffffffL +#define BIT_ARFRH1_8821C(x) \ + (((x) & BIT_MASK_ARFRH1_8821C) << BIT_SHIFT_ARFRH1_8821C) +#define BITS_ARFRH1_8821C (BIT_MASK_ARFRH1_8821C << BIT_SHIFT_ARFRH1_8821C) +#define BIT_CLEAR_ARFRH1_8821C(x) ((x) & (~BITS_ARFRH1_8821C)) +#define BIT_GET_ARFRH1_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRH1_8821C) & BIT_MASK_ARFRH1_8821C) +#define BIT_SET_ARFRH1_8821C(x, v) \ + (BIT_CLEAR_ARFRH1_8821C(x) | BIT_ARFRH1_8821C(v)) /* 2 REG_CCK_CHECK_8821C */ #define BIT_CHECK_CCK_EN_8821C BIT(7) @@ -5829,28 +9561,50 @@ #define BIT_SHIFT_AMPDU_MAX_TIME_8821C 0 #define BIT_MASK_AMPDU_MAX_TIME_8821C 0xff -#define BIT_AMPDU_MAX_TIME_8821C(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8821C) << BIT_SHIFT_AMPDU_MAX_TIME_8821C) -#define BIT_GET_AMPDU_MAX_TIME_8821C(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8821C) & BIT_MASK_AMPDU_MAX_TIME_8821C) - - +#define BIT_AMPDU_MAX_TIME_8821C(x) \ + (((x) & BIT_MASK_AMPDU_MAX_TIME_8821C) \ + << BIT_SHIFT_AMPDU_MAX_TIME_8821C) +#define BITS_AMPDU_MAX_TIME_8821C \ + (BIT_MASK_AMPDU_MAX_TIME_8821C << BIT_SHIFT_AMPDU_MAX_TIME_8821C) +#define BIT_CLEAR_AMPDU_MAX_TIME_8821C(x) ((x) & (~BITS_AMPDU_MAX_TIME_8821C)) +#define BIT_GET_AMPDU_MAX_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8821C) & \ + BIT_MASK_AMPDU_MAX_TIME_8821C) +#define BIT_SET_AMPDU_MAX_TIME_8821C(x, v) \ + (BIT_CLEAR_AMPDU_MAX_TIME_8821C(x) | BIT_AMPDU_MAX_TIME_8821C(v)) /* 2 REG_BCNQ1_BDNY_V1_8821C */ #define BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C 0 #define BIT_MASK_BCNQ1_PGBNDY_V1_8821C 0xfff -#define BIT_BCNQ1_PGBNDY_V1_8821C(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) -#define BIT_GET_BCNQ1_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C) - - +#define BIT_BCNQ1_PGBNDY_V1_8821C(x) \ + (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C) \ + << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) +#define BITS_BCNQ1_PGBNDY_V1_8821C \ + (BIT_MASK_BCNQ1_PGBNDY_V1_8821C << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) +#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8821C(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8821C)) +#define BIT_GET_BCNQ1_PGBNDY_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) & \ + BIT_MASK_BCNQ1_PGBNDY_V1_8821C) +#define BIT_SET_BCNQ1_PGBNDY_V1_8821C(x, v) \ + (BIT_CLEAR_BCNQ1_PGBNDY_V1_8821C(x) | BIT_BCNQ1_PGBNDY_V1_8821C(v)) /* 2 REG_AMPDU_MAX_LENGTH_8821C */ #define BIT_SHIFT_AMPDU_MAX_LENGTH_8821C 0 #define BIT_MASK_AMPDU_MAX_LENGTH_8821C 0xffffffffL -#define BIT_AMPDU_MAX_LENGTH_8821C(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8821C) << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) -#define BIT_GET_AMPDU_MAX_LENGTH_8821C(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) & BIT_MASK_AMPDU_MAX_LENGTH_8821C) - - +#define BIT_AMPDU_MAX_LENGTH_8821C(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8821C) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) +#define BITS_AMPDU_MAX_LENGTH_8821C \ + (BIT_MASK_AMPDU_MAX_LENGTH_8821C << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_8821C(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_8821C)) +#define BIT_GET_AMPDU_MAX_LENGTH_8821C(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) & \ + BIT_MASK_AMPDU_MAX_LENGTH_8821C) +#define BIT_SET_AMPDU_MAX_LENGTH_8821C(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_8821C(x) | BIT_AMPDU_MAX_LENGTH_8821C(v)) /* 2 REG_ACQ_STOP_8821C */ #define BIT_AC7Q_STOP_8821C BIT(7) @@ -5866,10 +9620,17 @@ #define BIT_SHIFT_R_NDPA_RATE_V1_8821C 0 #define BIT_MASK_R_NDPA_RATE_V1_8821C 0xff -#define BIT_R_NDPA_RATE_V1_8821C(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8821C) << BIT_SHIFT_R_NDPA_RATE_V1_8821C) -#define BIT_GET_R_NDPA_RATE_V1_8821C(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8821C) & BIT_MASK_R_NDPA_RATE_V1_8821C) - - +#define BIT_R_NDPA_RATE_V1_8821C(x) \ + (((x) & BIT_MASK_R_NDPA_RATE_V1_8821C) \ + << BIT_SHIFT_R_NDPA_RATE_V1_8821C) +#define BITS_R_NDPA_RATE_V1_8821C \ + (BIT_MASK_R_NDPA_RATE_V1_8821C << BIT_SHIFT_R_NDPA_RATE_V1_8821C) +#define BIT_CLEAR_R_NDPA_RATE_V1_8821C(x) ((x) & (~BITS_R_NDPA_RATE_V1_8821C)) +#define BIT_GET_R_NDPA_RATE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8821C) & \ + BIT_MASK_R_NDPA_RATE_V1_8821C) +#define BIT_SET_R_NDPA_RATE_V1_8821C(x, v) \ + (BIT_CLEAR_R_NDPA_RATE_V1_8821C(x) | BIT_R_NDPA_RATE_V1_8821C(v)) /* 2 REG_TX_HANG_CTRL_8821C */ #define BIT_R_EN_GNT_BT_AWAKE_8821C BIT(3) @@ -5882,20 +9643,29 @@ #define BIT_SHIFT_BW_SIGTA_8821C 3 #define BIT_MASK_BW_SIGTA_8821C 0x3 -#define BIT_BW_SIGTA_8821C(x) (((x) & BIT_MASK_BW_SIGTA_8821C) << BIT_SHIFT_BW_SIGTA_8821C) -#define BIT_GET_BW_SIGTA_8821C(x) (((x) >> BIT_SHIFT_BW_SIGTA_8821C) & BIT_MASK_BW_SIGTA_8821C) - +#define BIT_BW_SIGTA_8821C(x) \ + (((x) & BIT_MASK_BW_SIGTA_8821C) << BIT_SHIFT_BW_SIGTA_8821C) +#define BITS_BW_SIGTA_8821C \ + (BIT_MASK_BW_SIGTA_8821C << BIT_SHIFT_BW_SIGTA_8821C) +#define BIT_CLEAR_BW_SIGTA_8821C(x) ((x) & (~BITS_BW_SIGTA_8821C)) +#define BIT_GET_BW_SIGTA_8821C(x) \ + (((x) >> BIT_SHIFT_BW_SIGTA_8821C) & BIT_MASK_BW_SIGTA_8821C) +#define BIT_SET_BW_SIGTA_8821C(x, v) \ + (BIT_CLEAR_BW_SIGTA_8821C(x) | BIT_BW_SIGTA_8821C(v)) #define BIT_EN_BAR_SIGTA_8821C BIT(2) #define BIT_SHIFT_R_NDPA_BW_8821C 0 #define BIT_MASK_R_NDPA_BW_8821C 0x3 -#define BIT_R_NDPA_BW_8821C(x) (((x) & BIT_MASK_R_NDPA_BW_8821C) << BIT_SHIFT_R_NDPA_BW_8821C) -#define BIT_GET_R_NDPA_BW_8821C(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8821C) & BIT_MASK_R_NDPA_BW_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_R_NDPA_BW_8821C(x) \ + (((x) & BIT_MASK_R_NDPA_BW_8821C) << BIT_SHIFT_R_NDPA_BW_8821C) +#define BITS_R_NDPA_BW_8821C \ + (BIT_MASK_R_NDPA_BW_8821C << BIT_SHIFT_R_NDPA_BW_8821C) +#define BIT_CLEAR_R_NDPA_BW_8821C(x) ((x) & (~BITS_R_NDPA_BW_8821C)) +#define BIT_GET_R_NDPA_BW_8821C(x) \ + (((x) >> BIT_SHIFT_R_NDPA_BW_8821C) & BIT_MASK_R_NDPA_BW_8821C) +#define BIT_SET_R_NDPA_BW_8821C(x, v) \ + (BIT_CLEAR_R_NDPA_BW_8821C(x) | BIT_R_NDPA_BW_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -5903,213 +9673,408 @@ #define BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C 0 #define BIT_MASK_RD_RESP_PKT_TH_V1_8821C 0x3f -#define BIT_RD_RESP_PKT_TH_V1_8821C(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) -#define BIT_GET_RD_RESP_PKT_TH_V1_8821C(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C) - - +#define BIT_RD_RESP_PKT_TH_V1_8821C(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C) \ + << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) +#define BITS_RD_RESP_PKT_TH_V1_8821C \ + (BIT_MASK_RD_RESP_PKT_TH_V1_8821C << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8821C(x) \ + ((x) & (~BITS_RD_RESP_PKT_TH_V1_8821C)) +#define BIT_GET_RD_RESP_PKT_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) & \ + BIT_MASK_RD_RESP_PKT_TH_V1_8821C) +#define BIT_SET_RD_RESP_PKT_TH_V1_8821C(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH_V1_8821C(x) | BIT_RD_RESP_PKT_TH_V1_8821C(v)) /* 2 REG_CMDQ_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C 25 #define BIT_MASK_QUEUEMACID_CMDQ_V1_8821C 0x7f -#define BIT_QUEUEMACID_CMDQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) -#define BIT_GET_QUEUEMACID_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) - - +#define BIT_QUEUEMACID_CMDQ_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) +#define BITS_QUEUEMACID_CMDQ_V1_8821C \ + (BIT_MASK_QUEUEMACID_CMDQ_V1_8821C \ + << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_CMDQ_V1_8821C)) +#define BIT_GET_QUEUEMACID_CMDQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) & \ + BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) +#define BIT_SET_QUEUEMACID_CMDQ_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_CMDQ_V1_8821C(x) | \ + BIT_QUEUEMACID_CMDQ_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C 23 #define BIT_MASK_QUEUEAC_CMDQ_V1_8821C 0x3 -#define BIT_QUEUEAC_CMDQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C) << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) -#define BIT_GET_QUEUEAC_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C) - +#define BIT_QUEUEAC_CMDQ_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C) \ + << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) +#define BITS_QUEUEAC_CMDQ_V1_8821C \ + (BIT_MASK_QUEUEAC_CMDQ_V1_8821C << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) +#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8821C)) +#define BIT_GET_QUEUEAC_CMDQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) & \ + BIT_MASK_QUEUEAC_CMDQ_V1_8821C) +#define BIT_SET_QUEUEAC_CMDQ_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_CMDQ_V1_8821C(x) | BIT_QUEUEAC_CMDQ_V1_8821C(v)) #define BIT_TIDEMPTY_CMDQ_V1_8821C BIT(22) -#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C 11 -#define BIT_MASK_TAIL_PKT_CMDQ_V2_8821C 0x7ff -#define BIT_TAIL_PKT_CMDQ_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8821C) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C) -#define BIT_GET_TAIL_PKT_CMDQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C) & BIT_MASK_TAIL_PKT_CMDQ_V2_8821C) - - +#define BIT_SHIFT_TAIL_PKT_Q4_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_Q4_V2_8821C 0x7ff +#define BIT_TAIL_PKT_Q4_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) +#define BITS_TAIL_PKT_Q4_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q4_V2_8821C << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q4_V2_8821C) +#define BIT_SET_TAIL_PKT_Q4_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) | BIT_TAIL_PKT_Q4_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C 0 #define BIT_MASK_HEAD_PKT_CMDQ_V1_8821C 0x7ff -#define BIT_HEAD_PKT_CMDQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) -#define BIT_GET_HEAD_PKT_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) - - +#define BIT_HEAD_PKT_CMDQ_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) +#define BITS_HEAD_PKT_CMDQ_V1_8821C \ + (BIT_MASK_HEAD_PKT_CMDQ_V1_8821C << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8821C(x) \ + ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8821C)) +#define BIT_GET_HEAD_PKT_CMDQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) & \ + BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) +#define BIT_SET_HEAD_PKT_CMDQ_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8821C(x) | BIT_HEAD_PKT_CMDQ_V1_8821C(v)) /* 2 REG_Q4_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q4_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q4_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q4_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) -#define BIT_GET_QUEUEMACID_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) & BIT_MASK_QUEUEMACID_Q4_V1_8821C) - - +#define BIT_QUEUEMACID_Q4_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) +#define BITS_QUEUEMACID_Q4_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q4_V1_8821C << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q4_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q4_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q4_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q4_V1_8821C) +#define BIT_SET_QUEUEMACID_Q4_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q4_V1_8821C(x) | BIT_QUEUEMACID_Q4_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q4_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q4_V1_8821C 0x3 -#define BIT_QUEUEAC_Q4_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8821C) << BIT_SHIFT_QUEUEAC_Q4_V1_8821C) -#define BIT_GET_QUEUEAC_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8821C) & BIT_MASK_QUEUEAC_Q4_V1_8821C) - +#define BIT_QUEUEAC_Q4_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q4_V1_8821C) << BIT_SHIFT_QUEUEAC_Q4_V1_8821C) +#define BITS_QUEUEAC_Q4_V1_8821C \ + (BIT_MASK_QUEUEAC_Q4_V1_8821C << BIT_SHIFT_QUEUEAC_Q4_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q4_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8821C)) +#define BIT_GET_QUEUEAC_Q4_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8821C) & BIT_MASK_QUEUEAC_Q4_V1_8821C) +#define BIT_SET_QUEUEAC_Q4_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q4_V1_8821C(x) | BIT_QUEUEAC_Q4_V1_8821C(v)) #define BIT_TIDEMPTY_Q4_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q4_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q4_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q4_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) -#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) - - +#define BIT_TAIL_PKT_Q4_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) +#define BITS_TAIL_PKT_Q4_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q4_V2_8821C << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q4_V2_8821C) +#define BIT_SET_TAIL_PKT_Q4_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) | BIT_TAIL_PKT_Q4_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q4_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q4_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q4_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) -#define BIT_GET_HEAD_PKT_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) & BIT_MASK_HEAD_PKT_Q4_V1_8821C) - - +#define BIT_HEAD_PKT_Q4_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) +#define BITS_HEAD_PKT_Q4_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q4_V1_8821C << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q4_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q4_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q4_V1_8821C) +#define BIT_SET_HEAD_PKT_Q4_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q4_V1_8821C(x) | BIT_HEAD_PKT_Q4_V1_8821C(v)) /* 2 REG_Q5_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q5_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q5_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q5_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) -#define BIT_GET_QUEUEMACID_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) & BIT_MASK_QUEUEMACID_Q5_V1_8821C) - - +#define BIT_QUEUEMACID_Q5_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) +#define BITS_QUEUEMACID_Q5_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q5_V1_8821C << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q5_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q5_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q5_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q5_V1_8821C) +#define BIT_SET_QUEUEMACID_Q5_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q5_V1_8821C(x) | BIT_QUEUEMACID_Q5_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q5_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q5_V1_8821C 0x3 -#define BIT_QUEUEAC_Q5_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8821C) << BIT_SHIFT_QUEUEAC_Q5_V1_8821C) -#define BIT_GET_QUEUEAC_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8821C) & BIT_MASK_QUEUEAC_Q5_V1_8821C) - +#define BIT_QUEUEAC_Q5_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q5_V1_8821C) << BIT_SHIFT_QUEUEAC_Q5_V1_8821C) +#define BITS_QUEUEAC_Q5_V1_8821C \ + (BIT_MASK_QUEUEAC_Q5_V1_8821C << BIT_SHIFT_QUEUEAC_Q5_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q5_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8821C)) +#define BIT_GET_QUEUEAC_Q5_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8821C) & BIT_MASK_QUEUEAC_Q5_V1_8821C) +#define BIT_SET_QUEUEAC_Q5_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q5_V1_8821C(x) | BIT_QUEUEAC_Q5_V1_8821C(v)) #define BIT_TIDEMPTY_Q5_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q5_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q5_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q5_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) -#define BIT_GET_TAIL_PKT_Q5_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) & BIT_MASK_TAIL_PKT_Q5_V2_8821C) - - +#define BIT_TAIL_PKT_Q5_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) +#define BITS_TAIL_PKT_Q5_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q5_V2_8821C << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q5_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q5_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q5_V2_8821C) +#define BIT_SET_TAIL_PKT_Q5_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q5_V2_8821C(x) | BIT_TAIL_PKT_Q5_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q5_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q5_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q5_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) -#define BIT_GET_HEAD_PKT_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) & BIT_MASK_HEAD_PKT_Q5_V1_8821C) - - +#define BIT_HEAD_PKT_Q5_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) +#define BITS_HEAD_PKT_Q5_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q5_V1_8821C << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q5_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q5_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q5_V1_8821C) +#define BIT_SET_HEAD_PKT_Q5_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q5_V1_8821C(x) | BIT_HEAD_PKT_Q5_V1_8821C(v)) /* 2 REG_Q6_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q6_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q6_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q6_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) -#define BIT_GET_QUEUEMACID_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) & BIT_MASK_QUEUEMACID_Q6_V1_8821C) - - +#define BIT_QUEUEMACID_Q6_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) +#define BITS_QUEUEMACID_Q6_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q6_V1_8821C << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q6_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q6_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q6_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q6_V1_8821C) +#define BIT_SET_QUEUEMACID_Q6_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q6_V1_8821C(x) | BIT_QUEUEMACID_Q6_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q6_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q6_V1_8821C 0x3 -#define BIT_QUEUEAC_Q6_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8821C) << BIT_SHIFT_QUEUEAC_Q6_V1_8821C) -#define BIT_GET_QUEUEAC_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8821C) & BIT_MASK_QUEUEAC_Q6_V1_8821C) - +#define BIT_QUEUEAC_Q6_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q6_V1_8821C) << BIT_SHIFT_QUEUEAC_Q6_V1_8821C) +#define BITS_QUEUEAC_Q6_V1_8821C \ + (BIT_MASK_QUEUEAC_Q6_V1_8821C << BIT_SHIFT_QUEUEAC_Q6_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q6_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8821C)) +#define BIT_GET_QUEUEAC_Q6_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8821C) & BIT_MASK_QUEUEAC_Q6_V1_8821C) +#define BIT_SET_QUEUEAC_Q6_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q6_V1_8821C(x) | BIT_QUEUEAC_Q6_V1_8821C(v)) #define BIT_TIDEMPTY_Q6_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q6_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q6_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q6_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) -#define BIT_GET_TAIL_PKT_Q6_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) & BIT_MASK_TAIL_PKT_Q6_V2_8821C) - - +#define BIT_TAIL_PKT_Q6_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) +#define BITS_TAIL_PKT_Q6_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q6_V2_8821C << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q6_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q6_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q6_V2_8821C) +#define BIT_SET_TAIL_PKT_Q6_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q6_V2_8821C(x) | BIT_TAIL_PKT_Q6_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q6_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q6_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q6_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) -#define BIT_GET_HEAD_PKT_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) & BIT_MASK_HEAD_PKT_Q6_V1_8821C) - - +#define BIT_HEAD_PKT_Q6_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) +#define BITS_HEAD_PKT_Q6_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q6_V1_8821C << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q6_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q6_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q6_V1_8821C) +#define BIT_SET_HEAD_PKT_Q6_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q6_V1_8821C(x) | BIT_HEAD_PKT_Q6_V1_8821C(v)) /* 2 REG_Q7_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q7_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q7_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q7_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) -#define BIT_GET_QUEUEMACID_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) & BIT_MASK_QUEUEMACID_Q7_V1_8821C) - - +#define BIT_QUEUEMACID_Q7_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) +#define BITS_QUEUEMACID_Q7_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q7_V1_8821C << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q7_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q7_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q7_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q7_V1_8821C) +#define BIT_SET_QUEUEMACID_Q7_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q7_V1_8821C(x) | BIT_QUEUEMACID_Q7_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q7_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q7_V1_8821C 0x3 -#define BIT_QUEUEAC_Q7_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8821C) << BIT_SHIFT_QUEUEAC_Q7_V1_8821C) -#define BIT_GET_QUEUEAC_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8821C) & BIT_MASK_QUEUEAC_Q7_V1_8821C) - +#define BIT_QUEUEAC_Q7_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q7_V1_8821C) << BIT_SHIFT_QUEUEAC_Q7_V1_8821C) +#define BITS_QUEUEAC_Q7_V1_8821C \ + (BIT_MASK_QUEUEAC_Q7_V1_8821C << BIT_SHIFT_QUEUEAC_Q7_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q7_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8821C)) +#define BIT_GET_QUEUEAC_Q7_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8821C) & BIT_MASK_QUEUEAC_Q7_V1_8821C) +#define BIT_SET_QUEUEAC_Q7_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q7_V1_8821C(x) | BIT_QUEUEAC_Q7_V1_8821C(v)) #define BIT_TIDEMPTY_Q7_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q7_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q7_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q7_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) -#define BIT_GET_TAIL_PKT_Q7_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) & BIT_MASK_TAIL_PKT_Q7_V2_8821C) - - +#define BIT_TAIL_PKT_Q7_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) +#define BITS_TAIL_PKT_Q7_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q7_V2_8821C << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q7_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q7_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q7_V2_8821C) +#define BIT_SET_TAIL_PKT_Q7_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q7_V2_8821C(x) | BIT_TAIL_PKT_Q7_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q7_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q7_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q7_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) -#define BIT_GET_HEAD_PKT_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) & BIT_MASK_HEAD_PKT_Q7_V1_8821C) - - +#define BIT_HEAD_PKT_Q7_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) +#define BITS_HEAD_PKT_Q7_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q7_V1_8821C << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q7_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q7_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q7_V1_8821C) +#define BIT_SET_HEAD_PKT_Q7_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q7_V1_8821C(x) | BIT_HEAD_PKT_Q7_V1_8821C(v)) /* 2 REG_WMAC_LBK_BUF_HD_V1_8821C */ #define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C 0 #define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C 0xfff -#define BIT_WMAC_LBK_BUF_HEAD_V1_8821C(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) -#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8821C(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) - - +#define BIT_WMAC_LBK_BUF_HEAD_V1_8821C(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) +#define BITS_WMAC_LBK_BUF_HEAD_V1_8821C \ + (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8821C(x) \ + ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8821C)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) & \ + BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8821C(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8821C(x) | \ + BIT_WMAC_LBK_BUF_HEAD_V1_8821C(v)) /* 2 REG_MGQ_BDNY_V1_8821C */ #define BIT_SHIFT_MGQ_PGBNDY_V1_8821C 0 #define BIT_MASK_MGQ_PGBNDY_V1_8821C 0xfff -#define BIT_MGQ_PGBNDY_V1_8821C(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8821C) << BIT_SHIFT_MGQ_PGBNDY_V1_8821C) -#define BIT_GET_MGQ_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8821C) & BIT_MASK_MGQ_PGBNDY_V1_8821C) - - +#define BIT_MGQ_PGBNDY_V1_8821C(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V1_8821C) << BIT_SHIFT_MGQ_PGBNDY_V1_8821C) +#define BITS_MGQ_PGBNDY_V1_8821C \ + (BIT_MASK_MGQ_PGBNDY_V1_8821C << BIT_SHIFT_MGQ_PGBNDY_V1_8821C) +#define BIT_CLEAR_MGQ_PGBNDY_V1_8821C(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8821C)) +#define BIT_GET_MGQ_PGBNDY_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8821C) & BIT_MASK_MGQ_PGBNDY_V1_8821C) +#define BIT_SET_MGQ_PGBNDY_V1_8821C(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V1_8821C(x) | BIT_MGQ_PGBNDY_V1_8821C(v)) /* 2 REG_TXRPT_CTRL_8821C */ #define BIT_SHIFT_TRXRPT_TIMER_TH_8821C 24 #define BIT_MASK_TRXRPT_TIMER_TH_8821C 0xff -#define BIT_TRXRPT_TIMER_TH_8821C(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8821C) << BIT_SHIFT_TRXRPT_TIMER_TH_8821C) -#define BIT_GET_TRXRPT_TIMER_TH_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8821C) & BIT_MASK_TRXRPT_TIMER_TH_8821C) - - +#define BIT_TRXRPT_TIMER_TH_8821C(x) \ + (((x) & BIT_MASK_TRXRPT_TIMER_TH_8821C) \ + << BIT_SHIFT_TRXRPT_TIMER_TH_8821C) +#define BITS_TRXRPT_TIMER_TH_8821C \ + (BIT_MASK_TRXRPT_TIMER_TH_8821C << BIT_SHIFT_TRXRPT_TIMER_TH_8821C) +#define BIT_CLEAR_TRXRPT_TIMER_TH_8821C(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8821C)) +#define BIT_GET_TRXRPT_TIMER_TH_8821C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8821C) & \ + BIT_MASK_TRXRPT_TIMER_TH_8821C) +#define BIT_SET_TRXRPT_TIMER_TH_8821C(x, v) \ + (BIT_CLEAR_TRXRPT_TIMER_TH_8821C(x) | BIT_TRXRPT_TIMER_TH_8821C(v)) #define BIT_SHIFT_TRXRPT_LEN_TH_8821C 16 #define BIT_MASK_TRXRPT_LEN_TH_8821C 0xff -#define BIT_TRXRPT_LEN_TH_8821C(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8821C) << BIT_SHIFT_TRXRPT_LEN_TH_8821C) -#define BIT_GET_TRXRPT_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8821C) & BIT_MASK_TRXRPT_LEN_TH_8821C) - - +#define BIT_TRXRPT_LEN_TH_8821C(x) \ + (((x) & BIT_MASK_TRXRPT_LEN_TH_8821C) << BIT_SHIFT_TRXRPT_LEN_TH_8821C) +#define BITS_TRXRPT_LEN_TH_8821C \ + (BIT_MASK_TRXRPT_LEN_TH_8821C << BIT_SHIFT_TRXRPT_LEN_TH_8821C) +#define BIT_CLEAR_TRXRPT_LEN_TH_8821C(x) ((x) & (~BITS_TRXRPT_LEN_TH_8821C)) +#define BIT_GET_TRXRPT_LEN_TH_8821C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8821C) & BIT_MASK_TRXRPT_LEN_TH_8821C) +#define BIT_SET_TRXRPT_LEN_TH_8821C(x, v) \ + (BIT_CLEAR_TRXRPT_LEN_TH_8821C(x) | BIT_TRXRPT_LEN_TH_8821C(v)) #define BIT_SHIFT_TRXRPT_READ_PTR_8821C 8 #define BIT_MASK_TRXRPT_READ_PTR_8821C 0xff -#define BIT_TRXRPT_READ_PTR_8821C(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8821C) << BIT_SHIFT_TRXRPT_READ_PTR_8821C) -#define BIT_GET_TRXRPT_READ_PTR_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8821C) & BIT_MASK_TRXRPT_READ_PTR_8821C) - - +#define BIT_TRXRPT_READ_PTR_8821C(x) \ + (((x) & BIT_MASK_TRXRPT_READ_PTR_8821C) \ + << BIT_SHIFT_TRXRPT_READ_PTR_8821C) +#define BITS_TRXRPT_READ_PTR_8821C \ + (BIT_MASK_TRXRPT_READ_PTR_8821C << BIT_SHIFT_TRXRPT_READ_PTR_8821C) +#define BIT_CLEAR_TRXRPT_READ_PTR_8821C(x) ((x) & (~BITS_TRXRPT_READ_PTR_8821C)) +#define BIT_GET_TRXRPT_READ_PTR_8821C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8821C) & \ + BIT_MASK_TRXRPT_READ_PTR_8821C) +#define BIT_SET_TRXRPT_READ_PTR_8821C(x, v) \ + (BIT_CLEAR_TRXRPT_READ_PTR_8821C(x) | BIT_TRXRPT_READ_PTR_8821C(v)) #define BIT_SHIFT_TRXRPT_WRITE_PTR_8821C 0 #define BIT_MASK_TRXRPT_WRITE_PTR_8821C 0xff -#define BIT_TRXRPT_WRITE_PTR_8821C(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8821C) << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) -#define BIT_GET_TRXRPT_WRITE_PTR_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) & BIT_MASK_TRXRPT_WRITE_PTR_8821C) - - +#define BIT_TRXRPT_WRITE_PTR_8821C(x) \ + (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8821C) \ + << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) +#define BITS_TRXRPT_WRITE_PTR_8821C \ + (BIT_MASK_TRXRPT_WRITE_PTR_8821C << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) +#define BIT_CLEAR_TRXRPT_WRITE_PTR_8821C(x) \ + ((x) & (~BITS_TRXRPT_WRITE_PTR_8821C)) +#define BIT_GET_TRXRPT_WRITE_PTR_8821C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) & \ + BIT_MASK_TRXRPT_WRITE_PTR_8821C) +#define BIT_SET_TRXRPT_WRITE_PTR_8821C(x, v) \ + (BIT_CLEAR_TRXRPT_WRITE_PTR_8821C(x) | BIT_TRXRPT_WRITE_PTR_8821C(v)) /* 2 REG_INIRTS_RATE_SEL_8821C */ #define BIT_LEAG_RTS_BW_DUP_8821C BIT(5) @@ -6118,115 +10083,255 @@ #define BIT_SHIFT_BASIC_CFEND_RATE_8821C 0 #define BIT_MASK_BASIC_CFEND_RATE_8821C 0x1f -#define BIT_BASIC_CFEND_RATE_8821C(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8821C) << BIT_SHIFT_BASIC_CFEND_RATE_8821C) -#define BIT_GET_BASIC_CFEND_RATE_8821C(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8821C) & BIT_MASK_BASIC_CFEND_RATE_8821C) - - +#define BIT_BASIC_CFEND_RATE_8821C(x) \ + (((x) & BIT_MASK_BASIC_CFEND_RATE_8821C) \ + << BIT_SHIFT_BASIC_CFEND_RATE_8821C) +#define BITS_BASIC_CFEND_RATE_8821C \ + (BIT_MASK_BASIC_CFEND_RATE_8821C << BIT_SHIFT_BASIC_CFEND_RATE_8821C) +#define BIT_CLEAR_BASIC_CFEND_RATE_8821C(x) \ + ((x) & (~BITS_BASIC_CFEND_RATE_8821C)) +#define BIT_GET_BASIC_CFEND_RATE_8821C(x) \ + (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8821C) & \ + BIT_MASK_BASIC_CFEND_RATE_8821C) +#define BIT_SET_BASIC_CFEND_RATE_8821C(x, v) \ + (BIT_CLEAR_BASIC_CFEND_RATE_8821C(x) | BIT_BASIC_CFEND_RATE_8821C(v)) /* 2 REG_STBC_CFEND_RATE_8821C */ #define BIT_SHIFT_STBC_CFEND_RATE_8821C 0 #define BIT_MASK_STBC_CFEND_RATE_8821C 0x1f -#define BIT_STBC_CFEND_RATE_8821C(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8821C) << BIT_SHIFT_STBC_CFEND_RATE_8821C) -#define BIT_GET_STBC_CFEND_RATE_8821C(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8821C) & BIT_MASK_STBC_CFEND_RATE_8821C) - - +#define BIT_STBC_CFEND_RATE_8821C(x) \ + (((x) & BIT_MASK_STBC_CFEND_RATE_8821C) \ + << BIT_SHIFT_STBC_CFEND_RATE_8821C) +#define BITS_STBC_CFEND_RATE_8821C \ + (BIT_MASK_STBC_CFEND_RATE_8821C << BIT_SHIFT_STBC_CFEND_RATE_8821C) +#define BIT_CLEAR_STBC_CFEND_RATE_8821C(x) ((x) & (~BITS_STBC_CFEND_RATE_8821C)) +#define BIT_GET_STBC_CFEND_RATE_8821C(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8821C) & \ + BIT_MASK_STBC_CFEND_RATE_8821C) +#define BIT_SET_STBC_CFEND_RATE_8821C(x, v) \ + (BIT_CLEAR_STBC_CFEND_RATE_8821C(x) | BIT_STBC_CFEND_RATE_8821C(v)) /* 2 REG_DATA_SC_8821C */ #define BIT_SHIFT_TXSC_40M_8821C 4 #define BIT_MASK_TXSC_40M_8821C 0xf -#define BIT_TXSC_40M_8821C(x) (((x) & BIT_MASK_TXSC_40M_8821C) << BIT_SHIFT_TXSC_40M_8821C) -#define BIT_GET_TXSC_40M_8821C(x) (((x) >> BIT_SHIFT_TXSC_40M_8821C) & BIT_MASK_TXSC_40M_8821C) - - +#define BIT_TXSC_40M_8821C(x) \ + (((x) & BIT_MASK_TXSC_40M_8821C) << BIT_SHIFT_TXSC_40M_8821C) +#define BITS_TXSC_40M_8821C \ + (BIT_MASK_TXSC_40M_8821C << BIT_SHIFT_TXSC_40M_8821C) +#define BIT_CLEAR_TXSC_40M_8821C(x) ((x) & (~BITS_TXSC_40M_8821C)) +#define BIT_GET_TXSC_40M_8821C(x) \ + (((x) >> BIT_SHIFT_TXSC_40M_8821C) & BIT_MASK_TXSC_40M_8821C) +#define BIT_SET_TXSC_40M_8821C(x, v) \ + (BIT_CLEAR_TXSC_40M_8821C(x) | BIT_TXSC_40M_8821C(v)) #define BIT_SHIFT_TXSC_20M_8821C 0 #define BIT_MASK_TXSC_20M_8821C 0xf -#define BIT_TXSC_20M_8821C(x) (((x) & BIT_MASK_TXSC_20M_8821C) << BIT_SHIFT_TXSC_20M_8821C) -#define BIT_GET_TXSC_20M_8821C(x) (((x) >> BIT_SHIFT_TXSC_20M_8821C) & BIT_MASK_TXSC_20M_8821C) - - +#define BIT_TXSC_20M_8821C(x) \ + (((x) & BIT_MASK_TXSC_20M_8821C) << BIT_SHIFT_TXSC_20M_8821C) +#define BITS_TXSC_20M_8821C \ + (BIT_MASK_TXSC_20M_8821C << BIT_SHIFT_TXSC_20M_8821C) +#define BIT_CLEAR_TXSC_20M_8821C(x) ((x) & (~BITS_TXSC_20M_8821C)) +#define BIT_GET_TXSC_20M_8821C(x) \ + (((x) >> BIT_SHIFT_TXSC_20M_8821C) & BIT_MASK_TXSC_20M_8821C) +#define BIT_SET_TXSC_20M_8821C(x, v) \ + (BIT_CLEAR_TXSC_20M_8821C(x) | BIT_TXSC_20M_8821C(v)) /* 2 REG_MACID_SLEEP3_8821C */ #define BIT_SHIFT_MACID127_96_PKTSLEEP_8821C 0 #define BIT_MASK_MACID127_96_PKTSLEEP_8821C 0xffffffffL -#define BIT_MACID127_96_PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8821C) << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) -#define BIT_GET_MACID127_96_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) & BIT_MASK_MACID127_96_PKTSLEEP_8821C) - - +#define BIT_MACID127_96_PKTSLEEP_8821C(x) \ + (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8821C) \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) +#define BITS_MACID127_96_PKTSLEEP_8821C \ + (BIT_MASK_MACID127_96_PKTSLEEP_8821C \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) +#define BIT_CLEAR_MACID127_96_PKTSLEEP_8821C(x) \ + ((x) & (~BITS_MACID127_96_PKTSLEEP_8821C)) +#define BIT_GET_MACID127_96_PKTSLEEP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) & \ + BIT_MASK_MACID127_96_PKTSLEEP_8821C) +#define BIT_SET_MACID127_96_PKTSLEEP_8821C(x, v) \ + (BIT_CLEAR_MACID127_96_PKTSLEEP_8821C(x) | \ + BIT_MACID127_96_PKTSLEEP_8821C(v)) /* 2 REG_MACID_SLEEP1_8821C */ #define BIT_SHIFT_MACID63_32_PKTSLEEP_8821C 0 #define BIT_MASK_MACID63_32_PKTSLEEP_8821C 0xffffffffL -#define BIT_MACID63_32_PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8821C) << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) -#define BIT_GET_MACID63_32_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) & BIT_MASK_MACID63_32_PKTSLEEP_8821C) - - +#define BIT_MACID63_32_PKTSLEEP_8821C(x) \ + (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8821C) \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) +#define BITS_MACID63_32_PKTSLEEP_8821C \ + (BIT_MASK_MACID63_32_PKTSLEEP_8821C \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) +#define BIT_CLEAR_MACID63_32_PKTSLEEP_8821C(x) \ + ((x) & (~BITS_MACID63_32_PKTSLEEP_8821C)) +#define BIT_GET_MACID63_32_PKTSLEEP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) & \ + BIT_MASK_MACID63_32_PKTSLEEP_8821C) +#define BIT_SET_MACID63_32_PKTSLEEP_8821C(x, v) \ + (BIT_CLEAR_MACID63_32_PKTSLEEP_8821C(x) | \ + BIT_MACID63_32_PKTSLEEP_8821C(v)) /* 2 REG_ARFR2_V1_8821C */ -#define BIT_SHIFT_ARFR2_V1_8821C 0 -#define BIT_MASK_ARFR2_V1_8821C 0xffffffffffffffffL -#define BIT_ARFR2_V1_8821C(x) (((x) & BIT_MASK_ARFR2_V1_8821C) << BIT_SHIFT_ARFR2_V1_8821C) -#define BIT_GET_ARFR2_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR2_V1_8821C) & BIT_MASK_ARFR2_V1_8821C) - - +#define BIT_SHIFT_ARFRL2_8821C 0 +#define BIT_MASK_ARFRL2_8821C 0xffffffffL +#define BIT_ARFRL2_8821C(x) \ + (((x) & BIT_MASK_ARFRL2_8821C) << BIT_SHIFT_ARFRL2_8821C) +#define BITS_ARFRL2_8821C (BIT_MASK_ARFRL2_8821C << BIT_SHIFT_ARFRL2_8821C) +#define BIT_CLEAR_ARFRL2_8821C(x) ((x) & (~BITS_ARFRL2_8821C)) +#define BIT_GET_ARFRL2_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRL2_8821C) & BIT_MASK_ARFRL2_8821C) +#define BIT_SET_ARFRL2_8821C(x, v) \ + (BIT_CLEAR_ARFRL2_8821C(x) | BIT_ARFRL2_8821C(v)) + +/* 2 REG_ARFRH2_V1_8821C */ + +#define BIT_SHIFT_ARFRH2_8821C 0 +#define BIT_MASK_ARFRH2_8821C 0xffffffffL +#define BIT_ARFRH2_8821C(x) \ + (((x) & BIT_MASK_ARFRH2_8821C) << BIT_SHIFT_ARFRH2_8821C) +#define BITS_ARFRH2_8821C (BIT_MASK_ARFRH2_8821C << BIT_SHIFT_ARFRH2_8821C) +#define BIT_CLEAR_ARFRH2_8821C(x) ((x) & (~BITS_ARFRH2_8821C)) +#define BIT_GET_ARFRH2_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRH2_8821C) & BIT_MASK_ARFRH2_8821C) +#define BIT_SET_ARFRH2_8821C(x, v) \ + (BIT_CLEAR_ARFRH2_8821C(x) | BIT_ARFRH2_8821C(v)) /* 2 REG_ARFR3_V1_8821C */ -#define BIT_SHIFT_ARFR3_V1_8821C 0 -#define BIT_MASK_ARFR3_V1_8821C 0xffffffffffffffffL -#define BIT_ARFR3_V1_8821C(x) (((x) & BIT_MASK_ARFR3_V1_8821C) << BIT_SHIFT_ARFR3_V1_8821C) -#define BIT_GET_ARFR3_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR3_V1_8821C) & BIT_MASK_ARFR3_V1_8821C) - - +#define BIT_SHIFT_ARFRL3_8821C 0 +#define BIT_MASK_ARFRL3_8821C 0xffffffffL +#define BIT_ARFRL3_8821C(x) \ + (((x) & BIT_MASK_ARFRL3_8821C) << BIT_SHIFT_ARFRL3_8821C) +#define BITS_ARFRL3_8821C (BIT_MASK_ARFRL3_8821C << BIT_SHIFT_ARFRL3_8821C) +#define BIT_CLEAR_ARFRL3_8821C(x) ((x) & (~BITS_ARFRL3_8821C)) +#define BIT_GET_ARFRL3_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRL3_8821C) & BIT_MASK_ARFRL3_8821C) +#define BIT_SET_ARFRL3_8821C(x, v) \ + (BIT_CLEAR_ARFRL3_8821C(x) | BIT_ARFRL3_8821C(v)) + +/* 2 REG_ARFRH3_V1_8821C */ + +#define BIT_SHIFT_ARFRH3_8821C 0 +#define BIT_MASK_ARFRH3_8821C 0xffffffffL +#define BIT_ARFRH3_8821C(x) \ + (((x) & BIT_MASK_ARFRH3_8821C) << BIT_SHIFT_ARFRH3_8821C) +#define BITS_ARFRH3_8821C (BIT_MASK_ARFRH3_8821C << BIT_SHIFT_ARFRH3_8821C) +#define BIT_CLEAR_ARFRH3_8821C(x) ((x) & (~BITS_ARFRH3_8821C)) +#define BIT_GET_ARFRH3_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRH3_8821C) & BIT_MASK_ARFRH3_8821C) +#define BIT_SET_ARFRH3_8821C(x, v) \ + (BIT_CLEAR_ARFRH3_8821C(x) | BIT_ARFRH3_8821C(v)) /* 2 REG_ARFR4_8821C */ -#define BIT_SHIFT_ARFR4_8821C 0 -#define BIT_MASK_ARFR4_8821C 0xffffffffffffffffL -#define BIT_ARFR4_8821C(x) (((x) & BIT_MASK_ARFR4_8821C) << BIT_SHIFT_ARFR4_8821C) -#define BIT_GET_ARFR4_8821C(x) (((x) >> BIT_SHIFT_ARFR4_8821C) & BIT_MASK_ARFR4_8821C) - - +#define BIT_SHIFT_ARFRL4_8821C 0 +#define BIT_MASK_ARFRL4_8821C 0xffffffffL +#define BIT_ARFRL4_8821C(x) \ + (((x) & BIT_MASK_ARFRL4_8821C) << BIT_SHIFT_ARFRL4_8821C) +#define BITS_ARFRL4_8821C (BIT_MASK_ARFRL4_8821C << BIT_SHIFT_ARFRL4_8821C) +#define BIT_CLEAR_ARFRL4_8821C(x) ((x) & (~BITS_ARFRL4_8821C)) +#define BIT_GET_ARFRL4_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRL4_8821C) & BIT_MASK_ARFRL4_8821C) +#define BIT_SET_ARFRL4_8821C(x, v) \ + (BIT_CLEAR_ARFRL4_8821C(x) | BIT_ARFRL4_8821C(v)) + +/* 2 REG_ARFRH4_8821C */ + +#define BIT_SHIFT_ARFRH4_8821C 0 +#define BIT_MASK_ARFRH4_8821C 0xffffffffL +#define BIT_ARFRH4_8821C(x) \ + (((x) & BIT_MASK_ARFRH4_8821C) << BIT_SHIFT_ARFRH4_8821C) +#define BITS_ARFRH4_8821C (BIT_MASK_ARFRH4_8821C << BIT_SHIFT_ARFRH4_8821C) +#define BIT_CLEAR_ARFRH4_8821C(x) ((x) & (~BITS_ARFRH4_8821C)) +#define BIT_GET_ARFRH4_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRH4_8821C) & BIT_MASK_ARFRH4_8821C) +#define BIT_SET_ARFRH4_8821C(x, v) \ + (BIT_CLEAR_ARFRH4_8821C(x) | BIT_ARFRH4_8821C(v)) /* 2 REG_ARFR5_8821C */ -#define BIT_SHIFT_ARFR5_8821C 0 -#define BIT_MASK_ARFR5_8821C 0xffffffffffffffffL -#define BIT_ARFR5_8821C(x) (((x) & BIT_MASK_ARFR5_8821C) << BIT_SHIFT_ARFR5_8821C) -#define BIT_GET_ARFR5_8821C(x) (((x) >> BIT_SHIFT_ARFR5_8821C) & BIT_MASK_ARFR5_8821C) - - +#define BIT_SHIFT_ARFRL5_8821C 0 +#define BIT_MASK_ARFRL5_8821C 0xffffffffL +#define BIT_ARFRL5_8821C(x) \ + (((x) & BIT_MASK_ARFRL5_8821C) << BIT_SHIFT_ARFRL5_8821C) +#define BITS_ARFRL5_8821C (BIT_MASK_ARFRL5_8821C << BIT_SHIFT_ARFRL5_8821C) +#define BIT_CLEAR_ARFRL5_8821C(x) ((x) & (~BITS_ARFRL5_8821C)) +#define BIT_GET_ARFRL5_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRL5_8821C) & BIT_MASK_ARFRL5_8821C) +#define BIT_SET_ARFRL5_8821C(x, v) \ + (BIT_CLEAR_ARFRL5_8821C(x) | BIT_ARFRL5_8821C(v)) + +/* 2 REG_ARFRH5_8821C */ + +#define BIT_SHIFT_ARFRH5_8821C 0 +#define BIT_MASK_ARFRH5_8821C 0xffffffffL +#define BIT_ARFRH5_8821C(x) \ + (((x) & BIT_MASK_ARFRH5_8821C) << BIT_SHIFT_ARFRH5_8821C) +#define BITS_ARFRH5_8821C (BIT_MASK_ARFRH5_8821C << BIT_SHIFT_ARFRH5_8821C) +#define BIT_CLEAR_ARFRH5_8821C(x) ((x) & (~BITS_ARFRH5_8821C)) +#define BIT_GET_ARFRH5_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRH5_8821C) & BIT_MASK_ARFRH5_8821C) +#define BIT_SET_ARFRH5_8821C(x, v) \ + (BIT_CLEAR_ARFRH5_8821C(x) | BIT_ARFRH5_8821C(v)) /* 2 REG_TXRPT_START_OFFSET_8821C */ #define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C 24 #define BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C 0xff -#define BIT_R_MUTAB_TXRPT_OFFSET_8821C(x) (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) -#define BIT_GET_R_MUTAB_TXRPT_OFFSET_8821C(x) (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) - +#define BIT_R_MUTAB_TXRPT_OFFSET_8821C(x) \ + (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) \ + << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) +#define BITS_R_MUTAB_TXRPT_OFFSET_8821C \ + (BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C \ + << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) +#define BIT_CLEAR_R_MUTAB_TXRPT_OFFSET_8821C(x) \ + ((x) & (~BITS_R_MUTAB_TXRPT_OFFSET_8821C)) +#define BIT_GET_R_MUTAB_TXRPT_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) & \ + BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) +#define BIT_SET_R_MUTAB_TXRPT_OFFSET_8821C(x, v) \ + (BIT_CLEAR_R_MUTAB_TXRPT_OFFSET_8821C(x) | \ + BIT_R_MUTAB_TXRPT_OFFSET_8821C(v)) #define BIT__R_RPTFIFO_1K_8821C BIT(16) #define BIT_SHIFT_MACID_CTRL_OFFSET_8821C 8 #define BIT_MASK_MACID_CTRL_OFFSET_8821C 0xff -#define BIT_MACID_CTRL_OFFSET_8821C(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8821C) << BIT_SHIFT_MACID_CTRL_OFFSET_8821C) -#define BIT_GET_MACID_CTRL_OFFSET_8821C(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8821C) & BIT_MASK_MACID_CTRL_OFFSET_8821C) - - +#define BIT_MACID_CTRL_OFFSET_8821C(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET_8821C) \ + << BIT_SHIFT_MACID_CTRL_OFFSET_8821C) +#define BITS_MACID_CTRL_OFFSET_8821C \ + (BIT_MASK_MACID_CTRL_OFFSET_8821C << BIT_SHIFT_MACID_CTRL_OFFSET_8821C) +#define BIT_CLEAR_MACID_CTRL_OFFSET_8821C(x) \ + ((x) & (~BITS_MACID_CTRL_OFFSET_8821C)) +#define BIT_GET_MACID_CTRL_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8821C) & \ + BIT_MASK_MACID_CTRL_OFFSET_8821C) +#define BIT_SET_MACID_CTRL_OFFSET_8821C(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET_8821C(x) | BIT_MACID_CTRL_OFFSET_8821C(v)) #define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C 0 #define BIT_MASK_AMPDU_TXRPT_OFFSET_8821C 0xff -#define BIT_AMPDU_TXRPT_OFFSET_8821C(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) -#define BIT_GET_AMPDU_TXRPT_OFFSET_8821C(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_AMPDU_TXRPT_OFFSET_8821C(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) +#define BITS_AMPDU_TXRPT_OFFSET_8821C \ + (BIT_MASK_AMPDU_TXRPT_OFFSET_8821C \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8821C(x) \ + ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8821C)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) & \ + BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) +#define BIT_SET_AMPDU_TXRPT_OFFSET_8821C(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8821C(x) | \ + BIT_AMPDU_TXRPT_OFFSET_8821C(v)) /* 2 REG_POWER_STAGE1_8821C */ #define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8821C BIT(31) @@ -6240,28 +10345,44 @@ #define BIT_SHIFT_POWER_STAGE1_8821C 0 #define BIT_MASK_POWER_STAGE1_8821C 0xffffff -#define BIT_POWER_STAGE1_8821C(x) (((x) & BIT_MASK_POWER_STAGE1_8821C) << BIT_SHIFT_POWER_STAGE1_8821C) -#define BIT_GET_POWER_STAGE1_8821C(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8821C) & BIT_MASK_POWER_STAGE1_8821C) - - +#define BIT_POWER_STAGE1_8821C(x) \ + (((x) & BIT_MASK_POWER_STAGE1_8821C) << BIT_SHIFT_POWER_STAGE1_8821C) +#define BITS_POWER_STAGE1_8821C \ + (BIT_MASK_POWER_STAGE1_8821C << BIT_SHIFT_POWER_STAGE1_8821C) +#define BIT_CLEAR_POWER_STAGE1_8821C(x) ((x) & (~BITS_POWER_STAGE1_8821C)) +#define BIT_GET_POWER_STAGE1_8821C(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1_8821C) & BIT_MASK_POWER_STAGE1_8821C) +#define BIT_SET_POWER_STAGE1_8821C(x, v) \ + (BIT_CLEAR_POWER_STAGE1_8821C(x) | BIT_POWER_STAGE1_8821C(v)) /* 2 REG_POWER_STAGE2_8821C */ #define BIT__R_CTRL_PKT_POW_ADJ_8821C BIT(24) #define BIT_SHIFT_POWER_STAGE2_8821C 0 #define BIT_MASK_POWER_STAGE2_8821C 0xffffff -#define BIT_POWER_STAGE2_8821C(x) (((x) & BIT_MASK_POWER_STAGE2_8821C) << BIT_SHIFT_POWER_STAGE2_8821C) -#define BIT_GET_POWER_STAGE2_8821C(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8821C) & BIT_MASK_POWER_STAGE2_8821C) - - +#define BIT_POWER_STAGE2_8821C(x) \ + (((x) & BIT_MASK_POWER_STAGE2_8821C) << BIT_SHIFT_POWER_STAGE2_8821C) +#define BITS_POWER_STAGE2_8821C \ + (BIT_MASK_POWER_STAGE2_8821C << BIT_SHIFT_POWER_STAGE2_8821C) +#define BIT_CLEAR_POWER_STAGE2_8821C(x) ((x) & (~BITS_POWER_STAGE2_8821C)) +#define BIT_GET_POWER_STAGE2_8821C(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2_8821C) & BIT_MASK_POWER_STAGE2_8821C) +#define BIT_SET_POWER_STAGE2_8821C(x, v) \ + (BIT_CLEAR_POWER_STAGE2_8821C(x) | BIT_POWER_STAGE2_8821C(v)) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8821C */ #define BIT_SHIFT_PAD_NUM_THRES_8821C 24 #define BIT_MASK_PAD_NUM_THRES_8821C 0x3f -#define BIT_PAD_NUM_THRES_8821C(x) (((x) & BIT_MASK_PAD_NUM_THRES_8821C) << BIT_SHIFT_PAD_NUM_THRES_8821C) -#define BIT_GET_PAD_NUM_THRES_8821C(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8821C) & BIT_MASK_PAD_NUM_THRES_8821C) - +#define BIT_PAD_NUM_THRES_8821C(x) \ + (((x) & BIT_MASK_PAD_NUM_THRES_8821C) << BIT_SHIFT_PAD_NUM_THRES_8821C) +#define BITS_PAD_NUM_THRES_8821C \ + (BIT_MASK_PAD_NUM_THRES_8821C << BIT_SHIFT_PAD_NUM_THRES_8821C) +#define BIT_CLEAR_PAD_NUM_THRES_8821C(x) ((x) & (~BITS_PAD_NUM_THRES_8821C)) +#define BIT_GET_PAD_NUM_THRES_8821C(x) \ + (((x) >> BIT_SHIFT_PAD_NUM_THRES_8821C) & BIT_MASK_PAD_NUM_THRES_8821C) +#define BIT_SET_PAD_NUM_THRES_8821C(x, v) \ + (BIT_CLEAR_PAD_NUM_THRES_8821C(x) | BIT_PAD_NUM_THRES_8821C(v)) #define BIT_R_DMA_THIS_QUEUE_BK_8821C BIT(23) #define BIT_R_DMA_THIS_QUEUE_BE_8821C BIT(22) @@ -6270,18 +10391,32 @@ #define BIT_SHIFT_R_TOTAL_LEN_TH_8821C 8 #define BIT_MASK_R_TOTAL_LEN_TH_8821C 0xfff -#define BIT_R_TOTAL_LEN_TH_8821C(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8821C) << BIT_SHIFT_R_TOTAL_LEN_TH_8821C) -#define BIT_GET_R_TOTAL_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8821C) & BIT_MASK_R_TOTAL_LEN_TH_8821C) - +#define BIT_R_TOTAL_LEN_TH_8821C(x) \ + (((x) & BIT_MASK_R_TOTAL_LEN_TH_8821C) \ + << BIT_SHIFT_R_TOTAL_LEN_TH_8821C) +#define BITS_R_TOTAL_LEN_TH_8821C \ + (BIT_MASK_R_TOTAL_LEN_TH_8821C << BIT_SHIFT_R_TOTAL_LEN_TH_8821C) +#define BIT_CLEAR_R_TOTAL_LEN_TH_8821C(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8821C)) +#define BIT_GET_R_TOTAL_LEN_TH_8821C(x) \ + (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8821C) & \ + BIT_MASK_R_TOTAL_LEN_TH_8821C) +#define BIT_SET_R_TOTAL_LEN_TH_8821C(x, v) \ + (BIT_CLEAR_R_TOTAL_LEN_TH_8821C(x) | BIT_R_TOTAL_LEN_TH_8821C(v)) #define BIT_EN_NEW_EARLY_8821C BIT(7) #define BIT_PRE_TX_CMD_8821C BIT(6) #define BIT_SHIFT_NUM_SCL_EN_8821C 4 #define BIT_MASK_NUM_SCL_EN_8821C 0x3 -#define BIT_NUM_SCL_EN_8821C(x) (((x) & BIT_MASK_NUM_SCL_EN_8821C) << BIT_SHIFT_NUM_SCL_EN_8821C) -#define BIT_GET_NUM_SCL_EN_8821C(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8821C) & BIT_MASK_NUM_SCL_EN_8821C) - +#define BIT_NUM_SCL_EN_8821C(x) \ + (((x) & BIT_MASK_NUM_SCL_EN_8821C) << BIT_SHIFT_NUM_SCL_EN_8821C) +#define BITS_NUM_SCL_EN_8821C \ + (BIT_MASK_NUM_SCL_EN_8821C << BIT_SHIFT_NUM_SCL_EN_8821C) +#define BIT_CLEAR_NUM_SCL_EN_8821C(x) ((x) & (~BITS_NUM_SCL_EN_8821C)) +#define BIT_GET_NUM_SCL_EN_8821C(x) \ + (((x) >> BIT_SHIFT_NUM_SCL_EN_8821C) & BIT_MASK_NUM_SCL_EN_8821C) +#define BIT_SET_NUM_SCL_EN_8821C(x, v) \ + (BIT_CLEAR_NUM_SCL_EN_8821C(x) | BIT_NUM_SCL_EN_8821C(v)) #define BIT_BK_EN_8821C BIT(3) #define BIT_BE_EN_8821C BIT(2) @@ -6292,49 +10427,86 @@ #define BIT_SHIFT_PKT_LIFTIME_BEBK_8821C 16 #define BIT_MASK_PKT_LIFTIME_BEBK_8821C 0xffff -#define BIT_PKT_LIFTIME_BEBK_8821C(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8821C) << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) -#define BIT_GET_PKT_LIFTIME_BEBK_8821C(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) & BIT_MASK_PKT_LIFTIME_BEBK_8821C) - - +#define BIT_PKT_LIFTIME_BEBK_8821C(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8821C) \ + << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) +#define BITS_PKT_LIFTIME_BEBK_8821C \ + (BIT_MASK_PKT_LIFTIME_BEBK_8821C << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) +#define BIT_CLEAR_PKT_LIFTIME_BEBK_8821C(x) \ + ((x) & (~BITS_PKT_LIFTIME_BEBK_8821C)) +#define BIT_GET_PKT_LIFTIME_BEBK_8821C(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) & \ + BIT_MASK_PKT_LIFTIME_BEBK_8821C) +#define BIT_SET_PKT_LIFTIME_BEBK_8821C(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_BEBK_8821C(x) | BIT_PKT_LIFTIME_BEBK_8821C(v)) #define BIT_SHIFT_PKT_LIFTIME_VOVI_8821C 0 #define BIT_MASK_PKT_LIFTIME_VOVI_8821C 0xffff -#define BIT_PKT_LIFTIME_VOVI_8821C(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8821C) << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) -#define BIT_GET_PKT_LIFTIME_VOVI_8821C(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) & BIT_MASK_PKT_LIFTIME_VOVI_8821C) - - +#define BIT_PKT_LIFTIME_VOVI_8821C(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8821C) \ + << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) +#define BITS_PKT_LIFTIME_VOVI_8821C \ + (BIT_MASK_PKT_LIFTIME_VOVI_8821C << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) +#define BIT_CLEAR_PKT_LIFTIME_VOVI_8821C(x) \ + ((x) & (~BITS_PKT_LIFTIME_VOVI_8821C)) +#define BIT_GET_PKT_LIFTIME_VOVI_8821C(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) & \ + BIT_MASK_PKT_LIFTIME_VOVI_8821C) +#define BIT_SET_PKT_LIFTIME_VOVI_8821C(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_VOVI_8821C(x) | BIT_PKT_LIFTIME_VOVI_8821C(v)) /* 2 REG_STBC_SETTING_8821C */ #define BIT_SHIFT_CDEND_TXTIME_L_8821C 4 #define BIT_MASK_CDEND_TXTIME_L_8821C 0xf -#define BIT_CDEND_TXTIME_L_8821C(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8821C) << BIT_SHIFT_CDEND_TXTIME_L_8821C) -#define BIT_GET_CDEND_TXTIME_L_8821C(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8821C) & BIT_MASK_CDEND_TXTIME_L_8821C) - - +#define BIT_CDEND_TXTIME_L_8821C(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_L_8821C) \ + << BIT_SHIFT_CDEND_TXTIME_L_8821C) +#define BITS_CDEND_TXTIME_L_8821C \ + (BIT_MASK_CDEND_TXTIME_L_8821C << BIT_SHIFT_CDEND_TXTIME_L_8821C) +#define BIT_CLEAR_CDEND_TXTIME_L_8821C(x) ((x) & (~BITS_CDEND_TXTIME_L_8821C)) +#define BIT_GET_CDEND_TXTIME_L_8821C(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8821C) & \ + BIT_MASK_CDEND_TXTIME_L_8821C) +#define BIT_SET_CDEND_TXTIME_L_8821C(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_L_8821C(x) | BIT_CDEND_TXTIME_L_8821C(v)) #define BIT_SHIFT_NESS_8821C 2 #define BIT_MASK_NESS_8821C 0x3 #define BIT_NESS_8821C(x) (((x) & BIT_MASK_NESS_8821C) << BIT_SHIFT_NESS_8821C) -#define BIT_GET_NESS_8821C(x) (((x) >> BIT_SHIFT_NESS_8821C) & BIT_MASK_NESS_8821C) - - +#define BITS_NESS_8821C (BIT_MASK_NESS_8821C << BIT_SHIFT_NESS_8821C) +#define BIT_CLEAR_NESS_8821C(x) ((x) & (~BITS_NESS_8821C)) +#define BIT_GET_NESS_8821C(x) \ + (((x) >> BIT_SHIFT_NESS_8821C) & BIT_MASK_NESS_8821C) +#define BIT_SET_NESS_8821C(x, v) (BIT_CLEAR_NESS_8821C(x) | BIT_NESS_8821C(v)) #define BIT_SHIFT_STBC_CFEND_8821C 0 #define BIT_MASK_STBC_CFEND_8821C 0x3 -#define BIT_STBC_CFEND_8821C(x) (((x) & BIT_MASK_STBC_CFEND_8821C) << BIT_SHIFT_STBC_CFEND_8821C) -#define BIT_GET_STBC_CFEND_8821C(x) (((x) >> BIT_SHIFT_STBC_CFEND_8821C) & BIT_MASK_STBC_CFEND_8821C) - - +#define BIT_STBC_CFEND_8821C(x) \ + (((x) & BIT_MASK_STBC_CFEND_8821C) << BIT_SHIFT_STBC_CFEND_8821C) +#define BITS_STBC_CFEND_8821C \ + (BIT_MASK_STBC_CFEND_8821C << BIT_SHIFT_STBC_CFEND_8821C) +#define BIT_CLEAR_STBC_CFEND_8821C(x) ((x) & (~BITS_STBC_CFEND_8821C)) +#define BIT_GET_STBC_CFEND_8821C(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_8821C) & BIT_MASK_STBC_CFEND_8821C) +#define BIT_SET_STBC_CFEND_8821C(x, v) \ + (BIT_CLEAR_STBC_CFEND_8821C(x) | BIT_STBC_CFEND_8821C(v)) /* 2 REG_STBC_SETTING2_8821C */ #define BIT_SHIFT_CDEND_TXTIME_H_8821C 0 #define BIT_MASK_CDEND_TXTIME_H_8821C 0x1f -#define BIT_CDEND_TXTIME_H_8821C(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8821C) << BIT_SHIFT_CDEND_TXTIME_H_8821C) -#define BIT_GET_CDEND_TXTIME_H_8821C(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8821C) & BIT_MASK_CDEND_TXTIME_H_8821C) - - +#define BIT_CDEND_TXTIME_H_8821C(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_H_8821C) \ + << BIT_SHIFT_CDEND_TXTIME_H_8821C) +#define BITS_CDEND_TXTIME_H_8821C \ + (BIT_MASK_CDEND_TXTIME_H_8821C << BIT_SHIFT_CDEND_TXTIME_H_8821C) +#define BIT_CLEAR_CDEND_TXTIME_H_8821C(x) ((x) & (~BITS_CDEND_TXTIME_H_8821C)) +#define BIT_GET_CDEND_TXTIME_H_8821C(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8821C) & \ + BIT_MASK_CDEND_TXTIME_H_8821C) +#define BIT_SET_CDEND_TXTIME_H_8821C(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_H_8821C(x) | BIT_CDEND_TXTIME_H_8821C(v)) /* 2 REG_QUEUE_CTRL_8821C */ #define BIT_PTA_EDCCA_EN_8821C BIT(5) @@ -6351,126 +10523,241 @@ #define BIT_SHIFT_RTS_MAX_AGG_NUM_8821C 24 #define BIT_MASK_RTS_MAX_AGG_NUM_8821C 0x3f -#define BIT_RTS_MAX_AGG_NUM_8821C(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8821C) << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) -#define BIT_GET_RTS_MAX_AGG_NUM_8821C(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) & BIT_MASK_RTS_MAX_AGG_NUM_8821C) - - +#define BIT_RTS_MAX_AGG_NUM_8821C(x) \ + (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8821C) \ + << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) +#define BITS_RTS_MAX_AGG_NUM_8821C \ + (BIT_MASK_RTS_MAX_AGG_NUM_8821C << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) +#define BIT_CLEAR_RTS_MAX_AGG_NUM_8821C(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8821C)) +#define BIT_GET_RTS_MAX_AGG_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) & \ + BIT_MASK_RTS_MAX_AGG_NUM_8821C) +#define BIT_SET_RTS_MAX_AGG_NUM_8821C(x, v) \ + (BIT_CLEAR_RTS_MAX_AGG_NUM_8821C(x) | BIT_RTS_MAX_AGG_NUM_8821C(v)) #define BIT_SHIFT_MAX_AGG_NUM_8821C 16 #define BIT_MASK_MAX_AGG_NUM_8821C 0x3f -#define BIT_MAX_AGG_NUM_8821C(x) (((x) & BIT_MASK_MAX_AGG_NUM_8821C) << BIT_SHIFT_MAX_AGG_NUM_8821C) -#define BIT_GET_MAX_AGG_NUM_8821C(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8821C) & BIT_MASK_MAX_AGG_NUM_8821C) - - +#define BIT_MAX_AGG_NUM_8821C(x) \ + (((x) & BIT_MASK_MAX_AGG_NUM_8821C) << BIT_SHIFT_MAX_AGG_NUM_8821C) +#define BITS_MAX_AGG_NUM_8821C \ + (BIT_MASK_MAX_AGG_NUM_8821C << BIT_SHIFT_MAX_AGG_NUM_8821C) +#define BIT_CLEAR_MAX_AGG_NUM_8821C(x) ((x) & (~BITS_MAX_AGG_NUM_8821C)) +#define BIT_GET_MAX_AGG_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_MAX_AGG_NUM_8821C) & BIT_MASK_MAX_AGG_NUM_8821C) +#define BIT_SET_MAX_AGG_NUM_8821C(x, v) \ + (BIT_CLEAR_MAX_AGG_NUM_8821C(x) | BIT_MAX_AGG_NUM_8821C(v)) #define BIT_SHIFT_RTS_TXTIME_TH_8821C 8 #define BIT_MASK_RTS_TXTIME_TH_8821C 0xff -#define BIT_RTS_TXTIME_TH_8821C(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8821C) << BIT_SHIFT_RTS_TXTIME_TH_8821C) -#define BIT_GET_RTS_TXTIME_TH_8821C(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8821C) & BIT_MASK_RTS_TXTIME_TH_8821C) - - +#define BIT_RTS_TXTIME_TH_8821C(x) \ + (((x) & BIT_MASK_RTS_TXTIME_TH_8821C) << BIT_SHIFT_RTS_TXTIME_TH_8821C) +#define BITS_RTS_TXTIME_TH_8821C \ + (BIT_MASK_RTS_TXTIME_TH_8821C << BIT_SHIFT_RTS_TXTIME_TH_8821C) +#define BIT_CLEAR_RTS_TXTIME_TH_8821C(x) ((x) & (~BITS_RTS_TXTIME_TH_8821C)) +#define BIT_GET_RTS_TXTIME_TH_8821C(x) \ + (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8821C) & BIT_MASK_RTS_TXTIME_TH_8821C) +#define BIT_SET_RTS_TXTIME_TH_8821C(x, v) \ + (BIT_CLEAR_RTS_TXTIME_TH_8821C(x) | BIT_RTS_TXTIME_TH_8821C(v)) #define BIT_SHIFT_RTS_LEN_TH_8821C 0 #define BIT_MASK_RTS_LEN_TH_8821C 0xff -#define BIT_RTS_LEN_TH_8821C(x) (((x) & BIT_MASK_RTS_LEN_TH_8821C) << BIT_SHIFT_RTS_LEN_TH_8821C) -#define BIT_GET_RTS_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8821C) & BIT_MASK_RTS_LEN_TH_8821C) - - +#define BIT_RTS_LEN_TH_8821C(x) \ + (((x) & BIT_MASK_RTS_LEN_TH_8821C) << BIT_SHIFT_RTS_LEN_TH_8821C) +#define BITS_RTS_LEN_TH_8821C \ + (BIT_MASK_RTS_LEN_TH_8821C << BIT_SHIFT_RTS_LEN_TH_8821C) +#define BIT_CLEAR_RTS_LEN_TH_8821C(x) ((x) & (~BITS_RTS_LEN_TH_8821C)) +#define BIT_GET_RTS_LEN_TH_8821C(x) \ + (((x) >> BIT_SHIFT_RTS_LEN_TH_8821C) & BIT_MASK_RTS_LEN_TH_8821C) +#define BIT_SET_RTS_LEN_TH_8821C(x, v) \ + (BIT_CLEAR_RTS_LEN_TH_8821C(x) | BIT_RTS_LEN_TH_8821C(v)) /* 2 REG_BAR_MODE_CTRL_8821C */ #define BIT_SHIFT_BAR_RTY_LMT_8821C 16 #define BIT_MASK_BAR_RTY_LMT_8821C 0x3 -#define BIT_BAR_RTY_LMT_8821C(x) (((x) & BIT_MASK_BAR_RTY_LMT_8821C) << BIT_SHIFT_BAR_RTY_LMT_8821C) -#define BIT_GET_BAR_RTY_LMT_8821C(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8821C) & BIT_MASK_BAR_RTY_LMT_8821C) - - +#define BIT_BAR_RTY_LMT_8821C(x) \ + (((x) & BIT_MASK_BAR_RTY_LMT_8821C) << BIT_SHIFT_BAR_RTY_LMT_8821C) +#define BITS_BAR_RTY_LMT_8821C \ + (BIT_MASK_BAR_RTY_LMT_8821C << BIT_SHIFT_BAR_RTY_LMT_8821C) +#define BIT_CLEAR_BAR_RTY_LMT_8821C(x) ((x) & (~BITS_BAR_RTY_LMT_8821C)) +#define BIT_GET_BAR_RTY_LMT_8821C(x) \ + (((x) >> BIT_SHIFT_BAR_RTY_LMT_8821C) & BIT_MASK_BAR_RTY_LMT_8821C) +#define BIT_SET_BAR_RTY_LMT_8821C(x, v) \ + (BIT_CLEAR_BAR_RTY_LMT_8821C(x) | BIT_BAR_RTY_LMT_8821C(v)) #define BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C 8 #define BIT_MASK_BAR_PKT_TXTIME_TH_8821C 0xff -#define BIT_BAR_PKT_TXTIME_TH_8821C(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) -#define BIT_GET_BAR_PKT_TXTIME_TH_8821C(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C) - +#define BIT_BAR_PKT_TXTIME_TH_8821C(x) \ + (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C) \ + << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) +#define BITS_BAR_PKT_TXTIME_TH_8821C \ + (BIT_MASK_BAR_PKT_TXTIME_TH_8821C << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8821C(x) \ + ((x) & (~BITS_BAR_PKT_TXTIME_TH_8821C)) +#define BIT_GET_BAR_PKT_TXTIME_TH_8821C(x) \ + (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) & \ + BIT_MASK_BAR_PKT_TXTIME_TH_8821C) +#define BIT_SET_BAR_PKT_TXTIME_TH_8821C(x, v) \ + (BIT_CLEAR_BAR_PKT_TXTIME_TH_8821C(x) | BIT_BAR_PKT_TXTIME_TH_8821C(v)) #define BIT_BAR_EN_V1_8821C BIT(6) #define BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C 0 #define BIT_MASK_BAR_PKTNUM_TH_V1_8821C 0x3f -#define BIT_BAR_PKTNUM_TH_V1_8821C(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) -#define BIT_GET_BAR_PKTNUM_TH_V1_8821C(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C) - - +#define BIT_BAR_PKTNUM_TH_V1_8821C(x) \ + (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C) \ + << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) +#define BITS_BAR_PKTNUM_TH_V1_8821C \ + (BIT_MASK_BAR_PKTNUM_TH_V1_8821C << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8821C(x) \ + ((x) & (~BITS_BAR_PKTNUM_TH_V1_8821C)) +#define BIT_GET_BAR_PKTNUM_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) & \ + BIT_MASK_BAR_PKTNUM_TH_V1_8821C) +#define BIT_SET_BAR_PKTNUM_TH_V1_8821C(x, v) \ + (BIT_CLEAR_BAR_PKTNUM_TH_V1_8821C(x) | BIT_BAR_PKTNUM_TH_V1_8821C(v)) /* 2 REG_RA_TRY_RATE_AGG_LMT_8821C */ #define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C 0 #define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C 0x3f -#define BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) -#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8821C(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) - - +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) +#define BITS_RA_TRY_RATE_AGG_LMT_V1_8821C \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8821C(x) \ + ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8821C)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) & \ + BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8821C(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8821C(x) | \ + BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(v)) /* 2 REG_MACID_SLEEP2_8821C */ #define BIT_SHIFT_MACID95_64PKTSLEEP_8821C 0 #define BIT_MASK_MACID95_64PKTSLEEP_8821C 0xffffffffL -#define BIT_MACID95_64PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8821C) << BIT_SHIFT_MACID95_64PKTSLEEP_8821C) -#define BIT_GET_MACID95_64PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8821C) & BIT_MASK_MACID95_64PKTSLEEP_8821C) - - +#define BIT_MACID95_64PKTSLEEP_8821C(x) \ + (((x) & BIT_MASK_MACID95_64PKTSLEEP_8821C) \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8821C) +#define BITS_MACID95_64PKTSLEEP_8821C \ + (BIT_MASK_MACID95_64PKTSLEEP_8821C \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8821C) +#define BIT_CLEAR_MACID95_64PKTSLEEP_8821C(x) \ + ((x) & (~BITS_MACID95_64PKTSLEEP_8821C)) +#define BIT_GET_MACID95_64PKTSLEEP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8821C) & \ + BIT_MASK_MACID95_64PKTSLEEP_8821C) +#define BIT_SET_MACID95_64PKTSLEEP_8821C(x, v) \ + (BIT_CLEAR_MACID95_64PKTSLEEP_8821C(x) | \ + BIT_MACID95_64PKTSLEEP_8821C(v)) /* 2 REG_MACID_SLEEP_8821C */ #define BIT_SHIFT_MACID31_0_PKTSLEEP_8821C 0 #define BIT_MASK_MACID31_0_PKTSLEEP_8821C 0xffffffffL -#define BIT_MACID31_0_PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8821C) << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) -#define BIT_GET_MACID31_0_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) & BIT_MASK_MACID31_0_PKTSLEEP_8821C) - - +#define BIT_MACID31_0_PKTSLEEP_8821C(x) \ + (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8821C) \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) +#define BITS_MACID31_0_PKTSLEEP_8821C \ + (BIT_MASK_MACID31_0_PKTSLEEP_8821C \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) +#define BIT_CLEAR_MACID31_0_PKTSLEEP_8821C(x) \ + ((x) & (~BITS_MACID31_0_PKTSLEEP_8821C)) +#define BIT_GET_MACID31_0_PKTSLEEP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) & \ + BIT_MASK_MACID31_0_PKTSLEEP_8821C) +#define BIT_SET_MACID31_0_PKTSLEEP_8821C(x, v) \ + (BIT_CLEAR_MACID31_0_PKTSLEEP_8821C(x) | \ + BIT_MACID31_0_PKTSLEEP_8821C(v)) /* 2 REG_HW_SEQ0_8821C */ #define BIT_SHIFT_HW_SSN_SEQ0_8821C 0 #define BIT_MASK_HW_SSN_SEQ0_8821C 0xfff -#define BIT_HW_SSN_SEQ0_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8821C) << BIT_SHIFT_HW_SSN_SEQ0_8821C) -#define BIT_GET_HW_SSN_SEQ0_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8821C) & BIT_MASK_HW_SSN_SEQ0_8821C) - - +#define BIT_HW_SSN_SEQ0_8821C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ0_8821C) << BIT_SHIFT_HW_SSN_SEQ0_8821C) +#define BITS_HW_SSN_SEQ0_8821C \ + (BIT_MASK_HW_SSN_SEQ0_8821C << BIT_SHIFT_HW_SSN_SEQ0_8821C) +#define BIT_CLEAR_HW_SSN_SEQ0_8821C(x) ((x) & (~BITS_HW_SSN_SEQ0_8821C)) +#define BIT_GET_HW_SSN_SEQ0_8821C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8821C) & BIT_MASK_HW_SSN_SEQ0_8821C) +#define BIT_SET_HW_SSN_SEQ0_8821C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ0_8821C(x) | BIT_HW_SSN_SEQ0_8821C(v)) /* 2 REG_HW_SEQ1_8821C */ #define BIT_SHIFT_HW_SSN_SEQ1_8821C 0 #define BIT_MASK_HW_SSN_SEQ1_8821C 0xfff -#define BIT_HW_SSN_SEQ1_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8821C) << BIT_SHIFT_HW_SSN_SEQ1_8821C) -#define BIT_GET_HW_SSN_SEQ1_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8821C) & BIT_MASK_HW_SSN_SEQ1_8821C) - - +#define BIT_HW_SSN_SEQ1_8821C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ1_8821C) << BIT_SHIFT_HW_SSN_SEQ1_8821C) +#define BITS_HW_SSN_SEQ1_8821C \ + (BIT_MASK_HW_SSN_SEQ1_8821C << BIT_SHIFT_HW_SSN_SEQ1_8821C) +#define BIT_CLEAR_HW_SSN_SEQ1_8821C(x) ((x) & (~BITS_HW_SSN_SEQ1_8821C)) +#define BIT_GET_HW_SSN_SEQ1_8821C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8821C) & BIT_MASK_HW_SSN_SEQ1_8821C) +#define BIT_SET_HW_SSN_SEQ1_8821C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ1_8821C(x) | BIT_HW_SSN_SEQ1_8821C(v)) /* 2 REG_HW_SEQ2_8821C */ #define BIT_SHIFT_HW_SSN_SEQ2_8821C 0 #define BIT_MASK_HW_SSN_SEQ2_8821C 0xfff -#define BIT_HW_SSN_SEQ2_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8821C) << BIT_SHIFT_HW_SSN_SEQ2_8821C) -#define BIT_GET_HW_SSN_SEQ2_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8821C) & BIT_MASK_HW_SSN_SEQ2_8821C) - - +#define BIT_HW_SSN_SEQ2_8821C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ2_8821C) << BIT_SHIFT_HW_SSN_SEQ2_8821C) +#define BITS_HW_SSN_SEQ2_8821C \ + (BIT_MASK_HW_SSN_SEQ2_8821C << BIT_SHIFT_HW_SSN_SEQ2_8821C) +#define BIT_CLEAR_HW_SSN_SEQ2_8821C(x) ((x) & (~BITS_HW_SSN_SEQ2_8821C)) +#define BIT_GET_HW_SSN_SEQ2_8821C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8821C) & BIT_MASK_HW_SSN_SEQ2_8821C) +#define BIT_SET_HW_SSN_SEQ2_8821C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ2_8821C(x) | BIT_HW_SSN_SEQ2_8821C(v)) /* 2 REG_HW_SEQ3_8821C */ +#define BIT_SHIFT_CSI_HWSEQ_SEL_8821C 12 +#define BIT_MASK_CSI_HWSEQ_SEL_8821C 0x3 +#define BIT_CSI_HWSEQ_SEL_8821C(x) \ + (((x) & BIT_MASK_CSI_HWSEQ_SEL_8821C) << BIT_SHIFT_CSI_HWSEQ_SEL_8821C) +#define BITS_CSI_HWSEQ_SEL_8821C \ + (BIT_MASK_CSI_HWSEQ_SEL_8821C << BIT_SHIFT_CSI_HWSEQ_SEL_8821C) +#define BIT_CLEAR_CSI_HWSEQ_SEL_8821C(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8821C)) +#define BIT_GET_CSI_HWSEQ_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8821C) & BIT_MASK_CSI_HWSEQ_SEL_8821C) +#define BIT_SET_CSI_HWSEQ_SEL_8821C(x, v) \ + (BIT_CLEAR_CSI_HWSEQ_SEL_8821C(x) | BIT_CSI_HWSEQ_SEL_8821C(v)) + #define BIT_SHIFT_HW_SSN_SEQ3_8821C 0 #define BIT_MASK_HW_SSN_SEQ3_8821C 0xfff -#define BIT_HW_SSN_SEQ3_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8821C) << BIT_SHIFT_HW_SSN_SEQ3_8821C) -#define BIT_GET_HW_SSN_SEQ3_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8821C) & BIT_MASK_HW_SSN_SEQ3_8821C) - - +#define BIT_HW_SSN_SEQ3_8821C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ3_8821C) << BIT_SHIFT_HW_SSN_SEQ3_8821C) +#define BITS_HW_SSN_SEQ3_8821C \ + (BIT_MASK_HW_SSN_SEQ3_8821C << BIT_SHIFT_HW_SSN_SEQ3_8821C) +#define BIT_CLEAR_HW_SSN_SEQ3_8821C(x) ((x) & (~BITS_HW_SSN_SEQ3_8821C)) +#define BIT_GET_HW_SSN_SEQ3_8821C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8821C) & BIT_MASK_HW_SSN_SEQ3_8821C) +#define BIT_SET_HW_SSN_SEQ3_8821C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ3_8821C(x) | BIT_HW_SSN_SEQ3_8821C(v)) /* 2 REG_NULL_PKT_STATUS_V1_8821C */ #define BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C 2 #define BIT_MASK_PTCL_TOTAL_PG_V2_8821C 0x3fff -#define BIT_PTCL_TOTAL_PG_V2_8821C(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C) << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) -#define BIT_GET_PTCL_TOTAL_PG_V2_8821C(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C) - +#define BIT_PTCL_TOTAL_PG_V2_8821C(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C) \ + << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) +#define BITS_PTCL_TOTAL_PG_V2_8821C \ + (BIT_MASK_PTCL_TOTAL_PG_V2_8821C << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) +#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8821C(x) \ + ((x) & (~BITS_PTCL_TOTAL_PG_V2_8821C)) +#define BIT_GET_PTCL_TOTAL_PG_V2_8821C(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) & \ + BIT_MASK_PTCL_TOTAL_PG_V2_8821C) +#define BIT_SET_PTCL_TOTAL_PG_V2_8821C(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V2_8821C(x) | BIT_PTCL_TOTAL_PG_V2_8821C(v)) #define BIT_TX_NULL_1_8821C BIT(1) #define BIT_TX_NULL_0_8821C BIT(0) @@ -6496,17 +10783,46 @@ #define BIT_CLI0_TX_NULL_0_8821C BIT(0) /* 2 REG_VIDEO_ENHANCEMENT_FUN_8821C */ +#define BIT_HIQ_DROP_8821C BIT(7) +#define BIT_MGQ_DROP_8821C BIT(6) #define BIT_VIDEO_JUST_DROP_8821C BIT(1) #define BIT_VIDEO_ENHANCEMENT_FUN_EN_8821C BIT(0) +/* 2 REG_PRECNT_CTRL_8821C */ +#define BIT_EN_PRECNT_8821C BIT(11) + +#define BIT_SHIFT_PRECNT_TH_8821C 0 +#define BIT_MASK_PRECNT_TH_8821C 0x7ff +#define BIT_PRECNT_TH_8821C(x) \ + (((x) & BIT_MASK_PRECNT_TH_8821C) << BIT_SHIFT_PRECNT_TH_8821C) +#define BITS_PRECNT_TH_8821C \ + (BIT_MASK_PRECNT_TH_8821C << BIT_SHIFT_PRECNT_TH_8821C) +#define BIT_CLEAR_PRECNT_TH_8821C(x) ((x) & (~BITS_PRECNT_TH_8821C)) +#define BIT_GET_PRECNT_TH_8821C(x) \ + (((x) >> BIT_SHIFT_PRECNT_TH_8821C) & BIT_MASK_PRECNT_TH_8821C) +#define BIT_SET_PRECNT_TH_8821C(x, v) \ + (BIT_CLEAR_PRECNT_TH_8821C(x) | BIT_PRECNT_TH_8821C(v)) + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_BT_POLLUTE_PKT_CNT_8821C */ #define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C 0 #define BIT_MASK_BT_POLLUTE_PKT_CNT_8821C 0xffff -#define BIT_BT_POLLUTE_PKT_CNT_8821C(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) -#define BIT_GET_BT_POLLUTE_PKT_CNT_8821C(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) - - +#define BIT_BT_POLLUTE_PKT_CNT_8821C(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) +#define BITS_BT_POLLUTE_PKT_CNT_8821C \ + (BIT_MASK_BT_POLLUTE_PKT_CNT_8821C \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) +#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8821C(x) \ + ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8821C)) +#define BIT_GET_BT_POLLUTE_PKT_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) & \ + BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) +#define BIT_SET_BT_POLLUTE_PKT_CNT_8821C(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8821C(x) | \ + BIT_BT_POLLUTE_PKT_CNT_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -6514,10 +10830,15 @@ #define BIT_SHIFT_PTCL_DBG_8821C 0 #define BIT_MASK_PTCL_DBG_8821C 0xffffffffL -#define BIT_PTCL_DBG_8821C(x) (((x) & BIT_MASK_PTCL_DBG_8821C) << BIT_SHIFT_PTCL_DBG_8821C) -#define BIT_GET_PTCL_DBG_8821C(x) (((x) >> BIT_SHIFT_PTCL_DBG_8821C) & BIT_MASK_PTCL_DBG_8821C) - - +#define BIT_PTCL_DBG_8821C(x) \ + (((x) & BIT_MASK_PTCL_DBG_8821C) << BIT_SHIFT_PTCL_DBG_8821C) +#define BITS_PTCL_DBG_8821C \ + (BIT_MASK_PTCL_DBG_8821C << BIT_SHIFT_PTCL_DBG_8821C) +#define BIT_CLEAR_PTCL_DBG_8821C(x) ((x) & (~BITS_PTCL_DBG_8821C)) +#define BIT_GET_PTCL_DBG_8821C(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_8821C) & BIT_MASK_PTCL_DBG_8821C) +#define BIT_SET_PTCL_DBG_8821C(x, v) \ + (BIT_CLEAR_PTCL_DBG_8821C(x) | BIT_PTCL_DBG_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -6525,18 +10846,28 @@ #define BIT_SHIFT_TRI_HEAD_ADDR_8821C 16 #define BIT_MASK_TRI_HEAD_ADDR_8821C 0xfff -#define BIT_TRI_HEAD_ADDR_8821C(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8821C) << BIT_SHIFT_TRI_HEAD_ADDR_8821C) -#define BIT_GET_TRI_HEAD_ADDR_8821C(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8821C) & BIT_MASK_TRI_HEAD_ADDR_8821C) - +#define BIT_TRI_HEAD_ADDR_8821C(x) \ + (((x) & BIT_MASK_TRI_HEAD_ADDR_8821C) << BIT_SHIFT_TRI_HEAD_ADDR_8821C) +#define BITS_TRI_HEAD_ADDR_8821C \ + (BIT_MASK_TRI_HEAD_ADDR_8821C << BIT_SHIFT_TRI_HEAD_ADDR_8821C) +#define BIT_CLEAR_TRI_HEAD_ADDR_8821C(x) ((x) & (~BITS_TRI_HEAD_ADDR_8821C)) +#define BIT_GET_TRI_HEAD_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8821C) & BIT_MASK_TRI_HEAD_ADDR_8821C) +#define BIT_SET_TRI_HEAD_ADDR_8821C(x, v) \ + (BIT_CLEAR_TRI_HEAD_ADDR_8821C(x) | BIT_TRI_HEAD_ADDR_8821C(v)) #define BIT_DROP_TH_EN_8821C BIT(8) #define BIT_SHIFT_DROP_TH_8821C 0 #define BIT_MASK_DROP_TH_8821C 0xff -#define BIT_DROP_TH_8821C(x) (((x) & BIT_MASK_DROP_TH_8821C) << BIT_SHIFT_DROP_TH_8821C) -#define BIT_GET_DROP_TH_8821C(x) (((x) >> BIT_SHIFT_DROP_TH_8821C) & BIT_MASK_DROP_TH_8821C) - - +#define BIT_DROP_TH_8821C(x) \ + (((x) & BIT_MASK_DROP_TH_8821C) << BIT_SHIFT_DROP_TH_8821C) +#define BITS_DROP_TH_8821C (BIT_MASK_DROP_TH_8821C << BIT_SHIFT_DROP_TH_8821C) +#define BIT_CLEAR_DROP_TH_8821C(x) ((x) & (~BITS_DROP_TH_8821C)) +#define BIT_GET_DROP_TH_8821C(x) \ + (((x) >> BIT_SHIFT_DROP_TH_8821C) & BIT_MASK_DROP_TH_8821C) +#define BIT_SET_DROP_TH_8821C(x, v) \ + (BIT_CLEAR_DROP_TH_8821C(x) | BIT_DROP_TH_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -6547,194 +10878,308 @@ #define BIT_MOREDATA_CTRL1_EN_V1_8821C BIT(2) #define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8821C BIT(0) -/* 2 REG_NOT_VALID_8821C */ - /* 2 REG_Q0_Q1_INFO_8821C */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) #define BIT_SHIFT_GTAB_ID_8821C 28 #define BIT_MASK_GTAB_ID_8821C 0x7 -#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) -#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) - - +#define BIT_GTAB_ID_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) +#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C) +#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C)) +#define BIT_GET_GTAB_ID_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) +#define BIT_SET_GTAB_ID_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v)) #define BIT_SHIFT_AC1_PKT_INFO_8821C 16 #define BIT_MASK_AC1_PKT_INFO_8821C 0xfff -#define BIT_AC1_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC1_PKT_INFO_8821C) << BIT_SHIFT_AC1_PKT_INFO_8821C) -#define BIT_GET_AC1_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8821C) & BIT_MASK_AC1_PKT_INFO_8821C) - +#define BIT_AC1_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC1_PKT_INFO_8821C) << BIT_SHIFT_AC1_PKT_INFO_8821C) +#define BITS_AC1_PKT_INFO_8821C \ + (BIT_MASK_AC1_PKT_INFO_8821C << BIT_SHIFT_AC1_PKT_INFO_8821C) +#define BIT_CLEAR_AC1_PKT_INFO_8821C(x) ((x) & (~BITS_AC1_PKT_INFO_8821C)) +#define BIT_GET_AC1_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC1_PKT_INFO_8821C) & BIT_MASK_AC1_PKT_INFO_8821C) +#define BIT_SET_AC1_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC1_PKT_INFO_8821C(x) | BIT_AC1_PKT_INFO_8821C(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8821C 12 #define BIT_MASK_GTAB_ID_V1_8821C 0x7 -#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) -#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) - - +#define BIT_GTAB_ID_V1_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BITS_GTAB_ID_V1_8821C \ + (BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C)) +#define BIT_GET_GTAB_ID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) +#define BIT_SET_GTAB_ID_V1_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v)) #define BIT_SHIFT_AC0_PKT_INFO_8821C 0 #define BIT_MASK_AC0_PKT_INFO_8821C 0xfff -#define BIT_AC0_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC0_PKT_INFO_8821C) << BIT_SHIFT_AC0_PKT_INFO_8821C) -#define BIT_GET_AC0_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8821C) & BIT_MASK_AC0_PKT_INFO_8821C) - - +#define BIT_AC0_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC0_PKT_INFO_8821C) << BIT_SHIFT_AC0_PKT_INFO_8821C) +#define BITS_AC0_PKT_INFO_8821C \ + (BIT_MASK_AC0_PKT_INFO_8821C << BIT_SHIFT_AC0_PKT_INFO_8821C) +#define BIT_CLEAR_AC0_PKT_INFO_8821C(x) ((x) & (~BITS_AC0_PKT_INFO_8821C)) +#define BIT_GET_AC0_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC0_PKT_INFO_8821C) & BIT_MASK_AC0_PKT_INFO_8821C) +#define BIT_SET_AC0_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC0_PKT_INFO_8821C(x) | BIT_AC0_PKT_INFO_8821C(v)) /* 2 REG_Q2_Q3_INFO_8821C */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) #define BIT_SHIFT_GTAB_ID_8821C 28 #define BIT_MASK_GTAB_ID_8821C 0x7 -#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) -#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) - - +#define BIT_GTAB_ID_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) +#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C) +#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C)) +#define BIT_GET_GTAB_ID_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) +#define BIT_SET_GTAB_ID_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v)) #define BIT_SHIFT_AC3_PKT_INFO_8821C 16 #define BIT_MASK_AC3_PKT_INFO_8821C 0xfff -#define BIT_AC3_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC3_PKT_INFO_8821C) << BIT_SHIFT_AC3_PKT_INFO_8821C) -#define BIT_GET_AC3_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8821C) & BIT_MASK_AC3_PKT_INFO_8821C) - +#define BIT_AC3_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC3_PKT_INFO_8821C) << BIT_SHIFT_AC3_PKT_INFO_8821C) +#define BITS_AC3_PKT_INFO_8821C \ + (BIT_MASK_AC3_PKT_INFO_8821C << BIT_SHIFT_AC3_PKT_INFO_8821C) +#define BIT_CLEAR_AC3_PKT_INFO_8821C(x) ((x) & (~BITS_AC3_PKT_INFO_8821C)) +#define BIT_GET_AC3_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC3_PKT_INFO_8821C) & BIT_MASK_AC3_PKT_INFO_8821C) +#define BIT_SET_AC3_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC3_PKT_INFO_8821C(x) | BIT_AC3_PKT_INFO_8821C(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8821C 12 #define BIT_MASK_GTAB_ID_V1_8821C 0x7 -#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) -#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) - - +#define BIT_GTAB_ID_V1_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BITS_GTAB_ID_V1_8821C \ + (BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C)) +#define BIT_GET_GTAB_ID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) +#define BIT_SET_GTAB_ID_V1_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v)) #define BIT_SHIFT_AC2_PKT_INFO_8821C 0 #define BIT_MASK_AC2_PKT_INFO_8821C 0xfff -#define BIT_AC2_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC2_PKT_INFO_8821C) << BIT_SHIFT_AC2_PKT_INFO_8821C) -#define BIT_GET_AC2_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8821C) & BIT_MASK_AC2_PKT_INFO_8821C) - - +#define BIT_AC2_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC2_PKT_INFO_8821C) << BIT_SHIFT_AC2_PKT_INFO_8821C) +#define BITS_AC2_PKT_INFO_8821C \ + (BIT_MASK_AC2_PKT_INFO_8821C << BIT_SHIFT_AC2_PKT_INFO_8821C) +#define BIT_CLEAR_AC2_PKT_INFO_8821C(x) ((x) & (~BITS_AC2_PKT_INFO_8821C)) +#define BIT_GET_AC2_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC2_PKT_INFO_8821C) & BIT_MASK_AC2_PKT_INFO_8821C) +#define BIT_SET_AC2_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC2_PKT_INFO_8821C(x) | BIT_AC2_PKT_INFO_8821C(v)) /* 2 REG_Q4_Q5_INFO_8821C */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) #define BIT_SHIFT_GTAB_ID_8821C 28 #define BIT_MASK_GTAB_ID_8821C 0x7 -#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) -#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) - - +#define BIT_GTAB_ID_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) +#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C) +#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C)) +#define BIT_GET_GTAB_ID_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) +#define BIT_SET_GTAB_ID_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v)) #define BIT_SHIFT_AC5_PKT_INFO_8821C 16 #define BIT_MASK_AC5_PKT_INFO_8821C 0xfff -#define BIT_AC5_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC5_PKT_INFO_8821C) << BIT_SHIFT_AC5_PKT_INFO_8821C) -#define BIT_GET_AC5_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8821C) & BIT_MASK_AC5_PKT_INFO_8821C) - +#define BIT_AC5_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC5_PKT_INFO_8821C) << BIT_SHIFT_AC5_PKT_INFO_8821C) +#define BITS_AC5_PKT_INFO_8821C \ + (BIT_MASK_AC5_PKT_INFO_8821C << BIT_SHIFT_AC5_PKT_INFO_8821C) +#define BIT_CLEAR_AC5_PKT_INFO_8821C(x) ((x) & (~BITS_AC5_PKT_INFO_8821C)) +#define BIT_GET_AC5_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC5_PKT_INFO_8821C) & BIT_MASK_AC5_PKT_INFO_8821C) +#define BIT_SET_AC5_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC5_PKT_INFO_8821C(x) | BIT_AC5_PKT_INFO_8821C(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8821C 12 #define BIT_MASK_GTAB_ID_V1_8821C 0x7 -#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) -#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) - - +#define BIT_GTAB_ID_V1_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BITS_GTAB_ID_V1_8821C \ + (BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C)) +#define BIT_GET_GTAB_ID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) +#define BIT_SET_GTAB_ID_V1_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v)) #define BIT_SHIFT_AC4_PKT_INFO_8821C 0 #define BIT_MASK_AC4_PKT_INFO_8821C 0xfff -#define BIT_AC4_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC4_PKT_INFO_8821C) << BIT_SHIFT_AC4_PKT_INFO_8821C) -#define BIT_GET_AC4_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8821C) & BIT_MASK_AC4_PKT_INFO_8821C) - - +#define BIT_AC4_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC4_PKT_INFO_8821C) << BIT_SHIFT_AC4_PKT_INFO_8821C) +#define BITS_AC4_PKT_INFO_8821C \ + (BIT_MASK_AC4_PKT_INFO_8821C << BIT_SHIFT_AC4_PKT_INFO_8821C) +#define BIT_CLEAR_AC4_PKT_INFO_8821C(x) ((x) & (~BITS_AC4_PKT_INFO_8821C)) +#define BIT_GET_AC4_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC4_PKT_INFO_8821C) & BIT_MASK_AC4_PKT_INFO_8821C) +#define BIT_SET_AC4_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC4_PKT_INFO_8821C(x) | BIT_AC4_PKT_INFO_8821C(v)) /* 2 REG_Q6_Q7_INFO_8821C */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) #define BIT_SHIFT_GTAB_ID_8821C 28 #define BIT_MASK_GTAB_ID_8821C 0x7 -#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) -#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) - - +#define BIT_GTAB_ID_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) +#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C) +#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C)) +#define BIT_GET_GTAB_ID_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) +#define BIT_SET_GTAB_ID_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v)) #define BIT_SHIFT_AC7_PKT_INFO_8821C 16 #define BIT_MASK_AC7_PKT_INFO_8821C 0xfff -#define BIT_AC7_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC7_PKT_INFO_8821C) << BIT_SHIFT_AC7_PKT_INFO_8821C) -#define BIT_GET_AC7_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8821C) & BIT_MASK_AC7_PKT_INFO_8821C) - +#define BIT_AC7_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC7_PKT_INFO_8821C) << BIT_SHIFT_AC7_PKT_INFO_8821C) +#define BITS_AC7_PKT_INFO_8821C \ + (BIT_MASK_AC7_PKT_INFO_8821C << BIT_SHIFT_AC7_PKT_INFO_8821C) +#define BIT_CLEAR_AC7_PKT_INFO_8821C(x) ((x) & (~BITS_AC7_PKT_INFO_8821C)) +#define BIT_GET_AC7_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC7_PKT_INFO_8821C) & BIT_MASK_AC7_PKT_INFO_8821C) +#define BIT_SET_AC7_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC7_PKT_INFO_8821C(x) | BIT_AC7_PKT_INFO_8821C(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8821C 12 #define BIT_MASK_GTAB_ID_V1_8821C 0x7 -#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) -#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) - - +#define BIT_GTAB_ID_V1_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BITS_GTAB_ID_V1_8821C \ + (BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C)) +#define BIT_GET_GTAB_ID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) +#define BIT_SET_GTAB_ID_V1_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v)) #define BIT_SHIFT_AC6_PKT_INFO_8821C 0 #define BIT_MASK_AC6_PKT_INFO_8821C 0xfff -#define BIT_AC6_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC6_PKT_INFO_8821C) << BIT_SHIFT_AC6_PKT_INFO_8821C) -#define BIT_GET_AC6_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8821C) & BIT_MASK_AC6_PKT_INFO_8821C) - - +#define BIT_AC6_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC6_PKT_INFO_8821C) << BIT_SHIFT_AC6_PKT_INFO_8821C) +#define BITS_AC6_PKT_INFO_8821C \ + (BIT_MASK_AC6_PKT_INFO_8821C << BIT_SHIFT_AC6_PKT_INFO_8821C) +#define BIT_CLEAR_AC6_PKT_INFO_8821C(x) ((x) & (~BITS_AC6_PKT_INFO_8821C)) +#define BIT_GET_AC6_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC6_PKT_INFO_8821C) & BIT_MASK_AC6_PKT_INFO_8821C) +#define BIT_SET_AC6_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC6_PKT_INFO_8821C(x) | BIT_AC6_PKT_INFO_8821C(v)) /* 2 REG_MGQ_HIQ_INFO_8821C */ #define BIT_SHIFT_HIQ_PKT_INFO_8821C 16 #define BIT_MASK_HIQ_PKT_INFO_8821C 0xfff -#define BIT_HIQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8821C) << BIT_SHIFT_HIQ_PKT_INFO_8821C) -#define BIT_GET_HIQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8821C) & BIT_MASK_HIQ_PKT_INFO_8821C) - - +#define BIT_HIQ_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_HIQ_PKT_INFO_8821C) << BIT_SHIFT_HIQ_PKT_INFO_8821C) +#define BITS_HIQ_PKT_INFO_8821C \ + (BIT_MASK_HIQ_PKT_INFO_8821C << BIT_SHIFT_HIQ_PKT_INFO_8821C) +#define BIT_CLEAR_HIQ_PKT_INFO_8821C(x) ((x) & (~BITS_HIQ_PKT_INFO_8821C)) +#define BIT_GET_HIQ_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8821C) & BIT_MASK_HIQ_PKT_INFO_8821C) +#define BIT_SET_HIQ_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_HIQ_PKT_INFO_8821C(x) | BIT_HIQ_PKT_INFO_8821C(v)) #define BIT_SHIFT_MGQ_PKT_INFO_8821C 0 #define BIT_MASK_MGQ_PKT_INFO_8821C 0xfff -#define BIT_MGQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8821C) << BIT_SHIFT_MGQ_PKT_INFO_8821C) -#define BIT_GET_MGQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8821C) & BIT_MASK_MGQ_PKT_INFO_8821C) - - +#define BIT_MGQ_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_MGQ_PKT_INFO_8821C) << BIT_SHIFT_MGQ_PKT_INFO_8821C) +#define BITS_MGQ_PKT_INFO_8821C \ + (BIT_MASK_MGQ_PKT_INFO_8821C << BIT_SHIFT_MGQ_PKT_INFO_8821C) +#define BIT_CLEAR_MGQ_PKT_INFO_8821C(x) ((x) & (~BITS_MGQ_PKT_INFO_8821C)) +#define BIT_GET_MGQ_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8821C) & BIT_MASK_MGQ_PKT_INFO_8821C) +#define BIT_SET_MGQ_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_MGQ_PKT_INFO_8821C(x) | BIT_MGQ_PKT_INFO_8821C(v)) /* 2 REG_CMDQ_BCNQ_INFO_8821C */ #define BIT_SHIFT_CMDQ_PKT_INFO_8821C 16 #define BIT_MASK_CMDQ_PKT_INFO_8821C 0xfff -#define BIT_CMDQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_8821C) << BIT_SHIFT_CMDQ_PKT_INFO_8821C) -#define BIT_GET_CMDQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8821C) & BIT_MASK_CMDQ_PKT_INFO_8821C) - - +#define BIT_CMDQ_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_CMDQ_PKT_INFO_8821C) << BIT_SHIFT_CMDQ_PKT_INFO_8821C) +#define BITS_CMDQ_PKT_INFO_8821C \ + (BIT_MASK_CMDQ_PKT_INFO_8821C << BIT_SHIFT_CMDQ_PKT_INFO_8821C) +#define BIT_CLEAR_CMDQ_PKT_INFO_8821C(x) ((x) & (~BITS_CMDQ_PKT_INFO_8821C)) +#define BIT_GET_CMDQ_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8821C) & BIT_MASK_CMDQ_PKT_INFO_8821C) +#define BIT_SET_CMDQ_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_CMDQ_PKT_INFO_8821C(x) | BIT_CMDQ_PKT_INFO_8821C(v)) #define BIT_SHIFT_BCNQ_PKT_INFO_8821C 0 #define BIT_MASK_BCNQ_PKT_INFO_8821C 0xfff -#define BIT_BCNQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_8821C) << BIT_SHIFT_BCNQ_PKT_INFO_8821C) -#define BIT_GET_BCNQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8821C) & BIT_MASK_BCNQ_PKT_INFO_8821C) - - +#define BIT_BCNQ_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_BCNQ_PKT_INFO_8821C) << BIT_SHIFT_BCNQ_PKT_INFO_8821C) +#define BITS_BCNQ_PKT_INFO_8821C \ + (BIT_MASK_BCNQ_PKT_INFO_8821C << BIT_SHIFT_BCNQ_PKT_INFO_8821C) +#define BIT_CLEAR_BCNQ_PKT_INFO_8821C(x) ((x) & (~BITS_BCNQ_PKT_INFO_8821C)) +#define BIT_GET_BCNQ_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8821C) & BIT_MASK_BCNQ_PKT_INFO_8821C) +#define BIT_SET_BCNQ_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_BCNQ_PKT_INFO_8821C(x) | BIT_BCNQ_PKT_INFO_8821C(v)) /* 2 REG_USEREG_SETTING_8821C */ #define BIT_NDPA_USEREG_8821C BIT(21) #define BIT_SHIFT_RETRY_USEREG_8821C 19 #define BIT_MASK_RETRY_USEREG_8821C 0x3 -#define BIT_RETRY_USEREG_8821C(x) (((x) & BIT_MASK_RETRY_USEREG_8821C) << BIT_SHIFT_RETRY_USEREG_8821C) -#define BIT_GET_RETRY_USEREG_8821C(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8821C) & BIT_MASK_RETRY_USEREG_8821C) - - +#define BIT_RETRY_USEREG_8821C(x) \ + (((x) & BIT_MASK_RETRY_USEREG_8821C) << BIT_SHIFT_RETRY_USEREG_8821C) +#define BITS_RETRY_USEREG_8821C \ + (BIT_MASK_RETRY_USEREG_8821C << BIT_SHIFT_RETRY_USEREG_8821C) +#define BIT_CLEAR_RETRY_USEREG_8821C(x) ((x) & (~BITS_RETRY_USEREG_8821C)) +#define BIT_GET_RETRY_USEREG_8821C(x) \ + (((x) >> BIT_SHIFT_RETRY_USEREG_8821C) & BIT_MASK_RETRY_USEREG_8821C) +#define BIT_SET_RETRY_USEREG_8821C(x, v) \ + (BIT_CLEAR_RETRY_USEREG_8821C(x) | BIT_RETRY_USEREG_8821C(v)) #define BIT_SHIFT_TRYPKT_USEREG_8821C 17 #define BIT_MASK_TRYPKT_USEREG_8821C 0x3 -#define BIT_TRYPKT_USEREG_8821C(x) (((x) & BIT_MASK_TRYPKT_USEREG_8821C) << BIT_SHIFT_TRYPKT_USEREG_8821C) -#define BIT_GET_TRYPKT_USEREG_8821C(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8821C) & BIT_MASK_TRYPKT_USEREG_8821C) - +#define BIT_TRYPKT_USEREG_8821C(x) \ + (((x) & BIT_MASK_TRYPKT_USEREG_8821C) << BIT_SHIFT_TRYPKT_USEREG_8821C) +#define BITS_TRYPKT_USEREG_8821C \ + (BIT_MASK_TRYPKT_USEREG_8821C << BIT_SHIFT_TRYPKT_USEREG_8821C) +#define BIT_CLEAR_TRYPKT_USEREG_8821C(x) ((x) & (~BITS_TRYPKT_USEREG_8821C)) +#define BIT_GET_TRYPKT_USEREG_8821C(x) \ + (((x) >> BIT_SHIFT_TRYPKT_USEREG_8821C) & BIT_MASK_TRYPKT_USEREG_8821C) +#define BIT_SET_TRYPKT_USEREG_8821C(x, v) \ + (BIT_CLEAR_TRYPKT_USEREG_8821C(x) | BIT_TRYPKT_USEREG_8821C(v)) #define BIT_CTLPKT_USEREG_8821C BIT(16) /* 2 REG_AESIV_SETTING_8821C */ #define BIT_SHIFT_AESIV_OFFSET_8821C 0 -#define BIT_MASK_AESIV_OFFSET_8821C 0xfff -#define BIT_AESIV_OFFSET_8821C(x) (((x) & BIT_MASK_AESIV_OFFSET_8821C) << BIT_SHIFT_AESIV_OFFSET_8821C) -#define BIT_GET_AESIV_OFFSET_8821C(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8821C) & BIT_MASK_AESIV_OFFSET_8821C) - - +#define BIT_MASK_AESIV_OFFSET_8821C 0xfff +#define BIT_AESIV_OFFSET_8821C(x) \ + (((x) & BIT_MASK_AESIV_OFFSET_8821C) << BIT_SHIFT_AESIV_OFFSET_8821C) +#define BITS_AESIV_OFFSET_8821C \ + (BIT_MASK_AESIV_OFFSET_8821C << BIT_SHIFT_AESIV_OFFSET_8821C) +#define BIT_CLEAR_AESIV_OFFSET_8821C(x) ((x) & (~BITS_AESIV_OFFSET_8821C)) +#define BIT_GET_AESIV_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_AESIV_OFFSET_8821C) & BIT_MASK_AESIV_OFFSET_8821C) +#define BIT_SET_AESIV_OFFSET_8821C(x, v) \ + (BIT_CLEAR_AESIV_OFFSET_8821C(x) | BIT_AESIV_OFFSET_8821C(v)) /* 2 REG_BF0_TIME_SETTING_8821C */ #define BIT_BF0_TIMER_SET_8821C BIT(31) @@ -6744,17 +11189,30 @@ #define BIT_SHIFT_BF0_PRETIME_OVER_8821C 16 #define BIT_MASK_BF0_PRETIME_OVER_8821C 0xfff -#define BIT_BF0_PRETIME_OVER_8821C(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8821C) << BIT_SHIFT_BF0_PRETIME_OVER_8821C) -#define BIT_GET_BF0_PRETIME_OVER_8821C(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8821C) & BIT_MASK_BF0_PRETIME_OVER_8821C) - - +#define BIT_BF0_PRETIME_OVER_8821C(x) \ + (((x) & BIT_MASK_BF0_PRETIME_OVER_8821C) \ + << BIT_SHIFT_BF0_PRETIME_OVER_8821C) +#define BITS_BF0_PRETIME_OVER_8821C \ + (BIT_MASK_BF0_PRETIME_OVER_8821C << BIT_SHIFT_BF0_PRETIME_OVER_8821C) +#define BIT_CLEAR_BF0_PRETIME_OVER_8821C(x) \ + ((x) & (~BITS_BF0_PRETIME_OVER_8821C)) +#define BIT_GET_BF0_PRETIME_OVER_8821C(x) \ + (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8821C) & \ + BIT_MASK_BF0_PRETIME_OVER_8821C) +#define BIT_SET_BF0_PRETIME_OVER_8821C(x, v) \ + (BIT_CLEAR_BF0_PRETIME_OVER_8821C(x) | BIT_BF0_PRETIME_OVER_8821C(v)) #define BIT_SHIFT_BF0_LIFETIME_8821C 0 #define BIT_MASK_BF0_LIFETIME_8821C 0xffff -#define BIT_BF0_LIFETIME_8821C(x) (((x) & BIT_MASK_BF0_LIFETIME_8821C) << BIT_SHIFT_BF0_LIFETIME_8821C) -#define BIT_GET_BF0_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8821C) & BIT_MASK_BF0_LIFETIME_8821C) - - +#define BIT_BF0_LIFETIME_8821C(x) \ + (((x) & BIT_MASK_BF0_LIFETIME_8821C) << BIT_SHIFT_BF0_LIFETIME_8821C) +#define BITS_BF0_LIFETIME_8821C \ + (BIT_MASK_BF0_LIFETIME_8821C << BIT_SHIFT_BF0_LIFETIME_8821C) +#define BIT_CLEAR_BF0_LIFETIME_8821C(x) ((x) & (~BITS_BF0_LIFETIME_8821C)) +#define BIT_GET_BF0_LIFETIME_8821C(x) \ + (((x) >> BIT_SHIFT_BF0_LIFETIME_8821C) & BIT_MASK_BF0_LIFETIME_8821C) +#define BIT_SET_BF0_LIFETIME_8821C(x, v) \ + (BIT_CLEAR_BF0_LIFETIME_8821C(x) | BIT_BF0_LIFETIME_8821C(v)) /* 2 REG_BF1_TIME_SETTING_8821C */ #define BIT_BF1_TIMER_SET_8821C BIT(31) @@ -6764,17 +11222,30 @@ #define BIT_SHIFT_BF1_PRETIME_OVER_8821C 16 #define BIT_MASK_BF1_PRETIME_OVER_8821C 0xfff -#define BIT_BF1_PRETIME_OVER_8821C(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8821C) << BIT_SHIFT_BF1_PRETIME_OVER_8821C) -#define BIT_GET_BF1_PRETIME_OVER_8821C(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8821C) & BIT_MASK_BF1_PRETIME_OVER_8821C) - - +#define BIT_BF1_PRETIME_OVER_8821C(x) \ + (((x) & BIT_MASK_BF1_PRETIME_OVER_8821C) \ + << BIT_SHIFT_BF1_PRETIME_OVER_8821C) +#define BITS_BF1_PRETIME_OVER_8821C \ + (BIT_MASK_BF1_PRETIME_OVER_8821C << BIT_SHIFT_BF1_PRETIME_OVER_8821C) +#define BIT_CLEAR_BF1_PRETIME_OVER_8821C(x) \ + ((x) & (~BITS_BF1_PRETIME_OVER_8821C)) +#define BIT_GET_BF1_PRETIME_OVER_8821C(x) \ + (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8821C) & \ + BIT_MASK_BF1_PRETIME_OVER_8821C) +#define BIT_SET_BF1_PRETIME_OVER_8821C(x, v) \ + (BIT_CLEAR_BF1_PRETIME_OVER_8821C(x) | BIT_BF1_PRETIME_OVER_8821C(v)) #define BIT_SHIFT_BF1_LIFETIME_8821C 0 #define BIT_MASK_BF1_LIFETIME_8821C 0xffff -#define BIT_BF1_LIFETIME_8821C(x) (((x) & BIT_MASK_BF1_LIFETIME_8821C) << BIT_SHIFT_BF1_LIFETIME_8821C) -#define BIT_GET_BF1_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8821C) & BIT_MASK_BF1_LIFETIME_8821C) - - +#define BIT_BF1_LIFETIME_8821C(x) \ + (((x) & BIT_MASK_BF1_LIFETIME_8821C) << BIT_SHIFT_BF1_LIFETIME_8821C) +#define BITS_BF1_LIFETIME_8821C \ + (BIT_MASK_BF1_LIFETIME_8821C << BIT_SHIFT_BF1_LIFETIME_8821C) +#define BIT_CLEAR_BF1_LIFETIME_8821C(x) ((x) & (~BITS_BF1_LIFETIME_8821C)) +#define BIT_GET_BF1_LIFETIME_8821C(x) \ + (((x) >> BIT_SHIFT_BF1_LIFETIME_8821C) & BIT_MASK_BF1_LIFETIME_8821C) +#define BIT_SET_BF1_LIFETIME_8821C(x, v) \ + (BIT_CLEAR_BF1_LIFETIME_8821C(x) | BIT_BF1_LIFETIME_8821C(v)) /* 2 REG_BF_TIMEOUT_EN_8821C */ #define BIT_EN_VHT_LDPC_8821C BIT(9) @@ -6786,338 +11257,680 @@ #define BIT_SHIFT_MACID31_0_RELEASE_8821C 0 #define BIT_MASK_MACID31_0_RELEASE_8821C 0xffffffffL -#define BIT_MACID31_0_RELEASE_8821C(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8821C) << BIT_SHIFT_MACID31_0_RELEASE_8821C) -#define BIT_GET_MACID31_0_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8821C) & BIT_MASK_MACID31_0_RELEASE_8821C) - - +#define BIT_MACID31_0_RELEASE_8821C(x) \ + (((x) & BIT_MASK_MACID31_0_RELEASE_8821C) \ + << BIT_SHIFT_MACID31_0_RELEASE_8821C) +#define BITS_MACID31_0_RELEASE_8821C \ + (BIT_MASK_MACID31_0_RELEASE_8821C << BIT_SHIFT_MACID31_0_RELEASE_8821C) +#define BIT_CLEAR_MACID31_0_RELEASE_8821C(x) \ + ((x) & (~BITS_MACID31_0_RELEASE_8821C)) +#define BIT_GET_MACID31_0_RELEASE_8821C(x) \ + (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8821C) & \ + BIT_MASK_MACID31_0_RELEASE_8821C) +#define BIT_SET_MACID31_0_RELEASE_8821C(x, v) \ + (BIT_CLEAR_MACID31_0_RELEASE_8821C(x) | BIT_MACID31_0_RELEASE_8821C(v)) /* 2 REG_MACID_RELEASE1_8821C */ #define BIT_SHIFT_MACID63_32_RELEASE_8821C 0 #define BIT_MASK_MACID63_32_RELEASE_8821C 0xffffffffL -#define BIT_MACID63_32_RELEASE_8821C(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8821C) << BIT_SHIFT_MACID63_32_RELEASE_8821C) -#define BIT_GET_MACID63_32_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8821C) & BIT_MASK_MACID63_32_RELEASE_8821C) - - +#define BIT_MACID63_32_RELEASE_8821C(x) \ + (((x) & BIT_MASK_MACID63_32_RELEASE_8821C) \ + << BIT_SHIFT_MACID63_32_RELEASE_8821C) +#define BITS_MACID63_32_RELEASE_8821C \ + (BIT_MASK_MACID63_32_RELEASE_8821C \ + << BIT_SHIFT_MACID63_32_RELEASE_8821C) +#define BIT_CLEAR_MACID63_32_RELEASE_8821C(x) \ + ((x) & (~BITS_MACID63_32_RELEASE_8821C)) +#define BIT_GET_MACID63_32_RELEASE_8821C(x) \ + (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8821C) & \ + BIT_MASK_MACID63_32_RELEASE_8821C) +#define BIT_SET_MACID63_32_RELEASE_8821C(x, v) \ + (BIT_CLEAR_MACID63_32_RELEASE_8821C(x) | \ + BIT_MACID63_32_RELEASE_8821C(v)) /* 2 REG_MACID_RELEASE2_8821C */ #define BIT_SHIFT_MACID95_64_RELEASE_8821C 0 #define BIT_MASK_MACID95_64_RELEASE_8821C 0xffffffffL -#define BIT_MACID95_64_RELEASE_8821C(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8821C) << BIT_SHIFT_MACID95_64_RELEASE_8821C) -#define BIT_GET_MACID95_64_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8821C) & BIT_MASK_MACID95_64_RELEASE_8821C) - - +#define BIT_MACID95_64_RELEASE_8821C(x) \ + (((x) & BIT_MASK_MACID95_64_RELEASE_8821C) \ + << BIT_SHIFT_MACID95_64_RELEASE_8821C) +#define BITS_MACID95_64_RELEASE_8821C \ + (BIT_MASK_MACID95_64_RELEASE_8821C \ + << BIT_SHIFT_MACID95_64_RELEASE_8821C) +#define BIT_CLEAR_MACID95_64_RELEASE_8821C(x) \ + ((x) & (~BITS_MACID95_64_RELEASE_8821C)) +#define BIT_GET_MACID95_64_RELEASE_8821C(x) \ + (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8821C) & \ + BIT_MASK_MACID95_64_RELEASE_8821C) +#define BIT_SET_MACID95_64_RELEASE_8821C(x, v) \ + (BIT_CLEAR_MACID95_64_RELEASE_8821C(x) | \ + BIT_MACID95_64_RELEASE_8821C(v)) /* 2 REG_MACID_RELEASE3_8821C */ #define BIT_SHIFT_MACID127_96_RELEASE_8821C 0 #define BIT_MASK_MACID127_96_RELEASE_8821C 0xffffffffL -#define BIT_MACID127_96_RELEASE_8821C(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8821C) << BIT_SHIFT_MACID127_96_RELEASE_8821C) -#define BIT_GET_MACID127_96_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8821C) & BIT_MASK_MACID127_96_RELEASE_8821C) - - +#define BIT_MACID127_96_RELEASE_8821C(x) \ + (((x) & BIT_MASK_MACID127_96_RELEASE_8821C) \ + << BIT_SHIFT_MACID127_96_RELEASE_8821C) +#define BITS_MACID127_96_RELEASE_8821C \ + (BIT_MASK_MACID127_96_RELEASE_8821C \ + << BIT_SHIFT_MACID127_96_RELEASE_8821C) +#define BIT_CLEAR_MACID127_96_RELEASE_8821C(x) \ + ((x) & (~BITS_MACID127_96_RELEASE_8821C)) +#define BIT_GET_MACID127_96_RELEASE_8821C(x) \ + (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8821C) & \ + BIT_MASK_MACID127_96_RELEASE_8821C) +#define BIT_SET_MACID127_96_RELEASE_8821C(x, v) \ + (BIT_CLEAR_MACID127_96_RELEASE_8821C(x) | \ + BIT_MACID127_96_RELEASE_8821C(v)) /* 2 REG_MACID_RELEASE_SETTING_8821C */ #define BIT_MACID_VALUE_8821C BIT(7) #define BIT_SHIFT_MACID_OFFSET_8821C 0 #define BIT_MASK_MACID_OFFSET_8821C 0x7f -#define BIT_MACID_OFFSET_8821C(x) (((x) & BIT_MASK_MACID_OFFSET_8821C) << BIT_SHIFT_MACID_OFFSET_8821C) -#define BIT_GET_MACID_OFFSET_8821C(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8821C) & BIT_MASK_MACID_OFFSET_8821C) - - +#define BIT_MACID_OFFSET_8821C(x) \ + (((x) & BIT_MASK_MACID_OFFSET_8821C) << BIT_SHIFT_MACID_OFFSET_8821C) +#define BITS_MACID_OFFSET_8821C \ + (BIT_MASK_MACID_OFFSET_8821C << BIT_SHIFT_MACID_OFFSET_8821C) +#define BIT_CLEAR_MACID_OFFSET_8821C(x) ((x) & (~BITS_MACID_OFFSET_8821C)) +#define BIT_GET_MACID_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_MACID_OFFSET_8821C) & BIT_MASK_MACID_OFFSET_8821C) +#define BIT_SET_MACID_OFFSET_8821C(x, v) \ + (BIT_CLEAR_MACID_OFFSET_8821C(x) | BIT_MACID_OFFSET_8821C(v)) /* 2 REG_FAST_EDCA_VOVI_SETTING_8821C */ #define BIT_SHIFT_VI_FAST_EDCA_TO_8821C 24 #define BIT_MASK_VI_FAST_EDCA_TO_8821C 0xff -#define BIT_VI_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8821C) << BIT_SHIFT_VI_FAST_EDCA_TO_8821C) -#define BIT_GET_VI_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8821C) & BIT_MASK_VI_FAST_EDCA_TO_8821C) - +#define BIT_VI_FAST_EDCA_TO_8821C(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_TO_8821C) \ + << BIT_SHIFT_VI_FAST_EDCA_TO_8821C) +#define BITS_VI_FAST_EDCA_TO_8821C \ + (BIT_MASK_VI_FAST_EDCA_TO_8821C << BIT_SHIFT_VI_FAST_EDCA_TO_8821C) +#define BIT_CLEAR_VI_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8821C)) +#define BIT_GET_VI_FAST_EDCA_TO_8821C(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8821C) & \ + BIT_MASK_VI_FAST_EDCA_TO_8821C) +#define BIT_SET_VI_FAST_EDCA_TO_8821C(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_TO_8821C(x) | BIT_VI_FAST_EDCA_TO_8821C(v)) #define BIT_VI_THRESHOLD_SEL_8821C BIT(23) #define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C 16 #define BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C 0x7f -#define BIT_VI_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) -#define BIT_GET_VI_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) - - +#define BIT_VI_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) +#define BITS_VI_FAST_EDCA_PKT_TH_8821C \ + (BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8821C(x) \ + ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8821C)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) & \ + BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) +#define BIT_SET_VI_FAST_EDCA_PKT_TH_8821C(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8821C(x) | \ + BIT_VI_FAST_EDCA_PKT_TH_8821C(v)) #define BIT_SHIFT_VO_FAST_EDCA_TO_8821C 8 #define BIT_MASK_VO_FAST_EDCA_TO_8821C 0xff -#define BIT_VO_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8821C) << BIT_SHIFT_VO_FAST_EDCA_TO_8821C) -#define BIT_GET_VO_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8821C) & BIT_MASK_VO_FAST_EDCA_TO_8821C) - +#define BIT_VO_FAST_EDCA_TO_8821C(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO_8821C) \ + << BIT_SHIFT_VO_FAST_EDCA_TO_8821C) +#define BITS_VO_FAST_EDCA_TO_8821C \ + (BIT_MASK_VO_FAST_EDCA_TO_8821C << BIT_SHIFT_VO_FAST_EDCA_TO_8821C) +#define BIT_CLEAR_VO_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8821C)) +#define BIT_GET_VO_FAST_EDCA_TO_8821C(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8821C) & \ + BIT_MASK_VO_FAST_EDCA_TO_8821C) +#define BIT_SET_VO_FAST_EDCA_TO_8821C(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO_8821C(x) | BIT_VO_FAST_EDCA_TO_8821C(v)) #define BIT_VO_THRESHOLD_SEL_8821C BIT(7) #define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C 0 #define BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C 0x7f -#define BIT_VO_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) -#define BIT_GET_VO_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) - - +#define BIT_VO_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) +#define BITS_VO_FAST_EDCA_PKT_TH_8821C \ + (BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8821C(x) \ + ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8821C)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) & \ + BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) +#define BIT_SET_VO_FAST_EDCA_PKT_TH_8821C(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8821C(x) | \ + BIT_VO_FAST_EDCA_PKT_TH_8821C(v)) /* 2 REG_FAST_EDCA_BEBK_SETTING_8821C */ #define BIT_SHIFT_BK_FAST_EDCA_TO_8821C 24 #define BIT_MASK_BK_FAST_EDCA_TO_8821C 0xff -#define BIT_BK_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8821C) << BIT_SHIFT_BK_FAST_EDCA_TO_8821C) -#define BIT_GET_BK_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8821C) & BIT_MASK_BK_FAST_EDCA_TO_8821C) - +#define BIT_BK_FAST_EDCA_TO_8821C(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_TO_8821C) \ + << BIT_SHIFT_BK_FAST_EDCA_TO_8821C) +#define BITS_BK_FAST_EDCA_TO_8821C \ + (BIT_MASK_BK_FAST_EDCA_TO_8821C << BIT_SHIFT_BK_FAST_EDCA_TO_8821C) +#define BIT_CLEAR_BK_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8821C)) +#define BIT_GET_BK_FAST_EDCA_TO_8821C(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8821C) & \ + BIT_MASK_BK_FAST_EDCA_TO_8821C) +#define BIT_SET_BK_FAST_EDCA_TO_8821C(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_TO_8821C(x) | BIT_BK_FAST_EDCA_TO_8821C(v)) #define BIT_BK_THRESHOLD_SEL_8821C BIT(23) #define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C 16 #define BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C 0x7f -#define BIT_BK_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) -#define BIT_GET_BK_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) - - +#define BIT_BK_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) +#define BITS_BK_FAST_EDCA_PKT_TH_8821C \ + (BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8821C(x) \ + ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8821C)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) & \ + BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) +#define BIT_SET_BK_FAST_EDCA_PKT_TH_8821C(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8821C(x) | \ + BIT_BK_FAST_EDCA_PKT_TH_8821C(v)) #define BIT_SHIFT_BE_FAST_EDCA_TO_8821C 8 #define BIT_MASK_BE_FAST_EDCA_TO_8821C 0xff -#define BIT_BE_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8821C) << BIT_SHIFT_BE_FAST_EDCA_TO_8821C) -#define BIT_GET_BE_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8821C) & BIT_MASK_BE_FAST_EDCA_TO_8821C) - +#define BIT_BE_FAST_EDCA_TO_8821C(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO_8821C) \ + << BIT_SHIFT_BE_FAST_EDCA_TO_8821C) +#define BITS_BE_FAST_EDCA_TO_8821C \ + (BIT_MASK_BE_FAST_EDCA_TO_8821C << BIT_SHIFT_BE_FAST_EDCA_TO_8821C) +#define BIT_CLEAR_BE_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8821C)) +#define BIT_GET_BE_FAST_EDCA_TO_8821C(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8821C) & \ + BIT_MASK_BE_FAST_EDCA_TO_8821C) +#define BIT_SET_BE_FAST_EDCA_TO_8821C(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO_8821C(x) | BIT_BE_FAST_EDCA_TO_8821C(v)) #define BIT_BE_THRESHOLD_SEL_8821C BIT(7) #define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C 0 #define BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C 0x7f -#define BIT_BE_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) -#define BIT_GET_BE_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) - - +#define BIT_BE_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) +#define BITS_BE_FAST_EDCA_PKT_TH_8821C \ + (BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8821C(x) \ + ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8821C)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) & \ + BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) +#define BIT_SET_BE_FAST_EDCA_PKT_TH_8821C(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8821C(x) | \ + BIT_BE_FAST_EDCA_PKT_TH_8821C(v)) /* 2 REG_MACID_DROP0_8821C */ #define BIT_SHIFT_MACID31_0_DROP_8821C 0 #define BIT_MASK_MACID31_0_DROP_8821C 0xffffffffL -#define BIT_MACID31_0_DROP_8821C(x) (((x) & BIT_MASK_MACID31_0_DROP_8821C) << BIT_SHIFT_MACID31_0_DROP_8821C) -#define BIT_GET_MACID31_0_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8821C) & BIT_MASK_MACID31_0_DROP_8821C) - - +#define BIT_MACID31_0_DROP_8821C(x) \ + (((x) & BIT_MASK_MACID31_0_DROP_8821C) \ + << BIT_SHIFT_MACID31_0_DROP_8821C) +#define BITS_MACID31_0_DROP_8821C \ + (BIT_MASK_MACID31_0_DROP_8821C << BIT_SHIFT_MACID31_0_DROP_8821C) +#define BIT_CLEAR_MACID31_0_DROP_8821C(x) ((x) & (~BITS_MACID31_0_DROP_8821C)) +#define BIT_GET_MACID31_0_DROP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID31_0_DROP_8821C) & \ + BIT_MASK_MACID31_0_DROP_8821C) +#define BIT_SET_MACID31_0_DROP_8821C(x, v) \ + (BIT_CLEAR_MACID31_0_DROP_8821C(x) | BIT_MACID31_0_DROP_8821C(v)) /* 2 REG_MACID_DROP1_8821C */ #define BIT_SHIFT_MACID63_32_DROP_8821C 0 #define BIT_MASK_MACID63_32_DROP_8821C 0xffffffffL -#define BIT_MACID63_32_DROP_8821C(x) (((x) & BIT_MASK_MACID63_32_DROP_8821C) << BIT_SHIFT_MACID63_32_DROP_8821C) -#define BIT_GET_MACID63_32_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8821C) & BIT_MASK_MACID63_32_DROP_8821C) - - +#define BIT_MACID63_32_DROP_8821C(x) \ + (((x) & BIT_MASK_MACID63_32_DROP_8821C) \ + << BIT_SHIFT_MACID63_32_DROP_8821C) +#define BITS_MACID63_32_DROP_8821C \ + (BIT_MASK_MACID63_32_DROP_8821C << BIT_SHIFT_MACID63_32_DROP_8821C) +#define BIT_CLEAR_MACID63_32_DROP_8821C(x) ((x) & (~BITS_MACID63_32_DROP_8821C)) +#define BIT_GET_MACID63_32_DROP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID63_32_DROP_8821C) & \ + BIT_MASK_MACID63_32_DROP_8821C) +#define BIT_SET_MACID63_32_DROP_8821C(x, v) \ + (BIT_CLEAR_MACID63_32_DROP_8821C(x) | BIT_MACID63_32_DROP_8821C(v)) /* 2 REG_MACID_DROP2_8821C */ #define BIT_SHIFT_MACID95_64_DROP_8821C 0 #define BIT_MASK_MACID95_64_DROP_8821C 0xffffffffL -#define BIT_MACID95_64_DROP_8821C(x) (((x) & BIT_MASK_MACID95_64_DROP_8821C) << BIT_SHIFT_MACID95_64_DROP_8821C) -#define BIT_GET_MACID95_64_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8821C) & BIT_MASK_MACID95_64_DROP_8821C) - - +#define BIT_MACID95_64_DROP_8821C(x) \ + (((x) & BIT_MASK_MACID95_64_DROP_8821C) \ + << BIT_SHIFT_MACID95_64_DROP_8821C) +#define BITS_MACID95_64_DROP_8821C \ + (BIT_MASK_MACID95_64_DROP_8821C << BIT_SHIFT_MACID95_64_DROP_8821C) +#define BIT_CLEAR_MACID95_64_DROP_8821C(x) ((x) & (~BITS_MACID95_64_DROP_8821C)) +#define BIT_GET_MACID95_64_DROP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID95_64_DROP_8821C) & \ + BIT_MASK_MACID95_64_DROP_8821C) +#define BIT_SET_MACID95_64_DROP_8821C(x, v) \ + (BIT_CLEAR_MACID95_64_DROP_8821C(x) | BIT_MACID95_64_DROP_8821C(v)) /* 2 REG_MACID_DROP3_8821C */ #define BIT_SHIFT_MACID127_96_DROP_8821C 0 #define BIT_MASK_MACID127_96_DROP_8821C 0xffffffffL -#define BIT_MACID127_96_DROP_8821C(x) (((x) & BIT_MASK_MACID127_96_DROP_8821C) << BIT_SHIFT_MACID127_96_DROP_8821C) -#define BIT_GET_MACID127_96_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8821C) & BIT_MASK_MACID127_96_DROP_8821C) - - +#define BIT_MACID127_96_DROP_8821C(x) \ + (((x) & BIT_MASK_MACID127_96_DROP_8821C) \ + << BIT_SHIFT_MACID127_96_DROP_8821C) +#define BITS_MACID127_96_DROP_8821C \ + (BIT_MASK_MACID127_96_DROP_8821C << BIT_SHIFT_MACID127_96_DROP_8821C) +#define BIT_CLEAR_MACID127_96_DROP_8821C(x) \ + ((x) & (~BITS_MACID127_96_DROP_8821C)) +#define BIT_GET_MACID127_96_DROP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID127_96_DROP_8821C) & \ + BIT_MASK_MACID127_96_DROP_8821C) +#define BIT_SET_MACID127_96_DROP_8821C(x, v) \ + (BIT_CLEAR_MACID127_96_DROP_8821C(x) | BIT_MACID127_96_DROP_8821C(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_0_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_0_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) - - +#define BIT_R_MACID_RELEASE_SUCCESS_0_8821C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) +#define BITS_R_MACID_RELEASE_SUCCESS_0_8821C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8821C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8821C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8821C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8821C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8821C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_0_8821C(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_1_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_1_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) - - +#define BIT_R_MACID_RELEASE_SUCCESS_1_8821C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) +#define BITS_R_MACID_RELEASE_SUCCESS_1_8821C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8821C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8821C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8821C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8821C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8821C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_1_8821C(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_2_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_2_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) - - +#define BIT_R_MACID_RELEASE_SUCCESS_2_8821C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) +#define BITS_R_MACID_RELEASE_SUCCESS_2_8821C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8821C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8821C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8821C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8821C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8821C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_2_8821C(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_3_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_3_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) - - - -/* 2 REG_MGG_FIFO_CRTL_8821C */ -#define BIT_R_MGG_FIFO_EN_8821C BIT(31) - -#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C 28 -#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C 0x7 -#define BIT_R_MGG_FIFO_PG_SIZE_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C) -#define BIT_GET_R_MGG_FIFO_PG_SIZE_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C) - - - -#define BIT_SHIFT_R_MGG_FIFO_START_PG_8821C 16 -#define BIT_MASK_R_MGG_FIFO_START_PG_8821C 0xfff -#define BIT_R_MGG_FIFO_START_PG_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8821C) << BIT_SHIFT_R_MGG_FIFO_START_PG_8821C) -#define BIT_GET_R_MGG_FIFO_START_PG_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8821C) & BIT_MASK_R_MGG_FIFO_START_PG_8821C) - - - -#define BIT_SHIFT_R_MGG_FIFO_SIZE_8821C 14 -#define BIT_MASK_R_MGG_FIFO_SIZE_8821C 0x3 -#define BIT_R_MGG_FIFO_SIZE_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8821C) << BIT_SHIFT_R_MGG_FIFO_SIZE_8821C) -#define BIT_GET_R_MGG_FIFO_SIZE_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8821C) & BIT_MASK_R_MGG_FIFO_SIZE_8821C) - - -#define BIT_R_MGG_FIFO_PAUSE_8821C BIT(13) - -#define BIT_SHIFT_R_MGG_FIFO_RPTR_8821C 8 -#define BIT_MASK_R_MGG_FIFO_RPTR_8821C 0x1f -#define BIT_R_MGG_FIFO_RPTR_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8821C) << BIT_SHIFT_R_MGG_FIFO_RPTR_8821C) -#define BIT_GET_R_MGG_FIFO_RPTR_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8821C) & BIT_MASK_R_MGG_FIFO_RPTR_8821C) - - -#define BIT_R_MGG_FIFO_OV_8821C BIT(7) -#define BIT_R_MGG_FIFO_WPTR_ERROR_8821C BIT(6) -#define BIT_R_EN_CPU_LIFETIME_8821C BIT(5) - -#define BIT_SHIFT_R_MGG_FIFO_WPTR_8821C 0 -#define BIT_MASK_R_MGG_FIFO_WPTR_8821C 0x1f -#define BIT_R_MGG_FIFO_WPTR_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8821C) << BIT_SHIFT_R_MGG_FIFO_WPTR_8821C) -#define BIT_GET_R_MGG_FIFO_WPTR_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8821C) & BIT_MASK_R_MGG_FIFO_WPTR_8821C) - - - -/* 2 REG_MGG_FIFO_INT_8821C */ - -#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C 16 -#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C 0xffff -#define BIT_R_MGG_FIFO_INT_FLAG_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C) -#define BIT_GET_R_MGG_FIFO_INT_FLAG_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C) - - - -#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C 0 -#define BIT_MASK_R_MGG_FIFO_INT_MASK_8821C 0xffff -#define BIT_R_MGG_FIFO_INT_MASK_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8821C) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C) -#define BIT_GET_R_MGG_FIFO_INT_MASK_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C) & BIT_MASK_R_MGG_FIFO_INT_MASK_8821C) - - - -/* 2 REG_MGG_FIFO_LIFETIME_8821C */ - -#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C 16 -#define BIT_MASK_R_MGG_FIFO_LIFETIME_8821C 0xffff -#define BIT_R_MGG_FIFO_LIFETIME_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8821C) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C) -#define BIT_GET_R_MGG_FIFO_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C) & BIT_MASK_R_MGG_FIFO_LIFETIME_8821C) - - - -#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C 0 -#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C 0xffff -#define BIT_R_MGG_FIFO_VALID_MAP_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C) -#define BIT_GET_R_MGG_FIFO_VALID_MAP_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C) - - +#define BIT_R_MACID_RELEASE_SUCCESS_3_8821C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) +#define BITS_R_MACID_RELEASE_SUCCESS_3_8821C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8821C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8821C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8821C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8821C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8821C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_3_8821C(v)) + +/* 2 REG_MGQ_FIFO_WRITE_POINTER_8821C */ +#define BIT_MGQ_FIFO_OV_8821C BIT(7) +#define BIT_MGQ_FIFO_WPTR_ERROR_8821C BIT(6) +#define BIT_EN_MGQ_FIFO_LIFETIME_8821C BIT(5) + +#define BIT_SHIFT_MGQ_FIFO_WPTR_8821C 0 +#define BIT_MASK_MGQ_FIFO_WPTR_8821C 0x1f +#define BIT_MGQ_FIFO_WPTR_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_WPTR_8821C) << BIT_SHIFT_MGQ_FIFO_WPTR_8821C) +#define BITS_MGQ_FIFO_WPTR_8821C \ + (BIT_MASK_MGQ_FIFO_WPTR_8821C << BIT_SHIFT_MGQ_FIFO_WPTR_8821C) +#define BIT_CLEAR_MGQ_FIFO_WPTR_8821C(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8821C)) +#define BIT_GET_MGQ_FIFO_WPTR_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8821C) & BIT_MASK_MGQ_FIFO_WPTR_8821C) +#define BIT_SET_MGQ_FIFO_WPTR_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_WPTR_8821C(x) | BIT_MGQ_FIFO_WPTR_8821C(v)) + +/* 2 REG_MGQ_FIFO_READ_POINTER_8821C */ + +#define BIT_SHIFT_MGQ_FIFO_SIZE_8821C 14 +#define BIT_MASK_MGQ_FIFO_SIZE_8821C 0x3 +#define BIT_MGQ_FIFO_SIZE_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_SIZE_8821C) << BIT_SHIFT_MGQ_FIFO_SIZE_8821C) +#define BITS_MGQ_FIFO_SIZE_8821C \ + (BIT_MASK_MGQ_FIFO_SIZE_8821C << BIT_SHIFT_MGQ_FIFO_SIZE_8821C) +#define BIT_CLEAR_MGQ_FIFO_SIZE_8821C(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8821C)) +#define BIT_GET_MGQ_FIFO_SIZE_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8821C) & BIT_MASK_MGQ_FIFO_SIZE_8821C) +#define BIT_SET_MGQ_FIFO_SIZE_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_SIZE_8821C(x) | BIT_MGQ_FIFO_SIZE_8821C(v)) + +#define BIT_MGQ_FIFO_PAUSE_8821C BIT(13) + +#define BIT_SHIFT_MGQ_FIFO_RPTR_8821C 8 +#define BIT_MASK_MGQ_FIFO_RPTR_8821C 0x1f +#define BIT_MGQ_FIFO_RPTR_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_RPTR_8821C) << BIT_SHIFT_MGQ_FIFO_RPTR_8821C) +#define BITS_MGQ_FIFO_RPTR_8821C \ + (BIT_MASK_MGQ_FIFO_RPTR_8821C << BIT_SHIFT_MGQ_FIFO_RPTR_8821C) +#define BIT_CLEAR_MGQ_FIFO_RPTR_8821C(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8821C)) +#define BIT_GET_MGQ_FIFO_RPTR_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8821C) & BIT_MASK_MGQ_FIFO_RPTR_8821C) +#define BIT_SET_MGQ_FIFO_RPTR_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_RPTR_8821C(x) | BIT_MGQ_FIFO_RPTR_8821C(v)) + +/* 2 REG_MGQ_FIFO_ENABLE_8821C */ +#define BIT_MGQ_FIFO_EN_8821C BIT(15) + +#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C 12 +#define BIT_MASK_MGQ_FIFO_PG_SIZE_8821C 0x7 +#define BIT_MGQ_FIFO_PG_SIZE_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8821C) \ + << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C) +#define BITS_MGQ_FIFO_PG_SIZE_8821C \ + (BIT_MASK_MGQ_FIFO_PG_SIZE_8821C << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C) +#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8821C(x) \ + ((x) & (~BITS_MGQ_FIFO_PG_SIZE_8821C)) +#define BIT_GET_MGQ_FIFO_PG_SIZE_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C) & \ + BIT_MASK_MGQ_FIFO_PG_SIZE_8821C) +#define BIT_SET_MGQ_FIFO_PG_SIZE_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PG_SIZE_8821C(x) | BIT_MGQ_FIFO_PG_SIZE_8821C(v)) + +#define BIT_SHIFT_MGQ_FIFO_START_PG_8821C 0 +#define BIT_MASK_MGQ_FIFO_START_PG_8821C 0xfff +#define BIT_MGQ_FIFO_START_PG_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_START_PG_8821C) \ + << BIT_SHIFT_MGQ_FIFO_START_PG_8821C) +#define BITS_MGQ_FIFO_START_PG_8821C \ + (BIT_MASK_MGQ_FIFO_START_PG_8821C << BIT_SHIFT_MGQ_FIFO_START_PG_8821C) +#define BIT_CLEAR_MGQ_FIFO_START_PG_8821C(x) \ + ((x) & (~BITS_MGQ_FIFO_START_PG_8821C)) +#define BIT_GET_MGQ_FIFO_START_PG_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8821C) & \ + BIT_MASK_MGQ_FIFO_START_PG_8821C) +#define BIT_SET_MGQ_FIFO_START_PG_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_START_PG_8821C(x) | BIT_MGQ_FIFO_START_PG_8821C(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8821C */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C 0xffff +#define BIT_MGQ_FIFO_REL_INT_MASK_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C) +#define BITS_MGQ_FIFO_REL_INT_MASK_8821C \ + (BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8821C(x) \ + ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8821C)) +#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C) & \ + BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C) +#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8821C(x) | \ + BIT_MGQ_FIFO_REL_INT_MASK_8821C(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8821C */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C 0xffff +#define BIT_MGQ_FIFO_REL_INT_FLAG_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C) +#define BITS_MGQ_FIFO_REL_INT_FLAG_8821C \ + (BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8821C(x) \ + ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8821C)) +#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C) & \ + BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C) +#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8821C(x) | \ + BIT_MGQ_FIFO_REL_INT_FLAG_8821C(v)) + +/* 2 REG_MGQ_FIFO_VALID_MAP_8821C */ + +#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C 0 +#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C 0xffff +#define BIT_MGQ_FIFO_PKT_VALID_MAP_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C) \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C) +#define BITS_MGQ_FIFO_PKT_VALID_MAP_8821C \ + (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C) +#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8821C(x) \ + ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8821C)) +#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C) & \ + BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C) +#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8821C(x) | \ + BIT_MGQ_FIFO_PKT_VALID_MAP_8821C(v)) + +/* 2 REG_MGQ_FIFO_LIFETIME_8821C */ + +#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C 0 +#define BIT_MASK_MGQ_FIFO_LIFETIME_8821C 0xffff +#define BIT_MGQ_FIFO_LIFETIME_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8821C) \ + << BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C) +#define BITS_MGQ_FIFO_LIFETIME_8821C \ + (BIT_MASK_MGQ_FIFO_LIFETIME_8821C << BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C) +#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8821C(x) \ + ((x) & (~BITS_MGQ_FIFO_LIFETIME_8821C)) +#define BIT_GET_MGQ_FIFO_LIFETIME_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C) & \ + BIT_MASK_MGQ_FIFO_LIFETIME_8821C) +#define BIT_SET_MGQ_FIFO_LIFETIME_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_LIFETIME_8821C(x) | BIT_MGQ_FIFO_LIFETIME_8821C(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x7f -#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) - +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) +#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(v)) + +/* 2 REG_SHCUT_SETTING_8821C */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE0_8821C */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE1_8821C */ + +/* 2 REG_SHCUT_LLC_OUI0_8821C */ + +/* 2 REG_SHCUT_LLC_OUI1_8821C */ + +/* 2 REG_SHCUT_LLC_OUI2_8821C */ + +/* 2 REG_MU_TX_CTL_8821C */ +#define BIT_R_MU_P1_WAIT_STATE_EN_8821C BIT(16) + +#define BIT_SHIFT_R_MU_RL_8821C 12 +#define BIT_MASK_R_MU_RL_8821C 0xf +#define BIT_R_MU_RL_8821C(x) \ + (((x) & BIT_MASK_R_MU_RL_8821C) << BIT_SHIFT_R_MU_RL_8821C) +#define BITS_R_MU_RL_8821C (BIT_MASK_R_MU_RL_8821C << BIT_SHIFT_R_MU_RL_8821C) +#define BIT_CLEAR_R_MU_RL_8821C(x) ((x) & (~BITS_R_MU_RL_8821C)) +#define BIT_GET_R_MU_RL_8821C(x) \ + (((x) >> BIT_SHIFT_R_MU_RL_8821C) & BIT_MASK_R_MU_RL_8821C) +#define BIT_SET_R_MU_RL_8821C(x, v) \ + (BIT_CLEAR_R_MU_RL_8821C(x) | BIT_R_MU_RL_8821C(v)) - -/* 2 REG_MU_TX_CTL_8821C (NOT SUPPORT) */ #define BIT_R_FORCE_P1_RATEDOWN_8821C BIT(11) #define BIT_SHIFT_R_MU_TAB_SEL_8821C 8 #define BIT_MASK_R_MU_TAB_SEL_8821C 0x7 -#define BIT_R_MU_TAB_SEL_8821C(x) (((x) & BIT_MASK_R_MU_TAB_SEL_8821C) << BIT_SHIFT_R_MU_TAB_SEL_8821C) -#define BIT_GET_R_MU_TAB_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8821C) & BIT_MASK_R_MU_TAB_SEL_8821C) - +#define BIT_R_MU_TAB_SEL_8821C(x) \ + (((x) & BIT_MASK_R_MU_TAB_SEL_8821C) << BIT_SHIFT_R_MU_TAB_SEL_8821C) +#define BITS_R_MU_TAB_SEL_8821C \ + (BIT_MASK_R_MU_TAB_SEL_8821C << BIT_SHIFT_R_MU_TAB_SEL_8821C) +#define BIT_CLEAR_R_MU_TAB_SEL_8821C(x) ((x) & (~BITS_R_MU_TAB_SEL_8821C)) +#define BIT_GET_R_MU_TAB_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8821C) & BIT_MASK_R_MU_TAB_SEL_8821C) +#define BIT_SET_R_MU_TAB_SEL_8821C(x, v) \ + (BIT_CLEAR_R_MU_TAB_SEL_8821C(x) | BIT_R_MU_TAB_SEL_8821C(v)) #define BIT_R_EN_MU_MIMO_8821C BIT(7) #define BIT_R_EN_REVERS_GTAB_8821C BIT(6) #define BIT_SHIFT_R_MU_TABLE_VALID_8821C 0 #define BIT_MASK_R_MU_TABLE_VALID_8821C 0x3f -#define BIT_R_MU_TABLE_VALID_8821C(x) (((x) & BIT_MASK_R_MU_TABLE_VALID_8821C) << BIT_SHIFT_R_MU_TABLE_VALID_8821C) -#define BIT_GET_R_MU_TABLE_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8821C) & BIT_MASK_R_MU_TABLE_VALID_8821C) - - - -/* 2 REG_MU_STA_GID_VLD_8821C (NOT SUPPORT) */ - -/* 2 REG_NOT_VALID_8821C */ - -#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C 0 -#define BIT_MASK_R_MU_STA_GTAB_VALID_8821C 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) -#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) - - +#define BIT_R_MU_TABLE_VALID_8821C(x) \ + (((x) & BIT_MASK_R_MU_TABLE_VALID_8821C) \ + << BIT_SHIFT_R_MU_TABLE_VALID_8821C) +#define BITS_R_MU_TABLE_VALID_8821C \ + (BIT_MASK_R_MU_TABLE_VALID_8821C << BIT_SHIFT_R_MU_TABLE_VALID_8821C) +#define BIT_CLEAR_R_MU_TABLE_VALID_8821C(x) \ + ((x) & (~BITS_R_MU_TABLE_VALID_8821C)) +#define BIT_GET_R_MU_TABLE_VALID_8821C(x) \ + (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8821C) & \ + BIT_MASK_R_MU_TABLE_VALID_8821C) +#define BIT_SET_R_MU_TABLE_VALID_8821C(x, v) \ + (BIT_CLEAR_R_MU_TABLE_VALID_8821C(x) | BIT_R_MU_TABLE_VALID_8821C(v)) + +/* 2 REG_MU_STA_GID_VLD_8821C */ #define BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C 0 #define BIT_MASK_R_MU_STA_GTAB_VALID_8821C 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) -#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) - - - -/* 2 REG_MU_STA_USER_POS_INFO_8821C (NOT SUPPORT) */ - -/* 2 REG_NOT_VALID_8821C */ - -#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C 0 -#define BIT_MASK_R_MU_STA_GTAB_POSITION_8821C 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) -#define BIT_GET_R_MU_STA_GTAB_POSITION_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) - - - -#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C 0 -#define BIT_MASK_R_MU_STA_GTAB_POSITION_8821C 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) -#define BIT_GET_R_MU_STA_GTAB_POSITION_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) - - - -/* 2 REG_MU_TRX_DBG_CNT_8821C (NOT SUPPORT) */ +#define BIT_R_MU_STA_GTAB_VALID_8821C(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) +#define BITS_R_MU_STA_GTAB_VALID_8821C \ + (BIT_MASK_R_MU_STA_GTAB_VALID_8821C \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8821C(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_VALID_8821C)) +#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & \ + BIT_MASK_R_MU_STA_GTAB_VALID_8821C) +#define BIT_SET_R_MU_STA_GTAB_VALID_8821C(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID_8821C(x) | \ + BIT_R_MU_STA_GTAB_VALID_8821C(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_8821C */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C 0xffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_L_8821C(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C) +#define BITS_R_MU_STA_GTAB_POSITION_L_8821C \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8821C(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_L_8821C)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_L_8821C(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C) +#define BIT_SET_R_MU_STA_GTAB_POSITION_L_8821C(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8821C(x) | \ + BIT_R_MU_STA_GTAB_POSITION_L_8821C(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_H_8821C */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C 0xffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_H_8821C(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C) +#define BITS_R_MU_STA_GTAB_POSITION_H_8821C \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8821C(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_H_8821C)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_H_8821C(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C) +#define BIT_SET_R_MU_STA_GTAB_POSITION_H_8821C(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8821C(x) | \ + BIT_R_MU_STA_GTAB_POSITION_H_8821C(v)) + +/* 2 REG_MU_TRX_DBG_CNT_8821C */ #define BIT_MU_DNGCNT_RST_8821C BIT(20) #define BIT_SHIFT_MU_DBGCNT_SEL_8821C 16 #define BIT_MASK_MU_DBGCNT_SEL_8821C 0xf -#define BIT_MU_DBGCNT_SEL_8821C(x) (((x) & BIT_MASK_MU_DBGCNT_SEL_8821C) << BIT_SHIFT_MU_DBGCNT_SEL_8821C) -#define BIT_GET_MU_DBGCNT_SEL_8821C(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8821C) & BIT_MASK_MU_DBGCNT_SEL_8821C) - - +#define BIT_MU_DBGCNT_SEL_8821C(x) \ + (((x) & BIT_MASK_MU_DBGCNT_SEL_8821C) << BIT_SHIFT_MU_DBGCNT_SEL_8821C) +#define BITS_MU_DBGCNT_SEL_8821C \ + (BIT_MASK_MU_DBGCNT_SEL_8821C << BIT_SHIFT_MU_DBGCNT_SEL_8821C) +#define BIT_CLEAR_MU_DBGCNT_SEL_8821C(x) ((x) & (~BITS_MU_DBGCNT_SEL_8821C)) +#define BIT_GET_MU_DBGCNT_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8821C) & BIT_MASK_MU_DBGCNT_SEL_8821C) +#define BIT_SET_MU_DBGCNT_SEL_8821C(x, v) \ + (BIT_CLEAR_MU_DBGCNT_SEL_8821C(x) | BIT_MU_DBGCNT_SEL_8821C(v)) #define BIT_SHIFT_MU_DNGCNT_8821C 0 #define BIT_MASK_MU_DNGCNT_8821C 0xffff -#define BIT_MU_DNGCNT_8821C(x) (((x) & BIT_MASK_MU_DNGCNT_8821C) << BIT_SHIFT_MU_DNGCNT_8821C) -#define BIT_GET_MU_DNGCNT_8821C(x) (((x) >> BIT_SHIFT_MU_DNGCNT_8821C) & BIT_MASK_MU_DNGCNT_8821C) - - +#define BIT_MU_DNGCNT_8821C(x) \ + (((x) & BIT_MASK_MU_DNGCNT_8821C) << BIT_SHIFT_MU_DNGCNT_8821C) +#define BITS_MU_DNGCNT_8821C \ + (BIT_MASK_MU_DNGCNT_8821C << BIT_SHIFT_MU_DNGCNT_8821C) +#define BIT_CLEAR_MU_DNGCNT_8821C(x) ((x) & (~BITS_MU_DNGCNT_8821C)) +#define BIT_GET_MU_DNGCNT_8821C(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_8821C) & BIT_MASK_MU_DNGCNT_8821C) +#define BIT_SET_MU_DNGCNT_8821C(x, v) \ + (BIT_CLEAR_MU_DNGCNT_8821C(x) | BIT_MU_DNGCNT_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -7125,24 +11938,32 @@ #define BIT_SHIFT_TXOPLIMIT_8821C 16 #define BIT_MASK_TXOPLIMIT_8821C 0x7ff -#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) -#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) - - +#define BIT_TXOPLIMIT_8821C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) +#define BITS_TXOPLIMIT_8821C \ + (BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C) +#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C)) +#define BIT_GET_TXOPLIMIT_8821C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) +#define BIT_SET_TXOPLIMIT_8821C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v)) #define BIT_SHIFT_CW_8821C 8 #define BIT_MASK_CW_8821C 0xff #define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C) +#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C)) #define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) - - +#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v)) #define BIT_SHIFT_AIFS_8821C 0 #define BIT_MASK_AIFS_8821C 0xff #define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) -#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) - - +#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C) +#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C)) +#define BIT_GET_AIFS_8821C(x) \ + (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) +#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v)) /* 2 REG_EDCA_VI_PARAM_8821C */ @@ -7150,24 +11971,32 @@ #define BIT_SHIFT_TXOPLIMIT_8821C 16 #define BIT_MASK_TXOPLIMIT_8821C 0x7ff -#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) -#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) - - +#define BIT_TXOPLIMIT_8821C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) +#define BITS_TXOPLIMIT_8821C \ + (BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C) +#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C)) +#define BIT_GET_TXOPLIMIT_8821C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) +#define BIT_SET_TXOPLIMIT_8821C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v)) #define BIT_SHIFT_CW_8821C 8 #define BIT_MASK_CW_8821C 0xff #define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C) +#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C)) #define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) - - +#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v)) #define BIT_SHIFT_AIFS_8821C 0 #define BIT_MASK_AIFS_8821C 0xff #define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) -#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) - - +#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C) +#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C)) +#define BIT_GET_AIFS_8821C(x) \ + (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) +#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v)) /* 2 REG_EDCA_BE_PARAM_8821C */ @@ -7175,24 +12004,32 @@ #define BIT_SHIFT_TXOPLIMIT_8821C 16 #define BIT_MASK_TXOPLIMIT_8821C 0x7ff -#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) -#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) - - +#define BIT_TXOPLIMIT_8821C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) +#define BITS_TXOPLIMIT_8821C \ + (BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C) +#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C)) +#define BIT_GET_TXOPLIMIT_8821C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) +#define BIT_SET_TXOPLIMIT_8821C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v)) #define BIT_SHIFT_CW_8821C 8 #define BIT_MASK_CW_8821C 0xff #define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C) +#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C)) #define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) - - +#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v)) #define BIT_SHIFT_AIFS_8821C 0 #define BIT_MASK_AIFS_8821C 0xff #define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) -#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) - - +#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C) +#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C)) +#define BIT_GET_AIFS_8821C(x) \ + (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) +#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v)) /* 2 REG_EDCA_BK_PARAM_8821C */ @@ -7200,47 +12037,69 @@ #define BIT_SHIFT_TXOPLIMIT_8821C 16 #define BIT_MASK_TXOPLIMIT_8821C 0x7ff -#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) -#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) - - +#define BIT_TXOPLIMIT_8821C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) +#define BITS_TXOPLIMIT_8821C \ + (BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C) +#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C)) +#define BIT_GET_TXOPLIMIT_8821C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) +#define BIT_SET_TXOPLIMIT_8821C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v)) #define BIT_SHIFT_CW_8821C 8 #define BIT_MASK_CW_8821C 0xff #define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C) +#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C)) #define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) - - +#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v)) #define BIT_SHIFT_AIFS_8821C 0 #define BIT_MASK_AIFS_8821C 0xff #define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) -#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) - - +#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C) +#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C)) +#define BIT_GET_AIFS_8821C(x) \ + (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) +#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v)) /* 2 REG_BCNTCFG_8821C */ #define BIT_SHIFT_BCNCW_MAX_8821C 12 #define BIT_MASK_BCNCW_MAX_8821C 0xf -#define BIT_BCNCW_MAX_8821C(x) (((x) & BIT_MASK_BCNCW_MAX_8821C) << BIT_SHIFT_BCNCW_MAX_8821C) -#define BIT_GET_BCNCW_MAX_8821C(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8821C) & BIT_MASK_BCNCW_MAX_8821C) - - +#define BIT_BCNCW_MAX_8821C(x) \ + (((x) & BIT_MASK_BCNCW_MAX_8821C) << BIT_SHIFT_BCNCW_MAX_8821C) +#define BITS_BCNCW_MAX_8821C \ + (BIT_MASK_BCNCW_MAX_8821C << BIT_SHIFT_BCNCW_MAX_8821C) +#define BIT_CLEAR_BCNCW_MAX_8821C(x) ((x) & (~BITS_BCNCW_MAX_8821C)) +#define BIT_GET_BCNCW_MAX_8821C(x) \ + (((x) >> BIT_SHIFT_BCNCW_MAX_8821C) & BIT_MASK_BCNCW_MAX_8821C) +#define BIT_SET_BCNCW_MAX_8821C(x, v) \ + (BIT_CLEAR_BCNCW_MAX_8821C(x) | BIT_BCNCW_MAX_8821C(v)) #define BIT_SHIFT_BCNCW_MIN_8821C 8 #define BIT_MASK_BCNCW_MIN_8821C 0xf -#define BIT_BCNCW_MIN_8821C(x) (((x) & BIT_MASK_BCNCW_MIN_8821C) << BIT_SHIFT_BCNCW_MIN_8821C) -#define BIT_GET_BCNCW_MIN_8821C(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8821C) & BIT_MASK_BCNCW_MIN_8821C) - - +#define BIT_BCNCW_MIN_8821C(x) \ + (((x) & BIT_MASK_BCNCW_MIN_8821C) << BIT_SHIFT_BCNCW_MIN_8821C) +#define BITS_BCNCW_MIN_8821C \ + (BIT_MASK_BCNCW_MIN_8821C << BIT_SHIFT_BCNCW_MIN_8821C) +#define BIT_CLEAR_BCNCW_MIN_8821C(x) ((x) & (~BITS_BCNCW_MIN_8821C)) +#define BIT_GET_BCNCW_MIN_8821C(x) \ + (((x) >> BIT_SHIFT_BCNCW_MIN_8821C) & BIT_MASK_BCNCW_MIN_8821C) +#define BIT_SET_BCNCW_MIN_8821C(x, v) \ + (BIT_CLEAR_BCNCW_MIN_8821C(x) | BIT_BCNCW_MIN_8821C(v)) #define BIT_SHIFT_BCNIFS_8821C 0 #define BIT_MASK_BCNIFS_8821C 0xff -#define BIT_BCNIFS_8821C(x) (((x) & BIT_MASK_BCNIFS_8821C) << BIT_SHIFT_BCNIFS_8821C) -#define BIT_GET_BCNIFS_8821C(x) (((x) >> BIT_SHIFT_BCNIFS_8821C) & BIT_MASK_BCNIFS_8821C) - - +#define BIT_BCNIFS_8821C(x) \ + (((x) & BIT_MASK_BCNIFS_8821C) << BIT_SHIFT_BCNIFS_8821C) +#define BITS_BCNIFS_8821C (BIT_MASK_BCNIFS_8821C << BIT_SHIFT_BCNIFS_8821C) +#define BIT_CLEAR_BCNIFS_8821C(x) ((x) & (~BITS_BCNIFS_8821C)) +#define BIT_GET_BCNIFS_8821C(x) \ + (((x) >> BIT_SHIFT_BCNIFS_8821C) & BIT_MASK_BCNIFS_8821C) +#define BIT_SET_BCNIFS_8821C(x, v) \ + (BIT_CLEAR_BCNIFS_8821C(x) | BIT_BCNIFS_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -7249,75 +12108,155 @@ #define BIT_SHIFT_PIFS_8821C 0 #define BIT_MASK_PIFS_8821C 0xff #define BIT_PIFS_8821C(x) (((x) & BIT_MASK_PIFS_8821C) << BIT_SHIFT_PIFS_8821C) -#define BIT_GET_PIFS_8821C(x) (((x) >> BIT_SHIFT_PIFS_8821C) & BIT_MASK_PIFS_8821C) - - +#define BITS_PIFS_8821C (BIT_MASK_PIFS_8821C << BIT_SHIFT_PIFS_8821C) +#define BIT_CLEAR_PIFS_8821C(x) ((x) & (~BITS_PIFS_8821C)) +#define BIT_GET_PIFS_8821C(x) \ + (((x) >> BIT_SHIFT_PIFS_8821C) & BIT_MASK_PIFS_8821C) +#define BIT_SET_PIFS_8821C(x, v) (BIT_CLEAR_PIFS_8821C(x) | BIT_PIFS_8821C(v)) /* 2 REG_RDG_PIFS_8821C */ #define BIT_SHIFT_RDG_PIFS_8821C 0 #define BIT_MASK_RDG_PIFS_8821C 0xff -#define BIT_RDG_PIFS_8821C(x) (((x) & BIT_MASK_RDG_PIFS_8821C) << BIT_SHIFT_RDG_PIFS_8821C) -#define BIT_GET_RDG_PIFS_8821C(x) (((x) >> BIT_SHIFT_RDG_PIFS_8821C) & BIT_MASK_RDG_PIFS_8821C) - - +#define BIT_RDG_PIFS_8821C(x) \ + (((x) & BIT_MASK_RDG_PIFS_8821C) << BIT_SHIFT_RDG_PIFS_8821C) +#define BITS_RDG_PIFS_8821C \ + (BIT_MASK_RDG_PIFS_8821C << BIT_SHIFT_RDG_PIFS_8821C) +#define BIT_CLEAR_RDG_PIFS_8821C(x) ((x) & (~BITS_RDG_PIFS_8821C)) +#define BIT_GET_RDG_PIFS_8821C(x) \ + (((x) >> BIT_SHIFT_RDG_PIFS_8821C) & BIT_MASK_RDG_PIFS_8821C) +#define BIT_SET_RDG_PIFS_8821C(x, v) \ + (BIT_CLEAR_RDG_PIFS_8821C(x) | BIT_RDG_PIFS_8821C(v)) /* 2 REG_SIFS_8821C */ #define BIT_SHIFT_SIFS_OFDM_TRX_8821C 24 #define BIT_MASK_SIFS_OFDM_TRX_8821C 0xff -#define BIT_SIFS_OFDM_TRX_8821C(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8821C) << BIT_SHIFT_SIFS_OFDM_TRX_8821C) -#define BIT_GET_SIFS_OFDM_TRX_8821C(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8821C) & BIT_MASK_SIFS_OFDM_TRX_8821C) - - +#define BIT_SIFS_OFDM_TRX_8821C(x) \ + (((x) & BIT_MASK_SIFS_OFDM_TRX_8821C) << BIT_SHIFT_SIFS_OFDM_TRX_8821C) +#define BITS_SIFS_OFDM_TRX_8821C \ + (BIT_MASK_SIFS_OFDM_TRX_8821C << BIT_SHIFT_SIFS_OFDM_TRX_8821C) +#define BIT_CLEAR_SIFS_OFDM_TRX_8821C(x) ((x) & (~BITS_SIFS_OFDM_TRX_8821C)) +#define BIT_GET_SIFS_OFDM_TRX_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8821C) & BIT_MASK_SIFS_OFDM_TRX_8821C) +#define BIT_SET_SIFS_OFDM_TRX_8821C(x, v) \ + (BIT_CLEAR_SIFS_OFDM_TRX_8821C(x) | BIT_SIFS_OFDM_TRX_8821C(v)) #define BIT_SHIFT_SIFS_CCK_TRX_8821C 16 #define BIT_MASK_SIFS_CCK_TRX_8821C 0xff -#define BIT_SIFS_CCK_TRX_8821C(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8821C) << BIT_SHIFT_SIFS_CCK_TRX_8821C) -#define BIT_GET_SIFS_CCK_TRX_8821C(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8821C) & BIT_MASK_SIFS_CCK_TRX_8821C) - - +#define BIT_SIFS_CCK_TRX_8821C(x) \ + (((x) & BIT_MASK_SIFS_CCK_TRX_8821C) << BIT_SHIFT_SIFS_CCK_TRX_8821C) +#define BITS_SIFS_CCK_TRX_8821C \ + (BIT_MASK_SIFS_CCK_TRX_8821C << BIT_SHIFT_SIFS_CCK_TRX_8821C) +#define BIT_CLEAR_SIFS_CCK_TRX_8821C(x) ((x) & (~BITS_SIFS_CCK_TRX_8821C)) +#define BIT_GET_SIFS_CCK_TRX_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8821C) & BIT_MASK_SIFS_CCK_TRX_8821C) +#define BIT_SET_SIFS_CCK_TRX_8821C(x, v) \ + (BIT_CLEAR_SIFS_CCK_TRX_8821C(x) | BIT_SIFS_CCK_TRX_8821C(v)) #define BIT_SHIFT_SIFS_OFDM_CTX_8821C 8 #define BIT_MASK_SIFS_OFDM_CTX_8821C 0xff -#define BIT_SIFS_OFDM_CTX_8821C(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8821C) << BIT_SHIFT_SIFS_OFDM_CTX_8821C) -#define BIT_GET_SIFS_OFDM_CTX_8821C(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8821C) & BIT_MASK_SIFS_OFDM_CTX_8821C) - - +#define BIT_SIFS_OFDM_CTX_8821C(x) \ + (((x) & BIT_MASK_SIFS_OFDM_CTX_8821C) << BIT_SHIFT_SIFS_OFDM_CTX_8821C) +#define BITS_SIFS_OFDM_CTX_8821C \ + (BIT_MASK_SIFS_OFDM_CTX_8821C << BIT_SHIFT_SIFS_OFDM_CTX_8821C) +#define BIT_CLEAR_SIFS_OFDM_CTX_8821C(x) ((x) & (~BITS_SIFS_OFDM_CTX_8821C)) +#define BIT_GET_SIFS_OFDM_CTX_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8821C) & BIT_MASK_SIFS_OFDM_CTX_8821C) +#define BIT_SET_SIFS_OFDM_CTX_8821C(x, v) \ + (BIT_CLEAR_SIFS_OFDM_CTX_8821C(x) | BIT_SIFS_OFDM_CTX_8821C(v)) #define BIT_SHIFT_SIFS_CCK_CTX_8821C 0 #define BIT_MASK_SIFS_CCK_CTX_8821C 0xff -#define BIT_SIFS_CCK_CTX_8821C(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8821C) << BIT_SHIFT_SIFS_CCK_CTX_8821C) -#define BIT_GET_SIFS_CCK_CTX_8821C(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8821C) & BIT_MASK_SIFS_CCK_CTX_8821C) - - +#define BIT_SIFS_CCK_CTX_8821C(x) \ + (((x) & BIT_MASK_SIFS_CCK_CTX_8821C) << BIT_SHIFT_SIFS_CCK_CTX_8821C) +#define BITS_SIFS_CCK_CTX_8821C \ + (BIT_MASK_SIFS_CCK_CTX_8821C << BIT_SHIFT_SIFS_CCK_CTX_8821C) +#define BIT_CLEAR_SIFS_CCK_CTX_8821C(x) ((x) & (~BITS_SIFS_CCK_CTX_8821C)) +#define BIT_GET_SIFS_CCK_CTX_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8821C) & BIT_MASK_SIFS_CCK_CTX_8821C) +#define BIT_SET_SIFS_CCK_CTX_8821C(x, v) \ + (BIT_CLEAR_SIFS_CCK_CTX_8821C(x) | BIT_SIFS_CCK_CTX_8821C(v)) /* 2 REG_TSFTR_SYN_OFFSET_8821C */ #define BIT_SHIFT_TSFTR_SNC_OFFSET_8821C 0 #define BIT_MASK_TSFTR_SNC_OFFSET_8821C 0xffff -#define BIT_TSFTR_SNC_OFFSET_8821C(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8821C) << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) -#define BIT_GET_TSFTR_SNC_OFFSET_8821C(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) & BIT_MASK_TSFTR_SNC_OFFSET_8821C) - - +#define BIT_TSFTR_SNC_OFFSET_8821C(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8821C) \ + << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) +#define BITS_TSFTR_SNC_OFFSET_8821C \ + (BIT_MASK_TSFTR_SNC_OFFSET_8821C << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_8821C(x) \ + ((x) & (~BITS_TSFTR_SNC_OFFSET_8821C)) +#define BIT_GET_TSFTR_SNC_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) & \ + BIT_MASK_TSFTR_SNC_OFFSET_8821C) +#define BIT_SET_TSFTR_SNC_OFFSET_8821C(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET_8821C(x) | BIT_TSFTR_SNC_OFFSET_8821C(v)) /* 2 REG_AGGR_BREAK_TIME_8821C */ #define BIT_SHIFT_AGGR_BK_TIME_8821C 0 #define BIT_MASK_AGGR_BK_TIME_8821C 0xff -#define BIT_AGGR_BK_TIME_8821C(x) (((x) & BIT_MASK_AGGR_BK_TIME_8821C) << BIT_SHIFT_AGGR_BK_TIME_8821C) -#define BIT_GET_AGGR_BK_TIME_8821C(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8821C) & BIT_MASK_AGGR_BK_TIME_8821C) - - +#define BIT_AGGR_BK_TIME_8821C(x) \ + (((x) & BIT_MASK_AGGR_BK_TIME_8821C) << BIT_SHIFT_AGGR_BK_TIME_8821C) +#define BITS_AGGR_BK_TIME_8821C \ + (BIT_MASK_AGGR_BK_TIME_8821C << BIT_SHIFT_AGGR_BK_TIME_8821C) +#define BIT_CLEAR_AGGR_BK_TIME_8821C(x) ((x) & (~BITS_AGGR_BK_TIME_8821C)) +#define BIT_GET_AGGR_BK_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_AGGR_BK_TIME_8821C) & BIT_MASK_AGGR_BK_TIME_8821C) +#define BIT_SET_AGGR_BK_TIME_8821C(x, v) \ + (BIT_CLEAR_AGGR_BK_TIME_8821C(x) | BIT_AGGR_BK_TIME_8821C(v)) /* 2 REG_SLOT_8821C */ #define BIT_SHIFT_SLOT_8821C 0 #define BIT_MASK_SLOT_8821C 0xff #define BIT_SLOT_8821C(x) (((x) & BIT_MASK_SLOT_8821C) << BIT_SHIFT_SLOT_8821C) -#define BIT_GET_SLOT_8821C(x) (((x) >> BIT_SHIFT_SLOT_8821C) & BIT_MASK_SLOT_8821C) - +#define BITS_SLOT_8821C (BIT_MASK_SLOT_8821C << BIT_SHIFT_SLOT_8821C) +#define BIT_CLEAR_SLOT_8821C(x) ((x) & (~BITS_SLOT_8821C)) +#define BIT_GET_SLOT_8821C(x) \ + (((x) >> BIT_SHIFT_SLOT_8821C) & BIT_MASK_SLOT_8821C) +#define BIT_SET_SLOT_8821C(x, v) (BIT_CLEAR_SLOT_8821C(x) | BIT_SLOT_8821C(v)) + +/* 2 REG_NOA_ON_ERLY_TIME_8821C */ + +#define BIT_SHIFT__NOA_ON_ERLY_TIME_8821C 0 +#define BIT_MASK__NOA_ON_ERLY_TIME_8821C 0xff +#define BIT__NOA_ON_ERLY_TIME_8821C(x) \ + (((x) & BIT_MASK__NOA_ON_ERLY_TIME_8821C) \ + << BIT_SHIFT__NOA_ON_ERLY_TIME_8821C) +#define BITS__NOA_ON_ERLY_TIME_8821C \ + (BIT_MASK__NOA_ON_ERLY_TIME_8821C << BIT_SHIFT__NOA_ON_ERLY_TIME_8821C) +#define BIT_CLEAR__NOA_ON_ERLY_TIME_8821C(x) \ + ((x) & (~BITS__NOA_ON_ERLY_TIME_8821C)) +#define BIT_GET__NOA_ON_ERLY_TIME_8821C(x) \ + (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8821C) & \ + BIT_MASK__NOA_ON_ERLY_TIME_8821C) +#define BIT_SET__NOA_ON_ERLY_TIME_8821C(x, v) \ + (BIT_CLEAR__NOA_ON_ERLY_TIME_8821C(x) | BIT__NOA_ON_ERLY_TIME_8821C(v)) + +/* 2 REG_NOA_OFF_ERLY_TIME_8821C */ + +#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C 0 +#define BIT_MASK__NOA_OFF_ERLY_TIME_8821C 0xff +#define BIT__NOA_OFF_ERLY_TIME_8821C(x) \ + (((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8821C) \ + << BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C) +#define BITS__NOA_OFF_ERLY_TIME_8821C \ + (BIT_MASK__NOA_OFF_ERLY_TIME_8821C \ + << BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C) +#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8821C(x) \ + ((x) & (~BITS__NOA_OFF_ERLY_TIME_8821C)) +#define BIT_GET__NOA_OFF_ERLY_TIME_8821C(x) \ + (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C) & \ + BIT_MASK__NOA_OFF_ERLY_TIME_8821C) +#define BIT_SET__NOA_OFF_ERLY_TIME_8821C(x, v) \ + (BIT_CLEAR__NOA_OFF_ERLY_TIME_8821C(x) | \ + BIT__NOA_OFF_ERLY_TIME_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -7329,9 +12268,15 @@ #define BIT_SHIFT_TXQ_NAV_MSK_8821C 8 #define BIT_MASK_TXQ_NAV_MSK_8821C 0xf -#define BIT_TXQ_NAV_MSK_8821C(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8821C) << BIT_SHIFT_TXQ_NAV_MSK_8821C) -#define BIT_GET_TXQ_NAV_MSK_8821C(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8821C) & BIT_MASK_TXQ_NAV_MSK_8821C) - +#define BIT_TXQ_NAV_MSK_8821C(x) \ + (((x) & BIT_MASK_TXQ_NAV_MSK_8821C) << BIT_SHIFT_TXQ_NAV_MSK_8821C) +#define BITS_TXQ_NAV_MSK_8821C \ + (BIT_MASK_TXQ_NAV_MSK_8821C << BIT_SHIFT_TXQ_NAV_MSK_8821C) +#define BIT_CLEAR_TXQ_NAV_MSK_8821C(x) ((x) & (~BITS_TXQ_NAV_MSK_8821C)) +#define BIT_GET_TXQ_NAV_MSK_8821C(x) \ + (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8821C) & BIT_MASK_TXQ_NAV_MSK_8821C) +#define BIT_SET_TXQ_NAV_MSK_8821C(x, v) \ + (BIT_CLEAR_TXQ_NAV_MSK_8821C(x) | BIT_TXQ_NAV_MSK_8821C(v)) #define BIT_DIS_CW_8821C BIT(7) #define BIT_NAV_END_TXOP_8821C BIT(6) @@ -7407,17 +12352,29 @@ #define BIT_SHIFT_CCA_FILTER_THRS_8821C 8 #define BIT_MASK_CCA_FILTER_THRS_8821C 0xff -#define BIT_CCA_FILTER_THRS_8821C(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8821C) << BIT_SHIFT_CCA_FILTER_THRS_8821C) -#define BIT_GET_CCA_FILTER_THRS_8821C(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8821C) & BIT_MASK_CCA_FILTER_THRS_8821C) - - +#define BIT_CCA_FILTER_THRS_8821C(x) \ + (((x) & BIT_MASK_CCA_FILTER_THRS_8821C) \ + << BIT_SHIFT_CCA_FILTER_THRS_8821C) +#define BITS_CCA_FILTER_THRS_8821C \ + (BIT_MASK_CCA_FILTER_THRS_8821C << BIT_SHIFT_CCA_FILTER_THRS_8821C) +#define BIT_CLEAR_CCA_FILTER_THRS_8821C(x) ((x) & (~BITS_CCA_FILTER_THRS_8821C)) +#define BIT_GET_CCA_FILTER_THRS_8821C(x) \ + (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8821C) & \ + BIT_MASK_CCA_FILTER_THRS_8821C) +#define BIT_SET_CCA_FILTER_THRS_8821C(x, v) \ + (BIT_CLEAR_CCA_FILTER_THRS_8821C(x) | BIT_CCA_FILTER_THRS_8821C(v)) #define BIT_SHIFT_EDCCA_THRS_8821C 0 #define BIT_MASK_EDCCA_THRS_8821C 0xff -#define BIT_EDCCA_THRS_8821C(x) (((x) & BIT_MASK_EDCCA_THRS_8821C) << BIT_SHIFT_EDCCA_THRS_8821C) -#define BIT_GET_EDCCA_THRS_8821C(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8821C) & BIT_MASK_EDCCA_THRS_8821C) - - +#define BIT_EDCCA_THRS_8821C(x) \ + (((x) & BIT_MASK_EDCCA_THRS_8821C) << BIT_SHIFT_EDCCA_THRS_8821C) +#define BITS_EDCCA_THRS_8821C \ + (BIT_MASK_EDCCA_THRS_8821C << BIT_SHIFT_EDCCA_THRS_8821C) +#define BIT_CLEAR_EDCCA_THRS_8821C(x) ((x) & (~BITS_EDCCA_THRS_8821C)) +#define BIT_GET_EDCCA_THRS_8821C(x) \ + (((x) >> BIT_SHIFT_EDCCA_THRS_8821C) & BIT_MASK_EDCCA_THRS_8821C) +#define BIT_SET_EDCCA_THRS_8821C(x, v) \ + (BIT_CLEAR_EDCCA_THRS_8821C(x) | BIT_EDCCA_THRS_8821C(v)) /* 2 REG_P2PPS_SPEC_STATE_8821C */ #define BIT_SPEC_POWER_STATE_8821C BIT(7) @@ -7433,14 +12390,22 @@ /* 2 REG_BAR_TX_CTRL_8821C */ -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_P2PON_DIS_TXTIME_8821C */ #define BIT_SHIFT_P2PON_DIS_TXTIME_8821C 0 #define BIT_MASK_P2PON_DIS_TXTIME_8821C 0xff -#define BIT_P2PON_DIS_TXTIME_8821C(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8821C) << BIT_SHIFT_P2PON_DIS_TXTIME_8821C) -#define BIT_GET_P2PON_DIS_TXTIME_8821C(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8821C) & BIT_MASK_P2PON_DIS_TXTIME_8821C) - - +#define BIT_P2PON_DIS_TXTIME_8821C(x) \ + (((x) & BIT_MASK_P2PON_DIS_TXTIME_8821C) \ + << BIT_SHIFT_P2PON_DIS_TXTIME_8821C) +#define BITS_P2PON_DIS_TXTIME_8821C \ + (BIT_MASK_P2PON_DIS_TXTIME_8821C << BIT_SHIFT_P2PON_DIS_TXTIME_8821C) +#define BIT_CLEAR_P2PON_DIS_TXTIME_8821C(x) \ + ((x) & (~BITS_P2PON_DIS_TXTIME_8821C)) +#define BIT_GET_P2PON_DIS_TXTIME_8821C(x) \ + (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8821C) & \ + BIT_MASK_P2PON_DIS_TXTIME_8821C) +#define BIT_SET_P2PON_DIS_TXTIME_8821C(x, v) \ + (BIT_CLEAR_P2PON_DIS_TXTIME_8821C(x) | BIT_P2PON_DIS_TXTIME_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -7456,17 +12421,35 @@ #define BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C 8 #define BIT_MASK_TBTT_HOLD_TIME_AP_8821C 0xfff -#define BIT_TBTT_HOLD_TIME_AP_8821C(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) -#define BIT_GET_TBTT_HOLD_TIME_AP_8821C(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C) - - +#define BIT_TBTT_HOLD_TIME_AP_8821C(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C) \ + << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) +#define BITS_TBTT_HOLD_TIME_AP_8821C \ + (BIT_MASK_TBTT_HOLD_TIME_AP_8821C << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) +#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8821C(x) \ + ((x) & (~BITS_TBTT_HOLD_TIME_AP_8821C)) +#define BIT_GET_TBTT_HOLD_TIME_AP_8821C(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) & \ + BIT_MASK_TBTT_HOLD_TIME_AP_8821C) +#define BIT_SET_TBTT_HOLD_TIME_AP_8821C(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_AP_8821C(x) | BIT_TBTT_HOLD_TIME_AP_8821C(v)) #define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C 0 #define BIT_MASK_TBTT_PROHIBIT_SETUP_8821C 0xf -#define BIT_TBTT_PROHIBIT_SETUP_8821C(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) -#define BIT_GET_TBTT_PROHIBIT_SETUP_8821C(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) - - +#define BIT_TBTT_PROHIBIT_SETUP_8821C(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) +#define BITS_TBTT_PROHIBIT_SETUP_8821C \ + (BIT_MASK_TBTT_PROHIBIT_SETUP_8821C \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8821C(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8821C)) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8821C(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) & \ + BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) +#define BIT_SET_TBTT_PROHIBIT_SETUP_8821C(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8821C(x) | \ + BIT_TBTT_PROHIBIT_SETUP_8821C(v)) /* 2 REG_P2PPS_STATE_8821C */ #define BIT_POWER_STATE_8821C BIT(7) @@ -7482,19 +12465,31 @@ #define BIT_SHIFT_RD_NAV_PROT_NXT_8821C 0 #define BIT_MASK_RD_NAV_PROT_NXT_8821C 0xffff -#define BIT_RD_NAV_PROT_NXT_8821C(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8821C) << BIT_SHIFT_RD_NAV_PROT_NXT_8821C) -#define BIT_GET_RD_NAV_PROT_NXT_8821C(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8821C) & BIT_MASK_RD_NAV_PROT_NXT_8821C) - - +#define BIT_RD_NAV_PROT_NXT_8821C(x) \ + (((x) & BIT_MASK_RD_NAV_PROT_NXT_8821C) \ + << BIT_SHIFT_RD_NAV_PROT_NXT_8821C) +#define BITS_RD_NAV_PROT_NXT_8821C \ + (BIT_MASK_RD_NAV_PROT_NXT_8821C << BIT_SHIFT_RD_NAV_PROT_NXT_8821C) +#define BIT_CLEAR_RD_NAV_PROT_NXT_8821C(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8821C)) +#define BIT_GET_RD_NAV_PROT_NXT_8821C(x) \ + (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8821C) & \ + BIT_MASK_RD_NAV_PROT_NXT_8821C) +#define BIT_SET_RD_NAV_PROT_NXT_8821C(x, v) \ + (BIT_CLEAR_RD_NAV_PROT_NXT_8821C(x) | BIT_RD_NAV_PROT_NXT_8821C(v)) /* 2 REG_NAV_PROT_LEN_8821C */ #define BIT_SHIFT_NAV_PROT_LEN_8821C 0 #define BIT_MASK_NAV_PROT_LEN_8821C 0xffff -#define BIT_NAV_PROT_LEN_8821C(x) (((x) & BIT_MASK_NAV_PROT_LEN_8821C) << BIT_SHIFT_NAV_PROT_LEN_8821C) -#define BIT_GET_NAV_PROT_LEN_8821C(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8821C) & BIT_MASK_NAV_PROT_LEN_8821C) - - +#define BIT_NAV_PROT_LEN_8821C(x) \ + (((x) & BIT_MASK_NAV_PROT_LEN_8821C) << BIT_SHIFT_NAV_PROT_LEN_8821C) +#define BITS_NAV_PROT_LEN_8821C \ + (BIT_MASK_NAV_PROT_LEN_8821C << BIT_SHIFT_NAV_PROT_LEN_8821C) +#define BIT_CLEAR_NAV_PROT_LEN_8821C(x) ((x) & (~BITS_NAV_PROT_LEN_8821C)) +#define BIT_GET_NAV_PROT_LEN_8821C(x) \ + (((x) >> BIT_SHIFT_NAV_PROT_LEN_8821C) & BIT_MASK_NAV_PROT_LEN_8821C) +#define BIT_SET_NAV_PROT_LEN_8821C(x, v) \ + (BIT_CLEAR_NAV_PROT_LEN_8821C(x) | BIT_NAV_PROT_LEN_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -7522,10 +12517,15 @@ #define BIT_SHIFT_MBID_BCN_NUM_8821C 0 #define BIT_MASK_MBID_BCN_NUM_8821C 0x7 -#define BIT_MBID_BCN_NUM_8821C(x) (((x) & BIT_MASK_MBID_BCN_NUM_8821C) << BIT_SHIFT_MBID_BCN_NUM_8821C) -#define BIT_GET_MBID_BCN_NUM_8821C(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8821C) & BIT_MASK_MBID_BCN_NUM_8821C) - - +#define BIT_MBID_BCN_NUM_8821C(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_8821C) << BIT_SHIFT_MBID_BCN_NUM_8821C) +#define BITS_MBID_BCN_NUM_8821C \ + (BIT_MASK_MBID_BCN_NUM_8821C << BIT_SHIFT_MBID_BCN_NUM_8821C) +#define BIT_CLEAR_MBID_BCN_NUM_8821C(x) ((x) & (~BITS_MBID_BCN_NUM_8821C)) +#define BIT_GET_MBID_BCN_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_8821C) & BIT_MASK_MBID_BCN_NUM_8821C) +#define BIT_SET_MBID_BCN_NUM_8821C(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_8821C(x) | BIT_MBID_BCN_NUM_8821C(v)) /* 2 REG_DUAL_TSF_RST_8821C */ #define BIT_FREECNT_RST_8821C BIT(5) @@ -7539,189 +12539,329 @@ #define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C 28 #define BIT_MASK_BCN_TIMER_SEL_FWRD_8821C 0x7 -#define BIT_BCN_TIMER_SEL_FWRD_8821C(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) -#define BIT_GET_BCN_TIMER_SEL_FWRD_8821C(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) - - +#define BIT_BCN_TIMER_SEL_FWRD_8821C(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) +#define BITS_BCN_TIMER_SEL_FWRD_8821C \ + (BIT_MASK_BCN_TIMER_SEL_FWRD_8821C \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8821C(x) \ + ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8821C)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) & \ + BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) +#define BIT_SET_BCN_TIMER_SEL_FWRD_8821C(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8821C(x) | \ + BIT_BCN_TIMER_SEL_FWRD_8821C(v)) #define BIT_SHIFT_BCN_SPACE_CLINT0_8821C 16 #define BIT_MASK_BCN_SPACE_CLINT0_8821C 0xfff -#define BIT_BCN_SPACE_CLINT0_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8821C) << BIT_SHIFT_BCN_SPACE_CLINT0_8821C) -#define BIT_GET_BCN_SPACE_CLINT0_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8821C) & BIT_MASK_BCN_SPACE_CLINT0_8821C) - - +#define BIT_BCN_SPACE_CLINT0_8821C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT0_8821C) \ + << BIT_SHIFT_BCN_SPACE_CLINT0_8821C) +#define BITS_BCN_SPACE_CLINT0_8821C \ + (BIT_MASK_BCN_SPACE_CLINT0_8821C << BIT_SHIFT_BCN_SPACE_CLINT0_8821C) +#define BIT_CLEAR_BCN_SPACE_CLINT0_8821C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT0_8821C)) +#define BIT_GET_BCN_SPACE_CLINT0_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8821C) & \ + BIT_MASK_BCN_SPACE_CLINT0_8821C) +#define BIT_SET_BCN_SPACE_CLINT0_8821C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT0_8821C(x) | BIT_BCN_SPACE_CLINT0_8821C(v)) #define BIT_SHIFT_BCN_SPACE0_8821C 0 #define BIT_MASK_BCN_SPACE0_8821C 0xffff -#define BIT_BCN_SPACE0_8821C(x) (((x) & BIT_MASK_BCN_SPACE0_8821C) << BIT_SHIFT_BCN_SPACE0_8821C) -#define BIT_GET_BCN_SPACE0_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8821C) & BIT_MASK_BCN_SPACE0_8821C) - - +#define BIT_BCN_SPACE0_8821C(x) \ + (((x) & BIT_MASK_BCN_SPACE0_8821C) << BIT_SHIFT_BCN_SPACE0_8821C) +#define BITS_BCN_SPACE0_8821C \ + (BIT_MASK_BCN_SPACE0_8821C << BIT_SHIFT_BCN_SPACE0_8821C) +#define BIT_CLEAR_BCN_SPACE0_8821C(x) ((x) & (~BITS_BCN_SPACE0_8821C)) +#define BIT_GET_BCN_SPACE0_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE0_8821C) & BIT_MASK_BCN_SPACE0_8821C) +#define BIT_SET_BCN_SPACE0_8821C(x, v) \ + (BIT_CLEAR_BCN_SPACE0_8821C(x) | BIT_BCN_SPACE0_8821C(v)) /* 2 REG_DRVERLYINT_8821C */ #define BIT_SHIFT_DRVERLYITV_8821C 0 #define BIT_MASK_DRVERLYITV_8821C 0xff -#define BIT_DRVERLYITV_8821C(x) (((x) & BIT_MASK_DRVERLYITV_8821C) << BIT_SHIFT_DRVERLYITV_8821C) -#define BIT_GET_DRVERLYITV_8821C(x) (((x) >> BIT_SHIFT_DRVERLYITV_8821C) & BIT_MASK_DRVERLYITV_8821C) - - +#define BIT_DRVERLYITV_8821C(x) \ + (((x) & BIT_MASK_DRVERLYITV_8821C) << BIT_SHIFT_DRVERLYITV_8821C) +#define BITS_DRVERLYITV_8821C \ + (BIT_MASK_DRVERLYITV_8821C << BIT_SHIFT_DRVERLYITV_8821C) +#define BIT_CLEAR_DRVERLYITV_8821C(x) ((x) & (~BITS_DRVERLYITV_8821C)) +#define BIT_GET_DRVERLYITV_8821C(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV_8821C) & BIT_MASK_DRVERLYITV_8821C) +#define BIT_SET_DRVERLYITV_8821C(x, v) \ + (BIT_CLEAR_DRVERLYITV_8821C(x) | BIT_DRVERLYITV_8821C(v)) /* 2 REG_BCNDMATIM_8821C */ #define BIT_SHIFT_BCNDMATIM_8821C 0 #define BIT_MASK_BCNDMATIM_8821C 0xff -#define BIT_BCNDMATIM_8821C(x) (((x) & BIT_MASK_BCNDMATIM_8821C) << BIT_SHIFT_BCNDMATIM_8821C) -#define BIT_GET_BCNDMATIM_8821C(x) (((x) >> BIT_SHIFT_BCNDMATIM_8821C) & BIT_MASK_BCNDMATIM_8821C) - - +#define BIT_BCNDMATIM_8821C(x) \ + (((x) & BIT_MASK_BCNDMATIM_8821C) << BIT_SHIFT_BCNDMATIM_8821C) +#define BITS_BCNDMATIM_8821C \ + (BIT_MASK_BCNDMATIM_8821C << BIT_SHIFT_BCNDMATIM_8821C) +#define BIT_CLEAR_BCNDMATIM_8821C(x) ((x) & (~BITS_BCNDMATIM_8821C)) +#define BIT_GET_BCNDMATIM_8821C(x) \ + (((x) >> BIT_SHIFT_BCNDMATIM_8821C) & BIT_MASK_BCNDMATIM_8821C) +#define BIT_SET_BCNDMATIM_8821C(x, v) \ + (BIT_CLEAR_BCNDMATIM_8821C(x) | BIT_BCNDMATIM_8821C(v)) /* 2 REG_ATIMWND_8821C */ #define BIT_SHIFT_ATIMWND0_8821C 0 #define BIT_MASK_ATIMWND0_8821C 0xffff -#define BIT_ATIMWND0_8821C(x) (((x) & BIT_MASK_ATIMWND0_8821C) << BIT_SHIFT_ATIMWND0_8821C) -#define BIT_GET_ATIMWND0_8821C(x) (((x) >> BIT_SHIFT_ATIMWND0_8821C) & BIT_MASK_ATIMWND0_8821C) - - +#define BIT_ATIMWND0_8821C(x) \ + (((x) & BIT_MASK_ATIMWND0_8821C) << BIT_SHIFT_ATIMWND0_8821C) +#define BITS_ATIMWND0_8821C \ + (BIT_MASK_ATIMWND0_8821C << BIT_SHIFT_ATIMWND0_8821C) +#define BIT_CLEAR_ATIMWND0_8821C(x) ((x) & (~BITS_ATIMWND0_8821C)) +#define BIT_GET_ATIMWND0_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND0_8821C) & BIT_MASK_ATIMWND0_8821C) +#define BIT_SET_ATIMWND0_8821C(x, v) \ + (BIT_CLEAR_ATIMWND0_8821C(x) | BIT_ATIMWND0_8821C(v)) /* 2 REG_USTIME_TSF_8821C */ #define BIT_SHIFT_USTIME_TSF_V1_8821C 0 #define BIT_MASK_USTIME_TSF_V1_8821C 0xff -#define BIT_USTIME_TSF_V1_8821C(x) (((x) & BIT_MASK_USTIME_TSF_V1_8821C) << BIT_SHIFT_USTIME_TSF_V1_8821C) -#define BIT_GET_USTIME_TSF_V1_8821C(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8821C) & BIT_MASK_USTIME_TSF_V1_8821C) - - +#define BIT_USTIME_TSF_V1_8821C(x) \ + (((x) & BIT_MASK_USTIME_TSF_V1_8821C) << BIT_SHIFT_USTIME_TSF_V1_8821C) +#define BITS_USTIME_TSF_V1_8821C \ + (BIT_MASK_USTIME_TSF_V1_8821C << BIT_SHIFT_USTIME_TSF_V1_8821C) +#define BIT_CLEAR_USTIME_TSF_V1_8821C(x) ((x) & (~BITS_USTIME_TSF_V1_8821C)) +#define BIT_GET_USTIME_TSF_V1_8821C(x) \ + (((x) >> BIT_SHIFT_USTIME_TSF_V1_8821C) & BIT_MASK_USTIME_TSF_V1_8821C) +#define BIT_SET_USTIME_TSF_V1_8821C(x, v) \ + (BIT_CLEAR_USTIME_TSF_V1_8821C(x) | BIT_USTIME_TSF_V1_8821C(v)) /* 2 REG_BCN_MAX_ERR_8821C */ #define BIT_SHIFT_BCN_MAX_ERR_8821C 0 #define BIT_MASK_BCN_MAX_ERR_8821C 0xff -#define BIT_BCN_MAX_ERR_8821C(x) (((x) & BIT_MASK_BCN_MAX_ERR_8821C) << BIT_SHIFT_BCN_MAX_ERR_8821C) -#define BIT_GET_BCN_MAX_ERR_8821C(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8821C) & BIT_MASK_BCN_MAX_ERR_8821C) - - +#define BIT_BCN_MAX_ERR_8821C(x) \ + (((x) & BIT_MASK_BCN_MAX_ERR_8821C) << BIT_SHIFT_BCN_MAX_ERR_8821C) +#define BITS_BCN_MAX_ERR_8821C \ + (BIT_MASK_BCN_MAX_ERR_8821C << BIT_SHIFT_BCN_MAX_ERR_8821C) +#define BIT_CLEAR_BCN_MAX_ERR_8821C(x) ((x) & (~BITS_BCN_MAX_ERR_8821C)) +#define BIT_GET_BCN_MAX_ERR_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_MAX_ERR_8821C) & BIT_MASK_BCN_MAX_ERR_8821C) +#define BIT_SET_BCN_MAX_ERR_8821C(x, v) \ + (BIT_CLEAR_BCN_MAX_ERR_8821C(x) | BIT_BCN_MAX_ERR_8821C(v)) /* 2 REG_RXTSF_OFFSET_CCK_8821C */ #define BIT_SHIFT_CCK_RXTSF_OFFSET_8821C 0 #define BIT_MASK_CCK_RXTSF_OFFSET_8821C 0xff -#define BIT_CCK_RXTSF_OFFSET_8821C(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8821C) << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) -#define BIT_GET_CCK_RXTSF_OFFSET_8821C(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) & BIT_MASK_CCK_RXTSF_OFFSET_8821C) - - +#define BIT_CCK_RXTSF_OFFSET_8821C(x) \ + (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8821C) \ + << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) +#define BITS_CCK_RXTSF_OFFSET_8821C \ + (BIT_MASK_CCK_RXTSF_OFFSET_8821C << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) +#define BIT_CLEAR_CCK_RXTSF_OFFSET_8821C(x) \ + ((x) & (~BITS_CCK_RXTSF_OFFSET_8821C)) +#define BIT_GET_CCK_RXTSF_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) & \ + BIT_MASK_CCK_RXTSF_OFFSET_8821C) +#define BIT_SET_CCK_RXTSF_OFFSET_8821C(x, v) \ + (BIT_CLEAR_CCK_RXTSF_OFFSET_8821C(x) | BIT_CCK_RXTSF_OFFSET_8821C(v)) /* 2 REG_RXTSF_OFFSET_OFDM_8821C */ #define BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C 0 #define BIT_MASK_OFDM_RXTSF_OFFSET_8821C 0xff -#define BIT_OFDM_RXTSF_OFFSET_8821C(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) -#define BIT_GET_OFDM_RXTSF_OFFSET_8821C(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C) - - +#define BIT_OFDM_RXTSF_OFFSET_8821C(x) \ + (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C) \ + << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) +#define BITS_OFDM_RXTSF_OFFSET_8821C \ + (BIT_MASK_OFDM_RXTSF_OFFSET_8821C << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8821C(x) \ + ((x) & (~BITS_OFDM_RXTSF_OFFSET_8821C)) +#define BIT_GET_OFDM_RXTSF_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) & \ + BIT_MASK_OFDM_RXTSF_OFFSET_8821C) +#define BIT_SET_OFDM_RXTSF_OFFSET_8821C(x, v) \ + (BIT_CLEAR_OFDM_RXTSF_OFFSET_8821C(x) | BIT_OFDM_RXTSF_OFFSET_8821C(v)) /* 2 REG_TSFTR_8821C */ #define BIT_SHIFT_TSF_TIMER_V1_8821C 0 #define BIT_MASK_TSF_TIMER_V1_8821C 0xffffffffL -#define BIT_TSF_TIMER_V1_8821C(x) (((x) & BIT_MASK_TSF_TIMER_V1_8821C) << BIT_SHIFT_TSF_TIMER_V1_8821C) -#define BIT_GET_TSF_TIMER_V1_8821C(x) (((x) >> BIT_SHIFT_TSF_TIMER_V1_8821C) & BIT_MASK_TSF_TIMER_V1_8821C) - - +#define BIT_TSF_TIMER_V1_8821C(x) \ + (((x) & BIT_MASK_TSF_TIMER_V1_8821C) << BIT_SHIFT_TSF_TIMER_V1_8821C) +#define BITS_TSF_TIMER_V1_8821C \ + (BIT_MASK_TSF_TIMER_V1_8821C << BIT_SHIFT_TSF_TIMER_V1_8821C) +#define BIT_CLEAR_TSF_TIMER_V1_8821C(x) ((x) & (~BITS_TSF_TIMER_V1_8821C)) +#define BIT_GET_TSF_TIMER_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_V1_8821C) & BIT_MASK_TSF_TIMER_V1_8821C) +#define BIT_SET_TSF_TIMER_V1_8821C(x, v) \ + (BIT_CLEAR_TSF_TIMER_V1_8821C(x) | BIT_TSF_TIMER_V1_8821C(v)) /* 2 REG_TSFTR_1_8821C */ #define BIT_SHIFT_TSF_TIMER_V2_8821C 0 #define BIT_MASK_TSF_TIMER_V2_8821C 0xffffffffL -#define BIT_TSF_TIMER_V2_8821C(x) (((x) & BIT_MASK_TSF_TIMER_V2_8821C) << BIT_SHIFT_TSF_TIMER_V2_8821C) -#define BIT_GET_TSF_TIMER_V2_8821C(x) (((x) >> BIT_SHIFT_TSF_TIMER_V2_8821C) & BIT_MASK_TSF_TIMER_V2_8821C) - - +#define BIT_TSF_TIMER_V2_8821C(x) \ + (((x) & BIT_MASK_TSF_TIMER_V2_8821C) << BIT_SHIFT_TSF_TIMER_V2_8821C) +#define BITS_TSF_TIMER_V2_8821C \ + (BIT_MASK_TSF_TIMER_V2_8821C << BIT_SHIFT_TSF_TIMER_V2_8821C) +#define BIT_CLEAR_TSF_TIMER_V2_8821C(x) ((x) & (~BITS_TSF_TIMER_V2_8821C)) +#define BIT_GET_TSF_TIMER_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_V2_8821C) & BIT_MASK_TSF_TIMER_V2_8821C) +#define BIT_SET_TSF_TIMER_V2_8821C(x, v) \ + (BIT_CLEAR_TSF_TIMER_V2_8821C(x) | BIT_TSF_TIMER_V2_8821C(v)) /* 2 REG_FREERUN_CNT_8821C */ #define BIT_SHIFT_FREERUN_CNT_V1_8821C 0 #define BIT_MASK_FREERUN_CNT_V1_8821C 0xffffffffL -#define BIT_FREERUN_CNT_V1_8821C(x) (((x) & BIT_MASK_FREERUN_CNT_V1_8821C) << BIT_SHIFT_FREERUN_CNT_V1_8821C) -#define BIT_GET_FREERUN_CNT_V1_8821C(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8821C) & BIT_MASK_FREERUN_CNT_V1_8821C) - - +#define BIT_FREERUN_CNT_V1_8821C(x) \ + (((x) & BIT_MASK_FREERUN_CNT_V1_8821C) \ + << BIT_SHIFT_FREERUN_CNT_V1_8821C) +#define BITS_FREERUN_CNT_V1_8821C \ + (BIT_MASK_FREERUN_CNT_V1_8821C << BIT_SHIFT_FREERUN_CNT_V1_8821C) +#define BIT_CLEAR_FREERUN_CNT_V1_8821C(x) ((x) & (~BITS_FREERUN_CNT_V1_8821C)) +#define BIT_GET_FREERUN_CNT_V1_8821C(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8821C) & \ + BIT_MASK_FREERUN_CNT_V1_8821C) +#define BIT_SET_FREERUN_CNT_V1_8821C(x, v) \ + (BIT_CLEAR_FREERUN_CNT_V1_8821C(x) | BIT_FREERUN_CNT_V1_8821C(v)) /* 2 REG_FREERUN_CNT_1_8821C */ #define BIT_SHIFT_FREERUN_CNT_V2_8821C 0 #define BIT_MASK_FREERUN_CNT_V2_8821C 0xffffffffL -#define BIT_FREERUN_CNT_V2_8821C(x) (((x) & BIT_MASK_FREERUN_CNT_V2_8821C) << BIT_SHIFT_FREERUN_CNT_V2_8821C) -#define BIT_GET_FREERUN_CNT_V2_8821C(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8821C) & BIT_MASK_FREERUN_CNT_V2_8821C) - - +#define BIT_FREERUN_CNT_V2_8821C(x) \ + (((x) & BIT_MASK_FREERUN_CNT_V2_8821C) \ + << BIT_SHIFT_FREERUN_CNT_V2_8821C) +#define BITS_FREERUN_CNT_V2_8821C \ + (BIT_MASK_FREERUN_CNT_V2_8821C << BIT_SHIFT_FREERUN_CNT_V2_8821C) +#define BIT_CLEAR_FREERUN_CNT_V2_8821C(x) ((x) & (~BITS_FREERUN_CNT_V2_8821C)) +#define BIT_GET_FREERUN_CNT_V2_8821C(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8821C) & \ + BIT_MASK_FREERUN_CNT_V2_8821C) +#define BIT_SET_FREERUN_CNT_V2_8821C(x, v) \ + (BIT_CLEAR_FREERUN_CNT_V2_8821C(x) | BIT_FREERUN_CNT_V2_8821C(v)) /* 2 REG_ATIMWND1_V1_8821C */ #define BIT_SHIFT_ATIMWND1_V1_8821C 0 #define BIT_MASK_ATIMWND1_V1_8821C 0xff -#define BIT_ATIMWND1_V1_8821C(x) (((x) & BIT_MASK_ATIMWND1_V1_8821C) << BIT_SHIFT_ATIMWND1_V1_8821C) -#define BIT_GET_ATIMWND1_V1_8821C(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8821C) & BIT_MASK_ATIMWND1_V1_8821C) - - +#define BIT_ATIMWND1_V1_8821C(x) \ + (((x) & BIT_MASK_ATIMWND1_V1_8821C) << BIT_SHIFT_ATIMWND1_V1_8821C) +#define BITS_ATIMWND1_V1_8821C \ + (BIT_MASK_ATIMWND1_V1_8821C << BIT_SHIFT_ATIMWND1_V1_8821C) +#define BIT_CLEAR_ATIMWND1_V1_8821C(x) ((x) & (~BITS_ATIMWND1_V1_8821C)) +#define BIT_GET_ATIMWND1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND1_V1_8821C) & BIT_MASK_ATIMWND1_V1_8821C) +#define BIT_SET_ATIMWND1_V1_8821C(x, v) \ + (BIT_CLEAR_ATIMWND1_V1_8821C(x) | BIT_ATIMWND1_V1_8821C(v)) /* 2 REG_TBTT_PROHIBIT_INFRA_8821C */ #define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C 0 #define BIT_MASK_TBTT_PROHIBIT_INFRA_8821C 0xff -#define BIT_TBTT_PROHIBIT_INFRA_8821C(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) -#define BIT_GET_TBTT_PROHIBIT_INFRA_8821C(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) - - +#define BIT_TBTT_PROHIBIT_INFRA_8821C(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) +#define BITS_TBTT_PROHIBIT_INFRA_8821C \ + (BIT_MASK_TBTT_PROHIBIT_INFRA_8821C \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) +#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8821C(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8821C)) +#define BIT_GET_TBTT_PROHIBIT_INFRA_8821C(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) & \ + BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) +#define BIT_SET_TBTT_PROHIBIT_INFRA_8821C(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8821C(x) | \ + BIT_TBTT_PROHIBIT_INFRA_8821C(v)) /* 2 REG_CTWND_8821C */ #define BIT_SHIFT_CTWND_8821C 0 #define BIT_MASK_CTWND_8821C 0xff -#define BIT_CTWND_8821C(x) (((x) & BIT_MASK_CTWND_8821C) << BIT_SHIFT_CTWND_8821C) -#define BIT_GET_CTWND_8821C(x) (((x) >> BIT_SHIFT_CTWND_8821C) & BIT_MASK_CTWND_8821C) - - +#define BIT_CTWND_8821C(x) \ + (((x) & BIT_MASK_CTWND_8821C) << BIT_SHIFT_CTWND_8821C) +#define BITS_CTWND_8821C (BIT_MASK_CTWND_8821C << BIT_SHIFT_CTWND_8821C) +#define BIT_CLEAR_CTWND_8821C(x) ((x) & (~BITS_CTWND_8821C)) +#define BIT_GET_CTWND_8821C(x) \ + (((x) >> BIT_SHIFT_CTWND_8821C) & BIT_MASK_CTWND_8821C) +#define BIT_SET_CTWND_8821C(x, v) \ + (BIT_CLEAR_CTWND_8821C(x) | BIT_CTWND_8821C(v)) /* 2 REG_BCNIVLCUNT_8821C */ #define BIT_SHIFT_BCNIVLCUNT_8821C 0 #define BIT_MASK_BCNIVLCUNT_8821C 0x7f -#define BIT_BCNIVLCUNT_8821C(x) (((x) & BIT_MASK_BCNIVLCUNT_8821C) << BIT_SHIFT_BCNIVLCUNT_8821C) -#define BIT_GET_BCNIVLCUNT_8821C(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8821C) & BIT_MASK_BCNIVLCUNT_8821C) - - +#define BIT_BCNIVLCUNT_8821C(x) \ + (((x) & BIT_MASK_BCNIVLCUNT_8821C) << BIT_SHIFT_BCNIVLCUNT_8821C) +#define BITS_BCNIVLCUNT_8821C \ + (BIT_MASK_BCNIVLCUNT_8821C << BIT_SHIFT_BCNIVLCUNT_8821C) +#define BIT_CLEAR_BCNIVLCUNT_8821C(x) ((x) & (~BITS_BCNIVLCUNT_8821C)) +#define BIT_GET_BCNIVLCUNT_8821C(x) \ + (((x) >> BIT_SHIFT_BCNIVLCUNT_8821C) & BIT_MASK_BCNIVLCUNT_8821C) +#define BIT_SET_BCNIVLCUNT_8821C(x, v) \ + (BIT_CLEAR_BCNIVLCUNT_8821C(x) | BIT_BCNIVLCUNT_8821C(v)) /* 2 REG_BCNDROPCTRL_8821C */ #define BIT_BEACON_DROP_EN_8821C BIT(7) #define BIT_SHIFT_BEACON_DROP_IVL_8821C 0 #define BIT_MASK_BEACON_DROP_IVL_8821C 0x7f -#define BIT_BEACON_DROP_IVL_8821C(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8821C) << BIT_SHIFT_BEACON_DROP_IVL_8821C) -#define BIT_GET_BEACON_DROP_IVL_8821C(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8821C) & BIT_MASK_BEACON_DROP_IVL_8821C) - - +#define BIT_BEACON_DROP_IVL_8821C(x) \ + (((x) & BIT_MASK_BEACON_DROP_IVL_8821C) \ + << BIT_SHIFT_BEACON_DROP_IVL_8821C) +#define BITS_BEACON_DROP_IVL_8821C \ + (BIT_MASK_BEACON_DROP_IVL_8821C << BIT_SHIFT_BEACON_DROP_IVL_8821C) +#define BIT_CLEAR_BEACON_DROP_IVL_8821C(x) ((x) & (~BITS_BEACON_DROP_IVL_8821C)) +#define BIT_GET_BEACON_DROP_IVL_8821C(x) \ + (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8821C) & \ + BIT_MASK_BEACON_DROP_IVL_8821C) +#define BIT_SET_BEACON_DROP_IVL_8821C(x, v) \ + (BIT_CLEAR_BEACON_DROP_IVL_8821C(x) | BIT_BEACON_DROP_IVL_8821C(v)) /* 2 REG_HGQ_TIMEOUT_PERIOD_8821C */ #define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C 0 #define BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C 0xff -#define BIT_HGQ_TIMEOUT_PERIOD_8821C(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) -#define BIT_GET_HGQ_TIMEOUT_PERIOD_8821C(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) - - +#define BIT_HGQ_TIMEOUT_PERIOD_8821C(x) \ + (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) +#define BITS_HGQ_TIMEOUT_PERIOD_8821C \ + (BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8821C(x) \ + ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8821C)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8821C(x) \ + (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) & \ + BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) +#define BIT_SET_HGQ_TIMEOUT_PERIOD_8821C(x, v) \ + (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8821C(x) | \ + BIT_HGQ_TIMEOUT_PERIOD_8821C(v)) /* 2 REG_TXCMD_TIMEOUT_PERIOD_8821C */ #define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C 0 #define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C 0xff -#define BIT_TXCMD_TIMEOUT_PERIOD_8821C(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) -#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8821C(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) - - +#define BIT_TXCMD_TIMEOUT_PERIOD_8821C(x) \ + (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) +#define BITS_TXCMD_TIMEOUT_PERIOD_8821C \ + (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8821C(x) \ + ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8821C)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8821C(x) \ + (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) & \ + BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8821C(x, v) \ + (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8821C(x) | \ + BIT_TXCMD_TIMEOUT_PERIOD_8821C(v)) /* 2 REG_MISC_CTRL_8821C */ +#define BIT_AUTO_SYNC_BY_TBTT_8821C BIT(6) #define BIT_DIS_TRX_CAL_BCN_8821C BIT(5) #define BIT_DIS_TX_CAL_TBTT_8821C BIT(4) #define BIT_EN_FREECNT_8821C BIT(3) @@ -7729,10 +12869,18 @@ #define BIT_SHIFT_DIS_SECONDARY_CCA_8821C 0 #define BIT_MASK_DIS_SECONDARY_CCA_8821C 0x3 -#define BIT_DIS_SECONDARY_CCA_8821C(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8821C) << BIT_SHIFT_DIS_SECONDARY_CCA_8821C) -#define BIT_GET_DIS_SECONDARY_CCA_8821C(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8821C) & BIT_MASK_DIS_SECONDARY_CCA_8821C) - - +#define BIT_DIS_SECONDARY_CCA_8821C(x) \ + (((x) & BIT_MASK_DIS_SECONDARY_CCA_8821C) \ + << BIT_SHIFT_DIS_SECONDARY_CCA_8821C) +#define BITS_DIS_SECONDARY_CCA_8821C \ + (BIT_MASK_DIS_SECONDARY_CCA_8821C << BIT_SHIFT_DIS_SECONDARY_CCA_8821C) +#define BIT_CLEAR_DIS_SECONDARY_CCA_8821C(x) \ + ((x) & (~BITS_DIS_SECONDARY_CCA_8821C)) +#define BIT_GET_DIS_SECONDARY_CCA_8821C(x) \ + (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8821C) & \ + BIT_MASK_DIS_SECONDARY_CCA_8821C) +#define BIT_SET_DIS_SECONDARY_CCA_8821C(x, v) \ + (BIT_CLEAR_DIS_SECONDARY_CCA_8821C(x) | BIT_DIS_SECONDARY_CCA_8821C(v)) /* 2 REG_BCN_CTRL_CLINT1_8821C */ #define BIT_CLI1_DIS_RX_BSSID_FIT_8821C BIT(6) @@ -7764,10 +12912,15 @@ #define BIT_SHIFT_PORT_SEL_8821C 0 #define BIT_MASK_PORT_SEL_8821C 0x7 -#define BIT_PORT_SEL_8821C(x) (((x) & BIT_MASK_PORT_SEL_8821C) << BIT_SHIFT_PORT_SEL_8821C) -#define BIT_GET_PORT_SEL_8821C(x) (((x) >> BIT_SHIFT_PORT_SEL_8821C) & BIT_MASK_PORT_SEL_8821C) - - +#define BIT_PORT_SEL_8821C(x) \ + (((x) & BIT_MASK_PORT_SEL_8821C) << BIT_SHIFT_PORT_SEL_8821C) +#define BITS_PORT_SEL_8821C \ + (BIT_MASK_PORT_SEL_8821C << BIT_SHIFT_PORT_SEL_8821C) +#define BIT_CLEAR_PORT_SEL_8821C(x) ((x) & (~BITS_PORT_SEL_8821C)) +#define BIT_GET_PORT_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_PORT_SEL_8821C) & BIT_MASK_PORT_SEL_8821C) +#define BIT_SET_PORT_SEL_8821C(x, v) \ + (BIT_CLEAR_PORT_SEL_8821C(x) | BIT_PORT_SEL_8821C(v)) /* 2 REG_P2PPS1_SPEC_STATE_8821C */ #define BIT_P2P1_SPEC_POWER_STATE_8821C BIT(7) @@ -7813,37 +12966,57 @@ #define BIT_SHIFT_PSTIMER0_INT_8821C 5 #define BIT_MASK_PSTIMER0_INT_8821C 0x7ffffff -#define BIT_PSTIMER0_INT_8821C(x) (((x) & BIT_MASK_PSTIMER0_INT_8821C) << BIT_SHIFT_PSTIMER0_INT_8821C) -#define BIT_GET_PSTIMER0_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8821C) & BIT_MASK_PSTIMER0_INT_8821C) - - +#define BIT_PSTIMER0_INT_8821C(x) \ + (((x) & BIT_MASK_PSTIMER0_INT_8821C) << BIT_SHIFT_PSTIMER0_INT_8821C) +#define BITS_PSTIMER0_INT_8821C \ + (BIT_MASK_PSTIMER0_INT_8821C << BIT_SHIFT_PSTIMER0_INT_8821C) +#define BIT_CLEAR_PSTIMER0_INT_8821C(x) ((x) & (~BITS_PSTIMER0_INT_8821C)) +#define BIT_GET_PSTIMER0_INT_8821C(x) \ + (((x) >> BIT_SHIFT_PSTIMER0_INT_8821C) & BIT_MASK_PSTIMER0_INT_8821C) +#define BIT_SET_PSTIMER0_INT_8821C(x, v) \ + (BIT_CLEAR_PSTIMER0_INT_8821C(x) | BIT_PSTIMER0_INT_8821C(v)) /* 2 REG_PS_TIMER1_8821C */ #define BIT_SHIFT_PSTIMER1_INT_8821C 5 #define BIT_MASK_PSTIMER1_INT_8821C 0x7ffffff -#define BIT_PSTIMER1_INT_8821C(x) (((x) & BIT_MASK_PSTIMER1_INT_8821C) << BIT_SHIFT_PSTIMER1_INT_8821C) -#define BIT_GET_PSTIMER1_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8821C) & BIT_MASK_PSTIMER1_INT_8821C) - - +#define BIT_PSTIMER1_INT_8821C(x) \ + (((x) & BIT_MASK_PSTIMER1_INT_8821C) << BIT_SHIFT_PSTIMER1_INT_8821C) +#define BITS_PSTIMER1_INT_8821C \ + (BIT_MASK_PSTIMER1_INT_8821C << BIT_SHIFT_PSTIMER1_INT_8821C) +#define BIT_CLEAR_PSTIMER1_INT_8821C(x) ((x) & (~BITS_PSTIMER1_INT_8821C)) +#define BIT_GET_PSTIMER1_INT_8821C(x) \ + (((x) >> BIT_SHIFT_PSTIMER1_INT_8821C) & BIT_MASK_PSTIMER1_INT_8821C) +#define BIT_SET_PSTIMER1_INT_8821C(x, v) \ + (BIT_CLEAR_PSTIMER1_INT_8821C(x) | BIT_PSTIMER1_INT_8821C(v)) /* 2 REG_PS_TIMER2_8821C */ #define BIT_SHIFT_PSTIMER2_INT_8821C 5 #define BIT_MASK_PSTIMER2_INT_8821C 0x7ffffff -#define BIT_PSTIMER2_INT_8821C(x) (((x) & BIT_MASK_PSTIMER2_INT_8821C) << BIT_SHIFT_PSTIMER2_INT_8821C) -#define BIT_GET_PSTIMER2_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8821C) & BIT_MASK_PSTIMER2_INT_8821C) - - +#define BIT_PSTIMER2_INT_8821C(x) \ + (((x) & BIT_MASK_PSTIMER2_INT_8821C) << BIT_SHIFT_PSTIMER2_INT_8821C) +#define BITS_PSTIMER2_INT_8821C \ + (BIT_MASK_PSTIMER2_INT_8821C << BIT_SHIFT_PSTIMER2_INT_8821C) +#define BIT_CLEAR_PSTIMER2_INT_8821C(x) ((x) & (~BITS_PSTIMER2_INT_8821C)) +#define BIT_GET_PSTIMER2_INT_8821C(x) \ + (((x) >> BIT_SHIFT_PSTIMER2_INT_8821C) & BIT_MASK_PSTIMER2_INT_8821C) +#define BIT_SET_PSTIMER2_INT_8821C(x, v) \ + (BIT_CLEAR_PSTIMER2_INT_8821C(x) | BIT_PSTIMER2_INT_8821C(v)) /* 2 REG_TBTT_CTN_AREA_8821C */ #define BIT_SHIFT_TBTT_CTN_AREA_8821C 0 #define BIT_MASK_TBTT_CTN_AREA_8821C 0xff -#define BIT_TBTT_CTN_AREA_8821C(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8821C) << BIT_SHIFT_TBTT_CTN_AREA_8821C) -#define BIT_GET_TBTT_CTN_AREA_8821C(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8821C) & BIT_MASK_TBTT_CTN_AREA_8821C) - - +#define BIT_TBTT_CTN_AREA_8821C(x) \ + (((x) & BIT_MASK_TBTT_CTN_AREA_8821C) << BIT_SHIFT_TBTT_CTN_AREA_8821C) +#define BITS_TBTT_CTN_AREA_8821C \ + (BIT_MASK_TBTT_CTN_AREA_8821C << BIT_SHIFT_TBTT_CTN_AREA_8821C) +#define BIT_CLEAR_TBTT_CTN_AREA_8821C(x) ((x) & (~BITS_TBTT_CTN_AREA_8821C)) +#define BIT_GET_TBTT_CTN_AREA_8821C(x) \ + (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8821C) & BIT_MASK_TBTT_CTN_AREA_8821C) +#define BIT_SET_TBTT_CTN_AREA_8821C(x, v) \ + (BIT_CLEAR_TBTT_CTN_AREA_8821C(x) | BIT_TBTT_CTN_AREA_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -7851,10 +13024,15 @@ #define BIT_SHIFT_FORCE_BCN_IFS_8821C 0 #define BIT_MASK_FORCE_BCN_IFS_8821C 0xff -#define BIT_FORCE_BCN_IFS_8821C(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8821C) << BIT_SHIFT_FORCE_BCN_IFS_8821C) -#define BIT_GET_FORCE_BCN_IFS_8821C(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8821C) & BIT_MASK_FORCE_BCN_IFS_8821C) - - +#define BIT_FORCE_BCN_IFS_8821C(x) \ + (((x) & BIT_MASK_FORCE_BCN_IFS_8821C) << BIT_SHIFT_FORCE_BCN_IFS_8821C) +#define BITS_FORCE_BCN_IFS_8821C \ + (BIT_MASK_FORCE_BCN_IFS_8821C << BIT_SHIFT_FORCE_BCN_IFS_8821C) +#define BIT_CLEAR_FORCE_BCN_IFS_8821C(x) ((x) & (~BITS_FORCE_BCN_IFS_8821C)) +#define BIT_GET_FORCE_BCN_IFS_8821C(x) \ + (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8821C) & BIT_MASK_FORCE_BCN_IFS_8821C) +#define BIT_SET_FORCE_BCN_IFS_8821C(x, v) \ + (BIT_CLEAR_FORCE_BCN_IFS_8821C(x) | BIT_FORCE_BCN_IFS_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -7862,19 +13040,29 @@ #define BIT_SHIFT_TXOP_MIN_8821C 0 #define BIT_MASK_TXOP_MIN_8821C 0x3fff -#define BIT_TXOP_MIN_8821C(x) (((x) & BIT_MASK_TXOP_MIN_8821C) << BIT_SHIFT_TXOP_MIN_8821C) -#define BIT_GET_TXOP_MIN_8821C(x) (((x) >> BIT_SHIFT_TXOP_MIN_8821C) & BIT_MASK_TXOP_MIN_8821C) - - +#define BIT_TXOP_MIN_8821C(x) \ + (((x) & BIT_MASK_TXOP_MIN_8821C) << BIT_SHIFT_TXOP_MIN_8821C) +#define BITS_TXOP_MIN_8821C \ + (BIT_MASK_TXOP_MIN_8821C << BIT_SHIFT_TXOP_MIN_8821C) +#define BIT_CLEAR_TXOP_MIN_8821C(x) ((x) & (~BITS_TXOP_MIN_8821C)) +#define BIT_GET_TXOP_MIN_8821C(x) \ + (((x) >> BIT_SHIFT_TXOP_MIN_8821C) & BIT_MASK_TXOP_MIN_8821C) +#define BIT_SET_TXOP_MIN_8821C(x, v) \ + (BIT_CLEAR_TXOP_MIN_8821C(x) | BIT_TXOP_MIN_8821C(v)) /* 2 REG_PRE_BKF_TIME_8821C */ #define BIT_SHIFT_PRE_BKF_TIME_8821C 0 #define BIT_MASK_PRE_BKF_TIME_8821C 0xff -#define BIT_PRE_BKF_TIME_8821C(x) (((x) & BIT_MASK_PRE_BKF_TIME_8821C) << BIT_SHIFT_PRE_BKF_TIME_8821C) -#define BIT_GET_PRE_BKF_TIME_8821C(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8821C) & BIT_MASK_PRE_BKF_TIME_8821C) - - +#define BIT_PRE_BKF_TIME_8821C(x) \ + (((x) & BIT_MASK_PRE_BKF_TIME_8821C) << BIT_SHIFT_PRE_BKF_TIME_8821C) +#define BITS_PRE_BKF_TIME_8821C \ + (BIT_MASK_PRE_BKF_TIME_8821C << BIT_SHIFT_PRE_BKF_TIME_8821C) +#define BIT_CLEAR_PRE_BKF_TIME_8821C(x) ((x) & (~BITS_PRE_BKF_TIME_8821C)) +#define BIT_GET_PRE_BKF_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_PRE_BKF_TIME_8821C) & BIT_MASK_PRE_BKF_TIME_8821C) +#define BIT_SET_PRE_BKF_TIME_8821C(x, v) \ + (BIT_CLEAR_PRE_BKF_TIME_8821C(x) | BIT_PRE_BKF_TIME_8821C(v)) /* 2 REG_CROSS_TXOP_CTRL_8821C */ #define BIT_TXFAIL_BREACK_TXOP_EN_8821C BIT(3) @@ -7892,64 +13080,99 @@ #define BIT_SHIFT_ATIMWND2_8821C 0 #define BIT_MASK_ATIMWND2_8821C 0xff -#define BIT_ATIMWND2_8821C(x) (((x) & BIT_MASK_ATIMWND2_8821C) << BIT_SHIFT_ATIMWND2_8821C) -#define BIT_GET_ATIMWND2_8821C(x) (((x) >> BIT_SHIFT_ATIMWND2_8821C) & BIT_MASK_ATIMWND2_8821C) - - +#define BIT_ATIMWND2_8821C(x) \ + (((x) & BIT_MASK_ATIMWND2_8821C) << BIT_SHIFT_ATIMWND2_8821C) +#define BITS_ATIMWND2_8821C \ + (BIT_MASK_ATIMWND2_8821C << BIT_SHIFT_ATIMWND2_8821C) +#define BIT_CLEAR_ATIMWND2_8821C(x) ((x) & (~BITS_ATIMWND2_8821C)) +#define BIT_GET_ATIMWND2_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND2_8821C) & BIT_MASK_ATIMWND2_8821C) +#define BIT_SET_ATIMWND2_8821C(x, v) \ + (BIT_CLEAR_ATIMWND2_8821C(x) | BIT_ATIMWND2_8821C(v)) /* 2 REG_ATIMWND3_8821C */ #define BIT_SHIFT_ATIMWND3_8821C 0 #define BIT_MASK_ATIMWND3_8821C 0xff -#define BIT_ATIMWND3_8821C(x) (((x) & BIT_MASK_ATIMWND3_8821C) << BIT_SHIFT_ATIMWND3_8821C) -#define BIT_GET_ATIMWND3_8821C(x) (((x) >> BIT_SHIFT_ATIMWND3_8821C) & BIT_MASK_ATIMWND3_8821C) - - +#define BIT_ATIMWND3_8821C(x) \ + (((x) & BIT_MASK_ATIMWND3_8821C) << BIT_SHIFT_ATIMWND3_8821C) +#define BITS_ATIMWND3_8821C \ + (BIT_MASK_ATIMWND3_8821C << BIT_SHIFT_ATIMWND3_8821C) +#define BIT_CLEAR_ATIMWND3_8821C(x) ((x) & (~BITS_ATIMWND3_8821C)) +#define BIT_GET_ATIMWND3_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND3_8821C) & BIT_MASK_ATIMWND3_8821C) +#define BIT_SET_ATIMWND3_8821C(x, v) \ + (BIT_CLEAR_ATIMWND3_8821C(x) | BIT_ATIMWND3_8821C(v)) /* 2 REG_ATIMWND4_8821C */ #define BIT_SHIFT_ATIMWND4_8821C 0 #define BIT_MASK_ATIMWND4_8821C 0xff -#define BIT_ATIMWND4_8821C(x) (((x) & BIT_MASK_ATIMWND4_8821C) << BIT_SHIFT_ATIMWND4_8821C) -#define BIT_GET_ATIMWND4_8821C(x) (((x) >> BIT_SHIFT_ATIMWND4_8821C) & BIT_MASK_ATIMWND4_8821C) - - +#define BIT_ATIMWND4_8821C(x) \ + (((x) & BIT_MASK_ATIMWND4_8821C) << BIT_SHIFT_ATIMWND4_8821C) +#define BITS_ATIMWND4_8821C \ + (BIT_MASK_ATIMWND4_8821C << BIT_SHIFT_ATIMWND4_8821C) +#define BIT_CLEAR_ATIMWND4_8821C(x) ((x) & (~BITS_ATIMWND4_8821C)) +#define BIT_GET_ATIMWND4_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND4_8821C) & BIT_MASK_ATIMWND4_8821C) +#define BIT_SET_ATIMWND4_8821C(x, v) \ + (BIT_CLEAR_ATIMWND4_8821C(x) | BIT_ATIMWND4_8821C(v)) /* 2 REG_ATIMWND5_8821C */ #define BIT_SHIFT_ATIMWND5_8821C 0 #define BIT_MASK_ATIMWND5_8821C 0xff -#define BIT_ATIMWND5_8821C(x) (((x) & BIT_MASK_ATIMWND5_8821C) << BIT_SHIFT_ATIMWND5_8821C) -#define BIT_GET_ATIMWND5_8821C(x) (((x) >> BIT_SHIFT_ATIMWND5_8821C) & BIT_MASK_ATIMWND5_8821C) - - +#define BIT_ATIMWND5_8821C(x) \ + (((x) & BIT_MASK_ATIMWND5_8821C) << BIT_SHIFT_ATIMWND5_8821C) +#define BITS_ATIMWND5_8821C \ + (BIT_MASK_ATIMWND5_8821C << BIT_SHIFT_ATIMWND5_8821C) +#define BIT_CLEAR_ATIMWND5_8821C(x) ((x) & (~BITS_ATIMWND5_8821C)) +#define BIT_GET_ATIMWND5_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND5_8821C) & BIT_MASK_ATIMWND5_8821C) +#define BIT_SET_ATIMWND5_8821C(x, v) \ + (BIT_CLEAR_ATIMWND5_8821C(x) | BIT_ATIMWND5_8821C(v)) /* 2 REG_ATIMWND6_8821C */ #define BIT_SHIFT_ATIMWND6_8821C 0 #define BIT_MASK_ATIMWND6_8821C 0xff -#define BIT_ATIMWND6_8821C(x) (((x) & BIT_MASK_ATIMWND6_8821C) << BIT_SHIFT_ATIMWND6_8821C) -#define BIT_GET_ATIMWND6_8821C(x) (((x) >> BIT_SHIFT_ATIMWND6_8821C) & BIT_MASK_ATIMWND6_8821C) - - +#define BIT_ATIMWND6_8821C(x) \ + (((x) & BIT_MASK_ATIMWND6_8821C) << BIT_SHIFT_ATIMWND6_8821C) +#define BITS_ATIMWND6_8821C \ + (BIT_MASK_ATIMWND6_8821C << BIT_SHIFT_ATIMWND6_8821C) +#define BIT_CLEAR_ATIMWND6_8821C(x) ((x) & (~BITS_ATIMWND6_8821C)) +#define BIT_GET_ATIMWND6_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND6_8821C) & BIT_MASK_ATIMWND6_8821C) +#define BIT_SET_ATIMWND6_8821C(x, v) \ + (BIT_CLEAR_ATIMWND6_8821C(x) | BIT_ATIMWND6_8821C(v)) /* 2 REG_ATIMWND7_8821C */ #define BIT_SHIFT_ATIMWND7_8821C 0 #define BIT_MASK_ATIMWND7_8821C 0xff -#define BIT_ATIMWND7_8821C(x) (((x) & BIT_MASK_ATIMWND7_8821C) << BIT_SHIFT_ATIMWND7_8821C) -#define BIT_GET_ATIMWND7_8821C(x) (((x) >> BIT_SHIFT_ATIMWND7_8821C) & BIT_MASK_ATIMWND7_8821C) - - +#define BIT_ATIMWND7_8821C(x) \ + (((x) & BIT_MASK_ATIMWND7_8821C) << BIT_SHIFT_ATIMWND7_8821C) +#define BITS_ATIMWND7_8821C \ + (BIT_MASK_ATIMWND7_8821C << BIT_SHIFT_ATIMWND7_8821C) +#define BIT_CLEAR_ATIMWND7_8821C(x) ((x) & (~BITS_ATIMWND7_8821C)) +#define BIT_GET_ATIMWND7_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND7_8821C) & BIT_MASK_ATIMWND7_8821C) +#define BIT_SET_ATIMWND7_8821C(x, v) \ + (BIT_CLEAR_ATIMWND7_8821C(x) | BIT_ATIMWND7_8821C(v)) /* 2 REG_ATIMUGT_8821C */ #define BIT_SHIFT_ATIM_URGENT_8821C 0 #define BIT_MASK_ATIM_URGENT_8821C 0xff -#define BIT_ATIM_URGENT_8821C(x) (((x) & BIT_MASK_ATIM_URGENT_8821C) << BIT_SHIFT_ATIM_URGENT_8821C) -#define BIT_GET_ATIM_URGENT_8821C(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8821C) & BIT_MASK_ATIM_URGENT_8821C) - - +#define BIT_ATIM_URGENT_8821C(x) \ + (((x) & BIT_MASK_ATIM_URGENT_8821C) << BIT_SHIFT_ATIM_URGENT_8821C) +#define BITS_ATIM_URGENT_8821C \ + (BIT_MASK_ATIM_URGENT_8821C << BIT_SHIFT_ATIM_URGENT_8821C) +#define BIT_CLEAR_ATIM_URGENT_8821C(x) ((x) & (~BITS_ATIM_URGENT_8821C)) +#define BIT_GET_ATIM_URGENT_8821C(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT_8821C) & BIT_MASK_ATIM_URGENT_8821C) +#define BIT_SET_ATIM_URGENT_8821C(x, v) \ + (BIT_CLEAR_ATIM_URGENT_8821C(x) | BIT_ATIM_URGENT_8821C(v)) /* 2 REG_HIQ_NO_LMT_EN_8821C */ #define BIT_HIQ_NO_LMT_EN_VAP7_8821C BIT(7) @@ -7965,73 +13188,129 @@ #define BIT_SHIFT_DTIM_COUNT_ROOT_8821C 0 #define BIT_MASK_DTIM_COUNT_ROOT_8821C 0xff -#define BIT_DTIM_COUNT_ROOT_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8821C) << BIT_SHIFT_DTIM_COUNT_ROOT_8821C) -#define BIT_GET_DTIM_COUNT_ROOT_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8821C) & BIT_MASK_DTIM_COUNT_ROOT_8821C) - - +#define BIT_DTIM_COUNT_ROOT_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_ROOT_8821C) \ + << BIT_SHIFT_DTIM_COUNT_ROOT_8821C) +#define BITS_DTIM_COUNT_ROOT_8821C \ + (BIT_MASK_DTIM_COUNT_ROOT_8821C << BIT_SHIFT_DTIM_COUNT_ROOT_8821C) +#define BIT_CLEAR_DTIM_COUNT_ROOT_8821C(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8821C)) +#define BIT_GET_DTIM_COUNT_ROOT_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8821C) & \ + BIT_MASK_DTIM_COUNT_ROOT_8821C) +#define BIT_SET_DTIM_COUNT_ROOT_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_ROOT_8821C(x) | BIT_DTIM_COUNT_ROOT_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP1_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP1_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP1_8821C 0xff -#define BIT_DTIM_COUNT_VAP1_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8821C) << BIT_SHIFT_DTIM_COUNT_VAP1_8821C) -#define BIT_GET_DTIM_COUNT_VAP1_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8821C) & BIT_MASK_DTIM_COUNT_VAP1_8821C) - - +#define BIT_DTIM_COUNT_VAP1_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP1_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP1_8821C) +#define BITS_DTIM_COUNT_VAP1_8821C \ + (BIT_MASK_DTIM_COUNT_VAP1_8821C << BIT_SHIFT_DTIM_COUNT_VAP1_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP1_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8821C)) +#define BIT_GET_DTIM_COUNT_VAP1_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP1_8821C) +#define BIT_SET_DTIM_COUNT_VAP1_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP1_8821C(x) | BIT_DTIM_COUNT_VAP1_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP2_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP2_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP2_8821C 0xff -#define BIT_DTIM_COUNT_VAP2_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8821C) << BIT_SHIFT_DTIM_COUNT_VAP2_8821C) -#define BIT_GET_DTIM_COUNT_VAP2_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8821C) & BIT_MASK_DTIM_COUNT_VAP2_8821C) - - +#define BIT_DTIM_COUNT_VAP2_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP2_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP2_8821C) +#define BITS_DTIM_COUNT_VAP2_8821C \ + (BIT_MASK_DTIM_COUNT_VAP2_8821C << BIT_SHIFT_DTIM_COUNT_VAP2_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP2_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8821C)) +#define BIT_GET_DTIM_COUNT_VAP2_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP2_8821C) +#define BIT_SET_DTIM_COUNT_VAP2_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP2_8821C(x) | BIT_DTIM_COUNT_VAP2_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP3_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP3_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP3_8821C 0xff -#define BIT_DTIM_COUNT_VAP3_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8821C) << BIT_SHIFT_DTIM_COUNT_VAP3_8821C) -#define BIT_GET_DTIM_COUNT_VAP3_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8821C) & BIT_MASK_DTIM_COUNT_VAP3_8821C) - - +#define BIT_DTIM_COUNT_VAP3_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP3_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP3_8821C) +#define BITS_DTIM_COUNT_VAP3_8821C \ + (BIT_MASK_DTIM_COUNT_VAP3_8821C << BIT_SHIFT_DTIM_COUNT_VAP3_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP3_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8821C)) +#define BIT_GET_DTIM_COUNT_VAP3_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP3_8821C) +#define BIT_SET_DTIM_COUNT_VAP3_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP3_8821C(x) | BIT_DTIM_COUNT_VAP3_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP4_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP4_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP4_8821C 0xff -#define BIT_DTIM_COUNT_VAP4_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8821C) << BIT_SHIFT_DTIM_COUNT_VAP4_8821C) -#define BIT_GET_DTIM_COUNT_VAP4_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8821C) & BIT_MASK_DTIM_COUNT_VAP4_8821C) - - +#define BIT_DTIM_COUNT_VAP4_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP4_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP4_8821C) +#define BITS_DTIM_COUNT_VAP4_8821C \ + (BIT_MASK_DTIM_COUNT_VAP4_8821C << BIT_SHIFT_DTIM_COUNT_VAP4_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP4_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8821C)) +#define BIT_GET_DTIM_COUNT_VAP4_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP4_8821C) +#define BIT_SET_DTIM_COUNT_VAP4_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP4_8821C(x) | BIT_DTIM_COUNT_VAP4_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP5_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP5_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP5_8821C 0xff -#define BIT_DTIM_COUNT_VAP5_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8821C) << BIT_SHIFT_DTIM_COUNT_VAP5_8821C) -#define BIT_GET_DTIM_COUNT_VAP5_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8821C) & BIT_MASK_DTIM_COUNT_VAP5_8821C) - - +#define BIT_DTIM_COUNT_VAP5_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP5_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP5_8821C) +#define BITS_DTIM_COUNT_VAP5_8821C \ + (BIT_MASK_DTIM_COUNT_VAP5_8821C << BIT_SHIFT_DTIM_COUNT_VAP5_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP5_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8821C)) +#define BIT_GET_DTIM_COUNT_VAP5_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP5_8821C) +#define BIT_SET_DTIM_COUNT_VAP5_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP5_8821C(x) | BIT_DTIM_COUNT_VAP5_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP6_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP6_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP6_8821C 0xff -#define BIT_DTIM_COUNT_VAP6_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8821C) << BIT_SHIFT_DTIM_COUNT_VAP6_8821C) -#define BIT_GET_DTIM_COUNT_VAP6_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8821C) & BIT_MASK_DTIM_COUNT_VAP6_8821C) - - +#define BIT_DTIM_COUNT_VAP6_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP6_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP6_8821C) +#define BITS_DTIM_COUNT_VAP6_8821C \ + (BIT_MASK_DTIM_COUNT_VAP6_8821C << BIT_SHIFT_DTIM_COUNT_VAP6_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP6_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8821C)) +#define BIT_GET_DTIM_COUNT_VAP6_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP6_8821C) +#define BIT_SET_DTIM_COUNT_VAP6_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP6_8821C(x) | BIT_DTIM_COUNT_VAP6_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP7_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP7_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP7_8821C 0xff -#define BIT_DTIM_COUNT_VAP7_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8821C) << BIT_SHIFT_DTIM_COUNT_VAP7_8821C) -#define BIT_GET_DTIM_COUNT_VAP7_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8821C) & BIT_MASK_DTIM_COUNT_VAP7_8821C) - - +#define BIT_DTIM_COUNT_VAP7_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP7_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP7_8821C) +#define BITS_DTIM_COUNT_VAP7_8821C \ + (BIT_MASK_DTIM_COUNT_VAP7_8821C << BIT_SHIFT_DTIM_COUNT_VAP7_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP7_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8821C)) +#define BIT_GET_DTIM_COUNT_VAP7_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP7_8821C) +#define BIT_SET_DTIM_COUNT_VAP7_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP7_8821C(x) | BIT_DTIM_COUNT_VAP7_8821C(v)) /* 2 REG_DIS_ATIM_8821C */ #define BIT_DIS_ATIM_VAP7_8821C BIT(7) @@ -8047,17 +13326,29 @@ #define BIT_SHIFT_TSFT_SEL_TIMER1_8821C 3 #define BIT_MASK_TSFT_SEL_TIMER1_8821C 0x7 -#define BIT_TSFT_SEL_TIMER1_8821C(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8821C) << BIT_SHIFT_TSFT_SEL_TIMER1_8821C) -#define BIT_GET_TSFT_SEL_TIMER1_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8821C) & BIT_MASK_TSFT_SEL_TIMER1_8821C) - - +#define BIT_TSFT_SEL_TIMER1_8821C(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER1_8821C) \ + << BIT_SHIFT_TSFT_SEL_TIMER1_8821C) +#define BITS_TSFT_SEL_TIMER1_8821C \ + (BIT_MASK_TSFT_SEL_TIMER1_8821C << BIT_SHIFT_TSFT_SEL_TIMER1_8821C) +#define BIT_CLEAR_TSFT_SEL_TIMER1_8821C(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8821C)) +#define BIT_GET_TSFT_SEL_TIMER1_8821C(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8821C) & \ + BIT_MASK_TSFT_SEL_TIMER1_8821C) +#define BIT_SET_TSFT_SEL_TIMER1_8821C(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER1_8821C(x) | BIT_TSFT_SEL_TIMER1_8821C(v)) #define BIT_SHIFT_EARLY_128US_8821C 0 #define BIT_MASK_EARLY_128US_8821C 0x7 -#define BIT_EARLY_128US_8821C(x) (((x) & BIT_MASK_EARLY_128US_8821C) << BIT_SHIFT_EARLY_128US_8821C) -#define BIT_GET_EARLY_128US_8821C(x) (((x) >> BIT_SHIFT_EARLY_128US_8821C) & BIT_MASK_EARLY_128US_8821C) - - +#define BIT_EARLY_128US_8821C(x) \ + (((x) & BIT_MASK_EARLY_128US_8821C) << BIT_SHIFT_EARLY_128US_8821C) +#define BITS_EARLY_128US_8821C \ + (BIT_MASK_EARLY_128US_8821C << BIT_SHIFT_EARLY_128US_8821C) +#define BIT_CLEAR_EARLY_128US_8821C(x) ((x) & (~BITS_EARLY_128US_8821C)) +#define BIT_GET_EARLY_128US_8821C(x) \ + (((x) >> BIT_SHIFT_EARLY_128US_8821C) & BIT_MASK_EARLY_128US_8821C) +#define BIT_SET_EARLY_128US_8821C(x, v) \ + (BIT_CLEAR_EARLY_128US_8821C(x) | BIT_EARLY_128US_8821C(v)) /* 2 REG_P2PPS1_CTRL_8821C */ #define BIT_P2P1_CTW_ALLSTASLEEP_8821C BIT(7) @@ -8077,81 +13368,145 @@ #define BIT_SHIFT_SYNC_CLI_SEL_8821C 4 #define BIT_MASK_SYNC_CLI_SEL_8821C 0x7 -#define BIT_SYNC_CLI_SEL_8821C(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8821C) << BIT_SHIFT_SYNC_CLI_SEL_8821C) -#define BIT_GET_SYNC_CLI_SEL_8821C(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8821C) & BIT_MASK_SYNC_CLI_SEL_8821C) - - +#define BIT_SYNC_CLI_SEL_8821C(x) \ + (((x) & BIT_MASK_SYNC_CLI_SEL_8821C) << BIT_SHIFT_SYNC_CLI_SEL_8821C) +#define BITS_SYNC_CLI_SEL_8821C \ + (BIT_MASK_SYNC_CLI_SEL_8821C << BIT_SHIFT_SYNC_CLI_SEL_8821C) +#define BIT_CLEAR_SYNC_CLI_SEL_8821C(x) ((x) & (~BITS_SYNC_CLI_SEL_8821C)) +#define BIT_GET_SYNC_CLI_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8821C) & BIT_MASK_SYNC_CLI_SEL_8821C) +#define BIT_SET_SYNC_CLI_SEL_8821C(x, v) \ + (BIT_CLEAR_SYNC_CLI_SEL_8821C(x) | BIT_SYNC_CLI_SEL_8821C(v)) #define BIT_SHIFT_TSFT_SEL_TIMER0_8821C 0 #define BIT_MASK_TSFT_SEL_TIMER0_8821C 0x7 -#define BIT_TSFT_SEL_TIMER0_8821C(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8821C) << BIT_SHIFT_TSFT_SEL_TIMER0_8821C) -#define BIT_GET_TSFT_SEL_TIMER0_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8821C) & BIT_MASK_TSFT_SEL_TIMER0_8821C) - - +#define BIT_TSFT_SEL_TIMER0_8821C(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER0_8821C) \ + << BIT_SHIFT_TSFT_SEL_TIMER0_8821C) +#define BITS_TSFT_SEL_TIMER0_8821C \ + (BIT_MASK_TSFT_SEL_TIMER0_8821C << BIT_SHIFT_TSFT_SEL_TIMER0_8821C) +#define BIT_CLEAR_TSFT_SEL_TIMER0_8821C(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8821C)) +#define BIT_GET_TSFT_SEL_TIMER0_8821C(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8821C) & \ + BIT_MASK_TSFT_SEL_TIMER0_8821C) +#define BIT_SET_TSFT_SEL_TIMER0_8821C(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER0_8821C(x) | BIT_TSFT_SEL_TIMER0_8821C(v)) /* 2 REG_NOA_UNIT_SEL_8821C */ #define BIT_SHIFT_NOA_UNIT2_SEL_8821C 8 #define BIT_MASK_NOA_UNIT2_SEL_8821C 0x7 -#define BIT_NOA_UNIT2_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8821C) << BIT_SHIFT_NOA_UNIT2_SEL_8821C) -#define BIT_GET_NOA_UNIT2_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8821C) & BIT_MASK_NOA_UNIT2_SEL_8821C) - - +#define BIT_NOA_UNIT2_SEL_8821C(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL_8821C) << BIT_SHIFT_NOA_UNIT2_SEL_8821C) +#define BITS_NOA_UNIT2_SEL_8821C \ + (BIT_MASK_NOA_UNIT2_SEL_8821C << BIT_SHIFT_NOA_UNIT2_SEL_8821C) +#define BIT_CLEAR_NOA_UNIT2_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT2_SEL_8821C)) +#define BIT_GET_NOA_UNIT2_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8821C) & BIT_MASK_NOA_UNIT2_SEL_8821C) +#define BIT_SET_NOA_UNIT2_SEL_8821C(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL_8821C(x) | BIT_NOA_UNIT2_SEL_8821C(v)) #define BIT_SHIFT_NOA_UNIT1_SEL_8821C 4 #define BIT_MASK_NOA_UNIT1_SEL_8821C 0x7 -#define BIT_NOA_UNIT1_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8821C) << BIT_SHIFT_NOA_UNIT1_SEL_8821C) -#define BIT_GET_NOA_UNIT1_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8821C) & BIT_MASK_NOA_UNIT1_SEL_8821C) - - +#define BIT_NOA_UNIT1_SEL_8821C(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL_8821C) << BIT_SHIFT_NOA_UNIT1_SEL_8821C) +#define BITS_NOA_UNIT1_SEL_8821C \ + (BIT_MASK_NOA_UNIT1_SEL_8821C << BIT_SHIFT_NOA_UNIT1_SEL_8821C) +#define BIT_CLEAR_NOA_UNIT1_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT1_SEL_8821C)) +#define BIT_GET_NOA_UNIT1_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8821C) & BIT_MASK_NOA_UNIT1_SEL_8821C) +#define BIT_SET_NOA_UNIT1_SEL_8821C(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL_8821C(x) | BIT_NOA_UNIT1_SEL_8821C(v)) #define BIT_SHIFT_NOA_UNIT0_SEL_8821C 0 #define BIT_MASK_NOA_UNIT0_SEL_8821C 0x7 -#define BIT_NOA_UNIT0_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8821C) << BIT_SHIFT_NOA_UNIT0_SEL_8821C) -#define BIT_GET_NOA_UNIT0_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8821C) & BIT_MASK_NOA_UNIT0_SEL_8821C) - - +#define BIT_NOA_UNIT0_SEL_8821C(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL_8821C) << BIT_SHIFT_NOA_UNIT0_SEL_8821C) +#define BITS_NOA_UNIT0_SEL_8821C \ + (BIT_MASK_NOA_UNIT0_SEL_8821C << BIT_SHIFT_NOA_UNIT0_SEL_8821C) +#define BIT_CLEAR_NOA_UNIT0_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT0_SEL_8821C)) +#define BIT_GET_NOA_UNIT0_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8821C) & BIT_MASK_NOA_UNIT0_SEL_8821C) +#define BIT_SET_NOA_UNIT0_SEL_8821C(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL_8821C(x) | BIT_NOA_UNIT0_SEL_8821C(v)) /* 2 REG_P2POFF_DIS_TXTIME_8821C */ #define BIT_SHIFT_P2POFF_DIS_TXTIME_8821C 0 #define BIT_MASK_P2POFF_DIS_TXTIME_8821C 0xff -#define BIT_P2POFF_DIS_TXTIME_8821C(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8821C) << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) -#define BIT_GET_P2POFF_DIS_TXTIME_8821C(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) & BIT_MASK_P2POFF_DIS_TXTIME_8821C) - - +#define BIT_P2POFF_DIS_TXTIME_8821C(x) \ + (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8821C) \ + << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) +#define BITS_P2POFF_DIS_TXTIME_8821C \ + (BIT_MASK_P2POFF_DIS_TXTIME_8821C << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) +#define BIT_CLEAR_P2POFF_DIS_TXTIME_8821C(x) \ + ((x) & (~BITS_P2POFF_DIS_TXTIME_8821C)) +#define BIT_GET_P2POFF_DIS_TXTIME_8821C(x) \ + (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) & \ + BIT_MASK_P2POFF_DIS_TXTIME_8821C) +#define BIT_SET_P2POFF_DIS_TXTIME_8821C(x, v) \ + (BIT_CLEAR_P2POFF_DIS_TXTIME_8821C(x) | BIT_P2POFF_DIS_TXTIME_8821C(v)) /* 2 REG_MBSSID_BCN_SPACE2_8821C */ #define BIT_SHIFT_BCN_SPACE_CLINT2_8821C 16 #define BIT_MASK_BCN_SPACE_CLINT2_8821C 0xfff -#define BIT_BCN_SPACE_CLINT2_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8821C) << BIT_SHIFT_BCN_SPACE_CLINT2_8821C) -#define BIT_GET_BCN_SPACE_CLINT2_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8821C) & BIT_MASK_BCN_SPACE_CLINT2_8821C) - - +#define BIT_BCN_SPACE_CLINT2_8821C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT2_8821C) \ + << BIT_SHIFT_BCN_SPACE_CLINT2_8821C) +#define BITS_BCN_SPACE_CLINT2_8821C \ + (BIT_MASK_BCN_SPACE_CLINT2_8821C << BIT_SHIFT_BCN_SPACE_CLINT2_8821C) +#define BIT_CLEAR_BCN_SPACE_CLINT2_8821C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT2_8821C)) +#define BIT_GET_BCN_SPACE_CLINT2_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8821C) & \ + BIT_MASK_BCN_SPACE_CLINT2_8821C) +#define BIT_SET_BCN_SPACE_CLINT2_8821C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT2_8821C(x) | BIT_BCN_SPACE_CLINT2_8821C(v)) #define BIT_SHIFT_BCN_SPACE_CLINT1_8821C 0 #define BIT_MASK_BCN_SPACE_CLINT1_8821C 0xfff -#define BIT_BCN_SPACE_CLINT1_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8821C) << BIT_SHIFT_BCN_SPACE_CLINT1_8821C) -#define BIT_GET_BCN_SPACE_CLINT1_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8821C) & BIT_MASK_BCN_SPACE_CLINT1_8821C) - - +#define BIT_BCN_SPACE_CLINT1_8821C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT1_8821C) \ + << BIT_SHIFT_BCN_SPACE_CLINT1_8821C) +#define BITS_BCN_SPACE_CLINT1_8821C \ + (BIT_MASK_BCN_SPACE_CLINT1_8821C << BIT_SHIFT_BCN_SPACE_CLINT1_8821C) +#define BIT_CLEAR_BCN_SPACE_CLINT1_8821C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT1_8821C)) +#define BIT_GET_BCN_SPACE_CLINT1_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8821C) & \ + BIT_MASK_BCN_SPACE_CLINT1_8821C) +#define BIT_SET_BCN_SPACE_CLINT1_8821C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT1_8821C(x) | BIT_BCN_SPACE_CLINT1_8821C(v)) /* 2 REG_MBSSID_BCN_SPACE3_8821C */ #define BIT_SHIFT_SUB_BCN_SPACE_8821C 16 #define BIT_MASK_SUB_BCN_SPACE_8821C 0xff -#define BIT_SUB_BCN_SPACE_8821C(x) (((x) & BIT_MASK_SUB_BCN_SPACE_8821C) << BIT_SHIFT_SUB_BCN_SPACE_8821C) -#define BIT_GET_SUB_BCN_SPACE_8821C(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8821C) & BIT_MASK_SUB_BCN_SPACE_8821C) - - +#define BIT_SUB_BCN_SPACE_8821C(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE_8821C) << BIT_SHIFT_SUB_BCN_SPACE_8821C) +#define BITS_SUB_BCN_SPACE_8821C \ + (BIT_MASK_SUB_BCN_SPACE_8821C << BIT_SHIFT_SUB_BCN_SPACE_8821C) +#define BIT_CLEAR_SUB_BCN_SPACE_8821C(x) ((x) & (~BITS_SUB_BCN_SPACE_8821C)) +#define BIT_GET_SUB_BCN_SPACE_8821C(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8821C) & BIT_MASK_SUB_BCN_SPACE_8821C) +#define BIT_SET_SUB_BCN_SPACE_8821C(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE_8821C(x) | BIT_SUB_BCN_SPACE_8821C(v)) #define BIT_SHIFT_BCN_SPACE_CLINT3_8821C 0 #define BIT_MASK_BCN_SPACE_CLINT3_8821C 0xfff -#define BIT_BCN_SPACE_CLINT3_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8821C) << BIT_SHIFT_BCN_SPACE_CLINT3_8821C) -#define BIT_GET_BCN_SPACE_CLINT3_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8821C) & BIT_MASK_BCN_SPACE_CLINT3_8821C) - - +#define BIT_BCN_SPACE_CLINT3_8821C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT3_8821C) \ + << BIT_SHIFT_BCN_SPACE_CLINT3_8821C) +#define BITS_BCN_SPACE_CLINT3_8821C \ + (BIT_MASK_BCN_SPACE_CLINT3_8821C << BIT_SHIFT_BCN_SPACE_CLINT3_8821C) +#define BIT_CLEAR_BCN_SPACE_CLINT3_8821C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT3_8821C)) +#define BIT_GET_BCN_SPACE_CLINT3_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8821C) & \ + BIT_MASK_BCN_SPACE_CLINT3_8821C) +#define BIT_SET_BCN_SPACE_CLINT3_8821C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT3_8821C(x) | BIT_BCN_SPACE_CLINT3_8821C(v)) /* 2 REG_ACMHWCTRL_8821C */ #define BIT_BEQ_ACM_STATUS_8821C BIT(7) @@ -8171,37 +13526,66 @@ #define BIT_SHIFT_AVGPERIOD_8821C 0 #define BIT_MASK_AVGPERIOD_8821C 0xffff -#define BIT_AVGPERIOD_8821C(x) (((x) & BIT_MASK_AVGPERIOD_8821C) << BIT_SHIFT_AVGPERIOD_8821C) -#define BIT_GET_AVGPERIOD_8821C(x) (((x) >> BIT_SHIFT_AVGPERIOD_8821C) & BIT_MASK_AVGPERIOD_8821C) - - +#define BIT_AVGPERIOD_8821C(x) \ + (((x) & BIT_MASK_AVGPERIOD_8821C) << BIT_SHIFT_AVGPERIOD_8821C) +#define BITS_AVGPERIOD_8821C \ + (BIT_MASK_AVGPERIOD_8821C << BIT_SHIFT_AVGPERIOD_8821C) +#define BIT_CLEAR_AVGPERIOD_8821C(x) ((x) & (~BITS_AVGPERIOD_8821C)) +#define BIT_GET_AVGPERIOD_8821C(x) \ + (((x) >> BIT_SHIFT_AVGPERIOD_8821C) & BIT_MASK_AVGPERIOD_8821C) +#define BIT_SET_AVGPERIOD_8821C(x, v) \ + (BIT_CLEAR_AVGPERIOD_8821C(x) | BIT_AVGPERIOD_8821C(v)) /* 2 REG_VO_ADMTIME_8821C */ #define BIT_SHIFT_VO_ADMITTED_TIME_8821C 0 #define BIT_MASK_VO_ADMITTED_TIME_8821C 0xffff -#define BIT_VO_ADMITTED_TIME_8821C(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8821C) << BIT_SHIFT_VO_ADMITTED_TIME_8821C) -#define BIT_GET_VO_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8821C) & BIT_MASK_VO_ADMITTED_TIME_8821C) - - +#define BIT_VO_ADMITTED_TIME_8821C(x) \ + (((x) & BIT_MASK_VO_ADMITTED_TIME_8821C) \ + << BIT_SHIFT_VO_ADMITTED_TIME_8821C) +#define BITS_VO_ADMITTED_TIME_8821C \ + (BIT_MASK_VO_ADMITTED_TIME_8821C << BIT_SHIFT_VO_ADMITTED_TIME_8821C) +#define BIT_CLEAR_VO_ADMITTED_TIME_8821C(x) \ + ((x) & (~BITS_VO_ADMITTED_TIME_8821C)) +#define BIT_GET_VO_ADMITTED_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8821C) & \ + BIT_MASK_VO_ADMITTED_TIME_8821C) +#define BIT_SET_VO_ADMITTED_TIME_8821C(x, v) \ + (BIT_CLEAR_VO_ADMITTED_TIME_8821C(x) | BIT_VO_ADMITTED_TIME_8821C(v)) /* 2 REG_VI_ADMTIME_8821C */ #define BIT_SHIFT_VI_ADMITTED_TIME_8821C 0 #define BIT_MASK_VI_ADMITTED_TIME_8821C 0xffff -#define BIT_VI_ADMITTED_TIME_8821C(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8821C) << BIT_SHIFT_VI_ADMITTED_TIME_8821C) -#define BIT_GET_VI_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8821C) & BIT_MASK_VI_ADMITTED_TIME_8821C) - - +#define BIT_VI_ADMITTED_TIME_8821C(x) \ + (((x) & BIT_MASK_VI_ADMITTED_TIME_8821C) \ + << BIT_SHIFT_VI_ADMITTED_TIME_8821C) +#define BITS_VI_ADMITTED_TIME_8821C \ + (BIT_MASK_VI_ADMITTED_TIME_8821C << BIT_SHIFT_VI_ADMITTED_TIME_8821C) +#define BIT_CLEAR_VI_ADMITTED_TIME_8821C(x) \ + ((x) & (~BITS_VI_ADMITTED_TIME_8821C)) +#define BIT_GET_VI_ADMITTED_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8821C) & \ + BIT_MASK_VI_ADMITTED_TIME_8821C) +#define BIT_SET_VI_ADMITTED_TIME_8821C(x, v) \ + (BIT_CLEAR_VI_ADMITTED_TIME_8821C(x) | BIT_VI_ADMITTED_TIME_8821C(v)) /* 2 REG_BE_ADMTIME_8821C */ #define BIT_SHIFT_BE_ADMITTED_TIME_8821C 0 #define BIT_MASK_BE_ADMITTED_TIME_8821C 0xffff -#define BIT_BE_ADMITTED_TIME_8821C(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8821C) << BIT_SHIFT_BE_ADMITTED_TIME_8821C) -#define BIT_GET_BE_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8821C) & BIT_MASK_BE_ADMITTED_TIME_8821C) - - +#define BIT_BE_ADMITTED_TIME_8821C(x) \ + (((x) & BIT_MASK_BE_ADMITTED_TIME_8821C) \ + << BIT_SHIFT_BE_ADMITTED_TIME_8821C) +#define BITS_BE_ADMITTED_TIME_8821C \ + (BIT_MASK_BE_ADMITTED_TIME_8821C << BIT_SHIFT_BE_ADMITTED_TIME_8821C) +#define BIT_CLEAR_BE_ADMITTED_TIME_8821C(x) \ + ((x) & (~BITS_BE_ADMITTED_TIME_8821C)) +#define BIT_GET_BE_ADMITTED_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8821C) & \ + BIT_MASK_BE_ADMITTED_TIME_8821C) +#define BIT_SET_BE_ADMITTED_TIME_8821C(x, v) \ + (BIT_CLEAR_BE_ADMITTED_TIME_8821C(x) | BIT_BE_ADMITTED_TIME_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -8211,26 +13595,41 @@ #define BIT_SHIFT_RANDOM_GEN_8821C 0 #define BIT_MASK_RANDOM_GEN_8821C 0xffffff -#define BIT_RANDOM_GEN_8821C(x) (((x) & BIT_MASK_RANDOM_GEN_8821C) << BIT_SHIFT_RANDOM_GEN_8821C) -#define BIT_GET_RANDOM_GEN_8821C(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8821C) & BIT_MASK_RANDOM_GEN_8821C) - - +#define BIT_RANDOM_GEN_8821C(x) \ + (((x) & BIT_MASK_RANDOM_GEN_8821C) << BIT_SHIFT_RANDOM_GEN_8821C) +#define BITS_RANDOM_GEN_8821C \ + (BIT_MASK_RANDOM_GEN_8821C << BIT_SHIFT_RANDOM_GEN_8821C) +#define BIT_CLEAR_RANDOM_GEN_8821C(x) ((x) & (~BITS_RANDOM_GEN_8821C)) +#define BIT_GET_RANDOM_GEN_8821C(x) \ + (((x) >> BIT_SHIFT_RANDOM_GEN_8821C) & BIT_MASK_RANDOM_GEN_8821C) +#define BIT_SET_RANDOM_GEN_8821C(x, v) \ + (BIT_CLEAR_RANDOM_GEN_8821C(x) | BIT_RANDOM_GEN_8821C(v)) /* 2 REG_TXCMD_NOA_SEL_8821C */ -#define BIT_SHIFT_NOA_SEL_8821C 4 -#define BIT_MASK_NOA_SEL_8821C 0x7 -#define BIT_NOA_SEL_8821C(x) (((x) & BIT_MASK_NOA_SEL_8821C) << BIT_SHIFT_NOA_SEL_8821C) -#define BIT_GET_NOA_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_SEL_8821C) & BIT_MASK_NOA_SEL_8821C) - - +#define BIT_SHIFT_NOA_SEL_V2_8821C 4 +#define BIT_MASK_NOA_SEL_V2_8821C 0x7 +#define BIT_NOA_SEL_V2_8821C(x) \ + (((x) & BIT_MASK_NOA_SEL_V2_8821C) << BIT_SHIFT_NOA_SEL_V2_8821C) +#define BITS_NOA_SEL_V2_8821C \ + (BIT_MASK_NOA_SEL_V2_8821C << BIT_SHIFT_NOA_SEL_V2_8821C) +#define BIT_CLEAR_NOA_SEL_V2_8821C(x) ((x) & (~BITS_NOA_SEL_V2_8821C)) +#define BIT_GET_NOA_SEL_V2_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V2_8821C) & BIT_MASK_NOA_SEL_V2_8821C) +#define BIT_SET_NOA_SEL_V2_8821C(x, v) \ + (BIT_CLEAR_NOA_SEL_V2_8821C(x) | BIT_NOA_SEL_V2_8821C(v)) #define BIT_SHIFT_TXCMD_SEG_SEL_8821C 0 #define BIT_MASK_TXCMD_SEG_SEL_8821C 0xf -#define BIT_TXCMD_SEG_SEL_8821C(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8821C) << BIT_SHIFT_TXCMD_SEG_SEL_8821C) -#define BIT_GET_TXCMD_SEG_SEL_8821C(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8821C) & BIT_MASK_TXCMD_SEG_SEL_8821C) - - +#define BIT_TXCMD_SEG_SEL_8821C(x) \ + (((x) & BIT_MASK_TXCMD_SEG_SEL_8821C) << BIT_SHIFT_TXCMD_SEG_SEL_8821C) +#define BITS_TXCMD_SEG_SEL_8821C \ + (BIT_MASK_TXCMD_SEG_SEL_8821C << BIT_SHIFT_TXCMD_SEG_SEL_8821C) +#define BIT_CLEAR_TXCMD_SEG_SEL_8821C(x) ((x) & (~BITS_TXCMD_SEG_SEL_8821C)) +#define BIT_GET_TXCMD_SEG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8821C) & BIT_MASK_TXCMD_SEG_SEL_8821C) +#define BIT_SET_TXCMD_SEG_SEL_8821C(x, v) \ + (BIT_CLEAR_TXCMD_SEG_SEL_8821C(x) | BIT_TXCMD_SEG_SEL_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -8244,37 +13643,64 @@ #define BIT_SHIFT_NOA_DURATION_V1_8821C 0 #define BIT_MASK_NOA_DURATION_V1_8821C 0xffffffffL -#define BIT_NOA_DURATION_V1_8821C(x) (((x) & BIT_MASK_NOA_DURATION_V1_8821C) << BIT_SHIFT_NOA_DURATION_V1_8821C) -#define BIT_GET_NOA_DURATION_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_DURATION_V1_8821C) & BIT_MASK_NOA_DURATION_V1_8821C) - - +#define BIT_NOA_DURATION_V1_8821C(x) \ + (((x) & BIT_MASK_NOA_DURATION_V1_8821C) \ + << BIT_SHIFT_NOA_DURATION_V1_8821C) +#define BITS_NOA_DURATION_V1_8821C \ + (BIT_MASK_NOA_DURATION_V1_8821C << BIT_SHIFT_NOA_DURATION_V1_8821C) +#define BIT_CLEAR_NOA_DURATION_V1_8821C(x) ((x) & (~BITS_NOA_DURATION_V1_8821C)) +#define BIT_GET_NOA_DURATION_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION_V1_8821C) & \ + BIT_MASK_NOA_DURATION_V1_8821C) +#define BIT_SET_NOA_DURATION_V1_8821C(x, v) \ + (BIT_CLEAR_NOA_DURATION_V1_8821C(x) | BIT_NOA_DURATION_V1_8821C(v)) /* 2 REG_NOA_PARAM_1_8821C */ #define BIT_SHIFT_NOA_INTERVAL_V1_8821C 0 #define BIT_MASK_NOA_INTERVAL_V1_8821C 0xffffffffL -#define BIT_NOA_INTERVAL_V1_8821C(x) (((x) & BIT_MASK_NOA_INTERVAL_V1_8821C) << BIT_SHIFT_NOA_INTERVAL_V1_8821C) -#define BIT_GET_NOA_INTERVAL_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8821C) & BIT_MASK_NOA_INTERVAL_V1_8821C) - - +#define BIT_NOA_INTERVAL_V1_8821C(x) \ + (((x) & BIT_MASK_NOA_INTERVAL_V1_8821C) \ + << BIT_SHIFT_NOA_INTERVAL_V1_8821C) +#define BITS_NOA_INTERVAL_V1_8821C \ + (BIT_MASK_NOA_INTERVAL_V1_8821C << BIT_SHIFT_NOA_INTERVAL_V1_8821C) +#define BIT_CLEAR_NOA_INTERVAL_V1_8821C(x) ((x) & (~BITS_NOA_INTERVAL_V1_8821C)) +#define BIT_GET_NOA_INTERVAL_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8821C) & \ + BIT_MASK_NOA_INTERVAL_V1_8821C) +#define BIT_SET_NOA_INTERVAL_V1_8821C(x, v) \ + (BIT_CLEAR_NOA_INTERVAL_V1_8821C(x) | BIT_NOA_INTERVAL_V1_8821C(v)) /* 2 REG_NOA_PARAM_2_8821C */ #define BIT_SHIFT_NOA_START_TIME_V1_8821C 0 #define BIT_MASK_NOA_START_TIME_V1_8821C 0xffffffffL -#define BIT_NOA_START_TIME_V1_8821C(x) (((x) & BIT_MASK_NOA_START_TIME_V1_8821C) << BIT_SHIFT_NOA_START_TIME_V1_8821C) -#define BIT_GET_NOA_START_TIME_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8821C) & BIT_MASK_NOA_START_TIME_V1_8821C) - - +#define BIT_NOA_START_TIME_V1_8821C(x) \ + (((x) & BIT_MASK_NOA_START_TIME_V1_8821C) \ + << BIT_SHIFT_NOA_START_TIME_V1_8821C) +#define BITS_NOA_START_TIME_V1_8821C \ + (BIT_MASK_NOA_START_TIME_V1_8821C << BIT_SHIFT_NOA_START_TIME_V1_8821C) +#define BIT_CLEAR_NOA_START_TIME_V1_8821C(x) \ + ((x) & (~BITS_NOA_START_TIME_V1_8821C)) +#define BIT_GET_NOA_START_TIME_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8821C) & \ + BIT_MASK_NOA_START_TIME_V1_8821C) +#define BIT_SET_NOA_START_TIME_V1_8821C(x, v) \ + (BIT_CLEAR_NOA_START_TIME_V1_8821C(x) | BIT_NOA_START_TIME_V1_8821C(v)) /* 2 REG_NOA_PARAM_3_8821C */ #define BIT_SHIFT_NOA_COUNT_V1_8821C 0 #define BIT_MASK_NOA_COUNT_V1_8821C 0xffffffffL -#define BIT_NOA_COUNT_V1_8821C(x) (((x) & BIT_MASK_NOA_COUNT_V1_8821C) << BIT_SHIFT_NOA_COUNT_V1_8821C) -#define BIT_GET_NOA_COUNT_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_COUNT_V1_8821C) & BIT_MASK_NOA_COUNT_V1_8821C) - - +#define BIT_NOA_COUNT_V1_8821C(x) \ + (((x) & BIT_MASK_NOA_COUNT_V1_8821C) << BIT_SHIFT_NOA_COUNT_V1_8821C) +#define BITS_NOA_COUNT_V1_8821C \ + (BIT_MASK_NOA_COUNT_V1_8821C << BIT_SHIFT_NOA_COUNT_V1_8821C) +#define BIT_CLEAR_NOA_COUNT_V1_8821C(x) ((x) & (~BITS_NOA_COUNT_V1_8821C)) +#define BIT_GET_NOA_COUNT_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_V1_8821C) & BIT_MASK_NOA_COUNT_V1_8821C) +#define BIT_SET_NOA_COUNT_V1_8821C(x, v) \ + (BIT_CLEAR_NOA_COUNT_V1_8821C(x) | BIT_NOA_COUNT_V1_8821C(v)) /* 2 REG_P2P_RST_8821C */ #define BIT_P2P2_PWR_RST1_8821C BIT(5) @@ -8285,7 +13711,8 @@ #define BIT_P2P_PWR_RST0_V1_8821C BIT(0) /* 2 REG_SCHEDULER_RST_8821C */ -#define BIT_SYNC_CLI_8821C BIT(1) +#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8821C BIT(2) +#define BIT_SYNC_CLI_ONCE_BY_TBTT_8821C BIT(1) #define BIT_SCHEDULER_RST_V1_8821C BIT(0) /* 2 REG_NOT_VALID_8821C */ @@ -8298,48 +13725,79 @@ #define BIT_SHIFT_SCH_TXCMD_8821C 0 #define BIT_MASK_SCH_TXCMD_8821C 0xffffffffL -#define BIT_SCH_TXCMD_8821C(x) (((x) & BIT_MASK_SCH_TXCMD_8821C) << BIT_SHIFT_SCH_TXCMD_8821C) -#define BIT_GET_SCH_TXCMD_8821C(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8821C) & BIT_MASK_SCH_TXCMD_8821C) - - +#define BIT_SCH_TXCMD_8821C(x) \ + (((x) & BIT_MASK_SCH_TXCMD_8821C) << BIT_SHIFT_SCH_TXCMD_8821C) +#define BITS_SCH_TXCMD_8821C \ + (BIT_MASK_SCH_TXCMD_8821C << BIT_SHIFT_SCH_TXCMD_8821C) +#define BIT_CLEAR_SCH_TXCMD_8821C(x) ((x) & (~BITS_SCH_TXCMD_8821C)) +#define BIT_GET_SCH_TXCMD_8821C(x) \ + (((x) >> BIT_SHIFT_SCH_TXCMD_8821C) & BIT_MASK_SCH_TXCMD_8821C) +#define BIT_SET_SCH_TXCMD_8821C(x, v) \ + (BIT_CLEAR_SCH_TXCMD_8821C(x) | BIT_SCH_TXCMD_8821C(v)) /* 2 REG_PAGE5_DUMMY_8821C */ +#define BIT_ECO_TXOP_BREAK_FORCE_CFEND_8821C BIT(0) /* 2 REG_CPUMGQ_TX_TIMER_8821C */ #define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C 0 #define BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C 0xffffffffL -#define BIT_CPUMGQ_TX_TIMER_V1_8821C(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) -#define BIT_GET_CPUMGQ_TX_TIMER_V1_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) - - +#define BIT_CPUMGQ_TX_TIMER_V1_8821C(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) +#define BITS_CPUMGQ_TX_TIMER_V1_8821C \ + (BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8821C(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8821C)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8821C(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) & \ + BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) +#define BIT_SET_CPUMGQ_TX_TIMER_V1_8821C(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8821C(x) | \ + BIT_CPUMGQ_TX_TIMER_V1_8821C(v)) /* 2 REG_PS_TIMER_A_8821C */ #define BIT_SHIFT_PS_TIMER_A_V1_8821C 0 #define BIT_MASK_PS_TIMER_A_V1_8821C 0xffffffffL -#define BIT_PS_TIMER_A_V1_8821C(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8821C) << BIT_SHIFT_PS_TIMER_A_V1_8821C) -#define BIT_GET_PS_TIMER_A_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8821C) & BIT_MASK_PS_TIMER_A_V1_8821C) - - +#define BIT_PS_TIMER_A_V1_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_A_V1_8821C) << BIT_SHIFT_PS_TIMER_A_V1_8821C) +#define BITS_PS_TIMER_A_V1_8821C \ + (BIT_MASK_PS_TIMER_A_V1_8821C << BIT_SHIFT_PS_TIMER_A_V1_8821C) +#define BIT_CLEAR_PS_TIMER_A_V1_8821C(x) ((x) & (~BITS_PS_TIMER_A_V1_8821C)) +#define BIT_GET_PS_TIMER_A_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8821C) & BIT_MASK_PS_TIMER_A_V1_8821C) +#define BIT_SET_PS_TIMER_A_V1_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_A_V1_8821C(x) | BIT_PS_TIMER_A_V1_8821C(v)) /* 2 REG_PS_TIMER_B_8821C */ #define BIT_SHIFT_PS_TIMER_B_V1_8821C 0 #define BIT_MASK_PS_TIMER_B_V1_8821C 0xffffffffL -#define BIT_PS_TIMER_B_V1_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8821C) << BIT_SHIFT_PS_TIMER_B_V1_8821C) -#define BIT_GET_PS_TIMER_B_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8821C) & BIT_MASK_PS_TIMER_B_V1_8821C) - - +#define BIT_PS_TIMER_B_V1_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_B_V1_8821C) << BIT_SHIFT_PS_TIMER_B_V1_8821C) +#define BITS_PS_TIMER_B_V1_8821C \ + (BIT_MASK_PS_TIMER_B_V1_8821C << BIT_SHIFT_PS_TIMER_B_V1_8821C) +#define BIT_CLEAR_PS_TIMER_B_V1_8821C(x) ((x) & (~BITS_PS_TIMER_B_V1_8821C)) +#define BIT_GET_PS_TIMER_B_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8821C) & BIT_MASK_PS_TIMER_B_V1_8821C) +#define BIT_SET_PS_TIMER_B_V1_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_B_V1_8821C(x) | BIT_PS_TIMER_B_V1_8821C(v)) /* 2 REG_PS_TIMER_C_8821C */ #define BIT_SHIFT_PS_TIMER_C_V1_8821C 0 #define BIT_MASK_PS_TIMER_C_V1_8821C 0xffffffffL -#define BIT_PS_TIMER_C_V1_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8821C) << BIT_SHIFT_PS_TIMER_C_V1_8821C) -#define BIT_GET_PS_TIMER_C_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8821C) & BIT_MASK_PS_TIMER_C_V1_8821C) - - +#define BIT_PS_TIMER_C_V1_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_C_V1_8821C) << BIT_SHIFT_PS_TIMER_C_V1_8821C) +#define BITS_PS_TIMER_C_V1_8821C \ + (BIT_MASK_PS_TIMER_C_V1_8821C << BIT_SHIFT_PS_TIMER_C_V1_8821C) +#define BIT_CLEAR_PS_TIMER_C_V1_8821C(x) ((x) & (~BITS_PS_TIMER_C_V1_8821C)) +#define BIT_GET_PS_TIMER_C_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8821C) & BIT_MASK_PS_TIMER_C_V1_8821C) +#define BIT_SET_PS_TIMER_C_V1_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_C_V1_8821C(x) | BIT_PS_TIMER_C_V1_8821C(v)) /* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8821C */ #define BIT_CPUMGQ_TIMER_EN_8821C BIT(31) @@ -8347,72 +13805,169 @@ #define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C 24 #define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C 0x7 -#define BIT_CPUMGQ_TIMER_TSF_SEL_8821C(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) -#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) - +#define BIT_CPUMGQ_TIMER_TSF_SEL_8821C(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) +#define BITS_CPUMGQ_TIMER_TSF_SEL_8821C \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8821C(x) \ + ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8821C)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8821C(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8821C(x) | \ + BIT_CPUMGQ_TIMER_TSF_SEL_8821C(v)) #define BIT_PS_TIMER_C_EN_8821C BIT(23) #define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C 16 #define BIT_MASK_PS_TIMER_C_TSF_SEL_8821C 0x7 -#define BIT_PS_TIMER_C_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) -#define BIT_GET_PS_TIMER_C_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) - +#define BIT_PS_TIMER_C_TSF_SEL_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) +#define BITS_PS_TIMER_C_TSF_SEL_8821C \ + (BIT_MASK_PS_TIMER_C_TSF_SEL_8821C \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) +#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8821C(x) \ + ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8821C)) +#define BIT_GET_PS_TIMER_C_TSF_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) & \ + BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) +#define BIT_SET_PS_TIMER_C_TSF_SEL_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8821C(x) | \ + BIT_PS_TIMER_C_TSF_SEL_8821C(v)) #define BIT_PS_TIMER_B_EN_8821C BIT(15) #define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C 8 #define BIT_MASK_PS_TIMER_B_TSF_SEL_8821C 0x7 -#define BIT_PS_TIMER_B_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) -#define BIT_GET_PS_TIMER_B_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) - +#define BIT_PS_TIMER_B_TSF_SEL_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) +#define BITS_PS_TIMER_B_TSF_SEL_8821C \ + (BIT_MASK_PS_TIMER_B_TSF_SEL_8821C \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) +#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8821C(x) \ + ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8821C)) +#define BIT_GET_PS_TIMER_B_TSF_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) & \ + BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) +#define BIT_SET_PS_TIMER_B_TSF_SEL_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8821C(x) | \ + BIT_PS_TIMER_B_TSF_SEL_8821C(v)) #define BIT_PS_TIMER_A_EN_8821C BIT(7) #define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C 0 #define BIT_MASK_PS_TIMER_A_TSF_SEL_8821C 0x7 -#define BIT_PS_TIMER_A_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) -#define BIT_GET_PS_TIMER_A_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) - - +#define BIT_PS_TIMER_A_TSF_SEL_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) +#define BITS_PS_TIMER_A_TSF_SEL_8821C \ + (BIT_MASK_PS_TIMER_A_TSF_SEL_8821C \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) +#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8821C(x) \ + ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8821C)) +#define BIT_GET_PS_TIMER_A_TSF_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) & \ + BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) +#define BIT_SET_PS_TIMER_A_TSF_SEL_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8821C(x) | \ + BIT_PS_TIMER_A_TSF_SEL_8821C(v)) /* 2 REG_CPUMGQ_TX_TIMER_EARLY_8821C */ #define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C 0 #define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C 0xff -#define BIT_CPUMGQ_TX_TIMER_EARLY_8821C(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) -#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) - - +#define BIT_CPUMGQ_TX_TIMER_EARLY_8821C(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) +#define BITS_CPUMGQ_TX_TIMER_EARLY_8821C \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8821C(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8821C)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8821C(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8821C(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8821C(x) | \ + BIT_CPUMGQ_TX_TIMER_EARLY_8821C(v)) /* 2 REG_PS_TIMER_A_EARLY_8821C */ #define BIT_SHIFT_PS_TIMER_A_EARLY_8821C 0 #define BIT_MASK_PS_TIMER_A_EARLY_8821C 0xff -#define BIT_PS_TIMER_A_EARLY_8821C(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8821C) << BIT_SHIFT_PS_TIMER_A_EARLY_8821C) -#define BIT_GET_PS_TIMER_A_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8821C) & BIT_MASK_PS_TIMER_A_EARLY_8821C) - - +#define BIT_PS_TIMER_A_EARLY_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_A_EARLY_8821C) \ + << BIT_SHIFT_PS_TIMER_A_EARLY_8821C) +#define BITS_PS_TIMER_A_EARLY_8821C \ + (BIT_MASK_PS_TIMER_A_EARLY_8821C << BIT_SHIFT_PS_TIMER_A_EARLY_8821C) +#define BIT_CLEAR_PS_TIMER_A_EARLY_8821C(x) \ + ((x) & (~BITS_PS_TIMER_A_EARLY_8821C)) +#define BIT_GET_PS_TIMER_A_EARLY_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8821C) & \ + BIT_MASK_PS_TIMER_A_EARLY_8821C) +#define BIT_SET_PS_TIMER_A_EARLY_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_A_EARLY_8821C(x) | BIT_PS_TIMER_A_EARLY_8821C(v)) /* 2 REG_PS_TIMER_B_EARLY_8821C */ #define BIT_SHIFT_PS_TIMER_B_EARLY_8821C 0 #define BIT_MASK_PS_TIMER_B_EARLY_8821C 0xff -#define BIT_PS_TIMER_B_EARLY_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8821C) << BIT_SHIFT_PS_TIMER_B_EARLY_8821C) -#define BIT_GET_PS_TIMER_B_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8821C) & BIT_MASK_PS_TIMER_B_EARLY_8821C) - - +#define BIT_PS_TIMER_B_EARLY_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_B_EARLY_8821C) \ + << BIT_SHIFT_PS_TIMER_B_EARLY_8821C) +#define BITS_PS_TIMER_B_EARLY_8821C \ + (BIT_MASK_PS_TIMER_B_EARLY_8821C << BIT_SHIFT_PS_TIMER_B_EARLY_8821C) +#define BIT_CLEAR_PS_TIMER_B_EARLY_8821C(x) \ + ((x) & (~BITS_PS_TIMER_B_EARLY_8821C)) +#define BIT_GET_PS_TIMER_B_EARLY_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8821C) & \ + BIT_MASK_PS_TIMER_B_EARLY_8821C) +#define BIT_SET_PS_TIMER_B_EARLY_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_B_EARLY_8821C(x) | BIT_PS_TIMER_B_EARLY_8821C(v)) /* 2 REG_PS_TIMER_C_EARLY_8821C */ #define BIT_SHIFT_PS_TIMER_C_EARLY_8821C 0 #define BIT_MASK_PS_TIMER_C_EARLY_8821C 0xff -#define BIT_PS_TIMER_C_EARLY_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8821C) << BIT_SHIFT_PS_TIMER_C_EARLY_8821C) -#define BIT_GET_PS_TIMER_C_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8821C) & BIT_MASK_PS_TIMER_C_EARLY_8821C) +#define BIT_PS_TIMER_C_EARLY_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_C_EARLY_8821C) \ + << BIT_SHIFT_PS_TIMER_C_EARLY_8821C) +#define BITS_PS_TIMER_C_EARLY_8821C \ + (BIT_MASK_PS_TIMER_C_EARLY_8821C << BIT_SHIFT_PS_TIMER_C_EARLY_8821C) +#define BIT_CLEAR_PS_TIMER_C_EARLY_8821C(x) \ + ((x) & (~BITS_PS_TIMER_C_EARLY_8821C)) +#define BIT_GET_PS_TIMER_C_EARLY_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8821C) & \ + BIT_MASK_PS_TIMER_C_EARLY_8821C) +#define BIT_SET_PS_TIMER_C_EARLY_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_C_EARLY_8821C(x) | BIT_PS_TIMER_C_EARLY_8821C(v)) + +/* 2 REG_CPUMGQ_PARAMETER_8821C */ +/* 2 REG_NOT_VALID_8821C */ +#define BIT_MAC_STOP_CPUMGQ_8821C BIT(16) +#define BIT_SHIFT_CW_8821C 8 +#define BIT_MASK_CW_8821C 0xff +#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C) +#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C)) +#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) +#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v)) -/* 2 REG_NOT_VALID_8821C */ +#define BIT_SHIFT_AIFS_8821C 0 +#define BIT_MASK_AIFS_8821C 0xff +#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) +#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C) +#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C)) +#define BIT_GET_AIFS_8821C(x) \ + (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) +#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -8530,28 +14085,36 @@ /* 2 REG_NOT_VALID_8821C */ -/* 2 REG_BWOPMODE_8821C (BW OPERATION MODE REGISTER) */ +/* 2 REG_WMAC_CR_8821C (WMAC CR AND APSD CONTROL REGISTER) */ +#define BIT_IC_MACPHY_M_8821C BIT(0) /* 2 REG_WMAC_FWPKT_CR_8821C */ #define BIT_FWEN_8821C BIT(7) #define BIT_PHYSTS_PKT_CTRL_8821C BIT(6) +#define BIT_FWFULL_TO_RXFF_EN_8821C BIT(5) #define BIT_APPHDR_MIDSRCH_FAIL_8821C BIT(4) #define BIT_FWPARSING_EN_8821C BIT(3) #define BIT_SHIFT_APPEND_MHDR_LEN_8821C 0 #define BIT_MASK_APPEND_MHDR_LEN_8821C 0x7 -#define BIT_APPEND_MHDR_LEN_8821C(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8821C) << BIT_SHIFT_APPEND_MHDR_LEN_8821C) -#define BIT_GET_APPEND_MHDR_LEN_8821C(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8821C) & BIT_MASK_APPEND_MHDR_LEN_8821C) - - +#define BIT_APPEND_MHDR_LEN_8821C(x) \ + (((x) & BIT_MASK_APPEND_MHDR_LEN_8821C) \ + << BIT_SHIFT_APPEND_MHDR_LEN_8821C) +#define BITS_APPEND_MHDR_LEN_8821C \ + (BIT_MASK_APPEND_MHDR_LEN_8821C << BIT_SHIFT_APPEND_MHDR_LEN_8821C) +#define BIT_CLEAR_APPEND_MHDR_LEN_8821C(x) ((x) & (~BITS_APPEND_MHDR_LEN_8821C)) +#define BIT_GET_APPEND_MHDR_LEN_8821C(x) \ + (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8821C) & \ + BIT_MASK_APPEND_MHDR_LEN_8821C) +#define BIT_SET_APPEND_MHDR_LEN_8821C(x, v) \ + (BIT_CLEAR_APPEND_MHDR_LEN_8821C(x) | BIT_APPEND_MHDR_LEN_8821C(v)) /* 2 REG_FW_STS_FILTER_8821C */ #define BIT_DATA_FW_STS_FILTER_8821C BIT(2) #define BIT_CTRL_FW_STS_FILTER_8821C BIT(1) #define BIT_MGNT_FW_STS_FILTER_8821C BIT(0) -/* 2 REG_WMAC_CR_8821C (WMAC CR AND APSD CONTROL REGISTER) */ -#define BIT_IC_MACPHY_M_8821C BIT(0) +/* 2 REG_RSVD_8821C */ /* 2 REG_TCR_8821C (TRANSMISSION CONFIGURATION REGISTER) */ #define BIT_WMAC_EN_RTS_ADDR_8821C BIT(31) @@ -8616,69 +14179,152 @@ #define BIT_APM_8821C BIT(1) #define BIT_AAP_8821C BIT(0) -/* 2 REG_RX_DRVINFO_SZ_8821C (RX DRIVER INFO SIZE REGISTER) */ -#define BIT_PHYSTS_PER_PKT_MODE_8821C BIT(7) - -#define BIT_SHIFT_DRVINFO_SZ_V1_8821C 0 -#define BIT_MASK_DRVINFO_SZ_V1_8821C 0xf -#define BIT_DRVINFO_SZ_V1_8821C(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8821C) << BIT_SHIFT_DRVINFO_SZ_V1_8821C) -#define BIT_GET_DRVINFO_SZ_V1_8821C(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8821C) & BIT_MASK_DRVINFO_SZ_V1_8821C) - - - -/* 2 REG_RX_DLK_TIME_8821C (RX DEADLOCK TIME REGISTER) */ - -#define BIT_SHIFT_RX_DLK_TIME_8821C 0 -#define BIT_MASK_RX_DLK_TIME_8821C 0xff -#define BIT_RX_DLK_TIME_8821C(x) (((x) & BIT_MASK_RX_DLK_TIME_8821C) << BIT_SHIFT_RX_DLK_TIME_8821C) -#define BIT_GET_RX_DLK_TIME_8821C(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8821C) & BIT_MASK_RX_DLK_TIME_8821C) - - - /* 2 REG_RX_PKT_LIMIT_8821C (RX PACKET LENGTH LIMIT REGISTER) */ #define BIT_SHIFT_RXPKTLMT_8821C 0 #define BIT_MASK_RXPKTLMT_8821C 0x3f -#define BIT_RXPKTLMT_8821C(x) (((x) & BIT_MASK_RXPKTLMT_8821C) << BIT_SHIFT_RXPKTLMT_8821C) -#define BIT_GET_RXPKTLMT_8821C(x) (((x) >> BIT_SHIFT_RXPKTLMT_8821C) & BIT_MASK_RXPKTLMT_8821C) - +#define BIT_RXPKTLMT_8821C(x) \ + (((x) & BIT_MASK_RXPKTLMT_8821C) << BIT_SHIFT_RXPKTLMT_8821C) +#define BITS_RXPKTLMT_8821C \ + (BIT_MASK_RXPKTLMT_8821C << BIT_SHIFT_RXPKTLMT_8821C) +#define BIT_CLEAR_RXPKTLMT_8821C(x) ((x) & (~BITS_RXPKTLMT_8821C)) +#define BIT_GET_RXPKTLMT_8821C(x) \ + (((x) >> BIT_SHIFT_RXPKTLMT_8821C) & BIT_MASK_RXPKTLMT_8821C) +#define BIT_SET_RXPKTLMT_8821C(x, v) \ + (BIT_CLEAR_RXPKTLMT_8821C(x) | BIT_RXPKTLMT_8821C(v)) +/* 2 REG_RX_DLK_TIME_8821C (RX DEADLOCK TIME REGISTER) */ -/* 2 REG_MACID_8821C (MAC ID REGISTER) */ +#define BIT_SHIFT_RX_DLK_TIME_8821C 0 +#define BIT_MASK_RX_DLK_TIME_8821C 0xff +#define BIT_RX_DLK_TIME_8821C(x) \ + (((x) & BIT_MASK_RX_DLK_TIME_8821C) << BIT_SHIFT_RX_DLK_TIME_8821C) +#define BITS_RX_DLK_TIME_8821C \ + (BIT_MASK_RX_DLK_TIME_8821C << BIT_SHIFT_RX_DLK_TIME_8821C) +#define BIT_CLEAR_RX_DLK_TIME_8821C(x) ((x) & (~BITS_RX_DLK_TIME_8821C)) +#define BIT_GET_RX_DLK_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_RX_DLK_TIME_8821C) & BIT_MASK_RX_DLK_TIME_8821C) +#define BIT_SET_RX_DLK_TIME_8821C(x, v) \ + (BIT_CLEAR_RX_DLK_TIME_8821C(x) | BIT_RX_DLK_TIME_8821C(v)) -#define BIT_SHIFT_MACID_8821C 0 -#define BIT_MASK_MACID_8821C 0xffffffffffffL -#define BIT_MACID_8821C(x) (((x) & BIT_MASK_MACID_8821C) << BIT_SHIFT_MACID_8821C) -#define BIT_GET_MACID_8821C(x) (((x) >> BIT_SHIFT_MACID_8821C) & BIT_MASK_MACID_8821C) +/* 2 REG_RSVD_8821C */ +/* 2 REG_RX_DRVINFO_SZ_8821C (RX DRIVER INFO SIZE REGISTER) */ +#define BIT_PHYSTS_PER_PKT_MODE_8821C BIT(7) +#define BIT_SHIFT_DRVINFO_SZ_V1_8821C 0 +#define BIT_MASK_DRVINFO_SZ_V1_8821C 0xf +#define BIT_DRVINFO_SZ_V1_8821C(x) \ + (((x) & BIT_MASK_DRVINFO_SZ_V1_8821C) << BIT_SHIFT_DRVINFO_SZ_V1_8821C) +#define BITS_DRVINFO_SZ_V1_8821C \ + (BIT_MASK_DRVINFO_SZ_V1_8821C << BIT_SHIFT_DRVINFO_SZ_V1_8821C) +#define BIT_CLEAR_DRVINFO_SZ_V1_8821C(x) ((x) & (~BITS_DRVINFO_SZ_V1_8821C)) +#define BIT_GET_DRVINFO_SZ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8821C) & BIT_MASK_DRVINFO_SZ_V1_8821C) +#define BIT_SET_DRVINFO_SZ_V1_8821C(x, v) \ + (BIT_CLEAR_DRVINFO_SZ_V1_8821C(x) | BIT_DRVINFO_SZ_V1_8821C(v)) + +/* 2 REG_MACID_8821C (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_V1_8821C 0 +#define BIT_MASK_MACID_V1_8821C 0xffffffffL +#define BIT_MACID_V1_8821C(x) \ + (((x) & BIT_MASK_MACID_V1_8821C) << BIT_SHIFT_MACID_V1_8821C) +#define BITS_MACID_V1_8821C \ + (BIT_MASK_MACID_V1_8821C << BIT_SHIFT_MACID_V1_8821C) +#define BIT_CLEAR_MACID_V1_8821C(x) ((x) & (~BITS_MACID_V1_8821C)) +#define BIT_GET_MACID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID_V1_8821C) & BIT_MASK_MACID_V1_8821C) +#define BIT_SET_MACID_V1_8821C(x, v) \ + (BIT_CLEAR_MACID_V1_8821C(x) | BIT_MACID_V1_8821C(v)) + +/* 2 REG_MACID_H_8821C (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_H_V1_8821C 0 +#define BIT_MASK_MACID_H_V1_8821C 0xffff +#define BIT_MACID_H_V1_8821C(x) \ + (((x) & BIT_MASK_MACID_H_V1_8821C) << BIT_SHIFT_MACID_H_V1_8821C) +#define BITS_MACID_H_V1_8821C \ + (BIT_MASK_MACID_H_V1_8821C << BIT_SHIFT_MACID_H_V1_8821C) +#define BIT_CLEAR_MACID_H_V1_8821C(x) ((x) & (~BITS_MACID_H_V1_8821C)) +#define BIT_GET_MACID_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID_H_V1_8821C) & BIT_MASK_MACID_H_V1_8821C) +#define BIT_SET_MACID_H_V1_8821C(x, v) \ + (BIT_CLEAR_MACID_H_V1_8821C(x) | BIT_MACID_H_V1_8821C(v)) /* 2 REG_BSSID_8821C (BSSID REGISTER) */ -#define BIT_SHIFT_BSSID_8821C 0 -#define BIT_MASK_BSSID_8821C 0xffffffffffffL -#define BIT_BSSID_8821C(x) (((x) & BIT_MASK_BSSID_8821C) << BIT_SHIFT_BSSID_8821C) -#define BIT_GET_BSSID_8821C(x) (((x) >> BIT_SHIFT_BSSID_8821C) & BIT_MASK_BSSID_8821C) - +#define BIT_SHIFT_BSSID_V1_8821C 0 +#define BIT_MASK_BSSID_V1_8821C 0xffffffffL +#define BIT_BSSID_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID_V1_8821C) << BIT_SHIFT_BSSID_V1_8821C) +#define BITS_BSSID_V1_8821C \ + (BIT_MASK_BSSID_V1_8821C << BIT_SHIFT_BSSID_V1_8821C) +#define BIT_CLEAR_BSSID_V1_8821C(x) ((x) & (~BITS_BSSID_V1_8821C)) +#define BIT_GET_BSSID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID_V1_8821C) & BIT_MASK_BSSID_V1_8821C) +#define BIT_SET_BSSID_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID_V1_8821C(x) | BIT_BSSID_V1_8821C(v)) +/* 2 REG_BSSID_H_8821C (BSSID REGISTER) */ -/* 2 REG_MAR_8821C (MULTICAST ADDRESS REGISTER) */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_MAR_8821C 0 -#define BIT_MASK_MAR_8821C 0xffffffffffffffffL -#define BIT_MAR_8821C(x) (((x) & BIT_MASK_MAR_8821C) << BIT_SHIFT_MAR_8821C) -#define BIT_GET_MAR_8821C(x) (((x) >> BIT_SHIFT_MAR_8821C) & BIT_MASK_MAR_8821C) +#define BIT_SHIFT_BSSID_H_V1_8821C 0 +#define BIT_MASK_BSSID_H_V1_8821C 0xffff +#define BIT_BSSID_H_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID_H_V1_8821C) << BIT_SHIFT_BSSID_H_V1_8821C) +#define BITS_BSSID_H_V1_8821C \ + (BIT_MASK_BSSID_H_V1_8821C << BIT_SHIFT_BSSID_H_V1_8821C) +#define BIT_CLEAR_BSSID_H_V1_8821C(x) ((x) & (~BITS_BSSID_H_V1_8821C)) +#define BIT_GET_BSSID_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID_H_V1_8821C) & BIT_MASK_BSSID_H_V1_8821C) +#define BIT_SET_BSSID_H_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID_H_V1_8821C(x) | BIT_BSSID_H_V1_8821C(v)) +/* 2 REG_MAR_8821C (MULTICAST ADDRESS REGISTER) */ +#define BIT_SHIFT_MAR_V1_8821C 0 +#define BIT_MASK_MAR_V1_8821C 0xffffffffL +#define BIT_MAR_V1_8821C(x) \ + (((x) & BIT_MASK_MAR_V1_8821C) << BIT_SHIFT_MAR_V1_8821C) +#define BITS_MAR_V1_8821C (BIT_MASK_MAR_V1_8821C << BIT_SHIFT_MAR_V1_8821C) +#define BIT_CLEAR_MAR_V1_8821C(x) ((x) & (~BITS_MAR_V1_8821C)) +#define BIT_GET_MAR_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MAR_V1_8821C) & BIT_MASK_MAR_V1_8821C) +#define BIT_SET_MAR_V1_8821C(x, v) \ + (BIT_CLEAR_MAR_V1_8821C(x) | BIT_MAR_V1_8821C(v)) + +/* 2 REG_MAR_H_8821C (MULTICAST ADDRESS REGISTER) */ + +#define BIT_SHIFT_MAR_H_V1_8821C 0 +#define BIT_MASK_MAR_H_V1_8821C 0xffffffffL +#define BIT_MAR_H_V1_8821C(x) \ + (((x) & BIT_MASK_MAR_H_V1_8821C) << BIT_SHIFT_MAR_H_V1_8821C) +#define BITS_MAR_H_V1_8821C \ + (BIT_MASK_MAR_H_V1_8821C << BIT_SHIFT_MAR_H_V1_8821C) +#define BIT_CLEAR_MAR_H_V1_8821C(x) ((x) & (~BITS_MAR_H_V1_8821C)) +#define BIT_GET_MAR_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MAR_H_V1_8821C) & BIT_MASK_MAR_H_V1_8821C) +#define BIT_SET_MAR_H_V1_8821C(x, v) \ + (BIT_CLEAR_MAR_H_V1_8821C(x) | BIT_MAR_H_V1_8821C(v)) /* 2 REG_MBIDCAMCFG_1_8821C (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_SHIFT_MBIDCAM_RWDATA_L_8821C 0 #define BIT_MASK_MBIDCAM_RWDATA_L_8821C 0xffffffffL -#define BIT_MBIDCAM_RWDATA_L_8821C(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8821C) << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) -#define BIT_GET_MBIDCAM_RWDATA_L_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) & BIT_MASK_MBIDCAM_RWDATA_L_8821C) - - +#define BIT_MBIDCAM_RWDATA_L_8821C(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8821C) \ + << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) +#define BITS_MBIDCAM_RWDATA_L_8821C \ + (BIT_MASK_MBIDCAM_RWDATA_L_8821C << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) +#define BIT_CLEAR_MBIDCAM_RWDATA_L_8821C(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_L_8821C)) +#define BIT_GET_MBIDCAM_RWDATA_L_8821C(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) & \ + BIT_MASK_MBIDCAM_RWDATA_L_8821C) +#define BIT_SET_MBIDCAM_RWDATA_L_8821C(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_L_8821C(x) | BIT_MBIDCAM_RWDATA_L_8821C(v)) /* 2 REG_MBIDCAMCFG_2_8821C (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_MBIDCAM_POLL_8821C BIT(31) @@ -8686,9 +14332,15 @@ #define BIT_SHIFT_MBIDCAM_ADDR_8821C 24 #define BIT_MASK_MBIDCAM_ADDR_8821C 0x1f -#define BIT_MBIDCAM_ADDR_8821C(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8821C) << BIT_SHIFT_MBIDCAM_ADDR_8821C) -#define BIT_GET_MBIDCAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8821C) & BIT_MASK_MBIDCAM_ADDR_8821C) - +#define BIT_MBIDCAM_ADDR_8821C(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR_8821C) << BIT_SHIFT_MBIDCAM_ADDR_8821C) +#define BITS_MBIDCAM_ADDR_8821C \ + (BIT_MASK_MBIDCAM_ADDR_8821C << BIT_SHIFT_MBIDCAM_ADDR_8821C) +#define BIT_CLEAR_MBIDCAM_ADDR_8821C(x) ((x) & (~BITS_MBIDCAM_ADDR_8821C)) +#define BIT_GET_MBIDCAM_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8821C) & BIT_MASK_MBIDCAM_ADDR_8821C) +#define BIT_SET_MBIDCAM_ADDR_8821C(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR_8821C(x) | BIT_MBIDCAM_ADDR_8821C(v)) #define BIT_MBIDCAM_VALID_8821C BIT(23) #define BIT_LSIC_TXOP_EN_8821C BIT(17) @@ -8696,159 +14348,253 @@ #define BIT_SHIFT_MBIDCAM_RWDATA_H_8821C 0 #define BIT_MASK_MBIDCAM_RWDATA_H_8821C 0xffff -#define BIT_MBIDCAM_RWDATA_H_8821C(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8821C) << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) -#define BIT_GET_MBIDCAM_RWDATA_H_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) & BIT_MASK_MBIDCAM_RWDATA_H_8821C) - - - -/* 2 REG_ZLD_NUM_8821C */ - -#define BIT_SHIFT_ZLD_NUM_8821C 0 -#define BIT_MASK_ZLD_NUM_8821C 0xff -#define BIT_ZLD_NUM_8821C(x) (((x) & BIT_MASK_ZLD_NUM_8821C) << BIT_SHIFT_ZLD_NUM_8821C) -#define BIT_GET_ZLD_NUM_8821C(x) (((x) >> BIT_SHIFT_ZLD_NUM_8821C) & BIT_MASK_ZLD_NUM_8821C) - - - -/* 2 REG_UDF_THSD_8821C */ - -#define BIT_SHIFT_UDF_THSD_8821C 0 -#define BIT_MASK_UDF_THSD_8821C 0xff -#define BIT_UDF_THSD_8821C(x) (((x) & BIT_MASK_UDF_THSD_8821C) << BIT_SHIFT_UDF_THSD_8821C) -#define BIT_GET_UDF_THSD_8821C(x) (((x) >> BIT_SHIFT_UDF_THSD_8821C) & BIT_MASK_UDF_THSD_8821C) - - +#define BIT_MBIDCAM_RWDATA_H_8821C(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8821C) \ + << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) +#define BITS_MBIDCAM_RWDATA_H_8821C \ + (BIT_MASK_MBIDCAM_RWDATA_H_8821C << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) +#define BIT_CLEAR_MBIDCAM_RWDATA_H_8821C(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_H_8821C)) +#define BIT_GET_MBIDCAM_RWDATA_H_8821C(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) & \ + BIT_MASK_MBIDCAM_RWDATA_H_8821C) +#define BIT_SET_MBIDCAM_RWDATA_H_8821C(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_H_8821C(x) | BIT_MBIDCAM_RWDATA_H_8821C(v)) /* 2 REG_WMAC_TCR_TSFT_OFS_8821C */ #define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C 0 #define BIT_MASK_WMAC_TCR_TSFT_OFS_8821C 0xffff -#define BIT_WMAC_TCR_TSFT_OFS_8821C(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) -#define BIT_GET_WMAC_TCR_TSFT_OFS_8821C(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) +#define BIT_WMAC_TCR_TSFT_OFS_8821C(x) \ + (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) \ + << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) +#define BITS_WMAC_TCR_TSFT_OFS_8821C \ + (BIT_MASK_WMAC_TCR_TSFT_OFS_8821C << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8821C(x) \ + ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8821C)) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) & \ + BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) +#define BIT_SET_WMAC_TCR_TSFT_OFS_8821C(x, v) \ + (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8821C(x) | BIT_WMAC_TCR_TSFT_OFS_8821C(v)) +/* 2 REG_UDF_THSD_8821C */ +#define BIT_SHIFT_UDF_THSD_8821C 0 +#define BIT_MASK_UDF_THSD_8821C 0xff +#define BIT_UDF_THSD_8821C(x) \ + (((x) & BIT_MASK_UDF_THSD_8821C) << BIT_SHIFT_UDF_THSD_8821C) +#define BITS_UDF_THSD_8821C \ + (BIT_MASK_UDF_THSD_8821C << BIT_SHIFT_UDF_THSD_8821C) +#define BIT_CLEAR_UDF_THSD_8821C(x) ((x) & (~BITS_UDF_THSD_8821C)) +#define BIT_GET_UDF_THSD_8821C(x) \ + (((x) >> BIT_SHIFT_UDF_THSD_8821C) & BIT_MASK_UDF_THSD_8821C) +#define BIT_SET_UDF_THSD_8821C(x, v) \ + (BIT_CLEAR_UDF_THSD_8821C(x) | BIT_UDF_THSD_8821C(v)) -/* 2 REG_MCU_TEST_2_V1_8821C */ +/* 2 REG_ZLD_NUM_8821C */ -#define BIT_SHIFT_MCU_RSVD_2_V1_8821C 0 -#define BIT_MASK_MCU_RSVD_2_V1_8821C 0xffff -#define BIT_MCU_RSVD_2_V1_8821C(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8821C) << BIT_SHIFT_MCU_RSVD_2_V1_8821C) -#define BIT_GET_MCU_RSVD_2_V1_8821C(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8821C) & BIT_MASK_MCU_RSVD_2_V1_8821C) +#define BIT_SHIFT_ZLD_NUM_8821C 0 +#define BIT_MASK_ZLD_NUM_8821C 0xff +#define BIT_ZLD_NUM_8821C(x) \ + (((x) & BIT_MASK_ZLD_NUM_8821C) << BIT_SHIFT_ZLD_NUM_8821C) +#define BITS_ZLD_NUM_8821C (BIT_MASK_ZLD_NUM_8821C << BIT_SHIFT_ZLD_NUM_8821C) +#define BIT_CLEAR_ZLD_NUM_8821C(x) ((x) & (~BITS_ZLD_NUM_8821C)) +#define BIT_GET_ZLD_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_ZLD_NUM_8821C) & BIT_MASK_ZLD_NUM_8821C) +#define BIT_SET_ZLD_NUM_8821C(x, v) \ + (BIT_CLEAR_ZLD_NUM_8821C(x) | BIT_ZLD_NUM_8821C(v)) +/* 2 REG_STMP_THSD_8821C */ +#define BIT_SHIFT_STMP_THSD_8821C 0 +#define BIT_MASK_STMP_THSD_8821C 0xff +#define BIT_STMP_THSD_8821C(x) \ + (((x) & BIT_MASK_STMP_THSD_8821C) << BIT_SHIFT_STMP_THSD_8821C) +#define BITS_STMP_THSD_8821C \ + (BIT_MASK_STMP_THSD_8821C << BIT_SHIFT_STMP_THSD_8821C) +#define BIT_CLEAR_STMP_THSD_8821C(x) ((x) & (~BITS_STMP_THSD_8821C)) +#define BIT_GET_STMP_THSD_8821C(x) \ + (((x) >> BIT_SHIFT_STMP_THSD_8821C) & BIT_MASK_STMP_THSD_8821C) +#define BIT_SET_STMP_THSD_8821C(x, v) \ + (BIT_CLEAR_STMP_THSD_8821C(x) | BIT_STMP_THSD_8821C(v)) /* 2 REG_WMAC_TXTIMEOUT_8821C */ #define BIT_SHIFT_WMAC_TXTIMEOUT_8821C 0 #define BIT_MASK_WMAC_TXTIMEOUT_8821C 0xff -#define BIT_WMAC_TXTIMEOUT_8821C(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8821C) << BIT_SHIFT_WMAC_TXTIMEOUT_8821C) -#define BIT_GET_WMAC_TXTIMEOUT_8821C(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8821C) & BIT_MASK_WMAC_TXTIMEOUT_8821C) +#define BIT_WMAC_TXTIMEOUT_8821C(x) \ + (((x) & BIT_MASK_WMAC_TXTIMEOUT_8821C) \ + << BIT_SHIFT_WMAC_TXTIMEOUT_8821C) +#define BITS_WMAC_TXTIMEOUT_8821C \ + (BIT_MASK_WMAC_TXTIMEOUT_8821C << BIT_SHIFT_WMAC_TXTIMEOUT_8821C) +#define BIT_CLEAR_WMAC_TXTIMEOUT_8821C(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8821C)) +#define BIT_GET_WMAC_TXTIMEOUT_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8821C) & \ + BIT_MASK_WMAC_TXTIMEOUT_8821C) +#define BIT_SET_WMAC_TXTIMEOUT_8821C(x, v) \ + (BIT_CLEAR_WMAC_TXTIMEOUT_8821C(x) | BIT_WMAC_TXTIMEOUT_8821C(v)) +/* 2 REG_MCU_TEST_2_V1_8821C */ +#define BIT_SHIFT_MCU_RSVD_2_V1_8821C 0 +#define BIT_MASK_MCU_RSVD_2_V1_8821C 0xffff +#define BIT_MCU_RSVD_2_V1_8821C(x) \ + (((x) & BIT_MASK_MCU_RSVD_2_V1_8821C) << BIT_SHIFT_MCU_RSVD_2_V1_8821C) +#define BITS_MCU_RSVD_2_V1_8821C \ + (BIT_MASK_MCU_RSVD_2_V1_8821C << BIT_SHIFT_MCU_RSVD_2_V1_8821C) +#define BIT_CLEAR_MCU_RSVD_2_V1_8821C(x) ((x) & (~BITS_MCU_RSVD_2_V1_8821C)) +#define BIT_GET_MCU_RSVD_2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8821C) & BIT_MASK_MCU_RSVD_2_V1_8821C) +#define BIT_SET_MCU_RSVD_2_V1_8821C(x, v) \ + (BIT_CLEAR_MCU_RSVD_2_V1_8821C(x) | BIT_MCU_RSVD_2_V1_8821C(v)) -/* 2 REG_STMP_THSD_8821C */ +/* 2 REG_USTIME_EDCA_8821C (US TIME TUNING FOR EDCA REGISTER) */ -#define BIT_SHIFT_STMP_THSD_8821C 0 -#define BIT_MASK_STMP_THSD_8821C 0xff -#define BIT_STMP_THSD_8821C(x) (((x) & BIT_MASK_STMP_THSD_8821C) << BIT_SHIFT_STMP_THSD_8821C) -#define BIT_GET_STMP_THSD_8821C(x) (((x) >> BIT_SHIFT_STMP_THSD_8821C) & BIT_MASK_STMP_THSD_8821C) +#define BIT_SHIFT_USTIME_EDCA_8821C 0 +#define BIT_MASK_USTIME_EDCA_8821C 0xff +#define BIT_USTIME_EDCA_8821C(x) \ + (((x) & BIT_MASK_USTIME_EDCA_8821C) << BIT_SHIFT_USTIME_EDCA_8821C) +#define BITS_USTIME_EDCA_8821C \ + (BIT_MASK_USTIME_EDCA_8821C << BIT_SHIFT_USTIME_EDCA_8821C) +#define BIT_CLEAR_USTIME_EDCA_8821C(x) ((x) & (~BITS_USTIME_EDCA_8821C)) +#define BIT_GET_USTIME_EDCA_8821C(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA_8821C) & BIT_MASK_USTIME_EDCA_8821C) +#define BIT_SET_USTIME_EDCA_8821C(x, v) \ + (BIT_CLEAR_USTIME_EDCA_8821C(x) | BIT_USTIME_EDCA_8821C(v)) +/* 2 REG_ACKTO_CCK_8821C (ACK TIMEOUT REGISTER FOR CCK RATE) */ +#define BIT_SHIFT_ACKTO_CCK_8821C 0 +#define BIT_MASK_ACKTO_CCK_8821C 0xff +#define BIT_ACKTO_CCK_8821C(x) \ + (((x) & BIT_MASK_ACKTO_CCK_8821C) << BIT_SHIFT_ACKTO_CCK_8821C) +#define BITS_ACKTO_CCK_8821C \ + (BIT_MASK_ACKTO_CCK_8821C << BIT_SHIFT_ACKTO_CCK_8821C) +#define BIT_CLEAR_ACKTO_CCK_8821C(x) ((x) & (~BITS_ACKTO_CCK_8821C)) +#define BIT_GET_ACKTO_CCK_8821C(x) \ + (((x) >> BIT_SHIFT_ACKTO_CCK_8821C) & BIT_MASK_ACKTO_CCK_8821C) +#define BIT_SET_ACKTO_CCK_8821C(x, v) \ + (BIT_CLEAR_ACKTO_CCK_8821C(x) | BIT_ACKTO_CCK_8821C(v)) /* 2 REG_MAC_SPEC_SIFS_8821C (SPECIFICATION SIFS REGISTER) */ #define BIT_SHIFT_SPEC_SIFS_OFDM_8821C 8 #define BIT_MASK_SPEC_SIFS_OFDM_8821C 0xff -#define BIT_SPEC_SIFS_OFDM_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8821C) << BIT_SHIFT_SPEC_SIFS_OFDM_8821C) -#define BIT_GET_SPEC_SIFS_OFDM_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8821C) & BIT_MASK_SPEC_SIFS_OFDM_8821C) - - +#define BIT_SPEC_SIFS_OFDM_8821C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_8821C) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_8821C) +#define BITS_SPEC_SIFS_OFDM_8821C \ + (BIT_MASK_SPEC_SIFS_OFDM_8821C << BIT_SHIFT_SPEC_SIFS_OFDM_8821C) +#define BIT_CLEAR_SPEC_SIFS_OFDM_8821C(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8821C)) +#define BIT_GET_SPEC_SIFS_OFDM_8821C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8821C) & \ + BIT_MASK_SPEC_SIFS_OFDM_8821C) +#define BIT_SET_SPEC_SIFS_OFDM_8821C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_8821C(x) | BIT_SPEC_SIFS_OFDM_8821C(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_8821C 0 #define BIT_MASK_SPEC_SIFS_CCK_8821C 0xff -#define BIT_SPEC_SIFS_CCK_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_8821C) -#define BIT_GET_SPEC_SIFS_CCK_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8821C) & BIT_MASK_SPEC_SIFS_CCK_8821C) +#define BIT_SPEC_SIFS_CCK_8821C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_8821C) +#define BITS_SPEC_SIFS_CCK_8821C \ + (BIT_MASK_SPEC_SIFS_CCK_8821C << BIT_SHIFT_SPEC_SIFS_CCK_8821C) +#define BIT_CLEAR_SPEC_SIFS_CCK_8821C(x) ((x) & (~BITS_SPEC_SIFS_CCK_8821C)) +#define BIT_GET_SPEC_SIFS_CCK_8821C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8821C) & BIT_MASK_SPEC_SIFS_CCK_8821C) +#define BIT_SET_SPEC_SIFS_CCK_8821C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_8821C(x) | BIT_SPEC_SIFS_CCK_8821C(v)) +/* 2 REG_RESP_SIFS_CCK_8821C (RESPONSE SIFS FOR CCK REGISTER) */ +#define BIT_SHIFT_SIFS_R2T_CCK_8821C 8 +#define BIT_MASK_SIFS_R2T_CCK_8821C 0xff +#define BIT_SIFS_R2T_CCK_8821C(x) \ + (((x) & BIT_MASK_SIFS_R2T_CCK_8821C) << BIT_SHIFT_SIFS_R2T_CCK_8821C) +#define BITS_SIFS_R2T_CCK_8821C \ + (BIT_MASK_SIFS_R2T_CCK_8821C << BIT_SHIFT_SIFS_R2T_CCK_8821C) +#define BIT_CLEAR_SIFS_R2T_CCK_8821C(x) ((x) & (~BITS_SIFS_R2T_CCK_8821C)) +#define BIT_GET_SIFS_R2T_CCK_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8821C) & BIT_MASK_SIFS_R2T_CCK_8821C) +#define BIT_SET_SIFS_R2T_CCK_8821C(x, v) \ + (BIT_CLEAR_SIFS_R2T_CCK_8821C(x) | BIT_SIFS_R2T_CCK_8821C(v)) -/* 2 REG_ACKTO_CCK_8821C (ACK TIMEOUT REGISTER FOR CCK RATE) */ - -#define BIT_SHIFT_ACKTO_CCK_8821C 0 -#define BIT_MASK_ACKTO_CCK_8821C 0xff -#define BIT_ACKTO_CCK_8821C(x) (((x) & BIT_MASK_ACKTO_CCK_8821C) << BIT_SHIFT_ACKTO_CCK_8821C) -#define BIT_GET_ACKTO_CCK_8821C(x) (((x) >> BIT_SHIFT_ACKTO_CCK_8821C) & BIT_MASK_ACKTO_CCK_8821C) - - - -/* 2 REG_USTIME_EDCA_8821C (US TIME TUNING FOR EDCA REGISTER) */ - -#define BIT_SHIFT_USTIME_EDCA_V1_8821C 0 -#define BIT_MASK_USTIME_EDCA_V1_8821C 0x1ff -#define BIT_USTIME_EDCA_V1_8821C(x) (((x) & BIT_MASK_USTIME_EDCA_V1_8821C) << BIT_SHIFT_USTIME_EDCA_V1_8821C) -#define BIT_GET_USTIME_EDCA_V1_8821C(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8821C) & BIT_MASK_USTIME_EDCA_V1_8821C) - - +#define BIT_SHIFT_SIFS_T2T_CCK_8821C 0 +#define BIT_MASK_SIFS_T2T_CCK_8821C 0xff +#define BIT_SIFS_T2T_CCK_8821C(x) \ + (((x) & BIT_MASK_SIFS_T2T_CCK_8821C) << BIT_SHIFT_SIFS_T2T_CCK_8821C) +#define BITS_SIFS_T2T_CCK_8821C \ + (BIT_MASK_SIFS_T2T_CCK_8821C << BIT_SHIFT_SIFS_T2T_CCK_8821C) +#define BIT_CLEAR_SIFS_T2T_CCK_8821C(x) ((x) & (~BITS_SIFS_T2T_CCK_8821C)) +#define BIT_GET_SIFS_T2T_CCK_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8821C) & BIT_MASK_SIFS_T2T_CCK_8821C) +#define BIT_SET_SIFS_T2T_CCK_8821C(x, v) \ + (BIT_CLEAR_SIFS_T2T_CCK_8821C(x) | BIT_SIFS_T2T_CCK_8821C(v)) /* 2 REG_RESP_SIFS_OFDM_8821C (RESPONSE SIFS FOR OFDM REGISTER) */ #define BIT_SHIFT_SIFS_R2T_OFDM_8821C 8 #define BIT_MASK_SIFS_R2T_OFDM_8821C 0xff -#define BIT_SIFS_R2T_OFDM_8821C(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8821C) << BIT_SHIFT_SIFS_R2T_OFDM_8821C) -#define BIT_GET_SIFS_R2T_OFDM_8821C(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8821C) & BIT_MASK_SIFS_R2T_OFDM_8821C) - - +#define BIT_SIFS_R2T_OFDM_8821C(x) \ + (((x) & BIT_MASK_SIFS_R2T_OFDM_8821C) << BIT_SHIFT_SIFS_R2T_OFDM_8821C) +#define BITS_SIFS_R2T_OFDM_8821C \ + (BIT_MASK_SIFS_R2T_OFDM_8821C << BIT_SHIFT_SIFS_R2T_OFDM_8821C) +#define BIT_CLEAR_SIFS_R2T_OFDM_8821C(x) ((x) & (~BITS_SIFS_R2T_OFDM_8821C)) +#define BIT_GET_SIFS_R2T_OFDM_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8821C) & BIT_MASK_SIFS_R2T_OFDM_8821C) +#define BIT_SET_SIFS_R2T_OFDM_8821C(x, v) \ + (BIT_CLEAR_SIFS_R2T_OFDM_8821C(x) | BIT_SIFS_R2T_OFDM_8821C(v)) #define BIT_SHIFT_SIFS_T2T_OFDM_8821C 0 #define BIT_MASK_SIFS_T2T_OFDM_8821C 0xff -#define BIT_SIFS_T2T_OFDM_8821C(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8821C) << BIT_SHIFT_SIFS_T2T_OFDM_8821C) -#define BIT_GET_SIFS_T2T_OFDM_8821C(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8821C) & BIT_MASK_SIFS_T2T_OFDM_8821C) - - - -/* 2 REG_RESP_SIFS_CCK_8821C (RESPONSE SIFS FOR CCK REGISTER) */ - -#define BIT_SHIFT_SIFS_R2T_CCK_8821C 8 -#define BIT_MASK_SIFS_R2T_CCK_8821C 0xff -#define BIT_SIFS_R2T_CCK_8821C(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8821C) << BIT_SHIFT_SIFS_R2T_CCK_8821C) -#define BIT_GET_SIFS_R2T_CCK_8821C(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8821C) & BIT_MASK_SIFS_R2T_CCK_8821C) - +#define BIT_SIFS_T2T_OFDM_8821C(x) \ + (((x) & BIT_MASK_SIFS_T2T_OFDM_8821C) << BIT_SHIFT_SIFS_T2T_OFDM_8821C) +#define BITS_SIFS_T2T_OFDM_8821C \ + (BIT_MASK_SIFS_T2T_OFDM_8821C << BIT_SHIFT_SIFS_T2T_OFDM_8821C) +#define BIT_CLEAR_SIFS_T2T_OFDM_8821C(x) ((x) & (~BITS_SIFS_T2T_OFDM_8821C)) +#define BIT_GET_SIFS_T2T_OFDM_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8821C) & BIT_MASK_SIFS_T2T_OFDM_8821C) +#define BIT_SET_SIFS_T2T_OFDM_8821C(x, v) \ + (BIT_CLEAR_SIFS_T2T_OFDM_8821C(x) | BIT_SIFS_T2T_OFDM_8821C(v)) +/* 2 REG_ACKTO_8821C (ACK TIMEOUT REGISTER) */ -#define BIT_SHIFT_SIFS_T2T_CCK_8821C 0 -#define BIT_MASK_SIFS_T2T_CCK_8821C 0xff -#define BIT_SIFS_T2T_CCK_8821C(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8821C) << BIT_SHIFT_SIFS_T2T_CCK_8821C) -#define BIT_GET_SIFS_T2T_CCK_8821C(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8821C) & BIT_MASK_SIFS_T2T_CCK_8821C) +#define BIT_SHIFT_ACKTO_8821C 0 +#define BIT_MASK_ACKTO_8821C 0xff +#define BIT_ACKTO_8821C(x) \ + (((x) & BIT_MASK_ACKTO_8821C) << BIT_SHIFT_ACKTO_8821C) +#define BITS_ACKTO_8821C (BIT_MASK_ACKTO_8821C << BIT_SHIFT_ACKTO_8821C) +#define BIT_CLEAR_ACKTO_8821C(x) ((x) & (~BITS_ACKTO_8821C)) +#define BIT_GET_ACKTO_8821C(x) \ + (((x) >> BIT_SHIFT_ACKTO_8821C) & BIT_MASK_ACKTO_8821C) +#define BIT_SET_ACKTO_8821C(x, v) \ + (BIT_CLEAR_ACKTO_8821C(x) | BIT_ACKTO_8821C(v)) +/* 2 REG_CTS2TO_8821C (CTS2 TIMEOUT REGISTER) */ +#define BIT_SHIFT_CTS2TO_8821C 0 +#define BIT_MASK_CTS2TO_8821C 0xff +#define BIT_CTS2TO_8821C(x) \ + (((x) & BIT_MASK_CTS2TO_8821C) << BIT_SHIFT_CTS2TO_8821C) +#define BITS_CTS2TO_8821C (BIT_MASK_CTS2TO_8821C << BIT_SHIFT_CTS2TO_8821C) +#define BIT_CLEAR_CTS2TO_8821C(x) ((x) & (~BITS_CTS2TO_8821C)) +#define BIT_GET_CTS2TO_8821C(x) \ + (((x) >> BIT_SHIFT_CTS2TO_8821C) & BIT_MASK_CTS2TO_8821C) +#define BIT_SET_CTS2TO_8821C(x, v) \ + (BIT_CLEAR_CTS2TO_8821C(x) | BIT_CTS2TO_8821C(v)) /* 2 REG_EIFS_8821C (EIFS REGISTER) */ #define BIT_SHIFT_EIFS_8821C 0 #define BIT_MASK_EIFS_8821C 0xffff #define BIT_EIFS_8821C(x) (((x) & BIT_MASK_EIFS_8821C) << BIT_SHIFT_EIFS_8821C) -#define BIT_GET_EIFS_8821C(x) (((x) >> BIT_SHIFT_EIFS_8821C) & BIT_MASK_EIFS_8821C) - - - -/* 2 REG_CTS2TO_8821C (CTS2 TIMEOUT REGISTER) */ - -#define BIT_SHIFT_CTS2TO_8821C 0 -#define BIT_MASK_CTS2TO_8821C 0xff -#define BIT_CTS2TO_8821C(x) (((x) & BIT_MASK_CTS2TO_8821C) << BIT_SHIFT_CTS2TO_8821C) -#define BIT_GET_CTS2TO_8821C(x) (((x) >> BIT_SHIFT_CTS2TO_8821C) & BIT_MASK_CTS2TO_8821C) - - - -/* 2 REG_ACKTO_8821C (ACK TIMEOUT REGISTER) */ - -#define BIT_SHIFT_ACKTO_8821C 0 -#define BIT_MASK_ACKTO_8821C 0xff -#define BIT_ACKTO_8821C(x) (((x) & BIT_MASK_ACKTO_8821C) << BIT_SHIFT_ACKTO_8821C) -#define BIT_GET_ACKTO_8821C(x) (((x) >> BIT_SHIFT_ACKTO_8821C) & BIT_MASK_ACKTO_8821C) +#define BITS_EIFS_8821C (BIT_MASK_EIFS_8821C << BIT_SHIFT_EIFS_8821C) +#define BIT_CLEAR_EIFS_8821C(x) ((x) & (~BITS_EIFS_8821C)) +#define BIT_GET_EIFS_8821C(x) \ + (((x) >> BIT_SHIFT_EIFS_8821C) & BIT_MASK_EIFS_8821C) +#define BIT_SET_EIFS_8821C(x, v) (BIT_CLEAR_EIFS_8821C(x) | BIT_EIFS_8821C(v)) - - -/* 2 REG_RPFM_MAP0_8821C (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 0) */ +/* 2 REG_RPFM_MAP0_8821C */ #define BIT_MGT_RPFM15EN_8821C BIT(15) #define BIT_MGT_RPFM14EN_8821C BIT(14) #define BIT_MGT_RPFM13EN_8821C BIT(13) @@ -8866,7 +14612,7 @@ #define BIT_MGT_RPFM1EN_8821C BIT(1) #define BIT_MGT_RPFM0EN_8821C BIT(0) -/* 2 REG_RPFM_MAP1_8821C (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 1) */ +/* 2 REG_RPFM_MAP1_V1_8821C */ #define BIT_DATA_RPFM15EN_8821C BIT(15) #define BIT_DATA_RPFM14EN_8821C BIT(14) #define BIT_DATA_RPFM13EN_8821C BIT(13) @@ -8891,44 +14637,66 @@ #define BIT_SHIFT_RPFM_CAM_ADDR_8821C 0 #define BIT_MASK_RPFM_CAM_ADDR_8821C 0x7f -#define BIT_RPFM_CAM_ADDR_8821C(x) (((x) & BIT_MASK_RPFM_CAM_ADDR_8821C) << BIT_SHIFT_RPFM_CAM_ADDR_8821C) -#define BIT_GET_RPFM_CAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8821C) & BIT_MASK_RPFM_CAM_ADDR_8821C) - - +#define BIT_RPFM_CAM_ADDR_8821C(x) \ + (((x) & BIT_MASK_RPFM_CAM_ADDR_8821C) << BIT_SHIFT_RPFM_CAM_ADDR_8821C) +#define BITS_RPFM_CAM_ADDR_8821C \ + (BIT_MASK_RPFM_CAM_ADDR_8821C << BIT_SHIFT_RPFM_CAM_ADDR_8821C) +#define BIT_CLEAR_RPFM_CAM_ADDR_8821C(x) ((x) & (~BITS_RPFM_CAM_ADDR_8821C)) +#define BIT_GET_RPFM_CAM_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8821C) & BIT_MASK_RPFM_CAM_ADDR_8821C) +#define BIT_SET_RPFM_CAM_ADDR_8821C(x, v) \ + (BIT_CLEAR_RPFM_CAM_ADDR_8821C(x) | BIT_RPFM_CAM_ADDR_8821C(v)) /* 2 REG_RPFM_CAM_RWD_8821C (ACK TIMEOUT REGISTER) */ #define BIT_SHIFT_RPFM_CAM_RWD_8821C 0 #define BIT_MASK_RPFM_CAM_RWD_8821C 0xffffffffL -#define BIT_RPFM_CAM_RWD_8821C(x) (((x) & BIT_MASK_RPFM_CAM_RWD_8821C) << BIT_SHIFT_RPFM_CAM_RWD_8821C) -#define BIT_GET_RPFM_CAM_RWD_8821C(x) (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8821C) & BIT_MASK_RPFM_CAM_RWD_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_RPFM_CAM_RWD_8821C(x) \ + (((x) & BIT_MASK_RPFM_CAM_RWD_8821C) << BIT_SHIFT_RPFM_CAM_RWD_8821C) +#define BITS_RPFM_CAM_RWD_8821C \ + (BIT_MASK_RPFM_CAM_RWD_8821C << BIT_SHIFT_RPFM_CAM_RWD_8821C) +#define BIT_CLEAR_RPFM_CAM_RWD_8821C(x) ((x) & (~BITS_RPFM_CAM_RWD_8821C)) +#define BIT_GET_RPFM_CAM_RWD_8821C(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8821C) & BIT_MASK_RPFM_CAM_RWD_8821C) +#define BIT_SET_RPFM_CAM_RWD_8821C(x, v) \ + (BIT_CLEAR_RPFM_CAM_RWD_8821C(x) | BIT_RPFM_CAM_RWD_8821C(v)) /* 2 REG_NAV_CTRL_8821C (NAV CONTROL REGISTER) */ #define BIT_SHIFT_NAV_UPPER_8821C 16 #define BIT_MASK_NAV_UPPER_8821C 0xff -#define BIT_NAV_UPPER_8821C(x) (((x) & BIT_MASK_NAV_UPPER_8821C) << BIT_SHIFT_NAV_UPPER_8821C) -#define BIT_GET_NAV_UPPER_8821C(x) (((x) >> BIT_SHIFT_NAV_UPPER_8821C) & BIT_MASK_NAV_UPPER_8821C) - - +#define BIT_NAV_UPPER_8821C(x) \ + (((x) & BIT_MASK_NAV_UPPER_8821C) << BIT_SHIFT_NAV_UPPER_8821C) +#define BITS_NAV_UPPER_8821C \ + (BIT_MASK_NAV_UPPER_8821C << BIT_SHIFT_NAV_UPPER_8821C) +#define BIT_CLEAR_NAV_UPPER_8821C(x) ((x) & (~BITS_NAV_UPPER_8821C)) +#define BIT_GET_NAV_UPPER_8821C(x) \ + (((x) >> BIT_SHIFT_NAV_UPPER_8821C) & BIT_MASK_NAV_UPPER_8821C) +#define BIT_SET_NAV_UPPER_8821C(x, v) \ + (BIT_CLEAR_NAV_UPPER_8821C(x) | BIT_NAV_UPPER_8821C(v)) #define BIT_SHIFT_RXMYRTS_NAV_8821C 8 #define BIT_MASK_RXMYRTS_NAV_8821C 0xf -#define BIT_RXMYRTS_NAV_8821C(x) (((x) & BIT_MASK_RXMYRTS_NAV_8821C) << BIT_SHIFT_RXMYRTS_NAV_8821C) -#define BIT_GET_RXMYRTS_NAV_8821C(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8821C) & BIT_MASK_RXMYRTS_NAV_8821C) - - +#define BIT_RXMYRTS_NAV_8821C(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_8821C) << BIT_SHIFT_RXMYRTS_NAV_8821C) +#define BITS_RXMYRTS_NAV_8821C \ + (BIT_MASK_RXMYRTS_NAV_8821C << BIT_SHIFT_RXMYRTS_NAV_8821C) +#define BIT_CLEAR_RXMYRTS_NAV_8821C(x) ((x) & (~BITS_RXMYRTS_NAV_8821C)) +#define BIT_GET_RXMYRTS_NAV_8821C(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_8821C) & BIT_MASK_RXMYRTS_NAV_8821C) +#define BIT_SET_RXMYRTS_NAV_8821C(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_8821C(x) | BIT_RXMYRTS_NAV_8821C(v)) #define BIT_SHIFT_RTSRST_8821C 0 #define BIT_MASK_RTSRST_8821C 0xff -#define BIT_RTSRST_8821C(x) (((x) & BIT_MASK_RTSRST_8821C) << BIT_SHIFT_RTSRST_8821C) -#define BIT_GET_RTSRST_8821C(x) (((x) >> BIT_SHIFT_RTSRST_8821C) & BIT_MASK_RTSRST_8821C) - - +#define BIT_RTSRST_8821C(x) \ + (((x) & BIT_MASK_RTSRST_8821C) << BIT_SHIFT_RTSRST_8821C) +#define BITS_RTSRST_8821C (BIT_MASK_RTSRST_8821C << BIT_SHIFT_RTSRST_8821C) +#define BIT_CLEAR_RTSRST_8821C(x) ((x) & (~BITS_RTSRST_8821C)) +#define BIT_GET_RTSRST_8821C(x) \ + (((x) >> BIT_SHIFT_RTSRST_8821C) & BIT_MASK_RTSRST_8821C) +#define BIT_SET_RTSRST_8821C(x, v) \ + (BIT_CLEAR_RTSRST_8821C(x) | BIT_RTSRST_8821C(v)) /* 2 REG_BACAMCMD_8821C (BLOCK ACK CAM COMMAND REGISTER) */ #define BIT_BACAM_POLL_8821C BIT(31) @@ -8937,87 +14705,149 @@ #define BIT_SHIFT_TXSBM_8821C 14 #define BIT_MASK_TXSBM_8821C 0x3 -#define BIT_TXSBM_8821C(x) (((x) & BIT_MASK_TXSBM_8821C) << BIT_SHIFT_TXSBM_8821C) -#define BIT_GET_TXSBM_8821C(x) (((x) >> BIT_SHIFT_TXSBM_8821C) & BIT_MASK_TXSBM_8821C) - - +#define BIT_TXSBM_8821C(x) \ + (((x) & BIT_MASK_TXSBM_8821C) << BIT_SHIFT_TXSBM_8821C) +#define BITS_TXSBM_8821C (BIT_MASK_TXSBM_8821C << BIT_SHIFT_TXSBM_8821C) +#define BIT_CLEAR_TXSBM_8821C(x) ((x) & (~BITS_TXSBM_8821C)) +#define BIT_GET_TXSBM_8821C(x) \ + (((x) >> BIT_SHIFT_TXSBM_8821C) & BIT_MASK_TXSBM_8821C) +#define BIT_SET_TXSBM_8821C(x, v) \ + (BIT_CLEAR_TXSBM_8821C(x) | BIT_TXSBM_8821C(v)) #define BIT_SHIFT_BACAM_ADDR_8821C 0 #define BIT_MASK_BACAM_ADDR_8821C 0x3f -#define BIT_BACAM_ADDR_8821C(x) (((x) & BIT_MASK_BACAM_ADDR_8821C) << BIT_SHIFT_BACAM_ADDR_8821C) -#define BIT_GET_BACAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8821C) & BIT_MASK_BACAM_ADDR_8821C) - - +#define BIT_BACAM_ADDR_8821C(x) \ + (((x) & BIT_MASK_BACAM_ADDR_8821C) << BIT_SHIFT_BACAM_ADDR_8821C) +#define BITS_BACAM_ADDR_8821C \ + (BIT_MASK_BACAM_ADDR_8821C << BIT_SHIFT_BACAM_ADDR_8821C) +#define BIT_CLEAR_BACAM_ADDR_8821C(x) ((x) & (~BITS_BACAM_ADDR_8821C)) +#define BIT_GET_BACAM_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_BACAM_ADDR_8821C) & BIT_MASK_BACAM_ADDR_8821C) +#define BIT_SET_BACAM_ADDR_8821C(x, v) \ + (BIT_CLEAR_BACAM_ADDR_8821C(x) | BIT_BACAM_ADDR_8821C(v)) /* 2 REG_BACAMCONTENT_8821C (BLOCK ACK CAM CONTENT REGISTER) */ -#define BIT_SHIFT_BA_CONTENT_H_8821C (32 & CPU_OPT_WIDTH) -#define BIT_MASK_BA_CONTENT_H_8821C 0xffffffffL -#define BIT_BA_CONTENT_H_8821C(x) (((x) & BIT_MASK_BA_CONTENT_H_8821C) << BIT_SHIFT_BA_CONTENT_H_8821C) -#define BIT_GET_BA_CONTENT_H_8821C(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8821C) & BIT_MASK_BA_CONTENT_H_8821C) - - - #define BIT_SHIFT_BA_CONTENT_L_8821C 0 #define BIT_MASK_BA_CONTENT_L_8821C 0xffffffffL -#define BIT_BA_CONTENT_L_8821C(x) (((x) & BIT_MASK_BA_CONTENT_L_8821C) << BIT_SHIFT_BA_CONTENT_L_8821C) -#define BIT_GET_BA_CONTENT_L_8821C(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8821C) & BIT_MASK_BA_CONTENT_L_8821C) - - - -/* 2 REG_WMAC_BITMAP_CTL_8821C */ -#define BIT_BITMAP_VO_8821C BIT(7) -#define BIT_BITMAP_VI_8821C BIT(6) -#define BIT_BITMAP_BE_8821C BIT(5) -#define BIT_BITMAP_BK_8821C BIT(4) - -#define BIT_SHIFT_BITMAP_CONDITION_8821C 2 -#define BIT_MASK_BITMAP_CONDITION_8821C 0x3 -#define BIT_BITMAP_CONDITION_8821C(x) (((x) & BIT_MASK_BITMAP_CONDITION_8821C) << BIT_SHIFT_BITMAP_CONDITION_8821C) -#define BIT_GET_BITMAP_CONDITION_8821C(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8821C) & BIT_MASK_BITMAP_CONDITION_8821C) - - -#define BIT_BITMAP_SSNBK_COUNTER_CLR_8821C BIT(1) -#define BIT_BITMAP_FORCE_8821C BIT(0) - -/* 2 REG_TX_RX_8821C STATUS */ - -#define BIT_SHIFT_RXPKT_TYPE_8821C 2 -#define BIT_MASK_RXPKT_TYPE_8821C 0x3f -#define BIT_RXPKT_TYPE_8821C(x) (((x) & BIT_MASK_RXPKT_TYPE_8821C) << BIT_SHIFT_RXPKT_TYPE_8821C) -#define BIT_GET_RXPKT_TYPE_8821C(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8821C) & BIT_MASK_RXPKT_TYPE_8821C) +#define BIT_BA_CONTENT_L_8821C(x) \ + (((x) & BIT_MASK_BA_CONTENT_L_8821C) << BIT_SHIFT_BA_CONTENT_L_8821C) +#define BITS_BA_CONTENT_L_8821C \ + (BIT_MASK_BA_CONTENT_L_8821C << BIT_SHIFT_BA_CONTENT_L_8821C) +#define BIT_CLEAR_BA_CONTENT_L_8821C(x) ((x) & (~BITS_BA_CONTENT_L_8821C)) +#define BIT_GET_BA_CONTENT_L_8821C(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_L_8821C) & BIT_MASK_BA_CONTENT_L_8821C) +#define BIT_SET_BA_CONTENT_L_8821C(x, v) \ + (BIT_CLEAR_BA_CONTENT_L_8821C(x) | BIT_BA_CONTENT_L_8821C(v)) + +/* 2 REG_BACAMCONTENT_H_8821C (BLOCK ACK CAM CONTENT REGISTER) */ + +#define BIT_SHIFT_BA_CONTENT_H_8821C 0 +#define BIT_MASK_BA_CONTENT_H_8821C 0xffffffffL +#define BIT_BA_CONTENT_H_8821C(x) \ + (((x) & BIT_MASK_BA_CONTENT_H_8821C) << BIT_SHIFT_BA_CONTENT_H_8821C) +#define BITS_BA_CONTENT_H_8821C \ + (BIT_MASK_BA_CONTENT_H_8821C << BIT_SHIFT_BA_CONTENT_H_8821C) +#define BIT_CLEAR_BA_CONTENT_H_8821C(x) ((x) & (~BITS_BA_CONTENT_H_8821C)) +#define BIT_GET_BA_CONTENT_H_8821C(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_H_8821C) & BIT_MASK_BA_CONTENT_H_8821C) +#define BIT_SET_BA_CONTENT_H_8821C(x, v) \ + (BIT_CLEAR_BA_CONTENT_H_8821C(x) | BIT_BA_CONTENT_H_8821C(v)) +/* 2 REG_LBDLY_8821C (LOOPBACK DELAY REGISTER) */ -#define BIT_TXACT_IND_8821C BIT(1) -#define BIT_RXACT_IND_8821C BIT(0) +#define BIT_SHIFT_LBDLY_8821C 0 +#define BIT_MASK_LBDLY_8821C 0x1f +#define BIT_LBDLY_8821C(x) \ + (((x) & BIT_MASK_LBDLY_8821C) << BIT_SHIFT_LBDLY_8821C) +#define BITS_LBDLY_8821C (BIT_MASK_LBDLY_8821C << BIT_SHIFT_LBDLY_8821C) +#define BIT_CLEAR_LBDLY_8821C(x) ((x) & (~BITS_LBDLY_8821C)) +#define BIT_GET_LBDLY_8821C(x) \ + (((x) >> BIT_SHIFT_LBDLY_8821C) & BIT_MASK_LBDLY_8821C) +#define BIT_SET_LBDLY_8821C(x, v) \ + (BIT_CLEAR_LBDLY_8821C(x) | BIT_LBDLY_8821C(v)) /* 2 REG_WMAC_BACAM_RPMEN_8821C */ #define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C 2 #define BIT_MASK_BITMAP_SSNBK_COUNTER_8821C 0x3f -#define BIT_BITMAP_SSNBK_COUNTER_8821C(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) -#define BIT_GET_BITMAP_SSNBK_COUNTER_8821C(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) - +#define BIT_BITMAP_SSNBK_COUNTER_8821C(x) \ + (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) +#define BITS_BITMAP_SSNBK_COUNTER_8821C \ + (BIT_MASK_BITMAP_SSNBK_COUNTER_8821C \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8821C(x) \ + ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8821C)) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8821C(x) \ + (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) & \ + BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) +#define BIT_SET_BITMAP_SSNBK_COUNTER_8821C(x, v) \ + (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8821C(x) | \ + BIT_BITMAP_SSNBK_COUNTER_8821C(v)) #define BIT_BITMAP_EN_8821C BIT(1) #define BIT_WMAC_BACAM_RPMEN_8821C BIT(0) -/* 2 REG_LBDLY_8821C (LOOPBACK DELAY REGISTER) */ +/* 2 REG_TX_RX_8821C STATUS */ -#define BIT_SHIFT_LBDLY_8821C 0 -#define BIT_MASK_LBDLY_8821C 0x1f -#define BIT_LBDLY_8821C(x) (((x) & BIT_MASK_LBDLY_8821C) << BIT_SHIFT_LBDLY_8821C) -#define BIT_GET_LBDLY_8821C(x) (((x) >> BIT_SHIFT_LBDLY_8821C) & BIT_MASK_LBDLY_8821C) +#define BIT_SHIFT_RXPKT_TYPE_8821C 2 +#define BIT_MASK_RXPKT_TYPE_8821C 0x3f +#define BIT_RXPKT_TYPE_8821C(x) \ + (((x) & BIT_MASK_RXPKT_TYPE_8821C) << BIT_SHIFT_RXPKT_TYPE_8821C) +#define BITS_RXPKT_TYPE_8821C \ + (BIT_MASK_RXPKT_TYPE_8821C << BIT_SHIFT_RXPKT_TYPE_8821C) +#define BIT_CLEAR_RXPKT_TYPE_8821C(x) ((x) & (~BITS_RXPKT_TYPE_8821C)) +#define BIT_GET_RXPKT_TYPE_8821C(x) \ + (((x) >> BIT_SHIFT_RXPKT_TYPE_8821C) & BIT_MASK_RXPKT_TYPE_8821C) +#define BIT_SET_RXPKT_TYPE_8821C(x, v) \ + (BIT_CLEAR_RXPKT_TYPE_8821C(x) | BIT_RXPKT_TYPE_8821C(v)) + +#define BIT_TXACT_IND_8821C BIT(1) +#define BIT_RXACT_IND_8821C BIT(0) + +/* 2 REG_WMAC_BITMAP_CTL_8821C */ +#define BIT_BITMAP_VO_8821C BIT(7) +#define BIT_BITMAP_VI_8821C BIT(6) +#define BIT_BITMAP_BE_8821C BIT(5) +#define BIT_BITMAP_BK_8821C BIT(4) +#define BIT_SHIFT_BITMAP_CONDITION_8821C 2 +#define BIT_MASK_BITMAP_CONDITION_8821C 0x3 +#define BIT_BITMAP_CONDITION_8821C(x) \ + (((x) & BIT_MASK_BITMAP_CONDITION_8821C) \ + << BIT_SHIFT_BITMAP_CONDITION_8821C) +#define BITS_BITMAP_CONDITION_8821C \ + (BIT_MASK_BITMAP_CONDITION_8821C << BIT_SHIFT_BITMAP_CONDITION_8821C) +#define BIT_CLEAR_BITMAP_CONDITION_8821C(x) \ + ((x) & (~BITS_BITMAP_CONDITION_8821C)) +#define BIT_GET_BITMAP_CONDITION_8821C(x) \ + (((x) >> BIT_SHIFT_BITMAP_CONDITION_8821C) & \ + BIT_MASK_BITMAP_CONDITION_8821C) +#define BIT_SET_BITMAP_CONDITION_8821C(x, v) \ + (BIT_CLEAR_BITMAP_CONDITION_8821C(x) | BIT_BITMAP_CONDITION_8821C(v)) +#define BIT_BITMAP_SSNBK_COUNTER_CLR_8821C BIT(1) +#define BIT_BITMAP_FORCE_8821C BIT(0) /* 2 REG_RXERR_RPT_8821C (RX ERROR REPORT REGISTER) */ #define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C 28 #define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C 0xf -#define BIT_RXERR_RPT_SEL_V1_3_0_8821C(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) -#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8821C(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) - +#define BIT_RXERR_RPT_SEL_V1_3_0_8821C(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) +#define BITS_RXERR_RPT_SEL_V1_3_0_8821C \ + (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8821C(x) \ + ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8821C)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8821C(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) & \ + BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8821C(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8821C(x) | \ + BIT_RXERR_RPT_SEL_V1_3_0_8821C(v)) #define BIT_RXERR_RPT_RST_8821C BIT(27) #define BIT_RXERR_RPT_SEL_V1_4_8821C BIT(26) @@ -9026,64 +14856,40 @@ #define BIT_SHIFT_UD_SUB_TYPE_8821C 18 #define BIT_MASK_UD_SUB_TYPE_8821C 0xf -#define BIT_UD_SUB_TYPE_8821C(x) (((x) & BIT_MASK_UD_SUB_TYPE_8821C) << BIT_SHIFT_UD_SUB_TYPE_8821C) -#define BIT_GET_UD_SUB_TYPE_8821C(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8821C) & BIT_MASK_UD_SUB_TYPE_8821C) - - +#define BIT_UD_SUB_TYPE_8821C(x) \ + (((x) & BIT_MASK_UD_SUB_TYPE_8821C) << BIT_SHIFT_UD_SUB_TYPE_8821C) +#define BITS_UD_SUB_TYPE_8821C \ + (BIT_MASK_UD_SUB_TYPE_8821C << BIT_SHIFT_UD_SUB_TYPE_8821C) +#define BIT_CLEAR_UD_SUB_TYPE_8821C(x) ((x) & (~BITS_UD_SUB_TYPE_8821C)) +#define BIT_GET_UD_SUB_TYPE_8821C(x) \ + (((x) >> BIT_SHIFT_UD_SUB_TYPE_8821C) & BIT_MASK_UD_SUB_TYPE_8821C) +#define BIT_SET_UD_SUB_TYPE_8821C(x, v) \ + (BIT_CLEAR_UD_SUB_TYPE_8821C(x) | BIT_UD_SUB_TYPE_8821C(v)) #define BIT_SHIFT_UD_TYPE_8821C 16 #define BIT_MASK_UD_TYPE_8821C 0x3 -#define BIT_UD_TYPE_8821C(x) (((x) & BIT_MASK_UD_TYPE_8821C) << BIT_SHIFT_UD_TYPE_8821C) -#define BIT_GET_UD_TYPE_8821C(x) (((x) >> BIT_SHIFT_UD_TYPE_8821C) & BIT_MASK_UD_TYPE_8821C) - - +#define BIT_UD_TYPE_8821C(x) \ + (((x) & BIT_MASK_UD_TYPE_8821C) << BIT_SHIFT_UD_TYPE_8821C) +#define BITS_UD_TYPE_8821C (BIT_MASK_UD_TYPE_8821C << BIT_SHIFT_UD_TYPE_8821C) +#define BIT_CLEAR_UD_TYPE_8821C(x) ((x) & (~BITS_UD_TYPE_8821C)) +#define BIT_GET_UD_TYPE_8821C(x) \ + (((x) >> BIT_SHIFT_UD_TYPE_8821C) & BIT_MASK_UD_TYPE_8821C) +#define BIT_SET_UD_TYPE_8821C(x, v) \ + (BIT_CLEAR_UD_TYPE_8821C(x) | BIT_UD_TYPE_8821C(v)) #define BIT_SHIFT_RPT_COUNTER_8821C 0 #define BIT_MASK_RPT_COUNTER_8821C 0xffff -#define BIT_RPT_COUNTER_8821C(x) (((x) & BIT_MASK_RPT_COUNTER_8821C) << BIT_SHIFT_RPT_COUNTER_8821C) -#define BIT_GET_RPT_COUNTER_8821C(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8821C) & BIT_MASK_RPT_COUNTER_8821C) - - - -/* 2 REG_WMAC_TRXPTCL_CTL_8821C (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ - -#define BIT_SHIFT_ACKBA_TYPSEL_8821C (60 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBA_TYPSEL_8821C 0xf -#define BIT_ACKBA_TYPSEL_8821C(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8821C) << BIT_SHIFT_ACKBA_TYPSEL_8821C) -#define BIT_GET_ACKBA_TYPSEL_8821C(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8821C) & BIT_MASK_ACKBA_TYPSEL_8821C) - - - -#define BIT_SHIFT_ACKBA_ACKPCHK_8821C (56 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBA_ACKPCHK_8821C 0xf -#define BIT_ACKBA_ACKPCHK_8821C(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8821C) << BIT_SHIFT_ACKBA_ACKPCHK_8821C) -#define BIT_GET_ACKBA_ACKPCHK_8821C(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8821C) & BIT_MASK_ACKBA_ACKPCHK_8821C) - - - -#define BIT_SHIFT_ACKBAR_TYPESEL_8821C (48 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBAR_TYPESEL_8821C 0xff -#define BIT_ACKBAR_TYPESEL_8821C(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8821C) << BIT_SHIFT_ACKBAR_TYPESEL_8821C) -#define BIT_GET_ACKBAR_TYPESEL_8821C(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8821C) & BIT_MASK_ACKBAR_TYPESEL_8821C) - - - -#define BIT_SHIFT_ACKBAR_ACKPCHK_8821C (44 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBAR_ACKPCHK_8821C 0xf -#define BIT_ACKBAR_ACKPCHK_8821C(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8821C) << BIT_SHIFT_ACKBAR_ACKPCHK_8821C) -#define BIT_GET_ACKBAR_ACKPCHK_8821C(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8821C) & BIT_MASK_ACKBAR_ACKPCHK_8821C) - - -#define BIT_RXBA_IGNOREA2_8821C BIT(42) -#define BIT_EN_SAVE_ALL_TXOPADDR_8821C BIT(41) -#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8821C BIT(40) -#define BIT_DIS_TXBA_AMPDUFCSERR_8821C BIT(39) -#define BIT_DIS_TXBA_RXBARINFULL_8821C BIT(38) -#define BIT_DIS_TXCFE_INFULL_8821C BIT(37) -#define BIT_DIS_TXCTS_INFULL_8821C BIT(36) -#define BIT_EN_TXACKBA_IN_TX_RDG_8821C BIT(35) -#define BIT_EN_TXACKBA_IN_TXOP_8821C BIT(34) -#define BIT_EN_TXCTS_IN_RXNAV_8821C BIT(33) +#define BIT_RPT_COUNTER_8821C(x) \ + (((x) & BIT_MASK_RPT_COUNTER_8821C) << BIT_SHIFT_RPT_COUNTER_8821C) +#define BITS_RPT_COUNTER_8821C \ + (BIT_MASK_RPT_COUNTER_8821C << BIT_SHIFT_RPT_COUNTER_8821C) +#define BIT_CLEAR_RPT_COUNTER_8821C(x) ((x) & (~BITS_RPT_COUNTER_8821C)) +#define BIT_GET_RPT_COUNTER_8821C(x) \ + (((x) >> BIT_SHIFT_RPT_COUNTER_8821C) & BIT_MASK_RPT_COUNTER_8821C) +#define BIT_SET_RPT_COUNTER_8821C(x, v) \ + (BIT_CLEAR_RPT_COUNTER_8821C(x) | BIT_RPT_COUNTER_8821C(v)) + +/* 2 REG_WMAC_TRXPTCL_CTL_8821C (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ #define BIT_EN_TXCTS_INTXOP_8821C BIT(32) #define BIT_BLK_EDCA_BBSLP_8821C BIT(31) #define BIT_BLK_EDCA_BBSBY_8821C BIT(30) @@ -9096,9 +14902,15 @@ #define BIT_SHIFT_RESP_CHNBUSY_8821C 20 #define BIT_MASK_RESP_CHNBUSY_8821C 0x3 -#define BIT_RESP_CHNBUSY_8821C(x) (((x) & BIT_MASK_RESP_CHNBUSY_8821C) << BIT_SHIFT_RESP_CHNBUSY_8821C) -#define BIT_GET_RESP_CHNBUSY_8821C(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8821C) & BIT_MASK_RESP_CHNBUSY_8821C) - +#define BIT_RESP_CHNBUSY_8821C(x) \ + (((x) & BIT_MASK_RESP_CHNBUSY_8821C) << BIT_SHIFT_RESP_CHNBUSY_8821C) +#define BITS_RESP_CHNBUSY_8821C \ + (BIT_MASK_RESP_CHNBUSY_8821C << BIT_SHIFT_RESP_CHNBUSY_8821C) +#define BIT_CLEAR_RESP_CHNBUSY_8821C(x) ((x) & (~BITS_RESP_CHNBUSY_8821C)) +#define BIT_GET_RESP_CHNBUSY_8821C(x) \ + (((x) >> BIT_SHIFT_RESP_CHNBUSY_8821C) & BIT_MASK_RESP_CHNBUSY_8821C) +#define BIT_SET_RESP_CHNBUSY_8821C(x, v) \ + (BIT_CLEAR_RESP_CHNBUSY_8821C(x) | BIT_RESP_CHNBUSY_8821C(v)) #define BIT_RESP_DCTS_EN_8821C BIT(19) #define BIT_RESP_DCFE_EN_8821C BIT(18) @@ -9110,33 +14922,129 @@ #define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C 10 #define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C 0x7 -#define BIT_R_WMAC_SECOND_CCA_TIMER_8821C(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) -#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) - - +#define BIT_R_WMAC_SECOND_CCA_TIMER_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) +#define BITS_R_WMAC_SECOND_CCA_TIMER_8821C \ + (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8821C(x) \ + ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8821C)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) & \ + BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8821C(x) | \ + BIT_R_WMAC_SECOND_CCA_TIMER_8821C(v)) #define BIT_SHIFT_RFMOD_8821C 7 #define BIT_MASK_RFMOD_8821C 0x3 -#define BIT_RFMOD_8821C(x) (((x) & BIT_MASK_RFMOD_8821C) << BIT_SHIFT_RFMOD_8821C) -#define BIT_GET_RFMOD_8821C(x) (((x) >> BIT_SHIFT_RFMOD_8821C) & BIT_MASK_RFMOD_8821C) - - +#define BIT_RFMOD_8821C(x) \ + (((x) & BIT_MASK_RFMOD_8821C) << BIT_SHIFT_RFMOD_8821C) +#define BITS_RFMOD_8821C (BIT_MASK_RFMOD_8821C << BIT_SHIFT_RFMOD_8821C) +#define BIT_CLEAR_RFMOD_8821C(x) ((x) & (~BITS_RFMOD_8821C)) +#define BIT_GET_RFMOD_8821C(x) \ + (((x) >> BIT_SHIFT_RFMOD_8821C) & BIT_MASK_RFMOD_8821C) +#define BIT_SET_RFMOD_8821C(x, v) \ + (BIT_CLEAR_RFMOD_8821C(x) | BIT_RFMOD_8821C(v)) #define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C 5 #define BIT_MASK_RESP_CTS_DYNBW_SEL_8821C 0x3 -#define BIT_RESP_CTS_DYNBW_SEL_8821C(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) -#define BIT_GET_RESP_CTS_DYNBW_SEL_8821C(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) - +#define BIT_RESP_CTS_DYNBW_SEL_8821C(x) \ + (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) +#define BITS_RESP_CTS_DYNBW_SEL_8821C \ + (BIT_MASK_RESP_CTS_DYNBW_SEL_8821C \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8821C(x) \ + ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8821C)) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) & \ + BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) +#define BIT_SET_RESP_CTS_DYNBW_SEL_8821C(x, v) \ + (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8821C(x) | \ + BIT_RESP_CTS_DYNBW_SEL_8821C(v)) #define BIT_DLY_TX_WAIT_RXANTSEL_8821C BIT(4) #define BIT_TXRESP_BY_RXANTSEL_8821C BIT(3) #define BIT_SHIFT_ORIG_DCTS_CHK_8821C 0 #define BIT_MASK_ORIG_DCTS_CHK_8821C 0x3 -#define BIT_ORIG_DCTS_CHK_8821C(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8821C) << BIT_SHIFT_ORIG_DCTS_CHK_8821C) -#define BIT_GET_ORIG_DCTS_CHK_8821C(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8821C) & BIT_MASK_ORIG_DCTS_CHK_8821C) - - +#define BIT_ORIG_DCTS_CHK_8821C(x) \ + (((x) & BIT_MASK_ORIG_DCTS_CHK_8821C) << BIT_SHIFT_ORIG_DCTS_CHK_8821C) +#define BITS_ORIG_DCTS_CHK_8821C \ + (BIT_MASK_ORIG_DCTS_CHK_8821C << BIT_SHIFT_ORIG_DCTS_CHK_8821C) +#define BIT_CLEAR_ORIG_DCTS_CHK_8821C(x) ((x) & (~BITS_ORIG_DCTS_CHK_8821C)) +#define BIT_GET_ORIG_DCTS_CHK_8821C(x) \ + (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8821C) & BIT_MASK_ORIG_DCTS_CHK_8821C) +#define BIT_SET_ORIG_DCTS_CHK_8821C(x, v) \ + (BIT_CLEAR_ORIG_DCTS_CHK_8821C(x) | BIT_ORIG_DCTS_CHK_8821C(v)) + +/* 2 REG_WMAC_TRXPTCL_CTL_H_8821C */ + +#define BIT_SHIFT_ACKBA_TYPSEL_8821C 28 +#define BIT_MASK_ACKBA_TYPSEL_8821C 0xf +#define BIT_ACKBA_TYPSEL_8821C(x) \ + (((x) & BIT_MASK_ACKBA_TYPSEL_8821C) << BIT_SHIFT_ACKBA_TYPSEL_8821C) +#define BITS_ACKBA_TYPSEL_8821C \ + (BIT_MASK_ACKBA_TYPSEL_8821C << BIT_SHIFT_ACKBA_TYPSEL_8821C) +#define BIT_CLEAR_ACKBA_TYPSEL_8821C(x) ((x) & (~BITS_ACKBA_TYPSEL_8821C)) +#define BIT_GET_ACKBA_TYPSEL_8821C(x) \ + (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8821C) & BIT_MASK_ACKBA_TYPSEL_8821C) +#define BIT_SET_ACKBA_TYPSEL_8821C(x, v) \ + (BIT_CLEAR_ACKBA_TYPSEL_8821C(x) | BIT_ACKBA_TYPSEL_8821C(v)) + +#define BIT_SHIFT_ACKBA_ACKPCHK_8821C 24 +#define BIT_MASK_ACKBA_ACKPCHK_8821C 0xf +#define BIT_ACKBA_ACKPCHK_8821C(x) \ + (((x) & BIT_MASK_ACKBA_ACKPCHK_8821C) << BIT_SHIFT_ACKBA_ACKPCHK_8821C) +#define BITS_ACKBA_ACKPCHK_8821C \ + (BIT_MASK_ACKBA_ACKPCHK_8821C << BIT_SHIFT_ACKBA_ACKPCHK_8821C) +#define BIT_CLEAR_ACKBA_ACKPCHK_8821C(x) ((x) & (~BITS_ACKBA_ACKPCHK_8821C)) +#define BIT_GET_ACKBA_ACKPCHK_8821C(x) \ + (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8821C) & BIT_MASK_ACKBA_ACKPCHK_8821C) +#define BIT_SET_ACKBA_ACKPCHK_8821C(x, v) \ + (BIT_CLEAR_ACKBA_ACKPCHK_8821C(x) | BIT_ACKBA_ACKPCHK_8821C(v)) + +#define BIT_SHIFT_ACKBAR_TYPESEL_8821C 16 +#define BIT_MASK_ACKBAR_TYPESEL_8821C 0xff +#define BIT_ACKBAR_TYPESEL_8821C(x) \ + (((x) & BIT_MASK_ACKBAR_TYPESEL_8821C) \ + << BIT_SHIFT_ACKBAR_TYPESEL_8821C) +#define BITS_ACKBAR_TYPESEL_8821C \ + (BIT_MASK_ACKBAR_TYPESEL_8821C << BIT_SHIFT_ACKBAR_TYPESEL_8821C) +#define BIT_CLEAR_ACKBAR_TYPESEL_8821C(x) ((x) & (~BITS_ACKBAR_TYPESEL_8821C)) +#define BIT_GET_ACKBAR_TYPESEL_8821C(x) \ + (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8821C) & \ + BIT_MASK_ACKBAR_TYPESEL_8821C) +#define BIT_SET_ACKBAR_TYPESEL_8821C(x, v) \ + (BIT_CLEAR_ACKBAR_TYPESEL_8821C(x) | BIT_ACKBAR_TYPESEL_8821C(v)) + +#define BIT_SHIFT_ACKBAR_ACKPCHK_8821C 12 +#define BIT_MASK_ACKBAR_ACKPCHK_8821C 0xf +#define BIT_ACKBAR_ACKPCHK_8821C(x) \ + (((x) & BIT_MASK_ACKBAR_ACKPCHK_8821C) \ + << BIT_SHIFT_ACKBAR_ACKPCHK_8821C) +#define BITS_ACKBAR_ACKPCHK_8821C \ + (BIT_MASK_ACKBAR_ACKPCHK_8821C << BIT_SHIFT_ACKBAR_ACKPCHK_8821C) +#define BIT_CLEAR_ACKBAR_ACKPCHK_8821C(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8821C)) +#define BIT_GET_ACKBAR_ACKPCHK_8821C(x) \ + (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8821C) & \ + BIT_MASK_ACKBAR_ACKPCHK_8821C) +#define BIT_SET_ACKBAR_ACKPCHK_8821C(x, v) \ + (BIT_CLEAR_ACKBAR_ACKPCHK_8821C(x) | BIT_ACKBAR_ACKPCHK_8821C(v)) + +#define BIT_RXBA_IGNOREA2_V1_8821C BIT(10) +#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8821C BIT(9) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8821C BIT(8) +#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8821C BIT(7) +#define BIT_DIS_TXBA_RXBARINFULL_V1_8821C BIT(6) +#define BIT_DIS_TXCFE_INFULL_V1_8821C BIT(5) +#define BIT_DIS_TXCTS_INFULL_V1_8821C BIT(4) +#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8821C BIT(3) +#define BIT_EN_TXACKBA_IN_TXOP_V1_8821C BIT(2) +#define BIT_EN_TXCTS_IN_RXNAV_V1_8821C BIT(1) +#define BIT_EN_TXCTS_INTXOP_V1_8821C BIT(0) /* 2 REG_CAMCMD_8821C (CAM COMMAND REGISTER) */ #define BIT_SECCAM_POLLING_8821C BIT(31) @@ -9146,28 +15054,45 @@ #define BIT_SHIFT_SECCAM_ADDR_V2_8821C 0 #define BIT_MASK_SECCAM_ADDR_V2_8821C 0x3ff -#define BIT_SECCAM_ADDR_V2_8821C(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8821C) << BIT_SHIFT_SECCAM_ADDR_V2_8821C) -#define BIT_GET_SECCAM_ADDR_V2_8821C(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8821C) & BIT_MASK_SECCAM_ADDR_V2_8821C) - - +#define BIT_SECCAM_ADDR_V2_8821C(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V2_8821C) \ + << BIT_SHIFT_SECCAM_ADDR_V2_8821C) +#define BITS_SECCAM_ADDR_V2_8821C \ + (BIT_MASK_SECCAM_ADDR_V2_8821C << BIT_SHIFT_SECCAM_ADDR_V2_8821C) +#define BIT_CLEAR_SECCAM_ADDR_V2_8821C(x) ((x) & (~BITS_SECCAM_ADDR_V2_8821C)) +#define BIT_GET_SECCAM_ADDR_V2_8821C(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8821C) & \ + BIT_MASK_SECCAM_ADDR_V2_8821C) +#define BIT_SET_SECCAM_ADDR_V2_8821C(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V2_8821C(x) | BIT_SECCAM_ADDR_V2_8821C(v)) /* 2 REG_CAMWRITE_8821C (CAM WRITE REGISTER) */ #define BIT_SHIFT_CAMW_DATA_8821C 0 #define BIT_MASK_CAMW_DATA_8821C 0xffffffffL -#define BIT_CAMW_DATA_8821C(x) (((x) & BIT_MASK_CAMW_DATA_8821C) << BIT_SHIFT_CAMW_DATA_8821C) -#define BIT_GET_CAMW_DATA_8821C(x) (((x) >> BIT_SHIFT_CAMW_DATA_8821C) & BIT_MASK_CAMW_DATA_8821C) - - +#define BIT_CAMW_DATA_8821C(x) \ + (((x) & BIT_MASK_CAMW_DATA_8821C) << BIT_SHIFT_CAMW_DATA_8821C) +#define BITS_CAMW_DATA_8821C \ + (BIT_MASK_CAMW_DATA_8821C << BIT_SHIFT_CAMW_DATA_8821C) +#define BIT_CLEAR_CAMW_DATA_8821C(x) ((x) & (~BITS_CAMW_DATA_8821C)) +#define BIT_GET_CAMW_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_CAMW_DATA_8821C) & BIT_MASK_CAMW_DATA_8821C) +#define BIT_SET_CAMW_DATA_8821C(x, v) \ + (BIT_CLEAR_CAMW_DATA_8821C(x) | BIT_CAMW_DATA_8821C(v)) /* 2 REG_CAMREAD_8821C (CAM READ REGISTER) */ #define BIT_SHIFT_CAMR_DATA_8821C 0 #define BIT_MASK_CAMR_DATA_8821C 0xffffffffL -#define BIT_CAMR_DATA_8821C(x) (((x) & BIT_MASK_CAMR_DATA_8821C) << BIT_SHIFT_CAMR_DATA_8821C) -#define BIT_GET_CAMR_DATA_8821C(x) (((x) >> BIT_SHIFT_CAMR_DATA_8821C) & BIT_MASK_CAMR_DATA_8821C) - - +#define BIT_CAMR_DATA_8821C(x) \ + (((x) & BIT_MASK_CAMR_DATA_8821C) << BIT_SHIFT_CAMR_DATA_8821C) +#define BITS_CAMR_DATA_8821C \ + (BIT_MASK_CAMR_DATA_8821C << BIT_SHIFT_CAMR_DATA_8821C) +#define BIT_CLEAR_CAMR_DATA_8821C(x) ((x) & (~BITS_CAMR_DATA_8821C)) +#define BIT_GET_CAMR_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_CAMR_DATA_8821C) & BIT_MASK_CAMR_DATA_8821C) +#define BIT_SET_CAMR_DATA_8821C(x, v) \ + (BIT_CLEAR_CAMR_DATA_8821C(x) | BIT_CAMR_DATA_8821C(v)) /* 2 REG_CAMDBG_8821C (CAM DEBUG REGISTER) */ #define BIT_SECCAM_INFO_8821C BIT(31) @@ -9175,43 +15100,53 @@ #define BIT_SHIFT_CAMDBG_SEC_TYPE_8821C 12 #define BIT_MASK_CAMDBG_SEC_TYPE_8821C 0x7 -#define BIT_CAMDBG_SEC_TYPE_8821C(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8821C) << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) -#define BIT_GET_CAMDBG_SEC_TYPE_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) & BIT_MASK_CAMDBG_SEC_TYPE_8821C) - +#define BIT_CAMDBG_SEC_TYPE_8821C(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8821C) \ + << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) +#define BITS_CAMDBG_SEC_TYPE_8821C \ + (BIT_MASK_CAMDBG_SEC_TYPE_8821C << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) +#define BIT_CLEAR_CAMDBG_SEC_TYPE_8821C(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8821C)) +#define BIT_GET_CAMDBG_SEC_TYPE_8821C(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) & \ + BIT_MASK_CAMDBG_SEC_TYPE_8821C) +#define BIT_SET_CAMDBG_SEC_TYPE_8821C(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE_8821C(x) | BIT_CAMDBG_SEC_TYPE_8821C(v)) #define BIT_CAMDBG_EXT_SECTYPE_8821C BIT(11) #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C 5 #define BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C 0x1f -#define BIT_CAMDBG_MIC_KEY_IDX_8821C(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) -#define BIT_GET_CAMDBG_MIC_KEY_IDX_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) - - +#define BIT_CAMDBG_MIC_KEY_IDX_8821C(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) +#define BITS_CAMDBG_MIC_KEY_IDX_8821C \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8821C(x) \ + ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8821C)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) & \ + BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_8821C(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8821C(x) | \ + BIT_CAMDBG_MIC_KEY_IDX_8821C(v)) #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C 0 #define BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C 0x1f -#define BIT_CAMDBG_SEC_KEY_IDX_8821C(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) -#define BIT_GET_CAMDBG_SEC_KEY_IDX_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) - - - -/* 2 REG_RXFILTER_ACTION_1_8821C */ - -#define BIT_SHIFT_RXFILTER_ACTION_1_8821C 0 -#define BIT_MASK_RXFILTER_ACTION_1_8821C 0xff -#define BIT_RXFILTER_ACTION_1_8821C(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8821C) << BIT_SHIFT_RXFILTER_ACTION_1_8821C) -#define BIT_GET_RXFILTER_ACTION_1_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8821C) & BIT_MASK_RXFILTER_ACTION_1_8821C) - - - -/* 2 REG_RXFILTER_CATEGORY_1_8821C */ - -#define BIT_SHIFT_RXFILTER_CATEGORY_1_8821C 0 -#define BIT_MASK_RXFILTER_CATEGORY_1_8821C 0xff -#define BIT_RXFILTER_CATEGORY_1_8821C(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8821C) << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) -#define BIT_GET_RXFILTER_CATEGORY_1_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) & BIT_MASK_RXFILTER_CATEGORY_1_8821C) - - +#define BIT_CAMDBG_SEC_KEY_IDX_8821C(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) +#define BITS_CAMDBG_SEC_KEY_IDX_8821C \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8821C(x) \ + ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8821C)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) & \ + BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_8821C(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8821C(x) | \ + BIT_CAMDBG_SEC_KEY_IDX_8821C(v)) /* 2 REG_SECCFG_8821C (SECURITY CONFIGURATION REGISTER) */ #define BIT_DIS_GCLK_WAPI_8821C BIT(15) @@ -9230,41 +15165,131 @@ #define BIT_RXUHUSEDK_8821C BIT(1) #define BIT_TXUHUSEDK_8821C BIT(0) -/* 2 REG_RXFILTER_ACTION_3_8821C */ - -#define BIT_SHIFT_RXFILTER_ACTION_3_8821C 0 -#define BIT_MASK_RXFILTER_ACTION_3_8821C 0xff -#define BIT_RXFILTER_ACTION_3_8821C(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8821C) << BIT_SHIFT_RXFILTER_ACTION_3_8821C) -#define BIT_GET_RXFILTER_ACTION_3_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8821C) & BIT_MASK_RXFILTER_ACTION_3_8821C) - +/* 2 REG_RXFILTER_CATEGORY_1_8821C */ +#define BIT_SHIFT_RXFILTER_CATEGORY_1_8821C 0 +#define BIT_MASK_RXFILTER_CATEGORY_1_8821C 0xff +#define BIT_RXFILTER_CATEGORY_1_8821C(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8821C) \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) +#define BITS_RXFILTER_CATEGORY_1_8821C \ + (BIT_MASK_RXFILTER_CATEGORY_1_8821C \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) +#define BIT_CLEAR_RXFILTER_CATEGORY_1_8821C(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_1_8821C)) +#define BIT_GET_RXFILTER_CATEGORY_1_8821C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) & \ + BIT_MASK_RXFILTER_CATEGORY_1_8821C) +#define BIT_SET_RXFILTER_CATEGORY_1_8821C(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_1_8821C(x) | \ + BIT_RXFILTER_CATEGORY_1_8821C(v)) -/* 2 REG_RXFILTER_CATEGORY_3_8821C */ +/* 2 REG_RXFILTER_ACTION_1_8821C */ -#define BIT_SHIFT_RXFILTER_CATEGORY_3_8821C 0 -#define BIT_MASK_RXFILTER_CATEGORY_3_8821C 0xff -#define BIT_RXFILTER_CATEGORY_3_8821C(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8821C) << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) -#define BIT_GET_RXFILTER_CATEGORY_3_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) & BIT_MASK_RXFILTER_CATEGORY_3_8821C) +#define BIT_SHIFT_RXFILTER_ACTION_1_8821C 0 +#define BIT_MASK_RXFILTER_ACTION_1_8821C 0xff +#define BIT_RXFILTER_ACTION_1_8821C(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_1_8821C) \ + << BIT_SHIFT_RXFILTER_ACTION_1_8821C) +#define BITS_RXFILTER_ACTION_1_8821C \ + (BIT_MASK_RXFILTER_ACTION_1_8821C << BIT_SHIFT_RXFILTER_ACTION_1_8821C) +#define BIT_CLEAR_RXFILTER_ACTION_1_8821C(x) \ + ((x) & (~BITS_RXFILTER_ACTION_1_8821C)) +#define BIT_GET_RXFILTER_ACTION_1_8821C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8821C) & \ + BIT_MASK_RXFILTER_ACTION_1_8821C) +#define BIT_SET_RXFILTER_ACTION_1_8821C(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_1_8821C(x) | BIT_RXFILTER_ACTION_1_8821C(v)) +/* 2 REG_RXFILTER_CATEGORY_2_8821C */ +#define BIT_SHIFT_RXFILTER_CATEGORY_2_8821C 0 +#define BIT_MASK_RXFILTER_CATEGORY_2_8821C 0xff +#define BIT_RXFILTER_CATEGORY_2_8821C(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8821C) \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) +#define BITS_RXFILTER_CATEGORY_2_8821C \ + (BIT_MASK_RXFILTER_CATEGORY_2_8821C \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) +#define BIT_CLEAR_RXFILTER_CATEGORY_2_8821C(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_2_8821C)) +#define BIT_GET_RXFILTER_CATEGORY_2_8821C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) & \ + BIT_MASK_RXFILTER_CATEGORY_2_8821C) +#define BIT_SET_RXFILTER_CATEGORY_2_8821C(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_2_8821C(x) | \ + BIT_RXFILTER_CATEGORY_2_8821C(v)) /* 2 REG_RXFILTER_ACTION_2_8821C */ #define BIT_SHIFT_RXFILTER_ACTION_2_8821C 0 #define BIT_MASK_RXFILTER_ACTION_2_8821C 0xff -#define BIT_RXFILTER_ACTION_2_8821C(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8821C) << BIT_SHIFT_RXFILTER_ACTION_2_8821C) -#define BIT_GET_RXFILTER_ACTION_2_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8821C) & BIT_MASK_RXFILTER_ACTION_2_8821C) - +#define BIT_RXFILTER_ACTION_2_8821C(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_2_8821C) \ + << BIT_SHIFT_RXFILTER_ACTION_2_8821C) +#define BITS_RXFILTER_ACTION_2_8821C \ + (BIT_MASK_RXFILTER_ACTION_2_8821C << BIT_SHIFT_RXFILTER_ACTION_2_8821C) +#define BIT_CLEAR_RXFILTER_ACTION_2_8821C(x) \ + ((x) & (~BITS_RXFILTER_ACTION_2_8821C)) +#define BIT_GET_RXFILTER_ACTION_2_8821C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8821C) & \ + BIT_MASK_RXFILTER_ACTION_2_8821C) +#define BIT_SET_RXFILTER_ACTION_2_8821C(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_2_8821C(x) | BIT_RXFILTER_ACTION_2_8821C(v)) +/* 2 REG_RXFILTER_CATEGORY_3_8821C */ -/* 2 REG_RXFILTER_CATEGORY_2_8821C */ +#define BIT_SHIFT_RXFILTER_CATEGORY_3_8821C 0 +#define BIT_MASK_RXFILTER_CATEGORY_3_8821C 0xff +#define BIT_RXFILTER_CATEGORY_3_8821C(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8821C) \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) +#define BITS_RXFILTER_CATEGORY_3_8821C \ + (BIT_MASK_RXFILTER_CATEGORY_3_8821C \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) +#define BIT_CLEAR_RXFILTER_CATEGORY_3_8821C(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_3_8821C)) +#define BIT_GET_RXFILTER_CATEGORY_3_8821C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) & \ + BIT_MASK_RXFILTER_CATEGORY_3_8821C) +#define BIT_SET_RXFILTER_CATEGORY_3_8821C(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_3_8821C(x) | \ + BIT_RXFILTER_CATEGORY_3_8821C(v)) -#define BIT_SHIFT_RXFILTER_CATEGORY_2_8821C 0 -#define BIT_MASK_RXFILTER_CATEGORY_2_8821C 0xff -#define BIT_RXFILTER_CATEGORY_2_8821C(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8821C) << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) -#define BIT_GET_RXFILTER_CATEGORY_2_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) & BIT_MASK_RXFILTER_CATEGORY_2_8821C) +/* 2 REG_RXFILTER_ACTION_3_8821C */ +#define BIT_SHIFT_RXFILTER_ACTION_3_8821C 0 +#define BIT_MASK_RXFILTER_ACTION_3_8821C 0xff +#define BIT_RXFILTER_ACTION_3_8821C(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_3_8821C) \ + << BIT_SHIFT_RXFILTER_ACTION_3_8821C) +#define BITS_RXFILTER_ACTION_3_8821C \ + (BIT_MASK_RXFILTER_ACTION_3_8821C << BIT_SHIFT_RXFILTER_ACTION_3_8821C) +#define BIT_CLEAR_RXFILTER_ACTION_3_8821C(x) \ + ((x) & (~BITS_RXFILTER_ACTION_3_8821C)) +#define BIT_GET_RXFILTER_ACTION_3_8821C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8821C) & \ + BIT_MASK_RXFILTER_ACTION_3_8821C) +#define BIT_SET_RXFILTER_ACTION_3_8821C(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_3_8821C(x) | BIT_RXFILTER_ACTION_3_8821C(v)) +/* 2 REG_RXFLTMAP3_8821C (RX FILTER MAP GROUP 3) */ +#define BIT_MGTFLT15EN_FW_8821C BIT(15) +#define BIT_MGTFLT14EN_FW_8821C BIT(14) +#define BIT_MGTFLT13EN_FW_8821C BIT(13) +#define BIT_MGTFLT12EN_FW_8821C BIT(12) +#define BIT_MGTFLT11EN_FW_8821C BIT(11) +#define BIT_MGTFLT10EN_FW_8821C BIT(10) +#define BIT_MGTFLT9EN_FW_8821C BIT(9) +#define BIT_MGTFLT8EN_FW_8821C BIT(8) +#define BIT_MGTFLT7EN_FW_8821C BIT(7) +#define BIT_MGTFLT6EN_FW_8821C BIT(6) +#define BIT_MGTFLT5EN_FW_8821C BIT(5) +#define BIT_MGTFLT4EN_FW_8821C BIT(4) +#define BIT_MGTFLT3EN_FW_8821C BIT(3) +#define BIT_MGTFLT2EN_FW_8821C BIT(2) +#define BIT_MGTFLT1EN_FW_8821C BIT(1) +#define BIT_MGTFLT0EN_FW_8821C BIT(0) /* 2 REG_RXFLTMAP4_8821C (RX FILTER MAP GROUP 4) */ #define BIT_CTRLFLT15EN_FW_8821C BIT(15) @@ -9284,25 +15309,25 @@ #define BIT_CTRLFLT1EN_FW_8821C BIT(1) #define BIT_CTRLFLT0EN_FW_8821C BIT(0) -/* 2 REG_RXFLTMAP3_8821C (RX FILTER MAP GROUP 3) */ -#define BIT_MGTFLT15EN_FW_8821C BIT(15) -#define BIT_MGTFLT14EN_FW_8821C BIT(14) -#define BIT_MGTFLT13EN_FW_8821C BIT(13) -#define BIT_MGTFLT12EN_FW_8821C BIT(12) -#define BIT_MGTFLT11EN_FW_8821C BIT(11) -#define BIT_MGTFLT10EN_FW_8821C BIT(10) -#define BIT_MGTFLT9EN_FW_8821C BIT(9) -#define BIT_MGTFLT8EN_FW_8821C BIT(8) -#define BIT_MGTFLT7EN_FW_8821C BIT(7) -#define BIT_MGTFLT6EN_FW_8821C BIT(6) -#define BIT_MGTFLT5EN_FW_8821C BIT(5) -#define BIT_MGTFLT4EN_FW_8821C BIT(4) -#define BIT_MGTFLT3EN_FW_8821C BIT(3) -#define BIT_MGTFLT2EN_FW_8821C BIT(2) -#define BIT_MGTFLT1EN_FW_8821C BIT(1) -#define BIT_MGTFLT0EN_FW_8821C BIT(0) +/* 2 REG_RXFLTMAP5_8821C (RX FILTER MAP GROUP 5) */ +#define BIT_DATAFLT15EN_FW_8821C BIT(15) +#define BIT_DATAFLT14EN_FW_8821C BIT(14) +#define BIT_DATAFLT13EN_FW_8821C BIT(13) +#define BIT_DATAFLT12EN_FW_8821C BIT(12) +#define BIT_DATAFLT11EN_FW_8821C BIT(11) +#define BIT_DATAFLT10EN_FW_8821C BIT(10) +#define BIT_DATAFLT9EN_FW_8821C BIT(9) +#define BIT_DATAFLT8EN_FW_8821C BIT(8) +#define BIT_DATAFLT7EN_FW_8821C BIT(7) +#define BIT_DATAFLT6EN_FW_8821C BIT(6) +#define BIT_DATAFLT5EN_FW_8821C BIT(5) +#define BIT_DATAFLT4EN_FW_8821C BIT(4) +#define BIT_DATAFLT3EN_FW_8821C BIT(3) +#define BIT_DATAFLT2EN_FW_8821C BIT(2) +#define BIT_DATAFLT1EN_FW_8821C BIT(1) +#define BIT_DATAFLT0EN_FW_8821C BIT(0) -/* 2 REG_RXFLTMAP6_8821C (RX FILTER MAP GROUP 3) */ +/* 2 REG_RXFLTMAP6_8821C (RX FILTER MAP GROUP 6) */ #define BIT_ACTIONFLT15EN_FW_8821C BIT(15) #define BIT_ACTIONFLT14EN_FW_8821C BIT(14) #define BIT_ACTIONFLT13EN_FW_8821C BIT(13) @@ -9320,41 +15345,53 @@ #define BIT_ACTIONFLT1EN_FW_8821C BIT(1) #define BIT_ACTIONFLT0EN_FW_8821C BIT(0) -/* 2 REG_RXFLTMAP5_8821C (RX FILTER MAP GROUP 3) */ -#define BIT_DATAFLT15EN_FW_8821C BIT(15) -#define BIT_DATAFLT14EN_FW_8821C BIT(14) -#define BIT_DATAFLT13EN_FW_8821C BIT(13) -#define BIT_DATAFLT12EN_FW_8821C BIT(12) -#define BIT_DATAFLT11EN_FW_8821C BIT(11) -#define BIT_DATAFLT10EN_FW_8821C BIT(10) -#define BIT_DATAFLT9EN_FW_8821C BIT(9) -#define BIT_DATAFLT8EN_FW_8821C BIT(8) -#define BIT_DATAFLT7EN_FW_8821C BIT(7) -#define BIT_DATAFLT6EN_FW_8821C BIT(6) -#define BIT_DATAFLT5EN_FW_8821C BIT(5) -#define BIT_DATAFLT4EN_FW_8821C BIT(4) -#define BIT_DATAFLT3EN_FW_8821C BIT(3) -#define BIT_DATAFLT2EN_FW_8821C BIT(2) -#define BIT_DATAFLT1EN_FW_8821C BIT(1) -#define BIT_DATAFLT0EN_FW_8821C BIT(0) +/* 2 REG_WOW_CTRL_8821C (WAKE ON WLAN CONTROL REGISTER) */ -/* 2 REG_WMMPS_UAPSD_TID_8821C (WMM POWER SAVE UAPSD TID REGISTER) */ -#define BIT_WMMPS_UAPSD_TID7_8821C BIT(7) -#define BIT_WMMPS_UAPSD_TID6_8821C BIT(6) -#define BIT_WMMPS_UAPSD_TID5_8821C BIT(5) -#define BIT_WMMPS_UAPSD_TID4_8821C BIT(4) -#define BIT_WMMPS_UAPSD_TID3_8821C BIT(3) -#define BIT_WMMPS_UAPSD_TID2_8821C BIT(2) -#define BIT_WMMPS_UAPSD_TID1_8821C BIT(1) -#define BIT_WMMPS_UAPSD_TID0_8821C BIT(0) +#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C 6 +#define BIT_MASK_PSF_BSSIDSEL_B2B1_8821C 0x3 +#define BIT_PSF_BSSIDSEL_B2B1_8821C(x) \ + (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) \ + << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) +#define BITS_PSF_BSSIDSEL_B2B1_8821C \ + (BIT_MASK_PSF_BSSIDSEL_B2B1_8821C << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8821C(x) \ + ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8821C)) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8821C(x) \ + (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) & \ + BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) +#define BIT_SET_PSF_BSSIDSEL_B2B1_8821C(x, v) \ + (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8821C(x) | BIT_PSF_BSSIDSEL_B2B1_8821C(v)) + +#define BIT_WOWHCI_8821C BIT(5) +#define BIT_PSF_BSSIDSEL_B0_8821C BIT(4) +#define BIT_UWF_8821C BIT(3) +#define BIT_MAGIC_8821C BIT(2) +#define BIT_WOWEN_8821C BIT(1) +#define BIT_FORCE_WAKEUP_8821C BIT(0) + +/* 2 REG_NAN_RX_TSF_FILTER_8821C(NAN_RX_TSF_ADDRESS_FILTER) */ +#define BIT_CHK_TSF_TA_8821C BIT(2) +#define BIT_CHK_TSF_CBSSID_8821C BIT(1) +#define BIT_CHK_TSF_EN_8821C BIT(0) /* 2 REG_PS_RX_INFO_8821C (POWER SAVE RX INFORMATION REGISTER) */ #define BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C 5 #define BIT_MASK_PORTSEL__PS_RX_INFO_8821C 0x7 -#define BIT_PORTSEL__PS_RX_INFO_8821C(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) -#define BIT_GET_PORTSEL__PS_RX_INFO_8821C(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C) - +#define BIT_PORTSEL__PS_RX_INFO_8821C(x) \ + (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C) \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) +#define BITS_PORTSEL__PS_RX_INFO_8821C \ + (BIT_MASK_PORTSEL__PS_RX_INFO_8821C \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8821C(x) \ + ((x) & (~BITS_PORTSEL__PS_RX_INFO_8821C)) +#define BIT_GET_PORTSEL__PS_RX_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) & \ + BIT_MASK_PORTSEL__PS_RX_INFO_8821C) +#define BIT_SET_PORTSEL__PS_RX_INFO_8821C(x, v) \ + (BIT_CLEAR_PORTSEL__PS_RX_INFO_8821C(x) | \ + BIT_PORTSEL__PS_RX_INFO_8821C(v)) #define BIT_RXCTRLIN0_8821C BIT(4) #define BIT_RXMGTIN0_8821C BIT(3) @@ -9362,42 +15399,42 @@ #define BIT_RXDATAIN1_8821C BIT(1) #define BIT_RXDATAIN0_8821C BIT(0) -/* 2 REG_NAN_RX_TSF_FILTER_8821C(NAN_RX_TSF_ADDRESS_FILTER) */ -#define BIT_CHK_TSF_TA_8821C BIT(2) -#define BIT_CHK_TSF_CBSSID_8821C BIT(1) -#define BIT_CHK_TSF_EN_8821C BIT(0) - -/* 2 REG_WOW_CTRL_8821C (WAKE ON WLAN CONTROL REGISTER) */ - -#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C 6 -#define BIT_MASK_PSF_BSSIDSEL_B2B1_8821C 0x3 -#define BIT_PSF_BSSIDSEL_B2B1_8821C(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) -#define BIT_GET_PSF_BSSIDSEL_B2B1_8821C(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) - - -#define BIT_WOWHCI_8821C BIT(5) -#define BIT_PSF_BSSIDSEL_B0_8821C BIT(4) -#define BIT_UWF_8821C BIT(3) -#define BIT_MAGIC_8821C BIT(2) -#define BIT_WOWEN_8821C BIT(1) -#define BIT_FORCE_WAKEUP_8821C BIT(0) +/* 2 REG_WMMPS_UAPSD_TID_8821C (WMM POWER SAVE UAPSD TID REGISTER) */ +#define BIT_WMMPS_UAPSD_TID7_8821C BIT(7) +#define BIT_WMMPS_UAPSD_TID6_8821C BIT(6) +#define BIT_WMMPS_UAPSD_TID5_8821C BIT(5) +#define BIT_WMMPS_UAPSD_TID4_8821C BIT(4) +#define BIT_WMMPS_UAPSD_TID3_8821C BIT(3) +#define BIT_WMMPS_UAPSD_TID2_8821C BIT(2) +#define BIT_WMMPS_UAPSD_TID1_8821C BIT(1) +#define BIT_WMMPS_UAPSD_TID0_8821C BIT(0) /* 2 REG_LPNAV_CTRL_8821C (LOW POWER NAV CONTROL REGISTER) */ #define BIT_LPNAV_EN_8821C BIT(31) #define BIT_SHIFT_LPNAV_EARLY_8821C 16 #define BIT_MASK_LPNAV_EARLY_8821C 0x7fff -#define BIT_LPNAV_EARLY_8821C(x) (((x) & BIT_MASK_LPNAV_EARLY_8821C) << BIT_SHIFT_LPNAV_EARLY_8821C) -#define BIT_GET_LPNAV_EARLY_8821C(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8821C) & BIT_MASK_LPNAV_EARLY_8821C) - - +#define BIT_LPNAV_EARLY_8821C(x) \ + (((x) & BIT_MASK_LPNAV_EARLY_8821C) << BIT_SHIFT_LPNAV_EARLY_8821C) +#define BITS_LPNAV_EARLY_8821C \ + (BIT_MASK_LPNAV_EARLY_8821C << BIT_SHIFT_LPNAV_EARLY_8821C) +#define BIT_CLEAR_LPNAV_EARLY_8821C(x) ((x) & (~BITS_LPNAV_EARLY_8821C)) +#define BIT_GET_LPNAV_EARLY_8821C(x) \ + (((x) >> BIT_SHIFT_LPNAV_EARLY_8821C) & BIT_MASK_LPNAV_EARLY_8821C) +#define BIT_SET_LPNAV_EARLY_8821C(x, v) \ + (BIT_CLEAR_LPNAV_EARLY_8821C(x) | BIT_LPNAV_EARLY_8821C(v)) #define BIT_SHIFT_LPNAV_TH_8821C 0 #define BIT_MASK_LPNAV_TH_8821C 0xffff -#define BIT_LPNAV_TH_8821C(x) (((x) & BIT_MASK_LPNAV_TH_8821C) << BIT_SHIFT_LPNAV_TH_8821C) -#define BIT_GET_LPNAV_TH_8821C(x) (((x) >> BIT_SHIFT_LPNAV_TH_8821C) & BIT_MASK_LPNAV_TH_8821C) - - +#define BIT_LPNAV_TH_8821C(x) \ + (((x) & BIT_MASK_LPNAV_TH_8821C) << BIT_SHIFT_LPNAV_TH_8821C) +#define BITS_LPNAV_TH_8821C \ + (BIT_MASK_LPNAV_TH_8821C << BIT_SHIFT_LPNAV_TH_8821C) +#define BIT_CLEAR_LPNAV_TH_8821C(x) ((x) & (~BITS_LPNAV_TH_8821C)) +#define BIT_GET_LPNAV_TH_8821C(x) \ + (((x) >> BIT_SHIFT_LPNAV_TH_8821C) & BIT_MASK_LPNAV_TH_8821C) +#define BIT_SET_LPNAV_TH_8821C(x, v) \ + (BIT_CLEAR_LPNAV_TH_8821C(x) | BIT_LPNAV_TH_8821C(v)) /* 2 REG_WKFMCAM_CMD_8821C (WAKEUP FRAME CAM COMMAND REGISTER) */ #define BIT_WKFCAM_POLLING_V1_8821C BIT(31) @@ -9406,44 +15443,46 @@ #define BIT_SHIFT_WKFCAM_ADDR_V2_8821C 8 #define BIT_MASK_WKFCAM_ADDR_V2_8821C 0xff -#define BIT_WKFCAM_ADDR_V2_8821C(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8821C) << BIT_SHIFT_WKFCAM_ADDR_V2_8821C) -#define BIT_GET_WKFCAM_ADDR_V2_8821C(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8821C) & BIT_MASK_WKFCAM_ADDR_V2_8821C) - - +#define BIT_WKFCAM_ADDR_V2_8821C(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR_V2_8821C) \ + << BIT_SHIFT_WKFCAM_ADDR_V2_8821C) +#define BITS_WKFCAM_ADDR_V2_8821C \ + (BIT_MASK_WKFCAM_ADDR_V2_8821C << BIT_SHIFT_WKFCAM_ADDR_V2_8821C) +#define BIT_CLEAR_WKFCAM_ADDR_V2_8821C(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8821C)) +#define BIT_GET_WKFCAM_ADDR_V2_8821C(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8821C) & \ + BIT_MASK_WKFCAM_ADDR_V2_8821C) +#define BIT_SET_WKFCAM_ADDR_V2_8821C(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR_V2_8821C(x) | BIT_WKFCAM_ADDR_V2_8821C(v)) #define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C 0 #define BIT_MASK_WKFCAM_CAM_NUM_V1_8821C 0xff -#define BIT_WKFCAM_CAM_NUM_V1_8821C(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) -#define BIT_GET_WKFCAM_CAM_NUM_V1_8821C(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) - - - -/* 2 REG_WKFMCAM_RWD_8821C (WAKEUP FRAME READ/WRITE DATA) */ - -#define BIT_SHIFT_WKFMCAM_RWD_8821C 0 -#define BIT_MASK_WKFMCAM_RWD_8821C 0xffffffffL -#define BIT_WKFMCAM_RWD_8821C(x) (((x) & BIT_MASK_WKFMCAM_RWD_8821C) << BIT_SHIFT_WKFMCAM_RWD_8821C) -#define BIT_GET_WKFMCAM_RWD_8821C(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8821C) & BIT_MASK_WKFMCAM_RWD_8821C) - - - -/* 2 REG_RXFLTMAP1_8821C (RX FILTER MAP GROUP 1) */ -#define BIT_CTRLFLT15EN_8821C BIT(15) -#define BIT_CTRLFLT14EN_8821C BIT(14) -#define BIT_CTRLFLT13EN_8821C BIT(13) -#define BIT_CTRLFLT12EN_8821C BIT(12) -#define BIT_CTRLFLT11EN_8821C BIT(11) -#define BIT_CTRLFLT10EN_8821C BIT(10) -#define BIT_CTRLFLT9EN_8821C BIT(9) -#define BIT_CTRLFLT8EN_8821C BIT(8) -#define BIT_CTRLFLT7EN_8821C BIT(7) -#define BIT_CTRLFLT6EN_8821C BIT(6) -#define BIT_CTRLFLT5EN_8821C BIT(5) -#define BIT_CTRLFLT4EN_8821C BIT(4) -#define BIT_CTRLFLT3EN_8821C BIT(3) -#define BIT_CTRLFLT2EN_8821C BIT(2) -#define BIT_CTRLFLT1EN_8821C BIT(1) -#define BIT_CTRLFLT0EN_8821C BIT(0) +#define BIT_WKFCAM_CAM_NUM_V1_8821C(x) \ + (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) \ + << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) +#define BITS_WKFCAM_CAM_NUM_V1_8821C \ + (BIT_MASK_WKFCAM_CAM_NUM_V1_8821C << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8821C(x) \ + ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8821C)) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8821C(x) \ + (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) & \ + BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) +#define BIT_SET_WKFCAM_CAM_NUM_V1_8821C(x, v) \ + (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8821C(x) | BIT_WKFCAM_CAM_NUM_V1_8821C(v)) + +/* 2 REG_WKFMCAM_RWD_8821C (WAKEUP FRAME READ/WRITE DATA) */ + +#define BIT_SHIFT_WKFMCAM_RWD_8821C 0 +#define BIT_MASK_WKFMCAM_RWD_8821C 0xffffffffL +#define BIT_WKFMCAM_RWD_8821C(x) \ + (((x) & BIT_MASK_WKFMCAM_RWD_8821C) << BIT_SHIFT_WKFMCAM_RWD_8821C) +#define BITS_WKFMCAM_RWD_8821C \ + (BIT_MASK_WKFMCAM_RWD_8821C << BIT_SHIFT_WKFMCAM_RWD_8821C) +#define BIT_CLEAR_WKFMCAM_RWD_8821C(x) ((x) & (~BITS_WKFMCAM_RWD_8821C)) +#define BIT_GET_WKFMCAM_RWD_8821C(x) \ + (((x) >> BIT_SHIFT_WKFMCAM_RWD_8821C) & BIT_MASK_WKFMCAM_RWD_8821C) +#define BIT_SET_WKFMCAM_RWD_8821C(x, v) \ + (BIT_CLEAR_WKFMCAM_RWD_8821C(x) | BIT_WKFMCAM_RWD_8821C(v)) /* 2 REG_RXFLTMAP0_8821C (RX FILTER MAP GROUP 0) */ #define BIT_MGTFLT15EN_8821C BIT(15) @@ -9463,9 +15502,25 @@ #define BIT_MGTFLT1EN_8821C BIT(1) #define BIT_MGTFLT0EN_8821C BIT(0) -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_RXFLTMAP1_8821C (RX FILTER MAP GROUP 1) */ +#define BIT_CTRLFLT15EN_8821C BIT(15) +#define BIT_CTRLFLT14EN_8821C BIT(14) +#define BIT_CTRLFLT13EN_8821C BIT(13) +#define BIT_CTRLFLT12EN_8821C BIT(12) +#define BIT_CTRLFLT11EN_8821C BIT(11) +#define BIT_CTRLFLT10EN_8821C BIT(10) +#define BIT_CTRLFLT9EN_8821C BIT(9) +#define BIT_CTRLFLT8EN_8821C BIT(8) +#define BIT_CTRLFLT7EN_8821C BIT(7) +#define BIT_CTRLFLT6EN_8821C BIT(6) +#define BIT_CTRLFLT5EN_8821C BIT(5) +#define BIT_CTRLFLT4EN_8821C BIT(4) +#define BIT_CTRLFLT3EN_8821C BIT(3) +#define BIT_CTRLFLT2EN_8821C BIT(2) +#define BIT_CTRLFLT1EN_8821C BIT(1) +#define BIT_CTRLFLT0EN_8821C BIT(0) -/* 2 REG_RXFLTMAP_8821C (RX FILTER MAP GROUP 2) */ +/* 2 REG_RXFLTMAP2_8821C (RX FILTER MAP GROUP 2) */ #define BIT_DATAFLT15EN_8821C BIT(15) #define BIT_DATAFLT14EN_8821C BIT(14) #define BIT_DATAFLT13EN_8821C BIT(13) @@ -9483,93 +15538,146 @@ #define BIT_DATAFLT1EN_8821C BIT(1) #define BIT_DATAFLT0EN_8821C BIT(0) +/* 2 REG_RSVD_8821C */ + /* 2 REG_BCN_PSR_RPT_8821C (BEACON PARSER REPORT REGISTER) */ #define BIT_SHIFT_DTIM_CNT_8821C 24 #define BIT_MASK_DTIM_CNT_8821C 0xff -#define BIT_DTIM_CNT_8821C(x) (((x) & BIT_MASK_DTIM_CNT_8821C) << BIT_SHIFT_DTIM_CNT_8821C) -#define BIT_GET_DTIM_CNT_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT_8821C) & BIT_MASK_DTIM_CNT_8821C) - - +#define BIT_DTIM_CNT_8821C(x) \ + (((x) & BIT_MASK_DTIM_CNT_8821C) << BIT_SHIFT_DTIM_CNT_8821C) +#define BITS_DTIM_CNT_8821C \ + (BIT_MASK_DTIM_CNT_8821C << BIT_SHIFT_DTIM_CNT_8821C) +#define BIT_CLEAR_DTIM_CNT_8821C(x) ((x) & (~BITS_DTIM_CNT_8821C)) +#define BIT_GET_DTIM_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT_8821C) & BIT_MASK_DTIM_CNT_8821C) +#define BIT_SET_DTIM_CNT_8821C(x, v) \ + (BIT_CLEAR_DTIM_CNT_8821C(x) | BIT_DTIM_CNT_8821C(v)) #define BIT_SHIFT_DTIM_PERIOD_8821C 16 #define BIT_MASK_DTIM_PERIOD_8821C 0xff -#define BIT_DTIM_PERIOD_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD_8821C) << BIT_SHIFT_DTIM_PERIOD_8821C) -#define BIT_GET_DTIM_PERIOD_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8821C) & BIT_MASK_DTIM_PERIOD_8821C) - +#define BIT_DTIM_PERIOD_8821C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD_8821C) << BIT_SHIFT_DTIM_PERIOD_8821C) +#define BITS_DTIM_PERIOD_8821C \ + (BIT_MASK_DTIM_PERIOD_8821C << BIT_SHIFT_DTIM_PERIOD_8821C) +#define BIT_CLEAR_DTIM_PERIOD_8821C(x) ((x) & (~BITS_DTIM_PERIOD_8821C)) +#define BIT_GET_DTIM_PERIOD_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD_8821C) & BIT_MASK_DTIM_PERIOD_8821C) +#define BIT_SET_DTIM_PERIOD_8821C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD_8821C(x) | BIT_DTIM_PERIOD_8821C(v)) #define BIT_DTIM_8821C BIT(15) #define BIT_TIM_8821C BIT(14) +#define BIT_RPT_VALID_8821C BIT(13) #define BIT_SHIFT_PS_AID_0_8821C 0 #define BIT_MASK_PS_AID_0_8821C 0x7ff -#define BIT_PS_AID_0_8821C(x) (((x) & BIT_MASK_PS_AID_0_8821C) << BIT_SHIFT_PS_AID_0_8821C) -#define BIT_GET_PS_AID_0_8821C(x) (((x) >> BIT_SHIFT_PS_AID_0_8821C) & BIT_MASK_PS_AID_0_8821C) +#define BIT_PS_AID_0_8821C(x) \ + (((x) & BIT_MASK_PS_AID_0_8821C) << BIT_SHIFT_PS_AID_0_8821C) +#define BITS_PS_AID_0_8821C \ + (BIT_MASK_PS_AID_0_8821C << BIT_SHIFT_PS_AID_0_8821C) +#define BIT_CLEAR_PS_AID_0_8821C(x) ((x) & (~BITS_PS_AID_0_8821C)) +#define BIT_GET_PS_AID_0_8821C(x) \ + (((x) >> BIT_SHIFT_PS_AID_0_8821C) & BIT_MASK_PS_AID_0_8821C) +#define BIT_SET_PS_AID_0_8821C(x, v) \ + (BIT_CLEAR_PS_AID_0_8821C(x) | BIT_PS_AID_0_8821C(v)) +/* 2 REG_FLC_RPC_8821C (FW LPS CONDITION -- RX PKT COUNTER) */ +#define BIT_SHIFT_FLC_RPC_8821C 0 +#define BIT_MASK_FLC_RPC_8821C 0xff +#define BIT_FLC_RPC_8821C(x) \ + (((x) & BIT_MASK_FLC_RPC_8821C) << BIT_SHIFT_FLC_RPC_8821C) +#define BITS_FLC_RPC_8821C (BIT_MASK_FLC_RPC_8821C << BIT_SHIFT_FLC_RPC_8821C) +#define BIT_CLEAR_FLC_RPC_8821C(x) ((x) & (~BITS_FLC_RPC_8821C)) +#define BIT_GET_FLC_RPC_8821C(x) \ + (((x) >> BIT_SHIFT_FLC_RPC_8821C) & BIT_MASK_FLC_RPC_8821C) +#define BIT_SET_FLC_RPC_8821C(x, v) \ + (BIT_CLEAR_FLC_RPC_8821C(x) | BIT_FLC_RPC_8821C(v)) -/* 2 REG_FLC_TRPC_8821C (TIMER OF FLC_RPC) */ -#define BIT_FLC_RPCT_V1_8821C BIT(7) -#define BIT_MODE_8821C BIT(6) - -#define BIT_SHIFT_TRPCD_8821C 0 -#define BIT_MASK_TRPCD_8821C 0x3f -#define BIT_TRPCD_8821C(x) (((x) & BIT_MASK_TRPCD_8821C) << BIT_SHIFT_TRPCD_8821C) -#define BIT_GET_TRPCD_8821C(x) (((x) >> BIT_SHIFT_TRPCD_8821C) & BIT_MASK_TRPCD_8821C) - +/* 2 REG_FLC_RPCT_8821C (FLC_RPC THRESHOLD) */ +#define BIT_SHIFT_FLC_RPCT_8821C 0 +#define BIT_MASK_FLC_RPCT_8821C 0xff +#define BIT_FLC_RPCT_8821C(x) \ + (((x) & BIT_MASK_FLC_RPCT_8821C) << BIT_SHIFT_FLC_RPCT_8821C) +#define BITS_FLC_RPCT_8821C \ + (BIT_MASK_FLC_RPCT_8821C << BIT_SHIFT_FLC_RPCT_8821C) +#define BIT_CLEAR_FLC_RPCT_8821C(x) ((x) & (~BITS_FLC_RPCT_8821C)) +#define BIT_GET_FLC_RPCT_8821C(x) \ + (((x) >> BIT_SHIFT_FLC_RPCT_8821C) & BIT_MASK_FLC_RPCT_8821C) +#define BIT_SET_FLC_RPCT_8821C(x, v) \ + (BIT_CLEAR_FLC_RPCT_8821C(x) | BIT_FLC_RPCT_8821C(v)) /* 2 REG_FLC_PTS_8821C (PKT TYPE SELECTION OF FLC_RPC T) */ #define BIT_CMF_8821C BIT(2) #define BIT_CCF_8821C BIT(1) #define BIT_CDF_8821C BIT(0) -/* 2 REG_FLC_RPCT_8821C (FLC_RPC THRESHOLD) */ - -#define BIT_SHIFT_FLC_RPCT_8821C 0 -#define BIT_MASK_FLC_RPCT_8821C 0xff -#define BIT_FLC_RPCT_8821C(x) (((x) & BIT_MASK_FLC_RPCT_8821C) << BIT_SHIFT_FLC_RPCT_8821C) -#define BIT_GET_FLC_RPCT_8821C(x) (((x) >> BIT_SHIFT_FLC_RPCT_8821C) & BIT_MASK_FLC_RPCT_8821C) - - - -/* 2 REG_FLC_RPC_8821C (FW LPS CONDITION -- RX PKT COUNTER) */ - -#define BIT_SHIFT_FLC_RPC_8821C 0 -#define BIT_MASK_FLC_RPC_8821C 0xff -#define BIT_FLC_RPC_8821C(x) (((x) & BIT_MASK_FLC_RPC_8821C) << BIT_SHIFT_FLC_RPC_8821C) -#define BIT_GET_FLC_RPC_8821C(x) (((x) >> BIT_SHIFT_FLC_RPC_8821C) & BIT_MASK_FLC_RPC_8821C) - +/* 2 REG_FLC_TRPC_8821C (TIMER OF FLC_RPC) */ +#define BIT_FLC_RPCT_V1_8821C BIT(7) +#define BIT_MODE_8821C BIT(6) +#define BIT_SHIFT_TRPCD_8821C 0 +#define BIT_MASK_TRPCD_8821C 0x3f +#define BIT_TRPCD_8821C(x) \ + (((x) & BIT_MASK_TRPCD_8821C) << BIT_SHIFT_TRPCD_8821C) +#define BITS_TRPCD_8821C (BIT_MASK_TRPCD_8821C << BIT_SHIFT_TRPCD_8821C) +#define BIT_CLEAR_TRPCD_8821C(x) ((x) & (~BITS_TRPCD_8821C)) +#define BIT_GET_TRPCD_8821C(x) \ + (((x) >> BIT_SHIFT_TRPCD_8821C) & BIT_MASK_TRPCD_8821C) +#define BIT_SET_TRPCD_8821C(x, v) \ + (BIT_CLEAR_TRPCD_8821C(x) | BIT_TRPCD_8821C(v)) /* 2 REG_RXPKTMON_CTRL_8821C */ #define BIT_SHIFT_RXBKQPKT_SEQ_8821C 20 #define BIT_MASK_RXBKQPKT_SEQ_8821C 0xf -#define BIT_RXBKQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8821C) << BIT_SHIFT_RXBKQPKT_SEQ_8821C) -#define BIT_GET_RXBKQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8821C) & BIT_MASK_RXBKQPKT_SEQ_8821C) - - +#define BIT_RXBKQPKT_SEQ_8821C(x) \ + (((x) & BIT_MASK_RXBKQPKT_SEQ_8821C) << BIT_SHIFT_RXBKQPKT_SEQ_8821C) +#define BITS_RXBKQPKT_SEQ_8821C \ + (BIT_MASK_RXBKQPKT_SEQ_8821C << BIT_SHIFT_RXBKQPKT_SEQ_8821C) +#define BIT_CLEAR_RXBKQPKT_SEQ_8821C(x) ((x) & (~BITS_RXBKQPKT_SEQ_8821C)) +#define BIT_GET_RXBKQPKT_SEQ_8821C(x) \ + (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8821C) & BIT_MASK_RXBKQPKT_SEQ_8821C) +#define BIT_SET_RXBKQPKT_SEQ_8821C(x, v) \ + (BIT_CLEAR_RXBKQPKT_SEQ_8821C(x) | BIT_RXBKQPKT_SEQ_8821C(v)) #define BIT_SHIFT_RXBEQPKT_SEQ_8821C 16 #define BIT_MASK_RXBEQPKT_SEQ_8821C 0xf -#define BIT_RXBEQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8821C) << BIT_SHIFT_RXBEQPKT_SEQ_8821C) -#define BIT_GET_RXBEQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8821C) & BIT_MASK_RXBEQPKT_SEQ_8821C) - - +#define BIT_RXBEQPKT_SEQ_8821C(x) \ + (((x) & BIT_MASK_RXBEQPKT_SEQ_8821C) << BIT_SHIFT_RXBEQPKT_SEQ_8821C) +#define BITS_RXBEQPKT_SEQ_8821C \ + (BIT_MASK_RXBEQPKT_SEQ_8821C << BIT_SHIFT_RXBEQPKT_SEQ_8821C) +#define BIT_CLEAR_RXBEQPKT_SEQ_8821C(x) ((x) & (~BITS_RXBEQPKT_SEQ_8821C)) +#define BIT_GET_RXBEQPKT_SEQ_8821C(x) \ + (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8821C) & BIT_MASK_RXBEQPKT_SEQ_8821C) +#define BIT_SET_RXBEQPKT_SEQ_8821C(x, v) \ + (BIT_CLEAR_RXBEQPKT_SEQ_8821C(x) | BIT_RXBEQPKT_SEQ_8821C(v)) #define BIT_SHIFT_RXVIQPKT_SEQ_8821C 12 #define BIT_MASK_RXVIQPKT_SEQ_8821C 0xf -#define BIT_RXVIQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8821C) << BIT_SHIFT_RXVIQPKT_SEQ_8821C) -#define BIT_GET_RXVIQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8821C) & BIT_MASK_RXVIQPKT_SEQ_8821C) - - +#define BIT_RXVIQPKT_SEQ_8821C(x) \ + (((x) & BIT_MASK_RXVIQPKT_SEQ_8821C) << BIT_SHIFT_RXVIQPKT_SEQ_8821C) +#define BITS_RXVIQPKT_SEQ_8821C \ + (BIT_MASK_RXVIQPKT_SEQ_8821C << BIT_SHIFT_RXVIQPKT_SEQ_8821C) +#define BIT_CLEAR_RXVIQPKT_SEQ_8821C(x) ((x) & (~BITS_RXVIQPKT_SEQ_8821C)) +#define BIT_GET_RXVIQPKT_SEQ_8821C(x) \ + (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8821C) & BIT_MASK_RXVIQPKT_SEQ_8821C) +#define BIT_SET_RXVIQPKT_SEQ_8821C(x, v) \ + (BIT_CLEAR_RXVIQPKT_SEQ_8821C(x) | BIT_RXVIQPKT_SEQ_8821C(v)) #define BIT_SHIFT_RXVOQPKT_SEQ_8821C 8 #define BIT_MASK_RXVOQPKT_SEQ_8821C 0xf -#define BIT_RXVOQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8821C) << BIT_SHIFT_RXVOQPKT_SEQ_8821C) -#define BIT_GET_RXVOQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8821C) & BIT_MASK_RXVOQPKT_SEQ_8821C) - +#define BIT_RXVOQPKT_SEQ_8821C(x) \ + (((x) & BIT_MASK_RXVOQPKT_SEQ_8821C) << BIT_SHIFT_RXVOQPKT_SEQ_8821C) +#define BITS_RXVOQPKT_SEQ_8821C \ + (BIT_MASK_RXVOQPKT_SEQ_8821C << BIT_SHIFT_RXVOQPKT_SEQ_8821C) +#define BIT_CLEAR_RXVOQPKT_SEQ_8821C(x) ((x) & (~BITS_RXVOQPKT_SEQ_8821C)) +#define BIT_GET_RXVOQPKT_SEQ_8821C(x) \ + (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8821C) & BIT_MASK_RXVOQPKT_SEQ_8821C) +#define BIT_SET_RXVOQPKT_SEQ_8821C(x, v) \ + (BIT_CLEAR_RXVOQPKT_SEQ_8821C(x) | BIT_RXVOQPKT_SEQ_8821C(v)) #define BIT_RXBKQPKT_ERR_8821C BIT(7) #define BIT_RXBEQPKT_ERR_8821C BIT(6) @@ -9583,25 +15691,41 @@ #define BIT_SHIFT_STATE_SEL_8821C 24 #define BIT_MASK_STATE_SEL_8821C 0x1f -#define BIT_STATE_SEL_8821C(x) (((x) & BIT_MASK_STATE_SEL_8821C) << BIT_SHIFT_STATE_SEL_8821C) -#define BIT_GET_STATE_SEL_8821C(x) (((x) >> BIT_SHIFT_STATE_SEL_8821C) & BIT_MASK_STATE_SEL_8821C) - - +#define BIT_STATE_SEL_8821C(x) \ + (((x) & BIT_MASK_STATE_SEL_8821C) << BIT_SHIFT_STATE_SEL_8821C) +#define BITS_STATE_SEL_8821C \ + (BIT_MASK_STATE_SEL_8821C << BIT_SHIFT_STATE_SEL_8821C) +#define BIT_CLEAR_STATE_SEL_8821C(x) ((x) & (~BITS_STATE_SEL_8821C)) +#define BIT_GET_STATE_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_STATE_SEL_8821C) & BIT_MASK_STATE_SEL_8821C) +#define BIT_SET_STATE_SEL_8821C(x, v) \ + (BIT_CLEAR_STATE_SEL_8821C(x) | BIT_STATE_SEL_8821C(v)) #define BIT_SHIFT_STATE_INFO_8821C 8 #define BIT_MASK_STATE_INFO_8821C 0xff -#define BIT_STATE_INFO_8821C(x) (((x) & BIT_MASK_STATE_INFO_8821C) << BIT_SHIFT_STATE_INFO_8821C) -#define BIT_GET_STATE_INFO_8821C(x) (((x) >> BIT_SHIFT_STATE_INFO_8821C) & BIT_MASK_STATE_INFO_8821C) - +#define BIT_STATE_INFO_8821C(x) \ + (((x) & BIT_MASK_STATE_INFO_8821C) << BIT_SHIFT_STATE_INFO_8821C) +#define BITS_STATE_INFO_8821C \ + (BIT_MASK_STATE_INFO_8821C << BIT_SHIFT_STATE_INFO_8821C) +#define BIT_CLEAR_STATE_INFO_8821C(x) ((x) & (~BITS_STATE_INFO_8821C)) +#define BIT_GET_STATE_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_STATE_INFO_8821C) & BIT_MASK_STATE_INFO_8821C) +#define BIT_SET_STATE_INFO_8821C(x, v) \ + (BIT_CLEAR_STATE_INFO_8821C(x) | BIT_STATE_INFO_8821C(v)) #define BIT_UPD_NXT_STATE_8821C BIT(7) #define BIT_SHIFT_CUR_STATE_8821C 0 #define BIT_MASK_CUR_STATE_8821C 0x7f -#define BIT_CUR_STATE_8821C(x) (((x) & BIT_MASK_CUR_STATE_8821C) << BIT_SHIFT_CUR_STATE_8821C) -#define BIT_GET_CUR_STATE_8821C(x) (((x) >> BIT_SHIFT_CUR_STATE_8821C) & BIT_MASK_CUR_STATE_8821C) - - +#define BIT_CUR_STATE_8821C(x) \ + (((x) & BIT_MASK_CUR_STATE_8821C) << BIT_SHIFT_CUR_STATE_8821C) +#define BITS_CUR_STATE_8821C \ + (BIT_MASK_CUR_STATE_8821C << BIT_SHIFT_CUR_STATE_8821C) +#define BIT_CLEAR_CUR_STATE_8821C(x) ((x) & (~BITS_CUR_STATE_8821C)) +#define BIT_GET_CUR_STATE_8821C(x) \ + (((x) >> BIT_SHIFT_CUR_STATE_8821C) & BIT_MASK_CUR_STATE_8821C) +#define BIT_SET_CUR_STATE_8821C(x, v) \ + (BIT_CLEAR_CUR_STATE_8821C(x) | BIT_CUR_STATE_8821C(v)) /* 2 REG_ERROR_MON_8821C */ #define BIT_MACRX_ERR_1_8821C BIT(17) @@ -9616,9 +15740,18 @@ #define BIT_SHIFT_INFO_INDEX_OFFSET_8821C 16 #define BIT_MASK_INFO_INDEX_OFFSET_8821C 0x1fff -#define BIT_INFO_INDEX_OFFSET_8821C(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8821C) << BIT_SHIFT_INFO_INDEX_OFFSET_8821C) -#define BIT_GET_INFO_INDEX_OFFSET_8821C(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8821C) & BIT_MASK_INFO_INDEX_OFFSET_8821C) - +#define BIT_INFO_INDEX_OFFSET_8821C(x) \ + (((x) & BIT_MASK_INFO_INDEX_OFFSET_8821C) \ + << BIT_SHIFT_INFO_INDEX_OFFSET_8821C) +#define BITS_INFO_INDEX_OFFSET_8821C \ + (BIT_MASK_INFO_INDEX_OFFSET_8821C << BIT_SHIFT_INFO_INDEX_OFFSET_8821C) +#define BIT_CLEAR_INFO_INDEX_OFFSET_8821C(x) \ + ((x) & (~BITS_INFO_INDEX_OFFSET_8821C)) +#define BIT_GET_INFO_INDEX_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8821C) & \ + BIT_MASK_INFO_INDEX_OFFSET_8821C) +#define BIT_SET_INFO_INDEX_OFFSET_8821C(x, v) \ + (BIT_CLEAR_INFO_INDEX_OFFSET_8821C(x) | BIT_INFO_INDEX_OFFSET_8821C(v)) #define BIT_WMAC_SRCH_FIFOFULL_8821C BIT(15) #define BIT_DIS_INFOSRCH_8821C BIT(14) @@ -9626,134 +15759,262 @@ #define BIT_SHIFT_INFO_ADDR_OFFSET_8821C 0 #define BIT_MASK_INFO_ADDR_OFFSET_8821C 0x1fff -#define BIT_INFO_ADDR_OFFSET_8821C(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8821C) << BIT_SHIFT_INFO_ADDR_OFFSET_8821C) -#define BIT_GET_INFO_ADDR_OFFSET_8821C(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8821C) & BIT_MASK_INFO_ADDR_OFFSET_8821C) - - +#define BIT_INFO_ADDR_OFFSET_8821C(x) \ + (((x) & BIT_MASK_INFO_ADDR_OFFSET_8821C) \ + << BIT_SHIFT_INFO_ADDR_OFFSET_8821C) +#define BITS_INFO_ADDR_OFFSET_8821C \ + (BIT_MASK_INFO_ADDR_OFFSET_8821C << BIT_SHIFT_INFO_ADDR_OFFSET_8821C) +#define BIT_CLEAR_INFO_ADDR_OFFSET_8821C(x) \ + ((x) & (~BITS_INFO_ADDR_OFFSET_8821C)) +#define BIT_GET_INFO_ADDR_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8821C) & \ + BIT_MASK_INFO_ADDR_OFFSET_8821C) +#define BIT_SET_INFO_ADDR_OFFSET_8821C(x, v) \ + (BIT_CLEAR_INFO_ADDR_OFFSET_8821C(x) | BIT_INFO_ADDR_OFFSET_8821C(v)) /* 2 REG_BT_COEX_TABLE_8821C (BT-COEXISTENCE CONTROL REGISTER) */ -#define BIT_PRI_MASK_RX_RESP_8821C BIT(126) -#define BIT_PRI_MASK_RXOFDM_8821C BIT(125) -#define BIT_PRI_MASK_RXCCK_8821C BIT(124) -#define BIT_SHIFT_PRI_MASK_TXAC_8821C (117 & CPU_OPT_WIDTH) +#define BIT_SHIFT_COEX_TABLE_1_8821C 0 +#define BIT_MASK_COEX_TABLE_1_8821C 0xffffffffL +#define BIT_COEX_TABLE_1_8821C(x) \ + (((x) & BIT_MASK_COEX_TABLE_1_8821C) << BIT_SHIFT_COEX_TABLE_1_8821C) +#define BITS_COEX_TABLE_1_8821C \ + (BIT_MASK_COEX_TABLE_1_8821C << BIT_SHIFT_COEX_TABLE_1_8821C) +#define BIT_CLEAR_COEX_TABLE_1_8821C(x) ((x) & (~BITS_COEX_TABLE_1_8821C)) +#define BIT_GET_COEX_TABLE_1_8821C(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_1_8821C) & BIT_MASK_COEX_TABLE_1_8821C) +#define BIT_SET_COEX_TABLE_1_8821C(x, v) \ + (BIT_CLEAR_COEX_TABLE_1_8821C(x) | BIT_COEX_TABLE_1_8821C(v)) + +/* 2 REG_BT_COEX_TABLE2_8821C (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_COEX_TABLE_2_8821C 0 +#define BIT_MASK_COEX_TABLE_2_8821C 0xffffffffL +#define BIT_COEX_TABLE_2_8821C(x) \ + (((x) & BIT_MASK_COEX_TABLE_2_8821C) << BIT_SHIFT_COEX_TABLE_2_8821C) +#define BITS_COEX_TABLE_2_8821C \ + (BIT_MASK_COEX_TABLE_2_8821C << BIT_SHIFT_COEX_TABLE_2_8821C) +#define BIT_CLEAR_COEX_TABLE_2_8821C(x) ((x) & (~BITS_COEX_TABLE_2_8821C)) +#define BIT_GET_COEX_TABLE_2_8821C(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_2_8821C) & BIT_MASK_COEX_TABLE_2_8821C) +#define BIT_SET_COEX_TABLE_2_8821C(x, v) \ + (BIT_CLEAR_COEX_TABLE_2_8821C(x) | BIT_COEX_TABLE_2_8821C(v)) + +/* 2 REG_BT_COEX_BREAK_TABLE_8821C (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_BREAK_TABLE_2_8821C 16 +#define BIT_MASK_BREAK_TABLE_2_8821C 0xffff +#define BIT_BREAK_TABLE_2_8821C(x) \ + (((x) & BIT_MASK_BREAK_TABLE_2_8821C) << BIT_SHIFT_BREAK_TABLE_2_8821C) +#define BITS_BREAK_TABLE_2_8821C \ + (BIT_MASK_BREAK_TABLE_2_8821C << BIT_SHIFT_BREAK_TABLE_2_8821C) +#define BIT_CLEAR_BREAK_TABLE_2_8821C(x) ((x) & (~BITS_BREAK_TABLE_2_8821C)) +#define BIT_GET_BREAK_TABLE_2_8821C(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_2_8821C) & BIT_MASK_BREAK_TABLE_2_8821C) +#define BIT_SET_BREAK_TABLE_2_8821C(x, v) \ + (BIT_CLEAR_BREAK_TABLE_2_8821C(x) | BIT_BREAK_TABLE_2_8821C(v)) + +#define BIT_SHIFT_BREAK_TABLE_1_8821C 0 +#define BIT_MASK_BREAK_TABLE_1_8821C 0xffff +#define BIT_BREAK_TABLE_1_8821C(x) \ + (((x) & BIT_MASK_BREAK_TABLE_1_8821C) << BIT_SHIFT_BREAK_TABLE_1_8821C) +#define BITS_BREAK_TABLE_1_8821C \ + (BIT_MASK_BREAK_TABLE_1_8821C << BIT_SHIFT_BREAK_TABLE_1_8821C) +#define BIT_CLEAR_BREAK_TABLE_1_8821C(x) ((x) & (~BITS_BREAK_TABLE_1_8821C)) +#define BIT_GET_BREAK_TABLE_1_8821C(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_1_8821C) & BIT_MASK_BREAK_TABLE_1_8821C) +#define BIT_SET_BREAK_TABLE_1_8821C(x, v) \ + (BIT_CLEAR_BREAK_TABLE_1_8821C(x) | BIT_BREAK_TABLE_1_8821C(v)) + +/* 2 REG_BT_COEX_TABLE_H_8821C (BT-COEXISTENCE CONTROL REGISTER) */ +#define BIT_PRI_MASK_RX_RESP_V1_8821C BIT(30) +#define BIT_PRI_MASK_RXOFDM_V1_8821C BIT(29) +#define BIT_PRI_MASK_RXCCK_V1_8821C BIT(28) + +#define BIT_SHIFT_PRI_MASK_TXAC_8821C 21 #define BIT_MASK_PRI_MASK_TXAC_8821C 0x7f -#define BIT_PRI_MASK_TXAC_8821C(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8821C) << BIT_SHIFT_PRI_MASK_TXAC_8821C) -#define BIT_GET_PRI_MASK_TXAC_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8821C) & BIT_MASK_PRI_MASK_TXAC_8821C) - - - -#define BIT_SHIFT_PRI_MASK_NAV_8821C (109 & CPU_OPT_WIDTH) +#define BIT_PRI_MASK_TXAC_8821C(x) \ + (((x) & BIT_MASK_PRI_MASK_TXAC_8821C) << BIT_SHIFT_PRI_MASK_TXAC_8821C) +#define BITS_PRI_MASK_TXAC_8821C \ + (BIT_MASK_PRI_MASK_TXAC_8821C << BIT_SHIFT_PRI_MASK_TXAC_8821C) +#define BIT_CLEAR_PRI_MASK_TXAC_8821C(x) ((x) & (~BITS_PRI_MASK_TXAC_8821C)) +#define BIT_GET_PRI_MASK_TXAC_8821C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8821C) & BIT_MASK_PRI_MASK_TXAC_8821C) +#define BIT_SET_PRI_MASK_TXAC_8821C(x, v) \ + (BIT_CLEAR_PRI_MASK_TXAC_8821C(x) | BIT_PRI_MASK_TXAC_8821C(v)) + +#define BIT_SHIFT_PRI_MASK_NAV_8821C 13 #define BIT_MASK_PRI_MASK_NAV_8821C 0xff -#define BIT_PRI_MASK_NAV_8821C(x) (((x) & BIT_MASK_PRI_MASK_NAV_8821C) << BIT_SHIFT_PRI_MASK_NAV_8821C) -#define BIT_GET_PRI_MASK_NAV_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8821C) & BIT_MASK_PRI_MASK_NAV_8821C) - - -#define BIT_PRI_MASK_CCK_8821C BIT(108) -#define BIT_PRI_MASK_OFDM_8821C BIT(107) -#define BIT_PRI_MASK_RTY_8821C BIT(106) - -#define BIT_SHIFT_PRI_MASK_NUM_8821C (102 & CPU_OPT_WIDTH) +#define BIT_PRI_MASK_NAV_8821C(x) \ + (((x) & BIT_MASK_PRI_MASK_NAV_8821C) << BIT_SHIFT_PRI_MASK_NAV_8821C) +#define BITS_PRI_MASK_NAV_8821C \ + (BIT_MASK_PRI_MASK_NAV_8821C << BIT_SHIFT_PRI_MASK_NAV_8821C) +#define BIT_CLEAR_PRI_MASK_NAV_8821C(x) ((x) & (~BITS_PRI_MASK_NAV_8821C)) +#define BIT_GET_PRI_MASK_NAV_8821C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NAV_8821C) & BIT_MASK_PRI_MASK_NAV_8821C) +#define BIT_SET_PRI_MASK_NAV_8821C(x, v) \ + (BIT_CLEAR_PRI_MASK_NAV_8821C(x) | BIT_PRI_MASK_NAV_8821C(v)) + +#define BIT_PRI_MASK_CCK_V1_8821C BIT(12) +#define BIT_PRI_MASK_OFDM_V1_8821C BIT(11) +#define BIT_PRI_MASK_RTY_V1_8821C BIT(10) + +#define BIT_SHIFT_PRI_MASK_NUM_8821C 6 #define BIT_MASK_PRI_MASK_NUM_8821C 0xf -#define BIT_PRI_MASK_NUM_8821C(x) (((x) & BIT_MASK_PRI_MASK_NUM_8821C) << BIT_SHIFT_PRI_MASK_NUM_8821C) -#define BIT_GET_PRI_MASK_NUM_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8821C) & BIT_MASK_PRI_MASK_NUM_8821C) - - - -#define BIT_SHIFT_PRI_MASK_TYPE_8821C (98 & CPU_OPT_WIDTH) +#define BIT_PRI_MASK_NUM_8821C(x) \ + (((x) & BIT_MASK_PRI_MASK_NUM_8821C) << BIT_SHIFT_PRI_MASK_NUM_8821C) +#define BITS_PRI_MASK_NUM_8821C \ + (BIT_MASK_PRI_MASK_NUM_8821C << BIT_SHIFT_PRI_MASK_NUM_8821C) +#define BIT_CLEAR_PRI_MASK_NUM_8821C(x) ((x) & (~BITS_PRI_MASK_NUM_8821C)) +#define BIT_GET_PRI_MASK_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NUM_8821C) & BIT_MASK_PRI_MASK_NUM_8821C) +#define BIT_SET_PRI_MASK_NUM_8821C(x, v) \ + (BIT_CLEAR_PRI_MASK_NUM_8821C(x) | BIT_PRI_MASK_NUM_8821C(v)) + +#define BIT_SHIFT_PRI_MASK_TYPE_8821C 2 #define BIT_MASK_PRI_MASK_TYPE_8821C 0xf -#define BIT_PRI_MASK_TYPE_8821C(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8821C) << BIT_SHIFT_PRI_MASK_TYPE_8821C) -#define BIT_GET_PRI_MASK_TYPE_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8821C) & BIT_MASK_PRI_MASK_TYPE_8821C) - - -#define BIT_OOB_8821C BIT(97) -#define BIT_ANT_SEL_8821C BIT(96) - -#define BIT_SHIFT_BREAK_TABLE_2_8821C (80 & CPU_OPT_WIDTH) -#define BIT_MASK_BREAK_TABLE_2_8821C 0xffff -#define BIT_BREAK_TABLE_2_8821C(x) (((x) & BIT_MASK_BREAK_TABLE_2_8821C) << BIT_SHIFT_BREAK_TABLE_2_8821C) -#define BIT_GET_BREAK_TABLE_2_8821C(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8821C) & BIT_MASK_BREAK_TABLE_2_8821C) - - - -#define BIT_SHIFT_BREAK_TABLE_1_8821C (64 & CPU_OPT_WIDTH) -#define BIT_MASK_BREAK_TABLE_1_8821C 0xffff -#define BIT_BREAK_TABLE_1_8821C(x) (((x) & BIT_MASK_BREAK_TABLE_1_8821C) << BIT_SHIFT_BREAK_TABLE_1_8821C) -#define BIT_GET_BREAK_TABLE_1_8821C(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8821C) & BIT_MASK_BREAK_TABLE_1_8821C) - - - -#define BIT_SHIFT_COEX_TABLE_2_8821C (32 & CPU_OPT_WIDTH) -#define BIT_MASK_COEX_TABLE_2_8821C 0xffffffffL -#define BIT_COEX_TABLE_2_8821C(x) (((x) & BIT_MASK_COEX_TABLE_2_8821C) << BIT_SHIFT_COEX_TABLE_2_8821C) -#define BIT_GET_COEX_TABLE_2_8821C(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8821C) & BIT_MASK_COEX_TABLE_2_8821C) - - - -#define BIT_SHIFT_COEX_TABLE_1_8821C 0 -#define BIT_MASK_COEX_TABLE_1_8821C 0xffffffffL -#define BIT_COEX_TABLE_1_8821C(x) (((x) & BIT_MASK_COEX_TABLE_1_8821C) << BIT_SHIFT_COEX_TABLE_1_8821C) -#define BIT_GET_COEX_TABLE_1_8821C(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8821C) & BIT_MASK_COEX_TABLE_1_8821C) - - +#define BIT_PRI_MASK_TYPE_8821C(x) \ + (((x) & BIT_MASK_PRI_MASK_TYPE_8821C) << BIT_SHIFT_PRI_MASK_TYPE_8821C) +#define BITS_PRI_MASK_TYPE_8821C \ + (BIT_MASK_PRI_MASK_TYPE_8821C << BIT_SHIFT_PRI_MASK_TYPE_8821C) +#define BIT_CLEAR_PRI_MASK_TYPE_8821C(x) ((x) & (~BITS_PRI_MASK_TYPE_8821C)) +#define BIT_GET_PRI_MASK_TYPE_8821C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8821C) & BIT_MASK_PRI_MASK_TYPE_8821C) +#define BIT_SET_PRI_MASK_TYPE_8821C(x, v) \ + (BIT_CLEAR_PRI_MASK_TYPE_8821C(x) | BIT_PRI_MASK_TYPE_8821C(v)) + +#define BIT_OOB_V1_8821C BIT(1) +#define BIT_ANT_SEL_V1_8821C BIT(0) /* 2 REG_RXCMD_0_8821C */ #define BIT_RXCMD_EN_8821C BIT(31) #define BIT_SHIFT_RXCMD_INFO_8821C 0 #define BIT_MASK_RXCMD_INFO_8821C 0x7fffffffL -#define BIT_RXCMD_INFO_8821C(x) (((x) & BIT_MASK_RXCMD_INFO_8821C) << BIT_SHIFT_RXCMD_INFO_8821C) -#define BIT_GET_RXCMD_INFO_8821C(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8821C) & BIT_MASK_RXCMD_INFO_8821C) - - +#define BIT_RXCMD_INFO_8821C(x) \ + (((x) & BIT_MASK_RXCMD_INFO_8821C) << BIT_SHIFT_RXCMD_INFO_8821C) +#define BITS_RXCMD_INFO_8821C \ + (BIT_MASK_RXCMD_INFO_8821C << BIT_SHIFT_RXCMD_INFO_8821C) +#define BIT_CLEAR_RXCMD_INFO_8821C(x) ((x) & (~BITS_RXCMD_INFO_8821C)) +#define BIT_GET_RXCMD_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_RXCMD_INFO_8821C) & BIT_MASK_RXCMD_INFO_8821C) +#define BIT_SET_RXCMD_INFO_8821C(x, v) \ + (BIT_CLEAR_RXCMD_INFO_8821C(x) | BIT_RXCMD_INFO_8821C(v)) /* 2 REG_RXCMD_1_8821C */ +#define BIT_SHIFT_CSI_RADDR_LATCH_8821C 24 +#define BIT_MASK_CSI_RADDR_LATCH_8821C 0xff +#define BIT_CSI_RADDR_LATCH_8821C(x) \ + (((x) & BIT_MASK_CSI_RADDR_LATCH_8821C) \ + << BIT_SHIFT_CSI_RADDR_LATCH_8821C) +#define BITS_CSI_RADDR_LATCH_8821C \ + (BIT_MASK_CSI_RADDR_LATCH_8821C << BIT_SHIFT_CSI_RADDR_LATCH_8821C) +#define BIT_CLEAR_CSI_RADDR_LATCH_8821C(x) ((x) & (~BITS_CSI_RADDR_LATCH_8821C)) +#define BIT_GET_CSI_RADDR_LATCH_8821C(x) \ + (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_8821C) & \ + BIT_MASK_CSI_RADDR_LATCH_8821C) +#define BIT_SET_CSI_RADDR_LATCH_8821C(x, v) \ + (BIT_CLEAR_CSI_RADDR_LATCH_8821C(x) | BIT_CSI_RADDR_LATCH_8821C(v)) + +#define BIT_SHIFT_CSI_WADDR_LATCH_8821C 16 +#define BIT_MASK_CSI_WADDR_LATCH_8821C 0xff +#define BIT_CSI_WADDR_LATCH_8821C(x) \ + (((x) & BIT_MASK_CSI_WADDR_LATCH_8821C) \ + << BIT_SHIFT_CSI_WADDR_LATCH_8821C) +#define BITS_CSI_WADDR_LATCH_8821C \ + (BIT_MASK_CSI_WADDR_LATCH_8821C << BIT_SHIFT_CSI_WADDR_LATCH_8821C) +#define BIT_CLEAR_CSI_WADDR_LATCH_8821C(x) ((x) & (~BITS_CSI_WADDR_LATCH_8821C)) +#define BIT_GET_CSI_WADDR_LATCH_8821C(x) \ + (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_8821C) & \ + BIT_MASK_CSI_WADDR_LATCH_8821C) +#define BIT_SET_CSI_WADDR_LATCH_8821C(x, v) \ + (BIT_CLEAR_CSI_WADDR_LATCH_8821C(x) | BIT_CSI_WADDR_LATCH_8821C(v)) + #define BIT_SHIFT_RXCMD_PRD_8821C 0 #define BIT_MASK_RXCMD_PRD_8821C 0xffff -#define BIT_RXCMD_PRD_8821C(x) (((x) & BIT_MASK_RXCMD_PRD_8821C) << BIT_SHIFT_RXCMD_PRD_8821C) -#define BIT_GET_RXCMD_PRD_8821C(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8821C) & BIT_MASK_RXCMD_PRD_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_RXCMD_PRD_8821C(x) \ + (((x) & BIT_MASK_RXCMD_PRD_8821C) << BIT_SHIFT_RXCMD_PRD_8821C) +#define BITS_RXCMD_PRD_8821C \ + (BIT_MASK_RXCMD_PRD_8821C << BIT_SHIFT_RXCMD_PRD_8821C) +#define BIT_CLEAR_RXCMD_PRD_8821C(x) ((x) & (~BITS_RXCMD_PRD_8821C)) +#define BIT_GET_RXCMD_PRD_8821C(x) \ + (((x) >> BIT_SHIFT_RXCMD_PRD_8821C) & BIT_MASK_RXCMD_PRD_8821C) +#define BIT_SET_RXCMD_PRD_8821C(x, v) \ + (BIT_CLEAR_RXCMD_PRD_8821C(x) | BIT_RXCMD_PRD_8821C(v)) /* 2 REG_WMAC_RESP_TXINFO_8821C (RESPONSE TXINFO REGISTER) */ #define BIT_SHIFT_WMAC_RESP_MFB_8821C 25 #define BIT_MASK_WMAC_RESP_MFB_8821C 0x7f -#define BIT_WMAC_RESP_MFB_8821C(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8821C) << BIT_SHIFT_WMAC_RESP_MFB_8821C) -#define BIT_GET_WMAC_RESP_MFB_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8821C) & BIT_MASK_WMAC_RESP_MFB_8821C) - - +#define BIT_WMAC_RESP_MFB_8821C(x) \ + (((x) & BIT_MASK_WMAC_RESP_MFB_8821C) << BIT_SHIFT_WMAC_RESP_MFB_8821C) +#define BITS_WMAC_RESP_MFB_8821C \ + (BIT_MASK_WMAC_RESP_MFB_8821C << BIT_SHIFT_WMAC_RESP_MFB_8821C) +#define BIT_CLEAR_WMAC_RESP_MFB_8821C(x) ((x) & (~BITS_WMAC_RESP_MFB_8821C)) +#define BIT_GET_WMAC_RESP_MFB_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8821C) & BIT_MASK_WMAC_RESP_MFB_8821C) +#define BIT_SET_WMAC_RESP_MFB_8821C(x, v) \ + (BIT_CLEAR_WMAC_RESP_MFB_8821C(x) | BIT_WMAC_RESP_MFB_8821C(v)) #define BIT_SHIFT_WMAC_ANTINF_SEL_8821C 23 #define BIT_MASK_WMAC_ANTINF_SEL_8821C 0x3 -#define BIT_WMAC_ANTINF_SEL_8821C(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8821C) << BIT_SHIFT_WMAC_ANTINF_SEL_8821C) -#define BIT_GET_WMAC_ANTINF_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8821C) & BIT_MASK_WMAC_ANTINF_SEL_8821C) - - +#define BIT_WMAC_ANTINF_SEL_8821C(x) \ + (((x) & BIT_MASK_WMAC_ANTINF_SEL_8821C) \ + << BIT_SHIFT_WMAC_ANTINF_SEL_8821C) +#define BITS_WMAC_ANTINF_SEL_8821C \ + (BIT_MASK_WMAC_ANTINF_SEL_8821C << BIT_SHIFT_WMAC_ANTINF_SEL_8821C) +#define BIT_CLEAR_WMAC_ANTINF_SEL_8821C(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8821C)) +#define BIT_GET_WMAC_ANTINF_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8821C) & \ + BIT_MASK_WMAC_ANTINF_SEL_8821C) +#define BIT_SET_WMAC_ANTINF_SEL_8821C(x, v) \ + (BIT_CLEAR_WMAC_ANTINF_SEL_8821C(x) | BIT_WMAC_ANTINF_SEL_8821C(v)) #define BIT_SHIFT_WMAC_ANTSEL_SEL_8821C 21 #define BIT_MASK_WMAC_ANTSEL_SEL_8821C 0x3 -#define BIT_WMAC_ANTSEL_SEL_8821C(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8821C) << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) -#define BIT_GET_WMAC_ANTSEL_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) & BIT_MASK_WMAC_ANTSEL_SEL_8821C) - - +#define BIT_WMAC_ANTSEL_SEL_8821C(x) \ + (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8821C) \ + << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) +#define BITS_WMAC_ANTSEL_SEL_8821C \ + (BIT_MASK_WMAC_ANTSEL_SEL_8821C << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) +#define BIT_CLEAR_WMAC_ANTSEL_SEL_8821C(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8821C)) +#define BIT_GET_WMAC_ANTSEL_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) & \ + BIT_MASK_WMAC_ANTSEL_SEL_8821C) +#define BIT_SET_WMAC_ANTSEL_SEL_8821C(x, v) \ + (BIT_CLEAR_WMAC_ANTSEL_SEL_8821C(x) | BIT_WMAC_ANTSEL_SEL_8821C(v)) #define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C 18 #define BIT_MASK_R_WMAC_RESP_TXPOWER_8821C 0x7 -#define BIT_R_WMAC_RESP_TXPOWER_8821C(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) -#define BIT_GET_R_WMAC_RESP_TXPOWER_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) - - +#define BIT_R_WMAC_RESP_TXPOWER_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) \ + << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) +#define BITS_R_WMAC_RESP_TXPOWER_8821C \ + (BIT_MASK_R_WMAC_RESP_TXPOWER_8821C \ + << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) +#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8821C(x) \ + ((x) & (~BITS_R_WMAC_RESP_TXPOWER_8821C)) +#define BIT_GET_R_WMAC_RESP_TXPOWER_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) & \ + BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) +#define BIT_SET_R_WMAC_RESP_TXPOWER_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_RESP_TXPOWER_8821C(x) | \ + BIT_R_WMAC_RESP_TXPOWER_8821C(v)) #define BIT_SHIFT_WMAC_RESP_TXANT_8821C 0 #define BIT_MASK_WMAC_RESP_TXANT_8821C 0x3ffff -#define BIT_WMAC_RESP_TXANT_8821C(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8821C) << BIT_SHIFT_WMAC_RESP_TXANT_8821C) -#define BIT_GET_WMAC_RESP_TXANT_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8821C) & BIT_MASK_WMAC_RESP_TXANT_8821C) - - +#define BIT_WMAC_RESP_TXANT_8821C(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT_8821C) \ + << BIT_SHIFT_WMAC_RESP_TXANT_8821C) +#define BITS_WMAC_RESP_TXANT_8821C \ + (BIT_MASK_WMAC_RESP_TXANT_8821C << BIT_SHIFT_WMAC_RESP_TXANT_8821C) +#define BIT_CLEAR_WMAC_RESP_TXANT_8821C(x) ((x) & (~BITS_WMAC_RESP_TXANT_8821C)) +#define BIT_GET_WMAC_RESP_TXANT_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8821C) & \ + BIT_MASK_WMAC_RESP_TXANT_8821C) +#define BIT_SET_WMAC_RESP_TXANT_8821C(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT_8821C(x) | BIT_WMAC_RESP_TXANT_8821C(v)) /* 2 REG_BBPSF_CTRL_8821C */ #define BIT_CTL_IDLE_CLR_CSI_RPT_8821C BIT(31) @@ -9761,28 +16022,47 @@ #define BIT_SHIFT_WMAC_CSI_RATE_8821C 24 #define BIT_MASK_WMAC_CSI_RATE_8821C 0x3f -#define BIT_WMAC_CSI_RATE_8821C(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8821C) << BIT_SHIFT_WMAC_CSI_RATE_8821C) -#define BIT_GET_WMAC_CSI_RATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8821C) & BIT_MASK_WMAC_CSI_RATE_8821C) - - +#define BIT_WMAC_CSI_RATE_8821C(x) \ + (((x) & BIT_MASK_WMAC_CSI_RATE_8821C) << BIT_SHIFT_WMAC_CSI_RATE_8821C) +#define BITS_WMAC_CSI_RATE_8821C \ + (BIT_MASK_WMAC_CSI_RATE_8821C << BIT_SHIFT_WMAC_CSI_RATE_8821C) +#define BIT_CLEAR_WMAC_CSI_RATE_8821C(x) ((x) & (~BITS_WMAC_CSI_RATE_8821C)) +#define BIT_GET_WMAC_CSI_RATE_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8821C) & BIT_MASK_WMAC_CSI_RATE_8821C) +#define BIT_SET_WMAC_CSI_RATE_8821C(x, v) \ + (BIT_CLEAR_WMAC_CSI_RATE_8821C(x) | BIT_WMAC_CSI_RATE_8821C(v)) #define BIT_SHIFT_WMAC_RESP_TXRATE_8821C 16 #define BIT_MASK_WMAC_RESP_TXRATE_8821C 0xff -#define BIT_WMAC_RESP_TXRATE_8821C(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8821C) << BIT_SHIFT_WMAC_RESP_TXRATE_8821C) -#define BIT_GET_WMAC_RESP_TXRATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8821C) & BIT_MASK_WMAC_RESP_TXRATE_8821C) - +#define BIT_WMAC_RESP_TXRATE_8821C(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXRATE_8821C) \ + << BIT_SHIFT_WMAC_RESP_TXRATE_8821C) +#define BITS_WMAC_RESP_TXRATE_8821C \ + (BIT_MASK_WMAC_RESP_TXRATE_8821C << BIT_SHIFT_WMAC_RESP_TXRATE_8821C) +#define BIT_CLEAR_WMAC_RESP_TXRATE_8821C(x) \ + ((x) & (~BITS_WMAC_RESP_TXRATE_8821C)) +#define BIT_GET_WMAC_RESP_TXRATE_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8821C) & \ + BIT_MASK_WMAC_RESP_TXRATE_8821C) +#define BIT_SET_WMAC_RESP_TXRATE_8821C(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXRATE_8821C(x) | BIT_WMAC_RESP_TXRATE_8821C(v)) #define BIT_CSI_FORCE_RATE_EN_8821C BIT(15) #define BIT_SHIFT_CSI_RSC_8821C 13 #define BIT_MASK_CSI_RSC_8821C 0x3 -#define BIT_CSI_RSC_8821C(x) (((x) & BIT_MASK_CSI_RSC_8821C) << BIT_SHIFT_CSI_RSC_8821C) -#define BIT_GET_CSI_RSC_8821C(x) (((x) >> BIT_SHIFT_CSI_RSC_8821C) & BIT_MASK_CSI_RSC_8821C) - +#define BIT_CSI_RSC_8821C(x) \ + (((x) & BIT_MASK_CSI_RSC_8821C) << BIT_SHIFT_CSI_RSC_8821C) +#define BITS_CSI_RSC_8821C (BIT_MASK_CSI_RSC_8821C << BIT_SHIFT_CSI_RSC_8821C) +#define BIT_CLEAR_CSI_RSC_8821C(x) ((x) & (~BITS_CSI_RSC_8821C)) +#define BIT_GET_CSI_RSC_8821C(x) \ + (((x) >> BIT_SHIFT_CSI_RSC_8821C) & BIT_MASK_CSI_RSC_8821C) +#define BIT_SET_CSI_RSC_8821C(x, v) \ + (BIT_CLEAR_CSI_RSC_8821C(x) | BIT_CSI_RSC_8821C(v)) #define BIT_CSI_GID_SEL_8821C BIT(12) #define BIT_RDCSIMD_FLAG_TRIG_SEL_8821C BIT(11) -#define BIT_NDPVLD_POS_RST_FFPTR_DIS_8821C BIT(10) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1_8821C BIT(10) #define BIT_NDPVLD_PROTECT_RDRDY_DIS_8821C BIT(9) #define BIT_RDCSI_EMPTY_APPZERO_8821C BIT(8) #define BIT_BBPSF_MPDUCHKEN_8821C BIT(5) @@ -9791,12 +16071,15 @@ #define BIT_SHIFT_BBPSF_ERRTHR_8821C 0 #define BIT_MASK_BBPSF_ERRTHR_8821C 0x7 -#define BIT_BBPSF_ERRTHR_8821C(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8821C) << BIT_SHIFT_BBPSF_ERRTHR_8821C) -#define BIT_GET_BBPSF_ERRTHR_8821C(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8821C) & BIT_MASK_BBPSF_ERRTHR_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_BBPSF_ERRTHR_8821C(x) \ + (((x) & BIT_MASK_BBPSF_ERRTHR_8821C) << BIT_SHIFT_BBPSF_ERRTHR_8821C) +#define BITS_BBPSF_ERRTHR_8821C \ + (BIT_MASK_BBPSF_ERRTHR_8821C << BIT_SHIFT_BBPSF_ERRTHR_8821C) +#define BIT_CLEAR_BBPSF_ERRTHR_8821C(x) ((x) & (~BITS_BBPSF_ERRTHR_8821C)) +#define BIT_GET_BBPSF_ERRTHR_8821C(x) \ + (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8821C) & BIT_MASK_BBPSF_ERRTHR_8821C) +#define BIT_SET_BBPSF_ERRTHR_8821C(x, v) \ + (BIT_CLEAR_BBPSF_ERRTHR_8821C(x) | BIT_BBPSF_ERRTHR_8821C(v)) /* 2 REG_P2P_RX_BCN_NOA_8821C (P2P RX BEACON NOA REGISTER) */ #define BIT_NOA_PARSER_EN_8821C BIT(15) @@ -9804,219 +16087,498 @@ #define BIT_SHIFT_P2P_OUI_TYPE_8821C 0 #define BIT_MASK_P2P_OUI_TYPE_8821C 0xff -#define BIT_P2P_OUI_TYPE_8821C(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8821C) << BIT_SHIFT_P2P_OUI_TYPE_8821C) -#define BIT_GET_P2P_OUI_TYPE_8821C(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8821C) & BIT_MASK_P2P_OUI_TYPE_8821C) - +#define BIT_P2P_OUI_TYPE_8821C(x) \ + (((x) & BIT_MASK_P2P_OUI_TYPE_8821C) << BIT_SHIFT_P2P_OUI_TYPE_8821C) +#define BITS_P2P_OUI_TYPE_8821C \ + (BIT_MASK_P2P_OUI_TYPE_8821C << BIT_SHIFT_P2P_OUI_TYPE_8821C) +#define BIT_CLEAR_P2P_OUI_TYPE_8821C(x) ((x) & (~BITS_P2P_OUI_TYPE_8821C)) +#define BIT_GET_P2P_OUI_TYPE_8821C(x) \ + (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8821C) & BIT_MASK_P2P_OUI_TYPE_8821C) +#define BIT_SET_P2P_OUI_TYPE_8821C(x, v) \ + (BIT_CLEAR_P2P_OUI_TYPE_8821C(x) | BIT_P2P_OUI_TYPE_8821C(v)) +/* 2 REG_RSVD_8821C */ /* 2 REG_ASSOCIATED_BFMER0_INFO_8821C (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ -#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C (48 & CPU_OPT_WIDTH) +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8821C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(v)) + +/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8821C */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C 16 #define BIT_MASK_R_WMAC_TXCSI_AID0_8821C 0x1ff -#define BIT_R_WMAC_TXCSI_AID0_8821C(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) -#define BIT_GET_R_WMAC_TXCSI_AID0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C) - - - -#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C 0 -#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R0_8821C(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C) - - +#define BIT_R_WMAC_TXCSI_AID0_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) +#define BITS_R_WMAC_TXCSI_AID0_8821C \ + (BIT_MASK_R_WMAC_TXCSI_AID0_8821C << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) +#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8821C(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID0_8821C)) +#define BIT_GET_R_WMAC_TXCSI_AID0_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) & \ + BIT_MASK_R_WMAC_TXCSI_AID0_8821C) +#define BIT_SET_R_WMAC_TXCSI_AID0_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID0_8821C(x) | BIT_R_WMAC_TXCSI_AID0_8821C(v)) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(v)) /* 2 REG_ASSOCIATED_BFMER1_INFO_8821C (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ -#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C (48 & CPU_OPT_WIDTH) +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8821C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(v)) + +/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8821C */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C 16 #define BIT_MASK_R_WMAC_TXCSI_AID1_8821C 0x1ff -#define BIT_R_WMAC_TXCSI_AID1_8821C(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) -#define BIT_GET_R_WMAC_TXCSI_AID1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C) - - - -#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C 0 -#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R1_8821C(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_R_WMAC_TXCSI_AID1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) +#define BITS_R_WMAC_TXCSI_AID1_8821C \ + (BIT_MASK_R_WMAC_TXCSI_AID1_8821C << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) +#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8821C(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID1_8821C)) +#define BIT_GET_R_WMAC_TXCSI_AID1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) & \ + BIT_MASK_R_WMAC_TXCSI_AID1_8821C) +#define BIT_SET_R_WMAC_TXCSI_AID1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID1_8821C(x) | BIT_R_WMAC_TXCSI_AID1_8821C(v)) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW20_8821C (TX CSI REPORT PARAMETER REGISTER) */ #define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C 16 #define BIT_MASK_R_WMAC_BFINFO_20M_1_8821C 0xfff -#define BIT_R_WMAC_BFINFO_20M_1_8821C(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) -#define BIT_GET_R_WMAC_BFINFO_20M_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) - - +#define BIT_R_WMAC_BFINFO_20M_1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) +#define BITS_R_WMAC_BFINFO_20M_1_8821C \ + (BIT_MASK_R_WMAC_BFINFO_20M_1_8821C \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8821C(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8821C)) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) & \ + BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) +#define BIT_SET_R_WMAC_BFINFO_20M_1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8821C(x) | \ + BIT_R_WMAC_BFINFO_20M_1_8821C(v)) #define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C 0 #define BIT_MASK_R_WMAC_BFINFO_20M_0_8821C 0xfff -#define BIT_R_WMAC_BFINFO_20M_0_8821C(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) -#define BIT_GET_R_WMAC_BFINFO_20M_0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) - - +#define BIT_R_WMAC_BFINFO_20M_0_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) +#define BITS_R_WMAC_BFINFO_20M_0_8821C \ + (BIT_MASK_R_WMAC_BFINFO_20M_0_8821C \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8821C(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8821C)) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) & \ + BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) +#define BIT_SET_R_WMAC_BFINFO_20M_0_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8821C(x) | \ + BIT_R_WMAC_BFINFO_20M_0_8821C(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW40_8821C (TX CSI REPORT PARAMETER_BW40 REGISTER) */ #define BIT_SHIFT_WMAC_RESP_ANTCD_8821C 0 #define BIT_MASK_WMAC_RESP_ANTCD_8821C 0xf -#define BIT_WMAC_RESP_ANTCD_8821C(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8821C) << BIT_SHIFT_WMAC_RESP_ANTCD_8821C) -#define BIT_GET_WMAC_RESP_ANTCD_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8821C) & BIT_MASK_WMAC_RESP_ANTCD_8821C) - +#define BIT_WMAC_RESP_ANTCD_8821C(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTCD_8821C) \ + << BIT_SHIFT_WMAC_RESP_ANTCD_8821C) +#define BITS_WMAC_RESP_ANTCD_8821C \ + (BIT_MASK_WMAC_RESP_ANTCD_8821C << BIT_SHIFT_WMAC_RESP_ANTCD_8821C) +#define BIT_CLEAR_WMAC_RESP_ANTCD_8821C(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8821C)) +#define BIT_GET_WMAC_RESP_ANTCD_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8821C) & \ + BIT_MASK_WMAC_RESP_ANTCD_8821C) +#define BIT_SET_WMAC_RESP_ANTCD_8821C(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTCD_8821C(x) | BIT_WMAC_RESP_ANTCD_8821C(v)) - -/* 2 REG_TX_CSI_RPT_PARAM_BW80_8821C (TX CSI REPORT PARAMETER_BW80 REGISTER) */ +/* 2 REG_RSVD_8821C */ /* 2 REG_BCN_PSR_RPT2_8821C (BEACON PARSER REPORT REGISTER2) */ #define BIT_SHIFT_DTIM_CNT2_8821C 24 #define BIT_MASK_DTIM_CNT2_8821C 0xff -#define BIT_DTIM_CNT2_8821C(x) (((x) & BIT_MASK_DTIM_CNT2_8821C) << BIT_SHIFT_DTIM_CNT2_8821C) -#define BIT_GET_DTIM_CNT2_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8821C) & BIT_MASK_DTIM_CNT2_8821C) - - +#define BIT_DTIM_CNT2_8821C(x) \ + (((x) & BIT_MASK_DTIM_CNT2_8821C) << BIT_SHIFT_DTIM_CNT2_8821C) +#define BITS_DTIM_CNT2_8821C \ + (BIT_MASK_DTIM_CNT2_8821C << BIT_SHIFT_DTIM_CNT2_8821C) +#define BIT_CLEAR_DTIM_CNT2_8821C(x) ((x) & (~BITS_DTIM_CNT2_8821C)) +#define BIT_GET_DTIM_CNT2_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT2_8821C) & BIT_MASK_DTIM_CNT2_8821C) +#define BIT_SET_DTIM_CNT2_8821C(x, v) \ + (BIT_CLEAR_DTIM_CNT2_8821C(x) | BIT_DTIM_CNT2_8821C(v)) #define BIT_SHIFT_DTIM_PERIOD2_8821C 16 #define BIT_MASK_DTIM_PERIOD2_8821C 0xff -#define BIT_DTIM_PERIOD2_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD2_8821C) << BIT_SHIFT_DTIM_PERIOD2_8821C) -#define BIT_GET_DTIM_PERIOD2_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8821C) & BIT_MASK_DTIM_PERIOD2_8821C) - +#define BIT_DTIM_PERIOD2_8821C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD2_8821C) << BIT_SHIFT_DTIM_PERIOD2_8821C) +#define BITS_DTIM_PERIOD2_8821C \ + (BIT_MASK_DTIM_PERIOD2_8821C << BIT_SHIFT_DTIM_PERIOD2_8821C) +#define BIT_CLEAR_DTIM_PERIOD2_8821C(x) ((x) & (~BITS_DTIM_PERIOD2_8821C)) +#define BIT_GET_DTIM_PERIOD2_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD2_8821C) & BIT_MASK_DTIM_PERIOD2_8821C) +#define BIT_SET_DTIM_PERIOD2_8821C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD2_8821C(x) | BIT_DTIM_PERIOD2_8821C(v)) #define BIT_DTIM2_8821C BIT(15) #define BIT_TIM2_8821C BIT(14) #define BIT_SHIFT_PS_AID_2_8821C 0 #define BIT_MASK_PS_AID_2_8821C 0x7ff -#define BIT_PS_AID_2_8821C(x) (((x) & BIT_MASK_PS_AID_2_8821C) << BIT_SHIFT_PS_AID_2_8821C) -#define BIT_GET_PS_AID_2_8821C(x) (((x) >> BIT_SHIFT_PS_AID_2_8821C) & BIT_MASK_PS_AID_2_8821C) - - +#define BIT_PS_AID_2_8821C(x) \ + (((x) & BIT_MASK_PS_AID_2_8821C) << BIT_SHIFT_PS_AID_2_8821C) +#define BITS_PS_AID_2_8821C \ + (BIT_MASK_PS_AID_2_8821C << BIT_SHIFT_PS_AID_2_8821C) +#define BIT_CLEAR_PS_AID_2_8821C(x) ((x) & (~BITS_PS_AID_2_8821C)) +#define BIT_GET_PS_AID_2_8821C(x) \ + (((x) >> BIT_SHIFT_PS_AID_2_8821C) & BIT_MASK_PS_AID_2_8821C) +#define BIT_SET_PS_AID_2_8821C(x, v) \ + (BIT_CLEAR_PS_AID_2_8821C(x) | BIT_PS_AID_2_8821C(v)) /* 2 REG_BCN_PSR_RPT3_8821C (BEACON PARSER REPORT REGISTER3) */ #define BIT_SHIFT_DTIM_CNT3_8821C 24 #define BIT_MASK_DTIM_CNT3_8821C 0xff -#define BIT_DTIM_CNT3_8821C(x) (((x) & BIT_MASK_DTIM_CNT3_8821C) << BIT_SHIFT_DTIM_CNT3_8821C) -#define BIT_GET_DTIM_CNT3_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8821C) & BIT_MASK_DTIM_CNT3_8821C) - - +#define BIT_DTIM_CNT3_8821C(x) \ + (((x) & BIT_MASK_DTIM_CNT3_8821C) << BIT_SHIFT_DTIM_CNT3_8821C) +#define BITS_DTIM_CNT3_8821C \ + (BIT_MASK_DTIM_CNT3_8821C << BIT_SHIFT_DTIM_CNT3_8821C) +#define BIT_CLEAR_DTIM_CNT3_8821C(x) ((x) & (~BITS_DTIM_CNT3_8821C)) +#define BIT_GET_DTIM_CNT3_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT3_8821C) & BIT_MASK_DTIM_CNT3_8821C) +#define BIT_SET_DTIM_CNT3_8821C(x, v) \ + (BIT_CLEAR_DTIM_CNT3_8821C(x) | BIT_DTIM_CNT3_8821C(v)) #define BIT_SHIFT_DTIM_PERIOD3_8821C 16 #define BIT_MASK_DTIM_PERIOD3_8821C 0xff -#define BIT_DTIM_PERIOD3_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD3_8821C) << BIT_SHIFT_DTIM_PERIOD3_8821C) -#define BIT_GET_DTIM_PERIOD3_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8821C) & BIT_MASK_DTIM_PERIOD3_8821C) - +#define BIT_DTIM_PERIOD3_8821C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD3_8821C) << BIT_SHIFT_DTIM_PERIOD3_8821C) +#define BITS_DTIM_PERIOD3_8821C \ + (BIT_MASK_DTIM_PERIOD3_8821C << BIT_SHIFT_DTIM_PERIOD3_8821C) +#define BIT_CLEAR_DTIM_PERIOD3_8821C(x) ((x) & (~BITS_DTIM_PERIOD3_8821C)) +#define BIT_GET_DTIM_PERIOD3_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD3_8821C) & BIT_MASK_DTIM_PERIOD3_8821C) +#define BIT_SET_DTIM_PERIOD3_8821C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD3_8821C(x) | BIT_DTIM_PERIOD3_8821C(v)) #define BIT_DTIM3_8821C BIT(15) #define BIT_TIM3_8821C BIT(14) #define BIT_SHIFT_PS_AID_3_8821C 0 #define BIT_MASK_PS_AID_3_8821C 0x7ff -#define BIT_PS_AID_3_8821C(x) (((x) & BIT_MASK_PS_AID_3_8821C) << BIT_SHIFT_PS_AID_3_8821C) -#define BIT_GET_PS_AID_3_8821C(x) (((x) >> BIT_SHIFT_PS_AID_3_8821C) & BIT_MASK_PS_AID_3_8821C) - - +#define BIT_PS_AID_3_8821C(x) \ + (((x) & BIT_MASK_PS_AID_3_8821C) << BIT_SHIFT_PS_AID_3_8821C) +#define BITS_PS_AID_3_8821C \ + (BIT_MASK_PS_AID_3_8821C << BIT_SHIFT_PS_AID_3_8821C) +#define BIT_CLEAR_PS_AID_3_8821C(x) ((x) & (~BITS_PS_AID_3_8821C)) +#define BIT_GET_PS_AID_3_8821C(x) \ + (((x) >> BIT_SHIFT_PS_AID_3_8821C) & BIT_MASK_PS_AID_3_8821C) +#define BIT_SET_PS_AID_3_8821C(x, v) \ + (BIT_CLEAR_PS_AID_3_8821C(x) | BIT_PS_AID_3_8821C(v)) /* 2 REG_BCN_PSR_RPT4_8821C (BEACON PARSER REPORT REGISTER4) */ #define BIT_SHIFT_DTIM_CNT4_8821C 24 #define BIT_MASK_DTIM_CNT4_8821C 0xff -#define BIT_DTIM_CNT4_8821C(x) (((x) & BIT_MASK_DTIM_CNT4_8821C) << BIT_SHIFT_DTIM_CNT4_8821C) -#define BIT_GET_DTIM_CNT4_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8821C) & BIT_MASK_DTIM_CNT4_8821C) - - +#define BIT_DTIM_CNT4_8821C(x) \ + (((x) & BIT_MASK_DTIM_CNT4_8821C) << BIT_SHIFT_DTIM_CNT4_8821C) +#define BITS_DTIM_CNT4_8821C \ + (BIT_MASK_DTIM_CNT4_8821C << BIT_SHIFT_DTIM_CNT4_8821C) +#define BIT_CLEAR_DTIM_CNT4_8821C(x) ((x) & (~BITS_DTIM_CNT4_8821C)) +#define BIT_GET_DTIM_CNT4_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT4_8821C) & BIT_MASK_DTIM_CNT4_8821C) +#define BIT_SET_DTIM_CNT4_8821C(x, v) \ + (BIT_CLEAR_DTIM_CNT4_8821C(x) | BIT_DTIM_CNT4_8821C(v)) #define BIT_SHIFT_DTIM_PERIOD4_8821C 16 #define BIT_MASK_DTIM_PERIOD4_8821C 0xff -#define BIT_DTIM_PERIOD4_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD4_8821C) << BIT_SHIFT_DTIM_PERIOD4_8821C) -#define BIT_GET_DTIM_PERIOD4_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8821C) & BIT_MASK_DTIM_PERIOD4_8821C) - +#define BIT_DTIM_PERIOD4_8821C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD4_8821C) << BIT_SHIFT_DTIM_PERIOD4_8821C) +#define BITS_DTIM_PERIOD4_8821C \ + (BIT_MASK_DTIM_PERIOD4_8821C << BIT_SHIFT_DTIM_PERIOD4_8821C) +#define BIT_CLEAR_DTIM_PERIOD4_8821C(x) ((x) & (~BITS_DTIM_PERIOD4_8821C)) +#define BIT_GET_DTIM_PERIOD4_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD4_8821C) & BIT_MASK_DTIM_PERIOD4_8821C) +#define BIT_SET_DTIM_PERIOD4_8821C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD4_8821C(x) | BIT_DTIM_PERIOD4_8821C(v)) #define BIT_DTIM4_8821C BIT(15) #define BIT_TIM4_8821C BIT(14) #define BIT_SHIFT_PS_AID_4_8821C 0 #define BIT_MASK_PS_AID_4_8821C 0x7ff -#define BIT_PS_AID_4_8821C(x) (((x) & BIT_MASK_PS_AID_4_8821C) << BIT_SHIFT_PS_AID_4_8821C) -#define BIT_GET_PS_AID_4_8821C(x) (((x) >> BIT_SHIFT_PS_AID_4_8821C) & BIT_MASK_PS_AID_4_8821C) - - +#define BIT_PS_AID_4_8821C(x) \ + (((x) & BIT_MASK_PS_AID_4_8821C) << BIT_SHIFT_PS_AID_4_8821C) +#define BITS_PS_AID_4_8821C \ + (BIT_MASK_PS_AID_4_8821C << BIT_SHIFT_PS_AID_4_8821C) +#define BIT_CLEAR_PS_AID_4_8821C(x) ((x) & (~BITS_PS_AID_4_8821C)) +#define BIT_GET_PS_AID_4_8821C(x) \ + (((x) >> BIT_SHIFT_PS_AID_4_8821C) & BIT_MASK_PS_AID_4_8821C) +#define BIT_SET_PS_AID_4_8821C(x, v) \ + (BIT_CLEAR_PS_AID_4_8821C(x) | BIT_PS_AID_4_8821C(v)) /* 2 REG_A1_ADDR_MASK_8821C (A1 ADDR MASK REGISTER) */ #define BIT_SHIFT_A1_ADDR_MASK_8821C 0 #define BIT_MASK_A1_ADDR_MASK_8821C 0xffffffffL -#define BIT_A1_ADDR_MASK_8821C(x) (((x) & BIT_MASK_A1_ADDR_MASK_8821C) << BIT_SHIFT_A1_ADDR_MASK_8821C) -#define BIT_GET_A1_ADDR_MASK_8821C(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8821C) & BIT_MASK_A1_ADDR_MASK_8821C) +#define BIT_A1_ADDR_MASK_8821C(x) \ + (((x) & BIT_MASK_A1_ADDR_MASK_8821C) << BIT_SHIFT_A1_ADDR_MASK_8821C) +#define BITS_A1_ADDR_MASK_8821C \ + (BIT_MASK_A1_ADDR_MASK_8821C << BIT_SHIFT_A1_ADDR_MASK_8821C) +#define BIT_CLEAR_A1_ADDR_MASK_8821C(x) ((x) & (~BITS_A1_ADDR_MASK_8821C)) +#define BIT_GET_A1_ADDR_MASK_8821C(x) \ + (((x) >> BIT_SHIFT_A1_ADDR_MASK_8821C) & BIT_MASK_A1_ADDR_MASK_8821C) +#define BIT_SET_A1_ADDR_MASK_8821C(x, v) \ + (BIT_CLEAR_A1_ADDR_MASK_8821C(x) | BIT_A1_ADDR_MASK_8821C(v)) +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ -/* 2 REG_MACID2_8821C (MAC ID2 REGISTER) */ +/* 2 REG_RSVD_8821C */ -#define BIT_SHIFT_MACID2_8821C 0 -#define BIT_MASK_MACID2_8821C 0xffffffffffffL -#define BIT_MACID2_8821C(x) (((x) & BIT_MASK_MACID2_8821C) << BIT_SHIFT_MACID2_8821C) -#define BIT_GET_MACID2_8821C(x) (((x) >> BIT_SHIFT_MACID2_8821C) & BIT_MASK_MACID2_8821C) +/* 2 REG_RSVD_8821C */ +/* 2 REG_MACID2_8821C (MAC ID2 REGISTER) */ +#define BIT_SHIFT_MACID2_V1_8821C 0 +#define BIT_MASK_MACID2_V1_8821C 0xffffffffL +#define BIT_MACID2_V1_8821C(x) \ + (((x) & BIT_MASK_MACID2_V1_8821C) << BIT_SHIFT_MACID2_V1_8821C) +#define BITS_MACID2_V1_8821C \ + (BIT_MASK_MACID2_V1_8821C << BIT_SHIFT_MACID2_V1_8821C) +#define BIT_CLEAR_MACID2_V1_8821C(x) ((x) & (~BITS_MACID2_V1_8821C)) +#define BIT_GET_MACID2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID2_V1_8821C) & BIT_MASK_MACID2_V1_8821C) +#define BIT_SET_MACID2_V1_8821C(x, v) \ + (BIT_CLEAR_MACID2_V1_8821C(x) | BIT_MACID2_V1_8821C(v)) + +/* 2 REG_MACID2_H_8821C (MAC ID2 REGISTER) */ + +#define BIT_SHIFT_MACID2_H_V1_8821C 0 +#define BIT_MASK_MACID2_H_V1_8821C 0xffff +#define BIT_MACID2_H_V1_8821C(x) \ + (((x) & BIT_MASK_MACID2_H_V1_8821C) << BIT_SHIFT_MACID2_H_V1_8821C) +#define BITS_MACID2_H_V1_8821C \ + (BIT_MASK_MACID2_H_V1_8821C << BIT_SHIFT_MACID2_H_V1_8821C) +#define BIT_CLEAR_MACID2_H_V1_8821C(x) ((x) & (~BITS_MACID2_H_V1_8821C)) +#define BIT_GET_MACID2_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID2_H_V1_8821C) & BIT_MASK_MACID2_H_V1_8821C) +#define BIT_SET_MACID2_H_V1_8821C(x, v) \ + (BIT_CLEAR_MACID2_H_V1_8821C(x) | BIT_MACID2_H_V1_8821C(v)) /* 2 REG_BSSID2_8821C (BSSID2 REGISTER) */ -#define BIT_SHIFT_BSSID2_8821C 0 -#define BIT_MASK_BSSID2_8821C 0xffffffffffffL -#define BIT_BSSID2_8821C(x) (((x) & BIT_MASK_BSSID2_8821C) << BIT_SHIFT_BSSID2_8821C) -#define BIT_GET_BSSID2_8821C(x) (((x) >> BIT_SHIFT_BSSID2_8821C) & BIT_MASK_BSSID2_8821C) - - +#define BIT_SHIFT_BSSID2_V1_8821C 0 +#define BIT_MASK_BSSID2_V1_8821C 0xffffffffL +#define BIT_BSSID2_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID2_V1_8821C) << BIT_SHIFT_BSSID2_V1_8821C) +#define BITS_BSSID2_V1_8821C \ + (BIT_MASK_BSSID2_V1_8821C << BIT_SHIFT_BSSID2_V1_8821C) +#define BIT_CLEAR_BSSID2_V1_8821C(x) ((x) & (~BITS_BSSID2_V1_8821C)) +#define BIT_GET_BSSID2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID2_V1_8821C) & BIT_MASK_BSSID2_V1_8821C) +#define BIT_SET_BSSID2_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID2_V1_8821C(x) | BIT_BSSID2_V1_8821C(v)) + +/* 2 REG_BSSID2_H_8821C (BSSID2 REGISTER) */ + +#define BIT_SHIFT_BSSID2_H_V1_8821C 0 +#define BIT_MASK_BSSID2_H_V1_8821C 0xffff +#define BIT_BSSID2_H_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID2_H_V1_8821C) << BIT_SHIFT_BSSID2_H_V1_8821C) +#define BITS_BSSID2_H_V1_8821C \ + (BIT_MASK_BSSID2_H_V1_8821C << BIT_SHIFT_BSSID2_H_V1_8821C) +#define BIT_CLEAR_BSSID2_H_V1_8821C(x) ((x) & (~BITS_BSSID2_H_V1_8821C)) +#define BIT_GET_BSSID2_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID2_H_V1_8821C) & BIT_MASK_BSSID2_H_V1_8821C) +#define BIT_SET_BSSID2_H_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID2_H_V1_8821C(x) | BIT_BSSID2_H_V1_8821C(v)) /* 2 REG_MACID3_8821C (MAC ID3 REGISTER) */ -#define BIT_SHIFT_MACID3_8821C 0 -#define BIT_MASK_MACID3_8821C 0xffffffffffffL -#define BIT_MACID3_8821C(x) (((x) & BIT_MASK_MACID3_8821C) << BIT_SHIFT_MACID3_8821C) -#define BIT_GET_MACID3_8821C(x) (((x) >> BIT_SHIFT_MACID3_8821C) & BIT_MASK_MACID3_8821C) - - +#define BIT_SHIFT_MACID3_V1_8821C 0 +#define BIT_MASK_MACID3_V1_8821C 0xffffffffL +#define BIT_MACID3_V1_8821C(x) \ + (((x) & BIT_MASK_MACID3_V1_8821C) << BIT_SHIFT_MACID3_V1_8821C) +#define BITS_MACID3_V1_8821C \ + (BIT_MASK_MACID3_V1_8821C << BIT_SHIFT_MACID3_V1_8821C) +#define BIT_CLEAR_MACID3_V1_8821C(x) ((x) & (~BITS_MACID3_V1_8821C)) +#define BIT_GET_MACID3_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID3_V1_8821C) & BIT_MASK_MACID3_V1_8821C) +#define BIT_SET_MACID3_V1_8821C(x, v) \ + (BIT_CLEAR_MACID3_V1_8821C(x) | BIT_MACID3_V1_8821C(v)) + +/* 2 REG_MACID3_H_8821C (MAC ID3 REGISTER) */ + +#define BIT_SHIFT_MACID3_H_V1_8821C 0 +#define BIT_MASK_MACID3_H_V1_8821C 0xffff +#define BIT_MACID3_H_V1_8821C(x) \ + (((x) & BIT_MASK_MACID3_H_V1_8821C) << BIT_SHIFT_MACID3_H_V1_8821C) +#define BITS_MACID3_H_V1_8821C \ + (BIT_MASK_MACID3_H_V1_8821C << BIT_SHIFT_MACID3_H_V1_8821C) +#define BIT_CLEAR_MACID3_H_V1_8821C(x) ((x) & (~BITS_MACID3_H_V1_8821C)) +#define BIT_GET_MACID3_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID3_H_V1_8821C) & BIT_MASK_MACID3_H_V1_8821C) +#define BIT_SET_MACID3_H_V1_8821C(x, v) \ + (BIT_CLEAR_MACID3_H_V1_8821C(x) | BIT_MACID3_H_V1_8821C(v)) /* 2 REG_BSSID3_8821C (BSSID3 REGISTER) */ -#define BIT_SHIFT_BSSID3_8821C 0 -#define BIT_MASK_BSSID3_8821C 0xffffffffffffL -#define BIT_BSSID3_8821C(x) (((x) & BIT_MASK_BSSID3_8821C) << BIT_SHIFT_BSSID3_8821C) -#define BIT_GET_BSSID3_8821C(x) (((x) >> BIT_SHIFT_BSSID3_8821C) & BIT_MASK_BSSID3_8821C) - - +#define BIT_SHIFT_BSSID3_V1_8821C 0 +#define BIT_MASK_BSSID3_V1_8821C 0xffffffffL +#define BIT_BSSID3_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID3_V1_8821C) << BIT_SHIFT_BSSID3_V1_8821C) +#define BITS_BSSID3_V1_8821C \ + (BIT_MASK_BSSID3_V1_8821C << BIT_SHIFT_BSSID3_V1_8821C) +#define BIT_CLEAR_BSSID3_V1_8821C(x) ((x) & (~BITS_BSSID3_V1_8821C)) +#define BIT_GET_BSSID3_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID3_V1_8821C) & BIT_MASK_BSSID3_V1_8821C) +#define BIT_SET_BSSID3_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID3_V1_8821C(x) | BIT_BSSID3_V1_8821C(v)) + +/* 2 REG_BSSID3_H_8821C (BSSID3 REGISTER) */ + +#define BIT_SHIFT_BSSID3_H_V1_8821C 0 +#define BIT_MASK_BSSID3_H_V1_8821C 0xffff +#define BIT_BSSID3_H_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID3_H_V1_8821C) << BIT_SHIFT_BSSID3_H_V1_8821C) +#define BITS_BSSID3_H_V1_8821C \ + (BIT_MASK_BSSID3_H_V1_8821C << BIT_SHIFT_BSSID3_H_V1_8821C) +#define BIT_CLEAR_BSSID3_H_V1_8821C(x) ((x) & (~BITS_BSSID3_H_V1_8821C)) +#define BIT_GET_BSSID3_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID3_H_V1_8821C) & BIT_MASK_BSSID3_H_V1_8821C) +#define BIT_SET_BSSID3_H_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID3_H_V1_8821C(x) | BIT_BSSID3_H_V1_8821C(v)) /* 2 REG_MACID4_8821C (MAC ID4 REGISTER) */ -#define BIT_SHIFT_MACID4_8821C 0 -#define BIT_MASK_MACID4_8821C 0xffffffffffffL -#define BIT_MACID4_8821C(x) (((x) & BIT_MASK_MACID4_8821C) << BIT_SHIFT_MACID4_8821C) -#define BIT_GET_MACID4_8821C(x) (((x) >> BIT_SHIFT_MACID4_8821C) & BIT_MASK_MACID4_8821C) - - +#define BIT_SHIFT_MACID4_V1_8821C 0 +#define BIT_MASK_MACID4_V1_8821C 0xffffffffL +#define BIT_MACID4_V1_8821C(x) \ + (((x) & BIT_MASK_MACID4_V1_8821C) << BIT_SHIFT_MACID4_V1_8821C) +#define BITS_MACID4_V1_8821C \ + (BIT_MASK_MACID4_V1_8821C << BIT_SHIFT_MACID4_V1_8821C) +#define BIT_CLEAR_MACID4_V1_8821C(x) ((x) & (~BITS_MACID4_V1_8821C)) +#define BIT_GET_MACID4_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID4_V1_8821C) & BIT_MASK_MACID4_V1_8821C) +#define BIT_SET_MACID4_V1_8821C(x, v) \ + (BIT_CLEAR_MACID4_V1_8821C(x) | BIT_MACID4_V1_8821C(v)) + +/* 2 REG_MACID4_H_8821C (MAC ID4 REGISTER) */ + +#define BIT_SHIFT_MACID4_H_V1_8821C 0 +#define BIT_MASK_MACID4_H_V1_8821C 0xffff +#define BIT_MACID4_H_V1_8821C(x) \ + (((x) & BIT_MASK_MACID4_H_V1_8821C) << BIT_SHIFT_MACID4_H_V1_8821C) +#define BITS_MACID4_H_V1_8821C \ + (BIT_MASK_MACID4_H_V1_8821C << BIT_SHIFT_MACID4_H_V1_8821C) +#define BIT_CLEAR_MACID4_H_V1_8821C(x) ((x) & (~BITS_MACID4_H_V1_8821C)) +#define BIT_GET_MACID4_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID4_H_V1_8821C) & BIT_MASK_MACID4_H_V1_8821C) +#define BIT_SET_MACID4_H_V1_8821C(x, v) \ + (BIT_CLEAR_MACID4_H_V1_8821C(x) | BIT_MACID4_H_V1_8821C(v)) /* 2 REG_BSSID4_8821C (BSSID4 REGISTER) */ -#define BIT_SHIFT_BSSID4_8821C 0 -#define BIT_MASK_BSSID4_8821C 0xffffffffffffL -#define BIT_BSSID4_8821C(x) (((x) & BIT_MASK_BSSID4_8821C) << BIT_SHIFT_BSSID4_8821C) -#define BIT_GET_BSSID4_8821C(x) (((x) >> BIT_SHIFT_BSSID4_8821C) & BIT_MASK_BSSID4_8821C) +#define BIT_SHIFT_BSSID4_V1_8821C 0 +#define BIT_MASK_BSSID4_V1_8821C 0xffffffffL +#define BIT_BSSID4_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID4_V1_8821C) << BIT_SHIFT_BSSID4_V1_8821C) +#define BITS_BSSID4_V1_8821C \ + (BIT_MASK_BSSID4_V1_8821C << BIT_SHIFT_BSSID4_V1_8821C) +#define BIT_CLEAR_BSSID4_V1_8821C(x) ((x) & (~BITS_BSSID4_V1_8821C)) +#define BIT_GET_BSSID4_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID4_V1_8821C) & BIT_MASK_BSSID4_V1_8821C) +#define BIT_SET_BSSID4_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID4_V1_8821C(x) | BIT_BSSID4_V1_8821C(v)) + +/* 2 REG_BSSID4_H_8821C (BSSID4 REGISTER) */ + +#define BIT_SHIFT_BSSID4_H_V1_8821C 0 +#define BIT_MASK_BSSID4_H_V1_8821C 0xffff +#define BIT_BSSID4_H_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID4_H_V1_8821C) << BIT_SHIFT_BSSID4_H_V1_8821C) +#define BITS_BSSID4_H_V1_8821C \ + (BIT_MASK_BSSID4_H_V1_8821C << BIT_SHIFT_BSSID4_H_V1_8821C) +#define BIT_CLEAR_BSSID4_H_V1_8821C(x) ((x) & (~BITS_BSSID4_H_V1_8821C)) +#define BIT_GET_BSSID4_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID4_H_V1_8821C) & BIT_MASK_BSSID4_H_V1_8821C) +#define BIT_SET_BSSID4_H_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID4_H_V1_8821C(x) | BIT_BSSID4_H_V1_8821C(v)) + +/* 2 REG_NOA_REPORT_8821C */ +/* 2 REG_NOA_REPORT_1_8821C */ +/* 2 REG_NOA_REPORT_2_8821C */ -/* 2 REG_NOA_REPORT_8821C */ +/* 2 REG_NOA_REPORT_3_8821C */ /* 2 REG_PWRBIT_SETTING_8821C */ #define BIT_CLI3_PWRBIT_OW_EN_8821C BIT(7) @@ -10028,22 +16590,55 @@ #define BIT_CLI0_PWRBIT_OW_EN_8821C BIT(1) #define BIT_CLI0_PWR_ST_8821C BIT(0) -/* 2 REG_WMAC_MU_BF_OPTION_8821C */ +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_MU_BF_OPTION_8821C */ #define BIT_WMAC_RESP_NONSTA1_DIS_8821C BIT(7) #define BIT_WMAC_TXMU_ACKPOLICY_EN_8821C BIT(6) #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C 4 #define BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C 0x3 -#define BIT_WMAC_TXMU_ACKPOLICY_8821C(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) -#define BIT_GET_WMAC_TXMU_ACKPOLICY_8821C(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) - - +#define BIT_WMAC_TXMU_ACKPOLICY_8821C(x) \ + (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) +#define BITS_WMAC_TXMU_ACKPOLICY_8821C \ + (BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8821C(x) \ + ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8821C)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) & \ + BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) +#define BIT_SET_WMAC_TXMU_ACKPOLICY_8821C(x, v) \ + (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8821C(x) | \ + BIT_WMAC_TXMU_ACKPOLICY_8821C(v)) #define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C 1 #define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C 0x7 -#define BIT_WMAC_MU_BFEE_PORT_SEL_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) -#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) - +#define BIT_WMAC_MU_BFEE_PORT_SEL_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) +#define BITS_WMAC_MU_BFEE_PORT_SEL_8821C \ + (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8821C)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) & \ + BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8821C(x) | \ + BIT_WMAC_MU_BFEE_PORT_SEL_8821C(v)) #define BIT_WMAC_MU_BFEE_DIS_8821C BIT(0) @@ -10051,10 +16646,20 @@ #define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C 0 #define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C 0xff -#define BIT_WMAC_PAUSE_BB_CLR_TH_8821C(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) -#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8821C(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) - - +#define BIT_WMAC_PAUSE_BB_CLR_TH_8821C(x) \ + (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) +#define BITS_WMAC_PAUSE_BB_CLR_TH_8821C \ + (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8821C(x) \ + ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8821C)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) & \ + BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8821C(x, v) \ + (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8821C(x) | \ + BIT_WMAC_PAUSE_BB_CLR_TH_8821C(v)) /* 2 REG_WMAC_MU_ARB_8821C */ #define BIT_WMAC_ARB_HW_ADAPT_EN_8821C BIT(7) @@ -10062,26 +16667,51 @@ #define BIT_SHIFT_WMAC_ARB_SW_STATE_8821C 0 #define BIT_MASK_WMAC_ARB_SW_STATE_8821C 0x3f -#define BIT_WMAC_ARB_SW_STATE_8821C(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8821C) << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) -#define BIT_GET_WMAC_ARB_SW_STATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) & BIT_MASK_WMAC_ARB_SW_STATE_8821C) - - +#define BIT_WMAC_ARB_SW_STATE_8821C(x) \ + (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8821C) \ + << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) +#define BITS_WMAC_ARB_SW_STATE_8821C \ + (BIT_MASK_WMAC_ARB_SW_STATE_8821C << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) +#define BIT_CLEAR_WMAC_ARB_SW_STATE_8821C(x) \ + ((x) & (~BITS_WMAC_ARB_SW_STATE_8821C)) +#define BIT_GET_WMAC_ARB_SW_STATE_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) & \ + BIT_MASK_WMAC_ARB_SW_STATE_8821C) +#define BIT_SET_WMAC_ARB_SW_STATE_8821C(x, v) \ + (BIT_CLEAR_WMAC_ARB_SW_STATE_8821C(x) | BIT_WMAC_ARB_SW_STATE_8821C(v)) /* 2 REG_WMAC_MU_OPTION_8821C */ #define BIT_SHIFT_WMAC_MU_DBGSEL_8821C 5 #define BIT_MASK_WMAC_MU_DBGSEL_8821C 0x3 -#define BIT_WMAC_MU_DBGSEL_8821C(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8821C) << BIT_SHIFT_WMAC_MU_DBGSEL_8821C) -#define BIT_GET_WMAC_MU_DBGSEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8821C) & BIT_MASK_WMAC_MU_DBGSEL_8821C) - - +#define BIT_WMAC_MU_DBGSEL_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_DBGSEL_8821C) \ + << BIT_SHIFT_WMAC_MU_DBGSEL_8821C) +#define BITS_WMAC_MU_DBGSEL_8821C \ + (BIT_MASK_WMAC_MU_DBGSEL_8821C << BIT_SHIFT_WMAC_MU_DBGSEL_8821C) +#define BIT_CLEAR_WMAC_MU_DBGSEL_8821C(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8821C)) +#define BIT_GET_WMAC_MU_DBGSEL_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8821C) & \ + BIT_MASK_WMAC_MU_DBGSEL_8821C) +#define BIT_SET_WMAC_MU_DBGSEL_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_DBGSEL_8821C(x) | BIT_WMAC_MU_DBGSEL_8821C(v)) #define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C 0 #define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C 0x1f -#define BIT_WMAC_MU_CPRD_TIMEOUT_8821C(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) -#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) - - +#define BIT_WMAC_MU_CPRD_TIMEOUT_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) +#define BITS_WMAC_MU_CPRD_TIMEOUT_8821C \ + (BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) +#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8821C(x) \ + ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8821C)) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) & \ + BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) +#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8821C(x) | \ + BIT_WMAC_MU_CPRD_TIMEOUT_8821C(v)) /* 2 REG_WMAC_MU_BF_CTL_8821C */ #define BIT_WMAC_INVLD_BFPRT_CHK_8821C BIT(15) @@ -10089,33 +16719,66 @@ #define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C 12 #define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C 0x3 -#define BIT_WMAC_MU_BFRPTSEG_SEL_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) -#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) - - +#define BIT_WMAC_MU_BFRPTSEG_SEL_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) +#define BITS_WMAC_MU_BFRPTSEG_SEL_8821C \ + (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8821C)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) & \ + BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x) | \ + BIT_WMAC_MU_BFRPTSEG_SEL_8821C(v)) #define BIT_SHIFT_WMAC_MU_BF_MYAID_8821C 0 #define BIT_MASK_WMAC_MU_BF_MYAID_8821C 0xfff -#define BIT_WMAC_MU_BF_MYAID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8821C) << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) -#define BIT_GET_WMAC_MU_BF_MYAID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) & BIT_MASK_WMAC_MU_BF_MYAID_8821C) - - - -/* 2 REG_WMAC_MU_BIT_BFRPT_PARA_8821C */ +#define BIT_WMAC_MU_BF_MYAID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8821C) \ + << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) +#define BITS_WMAC_MU_BF_MYAID_8821C \ + (BIT_MASK_WMAC_MU_BF_MYAID_8821C << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BF_MYAID_8821C)) +#define BIT_GET_WMAC_MU_BF_MYAID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) & \ + BIT_MASK_WMAC_MU_BF_MYAID_8821C) +#define BIT_SET_WMAC_MU_BF_MYAID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x) | BIT_WMAC_MU_BF_MYAID_8821C(v)) + +/* 2 REG_WMAC_MU_BFRPT_PARA_8821C */ #define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C 12 #define BIT_MASK_BFRPT_PARA_USERID_SEL_8821C 0x7 -#define BIT_BFRPT_PARA_USERID_SEL_8821C(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) -#define BIT_GET_BFRPT_PARA_USERID_SEL_8821C(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) - - +#define BIT_BFRPT_PARA_USERID_SEL_8821C(x) \ + (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) +#define BITS_BFRPT_PARA_USERID_SEL_8821C \ + (BIT_MASK_BFRPT_PARA_USERID_SEL_8821C \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8821C(x) \ + ((x) & (~BITS_BFRPT_PARA_USERID_SEL_8821C)) +#define BIT_GET_BFRPT_PARA_USERID_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) & \ + BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) +#define BIT_SET_BFRPT_PARA_USERID_SEL_8821C(x, v) \ + (BIT_CLEAR_BFRPT_PARA_USERID_SEL_8821C(x) | \ + BIT_BFRPT_PARA_USERID_SEL_8821C(v)) #define BIT_SHIFT_BFRPT_PARA_8821C 0 #define BIT_MASK_BFRPT_PARA_8821C 0xfff -#define BIT_BFRPT_PARA_8821C(x) (((x) & BIT_MASK_BFRPT_PARA_8821C) << BIT_SHIFT_BFRPT_PARA_8821C) -#define BIT_GET_BFRPT_PARA_8821C(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8821C) & BIT_MASK_BFRPT_PARA_8821C) - - +#define BIT_BFRPT_PARA_8821C(x) \ + (((x) & BIT_MASK_BFRPT_PARA_8821C) << BIT_SHIFT_BFRPT_PARA_8821C) +#define BITS_BFRPT_PARA_8821C \ + (BIT_MASK_BFRPT_PARA_8821C << BIT_SHIFT_BFRPT_PARA_8821C) +#define BIT_CLEAR_BFRPT_PARA_8821C(x) ((x) & (~BITS_BFRPT_PARA_8821C)) +#define BIT_GET_BFRPT_PARA_8821C(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_8821C) & BIT_MASK_BFRPT_PARA_8821C) +#define BIT_SET_BFRPT_PARA_8821C(x, v) \ + (BIT_CLEAR_BFRPT_PARA_8821C(x) | BIT_BFRPT_PARA_8821C(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C */ #define BIT_STATUS_BFEE2_8821C BIT(10) @@ -10123,10 +16786,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C 0 #define BIT_MASK_WMAC_MU_BFEE2_AID_8821C 0x1ff -#define BIT_WMAC_MU_BFEE2_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) -#define BIT_GET_WMAC_MU_BFEE2_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C) - - +#define BIT_WMAC_MU_BFEE2_AID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) +#define BITS_WMAC_MU_BFEE2_AID_8821C \ + (BIT_MASK_WMAC_MU_BFEE2_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE2_AID_8821C)) +#define BIT_GET_WMAC_MU_BFEE2_AID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) & \ + BIT_MASK_WMAC_MU_BFEE2_AID_8821C) +#define BIT_SET_WMAC_MU_BFEE2_AID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE2_AID_8821C(x) | BIT_WMAC_MU_BFEE2_AID_8821C(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C */ #define BIT_STATUS_BFEE3_8821C BIT(10) @@ -10134,10 +16805,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C 0 #define BIT_MASK_WMAC_MU_BFEE3_AID_8821C 0x1ff -#define BIT_WMAC_MU_BFEE3_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) -#define BIT_GET_WMAC_MU_BFEE3_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C) - - +#define BIT_WMAC_MU_BFEE3_AID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) +#define BITS_WMAC_MU_BFEE3_AID_8821C \ + (BIT_MASK_WMAC_MU_BFEE3_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE3_AID_8821C)) +#define BIT_GET_WMAC_MU_BFEE3_AID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) & \ + BIT_MASK_WMAC_MU_BFEE3_AID_8821C) +#define BIT_SET_WMAC_MU_BFEE3_AID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE3_AID_8821C(x) | BIT_WMAC_MU_BFEE3_AID_8821C(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C */ #define BIT_STATUS_BFEE4_8821C BIT(10) @@ -10145,10 +16824,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C 0 #define BIT_MASK_WMAC_MU_BFEE4_AID_8821C 0x1ff -#define BIT_WMAC_MU_BFEE4_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) -#define BIT_GET_WMAC_MU_BFEE4_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C) - - +#define BIT_WMAC_MU_BFEE4_AID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) +#define BITS_WMAC_MU_BFEE4_AID_8821C \ + (BIT_MASK_WMAC_MU_BFEE4_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE4_AID_8821C)) +#define BIT_GET_WMAC_MU_BFEE4_AID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) & \ + BIT_MASK_WMAC_MU_BFEE4_AID_8821C) +#define BIT_SET_WMAC_MU_BFEE4_AID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE4_AID_8821C(x) | BIT_WMAC_MU_BFEE4_AID_8821C(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C */ #define BIT_BIT_STATUS_BFEE5_8821C BIT(10) @@ -10156,10 +16843,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C 0 #define BIT_MASK_WMAC_MU_BFEE5_AID_8821C 0x1ff -#define BIT_WMAC_MU_BFEE5_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) -#define BIT_GET_WMAC_MU_BFEE5_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C) - - +#define BIT_WMAC_MU_BFEE5_AID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) +#define BITS_WMAC_MU_BFEE5_AID_8821C \ + (BIT_MASK_WMAC_MU_BFEE5_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE5_AID_8821C)) +#define BIT_GET_WMAC_MU_BFEE5_AID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) & \ + BIT_MASK_WMAC_MU_BFEE5_AID_8821C) +#define BIT_SET_WMAC_MU_BFEE5_AID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE5_AID_8821C(x) | BIT_WMAC_MU_BFEE5_AID_8821C(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C */ #define BIT_STATUS_BFEE6_8821C BIT(10) @@ -10167,124 +16862,319 @@ #define BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C 0 #define BIT_MASK_WMAC_MU_BFEE6_AID_8821C 0x1ff -#define BIT_WMAC_MU_BFEE6_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) -#define BIT_GET_WMAC_MU_BFEE6_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C) - - +#define BIT_WMAC_MU_BFEE6_AID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) +#define BITS_WMAC_MU_BFEE6_AID_8821C \ + (BIT_MASK_WMAC_MU_BFEE6_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE6_AID_8821C)) +#define BIT_GET_WMAC_MU_BFEE6_AID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) & \ + BIT_MASK_WMAC_MU_BFEE6_AID_8821C) +#define BIT_SET_WMAC_MU_BFEE6_AID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE6_AID_8821C(x) | BIT_WMAC_MU_BFEE6_AID_8821C(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C */ -#define BIT_BIT_STATUS_BFEE4_8821C BIT(10) +#define BIT_STATUS_BFEE7_8821C BIT(10) #define BIT_WMAC_MU_BFEE7_EN_8821C BIT(9) #define BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C 0 #define BIT_MASK_WMAC_MU_BFEE7_AID_8821C 0x1ff -#define BIT_WMAC_MU_BFEE7_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) -#define BIT_GET_WMAC_MU_BFEE7_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C) - - +#define BIT_WMAC_MU_BFEE7_AID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) +#define BITS_WMAC_MU_BFEE7_AID_8821C \ + (BIT_MASK_WMAC_MU_BFEE7_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE7_AID_8821C)) +#define BIT_GET_WMAC_MU_BFEE7_AID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) & \ + BIT_MASK_WMAC_MU_BFEE7_AID_8821C) +#define BIT_SET_WMAC_MU_BFEE7_AID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE7_AID_8821C(x) | BIT_WMAC_MU_BFEE7_AID_8821C(v)) /* 2 REG_WMAC_BB_STOP_RX_COUNTER_8821C */ #define BIT_RST_ALL_COUNTER_8821C BIT(31) #define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C 16 #define BIT_MASK_ABORT_RX_VBON_COUNTER_8821C 0xff -#define BIT_ABORT_RX_VBON_COUNTER_8821C(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) -#define BIT_GET_ABORT_RX_VBON_COUNTER_8821C(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) - - +#define BIT_ABORT_RX_VBON_COUNTER_8821C(x) \ + (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) +#define BITS_ABORT_RX_VBON_COUNTER_8821C \ + (BIT_MASK_ABORT_RX_VBON_COUNTER_8821C \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8821C(x) \ + ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8821C)) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8821C(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) & \ + BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) +#define BIT_SET_ABORT_RX_VBON_COUNTER_8821C(x, v) \ + (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8821C(x) | \ + BIT_ABORT_RX_VBON_COUNTER_8821C(v)) #define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C 8 #define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C 0xff -#define BIT_ABORT_RX_RDRDY_COUNTER_8821C(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) -#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8821C(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) - - +#define BIT_ABORT_RX_RDRDY_COUNTER_8821C(x) \ + (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) +#define BITS_ABORT_RX_RDRDY_COUNTER_8821C \ + (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8821C(x) \ + ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8821C)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8821C(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) & \ + BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8821C(x, v) \ + (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8821C(x) | \ + BIT_ABORT_RX_RDRDY_COUNTER_8821C(v)) #define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C 0 #define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C 0xff -#define BIT_VBON_EARLY_FALLING_COUNTER_8821C(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) -#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8821C(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) - - +#define BIT_VBON_EARLY_FALLING_COUNTER_8821C(x) \ + (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) +#define BITS_VBON_EARLY_FALLING_COUNTER_8821C \ + (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8821C(x) \ + ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8821C)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8821C(x) \ + (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) & \ + BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8821C(x, v) \ + (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8821C(x) | \ + BIT_VBON_EARLY_FALLING_COUNTER_8821C(v)) /* 2 REG_WMAC_PLCP_MONITOR_8821C */ #define BIT_WMAC_PLCP_TRX_SEL_8821C BIT(31) #define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C 28 #define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C 0x7 -#define BIT_WMAC_PLCP_RDSIG_SEL_8821C(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) -#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) - - +#define BIT_WMAC_PLCP_RDSIG_SEL_8821C(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) +#define BITS_WMAC_PLCP_RDSIG_SEL_8821C \ + (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8821C(x) \ + ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8821C)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) & \ + BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8821C(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8821C(x) | \ + BIT_WMAC_PLCP_RDSIG_SEL_8821C(v)) #define BIT_SHIFT_WMAC_RATE_IDX_8821C 24 #define BIT_MASK_WMAC_RATE_IDX_8821C 0xf -#define BIT_WMAC_RATE_IDX_8821C(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8821C) << BIT_SHIFT_WMAC_RATE_IDX_8821C) -#define BIT_GET_WMAC_RATE_IDX_8821C(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8821C) & BIT_MASK_WMAC_RATE_IDX_8821C) - - +#define BIT_WMAC_RATE_IDX_8821C(x) \ + (((x) & BIT_MASK_WMAC_RATE_IDX_8821C) << BIT_SHIFT_WMAC_RATE_IDX_8821C) +#define BITS_WMAC_RATE_IDX_8821C \ + (BIT_MASK_WMAC_RATE_IDX_8821C << BIT_SHIFT_WMAC_RATE_IDX_8821C) +#define BIT_CLEAR_WMAC_RATE_IDX_8821C(x) ((x) & (~BITS_WMAC_RATE_IDX_8821C)) +#define BIT_GET_WMAC_RATE_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8821C) & BIT_MASK_WMAC_RATE_IDX_8821C) +#define BIT_SET_WMAC_RATE_IDX_8821C(x, v) \ + (BIT_CLEAR_WMAC_RATE_IDX_8821C(x) | BIT_WMAC_RATE_IDX_8821C(v)) #define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0 #define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8821C(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) -#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) - - +#define BIT_WMAC_PLCP_RDSIG_8821C(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) +#define BITS_WMAC_PLCP_RDSIG_8821C \ + (BIT_MASK_WMAC_PLCP_RDSIG_8821C << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8821C)) +#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8821C) +#define BIT_SET_WMAC_PLCP_RDSIG_8821C(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) | BIT_WMAC_PLCP_RDSIG_8821C(v)) /* 2 REG_WMAC_PLCP_MONITOR_MUTX_8821C */ #define BIT_WMAC_MUTX_IDX_8821C BIT(24) #define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0 #define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8821C(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) -#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) - +#define BIT_WMAC_PLCP_RDSIG_8821C(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) +#define BITS_WMAC_PLCP_RDSIG_8821C \ + (BIT_MASK_WMAC_PLCP_RDSIG_8821C << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8821C)) +#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8821C) +#define BIT_SET_WMAC_PLCP_RDSIG_8821C(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) | BIT_WMAC_PLCP_RDSIG_8821C(v)) +/* 2 REG_RSVD_8821C */ /* 2 REG_TRANSMIT_ADDRSS_0_8821C (TA0 REGISTER) */ -#define BIT_SHIFT_TA0_8821C 0 -#define BIT_MASK_TA0_8821C 0xffffffffffffL -#define BIT_TA0_8821C(x) (((x) & BIT_MASK_TA0_8821C) << BIT_SHIFT_TA0_8821C) -#define BIT_GET_TA0_8821C(x) (((x) >> BIT_SHIFT_TA0_8821C) & BIT_MASK_TA0_8821C) +#define BIT_SHIFT_TA0_V1_8821C 0 +#define BIT_MASK_TA0_V1_8821C 0xffffffffL +#define BIT_TA0_V1_8821C(x) \ + (((x) & BIT_MASK_TA0_V1_8821C) << BIT_SHIFT_TA0_V1_8821C) +#define BITS_TA0_V1_8821C (BIT_MASK_TA0_V1_8821C << BIT_SHIFT_TA0_V1_8821C) +#define BIT_CLEAR_TA0_V1_8821C(x) ((x) & (~BITS_TA0_V1_8821C)) +#define BIT_GET_TA0_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA0_V1_8821C) & BIT_MASK_TA0_V1_8821C) +#define BIT_SET_TA0_V1_8821C(x, v) \ + (BIT_CLEAR_TA0_V1_8821C(x) | BIT_TA0_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_0_H_8821C (TA0 REGISTER) */ + +#define BIT_SHIFT_TA0_H_V1_8821C 0 +#define BIT_MASK_TA0_H_V1_8821C 0xffff +#define BIT_TA0_H_V1_8821C(x) \ + (((x) & BIT_MASK_TA0_H_V1_8821C) << BIT_SHIFT_TA0_H_V1_8821C) +#define BITS_TA0_H_V1_8821C \ + (BIT_MASK_TA0_H_V1_8821C << BIT_SHIFT_TA0_H_V1_8821C) +#define BIT_CLEAR_TA0_H_V1_8821C(x) ((x) & (~BITS_TA0_H_V1_8821C)) +#define BIT_GET_TA0_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA0_H_V1_8821C) & BIT_MASK_TA0_H_V1_8821C) +#define BIT_SET_TA0_H_V1_8821C(x, v) \ + (BIT_CLEAR_TA0_H_V1_8821C(x) | BIT_TA0_H_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_1_8821C (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_V1_8821C 0 +#define BIT_MASK_TA1_V1_8821C 0xffffffffL +#define BIT_TA1_V1_8821C(x) \ + (((x) & BIT_MASK_TA1_V1_8821C) << BIT_SHIFT_TA1_V1_8821C) +#define BITS_TA1_V1_8821C (BIT_MASK_TA1_V1_8821C << BIT_SHIFT_TA1_V1_8821C) +#define BIT_CLEAR_TA1_V1_8821C(x) ((x) & (~BITS_TA1_V1_8821C)) +#define BIT_GET_TA1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA1_V1_8821C) & BIT_MASK_TA1_V1_8821C) +#define BIT_SET_TA1_V1_8821C(x, v) \ + (BIT_CLEAR_TA1_V1_8821C(x) | BIT_TA1_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_1_H_8821C (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_H_V1_8821C 0 +#define BIT_MASK_TA1_H_V1_8821C 0xffff +#define BIT_TA1_H_V1_8821C(x) \ + (((x) & BIT_MASK_TA1_H_V1_8821C) << BIT_SHIFT_TA1_H_V1_8821C) +#define BITS_TA1_H_V1_8821C \ + (BIT_MASK_TA1_H_V1_8821C << BIT_SHIFT_TA1_H_V1_8821C) +#define BIT_CLEAR_TA1_H_V1_8821C(x) ((x) & (~BITS_TA1_H_V1_8821C)) +#define BIT_GET_TA1_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA1_H_V1_8821C) & BIT_MASK_TA1_H_V1_8821C) +#define BIT_SET_TA1_H_V1_8821C(x, v) \ + (BIT_CLEAR_TA1_H_V1_8821C(x) | BIT_TA1_H_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_2_8821C (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_V1_8821C 0 +#define BIT_MASK_TA2_V1_8821C 0xffffffffL +#define BIT_TA2_V1_8821C(x) \ + (((x) & BIT_MASK_TA2_V1_8821C) << BIT_SHIFT_TA2_V1_8821C) +#define BITS_TA2_V1_8821C (BIT_MASK_TA2_V1_8821C << BIT_SHIFT_TA2_V1_8821C) +#define BIT_CLEAR_TA2_V1_8821C(x) ((x) & (~BITS_TA2_V1_8821C)) +#define BIT_GET_TA2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA2_V1_8821C) & BIT_MASK_TA2_V1_8821C) +#define BIT_SET_TA2_V1_8821C(x, v) \ + (BIT_CLEAR_TA2_V1_8821C(x) | BIT_TA2_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_2_H_8821C (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_H_V1_8821C 0 +#define BIT_MASK_TA2_H_V1_8821C 0xffff +#define BIT_TA2_H_V1_8821C(x) \ + (((x) & BIT_MASK_TA2_H_V1_8821C) << BIT_SHIFT_TA2_H_V1_8821C) +#define BITS_TA2_H_V1_8821C \ + (BIT_MASK_TA2_H_V1_8821C << BIT_SHIFT_TA2_H_V1_8821C) +#define BIT_CLEAR_TA2_H_V1_8821C(x) ((x) & (~BITS_TA2_H_V1_8821C)) +#define BIT_GET_TA2_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA2_H_V1_8821C) & BIT_MASK_TA2_H_V1_8821C) +#define BIT_SET_TA2_H_V1_8821C(x, v) \ + (BIT_CLEAR_TA2_H_V1_8821C(x) | BIT_TA2_H_V1_8821C(v)) +/* 2 REG_TRANSMIT_ADDRSS_3_8821C (TA3 REGISTER) */ +#define BIT_SHIFT_TA2_V1_8821C 0 +#define BIT_MASK_TA2_V1_8821C 0xffffffffL +#define BIT_TA2_V1_8821C(x) \ + (((x) & BIT_MASK_TA2_V1_8821C) << BIT_SHIFT_TA2_V1_8821C) +#define BITS_TA2_V1_8821C (BIT_MASK_TA2_V1_8821C << BIT_SHIFT_TA2_V1_8821C) +#define BIT_CLEAR_TA2_V1_8821C(x) ((x) & (~BITS_TA2_V1_8821C)) +#define BIT_GET_TA2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA2_V1_8821C) & BIT_MASK_TA2_V1_8821C) +#define BIT_SET_TA2_V1_8821C(x, v) \ + (BIT_CLEAR_TA2_V1_8821C(x) | BIT_TA2_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_3_H_8821C (TA3 REGISTER) */ + +#define BIT_SHIFT_TA3_H_V1_8821C 0 +#define BIT_MASK_TA3_H_V1_8821C 0xffff +#define BIT_TA3_H_V1_8821C(x) \ + (((x) & BIT_MASK_TA3_H_V1_8821C) << BIT_SHIFT_TA3_H_V1_8821C) +#define BITS_TA3_H_V1_8821C \ + (BIT_MASK_TA3_H_V1_8821C << BIT_SHIFT_TA3_H_V1_8821C) +#define BIT_CLEAR_TA3_H_V1_8821C(x) ((x) & (~BITS_TA3_H_V1_8821C)) +#define BIT_GET_TA3_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA3_H_V1_8821C) & BIT_MASK_TA3_H_V1_8821C) +#define BIT_SET_TA3_H_V1_8821C(x, v) \ + (BIT_CLEAR_TA3_H_V1_8821C(x) | BIT_TA3_H_V1_8821C(v)) -/* 2 REG_TRANSMIT_ADDRSS_1_8821C (TA1 REGISTER) */ +/* 2 REG_TRANSMIT_ADDRSS_4_8821C (TA4 REGISTER) */ -#define BIT_SHIFT_TA1_8821C 0 -#define BIT_MASK_TA1_8821C 0xffffffffffffL -#define BIT_TA1_8821C(x) (((x) & BIT_MASK_TA1_8821C) << BIT_SHIFT_TA1_8821C) -#define BIT_GET_TA1_8821C(x) (((x) >> BIT_SHIFT_TA1_8821C) & BIT_MASK_TA1_8821C) +#define BIT_SHIFT_TA4_V1_8821C 0 +#define BIT_MASK_TA4_V1_8821C 0xffffffffL +#define BIT_TA4_V1_8821C(x) \ + (((x) & BIT_MASK_TA4_V1_8821C) << BIT_SHIFT_TA4_V1_8821C) +#define BITS_TA4_V1_8821C (BIT_MASK_TA4_V1_8821C << BIT_SHIFT_TA4_V1_8821C) +#define BIT_CLEAR_TA4_V1_8821C(x) ((x) & (~BITS_TA4_V1_8821C)) +#define BIT_GET_TA4_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA4_V1_8821C) & BIT_MASK_TA4_V1_8821C) +#define BIT_SET_TA4_V1_8821C(x, v) \ + (BIT_CLEAR_TA4_V1_8821C(x) | BIT_TA4_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_4_H_8821C (TA4 REGISTER) */ + +#define BIT_SHIFT_TA4_H_V1_8821C 0 +#define BIT_MASK_TA4_H_V1_8821C 0xffff +#define BIT_TA4_H_V1_8821C(x) \ + (((x) & BIT_MASK_TA4_H_V1_8821C) << BIT_SHIFT_TA4_H_V1_8821C) +#define BITS_TA4_H_V1_8821C \ + (BIT_MASK_TA4_H_V1_8821C << BIT_SHIFT_TA4_H_V1_8821C) +#define BIT_CLEAR_TA4_H_V1_8821C(x) ((x) & (~BITS_TA4_H_V1_8821C)) +#define BIT_GET_TA4_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA4_H_V1_8821C) & BIT_MASK_TA4_H_V1_8821C) +#define BIT_SET_TA4_H_V1_8821C(x, v) \ + (BIT_CLEAR_TA4_H_V1_8821C(x) | BIT_TA4_H_V1_8821C(v)) +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ -/* 2 REG_TRANSMIT_ADDRSS_2_8821C (TA2 REGISTER) */ +/* 2 REG_RSVD_8821C */ -#define BIT_SHIFT_TA2_8821C 0 -#define BIT_MASK_TA2_8821C 0xffffffffffffL -#define BIT_TA2_8821C(x) (((x) & BIT_MASK_TA2_8821C) << BIT_SHIFT_TA2_8821C) -#define BIT_GET_TA2_8821C(x) (((x) >> BIT_SHIFT_TA2_8821C) & BIT_MASK_TA2_8821C) +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ -/* 2 REG_TRANSMIT_ADDRSS_3_8821C (TA3 REGISTER) */ +/* 2 REG_RSVD_8821C */ -#define BIT_SHIFT_TA3_8821C 0 -#define BIT_MASK_TA3_8821C 0xffffffffffffL -#define BIT_TA3_8821C(x) (((x) & BIT_MASK_TA3_8821C) << BIT_SHIFT_TA3_8821C) -#define BIT_GET_TA3_8821C(x) (((x) >> BIT_SHIFT_TA3_8821C) & BIT_MASK_TA3_8821C) +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ -/* 2 REG_TRANSMIT_ADDRSS_4_8821C (TA4 REGISTER) */ +/* 2 REG_RSVD_8821C */ -#define BIT_SHIFT_TA4_8821C 0 -#define BIT_MASK_TA4_8821C 0xffffffffffffL -#define BIT_TA4_8821C(x) (((x) & BIT_MASK_TA4_8821C) << BIT_SHIFT_TA4_8821C) -#define BIT_GET_TA4_8821C(x) (((x) >> BIT_SHIFT_TA4_8821C) & BIT_MASK_TA4_8821C) +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -10292,62 +17182,98 @@ #define BIT_SHIFT_MACID1_0_8821C 0 #define BIT_MASK_MACID1_0_8821C 0xffffffffL -#define BIT_MACID1_0_8821C(x) (((x) & BIT_MASK_MACID1_0_8821C) << BIT_SHIFT_MACID1_0_8821C) -#define BIT_GET_MACID1_0_8821C(x) (((x) >> BIT_SHIFT_MACID1_0_8821C) & BIT_MASK_MACID1_0_8821C) - - +#define BIT_MACID1_0_8821C(x) \ + (((x) & BIT_MASK_MACID1_0_8821C) << BIT_SHIFT_MACID1_0_8821C) +#define BITS_MACID1_0_8821C \ + (BIT_MASK_MACID1_0_8821C << BIT_SHIFT_MACID1_0_8821C) +#define BIT_CLEAR_MACID1_0_8821C(x) ((x) & (~BITS_MACID1_0_8821C)) +#define BIT_GET_MACID1_0_8821C(x) \ + (((x) >> BIT_SHIFT_MACID1_0_8821C) & BIT_MASK_MACID1_0_8821C) +#define BIT_SET_MACID1_0_8821C(x, v) \ + (BIT_CLEAR_MACID1_0_8821C(x) | BIT_MACID1_0_8821C(v)) /* 2 REG_MACID1_1_8821C */ #define BIT_SHIFT_MACID1_1_8821C 0 #define BIT_MASK_MACID1_1_8821C 0xffff -#define BIT_MACID1_1_8821C(x) (((x) & BIT_MASK_MACID1_1_8821C) << BIT_SHIFT_MACID1_1_8821C) -#define BIT_GET_MACID1_1_8821C(x) (((x) >> BIT_SHIFT_MACID1_1_8821C) & BIT_MASK_MACID1_1_8821C) - - +#define BIT_MACID1_1_8821C(x) \ + (((x) & BIT_MASK_MACID1_1_8821C) << BIT_SHIFT_MACID1_1_8821C) +#define BITS_MACID1_1_8821C \ + (BIT_MASK_MACID1_1_8821C << BIT_SHIFT_MACID1_1_8821C) +#define BIT_CLEAR_MACID1_1_8821C(x) ((x) & (~BITS_MACID1_1_8821C)) +#define BIT_GET_MACID1_1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID1_1_8821C) & BIT_MASK_MACID1_1_8821C) +#define BIT_SET_MACID1_1_8821C(x, v) \ + (BIT_CLEAR_MACID1_1_8821C(x) | BIT_MACID1_1_8821C(v)) /* 2 REG_BSSID1_8821C */ #define BIT_SHIFT_BSSID1_0_8821C 0 #define BIT_MASK_BSSID1_0_8821C 0xffffffffL -#define BIT_BSSID1_0_8821C(x) (((x) & BIT_MASK_BSSID1_0_8821C) << BIT_SHIFT_BSSID1_0_8821C) -#define BIT_GET_BSSID1_0_8821C(x) (((x) >> BIT_SHIFT_BSSID1_0_8821C) & BIT_MASK_BSSID1_0_8821C) - - +#define BIT_BSSID1_0_8821C(x) \ + (((x) & BIT_MASK_BSSID1_0_8821C) << BIT_SHIFT_BSSID1_0_8821C) +#define BITS_BSSID1_0_8821C \ + (BIT_MASK_BSSID1_0_8821C << BIT_SHIFT_BSSID1_0_8821C) +#define BIT_CLEAR_BSSID1_0_8821C(x) ((x) & (~BITS_BSSID1_0_8821C)) +#define BIT_GET_BSSID1_0_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID1_0_8821C) & BIT_MASK_BSSID1_0_8821C) +#define BIT_SET_BSSID1_0_8821C(x, v) \ + (BIT_CLEAR_BSSID1_0_8821C(x) | BIT_BSSID1_0_8821C(v)) /* 2 REG_BSSID1_1_8821C */ #define BIT_SHIFT_BSSID1_1_8821C 0 #define BIT_MASK_BSSID1_1_8821C 0xffff -#define BIT_BSSID1_1_8821C(x) (((x) & BIT_MASK_BSSID1_1_8821C) << BIT_SHIFT_BSSID1_1_8821C) -#define BIT_GET_BSSID1_1_8821C(x) (((x) >> BIT_SHIFT_BSSID1_1_8821C) & BIT_MASK_BSSID1_1_8821C) - - +#define BIT_BSSID1_1_8821C(x) \ + (((x) & BIT_MASK_BSSID1_1_8821C) << BIT_SHIFT_BSSID1_1_8821C) +#define BITS_BSSID1_1_8821C \ + (BIT_MASK_BSSID1_1_8821C << BIT_SHIFT_BSSID1_1_8821C) +#define BIT_CLEAR_BSSID1_1_8821C(x) ((x) & (~BITS_BSSID1_1_8821C)) +#define BIT_GET_BSSID1_1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID1_1_8821C) & BIT_MASK_BSSID1_1_8821C) +#define BIT_SET_BSSID1_1_8821C(x, v) \ + (BIT_CLEAR_BSSID1_1_8821C(x) | BIT_BSSID1_1_8821C(v)) /* 2 REG_BCN_PSR_RPT1_8821C */ #define BIT_SHIFT_DTIM_CNT1_8821C 24 #define BIT_MASK_DTIM_CNT1_8821C 0xff -#define BIT_DTIM_CNT1_8821C(x) (((x) & BIT_MASK_DTIM_CNT1_8821C) << BIT_SHIFT_DTIM_CNT1_8821C) -#define BIT_GET_DTIM_CNT1_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8821C) & BIT_MASK_DTIM_CNT1_8821C) - - +#define BIT_DTIM_CNT1_8821C(x) \ + (((x) & BIT_MASK_DTIM_CNT1_8821C) << BIT_SHIFT_DTIM_CNT1_8821C) +#define BITS_DTIM_CNT1_8821C \ + (BIT_MASK_DTIM_CNT1_8821C << BIT_SHIFT_DTIM_CNT1_8821C) +#define BIT_CLEAR_DTIM_CNT1_8821C(x) ((x) & (~BITS_DTIM_CNT1_8821C)) +#define BIT_GET_DTIM_CNT1_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT1_8821C) & BIT_MASK_DTIM_CNT1_8821C) +#define BIT_SET_DTIM_CNT1_8821C(x, v) \ + (BIT_CLEAR_DTIM_CNT1_8821C(x) | BIT_DTIM_CNT1_8821C(v)) #define BIT_SHIFT_DTIM_PERIOD1_8821C 16 #define BIT_MASK_DTIM_PERIOD1_8821C 0xff -#define BIT_DTIM_PERIOD1_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD1_8821C) << BIT_SHIFT_DTIM_PERIOD1_8821C) -#define BIT_GET_DTIM_PERIOD1_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8821C) & BIT_MASK_DTIM_PERIOD1_8821C) - +#define BIT_DTIM_PERIOD1_8821C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD1_8821C) << BIT_SHIFT_DTIM_PERIOD1_8821C) +#define BITS_DTIM_PERIOD1_8821C \ + (BIT_MASK_DTIM_PERIOD1_8821C << BIT_SHIFT_DTIM_PERIOD1_8821C) +#define BIT_CLEAR_DTIM_PERIOD1_8821C(x) ((x) & (~BITS_DTIM_PERIOD1_8821C)) +#define BIT_GET_DTIM_PERIOD1_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD1_8821C) & BIT_MASK_DTIM_PERIOD1_8821C) +#define BIT_SET_DTIM_PERIOD1_8821C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD1_8821C(x) | BIT_DTIM_PERIOD1_8821C(v)) #define BIT_DTIM1_8821C BIT(15) #define BIT_TIM1_8821C BIT(14) #define BIT_SHIFT_PS_AID_1_8821C 0 #define BIT_MASK_PS_AID_1_8821C 0x7ff -#define BIT_PS_AID_1_8821C(x) (((x) & BIT_MASK_PS_AID_1_8821C) << BIT_SHIFT_PS_AID_1_8821C) -#define BIT_GET_PS_AID_1_8821C(x) (((x) >> BIT_SHIFT_PS_AID_1_8821C) & BIT_MASK_PS_AID_1_8821C) - - +#define BIT_PS_AID_1_8821C(x) \ + (((x) & BIT_MASK_PS_AID_1_8821C) << BIT_SHIFT_PS_AID_1_8821C) +#define BITS_PS_AID_1_8821C \ + (BIT_MASK_PS_AID_1_8821C << BIT_SHIFT_PS_AID_1_8821C) +#define BIT_CLEAR_PS_AID_1_8821C(x) ((x) & (~BITS_PS_AID_1_8821C)) +#define BIT_GET_PS_AID_1_8821C(x) \ + (((x) >> BIT_SHIFT_PS_AID_1_8821C) & BIT_MASK_PS_AID_1_8821C) +#define BIT_SET_PS_AID_1_8821C(x, v) \ + (BIT_CLEAR_PS_AID_1_8821C(x) | BIT_PS_AID_1_8821C(v)) /* 2 REG_ASSOCIATED_BFMEE_SEL_8821C */ #define BIT_TXUSER_ID1_8821C BIT(25) @@ -10355,39 +17281,73 @@ #define BIT_SHIFT_AID1_8821C 16 #define BIT_MASK_AID1_8821C 0x1ff #define BIT_AID1_8821C(x) (((x) & BIT_MASK_AID1_8821C) << BIT_SHIFT_AID1_8821C) -#define BIT_GET_AID1_8821C(x) (((x) >> BIT_SHIFT_AID1_8821C) & BIT_MASK_AID1_8821C) - +#define BITS_AID1_8821C (BIT_MASK_AID1_8821C << BIT_SHIFT_AID1_8821C) +#define BIT_CLEAR_AID1_8821C(x) ((x) & (~BITS_AID1_8821C)) +#define BIT_GET_AID1_8821C(x) \ + (((x) >> BIT_SHIFT_AID1_8821C) & BIT_MASK_AID1_8821C) +#define BIT_SET_AID1_8821C(x, v) (BIT_CLEAR_AID1_8821C(x) | BIT_AID1_8821C(v)) #define BIT_TXUSER_ID0_8821C BIT(9) #define BIT_SHIFT_AID0_8821C 0 #define BIT_MASK_AID0_8821C 0x1ff #define BIT_AID0_8821C(x) (((x) & BIT_MASK_AID0_8821C) << BIT_SHIFT_AID0_8821C) -#define BIT_GET_AID0_8821C(x) (((x) >> BIT_SHIFT_AID0_8821C) & BIT_MASK_AID0_8821C) - - +#define BITS_AID0_8821C (BIT_MASK_AID0_8821C << BIT_SHIFT_AID0_8821C) +#define BIT_CLEAR_AID0_8821C(x) ((x) & (~BITS_AID0_8821C)) +#define BIT_GET_AID0_8821C(x) \ + (((x) >> BIT_SHIFT_AID0_8821C) & BIT_MASK_AID0_8821C) +#define BIT_SET_AID0_8821C(x, v) (BIT_CLEAR_AID0_8821C(x) | BIT_AID0_8821C(v)) /* 2 REG_SND_PTCL_CTRL_8821C */ #define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C 24 #define BIT_MASK_NDP_RX_STANDBY_TIMER_8821C 0xff -#define BIT_NDP_RX_STANDBY_TIMER_8821C(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) -#define BIT_GET_NDP_RX_STANDBY_TIMER_8821C(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) - - +#define BIT_NDP_RX_STANDBY_TIMER_8821C(x) \ + (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) +#define BITS_NDP_RX_STANDBY_TIMER_8821C \ + (BIT_MASK_NDP_RX_STANDBY_TIMER_8821C \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8821C(x) \ + ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8821C)) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8821C(x) \ + (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) & \ + BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) +#define BIT_SET_NDP_RX_STANDBY_TIMER_8821C(x, v) \ + (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8821C(x) | \ + BIT_NDP_RX_STANDBY_TIMER_8821C(v)) #define BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C 16 #define BIT_MASK_CSI_RPT_OFFSET_HT_8821C 0xff -#define BIT_CSI_RPT_OFFSET_HT_8821C(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) -#define BIT_GET_CSI_RPT_OFFSET_HT_8821C(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C) - - +#define BIT_CSI_RPT_OFFSET_HT_8821C(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C) \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) +#define BITS_CSI_RPT_OFFSET_HT_8821C \ + (BIT_MASK_CSI_RPT_OFFSET_HT_8821C << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8821C(x) \ + ((x) & (~BITS_CSI_RPT_OFFSET_HT_8821C)) +#define BIT_GET_CSI_RPT_OFFSET_HT_8821C(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) & \ + BIT_MASK_CSI_RPT_OFFSET_HT_8821C) +#define BIT_SET_CSI_RPT_OFFSET_HT_8821C(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT_8821C(x) | BIT_CSI_RPT_OFFSET_HT_8821C(v)) #define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C 8 #define BIT_MASK_R_WMAC_VHT_CATEGORY_8821C 0xff -#define BIT_R_WMAC_VHT_CATEGORY_8821C(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) -#define BIT_GET_R_WMAC_VHT_CATEGORY_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) - +#define BIT_R_WMAC_VHT_CATEGORY_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) \ + << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) +#define BITS_R_WMAC_VHT_CATEGORY_8821C \ + (BIT_MASK_R_WMAC_VHT_CATEGORY_8821C \ + << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) +#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_8821C(x) \ + ((x) & (~BITS_R_WMAC_VHT_CATEGORY_8821C)) +#define BIT_GET_R_WMAC_VHT_CATEGORY_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) & \ + BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) +#define BIT_SET_R_WMAC_VHT_CATEGORY_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_VHT_CATEGORY_8821C(x) | \ + BIT_R_WMAC_VHT_CATEGORY_8821C(v)) #define BIT_R_WMAC_USE_NSTS_8821C BIT(7) #define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8821C BIT(6) @@ -10407,24 +17367,54 @@ #define BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C 6 #define BIT_MASK_R_WMAC_NSARP_MODEN_8821C 0x3 -#define BIT_R_WMAC_NSARP_MODEN_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) -#define BIT_GET_R_WMAC_NSARP_MODEN_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C) - - +#define BIT_R_WMAC_NSARP_MODEN_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C) \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) +#define BITS_R_WMAC_NSARP_MODEN_8821C \ + (BIT_MASK_R_WMAC_NSARP_MODEN_8821C \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8821C(x) \ + ((x) & (~BITS_R_WMAC_NSARP_MODEN_8821C)) +#define BIT_GET_R_WMAC_NSARP_MODEN_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) & \ + BIT_MASK_R_WMAC_NSARP_MODEN_8821C) +#define BIT_SET_R_WMAC_NSARP_MODEN_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_MODEN_8821C(x) | \ + BIT_R_WMAC_NSARP_MODEN_8821C(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C 4 #define BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C 0x3 -#define BIT_R_WMAC_NSARP_RSPFTP_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) -#define BIT_GET_R_WMAC_NSARP_RSPFTP_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) - - +#define BIT_R_WMAC_NSARP_RSPFTP_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) +#define BITS_R_WMAC_NSARP_RSPFTP_8821C \ + (BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8821C(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8821C)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) & \ + BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) +#define BIT_SET_R_WMAC_NSARP_RSPFTP_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8821C(x) | \ + BIT_R_WMAC_NSARP_RSPFTP_8821C(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C 0 #define BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C 0xf -#define BIT_R_WMAC_NSARP_RSPSEC_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) -#define BIT_GET_R_WMAC_NSARP_RSPSEC_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) - - +#define BIT_R_WMAC_NSARP_RSPSEC_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) +#define BITS_R_WMAC_NSARP_RSPSEC_8821C \ + (BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8821C(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8821C)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) & \ + BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) +#define BIT_SET_R_WMAC_NSARP_RSPSEC_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8821C(x) | \ + BIT_R_WMAC_NSARP_RSPSEC_8821C(v)) /* 2 REG_NS_ARP_INFO_8821C */ #define BIT_REQ_IS_MCNS_8821C BIT(23) @@ -10435,78 +17425,158 @@ #define BIT_SHIFT_EXPRSP_SECTYPE_8821C 16 #define BIT_MASK_EXPRSP_SECTYPE_8821C 0x7 -#define BIT_EXPRSP_SECTYPE_8821C(x) (((x) & BIT_MASK_EXPRSP_SECTYPE_8821C) << BIT_SHIFT_EXPRSP_SECTYPE_8821C) -#define BIT_GET_EXPRSP_SECTYPE_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8821C) & BIT_MASK_EXPRSP_SECTYPE_8821C) - - +#define BIT_EXPRSP_SECTYPE_8821C(x) \ + (((x) & BIT_MASK_EXPRSP_SECTYPE_8821C) \ + << BIT_SHIFT_EXPRSP_SECTYPE_8821C) +#define BITS_EXPRSP_SECTYPE_8821C \ + (BIT_MASK_EXPRSP_SECTYPE_8821C << BIT_SHIFT_EXPRSP_SECTYPE_8821C) +#define BIT_CLEAR_EXPRSP_SECTYPE_8821C(x) ((x) & (~BITS_EXPRSP_SECTYPE_8821C)) +#define BIT_GET_EXPRSP_SECTYPE_8821C(x) \ + (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8821C) & \ + BIT_MASK_EXPRSP_SECTYPE_8821C) +#define BIT_SET_EXPRSP_SECTYPE_8821C(x, v) \ + (BIT_CLEAR_EXPRSP_SECTYPE_8821C(x) | BIT_EXPRSP_SECTYPE_8821C(v)) #define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C 8 #define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C 0xff -#define BIT_EXPRSP_CHKSM_7_TO_0_8821C(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) -#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) - - +#define BIT_EXPRSP_CHKSM_7_TO_0_8821C(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) +#define BITS_EXPRSP_CHKSM_7_TO_0_8821C \ + (BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) +#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8821C(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8821C)) +#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8821C(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) & \ + BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) +#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8821C(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8821C(x) | \ + BIT_EXPRSP_CHKSM_7_TO_0_8821C(v)) #define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C 0 #define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C 0xff -#define BIT_EXPRSP_CHKSM_15_TO_8_8821C(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) -#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) - - +#define BIT_EXPRSP_CHKSM_15_TO_8_8821C(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) +#define BITS_EXPRSP_CHKSM_15_TO_8_8821C \ + (BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) +#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8821C(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8821C)) +#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8821C(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) & \ + BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) +#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8821C(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8821C(x) | \ + BIT_EXPRSP_CHKSM_15_TO_8_8821C(v)) /* 2 REG_BEAMFORMING_INFO_NSARP_V1_8821C */ #define BIT_SHIFT_WMAC_ARPIP_8821C 0 #define BIT_MASK_WMAC_ARPIP_8821C 0xffffffffL -#define BIT_WMAC_ARPIP_8821C(x) (((x) & BIT_MASK_WMAC_ARPIP_8821C) << BIT_SHIFT_WMAC_ARPIP_8821C) -#define BIT_GET_WMAC_ARPIP_8821C(x) (((x) >> BIT_SHIFT_WMAC_ARPIP_8821C) & BIT_MASK_WMAC_ARPIP_8821C) - - +#define BIT_WMAC_ARPIP_8821C(x) \ + (((x) & BIT_MASK_WMAC_ARPIP_8821C) << BIT_SHIFT_WMAC_ARPIP_8821C) +#define BITS_WMAC_ARPIP_8821C \ + (BIT_MASK_WMAC_ARPIP_8821C << BIT_SHIFT_WMAC_ARPIP_8821C) +#define BIT_CLEAR_WMAC_ARPIP_8821C(x) ((x) & (~BITS_WMAC_ARPIP_8821C)) +#define BIT_GET_WMAC_ARPIP_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_ARPIP_8821C) & BIT_MASK_WMAC_ARPIP_8821C) +#define BIT_SET_WMAC_ARPIP_8821C(x, v) \ + (BIT_CLEAR_WMAC_ARPIP_8821C(x) | BIT_WMAC_ARPIP_8821C(v)) /* 2 REG_BEAMFORMING_INFO_NSARP_8821C */ #define BIT_SHIFT_BEAMFORMING_INFO_8821C 0 #define BIT_MASK_BEAMFORMING_INFO_8821C 0xffffffffL -#define BIT_BEAMFORMING_INFO_8821C(x) (((x) & BIT_MASK_BEAMFORMING_INFO_8821C) << BIT_SHIFT_BEAMFORMING_INFO_8821C) -#define BIT_GET_BEAMFORMING_INFO_8821C(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8821C) & BIT_MASK_BEAMFORMING_INFO_8821C) - - +#define BIT_BEAMFORMING_INFO_8821C(x) \ + (((x) & BIT_MASK_BEAMFORMING_INFO_8821C) \ + << BIT_SHIFT_BEAMFORMING_INFO_8821C) +#define BITS_BEAMFORMING_INFO_8821C \ + (BIT_MASK_BEAMFORMING_INFO_8821C << BIT_SHIFT_BEAMFORMING_INFO_8821C) +#define BIT_CLEAR_BEAMFORMING_INFO_8821C(x) \ + ((x) & (~BITS_BEAMFORMING_INFO_8821C)) +#define BIT_GET_BEAMFORMING_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8821C) & \ + BIT_MASK_BEAMFORMING_INFO_8821C) +#define BIT_SET_BEAMFORMING_INFO_8821C(x, v) \ + (BIT_CLEAR_BEAMFORMING_INFO_8821C(x) | BIT_BEAMFORMING_INFO_8821C(v)) /* 2 REG_IPV6_8821C */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_0_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) - - +#define BIT_R_WMAC_IPV6_MYIPAD_0_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) +#define BITS_R_WMAC_IPV6_MYIPAD_0_8821C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8821C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8821C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8821C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_0_8821C(v)) /* 2 REG_IPV6_1_8821C */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_1_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) - - +#define BIT_R_WMAC_IPV6_MYIPAD_1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) +#define BITS_R_WMAC_IPV6_MYIPAD_1_8821C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8821C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8821C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8821C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_1_8821C(v)) /* 2 REG_IPV6_2_8821C */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_2_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) - - +#define BIT_R_WMAC_IPV6_MYIPAD_2_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) +#define BITS_R_WMAC_IPV6_MYIPAD_2_8821C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8821C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8821C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8821C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_2_8821C(v)) /* 2 REG_IPV6_3_8821C */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_3_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) - - +#define BIT_R_WMAC_IPV6_MYIPAD_3_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) +#define BITS_R_WMAC_IPV6_MYIPAD_3_8821C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8821C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8821C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8821C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_3_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -10520,17 +17590,37 @@ #define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C 4 #define BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C 0xf -#define BIT_R_WMAC_CTX_SUBTYPE_8821C(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) -#define BIT_GET_R_WMAC_CTX_SUBTYPE_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) - - +#define BIT_R_WMAC_CTX_SUBTYPE_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) +#define BITS_R_WMAC_CTX_SUBTYPE_8821C \ + (BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8821C(x) \ + ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8821C)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) & \ + BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) +#define BIT_SET_R_WMAC_CTX_SUBTYPE_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8821C(x) | \ + BIT_R_WMAC_CTX_SUBTYPE_8821C(v)) #define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C 0 #define BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C 0xf -#define BIT_R_WMAC_RTX_SUBTYPE_8821C(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) -#define BIT_GET_R_WMAC_RTX_SUBTYPE_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) - - +#define BIT_R_WMAC_RTX_SUBTYPE_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) +#define BITS_R_WMAC_RTX_SUBTYPE_8821C \ + (BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8821C(x) \ + ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8821C)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) & \ + BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) +#define BIT_SET_R_WMAC_RTX_SUBTYPE_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8821C(x) | \ + BIT_R_WMAC_RTX_SUBTYPE_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -10546,10 +17636,14 @@ #define BIT_SHIFT_TIMER_8821C 0 #define BIT_MASK_TIMER_8821C 0xff -#define BIT_TIMER_8821C(x) (((x) & BIT_MASK_TIMER_8821C) << BIT_SHIFT_TIMER_8821C) -#define BIT_GET_TIMER_8821C(x) (((x) >> BIT_SHIFT_TIMER_8821C) & BIT_MASK_TIMER_8821C) - - +#define BIT_TIMER_8821C(x) \ + (((x) & BIT_MASK_TIMER_8821C) << BIT_SHIFT_TIMER_8821C) +#define BITS_TIMER_8821C (BIT_MASK_TIMER_8821C << BIT_SHIFT_TIMER_8821C) +#define BIT_CLEAR_TIMER_8821C(x) ((x) & (~BITS_TIMER_8821C)) +#define BIT_GET_TIMER_8821C(x) \ + (((x) >> BIT_SHIFT_TIMER_8821C) & BIT_MASK_TIMER_8821C) +#define BIT_SET_TIMER_8821C(x, v) \ + (BIT_CLEAR_TIMER_8821C(x) | BIT_TIMER_8821C(v)) /* 2 REG_BT_COEX_8821C */ #define BIT_R_GNT_BT_RFC_SW_8821C BIT(12) @@ -10560,26 +17654,43 @@ #define BIT_SHIFT_R_BT_CNT_THR_8821C 0 #define BIT_MASK_R_BT_CNT_THR_8821C 0xff -#define BIT_R_BT_CNT_THR_8821C(x) (((x) & BIT_MASK_R_BT_CNT_THR_8821C) << BIT_SHIFT_R_BT_CNT_THR_8821C) -#define BIT_GET_R_BT_CNT_THR_8821C(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8821C) & BIT_MASK_R_BT_CNT_THR_8821C) - - +#define BIT_R_BT_CNT_THR_8821C(x) \ + (((x) & BIT_MASK_R_BT_CNT_THR_8821C) << BIT_SHIFT_R_BT_CNT_THR_8821C) +#define BITS_R_BT_CNT_THR_8821C \ + (BIT_MASK_R_BT_CNT_THR_8821C << BIT_SHIFT_R_BT_CNT_THR_8821C) +#define BIT_CLEAR_R_BT_CNT_THR_8821C(x) ((x) & (~BITS_R_BT_CNT_THR_8821C)) +#define BIT_GET_R_BT_CNT_THR_8821C(x) \ + (((x) >> BIT_SHIFT_R_BT_CNT_THR_8821C) & BIT_MASK_R_BT_CNT_THR_8821C) +#define BIT_SET_R_BT_CNT_THR_8821C(x, v) \ + (BIT_CLEAR_R_BT_CNT_THR_8821C(x) | BIT_R_BT_CNT_THR_8821C(v)) /* 2 REG_WLAN_ACT_MASK_CTRL_8821C */ #define BIT_SHIFT_RXMYRTS_NAV_V1_8821C 8 #define BIT_MASK_RXMYRTS_NAV_V1_8821C 0xff -#define BIT_RXMYRTS_NAV_V1_8821C(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8821C) << BIT_SHIFT_RXMYRTS_NAV_V1_8821C) -#define BIT_GET_RXMYRTS_NAV_V1_8821C(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8821C) & BIT_MASK_RXMYRTS_NAV_V1_8821C) - - +#define BIT_RXMYRTS_NAV_V1_8821C(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_V1_8821C) \ + << BIT_SHIFT_RXMYRTS_NAV_V1_8821C) +#define BITS_RXMYRTS_NAV_V1_8821C \ + (BIT_MASK_RXMYRTS_NAV_V1_8821C << BIT_SHIFT_RXMYRTS_NAV_V1_8821C) +#define BIT_CLEAR_RXMYRTS_NAV_V1_8821C(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8821C)) +#define BIT_GET_RXMYRTS_NAV_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8821C) & \ + BIT_MASK_RXMYRTS_NAV_V1_8821C) +#define BIT_SET_RXMYRTS_NAV_V1_8821C(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_V1_8821C(x) | BIT_RXMYRTS_NAV_V1_8821C(v)) #define BIT_SHIFT_RTSRST_V1_8821C 0 #define BIT_MASK_RTSRST_V1_8821C 0xff -#define BIT_RTSRST_V1_8821C(x) (((x) & BIT_MASK_RTSRST_V1_8821C) << BIT_SHIFT_RTSRST_V1_8821C) -#define BIT_GET_RTSRST_V1_8821C(x) (((x) >> BIT_SHIFT_RTSRST_V1_8821C) & BIT_MASK_RTSRST_V1_8821C) - - +#define BIT_RTSRST_V1_8821C(x) \ + (((x) & BIT_MASK_RTSRST_V1_8821C) << BIT_SHIFT_RTSRST_V1_8821C) +#define BITS_RTSRST_V1_8821C \ + (BIT_MASK_RTSRST_V1_8821C << BIT_SHIFT_RTSRST_V1_8821C) +#define BIT_CLEAR_RTSRST_V1_8821C(x) ((x) & (~BITS_RTSRST_V1_8821C)) +#define BIT_GET_RTSRST_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RTSRST_V1_8821C) & BIT_MASK_RTSRST_V1_8821C) +#define BIT_SET_RTSRST_V1_8821C(x, v) \ + (BIT_CLEAR_RTSRST_V1_8821C(x) | BIT_RTSRST_V1_8821C(v)) /* 2 REG_WLAN_ACT_MASK_CTRL_1_8821C */ #define BIT_WLRX_TER_BY_CTL_1_8821C BIT(11) @@ -10594,23 +17705,47 @@ #define BIT_SHIFT_BT_STAT_DELAY_8821C 12 #define BIT_MASK_BT_STAT_DELAY_8821C 0xf -#define BIT_BT_STAT_DELAY_8821C(x) (((x) & BIT_MASK_BT_STAT_DELAY_8821C) << BIT_SHIFT_BT_STAT_DELAY_8821C) -#define BIT_GET_BT_STAT_DELAY_8821C(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8821C) & BIT_MASK_BT_STAT_DELAY_8821C) - - +#define BIT_BT_STAT_DELAY_8821C(x) \ + (((x) & BIT_MASK_BT_STAT_DELAY_8821C) << BIT_SHIFT_BT_STAT_DELAY_8821C) +#define BITS_BT_STAT_DELAY_8821C \ + (BIT_MASK_BT_STAT_DELAY_8821C << BIT_SHIFT_BT_STAT_DELAY_8821C) +#define BIT_CLEAR_BT_STAT_DELAY_8821C(x) ((x) & (~BITS_BT_STAT_DELAY_8821C)) +#define BIT_GET_BT_STAT_DELAY_8821C(x) \ + (((x) >> BIT_SHIFT_BT_STAT_DELAY_8821C) & BIT_MASK_BT_STAT_DELAY_8821C) +#define BIT_SET_BT_STAT_DELAY_8821C(x, v) \ + (BIT_CLEAR_BT_STAT_DELAY_8821C(x) | BIT_BT_STAT_DELAY_8821C(v)) #define BIT_SHIFT_BT_TRX_INIT_DETECT_8821C 8 #define BIT_MASK_BT_TRX_INIT_DETECT_8821C 0xf -#define BIT_BT_TRX_INIT_DETECT_8821C(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8821C) << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) -#define BIT_GET_BT_TRX_INIT_DETECT_8821C(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) & BIT_MASK_BT_TRX_INIT_DETECT_8821C) - - +#define BIT_BT_TRX_INIT_DETECT_8821C(x) \ + (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8821C) \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) +#define BITS_BT_TRX_INIT_DETECT_8821C \ + (BIT_MASK_BT_TRX_INIT_DETECT_8821C \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) +#define BIT_CLEAR_BT_TRX_INIT_DETECT_8821C(x) \ + ((x) & (~BITS_BT_TRX_INIT_DETECT_8821C)) +#define BIT_GET_BT_TRX_INIT_DETECT_8821C(x) \ + (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) & \ + BIT_MASK_BT_TRX_INIT_DETECT_8821C) +#define BIT_SET_BT_TRX_INIT_DETECT_8821C(x, v) \ + (BIT_CLEAR_BT_TRX_INIT_DETECT_8821C(x) | \ + BIT_BT_TRX_INIT_DETECT_8821C(v)) #define BIT_SHIFT_BT_PRI_DETECT_TO_8821C 4 #define BIT_MASK_BT_PRI_DETECT_TO_8821C 0xf -#define BIT_BT_PRI_DETECT_TO_8821C(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8821C) << BIT_SHIFT_BT_PRI_DETECT_TO_8821C) -#define BIT_GET_BT_PRI_DETECT_TO_8821C(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8821C) & BIT_MASK_BT_PRI_DETECT_TO_8821C) - +#define BIT_BT_PRI_DETECT_TO_8821C(x) \ + (((x) & BIT_MASK_BT_PRI_DETECT_TO_8821C) \ + << BIT_SHIFT_BT_PRI_DETECT_TO_8821C) +#define BITS_BT_PRI_DETECT_TO_8821C \ + (BIT_MASK_BT_PRI_DETECT_TO_8821C << BIT_SHIFT_BT_PRI_DETECT_TO_8821C) +#define BIT_CLEAR_BT_PRI_DETECT_TO_8821C(x) \ + ((x) & (~BITS_BT_PRI_DETECT_TO_8821C)) +#define BIT_GET_BT_PRI_DETECT_TO_8821C(x) \ + (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8821C) & \ + BIT_MASK_BT_PRI_DETECT_TO_8821C) +#define BIT_SET_BT_PRI_DETECT_TO_8821C(x, v) \ + (BIT_CLEAR_BT_PRI_DETECT_TO_8821C(x) | BIT_BT_PRI_DETECT_TO_8821C(v)) #define BIT_R_GRANTALL_WLMASK_8821C BIT(3) #define BIT_STATIS_BT_EN_8821C BIT(2) @@ -10621,55 +17756,103 @@ #define BIT_SHIFT_STATIS_BT_HI_RX_8821C 16 #define BIT_MASK_STATIS_BT_HI_RX_8821C 0xffff -#define BIT_STATIS_BT_HI_RX_8821C(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8821C) << BIT_SHIFT_STATIS_BT_HI_RX_8821C) -#define BIT_GET_STATIS_BT_HI_RX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8821C) & BIT_MASK_STATIS_BT_HI_RX_8821C) - - +#define BIT_STATIS_BT_HI_RX_8821C(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_RX_8821C) \ + << BIT_SHIFT_STATIS_BT_HI_RX_8821C) +#define BITS_STATIS_BT_HI_RX_8821C \ + (BIT_MASK_STATIS_BT_HI_RX_8821C << BIT_SHIFT_STATIS_BT_HI_RX_8821C) +#define BIT_CLEAR_STATIS_BT_HI_RX_8821C(x) ((x) & (~BITS_STATIS_BT_HI_RX_8821C)) +#define BIT_GET_STATIS_BT_HI_RX_8821C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8821C) & \ + BIT_MASK_STATIS_BT_HI_RX_8821C) +#define BIT_SET_STATIS_BT_HI_RX_8821C(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_RX_8821C(x) | BIT_STATIS_BT_HI_RX_8821C(v)) #define BIT_SHIFT_STATIS_BT_HI_TX_8821C 0 #define BIT_MASK_STATIS_BT_HI_TX_8821C 0xffff -#define BIT_STATIS_BT_HI_TX_8821C(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8821C) << BIT_SHIFT_STATIS_BT_HI_TX_8821C) -#define BIT_GET_STATIS_BT_HI_TX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8821C) & BIT_MASK_STATIS_BT_HI_TX_8821C) - - +#define BIT_STATIS_BT_HI_TX_8821C(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_TX_8821C) \ + << BIT_SHIFT_STATIS_BT_HI_TX_8821C) +#define BITS_STATIS_BT_HI_TX_8821C \ + (BIT_MASK_STATIS_BT_HI_TX_8821C << BIT_SHIFT_STATIS_BT_HI_TX_8821C) +#define BIT_CLEAR_STATIS_BT_HI_TX_8821C(x) ((x) & (~BITS_STATIS_BT_HI_TX_8821C)) +#define BIT_GET_STATIS_BT_HI_TX_8821C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8821C) & \ + BIT_MASK_STATIS_BT_HI_TX_8821C) +#define BIT_SET_STATIS_BT_HI_TX_8821C(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_TX_8821C(x) | BIT_STATIS_BT_HI_TX_8821C(v)) /* 2 REG_BT_ACT_STATISTICS_1_8821C */ #define BIT_SHIFT_STATIS_BT_LO_RX_1_8821C 16 #define BIT_MASK_STATIS_BT_LO_RX_1_8821C 0xffff -#define BIT_STATIS_BT_LO_RX_1_8821C(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8821C) << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) -#define BIT_GET_STATIS_BT_LO_RX_1_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) & BIT_MASK_STATIS_BT_LO_RX_1_8821C) - - +#define BIT_STATIS_BT_LO_RX_1_8821C(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8821C) \ + << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) +#define BITS_STATIS_BT_LO_RX_1_8821C \ + (BIT_MASK_STATIS_BT_LO_RX_1_8821C << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) +#define BIT_CLEAR_STATIS_BT_LO_RX_1_8821C(x) \ + ((x) & (~BITS_STATIS_BT_LO_RX_1_8821C)) +#define BIT_GET_STATIS_BT_LO_RX_1_8821C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) & \ + BIT_MASK_STATIS_BT_LO_RX_1_8821C) +#define BIT_SET_STATIS_BT_LO_RX_1_8821C(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX_1_8821C(x) | BIT_STATIS_BT_LO_RX_1_8821C(v)) #define BIT_SHIFT_STATIS_BT_LO_TX_1_8821C 0 #define BIT_MASK_STATIS_BT_LO_TX_1_8821C 0xffff -#define BIT_STATIS_BT_LO_TX_1_8821C(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8821C) << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) -#define BIT_GET_STATIS_BT_LO_TX_1_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) & BIT_MASK_STATIS_BT_LO_TX_1_8821C) - - +#define BIT_STATIS_BT_LO_TX_1_8821C(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8821C) \ + << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) +#define BITS_STATIS_BT_LO_TX_1_8821C \ + (BIT_MASK_STATIS_BT_LO_TX_1_8821C << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) +#define BIT_CLEAR_STATIS_BT_LO_TX_1_8821C(x) \ + ((x) & (~BITS_STATIS_BT_LO_TX_1_8821C)) +#define BIT_GET_STATIS_BT_LO_TX_1_8821C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) & \ + BIT_MASK_STATIS_BT_LO_TX_1_8821C) +#define BIT_SET_STATIS_BT_LO_TX_1_8821C(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX_1_8821C(x) | BIT_STATIS_BT_LO_TX_1_8821C(v)) /* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8821C */ #define BIT_SHIFT_R_BT_CMD_RPT_8821C 16 #define BIT_MASK_R_BT_CMD_RPT_8821C 0xffff -#define BIT_R_BT_CMD_RPT_8821C(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8821C) << BIT_SHIFT_R_BT_CMD_RPT_8821C) -#define BIT_GET_R_BT_CMD_RPT_8821C(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8821C) & BIT_MASK_R_BT_CMD_RPT_8821C) - - +#define BIT_R_BT_CMD_RPT_8821C(x) \ + (((x) & BIT_MASK_R_BT_CMD_RPT_8821C) << BIT_SHIFT_R_BT_CMD_RPT_8821C) +#define BITS_R_BT_CMD_RPT_8821C \ + (BIT_MASK_R_BT_CMD_RPT_8821C << BIT_SHIFT_R_BT_CMD_RPT_8821C) +#define BIT_CLEAR_R_BT_CMD_RPT_8821C(x) ((x) & (~BITS_R_BT_CMD_RPT_8821C)) +#define BIT_GET_R_BT_CMD_RPT_8821C(x) \ + (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8821C) & BIT_MASK_R_BT_CMD_RPT_8821C) +#define BIT_SET_R_BT_CMD_RPT_8821C(x, v) \ + (BIT_CLEAR_R_BT_CMD_RPT_8821C(x) | BIT_R_BT_CMD_RPT_8821C(v)) #define BIT_SHIFT_R_RPT_FROM_BT_8821C 8 #define BIT_MASK_R_RPT_FROM_BT_8821C 0xff -#define BIT_R_RPT_FROM_BT_8821C(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8821C) << BIT_SHIFT_R_RPT_FROM_BT_8821C) -#define BIT_GET_R_RPT_FROM_BT_8821C(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8821C) & BIT_MASK_R_RPT_FROM_BT_8821C) - - +#define BIT_R_RPT_FROM_BT_8821C(x) \ + (((x) & BIT_MASK_R_RPT_FROM_BT_8821C) << BIT_SHIFT_R_RPT_FROM_BT_8821C) +#define BITS_R_RPT_FROM_BT_8821C \ + (BIT_MASK_R_RPT_FROM_BT_8821C << BIT_SHIFT_R_RPT_FROM_BT_8821C) +#define BIT_CLEAR_R_RPT_FROM_BT_8821C(x) ((x) & (~BITS_R_RPT_FROM_BT_8821C)) +#define BIT_GET_R_RPT_FROM_BT_8821C(x) \ + (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8821C) & BIT_MASK_R_RPT_FROM_BT_8821C) +#define BIT_SET_R_RPT_FROM_BT_8821C(x, v) \ + (BIT_CLEAR_R_RPT_FROM_BT_8821C(x) | BIT_R_RPT_FROM_BT_8821C(v)) #define BIT_SHIFT_BT_HID_ISR_SET_8821C 6 #define BIT_MASK_BT_HID_ISR_SET_8821C 0x3 -#define BIT_BT_HID_ISR_SET_8821C(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8821C) << BIT_SHIFT_BT_HID_ISR_SET_8821C) -#define BIT_GET_BT_HID_ISR_SET_8821C(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8821C) & BIT_MASK_BT_HID_ISR_SET_8821C) - +#define BIT_BT_HID_ISR_SET_8821C(x) \ + (((x) & BIT_MASK_BT_HID_ISR_SET_8821C) \ + << BIT_SHIFT_BT_HID_ISR_SET_8821C) +#define BITS_BT_HID_ISR_SET_8821C \ + (BIT_MASK_BT_HID_ISR_SET_8821C << BIT_SHIFT_BT_HID_ISR_SET_8821C) +#define BIT_CLEAR_BT_HID_ISR_SET_8821C(x) ((x) & (~BITS_BT_HID_ISR_SET_8821C)) +#define BIT_GET_BT_HID_ISR_SET_8821C(x) \ + (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8821C) & \ + BIT_MASK_BT_HID_ISR_SET_8821C) +#define BIT_SET_BT_HID_ISR_SET_8821C(x, v) \ + (BIT_CLEAR_BT_HID_ISR_SET_8821C(x) | BIT_BT_HID_ISR_SET_8821C(v)) #define BIT_TDMA_BT_START_NOTIFY_8821C BIT(5) #define BIT_ENABLE_TDMA_FW_MODE_8821C BIT(4) @@ -10682,31 +17865,54 @@ #define BIT_SHIFT_BT_PROFILE_8821C 24 #define BIT_MASK_BT_PROFILE_8821C 0xff -#define BIT_BT_PROFILE_8821C(x) (((x) & BIT_MASK_BT_PROFILE_8821C) << BIT_SHIFT_BT_PROFILE_8821C) -#define BIT_GET_BT_PROFILE_8821C(x) (((x) >> BIT_SHIFT_BT_PROFILE_8821C) & BIT_MASK_BT_PROFILE_8821C) - - +#define BIT_BT_PROFILE_8821C(x) \ + (((x) & BIT_MASK_BT_PROFILE_8821C) << BIT_SHIFT_BT_PROFILE_8821C) +#define BITS_BT_PROFILE_8821C \ + (BIT_MASK_BT_PROFILE_8821C << BIT_SHIFT_BT_PROFILE_8821C) +#define BIT_CLEAR_BT_PROFILE_8821C(x) ((x) & (~BITS_BT_PROFILE_8821C)) +#define BIT_GET_BT_PROFILE_8821C(x) \ + (((x) >> BIT_SHIFT_BT_PROFILE_8821C) & BIT_MASK_BT_PROFILE_8821C) +#define BIT_SET_BT_PROFILE_8821C(x, v) \ + (BIT_CLEAR_BT_PROFILE_8821C(x) | BIT_BT_PROFILE_8821C(v)) #define BIT_SHIFT_BT_POWER_8821C 16 #define BIT_MASK_BT_POWER_8821C 0xff -#define BIT_BT_POWER_8821C(x) (((x) & BIT_MASK_BT_POWER_8821C) << BIT_SHIFT_BT_POWER_8821C) -#define BIT_GET_BT_POWER_8821C(x) (((x) >> BIT_SHIFT_BT_POWER_8821C) & BIT_MASK_BT_POWER_8821C) - - +#define BIT_BT_POWER_8821C(x) \ + (((x) & BIT_MASK_BT_POWER_8821C) << BIT_SHIFT_BT_POWER_8821C) +#define BITS_BT_POWER_8821C \ + (BIT_MASK_BT_POWER_8821C << BIT_SHIFT_BT_POWER_8821C) +#define BIT_CLEAR_BT_POWER_8821C(x) ((x) & (~BITS_BT_POWER_8821C)) +#define BIT_GET_BT_POWER_8821C(x) \ + (((x) >> BIT_SHIFT_BT_POWER_8821C) & BIT_MASK_BT_POWER_8821C) +#define BIT_SET_BT_POWER_8821C(x, v) \ + (BIT_CLEAR_BT_POWER_8821C(x) | BIT_BT_POWER_8821C(v)) #define BIT_SHIFT_BT_PREDECT_STATUS_8821C 8 #define BIT_MASK_BT_PREDECT_STATUS_8821C 0xff -#define BIT_BT_PREDECT_STATUS_8821C(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8821C) << BIT_SHIFT_BT_PREDECT_STATUS_8821C) -#define BIT_GET_BT_PREDECT_STATUS_8821C(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8821C) & BIT_MASK_BT_PREDECT_STATUS_8821C) - - +#define BIT_BT_PREDECT_STATUS_8821C(x) \ + (((x) & BIT_MASK_BT_PREDECT_STATUS_8821C) \ + << BIT_SHIFT_BT_PREDECT_STATUS_8821C) +#define BITS_BT_PREDECT_STATUS_8821C \ + (BIT_MASK_BT_PREDECT_STATUS_8821C << BIT_SHIFT_BT_PREDECT_STATUS_8821C) +#define BIT_CLEAR_BT_PREDECT_STATUS_8821C(x) \ + ((x) & (~BITS_BT_PREDECT_STATUS_8821C)) +#define BIT_GET_BT_PREDECT_STATUS_8821C(x) \ + (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8821C) & \ + BIT_MASK_BT_PREDECT_STATUS_8821C) +#define BIT_SET_BT_PREDECT_STATUS_8821C(x, v) \ + (BIT_CLEAR_BT_PREDECT_STATUS_8821C(x) | BIT_BT_PREDECT_STATUS_8821C(v)) #define BIT_SHIFT_BT_CMD_INFO_8821C 0 #define BIT_MASK_BT_CMD_INFO_8821C 0xff -#define BIT_BT_CMD_INFO_8821C(x) (((x) & BIT_MASK_BT_CMD_INFO_8821C) << BIT_SHIFT_BT_CMD_INFO_8821C) -#define BIT_GET_BT_CMD_INFO_8821C(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8821C) & BIT_MASK_BT_CMD_INFO_8821C) - - +#define BIT_BT_CMD_INFO_8821C(x) \ + (((x) & BIT_MASK_BT_CMD_INFO_8821C) << BIT_SHIFT_BT_CMD_INFO_8821C) +#define BITS_BT_CMD_INFO_8821C \ + (BIT_MASK_BT_CMD_INFO_8821C << BIT_SHIFT_BT_CMD_INFO_8821C) +#define BIT_CLEAR_BT_CMD_INFO_8821C(x) ((x) & (~BITS_BT_CMD_INFO_8821C)) +#define BIT_GET_BT_CMD_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_BT_CMD_INFO_8821C) & BIT_MASK_BT_CMD_INFO_8821C) +#define BIT_SET_BT_CMD_INFO_8821C(x, v) \ + (BIT_CLEAR_BT_CMD_INFO_8821C(x) | BIT_BT_CMD_INFO_8821C(v)) /* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8821C */ #define BIT_EN_MAC_NULL_PKT_NOTIFY_8821C BIT(31) @@ -10720,41 +17926,67 @@ #define BIT_SHIFT_WLAN_RPT_DATA_8821C 16 #define BIT_MASK_WLAN_RPT_DATA_8821C 0xff -#define BIT_WLAN_RPT_DATA_8821C(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8821C) << BIT_SHIFT_WLAN_RPT_DATA_8821C) -#define BIT_GET_WLAN_RPT_DATA_8821C(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8821C) & BIT_MASK_WLAN_RPT_DATA_8821C) - - +#define BIT_WLAN_RPT_DATA_8821C(x) \ + (((x) & BIT_MASK_WLAN_RPT_DATA_8821C) << BIT_SHIFT_WLAN_RPT_DATA_8821C) +#define BITS_WLAN_RPT_DATA_8821C \ + (BIT_MASK_WLAN_RPT_DATA_8821C << BIT_SHIFT_WLAN_RPT_DATA_8821C) +#define BIT_CLEAR_WLAN_RPT_DATA_8821C(x) ((x) & (~BITS_WLAN_RPT_DATA_8821C)) +#define BIT_GET_WLAN_RPT_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8821C) & BIT_MASK_WLAN_RPT_DATA_8821C) +#define BIT_SET_WLAN_RPT_DATA_8821C(x, v) \ + (BIT_CLEAR_WLAN_RPT_DATA_8821C(x) | BIT_WLAN_RPT_DATA_8821C(v)) #define BIT_SHIFT_CMD_ID_8821C 8 #define BIT_MASK_CMD_ID_8821C 0xff -#define BIT_CMD_ID_8821C(x) (((x) & BIT_MASK_CMD_ID_8821C) << BIT_SHIFT_CMD_ID_8821C) -#define BIT_GET_CMD_ID_8821C(x) (((x) >> BIT_SHIFT_CMD_ID_8821C) & BIT_MASK_CMD_ID_8821C) - - +#define BIT_CMD_ID_8821C(x) \ + (((x) & BIT_MASK_CMD_ID_8821C) << BIT_SHIFT_CMD_ID_8821C) +#define BITS_CMD_ID_8821C (BIT_MASK_CMD_ID_8821C << BIT_SHIFT_CMD_ID_8821C) +#define BIT_CLEAR_CMD_ID_8821C(x) ((x) & (~BITS_CMD_ID_8821C)) +#define BIT_GET_CMD_ID_8821C(x) \ + (((x) >> BIT_SHIFT_CMD_ID_8821C) & BIT_MASK_CMD_ID_8821C) +#define BIT_SET_CMD_ID_8821C(x, v) \ + (BIT_CLEAR_CMD_ID_8821C(x) | BIT_CMD_ID_8821C(v)) #define BIT_SHIFT_BT_DATA_8821C 0 #define BIT_MASK_BT_DATA_8821C 0xff -#define BIT_BT_DATA_8821C(x) (((x) & BIT_MASK_BT_DATA_8821C) << BIT_SHIFT_BT_DATA_8821C) -#define BIT_GET_BT_DATA_8821C(x) (((x) >> BIT_SHIFT_BT_DATA_8821C) & BIT_MASK_BT_DATA_8821C) - - +#define BIT_BT_DATA_8821C(x) \ + (((x) & BIT_MASK_BT_DATA_8821C) << BIT_SHIFT_BT_DATA_8821C) +#define BITS_BT_DATA_8821C (BIT_MASK_BT_DATA_8821C << BIT_SHIFT_BT_DATA_8821C) +#define BIT_CLEAR_BT_DATA_8821C(x) ((x) & (~BITS_BT_DATA_8821C)) +#define BIT_GET_BT_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_BT_DATA_8821C) & BIT_MASK_BT_DATA_8821C) +#define BIT_SET_BT_DATA_8821C(x, v) \ + (BIT_CLEAR_BT_DATA_8821C(x) | BIT_BT_DATA_8821C(v)) /* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C */ #define BIT_SHIFT_WLAN_RPT_TO_8821C 0 #define BIT_MASK_WLAN_RPT_TO_8821C 0xff -#define BIT_WLAN_RPT_TO_8821C(x) (((x) & BIT_MASK_WLAN_RPT_TO_8821C) << BIT_SHIFT_WLAN_RPT_TO_8821C) -#define BIT_GET_WLAN_RPT_TO_8821C(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8821C) & BIT_MASK_WLAN_RPT_TO_8821C) - - +#define BIT_WLAN_RPT_TO_8821C(x) \ + (((x) & BIT_MASK_WLAN_RPT_TO_8821C) << BIT_SHIFT_WLAN_RPT_TO_8821C) +#define BITS_WLAN_RPT_TO_8821C \ + (BIT_MASK_WLAN_RPT_TO_8821C << BIT_SHIFT_WLAN_RPT_TO_8821C) +#define BIT_CLEAR_WLAN_RPT_TO_8821C(x) ((x) & (~BITS_WLAN_RPT_TO_8821C)) +#define BIT_GET_WLAN_RPT_TO_8821C(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_TO_8821C) & BIT_MASK_WLAN_RPT_TO_8821C) +#define BIT_SET_WLAN_RPT_TO_8821C(x, v) \ + (BIT_CLEAR_WLAN_RPT_TO_8821C(x) | BIT_WLAN_RPT_TO_8821C(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C */ #define BIT_SHIFT_ISOLATION_CHK_0_8821C 1 #define BIT_MASK_ISOLATION_CHK_0_8821C 0x7fffff -#define BIT_ISOLATION_CHK_0_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_0_8821C) << BIT_SHIFT_ISOLATION_CHK_0_8821C) -#define BIT_GET_ISOLATION_CHK_0_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8821C) & BIT_MASK_ISOLATION_CHK_0_8821C) - +#define BIT_ISOLATION_CHK_0_8821C(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_0_8821C) \ + << BIT_SHIFT_ISOLATION_CHK_0_8821C) +#define BITS_ISOLATION_CHK_0_8821C \ + (BIT_MASK_ISOLATION_CHK_0_8821C << BIT_SHIFT_ISOLATION_CHK_0_8821C) +#define BIT_CLEAR_ISOLATION_CHK_0_8821C(x) ((x) & (~BITS_ISOLATION_CHK_0_8821C)) +#define BIT_GET_ISOLATION_CHK_0_8821C(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8821C) & \ + BIT_MASK_ISOLATION_CHK_0_8821C) +#define BIT_SET_ISOLATION_CHK_0_8821C(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_0_8821C(x) | BIT_ISOLATION_CHK_0_8821C(v)) #define BIT_ISOLATION_EN_8821C BIT(0) @@ -10762,19 +17994,33 @@ #define BIT_SHIFT_ISOLATION_CHK_1_8821C 0 #define BIT_MASK_ISOLATION_CHK_1_8821C 0xffffffffL -#define BIT_ISOLATION_CHK_1_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_1_8821C) << BIT_SHIFT_ISOLATION_CHK_1_8821C) -#define BIT_GET_ISOLATION_CHK_1_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8821C) & BIT_MASK_ISOLATION_CHK_1_8821C) - - +#define BIT_ISOLATION_CHK_1_8821C(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_1_8821C) \ + << BIT_SHIFT_ISOLATION_CHK_1_8821C) +#define BITS_ISOLATION_CHK_1_8821C \ + (BIT_MASK_ISOLATION_CHK_1_8821C << BIT_SHIFT_ISOLATION_CHK_1_8821C) +#define BIT_CLEAR_ISOLATION_CHK_1_8821C(x) ((x) & (~BITS_ISOLATION_CHK_1_8821C)) +#define BIT_GET_ISOLATION_CHK_1_8821C(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8821C) & \ + BIT_MASK_ISOLATION_CHK_1_8821C) +#define BIT_SET_ISOLATION_CHK_1_8821C(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_1_8821C(x) | BIT_ISOLATION_CHK_1_8821C(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C */ #define BIT_SHIFT_ISOLATION_CHK_2_8821C 0 #define BIT_MASK_ISOLATION_CHK_2_8821C 0xffffff -#define BIT_ISOLATION_CHK_2_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_2_8821C) << BIT_SHIFT_ISOLATION_CHK_2_8821C) -#define BIT_GET_ISOLATION_CHK_2_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8821C) & BIT_MASK_ISOLATION_CHK_2_8821C) - - +#define BIT_ISOLATION_CHK_2_8821C(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_2_8821C) \ + << BIT_SHIFT_ISOLATION_CHK_2_8821C) +#define BITS_ISOLATION_CHK_2_8821C \ + (BIT_MASK_ISOLATION_CHK_2_8821C << BIT_SHIFT_ISOLATION_CHK_2_8821C) +#define BIT_CLEAR_ISOLATION_CHK_2_8821C(x) ((x) & (~BITS_ISOLATION_CHK_2_8821C)) +#define BIT_GET_ISOLATION_CHK_2_8821C(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8821C) & \ + BIT_MASK_ISOLATION_CHK_2_8821C) +#define BIT_SET_ISOLATION_CHK_2_8821C(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_2_8821C(x) | BIT_ISOLATION_CHK_2_8821C(v)) /* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8821C */ #define BIT_BT_HID_ISR_8821C BIT(7) @@ -10790,25 +18036,45 @@ #define BIT_SHIFT_BT_TIME_8821C 6 #define BIT_MASK_BT_TIME_8821C 0x3ffffff -#define BIT_BT_TIME_8821C(x) (((x) & BIT_MASK_BT_TIME_8821C) << BIT_SHIFT_BT_TIME_8821C) -#define BIT_GET_BT_TIME_8821C(x) (((x) >> BIT_SHIFT_BT_TIME_8821C) & BIT_MASK_BT_TIME_8821C) - - +#define BIT_BT_TIME_8821C(x) \ + (((x) & BIT_MASK_BT_TIME_8821C) << BIT_SHIFT_BT_TIME_8821C) +#define BITS_BT_TIME_8821C (BIT_MASK_BT_TIME_8821C << BIT_SHIFT_BT_TIME_8821C) +#define BIT_CLEAR_BT_TIME_8821C(x) ((x) & (~BITS_BT_TIME_8821C)) +#define BIT_GET_BT_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_BT_TIME_8821C) & BIT_MASK_BT_TIME_8821C) +#define BIT_SET_BT_TIME_8821C(x, v) \ + (BIT_CLEAR_BT_TIME_8821C(x) | BIT_BT_TIME_8821C(v)) #define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C 0 #define BIT_MASK_BT_RPT_SAMPLE_RATE_8821C 0x3f -#define BIT_BT_RPT_SAMPLE_RATE_8821C(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) -#define BIT_GET_BT_RPT_SAMPLE_RATE_8821C(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) - - +#define BIT_BT_RPT_SAMPLE_RATE_8821C(x) \ + (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) +#define BITS_BT_RPT_SAMPLE_RATE_8821C \ + (BIT_MASK_BT_RPT_SAMPLE_RATE_8821C \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8821C(x) \ + ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8821C)) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8821C(x) \ + (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) & \ + BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) +#define BIT_SET_BT_RPT_SAMPLE_RATE_8821C(x, v) \ + (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8821C(x) | \ + BIT_BT_RPT_SAMPLE_RATE_8821C(v)) /* 2 REG_BT_ACT_REGISTER_8821C */ #define BIT_SHIFT_BT_EISR_EN_8821C 16 #define BIT_MASK_BT_EISR_EN_8821C 0xff -#define BIT_BT_EISR_EN_8821C(x) (((x) & BIT_MASK_BT_EISR_EN_8821C) << BIT_SHIFT_BT_EISR_EN_8821C) -#define BIT_GET_BT_EISR_EN_8821C(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8821C) & BIT_MASK_BT_EISR_EN_8821C) - +#define BIT_BT_EISR_EN_8821C(x) \ + (((x) & BIT_MASK_BT_EISR_EN_8821C) << BIT_SHIFT_BT_EISR_EN_8821C) +#define BITS_BT_EISR_EN_8821C \ + (BIT_MASK_BT_EISR_EN_8821C << BIT_SHIFT_BT_EISR_EN_8821C) +#define BIT_CLEAR_BT_EISR_EN_8821C(x) ((x) & (~BITS_BT_EISR_EN_8821C)) +#define BIT_GET_BT_EISR_EN_8821C(x) \ + (((x) >> BIT_SHIFT_BT_EISR_EN_8821C) & BIT_MASK_BT_EISR_EN_8821C) +#define BIT_SET_BT_EISR_EN_8821C(x, v) \ + (BIT_CLEAR_BT_EISR_EN_8821C(x) | BIT_BT_EISR_EN_8821C(v)) #define BIT_BT_ACT_FALLING_ISR_8821C BIT(10) #define BIT_BT_ACT_RISING_ISR_8821C BIT(9) @@ -10816,19 +18082,29 @@ #define BIT_SHIFT_BT_CH_8821C 0 #define BIT_MASK_BT_CH_8821C 0xff -#define BIT_BT_CH_8821C(x) (((x) & BIT_MASK_BT_CH_8821C) << BIT_SHIFT_BT_CH_8821C) -#define BIT_GET_BT_CH_8821C(x) (((x) >> BIT_SHIFT_BT_CH_8821C) & BIT_MASK_BT_CH_8821C) - - +#define BIT_BT_CH_8821C(x) \ + (((x) & BIT_MASK_BT_CH_8821C) << BIT_SHIFT_BT_CH_8821C) +#define BITS_BT_CH_8821C (BIT_MASK_BT_CH_8821C << BIT_SHIFT_BT_CH_8821C) +#define BIT_CLEAR_BT_CH_8821C(x) ((x) & (~BITS_BT_CH_8821C)) +#define BIT_GET_BT_CH_8821C(x) \ + (((x) >> BIT_SHIFT_BT_CH_8821C) & BIT_MASK_BT_CH_8821C) +#define BIT_SET_BT_CH_8821C(x, v) \ + (BIT_CLEAR_BT_CH_8821C(x) | BIT_BT_CH_8821C(v)) /* 2 REG_OBFF_CTRL_BASIC_8821C */ #define BIT_OBFF_EN_V1_8821C BIT(31) #define BIT_SHIFT_OBFF_STATE_V1_8821C 28 #define BIT_MASK_OBFF_STATE_V1_8821C 0x3 -#define BIT_OBFF_STATE_V1_8821C(x) (((x) & BIT_MASK_OBFF_STATE_V1_8821C) << BIT_SHIFT_OBFF_STATE_V1_8821C) -#define BIT_GET_OBFF_STATE_V1_8821C(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8821C) & BIT_MASK_OBFF_STATE_V1_8821C) - +#define BIT_OBFF_STATE_V1_8821C(x) \ + (((x) & BIT_MASK_OBFF_STATE_V1_8821C) << BIT_SHIFT_OBFF_STATE_V1_8821C) +#define BITS_OBFF_STATE_V1_8821C \ + (BIT_MASK_OBFF_STATE_V1_8821C << BIT_SHIFT_OBFF_STATE_V1_8821C) +#define BIT_CLEAR_OBFF_STATE_V1_8821C(x) ((x) & (~BITS_OBFF_STATE_V1_8821C)) +#define BIT_GET_OBFF_STATE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_OBFF_STATE_V1_8821C) & BIT_MASK_OBFF_STATE_V1_8821C) +#define BIT_SET_OBFF_STATE_V1_8821C(x, v) \ + (BIT_CLEAR_OBFF_STATE_V1_8821C(x) | BIT_OBFF_STATE_V1_8821C(v)) #define BIT_OBFF_ACT_RXDMA_EN_8821C BIT(27) #define BIT_OBFF_BLOCK_INT_EN_8821C BIT(26) @@ -10837,30 +18113,51 @@ #define BIT_SHIFT_WAKE_MAX_PLS_8821C 20 #define BIT_MASK_WAKE_MAX_PLS_8821C 0x7 -#define BIT_WAKE_MAX_PLS_8821C(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8821C) << BIT_SHIFT_WAKE_MAX_PLS_8821C) -#define BIT_GET_WAKE_MAX_PLS_8821C(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8821C) & BIT_MASK_WAKE_MAX_PLS_8821C) - - +#define BIT_WAKE_MAX_PLS_8821C(x) \ + (((x) & BIT_MASK_WAKE_MAX_PLS_8821C) << BIT_SHIFT_WAKE_MAX_PLS_8821C) +#define BITS_WAKE_MAX_PLS_8821C \ + (BIT_MASK_WAKE_MAX_PLS_8821C << BIT_SHIFT_WAKE_MAX_PLS_8821C) +#define BIT_CLEAR_WAKE_MAX_PLS_8821C(x) ((x) & (~BITS_WAKE_MAX_PLS_8821C)) +#define BIT_GET_WAKE_MAX_PLS_8821C(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8821C) & BIT_MASK_WAKE_MAX_PLS_8821C) +#define BIT_SET_WAKE_MAX_PLS_8821C(x, v) \ + (BIT_CLEAR_WAKE_MAX_PLS_8821C(x) | BIT_WAKE_MAX_PLS_8821C(v)) #define BIT_SHIFT_WAKE_MIN_PLS_8821C 16 #define BIT_MASK_WAKE_MIN_PLS_8821C 0x7 -#define BIT_WAKE_MIN_PLS_8821C(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8821C) << BIT_SHIFT_WAKE_MIN_PLS_8821C) -#define BIT_GET_WAKE_MIN_PLS_8821C(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8821C) & BIT_MASK_WAKE_MIN_PLS_8821C) - - +#define BIT_WAKE_MIN_PLS_8821C(x) \ + (((x) & BIT_MASK_WAKE_MIN_PLS_8821C) << BIT_SHIFT_WAKE_MIN_PLS_8821C) +#define BITS_WAKE_MIN_PLS_8821C \ + (BIT_MASK_WAKE_MIN_PLS_8821C << BIT_SHIFT_WAKE_MIN_PLS_8821C) +#define BIT_CLEAR_WAKE_MIN_PLS_8821C(x) ((x) & (~BITS_WAKE_MIN_PLS_8821C)) +#define BIT_GET_WAKE_MIN_PLS_8821C(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8821C) & BIT_MASK_WAKE_MIN_PLS_8821C) +#define BIT_SET_WAKE_MIN_PLS_8821C(x, v) \ + (BIT_CLEAR_WAKE_MIN_PLS_8821C(x) | BIT_WAKE_MIN_PLS_8821C(v)) #define BIT_SHIFT_WAKE_MAX_F2F_8821C 12 #define BIT_MASK_WAKE_MAX_F2F_8821C 0x7 -#define BIT_WAKE_MAX_F2F_8821C(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8821C) << BIT_SHIFT_WAKE_MAX_F2F_8821C) -#define BIT_GET_WAKE_MAX_F2F_8821C(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8821C) & BIT_MASK_WAKE_MAX_F2F_8821C) - - +#define BIT_WAKE_MAX_F2F_8821C(x) \ + (((x) & BIT_MASK_WAKE_MAX_F2F_8821C) << BIT_SHIFT_WAKE_MAX_F2F_8821C) +#define BITS_WAKE_MAX_F2F_8821C \ + (BIT_MASK_WAKE_MAX_F2F_8821C << BIT_SHIFT_WAKE_MAX_F2F_8821C) +#define BIT_CLEAR_WAKE_MAX_F2F_8821C(x) ((x) & (~BITS_WAKE_MAX_F2F_8821C)) +#define BIT_GET_WAKE_MAX_F2F_8821C(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8821C) & BIT_MASK_WAKE_MAX_F2F_8821C) +#define BIT_SET_WAKE_MAX_F2F_8821C(x, v) \ + (BIT_CLEAR_WAKE_MAX_F2F_8821C(x) | BIT_WAKE_MAX_F2F_8821C(v)) #define BIT_SHIFT_WAKE_MIN_F2F_8821C 8 #define BIT_MASK_WAKE_MIN_F2F_8821C 0x7 -#define BIT_WAKE_MIN_F2F_8821C(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8821C) << BIT_SHIFT_WAKE_MIN_F2F_8821C) -#define BIT_GET_WAKE_MIN_F2F_8821C(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8821C) & BIT_MASK_WAKE_MIN_F2F_8821C) - +#define BIT_WAKE_MIN_F2F_8821C(x) \ + (((x) & BIT_MASK_WAKE_MIN_F2F_8821C) << BIT_SHIFT_WAKE_MIN_F2F_8821C) +#define BITS_WAKE_MIN_F2F_8821C \ + (BIT_MASK_WAKE_MIN_F2F_8821C << BIT_SHIFT_WAKE_MIN_F2F_8821C) +#define BIT_CLEAR_WAKE_MIN_F2F_8821C(x) ((x) & (~BITS_WAKE_MIN_F2F_8821C)) +#define BIT_GET_WAKE_MIN_F2F_8821C(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8821C) & BIT_MASK_WAKE_MIN_F2F_8821C) +#define BIT_SET_WAKE_MIN_F2F_8821C(x, v) \ + (BIT_CLEAR_WAKE_MIN_F2F_8821C(x) | BIT_WAKE_MIN_F2F_8821C(v)) #define BIT_APP_CPU_ACT_V1_8821C BIT(3) #define BIT_APP_OBFF_V1_8821C BIT(2) @@ -10871,31 +18168,65 @@ #define BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C 24 #define BIT_MASK_RX_HIGH_TIMER_IDX_8821C 0x7 -#define BIT_RX_HIGH_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) -#define BIT_GET_RX_HIGH_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C) - - +#define BIT_RX_HIGH_TIMER_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C) \ + << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) +#define BITS_RX_HIGH_TIMER_IDX_8821C \ + (BIT_MASK_RX_HIGH_TIMER_IDX_8821C << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8821C(x) \ + ((x) & (~BITS_RX_HIGH_TIMER_IDX_8821C)) +#define BIT_GET_RX_HIGH_TIMER_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) & \ + BIT_MASK_RX_HIGH_TIMER_IDX_8821C) +#define BIT_SET_RX_HIGH_TIMER_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_HIGH_TIMER_IDX_8821C(x) | BIT_RX_HIGH_TIMER_IDX_8821C(v)) #define BIT_SHIFT_RX_MED_TIMER_IDX_8821C 16 #define BIT_MASK_RX_MED_TIMER_IDX_8821C 0x7 -#define BIT_RX_MED_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8821C) << BIT_SHIFT_RX_MED_TIMER_IDX_8821C) -#define BIT_GET_RX_MED_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8821C) & BIT_MASK_RX_MED_TIMER_IDX_8821C) - - +#define BIT_RX_MED_TIMER_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_MED_TIMER_IDX_8821C) \ + << BIT_SHIFT_RX_MED_TIMER_IDX_8821C) +#define BITS_RX_MED_TIMER_IDX_8821C \ + (BIT_MASK_RX_MED_TIMER_IDX_8821C << BIT_SHIFT_RX_MED_TIMER_IDX_8821C) +#define BIT_CLEAR_RX_MED_TIMER_IDX_8821C(x) \ + ((x) & (~BITS_RX_MED_TIMER_IDX_8821C)) +#define BIT_GET_RX_MED_TIMER_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8821C) & \ + BIT_MASK_RX_MED_TIMER_IDX_8821C) +#define BIT_SET_RX_MED_TIMER_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_MED_TIMER_IDX_8821C(x) | BIT_RX_MED_TIMER_IDX_8821C(v)) #define BIT_SHIFT_RX_LOW_TIMER_IDX_8821C 8 #define BIT_MASK_RX_LOW_TIMER_IDX_8821C 0x7 -#define BIT_RX_LOW_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8821C) << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) -#define BIT_GET_RX_LOW_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) & BIT_MASK_RX_LOW_TIMER_IDX_8821C) - - +#define BIT_RX_LOW_TIMER_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8821C) \ + << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) +#define BITS_RX_LOW_TIMER_IDX_8821C \ + (BIT_MASK_RX_LOW_TIMER_IDX_8821C << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) +#define BIT_CLEAR_RX_LOW_TIMER_IDX_8821C(x) \ + ((x) & (~BITS_RX_LOW_TIMER_IDX_8821C)) +#define BIT_GET_RX_LOW_TIMER_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) & \ + BIT_MASK_RX_LOW_TIMER_IDX_8821C) +#define BIT_SET_RX_LOW_TIMER_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_LOW_TIMER_IDX_8821C(x) | BIT_RX_LOW_TIMER_IDX_8821C(v)) #define BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C 0 #define BIT_MASK_OBFF_INT_TIMER_IDX_8821C 0x7 -#define BIT_OBFF_INT_TIMER_IDX_8821C(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) -#define BIT_GET_OBFF_INT_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C) - - +#define BIT_OBFF_INT_TIMER_IDX_8821C(x) \ + (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C) \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) +#define BITS_OBFF_INT_TIMER_IDX_8821C \ + (BIT_MASK_OBFF_INT_TIMER_IDX_8821C \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8821C(x) \ + ((x) & (~BITS_OBFF_INT_TIMER_IDX_8821C)) +#define BIT_GET_OBFF_INT_TIMER_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) & \ + BIT_MASK_OBFF_INT_TIMER_IDX_8821C) +#define BIT_SET_OBFF_INT_TIMER_IDX_8821C(x, v) \ + (BIT_CLEAR_OBFF_INT_TIMER_IDX_8821C(x) | \ + BIT_OBFF_INT_TIMER_IDX_8821C(v)) /* 2 REG_LTR_CTRL_BASIC_8821C */ #define BIT_LTR_EN_V1_8821C BIT(31) @@ -10911,116 +18242,224 @@ #define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C 20 #define BIT_MASK_HIGH_RATE_TRIG_SEL_8821C 0x3 -#define BIT_HIGH_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) -#define BIT_GET_HIGH_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) - - +#define BIT_HIGH_RATE_TRIG_SEL_8821C(x) \ + (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) +#define BITS_HIGH_RATE_TRIG_SEL_8821C \ + (BIT_MASK_HIGH_RATE_TRIG_SEL_8821C \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8821C(x) \ + ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8821C)) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) & \ + BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) +#define BIT_SET_HIGH_RATE_TRIG_SEL_8821C(x, v) \ + (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8821C(x) | \ + BIT_HIGH_RATE_TRIG_SEL_8821C(v)) #define BIT_SHIFT_MED_RATE_TRIG_SEL_8821C 18 #define BIT_MASK_MED_RATE_TRIG_SEL_8821C 0x3 -#define BIT_MED_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8821C) << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) -#define BIT_GET_MED_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) & BIT_MASK_MED_RATE_TRIG_SEL_8821C) - - +#define BIT_MED_RATE_TRIG_SEL_8821C(x) \ + (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8821C) \ + << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) +#define BITS_MED_RATE_TRIG_SEL_8821C \ + (BIT_MASK_MED_RATE_TRIG_SEL_8821C << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) +#define BIT_CLEAR_MED_RATE_TRIG_SEL_8821C(x) \ + ((x) & (~BITS_MED_RATE_TRIG_SEL_8821C)) +#define BIT_GET_MED_RATE_TRIG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) & \ + BIT_MASK_MED_RATE_TRIG_SEL_8821C) +#define BIT_SET_MED_RATE_TRIG_SEL_8821C(x, v) \ + (BIT_CLEAR_MED_RATE_TRIG_SEL_8821C(x) | BIT_MED_RATE_TRIG_SEL_8821C(v)) #define BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C 16 #define BIT_MASK_LOW_RATE_TRIG_SEL_8821C 0x3 -#define BIT_LOW_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) -#define BIT_GET_LOW_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C) - - +#define BIT_LOW_RATE_TRIG_SEL_8821C(x) \ + (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C) \ + << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) +#define BITS_LOW_RATE_TRIG_SEL_8821C \ + (BIT_MASK_LOW_RATE_TRIG_SEL_8821C << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8821C(x) \ + ((x) & (~BITS_LOW_RATE_TRIG_SEL_8821C)) +#define BIT_GET_LOW_RATE_TRIG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) & \ + BIT_MASK_LOW_RATE_TRIG_SEL_8821C) +#define BIT_SET_LOW_RATE_TRIG_SEL_8821C(x, v) \ + (BIT_CLEAR_LOW_RATE_TRIG_SEL_8821C(x) | BIT_LOW_RATE_TRIG_SEL_8821C(v)) #define BIT_SHIFT_HIGH_RATE_BD_IDX_8821C 8 #define BIT_MASK_HIGH_RATE_BD_IDX_8821C 0x7f -#define BIT_HIGH_RATE_BD_IDX_8821C(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8821C) << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) -#define BIT_GET_HIGH_RATE_BD_IDX_8821C(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) & BIT_MASK_HIGH_RATE_BD_IDX_8821C) - - +#define BIT_HIGH_RATE_BD_IDX_8821C(x) \ + (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8821C) \ + << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) +#define BITS_HIGH_RATE_BD_IDX_8821C \ + (BIT_MASK_HIGH_RATE_BD_IDX_8821C << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) +#define BIT_CLEAR_HIGH_RATE_BD_IDX_8821C(x) \ + ((x) & (~BITS_HIGH_RATE_BD_IDX_8821C)) +#define BIT_GET_HIGH_RATE_BD_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) & \ + BIT_MASK_HIGH_RATE_BD_IDX_8821C) +#define BIT_SET_HIGH_RATE_BD_IDX_8821C(x, v) \ + (BIT_CLEAR_HIGH_RATE_BD_IDX_8821C(x) | BIT_HIGH_RATE_BD_IDX_8821C(v)) #define BIT_SHIFT_LOW_RATE_BD_IDX_8821C 0 #define BIT_MASK_LOW_RATE_BD_IDX_8821C 0x7f -#define BIT_LOW_RATE_BD_IDX_8821C(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8821C) << BIT_SHIFT_LOW_RATE_BD_IDX_8821C) -#define BIT_GET_LOW_RATE_BD_IDX_8821C(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8821C) & BIT_MASK_LOW_RATE_BD_IDX_8821C) - - +#define BIT_LOW_RATE_BD_IDX_8821C(x) \ + (((x) & BIT_MASK_LOW_RATE_BD_IDX_8821C) \ + << BIT_SHIFT_LOW_RATE_BD_IDX_8821C) +#define BITS_LOW_RATE_BD_IDX_8821C \ + (BIT_MASK_LOW_RATE_BD_IDX_8821C << BIT_SHIFT_LOW_RATE_BD_IDX_8821C) +#define BIT_CLEAR_LOW_RATE_BD_IDX_8821C(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8821C)) +#define BIT_GET_LOW_RATE_BD_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8821C) & \ + BIT_MASK_LOW_RATE_BD_IDX_8821C) +#define BIT_SET_LOW_RATE_BD_IDX_8821C(x, v) \ + (BIT_CLEAR_LOW_RATE_BD_IDX_8821C(x) | BIT_LOW_RATE_BD_IDX_8821C(v)) /* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8821C */ #define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C 24 #define BIT_MASK_RX_EMPTY_TIMER_IDX_8821C 0x7 -#define BIT_RX_EMPTY_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) -#define BIT_GET_RX_EMPTY_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) - - +#define BIT_RX_EMPTY_TIMER_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) +#define BITS_RX_EMPTY_TIMER_IDX_8821C \ + (BIT_MASK_RX_EMPTY_TIMER_IDX_8821C \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8821C(x) \ + ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8821C)) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) & \ + BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) +#define BIT_SET_RX_EMPTY_TIMER_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8821C(x) | \ + BIT_RX_EMPTY_TIMER_IDX_8821C(v)) #define BIT_SHIFT_RX_AFULL_TH_IDX_8821C 20 #define BIT_MASK_RX_AFULL_TH_IDX_8821C 0x7 -#define BIT_RX_AFULL_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8821C) << BIT_SHIFT_RX_AFULL_TH_IDX_8821C) -#define BIT_GET_RX_AFULL_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8821C) & BIT_MASK_RX_AFULL_TH_IDX_8821C) - - +#define BIT_RX_AFULL_TH_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_AFULL_TH_IDX_8821C) \ + << BIT_SHIFT_RX_AFULL_TH_IDX_8821C) +#define BITS_RX_AFULL_TH_IDX_8821C \ + (BIT_MASK_RX_AFULL_TH_IDX_8821C << BIT_SHIFT_RX_AFULL_TH_IDX_8821C) +#define BIT_CLEAR_RX_AFULL_TH_IDX_8821C(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8821C)) +#define BIT_GET_RX_AFULL_TH_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8821C) & \ + BIT_MASK_RX_AFULL_TH_IDX_8821C) +#define BIT_SET_RX_AFULL_TH_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_AFULL_TH_IDX_8821C(x) | BIT_RX_AFULL_TH_IDX_8821C(v)) #define BIT_SHIFT_RX_HIGH_TH_IDX_8821C 16 #define BIT_MASK_RX_HIGH_TH_IDX_8821C 0x7 -#define BIT_RX_HIGH_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8821C) << BIT_SHIFT_RX_HIGH_TH_IDX_8821C) -#define BIT_GET_RX_HIGH_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8821C) & BIT_MASK_RX_HIGH_TH_IDX_8821C) - - +#define BIT_RX_HIGH_TH_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_HIGH_TH_IDX_8821C) \ + << BIT_SHIFT_RX_HIGH_TH_IDX_8821C) +#define BITS_RX_HIGH_TH_IDX_8821C \ + (BIT_MASK_RX_HIGH_TH_IDX_8821C << BIT_SHIFT_RX_HIGH_TH_IDX_8821C) +#define BIT_CLEAR_RX_HIGH_TH_IDX_8821C(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8821C)) +#define BIT_GET_RX_HIGH_TH_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8821C) & \ + BIT_MASK_RX_HIGH_TH_IDX_8821C) +#define BIT_SET_RX_HIGH_TH_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_HIGH_TH_IDX_8821C(x) | BIT_RX_HIGH_TH_IDX_8821C(v)) #define BIT_SHIFT_RX_MED_TH_IDX_8821C 12 #define BIT_MASK_RX_MED_TH_IDX_8821C 0x7 -#define BIT_RX_MED_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8821C) << BIT_SHIFT_RX_MED_TH_IDX_8821C) -#define BIT_GET_RX_MED_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8821C) & BIT_MASK_RX_MED_TH_IDX_8821C) - - +#define BIT_RX_MED_TH_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_MED_TH_IDX_8821C) << BIT_SHIFT_RX_MED_TH_IDX_8821C) +#define BITS_RX_MED_TH_IDX_8821C \ + (BIT_MASK_RX_MED_TH_IDX_8821C << BIT_SHIFT_RX_MED_TH_IDX_8821C) +#define BIT_CLEAR_RX_MED_TH_IDX_8821C(x) ((x) & (~BITS_RX_MED_TH_IDX_8821C)) +#define BIT_GET_RX_MED_TH_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8821C) & BIT_MASK_RX_MED_TH_IDX_8821C) +#define BIT_SET_RX_MED_TH_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_MED_TH_IDX_8821C(x) | BIT_RX_MED_TH_IDX_8821C(v)) #define BIT_SHIFT_RX_LOW_TH_IDX_8821C 8 #define BIT_MASK_RX_LOW_TH_IDX_8821C 0x7 -#define BIT_RX_LOW_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8821C) << BIT_SHIFT_RX_LOW_TH_IDX_8821C) -#define BIT_GET_RX_LOW_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8821C) & BIT_MASK_RX_LOW_TH_IDX_8821C) - - +#define BIT_RX_LOW_TH_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_LOW_TH_IDX_8821C) << BIT_SHIFT_RX_LOW_TH_IDX_8821C) +#define BITS_RX_LOW_TH_IDX_8821C \ + (BIT_MASK_RX_LOW_TH_IDX_8821C << BIT_SHIFT_RX_LOW_TH_IDX_8821C) +#define BIT_CLEAR_RX_LOW_TH_IDX_8821C(x) ((x) & (~BITS_RX_LOW_TH_IDX_8821C)) +#define BIT_GET_RX_LOW_TH_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8821C) & BIT_MASK_RX_LOW_TH_IDX_8821C) +#define BIT_SET_RX_LOW_TH_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_LOW_TH_IDX_8821C(x) | BIT_RX_LOW_TH_IDX_8821C(v)) #define BIT_SHIFT_LTR_SPACE_IDX_8821C 4 #define BIT_MASK_LTR_SPACE_IDX_8821C 0x3 -#define BIT_LTR_SPACE_IDX_8821C(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8821C) << BIT_SHIFT_LTR_SPACE_IDX_8821C) -#define BIT_GET_LTR_SPACE_IDX_8821C(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8821C) & BIT_MASK_LTR_SPACE_IDX_8821C) - - +#define BIT_LTR_SPACE_IDX_8821C(x) \ + (((x) & BIT_MASK_LTR_SPACE_IDX_8821C) << BIT_SHIFT_LTR_SPACE_IDX_8821C) +#define BITS_LTR_SPACE_IDX_8821C \ + (BIT_MASK_LTR_SPACE_IDX_8821C << BIT_SHIFT_LTR_SPACE_IDX_8821C) +#define BIT_CLEAR_LTR_SPACE_IDX_8821C(x) ((x) & (~BITS_LTR_SPACE_IDX_8821C)) +#define BIT_GET_LTR_SPACE_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8821C) & BIT_MASK_LTR_SPACE_IDX_8821C) +#define BIT_SET_LTR_SPACE_IDX_8821C(x, v) \ + (BIT_CLEAR_LTR_SPACE_IDX_8821C(x) | BIT_LTR_SPACE_IDX_8821C(v)) #define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C 0 #define BIT_MASK_LTR_IDLE_TIMER_IDX_8821C 0x7 -#define BIT_LTR_IDLE_TIMER_IDX_8821C(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) -#define BIT_GET_LTR_IDLE_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) - - +#define BIT_LTR_IDLE_TIMER_IDX_8821C(x) \ + (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) +#define BITS_LTR_IDLE_TIMER_IDX_8821C \ + (BIT_MASK_LTR_IDLE_TIMER_IDX_8821C \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8821C(x) \ + ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8821C)) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) & \ + BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) +#define BIT_SET_LTR_IDLE_TIMER_IDX_8821C(x, v) \ + (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8821C(x) | \ + BIT_LTR_IDLE_TIMER_IDX_8821C(v)) /* 2 REG_LTR_IDLE_LATENCY_V1_8821C */ #define BIT_SHIFT_LTR_IDLE_L_8821C 0 #define BIT_MASK_LTR_IDLE_L_8821C 0xffffffffL -#define BIT_LTR_IDLE_L_8821C(x) (((x) & BIT_MASK_LTR_IDLE_L_8821C) << BIT_SHIFT_LTR_IDLE_L_8821C) -#define BIT_GET_LTR_IDLE_L_8821C(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8821C) & BIT_MASK_LTR_IDLE_L_8821C) - - +#define BIT_LTR_IDLE_L_8821C(x) \ + (((x) & BIT_MASK_LTR_IDLE_L_8821C) << BIT_SHIFT_LTR_IDLE_L_8821C) +#define BITS_LTR_IDLE_L_8821C \ + (BIT_MASK_LTR_IDLE_L_8821C << BIT_SHIFT_LTR_IDLE_L_8821C) +#define BIT_CLEAR_LTR_IDLE_L_8821C(x) ((x) & (~BITS_LTR_IDLE_L_8821C)) +#define BIT_GET_LTR_IDLE_L_8821C(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_L_8821C) & BIT_MASK_LTR_IDLE_L_8821C) +#define BIT_SET_LTR_IDLE_L_8821C(x, v) \ + (BIT_CLEAR_LTR_IDLE_L_8821C(x) | BIT_LTR_IDLE_L_8821C(v)) /* 2 REG_LTR_ACTIVE_LATENCY_V1_8821C */ #define BIT_SHIFT_LTR_ACT_L_8821C 0 #define BIT_MASK_LTR_ACT_L_8821C 0xffffffffL -#define BIT_LTR_ACT_L_8821C(x) (((x) & BIT_MASK_LTR_ACT_L_8821C) << BIT_SHIFT_LTR_ACT_L_8821C) -#define BIT_GET_LTR_ACT_L_8821C(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8821C) & BIT_MASK_LTR_ACT_L_8821C) - - +#define BIT_LTR_ACT_L_8821C(x) \ + (((x) & BIT_MASK_LTR_ACT_L_8821C) << BIT_SHIFT_LTR_ACT_L_8821C) +#define BITS_LTR_ACT_L_8821C \ + (BIT_MASK_LTR_ACT_L_8821C << BIT_SHIFT_LTR_ACT_L_8821C) +#define BIT_CLEAR_LTR_ACT_L_8821C(x) ((x) & (~BITS_LTR_ACT_L_8821C)) +#define BIT_GET_LTR_ACT_L_8821C(x) \ + (((x) >> BIT_SHIFT_LTR_ACT_L_8821C) & BIT_MASK_LTR_ACT_L_8821C) +#define BIT_SET_LTR_ACT_L_8821C(x, v) \ + (BIT_CLEAR_LTR_ACT_L_8821C(x) | BIT_LTR_ACT_L_8821C(v)) /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C */ #define BIT_SHIFT_TRAIN_STA_ADDR_0_8821C 0 #define BIT_MASK_TRAIN_STA_ADDR_0_8821C 0xffffffffL -#define BIT_TRAIN_STA_ADDR_0_8821C(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8821C) << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) -#define BIT_GET_TRAIN_STA_ADDR_0_8821C(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) & BIT_MASK_TRAIN_STA_ADDR_0_8821C) - - +#define BIT_TRAIN_STA_ADDR_0_8821C(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8821C) \ + << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) +#define BITS_TRAIN_STA_ADDR_0_8821C \ + (BIT_MASK_TRAIN_STA_ADDR_0_8821C << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) +#define BIT_CLEAR_TRAIN_STA_ADDR_0_8821C(x) \ + ((x) & (~BITS_TRAIN_STA_ADDR_0_8821C)) +#define BIT_GET_TRAIN_STA_ADDR_0_8821C(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) & \ + BIT_MASK_TRAIN_STA_ADDR_0_8821C) +#define BIT_SET_TRAIN_STA_ADDR_0_8821C(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_0_8821C(x) | BIT_TRAIN_STA_ADDR_0_8821C(v)) /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C */ #define BIT_APPEND_MACID_IN_RESP_EN_1_8821C BIT(18) @@ -11029,18 +18468,34 @@ #define BIT_SHIFT_TRAIN_STA_ADDR_1_8821C 0 #define BIT_MASK_TRAIN_STA_ADDR_1_8821C 0xffff -#define BIT_TRAIN_STA_ADDR_1_8821C(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8821C) << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) -#define BIT_GET_TRAIN_STA_ADDR_1_8821C(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) & BIT_MASK_TRAIN_STA_ADDR_1_8821C) - - +#define BIT_TRAIN_STA_ADDR_1_8821C(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8821C) \ + << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) +#define BITS_TRAIN_STA_ADDR_1_8821C \ + (BIT_MASK_TRAIN_STA_ADDR_1_8821C << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) +#define BIT_CLEAR_TRAIN_STA_ADDR_1_8821C(x) \ + ((x) & (~BITS_TRAIN_STA_ADDR_1_8821C)) +#define BIT_GET_TRAIN_STA_ADDR_1_8821C(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) & \ + BIT_MASK_TRAIN_STA_ADDR_1_8821C) +#define BIT_SET_TRAIN_STA_ADDR_1_8821C(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_1_8821C(x) | BIT_TRAIN_STA_ADDR_1_8821C(v)) /* 2 REG_WMAC_PKTCNT_RWD_8821C */ #define BIT_SHIFT_PKTCNT_BSSIDMAP_8821C 4 #define BIT_MASK_PKTCNT_BSSIDMAP_8821C 0xf -#define BIT_PKTCNT_BSSIDMAP_8821C(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8821C) << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) -#define BIT_GET_PKTCNT_BSSIDMAP_8821C(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) & BIT_MASK_PKTCNT_BSSIDMAP_8821C) - +#define BIT_PKTCNT_BSSIDMAP_8821C(x) \ + (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8821C) \ + << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) +#define BITS_PKTCNT_BSSIDMAP_8821C \ + (BIT_MASK_PKTCNT_BSSIDMAP_8821C << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) +#define BIT_CLEAR_PKTCNT_BSSIDMAP_8821C(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8821C)) +#define BIT_GET_PKTCNT_BSSIDMAP_8821C(x) \ + (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) & \ + BIT_MASK_PKTCNT_BSSIDMAP_8821C) +#define BIT_SET_PKTCNT_BSSIDMAP_8821C(x, v) \ + (BIT_CLEAR_PKTCNT_BSSIDMAP_8821C(x) | BIT_PKTCNT_BSSIDMAP_8821C(v)) #define BIT_PKTCNT_CNTRST_8821C BIT(1) #define BIT_PKTCNT_CNTEN_8821C BIT(0) @@ -11051,40 +18506,77 @@ #define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C 0 #define BIT_MASK_WMAC_PKTCNT_CFGAD_8821C 0xff -#define BIT_WMAC_PKTCNT_CFGAD_8821C(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) -#define BIT_GET_WMAC_PKTCNT_CFGAD_8821C(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) - - +#define BIT_WMAC_PKTCNT_CFGAD_8821C(x) \ + (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) \ + << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) +#define BITS_WMAC_PKTCNT_CFGAD_8821C \ + (BIT_MASK_WMAC_PKTCNT_CFGAD_8821C << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) +#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8821C(x) \ + ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8821C)) +#define BIT_GET_WMAC_PKTCNT_CFGAD_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) & \ + BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) +#define BIT_SET_WMAC_PKTCNT_CFGAD_8821C(x, v) \ + (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8821C(x) | BIT_WMAC_PKTCNT_CFGAD_8821C(v)) /* 2 REG_IQ_DUMP_8821C */ -#define BIT_SHIFT_DUMP_OK_ADDR_8821C 15 -#define BIT_MASK_DUMP_OK_ADDR_8821C 0x1ffff -#define BIT_DUMP_OK_ADDR_8821C(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8821C) << BIT_SHIFT_DUMP_OK_ADDR_8821C) -#define BIT_GET_DUMP_OK_ADDR_8821C(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8821C) & BIT_MASK_DUMP_OK_ADDR_8821C) - - +#define BIT_SHIFT_DUMP_OK_ADDR_8821C 16 +#define BIT_MASK_DUMP_OK_ADDR_8821C 0xffff +#define BIT_DUMP_OK_ADDR_8821C(x) \ + (((x) & BIT_MASK_DUMP_OK_ADDR_8821C) << BIT_SHIFT_DUMP_OK_ADDR_8821C) +#define BITS_DUMP_OK_ADDR_8821C \ + (BIT_MASK_DUMP_OK_ADDR_8821C << BIT_SHIFT_DUMP_OK_ADDR_8821C) +#define BIT_CLEAR_DUMP_OK_ADDR_8821C(x) ((x) & (~BITS_DUMP_OK_ADDR_8821C)) +#define BIT_GET_DUMP_OK_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8821C) & BIT_MASK_DUMP_OK_ADDR_8821C) +#define BIT_SET_DUMP_OK_ADDR_8821C(x, v) \ + (BIT_CLEAR_DUMP_OK_ADDR_8821C(x) | BIT_DUMP_OK_ADDR_8821C(v)) #define BIT_SHIFT_R_TRIG_TIME_SEL_8821C 8 #define BIT_MASK_R_TRIG_TIME_SEL_8821C 0x7f -#define BIT_R_TRIG_TIME_SEL_8821C(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8821C) << BIT_SHIFT_R_TRIG_TIME_SEL_8821C) -#define BIT_GET_R_TRIG_TIME_SEL_8821C(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8821C) & BIT_MASK_R_TRIG_TIME_SEL_8821C) - - +#define BIT_R_TRIG_TIME_SEL_8821C(x) \ + (((x) & BIT_MASK_R_TRIG_TIME_SEL_8821C) \ + << BIT_SHIFT_R_TRIG_TIME_SEL_8821C) +#define BITS_R_TRIG_TIME_SEL_8821C \ + (BIT_MASK_R_TRIG_TIME_SEL_8821C << BIT_SHIFT_R_TRIG_TIME_SEL_8821C) +#define BIT_CLEAR_R_TRIG_TIME_SEL_8821C(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8821C)) +#define BIT_GET_R_TRIG_TIME_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8821C) & \ + BIT_MASK_R_TRIG_TIME_SEL_8821C) +#define BIT_SET_R_TRIG_TIME_SEL_8821C(x, v) \ + (BIT_CLEAR_R_TRIG_TIME_SEL_8821C(x) | BIT_R_TRIG_TIME_SEL_8821C(v)) #define BIT_SHIFT_R_MAC_TRIG_SEL_8821C 6 #define BIT_MASK_R_MAC_TRIG_SEL_8821C 0x3 -#define BIT_R_MAC_TRIG_SEL_8821C(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8821C) << BIT_SHIFT_R_MAC_TRIG_SEL_8821C) -#define BIT_GET_R_MAC_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8821C) & BIT_MASK_R_MAC_TRIG_SEL_8821C) - +#define BIT_R_MAC_TRIG_SEL_8821C(x) \ + (((x) & BIT_MASK_R_MAC_TRIG_SEL_8821C) \ + << BIT_SHIFT_R_MAC_TRIG_SEL_8821C) +#define BITS_R_MAC_TRIG_SEL_8821C \ + (BIT_MASK_R_MAC_TRIG_SEL_8821C << BIT_SHIFT_R_MAC_TRIG_SEL_8821C) +#define BIT_CLEAR_R_MAC_TRIG_SEL_8821C(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8821C)) +#define BIT_GET_R_MAC_TRIG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8821C) & \ + BIT_MASK_R_MAC_TRIG_SEL_8821C) +#define BIT_SET_R_MAC_TRIG_SEL_8821C(x, v) \ + (BIT_CLEAR_R_MAC_TRIG_SEL_8821C(x) | BIT_R_MAC_TRIG_SEL_8821C(v)) #define BIT_MAC_TRIG_REG_8821C BIT(5) #define BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C 3 #define BIT_MASK_R_LEVEL_PULSE_SEL_8821C 0x3 -#define BIT_R_LEVEL_PULSE_SEL_8821C(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) -#define BIT_GET_R_LEVEL_PULSE_SEL_8821C(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C) - +#define BIT_R_LEVEL_PULSE_SEL_8821C(x) \ + (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C) \ + << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) +#define BITS_R_LEVEL_PULSE_SEL_8821C \ + (BIT_MASK_R_LEVEL_PULSE_SEL_8821C << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8821C(x) \ + ((x) & (~BITS_R_LEVEL_PULSE_SEL_8821C)) +#define BIT_GET_R_LEVEL_PULSE_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) & \ + BIT_MASK_R_LEVEL_PULSE_SEL_8821C) +#define BIT_SET_R_LEVEL_PULSE_SEL_8821C(x, v) \ + (BIT_CLEAR_R_LEVEL_PULSE_SEL_8821C(x) | BIT_R_LEVEL_PULSE_SEL_8821C(v)) #define BIT_EN_LA_MAC_8821C BIT(2) #define BIT_R_EN_IQDUMP_8821C BIT(1) @@ -11094,19 +18586,39 @@ #define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C 0 #define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC_1_8821C(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) -#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) - - +#define BIT_R_WMAC_MASK_LA_MAC_1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) +#define BITS_R_WMAC_MASK_LA_MAC_1_8821C \ + (BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8821C(x) \ + ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8821C)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) & \ + BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) +#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8821C(x) | \ + BIT_R_WMAC_MASK_LA_MAC_1_8821C(v)) /* 2 REG_IQ_DUMP_2_8821C */ #define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C 0 #define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC_2_8821C(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) -#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) - - +#define BIT_R_WMAC_MATCH_REF_MAC_2_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) +#define BITS_R_WMAC_MATCH_REF_MAC_2_8821C \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8821C(x) \ + ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8821C)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8821C(x) | \ + BIT_R_WMAC_MATCH_REF_MAC_2_8821C(v)) /* 2 REG_WMAC_FTM_CTL_8821C */ #define BIT_RXFTM_TXACK_SC_8821C BIT(6) @@ -11122,25 +18634,46 @@ #define BIT_SHIFT_R_OFDM_LEN_8821C 26 #define BIT_MASK_R_OFDM_LEN_8821C 0x3f -#define BIT_R_OFDM_LEN_8821C(x) (((x) & BIT_MASK_R_OFDM_LEN_8821C) << BIT_SHIFT_R_OFDM_LEN_8821C) -#define BIT_GET_R_OFDM_LEN_8821C(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8821C) & BIT_MASK_R_OFDM_LEN_8821C) - - +#define BIT_R_OFDM_LEN_8821C(x) \ + (((x) & BIT_MASK_R_OFDM_LEN_8821C) << BIT_SHIFT_R_OFDM_LEN_8821C) +#define BITS_R_OFDM_LEN_8821C \ + (BIT_MASK_R_OFDM_LEN_8821C << BIT_SHIFT_R_OFDM_LEN_8821C) +#define BIT_CLEAR_R_OFDM_LEN_8821C(x) ((x) & (~BITS_R_OFDM_LEN_8821C)) +#define BIT_GET_R_OFDM_LEN_8821C(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN_8821C) & BIT_MASK_R_OFDM_LEN_8821C) +#define BIT_SET_R_OFDM_LEN_8821C(x, v) \ + (BIT_CLEAR_R_OFDM_LEN_8821C(x) | BIT_R_OFDM_LEN_8821C(v)) #define BIT_SHIFT_R_CCK_LEN_8821C 0 #define BIT_MASK_R_CCK_LEN_8821C 0xffff -#define BIT_R_CCK_LEN_8821C(x) (((x) & BIT_MASK_R_CCK_LEN_8821C) << BIT_SHIFT_R_CCK_LEN_8821C) -#define BIT_GET_R_CCK_LEN_8821C(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8821C) & BIT_MASK_R_CCK_LEN_8821C) - - +#define BIT_R_CCK_LEN_8821C(x) \ + (((x) & BIT_MASK_R_CCK_LEN_8821C) << BIT_SHIFT_R_CCK_LEN_8821C) +#define BITS_R_CCK_LEN_8821C \ + (BIT_MASK_R_CCK_LEN_8821C << BIT_SHIFT_R_CCK_LEN_8821C) +#define BIT_CLEAR_R_CCK_LEN_8821C(x) ((x) & (~BITS_R_CCK_LEN_8821C)) +#define BIT_GET_R_CCK_LEN_8821C(x) \ + (((x) >> BIT_SHIFT_R_CCK_LEN_8821C) & BIT_MASK_R_CCK_LEN_8821C) +#define BIT_SET_R_CCK_LEN_8821C(x, v) \ + (BIT_CLEAR_R_CCK_LEN_8821C(x) | BIT_R_CCK_LEN_8821C(v)) /* 2 REG_WMAC_OPTION_FUNCTION_1_8821C */ #define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C 24 #define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) - +#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) +#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8821C \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) \ + ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8821C)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) | \ + BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(v)) #define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8821C BIT(23) #define BIT_R_WMAC_RXRST_DLY_1_8821C BIT(22) @@ -11171,10 +18704,20 @@ #define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C 0 #define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C 0xffff -#define BIT_R_WMAC_RX_FIL_LEN_2_8821C(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) -#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) - - +#define BIT_R_WMAC_RX_FIL_LEN_2_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) +#define BITS_R_WMAC_RX_FIL_LEN_2_8821C \ + (BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8821C(x) \ + ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8821C)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) & \ + BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) +#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8821C(x) | \ + BIT_R_WMAC_RX_FIL_LEN_2_8821C(v)) /* 2 REG_RX_FILTER_FUNCTION_8821C */ #define BIT_R_WMAC_MHRDDY_LATCH_8821C BIT(14) @@ -11199,35 +18742,60 @@ #define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C 0 #define BIT_MASK_R_WMAC_TXNDP_SIGB_8821C 0x1fffff -#define BIT_R_WMAC_TXNDP_SIGB_8821C(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) -#define BIT_GET_R_WMAC_TXNDP_SIGB_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) - - +#define BIT_R_WMAC_TXNDP_SIGB_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) \ + << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) +#define BITS_R_WMAC_TXNDP_SIGB_8821C \ + (BIT_MASK_R_WMAC_TXNDP_SIGB_8821C << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8821C(x) \ + ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8821C)) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) & \ + BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) +#define BIT_SET_R_WMAC_TXNDP_SIGB_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8821C(x) | BIT_R_WMAC_TXNDP_SIGB_8821C(v)) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8821C */ #define BIT_SHIFT_R_MAC_DBG_SHIFT_8821C 8 #define BIT_MASK_R_MAC_DBG_SHIFT_8821C 0x7 -#define BIT_R_MAC_DBG_SHIFT_8821C(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8821C) << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) -#define BIT_GET_R_MAC_DBG_SHIFT_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) & BIT_MASK_R_MAC_DBG_SHIFT_8821C) - - +#define BIT_R_MAC_DBG_SHIFT_8821C(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8821C) \ + << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) +#define BITS_R_MAC_DBG_SHIFT_8821C \ + (BIT_MASK_R_MAC_DBG_SHIFT_8821C << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) +#define BIT_CLEAR_R_MAC_DBG_SHIFT_8821C(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8821C)) +#define BIT_GET_R_MAC_DBG_SHIFT_8821C(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) & \ + BIT_MASK_R_MAC_DBG_SHIFT_8821C) +#define BIT_SET_R_MAC_DBG_SHIFT_8821C(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SHIFT_8821C(x) | BIT_R_MAC_DBG_SHIFT_8821C(v)) #define BIT_SHIFT_R_MAC_DBG_SEL_8821C 0 #define BIT_MASK_R_MAC_DBG_SEL_8821C 0x3 -#define BIT_R_MAC_DBG_SEL_8821C(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8821C) << BIT_SHIFT_R_MAC_DBG_SEL_8821C) -#define BIT_GET_R_MAC_DBG_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8821C) & BIT_MASK_R_MAC_DBG_SEL_8821C) - - +#define BIT_R_MAC_DBG_SEL_8821C(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SEL_8821C) << BIT_SHIFT_R_MAC_DBG_SEL_8821C) +#define BITS_R_MAC_DBG_SEL_8821C \ + (BIT_MASK_R_MAC_DBG_SEL_8821C << BIT_SHIFT_R_MAC_DBG_SEL_8821C) +#define BIT_CLEAR_R_MAC_DBG_SEL_8821C(x) ((x) & (~BITS_R_MAC_DBG_SEL_8821C)) +#define BIT_GET_R_MAC_DBG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8821C) & BIT_MASK_R_MAC_DBG_SEL_8821C) +#define BIT_SET_R_MAC_DBG_SEL_8821C(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SEL_8821C(x) | BIT_R_MAC_DBG_SEL_8821C(v)) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C */ #define BIT_SHIFT_R_MAC_DEBUG_1_8821C 0 #define BIT_MASK_R_MAC_DEBUG_1_8821C 0xffffffffL -#define BIT_R_MAC_DEBUG_1_8821C(x) (((x) & BIT_MASK_R_MAC_DEBUG_1_8821C) << BIT_SHIFT_R_MAC_DEBUG_1_8821C) -#define BIT_GET_R_MAC_DEBUG_1_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8821C) & BIT_MASK_R_MAC_DEBUG_1_8821C) - - +#define BIT_R_MAC_DEBUG_1_8821C(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG_1_8821C) << BIT_SHIFT_R_MAC_DEBUG_1_8821C) +#define BITS_R_MAC_DEBUG_1_8821C \ + (BIT_MASK_R_MAC_DEBUG_1_8821C << BIT_SHIFT_R_MAC_DEBUG_1_8821C) +#define BIT_CLEAR_R_MAC_DEBUG_1_8821C(x) ((x) & (~BITS_R_MAC_DEBUG_1_8821C)) +#define BIT_GET_R_MAC_DEBUG_1_8821C(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8821C) & BIT_MASK_R_MAC_DEBUG_1_8821C) +#define BIT_SET_R_MAC_DEBUG_1_8821C(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG_1_8821C(x) | BIT_R_MAC_DEBUG_1_8821C(v)) /* 2 REG_WSEC_OPTION_8821C */ #define BIT_RXDEC_BM_MGNT_8821C BIT(22) @@ -11250,35 +18818,69 @@ #define BIT_SHIFT_WRITE_BYTE_EN_V1_8821C 16 #define BIT_MASK_WRITE_BYTE_EN_V1_8821C 0xf -#define BIT_WRITE_BYTE_EN_V1_8821C(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8821C) << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) -#define BIT_GET_WRITE_BYTE_EN_V1_8821C(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) & BIT_MASK_WRITE_BYTE_EN_V1_8821C) - - +#define BIT_WRITE_BYTE_EN_V1_8821C(x) \ + (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8821C) \ + << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) +#define BITS_WRITE_BYTE_EN_V1_8821C \ + (BIT_MASK_WRITE_BYTE_EN_V1_8821C << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) +#define BIT_CLEAR_WRITE_BYTE_EN_V1_8821C(x) \ + ((x) & (~BITS_WRITE_BYTE_EN_V1_8821C)) +#define BIT_GET_WRITE_BYTE_EN_V1_8821C(x) \ + (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) & \ + BIT_MASK_WRITE_BYTE_EN_V1_8821C) +#define BIT_SET_WRITE_BYTE_EN_V1_8821C(x, v) \ + (BIT_CLEAR_WRITE_BYTE_EN_V1_8821C(x) | BIT_WRITE_BYTE_EN_V1_8821C(v)) #define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C 0 #define BIT_MASK_LTECOEX_REG_ADDR_V1_8821C 0xffff -#define BIT_LTECOEX_REG_ADDR_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) -#define BIT_GET_LTECOEX_REG_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) - - +#define BIT_LTECOEX_REG_ADDR_V1_8821C(x) \ + (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) +#define BITS_LTECOEX_REG_ADDR_V1_8821C \ + (BIT_MASK_LTECOEX_REG_ADDR_V1_8821C \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) +#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8821C(x) \ + ((x) & (~BITS_LTECOEX_REG_ADDR_V1_8821C)) +#define BIT_GET_LTECOEX_REG_ADDR_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) & \ + BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) +#define BIT_SET_LTECOEX_REG_ADDR_V1_8821C(x, v) \ + (BIT_CLEAR_LTECOEX_REG_ADDR_V1_8821C(x) | \ + BIT_LTECOEX_REG_ADDR_V1_8821C(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C */ #define BIT_SHIFT_LTECOEX_W_DATA_V1_8821C 0 #define BIT_MASK_LTECOEX_W_DATA_V1_8821C 0xffffffffL -#define BIT_LTECOEX_W_DATA_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8821C) << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) -#define BIT_GET_LTECOEX_W_DATA_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) & BIT_MASK_LTECOEX_W_DATA_V1_8821C) - - +#define BIT_LTECOEX_W_DATA_V1_8821C(x) \ + (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8821C) \ + << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) +#define BITS_LTECOEX_W_DATA_V1_8821C \ + (BIT_MASK_LTECOEX_W_DATA_V1_8821C << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) +#define BIT_CLEAR_LTECOEX_W_DATA_V1_8821C(x) \ + ((x) & (~BITS_LTECOEX_W_DATA_V1_8821C)) +#define BIT_GET_LTECOEX_W_DATA_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) & \ + BIT_MASK_LTECOEX_W_DATA_V1_8821C) +#define BIT_SET_LTECOEX_W_DATA_V1_8821C(x, v) \ + (BIT_CLEAR_LTECOEX_W_DATA_V1_8821C(x) | BIT_LTECOEX_W_DATA_V1_8821C(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C */ #define BIT_SHIFT_LTECOEX_R_DATA_V1_8821C 0 #define BIT_MASK_LTECOEX_R_DATA_V1_8821C 0xffffffffL -#define BIT_LTECOEX_R_DATA_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8821C) << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) -#define BIT_GET_LTECOEX_R_DATA_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) & BIT_MASK_LTECOEX_R_DATA_V1_8821C) - - +#define BIT_LTECOEX_R_DATA_V1_8821C(x) \ + (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8821C) \ + << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) +#define BITS_LTECOEX_R_DATA_V1_8821C \ + (BIT_MASK_LTECOEX_R_DATA_V1_8821C << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) +#define BIT_CLEAR_LTECOEX_R_DATA_V1_8821C(x) \ + ((x) & (~BITS_LTECOEX_R_DATA_V1_8821C)) +#define BIT_GET_LTECOEX_R_DATA_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) & \ + BIT_MASK_LTECOEX_R_DATA_V1_8821C) +#define BIT_SET_LTECOEX_R_DATA_V1_8821C(x, v) \ + (BIT_CLEAR_LTECOEX_R_DATA_V1_8821C(x) | BIT_LTECOEX_R_DATA_V1_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -11406,16 +19008,26 @@ #define BIT_SHIFT_SDIO_INT_TIMEOUT_8821C 16 #define BIT_MASK_SDIO_INT_TIMEOUT_8821C 0xffff -#define BIT_SDIO_INT_TIMEOUT_8821C(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8821C) << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) -#define BIT_GET_SDIO_INT_TIMEOUT_8821C(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) & BIT_MASK_SDIO_INT_TIMEOUT_8821C) - +#define BIT_SDIO_INT_TIMEOUT_8821C(x) \ + (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8821C) \ + << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) +#define BITS_SDIO_INT_TIMEOUT_8821C \ + (BIT_MASK_SDIO_INT_TIMEOUT_8821C << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) +#define BIT_CLEAR_SDIO_INT_TIMEOUT_8821C(x) \ + ((x) & (~BITS_SDIO_INT_TIMEOUT_8821C)) +#define BIT_GET_SDIO_INT_TIMEOUT_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) & \ + BIT_MASK_SDIO_INT_TIMEOUT_8821C) +#define BIT_SET_SDIO_INT_TIMEOUT_8821C(x, v) \ + (BIT_CLEAR_SDIO_INT_TIMEOUT_8821C(x) | BIT_SDIO_INT_TIMEOUT_8821C(v)) #define BIT_IO_ERR_STATUS_8821C BIT(15) #define BIT_REPLY_ERRCRC_IN_DATA_8821C BIT(9) #define BIT_EN_CMD53_OVERLAP_8821C BIT(8) #define BIT_REPLY_ERR_IN_R5_8821C BIT(7) #define BIT_R18A_EN_8821C BIT(6) -#define BIT_INIT_CMD_EN_8821C BIT(5) +#define BIT_SDIO_CMD_FORCE_VLD_8821C BIT(5) +#define BIT_INIT_CMD_EN_8821C BIT(4) #define BIT_EN_RXDMA_MASK_INT_8821C BIT(2) #define BIT_EN_MASK_TIMER_8821C BIT(1) #define BIT_CMD_ERR_STOP_INT_EN_8821C BIT(0) @@ -11476,95 +19088,155 @@ #define BIT_SHIFT_RX_REQ_LEN_V1_8821C 0 #define BIT_MASK_RX_REQ_LEN_V1_8821C 0x3ffff -#define BIT_RX_REQ_LEN_V1_8821C(x) (((x) & BIT_MASK_RX_REQ_LEN_V1_8821C) << BIT_SHIFT_RX_REQ_LEN_V1_8821C) -#define BIT_GET_RX_REQ_LEN_V1_8821C(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8821C) & BIT_MASK_RX_REQ_LEN_V1_8821C) - - +#define BIT_RX_REQ_LEN_V1_8821C(x) \ + (((x) & BIT_MASK_RX_REQ_LEN_V1_8821C) << BIT_SHIFT_RX_REQ_LEN_V1_8821C) +#define BITS_RX_REQ_LEN_V1_8821C \ + (BIT_MASK_RX_REQ_LEN_V1_8821C << BIT_SHIFT_RX_REQ_LEN_V1_8821C) +#define BIT_CLEAR_RX_REQ_LEN_V1_8821C(x) ((x) & (~BITS_RX_REQ_LEN_V1_8821C)) +#define BIT_GET_RX_REQ_LEN_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8821C) & BIT_MASK_RX_REQ_LEN_V1_8821C) +#define BIT_SET_RX_REQ_LEN_V1_8821C(x, v) \ + (BIT_CLEAR_RX_REQ_LEN_V1_8821C(x) | BIT_RX_REQ_LEN_V1_8821C(v)) /* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8821C */ #define BIT_SHIFT_FREE_TXPG_SEQ_8821C 0 #define BIT_MASK_FREE_TXPG_SEQ_8821C 0xff -#define BIT_FREE_TXPG_SEQ_8821C(x) (((x) & BIT_MASK_FREE_TXPG_SEQ_8821C) << BIT_SHIFT_FREE_TXPG_SEQ_8821C) -#define BIT_GET_FREE_TXPG_SEQ_8821C(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8821C) & BIT_MASK_FREE_TXPG_SEQ_8821C) - - +#define BIT_FREE_TXPG_SEQ_8821C(x) \ + (((x) & BIT_MASK_FREE_TXPG_SEQ_8821C) << BIT_SHIFT_FREE_TXPG_SEQ_8821C) +#define BITS_FREE_TXPG_SEQ_8821C \ + (BIT_MASK_FREE_TXPG_SEQ_8821C << BIT_SHIFT_FREE_TXPG_SEQ_8821C) +#define BIT_CLEAR_FREE_TXPG_SEQ_8821C(x) ((x) & (~BITS_FREE_TXPG_SEQ_8821C)) +#define BIT_GET_FREE_TXPG_SEQ_8821C(x) \ + (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8821C) & BIT_MASK_FREE_TXPG_SEQ_8821C) +#define BIT_SET_FREE_TXPG_SEQ_8821C(x, v) \ + (BIT_CLEAR_FREE_TXPG_SEQ_8821C(x) | BIT_FREE_TXPG_SEQ_8821C(v)) /* 2 REG_SDIO_FREE_TXPG_8821C */ #define BIT_SHIFT_MID_FREEPG_V1_8821C 16 #define BIT_MASK_MID_FREEPG_V1_8821C 0xfff -#define BIT_MID_FREEPG_V1_8821C(x) (((x) & BIT_MASK_MID_FREEPG_V1_8821C) << BIT_SHIFT_MID_FREEPG_V1_8821C) -#define BIT_GET_MID_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1_8821C) & BIT_MASK_MID_FREEPG_V1_8821C) - - +#define BIT_MID_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_MID_FREEPG_V1_8821C) << BIT_SHIFT_MID_FREEPG_V1_8821C) +#define BITS_MID_FREEPG_V1_8821C \ + (BIT_MASK_MID_FREEPG_V1_8821C << BIT_SHIFT_MID_FREEPG_V1_8821C) +#define BIT_CLEAR_MID_FREEPG_V1_8821C(x) ((x) & (~BITS_MID_FREEPG_V1_8821C)) +#define BIT_GET_MID_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MID_FREEPG_V1_8821C) & BIT_MASK_MID_FREEPG_V1_8821C) +#define BIT_SET_MID_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_MID_FREEPG_V1_8821C(x) | BIT_MID_FREEPG_V1_8821C(v)) #define BIT_SHIFT_HIQ_FREEPG_V1_8821C 0 #define BIT_MASK_HIQ_FREEPG_V1_8821C 0xfff -#define BIT_HIQ_FREEPG_V1_8821C(x) (((x) & BIT_MASK_HIQ_FREEPG_V1_8821C) << BIT_SHIFT_HIQ_FREEPG_V1_8821C) -#define BIT_GET_HIQ_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8821C) & BIT_MASK_HIQ_FREEPG_V1_8821C) - - +#define BIT_HIQ_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_HIQ_FREEPG_V1_8821C) << BIT_SHIFT_HIQ_FREEPG_V1_8821C) +#define BITS_HIQ_FREEPG_V1_8821C \ + (BIT_MASK_HIQ_FREEPG_V1_8821C << BIT_SHIFT_HIQ_FREEPG_V1_8821C) +#define BIT_CLEAR_HIQ_FREEPG_V1_8821C(x) ((x) & (~BITS_HIQ_FREEPG_V1_8821C)) +#define BIT_GET_HIQ_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8821C) & BIT_MASK_HIQ_FREEPG_V1_8821C) +#define BIT_SET_HIQ_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_HIQ_FREEPG_V1_8821C(x) | BIT_HIQ_FREEPG_V1_8821C(v)) /* 2 REG_SDIO_FREE_TXPG2_8821C */ #define BIT_SHIFT_PUB_FREEPG_V1_8821C 16 #define BIT_MASK_PUB_FREEPG_V1_8821C 0xfff -#define BIT_PUB_FREEPG_V1_8821C(x) (((x) & BIT_MASK_PUB_FREEPG_V1_8821C) << BIT_SHIFT_PUB_FREEPG_V1_8821C) -#define BIT_GET_PUB_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8821C) & BIT_MASK_PUB_FREEPG_V1_8821C) - - +#define BIT_PUB_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_PUB_FREEPG_V1_8821C) << BIT_SHIFT_PUB_FREEPG_V1_8821C) +#define BITS_PUB_FREEPG_V1_8821C \ + (BIT_MASK_PUB_FREEPG_V1_8821C << BIT_SHIFT_PUB_FREEPG_V1_8821C) +#define BIT_CLEAR_PUB_FREEPG_V1_8821C(x) ((x) & (~BITS_PUB_FREEPG_V1_8821C)) +#define BIT_GET_PUB_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8821C) & BIT_MASK_PUB_FREEPG_V1_8821C) +#define BIT_SET_PUB_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_PUB_FREEPG_V1_8821C(x) | BIT_PUB_FREEPG_V1_8821C(v)) #define BIT_SHIFT_LOW_FREEPG_V1_8821C 0 #define BIT_MASK_LOW_FREEPG_V1_8821C 0xfff -#define BIT_LOW_FREEPG_V1_8821C(x) (((x) & BIT_MASK_LOW_FREEPG_V1_8821C) << BIT_SHIFT_LOW_FREEPG_V1_8821C) -#define BIT_GET_LOW_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8821C) & BIT_MASK_LOW_FREEPG_V1_8821C) - - +#define BIT_LOW_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_LOW_FREEPG_V1_8821C) << BIT_SHIFT_LOW_FREEPG_V1_8821C) +#define BITS_LOW_FREEPG_V1_8821C \ + (BIT_MASK_LOW_FREEPG_V1_8821C << BIT_SHIFT_LOW_FREEPG_V1_8821C) +#define BIT_CLEAR_LOW_FREEPG_V1_8821C(x) ((x) & (~BITS_LOW_FREEPG_V1_8821C)) +#define BIT_GET_LOW_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8821C) & BIT_MASK_LOW_FREEPG_V1_8821C) +#define BIT_SET_LOW_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_LOW_FREEPG_V1_8821C(x) | BIT_LOW_FREEPG_V1_8821C(v)) /* 2 REG_SDIO_OQT_FREE_TXPG_V1_8821C */ #define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C 24 #define BIT_MASK_NOAC_OQT_FREEPG_V1_8821C 0xff -#define BIT_NOAC_OQT_FREEPG_V1_8821C(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) -#define BIT_GET_NOAC_OQT_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) - - +#define BIT_NOAC_OQT_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) +#define BITS_NOAC_OQT_FREEPG_V1_8821C \ + (BIT_MASK_NOAC_OQT_FREEPG_V1_8821C \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) +#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8821C(x) \ + ((x) & (~BITS_NOAC_OQT_FREEPG_V1_8821C)) +#define BIT_GET_NOAC_OQT_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) & \ + BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) +#define BIT_SET_NOAC_OQT_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_NOAC_OQT_FREEPG_V1_8821C(x) | \ + BIT_NOAC_OQT_FREEPG_V1_8821C(v)) #define BIT_SHIFT_AC_OQT_FREEPG_V1_8821C 16 #define BIT_MASK_AC_OQT_FREEPG_V1_8821C 0xff -#define BIT_AC_OQT_FREEPG_V1_8821C(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8821C) << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) -#define BIT_GET_AC_OQT_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) & BIT_MASK_AC_OQT_FREEPG_V1_8821C) - - +#define BIT_AC_OQT_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8821C) \ + << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) +#define BITS_AC_OQT_FREEPG_V1_8821C \ + (BIT_MASK_AC_OQT_FREEPG_V1_8821C << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) +#define BIT_CLEAR_AC_OQT_FREEPG_V1_8821C(x) \ + ((x) & (~BITS_AC_OQT_FREEPG_V1_8821C)) +#define BIT_GET_AC_OQT_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) & \ + BIT_MASK_AC_OQT_FREEPG_V1_8821C) +#define BIT_SET_AC_OQT_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_AC_OQT_FREEPG_V1_8821C(x) | BIT_AC_OQT_FREEPG_V1_8821C(v)) #define BIT_SHIFT_EXQ_FREEPG_V1_8821C 0 #define BIT_MASK_EXQ_FREEPG_V1_8821C 0xfff -#define BIT_EXQ_FREEPG_V1_8821C(x) (((x) & BIT_MASK_EXQ_FREEPG_V1_8821C) << BIT_SHIFT_EXQ_FREEPG_V1_8821C) -#define BIT_GET_EXQ_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8821C) & BIT_MASK_EXQ_FREEPG_V1_8821C) - - +#define BIT_EXQ_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_EXQ_FREEPG_V1_8821C) << BIT_SHIFT_EXQ_FREEPG_V1_8821C) +#define BITS_EXQ_FREEPG_V1_8821C \ + (BIT_MASK_EXQ_FREEPG_V1_8821C << BIT_SHIFT_EXQ_FREEPG_V1_8821C) +#define BIT_CLEAR_EXQ_FREEPG_V1_8821C(x) ((x) & (~BITS_EXQ_FREEPG_V1_8821C)) +#define BIT_GET_EXQ_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8821C) & BIT_MASK_EXQ_FREEPG_V1_8821C) +#define BIT_SET_EXQ_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_EXQ_FREEPG_V1_8821C(x) | BIT_EXQ_FREEPG_V1_8821C(v)) /* 2 REG_SDIO_HTSFR_INFO_8821C */ #define BIT_SHIFT_HTSFR1_8821C 16 #define BIT_MASK_HTSFR1_8821C 0xffff -#define BIT_HTSFR1_8821C(x) (((x) & BIT_MASK_HTSFR1_8821C) << BIT_SHIFT_HTSFR1_8821C) -#define BIT_GET_HTSFR1_8821C(x) (((x) >> BIT_SHIFT_HTSFR1_8821C) & BIT_MASK_HTSFR1_8821C) - - +#define BIT_HTSFR1_8821C(x) \ + (((x) & BIT_MASK_HTSFR1_8821C) << BIT_SHIFT_HTSFR1_8821C) +#define BITS_HTSFR1_8821C (BIT_MASK_HTSFR1_8821C << BIT_SHIFT_HTSFR1_8821C) +#define BIT_CLEAR_HTSFR1_8821C(x) ((x) & (~BITS_HTSFR1_8821C)) +#define BIT_GET_HTSFR1_8821C(x) \ + (((x) >> BIT_SHIFT_HTSFR1_8821C) & BIT_MASK_HTSFR1_8821C) +#define BIT_SET_HTSFR1_8821C(x, v) \ + (BIT_CLEAR_HTSFR1_8821C(x) | BIT_HTSFR1_8821C(v)) #define BIT_SHIFT_HTSFR0_8821C 0 #define BIT_MASK_HTSFR0_8821C 0xffff -#define BIT_HTSFR0_8821C(x) (((x) & BIT_MASK_HTSFR0_8821C) << BIT_SHIFT_HTSFR0_8821C) -#define BIT_GET_HTSFR0_8821C(x) (((x) >> BIT_SHIFT_HTSFR0_8821C) & BIT_MASK_HTSFR0_8821C) - - +#define BIT_HTSFR0_8821C(x) \ + (((x) & BIT_MASK_HTSFR0_8821C) << BIT_SHIFT_HTSFR0_8821C) +#define BITS_HTSFR0_8821C (BIT_MASK_HTSFR0_8821C << BIT_SHIFT_HTSFR0_8821C) +#define BIT_CLEAR_HTSFR0_8821C(x) ((x) & (~BITS_HTSFR0_8821C)) +#define BIT_GET_HTSFR0_8821C(x) \ + (((x) >> BIT_SHIFT_HTSFR0_8821C) & BIT_MASK_HTSFR0_8821C) +#define BIT_SET_HTSFR0_8821C(x, v) \ + (BIT_CLEAR_HTSFR0_8821C(x) | BIT_HTSFR0_8821C(v)) /* 2 REG_SDIO_HCPWM1_V2_8821C */ -#define BIT_TOGGLING_8821C BIT(7) -#define BIT_ACK_8821C BIT(6) -#define BIT_SYS_CLK_8821C BIT(0) +#define BIT_TOGGLE_8821C BIT(7) +#define BIT_CUR_PS_8821C BIT(0) /* 2 REG_SDIO_HCPWM2_V2_8821C */ @@ -11575,49 +19247,83 @@ #define BIT_SHIFT_INDIRECT_REG_SIZE_8821C 16 #define BIT_MASK_INDIRECT_REG_SIZE_8821C 0x3 -#define BIT_INDIRECT_REG_SIZE_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE_8821C) << BIT_SHIFT_INDIRECT_REG_SIZE_8821C) -#define BIT_GET_INDIRECT_REG_SIZE_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8821C) & BIT_MASK_INDIRECT_REG_SIZE_8821C) - - +#define BIT_INDIRECT_REG_SIZE_8821C(x) \ + (((x) & BIT_MASK_INDIRECT_REG_SIZE_8821C) \ + << BIT_SHIFT_INDIRECT_REG_SIZE_8821C) +#define BITS_INDIRECT_REG_SIZE_8821C \ + (BIT_MASK_INDIRECT_REG_SIZE_8821C << BIT_SHIFT_INDIRECT_REG_SIZE_8821C) +#define BIT_CLEAR_INDIRECT_REG_SIZE_8821C(x) \ + ((x) & (~BITS_INDIRECT_REG_SIZE_8821C)) +#define BIT_GET_INDIRECT_REG_SIZE_8821C(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8821C) & \ + BIT_MASK_INDIRECT_REG_SIZE_8821C) +#define BIT_SET_INDIRECT_REG_SIZE_8821C(x, v) \ + (BIT_CLEAR_INDIRECT_REG_SIZE_8821C(x) | BIT_INDIRECT_REG_SIZE_8821C(v)) #define BIT_SHIFT_INDIRECT_REG_ADDR_8821C 0 #define BIT_MASK_INDIRECT_REG_ADDR_8821C 0xffff -#define BIT_INDIRECT_REG_ADDR_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR_8821C) << BIT_SHIFT_INDIRECT_REG_ADDR_8821C) -#define BIT_GET_INDIRECT_REG_ADDR_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8821C) & BIT_MASK_INDIRECT_REG_ADDR_8821C) - - +#define BIT_INDIRECT_REG_ADDR_8821C(x) \ + (((x) & BIT_MASK_INDIRECT_REG_ADDR_8821C) \ + << BIT_SHIFT_INDIRECT_REG_ADDR_8821C) +#define BITS_INDIRECT_REG_ADDR_8821C \ + (BIT_MASK_INDIRECT_REG_ADDR_8821C << BIT_SHIFT_INDIRECT_REG_ADDR_8821C) +#define BIT_CLEAR_INDIRECT_REG_ADDR_8821C(x) \ + ((x) & (~BITS_INDIRECT_REG_ADDR_8821C)) +#define BIT_GET_INDIRECT_REG_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8821C) & \ + BIT_MASK_INDIRECT_REG_ADDR_8821C) +#define BIT_SET_INDIRECT_REG_ADDR_8821C(x, v) \ + (BIT_CLEAR_INDIRECT_REG_ADDR_8821C(x) | BIT_INDIRECT_REG_ADDR_8821C(v)) /* 2 REG_SDIO_INDIRECT_REG_DATA_8821C */ #define BIT_SHIFT_INDIRECT_REG_DATA_8821C 0 #define BIT_MASK_INDIRECT_REG_DATA_8821C 0xffffffffL -#define BIT_INDIRECT_REG_DATA_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_DATA_8821C) << BIT_SHIFT_INDIRECT_REG_DATA_8821C) -#define BIT_GET_INDIRECT_REG_DATA_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8821C) & BIT_MASK_INDIRECT_REG_DATA_8821C) - - +#define BIT_INDIRECT_REG_DATA_8821C(x) \ + (((x) & BIT_MASK_INDIRECT_REG_DATA_8821C) \ + << BIT_SHIFT_INDIRECT_REG_DATA_8821C) +#define BITS_INDIRECT_REG_DATA_8821C \ + (BIT_MASK_INDIRECT_REG_DATA_8821C << BIT_SHIFT_INDIRECT_REG_DATA_8821C) +#define BIT_CLEAR_INDIRECT_REG_DATA_8821C(x) \ + ((x) & (~BITS_INDIRECT_REG_DATA_8821C)) +#define BIT_GET_INDIRECT_REG_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8821C) & \ + BIT_MASK_INDIRECT_REG_DATA_8821C) +#define BIT_SET_INDIRECT_REG_DATA_8821C(x, v) \ + (BIT_CLEAR_INDIRECT_REG_DATA_8821C(x) | BIT_INDIRECT_REG_DATA_8821C(v)) /* 2 REG_SDIO_H2C_8821C */ #define BIT_SHIFT_SDIO_H2C_MSG_8821C 0 #define BIT_MASK_SDIO_H2C_MSG_8821C 0xffffffffL -#define BIT_SDIO_H2C_MSG_8821C(x) (((x) & BIT_MASK_SDIO_H2C_MSG_8821C) << BIT_SHIFT_SDIO_H2C_MSG_8821C) -#define BIT_GET_SDIO_H2C_MSG_8821C(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8821C) & BIT_MASK_SDIO_H2C_MSG_8821C) - - +#define BIT_SDIO_H2C_MSG_8821C(x) \ + (((x) & BIT_MASK_SDIO_H2C_MSG_8821C) << BIT_SHIFT_SDIO_H2C_MSG_8821C) +#define BITS_SDIO_H2C_MSG_8821C \ + (BIT_MASK_SDIO_H2C_MSG_8821C << BIT_SHIFT_SDIO_H2C_MSG_8821C) +#define BIT_CLEAR_SDIO_H2C_MSG_8821C(x) ((x) & (~BITS_SDIO_H2C_MSG_8821C)) +#define BIT_GET_SDIO_H2C_MSG_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8821C) & BIT_MASK_SDIO_H2C_MSG_8821C) +#define BIT_SET_SDIO_H2C_MSG_8821C(x, v) \ + (BIT_CLEAR_SDIO_H2C_MSG_8821C(x) | BIT_SDIO_H2C_MSG_8821C(v)) /* 2 REG_SDIO_C2H_8821C */ #define BIT_SHIFT_SDIO_C2H_MSG_8821C 0 #define BIT_MASK_SDIO_C2H_MSG_8821C 0xffffffffL -#define BIT_SDIO_C2H_MSG_8821C(x) (((x) & BIT_MASK_SDIO_C2H_MSG_8821C) << BIT_SHIFT_SDIO_C2H_MSG_8821C) -#define BIT_GET_SDIO_C2H_MSG_8821C(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8821C) & BIT_MASK_SDIO_C2H_MSG_8821C) - - +#define BIT_SDIO_C2H_MSG_8821C(x) \ + (((x) & BIT_MASK_SDIO_C2H_MSG_8821C) << BIT_SHIFT_SDIO_C2H_MSG_8821C) +#define BITS_SDIO_C2H_MSG_8821C \ + (BIT_MASK_SDIO_C2H_MSG_8821C << BIT_SHIFT_SDIO_C2H_MSG_8821C) +#define BIT_CLEAR_SDIO_C2H_MSG_8821C(x) ((x) & (~BITS_SDIO_C2H_MSG_8821C)) +#define BIT_GET_SDIO_C2H_MSG_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8821C) & BIT_MASK_SDIO_C2H_MSG_8821C) +#define BIT_SET_SDIO_C2H_MSG_8821C(x, v) \ + (BIT_CLEAR_SDIO_C2H_MSG_8821C(x) | BIT_SDIO_C2H_MSG_8821C(v)) /* 2 REG_SDIO_HRPWM1_8821C */ -#define BIT_TOGGLING_8821C BIT(7) +#define BIT_TOGGLE_8821C BIT(7) #define BIT_ACK_8821C BIT(6) -#define BIT_32K_PERMISSION_8821C BIT(0) +#define BIT_REQ_PS_8821C BIT(0) /* 2 REG_SDIO_HRPWM2_8821C */ @@ -11640,27 +19346,39 @@ #define BIT_SHIFT_CMDIN_2RESP_TIMER_8821C 0 #define BIT_MASK_CMDIN_2RESP_TIMER_8821C 0xffff -#define BIT_CMDIN_2RESP_TIMER_8821C(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8821C) << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) -#define BIT_GET_CMDIN_2RESP_TIMER_8821C(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) & BIT_MASK_CMDIN_2RESP_TIMER_8821C) - - +#define BIT_CMDIN_2RESP_TIMER_8821C(x) \ + (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8821C) \ + << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) +#define BITS_CMDIN_2RESP_TIMER_8821C \ + (BIT_MASK_CMDIN_2RESP_TIMER_8821C << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) +#define BIT_CLEAR_CMDIN_2RESP_TIMER_8821C(x) \ + ((x) & (~BITS_CMDIN_2RESP_TIMER_8821C)) +#define BIT_GET_CMDIN_2RESP_TIMER_8821C(x) \ + (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) & \ + BIT_MASK_CMDIN_2RESP_TIMER_8821C) +#define BIT_SET_CMDIN_2RESP_TIMER_8821C(x, v) \ + (BIT_CLEAR_CMDIN_2RESP_TIMER_8821C(x) | BIT_CMDIN_2RESP_TIMER_8821C(v)) /* 2 REG_SDIO_CMD_CRC_8821C */ #define BIT_SHIFT_SDIO_CMD_CRC_V1_8821C 0 #define BIT_MASK_SDIO_CMD_CRC_V1_8821C 0xff -#define BIT_SDIO_CMD_CRC_V1_8821C(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8821C) << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) -#define BIT_GET_SDIO_CMD_CRC_V1_8821C(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) & BIT_MASK_SDIO_CMD_CRC_V1_8821C) - - +#define BIT_SDIO_CMD_CRC_V1_8821C(x) \ + (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8821C) \ + << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) +#define BITS_SDIO_CMD_CRC_V1_8821C \ + (BIT_MASK_SDIO_CMD_CRC_V1_8821C << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) +#define BIT_CLEAR_SDIO_CMD_CRC_V1_8821C(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8821C)) +#define BIT_GET_SDIO_CMD_CRC_V1_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) & \ + BIT_MASK_SDIO_CMD_CRC_V1_8821C) +#define BIT_SET_SDIO_CMD_CRC_V1_8821C(x, v) \ + (BIT_CLEAR_SDIO_CMD_CRC_V1_8821C(x) | BIT_SDIO_CMD_CRC_V1_8821C(v)) /* 2 REG_SDIO_HSISR_8821C */ #define BIT_DRV_WLAN_INT_CLR_8821C BIT(1) #define BIT_DRV_WLAN_INT_8821C BIT(0) -/* 2 REG_SDIO_HSIMR_8821C */ -#define BIT_HISR_MASK_8821C BIT(0) - /* 2 REG_SDIO_ERR_RPT_8821C */ #define BIT_HR_FF_OVF_8821C BIT(6) #define BIT_HR_FF_UDN_8821C BIT(5) @@ -11674,28 +19392,53 @@ #define BIT_SHIFT_CMD_CRC_ERR_CNT_8821C 0 #define BIT_MASK_CMD_CRC_ERR_CNT_8821C 0xff -#define BIT_CMD_CRC_ERR_CNT_8821C(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8821C) << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) -#define BIT_GET_CMD_CRC_ERR_CNT_8821C(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) & BIT_MASK_CMD_CRC_ERR_CNT_8821C) - - +#define BIT_CMD_CRC_ERR_CNT_8821C(x) \ + (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8821C) \ + << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) +#define BITS_CMD_CRC_ERR_CNT_8821C \ + (BIT_MASK_CMD_CRC_ERR_CNT_8821C << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) +#define BIT_CLEAR_CMD_CRC_ERR_CNT_8821C(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8821C)) +#define BIT_GET_CMD_CRC_ERR_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) & \ + BIT_MASK_CMD_CRC_ERR_CNT_8821C) +#define BIT_SET_CMD_CRC_ERR_CNT_8821C(x, v) \ + (BIT_CLEAR_CMD_CRC_ERR_CNT_8821C(x) | BIT_CMD_CRC_ERR_CNT_8821C(v)) /* 2 REG_SDIO_DATA_ERRCNT_8821C */ #define BIT_SHIFT_DATA_CRC_ERR_CNT_8821C 0 #define BIT_MASK_DATA_CRC_ERR_CNT_8821C 0xff -#define BIT_DATA_CRC_ERR_CNT_8821C(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8821C) << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) -#define BIT_GET_DATA_CRC_ERR_CNT_8821C(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) & BIT_MASK_DATA_CRC_ERR_CNT_8821C) - - +#define BIT_DATA_CRC_ERR_CNT_8821C(x) \ + (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8821C) \ + << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) +#define BITS_DATA_CRC_ERR_CNT_8821C \ + (BIT_MASK_DATA_CRC_ERR_CNT_8821C << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) +#define BIT_CLEAR_DATA_CRC_ERR_CNT_8821C(x) \ + ((x) & (~BITS_DATA_CRC_ERR_CNT_8821C)) +#define BIT_GET_DATA_CRC_ERR_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) & \ + BIT_MASK_DATA_CRC_ERR_CNT_8821C) +#define BIT_SET_DATA_CRC_ERR_CNT_8821C(x, v) \ + (BIT_CLEAR_DATA_CRC_ERR_CNT_8821C(x) | BIT_DATA_CRC_ERR_CNT_8821C(v)) /* 2 REG_SDIO_CMD_ERR_CONTENT_8821C */ #define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C 0 #define BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C 0xffffffffffL -#define BIT_SDIO_CMD_ERR_CONTENT_8821C(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) -#define BIT_GET_SDIO_CMD_ERR_CONTENT_8821C(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) - - +#define BIT_SDIO_CMD_ERR_CONTENT_8821C(x) \ + (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) +#define BITS_SDIO_CMD_ERR_CONTENT_8821C \ + (BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) +#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8821C(x) \ + ((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8821C)) +#define BIT_GET_SDIO_CMD_ERR_CONTENT_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) & \ + BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) +#define BIT_SET_SDIO_CMD_ERR_CONTENT_8821C(x, v) \ + (BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8821C(x) | \ + BIT_SDIO_CMD_ERR_CONTENT_8821C(v)) /* 2 REG_SDIO_CRC_ERR_IDX_8821C */ #define BIT_D3_CRC_ERR_8821C BIT(4) @@ -11707,19 +19450,34 @@ /* 2 REG_SDIO_DATA_CRC_8821C */ #define BIT_SHIFT_SDIO_DATA_CRC_8821C 0 -#define BIT_MASK_SDIO_DATA_CRC_8821C 0xff -#define BIT_SDIO_DATA_CRC_8821C(x) (((x) & BIT_MASK_SDIO_DATA_CRC_8821C) << BIT_SHIFT_SDIO_DATA_CRC_8821C) -#define BIT_GET_SDIO_DATA_CRC_8821C(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8821C) & BIT_MASK_SDIO_DATA_CRC_8821C) - - +#define BIT_MASK_SDIO_DATA_CRC_8821C 0xffff +#define BIT_SDIO_DATA_CRC_8821C(x) \ + (((x) & BIT_MASK_SDIO_DATA_CRC_8821C) << BIT_SHIFT_SDIO_DATA_CRC_8821C) +#define BITS_SDIO_DATA_CRC_8821C \ + (BIT_MASK_SDIO_DATA_CRC_8821C << BIT_SHIFT_SDIO_DATA_CRC_8821C) +#define BIT_CLEAR_SDIO_DATA_CRC_8821C(x) ((x) & (~BITS_SDIO_DATA_CRC_8821C)) +#define BIT_GET_SDIO_DATA_CRC_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8821C) & BIT_MASK_SDIO_DATA_CRC_8821C) +#define BIT_SET_SDIO_DATA_CRC_8821C(x, v) \ + (BIT_CLEAR_SDIO_DATA_CRC_8821C(x) | BIT_SDIO_DATA_CRC_8821C(v)) /* 2 REG_SDIO_DATA_REPLY_TIME_8821C */ #define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C 0 #define BIT_MASK_SDIO_DATA_REPLY_TIME_8821C 0x7 -#define BIT_SDIO_DATA_REPLY_TIME_8821C(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) -#define BIT_GET_SDIO_DATA_REPLY_TIME_8821C(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) - - +#define BIT_SDIO_DATA_REPLY_TIME_8821C(x) \ + (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) +#define BITS_SDIO_DATA_REPLY_TIME_8821C \ + (BIT_MASK_SDIO_DATA_REPLY_TIME_8821C \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) +#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8821C(x) \ + ((x) & (~BITS_SDIO_DATA_REPLY_TIME_8821C)) +#define BIT_GET_SDIO_DATA_REPLY_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) & \ + BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) +#define BIT_SET_SDIO_DATA_REPLY_TIME_8821C(x, v) \ + (BIT_CLEAR_SDIO_DATA_REPLY_TIME_8821C(x) | \ + BIT_SDIO_DATA_REPLY_TIME_8821C(v)) #endif diff --git a/hal/halmac/halmac_bit_8822b.h b/hal/halmac/halmac_bit_8822b.h index db8680b..0b29665 100644 --- a/hal/halmac/halmac_bit_8822b.h +++ b/hal/halmac/halmac_bit_8822b.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -106,16 +106,25 @@ #define BIT_SHIFT_VPDIDX_8822B 8 #define BIT_MASK_VPDIDX_8822B 0xff -#define BIT_VPDIDX_8822B(x) (((x) & BIT_MASK_VPDIDX_8822B) << BIT_SHIFT_VPDIDX_8822B) -#define BIT_GET_VPDIDX_8822B(x) (((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B) - - +#define BIT_VPDIDX_8822B(x) \ + (((x) & BIT_MASK_VPDIDX_8822B) << BIT_SHIFT_VPDIDX_8822B) +#define BITS_VPDIDX_8822B (BIT_MASK_VPDIDX_8822B << BIT_SHIFT_VPDIDX_8822B) +#define BIT_CLEAR_VPDIDX_8822B(x) ((x) & (~BITS_VPDIDX_8822B)) +#define BIT_GET_VPDIDX_8822B(x) \ + (((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B) +#define BIT_SET_VPDIDX_8822B(x, v) \ + (BIT_CLEAR_VPDIDX_8822B(x) | BIT_VPDIDX_8822B(v)) #define BIT_SHIFT_EEM1_0_8822B 6 #define BIT_MASK_EEM1_0_8822B 0x3 -#define BIT_EEM1_0_8822B(x) (((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B) -#define BIT_GET_EEM1_0_8822B(x) (((x) >> BIT_SHIFT_EEM1_0_8822B) & BIT_MASK_EEM1_0_8822B) - +#define BIT_EEM1_0_8822B(x) \ + (((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B) +#define BITS_EEM1_0_8822B (BIT_MASK_EEM1_0_8822B << BIT_SHIFT_EEM1_0_8822B) +#define BIT_CLEAR_EEM1_0_8822B(x) ((x) & (~BITS_EEM1_0_8822B)) +#define BIT_GET_EEM1_0_8822B(x) \ + (((x) >> BIT_SHIFT_EEM1_0_8822B) & BIT_MASK_EEM1_0_8822B) +#define BIT_SET_EEM1_0_8822B(x, v) \ + (BIT_CLEAR_EEM1_0_8822B(x) | BIT_EEM1_0_8822B(v)) #define BIT_AUTOLOAD_SUS_8822B BIT(5) #define BIT_EERPOMSEL_8822B BIT(4) @@ -128,10 +137,15 @@ #define BIT_SHIFT_VPD_DATA_8822B 0 #define BIT_MASK_VPD_DATA_8822B 0xffffffffL -#define BIT_VPD_DATA_8822B(x) (((x) & BIT_MASK_VPD_DATA_8822B) << BIT_SHIFT_VPD_DATA_8822B) -#define BIT_GET_VPD_DATA_8822B(x) (((x) >> BIT_SHIFT_VPD_DATA_8822B) & BIT_MASK_VPD_DATA_8822B) - - +#define BIT_VPD_DATA_8822B(x) \ + (((x) & BIT_MASK_VPD_DATA_8822B) << BIT_SHIFT_VPD_DATA_8822B) +#define BITS_VPD_DATA_8822B \ + (BIT_MASK_VPD_DATA_8822B << BIT_SHIFT_VPD_DATA_8822B) +#define BIT_CLEAR_VPD_DATA_8822B(x) ((x) & (~BITS_VPD_DATA_8822B)) +#define BIT_GET_VPD_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_VPD_DATA_8822B) & BIT_MASK_VPD_DATA_8822B) +#define BIT_SET_VPD_DATA_8822B(x, v) \ + (BIT_CLEAR_VPD_DATA_8822B(x) | BIT_VPD_DATA_8822B(v)) /* 2 REG_SYS_SWR_CTRL1_8822B */ #define BIT_C2_L_BIT0_8822B BIT(31) @@ -139,23 +153,37 @@ #define BIT_SHIFT_C1_L_8822B 29 #define BIT_MASK_C1_L_8822B 0x3 #define BIT_C1_L_8822B(x) (((x) & BIT_MASK_C1_L_8822B) << BIT_SHIFT_C1_L_8822B) -#define BIT_GET_C1_L_8822B(x) (((x) >> BIT_SHIFT_C1_L_8822B) & BIT_MASK_C1_L_8822B) - - +#define BITS_C1_L_8822B (BIT_MASK_C1_L_8822B << BIT_SHIFT_C1_L_8822B) +#define BIT_CLEAR_C1_L_8822B(x) ((x) & (~BITS_C1_L_8822B)) +#define BIT_GET_C1_L_8822B(x) \ + (((x) >> BIT_SHIFT_C1_L_8822B) & BIT_MASK_C1_L_8822B) +#define BIT_SET_C1_L_8822B(x, v) (BIT_CLEAR_C1_L_8822B(x) | BIT_C1_L_8822B(v)) #define BIT_SHIFT_REG_FREQ_L_8822B 25 #define BIT_MASK_REG_FREQ_L_8822B 0x7 -#define BIT_REG_FREQ_L_8822B(x) (((x) & BIT_MASK_REG_FREQ_L_8822B) << BIT_SHIFT_REG_FREQ_L_8822B) -#define BIT_GET_REG_FREQ_L_8822B(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8822B) & BIT_MASK_REG_FREQ_L_8822B) - +#define BIT_REG_FREQ_L_8822B(x) \ + (((x) & BIT_MASK_REG_FREQ_L_8822B) << BIT_SHIFT_REG_FREQ_L_8822B) +#define BITS_REG_FREQ_L_8822B \ + (BIT_MASK_REG_FREQ_L_8822B << BIT_SHIFT_REG_FREQ_L_8822B) +#define BIT_CLEAR_REG_FREQ_L_8822B(x) ((x) & (~BITS_REG_FREQ_L_8822B)) +#define BIT_GET_REG_FREQ_L_8822B(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L_8822B) & BIT_MASK_REG_FREQ_L_8822B) +#define BIT_SET_REG_FREQ_L_8822B(x, v) \ + (BIT_CLEAR_REG_FREQ_L_8822B(x) | BIT_REG_FREQ_L_8822B(v)) #define BIT_REG_EN_DUTY_8822B BIT(24) #define BIT_SHIFT_REG_MODE_8822B 22 #define BIT_MASK_REG_MODE_8822B 0x3 -#define BIT_REG_MODE_8822B(x) (((x) & BIT_MASK_REG_MODE_8822B) << BIT_SHIFT_REG_MODE_8822B) -#define BIT_GET_REG_MODE_8822B(x) (((x) >> BIT_SHIFT_REG_MODE_8822B) & BIT_MASK_REG_MODE_8822B) - +#define BIT_REG_MODE_8822B(x) \ + (((x) & BIT_MASK_REG_MODE_8822B) << BIT_SHIFT_REG_MODE_8822B) +#define BITS_REG_MODE_8822B \ + (BIT_MASK_REG_MODE_8822B << BIT_SHIFT_REG_MODE_8822B) +#define BIT_CLEAR_REG_MODE_8822B(x) ((x) & (~BITS_REG_MODE_8822B)) +#define BIT_GET_REG_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_REG_MODE_8822B) & BIT_MASK_REG_MODE_8822B) +#define BIT_SET_REG_MODE_8822B(x, v) \ + (BIT_CLEAR_REG_MODE_8822B(x) | BIT_REG_MODE_8822B(v)) #define BIT_REG_EN_SP_8822B BIT(21) #define BIT_REG_AUTO_L_8822B BIT(20) @@ -164,16 +192,23 @@ #define BIT_SHIFT_OCP_L1_8822B 15 #define BIT_MASK_OCP_L1_8822B 0x7 -#define BIT_OCP_L1_8822B(x) (((x) & BIT_MASK_OCP_L1_8822B) << BIT_SHIFT_OCP_L1_8822B) -#define BIT_GET_OCP_L1_8822B(x) (((x) >> BIT_SHIFT_OCP_L1_8822B) & BIT_MASK_OCP_L1_8822B) - - +#define BIT_OCP_L1_8822B(x) \ + (((x) & BIT_MASK_OCP_L1_8822B) << BIT_SHIFT_OCP_L1_8822B) +#define BITS_OCP_L1_8822B (BIT_MASK_OCP_L1_8822B << BIT_SHIFT_OCP_L1_8822B) +#define BIT_CLEAR_OCP_L1_8822B(x) ((x) & (~BITS_OCP_L1_8822B)) +#define BIT_GET_OCP_L1_8822B(x) \ + (((x) >> BIT_SHIFT_OCP_L1_8822B) & BIT_MASK_OCP_L1_8822B) +#define BIT_SET_OCP_L1_8822B(x, v) \ + (BIT_CLEAR_OCP_L1_8822B(x) | BIT_OCP_L1_8822B(v)) #define BIT_SHIFT_CF_L_8822B 13 #define BIT_MASK_CF_L_8822B 0x3 #define BIT_CF_L_8822B(x) (((x) & BIT_MASK_CF_L_8822B) << BIT_SHIFT_CF_L_8822B) -#define BIT_GET_CF_L_8822B(x) (((x) >> BIT_SHIFT_CF_L_8822B) & BIT_MASK_CF_L_8822B) - +#define BITS_CF_L_8822B (BIT_MASK_CF_L_8822B << BIT_SHIFT_CF_L_8822B) +#define BIT_CLEAR_CF_L_8822B(x) ((x) & (~BITS_CF_L_8822B)) +#define BIT_GET_CF_L_8822B(x) \ + (((x) >> BIT_SHIFT_CF_L_8822B) & BIT_MASK_CF_L_8822B) +#define BIT_SET_CF_L_8822B(x, v) (BIT_CLEAR_CF_L_8822B(x) | BIT_CF_L_8822B(v)) #define BIT_SW18_FPWM_8822B BIT(11) #define BIT_SW18_SWEN_8822B BIT(9) @@ -187,37 +222,62 @@ #define BIT_SHIFT_REG_DELAY_8822B 28 #define BIT_MASK_REG_DELAY_8822B 0x3 -#define BIT_REG_DELAY_8822B(x) (((x) & BIT_MASK_REG_DELAY_8822B) << BIT_SHIFT_REG_DELAY_8822B) -#define BIT_GET_REG_DELAY_8822B(x) (((x) >> BIT_SHIFT_REG_DELAY_8822B) & BIT_MASK_REG_DELAY_8822B) - - +#define BIT_REG_DELAY_8822B(x) \ + (((x) & BIT_MASK_REG_DELAY_8822B) << BIT_SHIFT_REG_DELAY_8822B) +#define BITS_REG_DELAY_8822B \ + (BIT_MASK_REG_DELAY_8822B << BIT_SHIFT_REG_DELAY_8822B) +#define BIT_CLEAR_REG_DELAY_8822B(x) ((x) & (~BITS_REG_DELAY_8822B)) +#define BIT_GET_REG_DELAY_8822B(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_8822B) & BIT_MASK_REG_DELAY_8822B) +#define BIT_SET_REG_DELAY_8822B(x, v) \ + (BIT_CLEAR_REG_DELAY_8822B(x) | BIT_REG_DELAY_8822B(v)) #define BIT_SHIFT_V15ADJ_L1_V1_8822B 24 #define BIT_MASK_V15ADJ_L1_V1_8822B 0x7 -#define BIT_V15ADJ_L1_V1_8822B(x) (((x) & BIT_MASK_V15ADJ_L1_V1_8822B) << BIT_SHIFT_V15ADJ_L1_V1_8822B) -#define BIT_GET_V15ADJ_L1_V1_8822B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8822B) & BIT_MASK_V15ADJ_L1_V1_8822B) - - +#define BIT_V15ADJ_L1_V1_8822B(x) \ + (((x) & BIT_MASK_V15ADJ_L1_V1_8822B) << BIT_SHIFT_V15ADJ_L1_V1_8822B) +#define BITS_V15ADJ_L1_V1_8822B \ + (BIT_MASK_V15ADJ_L1_V1_8822B << BIT_SHIFT_V15ADJ_L1_V1_8822B) +#define BIT_CLEAR_V15ADJ_L1_V1_8822B(x) ((x) & (~BITS_V15ADJ_L1_V1_8822B)) +#define BIT_GET_V15ADJ_L1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8822B) & BIT_MASK_V15ADJ_L1_V1_8822B) +#define BIT_SET_V15ADJ_L1_V1_8822B(x, v) \ + (BIT_CLEAR_V15ADJ_L1_V1_8822B(x) | BIT_V15ADJ_L1_V1_8822B(v)) #define BIT_SHIFT_VOL_L1_V1_8822B 20 #define BIT_MASK_VOL_L1_V1_8822B 0xf -#define BIT_VOL_L1_V1_8822B(x) (((x) & BIT_MASK_VOL_L1_V1_8822B) << BIT_SHIFT_VOL_L1_V1_8822B) -#define BIT_GET_VOL_L1_V1_8822B(x) (((x) >> BIT_SHIFT_VOL_L1_V1_8822B) & BIT_MASK_VOL_L1_V1_8822B) - - +#define BIT_VOL_L1_V1_8822B(x) \ + (((x) & BIT_MASK_VOL_L1_V1_8822B) << BIT_SHIFT_VOL_L1_V1_8822B) +#define BITS_VOL_L1_V1_8822B \ + (BIT_MASK_VOL_L1_V1_8822B << BIT_SHIFT_VOL_L1_V1_8822B) +#define BIT_CLEAR_VOL_L1_V1_8822B(x) ((x) & (~BITS_VOL_L1_V1_8822B)) +#define BIT_GET_VOL_L1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_VOL_L1_V1_8822B) & BIT_MASK_VOL_L1_V1_8822B) +#define BIT_SET_VOL_L1_V1_8822B(x, v) \ + (BIT_CLEAR_VOL_L1_V1_8822B(x) | BIT_VOL_L1_V1_8822B(v)) #define BIT_SHIFT_IN_L1_V1_8822B 17 #define BIT_MASK_IN_L1_V1_8822B 0x7 -#define BIT_IN_L1_V1_8822B(x) (((x) & BIT_MASK_IN_L1_V1_8822B) << BIT_SHIFT_IN_L1_V1_8822B) -#define BIT_GET_IN_L1_V1_8822B(x) (((x) >> BIT_SHIFT_IN_L1_V1_8822B) & BIT_MASK_IN_L1_V1_8822B) - - +#define BIT_IN_L1_V1_8822B(x) \ + (((x) & BIT_MASK_IN_L1_V1_8822B) << BIT_SHIFT_IN_L1_V1_8822B) +#define BITS_IN_L1_V1_8822B \ + (BIT_MASK_IN_L1_V1_8822B << BIT_SHIFT_IN_L1_V1_8822B) +#define BIT_CLEAR_IN_L1_V1_8822B(x) ((x) & (~BITS_IN_L1_V1_8822B)) +#define BIT_GET_IN_L1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_IN_L1_V1_8822B) & BIT_MASK_IN_L1_V1_8822B) +#define BIT_SET_IN_L1_V1_8822B(x, v) \ + (BIT_CLEAR_IN_L1_V1_8822B(x) | BIT_IN_L1_V1_8822B(v)) #define BIT_SHIFT_TBOX_L1_8822B 15 #define BIT_MASK_TBOX_L1_8822B 0x3 -#define BIT_TBOX_L1_8822B(x) (((x) & BIT_MASK_TBOX_L1_8822B) << BIT_SHIFT_TBOX_L1_8822B) -#define BIT_GET_TBOX_L1_8822B(x) (((x) >> BIT_SHIFT_TBOX_L1_8822B) & BIT_MASK_TBOX_L1_8822B) - +#define BIT_TBOX_L1_8822B(x) \ + (((x) & BIT_MASK_TBOX_L1_8822B) << BIT_SHIFT_TBOX_L1_8822B) +#define BITS_TBOX_L1_8822B (BIT_MASK_TBOX_L1_8822B << BIT_SHIFT_TBOX_L1_8822B) +#define BIT_CLEAR_TBOX_L1_8822B(x) ((x) & (~BITS_TBOX_L1_8822B)) +#define BIT_GET_TBOX_L1_8822B(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_8822B) & BIT_MASK_TBOX_L1_8822B) +#define BIT_SET_TBOX_L1_8822B(x, v) \ + (BIT_CLEAR_TBOX_L1_8822B(x) | BIT_TBOX_L1_8822B(v)) #define BIT_SW18_SEL_8822B BIT(13) @@ -227,29 +287,44 @@ #define BIT_SHIFT_R3_L_8822B 7 #define BIT_MASK_R3_L_8822B 0x3 #define BIT_R3_L_8822B(x) (((x) & BIT_MASK_R3_L_8822B) << BIT_SHIFT_R3_L_8822B) -#define BIT_GET_R3_L_8822B(x) (((x) >> BIT_SHIFT_R3_L_8822B) & BIT_MASK_R3_L_8822B) - - +#define BITS_R3_L_8822B (BIT_MASK_R3_L_8822B << BIT_SHIFT_R3_L_8822B) +#define BIT_CLEAR_R3_L_8822B(x) ((x) & (~BITS_R3_L_8822B)) +#define BIT_GET_R3_L_8822B(x) \ + (((x) >> BIT_SHIFT_R3_L_8822B) & BIT_MASK_R3_L_8822B) +#define BIT_SET_R3_L_8822B(x, v) (BIT_CLEAR_R3_L_8822B(x) | BIT_R3_L_8822B(v)) #define BIT_SHIFT_SW18_R2_8822B 5 #define BIT_MASK_SW18_R2_8822B 0x3 -#define BIT_SW18_R2_8822B(x) (((x) & BIT_MASK_SW18_R2_8822B) << BIT_SHIFT_SW18_R2_8822B) -#define BIT_GET_SW18_R2_8822B(x) (((x) >> BIT_SHIFT_SW18_R2_8822B) & BIT_MASK_SW18_R2_8822B) - - +#define BIT_SW18_R2_8822B(x) \ + (((x) & BIT_MASK_SW18_R2_8822B) << BIT_SHIFT_SW18_R2_8822B) +#define BITS_SW18_R2_8822B (BIT_MASK_SW18_R2_8822B << BIT_SHIFT_SW18_R2_8822B) +#define BIT_CLEAR_SW18_R2_8822B(x) ((x) & (~BITS_SW18_R2_8822B)) +#define BIT_GET_SW18_R2_8822B(x) \ + (((x) >> BIT_SHIFT_SW18_R2_8822B) & BIT_MASK_SW18_R2_8822B) +#define BIT_SET_SW18_R2_8822B(x, v) \ + (BIT_CLEAR_SW18_R2_8822B(x) | BIT_SW18_R2_8822B(v)) #define BIT_SHIFT_SW18_R1_8822B 3 #define BIT_MASK_SW18_R1_8822B 0x3 -#define BIT_SW18_R1_8822B(x) (((x) & BIT_MASK_SW18_R1_8822B) << BIT_SHIFT_SW18_R1_8822B) -#define BIT_GET_SW18_R1_8822B(x) (((x) >> BIT_SHIFT_SW18_R1_8822B) & BIT_MASK_SW18_R1_8822B) - - +#define BIT_SW18_R1_8822B(x) \ + (((x) & BIT_MASK_SW18_R1_8822B) << BIT_SHIFT_SW18_R1_8822B) +#define BITS_SW18_R1_8822B (BIT_MASK_SW18_R1_8822B << BIT_SHIFT_SW18_R1_8822B) +#define BIT_CLEAR_SW18_R1_8822B(x) ((x) & (~BITS_SW18_R1_8822B)) +#define BIT_GET_SW18_R1_8822B(x) \ + (((x) >> BIT_SHIFT_SW18_R1_8822B) & BIT_MASK_SW18_R1_8822B) +#define BIT_SET_SW18_R1_8822B(x, v) \ + (BIT_CLEAR_SW18_R1_8822B(x) | BIT_SW18_R1_8822B(v)) #define BIT_SHIFT_C3_L_C3_8822B 1 #define BIT_MASK_C3_L_C3_8822B 0x3 -#define BIT_C3_L_C3_8822B(x) (((x) & BIT_MASK_C3_L_C3_8822B) << BIT_SHIFT_C3_L_C3_8822B) -#define BIT_GET_C3_L_C3_8822B(x) (((x) >> BIT_SHIFT_C3_L_C3_8822B) & BIT_MASK_C3_L_C3_8822B) - +#define BIT_C3_L_C3_8822B(x) \ + (((x) & BIT_MASK_C3_L_C3_8822B) << BIT_SHIFT_C3_L_C3_8822B) +#define BITS_C3_L_C3_8822B (BIT_MASK_C3_L_C3_8822B << BIT_SHIFT_C3_L_C3_8822B) +#define BIT_CLEAR_C3_L_C3_8822B(x) ((x) & (~BITS_C3_L_C3_8822B)) +#define BIT_GET_C3_L_C3_8822B(x) \ + (((x) >> BIT_SHIFT_C3_L_C3_8822B) & BIT_MASK_C3_L_C3_8822B) +#define BIT_SET_C3_L_C3_8822B(x, v) \ + (BIT_CLEAR_C3_L_C3_8822B(x) | BIT_C3_L_C3_8822B(v)) #define BIT_C2_L_BIT1_8822B BIT(0) @@ -258,17 +333,27 @@ #define BIT_SHIFT_SPS18_OCP_TH_8822B 16 #define BIT_MASK_SPS18_OCP_TH_8822B 0x7fff -#define BIT_SPS18_OCP_TH_8822B(x) (((x) & BIT_MASK_SPS18_OCP_TH_8822B) << BIT_SHIFT_SPS18_OCP_TH_8822B) -#define BIT_GET_SPS18_OCP_TH_8822B(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8822B) & BIT_MASK_SPS18_OCP_TH_8822B) - - +#define BIT_SPS18_OCP_TH_8822B(x) \ + (((x) & BIT_MASK_SPS18_OCP_TH_8822B) << BIT_SHIFT_SPS18_OCP_TH_8822B) +#define BITS_SPS18_OCP_TH_8822B \ + (BIT_MASK_SPS18_OCP_TH_8822B << BIT_SHIFT_SPS18_OCP_TH_8822B) +#define BIT_CLEAR_SPS18_OCP_TH_8822B(x) ((x) & (~BITS_SPS18_OCP_TH_8822B)) +#define BIT_GET_SPS18_OCP_TH_8822B(x) \ + (((x) >> BIT_SHIFT_SPS18_OCP_TH_8822B) & BIT_MASK_SPS18_OCP_TH_8822B) +#define BIT_SET_SPS18_OCP_TH_8822B(x, v) \ + (BIT_CLEAR_SPS18_OCP_TH_8822B(x) | BIT_SPS18_OCP_TH_8822B(v)) #define BIT_SHIFT_OCP_WINDOW_8822B 0 #define BIT_MASK_OCP_WINDOW_8822B 0xffff -#define BIT_OCP_WINDOW_8822B(x) (((x) & BIT_MASK_OCP_WINDOW_8822B) << BIT_SHIFT_OCP_WINDOW_8822B) -#define BIT_GET_OCP_WINDOW_8822B(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8822B) & BIT_MASK_OCP_WINDOW_8822B) - - +#define BIT_OCP_WINDOW_8822B(x) \ + (((x) & BIT_MASK_OCP_WINDOW_8822B) << BIT_SHIFT_OCP_WINDOW_8822B) +#define BITS_OCP_WINDOW_8822B \ + (BIT_MASK_OCP_WINDOW_8822B << BIT_SHIFT_OCP_WINDOW_8822B) +#define BIT_CLEAR_OCP_WINDOW_8822B(x) ((x) & (~BITS_OCP_WINDOW_8822B)) +#define BIT_GET_OCP_WINDOW_8822B(x) \ + (((x) >> BIT_SHIFT_OCP_WINDOW_8822B) & BIT_MASK_OCP_WINDOW_8822B) +#define BIT_SET_OCP_WINDOW_8822B(x, v) \ + (BIT_CLEAR_OCP_WINDOW_8822B(x) | BIT_OCP_WINDOW_8822B(v)) /* 2 REG_RSV_CTRL_8822B */ #define BIT_HREG_DBG_8822B BIT(23) @@ -291,17 +376,29 @@ #define BIT_SHIFT_LPLDH12_RSV_8822B 29 #define BIT_MASK_LPLDH12_RSV_8822B 0x7 -#define BIT_LPLDH12_RSV_8822B(x) (((x) & BIT_MASK_LPLDH12_RSV_8822B) << BIT_SHIFT_LPLDH12_RSV_8822B) -#define BIT_GET_LPLDH12_RSV_8822B(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8822B) & BIT_MASK_LPLDH12_RSV_8822B) - +#define BIT_LPLDH12_RSV_8822B(x) \ + (((x) & BIT_MASK_LPLDH12_RSV_8822B) << BIT_SHIFT_LPLDH12_RSV_8822B) +#define BITS_LPLDH12_RSV_8822B \ + (BIT_MASK_LPLDH12_RSV_8822B << BIT_SHIFT_LPLDH12_RSV_8822B) +#define BIT_CLEAR_LPLDH12_RSV_8822B(x) ((x) & (~BITS_LPLDH12_RSV_8822B)) +#define BIT_GET_LPLDH12_RSV_8822B(x) \ + (((x) >> BIT_SHIFT_LPLDH12_RSV_8822B) & BIT_MASK_LPLDH12_RSV_8822B) +#define BIT_SET_LPLDH12_RSV_8822B(x, v) \ + (BIT_CLEAR_LPLDH12_RSV_8822B(x) | BIT_LPLDH12_RSV_8822B(v)) #define BIT_LPLDH12_SLP_8822B BIT(28) #define BIT_SHIFT_LPLDH12_VADJ_8822B 24 #define BIT_MASK_LPLDH12_VADJ_8822B 0xf -#define BIT_LPLDH12_VADJ_8822B(x) (((x) & BIT_MASK_LPLDH12_VADJ_8822B) << BIT_SHIFT_LPLDH12_VADJ_8822B) -#define BIT_GET_LPLDH12_VADJ_8822B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8822B) & BIT_MASK_LPLDH12_VADJ_8822B) - +#define BIT_LPLDH12_VADJ_8822B(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_8822B) << BIT_SHIFT_LPLDH12_VADJ_8822B) +#define BITS_LPLDH12_VADJ_8822B \ + (BIT_MASK_LPLDH12_VADJ_8822B << BIT_SHIFT_LPLDH12_VADJ_8822B) +#define BIT_CLEAR_LPLDH12_VADJ_8822B(x) ((x) & (~BITS_LPLDH12_VADJ_8822B)) +#define BIT_GET_LPLDH12_VADJ_8822B(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_8822B) & BIT_MASK_LPLDH12_VADJ_8822B) +#define BIT_SET_LPLDH12_VADJ_8822B(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_8822B(x) | BIT_LPLDH12_VADJ_8822B(v)) #define BIT_LDH12_EN_8822B BIT(16) #define BIT_WLBBOFF_BIG_PWC_EN_8822B BIT(14) @@ -325,46 +422,79 @@ #define BIT_SHIFT_XTAL_CAP_XI_8822B 25 #define BIT_MASK_XTAL_CAP_XI_8822B 0x3f -#define BIT_XTAL_CAP_XI_8822B(x) (((x) & BIT_MASK_XTAL_CAP_XI_8822B) << BIT_SHIFT_XTAL_CAP_XI_8822B) -#define BIT_GET_XTAL_CAP_XI_8822B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8822B) & BIT_MASK_XTAL_CAP_XI_8822B) - - +#define BIT_XTAL_CAP_XI_8822B(x) \ + (((x) & BIT_MASK_XTAL_CAP_XI_8822B) << BIT_SHIFT_XTAL_CAP_XI_8822B) +#define BITS_XTAL_CAP_XI_8822B \ + (BIT_MASK_XTAL_CAP_XI_8822B << BIT_SHIFT_XTAL_CAP_XI_8822B) +#define BIT_CLEAR_XTAL_CAP_XI_8822B(x) ((x) & (~BITS_XTAL_CAP_XI_8822B)) +#define BIT_GET_XTAL_CAP_XI_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XI_8822B) & BIT_MASK_XTAL_CAP_XI_8822B) +#define BIT_SET_XTAL_CAP_XI_8822B(x, v) \ + (BIT_CLEAR_XTAL_CAP_XI_8822B(x) | BIT_XTAL_CAP_XI_8822B(v)) #define BIT_SHIFT_XTAL_DRV_DIGI_8822B 23 #define BIT_MASK_XTAL_DRV_DIGI_8822B 0x3 -#define BIT_XTAL_DRV_DIGI_8822B(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8822B) << BIT_SHIFT_XTAL_DRV_DIGI_8822B) -#define BIT_GET_XTAL_DRV_DIGI_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8822B) & BIT_MASK_XTAL_DRV_DIGI_8822B) - +#define BIT_XTAL_DRV_DIGI_8822B(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_8822B) << BIT_SHIFT_XTAL_DRV_DIGI_8822B) +#define BITS_XTAL_DRV_DIGI_8822B \ + (BIT_MASK_XTAL_DRV_DIGI_8822B << BIT_SHIFT_XTAL_DRV_DIGI_8822B) +#define BIT_CLEAR_XTAL_DRV_DIGI_8822B(x) ((x) & (~BITS_XTAL_DRV_DIGI_8822B)) +#define BIT_GET_XTAL_DRV_DIGI_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8822B) & BIT_MASK_XTAL_DRV_DIGI_8822B) +#define BIT_SET_XTAL_DRV_DIGI_8822B(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_8822B(x) | BIT_XTAL_DRV_DIGI_8822B(v)) #define BIT_XTAL_DRV_USB_BIT1_8822B BIT(22) #define BIT_SHIFT_MAC_CLK_SEL_8822B 20 #define BIT_MASK_MAC_CLK_SEL_8822B 0x3 -#define BIT_MAC_CLK_SEL_8822B(x) (((x) & BIT_MASK_MAC_CLK_SEL_8822B) << BIT_SHIFT_MAC_CLK_SEL_8822B) -#define BIT_GET_MAC_CLK_SEL_8822B(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8822B) & BIT_MASK_MAC_CLK_SEL_8822B) - +#define BIT_MAC_CLK_SEL_8822B(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL_8822B) << BIT_SHIFT_MAC_CLK_SEL_8822B) +#define BITS_MAC_CLK_SEL_8822B \ + (BIT_MASK_MAC_CLK_SEL_8822B << BIT_SHIFT_MAC_CLK_SEL_8822B) +#define BIT_CLEAR_MAC_CLK_SEL_8822B(x) ((x) & (~BITS_MAC_CLK_SEL_8822B)) +#define BIT_GET_MAC_CLK_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL_8822B) & BIT_MASK_MAC_CLK_SEL_8822B) +#define BIT_SET_MAC_CLK_SEL_8822B(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL_8822B(x) | BIT_MAC_CLK_SEL_8822B(v)) #define BIT_XTAL_DRV_USB_BIT0_8822B BIT(19) #define BIT_SHIFT_XTAL_DRV_AFE_8822B 17 #define BIT_MASK_XTAL_DRV_AFE_8822B 0x3 -#define BIT_XTAL_DRV_AFE_8822B(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8822B) << BIT_SHIFT_XTAL_DRV_AFE_8822B) -#define BIT_GET_XTAL_DRV_AFE_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8822B) & BIT_MASK_XTAL_DRV_AFE_8822B) - - +#define BIT_XTAL_DRV_AFE_8822B(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_8822B) << BIT_SHIFT_XTAL_DRV_AFE_8822B) +#define BITS_XTAL_DRV_AFE_8822B \ + (BIT_MASK_XTAL_DRV_AFE_8822B << BIT_SHIFT_XTAL_DRV_AFE_8822B) +#define BIT_CLEAR_XTAL_DRV_AFE_8822B(x) ((x) & (~BITS_XTAL_DRV_AFE_8822B)) +#define BIT_GET_XTAL_DRV_AFE_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8822B) & BIT_MASK_XTAL_DRV_AFE_8822B) +#define BIT_SET_XTAL_DRV_AFE_8822B(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_8822B(x) | BIT_XTAL_DRV_AFE_8822B(v)) #define BIT_SHIFT_XTAL_DRV_RF2_8822B 15 #define BIT_MASK_XTAL_DRV_RF2_8822B 0x3 -#define BIT_XTAL_DRV_RF2_8822B(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8822B) << BIT_SHIFT_XTAL_DRV_RF2_8822B) -#define BIT_GET_XTAL_DRV_RF2_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8822B) & BIT_MASK_XTAL_DRV_RF2_8822B) - - +#define BIT_XTAL_DRV_RF2_8822B(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_8822B) << BIT_SHIFT_XTAL_DRV_RF2_8822B) +#define BITS_XTAL_DRV_RF2_8822B \ + (BIT_MASK_XTAL_DRV_RF2_8822B << BIT_SHIFT_XTAL_DRV_RF2_8822B) +#define BIT_CLEAR_XTAL_DRV_RF2_8822B(x) ((x) & (~BITS_XTAL_DRV_RF2_8822B)) +#define BIT_GET_XTAL_DRV_RF2_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8822B) & BIT_MASK_XTAL_DRV_RF2_8822B) +#define BIT_SET_XTAL_DRV_RF2_8822B(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_8822B(x) | BIT_XTAL_DRV_RF2_8822B(v)) #define BIT_SHIFT_XTAL_DRV_RF1_8822B 13 #define BIT_MASK_XTAL_DRV_RF1_8822B 0x3 -#define BIT_XTAL_DRV_RF1_8822B(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8822B) << BIT_SHIFT_XTAL_DRV_RF1_8822B) -#define BIT_GET_XTAL_DRV_RF1_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822B) & BIT_MASK_XTAL_DRV_RF1_8822B) - +#define BIT_XTAL_DRV_RF1_8822B(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF1_8822B) << BIT_SHIFT_XTAL_DRV_RF1_8822B) +#define BITS_XTAL_DRV_RF1_8822B \ + (BIT_MASK_XTAL_DRV_RF1_8822B << BIT_SHIFT_XTAL_DRV_RF1_8822B) +#define BIT_CLEAR_XTAL_DRV_RF1_8822B(x) ((x) & (~BITS_XTAL_DRV_RF1_8822B)) +#define BIT_GET_XTAL_DRV_RF1_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822B) & BIT_MASK_XTAL_DRV_RF1_8822B) +#define BIT_SET_XTAL_DRV_RF1_8822B(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF1_8822B(x) | BIT_XTAL_DRV_RF1_8822B(v)) #define BIT_XTAL_DELAY_DIGI_8822B BIT(12) #define BIT_XTAL_DELAY_USB_8822B BIT(11) @@ -372,25 +502,42 @@ #define BIT_SHIFT_XTAL_LDO_VREF_8822B 7 #define BIT_MASK_XTAL_LDO_VREF_8822B 0x7 -#define BIT_XTAL_LDO_VREF_8822B(x) (((x) & BIT_MASK_XTAL_LDO_VREF_8822B) << BIT_SHIFT_XTAL_LDO_VREF_8822B) -#define BIT_GET_XTAL_LDO_VREF_8822B(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8822B) & BIT_MASK_XTAL_LDO_VREF_8822B) - +#define BIT_XTAL_LDO_VREF_8822B(x) \ + (((x) & BIT_MASK_XTAL_LDO_VREF_8822B) << BIT_SHIFT_XTAL_LDO_VREF_8822B) +#define BITS_XTAL_LDO_VREF_8822B \ + (BIT_MASK_XTAL_LDO_VREF_8822B << BIT_SHIFT_XTAL_LDO_VREF_8822B) +#define BIT_CLEAR_XTAL_LDO_VREF_8822B(x) ((x) & (~BITS_XTAL_LDO_VREF_8822B)) +#define BIT_GET_XTAL_LDO_VREF_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8822B) & BIT_MASK_XTAL_LDO_VREF_8822B) +#define BIT_SET_XTAL_LDO_VREF_8822B(x, v) \ + (BIT_CLEAR_XTAL_LDO_VREF_8822B(x) | BIT_XTAL_LDO_VREF_8822B(v)) #define BIT_XTAL_XQSEL_RF_8822B BIT(6) #define BIT_XTAL_XQSEL_8822B BIT(5) #define BIT_SHIFT_XTAL_GMN_V2_8822B 3 #define BIT_MASK_XTAL_GMN_V2_8822B 0x3 -#define BIT_XTAL_GMN_V2_8822B(x) (((x) & BIT_MASK_XTAL_GMN_V2_8822B) << BIT_SHIFT_XTAL_GMN_V2_8822B) -#define BIT_GET_XTAL_GMN_V2_8822B(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2_8822B) & BIT_MASK_XTAL_GMN_V2_8822B) - - +#define BIT_XTAL_GMN_V2_8822B(x) \ + (((x) & BIT_MASK_XTAL_GMN_V2_8822B) << BIT_SHIFT_XTAL_GMN_V2_8822B) +#define BITS_XTAL_GMN_V2_8822B \ + (BIT_MASK_XTAL_GMN_V2_8822B << BIT_SHIFT_XTAL_GMN_V2_8822B) +#define BIT_CLEAR_XTAL_GMN_V2_8822B(x) ((x) & (~BITS_XTAL_GMN_V2_8822B)) +#define BIT_GET_XTAL_GMN_V2_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V2_8822B) & BIT_MASK_XTAL_GMN_V2_8822B) +#define BIT_SET_XTAL_GMN_V2_8822B(x, v) \ + (BIT_CLEAR_XTAL_GMN_V2_8822B(x) | BIT_XTAL_GMN_V2_8822B(v)) #define BIT_SHIFT_XTAL_GMP_V2_8822B 1 #define BIT_MASK_XTAL_GMP_V2_8822B 0x3 -#define BIT_XTAL_GMP_V2_8822B(x) (((x) & BIT_MASK_XTAL_GMP_V2_8822B) << BIT_SHIFT_XTAL_GMP_V2_8822B) -#define BIT_GET_XTAL_GMP_V2_8822B(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2_8822B) & BIT_MASK_XTAL_GMP_V2_8822B) - +#define BIT_XTAL_GMP_V2_8822B(x) \ + (((x) & BIT_MASK_XTAL_GMP_V2_8822B) << BIT_SHIFT_XTAL_GMP_V2_8822B) +#define BITS_XTAL_GMP_V2_8822B \ + (BIT_MASK_XTAL_GMP_V2_8822B << BIT_SHIFT_XTAL_GMP_V2_8822B) +#define BIT_CLEAR_XTAL_GMP_V2_8822B(x) ((x) & (~BITS_XTAL_GMP_V2_8822B)) +#define BIT_GET_XTAL_GMP_V2_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V2_8822B) & BIT_MASK_XTAL_GMP_V2_8822B) +#define BIT_SET_XTAL_GMP_V2_8822B(x, v) \ + (BIT_CLEAR_XTAL_GMP_V2_8822B(x) | BIT_XTAL_GMP_V2_8822B(v)) #define BIT_XTAL_EN_8822B BIT(0) @@ -398,38 +545,63 @@ #define BIT_SHIFT_REG_C3_V4_8822B 30 #define BIT_MASK_REG_C3_V4_8822B 0x3 -#define BIT_REG_C3_V4_8822B(x) (((x) & BIT_MASK_REG_C3_V4_8822B) << BIT_SHIFT_REG_C3_V4_8822B) -#define BIT_GET_REG_C3_V4_8822B(x) (((x) >> BIT_SHIFT_REG_C3_V4_8822B) & BIT_MASK_REG_C3_V4_8822B) - +#define BIT_REG_C3_V4_8822B(x) \ + (((x) & BIT_MASK_REG_C3_V4_8822B) << BIT_SHIFT_REG_C3_V4_8822B) +#define BITS_REG_C3_V4_8822B \ + (BIT_MASK_REG_C3_V4_8822B << BIT_SHIFT_REG_C3_V4_8822B) +#define BIT_CLEAR_REG_C3_V4_8822B(x) ((x) & (~BITS_REG_C3_V4_8822B)) +#define BIT_GET_REG_C3_V4_8822B(x) \ + (((x) >> BIT_SHIFT_REG_C3_V4_8822B) & BIT_MASK_REG_C3_V4_8822B) +#define BIT_SET_REG_C3_V4_8822B(x, v) \ + (BIT_CLEAR_REG_C3_V4_8822B(x) | BIT_REG_C3_V4_8822B(v)) #define BIT_REG_CP_BIT1_8822B BIT(29) #define BIT_SHIFT_REG_RS_V4_8822B 26 #define BIT_MASK_REG_RS_V4_8822B 0x7 -#define BIT_REG_RS_V4_8822B(x) (((x) & BIT_MASK_REG_RS_V4_8822B) << BIT_SHIFT_REG_RS_V4_8822B) -#define BIT_GET_REG_RS_V4_8822B(x) (((x) >> BIT_SHIFT_REG_RS_V4_8822B) & BIT_MASK_REG_RS_V4_8822B) - - +#define BIT_REG_RS_V4_8822B(x) \ + (((x) & BIT_MASK_REG_RS_V4_8822B) << BIT_SHIFT_REG_RS_V4_8822B) +#define BITS_REG_RS_V4_8822B \ + (BIT_MASK_REG_RS_V4_8822B << BIT_SHIFT_REG_RS_V4_8822B) +#define BIT_CLEAR_REG_RS_V4_8822B(x) ((x) & (~BITS_REG_RS_V4_8822B)) +#define BIT_GET_REG_RS_V4_8822B(x) \ + (((x) >> BIT_SHIFT_REG_RS_V4_8822B) & BIT_MASK_REG_RS_V4_8822B) +#define BIT_SET_REG_RS_V4_8822B(x, v) \ + (BIT_CLEAR_REG_RS_V4_8822B(x) | BIT_REG_RS_V4_8822B(v)) #define BIT_SHIFT_REG__CS_8822B 24 #define BIT_MASK_REG__CS_8822B 0x3 -#define BIT_REG__CS_8822B(x) (((x) & BIT_MASK_REG__CS_8822B) << BIT_SHIFT_REG__CS_8822B) -#define BIT_GET_REG__CS_8822B(x) (((x) >> BIT_SHIFT_REG__CS_8822B) & BIT_MASK_REG__CS_8822B) - - +#define BIT_REG__CS_8822B(x) \ + (((x) & BIT_MASK_REG__CS_8822B) << BIT_SHIFT_REG__CS_8822B) +#define BITS_REG__CS_8822B (BIT_MASK_REG__CS_8822B << BIT_SHIFT_REG__CS_8822B) +#define BIT_CLEAR_REG__CS_8822B(x) ((x) & (~BITS_REG__CS_8822B)) +#define BIT_GET_REG__CS_8822B(x) \ + (((x) >> BIT_SHIFT_REG__CS_8822B) & BIT_MASK_REG__CS_8822B) +#define BIT_SET_REG__CS_8822B(x, v) \ + (BIT_CLEAR_REG__CS_8822B(x) | BIT_REG__CS_8822B(v)) #define BIT_SHIFT_REG_CP_OFFSET_8822B 21 #define BIT_MASK_REG_CP_OFFSET_8822B 0x7 -#define BIT_REG_CP_OFFSET_8822B(x) (((x) & BIT_MASK_REG_CP_OFFSET_8822B) << BIT_SHIFT_REG_CP_OFFSET_8822B) -#define BIT_GET_REG_CP_OFFSET_8822B(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_8822B) & BIT_MASK_REG_CP_OFFSET_8822B) - - +#define BIT_REG_CP_OFFSET_8822B(x) \ + (((x) & BIT_MASK_REG_CP_OFFSET_8822B) << BIT_SHIFT_REG_CP_OFFSET_8822B) +#define BITS_REG_CP_OFFSET_8822B \ + (BIT_MASK_REG_CP_OFFSET_8822B << BIT_SHIFT_REG_CP_OFFSET_8822B) +#define BIT_CLEAR_REG_CP_OFFSET_8822B(x) ((x) & (~BITS_REG_CP_OFFSET_8822B)) +#define BIT_GET_REG_CP_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_REG_CP_OFFSET_8822B) & BIT_MASK_REG_CP_OFFSET_8822B) +#define BIT_SET_REG_CP_OFFSET_8822B(x, v) \ + (BIT_CLEAR_REG_CP_OFFSET_8822B(x) | BIT_REG_CP_OFFSET_8822B(v)) #define BIT_SHIFT_CP_BIAS_8822B 18 #define BIT_MASK_CP_BIAS_8822B 0x7 -#define BIT_CP_BIAS_8822B(x) (((x) & BIT_MASK_CP_BIAS_8822B) << BIT_SHIFT_CP_BIAS_8822B) -#define BIT_GET_CP_BIAS_8822B(x) (((x) >> BIT_SHIFT_CP_BIAS_8822B) & BIT_MASK_CP_BIAS_8822B) - +#define BIT_CP_BIAS_8822B(x) \ + (((x) & BIT_MASK_CP_BIAS_8822B) << BIT_SHIFT_CP_BIAS_8822B) +#define BITS_CP_BIAS_8822B (BIT_MASK_CP_BIAS_8822B << BIT_SHIFT_CP_BIAS_8822B) +#define BIT_CLEAR_CP_BIAS_8822B(x) ((x) & (~BITS_CP_BIAS_8822B)) +#define BIT_GET_CP_BIAS_8822B(x) \ + (((x) >> BIT_SHIFT_CP_BIAS_8822B) & BIT_MASK_CP_BIAS_8822B) +#define BIT_SET_CP_BIAS_8822B(x, v) \ + (BIT_CLEAR_CP_BIAS_8822B(x) | BIT_CP_BIAS_8822B(v)) #define BIT_REG_IDOUBLE_V2_8822B BIT(17) #define BIT_EN_SYN_8822B BIT(16) @@ -437,31 +609,50 @@ #define BIT_SHIFT_MCCO_8822B 14 #define BIT_MASK_MCCO_8822B 0x3 #define BIT_MCCO_8822B(x) (((x) & BIT_MASK_MCCO_8822B) << BIT_SHIFT_MCCO_8822B) -#define BIT_GET_MCCO_8822B(x) (((x) >> BIT_SHIFT_MCCO_8822B) & BIT_MASK_MCCO_8822B) - - +#define BITS_MCCO_8822B (BIT_MASK_MCCO_8822B << BIT_SHIFT_MCCO_8822B) +#define BIT_CLEAR_MCCO_8822B(x) ((x) & (~BITS_MCCO_8822B)) +#define BIT_GET_MCCO_8822B(x) \ + (((x) >> BIT_SHIFT_MCCO_8822B) & BIT_MASK_MCCO_8822B) +#define BIT_SET_MCCO_8822B(x, v) (BIT_CLEAR_MCCO_8822B(x) | BIT_MCCO_8822B(v)) #define BIT_SHIFT_REG_LDO_SEL_8822B 12 #define BIT_MASK_REG_LDO_SEL_8822B 0x3 -#define BIT_REG_LDO_SEL_8822B(x) (((x) & BIT_MASK_REG_LDO_SEL_8822B) << BIT_SHIFT_REG_LDO_SEL_8822B) -#define BIT_GET_REG_LDO_SEL_8822B(x) (((x) >> BIT_SHIFT_REG_LDO_SEL_8822B) & BIT_MASK_REG_LDO_SEL_8822B) - +#define BIT_REG_LDO_SEL_8822B(x) \ + (((x) & BIT_MASK_REG_LDO_SEL_8822B) << BIT_SHIFT_REG_LDO_SEL_8822B) +#define BITS_REG_LDO_SEL_8822B \ + (BIT_MASK_REG_LDO_SEL_8822B << BIT_SHIFT_REG_LDO_SEL_8822B) +#define BIT_CLEAR_REG_LDO_SEL_8822B(x) ((x) & (~BITS_REG_LDO_SEL_8822B)) +#define BIT_GET_REG_LDO_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_REG_LDO_SEL_8822B) & BIT_MASK_REG_LDO_SEL_8822B) +#define BIT_SET_REG_LDO_SEL_8822B(x, v) \ + (BIT_CLEAR_REG_LDO_SEL_8822B(x) | BIT_REG_LDO_SEL_8822B(v)) #define BIT_REG_KVCO_V2_8822B BIT(10) #define BIT_AGPIO_GPO_8822B BIT(9) #define BIT_SHIFT_AGPIO_DRV_8822B 7 #define BIT_MASK_AGPIO_DRV_8822B 0x3 -#define BIT_AGPIO_DRV_8822B(x) (((x) & BIT_MASK_AGPIO_DRV_8822B) << BIT_SHIFT_AGPIO_DRV_8822B) -#define BIT_GET_AGPIO_DRV_8822B(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8822B) & BIT_MASK_AGPIO_DRV_8822B) - - +#define BIT_AGPIO_DRV_8822B(x) \ + (((x) & BIT_MASK_AGPIO_DRV_8822B) << BIT_SHIFT_AGPIO_DRV_8822B) +#define BITS_AGPIO_DRV_8822B \ + (BIT_MASK_AGPIO_DRV_8822B << BIT_SHIFT_AGPIO_DRV_8822B) +#define BIT_CLEAR_AGPIO_DRV_8822B(x) ((x) & (~BITS_AGPIO_DRV_8822B)) +#define BIT_GET_AGPIO_DRV_8822B(x) \ + (((x) >> BIT_SHIFT_AGPIO_DRV_8822B) & BIT_MASK_AGPIO_DRV_8822B) +#define BIT_SET_AGPIO_DRV_8822B(x, v) \ + (BIT_CLEAR_AGPIO_DRV_8822B(x) | BIT_AGPIO_DRV_8822B(v)) #define BIT_SHIFT_XTAL_CAP_XO_8822B 1 #define BIT_MASK_XTAL_CAP_XO_8822B 0x3f -#define BIT_XTAL_CAP_XO_8822B(x) (((x) & BIT_MASK_XTAL_CAP_XO_8822B) << BIT_SHIFT_XTAL_CAP_XO_8822B) -#define BIT_GET_XTAL_CAP_XO_8822B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8822B) & BIT_MASK_XTAL_CAP_XO_8822B) - +#define BIT_XTAL_CAP_XO_8822B(x) \ + (((x) & BIT_MASK_XTAL_CAP_XO_8822B) << BIT_SHIFT_XTAL_CAP_XO_8822B) +#define BITS_XTAL_CAP_XO_8822B \ + (BIT_MASK_XTAL_CAP_XO_8822B << BIT_SHIFT_XTAL_CAP_XO_8822B) +#define BIT_CLEAR_XTAL_CAP_XO_8822B(x) ((x) & (~BITS_XTAL_CAP_XO_8822B)) +#define BIT_GET_XTAL_CAP_XO_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XO_8822B) & BIT_MASK_XTAL_CAP_XO_8822B) +#define BIT_SET_XTAL_CAP_XO_8822B(x, v) \ + (BIT_CLEAR_XTAL_CAP_XO_8822B(x) | BIT_XTAL_CAP_XO_8822B(v)) #define BIT_POW_PLL_8822B BIT(0) @@ -470,8 +661,10 @@ #define BIT_SHIFT_PS_8822B 7 #define BIT_MASK_PS_8822B 0x7 #define BIT_PS_8822B(x) (((x) & BIT_MASK_PS_8822B) << BIT_SHIFT_PS_8822B) +#define BITS_PS_8822B (BIT_MASK_PS_8822B << BIT_SHIFT_PS_8822B) +#define BIT_CLEAR_PS_8822B(x) ((x) & (~BITS_PS_8822B)) #define BIT_GET_PS_8822B(x) (((x) >> BIT_SHIFT_PS_8822B) & BIT_MASK_PS_8822B) - +#define BIT_SET_PS_8822B(x, v) (BIT_CLEAR_PS_8822B(x) | BIT_PS_8822B(v)) #define BIT_PSEN_8822B BIT(6) #define BIT_DOGENB_8822B BIT(5) @@ -479,9 +672,15 @@ #define BIT_SHIFT_REG_R3_V4_8822B 1 #define BIT_MASK_REG_R3_V4_8822B 0x7 -#define BIT_REG_R3_V4_8822B(x) (((x) & BIT_MASK_REG_R3_V4_8822B) << BIT_SHIFT_REG_R3_V4_8822B) -#define BIT_GET_REG_R3_V4_8822B(x) (((x) >> BIT_SHIFT_REG_R3_V4_8822B) & BIT_MASK_REG_R3_V4_8822B) - +#define BIT_REG_R3_V4_8822B(x) \ + (((x) & BIT_MASK_REG_R3_V4_8822B) << BIT_SHIFT_REG_R3_V4_8822B) +#define BITS_REG_R3_V4_8822B \ + (BIT_MASK_REG_R3_V4_8822B << BIT_SHIFT_REG_R3_V4_8822B) +#define BIT_CLEAR_REG_R3_V4_8822B(x) ((x) & (~BITS_REG_R3_V4_8822B)) +#define BIT_GET_REG_R3_V4_8822B(x) \ + (((x) >> BIT_SHIFT_REG_R3_V4_8822B) & BIT_MASK_REG_R3_V4_8822B) +#define BIT_SET_REG_R3_V4_8822B(x, v) \ + (BIT_CLEAR_REG_R3_V4_8822B(x) | BIT_REG_R3_V4_8822B(v)) #define BIT_REG_CP_BIT0_8822B BIT(0) @@ -490,103 +689,172 @@ #define BIT_SHIFT_EF_PGPD_8822B 28 #define BIT_MASK_EF_PGPD_8822B 0x7 -#define BIT_EF_PGPD_8822B(x) (((x) & BIT_MASK_EF_PGPD_8822B) << BIT_SHIFT_EF_PGPD_8822B) -#define BIT_GET_EF_PGPD_8822B(x) (((x) >> BIT_SHIFT_EF_PGPD_8822B) & BIT_MASK_EF_PGPD_8822B) - - +#define BIT_EF_PGPD_8822B(x) \ + (((x) & BIT_MASK_EF_PGPD_8822B) << BIT_SHIFT_EF_PGPD_8822B) +#define BITS_EF_PGPD_8822B (BIT_MASK_EF_PGPD_8822B << BIT_SHIFT_EF_PGPD_8822B) +#define BIT_CLEAR_EF_PGPD_8822B(x) ((x) & (~BITS_EF_PGPD_8822B)) +#define BIT_GET_EF_PGPD_8822B(x) \ + (((x) >> BIT_SHIFT_EF_PGPD_8822B) & BIT_MASK_EF_PGPD_8822B) +#define BIT_SET_EF_PGPD_8822B(x, v) \ + (BIT_CLEAR_EF_PGPD_8822B(x) | BIT_EF_PGPD_8822B(v)) #define BIT_SHIFT_EF_RDT_8822B 24 #define BIT_MASK_EF_RDT_8822B 0xf -#define BIT_EF_RDT_8822B(x) (((x) & BIT_MASK_EF_RDT_8822B) << BIT_SHIFT_EF_RDT_8822B) -#define BIT_GET_EF_RDT_8822B(x) (((x) >> BIT_SHIFT_EF_RDT_8822B) & BIT_MASK_EF_RDT_8822B) - - +#define BIT_EF_RDT_8822B(x) \ + (((x) & BIT_MASK_EF_RDT_8822B) << BIT_SHIFT_EF_RDT_8822B) +#define BITS_EF_RDT_8822B (BIT_MASK_EF_RDT_8822B << BIT_SHIFT_EF_RDT_8822B) +#define BIT_CLEAR_EF_RDT_8822B(x) ((x) & (~BITS_EF_RDT_8822B)) +#define BIT_GET_EF_RDT_8822B(x) \ + (((x) >> BIT_SHIFT_EF_RDT_8822B) & BIT_MASK_EF_RDT_8822B) +#define BIT_SET_EF_RDT_8822B(x, v) \ + (BIT_CLEAR_EF_RDT_8822B(x) | BIT_EF_RDT_8822B(v)) #define BIT_SHIFT_EF_PGTS_8822B 20 #define BIT_MASK_EF_PGTS_8822B 0xf -#define BIT_EF_PGTS_8822B(x) (((x) & BIT_MASK_EF_PGTS_8822B) << BIT_SHIFT_EF_PGTS_8822B) -#define BIT_GET_EF_PGTS_8822B(x) (((x) >> BIT_SHIFT_EF_PGTS_8822B) & BIT_MASK_EF_PGTS_8822B) - +#define BIT_EF_PGTS_8822B(x) \ + (((x) & BIT_MASK_EF_PGTS_8822B) << BIT_SHIFT_EF_PGTS_8822B) +#define BITS_EF_PGTS_8822B (BIT_MASK_EF_PGTS_8822B << BIT_SHIFT_EF_PGTS_8822B) +#define BIT_CLEAR_EF_PGTS_8822B(x) ((x) & (~BITS_EF_PGTS_8822B)) +#define BIT_GET_EF_PGTS_8822B(x) \ + (((x) >> BIT_SHIFT_EF_PGTS_8822B) & BIT_MASK_EF_PGTS_8822B) +#define BIT_SET_EF_PGTS_8822B(x, v) \ + (BIT_CLEAR_EF_PGTS_8822B(x) | BIT_EF_PGTS_8822B(v)) #define BIT_EF_PDWN_8822B BIT(19) #define BIT_EF_ALDEN_8822B BIT(18) #define BIT_SHIFT_EF_ADDR_8822B 8 #define BIT_MASK_EF_ADDR_8822B 0x3ff -#define BIT_EF_ADDR_8822B(x) (((x) & BIT_MASK_EF_ADDR_8822B) << BIT_SHIFT_EF_ADDR_8822B) -#define BIT_GET_EF_ADDR_8822B(x) (((x) >> BIT_SHIFT_EF_ADDR_8822B) & BIT_MASK_EF_ADDR_8822B) - - +#define BIT_EF_ADDR_8822B(x) \ + (((x) & BIT_MASK_EF_ADDR_8822B) << BIT_SHIFT_EF_ADDR_8822B) +#define BITS_EF_ADDR_8822B (BIT_MASK_EF_ADDR_8822B << BIT_SHIFT_EF_ADDR_8822B) +#define BIT_CLEAR_EF_ADDR_8822B(x) ((x) & (~BITS_EF_ADDR_8822B)) +#define BIT_GET_EF_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_EF_ADDR_8822B) & BIT_MASK_EF_ADDR_8822B) +#define BIT_SET_EF_ADDR_8822B(x, v) \ + (BIT_CLEAR_EF_ADDR_8822B(x) | BIT_EF_ADDR_8822B(v)) #define BIT_SHIFT_EF_DATA_8822B 0 #define BIT_MASK_EF_DATA_8822B 0xff -#define BIT_EF_DATA_8822B(x) (((x) & BIT_MASK_EF_DATA_8822B) << BIT_SHIFT_EF_DATA_8822B) -#define BIT_GET_EF_DATA_8822B(x) (((x) >> BIT_SHIFT_EF_DATA_8822B) & BIT_MASK_EF_DATA_8822B) - - +#define BIT_EF_DATA_8822B(x) \ + (((x) & BIT_MASK_EF_DATA_8822B) << BIT_SHIFT_EF_DATA_8822B) +#define BITS_EF_DATA_8822B (BIT_MASK_EF_DATA_8822B << BIT_SHIFT_EF_DATA_8822B) +#define BIT_CLEAR_EF_DATA_8822B(x) ((x) & (~BITS_EF_DATA_8822B)) +#define BIT_GET_EF_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_EF_DATA_8822B) & BIT_MASK_EF_DATA_8822B) +#define BIT_SET_EF_DATA_8822B(x, v) \ + (BIT_CLEAR_EF_DATA_8822B(x) | BIT_EF_DATA_8822B(v)) /* 2 REG_LDO_EFUSE_CTRL_8822B */ #define BIT_LDOE25_EN_8822B BIT(31) #define BIT_SHIFT_LDOE25_V12ADJ_L_8822B 27 #define BIT_MASK_LDOE25_V12ADJ_L_8822B 0xf -#define BIT_LDOE25_V12ADJ_L_8822B(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8822B) << BIT_SHIFT_LDOE25_V12ADJ_L_8822B) -#define BIT_GET_LDOE25_V12ADJ_L_8822B(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8822B) & BIT_MASK_LDOE25_V12ADJ_L_8822B) - +#define BIT_LDOE25_V12ADJ_L_8822B(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L_8822B) \ + << BIT_SHIFT_LDOE25_V12ADJ_L_8822B) +#define BITS_LDOE25_V12ADJ_L_8822B \ + (BIT_MASK_LDOE25_V12ADJ_L_8822B << BIT_SHIFT_LDOE25_V12ADJ_L_8822B) +#define BIT_CLEAR_LDOE25_V12ADJ_L_8822B(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8822B)) +#define BIT_GET_LDOE25_V12ADJ_L_8822B(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8822B) & \ + BIT_MASK_LDOE25_V12ADJ_L_8822B) +#define BIT_SET_LDOE25_V12ADJ_L_8822B(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L_8822B(x) | BIT_LDOE25_V12ADJ_L_8822B(v)) #define BIT_EF_CRES_SEL_8822B BIT(26) #define BIT_SHIFT_EF_SCAN_START_V1_8822B 16 #define BIT_MASK_EF_SCAN_START_V1_8822B 0x3ff -#define BIT_EF_SCAN_START_V1_8822B(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8822B) << BIT_SHIFT_EF_SCAN_START_V1_8822B) -#define BIT_GET_EF_SCAN_START_V1_8822B(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822B) & BIT_MASK_EF_SCAN_START_V1_8822B) - - +#define BIT_EF_SCAN_START_V1_8822B(x) \ + (((x) & BIT_MASK_EF_SCAN_START_V1_8822B) \ + << BIT_SHIFT_EF_SCAN_START_V1_8822B) +#define BITS_EF_SCAN_START_V1_8822B \ + (BIT_MASK_EF_SCAN_START_V1_8822B << BIT_SHIFT_EF_SCAN_START_V1_8822B) +#define BIT_CLEAR_EF_SCAN_START_V1_8822B(x) \ + ((x) & (~BITS_EF_SCAN_START_V1_8822B)) +#define BIT_GET_EF_SCAN_START_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822B) & \ + BIT_MASK_EF_SCAN_START_V1_8822B) +#define BIT_SET_EF_SCAN_START_V1_8822B(x, v) \ + (BIT_CLEAR_EF_SCAN_START_V1_8822B(x) | BIT_EF_SCAN_START_V1_8822B(v)) #define BIT_SHIFT_EF_SCAN_END_8822B 12 #define BIT_MASK_EF_SCAN_END_8822B 0xf -#define BIT_EF_SCAN_END_8822B(x) (((x) & BIT_MASK_EF_SCAN_END_8822B) << BIT_SHIFT_EF_SCAN_END_8822B) -#define BIT_GET_EF_SCAN_END_8822B(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8822B) & BIT_MASK_EF_SCAN_END_8822B) - +#define BIT_EF_SCAN_END_8822B(x) \ + (((x) & BIT_MASK_EF_SCAN_END_8822B) << BIT_SHIFT_EF_SCAN_END_8822B) +#define BITS_EF_SCAN_END_8822B \ + (BIT_MASK_EF_SCAN_END_8822B << BIT_SHIFT_EF_SCAN_END_8822B) +#define BIT_CLEAR_EF_SCAN_END_8822B(x) ((x) & (~BITS_EF_SCAN_END_8822B)) +#define BIT_GET_EF_SCAN_END_8822B(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_END_8822B) & BIT_MASK_EF_SCAN_END_8822B) +#define BIT_SET_EF_SCAN_END_8822B(x, v) \ + (BIT_CLEAR_EF_SCAN_END_8822B(x) | BIT_EF_SCAN_END_8822B(v)) #define BIT_EF_PD_DIS_8822B BIT(11) #define BIT_SHIFT_EF_CELL_SEL_8822B 8 #define BIT_MASK_EF_CELL_SEL_8822B 0x3 -#define BIT_EF_CELL_SEL_8822B(x) (((x) & BIT_MASK_EF_CELL_SEL_8822B) << BIT_SHIFT_EF_CELL_SEL_8822B) -#define BIT_GET_EF_CELL_SEL_8822B(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8822B) & BIT_MASK_EF_CELL_SEL_8822B) - +#define BIT_EF_CELL_SEL_8822B(x) \ + (((x) & BIT_MASK_EF_CELL_SEL_8822B) << BIT_SHIFT_EF_CELL_SEL_8822B) +#define BITS_EF_CELL_SEL_8822B \ + (BIT_MASK_EF_CELL_SEL_8822B << BIT_SHIFT_EF_CELL_SEL_8822B) +#define BIT_CLEAR_EF_CELL_SEL_8822B(x) ((x) & (~BITS_EF_CELL_SEL_8822B)) +#define BIT_GET_EF_CELL_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_EF_CELL_SEL_8822B) & BIT_MASK_EF_CELL_SEL_8822B) +#define BIT_SET_EF_CELL_SEL_8822B(x, v) \ + (BIT_CLEAR_EF_CELL_SEL_8822B(x) | BIT_EF_CELL_SEL_8822B(v)) #define BIT_EF_TRPT_8822B BIT(7) #define BIT_SHIFT_EF_TTHD_8822B 0 #define BIT_MASK_EF_TTHD_8822B 0x7f -#define BIT_EF_TTHD_8822B(x) (((x) & BIT_MASK_EF_TTHD_8822B) << BIT_SHIFT_EF_TTHD_8822B) -#define BIT_GET_EF_TTHD_8822B(x) (((x) >> BIT_SHIFT_EF_TTHD_8822B) & BIT_MASK_EF_TTHD_8822B) - - +#define BIT_EF_TTHD_8822B(x) \ + (((x) & BIT_MASK_EF_TTHD_8822B) << BIT_SHIFT_EF_TTHD_8822B) +#define BITS_EF_TTHD_8822B (BIT_MASK_EF_TTHD_8822B << BIT_SHIFT_EF_TTHD_8822B) +#define BIT_CLEAR_EF_TTHD_8822B(x) ((x) & (~BITS_EF_TTHD_8822B)) +#define BIT_GET_EF_TTHD_8822B(x) \ + (((x) >> BIT_SHIFT_EF_TTHD_8822B) & BIT_MASK_EF_TTHD_8822B) +#define BIT_SET_EF_TTHD_8822B(x, v) \ + (BIT_CLEAR_EF_TTHD_8822B(x) | BIT_EF_TTHD_8822B(v)) /* 2 REG_PWR_OPTION_CTRL_8822B */ #define BIT_SHIFT_DBG_SEL_V1_8822B 16 #define BIT_MASK_DBG_SEL_V1_8822B 0xff -#define BIT_DBG_SEL_V1_8822B(x) (((x) & BIT_MASK_DBG_SEL_V1_8822B) << BIT_SHIFT_DBG_SEL_V1_8822B) -#define BIT_GET_DBG_SEL_V1_8822B(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8822B) & BIT_MASK_DBG_SEL_V1_8822B) - - +#define BIT_DBG_SEL_V1_8822B(x) \ + (((x) & BIT_MASK_DBG_SEL_V1_8822B) << BIT_SHIFT_DBG_SEL_V1_8822B) +#define BITS_DBG_SEL_V1_8822B \ + (BIT_MASK_DBG_SEL_V1_8822B << BIT_SHIFT_DBG_SEL_V1_8822B) +#define BIT_CLEAR_DBG_SEL_V1_8822B(x) ((x) & (~BITS_DBG_SEL_V1_8822B)) +#define BIT_GET_DBG_SEL_V1_8822B(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_V1_8822B) & BIT_MASK_DBG_SEL_V1_8822B) +#define BIT_SET_DBG_SEL_V1_8822B(x, v) \ + (BIT_CLEAR_DBG_SEL_V1_8822B(x) | BIT_DBG_SEL_V1_8822B(v)) #define BIT_SHIFT_DBG_SEL_BYTE_8822B 14 #define BIT_MASK_DBG_SEL_BYTE_8822B 0x3 -#define BIT_DBG_SEL_BYTE_8822B(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8822B) << BIT_SHIFT_DBG_SEL_BYTE_8822B) -#define BIT_GET_DBG_SEL_BYTE_8822B(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822B) & BIT_MASK_DBG_SEL_BYTE_8822B) - - +#define BIT_DBG_SEL_BYTE_8822B(x) \ + (((x) & BIT_MASK_DBG_SEL_BYTE_8822B) << BIT_SHIFT_DBG_SEL_BYTE_8822B) +#define BITS_DBG_SEL_BYTE_8822B \ + (BIT_MASK_DBG_SEL_BYTE_8822B << BIT_SHIFT_DBG_SEL_BYTE_8822B) +#define BIT_CLEAR_DBG_SEL_BYTE_8822B(x) ((x) & (~BITS_DBG_SEL_BYTE_8822B)) +#define BIT_GET_DBG_SEL_BYTE_8822B(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822B) & BIT_MASK_DBG_SEL_BYTE_8822B) +#define BIT_SET_DBG_SEL_BYTE_8822B(x, v) \ + (BIT_CLEAR_DBG_SEL_BYTE_8822B(x) | BIT_DBG_SEL_BYTE_8822B(v)) #define BIT_SHIFT_STD_L1_V1_8822B 12 #define BIT_MASK_STD_L1_V1_8822B 0x3 -#define BIT_STD_L1_V1_8822B(x) (((x) & BIT_MASK_STD_L1_V1_8822B) << BIT_SHIFT_STD_L1_V1_8822B) -#define BIT_GET_STD_L1_V1_8822B(x) (((x) >> BIT_SHIFT_STD_L1_V1_8822B) & BIT_MASK_STD_L1_V1_8822B) - +#define BIT_STD_L1_V1_8822B(x) \ + (((x) & BIT_MASK_STD_L1_V1_8822B) << BIT_SHIFT_STD_L1_V1_8822B) +#define BITS_STD_L1_V1_8822B \ + (BIT_MASK_STD_L1_V1_8822B << BIT_SHIFT_STD_L1_V1_8822B) +#define BIT_CLEAR_STD_L1_V1_8822B(x) ((x) & (~BITS_STD_L1_V1_8822B)) +#define BIT_GET_STD_L1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_STD_L1_V1_8822B) & BIT_MASK_STD_L1_V1_8822B) +#define BIT_SET_STD_L1_V1_8822B(x, v) \ + (BIT_CLEAR_STD_L1_V1_8822B(x) | BIT_STD_L1_V1_8822B(v)) #define BIT_SYSON_DBG_PAD_E2_8822B BIT(11) #define BIT_SYSON_LED_PAD_E2_8822B BIT(10) @@ -596,56 +864,101 @@ #define BIT_SHIFT_SYSON_SPS0WWV_WT_8822B 4 #define BIT_MASK_SYSON_SPS0WWV_WT_8822B 0x3 -#define BIT_SYSON_SPS0WWV_WT_8822B(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822B) << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) -#define BIT_GET_SYSON_SPS0WWV_WT_8822B(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) & BIT_MASK_SYSON_SPS0WWV_WT_8822B) - - +#define BIT_SYSON_SPS0WWV_WT_8822B(x) \ + (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822B) \ + << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) +#define BITS_SYSON_SPS0WWV_WT_8822B \ + (BIT_MASK_SYSON_SPS0WWV_WT_8822B << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) +#define BIT_CLEAR_SYSON_SPS0WWV_WT_8822B(x) \ + ((x) & (~BITS_SYSON_SPS0WWV_WT_8822B)) +#define BIT_GET_SYSON_SPS0WWV_WT_8822B(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) & \ + BIT_MASK_SYSON_SPS0WWV_WT_8822B) +#define BIT_SET_SYSON_SPS0WWV_WT_8822B(x, v) \ + (BIT_CLEAR_SYSON_SPS0WWV_WT_8822B(x) | BIT_SYSON_SPS0WWV_WT_8822B(v)) #define BIT_SHIFT_SYSON_SPS0LDO_WT_8822B 2 #define BIT_MASK_SYSON_SPS0LDO_WT_8822B 0x3 -#define BIT_SYSON_SPS0LDO_WT_8822B(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822B) << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) -#define BIT_GET_SYSON_SPS0LDO_WT_8822B(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) & BIT_MASK_SYSON_SPS0LDO_WT_8822B) - - +#define BIT_SYSON_SPS0LDO_WT_8822B(x) \ + (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822B) \ + << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) +#define BITS_SYSON_SPS0LDO_WT_8822B \ + (BIT_MASK_SYSON_SPS0LDO_WT_8822B << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) +#define BIT_CLEAR_SYSON_SPS0LDO_WT_8822B(x) \ + ((x) & (~BITS_SYSON_SPS0LDO_WT_8822B)) +#define BIT_GET_SYSON_SPS0LDO_WT_8822B(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) & \ + BIT_MASK_SYSON_SPS0LDO_WT_8822B) +#define BIT_SET_SYSON_SPS0LDO_WT_8822B(x, v) \ + (BIT_CLEAR_SYSON_SPS0LDO_WT_8822B(x) | BIT_SYSON_SPS0LDO_WT_8822B(v)) #define BIT_SHIFT_SYSON_RCLK_SCALE_8822B 0 #define BIT_MASK_SYSON_RCLK_SCALE_8822B 0x3 -#define BIT_SYSON_RCLK_SCALE_8822B(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8822B) << BIT_SHIFT_SYSON_RCLK_SCALE_8822B) -#define BIT_GET_SYSON_RCLK_SCALE_8822B(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822B) & BIT_MASK_SYSON_RCLK_SCALE_8822B) - - +#define BIT_SYSON_RCLK_SCALE_8822B(x) \ + (((x) & BIT_MASK_SYSON_RCLK_SCALE_8822B) \ + << BIT_SHIFT_SYSON_RCLK_SCALE_8822B) +#define BITS_SYSON_RCLK_SCALE_8822B \ + (BIT_MASK_SYSON_RCLK_SCALE_8822B << BIT_SHIFT_SYSON_RCLK_SCALE_8822B) +#define BIT_CLEAR_SYSON_RCLK_SCALE_8822B(x) \ + ((x) & (~BITS_SYSON_RCLK_SCALE_8822B)) +#define BIT_GET_SYSON_RCLK_SCALE_8822B(x) \ + (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822B) & \ + BIT_MASK_SYSON_RCLK_SCALE_8822B) +#define BIT_SET_SYSON_RCLK_SCALE_8822B(x, v) \ + (BIT_CLEAR_SYSON_RCLK_SCALE_8822B(x) | BIT_SYSON_RCLK_SCALE_8822B(v)) /* 2 REG_CAL_TIMER_8822B */ #define BIT_SHIFT_MATCH_CNT_8822B 8 #define BIT_MASK_MATCH_CNT_8822B 0xff -#define BIT_MATCH_CNT_8822B(x) (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B) -#define BIT_GET_MATCH_CNT_8822B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B) - - +#define BIT_MATCH_CNT_8822B(x) \ + (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B) +#define BITS_MATCH_CNT_8822B \ + (BIT_MASK_MATCH_CNT_8822B << BIT_SHIFT_MATCH_CNT_8822B) +#define BIT_CLEAR_MATCH_CNT_8822B(x) ((x) & (~BITS_MATCH_CNT_8822B)) +#define BIT_GET_MATCH_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B) +#define BIT_SET_MATCH_CNT_8822B(x, v) \ + (BIT_CLEAR_MATCH_CNT_8822B(x) | BIT_MATCH_CNT_8822B(v)) #define BIT_SHIFT_CAL_SCAL_8822B 0 #define BIT_MASK_CAL_SCAL_8822B 0xff -#define BIT_CAL_SCAL_8822B(x) (((x) & BIT_MASK_CAL_SCAL_8822B) << BIT_SHIFT_CAL_SCAL_8822B) -#define BIT_GET_CAL_SCAL_8822B(x) (((x) >> BIT_SHIFT_CAL_SCAL_8822B) & BIT_MASK_CAL_SCAL_8822B) - - +#define BIT_CAL_SCAL_8822B(x) \ + (((x) & BIT_MASK_CAL_SCAL_8822B) << BIT_SHIFT_CAL_SCAL_8822B) +#define BITS_CAL_SCAL_8822B \ + (BIT_MASK_CAL_SCAL_8822B << BIT_SHIFT_CAL_SCAL_8822B) +#define BIT_CLEAR_CAL_SCAL_8822B(x) ((x) & (~BITS_CAL_SCAL_8822B)) +#define BIT_GET_CAL_SCAL_8822B(x) \ + (((x) >> BIT_SHIFT_CAL_SCAL_8822B) & BIT_MASK_CAL_SCAL_8822B) +#define BIT_SET_CAL_SCAL_8822B(x, v) \ + (BIT_CLEAR_CAL_SCAL_8822B(x) | BIT_CAL_SCAL_8822B(v)) /* 2 REG_ACLK_MON_8822B */ #define BIT_SHIFT_RCLK_MON_8822B 5 #define BIT_MASK_RCLK_MON_8822B 0x7ff -#define BIT_RCLK_MON_8822B(x) (((x) & BIT_MASK_RCLK_MON_8822B) << BIT_SHIFT_RCLK_MON_8822B) -#define BIT_GET_RCLK_MON_8822B(x) (((x) >> BIT_SHIFT_RCLK_MON_8822B) & BIT_MASK_RCLK_MON_8822B) - +#define BIT_RCLK_MON_8822B(x) \ + (((x) & BIT_MASK_RCLK_MON_8822B) << BIT_SHIFT_RCLK_MON_8822B) +#define BITS_RCLK_MON_8822B \ + (BIT_MASK_RCLK_MON_8822B << BIT_SHIFT_RCLK_MON_8822B) +#define BIT_CLEAR_RCLK_MON_8822B(x) ((x) & (~BITS_RCLK_MON_8822B)) +#define BIT_GET_RCLK_MON_8822B(x) \ + (((x) >> BIT_SHIFT_RCLK_MON_8822B) & BIT_MASK_RCLK_MON_8822B) +#define BIT_SET_RCLK_MON_8822B(x, v) \ + (BIT_CLEAR_RCLK_MON_8822B(x) | BIT_RCLK_MON_8822B(v)) #define BIT_CAL_EN_8822B BIT(4) #define BIT_SHIFT_DPSTU_8822B 2 #define BIT_MASK_DPSTU_8822B 0x3 -#define BIT_DPSTU_8822B(x) (((x) & BIT_MASK_DPSTU_8822B) << BIT_SHIFT_DPSTU_8822B) -#define BIT_GET_DPSTU_8822B(x) (((x) >> BIT_SHIFT_DPSTU_8822B) & BIT_MASK_DPSTU_8822B) - +#define BIT_DPSTU_8822B(x) \ + (((x) & BIT_MASK_DPSTU_8822B) << BIT_SHIFT_DPSTU_8822B) +#define BITS_DPSTU_8822B (BIT_MASK_DPSTU_8822B << BIT_SHIFT_DPSTU_8822B) +#define BIT_CLEAR_DPSTU_8822B(x) ((x) & (~BITS_DPSTU_8822B)) +#define BIT_GET_DPSTU_8822B(x) \ + (((x) >> BIT_SHIFT_DPSTU_8822B) & BIT_MASK_DPSTU_8822B) +#define BIT_SET_DPSTU_8822B(x, v) \ + (BIT_CLEAR_DPSTU_8822B(x) | BIT_DPSTU_8822B(v)) #define BIT_SUS_16X_8822B BIT(1) @@ -663,9 +976,14 @@ #define BIT_SHIFT_BTMODE_8822B 6 #define BIT_MASK_BTMODE_8822B 0x3 -#define BIT_BTMODE_8822B(x) (((x) & BIT_MASK_BTMODE_8822B) << BIT_SHIFT_BTMODE_8822B) -#define BIT_GET_BTMODE_8822B(x) (((x) >> BIT_SHIFT_BTMODE_8822B) & BIT_MASK_BTMODE_8822B) - +#define BIT_BTMODE_8822B(x) \ + (((x) & BIT_MASK_BTMODE_8822B) << BIT_SHIFT_BTMODE_8822B) +#define BITS_BTMODE_8822B (BIT_MASK_BTMODE_8822B << BIT_SHIFT_BTMODE_8822B) +#define BIT_CLEAR_BTMODE_8822B(x) ((x) & (~BITS_BTMODE_8822B)) +#define BIT_GET_BTMODE_8822B(x) \ + (((x) >> BIT_SHIFT_BTMODE_8822B) & BIT_MASK_BTMODE_8822B) +#define BIT_SET_BTMODE_8822B(x, v) \ + (BIT_CLEAR_BTMODE_8822B(x) | BIT_BTMODE_8822B(v)) #define BIT_ENBT_8822B BIT(5) #define BIT_EROM_EN_8822B BIT(4) @@ -674,48 +992,89 @@ #define BIT_SHIFT_GPIOSEL_8822B 0 #define BIT_MASK_GPIOSEL_8822B 0x3 -#define BIT_GPIOSEL_8822B(x) (((x) & BIT_MASK_GPIOSEL_8822B) << BIT_SHIFT_GPIOSEL_8822B) -#define BIT_GET_GPIOSEL_8822B(x) (((x) >> BIT_SHIFT_GPIOSEL_8822B) & BIT_MASK_GPIOSEL_8822B) - - +#define BIT_GPIOSEL_8822B(x) \ + (((x) & BIT_MASK_GPIOSEL_8822B) << BIT_SHIFT_GPIOSEL_8822B) +#define BITS_GPIOSEL_8822B (BIT_MASK_GPIOSEL_8822B << BIT_SHIFT_GPIOSEL_8822B) +#define BIT_CLEAR_GPIOSEL_8822B(x) ((x) & (~BITS_GPIOSEL_8822B)) +#define BIT_GET_GPIOSEL_8822B(x) \ + (((x) >> BIT_SHIFT_GPIOSEL_8822B) & BIT_MASK_GPIOSEL_8822B) +#define BIT_SET_GPIOSEL_8822B(x, v) \ + (BIT_CLEAR_GPIOSEL_8822B(x) | BIT_GPIOSEL_8822B(v)) /* 2 REG_GPIO_PIN_CTRL_8822B */ #define BIT_SHIFT_GPIO_MOD_7_TO_0_8822B 24 #define BIT_MASK_GPIO_MOD_7_TO_0_8822B 0xff -#define BIT_GPIO_MOD_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822B) << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) -#define BIT_GET_GPIO_MOD_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) & BIT_MASK_GPIO_MOD_7_TO_0_8822B) - - +#define BIT_GPIO_MOD_7_TO_0_8822B(x) \ + (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822B) \ + << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) +#define BITS_GPIO_MOD_7_TO_0_8822B \ + (BIT_MASK_GPIO_MOD_7_TO_0_8822B << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) +#define BIT_CLEAR_GPIO_MOD_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8822B)) +#define BIT_GET_GPIO_MOD_7_TO_0_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) & \ + BIT_MASK_GPIO_MOD_7_TO_0_8822B) +#define BIT_SET_GPIO_MOD_7_TO_0_8822B(x, v) \ + (BIT_CLEAR_GPIO_MOD_7_TO_0_8822B(x) | BIT_GPIO_MOD_7_TO_0_8822B(v)) #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B 16 #define BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B 0xff -#define BIT_GPIO_IO_SEL_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) -#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) - - +#define BIT_GPIO_IO_SEL_7_TO_0_8822B(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) +#define BITS_GPIO_IO_SEL_7_TO_0_8822B \ + (BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822B(x) \ + ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8822B)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) & \ + BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) +#define BIT_SET_GPIO_IO_SEL_7_TO_0_8822B(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822B(x) | \ + BIT_GPIO_IO_SEL_7_TO_0_8822B(v)) #define BIT_SHIFT_GPIO_OUT_7_TO_0_8822B 8 #define BIT_MASK_GPIO_OUT_7_TO_0_8822B 0xff -#define BIT_GPIO_OUT_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822B) << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) -#define BIT_GET_GPIO_OUT_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) & BIT_MASK_GPIO_OUT_7_TO_0_8822B) - - +#define BIT_GPIO_OUT_7_TO_0_8822B(x) \ + (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822B) \ + << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) +#define BITS_GPIO_OUT_7_TO_0_8822B \ + (BIT_MASK_GPIO_OUT_7_TO_0_8822B << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) +#define BIT_CLEAR_GPIO_OUT_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8822B)) +#define BIT_GET_GPIO_OUT_7_TO_0_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) & \ + BIT_MASK_GPIO_OUT_7_TO_0_8822B) +#define BIT_SET_GPIO_OUT_7_TO_0_8822B(x, v) \ + (BIT_CLEAR_GPIO_OUT_7_TO_0_8822B(x) | BIT_GPIO_OUT_7_TO_0_8822B(v)) #define BIT_SHIFT_GPIO_IN_7_TO_0_8822B 0 #define BIT_MASK_GPIO_IN_7_TO_0_8822B 0xff -#define BIT_GPIO_IN_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8822B) << BIT_SHIFT_GPIO_IN_7_TO_0_8822B) -#define BIT_GET_GPIO_IN_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822B) & BIT_MASK_GPIO_IN_7_TO_0_8822B) - - +#define BIT_GPIO_IN_7_TO_0_8822B(x) \ + (((x) & BIT_MASK_GPIO_IN_7_TO_0_8822B) \ + << BIT_SHIFT_GPIO_IN_7_TO_0_8822B) +#define BITS_GPIO_IN_7_TO_0_8822B \ + (BIT_MASK_GPIO_IN_7_TO_0_8822B << BIT_SHIFT_GPIO_IN_7_TO_0_8822B) +#define BIT_CLEAR_GPIO_IN_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8822B)) +#define BIT_GET_GPIO_IN_7_TO_0_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822B) & \ + BIT_MASK_GPIO_IN_7_TO_0_8822B) +#define BIT_SET_GPIO_IN_7_TO_0_8822B(x, v) \ + (BIT_CLEAR_GPIO_IN_7_TO_0_8822B(x) | BIT_GPIO_IN_7_TO_0_8822B(v)) /* 2 REG_GPIO_INTM_8822B */ #define BIT_SHIFT_MUXDBG_SEL_8822B 30 #define BIT_MASK_MUXDBG_SEL_8822B 0x3 -#define BIT_MUXDBG_SEL_8822B(x) (((x) & BIT_MASK_MUXDBG_SEL_8822B) << BIT_SHIFT_MUXDBG_SEL_8822B) -#define BIT_GET_MUXDBG_SEL_8822B(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8822B) & BIT_MASK_MUXDBG_SEL_8822B) - +#define BIT_MUXDBG_SEL_8822B(x) \ + (((x) & BIT_MASK_MUXDBG_SEL_8822B) << BIT_SHIFT_MUXDBG_SEL_8822B) +#define BITS_MUXDBG_SEL_8822B \ + (BIT_MASK_MUXDBG_SEL_8822B << BIT_SHIFT_MUXDBG_SEL_8822B) +#define BIT_CLEAR_MUXDBG_SEL_8822B(x) ((x) & (~BITS_MUXDBG_SEL_8822B)) +#define BIT_GET_MUXDBG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL_8822B) & BIT_MASK_MUXDBG_SEL_8822B) +#define BIT_SET_MUXDBG_SEL_8822B(x, v) \ + (BIT_CLEAR_MUXDBG_SEL_8822B(x) | BIT_MUXDBG_SEL_8822B(v)) #define BIT_EXTWOL_SEL_8822B BIT(17) #define BIT_EXTWOL_EN_8822B BIT(16) @@ -753,9 +1112,14 @@ #define BIT_SHIFT_LED2CM_8822B 16 #define BIT_MASK_LED2CM_8822B 0x7 -#define BIT_LED2CM_8822B(x) (((x) & BIT_MASK_LED2CM_8822B) << BIT_SHIFT_LED2CM_8822B) -#define BIT_GET_LED2CM_8822B(x) (((x) >> BIT_SHIFT_LED2CM_8822B) & BIT_MASK_LED2CM_8822B) - +#define BIT_LED2CM_8822B(x) \ + (((x) & BIT_MASK_LED2CM_8822B) << BIT_SHIFT_LED2CM_8822B) +#define BITS_LED2CM_8822B (BIT_MASK_LED2CM_8822B << BIT_SHIFT_LED2CM_8822B) +#define BIT_CLEAR_LED2CM_8822B(x) ((x) & (~BITS_LED2CM_8822B)) +#define BIT_GET_LED2CM_8822B(x) \ + (((x) >> BIT_SHIFT_LED2CM_8822B) & BIT_MASK_LED2CM_8822B) +#define BIT_SET_LED2CM_8822B(x, v) \ + (BIT_CLEAR_LED2CM_8822B(x) | BIT_LED2CM_8822B(v)) #define BIT_LED1DIS_8822B BIT(15) #define BIT_LED1PL_8822B BIT(12) @@ -763,27 +1127,45 @@ #define BIT_SHIFT_LED1CM_8822B 8 #define BIT_MASK_LED1CM_8822B 0x7 -#define BIT_LED1CM_8822B(x) (((x) & BIT_MASK_LED1CM_8822B) << BIT_SHIFT_LED1CM_8822B) -#define BIT_GET_LED1CM_8822B(x) (((x) >> BIT_SHIFT_LED1CM_8822B) & BIT_MASK_LED1CM_8822B) - +#define BIT_LED1CM_8822B(x) \ + (((x) & BIT_MASK_LED1CM_8822B) << BIT_SHIFT_LED1CM_8822B) +#define BITS_LED1CM_8822B (BIT_MASK_LED1CM_8822B << BIT_SHIFT_LED1CM_8822B) +#define BIT_CLEAR_LED1CM_8822B(x) ((x) & (~BITS_LED1CM_8822B)) +#define BIT_GET_LED1CM_8822B(x) \ + (((x) >> BIT_SHIFT_LED1CM_8822B) & BIT_MASK_LED1CM_8822B) +#define BIT_SET_LED1CM_8822B(x, v) \ + (BIT_CLEAR_LED1CM_8822B(x) | BIT_LED1CM_8822B(v)) #define BIT_LED0DIS_8822B BIT(7) #define BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B 5 #define BIT_MASK_AFE_LDO_SWR_CHECK_8822B 0x3 -#define BIT_AFE_LDO_SWR_CHECK_8822B(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) -#define BIT_GET_AFE_LDO_SWR_CHECK_8822B(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B) - +#define BIT_AFE_LDO_SWR_CHECK_8822B(x) \ + (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B) \ + << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) +#define BITS_AFE_LDO_SWR_CHECK_8822B \ + (BIT_MASK_AFE_LDO_SWR_CHECK_8822B << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8822B(x) \ + ((x) & (~BITS_AFE_LDO_SWR_CHECK_8822B)) +#define BIT_GET_AFE_LDO_SWR_CHECK_8822B(x) \ + (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) & \ + BIT_MASK_AFE_LDO_SWR_CHECK_8822B) +#define BIT_SET_AFE_LDO_SWR_CHECK_8822B(x, v) \ + (BIT_CLEAR_AFE_LDO_SWR_CHECK_8822B(x) | BIT_AFE_LDO_SWR_CHECK_8822B(v)) #define BIT_LED0PL_8822B BIT(4) #define BIT_LED0SV_8822B BIT(3) #define BIT_SHIFT_LED0CM_8822B 0 #define BIT_MASK_LED0CM_8822B 0x7 -#define BIT_LED0CM_8822B(x) (((x) & BIT_MASK_LED0CM_8822B) << BIT_SHIFT_LED0CM_8822B) -#define BIT_GET_LED0CM_8822B(x) (((x) >> BIT_SHIFT_LED0CM_8822B) & BIT_MASK_LED0CM_8822B) - - +#define BIT_LED0CM_8822B(x) \ + (((x) & BIT_MASK_LED0CM_8822B) << BIT_SHIFT_LED0CM_8822B) +#define BITS_LED0CM_8822B (BIT_MASK_LED0CM_8822B << BIT_SHIFT_LED0CM_8822B) +#define BIT_CLEAR_LED0CM_8822B(x) ((x) & (~BITS_LED0CM_8822B)) +#define BIT_GET_LED0CM_8822B(x) \ + (((x) >> BIT_SHIFT_LED0CM_8822B) & BIT_MASK_LED0CM_8822B) +#define BIT_SET_LED0CM_8822B(x, v) \ + (BIT_CLEAR_LED0CM_8822B(x) | BIT_LED0CM_8822B(v)) /* 2 REG_FSIMR_8822B */ #define BIT_FS_PDNINT_EN_8822B BIT(31) @@ -863,7 +1245,7 @@ #define BIT_GPIO5_INT_EN_8822B BIT(21) #define BIT_GPIO4_INT_EN_8822B BIT(20) #define BIT_GPIO3_INT_EN_8822B BIT(19) -#define BIT_GPIO2_INT_EN_V1_8822B BIT(16) +#define BIT_GPIO2_INT_EN_V1_8822B BIT(18) #define BIT_GPIO1_INT_EN_8822B BIT(17) #define BIT_GPIO0_INT_EN_8822B BIT(16) #define BIT_PDNINT_EN_8822B BIT(7) @@ -885,7 +1267,7 @@ #define BIT_GPIO5_INT_8822B BIT(21) #define BIT_GPIO4_INT_8822B BIT(20) #define BIT_GPIO3_INT_8822B BIT(19) -#define BIT_GPIO2_INT_V1_8822B BIT(16) +#define BIT_GPIO2_INT_V1_8822B BIT(18) #define BIT_GPIO1_INT_8822B BIT(17) #define BIT_GPIO0_INT_8822B BIT(16) #define BIT_PDNINT_8822B BIT(7) @@ -897,31 +1279,64 @@ #define BIT_SHIFT_GPIO_MOD_15_TO_8_8822B 24 #define BIT_MASK_GPIO_MOD_15_TO_8_8822B 0xff -#define BIT_GPIO_MOD_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822B) << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) -#define BIT_GET_GPIO_MOD_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) & BIT_MASK_GPIO_MOD_15_TO_8_8822B) - - +#define BIT_GPIO_MOD_15_TO_8_8822B(x) \ + (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822B) \ + << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) +#define BITS_GPIO_MOD_15_TO_8_8822B \ + (BIT_MASK_GPIO_MOD_15_TO_8_8822B << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) +#define BIT_CLEAR_GPIO_MOD_15_TO_8_8822B(x) \ + ((x) & (~BITS_GPIO_MOD_15_TO_8_8822B)) +#define BIT_GET_GPIO_MOD_15_TO_8_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) & \ + BIT_MASK_GPIO_MOD_15_TO_8_8822B) +#define BIT_SET_GPIO_MOD_15_TO_8_8822B(x, v) \ + (BIT_CLEAR_GPIO_MOD_15_TO_8_8822B(x) | BIT_GPIO_MOD_15_TO_8_8822B(v)) #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B 16 #define BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B 0xff -#define BIT_GPIO_IO_SEL_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) -#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) - - +#define BIT_GPIO_IO_SEL_15_TO_8_8822B(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) +#define BITS_GPIO_IO_SEL_15_TO_8_8822B \ + (BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822B(x) \ + ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8822B)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) & \ + BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) +#define BIT_SET_GPIO_IO_SEL_15_TO_8_8822B(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822B(x) | \ + BIT_GPIO_IO_SEL_15_TO_8_8822B(v)) #define BIT_SHIFT_GPIO_OUT_15_TO_8_8822B 8 #define BIT_MASK_GPIO_OUT_15_TO_8_8822B 0xff -#define BIT_GPIO_OUT_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822B) << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) -#define BIT_GET_GPIO_OUT_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) & BIT_MASK_GPIO_OUT_15_TO_8_8822B) - - +#define BIT_GPIO_OUT_15_TO_8_8822B(x) \ + (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822B) \ + << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) +#define BITS_GPIO_OUT_15_TO_8_8822B \ + (BIT_MASK_GPIO_OUT_15_TO_8_8822B << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) +#define BIT_CLEAR_GPIO_OUT_15_TO_8_8822B(x) \ + ((x) & (~BITS_GPIO_OUT_15_TO_8_8822B)) +#define BIT_GET_GPIO_OUT_15_TO_8_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) & \ + BIT_MASK_GPIO_OUT_15_TO_8_8822B) +#define BIT_SET_GPIO_OUT_15_TO_8_8822B(x, v) \ + (BIT_CLEAR_GPIO_OUT_15_TO_8_8822B(x) | BIT_GPIO_OUT_15_TO_8_8822B(v)) #define BIT_SHIFT_GPIO_IN_15_TO_8_8822B 0 #define BIT_MASK_GPIO_IN_15_TO_8_8822B 0xff -#define BIT_GPIO_IN_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8822B) << BIT_SHIFT_GPIO_IN_15_TO_8_8822B) -#define BIT_GET_GPIO_IN_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822B) & BIT_MASK_GPIO_IN_15_TO_8_8822B) - - +#define BIT_GPIO_IN_15_TO_8_8822B(x) \ + (((x) & BIT_MASK_GPIO_IN_15_TO_8_8822B) \ + << BIT_SHIFT_GPIO_IN_15_TO_8_8822B) +#define BITS_GPIO_IN_15_TO_8_8822B \ + (BIT_MASK_GPIO_IN_15_TO_8_8822B << BIT_SHIFT_GPIO_IN_15_TO_8_8822B) +#define BIT_CLEAR_GPIO_IN_15_TO_8_8822B(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8822B)) +#define BIT_GET_GPIO_IN_15_TO_8_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822B) & \ + BIT_MASK_GPIO_IN_15_TO_8_8822B) +#define BIT_SET_GPIO_IN_15_TO_8_8822B(x, v) \ + (BIT_CLEAR_GPIO_IN_15_TO_8_8822B(x) | BIT_GPIO_IN_15_TO_8_8822B(v)) /* 2 REG_PAD_CTRL1_8822B */ #define BIT_PAPE_WLBT_SEL_8822B BIT(29) @@ -938,9 +1353,15 @@ #define BIT_SHIFT_BTGP_GPIO_SL_8822B 16 #define BIT_MASK_BTGP_GPIO_SL_8822B 0x3 -#define BIT_BTGP_GPIO_SL_8822B(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8822B) << BIT_SHIFT_BTGP_GPIO_SL_8822B) -#define BIT_GET_BTGP_GPIO_SL_8822B(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822B) & BIT_MASK_BTGP_GPIO_SL_8822B) - +#define BIT_BTGP_GPIO_SL_8822B(x) \ + (((x) & BIT_MASK_BTGP_GPIO_SL_8822B) << BIT_SHIFT_BTGP_GPIO_SL_8822B) +#define BITS_BTGP_GPIO_SL_8822B \ + (BIT_MASK_BTGP_GPIO_SL_8822B << BIT_SHIFT_BTGP_GPIO_SL_8822B) +#define BIT_CLEAR_BTGP_GPIO_SL_8822B(x) ((x) & (~BITS_BTGP_GPIO_SL_8822B)) +#define BIT_GET_BTGP_GPIO_SL_8822B(x) \ + (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822B) & BIT_MASK_BTGP_GPIO_SL_8822B) +#define BIT_SET_BTGP_GPIO_SL_8822B(x, v) \ + (BIT_CLEAR_BTGP_GPIO_SL_8822B(x) | BIT_BTGP_GPIO_SL_8822B(v)) #define BIT_PAD_SDIO_SR_8822B BIT(14) #define BIT_GPIO14_OUTPUT_PL_8822B BIT(13) @@ -991,10 +1412,15 @@ #define BIT_SHIFT_WLCLK_PHASE_8822B 0 #define BIT_MASK_WLCLK_PHASE_8822B 0x1f -#define BIT_WLCLK_PHASE_8822B(x) (((x) & BIT_MASK_WLCLK_PHASE_8822B) << BIT_SHIFT_WLCLK_PHASE_8822B) -#define BIT_GET_WLCLK_PHASE_8822B(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8822B) & BIT_MASK_WLCLK_PHASE_8822B) - - +#define BIT_WLCLK_PHASE_8822B(x) \ + (((x) & BIT_MASK_WLCLK_PHASE_8822B) << BIT_SHIFT_WLCLK_PHASE_8822B) +#define BITS_WLCLK_PHASE_8822B \ + (BIT_MASK_WLCLK_PHASE_8822B << BIT_SHIFT_WLCLK_PHASE_8822B) +#define BIT_CLEAR_WLCLK_PHASE_8822B(x) ((x) & (~BITS_WLCLK_PHASE_8822B)) +#define BIT_GET_WLCLK_PHASE_8822B(x) \ + (((x) >> BIT_SHIFT_WLCLK_PHASE_8822B) & BIT_MASK_WLCLK_PHASE_8822B) +#define BIT_SET_WLCLK_PHASE_8822B(x, v) \ + (BIT_CLEAR_WLCLK_PHASE_8822B(x) | BIT_WLCLK_PHASE_8822B(v)) /* 2 REG_SYS_SDIO_CTRL_8822B */ #define BIT_DBG_GNT_WL_BT_8822B BIT(27) @@ -1009,13 +1435,34 @@ #define BIT_PCIE_WAIT_TIME_8822B BIT(9) #define BIT_MPCIE_REFCLK_XTAL_SEL_8822B BIT(8) +#define BIT_SHIFT_SI_AUTHORIZATION_8822B 0 +#define BIT_MASK_SI_AUTHORIZATION_8822B 0xff +#define BIT_SI_AUTHORIZATION_8822B(x) \ + (((x) & BIT_MASK_SI_AUTHORIZATION_8822B) \ + << BIT_SHIFT_SI_AUTHORIZATION_8822B) +#define BITS_SI_AUTHORIZATION_8822B \ + (BIT_MASK_SI_AUTHORIZATION_8822B << BIT_SHIFT_SI_AUTHORIZATION_8822B) +#define BIT_CLEAR_SI_AUTHORIZATION_8822B(x) \ + ((x) & (~BITS_SI_AUTHORIZATION_8822B)) +#define BIT_GET_SI_AUTHORIZATION_8822B(x) \ + (((x) >> BIT_SHIFT_SI_AUTHORIZATION_8822B) & \ + BIT_MASK_SI_AUTHORIZATION_8822B) +#define BIT_SET_SI_AUTHORIZATION_8822B(x, v) \ + (BIT_CLEAR_SI_AUTHORIZATION_8822B(x) | BIT_SI_AUTHORIZATION_8822B(v)) + /* 2 REG_HCI_OPT_CTRL_8822B */ #define BIT_SHIFT_TSFT_SEL_8822B 29 #define BIT_MASK_TSFT_SEL_8822B 0x7 -#define BIT_TSFT_SEL_8822B(x) (((x) & BIT_MASK_TSFT_SEL_8822B) << BIT_SHIFT_TSFT_SEL_8822B) -#define BIT_GET_TSFT_SEL_8822B(x) (((x) >> BIT_SHIFT_TSFT_SEL_8822B) & BIT_MASK_TSFT_SEL_8822B) - +#define BIT_TSFT_SEL_8822B(x) \ + (((x) & BIT_MASK_TSFT_SEL_8822B) << BIT_SHIFT_TSFT_SEL_8822B) +#define BITS_TSFT_SEL_8822B \ + (BIT_MASK_TSFT_SEL_8822B << BIT_SHIFT_TSFT_SEL_8822B) +#define BIT_CLEAR_TSFT_SEL_8822B(x) ((x) & (~BITS_TSFT_SEL_8822B)) +#define BIT_GET_TSFT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_8822B) & BIT_MASK_TSFT_SEL_8822B) +#define BIT_SET_TSFT_SEL_8822B(x, v) \ + (BIT_CLEAR_TSFT_SEL_8822B(x) | BIT_TSFT_SEL_8822B(v)) #define BIT_USB_HOST_PWR_OFF_EN_8822B BIT(12) #define BIT_SYM_LPS_BLOCK_EN_8822B BIT(11) @@ -1025,9 +1472,15 @@ #define BIT_SHIFT_SDIO_PAD_E_8822B 5 #define BIT_MASK_SDIO_PAD_E_8822B 0x7 -#define BIT_SDIO_PAD_E_8822B(x) (((x) & BIT_MASK_SDIO_PAD_E_8822B) << BIT_SHIFT_SDIO_PAD_E_8822B) -#define BIT_GET_SDIO_PAD_E_8822B(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8822B) & BIT_MASK_SDIO_PAD_E_8822B) - +#define BIT_SDIO_PAD_E_8822B(x) \ + (((x) & BIT_MASK_SDIO_PAD_E_8822B) << BIT_SHIFT_SDIO_PAD_E_8822B) +#define BITS_SDIO_PAD_E_8822B \ + (BIT_MASK_SDIO_PAD_E_8822B << BIT_SHIFT_SDIO_PAD_E_8822B) +#define BIT_CLEAR_SDIO_PAD_E_8822B(x) ((x) & (~BITS_SDIO_PAD_E_8822B)) +#define BIT_GET_SDIO_PAD_E_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_PAD_E_8822B) & BIT_MASK_SDIO_PAD_E_8822B) +#define BIT_SET_SDIO_PAD_E_8822B(x, v) \ + (BIT_CLEAR_SDIO_PAD_E_8822B(x) | BIT_SDIO_PAD_E_8822B(v)) #define BIT_USB_LPPLL_EN_8822B BIT(4) #define BIT_ROP_SW15_8822B BIT(2) @@ -1042,44 +1495,93 @@ #define BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B 21 #define BIT_MASK_AUTO_ZCD_IN_CODE_8822B 0x1f -#define BIT_AUTO_ZCD_IN_CODE_8822B(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B) << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) -#define BIT_GET_AUTO_ZCD_IN_CODE_8822B(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B) - - +#define BIT_AUTO_ZCD_IN_CODE_8822B(x) \ + (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B) \ + << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) +#define BITS_AUTO_ZCD_IN_CODE_8822B \ + (BIT_MASK_AUTO_ZCD_IN_CODE_8822B << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) +#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8822B(x) \ + ((x) & (~BITS_AUTO_ZCD_IN_CODE_8822B)) +#define BIT_GET_AUTO_ZCD_IN_CODE_8822B(x) \ + (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) & \ + BIT_MASK_AUTO_ZCD_IN_CODE_8822B) +#define BIT_SET_AUTO_ZCD_IN_CODE_8822B(x, v) \ + (BIT_CLEAR_AUTO_ZCD_IN_CODE_8822B(x) | BIT_AUTO_ZCD_IN_CODE_8822B(v)) #define BIT_SHIFT_ZCD_CODE_IN_L_8822B 16 #define BIT_MASK_ZCD_CODE_IN_L_8822B 0x1f -#define BIT_ZCD_CODE_IN_L_8822B(x) (((x) & BIT_MASK_ZCD_CODE_IN_L_8822B) << BIT_SHIFT_ZCD_CODE_IN_L_8822B) -#define BIT_GET_ZCD_CODE_IN_L_8822B(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822B) & BIT_MASK_ZCD_CODE_IN_L_8822B) - - +#define BIT_ZCD_CODE_IN_L_8822B(x) \ + (((x) & BIT_MASK_ZCD_CODE_IN_L_8822B) << BIT_SHIFT_ZCD_CODE_IN_L_8822B) +#define BITS_ZCD_CODE_IN_L_8822B \ + (BIT_MASK_ZCD_CODE_IN_L_8822B << BIT_SHIFT_ZCD_CODE_IN_L_8822B) +#define BIT_CLEAR_ZCD_CODE_IN_L_8822B(x) ((x) & (~BITS_ZCD_CODE_IN_L_8822B)) +#define BIT_GET_ZCD_CODE_IN_L_8822B(x) \ + (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822B) & BIT_MASK_ZCD_CODE_IN_L_8822B) +#define BIT_SET_ZCD_CODE_IN_L_8822B(x, v) \ + (BIT_CLEAR_ZCD_CODE_IN_L_8822B(x) | BIT_ZCD_CODE_IN_L_8822B(v)) #define BIT_SHIFT_LDO_HV5_DUMMY_8822B 14 #define BIT_MASK_LDO_HV5_DUMMY_8822B 0x3 -#define BIT_LDO_HV5_DUMMY_8822B(x) (((x) & BIT_MASK_LDO_HV5_DUMMY_8822B) << BIT_SHIFT_LDO_HV5_DUMMY_8822B) -#define BIT_GET_LDO_HV5_DUMMY_8822B(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8822B) & BIT_MASK_LDO_HV5_DUMMY_8822B) - - +#define BIT_LDO_HV5_DUMMY_8822B(x) \ + (((x) & BIT_MASK_LDO_HV5_DUMMY_8822B) << BIT_SHIFT_LDO_HV5_DUMMY_8822B) +#define BITS_LDO_HV5_DUMMY_8822B \ + (BIT_MASK_LDO_HV5_DUMMY_8822B << BIT_SHIFT_LDO_HV5_DUMMY_8822B) +#define BIT_CLEAR_LDO_HV5_DUMMY_8822B(x) ((x) & (~BITS_LDO_HV5_DUMMY_8822B)) +#define BIT_GET_LDO_HV5_DUMMY_8822B(x) \ + (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8822B) & BIT_MASK_LDO_HV5_DUMMY_8822B) +#define BIT_SET_LDO_HV5_DUMMY_8822B(x, v) \ + (BIT_CLEAR_LDO_HV5_DUMMY_8822B(x) | BIT_LDO_HV5_DUMMY_8822B(v)) #define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B 12 #define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B 0x3 -#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) -#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) - - +#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) \ + (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) \ + << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) +#define BITS_REG_VTUNE33_BIT0_TO_BIT1_8822B \ + (BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B \ + << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) +#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) \ + ((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1_8822B)) +#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) \ + (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) & \ + BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) +#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x, v) \ + (BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) | \ + BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(v)) #define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B 10 #define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B 0x3 -#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) -#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) - - +#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) \ + (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) \ + << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) +#define BITS_REG_STANDBY33_BIT0_TO_BIT1_8822B \ + (BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B \ + << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) +#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) \ + ((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1_8822B)) +#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) \ + (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) & \ + BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) +#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x, v) \ + (BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) | \ + BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(v)) #define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B 8 #define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B 0x3 -#define BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) -#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8822B(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) - +#define BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(x) \ + (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) \ + << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) +#define BITS_REG_LOAD33_BIT0_TO_BIT1_8822B \ + (BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B \ + << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) +#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8822B(x) \ + ((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1_8822B)) +#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8822B(x) \ + (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) & \ + BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) +#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1_8822B(x, v) \ + (BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8822B(x) | \ + BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(v)) #define BIT_REG_BYPASS_L_8822B BIT(7) #define BIT_REG_LDOF_L_8822B BIT(6) @@ -1088,9 +1590,14 @@ #define BIT_SHIFT_CFC_L_8822B 1 #define BIT_MASK_CFC_L_8822B 0x3 -#define BIT_CFC_L_8822B(x) (((x) & BIT_MASK_CFC_L_8822B) << BIT_SHIFT_CFC_L_8822B) -#define BIT_GET_CFC_L_8822B(x) (((x) >> BIT_SHIFT_CFC_L_8822B) & BIT_MASK_CFC_L_8822B) - +#define BIT_CFC_L_8822B(x) \ + (((x) & BIT_MASK_CFC_L_8822B) << BIT_SHIFT_CFC_L_8822B) +#define BITS_CFC_L_8822B (BIT_MASK_CFC_L_8822B << BIT_SHIFT_CFC_L_8822B) +#define BIT_CLEAR_CFC_L_8822B(x) ((x) & (~BITS_CFC_L_8822B)) +#define BIT_GET_CFC_L_8822B(x) \ + (((x) >> BIT_SHIFT_CFC_L_8822B) & BIT_MASK_CFC_L_8822B) +#define BIT_SET_CFC_L_8822B(x, v) \ + (BIT_CLEAR_CFC_L_8822B(x) | BIT_CFC_L_8822B(v)) #define BIT_REG_OCPS_L_V1_8822B BIT(0) @@ -1099,8 +1606,11 @@ #define BIT_SHIFT_RPWM_8822B 24 #define BIT_MASK_RPWM_8822B 0xff #define BIT_RPWM_8822B(x) (((x) & BIT_MASK_RPWM_8822B) << BIT_SHIFT_RPWM_8822B) -#define BIT_GET_RPWM_8822B(x) (((x) >> BIT_SHIFT_RPWM_8822B) & BIT_MASK_RPWM_8822B) - +#define BITS_RPWM_8822B (BIT_MASK_RPWM_8822B << BIT_SHIFT_RPWM_8822B) +#define BIT_CLEAR_RPWM_8822B(x) ((x) & (~BITS_RPWM_8822B)) +#define BIT_GET_RPWM_8822B(x) \ + (((x) >> BIT_SHIFT_RPWM_8822B) & BIT_MASK_RPWM_8822B) +#define BIT_SET_RPWM_8822B(x, v) (BIT_CLEAR_RPWM_8822B(x) | BIT_RPWM_8822B(v)) #define BIT_ANA_PORT_EN_8822B BIT(22) #define BIT_MAC_PORT_EN_8822B BIT(21) @@ -1109,18 +1619,29 @@ #define BIT_SHIFT_ROM_PGE_8822B 16 #define BIT_MASK_ROM_PGE_8822B 0x7 -#define BIT_ROM_PGE_8822B(x) (((x) & BIT_MASK_ROM_PGE_8822B) << BIT_SHIFT_ROM_PGE_8822B) -#define BIT_GET_ROM_PGE_8822B(x) (((x) >> BIT_SHIFT_ROM_PGE_8822B) & BIT_MASK_ROM_PGE_8822B) - +#define BIT_ROM_PGE_8822B(x) \ + (((x) & BIT_MASK_ROM_PGE_8822B) << BIT_SHIFT_ROM_PGE_8822B) +#define BITS_ROM_PGE_8822B (BIT_MASK_ROM_PGE_8822B << BIT_SHIFT_ROM_PGE_8822B) +#define BIT_CLEAR_ROM_PGE_8822B(x) ((x) & (~BITS_ROM_PGE_8822B)) +#define BIT_GET_ROM_PGE_8822B(x) \ + (((x) >> BIT_SHIFT_ROM_PGE_8822B) & BIT_MASK_ROM_PGE_8822B) +#define BIT_SET_ROM_PGE_8822B(x, v) \ + (BIT_CLEAR_ROM_PGE_8822B(x) | BIT_ROM_PGE_8822B(v)) #define BIT_FW_INIT_RDY_8822B BIT(15) #define BIT_FW_DW_RDY_8822B BIT(14) #define BIT_SHIFT_CPU_CLK_SEL_8822B 12 #define BIT_MASK_CPU_CLK_SEL_8822B 0x3 -#define BIT_CPU_CLK_SEL_8822B(x) (((x) & BIT_MASK_CPU_CLK_SEL_8822B) << BIT_SHIFT_CPU_CLK_SEL_8822B) -#define BIT_GET_CPU_CLK_SEL_8822B(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8822B) & BIT_MASK_CPU_CLK_SEL_8822B) - +#define BIT_CPU_CLK_SEL_8822B(x) \ + (((x) & BIT_MASK_CPU_CLK_SEL_8822B) << BIT_SHIFT_CPU_CLK_SEL_8822B) +#define BITS_CPU_CLK_SEL_8822B \ + (BIT_MASK_CPU_CLK_SEL_8822B << BIT_SHIFT_CPU_CLK_SEL_8822B) +#define BIT_CLEAR_CPU_CLK_SEL_8822B(x) ((x) & (~BITS_CPU_CLK_SEL_8822B)) +#define BIT_GET_CPU_CLK_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_CPU_CLK_SEL_8822B) & BIT_MASK_CPU_CLK_SEL_8822B) +#define BIT_SET_CPU_CLK_SEL_8822B(x, v) \ + (BIT_CLEAR_CPU_CLK_SEL_8822B(x) | BIT_CPU_CLK_SEL_8822B(v)) #define BIT_CCLK_CHG_MASK_8822B BIT(11) #define BIT_EMEM__TXBUF_CHKSUM_OK_8822B BIT(10) @@ -1137,44 +1658,68 @@ /* 2 REG_MCU_TST_CFG_8822B */ -#define BIT_SHIFT_LBKTST_8822B 0 -#define BIT_MASK_LBKTST_8822B 0xffff -#define BIT_LBKTST_8822B(x) (((x) & BIT_MASK_LBKTST_8822B) << BIT_SHIFT_LBKTST_8822B) -#define BIT_GET_LBKTST_8822B(x) (((x) >> BIT_SHIFT_LBKTST_8822B) & BIT_MASK_LBKTST_8822B) - - +#define BIT_SHIFT_C2H_MSG_8822B 0 +#define BIT_MASK_C2H_MSG_8822B 0xffff +#define BIT_C2H_MSG_8822B(x) \ + (((x) & BIT_MASK_C2H_MSG_8822B) << BIT_SHIFT_C2H_MSG_8822B) +#define BITS_C2H_MSG_8822B (BIT_MASK_C2H_MSG_8822B << BIT_SHIFT_C2H_MSG_8822B) +#define BIT_CLEAR_C2H_MSG_8822B(x) ((x) & (~BITS_C2H_MSG_8822B)) +#define BIT_GET_C2H_MSG_8822B(x) \ + (((x) >> BIT_SHIFT_C2H_MSG_8822B) & BIT_MASK_C2H_MSG_8822B) +#define BIT_SET_C2H_MSG_8822B(x, v) \ + (BIT_CLEAR_C2H_MSG_8822B(x) | BIT_C2H_MSG_8822B(v)) /* 2 REG_HMEBOX_E0_E1_8822B */ #define BIT_SHIFT_HOST_MSG_E1_8822B 16 #define BIT_MASK_HOST_MSG_E1_8822B 0xffff -#define BIT_HOST_MSG_E1_8822B(x) (((x) & BIT_MASK_HOST_MSG_E1_8822B) << BIT_SHIFT_HOST_MSG_E1_8822B) -#define BIT_GET_HOST_MSG_E1_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8822B) & BIT_MASK_HOST_MSG_E1_8822B) - - +#define BIT_HOST_MSG_E1_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_E1_8822B) << BIT_SHIFT_HOST_MSG_E1_8822B) +#define BITS_HOST_MSG_E1_8822B \ + (BIT_MASK_HOST_MSG_E1_8822B << BIT_SHIFT_HOST_MSG_E1_8822B) +#define BIT_CLEAR_HOST_MSG_E1_8822B(x) ((x) & (~BITS_HOST_MSG_E1_8822B)) +#define BIT_GET_HOST_MSG_E1_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E1_8822B) & BIT_MASK_HOST_MSG_E1_8822B) +#define BIT_SET_HOST_MSG_E1_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_E1_8822B(x) | BIT_HOST_MSG_E1_8822B(v)) #define BIT_SHIFT_HOST_MSG_E0_8822B 0 #define BIT_MASK_HOST_MSG_E0_8822B 0xffff -#define BIT_HOST_MSG_E0_8822B(x) (((x) & BIT_MASK_HOST_MSG_E0_8822B) << BIT_SHIFT_HOST_MSG_E0_8822B) -#define BIT_GET_HOST_MSG_E0_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8822B) & BIT_MASK_HOST_MSG_E0_8822B) - - +#define BIT_HOST_MSG_E0_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_E0_8822B) << BIT_SHIFT_HOST_MSG_E0_8822B) +#define BITS_HOST_MSG_E0_8822B \ + (BIT_MASK_HOST_MSG_E0_8822B << BIT_SHIFT_HOST_MSG_E0_8822B) +#define BIT_CLEAR_HOST_MSG_E0_8822B(x) ((x) & (~BITS_HOST_MSG_E0_8822B)) +#define BIT_GET_HOST_MSG_E0_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E0_8822B) & BIT_MASK_HOST_MSG_E0_8822B) +#define BIT_SET_HOST_MSG_E0_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_E0_8822B(x) | BIT_HOST_MSG_E0_8822B(v)) /* 2 REG_HMEBOX_E2_E3_8822B */ #define BIT_SHIFT_HOST_MSG_E3_8822B 16 #define BIT_MASK_HOST_MSG_E3_8822B 0xffff -#define BIT_HOST_MSG_E3_8822B(x) (((x) & BIT_MASK_HOST_MSG_E3_8822B) << BIT_SHIFT_HOST_MSG_E3_8822B) -#define BIT_GET_HOST_MSG_E3_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8822B) & BIT_MASK_HOST_MSG_E3_8822B) - - +#define BIT_HOST_MSG_E3_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_E3_8822B) << BIT_SHIFT_HOST_MSG_E3_8822B) +#define BITS_HOST_MSG_E3_8822B \ + (BIT_MASK_HOST_MSG_E3_8822B << BIT_SHIFT_HOST_MSG_E3_8822B) +#define BIT_CLEAR_HOST_MSG_E3_8822B(x) ((x) & (~BITS_HOST_MSG_E3_8822B)) +#define BIT_GET_HOST_MSG_E3_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E3_8822B) & BIT_MASK_HOST_MSG_E3_8822B) +#define BIT_SET_HOST_MSG_E3_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_E3_8822B(x) | BIT_HOST_MSG_E3_8822B(v)) #define BIT_SHIFT_HOST_MSG_E2_8822B 0 #define BIT_MASK_HOST_MSG_E2_8822B 0xffff -#define BIT_HOST_MSG_E2_8822B(x) (((x) & BIT_MASK_HOST_MSG_E2_8822B) << BIT_SHIFT_HOST_MSG_E2_8822B) -#define BIT_GET_HOST_MSG_E2_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8822B) & BIT_MASK_HOST_MSG_E2_8822B) - - +#define BIT_HOST_MSG_E2_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_E2_8822B) << BIT_SHIFT_HOST_MSG_E2_8822B) +#define BITS_HOST_MSG_E2_8822B \ + (BIT_MASK_HOST_MSG_E2_8822B << BIT_SHIFT_HOST_MSG_E2_8822B) +#define BIT_CLEAR_HOST_MSG_E2_8822B(x) ((x) & (~BITS_HOST_MSG_E2_8822B)) +#define BIT_GET_HOST_MSG_E2_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E2_8822B) & BIT_MASK_HOST_MSG_E2_8822B) +#define BIT_SET_HOST_MSG_E2_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_E2_8822B(x) | BIT_HOST_MSG_E2_8822B(v)) /* 2 REG_WLLPS_CTRL_8822B */ #define BIT_WLLPSOP_EABM_8822B BIT(31) @@ -1191,16 +1736,35 @@ #define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B 12 #define BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B 0xf -#define BIT_LPLDH12_VADJ_STEP_DN_8822B(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) -#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B) - - +#define BIT_LPLDH12_VADJ_STEP_DN_8822B(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B) \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) +#define BITS_LPLDH12_VADJ_STEP_DN_8822B \ + (BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) +#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822B(x) \ + ((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8822B)) +#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822B(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) & \ + BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B) +#define BIT_SET_LPLDH12_VADJ_STEP_DN_8822B(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822B(x) | \ + BIT_LPLDH12_VADJ_STEP_DN_8822B(v)) #define BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B 8 #define BIT_MASK_V15ADJ_L1_STEP_DN_8822B 0x7 -#define BIT_V15ADJ_L1_STEP_DN_8822B(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B) << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) -#define BIT_GET_V15ADJ_L1_STEP_DN_8822B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B) - +#define BIT_V15ADJ_L1_STEP_DN_8822B(x) \ + (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B) \ + << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) +#define BITS_V15ADJ_L1_STEP_DN_8822B \ + (BIT_MASK_V15ADJ_L1_STEP_DN_8822B << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) +#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8822B(x) \ + ((x) & (~BITS_V15ADJ_L1_STEP_DN_8822B)) +#define BIT_GET_V15ADJ_L1_STEP_DN_8822B(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) & \ + BIT_MASK_V15ADJ_L1_STEP_DN_8822B) +#define BIT_SET_V15ADJ_L1_STEP_DN_8822B(x, v) \ + (BIT_CLEAR_V15ADJ_L1_STEP_DN_8822B(x) | BIT_V15ADJ_L1_STEP_DN_8822B(v)) #define BIT_REGU_32K_CLK_EN_8822B BIT(1) #define BIT_WL_LPS_EN_8822B BIT(0) @@ -1212,119 +1776,198 @@ #define BIT_SHIFT_REF_SEL_8822B 25 #define BIT_MASK_REF_SEL_8822B 0xf -#define BIT_REF_SEL_8822B(x) (((x) & BIT_MASK_REF_SEL_8822B) << BIT_SHIFT_REF_SEL_8822B) -#define BIT_GET_REF_SEL_8822B(x) (((x) >> BIT_SHIFT_REF_SEL_8822B) & BIT_MASK_REF_SEL_8822B) - - +#define BIT_REF_SEL_8822B(x) \ + (((x) & BIT_MASK_REF_SEL_8822B) << BIT_SHIFT_REF_SEL_8822B) +#define BITS_REF_SEL_8822B (BIT_MASK_REF_SEL_8822B << BIT_SHIFT_REF_SEL_8822B) +#define BIT_CLEAR_REF_SEL_8822B(x) ((x) & (~BITS_REF_SEL_8822B)) +#define BIT_GET_REF_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_REF_SEL_8822B) & BIT_MASK_REF_SEL_8822B) +#define BIT_SET_REF_SEL_8822B(x, v) \ + (BIT_CLEAR_REF_SEL_8822B(x) | BIT_REF_SEL_8822B(v)) #define BIT_SHIFT_F0F_SDM_8822B 12 #define BIT_MASK_F0F_SDM_8822B 0x1fff -#define BIT_F0F_SDM_8822B(x) (((x) & BIT_MASK_F0F_SDM_8822B) << BIT_SHIFT_F0F_SDM_8822B) -#define BIT_GET_F0F_SDM_8822B(x) (((x) >> BIT_SHIFT_F0F_SDM_8822B) & BIT_MASK_F0F_SDM_8822B) - - +#define BIT_F0F_SDM_8822B(x) \ + (((x) & BIT_MASK_F0F_SDM_8822B) << BIT_SHIFT_F0F_SDM_8822B) +#define BITS_F0F_SDM_8822B (BIT_MASK_F0F_SDM_8822B << BIT_SHIFT_F0F_SDM_8822B) +#define BIT_CLEAR_F0F_SDM_8822B(x) ((x) & (~BITS_F0F_SDM_8822B)) +#define BIT_GET_F0F_SDM_8822B(x) \ + (((x) >> BIT_SHIFT_F0F_SDM_8822B) & BIT_MASK_F0F_SDM_8822B) +#define BIT_SET_F0F_SDM_8822B(x, v) \ + (BIT_CLEAR_F0F_SDM_8822B(x) | BIT_F0F_SDM_8822B(v)) #define BIT_SHIFT_F0N_SDM_8822B 9 #define BIT_MASK_F0N_SDM_8822B 0x7 -#define BIT_F0N_SDM_8822B(x) (((x) & BIT_MASK_F0N_SDM_8822B) << BIT_SHIFT_F0N_SDM_8822B) -#define BIT_GET_F0N_SDM_8822B(x) (((x) >> BIT_SHIFT_F0N_SDM_8822B) & BIT_MASK_F0N_SDM_8822B) - - +#define BIT_F0N_SDM_8822B(x) \ + (((x) & BIT_MASK_F0N_SDM_8822B) << BIT_SHIFT_F0N_SDM_8822B) +#define BITS_F0N_SDM_8822B (BIT_MASK_F0N_SDM_8822B << BIT_SHIFT_F0N_SDM_8822B) +#define BIT_CLEAR_F0N_SDM_8822B(x) ((x) & (~BITS_F0N_SDM_8822B)) +#define BIT_GET_F0N_SDM_8822B(x) \ + (((x) >> BIT_SHIFT_F0N_SDM_8822B) & BIT_MASK_F0N_SDM_8822B) +#define BIT_SET_F0N_SDM_8822B(x, v) \ + (BIT_CLEAR_F0N_SDM_8822B(x) | BIT_F0N_SDM_8822B(v)) #define BIT_SHIFT_DIVN_SDM_8822B 3 #define BIT_MASK_DIVN_SDM_8822B 0x3f -#define BIT_DIVN_SDM_8822B(x) (((x) & BIT_MASK_DIVN_SDM_8822B) << BIT_SHIFT_DIVN_SDM_8822B) -#define BIT_GET_DIVN_SDM_8822B(x) (((x) >> BIT_SHIFT_DIVN_SDM_8822B) & BIT_MASK_DIVN_SDM_8822B) - - +#define BIT_DIVN_SDM_8822B(x) \ + (((x) & BIT_MASK_DIVN_SDM_8822B) << BIT_SHIFT_DIVN_SDM_8822B) +#define BITS_DIVN_SDM_8822B \ + (BIT_MASK_DIVN_SDM_8822B << BIT_SHIFT_DIVN_SDM_8822B) +#define BIT_CLEAR_DIVN_SDM_8822B(x) ((x) & (~BITS_DIVN_SDM_8822B)) +#define BIT_GET_DIVN_SDM_8822B(x) \ + (((x) >> BIT_SHIFT_DIVN_SDM_8822B) & BIT_MASK_DIVN_SDM_8822B) +#define BIT_SET_DIVN_SDM_8822B(x, v) \ + (BIT_CLEAR_DIVN_SDM_8822B(x) | BIT_DIVN_SDM_8822B(v)) /* 2 REG_GPIO_DEBOUNCE_CTRL_8822B */ #define BIT_WLGP_DBC1EN_8822B BIT(15) #define BIT_SHIFT_WLGP_DBC1_8822B 8 #define BIT_MASK_WLGP_DBC1_8822B 0xf -#define BIT_WLGP_DBC1_8822B(x) (((x) & BIT_MASK_WLGP_DBC1_8822B) << BIT_SHIFT_WLGP_DBC1_8822B) -#define BIT_GET_WLGP_DBC1_8822B(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8822B) & BIT_MASK_WLGP_DBC1_8822B) - +#define BIT_WLGP_DBC1_8822B(x) \ + (((x) & BIT_MASK_WLGP_DBC1_8822B) << BIT_SHIFT_WLGP_DBC1_8822B) +#define BITS_WLGP_DBC1_8822B \ + (BIT_MASK_WLGP_DBC1_8822B << BIT_SHIFT_WLGP_DBC1_8822B) +#define BIT_CLEAR_WLGP_DBC1_8822B(x) ((x) & (~BITS_WLGP_DBC1_8822B)) +#define BIT_GET_WLGP_DBC1_8822B(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC1_8822B) & BIT_MASK_WLGP_DBC1_8822B) +#define BIT_SET_WLGP_DBC1_8822B(x, v) \ + (BIT_CLEAR_WLGP_DBC1_8822B(x) | BIT_WLGP_DBC1_8822B(v)) #define BIT_WLGP_DBC0EN_8822B BIT(7) #define BIT_SHIFT_WLGP_DBC0_8822B 0 #define BIT_MASK_WLGP_DBC0_8822B 0xf -#define BIT_WLGP_DBC0_8822B(x) (((x) & BIT_MASK_WLGP_DBC0_8822B) << BIT_SHIFT_WLGP_DBC0_8822B) -#define BIT_GET_WLGP_DBC0_8822B(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8822B) & BIT_MASK_WLGP_DBC0_8822B) - - +#define BIT_WLGP_DBC0_8822B(x) \ + (((x) & BIT_MASK_WLGP_DBC0_8822B) << BIT_SHIFT_WLGP_DBC0_8822B) +#define BITS_WLGP_DBC0_8822B \ + (BIT_MASK_WLGP_DBC0_8822B << BIT_SHIFT_WLGP_DBC0_8822B) +#define BIT_CLEAR_WLGP_DBC0_8822B(x) ((x) & (~BITS_WLGP_DBC0_8822B)) +#define BIT_GET_WLGP_DBC0_8822B(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC0_8822B) & BIT_MASK_WLGP_DBC0_8822B) +#define BIT_SET_WLGP_DBC0_8822B(x, v) \ + (BIT_CLEAR_WLGP_DBC0_8822B(x) | BIT_WLGP_DBC0_8822B(v)) /* 2 REG_RPWM2_8822B */ #define BIT_SHIFT_RPWM2_8822B 16 #define BIT_MASK_RPWM2_8822B 0xffff -#define BIT_RPWM2_8822B(x) (((x) & BIT_MASK_RPWM2_8822B) << BIT_SHIFT_RPWM2_8822B) -#define BIT_GET_RPWM2_8822B(x) (((x) >> BIT_SHIFT_RPWM2_8822B) & BIT_MASK_RPWM2_8822B) - - +#define BIT_RPWM2_8822B(x) \ + (((x) & BIT_MASK_RPWM2_8822B) << BIT_SHIFT_RPWM2_8822B) +#define BITS_RPWM2_8822B (BIT_MASK_RPWM2_8822B << BIT_SHIFT_RPWM2_8822B) +#define BIT_CLEAR_RPWM2_8822B(x) ((x) & (~BITS_RPWM2_8822B)) +#define BIT_GET_RPWM2_8822B(x) \ + (((x) >> BIT_SHIFT_RPWM2_8822B) & BIT_MASK_RPWM2_8822B) +#define BIT_SET_RPWM2_8822B(x, v) \ + (BIT_CLEAR_RPWM2_8822B(x) | BIT_RPWM2_8822B(v)) /* 2 REG_SYSON_FSM_MON_8822B */ #define BIT_SHIFT_FSM_MON_SEL_8822B 24 #define BIT_MASK_FSM_MON_SEL_8822B 0x7 -#define BIT_FSM_MON_SEL_8822B(x) (((x) & BIT_MASK_FSM_MON_SEL_8822B) << BIT_SHIFT_FSM_MON_SEL_8822B) -#define BIT_GET_FSM_MON_SEL_8822B(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8822B) & BIT_MASK_FSM_MON_SEL_8822B) - +#define BIT_FSM_MON_SEL_8822B(x) \ + (((x) & BIT_MASK_FSM_MON_SEL_8822B) << BIT_SHIFT_FSM_MON_SEL_8822B) +#define BITS_FSM_MON_SEL_8822B \ + (BIT_MASK_FSM_MON_SEL_8822B << BIT_SHIFT_FSM_MON_SEL_8822B) +#define BIT_CLEAR_FSM_MON_SEL_8822B(x) ((x) & (~BITS_FSM_MON_SEL_8822B)) +#define BIT_GET_FSM_MON_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_FSM_MON_SEL_8822B) & BIT_MASK_FSM_MON_SEL_8822B) +#define BIT_SET_FSM_MON_SEL_8822B(x, v) \ + (BIT_CLEAR_FSM_MON_SEL_8822B(x) | BIT_FSM_MON_SEL_8822B(v)) #define BIT_DOP_ELDO_8822B BIT(23) #define BIT_FSM_MON_UPD_8822B BIT(15) #define BIT_SHIFT_FSM_PAR_8822B 0 #define BIT_MASK_FSM_PAR_8822B 0x7fff -#define BIT_FSM_PAR_8822B(x) (((x) & BIT_MASK_FSM_PAR_8822B) << BIT_SHIFT_FSM_PAR_8822B) -#define BIT_GET_FSM_PAR_8822B(x) (((x) >> BIT_SHIFT_FSM_PAR_8822B) & BIT_MASK_FSM_PAR_8822B) - - +#define BIT_FSM_PAR_8822B(x) \ + (((x) & BIT_MASK_FSM_PAR_8822B) << BIT_SHIFT_FSM_PAR_8822B) +#define BITS_FSM_PAR_8822B (BIT_MASK_FSM_PAR_8822B << BIT_SHIFT_FSM_PAR_8822B) +#define BIT_CLEAR_FSM_PAR_8822B(x) ((x) & (~BITS_FSM_PAR_8822B)) +#define BIT_GET_FSM_PAR_8822B(x) \ + (((x) >> BIT_SHIFT_FSM_PAR_8822B) & BIT_MASK_FSM_PAR_8822B) +#define BIT_SET_FSM_PAR_8822B(x, v) \ + (BIT_CLEAR_FSM_PAR_8822B(x) | BIT_FSM_PAR_8822B(v)) /* 2 REG_AFE_CTRL6_8822B */ #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0 #define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0x7 -#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) - - +#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) +#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) \ + ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) & \ + BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) | \ + BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(v)) /* 2 REG_PMC_DBG_CTRL1_8822B */ #define BIT_BT_INT_EN_8822B BIT(31) #define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B 16 #define BIT_MASK_RD_WR_WIFI_BT_INFO_8822B 0x7fff -#define BIT_RD_WR_WIFI_BT_INFO_8822B(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) -#define BIT_GET_RD_WR_WIFI_BT_INFO_8822B(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) - +#define BIT_RD_WR_WIFI_BT_INFO_8822B(x) \ + (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) +#define BITS_RD_WR_WIFI_BT_INFO_8822B \ + (BIT_MASK_RD_WR_WIFI_BT_INFO_8822B \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822B(x) \ + ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8822B)) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) & \ + BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) +#define BIT_SET_RD_WR_WIFI_BT_INFO_8822B(x, v) \ + (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822B(x) | \ + BIT_RD_WR_WIFI_BT_INFO_8822B(v)) #define BIT_PMC_WR_OVF_8822B BIT(8) #define BIT_SHIFT_WLPMC_ERRINT_8822B 0 #define BIT_MASK_WLPMC_ERRINT_8822B 0xff -#define BIT_WLPMC_ERRINT_8822B(x) (((x) & BIT_MASK_WLPMC_ERRINT_8822B) << BIT_SHIFT_WLPMC_ERRINT_8822B) -#define BIT_GET_WLPMC_ERRINT_8822B(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8822B) & BIT_MASK_WLPMC_ERRINT_8822B) - - +#define BIT_WLPMC_ERRINT_8822B(x) \ + (((x) & BIT_MASK_WLPMC_ERRINT_8822B) << BIT_SHIFT_WLPMC_ERRINT_8822B) +#define BITS_WLPMC_ERRINT_8822B \ + (BIT_MASK_WLPMC_ERRINT_8822B << BIT_SHIFT_WLPMC_ERRINT_8822B) +#define BIT_CLEAR_WLPMC_ERRINT_8822B(x) ((x) & (~BITS_WLPMC_ERRINT_8822B)) +#define BIT_GET_WLPMC_ERRINT_8822B(x) \ + (((x) >> BIT_SHIFT_WLPMC_ERRINT_8822B) & BIT_MASK_WLPMC_ERRINT_8822B) +#define BIT_SET_WLPMC_ERRINT_8822B(x, v) \ + (BIT_CLEAR_WLPMC_ERRINT_8822B(x) | BIT_WLPMC_ERRINT_8822B(v)) /* 2 REG_AFE_CTRL7_8822B */ #define BIT_SHIFT_SEL_V_8822B 30 #define BIT_MASK_SEL_V_8822B 0x3 -#define BIT_SEL_V_8822B(x) (((x) & BIT_MASK_SEL_V_8822B) << BIT_SHIFT_SEL_V_8822B) -#define BIT_GET_SEL_V_8822B(x) (((x) >> BIT_SHIFT_SEL_V_8822B) & BIT_MASK_SEL_V_8822B) - +#define BIT_SEL_V_8822B(x) \ + (((x) & BIT_MASK_SEL_V_8822B) << BIT_SHIFT_SEL_V_8822B) +#define BITS_SEL_V_8822B (BIT_MASK_SEL_V_8822B << BIT_SHIFT_SEL_V_8822B) +#define BIT_CLEAR_SEL_V_8822B(x) ((x) & (~BITS_SEL_V_8822B)) +#define BIT_GET_SEL_V_8822B(x) \ + (((x) >> BIT_SHIFT_SEL_V_8822B) & BIT_MASK_SEL_V_8822B) +#define BIT_SET_SEL_V_8822B(x, v) \ + (BIT_CLEAR_SEL_V_8822B(x) | BIT_SEL_V_8822B(v)) #define BIT_SEL_LDO_PC_8822B BIT(29) #define BIT_SHIFT_CK_MON_SEL_8822B 26 #define BIT_MASK_CK_MON_SEL_8822B 0x7 -#define BIT_CK_MON_SEL_8822B(x) (((x) & BIT_MASK_CK_MON_SEL_8822B) << BIT_SHIFT_CK_MON_SEL_8822B) -#define BIT_GET_CK_MON_SEL_8822B(x) (((x) >> BIT_SHIFT_CK_MON_SEL_8822B) & BIT_MASK_CK_MON_SEL_8822B) - +#define BIT_CK_MON_SEL_8822B(x) \ + (((x) & BIT_MASK_CK_MON_SEL_8822B) << BIT_SHIFT_CK_MON_SEL_8822B) +#define BITS_CK_MON_SEL_8822B \ + (BIT_MASK_CK_MON_SEL_8822B << BIT_SHIFT_CK_MON_SEL_8822B) +#define BIT_CLEAR_CK_MON_SEL_8822B(x) ((x) & (~BITS_CK_MON_SEL_8822B)) +#define BIT_GET_CK_MON_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL_8822B) & BIT_MASK_CK_MON_SEL_8822B) +#define BIT_SET_CK_MON_SEL_8822B(x, v) \ + (BIT_CLEAR_CK_MON_SEL_8822B(x) | BIT_CK_MON_SEL_8822B(v)) #define BIT_CK_MON_EN_8822B BIT(25) #define BIT_FREF_EDGE_8822B BIT(24) @@ -1344,8 +1987,8 @@ #define BIT_BCNDMAINT0_MSK_8822B BIT(20) #define BIT_BCNDERR0_MSK_8822B BIT(16) #define BIT_HSISR_IND_ON_INT_MSK_8822B BIT(15) -#define BIT_BCNDMAINT_E_MSK_8822B BIT(14) -#define BIT_CTWEND_MSK_8822B BIT(12) +#define BIT_HISR3_IND_INT_MSK_8822B BIT(14) +#define BIT_HISR2_IND_INT_MSK_8822B BIT(13) #define BIT_HISR1_IND_MSK_8822B BIT(11) #define BIT_C2HCMD_MSK_8822B BIT(10) #define BIT_CPWM2_MSK_8822B BIT(9) @@ -1360,8 +2003,8 @@ #define BIT_RXOK_MSK_8822B BIT(0) /* 2 REG_HISR0_8822B */ -#define BIT_TIMEOUT_INTERRUPT2_8822B BIT(31) -#define BIT_TIMEOUT_INTERRUTP1_8822B BIT(30) +#define BIT_PSTIMEOUT2_8822B BIT(31) +#define BIT_PSTIMEOUT1_8822B BIT(30) #define BIT_PSTIMEOUT_8822B BIT(29) #define BIT_GTINT4_8822B BIT(28) #define BIT_GTINT3_8822B BIT(27) @@ -1371,8 +2014,8 @@ #define BIT_BCNDMAINT0_8822B BIT(20) #define BIT_BCNDERR0_8822B BIT(16) #define BIT_HSISR_IND_ON_INT_8822B BIT(15) -#define BIT_BCNDMAINT_E_8822B BIT(14) -#define BIT_CTWEND_8822B BIT(12) +#define BIT_HISR3_IND_INT_8822B BIT(14) +#define BIT_HISR2_IND_INT_8822B BIT(13) #define BIT_HISR1_IND_INT_8822B BIT(11) #define BIT_C2HCMD_8822B BIT(10) #define BIT_CPWM2_8822B BIT(9) @@ -1389,7 +2032,6 @@ /* 2 REG_HIMR1_8822B */ #define BIT_TXFIFO_TH_INT_8822B BIT(30) #define BIT_BTON_STS_UPDATE_MASK_8822B BIT(29) -#define BIT_MCU_ERR_MASK_8822B BIT(28) #define BIT_BCNDMAINT7__MSK_8822B BIT(27) #define BIT_BCNDMAINT6__MSK_8822B BIT(26) #define BIT_BCNDMAINT5__MSK_8822B BIT(25) @@ -1404,8 +2046,7 @@ #define BIT_BCNDERR3_MSK_8822B BIT(16) #define BIT_BCNDERR2_MSK_8822B BIT(15) #define BIT_BCNDERR1_MSK_8822B BIT(14) -#define BIT_ATIMEND_E_MSK_8822B BIT(13) -#define BIT_ATIMEND__MSK_8822B BIT(12) +#define BIT_ATIMEND_E_V1_MSK_8822B BIT(12) #define BIT_TXERR_MSK_8822B BIT(11) #define BIT_RXERR_MSK_8822B BIT(10) #define BIT_TXFOVW_MSK_8822B BIT(9) @@ -1419,7 +2060,6 @@ /* 2 REG_HISR1_8822B */ #define BIT_TXFIFO_TH_INT_8822B BIT(30) #define BIT_BTON_STS_UPDATE_INT_8822B BIT(29) -#define BIT_MCU_ERR_8822B BIT(28) #define BIT_BCNDMAINT7_8822B BIT(27) #define BIT_BCNDMAINT6_8822B BIT(26) #define BIT_BCNDMAINT5_8822B BIT(25) @@ -1434,8 +2074,7 @@ #define BIT_BCNDERR3_8822B BIT(16) #define BIT_BCNDERR2_8822B BIT(15) #define BIT_BCNDERR1_8822B BIT(14) -#define BIT_ATIMEND_E_8822B BIT(13) -#define BIT_ATIMEND_8822B BIT(12) +#define BIT_ATIMEND_E_V1_INT_8822B BIT(12) #define BIT_TXERR_INT_8822B BIT(11) #define BIT_RXERR_INT_8822B BIT(10) #define BIT_TXFOVW_8822B BIT(9) @@ -1450,28 +2089,48 @@ #define BIT_SHIFT_DEBUG_ST_8822B 0 #define BIT_MASK_DEBUG_ST_8822B 0xffffffffL -#define BIT_DEBUG_ST_8822B(x) (((x) & BIT_MASK_DEBUG_ST_8822B) << BIT_SHIFT_DEBUG_ST_8822B) -#define BIT_GET_DEBUG_ST_8822B(x) (((x) >> BIT_SHIFT_DEBUG_ST_8822B) & BIT_MASK_DEBUG_ST_8822B) - - +#define BIT_DEBUG_ST_8822B(x) \ + (((x) & BIT_MASK_DEBUG_ST_8822B) << BIT_SHIFT_DEBUG_ST_8822B) +#define BITS_DEBUG_ST_8822B \ + (BIT_MASK_DEBUG_ST_8822B << BIT_SHIFT_DEBUG_ST_8822B) +#define BIT_CLEAR_DEBUG_ST_8822B(x) ((x) & (~BITS_DEBUG_ST_8822B)) +#define BIT_GET_DEBUG_ST_8822B(x) \ + (((x) >> BIT_SHIFT_DEBUG_ST_8822B) & BIT_MASK_DEBUG_ST_8822B) +#define BIT_SET_DEBUG_ST_8822B(x, v) \ + (BIT_CLEAR_DEBUG_ST_8822B(x) | BIT_DEBUG_ST_8822B(v)) /* 2 REG_PAD_CTRL2_8822B */ #define BIT_USB3_USB2_TRANSITION_8822B BIT(20) #define BIT_SHIFT_USB23_SW_MODE_V1_8822B 18 #define BIT_MASK_USB23_SW_MODE_V1_8822B 0x3 -#define BIT_USB23_SW_MODE_V1_8822B(x) (((x) & BIT_MASK_USB23_SW_MODE_V1_8822B) << BIT_SHIFT_USB23_SW_MODE_V1_8822B) -#define BIT_GET_USB23_SW_MODE_V1_8822B(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822B) & BIT_MASK_USB23_SW_MODE_V1_8822B) - +#define BIT_USB23_SW_MODE_V1_8822B(x) \ + (((x) & BIT_MASK_USB23_SW_MODE_V1_8822B) \ + << BIT_SHIFT_USB23_SW_MODE_V1_8822B) +#define BITS_USB23_SW_MODE_V1_8822B \ + (BIT_MASK_USB23_SW_MODE_V1_8822B << BIT_SHIFT_USB23_SW_MODE_V1_8822B) +#define BIT_CLEAR_USB23_SW_MODE_V1_8822B(x) \ + ((x) & (~BITS_USB23_SW_MODE_V1_8822B)) +#define BIT_GET_USB23_SW_MODE_V1_8822B(x) \ + (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822B) & \ + BIT_MASK_USB23_SW_MODE_V1_8822B) +#define BIT_SET_USB23_SW_MODE_V1_8822B(x, v) \ + (BIT_CLEAR_USB23_SW_MODE_V1_8822B(x) | BIT_USB23_SW_MODE_V1_8822B(v)) #define BIT_NO_PDN_CHIPOFF_V1_8822B BIT(17) #define BIT_RSM_EN_V1_8822B BIT(16) #define BIT_SHIFT_MATCH_CNT_8822B 8 #define BIT_MASK_MATCH_CNT_8822B 0xff -#define BIT_MATCH_CNT_8822B(x) (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B) -#define BIT_GET_MATCH_CNT_8822B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B) - +#define BIT_MATCH_CNT_8822B(x) \ + (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B) +#define BITS_MATCH_CNT_8822B \ + (BIT_MASK_MATCH_CNT_8822B << BIT_SHIFT_MATCH_CNT_8822B) +#define BIT_CLEAR_MATCH_CNT_8822B(x) ((x) & (~BITS_MATCH_CNT_8822B)) +#define BIT_GET_MATCH_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B) +#define BIT_SET_MATCH_CNT_8822B(x, v) \ + (BIT_CLEAR_MATCH_CNT_8822B(x) | BIT_MATCH_CNT_8822B(v)) #define BIT_LD_B12V_EN_8822B BIT(7) #define BIT_EECS_IOSEL_V1_8822B BIT(6) @@ -1487,9 +2146,17 @@ #define BIT_SHIFT_EFUSE_BURN_GNT_8822B 24 #define BIT_MASK_EFUSE_BURN_GNT_8822B 0xff -#define BIT_EFUSE_BURN_GNT_8822B(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8822B) << BIT_SHIFT_EFUSE_BURN_GNT_8822B) -#define BIT_GET_EFUSE_BURN_GNT_8822B(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822B) & BIT_MASK_EFUSE_BURN_GNT_8822B) - +#define BIT_EFUSE_BURN_GNT_8822B(x) \ + (((x) & BIT_MASK_EFUSE_BURN_GNT_8822B) \ + << BIT_SHIFT_EFUSE_BURN_GNT_8822B) +#define BITS_EFUSE_BURN_GNT_8822B \ + (BIT_MASK_EFUSE_BURN_GNT_8822B << BIT_SHIFT_EFUSE_BURN_GNT_8822B) +#define BIT_CLEAR_EFUSE_BURN_GNT_8822B(x) ((x) & (~BITS_EFUSE_BURN_GNT_8822B)) +#define BIT_GET_EFUSE_BURN_GNT_8822B(x) \ + (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822B) & \ + BIT_MASK_EFUSE_BURN_GNT_8822B) +#define BIT_SET_EFUSE_BURN_GNT_8822B(x, v) \ + (BIT_CLEAR_EFUSE_BURN_GNT_8822B(x) | BIT_EFUSE_BURN_GNT_8822B(v)) #define BIT_STOP_WL_PMC_8822B BIT(9) #define BIT_STOP_SYM_PMC_8822B BIT(8) @@ -1500,10 +2167,15 @@ #define BIT_SHIFT_SYSON_REG_ARB_8822B 0 #define BIT_MASK_SYSON_REG_ARB_8822B 0x3 -#define BIT_SYSON_REG_ARB_8822B(x) (((x) & BIT_MASK_SYSON_REG_ARB_8822B) << BIT_SHIFT_SYSON_REG_ARB_8822B) -#define BIT_GET_SYSON_REG_ARB_8822B(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8822B) & BIT_MASK_SYSON_REG_ARB_8822B) - - +#define BIT_SYSON_REG_ARB_8822B(x) \ + (((x) & BIT_MASK_SYSON_REG_ARB_8822B) << BIT_SHIFT_SYSON_REG_ARB_8822B) +#define BITS_SYSON_REG_ARB_8822B \ + (BIT_MASK_SYSON_REG_ARB_8822B << BIT_SHIFT_SYSON_REG_ARB_8822B) +#define BIT_CLEAR_SYSON_REG_ARB_8822B(x) ((x) & (~BITS_SYSON_REG_ARB_8822B)) +#define BIT_GET_SYSON_REG_ARB_8822B(x) \ + (((x) >> BIT_SHIFT_SYSON_REG_ARB_8822B) & BIT_MASK_SYSON_REG_ARB_8822B) +#define BIT_SET_SYSON_REG_ARB_8822B(x, v) \ + (BIT_CLEAR_SYSON_REG_ARB_8822B(x) | BIT_SYSON_REG_ARB_8822B(v)) /* 2 REG_BIST_CTRL_8822B */ #define BIT_BIST_USB_DIS_8822B BIT(27) @@ -1513,9 +2185,15 @@ #define BIT_SHIFT_BIST_RPT_SEL_8822B 16 #define BIT_MASK_BIST_RPT_SEL_8822B 0xf -#define BIT_BIST_RPT_SEL_8822B(x) (((x) & BIT_MASK_BIST_RPT_SEL_8822B) << BIT_SHIFT_BIST_RPT_SEL_8822B) -#define BIT_GET_BIST_RPT_SEL_8822B(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8822B) & BIT_MASK_BIST_RPT_SEL_8822B) - +#define BIT_BIST_RPT_SEL_8822B(x) \ + (((x) & BIT_MASK_BIST_RPT_SEL_8822B) << BIT_SHIFT_BIST_RPT_SEL_8822B) +#define BITS_BIST_RPT_SEL_8822B \ + (BIT_MASK_BIST_RPT_SEL_8822B << BIT_SHIFT_BIST_RPT_SEL_8822B) +#define BIT_CLEAR_BIST_RPT_SEL_8822B(x) ((x) & (~BITS_BIST_RPT_SEL_8822B)) +#define BIT_GET_BIST_RPT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_BIST_RPT_SEL_8822B) & BIT_MASK_BIST_RPT_SEL_8822B) +#define BIT_SET_BIST_RPT_SEL_8822B(x, v) \ + (BIT_CLEAR_BIST_RPT_SEL_8822B(x) | BIT_BIST_RPT_SEL_8822B(v)) #define BIT_BIST_RESUME_PS_8822B BIT(4) #define BIT_BIST_RESUME_8822B BIT(3) @@ -1527,62 +2205,100 @@ #define BIT_SHIFT_MBIST_REPORT_8822B 0 #define BIT_MASK_MBIST_REPORT_8822B 0xffffffffL -#define BIT_MBIST_REPORT_8822B(x) (((x) & BIT_MASK_MBIST_REPORT_8822B) << BIT_SHIFT_MBIST_REPORT_8822B) -#define BIT_GET_MBIST_REPORT_8822B(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8822B) & BIT_MASK_MBIST_REPORT_8822B) - - +#define BIT_MBIST_REPORT_8822B(x) \ + (((x) & BIT_MASK_MBIST_REPORT_8822B) << BIT_SHIFT_MBIST_REPORT_8822B) +#define BITS_MBIST_REPORT_8822B \ + (BIT_MASK_MBIST_REPORT_8822B << BIT_SHIFT_MBIST_REPORT_8822B) +#define BIT_CLEAR_MBIST_REPORT_8822B(x) ((x) & (~BITS_MBIST_REPORT_8822B)) +#define BIT_GET_MBIST_REPORT_8822B(x) \ + (((x) >> BIT_SHIFT_MBIST_REPORT_8822B) & BIT_MASK_MBIST_REPORT_8822B) +#define BIT_SET_MBIST_REPORT_8822B(x, v) \ + (BIT_CLEAR_MBIST_REPORT_8822B(x) | BIT_MBIST_REPORT_8822B(v)) /* 2 REG_MEM_CTRL_8822B */ #define BIT_UMEM_RME_8822B BIT(31) #define BIT_SHIFT_BT_SPRAM_8822B 28 #define BIT_MASK_BT_SPRAM_8822B 0x3 -#define BIT_BT_SPRAM_8822B(x) (((x) & BIT_MASK_BT_SPRAM_8822B) << BIT_SHIFT_BT_SPRAM_8822B) -#define BIT_GET_BT_SPRAM_8822B(x) (((x) >> BIT_SHIFT_BT_SPRAM_8822B) & BIT_MASK_BT_SPRAM_8822B) - - +#define BIT_BT_SPRAM_8822B(x) \ + (((x) & BIT_MASK_BT_SPRAM_8822B) << BIT_SHIFT_BT_SPRAM_8822B) +#define BITS_BT_SPRAM_8822B \ + (BIT_MASK_BT_SPRAM_8822B << BIT_SHIFT_BT_SPRAM_8822B) +#define BIT_CLEAR_BT_SPRAM_8822B(x) ((x) & (~BITS_BT_SPRAM_8822B)) +#define BIT_GET_BT_SPRAM_8822B(x) \ + (((x) >> BIT_SHIFT_BT_SPRAM_8822B) & BIT_MASK_BT_SPRAM_8822B) +#define BIT_SET_BT_SPRAM_8822B(x, v) \ + (BIT_CLEAR_BT_SPRAM_8822B(x) | BIT_BT_SPRAM_8822B(v)) #define BIT_SHIFT_BT_ROM_8822B 24 #define BIT_MASK_BT_ROM_8822B 0xf -#define BIT_BT_ROM_8822B(x) (((x) & BIT_MASK_BT_ROM_8822B) << BIT_SHIFT_BT_ROM_8822B) -#define BIT_GET_BT_ROM_8822B(x) (((x) >> BIT_SHIFT_BT_ROM_8822B) & BIT_MASK_BT_ROM_8822B) - - +#define BIT_BT_ROM_8822B(x) \ + (((x) & BIT_MASK_BT_ROM_8822B) << BIT_SHIFT_BT_ROM_8822B) +#define BITS_BT_ROM_8822B (BIT_MASK_BT_ROM_8822B << BIT_SHIFT_BT_ROM_8822B) +#define BIT_CLEAR_BT_ROM_8822B(x) ((x) & (~BITS_BT_ROM_8822B)) +#define BIT_GET_BT_ROM_8822B(x) \ + (((x) >> BIT_SHIFT_BT_ROM_8822B) & BIT_MASK_BT_ROM_8822B) +#define BIT_SET_BT_ROM_8822B(x, v) \ + (BIT_CLEAR_BT_ROM_8822B(x) | BIT_BT_ROM_8822B(v)) #define BIT_SHIFT_PCI_DPRAM_8822B 10 #define BIT_MASK_PCI_DPRAM_8822B 0x3 -#define BIT_PCI_DPRAM_8822B(x) (((x) & BIT_MASK_PCI_DPRAM_8822B) << BIT_SHIFT_PCI_DPRAM_8822B) -#define BIT_GET_PCI_DPRAM_8822B(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8822B) & BIT_MASK_PCI_DPRAM_8822B) - - +#define BIT_PCI_DPRAM_8822B(x) \ + (((x) & BIT_MASK_PCI_DPRAM_8822B) << BIT_SHIFT_PCI_DPRAM_8822B) +#define BITS_PCI_DPRAM_8822B \ + (BIT_MASK_PCI_DPRAM_8822B << BIT_SHIFT_PCI_DPRAM_8822B) +#define BIT_CLEAR_PCI_DPRAM_8822B(x) ((x) & (~BITS_PCI_DPRAM_8822B)) +#define BIT_GET_PCI_DPRAM_8822B(x) \ + (((x) >> BIT_SHIFT_PCI_DPRAM_8822B) & BIT_MASK_PCI_DPRAM_8822B) +#define BIT_SET_PCI_DPRAM_8822B(x, v) \ + (BIT_CLEAR_PCI_DPRAM_8822B(x) | BIT_PCI_DPRAM_8822B(v)) #define BIT_SHIFT_PCI_SPRAM_8822B 8 #define BIT_MASK_PCI_SPRAM_8822B 0x3 -#define BIT_PCI_SPRAM_8822B(x) (((x) & BIT_MASK_PCI_SPRAM_8822B) << BIT_SHIFT_PCI_SPRAM_8822B) -#define BIT_GET_PCI_SPRAM_8822B(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8822B) & BIT_MASK_PCI_SPRAM_8822B) - - +#define BIT_PCI_SPRAM_8822B(x) \ + (((x) & BIT_MASK_PCI_SPRAM_8822B) << BIT_SHIFT_PCI_SPRAM_8822B) +#define BITS_PCI_SPRAM_8822B \ + (BIT_MASK_PCI_SPRAM_8822B << BIT_SHIFT_PCI_SPRAM_8822B) +#define BIT_CLEAR_PCI_SPRAM_8822B(x) ((x) & (~BITS_PCI_SPRAM_8822B)) +#define BIT_GET_PCI_SPRAM_8822B(x) \ + (((x) >> BIT_SHIFT_PCI_SPRAM_8822B) & BIT_MASK_PCI_SPRAM_8822B) +#define BIT_SET_PCI_SPRAM_8822B(x, v) \ + (BIT_CLEAR_PCI_SPRAM_8822B(x) | BIT_PCI_SPRAM_8822B(v)) #define BIT_SHIFT_USB_SPRAM_8822B 6 #define BIT_MASK_USB_SPRAM_8822B 0x3 -#define BIT_USB_SPRAM_8822B(x) (((x) & BIT_MASK_USB_SPRAM_8822B) << BIT_SHIFT_USB_SPRAM_8822B) -#define BIT_GET_USB_SPRAM_8822B(x) (((x) >> BIT_SHIFT_USB_SPRAM_8822B) & BIT_MASK_USB_SPRAM_8822B) - - +#define BIT_USB_SPRAM_8822B(x) \ + (((x) & BIT_MASK_USB_SPRAM_8822B) << BIT_SHIFT_USB_SPRAM_8822B) +#define BITS_USB_SPRAM_8822B \ + (BIT_MASK_USB_SPRAM_8822B << BIT_SHIFT_USB_SPRAM_8822B) +#define BIT_CLEAR_USB_SPRAM_8822B(x) ((x) & (~BITS_USB_SPRAM_8822B)) +#define BIT_GET_USB_SPRAM_8822B(x) \ + (((x) >> BIT_SHIFT_USB_SPRAM_8822B) & BIT_MASK_USB_SPRAM_8822B) +#define BIT_SET_USB_SPRAM_8822B(x, v) \ + (BIT_CLEAR_USB_SPRAM_8822B(x) | BIT_USB_SPRAM_8822B(v)) #define BIT_SHIFT_USB_SPRF_8822B 4 #define BIT_MASK_USB_SPRF_8822B 0x3 -#define BIT_USB_SPRF_8822B(x) (((x) & BIT_MASK_USB_SPRF_8822B) << BIT_SHIFT_USB_SPRF_8822B) -#define BIT_GET_USB_SPRF_8822B(x) (((x) >> BIT_SHIFT_USB_SPRF_8822B) & BIT_MASK_USB_SPRF_8822B) - - +#define BIT_USB_SPRF_8822B(x) \ + (((x) & BIT_MASK_USB_SPRF_8822B) << BIT_SHIFT_USB_SPRF_8822B) +#define BITS_USB_SPRF_8822B \ + (BIT_MASK_USB_SPRF_8822B << BIT_SHIFT_USB_SPRF_8822B) +#define BIT_CLEAR_USB_SPRF_8822B(x) ((x) & (~BITS_USB_SPRF_8822B)) +#define BIT_GET_USB_SPRF_8822B(x) \ + (((x) >> BIT_SHIFT_USB_SPRF_8822B) & BIT_MASK_USB_SPRF_8822B) +#define BIT_SET_USB_SPRF_8822B(x, v) \ + (BIT_CLEAR_USB_SPRF_8822B(x) | BIT_USB_SPRF_8822B(v)) #define BIT_SHIFT_MCU_ROM_8822B 0 #define BIT_MASK_MCU_ROM_8822B 0xf -#define BIT_MCU_ROM_8822B(x) (((x) & BIT_MASK_MCU_ROM_8822B) << BIT_SHIFT_MCU_ROM_8822B) -#define BIT_GET_MCU_ROM_8822B(x) (((x) >> BIT_SHIFT_MCU_ROM_8822B) & BIT_MASK_MCU_ROM_8822B) - - +#define BIT_MCU_ROM_8822B(x) \ + (((x) & BIT_MASK_MCU_ROM_8822B) << BIT_SHIFT_MCU_ROM_8822B) +#define BITS_MCU_ROM_8822B (BIT_MASK_MCU_ROM_8822B << BIT_SHIFT_MCU_ROM_8822B) +#define BIT_CLEAR_MCU_ROM_8822B(x) ((x) & (~BITS_MCU_ROM_8822B)) +#define BIT_GET_MCU_ROM_8822B(x) \ + (((x) >> BIT_SHIFT_MCU_ROM_8822B) & BIT_MASK_MCU_ROM_8822B) +#define BIT_SET_MCU_ROM_8822B(x, v) \ + (BIT_CLEAR_MCU_ROM_8822B(x) | BIT_MCU_ROM_8822B(v)) /* 2 REG_AFE_CTRL8_8822B */ #define BIT_SYN_AGPIO_8822B BIT(20) @@ -1591,10 +2307,15 @@ #define BIT_SHIFT_XTAL_SEL_TOK_8822B 0 #define BIT_MASK_XTAL_SEL_TOK_8822B 0x7 -#define BIT_XTAL_SEL_TOK_8822B(x) (((x) & BIT_MASK_XTAL_SEL_TOK_8822B) << BIT_SHIFT_XTAL_SEL_TOK_8822B) -#define BIT_GET_XTAL_SEL_TOK_8822B(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8822B) & BIT_MASK_XTAL_SEL_TOK_8822B) - - +#define BIT_XTAL_SEL_TOK_8822B(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_8822B) << BIT_SHIFT_XTAL_SEL_TOK_8822B) +#define BITS_XTAL_SEL_TOK_8822B \ + (BIT_MASK_XTAL_SEL_TOK_8822B << BIT_SHIFT_XTAL_SEL_TOK_8822B) +#define BIT_CLEAR_XTAL_SEL_TOK_8822B(x) ((x) & (~BITS_XTAL_SEL_TOK_8822B)) +#define BIT_GET_XTAL_SEL_TOK_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8822B) & BIT_MASK_XTAL_SEL_TOK_8822B) +#define BIT_SET_XTAL_SEL_TOK_8822B(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_8822B(x) | BIT_XTAL_SEL_TOK_8822B(v)) /* 2 REG_USB_SIE_INTF_8822B */ #define BIT_RD_SEL_8822B BIT(31) @@ -1604,24 +2325,48 @@ #define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B 16 #define BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B 0x1ff -#define BIT_USB_SIE_INTF_ADDR_V1_8822B(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) -#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B) - - +#define BIT_USB_SIE_INTF_ADDR_V1_8822B(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B) \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) +#define BITS_USB_SIE_INTF_ADDR_V1_8822B \ + (BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) +#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822B(x) \ + ((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8822B)) +#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822B(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) & \ + BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B) +#define BIT_SET_USB_SIE_INTF_ADDR_V1_8822B(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822B(x) | \ + BIT_USB_SIE_INTF_ADDR_V1_8822B(v)) #define BIT_SHIFT_USB_SIE_INTF_RD_8822B 8 #define BIT_MASK_USB_SIE_INTF_RD_8822B 0xff -#define BIT_USB_SIE_INTF_RD_8822B(x) (((x) & BIT_MASK_USB_SIE_INTF_RD_8822B) << BIT_SHIFT_USB_SIE_INTF_RD_8822B) -#define BIT_GET_USB_SIE_INTF_RD_8822B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822B) & BIT_MASK_USB_SIE_INTF_RD_8822B) - - +#define BIT_USB_SIE_INTF_RD_8822B(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_RD_8822B) \ + << BIT_SHIFT_USB_SIE_INTF_RD_8822B) +#define BITS_USB_SIE_INTF_RD_8822B \ + (BIT_MASK_USB_SIE_INTF_RD_8822B << BIT_SHIFT_USB_SIE_INTF_RD_8822B) +#define BIT_CLEAR_USB_SIE_INTF_RD_8822B(x) ((x) & (~BITS_USB_SIE_INTF_RD_8822B)) +#define BIT_GET_USB_SIE_INTF_RD_8822B(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822B) & \ + BIT_MASK_USB_SIE_INTF_RD_8822B) +#define BIT_SET_USB_SIE_INTF_RD_8822B(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_RD_8822B(x) | BIT_USB_SIE_INTF_RD_8822B(v)) #define BIT_SHIFT_USB_SIE_INTF_WD_8822B 0 #define BIT_MASK_USB_SIE_INTF_WD_8822B 0xff -#define BIT_USB_SIE_INTF_WD_8822B(x) (((x) & BIT_MASK_USB_SIE_INTF_WD_8822B) << BIT_SHIFT_USB_SIE_INTF_WD_8822B) -#define BIT_GET_USB_SIE_INTF_WD_8822B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822B) & BIT_MASK_USB_SIE_INTF_WD_8822B) - - +#define BIT_USB_SIE_INTF_WD_8822B(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_WD_8822B) \ + << BIT_SHIFT_USB_SIE_INTF_WD_8822B) +#define BITS_USB_SIE_INTF_WD_8822B \ + (BIT_MASK_USB_SIE_INTF_WD_8822B << BIT_SHIFT_USB_SIE_INTF_WD_8822B) +#define BIT_CLEAR_USB_SIE_INTF_WD_8822B(x) ((x) & (~BITS_USB_SIE_INTF_WD_8822B)) +#define BIT_GET_USB_SIE_INTF_WD_8822B(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822B) & \ + BIT_MASK_USB_SIE_INTF_WD_8822B) +#define BIT_SET_USB_SIE_INTF_WD_8822B(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_WD_8822B(x) | BIT_USB_SIE_INTF_WD_8822B(v)) /* 2 REG_PCIE_MIO_INTF_8822B */ #define BIT_PCIE_MIO_BYIOREG_8822B BIT(13) @@ -1629,43 +2374,69 @@ #define BIT_SHIFT_PCIE_MIO_WE_8822B 8 #define BIT_MASK_PCIE_MIO_WE_8822B 0xf -#define BIT_PCIE_MIO_WE_8822B(x) (((x) & BIT_MASK_PCIE_MIO_WE_8822B) << BIT_SHIFT_PCIE_MIO_WE_8822B) -#define BIT_GET_PCIE_MIO_WE_8822B(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8822B) & BIT_MASK_PCIE_MIO_WE_8822B) - - +#define BIT_PCIE_MIO_WE_8822B(x) \ + (((x) & BIT_MASK_PCIE_MIO_WE_8822B) << BIT_SHIFT_PCIE_MIO_WE_8822B) +#define BITS_PCIE_MIO_WE_8822B \ + (BIT_MASK_PCIE_MIO_WE_8822B << BIT_SHIFT_PCIE_MIO_WE_8822B) +#define BIT_CLEAR_PCIE_MIO_WE_8822B(x) ((x) & (~BITS_PCIE_MIO_WE_8822B)) +#define BIT_GET_PCIE_MIO_WE_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_WE_8822B) & BIT_MASK_PCIE_MIO_WE_8822B) +#define BIT_SET_PCIE_MIO_WE_8822B(x, v) \ + (BIT_CLEAR_PCIE_MIO_WE_8822B(x) | BIT_PCIE_MIO_WE_8822B(v)) #define BIT_SHIFT_PCIE_MIO_ADDR_8822B 0 #define BIT_MASK_PCIE_MIO_ADDR_8822B 0xff -#define BIT_PCIE_MIO_ADDR_8822B(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8822B) << BIT_SHIFT_PCIE_MIO_ADDR_8822B) -#define BIT_GET_PCIE_MIO_ADDR_8822B(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822B) & BIT_MASK_PCIE_MIO_ADDR_8822B) - - +#define BIT_PCIE_MIO_ADDR_8822B(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_8822B) << BIT_SHIFT_PCIE_MIO_ADDR_8822B) +#define BITS_PCIE_MIO_ADDR_8822B \ + (BIT_MASK_PCIE_MIO_ADDR_8822B << BIT_SHIFT_PCIE_MIO_ADDR_8822B) +#define BIT_CLEAR_PCIE_MIO_ADDR_8822B(x) ((x) & (~BITS_PCIE_MIO_ADDR_8822B)) +#define BIT_GET_PCIE_MIO_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822B) & BIT_MASK_PCIE_MIO_ADDR_8822B) +#define BIT_SET_PCIE_MIO_ADDR_8822B(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_8822B(x) | BIT_PCIE_MIO_ADDR_8822B(v)) /* 2 REG_PCIE_MIO_INTD_8822B */ #define BIT_SHIFT_PCIE_MIO_DATA_8822B 0 #define BIT_MASK_PCIE_MIO_DATA_8822B 0xffffffffL -#define BIT_PCIE_MIO_DATA_8822B(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8822B) << BIT_SHIFT_PCIE_MIO_DATA_8822B) -#define BIT_GET_PCIE_MIO_DATA_8822B(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822B) & BIT_MASK_PCIE_MIO_DATA_8822B) - - +#define BIT_PCIE_MIO_DATA_8822B(x) \ + (((x) & BIT_MASK_PCIE_MIO_DATA_8822B) << BIT_SHIFT_PCIE_MIO_DATA_8822B) +#define BITS_PCIE_MIO_DATA_8822B \ + (BIT_MASK_PCIE_MIO_DATA_8822B << BIT_SHIFT_PCIE_MIO_DATA_8822B) +#define BIT_CLEAR_PCIE_MIO_DATA_8822B(x) ((x) & (~BITS_PCIE_MIO_DATA_8822B)) +#define BIT_GET_PCIE_MIO_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822B) & BIT_MASK_PCIE_MIO_DATA_8822B) +#define BIT_SET_PCIE_MIO_DATA_8822B(x, v) \ + (BIT_CLEAR_PCIE_MIO_DATA_8822B(x) | BIT_PCIE_MIO_DATA_8822B(v)) /* 2 REG_WLRF1_8822B */ #define BIT_SHIFT_WLRF1_CTRL_8822B 24 #define BIT_MASK_WLRF1_CTRL_8822B 0xff -#define BIT_WLRF1_CTRL_8822B(x) (((x) & BIT_MASK_WLRF1_CTRL_8822B) << BIT_SHIFT_WLRF1_CTRL_8822B) -#define BIT_GET_WLRF1_CTRL_8822B(x) (((x) >> BIT_SHIFT_WLRF1_CTRL_8822B) & BIT_MASK_WLRF1_CTRL_8822B) - - +#define BIT_WLRF1_CTRL_8822B(x) \ + (((x) & BIT_MASK_WLRF1_CTRL_8822B) << BIT_SHIFT_WLRF1_CTRL_8822B) +#define BITS_WLRF1_CTRL_8822B \ + (BIT_MASK_WLRF1_CTRL_8822B << BIT_SHIFT_WLRF1_CTRL_8822B) +#define BIT_CLEAR_WLRF1_CTRL_8822B(x) ((x) & (~BITS_WLRF1_CTRL_8822B)) +#define BIT_GET_WLRF1_CTRL_8822B(x) \ + (((x) >> BIT_SHIFT_WLRF1_CTRL_8822B) & BIT_MASK_WLRF1_CTRL_8822B) +#define BIT_SET_WLRF1_CTRL_8822B(x, v) \ + (BIT_CLEAR_WLRF1_CTRL_8822B(x) | BIT_WLRF1_CTRL_8822B(v)) /* 2 REG_SYS_CFG1_8822B */ #define BIT_SHIFT_TRP_ICFG_8822B 28 #define BIT_MASK_TRP_ICFG_8822B 0xf -#define BIT_TRP_ICFG_8822B(x) (((x) & BIT_MASK_TRP_ICFG_8822B) << BIT_SHIFT_TRP_ICFG_8822B) -#define BIT_GET_TRP_ICFG_8822B(x) (((x) >> BIT_SHIFT_TRP_ICFG_8822B) & BIT_MASK_TRP_ICFG_8822B) - +#define BIT_TRP_ICFG_8822B(x) \ + (((x) & BIT_MASK_TRP_ICFG_8822B) << BIT_SHIFT_TRP_ICFG_8822B) +#define BITS_TRP_ICFG_8822B \ + (BIT_MASK_TRP_ICFG_8822B << BIT_SHIFT_TRP_ICFG_8822B) +#define BIT_CLEAR_TRP_ICFG_8822B(x) ((x) & (~BITS_TRP_ICFG_8822B)) +#define BIT_GET_TRP_ICFG_8822B(x) \ + (((x) >> BIT_SHIFT_TRP_ICFG_8822B) & BIT_MASK_TRP_ICFG_8822B) +#define BIT_SET_TRP_ICFG_8822B(x, v) \ + (BIT_CLEAR_TRP_ICFG_8822B(x) | BIT_TRP_ICFG_8822B(v)) #define BIT_RF_TYPE_ID_8822B BIT(27) #define BIT_BD_HCI_SEL_8822B BIT(26) @@ -1677,16 +2448,27 @@ #define BIT_SHIFT_VENDOR_ID_8822B 16 #define BIT_MASK_VENDOR_ID_8822B 0xf -#define BIT_VENDOR_ID_8822B(x) (((x) & BIT_MASK_VENDOR_ID_8822B) << BIT_SHIFT_VENDOR_ID_8822B) -#define BIT_GET_VENDOR_ID_8822B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8822B) & BIT_MASK_VENDOR_ID_8822B) - - +#define BIT_VENDOR_ID_8822B(x) \ + (((x) & BIT_MASK_VENDOR_ID_8822B) << BIT_SHIFT_VENDOR_ID_8822B) +#define BITS_VENDOR_ID_8822B \ + (BIT_MASK_VENDOR_ID_8822B << BIT_SHIFT_VENDOR_ID_8822B) +#define BIT_CLEAR_VENDOR_ID_8822B(x) ((x) & (~BITS_VENDOR_ID_8822B)) +#define BIT_GET_VENDOR_ID_8822B(x) \ + (((x) >> BIT_SHIFT_VENDOR_ID_8822B) & BIT_MASK_VENDOR_ID_8822B) +#define BIT_SET_VENDOR_ID_8822B(x, v) \ + (BIT_CLEAR_VENDOR_ID_8822B(x) | BIT_VENDOR_ID_8822B(v)) #define BIT_SHIFT_CHIP_VER_8822B 12 #define BIT_MASK_CHIP_VER_8822B 0xf -#define BIT_CHIP_VER_8822B(x) (((x) & BIT_MASK_CHIP_VER_8822B) << BIT_SHIFT_CHIP_VER_8822B) -#define BIT_GET_CHIP_VER_8822B(x) (((x) >> BIT_SHIFT_CHIP_VER_8822B) & BIT_MASK_CHIP_VER_8822B) - +#define BIT_CHIP_VER_8822B(x) \ + (((x) & BIT_MASK_CHIP_VER_8822B) << BIT_SHIFT_CHIP_VER_8822B) +#define BITS_CHIP_VER_8822B \ + (BIT_MASK_CHIP_VER_8822B << BIT_SHIFT_CHIP_VER_8822B) +#define BIT_CLEAR_CHIP_VER_8822B(x) ((x) & (~BITS_CHIP_VER_8822B)) +#define BIT_GET_CHIP_VER_8822B(x) \ + (((x) >> BIT_SHIFT_CHIP_VER_8822B) & BIT_MASK_CHIP_VER_8822B) +#define BIT_SET_CHIP_VER_8822B(x, v) \ + (BIT_CLEAR_CHIP_VER_8822B(x) | BIT_CHIP_VER_8822B(v)) #define BIT_BD_MAC3_8822B BIT(11) #define BIT_BD_MAC1_8822B BIT(10) @@ -1705,24 +2487,41 @@ #define BIT_SHIFT_RF_RL_ID_8822B 28 #define BIT_MASK_RF_RL_ID_8822B 0xf -#define BIT_RF_RL_ID_8822B(x) (((x) & BIT_MASK_RF_RL_ID_8822B) << BIT_SHIFT_RF_RL_ID_8822B) -#define BIT_GET_RF_RL_ID_8822B(x) (((x) >> BIT_SHIFT_RF_RL_ID_8822B) & BIT_MASK_RF_RL_ID_8822B) - +#define BIT_RF_RL_ID_8822B(x) \ + (((x) & BIT_MASK_RF_RL_ID_8822B) << BIT_SHIFT_RF_RL_ID_8822B) +#define BITS_RF_RL_ID_8822B \ + (BIT_MASK_RF_RL_ID_8822B << BIT_SHIFT_RF_RL_ID_8822B) +#define BIT_CLEAR_RF_RL_ID_8822B(x) ((x) & (~BITS_RF_RL_ID_8822B)) +#define BIT_GET_RF_RL_ID_8822B(x) \ + (((x) >> BIT_SHIFT_RF_RL_ID_8822B) & BIT_MASK_RF_RL_ID_8822B) +#define BIT_SET_RF_RL_ID_8822B(x, v) \ + (BIT_CLEAR_RF_RL_ID_8822B(x) | BIT_RF_RL_ID_8822B(v)) #define BIT_HPHY_ICFG_8822B BIT(19) #define BIT_SHIFT_SEL_0XC0_8822B 16 #define BIT_MASK_SEL_0XC0_8822B 0x3 -#define BIT_SEL_0XC0_8822B(x) (((x) & BIT_MASK_SEL_0XC0_8822B) << BIT_SHIFT_SEL_0XC0_8822B) -#define BIT_GET_SEL_0XC0_8822B(x) (((x) >> BIT_SHIFT_SEL_0XC0_8822B) & BIT_MASK_SEL_0XC0_8822B) - - +#define BIT_SEL_0XC0_8822B(x) \ + (((x) & BIT_MASK_SEL_0XC0_8822B) << BIT_SHIFT_SEL_0XC0_8822B) +#define BITS_SEL_0XC0_8822B \ + (BIT_MASK_SEL_0XC0_8822B << BIT_SHIFT_SEL_0XC0_8822B) +#define BIT_CLEAR_SEL_0XC0_8822B(x) ((x) & (~BITS_SEL_0XC0_8822B)) +#define BIT_GET_SEL_0XC0_8822B(x) \ + (((x) >> BIT_SHIFT_SEL_0XC0_8822B) & BIT_MASK_SEL_0XC0_8822B) +#define BIT_SET_SEL_0XC0_8822B(x, v) \ + (BIT_CLEAR_SEL_0XC0_8822B(x) | BIT_SEL_0XC0_8822B(v)) #define BIT_SHIFT_HCI_SEL_V3_8822B 12 #define BIT_MASK_HCI_SEL_V3_8822B 0x7 -#define BIT_HCI_SEL_V3_8822B(x) (((x) & BIT_MASK_HCI_SEL_V3_8822B) << BIT_SHIFT_HCI_SEL_V3_8822B) -#define BIT_GET_HCI_SEL_V3_8822B(x) (((x) >> BIT_SHIFT_HCI_SEL_V3_8822B) & BIT_MASK_HCI_SEL_V3_8822B) - +#define BIT_HCI_SEL_V3_8822B(x) \ + (((x) & BIT_MASK_HCI_SEL_V3_8822B) << BIT_SHIFT_HCI_SEL_V3_8822B) +#define BITS_HCI_SEL_V3_8822B \ + (BIT_MASK_HCI_SEL_V3_8822B << BIT_SHIFT_HCI_SEL_V3_8822B) +#define BIT_CLEAR_HCI_SEL_V3_8822B(x) ((x) & (~BITS_HCI_SEL_V3_8822B)) +#define BIT_GET_HCI_SEL_V3_8822B(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V3_8822B) & BIT_MASK_HCI_SEL_V3_8822B) +#define BIT_SET_HCI_SEL_V3_8822B(x, v) \ + (BIT_CLEAR_HCI_SEL_V3_8822B(x) | BIT_HCI_SEL_V3_8822B(v)) #define BIT_USB_OPERATION_MODE_8822B BIT(10) #define BIT_BT_PDN_8822B BIT(9) @@ -1732,17 +2531,31 @@ #define BIT_SHIFT_PAD_HCI_SEL_V1_8822B 3 #define BIT_MASK_PAD_HCI_SEL_V1_8822B 0x7 -#define BIT_PAD_HCI_SEL_V1_8822B(x) (((x) & BIT_MASK_PAD_HCI_SEL_V1_8822B) << BIT_SHIFT_PAD_HCI_SEL_V1_8822B) -#define BIT_GET_PAD_HCI_SEL_V1_8822B(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1_8822B) & BIT_MASK_PAD_HCI_SEL_V1_8822B) - - +#define BIT_PAD_HCI_SEL_V1_8822B(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_V1_8822B) \ + << BIT_SHIFT_PAD_HCI_SEL_V1_8822B) +#define BITS_PAD_HCI_SEL_V1_8822B \ + (BIT_MASK_PAD_HCI_SEL_V1_8822B << BIT_SHIFT_PAD_HCI_SEL_V1_8822B) +#define BIT_CLEAR_PAD_HCI_SEL_V1_8822B(x) ((x) & (~BITS_PAD_HCI_SEL_V1_8822B)) +#define BIT_GET_PAD_HCI_SEL_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1_8822B) & \ + BIT_MASK_PAD_HCI_SEL_V1_8822B) +#define BIT_SET_PAD_HCI_SEL_V1_8822B(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_V1_8822B(x) | BIT_PAD_HCI_SEL_V1_8822B(v)) #define BIT_SHIFT_EFS_HCI_SEL_V1_8822B 0 #define BIT_MASK_EFS_HCI_SEL_V1_8822B 0x7 -#define BIT_EFS_HCI_SEL_V1_8822B(x) (((x) & BIT_MASK_EFS_HCI_SEL_V1_8822B) << BIT_SHIFT_EFS_HCI_SEL_V1_8822B) -#define BIT_GET_EFS_HCI_SEL_V1_8822B(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822B) & BIT_MASK_EFS_HCI_SEL_V1_8822B) - - +#define BIT_EFS_HCI_SEL_V1_8822B(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL_V1_8822B) \ + << BIT_SHIFT_EFS_HCI_SEL_V1_8822B) +#define BITS_EFS_HCI_SEL_V1_8822B \ + (BIT_MASK_EFS_HCI_SEL_V1_8822B << BIT_SHIFT_EFS_HCI_SEL_V1_8822B) +#define BIT_CLEAR_EFS_HCI_SEL_V1_8822B(x) ((x) & (~BITS_EFS_HCI_SEL_V1_8822B)) +#define BIT_GET_EFS_HCI_SEL_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822B) & \ + BIT_MASK_EFS_HCI_SEL_V1_8822B) +#define BIT_SET_EFS_HCI_SEL_V1_8822B(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL_V1_8822B(x) | BIT_EFS_HCI_SEL_V1_8822B(v)) /* 2 REG_SYS_STATUS2_8822B */ #define BIT_SIO_ALDN_8822B BIT(19) @@ -1752,27 +2565,39 @@ #define BIT_SHIFT_EPVID1_8822B 8 #define BIT_MASK_EPVID1_8822B 0xff -#define BIT_EPVID1_8822B(x) (((x) & BIT_MASK_EPVID1_8822B) << BIT_SHIFT_EPVID1_8822B) -#define BIT_GET_EPVID1_8822B(x) (((x) >> BIT_SHIFT_EPVID1_8822B) & BIT_MASK_EPVID1_8822B) - - +#define BIT_EPVID1_8822B(x) \ + (((x) & BIT_MASK_EPVID1_8822B) << BIT_SHIFT_EPVID1_8822B) +#define BITS_EPVID1_8822B (BIT_MASK_EPVID1_8822B << BIT_SHIFT_EPVID1_8822B) +#define BIT_CLEAR_EPVID1_8822B(x) ((x) & (~BITS_EPVID1_8822B)) +#define BIT_GET_EPVID1_8822B(x) \ + (((x) >> BIT_SHIFT_EPVID1_8822B) & BIT_MASK_EPVID1_8822B) +#define BIT_SET_EPVID1_8822B(x, v) \ + (BIT_CLEAR_EPVID1_8822B(x) | BIT_EPVID1_8822B(v)) #define BIT_SHIFT_EPVID0_8822B 0 #define BIT_MASK_EPVID0_8822B 0xff -#define BIT_EPVID0_8822B(x) (((x) & BIT_MASK_EPVID0_8822B) << BIT_SHIFT_EPVID0_8822B) -#define BIT_GET_EPVID0_8822B(x) (((x) >> BIT_SHIFT_EPVID0_8822B) & BIT_MASK_EPVID0_8822B) - - +#define BIT_EPVID0_8822B(x) \ + (((x) & BIT_MASK_EPVID0_8822B) << BIT_SHIFT_EPVID0_8822B) +#define BITS_EPVID0_8822B (BIT_MASK_EPVID0_8822B << BIT_SHIFT_EPVID0_8822B) +#define BIT_CLEAR_EPVID0_8822B(x) ((x) & (~BITS_EPVID0_8822B)) +#define BIT_GET_EPVID0_8822B(x) \ + (((x) >> BIT_SHIFT_EPVID0_8822B) & BIT_MASK_EPVID0_8822B) +#define BIT_SET_EPVID0_8822B(x, v) \ + (BIT_CLEAR_EPVID0_8822B(x) | BIT_EPVID0_8822B(v)) /* 2 REG_SYS_CFG2_8822B */ -#define BIT_HCI_SEL_EMBEDED_8822B BIT(8) +#define BIT_HCI_SEL_EMBEDDED_8822B BIT(8) #define BIT_SHIFT_HW_ID_8822B 0 #define BIT_MASK_HW_ID_8822B 0xff -#define BIT_HW_ID_8822B(x) (((x) & BIT_MASK_HW_ID_8822B) << BIT_SHIFT_HW_ID_8822B) -#define BIT_GET_HW_ID_8822B(x) (((x) >> BIT_SHIFT_HW_ID_8822B) & BIT_MASK_HW_ID_8822B) - - +#define BIT_HW_ID_8822B(x) \ + (((x) & BIT_MASK_HW_ID_8822B) << BIT_SHIFT_HW_ID_8822B) +#define BITS_HW_ID_8822B (BIT_MASK_HW_ID_8822B << BIT_SHIFT_HW_ID_8822B) +#define BIT_CLEAR_HW_ID_8822B(x) ((x) & (~BITS_HW_ID_8822B)) +#define BIT_GET_HW_ID_8822B(x) \ + (((x) >> BIT_SHIFT_HW_ID_8822B) & BIT_MASK_HW_ID_8822B) +#define BIT_SET_HW_ID_8822B(x, v) \ + (BIT_CLEAR_HW_ID_8822B(x) | BIT_HW_ID_8822B(v)) /* 2 REG_SYS_CFG3_8822B */ #define BIT_PWC_MA33V_8822B BIT(15) @@ -1800,19 +2625,31 @@ #define BIT_SHIFT_CPU_DMEM_CON_8822B 0 #define BIT_MASK_CPU_DMEM_CON_8822B 0xff -#define BIT_CPU_DMEM_CON_8822B(x) (((x) & BIT_MASK_CPU_DMEM_CON_8822B) << BIT_SHIFT_CPU_DMEM_CON_8822B) -#define BIT_GET_CPU_DMEM_CON_8822B(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8822B) & BIT_MASK_CPU_DMEM_CON_8822B) - - +#define BIT_CPU_DMEM_CON_8822B(x) \ + (((x) & BIT_MASK_CPU_DMEM_CON_8822B) << BIT_SHIFT_CPU_DMEM_CON_8822B) +#define BITS_CPU_DMEM_CON_8822B \ + (BIT_MASK_CPU_DMEM_CON_8822B << BIT_SHIFT_CPU_DMEM_CON_8822B) +#define BIT_CLEAR_CPU_DMEM_CON_8822B(x) ((x) & (~BITS_CPU_DMEM_CON_8822B)) +#define BIT_GET_CPU_DMEM_CON_8822B(x) \ + (((x) >> BIT_SHIFT_CPU_DMEM_CON_8822B) & BIT_MASK_CPU_DMEM_CON_8822B) +#define BIT_SET_CPU_DMEM_CON_8822B(x, v) \ + (BIT_CLEAR_CPU_DMEM_CON_8822B(x) | BIT_CPU_DMEM_CON_8822B(v)) /* 2 REG_BOOT_REASON_8822B */ -#define BIT_SHIFT_BOOT_REASON_8822B 0 -#define BIT_MASK_BOOT_REASON_8822B 0x7 -#define BIT_BOOT_REASON_8822B(x) (((x) & BIT_MASK_BOOT_REASON_8822B) << BIT_SHIFT_BOOT_REASON_8822B) -#define BIT_GET_BOOT_REASON_8822B(x) (((x) >> BIT_SHIFT_BOOT_REASON_8822B) & BIT_MASK_BOOT_REASON_8822B) - - +#define BIT_SHIFT_BOOT_REASON_V1_8822B 0 +#define BIT_MASK_BOOT_REASON_V1_8822B 0x7 +#define BIT_BOOT_REASON_V1_8822B(x) \ + (((x) & BIT_MASK_BOOT_REASON_V1_8822B) \ + << BIT_SHIFT_BOOT_REASON_V1_8822B) +#define BITS_BOOT_REASON_V1_8822B \ + (BIT_MASK_BOOT_REASON_V1_8822B << BIT_SHIFT_BOOT_REASON_V1_8822B) +#define BIT_CLEAR_BOOT_REASON_V1_8822B(x) ((x) & (~BITS_BOOT_REASON_V1_8822B)) +#define BIT_GET_BOOT_REASON_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BOOT_REASON_V1_8822B) & \ + BIT_MASK_BOOT_REASON_V1_8822B) +#define BIT_SET_BOOT_REASON_V1_8822B(x, v) \ + (BIT_CLEAR_BOOT_REASON_V1_8822B(x) | BIT_BOOT_REASON_V1_8822B(v)) /* 2 REG_NFCPAD_CTRL_8822B */ #define BIT_PAD_SHUTDW_8822B BIT(18) @@ -1825,24 +2662,39 @@ #define BIT_SHIFT_NFCPAD_IO_SEL_8822B 8 #define BIT_MASK_NFCPAD_IO_SEL_8822B 0xf -#define BIT_NFCPAD_IO_SEL_8822B(x) (((x) & BIT_MASK_NFCPAD_IO_SEL_8822B) << BIT_SHIFT_NFCPAD_IO_SEL_8822B) -#define BIT_GET_NFCPAD_IO_SEL_8822B(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8822B) & BIT_MASK_NFCPAD_IO_SEL_8822B) - - +#define BIT_NFCPAD_IO_SEL_8822B(x) \ + (((x) & BIT_MASK_NFCPAD_IO_SEL_8822B) << BIT_SHIFT_NFCPAD_IO_SEL_8822B) +#define BITS_NFCPAD_IO_SEL_8822B \ + (BIT_MASK_NFCPAD_IO_SEL_8822B << BIT_SHIFT_NFCPAD_IO_SEL_8822B) +#define BIT_CLEAR_NFCPAD_IO_SEL_8822B(x) ((x) & (~BITS_NFCPAD_IO_SEL_8822B)) +#define BIT_GET_NFCPAD_IO_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8822B) & BIT_MASK_NFCPAD_IO_SEL_8822B) +#define BIT_SET_NFCPAD_IO_SEL_8822B(x, v) \ + (BIT_CLEAR_NFCPAD_IO_SEL_8822B(x) | BIT_NFCPAD_IO_SEL_8822B(v)) #define BIT_SHIFT_NFCPAD_OUT_8822B 4 #define BIT_MASK_NFCPAD_OUT_8822B 0xf -#define BIT_NFCPAD_OUT_8822B(x) (((x) & BIT_MASK_NFCPAD_OUT_8822B) << BIT_SHIFT_NFCPAD_OUT_8822B) -#define BIT_GET_NFCPAD_OUT_8822B(x) (((x) >> BIT_SHIFT_NFCPAD_OUT_8822B) & BIT_MASK_NFCPAD_OUT_8822B) - - +#define BIT_NFCPAD_OUT_8822B(x) \ + (((x) & BIT_MASK_NFCPAD_OUT_8822B) << BIT_SHIFT_NFCPAD_OUT_8822B) +#define BITS_NFCPAD_OUT_8822B \ + (BIT_MASK_NFCPAD_OUT_8822B << BIT_SHIFT_NFCPAD_OUT_8822B) +#define BIT_CLEAR_NFCPAD_OUT_8822B(x) ((x) & (~BITS_NFCPAD_OUT_8822B)) +#define BIT_GET_NFCPAD_OUT_8822B(x) \ + (((x) >> BIT_SHIFT_NFCPAD_OUT_8822B) & BIT_MASK_NFCPAD_OUT_8822B) +#define BIT_SET_NFCPAD_OUT_8822B(x, v) \ + (BIT_CLEAR_NFCPAD_OUT_8822B(x) | BIT_NFCPAD_OUT_8822B(v)) #define BIT_SHIFT_NFCPAD_IN_8822B 0 #define BIT_MASK_NFCPAD_IN_8822B 0xf -#define BIT_NFCPAD_IN_8822B(x) (((x) & BIT_MASK_NFCPAD_IN_8822B) << BIT_SHIFT_NFCPAD_IN_8822B) -#define BIT_GET_NFCPAD_IN_8822B(x) (((x) >> BIT_SHIFT_NFCPAD_IN_8822B) & BIT_MASK_NFCPAD_IN_8822B) - - +#define BIT_NFCPAD_IN_8822B(x) \ + (((x) & BIT_MASK_NFCPAD_IN_8822B) << BIT_SHIFT_NFCPAD_IN_8822B) +#define BITS_NFCPAD_IN_8822B \ + (BIT_MASK_NFCPAD_IN_8822B << BIT_SHIFT_NFCPAD_IN_8822B) +#define BIT_CLEAR_NFCPAD_IN_8822B(x) ((x) & (~BITS_NFCPAD_IN_8822B)) +#define BIT_GET_NFCPAD_IN_8822B(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IN_8822B) & BIT_MASK_NFCPAD_IN_8822B) +#define BIT_SET_NFCPAD_IN_8822B(x, v) \ + (BIT_CLEAR_NFCPAD_IN_8822B(x) | BIT_NFCPAD_IN_8822B(v)) /* 2 REG_HIMR2_8822B */ #define BIT_BCNDMAINT_P4_MSK_8822B BIT(31) @@ -1962,19 +2814,35 @@ #define BIT_SHIFT_H2C_PKT_READADDR_8822B 0 #define BIT_MASK_H2C_PKT_READADDR_8822B 0x3ffff -#define BIT_H2C_PKT_READADDR_8822B(x) (((x) & BIT_MASK_H2C_PKT_READADDR_8822B) << BIT_SHIFT_H2C_PKT_READADDR_8822B) -#define BIT_GET_H2C_PKT_READADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822B) & BIT_MASK_H2C_PKT_READADDR_8822B) - - +#define BIT_H2C_PKT_READADDR_8822B(x) \ + (((x) & BIT_MASK_H2C_PKT_READADDR_8822B) \ + << BIT_SHIFT_H2C_PKT_READADDR_8822B) +#define BITS_H2C_PKT_READADDR_8822B \ + (BIT_MASK_H2C_PKT_READADDR_8822B << BIT_SHIFT_H2C_PKT_READADDR_8822B) +#define BIT_CLEAR_H2C_PKT_READADDR_8822B(x) \ + ((x) & (~BITS_H2C_PKT_READADDR_8822B)) +#define BIT_GET_H2C_PKT_READADDR_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822B) & \ + BIT_MASK_H2C_PKT_READADDR_8822B) +#define BIT_SET_H2C_PKT_READADDR_8822B(x, v) \ + (BIT_CLEAR_H2C_PKT_READADDR_8822B(x) | BIT_H2C_PKT_READADDR_8822B(v)) /* 2 REG_H2C_PKT_WRITEADDR_8822B */ #define BIT_SHIFT_H2C_PKT_WRITEADDR_8822B 0 #define BIT_MASK_H2C_PKT_WRITEADDR_8822B 0x3ffff -#define BIT_H2C_PKT_WRITEADDR_8822B(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822B) << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) -#define BIT_GET_H2C_PKT_WRITEADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) & BIT_MASK_H2C_PKT_WRITEADDR_8822B) - - +#define BIT_H2C_PKT_WRITEADDR_8822B(x) \ + (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822B) \ + << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) +#define BITS_H2C_PKT_WRITEADDR_8822B \ + (BIT_MASK_H2C_PKT_WRITEADDR_8822B << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) +#define BIT_CLEAR_H2C_PKT_WRITEADDR_8822B(x) \ + ((x) & (~BITS_H2C_PKT_WRITEADDR_8822B)) +#define BIT_GET_H2C_PKT_WRITEADDR_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) & \ + BIT_MASK_H2C_PKT_WRITEADDR_8822B) +#define BIT_SET_H2C_PKT_WRITEADDR_8822B(x, v) \ + (BIT_CLEAR_H2C_PKT_WRITEADDR_8822B(x) | BIT_H2C_PKT_WRITEADDR_8822B(v)) /* 2 REG_MEM_PWR_CRTL_8822B */ #define BIT_MEM_BB_SD_8822B BIT(17) @@ -1995,73 +2863,105 @@ #define BIT_SHIFT_FW_DBG0_8822B 0 #define BIT_MASK_FW_DBG0_8822B 0xffffffffL -#define BIT_FW_DBG0_8822B(x) (((x) & BIT_MASK_FW_DBG0_8822B) << BIT_SHIFT_FW_DBG0_8822B) -#define BIT_GET_FW_DBG0_8822B(x) (((x) >> BIT_SHIFT_FW_DBG0_8822B) & BIT_MASK_FW_DBG0_8822B) - - +#define BIT_FW_DBG0_8822B(x) \ + (((x) & BIT_MASK_FW_DBG0_8822B) << BIT_SHIFT_FW_DBG0_8822B) +#define BITS_FW_DBG0_8822B (BIT_MASK_FW_DBG0_8822B << BIT_SHIFT_FW_DBG0_8822B) +#define BIT_CLEAR_FW_DBG0_8822B(x) ((x) & (~BITS_FW_DBG0_8822B)) +#define BIT_GET_FW_DBG0_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG0_8822B) & BIT_MASK_FW_DBG0_8822B) +#define BIT_SET_FW_DBG0_8822B(x, v) \ + (BIT_CLEAR_FW_DBG0_8822B(x) | BIT_FW_DBG0_8822B(v)) /* 2 REG_FW_DBG1_8822B */ #define BIT_SHIFT_FW_DBG1_8822B 0 #define BIT_MASK_FW_DBG1_8822B 0xffffffffL -#define BIT_FW_DBG1_8822B(x) (((x) & BIT_MASK_FW_DBG1_8822B) << BIT_SHIFT_FW_DBG1_8822B) -#define BIT_GET_FW_DBG1_8822B(x) (((x) >> BIT_SHIFT_FW_DBG1_8822B) & BIT_MASK_FW_DBG1_8822B) - - +#define BIT_FW_DBG1_8822B(x) \ + (((x) & BIT_MASK_FW_DBG1_8822B) << BIT_SHIFT_FW_DBG1_8822B) +#define BITS_FW_DBG1_8822B (BIT_MASK_FW_DBG1_8822B << BIT_SHIFT_FW_DBG1_8822B) +#define BIT_CLEAR_FW_DBG1_8822B(x) ((x) & (~BITS_FW_DBG1_8822B)) +#define BIT_GET_FW_DBG1_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG1_8822B) & BIT_MASK_FW_DBG1_8822B) +#define BIT_SET_FW_DBG1_8822B(x, v) \ + (BIT_CLEAR_FW_DBG1_8822B(x) | BIT_FW_DBG1_8822B(v)) /* 2 REG_FW_DBG2_8822B */ #define BIT_SHIFT_FW_DBG2_8822B 0 #define BIT_MASK_FW_DBG2_8822B 0xffffffffL -#define BIT_FW_DBG2_8822B(x) (((x) & BIT_MASK_FW_DBG2_8822B) << BIT_SHIFT_FW_DBG2_8822B) -#define BIT_GET_FW_DBG2_8822B(x) (((x) >> BIT_SHIFT_FW_DBG2_8822B) & BIT_MASK_FW_DBG2_8822B) - - +#define BIT_FW_DBG2_8822B(x) \ + (((x) & BIT_MASK_FW_DBG2_8822B) << BIT_SHIFT_FW_DBG2_8822B) +#define BITS_FW_DBG2_8822B (BIT_MASK_FW_DBG2_8822B << BIT_SHIFT_FW_DBG2_8822B) +#define BIT_CLEAR_FW_DBG2_8822B(x) ((x) & (~BITS_FW_DBG2_8822B)) +#define BIT_GET_FW_DBG2_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG2_8822B) & BIT_MASK_FW_DBG2_8822B) +#define BIT_SET_FW_DBG2_8822B(x, v) \ + (BIT_CLEAR_FW_DBG2_8822B(x) | BIT_FW_DBG2_8822B(v)) /* 2 REG_FW_DBG3_8822B */ #define BIT_SHIFT_FW_DBG3_8822B 0 #define BIT_MASK_FW_DBG3_8822B 0xffffffffL -#define BIT_FW_DBG3_8822B(x) (((x) & BIT_MASK_FW_DBG3_8822B) << BIT_SHIFT_FW_DBG3_8822B) -#define BIT_GET_FW_DBG3_8822B(x) (((x) >> BIT_SHIFT_FW_DBG3_8822B) & BIT_MASK_FW_DBG3_8822B) - - +#define BIT_FW_DBG3_8822B(x) \ + (((x) & BIT_MASK_FW_DBG3_8822B) << BIT_SHIFT_FW_DBG3_8822B) +#define BITS_FW_DBG3_8822B (BIT_MASK_FW_DBG3_8822B << BIT_SHIFT_FW_DBG3_8822B) +#define BIT_CLEAR_FW_DBG3_8822B(x) ((x) & (~BITS_FW_DBG3_8822B)) +#define BIT_GET_FW_DBG3_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG3_8822B) & BIT_MASK_FW_DBG3_8822B) +#define BIT_SET_FW_DBG3_8822B(x, v) \ + (BIT_CLEAR_FW_DBG3_8822B(x) | BIT_FW_DBG3_8822B(v)) /* 2 REG_FW_DBG4_8822B */ #define BIT_SHIFT_FW_DBG4_8822B 0 #define BIT_MASK_FW_DBG4_8822B 0xffffffffL -#define BIT_FW_DBG4_8822B(x) (((x) & BIT_MASK_FW_DBG4_8822B) << BIT_SHIFT_FW_DBG4_8822B) -#define BIT_GET_FW_DBG4_8822B(x) (((x) >> BIT_SHIFT_FW_DBG4_8822B) & BIT_MASK_FW_DBG4_8822B) - - +#define BIT_FW_DBG4_8822B(x) \ + (((x) & BIT_MASK_FW_DBG4_8822B) << BIT_SHIFT_FW_DBG4_8822B) +#define BITS_FW_DBG4_8822B (BIT_MASK_FW_DBG4_8822B << BIT_SHIFT_FW_DBG4_8822B) +#define BIT_CLEAR_FW_DBG4_8822B(x) ((x) & (~BITS_FW_DBG4_8822B)) +#define BIT_GET_FW_DBG4_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG4_8822B) & BIT_MASK_FW_DBG4_8822B) +#define BIT_SET_FW_DBG4_8822B(x, v) \ + (BIT_CLEAR_FW_DBG4_8822B(x) | BIT_FW_DBG4_8822B(v)) /* 2 REG_FW_DBG5_8822B */ #define BIT_SHIFT_FW_DBG5_8822B 0 #define BIT_MASK_FW_DBG5_8822B 0xffffffffL -#define BIT_FW_DBG5_8822B(x) (((x) & BIT_MASK_FW_DBG5_8822B) << BIT_SHIFT_FW_DBG5_8822B) -#define BIT_GET_FW_DBG5_8822B(x) (((x) >> BIT_SHIFT_FW_DBG5_8822B) & BIT_MASK_FW_DBG5_8822B) - - +#define BIT_FW_DBG5_8822B(x) \ + (((x) & BIT_MASK_FW_DBG5_8822B) << BIT_SHIFT_FW_DBG5_8822B) +#define BITS_FW_DBG5_8822B (BIT_MASK_FW_DBG5_8822B << BIT_SHIFT_FW_DBG5_8822B) +#define BIT_CLEAR_FW_DBG5_8822B(x) ((x) & (~BITS_FW_DBG5_8822B)) +#define BIT_GET_FW_DBG5_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG5_8822B) & BIT_MASK_FW_DBG5_8822B) +#define BIT_SET_FW_DBG5_8822B(x, v) \ + (BIT_CLEAR_FW_DBG5_8822B(x) | BIT_FW_DBG5_8822B(v)) /* 2 REG_FW_DBG6_8822B */ #define BIT_SHIFT_FW_DBG6_8822B 0 #define BIT_MASK_FW_DBG6_8822B 0xffffffffL -#define BIT_FW_DBG6_8822B(x) (((x) & BIT_MASK_FW_DBG6_8822B) << BIT_SHIFT_FW_DBG6_8822B) -#define BIT_GET_FW_DBG6_8822B(x) (((x) >> BIT_SHIFT_FW_DBG6_8822B) & BIT_MASK_FW_DBG6_8822B) - - +#define BIT_FW_DBG6_8822B(x) \ + (((x) & BIT_MASK_FW_DBG6_8822B) << BIT_SHIFT_FW_DBG6_8822B) +#define BITS_FW_DBG6_8822B (BIT_MASK_FW_DBG6_8822B << BIT_SHIFT_FW_DBG6_8822B) +#define BIT_CLEAR_FW_DBG6_8822B(x) ((x) & (~BITS_FW_DBG6_8822B)) +#define BIT_GET_FW_DBG6_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG6_8822B) & BIT_MASK_FW_DBG6_8822B) +#define BIT_SET_FW_DBG6_8822B(x, v) \ + (BIT_CLEAR_FW_DBG6_8822B(x) | BIT_FW_DBG6_8822B(v)) /* 2 REG_FW_DBG7_8822B */ #define BIT_SHIFT_FW_DBG7_8822B 0 #define BIT_MASK_FW_DBG7_8822B 0xffffffffL -#define BIT_FW_DBG7_8822B(x) (((x) & BIT_MASK_FW_DBG7_8822B) << BIT_SHIFT_FW_DBG7_8822B) -#define BIT_GET_FW_DBG7_8822B(x) (((x) >> BIT_SHIFT_FW_DBG7_8822B) & BIT_MASK_FW_DBG7_8822B) - - +#define BIT_FW_DBG7_8822B(x) \ + (((x) & BIT_MASK_FW_DBG7_8822B) << BIT_SHIFT_FW_DBG7_8822B) +#define BITS_FW_DBG7_8822B (BIT_MASK_FW_DBG7_8822B << BIT_SHIFT_FW_DBG7_8822B) +#define BIT_CLEAR_FW_DBG7_8822B(x) ((x) & (~BITS_FW_DBG7_8822B)) +#define BIT_GET_FW_DBG7_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG7_8822B) & BIT_MASK_FW_DBG7_8822B) +#define BIT_SET_FW_DBG7_8822B(x, v) \ + (BIT_CLEAR_FW_DBG7_8822B(x) | BIT_FW_DBG7_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -2069,23 +2969,36 @@ #define BIT_SHIFT_LBMODE_8822B 24 #define BIT_MASK_LBMODE_8822B 0x1f -#define BIT_LBMODE_8822B(x) (((x) & BIT_MASK_LBMODE_8822B) << BIT_SHIFT_LBMODE_8822B) -#define BIT_GET_LBMODE_8822B(x) (((x) >> BIT_SHIFT_LBMODE_8822B) & BIT_MASK_LBMODE_8822B) - - +#define BIT_LBMODE_8822B(x) \ + (((x) & BIT_MASK_LBMODE_8822B) << BIT_SHIFT_LBMODE_8822B) +#define BITS_LBMODE_8822B (BIT_MASK_LBMODE_8822B << BIT_SHIFT_LBMODE_8822B) +#define BIT_CLEAR_LBMODE_8822B(x) ((x) & (~BITS_LBMODE_8822B)) +#define BIT_GET_LBMODE_8822B(x) \ + (((x) >> BIT_SHIFT_LBMODE_8822B) & BIT_MASK_LBMODE_8822B) +#define BIT_SET_LBMODE_8822B(x, v) \ + (BIT_CLEAR_LBMODE_8822B(x) | BIT_LBMODE_8822B(v)) #define BIT_SHIFT_NETYPE1_8822B 18 #define BIT_MASK_NETYPE1_8822B 0x3 -#define BIT_NETYPE1_8822B(x) (((x) & BIT_MASK_NETYPE1_8822B) << BIT_SHIFT_NETYPE1_8822B) -#define BIT_GET_NETYPE1_8822B(x) (((x) >> BIT_SHIFT_NETYPE1_8822B) & BIT_MASK_NETYPE1_8822B) - - +#define BIT_NETYPE1_8822B(x) \ + (((x) & BIT_MASK_NETYPE1_8822B) << BIT_SHIFT_NETYPE1_8822B) +#define BITS_NETYPE1_8822B (BIT_MASK_NETYPE1_8822B << BIT_SHIFT_NETYPE1_8822B) +#define BIT_CLEAR_NETYPE1_8822B(x) ((x) & (~BITS_NETYPE1_8822B)) +#define BIT_GET_NETYPE1_8822B(x) \ + (((x) >> BIT_SHIFT_NETYPE1_8822B) & BIT_MASK_NETYPE1_8822B) +#define BIT_SET_NETYPE1_8822B(x, v) \ + (BIT_CLEAR_NETYPE1_8822B(x) | BIT_NETYPE1_8822B(v)) #define BIT_SHIFT_NETYPE0_8822B 16 #define BIT_MASK_NETYPE0_8822B 0x3 -#define BIT_NETYPE0_8822B(x) (((x) & BIT_MASK_NETYPE0_8822B) << BIT_SHIFT_NETYPE0_8822B) -#define BIT_GET_NETYPE0_8822B(x) (((x) >> BIT_SHIFT_NETYPE0_8822B) & BIT_MASK_NETYPE0_8822B) - +#define BIT_NETYPE0_8822B(x) \ + (((x) & BIT_MASK_NETYPE0_8822B) << BIT_SHIFT_NETYPE0_8822B) +#define BITS_NETYPE0_8822B (BIT_MASK_NETYPE0_8822B << BIT_SHIFT_NETYPE0_8822B) +#define BIT_CLEAR_NETYPE0_8822B(x) ((x) & (~BITS_NETYPE0_8822B)) +#define BIT_GET_NETYPE0_8822B(x) \ + (((x) >> BIT_SHIFT_NETYPE0_8822B) & BIT_MASK_NETYPE0_8822B) +#define BIT_SET_NETYPE0_8822B(x, v) \ + (BIT_CLEAR_NETYPE0_8822B(x) | BIT_NETYPE0_8822B(v)) #define BIT_I2C_MAILBOX_EN_8822B BIT(12) #define BIT_SHCUT_EN_8822B BIT(11) @@ -2101,15 +3014,6 @@ #define BIT_HCI_RXDMA_EN_8822B BIT(1) #define BIT_HCI_TXDMA_EN_8822B BIT(0) -/* 2 REG_PKT_BUFF_ACCESS_CTRL_8822B */ - -#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822B 0 -#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822B 0xff -#define BIT_PKT_BUFF_ACCESS_CTRL_8822B(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822B) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822B) -#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8822B(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822B) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822B) - - - /* 2 REG_TSF_CLK_STATE_8822B */ #define BIT_TSF_CLK_STABLE_8822B BIT(15) @@ -2117,44 +3021,75 @@ #define BIT_SHIFT_TXDMA_HIQ_MAP_8822B 14 #define BIT_MASK_TXDMA_HIQ_MAP_8822B 0x3 -#define BIT_TXDMA_HIQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8822B) << BIT_SHIFT_TXDMA_HIQ_MAP_8822B) -#define BIT_GET_TXDMA_HIQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822B) & BIT_MASK_TXDMA_HIQ_MAP_8822B) - - +#define BIT_TXDMA_HIQ_MAP_8822B(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP_8822B) << BIT_SHIFT_TXDMA_HIQ_MAP_8822B) +#define BITS_TXDMA_HIQ_MAP_8822B \ + (BIT_MASK_TXDMA_HIQ_MAP_8822B << BIT_SHIFT_TXDMA_HIQ_MAP_8822B) +#define BIT_CLEAR_TXDMA_HIQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8822B)) +#define BIT_GET_TXDMA_HIQ_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822B) & BIT_MASK_TXDMA_HIQ_MAP_8822B) +#define BIT_SET_TXDMA_HIQ_MAP_8822B(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP_8822B(x) | BIT_TXDMA_HIQ_MAP_8822B(v)) #define BIT_SHIFT_TXDMA_MGQ_MAP_8822B 12 #define BIT_MASK_TXDMA_MGQ_MAP_8822B 0x3 -#define BIT_TXDMA_MGQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8822B) << BIT_SHIFT_TXDMA_MGQ_MAP_8822B) -#define BIT_GET_TXDMA_MGQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822B) & BIT_MASK_TXDMA_MGQ_MAP_8822B) - - +#define BIT_TXDMA_MGQ_MAP_8822B(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP_8822B) << BIT_SHIFT_TXDMA_MGQ_MAP_8822B) +#define BITS_TXDMA_MGQ_MAP_8822B \ + (BIT_MASK_TXDMA_MGQ_MAP_8822B << BIT_SHIFT_TXDMA_MGQ_MAP_8822B) +#define BIT_CLEAR_TXDMA_MGQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8822B)) +#define BIT_GET_TXDMA_MGQ_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822B) & BIT_MASK_TXDMA_MGQ_MAP_8822B) +#define BIT_SET_TXDMA_MGQ_MAP_8822B(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP_8822B(x) | BIT_TXDMA_MGQ_MAP_8822B(v)) #define BIT_SHIFT_TXDMA_BKQ_MAP_8822B 10 #define BIT_MASK_TXDMA_BKQ_MAP_8822B 0x3 -#define BIT_TXDMA_BKQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8822B) << BIT_SHIFT_TXDMA_BKQ_MAP_8822B) -#define BIT_GET_TXDMA_BKQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822B) & BIT_MASK_TXDMA_BKQ_MAP_8822B) - - +#define BIT_TXDMA_BKQ_MAP_8822B(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP_8822B) << BIT_SHIFT_TXDMA_BKQ_MAP_8822B) +#define BITS_TXDMA_BKQ_MAP_8822B \ + (BIT_MASK_TXDMA_BKQ_MAP_8822B << BIT_SHIFT_TXDMA_BKQ_MAP_8822B) +#define BIT_CLEAR_TXDMA_BKQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8822B)) +#define BIT_GET_TXDMA_BKQ_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822B) & BIT_MASK_TXDMA_BKQ_MAP_8822B) +#define BIT_SET_TXDMA_BKQ_MAP_8822B(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP_8822B(x) | BIT_TXDMA_BKQ_MAP_8822B(v)) #define BIT_SHIFT_TXDMA_BEQ_MAP_8822B 8 #define BIT_MASK_TXDMA_BEQ_MAP_8822B 0x3 -#define BIT_TXDMA_BEQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8822B) << BIT_SHIFT_TXDMA_BEQ_MAP_8822B) -#define BIT_GET_TXDMA_BEQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822B) & BIT_MASK_TXDMA_BEQ_MAP_8822B) - - +#define BIT_TXDMA_BEQ_MAP_8822B(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP_8822B) << BIT_SHIFT_TXDMA_BEQ_MAP_8822B) +#define BITS_TXDMA_BEQ_MAP_8822B \ + (BIT_MASK_TXDMA_BEQ_MAP_8822B << BIT_SHIFT_TXDMA_BEQ_MAP_8822B) +#define BIT_CLEAR_TXDMA_BEQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8822B)) +#define BIT_GET_TXDMA_BEQ_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822B) & BIT_MASK_TXDMA_BEQ_MAP_8822B) +#define BIT_SET_TXDMA_BEQ_MAP_8822B(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP_8822B(x) | BIT_TXDMA_BEQ_MAP_8822B(v)) #define BIT_SHIFT_TXDMA_VIQ_MAP_8822B 6 #define BIT_MASK_TXDMA_VIQ_MAP_8822B 0x3 -#define BIT_TXDMA_VIQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8822B) << BIT_SHIFT_TXDMA_VIQ_MAP_8822B) -#define BIT_GET_TXDMA_VIQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822B) & BIT_MASK_TXDMA_VIQ_MAP_8822B) - - +#define BIT_TXDMA_VIQ_MAP_8822B(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP_8822B) << BIT_SHIFT_TXDMA_VIQ_MAP_8822B) +#define BITS_TXDMA_VIQ_MAP_8822B \ + (BIT_MASK_TXDMA_VIQ_MAP_8822B << BIT_SHIFT_TXDMA_VIQ_MAP_8822B) +#define BIT_CLEAR_TXDMA_VIQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8822B)) +#define BIT_GET_TXDMA_VIQ_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822B) & BIT_MASK_TXDMA_VIQ_MAP_8822B) +#define BIT_SET_TXDMA_VIQ_MAP_8822B(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP_8822B(x) | BIT_TXDMA_VIQ_MAP_8822B(v)) #define BIT_SHIFT_TXDMA_VOQ_MAP_8822B 4 #define BIT_MASK_TXDMA_VOQ_MAP_8822B 0x3 -#define BIT_TXDMA_VOQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8822B) << BIT_SHIFT_TXDMA_VOQ_MAP_8822B) -#define BIT_GET_TXDMA_VOQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822B) & BIT_MASK_TXDMA_VOQ_MAP_8822B) - +#define BIT_TXDMA_VOQ_MAP_8822B(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP_8822B) << BIT_SHIFT_TXDMA_VOQ_MAP_8822B) +#define BITS_TXDMA_VOQ_MAP_8822B \ + (BIT_MASK_TXDMA_VOQ_MAP_8822B << BIT_SHIFT_TXDMA_VOQ_MAP_8822B) +#define BIT_CLEAR_TXDMA_VOQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8822B)) +#define BIT_GET_TXDMA_VOQ_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822B) & BIT_MASK_TXDMA_VOQ_MAP_8822B) +#define BIT_SET_TXDMA_VOQ_MAP_8822B(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP_8822B(x) | BIT_TXDMA_VOQ_MAP_8822B(v)) #define BIT_RXDMA_AGG_EN_8822B BIT(2) #define BIT_RXSHFT_EN_8822B BIT(1) @@ -2164,17 +3099,31 @@ #define BIT_SHIFT_RXFFOVFL_RSV_V2_8822B 8 #define BIT_MASK_RXFFOVFL_RSV_V2_8822B 0xf -#define BIT_RXFFOVFL_RSV_V2_8822B(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822B) << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) -#define BIT_GET_RXFFOVFL_RSV_V2_8822B(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) & BIT_MASK_RXFFOVFL_RSV_V2_8822B) - - +#define BIT_RXFFOVFL_RSV_V2_8822B(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822B) \ + << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) +#define BITS_RXFFOVFL_RSV_V2_8822B \ + (BIT_MASK_RXFFOVFL_RSV_V2_8822B << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) +#define BIT_CLEAR_RXFFOVFL_RSV_V2_8822B(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8822B)) +#define BIT_GET_RXFFOVFL_RSV_V2_8822B(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) & \ + BIT_MASK_RXFFOVFL_RSV_V2_8822B) +#define BIT_SET_RXFFOVFL_RSV_V2_8822B(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V2_8822B(x) | BIT_RXFFOVFL_RSV_V2_8822B(v)) #define BIT_SHIFT_TXPKTBUF_PGBNDY_8822B 0 #define BIT_MASK_TXPKTBUF_PGBNDY_8822B 0xff -#define BIT_TXPKTBUF_PGBNDY_8822B(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8822B) << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) -#define BIT_GET_TXPKTBUF_PGBNDY_8822B(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) & BIT_MASK_TXPKTBUF_PGBNDY_8822B) - - +#define BIT_TXPKTBUF_PGBNDY_8822B(x) \ + (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8822B) \ + << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) +#define BITS_TXPKTBUF_PGBNDY_8822B \ + (BIT_MASK_TXPKTBUF_PGBNDY_8822B << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) +#define BIT_CLEAR_TXPKTBUF_PGBNDY_8822B(x) ((x) & (~BITS_TXPKTBUF_PGBNDY_8822B)) +#define BIT_GET_TXPKTBUF_PGBNDY_8822B(x) \ + (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) & \ + BIT_MASK_TXPKTBUF_PGBNDY_8822B) +#define BIT_SET_TXPKTBUF_PGBNDY_8822B(x, v) \ + (BIT_CLEAR_TXPKTBUF_PGBNDY_8822B(x) | BIT_TXPKTBUF_PGBNDY_8822B(v)) /* 2 REG_PTA_I2C_MBOX_8822B */ @@ -2182,24 +3131,44 @@ #define BIT_SHIFT_I2C_M_STATUS_8822B 8 #define BIT_MASK_I2C_M_STATUS_8822B 0xf -#define BIT_I2C_M_STATUS_8822B(x) (((x) & BIT_MASK_I2C_M_STATUS_8822B) << BIT_SHIFT_I2C_M_STATUS_8822B) -#define BIT_GET_I2C_M_STATUS_8822B(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8822B) & BIT_MASK_I2C_M_STATUS_8822B) - - +#define BIT_I2C_M_STATUS_8822B(x) \ + (((x) & BIT_MASK_I2C_M_STATUS_8822B) << BIT_SHIFT_I2C_M_STATUS_8822B) +#define BITS_I2C_M_STATUS_8822B \ + (BIT_MASK_I2C_M_STATUS_8822B << BIT_SHIFT_I2C_M_STATUS_8822B) +#define BIT_CLEAR_I2C_M_STATUS_8822B(x) ((x) & (~BITS_I2C_M_STATUS_8822B)) +#define BIT_GET_I2C_M_STATUS_8822B(x) \ + (((x) >> BIT_SHIFT_I2C_M_STATUS_8822B) & BIT_MASK_I2C_M_STATUS_8822B) +#define BIT_SET_I2C_M_STATUS_8822B(x, v) \ + (BIT_CLEAR_I2C_M_STATUS_8822B(x) | BIT_I2C_M_STATUS_8822B(v)) #define BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B 4 #define BIT_MASK_I2C_M_BUS_GNT_FW_8822B 0x7 -#define BIT_I2C_M_BUS_GNT_FW_8822B(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) -#define BIT_GET_I2C_M_BUS_GNT_FW_8822B(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B) - +#define BIT_I2C_M_BUS_GNT_FW_8822B(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B) \ + << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) +#define BITS_I2C_M_BUS_GNT_FW_8822B \ + (BIT_MASK_I2C_M_BUS_GNT_FW_8822B << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8822B(x) \ + ((x) & (~BITS_I2C_M_BUS_GNT_FW_8822B)) +#define BIT_GET_I2C_M_BUS_GNT_FW_8822B(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) & \ + BIT_MASK_I2C_M_BUS_GNT_FW_8822B) +#define BIT_SET_I2C_M_BUS_GNT_FW_8822B(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT_FW_8822B(x) | BIT_I2C_M_BUS_GNT_FW_8822B(v)) #define BIT_I2C_M_GNT_FW_8822B BIT(3) #define BIT_SHIFT_I2C_M_SPEED_8822B 1 #define BIT_MASK_I2C_M_SPEED_8822B 0x3 -#define BIT_I2C_M_SPEED_8822B(x) (((x) & BIT_MASK_I2C_M_SPEED_8822B) << BIT_SHIFT_I2C_M_SPEED_8822B) -#define BIT_GET_I2C_M_SPEED_8822B(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8822B) & BIT_MASK_I2C_M_SPEED_8822B) - +#define BIT_I2C_M_SPEED_8822B(x) \ + (((x) & BIT_MASK_I2C_M_SPEED_8822B) << BIT_SHIFT_I2C_M_SPEED_8822B) +#define BITS_I2C_M_SPEED_8822B \ + (BIT_MASK_I2C_M_SPEED_8822B << BIT_SHIFT_I2C_M_SPEED_8822B) +#define BIT_CLEAR_I2C_M_SPEED_8822B(x) ((x) & (~BITS_I2C_M_SPEED_8822B)) +#define BIT_GET_I2C_M_SPEED_8822B(x) \ + (((x) >> BIT_SHIFT_I2C_M_SPEED_8822B) & BIT_MASK_I2C_M_SPEED_8822B) +#define BIT_SET_I2C_M_SPEED_8822B(x, v) \ + (BIT_CLEAR_I2C_M_SPEED_8822B(x) | BIT_I2C_M_SPEED_8822B(v)) #define BIT_I2C_M_UNLOCK_8822B BIT(0) @@ -2209,10 +3178,15 @@ #define BIT_SHIFT_RXFF0_BNDY_V2_8822B 0 #define BIT_MASK_RXFF0_BNDY_V2_8822B 0x3ffff -#define BIT_RXFF0_BNDY_V2_8822B(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8822B) << BIT_SHIFT_RXFF0_BNDY_V2_8822B) -#define BIT_GET_RXFF0_BNDY_V2_8822B(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822B) & BIT_MASK_RXFF0_BNDY_V2_8822B) - - +#define BIT_RXFF0_BNDY_V2_8822B(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V2_8822B) << BIT_SHIFT_RXFF0_BNDY_V2_8822B) +#define BITS_RXFF0_BNDY_V2_8822B \ + (BIT_MASK_RXFF0_BNDY_V2_8822B << BIT_SHIFT_RXFF0_BNDY_V2_8822B) +#define BIT_CLEAR_RXFF0_BNDY_V2_8822B(x) ((x) & (~BITS_RXFF0_BNDY_V2_8822B)) +#define BIT_GET_RXFF0_BNDY_V2_8822B(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822B) & BIT_MASK_RXFF0_BNDY_V2_8822B) +#define BIT_SET_RXFF0_BNDY_V2_8822B(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V2_8822B(x) | BIT_RXFF0_BNDY_V2_8822B(v)) /* 2 REG_FE1IMR_8822B */ #define BIT_FS_RXDMA2_DONE_INT_EN_8822B BIT(28) @@ -2279,10 +3253,15 @@ #define BIT_SHIFT_CPWM_MOD_8822B 24 #define BIT_MASK_CPWM_MOD_8822B 0x7f -#define BIT_CPWM_MOD_8822B(x) (((x) & BIT_MASK_CPWM_MOD_8822B) << BIT_SHIFT_CPWM_MOD_8822B) -#define BIT_GET_CPWM_MOD_8822B(x) (((x) >> BIT_SHIFT_CPWM_MOD_8822B) & BIT_MASK_CPWM_MOD_8822B) - - +#define BIT_CPWM_MOD_8822B(x) \ + (((x) & BIT_MASK_CPWM_MOD_8822B) << BIT_SHIFT_CPWM_MOD_8822B) +#define BITS_CPWM_MOD_8822B \ + (BIT_MASK_CPWM_MOD_8822B << BIT_SHIFT_CPWM_MOD_8822B) +#define BIT_CLEAR_CPWM_MOD_8822B(x) ((x) & (~BITS_CPWM_MOD_8822B)) +#define BIT_GET_CPWM_MOD_8822B(x) \ + (((x) >> BIT_SHIFT_CPWM_MOD_8822B) & BIT_MASK_CPWM_MOD_8822B) +#define BIT_SET_CPWM_MOD_8822B(x, v) \ + (BIT_CLEAR_CPWM_MOD_8822B(x) | BIT_CPWM_MOD_8822B(v)) /* 2 REG_FWIMR_8822B */ #define BIT_FS_TXBCNOK_MB7_INT_EN_8822B BIT(31) @@ -2305,8 +3284,7 @@ #define BIT_SIFS_OVERSPEC_INT_EN_8822B BIT(14) #define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8822B BIT(13) #define BIT_FS_MGNTQFF_TO_INT_EN_8822B BIT(12) -#define BIT_FS_DDMA1_LP_INT_EN_8822B BIT(11) -#define BIT_FS_DDMA1_HP_INT_EN_8822B BIT(10) +#define BIT_FS_CPUMGQ_ERR_INT_EN_8822B BIT(11) #define BIT_FS_DDMA0_LP_INT_EN_8822B BIT(9) #define BIT_FS_DDMA0_HP_INT_EN_8822B BIT(8) #define BIT_FS_TRXRPT_INT_EN_8822B BIT(7) @@ -2339,8 +3317,7 @@ #define BIT_SIFS_OVERSPEC_INT_8822B BIT(14) #define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8822B BIT(13) #define BIT_FS_MGNTQFF_TO_INT_8822B BIT(12) -#define BIT_FS_DDMA1_LP_INT_8822B BIT(11) -#define BIT_FS_DDMA1_HP_INT_8822B BIT(10) +#define BIT_FS_CPUMGQ_ERR_INT_8822B BIT(11) #define BIT_FS_DDMA0_LP_INT_8822B BIT(9) #define BIT_FS_DDMA0_HP_INT_8822B BIT(8) #define BIT_FS_TRXRPT_INT_8822B BIT(7) @@ -2400,9 +3377,17 @@ #define BIT_SHIFT_PKTBUF_WRITE_EN_8822B 24 #define BIT_MASK_PKTBUF_WRITE_EN_8822B 0xff -#define BIT_PKTBUF_WRITE_EN_8822B(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8822B) << BIT_SHIFT_PKTBUF_WRITE_EN_8822B) -#define BIT_GET_PKTBUF_WRITE_EN_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822B) & BIT_MASK_PKTBUF_WRITE_EN_8822B) - +#define BIT_PKTBUF_WRITE_EN_8822B(x) \ + (((x) & BIT_MASK_PKTBUF_WRITE_EN_8822B) \ + << BIT_SHIFT_PKTBUF_WRITE_EN_8822B) +#define BITS_PKTBUF_WRITE_EN_8822B \ + (BIT_MASK_PKTBUF_WRITE_EN_8822B << BIT_SHIFT_PKTBUF_WRITE_EN_8822B) +#define BIT_CLEAR_PKTBUF_WRITE_EN_8822B(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8822B)) +#define BIT_GET_PKTBUF_WRITE_EN_8822B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822B) & \ + BIT_MASK_PKTBUF_WRITE_EN_8822B) +#define BIT_SET_PKTBUF_WRITE_EN_8822B(x, v) \ + (BIT_CLEAR_PKTBUF_WRITE_EN_8822B(x) | BIT_PKTBUF_WRITE_EN_8822B(v)) #define BIT_TXRPTBUF_DBG_8822B BIT(23) @@ -2412,45 +3397,81 @@ #define BIT_SHIFT_PKTBUF_DBG_ADDR_8822B 0 #define BIT_MASK_PKTBUF_DBG_ADDR_8822B 0x1fff -#define BIT_PKTBUF_DBG_ADDR_8822B(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822B) << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) -#define BIT_GET_PKTBUF_DBG_ADDR_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) & BIT_MASK_PKTBUF_DBG_ADDR_8822B) - - +#define BIT_PKTBUF_DBG_ADDR_8822B(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822B) \ + << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) +#define BITS_PKTBUF_DBG_ADDR_8822B \ + (BIT_MASK_PKTBUF_DBG_ADDR_8822B << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) +#define BIT_CLEAR_PKTBUF_DBG_ADDR_8822B(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8822B)) +#define BIT_GET_PKTBUF_DBG_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) & \ + BIT_MASK_PKTBUF_DBG_ADDR_8822B) +#define BIT_SET_PKTBUF_DBG_ADDR_8822B(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_ADDR_8822B(x) | BIT_PKTBUF_DBG_ADDR_8822B(v)) /* 2 REG_PKTBUF_DBG_DATA_L_8822B */ #define BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B 0 #define BIT_MASK_PKTBUF_DBG_DATA_L_8822B 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_L_8822B(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) -#define BIT_GET_PKTBUF_DBG_DATA_L_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B) - - +#define BIT_PKTBUF_DBG_DATA_L_8822B(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) +#define BITS_PKTBUF_DBG_DATA_L_8822B \ + (BIT_MASK_PKTBUF_DBG_DATA_L_8822B << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8822B(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_L_8822B)) +#define BIT_GET_PKTBUF_DBG_DATA_L_8822B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) & \ + BIT_MASK_PKTBUF_DBG_DATA_L_8822B) +#define BIT_SET_PKTBUF_DBG_DATA_L_8822B(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_L_8822B(x) | BIT_PKTBUF_DBG_DATA_L_8822B(v)) /* 2 REG_PKTBUF_DBG_DATA_H_8822B */ #define BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B 0 #define BIT_MASK_PKTBUF_DBG_DATA_H_8822B 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_H_8822B(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) -#define BIT_GET_PKTBUF_DBG_DATA_H_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B) - - +#define BIT_PKTBUF_DBG_DATA_H_8822B(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) +#define BITS_PKTBUF_DBG_DATA_H_8822B \ + (BIT_MASK_PKTBUF_DBG_DATA_H_8822B << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8822B(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_H_8822B)) +#define BIT_GET_PKTBUF_DBG_DATA_H_8822B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) & \ + BIT_MASK_PKTBUF_DBG_DATA_H_8822B) +#define BIT_SET_PKTBUF_DBG_DATA_H_8822B(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_H_8822B(x) | BIT_PKTBUF_DBG_DATA_H_8822B(v)) /* 2 REG_CPWM2_8822B */ #define BIT_SHIFT_L0S_TO_RCVY_NUM_8822B 16 #define BIT_MASK_L0S_TO_RCVY_NUM_8822B 0xff -#define BIT_L0S_TO_RCVY_NUM_8822B(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822B) << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) -#define BIT_GET_L0S_TO_RCVY_NUM_8822B(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) & BIT_MASK_L0S_TO_RCVY_NUM_8822B) - +#define BIT_L0S_TO_RCVY_NUM_8822B(x) \ + (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822B) \ + << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) +#define BITS_L0S_TO_RCVY_NUM_8822B \ + (BIT_MASK_L0S_TO_RCVY_NUM_8822B << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) +#define BIT_CLEAR_L0S_TO_RCVY_NUM_8822B(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8822B)) +#define BIT_GET_L0S_TO_RCVY_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) & \ + BIT_MASK_L0S_TO_RCVY_NUM_8822B) +#define BIT_SET_L0S_TO_RCVY_NUM_8822B(x, v) \ + (BIT_CLEAR_L0S_TO_RCVY_NUM_8822B(x) | BIT_L0S_TO_RCVY_NUM_8822B(v)) #define BIT_CPWM2_TOGGLING_8822B BIT(15) #define BIT_SHIFT_CPWM2_MOD_8822B 0 #define BIT_MASK_CPWM2_MOD_8822B 0x7fff -#define BIT_CPWM2_MOD_8822B(x) (((x) & BIT_MASK_CPWM2_MOD_8822B) << BIT_SHIFT_CPWM2_MOD_8822B) -#define BIT_GET_CPWM2_MOD_8822B(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8822B) & BIT_MASK_CPWM2_MOD_8822B) - - +#define BIT_CPWM2_MOD_8822B(x) \ + (((x) & BIT_MASK_CPWM2_MOD_8822B) << BIT_SHIFT_CPWM2_MOD_8822B) +#define BITS_CPWM2_MOD_8822B \ + (BIT_MASK_CPWM2_MOD_8822B << BIT_SHIFT_CPWM2_MOD_8822B) +#define BIT_CLEAR_CPWM2_MOD_8822B(x) ((x) & (~BITS_CPWM2_MOD_8822B)) +#define BIT_GET_CPWM2_MOD_8822B(x) \ + (((x) >> BIT_SHIFT_CPWM2_MOD_8822B) & BIT_MASK_CPWM2_MOD_8822B) +#define BIT_SET_CPWM2_MOD_8822B(x, v) \ + (BIT_CLEAR_CPWM2_MOD_8822B(x) | BIT_CPWM2_MOD_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -2461,10 +3482,14 @@ #define BIT_SHIFT_TC0DATA_8822B 0 #define BIT_MASK_TC0DATA_8822B 0xffffff -#define BIT_TC0DATA_8822B(x) (((x) & BIT_MASK_TC0DATA_8822B) << BIT_SHIFT_TC0DATA_8822B) -#define BIT_GET_TC0DATA_8822B(x) (((x) >> BIT_SHIFT_TC0DATA_8822B) & BIT_MASK_TC0DATA_8822B) - - +#define BIT_TC0DATA_8822B(x) \ + (((x) & BIT_MASK_TC0DATA_8822B) << BIT_SHIFT_TC0DATA_8822B) +#define BITS_TC0DATA_8822B (BIT_MASK_TC0DATA_8822B << BIT_SHIFT_TC0DATA_8822B) +#define BIT_CLEAR_TC0DATA_8822B(x) ((x) & (~BITS_TC0DATA_8822B)) +#define BIT_GET_TC0DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC0DATA_8822B) & BIT_MASK_TC0DATA_8822B) +#define BIT_SET_TC0DATA_8822B(x, v) \ + (BIT_CLEAR_TC0DATA_8822B(x) | BIT_TC0DATA_8822B(v)) /* 2 REG_TC1_CTRL_8822B */ #define BIT_TC1INT_EN_8822B BIT(26) @@ -2473,10 +3498,14 @@ #define BIT_SHIFT_TC1DATA_8822B 0 #define BIT_MASK_TC1DATA_8822B 0xffffff -#define BIT_TC1DATA_8822B(x) (((x) & BIT_MASK_TC1DATA_8822B) << BIT_SHIFT_TC1DATA_8822B) -#define BIT_GET_TC1DATA_8822B(x) (((x) >> BIT_SHIFT_TC1DATA_8822B) & BIT_MASK_TC1DATA_8822B) - - +#define BIT_TC1DATA_8822B(x) \ + (((x) & BIT_MASK_TC1DATA_8822B) << BIT_SHIFT_TC1DATA_8822B) +#define BITS_TC1DATA_8822B (BIT_MASK_TC1DATA_8822B << BIT_SHIFT_TC1DATA_8822B) +#define BIT_CLEAR_TC1DATA_8822B(x) ((x) & (~BITS_TC1DATA_8822B)) +#define BIT_GET_TC1DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC1DATA_8822B) & BIT_MASK_TC1DATA_8822B) +#define BIT_SET_TC1DATA_8822B(x, v) \ + (BIT_CLEAR_TC1DATA_8822B(x) | BIT_TC1DATA_8822B(v)) /* 2 REG_TC2_CTRL_8822B */ #define BIT_TC2INT_EN_8822B BIT(26) @@ -2485,10 +3514,14 @@ #define BIT_SHIFT_TC2DATA_8822B 0 #define BIT_MASK_TC2DATA_8822B 0xffffff -#define BIT_TC2DATA_8822B(x) (((x) & BIT_MASK_TC2DATA_8822B) << BIT_SHIFT_TC2DATA_8822B) -#define BIT_GET_TC2DATA_8822B(x) (((x) >> BIT_SHIFT_TC2DATA_8822B) & BIT_MASK_TC2DATA_8822B) - - +#define BIT_TC2DATA_8822B(x) \ + (((x) & BIT_MASK_TC2DATA_8822B) << BIT_SHIFT_TC2DATA_8822B) +#define BITS_TC2DATA_8822B (BIT_MASK_TC2DATA_8822B << BIT_SHIFT_TC2DATA_8822B) +#define BIT_CLEAR_TC2DATA_8822B(x) ((x) & (~BITS_TC2DATA_8822B)) +#define BIT_GET_TC2DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC2DATA_8822B) & BIT_MASK_TC2DATA_8822B) +#define BIT_SET_TC2DATA_8822B(x, v) \ + (BIT_CLEAR_TC2DATA_8822B(x) | BIT_TC2DATA_8822B(v)) /* 2 REG_TC3_CTRL_8822B */ #define BIT_TC3INT_EN_8822B BIT(26) @@ -2497,10 +3530,14 @@ #define BIT_SHIFT_TC3DATA_8822B 0 #define BIT_MASK_TC3DATA_8822B 0xffffff -#define BIT_TC3DATA_8822B(x) (((x) & BIT_MASK_TC3DATA_8822B) << BIT_SHIFT_TC3DATA_8822B) -#define BIT_GET_TC3DATA_8822B(x) (((x) >> BIT_SHIFT_TC3DATA_8822B) & BIT_MASK_TC3DATA_8822B) - - +#define BIT_TC3DATA_8822B(x) \ + (((x) & BIT_MASK_TC3DATA_8822B) << BIT_SHIFT_TC3DATA_8822B) +#define BITS_TC3DATA_8822B (BIT_MASK_TC3DATA_8822B << BIT_SHIFT_TC3DATA_8822B) +#define BIT_CLEAR_TC3DATA_8822B(x) ((x) & (~BITS_TC3DATA_8822B)) +#define BIT_GET_TC3DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC3DATA_8822B) & BIT_MASK_TC3DATA_8822B) +#define BIT_SET_TC3DATA_8822B(x, v) \ + (BIT_CLEAR_TC3DATA_8822B(x) | BIT_TC3DATA_8822B(v)) /* 2 REG_TC4_CTRL_8822B */ #define BIT_TC4INT_EN_8822B BIT(26) @@ -2509,19 +3546,28 @@ #define BIT_SHIFT_TC4DATA_8822B 0 #define BIT_MASK_TC4DATA_8822B 0xffffff -#define BIT_TC4DATA_8822B(x) (((x) & BIT_MASK_TC4DATA_8822B) << BIT_SHIFT_TC4DATA_8822B) -#define BIT_GET_TC4DATA_8822B(x) (((x) >> BIT_SHIFT_TC4DATA_8822B) & BIT_MASK_TC4DATA_8822B) - - +#define BIT_TC4DATA_8822B(x) \ + (((x) & BIT_MASK_TC4DATA_8822B) << BIT_SHIFT_TC4DATA_8822B) +#define BITS_TC4DATA_8822B (BIT_MASK_TC4DATA_8822B << BIT_SHIFT_TC4DATA_8822B) +#define BIT_CLEAR_TC4DATA_8822B(x) ((x) & (~BITS_TC4DATA_8822B)) +#define BIT_GET_TC4DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC4DATA_8822B) & BIT_MASK_TC4DATA_8822B) +#define BIT_SET_TC4DATA_8822B(x, v) \ + (BIT_CLEAR_TC4DATA_8822B(x) | BIT_TC4DATA_8822B(v)) /* 2 REG_TCUNIT_BASE_8822B */ #define BIT_SHIFT_TCUNIT_BASE_8822B 0 #define BIT_MASK_TCUNIT_BASE_8822B 0x3fff -#define BIT_TCUNIT_BASE_8822B(x) (((x) & BIT_MASK_TCUNIT_BASE_8822B) << BIT_SHIFT_TCUNIT_BASE_8822B) -#define BIT_GET_TCUNIT_BASE_8822B(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8822B) & BIT_MASK_TCUNIT_BASE_8822B) - - +#define BIT_TCUNIT_BASE_8822B(x) \ + (((x) & BIT_MASK_TCUNIT_BASE_8822B) << BIT_SHIFT_TCUNIT_BASE_8822B) +#define BITS_TCUNIT_BASE_8822B \ + (BIT_MASK_TCUNIT_BASE_8822B << BIT_SHIFT_TCUNIT_BASE_8822B) +#define BIT_CLEAR_TCUNIT_BASE_8822B(x) ((x) & (~BITS_TCUNIT_BASE_8822B)) +#define BIT_GET_TCUNIT_BASE_8822B(x) \ + (((x) >> BIT_SHIFT_TCUNIT_BASE_8822B) & BIT_MASK_TCUNIT_BASE_8822B) +#define BIT_SET_TCUNIT_BASE_8822B(x, v) \ + (BIT_CLEAR_TCUNIT_BASE_8822B(x) | BIT_TCUNIT_BASE_8822B(v)) /* 2 REG_TC5_CTRL_8822B */ #define BIT_TC5INT_EN_8822B BIT(26) @@ -2530,10 +3576,14 @@ #define BIT_SHIFT_TC5DATA_8822B 0 #define BIT_MASK_TC5DATA_8822B 0xffffff -#define BIT_TC5DATA_8822B(x) (((x) & BIT_MASK_TC5DATA_8822B) << BIT_SHIFT_TC5DATA_8822B) -#define BIT_GET_TC5DATA_8822B(x) (((x) >> BIT_SHIFT_TC5DATA_8822B) & BIT_MASK_TC5DATA_8822B) - - +#define BIT_TC5DATA_8822B(x) \ + (((x) & BIT_MASK_TC5DATA_8822B) << BIT_SHIFT_TC5DATA_8822B) +#define BITS_TC5DATA_8822B (BIT_MASK_TC5DATA_8822B << BIT_SHIFT_TC5DATA_8822B) +#define BIT_CLEAR_TC5DATA_8822B(x) ((x) & (~BITS_TC5DATA_8822B)) +#define BIT_GET_TC5DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC5DATA_8822B) & BIT_MASK_TC5DATA_8822B) +#define BIT_SET_TC5DATA_8822B(x, v) \ + (BIT_CLEAR_TC5DATA_8822B(x) | BIT_TC5DATA_8822B(v)) /* 2 REG_TC6_CTRL_8822B */ #define BIT_TC6INT_EN_8822B BIT(26) @@ -2542,127 +3592,244 @@ #define BIT_SHIFT_TC6DATA_8822B 0 #define BIT_MASK_TC6DATA_8822B 0xffffff -#define BIT_TC6DATA_8822B(x) (((x) & BIT_MASK_TC6DATA_8822B) << BIT_SHIFT_TC6DATA_8822B) -#define BIT_GET_TC6DATA_8822B(x) (((x) >> BIT_SHIFT_TC6DATA_8822B) & BIT_MASK_TC6DATA_8822B) - - +#define BIT_TC6DATA_8822B(x) \ + (((x) & BIT_MASK_TC6DATA_8822B) << BIT_SHIFT_TC6DATA_8822B) +#define BITS_TC6DATA_8822B (BIT_MASK_TC6DATA_8822B << BIT_SHIFT_TC6DATA_8822B) +#define BIT_CLEAR_TC6DATA_8822B(x) ((x) & (~BITS_TC6DATA_8822B)) +#define BIT_GET_TC6DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC6DATA_8822B) & BIT_MASK_TC6DATA_8822B) +#define BIT_SET_TC6DATA_8822B(x, v) \ + (BIT_CLEAR_TC6DATA_8822B(x) | BIT_TC6DATA_8822B(v)) /* 2 REG_MBIST_FAIL_8822B */ #define BIT_SHIFT_8051_MBIST_FAIL_8822B 26 #define BIT_MASK_8051_MBIST_FAIL_8822B 0x7 -#define BIT_8051_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8822B) << BIT_SHIFT_8051_MBIST_FAIL_8822B) -#define BIT_GET_8051_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8822B) & BIT_MASK_8051_MBIST_FAIL_8822B) - - +#define BIT_8051_MBIST_FAIL_8822B(x) \ + (((x) & BIT_MASK_8051_MBIST_FAIL_8822B) \ + << BIT_SHIFT_8051_MBIST_FAIL_8822B) +#define BITS_8051_MBIST_FAIL_8822B \ + (BIT_MASK_8051_MBIST_FAIL_8822B << BIT_SHIFT_8051_MBIST_FAIL_8822B) +#define BIT_CLEAR_8051_MBIST_FAIL_8822B(x) ((x) & (~BITS_8051_MBIST_FAIL_8822B)) +#define BIT_GET_8051_MBIST_FAIL_8822B(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8822B) & \ + BIT_MASK_8051_MBIST_FAIL_8822B) +#define BIT_SET_8051_MBIST_FAIL_8822B(x, v) \ + (BIT_CLEAR_8051_MBIST_FAIL_8822B(x) | BIT_8051_MBIST_FAIL_8822B(v)) #define BIT_SHIFT_USB_MBIST_FAIL_8822B 24 #define BIT_MASK_USB_MBIST_FAIL_8822B 0x3 -#define BIT_USB_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8822B) << BIT_SHIFT_USB_MBIST_FAIL_8822B) -#define BIT_GET_USB_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8822B) & BIT_MASK_USB_MBIST_FAIL_8822B) - - +#define BIT_USB_MBIST_FAIL_8822B(x) \ + (((x) & BIT_MASK_USB_MBIST_FAIL_8822B) \ + << BIT_SHIFT_USB_MBIST_FAIL_8822B) +#define BITS_USB_MBIST_FAIL_8822B \ + (BIT_MASK_USB_MBIST_FAIL_8822B << BIT_SHIFT_USB_MBIST_FAIL_8822B) +#define BIT_CLEAR_USB_MBIST_FAIL_8822B(x) ((x) & (~BITS_USB_MBIST_FAIL_8822B)) +#define BIT_GET_USB_MBIST_FAIL_8822B(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8822B) & \ + BIT_MASK_USB_MBIST_FAIL_8822B) +#define BIT_SET_USB_MBIST_FAIL_8822B(x, v) \ + (BIT_CLEAR_USB_MBIST_FAIL_8822B(x) | BIT_USB_MBIST_FAIL_8822B(v)) #define BIT_SHIFT_PCIE_MBIST_FAIL_8822B 16 #define BIT_MASK_PCIE_MBIST_FAIL_8822B 0x3f -#define BIT_PCIE_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8822B) << BIT_SHIFT_PCIE_MBIST_FAIL_8822B) -#define BIT_GET_PCIE_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8822B) & BIT_MASK_PCIE_MBIST_FAIL_8822B) - - +#define BIT_PCIE_MBIST_FAIL_8822B(x) \ + (((x) & BIT_MASK_PCIE_MBIST_FAIL_8822B) \ + << BIT_SHIFT_PCIE_MBIST_FAIL_8822B) +#define BITS_PCIE_MBIST_FAIL_8822B \ + (BIT_MASK_PCIE_MBIST_FAIL_8822B << BIT_SHIFT_PCIE_MBIST_FAIL_8822B) +#define BIT_CLEAR_PCIE_MBIST_FAIL_8822B(x) ((x) & (~BITS_PCIE_MBIST_FAIL_8822B)) +#define BIT_GET_PCIE_MBIST_FAIL_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8822B) & \ + BIT_MASK_PCIE_MBIST_FAIL_8822B) +#define BIT_SET_PCIE_MBIST_FAIL_8822B(x, v) \ + (BIT_CLEAR_PCIE_MBIST_FAIL_8822B(x) | BIT_PCIE_MBIST_FAIL_8822B(v)) #define BIT_SHIFT_MAC_MBIST_FAIL_8822B 0 #define BIT_MASK_MAC_MBIST_FAIL_8822B 0xfff -#define BIT_MAC_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_8822B) << BIT_SHIFT_MAC_MBIST_FAIL_8822B) -#define BIT_GET_MAC_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8822B) & BIT_MASK_MAC_MBIST_FAIL_8822B) - - +#define BIT_MAC_MBIST_FAIL_8822B(x) \ + (((x) & BIT_MASK_MAC_MBIST_FAIL_8822B) \ + << BIT_SHIFT_MAC_MBIST_FAIL_8822B) +#define BITS_MAC_MBIST_FAIL_8822B \ + (BIT_MASK_MAC_MBIST_FAIL_8822B << BIT_SHIFT_MAC_MBIST_FAIL_8822B) +#define BIT_CLEAR_MAC_MBIST_FAIL_8822B(x) ((x) & (~BITS_MAC_MBIST_FAIL_8822B)) +#define BIT_GET_MAC_MBIST_FAIL_8822B(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8822B) & \ + BIT_MASK_MAC_MBIST_FAIL_8822B) +#define BIT_SET_MAC_MBIST_FAIL_8822B(x, v) \ + (BIT_CLEAR_MAC_MBIST_FAIL_8822B(x) | BIT_MAC_MBIST_FAIL_8822B(v)) /* 2 REG_MBIST_START_PAUSE_8822B */ #define BIT_SHIFT_8051_MBIST_START_PAUSE_8822B 26 #define BIT_MASK_8051_MBIST_START_PAUSE_8822B 0x7 -#define BIT_8051_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8822B) << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) -#define BIT_GET_8051_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) & BIT_MASK_8051_MBIST_START_PAUSE_8822B) - - +#define BIT_8051_MBIST_START_PAUSE_8822B(x) \ + (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8822B) \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) +#define BITS_8051_MBIST_START_PAUSE_8822B \ + (BIT_MASK_8051_MBIST_START_PAUSE_8822B \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) +#define BIT_CLEAR_8051_MBIST_START_PAUSE_8822B(x) \ + ((x) & (~BITS_8051_MBIST_START_PAUSE_8822B)) +#define BIT_GET_8051_MBIST_START_PAUSE_8822B(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) & \ + BIT_MASK_8051_MBIST_START_PAUSE_8822B) +#define BIT_SET_8051_MBIST_START_PAUSE_8822B(x, v) \ + (BIT_CLEAR_8051_MBIST_START_PAUSE_8822B(x) | \ + BIT_8051_MBIST_START_PAUSE_8822B(v)) #define BIT_SHIFT_USB_MBIST_START_PAUSE_8822B 24 #define BIT_MASK_USB_MBIST_START_PAUSE_8822B 0x3 -#define BIT_USB_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8822B) << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) -#define BIT_GET_USB_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) & BIT_MASK_USB_MBIST_START_PAUSE_8822B) - - +#define BIT_USB_MBIST_START_PAUSE_8822B(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8822B) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) +#define BITS_USB_MBIST_START_PAUSE_8822B \ + (BIT_MASK_USB_MBIST_START_PAUSE_8822B \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) +#define BIT_CLEAR_USB_MBIST_START_PAUSE_8822B(x) \ + ((x) & (~BITS_USB_MBIST_START_PAUSE_8822B)) +#define BIT_GET_USB_MBIST_START_PAUSE_8822B(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) & \ + BIT_MASK_USB_MBIST_START_PAUSE_8822B) +#define BIT_SET_USB_MBIST_START_PAUSE_8822B(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE_8822B(x) | \ + BIT_USB_MBIST_START_PAUSE_8822B(v)) #define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B 16 #define BIT_MASK_PCIE_MBIST_START_PAUSE_8822B 0x3f -#define BIT_PCIE_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) -#define BIT_GET_PCIE_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) - - +#define BIT_PCIE_MBIST_START_PAUSE_8822B(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) +#define BITS_PCIE_MBIST_START_PAUSE_8822B \ + (BIT_MASK_PCIE_MBIST_START_PAUSE_8822B \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8822B(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE_8822B)) +#define BIT_GET_PCIE_MBIST_START_PAUSE_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) +#define BIT_SET_PCIE_MBIST_START_PAUSE_8822B(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE_8822B(x) | \ + BIT_PCIE_MBIST_START_PAUSE_8822B(v)) #define BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B 0 #define BIT_MASK_MAC_MBIST_START_PAUSE_8822B 0xfff -#define BIT_MAC_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B) << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) -#define BIT_GET_MAC_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B) - - +#define BIT_MAC_MBIST_START_PAUSE_8822B(x) \ + (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B) \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) +#define BITS_MAC_MBIST_START_PAUSE_8822B \ + (BIT_MASK_MAC_MBIST_START_PAUSE_8822B \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE_8822B(x) \ + ((x) & (~BITS_MAC_MBIST_START_PAUSE_8822B)) +#define BIT_GET_MAC_MBIST_START_PAUSE_8822B(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) & \ + BIT_MASK_MAC_MBIST_START_PAUSE_8822B) +#define BIT_SET_MAC_MBIST_START_PAUSE_8822B(x, v) \ + (BIT_CLEAR_MAC_MBIST_START_PAUSE_8822B(x) | \ + BIT_MAC_MBIST_START_PAUSE_8822B(v)) /* 2 REG_MBIST_DONE_8822B */ #define BIT_SHIFT_8051_MBIST_DONE_8822B 26 #define BIT_MASK_8051_MBIST_DONE_8822B 0x7 -#define BIT_8051_MBIST_DONE_8822B(x) (((x) & BIT_MASK_8051_MBIST_DONE_8822B) << BIT_SHIFT_8051_MBIST_DONE_8822B) -#define BIT_GET_8051_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8822B) & BIT_MASK_8051_MBIST_DONE_8822B) - - +#define BIT_8051_MBIST_DONE_8822B(x) \ + (((x) & BIT_MASK_8051_MBIST_DONE_8822B) \ + << BIT_SHIFT_8051_MBIST_DONE_8822B) +#define BITS_8051_MBIST_DONE_8822B \ + (BIT_MASK_8051_MBIST_DONE_8822B << BIT_SHIFT_8051_MBIST_DONE_8822B) +#define BIT_CLEAR_8051_MBIST_DONE_8822B(x) ((x) & (~BITS_8051_MBIST_DONE_8822B)) +#define BIT_GET_8051_MBIST_DONE_8822B(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DONE_8822B) & \ + BIT_MASK_8051_MBIST_DONE_8822B) +#define BIT_SET_8051_MBIST_DONE_8822B(x, v) \ + (BIT_CLEAR_8051_MBIST_DONE_8822B(x) | BIT_8051_MBIST_DONE_8822B(v)) #define BIT_SHIFT_USB_MBIST_DONE_8822B 24 #define BIT_MASK_USB_MBIST_DONE_8822B 0x3 -#define BIT_USB_MBIST_DONE_8822B(x) (((x) & BIT_MASK_USB_MBIST_DONE_8822B) << BIT_SHIFT_USB_MBIST_DONE_8822B) -#define BIT_GET_USB_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8822B) & BIT_MASK_USB_MBIST_DONE_8822B) - - +#define BIT_USB_MBIST_DONE_8822B(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE_8822B) \ + << BIT_SHIFT_USB_MBIST_DONE_8822B) +#define BITS_USB_MBIST_DONE_8822B \ + (BIT_MASK_USB_MBIST_DONE_8822B << BIT_SHIFT_USB_MBIST_DONE_8822B) +#define BIT_CLEAR_USB_MBIST_DONE_8822B(x) ((x) & (~BITS_USB_MBIST_DONE_8822B)) +#define BIT_GET_USB_MBIST_DONE_8822B(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE_8822B) & \ + BIT_MASK_USB_MBIST_DONE_8822B) +#define BIT_SET_USB_MBIST_DONE_8822B(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE_8822B(x) | BIT_USB_MBIST_DONE_8822B(v)) #define BIT_SHIFT_PCIE_MBIST_DONE_8822B 16 #define BIT_MASK_PCIE_MBIST_DONE_8822B 0x3f -#define BIT_PCIE_MBIST_DONE_8822B(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8822B) << BIT_SHIFT_PCIE_MBIST_DONE_8822B) -#define BIT_GET_PCIE_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8822B) & BIT_MASK_PCIE_MBIST_DONE_8822B) - - +#define BIT_PCIE_MBIST_DONE_8822B(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE_8822B) \ + << BIT_SHIFT_PCIE_MBIST_DONE_8822B) +#define BITS_PCIE_MBIST_DONE_8822B \ + (BIT_MASK_PCIE_MBIST_DONE_8822B << BIT_SHIFT_PCIE_MBIST_DONE_8822B) +#define BIT_CLEAR_PCIE_MBIST_DONE_8822B(x) ((x) & (~BITS_PCIE_MBIST_DONE_8822B)) +#define BIT_GET_PCIE_MBIST_DONE_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8822B) & \ + BIT_MASK_PCIE_MBIST_DONE_8822B) +#define BIT_SET_PCIE_MBIST_DONE_8822B(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE_8822B(x) | BIT_PCIE_MBIST_DONE_8822B(v)) #define BIT_SHIFT_MAC_MBIST_DONE_8822B 0 #define BIT_MASK_MAC_MBIST_DONE_8822B 0xfff -#define BIT_MAC_MBIST_DONE_8822B(x) (((x) & BIT_MASK_MAC_MBIST_DONE_8822B) << BIT_SHIFT_MAC_MBIST_DONE_8822B) -#define BIT_GET_MAC_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8822B) & BIT_MASK_MAC_MBIST_DONE_8822B) - - +#define BIT_MAC_MBIST_DONE_8822B(x) \ + (((x) & BIT_MASK_MAC_MBIST_DONE_8822B) \ + << BIT_SHIFT_MAC_MBIST_DONE_8822B) +#define BITS_MAC_MBIST_DONE_8822B \ + (BIT_MASK_MAC_MBIST_DONE_8822B << BIT_SHIFT_MAC_MBIST_DONE_8822B) +#define BIT_CLEAR_MAC_MBIST_DONE_8822B(x) ((x) & (~BITS_MAC_MBIST_DONE_8822B)) +#define BIT_GET_MAC_MBIST_DONE_8822B(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8822B) & \ + BIT_MASK_MAC_MBIST_DONE_8822B) +#define BIT_SET_MAC_MBIST_DONE_8822B(x, v) \ + (BIT_CLEAR_MAC_MBIST_DONE_8822B(x) | BIT_MAC_MBIST_DONE_8822B(v)) /* 2 REG_MBIST_FAIL_NRML_8822B */ #define BIT_SHIFT_MBIST_FAIL_NRML_8822B 0 #define BIT_MASK_MBIST_FAIL_NRML_8822B 0xffffffffL -#define BIT_MBIST_FAIL_NRML_8822B(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_8822B) << BIT_SHIFT_MBIST_FAIL_NRML_8822B) -#define BIT_GET_MBIST_FAIL_NRML_8822B(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8822B) & BIT_MASK_MBIST_FAIL_NRML_8822B) - - +#define BIT_MBIST_FAIL_NRML_8822B(x) \ + (((x) & BIT_MASK_MBIST_FAIL_NRML_8822B) \ + << BIT_SHIFT_MBIST_FAIL_NRML_8822B) +#define BITS_MBIST_FAIL_NRML_8822B \ + (BIT_MASK_MBIST_FAIL_NRML_8822B << BIT_SHIFT_MBIST_FAIL_NRML_8822B) +#define BIT_CLEAR_MBIST_FAIL_NRML_8822B(x) ((x) & (~BITS_MBIST_FAIL_NRML_8822B)) +#define BIT_GET_MBIST_FAIL_NRML_8822B(x) \ + (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8822B) & \ + BIT_MASK_MBIST_FAIL_NRML_8822B) +#define BIT_SET_MBIST_FAIL_NRML_8822B(x, v) \ + (BIT_CLEAR_MBIST_FAIL_NRML_8822B(x) | BIT_MBIST_FAIL_NRML_8822B(v)) /* 2 REG_AES_DECRPT_DATA_8822B */ #define BIT_SHIFT_IPS_CFG_ADDR_8822B 0 #define BIT_MASK_IPS_CFG_ADDR_8822B 0xff -#define BIT_IPS_CFG_ADDR_8822B(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8822B) << BIT_SHIFT_IPS_CFG_ADDR_8822B) -#define BIT_GET_IPS_CFG_ADDR_8822B(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822B) & BIT_MASK_IPS_CFG_ADDR_8822B) - - +#define BIT_IPS_CFG_ADDR_8822B(x) \ + (((x) & BIT_MASK_IPS_CFG_ADDR_8822B) << BIT_SHIFT_IPS_CFG_ADDR_8822B) +#define BITS_IPS_CFG_ADDR_8822B \ + (BIT_MASK_IPS_CFG_ADDR_8822B << BIT_SHIFT_IPS_CFG_ADDR_8822B) +#define BIT_CLEAR_IPS_CFG_ADDR_8822B(x) ((x) & (~BITS_IPS_CFG_ADDR_8822B)) +#define BIT_GET_IPS_CFG_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822B) & BIT_MASK_IPS_CFG_ADDR_8822B) +#define BIT_SET_IPS_CFG_ADDR_8822B(x, v) \ + (BIT_CLEAR_IPS_CFG_ADDR_8822B(x) | BIT_IPS_CFG_ADDR_8822B(v)) /* 2 REG_AES_DECRPT_CFG_8822B */ #define BIT_SHIFT_IPS_CFG_DATA_8822B 0 #define BIT_MASK_IPS_CFG_DATA_8822B 0xffffffffL -#define BIT_IPS_CFG_DATA_8822B(x) (((x) & BIT_MASK_IPS_CFG_DATA_8822B) << BIT_SHIFT_IPS_CFG_DATA_8822B) -#define BIT_GET_IPS_CFG_DATA_8822B(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8822B) & BIT_MASK_IPS_CFG_DATA_8822B) - - +#define BIT_IPS_CFG_DATA_8822B(x) \ + (((x) & BIT_MASK_IPS_CFG_DATA_8822B) << BIT_SHIFT_IPS_CFG_DATA_8822B) +#define BITS_IPS_CFG_DATA_8822B \ + (BIT_MASK_IPS_CFG_DATA_8822B << BIT_SHIFT_IPS_CFG_DATA_8822B) +#define BIT_CLEAR_IPS_CFG_DATA_8822B(x) ((x) & (~BITS_IPS_CFG_DATA_8822B)) +#define BIT_GET_IPS_CFG_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_DATA_8822B) & BIT_MASK_IPS_CFG_DATA_8822B) +#define BIT_SET_IPS_CFG_DATA_8822B(x, v) \ + (BIT_CLEAR_IPS_CFG_DATA_8822B(x) | BIT_IPS_CFG_DATA_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -2673,23 +3840,44 @@ #define BIT_SHIFT_TEMP_VALUE_8822B 24 #define BIT_MASK_TEMP_VALUE_8822B 0x3f -#define BIT_TEMP_VALUE_8822B(x) (((x) & BIT_MASK_TEMP_VALUE_8822B) << BIT_SHIFT_TEMP_VALUE_8822B) -#define BIT_GET_TEMP_VALUE_8822B(x) (((x) >> BIT_SHIFT_TEMP_VALUE_8822B) & BIT_MASK_TEMP_VALUE_8822B) - - +#define BIT_TEMP_VALUE_8822B(x) \ + (((x) & BIT_MASK_TEMP_VALUE_8822B) << BIT_SHIFT_TEMP_VALUE_8822B) +#define BITS_TEMP_VALUE_8822B \ + (BIT_MASK_TEMP_VALUE_8822B << BIT_SHIFT_TEMP_VALUE_8822B) +#define BIT_CLEAR_TEMP_VALUE_8822B(x) ((x) & (~BITS_TEMP_VALUE_8822B)) +#define BIT_GET_TEMP_VALUE_8822B(x) \ + (((x) >> BIT_SHIFT_TEMP_VALUE_8822B) & BIT_MASK_TEMP_VALUE_8822B) +#define BIT_SET_TEMP_VALUE_8822B(x, v) \ + (BIT_CLEAR_TEMP_VALUE_8822B(x) | BIT_TEMP_VALUE_8822B(v)) #define BIT_SHIFT_REG_TMETER_TIMER_8822B 8 #define BIT_MASK_REG_TMETER_TIMER_8822B 0xfff -#define BIT_REG_TMETER_TIMER_8822B(x) (((x) & BIT_MASK_REG_TMETER_TIMER_8822B) << BIT_SHIFT_REG_TMETER_TIMER_8822B) -#define BIT_GET_REG_TMETER_TIMER_8822B(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822B) & BIT_MASK_REG_TMETER_TIMER_8822B) - - +#define BIT_REG_TMETER_TIMER_8822B(x) \ + (((x) & BIT_MASK_REG_TMETER_TIMER_8822B) \ + << BIT_SHIFT_REG_TMETER_TIMER_8822B) +#define BITS_REG_TMETER_TIMER_8822B \ + (BIT_MASK_REG_TMETER_TIMER_8822B << BIT_SHIFT_REG_TMETER_TIMER_8822B) +#define BIT_CLEAR_REG_TMETER_TIMER_8822B(x) \ + ((x) & (~BITS_REG_TMETER_TIMER_8822B)) +#define BIT_GET_REG_TMETER_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822B) & \ + BIT_MASK_REG_TMETER_TIMER_8822B) +#define BIT_SET_REG_TMETER_TIMER_8822B(x, v) \ + (BIT_CLEAR_REG_TMETER_TIMER_8822B(x) | BIT_REG_TMETER_TIMER_8822B(v)) #define BIT_SHIFT_REG_TEMP_DELTA_8822B 2 #define BIT_MASK_REG_TEMP_DELTA_8822B 0x3f -#define BIT_REG_TEMP_DELTA_8822B(x) (((x) & BIT_MASK_REG_TEMP_DELTA_8822B) << BIT_SHIFT_REG_TEMP_DELTA_8822B) -#define BIT_GET_REG_TEMP_DELTA_8822B(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822B) & BIT_MASK_REG_TEMP_DELTA_8822B) - +#define BIT_REG_TEMP_DELTA_8822B(x) \ + (((x) & BIT_MASK_REG_TEMP_DELTA_8822B) \ + << BIT_SHIFT_REG_TEMP_DELTA_8822B) +#define BITS_REG_TEMP_DELTA_8822B \ + (BIT_MASK_REG_TEMP_DELTA_8822B << BIT_SHIFT_REG_TEMP_DELTA_8822B) +#define BIT_CLEAR_REG_TEMP_DELTA_8822B(x) ((x) & (~BITS_REG_TEMP_DELTA_8822B)) +#define BIT_GET_REG_TEMP_DELTA_8822B(x) \ + (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822B) & \ + BIT_MASK_REG_TEMP_DELTA_8822B) +#define BIT_SET_REG_TEMP_DELTA_8822B(x, v) \ + (BIT_CLEAR_REG_TEMP_DELTA_8822B(x) | BIT_REG_TEMP_DELTA_8822B(v)) #define BIT_REG_TMETER_EN_8822B BIT(0) @@ -2697,16 +3885,33 @@ #define BIT_SHIFT_OSC_32K_CLKGEN_0_8822B 16 #define BIT_MASK_OSC_32K_CLKGEN_0_8822B 0xffff -#define BIT_OSC_32K_CLKGEN_0_8822B(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822B) << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) -#define BIT_GET_OSC_32K_CLKGEN_0_8822B(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) & BIT_MASK_OSC_32K_CLKGEN_0_8822B) - - +#define BIT_OSC_32K_CLKGEN_0_8822B(x) \ + (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822B) \ + << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) +#define BITS_OSC_32K_CLKGEN_0_8822B \ + (BIT_MASK_OSC_32K_CLKGEN_0_8822B << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) +#define BIT_CLEAR_OSC_32K_CLKGEN_0_8822B(x) \ + ((x) & (~BITS_OSC_32K_CLKGEN_0_8822B)) +#define BIT_GET_OSC_32K_CLKGEN_0_8822B(x) \ + (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) & \ + BIT_MASK_OSC_32K_CLKGEN_0_8822B) +#define BIT_SET_OSC_32K_CLKGEN_0_8822B(x, v) \ + (BIT_CLEAR_OSC_32K_CLKGEN_0_8822B(x) | BIT_OSC_32K_CLKGEN_0_8822B(v)) #define BIT_SHIFT_OSC_32K_RES_COMP_8822B 4 #define BIT_MASK_OSC_32K_RES_COMP_8822B 0x3 -#define BIT_OSC_32K_RES_COMP_8822B(x) (((x) & BIT_MASK_OSC_32K_RES_COMP_8822B) << BIT_SHIFT_OSC_32K_RES_COMP_8822B) -#define BIT_GET_OSC_32K_RES_COMP_8822B(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822B) & BIT_MASK_OSC_32K_RES_COMP_8822B) - +#define BIT_OSC_32K_RES_COMP_8822B(x) \ + (((x) & BIT_MASK_OSC_32K_RES_COMP_8822B) \ + << BIT_SHIFT_OSC_32K_RES_COMP_8822B) +#define BITS_OSC_32K_RES_COMP_8822B \ + (BIT_MASK_OSC_32K_RES_COMP_8822B << BIT_SHIFT_OSC_32K_RES_COMP_8822B) +#define BIT_CLEAR_OSC_32K_RES_COMP_8822B(x) \ + ((x) & (~BITS_OSC_32K_RES_COMP_8822B)) +#define BIT_GET_OSC_32K_RES_COMP_8822B(x) \ + (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822B) & \ + BIT_MASK_OSC_32K_RES_COMP_8822B) +#define BIT_SET_OSC_32K_RES_COMP_8822B(x, v) \ + (BIT_CLEAR_OSC_32K_RES_COMP_8822B(x) | BIT_OSC_32K_RES_COMP_8822B(v)) #define BIT_OSC_32K_OUT_SEL_8822B BIT(3) #define BIT_ISO_WL_2_OSC_32K_8822B BIT(1) @@ -2718,73 +3923,164 @@ #define BIT_SHIFT_CAL_32K_REG_ADDR_8822B 16 #define BIT_MASK_CAL_32K_REG_ADDR_8822B 0x3f -#define BIT_CAL_32K_REG_ADDR_8822B(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR_8822B) << BIT_SHIFT_CAL_32K_REG_ADDR_8822B) -#define BIT_GET_CAL_32K_REG_ADDR_8822B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822B) & BIT_MASK_CAL_32K_REG_ADDR_8822B) - - +#define BIT_CAL_32K_REG_ADDR_8822B(x) \ + (((x) & BIT_MASK_CAL_32K_REG_ADDR_8822B) \ + << BIT_SHIFT_CAL_32K_REG_ADDR_8822B) +#define BITS_CAL_32K_REG_ADDR_8822B \ + (BIT_MASK_CAL_32K_REG_ADDR_8822B << BIT_SHIFT_CAL_32K_REG_ADDR_8822B) +#define BIT_CLEAR_CAL_32K_REG_ADDR_8822B(x) \ + ((x) & (~BITS_CAL_32K_REG_ADDR_8822B)) +#define BIT_GET_CAL_32K_REG_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822B) & \ + BIT_MASK_CAL_32K_REG_ADDR_8822B) +#define BIT_SET_CAL_32K_REG_ADDR_8822B(x, v) \ + (BIT_CLEAR_CAL_32K_REG_ADDR_8822B(x) | BIT_CAL_32K_REG_ADDR_8822B(v)) #define BIT_SHIFT_CAL_32K_REG_DATA_8822B 0 #define BIT_MASK_CAL_32K_REG_DATA_8822B 0xffff -#define BIT_CAL_32K_REG_DATA_8822B(x) (((x) & BIT_MASK_CAL_32K_REG_DATA_8822B) << BIT_SHIFT_CAL_32K_REG_DATA_8822B) -#define BIT_GET_CAL_32K_REG_DATA_8822B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822B) & BIT_MASK_CAL_32K_REG_DATA_8822B) - - +#define BIT_CAL_32K_REG_DATA_8822B(x) \ + (((x) & BIT_MASK_CAL_32K_REG_DATA_8822B) \ + << BIT_SHIFT_CAL_32K_REG_DATA_8822B) +#define BITS_CAL_32K_REG_DATA_8822B \ + (BIT_MASK_CAL_32K_REG_DATA_8822B << BIT_SHIFT_CAL_32K_REG_DATA_8822B) +#define BIT_CLEAR_CAL_32K_REG_DATA_8822B(x) \ + ((x) & (~BITS_CAL_32K_REG_DATA_8822B)) +#define BIT_GET_CAL_32K_REG_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822B) & \ + BIT_MASK_CAL_32K_REG_DATA_8822B) +#define BIT_SET_CAL_32K_REG_DATA_8822B(x, v) \ + (BIT_CLEAR_CAL_32K_REG_DATA_8822B(x) | BIT_CAL_32K_REG_DATA_8822B(v)) /* 2 REG_NOT_VALID_8822B */ /* 2 REG_C2HEVT_8822B */ -#define BIT_SHIFT_C2HEVT_MSG_8822B 0 -#define BIT_MASK_C2HEVT_MSG_8822B 0xffffffffffffffffffffffffffffffffL -#define BIT_C2HEVT_MSG_8822B(x) (((x) & BIT_MASK_C2HEVT_MSG_8822B) << BIT_SHIFT_C2HEVT_MSG_8822B) -#define BIT_GET_C2HEVT_MSG_8822B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_8822B) & BIT_MASK_C2HEVT_MSG_8822B) - - +#define BIT_SHIFT_C2HEVT_MSG_V1_8822B 0 +#define BIT_MASK_C2HEVT_MSG_V1_8822B 0xffffffffL +#define BIT_C2HEVT_MSG_V1_8822B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_V1_8822B) << BIT_SHIFT_C2HEVT_MSG_V1_8822B) +#define BITS_C2HEVT_MSG_V1_8822B \ + (BIT_MASK_C2HEVT_MSG_V1_8822B << BIT_SHIFT_C2HEVT_MSG_V1_8822B) +#define BIT_CLEAR_C2HEVT_MSG_V1_8822B(x) ((x) & (~BITS_C2HEVT_MSG_V1_8822B)) +#define BIT_GET_C2HEVT_MSG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8822B) & BIT_MASK_C2HEVT_MSG_V1_8822B) +#define BIT_SET_C2HEVT_MSG_V1_8822B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_V1_8822B(x) | BIT_C2HEVT_MSG_V1_8822B(v)) + +/* 2 REG_C2HEVT_1_8822B */ + +#define BIT_SHIFT_C2HEVT_MSG_1_8822B 0 +#define BIT_MASK_C2HEVT_MSG_1_8822B 0xffffffffL +#define BIT_C2HEVT_MSG_1_8822B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_1_8822B) << BIT_SHIFT_C2HEVT_MSG_1_8822B) +#define BITS_C2HEVT_MSG_1_8822B \ + (BIT_MASK_C2HEVT_MSG_1_8822B << BIT_SHIFT_C2HEVT_MSG_1_8822B) +#define BIT_CLEAR_C2HEVT_MSG_1_8822B(x) ((x) & (~BITS_C2HEVT_MSG_1_8822B)) +#define BIT_GET_C2HEVT_MSG_1_8822B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8822B) & BIT_MASK_C2HEVT_MSG_1_8822B) +#define BIT_SET_C2HEVT_MSG_1_8822B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_1_8822B(x) | BIT_C2HEVT_MSG_1_8822B(v)) + +/* 2 REG_C2HEVT_2_8822B */ + +#define BIT_SHIFT_C2HEVT_MSG_2_8822B 0 +#define BIT_MASK_C2HEVT_MSG_2_8822B 0xffffffffL +#define BIT_C2HEVT_MSG_2_8822B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_2_8822B) << BIT_SHIFT_C2HEVT_MSG_2_8822B) +#define BITS_C2HEVT_MSG_2_8822B \ + (BIT_MASK_C2HEVT_MSG_2_8822B << BIT_SHIFT_C2HEVT_MSG_2_8822B) +#define BIT_CLEAR_C2HEVT_MSG_2_8822B(x) ((x) & (~BITS_C2HEVT_MSG_2_8822B)) +#define BIT_GET_C2HEVT_MSG_2_8822B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8822B) & BIT_MASK_C2HEVT_MSG_2_8822B) +#define BIT_SET_C2HEVT_MSG_2_8822B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_2_8822B(x) | BIT_C2HEVT_MSG_2_8822B(v)) + +/* 2 REG_C2HEVT_3_8822B */ + +#define BIT_SHIFT_C2HEVT_MSG_3_8822B 0 +#define BIT_MASK_C2HEVT_MSG_3_8822B 0xffffffffL +#define BIT_C2HEVT_MSG_3_8822B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_3_8822B) << BIT_SHIFT_C2HEVT_MSG_3_8822B) +#define BITS_C2HEVT_MSG_3_8822B \ + (BIT_MASK_C2HEVT_MSG_3_8822B << BIT_SHIFT_C2HEVT_MSG_3_8822B) +#define BIT_CLEAR_C2HEVT_MSG_3_8822B(x) ((x) & (~BITS_C2HEVT_MSG_3_8822B)) +#define BIT_GET_C2HEVT_MSG_3_8822B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8822B) & BIT_MASK_C2HEVT_MSG_3_8822B) +#define BIT_SET_C2HEVT_MSG_3_8822B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_3_8822B(x) | BIT_C2HEVT_MSG_3_8822B(v)) /* 2 REG_SW_DEFINED_PAGE1_8822B */ #define BIT_SHIFT_SW_DEFINED_PAGE1_8822B 0 #define BIT_MASK_SW_DEFINED_PAGE1_8822B 0xffffffffffffffffL -#define BIT_SW_DEFINED_PAGE1_8822B(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_8822B) << BIT_SHIFT_SW_DEFINED_PAGE1_8822B) -#define BIT_GET_SW_DEFINED_PAGE1_8822B(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8822B) & BIT_MASK_SW_DEFINED_PAGE1_8822B) - - +#define BIT_SW_DEFINED_PAGE1_8822B(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1_8822B) \ + << BIT_SHIFT_SW_DEFINED_PAGE1_8822B) +#define BITS_SW_DEFINED_PAGE1_8822B \ + (BIT_MASK_SW_DEFINED_PAGE1_8822B << BIT_SHIFT_SW_DEFINED_PAGE1_8822B) +#define BIT_CLEAR_SW_DEFINED_PAGE1_8822B(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE1_8822B)) +#define BIT_GET_SW_DEFINED_PAGE1_8822B(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8822B) & \ + BIT_MASK_SW_DEFINED_PAGE1_8822B) +#define BIT_SET_SW_DEFINED_PAGE1_8822B(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1_8822B(x) | BIT_SW_DEFINED_PAGE1_8822B(v)) /* 2 REG_MCUTST_I_8822B */ #define BIT_SHIFT_MCUDMSG_I_8822B 0 #define BIT_MASK_MCUDMSG_I_8822B 0xffffffffL -#define BIT_MCUDMSG_I_8822B(x) (((x) & BIT_MASK_MCUDMSG_I_8822B) << BIT_SHIFT_MCUDMSG_I_8822B) -#define BIT_GET_MCUDMSG_I_8822B(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8822B) & BIT_MASK_MCUDMSG_I_8822B) - - +#define BIT_MCUDMSG_I_8822B(x) \ + (((x) & BIT_MASK_MCUDMSG_I_8822B) << BIT_SHIFT_MCUDMSG_I_8822B) +#define BITS_MCUDMSG_I_8822B \ + (BIT_MASK_MCUDMSG_I_8822B << BIT_SHIFT_MCUDMSG_I_8822B) +#define BIT_CLEAR_MCUDMSG_I_8822B(x) ((x) & (~BITS_MCUDMSG_I_8822B)) +#define BIT_GET_MCUDMSG_I_8822B(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_I_8822B) & BIT_MASK_MCUDMSG_I_8822B) +#define BIT_SET_MCUDMSG_I_8822B(x, v) \ + (BIT_CLEAR_MCUDMSG_I_8822B(x) | BIT_MCUDMSG_I_8822B(v)) /* 2 REG_MCUTST_II_8822B */ #define BIT_SHIFT_MCUDMSG_II_8822B 0 #define BIT_MASK_MCUDMSG_II_8822B 0xffffffffL -#define BIT_MCUDMSG_II_8822B(x) (((x) & BIT_MASK_MCUDMSG_II_8822B) << BIT_SHIFT_MCUDMSG_II_8822B) -#define BIT_GET_MCUDMSG_II_8822B(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8822B) & BIT_MASK_MCUDMSG_II_8822B) - - +#define BIT_MCUDMSG_II_8822B(x) \ + (((x) & BIT_MASK_MCUDMSG_II_8822B) << BIT_SHIFT_MCUDMSG_II_8822B) +#define BITS_MCUDMSG_II_8822B \ + (BIT_MASK_MCUDMSG_II_8822B << BIT_SHIFT_MCUDMSG_II_8822B) +#define BIT_CLEAR_MCUDMSG_II_8822B(x) ((x) & (~BITS_MCUDMSG_II_8822B)) +#define BIT_GET_MCUDMSG_II_8822B(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_II_8822B) & BIT_MASK_MCUDMSG_II_8822B) +#define BIT_SET_MCUDMSG_II_8822B(x, v) \ + (BIT_CLEAR_MCUDMSG_II_8822B(x) | BIT_MCUDMSG_II_8822B(v)) /* 2 REG_FMETHR_8822B */ #define BIT_FMSG_INT_8822B BIT(31) #define BIT_SHIFT_FW_MSG_8822B 0 #define BIT_MASK_FW_MSG_8822B 0xffffffffL -#define BIT_FW_MSG_8822B(x) (((x) & BIT_MASK_FW_MSG_8822B) << BIT_SHIFT_FW_MSG_8822B) -#define BIT_GET_FW_MSG_8822B(x) (((x) >> BIT_SHIFT_FW_MSG_8822B) & BIT_MASK_FW_MSG_8822B) - - +#define BIT_FW_MSG_8822B(x) \ + (((x) & BIT_MASK_FW_MSG_8822B) << BIT_SHIFT_FW_MSG_8822B) +#define BITS_FW_MSG_8822B (BIT_MASK_FW_MSG_8822B << BIT_SHIFT_FW_MSG_8822B) +#define BIT_CLEAR_FW_MSG_8822B(x) ((x) & (~BITS_FW_MSG_8822B)) +#define BIT_GET_FW_MSG_8822B(x) \ + (((x) >> BIT_SHIFT_FW_MSG_8822B) & BIT_MASK_FW_MSG_8822B) +#define BIT_SET_FW_MSG_8822B(x, v) \ + (BIT_CLEAR_FW_MSG_8822B(x) | BIT_FW_MSG_8822B(v)) /* 2 REG_HMETFR_8822B */ #define BIT_SHIFT_HRCV_MSG_8822B 24 #define BIT_MASK_HRCV_MSG_8822B 0xff -#define BIT_HRCV_MSG_8822B(x) (((x) & BIT_MASK_HRCV_MSG_8822B) << BIT_SHIFT_HRCV_MSG_8822B) -#define BIT_GET_HRCV_MSG_8822B(x) (((x) >> BIT_SHIFT_HRCV_MSG_8822B) & BIT_MASK_HRCV_MSG_8822B) - +#define BIT_HRCV_MSG_8822B(x) \ + (((x) & BIT_MASK_HRCV_MSG_8822B) << BIT_SHIFT_HRCV_MSG_8822B) +#define BITS_HRCV_MSG_8822B \ + (BIT_MASK_HRCV_MSG_8822B << BIT_SHIFT_HRCV_MSG_8822B) +#define BIT_CLEAR_HRCV_MSG_8822B(x) ((x) & (~BITS_HRCV_MSG_8822B)) +#define BIT_GET_HRCV_MSG_8822B(x) \ + (((x) >> BIT_SHIFT_HRCV_MSG_8822B) & BIT_MASK_HRCV_MSG_8822B) +#define BIT_SET_HRCV_MSG_8822B(x, v) \ + (BIT_CLEAR_HRCV_MSG_8822B(x) | BIT_HRCV_MSG_8822B(v)) #define BIT_INT_BOX3_8822B BIT(3) #define BIT_INT_BOX2_8822B BIT(2) @@ -2795,91 +4091,152 @@ #define BIT_SHIFT_HOST_MSG_0_8822B 0 #define BIT_MASK_HOST_MSG_0_8822B 0xffffffffL -#define BIT_HOST_MSG_0_8822B(x) (((x) & BIT_MASK_HOST_MSG_0_8822B) << BIT_SHIFT_HOST_MSG_0_8822B) -#define BIT_GET_HOST_MSG_0_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8822B) & BIT_MASK_HOST_MSG_0_8822B) - - +#define BIT_HOST_MSG_0_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_0_8822B) << BIT_SHIFT_HOST_MSG_0_8822B) +#define BITS_HOST_MSG_0_8822B \ + (BIT_MASK_HOST_MSG_0_8822B << BIT_SHIFT_HOST_MSG_0_8822B) +#define BIT_CLEAR_HOST_MSG_0_8822B(x) ((x) & (~BITS_HOST_MSG_0_8822B)) +#define BIT_GET_HOST_MSG_0_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_0_8822B) & BIT_MASK_HOST_MSG_0_8822B) +#define BIT_SET_HOST_MSG_0_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_0_8822B(x) | BIT_HOST_MSG_0_8822B(v)) /* 2 REG_HMEBOX1_8822B */ #define BIT_SHIFT_HOST_MSG_1_8822B 0 #define BIT_MASK_HOST_MSG_1_8822B 0xffffffffL -#define BIT_HOST_MSG_1_8822B(x) (((x) & BIT_MASK_HOST_MSG_1_8822B) << BIT_SHIFT_HOST_MSG_1_8822B) -#define BIT_GET_HOST_MSG_1_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8822B) & BIT_MASK_HOST_MSG_1_8822B) - - +#define BIT_HOST_MSG_1_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_1_8822B) << BIT_SHIFT_HOST_MSG_1_8822B) +#define BITS_HOST_MSG_1_8822B \ + (BIT_MASK_HOST_MSG_1_8822B << BIT_SHIFT_HOST_MSG_1_8822B) +#define BIT_CLEAR_HOST_MSG_1_8822B(x) ((x) & (~BITS_HOST_MSG_1_8822B)) +#define BIT_GET_HOST_MSG_1_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_1_8822B) & BIT_MASK_HOST_MSG_1_8822B) +#define BIT_SET_HOST_MSG_1_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_1_8822B(x) | BIT_HOST_MSG_1_8822B(v)) /* 2 REG_HMEBOX2_8822B */ #define BIT_SHIFT_HOST_MSG_2_8822B 0 #define BIT_MASK_HOST_MSG_2_8822B 0xffffffffL -#define BIT_HOST_MSG_2_8822B(x) (((x) & BIT_MASK_HOST_MSG_2_8822B) << BIT_SHIFT_HOST_MSG_2_8822B) -#define BIT_GET_HOST_MSG_2_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8822B) & BIT_MASK_HOST_MSG_2_8822B) - - +#define BIT_HOST_MSG_2_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_2_8822B) << BIT_SHIFT_HOST_MSG_2_8822B) +#define BITS_HOST_MSG_2_8822B \ + (BIT_MASK_HOST_MSG_2_8822B << BIT_SHIFT_HOST_MSG_2_8822B) +#define BIT_CLEAR_HOST_MSG_2_8822B(x) ((x) & (~BITS_HOST_MSG_2_8822B)) +#define BIT_GET_HOST_MSG_2_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_2_8822B) & BIT_MASK_HOST_MSG_2_8822B) +#define BIT_SET_HOST_MSG_2_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_2_8822B(x) | BIT_HOST_MSG_2_8822B(v)) /* 2 REG_HMEBOX3_8822B */ #define BIT_SHIFT_HOST_MSG_3_8822B 0 #define BIT_MASK_HOST_MSG_3_8822B 0xffffffffL -#define BIT_HOST_MSG_3_8822B(x) (((x) & BIT_MASK_HOST_MSG_3_8822B) << BIT_SHIFT_HOST_MSG_3_8822B) -#define BIT_GET_HOST_MSG_3_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8822B) & BIT_MASK_HOST_MSG_3_8822B) - - +#define BIT_HOST_MSG_3_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_3_8822B) << BIT_SHIFT_HOST_MSG_3_8822B) +#define BITS_HOST_MSG_3_8822B \ + (BIT_MASK_HOST_MSG_3_8822B << BIT_SHIFT_HOST_MSG_3_8822B) +#define BIT_CLEAR_HOST_MSG_3_8822B(x) ((x) & (~BITS_HOST_MSG_3_8822B)) +#define BIT_GET_HOST_MSG_3_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_3_8822B) & BIT_MASK_HOST_MSG_3_8822B) +#define BIT_SET_HOST_MSG_3_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_3_8822B(x) | BIT_HOST_MSG_3_8822B(v)) /* 2 REG_LLT_INIT_8822B */ #define BIT_SHIFT_LLTE_RWM_8822B 30 #define BIT_MASK_LLTE_RWM_8822B 0x3 -#define BIT_LLTE_RWM_8822B(x) (((x) & BIT_MASK_LLTE_RWM_8822B) << BIT_SHIFT_LLTE_RWM_8822B) -#define BIT_GET_LLTE_RWM_8822B(x) (((x) >> BIT_SHIFT_LLTE_RWM_8822B) & BIT_MASK_LLTE_RWM_8822B) - - +#define BIT_LLTE_RWM_8822B(x) \ + (((x) & BIT_MASK_LLTE_RWM_8822B) << BIT_SHIFT_LLTE_RWM_8822B) +#define BITS_LLTE_RWM_8822B \ + (BIT_MASK_LLTE_RWM_8822B << BIT_SHIFT_LLTE_RWM_8822B) +#define BIT_CLEAR_LLTE_RWM_8822B(x) ((x) & (~BITS_LLTE_RWM_8822B)) +#define BIT_GET_LLTE_RWM_8822B(x) \ + (((x) >> BIT_SHIFT_LLTE_RWM_8822B) & BIT_MASK_LLTE_RWM_8822B) +#define BIT_SET_LLTE_RWM_8822B(x, v) \ + (BIT_CLEAR_LLTE_RWM_8822B(x) | BIT_LLTE_RWM_8822B(v)) #define BIT_SHIFT_LLTINI_PDATA_V1_8822B 16 #define BIT_MASK_LLTINI_PDATA_V1_8822B 0xfff -#define BIT_LLTINI_PDATA_V1_8822B(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8822B) << BIT_SHIFT_LLTINI_PDATA_V1_8822B) -#define BIT_GET_LLTINI_PDATA_V1_8822B(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8822B) & BIT_MASK_LLTINI_PDATA_V1_8822B) - - +#define BIT_LLTINI_PDATA_V1_8822B(x) \ + (((x) & BIT_MASK_LLTINI_PDATA_V1_8822B) \ + << BIT_SHIFT_LLTINI_PDATA_V1_8822B) +#define BITS_LLTINI_PDATA_V1_8822B \ + (BIT_MASK_LLTINI_PDATA_V1_8822B << BIT_SHIFT_LLTINI_PDATA_V1_8822B) +#define BIT_CLEAR_LLTINI_PDATA_V1_8822B(x) ((x) & (~BITS_LLTINI_PDATA_V1_8822B)) +#define BIT_GET_LLTINI_PDATA_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8822B) & \ + BIT_MASK_LLTINI_PDATA_V1_8822B) +#define BIT_SET_LLTINI_PDATA_V1_8822B(x, v) \ + (BIT_CLEAR_LLTINI_PDATA_V1_8822B(x) | BIT_LLTINI_PDATA_V1_8822B(v)) #define BIT_SHIFT_LLTINI_HDATA_V1_8822B 0 #define BIT_MASK_LLTINI_HDATA_V1_8822B 0xfff -#define BIT_LLTINI_HDATA_V1_8822B(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8822B) << BIT_SHIFT_LLTINI_HDATA_V1_8822B) -#define BIT_GET_LLTINI_HDATA_V1_8822B(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8822B) & BIT_MASK_LLTINI_HDATA_V1_8822B) - - +#define BIT_LLTINI_HDATA_V1_8822B(x) \ + (((x) & BIT_MASK_LLTINI_HDATA_V1_8822B) \ + << BIT_SHIFT_LLTINI_HDATA_V1_8822B) +#define BITS_LLTINI_HDATA_V1_8822B \ + (BIT_MASK_LLTINI_HDATA_V1_8822B << BIT_SHIFT_LLTINI_HDATA_V1_8822B) +#define BIT_CLEAR_LLTINI_HDATA_V1_8822B(x) ((x) & (~BITS_LLTINI_HDATA_V1_8822B)) +#define BIT_GET_LLTINI_HDATA_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8822B) & \ + BIT_MASK_LLTINI_HDATA_V1_8822B) +#define BIT_SET_LLTINI_HDATA_V1_8822B(x, v) \ + (BIT_CLEAR_LLTINI_HDATA_V1_8822B(x) | BIT_LLTINI_HDATA_V1_8822B(v)) /* 2 REG_LLT_INIT_ADDR_8822B */ #define BIT_SHIFT_LLTINI_ADDR_V1_8822B 0 #define BIT_MASK_LLTINI_ADDR_V1_8822B 0xfff -#define BIT_LLTINI_ADDR_V1_8822B(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8822B) << BIT_SHIFT_LLTINI_ADDR_V1_8822B) -#define BIT_GET_LLTINI_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8822B) & BIT_MASK_LLTINI_ADDR_V1_8822B) - - +#define BIT_LLTINI_ADDR_V1_8822B(x) \ + (((x) & BIT_MASK_LLTINI_ADDR_V1_8822B) \ + << BIT_SHIFT_LLTINI_ADDR_V1_8822B) +#define BITS_LLTINI_ADDR_V1_8822B \ + (BIT_MASK_LLTINI_ADDR_V1_8822B << BIT_SHIFT_LLTINI_ADDR_V1_8822B) +#define BIT_CLEAR_LLTINI_ADDR_V1_8822B(x) ((x) & (~BITS_LLTINI_ADDR_V1_8822B)) +#define BIT_GET_LLTINI_ADDR_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8822B) & \ + BIT_MASK_LLTINI_ADDR_V1_8822B) +#define BIT_SET_LLTINI_ADDR_V1_8822B(x, v) \ + (BIT_CLEAR_LLTINI_ADDR_V1_8822B(x) | BIT_LLTINI_ADDR_V1_8822B(v)) /* 2 REG_BB_ACCESS_CTRL_8822B */ #define BIT_SHIFT_BB_WRITE_READ_8822B 30 #define BIT_MASK_BB_WRITE_READ_8822B 0x3 -#define BIT_BB_WRITE_READ_8822B(x) (((x) & BIT_MASK_BB_WRITE_READ_8822B) << BIT_SHIFT_BB_WRITE_READ_8822B) -#define BIT_GET_BB_WRITE_READ_8822B(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8822B) & BIT_MASK_BB_WRITE_READ_8822B) - - +#define BIT_BB_WRITE_READ_8822B(x) \ + (((x) & BIT_MASK_BB_WRITE_READ_8822B) << BIT_SHIFT_BB_WRITE_READ_8822B) +#define BITS_BB_WRITE_READ_8822B \ + (BIT_MASK_BB_WRITE_READ_8822B << BIT_SHIFT_BB_WRITE_READ_8822B) +#define BIT_CLEAR_BB_WRITE_READ_8822B(x) ((x) & (~BITS_BB_WRITE_READ_8822B)) +#define BIT_GET_BB_WRITE_READ_8822B(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_READ_8822B) & BIT_MASK_BB_WRITE_READ_8822B) +#define BIT_SET_BB_WRITE_READ_8822B(x, v) \ + (BIT_CLEAR_BB_WRITE_READ_8822B(x) | BIT_BB_WRITE_READ_8822B(v)) #define BIT_SHIFT_BB_WRITE_EN_8822B 12 #define BIT_MASK_BB_WRITE_EN_8822B 0xf -#define BIT_BB_WRITE_EN_8822B(x) (((x) & BIT_MASK_BB_WRITE_EN_8822B) << BIT_SHIFT_BB_WRITE_EN_8822B) -#define BIT_GET_BB_WRITE_EN_8822B(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_8822B) & BIT_MASK_BB_WRITE_EN_8822B) - - +#define BIT_BB_WRITE_EN_8822B(x) \ + (((x) & BIT_MASK_BB_WRITE_EN_8822B) << BIT_SHIFT_BB_WRITE_EN_8822B) +#define BITS_BB_WRITE_EN_8822B \ + (BIT_MASK_BB_WRITE_EN_8822B << BIT_SHIFT_BB_WRITE_EN_8822B) +#define BIT_CLEAR_BB_WRITE_EN_8822B(x) ((x) & (~BITS_BB_WRITE_EN_8822B)) +#define BIT_GET_BB_WRITE_EN_8822B(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN_8822B) & BIT_MASK_BB_WRITE_EN_8822B) +#define BIT_SET_BB_WRITE_EN_8822B(x, v) \ + (BIT_CLEAR_BB_WRITE_EN_8822B(x) | BIT_BB_WRITE_EN_8822B(v)) #define BIT_SHIFT_BB_ADDR_8822B 2 #define BIT_MASK_BB_ADDR_8822B 0x1ff -#define BIT_BB_ADDR_8822B(x) (((x) & BIT_MASK_BB_ADDR_8822B) << BIT_SHIFT_BB_ADDR_8822B) -#define BIT_GET_BB_ADDR_8822B(x) (((x) >> BIT_SHIFT_BB_ADDR_8822B) & BIT_MASK_BB_ADDR_8822B) - +#define BIT_BB_ADDR_8822B(x) \ + (((x) & BIT_MASK_BB_ADDR_8822B) << BIT_SHIFT_BB_ADDR_8822B) +#define BITS_BB_ADDR_8822B (BIT_MASK_BB_ADDR_8822B << BIT_SHIFT_BB_ADDR_8822B) +#define BIT_CLEAR_BB_ADDR_8822B(x) ((x) & (~BITS_BB_ADDR_8822B)) +#define BIT_GET_BB_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_BB_ADDR_8822B) & BIT_MASK_BB_ADDR_8822B) +#define BIT_SET_BB_ADDR_8822B(x, v) \ + (BIT_CLEAR_BB_ADDR_8822B(x) | BIT_BB_ADDR_8822B(v)) #define BIT_BB_ERRACC_8822B BIT(0) @@ -2887,46 +4244,70 @@ #define BIT_SHIFT_BB_DATA_8822B 0 #define BIT_MASK_BB_DATA_8822B 0xffffffffL -#define BIT_BB_DATA_8822B(x) (((x) & BIT_MASK_BB_DATA_8822B) << BIT_SHIFT_BB_DATA_8822B) -#define BIT_GET_BB_DATA_8822B(x) (((x) >> BIT_SHIFT_BB_DATA_8822B) & BIT_MASK_BB_DATA_8822B) - - +#define BIT_BB_DATA_8822B(x) \ + (((x) & BIT_MASK_BB_DATA_8822B) << BIT_SHIFT_BB_DATA_8822B) +#define BITS_BB_DATA_8822B (BIT_MASK_BB_DATA_8822B << BIT_SHIFT_BB_DATA_8822B) +#define BIT_CLEAR_BB_DATA_8822B(x) ((x) & (~BITS_BB_DATA_8822B)) +#define BIT_GET_BB_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_BB_DATA_8822B) & BIT_MASK_BB_DATA_8822B) +#define BIT_SET_BB_DATA_8822B(x, v) \ + (BIT_CLEAR_BB_DATA_8822B(x) | BIT_BB_DATA_8822B(v)) /* 2 REG_HMEBOX_E0_8822B */ #define BIT_SHIFT_HMEBOX_E0_8822B 0 #define BIT_MASK_HMEBOX_E0_8822B 0xffffffffL -#define BIT_HMEBOX_E0_8822B(x) (((x) & BIT_MASK_HMEBOX_E0_8822B) << BIT_SHIFT_HMEBOX_E0_8822B) -#define BIT_GET_HMEBOX_E0_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8822B) & BIT_MASK_HMEBOX_E0_8822B) - - +#define BIT_HMEBOX_E0_8822B(x) \ + (((x) & BIT_MASK_HMEBOX_E0_8822B) << BIT_SHIFT_HMEBOX_E0_8822B) +#define BITS_HMEBOX_E0_8822B \ + (BIT_MASK_HMEBOX_E0_8822B << BIT_SHIFT_HMEBOX_E0_8822B) +#define BIT_CLEAR_HMEBOX_E0_8822B(x) ((x) & (~BITS_HMEBOX_E0_8822B)) +#define BIT_GET_HMEBOX_E0_8822B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E0_8822B) & BIT_MASK_HMEBOX_E0_8822B) +#define BIT_SET_HMEBOX_E0_8822B(x, v) \ + (BIT_CLEAR_HMEBOX_E0_8822B(x) | BIT_HMEBOX_E0_8822B(v)) /* 2 REG_HMEBOX_E1_8822B */ #define BIT_SHIFT_HMEBOX_E1_8822B 0 #define BIT_MASK_HMEBOX_E1_8822B 0xffffffffL -#define BIT_HMEBOX_E1_8822B(x) (((x) & BIT_MASK_HMEBOX_E1_8822B) << BIT_SHIFT_HMEBOX_E1_8822B) -#define BIT_GET_HMEBOX_E1_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8822B) & BIT_MASK_HMEBOX_E1_8822B) - - +#define BIT_HMEBOX_E1_8822B(x) \ + (((x) & BIT_MASK_HMEBOX_E1_8822B) << BIT_SHIFT_HMEBOX_E1_8822B) +#define BITS_HMEBOX_E1_8822B \ + (BIT_MASK_HMEBOX_E1_8822B << BIT_SHIFT_HMEBOX_E1_8822B) +#define BIT_CLEAR_HMEBOX_E1_8822B(x) ((x) & (~BITS_HMEBOX_E1_8822B)) +#define BIT_GET_HMEBOX_E1_8822B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E1_8822B) & BIT_MASK_HMEBOX_E1_8822B) +#define BIT_SET_HMEBOX_E1_8822B(x, v) \ + (BIT_CLEAR_HMEBOX_E1_8822B(x) | BIT_HMEBOX_E1_8822B(v)) /* 2 REG_HMEBOX_E2_8822B */ #define BIT_SHIFT_HMEBOX_E2_8822B 0 #define BIT_MASK_HMEBOX_E2_8822B 0xffffffffL -#define BIT_HMEBOX_E2_8822B(x) (((x) & BIT_MASK_HMEBOX_E2_8822B) << BIT_SHIFT_HMEBOX_E2_8822B) -#define BIT_GET_HMEBOX_E2_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8822B) & BIT_MASK_HMEBOX_E2_8822B) - - +#define BIT_HMEBOX_E2_8822B(x) \ + (((x) & BIT_MASK_HMEBOX_E2_8822B) << BIT_SHIFT_HMEBOX_E2_8822B) +#define BITS_HMEBOX_E2_8822B \ + (BIT_MASK_HMEBOX_E2_8822B << BIT_SHIFT_HMEBOX_E2_8822B) +#define BIT_CLEAR_HMEBOX_E2_8822B(x) ((x) & (~BITS_HMEBOX_E2_8822B)) +#define BIT_GET_HMEBOX_E2_8822B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E2_8822B) & BIT_MASK_HMEBOX_E2_8822B) +#define BIT_SET_HMEBOX_E2_8822B(x, v) \ + (BIT_CLEAR_HMEBOX_E2_8822B(x) | BIT_HMEBOX_E2_8822B(v)) /* 2 REG_HMEBOX_E3_8822B */ #define BIT_SHIFT_HMEBOX_E3_8822B 0 #define BIT_MASK_HMEBOX_E3_8822B 0xffffffffL -#define BIT_HMEBOX_E3_8822B(x) (((x) & BIT_MASK_HMEBOX_E3_8822B) << BIT_SHIFT_HMEBOX_E3_8822B) -#define BIT_GET_HMEBOX_E3_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8822B) & BIT_MASK_HMEBOX_E3_8822B) - - +#define BIT_HMEBOX_E3_8822B(x) \ + (((x) & BIT_MASK_HMEBOX_E3_8822B) << BIT_SHIFT_HMEBOX_E3_8822B) +#define BITS_HMEBOX_E3_8822B \ + (BIT_MASK_HMEBOX_E3_8822B << BIT_SHIFT_HMEBOX_E3_8822B) +#define BIT_CLEAR_HMEBOX_E3_8822B(x) ((x) & (~BITS_HMEBOX_E3_8822B)) +#define BIT_GET_HMEBOX_E3_8822B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E3_8822B) & BIT_MASK_HMEBOX_E3_8822B) +#define BIT_SET_HMEBOX_E3_8822B(x, v) \ + (BIT_CLEAR_HMEBOX_E3_8822B(x) | BIT_HMEBOX_E3_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -2934,55 +4315,88 @@ #define BIT_SHIFT_PHY_REQ_DELAY_8822B 24 #define BIT_MASK_PHY_REQ_DELAY_8822B 0xf -#define BIT_PHY_REQ_DELAY_8822B(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8822B) << BIT_SHIFT_PHY_REQ_DELAY_8822B) -#define BIT_GET_PHY_REQ_DELAY_8822B(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822B) & BIT_MASK_PHY_REQ_DELAY_8822B) - +#define BIT_PHY_REQ_DELAY_8822B(x) \ + (((x) & BIT_MASK_PHY_REQ_DELAY_8822B) << BIT_SHIFT_PHY_REQ_DELAY_8822B) +#define BITS_PHY_REQ_DELAY_8822B \ + (BIT_MASK_PHY_REQ_DELAY_8822B << BIT_SHIFT_PHY_REQ_DELAY_8822B) +#define BIT_CLEAR_PHY_REQ_DELAY_8822B(x) ((x) & (~BITS_PHY_REQ_DELAY_8822B)) +#define BIT_GET_PHY_REQ_DELAY_8822B(x) \ + (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822B) & BIT_MASK_PHY_REQ_DELAY_8822B) +#define BIT_SET_PHY_REQ_DELAY_8822B(x, v) \ + (BIT_CLEAR_PHY_REQ_DELAY_8822B(x) | BIT_PHY_REQ_DELAY_8822B(v)) #define BIT_SPD_DOWN_8822B BIT(16) #define BIT_SHIFT_NETYPE4_8822B 4 #define BIT_MASK_NETYPE4_8822B 0x3 -#define BIT_NETYPE4_8822B(x) (((x) & BIT_MASK_NETYPE4_8822B) << BIT_SHIFT_NETYPE4_8822B) -#define BIT_GET_NETYPE4_8822B(x) (((x) >> BIT_SHIFT_NETYPE4_8822B) & BIT_MASK_NETYPE4_8822B) - - +#define BIT_NETYPE4_8822B(x) \ + (((x) & BIT_MASK_NETYPE4_8822B) << BIT_SHIFT_NETYPE4_8822B) +#define BITS_NETYPE4_8822B (BIT_MASK_NETYPE4_8822B << BIT_SHIFT_NETYPE4_8822B) +#define BIT_CLEAR_NETYPE4_8822B(x) ((x) & (~BITS_NETYPE4_8822B)) +#define BIT_GET_NETYPE4_8822B(x) \ + (((x) >> BIT_SHIFT_NETYPE4_8822B) & BIT_MASK_NETYPE4_8822B) +#define BIT_SET_NETYPE4_8822B(x, v) \ + (BIT_CLEAR_NETYPE4_8822B(x) | BIT_NETYPE4_8822B(v)) #define BIT_SHIFT_NETYPE3_8822B 2 #define BIT_MASK_NETYPE3_8822B 0x3 -#define BIT_NETYPE3_8822B(x) (((x) & BIT_MASK_NETYPE3_8822B) << BIT_SHIFT_NETYPE3_8822B) -#define BIT_GET_NETYPE3_8822B(x) (((x) >> BIT_SHIFT_NETYPE3_8822B) & BIT_MASK_NETYPE3_8822B) - - +#define BIT_NETYPE3_8822B(x) \ + (((x) & BIT_MASK_NETYPE3_8822B) << BIT_SHIFT_NETYPE3_8822B) +#define BITS_NETYPE3_8822B (BIT_MASK_NETYPE3_8822B << BIT_SHIFT_NETYPE3_8822B) +#define BIT_CLEAR_NETYPE3_8822B(x) ((x) & (~BITS_NETYPE3_8822B)) +#define BIT_GET_NETYPE3_8822B(x) \ + (((x) >> BIT_SHIFT_NETYPE3_8822B) & BIT_MASK_NETYPE3_8822B) +#define BIT_SET_NETYPE3_8822B(x, v) \ + (BIT_CLEAR_NETYPE3_8822B(x) | BIT_NETYPE3_8822B(v)) #define BIT_SHIFT_NETYPE2_8822B 0 #define BIT_MASK_NETYPE2_8822B 0x3 -#define BIT_NETYPE2_8822B(x) (((x) & BIT_MASK_NETYPE2_8822B) << BIT_SHIFT_NETYPE2_8822B) -#define BIT_GET_NETYPE2_8822B(x) (((x) >> BIT_SHIFT_NETYPE2_8822B) & BIT_MASK_NETYPE2_8822B) - - +#define BIT_NETYPE2_8822B(x) \ + (((x) & BIT_MASK_NETYPE2_8822B) << BIT_SHIFT_NETYPE2_8822B) +#define BITS_NETYPE2_8822B (BIT_MASK_NETYPE2_8822B << BIT_SHIFT_NETYPE2_8822B) +#define BIT_CLEAR_NETYPE2_8822B(x) ((x) & (~BITS_NETYPE2_8822B)) +#define BIT_GET_NETYPE2_8822B(x) \ + (((x) >> BIT_SHIFT_NETYPE2_8822B) & BIT_MASK_NETYPE2_8822B) +#define BIT_SET_NETYPE2_8822B(x, v) \ + (BIT_CLEAR_NETYPE2_8822B(x) | BIT_NETYPE2_8822B(v)) /* 2 REG_FWFF_8822B */ #define BIT_SHIFT_PKTNUM_TH_V1_8822B 24 #define BIT_MASK_PKTNUM_TH_V1_8822B 0xff -#define BIT_PKTNUM_TH_V1_8822B(x) (((x) & BIT_MASK_PKTNUM_TH_V1_8822B) << BIT_SHIFT_PKTNUM_TH_V1_8822B) -#define BIT_GET_PKTNUM_TH_V1_8822B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822B) & BIT_MASK_PKTNUM_TH_V1_8822B) - - +#define BIT_PKTNUM_TH_V1_8822B(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V1_8822B) << BIT_SHIFT_PKTNUM_TH_V1_8822B) +#define BITS_PKTNUM_TH_V1_8822B \ + (BIT_MASK_PKTNUM_TH_V1_8822B << BIT_SHIFT_PKTNUM_TH_V1_8822B) +#define BIT_CLEAR_PKTNUM_TH_V1_8822B(x) ((x) & (~BITS_PKTNUM_TH_V1_8822B)) +#define BIT_GET_PKTNUM_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822B) & BIT_MASK_PKTNUM_TH_V1_8822B) +#define BIT_SET_PKTNUM_TH_V1_8822B(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V1_8822B(x) | BIT_PKTNUM_TH_V1_8822B(v)) #define BIT_SHIFT_TIMER_TH_8822B 16 #define BIT_MASK_TIMER_TH_8822B 0xff -#define BIT_TIMER_TH_8822B(x) (((x) & BIT_MASK_TIMER_TH_8822B) << BIT_SHIFT_TIMER_TH_8822B) -#define BIT_GET_TIMER_TH_8822B(x) (((x) >> BIT_SHIFT_TIMER_TH_8822B) & BIT_MASK_TIMER_TH_8822B) - - +#define BIT_TIMER_TH_8822B(x) \ + (((x) & BIT_MASK_TIMER_TH_8822B) << BIT_SHIFT_TIMER_TH_8822B) +#define BITS_TIMER_TH_8822B \ + (BIT_MASK_TIMER_TH_8822B << BIT_SHIFT_TIMER_TH_8822B) +#define BIT_CLEAR_TIMER_TH_8822B(x) ((x) & (~BITS_TIMER_TH_8822B)) +#define BIT_GET_TIMER_TH_8822B(x) \ + (((x) >> BIT_SHIFT_TIMER_TH_8822B) & BIT_MASK_TIMER_TH_8822B) +#define BIT_SET_TIMER_TH_8822B(x, v) \ + (BIT_CLEAR_TIMER_TH_8822B(x) | BIT_TIMER_TH_8822B(v)) #define BIT_SHIFT_RXPKT1ENADDR_8822B 0 #define BIT_MASK_RXPKT1ENADDR_8822B 0xffff -#define BIT_RXPKT1ENADDR_8822B(x) (((x) & BIT_MASK_RXPKT1ENADDR_8822B) << BIT_SHIFT_RXPKT1ENADDR_8822B) -#define BIT_GET_RXPKT1ENADDR_8822B(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8822B) & BIT_MASK_RXPKT1ENADDR_8822B) - - +#define BIT_RXPKT1ENADDR_8822B(x) \ + (((x) & BIT_MASK_RXPKT1ENADDR_8822B) << BIT_SHIFT_RXPKT1ENADDR_8822B) +#define BITS_RXPKT1ENADDR_8822B \ + (BIT_MASK_RXPKT1ENADDR_8822B << BIT_SHIFT_RXPKT1ENADDR_8822B) +#define BIT_CLEAR_RXPKT1ENADDR_8822B(x) ((x) & (~BITS_RXPKT1ENADDR_8822B)) +#define BIT_GET_RXPKT1ENADDR_8822B(x) \ + (((x) >> BIT_SHIFT_RXPKT1ENADDR_8822B) & BIT_MASK_RXPKT1ENADDR_8822B) +#define BIT_SET_RXPKT1ENADDR_8822B(x, v) \ + (BIT_CLEAR_RXPKT1ENADDR_8822B(x) | BIT_RXPKT1ENADDR_8822B(v)) /* 2 REG_RXFF_PTR_V1_8822B */ @@ -2990,10 +4404,17 @@ #define BIT_SHIFT_RXFF0_RDPTR_V2_8822B 0 #define BIT_MASK_RXFF0_RDPTR_V2_8822B 0x3ffff -#define BIT_RXFF0_RDPTR_V2_8822B(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8822B) << BIT_SHIFT_RXFF0_RDPTR_V2_8822B) -#define BIT_GET_RXFF0_RDPTR_V2_8822B(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822B) & BIT_MASK_RXFF0_RDPTR_V2_8822B) - - +#define BIT_RXFF0_RDPTR_V2_8822B(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V2_8822B) \ + << BIT_SHIFT_RXFF0_RDPTR_V2_8822B) +#define BITS_RXFF0_RDPTR_V2_8822B \ + (BIT_MASK_RXFF0_RDPTR_V2_8822B << BIT_SHIFT_RXFF0_RDPTR_V2_8822B) +#define BIT_CLEAR_RXFF0_RDPTR_V2_8822B(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8822B)) +#define BIT_GET_RXFF0_RDPTR_V2_8822B(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822B) & \ + BIT_MASK_RXFF0_RDPTR_V2_8822B) +#define BIT_SET_RXFF0_RDPTR_V2_8822B(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V2_8822B(x) | BIT_RXFF0_RDPTR_V2_8822B(v)) /* 2 REG_RXFF_WTR_V1_8822B */ @@ -3001,10 +4422,17 @@ #define BIT_SHIFT_RXFF0_WTPTR_V2_8822B 0 #define BIT_MASK_RXFF0_WTPTR_V2_8822B 0x3ffff -#define BIT_RXFF0_WTPTR_V2_8822B(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8822B) << BIT_SHIFT_RXFF0_WTPTR_V2_8822B) -#define BIT_GET_RXFF0_WTPTR_V2_8822B(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822B) & BIT_MASK_RXFF0_WTPTR_V2_8822B) - - +#define BIT_RXFF0_WTPTR_V2_8822B(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V2_8822B) \ + << BIT_SHIFT_RXFF0_WTPTR_V2_8822B) +#define BITS_RXFF0_WTPTR_V2_8822B \ + (BIT_MASK_RXFF0_WTPTR_V2_8822B << BIT_SHIFT_RXFF0_WTPTR_V2_8822B) +#define BIT_CLEAR_RXFF0_WTPTR_V2_8822B(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8822B)) +#define BIT_GET_RXFF0_WTPTR_V2_8822B(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822B) & \ + BIT_MASK_RXFF0_WTPTR_V2_8822B) +#define BIT_SET_RXFF0_WTPTR_V2_8822B(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V2_8822B(x) | BIT_RXFF0_WTPTR_V2_8822B(v)) /* 2 REG_FE2IMR_8822B */ #define BIT__FE4ISR__IND_MSK_8822B BIT(29) @@ -3238,53 +4666,82 @@ #define BIT_SHIFT_MID_31TO0_8822B 0 #define BIT_MASK_MID_31TO0_8822B 0xffffffffL -#define BIT_MID_31TO0_8822B(x) (((x) & BIT_MASK_MID_31TO0_8822B) << BIT_SHIFT_MID_31TO0_8822B) -#define BIT_GET_MID_31TO0_8822B(x) (((x) >> BIT_SHIFT_MID_31TO0_8822B) & BIT_MASK_MID_31TO0_8822B) - - +#define BIT_MID_31TO0_8822B(x) \ + (((x) & BIT_MASK_MID_31TO0_8822B) << BIT_SHIFT_MID_31TO0_8822B) +#define BITS_MID_31TO0_8822B \ + (BIT_MASK_MID_31TO0_8822B << BIT_SHIFT_MID_31TO0_8822B) +#define BIT_CLEAR_MID_31TO0_8822B(x) ((x) & (~BITS_MID_31TO0_8822B)) +#define BIT_GET_MID_31TO0_8822B(x) \ + (((x) >> BIT_SHIFT_MID_31TO0_8822B) & BIT_MASK_MID_31TO0_8822B) +#define BIT_SET_MID_31TO0_8822B(x, v) \ + (BIT_CLEAR_MID_31TO0_8822B(x) | BIT_MID_31TO0_8822B(v)) /* 2 REG_SPWR1_8822B */ #define BIT_SHIFT_MID_63TO32_8822B 0 #define BIT_MASK_MID_63TO32_8822B 0xffffffffL -#define BIT_MID_63TO32_8822B(x) (((x) & BIT_MASK_MID_63TO32_8822B) << BIT_SHIFT_MID_63TO32_8822B) -#define BIT_GET_MID_63TO32_8822B(x) (((x) >> BIT_SHIFT_MID_63TO32_8822B) & BIT_MASK_MID_63TO32_8822B) - - +#define BIT_MID_63TO32_8822B(x) \ + (((x) & BIT_MASK_MID_63TO32_8822B) << BIT_SHIFT_MID_63TO32_8822B) +#define BITS_MID_63TO32_8822B \ + (BIT_MASK_MID_63TO32_8822B << BIT_SHIFT_MID_63TO32_8822B) +#define BIT_CLEAR_MID_63TO32_8822B(x) ((x) & (~BITS_MID_63TO32_8822B)) +#define BIT_GET_MID_63TO32_8822B(x) \ + (((x) >> BIT_SHIFT_MID_63TO32_8822B) & BIT_MASK_MID_63TO32_8822B) +#define BIT_SET_MID_63TO32_8822B(x, v) \ + (BIT_CLEAR_MID_63TO32_8822B(x) | BIT_MID_63TO32_8822B(v)) /* 2 REG_SPWR2_8822B */ #define BIT_SHIFT_MID_95O64_8822B 0 #define BIT_MASK_MID_95O64_8822B 0xffffffffL -#define BIT_MID_95O64_8822B(x) (((x) & BIT_MASK_MID_95O64_8822B) << BIT_SHIFT_MID_95O64_8822B) -#define BIT_GET_MID_95O64_8822B(x) (((x) >> BIT_SHIFT_MID_95O64_8822B) & BIT_MASK_MID_95O64_8822B) - - +#define BIT_MID_95O64_8822B(x) \ + (((x) & BIT_MASK_MID_95O64_8822B) << BIT_SHIFT_MID_95O64_8822B) +#define BITS_MID_95O64_8822B \ + (BIT_MASK_MID_95O64_8822B << BIT_SHIFT_MID_95O64_8822B) +#define BIT_CLEAR_MID_95O64_8822B(x) ((x) & (~BITS_MID_95O64_8822B)) +#define BIT_GET_MID_95O64_8822B(x) \ + (((x) >> BIT_SHIFT_MID_95O64_8822B) & BIT_MASK_MID_95O64_8822B) +#define BIT_SET_MID_95O64_8822B(x, v) \ + (BIT_CLEAR_MID_95O64_8822B(x) | BIT_MID_95O64_8822B(v)) /* 2 REG_SPWR3_8822B */ #define BIT_SHIFT_MID_127TO96_8822B 0 #define BIT_MASK_MID_127TO96_8822B 0xffffffffL -#define BIT_MID_127TO96_8822B(x) (((x) & BIT_MASK_MID_127TO96_8822B) << BIT_SHIFT_MID_127TO96_8822B) -#define BIT_GET_MID_127TO96_8822B(x) (((x) >> BIT_SHIFT_MID_127TO96_8822B) & BIT_MASK_MID_127TO96_8822B) - - +#define BIT_MID_127TO96_8822B(x) \ + (((x) & BIT_MASK_MID_127TO96_8822B) << BIT_SHIFT_MID_127TO96_8822B) +#define BITS_MID_127TO96_8822B \ + (BIT_MASK_MID_127TO96_8822B << BIT_SHIFT_MID_127TO96_8822B) +#define BIT_CLEAR_MID_127TO96_8822B(x) ((x) & (~BITS_MID_127TO96_8822B)) +#define BIT_GET_MID_127TO96_8822B(x) \ + (((x) >> BIT_SHIFT_MID_127TO96_8822B) & BIT_MASK_MID_127TO96_8822B) +#define BIT_SET_MID_127TO96_8822B(x, v) \ + (BIT_CLEAR_MID_127TO96_8822B(x) | BIT_MID_127TO96_8822B(v)) /* 2 REG_POWSEQ_8822B */ #define BIT_SHIFT_SEQNUM_MID_8822B 16 #define BIT_MASK_SEQNUM_MID_8822B 0xffff -#define BIT_SEQNUM_MID_8822B(x) (((x) & BIT_MASK_SEQNUM_MID_8822B) << BIT_SHIFT_SEQNUM_MID_8822B) -#define BIT_GET_SEQNUM_MID_8822B(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8822B) & BIT_MASK_SEQNUM_MID_8822B) - - +#define BIT_SEQNUM_MID_8822B(x) \ + (((x) & BIT_MASK_SEQNUM_MID_8822B) << BIT_SHIFT_SEQNUM_MID_8822B) +#define BITS_SEQNUM_MID_8822B \ + (BIT_MASK_SEQNUM_MID_8822B << BIT_SHIFT_SEQNUM_MID_8822B) +#define BIT_CLEAR_SEQNUM_MID_8822B(x) ((x) & (~BITS_SEQNUM_MID_8822B)) +#define BIT_GET_SEQNUM_MID_8822B(x) \ + (((x) >> BIT_SHIFT_SEQNUM_MID_8822B) & BIT_MASK_SEQNUM_MID_8822B) +#define BIT_SET_SEQNUM_MID_8822B(x, v) \ + (BIT_CLEAR_SEQNUM_MID_8822B(x) | BIT_SEQNUM_MID_8822B(v)) #define BIT_SHIFT_REF_MID_8822B 0 #define BIT_MASK_REF_MID_8822B 0x7f -#define BIT_REF_MID_8822B(x) (((x) & BIT_MASK_REF_MID_8822B) << BIT_SHIFT_REF_MID_8822B) -#define BIT_GET_REF_MID_8822B(x) (((x) >> BIT_SHIFT_REF_MID_8822B) & BIT_MASK_REF_MID_8822B) - - +#define BIT_REF_MID_8822B(x) \ + (((x) & BIT_MASK_REF_MID_8822B) << BIT_SHIFT_REF_MID_8822B) +#define BITS_REF_MID_8822B (BIT_MASK_REF_MID_8822B << BIT_SHIFT_REF_MID_8822B) +#define BIT_CLEAR_REF_MID_8822B(x) ((x) & (~BITS_REF_MID_8822B)) +#define BIT_GET_REF_MID_8822B(x) \ + (((x) >> BIT_SHIFT_REF_MID_8822B) & BIT_MASK_REF_MID_8822B) +#define BIT_SET_REF_MID_8822B(x, v) \ + (BIT_CLEAR_REF_MID_8822B(x) | BIT_REF_MID_8822B(v)) /* 2 REG_TC7_CTRL_V1_8822B */ #define BIT_TC7INT_EN_8822B BIT(26) @@ -3293,10 +4750,14 @@ #define BIT_SHIFT_TC7DATA_8822B 0 #define BIT_MASK_TC7DATA_8822B 0xffffff -#define BIT_TC7DATA_8822B(x) (((x) & BIT_MASK_TC7DATA_8822B) << BIT_SHIFT_TC7DATA_8822B) -#define BIT_GET_TC7DATA_8822B(x) (((x) >> BIT_SHIFT_TC7DATA_8822B) & BIT_MASK_TC7DATA_8822B) - - +#define BIT_TC7DATA_8822B(x) \ + (((x) & BIT_MASK_TC7DATA_8822B) << BIT_SHIFT_TC7DATA_8822B) +#define BITS_TC7DATA_8822B (BIT_MASK_TC7DATA_8822B << BIT_SHIFT_TC7DATA_8822B) +#define BIT_CLEAR_TC7DATA_8822B(x) ((x) & (~BITS_TC7DATA_8822B)) +#define BIT_GET_TC7DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC7DATA_8822B) & BIT_MASK_TC7DATA_8822B) +#define BIT_SET_TC7DATA_8822B(x, v) \ + (BIT_CLEAR_TC7DATA_8822B(x) | BIT_TC7DATA_8822B(v)) /* 2 REG_TC8_CTRL_V1_8822B */ #define BIT_TC8INT_EN_8822B BIT(26) @@ -3305,10 +4766,14 @@ #define BIT_SHIFT_TC8DATA_8822B 0 #define BIT_MASK_TC8DATA_8822B 0xffffff -#define BIT_TC8DATA_8822B(x) (((x) & BIT_MASK_TC8DATA_8822B) << BIT_SHIFT_TC8DATA_8822B) -#define BIT_GET_TC8DATA_8822B(x) (((x) >> BIT_SHIFT_TC8DATA_8822B) & BIT_MASK_TC8DATA_8822B) - - +#define BIT_TC8DATA_8822B(x) \ + (((x) & BIT_MASK_TC8DATA_8822B) << BIT_SHIFT_TC8DATA_8822B) +#define BITS_TC8DATA_8822B (BIT_MASK_TC8DATA_8822B << BIT_SHIFT_TC8DATA_8822B) +#define BIT_CLEAR_TC8DATA_8822B(x) ((x) & (~BITS_TC8DATA_8822B)) +#define BIT_GET_TC8DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC8DATA_8822B) & BIT_MASK_TC8DATA_8822B) +#define BIT_SET_TC8DATA_8822B(x, v) \ + (BIT_CLEAR_TC8DATA_8822B(x) | BIT_TC8DATA_8822B(v)) /* 2 REG_FT2IMR_8822B */ #define BIT_FS_CLI3_RX_UAPSDMD1_EN_8822B BIT(31) @@ -3370,37 +4835,53 @@ #define BIT_SHIFT_FW_MSG2_8822B 0 #define BIT_MASK_FW_MSG2_8822B 0xffffffffL -#define BIT_FW_MSG2_8822B(x) (((x) & BIT_MASK_FW_MSG2_8822B) << BIT_SHIFT_FW_MSG2_8822B) -#define BIT_GET_FW_MSG2_8822B(x) (((x) >> BIT_SHIFT_FW_MSG2_8822B) & BIT_MASK_FW_MSG2_8822B) - - +#define BIT_FW_MSG2_8822B(x) \ + (((x) & BIT_MASK_FW_MSG2_8822B) << BIT_SHIFT_FW_MSG2_8822B) +#define BITS_FW_MSG2_8822B (BIT_MASK_FW_MSG2_8822B << BIT_SHIFT_FW_MSG2_8822B) +#define BIT_CLEAR_FW_MSG2_8822B(x) ((x) & (~BITS_FW_MSG2_8822B)) +#define BIT_GET_FW_MSG2_8822B(x) \ + (((x) >> BIT_SHIFT_FW_MSG2_8822B) & BIT_MASK_FW_MSG2_8822B) +#define BIT_SET_FW_MSG2_8822B(x, v) \ + (BIT_CLEAR_FW_MSG2_8822B(x) | BIT_FW_MSG2_8822B(v)) /* 2 REG_MSG3_8822B */ #define BIT_SHIFT_FW_MSG3_8822B 0 #define BIT_MASK_FW_MSG3_8822B 0xffffffffL -#define BIT_FW_MSG3_8822B(x) (((x) & BIT_MASK_FW_MSG3_8822B) << BIT_SHIFT_FW_MSG3_8822B) -#define BIT_GET_FW_MSG3_8822B(x) (((x) >> BIT_SHIFT_FW_MSG3_8822B) & BIT_MASK_FW_MSG3_8822B) - - +#define BIT_FW_MSG3_8822B(x) \ + (((x) & BIT_MASK_FW_MSG3_8822B) << BIT_SHIFT_FW_MSG3_8822B) +#define BITS_FW_MSG3_8822B (BIT_MASK_FW_MSG3_8822B << BIT_SHIFT_FW_MSG3_8822B) +#define BIT_CLEAR_FW_MSG3_8822B(x) ((x) & (~BITS_FW_MSG3_8822B)) +#define BIT_GET_FW_MSG3_8822B(x) \ + (((x) >> BIT_SHIFT_FW_MSG3_8822B) & BIT_MASK_FW_MSG3_8822B) +#define BIT_SET_FW_MSG3_8822B(x, v) \ + (BIT_CLEAR_FW_MSG3_8822B(x) | BIT_FW_MSG3_8822B(v)) /* 2 REG_MSG4_8822B */ #define BIT_SHIFT_FW_MSG4_8822B 0 #define BIT_MASK_FW_MSG4_8822B 0xffffffffL -#define BIT_FW_MSG4_8822B(x) (((x) & BIT_MASK_FW_MSG4_8822B) << BIT_SHIFT_FW_MSG4_8822B) -#define BIT_GET_FW_MSG4_8822B(x) (((x) >> BIT_SHIFT_FW_MSG4_8822B) & BIT_MASK_FW_MSG4_8822B) - - +#define BIT_FW_MSG4_8822B(x) \ + (((x) & BIT_MASK_FW_MSG4_8822B) << BIT_SHIFT_FW_MSG4_8822B) +#define BITS_FW_MSG4_8822B (BIT_MASK_FW_MSG4_8822B << BIT_SHIFT_FW_MSG4_8822B) +#define BIT_CLEAR_FW_MSG4_8822B(x) ((x) & (~BITS_FW_MSG4_8822B)) +#define BIT_GET_FW_MSG4_8822B(x) \ + (((x) >> BIT_SHIFT_FW_MSG4_8822B) & BIT_MASK_FW_MSG4_8822B) +#define BIT_SET_FW_MSG4_8822B(x, v) \ + (BIT_CLEAR_FW_MSG4_8822B(x) | BIT_FW_MSG4_8822B(v)) /* 2 REG_MSG5_8822B */ #define BIT_SHIFT_FW_MSG5_8822B 0 #define BIT_MASK_FW_MSG5_8822B 0xffffffffL -#define BIT_FW_MSG5_8822B(x) (((x) & BIT_MASK_FW_MSG5_8822B) << BIT_SHIFT_FW_MSG5_8822B) -#define BIT_GET_FW_MSG5_8822B(x) (((x) >> BIT_SHIFT_FW_MSG5_8822B) & BIT_MASK_FW_MSG5_8822B) - - +#define BIT_FW_MSG5_8822B(x) \ + (((x) & BIT_MASK_FW_MSG5_8822B) << BIT_SHIFT_FW_MSG5_8822B) +#define BITS_FW_MSG5_8822B (BIT_MASK_FW_MSG5_8822B << BIT_SHIFT_FW_MSG5_8822B) +#define BIT_CLEAR_FW_MSG5_8822B(x) ((x) & (~BITS_FW_MSG5_8822B)) +#define BIT_GET_FW_MSG5_8822B(x) \ + (((x) >> BIT_SHIFT_FW_MSG5_8822B) & BIT_MASK_FW_MSG5_8822B) +#define BIT_SET_FW_MSG5_8822B(x, v) \ + (BIT_CLEAR_FW_MSG5_8822B(x) | BIT_FW_MSG5_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -3408,57 +4889,112 @@ #define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B 16 #define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B 0xff -#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) -#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822B(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B) - - +#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(x) \ + (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B) \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) +#define BITS_TX_OQT_HE_FREE_SPACE_V1_8822B \ + (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822B(x) \ + ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8822B)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) & \ + BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B) +#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8822B(x, v) \ + (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822B(x) | \ + BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(v)) #define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B 0 #define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B 0xff -#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) -#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822B(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) - - +#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(x) \ + (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) +#define BITS_TX_OQT_NL_FREE_SPACE_V1_8822B \ + (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822B(x) \ + ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8822B)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) & \ + BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) +#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8822B(x, v) \ + (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822B(x) | \ + BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(v)) /* 2 REG_FIFOPAGE_CTRL_2_8822B */ #define BIT_BCN_VALID_1_V1_8822B BIT(31) #define BIT_SHIFT_BCN_HEAD_1_V1_8822B 16 #define BIT_MASK_BCN_HEAD_1_V1_8822B 0xfff -#define BIT_BCN_HEAD_1_V1_8822B(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8822B) << BIT_SHIFT_BCN_HEAD_1_V1_8822B) -#define BIT_GET_BCN_HEAD_1_V1_8822B(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822B) & BIT_MASK_BCN_HEAD_1_V1_8822B) - +#define BIT_BCN_HEAD_1_V1_8822B(x) \ + (((x) & BIT_MASK_BCN_HEAD_1_V1_8822B) << BIT_SHIFT_BCN_HEAD_1_V1_8822B) +#define BITS_BCN_HEAD_1_V1_8822B \ + (BIT_MASK_BCN_HEAD_1_V1_8822B << BIT_SHIFT_BCN_HEAD_1_V1_8822B) +#define BIT_CLEAR_BCN_HEAD_1_V1_8822B(x) ((x) & (~BITS_BCN_HEAD_1_V1_8822B)) +#define BIT_GET_BCN_HEAD_1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822B) & BIT_MASK_BCN_HEAD_1_V1_8822B) +#define BIT_SET_BCN_HEAD_1_V1_8822B(x, v) \ + (BIT_CLEAR_BCN_HEAD_1_V1_8822B(x) | BIT_BCN_HEAD_1_V1_8822B(v)) #define BIT_BCN_VALID_V1_8822B BIT(15) #define BIT_SHIFT_BCN_HEAD_V1_8822B 0 #define BIT_MASK_BCN_HEAD_V1_8822B 0xfff -#define BIT_BCN_HEAD_V1_8822B(x) (((x) & BIT_MASK_BCN_HEAD_V1_8822B) << BIT_SHIFT_BCN_HEAD_V1_8822B) -#define BIT_GET_BCN_HEAD_V1_8822B(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8822B) & BIT_MASK_BCN_HEAD_V1_8822B) - - +#define BIT_BCN_HEAD_V1_8822B(x) \ + (((x) & BIT_MASK_BCN_HEAD_V1_8822B) << BIT_SHIFT_BCN_HEAD_V1_8822B) +#define BITS_BCN_HEAD_V1_8822B \ + (BIT_MASK_BCN_HEAD_V1_8822B << BIT_SHIFT_BCN_HEAD_V1_8822B) +#define BIT_CLEAR_BCN_HEAD_V1_8822B(x) ((x) & (~BITS_BCN_HEAD_V1_8822B)) +#define BIT_GET_BCN_HEAD_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_V1_8822B) & BIT_MASK_BCN_HEAD_V1_8822B) +#define BIT_SET_BCN_HEAD_V1_8822B(x, v) \ + (BIT_CLEAR_BCN_HEAD_V1_8822B(x) | BIT_BCN_HEAD_V1_8822B(v)) /* 2 REG_AUTO_LLT_V1_8822B */ #define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 24 #define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 0xff -#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) -#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) - - +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) +#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B \ + (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) +#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) \ + ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) & \ + BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) +#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) | \ + BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(v)) #define BIT_SHIFT_LLT_FREE_PAGE_V1_8822B 8 #define BIT_MASK_LLT_FREE_PAGE_V1_8822B 0xffff -#define BIT_LLT_FREE_PAGE_V1_8822B(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8822B) << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) -#define BIT_GET_LLT_FREE_PAGE_V1_8822B(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) & BIT_MASK_LLT_FREE_PAGE_V1_8822B) - - +#define BIT_LLT_FREE_PAGE_V1_8822B(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8822B) \ + << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) +#define BITS_LLT_FREE_PAGE_V1_8822B \ + (BIT_MASK_LLT_FREE_PAGE_V1_8822B << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) +#define BIT_CLEAR_LLT_FREE_PAGE_V1_8822B(x) \ + ((x) & (~BITS_LLT_FREE_PAGE_V1_8822B)) +#define BIT_GET_LLT_FREE_PAGE_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) & \ + BIT_MASK_LLT_FREE_PAGE_V1_8822B) +#define BIT_SET_LLT_FREE_PAGE_V1_8822B(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V1_8822B(x) | BIT_LLT_FREE_PAGE_V1_8822B(v)) #define BIT_SHIFT_BLK_DESC_NUM_8822B 4 #define BIT_MASK_BLK_DESC_NUM_8822B 0xf -#define BIT_BLK_DESC_NUM_8822B(x) (((x) & BIT_MASK_BLK_DESC_NUM_8822B) << BIT_SHIFT_BLK_DESC_NUM_8822B) -#define BIT_GET_BLK_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8822B) & BIT_MASK_BLK_DESC_NUM_8822B) - +#define BIT_BLK_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_BLK_DESC_NUM_8822B) << BIT_SHIFT_BLK_DESC_NUM_8822B) +#define BITS_BLK_DESC_NUM_8822B \ + (BIT_MASK_BLK_DESC_NUM_8822B << BIT_SHIFT_BLK_DESC_NUM_8822B) +#define BIT_CLEAR_BLK_DESC_NUM_8822B(x) ((x) & (~BITS_BLK_DESC_NUM_8822B)) +#define BIT_GET_BLK_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_BLK_DESC_NUM_8822B) & BIT_MASK_BLK_DESC_NUM_8822B) +#define BIT_SET_BLK_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_BLK_DESC_NUM_8822B(x) | BIT_BLK_DESC_NUM_8822B(v)) #define BIT_R_BCN_HEAD_SEL_8822B BIT(3) #define BIT_R_EN_BCN_SW_HEAD_SEL_8822B BIT(2) @@ -3473,9 +5009,17 @@ #define BIT_SHIFT_PG_UNDER_TH_V1_8822B 16 #define BIT_MASK_PG_UNDER_TH_V1_8822B 0xfff -#define BIT_PG_UNDER_TH_V1_8822B(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8822B) << BIT_SHIFT_PG_UNDER_TH_V1_8822B) -#define BIT_GET_PG_UNDER_TH_V1_8822B(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822B) & BIT_MASK_PG_UNDER_TH_V1_8822B) - +#define BIT_PG_UNDER_TH_V1_8822B(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V1_8822B) \ + << BIT_SHIFT_PG_UNDER_TH_V1_8822B) +#define BITS_PG_UNDER_TH_V1_8822B \ + (BIT_MASK_PG_UNDER_TH_V1_8822B << BIT_SHIFT_PG_UNDER_TH_V1_8822B) +#define BIT_CLEAR_PG_UNDER_TH_V1_8822B(x) ((x) & (~BITS_PG_UNDER_TH_V1_8822B)) +#define BIT_GET_PG_UNDER_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822B) & \ + BIT_MASK_PG_UNDER_TH_V1_8822B) +#define BIT_SET_PG_UNDER_TH_V1_8822B(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V1_8822B(x) | BIT_PG_UNDER_TH_V1_8822B(v)) #define BIT_RESTORE_H2C_ADDRESS_8822B BIT(15) #define BIT_SDIO_TXDESC_CHKSUM_EN_8822B BIT(13) @@ -3487,10 +5031,15 @@ #define BIT_SHIFT_CHECK_OFFSET_8822B 0 #define BIT_MASK_CHECK_OFFSET_8822B 0xff -#define BIT_CHECK_OFFSET_8822B(x) (((x) & BIT_MASK_CHECK_OFFSET_8822B) << BIT_SHIFT_CHECK_OFFSET_8822B) -#define BIT_GET_CHECK_OFFSET_8822B(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8822B) & BIT_MASK_CHECK_OFFSET_8822B) - - +#define BIT_CHECK_OFFSET_8822B(x) \ + (((x) & BIT_MASK_CHECK_OFFSET_8822B) << BIT_SHIFT_CHECK_OFFSET_8822B) +#define BITS_CHECK_OFFSET_8822B \ + (BIT_MASK_CHECK_OFFSET_8822B << BIT_SHIFT_CHECK_OFFSET_8822B) +#define BIT_CLEAR_CHECK_OFFSET_8822B(x) ((x) & (~BITS_CHECK_OFFSET_8822B)) +#define BIT_GET_CHECK_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_CHECK_OFFSET_8822B) & BIT_MASK_CHECK_OFFSET_8822B) +#define BIT_SET_CHECK_OFFSET_8822B(x, v) \ + (BIT_CLEAR_CHECK_OFFSET_8822B(x) | BIT_CHECK_OFFSET_8822B(v)) /* 2 REG_TXDMA_STATUS_8822B */ #define BIT_HI_OQT_UDN_8822B BIT(17) @@ -3518,81 +5067,139 @@ #define BIT_SHIFT_HPQ_HIGH_TH_V1_8822B 16 #define BIT_MASK_HPQ_HIGH_TH_V1_8822B 0xfff -#define BIT_HPQ_HIGH_TH_V1_8822B(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822B) << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) -#define BIT_GET_HPQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) & BIT_MASK_HPQ_HIGH_TH_V1_8822B) - - +#define BIT_HPQ_HIGH_TH_V1_8822B(x) \ + (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822B) \ + << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) +#define BITS_HPQ_HIGH_TH_V1_8822B \ + (BIT_MASK_HPQ_HIGH_TH_V1_8822B << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) +#define BIT_CLEAR_HPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8822B)) +#define BIT_GET_HPQ_HIGH_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) & \ + BIT_MASK_HPQ_HIGH_TH_V1_8822B) +#define BIT_SET_HPQ_HIGH_TH_V1_8822B(x, v) \ + (BIT_CLEAR_HPQ_HIGH_TH_V1_8822B(x) | BIT_HPQ_HIGH_TH_V1_8822B(v)) #define BIT_SHIFT_HPQ_LOW_TH_V1_8822B 0 #define BIT_MASK_HPQ_LOW_TH_V1_8822B 0xfff -#define BIT_HPQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8822B) << BIT_SHIFT_HPQ_LOW_TH_V1_8822B) -#define BIT_GET_HPQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822B) & BIT_MASK_HPQ_LOW_TH_V1_8822B) - - +#define BIT_HPQ_LOW_TH_V1_8822B(x) \ + (((x) & BIT_MASK_HPQ_LOW_TH_V1_8822B) << BIT_SHIFT_HPQ_LOW_TH_V1_8822B) +#define BITS_HPQ_LOW_TH_V1_8822B \ + (BIT_MASK_HPQ_LOW_TH_V1_8822B << BIT_SHIFT_HPQ_LOW_TH_V1_8822B) +#define BIT_CLEAR_HPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8822B)) +#define BIT_GET_HPQ_LOW_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822B) & BIT_MASK_HPQ_LOW_TH_V1_8822B) +#define BIT_SET_HPQ_LOW_TH_V1_8822B(x, v) \ + (BIT_CLEAR_HPQ_LOW_TH_V1_8822B(x) | BIT_HPQ_LOW_TH_V1_8822B(v)) /* 2 REG_TQPNT2_8822B */ #define BIT_SHIFT_NPQ_HIGH_TH_V1_8822B 16 #define BIT_MASK_NPQ_HIGH_TH_V1_8822B 0xfff -#define BIT_NPQ_HIGH_TH_V1_8822B(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822B) << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) -#define BIT_GET_NPQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) & BIT_MASK_NPQ_HIGH_TH_V1_8822B) - - +#define BIT_NPQ_HIGH_TH_V1_8822B(x) \ + (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822B) \ + << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) +#define BITS_NPQ_HIGH_TH_V1_8822B \ + (BIT_MASK_NPQ_HIGH_TH_V1_8822B << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) +#define BIT_CLEAR_NPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8822B)) +#define BIT_GET_NPQ_HIGH_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) & \ + BIT_MASK_NPQ_HIGH_TH_V1_8822B) +#define BIT_SET_NPQ_HIGH_TH_V1_8822B(x, v) \ + (BIT_CLEAR_NPQ_HIGH_TH_V1_8822B(x) | BIT_NPQ_HIGH_TH_V1_8822B(v)) #define BIT_SHIFT_NPQ_LOW_TH_V1_8822B 0 #define BIT_MASK_NPQ_LOW_TH_V1_8822B 0xfff -#define BIT_NPQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8822B) << BIT_SHIFT_NPQ_LOW_TH_V1_8822B) -#define BIT_GET_NPQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822B) & BIT_MASK_NPQ_LOW_TH_V1_8822B) - - +#define BIT_NPQ_LOW_TH_V1_8822B(x) \ + (((x) & BIT_MASK_NPQ_LOW_TH_V1_8822B) << BIT_SHIFT_NPQ_LOW_TH_V1_8822B) +#define BITS_NPQ_LOW_TH_V1_8822B \ + (BIT_MASK_NPQ_LOW_TH_V1_8822B << BIT_SHIFT_NPQ_LOW_TH_V1_8822B) +#define BIT_CLEAR_NPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8822B)) +#define BIT_GET_NPQ_LOW_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822B) & BIT_MASK_NPQ_LOW_TH_V1_8822B) +#define BIT_SET_NPQ_LOW_TH_V1_8822B(x, v) \ + (BIT_CLEAR_NPQ_LOW_TH_V1_8822B(x) | BIT_NPQ_LOW_TH_V1_8822B(v)) /* 2 REG_TQPNT3_8822B */ #define BIT_SHIFT_LPQ_HIGH_TH_V1_8822B 16 #define BIT_MASK_LPQ_HIGH_TH_V1_8822B 0xfff -#define BIT_LPQ_HIGH_TH_V1_8822B(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822B) << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) -#define BIT_GET_LPQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) & BIT_MASK_LPQ_HIGH_TH_V1_8822B) - - +#define BIT_LPQ_HIGH_TH_V1_8822B(x) \ + (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822B) \ + << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) +#define BITS_LPQ_HIGH_TH_V1_8822B \ + (BIT_MASK_LPQ_HIGH_TH_V1_8822B << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) +#define BIT_CLEAR_LPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8822B)) +#define BIT_GET_LPQ_HIGH_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) & \ + BIT_MASK_LPQ_HIGH_TH_V1_8822B) +#define BIT_SET_LPQ_HIGH_TH_V1_8822B(x, v) \ + (BIT_CLEAR_LPQ_HIGH_TH_V1_8822B(x) | BIT_LPQ_HIGH_TH_V1_8822B(v)) #define BIT_SHIFT_LPQ_LOW_TH_V1_8822B 0 #define BIT_MASK_LPQ_LOW_TH_V1_8822B 0xfff -#define BIT_LPQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8822B) << BIT_SHIFT_LPQ_LOW_TH_V1_8822B) -#define BIT_GET_LPQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822B) & BIT_MASK_LPQ_LOW_TH_V1_8822B) - - +#define BIT_LPQ_LOW_TH_V1_8822B(x) \ + (((x) & BIT_MASK_LPQ_LOW_TH_V1_8822B) << BIT_SHIFT_LPQ_LOW_TH_V1_8822B) +#define BITS_LPQ_LOW_TH_V1_8822B \ + (BIT_MASK_LPQ_LOW_TH_V1_8822B << BIT_SHIFT_LPQ_LOW_TH_V1_8822B) +#define BIT_CLEAR_LPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8822B)) +#define BIT_GET_LPQ_LOW_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822B) & BIT_MASK_LPQ_LOW_TH_V1_8822B) +#define BIT_SET_LPQ_LOW_TH_V1_8822B(x, v) \ + (BIT_CLEAR_LPQ_LOW_TH_V1_8822B(x) | BIT_LPQ_LOW_TH_V1_8822B(v)) /* 2 REG_TQPNT4_8822B */ #define BIT_SHIFT_EXQ_HIGH_TH_V1_8822B 16 #define BIT_MASK_EXQ_HIGH_TH_V1_8822B 0xfff -#define BIT_EXQ_HIGH_TH_V1_8822B(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822B) << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) -#define BIT_GET_EXQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) & BIT_MASK_EXQ_HIGH_TH_V1_8822B) - - +#define BIT_EXQ_HIGH_TH_V1_8822B(x) \ + (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822B) \ + << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) +#define BITS_EXQ_HIGH_TH_V1_8822B \ + (BIT_MASK_EXQ_HIGH_TH_V1_8822B << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) +#define BIT_CLEAR_EXQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8822B)) +#define BIT_GET_EXQ_HIGH_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) & \ + BIT_MASK_EXQ_HIGH_TH_V1_8822B) +#define BIT_SET_EXQ_HIGH_TH_V1_8822B(x, v) \ + (BIT_CLEAR_EXQ_HIGH_TH_V1_8822B(x) | BIT_EXQ_HIGH_TH_V1_8822B(v)) #define BIT_SHIFT_EXQ_LOW_TH_V1_8822B 0 #define BIT_MASK_EXQ_LOW_TH_V1_8822B 0xfff -#define BIT_EXQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8822B) << BIT_SHIFT_EXQ_LOW_TH_V1_8822B) -#define BIT_GET_EXQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822B) & BIT_MASK_EXQ_LOW_TH_V1_8822B) - - +#define BIT_EXQ_LOW_TH_V1_8822B(x) \ + (((x) & BIT_MASK_EXQ_LOW_TH_V1_8822B) << BIT_SHIFT_EXQ_LOW_TH_V1_8822B) +#define BITS_EXQ_LOW_TH_V1_8822B \ + (BIT_MASK_EXQ_LOW_TH_V1_8822B << BIT_SHIFT_EXQ_LOW_TH_V1_8822B) +#define BIT_CLEAR_EXQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8822B)) +#define BIT_GET_EXQ_LOW_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822B) & BIT_MASK_EXQ_LOW_TH_V1_8822B) +#define BIT_SET_EXQ_LOW_TH_V1_8822B(x, v) \ + (BIT_CLEAR_EXQ_LOW_TH_V1_8822B(x) | BIT_EXQ_LOW_TH_V1_8822B(v)) /* 2 REG_RQPN_CTRL_1_8822B */ #define BIT_SHIFT_TXPKTNUM_H_8822B 16 #define BIT_MASK_TXPKTNUM_H_8822B 0xffff -#define BIT_TXPKTNUM_H_8822B(x) (((x) & BIT_MASK_TXPKTNUM_H_8822B) << BIT_SHIFT_TXPKTNUM_H_8822B) -#define BIT_GET_TXPKTNUM_H_8822B(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8822B) & BIT_MASK_TXPKTNUM_H_8822B) - - +#define BIT_TXPKTNUM_H_8822B(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_8822B) << BIT_SHIFT_TXPKTNUM_H_8822B) +#define BITS_TXPKTNUM_H_8822B \ + (BIT_MASK_TXPKTNUM_H_8822B << BIT_SHIFT_TXPKTNUM_H_8822B) +#define BIT_CLEAR_TXPKTNUM_H_8822B(x) ((x) & (~BITS_TXPKTNUM_H_8822B)) +#define BIT_GET_TXPKTNUM_H_8822B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_8822B) & BIT_MASK_TXPKTNUM_H_8822B) +#define BIT_SET_TXPKTNUM_H_8822B(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_8822B(x) | BIT_TXPKTNUM_H_8822B(v)) #define BIT_SHIFT_TXPKTNUM_V2_8822B 0 #define BIT_MASK_TXPKTNUM_V2_8822B 0xffff -#define BIT_TXPKTNUM_V2_8822B(x) (((x) & BIT_MASK_TXPKTNUM_V2_8822B) << BIT_SHIFT_TXPKTNUM_V2_8822B) -#define BIT_GET_TXPKTNUM_V2_8822B(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2_8822B) & BIT_MASK_TXPKTNUM_V2_8822B) - - +#define BIT_TXPKTNUM_V2_8822B(x) \ + (((x) & BIT_MASK_TXPKTNUM_V2_8822B) << BIT_SHIFT_TXPKTNUM_V2_8822B) +#define BITS_TXPKTNUM_V2_8822B \ + (BIT_MASK_TXPKTNUM_V2_8822B << BIT_SHIFT_TXPKTNUM_V2_8822B) +#define BIT_CLEAR_TXPKTNUM_V2_8822B(x) ((x) & (~BITS_TXPKTNUM_V2_8822B)) +#define BIT_GET_TXPKTNUM_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_V2_8822B) & BIT_MASK_TXPKTNUM_V2_8822B) +#define BIT_SET_TXPKTNUM_V2_8822B(x, v) \ + (BIT_CLEAR_TXPKTNUM_V2_8822B(x) | BIT_TXPKTNUM_V2_8822B(v)) /* 2 REG_RQPN_CTRL_2_8822B */ #define BIT_LD_RQPN_8822B BIT(31) @@ -3605,117 +5212,192 @@ #define BIT_SHIFT_HPQ_AVAL_PG_V1_8822B 16 #define BIT_MASK_HPQ_AVAL_PG_V1_8822B 0xfff -#define BIT_HPQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822B) << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) -#define BIT_GET_HPQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) & BIT_MASK_HPQ_AVAL_PG_V1_8822B) - - +#define BIT_HPQ_AVAL_PG_V1_8822B(x) \ + (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822B) \ + << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) +#define BITS_HPQ_AVAL_PG_V1_8822B \ + (BIT_MASK_HPQ_AVAL_PG_V1_8822B << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) +#define BIT_CLEAR_HPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8822B)) +#define BIT_GET_HPQ_AVAL_PG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) & \ + BIT_MASK_HPQ_AVAL_PG_V1_8822B) +#define BIT_SET_HPQ_AVAL_PG_V1_8822B(x, v) \ + (BIT_CLEAR_HPQ_AVAL_PG_V1_8822B(x) | BIT_HPQ_AVAL_PG_V1_8822B(v)) #define BIT_SHIFT_HPQ_V1_8822B 0 #define BIT_MASK_HPQ_V1_8822B 0xfff -#define BIT_HPQ_V1_8822B(x) (((x) & BIT_MASK_HPQ_V1_8822B) << BIT_SHIFT_HPQ_V1_8822B) -#define BIT_GET_HPQ_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_V1_8822B) & BIT_MASK_HPQ_V1_8822B) - - +#define BIT_HPQ_V1_8822B(x) \ + (((x) & BIT_MASK_HPQ_V1_8822B) << BIT_SHIFT_HPQ_V1_8822B) +#define BITS_HPQ_V1_8822B (BIT_MASK_HPQ_V1_8822B << BIT_SHIFT_HPQ_V1_8822B) +#define BIT_CLEAR_HPQ_V1_8822B(x) ((x) & (~BITS_HPQ_V1_8822B)) +#define BIT_GET_HPQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HPQ_V1_8822B) & BIT_MASK_HPQ_V1_8822B) +#define BIT_SET_HPQ_V1_8822B(x, v) \ + (BIT_CLEAR_HPQ_V1_8822B(x) | BIT_HPQ_V1_8822B(v)) /* 2 REG_FIFOPAGE_INFO_2_8822B */ #define BIT_SHIFT_LPQ_AVAL_PG_V1_8822B 16 #define BIT_MASK_LPQ_AVAL_PG_V1_8822B 0xfff -#define BIT_LPQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822B) << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) -#define BIT_GET_LPQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) & BIT_MASK_LPQ_AVAL_PG_V1_8822B) - - +#define BIT_LPQ_AVAL_PG_V1_8822B(x) \ + (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822B) \ + << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) +#define BITS_LPQ_AVAL_PG_V1_8822B \ + (BIT_MASK_LPQ_AVAL_PG_V1_8822B << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) +#define BIT_CLEAR_LPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8822B)) +#define BIT_GET_LPQ_AVAL_PG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) & \ + BIT_MASK_LPQ_AVAL_PG_V1_8822B) +#define BIT_SET_LPQ_AVAL_PG_V1_8822B(x, v) \ + (BIT_CLEAR_LPQ_AVAL_PG_V1_8822B(x) | BIT_LPQ_AVAL_PG_V1_8822B(v)) #define BIT_SHIFT_LPQ_V1_8822B 0 #define BIT_MASK_LPQ_V1_8822B 0xfff -#define BIT_LPQ_V1_8822B(x) (((x) & BIT_MASK_LPQ_V1_8822B) << BIT_SHIFT_LPQ_V1_8822B) -#define BIT_GET_LPQ_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_V1_8822B) & BIT_MASK_LPQ_V1_8822B) - - +#define BIT_LPQ_V1_8822B(x) \ + (((x) & BIT_MASK_LPQ_V1_8822B) << BIT_SHIFT_LPQ_V1_8822B) +#define BITS_LPQ_V1_8822B (BIT_MASK_LPQ_V1_8822B << BIT_SHIFT_LPQ_V1_8822B) +#define BIT_CLEAR_LPQ_V1_8822B(x) ((x) & (~BITS_LPQ_V1_8822B)) +#define BIT_GET_LPQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LPQ_V1_8822B) & BIT_MASK_LPQ_V1_8822B) +#define BIT_SET_LPQ_V1_8822B(x, v) \ + (BIT_CLEAR_LPQ_V1_8822B(x) | BIT_LPQ_V1_8822B(v)) /* 2 REG_FIFOPAGE_INFO_3_8822B */ #define BIT_SHIFT_NPQ_AVAL_PG_V1_8822B 16 #define BIT_MASK_NPQ_AVAL_PG_V1_8822B 0xfff -#define BIT_NPQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822B) << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) -#define BIT_GET_NPQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) & BIT_MASK_NPQ_AVAL_PG_V1_8822B) - - +#define BIT_NPQ_AVAL_PG_V1_8822B(x) \ + (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822B) \ + << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) +#define BITS_NPQ_AVAL_PG_V1_8822B \ + (BIT_MASK_NPQ_AVAL_PG_V1_8822B << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) +#define BIT_CLEAR_NPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8822B)) +#define BIT_GET_NPQ_AVAL_PG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) & \ + BIT_MASK_NPQ_AVAL_PG_V1_8822B) +#define BIT_SET_NPQ_AVAL_PG_V1_8822B(x, v) \ + (BIT_CLEAR_NPQ_AVAL_PG_V1_8822B(x) | BIT_NPQ_AVAL_PG_V1_8822B(v)) #define BIT_SHIFT_NPQ_V1_8822B 0 #define BIT_MASK_NPQ_V1_8822B 0xfff -#define BIT_NPQ_V1_8822B(x) (((x) & BIT_MASK_NPQ_V1_8822B) << BIT_SHIFT_NPQ_V1_8822B) -#define BIT_GET_NPQ_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_V1_8822B) & BIT_MASK_NPQ_V1_8822B) - - +#define BIT_NPQ_V1_8822B(x) \ + (((x) & BIT_MASK_NPQ_V1_8822B) << BIT_SHIFT_NPQ_V1_8822B) +#define BITS_NPQ_V1_8822B (BIT_MASK_NPQ_V1_8822B << BIT_SHIFT_NPQ_V1_8822B) +#define BIT_CLEAR_NPQ_V1_8822B(x) ((x) & (~BITS_NPQ_V1_8822B)) +#define BIT_GET_NPQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_NPQ_V1_8822B) & BIT_MASK_NPQ_V1_8822B) +#define BIT_SET_NPQ_V1_8822B(x, v) \ + (BIT_CLEAR_NPQ_V1_8822B(x) | BIT_NPQ_V1_8822B(v)) /* 2 REG_FIFOPAGE_INFO_4_8822B */ #define BIT_SHIFT_EXQ_AVAL_PG_V1_8822B 16 #define BIT_MASK_EXQ_AVAL_PG_V1_8822B 0xfff -#define BIT_EXQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822B) << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) -#define BIT_GET_EXQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) & BIT_MASK_EXQ_AVAL_PG_V1_8822B) - - +#define BIT_EXQ_AVAL_PG_V1_8822B(x) \ + (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822B) \ + << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) +#define BITS_EXQ_AVAL_PG_V1_8822B \ + (BIT_MASK_EXQ_AVAL_PG_V1_8822B << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) +#define BIT_CLEAR_EXQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8822B)) +#define BIT_GET_EXQ_AVAL_PG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) & \ + BIT_MASK_EXQ_AVAL_PG_V1_8822B) +#define BIT_SET_EXQ_AVAL_PG_V1_8822B(x, v) \ + (BIT_CLEAR_EXQ_AVAL_PG_V1_8822B(x) | BIT_EXQ_AVAL_PG_V1_8822B(v)) #define BIT_SHIFT_EXQ_V1_8822B 0 #define BIT_MASK_EXQ_V1_8822B 0xfff -#define BIT_EXQ_V1_8822B(x) (((x) & BIT_MASK_EXQ_V1_8822B) << BIT_SHIFT_EXQ_V1_8822B) -#define BIT_GET_EXQ_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_V1_8822B) & BIT_MASK_EXQ_V1_8822B) - - +#define BIT_EXQ_V1_8822B(x) \ + (((x) & BIT_MASK_EXQ_V1_8822B) << BIT_SHIFT_EXQ_V1_8822B) +#define BITS_EXQ_V1_8822B (BIT_MASK_EXQ_V1_8822B << BIT_SHIFT_EXQ_V1_8822B) +#define BIT_CLEAR_EXQ_V1_8822B(x) ((x) & (~BITS_EXQ_V1_8822B)) +#define BIT_GET_EXQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EXQ_V1_8822B) & BIT_MASK_EXQ_V1_8822B) +#define BIT_SET_EXQ_V1_8822B(x, v) \ + (BIT_CLEAR_EXQ_V1_8822B(x) | BIT_EXQ_V1_8822B(v)) /* 2 REG_FIFOPAGE_INFO_5_8822B */ #define BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B 16 #define BIT_MASK_PUBQ_AVAL_PG_V1_8822B 0xfff -#define BIT_PUBQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) -#define BIT_GET_PUBQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B) - - +#define BIT_PUBQ_AVAL_PG_V1_8822B(x) \ + (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B) \ + << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) +#define BITS_PUBQ_AVAL_PG_V1_8822B \ + (BIT_MASK_PUBQ_AVAL_PG_V1_8822B << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) +#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8822B)) +#define BIT_GET_PUBQ_AVAL_PG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) & \ + BIT_MASK_PUBQ_AVAL_PG_V1_8822B) +#define BIT_SET_PUBQ_AVAL_PG_V1_8822B(x, v) \ + (BIT_CLEAR_PUBQ_AVAL_PG_V1_8822B(x) | BIT_PUBQ_AVAL_PG_V1_8822B(v)) #define BIT_SHIFT_PUBQ_V1_8822B 0 #define BIT_MASK_PUBQ_V1_8822B 0xfff -#define BIT_PUBQ_V1_8822B(x) (((x) & BIT_MASK_PUBQ_V1_8822B) << BIT_SHIFT_PUBQ_V1_8822B) -#define BIT_GET_PUBQ_V1_8822B(x) (((x) >> BIT_SHIFT_PUBQ_V1_8822B) & BIT_MASK_PUBQ_V1_8822B) - - +#define BIT_PUBQ_V1_8822B(x) \ + (((x) & BIT_MASK_PUBQ_V1_8822B) << BIT_SHIFT_PUBQ_V1_8822B) +#define BITS_PUBQ_V1_8822B (BIT_MASK_PUBQ_V1_8822B << BIT_SHIFT_PUBQ_V1_8822B) +#define BIT_CLEAR_PUBQ_V1_8822B(x) ((x) & (~BITS_PUBQ_V1_8822B)) +#define BIT_GET_PUBQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PUBQ_V1_8822B) & BIT_MASK_PUBQ_V1_8822B) +#define BIT_SET_PUBQ_V1_8822B(x, v) \ + (BIT_CLEAR_PUBQ_V1_8822B(x) | BIT_PUBQ_V1_8822B(v)) /* 2 REG_H2C_HEAD_8822B */ #define BIT_SHIFT_H2C_HEAD_8822B 0 #define BIT_MASK_H2C_HEAD_8822B 0x3ffff -#define BIT_H2C_HEAD_8822B(x) (((x) & BIT_MASK_H2C_HEAD_8822B) << BIT_SHIFT_H2C_HEAD_8822B) -#define BIT_GET_H2C_HEAD_8822B(x) (((x) >> BIT_SHIFT_H2C_HEAD_8822B) & BIT_MASK_H2C_HEAD_8822B) - - +#define BIT_H2C_HEAD_8822B(x) \ + (((x) & BIT_MASK_H2C_HEAD_8822B) << BIT_SHIFT_H2C_HEAD_8822B) +#define BITS_H2C_HEAD_8822B \ + (BIT_MASK_H2C_HEAD_8822B << BIT_SHIFT_H2C_HEAD_8822B) +#define BIT_CLEAR_H2C_HEAD_8822B(x) ((x) & (~BITS_H2C_HEAD_8822B)) +#define BIT_GET_H2C_HEAD_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_8822B) & BIT_MASK_H2C_HEAD_8822B) +#define BIT_SET_H2C_HEAD_8822B(x, v) \ + (BIT_CLEAR_H2C_HEAD_8822B(x) | BIT_H2C_HEAD_8822B(v)) /* 2 REG_H2C_TAIL_8822B */ #define BIT_SHIFT_H2C_TAIL_8822B 0 #define BIT_MASK_H2C_TAIL_8822B 0x3ffff -#define BIT_H2C_TAIL_8822B(x) (((x) & BIT_MASK_H2C_TAIL_8822B) << BIT_SHIFT_H2C_TAIL_8822B) -#define BIT_GET_H2C_TAIL_8822B(x) (((x) >> BIT_SHIFT_H2C_TAIL_8822B) & BIT_MASK_H2C_TAIL_8822B) - - +#define BIT_H2C_TAIL_8822B(x) \ + (((x) & BIT_MASK_H2C_TAIL_8822B) << BIT_SHIFT_H2C_TAIL_8822B) +#define BITS_H2C_TAIL_8822B \ + (BIT_MASK_H2C_TAIL_8822B << BIT_SHIFT_H2C_TAIL_8822B) +#define BIT_CLEAR_H2C_TAIL_8822B(x) ((x) & (~BITS_H2C_TAIL_8822B)) +#define BIT_GET_H2C_TAIL_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_8822B) & BIT_MASK_H2C_TAIL_8822B) +#define BIT_SET_H2C_TAIL_8822B(x, v) \ + (BIT_CLEAR_H2C_TAIL_8822B(x) | BIT_H2C_TAIL_8822B(v)) /* 2 REG_H2C_READ_ADDR_8822B */ #define BIT_SHIFT_H2C_READ_ADDR_8822B 0 #define BIT_MASK_H2C_READ_ADDR_8822B 0x3ffff -#define BIT_H2C_READ_ADDR_8822B(x) (((x) & BIT_MASK_H2C_READ_ADDR_8822B) << BIT_SHIFT_H2C_READ_ADDR_8822B) -#define BIT_GET_H2C_READ_ADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8822B) & BIT_MASK_H2C_READ_ADDR_8822B) - - +#define BIT_H2C_READ_ADDR_8822B(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_8822B) << BIT_SHIFT_H2C_READ_ADDR_8822B) +#define BITS_H2C_READ_ADDR_8822B \ + (BIT_MASK_H2C_READ_ADDR_8822B << BIT_SHIFT_H2C_READ_ADDR_8822B) +#define BIT_CLEAR_H2C_READ_ADDR_8822B(x) ((x) & (~BITS_H2C_READ_ADDR_8822B)) +#define BIT_GET_H2C_READ_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_8822B) & BIT_MASK_H2C_READ_ADDR_8822B) +#define BIT_SET_H2C_READ_ADDR_8822B(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_8822B(x) | BIT_H2C_READ_ADDR_8822B(v)) /* 2 REG_H2C_WR_ADDR_8822B */ #define BIT_SHIFT_H2C_WR_ADDR_8822B 0 #define BIT_MASK_H2C_WR_ADDR_8822B 0x3ffff -#define BIT_H2C_WR_ADDR_8822B(x) (((x) & BIT_MASK_H2C_WR_ADDR_8822B) << BIT_SHIFT_H2C_WR_ADDR_8822B) -#define BIT_GET_H2C_WR_ADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8822B) & BIT_MASK_H2C_WR_ADDR_8822B) - - +#define BIT_H2C_WR_ADDR_8822B(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_8822B) << BIT_SHIFT_H2C_WR_ADDR_8822B) +#define BITS_H2C_WR_ADDR_8822B \ + (BIT_MASK_H2C_WR_ADDR_8822B << BIT_SHIFT_H2C_WR_ADDR_8822B) +#define BIT_CLEAR_H2C_WR_ADDR_8822B(x) ((x) & (~BITS_H2C_WR_ADDR_8822B)) +#define BIT_GET_H2C_WR_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_8822B) & BIT_MASK_H2C_WR_ADDR_8822B) +#define BIT_SET_H2C_WR_ADDR_8822B(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_8822B(x) | BIT_H2C_WR_ADDR_8822B(v)) /* 2 REG_H2C_INFO_8822B */ #define BIT_H2C_SPACE_VLD_8822B BIT(3) @@ -3723,55 +5405,90 @@ #define BIT_SHIFT_H2C_LEN_SEL_8822B 0 #define BIT_MASK_H2C_LEN_SEL_8822B 0x3 -#define BIT_H2C_LEN_SEL_8822B(x) (((x) & BIT_MASK_H2C_LEN_SEL_8822B) << BIT_SHIFT_H2C_LEN_SEL_8822B) -#define BIT_GET_H2C_LEN_SEL_8822B(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8822B) & BIT_MASK_H2C_LEN_SEL_8822B) - - +#define BIT_H2C_LEN_SEL_8822B(x) \ + (((x) & BIT_MASK_H2C_LEN_SEL_8822B) << BIT_SHIFT_H2C_LEN_SEL_8822B) +#define BITS_H2C_LEN_SEL_8822B \ + (BIT_MASK_H2C_LEN_SEL_8822B << BIT_SHIFT_H2C_LEN_SEL_8822B) +#define BIT_CLEAR_H2C_LEN_SEL_8822B(x) ((x) & (~BITS_H2C_LEN_SEL_8822B)) +#define BIT_GET_H2C_LEN_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_LEN_SEL_8822B) & BIT_MASK_H2C_LEN_SEL_8822B) +#define BIT_SET_H2C_LEN_SEL_8822B(x, v) \ + (BIT_CLEAR_H2C_LEN_SEL_8822B(x) | BIT_H2C_LEN_SEL_8822B(v)) /* 2 REG_RXDMA_AGG_PG_TH_8822B */ - -#define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B 24 -#define BIT_MASK_RXDMA_AGG_OLD_MOD_8822B 0xff -#define BIT_RXDMA_AGG_OLD_MOD_8822B(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD_8822B) << BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B) -#define BIT_GET_RXDMA_AGG_OLD_MOD_8822B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B) & BIT_MASK_RXDMA_AGG_OLD_MOD_8822B) - - +#define BIT_USB_RXDMA_AGG_EN_8822B BIT(31) +#define BIT_EN_PRE_CALC_8822B BIT(29) +#define BIT_RXAGG_SW_EN_8822B BIT(28) +#define BIT_RXAGG_SW_TRIG_8822B BIT(27) #define BIT_SHIFT_PKT_NUM_WOL_8822B 16 #define BIT_MASK_PKT_NUM_WOL_8822B 0xff -#define BIT_PKT_NUM_WOL_8822B(x) (((x) & BIT_MASK_PKT_NUM_WOL_8822B) << BIT_SHIFT_PKT_NUM_WOL_8822B) -#define BIT_GET_PKT_NUM_WOL_8822B(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8822B) & BIT_MASK_PKT_NUM_WOL_8822B) - - - -#define BIT_SHIFT_DMA_AGG_TO_8822B 8 -#define BIT_MASK_DMA_AGG_TO_8822B 0xf -#define BIT_DMA_AGG_TO_8822B(x) (((x) & BIT_MASK_DMA_AGG_TO_8822B) << BIT_SHIFT_DMA_AGG_TO_8822B) -#define BIT_GET_DMA_AGG_TO_8822B(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_8822B) & BIT_MASK_DMA_AGG_TO_8822B) - - - -#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B 0 -#define BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B 0xf -#define BIT_RXDMA_AGG_PG_TH_V1_8822B(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B) -#define BIT_GET_RXDMA_AGG_PG_TH_V1_8822B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B) - - +#define BIT_PKT_NUM_WOL_8822B(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL_8822B) << BIT_SHIFT_PKT_NUM_WOL_8822B) +#define BITS_PKT_NUM_WOL_8822B \ + (BIT_MASK_PKT_NUM_WOL_8822B << BIT_SHIFT_PKT_NUM_WOL_8822B) +#define BIT_CLEAR_PKT_NUM_WOL_8822B(x) ((x) & (~BITS_PKT_NUM_WOL_8822B)) +#define BIT_GET_PKT_NUM_WOL_8822B(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL_8822B) & BIT_MASK_PKT_NUM_WOL_8822B) +#define BIT_SET_PKT_NUM_WOL_8822B(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL_8822B(x) | BIT_PKT_NUM_WOL_8822B(v)) + +#define BIT_SHIFT_DMA_AGG_TO_V1_8822B 8 +#define BIT_MASK_DMA_AGG_TO_V1_8822B 0xff +#define BIT_DMA_AGG_TO_V1_8822B(x) \ + (((x) & BIT_MASK_DMA_AGG_TO_V1_8822B) << BIT_SHIFT_DMA_AGG_TO_V1_8822B) +#define BITS_DMA_AGG_TO_V1_8822B \ + (BIT_MASK_DMA_AGG_TO_V1_8822B << BIT_SHIFT_DMA_AGG_TO_V1_8822B) +#define BIT_CLEAR_DMA_AGG_TO_V1_8822B(x) ((x) & (~BITS_DMA_AGG_TO_V1_8822B)) +#define BIT_GET_DMA_AGG_TO_V1_8822B(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8822B) & BIT_MASK_DMA_AGG_TO_V1_8822B) +#define BIT_SET_DMA_AGG_TO_V1_8822B(x, v) \ + (BIT_CLEAR_DMA_AGG_TO_V1_8822B(x) | BIT_DMA_AGG_TO_V1_8822B(v)) + +#define BIT_SHIFT_RXDMA_AGG_PG_TH_8822B 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_8822B 0xff +#define BIT_RXDMA_AGG_PG_TH_8822B(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8822B) \ + << BIT_SHIFT_RXDMA_AGG_PG_TH_8822B) +#define BITS_RXDMA_AGG_PG_TH_8822B \ + (BIT_MASK_RXDMA_AGG_PG_TH_8822B << BIT_SHIFT_RXDMA_AGG_PG_TH_8822B) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_8822B(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8822B)) +#define BIT_GET_RXDMA_AGG_PG_TH_8822B(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8822B) & \ + BIT_MASK_RXDMA_AGG_PG_TH_8822B) +#define BIT_SET_RXDMA_AGG_PG_TH_8822B(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_8822B(x) | BIT_RXDMA_AGG_PG_TH_8822B(v)) /* 2 REG_RXPKT_NUM_8822B */ #define BIT_SHIFT_RXPKT_NUM_8822B 24 #define BIT_MASK_RXPKT_NUM_8822B 0xff -#define BIT_RXPKT_NUM_8822B(x) (((x) & BIT_MASK_RXPKT_NUM_8822B) << BIT_SHIFT_RXPKT_NUM_8822B) -#define BIT_GET_RXPKT_NUM_8822B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8822B) & BIT_MASK_RXPKT_NUM_8822B) - - +#define BIT_RXPKT_NUM_8822B(x) \ + (((x) & BIT_MASK_RXPKT_NUM_8822B) << BIT_SHIFT_RXPKT_NUM_8822B) +#define BITS_RXPKT_NUM_8822B \ + (BIT_MASK_RXPKT_NUM_8822B << BIT_SHIFT_RXPKT_NUM_8822B) +#define BIT_CLEAR_RXPKT_NUM_8822B(x) ((x) & (~BITS_RXPKT_NUM_8822B)) +#define BIT_GET_RXPKT_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_8822B) & BIT_MASK_RXPKT_NUM_8822B) +#define BIT_SET_RXPKT_NUM_8822B(x, v) \ + (BIT_CLEAR_RXPKT_NUM_8822B(x) | BIT_RXPKT_NUM_8822B(v)) #define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B 20 #define BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B 0xf -#define BIT_FW_UPD_RDPTR19_TO_16_8822B(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) -#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) - +#define BIT_FW_UPD_RDPTR19_TO_16_8822B(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) +#define BITS_FW_UPD_RDPTR19_TO_16_8822B \ + (BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822B(x) \ + ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8822B)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822B(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) & \ + BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) +#define BIT_SET_FW_UPD_RDPTR19_TO_16_8822B(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822B(x) | \ + BIT_FW_UPD_RDPTR19_TO_16_8822B(v)) #define BIT_RXDMA_REQ_8822B BIT(19) #define BIT_RW_RELEASE_EN_8822B BIT(18) @@ -3780,10 +5497,15 @@ #define BIT_SHIFT_FW_UPD_RDPTR_8822B 0 #define BIT_MASK_FW_UPD_RDPTR_8822B 0xffff -#define BIT_FW_UPD_RDPTR_8822B(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8822B) << BIT_SHIFT_FW_UPD_RDPTR_8822B) -#define BIT_GET_FW_UPD_RDPTR_8822B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822B) & BIT_MASK_FW_UPD_RDPTR_8822B) - - +#define BIT_FW_UPD_RDPTR_8822B(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR_8822B) << BIT_SHIFT_FW_UPD_RDPTR_8822B) +#define BITS_FW_UPD_RDPTR_8822B \ + (BIT_MASK_FW_UPD_RDPTR_8822B << BIT_SHIFT_FW_UPD_RDPTR_8822B) +#define BIT_CLEAR_FW_UPD_RDPTR_8822B(x) ((x) & (~BITS_FW_UPD_RDPTR_8822B)) +#define BIT_GET_FW_UPD_RDPTR_8822B(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822B) & BIT_MASK_FW_UPD_RDPTR_8822B) +#define BIT_SET_FW_UPD_RDPTR_8822B(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR_8822B(x) | BIT_FW_UPD_RDPTR_8822B(v)) /* 2 REG_RXDMA_STATUS_8822B */ #define BIT_C2H_PKT_OVF_8822B BIT(7) @@ -3798,27 +5520,43 @@ #define BIT_SHIFT_RDE_DEBUG_8822B 0 #define BIT_MASK_RDE_DEBUG_8822B 0xffffffffL -#define BIT_RDE_DEBUG_8822B(x) (((x) & BIT_MASK_RDE_DEBUG_8822B) << BIT_SHIFT_RDE_DEBUG_8822B) -#define BIT_GET_RDE_DEBUG_8822B(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8822B) & BIT_MASK_RDE_DEBUG_8822B) - - +#define BIT_RDE_DEBUG_8822B(x) \ + (((x) & BIT_MASK_RDE_DEBUG_8822B) << BIT_SHIFT_RDE_DEBUG_8822B) +#define BITS_RDE_DEBUG_8822B \ + (BIT_MASK_RDE_DEBUG_8822B << BIT_SHIFT_RDE_DEBUG_8822B) +#define BIT_CLEAR_RDE_DEBUG_8822B(x) ((x) & (~BITS_RDE_DEBUG_8822B)) +#define BIT_GET_RDE_DEBUG_8822B(x) \ + (((x) >> BIT_SHIFT_RDE_DEBUG_8822B) & BIT_MASK_RDE_DEBUG_8822B) +#define BIT_SET_RDE_DEBUG_8822B(x, v) \ + (BIT_CLEAR_RDE_DEBUG_8822B(x) | BIT_RDE_DEBUG_8822B(v)) /* 2 REG_RXDMA_MODE_8822B */ #define BIT_SHIFT_PKTNUM_TH_V2_8822B 24 #define BIT_MASK_PKTNUM_TH_V2_8822B 0x1f -#define BIT_PKTNUM_TH_V2_8822B(x) (((x) & BIT_MASK_PKTNUM_TH_V2_8822B) << BIT_SHIFT_PKTNUM_TH_V2_8822B) -#define BIT_GET_PKTNUM_TH_V2_8822B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822B) & BIT_MASK_PKTNUM_TH_V2_8822B) - +#define BIT_PKTNUM_TH_V2_8822B(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V2_8822B) << BIT_SHIFT_PKTNUM_TH_V2_8822B) +#define BITS_PKTNUM_TH_V2_8822B \ + (BIT_MASK_PKTNUM_TH_V2_8822B << BIT_SHIFT_PKTNUM_TH_V2_8822B) +#define BIT_CLEAR_PKTNUM_TH_V2_8822B(x) ((x) & (~BITS_PKTNUM_TH_V2_8822B)) +#define BIT_GET_PKTNUM_TH_V2_8822B(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822B) & BIT_MASK_PKTNUM_TH_V2_8822B) +#define BIT_SET_PKTNUM_TH_V2_8822B(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V2_8822B(x) | BIT_PKTNUM_TH_V2_8822B(v)) #define BIT_TXBA_BREAK_USBAGG_8822B BIT(23) #define BIT_SHIFT_PKTLEN_PARA_8822B 16 #define BIT_MASK_PKTLEN_PARA_8822B 0x7 -#define BIT_PKTLEN_PARA_8822B(x) (((x) & BIT_MASK_PKTLEN_PARA_8822B) << BIT_SHIFT_PKTLEN_PARA_8822B) -#define BIT_GET_PKTLEN_PARA_8822B(x) (((x) >> BIT_SHIFT_PKTLEN_PARA_8822B) & BIT_MASK_PKTLEN_PARA_8822B) - - +#define BIT_PKTLEN_PARA_8822B(x) \ + (((x) & BIT_MASK_PKTLEN_PARA_8822B) << BIT_SHIFT_PKTLEN_PARA_8822B) +#define BITS_PKTLEN_PARA_8822B \ + (BIT_MASK_PKTLEN_PARA_8822B << BIT_SHIFT_PKTLEN_PARA_8822B) +#define BIT_CLEAR_PKTLEN_PARA_8822B(x) ((x) & (~BITS_PKTLEN_PARA_8822B)) +#define BIT_GET_PKTLEN_PARA_8822B(x) \ + (((x) >> BIT_SHIFT_PKTLEN_PARA_8822B) & BIT_MASK_PKTLEN_PARA_8822B) +#define BIT_SET_PKTLEN_PARA_8822B(x, v) \ + (BIT_CLEAR_PKTLEN_PARA_8822B(x) | BIT_PKTLEN_PARA_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -3828,16 +5566,27 @@ #define BIT_SHIFT_BURST_SIZE_8822B 4 #define BIT_MASK_BURST_SIZE_8822B 0x3 -#define BIT_BURST_SIZE_8822B(x) (((x) & BIT_MASK_BURST_SIZE_8822B) << BIT_SHIFT_BURST_SIZE_8822B) -#define BIT_GET_BURST_SIZE_8822B(x) (((x) >> BIT_SHIFT_BURST_SIZE_8822B) & BIT_MASK_BURST_SIZE_8822B) - - +#define BIT_BURST_SIZE_8822B(x) \ + (((x) & BIT_MASK_BURST_SIZE_8822B) << BIT_SHIFT_BURST_SIZE_8822B) +#define BITS_BURST_SIZE_8822B \ + (BIT_MASK_BURST_SIZE_8822B << BIT_SHIFT_BURST_SIZE_8822B) +#define BIT_CLEAR_BURST_SIZE_8822B(x) ((x) & (~BITS_BURST_SIZE_8822B)) +#define BIT_GET_BURST_SIZE_8822B(x) \ + (((x) >> BIT_SHIFT_BURST_SIZE_8822B) & BIT_MASK_BURST_SIZE_8822B) +#define BIT_SET_BURST_SIZE_8822B(x, v) \ + (BIT_CLEAR_BURST_SIZE_8822B(x) | BIT_BURST_SIZE_8822B(v)) #define BIT_SHIFT_BURST_CNT_8822B 2 #define BIT_MASK_BURST_CNT_8822B 0x3 -#define BIT_BURST_CNT_8822B(x) (((x) & BIT_MASK_BURST_CNT_8822B) << BIT_SHIFT_BURST_CNT_8822B) -#define BIT_GET_BURST_CNT_8822B(x) (((x) >> BIT_SHIFT_BURST_CNT_8822B) & BIT_MASK_BURST_CNT_8822B) - +#define BIT_BURST_CNT_8822B(x) \ + (((x) & BIT_MASK_BURST_CNT_8822B) << BIT_SHIFT_BURST_CNT_8822B) +#define BITS_BURST_CNT_8822B \ + (BIT_MASK_BURST_CNT_8822B << BIT_SHIFT_BURST_CNT_8822B) +#define BIT_CLEAR_BURST_CNT_8822B(x) ((x) & (~BITS_BURST_CNT_8822B)) +#define BIT_GET_BURST_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_BURST_CNT_8822B) & BIT_MASK_BURST_CNT_8822B) +#define BIT_SET_BURST_CNT_8822B(x, v) \ + (BIT_CLEAR_BURST_CNT_8822B(x) | BIT_BURST_CNT_8822B(v)) #define BIT_DMA_MODE_8822B BIT(1) @@ -3845,60 +5594,111 @@ #define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B 24 #define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B 0xf -#define BIT_R_C2H_STR_ADDR_16_TO_19_8822B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) -#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) - +#define BIT_R_C2H_STR_ADDR_16_TO_19_8822B(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) +#define BITS_R_C2H_STR_ADDR_16_TO_19_8822B \ + (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822B(x) \ + ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8822B)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822B(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) & \ + BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8822B(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822B(x) | \ + BIT_R_C2H_STR_ADDR_16_TO_19_8822B(v)) #define BIT_R_C2H_PKT_REQ_8822B BIT(16) #define BIT_SHIFT_R_C2H_STR_ADDR_8822B 0 #define BIT_MASK_R_C2H_STR_ADDR_8822B 0xffff -#define BIT_R_C2H_STR_ADDR_8822B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8822B) << BIT_SHIFT_R_C2H_STR_ADDR_8822B) -#define BIT_GET_R_C2H_STR_ADDR_8822B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822B) & BIT_MASK_R_C2H_STR_ADDR_8822B) - - +#define BIT_R_C2H_STR_ADDR_8822B(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_8822B) \ + << BIT_SHIFT_R_C2H_STR_ADDR_8822B) +#define BITS_R_C2H_STR_ADDR_8822B \ + (BIT_MASK_R_C2H_STR_ADDR_8822B << BIT_SHIFT_R_C2H_STR_ADDR_8822B) +#define BIT_CLEAR_R_C2H_STR_ADDR_8822B(x) ((x) & (~BITS_R_C2H_STR_ADDR_8822B)) +#define BIT_GET_R_C2H_STR_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822B) & \ + BIT_MASK_R_C2H_STR_ADDR_8822B) +#define BIT_SET_R_C2H_STR_ADDR_8822B(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_8822B(x) | BIT_R_C2H_STR_ADDR_8822B(v)) /* 2 REG_FWFF_C2H_8822B */ #define BIT_SHIFT_C2H_DMA_ADDR_8822B 0 #define BIT_MASK_C2H_DMA_ADDR_8822B 0x3ffff -#define BIT_C2H_DMA_ADDR_8822B(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8822B) << BIT_SHIFT_C2H_DMA_ADDR_8822B) -#define BIT_GET_C2H_DMA_ADDR_8822B(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822B) & BIT_MASK_C2H_DMA_ADDR_8822B) - - +#define BIT_C2H_DMA_ADDR_8822B(x) \ + (((x) & BIT_MASK_C2H_DMA_ADDR_8822B) << BIT_SHIFT_C2H_DMA_ADDR_8822B) +#define BITS_C2H_DMA_ADDR_8822B \ + (BIT_MASK_C2H_DMA_ADDR_8822B << BIT_SHIFT_C2H_DMA_ADDR_8822B) +#define BIT_CLEAR_C2H_DMA_ADDR_8822B(x) ((x) & (~BITS_C2H_DMA_ADDR_8822B)) +#define BIT_GET_C2H_DMA_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822B) & BIT_MASK_C2H_DMA_ADDR_8822B) +#define BIT_SET_C2H_DMA_ADDR_8822B(x, v) \ + (BIT_CLEAR_C2H_DMA_ADDR_8822B(x) | BIT_C2H_DMA_ADDR_8822B(v)) /* 2 REG_FWFF_CTRL_8822B */ #define BIT_FWFF_DMAPKT_REQ_8822B BIT(31) #define BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B 16 #define BIT_MASK_FWFF_DMA_PKT_NUM_8822B 0xff -#define BIT_FWFF_DMA_PKT_NUM_8822B(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) -#define BIT_GET_FWFF_DMA_PKT_NUM_8822B(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B) - - +#define BIT_FWFF_DMA_PKT_NUM_8822B(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B) \ + << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) +#define BITS_FWFF_DMA_PKT_NUM_8822B \ + (BIT_MASK_FWFF_DMA_PKT_NUM_8822B << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8822B(x) \ + ((x) & (~BITS_FWFF_DMA_PKT_NUM_8822B)) +#define BIT_GET_FWFF_DMA_PKT_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) & \ + BIT_MASK_FWFF_DMA_PKT_NUM_8822B) +#define BIT_SET_FWFF_DMA_PKT_NUM_8822B(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM_8822B(x) | BIT_FWFF_DMA_PKT_NUM_8822B(v)) #define BIT_SHIFT_FWFF_STR_ADDR_8822B 0 #define BIT_MASK_FWFF_STR_ADDR_8822B 0xffff -#define BIT_FWFF_STR_ADDR_8822B(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8822B) << BIT_SHIFT_FWFF_STR_ADDR_8822B) -#define BIT_GET_FWFF_STR_ADDR_8822B(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822B) & BIT_MASK_FWFF_STR_ADDR_8822B) - - +#define BIT_FWFF_STR_ADDR_8822B(x) \ + (((x) & BIT_MASK_FWFF_STR_ADDR_8822B) << BIT_SHIFT_FWFF_STR_ADDR_8822B) +#define BITS_FWFF_STR_ADDR_8822B \ + (BIT_MASK_FWFF_STR_ADDR_8822B << BIT_SHIFT_FWFF_STR_ADDR_8822B) +#define BIT_CLEAR_FWFF_STR_ADDR_8822B(x) ((x) & (~BITS_FWFF_STR_ADDR_8822B)) +#define BIT_GET_FWFF_STR_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822B) & BIT_MASK_FWFF_STR_ADDR_8822B) +#define BIT_SET_FWFF_STR_ADDR_8822B(x, v) \ + (BIT_CLEAR_FWFF_STR_ADDR_8822B(x) | BIT_FWFF_STR_ADDR_8822B(v)) /* 2 REG_FWFF_PKT_INFO_8822B */ #define BIT_SHIFT_FWFF_PKT_QUEUED_8822B 16 #define BIT_MASK_FWFF_PKT_QUEUED_8822B 0xff -#define BIT_FWFF_PKT_QUEUED_8822B(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8822B) << BIT_SHIFT_FWFF_PKT_QUEUED_8822B) -#define BIT_GET_FWFF_PKT_QUEUED_8822B(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822B) & BIT_MASK_FWFF_PKT_QUEUED_8822B) - - +#define BIT_FWFF_PKT_QUEUED_8822B(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED_8822B) \ + << BIT_SHIFT_FWFF_PKT_QUEUED_8822B) +#define BITS_FWFF_PKT_QUEUED_8822B \ + (BIT_MASK_FWFF_PKT_QUEUED_8822B << BIT_SHIFT_FWFF_PKT_QUEUED_8822B) +#define BIT_CLEAR_FWFF_PKT_QUEUED_8822B(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8822B)) +#define BIT_GET_FWFF_PKT_QUEUED_8822B(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822B) & \ + BIT_MASK_FWFF_PKT_QUEUED_8822B) +#define BIT_SET_FWFF_PKT_QUEUED_8822B(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED_8822B(x) | BIT_FWFF_PKT_QUEUED_8822B(v)) #define BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B 0 #define BIT_MASK_FWFF_PKT_STR_ADDR_8822B 0xffff -#define BIT_FWFF_PKT_STR_ADDR_8822B(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) -#define BIT_GET_FWFF_PKT_STR_ADDR_8822B(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B) - - +#define BIT_FWFF_PKT_STR_ADDR_8822B(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B) \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) +#define BITS_FWFF_PKT_STR_ADDR_8822B \ + (BIT_MASK_FWFF_PKT_STR_ADDR_8822B << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8822B(x) \ + ((x) & (~BITS_FWFF_PKT_STR_ADDR_8822B)) +#define BIT_GET_FWFF_PKT_STR_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) & \ + BIT_MASK_FWFF_PKT_STR_ADDR_8822B) +#define BIT_SET_FWFF_PKT_STR_ADDR_8822B(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR_8822B(x) | BIT_FWFF_PKT_STR_ADDR_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -3906,22 +5706,33 @@ #define BIT_SHIFT_DDMACH0_SA_8822B 0 #define BIT_MASK_DDMACH0_SA_8822B 0xffffffffL -#define BIT_DDMACH0_SA_8822B(x) (((x) & BIT_MASK_DDMACH0_SA_8822B) << BIT_SHIFT_DDMACH0_SA_8822B) -#define BIT_GET_DDMACH0_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8822B) & BIT_MASK_DDMACH0_SA_8822B) - - +#define BIT_DDMACH0_SA_8822B(x) \ + (((x) & BIT_MASK_DDMACH0_SA_8822B) << BIT_SHIFT_DDMACH0_SA_8822B) +#define BITS_DDMACH0_SA_8822B \ + (BIT_MASK_DDMACH0_SA_8822B << BIT_SHIFT_DDMACH0_SA_8822B) +#define BIT_CLEAR_DDMACH0_SA_8822B(x) ((x) & (~BITS_DDMACH0_SA_8822B)) +#define BIT_GET_DDMACH0_SA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH0_SA_8822B) & BIT_MASK_DDMACH0_SA_8822B) +#define BIT_SET_DDMACH0_SA_8822B(x, v) \ + (BIT_CLEAR_DDMACH0_SA_8822B(x) | BIT_DDMACH0_SA_8822B(v)) /* 2 REG_DDMA_CH0DA_8822B */ #define BIT_SHIFT_DDMACH0_DA_8822B 0 #define BIT_MASK_DDMACH0_DA_8822B 0xffffffffL -#define BIT_DDMACH0_DA_8822B(x) (((x) & BIT_MASK_DDMACH0_DA_8822B) << BIT_SHIFT_DDMACH0_DA_8822B) -#define BIT_GET_DDMACH0_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8822B) & BIT_MASK_DDMACH0_DA_8822B) - - +#define BIT_DDMACH0_DA_8822B(x) \ + (((x) & BIT_MASK_DDMACH0_DA_8822B) << BIT_SHIFT_DDMACH0_DA_8822B) +#define BITS_DDMACH0_DA_8822B \ + (BIT_MASK_DDMACH0_DA_8822B << BIT_SHIFT_DDMACH0_DA_8822B) +#define BIT_CLEAR_DDMACH0_DA_8822B(x) ((x) & (~BITS_DDMACH0_DA_8822B)) +#define BIT_GET_DDMACH0_DA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DA_8822B) & BIT_MASK_DDMACH0_DA_8822B) +#define BIT_SET_DDMACH0_DA_8822B(x, v) \ + (BIT_CLEAR_DDMACH0_DA_8822B(x) | BIT_DDMACH0_DA_8822B(v)) /* 2 REG_DDMA_CH0CTRL_8822B */ #define BIT_DDMACH0_OWN_8822B BIT(31) +#define BIT_DDMACH0_IDMEM_ERR_8822B BIT(30) #define BIT_DDMACH0_CHKSUM_EN_8822B BIT(29) #define BIT_DDMACH0_DA_W_DISABLE_8822B BIT(28) #define BIT_DDMACH0_CHKSUM_STS_8822B BIT(27) @@ -3931,31 +5742,47 @@ #define BIT_SHIFT_DDMACH0_DLEN_8822B 0 #define BIT_MASK_DDMACH0_DLEN_8822B 0x3ffff -#define BIT_DDMACH0_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH0_DLEN_8822B) << BIT_SHIFT_DDMACH0_DLEN_8822B) -#define BIT_GET_DDMACH0_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8822B) & BIT_MASK_DDMACH0_DLEN_8822B) - - +#define BIT_DDMACH0_DLEN_8822B(x) \ + (((x) & BIT_MASK_DDMACH0_DLEN_8822B) << BIT_SHIFT_DDMACH0_DLEN_8822B) +#define BITS_DDMACH0_DLEN_8822B \ + (BIT_MASK_DDMACH0_DLEN_8822B << BIT_SHIFT_DDMACH0_DLEN_8822B) +#define BIT_CLEAR_DDMACH0_DLEN_8822B(x) ((x) & (~BITS_DDMACH0_DLEN_8822B)) +#define BIT_GET_DDMACH0_DLEN_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DLEN_8822B) & BIT_MASK_DDMACH0_DLEN_8822B) +#define BIT_SET_DDMACH0_DLEN_8822B(x, v) \ + (BIT_CLEAR_DDMACH0_DLEN_8822B(x) | BIT_DDMACH0_DLEN_8822B(v)) /* 2 REG_DDMA_CH1SA_8822B */ #define BIT_SHIFT_DDMACH1_SA_8822B 0 #define BIT_MASK_DDMACH1_SA_8822B 0xffffffffL -#define BIT_DDMACH1_SA_8822B(x) (((x) & BIT_MASK_DDMACH1_SA_8822B) << BIT_SHIFT_DDMACH1_SA_8822B) -#define BIT_GET_DDMACH1_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8822B) & BIT_MASK_DDMACH1_SA_8822B) - - +#define BIT_DDMACH1_SA_8822B(x) \ + (((x) & BIT_MASK_DDMACH1_SA_8822B) << BIT_SHIFT_DDMACH1_SA_8822B) +#define BITS_DDMACH1_SA_8822B \ + (BIT_MASK_DDMACH1_SA_8822B << BIT_SHIFT_DDMACH1_SA_8822B) +#define BIT_CLEAR_DDMACH1_SA_8822B(x) ((x) & (~BITS_DDMACH1_SA_8822B)) +#define BIT_GET_DDMACH1_SA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH1_SA_8822B) & BIT_MASK_DDMACH1_SA_8822B) +#define BIT_SET_DDMACH1_SA_8822B(x, v) \ + (BIT_CLEAR_DDMACH1_SA_8822B(x) | BIT_DDMACH1_SA_8822B(v)) /* 2 REG_DDMA_CH1DA_8822B */ #define BIT_SHIFT_DDMACH1_DA_8822B 0 #define BIT_MASK_DDMACH1_DA_8822B 0xffffffffL -#define BIT_DDMACH1_DA_8822B(x) (((x) & BIT_MASK_DDMACH1_DA_8822B) << BIT_SHIFT_DDMACH1_DA_8822B) -#define BIT_GET_DDMACH1_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8822B) & BIT_MASK_DDMACH1_DA_8822B) - - +#define BIT_DDMACH1_DA_8822B(x) \ + (((x) & BIT_MASK_DDMACH1_DA_8822B) << BIT_SHIFT_DDMACH1_DA_8822B) +#define BITS_DDMACH1_DA_8822B \ + (BIT_MASK_DDMACH1_DA_8822B << BIT_SHIFT_DDMACH1_DA_8822B) +#define BIT_CLEAR_DDMACH1_DA_8822B(x) ((x) & (~BITS_DDMACH1_DA_8822B)) +#define BIT_GET_DDMACH1_DA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DA_8822B) & BIT_MASK_DDMACH1_DA_8822B) +#define BIT_SET_DDMACH1_DA_8822B(x, v) \ + (BIT_CLEAR_DDMACH1_DA_8822B(x) | BIT_DDMACH1_DA_8822B(v)) /* 2 REG_DDMA_CH1CTRL_8822B */ #define BIT_DDMACH1_OWN_8822B BIT(31) +#define BIT_DDMACH1_IDMEM_ERR_8822B BIT(30) #define BIT_DDMACH1_CHKSUM_EN_8822B BIT(29) #define BIT_DDMACH1_DA_W_DISABLE_8822B BIT(28) #define BIT_DDMACH1_CHKSUM_STS_8822B BIT(27) @@ -3965,31 +5792,47 @@ #define BIT_SHIFT_DDMACH1_DLEN_8822B 0 #define BIT_MASK_DDMACH1_DLEN_8822B 0x3ffff -#define BIT_DDMACH1_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH1_DLEN_8822B) << BIT_SHIFT_DDMACH1_DLEN_8822B) -#define BIT_GET_DDMACH1_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8822B) & BIT_MASK_DDMACH1_DLEN_8822B) - - +#define BIT_DDMACH1_DLEN_8822B(x) \ + (((x) & BIT_MASK_DDMACH1_DLEN_8822B) << BIT_SHIFT_DDMACH1_DLEN_8822B) +#define BITS_DDMACH1_DLEN_8822B \ + (BIT_MASK_DDMACH1_DLEN_8822B << BIT_SHIFT_DDMACH1_DLEN_8822B) +#define BIT_CLEAR_DDMACH1_DLEN_8822B(x) ((x) & (~BITS_DDMACH1_DLEN_8822B)) +#define BIT_GET_DDMACH1_DLEN_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DLEN_8822B) & BIT_MASK_DDMACH1_DLEN_8822B) +#define BIT_SET_DDMACH1_DLEN_8822B(x, v) \ + (BIT_CLEAR_DDMACH1_DLEN_8822B(x) | BIT_DDMACH1_DLEN_8822B(v)) /* 2 REG_DDMA_CH2SA_8822B */ #define BIT_SHIFT_DDMACH2_SA_8822B 0 #define BIT_MASK_DDMACH2_SA_8822B 0xffffffffL -#define BIT_DDMACH2_SA_8822B(x) (((x) & BIT_MASK_DDMACH2_SA_8822B) << BIT_SHIFT_DDMACH2_SA_8822B) -#define BIT_GET_DDMACH2_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8822B) & BIT_MASK_DDMACH2_SA_8822B) - - +#define BIT_DDMACH2_SA_8822B(x) \ + (((x) & BIT_MASK_DDMACH2_SA_8822B) << BIT_SHIFT_DDMACH2_SA_8822B) +#define BITS_DDMACH2_SA_8822B \ + (BIT_MASK_DDMACH2_SA_8822B << BIT_SHIFT_DDMACH2_SA_8822B) +#define BIT_CLEAR_DDMACH2_SA_8822B(x) ((x) & (~BITS_DDMACH2_SA_8822B)) +#define BIT_GET_DDMACH2_SA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH2_SA_8822B) & BIT_MASK_DDMACH2_SA_8822B) +#define BIT_SET_DDMACH2_SA_8822B(x, v) \ + (BIT_CLEAR_DDMACH2_SA_8822B(x) | BIT_DDMACH2_SA_8822B(v)) /* 2 REG_DDMA_CH2DA_8822B */ #define BIT_SHIFT_DDMACH2_DA_8822B 0 #define BIT_MASK_DDMACH2_DA_8822B 0xffffffffL -#define BIT_DDMACH2_DA_8822B(x) (((x) & BIT_MASK_DDMACH2_DA_8822B) << BIT_SHIFT_DDMACH2_DA_8822B) -#define BIT_GET_DDMACH2_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8822B) & BIT_MASK_DDMACH2_DA_8822B) - - +#define BIT_DDMACH2_DA_8822B(x) \ + (((x) & BIT_MASK_DDMACH2_DA_8822B) << BIT_SHIFT_DDMACH2_DA_8822B) +#define BITS_DDMACH2_DA_8822B \ + (BIT_MASK_DDMACH2_DA_8822B << BIT_SHIFT_DDMACH2_DA_8822B) +#define BIT_CLEAR_DDMACH2_DA_8822B(x) ((x) & (~BITS_DDMACH2_DA_8822B)) +#define BIT_GET_DDMACH2_DA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DA_8822B) & BIT_MASK_DDMACH2_DA_8822B) +#define BIT_SET_DDMACH2_DA_8822B(x, v) \ + (BIT_CLEAR_DDMACH2_DA_8822B(x) | BIT_DDMACH2_DA_8822B(v)) /* 2 REG_DDMA_CH2CTRL_8822B */ #define BIT_DDMACH2_OWN_8822B BIT(31) +#define BIT_DDMACH2_IDMEM_ERR_8822B BIT(30) #define BIT_DDMACH2_CHKSUM_EN_8822B BIT(29) #define BIT_DDMACH2_DA_W_DISABLE_8822B BIT(28) #define BIT_DDMACH2_CHKSUM_STS_8822B BIT(27) @@ -3999,31 +5842,47 @@ #define BIT_SHIFT_DDMACH2_DLEN_8822B 0 #define BIT_MASK_DDMACH2_DLEN_8822B 0x3ffff -#define BIT_DDMACH2_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH2_DLEN_8822B) << BIT_SHIFT_DDMACH2_DLEN_8822B) -#define BIT_GET_DDMACH2_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8822B) & BIT_MASK_DDMACH2_DLEN_8822B) - - +#define BIT_DDMACH2_DLEN_8822B(x) \ + (((x) & BIT_MASK_DDMACH2_DLEN_8822B) << BIT_SHIFT_DDMACH2_DLEN_8822B) +#define BITS_DDMACH2_DLEN_8822B \ + (BIT_MASK_DDMACH2_DLEN_8822B << BIT_SHIFT_DDMACH2_DLEN_8822B) +#define BIT_CLEAR_DDMACH2_DLEN_8822B(x) ((x) & (~BITS_DDMACH2_DLEN_8822B)) +#define BIT_GET_DDMACH2_DLEN_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DLEN_8822B) & BIT_MASK_DDMACH2_DLEN_8822B) +#define BIT_SET_DDMACH2_DLEN_8822B(x, v) \ + (BIT_CLEAR_DDMACH2_DLEN_8822B(x) | BIT_DDMACH2_DLEN_8822B(v)) /* 2 REG_DDMA_CH3SA_8822B */ #define BIT_SHIFT_DDMACH3_SA_8822B 0 #define BIT_MASK_DDMACH3_SA_8822B 0xffffffffL -#define BIT_DDMACH3_SA_8822B(x) (((x) & BIT_MASK_DDMACH3_SA_8822B) << BIT_SHIFT_DDMACH3_SA_8822B) -#define BIT_GET_DDMACH3_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8822B) & BIT_MASK_DDMACH3_SA_8822B) - - +#define BIT_DDMACH3_SA_8822B(x) \ + (((x) & BIT_MASK_DDMACH3_SA_8822B) << BIT_SHIFT_DDMACH3_SA_8822B) +#define BITS_DDMACH3_SA_8822B \ + (BIT_MASK_DDMACH3_SA_8822B << BIT_SHIFT_DDMACH3_SA_8822B) +#define BIT_CLEAR_DDMACH3_SA_8822B(x) ((x) & (~BITS_DDMACH3_SA_8822B)) +#define BIT_GET_DDMACH3_SA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH3_SA_8822B) & BIT_MASK_DDMACH3_SA_8822B) +#define BIT_SET_DDMACH3_SA_8822B(x, v) \ + (BIT_CLEAR_DDMACH3_SA_8822B(x) | BIT_DDMACH3_SA_8822B(v)) /* 2 REG_DDMA_CH3DA_8822B */ #define BIT_SHIFT_DDMACH3_DA_8822B 0 #define BIT_MASK_DDMACH3_DA_8822B 0xffffffffL -#define BIT_DDMACH3_DA_8822B(x) (((x) & BIT_MASK_DDMACH3_DA_8822B) << BIT_SHIFT_DDMACH3_DA_8822B) -#define BIT_GET_DDMACH3_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8822B) & BIT_MASK_DDMACH3_DA_8822B) - - +#define BIT_DDMACH3_DA_8822B(x) \ + (((x) & BIT_MASK_DDMACH3_DA_8822B) << BIT_SHIFT_DDMACH3_DA_8822B) +#define BITS_DDMACH3_DA_8822B \ + (BIT_MASK_DDMACH3_DA_8822B << BIT_SHIFT_DDMACH3_DA_8822B) +#define BIT_CLEAR_DDMACH3_DA_8822B(x) ((x) & (~BITS_DDMACH3_DA_8822B)) +#define BIT_GET_DDMACH3_DA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DA_8822B) & BIT_MASK_DDMACH3_DA_8822B) +#define BIT_SET_DDMACH3_DA_8822B(x, v) \ + (BIT_CLEAR_DDMACH3_DA_8822B(x) | BIT_DDMACH3_DA_8822B(v)) /* 2 REG_DDMA_CH3CTRL_8822B */ #define BIT_DDMACH3_OWN_8822B BIT(31) +#define BIT_DDMACH3_IDMEM_ERR_8822B BIT(30) #define BIT_DDMACH3_CHKSUM_EN_8822B BIT(29) #define BIT_DDMACH3_DA_W_DISABLE_8822B BIT(28) #define BIT_DDMACH3_CHKSUM_STS_8822B BIT(27) @@ -4033,31 +5892,47 @@ #define BIT_SHIFT_DDMACH3_DLEN_8822B 0 #define BIT_MASK_DDMACH3_DLEN_8822B 0x3ffff -#define BIT_DDMACH3_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH3_DLEN_8822B) << BIT_SHIFT_DDMACH3_DLEN_8822B) -#define BIT_GET_DDMACH3_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8822B) & BIT_MASK_DDMACH3_DLEN_8822B) - - +#define BIT_DDMACH3_DLEN_8822B(x) \ + (((x) & BIT_MASK_DDMACH3_DLEN_8822B) << BIT_SHIFT_DDMACH3_DLEN_8822B) +#define BITS_DDMACH3_DLEN_8822B \ + (BIT_MASK_DDMACH3_DLEN_8822B << BIT_SHIFT_DDMACH3_DLEN_8822B) +#define BIT_CLEAR_DDMACH3_DLEN_8822B(x) ((x) & (~BITS_DDMACH3_DLEN_8822B)) +#define BIT_GET_DDMACH3_DLEN_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DLEN_8822B) & BIT_MASK_DDMACH3_DLEN_8822B) +#define BIT_SET_DDMACH3_DLEN_8822B(x, v) \ + (BIT_CLEAR_DDMACH3_DLEN_8822B(x) | BIT_DDMACH3_DLEN_8822B(v)) /* 2 REG_DDMA_CH4SA_8822B */ #define BIT_SHIFT_DDMACH4_SA_8822B 0 #define BIT_MASK_DDMACH4_SA_8822B 0xffffffffL -#define BIT_DDMACH4_SA_8822B(x) (((x) & BIT_MASK_DDMACH4_SA_8822B) << BIT_SHIFT_DDMACH4_SA_8822B) -#define BIT_GET_DDMACH4_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8822B) & BIT_MASK_DDMACH4_SA_8822B) - - +#define BIT_DDMACH4_SA_8822B(x) \ + (((x) & BIT_MASK_DDMACH4_SA_8822B) << BIT_SHIFT_DDMACH4_SA_8822B) +#define BITS_DDMACH4_SA_8822B \ + (BIT_MASK_DDMACH4_SA_8822B << BIT_SHIFT_DDMACH4_SA_8822B) +#define BIT_CLEAR_DDMACH4_SA_8822B(x) ((x) & (~BITS_DDMACH4_SA_8822B)) +#define BIT_GET_DDMACH4_SA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH4_SA_8822B) & BIT_MASK_DDMACH4_SA_8822B) +#define BIT_SET_DDMACH4_SA_8822B(x, v) \ + (BIT_CLEAR_DDMACH4_SA_8822B(x) | BIT_DDMACH4_SA_8822B(v)) /* 2 REG_DDMA_CH4DA_8822B */ #define BIT_SHIFT_DDMACH4_DA_8822B 0 #define BIT_MASK_DDMACH4_DA_8822B 0xffffffffL -#define BIT_DDMACH4_DA_8822B(x) (((x) & BIT_MASK_DDMACH4_DA_8822B) << BIT_SHIFT_DDMACH4_DA_8822B) -#define BIT_GET_DDMACH4_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8822B) & BIT_MASK_DDMACH4_DA_8822B) - - +#define BIT_DDMACH4_DA_8822B(x) \ + (((x) & BIT_MASK_DDMACH4_DA_8822B) << BIT_SHIFT_DDMACH4_DA_8822B) +#define BITS_DDMACH4_DA_8822B \ + (BIT_MASK_DDMACH4_DA_8822B << BIT_SHIFT_DDMACH4_DA_8822B) +#define BIT_CLEAR_DDMACH4_DA_8822B(x) ((x) & (~BITS_DDMACH4_DA_8822B)) +#define BIT_GET_DDMACH4_DA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DA_8822B) & BIT_MASK_DDMACH4_DA_8822B) +#define BIT_SET_DDMACH4_DA_8822B(x, v) \ + (BIT_CLEAR_DDMACH4_DA_8822B(x) | BIT_DDMACH4_DA_8822B(v)) /* 2 REG_DDMA_CH4CTRL_8822B */ #define BIT_DDMACH4_OWN_8822B BIT(31) +#define BIT_DDMACH4_IDMEM_ERR_8822B BIT(30) #define BIT_DDMACH4_CHKSUM_EN_8822B BIT(29) #define BIT_DDMACH4_DA_W_DISABLE_8822B BIT(28) #define BIT_DDMACH4_CHKSUM_STS_8822B BIT(27) @@ -4067,31 +5942,47 @@ #define BIT_SHIFT_DDMACH4_DLEN_8822B 0 #define BIT_MASK_DDMACH4_DLEN_8822B 0x3ffff -#define BIT_DDMACH4_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH4_DLEN_8822B) << BIT_SHIFT_DDMACH4_DLEN_8822B) -#define BIT_GET_DDMACH4_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8822B) & BIT_MASK_DDMACH4_DLEN_8822B) - - +#define BIT_DDMACH4_DLEN_8822B(x) \ + (((x) & BIT_MASK_DDMACH4_DLEN_8822B) << BIT_SHIFT_DDMACH4_DLEN_8822B) +#define BITS_DDMACH4_DLEN_8822B \ + (BIT_MASK_DDMACH4_DLEN_8822B << BIT_SHIFT_DDMACH4_DLEN_8822B) +#define BIT_CLEAR_DDMACH4_DLEN_8822B(x) ((x) & (~BITS_DDMACH4_DLEN_8822B)) +#define BIT_GET_DDMACH4_DLEN_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DLEN_8822B) & BIT_MASK_DDMACH4_DLEN_8822B) +#define BIT_SET_DDMACH4_DLEN_8822B(x, v) \ + (BIT_CLEAR_DDMACH4_DLEN_8822B(x) | BIT_DDMACH4_DLEN_8822B(v)) /* 2 REG_DDMA_CH5SA_8822B */ #define BIT_SHIFT_DDMACH5_SA_8822B 0 #define BIT_MASK_DDMACH5_SA_8822B 0xffffffffL -#define BIT_DDMACH5_SA_8822B(x) (((x) & BIT_MASK_DDMACH5_SA_8822B) << BIT_SHIFT_DDMACH5_SA_8822B) -#define BIT_GET_DDMACH5_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8822B) & BIT_MASK_DDMACH5_SA_8822B) - - +#define BIT_DDMACH5_SA_8822B(x) \ + (((x) & BIT_MASK_DDMACH5_SA_8822B) << BIT_SHIFT_DDMACH5_SA_8822B) +#define BITS_DDMACH5_SA_8822B \ + (BIT_MASK_DDMACH5_SA_8822B << BIT_SHIFT_DDMACH5_SA_8822B) +#define BIT_CLEAR_DDMACH5_SA_8822B(x) ((x) & (~BITS_DDMACH5_SA_8822B)) +#define BIT_GET_DDMACH5_SA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH5_SA_8822B) & BIT_MASK_DDMACH5_SA_8822B) +#define BIT_SET_DDMACH5_SA_8822B(x, v) \ + (BIT_CLEAR_DDMACH5_SA_8822B(x) | BIT_DDMACH5_SA_8822B(v)) /* 2 REG_DDMA_CH5DA_8822B */ #define BIT_SHIFT_DDMACH5_DA_8822B 0 #define BIT_MASK_DDMACH5_DA_8822B 0xffffffffL -#define BIT_DDMACH5_DA_8822B(x) (((x) & BIT_MASK_DDMACH5_DA_8822B) << BIT_SHIFT_DDMACH5_DA_8822B) -#define BIT_GET_DDMACH5_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8822B) & BIT_MASK_DDMACH5_DA_8822B) - - +#define BIT_DDMACH5_DA_8822B(x) \ + (((x) & BIT_MASK_DDMACH5_DA_8822B) << BIT_SHIFT_DDMACH5_DA_8822B) +#define BITS_DDMACH5_DA_8822B \ + (BIT_MASK_DDMACH5_DA_8822B << BIT_SHIFT_DDMACH5_DA_8822B) +#define BIT_CLEAR_DDMACH5_DA_8822B(x) ((x) & (~BITS_DDMACH5_DA_8822B)) +#define BIT_GET_DDMACH5_DA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DA_8822B) & BIT_MASK_DDMACH5_DA_8822B) +#define BIT_SET_DDMACH5_DA_8822B(x, v) \ + (BIT_CLEAR_DDMACH5_DA_8822B(x) | BIT_DDMACH5_DA_8822B(v)) /* 2 REG_REG_DDMA_CH5CTRL_8822B */ #define BIT_DDMACH5_OWN_8822B BIT(31) +#define BIT_DDMACH5_IDMEM_ERR_8822B BIT(30) #define BIT_DDMACH5_CHKSUM_EN_8822B BIT(29) #define BIT_DDMACH5_DA_W_DISABLE_8822B BIT(28) #define BIT_DDMACH5_CHKSUM_STS_8822B BIT(27) @@ -4101,10 +5992,15 @@ #define BIT_SHIFT_DDMACH5_DLEN_8822B 0 #define BIT_MASK_DDMACH5_DLEN_8822B 0x3ffff -#define BIT_DDMACH5_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH5_DLEN_8822B) << BIT_SHIFT_DDMACH5_DLEN_8822B) -#define BIT_GET_DDMACH5_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8822B) & BIT_MASK_DDMACH5_DLEN_8822B) - - +#define BIT_DDMACH5_DLEN_8822B(x) \ + (((x) & BIT_MASK_DDMACH5_DLEN_8822B) << BIT_SHIFT_DDMACH5_DLEN_8822B) +#define BITS_DDMACH5_DLEN_8822B \ + (BIT_MASK_DDMACH5_DLEN_8822B << BIT_SHIFT_DDMACH5_DLEN_8822B) +#define BIT_CLEAR_DDMACH5_DLEN_8822B(x) ((x) & (~BITS_DDMACH5_DLEN_8822B)) +#define BIT_GET_DDMACH5_DLEN_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DLEN_8822B) & BIT_MASK_DDMACH5_DLEN_8822B) +#define BIT_SET_DDMACH5_DLEN_8822B(x, v) \ + (BIT_CLEAR_DDMACH5_DLEN_8822B(x) | BIT_DDMACH5_DLEN_8822B(v)) /* 2 REG_DDMA_INT_MSK_8822B */ #define BIT_DDMACH5_MSK_8822B BIT(5) @@ -4126,10 +6022,15 @@ #define BIT_SHIFT_IDDMA0_CHKSUM_8822B 0 #define BIT_MASK_IDDMA0_CHKSUM_8822B 0xffff -#define BIT_IDDMA0_CHKSUM_8822B(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8822B) << BIT_SHIFT_IDDMA0_CHKSUM_8822B) -#define BIT_GET_IDDMA0_CHKSUM_8822B(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822B) & BIT_MASK_IDDMA0_CHKSUM_8822B) - - +#define BIT_IDDMA0_CHKSUM_8822B(x) \ + (((x) & BIT_MASK_IDDMA0_CHKSUM_8822B) << BIT_SHIFT_IDDMA0_CHKSUM_8822B) +#define BITS_IDDMA0_CHKSUM_8822B \ + (BIT_MASK_IDDMA0_CHKSUM_8822B << BIT_SHIFT_IDDMA0_CHKSUM_8822B) +#define BIT_CLEAR_IDDMA0_CHKSUM_8822B(x) ((x) & (~BITS_IDDMA0_CHKSUM_8822B)) +#define BIT_GET_IDDMA0_CHKSUM_8822B(x) \ + (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822B) & BIT_MASK_IDDMA0_CHKSUM_8822B) +#define BIT_SET_IDDMA0_CHKSUM_8822B(x, v) \ + (BIT_CLEAR_IDDMA0_CHKSUM_8822B(x) | BIT_IDDMA0_CHKSUM_8822B(v)) /* 2 REG_DDMA_MONITOR_8822B */ #define BIT_IDDMA0_PERMU_UNDERFLOW_8822B BIT(14) @@ -4149,17 +6050,33 @@ #define BIT_SHIFT_PCIE_MAX_RXDMA_8822B 28 #define BIT_MASK_PCIE_MAX_RXDMA_8822B 0x7 -#define BIT_PCIE_MAX_RXDMA_8822B(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA_8822B) << BIT_SHIFT_PCIE_MAX_RXDMA_8822B) -#define BIT_GET_PCIE_MAX_RXDMA_8822B(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822B) & BIT_MASK_PCIE_MAX_RXDMA_8822B) - +#define BIT_PCIE_MAX_RXDMA_8822B(x) \ + (((x) & BIT_MASK_PCIE_MAX_RXDMA_8822B) \ + << BIT_SHIFT_PCIE_MAX_RXDMA_8822B) +#define BITS_PCIE_MAX_RXDMA_8822B \ + (BIT_MASK_PCIE_MAX_RXDMA_8822B << BIT_SHIFT_PCIE_MAX_RXDMA_8822B) +#define BIT_CLEAR_PCIE_MAX_RXDMA_8822B(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8822B)) +#define BIT_GET_PCIE_MAX_RXDMA_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822B) & \ + BIT_MASK_PCIE_MAX_RXDMA_8822B) +#define BIT_SET_PCIE_MAX_RXDMA_8822B(x, v) \ + (BIT_CLEAR_PCIE_MAX_RXDMA_8822B(x) | BIT_PCIE_MAX_RXDMA_8822B(v)) #define BIT_MULRW_8822B BIT(27) #define BIT_SHIFT_PCIE_MAX_TXDMA_8822B 24 #define BIT_MASK_PCIE_MAX_TXDMA_8822B 0x7 -#define BIT_PCIE_MAX_TXDMA_8822B(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA_8822B) << BIT_SHIFT_PCIE_MAX_TXDMA_8822B) -#define BIT_GET_PCIE_MAX_TXDMA_8822B(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822B) & BIT_MASK_PCIE_MAX_TXDMA_8822B) - +#define BIT_PCIE_MAX_TXDMA_8822B(x) \ + (((x) & BIT_MASK_PCIE_MAX_TXDMA_8822B) \ + << BIT_SHIFT_PCIE_MAX_TXDMA_8822B) +#define BITS_PCIE_MAX_TXDMA_8822B \ + (BIT_MASK_PCIE_MAX_TXDMA_8822B << BIT_SHIFT_PCIE_MAX_TXDMA_8822B) +#define BIT_CLEAR_PCIE_MAX_TXDMA_8822B(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8822B)) +#define BIT_GET_PCIE_MAX_TXDMA_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822B) & \ + BIT_MASK_PCIE_MAX_TXDMA_8822B) +#define BIT_SET_PCIE_MAX_TXDMA_8822B(x, v) \ + (BIT_CLEAR_PCIE_MAX_TXDMA_8822B(x) | BIT_PCIE_MAX_TXDMA_8822B(v)) #define BIT_EN_CPL_TIMEOUT_PS_8822B BIT(22) #define BIT_REG_TXDMA_FAIL_PS_8822B BIT(21) @@ -4189,428 +6106,729 @@ #define BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B 28 #define BIT_MASK_TXTTIMER_MATCH_NUM_8822B 0xf -#define BIT_TXTTIMER_MATCH_NUM_8822B(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) -#define BIT_GET_TXTTIMER_MATCH_NUM_8822B(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B) - - +#define BIT_TXTTIMER_MATCH_NUM_8822B(x) \ + (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B) \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) +#define BITS_TXTTIMER_MATCH_NUM_8822B \ + (BIT_MASK_TXTTIMER_MATCH_NUM_8822B \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) +#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8822B(x) \ + ((x) & (~BITS_TXTTIMER_MATCH_NUM_8822B)) +#define BIT_GET_TXTTIMER_MATCH_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) & \ + BIT_MASK_TXTTIMER_MATCH_NUM_8822B) +#define BIT_SET_TXTTIMER_MATCH_NUM_8822B(x, v) \ + (BIT_CLEAR_TXTTIMER_MATCH_NUM_8822B(x) | \ + BIT_TXTTIMER_MATCH_NUM_8822B(v)) #define BIT_SHIFT_TXPKT_NUM_MATCH_8822B 24 #define BIT_MASK_TXPKT_NUM_MATCH_8822B 0xf -#define BIT_TXPKT_NUM_MATCH_8822B(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8822B) << BIT_SHIFT_TXPKT_NUM_MATCH_8822B) -#define BIT_GET_TXPKT_NUM_MATCH_8822B(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8822B) & BIT_MASK_TXPKT_NUM_MATCH_8822B) - - +#define BIT_TXPKT_NUM_MATCH_8822B(x) \ + (((x) & BIT_MASK_TXPKT_NUM_MATCH_8822B) \ + << BIT_SHIFT_TXPKT_NUM_MATCH_8822B) +#define BITS_TXPKT_NUM_MATCH_8822B \ + (BIT_MASK_TXPKT_NUM_MATCH_8822B << BIT_SHIFT_TXPKT_NUM_MATCH_8822B) +#define BIT_CLEAR_TXPKT_NUM_MATCH_8822B(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8822B)) +#define BIT_GET_TXPKT_NUM_MATCH_8822B(x) \ + (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8822B) & \ + BIT_MASK_TXPKT_NUM_MATCH_8822B) +#define BIT_SET_TXPKT_NUM_MATCH_8822B(x, v) \ + (BIT_CLEAR_TXPKT_NUM_MATCH_8822B(x) | BIT_TXPKT_NUM_MATCH_8822B(v)) #define BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B 20 #define BIT_MASK_RXTTIMER_MATCH_NUM_8822B 0xf -#define BIT_RXTTIMER_MATCH_NUM_8822B(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) -#define BIT_GET_RXTTIMER_MATCH_NUM_8822B(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B) - - +#define BIT_RXTTIMER_MATCH_NUM_8822B(x) \ + (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B) \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) +#define BITS_RXTTIMER_MATCH_NUM_8822B \ + (BIT_MASK_RXTTIMER_MATCH_NUM_8822B \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) +#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8822B(x) \ + ((x) & (~BITS_RXTTIMER_MATCH_NUM_8822B)) +#define BIT_GET_RXTTIMER_MATCH_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) & \ + BIT_MASK_RXTTIMER_MATCH_NUM_8822B) +#define BIT_SET_RXTTIMER_MATCH_NUM_8822B(x, v) \ + (BIT_CLEAR_RXTTIMER_MATCH_NUM_8822B(x) | \ + BIT_RXTTIMER_MATCH_NUM_8822B(v)) #define BIT_SHIFT_RXPKT_NUM_MATCH_8822B 16 #define BIT_MASK_RXPKT_NUM_MATCH_8822B 0xf -#define BIT_RXPKT_NUM_MATCH_8822B(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8822B) << BIT_SHIFT_RXPKT_NUM_MATCH_8822B) -#define BIT_GET_RXPKT_NUM_MATCH_8822B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8822B) & BIT_MASK_RXPKT_NUM_MATCH_8822B) - - +#define BIT_RXPKT_NUM_MATCH_8822B(x) \ + (((x) & BIT_MASK_RXPKT_NUM_MATCH_8822B) \ + << BIT_SHIFT_RXPKT_NUM_MATCH_8822B) +#define BITS_RXPKT_NUM_MATCH_8822B \ + (BIT_MASK_RXPKT_NUM_MATCH_8822B << BIT_SHIFT_RXPKT_NUM_MATCH_8822B) +#define BIT_CLEAR_RXPKT_NUM_MATCH_8822B(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8822B)) +#define BIT_GET_RXPKT_NUM_MATCH_8822B(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8822B) & \ + BIT_MASK_RXPKT_NUM_MATCH_8822B) +#define BIT_SET_RXPKT_NUM_MATCH_8822B(x, v) \ + (BIT_CLEAR_RXPKT_NUM_MATCH_8822B(x) | BIT_RXPKT_NUM_MATCH_8822B(v)) #define BIT_SHIFT_MIGRATE_TIMER_8822B 0 #define BIT_MASK_MIGRATE_TIMER_8822B 0xffff -#define BIT_MIGRATE_TIMER_8822B(x) (((x) & BIT_MASK_MIGRATE_TIMER_8822B) << BIT_SHIFT_MIGRATE_TIMER_8822B) -#define BIT_GET_MIGRATE_TIMER_8822B(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8822B) & BIT_MASK_MIGRATE_TIMER_8822B) - - +#define BIT_MIGRATE_TIMER_8822B(x) \ + (((x) & BIT_MASK_MIGRATE_TIMER_8822B) << BIT_SHIFT_MIGRATE_TIMER_8822B) +#define BITS_MIGRATE_TIMER_8822B \ + (BIT_MASK_MIGRATE_TIMER_8822B << BIT_SHIFT_MIGRATE_TIMER_8822B) +#define BIT_CLEAR_MIGRATE_TIMER_8822B(x) ((x) & (~BITS_MIGRATE_TIMER_8822B)) +#define BIT_GET_MIGRATE_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_MIGRATE_TIMER_8822B) & BIT_MASK_MIGRATE_TIMER_8822B) +#define BIT_SET_MIGRATE_TIMER_8822B(x, v) \ + (BIT_CLEAR_MIGRATE_TIMER_8822B(x) | BIT_MIGRATE_TIMER_8822B(v)) /* 2 REG_BCNQ_TXBD_DESA_8822B */ #define BIT_SHIFT_BCNQ_TXBD_DESA_8822B 0 #define BIT_MASK_BCNQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_BCNQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8822B) << BIT_SHIFT_BCNQ_TXBD_DESA_8822B) -#define BIT_GET_BCNQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822B) & BIT_MASK_BCNQ_TXBD_DESA_8822B) - - +#define BIT_BCNQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_BCNQ_TXBD_DESA_8822B) \ + << BIT_SHIFT_BCNQ_TXBD_DESA_8822B) +#define BITS_BCNQ_TXBD_DESA_8822B \ + (BIT_MASK_BCNQ_TXBD_DESA_8822B << BIT_SHIFT_BCNQ_TXBD_DESA_8822B) +#define BIT_CLEAR_BCNQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8822B)) +#define BIT_GET_BCNQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822B) & \ + BIT_MASK_BCNQ_TXBD_DESA_8822B) +#define BIT_SET_BCNQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_BCNQ_TXBD_DESA_8822B(x) | BIT_BCNQ_TXBD_DESA_8822B(v)) /* 2 REG_MGQ_TXBD_DESA_8822B */ #define BIT_SHIFT_MGQ_TXBD_DESA_8822B 0 #define BIT_MASK_MGQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_MGQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8822B) << BIT_SHIFT_MGQ_TXBD_DESA_8822B) -#define BIT_GET_MGQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822B) & BIT_MASK_MGQ_TXBD_DESA_8822B) - - +#define BIT_MGQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_MGQ_TXBD_DESA_8822B) << BIT_SHIFT_MGQ_TXBD_DESA_8822B) +#define BITS_MGQ_TXBD_DESA_8822B \ + (BIT_MASK_MGQ_TXBD_DESA_8822B << BIT_SHIFT_MGQ_TXBD_DESA_8822B) +#define BIT_CLEAR_MGQ_TXBD_DESA_8822B(x) ((x) & (~BITS_MGQ_TXBD_DESA_8822B)) +#define BIT_GET_MGQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822B) & BIT_MASK_MGQ_TXBD_DESA_8822B) +#define BIT_SET_MGQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_MGQ_TXBD_DESA_8822B(x) | BIT_MGQ_TXBD_DESA_8822B(v)) /* 2 REG_VOQ_TXBD_DESA_8822B */ #define BIT_SHIFT_VOQ_TXBD_DESA_8822B 0 #define BIT_MASK_VOQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_VOQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8822B) << BIT_SHIFT_VOQ_TXBD_DESA_8822B) -#define BIT_GET_VOQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822B) & BIT_MASK_VOQ_TXBD_DESA_8822B) - - +#define BIT_VOQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_VOQ_TXBD_DESA_8822B) << BIT_SHIFT_VOQ_TXBD_DESA_8822B) +#define BITS_VOQ_TXBD_DESA_8822B \ + (BIT_MASK_VOQ_TXBD_DESA_8822B << BIT_SHIFT_VOQ_TXBD_DESA_8822B) +#define BIT_CLEAR_VOQ_TXBD_DESA_8822B(x) ((x) & (~BITS_VOQ_TXBD_DESA_8822B)) +#define BIT_GET_VOQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822B) & BIT_MASK_VOQ_TXBD_DESA_8822B) +#define BIT_SET_VOQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_VOQ_TXBD_DESA_8822B(x) | BIT_VOQ_TXBD_DESA_8822B(v)) /* 2 REG_VIQ_TXBD_DESA_8822B */ #define BIT_SHIFT_VIQ_TXBD_DESA_8822B 0 #define BIT_MASK_VIQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_VIQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8822B) << BIT_SHIFT_VIQ_TXBD_DESA_8822B) -#define BIT_GET_VIQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822B) & BIT_MASK_VIQ_TXBD_DESA_8822B) - - +#define BIT_VIQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_VIQ_TXBD_DESA_8822B) << BIT_SHIFT_VIQ_TXBD_DESA_8822B) +#define BITS_VIQ_TXBD_DESA_8822B \ + (BIT_MASK_VIQ_TXBD_DESA_8822B << BIT_SHIFT_VIQ_TXBD_DESA_8822B) +#define BIT_CLEAR_VIQ_TXBD_DESA_8822B(x) ((x) & (~BITS_VIQ_TXBD_DESA_8822B)) +#define BIT_GET_VIQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822B) & BIT_MASK_VIQ_TXBD_DESA_8822B) +#define BIT_SET_VIQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_VIQ_TXBD_DESA_8822B(x) | BIT_VIQ_TXBD_DESA_8822B(v)) /* 2 REG_BEQ_TXBD_DESA_8822B */ #define BIT_SHIFT_BEQ_TXBD_DESA_8822B 0 #define BIT_MASK_BEQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_BEQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8822B) << BIT_SHIFT_BEQ_TXBD_DESA_8822B) -#define BIT_GET_BEQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822B) & BIT_MASK_BEQ_TXBD_DESA_8822B) - - +#define BIT_BEQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_BEQ_TXBD_DESA_8822B) << BIT_SHIFT_BEQ_TXBD_DESA_8822B) +#define BITS_BEQ_TXBD_DESA_8822B \ + (BIT_MASK_BEQ_TXBD_DESA_8822B << BIT_SHIFT_BEQ_TXBD_DESA_8822B) +#define BIT_CLEAR_BEQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BEQ_TXBD_DESA_8822B)) +#define BIT_GET_BEQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822B) & BIT_MASK_BEQ_TXBD_DESA_8822B) +#define BIT_SET_BEQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_BEQ_TXBD_DESA_8822B(x) | BIT_BEQ_TXBD_DESA_8822B(v)) /* 2 REG_BKQ_TXBD_DESA_8822B */ #define BIT_SHIFT_BKQ_TXBD_DESA_8822B 0 #define BIT_MASK_BKQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_BKQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8822B) << BIT_SHIFT_BKQ_TXBD_DESA_8822B) -#define BIT_GET_BKQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822B) & BIT_MASK_BKQ_TXBD_DESA_8822B) - - +#define BIT_BKQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_BKQ_TXBD_DESA_8822B) << BIT_SHIFT_BKQ_TXBD_DESA_8822B) +#define BITS_BKQ_TXBD_DESA_8822B \ + (BIT_MASK_BKQ_TXBD_DESA_8822B << BIT_SHIFT_BKQ_TXBD_DESA_8822B) +#define BIT_CLEAR_BKQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BKQ_TXBD_DESA_8822B)) +#define BIT_GET_BKQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822B) & BIT_MASK_BKQ_TXBD_DESA_8822B) +#define BIT_SET_BKQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_BKQ_TXBD_DESA_8822B(x) | BIT_BKQ_TXBD_DESA_8822B(v)) /* 2 REG_RXQ_RXBD_DESA_8822B */ #define BIT_SHIFT_RXQ_RXBD_DESA_8822B 0 #define BIT_MASK_RXQ_RXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_RXQ_RXBD_DESA_8822B(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8822B) << BIT_SHIFT_RXQ_RXBD_DESA_8822B) -#define BIT_GET_RXQ_RXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822B) & BIT_MASK_RXQ_RXBD_DESA_8822B) - - +#define BIT_RXQ_RXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_RXQ_RXBD_DESA_8822B) << BIT_SHIFT_RXQ_RXBD_DESA_8822B) +#define BITS_RXQ_RXBD_DESA_8822B \ + (BIT_MASK_RXQ_RXBD_DESA_8822B << BIT_SHIFT_RXQ_RXBD_DESA_8822B) +#define BIT_CLEAR_RXQ_RXBD_DESA_8822B(x) ((x) & (~BITS_RXQ_RXBD_DESA_8822B)) +#define BIT_GET_RXQ_RXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822B) & BIT_MASK_RXQ_RXBD_DESA_8822B) +#define BIT_SET_RXQ_RXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_RXQ_RXBD_DESA_8822B(x) | BIT_RXQ_RXBD_DESA_8822B(v)) /* 2 REG_HI0Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI0Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI0Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI0Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8822B) << BIT_SHIFT_HI0Q_TXBD_DESA_8822B) -#define BIT_GET_HI0Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822B) & BIT_MASK_HI0Q_TXBD_DESA_8822B) - - +#define BIT_HI0Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI0Q_TXBD_DESA_8822B) +#define BITS_HI0Q_TXBD_DESA_8822B \ + (BIT_MASK_HI0Q_TXBD_DESA_8822B << BIT_SHIFT_HI0Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI0Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8822B)) +#define BIT_GET_HI0Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI0Q_TXBD_DESA_8822B) +#define BIT_SET_HI0Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_8822B(x) | BIT_HI0Q_TXBD_DESA_8822B(v)) /* 2 REG_HI1Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI1Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI1Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI1Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8822B) << BIT_SHIFT_HI1Q_TXBD_DESA_8822B) -#define BIT_GET_HI1Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822B) & BIT_MASK_HI1Q_TXBD_DESA_8822B) - - +#define BIT_HI1Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI1Q_TXBD_DESA_8822B) +#define BITS_HI1Q_TXBD_DESA_8822B \ + (BIT_MASK_HI1Q_TXBD_DESA_8822B << BIT_SHIFT_HI1Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI1Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8822B)) +#define BIT_GET_HI1Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI1Q_TXBD_DESA_8822B) +#define BIT_SET_HI1Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_8822B(x) | BIT_HI1Q_TXBD_DESA_8822B(v)) /* 2 REG_HI2Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI2Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI2Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI2Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8822B) << BIT_SHIFT_HI2Q_TXBD_DESA_8822B) -#define BIT_GET_HI2Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822B) & BIT_MASK_HI2Q_TXBD_DESA_8822B) - - +#define BIT_HI2Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI2Q_TXBD_DESA_8822B) +#define BITS_HI2Q_TXBD_DESA_8822B \ + (BIT_MASK_HI2Q_TXBD_DESA_8822B << BIT_SHIFT_HI2Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI2Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8822B)) +#define BIT_GET_HI2Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI2Q_TXBD_DESA_8822B) +#define BIT_SET_HI2Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_8822B(x) | BIT_HI2Q_TXBD_DESA_8822B(v)) /* 2 REG_HI3Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI3Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI3Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI3Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8822B) << BIT_SHIFT_HI3Q_TXBD_DESA_8822B) -#define BIT_GET_HI3Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822B) & BIT_MASK_HI3Q_TXBD_DESA_8822B) - - +#define BIT_HI3Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI3Q_TXBD_DESA_8822B) +#define BITS_HI3Q_TXBD_DESA_8822B \ + (BIT_MASK_HI3Q_TXBD_DESA_8822B << BIT_SHIFT_HI3Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI3Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8822B)) +#define BIT_GET_HI3Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI3Q_TXBD_DESA_8822B) +#define BIT_SET_HI3Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_8822B(x) | BIT_HI3Q_TXBD_DESA_8822B(v)) /* 2 REG_HI4Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI4Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI4Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI4Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8822B) << BIT_SHIFT_HI4Q_TXBD_DESA_8822B) -#define BIT_GET_HI4Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822B) & BIT_MASK_HI4Q_TXBD_DESA_8822B) - - +#define BIT_HI4Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI4Q_TXBD_DESA_8822B) +#define BITS_HI4Q_TXBD_DESA_8822B \ + (BIT_MASK_HI4Q_TXBD_DESA_8822B << BIT_SHIFT_HI4Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI4Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8822B)) +#define BIT_GET_HI4Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI4Q_TXBD_DESA_8822B) +#define BIT_SET_HI4Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_8822B(x) | BIT_HI4Q_TXBD_DESA_8822B(v)) /* 2 REG_HI5Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI5Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI5Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI5Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8822B) << BIT_SHIFT_HI5Q_TXBD_DESA_8822B) -#define BIT_GET_HI5Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822B) & BIT_MASK_HI5Q_TXBD_DESA_8822B) - - +#define BIT_HI5Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI5Q_TXBD_DESA_8822B) +#define BITS_HI5Q_TXBD_DESA_8822B \ + (BIT_MASK_HI5Q_TXBD_DESA_8822B << BIT_SHIFT_HI5Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI5Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8822B)) +#define BIT_GET_HI5Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI5Q_TXBD_DESA_8822B) +#define BIT_SET_HI5Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_8822B(x) | BIT_HI5Q_TXBD_DESA_8822B(v)) /* 2 REG_HI6Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI6Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI6Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI6Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8822B) << BIT_SHIFT_HI6Q_TXBD_DESA_8822B) -#define BIT_GET_HI6Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822B) & BIT_MASK_HI6Q_TXBD_DESA_8822B) - - +#define BIT_HI6Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI6Q_TXBD_DESA_8822B) +#define BITS_HI6Q_TXBD_DESA_8822B \ + (BIT_MASK_HI6Q_TXBD_DESA_8822B << BIT_SHIFT_HI6Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI6Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8822B)) +#define BIT_GET_HI6Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI6Q_TXBD_DESA_8822B) +#define BIT_SET_HI6Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_8822B(x) | BIT_HI6Q_TXBD_DESA_8822B(v)) /* 2 REG_HI7Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI7Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI7Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI7Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8822B) << BIT_SHIFT_HI7Q_TXBD_DESA_8822B) -#define BIT_GET_HI7Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822B) & BIT_MASK_HI7Q_TXBD_DESA_8822B) - - +#define BIT_HI7Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI7Q_TXBD_DESA_8822B) +#define BITS_HI7Q_TXBD_DESA_8822B \ + (BIT_MASK_HI7Q_TXBD_DESA_8822B << BIT_SHIFT_HI7Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI7Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8822B)) +#define BIT_GET_HI7Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI7Q_TXBD_DESA_8822B) +#define BIT_SET_HI7Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_8822B(x) | BIT_HI7Q_TXBD_DESA_8822B(v)) /* 2 REG_MGQ_TXBD_NUM_8822B */ #define BIT_PCIE_MGQ_FLAG_8822B BIT(14) #define BIT_SHIFT_MGQ_DESC_MODE_8822B 12 #define BIT_MASK_MGQ_DESC_MODE_8822B 0x3 -#define BIT_MGQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8822B) << BIT_SHIFT_MGQ_DESC_MODE_8822B) -#define BIT_GET_MGQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822B) & BIT_MASK_MGQ_DESC_MODE_8822B) - - +#define BIT_MGQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_MGQ_DESC_MODE_8822B) << BIT_SHIFT_MGQ_DESC_MODE_8822B) +#define BITS_MGQ_DESC_MODE_8822B \ + (BIT_MASK_MGQ_DESC_MODE_8822B << BIT_SHIFT_MGQ_DESC_MODE_8822B) +#define BIT_CLEAR_MGQ_DESC_MODE_8822B(x) ((x) & (~BITS_MGQ_DESC_MODE_8822B)) +#define BIT_GET_MGQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822B) & BIT_MASK_MGQ_DESC_MODE_8822B) +#define BIT_SET_MGQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_MGQ_DESC_MODE_8822B(x) | BIT_MGQ_DESC_MODE_8822B(v)) #define BIT_SHIFT_MGQ_DESC_NUM_8822B 0 #define BIT_MASK_MGQ_DESC_NUM_8822B 0xfff -#define BIT_MGQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8822B) << BIT_SHIFT_MGQ_DESC_NUM_8822B) -#define BIT_GET_MGQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822B) & BIT_MASK_MGQ_DESC_NUM_8822B) - - +#define BIT_MGQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_MGQ_DESC_NUM_8822B) << BIT_SHIFT_MGQ_DESC_NUM_8822B) +#define BITS_MGQ_DESC_NUM_8822B \ + (BIT_MASK_MGQ_DESC_NUM_8822B << BIT_SHIFT_MGQ_DESC_NUM_8822B) +#define BIT_CLEAR_MGQ_DESC_NUM_8822B(x) ((x) & (~BITS_MGQ_DESC_NUM_8822B)) +#define BIT_GET_MGQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822B) & BIT_MASK_MGQ_DESC_NUM_8822B) +#define BIT_SET_MGQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_MGQ_DESC_NUM_8822B(x) | BIT_MGQ_DESC_NUM_8822B(v)) /* 2 REG_RX_RXBD_NUM_8822B */ #define BIT_SYS_32_64_8822B BIT(15) #define BIT_SHIFT_BCNQ_DESC_MODE_8822B 13 #define BIT_MASK_BCNQ_DESC_MODE_8822B 0x3 -#define BIT_BCNQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8822B) << BIT_SHIFT_BCNQ_DESC_MODE_8822B) -#define BIT_GET_BCNQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822B) & BIT_MASK_BCNQ_DESC_MODE_8822B) - +#define BIT_BCNQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_BCNQ_DESC_MODE_8822B) \ + << BIT_SHIFT_BCNQ_DESC_MODE_8822B) +#define BITS_BCNQ_DESC_MODE_8822B \ + (BIT_MASK_BCNQ_DESC_MODE_8822B << BIT_SHIFT_BCNQ_DESC_MODE_8822B) +#define BIT_CLEAR_BCNQ_DESC_MODE_8822B(x) ((x) & (~BITS_BCNQ_DESC_MODE_8822B)) +#define BIT_GET_BCNQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822B) & \ + BIT_MASK_BCNQ_DESC_MODE_8822B) +#define BIT_SET_BCNQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_BCNQ_DESC_MODE_8822B(x) | BIT_BCNQ_DESC_MODE_8822B(v)) #define BIT_PCIE_BCNQ_FLAG_8822B BIT(12) #define BIT_SHIFT_RXQ_DESC_NUM_8822B 0 #define BIT_MASK_RXQ_DESC_NUM_8822B 0xfff -#define BIT_RXQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8822B) << BIT_SHIFT_RXQ_DESC_NUM_8822B) -#define BIT_GET_RXQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822B) & BIT_MASK_RXQ_DESC_NUM_8822B) - - +#define BIT_RXQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_RXQ_DESC_NUM_8822B) << BIT_SHIFT_RXQ_DESC_NUM_8822B) +#define BITS_RXQ_DESC_NUM_8822B \ + (BIT_MASK_RXQ_DESC_NUM_8822B << BIT_SHIFT_RXQ_DESC_NUM_8822B) +#define BIT_CLEAR_RXQ_DESC_NUM_8822B(x) ((x) & (~BITS_RXQ_DESC_NUM_8822B)) +#define BIT_GET_RXQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822B) & BIT_MASK_RXQ_DESC_NUM_8822B) +#define BIT_SET_RXQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_RXQ_DESC_NUM_8822B(x) | BIT_RXQ_DESC_NUM_8822B(v)) /* 2 REG_VOQ_TXBD_NUM_8822B */ #define BIT_PCIE_VOQ_FLAG_8822B BIT(14) #define BIT_SHIFT_VOQ_DESC_MODE_8822B 12 #define BIT_MASK_VOQ_DESC_MODE_8822B 0x3 -#define BIT_VOQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8822B) << BIT_SHIFT_VOQ_DESC_MODE_8822B) -#define BIT_GET_VOQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822B) & BIT_MASK_VOQ_DESC_MODE_8822B) - - +#define BIT_VOQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_VOQ_DESC_MODE_8822B) << BIT_SHIFT_VOQ_DESC_MODE_8822B) +#define BITS_VOQ_DESC_MODE_8822B \ + (BIT_MASK_VOQ_DESC_MODE_8822B << BIT_SHIFT_VOQ_DESC_MODE_8822B) +#define BIT_CLEAR_VOQ_DESC_MODE_8822B(x) ((x) & (~BITS_VOQ_DESC_MODE_8822B)) +#define BIT_GET_VOQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822B) & BIT_MASK_VOQ_DESC_MODE_8822B) +#define BIT_SET_VOQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_VOQ_DESC_MODE_8822B(x) | BIT_VOQ_DESC_MODE_8822B(v)) #define BIT_SHIFT_VOQ_DESC_NUM_8822B 0 #define BIT_MASK_VOQ_DESC_NUM_8822B 0xfff -#define BIT_VOQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8822B) << BIT_SHIFT_VOQ_DESC_NUM_8822B) -#define BIT_GET_VOQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822B) & BIT_MASK_VOQ_DESC_NUM_8822B) - - +#define BIT_VOQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_VOQ_DESC_NUM_8822B) << BIT_SHIFT_VOQ_DESC_NUM_8822B) +#define BITS_VOQ_DESC_NUM_8822B \ + (BIT_MASK_VOQ_DESC_NUM_8822B << BIT_SHIFT_VOQ_DESC_NUM_8822B) +#define BIT_CLEAR_VOQ_DESC_NUM_8822B(x) ((x) & (~BITS_VOQ_DESC_NUM_8822B)) +#define BIT_GET_VOQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822B) & BIT_MASK_VOQ_DESC_NUM_8822B) +#define BIT_SET_VOQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_VOQ_DESC_NUM_8822B(x) | BIT_VOQ_DESC_NUM_8822B(v)) /* 2 REG_VIQ_TXBD_NUM_8822B */ #define BIT_PCIE_VIQ_FLAG_8822B BIT(14) #define BIT_SHIFT_VIQ_DESC_MODE_8822B 12 #define BIT_MASK_VIQ_DESC_MODE_8822B 0x3 -#define BIT_VIQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8822B) << BIT_SHIFT_VIQ_DESC_MODE_8822B) -#define BIT_GET_VIQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822B) & BIT_MASK_VIQ_DESC_MODE_8822B) - - +#define BIT_VIQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_VIQ_DESC_MODE_8822B) << BIT_SHIFT_VIQ_DESC_MODE_8822B) +#define BITS_VIQ_DESC_MODE_8822B \ + (BIT_MASK_VIQ_DESC_MODE_8822B << BIT_SHIFT_VIQ_DESC_MODE_8822B) +#define BIT_CLEAR_VIQ_DESC_MODE_8822B(x) ((x) & (~BITS_VIQ_DESC_MODE_8822B)) +#define BIT_GET_VIQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822B) & BIT_MASK_VIQ_DESC_MODE_8822B) +#define BIT_SET_VIQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_VIQ_DESC_MODE_8822B(x) | BIT_VIQ_DESC_MODE_8822B(v)) #define BIT_SHIFT_VIQ_DESC_NUM_8822B 0 #define BIT_MASK_VIQ_DESC_NUM_8822B 0xfff -#define BIT_VIQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8822B) << BIT_SHIFT_VIQ_DESC_NUM_8822B) -#define BIT_GET_VIQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822B) & BIT_MASK_VIQ_DESC_NUM_8822B) - - +#define BIT_VIQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_VIQ_DESC_NUM_8822B) << BIT_SHIFT_VIQ_DESC_NUM_8822B) +#define BITS_VIQ_DESC_NUM_8822B \ + (BIT_MASK_VIQ_DESC_NUM_8822B << BIT_SHIFT_VIQ_DESC_NUM_8822B) +#define BIT_CLEAR_VIQ_DESC_NUM_8822B(x) ((x) & (~BITS_VIQ_DESC_NUM_8822B)) +#define BIT_GET_VIQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822B) & BIT_MASK_VIQ_DESC_NUM_8822B) +#define BIT_SET_VIQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_VIQ_DESC_NUM_8822B(x) | BIT_VIQ_DESC_NUM_8822B(v)) /* 2 REG_BEQ_TXBD_NUM_8822B */ #define BIT_PCIE_BEQ_FLAG_8822B BIT(14) #define BIT_SHIFT_BEQ_DESC_MODE_8822B 12 #define BIT_MASK_BEQ_DESC_MODE_8822B 0x3 -#define BIT_BEQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8822B) << BIT_SHIFT_BEQ_DESC_MODE_8822B) -#define BIT_GET_BEQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822B) & BIT_MASK_BEQ_DESC_MODE_8822B) - - +#define BIT_BEQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_BEQ_DESC_MODE_8822B) << BIT_SHIFT_BEQ_DESC_MODE_8822B) +#define BITS_BEQ_DESC_MODE_8822B \ + (BIT_MASK_BEQ_DESC_MODE_8822B << BIT_SHIFT_BEQ_DESC_MODE_8822B) +#define BIT_CLEAR_BEQ_DESC_MODE_8822B(x) ((x) & (~BITS_BEQ_DESC_MODE_8822B)) +#define BIT_GET_BEQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822B) & BIT_MASK_BEQ_DESC_MODE_8822B) +#define BIT_SET_BEQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_BEQ_DESC_MODE_8822B(x) | BIT_BEQ_DESC_MODE_8822B(v)) #define BIT_SHIFT_BEQ_DESC_NUM_8822B 0 #define BIT_MASK_BEQ_DESC_NUM_8822B 0xfff -#define BIT_BEQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8822B) << BIT_SHIFT_BEQ_DESC_NUM_8822B) -#define BIT_GET_BEQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822B) & BIT_MASK_BEQ_DESC_NUM_8822B) - - +#define BIT_BEQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_BEQ_DESC_NUM_8822B) << BIT_SHIFT_BEQ_DESC_NUM_8822B) +#define BITS_BEQ_DESC_NUM_8822B \ + (BIT_MASK_BEQ_DESC_NUM_8822B << BIT_SHIFT_BEQ_DESC_NUM_8822B) +#define BIT_CLEAR_BEQ_DESC_NUM_8822B(x) ((x) & (~BITS_BEQ_DESC_NUM_8822B)) +#define BIT_GET_BEQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822B) & BIT_MASK_BEQ_DESC_NUM_8822B) +#define BIT_SET_BEQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_BEQ_DESC_NUM_8822B(x) | BIT_BEQ_DESC_NUM_8822B(v)) /* 2 REG_BKQ_TXBD_NUM_8822B */ #define BIT_PCIE_BKQ_FLAG_8822B BIT(14) #define BIT_SHIFT_BKQ_DESC_MODE_8822B 12 #define BIT_MASK_BKQ_DESC_MODE_8822B 0x3 -#define BIT_BKQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8822B) << BIT_SHIFT_BKQ_DESC_MODE_8822B) -#define BIT_GET_BKQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822B) & BIT_MASK_BKQ_DESC_MODE_8822B) - - +#define BIT_BKQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_BKQ_DESC_MODE_8822B) << BIT_SHIFT_BKQ_DESC_MODE_8822B) +#define BITS_BKQ_DESC_MODE_8822B \ + (BIT_MASK_BKQ_DESC_MODE_8822B << BIT_SHIFT_BKQ_DESC_MODE_8822B) +#define BIT_CLEAR_BKQ_DESC_MODE_8822B(x) ((x) & (~BITS_BKQ_DESC_MODE_8822B)) +#define BIT_GET_BKQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822B) & BIT_MASK_BKQ_DESC_MODE_8822B) +#define BIT_SET_BKQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_BKQ_DESC_MODE_8822B(x) | BIT_BKQ_DESC_MODE_8822B(v)) #define BIT_SHIFT_BKQ_DESC_NUM_8822B 0 #define BIT_MASK_BKQ_DESC_NUM_8822B 0xfff -#define BIT_BKQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8822B) << BIT_SHIFT_BKQ_DESC_NUM_8822B) -#define BIT_GET_BKQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822B) & BIT_MASK_BKQ_DESC_NUM_8822B) - - +#define BIT_BKQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_BKQ_DESC_NUM_8822B) << BIT_SHIFT_BKQ_DESC_NUM_8822B) +#define BITS_BKQ_DESC_NUM_8822B \ + (BIT_MASK_BKQ_DESC_NUM_8822B << BIT_SHIFT_BKQ_DESC_NUM_8822B) +#define BIT_CLEAR_BKQ_DESC_NUM_8822B(x) ((x) & (~BITS_BKQ_DESC_NUM_8822B)) +#define BIT_GET_BKQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822B) & BIT_MASK_BKQ_DESC_NUM_8822B) +#define BIT_SET_BKQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_BKQ_DESC_NUM_8822B(x) | BIT_BKQ_DESC_NUM_8822B(v)) /* 2 REG_HI0Q_TXBD_NUM_8822B */ #define BIT_HI0Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI0Q_DESC_MODE_8822B 12 #define BIT_MASK_HI0Q_DESC_MODE_8822B 0x3 -#define BIT_HI0Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8822B) << BIT_SHIFT_HI0Q_DESC_MODE_8822B) -#define BIT_GET_HI0Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822B) & BIT_MASK_HI0Q_DESC_MODE_8822B) - - +#define BIT_HI0Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI0Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI0Q_DESC_MODE_8822B) +#define BITS_HI0Q_DESC_MODE_8822B \ + (BIT_MASK_HI0Q_DESC_MODE_8822B << BIT_SHIFT_HI0Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI0Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI0Q_DESC_MODE_8822B)) +#define BIT_GET_HI0Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822B) & \ + BIT_MASK_HI0Q_DESC_MODE_8822B) +#define BIT_SET_HI0Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI0Q_DESC_MODE_8822B(x) | BIT_HI0Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI0Q_DESC_NUM_8822B 0 #define BIT_MASK_HI0Q_DESC_NUM_8822B 0xfff -#define BIT_HI0Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8822B) << BIT_SHIFT_HI0Q_DESC_NUM_8822B) -#define BIT_GET_HI0Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822B) & BIT_MASK_HI0Q_DESC_NUM_8822B) - - +#define BIT_HI0Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI0Q_DESC_NUM_8822B) << BIT_SHIFT_HI0Q_DESC_NUM_8822B) +#define BITS_HI0Q_DESC_NUM_8822B \ + (BIT_MASK_HI0Q_DESC_NUM_8822B << BIT_SHIFT_HI0Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI0Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI0Q_DESC_NUM_8822B)) +#define BIT_GET_HI0Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822B) & BIT_MASK_HI0Q_DESC_NUM_8822B) +#define BIT_SET_HI0Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI0Q_DESC_NUM_8822B(x) | BIT_HI0Q_DESC_NUM_8822B(v)) /* 2 REG_HI1Q_TXBD_NUM_8822B */ #define BIT_HI1Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI1Q_DESC_MODE_8822B 12 #define BIT_MASK_HI1Q_DESC_MODE_8822B 0x3 -#define BIT_HI1Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8822B) << BIT_SHIFT_HI1Q_DESC_MODE_8822B) -#define BIT_GET_HI1Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822B) & BIT_MASK_HI1Q_DESC_MODE_8822B) - - +#define BIT_HI1Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI1Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI1Q_DESC_MODE_8822B) +#define BITS_HI1Q_DESC_MODE_8822B \ + (BIT_MASK_HI1Q_DESC_MODE_8822B << BIT_SHIFT_HI1Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI1Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI1Q_DESC_MODE_8822B)) +#define BIT_GET_HI1Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822B) & \ + BIT_MASK_HI1Q_DESC_MODE_8822B) +#define BIT_SET_HI1Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI1Q_DESC_MODE_8822B(x) | BIT_HI1Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI1Q_DESC_NUM_8822B 0 #define BIT_MASK_HI1Q_DESC_NUM_8822B 0xfff -#define BIT_HI1Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8822B) << BIT_SHIFT_HI1Q_DESC_NUM_8822B) -#define BIT_GET_HI1Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822B) & BIT_MASK_HI1Q_DESC_NUM_8822B) - - +#define BIT_HI1Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI1Q_DESC_NUM_8822B) << BIT_SHIFT_HI1Q_DESC_NUM_8822B) +#define BITS_HI1Q_DESC_NUM_8822B \ + (BIT_MASK_HI1Q_DESC_NUM_8822B << BIT_SHIFT_HI1Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI1Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI1Q_DESC_NUM_8822B)) +#define BIT_GET_HI1Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822B) & BIT_MASK_HI1Q_DESC_NUM_8822B) +#define BIT_SET_HI1Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI1Q_DESC_NUM_8822B(x) | BIT_HI1Q_DESC_NUM_8822B(v)) /* 2 REG_HI2Q_TXBD_NUM_8822B */ #define BIT_HI2Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI2Q_DESC_MODE_8822B 12 #define BIT_MASK_HI2Q_DESC_MODE_8822B 0x3 -#define BIT_HI2Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8822B) << BIT_SHIFT_HI2Q_DESC_MODE_8822B) -#define BIT_GET_HI2Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822B) & BIT_MASK_HI2Q_DESC_MODE_8822B) - - +#define BIT_HI2Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI2Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI2Q_DESC_MODE_8822B) +#define BITS_HI2Q_DESC_MODE_8822B \ + (BIT_MASK_HI2Q_DESC_MODE_8822B << BIT_SHIFT_HI2Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI2Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI2Q_DESC_MODE_8822B)) +#define BIT_GET_HI2Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822B) & \ + BIT_MASK_HI2Q_DESC_MODE_8822B) +#define BIT_SET_HI2Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI2Q_DESC_MODE_8822B(x) | BIT_HI2Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI2Q_DESC_NUM_8822B 0 #define BIT_MASK_HI2Q_DESC_NUM_8822B 0xfff -#define BIT_HI2Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8822B) << BIT_SHIFT_HI2Q_DESC_NUM_8822B) -#define BIT_GET_HI2Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822B) & BIT_MASK_HI2Q_DESC_NUM_8822B) - - +#define BIT_HI2Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI2Q_DESC_NUM_8822B) << BIT_SHIFT_HI2Q_DESC_NUM_8822B) +#define BITS_HI2Q_DESC_NUM_8822B \ + (BIT_MASK_HI2Q_DESC_NUM_8822B << BIT_SHIFT_HI2Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI2Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI2Q_DESC_NUM_8822B)) +#define BIT_GET_HI2Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822B) & BIT_MASK_HI2Q_DESC_NUM_8822B) +#define BIT_SET_HI2Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI2Q_DESC_NUM_8822B(x) | BIT_HI2Q_DESC_NUM_8822B(v)) /* 2 REG_HI3Q_TXBD_NUM_8822B */ #define BIT_HI3Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI3Q_DESC_MODE_8822B 12 #define BIT_MASK_HI3Q_DESC_MODE_8822B 0x3 -#define BIT_HI3Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8822B) << BIT_SHIFT_HI3Q_DESC_MODE_8822B) -#define BIT_GET_HI3Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822B) & BIT_MASK_HI3Q_DESC_MODE_8822B) - - +#define BIT_HI3Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI3Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI3Q_DESC_MODE_8822B) +#define BITS_HI3Q_DESC_MODE_8822B \ + (BIT_MASK_HI3Q_DESC_MODE_8822B << BIT_SHIFT_HI3Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI3Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI3Q_DESC_MODE_8822B)) +#define BIT_GET_HI3Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822B) & \ + BIT_MASK_HI3Q_DESC_MODE_8822B) +#define BIT_SET_HI3Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI3Q_DESC_MODE_8822B(x) | BIT_HI3Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI3Q_DESC_NUM_8822B 0 #define BIT_MASK_HI3Q_DESC_NUM_8822B 0xfff -#define BIT_HI3Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8822B) << BIT_SHIFT_HI3Q_DESC_NUM_8822B) -#define BIT_GET_HI3Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822B) & BIT_MASK_HI3Q_DESC_NUM_8822B) - - +#define BIT_HI3Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI3Q_DESC_NUM_8822B) << BIT_SHIFT_HI3Q_DESC_NUM_8822B) +#define BITS_HI3Q_DESC_NUM_8822B \ + (BIT_MASK_HI3Q_DESC_NUM_8822B << BIT_SHIFT_HI3Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI3Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI3Q_DESC_NUM_8822B)) +#define BIT_GET_HI3Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822B) & BIT_MASK_HI3Q_DESC_NUM_8822B) +#define BIT_SET_HI3Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI3Q_DESC_NUM_8822B(x) | BIT_HI3Q_DESC_NUM_8822B(v)) /* 2 REG_HI4Q_TXBD_NUM_8822B */ #define BIT_HI4Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI4Q_DESC_MODE_8822B 12 #define BIT_MASK_HI4Q_DESC_MODE_8822B 0x3 -#define BIT_HI4Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8822B) << BIT_SHIFT_HI4Q_DESC_MODE_8822B) -#define BIT_GET_HI4Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822B) & BIT_MASK_HI4Q_DESC_MODE_8822B) - - +#define BIT_HI4Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI4Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI4Q_DESC_MODE_8822B) +#define BITS_HI4Q_DESC_MODE_8822B \ + (BIT_MASK_HI4Q_DESC_MODE_8822B << BIT_SHIFT_HI4Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI4Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI4Q_DESC_MODE_8822B)) +#define BIT_GET_HI4Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822B) & \ + BIT_MASK_HI4Q_DESC_MODE_8822B) +#define BIT_SET_HI4Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI4Q_DESC_MODE_8822B(x) | BIT_HI4Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI4Q_DESC_NUM_8822B 0 #define BIT_MASK_HI4Q_DESC_NUM_8822B 0xfff -#define BIT_HI4Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8822B) << BIT_SHIFT_HI4Q_DESC_NUM_8822B) -#define BIT_GET_HI4Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822B) & BIT_MASK_HI4Q_DESC_NUM_8822B) - - +#define BIT_HI4Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI4Q_DESC_NUM_8822B) << BIT_SHIFT_HI4Q_DESC_NUM_8822B) +#define BITS_HI4Q_DESC_NUM_8822B \ + (BIT_MASK_HI4Q_DESC_NUM_8822B << BIT_SHIFT_HI4Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI4Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI4Q_DESC_NUM_8822B)) +#define BIT_GET_HI4Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822B) & BIT_MASK_HI4Q_DESC_NUM_8822B) +#define BIT_SET_HI4Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI4Q_DESC_NUM_8822B(x) | BIT_HI4Q_DESC_NUM_8822B(v)) /* 2 REG_HI5Q_TXBD_NUM_8822B */ #define BIT_HI5Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI5Q_DESC_MODE_8822B 12 #define BIT_MASK_HI5Q_DESC_MODE_8822B 0x3 -#define BIT_HI5Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8822B) << BIT_SHIFT_HI5Q_DESC_MODE_8822B) -#define BIT_GET_HI5Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822B) & BIT_MASK_HI5Q_DESC_MODE_8822B) - - +#define BIT_HI5Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI5Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI5Q_DESC_MODE_8822B) +#define BITS_HI5Q_DESC_MODE_8822B \ + (BIT_MASK_HI5Q_DESC_MODE_8822B << BIT_SHIFT_HI5Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI5Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI5Q_DESC_MODE_8822B)) +#define BIT_GET_HI5Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822B) & \ + BIT_MASK_HI5Q_DESC_MODE_8822B) +#define BIT_SET_HI5Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI5Q_DESC_MODE_8822B(x) | BIT_HI5Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI5Q_DESC_NUM_8822B 0 #define BIT_MASK_HI5Q_DESC_NUM_8822B 0xfff -#define BIT_HI5Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8822B) << BIT_SHIFT_HI5Q_DESC_NUM_8822B) -#define BIT_GET_HI5Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822B) & BIT_MASK_HI5Q_DESC_NUM_8822B) - - +#define BIT_HI5Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI5Q_DESC_NUM_8822B) << BIT_SHIFT_HI5Q_DESC_NUM_8822B) +#define BITS_HI5Q_DESC_NUM_8822B \ + (BIT_MASK_HI5Q_DESC_NUM_8822B << BIT_SHIFT_HI5Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI5Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI5Q_DESC_NUM_8822B)) +#define BIT_GET_HI5Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822B) & BIT_MASK_HI5Q_DESC_NUM_8822B) +#define BIT_SET_HI5Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI5Q_DESC_NUM_8822B(x) | BIT_HI5Q_DESC_NUM_8822B(v)) /* 2 REG_HI6Q_TXBD_NUM_8822B */ #define BIT_HI6Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI6Q_DESC_MODE_8822B 12 #define BIT_MASK_HI6Q_DESC_MODE_8822B 0x3 -#define BIT_HI6Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8822B) << BIT_SHIFT_HI6Q_DESC_MODE_8822B) -#define BIT_GET_HI6Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822B) & BIT_MASK_HI6Q_DESC_MODE_8822B) - - +#define BIT_HI6Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI6Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI6Q_DESC_MODE_8822B) +#define BITS_HI6Q_DESC_MODE_8822B \ + (BIT_MASK_HI6Q_DESC_MODE_8822B << BIT_SHIFT_HI6Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI6Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI6Q_DESC_MODE_8822B)) +#define BIT_GET_HI6Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822B) & \ + BIT_MASK_HI6Q_DESC_MODE_8822B) +#define BIT_SET_HI6Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI6Q_DESC_MODE_8822B(x) | BIT_HI6Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI6Q_DESC_NUM_8822B 0 #define BIT_MASK_HI6Q_DESC_NUM_8822B 0xfff -#define BIT_HI6Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8822B) << BIT_SHIFT_HI6Q_DESC_NUM_8822B) -#define BIT_GET_HI6Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822B) & BIT_MASK_HI6Q_DESC_NUM_8822B) - - +#define BIT_HI6Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI6Q_DESC_NUM_8822B) << BIT_SHIFT_HI6Q_DESC_NUM_8822B) +#define BITS_HI6Q_DESC_NUM_8822B \ + (BIT_MASK_HI6Q_DESC_NUM_8822B << BIT_SHIFT_HI6Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI6Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI6Q_DESC_NUM_8822B)) +#define BIT_GET_HI6Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822B) & BIT_MASK_HI6Q_DESC_NUM_8822B) +#define BIT_SET_HI6Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI6Q_DESC_NUM_8822B(x) | BIT_HI6Q_DESC_NUM_8822B(v)) /* 2 REG_HI7Q_TXBD_NUM_8822B */ #define BIT_HI7Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI7Q_DESC_MODE_8822B 12 #define BIT_MASK_HI7Q_DESC_MODE_8822B 0x3 -#define BIT_HI7Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8822B) << BIT_SHIFT_HI7Q_DESC_MODE_8822B) -#define BIT_GET_HI7Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822B) & BIT_MASK_HI7Q_DESC_MODE_8822B) - - +#define BIT_HI7Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI7Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI7Q_DESC_MODE_8822B) +#define BITS_HI7Q_DESC_MODE_8822B \ + (BIT_MASK_HI7Q_DESC_MODE_8822B << BIT_SHIFT_HI7Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI7Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI7Q_DESC_MODE_8822B)) +#define BIT_GET_HI7Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822B) & \ + BIT_MASK_HI7Q_DESC_MODE_8822B) +#define BIT_SET_HI7Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI7Q_DESC_MODE_8822B(x) | BIT_HI7Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI7Q_DESC_NUM_8822B 0 #define BIT_MASK_HI7Q_DESC_NUM_8822B 0xfff -#define BIT_HI7Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8822B) << BIT_SHIFT_HI7Q_DESC_NUM_8822B) -#define BIT_GET_HI7Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822B) & BIT_MASK_HI7Q_DESC_NUM_8822B) - - +#define BIT_HI7Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI7Q_DESC_NUM_8822B) << BIT_SHIFT_HI7Q_DESC_NUM_8822B) +#define BITS_HI7Q_DESC_NUM_8822B \ + (BIT_MASK_HI7Q_DESC_NUM_8822B << BIT_SHIFT_HI7Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI7Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI7Q_DESC_NUM_8822B)) +#define BIT_GET_HI7Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822B) & BIT_MASK_HI7Q_DESC_NUM_8822B) +#define BIT_SET_HI7Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI7Q_DESC_NUM_8822B(x) | BIT_HI7Q_DESC_NUM_8822B(v)) /* 2 REG_TSFTIMER_HCI_8822B */ #define BIT_SHIFT_TSFT2_HCI_8822B 16 #define BIT_MASK_TSFT2_HCI_8822B 0xffff -#define BIT_TSFT2_HCI_8822B(x) (((x) & BIT_MASK_TSFT2_HCI_8822B) << BIT_SHIFT_TSFT2_HCI_8822B) -#define BIT_GET_TSFT2_HCI_8822B(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8822B) & BIT_MASK_TSFT2_HCI_8822B) - - +#define BIT_TSFT2_HCI_8822B(x) \ + (((x) & BIT_MASK_TSFT2_HCI_8822B) << BIT_SHIFT_TSFT2_HCI_8822B) +#define BITS_TSFT2_HCI_8822B \ + (BIT_MASK_TSFT2_HCI_8822B << BIT_SHIFT_TSFT2_HCI_8822B) +#define BIT_CLEAR_TSFT2_HCI_8822B(x) ((x) & (~BITS_TSFT2_HCI_8822B)) +#define BIT_GET_TSFT2_HCI_8822B(x) \ + (((x) >> BIT_SHIFT_TSFT2_HCI_8822B) & BIT_MASK_TSFT2_HCI_8822B) +#define BIT_SET_TSFT2_HCI_8822B(x, v) \ + (BIT_CLEAR_TSFT2_HCI_8822B(x) | BIT_TSFT2_HCI_8822B(v)) #define BIT_SHIFT_TSFT1_HCI_8822B 0 #define BIT_MASK_TSFT1_HCI_8822B 0xffff -#define BIT_TSFT1_HCI_8822B(x) (((x) & BIT_MASK_TSFT1_HCI_8822B) << BIT_SHIFT_TSFT1_HCI_8822B) -#define BIT_GET_TSFT1_HCI_8822B(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8822B) & BIT_MASK_TSFT1_HCI_8822B) - - +#define BIT_TSFT1_HCI_8822B(x) \ + (((x) & BIT_MASK_TSFT1_HCI_8822B) << BIT_SHIFT_TSFT1_HCI_8822B) +#define BITS_TSFT1_HCI_8822B \ + (BIT_MASK_TSFT1_HCI_8822B << BIT_SHIFT_TSFT1_HCI_8822B) +#define BIT_CLEAR_TSFT1_HCI_8822B(x) ((x) & (~BITS_TSFT1_HCI_8822B)) +#define BIT_GET_TSFT1_HCI_8822B(x) \ + (((x) >> BIT_SHIFT_TSFT1_HCI_8822B) & BIT_MASK_TSFT1_HCI_8822B) +#define BIT_SET_TSFT1_HCI_8822B(x, v) \ + (BIT_CLEAR_TSFT1_HCI_8822B(x) | BIT_TSFT1_HCI_8822B(v)) /* 2 REG_BD_RWPTR_CLR_8822B */ #define BIT_CLR_HI7Q_HW_IDX_8822B BIT(29) @@ -4646,252 +6864,406 @@ #define BIT_SHIFT_VOQ_HW_IDX_8822B 16 #define BIT_MASK_VOQ_HW_IDX_8822B 0xfff -#define BIT_VOQ_HW_IDX_8822B(x) (((x) & BIT_MASK_VOQ_HW_IDX_8822B) << BIT_SHIFT_VOQ_HW_IDX_8822B) -#define BIT_GET_VOQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8822B) & BIT_MASK_VOQ_HW_IDX_8822B) - - +#define BIT_VOQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_VOQ_HW_IDX_8822B) << BIT_SHIFT_VOQ_HW_IDX_8822B) +#define BITS_VOQ_HW_IDX_8822B \ + (BIT_MASK_VOQ_HW_IDX_8822B << BIT_SHIFT_VOQ_HW_IDX_8822B) +#define BIT_CLEAR_VOQ_HW_IDX_8822B(x) ((x) & (~BITS_VOQ_HW_IDX_8822B)) +#define BIT_GET_VOQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_VOQ_HW_IDX_8822B) & BIT_MASK_VOQ_HW_IDX_8822B) +#define BIT_SET_VOQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_VOQ_HW_IDX_8822B(x) | BIT_VOQ_HW_IDX_8822B(v)) #define BIT_SHIFT_VOQ_HOST_IDX_8822B 0 #define BIT_MASK_VOQ_HOST_IDX_8822B 0xfff -#define BIT_VOQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8822B) << BIT_SHIFT_VOQ_HOST_IDX_8822B) -#define BIT_GET_VOQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822B) & BIT_MASK_VOQ_HOST_IDX_8822B) - - +#define BIT_VOQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_VOQ_HOST_IDX_8822B) << BIT_SHIFT_VOQ_HOST_IDX_8822B) +#define BITS_VOQ_HOST_IDX_8822B \ + (BIT_MASK_VOQ_HOST_IDX_8822B << BIT_SHIFT_VOQ_HOST_IDX_8822B) +#define BIT_CLEAR_VOQ_HOST_IDX_8822B(x) ((x) & (~BITS_VOQ_HOST_IDX_8822B)) +#define BIT_GET_VOQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822B) & BIT_MASK_VOQ_HOST_IDX_8822B) +#define BIT_SET_VOQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_VOQ_HOST_IDX_8822B(x) | BIT_VOQ_HOST_IDX_8822B(v)) /* 2 REG_VIQ_TXBD_IDX_8822B */ #define BIT_SHIFT_VIQ_HW_IDX_8822B 16 #define BIT_MASK_VIQ_HW_IDX_8822B 0xfff -#define BIT_VIQ_HW_IDX_8822B(x) (((x) & BIT_MASK_VIQ_HW_IDX_8822B) << BIT_SHIFT_VIQ_HW_IDX_8822B) -#define BIT_GET_VIQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8822B) & BIT_MASK_VIQ_HW_IDX_8822B) - - +#define BIT_VIQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_VIQ_HW_IDX_8822B) << BIT_SHIFT_VIQ_HW_IDX_8822B) +#define BITS_VIQ_HW_IDX_8822B \ + (BIT_MASK_VIQ_HW_IDX_8822B << BIT_SHIFT_VIQ_HW_IDX_8822B) +#define BIT_CLEAR_VIQ_HW_IDX_8822B(x) ((x) & (~BITS_VIQ_HW_IDX_8822B)) +#define BIT_GET_VIQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_VIQ_HW_IDX_8822B) & BIT_MASK_VIQ_HW_IDX_8822B) +#define BIT_SET_VIQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_VIQ_HW_IDX_8822B(x) | BIT_VIQ_HW_IDX_8822B(v)) #define BIT_SHIFT_VIQ_HOST_IDX_8822B 0 #define BIT_MASK_VIQ_HOST_IDX_8822B 0xfff -#define BIT_VIQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8822B) << BIT_SHIFT_VIQ_HOST_IDX_8822B) -#define BIT_GET_VIQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822B) & BIT_MASK_VIQ_HOST_IDX_8822B) - - +#define BIT_VIQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_VIQ_HOST_IDX_8822B) << BIT_SHIFT_VIQ_HOST_IDX_8822B) +#define BITS_VIQ_HOST_IDX_8822B \ + (BIT_MASK_VIQ_HOST_IDX_8822B << BIT_SHIFT_VIQ_HOST_IDX_8822B) +#define BIT_CLEAR_VIQ_HOST_IDX_8822B(x) ((x) & (~BITS_VIQ_HOST_IDX_8822B)) +#define BIT_GET_VIQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822B) & BIT_MASK_VIQ_HOST_IDX_8822B) +#define BIT_SET_VIQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_VIQ_HOST_IDX_8822B(x) | BIT_VIQ_HOST_IDX_8822B(v)) /* 2 REG_BEQ_TXBD_IDX_8822B */ #define BIT_SHIFT_BEQ_HW_IDX_8822B 16 #define BIT_MASK_BEQ_HW_IDX_8822B 0xfff -#define BIT_BEQ_HW_IDX_8822B(x) (((x) & BIT_MASK_BEQ_HW_IDX_8822B) << BIT_SHIFT_BEQ_HW_IDX_8822B) -#define BIT_GET_BEQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8822B) & BIT_MASK_BEQ_HW_IDX_8822B) - - +#define BIT_BEQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_BEQ_HW_IDX_8822B) << BIT_SHIFT_BEQ_HW_IDX_8822B) +#define BITS_BEQ_HW_IDX_8822B \ + (BIT_MASK_BEQ_HW_IDX_8822B << BIT_SHIFT_BEQ_HW_IDX_8822B) +#define BIT_CLEAR_BEQ_HW_IDX_8822B(x) ((x) & (~BITS_BEQ_HW_IDX_8822B)) +#define BIT_GET_BEQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_BEQ_HW_IDX_8822B) & BIT_MASK_BEQ_HW_IDX_8822B) +#define BIT_SET_BEQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_BEQ_HW_IDX_8822B(x) | BIT_BEQ_HW_IDX_8822B(v)) #define BIT_SHIFT_BEQ_HOST_IDX_8822B 0 #define BIT_MASK_BEQ_HOST_IDX_8822B 0xfff -#define BIT_BEQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8822B) << BIT_SHIFT_BEQ_HOST_IDX_8822B) -#define BIT_GET_BEQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822B) & BIT_MASK_BEQ_HOST_IDX_8822B) - - +#define BIT_BEQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_BEQ_HOST_IDX_8822B) << BIT_SHIFT_BEQ_HOST_IDX_8822B) +#define BITS_BEQ_HOST_IDX_8822B \ + (BIT_MASK_BEQ_HOST_IDX_8822B << BIT_SHIFT_BEQ_HOST_IDX_8822B) +#define BIT_CLEAR_BEQ_HOST_IDX_8822B(x) ((x) & (~BITS_BEQ_HOST_IDX_8822B)) +#define BIT_GET_BEQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822B) & BIT_MASK_BEQ_HOST_IDX_8822B) +#define BIT_SET_BEQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_BEQ_HOST_IDX_8822B(x) | BIT_BEQ_HOST_IDX_8822B(v)) /* 2 REG_BKQ_TXBD_IDX_8822B */ #define BIT_SHIFT_BKQ_HW_IDX_8822B 16 #define BIT_MASK_BKQ_HW_IDX_8822B 0xfff -#define BIT_BKQ_HW_IDX_8822B(x) (((x) & BIT_MASK_BKQ_HW_IDX_8822B) << BIT_SHIFT_BKQ_HW_IDX_8822B) -#define BIT_GET_BKQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8822B) & BIT_MASK_BKQ_HW_IDX_8822B) - - +#define BIT_BKQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_BKQ_HW_IDX_8822B) << BIT_SHIFT_BKQ_HW_IDX_8822B) +#define BITS_BKQ_HW_IDX_8822B \ + (BIT_MASK_BKQ_HW_IDX_8822B << BIT_SHIFT_BKQ_HW_IDX_8822B) +#define BIT_CLEAR_BKQ_HW_IDX_8822B(x) ((x) & (~BITS_BKQ_HW_IDX_8822B)) +#define BIT_GET_BKQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_BKQ_HW_IDX_8822B) & BIT_MASK_BKQ_HW_IDX_8822B) +#define BIT_SET_BKQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_BKQ_HW_IDX_8822B(x) | BIT_BKQ_HW_IDX_8822B(v)) #define BIT_SHIFT_BKQ_HOST_IDX_8822B 0 #define BIT_MASK_BKQ_HOST_IDX_8822B 0xfff -#define BIT_BKQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8822B) << BIT_SHIFT_BKQ_HOST_IDX_8822B) -#define BIT_GET_BKQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822B) & BIT_MASK_BKQ_HOST_IDX_8822B) - - +#define BIT_BKQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_BKQ_HOST_IDX_8822B) << BIT_SHIFT_BKQ_HOST_IDX_8822B) +#define BITS_BKQ_HOST_IDX_8822B \ + (BIT_MASK_BKQ_HOST_IDX_8822B << BIT_SHIFT_BKQ_HOST_IDX_8822B) +#define BIT_CLEAR_BKQ_HOST_IDX_8822B(x) ((x) & (~BITS_BKQ_HOST_IDX_8822B)) +#define BIT_GET_BKQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822B) & BIT_MASK_BKQ_HOST_IDX_8822B) +#define BIT_SET_BKQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_BKQ_HOST_IDX_8822B(x) | BIT_BKQ_HOST_IDX_8822B(v)) /* 2 REG_MGQ_TXBD_IDX_8822B */ #define BIT_SHIFT_MGQ_HW_IDX_8822B 16 #define BIT_MASK_MGQ_HW_IDX_8822B 0xfff -#define BIT_MGQ_HW_IDX_8822B(x) (((x) & BIT_MASK_MGQ_HW_IDX_8822B) << BIT_SHIFT_MGQ_HW_IDX_8822B) -#define BIT_GET_MGQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8822B) & BIT_MASK_MGQ_HW_IDX_8822B) - - +#define BIT_MGQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_MGQ_HW_IDX_8822B) << BIT_SHIFT_MGQ_HW_IDX_8822B) +#define BITS_MGQ_HW_IDX_8822B \ + (BIT_MASK_MGQ_HW_IDX_8822B << BIT_SHIFT_MGQ_HW_IDX_8822B) +#define BIT_CLEAR_MGQ_HW_IDX_8822B(x) ((x) & (~BITS_MGQ_HW_IDX_8822B)) +#define BIT_GET_MGQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_HW_IDX_8822B) & BIT_MASK_MGQ_HW_IDX_8822B) +#define BIT_SET_MGQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_MGQ_HW_IDX_8822B(x) | BIT_MGQ_HW_IDX_8822B(v)) #define BIT_SHIFT_MGQ_HOST_IDX_8822B 0 #define BIT_MASK_MGQ_HOST_IDX_8822B 0xfff -#define BIT_MGQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8822B) << BIT_SHIFT_MGQ_HOST_IDX_8822B) -#define BIT_GET_MGQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822B) & BIT_MASK_MGQ_HOST_IDX_8822B) - - +#define BIT_MGQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_MGQ_HOST_IDX_8822B) << BIT_SHIFT_MGQ_HOST_IDX_8822B) +#define BITS_MGQ_HOST_IDX_8822B \ + (BIT_MASK_MGQ_HOST_IDX_8822B << BIT_SHIFT_MGQ_HOST_IDX_8822B) +#define BIT_CLEAR_MGQ_HOST_IDX_8822B(x) ((x) & (~BITS_MGQ_HOST_IDX_8822B)) +#define BIT_GET_MGQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822B) & BIT_MASK_MGQ_HOST_IDX_8822B) +#define BIT_SET_MGQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_MGQ_HOST_IDX_8822B(x) | BIT_MGQ_HOST_IDX_8822B(v)) /* 2 REG_RXQ_RXBD_IDX_8822B */ #define BIT_SHIFT_RXQ_HW_IDX_8822B 16 #define BIT_MASK_RXQ_HW_IDX_8822B 0xfff -#define BIT_RXQ_HW_IDX_8822B(x) (((x) & BIT_MASK_RXQ_HW_IDX_8822B) << BIT_SHIFT_RXQ_HW_IDX_8822B) -#define BIT_GET_RXQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8822B) & BIT_MASK_RXQ_HW_IDX_8822B) - - +#define BIT_RXQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_RXQ_HW_IDX_8822B) << BIT_SHIFT_RXQ_HW_IDX_8822B) +#define BITS_RXQ_HW_IDX_8822B \ + (BIT_MASK_RXQ_HW_IDX_8822B << BIT_SHIFT_RXQ_HW_IDX_8822B) +#define BIT_CLEAR_RXQ_HW_IDX_8822B(x) ((x) & (~BITS_RXQ_HW_IDX_8822B)) +#define BIT_GET_RXQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RXQ_HW_IDX_8822B) & BIT_MASK_RXQ_HW_IDX_8822B) +#define BIT_SET_RXQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_RXQ_HW_IDX_8822B(x) | BIT_RXQ_HW_IDX_8822B(v)) #define BIT_SHIFT_RXQ_HOST_IDX_8822B 0 #define BIT_MASK_RXQ_HOST_IDX_8822B 0xfff -#define BIT_RXQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8822B) << BIT_SHIFT_RXQ_HOST_IDX_8822B) -#define BIT_GET_RXQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822B) & BIT_MASK_RXQ_HOST_IDX_8822B) - - +#define BIT_RXQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_RXQ_HOST_IDX_8822B) << BIT_SHIFT_RXQ_HOST_IDX_8822B) +#define BITS_RXQ_HOST_IDX_8822B \ + (BIT_MASK_RXQ_HOST_IDX_8822B << BIT_SHIFT_RXQ_HOST_IDX_8822B) +#define BIT_CLEAR_RXQ_HOST_IDX_8822B(x) ((x) & (~BITS_RXQ_HOST_IDX_8822B)) +#define BIT_GET_RXQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822B) & BIT_MASK_RXQ_HOST_IDX_8822B) +#define BIT_SET_RXQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_RXQ_HOST_IDX_8822B(x) | BIT_RXQ_HOST_IDX_8822B(v)) /* 2 REG_HI0Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI0Q_HW_IDX_8822B 16 #define BIT_MASK_HI0Q_HW_IDX_8822B 0xfff -#define BIT_HI0Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8822B) << BIT_SHIFT_HI0Q_HW_IDX_8822B) -#define BIT_GET_HI0Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822B) & BIT_MASK_HI0Q_HW_IDX_8822B) - - +#define BIT_HI0Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI0Q_HW_IDX_8822B) << BIT_SHIFT_HI0Q_HW_IDX_8822B) +#define BITS_HI0Q_HW_IDX_8822B \ + (BIT_MASK_HI0Q_HW_IDX_8822B << BIT_SHIFT_HI0Q_HW_IDX_8822B) +#define BIT_CLEAR_HI0Q_HW_IDX_8822B(x) ((x) & (~BITS_HI0Q_HW_IDX_8822B)) +#define BIT_GET_HI0Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822B) & BIT_MASK_HI0Q_HW_IDX_8822B) +#define BIT_SET_HI0Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI0Q_HW_IDX_8822B(x) | BIT_HI0Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI0Q_HOST_IDX_8822B 0 #define BIT_MASK_HI0Q_HOST_IDX_8822B 0xfff -#define BIT_HI0Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8822B) << BIT_SHIFT_HI0Q_HOST_IDX_8822B) -#define BIT_GET_HI0Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822B) & BIT_MASK_HI0Q_HOST_IDX_8822B) - - +#define BIT_HI0Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI0Q_HOST_IDX_8822B) << BIT_SHIFT_HI0Q_HOST_IDX_8822B) +#define BITS_HI0Q_HOST_IDX_8822B \ + (BIT_MASK_HI0Q_HOST_IDX_8822B << BIT_SHIFT_HI0Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI0Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI0Q_HOST_IDX_8822B)) +#define BIT_GET_HI0Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822B) & BIT_MASK_HI0Q_HOST_IDX_8822B) +#define BIT_SET_HI0Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI0Q_HOST_IDX_8822B(x) | BIT_HI0Q_HOST_IDX_8822B(v)) /* 2 REG_HI1Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI1Q_HW_IDX_8822B 16 #define BIT_MASK_HI1Q_HW_IDX_8822B 0xfff -#define BIT_HI1Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8822B) << BIT_SHIFT_HI1Q_HW_IDX_8822B) -#define BIT_GET_HI1Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822B) & BIT_MASK_HI1Q_HW_IDX_8822B) - - +#define BIT_HI1Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI1Q_HW_IDX_8822B) << BIT_SHIFT_HI1Q_HW_IDX_8822B) +#define BITS_HI1Q_HW_IDX_8822B \ + (BIT_MASK_HI1Q_HW_IDX_8822B << BIT_SHIFT_HI1Q_HW_IDX_8822B) +#define BIT_CLEAR_HI1Q_HW_IDX_8822B(x) ((x) & (~BITS_HI1Q_HW_IDX_8822B)) +#define BIT_GET_HI1Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822B) & BIT_MASK_HI1Q_HW_IDX_8822B) +#define BIT_SET_HI1Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI1Q_HW_IDX_8822B(x) | BIT_HI1Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI1Q_HOST_IDX_8822B 0 #define BIT_MASK_HI1Q_HOST_IDX_8822B 0xfff -#define BIT_HI1Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8822B) << BIT_SHIFT_HI1Q_HOST_IDX_8822B) -#define BIT_GET_HI1Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822B) & BIT_MASK_HI1Q_HOST_IDX_8822B) - - +#define BIT_HI1Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI1Q_HOST_IDX_8822B) << BIT_SHIFT_HI1Q_HOST_IDX_8822B) +#define BITS_HI1Q_HOST_IDX_8822B \ + (BIT_MASK_HI1Q_HOST_IDX_8822B << BIT_SHIFT_HI1Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI1Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI1Q_HOST_IDX_8822B)) +#define BIT_GET_HI1Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822B) & BIT_MASK_HI1Q_HOST_IDX_8822B) +#define BIT_SET_HI1Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI1Q_HOST_IDX_8822B(x) | BIT_HI1Q_HOST_IDX_8822B(v)) /* 2 REG_HI2Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI2Q_HW_IDX_8822B 16 #define BIT_MASK_HI2Q_HW_IDX_8822B 0xfff -#define BIT_HI2Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8822B) << BIT_SHIFT_HI2Q_HW_IDX_8822B) -#define BIT_GET_HI2Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822B) & BIT_MASK_HI2Q_HW_IDX_8822B) - - +#define BIT_HI2Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI2Q_HW_IDX_8822B) << BIT_SHIFT_HI2Q_HW_IDX_8822B) +#define BITS_HI2Q_HW_IDX_8822B \ + (BIT_MASK_HI2Q_HW_IDX_8822B << BIT_SHIFT_HI2Q_HW_IDX_8822B) +#define BIT_CLEAR_HI2Q_HW_IDX_8822B(x) ((x) & (~BITS_HI2Q_HW_IDX_8822B)) +#define BIT_GET_HI2Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822B) & BIT_MASK_HI2Q_HW_IDX_8822B) +#define BIT_SET_HI2Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI2Q_HW_IDX_8822B(x) | BIT_HI2Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI2Q_HOST_IDX_8822B 0 #define BIT_MASK_HI2Q_HOST_IDX_8822B 0xfff -#define BIT_HI2Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8822B) << BIT_SHIFT_HI2Q_HOST_IDX_8822B) -#define BIT_GET_HI2Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822B) & BIT_MASK_HI2Q_HOST_IDX_8822B) - - +#define BIT_HI2Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI2Q_HOST_IDX_8822B) << BIT_SHIFT_HI2Q_HOST_IDX_8822B) +#define BITS_HI2Q_HOST_IDX_8822B \ + (BIT_MASK_HI2Q_HOST_IDX_8822B << BIT_SHIFT_HI2Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI2Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI2Q_HOST_IDX_8822B)) +#define BIT_GET_HI2Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822B) & BIT_MASK_HI2Q_HOST_IDX_8822B) +#define BIT_SET_HI2Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI2Q_HOST_IDX_8822B(x) | BIT_HI2Q_HOST_IDX_8822B(v)) /* 2 REG_HI3Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI3Q_HW_IDX_8822B 16 #define BIT_MASK_HI3Q_HW_IDX_8822B 0xfff -#define BIT_HI3Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8822B) << BIT_SHIFT_HI3Q_HW_IDX_8822B) -#define BIT_GET_HI3Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822B) & BIT_MASK_HI3Q_HW_IDX_8822B) - - +#define BIT_HI3Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI3Q_HW_IDX_8822B) << BIT_SHIFT_HI3Q_HW_IDX_8822B) +#define BITS_HI3Q_HW_IDX_8822B \ + (BIT_MASK_HI3Q_HW_IDX_8822B << BIT_SHIFT_HI3Q_HW_IDX_8822B) +#define BIT_CLEAR_HI3Q_HW_IDX_8822B(x) ((x) & (~BITS_HI3Q_HW_IDX_8822B)) +#define BIT_GET_HI3Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822B) & BIT_MASK_HI3Q_HW_IDX_8822B) +#define BIT_SET_HI3Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI3Q_HW_IDX_8822B(x) | BIT_HI3Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI3Q_HOST_IDX_8822B 0 #define BIT_MASK_HI3Q_HOST_IDX_8822B 0xfff -#define BIT_HI3Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8822B) << BIT_SHIFT_HI3Q_HOST_IDX_8822B) -#define BIT_GET_HI3Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822B) & BIT_MASK_HI3Q_HOST_IDX_8822B) - - +#define BIT_HI3Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI3Q_HOST_IDX_8822B) << BIT_SHIFT_HI3Q_HOST_IDX_8822B) +#define BITS_HI3Q_HOST_IDX_8822B \ + (BIT_MASK_HI3Q_HOST_IDX_8822B << BIT_SHIFT_HI3Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI3Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI3Q_HOST_IDX_8822B)) +#define BIT_GET_HI3Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822B) & BIT_MASK_HI3Q_HOST_IDX_8822B) +#define BIT_SET_HI3Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI3Q_HOST_IDX_8822B(x) | BIT_HI3Q_HOST_IDX_8822B(v)) /* 2 REG_HI4Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI4Q_HW_IDX_8822B 16 #define BIT_MASK_HI4Q_HW_IDX_8822B 0xfff -#define BIT_HI4Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8822B) << BIT_SHIFT_HI4Q_HW_IDX_8822B) -#define BIT_GET_HI4Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822B) & BIT_MASK_HI4Q_HW_IDX_8822B) - - +#define BIT_HI4Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI4Q_HW_IDX_8822B) << BIT_SHIFT_HI4Q_HW_IDX_8822B) +#define BITS_HI4Q_HW_IDX_8822B \ + (BIT_MASK_HI4Q_HW_IDX_8822B << BIT_SHIFT_HI4Q_HW_IDX_8822B) +#define BIT_CLEAR_HI4Q_HW_IDX_8822B(x) ((x) & (~BITS_HI4Q_HW_IDX_8822B)) +#define BIT_GET_HI4Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822B) & BIT_MASK_HI4Q_HW_IDX_8822B) +#define BIT_SET_HI4Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI4Q_HW_IDX_8822B(x) | BIT_HI4Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI4Q_HOST_IDX_8822B 0 #define BIT_MASK_HI4Q_HOST_IDX_8822B 0xfff -#define BIT_HI4Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8822B) << BIT_SHIFT_HI4Q_HOST_IDX_8822B) -#define BIT_GET_HI4Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822B) & BIT_MASK_HI4Q_HOST_IDX_8822B) - - +#define BIT_HI4Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI4Q_HOST_IDX_8822B) << BIT_SHIFT_HI4Q_HOST_IDX_8822B) +#define BITS_HI4Q_HOST_IDX_8822B \ + (BIT_MASK_HI4Q_HOST_IDX_8822B << BIT_SHIFT_HI4Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI4Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI4Q_HOST_IDX_8822B)) +#define BIT_GET_HI4Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822B) & BIT_MASK_HI4Q_HOST_IDX_8822B) +#define BIT_SET_HI4Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI4Q_HOST_IDX_8822B(x) | BIT_HI4Q_HOST_IDX_8822B(v)) /* 2 REG_HI5Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI5Q_HW_IDX_8822B 16 #define BIT_MASK_HI5Q_HW_IDX_8822B 0xfff -#define BIT_HI5Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8822B) << BIT_SHIFT_HI5Q_HW_IDX_8822B) -#define BIT_GET_HI5Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822B) & BIT_MASK_HI5Q_HW_IDX_8822B) - - +#define BIT_HI5Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI5Q_HW_IDX_8822B) << BIT_SHIFT_HI5Q_HW_IDX_8822B) +#define BITS_HI5Q_HW_IDX_8822B \ + (BIT_MASK_HI5Q_HW_IDX_8822B << BIT_SHIFT_HI5Q_HW_IDX_8822B) +#define BIT_CLEAR_HI5Q_HW_IDX_8822B(x) ((x) & (~BITS_HI5Q_HW_IDX_8822B)) +#define BIT_GET_HI5Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822B) & BIT_MASK_HI5Q_HW_IDX_8822B) +#define BIT_SET_HI5Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI5Q_HW_IDX_8822B(x) | BIT_HI5Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI5Q_HOST_IDX_8822B 0 #define BIT_MASK_HI5Q_HOST_IDX_8822B 0xfff -#define BIT_HI5Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8822B) << BIT_SHIFT_HI5Q_HOST_IDX_8822B) -#define BIT_GET_HI5Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822B) & BIT_MASK_HI5Q_HOST_IDX_8822B) - - +#define BIT_HI5Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI5Q_HOST_IDX_8822B) << BIT_SHIFT_HI5Q_HOST_IDX_8822B) +#define BITS_HI5Q_HOST_IDX_8822B \ + (BIT_MASK_HI5Q_HOST_IDX_8822B << BIT_SHIFT_HI5Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI5Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI5Q_HOST_IDX_8822B)) +#define BIT_GET_HI5Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822B) & BIT_MASK_HI5Q_HOST_IDX_8822B) +#define BIT_SET_HI5Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI5Q_HOST_IDX_8822B(x) | BIT_HI5Q_HOST_IDX_8822B(v)) /* 2 REG_HI6Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI6Q_HW_IDX_8822B 16 #define BIT_MASK_HI6Q_HW_IDX_8822B 0xfff -#define BIT_HI6Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8822B) << BIT_SHIFT_HI6Q_HW_IDX_8822B) -#define BIT_GET_HI6Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822B) & BIT_MASK_HI6Q_HW_IDX_8822B) - - +#define BIT_HI6Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI6Q_HW_IDX_8822B) << BIT_SHIFT_HI6Q_HW_IDX_8822B) +#define BITS_HI6Q_HW_IDX_8822B \ + (BIT_MASK_HI6Q_HW_IDX_8822B << BIT_SHIFT_HI6Q_HW_IDX_8822B) +#define BIT_CLEAR_HI6Q_HW_IDX_8822B(x) ((x) & (~BITS_HI6Q_HW_IDX_8822B)) +#define BIT_GET_HI6Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822B) & BIT_MASK_HI6Q_HW_IDX_8822B) +#define BIT_SET_HI6Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI6Q_HW_IDX_8822B(x) | BIT_HI6Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI6Q_HOST_IDX_8822B 0 #define BIT_MASK_HI6Q_HOST_IDX_8822B 0xfff -#define BIT_HI6Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8822B) << BIT_SHIFT_HI6Q_HOST_IDX_8822B) -#define BIT_GET_HI6Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822B) & BIT_MASK_HI6Q_HOST_IDX_8822B) - - +#define BIT_HI6Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI6Q_HOST_IDX_8822B) << BIT_SHIFT_HI6Q_HOST_IDX_8822B) +#define BITS_HI6Q_HOST_IDX_8822B \ + (BIT_MASK_HI6Q_HOST_IDX_8822B << BIT_SHIFT_HI6Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI6Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI6Q_HOST_IDX_8822B)) +#define BIT_GET_HI6Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822B) & BIT_MASK_HI6Q_HOST_IDX_8822B) +#define BIT_SET_HI6Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI6Q_HOST_IDX_8822B(x) | BIT_HI6Q_HOST_IDX_8822B(v)) /* 2 REG_HI7Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI7Q_HW_IDX_8822B 16 #define BIT_MASK_HI7Q_HW_IDX_8822B 0xfff -#define BIT_HI7Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8822B) << BIT_SHIFT_HI7Q_HW_IDX_8822B) -#define BIT_GET_HI7Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822B) & BIT_MASK_HI7Q_HW_IDX_8822B) - - +#define BIT_HI7Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI7Q_HW_IDX_8822B) << BIT_SHIFT_HI7Q_HW_IDX_8822B) +#define BITS_HI7Q_HW_IDX_8822B \ + (BIT_MASK_HI7Q_HW_IDX_8822B << BIT_SHIFT_HI7Q_HW_IDX_8822B) +#define BIT_CLEAR_HI7Q_HW_IDX_8822B(x) ((x) & (~BITS_HI7Q_HW_IDX_8822B)) +#define BIT_GET_HI7Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822B) & BIT_MASK_HI7Q_HW_IDX_8822B) +#define BIT_SET_HI7Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI7Q_HW_IDX_8822B(x) | BIT_HI7Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI7Q_HOST_IDX_8822B 0 #define BIT_MASK_HI7Q_HOST_IDX_8822B 0xfff -#define BIT_HI7Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8822B) << BIT_SHIFT_HI7Q_HOST_IDX_8822B) -#define BIT_GET_HI7Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822B) & BIT_MASK_HI7Q_HOST_IDX_8822B) - - +#define BIT_HI7Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI7Q_HOST_IDX_8822B) << BIT_SHIFT_HI7Q_HOST_IDX_8822B) +#define BITS_HI7Q_HOST_IDX_8822B \ + (BIT_MASK_HI7Q_HOST_IDX_8822B << BIT_SHIFT_HI7Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI7Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI7Q_HOST_IDX_8822B)) +#define BIT_GET_HI7Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822B) & BIT_MASK_HI7Q_HOST_IDX_8822B) +#define BIT_SET_HI7Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI7Q_HOST_IDX_8822B(x) | BIT_HI7Q_HOST_IDX_8822B(v)) /* 2 REG_DBG_SEL_V1_8822B */ #define BIT_SHIFT_DBG_SEL_8822B 0 #define BIT_MASK_DBG_SEL_8822B 0xff -#define BIT_DBG_SEL_8822B(x) (((x) & BIT_MASK_DBG_SEL_8822B) << BIT_SHIFT_DBG_SEL_8822B) -#define BIT_GET_DBG_SEL_8822B(x) (((x) >> BIT_SHIFT_DBG_SEL_8822B) & BIT_MASK_DBG_SEL_8822B) - - +#define BIT_DBG_SEL_8822B(x) \ + (((x) & BIT_MASK_DBG_SEL_8822B) << BIT_SHIFT_DBG_SEL_8822B) +#define BITS_DBG_SEL_8822B (BIT_MASK_DBG_SEL_8822B << BIT_SHIFT_DBG_SEL_8822B) +#define BIT_CLEAR_DBG_SEL_8822B(x) ((x) & (~BITS_DBG_SEL_8822B)) +#define BIT_GET_DBG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_8822B) & BIT_MASK_DBG_SEL_8822B) +#define BIT_SET_DBG_SEL_8822B(x, v) \ + (BIT_CLEAR_DBG_SEL_8822B(x) | BIT_DBG_SEL_8822B(v)) /* 2 REG_PCIE_HRPWM1_V1_8822B */ #define BIT_SHIFT_PCIE_HRPWM_8822B 0 #define BIT_MASK_PCIE_HRPWM_8822B 0xff -#define BIT_PCIE_HRPWM_8822B(x) (((x) & BIT_MASK_PCIE_HRPWM_8822B) << BIT_SHIFT_PCIE_HRPWM_8822B) -#define BIT_GET_PCIE_HRPWM_8822B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM_8822B) & BIT_MASK_PCIE_HRPWM_8822B) - - +#define BIT_PCIE_HRPWM_8822B(x) \ + (((x) & BIT_MASK_PCIE_HRPWM_8822B) << BIT_SHIFT_PCIE_HRPWM_8822B) +#define BITS_PCIE_HRPWM_8822B \ + (BIT_MASK_PCIE_HRPWM_8822B << BIT_SHIFT_PCIE_HRPWM_8822B) +#define BIT_CLEAR_PCIE_HRPWM_8822B(x) ((x) & (~BITS_PCIE_HRPWM_8822B)) +#define BIT_GET_PCIE_HRPWM_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM_8822B) & BIT_MASK_PCIE_HRPWM_8822B) +#define BIT_SET_PCIE_HRPWM_8822B(x, v) \ + (BIT_CLEAR_PCIE_HRPWM_8822B(x) | BIT_PCIE_HRPWM_8822B(v)) /* 2 REG_PCIE_HCPWM1_V1_8822B */ #define BIT_SHIFT_PCIE_HCPWM_8822B 0 #define BIT_MASK_PCIE_HCPWM_8822B 0xff -#define BIT_PCIE_HCPWM_8822B(x) (((x) & BIT_MASK_PCIE_HCPWM_8822B) << BIT_SHIFT_PCIE_HCPWM_8822B) -#define BIT_GET_PCIE_HCPWM_8822B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM_8822B) & BIT_MASK_PCIE_HCPWM_8822B) - - +#define BIT_PCIE_HCPWM_8822B(x) \ + (((x) & BIT_MASK_PCIE_HCPWM_8822B) << BIT_SHIFT_PCIE_HCPWM_8822B) +#define BITS_PCIE_HCPWM_8822B \ + (BIT_MASK_PCIE_HCPWM_8822B << BIT_SHIFT_PCIE_HCPWM_8822B) +#define BIT_CLEAR_PCIE_HCPWM_8822B(x) ((x) & (~BITS_PCIE_HCPWM_8822B)) +#define BIT_GET_PCIE_HCPWM_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM_8822B) & BIT_MASK_PCIE_HCPWM_8822B) +#define BIT_SET_PCIE_HCPWM_8822B(x, v) \ + (BIT_CLEAR_PCIE_HCPWM_8822B(x) | BIT_PCIE_HCPWM_8822B(v)) /* 2 REG_PCIE_CTRL2_8822B */ #define BIT_DIS_TXDMA_PRE_8822B BIT(7) @@ -4899,9 +7271,15 @@ #define BIT_SHIFT_HPS_CLKR_PCIE_8822B 4 #define BIT_MASK_HPS_CLKR_PCIE_8822B 0x3 -#define BIT_HPS_CLKR_PCIE_8822B(x) (((x) & BIT_MASK_HPS_CLKR_PCIE_8822B) << BIT_SHIFT_HPS_CLKR_PCIE_8822B) -#define BIT_GET_HPS_CLKR_PCIE_8822B(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822B) & BIT_MASK_HPS_CLKR_PCIE_8822B) - +#define BIT_HPS_CLKR_PCIE_8822B(x) \ + (((x) & BIT_MASK_HPS_CLKR_PCIE_8822B) << BIT_SHIFT_HPS_CLKR_PCIE_8822B) +#define BITS_HPS_CLKR_PCIE_8822B \ + (BIT_MASK_HPS_CLKR_PCIE_8822B << BIT_SHIFT_HPS_CLKR_PCIE_8822B) +#define BIT_CLEAR_HPS_CLKR_PCIE_8822B(x) ((x) & (~BITS_HPS_CLKR_PCIE_8822B)) +#define BIT_GET_HPS_CLKR_PCIE_8822B(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822B) & BIT_MASK_HPS_CLKR_PCIE_8822B) +#define BIT_SET_HPS_CLKR_PCIE_8822B(x, v) \ + (BIT_CLEAR_HPS_CLKR_PCIE_8822B(x) | BIT_HPS_CLKR_PCIE_8822B(v)) #define BIT_PCIE_INT_8822B BIT(3) #define BIT_TXFLAG_EXIT_L1_EN_8822B BIT(2) @@ -4912,55 +7290,88 @@ #define BIT_SHIFT_PCIE_HRPWM2_8822B 0 #define BIT_MASK_PCIE_HRPWM2_8822B 0xffff -#define BIT_PCIE_HRPWM2_8822B(x) (((x) & BIT_MASK_PCIE_HRPWM2_8822B) << BIT_SHIFT_PCIE_HRPWM2_8822B) -#define BIT_GET_PCIE_HRPWM2_8822B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2_8822B) & BIT_MASK_PCIE_HRPWM2_8822B) - - +#define BIT_PCIE_HRPWM2_8822B(x) \ + (((x) & BIT_MASK_PCIE_HRPWM2_8822B) << BIT_SHIFT_PCIE_HRPWM2_8822B) +#define BITS_PCIE_HRPWM2_8822B \ + (BIT_MASK_PCIE_HRPWM2_8822B << BIT_SHIFT_PCIE_HRPWM2_8822B) +#define BIT_CLEAR_PCIE_HRPWM2_8822B(x) ((x) & (~BITS_PCIE_HRPWM2_8822B)) +#define BIT_GET_PCIE_HRPWM2_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM2_8822B) & BIT_MASK_PCIE_HRPWM2_8822B) +#define BIT_SET_PCIE_HRPWM2_8822B(x, v) \ + (BIT_CLEAR_PCIE_HRPWM2_8822B(x) | BIT_PCIE_HRPWM2_8822B(v)) /* 2 REG_PCIE_HCPWM2_V1_8822B */ #define BIT_SHIFT_PCIE_HCPWM2_8822B 0 #define BIT_MASK_PCIE_HCPWM2_8822B 0xffff -#define BIT_PCIE_HCPWM2_8822B(x) (((x) & BIT_MASK_PCIE_HCPWM2_8822B) << BIT_SHIFT_PCIE_HCPWM2_8822B) -#define BIT_GET_PCIE_HCPWM2_8822B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2_8822B) & BIT_MASK_PCIE_HCPWM2_8822B) - - +#define BIT_PCIE_HCPWM2_8822B(x) \ + (((x) & BIT_MASK_PCIE_HCPWM2_8822B) << BIT_SHIFT_PCIE_HCPWM2_8822B) +#define BITS_PCIE_HCPWM2_8822B \ + (BIT_MASK_PCIE_HCPWM2_8822B << BIT_SHIFT_PCIE_HCPWM2_8822B) +#define BIT_CLEAR_PCIE_HCPWM2_8822B(x) ((x) & (~BITS_PCIE_HCPWM2_8822B)) +#define BIT_GET_PCIE_HCPWM2_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM2_8822B) & BIT_MASK_PCIE_HCPWM2_8822B) +#define BIT_SET_PCIE_HCPWM2_8822B(x, v) \ + (BIT_CLEAR_PCIE_HCPWM2_8822B(x) | BIT_PCIE_HCPWM2_8822B(v)) /* 2 REG_PCIE_H2C_MSG_V1_8822B */ #define BIT_SHIFT_DRV2FW_INFO_8822B 0 #define BIT_MASK_DRV2FW_INFO_8822B 0xffffffffL -#define BIT_DRV2FW_INFO_8822B(x) (((x) & BIT_MASK_DRV2FW_INFO_8822B) << BIT_SHIFT_DRV2FW_INFO_8822B) -#define BIT_GET_DRV2FW_INFO_8822B(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8822B) & BIT_MASK_DRV2FW_INFO_8822B) - - +#define BIT_DRV2FW_INFO_8822B(x) \ + (((x) & BIT_MASK_DRV2FW_INFO_8822B) << BIT_SHIFT_DRV2FW_INFO_8822B) +#define BITS_DRV2FW_INFO_8822B \ + (BIT_MASK_DRV2FW_INFO_8822B << BIT_SHIFT_DRV2FW_INFO_8822B) +#define BIT_CLEAR_DRV2FW_INFO_8822B(x) ((x) & (~BITS_DRV2FW_INFO_8822B)) +#define BIT_GET_DRV2FW_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_DRV2FW_INFO_8822B) & BIT_MASK_DRV2FW_INFO_8822B) +#define BIT_SET_DRV2FW_INFO_8822B(x, v) \ + (BIT_CLEAR_DRV2FW_INFO_8822B(x) | BIT_DRV2FW_INFO_8822B(v)) /* 2 REG_PCIE_C2H_MSG_V1_8822B */ #define BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B 0 #define BIT_MASK_HCI_PCIE_C2H_MSG_8822B 0xffffffffL -#define BIT_HCI_PCIE_C2H_MSG_8822B(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B) << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) -#define BIT_GET_HCI_PCIE_C2H_MSG_8822B(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B) - - +#define BIT_HCI_PCIE_C2H_MSG_8822B(x) \ + (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B) \ + << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) +#define BITS_HCI_PCIE_C2H_MSG_8822B \ + (BIT_MASK_HCI_PCIE_C2H_MSG_8822B << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) +#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8822B(x) \ + ((x) & (~BITS_HCI_PCIE_C2H_MSG_8822B)) +#define BIT_GET_HCI_PCIE_C2H_MSG_8822B(x) \ + (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) & \ + BIT_MASK_HCI_PCIE_C2H_MSG_8822B) +#define BIT_SET_HCI_PCIE_C2H_MSG_8822B(x, v) \ + (BIT_CLEAR_HCI_PCIE_C2H_MSG_8822B(x) | BIT_HCI_PCIE_C2H_MSG_8822B(v)) /* 2 REG_DBI_WDATA_V1_8822B */ #define BIT_SHIFT_DBI_WDATA_8822B 0 #define BIT_MASK_DBI_WDATA_8822B 0xffffffffL -#define BIT_DBI_WDATA_8822B(x) (((x) & BIT_MASK_DBI_WDATA_8822B) << BIT_SHIFT_DBI_WDATA_8822B) -#define BIT_GET_DBI_WDATA_8822B(x) (((x) >> BIT_SHIFT_DBI_WDATA_8822B) & BIT_MASK_DBI_WDATA_8822B) - - +#define BIT_DBI_WDATA_8822B(x) \ + (((x) & BIT_MASK_DBI_WDATA_8822B) << BIT_SHIFT_DBI_WDATA_8822B) +#define BITS_DBI_WDATA_8822B \ + (BIT_MASK_DBI_WDATA_8822B << BIT_SHIFT_DBI_WDATA_8822B) +#define BIT_CLEAR_DBI_WDATA_8822B(x) ((x) & (~BITS_DBI_WDATA_8822B)) +#define BIT_GET_DBI_WDATA_8822B(x) \ + (((x) >> BIT_SHIFT_DBI_WDATA_8822B) & BIT_MASK_DBI_WDATA_8822B) +#define BIT_SET_DBI_WDATA_8822B(x, v) \ + (BIT_CLEAR_DBI_WDATA_8822B(x) | BIT_DBI_WDATA_8822B(v)) /* 2 REG_DBI_RDATA_V1_8822B */ #define BIT_SHIFT_DBI_RDATA_8822B 0 #define BIT_MASK_DBI_RDATA_8822B 0xffffffffL -#define BIT_DBI_RDATA_8822B(x) (((x) & BIT_MASK_DBI_RDATA_8822B) << BIT_SHIFT_DBI_RDATA_8822B) -#define BIT_GET_DBI_RDATA_8822B(x) (((x) >> BIT_SHIFT_DBI_RDATA_8822B) & BIT_MASK_DBI_RDATA_8822B) - - +#define BIT_DBI_RDATA_8822B(x) \ + (((x) & BIT_MASK_DBI_RDATA_8822B) << BIT_SHIFT_DBI_RDATA_8822B) +#define BITS_DBI_RDATA_8822B \ + (BIT_MASK_DBI_RDATA_8822B << BIT_SHIFT_DBI_RDATA_8822B) +#define BIT_CLEAR_DBI_RDATA_8822B(x) ((x) & (~BITS_DBI_RDATA_8822B)) +#define BIT_GET_DBI_RDATA_8822B(x) \ + (((x) >> BIT_SHIFT_DBI_RDATA_8822B) & BIT_MASK_DBI_RDATA_8822B) +#define BIT_SET_DBI_RDATA_8822B(x, v) \ + (BIT_CLEAR_DBI_RDATA_8822B(x) | BIT_DBI_RDATA_8822B(v)) /* 2 REG_DBI_FLAG_V1_8822B */ #define BIT_EN_STUCK_DBG_8822B BIT(26) @@ -4971,48 +7382,84 @@ #define BIT_SHIFT_DBI_WREN_8822B 12 #define BIT_MASK_DBI_WREN_8822B 0xf -#define BIT_DBI_WREN_8822B(x) (((x) & BIT_MASK_DBI_WREN_8822B) << BIT_SHIFT_DBI_WREN_8822B) -#define BIT_GET_DBI_WREN_8822B(x) (((x) >> BIT_SHIFT_DBI_WREN_8822B) & BIT_MASK_DBI_WREN_8822B) - - +#define BIT_DBI_WREN_8822B(x) \ + (((x) & BIT_MASK_DBI_WREN_8822B) << BIT_SHIFT_DBI_WREN_8822B) +#define BITS_DBI_WREN_8822B \ + (BIT_MASK_DBI_WREN_8822B << BIT_SHIFT_DBI_WREN_8822B) +#define BIT_CLEAR_DBI_WREN_8822B(x) ((x) & (~BITS_DBI_WREN_8822B)) +#define BIT_GET_DBI_WREN_8822B(x) \ + (((x) >> BIT_SHIFT_DBI_WREN_8822B) & BIT_MASK_DBI_WREN_8822B) +#define BIT_SET_DBI_WREN_8822B(x, v) \ + (BIT_CLEAR_DBI_WREN_8822B(x) | BIT_DBI_WREN_8822B(v)) #define BIT_SHIFT_DBI_ADDR_8822B 0 #define BIT_MASK_DBI_ADDR_8822B 0xfff -#define BIT_DBI_ADDR_8822B(x) (((x) & BIT_MASK_DBI_ADDR_8822B) << BIT_SHIFT_DBI_ADDR_8822B) -#define BIT_GET_DBI_ADDR_8822B(x) (((x) >> BIT_SHIFT_DBI_ADDR_8822B) & BIT_MASK_DBI_ADDR_8822B) +#define BIT_DBI_ADDR_8822B(x) \ + (((x) & BIT_MASK_DBI_ADDR_8822B) << BIT_SHIFT_DBI_ADDR_8822B) +#define BITS_DBI_ADDR_8822B \ + (BIT_MASK_DBI_ADDR_8822B << BIT_SHIFT_DBI_ADDR_8822B) +#define BIT_CLEAR_DBI_ADDR_8822B(x) ((x) & (~BITS_DBI_ADDR_8822B)) +#define BIT_GET_DBI_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_DBI_ADDR_8822B) & BIT_MASK_DBI_ADDR_8822B) +#define BIT_SET_DBI_ADDR_8822B(x, v) \ + (BIT_CLEAR_DBI_ADDR_8822B(x) | BIT_DBI_ADDR_8822B(v)) - - -/* 2 REG_MDIO_V1_8822B */ +/* 2 REG_MDIO_V1_8822B */ #define BIT_SHIFT_MDIO_RDATA_8822B 16 #define BIT_MASK_MDIO_RDATA_8822B 0xffff -#define BIT_MDIO_RDATA_8822B(x) (((x) & BIT_MASK_MDIO_RDATA_8822B) << BIT_SHIFT_MDIO_RDATA_8822B) -#define BIT_GET_MDIO_RDATA_8822B(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8822B) & BIT_MASK_MDIO_RDATA_8822B) - - +#define BIT_MDIO_RDATA_8822B(x) \ + (((x) & BIT_MASK_MDIO_RDATA_8822B) << BIT_SHIFT_MDIO_RDATA_8822B) +#define BITS_MDIO_RDATA_8822B \ + (BIT_MASK_MDIO_RDATA_8822B << BIT_SHIFT_MDIO_RDATA_8822B) +#define BIT_CLEAR_MDIO_RDATA_8822B(x) ((x) & (~BITS_MDIO_RDATA_8822B)) +#define BIT_GET_MDIO_RDATA_8822B(x) \ + (((x) >> BIT_SHIFT_MDIO_RDATA_8822B) & BIT_MASK_MDIO_RDATA_8822B) +#define BIT_SET_MDIO_RDATA_8822B(x, v) \ + (BIT_CLEAR_MDIO_RDATA_8822B(x) | BIT_MDIO_RDATA_8822B(v)) #define BIT_SHIFT_MDIO_WDATA_8822B 0 #define BIT_MASK_MDIO_WDATA_8822B 0xffff -#define BIT_MDIO_WDATA_8822B(x) (((x) & BIT_MASK_MDIO_WDATA_8822B) << BIT_SHIFT_MDIO_WDATA_8822B) -#define BIT_GET_MDIO_WDATA_8822B(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8822B) & BIT_MASK_MDIO_WDATA_8822B) - - +#define BIT_MDIO_WDATA_8822B(x) \ + (((x) & BIT_MASK_MDIO_WDATA_8822B) << BIT_SHIFT_MDIO_WDATA_8822B) +#define BITS_MDIO_WDATA_8822B \ + (BIT_MASK_MDIO_WDATA_8822B << BIT_SHIFT_MDIO_WDATA_8822B) +#define BIT_CLEAR_MDIO_WDATA_8822B(x) ((x) & (~BITS_MDIO_WDATA_8822B)) +#define BIT_GET_MDIO_WDATA_8822B(x) \ + (((x) >> BIT_SHIFT_MDIO_WDATA_8822B) & BIT_MASK_MDIO_WDATA_8822B) +#define BIT_SET_MDIO_WDATA_8822B(x, v) \ + (BIT_CLEAR_MDIO_WDATA_8822B(x) | BIT_MDIO_WDATA_8822B(v)) /* 2 REG_PCIE_MIX_CFG_8822B */ #define BIT_SHIFT_MDIO_PHY_ADDR_8822B 24 #define BIT_MASK_MDIO_PHY_ADDR_8822B 0x1f -#define BIT_MDIO_PHY_ADDR_8822B(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8822B) << BIT_SHIFT_MDIO_PHY_ADDR_8822B) -#define BIT_GET_MDIO_PHY_ADDR_8822B(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822B) & BIT_MASK_MDIO_PHY_ADDR_8822B) - - +#define BIT_MDIO_PHY_ADDR_8822B(x) \ + (((x) & BIT_MASK_MDIO_PHY_ADDR_8822B) << BIT_SHIFT_MDIO_PHY_ADDR_8822B) +#define BITS_MDIO_PHY_ADDR_8822B \ + (BIT_MASK_MDIO_PHY_ADDR_8822B << BIT_SHIFT_MDIO_PHY_ADDR_8822B) +#define BIT_CLEAR_MDIO_PHY_ADDR_8822B(x) ((x) & (~BITS_MDIO_PHY_ADDR_8822B)) +#define BIT_GET_MDIO_PHY_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822B) & BIT_MASK_MDIO_PHY_ADDR_8822B) +#define BIT_SET_MDIO_PHY_ADDR_8822B(x, v) \ + (BIT_CLEAR_MDIO_PHY_ADDR_8822B(x) | BIT_MDIO_PHY_ADDR_8822B(v)) #define BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B 10 #define BIT_MASK_WATCH_DOG_RECORD_V1_8822B 0x3fff -#define BIT_WATCH_DOG_RECORD_V1_8822B(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) -#define BIT_GET_WATCH_DOG_RECORD_V1_8822B(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B) - +#define BIT_WATCH_DOG_RECORD_V1_8822B(x) \ + (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B) \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) +#define BITS_WATCH_DOG_RECORD_V1_8822B \ + (BIT_MASK_WATCH_DOG_RECORD_V1_8822B \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8822B(x) \ + ((x) & (~BITS_WATCH_DOG_RECORD_V1_8822B)) +#define BIT_GET_WATCH_DOG_RECORD_V1_8822B(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) & \ + BIT_MASK_WATCH_DOG_RECORD_V1_8822B) +#define BIT_SET_WATCH_DOG_RECORD_V1_8822B(x, v) \ + (BIT_CLEAR_WATCH_DOG_RECORD_V1_8822B(x) | \ + BIT_WATCH_DOG_RECORD_V1_8822B(v)) #define BIT_R_IO_TIMEOUT_FLAG_V1_8822B BIT(9) #define BIT_EN_WATCH_DOG_8822B BIT(8) @@ -5022,34 +7469,66 @@ #define BIT_SHIFT_MDIO_REG_ADDR_V1_8822B 0 #define BIT_MASK_MDIO_REG_ADDR_V1_8822B 0x1f -#define BIT_MDIO_REG_ADDR_V1_8822B(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822B) << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) -#define BIT_GET_MDIO_REG_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) & BIT_MASK_MDIO_REG_ADDR_V1_8822B) - - +#define BIT_MDIO_REG_ADDR_V1_8822B(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822B) \ + << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) +#define BITS_MDIO_REG_ADDR_V1_8822B \ + (BIT_MASK_MDIO_REG_ADDR_V1_8822B << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) +#define BIT_CLEAR_MDIO_REG_ADDR_V1_8822B(x) \ + ((x) & (~BITS_MDIO_REG_ADDR_V1_8822B)) +#define BIT_GET_MDIO_REG_ADDR_V1_8822B(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) & \ + BIT_MASK_MDIO_REG_ADDR_V1_8822B) +#define BIT_SET_MDIO_REG_ADDR_V1_8822B(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR_V1_8822B(x) | BIT_MDIO_REG_ADDR_V1_8822B(v)) /* 2 REG_HCI_MIX_CFG_8822B */ #define BIT_HOST_GEN2_SUPPORT_8822B BIT(20) #define BIT_SHIFT_TXDMA_ERR_FLAG_8822B 16 #define BIT_MASK_TXDMA_ERR_FLAG_8822B 0xf -#define BIT_TXDMA_ERR_FLAG_8822B(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8822B) << BIT_SHIFT_TXDMA_ERR_FLAG_8822B) -#define BIT_GET_TXDMA_ERR_FLAG_8822B(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8822B) & BIT_MASK_TXDMA_ERR_FLAG_8822B) - - +#define BIT_TXDMA_ERR_FLAG_8822B(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG_8822B) \ + << BIT_SHIFT_TXDMA_ERR_FLAG_8822B) +#define BITS_TXDMA_ERR_FLAG_8822B \ + (BIT_MASK_TXDMA_ERR_FLAG_8822B << BIT_SHIFT_TXDMA_ERR_FLAG_8822B) +#define BIT_CLEAR_TXDMA_ERR_FLAG_8822B(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8822B)) +#define BIT_GET_TXDMA_ERR_FLAG_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8822B) & \ + BIT_MASK_TXDMA_ERR_FLAG_8822B) +#define BIT_SET_TXDMA_ERR_FLAG_8822B(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG_8822B(x) | BIT_TXDMA_ERR_FLAG_8822B(v)) #define BIT_SHIFT_EARLY_MODE_SEL_8822B 12 #define BIT_MASK_EARLY_MODE_SEL_8822B 0xf -#define BIT_EARLY_MODE_SEL_8822B(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8822B) << BIT_SHIFT_EARLY_MODE_SEL_8822B) -#define BIT_GET_EARLY_MODE_SEL_8822B(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8822B) & BIT_MASK_EARLY_MODE_SEL_8822B) - +#define BIT_EARLY_MODE_SEL_8822B(x) \ + (((x) & BIT_MASK_EARLY_MODE_SEL_8822B) \ + << BIT_SHIFT_EARLY_MODE_SEL_8822B) +#define BITS_EARLY_MODE_SEL_8822B \ + (BIT_MASK_EARLY_MODE_SEL_8822B << BIT_SHIFT_EARLY_MODE_SEL_8822B) +#define BIT_CLEAR_EARLY_MODE_SEL_8822B(x) ((x) & (~BITS_EARLY_MODE_SEL_8822B)) +#define BIT_GET_EARLY_MODE_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8822B) & \ + BIT_MASK_EARLY_MODE_SEL_8822B) +#define BIT_SET_EARLY_MODE_SEL_8822B(x, v) \ + (BIT_CLEAR_EARLY_MODE_SEL_8822B(x) | BIT_EARLY_MODE_SEL_8822B(v)) #define BIT_EPHY_RX50_EN_8822B BIT(11) #define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B 8 #define BIT_MASK_MSI_TIMEOUT_ID_V1_8822B 0x7 -#define BIT_MSI_TIMEOUT_ID_V1_8822B(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) -#define BIT_GET_MSI_TIMEOUT_ID_V1_8822B(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) - +#define BIT_MSI_TIMEOUT_ID_V1_8822B(x) \ + (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) \ + << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) +#define BITS_MSI_TIMEOUT_ID_V1_8822B \ + (BIT_MASK_MSI_TIMEOUT_ID_V1_8822B << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822B(x) \ + ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8822B)) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8822B(x) \ + (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) & \ + BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) +#define BIT_SET_MSI_TIMEOUT_ID_V1_8822B(x, v) \ + (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822B(x) | BIT_MSI_TIMEOUT_ID_V1_8822B(v)) #define BIT_RADDR_RD_8822B BIT(7) #define BIT_EN_MUL_TAG_8822B BIT(6) @@ -5064,41 +7543,77 @@ #define BIT_SHIFT_STC_INT_FLAG_8822B 16 #define BIT_MASK_STC_INT_FLAG_8822B 0xff -#define BIT_STC_INT_FLAG_8822B(x) (((x) & BIT_MASK_STC_INT_FLAG_8822B) << BIT_SHIFT_STC_INT_FLAG_8822B) -#define BIT_GET_STC_INT_FLAG_8822B(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8822B) & BIT_MASK_STC_INT_FLAG_8822B) - - +#define BIT_STC_INT_FLAG_8822B(x) \ + (((x) & BIT_MASK_STC_INT_FLAG_8822B) << BIT_SHIFT_STC_INT_FLAG_8822B) +#define BITS_STC_INT_FLAG_8822B \ + (BIT_MASK_STC_INT_FLAG_8822B << BIT_SHIFT_STC_INT_FLAG_8822B) +#define BIT_CLEAR_STC_INT_FLAG_8822B(x) ((x) & (~BITS_STC_INT_FLAG_8822B)) +#define BIT_GET_STC_INT_FLAG_8822B(x) \ + (((x) >> BIT_SHIFT_STC_INT_FLAG_8822B) & BIT_MASK_STC_INT_FLAG_8822B) +#define BIT_SET_STC_INT_FLAG_8822B(x, v) \ + (BIT_CLEAR_STC_INT_FLAG_8822B(x) | BIT_STC_INT_FLAG_8822B(v)) #define BIT_SHIFT_STC_INT_IDX_8822B 8 #define BIT_MASK_STC_INT_IDX_8822B 0x7 -#define BIT_STC_INT_IDX_8822B(x) (((x) & BIT_MASK_STC_INT_IDX_8822B) << BIT_SHIFT_STC_INT_IDX_8822B) -#define BIT_GET_STC_INT_IDX_8822B(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8822B) & BIT_MASK_STC_INT_IDX_8822B) - - +#define BIT_STC_INT_IDX_8822B(x) \ + (((x) & BIT_MASK_STC_INT_IDX_8822B) << BIT_SHIFT_STC_INT_IDX_8822B) +#define BITS_STC_INT_IDX_8822B \ + (BIT_MASK_STC_INT_IDX_8822B << BIT_SHIFT_STC_INT_IDX_8822B) +#define BIT_CLEAR_STC_INT_IDX_8822B(x) ((x) & (~BITS_STC_INT_IDX_8822B)) +#define BIT_GET_STC_INT_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_STC_INT_IDX_8822B) & BIT_MASK_STC_INT_IDX_8822B) +#define BIT_SET_STC_INT_IDX_8822B(x, v) \ + (BIT_CLEAR_STC_INT_IDX_8822B(x) | BIT_STC_INT_IDX_8822B(v)) #define BIT_SHIFT_STC_INT_REALTIME_CS_8822B 0 #define BIT_MASK_STC_INT_REALTIME_CS_8822B 0x3f -#define BIT_STC_INT_REALTIME_CS_8822B(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8822B) << BIT_SHIFT_STC_INT_REALTIME_CS_8822B) -#define BIT_GET_STC_INT_REALTIME_CS_8822B(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822B) & BIT_MASK_STC_INT_REALTIME_CS_8822B) - - +#define BIT_STC_INT_REALTIME_CS_8822B(x) \ + (((x) & BIT_MASK_STC_INT_REALTIME_CS_8822B) \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8822B) +#define BITS_STC_INT_REALTIME_CS_8822B \ + (BIT_MASK_STC_INT_REALTIME_CS_8822B \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8822B) +#define BIT_CLEAR_STC_INT_REALTIME_CS_8822B(x) \ + ((x) & (~BITS_STC_INT_REALTIME_CS_8822B)) +#define BIT_GET_STC_INT_REALTIME_CS_8822B(x) \ + (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822B) & \ + BIT_MASK_STC_INT_REALTIME_CS_8822B) +#define BIT_SET_STC_INT_REALTIME_CS_8822B(x, v) \ + (BIT_CLEAR_STC_INT_REALTIME_CS_8822B(x) | \ + BIT_STC_INT_REALTIME_CS_8822B(v)) /* 2 REG_ST_INT_CFG_8822B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */ #define BIT_STC_INT_GRP_EN_8822B BIT(31) #define BIT_SHIFT_STC_INT_EXPECT_LS_8822B 8 #define BIT_MASK_STC_INT_EXPECT_LS_8822B 0x3f -#define BIT_STC_INT_EXPECT_LS_8822B(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8822B) << BIT_SHIFT_STC_INT_EXPECT_LS_8822B) -#define BIT_GET_STC_INT_EXPECT_LS_8822B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822B) & BIT_MASK_STC_INT_EXPECT_LS_8822B) - - +#define BIT_STC_INT_EXPECT_LS_8822B(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_LS_8822B) \ + << BIT_SHIFT_STC_INT_EXPECT_LS_8822B) +#define BITS_STC_INT_EXPECT_LS_8822B \ + (BIT_MASK_STC_INT_EXPECT_LS_8822B << BIT_SHIFT_STC_INT_EXPECT_LS_8822B) +#define BIT_CLEAR_STC_INT_EXPECT_LS_8822B(x) \ + ((x) & (~BITS_STC_INT_EXPECT_LS_8822B)) +#define BIT_GET_STC_INT_EXPECT_LS_8822B(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822B) & \ + BIT_MASK_STC_INT_EXPECT_LS_8822B) +#define BIT_SET_STC_INT_EXPECT_LS_8822B(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_LS_8822B(x) | BIT_STC_INT_EXPECT_LS_8822B(v)) #define BIT_SHIFT_STC_INT_EXPECT_CS_8822B 0 #define BIT_MASK_STC_INT_EXPECT_CS_8822B 0x3f -#define BIT_STC_INT_EXPECT_CS_8822B(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8822B) << BIT_SHIFT_STC_INT_EXPECT_CS_8822B) -#define BIT_GET_STC_INT_EXPECT_CS_8822B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822B) & BIT_MASK_STC_INT_EXPECT_CS_8822B) - - +#define BIT_STC_INT_EXPECT_CS_8822B(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_CS_8822B) \ + << BIT_SHIFT_STC_INT_EXPECT_CS_8822B) +#define BITS_STC_INT_EXPECT_CS_8822B \ + (BIT_MASK_STC_INT_EXPECT_CS_8822B << BIT_SHIFT_STC_INT_EXPECT_CS_8822B) +#define BIT_CLEAR_STC_INT_EXPECT_CS_8822B(x) \ + ((x) & (~BITS_STC_INT_EXPECT_CS_8822B)) +#define BIT_GET_STC_INT_EXPECT_CS_8822B(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822B) & \ + BIT_MASK_STC_INT_EXPECT_CS_8822B) +#define BIT_SET_STC_INT_EXPECT_CS_8822B(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_CS_8822B(x) | BIT_STC_INT_EXPECT_CS_8822B(v)) /* 2 REG_CMU_DLY_CTRL_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */ #define BIT_CMU_DLY_EN_8822B BIT(31) @@ -5106,104 +7621,206 @@ #define BIT_SHIFT_CMU_DLY_PRE_DIV_8822B 0 #define BIT_MASK_CMU_DLY_PRE_DIV_8822B 0xff -#define BIT_CMU_DLY_PRE_DIV_8822B(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8822B) << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) -#define BIT_GET_CMU_DLY_PRE_DIV_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) & BIT_MASK_CMU_DLY_PRE_DIV_8822B) - - +#define BIT_CMU_DLY_PRE_DIV_8822B(x) \ + (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8822B) \ + << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) +#define BITS_CMU_DLY_PRE_DIV_8822B \ + (BIT_MASK_CMU_DLY_PRE_DIV_8822B << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) +#define BIT_CLEAR_CMU_DLY_PRE_DIV_8822B(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8822B)) +#define BIT_GET_CMU_DLY_PRE_DIV_8822B(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) & \ + BIT_MASK_CMU_DLY_PRE_DIV_8822B) +#define BIT_SET_CMU_DLY_PRE_DIV_8822B(x, v) \ + (BIT_CLEAR_CMU_DLY_PRE_DIV_8822B(x) | BIT_CMU_DLY_PRE_DIV_8822B(v)) /* 2 REG_CMU_DLY_CFG_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ #define BIT_SHIFT_CMU_DLY_LTR_A2I_8822B 24 #define BIT_MASK_CMU_DLY_LTR_A2I_8822B 0xff -#define BIT_CMU_DLY_LTR_A2I_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8822B) << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) -#define BIT_GET_CMU_DLY_LTR_A2I_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) & BIT_MASK_CMU_DLY_LTR_A2I_8822B) - - +#define BIT_CMU_DLY_LTR_A2I_8822B(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8822B) \ + << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) +#define BITS_CMU_DLY_LTR_A2I_8822B \ + (BIT_MASK_CMU_DLY_LTR_A2I_8822B << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) +#define BIT_CLEAR_CMU_DLY_LTR_A2I_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8822B)) +#define BIT_GET_CMU_DLY_LTR_A2I_8822B(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) & \ + BIT_MASK_CMU_DLY_LTR_A2I_8822B) +#define BIT_SET_CMU_DLY_LTR_A2I_8822B(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_A2I_8822B(x) | BIT_CMU_DLY_LTR_A2I_8822B(v)) #define BIT_SHIFT_CMU_DLY_LTR_I2A_8822B 16 #define BIT_MASK_CMU_DLY_LTR_I2A_8822B 0xff -#define BIT_CMU_DLY_LTR_I2A_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8822B) << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) -#define BIT_GET_CMU_DLY_LTR_I2A_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) & BIT_MASK_CMU_DLY_LTR_I2A_8822B) - - +#define BIT_CMU_DLY_LTR_I2A_8822B(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8822B) \ + << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) +#define BITS_CMU_DLY_LTR_I2A_8822B \ + (BIT_MASK_CMU_DLY_LTR_I2A_8822B << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) +#define BIT_CLEAR_CMU_DLY_LTR_I2A_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8822B)) +#define BIT_GET_CMU_DLY_LTR_I2A_8822B(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) & \ + BIT_MASK_CMU_DLY_LTR_I2A_8822B) +#define BIT_SET_CMU_DLY_LTR_I2A_8822B(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_I2A_8822B(x) | BIT_CMU_DLY_LTR_I2A_8822B(v)) #define BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B 8 #define BIT_MASK_CMU_DLY_LTR_IDLE_8822B 0xff -#define BIT_CMU_DLY_LTR_IDLE_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) -#define BIT_GET_CMU_DLY_LTR_IDLE_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B) - - +#define BIT_CMU_DLY_LTR_IDLE_8822B(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B) \ + << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) +#define BITS_CMU_DLY_LTR_IDLE_8822B \ + (BIT_MASK_CMU_DLY_LTR_IDLE_8822B << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) +#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8822B(x) \ + ((x) & (~BITS_CMU_DLY_LTR_IDLE_8822B)) +#define BIT_GET_CMU_DLY_LTR_IDLE_8822B(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) & \ + BIT_MASK_CMU_DLY_LTR_IDLE_8822B) +#define BIT_SET_CMU_DLY_LTR_IDLE_8822B(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_IDLE_8822B(x) | BIT_CMU_DLY_LTR_IDLE_8822B(v)) #define BIT_SHIFT_CMU_DLY_LTR_ACT_8822B 0 #define BIT_MASK_CMU_DLY_LTR_ACT_8822B 0xff -#define BIT_CMU_DLY_LTR_ACT_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8822B) << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) -#define BIT_GET_CMU_DLY_LTR_ACT_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) & BIT_MASK_CMU_DLY_LTR_ACT_8822B) - - +#define BIT_CMU_DLY_LTR_ACT_8822B(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8822B) \ + << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) +#define BITS_CMU_DLY_LTR_ACT_8822B \ + (BIT_MASK_CMU_DLY_LTR_ACT_8822B << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) +#define BIT_CLEAR_CMU_DLY_LTR_ACT_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8822B)) +#define BIT_GET_CMU_DLY_LTR_ACT_8822B(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) & \ + BIT_MASK_CMU_DLY_LTR_ACT_8822B) +#define BIT_SET_CMU_DLY_LTR_ACT_8822B(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_ACT_8822B(x) | BIT_CMU_DLY_LTR_ACT_8822B(v)) /* 2 REG_H2CQ_TXBD_DESA_8822B */ #define BIT_SHIFT_H2CQ_TXBD_DESA_8822B 0 #define BIT_MASK_H2CQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_H2CQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8822B) << BIT_SHIFT_H2CQ_TXBD_DESA_8822B) -#define BIT_GET_H2CQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822B) & BIT_MASK_H2CQ_TXBD_DESA_8822B) - - +#define BIT_H2CQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_8822B) \ + << BIT_SHIFT_H2CQ_TXBD_DESA_8822B) +#define BITS_H2CQ_TXBD_DESA_8822B \ + (BIT_MASK_H2CQ_TXBD_DESA_8822B << BIT_SHIFT_H2CQ_TXBD_DESA_8822B) +#define BIT_CLEAR_H2CQ_TXBD_DESA_8822B(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8822B)) +#define BIT_GET_H2CQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822B) & \ + BIT_MASK_H2CQ_TXBD_DESA_8822B) +#define BIT_SET_H2CQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_8822B(x) | BIT_H2CQ_TXBD_DESA_8822B(v)) /* 2 REG_H2CQ_TXBD_NUM_8822B */ #define BIT_PCIE_H2CQ_FLAG_8822B BIT(14) #define BIT_SHIFT_H2CQ_DESC_MODE_8822B 12 #define BIT_MASK_H2CQ_DESC_MODE_8822B 0x3 -#define BIT_H2CQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8822B) << BIT_SHIFT_H2CQ_DESC_MODE_8822B) -#define BIT_GET_H2CQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822B) & BIT_MASK_H2CQ_DESC_MODE_8822B) - - +#define BIT_H2CQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_H2CQ_DESC_MODE_8822B) \ + << BIT_SHIFT_H2CQ_DESC_MODE_8822B) +#define BITS_H2CQ_DESC_MODE_8822B \ + (BIT_MASK_H2CQ_DESC_MODE_8822B << BIT_SHIFT_H2CQ_DESC_MODE_8822B) +#define BIT_CLEAR_H2CQ_DESC_MODE_8822B(x) ((x) & (~BITS_H2CQ_DESC_MODE_8822B)) +#define BIT_GET_H2CQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822B) & \ + BIT_MASK_H2CQ_DESC_MODE_8822B) +#define BIT_SET_H2CQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_H2CQ_DESC_MODE_8822B(x) | BIT_H2CQ_DESC_MODE_8822B(v)) #define BIT_SHIFT_H2CQ_DESC_NUM_8822B 0 #define BIT_MASK_H2CQ_DESC_NUM_8822B 0xfff -#define BIT_H2CQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8822B) << BIT_SHIFT_H2CQ_DESC_NUM_8822B) -#define BIT_GET_H2CQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822B) & BIT_MASK_H2CQ_DESC_NUM_8822B) - - +#define BIT_H2CQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_H2CQ_DESC_NUM_8822B) << BIT_SHIFT_H2CQ_DESC_NUM_8822B) +#define BITS_H2CQ_DESC_NUM_8822B \ + (BIT_MASK_H2CQ_DESC_NUM_8822B << BIT_SHIFT_H2CQ_DESC_NUM_8822B) +#define BIT_CLEAR_H2CQ_DESC_NUM_8822B(x) ((x) & (~BITS_H2CQ_DESC_NUM_8822B)) +#define BIT_GET_H2CQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822B) & BIT_MASK_H2CQ_DESC_NUM_8822B) +#define BIT_SET_H2CQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_H2CQ_DESC_NUM_8822B(x) | BIT_H2CQ_DESC_NUM_8822B(v)) /* 2 REG_H2CQ_TXBD_IDX_8822B */ #define BIT_SHIFT_H2CQ_HW_IDX_8822B 16 #define BIT_MASK_H2CQ_HW_IDX_8822B 0xfff -#define BIT_H2CQ_HW_IDX_8822B(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8822B) << BIT_SHIFT_H2CQ_HW_IDX_8822B) -#define BIT_GET_H2CQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822B) & BIT_MASK_H2CQ_HW_IDX_8822B) - - +#define BIT_H2CQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_H2CQ_HW_IDX_8822B) << BIT_SHIFT_H2CQ_HW_IDX_8822B) +#define BITS_H2CQ_HW_IDX_8822B \ + (BIT_MASK_H2CQ_HW_IDX_8822B << BIT_SHIFT_H2CQ_HW_IDX_8822B) +#define BIT_CLEAR_H2CQ_HW_IDX_8822B(x) ((x) & (~BITS_H2CQ_HW_IDX_8822B)) +#define BIT_GET_H2CQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822B) & BIT_MASK_H2CQ_HW_IDX_8822B) +#define BIT_SET_H2CQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_H2CQ_HW_IDX_8822B(x) | BIT_H2CQ_HW_IDX_8822B(v)) #define BIT_SHIFT_H2CQ_HOST_IDX_8822B 0 #define BIT_MASK_H2CQ_HOST_IDX_8822B 0xfff -#define BIT_H2CQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8822B) << BIT_SHIFT_H2CQ_HOST_IDX_8822B) -#define BIT_GET_H2CQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822B) & BIT_MASK_H2CQ_HOST_IDX_8822B) - - +#define BIT_H2CQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_H2CQ_HOST_IDX_8822B) << BIT_SHIFT_H2CQ_HOST_IDX_8822B) +#define BITS_H2CQ_HOST_IDX_8822B \ + (BIT_MASK_H2CQ_HOST_IDX_8822B << BIT_SHIFT_H2CQ_HOST_IDX_8822B) +#define BIT_CLEAR_H2CQ_HOST_IDX_8822B(x) ((x) & (~BITS_H2CQ_HOST_IDX_8822B)) +#define BIT_GET_H2CQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822B) & BIT_MASK_H2CQ_HOST_IDX_8822B) +#define BIT_SET_H2CQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_H2CQ_HOST_IDX_8822B(x) | BIT_H2CQ_HOST_IDX_8822B(v)) /* 2 REG_H2CQ_CSR_8822B[31:0] (H2CQ CONTROL AND STATUS) */ #define BIT_H2CQ_FULL_8822B BIT(31) #define BIT_CLR_H2CQ_HOST_IDX_8822B BIT(16) #define BIT_CLR_H2CQ_HW_IDX_8822B BIT(8) +#define BIT_STOP_H2CQ_8822B BIT(0) /* 2 REG_CHANGE_PCIE_SPEED_8822B */ #define BIT_CHANGE_PCIE_SPEED_8822B BIT(18) #define BIT_SHIFT_GEN1_GEN2_8822B 16 #define BIT_MASK_GEN1_GEN2_8822B 0x3 -#define BIT_GEN1_GEN2_8822B(x) (((x) & BIT_MASK_GEN1_GEN2_8822B) << BIT_SHIFT_GEN1_GEN2_8822B) -#define BIT_GET_GEN1_GEN2_8822B(x) (((x) >> BIT_SHIFT_GEN1_GEN2_8822B) & BIT_MASK_GEN1_GEN2_8822B) - - +#define BIT_GEN1_GEN2_8822B(x) \ + (((x) & BIT_MASK_GEN1_GEN2_8822B) << BIT_SHIFT_GEN1_GEN2_8822B) +#define BITS_GEN1_GEN2_8822B \ + (BIT_MASK_GEN1_GEN2_8822B << BIT_SHIFT_GEN1_GEN2_8822B) +#define BIT_CLEAR_GEN1_GEN2_8822B(x) ((x) & (~BITS_GEN1_GEN2_8822B)) +#define BIT_GET_GEN1_GEN2_8822B(x) \ + (((x) >> BIT_SHIFT_GEN1_GEN2_8822B) & BIT_MASK_GEN1_GEN2_8822B) +#define BIT_SET_GEN1_GEN2_8822B(x, v) \ + (BIT_CLEAR_GEN1_GEN2_8822B(x) | BIT_GEN1_GEN2_8822B(v)) + +#define BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B 8 +#define BIT_MASK_RXDMA_ERROR_COUNTER_8822B 0xff +#define BIT_RXDMA_ERROR_COUNTER_8822B(x) \ + (((x) & BIT_MASK_RXDMA_ERROR_COUNTER_8822B) \ + << BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B) +#define BITS_RXDMA_ERROR_COUNTER_8822B \ + (BIT_MASK_RXDMA_ERROR_COUNTER_8822B \ + << BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B) +#define BIT_CLEAR_RXDMA_ERROR_COUNTER_8822B(x) \ + ((x) & (~BITS_RXDMA_ERROR_COUNTER_8822B)) +#define BIT_GET_RXDMA_ERROR_COUNTER_8822B(x) \ + (((x) >> BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B) & \ + BIT_MASK_RXDMA_ERROR_COUNTER_8822B) +#define BIT_SET_RXDMA_ERROR_COUNTER_8822B(x, v) \ + (BIT_CLEAR_RXDMA_ERROR_COUNTER_8822B(x) | \ + BIT_RXDMA_ERROR_COUNTER_8822B(v)) + +#define BIT_TXDMA_ERROR_HANDLE_STATUS_8822B BIT(7) +#define BIT_TXDMA_ERROR_PULSE_8822B BIT(6) +#define BIT_TXDMA_STUCK_ERROR_HANDLE_ENABLE_8822B BIT(5) +#define BIT_TXDMA_RETURN_ERROR_ENABLE_8822B BIT(4) +#define BIT_RXDMA_ERROR_HANDLE_STATUS_8822B BIT(3) #define BIT_SHIFT_AUTO_HANG_RELEASE_8822B 0 #define BIT_MASK_AUTO_HANG_RELEASE_8822B 0x7 -#define BIT_AUTO_HANG_RELEASE_8822B(x) (((x) & BIT_MASK_AUTO_HANG_RELEASE_8822B) << BIT_SHIFT_AUTO_HANG_RELEASE_8822B) -#define BIT_GET_AUTO_HANG_RELEASE_8822B(x) (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE_8822B) & BIT_MASK_AUTO_HANG_RELEASE_8822B) - - +#define BIT_AUTO_HANG_RELEASE_8822B(x) \ + (((x) & BIT_MASK_AUTO_HANG_RELEASE_8822B) \ + << BIT_SHIFT_AUTO_HANG_RELEASE_8822B) +#define BITS_AUTO_HANG_RELEASE_8822B \ + (BIT_MASK_AUTO_HANG_RELEASE_8822B << BIT_SHIFT_AUTO_HANG_RELEASE_8822B) +#define BIT_CLEAR_AUTO_HANG_RELEASE_8822B(x) \ + ((x) & (~BITS_AUTO_HANG_RELEASE_8822B)) +#define BIT_GET_AUTO_HANG_RELEASE_8822B(x) \ + (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE_8822B) & \ + BIT_MASK_AUTO_HANG_RELEASE_8822B) +#define BIT_SET_AUTO_HANG_RELEASE_8822B(x, v) \ + (BIT_CLEAR_AUTO_HANG_RELEASE_8822B(x) | BIT_AUTO_HANG_RELEASE_8822B(v)) /* 2 REG_OLD_DEHANG_8822B */ #define BIT_OLD_DEHANG_8822B BIT(1) @@ -5212,196 +7829,375 @@ #define BIT_SHIFT_QUEUEMACID_Q0_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q0_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q0_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) -#define BIT_GET_QUEUEMACID_Q0_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) & BIT_MASK_QUEUEMACID_Q0_V1_8822B) - - +#define BIT_QUEUEMACID_Q0_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) +#define BITS_QUEUEMACID_Q0_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q0_V1_8822B << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q0_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q0_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q0_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q0_V1_8822B) +#define BIT_SET_QUEUEMACID_Q0_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q0_V1_8822B(x) | BIT_QUEUEMACID_Q0_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q0_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q0_V1_8822B 0x3 -#define BIT_QUEUEAC_Q0_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8822B) << BIT_SHIFT_QUEUEAC_Q0_V1_8822B) -#define BIT_GET_QUEUEAC_Q0_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822B) & BIT_MASK_QUEUEAC_Q0_V1_8822B) - +#define BIT_QUEUEAC_Q0_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q0_V1_8822B) << BIT_SHIFT_QUEUEAC_Q0_V1_8822B) +#define BITS_QUEUEAC_Q0_V1_8822B \ + (BIT_MASK_QUEUEAC_Q0_V1_8822B << BIT_SHIFT_QUEUEAC_Q0_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q0_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8822B)) +#define BIT_GET_QUEUEAC_Q0_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822B) & BIT_MASK_QUEUEAC_Q0_V1_8822B) +#define BIT_SET_QUEUEAC_Q0_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q0_V1_8822B(x) | BIT_QUEUEAC_Q0_V1_8822B(v)) #define BIT_TIDEMPTY_Q0_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q0_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q0_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q0_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) -#define BIT_GET_TAIL_PKT_Q0_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) & BIT_MASK_TAIL_PKT_Q0_V2_8822B) - - +#define BIT_TAIL_PKT_Q0_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) +#define BITS_TAIL_PKT_Q0_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q0_V2_8822B << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q0_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q0_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q0_V2_8822B) +#define BIT_SET_TAIL_PKT_Q0_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q0_V2_8822B(x) | BIT_TAIL_PKT_Q0_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q0_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q0_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q0_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) -#define BIT_GET_HEAD_PKT_Q0_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) & BIT_MASK_HEAD_PKT_Q0_V1_8822B) - - +#define BIT_HEAD_PKT_Q0_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) +#define BITS_HEAD_PKT_Q0_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q0_V1_8822B << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q0_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q0_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q0_V1_8822B) +#define BIT_SET_HEAD_PKT_Q0_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q0_V1_8822B(x) | BIT_HEAD_PKT_Q0_V1_8822B(v)) /* 2 REG_Q1_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q1_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q1_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q1_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) -#define BIT_GET_QUEUEMACID_Q1_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) & BIT_MASK_QUEUEMACID_Q1_V1_8822B) - - +#define BIT_QUEUEMACID_Q1_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) +#define BITS_QUEUEMACID_Q1_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q1_V1_8822B << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q1_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q1_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q1_V1_8822B) +#define BIT_SET_QUEUEMACID_Q1_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q1_V1_8822B(x) | BIT_QUEUEMACID_Q1_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q1_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q1_V1_8822B 0x3 -#define BIT_QUEUEAC_Q1_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8822B) << BIT_SHIFT_QUEUEAC_Q1_V1_8822B) -#define BIT_GET_QUEUEAC_Q1_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822B) & BIT_MASK_QUEUEAC_Q1_V1_8822B) - +#define BIT_QUEUEAC_Q1_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q1_V1_8822B) << BIT_SHIFT_QUEUEAC_Q1_V1_8822B) +#define BITS_QUEUEAC_Q1_V1_8822B \ + (BIT_MASK_QUEUEAC_Q1_V1_8822B << BIT_SHIFT_QUEUEAC_Q1_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q1_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8822B)) +#define BIT_GET_QUEUEAC_Q1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822B) & BIT_MASK_QUEUEAC_Q1_V1_8822B) +#define BIT_SET_QUEUEAC_Q1_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q1_V1_8822B(x) | BIT_QUEUEAC_Q1_V1_8822B(v)) #define BIT_TIDEMPTY_Q1_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q1_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q1_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q1_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) -#define BIT_GET_TAIL_PKT_Q1_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) & BIT_MASK_TAIL_PKT_Q1_V2_8822B) - - +#define BIT_TAIL_PKT_Q1_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) +#define BITS_TAIL_PKT_Q1_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q1_V2_8822B << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q1_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q1_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q1_V2_8822B) +#define BIT_SET_TAIL_PKT_Q1_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q1_V2_8822B(x) | BIT_TAIL_PKT_Q1_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q1_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q1_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q1_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) -#define BIT_GET_HEAD_PKT_Q1_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) & BIT_MASK_HEAD_PKT_Q1_V1_8822B) - - +#define BIT_HEAD_PKT_Q1_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) +#define BITS_HEAD_PKT_Q1_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q1_V1_8822B << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q1_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q1_V1_8822B) +#define BIT_SET_HEAD_PKT_Q1_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q1_V1_8822B(x) | BIT_HEAD_PKT_Q1_V1_8822B(v)) /* 2 REG_Q2_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q2_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q2_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q2_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) -#define BIT_GET_QUEUEMACID_Q2_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) & BIT_MASK_QUEUEMACID_Q2_V1_8822B) - - +#define BIT_QUEUEMACID_Q2_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) +#define BITS_QUEUEMACID_Q2_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q2_V1_8822B << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q2_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q2_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q2_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q2_V1_8822B) +#define BIT_SET_QUEUEMACID_Q2_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q2_V1_8822B(x) | BIT_QUEUEMACID_Q2_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q2_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q2_V1_8822B 0x3 -#define BIT_QUEUEAC_Q2_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8822B) << BIT_SHIFT_QUEUEAC_Q2_V1_8822B) -#define BIT_GET_QUEUEAC_Q2_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822B) & BIT_MASK_QUEUEAC_Q2_V1_8822B) - +#define BIT_QUEUEAC_Q2_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q2_V1_8822B) << BIT_SHIFT_QUEUEAC_Q2_V1_8822B) +#define BITS_QUEUEAC_Q2_V1_8822B \ + (BIT_MASK_QUEUEAC_Q2_V1_8822B << BIT_SHIFT_QUEUEAC_Q2_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q2_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8822B)) +#define BIT_GET_QUEUEAC_Q2_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822B) & BIT_MASK_QUEUEAC_Q2_V1_8822B) +#define BIT_SET_QUEUEAC_Q2_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q2_V1_8822B(x) | BIT_QUEUEAC_Q2_V1_8822B(v)) #define BIT_TIDEMPTY_Q2_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q2_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q2_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q2_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) -#define BIT_GET_TAIL_PKT_Q2_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) & BIT_MASK_TAIL_PKT_Q2_V2_8822B) - - +#define BIT_TAIL_PKT_Q2_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) +#define BITS_TAIL_PKT_Q2_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q2_V2_8822B << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q2_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q2_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q2_V2_8822B) +#define BIT_SET_TAIL_PKT_Q2_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q2_V2_8822B(x) | BIT_TAIL_PKT_Q2_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q2_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q2_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q2_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) -#define BIT_GET_HEAD_PKT_Q2_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) & BIT_MASK_HEAD_PKT_Q2_V1_8822B) - - +#define BIT_HEAD_PKT_Q2_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) +#define BITS_HEAD_PKT_Q2_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q2_V1_8822B << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q2_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q2_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q2_V1_8822B) +#define BIT_SET_HEAD_PKT_Q2_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q2_V1_8822B(x) | BIT_HEAD_PKT_Q2_V1_8822B(v)) /* 2 REG_Q3_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q3_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q3_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q3_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) -#define BIT_GET_QUEUEMACID_Q3_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) & BIT_MASK_QUEUEMACID_Q3_V1_8822B) - - +#define BIT_QUEUEMACID_Q3_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) +#define BITS_QUEUEMACID_Q3_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q3_V1_8822B << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q3_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q3_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q3_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q3_V1_8822B) +#define BIT_SET_QUEUEMACID_Q3_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q3_V1_8822B(x) | BIT_QUEUEMACID_Q3_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q3_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q3_V1_8822B 0x3 -#define BIT_QUEUEAC_Q3_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8822B) << BIT_SHIFT_QUEUEAC_Q3_V1_8822B) -#define BIT_GET_QUEUEAC_Q3_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822B) & BIT_MASK_QUEUEAC_Q3_V1_8822B) - +#define BIT_QUEUEAC_Q3_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q3_V1_8822B) << BIT_SHIFT_QUEUEAC_Q3_V1_8822B) +#define BITS_QUEUEAC_Q3_V1_8822B \ + (BIT_MASK_QUEUEAC_Q3_V1_8822B << BIT_SHIFT_QUEUEAC_Q3_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q3_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8822B)) +#define BIT_GET_QUEUEAC_Q3_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822B) & BIT_MASK_QUEUEAC_Q3_V1_8822B) +#define BIT_SET_QUEUEAC_Q3_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q3_V1_8822B(x) | BIT_QUEUEAC_Q3_V1_8822B(v)) #define BIT_TIDEMPTY_Q3_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q3_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q3_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q3_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) -#define BIT_GET_TAIL_PKT_Q3_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) & BIT_MASK_TAIL_PKT_Q3_V2_8822B) - - +#define BIT_TAIL_PKT_Q3_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) +#define BITS_TAIL_PKT_Q3_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q3_V2_8822B << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q3_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q3_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q3_V2_8822B) +#define BIT_SET_TAIL_PKT_Q3_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q3_V2_8822B(x) | BIT_TAIL_PKT_Q3_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q3_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q3_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q3_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) -#define BIT_GET_HEAD_PKT_Q3_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) & BIT_MASK_HEAD_PKT_Q3_V1_8822B) - - +#define BIT_HEAD_PKT_Q3_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) +#define BITS_HEAD_PKT_Q3_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q3_V1_8822B << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q3_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q3_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q3_V1_8822B) +#define BIT_SET_HEAD_PKT_Q3_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q3_V1_8822B(x) | BIT_HEAD_PKT_Q3_V1_8822B(v)) /* 2 REG_MGQ_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B 25 #define BIT_MASK_QUEUEMACID_MGQ_V1_8822B 0x7f -#define BIT_QUEUEMACID_MGQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) -#define BIT_GET_QUEUEMACID_MGQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B) - - +#define BIT_QUEUEMACID_MGQ_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) +#define BITS_QUEUEMACID_MGQ_V1_8822B \ + (BIT_MASK_QUEUEMACID_MGQ_V1_8822B << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_MGQ_V1_8822B)) +#define BIT_GET_QUEUEMACID_MGQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) & \ + BIT_MASK_QUEUEMACID_MGQ_V1_8822B) +#define BIT_SET_QUEUEMACID_MGQ_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_MGQ_V1_8822B(x) | BIT_QUEUEMACID_MGQ_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_MGQ_V1_8822B 23 #define BIT_MASK_QUEUEAC_MGQ_V1_8822B 0x3 -#define BIT_QUEUEAC_MGQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822B) << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) -#define BIT_GET_QUEUEAC_MGQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) & BIT_MASK_QUEUEAC_MGQ_V1_8822B) - +#define BIT_QUEUEAC_MGQ_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822B) \ + << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) +#define BITS_QUEUEAC_MGQ_V1_8822B \ + (BIT_MASK_QUEUEAC_MGQ_V1_8822B << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) +#define BIT_CLEAR_QUEUEAC_MGQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8822B)) +#define BIT_GET_QUEUEAC_MGQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) & \ + BIT_MASK_QUEUEAC_MGQ_V1_8822B) +#define BIT_SET_QUEUEAC_MGQ_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_MGQ_V1_8822B(x) | BIT_QUEUEAC_MGQ_V1_8822B(v)) #define BIT_TIDEMPTY_MGQ_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B 11 #define BIT_MASK_TAIL_PKT_MGQ_V2_8822B 0x7ff -#define BIT_TAIL_PKT_MGQ_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) -#define BIT_GET_TAIL_PKT_MGQ_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B) - - +#define BIT_TAIL_PKT_MGQ_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) +#define BITS_TAIL_PKT_MGQ_V2_8822B \ + (BIT_MASK_TAIL_PKT_MGQ_V2_8822B << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8822B)) +#define BIT_GET_TAIL_PKT_MGQ_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) & \ + BIT_MASK_TAIL_PKT_MGQ_V2_8822B) +#define BIT_SET_TAIL_PKT_MGQ_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_MGQ_V2_8822B(x) | BIT_TAIL_PKT_MGQ_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B 0 #define BIT_MASK_HEAD_PKT_MGQ_V1_8822B 0x7ff -#define BIT_HEAD_PKT_MGQ_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) -#define BIT_GET_HEAD_PKT_MGQ_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B) - - +#define BIT_HEAD_PKT_MGQ_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) +#define BITS_HEAD_PKT_MGQ_V1_8822B \ + (BIT_MASK_HEAD_PKT_MGQ_V1_8822B << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8822B)) +#define BIT_GET_HEAD_PKT_MGQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) & \ + BIT_MASK_HEAD_PKT_MGQ_V1_8822B) +#define BIT_SET_HEAD_PKT_MGQ_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_MGQ_V1_8822B(x) | BIT_HEAD_PKT_MGQ_V1_8822B(v)) /* 2 REG_HIQ_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B 25 #define BIT_MASK_QUEUEMACID_HIQ_V1_8822B 0x7f -#define BIT_QUEUEMACID_HIQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) -#define BIT_GET_QUEUEMACID_HIQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B) - - +#define BIT_QUEUEMACID_HIQ_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) +#define BITS_QUEUEMACID_HIQ_V1_8822B \ + (BIT_MASK_QUEUEMACID_HIQ_V1_8822B << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_HIQ_V1_8822B)) +#define BIT_GET_QUEUEMACID_HIQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) & \ + BIT_MASK_QUEUEMACID_HIQ_V1_8822B) +#define BIT_SET_QUEUEMACID_HIQ_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_HIQ_V1_8822B(x) | BIT_QUEUEMACID_HIQ_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_HIQ_V1_8822B 23 #define BIT_MASK_QUEUEAC_HIQ_V1_8822B 0x3 -#define BIT_QUEUEAC_HIQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822B) << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) -#define BIT_GET_QUEUEAC_HIQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) & BIT_MASK_QUEUEAC_HIQ_V1_8822B) - +#define BIT_QUEUEAC_HIQ_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822B) \ + << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) +#define BITS_QUEUEAC_HIQ_V1_8822B \ + (BIT_MASK_QUEUEAC_HIQ_V1_8822B << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) +#define BIT_CLEAR_QUEUEAC_HIQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8822B)) +#define BIT_GET_QUEUEAC_HIQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) & \ + BIT_MASK_QUEUEAC_HIQ_V1_8822B) +#define BIT_SET_QUEUEAC_HIQ_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_HIQ_V1_8822B(x) | BIT_QUEUEAC_HIQ_V1_8822B(v)) #define BIT_TIDEMPTY_HIQ_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B 11 #define BIT_MASK_TAIL_PKT_HIQ_V2_8822B 0x7ff -#define BIT_TAIL_PKT_HIQ_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) -#define BIT_GET_TAIL_PKT_HIQ_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B) - - +#define BIT_TAIL_PKT_HIQ_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) +#define BITS_TAIL_PKT_HIQ_V2_8822B \ + (BIT_MASK_TAIL_PKT_HIQ_V2_8822B << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8822B)) +#define BIT_GET_TAIL_PKT_HIQ_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) & \ + BIT_MASK_TAIL_PKT_HIQ_V2_8822B) +#define BIT_SET_TAIL_PKT_HIQ_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_HIQ_V2_8822B(x) | BIT_TAIL_PKT_HIQ_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B 0 #define BIT_MASK_HEAD_PKT_HIQ_V1_8822B 0x7ff -#define BIT_HEAD_PKT_HIQ_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) -#define BIT_GET_HEAD_PKT_HIQ_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B) - - +#define BIT_HEAD_PKT_HIQ_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) +#define BITS_HEAD_PKT_HIQ_V1_8822B \ + (BIT_MASK_HEAD_PKT_HIQ_V1_8822B << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8822B)) +#define BIT_GET_HEAD_PKT_HIQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) & \ + BIT_MASK_HEAD_PKT_HIQ_V1_8822B) +#define BIT_SET_HEAD_PKT_HIQ_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_HIQ_V1_8822B(x) | BIT_HEAD_PKT_HIQ_V1_8822B(v)) /* 2 REG_BCNQ_INFO_8822B */ #define BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B 0 #define BIT_MASK_BCNQ_HEAD_PG_V1_8822B 0xfff -#define BIT_BCNQ_HEAD_PG_V1_8822B(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) -#define BIT_GET_BCNQ_HEAD_PG_V1_8822B(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B) - - +#define BIT_BCNQ_HEAD_PG_V1_8822B(x) \ + (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B) \ + << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) +#define BITS_BCNQ_HEAD_PG_V1_8822B \ + (BIT_MASK_BCNQ_HEAD_PG_V1_8822B << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) +#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8822B(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8822B)) +#define BIT_GET_BCNQ_HEAD_PG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) & \ + BIT_MASK_BCNQ_HEAD_PG_V1_8822B) +#define BIT_SET_BCNQ_HEAD_PG_V1_8822B(x, v) \ + (BIT_CLEAR_BCNQ_HEAD_PG_V1_8822B(x) | BIT_BCNQ_HEAD_PG_V1_8822B(v)) /* 2 REG_TXPKT_EMPTY_8822B */ #define BIT_BCNQ_EMPTY_8822B BIT(11) @@ -5425,10 +8221,17 @@ #define BIT_SHIFT_FW_FREE_TAIL_V1_8822B 0 #define BIT_MASK_FW_FREE_TAIL_V1_8822B 0xfff -#define BIT_FW_FREE_TAIL_V1_8822B(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8822B) << BIT_SHIFT_FW_FREE_TAIL_V1_8822B) -#define BIT_GET_FW_FREE_TAIL_V1_8822B(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822B) & BIT_MASK_FW_FREE_TAIL_V1_8822B) - - +#define BIT_FW_FREE_TAIL_V1_8822B(x) \ + (((x) & BIT_MASK_FW_FREE_TAIL_V1_8822B) \ + << BIT_SHIFT_FW_FREE_TAIL_V1_8822B) +#define BITS_FW_FREE_TAIL_V1_8822B \ + (BIT_MASK_FW_FREE_TAIL_V1_8822B << BIT_SHIFT_FW_FREE_TAIL_V1_8822B) +#define BIT_CLEAR_FW_FREE_TAIL_V1_8822B(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8822B)) +#define BIT_GET_FW_FREE_TAIL_V1_8822B(x) \ + (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822B) & \ + BIT_MASK_FW_FREE_TAIL_V1_8822B) +#define BIT_SET_FW_FREE_TAIL_V1_8822B(x, v) \ + (BIT_CLEAR_FW_FREE_TAIL_V1_8822B(x) | BIT_FW_FREE_TAIL_V1_8822B(v)) /* 2 REG_FWHW_TXQ_CTRL_8822B */ #define BIT_RTS_LIMIT_IN_OFDM_8822B BIT(23) @@ -5438,9 +8241,15 @@ #define BIT_SHIFT_EN_QUEUE_RPT_8822B 8 #define BIT_MASK_EN_QUEUE_RPT_8822B 0xff -#define BIT_EN_QUEUE_RPT_8822B(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8822B) << BIT_SHIFT_EN_QUEUE_RPT_8822B) -#define BIT_GET_EN_QUEUE_RPT_8822B(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822B) & BIT_MASK_EN_QUEUE_RPT_8822B) - +#define BIT_EN_QUEUE_RPT_8822B(x) \ + (((x) & BIT_MASK_EN_QUEUE_RPT_8822B) << BIT_SHIFT_EN_QUEUE_RPT_8822B) +#define BITS_EN_QUEUE_RPT_8822B \ + (BIT_MASK_EN_QUEUE_RPT_8822B << BIT_SHIFT_EN_QUEUE_RPT_8822B) +#define BIT_CLEAR_EN_QUEUE_RPT_8822B(x) ((x) & (~BITS_EN_QUEUE_RPT_8822B)) +#define BIT_GET_EN_QUEUE_RPT_8822B(x) \ + (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822B) & BIT_MASK_EN_QUEUE_RPT_8822B) +#define BIT_SET_EN_QUEUE_RPT_8822B(x, v) \ + (BIT_CLEAR_EN_QUEUE_RPT_8822B(x) | BIT_EN_QUEUE_RPT_8822B(v)) #define BIT_EN_RTY_BK_8822B BIT(7) #define BIT_EN_USE_INI_RAT_8822B BIT(6) @@ -5452,23 +8261,39 @@ #define BIT_EN_FTMRPT_8822B BIT(0) /* 2 REG_DATAFB_SEL_8822B */ -#define BIT__R_EN_RTY_BK_COD_8822B BIT(2) #define BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B 0 #define BIT_MASK__R_DATA_FALLBACK_SEL_8822B 0x3 -#define BIT__R_DATA_FALLBACK_SEL_8822B(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) -#define BIT_GET__R_DATA_FALLBACK_SEL_8822B(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B) - - +#define BIT__R_DATA_FALLBACK_SEL_8822B(x) \ + (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B) \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) +#define BITS__R_DATA_FALLBACK_SEL_8822B \ + (BIT_MASK__R_DATA_FALLBACK_SEL_8822B \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) +#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8822B(x) \ + ((x) & (~BITS__R_DATA_FALLBACK_SEL_8822B)) +#define BIT_GET__R_DATA_FALLBACK_SEL_8822B(x) \ + (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) & \ + BIT_MASK__R_DATA_FALLBACK_SEL_8822B) +#define BIT_SET__R_DATA_FALLBACK_SEL_8822B(x, v) \ + (BIT_CLEAR__R_DATA_FALLBACK_SEL_8822B(x) | \ + BIT__R_DATA_FALLBACK_SEL_8822B(v)) /* 2 REG_BCNQ_BDNY_V1_8822B */ #define BIT_SHIFT_BCNQ_PGBNDY_V1_8822B 0 #define BIT_MASK_BCNQ_PGBNDY_V1_8822B 0xfff -#define BIT_BCNQ_PGBNDY_V1_8822B(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822B) << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) -#define BIT_GET_BCNQ_PGBNDY_V1_8822B(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) & BIT_MASK_BCNQ_PGBNDY_V1_8822B) - - +#define BIT_BCNQ_PGBNDY_V1_8822B(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822B) \ + << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) +#define BITS_BCNQ_PGBNDY_V1_8822B \ + (BIT_MASK_BCNQ_PGBNDY_V1_8822B << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) +#define BIT_CLEAR_BCNQ_PGBNDY_V1_8822B(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8822B)) +#define BIT_GET_BCNQ_PGBNDY_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) & \ + BIT_MASK_BCNQ_PGBNDY_V1_8822B) +#define BIT_SET_BCNQ_PGBNDY_V1_8822B(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_V1_8822B(x) | BIT_BCNQ_PGBNDY_V1_8822B(v)) /* 2 REG_LIFETIME_EN_8822B */ #define BIT_BT_INT_CPU_8822B BIT(7) @@ -5483,33 +8308,55 @@ #define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B 8 #define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B 0xff -#define BIT_SPEC_SIFS_OFDM_PTCL_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) -#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B) - - +#define BIT_SPEC_SIFS_OFDM_PTCL_8822B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) +#define BITS_SPEC_SIFS_OFDM_PTCL_8822B \ + (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822B(x) \ + ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8822B)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) & \ + BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8822B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822B(x) | \ + BIT_SPEC_SIFS_OFDM_PTCL_8822B(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B 0 #define BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B 0xff -#define BIT_SPEC_SIFS_CCK_PTCL_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) -#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) - - +#define BIT_SPEC_SIFS_CCK_PTCL_8822B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) +#define BITS_SPEC_SIFS_CCK_PTCL_8822B \ + (BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822B(x) \ + ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8822B)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) & \ + BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) +#define BIT_SET_SPEC_SIFS_CCK_PTCL_8822B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822B(x) | \ + BIT_SPEC_SIFS_CCK_PTCL_8822B(v)) /* 2 REG_RETRY_LIMIT_8822B */ #define BIT_SHIFT_SRL_8822B 8 #define BIT_MASK_SRL_8822B 0x3f #define BIT_SRL_8822B(x) (((x) & BIT_MASK_SRL_8822B) << BIT_SHIFT_SRL_8822B) +#define BITS_SRL_8822B (BIT_MASK_SRL_8822B << BIT_SHIFT_SRL_8822B) +#define BIT_CLEAR_SRL_8822B(x) ((x) & (~BITS_SRL_8822B)) #define BIT_GET_SRL_8822B(x) (((x) >> BIT_SHIFT_SRL_8822B) & BIT_MASK_SRL_8822B) - - +#define BIT_SET_SRL_8822B(x, v) (BIT_CLEAR_SRL_8822B(x) | BIT_SRL_8822B(v)) #define BIT_SHIFT_LRL_8822B 0 #define BIT_MASK_LRL_8822B 0x3f #define BIT_LRL_8822B(x) (((x) & BIT_MASK_LRL_8822B) << BIT_SHIFT_LRL_8822B) +#define BITS_LRL_8822B (BIT_MASK_LRL_8822B << BIT_SHIFT_LRL_8822B) +#define BIT_CLEAR_LRL_8822B(x) ((x) & (~BITS_LRL_8822B)) #define BIT_GET_LRL_8822B(x) (((x) >> BIT_SHIFT_LRL_8822B) & BIT_MASK_LRL_8822B) - - +#define BIT_SET_LRL_8822B(x, v) (BIT_CLEAR_LRL_8822B(x) | BIT_LRL_8822B(v)) /* 2 REG_TXBF_CTRL_8822B */ #define BIT_R_ENABLE_NDPA_8822B BIT(31) @@ -5522,9 +8369,15 @@ #define BIT_SHIFT_R_TXBF1_AID_8822B 16 #define BIT_MASK_R_TXBF1_AID_8822B 0x1ff -#define BIT_R_TXBF1_AID_8822B(x) (((x) & BIT_MASK_R_TXBF1_AID_8822B) << BIT_SHIFT_R_TXBF1_AID_8822B) -#define BIT_GET_R_TXBF1_AID_8822B(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8822B) & BIT_MASK_R_TXBF1_AID_8822B) - +#define BIT_R_TXBF1_AID_8822B(x) \ + (((x) & BIT_MASK_R_TXBF1_AID_8822B) << BIT_SHIFT_R_TXBF1_AID_8822B) +#define BITS_R_TXBF1_AID_8822B \ + (BIT_MASK_R_TXBF1_AID_8822B << BIT_SHIFT_R_TXBF1_AID_8822B) +#define BIT_CLEAR_R_TXBF1_AID_8822B(x) ((x) & (~BITS_R_TXBF1_AID_8822B)) +#define BIT_GET_R_TXBF1_AID_8822B(x) \ + (((x) >> BIT_SHIFT_R_TXBF1_AID_8822B) & BIT_MASK_R_TXBF1_AID_8822B) +#define BIT_SET_R_TXBF1_AID_8822B(x, v) \ + (BIT_CLEAR_R_TXBF1_AID_8822B(x) | BIT_R_TXBF1_AID_8822B(v)) #define BIT_DIS_NDP_BFEN_8822B BIT(15) #define BIT_R_TXBCN_NOBLOCK_NDP_8822B BIT(14) @@ -5534,161 +8387,267 @@ #define BIT_SHIFT_R_TXBF0_AID_8822B 0 #define BIT_MASK_R_TXBF0_AID_8822B 0x1ff -#define BIT_R_TXBF0_AID_8822B(x) (((x) & BIT_MASK_R_TXBF0_AID_8822B) << BIT_SHIFT_R_TXBF0_AID_8822B) -#define BIT_GET_R_TXBF0_AID_8822B(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8822B) & BIT_MASK_R_TXBF0_AID_8822B) - - +#define BIT_R_TXBF0_AID_8822B(x) \ + (((x) & BIT_MASK_R_TXBF0_AID_8822B) << BIT_SHIFT_R_TXBF0_AID_8822B) +#define BITS_R_TXBF0_AID_8822B \ + (BIT_MASK_R_TXBF0_AID_8822B << BIT_SHIFT_R_TXBF0_AID_8822B) +#define BIT_CLEAR_R_TXBF0_AID_8822B(x) ((x) & (~BITS_R_TXBF0_AID_8822B)) +#define BIT_GET_R_TXBF0_AID_8822B(x) \ + (((x) >> BIT_SHIFT_R_TXBF0_AID_8822B) & BIT_MASK_R_TXBF0_AID_8822B) +#define BIT_SET_R_TXBF0_AID_8822B(x, v) \ + (BIT_CLEAR_R_TXBF0_AID_8822B(x) | BIT_R_TXBF0_AID_8822B(v)) /* 2 REG_DARFRC_8822B */ #define BIT_SHIFT_DARF_RC8_8822B (56 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC8_8822B 0x1f -#define BIT_DARF_RC8_8822B(x) (((x) & BIT_MASK_DARF_RC8_8822B) << BIT_SHIFT_DARF_RC8_8822B) -#define BIT_GET_DARF_RC8_8822B(x) (((x) >> BIT_SHIFT_DARF_RC8_8822B) & BIT_MASK_DARF_RC8_8822B) - - +#define BIT_DARF_RC8_8822B(x) \ + (((x) & BIT_MASK_DARF_RC8_8822B) << BIT_SHIFT_DARF_RC8_8822B) +#define BITS_DARF_RC8_8822B \ + (BIT_MASK_DARF_RC8_8822B << BIT_SHIFT_DARF_RC8_8822B) +#define BIT_CLEAR_DARF_RC8_8822B(x) ((x) & (~BITS_DARF_RC8_8822B)) +#define BIT_GET_DARF_RC8_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_8822B) & BIT_MASK_DARF_RC8_8822B) +#define BIT_SET_DARF_RC8_8822B(x, v) \ + (BIT_CLEAR_DARF_RC8_8822B(x) | BIT_DARF_RC8_8822B(v)) #define BIT_SHIFT_DARF_RC7_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC7_8822B 0x1f -#define BIT_DARF_RC7_8822B(x) (((x) & BIT_MASK_DARF_RC7_8822B) << BIT_SHIFT_DARF_RC7_8822B) -#define BIT_GET_DARF_RC7_8822B(x) (((x) >> BIT_SHIFT_DARF_RC7_8822B) & BIT_MASK_DARF_RC7_8822B) - - +#define BIT_DARF_RC7_8822B(x) \ + (((x) & BIT_MASK_DARF_RC7_8822B) << BIT_SHIFT_DARF_RC7_8822B) +#define BITS_DARF_RC7_8822B \ + (BIT_MASK_DARF_RC7_8822B << BIT_SHIFT_DARF_RC7_8822B) +#define BIT_CLEAR_DARF_RC7_8822B(x) ((x) & (~BITS_DARF_RC7_8822B)) +#define BIT_GET_DARF_RC7_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_8822B) & BIT_MASK_DARF_RC7_8822B) +#define BIT_SET_DARF_RC7_8822B(x, v) \ + (BIT_CLEAR_DARF_RC7_8822B(x) | BIT_DARF_RC7_8822B(v)) #define BIT_SHIFT_DARF_RC6_8822B (40 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC6_8822B 0x1f -#define BIT_DARF_RC6_8822B(x) (((x) & BIT_MASK_DARF_RC6_8822B) << BIT_SHIFT_DARF_RC6_8822B) -#define BIT_GET_DARF_RC6_8822B(x) (((x) >> BIT_SHIFT_DARF_RC6_8822B) & BIT_MASK_DARF_RC6_8822B) - - +#define BIT_DARF_RC6_8822B(x) \ + (((x) & BIT_MASK_DARF_RC6_8822B) << BIT_SHIFT_DARF_RC6_8822B) +#define BITS_DARF_RC6_8822B \ + (BIT_MASK_DARF_RC6_8822B << BIT_SHIFT_DARF_RC6_8822B) +#define BIT_CLEAR_DARF_RC6_8822B(x) ((x) & (~BITS_DARF_RC6_8822B)) +#define BIT_GET_DARF_RC6_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_8822B) & BIT_MASK_DARF_RC6_8822B) +#define BIT_SET_DARF_RC6_8822B(x, v) \ + (BIT_CLEAR_DARF_RC6_8822B(x) | BIT_DARF_RC6_8822B(v)) #define BIT_SHIFT_DARF_RC5_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC5_8822B 0x1f -#define BIT_DARF_RC5_8822B(x) (((x) & BIT_MASK_DARF_RC5_8822B) << BIT_SHIFT_DARF_RC5_8822B) -#define BIT_GET_DARF_RC5_8822B(x) (((x) >> BIT_SHIFT_DARF_RC5_8822B) & BIT_MASK_DARF_RC5_8822B) - - +#define BIT_DARF_RC5_8822B(x) \ + (((x) & BIT_MASK_DARF_RC5_8822B) << BIT_SHIFT_DARF_RC5_8822B) +#define BITS_DARF_RC5_8822B \ + (BIT_MASK_DARF_RC5_8822B << BIT_SHIFT_DARF_RC5_8822B) +#define BIT_CLEAR_DARF_RC5_8822B(x) ((x) & (~BITS_DARF_RC5_8822B)) +#define BIT_GET_DARF_RC5_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_8822B) & BIT_MASK_DARF_RC5_8822B) +#define BIT_SET_DARF_RC5_8822B(x, v) \ + (BIT_CLEAR_DARF_RC5_8822B(x) | BIT_DARF_RC5_8822B(v)) #define BIT_SHIFT_DARF_RC4_8822B 24 #define BIT_MASK_DARF_RC4_8822B 0x1f -#define BIT_DARF_RC4_8822B(x) (((x) & BIT_MASK_DARF_RC4_8822B) << BIT_SHIFT_DARF_RC4_8822B) -#define BIT_GET_DARF_RC4_8822B(x) (((x) >> BIT_SHIFT_DARF_RC4_8822B) & BIT_MASK_DARF_RC4_8822B) - - +#define BIT_DARF_RC4_8822B(x) \ + (((x) & BIT_MASK_DARF_RC4_8822B) << BIT_SHIFT_DARF_RC4_8822B) +#define BITS_DARF_RC4_8822B \ + (BIT_MASK_DARF_RC4_8822B << BIT_SHIFT_DARF_RC4_8822B) +#define BIT_CLEAR_DARF_RC4_8822B(x) ((x) & (~BITS_DARF_RC4_8822B)) +#define BIT_GET_DARF_RC4_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_8822B) & BIT_MASK_DARF_RC4_8822B) +#define BIT_SET_DARF_RC4_8822B(x, v) \ + (BIT_CLEAR_DARF_RC4_8822B(x) | BIT_DARF_RC4_8822B(v)) #define BIT_SHIFT_DARF_RC3_8822B 16 #define BIT_MASK_DARF_RC3_8822B 0x1f -#define BIT_DARF_RC3_8822B(x) (((x) & BIT_MASK_DARF_RC3_8822B) << BIT_SHIFT_DARF_RC3_8822B) -#define BIT_GET_DARF_RC3_8822B(x) (((x) >> BIT_SHIFT_DARF_RC3_8822B) & BIT_MASK_DARF_RC3_8822B) - - +#define BIT_DARF_RC3_8822B(x) \ + (((x) & BIT_MASK_DARF_RC3_8822B) << BIT_SHIFT_DARF_RC3_8822B) +#define BITS_DARF_RC3_8822B \ + (BIT_MASK_DARF_RC3_8822B << BIT_SHIFT_DARF_RC3_8822B) +#define BIT_CLEAR_DARF_RC3_8822B(x) ((x) & (~BITS_DARF_RC3_8822B)) +#define BIT_GET_DARF_RC3_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_8822B) & BIT_MASK_DARF_RC3_8822B) +#define BIT_SET_DARF_RC3_8822B(x, v) \ + (BIT_CLEAR_DARF_RC3_8822B(x) | BIT_DARF_RC3_8822B(v)) #define BIT_SHIFT_DARF_RC2_8822B 8 #define BIT_MASK_DARF_RC2_8822B 0x1f -#define BIT_DARF_RC2_8822B(x) (((x) & BIT_MASK_DARF_RC2_8822B) << BIT_SHIFT_DARF_RC2_8822B) -#define BIT_GET_DARF_RC2_8822B(x) (((x) >> BIT_SHIFT_DARF_RC2_8822B) & BIT_MASK_DARF_RC2_8822B) - - +#define BIT_DARF_RC2_8822B(x) \ + (((x) & BIT_MASK_DARF_RC2_8822B) << BIT_SHIFT_DARF_RC2_8822B) +#define BITS_DARF_RC2_8822B \ + (BIT_MASK_DARF_RC2_8822B << BIT_SHIFT_DARF_RC2_8822B) +#define BIT_CLEAR_DARF_RC2_8822B(x) ((x) & (~BITS_DARF_RC2_8822B)) +#define BIT_GET_DARF_RC2_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_8822B) & BIT_MASK_DARF_RC2_8822B) +#define BIT_SET_DARF_RC2_8822B(x, v) \ + (BIT_CLEAR_DARF_RC2_8822B(x) | BIT_DARF_RC2_8822B(v)) #define BIT_SHIFT_DARF_RC1_8822B 0 #define BIT_MASK_DARF_RC1_8822B 0x1f -#define BIT_DARF_RC1_8822B(x) (((x) & BIT_MASK_DARF_RC1_8822B) << BIT_SHIFT_DARF_RC1_8822B) -#define BIT_GET_DARF_RC1_8822B(x) (((x) >> BIT_SHIFT_DARF_RC1_8822B) & BIT_MASK_DARF_RC1_8822B) - - +#define BIT_DARF_RC1_8822B(x) \ + (((x) & BIT_MASK_DARF_RC1_8822B) << BIT_SHIFT_DARF_RC1_8822B) +#define BITS_DARF_RC1_8822B \ + (BIT_MASK_DARF_RC1_8822B << BIT_SHIFT_DARF_RC1_8822B) +#define BIT_CLEAR_DARF_RC1_8822B(x) ((x) & (~BITS_DARF_RC1_8822B)) +#define BIT_GET_DARF_RC1_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_8822B) & BIT_MASK_DARF_RC1_8822B) +#define BIT_SET_DARF_RC1_8822B(x, v) \ + (BIT_CLEAR_DARF_RC1_8822B(x) | BIT_DARF_RC1_8822B(v)) /* 2 REG_RARFRC_8822B */ #define BIT_SHIFT_RARF_RC8_8822B (56 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC8_8822B 0x1f -#define BIT_RARF_RC8_8822B(x) (((x) & BIT_MASK_RARF_RC8_8822B) << BIT_SHIFT_RARF_RC8_8822B) -#define BIT_GET_RARF_RC8_8822B(x) (((x) >> BIT_SHIFT_RARF_RC8_8822B) & BIT_MASK_RARF_RC8_8822B) - - +#define BIT_RARF_RC8_8822B(x) \ + (((x) & BIT_MASK_RARF_RC8_8822B) << BIT_SHIFT_RARF_RC8_8822B) +#define BITS_RARF_RC8_8822B \ + (BIT_MASK_RARF_RC8_8822B << BIT_SHIFT_RARF_RC8_8822B) +#define BIT_CLEAR_RARF_RC8_8822B(x) ((x) & (~BITS_RARF_RC8_8822B)) +#define BIT_GET_RARF_RC8_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC8_8822B) & BIT_MASK_RARF_RC8_8822B) +#define BIT_SET_RARF_RC8_8822B(x, v) \ + (BIT_CLEAR_RARF_RC8_8822B(x) | BIT_RARF_RC8_8822B(v)) #define BIT_SHIFT_RARF_RC7_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC7_8822B 0x1f -#define BIT_RARF_RC7_8822B(x) (((x) & BIT_MASK_RARF_RC7_8822B) << BIT_SHIFT_RARF_RC7_8822B) -#define BIT_GET_RARF_RC7_8822B(x) (((x) >> BIT_SHIFT_RARF_RC7_8822B) & BIT_MASK_RARF_RC7_8822B) - - +#define BIT_RARF_RC7_8822B(x) \ + (((x) & BIT_MASK_RARF_RC7_8822B) << BIT_SHIFT_RARF_RC7_8822B) +#define BITS_RARF_RC7_8822B \ + (BIT_MASK_RARF_RC7_8822B << BIT_SHIFT_RARF_RC7_8822B) +#define BIT_CLEAR_RARF_RC7_8822B(x) ((x) & (~BITS_RARF_RC7_8822B)) +#define BIT_GET_RARF_RC7_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC7_8822B) & BIT_MASK_RARF_RC7_8822B) +#define BIT_SET_RARF_RC7_8822B(x, v) \ + (BIT_CLEAR_RARF_RC7_8822B(x) | BIT_RARF_RC7_8822B(v)) #define BIT_SHIFT_RARF_RC6_8822B (40 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC6_8822B 0x1f -#define BIT_RARF_RC6_8822B(x) (((x) & BIT_MASK_RARF_RC6_8822B) << BIT_SHIFT_RARF_RC6_8822B) -#define BIT_GET_RARF_RC6_8822B(x) (((x) >> BIT_SHIFT_RARF_RC6_8822B) & BIT_MASK_RARF_RC6_8822B) - - +#define BIT_RARF_RC6_8822B(x) \ + (((x) & BIT_MASK_RARF_RC6_8822B) << BIT_SHIFT_RARF_RC6_8822B) +#define BITS_RARF_RC6_8822B \ + (BIT_MASK_RARF_RC6_8822B << BIT_SHIFT_RARF_RC6_8822B) +#define BIT_CLEAR_RARF_RC6_8822B(x) ((x) & (~BITS_RARF_RC6_8822B)) +#define BIT_GET_RARF_RC6_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC6_8822B) & BIT_MASK_RARF_RC6_8822B) +#define BIT_SET_RARF_RC6_8822B(x, v) \ + (BIT_CLEAR_RARF_RC6_8822B(x) | BIT_RARF_RC6_8822B(v)) #define BIT_SHIFT_RARF_RC5_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC5_8822B 0x1f -#define BIT_RARF_RC5_8822B(x) (((x) & BIT_MASK_RARF_RC5_8822B) << BIT_SHIFT_RARF_RC5_8822B) -#define BIT_GET_RARF_RC5_8822B(x) (((x) >> BIT_SHIFT_RARF_RC5_8822B) & BIT_MASK_RARF_RC5_8822B) - - +#define BIT_RARF_RC5_8822B(x) \ + (((x) & BIT_MASK_RARF_RC5_8822B) << BIT_SHIFT_RARF_RC5_8822B) +#define BITS_RARF_RC5_8822B \ + (BIT_MASK_RARF_RC5_8822B << BIT_SHIFT_RARF_RC5_8822B) +#define BIT_CLEAR_RARF_RC5_8822B(x) ((x) & (~BITS_RARF_RC5_8822B)) +#define BIT_GET_RARF_RC5_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC5_8822B) & BIT_MASK_RARF_RC5_8822B) +#define BIT_SET_RARF_RC5_8822B(x, v) \ + (BIT_CLEAR_RARF_RC5_8822B(x) | BIT_RARF_RC5_8822B(v)) #define BIT_SHIFT_RARF_RC4_8822B 24 #define BIT_MASK_RARF_RC4_8822B 0x1f -#define BIT_RARF_RC4_8822B(x) (((x) & BIT_MASK_RARF_RC4_8822B) << BIT_SHIFT_RARF_RC4_8822B) -#define BIT_GET_RARF_RC4_8822B(x) (((x) >> BIT_SHIFT_RARF_RC4_8822B) & BIT_MASK_RARF_RC4_8822B) - - +#define BIT_RARF_RC4_8822B(x) \ + (((x) & BIT_MASK_RARF_RC4_8822B) << BIT_SHIFT_RARF_RC4_8822B) +#define BITS_RARF_RC4_8822B \ + (BIT_MASK_RARF_RC4_8822B << BIT_SHIFT_RARF_RC4_8822B) +#define BIT_CLEAR_RARF_RC4_8822B(x) ((x) & (~BITS_RARF_RC4_8822B)) +#define BIT_GET_RARF_RC4_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC4_8822B) & BIT_MASK_RARF_RC4_8822B) +#define BIT_SET_RARF_RC4_8822B(x, v) \ + (BIT_CLEAR_RARF_RC4_8822B(x) | BIT_RARF_RC4_8822B(v)) #define BIT_SHIFT_RARF_RC3_8822B 16 #define BIT_MASK_RARF_RC3_8822B 0x1f -#define BIT_RARF_RC3_8822B(x) (((x) & BIT_MASK_RARF_RC3_8822B) << BIT_SHIFT_RARF_RC3_8822B) -#define BIT_GET_RARF_RC3_8822B(x) (((x) >> BIT_SHIFT_RARF_RC3_8822B) & BIT_MASK_RARF_RC3_8822B) - - +#define BIT_RARF_RC3_8822B(x) \ + (((x) & BIT_MASK_RARF_RC3_8822B) << BIT_SHIFT_RARF_RC3_8822B) +#define BITS_RARF_RC3_8822B \ + (BIT_MASK_RARF_RC3_8822B << BIT_SHIFT_RARF_RC3_8822B) +#define BIT_CLEAR_RARF_RC3_8822B(x) ((x) & (~BITS_RARF_RC3_8822B)) +#define BIT_GET_RARF_RC3_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC3_8822B) & BIT_MASK_RARF_RC3_8822B) +#define BIT_SET_RARF_RC3_8822B(x, v) \ + (BIT_CLEAR_RARF_RC3_8822B(x) | BIT_RARF_RC3_8822B(v)) #define BIT_SHIFT_RARF_RC2_8822B 8 #define BIT_MASK_RARF_RC2_8822B 0x1f -#define BIT_RARF_RC2_8822B(x) (((x) & BIT_MASK_RARF_RC2_8822B) << BIT_SHIFT_RARF_RC2_8822B) -#define BIT_GET_RARF_RC2_8822B(x) (((x) >> BIT_SHIFT_RARF_RC2_8822B) & BIT_MASK_RARF_RC2_8822B) - - +#define BIT_RARF_RC2_8822B(x) \ + (((x) & BIT_MASK_RARF_RC2_8822B) << BIT_SHIFT_RARF_RC2_8822B) +#define BITS_RARF_RC2_8822B \ + (BIT_MASK_RARF_RC2_8822B << BIT_SHIFT_RARF_RC2_8822B) +#define BIT_CLEAR_RARF_RC2_8822B(x) ((x) & (~BITS_RARF_RC2_8822B)) +#define BIT_GET_RARF_RC2_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC2_8822B) & BIT_MASK_RARF_RC2_8822B) +#define BIT_SET_RARF_RC2_8822B(x, v) \ + (BIT_CLEAR_RARF_RC2_8822B(x) | BIT_RARF_RC2_8822B(v)) #define BIT_SHIFT_RARF_RC1_8822B 0 #define BIT_MASK_RARF_RC1_8822B 0x1f -#define BIT_RARF_RC1_8822B(x) (((x) & BIT_MASK_RARF_RC1_8822B) << BIT_SHIFT_RARF_RC1_8822B) -#define BIT_GET_RARF_RC1_8822B(x) (((x) >> BIT_SHIFT_RARF_RC1_8822B) & BIT_MASK_RARF_RC1_8822B) - - +#define BIT_RARF_RC1_8822B(x) \ + (((x) & BIT_MASK_RARF_RC1_8822B) << BIT_SHIFT_RARF_RC1_8822B) +#define BITS_RARF_RC1_8822B \ + (BIT_MASK_RARF_RC1_8822B << BIT_SHIFT_RARF_RC1_8822B) +#define BIT_CLEAR_RARF_RC1_8822B(x) ((x) & (~BITS_RARF_RC1_8822B)) +#define BIT_GET_RARF_RC1_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC1_8822B) & BIT_MASK_RARF_RC1_8822B) +#define BIT_SET_RARF_RC1_8822B(x, v) \ + (BIT_CLEAR_RARF_RC1_8822B(x) | BIT_RARF_RC1_8822B(v)) /* 2 REG_RRSR_8822B */ #define BIT_SHIFT_RRSR_RSC_8822B 21 #define BIT_MASK_RRSR_RSC_8822B 0x3 -#define BIT_RRSR_RSC_8822B(x) (((x) & BIT_MASK_RRSR_RSC_8822B) << BIT_SHIFT_RRSR_RSC_8822B) -#define BIT_GET_RRSR_RSC_8822B(x) (((x) >> BIT_SHIFT_RRSR_RSC_8822B) & BIT_MASK_RRSR_RSC_8822B) - +#define BIT_RRSR_RSC_8822B(x) \ + (((x) & BIT_MASK_RRSR_RSC_8822B) << BIT_SHIFT_RRSR_RSC_8822B) +#define BITS_RRSR_RSC_8822B \ + (BIT_MASK_RRSR_RSC_8822B << BIT_SHIFT_RRSR_RSC_8822B) +#define BIT_CLEAR_RRSR_RSC_8822B(x) ((x) & (~BITS_RRSR_RSC_8822B)) +#define BIT_GET_RRSR_RSC_8822B(x) \ + (((x) >> BIT_SHIFT_RRSR_RSC_8822B) & BIT_MASK_RRSR_RSC_8822B) +#define BIT_SET_RRSR_RSC_8822B(x, v) \ + (BIT_CLEAR_RRSR_RSC_8822B(x) | BIT_RRSR_RSC_8822B(v)) #define BIT_RRSR_BW_8822B BIT(20) #define BIT_SHIFT_RRSC_BITMAP_8822B 0 #define BIT_MASK_RRSC_BITMAP_8822B 0xfffff -#define BIT_RRSC_BITMAP_8822B(x) (((x) & BIT_MASK_RRSC_BITMAP_8822B) << BIT_SHIFT_RRSC_BITMAP_8822B) -#define BIT_GET_RRSC_BITMAP_8822B(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8822B) & BIT_MASK_RRSC_BITMAP_8822B) - - +#define BIT_RRSC_BITMAP_8822B(x) \ + (((x) & BIT_MASK_RRSC_BITMAP_8822B) << BIT_SHIFT_RRSC_BITMAP_8822B) +#define BITS_RRSC_BITMAP_8822B \ + (BIT_MASK_RRSC_BITMAP_8822B << BIT_SHIFT_RRSC_BITMAP_8822B) +#define BIT_CLEAR_RRSC_BITMAP_8822B(x) ((x) & (~BITS_RRSC_BITMAP_8822B)) +#define BIT_GET_RRSC_BITMAP_8822B(x) \ + (((x) >> BIT_SHIFT_RRSC_BITMAP_8822B) & BIT_MASK_RRSC_BITMAP_8822B) +#define BIT_SET_RRSC_BITMAP_8822B(x, v) \ + (BIT_CLEAR_RRSC_BITMAP_8822B(x) | BIT_RRSC_BITMAP_8822B(v)) /* 2 REG_ARFR0_8822B */ #define BIT_SHIFT_ARFR0_V1_8822B 0 #define BIT_MASK_ARFR0_V1_8822B 0xffffffffffffffffL -#define BIT_ARFR0_V1_8822B(x) (((x) & BIT_MASK_ARFR0_V1_8822B) << BIT_SHIFT_ARFR0_V1_8822B) -#define BIT_GET_ARFR0_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR0_V1_8822B) & BIT_MASK_ARFR0_V1_8822B) - - +#define BIT_ARFR0_V1_8822B(x) \ + (((x) & BIT_MASK_ARFR0_V1_8822B) << BIT_SHIFT_ARFR0_V1_8822B) +#define BITS_ARFR0_V1_8822B \ + (BIT_MASK_ARFR0_V1_8822B << BIT_SHIFT_ARFR0_V1_8822B) +#define BIT_CLEAR_ARFR0_V1_8822B(x) ((x) & (~BITS_ARFR0_V1_8822B)) +#define BIT_GET_ARFR0_V1_8822B(x) \ + (((x) >> BIT_SHIFT_ARFR0_V1_8822B) & BIT_MASK_ARFR0_V1_8822B) +#define BIT_SET_ARFR0_V1_8822B(x, v) \ + (BIT_CLEAR_ARFR0_V1_8822B(x) | BIT_ARFR0_V1_8822B(v)) /* 2 REG_ARFR1_V1_8822B */ #define BIT_SHIFT_ARFR1_V1_8822B 0 #define BIT_MASK_ARFR1_V1_8822B 0xffffffffffffffffL -#define BIT_ARFR1_V1_8822B(x) (((x) & BIT_MASK_ARFR1_V1_8822B) << BIT_SHIFT_ARFR1_V1_8822B) -#define BIT_GET_ARFR1_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR1_V1_8822B) & BIT_MASK_ARFR1_V1_8822B) - - +#define BIT_ARFR1_V1_8822B(x) \ + (((x) & BIT_MASK_ARFR1_V1_8822B) << BIT_SHIFT_ARFR1_V1_8822B) +#define BITS_ARFR1_V1_8822B \ + (BIT_MASK_ARFR1_V1_8822B << BIT_SHIFT_ARFR1_V1_8822B) +#define BIT_CLEAR_ARFR1_V1_8822B(x) ((x) & (~BITS_ARFR1_V1_8822B)) +#define BIT_GET_ARFR1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_ARFR1_V1_8822B) & BIT_MASK_ARFR1_V1_8822B) +#define BIT_SET_ARFR1_V1_8822B(x, v) \ + (BIT_CLEAR_ARFR1_V1_8822B(x) | BIT_ARFR1_V1_8822B(v)) /* 2 REG_CCK_CHECK_8822B */ #define BIT_CHECK_CCK_EN_8822B BIT(7) @@ -5704,28 +8663,50 @@ #define BIT_SHIFT_AMPDU_MAX_TIME_8822B 0 #define BIT_MASK_AMPDU_MAX_TIME_8822B 0xff -#define BIT_AMPDU_MAX_TIME_8822B(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8822B) << BIT_SHIFT_AMPDU_MAX_TIME_8822B) -#define BIT_GET_AMPDU_MAX_TIME_8822B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822B) & BIT_MASK_AMPDU_MAX_TIME_8822B) - - +#define BIT_AMPDU_MAX_TIME_8822B(x) \ + (((x) & BIT_MASK_AMPDU_MAX_TIME_8822B) \ + << BIT_SHIFT_AMPDU_MAX_TIME_8822B) +#define BITS_AMPDU_MAX_TIME_8822B \ + (BIT_MASK_AMPDU_MAX_TIME_8822B << BIT_SHIFT_AMPDU_MAX_TIME_8822B) +#define BIT_CLEAR_AMPDU_MAX_TIME_8822B(x) ((x) & (~BITS_AMPDU_MAX_TIME_8822B)) +#define BIT_GET_AMPDU_MAX_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822B) & \ + BIT_MASK_AMPDU_MAX_TIME_8822B) +#define BIT_SET_AMPDU_MAX_TIME_8822B(x, v) \ + (BIT_CLEAR_AMPDU_MAX_TIME_8822B(x) | BIT_AMPDU_MAX_TIME_8822B(v)) /* 2 REG_BCNQ1_BDNY_V1_8822B */ #define BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B 0 #define BIT_MASK_BCNQ1_PGBNDY_V1_8822B 0xfff -#define BIT_BCNQ1_PGBNDY_V1_8822B(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) -#define BIT_GET_BCNQ1_PGBNDY_V1_8822B(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B) - - +#define BIT_BCNQ1_PGBNDY_V1_8822B(x) \ + (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B) \ + << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) +#define BITS_BCNQ1_PGBNDY_V1_8822B \ + (BIT_MASK_BCNQ1_PGBNDY_V1_8822B << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) +#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8822B(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8822B)) +#define BIT_GET_BCNQ1_PGBNDY_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) & \ + BIT_MASK_BCNQ1_PGBNDY_V1_8822B) +#define BIT_SET_BCNQ1_PGBNDY_V1_8822B(x, v) \ + (BIT_CLEAR_BCNQ1_PGBNDY_V1_8822B(x) | BIT_BCNQ1_PGBNDY_V1_8822B(v)) /* 2 REG_AMPDU_MAX_LENGTH_8822B */ #define BIT_SHIFT_AMPDU_MAX_LENGTH_8822B 0 #define BIT_MASK_AMPDU_MAX_LENGTH_8822B 0xffffffffL -#define BIT_AMPDU_MAX_LENGTH_8822B(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8822B) << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) -#define BIT_GET_AMPDU_MAX_LENGTH_8822B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) & BIT_MASK_AMPDU_MAX_LENGTH_8822B) - - +#define BIT_AMPDU_MAX_LENGTH_8822B(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8822B) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) +#define BITS_AMPDU_MAX_LENGTH_8822B \ + (BIT_MASK_AMPDU_MAX_LENGTH_8822B << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_8822B(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_8822B)) +#define BIT_GET_AMPDU_MAX_LENGTH_8822B(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) & \ + BIT_MASK_AMPDU_MAX_LENGTH_8822B) +#define BIT_SET_AMPDU_MAX_LENGTH_8822B(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_8822B(x) | BIT_AMPDU_MAX_LENGTH_8822B(v)) /* 2 REG_ACQ_STOP_8822B */ #define BIT_AC7Q_STOP_8822B BIT(7) @@ -5741,10 +8722,17 @@ #define BIT_SHIFT_R_NDPA_RATE_V1_8822B 0 #define BIT_MASK_R_NDPA_RATE_V1_8822B 0xff -#define BIT_R_NDPA_RATE_V1_8822B(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8822B) << BIT_SHIFT_R_NDPA_RATE_V1_8822B) -#define BIT_GET_R_NDPA_RATE_V1_8822B(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822B) & BIT_MASK_R_NDPA_RATE_V1_8822B) - - +#define BIT_R_NDPA_RATE_V1_8822B(x) \ + (((x) & BIT_MASK_R_NDPA_RATE_V1_8822B) \ + << BIT_SHIFT_R_NDPA_RATE_V1_8822B) +#define BITS_R_NDPA_RATE_V1_8822B \ + (BIT_MASK_R_NDPA_RATE_V1_8822B << BIT_SHIFT_R_NDPA_RATE_V1_8822B) +#define BIT_CLEAR_R_NDPA_RATE_V1_8822B(x) ((x) & (~BITS_R_NDPA_RATE_V1_8822B)) +#define BIT_GET_R_NDPA_RATE_V1_8822B(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822B) & \ + BIT_MASK_R_NDPA_RATE_V1_8822B) +#define BIT_SET_R_NDPA_RATE_V1_8822B(x, v) \ + (BIT_CLEAR_R_NDPA_RATE_V1_8822B(x) | BIT_R_NDPA_RATE_V1_8822B(v)) /* 2 REG_TX_HANG_CTRL_8822B */ #define BIT_R_EN_GNT_BT_AWAKE_8822B BIT(3) @@ -5757,230 +8745,437 @@ #define BIT_SHIFT_BW_SIGTA_8822B 3 #define BIT_MASK_BW_SIGTA_8822B 0x3 -#define BIT_BW_SIGTA_8822B(x) (((x) & BIT_MASK_BW_SIGTA_8822B) << BIT_SHIFT_BW_SIGTA_8822B) -#define BIT_GET_BW_SIGTA_8822B(x) (((x) >> BIT_SHIFT_BW_SIGTA_8822B) & BIT_MASK_BW_SIGTA_8822B) - +#define BIT_BW_SIGTA_8822B(x) \ + (((x) & BIT_MASK_BW_SIGTA_8822B) << BIT_SHIFT_BW_SIGTA_8822B) +#define BITS_BW_SIGTA_8822B \ + (BIT_MASK_BW_SIGTA_8822B << BIT_SHIFT_BW_SIGTA_8822B) +#define BIT_CLEAR_BW_SIGTA_8822B(x) ((x) & (~BITS_BW_SIGTA_8822B)) +#define BIT_GET_BW_SIGTA_8822B(x) \ + (((x) >> BIT_SHIFT_BW_SIGTA_8822B) & BIT_MASK_BW_SIGTA_8822B) +#define BIT_SET_BW_SIGTA_8822B(x, v) \ + (BIT_CLEAR_BW_SIGTA_8822B(x) | BIT_BW_SIGTA_8822B(v)) #define BIT_EN_BAR_SIGTA_8822B BIT(2) #define BIT_SHIFT_R_NDPA_BW_8822B 0 #define BIT_MASK_R_NDPA_BW_8822B 0x3 -#define BIT_R_NDPA_BW_8822B(x) (((x) & BIT_MASK_R_NDPA_BW_8822B) << BIT_SHIFT_R_NDPA_BW_8822B) -#define BIT_GET_R_NDPA_BW_8822B(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8822B) & BIT_MASK_R_NDPA_BW_8822B) - - +#define BIT_R_NDPA_BW_8822B(x) \ + (((x) & BIT_MASK_R_NDPA_BW_8822B) << BIT_SHIFT_R_NDPA_BW_8822B) +#define BITS_R_NDPA_BW_8822B \ + (BIT_MASK_R_NDPA_BW_8822B << BIT_SHIFT_R_NDPA_BW_8822B) +#define BIT_CLEAR_R_NDPA_BW_8822B(x) ((x) & (~BITS_R_NDPA_BW_8822B)) +#define BIT_GET_R_NDPA_BW_8822B(x) \ + (((x) >> BIT_SHIFT_R_NDPA_BW_8822B) & BIT_MASK_R_NDPA_BW_8822B) +#define BIT_SET_R_NDPA_BW_8822B(x, v) \ + (BIT_CLEAR_R_NDPA_BW_8822B(x) | BIT_R_NDPA_BW_8822B(v)) /* 2 REG_RD_RESP_PKT_TH_8822B */ #define BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B 0 #define BIT_MASK_RD_RESP_PKT_TH_V1_8822B 0x3f -#define BIT_RD_RESP_PKT_TH_V1_8822B(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) -#define BIT_GET_RD_RESP_PKT_TH_V1_8822B(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B) - - +#define BIT_RD_RESP_PKT_TH_V1_8822B(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B) \ + << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) +#define BITS_RD_RESP_PKT_TH_V1_8822B \ + (BIT_MASK_RD_RESP_PKT_TH_V1_8822B << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8822B(x) \ + ((x) & (~BITS_RD_RESP_PKT_TH_V1_8822B)) +#define BIT_GET_RD_RESP_PKT_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) & \ + BIT_MASK_RD_RESP_PKT_TH_V1_8822B) +#define BIT_SET_RD_RESP_PKT_TH_V1_8822B(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH_V1_8822B(x) | BIT_RD_RESP_PKT_TH_V1_8822B(v)) /* 2 REG_CMDQ_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B 25 #define BIT_MASK_QUEUEMACID_CMDQ_V1_8822B 0x7f -#define BIT_QUEUEMACID_CMDQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B) << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) -#define BIT_GET_QUEUEMACID_CMDQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B) - - +#define BIT_QUEUEMACID_CMDQ_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) +#define BITS_QUEUEMACID_CMDQ_V1_8822B \ + (BIT_MASK_QUEUEMACID_CMDQ_V1_8822B \ + << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_CMDQ_V1_8822B)) +#define BIT_GET_QUEUEMACID_CMDQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) & \ + BIT_MASK_QUEUEMACID_CMDQ_V1_8822B) +#define BIT_SET_QUEUEMACID_CMDQ_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822B(x) | \ + BIT_QUEUEMACID_CMDQ_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B 23 #define BIT_MASK_QUEUEAC_CMDQ_V1_8822B 0x3 -#define BIT_QUEUEAC_CMDQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B) << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) -#define BIT_GET_QUEUEAC_CMDQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B) - +#define BIT_QUEUEAC_CMDQ_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B) \ + << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) +#define BITS_QUEUEAC_CMDQ_V1_8822B \ + (BIT_MASK_QUEUEAC_CMDQ_V1_8822B << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) +#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8822B)) +#define BIT_GET_QUEUEAC_CMDQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) & \ + BIT_MASK_QUEUEAC_CMDQ_V1_8822B) +#define BIT_SET_QUEUEAC_CMDQ_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_CMDQ_V1_8822B(x) | BIT_QUEUEAC_CMDQ_V1_8822B(v)) #define BIT_TIDEMPTY_CMDQ_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B 11 #define BIT_MASK_TAIL_PKT_CMDQ_V2_8822B 0x7ff -#define BIT_TAIL_PKT_CMDQ_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) -#define BIT_GET_TAIL_PKT_CMDQ_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B) - - +#define BIT_TAIL_PKT_CMDQ_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) +#define BITS_TAIL_PKT_CMDQ_V2_8822B \ + (BIT_MASK_TAIL_PKT_CMDQ_V2_8822B << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8822B(x) \ + ((x) & (~BITS_TAIL_PKT_CMDQ_V2_8822B)) +#define BIT_GET_TAIL_PKT_CMDQ_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) & \ + BIT_MASK_TAIL_PKT_CMDQ_V2_8822B) +#define BIT_SET_TAIL_PKT_CMDQ_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_CMDQ_V2_8822B(x) | BIT_TAIL_PKT_CMDQ_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B 0 #define BIT_MASK_HEAD_PKT_CMDQ_V1_8822B 0x7ff -#define BIT_HEAD_PKT_CMDQ_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) -#define BIT_GET_HEAD_PKT_CMDQ_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) - - +#define BIT_HEAD_PKT_CMDQ_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) +#define BITS_HEAD_PKT_CMDQ_V1_8822B \ + (BIT_MASK_HEAD_PKT_CMDQ_V1_8822B << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822B(x) \ + ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8822B)) +#define BIT_GET_HEAD_PKT_CMDQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) & \ + BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) +#define BIT_SET_HEAD_PKT_CMDQ_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822B(x) | BIT_HEAD_PKT_CMDQ_V1_8822B(v)) /* 2 REG_Q4_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q4_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q4_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q4_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) -#define BIT_GET_QUEUEMACID_Q4_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) & BIT_MASK_QUEUEMACID_Q4_V1_8822B) - - +#define BIT_QUEUEMACID_Q4_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) +#define BITS_QUEUEMACID_Q4_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q4_V1_8822B << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q4_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q4_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q4_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q4_V1_8822B) +#define BIT_SET_QUEUEMACID_Q4_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q4_V1_8822B(x) | BIT_QUEUEMACID_Q4_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q4_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q4_V1_8822B 0x3 -#define BIT_QUEUEAC_Q4_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8822B) << BIT_SHIFT_QUEUEAC_Q4_V1_8822B) -#define BIT_GET_QUEUEAC_Q4_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822B) & BIT_MASK_QUEUEAC_Q4_V1_8822B) - +#define BIT_QUEUEAC_Q4_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q4_V1_8822B) << BIT_SHIFT_QUEUEAC_Q4_V1_8822B) +#define BITS_QUEUEAC_Q4_V1_8822B \ + (BIT_MASK_QUEUEAC_Q4_V1_8822B << BIT_SHIFT_QUEUEAC_Q4_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q4_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8822B)) +#define BIT_GET_QUEUEAC_Q4_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822B) & BIT_MASK_QUEUEAC_Q4_V1_8822B) +#define BIT_SET_QUEUEAC_Q4_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q4_V1_8822B(x) | BIT_QUEUEAC_Q4_V1_8822B(v)) #define BIT_TIDEMPTY_Q4_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q4_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q4_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q4_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) -#define BIT_GET_TAIL_PKT_Q4_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) & BIT_MASK_TAIL_PKT_Q4_V2_8822B) - - +#define BIT_TAIL_PKT_Q4_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) +#define BITS_TAIL_PKT_Q4_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q4_V2_8822B << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q4_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q4_V2_8822B) +#define BIT_SET_TAIL_PKT_Q4_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2_8822B(x) | BIT_TAIL_PKT_Q4_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q4_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q4_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q4_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) -#define BIT_GET_HEAD_PKT_Q4_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) & BIT_MASK_HEAD_PKT_Q4_V1_8822B) - - +#define BIT_HEAD_PKT_Q4_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) +#define BITS_HEAD_PKT_Q4_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q4_V1_8822B << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q4_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q4_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q4_V1_8822B) +#define BIT_SET_HEAD_PKT_Q4_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q4_V1_8822B(x) | BIT_HEAD_PKT_Q4_V1_8822B(v)) /* 2 REG_Q5_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q5_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q5_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q5_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) -#define BIT_GET_QUEUEMACID_Q5_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) & BIT_MASK_QUEUEMACID_Q5_V1_8822B) - - +#define BIT_QUEUEMACID_Q5_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) +#define BITS_QUEUEMACID_Q5_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q5_V1_8822B << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q5_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q5_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q5_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q5_V1_8822B) +#define BIT_SET_QUEUEMACID_Q5_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q5_V1_8822B(x) | BIT_QUEUEMACID_Q5_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q5_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q5_V1_8822B 0x3 -#define BIT_QUEUEAC_Q5_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8822B) << BIT_SHIFT_QUEUEAC_Q5_V1_8822B) -#define BIT_GET_QUEUEAC_Q5_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822B) & BIT_MASK_QUEUEAC_Q5_V1_8822B) - +#define BIT_QUEUEAC_Q5_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q5_V1_8822B) << BIT_SHIFT_QUEUEAC_Q5_V1_8822B) +#define BITS_QUEUEAC_Q5_V1_8822B \ + (BIT_MASK_QUEUEAC_Q5_V1_8822B << BIT_SHIFT_QUEUEAC_Q5_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q5_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8822B)) +#define BIT_GET_QUEUEAC_Q5_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822B) & BIT_MASK_QUEUEAC_Q5_V1_8822B) +#define BIT_SET_QUEUEAC_Q5_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q5_V1_8822B(x) | BIT_QUEUEAC_Q5_V1_8822B(v)) #define BIT_TIDEMPTY_Q5_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q5_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q5_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q5_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) -#define BIT_GET_TAIL_PKT_Q5_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) & BIT_MASK_TAIL_PKT_Q5_V2_8822B) - - +#define BIT_TAIL_PKT_Q5_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) +#define BITS_TAIL_PKT_Q5_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q5_V2_8822B << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q5_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q5_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q5_V2_8822B) +#define BIT_SET_TAIL_PKT_Q5_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q5_V2_8822B(x) | BIT_TAIL_PKT_Q5_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q5_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q5_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q5_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) -#define BIT_GET_HEAD_PKT_Q5_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) & BIT_MASK_HEAD_PKT_Q5_V1_8822B) - - +#define BIT_HEAD_PKT_Q5_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) +#define BITS_HEAD_PKT_Q5_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q5_V1_8822B << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q5_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q5_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q5_V1_8822B) +#define BIT_SET_HEAD_PKT_Q5_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q5_V1_8822B(x) | BIT_HEAD_PKT_Q5_V1_8822B(v)) /* 2 REG_Q6_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q6_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q6_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q6_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) -#define BIT_GET_QUEUEMACID_Q6_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) & BIT_MASK_QUEUEMACID_Q6_V1_8822B) - - +#define BIT_QUEUEMACID_Q6_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) +#define BITS_QUEUEMACID_Q6_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q6_V1_8822B << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q6_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q6_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q6_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q6_V1_8822B) +#define BIT_SET_QUEUEMACID_Q6_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q6_V1_8822B(x) | BIT_QUEUEMACID_Q6_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q6_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q6_V1_8822B 0x3 -#define BIT_QUEUEAC_Q6_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8822B) << BIT_SHIFT_QUEUEAC_Q6_V1_8822B) -#define BIT_GET_QUEUEAC_Q6_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822B) & BIT_MASK_QUEUEAC_Q6_V1_8822B) - +#define BIT_QUEUEAC_Q6_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q6_V1_8822B) << BIT_SHIFT_QUEUEAC_Q6_V1_8822B) +#define BITS_QUEUEAC_Q6_V1_8822B \ + (BIT_MASK_QUEUEAC_Q6_V1_8822B << BIT_SHIFT_QUEUEAC_Q6_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q6_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8822B)) +#define BIT_GET_QUEUEAC_Q6_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822B) & BIT_MASK_QUEUEAC_Q6_V1_8822B) +#define BIT_SET_QUEUEAC_Q6_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q6_V1_8822B(x) | BIT_QUEUEAC_Q6_V1_8822B(v)) #define BIT_TIDEMPTY_Q6_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q6_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q6_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q6_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) -#define BIT_GET_TAIL_PKT_Q6_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) & BIT_MASK_TAIL_PKT_Q6_V2_8822B) - - +#define BIT_TAIL_PKT_Q6_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) +#define BITS_TAIL_PKT_Q6_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q6_V2_8822B << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q6_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q6_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q6_V2_8822B) +#define BIT_SET_TAIL_PKT_Q6_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q6_V2_8822B(x) | BIT_TAIL_PKT_Q6_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q6_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q6_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q6_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) -#define BIT_GET_HEAD_PKT_Q6_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) & BIT_MASK_HEAD_PKT_Q6_V1_8822B) - - +#define BIT_HEAD_PKT_Q6_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) +#define BITS_HEAD_PKT_Q6_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q6_V1_8822B << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q6_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q6_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q6_V1_8822B) +#define BIT_SET_HEAD_PKT_Q6_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q6_V1_8822B(x) | BIT_HEAD_PKT_Q6_V1_8822B(v)) /* 2 REG_Q7_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q7_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q7_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q7_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) -#define BIT_GET_QUEUEMACID_Q7_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) & BIT_MASK_QUEUEMACID_Q7_V1_8822B) - - +#define BIT_QUEUEMACID_Q7_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) +#define BITS_QUEUEMACID_Q7_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q7_V1_8822B << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q7_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q7_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q7_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q7_V1_8822B) +#define BIT_SET_QUEUEMACID_Q7_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q7_V1_8822B(x) | BIT_QUEUEMACID_Q7_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q7_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q7_V1_8822B 0x3 -#define BIT_QUEUEAC_Q7_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8822B) << BIT_SHIFT_QUEUEAC_Q7_V1_8822B) -#define BIT_GET_QUEUEAC_Q7_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822B) & BIT_MASK_QUEUEAC_Q7_V1_8822B) - +#define BIT_QUEUEAC_Q7_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q7_V1_8822B) << BIT_SHIFT_QUEUEAC_Q7_V1_8822B) +#define BITS_QUEUEAC_Q7_V1_8822B \ + (BIT_MASK_QUEUEAC_Q7_V1_8822B << BIT_SHIFT_QUEUEAC_Q7_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q7_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8822B)) +#define BIT_GET_QUEUEAC_Q7_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822B) & BIT_MASK_QUEUEAC_Q7_V1_8822B) +#define BIT_SET_QUEUEAC_Q7_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q7_V1_8822B(x) | BIT_QUEUEAC_Q7_V1_8822B(v)) #define BIT_TIDEMPTY_Q7_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q7_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q7_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q7_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) -#define BIT_GET_TAIL_PKT_Q7_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) & BIT_MASK_TAIL_PKT_Q7_V2_8822B) - - +#define BIT_TAIL_PKT_Q7_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) +#define BITS_TAIL_PKT_Q7_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q7_V2_8822B << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q7_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q7_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q7_V2_8822B) +#define BIT_SET_TAIL_PKT_Q7_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q7_V2_8822B(x) | BIT_TAIL_PKT_Q7_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q7_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q7_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q7_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) -#define BIT_GET_HEAD_PKT_Q7_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) & BIT_MASK_HEAD_PKT_Q7_V1_8822B) - - +#define BIT_HEAD_PKT_Q7_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) +#define BITS_HEAD_PKT_Q7_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q7_V1_8822B << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q7_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q7_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q7_V1_8822B) +#define BIT_SET_HEAD_PKT_Q7_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q7_V1_8822B(x) | BIT_HEAD_PKT_Q7_V1_8822B(v)) /* 2 REG_WMAC_LBK_BUF_HD_V1_8822B */ #define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B 0 #define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B 0xfff -#define BIT_WMAC_LBK_BUF_HEAD_V1_8822B(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) -#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822B(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B) - - +#define BIT_WMAC_LBK_BUF_HEAD_V1_8822B(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B) \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) +#define BITS_WMAC_LBK_BUF_HEAD_V1_8822B \ + (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822B(x) \ + ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8822B)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) & \ + BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8822B(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822B(x) | \ + BIT_WMAC_LBK_BUF_HEAD_V1_8822B(v)) /* 2 REG_MGQ_BDNY_V1_8822B */ #define BIT_SHIFT_MGQ_PGBNDY_V1_8822B 0 #define BIT_MASK_MGQ_PGBNDY_V1_8822B 0xfff -#define BIT_MGQ_PGBNDY_V1_8822B(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8822B) << BIT_SHIFT_MGQ_PGBNDY_V1_8822B) -#define BIT_GET_MGQ_PGBNDY_V1_8822B(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822B) & BIT_MASK_MGQ_PGBNDY_V1_8822B) - - +#define BIT_MGQ_PGBNDY_V1_8822B(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V1_8822B) << BIT_SHIFT_MGQ_PGBNDY_V1_8822B) +#define BITS_MGQ_PGBNDY_V1_8822B \ + (BIT_MASK_MGQ_PGBNDY_V1_8822B << BIT_SHIFT_MGQ_PGBNDY_V1_8822B) +#define BIT_CLEAR_MGQ_PGBNDY_V1_8822B(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8822B)) +#define BIT_GET_MGQ_PGBNDY_V1_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822B) & BIT_MASK_MGQ_PGBNDY_V1_8822B) +#define BIT_SET_MGQ_PGBNDY_V1_8822B(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V1_8822B(x) | BIT_MGQ_PGBNDY_V1_8822B(v)) /* 2 REG_TXRPT_CTRL_8822B */ #define BIT_SHIFT_TRXRPT_TIMER_TH_8822B 24 #define BIT_MASK_TRXRPT_TIMER_TH_8822B 0xff -#define BIT_TRXRPT_TIMER_TH_8822B(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8822B) << BIT_SHIFT_TRXRPT_TIMER_TH_8822B) -#define BIT_GET_TRXRPT_TIMER_TH_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822B) & BIT_MASK_TRXRPT_TIMER_TH_8822B) - - +#define BIT_TRXRPT_TIMER_TH_8822B(x) \ + (((x) & BIT_MASK_TRXRPT_TIMER_TH_8822B) \ + << BIT_SHIFT_TRXRPT_TIMER_TH_8822B) +#define BITS_TRXRPT_TIMER_TH_8822B \ + (BIT_MASK_TRXRPT_TIMER_TH_8822B << BIT_SHIFT_TRXRPT_TIMER_TH_8822B) +#define BIT_CLEAR_TRXRPT_TIMER_TH_8822B(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8822B)) +#define BIT_GET_TRXRPT_TIMER_TH_8822B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822B) & \ + BIT_MASK_TRXRPT_TIMER_TH_8822B) +#define BIT_SET_TRXRPT_TIMER_TH_8822B(x, v) \ + (BIT_CLEAR_TRXRPT_TIMER_TH_8822B(x) | BIT_TRXRPT_TIMER_TH_8822B(v)) #define BIT_SHIFT_TRXRPT_LEN_TH_8822B 16 #define BIT_MASK_TRXRPT_LEN_TH_8822B 0xff -#define BIT_TRXRPT_LEN_TH_8822B(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8822B) << BIT_SHIFT_TRXRPT_LEN_TH_8822B) -#define BIT_GET_TRXRPT_LEN_TH_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822B) & BIT_MASK_TRXRPT_LEN_TH_8822B) - - +#define BIT_TRXRPT_LEN_TH_8822B(x) \ + (((x) & BIT_MASK_TRXRPT_LEN_TH_8822B) << BIT_SHIFT_TRXRPT_LEN_TH_8822B) +#define BITS_TRXRPT_LEN_TH_8822B \ + (BIT_MASK_TRXRPT_LEN_TH_8822B << BIT_SHIFT_TRXRPT_LEN_TH_8822B) +#define BIT_CLEAR_TRXRPT_LEN_TH_8822B(x) ((x) & (~BITS_TRXRPT_LEN_TH_8822B)) +#define BIT_GET_TRXRPT_LEN_TH_8822B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822B) & BIT_MASK_TRXRPT_LEN_TH_8822B) +#define BIT_SET_TRXRPT_LEN_TH_8822B(x, v) \ + (BIT_CLEAR_TRXRPT_LEN_TH_8822B(x) | BIT_TRXRPT_LEN_TH_8822B(v)) #define BIT_SHIFT_TRXRPT_READ_PTR_8822B 8 #define BIT_MASK_TRXRPT_READ_PTR_8822B 0xff -#define BIT_TRXRPT_READ_PTR_8822B(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8822B) << BIT_SHIFT_TRXRPT_READ_PTR_8822B) -#define BIT_GET_TRXRPT_READ_PTR_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822B) & BIT_MASK_TRXRPT_READ_PTR_8822B) - - +#define BIT_TRXRPT_READ_PTR_8822B(x) \ + (((x) & BIT_MASK_TRXRPT_READ_PTR_8822B) \ + << BIT_SHIFT_TRXRPT_READ_PTR_8822B) +#define BITS_TRXRPT_READ_PTR_8822B \ + (BIT_MASK_TRXRPT_READ_PTR_8822B << BIT_SHIFT_TRXRPT_READ_PTR_8822B) +#define BIT_CLEAR_TRXRPT_READ_PTR_8822B(x) ((x) & (~BITS_TRXRPT_READ_PTR_8822B)) +#define BIT_GET_TRXRPT_READ_PTR_8822B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822B) & \ + BIT_MASK_TRXRPT_READ_PTR_8822B) +#define BIT_SET_TRXRPT_READ_PTR_8822B(x, v) \ + (BIT_CLEAR_TRXRPT_READ_PTR_8822B(x) | BIT_TRXRPT_READ_PTR_8822B(v)) #define BIT_SHIFT_TRXRPT_WRITE_PTR_8822B 0 #define BIT_MASK_TRXRPT_WRITE_PTR_8822B 0xff -#define BIT_TRXRPT_WRITE_PTR_8822B(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822B) << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) -#define BIT_GET_TRXRPT_WRITE_PTR_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) & BIT_MASK_TRXRPT_WRITE_PTR_8822B) - - +#define BIT_TRXRPT_WRITE_PTR_8822B(x) \ + (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822B) \ + << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) +#define BITS_TRXRPT_WRITE_PTR_8822B \ + (BIT_MASK_TRXRPT_WRITE_PTR_8822B << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) +#define BIT_CLEAR_TRXRPT_WRITE_PTR_8822B(x) \ + ((x) & (~BITS_TRXRPT_WRITE_PTR_8822B)) +#define BIT_GET_TRXRPT_WRITE_PTR_8822B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) & \ + BIT_MASK_TRXRPT_WRITE_PTR_8822B) +#define BIT_SET_TRXRPT_WRITE_PTR_8822B(x, v) \ + (BIT_CLEAR_TRXRPT_WRITE_PTR_8822B(x) | BIT_TRXRPT_WRITE_PTR_8822B(v)) /* 2 REG_INIRTS_RATE_SEL_8822B */ #define BIT_LEAG_RTS_BW_DUP_8822B BIT(5) @@ -5989,113 +9184,205 @@ #define BIT_SHIFT_BASIC_CFEND_RATE_8822B 0 #define BIT_MASK_BASIC_CFEND_RATE_8822B 0x1f -#define BIT_BASIC_CFEND_RATE_8822B(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8822B) << BIT_SHIFT_BASIC_CFEND_RATE_8822B) -#define BIT_GET_BASIC_CFEND_RATE_8822B(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822B) & BIT_MASK_BASIC_CFEND_RATE_8822B) - - +#define BIT_BASIC_CFEND_RATE_8822B(x) \ + (((x) & BIT_MASK_BASIC_CFEND_RATE_8822B) \ + << BIT_SHIFT_BASIC_CFEND_RATE_8822B) +#define BITS_BASIC_CFEND_RATE_8822B \ + (BIT_MASK_BASIC_CFEND_RATE_8822B << BIT_SHIFT_BASIC_CFEND_RATE_8822B) +#define BIT_CLEAR_BASIC_CFEND_RATE_8822B(x) \ + ((x) & (~BITS_BASIC_CFEND_RATE_8822B)) +#define BIT_GET_BASIC_CFEND_RATE_8822B(x) \ + (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822B) & \ + BIT_MASK_BASIC_CFEND_RATE_8822B) +#define BIT_SET_BASIC_CFEND_RATE_8822B(x, v) \ + (BIT_CLEAR_BASIC_CFEND_RATE_8822B(x) | BIT_BASIC_CFEND_RATE_8822B(v)) /* 2 REG_STBC_CFEND_RATE_8822B */ #define BIT_SHIFT_STBC_CFEND_RATE_8822B 0 #define BIT_MASK_STBC_CFEND_RATE_8822B 0x1f -#define BIT_STBC_CFEND_RATE_8822B(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8822B) << BIT_SHIFT_STBC_CFEND_RATE_8822B) -#define BIT_GET_STBC_CFEND_RATE_8822B(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822B) & BIT_MASK_STBC_CFEND_RATE_8822B) - - +#define BIT_STBC_CFEND_RATE_8822B(x) \ + (((x) & BIT_MASK_STBC_CFEND_RATE_8822B) \ + << BIT_SHIFT_STBC_CFEND_RATE_8822B) +#define BITS_STBC_CFEND_RATE_8822B \ + (BIT_MASK_STBC_CFEND_RATE_8822B << BIT_SHIFT_STBC_CFEND_RATE_8822B) +#define BIT_CLEAR_STBC_CFEND_RATE_8822B(x) ((x) & (~BITS_STBC_CFEND_RATE_8822B)) +#define BIT_GET_STBC_CFEND_RATE_8822B(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822B) & \ + BIT_MASK_STBC_CFEND_RATE_8822B) +#define BIT_SET_STBC_CFEND_RATE_8822B(x, v) \ + (BIT_CLEAR_STBC_CFEND_RATE_8822B(x) | BIT_STBC_CFEND_RATE_8822B(v)) /* 2 REG_DATA_SC_8822B */ #define BIT_SHIFT_TXSC_40M_8822B 4 #define BIT_MASK_TXSC_40M_8822B 0xf -#define BIT_TXSC_40M_8822B(x) (((x) & BIT_MASK_TXSC_40M_8822B) << BIT_SHIFT_TXSC_40M_8822B) -#define BIT_GET_TXSC_40M_8822B(x) (((x) >> BIT_SHIFT_TXSC_40M_8822B) & BIT_MASK_TXSC_40M_8822B) - - +#define BIT_TXSC_40M_8822B(x) \ + (((x) & BIT_MASK_TXSC_40M_8822B) << BIT_SHIFT_TXSC_40M_8822B) +#define BITS_TXSC_40M_8822B \ + (BIT_MASK_TXSC_40M_8822B << BIT_SHIFT_TXSC_40M_8822B) +#define BIT_CLEAR_TXSC_40M_8822B(x) ((x) & (~BITS_TXSC_40M_8822B)) +#define BIT_GET_TXSC_40M_8822B(x) \ + (((x) >> BIT_SHIFT_TXSC_40M_8822B) & BIT_MASK_TXSC_40M_8822B) +#define BIT_SET_TXSC_40M_8822B(x, v) \ + (BIT_CLEAR_TXSC_40M_8822B(x) | BIT_TXSC_40M_8822B(v)) #define BIT_SHIFT_TXSC_20M_8822B 0 #define BIT_MASK_TXSC_20M_8822B 0xf -#define BIT_TXSC_20M_8822B(x) (((x) & BIT_MASK_TXSC_20M_8822B) << BIT_SHIFT_TXSC_20M_8822B) -#define BIT_GET_TXSC_20M_8822B(x) (((x) >> BIT_SHIFT_TXSC_20M_8822B) & BIT_MASK_TXSC_20M_8822B) - - +#define BIT_TXSC_20M_8822B(x) \ + (((x) & BIT_MASK_TXSC_20M_8822B) << BIT_SHIFT_TXSC_20M_8822B) +#define BITS_TXSC_20M_8822B \ + (BIT_MASK_TXSC_20M_8822B << BIT_SHIFT_TXSC_20M_8822B) +#define BIT_CLEAR_TXSC_20M_8822B(x) ((x) & (~BITS_TXSC_20M_8822B)) +#define BIT_GET_TXSC_20M_8822B(x) \ + (((x) >> BIT_SHIFT_TXSC_20M_8822B) & BIT_MASK_TXSC_20M_8822B) +#define BIT_SET_TXSC_20M_8822B(x, v) \ + (BIT_CLEAR_TXSC_20M_8822B(x) | BIT_TXSC_20M_8822B(v)) /* 2 REG_MACID_SLEEP3_8822B */ #define BIT_SHIFT_MACID127_96_PKTSLEEP_8822B 0 #define BIT_MASK_MACID127_96_PKTSLEEP_8822B 0xffffffffL -#define BIT_MACID127_96_PKTSLEEP_8822B(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822B) << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) -#define BIT_GET_MACID127_96_PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) & BIT_MASK_MACID127_96_PKTSLEEP_8822B) - - +#define BIT_MACID127_96_PKTSLEEP_8822B(x) \ + (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822B) \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) +#define BITS_MACID127_96_PKTSLEEP_8822B \ + (BIT_MASK_MACID127_96_PKTSLEEP_8822B \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) +#define BIT_CLEAR_MACID127_96_PKTSLEEP_8822B(x) \ + ((x) & (~BITS_MACID127_96_PKTSLEEP_8822B)) +#define BIT_GET_MACID127_96_PKTSLEEP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) & \ + BIT_MASK_MACID127_96_PKTSLEEP_8822B) +#define BIT_SET_MACID127_96_PKTSLEEP_8822B(x, v) \ + (BIT_CLEAR_MACID127_96_PKTSLEEP_8822B(x) | \ + BIT_MACID127_96_PKTSLEEP_8822B(v)) /* 2 REG_MACID_SLEEP1_8822B */ #define BIT_SHIFT_MACID63_32_PKTSLEEP_8822B 0 #define BIT_MASK_MACID63_32_PKTSLEEP_8822B 0xffffffffL -#define BIT_MACID63_32_PKTSLEEP_8822B(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822B) << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) -#define BIT_GET_MACID63_32_PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) & BIT_MASK_MACID63_32_PKTSLEEP_8822B) - - +#define BIT_MACID63_32_PKTSLEEP_8822B(x) \ + (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822B) \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) +#define BITS_MACID63_32_PKTSLEEP_8822B \ + (BIT_MASK_MACID63_32_PKTSLEEP_8822B \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) +#define BIT_CLEAR_MACID63_32_PKTSLEEP_8822B(x) \ + ((x) & (~BITS_MACID63_32_PKTSLEEP_8822B)) +#define BIT_GET_MACID63_32_PKTSLEEP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) & \ + BIT_MASK_MACID63_32_PKTSLEEP_8822B) +#define BIT_SET_MACID63_32_PKTSLEEP_8822B(x, v) \ + (BIT_CLEAR_MACID63_32_PKTSLEEP_8822B(x) | \ + BIT_MACID63_32_PKTSLEEP_8822B(v)) /* 2 REG_ARFR2_V1_8822B */ #define BIT_SHIFT_ARFR2_V1_8822B 0 #define BIT_MASK_ARFR2_V1_8822B 0xffffffffffffffffL -#define BIT_ARFR2_V1_8822B(x) (((x) & BIT_MASK_ARFR2_V1_8822B) << BIT_SHIFT_ARFR2_V1_8822B) -#define BIT_GET_ARFR2_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR2_V1_8822B) & BIT_MASK_ARFR2_V1_8822B) - - +#define BIT_ARFR2_V1_8822B(x) \ + (((x) & BIT_MASK_ARFR2_V1_8822B) << BIT_SHIFT_ARFR2_V1_8822B) +#define BITS_ARFR2_V1_8822B \ + (BIT_MASK_ARFR2_V1_8822B << BIT_SHIFT_ARFR2_V1_8822B) +#define BIT_CLEAR_ARFR2_V1_8822B(x) ((x) & (~BITS_ARFR2_V1_8822B)) +#define BIT_GET_ARFR2_V1_8822B(x) \ + (((x) >> BIT_SHIFT_ARFR2_V1_8822B) & BIT_MASK_ARFR2_V1_8822B) +#define BIT_SET_ARFR2_V1_8822B(x, v) \ + (BIT_CLEAR_ARFR2_V1_8822B(x) | BIT_ARFR2_V1_8822B(v)) /* 2 REG_ARFR3_V1_8822B */ #define BIT_SHIFT_ARFR3_V1_8822B 0 #define BIT_MASK_ARFR3_V1_8822B 0xffffffffffffffffL -#define BIT_ARFR3_V1_8822B(x) (((x) & BIT_MASK_ARFR3_V1_8822B) << BIT_SHIFT_ARFR3_V1_8822B) -#define BIT_GET_ARFR3_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR3_V1_8822B) & BIT_MASK_ARFR3_V1_8822B) - - +#define BIT_ARFR3_V1_8822B(x) \ + (((x) & BIT_MASK_ARFR3_V1_8822B) << BIT_SHIFT_ARFR3_V1_8822B) +#define BITS_ARFR3_V1_8822B \ + (BIT_MASK_ARFR3_V1_8822B << BIT_SHIFT_ARFR3_V1_8822B) +#define BIT_CLEAR_ARFR3_V1_8822B(x) ((x) & (~BITS_ARFR3_V1_8822B)) +#define BIT_GET_ARFR3_V1_8822B(x) \ + (((x) >> BIT_SHIFT_ARFR3_V1_8822B) & BIT_MASK_ARFR3_V1_8822B) +#define BIT_SET_ARFR3_V1_8822B(x, v) \ + (BIT_CLEAR_ARFR3_V1_8822B(x) | BIT_ARFR3_V1_8822B(v)) /* 2 REG_ARFR4_8822B */ #define BIT_SHIFT_ARFR4_8822B 0 #define BIT_MASK_ARFR4_8822B 0xffffffffffffffffL -#define BIT_ARFR4_8822B(x) (((x) & BIT_MASK_ARFR4_8822B) << BIT_SHIFT_ARFR4_8822B) -#define BIT_GET_ARFR4_8822B(x) (((x) >> BIT_SHIFT_ARFR4_8822B) & BIT_MASK_ARFR4_8822B) - - +#define BIT_ARFR4_8822B(x) \ + (((x) & BIT_MASK_ARFR4_8822B) << BIT_SHIFT_ARFR4_8822B) +#define BITS_ARFR4_8822B (BIT_MASK_ARFR4_8822B << BIT_SHIFT_ARFR4_8822B) +#define BIT_CLEAR_ARFR4_8822B(x) ((x) & (~BITS_ARFR4_8822B)) +#define BIT_GET_ARFR4_8822B(x) \ + (((x) >> BIT_SHIFT_ARFR4_8822B) & BIT_MASK_ARFR4_8822B) +#define BIT_SET_ARFR4_8822B(x, v) \ + (BIT_CLEAR_ARFR4_8822B(x) | BIT_ARFR4_8822B(v)) /* 2 REG_ARFR5_8822B */ #define BIT_SHIFT_ARFR5_8822B 0 #define BIT_MASK_ARFR5_8822B 0xffffffffffffffffL -#define BIT_ARFR5_8822B(x) (((x) & BIT_MASK_ARFR5_8822B) << BIT_SHIFT_ARFR5_8822B) -#define BIT_GET_ARFR5_8822B(x) (((x) >> BIT_SHIFT_ARFR5_8822B) & BIT_MASK_ARFR5_8822B) - - +#define BIT_ARFR5_8822B(x) \ + (((x) & BIT_MASK_ARFR5_8822B) << BIT_SHIFT_ARFR5_8822B) +#define BITS_ARFR5_8822B (BIT_MASK_ARFR5_8822B << BIT_SHIFT_ARFR5_8822B) +#define BIT_CLEAR_ARFR5_8822B(x) ((x) & (~BITS_ARFR5_8822B)) +#define BIT_GET_ARFR5_8822B(x) \ + (((x) >> BIT_SHIFT_ARFR5_8822B) & BIT_MASK_ARFR5_8822B) +#define BIT_SET_ARFR5_8822B(x, v) \ + (BIT_CLEAR_ARFR5_8822B(x) | BIT_ARFR5_8822B(v)) /* 2 REG_TXRPT_START_OFFSET_8822B */ #define BIT_SHIFT_MACID_MURATE_OFFSET_8822B 24 #define BIT_MASK_MACID_MURATE_OFFSET_8822B 0xff -#define BIT_MACID_MURATE_OFFSET_8822B(x) (((x) & BIT_MASK_MACID_MURATE_OFFSET_8822B) << BIT_SHIFT_MACID_MURATE_OFFSET_8822B) -#define BIT_GET_MACID_MURATE_OFFSET_8822B(x) (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822B) & BIT_MASK_MACID_MURATE_OFFSET_8822B) - +#define BIT_MACID_MURATE_OFFSET_8822B(x) \ + (((x) & BIT_MASK_MACID_MURATE_OFFSET_8822B) \ + << BIT_SHIFT_MACID_MURATE_OFFSET_8822B) +#define BITS_MACID_MURATE_OFFSET_8822B \ + (BIT_MASK_MACID_MURATE_OFFSET_8822B \ + << BIT_SHIFT_MACID_MURATE_OFFSET_8822B) +#define BIT_CLEAR_MACID_MURATE_OFFSET_8822B(x) \ + ((x) & (~BITS_MACID_MURATE_OFFSET_8822B)) +#define BIT_GET_MACID_MURATE_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822B) & \ + BIT_MASK_MACID_MURATE_OFFSET_8822B) +#define BIT_SET_MACID_MURATE_OFFSET_8822B(x, v) \ + (BIT_CLEAR_MACID_MURATE_OFFSET_8822B(x) | \ + BIT_MACID_MURATE_OFFSET_8822B(v)) #define BIT_RPTFIFO_SIZE_OPT_8822B BIT(16) #define BIT_SHIFT_MACID_CTRL_OFFSET_8822B 8 #define BIT_MASK_MACID_CTRL_OFFSET_8822B 0xff -#define BIT_MACID_CTRL_OFFSET_8822B(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8822B) << BIT_SHIFT_MACID_CTRL_OFFSET_8822B) -#define BIT_GET_MACID_CTRL_OFFSET_8822B(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822B) & BIT_MASK_MACID_CTRL_OFFSET_8822B) - - +#define BIT_MACID_CTRL_OFFSET_8822B(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET_8822B) \ + << BIT_SHIFT_MACID_CTRL_OFFSET_8822B) +#define BITS_MACID_CTRL_OFFSET_8822B \ + (BIT_MASK_MACID_CTRL_OFFSET_8822B << BIT_SHIFT_MACID_CTRL_OFFSET_8822B) +#define BIT_CLEAR_MACID_CTRL_OFFSET_8822B(x) \ + ((x) & (~BITS_MACID_CTRL_OFFSET_8822B)) +#define BIT_GET_MACID_CTRL_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822B) & \ + BIT_MASK_MACID_CTRL_OFFSET_8822B) +#define BIT_SET_MACID_CTRL_OFFSET_8822B(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET_8822B(x) | BIT_MACID_CTRL_OFFSET_8822B(v)) #define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B 0 #define BIT_MASK_AMPDU_TXRPT_OFFSET_8822B 0xff -#define BIT_AMPDU_TXRPT_OFFSET_8822B(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) -#define BIT_GET_AMPDU_TXRPT_OFFSET_8822B(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) - - +#define BIT_AMPDU_TXRPT_OFFSET_8822B(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) +#define BITS_AMPDU_TXRPT_OFFSET_8822B \ + (BIT_MASK_AMPDU_TXRPT_OFFSET_8822B \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822B(x) \ + ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8822B)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) & \ + BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) +#define BIT_SET_AMPDU_TXRPT_OFFSET_8822B(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822B(x) | \ + BIT_AMPDU_TXRPT_OFFSET_8822B(v)) /* 2 REG_POWER_STAGE1_8822B */ #define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8822B BIT(31) @@ -6109,28 +9396,44 @@ #define BIT_SHIFT_POWER_STAGE1_8822B 0 #define BIT_MASK_POWER_STAGE1_8822B 0xffffff -#define BIT_POWER_STAGE1_8822B(x) (((x) & BIT_MASK_POWER_STAGE1_8822B) << BIT_SHIFT_POWER_STAGE1_8822B) -#define BIT_GET_POWER_STAGE1_8822B(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8822B) & BIT_MASK_POWER_STAGE1_8822B) - - +#define BIT_POWER_STAGE1_8822B(x) \ + (((x) & BIT_MASK_POWER_STAGE1_8822B) << BIT_SHIFT_POWER_STAGE1_8822B) +#define BITS_POWER_STAGE1_8822B \ + (BIT_MASK_POWER_STAGE1_8822B << BIT_SHIFT_POWER_STAGE1_8822B) +#define BIT_CLEAR_POWER_STAGE1_8822B(x) ((x) & (~BITS_POWER_STAGE1_8822B)) +#define BIT_GET_POWER_STAGE1_8822B(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1_8822B) & BIT_MASK_POWER_STAGE1_8822B) +#define BIT_SET_POWER_STAGE1_8822B(x, v) \ + (BIT_CLEAR_POWER_STAGE1_8822B(x) | BIT_POWER_STAGE1_8822B(v)) /* 2 REG_POWER_STAGE2_8822B */ #define BIT__R_CTRL_PKT_POW_ADJ_8822B BIT(24) #define BIT_SHIFT_POWER_STAGE2_8822B 0 #define BIT_MASK_POWER_STAGE2_8822B 0xffffff -#define BIT_POWER_STAGE2_8822B(x) (((x) & BIT_MASK_POWER_STAGE2_8822B) << BIT_SHIFT_POWER_STAGE2_8822B) -#define BIT_GET_POWER_STAGE2_8822B(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8822B) & BIT_MASK_POWER_STAGE2_8822B) - - +#define BIT_POWER_STAGE2_8822B(x) \ + (((x) & BIT_MASK_POWER_STAGE2_8822B) << BIT_SHIFT_POWER_STAGE2_8822B) +#define BITS_POWER_STAGE2_8822B \ + (BIT_MASK_POWER_STAGE2_8822B << BIT_SHIFT_POWER_STAGE2_8822B) +#define BIT_CLEAR_POWER_STAGE2_8822B(x) ((x) & (~BITS_POWER_STAGE2_8822B)) +#define BIT_GET_POWER_STAGE2_8822B(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2_8822B) & BIT_MASK_POWER_STAGE2_8822B) +#define BIT_SET_POWER_STAGE2_8822B(x, v) \ + (BIT_CLEAR_POWER_STAGE2_8822B(x) | BIT_POWER_STAGE2_8822B(v)) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8822B */ #define BIT_SHIFT_PAD_NUM_THRES_8822B 24 #define BIT_MASK_PAD_NUM_THRES_8822B 0x3f -#define BIT_PAD_NUM_THRES_8822B(x) (((x) & BIT_MASK_PAD_NUM_THRES_8822B) << BIT_SHIFT_PAD_NUM_THRES_8822B) -#define BIT_GET_PAD_NUM_THRES_8822B(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8822B) & BIT_MASK_PAD_NUM_THRES_8822B) - +#define BIT_PAD_NUM_THRES_8822B(x) \ + (((x) & BIT_MASK_PAD_NUM_THRES_8822B) << BIT_SHIFT_PAD_NUM_THRES_8822B) +#define BITS_PAD_NUM_THRES_8822B \ + (BIT_MASK_PAD_NUM_THRES_8822B << BIT_SHIFT_PAD_NUM_THRES_8822B) +#define BIT_CLEAR_PAD_NUM_THRES_8822B(x) ((x) & (~BITS_PAD_NUM_THRES_8822B)) +#define BIT_GET_PAD_NUM_THRES_8822B(x) \ + (((x) >> BIT_SHIFT_PAD_NUM_THRES_8822B) & BIT_MASK_PAD_NUM_THRES_8822B) +#define BIT_SET_PAD_NUM_THRES_8822B(x, v) \ + (BIT_CLEAR_PAD_NUM_THRES_8822B(x) | BIT_PAD_NUM_THRES_8822B(v)) #define BIT_R_DMA_THIS_QUEUE_BK_8822B BIT(23) #define BIT_R_DMA_THIS_QUEUE_BE_8822B BIT(22) @@ -6139,18 +9442,32 @@ #define BIT_SHIFT_R_TOTAL_LEN_TH_8822B 8 #define BIT_MASK_R_TOTAL_LEN_TH_8822B 0xfff -#define BIT_R_TOTAL_LEN_TH_8822B(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8822B) << BIT_SHIFT_R_TOTAL_LEN_TH_8822B) -#define BIT_GET_R_TOTAL_LEN_TH_8822B(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822B) & BIT_MASK_R_TOTAL_LEN_TH_8822B) - +#define BIT_R_TOTAL_LEN_TH_8822B(x) \ + (((x) & BIT_MASK_R_TOTAL_LEN_TH_8822B) \ + << BIT_SHIFT_R_TOTAL_LEN_TH_8822B) +#define BITS_R_TOTAL_LEN_TH_8822B \ + (BIT_MASK_R_TOTAL_LEN_TH_8822B << BIT_SHIFT_R_TOTAL_LEN_TH_8822B) +#define BIT_CLEAR_R_TOTAL_LEN_TH_8822B(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8822B)) +#define BIT_GET_R_TOTAL_LEN_TH_8822B(x) \ + (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822B) & \ + BIT_MASK_R_TOTAL_LEN_TH_8822B) +#define BIT_SET_R_TOTAL_LEN_TH_8822B(x, v) \ + (BIT_CLEAR_R_TOTAL_LEN_TH_8822B(x) | BIT_R_TOTAL_LEN_TH_8822B(v)) #define BIT_EN_NEW_EARLY_8822B BIT(7) #define BIT_PRE_TX_CMD_8822B BIT(6) #define BIT_SHIFT_NUM_SCL_EN_8822B 4 #define BIT_MASK_NUM_SCL_EN_8822B 0x3 -#define BIT_NUM_SCL_EN_8822B(x) (((x) & BIT_MASK_NUM_SCL_EN_8822B) << BIT_SHIFT_NUM_SCL_EN_8822B) -#define BIT_GET_NUM_SCL_EN_8822B(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8822B) & BIT_MASK_NUM_SCL_EN_8822B) - +#define BIT_NUM_SCL_EN_8822B(x) \ + (((x) & BIT_MASK_NUM_SCL_EN_8822B) << BIT_SHIFT_NUM_SCL_EN_8822B) +#define BITS_NUM_SCL_EN_8822B \ + (BIT_MASK_NUM_SCL_EN_8822B << BIT_SHIFT_NUM_SCL_EN_8822B) +#define BIT_CLEAR_NUM_SCL_EN_8822B(x) ((x) & (~BITS_NUM_SCL_EN_8822B)) +#define BIT_GET_NUM_SCL_EN_8822B(x) \ + (((x) >> BIT_SHIFT_NUM_SCL_EN_8822B) & BIT_MASK_NUM_SCL_EN_8822B) +#define BIT_SET_NUM_SCL_EN_8822B(x, v) \ + (BIT_CLEAR_NUM_SCL_EN_8822B(x) | BIT_NUM_SCL_EN_8822B(v)) #define BIT_BK_EN_8822B BIT(3) #define BIT_BE_EN_8822B BIT(2) @@ -6161,49 +9478,86 @@ #define BIT_SHIFT_PKT_LIFTIME_BEBK_8822B 16 #define BIT_MASK_PKT_LIFTIME_BEBK_8822B 0xffff -#define BIT_PKT_LIFTIME_BEBK_8822B(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822B) << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) -#define BIT_GET_PKT_LIFTIME_BEBK_8822B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) & BIT_MASK_PKT_LIFTIME_BEBK_8822B) - - +#define BIT_PKT_LIFTIME_BEBK_8822B(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822B) \ + << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) +#define BITS_PKT_LIFTIME_BEBK_8822B \ + (BIT_MASK_PKT_LIFTIME_BEBK_8822B << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) +#define BIT_CLEAR_PKT_LIFTIME_BEBK_8822B(x) \ + ((x) & (~BITS_PKT_LIFTIME_BEBK_8822B)) +#define BIT_GET_PKT_LIFTIME_BEBK_8822B(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) & \ + BIT_MASK_PKT_LIFTIME_BEBK_8822B) +#define BIT_SET_PKT_LIFTIME_BEBK_8822B(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_BEBK_8822B(x) | BIT_PKT_LIFTIME_BEBK_8822B(v)) #define BIT_SHIFT_PKT_LIFTIME_VOVI_8822B 0 #define BIT_MASK_PKT_LIFTIME_VOVI_8822B 0xffff -#define BIT_PKT_LIFTIME_VOVI_8822B(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822B) << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) -#define BIT_GET_PKT_LIFTIME_VOVI_8822B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) & BIT_MASK_PKT_LIFTIME_VOVI_8822B) - - +#define BIT_PKT_LIFTIME_VOVI_8822B(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822B) \ + << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) +#define BITS_PKT_LIFTIME_VOVI_8822B \ + (BIT_MASK_PKT_LIFTIME_VOVI_8822B << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) +#define BIT_CLEAR_PKT_LIFTIME_VOVI_8822B(x) \ + ((x) & (~BITS_PKT_LIFTIME_VOVI_8822B)) +#define BIT_GET_PKT_LIFTIME_VOVI_8822B(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) & \ + BIT_MASK_PKT_LIFTIME_VOVI_8822B) +#define BIT_SET_PKT_LIFTIME_VOVI_8822B(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_VOVI_8822B(x) | BIT_PKT_LIFTIME_VOVI_8822B(v)) /* 2 REG_STBC_SETTING_8822B */ #define BIT_SHIFT_CDEND_TXTIME_L_8822B 4 #define BIT_MASK_CDEND_TXTIME_L_8822B 0xf -#define BIT_CDEND_TXTIME_L_8822B(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8822B) << BIT_SHIFT_CDEND_TXTIME_L_8822B) -#define BIT_GET_CDEND_TXTIME_L_8822B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822B) & BIT_MASK_CDEND_TXTIME_L_8822B) - - +#define BIT_CDEND_TXTIME_L_8822B(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_L_8822B) \ + << BIT_SHIFT_CDEND_TXTIME_L_8822B) +#define BITS_CDEND_TXTIME_L_8822B \ + (BIT_MASK_CDEND_TXTIME_L_8822B << BIT_SHIFT_CDEND_TXTIME_L_8822B) +#define BIT_CLEAR_CDEND_TXTIME_L_8822B(x) ((x) & (~BITS_CDEND_TXTIME_L_8822B)) +#define BIT_GET_CDEND_TXTIME_L_8822B(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822B) & \ + BIT_MASK_CDEND_TXTIME_L_8822B) +#define BIT_SET_CDEND_TXTIME_L_8822B(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_L_8822B(x) | BIT_CDEND_TXTIME_L_8822B(v)) #define BIT_SHIFT_NESS_8822B 2 #define BIT_MASK_NESS_8822B 0x3 #define BIT_NESS_8822B(x) (((x) & BIT_MASK_NESS_8822B) << BIT_SHIFT_NESS_8822B) -#define BIT_GET_NESS_8822B(x) (((x) >> BIT_SHIFT_NESS_8822B) & BIT_MASK_NESS_8822B) - - +#define BITS_NESS_8822B (BIT_MASK_NESS_8822B << BIT_SHIFT_NESS_8822B) +#define BIT_CLEAR_NESS_8822B(x) ((x) & (~BITS_NESS_8822B)) +#define BIT_GET_NESS_8822B(x) \ + (((x) >> BIT_SHIFT_NESS_8822B) & BIT_MASK_NESS_8822B) +#define BIT_SET_NESS_8822B(x, v) (BIT_CLEAR_NESS_8822B(x) | BIT_NESS_8822B(v)) #define BIT_SHIFT_STBC_CFEND_8822B 0 #define BIT_MASK_STBC_CFEND_8822B 0x3 -#define BIT_STBC_CFEND_8822B(x) (((x) & BIT_MASK_STBC_CFEND_8822B) << BIT_SHIFT_STBC_CFEND_8822B) -#define BIT_GET_STBC_CFEND_8822B(x) (((x) >> BIT_SHIFT_STBC_CFEND_8822B) & BIT_MASK_STBC_CFEND_8822B) - - +#define BIT_STBC_CFEND_8822B(x) \ + (((x) & BIT_MASK_STBC_CFEND_8822B) << BIT_SHIFT_STBC_CFEND_8822B) +#define BITS_STBC_CFEND_8822B \ + (BIT_MASK_STBC_CFEND_8822B << BIT_SHIFT_STBC_CFEND_8822B) +#define BIT_CLEAR_STBC_CFEND_8822B(x) ((x) & (~BITS_STBC_CFEND_8822B)) +#define BIT_GET_STBC_CFEND_8822B(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_8822B) & BIT_MASK_STBC_CFEND_8822B) +#define BIT_SET_STBC_CFEND_8822B(x, v) \ + (BIT_CLEAR_STBC_CFEND_8822B(x) | BIT_STBC_CFEND_8822B(v)) /* 2 REG_STBC_SETTING2_8822B */ #define BIT_SHIFT_CDEND_TXTIME_H_8822B 0 #define BIT_MASK_CDEND_TXTIME_H_8822B 0x1f -#define BIT_CDEND_TXTIME_H_8822B(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8822B) << BIT_SHIFT_CDEND_TXTIME_H_8822B) -#define BIT_GET_CDEND_TXTIME_H_8822B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822B) & BIT_MASK_CDEND_TXTIME_H_8822B) - - +#define BIT_CDEND_TXTIME_H_8822B(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_H_8822B) \ + << BIT_SHIFT_CDEND_TXTIME_H_8822B) +#define BITS_CDEND_TXTIME_H_8822B \ + (BIT_MASK_CDEND_TXTIME_H_8822B << BIT_SHIFT_CDEND_TXTIME_H_8822B) +#define BIT_CLEAR_CDEND_TXTIME_H_8822B(x) ((x) & (~BITS_CDEND_TXTIME_H_8822B)) +#define BIT_GET_CDEND_TXTIME_H_8822B(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822B) & \ + BIT_MASK_CDEND_TXTIME_H_8822B) +#define BIT_SET_CDEND_TXTIME_H_8822B(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_H_8822B(x) | BIT_CDEND_TXTIME_H_8822B(v)) /* 2 REG_QUEUE_CTRL_8822B */ #define BIT_PTA_EDCCA_EN_8822B BIT(5) @@ -6220,126 +9574,229 @@ #define BIT_SHIFT_RTS_MAX_AGG_NUM_8822B 24 #define BIT_MASK_RTS_MAX_AGG_NUM_8822B 0x3f -#define BIT_RTS_MAX_AGG_NUM_8822B(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822B) << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) -#define BIT_GET_RTS_MAX_AGG_NUM_8822B(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) & BIT_MASK_RTS_MAX_AGG_NUM_8822B) - - +#define BIT_RTS_MAX_AGG_NUM_8822B(x) \ + (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822B) \ + << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) +#define BITS_RTS_MAX_AGG_NUM_8822B \ + (BIT_MASK_RTS_MAX_AGG_NUM_8822B << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) +#define BIT_CLEAR_RTS_MAX_AGG_NUM_8822B(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8822B)) +#define BIT_GET_RTS_MAX_AGG_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) & \ + BIT_MASK_RTS_MAX_AGG_NUM_8822B) +#define BIT_SET_RTS_MAX_AGG_NUM_8822B(x, v) \ + (BIT_CLEAR_RTS_MAX_AGG_NUM_8822B(x) | BIT_RTS_MAX_AGG_NUM_8822B(v)) #define BIT_SHIFT_MAX_AGG_NUM_8822B 16 #define BIT_MASK_MAX_AGG_NUM_8822B 0x3f -#define BIT_MAX_AGG_NUM_8822B(x) (((x) & BIT_MASK_MAX_AGG_NUM_8822B) << BIT_SHIFT_MAX_AGG_NUM_8822B) -#define BIT_GET_MAX_AGG_NUM_8822B(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8822B) & BIT_MASK_MAX_AGG_NUM_8822B) - - +#define BIT_MAX_AGG_NUM_8822B(x) \ + (((x) & BIT_MASK_MAX_AGG_NUM_8822B) << BIT_SHIFT_MAX_AGG_NUM_8822B) +#define BITS_MAX_AGG_NUM_8822B \ + (BIT_MASK_MAX_AGG_NUM_8822B << BIT_SHIFT_MAX_AGG_NUM_8822B) +#define BIT_CLEAR_MAX_AGG_NUM_8822B(x) ((x) & (~BITS_MAX_AGG_NUM_8822B)) +#define BIT_GET_MAX_AGG_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_MAX_AGG_NUM_8822B) & BIT_MASK_MAX_AGG_NUM_8822B) +#define BIT_SET_MAX_AGG_NUM_8822B(x, v) \ + (BIT_CLEAR_MAX_AGG_NUM_8822B(x) | BIT_MAX_AGG_NUM_8822B(v)) #define BIT_SHIFT_RTS_TXTIME_TH_8822B 8 #define BIT_MASK_RTS_TXTIME_TH_8822B 0xff -#define BIT_RTS_TXTIME_TH_8822B(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8822B) << BIT_SHIFT_RTS_TXTIME_TH_8822B) -#define BIT_GET_RTS_TXTIME_TH_8822B(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822B) & BIT_MASK_RTS_TXTIME_TH_8822B) - - +#define BIT_RTS_TXTIME_TH_8822B(x) \ + (((x) & BIT_MASK_RTS_TXTIME_TH_8822B) << BIT_SHIFT_RTS_TXTIME_TH_8822B) +#define BITS_RTS_TXTIME_TH_8822B \ + (BIT_MASK_RTS_TXTIME_TH_8822B << BIT_SHIFT_RTS_TXTIME_TH_8822B) +#define BIT_CLEAR_RTS_TXTIME_TH_8822B(x) ((x) & (~BITS_RTS_TXTIME_TH_8822B)) +#define BIT_GET_RTS_TXTIME_TH_8822B(x) \ + (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822B) & BIT_MASK_RTS_TXTIME_TH_8822B) +#define BIT_SET_RTS_TXTIME_TH_8822B(x, v) \ + (BIT_CLEAR_RTS_TXTIME_TH_8822B(x) | BIT_RTS_TXTIME_TH_8822B(v)) #define BIT_SHIFT_RTS_LEN_TH_8822B 0 #define BIT_MASK_RTS_LEN_TH_8822B 0xff -#define BIT_RTS_LEN_TH_8822B(x) (((x) & BIT_MASK_RTS_LEN_TH_8822B) << BIT_SHIFT_RTS_LEN_TH_8822B) -#define BIT_GET_RTS_LEN_TH_8822B(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8822B) & BIT_MASK_RTS_LEN_TH_8822B) - - +#define BIT_RTS_LEN_TH_8822B(x) \ + (((x) & BIT_MASK_RTS_LEN_TH_8822B) << BIT_SHIFT_RTS_LEN_TH_8822B) +#define BITS_RTS_LEN_TH_8822B \ + (BIT_MASK_RTS_LEN_TH_8822B << BIT_SHIFT_RTS_LEN_TH_8822B) +#define BIT_CLEAR_RTS_LEN_TH_8822B(x) ((x) & (~BITS_RTS_LEN_TH_8822B)) +#define BIT_GET_RTS_LEN_TH_8822B(x) \ + (((x) >> BIT_SHIFT_RTS_LEN_TH_8822B) & BIT_MASK_RTS_LEN_TH_8822B) +#define BIT_SET_RTS_LEN_TH_8822B(x, v) \ + (BIT_CLEAR_RTS_LEN_TH_8822B(x) | BIT_RTS_LEN_TH_8822B(v)) /* 2 REG_BAR_MODE_CTRL_8822B */ #define BIT_SHIFT_BAR_RTY_LMT_8822B 16 #define BIT_MASK_BAR_RTY_LMT_8822B 0x3 -#define BIT_BAR_RTY_LMT_8822B(x) (((x) & BIT_MASK_BAR_RTY_LMT_8822B) << BIT_SHIFT_BAR_RTY_LMT_8822B) -#define BIT_GET_BAR_RTY_LMT_8822B(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8822B) & BIT_MASK_BAR_RTY_LMT_8822B) - - +#define BIT_BAR_RTY_LMT_8822B(x) \ + (((x) & BIT_MASK_BAR_RTY_LMT_8822B) << BIT_SHIFT_BAR_RTY_LMT_8822B) +#define BITS_BAR_RTY_LMT_8822B \ + (BIT_MASK_BAR_RTY_LMT_8822B << BIT_SHIFT_BAR_RTY_LMT_8822B) +#define BIT_CLEAR_BAR_RTY_LMT_8822B(x) ((x) & (~BITS_BAR_RTY_LMT_8822B)) +#define BIT_GET_BAR_RTY_LMT_8822B(x) \ + (((x) >> BIT_SHIFT_BAR_RTY_LMT_8822B) & BIT_MASK_BAR_RTY_LMT_8822B) +#define BIT_SET_BAR_RTY_LMT_8822B(x, v) \ + (BIT_CLEAR_BAR_RTY_LMT_8822B(x) | BIT_BAR_RTY_LMT_8822B(v)) #define BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B 8 #define BIT_MASK_BAR_PKT_TXTIME_TH_8822B 0xff -#define BIT_BAR_PKT_TXTIME_TH_8822B(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) -#define BIT_GET_BAR_PKT_TXTIME_TH_8822B(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B) - +#define BIT_BAR_PKT_TXTIME_TH_8822B(x) \ + (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B) \ + << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) +#define BITS_BAR_PKT_TXTIME_TH_8822B \ + (BIT_MASK_BAR_PKT_TXTIME_TH_8822B << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8822B(x) \ + ((x) & (~BITS_BAR_PKT_TXTIME_TH_8822B)) +#define BIT_GET_BAR_PKT_TXTIME_TH_8822B(x) \ + (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) & \ + BIT_MASK_BAR_PKT_TXTIME_TH_8822B) +#define BIT_SET_BAR_PKT_TXTIME_TH_8822B(x, v) \ + (BIT_CLEAR_BAR_PKT_TXTIME_TH_8822B(x) | BIT_BAR_PKT_TXTIME_TH_8822B(v)) #define BIT_BAR_EN_V1_8822B BIT(6) #define BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B 0 #define BIT_MASK_BAR_PKTNUM_TH_V1_8822B 0x3f -#define BIT_BAR_PKTNUM_TH_V1_8822B(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) -#define BIT_GET_BAR_PKTNUM_TH_V1_8822B(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B) - - +#define BIT_BAR_PKTNUM_TH_V1_8822B(x) \ + (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B) \ + << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) +#define BITS_BAR_PKTNUM_TH_V1_8822B \ + (BIT_MASK_BAR_PKTNUM_TH_V1_8822B << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8822B(x) \ + ((x) & (~BITS_BAR_PKTNUM_TH_V1_8822B)) +#define BIT_GET_BAR_PKTNUM_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) & \ + BIT_MASK_BAR_PKTNUM_TH_V1_8822B) +#define BIT_SET_BAR_PKTNUM_TH_V1_8822B(x, v) \ + (BIT_CLEAR_BAR_PKTNUM_TH_V1_8822B(x) | BIT_BAR_PKTNUM_TH_V1_8822B(v)) /* 2 REG_RA_TRY_RATE_AGG_LMT_8822B */ #define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B 0 #define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B 0x3f -#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) -#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822B(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B) - - +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B) \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) +#define BITS_RA_TRY_RATE_AGG_LMT_V1_8822B \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822B(x) \ + ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8822B)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822B(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) & \ + BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8822B(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822B(x) | \ + BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(v)) /* 2 REG_MACID_SLEEP2_8822B */ #define BIT_SHIFT_MACID95_64PKTSLEEP_8822B 0 #define BIT_MASK_MACID95_64PKTSLEEP_8822B 0xffffffffL -#define BIT_MACID95_64PKTSLEEP_8822B(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8822B) << BIT_SHIFT_MACID95_64PKTSLEEP_8822B) -#define BIT_GET_MACID95_64PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822B) & BIT_MASK_MACID95_64PKTSLEEP_8822B) - - +#define BIT_MACID95_64PKTSLEEP_8822B(x) \ + (((x) & BIT_MASK_MACID95_64PKTSLEEP_8822B) \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8822B) +#define BITS_MACID95_64PKTSLEEP_8822B \ + (BIT_MASK_MACID95_64PKTSLEEP_8822B \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8822B) +#define BIT_CLEAR_MACID95_64PKTSLEEP_8822B(x) \ + ((x) & (~BITS_MACID95_64PKTSLEEP_8822B)) +#define BIT_GET_MACID95_64PKTSLEEP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822B) & \ + BIT_MASK_MACID95_64PKTSLEEP_8822B) +#define BIT_SET_MACID95_64PKTSLEEP_8822B(x, v) \ + (BIT_CLEAR_MACID95_64PKTSLEEP_8822B(x) | \ + BIT_MACID95_64PKTSLEEP_8822B(v)) /* 2 REG_MACID_SLEEP_8822B */ #define BIT_SHIFT_MACID31_0_PKTSLEEP_8822B 0 #define BIT_MASK_MACID31_0_PKTSLEEP_8822B 0xffffffffL -#define BIT_MACID31_0_PKTSLEEP_8822B(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822B) << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) -#define BIT_GET_MACID31_0_PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) & BIT_MASK_MACID31_0_PKTSLEEP_8822B) - - +#define BIT_MACID31_0_PKTSLEEP_8822B(x) \ + (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822B) \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) +#define BITS_MACID31_0_PKTSLEEP_8822B \ + (BIT_MASK_MACID31_0_PKTSLEEP_8822B \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) +#define BIT_CLEAR_MACID31_0_PKTSLEEP_8822B(x) \ + ((x) & (~BITS_MACID31_0_PKTSLEEP_8822B)) +#define BIT_GET_MACID31_0_PKTSLEEP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) & \ + BIT_MASK_MACID31_0_PKTSLEEP_8822B) +#define BIT_SET_MACID31_0_PKTSLEEP_8822B(x, v) \ + (BIT_CLEAR_MACID31_0_PKTSLEEP_8822B(x) | \ + BIT_MACID31_0_PKTSLEEP_8822B(v)) /* 2 REG_HW_SEQ0_8822B */ #define BIT_SHIFT_HW_SSN_SEQ0_8822B 0 #define BIT_MASK_HW_SSN_SEQ0_8822B 0xfff -#define BIT_HW_SSN_SEQ0_8822B(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8822B) << BIT_SHIFT_HW_SSN_SEQ0_8822B) -#define BIT_GET_HW_SSN_SEQ0_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822B) & BIT_MASK_HW_SSN_SEQ0_8822B) - - +#define BIT_HW_SSN_SEQ0_8822B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ0_8822B) << BIT_SHIFT_HW_SSN_SEQ0_8822B) +#define BITS_HW_SSN_SEQ0_8822B \ + (BIT_MASK_HW_SSN_SEQ0_8822B << BIT_SHIFT_HW_SSN_SEQ0_8822B) +#define BIT_CLEAR_HW_SSN_SEQ0_8822B(x) ((x) & (~BITS_HW_SSN_SEQ0_8822B)) +#define BIT_GET_HW_SSN_SEQ0_8822B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822B) & BIT_MASK_HW_SSN_SEQ0_8822B) +#define BIT_SET_HW_SSN_SEQ0_8822B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ0_8822B(x) | BIT_HW_SSN_SEQ0_8822B(v)) /* 2 REG_HW_SEQ1_8822B */ #define BIT_SHIFT_HW_SSN_SEQ1_8822B 0 #define BIT_MASK_HW_SSN_SEQ1_8822B 0xfff -#define BIT_HW_SSN_SEQ1_8822B(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8822B) << BIT_SHIFT_HW_SSN_SEQ1_8822B) -#define BIT_GET_HW_SSN_SEQ1_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822B) & BIT_MASK_HW_SSN_SEQ1_8822B) - - +#define BIT_HW_SSN_SEQ1_8822B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ1_8822B) << BIT_SHIFT_HW_SSN_SEQ1_8822B) +#define BITS_HW_SSN_SEQ1_8822B \ + (BIT_MASK_HW_SSN_SEQ1_8822B << BIT_SHIFT_HW_SSN_SEQ1_8822B) +#define BIT_CLEAR_HW_SSN_SEQ1_8822B(x) ((x) & (~BITS_HW_SSN_SEQ1_8822B)) +#define BIT_GET_HW_SSN_SEQ1_8822B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822B) & BIT_MASK_HW_SSN_SEQ1_8822B) +#define BIT_SET_HW_SSN_SEQ1_8822B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ1_8822B(x) | BIT_HW_SSN_SEQ1_8822B(v)) /* 2 REG_HW_SEQ2_8822B */ #define BIT_SHIFT_HW_SSN_SEQ2_8822B 0 #define BIT_MASK_HW_SSN_SEQ2_8822B 0xfff -#define BIT_HW_SSN_SEQ2_8822B(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8822B) << BIT_SHIFT_HW_SSN_SEQ2_8822B) -#define BIT_GET_HW_SSN_SEQ2_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822B) & BIT_MASK_HW_SSN_SEQ2_8822B) - - +#define BIT_HW_SSN_SEQ2_8822B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ2_8822B) << BIT_SHIFT_HW_SSN_SEQ2_8822B) +#define BITS_HW_SSN_SEQ2_8822B \ + (BIT_MASK_HW_SSN_SEQ2_8822B << BIT_SHIFT_HW_SSN_SEQ2_8822B) +#define BIT_CLEAR_HW_SSN_SEQ2_8822B(x) ((x) & (~BITS_HW_SSN_SEQ2_8822B)) +#define BIT_GET_HW_SSN_SEQ2_8822B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822B) & BIT_MASK_HW_SSN_SEQ2_8822B) +#define BIT_SET_HW_SSN_SEQ2_8822B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ2_8822B(x) | BIT_HW_SSN_SEQ2_8822B(v)) /* 2 REG_HW_SEQ3_8822B */ #define BIT_SHIFT_HW_SSN_SEQ3_8822B 0 #define BIT_MASK_HW_SSN_SEQ3_8822B 0xfff -#define BIT_HW_SSN_SEQ3_8822B(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8822B) << BIT_SHIFT_HW_SSN_SEQ3_8822B) -#define BIT_GET_HW_SSN_SEQ3_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822B) & BIT_MASK_HW_SSN_SEQ3_8822B) - - +#define BIT_HW_SSN_SEQ3_8822B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ3_8822B) << BIT_SHIFT_HW_SSN_SEQ3_8822B) +#define BITS_HW_SSN_SEQ3_8822B \ + (BIT_MASK_HW_SSN_SEQ3_8822B << BIT_SHIFT_HW_SSN_SEQ3_8822B) +#define BIT_CLEAR_HW_SSN_SEQ3_8822B(x) ((x) & (~BITS_HW_SSN_SEQ3_8822B)) +#define BIT_GET_HW_SSN_SEQ3_8822B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822B) & BIT_MASK_HW_SSN_SEQ3_8822B) +#define BIT_SET_HW_SSN_SEQ3_8822B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ3_8822B(x) | BIT_HW_SSN_SEQ3_8822B(v)) /* 2 REG_NULL_PKT_STATUS_V1_8822B */ #define BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B 2 #define BIT_MASK_PTCL_TOTAL_PG_V2_8822B 0x3fff -#define BIT_PTCL_TOTAL_PG_V2_8822B(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B) << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) -#define BIT_GET_PTCL_TOTAL_PG_V2_8822B(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B) - +#define BIT_PTCL_TOTAL_PG_V2_8822B(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B) \ + << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) +#define BITS_PTCL_TOTAL_PG_V2_8822B \ + (BIT_MASK_PTCL_TOTAL_PG_V2_8822B << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) +#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8822B(x) \ + ((x) & (~BITS_PTCL_TOTAL_PG_V2_8822B)) +#define BIT_GET_PTCL_TOTAL_PG_V2_8822B(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) & \ + BIT_MASK_PTCL_TOTAL_PG_V2_8822B) +#define BIT_SET_PTCL_TOTAL_PG_V2_8822B(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V2_8822B(x) | BIT_PTCL_TOTAL_PG_V2_8822B(v)) #define BIT_TX_NULL_1_8822B BIT(1) #define BIT_TX_NULL_0_8822B BIT(0) @@ -6372,10 +9829,20 @@ #define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B 0 #define BIT_MASK_BT_POLLUTE_PKT_CNT_8822B 0xffff -#define BIT_BT_POLLUTE_PKT_CNT_8822B(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) -#define BIT_GET_BT_POLLUTE_PKT_CNT_8822B(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B) - - +#define BIT_BT_POLLUTE_PKT_CNT_8822B(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B) \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) +#define BITS_BT_POLLUTE_PKT_CNT_8822B \ + (BIT_MASK_BT_POLLUTE_PKT_CNT_8822B \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) +#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822B(x) \ + ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8822B)) +#define BIT_GET_BT_POLLUTE_PKT_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) & \ + BIT_MASK_BT_POLLUTE_PKT_CNT_8822B) +#define BIT_SET_BT_POLLUTE_PKT_CNT_8822B(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822B(x) | \ + BIT_BT_POLLUTE_PKT_CNT_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -6383,10 +9850,15 @@ #define BIT_SHIFT_PTCL_DBG_8822B 0 #define BIT_MASK_PTCL_DBG_8822B 0xffffffffL -#define BIT_PTCL_DBG_8822B(x) (((x) & BIT_MASK_PTCL_DBG_8822B) << BIT_SHIFT_PTCL_DBG_8822B) -#define BIT_GET_PTCL_DBG_8822B(x) (((x) >> BIT_SHIFT_PTCL_DBG_8822B) & BIT_MASK_PTCL_DBG_8822B) - - +#define BIT_PTCL_DBG_8822B(x) \ + (((x) & BIT_MASK_PTCL_DBG_8822B) << BIT_SHIFT_PTCL_DBG_8822B) +#define BITS_PTCL_DBG_8822B \ + (BIT_MASK_PTCL_DBG_8822B << BIT_SHIFT_PTCL_DBG_8822B) +#define BIT_CLEAR_PTCL_DBG_8822B(x) ((x) & (~BITS_PTCL_DBG_8822B)) +#define BIT_GET_PTCL_DBG_8822B(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_8822B) & BIT_MASK_PTCL_DBG_8822B) +#define BIT_SET_PTCL_DBG_8822B(x, v) \ + (BIT_CLEAR_PTCL_DBG_8822B(x) | BIT_PTCL_DBG_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -6394,18 +9866,28 @@ #define BIT_SHIFT_TRI_HEAD_ADDR_8822B 16 #define BIT_MASK_TRI_HEAD_ADDR_8822B 0xfff -#define BIT_TRI_HEAD_ADDR_8822B(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8822B) << BIT_SHIFT_TRI_HEAD_ADDR_8822B) -#define BIT_GET_TRI_HEAD_ADDR_8822B(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822B) & BIT_MASK_TRI_HEAD_ADDR_8822B) - +#define BIT_TRI_HEAD_ADDR_8822B(x) \ + (((x) & BIT_MASK_TRI_HEAD_ADDR_8822B) << BIT_SHIFT_TRI_HEAD_ADDR_8822B) +#define BITS_TRI_HEAD_ADDR_8822B \ + (BIT_MASK_TRI_HEAD_ADDR_8822B << BIT_SHIFT_TRI_HEAD_ADDR_8822B) +#define BIT_CLEAR_TRI_HEAD_ADDR_8822B(x) ((x) & (~BITS_TRI_HEAD_ADDR_8822B)) +#define BIT_GET_TRI_HEAD_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822B) & BIT_MASK_TRI_HEAD_ADDR_8822B) +#define BIT_SET_TRI_HEAD_ADDR_8822B(x, v) \ + (BIT_CLEAR_TRI_HEAD_ADDR_8822B(x) | BIT_TRI_HEAD_ADDR_8822B(v)) #define BIT_DROP_TH_EN_8822B BIT(8) #define BIT_SHIFT_DROP_TH_8822B 0 #define BIT_MASK_DROP_TH_8822B 0xff -#define BIT_DROP_TH_8822B(x) (((x) & BIT_MASK_DROP_TH_8822B) << BIT_SHIFT_DROP_TH_8822B) -#define BIT_GET_DROP_TH_8822B(x) (((x) >> BIT_SHIFT_DROP_TH_8822B) & BIT_MASK_DROP_TH_8822B) - - +#define BIT_DROP_TH_8822B(x) \ + (((x) & BIT_MASK_DROP_TH_8822B) << BIT_SHIFT_DROP_TH_8822B) +#define BITS_DROP_TH_8822B (BIT_MASK_DROP_TH_8822B << BIT_SHIFT_DROP_TH_8822B) +#define BIT_CLEAR_DROP_TH_8822B(x) ((x) & (~BITS_DROP_TH_8822B)) +#define BIT_GET_DROP_TH_8822B(x) \ + (((x) >> BIT_SHIFT_DROP_TH_8822B) & BIT_MASK_DROP_TH_8822B) +#define BIT_SET_DROP_TH_8822B(x, v) \ + (BIT_CLEAR_DROP_TH_8822B(x) | BIT_DROP_TH_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -6425,176 +9907,287 @@ #define BIT_SHIFT_GTAB_ID_8822B 28 #define BIT_MASK_GTAB_ID_8822B 0x7 -#define BIT_GTAB_ID_8822B(x) (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) -#define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) - - +#define BIT_GTAB_ID_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) +#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B) +#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B)) +#define BIT_GET_GTAB_ID_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) +#define BIT_SET_GTAB_ID_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v)) #define BIT_SHIFT_AC1_PKT_INFO_8822B 16 #define BIT_MASK_AC1_PKT_INFO_8822B 0xfff -#define BIT_AC1_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC1_PKT_INFO_8822B) << BIT_SHIFT_AC1_PKT_INFO_8822B) -#define BIT_GET_AC1_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8822B) & BIT_MASK_AC1_PKT_INFO_8822B) - +#define BIT_AC1_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC1_PKT_INFO_8822B) << BIT_SHIFT_AC1_PKT_INFO_8822B) +#define BITS_AC1_PKT_INFO_8822B \ + (BIT_MASK_AC1_PKT_INFO_8822B << BIT_SHIFT_AC1_PKT_INFO_8822B) +#define BIT_CLEAR_AC1_PKT_INFO_8822B(x) ((x) & (~BITS_AC1_PKT_INFO_8822B)) +#define BIT_GET_AC1_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC1_PKT_INFO_8822B) & BIT_MASK_AC1_PKT_INFO_8822B) +#define BIT_SET_AC1_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC1_PKT_INFO_8822B(x) | BIT_AC1_PKT_INFO_8822B(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8822B 12 #define BIT_MASK_GTAB_ID_V1_8822B 0x7 -#define BIT_GTAB_ID_V1_8822B(x) (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) -#define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) - - +#define BIT_GTAB_ID_V1_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BITS_GTAB_ID_V1_8822B \ + (BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B)) +#define BIT_GET_GTAB_ID_V1_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) +#define BIT_SET_GTAB_ID_V1_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v)) #define BIT_SHIFT_AC0_PKT_INFO_8822B 0 #define BIT_MASK_AC0_PKT_INFO_8822B 0xfff -#define BIT_AC0_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC0_PKT_INFO_8822B) << BIT_SHIFT_AC0_PKT_INFO_8822B) -#define BIT_GET_AC0_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8822B) & BIT_MASK_AC0_PKT_INFO_8822B) - - +#define BIT_AC0_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC0_PKT_INFO_8822B) << BIT_SHIFT_AC0_PKT_INFO_8822B) +#define BITS_AC0_PKT_INFO_8822B \ + (BIT_MASK_AC0_PKT_INFO_8822B << BIT_SHIFT_AC0_PKT_INFO_8822B) +#define BIT_CLEAR_AC0_PKT_INFO_8822B(x) ((x) & (~BITS_AC0_PKT_INFO_8822B)) +#define BIT_GET_AC0_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC0_PKT_INFO_8822B) & BIT_MASK_AC0_PKT_INFO_8822B) +#define BIT_SET_AC0_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC0_PKT_INFO_8822B(x) | BIT_AC0_PKT_INFO_8822B(v)) /* 2 REG_Q2_Q3_INFO_8822B */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31) #define BIT_SHIFT_GTAB_ID_8822B 28 #define BIT_MASK_GTAB_ID_8822B 0x7 -#define BIT_GTAB_ID_8822B(x) (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) -#define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) - - +#define BIT_GTAB_ID_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) +#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B) +#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B)) +#define BIT_GET_GTAB_ID_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) +#define BIT_SET_GTAB_ID_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v)) #define BIT_SHIFT_AC3_PKT_INFO_8822B 16 #define BIT_MASK_AC3_PKT_INFO_8822B 0xfff -#define BIT_AC3_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC3_PKT_INFO_8822B) << BIT_SHIFT_AC3_PKT_INFO_8822B) -#define BIT_GET_AC3_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8822B) & BIT_MASK_AC3_PKT_INFO_8822B) - +#define BIT_AC3_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC3_PKT_INFO_8822B) << BIT_SHIFT_AC3_PKT_INFO_8822B) +#define BITS_AC3_PKT_INFO_8822B \ + (BIT_MASK_AC3_PKT_INFO_8822B << BIT_SHIFT_AC3_PKT_INFO_8822B) +#define BIT_CLEAR_AC3_PKT_INFO_8822B(x) ((x) & (~BITS_AC3_PKT_INFO_8822B)) +#define BIT_GET_AC3_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC3_PKT_INFO_8822B) & BIT_MASK_AC3_PKT_INFO_8822B) +#define BIT_SET_AC3_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC3_PKT_INFO_8822B(x) | BIT_AC3_PKT_INFO_8822B(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8822B 12 #define BIT_MASK_GTAB_ID_V1_8822B 0x7 -#define BIT_GTAB_ID_V1_8822B(x) (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) -#define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) - - +#define BIT_GTAB_ID_V1_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BITS_GTAB_ID_V1_8822B \ + (BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B)) +#define BIT_GET_GTAB_ID_V1_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) +#define BIT_SET_GTAB_ID_V1_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v)) #define BIT_SHIFT_AC2_PKT_INFO_8822B 0 #define BIT_MASK_AC2_PKT_INFO_8822B 0xfff -#define BIT_AC2_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC2_PKT_INFO_8822B) << BIT_SHIFT_AC2_PKT_INFO_8822B) -#define BIT_GET_AC2_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8822B) & BIT_MASK_AC2_PKT_INFO_8822B) - - +#define BIT_AC2_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC2_PKT_INFO_8822B) << BIT_SHIFT_AC2_PKT_INFO_8822B) +#define BITS_AC2_PKT_INFO_8822B \ + (BIT_MASK_AC2_PKT_INFO_8822B << BIT_SHIFT_AC2_PKT_INFO_8822B) +#define BIT_CLEAR_AC2_PKT_INFO_8822B(x) ((x) & (~BITS_AC2_PKT_INFO_8822B)) +#define BIT_GET_AC2_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC2_PKT_INFO_8822B) & BIT_MASK_AC2_PKT_INFO_8822B) +#define BIT_SET_AC2_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC2_PKT_INFO_8822B(x) | BIT_AC2_PKT_INFO_8822B(v)) /* 2 REG_Q4_Q5_INFO_8822B */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31) #define BIT_SHIFT_GTAB_ID_8822B 28 #define BIT_MASK_GTAB_ID_8822B 0x7 -#define BIT_GTAB_ID_8822B(x) (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) -#define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) - - +#define BIT_GTAB_ID_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) +#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B) +#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B)) +#define BIT_GET_GTAB_ID_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) +#define BIT_SET_GTAB_ID_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v)) #define BIT_SHIFT_AC5_PKT_INFO_8822B 16 #define BIT_MASK_AC5_PKT_INFO_8822B 0xfff -#define BIT_AC5_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC5_PKT_INFO_8822B) << BIT_SHIFT_AC5_PKT_INFO_8822B) -#define BIT_GET_AC5_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8822B) & BIT_MASK_AC5_PKT_INFO_8822B) - +#define BIT_AC5_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC5_PKT_INFO_8822B) << BIT_SHIFT_AC5_PKT_INFO_8822B) +#define BITS_AC5_PKT_INFO_8822B \ + (BIT_MASK_AC5_PKT_INFO_8822B << BIT_SHIFT_AC5_PKT_INFO_8822B) +#define BIT_CLEAR_AC5_PKT_INFO_8822B(x) ((x) & (~BITS_AC5_PKT_INFO_8822B)) +#define BIT_GET_AC5_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC5_PKT_INFO_8822B) & BIT_MASK_AC5_PKT_INFO_8822B) +#define BIT_SET_AC5_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC5_PKT_INFO_8822B(x) | BIT_AC5_PKT_INFO_8822B(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8822B 12 #define BIT_MASK_GTAB_ID_V1_8822B 0x7 -#define BIT_GTAB_ID_V1_8822B(x) (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) -#define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) - - +#define BIT_GTAB_ID_V1_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BITS_GTAB_ID_V1_8822B \ + (BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B)) +#define BIT_GET_GTAB_ID_V1_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) +#define BIT_SET_GTAB_ID_V1_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v)) #define BIT_SHIFT_AC4_PKT_INFO_8822B 0 #define BIT_MASK_AC4_PKT_INFO_8822B 0xfff -#define BIT_AC4_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC4_PKT_INFO_8822B) << BIT_SHIFT_AC4_PKT_INFO_8822B) -#define BIT_GET_AC4_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8822B) & BIT_MASK_AC4_PKT_INFO_8822B) - - +#define BIT_AC4_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC4_PKT_INFO_8822B) << BIT_SHIFT_AC4_PKT_INFO_8822B) +#define BITS_AC4_PKT_INFO_8822B \ + (BIT_MASK_AC4_PKT_INFO_8822B << BIT_SHIFT_AC4_PKT_INFO_8822B) +#define BIT_CLEAR_AC4_PKT_INFO_8822B(x) ((x) & (~BITS_AC4_PKT_INFO_8822B)) +#define BIT_GET_AC4_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC4_PKT_INFO_8822B) & BIT_MASK_AC4_PKT_INFO_8822B) +#define BIT_SET_AC4_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC4_PKT_INFO_8822B(x) | BIT_AC4_PKT_INFO_8822B(v)) /* 2 REG_Q6_Q7_INFO_8822B */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31) #define BIT_SHIFT_GTAB_ID_8822B 28 #define BIT_MASK_GTAB_ID_8822B 0x7 -#define BIT_GTAB_ID_8822B(x) (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) -#define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) - - +#define BIT_GTAB_ID_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) +#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B) +#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B)) +#define BIT_GET_GTAB_ID_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) +#define BIT_SET_GTAB_ID_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v)) #define BIT_SHIFT_AC7_PKT_INFO_8822B 16 #define BIT_MASK_AC7_PKT_INFO_8822B 0xfff -#define BIT_AC7_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC7_PKT_INFO_8822B) << BIT_SHIFT_AC7_PKT_INFO_8822B) -#define BIT_GET_AC7_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8822B) & BIT_MASK_AC7_PKT_INFO_8822B) - +#define BIT_AC7_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC7_PKT_INFO_8822B) << BIT_SHIFT_AC7_PKT_INFO_8822B) +#define BITS_AC7_PKT_INFO_8822B \ + (BIT_MASK_AC7_PKT_INFO_8822B << BIT_SHIFT_AC7_PKT_INFO_8822B) +#define BIT_CLEAR_AC7_PKT_INFO_8822B(x) ((x) & (~BITS_AC7_PKT_INFO_8822B)) +#define BIT_GET_AC7_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC7_PKT_INFO_8822B) & BIT_MASK_AC7_PKT_INFO_8822B) +#define BIT_SET_AC7_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC7_PKT_INFO_8822B(x) | BIT_AC7_PKT_INFO_8822B(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8822B 12 #define BIT_MASK_GTAB_ID_V1_8822B 0x7 -#define BIT_GTAB_ID_V1_8822B(x) (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) -#define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) - - +#define BIT_GTAB_ID_V1_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BITS_GTAB_ID_V1_8822B \ + (BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B)) +#define BIT_GET_GTAB_ID_V1_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) +#define BIT_SET_GTAB_ID_V1_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v)) #define BIT_SHIFT_AC6_PKT_INFO_8822B 0 #define BIT_MASK_AC6_PKT_INFO_8822B 0xfff -#define BIT_AC6_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC6_PKT_INFO_8822B) << BIT_SHIFT_AC6_PKT_INFO_8822B) -#define BIT_GET_AC6_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8822B) & BIT_MASK_AC6_PKT_INFO_8822B) - - +#define BIT_AC6_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC6_PKT_INFO_8822B) << BIT_SHIFT_AC6_PKT_INFO_8822B) +#define BITS_AC6_PKT_INFO_8822B \ + (BIT_MASK_AC6_PKT_INFO_8822B << BIT_SHIFT_AC6_PKT_INFO_8822B) +#define BIT_CLEAR_AC6_PKT_INFO_8822B(x) ((x) & (~BITS_AC6_PKT_INFO_8822B)) +#define BIT_GET_AC6_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC6_PKT_INFO_8822B) & BIT_MASK_AC6_PKT_INFO_8822B) +#define BIT_SET_AC6_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC6_PKT_INFO_8822B(x) | BIT_AC6_PKT_INFO_8822B(v)) /* 2 REG_MGQ_HIQ_INFO_8822B */ #define BIT_SHIFT_HIQ_PKT_INFO_8822B 16 #define BIT_MASK_HIQ_PKT_INFO_8822B 0xfff -#define BIT_HIQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8822B) << BIT_SHIFT_HIQ_PKT_INFO_8822B) -#define BIT_GET_HIQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822B) & BIT_MASK_HIQ_PKT_INFO_8822B) - - +#define BIT_HIQ_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_HIQ_PKT_INFO_8822B) << BIT_SHIFT_HIQ_PKT_INFO_8822B) +#define BITS_HIQ_PKT_INFO_8822B \ + (BIT_MASK_HIQ_PKT_INFO_8822B << BIT_SHIFT_HIQ_PKT_INFO_8822B) +#define BIT_CLEAR_HIQ_PKT_INFO_8822B(x) ((x) & (~BITS_HIQ_PKT_INFO_8822B)) +#define BIT_GET_HIQ_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822B) & BIT_MASK_HIQ_PKT_INFO_8822B) +#define BIT_SET_HIQ_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_HIQ_PKT_INFO_8822B(x) | BIT_HIQ_PKT_INFO_8822B(v)) #define BIT_SHIFT_MGQ_PKT_INFO_8822B 0 #define BIT_MASK_MGQ_PKT_INFO_8822B 0xfff -#define BIT_MGQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8822B) << BIT_SHIFT_MGQ_PKT_INFO_8822B) -#define BIT_GET_MGQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822B) & BIT_MASK_MGQ_PKT_INFO_8822B) - - +#define BIT_MGQ_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_MGQ_PKT_INFO_8822B) << BIT_SHIFT_MGQ_PKT_INFO_8822B) +#define BITS_MGQ_PKT_INFO_8822B \ + (BIT_MASK_MGQ_PKT_INFO_8822B << BIT_SHIFT_MGQ_PKT_INFO_8822B) +#define BIT_CLEAR_MGQ_PKT_INFO_8822B(x) ((x) & (~BITS_MGQ_PKT_INFO_8822B)) +#define BIT_GET_MGQ_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822B) & BIT_MASK_MGQ_PKT_INFO_8822B) +#define BIT_SET_MGQ_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_MGQ_PKT_INFO_8822B(x) | BIT_MGQ_PKT_INFO_8822B(v)) /* 2 REG_CMDQ_BCNQ_INFO_8822B */ #define BIT_SHIFT_CMDQ_PKT_INFO_8822B 16 #define BIT_MASK_CMDQ_PKT_INFO_8822B 0xfff -#define BIT_CMDQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_8822B) << BIT_SHIFT_CMDQ_PKT_INFO_8822B) -#define BIT_GET_CMDQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822B) & BIT_MASK_CMDQ_PKT_INFO_8822B) - - +#define BIT_CMDQ_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_CMDQ_PKT_INFO_8822B) << BIT_SHIFT_CMDQ_PKT_INFO_8822B) +#define BITS_CMDQ_PKT_INFO_8822B \ + (BIT_MASK_CMDQ_PKT_INFO_8822B << BIT_SHIFT_CMDQ_PKT_INFO_8822B) +#define BIT_CLEAR_CMDQ_PKT_INFO_8822B(x) ((x) & (~BITS_CMDQ_PKT_INFO_8822B)) +#define BIT_GET_CMDQ_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822B) & BIT_MASK_CMDQ_PKT_INFO_8822B) +#define BIT_SET_CMDQ_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_CMDQ_PKT_INFO_8822B(x) | BIT_CMDQ_PKT_INFO_8822B(v)) #define BIT_SHIFT_BCNQ_PKT_INFO_8822B 0 #define BIT_MASK_BCNQ_PKT_INFO_8822B 0xfff -#define BIT_BCNQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_8822B) << BIT_SHIFT_BCNQ_PKT_INFO_8822B) -#define BIT_GET_BCNQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822B) & BIT_MASK_BCNQ_PKT_INFO_8822B) - - +#define BIT_BCNQ_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_BCNQ_PKT_INFO_8822B) << BIT_SHIFT_BCNQ_PKT_INFO_8822B) +#define BITS_BCNQ_PKT_INFO_8822B \ + (BIT_MASK_BCNQ_PKT_INFO_8822B << BIT_SHIFT_BCNQ_PKT_INFO_8822B) +#define BIT_CLEAR_BCNQ_PKT_INFO_8822B(x) ((x) & (~BITS_BCNQ_PKT_INFO_8822B)) +#define BIT_GET_BCNQ_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822B) & BIT_MASK_BCNQ_PKT_INFO_8822B) +#define BIT_SET_BCNQ_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_BCNQ_PKT_INFO_8822B(x) | BIT_BCNQ_PKT_INFO_8822B(v)) /* 2 REG_USEREG_SETTING_8822B */ #define BIT_NDPA_USEREG_8822B BIT(21) #define BIT_SHIFT_RETRY_USEREG_8822B 19 #define BIT_MASK_RETRY_USEREG_8822B 0x3 -#define BIT_RETRY_USEREG_8822B(x) (((x) & BIT_MASK_RETRY_USEREG_8822B) << BIT_SHIFT_RETRY_USEREG_8822B) -#define BIT_GET_RETRY_USEREG_8822B(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8822B) & BIT_MASK_RETRY_USEREG_8822B) - - +#define BIT_RETRY_USEREG_8822B(x) \ + (((x) & BIT_MASK_RETRY_USEREG_8822B) << BIT_SHIFT_RETRY_USEREG_8822B) +#define BITS_RETRY_USEREG_8822B \ + (BIT_MASK_RETRY_USEREG_8822B << BIT_SHIFT_RETRY_USEREG_8822B) +#define BIT_CLEAR_RETRY_USEREG_8822B(x) ((x) & (~BITS_RETRY_USEREG_8822B)) +#define BIT_GET_RETRY_USEREG_8822B(x) \ + (((x) >> BIT_SHIFT_RETRY_USEREG_8822B) & BIT_MASK_RETRY_USEREG_8822B) +#define BIT_SET_RETRY_USEREG_8822B(x, v) \ + (BIT_CLEAR_RETRY_USEREG_8822B(x) | BIT_RETRY_USEREG_8822B(v)) #define BIT_SHIFT_TRYPKT_USEREG_8822B 17 #define BIT_MASK_TRYPKT_USEREG_8822B 0x3 -#define BIT_TRYPKT_USEREG_8822B(x) (((x) & BIT_MASK_TRYPKT_USEREG_8822B) << BIT_SHIFT_TRYPKT_USEREG_8822B) -#define BIT_GET_TRYPKT_USEREG_8822B(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8822B) & BIT_MASK_TRYPKT_USEREG_8822B) - +#define BIT_TRYPKT_USEREG_8822B(x) \ + (((x) & BIT_MASK_TRYPKT_USEREG_8822B) << BIT_SHIFT_TRYPKT_USEREG_8822B) +#define BITS_TRYPKT_USEREG_8822B \ + (BIT_MASK_TRYPKT_USEREG_8822B << BIT_SHIFT_TRYPKT_USEREG_8822B) +#define BIT_CLEAR_TRYPKT_USEREG_8822B(x) ((x) & (~BITS_TRYPKT_USEREG_8822B)) +#define BIT_GET_TRYPKT_USEREG_8822B(x) \ + (((x) >> BIT_SHIFT_TRYPKT_USEREG_8822B) & BIT_MASK_TRYPKT_USEREG_8822B) +#define BIT_SET_TRYPKT_USEREG_8822B(x, v) \ + (BIT_CLEAR_TRYPKT_USEREG_8822B(x) | BIT_TRYPKT_USEREG_8822B(v)) #define BIT_CTLPKT_USEREG_8822B BIT(16) @@ -6602,10 +10195,15 @@ #define BIT_SHIFT_AESIV_OFFSET_8822B 0 #define BIT_MASK_AESIV_OFFSET_8822B 0xfff -#define BIT_AESIV_OFFSET_8822B(x) (((x) & BIT_MASK_AESIV_OFFSET_8822B) << BIT_SHIFT_AESIV_OFFSET_8822B) -#define BIT_GET_AESIV_OFFSET_8822B(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8822B) & BIT_MASK_AESIV_OFFSET_8822B) - - +#define BIT_AESIV_OFFSET_8822B(x) \ + (((x) & BIT_MASK_AESIV_OFFSET_8822B) << BIT_SHIFT_AESIV_OFFSET_8822B) +#define BITS_AESIV_OFFSET_8822B \ + (BIT_MASK_AESIV_OFFSET_8822B << BIT_SHIFT_AESIV_OFFSET_8822B) +#define BIT_CLEAR_AESIV_OFFSET_8822B(x) ((x) & (~BITS_AESIV_OFFSET_8822B)) +#define BIT_GET_AESIV_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_AESIV_OFFSET_8822B) & BIT_MASK_AESIV_OFFSET_8822B) +#define BIT_SET_AESIV_OFFSET_8822B(x, v) \ + (BIT_CLEAR_AESIV_OFFSET_8822B(x) | BIT_AESIV_OFFSET_8822B(v)) /* 2 REG_BF0_TIME_SETTING_8822B */ #define BIT_BF0_TIMER_SET_8822B BIT(31) @@ -6615,17 +10213,30 @@ #define BIT_SHIFT_BF0_PRETIME_OVER_8822B 16 #define BIT_MASK_BF0_PRETIME_OVER_8822B 0xfff -#define BIT_BF0_PRETIME_OVER_8822B(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8822B) << BIT_SHIFT_BF0_PRETIME_OVER_8822B) -#define BIT_GET_BF0_PRETIME_OVER_8822B(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822B) & BIT_MASK_BF0_PRETIME_OVER_8822B) - - +#define BIT_BF0_PRETIME_OVER_8822B(x) \ + (((x) & BIT_MASK_BF0_PRETIME_OVER_8822B) \ + << BIT_SHIFT_BF0_PRETIME_OVER_8822B) +#define BITS_BF0_PRETIME_OVER_8822B \ + (BIT_MASK_BF0_PRETIME_OVER_8822B << BIT_SHIFT_BF0_PRETIME_OVER_8822B) +#define BIT_CLEAR_BF0_PRETIME_OVER_8822B(x) \ + ((x) & (~BITS_BF0_PRETIME_OVER_8822B)) +#define BIT_GET_BF0_PRETIME_OVER_8822B(x) \ + (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822B) & \ + BIT_MASK_BF0_PRETIME_OVER_8822B) +#define BIT_SET_BF0_PRETIME_OVER_8822B(x, v) \ + (BIT_CLEAR_BF0_PRETIME_OVER_8822B(x) | BIT_BF0_PRETIME_OVER_8822B(v)) #define BIT_SHIFT_BF0_LIFETIME_8822B 0 #define BIT_MASK_BF0_LIFETIME_8822B 0xffff -#define BIT_BF0_LIFETIME_8822B(x) (((x) & BIT_MASK_BF0_LIFETIME_8822B) << BIT_SHIFT_BF0_LIFETIME_8822B) -#define BIT_GET_BF0_LIFETIME_8822B(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8822B) & BIT_MASK_BF0_LIFETIME_8822B) - - +#define BIT_BF0_LIFETIME_8822B(x) \ + (((x) & BIT_MASK_BF0_LIFETIME_8822B) << BIT_SHIFT_BF0_LIFETIME_8822B) +#define BITS_BF0_LIFETIME_8822B \ + (BIT_MASK_BF0_LIFETIME_8822B << BIT_SHIFT_BF0_LIFETIME_8822B) +#define BIT_CLEAR_BF0_LIFETIME_8822B(x) ((x) & (~BITS_BF0_LIFETIME_8822B)) +#define BIT_GET_BF0_LIFETIME_8822B(x) \ + (((x) >> BIT_SHIFT_BF0_LIFETIME_8822B) & BIT_MASK_BF0_LIFETIME_8822B) +#define BIT_SET_BF0_LIFETIME_8822B(x, v) \ + (BIT_CLEAR_BF0_LIFETIME_8822B(x) | BIT_BF0_LIFETIME_8822B(v)) /* 2 REG_BF1_TIME_SETTING_8822B */ #define BIT_BF1_TIMER_SET_8822B BIT(31) @@ -6635,17 +10246,30 @@ #define BIT_SHIFT_BF1_PRETIME_OVER_8822B 16 #define BIT_MASK_BF1_PRETIME_OVER_8822B 0xfff -#define BIT_BF1_PRETIME_OVER_8822B(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8822B) << BIT_SHIFT_BF1_PRETIME_OVER_8822B) -#define BIT_GET_BF1_PRETIME_OVER_8822B(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822B) & BIT_MASK_BF1_PRETIME_OVER_8822B) - - +#define BIT_BF1_PRETIME_OVER_8822B(x) \ + (((x) & BIT_MASK_BF1_PRETIME_OVER_8822B) \ + << BIT_SHIFT_BF1_PRETIME_OVER_8822B) +#define BITS_BF1_PRETIME_OVER_8822B \ + (BIT_MASK_BF1_PRETIME_OVER_8822B << BIT_SHIFT_BF1_PRETIME_OVER_8822B) +#define BIT_CLEAR_BF1_PRETIME_OVER_8822B(x) \ + ((x) & (~BITS_BF1_PRETIME_OVER_8822B)) +#define BIT_GET_BF1_PRETIME_OVER_8822B(x) \ + (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822B) & \ + BIT_MASK_BF1_PRETIME_OVER_8822B) +#define BIT_SET_BF1_PRETIME_OVER_8822B(x, v) \ + (BIT_CLEAR_BF1_PRETIME_OVER_8822B(x) | BIT_BF1_PRETIME_OVER_8822B(v)) #define BIT_SHIFT_BF1_LIFETIME_8822B 0 #define BIT_MASK_BF1_LIFETIME_8822B 0xffff -#define BIT_BF1_LIFETIME_8822B(x) (((x) & BIT_MASK_BF1_LIFETIME_8822B) << BIT_SHIFT_BF1_LIFETIME_8822B) -#define BIT_GET_BF1_LIFETIME_8822B(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8822B) & BIT_MASK_BF1_LIFETIME_8822B) - - +#define BIT_BF1_LIFETIME_8822B(x) \ + (((x) & BIT_MASK_BF1_LIFETIME_8822B) << BIT_SHIFT_BF1_LIFETIME_8822B) +#define BITS_BF1_LIFETIME_8822B \ + (BIT_MASK_BF1_LIFETIME_8822B << BIT_SHIFT_BF1_LIFETIME_8822B) +#define BIT_CLEAR_BF1_LIFETIME_8822B(x) ((x) & (~BITS_BF1_LIFETIME_8822B)) +#define BIT_GET_BF1_LIFETIME_8822B(x) \ + (((x) >> BIT_SHIFT_BF1_LIFETIME_8822B) & BIT_MASK_BF1_LIFETIME_8822B) +#define BIT_SET_BF1_LIFETIME_8822B(x, v) \ + (BIT_CLEAR_BF1_LIFETIME_8822B(x) | BIT_BF1_LIFETIME_8822B(v)) /* 2 REG_BF_TIMEOUT_EN_8822B */ #define BIT_EN_VHT_LDPC_8822B BIT(9) @@ -6657,214 +10281,434 @@ #define BIT_SHIFT_MACID31_0_RELEASE_8822B 0 #define BIT_MASK_MACID31_0_RELEASE_8822B 0xffffffffL -#define BIT_MACID31_0_RELEASE_8822B(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8822B) << BIT_SHIFT_MACID31_0_RELEASE_8822B) -#define BIT_GET_MACID31_0_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822B) & BIT_MASK_MACID31_0_RELEASE_8822B) - - +#define BIT_MACID31_0_RELEASE_8822B(x) \ + (((x) & BIT_MASK_MACID31_0_RELEASE_8822B) \ + << BIT_SHIFT_MACID31_0_RELEASE_8822B) +#define BITS_MACID31_0_RELEASE_8822B \ + (BIT_MASK_MACID31_0_RELEASE_8822B << BIT_SHIFT_MACID31_0_RELEASE_8822B) +#define BIT_CLEAR_MACID31_0_RELEASE_8822B(x) \ + ((x) & (~BITS_MACID31_0_RELEASE_8822B)) +#define BIT_GET_MACID31_0_RELEASE_8822B(x) \ + (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822B) & \ + BIT_MASK_MACID31_0_RELEASE_8822B) +#define BIT_SET_MACID31_0_RELEASE_8822B(x, v) \ + (BIT_CLEAR_MACID31_0_RELEASE_8822B(x) | BIT_MACID31_0_RELEASE_8822B(v)) /* 2 REG_MACID_RELEASE1_8822B */ #define BIT_SHIFT_MACID63_32_RELEASE_8822B 0 #define BIT_MASK_MACID63_32_RELEASE_8822B 0xffffffffL -#define BIT_MACID63_32_RELEASE_8822B(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8822B) << BIT_SHIFT_MACID63_32_RELEASE_8822B) -#define BIT_GET_MACID63_32_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822B) & BIT_MASK_MACID63_32_RELEASE_8822B) - - +#define BIT_MACID63_32_RELEASE_8822B(x) \ + (((x) & BIT_MASK_MACID63_32_RELEASE_8822B) \ + << BIT_SHIFT_MACID63_32_RELEASE_8822B) +#define BITS_MACID63_32_RELEASE_8822B \ + (BIT_MASK_MACID63_32_RELEASE_8822B \ + << BIT_SHIFT_MACID63_32_RELEASE_8822B) +#define BIT_CLEAR_MACID63_32_RELEASE_8822B(x) \ + ((x) & (~BITS_MACID63_32_RELEASE_8822B)) +#define BIT_GET_MACID63_32_RELEASE_8822B(x) \ + (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822B) & \ + BIT_MASK_MACID63_32_RELEASE_8822B) +#define BIT_SET_MACID63_32_RELEASE_8822B(x, v) \ + (BIT_CLEAR_MACID63_32_RELEASE_8822B(x) | \ + BIT_MACID63_32_RELEASE_8822B(v)) /* 2 REG_MACID_RELEASE2_8822B */ #define BIT_SHIFT_MACID95_64_RELEASE_8822B 0 #define BIT_MASK_MACID95_64_RELEASE_8822B 0xffffffffL -#define BIT_MACID95_64_RELEASE_8822B(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8822B) << BIT_SHIFT_MACID95_64_RELEASE_8822B) -#define BIT_GET_MACID95_64_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822B) & BIT_MASK_MACID95_64_RELEASE_8822B) - - +#define BIT_MACID95_64_RELEASE_8822B(x) \ + (((x) & BIT_MASK_MACID95_64_RELEASE_8822B) \ + << BIT_SHIFT_MACID95_64_RELEASE_8822B) +#define BITS_MACID95_64_RELEASE_8822B \ + (BIT_MASK_MACID95_64_RELEASE_8822B \ + << BIT_SHIFT_MACID95_64_RELEASE_8822B) +#define BIT_CLEAR_MACID95_64_RELEASE_8822B(x) \ + ((x) & (~BITS_MACID95_64_RELEASE_8822B)) +#define BIT_GET_MACID95_64_RELEASE_8822B(x) \ + (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822B) & \ + BIT_MASK_MACID95_64_RELEASE_8822B) +#define BIT_SET_MACID95_64_RELEASE_8822B(x, v) \ + (BIT_CLEAR_MACID95_64_RELEASE_8822B(x) | \ + BIT_MACID95_64_RELEASE_8822B(v)) /* 2 REG_MACID_RELEASE3_8822B */ #define BIT_SHIFT_MACID127_96_RELEASE_8822B 0 #define BIT_MASK_MACID127_96_RELEASE_8822B 0xffffffffL -#define BIT_MACID127_96_RELEASE_8822B(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8822B) << BIT_SHIFT_MACID127_96_RELEASE_8822B) -#define BIT_GET_MACID127_96_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822B) & BIT_MASK_MACID127_96_RELEASE_8822B) - - +#define BIT_MACID127_96_RELEASE_8822B(x) \ + (((x) & BIT_MASK_MACID127_96_RELEASE_8822B) \ + << BIT_SHIFT_MACID127_96_RELEASE_8822B) +#define BITS_MACID127_96_RELEASE_8822B \ + (BIT_MASK_MACID127_96_RELEASE_8822B \ + << BIT_SHIFT_MACID127_96_RELEASE_8822B) +#define BIT_CLEAR_MACID127_96_RELEASE_8822B(x) \ + ((x) & (~BITS_MACID127_96_RELEASE_8822B)) +#define BIT_GET_MACID127_96_RELEASE_8822B(x) \ + (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822B) & \ + BIT_MASK_MACID127_96_RELEASE_8822B) +#define BIT_SET_MACID127_96_RELEASE_8822B(x, v) \ + (BIT_CLEAR_MACID127_96_RELEASE_8822B(x) | \ + BIT_MACID127_96_RELEASE_8822B(v)) /* 2 REG_MACID_RELEASE_SETTING_8822B */ #define BIT_MACID_VALUE_8822B BIT(7) #define BIT_SHIFT_MACID_OFFSET_8822B 0 #define BIT_MASK_MACID_OFFSET_8822B 0x7f -#define BIT_MACID_OFFSET_8822B(x) (((x) & BIT_MASK_MACID_OFFSET_8822B) << BIT_SHIFT_MACID_OFFSET_8822B) -#define BIT_GET_MACID_OFFSET_8822B(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8822B) & BIT_MASK_MACID_OFFSET_8822B) - - +#define BIT_MACID_OFFSET_8822B(x) \ + (((x) & BIT_MASK_MACID_OFFSET_8822B) << BIT_SHIFT_MACID_OFFSET_8822B) +#define BITS_MACID_OFFSET_8822B \ + (BIT_MASK_MACID_OFFSET_8822B << BIT_SHIFT_MACID_OFFSET_8822B) +#define BIT_CLEAR_MACID_OFFSET_8822B(x) ((x) & (~BITS_MACID_OFFSET_8822B)) +#define BIT_GET_MACID_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_MACID_OFFSET_8822B) & BIT_MASK_MACID_OFFSET_8822B) +#define BIT_SET_MACID_OFFSET_8822B(x, v) \ + (BIT_CLEAR_MACID_OFFSET_8822B(x) | BIT_MACID_OFFSET_8822B(v)) /* 2 REG_FAST_EDCA_VOVI_SETTING_8822B */ #define BIT_SHIFT_VI_FAST_EDCA_TO_8822B 24 #define BIT_MASK_VI_FAST_EDCA_TO_8822B 0xff -#define BIT_VI_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8822B) << BIT_SHIFT_VI_FAST_EDCA_TO_8822B) -#define BIT_GET_VI_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822B) & BIT_MASK_VI_FAST_EDCA_TO_8822B) - +#define BIT_VI_FAST_EDCA_TO_8822B(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_TO_8822B) \ + << BIT_SHIFT_VI_FAST_EDCA_TO_8822B) +#define BITS_VI_FAST_EDCA_TO_8822B \ + (BIT_MASK_VI_FAST_EDCA_TO_8822B << BIT_SHIFT_VI_FAST_EDCA_TO_8822B) +#define BIT_CLEAR_VI_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8822B)) +#define BIT_GET_VI_FAST_EDCA_TO_8822B(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822B) & \ + BIT_MASK_VI_FAST_EDCA_TO_8822B) +#define BIT_SET_VI_FAST_EDCA_TO_8822B(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_TO_8822B(x) | BIT_VI_FAST_EDCA_TO_8822B(v)) #define BIT_VI_THRESHOLD_SEL_8822B BIT(23) #define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B 16 #define BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B 0x7f -#define BIT_VI_FAST_EDCA_PKT_TH_8822B(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) -#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B) - - +#define BIT_VI_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B) \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) +#define BITS_VI_FAST_EDCA_PKT_TH_8822B \ + (BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822B(x) \ + ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8822B)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) & \ + BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B) +#define BIT_SET_VI_FAST_EDCA_PKT_TH_8822B(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822B(x) | \ + BIT_VI_FAST_EDCA_PKT_TH_8822B(v)) #define BIT_SHIFT_VO_FAST_EDCA_TO_8822B 8 #define BIT_MASK_VO_FAST_EDCA_TO_8822B 0xff -#define BIT_VO_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8822B) << BIT_SHIFT_VO_FAST_EDCA_TO_8822B) -#define BIT_GET_VO_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822B) & BIT_MASK_VO_FAST_EDCA_TO_8822B) - +#define BIT_VO_FAST_EDCA_TO_8822B(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO_8822B) \ + << BIT_SHIFT_VO_FAST_EDCA_TO_8822B) +#define BITS_VO_FAST_EDCA_TO_8822B \ + (BIT_MASK_VO_FAST_EDCA_TO_8822B << BIT_SHIFT_VO_FAST_EDCA_TO_8822B) +#define BIT_CLEAR_VO_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8822B)) +#define BIT_GET_VO_FAST_EDCA_TO_8822B(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822B) & \ + BIT_MASK_VO_FAST_EDCA_TO_8822B) +#define BIT_SET_VO_FAST_EDCA_TO_8822B(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO_8822B(x) | BIT_VO_FAST_EDCA_TO_8822B(v)) #define BIT_VO_THRESHOLD_SEL_8822B BIT(7) #define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B 0 #define BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B 0x7f -#define BIT_VO_FAST_EDCA_PKT_TH_8822B(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) -#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B) - - +#define BIT_VO_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B) \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) +#define BITS_VO_FAST_EDCA_PKT_TH_8822B \ + (BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822B(x) \ + ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8822B)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) & \ + BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B) +#define BIT_SET_VO_FAST_EDCA_PKT_TH_8822B(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822B(x) | \ + BIT_VO_FAST_EDCA_PKT_TH_8822B(v)) /* 2 REG_FAST_EDCA_BEBK_SETTING_8822B */ #define BIT_SHIFT_BK_FAST_EDCA_TO_8822B 24 #define BIT_MASK_BK_FAST_EDCA_TO_8822B 0xff -#define BIT_BK_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8822B) << BIT_SHIFT_BK_FAST_EDCA_TO_8822B) -#define BIT_GET_BK_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822B) & BIT_MASK_BK_FAST_EDCA_TO_8822B) - +#define BIT_BK_FAST_EDCA_TO_8822B(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_TO_8822B) \ + << BIT_SHIFT_BK_FAST_EDCA_TO_8822B) +#define BITS_BK_FAST_EDCA_TO_8822B \ + (BIT_MASK_BK_FAST_EDCA_TO_8822B << BIT_SHIFT_BK_FAST_EDCA_TO_8822B) +#define BIT_CLEAR_BK_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8822B)) +#define BIT_GET_BK_FAST_EDCA_TO_8822B(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822B) & \ + BIT_MASK_BK_FAST_EDCA_TO_8822B) +#define BIT_SET_BK_FAST_EDCA_TO_8822B(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_TO_8822B(x) | BIT_BK_FAST_EDCA_TO_8822B(v)) #define BIT_BK_THRESHOLD_SEL_8822B BIT(23) #define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B 16 #define BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B 0x7f -#define BIT_BK_FAST_EDCA_PKT_TH_8822B(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) -#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B) - - +#define BIT_BK_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B) \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) +#define BITS_BK_FAST_EDCA_PKT_TH_8822B \ + (BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822B(x) \ + ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8822B)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) & \ + BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B) +#define BIT_SET_BK_FAST_EDCA_PKT_TH_8822B(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822B(x) | \ + BIT_BK_FAST_EDCA_PKT_TH_8822B(v)) #define BIT_SHIFT_BE_FAST_EDCA_TO_8822B 8 #define BIT_MASK_BE_FAST_EDCA_TO_8822B 0xff -#define BIT_BE_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8822B) << BIT_SHIFT_BE_FAST_EDCA_TO_8822B) -#define BIT_GET_BE_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822B) & BIT_MASK_BE_FAST_EDCA_TO_8822B) - +#define BIT_BE_FAST_EDCA_TO_8822B(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO_8822B) \ + << BIT_SHIFT_BE_FAST_EDCA_TO_8822B) +#define BITS_BE_FAST_EDCA_TO_8822B \ + (BIT_MASK_BE_FAST_EDCA_TO_8822B << BIT_SHIFT_BE_FAST_EDCA_TO_8822B) +#define BIT_CLEAR_BE_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8822B)) +#define BIT_GET_BE_FAST_EDCA_TO_8822B(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822B) & \ + BIT_MASK_BE_FAST_EDCA_TO_8822B) +#define BIT_SET_BE_FAST_EDCA_TO_8822B(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO_8822B(x) | BIT_BE_FAST_EDCA_TO_8822B(v)) #define BIT_BE_THRESHOLD_SEL_8822B BIT(7) #define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B 0 #define BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B 0x7f -#define BIT_BE_FAST_EDCA_PKT_TH_8822B(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) -#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B) - - +#define BIT_BE_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B) \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) +#define BITS_BE_FAST_EDCA_PKT_TH_8822B \ + (BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822B(x) \ + ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8822B)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) & \ + BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B) +#define BIT_SET_BE_FAST_EDCA_PKT_TH_8822B(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822B(x) | \ + BIT_BE_FAST_EDCA_PKT_TH_8822B(v)) /* 2 REG_MACID_DROP0_8822B */ #define BIT_SHIFT_MACID31_0_DROP_8822B 0 #define BIT_MASK_MACID31_0_DROP_8822B 0xffffffffL -#define BIT_MACID31_0_DROP_8822B(x) (((x) & BIT_MASK_MACID31_0_DROP_8822B) << BIT_SHIFT_MACID31_0_DROP_8822B) -#define BIT_GET_MACID31_0_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8822B) & BIT_MASK_MACID31_0_DROP_8822B) - - +#define BIT_MACID31_0_DROP_8822B(x) \ + (((x) & BIT_MASK_MACID31_0_DROP_8822B) \ + << BIT_SHIFT_MACID31_0_DROP_8822B) +#define BITS_MACID31_0_DROP_8822B \ + (BIT_MASK_MACID31_0_DROP_8822B << BIT_SHIFT_MACID31_0_DROP_8822B) +#define BIT_CLEAR_MACID31_0_DROP_8822B(x) ((x) & (~BITS_MACID31_0_DROP_8822B)) +#define BIT_GET_MACID31_0_DROP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID31_0_DROP_8822B) & \ + BIT_MASK_MACID31_0_DROP_8822B) +#define BIT_SET_MACID31_0_DROP_8822B(x, v) \ + (BIT_CLEAR_MACID31_0_DROP_8822B(x) | BIT_MACID31_0_DROP_8822B(v)) /* 2 REG_MACID_DROP1_8822B */ #define BIT_SHIFT_MACID63_32_DROP_8822B 0 #define BIT_MASK_MACID63_32_DROP_8822B 0xffffffffL -#define BIT_MACID63_32_DROP_8822B(x) (((x) & BIT_MASK_MACID63_32_DROP_8822B) << BIT_SHIFT_MACID63_32_DROP_8822B) -#define BIT_GET_MACID63_32_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8822B) & BIT_MASK_MACID63_32_DROP_8822B) - - +#define BIT_MACID63_32_DROP_8822B(x) \ + (((x) & BIT_MASK_MACID63_32_DROP_8822B) \ + << BIT_SHIFT_MACID63_32_DROP_8822B) +#define BITS_MACID63_32_DROP_8822B \ + (BIT_MASK_MACID63_32_DROP_8822B << BIT_SHIFT_MACID63_32_DROP_8822B) +#define BIT_CLEAR_MACID63_32_DROP_8822B(x) ((x) & (~BITS_MACID63_32_DROP_8822B)) +#define BIT_GET_MACID63_32_DROP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID63_32_DROP_8822B) & \ + BIT_MASK_MACID63_32_DROP_8822B) +#define BIT_SET_MACID63_32_DROP_8822B(x, v) \ + (BIT_CLEAR_MACID63_32_DROP_8822B(x) | BIT_MACID63_32_DROP_8822B(v)) /* 2 REG_MACID_DROP2_8822B */ #define BIT_SHIFT_MACID95_64_DROP_8822B 0 #define BIT_MASK_MACID95_64_DROP_8822B 0xffffffffL -#define BIT_MACID95_64_DROP_8822B(x) (((x) & BIT_MASK_MACID95_64_DROP_8822B) << BIT_SHIFT_MACID95_64_DROP_8822B) -#define BIT_GET_MACID95_64_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8822B) & BIT_MASK_MACID95_64_DROP_8822B) - - +#define BIT_MACID95_64_DROP_8822B(x) \ + (((x) & BIT_MASK_MACID95_64_DROP_8822B) \ + << BIT_SHIFT_MACID95_64_DROP_8822B) +#define BITS_MACID95_64_DROP_8822B \ + (BIT_MASK_MACID95_64_DROP_8822B << BIT_SHIFT_MACID95_64_DROP_8822B) +#define BIT_CLEAR_MACID95_64_DROP_8822B(x) ((x) & (~BITS_MACID95_64_DROP_8822B)) +#define BIT_GET_MACID95_64_DROP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID95_64_DROP_8822B) & \ + BIT_MASK_MACID95_64_DROP_8822B) +#define BIT_SET_MACID95_64_DROP_8822B(x, v) \ + (BIT_CLEAR_MACID95_64_DROP_8822B(x) | BIT_MACID95_64_DROP_8822B(v)) /* 2 REG_MACID_DROP3_8822B */ #define BIT_SHIFT_MACID127_96_DROP_8822B 0 #define BIT_MASK_MACID127_96_DROP_8822B 0xffffffffL -#define BIT_MACID127_96_DROP_8822B(x) (((x) & BIT_MASK_MACID127_96_DROP_8822B) << BIT_SHIFT_MACID127_96_DROP_8822B) -#define BIT_GET_MACID127_96_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8822B) & BIT_MASK_MACID127_96_DROP_8822B) - - +#define BIT_MACID127_96_DROP_8822B(x) \ + (((x) & BIT_MASK_MACID127_96_DROP_8822B) \ + << BIT_SHIFT_MACID127_96_DROP_8822B) +#define BITS_MACID127_96_DROP_8822B \ + (BIT_MASK_MACID127_96_DROP_8822B << BIT_SHIFT_MACID127_96_DROP_8822B) +#define BIT_CLEAR_MACID127_96_DROP_8822B(x) \ + ((x) & (~BITS_MACID127_96_DROP_8822B)) +#define BIT_GET_MACID127_96_DROP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID127_96_DROP_8822B) & \ + BIT_MASK_MACID127_96_DROP_8822B) +#define BIT_SET_MACID127_96_DROP_8822B(x, v) \ + (BIT_CLEAR_MACID127_96_DROP_8822B(x) | BIT_MACID127_96_DROP_8822B(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_0_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_0_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B) - - +#define BIT_R_MACID_RELEASE_SUCCESS_0_8822B(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) +#define BITS_R_MACID_RELEASE_SUCCESS_0_8822B \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822B(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8822B)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822B(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8822B(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822B(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_0_8822B(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_1_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_1_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B) - - +#define BIT_R_MACID_RELEASE_SUCCESS_1_8822B(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) +#define BITS_R_MACID_RELEASE_SUCCESS_1_8822B \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822B(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8822B)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822B(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8822B(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822B(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_1_8822B(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_2_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_2_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B) - - +#define BIT_R_MACID_RELEASE_SUCCESS_2_8822B(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) +#define BITS_R_MACID_RELEASE_SUCCESS_2_8822B \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822B(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8822B)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822B(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8822B(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822B(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_2_8822B(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_3_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_3_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B) - - +#define BIT_R_MACID_RELEASE_SUCCESS_3_8822B(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) +#define BITS_R_MACID_RELEASE_SUCCESS_3_8822B \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822B(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8822B)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822B(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8822B(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822B(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_3_8822B(v)) /* 2 REG_MGG_FIFO_CRTL_8822B */ #define BIT_R_MGG_FIFO_EN_8822B BIT(31) #define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B 28 #define BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B 0x7 -#define BIT_R_MGG_FIFO_PG_SIZE_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) -#define BIT_GET_R_MGG_FIFO_PG_SIZE_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B) - - +#define BIT_R_MGG_FIFO_PG_SIZE_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) +#define BITS_R_MGG_FIFO_PG_SIZE_8822B \ + (BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B \ + << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) +#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8822B(x) \ + ((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8822B)) +#define BIT_GET_R_MGG_FIFO_PG_SIZE_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) & \ + BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B) +#define BIT_SET_R_MGG_FIFO_PG_SIZE_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8822B(x) | \ + BIT_R_MGG_FIFO_PG_SIZE_8822B(v)) #define BIT_SHIFT_R_MGG_FIFO_START_PG_8822B 16 #define BIT_MASK_R_MGG_FIFO_START_PG_8822B 0xfff -#define BIT_R_MGG_FIFO_START_PG_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8822B) << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) -#define BIT_GET_R_MGG_FIFO_START_PG_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) & BIT_MASK_R_MGG_FIFO_START_PG_8822B) - - +#define BIT_R_MGG_FIFO_START_PG_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) +#define BITS_R_MGG_FIFO_START_PG_8822B \ + (BIT_MASK_R_MGG_FIFO_START_PG_8822B \ + << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) +#define BIT_CLEAR_R_MGG_FIFO_START_PG_8822B(x) \ + ((x) & (~BITS_R_MGG_FIFO_START_PG_8822B)) +#define BIT_GET_R_MGG_FIFO_START_PG_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) & \ + BIT_MASK_R_MGG_FIFO_START_PG_8822B) +#define BIT_SET_R_MGG_FIFO_START_PG_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_START_PG_8822B(x) | \ + BIT_R_MGG_FIFO_START_PG_8822B(v)) #define BIT_SHIFT_R_MGG_FIFO_SIZE_8822B 14 #define BIT_MASK_R_MGG_FIFO_SIZE_8822B 0x3 -#define BIT_R_MGG_FIFO_SIZE_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8822B) << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) -#define BIT_GET_R_MGG_FIFO_SIZE_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) & BIT_MASK_R_MGG_FIFO_SIZE_8822B) - +#define BIT_R_MGG_FIFO_SIZE_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) +#define BITS_R_MGG_FIFO_SIZE_8822B \ + (BIT_MASK_R_MGG_FIFO_SIZE_8822B << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) +#define BIT_CLEAR_R_MGG_FIFO_SIZE_8822B(x) ((x) & (~BITS_R_MGG_FIFO_SIZE_8822B)) +#define BIT_GET_R_MGG_FIFO_SIZE_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) & \ + BIT_MASK_R_MGG_FIFO_SIZE_8822B) +#define BIT_SET_R_MGG_FIFO_SIZE_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_SIZE_8822B(x) | BIT_R_MGG_FIFO_SIZE_8822B(v)) #define BIT_R_MGG_FIFO_PAUSE_8822B BIT(13) #define BIT_SHIFT_R_MGG_FIFO_RPTR_8822B 8 #define BIT_MASK_R_MGG_FIFO_RPTR_8822B 0x1f -#define BIT_R_MGG_FIFO_RPTR_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8822B) << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) -#define BIT_GET_R_MGG_FIFO_RPTR_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) & BIT_MASK_R_MGG_FIFO_RPTR_8822B) - +#define BIT_R_MGG_FIFO_RPTR_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) +#define BITS_R_MGG_FIFO_RPTR_8822B \ + (BIT_MASK_R_MGG_FIFO_RPTR_8822B << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) +#define BIT_CLEAR_R_MGG_FIFO_RPTR_8822B(x) ((x) & (~BITS_R_MGG_FIFO_RPTR_8822B)) +#define BIT_GET_R_MGG_FIFO_RPTR_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) & \ + BIT_MASK_R_MGG_FIFO_RPTR_8822B) +#define BIT_SET_R_MGG_FIFO_RPTR_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_RPTR_8822B(x) | BIT_R_MGG_FIFO_RPTR_8822B(v)) #define BIT_R_MGG_FIFO_OV_8822B BIT(7) #define BIT_R_MGG_FIFO_WPTR_ERROR_8822B BIT(6) @@ -6872,70 +10716,305 @@ #define BIT_SHIFT_R_MGG_FIFO_WPTR_8822B 0 #define BIT_MASK_R_MGG_FIFO_WPTR_8822B 0x1f -#define BIT_R_MGG_FIFO_WPTR_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8822B) << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) -#define BIT_GET_R_MGG_FIFO_WPTR_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) & BIT_MASK_R_MGG_FIFO_WPTR_8822B) - - +#define BIT_R_MGG_FIFO_WPTR_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) +#define BITS_R_MGG_FIFO_WPTR_8822B \ + (BIT_MASK_R_MGG_FIFO_WPTR_8822B << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) +#define BIT_CLEAR_R_MGG_FIFO_WPTR_8822B(x) ((x) & (~BITS_R_MGG_FIFO_WPTR_8822B)) +#define BIT_GET_R_MGG_FIFO_WPTR_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) & \ + BIT_MASK_R_MGG_FIFO_WPTR_8822B) +#define BIT_SET_R_MGG_FIFO_WPTR_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_WPTR_8822B(x) | BIT_R_MGG_FIFO_WPTR_8822B(v)) /* 2 REG_MGG_FIFO_INT_8822B */ #define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B 16 #define BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B 0xffff -#define BIT_R_MGG_FIFO_INT_FLAG_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) -#define BIT_GET_R_MGG_FIFO_INT_FLAG_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B) - - +#define BIT_R_MGG_FIFO_INT_FLAG_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) +#define BITS_R_MGG_FIFO_INT_FLAG_8822B \ + (BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B \ + << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) +#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8822B(x) \ + ((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8822B)) +#define BIT_GET_R_MGG_FIFO_INT_FLAG_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) & \ + BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B) +#define BIT_SET_R_MGG_FIFO_INT_FLAG_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8822B(x) | \ + BIT_R_MGG_FIFO_INT_FLAG_8822B(v)) #define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B 0 #define BIT_MASK_R_MGG_FIFO_INT_MASK_8822B 0xffff -#define BIT_R_MGG_FIFO_INT_MASK_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) -#define BIT_GET_R_MGG_FIFO_INT_MASK_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) - - +#define BIT_R_MGG_FIFO_INT_MASK_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) +#define BITS_R_MGG_FIFO_INT_MASK_8822B \ + (BIT_MASK_R_MGG_FIFO_INT_MASK_8822B \ + << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) +#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8822B(x) \ + ((x) & (~BITS_R_MGG_FIFO_INT_MASK_8822B)) +#define BIT_GET_R_MGG_FIFO_INT_MASK_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) & \ + BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) +#define BIT_SET_R_MGG_FIFO_INT_MASK_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_INT_MASK_8822B(x) | \ + BIT_R_MGG_FIFO_INT_MASK_8822B(v)) /* 2 REG_MGG_FIFO_LIFETIME_8822B */ #define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B 16 #define BIT_MASK_R_MGG_FIFO_LIFETIME_8822B 0xffff -#define BIT_R_MGG_FIFO_LIFETIME_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) -#define BIT_GET_R_MGG_FIFO_LIFETIME_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B) - - +#define BIT_R_MGG_FIFO_LIFETIME_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) +#define BITS_R_MGG_FIFO_LIFETIME_8822B \ + (BIT_MASK_R_MGG_FIFO_LIFETIME_8822B \ + << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) +#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8822B(x) \ + ((x) & (~BITS_R_MGG_FIFO_LIFETIME_8822B)) +#define BIT_GET_R_MGG_FIFO_LIFETIME_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) & \ + BIT_MASK_R_MGG_FIFO_LIFETIME_8822B) +#define BIT_SET_R_MGG_FIFO_LIFETIME_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_LIFETIME_8822B(x) | \ + BIT_R_MGG_FIFO_LIFETIME_8822B(v)) #define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B 0 #define BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B 0xffff -#define BIT_R_MGG_FIFO_VALID_MAP_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) -#define BIT_GET_R_MGG_FIFO_VALID_MAP_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) - - +#define BIT_R_MGG_FIFO_VALID_MAP_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) +#define BITS_R_MGG_FIFO_VALID_MAP_8822B \ + (BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B \ + << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) +#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8822B(x) \ + ((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8822B)) +#define BIT_GET_R_MGG_FIFO_VALID_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) & \ + BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) +#define BIT_SET_R_MGG_FIFO_VALID_MAP_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8822B(x) | \ + BIT_R_MGG_FIFO_VALID_MAP_8822B(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x7f -#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) +#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(v)) + +/* 2 REG_SHCUT_SETTING_8822B */ +/* 2 REG_NOT_VALID_8822B */ +/* 2 REG_NOT_VALID_8822B */ -/* 2 REG_MACID_SHCUT_OFFSET_8822B */ +/* 2 REG_NOT_VALID_8822B */ -#define BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B 0 -#define BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B 0xff -#define BIT_MACID_SHCUT_OFFSET_V1_8822B(x) (((x) & BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B) << BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B) -#define BIT_GET_MACID_SHCUT_OFFSET_V1_8822B(x) (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B) & BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B) +/* 2 REG_NOT_VALID_8822B */ +/* 2 REG_NOT_VALID_8822B */ +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE0_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE1_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_SHCUT_LLC_OUI0_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_SHCUT_LLC_OUI1_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_SHCUT_LLC_OUI2_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_SHCUT_LLC_OUI3_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ /* 2 REG_MU_TX_CTL_8822B */ #define BIT_R_EN_REVERS_GTAB_8822B BIT(6) #define BIT_SHIFT_R_MU_TABLE_VALID_8822B 0 #define BIT_MASK_R_MU_TABLE_VALID_8822B 0x3f -#define BIT_R_MU_TABLE_VALID_8822B(x) (((x) & BIT_MASK_R_MU_TABLE_VALID_8822B) << BIT_SHIFT_R_MU_TABLE_VALID_8822B) -#define BIT_GET_R_MU_TABLE_VALID_8822B(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) & BIT_MASK_R_MU_TABLE_VALID_8822B) +#define BIT_R_MU_TABLE_VALID_8822B(x) \ + (((x) & BIT_MASK_R_MU_TABLE_VALID_8822B) \ + << BIT_SHIFT_R_MU_TABLE_VALID_8822B) +#define BITS_R_MU_TABLE_VALID_8822B \ + (BIT_MASK_R_MU_TABLE_VALID_8822B << BIT_SHIFT_R_MU_TABLE_VALID_8822B) +#define BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) \ + ((x) & (~BITS_R_MU_TABLE_VALID_8822B)) +#define BIT_GET_R_MU_TABLE_VALID_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) & \ + BIT_MASK_R_MU_TABLE_VALID_8822B) +#define BIT_SET_R_MU_TABLE_VALID_8822B(x, v) \ + (BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) | BIT_R_MU_TABLE_VALID_8822B(v)) + +/* 2 REG_MU_STA_GID_VLD_8822B */ + +/* 2 REG_NOT_VALID_8822B */ +#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0 +#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL +#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BITS_R_MU_STA_GTAB_VALID_8822B \ + (BIT_MASK_R_MU_STA_GTAB_VALID_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B)) +#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_VALID_8822B) +#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) | \ + BIT_R_MU_STA_GTAB_VALID_8822B(v)) + +#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0 +#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL +#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BITS_R_MU_STA_GTAB_VALID_8822B \ + (BIT_MASK_R_MU_STA_GTAB_VALID_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B)) +#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_VALID_8822B) +#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) | \ + BIT_R_MU_STA_GTAB_VALID_8822B(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BITS_R_MU_STA_GTAB_POSITION_8822B \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) | \ + BIT_R_MU_STA_GTAB_POSITION_8822B(v)) + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BITS_R_MU_STA_GTAB_POSITION_8822B \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) | \ + BIT_R_MU_STA_GTAB_POSITION_8822B(v)) +/* 2 REG_MU_TRX_DBG_CNT_8822B */ +#define BIT_MU_DNGCNT_RST_8822B BIT(20) + +#define BIT_SHIFT_MU_DBGCNT_SEL_8822B 16 +#define BIT_MASK_MU_DBGCNT_SEL_8822B 0xf +#define BIT_MU_DBGCNT_SEL_8822B(x) \ + (((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B) +#define BITS_MU_DBGCNT_SEL_8822B \ + (BIT_MASK_MU_DBGCNT_SEL_8822B << BIT_SHIFT_MU_DBGCNT_SEL_8822B) +#define BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) ((x) & (~BITS_MU_DBGCNT_SEL_8822B)) +#define BIT_GET_MU_DBGCNT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B) +#define BIT_SET_MU_DBGCNT_SEL_8822B(x, v) \ + (BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) | BIT_MU_DBGCNT_SEL_8822B(v)) + +#define BIT_SHIFT_MU_DNGCNT_8822B 0 +#define BIT_MASK_MU_DNGCNT_8822B 0xffff +#define BIT_MU_DNGCNT_8822B(x) \ + (((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B) +#define BITS_MU_DNGCNT_8822B \ + (BIT_MASK_MU_DNGCNT_8822B << BIT_SHIFT_MU_DNGCNT_8822B) +#define BIT_CLEAR_MU_DNGCNT_8822B(x) ((x) & (~BITS_MU_DNGCNT_8822B)) +#define BIT_GET_MU_DNGCNT_8822B(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B) +#define BIT_SET_MU_DNGCNT_8822B(x, v) \ + (BIT_CLEAR_MU_DNGCNT_8822B(x) | BIT_MU_DNGCNT_8822B(v)) + +/* 2 REG_MU_TX_CTL_8822B */ +#define BIT_R_EN_REVERS_GTAB_8822B BIT(6) + +#define BIT_SHIFT_R_MU_TABLE_VALID_8822B 0 +#define BIT_MASK_R_MU_TABLE_VALID_8822B 0x3f +#define BIT_R_MU_TABLE_VALID_8822B(x) \ + (((x) & BIT_MASK_R_MU_TABLE_VALID_8822B) \ + << BIT_SHIFT_R_MU_TABLE_VALID_8822B) +#define BITS_R_MU_TABLE_VALID_8822B \ + (BIT_MASK_R_MU_TABLE_VALID_8822B << BIT_SHIFT_R_MU_TABLE_VALID_8822B) +#define BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) \ + ((x) & (~BITS_R_MU_TABLE_VALID_8822B)) +#define BIT_GET_R_MU_TABLE_VALID_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) & \ + BIT_MASK_R_MU_TABLE_VALID_8822B) +#define BIT_SET_R_MU_TABLE_VALID_8822B(x, v) \ + (BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) | BIT_R_MU_TABLE_VALID_8822B(v)) /* 2 REG_MU_STA_GID_VLD_8822B */ @@ -6943,17 +11022,37 @@ #define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0 #define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) -#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) - - +#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BITS_R_MU_STA_GTAB_VALID_8822B \ + (BIT_MASK_R_MU_STA_GTAB_VALID_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B)) +#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_VALID_8822B) +#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) | \ + BIT_R_MU_STA_GTAB_VALID_8822B(v)) #define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0 #define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) -#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) - - +#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BITS_R_MU_STA_GTAB_VALID_8822B \ + (BIT_MASK_R_MU_STA_GTAB_VALID_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B)) +#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_VALID_8822B) +#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) | \ + BIT_R_MU_STA_GTAB_VALID_8822B(v)) /* 2 REG_MU_STA_USER_POS_INFO_8822B */ @@ -6961,34 +11060,64 @@ #define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0 #define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) -#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) - - +#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BITS_R_MU_STA_GTAB_POSITION_8822B \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) | \ + BIT_R_MU_STA_GTAB_POSITION_8822B(v)) #define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0 #define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) -#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) - - +#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BITS_R_MU_STA_GTAB_POSITION_8822B \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) | \ + BIT_R_MU_STA_GTAB_POSITION_8822B(v)) /* 2 REG_MU_TRX_DBG_CNT_8822B */ #define BIT_MU_DNGCNT_RST_8822B BIT(20) #define BIT_SHIFT_MU_DBGCNT_SEL_8822B 16 #define BIT_MASK_MU_DBGCNT_SEL_8822B 0xf -#define BIT_MU_DBGCNT_SEL_8822B(x) (((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B) -#define BIT_GET_MU_DBGCNT_SEL_8822B(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B) - - +#define BIT_MU_DBGCNT_SEL_8822B(x) \ + (((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B) +#define BITS_MU_DBGCNT_SEL_8822B \ + (BIT_MASK_MU_DBGCNT_SEL_8822B << BIT_SHIFT_MU_DBGCNT_SEL_8822B) +#define BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) ((x) & (~BITS_MU_DBGCNT_SEL_8822B)) +#define BIT_GET_MU_DBGCNT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B) +#define BIT_SET_MU_DBGCNT_SEL_8822B(x, v) \ + (BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) | BIT_MU_DBGCNT_SEL_8822B(v)) #define BIT_SHIFT_MU_DNGCNT_8822B 0 #define BIT_MASK_MU_DNGCNT_8822B 0xffff -#define BIT_MU_DNGCNT_8822B(x) (((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B) -#define BIT_GET_MU_DNGCNT_8822B(x) (((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B) - - +#define BIT_MU_DNGCNT_8822B(x) \ + (((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B) +#define BITS_MU_DNGCNT_8822B \ + (BIT_MASK_MU_DNGCNT_8822B << BIT_SHIFT_MU_DNGCNT_8822B) +#define BIT_CLEAR_MU_DNGCNT_8822B(x) ((x) & (~BITS_MU_DNGCNT_8822B)) +#define BIT_GET_MU_DNGCNT_8822B(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B) +#define BIT_SET_MU_DNGCNT_8822B(x, v) \ + (BIT_CLEAR_MU_DNGCNT_8822B(x) | BIT_MU_DNGCNT_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -6996,24 +11125,32 @@ #define BIT_SHIFT_TXOPLIMIT_8822B 16 #define BIT_MASK_TXOPLIMIT_8822B 0x7ff -#define BIT_TXOPLIMIT_8822B(x) (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) -#define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) - - +#define BIT_TXOPLIMIT_8822B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) +#define BITS_TXOPLIMIT_8822B \ + (BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B) +#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B)) +#define BIT_GET_TXOPLIMIT_8822B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) +#define BIT_SET_TXOPLIMIT_8822B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v)) #define BIT_SHIFT_CW_8822B 8 #define BIT_MASK_CW_8822B 0xff #define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) +#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B) +#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B)) #define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) - - +#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v)) #define BIT_SHIFT_AIFS_8822B 0 #define BIT_MASK_AIFS_8822B 0xff #define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) -#define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) - - +#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B) +#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B)) +#define BIT_GET_AIFS_8822B(x) \ + (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) +#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v)) /* 2 REG_EDCA_VI_PARAM_8822B */ @@ -7021,24 +11158,32 @@ #define BIT_SHIFT_TXOPLIMIT_8822B 16 #define BIT_MASK_TXOPLIMIT_8822B 0x7ff -#define BIT_TXOPLIMIT_8822B(x) (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) -#define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) - - +#define BIT_TXOPLIMIT_8822B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) +#define BITS_TXOPLIMIT_8822B \ + (BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B) +#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B)) +#define BIT_GET_TXOPLIMIT_8822B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) +#define BIT_SET_TXOPLIMIT_8822B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v)) #define BIT_SHIFT_CW_8822B 8 #define BIT_MASK_CW_8822B 0xff #define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) +#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B) +#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B)) #define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) - - +#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v)) #define BIT_SHIFT_AIFS_8822B 0 #define BIT_MASK_AIFS_8822B 0xff #define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) -#define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) - - +#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B) +#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B)) +#define BIT_GET_AIFS_8822B(x) \ + (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) +#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v)) /* 2 REG_EDCA_BE_PARAM_8822B */ @@ -7046,24 +11191,32 @@ #define BIT_SHIFT_TXOPLIMIT_8822B 16 #define BIT_MASK_TXOPLIMIT_8822B 0x7ff -#define BIT_TXOPLIMIT_8822B(x) (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) -#define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) - - +#define BIT_TXOPLIMIT_8822B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) +#define BITS_TXOPLIMIT_8822B \ + (BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B) +#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B)) +#define BIT_GET_TXOPLIMIT_8822B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) +#define BIT_SET_TXOPLIMIT_8822B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v)) #define BIT_SHIFT_CW_8822B 8 #define BIT_MASK_CW_8822B 0xff #define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) +#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B) +#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B)) #define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) - - +#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v)) #define BIT_SHIFT_AIFS_8822B 0 #define BIT_MASK_AIFS_8822B 0xff #define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) -#define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) - - +#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B) +#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B)) +#define BIT_GET_AIFS_8822B(x) \ + (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) +#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v)) /* 2 REG_EDCA_BK_PARAM_8822B */ @@ -7071,122 +11224,186 @@ #define BIT_SHIFT_TXOPLIMIT_8822B 16 #define BIT_MASK_TXOPLIMIT_8822B 0x7ff -#define BIT_TXOPLIMIT_8822B(x) (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) -#define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) - - +#define BIT_TXOPLIMIT_8822B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) +#define BITS_TXOPLIMIT_8822B \ + (BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B) +#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B)) +#define BIT_GET_TXOPLIMIT_8822B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) +#define BIT_SET_TXOPLIMIT_8822B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v)) #define BIT_SHIFT_CW_8822B 8 #define BIT_MASK_CW_8822B 0xff #define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) +#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B) +#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B)) #define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) - - +#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v)) #define BIT_SHIFT_AIFS_8822B 0 #define BIT_MASK_AIFS_8822B 0xff #define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) -#define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) - - +#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B) +#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B)) +#define BIT_GET_AIFS_8822B(x) \ + (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) +#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v)) /* 2 REG_BCNTCFG_8822B */ #define BIT_SHIFT_BCNCW_MAX_8822B 12 #define BIT_MASK_BCNCW_MAX_8822B 0xf -#define BIT_BCNCW_MAX_8822B(x) (((x) & BIT_MASK_BCNCW_MAX_8822B) << BIT_SHIFT_BCNCW_MAX_8822B) -#define BIT_GET_BCNCW_MAX_8822B(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8822B) & BIT_MASK_BCNCW_MAX_8822B) - - +#define BIT_BCNCW_MAX_8822B(x) \ + (((x) & BIT_MASK_BCNCW_MAX_8822B) << BIT_SHIFT_BCNCW_MAX_8822B) +#define BITS_BCNCW_MAX_8822B \ + (BIT_MASK_BCNCW_MAX_8822B << BIT_SHIFT_BCNCW_MAX_8822B) +#define BIT_CLEAR_BCNCW_MAX_8822B(x) ((x) & (~BITS_BCNCW_MAX_8822B)) +#define BIT_GET_BCNCW_MAX_8822B(x) \ + (((x) >> BIT_SHIFT_BCNCW_MAX_8822B) & BIT_MASK_BCNCW_MAX_8822B) +#define BIT_SET_BCNCW_MAX_8822B(x, v) \ + (BIT_CLEAR_BCNCW_MAX_8822B(x) | BIT_BCNCW_MAX_8822B(v)) #define BIT_SHIFT_BCNCW_MIN_8822B 8 #define BIT_MASK_BCNCW_MIN_8822B 0xf -#define BIT_BCNCW_MIN_8822B(x) (((x) & BIT_MASK_BCNCW_MIN_8822B) << BIT_SHIFT_BCNCW_MIN_8822B) -#define BIT_GET_BCNCW_MIN_8822B(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8822B) & BIT_MASK_BCNCW_MIN_8822B) - - +#define BIT_BCNCW_MIN_8822B(x) \ + (((x) & BIT_MASK_BCNCW_MIN_8822B) << BIT_SHIFT_BCNCW_MIN_8822B) +#define BITS_BCNCW_MIN_8822B \ + (BIT_MASK_BCNCW_MIN_8822B << BIT_SHIFT_BCNCW_MIN_8822B) +#define BIT_CLEAR_BCNCW_MIN_8822B(x) ((x) & (~BITS_BCNCW_MIN_8822B)) +#define BIT_GET_BCNCW_MIN_8822B(x) \ + (((x) >> BIT_SHIFT_BCNCW_MIN_8822B) & BIT_MASK_BCNCW_MIN_8822B) +#define BIT_SET_BCNCW_MIN_8822B(x, v) \ + (BIT_CLEAR_BCNCW_MIN_8822B(x) | BIT_BCNCW_MIN_8822B(v)) #define BIT_SHIFT_BCNIFS_8822B 0 #define BIT_MASK_BCNIFS_8822B 0xff -#define BIT_BCNIFS_8822B(x) (((x) & BIT_MASK_BCNIFS_8822B) << BIT_SHIFT_BCNIFS_8822B) -#define BIT_GET_BCNIFS_8822B(x) (((x) >> BIT_SHIFT_BCNIFS_8822B) & BIT_MASK_BCNIFS_8822B) - - +#define BIT_BCNIFS_8822B(x) \ + (((x) & BIT_MASK_BCNIFS_8822B) << BIT_SHIFT_BCNIFS_8822B) +#define BITS_BCNIFS_8822B (BIT_MASK_BCNIFS_8822B << BIT_SHIFT_BCNIFS_8822B) +#define BIT_CLEAR_BCNIFS_8822B(x) ((x) & (~BITS_BCNIFS_8822B)) +#define BIT_GET_BCNIFS_8822B(x) \ + (((x) >> BIT_SHIFT_BCNIFS_8822B) & BIT_MASK_BCNIFS_8822B) +#define BIT_SET_BCNIFS_8822B(x, v) \ + (BIT_CLEAR_BCNIFS_8822B(x) | BIT_BCNIFS_8822B(v)) /* 2 REG_PIFS_8822B */ #define BIT_SHIFT_PIFS_8822B 0 #define BIT_MASK_PIFS_8822B 0xff #define BIT_PIFS_8822B(x) (((x) & BIT_MASK_PIFS_8822B) << BIT_SHIFT_PIFS_8822B) -#define BIT_GET_PIFS_8822B(x) (((x) >> BIT_SHIFT_PIFS_8822B) & BIT_MASK_PIFS_8822B) - - +#define BITS_PIFS_8822B (BIT_MASK_PIFS_8822B << BIT_SHIFT_PIFS_8822B) +#define BIT_CLEAR_PIFS_8822B(x) ((x) & (~BITS_PIFS_8822B)) +#define BIT_GET_PIFS_8822B(x) \ + (((x) >> BIT_SHIFT_PIFS_8822B) & BIT_MASK_PIFS_8822B) +#define BIT_SET_PIFS_8822B(x, v) (BIT_CLEAR_PIFS_8822B(x) | BIT_PIFS_8822B(v)) /* 2 REG_RDG_PIFS_8822B */ #define BIT_SHIFT_RDG_PIFS_8822B 0 #define BIT_MASK_RDG_PIFS_8822B 0xff -#define BIT_RDG_PIFS_8822B(x) (((x) & BIT_MASK_RDG_PIFS_8822B) << BIT_SHIFT_RDG_PIFS_8822B) -#define BIT_GET_RDG_PIFS_8822B(x) (((x) >> BIT_SHIFT_RDG_PIFS_8822B) & BIT_MASK_RDG_PIFS_8822B) - - +#define BIT_RDG_PIFS_8822B(x) \ + (((x) & BIT_MASK_RDG_PIFS_8822B) << BIT_SHIFT_RDG_PIFS_8822B) +#define BITS_RDG_PIFS_8822B \ + (BIT_MASK_RDG_PIFS_8822B << BIT_SHIFT_RDG_PIFS_8822B) +#define BIT_CLEAR_RDG_PIFS_8822B(x) ((x) & (~BITS_RDG_PIFS_8822B)) +#define BIT_GET_RDG_PIFS_8822B(x) \ + (((x) >> BIT_SHIFT_RDG_PIFS_8822B) & BIT_MASK_RDG_PIFS_8822B) +#define BIT_SET_RDG_PIFS_8822B(x, v) \ + (BIT_CLEAR_RDG_PIFS_8822B(x) | BIT_RDG_PIFS_8822B(v)) /* 2 REG_SIFS_8822B */ #define BIT_SHIFT_SIFS_OFDM_TRX_8822B 24 #define BIT_MASK_SIFS_OFDM_TRX_8822B 0xff -#define BIT_SIFS_OFDM_TRX_8822B(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8822B) << BIT_SHIFT_SIFS_OFDM_TRX_8822B) -#define BIT_GET_SIFS_OFDM_TRX_8822B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822B) & BIT_MASK_SIFS_OFDM_TRX_8822B) - - +#define BIT_SIFS_OFDM_TRX_8822B(x) \ + (((x) & BIT_MASK_SIFS_OFDM_TRX_8822B) << BIT_SHIFT_SIFS_OFDM_TRX_8822B) +#define BITS_SIFS_OFDM_TRX_8822B \ + (BIT_MASK_SIFS_OFDM_TRX_8822B << BIT_SHIFT_SIFS_OFDM_TRX_8822B) +#define BIT_CLEAR_SIFS_OFDM_TRX_8822B(x) ((x) & (~BITS_SIFS_OFDM_TRX_8822B)) +#define BIT_GET_SIFS_OFDM_TRX_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822B) & BIT_MASK_SIFS_OFDM_TRX_8822B) +#define BIT_SET_SIFS_OFDM_TRX_8822B(x, v) \ + (BIT_CLEAR_SIFS_OFDM_TRX_8822B(x) | BIT_SIFS_OFDM_TRX_8822B(v)) #define BIT_SHIFT_SIFS_CCK_TRX_8822B 16 #define BIT_MASK_SIFS_CCK_TRX_8822B 0xff -#define BIT_SIFS_CCK_TRX_8822B(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8822B) << BIT_SHIFT_SIFS_CCK_TRX_8822B) -#define BIT_GET_SIFS_CCK_TRX_8822B(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822B) & BIT_MASK_SIFS_CCK_TRX_8822B) - - +#define BIT_SIFS_CCK_TRX_8822B(x) \ + (((x) & BIT_MASK_SIFS_CCK_TRX_8822B) << BIT_SHIFT_SIFS_CCK_TRX_8822B) +#define BITS_SIFS_CCK_TRX_8822B \ + (BIT_MASK_SIFS_CCK_TRX_8822B << BIT_SHIFT_SIFS_CCK_TRX_8822B) +#define BIT_CLEAR_SIFS_CCK_TRX_8822B(x) ((x) & (~BITS_SIFS_CCK_TRX_8822B)) +#define BIT_GET_SIFS_CCK_TRX_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822B) & BIT_MASK_SIFS_CCK_TRX_8822B) +#define BIT_SET_SIFS_CCK_TRX_8822B(x, v) \ + (BIT_CLEAR_SIFS_CCK_TRX_8822B(x) | BIT_SIFS_CCK_TRX_8822B(v)) #define BIT_SHIFT_SIFS_OFDM_CTX_8822B 8 #define BIT_MASK_SIFS_OFDM_CTX_8822B 0xff -#define BIT_SIFS_OFDM_CTX_8822B(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8822B) << BIT_SHIFT_SIFS_OFDM_CTX_8822B) -#define BIT_GET_SIFS_OFDM_CTX_8822B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822B) & BIT_MASK_SIFS_OFDM_CTX_8822B) - - +#define BIT_SIFS_OFDM_CTX_8822B(x) \ + (((x) & BIT_MASK_SIFS_OFDM_CTX_8822B) << BIT_SHIFT_SIFS_OFDM_CTX_8822B) +#define BITS_SIFS_OFDM_CTX_8822B \ + (BIT_MASK_SIFS_OFDM_CTX_8822B << BIT_SHIFT_SIFS_OFDM_CTX_8822B) +#define BIT_CLEAR_SIFS_OFDM_CTX_8822B(x) ((x) & (~BITS_SIFS_OFDM_CTX_8822B)) +#define BIT_GET_SIFS_OFDM_CTX_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822B) & BIT_MASK_SIFS_OFDM_CTX_8822B) +#define BIT_SET_SIFS_OFDM_CTX_8822B(x, v) \ + (BIT_CLEAR_SIFS_OFDM_CTX_8822B(x) | BIT_SIFS_OFDM_CTX_8822B(v)) #define BIT_SHIFT_SIFS_CCK_CTX_8822B 0 #define BIT_MASK_SIFS_CCK_CTX_8822B 0xff -#define BIT_SIFS_CCK_CTX_8822B(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8822B) << BIT_SHIFT_SIFS_CCK_CTX_8822B) -#define BIT_GET_SIFS_CCK_CTX_8822B(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822B) & BIT_MASK_SIFS_CCK_CTX_8822B) - - +#define BIT_SIFS_CCK_CTX_8822B(x) \ + (((x) & BIT_MASK_SIFS_CCK_CTX_8822B) << BIT_SHIFT_SIFS_CCK_CTX_8822B) +#define BITS_SIFS_CCK_CTX_8822B \ + (BIT_MASK_SIFS_CCK_CTX_8822B << BIT_SHIFT_SIFS_CCK_CTX_8822B) +#define BIT_CLEAR_SIFS_CCK_CTX_8822B(x) ((x) & (~BITS_SIFS_CCK_CTX_8822B)) +#define BIT_GET_SIFS_CCK_CTX_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822B) & BIT_MASK_SIFS_CCK_CTX_8822B) +#define BIT_SET_SIFS_CCK_CTX_8822B(x, v) \ + (BIT_CLEAR_SIFS_CCK_CTX_8822B(x) | BIT_SIFS_CCK_CTX_8822B(v)) /* 2 REG_TSFTR_SYN_OFFSET_8822B */ #define BIT_SHIFT_TSFTR_SNC_OFFSET_8822B 0 #define BIT_MASK_TSFTR_SNC_OFFSET_8822B 0xffff -#define BIT_TSFTR_SNC_OFFSET_8822B(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822B) << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) -#define BIT_GET_TSFTR_SNC_OFFSET_8822B(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) & BIT_MASK_TSFTR_SNC_OFFSET_8822B) - - +#define BIT_TSFTR_SNC_OFFSET_8822B(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822B) \ + << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) +#define BITS_TSFTR_SNC_OFFSET_8822B \ + (BIT_MASK_TSFTR_SNC_OFFSET_8822B << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_8822B(x) \ + ((x) & (~BITS_TSFTR_SNC_OFFSET_8822B)) +#define BIT_GET_TSFTR_SNC_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) & \ + BIT_MASK_TSFTR_SNC_OFFSET_8822B) +#define BIT_SET_TSFTR_SNC_OFFSET_8822B(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET_8822B(x) | BIT_TSFTR_SNC_OFFSET_8822B(v)) /* 2 REG_AGGR_BREAK_TIME_8822B */ #define BIT_SHIFT_AGGR_BK_TIME_8822B 0 #define BIT_MASK_AGGR_BK_TIME_8822B 0xff -#define BIT_AGGR_BK_TIME_8822B(x) (((x) & BIT_MASK_AGGR_BK_TIME_8822B) << BIT_SHIFT_AGGR_BK_TIME_8822B) -#define BIT_GET_AGGR_BK_TIME_8822B(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8822B) & BIT_MASK_AGGR_BK_TIME_8822B) - - +#define BIT_AGGR_BK_TIME_8822B(x) \ + (((x) & BIT_MASK_AGGR_BK_TIME_8822B) << BIT_SHIFT_AGGR_BK_TIME_8822B) +#define BITS_AGGR_BK_TIME_8822B \ + (BIT_MASK_AGGR_BK_TIME_8822B << BIT_SHIFT_AGGR_BK_TIME_8822B) +#define BIT_CLEAR_AGGR_BK_TIME_8822B(x) ((x) & (~BITS_AGGR_BK_TIME_8822B)) +#define BIT_GET_AGGR_BK_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_AGGR_BK_TIME_8822B) & BIT_MASK_AGGR_BK_TIME_8822B) +#define BIT_SET_AGGR_BK_TIME_8822B(x, v) \ + (BIT_CLEAR_AGGR_BK_TIME_8822B(x) | BIT_AGGR_BK_TIME_8822B(v)) /* 2 REG_SLOT_8822B */ #define BIT_SHIFT_SLOT_8822B 0 #define BIT_MASK_SLOT_8822B 0xff #define BIT_SLOT_8822B(x) (((x) & BIT_MASK_SLOT_8822B) << BIT_SHIFT_SLOT_8822B) -#define BIT_GET_SLOT_8822B(x) (((x) >> BIT_SHIFT_SLOT_8822B) & BIT_MASK_SLOT_8822B) - - +#define BITS_SLOT_8822B (BIT_MASK_SLOT_8822B << BIT_SHIFT_SLOT_8822B) +#define BIT_CLEAR_SLOT_8822B(x) ((x) & (~BITS_SLOT_8822B)) +#define BIT_GET_SLOT_8822B(x) \ + (((x) >> BIT_SHIFT_SLOT_8822B) & BIT_MASK_SLOT_8822B) +#define BIT_SET_SLOT_8822B(x, v) (BIT_CLEAR_SLOT_8822B(x) | BIT_SLOT_8822B(v)) /* 2 REG_TX_PTCL_CTRL_8822B */ #define BIT_DIS_EDCCA_8822B BIT(15) @@ -7196,9 +11413,15 @@ #define BIT_SHIFT_TXQ_NAV_MSK_8822B 8 #define BIT_MASK_TXQ_NAV_MSK_8822B 0xf -#define BIT_TXQ_NAV_MSK_8822B(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8822B) << BIT_SHIFT_TXQ_NAV_MSK_8822B) -#define BIT_GET_TXQ_NAV_MSK_8822B(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822B) & BIT_MASK_TXQ_NAV_MSK_8822B) - +#define BIT_TXQ_NAV_MSK_8822B(x) \ + (((x) & BIT_MASK_TXQ_NAV_MSK_8822B) << BIT_SHIFT_TXQ_NAV_MSK_8822B) +#define BITS_TXQ_NAV_MSK_8822B \ + (BIT_MASK_TXQ_NAV_MSK_8822B << BIT_SHIFT_TXQ_NAV_MSK_8822B) +#define BIT_CLEAR_TXQ_NAV_MSK_8822B(x) ((x) & (~BITS_TXQ_NAV_MSK_8822B)) +#define BIT_GET_TXQ_NAV_MSK_8822B(x) \ + (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822B) & BIT_MASK_TXQ_NAV_MSK_8822B) +#define BIT_SET_TXQ_NAV_MSK_8822B(x, v) \ + (BIT_CLEAR_TXQ_NAV_MSK_8822B(x) | BIT_TXQ_NAV_MSK_8822B(v)) #define BIT_DIS_CW_8822B BIT(7) #define BIT_NAV_END_TXOP_8822B BIT(6) @@ -7274,17 +11497,29 @@ #define BIT_SHIFT_CCA_FILTER_THRS_8822B 8 #define BIT_MASK_CCA_FILTER_THRS_8822B 0xff -#define BIT_CCA_FILTER_THRS_8822B(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8822B) << BIT_SHIFT_CCA_FILTER_THRS_8822B) -#define BIT_GET_CCA_FILTER_THRS_8822B(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822B) & BIT_MASK_CCA_FILTER_THRS_8822B) - - +#define BIT_CCA_FILTER_THRS_8822B(x) \ + (((x) & BIT_MASK_CCA_FILTER_THRS_8822B) \ + << BIT_SHIFT_CCA_FILTER_THRS_8822B) +#define BITS_CCA_FILTER_THRS_8822B \ + (BIT_MASK_CCA_FILTER_THRS_8822B << BIT_SHIFT_CCA_FILTER_THRS_8822B) +#define BIT_CLEAR_CCA_FILTER_THRS_8822B(x) ((x) & (~BITS_CCA_FILTER_THRS_8822B)) +#define BIT_GET_CCA_FILTER_THRS_8822B(x) \ + (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822B) & \ + BIT_MASK_CCA_FILTER_THRS_8822B) +#define BIT_SET_CCA_FILTER_THRS_8822B(x, v) \ + (BIT_CLEAR_CCA_FILTER_THRS_8822B(x) | BIT_CCA_FILTER_THRS_8822B(v)) #define BIT_SHIFT_EDCCA_THRS_8822B 0 #define BIT_MASK_EDCCA_THRS_8822B 0xff -#define BIT_EDCCA_THRS_8822B(x) (((x) & BIT_MASK_EDCCA_THRS_8822B) << BIT_SHIFT_EDCCA_THRS_8822B) -#define BIT_GET_EDCCA_THRS_8822B(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8822B) & BIT_MASK_EDCCA_THRS_8822B) - - +#define BIT_EDCCA_THRS_8822B(x) \ + (((x) & BIT_MASK_EDCCA_THRS_8822B) << BIT_SHIFT_EDCCA_THRS_8822B) +#define BITS_EDCCA_THRS_8822B \ + (BIT_MASK_EDCCA_THRS_8822B << BIT_SHIFT_EDCCA_THRS_8822B) +#define BIT_CLEAR_EDCCA_THRS_8822B(x) ((x) & (~BITS_EDCCA_THRS_8822B)) +#define BIT_GET_EDCCA_THRS_8822B(x) \ + (((x) >> BIT_SHIFT_EDCCA_THRS_8822B) & BIT_MASK_EDCCA_THRS_8822B) +#define BIT_SET_EDCCA_THRS_8822B(x, v) \ + (BIT_CLEAR_EDCCA_THRS_8822B(x) | BIT_EDCCA_THRS_8822B(v)) /* 2 REG_P2PPS_SPEC_STATE_8822B */ #define BIT_SPEC_POWER_STATE_8822B BIT(7) @@ -7296,93 +11531,240 @@ #define BIT_SPEC_NOA0_OFF_PERIOD_8822B BIT(1) #define BIT_SPEC_FORCE_DOZE0_8822B BIT(0) +/* 2 REG_TXOP_LIMIT_CTRL_8822B */ + +#define BIT_SHIFT_TXOP_TBTT_CNT_8822B 24 +#define BIT_MASK_TXOP_TBTT_CNT_8822B 0xff +#define BIT_TXOP_TBTT_CNT_8822B(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_8822B) << BIT_SHIFT_TXOP_TBTT_CNT_8822B) +#define BITS_TXOP_TBTT_CNT_8822B \ + (BIT_MASK_TXOP_TBTT_CNT_8822B << BIT_SHIFT_TXOP_TBTT_CNT_8822B) +#define BIT_CLEAR_TXOP_TBTT_CNT_8822B(x) ((x) & (~BITS_TXOP_TBTT_CNT_8822B)) +#define BIT_GET_TXOP_TBTT_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8822B) & BIT_MASK_TXOP_TBTT_CNT_8822B) +#define BIT_SET_TXOP_TBTT_CNT_8822B(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_8822B(x) | BIT_TXOP_TBTT_CNT_8822B(v)) + +#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B 20 +#define BIT_MASK_TXOP_TBTT_CNT_SEL_8822B 0xf +#define BIT_TXOP_TBTT_CNT_SEL_8822B(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8822B) \ + << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B) +#define BITS_TXOP_TBTT_CNT_SEL_8822B \ + (BIT_MASK_TXOP_TBTT_CNT_SEL_8822B << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B) +#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822B(x) \ + ((x) & (~BITS_TXOP_TBTT_CNT_SEL_8822B)) +#define BIT_GET_TXOP_TBTT_CNT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B) & \ + BIT_MASK_TXOP_TBTT_CNT_SEL_8822B) +#define BIT_SET_TXOP_TBTT_CNT_SEL_8822B(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822B(x) | BIT_TXOP_TBTT_CNT_SEL_8822B(v)) + +#define BIT_SHIFT_TXOP_LMT_EN_8822B 16 +#define BIT_MASK_TXOP_LMT_EN_8822B 0xf +#define BIT_TXOP_LMT_EN_8822B(x) \ + (((x) & BIT_MASK_TXOP_LMT_EN_8822B) << BIT_SHIFT_TXOP_LMT_EN_8822B) +#define BITS_TXOP_LMT_EN_8822B \ + (BIT_MASK_TXOP_LMT_EN_8822B << BIT_SHIFT_TXOP_LMT_EN_8822B) +#define BIT_CLEAR_TXOP_LMT_EN_8822B(x) ((x) & (~BITS_TXOP_LMT_EN_8822B)) +#define BIT_GET_TXOP_LMT_EN_8822B(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_EN_8822B) & BIT_MASK_TXOP_LMT_EN_8822B) +#define BIT_SET_TXOP_LMT_EN_8822B(x, v) \ + (BIT_CLEAR_TXOP_LMT_EN_8822B(x) | BIT_TXOP_LMT_EN_8822B(v)) + +#define BIT_SHIFT_TXOP_LMT_TX_TIME_8822B 8 +#define BIT_MASK_TXOP_LMT_TX_TIME_8822B 0xff +#define BIT_TXOP_LMT_TX_TIME_8822B(x) \ + (((x) & BIT_MASK_TXOP_LMT_TX_TIME_8822B) \ + << BIT_SHIFT_TXOP_LMT_TX_TIME_8822B) +#define BITS_TXOP_LMT_TX_TIME_8822B \ + (BIT_MASK_TXOP_LMT_TX_TIME_8822B << BIT_SHIFT_TXOP_LMT_TX_TIME_8822B) +#define BIT_CLEAR_TXOP_LMT_TX_TIME_8822B(x) \ + ((x) & (~BITS_TXOP_LMT_TX_TIME_8822B)) +#define BIT_GET_TXOP_LMT_TX_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8822B) & \ + BIT_MASK_TXOP_LMT_TX_TIME_8822B) +#define BIT_SET_TXOP_LMT_TX_TIME_8822B(x, v) \ + (BIT_CLEAR_TXOP_LMT_TX_TIME_8822B(x) | BIT_TXOP_LMT_TX_TIME_8822B(v)) + +#define BIT_TXOP_CNT_TRIGGER_RESET_8822B BIT(7) + +#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B 0 +#define BIT_MASK_TXOP_LMT_PKT_NUM_8822B 0x3f +#define BIT_TXOP_LMT_PKT_NUM_8822B(x) \ + (((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8822B) \ + << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B) +#define BITS_TXOP_LMT_PKT_NUM_8822B \ + (BIT_MASK_TXOP_LMT_PKT_NUM_8822B << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B) +#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8822B(x) \ + ((x) & (~BITS_TXOP_LMT_PKT_NUM_8822B)) +#define BIT_GET_TXOP_LMT_PKT_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B) & \ + BIT_MASK_TXOP_LMT_PKT_NUM_8822B) +#define BIT_SET_TXOP_LMT_PKT_NUM_8822B(x, v) \ + (BIT_CLEAR_TXOP_LMT_PKT_NUM_8822B(x) | BIT_TXOP_LMT_PKT_NUM_8822B(v)) + /* 2 REG_BAR_TX_CTRL_8822B */ -/* 2 REG_NOT_VALID_8822B */ +/* 2 REG_P2PON_DIS_TXTIME_8822B */ #define BIT_SHIFT_P2PON_DIS_TXTIME_8822B 0 #define BIT_MASK_P2PON_DIS_TXTIME_8822B 0xff -#define BIT_P2PON_DIS_TXTIME_8822B(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8822B) << BIT_SHIFT_P2PON_DIS_TXTIME_8822B) -#define BIT_GET_P2PON_DIS_TXTIME_8822B(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822B) & BIT_MASK_P2PON_DIS_TXTIME_8822B) - - +#define BIT_P2PON_DIS_TXTIME_8822B(x) \ + (((x) & BIT_MASK_P2PON_DIS_TXTIME_8822B) \ + << BIT_SHIFT_P2PON_DIS_TXTIME_8822B) +#define BITS_P2PON_DIS_TXTIME_8822B \ + (BIT_MASK_P2PON_DIS_TXTIME_8822B << BIT_SHIFT_P2PON_DIS_TXTIME_8822B) +#define BIT_CLEAR_P2PON_DIS_TXTIME_8822B(x) \ + ((x) & (~BITS_P2PON_DIS_TXTIME_8822B)) +#define BIT_GET_P2PON_DIS_TXTIME_8822B(x) \ + (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822B) & \ + BIT_MASK_P2PON_DIS_TXTIME_8822B) +#define BIT_SET_P2PON_DIS_TXTIME_8822B(x, v) \ + (BIT_CLEAR_P2PON_DIS_TXTIME_8822B(x) | BIT_P2PON_DIS_TXTIME_8822B(v)) /* 2 REG_QUEUE_INCOL_THR_8822B */ #define BIT_SHIFT_BK_QUEUE_THR_8822B 24 #define BIT_MASK_BK_QUEUE_THR_8822B 0xff -#define BIT_BK_QUEUE_THR_8822B(x) (((x) & BIT_MASK_BK_QUEUE_THR_8822B) << BIT_SHIFT_BK_QUEUE_THR_8822B) -#define BIT_GET_BK_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_BK_QUEUE_THR_8822B) & BIT_MASK_BK_QUEUE_THR_8822B) - - +#define BIT_BK_QUEUE_THR_8822B(x) \ + (((x) & BIT_MASK_BK_QUEUE_THR_8822B) << BIT_SHIFT_BK_QUEUE_THR_8822B) +#define BITS_BK_QUEUE_THR_8822B \ + (BIT_MASK_BK_QUEUE_THR_8822B << BIT_SHIFT_BK_QUEUE_THR_8822B) +#define BIT_CLEAR_BK_QUEUE_THR_8822B(x) ((x) & (~BITS_BK_QUEUE_THR_8822B)) +#define BIT_GET_BK_QUEUE_THR_8822B(x) \ + (((x) >> BIT_SHIFT_BK_QUEUE_THR_8822B) & BIT_MASK_BK_QUEUE_THR_8822B) +#define BIT_SET_BK_QUEUE_THR_8822B(x, v) \ + (BIT_CLEAR_BK_QUEUE_THR_8822B(x) | BIT_BK_QUEUE_THR_8822B(v)) #define BIT_SHIFT_BE_QUEUE_THR_8822B 16 #define BIT_MASK_BE_QUEUE_THR_8822B 0xff -#define BIT_BE_QUEUE_THR_8822B(x) (((x) & BIT_MASK_BE_QUEUE_THR_8822B) << BIT_SHIFT_BE_QUEUE_THR_8822B) -#define BIT_GET_BE_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_BE_QUEUE_THR_8822B) & BIT_MASK_BE_QUEUE_THR_8822B) - - +#define BIT_BE_QUEUE_THR_8822B(x) \ + (((x) & BIT_MASK_BE_QUEUE_THR_8822B) << BIT_SHIFT_BE_QUEUE_THR_8822B) +#define BITS_BE_QUEUE_THR_8822B \ + (BIT_MASK_BE_QUEUE_THR_8822B << BIT_SHIFT_BE_QUEUE_THR_8822B) +#define BIT_CLEAR_BE_QUEUE_THR_8822B(x) ((x) & (~BITS_BE_QUEUE_THR_8822B)) +#define BIT_GET_BE_QUEUE_THR_8822B(x) \ + (((x) >> BIT_SHIFT_BE_QUEUE_THR_8822B) & BIT_MASK_BE_QUEUE_THR_8822B) +#define BIT_SET_BE_QUEUE_THR_8822B(x, v) \ + (BIT_CLEAR_BE_QUEUE_THR_8822B(x) | BIT_BE_QUEUE_THR_8822B(v)) #define BIT_SHIFT_VI_QUEUE_THR_8822B 8 #define BIT_MASK_VI_QUEUE_THR_8822B 0xff -#define BIT_VI_QUEUE_THR_8822B(x) (((x) & BIT_MASK_VI_QUEUE_THR_8822B) << BIT_SHIFT_VI_QUEUE_THR_8822B) -#define BIT_GET_VI_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_VI_QUEUE_THR_8822B) & BIT_MASK_VI_QUEUE_THR_8822B) - - +#define BIT_VI_QUEUE_THR_8822B(x) \ + (((x) & BIT_MASK_VI_QUEUE_THR_8822B) << BIT_SHIFT_VI_QUEUE_THR_8822B) +#define BITS_VI_QUEUE_THR_8822B \ + (BIT_MASK_VI_QUEUE_THR_8822B << BIT_SHIFT_VI_QUEUE_THR_8822B) +#define BIT_CLEAR_VI_QUEUE_THR_8822B(x) ((x) & (~BITS_VI_QUEUE_THR_8822B)) +#define BIT_GET_VI_QUEUE_THR_8822B(x) \ + (((x) >> BIT_SHIFT_VI_QUEUE_THR_8822B) & BIT_MASK_VI_QUEUE_THR_8822B) +#define BIT_SET_VI_QUEUE_THR_8822B(x, v) \ + (BIT_CLEAR_VI_QUEUE_THR_8822B(x) | BIT_VI_QUEUE_THR_8822B(v)) #define BIT_SHIFT_VO_QUEUE_THR_8822B 0 #define BIT_MASK_VO_QUEUE_THR_8822B 0xff -#define BIT_VO_QUEUE_THR_8822B(x) (((x) & BIT_MASK_VO_QUEUE_THR_8822B) << BIT_SHIFT_VO_QUEUE_THR_8822B) -#define BIT_GET_VO_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_VO_QUEUE_THR_8822B) & BIT_MASK_VO_QUEUE_THR_8822B) - - +#define BIT_VO_QUEUE_THR_8822B(x) \ + (((x) & BIT_MASK_VO_QUEUE_THR_8822B) << BIT_SHIFT_VO_QUEUE_THR_8822B) +#define BITS_VO_QUEUE_THR_8822B \ + (BIT_MASK_VO_QUEUE_THR_8822B << BIT_SHIFT_VO_QUEUE_THR_8822B) +#define BIT_CLEAR_VO_QUEUE_THR_8822B(x) ((x) & (~BITS_VO_QUEUE_THR_8822B)) +#define BIT_GET_VO_QUEUE_THR_8822B(x) \ + (((x) >> BIT_SHIFT_VO_QUEUE_THR_8822B) & BIT_MASK_VO_QUEUE_THR_8822B) +#define BIT_SET_VO_QUEUE_THR_8822B(x, v) \ + (BIT_CLEAR_VO_QUEUE_THR_8822B(x) | BIT_VO_QUEUE_THR_8822B(v)) /* 2 REG_QUEUE_INCOL_EN_8822B */ #define BIT_QUEUE_INCOL_EN_8822B BIT(16) #define BIT_SHIFT_BE_TRIGGER_NUM_8822B 12 #define BIT_MASK_BE_TRIGGER_NUM_8822B 0xf -#define BIT_BE_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_BE_TRIGGER_NUM_8822B) << BIT_SHIFT_BE_TRIGGER_NUM_8822B) -#define BIT_GET_BE_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_8822B) & BIT_MASK_BE_TRIGGER_NUM_8822B) - - +#define BIT_BE_TRIGGER_NUM_8822B(x) \ + (((x) & BIT_MASK_BE_TRIGGER_NUM_8822B) \ + << BIT_SHIFT_BE_TRIGGER_NUM_8822B) +#define BITS_BE_TRIGGER_NUM_8822B \ + (BIT_MASK_BE_TRIGGER_NUM_8822B << BIT_SHIFT_BE_TRIGGER_NUM_8822B) +#define BIT_CLEAR_BE_TRIGGER_NUM_8822B(x) ((x) & (~BITS_BE_TRIGGER_NUM_8822B)) +#define BIT_GET_BE_TRIGGER_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_8822B) & \ + BIT_MASK_BE_TRIGGER_NUM_8822B) +#define BIT_SET_BE_TRIGGER_NUM_8822B(x, v) \ + (BIT_CLEAR_BE_TRIGGER_NUM_8822B(x) | BIT_BE_TRIGGER_NUM_8822B(v)) #define BIT_SHIFT_BK_TRIGGER_NUM_8822B 8 #define BIT_MASK_BK_TRIGGER_NUM_8822B 0xf -#define BIT_BK_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_BK_TRIGGER_NUM_8822B) << BIT_SHIFT_BK_TRIGGER_NUM_8822B) -#define BIT_GET_BK_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_8822B) & BIT_MASK_BK_TRIGGER_NUM_8822B) - - +#define BIT_BK_TRIGGER_NUM_8822B(x) \ + (((x) & BIT_MASK_BK_TRIGGER_NUM_8822B) \ + << BIT_SHIFT_BK_TRIGGER_NUM_8822B) +#define BITS_BK_TRIGGER_NUM_8822B \ + (BIT_MASK_BK_TRIGGER_NUM_8822B << BIT_SHIFT_BK_TRIGGER_NUM_8822B) +#define BIT_CLEAR_BK_TRIGGER_NUM_8822B(x) ((x) & (~BITS_BK_TRIGGER_NUM_8822B)) +#define BIT_GET_BK_TRIGGER_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_8822B) & \ + BIT_MASK_BK_TRIGGER_NUM_8822B) +#define BIT_SET_BK_TRIGGER_NUM_8822B(x, v) \ + (BIT_CLEAR_BK_TRIGGER_NUM_8822B(x) | BIT_BK_TRIGGER_NUM_8822B(v)) #define BIT_SHIFT_VI_TRIGGER_NUM_8822B 4 #define BIT_MASK_VI_TRIGGER_NUM_8822B 0xf -#define BIT_VI_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_VI_TRIGGER_NUM_8822B) << BIT_SHIFT_VI_TRIGGER_NUM_8822B) -#define BIT_GET_VI_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8822B) & BIT_MASK_VI_TRIGGER_NUM_8822B) - - +#define BIT_VI_TRIGGER_NUM_8822B(x) \ + (((x) & BIT_MASK_VI_TRIGGER_NUM_8822B) \ + << BIT_SHIFT_VI_TRIGGER_NUM_8822B) +#define BITS_VI_TRIGGER_NUM_8822B \ + (BIT_MASK_VI_TRIGGER_NUM_8822B << BIT_SHIFT_VI_TRIGGER_NUM_8822B) +#define BIT_CLEAR_VI_TRIGGER_NUM_8822B(x) ((x) & (~BITS_VI_TRIGGER_NUM_8822B)) +#define BIT_GET_VI_TRIGGER_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8822B) & \ + BIT_MASK_VI_TRIGGER_NUM_8822B) +#define BIT_SET_VI_TRIGGER_NUM_8822B(x, v) \ + (BIT_CLEAR_VI_TRIGGER_NUM_8822B(x) | BIT_VI_TRIGGER_NUM_8822B(v)) #define BIT_SHIFT_VO_TRIGGER_NUM_8822B 0 #define BIT_MASK_VO_TRIGGER_NUM_8822B 0xf -#define BIT_VO_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_VO_TRIGGER_NUM_8822B) << BIT_SHIFT_VO_TRIGGER_NUM_8822B) -#define BIT_GET_VO_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8822B) & BIT_MASK_VO_TRIGGER_NUM_8822B) - - +#define BIT_VO_TRIGGER_NUM_8822B(x) \ + (((x) & BIT_MASK_VO_TRIGGER_NUM_8822B) \ + << BIT_SHIFT_VO_TRIGGER_NUM_8822B) +#define BITS_VO_TRIGGER_NUM_8822B \ + (BIT_MASK_VO_TRIGGER_NUM_8822B << BIT_SHIFT_VO_TRIGGER_NUM_8822B) +#define BIT_CLEAR_VO_TRIGGER_NUM_8822B(x) ((x) & (~BITS_VO_TRIGGER_NUM_8822B)) +#define BIT_GET_VO_TRIGGER_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8822B) & \ + BIT_MASK_VO_TRIGGER_NUM_8822B) +#define BIT_SET_VO_TRIGGER_NUM_8822B(x, v) \ + (BIT_CLEAR_VO_TRIGGER_NUM_8822B(x) | BIT_VO_TRIGGER_NUM_8822B(v)) /* 2 REG_TBTT_PROHIBIT_8822B */ #define BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B 8 #define BIT_MASK_TBTT_HOLD_TIME_AP_8822B 0xfff -#define BIT_TBTT_HOLD_TIME_AP_8822B(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) -#define BIT_GET_TBTT_HOLD_TIME_AP_8822B(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B) - - +#define BIT_TBTT_HOLD_TIME_AP_8822B(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B) \ + << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) +#define BITS_TBTT_HOLD_TIME_AP_8822B \ + (BIT_MASK_TBTT_HOLD_TIME_AP_8822B << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) +#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8822B(x) \ + ((x) & (~BITS_TBTT_HOLD_TIME_AP_8822B)) +#define BIT_GET_TBTT_HOLD_TIME_AP_8822B(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) & \ + BIT_MASK_TBTT_HOLD_TIME_AP_8822B) +#define BIT_SET_TBTT_HOLD_TIME_AP_8822B(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_AP_8822B(x) | BIT_TBTT_HOLD_TIME_AP_8822B(v)) #define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B 0 #define BIT_MASK_TBTT_PROHIBIT_SETUP_8822B 0xf -#define BIT_TBTT_PROHIBIT_SETUP_8822B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) -#define BIT_GET_TBTT_PROHIBIT_SETUP_8822B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) - - +#define BIT_TBTT_PROHIBIT_SETUP_8822B(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) +#define BITS_TBTT_PROHIBIT_SETUP_8822B \ + (BIT_MASK_TBTT_PROHIBIT_SETUP_8822B \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822B(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8822B)) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8822B(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) & \ + BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) +#define BIT_SET_TBTT_PROHIBIT_SETUP_8822B(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822B(x) | \ + BIT_TBTT_PROHIBIT_SETUP_8822B(v)) /* 2 REG_P2PPS_STATE_8822B */ #define BIT_POWER_STATE_8822B BIT(7) @@ -7398,19 +11780,31 @@ #define BIT_SHIFT_RD_NAV_PROT_NXT_8822B 0 #define BIT_MASK_RD_NAV_PROT_NXT_8822B 0xffff -#define BIT_RD_NAV_PROT_NXT_8822B(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8822B) << BIT_SHIFT_RD_NAV_PROT_NXT_8822B) -#define BIT_GET_RD_NAV_PROT_NXT_8822B(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822B) & BIT_MASK_RD_NAV_PROT_NXT_8822B) - - +#define BIT_RD_NAV_PROT_NXT_8822B(x) \ + (((x) & BIT_MASK_RD_NAV_PROT_NXT_8822B) \ + << BIT_SHIFT_RD_NAV_PROT_NXT_8822B) +#define BITS_RD_NAV_PROT_NXT_8822B \ + (BIT_MASK_RD_NAV_PROT_NXT_8822B << BIT_SHIFT_RD_NAV_PROT_NXT_8822B) +#define BIT_CLEAR_RD_NAV_PROT_NXT_8822B(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8822B)) +#define BIT_GET_RD_NAV_PROT_NXT_8822B(x) \ + (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822B) & \ + BIT_MASK_RD_NAV_PROT_NXT_8822B) +#define BIT_SET_RD_NAV_PROT_NXT_8822B(x, v) \ + (BIT_CLEAR_RD_NAV_PROT_NXT_8822B(x) | BIT_RD_NAV_PROT_NXT_8822B(v)) /* 2 REG_NAV_PROT_LEN_8822B */ #define BIT_SHIFT_NAV_PROT_LEN_8822B 0 #define BIT_MASK_NAV_PROT_LEN_8822B 0xffff -#define BIT_NAV_PROT_LEN_8822B(x) (((x) & BIT_MASK_NAV_PROT_LEN_8822B) << BIT_SHIFT_NAV_PROT_LEN_8822B) -#define BIT_GET_NAV_PROT_LEN_8822B(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8822B) & BIT_MASK_NAV_PROT_LEN_8822B) - - +#define BIT_NAV_PROT_LEN_8822B(x) \ + (((x) & BIT_MASK_NAV_PROT_LEN_8822B) << BIT_SHIFT_NAV_PROT_LEN_8822B) +#define BITS_NAV_PROT_LEN_8822B \ + (BIT_MASK_NAV_PROT_LEN_8822B << BIT_SHIFT_NAV_PROT_LEN_8822B) +#define BIT_CLEAR_NAV_PROT_LEN_8822B(x) ((x) & (~BITS_NAV_PROT_LEN_8822B)) +#define BIT_GET_NAV_PROT_LEN_8822B(x) \ + (((x) >> BIT_SHIFT_NAV_PROT_LEN_8822B) & BIT_MASK_NAV_PROT_LEN_8822B) +#define BIT_SET_NAV_PROT_LEN_8822B(x, v) \ + (BIT_CLEAR_NAV_PROT_LEN_8822B(x) | BIT_NAV_PROT_LEN_8822B(v)) /* 2 REG_BCN_CTRL_8822B */ #define BIT_DIS_RX_BSSID_FIT_8822B BIT(6) @@ -7434,10 +11828,15 @@ #define BIT_SHIFT_MBID_BCN_NUM_8822B 0 #define BIT_MASK_MBID_BCN_NUM_8822B 0x7 -#define BIT_MBID_BCN_NUM_8822B(x) (((x) & BIT_MASK_MBID_BCN_NUM_8822B) << BIT_SHIFT_MBID_BCN_NUM_8822B) -#define BIT_GET_MBID_BCN_NUM_8822B(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8822B) & BIT_MASK_MBID_BCN_NUM_8822B) - - +#define BIT_MBID_BCN_NUM_8822B(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_8822B) << BIT_SHIFT_MBID_BCN_NUM_8822B) +#define BITS_MBID_BCN_NUM_8822B \ + (BIT_MASK_MBID_BCN_NUM_8822B << BIT_SHIFT_MBID_BCN_NUM_8822B) +#define BIT_CLEAR_MBID_BCN_NUM_8822B(x) ((x) & (~BITS_MBID_BCN_NUM_8822B)) +#define BIT_GET_MBID_BCN_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_8822B) & BIT_MASK_MBID_BCN_NUM_8822B) +#define BIT_SET_MBID_BCN_NUM_8822B(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_8822B(x) | BIT_MBID_BCN_NUM_8822B(v)) /* 2 REG_DUAL_TSF_RST_8822B */ #define BIT_FREECNT_RST_8822B BIT(5) @@ -7451,171 +11850,297 @@ #define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B 28 #define BIT_MASK_BCN_TIMER_SEL_FWRD_8822B 0x7 -#define BIT_BCN_TIMER_SEL_FWRD_8822B(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) -#define BIT_GET_BCN_TIMER_SEL_FWRD_8822B(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B) - - +#define BIT_BCN_TIMER_SEL_FWRD_8822B(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B) \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) +#define BITS_BCN_TIMER_SEL_FWRD_8822B \ + (BIT_MASK_BCN_TIMER_SEL_FWRD_8822B \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822B(x) \ + ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8822B)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) & \ + BIT_MASK_BCN_TIMER_SEL_FWRD_8822B) +#define BIT_SET_BCN_TIMER_SEL_FWRD_8822B(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822B(x) | \ + BIT_BCN_TIMER_SEL_FWRD_8822B(v)) #define BIT_SHIFT_BCN_SPACE_CLINT0_8822B 16 #define BIT_MASK_BCN_SPACE_CLINT0_8822B 0xfff -#define BIT_BCN_SPACE_CLINT0_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8822B) << BIT_SHIFT_BCN_SPACE_CLINT0_8822B) -#define BIT_GET_BCN_SPACE_CLINT0_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822B) & BIT_MASK_BCN_SPACE_CLINT0_8822B) - - +#define BIT_BCN_SPACE_CLINT0_8822B(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT0_8822B) \ + << BIT_SHIFT_BCN_SPACE_CLINT0_8822B) +#define BITS_BCN_SPACE_CLINT0_8822B \ + (BIT_MASK_BCN_SPACE_CLINT0_8822B << BIT_SHIFT_BCN_SPACE_CLINT0_8822B) +#define BIT_CLEAR_BCN_SPACE_CLINT0_8822B(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT0_8822B)) +#define BIT_GET_BCN_SPACE_CLINT0_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822B) & \ + BIT_MASK_BCN_SPACE_CLINT0_8822B) +#define BIT_SET_BCN_SPACE_CLINT0_8822B(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT0_8822B(x) | BIT_BCN_SPACE_CLINT0_8822B(v)) #define BIT_SHIFT_BCN_SPACE0_8822B 0 #define BIT_MASK_BCN_SPACE0_8822B 0xffff -#define BIT_BCN_SPACE0_8822B(x) (((x) & BIT_MASK_BCN_SPACE0_8822B) << BIT_SHIFT_BCN_SPACE0_8822B) -#define BIT_GET_BCN_SPACE0_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8822B) & BIT_MASK_BCN_SPACE0_8822B) - - +#define BIT_BCN_SPACE0_8822B(x) \ + (((x) & BIT_MASK_BCN_SPACE0_8822B) << BIT_SHIFT_BCN_SPACE0_8822B) +#define BITS_BCN_SPACE0_8822B \ + (BIT_MASK_BCN_SPACE0_8822B << BIT_SHIFT_BCN_SPACE0_8822B) +#define BIT_CLEAR_BCN_SPACE0_8822B(x) ((x) & (~BITS_BCN_SPACE0_8822B)) +#define BIT_GET_BCN_SPACE0_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE0_8822B) & BIT_MASK_BCN_SPACE0_8822B) +#define BIT_SET_BCN_SPACE0_8822B(x, v) \ + (BIT_CLEAR_BCN_SPACE0_8822B(x) | BIT_BCN_SPACE0_8822B(v)) /* 2 REG_DRVERLYINT_8822B */ #define BIT_SHIFT_DRVERLYITV_8822B 0 #define BIT_MASK_DRVERLYITV_8822B 0xff -#define BIT_DRVERLYITV_8822B(x) (((x) & BIT_MASK_DRVERLYITV_8822B) << BIT_SHIFT_DRVERLYITV_8822B) -#define BIT_GET_DRVERLYITV_8822B(x) (((x) >> BIT_SHIFT_DRVERLYITV_8822B) & BIT_MASK_DRVERLYITV_8822B) - - +#define BIT_DRVERLYITV_8822B(x) \ + (((x) & BIT_MASK_DRVERLYITV_8822B) << BIT_SHIFT_DRVERLYITV_8822B) +#define BITS_DRVERLYITV_8822B \ + (BIT_MASK_DRVERLYITV_8822B << BIT_SHIFT_DRVERLYITV_8822B) +#define BIT_CLEAR_DRVERLYITV_8822B(x) ((x) & (~BITS_DRVERLYITV_8822B)) +#define BIT_GET_DRVERLYITV_8822B(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV_8822B) & BIT_MASK_DRVERLYITV_8822B) +#define BIT_SET_DRVERLYITV_8822B(x, v) \ + (BIT_CLEAR_DRVERLYITV_8822B(x) | BIT_DRVERLYITV_8822B(v)) /* 2 REG_BCNDMATIM_8822B */ #define BIT_SHIFT_BCNDMATIM_8822B 0 #define BIT_MASK_BCNDMATIM_8822B 0xff -#define BIT_BCNDMATIM_8822B(x) (((x) & BIT_MASK_BCNDMATIM_8822B) << BIT_SHIFT_BCNDMATIM_8822B) -#define BIT_GET_BCNDMATIM_8822B(x) (((x) >> BIT_SHIFT_BCNDMATIM_8822B) & BIT_MASK_BCNDMATIM_8822B) - - +#define BIT_BCNDMATIM_8822B(x) \ + (((x) & BIT_MASK_BCNDMATIM_8822B) << BIT_SHIFT_BCNDMATIM_8822B) +#define BITS_BCNDMATIM_8822B \ + (BIT_MASK_BCNDMATIM_8822B << BIT_SHIFT_BCNDMATIM_8822B) +#define BIT_CLEAR_BCNDMATIM_8822B(x) ((x) & (~BITS_BCNDMATIM_8822B)) +#define BIT_GET_BCNDMATIM_8822B(x) \ + (((x) >> BIT_SHIFT_BCNDMATIM_8822B) & BIT_MASK_BCNDMATIM_8822B) +#define BIT_SET_BCNDMATIM_8822B(x, v) \ + (BIT_CLEAR_BCNDMATIM_8822B(x) | BIT_BCNDMATIM_8822B(v)) /* 2 REG_ATIMWND_8822B */ #define BIT_SHIFT_ATIMWND0_8822B 0 #define BIT_MASK_ATIMWND0_8822B 0xffff -#define BIT_ATIMWND0_8822B(x) (((x) & BIT_MASK_ATIMWND0_8822B) << BIT_SHIFT_ATIMWND0_8822B) -#define BIT_GET_ATIMWND0_8822B(x) (((x) >> BIT_SHIFT_ATIMWND0_8822B) & BIT_MASK_ATIMWND0_8822B) - - +#define BIT_ATIMWND0_8822B(x) \ + (((x) & BIT_MASK_ATIMWND0_8822B) << BIT_SHIFT_ATIMWND0_8822B) +#define BITS_ATIMWND0_8822B \ + (BIT_MASK_ATIMWND0_8822B << BIT_SHIFT_ATIMWND0_8822B) +#define BIT_CLEAR_ATIMWND0_8822B(x) ((x) & (~BITS_ATIMWND0_8822B)) +#define BIT_GET_ATIMWND0_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND0_8822B) & BIT_MASK_ATIMWND0_8822B) +#define BIT_SET_ATIMWND0_8822B(x, v) \ + (BIT_CLEAR_ATIMWND0_8822B(x) | BIT_ATIMWND0_8822B(v)) /* 2 REG_USTIME_TSF_8822B */ #define BIT_SHIFT_USTIME_TSF_V1_8822B 0 #define BIT_MASK_USTIME_TSF_V1_8822B 0xff -#define BIT_USTIME_TSF_V1_8822B(x) (((x) & BIT_MASK_USTIME_TSF_V1_8822B) << BIT_SHIFT_USTIME_TSF_V1_8822B) -#define BIT_GET_USTIME_TSF_V1_8822B(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8822B) & BIT_MASK_USTIME_TSF_V1_8822B) - - +#define BIT_USTIME_TSF_V1_8822B(x) \ + (((x) & BIT_MASK_USTIME_TSF_V1_8822B) << BIT_SHIFT_USTIME_TSF_V1_8822B) +#define BITS_USTIME_TSF_V1_8822B \ + (BIT_MASK_USTIME_TSF_V1_8822B << BIT_SHIFT_USTIME_TSF_V1_8822B) +#define BIT_CLEAR_USTIME_TSF_V1_8822B(x) ((x) & (~BITS_USTIME_TSF_V1_8822B)) +#define BIT_GET_USTIME_TSF_V1_8822B(x) \ + (((x) >> BIT_SHIFT_USTIME_TSF_V1_8822B) & BIT_MASK_USTIME_TSF_V1_8822B) +#define BIT_SET_USTIME_TSF_V1_8822B(x, v) \ + (BIT_CLEAR_USTIME_TSF_V1_8822B(x) | BIT_USTIME_TSF_V1_8822B(v)) /* 2 REG_BCN_MAX_ERR_8822B */ #define BIT_SHIFT_BCN_MAX_ERR_8822B 0 #define BIT_MASK_BCN_MAX_ERR_8822B 0xff -#define BIT_BCN_MAX_ERR_8822B(x) (((x) & BIT_MASK_BCN_MAX_ERR_8822B) << BIT_SHIFT_BCN_MAX_ERR_8822B) -#define BIT_GET_BCN_MAX_ERR_8822B(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8822B) & BIT_MASK_BCN_MAX_ERR_8822B) - - +#define BIT_BCN_MAX_ERR_8822B(x) \ + (((x) & BIT_MASK_BCN_MAX_ERR_8822B) << BIT_SHIFT_BCN_MAX_ERR_8822B) +#define BITS_BCN_MAX_ERR_8822B \ + (BIT_MASK_BCN_MAX_ERR_8822B << BIT_SHIFT_BCN_MAX_ERR_8822B) +#define BIT_CLEAR_BCN_MAX_ERR_8822B(x) ((x) & (~BITS_BCN_MAX_ERR_8822B)) +#define BIT_GET_BCN_MAX_ERR_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_MAX_ERR_8822B) & BIT_MASK_BCN_MAX_ERR_8822B) +#define BIT_SET_BCN_MAX_ERR_8822B(x, v) \ + (BIT_CLEAR_BCN_MAX_ERR_8822B(x) | BIT_BCN_MAX_ERR_8822B(v)) /* 2 REG_RXTSF_OFFSET_CCK_8822B */ #define BIT_SHIFT_CCK_RXTSF_OFFSET_8822B 0 #define BIT_MASK_CCK_RXTSF_OFFSET_8822B 0xff -#define BIT_CCK_RXTSF_OFFSET_8822B(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822B) << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) -#define BIT_GET_CCK_RXTSF_OFFSET_8822B(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) & BIT_MASK_CCK_RXTSF_OFFSET_8822B) - - +#define BIT_CCK_RXTSF_OFFSET_8822B(x) \ + (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822B) \ + << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) +#define BITS_CCK_RXTSF_OFFSET_8822B \ + (BIT_MASK_CCK_RXTSF_OFFSET_8822B << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) +#define BIT_CLEAR_CCK_RXTSF_OFFSET_8822B(x) \ + ((x) & (~BITS_CCK_RXTSF_OFFSET_8822B)) +#define BIT_GET_CCK_RXTSF_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) & \ + BIT_MASK_CCK_RXTSF_OFFSET_8822B) +#define BIT_SET_CCK_RXTSF_OFFSET_8822B(x, v) \ + (BIT_CLEAR_CCK_RXTSF_OFFSET_8822B(x) | BIT_CCK_RXTSF_OFFSET_8822B(v)) /* 2 REG_RXTSF_OFFSET_OFDM_8822B */ #define BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B 0 #define BIT_MASK_OFDM_RXTSF_OFFSET_8822B 0xff -#define BIT_OFDM_RXTSF_OFFSET_8822B(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) -#define BIT_GET_OFDM_RXTSF_OFFSET_8822B(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B) - - +#define BIT_OFDM_RXTSF_OFFSET_8822B(x) \ + (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B) \ + << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) +#define BITS_OFDM_RXTSF_OFFSET_8822B \ + (BIT_MASK_OFDM_RXTSF_OFFSET_8822B << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8822B(x) \ + ((x) & (~BITS_OFDM_RXTSF_OFFSET_8822B)) +#define BIT_GET_OFDM_RXTSF_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) & \ + BIT_MASK_OFDM_RXTSF_OFFSET_8822B) +#define BIT_SET_OFDM_RXTSF_OFFSET_8822B(x, v) \ + (BIT_CLEAR_OFDM_RXTSF_OFFSET_8822B(x) | BIT_OFDM_RXTSF_OFFSET_8822B(v)) /* 2 REG_TSFTR_8822B */ #define BIT_SHIFT_TSF_TIMER_8822B 0 #define BIT_MASK_TSF_TIMER_8822B 0xffffffffffffffffL -#define BIT_TSF_TIMER_8822B(x) (((x) & BIT_MASK_TSF_TIMER_8822B) << BIT_SHIFT_TSF_TIMER_8822B) -#define BIT_GET_TSF_TIMER_8822B(x) (((x) >> BIT_SHIFT_TSF_TIMER_8822B) & BIT_MASK_TSF_TIMER_8822B) - - +#define BIT_TSF_TIMER_8822B(x) \ + (((x) & BIT_MASK_TSF_TIMER_8822B) << BIT_SHIFT_TSF_TIMER_8822B) +#define BITS_TSF_TIMER_8822B \ + (BIT_MASK_TSF_TIMER_8822B << BIT_SHIFT_TSF_TIMER_8822B) +#define BIT_CLEAR_TSF_TIMER_8822B(x) ((x) & (~BITS_TSF_TIMER_8822B)) +#define BIT_GET_TSF_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_8822B) & BIT_MASK_TSF_TIMER_8822B) +#define BIT_SET_TSF_TIMER_8822B(x, v) \ + (BIT_CLEAR_TSF_TIMER_8822B(x) | BIT_TSF_TIMER_8822B(v)) /* 2 REG_FREERUN_CNT_8822B */ #define BIT_SHIFT_FREERUN_CNT_8822B 0 #define BIT_MASK_FREERUN_CNT_8822B 0xffffffffffffffffL -#define BIT_FREERUN_CNT_8822B(x) (((x) & BIT_MASK_FREERUN_CNT_8822B) << BIT_SHIFT_FREERUN_CNT_8822B) -#define BIT_GET_FREERUN_CNT_8822B(x) (((x) >> BIT_SHIFT_FREERUN_CNT_8822B) & BIT_MASK_FREERUN_CNT_8822B) - - +#define BIT_FREERUN_CNT_8822B(x) \ + (((x) & BIT_MASK_FREERUN_CNT_8822B) << BIT_SHIFT_FREERUN_CNT_8822B) +#define BITS_FREERUN_CNT_8822B \ + (BIT_MASK_FREERUN_CNT_8822B << BIT_SHIFT_FREERUN_CNT_8822B) +#define BIT_CLEAR_FREERUN_CNT_8822B(x) ((x) & (~BITS_FREERUN_CNT_8822B)) +#define BIT_GET_FREERUN_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_8822B) & BIT_MASK_FREERUN_CNT_8822B) +#define BIT_SET_FREERUN_CNT_8822B(x, v) \ + (BIT_CLEAR_FREERUN_CNT_8822B(x) | BIT_FREERUN_CNT_8822B(v)) /* 2 REG_ATIMWND1_V1_8822B */ #define BIT_SHIFT_ATIMWND1_V1_8822B 0 #define BIT_MASK_ATIMWND1_V1_8822B 0xff -#define BIT_ATIMWND1_V1_8822B(x) (((x) & BIT_MASK_ATIMWND1_V1_8822B) << BIT_SHIFT_ATIMWND1_V1_8822B) -#define BIT_GET_ATIMWND1_V1_8822B(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8822B) & BIT_MASK_ATIMWND1_V1_8822B) - - +#define BIT_ATIMWND1_V1_8822B(x) \ + (((x) & BIT_MASK_ATIMWND1_V1_8822B) << BIT_SHIFT_ATIMWND1_V1_8822B) +#define BITS_ATIMWND1_V1_8822B \ + (BIT_MASK_ATIMWND1_V1_8822B << BIT_SHIFT_ATIMWND1_V1_8822B) +#define BIT_CLEAR_ATIMWND1_V1_8822B(x) ((x) & (~BITS_ATIMWND1_V1_8822B)) +#define BIT_GET_ATIMWND1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND1_V1_8822B) & BIT_MASK_ATIMWND1_V1_8822B) +#define BIT_SET_ATIMWND1_V1_8822B(x, v) \ + (BIT_CLEAR_ATIMWND1_V1_8822B(x) | BIT_ATIMWND1_V1_8822B(v)) /* 2 REG_TBTT_PROHIBIT_INFRA_8822B */ #define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B 0 #define BIT_MASK_TBTT_PROHIBIT_INFRA_8822B 0xff -#define BIT_TBTT_PROHIBIT_INFRA_8822B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) -#define BIT_GET_TBTT_PROHIBIT_INFRA_8822B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B) - - +#define BIT_TBTT_PROHIBIT_INFRA_8822B(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B) \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) +#define BITS_TBTT_PROHIBIT_INFRA_8822B \ + (BIT_MASK_TBTT_PROHIBIT_INFRA_8822B \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) +#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822B(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8822B)) +#define BIT_GET_TBTT_PROHIBIT_INFRA_8822B(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) & \ + BIT_MASK_TBTT_PROHIBIT_INFRA_8822B) +#define BIT_SET_TBTT_PROHIBIT_INFRA_8822B(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822B(x) | \ + BIT_TBTT_PROHIBIT_INFRA_8822B(v)) /* 2 REG_CTWND_8822B */ #define BIT_SHIFT_CTWND_8822B 0 #define BIT_MASK_CTWND_8822B 0xff -#define BIT_CTWND_8822B(x) (((x) & BIT_MASK_CTWND_8822B) << BIT_SHIFT_CTWND_8822B) -#define BIT_GET_CTWND_8822B(x) (((x) >> BIT_SHIFT_CTWND_8822B) & BIT_MASK_CTWND_8822B) - - +#define BIT_CTWND_8822B(x) \ + (((x) & BIT_MASK_CTWND_8822B) << BIT_SHIFT_CTWND_8822B) +#define BITS_CTWND_8822B (BIT_MASK_CTWND_8822B << BIT_SHIFT_CTWND_8822B) +#define BIT_CLEAR_CTWND_8822B(x) ((x) & (~BITS_CTWND_8822B)) +#define BIT_GET_CTWND_8822B(x) \ + (((x) >> BIT_SHIFT_CTWND_8822B) & BIT_MASK_CTWND_8822B) +#define BIT_SET_CTWND_8822B(x, v) \ + (BIT_CLEAR_CTWND_8822B(x) | BIT_CTWND_8822B(v)) /* 2 REG_BCNIVLCUNT_8822B */ #define BIT_SHIFT_BCNIVLCUNT_8822B 0 #define BIT_MASK_BCNIVLCUNT_8822B 0x7f -#define BIT_BCNIVLCUNT_8822B(x) (((x) & BIT_MASK_BCNIVLCUNT_8822B) << BIT_SHIFT_BCNIVLCUNT_8822B) -#define BIT_GET_BCNIVLCUNT_8822B(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8822B) & BIT_MASK_BCNIVLCUNT_8822B) - - +#define BIT_BCNIVLCUNT_8822B(x) \ + (((x) & BIT_MASK_BCNIVLCUNT_8822B) << BIT_SHIFT_BCNIVLCUNT_8822B) +#define BITS_BCNIVLCUNT_8822B \ + (BIT_MASK_BCNIVLCUNT_8822B << BIT_SHIFT_BCNIVLCUNT_8822B) +#define BIT_CLEAR_BCNIVLCUNT_8822B(x) ((x) & (~BITS_BCNIVLCUNT_8822B)) +#define BIT_GET_BCNIVLCUNT_8822B(x) \ + (((x) >> BIT_SHIFT_BCNIVLCUNT_8822B) & BIT_MASK_BCNIVLCUNT_8822B) +#define BIT_SET_BCNIVLCUNT_8822B(x, v) \ + (BIT_CLEAR_BCNIVLCUNT_8822B(x) | BIT_BCNIVLCUNT_8822B(v)) /* 2 REG_BCNDROPCTRL_8822B */ #define BIT_BEACON_DROP_EN_8822B BIT(7) #define BIT_SHIFT_BEACON_DROP_IVL_8822B 0 #define BIT_MASK_BEACON_DROP_IVL_8822B 0x7f -#define BIT_BEACON_DROP_IVL_8822B(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8822B) << BIT_SHIFT_BEACON_DROP_IVL_8822B) -#define BIT_GET_BEACON_DROP_IVL_8822B(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822B) & BIT_MASK_BEACON_DROP_IVL_8822B) - - +#define BIT_BEACON_DROP_IVL_8822B(x) \ + (((x) & BIT_MASK_BEACON_DROP_IVL_8822B) \ + << BIT_SHIFT_BEACON_DROP_IVL_8822B) +#define BITS_BEACON_DROP_IVL_8822B \ + (BIT_MASK_BEACON_DROP_IVL_8822B << BIT_SHIFT_BEACON_DROP_IVL_8822B) +#define BIT_CLEAR_BEACON_DROP_IVL_8822B(x) ((x) & (~BITS_BEACON_DROP_IVL_8822B)) +#define BIT_GET_BEACON_DROP_IVL_8822B(x) \ + (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822B) & \ + BIT_MASK_BEACON_DROP_IVL_8822B) +#define BIT_SET_BEACON_DROP_IVL_8822B(x, v) \ + (BIT_CLEAR_BEACON_DROP_IVL_8822B(x) | BIT_BEACON_DROP_IVL_8822B(v)) /* 2 REG_HGQ_TIMEOUT_PERIOD_8822B */ #define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B 0 #define BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B 0xff -#define BIT_HGQ_TIMEOUT_PERIOD_8822B(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) -#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822B(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B) - - +#define BIT_HGQ_TIMEOUT_PERIOD_8822B(x) \ + (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B) \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) +#define BITS_HGQ_TIMEOUT_PERIOD_8822B \ + (BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822B(x) \ + ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8822B)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822B(x) \ + (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) & \ + BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B) +#define BIT_SET_HGQ_TIMEOUT_PERIOD_8822B(x, v) \ + (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822B(x) | \ + BIT_HGQ_TIMEOUT_PERIOD_8822B(v)) /* 2 REG_TXCMD_TIMEOUT_PERIOD_8822B */ #define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B 0 #define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B 0xff -#define BIT_TXCMD_TIMEOUT_PERIOD_8822B(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) -#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822B(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B) - - +#define BIT_TXCMD_TIMEOUT_PERIOD_8822B(x) \ + (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B) \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) +#define BITS_TXCMD_TIMEOUT_PERIOD_8822B \ + (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822B(x) \ + ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8822B)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822B(x) \ + (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) & \ + BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8822B(x, v) \ + (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822B(x) | \ + BIT_TXCMD_TIMEOUT_PERIOD_8822B(v)) /* 2 REG_MISC_CTRL_8822B */ +#define BIT_AUTO_SYNC_BY_TBTT_8822B BIT(6) #define BIT_DIS_TRX_CAL_BCN_8822B BIT(5) #define BIT_DIS_TX_CAL_TBTT_8822B BIT(4) #define BIT_EN_FREECNT_8822B BIT(3) @@ -7623,10 +12148,18 @@ #define BIT_SHIFT_DIS_SECONDARY_CCA_8822B 0 #define BIT_MASK_DIS_SECONDARY_CCA_8822B 0x3 -#define BIT_DIS_SECONDARY_CCA_8822B(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8822B) << BIT_SHIFT_DIS_SECONDARY_CCA_8822B) -#define BIT_GET_DIS_SECONDARY_CCA_8822B(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822B) & BIT_MASK_DIS_SECONDARY_CCA_8822B) - - +#define BIT_DIS_SECONDARY_CCA_8822B(x) \ + (((x) & BIT_MASK_DIS_SECONDARY_CCA_8822B) \ + << BIT_SHIFT_DIS_SECONDARY_CCA_8822B) +#define BITS_DIS_SECONDARY_CCA_8822B \ + (BIT_MASK_DIS_SECONDARY_CCA_8822B << BIT_SHIFT_DIS_SECONDARY_CCA_8822B) +#define BIT_CLEAR_DIS_SECONDARY_CCA_8822B(x) \ + ((x) & (~BITS_DIS_SECONDARY_CCA_8822B)) +#define BIT_GET_DIS_SECONDARY_CCA_8822B(x) \ + (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822B) & \ + BIT_MASK_DIS_SECONDARY_CCA_8822B) +#define BIT_SET_DIS_SECONDARY_CCA_8822B(x, v) \ + (BIT_CLEAR_DIS_SECONDARY_CCA_8822B(x) | BIT_DIS_SECONDARY_CCA_8822B(v)) /* 2 REG_BCN_CTRL_CLINT1_8822B */ #define BIT_CLI1_DIS_RX_BSSID_FIT_8822B BIT(6) @@ -7658,10 +12191,15 @@ #define BIT_SHIFT_PORT_SEL_8822B 0 #define BIT_MASK_PORT_SEL_8822B 0x7 -#define BIT_PORT_SEL_8822B(x) (((x) & BIT_MASK_PORT_SEL_8822B) << BIT_SHIFT_PORT_SEL_8822B) -#define BIT_GET_PORT_SEL_8822B(x) (((x) >> BIT_SHIFT_PORT_SEL_8822B) & BIT_MASK_PORT_SEL_8822B) - - +#define BIT_PORT_SEL_8822B(x) \ + (((x) & BIT_MASK_PORT_SEL_8822B) << BIT_SHIFT_PORT_SEL_8822B) +#define BITS_PORT_SEL_8822B \ + (BIT_MASK_PORT_SEL_8822B << BIT_SHIFT_PORT_SEL_8822B) +#define BIT_CLEAR_PORT_SEL_8822B(x) ((x) & (~BITS_PORT_SEL_8822B)) +#define BIT_GET_PORT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_PORT_SEL_8822B) & BIT_MASK_PORT_SEL_8822B) +#define BIT_SET_PORT_SEL_8822B(x, v) \ + (BIT_CLEAR_PORT_SEL_8822B(x) | BIT_PORT_SEL_8822B(v)) /* 2 REG_P2PPS1_SPEC_STATE_8822B */ #define BIT_P2P1_SPEC_POWER_STATE_8822B BIT(7) @@ -7707,64 +12245,99 @@ #define BIT_SHIFT_PSTIMER0_INT_8822B 5 #define BIT_MASK_PSTIMER0_INT_8822B 0x7ffffff -#define BIT_PSTIMER0_INT_8822B(x) (((x) & BIT_MASK_PSTIMER0_INT_8822B) << BIT_SHIFT_PSTIMER0_INT_8822B) -#define BIT_GET_PSTIMER0_INT_8822B(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8822B) & BIT_MASK_PSTIMER0_INT_8822B) - - +#define BIT_PSTIMER0_INT_8822B(x) \ + (((x) & BIT_MASK_PSTIMER0_INT_8822B) << BIT_SHIFT_PSTIMER0_INT_8822B) +#define BITS_PSTIMER0_INT_8822B \ + (BIT_MASK_PSTIMER0_INT_8822B << BIT_SHIFT_PSTIMER0_INT_8822B) +#define BIT_CLEAR_PSTIMER0_INT_8822B(x) ((x) & (~BITS_PSTIMER0_INT_8822B)) +#define BIT_GET_PSTIMER0_INT_8822B(x) \ + (((x) >> BIT_SHIFT_PSTIMER0_INT_8822B) & BIT_MASK_PSTIMER0_INT_8822B) +#define BIT_SET_PSTIMER0_INT_8822B(x, v) \ + (BIT_CLEAR_PSTIMER0_INT_8822B(x) | BIT_PSTIMER0_INT_8822B(v)) /* 2 REG_PS_TIMER1_8822B */ #define BIT_SHIFT_PSTIMER1_INT_8822B 5 #define BIT_MASK_PSTIMER1_INT_8822B 0x7ffffff -#define BIT_PSTIMER1_INT_8822B(x) (((x) & BIT_MASK_PSTIMER1_INT_8822B) << BIT_SHIFT_PSTIMER1_INT_8822B) -#define BIT_GET_PSTIMER1_INT_8822B(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8822B) & BIT_MASK_PSTIMER1_INT_8822B) - - +#define BIT_PSTIMER1_INT_8822B(x) \ + (((x) & BIT_MASK_PSTIMER1_INT_8822B) << BIT_SHIFT_PSTIMER1_INT_8822B) +#define BITS_PSTIMER1_INT_8822B \ + (BIT_MASK_PSTIMER1_INT_8822B << BIT_SHIFT_PSTIMER1_INT_8822B) +#define BIT_CLEAR_PSTIMER1_INT_8822B(x) ((x) & (~BITS_PSTIMER1_INT_8822B)) +#define BIT_GET_PSTIMER1_INT_8822B(x) \ + (((x) >> BIT_SHIFT_PSTIMER1_INT_8822B) & BIT_MASK_PSTIMER1_INT_8822B) +#define BIT_SET_PSTIMER1_INT_8822B(x, v) \ + (BIT_CLEAR_PSTIMER1_INT_8822B(x) | BIT_PSTIMER1_INT_8822B(v)) /* 2 REG_PS_TIMER2_8822B */ #define BIT_SHIFT_PSTIMER2_INT_8822B 5 #define BIT_MASK_PSTIMER2_INT_8822B 0x7ffffff -#define BIT_PSTIMER2_INT_8822B(x) (((x) & BIT_MASK_PSTIMER2_INT_8822B) << BIT_SHIFT_PSTIMER2_INT_8822B) -#define BIT_GET_PSTIMER2_INT_8822B(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8822B) & BIT_MASK_PSTIMER2_INT_8822B) - - +#define BIT_PSTIMER2_INT_8822B(x) \ + (((x) & BIT_MASK_PSTIMER2_INT_8822B) << BIT_SHIFT_PSTIMER2_INT_8822B) +#define BITS_PSTIMER2_INT_8822B \ + (BIT_MASK_PSTIMER2_INT_8822B << BIT_SHIFT_PSTIMER2_INT_8822B) +#define BIT_CLEAR_PSTIMER2_INT_8822B(x) ((x) & (~BITS_PSTIMER2_INT_8822B)) +#define BIT_GET_PSTIMER2_INT_8822B(x) \ + (((x) >> BIT_SHIFT_PSTIMER2_INT_8822B) & BIT_MASK_PSTIMER2_INT_8822B) +#define BIT_SET_PSTIMER2_INT_8822B(x, v) \ + (BIT_CLEAR_PSTIMER2_INT_8822B(x) | BIT_PSTIMER2_INT_8822B(v)) /* 2 REG_TBTT_CTN_AREA_8822B */ #define BIT_SHIFT_TBTT_CTN_AREA_8822B 0 #define BIT_MASK_TBTT_CTN_AREA_8822B 0xff -#define BIT_TBTT_CTN_AREA_8822B(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8822B) << BIT_SHIFT_TBTT_CTN_AREA_8822B) -#define BIT_GET_TBTT_CTN_AREA_8822B(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822B) & BIT_MASK_TBTT_CTN_AREA_8822B) - - +#define BIT_TBTT_CTN_AREA_8822B(x) \ + (((x) & BIT_MASK_TBTT_CTN_AREA_8822B) << BIT_SHIFT_TBTT_CTN_AREA_8822B) +#define BITS_TBTT_CTN_AREA_8822B \ + (BIT_MASK_TBTT_CTN_AREA_8822B << BIT_SHIFT_TBTT_CTN_AREA_8822B) +#define BIT_CLEAR_TBTT_CTN_AREA_8822B(x) ((x) & (~BITS_TBTT_CTN_AREA_8822B)) +#define BIT_GET_TBTT_CTN_AREA_8822B(x) \ + (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822B) & BIT_MASK_TBTT_CTN_AREA_8822B) +#define BIT_SET_TBTT_CTN_AREA_8822B(x, v) \ + (BIT_CLEAR_TBTT_CTN_AREA_8822B(x) | BIT_TBTT_CTN_AREA_8822B(v)) /* 2 REG_FORCE_BCN_IFS_8822B */ #define BIT_SHIFT_FORCE_BCN_IFS_8822B 0 #define BIT_MASK_FORCE_BCN_IFS_8822B 0xff -#define BIT_FORCE_BCN_IFS_8822B(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8822B) << BIT_SHIFT_FORCE_BCN_IFS_8822B) -#define BIT_GET_FORCE_BCN_IFS_8822B(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822B) & BIT_MASK_FORCE_BCN_IFS_8822B) - - +#define BIT_FORCE_BCN_IFS_8822B(x) \ + (((x) & BIT_MASK_FORCE_BCN_IFS_8822B) << BIT_SHIFT_FORCE_BCN_IFS_8822B) +#define BITS_FORCE_BCN_IFS_8822B \ + (BIT_MASK_FORCE_BCN_IFS_8822B << BIT_SHIFT_FORCE_BCN_IFS_8822B) +#define BIT_CLEAR_FORCE_BCN_IFS_8822B(x) ((x) & (~BITS_FORCE_BCN_IFS_8822B)) +#define BIT_GET_FORCE_BCN_IFS_8822B(x) \ + (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822B) & BIT_MASK_FORCE_BCN_IFS_8822B) +#define BIT_SET_FORCE_BCN_IFS_8822B(x, v) \ + (BIT_CLEAR_FORCE_BCN_IFS_8822B(x) | BIT_FORCE_BCN_IFS_8822B(v)) /* 2 REG_TXOP_MIN_8822B */ #define BIT_SHIFT_TXOP_MIN_8822B 0 #define BIT_MASK_TXOP_MIN_8822B 0x3fff -#define BIT_TXOP_MIN_8822B(x) (((x) & BIT_MASK_TXOP_MIN_8822B) << BIT_SHIFT_TXOP_MIN_8822B) -#define BIT_GET_TXOP_MIN_8822B(x) (((x) >> BIT_SHIFT_TXOP_MIN_8822B) & BIT_MASK_TXOP_MIN_8822B) - - +#define BIT_TXOP_MIN_8822B(x) \ + (((x) & BIT_MASK_TXOP_MIN_8822B) << BIT_SHIFT_TXOP_MIN_8822B) +#define BITS_TXOP_MIN_8822B \ + (BIT_MASK_TXOP_MIN_8822B << BIT_SHIFT_TXOP_MIN_8822B) +#define BIT_CLEAR_TXOP_MIN_8822B(x) ((x) & (~BITS_TXOP_MIN_8822B)) +#define BIT_GET_TXOP_MIN_8822B(x) \ + (((x) >> BIT_SHIFT_TXOP_MIN_8822B) & BIT_MASK_TXOP_MIN_8822B) +#define BIT_SET_TXOP_MIN_8822B(x, v) \ + (BIT_CLEAR_TXOP_MIN_8822B(x) | BIT_TXOP_MIN_8822B(v)) /* 2 REG_PRE_BKF_TIME_8822B */ #define BIT_SHIFT_PRE_BKF_TIME_8822B 0 #define BIT_MASK_PRE_BKF_TIME_8822B 0xff -#define BIT_PRE_BKF_TIME_8822B(x) (((x) & BIT_MASK_PRE_BKF_TIME_8822B) << BIT_SHIFT_PRE_BKF_TIME_8822B) -#define BIT_GET_PRE_BKF_TIME_8822B(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8822B) & BIT_MASK_PRE_BKF_TIME_8822B) - - +#define BIT_PRE_BKF_TIME_8822B(x) \ + (((x) & BIT_MASK_PRE_BKF_TIME_8822B) << BIT_SHIFT_PRE_BKF_TIME_8822B) +#define BITS_PRE_BKF_TIME_8822B \ + (BIT_MASK_PRE_BKF_TIME_8822B << BIT_SHIFT_PRE_BKF_TIME_8822B) +#define BIT_CLEAR_PRE_BKF_TIME_8822B(x) ((x) & (~BITS_PRE_BKF_TIME_8822B)) +#define BIT_GET_PRE_BKF_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_PRE_BKF_TIME_8822B) & BIT_MASK_PRE_BKF_TIME_8822B) +#define BIT_SET_PRE_BKF_TIME_8822B(x, v) \ + (BIT_CLEAR_PRE_BKF_TIME_8822B(x) | BIT_PRE_BKF_TIME_8822B(v)) /* 2 REG_CROSS_TXOP_CTRL_8822B */ #define BIT_DTIM_BYPASS_8822B BIT(2) @@ -7775,64 +12348,99 @@ #define BIT_SHIFT_ATIMWND2_8822B 0 #define BIT_MASK_ATIMWND2_8822B 0xff -#define BIT_ATIMWND2_8822B(x) (((x) & BIT_MASK_ATIMWND2_8822B) << BIT_SHIFT_ATIMWND2_8822B) -#define BIT_GET_ATIMWND2_8822B(x) (((x) >> BIT_SHIFT_ATIMWND2_8822B) & BIT_MASK_ATIMWND2_8822B) - - +#define BIT_ATIMWND2_8822B(x) \ + (((x) & BIT_MASK_ATIMWND2_8822B) << BIT_SHIFT_ATIMWND2_8822B) +#define BITS_ATIMWND2_8822B \ + (BIT_MASK_ATIMWND2_8822B << BIT_SHIFT_ATIMWND2_8822B) +#define BIT_CLEAR_ATIMWND2_8822B(x) ((x) & (~BITS_ATIMWND2_8822B)) +#define BIT_GET_ATIMWND2_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND2_8822B) & BIT_MASK_ATIMWND2_8822B) +#define BIT_SET_ATIMWND2_8822B(x, v) \ + (BIT_CLEAR_ATIMWND2_8822B(x) | BIT_ATIMWND2_8822B(v)) /* 2 REG_ATIMWND3_8822B */ #define BIT_SHIFT_ATIMWND3_8822B 0 #define BIT_MASK_ATIMWND3_8822B 0xff -#define BIT_ATIMWND3_8822B(x) (((x) & BIT_MASK_ATIMWND3_8822B) << BIT_SHIFT_ATIMWND3_8822B) -#define BIT_GET_ATIMWND3_8822B(x) (((x) >> BIT_SHIFT_ATIMWND3_8822B) & BIT_MASK_ATIMWND3_8822B) - - +#define BIT_ATIMWND3_8822B(x) \ + (((x) & BIT_MASK_ATIMWND3_8822B) << BIT_SHIFT_ATIMWND3_8822B) +#define BITS_ATIMWND3_8822B \ + (BIT_MASK_ATIMWND3_8822B << BIT_SHIFT_ATIMWND3_8822B) +#define BIT_CLEAR_ATIMWND3_8822B(x) ((x) & (~BITS_ATIMWND3_8822B)) +#define BIT_GET_ATIMWND3_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND3_8822B) & BIT_MASK_ATIMWND3_8822B) +#define BIT_SET_ATIMWND3_8822B(x, v) \ + (BIT_CLEAR_ATIMWND3_8822B(x) | BIT_ATIMWND3_8822B(v)) /* 2 REG_ATIMWND4_8822B */ #define BIT_SHIFT_ATIMWND4_8822B 0 #define BIT_MASK_ATIMWND4_8822B 0xff -#define BIT_ATIMWND4_8822B(x) (((x) & BIT_MASK_ATIMWND4_8822B) << BIT_SHIFT_ATIMWND4_8822B) -#define BIT_GET_ATIMWND4_8822B(x) (((x) >> BIT_SHIFT_ATIMWND4_8822B) & BIT_MASK_ATIMWND4_8822B) - - +#define BIT_ATIMWND4_8822B(x) \ + (((x) & BIT_MASK_ATIMWND4_8822B) << BIT_SHIFT_ATIMWND4_8822B) +#define BITS_ATIMWND4_8822B \ + (BIT_MASK_ATIMWND4_8822B << BIT_SHIFT_ATIMWND4_8822B) +#define BIT_CLEAR_ATIMWND4_8822B(x) ((x) & (~BITS_ATIMWND4_8822B)) +#define BIT_GET_ATIMWND4_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND4_8822B) & BIT_MASK_ATIMWND4_8822B) +#define BIT_SET_ATIMWND4_8822B(x, v) \ + (BIT_CLEAR_ATIMWND4_8822B(x) | BIT_ATIMWND4_8822B(v)) /* 2 REG_ATIMWND5_8822B */ #define BIT_SHIFT_ATIMWND5_8822B 0 #define BIT_MASK_ATIMWND5_8822B 0xff -#define BIT_ATIMWND5_8822B(x) (((x) & BIT_MASK_ATIMWND5_8822B) << BIT_SHIFT_ATIMWND5_8822B) -#define BIT_GET_ATIMWND5_8822B(x) (((x) >> BIT_SHIFT_ATIMWND5_8822B) & BIT_MASK_ATIMWND5_8822B) - - +#define BIT_ATIMWND5_8822B(x) \ + (((x) & BIT_MASK_ATIMWND5_8822B) << BIT_SHIFT_ATIMWND5_8822B) +#define BITS_ATIMWND5_8822B \ + (BIT_MASK_ATIMWND5_8822B << BIT_SHIFT_ATIMWND5_8822B) +#define BIT_CLEAR_ATIMWND5_8822B(x) ((x) & (~BITS_ATIMWND5_8822B)) +#define BIT_GET_ATIMWND5_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND5_8822B) & BIT_MASK_ATIMWND5_8822B) +#define BIT_SET_ATIMWND5_8822B(x, v) \ + (BIT_CLEAR_ATIMWND5_8822B(x) | BIT_ATIMWND5_8822B(v)) /* 2 REG_ATIMWND6_8822B */ #define BIT_SHIFT_ATIMWND6_8822B 0 #define BIT_MASK_ATIMWND6_8822B 0xff -#define BIT_ATIMWND6_8822B(x) (((x) & BIT_MASK_ATIMWND6_8822B) << BIT_SHIFT_ATIMWND6_8822B) -#define BIT_GET_ATIMWND6_8822B(x) (((x) >> BIT_SHIFT_ATIMWND6_8822B) & BIT_MASK_ATIMWND6_8822B) - - +#define BIT_ATIMWND6_8822B(x) \ + (((x) & BIT_MASK_ATIMWND6_8822B) << BIT_SHIFT_ATIMWND6_8822B) +#define BITS_ATIMWND6_8822B \ + (BIT_MASK_ATIMWND6_8822B << BIT_SHIFT_ATIMWND6_8822B) +#define BIT_CLEAR_ATIMWND6_8822B(x) ((x) & (~BITS_ATIMWND6_8822B)) +#define BIT_GET_ATIMWND6_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND6_8822B) & BIT_MASK_ATIMWND6_8822B) +#define BIT_SET_ATIMWND6_8822B(x, v) \ + (BIT_CLEAR_ATIMWND6_8822B(x) | BIT_ATIMWND6_8822B(v)) /* 2 REG_ATIMWND7_8822B */ #define BIT_SHIFT_ATIMWND7_8822B 0 #define BIT_MASK_ATIMWND7_8822B 0xff -#define BIT_ATIMWND7_8822B(x) (((x) & BIT_MASK_ATIMWND7_8822B) << BIT_SHIFT_ATIMWND7_8822B) -#define BIT_GET_ATIMWND7_8822B(x) (((x) >> BIT_SHIFT_ATIMWND7_8822B) & BIT_MASK_ATIMWND7_8822B) - - +#define BIT_ATIMWND7_8822B(x) \ + (((x) & BIT_MASK_ATIMWND7_8822B) << BIT_SHIFT_ATIMWND7_8822B) +#define BITS_ATIMWND7_8822B \ + (BIT_MASK_ATIMWND7_8822B << BIT_SHIFT_ATIMWND7_8822B) +#define BIT_CLEAR_ATIMWND7_8822B(x) ((x) & (~BITS_ATIMWND7_8822B)) +#define BIT_GET_ATIMWND7_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND7_8822B) & BIT_MASK_ATIMWND7_8822B) +#define BIT_SET_ATIMWND7_8822B(x, v) \ + (BIT_CLEAR_ATIMWND7_8822B(x) | BIT_ATIMWND7_8822B(v)) /* 2 REG_ATIMUGT_8822B */ #define BIT_SHIFT_ATIM_URGENT_8822B 0 #define BIT_MASK_ATIM_URGENT_8822B 0xff -#define BIT_ATIM_URGENT_8822B(x) (((x) & BIT_MASK_ATIM_URGENT_8822B) << BIT_SHIFT_ATIM_URGENT_8822B) -#define BIT_GET_ATIM_URGENT_8822B(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8822B) & BIT_MASK_ATIM_URGENT_8822B) - - +#define BIT_ATIM_URGENT_8822B(x) \ + (((x) & BIT_MASK_ATIM_URGENT_8822B) << BIT_SHIFT_ATIM_URGENT_8822B) +#define BITS_ATIM_URGENT_8822B \ + (BIT_MASK_ATIM_URGENT_8822B << BIT_SHIFT_ATIM_URGENT_8822B) +#define BIT_CLEAR_ATIM_URGENT_8822B(x) ((x) & (~BITS_ATIM_URGENT_8822B)) +#define BIT_GET_ATIM_URGENT_8822B(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT_8822B) & BIT_MASK_ATIM_URGENT_8822B) +#define BIT_SET_ATIM_URGENT_8822B(x, v) \ + (BIT_CLEAR_ATIM_URGENT_8822B(x) | BIT_ATIM_URGENT_8822B(v)) /* 2 REG_HIQ_NO_LMT_EN_8822B */ #define BIT_HIQ_NO_LMT_EN_VAP7_8822B BIT(7) @@ -7848,73 +12456,129 @@ #define BIT_SHIFT_DTIM_COUNT_ROOT_8822B 0 #define BIT_MASK_DTIM_COUNT_ROOT_8822B 0xff -#define BIT_DTIM_COUNT_ROOT_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8822B) << BIT_SHIFT_DTIM_COUNT_ROOT_8822B) -#define BIT_GET_DTIM_COUNT_ROOT_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822B) & BIT_MASK_DTIM_COUNT_ROOT_8822B) - - +#define BIT_DTIM_COUNT_ROOT_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_ROOT_8822B) \ + << BIT_SHIFT_DTIM_COUNT_ROOT_8822B) +#define BITS_DTIM_COUNT_ROOT_8822B \ + (BIT_MASK_DTIM_COUNT_ROOT_8822B << BIT_SHIFT_DTIM_COUNT_ROOT_8822B) +#define BIT_CLEAR_DTIM_COUNT_ROOT_8822B(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8822B)) +#define BIT_GET_DTIM_COUNT_ROOT_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822B) & \ + BIT_MASK_DTIM_COUNT_ROOT_8822B) +#define BIT_SET_DTIM_COUNT_ROOT_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_ROOT_8822B(x) | BIT_DTIM_COUNT_ROOT_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP1_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP1_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP1_8822B 0xff -#define BIT_DTIM_COUNT_VAP1_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8822B) << BIT_SHIFT_DTIM_COUNT_VAP1_8822B) -#define BIT_GET_DTIM_COUNT_VAP1_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822B) & BIT_MASK_DTIM_COUNT_VAP1_8822B) - - +#define BIT_DTIM_COUNT_VAP1_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP1_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP1_8822B) +#define BITS_DTIM_COUNT_VAP1_8822B \ + (BIT_MASK_DTIM_COUNT_VAP1_8822B << BIT_SHIFT_DTIM_COUNT_VAP1_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP1_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8822B)) +#define BIT_GET_DTIM_COUNT_VAP1_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP1_8822B) +#define BIT_SET_DTIM_COUNT_VAP1_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP1_8822B(x) | BIT_DTIM_COUNT_VAP1_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP2_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP2_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP2_8822B 0xff -#define BIT_DTIM_COUNT_VAP2_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8822B) << BIT_SHIFT_DTIM_COUNT_VAP2_8822B) -#define BIT_GET_DTIM_COUNT_VAP2_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822B) & BIT_MASK_DTIM_COUNT_VAP2_8822B) - - +#define BIT_DTIM_COUNT_VAP2_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP2_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP2_8822B) +#define BITS_DTIM_COUNT_VAP2_8822B \ + (BIT_MASK_DTIM_COUNT_VAP2_8822B << BIT_SHIFT_DTIM_COUNT_VAP2_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP2_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8822B)) +#define BIT_GET_DTIM_COUNT_VAP2_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP2_8822B) +#define BIT_SET_DTIM_COUNT_VAP2_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP2_8822B(x) | BIT_DTIM_COUNT_VAP2_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP3_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP3_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP3_8822B 0xff -#define BIT_DTIM_COUNT_VAP3_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8822B) << BIT_SHIFT_DTIM_COUNT_VAP3_8822B) -#define BIT_GET_DTIM_COUNT_VAP3_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822B) & BIT_MASK_DTIM_COUNT_VAP3_8822B) - - +#define BIT_DTIM_COUNT_VAP3_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP3_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP3_8822B) +#define BITS_DTIM_COUNT_VAP3_8822B \ + (BIT_MASK_DTIM_COUNT_VAP3_8822B << BIT_SHIFT_DTIM_COUNT_VAP3_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP3_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8822B)) +#define BIT_GET_DTIM_COUNT_VAP3_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP3_8822B) +#define BIT_SET_DTIM_COUNT_VAP3_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP3_8822B(x) | BIT_DTIM_COUNT_VAP3_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP4_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP4_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP4_8822B 0xff -#define BIT_DTIM_COUNT_VAP4_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8822B) << BIT_SHIFT_DTIM_COUNT_VAP4_8822B) -#define BIT_GET_DTIM_COUNT_VAP4_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822B) & BIT_MASK_DTIM_COUNT_VAP4_8822B) - - +#define BIT_DTIM_COUNT_VAP4_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP4_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP4_8822B) +#define BITS_DTIM_COUNT_VAP4_8822B \ + (BIT_MASK_DTIM_COUNT_VAP4_8822B << BIT_SHIFT_DTIM_COUNT_VAP4_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP4_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8822B)) +#define BIT_GET_DTIM_COUNT_VAP4_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP4_8822B) +#define BIT_SET_DTIM_COUNT_VAP4_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP4_8822B(x) | BIT_DTIM_COUNT_VAP4_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP5_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP5_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP5_8822B 0xff -#define BIT_DTIM_COUNT_VAP5_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8822B) << BIT_SHIFT_DTIM_COUNT_VAP5_8822B) -#define BIT_GET_DTIM_COUNT_VAP5_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822B) & BIT_MASK_DTIM_COUNT_VAP5_8822B) - - +#define BIT_DTIM_COUNT_VAP5_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP5_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP5_8822B) +#define BITS_DTIM_COUNT_VAP5_8822B \ + (BIT_MASK_DTIM_COUNT_VAP5_8822B << BIT_SHIFT_DTIM_COUNT_VAP5_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP5_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8822B)) +#define BIT_GET_DTIM_COUNT_VAP5_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP5_8822B) +#define BIT_SET_DTIM_COUNT_VAP5_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP5_8822B(x) | BIT_DTIM_COUNT_VAP5_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP6_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP6_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP6_8822B 0xff -#define BIT_DTIM_COUNT_VAP6_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8822B) << BIT_SHIFT_DTIM_COUNT_VAP6_8822B) -#define BIT_GET_DTIM_COUNT_VAP6_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822B) & BIT_MASK_DTIM_COUNT_VAP6_8822B) - - +#define BIT_DTIM_COUNT_VAP6_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP6_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP6_8822B) +#define BITS_DTIM_COUNT_VAP6_8822B \ + (BIT_MASK_DTIM_COUNT_VAP6_8822B << BIT_SHIFT_DTIM_COUNT_VAP6_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP6_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8822B)) +#define BIT_GET_DTIM_COUNT_VAP6_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP6_8822B) +#define BIT_SET_DTIM_COUNT_VAP6_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP6_8822B(x) | BIT_DTIM_COUNT_VAP6_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP7_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP7_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP7_8822B 0xff -#define BIT_DTIM_COUNT_VAP7_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8822B) << BIT_SHIFT_DTIM_COUNT_VAP7_8822B) -#define BIT_GET_DTIM_COUNT_VAP7_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822B) & BIT_MASK_DTIM_COUNT_VAP7_8822B) - - +#define BIT_DTIM_COUNT_VAP7_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP7_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP7_8822B) +#define BITS_DTIM_COUNT_VAP7_8822B \ + (BIT_MASK_DTIM_COUNT_VAP7_8822B << BIT_SHIFT_DTIM_COUNT_VAP7_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP7_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8822B)) +#define BIT_GET_DTIM_COUNT_VAP7_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP7_8822B) +#define BIT_SET_DTIM_COUNT_VAP7_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP7_8822B(x) | BIT_DTIM_COUNT_VAP7_8822B(v)) /* 2 REG_DIS_ATIM_8822B */ #define BIT_DIS_ATIM_VAP7_8822B BIT(7) @@ -7930,17 +12594,29 @@ #define BIT_SHIFT_TSFT_SEL_TIMER1_8822B 3 #define BIT_MASK_TSFT_SEL_TIMER1_8822B 0x7 -#define BIT_TSFT_SEL_TIMER1_8822B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8822B) << BIT_SHIFT_TSFT_SEL_TIMER1_8822B) -#define BIT_GET_TSFT_SEL_TIMER1_8822B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822B) & BIT_MASK_TSFT_SEL_TIMER1_8822B) - - +#define BIT_TSFT_SEL_TIMER1_8822B(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER1_8822B) \ + << BIT_SHIFT_TSFT_SEL_TIMER1_8822B) +#define BITS_TSFT_SEL_TIMER1_8822B \ + (BIT_MASK_TSFT_SEL_TIMER1_8822B << BIT_SHIFT_TSFT_SEL_TIMER1_8822B) +#define BIT_CLEAR_TSFT_SEL_TIMER1_8822B(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8822B)) +#define BIT_GET_TSFT_SEL_TIMER1_8822B(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822B) & \ + BIT_MASK_TSFT_SEL_TIMER1_8822B) +#define BIT_SET_TSFT_SEL_TIMER1_8822B(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER1_8822B(x) | BIT_TSFT_SEL_TIMER1_8822B(v)) #define BIT_SHIFT_EARLY_128US_8822B 0 #define BIT_MASK_EARLY_128US_8822B 0x7 -#define BIT_EARLY_128US_8822B(x) (((x) & BIT_MASK_EARLY_128US_8822B) << BIT_SHIFT_EARLY_128US_8822B) -#define BIT_GET_EARLY_128US_8822B(x) (((x) >> BIT_SHIFT_EARLY_128US_8822B) & BIT_MASK_EARLY_128US_8822B) - - +#define BIT_EARLY_128US_8822B(x) \ + (((x) & BIT_MASK_EARLY_128US_8822B) << BIT_SHIFT_EARLY_128US_8822B) +#define BITS_EARLY_128US_8822B \ + (BIT_MASK_EARLY_128US_8822B << BIT_SHIFT_EARLY_128US_8822B) +#define BIT_CLEAR_EARLY_128US_8822B(x) ((x) & (~BITS_EARLY_128US_8822B)) +#define BIT_GET_EARLY_128US_8822B(x) \ + (((x) >> BIT_SHIFT_EARLY_128US_8822B) & BIT_MASK_EARLY_128US_8822B) +#define BIT_SET_EARLY_128US_8822B(x, v) \ + (BIT_CLEAR_EARLY_128US_8822B(x) | BIT_EARLY_128US_8822B(v)) /* 2 REG_P2PPS1_CTRL_8822B */ #define BIT_P2P1_CTW_ALLSTASLEEP_8822B BIT(7) @@ -7960,81 +12636,145 @@ #define BIT_SHIFT_SYNC_CLI_SEL_8822B 4 #define BIT_MASK_SYNC_CLI_SEL_8822B 0x7 -#define BIT_SYNC_CLI_SEL_8822B(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8822B) << BIT_SHIFT_SYNC_CLI_SEL_8822B) -#define BIT_GET_SYNC_CLI_SEL_8822B(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822B) & BIT_MASK_SYNC_CLI_SEL_8822B) - - +#define BIT_SYNC_CLI_SEL_8822B(x) \ + (((x) & BIT_MASK_SYNC_CLI_SEL_8822B) << BIT_SHIFT_SYNC_CLI_SEL_8822B) +#define BITS_SYNC_CLI_SEL_8822B \ + (BIT_MASK_SYNC_CLI_SEL_8822B << BIT_SHIFT_SYNC_CLI_SEL_8822B) +#define BIT_CLEAR_SYNC_CLI_SEL_8822B(x) ((x) & (~BITS_SYNC_CLI_SEL_8822B)) +#define BIT_GET_SYNC_CLI_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822B) & BIT_MASK_SYNC_CLI_SEL_8822B) +#define BIT_SET_SYNC_CLI_SEL_8822B(x, v) \ + (BIT_CLEAR_SYNC_CLI_SEL_8822B(x) | BIT_SYNC_CLI_SEL_8822B(v)) #define BIT_SHIFT_TSFT_SEL_TIMER0_8822B 0 #define BIT_MASK_TSFT_SEL_TIMER0_8822B 0x7 -#define BIT_TSFT_SEL_TIMER0_8822B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8822B) << BIT_SHIFT_TSFT_SEL_TIMER0_8822B) -#define BIT_GET_TSFT_SEL_TIMER0_8822B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822B) & BIT_MASK_TSFT_SEL_TIMER0_8822B) - - +#define BIT_TSFT_SEL_TIMER0_8822B(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER0_8822B) \ + << BIT_SHIFT_TSFT_SEL_TIMER0_8822B) +#define BITS_TSFT_SEL_TIMER0_8822B \ + (BIT_MASK_TSFT_SEL_TIMER0_8822B << BIT_SHIFT_TSFT_SEL_TIMER0_8822B) +#define BIT_CLEAR_TSFT_SEL_TIMER0_8822B(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8822B)) +#define BIT_GET_TSFT_SEL_TIMER0_8822B(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822B) & \ + BIT_MASK_TSFT_SEL_TIMER0_8822B) +#define BIT_SET_TSFT_SEL_TIMER0_8822B(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER0_8822B(x) | BIT_TSFT_SEL_TIMER0_8822B(v)) /* 2 REG_NOA_UNIT_SEL_8822B */ #define BIT_SHIFT_NOA_UNIT2_SEL_8822B 8 #define BIT_MASK_NOA_UNIT2_SEL_8822B 0x7 -#define BIT_NOA_UNIT2_SEL_8822B(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8822B) << BIT_SHIFT_NOA_UNIT2_SEL_8822B) -#define BIT_GET_NOA_UNIT2_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822B) & BIT_MASK_NOA_UNIT2_SEL_8822B) - - +#define BIT_NOA_UNIT2_SEL_8822B(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL_8822B) << BIT_SHIFT_NOA_UNIT2_SEL_8822B) +#define BITS_NOA_UNIT2_SEL_8822B \ + (BIT_MASK_NOA_UNIT2_SEL_8822B << BIT_SHIFT_NOA_UNIT2_SEL_8822B) +#define BIT_CLEAR_NOA_UNIT2_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT2_SEL_8822B)) +#define BIT_GET_NOA_UNIT2_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822B) & BIT_MASK_NOA_UNIT2_SEL_8822B) +#define BIT_SET_NOA_UNIT2_SEL_8822B(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL_8822B(x) | BIT_NOA_UNIT2_SEL_8822B(v)) #define BIT_SHIFT_NOA_UNIT1_SEL_8822B 4 #define BIT_MASK_NOA_UNIT1_SEL_8822B 0x7 -#define BIT_NOA_UNIT1_SEL_8822B(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8822B) << BIT_SHIFT_NOA_UNIT1_SEL_8822B) -#define BIT_GET_NOA_UNIT1_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822B) & BIT_MASK_NOA_UNIT1_SEL_8822B) - - +#define BIT_NOA_UNIT1_SEL_8822B(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL_8822B) << BIT_SHIFT_NOA_UNIT1_SEL_8822B) +#define BITS_NOA_UNIT1_SEL_8822B \ + (BIT_MASK_NOA_UNIT1_SEL_8822B << BIT_SHIFT_NOA_UNIT1_SEL_8822B) +#define BIT_CLEAR_NOA_UNIT1_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT1_SEL_8822B)) +#define BIT_GET_NOA_UNIT1_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822B) & BIT_MASK_NOA_UNIT1_SEL_8822B) +#define BIT_SET_NOA_UNIT1_SEL_8822B(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL_8822B(x) | BIT_NOA_UNIT1_SEL_8822B(v)) #define BIT_SHIFT_NOA_UNIT0_SEL_8822B 0 #define BIT_MASK_NOA_UNIT0_SEL_8822B 0x7 -#define BIT_NOA_UNIT0_SEL_8822B(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8822B) << BIT_SHIFT_NOA_UNIT0_SEL_8822B) -#define BIT_GET_NOA_UNIT0_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822B) & BIT_MASK_NOA_UNIT0_SEL_8822B) - - +#define BIT_NOA_UNIT0_SEL_8822B(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL_8822B) << BIT_SHIFT_NOA_UNIT0_SEL_8822B) +#define BITS_NOA_UNIT0_SEL_8822B \ + (BIT_MASK_NOA_UNIT0_SEL_8822B << BIT_SHIFT_NOA_UNIT0_SEL_8822B) +#define BIT_CLEAR_NOA_UNIT0_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT0_SEL_8822B)) +#define BIT_GET_NOA_UNIT0_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822B) & BIT_MASK_NOA_UNIT0_SEL_8822B) +#define BIT_SET_NOA_UNIT0_SEL_8822B(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL_8822B(x) | BIT_NOA_UNIT0_SEL_8822B(v)) /* 2 REG_P2POFF_DIS_TXTIME_8822B */ #define BIT_SHIFT_P2POFF_DIS_TXTIME_8822B 0 #define BIT_MASK_P2POFF_DIS_TXTIME_8822B 0xff -#define BIT_P2POFF_DIS_TXTIME_8822B(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822B) << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) -#define BIT_GET_P2POFF_DIS_TXTIME_8822B(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) & BIT_MASK_P2POFF_DIS_TXTIME_8822B) - - +#define BIT_P2POFF_DIS_TXTIME_8822B(x) \ + (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822B) \ + << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) +#define BITS_P2POFF_DIS_TXTIME_8822B \ + (BIT_MASK_P2POFF_DIS_TXTIME_8822B << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) +#define BIT_CLEAR_P2POFF_DIS_TXTIME_8822B(x) \ + ((x) & (~BITS_P2POFF_DIS_TXTIME_8822B)) +#define BIT_GET_P2POFF_DIS_TXTIME_8822B(x) \ + (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) & \ + BIT_MASK_P2POFF_DIS_TXTIME_8822B) +#define BIT_SET_P2POFF_DIS_TXTIME_8822B(x, v) \ + (BIT_CLEAR_P2POFF_DIS_TXTIME_8822B(x) | BIT_P2POFF_DIS_TXTIME_8822B(v)) /* 2 REG_MBSSID_BCN_SPACE2_8822B */ #define BIT_SHIFT_BCN_SPACE_CLINT2_8822B 16 #define BIT_MASK_BCN_SPACE_CLINT2_8822B 0xfff -#define BIT_BCN_SPACE_CLINT2_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8822B) << BIT_SHIFT_BCN_SPACE_CLINT2_8822B) -#define BIT_GET_BCN_SPACE_CLINT2_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822B) & BIT_MASK_BCN_SPACE_CLINT2_8822B) - - +#define BIT_BCN_SPACE_CLINT2_8822B(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT2_8822B) \ + << BIT_SHIFT_BCN_SPACE_CLINT2_8822B) +#define BITS_BCN_SPACE_CLINT2_8822B \ + (BIT_MASK_BCN_SPACE_CLINT2_8822B << BIT_SHIFT_BCN_SPACE_CLINT2_8822B) +#define BIT_CLEAR_BCN_SPACE_CLINT2_8822B(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT2_8822B)) +#define BIT_GET_BCN_SPACE_CLINT2_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822B) & \ + BIT_MASK_BCN_SPACE_CLINT2_8822B) +#define BIT_SET_BCN_SPACE_CLINT2_8822B(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT2_8822B(x) | BIT_BCN_SPACE_CLINT2_8822B(v)) #define BIT_SHIFT_BCN_SPACE_CLINT1_8822B 0 #define BIT_MASK_BCN_SPACE_CLINT1_8822B 0xfff -#define BIT_BCN_SPACE_CLINT1_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8822B) << BIT_SHIFT_BCN_SPACE_CLINT1_8822B) -#define BIT_GET_BCN_SPACE_CLINT1_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822B) & BIT_MASK_BCN_SPACE_CLINT1_8822B) - - +#define BIT_BCN_SPACE_CLINT1_8822B(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT1_8822B) \ + << BIT_SHIFT_BCN_SPACE_CLINT1_8822B) +#define BITS_BCN_SPACE_CLINT1_8822B \ + (BIT_MASK_BCN_SPACE_CLINT1_8822B << BIT_SHIFT_BCN_SPACE_CLINT1_8822B) +#define BIT_CLEAR_BCN_SPACE_CLINT1_8822B(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT1_8822B)) +#define BIT_GET_BCN_SPACE_CLINT1_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822B) & \ + BIT_MASK_BCN_SPACE_CLINT1_8822B) +#define BIT_SET_BCN_SPACE_CLINT1_8822B(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT1_8822B(x) | BIT_BCN_SPACE_CLINT1_8822B(v)) /* 2 REG_MBSSID_BCN_SPACE3_8822B */ #define BIT_SHIFT_SUB_BCN_SPACE_8822B 16 #define BIT_MASK_SUB_BCN_SPACE_8822B 0xff -#define BIT_SUB_BCN_SPACE_8822B(x) (((x) & BIT_MASK_SUB_BCN_SPACE_8822B) << BIT_SHIFT_SUB_BCN_SPACE_8822B) -#define BIT_GET_SUB_BCN_SPACE_8822B(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822B) & BIT_MASK_SUB_BCN_SPACE_8822B) - - +#define BIT_SUB_BCN_SPACE_8822B(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE_8822B) << BIT_SHIFT_SUB_BCN_SPACE_8822B) +#define BITS_SUB_BCN_SPACE_8822B \ + (BIT_MASK_SUB_BCN_SPACE_8822B << BIT_SHIFT_SUB_BCN_SPACE_8822B) +#define BIT_CLEAR_SUB_BCN_SPACE_8822B(x) ((x) & (~BITS_SUB_BCN_SPACE_8822B)) +#define BIT_GET_SUB_BCN_SPACE_8822B(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822B) & BIT_MASK_SUB_BCN_SPACE_8822B) +#define BIT_SET_SUB_BCN_SPACE_8822B(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE_8822B(x) | BIT_SUB_BCN_SPACE_8822B(v)) #define BIT_SHIFT_BCN_SPACE_CLINT3_8822B 0 #define BIT_MASK_BCN_SPACE_CLINT3_8822B 0xfff -#define BIT_BCN_SPACE_CLINT3_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8822B) << BIT_SHIFT_BCN_SPACE_CLINT3_8822B) -#define BIT_GET_BCN_SPACE_CLINT3_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822B) & BIT_MASK_BCN_SPACE_CLINT3_8822B) - - +#define BIT_BCN_SPACE_CLINT3_8822B(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT3_8822B) \ + << BIT_SHIFT_BCN_SPACE_CLINT3_8822B) +#define BITS_BCN_SPACE_CLINT3_8822B \ + (BIT_MASK_BCN_SPACE_CLINT3_8822B << BIT_SHIFT_BCN_SPACE_CLINT3_8822B) +#define BIT_CLEAR_BCN_SPACE_CLINT3_8822B(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT3_8822B)) +#define BIT_GET_BCN_SPACE_CLINT3_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822B) & \ + BIT_MASK_BCN_SPACE_CLINT3_8822B) +#define BIT_SET_BCN_SPACE_CLINT3_8822B(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT3_8822B(x) | BIT_BCN_SPACE_CLINT3_8822B(v)) /* 2 REG_ACMHWCTRL_8822B */ #define BIT_BEQ_ACM_STATUS_8822B BIT(7) @@ -8054,92 +12794,158 @@ #define BIT_SHIFT_AVGPERIOD_8822B 0 #define BIT_MASK_AVGPERIOD_8822B 0xffff -#define BIT_AVGPERIOD_8822B(x) (((x) & BIT_MASK_AVGPERIOD_8822B) << BIT_SHIFT_AVGPERIOD_8822B) -#define BIT_GET_AVGPERIOD_8822B(x) (((x) >> BIT_SHIFT_AVGPERIOD_8822B) & BIT_MASK_AVGPERIOD_8822B) - - +#define BIT_AVGPERIOD_8822B(x) \ + (((x) & BIT_MASK_AVGPERIOD_8822B) << BIT_SHIFT_AVGPERIOD_8822B) +#define BITS_AVGPERIOD_8822B \ + (BIT_MASK_AVGPERIOD_8822B << BIT_SHIFT_AVGPERIOD_8822B) +#define BIT_CLEAR_AVGPERIOD_8822B(x) ((x) & (~BITS_AVGPERIOD_8822B)) +#define BIT_GET_AVGPERIOD_8822B(x) \ + (((x) >> BIT_SHIFT_AVGPERIOD_8822B) & BIT_MASK_AVGPERIOD_8822B) +#define BIT_SET_AVGPERIOD_8822B(x, v) \ + (BIT_CLEAR_AVGPERIOD_8822B(x) | BIT_AVGPERIOD_8822B(v)) /* 2 REG_VO_ADMTIME_8822B */ #define BIT_SHIFT_VO_ADMITTED_TIME_8822B 0 #define BIT_MASK_VO_ADMITTED_TIME_8822B 0xffff -#define BIT_VO_ADMITTED_TIME_8822B(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8822B) << BIT_SHIFT_VO_ADMITTED_TIME_8822B) -#define BIT_GET_VO_ADMITTED_TIME_8822B(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822B) & BIT_MASK_VO_ADMITTED_TIME_8822B) - - +#define BIT_VO_ADMITTED_TIME_8822B(x) \ + (((x) & BIT_MASK_VO_ADMITTED_TIME_8822B) \ + << BIT_SHIFT_VO_ADMITTED_TIME_8822B) +#define BITS_VO_ADMITTED_TIME_8822B \ + (BIT_MASK_VO_ADMITTED_TIME_8822B << BIT_SHIFT_VO_ADMITTED_TIME_8822B) +#define BIT_CLEAR_VO_ADMITTED_TIME_8822B(x) \ + ((x) & (~BITS_VO_ADMITTED_TIME_8822B)) +#define BIT_GET_VO_ADMITTED_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822B) & \ + BIT_MASK_VO_ADMITTED_TIME_8822B) +#define BIT_SET_VO_ADMITTED_TIME_8822B(x, v) \ + (BIT_CLEAR_VO_ADMITTED_TIME_8822B(x) | BIT_VO_ADMITTED_TIME_8822B(v)) /* 2 REG_VI_ADMTIME_8822B */ #define BIT_SHIFT_VI_ADMITTED_TIME_8822B 0 #define BIT_MASK_VI_ADMITTED_TIME_8822B 0xffff -#define BIT_VI_ADMITTED_TIME_8822B(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8822B) << BIT_SHIFT_VI_ADMITTED_TIME_8822B) -#define BIT_GET_VI_ADMITTED_TIME_8822B(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822B) & BIT_MASK_VI_ADMITTED_TIME_8822B) - - +#define BIT_VI_ADMITTED_TIME_8822B(x) \ + (((x) & BIT_MASK_VI_ADMITTED_TIME_8822B) \ + << BIT_SHIFT_VI_ADMITTED_TIME_8822B) +#define BITS_VI_ADMITTED_TIME_8822B \ + (BIT_MASK_VI_ADMITTED_TIME_8822B << BIT_SHIFT_VI_ADMITTED_TIME_8822B) +#define BIT_CLEAR_VI_ADMITTED_TIME_8822B(x) \ + ((x) & (~BITS_VI_ADMITTED_TIME_8822B)) +#define BIT_GET_VI_ADMITTED_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822B) & \ + BIT_MASK_VI_ADMITTED_TIME_8822B) +#define BIT_SET_VI_ADMITTED_TIME_8822B(x, v) \ + (BIT_CLEAR_VI_ADMITTED_TIME_8822B(x) | BIT_VI_ADMITTED_TIME_8822B(v)) /* 2 REG_BE_ADMTIME_8822B */ #define BIT_SHIFT_BE_ADMITTED_TIME_8822B 0 #define BIT_MASK_BE_ADMITTED_TIME_8822B 0xffff -#define BIT_BE_ADMITTED_TIME_8822B(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8822B) << BIT_SHIFT_BE_ADMITTED_TIME_8822B) -#define BIT_GET_BE_ADMITTED_TIME_8822B(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822B) & BIT_MASK_BE_ADMITTED_TIME_8822B) - - +#define BIT_BE_ADMITTED_TIME_8822B(x) \ + (((x) & BIT_MASK_BE_ADMITTED_TIME_8822B) \ + << BIT_SHIFT_BE_ADMITTED_TIME_8822B) +#define BITS_BE_ADMITTED_TIME_8822B \ + (BIT_MASK_BE_ADMITTED_TIME_8822B << BIT_SHIFT_BE_ADMITTED_TIME_8822B) +#define BIT_CLEAR_BE_ADMITTED_TIME_8822B(x) \ + ((x) & (~BITS_BE_ADMITTED_TIME_8822B)) +#define BIT_GET_BE_ADMITTED_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822B) & \ + BIT_MASK_BE_ADMITTED_TIME_8822B) +#define BIT_SET_BE_ADMITTED_TIME_8822B(x, v) \ + (BIT_CLEAR_BE_ADMITTED_TIME_8822B(x) | BIT_BE_ADMITTED_TIME_8822B(v)) /* 2 REG_EDCA_RANDOM_GEN_8822B */ #define BIT_SHIFT_RANDOM_GEN_8822B 0 #define BIT_MASK_RANDOM_GEN_8822B 0xffffff -#define BIT_RANDOM_GEN_8822B(x) (((x) & BIT_MASK_RANDOM_GEN_8822B) << BIT_SHIFT_RANDOM_GEN_8822B) -#define BIT_GET_RANDOM_GEN_8822B(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8822B) & BIT_MASK_RANDOM_GEN_8822B) - - +#define BIT_RANDOM_GEN_8822B(x) \ + (((x) & BIT_MASK_RANDOM_GEN_8822B) << BIT_SHIFT_RANDOM_GEN_8822B) +#define BITS_RANDOM_GEN_8822B \ + (BIT_MASK_RANDOM_GEN_8822B << BIT_SHIFT_RANDOM_GEN_8822B) +#define BIT_CLEAR_RANDOM_GEN_8822B(x) ((x) & (~BITS_RANDOM_GEN_8822B)) +#define BIT_GET_RANDOM_GEN_8822B(x) \ + (((x) >> BIT_SHIFT_RANDOM_GEN_8822B) & BIT_MASK_RANDOM_GEN_8822B) +#define BIT_SET_RANDOM_GEN_8822B(x, v) \ + (BIT_CLEAR_RANDOM_GEN_8822B(x) | BIT_RANDOM_GEN_8822B(v)) /* 2 REG_TXCMD_NOA_SEL_8822B */ -#define BIT_SHIFT_NOA_SEL_8822B 4 -#define BIT_MASK_NOA_SEL_8822B 0x7 -#define BIT_NOA_SEL_8822B(x) (((x) & BIT_MASK_NOA_SEL_8822B) << BIT_SHIFT_NOA_SEL_8822B) -#define BIT_GET_NOA_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_SEL_8822B) & BIT_MASK_NOA_SEL_8822B) - - +#define BIT_SHIFT_NOA_SEL_V2_8822B 4 +#define BIT_MASK_NOA_SEL_V2_8822B 0x7 +#define BIT_NOA_SEL_V2_8822B(x) \ + (((x) & BIT_MASK_NOA_SEL_V2_8822B) << BIT_SHIFT_NOA_SEL_V2_8822B) +#define BITS_NOA_SEL_V2_8822B \ + (BIT_MASK_NOA_SEL_V2_8822B << BIT_SHIFT_NOA_SEL_V2_8822B) +#define BIT_CLEAR_NOA_SEL_V2_8822B(x) ((x) & (~BITS_NOA_SEL_V2_8822B)) +#define BIT_GET_NOA_SEL_V2_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V2_8822B) & BIT_MASK_NOA_SEL_V2_8822B) +#define BIT_SET_NOA_SEL_V2_8822B(x, v) \ + (BIT_CLEAR_NOA_SEL_V2_8822B(x) | BIT_NOA_SEL_V2_8822B(v)) #define BIT_SHIFT_TXCMD_SEG_SEL_8822B 0 #define BIT_MASK_TXCMD_SEG_SEL_8822B 0xf -#define BIT_TXCMD_SEG_SEL_8822B(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8822B) << BIT_SHIFT_TXCMD_SEG_SEL_8822B) -#define BIT_GET_TXCMD_SEG_SEL_8822B(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822B) & BIT_MASK_TXCMD_SEG_SEL_8822B) - - +#define BIT_TXCMD_SEG_SEL_8822B(x) \ + (((x) & BIT_MASK_TXCMD_SEG_SEL_8822B) << BIT_SHIFT_TXCMD_SEG_SEL_8822B) +#define BITS_TXCMD_SEG_SEL_8822B \ + (BIT_MASK_TXCMD_SEG_SEL_8822B << BIT_SHIFT_TXCMD_SEG_SEL_8822B) +#define BIT_CLEAR_TXCMD_SEG_SEL_8822B(x) ((x) & (~BITS_TXCMD_SEG_SEL_8822B)) +#define BIT_GET_TXCMD_SEG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822B) & BIT_MASK_TXCMD_SEG_SEL_8822B) +#define BIT_SET_TXCMD_SEG_SEL_8822B(x, v) \ + (BIT_CLEAR_TXCMD_SEG_SEL_8822B(x) | BIT_TXCMD_SEG_SEL_8822B(v)) /* 2 REG_NOA_PARAM_8822B */ #define BIT_SHIFT_NOA_COUNT_8822B (96 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_COUNT_8822B 0xff -#define BIT_NOA_COUNT_8822B(x) (((x) & BIT_MASK_NOA_COUNT_8822B) << BIT_SHIFT_NOA_COUNT_8822B) -#define BIT_GET_NOA_COUNT_8822B(x) (((x) >> BIT_SHIFT_NOA_COUNT_8822B) & BIT_MASK_NOA_COUNT_8822B) - - +#define BIT_NOA_COUNT_8822B(x) \ + (((x) & BIT_MASK_NOA_COUNT_8822B) << BIT_SHIFT_NOA_COUNT_8822B) +#define BITS_NOA_COUNT_8822B \ + (BIT_MASK_NOA_COUNT_8822B << BIT_SHIFT_NOA_COUNT_8822B) +#define BIT_CLEAR_NOA_COUNT_8822B(x) ((x) & (~BITS_NOA_COUNT_8822B)) +#define BIT_GET_NOA_COUNT_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_8822B) & BIT_MASK_NOA_COUNT_8822B) +#define BIT_SET_NOA_COUNT_8822B(x, v) \ + (BIT_CLEAR_NOA_COUNT_8822B(x) | BIT_NOA_COUNT_8822B(v)) #define BIT_SHIFT_NOA_START_TIME_8822B (64 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_START_TIME_8822B 0xffffffffL -#define BIT_NOA_START_TIME_8822B(x) (((x) & BIT_MASK_NOA_START_TIME_8822B) << BIT_SHIFT_NOA_START_TIME_8822B) -#define BIT_GET_NOA_START_TIME_8822B(x) (((x) >> BIT_SHIFT_NOA_START_TIME_8822B) & BIT_MASK_NOA_START_TIME_8822B) - - +#define BIT_NOA_START_TIME_8822B(x) \ + (((x) & BIT_MASK_NOA_START_TIME_8822B) \ + << BIT_SHIFT_NOA_START_TIME_8822B) +#define BITS_NOA_START_TIME_8822B \ + (BIT_MASK_NOA_START_TIME_8822B << BIT_SHIFT_NOA_START_TIME_8822B) +#define BIT_CLEAR_NOA_START_TIME_8822B(x) ((x) & (~BITS_NOA_START_TIME_8822B)) +#define BIT_GET_NOA_START_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_START_TIME_8822B) & \ + BIT_MASK_NOA_START_TIME_8822B) +#define BIT_SET_NOA_START_TIME_8822B(x, v) \ + (BIT_CLEAR_NOA_START_TIME_8822B(x) | BIT_NOA_START_TIME_8822B(v)) #define BIT_SHIFT_NOA_INTERVAL_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_INTERVAL_8822B 0xffffffffL -#define BIT_NOA_INTERVAL_8822B(x) (((x) & BIT_MASK_NOA_INTERVAL_8822B) << BIT_SHIFT_NOA_INTERVAL_8822B) -#define BIT_GET_NOA_INTERVAL_8822B(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_8822B) & BIT_MASK_NOA_INTERVAL_8822B) - - +#define BIT_NOA_INTERVAL_8822B(x) \ + (((x) & BIT_MASK_NOA_INTERVAL_8822B) << BIT_SHIFT_NOA_INTERVAL_8822B) +#define BITS_NOA_INTERVAL_8822B \ + (BIT_MASK_NOA_INTERVAL_8822B << BIT_SHIFT_NOA_INTERVAL_8822B) +#define BIT_CLEAR_NOA_INTERVAL_8822B(x) ((x) & (~BITS_NOA_INTERVAL_8822B)) +#define BIT_GET_NOA_INTERVAL_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_INTERVAL_8822B) & BIT_MASK_NOA_INTERVAL_8822B) +#define BIT_SET_NOA_INTERVAL_8822B(x, v) \ + (BIT_CLEAR_NOA_INTERVAL_8822B(x) | BIT_NOA_INTERVAL_8822B(v)) #define BIT_SHIFT_NOA_DURATION_8822B 0 #define BIT_MASK_NOA_DURATION_8822B 0xffffffffL -#define BIT_NOA_DURATION_8822B(x) (((x) & BIT_MASK_NOA_DURATION_8822B) << BIT_SHIFT_NOA_DURATION_8822B) -#define BIT_GET_NOA_DURATION_8822B(x) (((x) >> BIT_SHIFT_NOA_DURATION_8822B) & BIT_MASK_NOA_DURATION_8822B) - - +#define BIT_NOA_DURATION_8822B(x) \ + (((x) & BIT_MASK_NOA_DURATION_8822B) << BIT_SHIFT_NOA_DURATION_8822B) +#define BITS_NOA_DURATION_8822B \ + (BIT_MASK_NOA_DURATION_8822B << BIT_SHIFT_NOA_DURATION_8822B) +#define BIT_CLEAR_NOA_DURATION_8822B(x) ((x) & (~BITS_NOA_DURATION_8822B)) +#define BIT_GET_NOA_DURATION_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION_8822B) & BIT_MASK_NOA_DURATION_8822B) +#define BIT_SET_NOA_DURATION_8822B(x, v) \ + (BIT_CLEAR_NOA_DURATION_8822B(x) | BIT_NOA_DURATION_8822B(v)) /* 2 REG_P2P_RST_8822B */ #define BIT_P2P2_PWR_RST1_8822B BIT(5) @@ -8150,17 +12956,23 @@ #define BIT_P2P_PWR_RST0_V1_8822B BIT(0) /* 2 REG_SCHEDULER_RST_8822B */ -#define BIT_SYNC_CLI_8822B BIT(1) +#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8822B BIT(2) +#define BIT_SYNC_CLI_ONCE_BY_TBTT_8822B BIT(1) #define BIT_SCHEDULER_RST_V1_8822B BIT(0) /* 2 REG_SCH_TXCMD_8822B */ #define BIT_SHIFT_SCH_TXCMD_8822B 0 #define BIT_MASK_SCH_TXCMD_8822B 0xffffffffL -#define BIT_SCH_TXCMD_8822B(x) (((x) & BIT_MASK_SCH_TXCMD_8822B) << BIT_SHIFT_SCH_TXCMD_8822B) -#define BIT_GET_SCH_TXCMD_8822B(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8822B) & BIT_MASK_SCH_TXCMD_8822B) - - +#define BIT_SCH_TXCMD_8822B(x) \ + (((x) & BIT_MASK_SCH_TXCMD_8822B) << BIT_SHIFT_SCH_TXCMD_8822B) +#define BITS_SCH_TXCMD_8822B \ + (BIT_MASK_SCH_TXCMD_8822B << BIT_SHIFT_SCH_TXCMD_8822B) +#define BIT_CLEAR_SCH_TXCMD_8822B(x) ((x) & (~BITS_SCH_TXCMD_8822B)) +#define BIT_GET_SCH_TXCMD_8822B(x) \ + (((x) >> BIT_SHIFT_SCH_TXCMD_8822B) & BIT_MASK_SCH_TXCMD_8822B) +#define BIT_SET_SCH_TXCMD_8822B(x, v) \ + (BIT_CLEAR_SCH_TXCMD_8822B(x) | BIT_SCH_TXCMD_8822B(v)) /* 2 REG_PAGE5_DUMMY_8822B */ @@ -8168,37 +12980,62 @@ #define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B 0 #define BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B 0xffffffffL -#define BIT_CPUMGQ_TX_TIMER_V1_8822B(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) -#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B) - - +#define BIT_CPUMGQ_TX_TIMER_V1_8822B(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) +#define BITS_CPUMGQ_TX_TIMER_V1_8822B \ + (BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822B(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8822B)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) & \ + BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B) +#define BIT_SET_CPUMGQ_TX_TIMER_V1_8822B(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822B(x) | \ + BIT_CPUMGQ_TX_TIMER_V1_8822B(v)) /* 2 REG_PS_TIMER_A_8822B */ #define BIT_SHIFT_PS_TIMER_A_V1_8822B 0 #define BIT_MASK_PS_TIMER_A_V1_8822B 0xffffffffL -#define BIT_PS_TIMER_A_V1_8822B(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8822B) << BIT_SHIFT_PS_TIMER_A_V1_8822B) -#define BIT_GET_PS_TIMER_A_V1_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822B) & BIT_MASK_PS_TIMER_A_V1_8822B) - - +#define BIT_PS_TIMER_A_V1_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_A_V1_8822B) << BIT_SHIFT_PS_TIMER_A_V1_8822B) +#define BITS_PS_TIMER_A_V1_8822B \ + (BIT_MASK_PS_TIMER_A_V1_8822B << BIT_SHIFT_PS_TIMER_A_V1_8822B) +#define BIT_CLEAR_PS_TIMER_A_V1_8822B(x) ((x) & (~BITS_PS_TIMER_A_V1_8822B)) +#define BIT_GET_PS_TIMER_A_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822B) & BIT_MASK_PS_TIMER_A_V1_8822B) +#define BIT_SET_PS_TIMER_A_V1_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_A_V1_8822B(x) | BIT_PS_TIMER_A_V1_8822B(v)) /* 2 REG_PS_TIMER_B_8822B */ #define BIT_SHIFT_PS_TIMER_B_V1_8822B 0 #define BIT_MASK_PS_TIMER_B_V1_8822B 0xffffffffL -#define BIT_PS_TIMER_B_V1_8822B(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8822B) << BIT_SHIFT_PS_TIMER_B_V1_8822B) -#define BIT_GET_PS_TIMER_B_V1_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822B) & BIT_MASK_PS_TIMER_B_V1_8822B) - - +#define BIT_PS_TIMER_B_V1_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_B_V1_8822B) << BIT_SHIFT_PS_TIMER_B_V1_8822B) +#define BITS_PS_TIMER_B_V1_8822B \ + (BIT_MASK_PS_TIMER_B_V1_8822B << BIT_SHIFT_PS_TIMER_B_V1_8822B) +#define BIT_CLEAR_PS_TIMER_B_V1_8822B(x) ((x) & (~BITS_PS_TIMER_B_V1_8822B)) +#define BIT_GET_PS_TIMER_B_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822B) & BIT_MASK_PS_TIMER_B_V1_8822B) +#define BIT_SET_PS_TIMER_B_V1_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_B_V1_8822B(x) | BIT_PS_TIMER_B_V1_8822B(v)) /* 2 REG_PS_TIMER_C_8822B */ #define BIT_SHIFT_PS_TIMER_C_V1_8822B 0 #define BIT_MASK_PS_TIMER_C_V1_8822B 0xffffffffL -#define BIT_PS_TIMER_C_V1_8822B(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8822B) << BIT_SHIFT_PS_TIMER_C_V1_8822B) -#define BIT_GET_PS_TIMER_C_V1_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822B) & BIT_MASK_PS_TIMER_C_V1_8822B) - - +#define BIT_PS_TIMER_C_V1_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_C_V1_8822B) << BIT_SHIFT_PS_TIMER_C_V1_8822B) +#define BITS_PS_TIMER_C_V1_8822B \ + (BIT_MASK_PS_TIMER_C_V1_8822B << BIT_SHIFT_PS_TIMER_C_V1_8822B) +#define BIT_CLEAR_PS_TIMER_C_V1_8822B(x) ((x) & (~BITS_PS_TIMER_C_V1_8822B)) +#define BIT_GET_PS_TIMER_C_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822B) & BIT_MASK_PS_TIMER_C_V1_8822B) +#define BIT_SET_PS_TIMER_C_V1_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_C_V1_8822B(x) | BIT_PS_TIMER_C_V1_8822B(v)) /* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B */ #define BIT_CPUMGQ_TIMER_EN_8822B BIT(31) @@ -8206,70 +13043,169 @@ #define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B 24 #define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B 0x7 -#define BIT_CPUMGQ_TIMER_TSF_SEL_8822B(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) -#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) - +#define BIT_CPUMGQ_TIMER_TSF_SEL_8822B(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) +#define BITS_CPUMGQ_TIMER_TSF_SEL_8822B \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822B(x) \ + ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8822B)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8822B(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822B(x) | \ + BIT_CPUMGQ_TIMER_TSF_SEL_8822B(v)) #define BIT_PS_TIMER_C_EN_8822B BIT(23) #define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B 16 #define BIT_MASK_PS_TIMER_C_TSF_SEL_8822B 0x7 -#define BIT_PS_TIMER_C_TSF_SEL_8822B(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) -#define BIT_GET_PS_TIMER_C_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) - +#define BIT_PS_TIMER_C_TSF_SEL_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) +#define BITS_PS_TIMER_C_TSF_SEL_8822B \ + (BIT_MASK_PS_TIMER_C_TSF_SEL_8822B \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) +#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822B(x) \ + ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8822B)) +#define BIT_GET_PS_TIMER_C_TSF_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) & \ + BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) +#define BIT_SET_PS_TIMER_C_TSF_SEL_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822B(x) | \ + BIT_PS_TIMER_C_TSF_SEL_8822B(v)) #define BIT_PS_TIMER_B_EN_8822B BIT(15) #define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B 8 #define BIT_MASK_PS_TIMER_B_TSF_SEL_8822B 0x7 -#define BIT_PS_TIMER_B_TSF_SEL_8822B(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) -#define BIT_GET_PS_TIMER_B_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) - +#define BIT_PS_TIMER_B_TSF_SEL_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) +#define BITS_PS_TIMER_B_TSF_SEL_8822B \ + (BIT_MASK_PS_TIMER_B_TSF_SEL_8822B \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) +#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822B(x) \ + ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8822B)) +#define BIT_GET_PS_TIMER_B_TSF_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) & \ + BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) +#define BIT_SET_PS_TIMER_B_TSF_SEL_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822B(x) | \ + BIT_PS_TIMER_B_TSF_SEL_8822B(v)) #define BIT_PS_TIMER_A_EN_8822B BIT(7) #define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B 0 #define BIT_MASK_PS_TIMER_A_TSF_SEL_8822B 0x7 -#define BIT_PS_TIMER_A_TSF_SEL_8822B(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) -#define BIT_GET_PS_TIMER_A_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B) - - +#define BIT_PS_TIMER_A_TSF_SEL_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B) \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) +#define BITS_PS_TIMER_A_TSF_SEL_8822B \ + (BIT_MASK_PS_TIMER_A_TSF_SEL_8822B \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) +#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822B(x) \ + ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8822B)) +#define BIT_GET_PS_TIMER_A_TSF_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) & \ + BIT_MASK_PS_TIMER_A_TSF_SEL_8822B) +#define BIT_SET_PS_TIMER_A_TSF_SEL_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822B(x) | \ + BIT_PS_TIMER_A_TSF_SEL_8822B(v)) /* 2 REG_CPUMGQ_TX_TIMER_EARLY_8822B */ #define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B 0 #define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B 0xff -#define BIT_CPUMGQ_TX_TIMER_EARLY_8822B(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) -#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B) - - +#define BIT_CPUMGQ_TX_TIMER_EARLY_8822B(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) +#define BITS_CPUMGQ_TX_TIMER_EARLY_8822B \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822B(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8822B)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8822B(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822B(x) | \ + BIT_CPUMGQ_TX_TIMER_EARLY_8822B(v)) /* 2 REG_PS_TIMER_A_EARLY_8822B */ #define BIT_SHIFT_PS_TIMER_A_EARLY_8822B 0 #define BIT_MASK_PS_TIMER_A_EARLY_8822B 0xff -#define BIT_PS_TIMER_A_EARLY_8822B(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8822B) << BIT_SHIFT_PS_TIMER_A_EARLY_8822B) -#define BIT_GET_PS_TIMER_A_EARLY_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822B) & BIT_MASK_PS_TIMER_A_EARLY_8822B) - - +#define BIT_PS_TIMER_A_EARLY_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_A_EARLY_8822B) \ + << BIT_SHIFT_PS_TIMER_A_EARLY_8822B) +#define BITS_PS_TIMER_A_EARLY_8822B \ + (BIT_MASK_PS_TIMER_A_EARLY_8822B << BIT_SHIFT_PS_TIMER_A_EARLY_8822B) +#define BIT_CLEAR_PS_TIMER_A_EARLY_8822B(x) \ + ((x) & (~BITS_PS_TIMER_A_EARLY_8822B)) +#define BIT_GET_PS_TIMER_A_EARLY_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822B) & \ + BIT_MASK_PS_TIMER_A_EARLY_8822B) +#define BIT_SET_PS_TIMER_A_EARLY_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_A_EARLY_8822B(x) | BIT_PS_TIMER_A_EARLY_8822B(v)) /* 2 REG_PS_TIMER_B_EARLY_8822B */ #define BIT_SHIFT_PS_TIMER_B_EARLY_8822B 0 #define BIT_MASK_PS_TIMER_B_EARLY_8822B 0xff -#define BIT_PS_TIMER_B_EARLY_8822B(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8822B) << BIT_SHIFT_PS_TIMER_B_EARLY_8822B) -#define BIT_GET_PS_TIMER_B_EARLY_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822B) & BIT_MASK_PS_TIMER_B_EARLY_8822B) - - +#define BIT_PS_TIMER_B_EARLY_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_B_EARLY_8822B) \ + << BIT_SHIFT_PS_TIMER_B_EARLY_8822B) +#define BITS_PS_TIMER_B_EARLY_8822B \ + (BIT_MASK_PS_TIMER_B_EARLY_8822B << BIT_SHIFT_PS_TIMER_B_EARLY_8822B) +#define BIT_CLEAR_PS_TIMER_B_EARLY_8822B(x) \ + ((x) & (~BITS_PS_TIMER_B_EARLY_8822B)) +#define BIT_GET_PS_TIMER_B_EARLY_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822B) & \ + BIT_MASK_PS_TIMER_B_EARLY_8822B) +#define BIT_SET_PS_TIMER_B_EARLY_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_B_EARLY_8822B(x) | BIT_PS_TIMER_B_EARLY_8822B(v)) /* 2 REG_PS_TIMER_C_EARLY_8822B */ #define BIT_SHIFT_PS_TIMER_C_EARLY_8822B 0 #define BIT_MASK_PS_TIMER_C_EARLY_8822B 0xff -#define BIT_PS_TIMER_C_EARLY_8822B(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8822B) << BIT_SHIFT_PS_TIMER_C_EARLY_8822B) -#define BIT_GET_PS_TIMER_C_EARLY_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822B) & BIT_MASK_PS_TIMER_C_EARLY_8822B) +#define BIT_PS_TIMER_C_EARLY_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_C_EARLY_8822B) \ + << BIT_SHIFT_PS_TIMER_C_EARLY_8822B) +#define BITS_PS_TIMER_C_EARLY_8822B \ + (BIT_MASK_PS_TIMER_C_EARLY_8822B << BIT_SHIFT_PS_TIMER_C_EARLY_8822B) +#define BIT_CLEAR_PS_TIMER_C_EARLY_8822B(x) \ + ((x) & (~BITS_PS_TIMER_C_EARLY_8822B)) +#define BIT_GET_PS_TIMER_C_EARLY_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822B) & \ + BIT_MASK_PS_TIMER_C_EARLY_8822B) +#define BIT_SET_PS_TIMER_C_EARLY_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_C_EARLY_8822B(x) | BIT_PS_TIMER_C_EARLY_8822B(v)) + +/* 2 REG_CPUMGQ_PARAMETER_8822B */ +/* 2 REG_NOT_VALID_8822B */ +#define BIT_MAC_STOP_CPUMGQ_8822B BIT(16) + +#define BIT_SHIFT_CW_8822B 8 +#define BIT_MASK_CW_8822B 0xff +#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) +#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B) +#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B)) +#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) +#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v)) +#define BIT_SHIFT_AIFS_8822B 0 +#define BIT_MASK_AIFS_8822B 0xff +#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) +#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B) +#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B)) +#define BIT_GET_AIFS_8822B(x) \ + (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) +#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -8283,10 +13219,17 @@ #define BIT_SHIFT_APPEND_MHDR_LEN_8822B 0 #define BIT_MASK_APPEND_MHDR_LEN_8822B 0x7 -#define BIT_APPEND_MHDR_LEN_8822B(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8822B) << BIT_SHIFT_APPEND_MHDR_LEN_8822B) -#define BIT_GET_APPEND_MHDR_LEN_8822B(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822B) & BIT_MASK_APPEND_MHDR_LEN_8822B) - - +#define BIT_APPEND_MHDR_LEN_8822B(x) \ + (((x) & BIT_MASK_APPEND_MHDR_LEN_8822B) \ + << BIT_SHIFT_APPEND_MHDR_LEN_8822B) +#define BITS_APPEND_MHDR_LEN_8822B \ + (BIT_MASK_APPEND_MHDR_LEN_8822B << BIT_SHIFT_APPEND_MHDR_LEN_8822B) +#define BIT_CLEAR_APPEND_MHDR_LEN_8822B(x) ((x) & (~BITS_APPEND_MHDR_LEN_8822B)) +#define BIT_GET_APPEND_MHDR_LEN_8822B(x) \ + (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822B) & \ + BIT_MASK_APPEND_MHDR_LEN_8822B) +#define BIT_SET_APPEND_MHDR_LEN_8822B(x, v) \ + (BIT_CLEAR_APPEND_MHDR_LEN_8822B(x) | BIT_APPEND_MHDR_LEN_8822B(v)) /* 2 REG_WMAC_CR_8822B (WMAC CR AND APSD CONTROL REGISTER) */ #define BIT_IC_MACPHY_M_8822B BIT(0) @@ -8359,64 +13302,96 @@ #define BIT_SHIFT_DRVINFO_SZ_V1_8822B 0 #define BIT_MASK_DRVINFO_SZ_V1_8822B 0xf -#define BIT_DRVINFO_SZ_V1_8822B(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8822B) << BIT_SHIFT_DRVINFO_SZ_V1_8822B) -#define BIT_GET_DRVINFO_SZ_V1_8822B(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822B) & BIT_MASK_DRVINFO_SZ_V1_8822B) - - +#define BIT_DRVINFO_SZ_V1_8822B(x) \ + (((x) & BIT_MASK_DRVINFO_SZ_V1_8822B) << BIT_SHIFT_DRVINFO_SZ_V1_8822B) +#define BITS_DRVINFO_SZ_V1_8822B \ + (BIT_MASK_DRVINFO_SZ_V1_8822B << BIT_SHIFT_DRVINFO_SZ_V1_8822B) +#define BIT_CLEAR_DRVINFO_SZ_V1_8822B(x) ((x) & (~BITS_DRVINFO_SZ_V1_8822B)) +#define BIT_GET_DRVINFO_SZ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822B) & BIT_MASK_DRVINFO_SZ_V1_8822B) +#define BIT_SET_DRVINFO_SZ_V1_8822B(x, v) \ + (BIT_CLEAR_DRVINFO_SZ_V1_8822B(x) | BIT_DRVINFO_SZ_V1_8822B(v)) /* 2 REG_RX_DLK_TIME_8822B (RX DEADLOCK TIME REGISTER) */ #define BIT_SHIFT_RX_DLK_TIME_8822B 0 #define BIT_MASK_RX_DLK_TIME_8822B 0xff -#define BIT_RX_DLK_TIME_8822B(x) (((x) & BIT_MASK_RX_DLK_TIME_8822B) << BIT_SHIFT_RX_DLK_TIME_8822B) -#define BIT_GET_RX_DLK_TIME_8822B(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8822B) & BIT_MASK_RX_DLK_TIME_8822B) - - +#define BIT_RX_DLK_TIME_8822B(x) \ + (((x) & BIT_MASK_RX_DLK_TIME_8822B) << BIT_SHIFT_RX_DLK_TIME_8822B) +#define BITS_RX_DLK_TIME_8822B \ + (BIT_MASK_RX_DLK_TIME_8822B << BIT_SHIFT_RX_DLK_TIME_8822B) +#define BIT_CLEAR_RX_DLK_TIME_8822B(x) ((x) & (~BITS_RX_DLK_TIME_8822B)) +#define BIT_GET_RX_DLK_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_RX_DLK_TIME_8822B) & BIT_MASK_RX_DLK_TIME_8822B) +#define BIT_SET_RX_DLK_TIME_8822B(x, v) \ + (BIT_CLEAR_RX_DLK_TIME_8822B(x) | BIT_RX_DLK_TIME_8822B(v)) /* 2 REG_RX_PKT_LIMIT_8822B (RX PACKET LENGTH LIMIT REGISTER) */ #define BIT_SHIFT_RXPKTLMT_8822B 0 #define BIT_MASK_RXPKTLMT_8822B 0x3f -#define BIT_RXPKTLMT_8822B(x) (((x) & BIT_MASK_RXPKTLMT_8822B) << BIT_SHIFT_RXPKTLMT_8822B) -#define BIT_GET_RXPKTLMT_8822B(x) (((x) >> BIT_SHIFT_RXPKTLMT_8822B) & BIT_MASK_RXPKTLMT_8822B) - - +#define BIT_RXPKTLMT_8822B(x) \ + (((x) & BIT_MASK_RXPKTLMT_8822B) << BIT_SHIFT_RXPKTLMT_8822B) +#define BITS_RXPKTLMT_8822B \ + (BIT_MASK_RXPKTLMT_8822B << BIT_SHIFT_RXPKTLMT_8822B) +#define BIT_CLEAR_RXPKTLMT_8822B(x) ((x) & (~BITS_RXPKTLMT_8822B)) +#define BIT_GET_RXPKTLMT_8822B(x) \ + (((x) >> BIT_SHIFT_RXPKTLMT_8822B) & BIT_MASK_RXPKTLMT_8822B) +#define BIT_SET_RXPKTLMT_8822B(x, v) \ + (BIT_CLEAR_RXPKTLMT_8822B(x) | BIT_RXPKTLMT_8822B(v)) /* 2 REG_MACID_8822B (MAC ID REGISTER) */ #define BIT_SHIFT_MACID_8822B 0 #define BIT_MASK_MACID_8822B 0xffffffffffffL -#define BIT_MACID_8822B(x) (((x) & BIT_MASK_MACID_8822B) << BIT_SHIFT_MACID_8822B) -#define BIT_GET_MACID_8822B(x) (((x) >> BIT_SHIFT_MACID_8822B) & BIT_MASK_MACID_8822B) - - +#define BIT_MACID_8822B(x) \ + (((x) & BIT_MASK_MACID_8822B) << BIT_SHIFT_MACID_8822B) +#define BITS_MACID_8822B (BIT_MASK_MACID_8822B << BIT_SHIFT_MACID_8822B) +#define BIT_CLEAR_MACID_8822B(x) ((x) & (~BITS_MACID_8822B)) +#define BIT_GET_MACID_8822B(x) \ + (((x) >> BIT_SHIFT_MACID_8822B) & BIT_MASK_MACID_8822B) +#define BIT_SET_MACID_8822B(x, v) \ + (BIT_CLEAR_MACID_8822B(x) | BIT_MACID_8822B(v)) /* 2 REG_BSSID_8822B (BSSID REGISTER) */ #define BIT_SHIFT_BSSID_8822B 0 #define BIT_MASK_BSSID_8822B 0xffffffffffffL -#define BIT_BSSID_8822B(x) (((x) & BIT_MASK_BSSID_8822B) << BIT_SHIFT_BSSID_8822B) -#define BIT_GET_BSSID_8822B(x) (((x) >> BIT_SHIFT_BSSID_8822B) & BIT_MASK_BSSID_8822B) - - +#define BIT_BSSID_8822B(x) \ + (((x) & BIT_MASK_BSSID_8822B) << BIT_SHIFT_BSSID_8822B) +#define BITS_BSSID_8822B (BIT_MASK_BSSID_8822B << BIT_SHIFT_BSSID_8822B) +#define BIT_CLEAR_BSSID_8822B(x) ((x) & (~BITS_BSSID_8822B)) +#define BIT_GET_BSSID_8822B(x) \ + (((x) >> BIT_SHIFT_BSSID_8822B) & BIT_MASK_BSSID_8822B) +#define BIT_SET_BSSID_8822B(x, v) \ + (BIT_CLEAR_BSSID_8822B(x) | BIT_BSSID_8822B(v)) /* 2 REG_MAR_8822B (MULTICAST ADDRESS REGISTER) */ #define BIT_SHIFT_MAR_8822B 0 #define BIT_MASK_MAR_8822B 0xffffffffffffffffL #define BIT_MAR_8822B(x) (((x) & BIT_MASK_MAR_8822B) << BIT_SHIFT_MAR_8822B) +#define BITS_MAR_8822B (BIT_MASK_MAR_8822B << BIT_SHIFT_MAR_8822B) +#define BIT_CLEAR_MAR_8822B(x) ((x) & (~BITS_MAR_8822B)) #define BIT_GET_MAR_8822B(x) (((x) >> BIT_SHIFT_MAR_8822B) & BIT_MASK_MAR_8822B) - - +#define BIT_SET_MAR_8822B(x, v) (BIT_CLEAR_MAR_8822B(x) | BIT_MAR_8822B(v)) /* 2 REG_MBIDCAMCFG_1_8822B (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_SHIFT_MBIDCAM_RWDATA_L_8822B 0 #define BIT_MASK_MBIDCAM_RWDATA_L_8822B 0xffffffffL -#define BIT_MBIDCAM_RWDATA_L_8822B(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822B) << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) -#define BIT_GET_MBIDCAM_RWDATA_L_8822B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) & BIT_MASK_MBIDCAM_RWDATA_L_8822B) - - +#define BIT_MBIDCAM_RWDATA_L_8822B(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822B) \ + << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) +#define BITS_MBIDCAM_RWDATA_L_8822B \ + (BIT_MASK_MBIDCAM_RWDATA_L_8822B << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) +#define BIT_CLEAR_MBIDCAM_RWDATA_L_8822B(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_L_8822B)) +#define BIT_GET_MBIDCAM_RWDATA_L_8822B(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) & \ + BIT_MASK_MBIDCAM_RWDATA_L_8822B) +#define BIT_SET_MBIDCAM_RWDATA_L_8822B(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_L_8822B(x) | BIT_MBIDCAM_RWDATA_L_8822B(v)) /* 2 REG_MBIDCAMCFG_2_8822B (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_MBIDCAM_POLL_8822B BIT(31) @@ -8424,9 +13399,15 @@ #define BIT_SHIFT_MBIDCAM_ADDR_8822B 24 #define BIT_MASK_MBIDCAM_ADDR_8822B 0x1f -#define BIT_MBIDCAM_ADDR_8822B(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8822B) << BIT_SHIFT_MBIDCAM_ADDR_8822B) -#define BIT_GET_MBIDCAM_ADDR_8822B(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8822B) & BIT_MASK_MBIDCAM_ADDR_8822B) - +#define BIT_MBIDCAM_ADDR_8822B(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR_8822B) << BIT_SHIFT_MBIDCAM_ADDR_8822B) +#define BITS_MBIDCAM_ADDR_8822B \ + (BIT_MASK_MBIDCAM_ADDR_8822B << BIT_SHIFT_MBIDCAM_ADDR_8822B) +#define BIT_CLEAR_MBIDCAM_ADDR_8822B(x) ((x) & (~BITS_MBIDCAM_ADDR_8822B)) +#define BIT_GET_MBIDCAM_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8822B) & BIT_MASK_MBIDCAM_ADDR_8822B) +#define BIT_SET_MBIDCAM_ADDR_8822B(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR_8822B(x) | BIT_MBIDCAM_ADDR_8822B(v)) #define BIT_MBIDCAM_VALID_8822B BIT(23) #define BIT_LSIC_TXOP_EN_8822B BIT(17) @@ -8434,171 +13415,276 @@ #define BIT_SHIFT_MBIDCAM_RWDATA_H_8822B 0 #define BIT_MASK_MBIDCAM_RWDATA_H_8822B 0xffff -#define BIT_MBIDCAM_RWDATA_H_8822B(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822B) << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) -#define BIT_GET_MBIDCAM_RWDATA_H_8822B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) & BIT_MASK_MBIDCAM_RWDATA_H_8822B) - - +#define BIT_MBIDCAM_RWDATA_H_8822B(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822B) \ + << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) +#define BITS_MBIDCAM_RWDATA_H_8822B \ + (BIT_MASK_MBIDCAM_RWDATA_H_8822B << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) +#define BIT_CLEAR_MBIDCAM_RWDATA_H_8822B(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_H_8822B)) +#define BIT_GET_MBIDCAM_RWDATA_H_8822B(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) & \ + BIT_MASK_MBIDCAM_RWDATA_H_8822B) +#define BIT_SET_MBIDCAM_RWDATA_H_8822B(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_H_8822B(x) | BIT_MBIDCAM_RWDATA_H_8822B(v)) /* 2 REG_ZLD_NUM_8822B */ #define BIT_SHIFT_ZLD_NUM_8822B 0 #define BIT_MASK_ZLD_NUM_8822B 0xff -#define BIT_ZLD_NUM_8822B(x) (((x) & BIT_MASK_ZLD_NUM_8822B) << BIT_SHIFT_ZLD_NUM_8822B) -#define BIT_GET_ZLD_NUM_8822B(x) (((x) >> BIT_SHIFT_ZLD_NUM_8822B) & BIT_MASK_ZLD_NUM_8822B) - - +#define BIT_ZLD_NUM_8822B(x) \ + (((x) & BIT_MASK_ZLD_NUM_8822B) << BIT_SHIFT_ZLD_NUM_8822B) +#define BITS_ZLD_NUM_8822B (BIT_MASK_ZLD_NUM_8822B << BIT_SHIFT_ZLD_NUM_8822B) +#define BIT_CLEAR_ZLD_NUM_8822B(x) ((x) & (~BITS_ZLD_NUM_8822B)) +#define BIT_GET_ZLD_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_ZLD_NUM_8822B) & BIT_MASK_ZLD_NUM_8822B) +#define BIT_SET_ZLD_NUM_8822B(x, v) \ + (BIT_CLEAR_ZLD_NUM_8822B(x) | BIT_ZLD_NUM_8822B(v)) /* 2 REG_UDF_THSD_8822B */ #define BIT_SHIFT_UDF_THSD_8822B 0 #define BIT_MASK_UDF_THSD_8822B 0xff -#define BIT_UDF_THSD_8822B(x) (((x) & BIT_MASK_UDF_THSD_8822B) << BIT_SHIFT_UDF_THSD_8822B) -#define BIT_GET_UDF_THSD_8822B(x) (((x) >> BIT_SHIFT_UDF_THSD_8822B) & BIT_MASK_UDF_THSD_8822B) - - +#define BIT_UDF_THSD_8822B(x) \ + (((x) & BIT_MASK_UDF_THSD_8822B) << BIT_SHIFT_UDF_THSD_8822B) +#define BITS_UDF_THSD_8822B \ + (BIT_MASK_UDF_THSD_8822B << BIT_SHIFT_UDF_THSD_8822B) +#define BIT_CLEAR_UDF_THSD_8822B(x) ((x) & (~BITS_UDF_THSD_8822B)) +#define BIT_GET_UDF_THSD_8822B(x) \ + (((x) >> BIT_SHIFT_UDF_THSD_8822B) & BIT_MASK_UDF_THSD_8822B) +#define BIT_SET_UDF_THSD_8822B(x, v) \ + (BIT_CLEAR_UDF_THSD_8822B(x) | BIT_UDF_THSD_8822B(v)) /* 2 REG_WMAC_TCR_TSFT_OFS_8822B */ #define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B 0 #define BIT_MASK_WMAC_TCR_TSFT_OFS_8822B 0xffff -#define BIT_WMAC_TCR_TSFT_OFS_8822B(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) -#define BIT_GET_WMAC_TCR_TSFT_OFS_8822B(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B) - - +#define BIT_WMAC_TCR_TSFT_OFS_8822B(x) \ + (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B) \ + << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) +#define BITS_WMAC_TCR_TSFT_OFS_8822B \ + (BIT_MASK_WMAC_TCR_TSFT_OFS_8822B << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822B(x) \ + ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8822B)) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) & \ + BIT_MASK_WMAC_TCR_TSFT_OFS_8822B) +#define BIT_SET_WMAC_TCR_TSFT_OFS_8822B(x, v) \ + (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822B(x) | BIT_WMAC_TCR_TSFT_OFS_8822B(v)) /* 2 REG_MCU_TEST_2_V1_8822B */ #define BIT_SHIFT_MCU_RSVD_2_V1_8822B 0 #define BIT_MASK_MCU_RSVD_2_V1_8822B 0xffff -#define BIT_MCU_RSVD_2_V1_8822B(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8822B) << BIT_SHIFT_MCU_RSVD_2_V1_8822B) -#define BIT_GET_MCU_RSVD_2_V1_8822B(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8822B) & BIT_MASK_MCU_RSVD_2_V1_8822B) - - +#define BIT_MCU_RSVD_2_V1_8822B(x) \ + (((x) & BIT_MASK_MCU_RSVD_2_V1_8822B) << BIT_SHIFT_MCU_RSVD_2_V1_8822B) +#define BITS_MCU_RSVD_2_V1_8822B \ + (BIT_MASK_MCU_RSVD_2_V1_8822B << BIT_SHIFT_MCU_RSVD_2_V1_8822B) +#define BIT_CLEAR_MCU_RSVD_2_V1_8822B(x) ((x) & (~BITS_MCU_RSVD_2_V1_8822B)) +#define BIT_GET_MCU_RSVD_2_V1_8822B(x) \ + (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8822B) & BIT_MASK_MCU_RSVD_2_V1_8822B) +#define BIT_SET_MCU_RSVD_2_V1_8822B(x, v) \ + (BIT_CLEAR_MCU_RSVD_2_V1_8822B(x) | BIT_MCU_RSVD_2_V1_8822B(v)) /* 2 REG_WMAC_TXTIMEOUT_8822B */ #define BIT_SHIFT_WMAC_TXTIMEOUT_8822B 0 #define BIT_MASK_WMAC_TXTIMEOUT_8822B 0xff -#define BIT_WMAC_TXTIMEOUT_8822B(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8822B) << BIT_SHIFT_WMAC_TXTIMEOUT_8822B) -#define BIT_GET_WMAC_TXTIMEOUT_8822B(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822B) & BIT_MASK_WMAC_TXTIMEOUT_8822B) - - +#define BIT_WMAC_TXTIMEOUT_8822B(x) \ + (((x) & BIT_MASK_WMAC_TXTIMEOUT_8822B) \ + << BIT_SHIFT_WMAC_TXTIMEOUT_8822B) +#define BITS_WMAC_TXTIMEOUT_8822B \ + (BIT_MASK_WMAC_TXTIMEOUT_8822B << BIT_SHIFT_WMAC_TXTIMEOUT_8822B) +#define BIT_CLEAR_WMAC_TXTIMEOUT_8822B(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8822B)) +#define BIT_GET_WMAC_TXTIMEOUT_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822B) & \ + BIT_MASK_WMAC_TXTIMEOUT_8822B) +#define BIT_SET_WMAC_TXTIMEOUT_8822B(x, v) \ + (BIT_CLEAR_WMAC_TXTIMEOUT_8822B(x) | BIT_WMAC_TXTIMEOUT_8822B(v)) /* 2 REG_STMP_THSD_8822B */ #define BIT_SHIFT_STMP_THSD_8822B 0 #define BIT_MASK_STMP_THSD_8822B 0xff -#define BIT_STMP_THSD_8822B(x) (((x) & BIT_MASK_STMP_THSD_8822B) << BIT_SHIFT_STMP_THSD_8822B) -#define BIT_GET_STMP_THSD_8822B(x) (((x) >> BIT_SHIFT_STMP_THSD_8822B) & BIT_MASK_STMP_THSD_8822B) - - +#define BIT_STMP_THSD_8822B(x) \ + (((x) & BIT_MASK_STMP_THSD_8822B) << BIT_SHIFT_STMP_THSD_8822B) +#define BITS_STMP_THSD_8822B \ + (BIT_MASK_STMP_THSD_8822B << BIT_SHIFT_STMP_THSD_8822B) +#define BIT_CLEAR_STMP_THSD_8822B(x) ((x) & (~BITS_STMP_THSD_8822B)) +#define BIT_GET_STMP_THSD_8822B(x) \ + (((x) >> BIT_SHIFT_STMP_THSD_8822B) & BIT_MASK_STMP_THSD_8822B) +#define BIT_SET_STMP_THSD_8822B(x, v) \ + (BIT_CLEAR_STMP_THSD_8822B(x) | BIT_STMP_THSD_8822B(v)) /* 2 REG_MAC_SPEC_SIFS_8822B (SPECIFICATION SIFS REGISTER) */ #define BIT_SHIFT_SPEC_SIFS_OFDM_8822B 8 #define BIT_MASK_SPEC_SIFS_OFDM_8822B 0xff -#define BIT_SPEC_SIFS_OFDM_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8822B) << BIT_SHIFT_SPEC_SIFS_OFDM_8822B) -#define BIT_GET_SPEC_SIFS_OFDM_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822B) & BIT_MASK_SPEC_SIFS_OFDM_8822B) - - +#define BIT_SPEC_SIFS_OFDM_8822B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_8822B) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_8822B) +#define BITS_SPEC_SIFS_OFDM_8822B \ + (BIT_MASK_SPEC_SIFS_OFDM_8822B << BIT_SHIFT_SPEC_SIFS_OFDM_8822B) +#define BIT_CLEAR_SPEC_SIFS_OFDM_8822B(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8822B)) +#define BIT_GET_SPEC_SIFS_OFDM_8822B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822B) & \ + BIT_MASK_SPEC_SIFS_OFDM_8822B) +#define BIT_SET_SPEC_SIFS_OFDM_8822B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_8822B(x) | BIT_SPEC_SIFS_OFDM_8822B(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_8822B 0 #define BIT_MASK_SPEC_SIFS_CCK_8822B 0xff -#define BIT_SPEC_SIFS_CCK_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_8822B) -#define BIT_GET_SPEC_SIFS_CCK_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822B) & BIT_MASK_SPEC_SIFS_CCK_8822B) - - +#define BIT_SPEC_SIFS_CCK_8822B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_8822B) +#define BITS_SPEC_SIFS_CCK_8822B \ + (BIT_MASK_SPEC_SIFS_CCK_8822B << BIT_SHIFT_SPEC_SIFS_CCK_8822B) +#define BIT_CLEAR_SPEC_SIFS_CCK_8822B(x) ((x) & (~BITS_SPEC_SIFS_CCK_8822B)) +#define BIT_GET_SPEC_SIFS_CCK_8822B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822B) & BIT_MASK_SPEC_SIFS_CCK_8822B) +#define BIT_SET_SPEC_SIFS_CCK_8822B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_8822B(x) | BIT_SPEC_SIFS_CCK_8822B(v)) /* 2 REG_USTIME_EDCA_8822B (US TIME TUNING FOR EDCA REGISTER) */ #define BIT_SHIFT_USTIME_EDCA_V1_8822B 0 #define BIT_MASK_USTIME_EDCA_V1_8822B 0x1ff -#define BIT_USTIME_EDCA_V1_8822B(x) (((x) & BIT_MASK_USTIME_EDCA_V1_8822B) << BIT_SHIFT_USTIME_EDCA_V1_8822B) -#define BIT_GET_USTIME_EDCA_V1_8822B(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8822B) & BIT_MASK_USTIME_EDCA_V1_8822B) - - +#define BIT_USTIME_EDCA_V1_8822B(x) \ + (((x) & BIT_MASK_USTIME_EDCA_V1_8822B) \ + << BIT_SHIFT_USTIME_EDCA_V1_8822B) +#define BITS_USTIME_EDCA_V1_8822B \ + (BIT_MASK_USTIME_EDCA_V1_8822B << BIT_SHIFT_USTIME_EDCA_V1_8822B) +#define BIT_CLEAR_USTIME_EDCA_V1_8822B(x) ((x) & (~BITS_USTIME_EDCA_V1_8822B)) +#define BIT_GET_USTIME_EDCA_V1_8822B(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8822B) & \ + BIT_MASK_USTIME_EDCA_V1_8822B) +#define BIT_SET_USTIME_EDCA_V1_8822B(x, v) \ + (BIT_CLEAR_USTIME_EDCA_V1_8822B(x) | BIT_USTIME_EDCA_V1_8822B(v)) /* 2 REG_RESP_SIFS_OFDM_8822B (RESPONSE SIFS FOR OFDM REGISTER) */ #define BIT_SHIFT_SIFS_R2T_OFDM_8822B 8 #define BIT_MASK_SIFS_R2T_OFDM_8822B 0xff -#define BIT_SIFS_R2T_OFDM_8822B(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8822B) << BIT_SHIFT_SIFS_R2T_OFDM_8822B) -#define BIT_GET_SIFS_R2T_OFDM_8822B(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822B) & BIT_MASK_SIFS_R2T_OFDM_8822B) - - +#define BIT_SIFS_R2T_OFDM_8822B(x) \ + (((x) & BIT_MASK_SIFS_R2T_OFDM_8822B) << BIT_SHIFT_SIFS_R2T_OFDM_8822B) +#define BITS_SIFS_R2T_OFDM_8822B \ + (BIT_MASK_SIFS_R2T_OFDM_8822B << BIT_SHIFT_SIFS_R2T_OFDM_8822B) +#define BIT_CLEAR_SIFS_R2T_OFDM_8822B(x) ((x) & (~BITS_SIFS_R2T_OFDM_8822B)) +#define BIT_GET_SIFS_R2T_OFDM_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822B) & BIT_MASK_SIFS_R2T_OFDM_8822B) +#define BIT_SET_SIFS_R2T_OFDM_8822B(x, v) \ + (BIT_CLEAR_SIFS_R2T_OFDM_8822B(x) | BIT_SIFS_R2T_OFDM_8822B(v)) #define BIT_SHIFT_SIFS_T2T_OFDM_8822B 0 #define BIT_MASK_SIFS_T2T_OFDM_8822B 0xff -#define BIT_SIFS_T2T_OFDM_8822B(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8822B) << BIT_SHIFT_SIFS_T2T_OFDM_8822B) -#define BIT_GET_SIFS_T2T_OFDM_8822B(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822B) & BIT_MASK_SIFS_T2T_OFDM_8822B) - - +#define BIT_SIFS_T2T_OFDM_8822B(x) \ + (((x) & BIT_MASK_SIFS_T2T_OFDM_8822B) << BIT_SHIFT_SIFS_T2T_OFDM_8822B) +#define BITS_SIFS_T2T_OFDM_8822B \ + (BIT_MASK_SIFS_T2T_OFDM_8822B << BIT_SHIFT_SIFS_T2T_OFDM_8822B) +#define BIT_CLEAR_SIFS_T2T_OFDM_8822B(x) ((x) & (~BITS_SIFS_T2T_OFDM_8822B)) +#define BIT_GET_SIFS_T2T_OFDM_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822B) & BIT_MASK_SIFS_T2T_OFDM_8822B) +#define BIT_SET_SIFS_T2T_OFDM_8822B(x, v) \ + (BIT_CLEAR_SIFS_T2T_OFDM_8822B(x) | BIT_SIFS_T2T_OFDM_8822B(v)) /* 2 REG_RESP_SIFS_CCK_8822B (RESPONSE SIFS FOR CCK REGISTER) */ #define BIT_SHIFT_SIFS_R2T_CCK_8822B 8 #define BIT_MASK_SIFS_R2T_CCK_8822B 0xff -#define BIT_SIFS_R2T_CCK_8822B(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8822B) << BIT_SHIFT_SIFS_R2T_CCK_8822B) -#define BIT_GET_SIFS_R2T_CCK_8822B(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822B) & BIT_MASK_SIFS_R2T_CCK_8822B) - - +#define BIT_SIFS_R2T_CCK_8822B(x) \ + (((x) & BIT_MASK_SIFS_R2T_CCK_8822B) << BIT_SHIFT_SIFS_R2T_CCK_8822B) +#define BITS_SIFS_R2T_CCK_8822B \ + (BIT_MASK_SIFS_R2T_CCK_8822B << BIT_SHIFT_SIFS_R2T_CCK_8822B) +#define BIT_CLEAR_SIFS_R2T_CCK_8822B(x) ((x) & (~BITS_SIFS_R2T_CCK_8822B)) +#define BIT_GET_SIFS_R2T_CCK_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822B) & BIT_MASK_SIFS_R2T_CCK_8822B) +#define BIT_SET_SIFS_R2T_CCK_8822B(x, v) \ + (BIT_CLEAR_SIFS_R2T_CCK_8822B(x) | BIT_SIFS_R2T_CCK_8822B(v)) #define BIT_SHIFT_SIFS_T2T_CCK_8822B 0 #define BIT_MASK_SIFS_T2T_CCK_8822B 0xff -#define BIT_SIFS_T2T_CCK_8822B(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8822B) << BIT_SHIFT_SIFS_T2T_CCK_8822B) -#define BIT_GET_SIFS_T2T_CCK_8822B(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822B) & BIT_MASK_SIFS_T2T_CCK_8822B) - - +#define BIT_SIFS_T2T_CCK_8822B(x) \ + (((x) & BIT_MASK_SIFS_T2T_CCK_8822B) << BIT_SHIFT_SIFS_T2T_CCK_8822B) +#define BITS_SIFS_T2T_CCK_8822B \ + (BIT_MASK_SIFS_T2T_CCK_8822B << BIT_SHIFT_SIFS_T2T_CCK_8822B) +#define BIT_CLEAR_SIFS_T2T_CCK_8822B(x) ((x) & (~BITS_SIFS_T2T_CCK_8822B)) +#define BIT_GET_SIFS_T2T_CCK_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822B) & BIT_MASK_SIFS_T2T_CCK_8822B) +#define BIT_SET_SIFS_T2T_CCK_8822B(x, v) \ + (BIT_CLEAR_SIFS_T2T_CCK_8822B(x) | BIT_SIFS_T2T_CCK_8822B(v)) /* 2 REG_EIFS_8822B (EIFS REGISTER) */ #define BIT_SHIFT_EIFS_8822B 0 #define BIT_MASK_EIFS_8822B 0xffff #define BIT_EIFS_8822B(x) (((x) & BIT_MASK_EIFS_8822B) << BIT_SHIFT_EIFS_8822B) -#define BIT_GET_EIFS_8822B(x) (((x) >> BIT_SHIFT_EIFS_8822B) & BIT_MASK_EIFS_8822B) - - +#define BITS_EIFS_8822B (BIT_MASK_EIFS_8822B << BIT_SHIFT_EIFS_8822B) +#define BIT_CLEAR_EIFS_8822B(x) ((x) & (~BITS_EIFS_8822B)) +#define BIT_GET_EIFS_8822B(x) \ + (((x) >> BIT_SHIFT_EIFS_8822B) & BIT_MASK_EIFS_8822B) +#define BIT_SET_EIFS_8822B(x, v) (BIT_CLEAR_EIFS_8822B(x) | BIT_EIFS_8822B(v)) /* 2 REG_CTS2TO_8822B (CTS2 TIMEOUT REGISTER) */ #define BIT_SHIFT_CTS2TO_8822B 0 #define BIT_MASK_CTS2TO_8822B 0xff -#define BIT_CTS2TO_8822B(x) (((x) & BIT_MASK_CTS2TO_8822B) << BIT_SHIFT_CTS2TO_8822B) -#define BIT_GET_CTS2TO_8822B(x) (((x) >> BIT_SHIFT_CTS2TO_8822B) & BIT_MASK_CTS2TO_8822B) - - +#define BIT_CTS2TO_8822B(x) \ + (((x) & BIT_MASK_CTS2TO_8822B) << BIT_SHIFT_CTS2TO_8822B) +#define BITS_CTS2TO_8822B (BIT_MASK_CTS2TO_8822B << BIT_SHIFT_CTS2TO_8822B) +#define BIT_CLEAR_CTS2TO_8822B(x) ((x) & (~BITS_CTS2TO_8822B)) +#define BIT_GET_CTS2TO_8822B(x) \ + (((x) >> BIT_SHIFT_CTS2TO_8822B) & BIT_MASK_CTS2TO_8822B) +#define BIT_SET_CTS2TO_8822B(x, v) \ + (BIT_CLEAR_CTS2TO_8822B(x) | BIT_CTS2TO_8822B(v)) /* 2 REG_ACKTO_8822B (ACK TIMEOUT REGISTER) */ #define BIT_SHIFT_ACKTO_8822B 0 #define BIT_MASK_ACKTO_8822B 0xff -#define BIT_ACKTO_8822B(x) (((x) & BIT_MASK_ACKTO_8822B) << BIT_SHIFT_ACKTO_8822B) -#define BIT_GET_ACKTO_8822B(x) (((x) >> BIT_SHIFT_ACKTO_8822B) & BIT_MASK_ACKTO_8822B) - - +#define BIT_ACKTO_8822B(x) \ + (((x) & BIT_MASK_ACKTO_8822B) << BIT_SHIFT_ACKTO_8822B) +#define BITS_ACKTO_8822B (BIT_MASK_ACKTO_8822B << BIT_SHIFT_ACKTO_8822B) +#define BIT_CLEAR_ACKTO_8822B(x) ((x) & (~BITS_ACKTO_8822B)) +#define BIT_GET_ACKTO_8822B(x) \ + (((x) >> BIT_SHIFT_ACKTO_8822B) & BIT_MASK_ACKTO_8822B) +#define BIT_SET_ACKTO_8822B(x, v) \ + (BIT_CLEAR_ACKTO_8822B(x) | BIT_ACKTO_8822B(v)) /* 2 REG_NAV_CTRL_8822B (NAV CONTROL REGISTER) */ #define BIT_SHIFT_NAV_UPPER_8822B 16 #define BIT_MASK_NAV_UPPER_8822B 0xff -#define BIT_NAV_UPPER_8822B(x) (((x) & BIT_MASK_NAV_UPPER_8822B) << BIT_SHIFT_NAV_UPPER_8822B) -#define BIT_GET_NAV_UPPER_8822B(x) (((x) >> BIT_SHIFT_NAV_UPPER_8822B) & BIT_MASK_NAV_UPPER_8822B) - - +#define BIT_NAV_UPPER_8822B(x) \ + (((x) & BIT_MASK_NAV_UPPER_8822B) << BIT_SHIFT_NAV_UPPER_8822B) +#define BITS_NAV_UPPER_8822B \ + (BIT_MASK_NAV_UPPER_8822B << BIT_SHIFT_NAV_UPPER_8822B) +#define BIT_CLEAR_NAV_UPPER_8822B(x) ((x) & (~BITS_NAV_UPPER_8822B)) +#define BIT_GET_NAV_UPPER_8822B(x) \ + (((x) >> BIT_SHIFT_NAV_UPPER_8822B) & BIT_MASK_NAV_UPPER_8822B) +#define BIT_SET_NAV_UPPER_8822B(x, v) \ + (BIT_CLEAR_NAV_UPPER_8822B(x) | BIT_NAV_UPPER_8822B(v)) #define BIT_SHIFT_RXMYRTS_NAV_8822B 8 #define BIT_MASK_RXMYRTS_NAV_8822B 0xf -#define BIT_RXMYRTS_NAV_8822B(x) (((x) & BIT_MASK_RXMYRTS_NAV_8822B) << BIT_SHIFT_RXMYRTS_NAV_8822B) -#define BIT_GET_RXMYRTS_NAV_8822B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8822B) & BIT_MASK_RXMYRTS_NAV_8822B) - - +#define BIT_RXMYRTS_NAV_8822B(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_8822B) << BIT_SHIFT_RXMYRTS_NAV_8822B) +#define BITS_RXMYRTS_NAV_8822B \ + (BIT_MASK_RXMYRTS_NAV_8822B << BIT_SHIFT_RXMYRTS_NAV_8822B) +#define BIT_CLEAR_RXMYRTS_NAV_8822B(x) ((x) & (~BITS_RXMYRTS_NAV_8822B)) +#define BIT_GET_RXMYRTS_NAV_8822B(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_8822B) & BIT_MASK_RXMYRTS_NAV_8822B) +#define BIT_SET_RXMYRTS_NAV_8822B(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_8822B(x) | BIT_RXMYRTS_NAV_8822B(v)) #define BIT_SHIFT_RTSRST_8822B 0 #define BIT_MASK_RTSRST_8822B 0xff -#define BIT_RTSRST_8822B(x) (((x) & BIT_MASK_RTSRST_8822B) << BIT_SHIFT_RTSRST_8822B) -#define BIT_GET_RTSRST_8822B(x) (((x) >> BIT_SHIFT_RTSRST_8822B) & BIT_MASK_RTSRST_8822B) - - +#define BIT_RTSRST_8822B(x) \ + (((x) & BIT_MASK_RTSRST_8822B) << BIT_SHIFT_RTSRST_8822B) +#define BITS_RTSRST_8822B (BIT_MASK_RTSRST_8822B << BIT_SHIFT_RTSRST_8822B) +#define BIT_CLEAR_RTSRST_8822B(x) ((x) & (~BITS_RTSRST_8822B)) +#define BIT_GET_RTSRST_8822B(x) \ + (((x) >> BIT_SHIFT_RTSRST_8822B) & BIT_MASK_RTSRST_8822B) +#define BIT_SET_RTSRST_8822B(x, v) \ + (BIT_CLEAR_RTSRST_8822B(x) | BIT_RTSRST_8822B(v)) /* 2 REG_BACAMCMD_8822B (BLOCK ACK CAM COMMAND REGISTER) */ #define BIT_BACAM_POLL_8822B BIT(31) @@ -8607,33 +13693,52 @@ #define BIT_SHIFT_TXSBM_8822B 14 #define BIT_MASK_TXSBM_8822B 0x3 -#define BIT_TXSBM_8822B(x) (((x) & BIT_MASK_TXSBM_8822B) << BIT_SHIFT_TXSBM_8822B) -#define BIT_GET_TXSBM_8822B(x) (((x) >> BIT_SHIFT_TXSBM_8822B) & BIT_MASK_TXSBM_8822B) - - +#define BIT_TXSBM_8822B(x) \ + (((x) & BIT_MASK_TXSBM_8822B) << BIT_SHIFT_TXSBM_8822B) +#define BITS_TXSBM_8822B (BIT_MASK_TXSBM_8822B << BIT_SHIFT_TXSBM_8822B) +#define BIT_CLEAR_TXSBM_8822B(x) ((x) & (~BITS_TXSBM_8822B)) +#define BIT_GET_TXSBM_8822B(x) \ + (((x) >> BIT_SHIFT_TXSBM_8822B) & BIT_MASK_TXSBM_8822B) +#define BIT_SET_TXSBM_8822B(x, v) \ + (BIT_CLEAR_TXSBM_8822B(x) | BIT_TXSBM_8822B(v)) #define BIT_SHIFT_BACAM_ADDR_8822B 0 #define BIT_MASK_BACAM_ADDR_8822B 0x3f -#define BIT_BACAM_ADDR_8822B(x) (((x) & BIT_MASK_BACAM_ADDR_8822B) << BIT_SHIFT_BACAM_ADDR_8822B) -#define BIT_GET_BACAM_ADDR_8822B(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8822B) & BIT_MASK_BACAM_ADDR_8822B) - - +#define BIT_BACAM_ADDR_8822B(x) \ + (((x) & BIT_MASK_BACAM_ADDR_8822B) << BIT_SHIFT_BACAM_ADDR_8822B) +#define BITS_BACAM_ADDR_8822B \ + (BIT_MASK_BACAM_ADDR_8822B << BIT_SHIFT_BACAM_ADDR_8822B) +#define BIT_CLEAR_BACAM_ADDR_8822B(x) ((x) & (~BITS_BACAM_ADDR_8822B)) +#define BIT_GET_BACAM_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_BACAM_ADDR_8822B) & BIT_MASK_BACAM_ADDR_8822B) +#define BIT_SET_BACAM_ADDR_8822B(x, v) \ + (BIT_CLEAR_BACAM_ADDR_8822B(x) | BIT_BACAM_ADDR_8822B(v)) /* 2 REG_BACAMCONTENT_8822B (BLOCK ACK CAM CONTENT REGISTER) */ #define BIT_SHIFT_BA_CONTENT_H_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_BA_CONTENT_H_8822B 0xffffffffL -#define BIT_BA_CONTENT_H_8822B(x) (((x) & BIT_MASK_BA_CONTENT_H_8822B) << BIT_SHIFT_BA_CONTENT_H_8822B) -#define BIT_GET_BA_CONTENT_H_8822B(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8822B) & BIT_MASK_BA_CONTENT_H_8822B) - - +#define BIT_BA_CONTENT_H_8822B(x) \ + (((x) & BIT_MASK_BA_CONTENT_H_8822B) << BIT_SHIFT_BA_CONTENT_H_8822B) +#define BITS_BA_CONTENT_H_8822B \ + (BIT_MASK_BA_CONTENT_H_8822B << BIT_SHIFT_BA_CONTENT_H_8822B) +#define BIT_CLEAR_BA_CONTENT_H_8822B(x) ((x) & (~BITS_BA_CONTENT_H_8822B)) +#define BIT_GET_BA_CONTENT_H_8822B(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_H_8822B) & BIT_MASK_BA_CONTENT_H_8822B) +#define BIT_SET_BA_CONTENT_H_8822B(x, v) \ + (BIT_CLEAR_BA_CONTENT_H_8822B(x) | BIT_BA_CONTENT_H_8822B(v)) #define BIT_SHIFT_BA_CONTENT_L_8822B 0 #define BIT_MASK_BA_CONTENT_L_8822B 0xffffffffL -#define BIT_BA_CONTENT_L_8822B(x) (((x) & BIT_MASK_BA_CONTENT_L_8822B) << BIT_SHIFT_BA_CONTENT_L_8822B) -#define BIT_GET_BA_CONTENT_L_8822B(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8822B) & BIT_MASK_BA_CONTENT_L_8822B) - - +#define BIT_BA_CONTENT_L_8822B(x) \ + (((x) & BIT_MASK_BA_CONTENT_L_8822B) << BIT_SHIFT_BA_CONTENT_L_8822B) +#define BITS_BA_CONTENT_L_8822B \ + (BIT_MASK_BA_CONTENT_L_8822B << BIT_SHIFT_BA_CONTENT_L_8822B) +#define BIT_CLEAR_BA_CONTENT_L_8822B(x) ((x) & (~BITS_BA_CONTENT_L_8822B)) +#define BIT_GET_BA_CONTENT_L_8822B(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_L_8822B) & BIT_MASK_BA_CONTENT_L_8822B) +#define BIT_SET_BA_CONTENT_L_8822B(x, v) \ + (BIT_CLEAR_BA_CONTENT_L_8822B(x) | BIT_BA_CONTENT_L_8822B(v)) /* 2 REG_WMAC_BITMAP_CTL_8822B */ #define BIT_BITMAP_VO_8822B BIT(7) @@ -8643,9 +13748,18 @@ #define BIT_SHIFT_BITMAP_CONDITION_8822B 2 #define BIT_MASK_BITMAP_CONDITION_8822B 0x3 -#define BIT_BITMAP_CONDITION_8822B(x) (((x) & BIT_MASK_BITMAP_CONDITION_8822B) << BIT_SHIFT_BITMAP_CONDITION_8822B) -#define BIT_GET_BITMAP_CONDITION_8822B(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8822B) & BIT_MASK_BITMAP_CONDITION_8822B) - +#define BIT_BITMAP_CONDITION_8822B(x) \ + (((x) & BIT_MASK_BITMAP_CONDITION_8822B) \ + << BIT_SHIFT_BITMAP_CONDITION_8822B) +#define BITS_BITMAP_CONDITION_8822B \ + (BIT_MASK_BITMAP_CONDITION_8822B << BIT_SHIFT_BITMAP_CONDITION_8822B) +#define BIT_CLEAR_BITMAP_CONDITION_8822B(x) \ + ((x) & (~BITS_BITMAP_CONDITION_8822B)) +#define BIT_GET_BITMAP_CONDITION_8822B(x) \ + (((x) >> BIT_SHIFT_BITMAP_CONDITION_8822B) & \ + BIT_MASK_BITMAP_CONDITION_8822B) +#define BIT_SET_BITMAP_CONDITION_8822B(x, v) \ + (BIT_CLEAR_BITMAP_CONDITION_8822B(x) | BIT_BITMAP_CONDITION_8822B(v)) #define BIT_BITMAP_SSNBK_COUNTER_CLR_8822B BIT(1) #define BIT_BITMAP_FORCE_8822B BIT(0) @@ -8654,9 +13768,15 @@ #define BIT_SHIFT_RXPKT_TYPE_8822B 2 #define BIT_MASK_RXPKT_TYPE_8822B 0x3f -#define BIT_RXPKT_TYPE_8822B(x) (((x) & BIT_MASK_RXPKT_TYPE_8822B) << BIT_SHIFT_RXPKT_TYPE_8822B) -#define BIT_GET_RXPKT_TYPE_8822B(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8822B) & BIT_MASK_RXPKT_TYPE_8822B) - +#define BIT_RXPKT_TYPE_8822B(x) \ + (((x) & BIT_MASK_RXPKT_TYPE_8822B) << BIT_SHIFT_RXPKT_TYPE_8822B) +#define BITS_RXPKT_TYPE_8822B \ + (BIT_MASK_RXPKT_TYPE_8822B << BIT_SHIFT_RXPKT_TYPE_8822B) +#define BIT_CLEAR_RXPKT_TYPE_8822B(x) ((x) & (~BITS_RXPKT_TYPE_8822B)) +#define BIT_GET_RXPKT_TYPE_8822B(x) \ + (((x) >> BIT_SHIFT_RXPKT_TYPE_8822B) & BIT_MASK_RXPKT_TYPE_8822B) +#define BIT_SET_RXPKT_TYPE_8822B(x, v) \ + (BIT_CLEAR_RXPKT_TYPE_8822B(x) | BIT_RXPKT_TYPE_8822B(v)) #define BIT_TXACT_IND_8822B BIT(1) #define BIT_RXACT_IND_8822B BIT(0) @@ -8665,9 +13785,20 @@ #define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B 2 #define BIT_MASK_BITMAP_SSNBK_COUNTER_8822B 0x3f -#define BIT_BITMAP_SSNBK_COUNTER_8822B(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) -#define BIT_GET_BITMAP_SSNBK_COUNTER_8822B(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) - +#define BIT_BITMAP_SSNBK_COUNTER_8822B(x) \ + (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) +#define BITS_BITMAP_SSNBK_COUNTER_8822B \ + (BIT_MASK_BITMAP_SSNBK_COUNTER_8822B \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822B(x) \ + ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8822B)) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8822B(x) \ + (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) & \ + BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) +#define BIT_SET_BITMAP_SSNBK_COUNTER_8822B(x, v) \ + (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822B(x) | \ + BIT_BITMAP_SSNBK_COUNTER_8822B(v)) #define BIT_BITMAP_EN_8822B BIT(1) #define BIT_WMAC_BACAM_RPMEN_8822B BIT(0) @@ -8676,18 +13807,33 @@ #define BIT_SHIFT_LBDLY_8822B 0 #define BIT_MASK_LBDLY_8822B 0x1f -#define BIT_LBDLY_8822B(x) (((x) & BIT_MASK_LBDLY_8822B) << BIT_SHIFT_LBDLY_8822B) -#define BIT_GET_LBDLY_8822B(x) (((x) >> BIT_SHIFT_LBDLY_8822B) & BIT_MASK_LBDLY_8822B) - - +#define BIT_LBDLY_8822B(x) \ + (((x) & BIT_MASK_LBDLY_8822B) << BIT_SHIFT_LBDLY_8822B) +#define BITS_LBDLY_8822B (BIT_MASK_LBDLY_8822B << BIT_SHIFT_LBDLY_8822B) +#define BIT_CLEAR_LBDLY_8822B(x) ((x) & (~BITS_LBDLY_8822B)) +#define BIT_GET_LBDLY_8822B(x) \ + (((x) >> BIT_SHIFT_LBDLY_8822B) & BIT_MASK_LBDLY_8822B) +#define BIT_SET_LBDLY_8822B(x, v) \ + (BIT_CLEAR_LBDLY_8822B(x) | BIT_LBDLY_8822B(v)) /* 2 REG_RXERR_RPT_8822B (RX ERROR REPORT REGISTER) */ #define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B 28 #define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B 0xf -#define BIT_RXERR_RPT_SEL_V1_3_0_8822B(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) -#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822B(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) - +#define BIT_RXERR_RPT_SEL_V1_3_0_8822B(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) +#define BITS_RXERR_RPT_SEL_V1_3_0_8822B \ + (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822B(x) \ + ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8822B)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822B(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) & \ + BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8822B(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822B(x) | \ + BIT_RXERR_RPT_SEL_V1_3_0_8822B(v)) #define BIT_RXERR_RPT_RST_8822B BIT(27) #define BIT_RXERR_RPT_SEL_V1_4_8822B BIT(26) @@ -8696,53 +13842,92 @@ #define BIT_SHIFT_UD_SUB_TYPE_8822B 18 #define BIT_MASK_UD_SUB_TYPE_8822B 0xf -#define BIT_UD_SUB_TYPE_8822B(x) (((x) & BIT_MASK_UD_SUB_TYPE_8822B) << BIT_SHIFT_UD_SUB_TYPE_8822B) -#define BIT_GET_UD_SUB_TYPE_8822B(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8822B) & BIT_MASK_UD_SUB_TYPE_8822B) - - +#define BIT_UD_SUB_TYPE_8822B(x) \ + (((x) & BIT_MASK_UD_SUB_TYPE_8822B) << BIT_SHIFT_UD_SUB_TYPE_8822B) +#define BITS_UD_SUB_TYPE_8822B \ + (BIT_MASK_UD_SUB_TYPE_8822B << BIT_SHIFT_UD_SUB_TYPE_8822B) +#define BIT_CLEAR_UD_SUB_TYPE_8822B(x) ((x) & (~BITS_UD_SUB_TYPE_8822B)) +#define BIT_GET_UD_SUB_TYPE_8822B(x) \ + (((x) >> BIT_SHIFT_UD_SUB_TYPE_8822B) & BIT_MASK_UD_SUB_TYPE_8822B) +#define BIT_SET_UD_SUB_TYPE_8822B(x, v) \ + (BIT_CLEAR_UD_SUB_TYPE_8822B(x) | BIT_UD_SUB_TYPE_8822B(v)) #define BIT_SHIFT_UD_TYPE_8822B 16 #define BIT_MASK_UD_TYPE_8822B 0x3 -#define BIT_UD_TYPE_8822B(x) (((x) & BIT_MASK_UD_TYPE_8822B) << BIT_SHIFT_UD_TYPE_8822B) -#define BIT_GET_UD_TYPE_8822B(x) (((x) >> BIT_SHIFT_UD_TYPE_8822B) & BIT_MASK_UD_TYPE_8822B) - - +#define BIT_UD_TYPE_8822B(x) \ + (((x) & BIT_MASK_UD_TYPE_8822B) << BIT_SHIFT_UD_TYPE_8822B) +#define BITS_UD_TYPE_8822B (BIT_MASK_UD_TYPE_8822B << BIT_SHIFT_UD_TYPE_8822B) +#define BIT_CLEAR_UD_TYPE_8822B(x) ((x) & (~BITS_UD_TYPE_8822B)) +#define BIT_GET_UD_TYPE_8822B(x) \ + (((x) >> BIT_SHIFT_UD_TYPE_8822B) & BIT_MASK_UD_TYPE_8822B) +#define BIT_SET_UD_TYPE_8822B(x, v) \ + (BIT_CLEAR_UD_TYPE_8822B(x) | BIT_UD_TYPE_8822B(v)) #define BIT_SHIFT_RPT_COUNTER_8822B 0 #define BIT_MASK_RPT_COUNTER_8822B 0xffff -#define BIT_RPT_COUNTER_8822B(x) (((x) & BIT_MASK_RPT_COUNTER_8822B) << BIT_SHIFT_RPT_COUNTER_8822B) -#define BIT_GET_RPT_COUNTER_8822B(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8822B) & BIT_MASK_RPT_COUNTER_8822B) - - +#define BIT_RPT_COUNTER_8822B(x) \ + (((x) & BIT_MASK_RPT_COUNTER_8822B) << BIT_SHIFT_RPT_COUNTER_8822B) +#define BITS_RPT_COUNTER_8822B \ + (BIT_MASK_RPT_COUNTER_8822B << BIT_SHIFT_RPT_COUNTER_8822B) +#define BIT_CLEAR_RPT_COUNTER_8822B(x) ((x) & (~BITS_RPT_COUNTER_8822B)) +#define BIT_GET_RPT_COUNTER_8822B(x) \ + (((x) >> BIT_SHIFT_RPT_COUNTER_8822B) & BIT_MASK_RPT_COUNTER_8822B) +#define BIT_SET_RPT_COUNTER_8822B(x, v) \ + (BIT_CLEAR_RPT_COUNTER_8822B(x) | BIT_RPT_COUNTER_8822B(v)) /* 2 REG_WMAC_TRXPTCL_CTL_8822B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ #define BIT_SHIFT_ACKBA_TYPSEL_8822B (60 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBA_TYPSEL_8822B 0xf -#define BIT_ACKBA_TYPSEL_8822B(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8822B) << BIT_SHIFT_ACKBA_TYPSEL_8822B) -#define BIT_GET_ACKBA_TYPSEL_8822B(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822B) & BIT_MASK_ACKBA_TYPSEL_8822B) - - +#define BIT_ACKBA_TYPSEL_8822B(x) \ + (((x) & BIT_MASK_ACKBA_TYPSEL_8822B) << BIT_SHIFT_ACKBA_TYPSEL_8822B) +#define BITS_ACKBA_TYPSEL_8822B \ + (BIT_MASK_ACKBA_TYPSEL_8822B << BIT_SHIFT_ACKBA_TYPSEL_8822B) +#define BIT_CLEAR_ACKBA_TYPSEL_8822B(x) ((x) & (~BITS_ACKBA_TYPSEL_8822B)) +#define BIT_GET_ACKBA_TYPSEL_8822B(x) \ + (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822B) & BIT_MASK_ACKBA_TYPSEL_8822B) +#define BIT_SET_ACKBA_TYPSEL_8822B(x, v) \ + (BIT_CLEAR_ACKBA_TYPSEL_8822B(x) | BIT_ACKBA_TYPSEL_8822B(v)) #define BIT_SHIFT_ACKBA_ACKPCHK_8822B (56 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBA_ACKPCHK_8822B 0xf -#define BIT_ACKBA_ACKPCHK_8822B(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8822B) << BIT_SHIFT_ACKBA_ACKPCHK_8822B) -#define BIT_GET_ACKBA_ACKPCHK_8822B(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822B) & BIT_MASK_ACKBA_ACKPCHK_8822B) - - +#define BIT_ACKBA_ACKPCHK_8822B(x) \ + (((x) & BIT_MASK_ACKBA_ACKPCHK_8822B) << BIT_SHIFT_ACKBA_ACKPCHK_8822B) +#define BITS_ACKBA_ACKPCHK_8822B \ + (BIT_MASK_ACKBA_ACKPCHK_8822B << BIT_SHIFT_ACKBA_ACKPCHK_8822B) +#define BIT_CLEAR_ACKBA_ACKPCHK_8822B(x) ((x) & (~BITS_ACKBA_ACKPCHK_8822B)) +#define BIT_GET_ACKBA_ACKPCHK_8822B(x) \ + (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822B) & BIT_MASK_ACKBA_ACKPCHK_8822B) +#define BIT_SET_ACKBA_ACKPCHK_8822B(x, v) \ + (BIT_CLEAR_ACKBA_ACKPCHK_8822B(x) | BIT_ACKBA_ACKPCHK_8822B(v)) #define BIT_SHIFT_ACKBAR_TYPESEL_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBAR_TYPESEL_8822B 0xff -#define BIT_ACKBAR_TYPESEL_8822B(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8822B) << BIT_SHIFT_ACKBAR_TYPESEL_8822B) -#define BIT_GET_ACKBAR_TYPESEL_8822B(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822B) & BIT_MASK_ACKBAR_TYPESEL_8822B) - - +#define BIT_ACKBAR_TYPESEL_8822B(x) \ + (((x) & BIT_MASK_ACKBAR_TYPESEL_8822B) \ + << BIT_SHIFT_ACKBAR_TYPESEL_8822B) +#define BITS_ACKBAR_TYPESEL_8822B \ + (BIT_MASK_ACKBAR_TYPESEL_8822B << BIT_SHIFT_ACKBAR_TYPESEL_8822B) +#define BIT_CLEAR_ACKBAR_TYPESEL_8822B(x) ((x) & (~BITS_ACKBAR_TYPESEL_8822B)) +#define BIT_GET_ACKBAR_TYPESEL_8822B(x) \ + (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822B) & \ + BIT_MASK_ACKBAR_TYPESEL_8822B) +#define BIT_SET_ACKBAR_TYPESEL_8822B(x, v) \ + (BIT_CLEAR_ACKBAR_TYPESEL_8822B(x) | BIT_ACKBAR_TYPESEL_8822B(v)) #define BIT_SHIFT_ACKBAR_ACKPCHK_8822B (44 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBAR_ACKPCHK_8822B 0xf -#define BIT_ACKBAR_ACKPCHK_8822B(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8822B) << BIT_SHIFT_ACKBAR_ACKPCHK_8822B) -#define BIT_GET_ACKBAR_ACKPCHK_8822B(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822B) & BIT_MASK_ACKBAR_ACKPCHK_8822B) - +#define BIT_ACKBAR_ACKPCHK_8822B(x) \ + (((x) & BIT_MASK_ACKBAR_ACKPCHK_8822B) \ + << BIT_SHIFT_ACKBAR_ACKPCHK_8822B) +#define BITS_ACKBAR_ACKPCHK_8822B \ + (BIT_MASK_ACKBAR_ACKPCHK_8822B << BIT_SHIFT_ACKBAR_ACKPCHK_8822B) +#define BIT_CLEAR_ACKBAR_ACKPCHK_8822B(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8822B)) +#define BIT_GET_ACKBAR_ACKPCHK_8822B(x) \ + (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822B) & \ + BIT_MASK_ACKBAR_ACKPCHK_8822B) +#define BIT_SET_ACKBAR_ACKPCHK_8822B(x, v) \ + (BIT_CLEAR_ACKBAR_ACKPCHK_8822B(x) | BIT_ACKBAR_ACKPCHK_8822B(v)) #define BIT_RXBA_IGNOREA2_8822B BIT(42) #define BIT_EN_SAVE_ALL_TXOPADDR_8822B BIT(41) @@ -8766,9 +13951,15 @@ #define BIT_SHIFT_RESP_CHNBUSY_8822B 20 #define BIT_MASK_RESP_CHNBUSY_8822B 0x3 -#define BIT_RESP_CHNBUSY_8822B(x) (((x) & BIT_MASK_RESP_CHNBUSY_8822B) << BIT_SHIFT_RESP_CHNBUSY_8822B) -#define BIT_GET_RESP_CHNBUSY_8822B(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8822B) & BIT_MASK_RESP_CHNBUSY_8822B) - +#define BIT_RESP_CHNBUSY_8822B(x) \ + (((x) & BIT_MASK_RESP_CHNBUSY_8822B) << BIT_SHIFT_RESP_CHNBUSY_8822B) +#define BITS_RESP_CHNBUSY_8822B \ + (BIT_MASK_RESP_CHNBUSY_8822B << BIT_SHIFT_RESP_CHNBUSY_8822B) +#define BIT_CLEAR_RESP_CHNBUSY_8822B(x) ((x) & (~BITS_RESP_CHNBUSY_8822B)) +#define BIT_GET_RESP_CHNBUSY_8822B(x) \ + (((x) >> BIT_SHIFT_RESP_CHNBUSY_8822B) & BIT_MASK_RESP_CHNBUSY_8822B) +#define BIT_SET_RESP_CHNBUSY_8822B(x, v) \ + (BIT_CLEAR_RESP_CHNBUSY_8822B(x) | BIT_RESP_CHNBUSY_8822B(v)) #define BIT_RESP_DCTS_EN_8822B BIT(19) #define BIT_RESP_DCFE_EN_8822B BIT(18) @@ -8780,33 +13971,63 @@ #define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B 10 #define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B 0x7 -#define BIT_R_WMAC_SECOND_CCA_TIMER_8822B(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) -#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B) - - +#define BIT_R_WMAC_SECOND_CCA_TIMER_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B) \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) +#define BITS_R_WMAC_SECOND_CCA_TIMER_8822B \ + (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822B(x) \ + ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8822B)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) & \ + BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822B(x) | \ + BIT_R_WMAC_SECOND_CCA_TIMER_8822B(v)) #define BIT_SHIFT_RFMOD_8822B 7 #define BIT_MASK_RFMOD_8822B 0x3 -#define BIT_RFMOD_8822B(x) (((x) & BIT_MASK_RFMOD_8822B) << BIT_SHIFT_RFMOD_8822B) -#define BIT_GET_RFMOD_8822B(x) (((x) >> BIT_SHIFT_RFMOD_8822B) & BIT_MASK_RFMOD_8822B) - - +#define BIT_RFMOD_8822B(x) \ + (((x) & BIT_MASK_RFMOD_8822B) << BIT_SHIFT_RFMOD_8822B) +#define BITS_RFMOD_8822B (BIT_MASK_RFMOD_8822B << BIT_SHIFT_RFMOD_8822B) +#define BIT_CLEAR_RFMOD_8822B(x) ((x) & (~BITS_RFMOD_8822B)) +#define BIT_GET_RFMOD_8822B(x) \ + (((x) >> BIT_SHIFT_RFMOD_8822B) & BIT_MASK_RFMOD_8822B) +#define BIT_SET_RFMOD_8822B(x, v) \ + (BIT_CLEAR_RFMOD_8822B(x) | BIT_RFMOD_8822B(v)) #define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B 5 #define BIT_MASK_RESP_CTS_DYNBW_SEL_8822B 0x3 -#define BIT_RESP_CTS_DYNBW_SEL_8822B(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) -#define BIT_GET_RESP_CTS_DYNBW_SEL_8822B(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) - +#define BIT_RESP_CTS_DYNBW_SEL_8822B(x) \ + (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) +#define BITS_RESP_CTS_DYNBW_SEL_8822B \ + (BIT_MASK_RESP_CTS_DYNBW_SEL_8822B \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822B(x) \ + ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8822B)) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) & \ + BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) +#define BIT_SET_RESP_CTS_DYNBW_SEL_8822B(x, v) \ + (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822B(x) | \ + BIT_RESP_CTS_DYNBW_SEL_8822B(v)) #define BIT_DLY_TX_WAIT_RXANTSEL_8822B BIT(4) #define BIT_TXRESP_BY_RXANTSEL_8822B BIT(3) #define BIT_SHIFT_ORIG_DCTS_CHK_8822B 0 #define BIT_MASK_ORIG_DCTS_CHK_8822B 0x3 -#define BIT_ORIG_DCTS_CHK_8822B(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8822B) << BIT_SHIFT_ORIG_DCTS_CHK_8822B) -#define BIT_GET_ORIG_DCTS_CHK_8822B(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822B) & BIT_MASK_ORIG_DCTS_CHK_8822B) - - +#define BIT_ORIG_DCTS_CHK_8822B(x) \ + (((x) & BIT_MASK_ORIG_DCTS_CHK_8822B) << BIT_SHIFT_ORIG_DCTS_CHK_8822B) +#define BITS_ORIG_DCTS_CHK_8822B \ + (BIT_MASK_ORIG_DCTS_CHK_8822B << BIT_SHIFT_ORIG_DCTS_CHK_8822B) +#define BIT_CLEAR_ORIG_DCTS_CHK_8822B(x) ((x) & (~BITS_ORIG_DCTS_CHK_8822B)) +#define BIT_GET_ORIG_DCTS_CHK_8822B(x) \ + (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822B) & BIT_MASK_ORIG_DCTS_CHK_8822B) +#define BIT_SET_ORIG_DCTS_CHK_8822B(x, v) \ + (BIT_CLEAR_ORIG_DCTS_CHK_8822B(x) | BIT_ORIG_DCTS_CHK_8822B(v)) /* 2 REG_CAMCMD_8822B (CAM COMMAND REGISTER) */ #define BIT_SECCAM_POLLING_8822B BIT(31) @@ -8816,28 +14037,45 @@ #define BIT_SHIFT_SECCAM_ADDR_V2_8822B 0 #define BIT_MASK_SECCAM_ADDR_V2_8822B 0x3ff -#define BIT_SECCAM_ADDR_V2_8822B(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8822B) << BIT_SHIFT_SECCAM_ADDR_V2_8822B) -#define BIT_GET_SECCAM_ADDR_V2_8822B(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822B) & BIT_MASK_SECCAM_ADDR_V2_8822B) - - +#define BIT_SECCAM_ADDR_V2_8822B(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V2_8822B) \ + << BIT_SHIFT_SECCAM_ADDR_V2_8822B) +#define BITS_SECCAM_ADDR_V2_8822B \ + (BIT_MASK_SECCAM_ADDR_V2_8822B << BIT_SHIFT_SECCAM_ADDR_V2_8822B) +#define BIT_CLEAR_SECCAM_ADDR_V2_8822B(x) ((x) & (~BITS_SECCAM_ADDR_V2_8822B)) +#define BIT_GET_SECCAM_ADDR_V2_8822B(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822B) & \ + BIT_MASK_SECCAM_ADDR_V2_8822B) +#define BIT_SET_SECCAM_ADDR_V2_8822B(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V2_8822B(x) | BIT_SECCAM_ADDR_V2_8822B(v)) /* 2 REG_CAMWRITE_8822B (CAM WRITE REGISTER) */ #define BIT_SHIFT_CAMW_DATA_8822B 0 #define BIT_MASK_CAMW_DATA_8822B 0xffffffffL -#define BIT_CAMW_DATA_8822B(x) (((x) & BIT_MASK_CAMW_DATA_8822B) << BIT_SHIFT_CAMW_DATA_8822B) -#define BIT_GET_CAMW_DATA_8822B(x) (((x) >> BIT_SHIFT_CAMW_DATA_8822B) & BIT_MASK_CAMW_DATA_8822B) - - +#define BIT_CAMW_DATA_8822B(x) \ + (((x) & BIT_MASK_CAMW_DATA_8822B) << BIT_SHIFT_CAMW_DATA_8822B) +#define BITS_CAMW_DATA_8822B \ + (BIT_MASK_CAMW_DATA_8822B << BIT_SHIFT_CAMW_DATA_8822B) +#define BIT_CLEAR_CAMW_DATA_8822B(x) ((x) & (~BITS_CAMW_DATA_8822B)) +#define BIT_GET_CAMW_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_CAMW_DATA_8822B) & BIT_MASK_CAMW_DATA_8822B) +#define BIT_SET_CAMW_DATA_8822B(x, v) \ + (BIT_CLEAR_CAMW_DATA_8822B(x) | BIT_CAMW_DATA_8822B(v)) /* 2 REG_CAMREAD_8822B (CAM READ REGISTER) */ #define BIT_SHIFT_CAMR_DATA_8822B 0 #define BIT_MASK_CAMR_DATA_8822B 0xffffffffL -#define BIT_CAMR_DATA_8822B(x) (((x) & BIT_MASK_CAMR_DATA_8822B) << BIT_SHIFT_CAMR_DATA_8822B) -#define BIT_GET_CAMR_DATA_8822B(x) (((x) >> BIT_SHIFT_CAMR_DATA_8822B) & BIT_MASK_CAMR_DATA_8822B) - - +#define BIT_CAMR_DATA_8822B(x) \ + (((x) & BIT_MASK_CAMR_DATA_8822B) << BIT_SHIFT_CAMR_DATA_8822B) +#define BITS_CAMR_DATA_8822B \ + (BIT_MASK_CAMR_DATA_8822B << BIT_SHIFT_CAMR_DATA_8822B) +#define BIT_CLEAR_CAMR_DATA_8822B(x) ((x) & (~BITS_CAMR_DATA_8822B)) +#define BIT_GET_CAMR_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_CAMR_DATA_8822B) & BIT_MASK_CAMR_DATA_8822B) +#define BIT_SET_CAMR_DATA_8822B(x, v) \ + (BIT_CLEAR_CAMR_DATA_8822B(x) | BIT_CAMR_DATA_8822B(v)) /* 2 REG_CAMDBG_8822B (CAM DEBUG REGISTER) */ #define BIT_SECCAM_INFO_8822B BIT(31) @@ -8845,43 +14083,89 @@ #define BIT_SHIFT_CAMDBG_SEC_TYPE_8822B 12 #define BIT_MASK_CAMDBG_SEC_TYPE_8822B 0x7 -#define BIT_CAMDBG_SEC_TYPE_8822B(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822B) << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) -#define BIT_GET_CAMDBG_SEC_TYPE_8822B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) & BIT_MASK_CAMDBG_SEC_TYPE_8822B) - +#define BIT_CAMDBG_SEC_TYPE_8822B(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822B) \ + << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) +#define BITS_CAMDBG_SEC_TYPE_8822B \ + (BIT_MASK_CAMDBG_SEC_TYPE_8822B << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) +#define BIT_CLEAR_CAMDBG_SEC_TYPE_8822B(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8822B)) +#define BIT_GET_CAMDBG_SEC_TYPE_8822B(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) & \ + BIT_MASK_CAMDBG_SEC_TYPE_8822B) +#define BIT_SET_CAMDBG_SEC_TYPE_8822B(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE_8822B(x) | BIT_CAMDBG_SEC_TYPE_8822B(v)) #define BIT_CAMDBG_EXT_SECTYPE_8822B BIT(11) #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B 5 #define BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B 0x1f -#define BIT_CAMDBG_MIC_KEY_IDX_8822B(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) -#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822B(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B) - - +#define BIT_CAMDBG_MIC_KEY_IDX_8822B(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B) \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) +#define BITS_CAMDBG_MIC_KEY_IDX_8822B \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822B(x) \ + ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8822B)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) & \ + BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_8822B(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822B(x) | \ + BIT_CAMDBG_MIC_KEY_IDX_8822B(v)) #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B 0 #define BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B 0x1f -#define BIT_CAMDBG_SEC_KEY_IDX_8822B(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) -#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) - - +#define BIT_CAMDBG_SEC_KEY_IDX_8822B(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) +#define BITS_CAMDBG_SEC_KEY_IDX_8822B \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822B(x) \ + ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8822B)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) & \ + BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_8822B(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822B(x) | \ + BIT_CAMDBG_SEC_KEY_IDX_8822B(v)) /* 2 REG_RXFILTER_ACTION_1_8822B */ #define BIT_SHIFT_RXFILTER_ACTION_1_8822B 0 #define BIT_MASK_RXFILTER_ACTION_1_8822B 0xff -#define BIT_RXFILTER_ACTION_1_8822B(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8822B) << BIT_SHIFT_RXFILTER_ACTION_1_8822B) -#define BIT_GET_RXFILTER_ACTION_1_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822B) & BIT_MASK_RXFILTER_ACTION_1_8822B) - - +#define BIT_RXFILTER_ACTION_1_8822B(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_1_8822B) \ + << BIT_SHIFT_RXFILTER_ACTION_1_8822B) +#define BITS_RXFILTER_ACTION_1_8822B \ + (BIT_MASK_RXFILTER_ACTION_1_8822B << BIT_SHIFT_RXFILTER_ACTION_1_8822B) +#define BIT_CLEAR_RXFILTER_ACTION_1_8822B(x) \ + ((x) & (~BITS_RXFILTER_ACTION_1_8822B)) +#define BIT_GET_RXFILTER_ACTION_1_8822B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822B) & \ + BIT_MASK_RXFILTER_ACTION_1_8822B) +#define BIT_SET_RXFILTER_ACTION_1_8822B(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_1_8822B(x) | BIT_RXFILTER_ACTION_1_8822B(v)) /* 2 REG_RXFILTER_CATEGORY_1_8822B */ #define BIT_SHIFT_RXFILTER_CATEGORY_1_8822B 0 #define BIT_MASK_RXFILTER_CATEGORY_1_8822B 0xff -#define BIT_RXFILTER_CATEGORY_1_8822B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822B) << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) -#define BIT_GET_RXFILTER_CATEGORY_1_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) & BIT_MASK_RXFILTER_CATEGORY_1_8822B) - - +#define BIT_RXFILTER_CATEGORY_1_8822B(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822B) \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) +#define BITS_RXFILTER_CATEGORY_1_8822B \ + (BIT_MASK_RXFILTER_CATEGORY_1_8822B \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) +#define BIT_CLEAR_RXFILTER_CATEGORY_1_8822B(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_1_8822B)) +#define BIT_GET_RXFILTER_CATEGORY_1_8822B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) & \ + BIT_MASK_RXFILTER_CATEGORY_1_8822B) +#define BIT_SET_RXFILTER_CATEGORY_1_8822B(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_1_8822B(x) | \ + BIT_RXFILTER_CATEGORY_1_8822B(v)) /* 2 REG_SECCFG_8822B (SECURITY CONFIGURATION REGISTER) */ #define BIT_DIS_GCLK_WAPI_8822B BIT(15) @@ -8904,37 +14188,73 @@ #define BIT_SHIFT_RXFILTER_ACTION_3_8822B 0 #define BIT_MASK_RXFILTER_ACTION_3_8822B 0xff -#define BIT_RXFILTER_ACTION_3_8822B(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8822B) << BIT_SHIFT_RXFILTER_ACTION_3_8822B) -#define BIT_GET_RXFILTER_ACTION_3_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822B) & BIT_MASK_RXFILTER_ACTION_3_8822B) - - +#define BIT_RXFILTER_ACTION_3_8822B(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_3_8822B) \ + << BIT_SHIFT_RXFILTER_ACTION_3_8822B) +#define BITS_RXFILTER_ACTION_3_8822B \ + (BIT_MASK_RXFILTER_ACTION_3_8822B << BIT_SHIFT_RXFILTER_ACTION_3_8822B) +#define BIT_CLEAR_RXFILTER_ACTION_3_8822B(x) \ + ((x) & (~BITS_RXFILTER_ACTION_3_8822B)) +#define BIT_GET_RXFILTER_ACTION_3_8822B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822B) & \ + BIT_MASK_RXFILTER_ACTION_3_8822B) +#define BIT_SET_RXFILTER_ACTION_3_8822B(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_3_8822B(x) | BIT_RXFILTER_ACTION_3_8822B(v)) /* 2 REG_RXFILTER_CATEGORY_3_8822B */ #define BIT_SHIFT_RXFILTER_CATEGORY_3_8822B 0 #define BIT_MASK_RXFILTER_CATEGORY_3_8822B 0xff -#define BIT_RXFILTER_CATEGORY_3_8822B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822B) << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) -#define BIT_GET_RXFILTER_CATEGORY_3_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) & BIT_MASK_RXFILTER_CATEGORY_3_8822B) - - +#define BIT_RXFILTER_CATEGORY_3_8822B(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822B) \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) +#define BITS_RXFILTER_CATEGORY_3_8822B \ + (BIT_MASK_RXFILTER_CATEGORY_3_8822B \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) +#define BIT_CLEAR_RXFILTER_CATEGORY_3_8822B(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_3_8822B)) +#define BIT_GET_RXFILTER_CATEGORY_3_8822B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) & \ + BIT_MASK_RXFILTER_CATEGORY_3_8822B) +#define BIT_SET_RXFILTER_CATEGORY_3_8822B(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_3_8822B(x) | \ + BIT_RXFILTER_CATEGORY_3_8822B(v)) /* 2 REG_RXFILTER_ACTION_2_8822B */ #define BIT_SHIFT_RXFILTER_ACTION_2_8822B 0 #define BIT_MASK_RXFILTER_ACTION_2_8822B 0xff -#define BIT_RXFILTER_ACTION_2_8822B(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8822B) << BIT_SHIFT_RXFILTER_ACTION_2_8822B) -#define BIT_GET_RXFILTER_ACTION_2_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822B) & BIT_MASK_RXFILTER_ACTION_2_8822B) - - +#define BIT_RXFILTER_ACTION_2_8822B(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_2_8822B) \ + << BIT_SHIFT_RXFILTER_ACTION_2_8822B) +#define BITS_RXFILTER_ACTION_2_8822B \ + (BIT_MASK_RXFILTER_ACTION_2_8822B << BIT_SHIFT_RXFILTER_ACTION_2_8822B) +#define BIT_CLEAR_RXFILTER_ACTION_2_8822B(x) \ + ((x) & (~BITS_RXFILTER_ACTION_2_8822B)) +#define BIT_GET_RXFILTER_ACTION_2_8822B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822B) & \ + BIT_MASK_RXFILTER_ACTION_2_8822B) +#define BIT_SET_RXFILTER_ACTION_2_8822B(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_2_8822B(x) | BIT_RXFILTER_ACTION_2_8822B(v)) /* 2 REG_RXFILTER_CATEGORY_2_8822B */ #define BIT_SHIFT_RXFILTER_CATEGORY_2_8822B 0 #define BIT_MASK_RXFILTER_CATEGORY_2_8822B 0xff -#define BIT_RXFILTER_CATEGORY_2_8822B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822B) << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) -#define BIT_GET_RXFILTER_CATEGORY_2_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) & BIT_MASK_RXFILTER_CATEGORY_2_8822B) - - +#define BIT_RXFILTER_CATEGORY_2_8822B(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822B) \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) +#define BITS_RXFILTER_CATEGORY_2_8822B \ + (BIT_MASK_RXFILTER_CATEGORY_2_8822B \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) +#define BIT_CLEAR_RXFILTER_CATEGORY_2_8822B(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_2_8822B)) +#define BIT_GET_RXFILTER_CATEGORY_2_8822B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) & \ + BIT_MASK_RXFILTER_CATEGORY_2_8822B) +#define BIT_SET_RXFILTER_CATEGORY_2_8822B(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_2_8822B(x) | \ + BIT_RXFILTER_CATEGORY_2_8822B(v)) /* 2 REG_RXFLTMAP4_8822B (RX FILTER MAP GROUP 4) */ #define BIT_CTRLFLT15EN_FW_8822B BIT(15) @@ -8972,7 +14292,7 @@ #define BIT_MGTFLT1EN_FW_8822B BIT(1) #define BIT_MGTFLT0EN_FW_8822B BIT(0) -/* 2 REG_RXFLTMAP6_8822B (RX FILTER MAP GROUP 3) */ +/* 2 REG_RXFLTMAP6_8822B (RX FILTER MAP GROUP 6) */ #define BIT_ACTIONFLT15EN_FW_8822B BIT(15) #define BIT_ACTIONFLT14EN_FW_8822B BIT(14) #define BIT_ACTIONFLT13EN_FW_8822B BIT(13) @@ -8990,7 +14310,7 @@ #define BIT_ACTIONFLT1EN_FW_8822B BIT(1) #define BIT_ACTIONFLT0EN_FW_8822B BIT(0) -/* 2 REG_RXFLTMAP5_8822B (RX FILTER MAP GROUP 3) */ +/* 2 REG_RXFLTMAP5_8822B (RX FILTER MAP GROUP 5) */ #define BIT_DATAFLT15EN_FW_8822B BIT(15) #define BIT_DATAFLT14EN_FW_8822B BIT(14) #define BIT_DATAFLT13EN_FW_8822B BIT(13) @@ -9022,9 +14342,20 @@ #define BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B 5 #define BIT_MASK_PORTSEL__PS_RX_INFO_8822B 0x7 -#define BIT_PORTSEL__PS_RX_INFO_8822B(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) -#define BIT_GET_PORTSEL__PS_RX_INFO_8822B(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B) - +#define BIT_PORTSEL__PS_RX_INFO_8822B(x) \ + (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B) \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) +#define BITS_PORTSEL__PS_RX_INFO_8822B \ + (BIT_MASK_PORTSEL__PS_RX_INFO_8822B \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8822B(x) \ + ((x) & (~BITS_PORTSEL__PS_RX_INFO_8822B)) +#define BIT_GET_PORTSEL__PS_RX_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) & \ + BIT_MASK_PORTSEL__PS_RX_INFO_8822B) +#define BIT_SET_PORTSEL__PS_RX_INFO_8822B(x, v) \ + (BIT_CLEAR_PORTSEL__PS_RX_INFO_8822B(x) | \ + BIT_PORTSEL__PS_RX_INFO_8822B(v)) #define BIT_RXCTRLIN0_8822B BIT(4) #define BIT_RXMGTIN0_8822B BIT(3) @@ -9041,9 +14372,18 @@ #define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B 6 #define BIT_MASK_PSF_BSSIDSEL_B2B1_8822B 0x3 -#define BIT_PSF_BSSIDSEL_B2B1_8822B(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) -#define BIT_GET_PSF_BSSIDSEL_B2B1_8822B(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) - +#define BIT_PSF_BSSIDSEL_B2B1_8822B(x) \ + (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) \ + << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) +#define BITS_PSF_BSSIDSEL_B2B1_8822B \ + (BIT_MASK_PSF_BSSIDSEL_B2B1_8822B << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822B(x) \ + ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8822B)) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8822B(x) \ + (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) & \ + BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) +#define BIT_SET_PSF_BSSIDSEL_B2B1_8822B(x, v) \ + (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822B(x) | BIT_PSF_BSSIDSEL_B2B1_8822B(v)) #define BIT_WOWHCI_8822B BIT(5) #define BIT_PSF_BSSIDSEL_B0_8822B BIT(4) @@ -9057,17 +14397,27 @@ #define BIT_SHIFT_LPNAV_EARLY_8822B 16 #define BIT_MASK_LPNAV_EARLY_8822B 0x7fff -#define BIT_LPNAV_EARLY_8822B(x) (((x) & BIT_MASK_LPNAV_EARLY_8822B) << BIT_SHIFT_LPNAV_EARLY_8822B) -#define BIT_GET_LPNAV_EARLY_8822B(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8822B) & BIT_MASK_LPNAV_EARLY_8822B) - - +#define BIT_LPNAV_EARLY_8822B(x) \ + (((x) & BIT_MASK_LPNAV_EARLY_8822B) << BIT_SHIFT_LPNAV_EARLY_8822B) +#define BITS_LPNAV_EARLY_8822B \ + (BIT_MASK_LPNAV_EARLY_8822B << BIT_SHIFT_LPNAV_EARLY_8822B) +#define BIT_CLEAR_LPNAV_EARLY_8822B(x) ((x) & (~BITS_LPNAV_EARLY_8822B)) +#define BIT_GET_LPNAV_EARLY_8822B(x) \ + (((x) >> BIT_SHIFT_LPNAV_EARLY_8822B) & BIT_MASK_LPNAV_EARLY_8822B) +#define BIT_SET_LPNAV_EARLY_8822B(x, v) \ + (BIT_CLEAR_LPNAV_EARLY_8822B(x) | BIT_LPNAV_EARLY_8822B(v)) #define BIT_SHIFT_LPNAV_TH_8822B 0 #define BIT_MASK_LPNAV_TH_8822B 0xffff -#define BIT_LPNAV_TH_8822B(x) (((x) & BIT_MASK_LPNAV_TH_8822B) << BIT_SHIFT_LPNAV_TH_8822B) -#define BIT_GET_LPNAV_TH_8822B(x) (((x) >> BIT_SHIFT_LPNAV_TH_8822B) & BIT_MASK_LPNAV_TH_8822B) - - +#define BIT_LPNAV_TH_8822B(x) \ + (((x) & BIT_MASK_LPNAV_TH_8822B) << BIT_SHIFT_LPNAV_TH_8822B) +#define BITS_LPNAV_TH_8822B \ + (BIT_MASK_LPNAV_TH_8822B << BIT_SHIFT_LPNAV_TH_8822B) +#define BIT_CLEAR_LPNAV_TH_8822B(x) ((x) & (~BITS_LPNAV_TH_8822B)) +#define BIT_GET_LPNAV_TH_8822B(x) \ + (((x) >> BIT_SHIFT_LPNAV_TH_8822B) & BIT_MASK_LPNAV_TH_8822B) +#define BIT_SET_LPNAV_TH_8822B(x, v) \ + (BIT_CLEAR_LPNAV_TH_8822B(x) | BIT_LPNAV_TH_8822B(v)) /* 2 REG_WKFMCAM_CMD_8822B (WAKEUP FRAME CAM COMMAND REGISTER) */ #define BIT_WKFCAM_POLLING_V1_8822B BIT(31) @@ -9076,26 +14426,46 @@ #define BIT_SHIFT_WKFCAM_ADDR_V2_8822B 8 #define BIT_MASK_WKFCAM_ADDR_V2_8822B 0xff -#define BIT_WKFCAM_ADDR_V2_8822B(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8822B) << BIT_SHIFT_WKFCAM_ADDR_V2_8822B) -#define BIT_GET_WKFCAM_ADDR_V2_8822B(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822B) & BIT_MASK_WKFCAM_ADDR_V2_8822B) - - +#define BIT_WKFCAM_ADDR_V2_8822B(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR_V2_8822B) \ + << BIT_SHIFT_WKFCAM_ADDR_V2_8822B) +#define BITS_WKFCAM_ADDR_V2_8822B \ + (BIT_MASK_WKFCAM_ADDR_V2_8822B << BIT_SHIFT_WKFCAM_ADDR_V2_8822B) +#define BIT_CLEAR_WKFCAM_ADDR_V2_8822B(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8822B)) +#define BIT_GET_WKFCAM_ADDR_V2_8822B(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822B) & \ + BIT_MASK_WKFCAM_ADDR_V2_8822B) +#define BIT_SET_WKFCAM_ADDR_V2_8822B(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR_V2_8822B(x) | BIT_WKFCAM_ADDR_V2_8822B(v)) #define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B 0 #define BIT_MASK_WKFCAM_CAM_NUM_V1_8822B 0xff -#define BIT_WKFCAM_CAM_NUM_V1_8822B(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) -#define BIT_GET_WKFCAM_CAM_NUM_V1_8822B(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B) - - +#define BIT_WKFCAM_CAM_NUM_V1_8822B(x) \ + (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B) \ + << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) +#define BITS_WKFCAM_CAM_NUM_V1_8822B \ + (BIT_MASK_WKFCAM_CAM_NUM_V1_8822B << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822B(x) \ + ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8822B)) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8822B(x) \ + (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) & \ + BIT_MASK_WKFCAM_CAM_NUM_V1_8822B) +#define BIT_SET_WKFCAM_CAM_NUM_V1_8822B(x, v) \ + (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822B(x) | BIT_WKFCAM_CAM_NUM_V1_8822B(v)) /* 2 REG_WKFMCAM_RWD_8822B (WAKEUP FRAME READ/WRITE DATA) */ #define BIT_SHIFT_WKFMCAM_RWD_8822B 0 #define BIT_MASK_WKFMCAM_RWD_8822B 0xffffffffL -#define BIT_WKFMCAM_RWD_8822B(x) (((x) & BIT_MASK_WKFMCAM_RWD_8822B) << BIT_SHIFT_WKFMCAM_RWD_8822B) -#define BIT_GET_WKFMCAM_RWD_8822B(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8822B) & BIT_MASK_WKFMCAM_RWD_8822B) - - +#define BIT_WKFMCAM_RWD_8822B(x) \ + (((x) & BIT_MASK_WKFMCAM_RWD_8822B) << BIT_SHIFT_WKFMCAM_RWD_8822B) +#define BITS_WKFMCAM_RWD_8822B \ + (BIT_MASK_WKFMCAM_RWD_8822B << BIT_SHIFT_WKFMCAM_RWD_8822B) +#define BIT_CLEAR_WKFMCAM_RWD_8822B(x) ((x) & (~BITS_WKFMCAM_RWD_8822B)) +#define BIT_GET_WKFMCAM_RWD_8822B(x) \ + (((x) >> BIT_SHIFT_WKFMCAM_RWD_8822B) & BIT_MASK_WKFMCAM_RWD_8822B) +#define BIT_SET_WKFMCAM_RWD_8822B(x, v) \ + (BIT_CLEAR_WKFMCAM_RWD_8822B(x) | BIT_WKFMCAM_RWD_8822B(v)) /* 2 REG_RXFLTMAP1_8822B (RX FILTER MAP GROUP 1) */ #define BIT_CTRLFLT15EN_8822B BIT(15) @@ -9135,7 +14505,7 @@ /* 2 REG_NOT_VALID_8822B */ -/* 2 REG_RXFLTMAP_8822B (RX FILTER MAP GROUP 2) */ +/* 2 REG_RXFLTMAP2_8822B (RX FILTER MAP GROUP 2) */ #define BIT_DATAFLT15EN_8822B BIT(15) #define BIT_DATAFLT14EN_8822B BIT(14) #define BIT_DATAFLT13EN_8822B BIT(13) @@ -9157,26 +14527,42 @@ #define BIT_SHIFT_DTIM_CNT_8822B 24 #define BIT_MASK_DTIM_CNT_8822B 0xff -#define BIT_DTIM_CNT_8822B(x) (((x) & BIT_MASK_DTIM_CNT_8822B) << BIT_SHIFT_DTIM_CNT_8822B) -#define BIT_GET_DTIM_CNT_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT_8822B) & BIT_MASK_DTIM_CNT_8822B) - - +#define BIT_DTIM_CNT_8822B(x) \ + (((x) & BIT_MASK_DTIM_CNT_8822B) << BIT_SHIFT_DTIM_CNT_8822B) +#define BITS_DTIM_CNT_8822B \ + (BIT_MASK_DTIM_CNT_8822B << BIT_SHIFT_DTIM_CNT_8822B) +#define BIT_CLEAR_DTIM_CNT_8822B(x) ((x) & (~BITS_DTIM_CNT_8822B)) +#define BIT_GET_DTIM_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT_8822B) & BIT_MASK_DTIM_CNT_8822B) +#define BIT_SET_DTIM_CNT_8822B(x, v) \ + (BIT_CLEAR_DTIM_CNT_8822B(x) | BIT_DTIM_CNT_8822B(v)) #define BIT_SHIFT_DTIM_PERIOD_8822B 16 #define BIT_MASK_DTIM_PERIOD_8822B 0xff -#define BIT_DTIM_PERIOD_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD_8822B) << BIT_SHIFT_DTIM_PERIOD_8822B) -#define BIT_GET_DTIM_PERIOD_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8822B) & BIT_MASK_DTIM_PERIOD_8822B) - +#define BIT_DTIM_PERIOD_8822B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD_8822B) << BIT_SHIFT_DTIM_PERIOD_8822B) +#define BITS_DTIM_PERIOD_8822B \ + (BIT_MASK_DTIM_PERIOD_8822B << BIT_SHIFT_DTIM_PERIOD_8822B) +#define BIT_CLEAR_DTIM_PERIOD_8822B(x) ((x) & (~BITS_DTIM_PERIOD_8822B)) +#define BIT_GET_DTIM_PERIOD_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD_8822B) & BIT_MASK_DTIM_PERIOD_8822B) +#define BIT_SET_DTIM_PERIOD_8822B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD_8822B(x) | BIT_DTIM_PERIOD_8822B(v)) #define BIT_DTIM_8822B BIT(15) #define BIT_TIM_8822B BIT(14) #define BIT_SHIFT_PS_AID_0_8822B 0 #define BIT_MASK_PS_AID_0_8822B 0x7ff -#define BIT_PS_AID_0_8822B(x) (((x) & BIT_MASK_PS_AID_0_8822B) << BIT_SHIFT_PS_AID_0_8822B) -#define BIT_GET_PS_AID_0_8822B(x) (((x) >> BIT_SHIFT_PS_AID_0_8822B) & BIT_MASK_PS_AID_0_8822B) - - +#define BIT_PS_AID_0_8822B(x) \ + (((x) & BIT_MASK_PS_AID_0_8822B) << BIT_SHIFT_PS_AID_0_8822B) +#define BITS_PS_AID_0_8822B \ + (BIT_MASK_PS_AID_0_8822B << BIT_SHIFT_PS_AID_0_8822B) +#define BIT_CLEAR_PS_AID_0_8822B(x) ((x) & (~BITS_PS_AID_0_8822B)) +#define BIT_GET_PS_AID_0_8822B(x) \ + (((x) >> BIT_SHIFT_PS_AID_0_8822B) & BIT_MASK_PS_AID_0_8822B) +#define BIT_SET_PS_AID_0_8822B(x, v) \ + (BIT_CLEAR_PS_AID_0_8822B(x) | BIT_PS_AID_0_8822B(v)) /* 2 REG_FLC_TRPC_8822B (TIMER OF FLC_RPC) */ #define BIT_FLC_RPCT_V1_8822B BIT(7) @@ -9184,10 +14570,14 @@ #define BIT_SHIFT_TRPCD_8822B 0 #define BIT_MASK_TRPCD_8822B 0x3f -#define BIT_TRPCD_8822B(x) (((x) & BIT_MASK_TRPCD_8822B) << BIT_SHIFT_TRPCD_8822B) -#define BIT_GET_TRPCD_8822B(x) (((x) >> BIT_SHIFT_TRPCD_8822B) & BIT_MASK_TRPCD_8822B) - - +#define BIT_TRPCD_8822B(x) \ + (((x) & BIT_MASK_TRPCD_8822B) << BIT_SHIFT_TRPCD_8822B) +#define BITS_TRPCD_8822B (BIT_MASK_TRPCD_8822B << BIT_SHIFT_TRPCD_8822B) +#define BIT_CLEAR_TRPCD_8822B(x) ((x) & (~BITS_TRPCD_8822B)) +#define BIT_GET_TRPCD_8822B(x) \ + (((x) >> BIT_SHIFT_TRPCD_8822B) & BIT_MASK_TRPCD_8822B) +#define BIT_SET_TRPCD_8822B(x, v) \ + (BIT_CLEAR_TRPCD_8822B(x) | BIT_TRPCD_8822B(v)) /* 2 REG_FLC_PTS_8822B (PKT TYPE SELECTION OF FLC_RPC T) */ #define BIT_CMF_8822B BIT(2) @@ -9198,48 +14588,78 @@ #define BIT_SHIFT_FLC_RPCT_8822B 0 #define BIT_MASK_FLC_RPCT_8822B 0xff -#define BIT_FLC_RPCT_8822B(x) (((x) & BIT_MASK_FLC_RPCT_8822B) << BIT_SHIFT_FLC_RPCT_8822B) -#define BIT_GET_FLC_RPCT_8822B(x) (((x) >> BIT_SHIFT_FLC_RPCT_8822B) & BIT_MASK_FLC_RPCT_8822B) - - +#define BIT_FLC_RPCT_8822B(x) \ + (((x) & BIT_MASK_FLC_RPCT_8822B) << BIT_SHIFT_FLC_RPCT_8822B) +#define BITS_FLC_RPCT_8822B \ + (BIT_MASK_FLC_RPCT_8822B << BIT_SHIFT_FLC_RPCT_8822B) +#define BIT_CLEAR_FLC_RPCT_8822B(x) ((x) & (~BITS_FLC_RPCT_8822B)) +#define BIT_GET_FLC_RPCT_8822B(x) \ + (((x) >> BIT_SHIFT_FLC_RPCT_8822B) & BIT_MASK_FLC_RPCT_8822B) +#define BIT_SET_FLC_RPCT_8822B(x, v) \ + (BIT_CLEAR_FLC_RPCT_8822B(x) | BIT_FLC_RPCT_8822B(v)) /* 2 REG_FLC_RPC_8822B (FW LPS CONDITION -- RX PKT COUNTER) */ #define BIT_SHIFT_FLC_RPC_8822B 0 #define BIT_MASK_FLC_RPC_8822B 0xff -#define BIT_FLC_RPC_8822B(x) (((x) & BIT_MASK_FLC_RPC_8822B) << BIT_SHIFT_FLC_RPC_8822B) -#define BIT_GET_FLC_RPC_8822B(x) (((x) >> BIT_SHIFT_FLC_RPC_8822B) & BIT_MASK_FLC_RPC_8822B) - - +#define BIT_FLC_RPC_8822B(x) \ + (((x) & BIT_MASK_FLC_RPC_8822B) << BIT_SHIFT_FLC_RPC_8822B) +#define BITS_FLC_RPC_8822B (BIT_MASK_FLC_RPC_8822B << BIT_SHIFT_FLC_RPC_8822B) +#define BIT_CLEAR_FLC_RPC_8822B(x) ((x) & (~BITS_FLC_RPC_8822B)) +#define BIT_GET_FLC_RPC_8822B(x) \ + (((x) >> BIT_SHIFT_FLC_RPC_8822B) & BIT_MASK_FLC_RPC_8822B) +#define BIT_SET_FLC_RPC_8822B(x, v) \ + (BIT_CLEAR_FLC_RPC_8822B(x) | BIT_FLC_RPC_8822B(v)) /* 2 REG_RXPKTMON_CTRL_8822B */ #define BIT_SHIFT_RXBKQPKT_SEQ_8822B 20 #define BIT_MASK_RXBKQPKT_SEQ_8822B 0xf -#define BIT_RXBKQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8822B) << BIT_SHIFT_RXBKQPKT_SEQ_8822B) -#define BIT_GET_RXBKQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822B) & BIT_MASK_RXBKQPKT_SEQ_8822B) - - +#define BIT_RXBKQPKT_SEQ_8822B(x) \ + (((x) & BIT_MASK_RXBKQPKT_SEQ_8822B) << BIT_SHIFT_RXBKQPKT_SEQ_8822B) +#define BITS_RXBKQPKT_SEQ_8822B \ + (BIT_MASK_RXBKQPKT_SEQ_8822B << BIT_SHIFT_RXBKQPKT_SEQ_8822B) +#define BIT_CLEAR_RXBKQPKT_SEQ_8822B(x) ((x) & (~BITS_RXBKQPKT_SEQ_8822B)) +#define BIT_GET_RXBKQPKT_SEQ_8822B(x) \ + (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822B) & BIT_MASK_RXBKQPKT_SEQ_8822B) +#define BIT_SET_RXBKQPKT_SEQ_8822B(x, v) \ + (BIT_CLEAR_RXBKQPKT_SEQ_8822B(x) | BIT_RXBKQPKT_SEQ_8822B(v)) #define BIT_SHIFT_RXBEQPKT_SEQ_8822B 16 #define BIT_MASK_RXBEQPKT_SEQ_8822B 0xf -#define BIT_RXBEQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8822B) << BIT_SHIFT_RXBEQPKT_SEQ_8822B) -#define BIT_GET_RXBEQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822B) & BIT_MASK_RXBEQPKT_SEQ_8822B) - - +#define BIT_RXBEQPKT_SEQ_8822B(x) \ + (((x) & BIT_MASK_RXBEQPKT_SEQ_8822B) << BIT_SHIFT_RXBEQPKT_SEQ_8822B) +#define BITS_RXBEQPKT_SEQ_8822B \ + (BIT_MASK_RXBEQPKT_SEQ_8822B << BIT_SHIFT_RXBEQPKT_SEQ_8822B) +#define BIT_CLEAR_RXBEQPKT_SEQ_8822B(x) ((x) & (~BITS_RXBEQPKT_SEQ_8822B)) +#define BIT_GET_RXBEQPKT_SEQ_8822B(x) \ + (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822B) & BIT_MASK_RXBEQPKT_SEQ_8822B) +#define BIT_SET_RXBEQPKT_SEQ_8822B(x, v) \ + (BIT_CLEAR_RXBEQPKT_SEQ_8822B(x) | BIT_RXBEQPKT_SEQ_8822B(v)) #define BIT_SHIFT_RXVIQPKT_SEQ_8822B 12 #define BIT_MASK_RXVIQPKT_SEQ_8822B 0xf -#define BIT_RXVIQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8822B) << BIT_SHIFT_RXVIQPKT_SEQ_8822B) -#define BIT_GET_RXVIQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822B) & BIT_MASK_RXVIQPKT_SEQ_8822B) - - +#define BIT_RXVIQPKT_SEQ_8822B(x) \ + (((x) & BIT_MASK_RXVIQPKT_SEQ_8822B) << BIT_SHIFT_RXVIQPKT_SEQ_8822B) +#define BITS_RXVIQPKT_SEQ_8822B \ + (BIT_MASK_RXVIQPKT_SEQ_8822B << BIT_SHIFT_RXVIQPKT_SEQ_8822B) +#define BIT_CLEAR_RXVIQPKT_SEQ_8822B(x) ((x) & (~BITS_RXVIQPKT_SEQ_8822B)) +#define BIT_GET_RXVIQPKT_SEQ_8822B(x) \ + (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822B) & BIT_MASK_RXVIQPKT_SEQ_8822B) +#define BIT_SET_RXVIQPKT_SEQ_8822B(x, v) \ + (BIT_CLEAR_RXVIQPKT_SEQ_8822B(x) | BIT_RXVIQPKT_SEQ_8822B(v)) #define BIT_SHIFT_RXVOQPKT_SEQ_8822B 8 #define BIT_MASK_RXVOQPKT_SEQ_8822B 0xf -#define BIT_RXVOQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8822B) << BIT_SHIFT_RXVOQPKT_SEQ_8822B) -#define BIT_GET_RXVOQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822B) & BIT_MASK_RXVOQPKT_SEQ_8822B) - +#define BIT_RXVOQPKT_SEQ_8822B(x) \ + (((x) & BIT_MASK_RXVOQPKT_SEQ_8822B) << BIT_SHIFT_RXVOQPKT_SEQ_8822B) +#define BITS_RXVOQPKT_SEQ_8822B \ + (BIT_MASK_RXVOQPKT_SEQ_8822B << BIT_SHIFT_RXVOQPKT_SEQ_8822B) +#define BIT_CLEAR_RXVOQPKT_SEQ_8822B(x) ((x) & (~BITS_RXVOQPKT_SEQ_8822B)) +#define BIT_GET_RXVOQPKT_SEQ_8822B(x) \ + (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822B) & BIT_MASK_RXVOQPKT_SEQ_8822B) +#define BIT_SET_RXVOQPKT_SEQ_8822B(x, v) \ + (BIT_CLEAR_RXVOQPKT_SEQ_8822B(x) | BIT_RXVOQPKT_SEQ_8822B(v)) #define BIT_RXBKQPKT_ERR_8822B BIT(7) #define BIT_RXBEQPKT_ERR_8822B BIT(6) @@ -9253,25 +14673,41 @@ #define BIT_SHIFT_STATE_SEL_8822B 24 #define BIT_MASK_STATE_SEL_8822B 0x1f -#define BIT_STATE_SEL_8822B(x) (((x) & BIT_MASK_STATE_SEL_8822B) << BIT_SHIFT_STATE_SEL_8822B) -#define BIT_GET_STATE_SEL_8822B(x) (((x) >> BIT_SHIFT_STATE_SEL_8822B) & BIT_MASK_STATE_SEL_8822B) - - +#define BIT_STATE_SEL_8822B(x) \ + (((x) & BIT_MASK_STATE_SEL_8822B) << BIT_SHIFT_STATE_SEL_8822B) +#define BITS_STATE_SEL_8822B \ + (BIT_MASK_STATE_SEL_8822B << BIT_SHIFT_STATE_SEL_8822B) +#define BIT_CLEAR_STATE_SEL_8822B(x) ((x) & (~BITS_STATE_SEL_8822B)) +#define BIT_GET_STATE_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_STATE_SEL_8822B) & BIT_MASK_STATE_SEL_8822B) +#define BIT_SET_STATE_SEL_8822B(x, v) \ + (BIT_CLEAR_STATE_SEL_8822B(x) | BIT_STATE_SEL_8822B(v)) #define BIT_SHIFT_STATE_INFO_8822B 8 #define BIT_MASK_STATE_INFO_8822B 0xff -#define BIT_STATE_INFO_8822B(x) (((x) & BIT_MASK_STATE_INFO_8822B) << BIT_SHIFT_STATE_INFO_8822B) -#define BIT_GET_STATE_INFO_8822B(x) (((x) >> BIT_SHIFT_STATE_INFO_8822B) & BIT_MASK_STATE_INFO_8822B) - +#define BIT_STATE_INFO_8822B(x) \ + (((x) & BIT_MASK_STATE_INFO_8822B) << BIT_SHIFT_STATE_INFO_8822B) +#define BITS_STATE_INFO_8822B \ + (BIT_MASK_STATE_INFO_8822B << BIT_SHIFT_STATE_INFO_8822B) +#define BIT_CLEAR_STATE_INFO_8822B(x) ((x) & (~BITS_STATE_INFO_8822B)) +#define BIT_GET_STATE_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_STATE_INFO_8822B) & BIT_MASK_STATE_INFO_8822B) +#define BIT_SET_STATE_INFO_8822B(x, v) \ + (BIT_CLEAR_STATE_INFO_8822B(x) | BIT_STATE_INFO_8822B(v)) #define BIT_UPD_NXT_STATE_8822B BIT(7) #define BIT_SHIFT_CUR_STATE_8822B 0 #define BIT_MASK_CUR_STATE_8822B 0x7f -#define BIT_CUR_STATE_8822B(x) (((x) & BIT_MASK_CUR_STATE_8822B) << BIT_SHIFT_CUR_STATE_8822B) -#define BIT_GET_CUR_STATE_8822B(x) (((x) >> BIT_SHIFT_CUR_STATE_8822B) & BIT_MASK_CUR_STATE_8822B) - - +#define BIT_CUR_STATE_8822B(x) \ + (((x) & BIT_MASK_CUR_STATE_8822B) << BIT_SHIFT_CUR_STATE_8822B) +#define BITS_CUR_STATE_8822B \ + (BIT_MASK_CUR_STATE_8822B << BIT_SHIFT_CUR_STATE_8822B) +#define BIT_CLEAR_CUR_STATE_8822B(x) ((x) & (~BITS_CUR_STATE_8822B)) +#define BIT_GET_CUR_STATE_8822B(x) \ + (((x) >> BIT_SHIFT_CUR_STATE_8822B) & BIT_MASK_CUR_STATE_8822B) +#define BIT_SET_CUR_STATE_8822B(x, v) \ + (BIT_CLEAR_CUR_STATE_8822B(x) | BIT_CUR_STATE_8822B(v)) /* 2 REG_ERROR_MON_8822B */ #define BIT_MACRX_ERR_1_8822B BIT(17) @@ -9286,9 +14722,18 @@ #define BIT_SHIFT_INFO_INDEX_OFFSET_8822B 16 #define BIT_MASK_INFO_INDEX_OFFSET_8822B 0x1fff -#define BIT_INFO_INDEX_OFFSET_8822B(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8822B) << BIT_SHIFT_INFO_INDEX_OFFSET_8822B) -#define BIT_GET_INFO_INDEX_OFFSET_8822B(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822B) & BIT_MASK_INFO_INDEX_OFFSET_8822B) - +#define BIT_INFO_INDEX_OFFSET_8822B(x) \ + (((x) & BIT_MASK_INFO_INDEX_OFFSET_8822B) \ + << BIT_SHIFT_INFO_INDEX_OFFSET_8822B) +#define BITS_INFO_INDEX_OFFSET_8822B \ + (BIT_MASK_INFO_INDEX_OFFSET_8822B << BIT_SHIFT_INFO_INDEX_OFFSET_8822B) +#define BIT_CLEAR_INFO_INDEX_OFFSET_8822B(x) \ + ((x) & (~BITS_INFO_INDEX_OFFSET_8822B)) +#define BIT_GET_INFO_INDEX_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822B) & \ + BIT_MASK_INFO_INDEX_OFFSET_8822B) +#define BIT_SET_INFO_INDEX_OFFSET_8822B(x, v) \ + (BIT_CLEAR_INFO_INDEX_OFFSET_8822B(x) | BIT_INFO_INDEX_OFFSET_8822B(v)) #define BIT_WMAC_SRCH_FIFOFULL_8822B BIT(15) #define BIT_DIS_INFOSRCH_8822B BIT(14) @@ -9296,10 +14741,18 @@ #define BIT_SHIFT_INFO_ADDR_OFFSET_8822B 0 #define BIT_MASK_INFO_ADDR_OFFSET_8822B 0x1fff -#define BIT_INFO_ADDR_OFFSET_8822B(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8822B) << BIT_SHIFT_INFO_ADDR_OFFSET_8822B) -#define BIT_GET_INFO_ADDR_OFFSET_8822B(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822B) & BIT_MASK_INFO_ADDR_OFFSET_8822B) - - +#define BIT_INFO_ADDR_OFFSET_8822B(x) \ + (((x) & BIT_MASK_INFO_ADDR_OFFSET_8822B) \ + << BIT_SHIFT_INFO_ADDR_OFFSET_8822B) +#define BITS_INFO_ADDR_OFFSET_8822B \ + (BIT_MASK_INFO_ADDR_OFFSET_8822B << BIT_SHIFT_INFO_ADDR_OFFSET_8822B) +#define BIT_CLEAR_INFO_ADDR_OFFSET_8822B(x) \ + ((x) & (~BITS_INFO_ADDR_OFFSET_8822B)) +#define BIT_GET_INFO_ADDR_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822B) & \ + BIT_MASK_INFO_ADDR_OFFSET_8822B) +#define BIT_SET_INFO_ADDR_OFFSET_8822B(x, v) \ + (BIT_CLEAR_INFO_ADDR_OFFSET_8822B(x) | BIT_INFO_ADDR_OFFSET_8822B(v)) /* 2 REG_BT_COEX_TABLE_8822B (BT-COEXISTENCE CONTROL REGISTER) */ #define BIT_PRI_MASK_RX_RESP_8822B BIT(126) @@ -9308,16 +14761,27 @@ #define BIT_SHIFT_PRI_MASK_TXAC_8822B (117 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_TXAC_8822B 0x7f -#define BIT_PRI_MASK_TXAC_8822B(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8822B) << BIT_SHIFT_PRI_MASK_TXAC_8822B) -#define BIT_GET_PRI_MASK_TXAC_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822B) & BIT_MASK_PRI_MASK_TXAC_8822B) - - +#define BIT_PRI_MASK_TXAC_8822B(x) \ + (((x) & BIT_MASK_PRI_MASK_TXAC_8822B) << BIT_SHIFT_PRI_MASK_TXAC_8822B) +#define BITS_PRI_MASK_TXAC_8822B \ + (BIT_MASK_PRI_MASK_TXAC_8822B << BIT_SHIFT_PRI_MASK_TXAC_8822B) +#define BIT_CLEAR_PRI_MASK_TXAC_8822B(x) ((x) & (~BITS_PRI_MASK_TXAC_8822B)) +#define BIT_GET_PRI_MASK_TXAC_8822B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822B) & BIT_MASK_PRI_MASK_TXAC_8822B) +#define BIT_SET_PRI_MASK_TXAC_8822B(x, v) \ + (BIT_CLEAR_PRI_MASK_TXAC_8822B(x) | BIT_PRI_MASK_TXAC_8822B(v)) #define BIT_SHIFT_PRI_MASK_NAV_8822B (109 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_NAV_8822B 0xff -#define BIT_PRI_MASK_NAV_8822B(x) (((x) & BIT_MASK_PRI_MASK_NAV_8822B) << BIT_SHIFT_PRI_MASK_NAV_8822B) -#define BIT_GET_PRI_MASK_NAV_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8822B) & BIT_MASK_PRI_MASK_NAV_8822B) - +#define BIT_PRI_MASK_NAV_8822B(x) \ + (((x) & BIT_MASK_PRI_MASK_NAV_8822B) << BIT_SHIFT_PRI_MASK_NAV_8822B) +#define BITS_PRI_MASK_NAV_8822B \ + (BIT_MASK_PRI_MASK_NAV_8822B << BIT_SHIFT_PRI_MASK_NAV_8822B) +#define BIT_CLEAR_PRI_MASK_NAV_8822B(x) ((x) & (~BITS_PRI_MASK_NAV_8822B)) +#define BIT_GET_PRI_MASK_NAV_8822B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NAV_8822B) & BIT_MASK_PRI_MASK_NAV_8822B) +#define BIT_SET_PRI_MASK_NAV_8822B(x, v) \ + (BIT_CLEAR_PRI_MASK_NAV_8822B(x) | BIT_PRI_MASK_NAV_8822B(v)) #define BIT_PRI_MASK_CCK_8822B BIT(108) #define BIT_PRI_MASK_OFDM_8822B BIT(107) @@ -9325,66 +14789,107 @@ #define BIT_SHIFT_PRI_MASK_NUM_8822B (102 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_NUM_8822B 0xf -#define BIT_PRI_MASK_NUM_8822B(x) (((x) & BIT_MASK_PRI_MASK_NUM_8822B) << BIT_SHIFT_PRI_MASK_NUM_8822B) -#define BIT_GET_PRI_MASK_NUM_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8822B) & BIT_MASK_PRI_MASK_NUM_8822B) - - +#define BIT_PRI_MASK_NUM_8822B(x) \ + (((x) & BIT_MASK_PRI_MASK_NUM_8822B) << BIT_SHIFT_PRI_MASK_NUM_8822B) +#define BITS_PRI_MASK_NUM_8822B \ + (BIT_MASK_PRI_MASK_NUM_8822B << BIT_SHIFT_PRI_MASK_NUM_8822B) +#define BIT_CLEAR_PRI_MASK_NUM_8822B(x) ((x) & (~BITS_PRI_MASK_NUM_8822B)) +#define BIT_GET_PRI_MASK_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NUM_8822B) & BIT_MASK_PRI_MASK_NUM_8822B) +#define BIT_SET_PRI_MASK_NUM_8822B(x, v) \ + (BIT_CLEAR_PRI_MASK_NUM_8822B(x) | BIT_PRI_MASK_NUM_8822B(v)) #define BIT_SHIFT_PRI_MASK_TYPE_8822B (98 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_TYPE_8822B 0xf -#define BIT_PRI_MASK_TYPE_8822B(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8822B) << BIT_SHIFT_PRI_MASK_TYPE_8822B) -#define BIT_GET_PRI_MASK_TYPE_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822B) & BIT_MASK_PRI_MASK_TYPE_8822B) - +#define BIT_PRI_MASK_TYPE_8822B(x) \ + (((x) & BIT_MASK_PRI_MASK_TYPE_8822B) << BIT_SHIFT_PRI_MASK_TYPE_8822B) +#define BITS_PRI_MASK_TYPE_8822B \ + (BIT_MASK_PRI_MASK_TYPE_8822B << BIT_SHIFT_PRI_MASK_TYPE_8822B) +#define BIT_CLEAR_PRI_MASK_TYPE_8822B(x) ((x) & (~BITS_PRI_MASK_TYPE_8822B)) +#define BIT_GET_PRI_MASK_TYPE_8822B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822B) & BIT_MASK_PRI_MASK_TYPE_8822B) +#define BIT_SET_PRI_MASK_TYPE_8822B(x, v) \ + (BIT_CLEAR_PRI_MASK_TYPE_8822B(x) | BIT_PRI_MASK_TYPE_8822B(v)) #define BIT_OOB_8822B BIT(97) #define BIT_ANT_SEL_8822B BIT(96) #define BIT_SHIFT_BREAK_TABLE_2_8822B (80 & CPU_OPT_WIDTH) #define BIT_MASK_BREAK_TABLE_2_8822B 0xffff -#define BIT_BREAK_TABLE_2_8822B(x) (((x) & BIT_MASK_BREAK_TABLE_2_8822B) << BIT_SHIFT_BREAK_TABLE_2_8822B) -#define BIT_GET_BREAK_TABLE_2_8822B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8822B) & BIT_MASK_BREAK_TABLE_2_8822B) - - +#define BIT_BREAK_TABLE_2_8822B(x) \ + (((x) & BIT_MASK_BREAK_TABLE_2_8822B) << BIT_SHIFT_BREAK_TABLE_2_8822B) +#define BITS_BREAK_TABLE_2_8822B \ + (BIT_MASK_BREAK_TABLE_2_8822B << BIT_SHIFT_BREAK_TABLE_2_8822B) +#define BIT_CLEAR_BREAK_TABLE_2_8822B(x) ((x) & (~BITS_BREAK_TABLE_2_8822B)) +#define BIT_GET_BREAK_TABLE_2_8822B(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_2_8822B) & BIT_MASK_BREAK_TABLE_2_8822B) +#define BIT_SET_BREAK_TABLE_2_8822B(x, v) \ + (BIT_CLEAR_BREAK_TABLE_2_8822B(x) | BIT_BREAK_TABLE_2_8822B(v)) #define BIT_SHIFT_BREAK_TABLE_1_8822B (64 & CPU_OPT_WIDTH) #define BIT_MASK_BREAK_TABLE_1_8822B 0xffff -#define BIT_BREAK_TABLE_1_8822B(x) (((x) & BIT_MASK_BREAK_TABLE_1_8822B) << BIT_SHIFT_BREAK_TABLE_1_8822B) -#define BIT_GET_BREAK_TABLE_1_8822B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8822B) & BIT_MASK_BREAK_TABLE_1_8822B) - - +#define BIT_BREAK_TABLE_1_8822B(x) \ + (((x) & BIT_MASK_BREAK_TABLE_1_8822B) << BIT_SHIFT_BREAK_TABLE_1_8822B) +#define BITS_BREAK_TABLE_1_8822B \ + (BIT_MASK_BREAK_TABLE_1_8822B << BIT_SHIFT_BREAK_TABLE_1_8822B) +#define BIT_CLEAR_BREAK_TABLE_1_8822B(x) ((x) & (~BITS_BREAK_TABLE_1_8822B)) +#define BIT_GET_BREAK_TABLE_1_8822B(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_1_8822B) & BIT_MASK_BREAK_TABLE_1_8822B) +#define BIT_SET_BREAK_TABLE_1_8822B(x, v) \ + (BIT_CLEAR_BREAK_TABLE_1_8822B(x) | BIT_BREAK_TABLE_1_8822B(v)) #define BIT_SHIFT_COEX_TABLE_2_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_COEX_TABLE_2_8822B 0xffffffffL -#define BIT_COEX_TABLE_2_8822B(x) (((x) & BIT_MASK_COEX_TABLE_2_8822B) << BIT_SHIFT_COEX_TABLE_2_8822B) -#define BIT_GET_COEX_TABLE_2_8822B(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8822B) & BIT_MASK_COEX_TABLE_2_8822B) - - +#define BIT_COEX_TABLE_2_8822B(x) \ + (((x) & BIT_MASK_COEX_TABLE_2_8822B) << BIT_SHIFT_COEX_TABLE_2_8822B) +#define BITS_COEX_TABLE_2_8822B \ + (BIT_MASK_COEX_TABLE_2_8822B << BIT_SHIFT_COEX_TABLE_2_8822B) +#define BIT_CLEAR_COEX_TABLE_2_8822B(x) ((x) & (~BITS_COEX_TABLE_2_8822B)) +#define BIT_GET_COEX_TABLE_2_8822B(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_2_8822B) & BIT_MASK_COEX_TABLE_2_8822B) +#define BIT_SET_COEX_TABLE_2_8822B(x, v) \ + (BIT_CLEAR_COEX_TABLE_2_8822B(x) | BIT_COEX_TABLE_2_8822B(v)) #define BIT_SHIFT_COEX_TABLE_1_8822B 0 #define BIT_MASK_COEX_TABLE_1_8822B 0xffffffffL -#define BIT_COEX_TABLE_1_8822B(x) (((x) & BIT_MASK_COEX_TABLE_1_8822B) << BIT_SHIFT_COEX_TABLE_1_8822B) -#define BIT_GET_COEX_TABLE_1_8822B(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8822B) & BIT_MASK_COEX_TABLE_1_8822B) - - +#define BIT_COEX_TABLE_1_8822B(x) \ + (((x) & BIT_MASK_COEX_TABLE_1_8822B) << BIT_SHIFT_COEX_TABLE_1_8822B) +#define BITS_COEX_TABLE_1_8822B \ + (BIT_MASK_COEX_TABLE_1_8822B << BIT_SHIFT_COEX_TABLE_1_8822B) +#define BIT_CLEAR_COEX_TABLE_1_8822B(x) ((x) & (~BITS_COEX_TABLE_1_8822B)) +#define BIT_GET_COEX_TABLE_1_8822B(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_1_8822B) & BIT_MASK_COEX_TABLE_1_8822B) +#define BIT_SET_COEX_TABLE_1_8822B(x, v) \ + (BIT_CLEAR_COEX_TABLE_1_8822B(x) | BIT_COEX_TABLE_1_8822B(v)) /* 2 REG_RXCMD_0_8822B */ #define BIT_RXCMD_EN_8822B BIT(31) #define BIT_SHIFT_RXCMD_INFO_8822B 0 #define BIT_MASK_RXCMD_INFO_8822B 0x7fffffffL -#define BIT_RXCMD_INFO_8822B(x) (((x) & BIT_MASK_RXCMD_INFO_8822B) << BIT_SHIFT_RXCMD_INFO_8822B) -#define BIT_GET_RXCMD_INFO_8822B(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8822B) & BIT_MASK_RXCMD_INFO_8822B) - - +#define BIT_RXCMD_INFO_8822B(x) \ + (((x) & BIT_MASK_RXCMD_INFO_8822B) << BIT_SHIFT_RXCMD_INFO_8822B) +#define BITS_RXCMD_INFO_8822B \ + (BIT_MASK_RXCMD_INFO_8822B << BIT_SHIFT_RXCMD_INFO_8822B) +#define BIT_CLEAR_RXCMD_INFO_8822B(x) ((x) & (~BITS_RXCMD_INFO_8822B)) +#define BIT_GET_RXCMD_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_RXCMD_INFO_8822B) & BIT_MASK_RXCMD_INFO_8822B) +#define BIT_SET_RXCMD_INFO_8822B(x, v) \ + (BIT_CLEAR_RXCMD_INFO_8822B(x) | BIT_RXCMD_INFO_8822B(v)) /* 2 REG_RXCMD_1_8822B */ #define BIT_SHIFT_RXCMD_PRD_8822B 0 #define BIT_MASK_RXCMD_PRD_8822B 0xffff -#define BIT_RXCMD_PRD_8822B(x) (((x) & BIT_MASK_RXCMD_PRD_8822B) << BIT_SHIFT_RXCMD_PRD_8822B) -#define BIT_GET_RXCMD_PRD_8822B(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8822B) & BIT_MASK_RXCMD_PRD_8822B) - - +#define BIT_RXCMD_PRD_8822B(x) \ + (((x) & BIT_MASK_RXCMD_PRD_8822B) << BIT_SHIFT_RXCMD_PRD_8822B) +#define BITS_RXCMD_PRD_8822B \ + (BIT_MASK_RXCMD_PRD_8822B << BIT_SHIFT_RXCMD_PRD_8822B) +#define BIT_CLEAR_RXCMD_PRD_8822B(x) ((x) & (~BITS_RXCMD_PRD_8822B)) +#define BIT_GET_RXCMD_PRD_8822B(x) \ + (((x) >> BIT_SHIFT_RXCMD_PRD_8822B) & BIT_MASK_RXCMD_PRD_8822B) +#define BIT_SET_RXCMD_PRD_8822B(x, v) \ + (BIT_CLEAR_RXCMD_PRD_8822B(x) | BIT_RXCMD_PRD_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -9392,38 +14897,74 @@ #define BIT_SHIFT_WMAC_RESP_MFB_8822B 25 #define BIT_MASK_WMAC_RESP_MFB_8822B 0x7f -#define BIT_WMAC_RESP_MFB_8822B(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8822B) << BIT_SHIFT_WMAC_RESP_MFB_8822B) -#define BIT_GET_WMAC_RESP_MFB_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822B) & BIT_MASK_WMAC_RESP_MFB_8822B) - - +#define BIT_WMAC_RESP_MFB_8822B(x) \ + (((x) & BIT_MASK_WMAC_RESP_MFB_8822B) << BIT_SHIFT_WMAC_RESP_MFB_8822B) +#define BITS_WMAC_RESP_MFB_8822B \ + (BIT_MASK_WMAC_RESP_MFB_8822B << BIT_SHIFT_WMAC_RESP_MFB_8822B) +#define BIT_CLEAR_WMAC_RESP_MFB_8822B(x) ((x) & (~BITS_WMAC_RESP_MFB_8822B)) +#define BIT_GET_WMAC_RESP_MFB_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822B) & BIT_MASK_WMAC_RESP_MFB_8822B) +#define BIT_SET_WMAC_RESP_MFB_8822B(x, v) \ + (BIT_CLEAR_WMAC_RESP_MFB_8822B(x) | BIT_WMAC_RESP_MFB_8822B(v)) #define BIT_SHIFT_WMAC_ANTINF_SEL_8822B 23 #define BIT_MASK_WMAC_ANTINF_SEL_8822B 0x3 -#define BIT_WMAC_ANTINF_SEL_8822B(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8822B) << BIT_SHIFT_WMAC_ANTINF_SEL_8822B) -#define BIT_GET_WMAC_ANTINF_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822B) & BIT_MASK_WMAC_ANTINF_SEL_8822B) - - +#define BIT_WMAC_ANTINF_SEL_8822B(x) \ + (((x) & BIT_MASK_WMAC_ANTINF_SEL_8822B) \ + << BIT_SHIFT_WMAC_ANTINF_SEL_8822B) +#define BITS_WMAC_ANTINF_SEL_8822B \ + (BIT_MASK_WMAC_ANTINF_SEL_8822B << BIT_SHIFT_WMAC_ANTINF_SEL_8822B) +#define BIT_CLEAR_WMAC_ANTINF_SEL_8822B(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8822B)) +#define BIT_GET_WMAC_ANTINF_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822B) & \ + BIT_MASK_WMAC_ANTINF_SEL_8822B) +#define BIT_SET_WMAC_ANTINF_SEL_8822B(x, v) \ + (BIT_CLEAR_WMAC_ANTINF_SEL_8822B(x) | BIT_WMAC_ANTINF_SEL_8822B(v)) #define BIT_SHIFT_WMAC_ANTSEL_SEL_8822B 21 #define BIT_MASK_WMAC_ANTSEL_SEL_8822B 0x3 -#define BIT_WMAC_ANTSEL_SEL_8822B(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822B) << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) -#define BIT_GET_WMAC_ANTSEL_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) & BIT_MASK_WMAC_ANTSEL_SEL_8822B) - - +#define BIT_WMAC_ANTSEL_SEL_8822B(x) \ + (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822B) \ + << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) +#define BITS_WMAC_ANTSEL_SEL_8822B \ + (BIT_MASK_WMAC_ANTSEL_SEL_8822B << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) +#define BIT_CLEAR_WMAC_ANTSEL_SEL_8822B(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8822B)) +#define BIT_GET_WMAC_ANTSEL_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) & \ + BIT_MASK_WMAC_ANTSEL_SEL_8822B) +#define BIT_SET_WMAC_ANTSEL_SEL_8822B(x, v) \ + (BIT_CLEAR_WMAC_ANTSEL_SEL_8822B(x) | BIT_WMAC_ANTSEL_SEL_8822B(v)) #define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B 18 #define BIT_MASK_R_WMAC_RESP_TXPOWER_8822B 0x7 -#define BIT_R_WMAC_RESP_TXPOWER_8822B(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) -#define BIT_GET_R_WMAC_RESP_TXPOWER_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) - - +#define BIT_R_WMAC_RESP_TXPOWER_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) \ + << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) +#define BITS_R_WMAC_RESP_TXPOWER_8822B \ + (BIT_MASK_R_WMAC_RESP_TXPOWER_8822B \ + << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) +#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8822B(x) \ + ((x) & (~BITS_R_WMAC_RESP_TXPOWER_8822B)) +#define BIT_GET_R_WMAC_RESP_TXPOWER_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) & \ + BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) +#define BIT_SET_R_WMAC_RESP_TXPOWER_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_RESP_TXPOWER_8822B(x) | \ + BIT_R_WMAC_RESP_TXPOWER_8822B(v)) #define BIT_SHIFT_WMAC_RESP_TXANT_8822B 0 #define BIT_MASK_WMAC_RESP_TXANT_8822B 0x3ffff -#define BIT_WMAC_RESP_TXANT_8822B(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8822B) << BIT_SHIFT_WMAC_RESP_TXANT_8822B) -#define BIT_GET_WMAC_RESP_TXANT_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8822B) & BIT_MASK_WMAC_RESP_TXANT_8822B) - - +#define BIT_WMAC_RESP_TXANT_8822B(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT_8822B) \ + << BIT_SHIFT_WMAC_RESP_TXANT_8822B) +#define BITS_WMAC_RESP_TXANT_8822B \ + (BIT_MASK_WMAC_RESP_TXANT_8822B << BIT_SHIFT_WMAC_RESP_TXANT_8822B) +#define BIT_CLEAR_WMAC_RESP_TXANT_8822B(x) ((x) & (~BITS_WMAC_RESP_TXANT_8822B)) +#define BIT_GET_WMAC_RESP_TXANT_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8822B) & \ + BIT_MASK_WMAC_RESP_TXANT_8822B) +#define BIT_SET_WMAC_RESP_TXANT_8822B(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT_8822B(x) | BIT_WMAC_RESP_TXANT_8822B(v)) /* 2 REG_BBPSF_CTRL_8822B */ #define BIT_CTL_IDLE_CLR_CSI_RPT_8822B BIT(31) @@ -9431,16 +14972,30 @@ #define BIT_SHIFT_WMAC_CSI_RATE_8822B 24 #define BIT_MASK_WMAC_CSI_RATE_8822B 0x3f -#define BIT_WMAC_CSI_RATE_8822B(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8822B) << BIT_SHIFT_WMAC_CSI_RATE_8822B) -#define BIT_GET_WMAC_CSI_RATE_8822B(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822B) & BIT_MASK_WMAC_CSI_RATE_8822B) - - +#define BIT_WMAC_CSI_RATE_8822B(x) \ + (((x) & BIT_MASK_WMAC_CSI_RATE_8822B) << BIT_SHIFT_WMAC_CSI_RATE_8822B) +#define BITS_WMAC_CSI_RATE_8822B \ + (BIT_MASK_WMAC_CSI_RATE_8822B << BIT_SHIFT_WMAC_CSI_RATE_8822B) +#define BIT_CLEAR_WMAC_CSI_RATE_8822B(x) ((x) & (~BITS_WMAC_CSI_RATE_8822B)) +#define BIT_GET_WMAC_CSI_RATE_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822B) & BIT_MASK_WMAC_CSI_RATE_8822B) +#define BIT_SET_WMAC_CSI_RATE_8822B(x, v) \ + (BIT_CLEAR_WMAC_CSI_RATE_8822B(x) | BIT_WMAC_CSI_RATE_8822B(v)) #define BIT_SHIFT_WMAC_RESP_TXRATE_8822B 16 #define BIT_MASK_WMAC_RESP_TXRATE_8822B 0xff -#define BIT_WMAC_RESP_TXRATE_8822B(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8822B) << BIT_SHIFT_WMAC_RESP_TXRATE_8822B) -#define BIT_GET_WMAC_RESP_TXRATE_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822B) & BIT_MASK_WMAC_RESP_TXRATE_8822B) - +#define BIT_WMAC_RESP_TXRATE_8822B(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXRATE_8822B) \ + << BIT_SHIFT_WMAC_RESP_TXRATE_8822B) +#define BITS_WMAC_RESP_TXRATE_8822B \ + (BIT_MASK_WMAC_RESP_TXRATE_8822B << BIT_SHIFT_WMAC_RESP_TXRATE_8822B) +#define BIT_CLEAR_WMAC_RESP_TXRATE_8822B(x) \ + ((x) & (~BITS_WMAC_RESP_TXRATE_8822B)) +#define BIT_GET_WMAC_RESP_TXRATE_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822B) & \ + BIT_MASK_WMAC_RESP_TXRATE_8822B) +#define BIT_SET_WMAC_RESP_TXRATE_8822B(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXRATE_8822B(x) | BIT_WMAC_RESP_TXRATE_8822B(v)) #define BIT_BBPSF_MPDUCHKEN_8822B BIT(5) #define BIT_BBPSF_MHCHKEN_8822B BIT(4) @@ -9448,10 +15003,15 @@ #define BIT_SHIFT_BBPSF_ERRTHR_8822B 0 #define BIT_MASK_BBPSF_ERRTHR_8822B 0x7 -#define BIT_BBPSF_ERRTHR_8822B(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8822B) << BIT_SHIFT_BBPSF_ERRTHR_8822B) -#define BIT_GET_BBPSF_ERRTHR_8822B(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8822B) & BIT_MASK_BBPSF_ERRTHR_8822B) - - +#define BIT_BBPSF_ERRTHR_8822B(x) \ + (((x) & BIT_MASK_BBPSF_ERRTHR_8822B) << BIT_SHIFT_BBPSF_ERRTHR_8822B) +#define BITS_BBPSF_ERRTHR_8822B \ + (BIT_MASK_BBPSF_ERRTHR_8822B << BIT_SHIFT_BBPSF_ERRTHR_8822B) +#define BIT_CLEAR_BBPSF_ERRTHR_8822B(x) ((x) & (~BITS_BBPSF_ERRTHR_8822B)) +#define BIT_GET_BBPSF_ERRTHR_8822B(x) \ + (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8822B) & BIT_MASK_BBPSF_ERRTHR_8822B) +#define BIT_SET_BBPSF_ERRTHR_8822B(x, v) \ + (BIT_CLEAR_BBPSF_ERRTHR_8822B(x) | BIT_BBPSF_ERRTHR_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -9461,67 +15021,135 @@ #define BIT_SHIFT_P2P_OUI_TYPE_8822B 0 #define BIT_MASK_P2P_OUI_TYPE_8822B 0xff -#define BIT_P2P_OUI_TYPE_8822B(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8822B) << BIT_SHIFT_P2P_OUI_TYPE_8822B) -#define BIT_GET_P2P_OUI_TYPE_8822B(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822B) & BIT_MASK_P2P_OUI_TYPE_8822B) - - +#define BIT_P2P_OUI_TYPE_8822B(x) \ + (((x) & BIT_MASK_P2P_OUI_TYPE_8822B) << BIT_SHIFT_P2P_OUI_TYPE_8822B) +#define BITS_P2P_OUI_TYPE_8822B \ + (BIT_MASK_P2P_OUI_TYPE_8822B << BIT_SHIFT_P2P_OUI_TYPE_8822B) +#define BIT_CLEAR_P2P_OUI_TYPE_8822B(x) ((x) & (~BITS_P2P_OUI_TYPE_8822B)) +#define BIT_GET_P2P_OUI_TYPE_8822B(x) \ + (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822B) & BIT_MASK_P2P_OUI_TYPE_8822B) +#define BIT_SET_P2P_OUI_TYPE_8822B(x, v) \ + (BIT_CLEAR_P2P_OUI_TYPE_8822B(x) | BIT_P2P_OUI_TYPE_8822B(v)) /* 2 REG_ASSOCIATED_BFMER0_INFO_8822B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ #define BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_TXCSI_AID0_8822B 0x1ff -#define BIT_R_WMAC_TXCSI_AID0_8822B(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) -#define BIT_GET_R_WMAC_TXCSI_AID0_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B) - - +#define BIT_R_WMAC_TXCSI_AID0_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) +#define BITS_R_WMAC_TXCSI_AID0_8822B \ + (BIT_MASK_R_WMAC_TXCSI_AID0_8822B << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) +#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8822B(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID0_8822B)) +#define BIT_GET_R_WMAC_TXCSI_AID0_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) & \ + BIT_MASK_R_WMAC_TXCSI_AID0_8822B) +#define BIT_SET_R_WMAC_TXCSI_AID0_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID0_8822B(x) | BIT_R_WMAC_TXCSI_AID0_8822B(v)) #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) - - +#define BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_8822B \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8822B(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8822B)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8822B(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(v)) /* 2 REG_ASSOCIATED_BFMER1_INFO_8822B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ #define BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_TXCSI_AID1_8822B 0x1ff -#define BIT_R_WMAC_TXCSI_AID1_8822B(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) -#define BIT_GET_R_WMAC_TXCSI_AID1_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B) - - +#define BIT_R_WMAC_TXCSI_AID1_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) +#define BITS_R_WMAC_TXCSI_AID1_8822B \ + (BIT_MASK_R_WMAC_TXCSI_AID1_8822B << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) +#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8822B(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID1_8822B)) +#define BIT_GET_R_WMAC_TXCSI_AID1_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) & \ + BIT_MASK_R_WMAC_TXCSI_AID1_8822B) +#define BIT_SET_R_WMAC_TXCSI_AID1_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID1_8822B(x) | BIT_R_WMAC_TXCSI_AID1_8822B(v)) #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) - - +#define BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_8822B \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8822B(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8822B)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8822B(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW20_8822B (TX CSI REPORT PARAMETER REGISTER) */ #define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B 16 #define BIT_MASK_R_WMAC_BFINFO_20M_1_8822B 0xfff -#define BIT_R_WMAC_BFINFO_20M_1_8822B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) -#define BIT_GET_R_WMAC_BFINFO_20M_1_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B) - - +#define BIT_R_WMAC_BFINFO_20M_1_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) +#define BITS_R_WMAC_BFINFO_20M_1_8822B \ + (BIT_MASK_R_WMAC_BFINFO_20M_1_8822B \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822B(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8822B)) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) & \ + BIT_MASK_R_WMAC_BFINFO_20M_1_8822B) +#define BIT_SET_R_WMAC_BFINFO_20M_1_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822B(x) | \ + BIT_R_WMAC_BFINFO_20M_1_8822B(v)) #define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B 0 #define BIT_MASK_R_WMAC_BFINFO_20M_0_8822B 0xfff -#define BIT_R_WMAC_BFINFO_20M_0_8822B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) -#define BIT_GET_R_WMAC_BFINFO_20M_0_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) - - +#define BIT_R_WMAC_BFINFO_20M_0_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) +#define BITS_R_WMAC_BFINFO_20M_0_8822B \ + (BIT_MASK_R_WMAC_BFINFO_20M_0_8822B \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822B(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8822B)) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) & \ + BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) +#define BIT_SET_R_WMAC_BFINFO_20M_0_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822B(x) | \ + BIT_R_WMAC_BFINFO_20M_0_8822B(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW40_8822B (TX CSI REPORT PARAMETER_BW40 REGISTER) */ #define BIT_SHIFT_WMAC_RESP_ANTCD_8822B 0 #define BIT_MASK_WMAC_RESP_ANTCD_8822B 0xf -#define BIT_WMAC_RESP_ANTCD_8822B(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8822B) << BIT_SHIFT_WMAC_RESP_ANTCD_8822B) -#define BIT_GET_WMAC_RESP_ANTCD_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8822B) & BIT_MASK_WMAC_RESP_ANTCD_8822B) - - +#define BIT_WMAC_RESP_ANTCD_8822B(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTCD_8822B) \ + << BIT_SHIFT_WMAC_RESP_ANTCD_8822B) +#define BITS_WMAC_RESP_ANTCD_8822B \ + (BIT_MASK_WMAC_RESP_ANTCD_8822B << BIT_SHIFT_WMAC_RESP_ANTCD_8822B) +#define BIT_CLEAR_WMAC_RESP_ANTCD_8822B(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8822B)) +#define BIT_GET_WMAC_RESP_ANTCD_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8822B) & \ + BIT_MASK_WMAC_RESP_ANTCD_8822B) +#define BIT_SET_WMAC_RESP_ANTCD_8822B(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTCD_8822B(x) | BIT_WMAC_RESP_ANTCD_8822B(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW80_8822B (TX CSI REPORT PARAMETER_BW80 REGISTER) */ @@ -9529,139 +15157,216 @@ #define BIT_SHIFT_DTIM_CNT2_8822B 24 #define BIT_MASK_DTIM_CNT2_8822B 0xff -#define BIT_DTIM_CNT2_8822B(x) (((x) & BIT_MASK_DTIM_CNT2_8822B) << BIT_SHIFT_DTIM_CNT2_8822B) -#define BIT_GET_DTIM_CNT2_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8822B) & BIT_MASK_DTIM_CNT2_8822B) - - +#define BIT_DTIM_CNT2_8822B(x) \ + (((x) & BIT_MASK_DTIM_CNT2_8822B) << BIT_SHIFT_DTIM_CNT2_8822B) +#define BITS_DTIM_CNT2_8822B \ + (BIT_MASK_DTIM_CNT2_8822B << BIT_SHIFT_DTIM_CNT2_8822B) +#define BIT_CLEAR_DTIM_CNT2_8822B(x) ((x) & (~BITS_DTIM_CNT2_8822B)) +#define BIT_GET_DTIM_CNT2_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT2_8822B) & BIT_MASK_DTIM_CNT2_8822B) +#define BIT_SET_DTIM_CNT2_8822B(x, v) \ + (BIT_CLEAR_DTIM_CNT2_8822B(x) | BIT_DTIM_CNT2_8822B(v)) #define BIT_SHIFT_DTIM_PERIOD2_8822B 16 #define BIT_MASK_DTIM_PERIOD2_8822B 0xff -#define BIT_DTIM_PERIOD2_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD2_8822B) << BIT_SHIFT_DTIM_PERIOD2_8822B) -#define BIT_GET_DTIM_PERIOD2_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8822B) & BIT_MASK_DTIM_PERIOD2_8822B) - +#define BIT_DTIM_PERIOD2_8822B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD2_8822B) << BIT_SHIFT_DTIM_PERIOD2_8822B) +#define BITS_DTIM_PERIOD2_8822B \ + (BIT_MASK_DTIM_PERIOD2_8822B << BIT_SHIFT_DTIM_PERIOD2_8822B) +#define BIT_CLEAR_DTIM_PERIOD2_8822B(x) ((x) & (~BITS_DTIM_PERIOD2_8822B)) +#define BIT_GET_DTIM_PERIOD2_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD2_8822B) & BIT_MASK_DTIM_PERIOD2_8822B) +#define BIT_SET_DTIM_PERIOD2_8822B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD2_8822B(x) | BIT_DTIM_PERIOD2_8822B(v)) #define BIT_DTIM2_8822B BIT(15) #define BIT_TIM2_8822B BIT(14) #define BIT_SHIFT_PS_AID_2_8822B 0 #define BIT_MASK_PS_AID_2_8822B 0x7ff -#define BIT_PS_AID_2_8822B(x) (((x) & BIT_MASK_PS_AID_2_8822B) << BIT_SHIFT_PS_AID_2_8822B) -#define BIT_GET_PS_AID_2_8822B(x) (((x) >> BIT_SHIFT_PS_AID_2_8822B) & BIT_MASK_PS_AID_2_8822B) - - +#define BIT_PS_AID_2_8822B(x) \ + (((x) & BIT_MASK_PS_AID_2_8822B) << BIT_SHIFT_PS_AID_2_8822B) +#define BITS_PS_AID_2_8822B \ + (BIT_MASK_PS_AID_2_8822B << BIT_SHIFT_PS_AID_2_8822B) +#define BIT_CLEAR_PS_AID_2_8822B(x) ((x) & (~BITS_PS_AID_2_8822B)) +#define BIT_GET_PS_AID_2_8822B(x) \ + (((x) >> BIT_SHIFT_PS_AID_2_8822B) & BIT_MASK_PS_AID_2_8822B) +#define BIT_SET_PS_AID_2_8822B(x, v) \ + (BIT_CLEAR_PS_AID_2_8822B(x) | BIT_PS_AID_2_8822B(v)) /* 2 REG_BCN_PSR_RPT3_8822B (BEACON PARSER REPORT REGISTER3) */ #define BIT_SHIFT_DTIM_CNT3_8822B 24 #define BIT_MASK_DTIM_CNT3_8822B 0xff -#define BIT_DTIM_CNT3_8822B(x) (((x) & BIT_MASK_DTIM_CNT3_8822B) << BIT_SHIFT_DTIM_CNT3_8822B) -#define BIT_GET_DTIM_CNT3_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8822B) & BIT_MASK_DTIM_CNT3_8822B) - - +#define BIT_DTIM_CNT3_8822B(x) \ + (((x) & BIT_MASK_DTIM_CNT3_8822B) << BIT_SHIFT_DTIM_CNT3_8822B) +#define BITS_DTIM_CNT3_8822B \ + (BIT_MASK_DTIM_CNT3_8822B << BIT_SHIFT_DTIM_CNT3_8822B) +#define BIT_CLEAR_DTIM_CNT3_8822B(x) ((x) & (~BITS_DTIM_CNT3_8822B)) +#define BIT_GET_DTIM_CNT3_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT3_8822B) & BIT_MASK_DTIM_CNT3_8822B) +#define BIT_SET_DTIM_CNT3_8822B(x, v) \ + (BIT_CLEAR_DTIM_CNT3_8822B(x) | BIT_DTIM_CNT3_8822B(v)) #define BIT_SHIFT_DTIM_PERIOD3_8822B 16 #define BIT_MASK_DTIM_PERIOD3_8822B 0xff -#define BIT_DTIM_PERIOD3_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD3_8822B) << BIT_SHIFT_DTIM_PERIOD3_8822B) -#define BIT_GET_DTIM_PERIOD3_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8822B) & BIT_MASK_DTIM_PERIOD3_8822B) - +#define BIT_DTIM_PERIOD3_8822B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD3_8822B) << BIT_SHIFT_DTIM_PERIOD3_8822B) +#define BITS_DTIM_PERIOD3_8822B \ + (BIT_MASK_DTIM_PERIOD3_8822B << BIT_SHIFT_DTIM_PERIOD3_8822B) +#define BIT_CLEAR_DTIM_PERIOD3_8822B(x) ((x) & (~BITS_DTIM_PERIOD3_8822B)) +#define BIT_GET_DTIM_PERIOD3_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD3_8822B) & BIT_MASK_DTIM_PERIOD3_8822B) +#define BIT_SET_DTIM_PERIOD3_8822B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD3_8822B(x) | BIT_DTIM_PERIOD3_8822B(v)) #define BIT_DTIM3_8822B BIT(15) #define BIT_TIM3_8822B BIT(14) #define BIT_SHIFT_PS_AID_3_8822B 0 #define BIT_MASK_PS_AID_3_8822B 0x7ff -#define BIT_PS_AID_3_8822B(x) (((x) & BIT_MASK_PS_AID_3_8822B) << BIT_SHIFT_PS_AID_3_8822B) -#define BIT_GET_PS_AID_3_8822B(x) (((x) >> BIT_SHIFT_PS_AID_3_8822B) & BIT_MASK_PS_AID_3_8822B) - - +#define BIT_PS_AID_3_8822B(x) \ + (((x) & BIT_MASK_PS_AID_3_8822B) << BIT_SHIFT_PS_AID_3_8822B) +#define BITS_PS_AID_3_8822B \ + (BIT_MASK_PS_AID_3_8822B << BIT_SHIFT_PS_AID_3_8822B) +#define BIT_CLEAR_PS_AID_3_8822B(x) ((x) & (~BITS_PS_AID_3_8822B)) +#define BIT_GET_PS_AID_3_8822B(x) \ + (((x) >> BIT_SHIFT_PS_AID_3_8822B) & BIT_MASK_PS_AID_3_8822B) +#define BIT_SET_PS_AID_3_8822B(x, v) \ + (BIT_CLEAR_PS_AID_3_8822B(x) | BIT_PS_AID_3_8822B(v)) /* 2 REG_BCN_PSR_RPT4_8822B (BEACON PARSER REPORT REGISTER4) */ #define BIT_SHIFT_DTIM_CNT4_8822B 24 #define BIT_MASK_DTIM_CNT4_8822B 0xff -#define BIT_DTIM_CNT4_8822B(x) (((x) & BIT_MASK_DTIM_CNT4_8822B) << BIT_SHIFT_DTIM_CNT4_8822B) -#define BIT_GET_DTIM_CNT4_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8822B) & BIT_MASK_DTIM_CNT4_8822B) - - +#define BIT_DTIM_CNT4_8822B(x) \ + (((x) & BIT_MASK_DTIM_CNT4_8822B) << BIT_SHIFT_DTIM_CNT4_8822B) +#define BITS_DTIM_CNT4_8822B \ + (BIT_MASK_DTIM_CNT4_8822B << BIT_SHIFT_DTIM_CNT4_8822B) +#define BIT_CLEAR_DTIM_CNT4_8822B(x) ((x) & (~BITS_DTIM_CNT4_8822B)) +#define BIT_GET_DTIM_CNT4_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT4_8822B) & BIT_MASK_DTIM_CNT4_8822B) +#define BIT_SET_DTIM_CNT4_8822B(x, v) \ + (BIT_CLEAR_DTIM_CNT4_8822B(x) | BIT_DTIM_CNT4_8822B(v)) #define BIT_SHIFT_DTIM_PERIOD4_8822B 16 #define BIT_MASK_DTIM_PERIOD4_8822B 0xff -#define BIT_DTIM_PERIOD4_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD4_8822B) << BIT_SHIFT_DTIM_PERIOD4_8822B) -#define BIT_GET_DTIM_PERIOD4_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8822B) & BIT_MASK_DTIM_PERIOD4_8822B) - +#define BIT_DTIM_PERIOD4_8822B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD4_8822B) << BIT_SHIFT_DTIM_PERIOD4_8822B) +#define BITS_DTIM_PERIOD4_8822B \ + (BIT_MASK_DTIM_PERIOD4_8822B << BIT_SHIFT_DTIM_PERIOD4_8822B) +#define BIT_CLEAR_DTIM_PERIOD4_8822B(x) ((x) & (~BITS_DTIM_PERIOD4_8822B)) +#define BIT_GET_DTIM_PERIOD4_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD4_8822B) & BIT_MASK_DTIM_PERIOD4_8822B) +#define BIT_SET_DTIM_PERIOD4_8822B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD4_8822B(x) | BIT_DTIM_PERIOD4_8822B(v)) #define BIT_DTIM4_8822B BIT(15) #define BIT_TIM4_8822B BIT(14) #define BIT_SHIFT_PS_AID_4_8822B 0 #define BIT_MASK_PS_AID_4_8822B 0x7ff -#define BIT_PS_AID_4_8822B(x) (((x) & BIT_MASK_PS_AID_4_8822B) << BIT_SHIFT_PS_AID_4_8822B) -#define BIT_GET_PS_AID_4_8822B(x) (((x) >> BIT_SHIFT_PS_AID_4_8822B) & BIT_MASK_PS_AID_4_8822B) - - +#define BIT_PS_AID_4_8822B(x) \ + (((x) & BIT_MASK_PS_AID_4_8822B) << BIT_SHIFT_PS_AID_4_8822B) +#define BITS_PS_AID_4_8822B \ + (BIT_MASK_PS_AID_4_8822B << BIT_SHIFT_PS_AID_4_8822B) +#define BIT_CLEAR_PS_AID_4_8822B(x) ((x) & (~BITS_PS_AID_4_8822B)) +#define BIT_GET_PS_AID_4_8822B(x) \ + (((x) >> BIT_SHIFT_PS_AID_4_8822B) & BIT_MASK_PS_AID_4_8822B) +#define BIT_SET_PS_AID_4_8822B(x, v) \ + (BIT_CLEAR_PS_AID_4_8822B(x) | BIT_PS_AID_4_8822B(v)) /* 2 REG_A1_ADDR_MASK_8822B (A1 ADDR MASK REGISTER) */ #define BIT_SHIFT_A1_ADDR_MASK_8822B 0 #define BIT_MASK_A1_ADDR_MASK_8822B 0xffffffffL -#define BIT_A1_ADDR_MASK_8822B(x) (((x) & BIT_MASK_A1_ADDR_MASK_8822B) << BIT_SHIFT_A1_ADDR_MASK_8822B) -#define BIT_GET_A1_ADDR_MASK_8822B(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8822B) & BIT_MASK_A1_ADDR_MASK_8822B) - - +#define BIT_A1_ADDR_MASK_8822B(x) \ + (((x) & BIT_MASK_A1_ADDR_MASK_8822B) << BIT_SHIFT_A1_ADDR_MASK_8822B) +#define BITS_A1_ADDR_MASK_8822B \ + (BIT_MASK_A1_ADDR_MASK_8822B << BIT_SHIFT_A1_ADDR_MASK_8822B) +#define BIT_CLEAR_A1_ADDR_MASK_8822B(x) ((x) & (~BITS_A1_ADDR_MASK_8822B)) +#define BIT_GET_A1_ADDR_MASK_8822B(x) \ + (((x) >> BIT_SHIFT_A1_ADDR_MASK_8822B) & BIT_MASK_A1_ADDR_MASK_8822B) +#define BIT_SET_A1_ADDR_MASK_8822B(x, v) \ + (BIT_CLEAR_A1_ADDR_MASK_8822B(x) | BIT_A1_ADDR_MASK_8822B(v)) /* 2 REG_MACID2_8822B (MAC ID2 REGISTER) */ #define BIT_SHIFT_MACID2_8822B 0 #define BIT_MASK_MACID2_8822B 0xffffffffffffL -#define BIT_MACID2_8822B(x) (((x) & BIT_MASK_MACID2_8822B) << BIT_SHIFT_MACID2_8822B) -#define BIT_GET_MACID2_8822B(x) (((x) >> BIT_SHIFT_MACID2_8822B) & BIT_MASK_MACID2_8822B) - - +#define BIT_MACID2_8822B(x) \ + (((x) & BIT_MASK_MACID2_8822B) << BIT_SHIFT_MACID2_8822B) +#define BITS_MACID2_8822B (BIT_MASK_MACID2_8822B << BIT_SHIFT_MACID2_8822B) +#define BIT_CLEAR_MACID2_8822B(x) ((x) & (~BITS_MACID2_8822B)) +#define BIT_GET_MACID2_8822B(x) \ + (((x) >> BIT_SHIFT_MACID2_8822B) & BIT_MASK_MACID2_8822B) +#define BIT_SET_MACID2_8822B(x, v) \ + (BIT_CLEAR_MACID2_8822B(x) | BIT_MACID2_8822B(v)) /* 2 REG_BSSID2_8822B (BSSID2 REGISTER) */ #define BIT_SHIFT_BSSID2_8822B 0 #define BIT_MASK_BSSID2_8822B 0xffffffffffffL -#define BIT_BSSID2_8822B(x) (((x) & BIT_MASK_BSSID2_8822B) << BIT_SHIFT_BSSID2_8822B) -#define BIT_GET_BSSID2_8822B(x) (((x) >> BIT_SHIFT_BSSID2_8822B) & BIT_MASK_BSSID2_8822B) - - +#define BIT_BSSID2_8822B(x) \ + (((x) & BIT_MASK_BSSID2_8822B) << BIT_SHIFT_BSSID2_8822B) +#define BITS_BSSID2_8822B (BIT_MASK_BSSID2_8822B << BIT_SHIFT_BSSID2_8822B) +#define BIT_CLEAR_BSSID2_8822B(x) ((x) & (~BITS_BSSID2_8822B)) +#define BIT_GET_BSSID2_8822B(x) \ + (((x) >> BIT_SHIFT_BSSID2_8822B) & BIT_MASK_BSSID2_8822B) +#define BIT_SET_BSSID2_8822B(x, v) \ + (BIT_CLEAR_BSSID2_8822B(x) | BIT_BSSID2_8822B(v)) /* 2 REG_MACID3_8822B (MAC ID3 REGISTER) */ #define BIT_SHIFT_MACID3_8822B 0 #define BIT_MASK_MACID3_8822B 0xffffffffffffL -#define BIT_MACID3_8822B(x) (((x) & BIT_MASK_MACID3_8822B) << BIT_SHIFT_MACID3_8822B) -#define BIT_GET_MACID3_8822B(x) (((x) >> BIT_SHIFT_MACID3_8822B) & BIT_MASK_MACID3_8822B) - - +#define BIT_MACID3_8822B(x) \ + (((x) & BIT_MASK_MACID3_8822B) << BIT_SHIFT_MACID3_8822B) +#define BITS_MACID3_8822B (BIT_MASK_MACID3_8822B << BIT_SHIFT_MACID3_8822B) +#define BIT_CLEAR_MACID3_8822B(x) ((x) & (~BITS_MACID3_8822B)) +#define BIT_GET_MACID3_8822B(x) \ + (((x) >> BIT_SHIFT_MACID3_8822B) & BIT_MASK_MACID3_8822B) +#define BIT_SET_MACID3_8822B(x, v) \ + (BIT_CLEAR_MACID3_8822B(x) | BIT_MACID3_8822B(v)) /* 2 REG_BSSID3_8822B (BSSID3 REGISTER) */ #define BIT_SHIFT_BSSID3_8822B 0 #define BIT_MASK_BSSID3_8822B 0xffffffffffffL -#define BIT_BSSID3_8822B(x) (((x) & BIT_MASK_BSSID3_8822B) << BIT_SHIFT_BSSID3_8822B) -#define BIT_GET_BSSID3_8822B(x) (((x) >> BIT_SHIFT_BSSID3_8822B) & BIT_MASK_BSSID3_8822B) - - +#define BIT_BSSID3_8822B(x) \ + (((x) & BIT_MASK_BSSID3_8822B) << BIT_SHIFT_BSSID3_8822B) +#define BITS_BSSID3_8822B (BIT_MASK_BSSID3_8822B << BIT_SHIFT_BSSID3_8822B) +#define BIT_CLEAR_BSSID3_8822B(x) ((x) & (~BITS_BSSID3_8822B)) +#define BIT_GET_BSSID3_8822B(x) \ + (((x) >> BIT_SHIFT_BSSID3_8822B) & BIT_MASK_BSSID3_8822B) +#define BIT_SET_BSSID3_8822B(x, v) \ + (BIT_CLEAR_BSSID3_8822B(x) | BIT_BSSID3_8822B(v)) /* 2 REG_MACID4_8822B (MAC ID4 REGISTER) */ #define BIT_SHIFT_MACID4_8822B 0 #define BIT_MASK_MACID4_8822B 0xffffffffffffL -#define BIT_MACID4_8822B(x) (((x) & BIT_MASK_MACID4_8822B) << BIT_SHIFT_MACID4_8822B) -#define BIT_GET_MACID4_8822B(x) (((x) >> BIT_SHIFT_MACID4_8822B) & BIT_MASK_MACID4_8822B) - - +#define BIT_MACID4_8822B(x) \ + (((x) & BIT_MASK_MACID4_8822B) << BIT_SHIFT_MACID4_8822B) +#define BITS_MACID4_8822B (BIT_MASK_MACID4_8822B << BIT_SHIFT_MACID4_8822B) +#define BIT_CLEAR_MACID4_8822B(x) ((x) & (~BITS_MACID4_8822B)) +#define BIT_GET_MACID4_8822B(x) \ + (((x) >> BIT_SHIFT_MACID4_8822B) & BIT_MASK_MACID4_8822B) +#define BIT_SET_MACID4_8822B(x, v) \ + (BIT_CLEAR_MACID4_8822B(x) | BIT_MACID4_8822B(v)) /* 2 REG_BSSID4_8822B (BSSID4 REGISTER) */ #define BIT_SHIFT_BSSID4_8822B 0 #define BIT_MASK_BSSID4_8822B 0xffffffffffffL -#define BIT_BSSID4_8822B(x) (((x) & BIT_MASK_BSSID4_8822B) << BIT_SHIFT_BSSID4_8822B) -#define BIT_GET_BSSID4_8822B(x) (((x) >> BIT_SHIFT_BSSID4_8822B) & BIT_MASK_BSSID4_8822B) - - +#define BIT_BSSID4_8822B(x) \ + (((x) & BIT_MASK_BSSID4_8822B) << BIT_SHIFT_BSSID4_8822B) +#define BITS_BSSID4_8822B (BIT_MASK_BSSID4_8822B << BIT_SHIFT_BSSID4_8822B) +#define BIT_CLEAR_BSSID4_8822B(x) ((x) & (~BITS_BSSID4_8822B)) +#define BIT_GET_BSSID4_8822B(x) \ + (((x) >> BIT_SHIFT_BSSID4_8822B) & BIT_MASK_BSSID4_8822B) +#define BIT_SET_BSSID4_8822B(x, v) \ + (BIT_CLEAR_BSSID4_8822B(x) | BIT_BSSID4_8822B(v)) /* 2 REG_NOA_REPORT_8822B */ @@ -9681,16 +15386,37 @@ #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B 4 #define BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B 0x3 -#define BIT_WMAC_TXMU_ACKPOLICY_8822B(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) -#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822B(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B) - - +#define BIT_WMAC_TXMU_ACKPOLICY_8822B(x) \ + (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B) \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) +#define BITS_WMAC_TXMU_ACKPOLICY_8822B \ + (BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822B(x) \ + ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8822B)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) & \ + BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B) +#define BIT_SET_WMAC_TXMU_ACKPOLICY_8822B(x, v) \ + (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822B(x) | \ + BIT_WMAC_TXMU_ACKPOLICY_8822B(v)) #define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B 1 #define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B 0x7 -#define BIT_WMAC_MU_BFEE_PORT_SEL_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) -#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B) - +#define BIT_WMAC_MU_BFEE_PORT_SEL_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) +#define BITS_WMAC_MU_BFEE_PORT_SEL_8822B \ + (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8822B)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) & \ + BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822B(x) | \ + BIT_WMAC_MU_BFEE_PORT_SEL_8822B(v)) #define BIT_WMAC_MU_BFEE_DIS_8822B BIT(0) @@ -9698,10 +15424,20 @@ #define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B 0 #define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B 0xff -#define BIT_WMAC_PAUSE_BB_CLR_TH_8822B(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) -#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822B(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B) - - +#define BIT_WMAC_PAUSE_BB_CLR_TH_8822B(x) \ + (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B) \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) +#define BITS_WMAC_PAUSE_BB_CLR_TH_8822B \ + (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822B(x) \ + ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8822B)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) & \ + BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8822B(x, v) \ + (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822B(x) | \ + BIT_WMAC_PAUSE_BB_CLR_TH_8822B(v)) /* 2 REG_WMAC_MU_ARB_8822B */ #define BIT_WMAC_ARB_HW_ADAPT_EN_8822B BIT(7) @@ -9709,26 +15445,51 @@ #define BIT_SHIFT_WMAC_ARB_SW_STATE_8822B 0 #define BIT_MASK_WMAC_ARB_SW_STATE_8822B 0x3f -#define BIT_WMAC_ARB_SW_STATE_8822B(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8822B) << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) -#define BIT_GET_WMAC_ARB_SW_STATE_8822B(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) & BIT_MASK_WMAC_ARB_SW_STATE_8822B) - - +#define BIT_WMAC_ARB_SW_STATE_8822B(x) \ + (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8822B) \ + << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) +#define BITS_WMAC_ARB_SW_STATE_8822B \ + (BIT_MASK_WMAC_ARB_SW_STATE_8822B << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) +#define BIT_CLEAR_WMAC_ARB_SW_STATE_8822B(x) \ + ((x) & (~BITS_WMAC_ARB_SW_STATE_8822B)) +#define BIT_GET_WMAC_ARB_SW_STATE_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) & \ + BIT_MASK_WMAC_ARB_SW_STATE_8822B) +#define BIT_SET_WMAC_ARB_SW_STATE_8822B(x, v) \ + (BIT_CLEAR_WMAC_ARB_SW_STATE_8822B(x) | BIT_WMAC_ARB_SW_STATE_8822B(v)) /* 2 REG_WMAC_MU_OPTION_8822B */ #define BIT_SHIFT_WMAC_MU_DBGSEL_8822B 5 #define BIT_MASK_WMAC_MU_DBGSEL_8822B 0x3 -#define BIT_WMAC_MU_DBGSEL_8822B(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8822B) << BIT_SHIFT_WMAC_MU_DBGSEL_8822B) -#define BIT_GET_WMAC_MU_DBGSEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8822B) & BIT_MASK_WMAC_MU_DBGSEL_8822B) - - +#define BIT_WMAC_MU_DBGSEL_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_DBGSEL_8822B) \ + << BIT_SHIFT_WMAC_MU_DBGSEL_8822B) +#define BITS_WMAC_MU_DBGSEL_8822B \ + (BIT_MASK_WMAC_MU_DBGSEL_8822B << BIT_SHIFT_WMAC_MU_DBGSEL_8822B) +#define BIT_CLEAR_WMAC_MU_DBGSEL_8822B(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8822B)) +#define BIT_GET_WMAC_MU_DBGSEL_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8822B) & \ + BIT_MASK_WMAC_MU_DBGSEL_8822B) +#define BIT_SET_WMAC_MU_DBGSEL_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_DBGSEL_8822B(x) | BIT_WMAC_MU_DBGSEL_8822B(v)) #define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B 0 #define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B 0x1f -#define BIT_WMAC_MU_CPRD_TIMEOUT_8822B(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) -#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B) - - +#define BIT_WMAC_MU_CPRD_TIMEOUT_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B) \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) +#define BITS_WMAC_MU_CPRD_TIMEOUT_8822B \ + (BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) +#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8822B(x) \ + ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8822B)) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) & \ + BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B) +#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8822B(x) | \ + BIT_WMAC_MU_CPRD_TIMEOUT_8822B(v)) /* 2 REG_WMAC_MU_BF_CTL_8822B */ #define BIT_WMAC_INVLD_BFPRT_CHK_8822B BIT(15) @@ -9736,33 +15497,66 @@ #define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B 12 #define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B 0x3 -#define BIT_WMAC_MU_BFRPTSEG_SEL_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) -#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B) - - +#define BIT_WMAC_MU_BFRPTSEG_SEL_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B) \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) +#define BITS_WMAC_MU_BFRPTSEG_SEL_8822B \ + (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8822B)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) & \ + BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822B(x) | \ + BIT_WMAC_MU_BFRPTSEG_SEL_8822B(v)) #define BIT_SHIFT_WMAC_MU_BF_MYAID_8822B 0 #define BIT_MASK_WMAC_MU_BF_MYAID_8822B 0xfff -#define BIT_WMAC_MU_BF_MYAID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822B) << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) -#define BIT_GET_WMAC_MU_BF_MYAID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) & BIT_MASK_WMAC_MU_BF_MYAID_8822B) - - +#define BIT_WMAC_MU_BF_MYAID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822B) \ + << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) +#define BITS_WMAC_MU_BF_MYAID_8822B \ + (BIT_MASK_WMAC_MU_BF_MYAID_8822B << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BF_MYAID_8822B)) +#define BIT_GET_WMAC_MU_BF_MYAID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) & \ + BIT_MASK_WMAC_MU_BF_MYAID_8822B) +#define BIT_SET_WMAC_MU_BF_MYAID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BF_MYAID_8822B(x) | BIT_WMAC_MU_BF_MYAID_8822B(v)) /* 2 REG_WMAC_MU_BFRPT_PARA_8822B */ #define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B 12 #define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B 0x7 -#define BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(x) (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B) << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) -#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL_8822B(x) (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B) - - +#define BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(x) \ + (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B) \ + << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) +#define BITS_BIT_BFRPT_PARA_USERID_SEL_8822B \ + (BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B \ + << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) +#define BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL_8822B(x) \ + ((x) & (~BITS_BIT_BFRPT_PARA_USERID_SEL_8822B)) +#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) & \ + BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B) +#define BIT_SET_BIT_BFRPT_PARA_USERID_SEL_8822B(x, v) \ + (BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL_8822B(x) | \ + BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(v)) #define BIT_SHIFT_BFRPT_PARA_8822B 0 #define BIT_MASK_BFRPT_PARA_8822B 0xfff -#define BIT_BFRPT_PARA_8822B(x) (((x) & BIT_MASK_BFRPT_PARA_8822B) << BIT_SHIFT_BFRPT_PARA_8822B) -#define BIT_GET_BFRPT_PARA_8822B(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8822B) & BIT_MASK_BFRPT_PARA_8822B) - - +#define BIT_BFRPT_PARA_8822B(x) \ + (((x) & BIT_MASK_BFRPT_PARA_8822B) << BIT_SHIFT_BFRPT_PARA_8822B) +#define BITS_BFRPT_PARA_8822B \ + (BIT_MASK_BFRPT_PARA_8822B << BIT_SHIFT_BFRPT_PARA_8822B) +#define BIT_CLEAR_BFRPT_PARA_8822B(x) ((x) & (~BITS_BFRPT_PARA_8822B)) +#define BIT_GET_BFRPT_PARA_8822B(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_8822B) & BIT_MASK_BFRPT_PARA_8822B) +#define BIT_SET_BFRPT_PARA_8822B(x, v) \ + (BIT_CLEAR_BFRPT_PARA_8822B(x) | BIT_BFRPT_PARA_8822B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B */ #define BIT_STATUS_BFEE2_8822B BIT(10) @@ -9770,21 +15564,37 @@ #define BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B 0 #define BIT_MASK_WMAC_MU_BFEE2_AID_8822B 0x1ff -#define BIT_WMAC_MU_BFEE2_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) -#define BIT_GET_WMAC_MU_BFEE2_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) & BIT_MASK_WMAC_MU_BFEE2_AID_8822B) - - +#define BIT_WMAC_MU_BFEE2_AID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) +#define BITS_WMAC_MU_BFEE2_AID_8822B \ + (BIT_MASK_WMAC_MU_BFEE2_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE2_AID_8822B)) +#define BIT_GET_WMAC_MU_BFEE2_AID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) & \ + BIT_MASK_WMAC_MU_BFEE2_AID_8822B) +#define BIT_SET_WMAC_MU_BFEE2_AID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE2_AID_8822B(x) | BIT_WMAC_MU_BFEE2_AID_8822B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B */ #define BIT_STATUS_BFEE3_8822B BIT(10) #define BIT_WMAC_MU_BFEE3_EN_8822B BIT(9) #define BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B 0 -#define BIT_MASK_WMAC_MU_BFEE3_AID_8822B 0x1ff -#define BIT_WMAC_MU_BFEE3_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) -#define BIT_GET_WMAC_MU_BFEE3_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) & BIT_MASK_WMAC_MU_BFEE3_AID_8822B) - - +#define BIT_MASK_WMAC_MU_BFEE3_AID_8822B 0x1ff +#define BIT_WMAC_MU_BFEE3_AID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) +#define BITS_WMAC_MU_BFEE3_AID_8822B \ + (BIT_MASK_WMAC_MU_BFEE3_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE3_AID_8822B)) +#define BIT_GET_WMAC_MU_BFEE3_AID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) & \ + BIT_MASK_WMAC_MU_BFEE3_AID_8822B) +#define BIT_SET_WMAC_MU_BFEE3_AID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE3_AID_8822B(x) | BIT_WMAC_MU_BFEE3_AID_8822B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B */ #define BIT_STATUS_BFEE4_8822B BIT(10) @@ -9792,10 +15602,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B 0 #define BIT_MASK_WMAC_MU_BFEE4_AID_8822B 0x1ff -#define BIT_WMAC_MU_BFEE4_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) -#define BIT_GET_WMAC_MU_BFEE4_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) & BIT_MASK_WMAC_MU_BFEE4_AID_8822B) - - +#define BIT_WMAC_MU_BFEE4_AID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) +#define BITS_WMAC_MU_BFEE4_AID_8822B \ + (BIT_MASK_WMAC_MU_BFEE4_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE4_AID_8822B)) +#define BIT_GET_WMAC_MU_BFEE4_AID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) & \ + BIT_MASK_WMAC_MU_BFEE4_AID_8822B) +#define BIT_SET_WMAC_MU_BFEE4_AID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE4_AID_8822B(x) | BIT_WMAC_MU_BFEE4_AID_8822B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B */ #define BIT_STATUS_BFEE5_8822B BIT(10) @@ -9803,10 +15621,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B 0 #define BIT_MASK_WMAC_MU_BFEE5_AID_8822B 0x1ff -#define BIT_WMAC_MU_BFEE5_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) -#define BIT_GET_WMAC_MU_BFEE5_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) & BIT_MASK_WMAC_MU_BFEE5_AID_8822B) - - +#define BIT_WMAC_MU_BFEE5_AID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) +#define BITS_WMAC_MU_BFEE5_AID_8822B \ + (BIT_MASK_WMAC_MU_BFEE5_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE5_AID_8822B)) +#define BIT_GET_WMAC_MU_BFEE5_AID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) & \ + BIT_MASK_WMAC_MU_BFEE5_AID_8822B) +#define BIT_SET_WMAC_MU_BFEE5_AID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE5_AID_8822B(x) | BIT_WMAC_MU_BFEE5_AID_8822B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B */ #define BIT_STATUS_BFEE6_8822B BIT(10) @@ -9814,124 +15640,204 @@ #define BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B 0 #define BIT_MASK_WMAC_MU_BFEE6_AID_8822B 0x1ff -#define BIT_WMAC_MU_BFEE6_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) -#define BIT_GET_WMAC_MU_BFEE6_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) & BIT_MASK_WMAC_MU_BFEE6_AID_8822B) - - +#define BIT_WMAC_MU_BFEE6_AID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) +#define BITS_WMAC_MU_BFEE6_AID_8822B \ + (BIT_MASK_WMAC_MU_BFEE6_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE6_AID_8822B)) +#define BIT_GET_WMAC_MU_BFEE6_AID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) & \ + BIT_MASK_WMAC_MU_BFEE6_AID_8822B) +#define BIT_SET_WMAC_MU_BFEE6_AID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE6_AID_8822B(x) | BIT_WMAC_MU_BFEE6_AID_8822B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B */ -#define BIT_BIT_STATUS_BFEE4_8822B BIT(10) +#define BIT_STATUS_BFEE7_8822B BIT(10) #define BIT_WMAC_MU_BFEE7_EN_8822B BIT(9) #define BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B 0 #define BIT_MASK_WMAC_MU_BFEE7_AID_8822B 0x1ff -#define BIT_WMAC_MU_BFEE7_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) -#define BIT_GET_WMAC_MU_BFEE7_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) & BIT_MASK_WMAC_MU_BFEE7_AID_8822B) - - +#define BIT_WMAC_MU_BFEE7_AID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) +#define BITS_WMAC_MU_BFEE7_AID_8822B \ + (BIT_MASK_WMAC_MU_BFEE7_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE7_AID_8822B)) +#define BIT_GET_WMAC_MU_BFEE7_AID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) & \ + BIT_MASK_WMAC_MU_BFEE7_AID_8822B) +#define BIT_SET_WMAC_MU_BFEE7_AID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE7_AID_8822B(x) | BIT_WMAC_MU_BFEE7_AID_8822B(v)) /* 2 REG_NOT_VALID_8822B */ #define BIT_RST_ALL_COUNTER_8822B BIT(31) #define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B 16 #define BIT_MASK_ABORT_RX_VBON_COUNTER_8822B 0xff -#define BIT_ABORT_RX_VBON_COUNTER_8822B(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822B) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) -#define BIT_GET_ABORT_RX_VBON_COUNTER_8822B(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822B) - - +#define BIT_ABORT_RX_VBON_COUNTER_8822B(x) \ + (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822B) \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) +#define BITS_ABORT_RX_VBON_COUNTER_8822B \ + (BIT_MASK_ABORT_RX_VBON_COUNTER_8822B \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822B(x) \ + ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8822B)) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8822B(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) & \ + BIT_MASK_ABORT_RX_VBON_COUNTER_8822B) +#define BIT_SET_ABORT_RX_VBON_COUNTER_8822B(x, v) \ + (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822B(x) | \ + BIT_ABORT_RX_VBON_COUNTER_8822B(v)) #define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B 8 #define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B 0xff -#define BIT_ABORT_RX_RDRDY_COUNTER_8822B(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) -#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822B(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B) - - +#define BIT_ABORT_RX_RDRDY_COUNTER_8822B(x) \ + (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B) \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) +#define BITS_ABORT_RX_RDRDY_COUNTER_8822B \ + (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822B(x) \ + ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8822B)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822B(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) & \ + BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8822B(x, v) \ + (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822B(x) | \ + BIT_ABORT_RX_RDRDY_COUNTER_8822B(v)) #define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B 0 #define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B 0xff -#define BIT_VBON_EARLY_FALLING_COUNTER_8822B(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) -#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822B(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B) - - +#define BIT_VBON_EARLY_FALLING_COUNTER_8822B(x) \ + (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B) \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) +#define BITS_VBON_EARLY_FALLING_COUNTER_8822B \ + (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822B(x) \ + ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8822B)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822B(x) \ + (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) & \ + BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8822B(x, v) \ + (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822B(x) | \ + BIT_VBON_EARLY_FALLING_COUNTER_8822B(v)) /* 2 REG_NOT_VALID_8822B */ #define BIT_WMAC_PLCP_TRX_SEL_8822B BIT(31) #define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B 28 #define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B 0x7 -#define BIT_WMAC_PLCP_RDSIG_SEL_8822B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) -#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B) - - +#define BIT_WMAC_PLCP_RDSIG_SEL_8822B(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) +#define BITS_WMAC_PLCP_RDSIG_SEL_8822B \ + (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822B(x) \ + ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8822B)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) & \ + BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8822B(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822B(x) | \ + BIT_WMAC_PLCP_RDSIG_SEL_8822B(v)) #define BIT_SHIFT_WMAC_RATE_IDX_8822B 24 #define BIT_MASK_WMAC_RATE_IDX_8822B 0xf -#define BIT_WMAC_RATE_IDX_8822B(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8822B) << BIT_SHIFT_WMAC_RATE_IDX_8822B) -#define BIT_GET_WMAC_RATE_IDX_8822B(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822B) & BIT_MASK_WMAC_RATE_IDX_8822B) - - +#define BIT_WMAC_RATE_IDX_8822B(x) \ + (((x) & BIT_MASK_WMAC_RATE_IDX_8822B) << BIT_SHIFT_WMAC_RATE_IDX_8822B) +#define BITS_WMAC_RATE_IDX_8822B \ + (BIT_MASK_WMAC_RATE_IDX_8822B << BIT_SHIFT_WMAC_RATE_IDX_8822B) +#define BIT_CLEAR_WMAC_RATE_IDX_8822B(x) ((x) & (~BITS_WMAC_RATE_IDX_8822B)) +#define BIT_GET_WMAC_RATE_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822B) & BIT_MASK_WMAC_RATE_IDX_8822B) +#define BIT_SET_WMAC_RATE_IDX_8822B(x, v) \ + (BIT_CLEAR_WMAC_RATE_IDX_8822B(x) | BIT_WMAC_RATE_IDX_8822B(v)) #define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0 #define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8822B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) -#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) - - +#define BIT_WMAC_PLCP_RDSIG_8822B(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) +#define BITS_WMAC_PLCP_RDSIG_8822B \ + (BIT_MASK_WMAC_PLCP_RDSIG_8822B << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822B)) +#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8822B) +#define BIT_SET_WMAC_PLCP_RDSIG_8822B(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) | BIT_WMAC_PLCP_RDSIG_8822B(v)) /* 2 REG_NOT_VALID_8822B */ #define BIT_WMAC_MUTX_IDX_8822B BIT(24) #define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0 #define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8822B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) -#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) - - +#define BIT_WMAC_PLCP_RDSIG_8822B(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) +#define BITS_WMAC_PLCP_RDSIG_8822B \ + (BIT_MASK_WMAC_PLCP_RDSIG_8822B << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822B)) +#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8822B) +#define BIT_SET_WMAC_PLCP_RDSIG_8822B(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) | BIT_WMAC_PLCP_RDSIG_8822B(v)) /* 2 REG_TRANSMIT_ADDRSS_0_8822B (TA0 REGISTER) */ #define BIT_SHIFT_TA0_8822B 0 #define BIT_MASK_TA0_8822B 0xffffffffffffL #define BIT_TA0_8822B(x) (((x) & BIT_MASK_TA0_8822B) << BIT_SHIFT_TA0_8822B) +#define BITS_TA0_8822B (BIT_MASK_TA0_8822B << BIT_SHIFT_TA0_8822B) +#define BIT_CLEAR_TA0_8822B(x) ((x) & (~BITS_TA0_8822B)) #define BIT_GET_TA0_8822B(x) (((x) >> BIT_SHIFT_TA0_8822B) & BIT_MASK_TA0_8822B) - - +#define BIT_SET_TA0_8822B(x, v) (BIT_CLEAR_TA0_8822B(x) | BIT_TA0_8822B(v)) /* 2 REG_TRANSMIT_ADDRSS_1_8822B (TA1 REGISTER) */ #define BIT_SHIFT_TA1_8822B 0 #define BIT_MASK_TA1_8822B 0xffffffffffffL #define BIT_TA1_8822B(x) (((x) & BIT_MASK_TA1_8822B) << BIT_SHIFT_TA1_8822B) +#define BITS_TA1_8822B (BIT_MASK_TA1_8822B << BIT_SHIFT_TA1_8822B) +#define BIT_CLEAR_TA1_8822B(x) ((x) & (~BITS_TA1_8822B)) #define BIT_GET_TA1_8822B(x) (((x) >> BIT_SHIFT_TA1_8822B) & BIT_MASK_TA1_8822B) - - +#define BIT_SET_TA1_8822B(x, v) (BIT_CLEAR_TA1_8822B(x) | BIT_TA1_8822B(v)) /* 2 REG_TRANSMIT_ADDRSS_2_8822B (TA2 REGISTER) */ #define BIT_SHIFT_TA2_8822B 0 #define BIT_MASK_TA2_8822B 0xffffffffffffL #define BIT_TA2_8822B(x) (((x) & BIT_MASK_TA2_8822B) << BIT_SHIFT_TA2_8822B) +#define BITS_TA2_8822B (BIT_MASK_TA2_8822B << BIT_SHIFT_TA2_8822B) +#define BIT_CLEAR_TA2_8822B(x) ((x) & (~BITS_TA2_8822B)) #define BIT_GET_TA2_8822B(x) (((x) >> BIT_SHIFT_TA2_8822B) & BIT_MASK_TA2_8822B) - - +#define BIT_SET_TA2_8822B(x, v) (BIT_CLEAR_TA2_8822B(x) | BIT_TA2_8822B(v)) /* 2 REG_TRANSMIT_ADDRSS_3_8822B (TA3 REGISTER) */ #define BIT_SHIFT_TA3_8822B 0 #define BIT_MASK_TA3_8822B 0xffffffffffffL #define BIT_TA3_8822B(x) (((x) & BIT_MASK_TA3_8822B) << BIT_SHIFT_TA3_8822B) +#define BITS_TA3_8822B (BIT_MASK_TA3_8822B << BIT_SHIFT_TA3_8822B) +#define BIT_CLEAR_TA3_8822B(x) ((x) & (~BITS_TA3_8822B)) #define BIT_GET_TA3_8822B(x) (((x) >> BIT_SHIFT_TA3_8822B) & BIT_MASK_TA3_8822B) - - +#define BIT_SET_TA3_8822B(x, v) (BIT_CLEAR_TA3_8822B(x) | BIT_TA3_8822B(v)) /* 2 REG_TRANSMIT_ADDRSS_4_8822B (TA4 REGISTER) */ #define BIT_SHIFT_TA4_8822B 0 #define BIT_MASK_TA4_8822B 0xffffffffffffL #define BIT_TA4_8822B(x) (((x) & BIT_MASK_TA4_8822B) << BIT_SHIFT_TA4_8822B) +#define BITS_TA4_8822B (BIT_MASK_TA4_8822B << BIT_SHIFT_TA4_8822B) +#define BIT_CLEAR_TA4_8822B(x) ((x) & (~BITS_TA4_8822B)) #define BIT_GET_TA4_8822B(x) (((x) >> BIT_SHIFT_TA4_8822B) & BIT_MASK_TA4_8822B) - - +#define BIT_SET_TA4_8822B(x, v) (BIT_CLEAR_TA4_8822B(x) | BIT_TA4_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -9939,44 +15845,68 @@ #define BIT_SHIFT_MACID1_8822B 0 #define BIT_MASK_MACID1_8822B 0xffffffffffffL -#define BIT_MACID1_8822B(x) (((x) & BIT_MASK_MACID1_8822B) << BIT_SHIFT_MACID1_8822B) -#define BIT_GET_MACID1_8822B(x) (((x) >> BIT_SHIFT_MACID1_8822B) & BIT_MASK_MACID1_8822B) - - +#define BIT_MACID1_8822B(x) \ + (((x) & BIT_MASK_MACID1_8822B) << BIT_SHIFT_MACID1_8822B) +#define BITS_MACID1_8822B (BIT_MASK_MACID1_8822B << BIT_SHIFT_MACID1_8822B) +#define BIT_CLEAR_MACID1_8822B(x) ((x) & (~BITS_MACID1_8822B)) +#define BIT_GET_MACID1_8822B(x) \ + (((x) >> BIT_SHIFT_MACID1_8822B) & BIT_MASK_MACID1_8822B) +#define BIT_SET_MACID1_8822B(x, v) \ + (BIT_CLEAR_MACID1_8822B(x) | BIT_MACID1_8822B(v)) /* 2 REG_BSSID1_8822B */ #define BIT_SHIFT_BSSID1_8822B 0 #define BIT_MASK_BSSID1_8822B 0xffffffffffffL -#define BIT_BSSID1_8822B(x) (((x) & BIT_MASK_BSSID1_8822B) << BIT_SHIFT_BSSID1_8822B) -#define BIT_GET_BSSID1_8822B(x) (((x) >> BIT_SHIFT_BSSID1_8822B) & BIT_MASK_BSSID1_8822B) - - +#define BIT_BSSID1_8822B(x) \ + (((x) & BIT_MASK_BSSID1_8822B) << BIT_SHIFT_BSSID1_8822B) +#define BITS_BSSID1_8822B (BIT_MASK_BSSID1_8822B << BIT_SHIFT_BSSID1_8822B) +#define BIT_CLEAR_BSSID1_8822B(x) ((x) & (~BITS_BSSID1_8822B)) +#define BIT_GET_BSSID1_8822B(x) \ + (((x) >> BIT_SHIFT_BSSID1_8822B) & BIT_MASK_BSSID1_8822B) +#define BIT_SET_BSSID1_8822B(x, v) \ + (BIT_CLEAR_BSSID1_8822B(x) | BIT_BSSID1_8822B(v)) /* 2 REG_BCN_PSR_RPT1_8822B */ #define BIT_SHIFT_DTIM_CNT1_8822B 24 #define BIT_MASK_DTIM_CNT1_8822B 0xff -#define BIT_DTIM_CNT1_8822B(x) (((x) & BIT_MASK_DTIM_CNT1_8822B) << BIT_SHIFT_DTIM_CNT1_8822B) -#define BIT_GET_DTIM_CNT1_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8822B) & BIT_MASK_DTIM_CNT1_8822B) - - +#define BIT_DTIM_CNT1_8822B(x) \ + (((x) & BIT_MASK_DTIM_CNT1_8822B) << BIT_SHIFT_DTIM_CNT1_8822B) +#define BITS_DTIM_CNT1_8822B \ + (BIT_MASK_DTIM_CNT1_8822B << BIT_SHIFT_DTIM_CNT1_8822B) +#define BIT_CLEAR_DTIM_CNT1_8822B(x) ((x) & (~BITS_DTIM_CNT1_8822B)) +#define BIT_GET_DTIM_CNT1_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT1_8822B) & BIT_MASK_DTIM_CNT1_8822B) +#define BIT_SET_DTIM_CNT1_8822B(x, v) \ + (BIT_CLEAR_DTIM_CNT1_8822B(x) | BIT_DTIM_CNT1_8822B(v)) #define BIT_SHIFT_DTIM_PERIOD1_8822B 16 #define BIT_MASK_DTIM_PERIOD1_8822B 0xff -#define BIT_DTIM_PERIOD1_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD1_8822B) << BIT_SHIFT_DTIM_PERIOD1_8822B) -#define BIT_GET_DTIM_PERIOD1_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8822B) & BIT_MASK_DTIM_PERIOD1_8822B) - +#define BIT_DTIM_PERIOD1_8822B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD1_8822B) << BIT_SHIFT_DTIM_PERIOD1_8822B) +#define BITS_DTIM_PERIOD1_8822B \ + (BIT_MASK_DTIM_PERIOD1_8822B << BIT_SHIFT_DTIM_PERIOD1_8822B) +#define BIT_CLEAR_DTIM_PERIOD1_8822B(x) ((x) & (~BITS_DTIM_PERIOD1_8822B)) +#define BIT_GET_DTIM_PERIOD1_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD1_8822B) & BIT_MASK_DTIM_PERIOD1_8822B) +#define BIT_SET_DTIM_PERIOD1_8822B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD1_8822B(x) | BIT_DTIM_PERIOD1_8822B(v)) #define BIT_DTIM1_8822B BIT(15) #define BIT_TIM1_8822B BIT(14) #define BIT_SHIFT_PS_AID_1_8822B 0 #define BIT_MASK_PS_AID_1_8822B 0x7ff -#define BIT_PS_AID_1_8822B(x) (((x) & BIT_MASK_PS_AID_1_8822B) << BIT_SHIFT_PS_AID_1_8822B) -#define BIT_GET_PS_AID_1_8822B(x) (((x) >> BIT_SHIFT_PS_AID_1_8822B) & BIT_MASK_PS_AID_1_8822B) - - +#define BIT_PS_AID_1_8822B(x) \ + (((x) & BIT_MASK_PS_AID_1_8822B) << BIT_SHIFT_PS_AID_1_8822B) +#define BITS_PS_AID_1_8822B \ + (BIT_MASK_PS_AID_1_8822B << BIT_SHIFT_PS_AID_1_8822B) +#define BIT_CLEAR_PS_AID_1_8822B(x) ((x) & (~BITS_PS_AID_1_8822B)) +#define BIT_GET_PS_AID_1_8822B(x) \ + (((x) >> BIT_SHIFT_PS_AID_1_8822B) & BIT_MASK_PS_AID_1_8822B) +#define BIT_SET_PS_AID_1_8822B(x, v) \ + (BIT_CLEAR_PS_AID_1_8822B(x) | BIT_PS_AID_1_8822B(v)) /* 2 REG_ASSOCIATED_BFMEE_SEL_8822B */ #define BIT_TXUSER_ID1_8822B BIT(25) @@ -9984,39 +15914,78 @@ #define BIT_SHIFT_AID1_8822B 16 #define BIT_MASK_AID1_8822B 0x1ff #define BIT_AID1_8822B(x) (((x) & BIT_MASK_AID1_8822B) << BIT_SHIFT_AID1_8822B) -#define BIT_GET_AID1_8822B(x) (((x) >> BIT_SHIFT_AID1_8822B) & BIT_MASK_AID1_8822B) - +#define BITS_AID1_8822B (BIT_MASK_AID1_8822B << BIT_SHIFT_AID1_8822B) +#define BIT_CLEAR_AID1_8822B(x) ((x) & (~BITS_AID1_8822B)) +#define BIT_GET_AID1_8822B(x) \ + (((x) >> BIT_SHIFT_AID1_8822B) & BIT_MASK_AID1_8822B) +#define BIT_SET_AID1_8822B(x, v) (BIT_CLEAR_AID1_8822B(x) | BIT_AID1_8822B(v)) #define BIT_TXUSER_ID0_8822B BIT(9) #define BIT_SHIFT_AID0_8822B 0 #define BIT_MASK_AID0_8822B 0x1ff #define BIT_AID0_8822B(x) (((x) & BIT_MASK_AID0_8822B) << BIT_SHIFT_AID0_8822B) -#define BIT_GET_AID0_8822B(x) (((x) >> BIT_SHIFT_AID0_8822B) & BIT_MASK_AID0_8822B) - - +#define BITS_AID0_8822B (BIT_MASK_AID0_8822B << BIT_SHIFT_AID0_8822B) +#define BIT_CLEAR_AID0_8822B(x) ((x) & (~BITS_AID0_8822B)) +#define BIT_GET_AID0_8822B(x) \ + (((x) >> BIT_SHIFT_AID0_8822B) & BIT_MASK_AID0_8822B) +#define BIT_SET_AID0_8822B(x, v) (BIT_CLEAR_AID0_8822B(x) | BIT_AID0_8822B(v)) /* 2 REG_SND_PTCL_CTRL_8822B */ #define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B 24 #define BIT_MASK_NDP_RX_STANDBY_TIMER_8822B 0xff -#define BIT_NDP_RX_STANDBY_TIMER_8822B(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) -#define BIT_GET_NDP_RX_STANDBY_TIMER_8822B(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B) - - - -#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B 16 -#define BIT_MASK_CSI_RPT_OFFSET_HT_8822B 0xff -#define BIT_CSI_RPT_OFFSET_HT_8822B(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8822B) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B) -#define BIT_GET_CSI_RPT_OFFSET_HT_8822B(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B) & BIT_MASK_CSI_RPT_OFFSET_HT_8822B) - - - -#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B 8 -#define BIT_MASK_R_WMAC_VHT_CATEGORY_8822B 0xff -#define BIT_R_WMAC_VHT_CATEGORY_8822B(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8822B) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B) -#define BIT_GET_R_WMAC_VHT_CATEGORY_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B) & BIT_MASK_R_WMAC_VHT_CATEGORY_8822B) - +#define BIT_NDP_RX_STANDBY_TIMER_8822B(x) \ + (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B) \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) +#define BITS_NDP_RX_STANDBY_TIMER_8822B \ + (BIT_MASK_NDP_RX_STANDBY_TIMER_8822B \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822B(x) \ + ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8822B)) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) & \ + BIT_MASK_NDP_RX_STANDBY_TIMER_8822B) +#define BIT_SET_NDP_RX_STANDBY_TIMER_8822B(x, v) \ + (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822B(x) | \ + BIT_NDP_RX_STANDBY_TIMER_8822B(v)) + +#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B 16 +#define BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B 0x3f +#define BIT_CSI_RPT_OFFSET_HT_V1_8822B(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B) \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B) +#define BITS_CSI_RPT_OFFSET_HT_V1_8822B \ + (BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822B(x) \ + ((x) & (~BITS_CSI_RPT_OFFSET_HT_V1_8822B)) +#define BIT_GET_CSI_RPT_OFFSET_HT_V1_8822B(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B) & \ + BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B) +#define BIT_SET_CSI_RPT_OFFSET_HT_V1_8822B(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822B(x) | \ + BIT_CSI_RPT_OFFSET_HT_V1_8822B(v)) + +#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8822B BIT(15) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS_8822B BIT(14) + +#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B 8 +#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B 0x3f +#define BIT_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) \ + (((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B) \ + << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B) +#define BITS_R_CSI_RPT_OFFSET_VHT_V1_8822B \ + (BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B \ + << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B) +#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) \ + ((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1_8822B)) +#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) \ + (((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B) & \ + BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B) +#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1_8822B(x, v) \ + (BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) | \ + BIT_R_CSI_RPT_OFFSET_VHT_V1_8822B(v)) #define BIT_R_WMAC_USE_NSTS_8822B BIT(7) #define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8822B BIT(6) @@ -10036,24 +16005,54 @@ #define BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B 6 #define BIT_MASK_R_WMAC_NSARP_MODEN_8822B 0x3 -#define BIT_R_WMAC_NSARP_MODEN_8822B(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) -#define BIT_GET_R_WMAC_NSARP_MODEN_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B) - - +#define BIT_R_WMAC_NSARP_MODEN_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B) \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) +#define BITS_R_WMAC_NSARP_MODEN_8822B \ + (BIT_MASK_R_WMAC_NSARP_MODEN_8822B \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8822B(x) \ + ((x) & (~BITS_R_WMAC_NSARP_MODEN_8822B)) +#define BIT_GET_R_WMAC_NSARP_MODEN_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) & \ + BIT_MASK_R_WMAC_NSARP_MODEN_8822B) +#define BIT_SET_R_WMAC_NSARP_MODEN_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_MODEN_8822B(x) | \ + BIT_R_WMAC_NSARP_MODEN_8822B(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B 4 #define BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B 0x3 -#define BIT_R_WMAC_NSARP_RSPFTP_8822B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) -#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) - - +#define BIT_R_WMAC_NSARP_RSPFTP_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) +#define BITS_R_WMAC_NSARP_RSPFTP_8822B \ + (BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822B(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8822B)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) & \ + BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) +#define BIT_SET_R_WMAC_NSARP_RSPFTP_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822B(x) | \ + BIT_R_WMAC_NSARP_RSPFTP_8822B(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B 0 #define BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B 0xf -#define BIT_R_WMAC_NSARP_RSPSEC_8822B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) -#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) - - +#define BIT_R_WMAC_NSARP_RSPSEC_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) +#define BITS_R_WMAC_NSARP_RSPSEC_8822B \ + (BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822B(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8822B)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) & \ + BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) +#define BIT_SET_R_WMAC_NSARP_RSPSEC_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822B(x) | \ + BIT_R_WMAC_NSARP_RSPSEC_8822B(v)) /* 2 REG_NS_ARP_INFO_8822B */ #define BIT_REQ_IS_MCNS_8822B BIT(23) @@ -10064,51 +16063,101 @@ #define BIT_SHIFT_EXPRSP_SECTYPE_8822B 16 #define BIT_MASK_EXPRSP_SECTYPE_8822B 0x7 -#define BIT_EXPRSP_SECTYPE_8822B(x) (((x) & BIT_MASK_EXPRSP_SECTYPE_8822B) << BIT_SHIFT_EXPRSP_SECTYPE_8822B) -#define BIT_GET_EXPRSP_SECTYPE_8822B(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822B) & BIT_MASK_EXPRSP_SECTYPE_8822B) - - +#define BIT_EXPRSP_SECTYPE_8822B(x) \ + (((x) & BIT_MASK_EXPRSP_SECTYPE_8822B) \ + << BIT_SHIFT_EXPRSP_SECTYPE_8822B) +#define BITS_EXPRSP_SECTYPE_8822B \ + (BIT_MASK_EXPRSP_SECTYPE_8822B << BIT_SHIFT_EXPRSP_SECTYPE_8822B) +#define BIT_CLEAR_EXPRSP_SECTYPE_8822B(x) ((x) & (~BITS_EXPRSP_SECTYPE_8822B)) +#define BIT_GET_EXPRSP_SECTYPE_8822B(x) \ + (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822B) & \ + BIT_MASK_EXPRSP_SECTYPE_8822B) +#define BIT_SET_EXPRSP_SECTYPE_8822B(x, v) \ + (BIT_CLEAR_EXPRSP_SECTYPE_8822B(x) | BIT_EXPRSP_SECTYPE_8822B(v)) #define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B 8 #define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B 0xff -#define BIT_EXPRSP_CHKSM_7_TO_0_8822B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) -#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) - - +#define BIT_EXPRSP_CHKSM_7_TO_0_8822B(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) +#define BITS_EXPRSP_CHKSM_7_TO_0_8822B \ + (BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) +#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822B(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8822B)) +#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822B(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) & \ + BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) +#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8822B(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822B(x) | \ + BIT_EXPRSP_CHKSM_7_TO_0_8822B(v)) #define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B 0 #define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B 0xff -#define BIT_EXPRSP_CHKSM_15_TO_8_8822B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) -#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) - - +#define BIT_EXPRSP_CHKSM_15_TO_8_8822B(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) +#define BITS_EXPRSP_CHKSM_15_TO_8_8822B \ + (BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) +#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822B(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8822B)) +#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822B(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) & \ + BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) +#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8822B(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822B(x) | \ + BIT_EXPRSP_CHKSM_15_TO_8_8822B(v)) /* 2 REG_BEAMFORMING_INFO_NSARP_V1_8822B */ #define BIT_SHIFT_WMAC_ARPIP_8822B 0 #define BIT_MASK_WMAC_ARPIP_8822B 0xffffffffL -#define BIT_WMAC_ARPIP_8822B(x) (((x) & BIT_MASK_WMAC_ARPIP_8822B) << BIT_SHIFT_WMAC_ARPIP_8822B) -#define BIT_GET_WMAC_ARPIP_8822B(x) (((x) >> BIT_SHIFT_WMAC_ARPIP_8822B) & BIT_MASK_WMAC_ARPIP_8822B) - - +#define BIT_WMAC_ARPIP_8822B(x) \ + (((x) & BIT_MASK_WMAC_ARPIP_8822B) << BIT_SHIFT_WMAC_ARPIP_8822B) +#define BITS_WMAC_ARPIP_8822B \ + (BIT_MASK_WMAC_ARPIP_8822B << BIT_SHIFT_WMAC_ARPIP_8822B) +#define BIT_CLEAR_WMAC_ARPIP_8822B(x) ((x) & (~BITS_WMAC_ARPIP_8822B)) +#define BIT_GET_WMAC_ARPIP_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_ARPIP_8822B) & BIT_MASK_WMAC_ARPIP_8822B) +#define BIT_SET_WMAC_ARPIP_8822B(x, v) \ + (BIT_CLEAR_WMAC_ARPIP_8822B(x) | BIT_WMAC_ARPIP_8822B(v)) /* 2 REG_BEAMFORMING_INFO_NSARP_8822B */ #define BIT_SHIFT_BEAMFORMING_INFO_8822B 0 #define BIT_MASK_BEAMFORMING_INFO_8822B 0xffffffffL -#define BIT_BEAMFORMING_INFO_8822B(x) (((x) & BIT_MASK_BEAMFORMING_INFO_8822B) << BIT_SHIFT_BEAMFORMING_INFO_8822B) -#define BIT_GET_BEAMFORMING_INFO_8822B(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8822B) & BIT_MASK_BEAMFORMING_INFO_8822B) - - +#define BIT_BEAMFORMING_INFO_8822B(x) \ + (((x) & BIT_MASK_BEAMFORMING_INFO_8822B) \ + << BIT_SHIFT_BEAMFORMING_INFO_8822B) +#define BITS_BEAMFORMING_INFO_8822B \ + (BIT_MASK_BEAMFORMING_INFO_8822B << BIT_SHIFT_BEAMFORMING_INFO_8822B) +#define BIT_CLEAR_BEAMFORMING_INFO_8822B(x) \ + ((x) & (~BITS_BEAMFORMING_INFO_8822B)) +#define BIT_GET_BEAMFORMING_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8822B) & \ + BIT_MASK_BEAMFORMING_INFO_8822B) +#define BIT_SET_BEAMFORMING_INFO_8822B(x, v) \ + (BIT_CLEAR_BEAMFORMING_INFO_8822B(x) | BIT_BEAMFORMING_INFO_8822B(v)) /* 2 REG_NOT_VALID_8822B */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B 0xffffffffffffffffffffffffffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_8822B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B) - - +#define BIT_R_WMAC_IPV6_MYIPAD_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) +#define BITS_R_WMAC_IPV6_MYIPAD_8822B \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_8822B(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_8822B)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_8822B(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_8822B(v)) /* 2 REG_RSVD_0X740_8822B */ @@ -10116,17 +16165,37 @@ #define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B 4 #define BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B 0xf -#define BIT_R_WMAC_CTX_SUBTYPE_8822B(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) -#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B) - - +#define BIT_R_WMAC_CTX_SUBTYPE_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B) \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) +#define BITS_R_WMAC_CTX_SUBTYPE_8822B \ + (BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822B(x) \ + ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8822B)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) & \ + BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B) +#define BIT_SET_R_WMAC_CTX_SUBTYPE_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822B(x) | \ + BIT_R_WMAC_CTX_SUBTYPE_8822B(v)) #define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B 0 #define BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B 0xf -#define BIT_R_WMAC_RTX_SUBTYPE_8822B(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) -#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) - - +#define BIT_R_WMAC_RTX_SUBTYPE_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) +#define BITS_R_WMAC_RTX_SUBTYPE_8822B \ + (BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822B(x) \ + ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8822B)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) & \ + BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) +#define BIT_SET_R_WMAC_RTX_SUBTYPE_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822B(x) | \ + BIT_R_WMAC_RTX_SUBTYPE_8822B(v)) /* 2 REG_WMAC_SWAES_CFG_8822B */ @@ -10136,10 +16205,14 @@ #define BIT_SHIFT_TIMER_8822B 0 #define BIT_MASK_TIMER_8822B 0xff -#define BIT_TIMER_8822B(x) (((x) & BIT_MASK_TIMER_8822B) << BIT_SHIFT_TIMER_8822B) -#define BIT_GET_TIMER_8822B(x) (((x) >> BIT_SHIFT_TIMER_8822B) & BIT_MASK_TIMER_8822B) - - +#define BIT_TIMER_8822B(x) \ + (((x) & BIT_MASK_TIMER_8822B) << BIT_SHIFT_TIMER_8822B) +#define BITS_TIMER_8822B (BIT_MASK_TIMER_8822B << BIT_SHIFT_TIMER_8822B) +#define BIT_CLEAR_TIMER_8822B(x) ((x) & (~BITS_TIMER_8822B)) +#define BIT_GET_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_TIMER_8822B) & BIT_MASK_TIMER_8822B) +#define BIT_SET_TIMER_8822B(x, v) \ + (BIT_CLEAR_TIMER_8822B(x) | BIT_TIMER_8822B(v)) /* 2 REG_BT_COEX_8822B */ #define BIT_R_GNT_BT_RFC_SW_8822B BIT(12) @@ -10150,10 +16223,15 @@ #define BIT_SHIFT_R_BT_CNT_THR_8822B 0 #define BIT_MASK_R_BT_CNT_THR_8822B 0xff -#define BIT_R_BT_CNT_THR_8822B(x) (((x) & BIT_MASK_R_BT_CNT_THR_8822B) << BIT_SHIFT_R_BT_CNT_THR_8822B) -#define BIT_GET_R_BT_CNT_THR_8822B(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8822B) & BIT_MASK_R_BT_CNT_THR_8822B) - - +#define BIT_R_BT_CNT_THR_8822B(x) \ + (((x) & BIT_MASK_R_BT_CNT_THR_8822B) << BIT_SHIFT_R_BT_CNT_THR_8822B) +#define BITS_R_BT_CNT_THR_8822B \ + (BIT_MASK_R_BT_CNT_THR_8822B << BIT_SHIFT_R_BT_CNT_THR_8822B) +#define BIT_CLEAR_R_BT_CNT_THR_8822B(x) ((x) & (~BITS_R_BT_CNT_THR_8822B)) +#define BIT_GET_R_BT_CNT_THR_8822B(x) \ + (((x) >> BIT_SHIFT_R_BT_CNT_THR_8822B) & BIT_MASK_R_BT_CNT_THR_8822B) +#define BIT_SET_R_BT_CNT_THR_8822B(x, v) \ + (BIT_CLEAR_R_BT_CNT_THR_8822B(x) | BIT_R_BT_CNT_THR_8822B(v)) /* 2 REG_WLAN_ACT_MASK_CTRL_8822B */ #define BIT_WLRX_TER_BY_CTL_8822B BIT(43) @@ -10166,39 +16244,75 @@ #define BIT_SHIFT_RXMYRTS_NAV_V1_8822B 8 #define BIT_MASK_RXMYRTS_NAV_V1_8822B 0xff -#define BIT_RXMYRTS_NAV_V1_8822B(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8822B) << BIT_SHIFT_RXMYRTS_NAV_V1_8822B) -#define BIT_GET_RXMYRTS_NAV_V1_8822B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822B) & BIT_MASK_RXMYRTS_NAV_V1_8822B) - - +#define BIT_RXMYRTS_NAV_V1_8822B(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_V1_8822B) \ + << BIT_SHIFT_RXMYRTS_NAV_V1_8822B) +#define BITS_RXMYRTS_NAV_V1_8822B \ + (BIT_MASK_RXMYRTS_NAV_V1_8822B << BIT_SHIFT_RXMYRTS_NAV_V1_8822B) +#define BIT_CLEAR_RXMYRTS_NAV_V1_8822B(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8822B)) +#define BIT_GET_RXMYRTS_NAV_V1_8822B(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822B) & \ + BIT_MASK_RXMYRTS_NAV_V1_8822B) +#define BIT_SET_RXMYRTS_NAV_V1_8822B(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_V1_8822B(x) | BIT_RXMYRTS_NAV_V1_8822B(v)) #define BIT_SHIFT_RTSRST_V1_8822B 0 #define BIT_MASK_RTSRST_V1_8822B 0xff -#define BIT_RTSRST_V1_8822B(x) (((x) & BIT_MASK_RTSRST_V1_8822B) << BIT_SHIFT_RTSRST_V1_8822B) -#define BIT_GET_RTSRST_V1_8822B(x) (((x) >> BIT_SHIFT_RTSRST_V1_8822B) & BIT_MASK_RTSRST_V1_8822B) - - +#define BIT_RTSRST_V1_8822B(x) \ + (((x) & BIT_MASK_RTSRST_V1_8822B) << BIT_SHIFT_RTSRST_V1_8822B) +#define BITS_RTSRST_V1_8822B \ + (BIT_MASK_RTSRST_V1_8822B << BIT_SHIFT_RTSRST_V1_8822B) +#define BIT_CLEAR_RTSRST_V1_8822B(x) ((x) & (~BITS_RTSRST_V1_8822B)) +#define BIT_GET_RTSRST_V1_8822B(x) \ + (((x) >> BIT_SHIFT_RTSRST_V1_8822B) & BIT_MASK_RTSRST_V1_8822B) +#define BIT_SET_RTSRST_V1_8822B(x, v) \ + (BIT_CLEAR_RTSRST_V1_8822B(x) | BIT_RTSRST_V1_8822B(v)) /* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8822B */ #define BIT_SHIFT_BT_STAT_DELAY_8822B 12 #define BIT_MASK_BT_STAT_DELAY_8822B 0xf -#define BIT_BT_STAT_DELAY_8822B(x) (((x) & BIT_MASK_BT_STAT_DELAY_8822B) << BIT_SHIFT_BT_STAT_DELAY_8822B) -#define BIT_GET_BT_STAT_DELAY_8822B(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8822B) & BIT_MASK_BT_STAT_DELAY_8822B) - - +#define BIT_BT_STAT_DELAY_8822B(x) \ + (((x) & BIT_MASK_BT_STAT_DELAY_8822B) << BIT_SHIFT_BT_STAT_DELAY_8822B) +#define BITS_BT_STAT_DELAY_8822B \ + (BIT_MASK_BT_STAT_DELAY_8822B << BIT_SHIFT_BT_STAT_DELAY_8822B) +#define BIT_CLEAR_BT_STAT_DELAY_8822B(x) ((x) & (~BITS_BT_STAT_DELAY_8822B)) +#define BIT_GET_BT_STAT_DELAY_8822B(x) \ + (((x) >> BIT_SHIFT_BT_STAT_DELAY_8822B) & BIT_MASK_BT_STAT_DELAY_8822B) +#define BIT_SET_BT_STAT_DELAY_8822B(x, v) \ + (BIT_CLEAR_BT_STAT_DELAY_8822B(x) | BIT_BT_STAT_DELAY_8822B(v)) #define BIT_SHIFT_BT_TRX_INIT_DETECT_8822B 8 #define BIT_MASK_BT_TRX_INIT_DETECT_8822B 0xf -#define BIT_BT_TRX_INIT_DETECT_8822B(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822B) << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) -#define BIT_GET_BT_TRX_INIT_DETECT_8822B(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) & BIT_MASK_BT_TRX_INIT_DETECT_8822B) - - +#define BIT_BT_TRX_INIT_DETECT_8822B(x) \ + (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822B) \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) +#define BITS_BT_TRX_INIT_DETECT_8822B \ + (BIT_MASK_BT_TRX_INIT_DETECT_8822B \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) +#define BIT_CLEAR_BT_TRX_INIT_DETECT_8822B(x) \ + ((x) & (~BITS_BT_TRX_INIT_DETECT_8822B)) +#define BIT_GET_BT_TRX_INIT_DETECT_8822B(x) \ + (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) & \ + BIT_MASK_BT_TRX_INIT_DETECT_8822B) +#define BIT_SET_BT_TRX_INIT_DETECT_8822B(x, v) \ + (BIT_CLEAR_BT_TRX_INIT_DETECT_8822B(x) | \ + BIT_BT_TRX_INIT_DETECT_8822B(v)) #define BIT_SHIFT_BT_PRI_DETECT_TO_8822B 4 #define BIT_MASK_BT_PRI_DETECT_TO_8822B 0xf -#define BIT_BT_PRI_DETECT_TO_8822B(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8822B) << BIT_SHIFT_BT_PRI_DETECT_TO_8822B) -#define BIT_GET_BT_PRI_DETECT_TO_8822B(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822B) & BIT_MASK_BT_PRI_DETECT_TO_8822B) - +#define BIT_BT_PRI_DETECT_TO_8822B(x) \ + (((x) & BIT_MASK_BT_PRI_DETECT_TO_8822B) \ + << BIT_SHIFT_BT_PRI_DETECT_TO_8822B) +#define BITS_BT_PRI_DETECT_TO_8822B \ + (BIT_MASK_BT_PRI_DETECT_TO_8822B << BIT_SHIFT_BT_PRI_DETECT_TO_8822B) +#define BIT_CLEAR_BT_PRI_DETECT_TO_8822B(x) \ + ((x) & (~BITS_BT_PRI_DETECT_TO_8822B)) +#define BIT_GET_BT_PRI_DETECT_TO_8822B(x) \ + (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822B) & \ + BIT_MASK_BT_PRI_DETECT_TO_8822B) +#define BIT_SET_BT_PRI_DETECT_TO_8822B(x, v) \ + (BIT_CLEAR_BT_PRI_DETECT_TO_8822B(x) | BIT_BT_PRI_DETECT_TO_8822B(v)) #define BIT_R_GRANTALL_WLMASK_8822B BIT(3) #define BIT_STATIS_BT_EN_8822B BIT(2) @@ -10209,53 +16323,99 @@ #define BIT_SHIFT_STATIS_BT_LO_RX_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_STATIS_BT_LO_RX_8822B 0xffff -#define BIT_STATIS_BT_LO_RX_8822B(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_8822B) << BIT_SHIFT_STATIS_BT_LO_RX_8822B) -#define BIT_GET_STATIS_BT_LO_RX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8822B) & BIT_MASK_STATIS_BT_LO_RX_8822B) - - +#define BIT_STATIS_BT_LO_RX_8822B(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX_8822B) \ + << BIT_SHIFT_STATIS_BT_LO_RX_8822B) +#define BITS_STATIS_BT_LO_RX_8822B \ + (BIT_MASK_STATIS_BT_LO_RX_8822B << BIT_SHIFT_STATIS_BT_LO_RX_8822B) +#define BIT_CLEAR_STATIS_BT_LO_RX_8822B(x) ((x) & (~BITS_STATIS_BT_LO_RX_8822B)) +#define BIT_GET_STATIS_BT_LO_RX_8822B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8822B) & \ + BIT_MASK_STATIS_BT_LO_RX_8822B) +#define BIT_SET_STATIS_BT_LO_RX_8822B(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX_8822B(x) | BIT_STATIS_BT_LO_RX_8822B(v)) #define BIT_SHIFT_STATIS_BT_LO_TX_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_STATIS_BT_LO_TX_8822B 0xffff -#define BIT_STATIS_BT_LO_TX_8822B(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_8822B) << BIT_SHIFT_STATIS_BT_LO_TX_8822B) -#define BIT_GET_STATIS_BT_LO_TX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8822B) & BIT_MASK_STATIS_BT_LO_TX_8822B) - - +#define BIT_STATIS_BT_LO_TX_8822B(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX_8822B) \ + << BIT_SHIFT_STATIS_BT_LO_TX_8822B) +#define BITS_STATIS_BT_LO_TX_8822B \ + (BIT_MASK_STATIS_BT_LO_TX_8822B << BIT_SHIFT_STATIS_BT_LO_TX_8822B) +#define BIT_CLEAR_STATIS_BT_LO_TX_8822B(x) ((x) & (~BITS_STATIS_BT_LO_TX_8822B)) +#define BIT_GET_STATIS_BT_LO_TX_8822B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8822B) & \ + BIT_MASK_STATIS_BT_LO_TX_8822B) +#define BIT_SET_STATIS_BT_LO_TX_8822B(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX_8822B(x) | BIT_STATIS_BT_LO_TX_8822B(v)) #define BIT_SHIFT_STATIS_BT_HI_RX_8822B 16 #define BIT_MASK_STATIS_BT_HI_RX_8822B 0xffff -#define BIT_STATIS_BT_HI_RX_8822B(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8822B) << BIT_SHIFT_STATIS_BT_HI_RX_8822B) -#define BIT_GET_STATIS_BT_HI_RX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822B) & BIT_MASK_STATIS_BT_HI_RX_8822B) - - +#define BIT_STATIS_BT_HI_RX_8822B(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_RX_8822B) \ + << BIT_SHIFT_STATIS_BT_HI_RX_8822B) +#define BITS_STATIS_BT_HI_RX_8822B \ + (BIT_MASK_STATIS_BT_HI_RX_8822B << BIT_SHIFT_STATIS_BT_HI_RX_8822B) +#define BIT_CLEAR_STATIS_BT_HI_RX_8822B(x) ((x) & (~BITS_STATIS_BT_HI_RX_8822B)) +#define BIT_GET_STATIS_BT_HI_RX_8822B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822B) & \ + BIT_MASK_STATIS_BT_HI_RX_8822B) +#define BIT_SET_STATIS_BT_HI_RX_8822B(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_RX_8822B(x) | BIT_STATIS_BT_HI_RX_8822B(v)) #define BIT_SHIFT_STATIS_BT_HI_TX_8822B 0 #define BIT_MASK_STATIS_BT_HI_TX_8822B 0xffff -#define BIT_STATIS_BT_HI_TX_8822B(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8822B) << BIT_SHIFT_STATIS_BT_HI_TX_8822B) -#define BIT_GET_STATIS_BT_HI_TX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822B) & BIT_MASK_STATIS_BT_HI_TX_8822B) - - +#define BIT_STATIS_BT_HI_TX_8822B(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_TX_8822B) \ + << BIT_SHIFT_STATIS_BT_HI_TX_8822B) +#define BITS_STATIS_BT_HI_TX_8822B \ + (BIT_MASK_STATIS_BT_HI_TX_8822B << BIT_SHIFT_STATIS_BT_HI_TX_8822B) +#define BIT_CLEAR_STATIS_BT_HI_TX_8822B(x) ((x) & (~BITS_STATIS_BT_HI_TX_8822B)) +#define BIT_GET_STATIS_BT_HI_TX_8822B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822B) & \ + BIT_MASK_STATIS_BT_HI_TX_8822B) +#define BIT_SET_STATIS_BT_HI_TX_8822B(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_TX_8822B(x) | BIT_STATIS_BT_HI_TX_8822B(v)) /* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8822B */ #define BIT_SHIFT_R_BT_CMD_RPT_8822B 16 #define BIT_MASK_R_BT_CMD_RPT_8822B 0xffff -#define BIT_R_BT_CMD_RPT_8822B(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8822B) << BIT_SHIFT_R_BT_CMD_RPT_8822B) -#define BIT_GET_R_BT_CMD_RPT_8822B(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822B) & BIT_MASK_R_BT_CMD_RPT_8822B) - - +#define BIT_R_BT_CMD_RPT_8822B(x) \ + (((x) & BIT_MASK_R_BT_CMD_RPT_8822B) << BIT_SHIFT_R_BT_CMD_RPT_8822B) +#define BITS_R_BT_CMD_RPT_8822B \ + (BIT_MASK_R_BT_CMD_RPT_8822B << BIT_SHIFT_R_BT_CMD_RPT_8822B) +#define BIT_CLEAR_R_BT_CMD_RPT_8822B(x) ((x) & (~BITS_R_BT_CMD_RPT_8822B)) +#define BIT_GET_R_BT_CMD_RPT_8822B(x) \ + (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822B) & BIT_MASK_R_BT_CMD_RPT_8822B) +#define BIT_SET_R_BT_CMD_RPT_8822B(x, v) \ + (BIT_CLEAR_R_BT_CMD_RPT_8822B(x) | BIT_R_BT_CMD_RPT_8822B(v)) #define BIT_SHIFT_R_RPT_FROM_BT_8822B 8 #define BIT_MASK_R_RPT_FROM_BT_8822B 0xff -#define BIT_R_RPT_FROM_BT_8822B(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8822B) << BIT_SHIFT_R_RPT_FROM_BT_8822B) -#define BIT_GET_R_RPT_FROM_BT_8822B(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822B) & BIT_MASK_R_RPT_FROM_BT_8822B) - - +#define BIT_R_RPT_FROM_BT_8822B(x) \ + (((x) & BIT_MASK_R_RPT_FROM_BT_8822B) << BIT_SHIFT_R_RPT_FROM_BT_8822B) +#define BITS_R_RPT_FROM_BT_8822B \ + (BIT_MASK_R_RPT_FROM_BT_8822B << BIT_SHIFT_R_RPT_FROM_BT_8822B) +#define BIT_CLEAR_R_RPT_FROM_BT_8822B(x) ((x) & (~BITS_R_RPT_FROM_BT_8822B)) +#define BIT_GET_R_RPT_FROM_BT_8822B(x) \ + (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822B) & BIT_MASK_R_RPT_FROM_BT_8822B) +#define BIT_SET_R_RPT_FROM_BT_8822B(x, v) \ + (BIT_CLEAR_R_RPT_FROM_BT_8822B(x) | BIT_R_RPT_FROM_BT_8822B(v)) #define BIT_SHIFT_BT_HID_ISR_SET_8822B 6 #define BIT_MASK_BT_HID_ISR_SET_8822B 0x3 -#define BIT_BT_HID_ISR_SET_8822B(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8822B) << BIT_SHIFT_BT_HID_ISR_SET_8822B) -#define BIT_GET_BT_HID_ISR_SET_8822B(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822B) & BIT_MASK_BT_HID_ISR_SET_8822B) - +#define BIT_BT_HID_ISR_SET_8822B(x) \ + (((x) & BIT_MASK_BT_HID_ISR_SET_8822B) \ + << BIT_SHIFT_BT_HID_ISR_SET_8822B) +#define BITS_BT_HID_ISR_SET_8822B \ + (BIT_MASK_BT_HID_ISR_SET_8822B << BIT_SHIFT_BT_HID_ISR_SET_8822B) +#define BIT_CLEAR_BT_HID_ISR_SET_8822B(x) ((x) & (~BITS_BT_HID_ISR_SET_8822B)) +#define BIT_GET_BT_HID_ISR_SET_8822B(x) \ + (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822B) & \ + BIT_MASK_BT_HID_ISR_SET_8822B) +#define BIT_SET_BT_HID_ISR_SET_8822B(x, v) \ + (BIT_CLEAR_BT_HID_ISR_SET_8822B(x) | BIT_BT_HID_ISR_SET_8822B(v)) #define BIT_TDMA_BT_START_NOTIFY_8822B BIT(5) #define BIT_ENABLE_TDMA_FW_MODE_8822B BIT(4) @@ -10268,31 +16428,54 @@ #define BIT_SHIFT_BT_PROFILE_8822B 24 #define BIT_MASK_BT_PROFILE_8822B 0xff -#define BIT_BT_PROFILE_8822B(x) (((x) & BIT_MASK_BT_PROFILE_8822B) << BIT_SHIFT_BT_PROFILE_8822B) -#define BIT_GET_BT_PROFILE_8822B(x) (((x) >> BIT_SHIFT_BT_PROFILE_8822B) & BIT_MASK_BT_PROFILE_8822B) - - +#define BIT_BT_PROFILE_8822B(x) \ + (((x) & BIT_MASK_BT_PROFILE_8822B) << BIT_SHIFT_BT_PROFILE_8822B) +#define BITS_BT_PROFILE_8822B \ + (BIT_MASK_BT_PROFILE_8822B << BIT_SHIFT_BT_PROFILE_8822B) +#define BIT_CLEAR_BT_PROFILE_8822B(x) ((x) & (~BITS_BT_PROFILE_8822B)) +#define BIT_GET_BT_PROFILE_8822B(x) \ + (((x) >> BIT_SHIFT_BT_PROFILE_8822B) & BIT_MASK_BT_PROFILE_8822B) +#define BIT_SET_BT_PROFILE_8822B(x, v) \ + (BIT_CLEAR_BT_PROFILE_8822B(x) | BIT_BT_PROFILE_8822B(v)) #define BIT_SHIFT_BT_POWER_8822B 16 #define BIT_MASK_BT_POWER_8822B 0xff -#define BIT_BT_POWER_8822B(x) (((x) & BIT_MASK_BT_POWER_8822B) << BIT_SHIFT_BT_POWER_8822B) -#define BIT_GET_BT_POWER_8822B(x) (((x) >> BIT_SHIFT_BT_POWER_8822B) & BIT_MASK_BT_POWER_8822B) - - +#define BIT_BT_POWER_8822B(x) \ + (((x) & BIT_MASK_BT_POWER_8822B) << BIT_SHIFT_BT_POWER_8822B) +#define BITS_BT_POWER_8822B \ + (BIT_MASK_BT_POWER_8822B << BIT_SHIFT_BT_POWER_8822B) +#define BIT_CLEAR_BT_POWER_8822B(x) ((x) & (~BITS_BT_POWER_8822B)) +#define BIT_GET_BT_POWER_8822B(x) \ + (((x) >> BIT_SHIFT_BT_POWER_8822B) & BIT_MASK_BT_POWER_8822B) +#define BIT_SET_BT_POWER_8822B(x, v) \ + (BIT_CLEAR_BT_POWER_8822B(x) | BIT_BT_POWER_8822B(v)) #define BIT_SHIFT_BT_PREDECT_STATUS_8822B 8 #define BIT_MASK_BT_PREDECT_STATUS_8822B 0xff -#define BIT_BT_PREDECT_STATUS_8822B(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8822B) << BIT_SHIFT_BT_PREDECT_STATUS_8822B) -#define BIT_GET_BT_PREDECT_STATUS_8822B(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822B) & BIT_MASK_BT_PREDECT_STATUS_8822B) - - +#define BIT_BT_PREDECT_STATUS_8822B(x) \ + (((x) & BIT_MASK_BT_PREDECT_STATUS_8822B) \ + << BIT_SHIFT_BT_PREDECT_STATUS_8822B) +#define BITS_BT_PREDECT_STATUS_8822B \ + (BIT_MASK_BT_PREDECT_STATUS_8822B << BIT_SHIFT_BT_PREDECT_STATUS_8822B) +#define BIT_CLEAR_BT_PREDECT_STATUS_8822B(x) \ + ((x) & (~BITS_BT_PREDECT_STATUS_8822B)) +#define BIT_GET_BT_PREDECT_STATUS_8822B(x) \ + (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822B) & \ + BIT_MASK_BT_PREDECT_STATUS_8822B) +#define BIT_SET_BT_PREDECT_STATUS_8822B(x, v) \ + (BIT_CLEAR_BT_PREDECT_STATUS_8822B(x) | BIT_BT_PREDECT_STATUS_8822B(v)) #define BIT_SHIFT_BT_CMD_INFO_8822B 0 #define BIT_MASK_BT_CMD_INFO_8822B 0xff -#define BIT_BT_CMD_INFO_8822B(x) (((x) & BIT_MASK_BT_CMD_INFO_8822B) << BIT_SHIFT_BT_CMD_INFO_8822B) -#define BIT_GET_BT_CMD_INFO_8822B(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8822B) & BIT_MASK_BT_CMD_INFO_8822B) - - +#define BIT_BT_CMD_INFO_8822B(x) \ + (((x) & BIT_MASK_BT_CMD_INFO_8822B) << BIT_SHIFT_BT_CMD_INFO_8822B) +#define BITS_BT_CMD_INFO_8822B \ + (BIT_MASK_BT_CMD_INFO_8822B << BIT_SHIFT_BT_CMD_INFO_8822B) +#define BIT_CLEAR_BT_CMD_INFO_8822B(x) ((x) & (~BITS_BT_CMD_INFO_8822B)) +#define BIT_GET_BT_CMD_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_BT_CMD_INFO_8822B) & BIT_MASK_BT_CMD_INFO_8822B) +#define BIT_SET_BT_CMD_INFO_8822B(x, v) \ + (BIT_CLEAR_BT_CMD_INFO_8822B(x) | BIT_BT_CMD_INFO_8822B(v)) /* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8822B */ #define BIT_EN_MAC_NULL_PKT_NOTIFY_8822B BIT(31) @@ -10306,41 +16489,65 @@ #define BIT_SHIFT_WLAN_RPT_DATA_8822B 16 #define BIT_MASK_WLAN_RPT_DATA_8822B 0xff -#define BIT_WLAN_RPT_DATA_8822B(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8822B) << BIT_SHIFT_WLAN_RPT_DATA_8822B) -#define BIT_GET_WLAN_RPT_DATA_8822B(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822B) & BIT_MASK_WLAN_RPT_DATA_8822B) - - +#define BIT_WLAN_RPT_DATA_8822B(x) \ + (((x) & BIT_MASK_WLAN_RPT_DATA_8822B) << BIT_SHIFT_WLAN_RPT_DATA_8822B) +#define BITS_WLAN_RPT_DATA_8822B \ + (BIT_MASK_WLAN_RPT_DATA_8822B << BIT_SHIFT_WLAN_RPT_DATA_8822B) +#define BIT_CLEAR_WLAN_RPT_DATA_8822B(x) ((x) & (~BITS_WLAN_RPT_DATA_8822B)) +#define BIT_GET_WLAN_RPT_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822B) & BIT_MASK_WLAN_RPT_DATA_8822B) +#define BIT_SET_WLAN_RPT_DATA_8822B(x, v) \ + (BIT_CLEAR_WLAN_RPT_DATA_8822B(x) | BIT_WLAN_RPT_DATA_8822B(v)) #define BIT_SHIFT_CMD_ID_8822B 8 #define BIT_MASK_CMD_ID_8822B 0xff -#define BIT_CMD_ID_8822B(x) (((x) & BIT_MASK_CMD_ID_8822B) << BIT_SHIFT_CMD_ID_8822B) -#define BIT_GET_CMD_ID_8822B(x) (((x) >> BIT_SHIFT_CMD_ID_8822B) & BIT_MASK_CMD_ID_8822B) - - +#define BIT_CMD_ID_8822B(x) \ + (((x) & BIT_MASK_CMD_ID_8822B) << BIT_SHIFT_CMD_ID_8822B) +#define BITS_CMD_ID_8822B (BIT_MASK_CMD_ID_8822B << BIT_SHIFT_CMD_ID_8822B) +#define BIT_CLEAR_CMD_ID_8822B(x) ((x) & (~BITS_CMD_ID_8822B)) +#define BIT_GET_CMD_ID_8822B(x) \ + (((x) >> BIT_SHIFT_CMD_ID_8822B) & BIT_MASK_CMD_ID_8822B) +#define BIT_SET_CMD_ID_8822B(x, v) \ + (BIT_CLEAR_CMD_ID_8822B(x) | BIT_CMD_ID_8822B(v)) #define BIT_SHIFT_BT_DATA_8822B 0 #define BIT_MASK_BT_DATA_8822B 0xff -#define BIT_BT_DATA_8822B(x) (((x) & BIT_MASK_BT_DATA_8822B) << BIT_SHIFT_BT_DATA_8822B) -#define BIT_GET_BT_DATA_8822B(x) (((x) >> BIT_SHIFT_BT_DATA_8822B) & BIT_MASK_BT_DATA_8822B) - - +#define BIT_BT_DATA_8822B(x) \ + (((x) & BIT_MASK_BT_DATA_8822B) << BIT_SHIFT_BT_DATA_8822B) +#define BITS_BT_DATA_8822B (BIT_MASK_BT_DATA_8822B << BIT_SHIFT_BT_DATA_8822B) +#define BIT_CLEAR_BT_DATA_8822B(x) ((x) & (~BITS_BT_DATA_8822B)) +#define BIT_GET_BT_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_BT_DATA_8822B) & BIT_MASK_BT_DATA_8822B) +#define BIT_SET_BT_DATA_8822B(x, v) \ + (BIT_CLEAR_BT_DATA_8822B(x) | BIT_BT_DATA_8822B(v)) /* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B */ #define BIT_SHIFT_WLAN_RPT_TO_8822B 0 #define BIT_MASK_WLAN_RPT_TO_8822B 0xff -#define BIT_WLAN_RPT_TO_8822B(x) (((x) & BIT_MASK_WLAN_RPT_TO_8822B) << BIT_SHIFT_WLAN_RPT_TO_8822B) -#define BIT_GET_WLAN_RPT_TO_8822B(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8822B) & BIT_MASK_WLAN_RPT_TO_8822B) - - +#define BIT_WLAN_RPT_TO_8822B(x) \ + (((x) & BIT_MASK_WLAN_RPT_TO_8822B) << BIT_SHIFT_WLAN_RPT_TO_8822B) +#define BITS_WLAN_RPT_TO_8822B \ + (BIT_MASK_WLAN_RPT_TO_8822B << BIT_SHIFT_WLAN_RPT_TO_8822B) +#define BIT_CLEAR_WLAN_RPT_TO_8822B(x) ((x) & (~BITS_WLAN_RPT_TO_8822B)) +#define BIT_GET_WLAN_RPT_TO_8822B(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_TO_8822B) & BIT_MASK_WLAN_RPT_TO_8822B) +#define BIT_SET_WLAN_RPT_TO_8822B(x, v) \ + (BIT_CLEAR_WLAN_RPT_TO_8822B(x) | BIT_WLAN_RPT_TO_8822B(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B */ #define BIT_SHIFT_ISOLATION_CHK_8822B 1 #define BIT_MASK_ISOLATION_CHK_8822B 0x7fffffffffffffffffffL -#define BIT_ISOLATION_CHK_8822B(x) (((x) & BIT_MASK_ISOLATION_CHK_8822B) << BIT_SHIFT_ISOLATION_CHK_8822B) -#define BIT_GET_ISOLATION_CHK_8822B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_8822B) & BIT_MASK_ISOLATION_CHK_8822B) - +#define BIT_ISOLATION_CHK_8822B(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_8822B) << BIT_SHIFT_ISOLATION_CHK_8822B) +#define BITS_ISOLATION_CHK_8822B \ + (BIT_MASK_ISOLATION_CHK_8822B << BIT_SHIFT_ISOLATION_CHK_8822B) +#define BIT_CLEAR_ISOLATION_CHK_8822B(x) ((x) & (~BITS_ISOLATION_CHK_8822B)) +#define BIT_GET_ISOLATION_CHK_8822B(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_8822B) & BIT_MASK_ISOLATION_CHK_8822B) +#define BIT_SET_ISOLATION_CHK_8822B(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_8822B(x) | BIT_ISOLATION_CHK_8822B(v)) #define BIT_ISOLATION_EN_8822B BIT(0) @@ -10358,25 +16565,45 @@ #define BIT_SHIFT_BT_TIME_8822B 6 #define BIT_MASK_BT_TIME_8822B 0x3ffffff -#define BIT_BT_TIME_8822B(x) (((x) & BIT_MASK_BT_TIME_8822B) << BIT_SHIFT_BT_TIME_8822B) -#define BIT_GET_BT_TIME_8822B(x) (((x) >> BIT_SHIFT_BT_TIME_8822B) & BIT_MASK_BT_TIME_8822B) - - +#define BIT_BT_TIME_8822B(x) \ + (((x) & BIT_MASK_BT_TIME_8822B) << BIT_SHIFT_BT_TIME_8822B) +#define BITS_BT_TIME_8822B (BIT_MASK_BT_TIME_8822B << BIT_SHIFT_BT_TIME_8822B) +#define BIT_CLEAR_BT_TIME_8822B(x) ((x) & (~BITS_BT_TIME_8822B)) +#define BIT_GET_BT_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_BT_TIME_8822B) & BIT_MASK_BT_TIME_8822B) +#define BIT_SET_BT_TIME_8822B(x, v) \ + (BIT_CLEAR_BT_TIME_8822B(x) | BIT_BT_TIME_8822B(v)) #define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B 0 #define BIT_MASK_BT_RPT_SAMPLE_RATE_8822B 0x3f -#define BIT_BT_RPT_SAMPLE_RATE_8822B(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) -#define BIT_GET_BT_RPT_SAMPLE_RATE_8822B(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) - - +#define BIT_BT_RPT_SAMPLE_RATE_8822B(x) \ + (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) +#define BITS_BT_RPT_SAMPLE_RATE_8822B \ + (BIT_MASK_BT_RPT_SAMPLE_RATE_8822B \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822B(x) \ + ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8822B)) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8822B(x) \ + (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) & \ + BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) +#define BIT_SET_BT_RPT_SAMPLE_RATE_8822B(x, v) \ + (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822B(x) | \ + BIT_BT_RPT_SAMPLE_RATE_8822B(v)) /* 2 REG_BT_ACT_REGISTER_8822B */ #define BIT_SHIFT_BT_EISR_EN_8822B 16 #define BIT_MASK_BT_EISR_EN_8822B 0xff -#define BIT_BT_EISR_EN_8822B(x) (((x) & BIT_MASK_BT_EISR_EN_8822B) << BIT_SHIFT_BT_EISR_EN_8822B) -#define BIT_GET_BT_EISR_EN_8822B(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8822B) & BIT_MASK_BT_EISR_EN_8822B) - +#define BIT_BT_EISR_EN_8822B(x) \ + (((x) & BIT_MASK_BT_EISR_EN_8822B) << BIT_SHIFT_BT_EISR_EN_8822B) +#define BITS_BT_EISR_EN_8822B \ + (BIT_MASK_BT_EISR_EN_8822B << BIT_SHIFT_BT_EISR_EN_8822B) +#define BIT_CLEAR_BT_EISR_EN_8822B(x) ((x) & (~BITS_BT_EISR_EN_8822B)) +#define BIT_GET_BT_EISR_EN_8822B(x) \ + (((x) >> BIT_SHIFT_BT_EISR_EN_8822B) & BIT_MASK_BT_EISR_EN_8822B) +#define BIT_SET_BT_EISR_EN_8822B(x, v) \ + (BIT_CLEAR_BT_EISR_EN_8822B(x) | BIT_BT_EISR_EN_8822B(v)) #define BIT_BT_ACT_FALLING_ISR_8822B BIT(10) #define BIT_BT_ACT_RISING_ISR_8822B BIT(9) @@ -10384,19 +16611,29 @@ #define BIT_SHIFT_BT_CH_8822B 0 #define BIT_MASK_BT_CH_8822B 0xff -#define BIT_BT_CH_8822B(x) (((x) & BIT_MASK_BT_CH_8822B) << BIT_SHIFT_BT_CH_8822B) -#define BIT_GET_BT_CH_8822B(x) (((x) >> BIT_SHIFT_BT_CH_8822B) & BIT_MASK_BT_CH_8822B) - - +#define BIT_BT_CH_8822B(x) \ + (((x) & BIT_MASK_BT_CH_8822B) << BIT_SHIFT_BT_CH_8822B) +#define BITS_BT_CH_8822B (BIT_MASK_BT_CH_8822B << BIT_SHIFT_BT_CH_8822B) +#define BIT_CLEAR_BT_CH_8822B(x) ((x) & (~BITS_BT_CH_8822B)) +#define BIT_GET_BT_CH_8822B(x) \ + (((x) >> BIT_SHIFT_BT_CH_8822B) & BIT_MASK_BT_CH_8822B) +#define BIT_SET_BT_CH_8822B(x, v) \ + (BIT_CLEAR_BT_CH_8822B(x) | BIT_BT_CH_8822B(v)) /* 2 REG_OBFF_CTRL_BASIC_8822B */ #define BIT_OBFF_EN_V1_8822B BIT(31) #define BIT_SHIFT_OBFF_STATE_V1_8822B 28 #define BIT_MASK_OBFF_STATE_V1_8822B 0x3 -#define BIT_OBFF_STATE_V1_8822B(x) (((x) & BIT_MASK_OBFF_STATE_V1_8822B) << BIT_SHIFT_OBFF_STATE_V1_8822B) -#define BIT_GET_OBFF_STATE_V1_8822B(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8822B) & BIT_MASK_OBFF_STATE_V1_8822B) - +#define BIT_OBFF_STATE_V1_8822B(x) \ + (((x) & BIT_MASK_OBFF_STATE_V1_8822B) << BIT_SHIFT_OBFF_STATE_V1_8822B) +#define BITS_OBFF_STATE_V1_8822B \ + (BIT_MASK_OBFF_STATE_V1_8822B << BIT_SHIFT_OBFF_STATE_V1_8822B) +#define BIT_CLEAR_OBFF_STATE_V1_8822B(x) ((x) & (~BITS_OBFF_STATE_V1_8822B)) +#define BIT_GET_OBFF_STATE_V1_8822B(x) \ + (((x) >> BIT_SHIFT_OBFF_STATE_V1_8822B) & BIT_MASK_OBFF_STATE_V1_8822B) +#define BIT_SET_OBFF_STATE_V1_8822B(x, v) \ + (BIT_CLEAR_OBFF_STATE_V1_8822B(x) | BIT_OBFF_STATE_V1_8822B(v)) #define BIT_OBFF_ACT_RXDMA_EN_8822B BIT(27) #define BIT_OBFF_BLOCK_INT_EN_8822B BIT(26) @@ -10405,30 +16642,51 @@ #define BIT_SHIFT_WAKE_MAX_PLS_8822B 20 #define BIT_MASK_WAKE_MAX_PLS_8822B 0x7 -#define BIT_WAKE_MAX_PLS_8822B(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8822B) << BIT_SHIFT_WAKE_MAX_PLS_8822B) -#define BIT_GET_WAKE_MAX_PLS_8822B(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822B) & BIT_MASK_WAKE_MAX_PLS_8822B) - - +#define BIT_WAKE_MAX_PLS_8822B(x) \ + (((x) & BIT_MASK_WAKE_MAX_PLS_8822B) << BIT_SHIFT_WAKE_MAX_PLS_8822B) +#define BITS_WAKE_MAX_PLS_8822B \ + (BIT_MASK_WAKE_MAX_PLS_8822B << BIT_SHIFT_WAKE_MAX_PLS_8822B) +#define BIT_CLEAR_WAKE_MAX_PLS_8822B(x) ((x) & (~BITS_WAKE_MAX_PLS_8822B)) +#define BIT_GET_WAKE_MAX_PLS_8822B(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822B) & BIT_MASK_WAKE_MAX_PLS_8822B) +#define BIT_SET_WAKE_MAX_PLS_8822B(x, v) \ + (BIT_CLEAR_WAKE_MAX_PLS_8822B(x) | BIT_WAKE_MAX_PLS_8822B(v)) #define BIT_SHIFT_WAKE_MIN_PLS_8822B 16 #define BIT_MASK_WAKE_MIN_PLS_8822B 0x7 -#define BIT_WAKE_MIN_PLS_8822B(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8822B) << BIT_SHIFT_WAKE_MIN_PLS_8822B) -#define BIT_GET_WAKE_MIN_PLS_8822B(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822B) & BIT_MASK_WAKE_MIN_PLS_8822B) - - +#define BIT_WAKE_MIN_PLS_8822B(x) \ + (((x) & BIT_MASK_WAKE_MIN_PLS_8822B) << BIT_SHIFT_WAKE_MIN_PLS_8822B) +#define BITS_WAKE_MIN_PLS_8822B \ + (BIT_MASK_WAKE_MIN_PLS_8822B << BIT_SHIFT_WAKE_MIN_PLS_8822B) +#define BIT_CLEAR_WAKE_MIN_PLS_8822B(x) ((x) & (~BITS_WAKE_MIN_PLS_8822B)) +#define BIT_GET_WAKE_MIN_PLS_8822B(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822B) & BIT_MASK_WAKE_MIN_PLS_8822B) +#define BIT_SET_WAKE_MIN_PLS_8822B(x, v) \ + (BIT_CLEAR_WAKE_MIN_PLS_8822B(x) | BIT_WAKE_MIN_PLS_8822B(v)) #define BIT_SHIFT_WAKE_MAX_F2F_8822B 12 #define BIT_MASK_WAKE_MAX_F2F_8822B 0x7 -#define BIT_WAKE_MAX_F2F_8822B(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8822B) << BIT_SHIFT_WAKE_MAX_F2F_8822B) -#define BIT_GET_WAKE_MAX_F2F_8822B(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822B) & BIT_MASK_WAKE_MAX_F2F_8822B) - - +#define BIT_WAKE_MAX_F2F_8822B(x) \ + (((x) & BIT_MASK_WAKE_MAX_F2F_8822B) << BIT_SHIFT_WAKE_MAX_F2F_8822B) +#define BITS_WAKE_MAX_F2F_8822B \ + (BIT_MASK_WAKE_MAX_F2F_8822B << BIT_SHIFT_WAKE_MAX_F2F_8822B) +#define BIT_CLEAR_WAKE_MAX_F2F_8822B(x) ((x) & (~BITS_WAKE_MAX_F2F_8822B)) +#define BIT_GET_WAKE_MAX_F2F_8822B(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822B) & BIT_MASK_WAKE_MAX_F2F_8822B) +#define BIT_SET_WAKE_MAX_F2F_8822B(x, v) \ + (BIT_CLEAR_WAKE_MAX_F2F_8822B(x) | BIT_WAKE_MAX_F2F_8822B(v)) #define BIT_SHIFT_WAKE_MIN_F2F_8822B 8 #define BIT_MASK_WAKE_MIN_F2F_8822B 0x7 -#define BIT_WAKE_MIN_F2F_8822B(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8822B) << BIT_SHIFT_WAKE_MIN_F2F_8822B) -#define BIT_GET_WAKE_MIN_F2F_8822B(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822B) & BIT_MASK_WAKE_MIN_F2F_8822B) - +#define BIT_WAKE_MIN_F2F_8822B(x) \ + (((x) & BIT_MASK_WAKE_MIN_F2F_8822B) << BIT_SHIFT_WAKE_MIN_F2F_8822B) +#define BITS_WAKE_MIN_F2F_8822B \ + (BIT_MASK_WAKE_MIN_F2F_8822B << BIT_SHIFT_WAKE_MIN_F2F_8822B) +#define BIT_CLEAR_WAKE_MIN_F2F_8822B(x) ((x) & (~BITS_WAKE_MIN_F2F_8822B)) +#define BIT_GET_WAKE_MIN_F2F_8822B(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822B) & BIT_MASK_WAKE_MIN_F2F_8822B) +#define BIT_SET_WAKE_MIN_F2F_8822B(x, v) \ + (BIT_CLEAR_WAKE_MIN_F2F_8822B(x) | BIT_WAKE_MIN_F2F_8822B(v)) #define BIT_APP_CPU_ACT_V1_8822B BIT(3) #define BIT_APP_OBFF_V1_8822B BIT(2) @@ -10439,31 +16697,65 @@ #define BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B 24 #define BIT_MASK_RX_HIGH_TIMER_IDX_8822B 0x7 -#define BIT_RX_HIGH_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) -#define BIT_GET_RX_HIGH_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B) - - +#define BIT_RX_HIGH_TIMER_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B) \ + << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) +#define BITS_RX_HIGH_TIMER_IDX_8822B \ + (BIT_MASK_RX_HIGH_TIMER_IDX_8822B << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8822B(x) \ + ((x) & (~BITS_RX_HIGH_TIMER_IDX_8822B)) +#define BIT_GET_RX_HIGH_TIMER_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) & \ + BIT_MASK_RX_HIGH_TIMER_IDX_8822B) +#define BIT_SET_RX_HIGH_TIMER_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_HIGH_TIMER_IDX_8822B(x) | BIT_RX_HIGH_TIMER_IDX_8822B(v)) #define BIT_SHIFT_RX_MED_TIMER_IDX_8822B 16 #define BIT_MASK_RX_MED_TIMER_IDX_8822B 0x7 -#define BIT_RX_MED_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8822B) << BIT_SHIFT_RX_MED_TIMER_IDX_8822B) -#define BIT_GET_RX_MED_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822B) & BIT_MASK_RX_MED_TIMER_IDX_8822B) - - +#define BIT_RX_MED_TIMER_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_MED_TIMER_IDX_8822B) \ + << BIT_SHIFT_RX_MED_TIMER_IDX_8822B) +#define BITS_RX_MED_TIMER_IDX_8822B \ + (BIT_MASK_RX_MED_TIMER_IDX_8822B << BIT_SHIFT_RX_MED_TIMER_IDX_8822B) +#define BIT_CLEAR_RX_MED_TIMER_IDX_8822B(x) \ + ((x) & (~BITS_RX_MED_TIMER_IDX_8822B)) +#define BIT_GET_RX_MED_TIMER_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822B) & \ + BIT_MASK_RX_MED_TIMER_IDX_8822B) +#define BIT_SET_RX_MED_TIMER_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_MED_TIMER_IDX_8822B(x) | BIT_RX_MED_TIMER_IDX_8822B(v)) #define BIT_SHIFT_RX_LOW_TIMER_IDX_8822B 8 #define BIT_MASK_RX_LOW_TIMER_IDX_8822B 0x7 -#define BIT_RX_LOW_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822B) << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) -#define BIT_GET_RX_LOW_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) & BIT_MASK_RX_LOW_TIMER_IDX_8822B) - - +#define BIT_RX_LOW_TIMER_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822B) \ + << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) +#define BITS_RX_LOW_TIMER_IDX_8822B \ + (BIT_MASK_RX_LOW_TIMER_IDX_8822B << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) +#define BIT_CLEAR_RX_LOW_TIMER_IDX_8822B(x) \ + ((x) & (~BITS_RX_LOW_TIMER_IDX_8822B)) +#define BIT_GET_RX_LOW_TIMER_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) & \ + BIT_MASK_RX_LOW_TIMER_IDX_8822B) +#define BIT_SET_RX_LOW_TIMER_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_LOW_TIMER_IDX_8822B(x) | BIT_RX_LOW_TIMER_IDX_8822B(v)) #define BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B 0 #define BIT_MASK_OBFF_INT_TIMER_IDX_8822B 0x7 -#define BIT_OBFF_INT_TIMER_IDX_8822B(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) -#define BIT_GET_OBFF_INT_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B) - - +#define BIT_OBFF_INT_TIMER_IDX_8822B(x) \ + (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B) \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) +#define BITS_OBFF_INT_TIMER_IDX_8822B \ + (BIT_MASK_OBFF_INT_TIMER_IDX_8822B \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8822B(x) \ + ((x) & (~BITS_OBFF_INT_TIMER_IDX_8822B)) +#define BIT_GET_OBFF_INT_TIMER_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) & \ + BIT_MASK_OBFF_INT_TIMER_IDX_8822B) +#define BIT_SET_OBFF_INT_TIMER_IDX_8822B(x, v) \ + (BIT_CLEAR_OBFF_INT_TIMER_IDX_8822B(x) | \ + BIT_OBFF_INT_TIMER_IDX_8822B(v)) /* 2 REG_LTR_CTRL_BASIC_8822B */ #define BIT_LTR_EN_V1_8822B BIT(31) @@ -10479,107 +16771,207 @@ #define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B 20 #define BIT_MASK_HIGH_RATE_TRIG_SEL_8822B 0x3 -#define BIT_HIGH_RATE_TRIG_SEL_8822B(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) -#define BIT_GET_HIGH_RATE_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B) - - +#define BIT_HIGH_RATE_TRIG_SEL_8822B(x) \ + (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B) \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) +#define BITS_HIGH_RATE_TRIG_SEL_8822B \ + (BIT_MASK_HIGH_RATE_TRIG_SEL_8822B \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822B(x) \ + ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8822B)) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) & \ + BIT_MASK_HIGH_RATE_TRIG_SEL_8822B) +#define BIT_SET_HIGH_RATE_TRIG_SEL_8822B(x, v) \ + (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822B(x) | \ + BIT_HIGH_RATE_TRIG_SEL_8822B(v)) #define BIT_SHIFT_MED_RATE_TRIG_SEL_8822B 18 #define BIT_MASK_MED_RATE_TRIG_SEL_8822B 0x3 -#define BIT_MED_RATE_TRIG_SEL_8822B(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822B) << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) -#define BIT_GET_MED_RATE_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) & BIT_MASK_MED_RATE_TRIG_SEL_8822B) - - +#define BIT_MED_RATE_TRIG_SEL_8822B(x) \ + (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822B) \ + << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) +#define BITS_MED_RATE_TRIG_SEL_8822B \ + (BIT_MASK_MED_RATE_TRIG_SEL_8822B << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) +#define BIT_CLEAR_MED_RATE_TRIG_SEL_8822B(x) \ + ((x) & (~BITS_MED_RATE_TRIG_SEL_8822B)) +#define BIT_GET_MED_RATE_TRIG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) & \ + BIT_MASK_MED_RATE_TRIG_SEL_8822B) +#define BIT_SET_MED_RATE_TRIG_SEL_8822B(x, v) \ + (BIT_CLEAR_MED_RATE_TRIG_SEL_8822B(x) | BIT_MED_RATE_TRIG_SEL_8822B(v)) #define BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B 16 #define BIT_MASK_LOW_RATE_TRIG_SEL_8822B 0x3 -#define BIT_LOW_RATE_TRIG_SEL_8822B(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) -#define BIT_GET_LOW_RATE_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B) - - +#define BIT_LOW_RATE_TRIG_SEL_8822B(x) \ + (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B) \ + << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) +#define BITS_LOW_RATE_TRIG_SEL_8822B \ + (BIT_MASK_LOW_RATE_TRIG_SEL_8822B << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8822B(x) \ + ((x) & (~BITS_LOW_RATE_TRIG_SEL_8822B)) +#define BIT_GET_LOW_RATE_TRIG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) & \ + BIT_MASK_LOW_RATE_TRIG_SEL_8822B) +#define BIT_SET_LOW_RATE_TRIG_SEL_8822B(x, v) \ + (BIT_CLEAR_LOW_RATE_TRIG_SEL_8822B(x) | BIT_LOW_RATE_TRIG_SEL_8822B(v)) #define BIT_SHIFT_HIGH_RATE_BD_IDX_8822B 8 #define BIT_MASK_HIGH_RATE_BD_IDX_8822B 0x7f -#define BIT_HIGH_RATE_BD_IDX_8822B(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822B) << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) -#define BIT_GET_HIGH_RATE_BD_IDX_8822B(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) & BIT_MASK_HIGH_RATE_BD_IDX_8822B) - - +#define BIT_HIGH_RATE_BD_IDX_8822B(x) \ + (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822B) \ + << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) +#define BITS_HIGH_RATE_BD_IDX_8822B \ + (BIT_MASK_HIGH_RATE_BD_IDX_8822B << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) +#define BIT_CLEAR_HIGH_RATE_BD_IDX_8822B(x) \ + ((x) & (~BITS_HIGH_RATE_BD_IDX_8822B)) +#define BIT_GET_HIGH_RATE_BD_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) & \ + BIT_MASK_HIGH_RATE_BD_IDX_8822B) +#define BIT_SET_HIGH_RATE_BD_IDX_8822B(x, v) \ + (BIT_CLEAR_HIGH_RATE_BD_IDX_8822B(x) | BIT_HIGH_RATE_BD_IDX_8822B(v)) #define BIT_SHIFT_LOW_RATE_BD_IDX_8822B 0 #define BIT_MASK_LOW_RATE_BD_IDX_8822B 0x7f -#define BIT_LOW_RATE_BD_IDX_8822B(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8822B) << BIT_SHIFT_LOW_RATE_BD_IDX_8822B) -#define BIT_GET_LOW_RATE_BD_IDX_8822B(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822B) & BIT_MASK_LOW_RATE_BD_IDX_8822B) - - +#define BIT_LOW_RATE_BD_IDX_8822B(x) \ + (((x) & BIT_MASK_LOW_RATE_BD_IDX_8822B) \ + << BIT_SHIFT_LOW_RATE_BD_IDX_8822B) +#define BITS_LOW_RATE_BD_IDX_8822B \ + (BIT_MASK_LOW_RATE_BD_IDX_8822B << BIT_SHIFT_LOW_RATE_BD_IDX_8822B) +#define BIT_CLEAR_LOW_RATE_BD_IDX_8822B(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8822B)) +#define BIT_GET_LOW_RATE_BD_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822B) & \ + BIT_MASK_LOW_RATE_BD_IDX_8822B) +#define BIT_SET_LOW_RATE_BD_IDX_8822B(x, v) \ + (BIT_CLEAR_LOW_RATE_BD_IDX_8822B(x) | BIT_LOW_RATE_BD_IDX_8822B(v)) /* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8822B */ #define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B 24 #define BIT_MASK_RX_EMPTY_TIMER_IDX_8822B 0x7 -#define BIT_RX_EMPTY_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) -#define BIT_GET_RX_EMPTY_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B) - - +#define BIT_RX_EMPTY_TIMER_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B) \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) +#define BITS_RX_EMPTY_TIMER_IDX_8822B \ + (BIT_MASK_RX_EMPTY_TIMER_IDX_8822B \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822B(x) \ + ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8822B)) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) & \ + BIT_MASK_RX_EMPTY_TIMER_IDX_8822B) +#define BIT_SET_RX_EMPTY_TIMER_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822B(x) | \ + BIT_RX_EMPTY_TIMER_IDX_8822B(v)) #define BIT_SHIFT_RX_AFULL_TH_IDX_8822B 20 #define BIT_MASK_RX_AFULL_TH_IDX_8822B 0x7 -#define BIT_RX_AFULL_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8822B) << BIT_SHIFT_RX_AFULL_TH_IDX_8822B) -#define BIT_GET_RX_AFULL_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822B) & BIT_MASK_RX_AFULL_TH_IDX_8822B) - - +#define BIT_RX_AFULL_TH_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_AFULL_TH_IDX_8822B) \ + << BIT_SHIFT_RX_AFULL_TH_IDX_8822B) +#define BITS_RX_AFULL_TH_IDX_8822B \ + (BIT_MASK_RX_AFULL_TH_IDX_8822B << BIT_SHIFT_RX_AFULL_TH_IDX_8822B) +#define BIT_CLEAR_RX_AFULL_TH_IDX_8822B(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8822B)) +#define BIT_GET_RX_AFULL_TH_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822B) & \ + BIT_MASK_RX_AFULL_TH_IDX_8822B) +#define BIT_SET_RX_AFULL_TH_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_AFULL_TH_IDX_8822B(x) | BIT_RX_AFULL_TH_IDX_8822B(v)) #define BIT_SHIFT_RX_HIGH_TH_IDX_8822B 16 #define BIT_MASK_RX_HIGH_TH_IDX_8822B 0x7 -#define BIT_RX_HIGH_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8822B) << BIT_SHIFT_RX_HIGH_TH_IDX_8822B) -#define BIT_GET_RX_HIGH_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822B) & BIT_MASK_RX_HIGH_TH_IDX_8822B) - - +#define BIT_RX_HIGH_TH_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_HIGH_TH_IDX_8822B) \ + << BIT_SHIFT_RX_HIGH_TH_IDX_8822B) +#define BITS_RX_HIGH_TH_IDX_8822B \ + (BIT_MASK_RX_HIGH_TH_IDX_8822B << BIT_SHIFT_RX_HIGH_TH_IDX_8822B) +#define BIT_CLEAR_RX_HIGH_TH_IDX_8822B(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8822B)) +#define BIT_GET_RX_HIGH_TH_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822B) & \ + BIT_MASK_RX_HIGH_TH_IDX_8822B) +#define BIT_SET_RX_HIGH_TH_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_HIGH_TH_IDX_8822B(x) | BIT_RX_HIGH_TH_IDX_8822B(v)) #define BIT_SHIFT_RX_MED_TH_IDX_8822B 12 #define BIT_MASK_RX_MED_TH_IDX_8822B 0x7 -#define BIT_RX_MED_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8822B) << BIT_SHIFT_RX_MED_TH_IDX_8822B) -#define BIT_GET_RX_MED_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822B) & BIT_MASK_RX_MED_TH_IDX_8822B) - - +#define BIT_RX_MED_TH_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_MED_TH_IDX_8822B) << BIT_SHIFT_RX_MED_TH_IDX_8822B) +#define BITS_RX_MED_TH_IDX_8822B \ + (BIT_MASK_RX_MED_TH_IDX_8822B << BIT_SHIFT_RX_MED_TH_IDX_8822B) +#define BIT_CLEAR_RX_MED_TH_IDX_8822B(x) ((x) & (~BITS_RX_MED_TH_IDX_8822B)) +#define BIT_GET_RX_MED_TH_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822B) & BIT_MASK_RX_MED_TH_IDX_8822B) +#define BIT_SET_RX_MED_TH_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_MED_TH_IDX_8822B(x) | BIT_RX_MED_TH_IDX_8822B(v)) #define BIT_SHIFT_RX_LOW_TH_IDX_8822B 8 #define BIT_MASK_RX_LOW_TH_IDX_8822B 0x7 -#define BIT_RX_LOW_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8822B) << BIT_SHIFT_RX_LOW_TH_IDX_8822B) -#define BIT_GET_RX_LOW_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822B) & BIT_MASK_RX_LOW_TH_IDX_8822B) - - +#define BIT_RX_LOW_TH_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_LOW_TH_IDX_8822B) << BIT_SHIFT_RX_LOW_TH_IDX_8822B) +#define BITS_RX_LOW_TH_IDX_8822B \ + (BIT_MASK_RX_LOW_TH_IDX_8822B << BIT_SHIFT_RX_LOW_TH_IDX_8822B) +#define BIT_CLEAR_RX_LOW_TH_IDX_8822B(x) ((x) & (~BITS_RX_LOW_TH_IDX_8822B)) +#define BIT_GET_RX_LOW_TH_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822B) & BIT_MASK_RX_LOW_TH_IDX_8822B) +#define BIT_SET_RX_LOW_TH_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_LOW_TH_IDX_8822B(x) | BIT_RX_LOW_TH_IDX_8822B(v)) #define BIT_SHIFT_LTR_SPACE_IDX_8822B 4 #define BIT_MASK_LTR_SPACE_IDX_8822B 0x3 -#define BIT_LTR_SPACE_IDX_8822B(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8822B) << BIT_SHIFT_LTR_SPACE_IDX_8822B) -#define BIT_GET_LTR_SPACE_IDX_8822B(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822B) & BIT_MASK_LTR_SPACE_IDX_8822B) - - +#define BIT_LTR_SPACE_IDX_8822B(x) \ + (((x) & BIT_MASK_LTR_SPACE_IDX_8822B) << BIT_SHIFT_LTR_SPACE_IDX_8822B) +#define BITS_LTR_SPACE_IDX_8822B \ + (BIT_MASK_LTR_SPACE_IDX_8822B << BIT_SHIFT_LTR_SPACE_IDX_8822B) +#define BIT_CLEAR_LTR_SPACE_IDX_8822B(x) ((x) & (~BITS_LTR_SPACE_IDX_8822B)) +#define BIT_GET_LTR_SPACE_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822B) & BIT_MASK_LTR_SPACE_IDX_8822B) +#define BIT_SET_LTR_SPACE_IDX_8822B(x, v) \ + (BIT_CLEAR_LTR_SPACE_IDX_8822B(x) | BIT_LTR_SPACE_IDX_8822B(v)) #define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B 0 #define BIT_MASK_LTR_IDLE_TIMER_IDX_8822B 0x7 -#define BIT_LTR_IDLE_TIMER_IDX_8822B(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) -#define BIT_GET_LTR_IDLE_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) - - +#define BIT_LTR_IDLE_TIMER_IDX_8822B(x) \ + (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) +#define BITS_LTR_IDLE_TIMER_IDX_8822B \ + (BIT_MASK_LTR_IDLE_TIMER_IDX_8822B \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822B(x) \ + ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8822B)) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) & \ + BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) +#define BIT_SET_LTR_IDLE_TIMER_IDX_8822B(x, v) \ + (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822B(x) | \ + BIT_LTR_IDLE_TIMER_IDX_8822B(v)) /* 2 REG_LTR_IDLE_LATENCY_V1_8822B */ #define BIT_SHIFT_LTR_IDLE_L_8822B 0 #define BIT_MASK_LTR_IDLE_L_8822B 0xffffffffL -#define BIT_LTR_IDLE_L_8822B(x) (((x) & BIT_MASK_LTR_IDLE_L_8822B) << BIT_SHIFT_LTR_IDLE_L_8822B) -#define BIT_GET_LTR_IDLE_L_8822B(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8822B) & BIT_MASK_LTR_IDLE_L_8822B) - - +#define BIT_LTR_IDLE_L_8822B(x) \ + (((x) & BIT_MASK_LTR_IDLE_L_8822B) << BIT_SHIFT_LTR_IDLE_L_8822B) +#define BITS_LTR_IDLE_L_8822B \ + (BIT_MASK_LTR_IDLE_L_8822B << BIT_SHIFT_LTR_IDLE_L_8822B) +#define BIT_CLEAR_LTR_IDLE_L_8822B(x) ((x) & (~BITS_LTR_IDLE_L_8822B)) +#define BIT_GET_LTR_IDLE_L_8822B(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_L_8822B) & BIT_MASK_LTR_IDLE_L_8822B) +#define BIT_SET_LTR_IDLE_L_8822B(x, v) \ + (BIT_CLEAR_LTR_IDLE_L_8822B(x) | BIT_LTR_IDLE_L_8822B(v)) /* 2 REG_LTR_ACTIVE_LATENCY_V1_8822B */ #define BIT_SHIFT_LTR_ACT_L_8822B 0 #define BIT_MASK_LTR_ACT_L_8822B 0xffffffffL -#define BIT_LTR_ACT_L_8822B(x) (((x) & BIT_MASK_LTR_ACT_L_8822B) << BIT_SHIFT_LTR_ACT_L_8822B) -#define BIT_GET_LTR_ACT_L_8822B(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8822B) & BIT_MASK_LTR_ACT_L_8822B) - - +#define BIT_LTR_ACT_L_8822B(x) \ + (((x) & BIT_MASK_LTR_ACT_L_8822B) << BIT_SHIFT_LTR_ACT_L_8822B) +#define BITS_LTR_ACT_L_8822B \ + (BIT_MASK_LTR_ACT_L_8822B << BIT_SHIFT_LTR_ACT_L_8822B) +#define BIT_CLEAR_LTR_ACT_L_8822B(x) ((x) & (~BITS_LTR_ACT_L_8822B)) +#define BIT_GET_LTR_ACT_L_8822B(x) \ + (((x) >> BIT_SHIFT_LTR_ACT_L_8822B) & BIT_MASK_LTR_ACT_L_8822B) +#define BIT_SET_LTR_ACT_L_8822B(x, v) \ + (BIT_CLEAR_LTR_ACT_L_8822B(x) | BIT_LTR_ACT_L_8822B(v)) /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B */ #define BIT_APPEND_MACID_IN_RESP_EN_8822B BIT(50) @@ -10588,10 +16980,17 @@ #define BIT_SHIFT_TRAIN_STA_ADDR_8822B 0 #define BIT_MASK_TRAIN_STA_ADDR_8822B 0xffffffffffffL -#define BIT_TRAIN_STA_ADDR_8822B(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_8822B) << BIT_SHIFT_TRAIN_STA_ADDR_8822B) -#define BIT_GET_TRAIN_STA_ADDR_8822B(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8822B) & BIT_MASK_TRAIN_STA_ADDR_8822B) - - +#define BIT_TRAIN_STA_ADDR_8822B(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_8822B) \ + << BIT_SHIFT_TRAIN_STA_ADDR_8822B) +#define BITS_TRAIN_STA_ADDR_8822B \ + (BIT_MASK_TRAIN_STA_ADDR_8822B << BIT_SHIFT_TRAIN_STA_ADDR_8822B) +#define BIT_CLEAR_TRAIN_STA_ADDR_8822B(x) ((x) & (~BITS_TRAIN_STA_ADDR_8822B)) +#define BIT_GET_TRAIN_STA_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8822B) & \ + BIT_MASK_TRAIN_STA_ADDR_8822B) +#define BIT_SET_TRAIN_STA_ADDR_8822B(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_8822B(x) | BIT_TRAIN_STA_ADDR_8822B(v)) /* 2 REG_RSVD_0X7B4_8822B */ @@ -10599,9 +16998,17 @@ #define BIT_SHIFT_PKTCNT_BSSIDMAP_8822B 4 #define BIT_MASK_PKTCNT_BSSIDMAP_8822B 0xf -#define BIT_PKTCNT_BSSIDMAP_8822B(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822B) << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) -#define BIT_GET_PKTCNT_BSSIDMAP_8822B(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) & BIT_MASK_PKTCNT_BSSIDMAP_8822B) - +#define BIT_PKTCNT_BSSIDMAP_8822B(x) \ + (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822B) \ + << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) +#define BITS_PKTCNT_BSSIDMAP_8822B \ + (BIT_MASK_PKTCNT_BSSIDMAP_8822B << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) +#define BIT_CLEAR_PKTCNT_BSSIDMAP_8822B(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8822B)) +#define BIT_GET_PKTCNT_BSSIDMAP_8822B(x) \ + (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) & \ + BIT_MASK_PKTCNT_BSSIDMAP_8822B) +#define BIT_SET_PKTCNT_BSSIDMAP_8822B(x, v) \ + (BIT_CLEAR_PKTCNT_BSSIDMAP_8822B(x) | BIT_PKTCNT_BSSIDMAP_8822B(v)) #define BIT_PKTCNT_CNTRST_8822B BIT(1) #define BIT_PKTCNT_CNTEN_8822B BIT(0) @@ -10612,54 +17019,111 @@ #define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B 0 #define BIT_MASK_WMAC_PKTCNT_CFGAD_8822B 0xff -#define BIT_WMAC_PKTCNT_CFGAD_8822B(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) -#define BIT_GET_WMAC_PKTCNT_CFGAD_8822B(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B) - - +#define BIT_WMAC_PKTCNT_CFGAD_8822B(x) \ + (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B) \ + << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) +#define BITS_WMAC_PKTCNT_CFGAD_8822B \ + (BIT_MASK_WMAC_PKTCNT_CFGAD_8822B << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) +#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822B(x) \ + ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8822B)) +#define BIT_GET_WMAC_PKTCNT_CFGAD_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) & \ + BIT_MASK_WMAC_PKTCNT_CFGAD_8822B) +#define BIT_SET_WMAC_PKTCNT_CFGAD_8822B(x, v) \ + (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822B(x) | BIT_WMAC_PKTCNT_CFGAD_8822B(v)) /* 2 REG_IQ_DUMP_8822B */ #define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B (64 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC_8822B(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) -#define BIT_GET_R_WMAC_MATCH_REF_MAC_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B) - - +#define BIT_R_WMAC_MATCH_REF_MAC_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) +#define BITS_R_WMAC_MATCH_REF_MAC_8822B \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8822B(x) \ + ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8822B)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8822B(x) | \ + BIT_R_WMAC_MATCH_REF_MAC_8822B(v)) #define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_MASK_LA_MAC_8822B 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC_8822B(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) -#define BIT_GET_R_WMAC_MASK_LA_MAC_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) - - - -#define BIT_SHIFT_DUMP_OK_ADDR_8822B 15 -#define BIT_MASK_DUMP_OK_ADDR_8822B 0x1ffff -#define BIT_DUMP_OK_ADDR_8822B(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8822B) << BIT_SHIFT_DUMP_OK_ADDR_8822B) -#define BIT_GET_DUMP_OK_ADDR_8822B(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822B) & BIT_MASK_DUMP_OK_ADDR_8822B) - - +#define BIT_R_WMAC_MASK_LA_MAC_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) +#define BITS_R_WMAC_MASK_LA_MAC_8822B \ + (BIT_MASK_R_WMAC_MASK_LA_MAC_8822B \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8822B(x) \ + ((x) & (~BITS_R_WMAC_MASK_LA_MAC_8822B)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) & \ + BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) +#define BIT_SET_R_WMAC_MASK_LA_MAC_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC_8822B(x) | \ + BIT_R_WMAC_MASK_LA_MAC_8822B(v)) + +#define BIT_SHIFT_DUMP_OK_ADDR_8822B 16 +#define BIT_MASK_DUMP_OK_ADDR_8822B 0xffff +#define BIT_DUMP_OK_ADDR_8822B(x) \ + (((x) & BIT_MASK_DUMP_OK_ADDR_8822B) << BIT_SHIFT_DUMP_OK_ADDR_8822B) +#define BITS_DUMP_OK_ADDR_8822B \ + (BIT_MASK_DUMP_OK_ADDR_8822B << BIT_SHIFT_DUMP_OK_ADDR_8822B) +#define BIT_CLEAR_DUMP_OK_ADDR_8822B(x) ((x) & (~BITS_DUMP_OK_ADDR_8822B)) +#define BIT_GET_DUMP_OK_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822B) & BIT_MASK_DUMP_OK_ADDR_8822B) +#define BIT_SET_DUMP_OK_ADDR_8822B(x, v) \ + (BIT_CLEAR_DUMP_OK_ADDR_8822B(x) | BIT_DUMP_OK_ADDR_8822B(v)) #define BIT_SHIFT_R_TRIG_TIME_SEL_8822B 8 #define BIT_MASK_R_TRIG_TIME_SEL_8822B 0x7f -#define BIT_R_TRIG_TIME_SEL_8822B(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8822B) << BIT_SHIFT_R_TRIG_TIME_SEL_8822B) -#define BIT_GET_R_TRIG_TIME_SEL_8822B(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822B) & BIT_MASK_R_TRIG_TIME_SEL_8822B) - - +#define BIT_R_TRIG_TIME_SEL_8822B(x) \ + (((x) & BIT_MASK_R_TRIG_TIME_SEL_8822B) \ + << BIT_SHIFT_R_TRIG_TIME_SEL_8822B) +#define BITS_R_TRIG_TIME_SEL_8822B \ + (BIT_MASK_R_TRIG_TIME_SEL_8822B << BIT_SHIFT_R_TRIG_TIME_SEL_8822B) +#define BIT_CLEAR_R_TRIG_TIME_SEL_8822B(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8822B)) +#define BIT_GET_R_TRIG_TIME_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822B) & \ + BIT_MASK_R_TRIG_TIME_SEL_8822B) +#define BIT_SET_R_TRIG_TIME_SEL_8822B(x, v) \ + (BIT_CLEAR_R_TRIG_TIME_SEL_8822B(x) | BIT_R_TRIG_TIME_SEL_8822B(v)) #define BIT_SHIFT_R_MAC_TRIG_SEL_8822B 6 #define BIT_MASK_R_MAC_TRIG_SEL_8822B 0x3 -#define BIT_R_MAC_TRIG_SEL_8822B(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8822B) << BIT_SHIFT_R_MAC_TRIG_SEL_8822B) -#define BIT_GET_R_MAC_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822B) & BIT_MASK_R_MAC_TRIG_SEL_8822B) - +#define BIT_R_MAC_TRIG_SEL_8822B(x) \ + (((x) & BIT_MASK_R_MAC_TRIG_SEL_8822B) \ + << BIT_SHIFT_R_MAC_TRIG_SEL_8822B) +#define BITS_R_MAC_TRIG_SEL_8822B \ + (BIT_MASK_R_MAC_TRIG_SEL_8822B << BIT_SHIFT_R_MAC_TRIG_SEL_8822B) +#define BIT_CLEAR_R_MAC_TRIG_SEL_8822B(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8822B)) +#define BIT_GET_R_MAC_TRIG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822B) & \ + BIT_MASK_R_MAC_TRIG_SEL_8822B) +#define BIT_SET_R_MAC_TRIG_SEL_8822B(x, v) \ + (BIT_CLEAR_R_MAC_TRIG_SEL_8822B(x) | BIT_R_MAC_TRIG_SEL_8822B(v)) #define BIT_MAC_TRIG_REG_8822B BIT(5) #define BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B 3 #define BIT_MASK_R_LEVEL_PULSE_SEL_8822B 0x3 -#define BIT_R_LEVEL_PULSE_SEL_8822B(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) -#define BIT_GET_R_LEVEL_PULSE_SEL_8822B(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B) - +#define BIT_R_LEVEL_PULSE_SEL_8822B(x) \ + (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B) \ + << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) +#define BITS_R_LEVEL_PULSE_SEL_8822B \ + (BIT_MASK_R_LEVEL_PULSE_SEL_8822B << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8822B(x) \ + ((x) & (~BITS_R_LEVEL_PULSE_SEL_8822B)) +#define BIT_GET_R_LEVEL_PULSE_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) & \ + BIT_MASK_R_LEVEL_PULSE_SEL_8822B) +#define BIT_SET_R_LEVEL_PULSE_SEL_8822B(x, v) \ + (BIT_CLEAR_R_LEVEL_PULSE_SEL_8822B(x) | BIT_R_LEVEL_PULSE_SEL_8822B(v)) #define BIT_EN_LA_MAC_8822B BIT(2) #define BIT_R_EN_IQDUMP_8822B BIT(1) @@ -10679,16 +17143,35 @@ #define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B (64 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_RX_FIL_LEN_8822B 0xffff -#define BIT_R_WMAC_RX_FIL_LEN_8822B(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) -#define BIT_GET_R_WMAC_RX_FIL_LEN_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B) - - +#define BIT_R_WMAC_RX_FIL_LEN_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B) \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) +#define BITS_R_WMAC_RX_FIL_LEN_8822B \ + (BIT_MASK_R_WMAC_RX_FIL_LEN_8822B << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8822B(x) \ + ((x) & (~BITS_R_WMAC_RX_FIL_LEN_8822B)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) & \ + BIT_MASK_R_WMAC_RX_FIL_LEN_8822B) +#define BIT_SET_R_WMAC_RX_FIL_LEN_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN_8822B(x) | BIT_R_WMAC_RX_FIL_LEN_8822B(v)) #define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B (56 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH_8822B(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) - +#define BIT_R_WMAC_RXFIFO_FULL_TH_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) +#define BITS_R_WMAC_RXFIFO_FULL_TH_8822B \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8822B(x) \ + ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8822B)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8822B(x) | \ + BIT_R_WMAC_RXFIFO_FULL_TH_8822B(v)) #define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8822B BIT(55) #define BIT_R_WMAC_RXRST_DLY_8822B BIT(54) @@ -10717,17 +17200,27 @@ #define BIT_SHIFT_R_OFDM_LEN_8822B 26 #define BIT_MASK_R_OFDM_LEN_8822B 0x3f -#define BIT_R_OFDM_LEN_8822B(x) (((x) & BIT_MASK_R_OFDM_LEN_8822B) << BIT_SHIFT_R_OFDM_LEN_8822B) -#define BIT_GET_R_OFDM_LEN_8822B(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8822B) & BIT_MASK_R_OFDM_LEN_8822B) - - +#define BIT_R_OFDM_LEN_8822B(x) \ + (((x) & BIT_MASK_R_OFDM_LEN_8822B) << BIT_SHIFT_R_OFDM_LEN_8822B) +#define BITS_R_OFDM_LEN_8822B \ + (BIT_MASK_R_OFDM_LEN_8822B << BIT_SHIFT_R_OFDM_LEN_8822B) +#define BIT_CLEAR_R_OFDM_LEN_8822B(x) ((x) & (~BITS_R_OFDM_LEN_8822B)) +#define BIT_GET_R_OFDM_LEN_8822B(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN_8822B) & BIT_MASK_R_OFDM_LEN_8822B) +#define BIT_SET_R_OFDM_LEN_8822B(x, v) \ + (BIT_CLEAR_R_OFDM_LEN_8822B(x) | BIT_R_OFDM_LEN_8822B(v)) #define BIT_SHIFT_R_CCK_LEN_8822B 0 #define BIT_MASK_R_CCK_LEN_8822B 0xffff -#define BIT_R_CCK_LEN_8822B(x) (((x) & BIT_MASK_R_CCK_LEN_8822B) << BIT_SHIFT_R_CCK_LEN_8822B) -#define BIT_GET_R_CCK_LEN_8822B(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8822B) & BIT_MASK_R_CCK_LEN_8822B) - - +#define BIT_R_CCK_LEN_8822B(x) \ + (((x) & BIT_MASK_R_CCK_LEN_8822B) << BIT_SHIFT_R_CCK_LEN_8822B) +#define BITS_R_CCK_LEN_8822B \ + (BIT_MASK_R_CCK_LEN_8822B << BIT_SHIFT_R_CCK_LEN_8822B) +#define BIT_CLEAR_R_CCK_LEN_8822B(x) ((x) & (~BITS_R_CCK_LEN_8822B)) +#define BIT_GET_R_CCK_LEN_8822B(x) \ + (((x) >> BIT_SHIFT_R_CCK_LEN_8822B) & BIT_MASK_R_CCK_LEN_8822B) +#define BIT_SET_R_CCK_LEN_8822B(x, v) \ + (BIT_CLEAR_R_CCK_LEN_8822B(x) | BIT_R_CCK_LEN_8822B(v)) /* 2 REG_RX_FILTER_FUNCTION_8822B */ #define BIT_R_WMAC_MHRDDY_LATCH_8822B BIT(14) @@ -10750,39 +17243,64 @@ #define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B 0 #define BIT_MASK_R_WMAC_TXNDP_SIGB_8822B 0x1fffff -#define BIT_R_WMAC_TXNDP_SIGB_8822B(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) -#define BIT_GET_R_WMAC_TXNDP_SIGB_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B) - - +#define BIT_R_WMAC_TXNDP_SIGB_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B) \ + << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) +#define BITS_R_WMAC_TXNDP_SIGB_8822B \ + (BIT_MASK_R_WMAC_TXNDP_SIGB_8822B << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822B(x) \ + ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8822B)) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) & \ + BIT_MASK_R_WMAC_TXNDP_SIGB_8822B) +#define BIT_SET_R_WMAC_TXNDP_SIGB_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822B(x) | BIT_R_WMAC_TXNDP_SIGB_8822B(v)) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8822B */ #define BIT_SHIFT_R_MAC_DEBUG_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_R_MAC_DEBUG_8822B 0xffffffffL -#define BIT_R_MAC_DEBUG_8822B(x) (((x) & BIT_MASK_R_MAC_DEBUG_8822B) << BIT_SHIFT_R_MAC_DEBUG_8822B) -#define BIT_GET_R_MAC_DEBUG_8822B(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_8822B) & BIT_MASK_R_MAC_DEBUG_8822B) - - +#define BIT_R_MAC_DEBUG_8822B(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG_8822B) << BIT_SHIFT_R_MAC_DEBUG_8822B) +#define BITS_R_MAC_DEBUG_8822B \ + (BIT_MASK_R_MAC_DEBUG_8822B << BIT_SHIFT_R_MAC_DEBUG_8822B) +#define BIT_CLEAR_R_MAC_DEBUG_8822B(x) ((x) & (~BITS_R_MAC_DEBUG_8822B)) +#define BIT_GET_R_MAC_DEBUG_8822B(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG_8822B) & BIT_MASK_R_MAC_DEBUG_8822B) +#define BIT_SET_R_MAC_DEBUG_8822B(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG_8822B(x) | BIT_R_MAC_DEBUG_8822B(v)) #define BIT_SHIFT_R_MAC_DBG_SHIFT_8822B 8 #define BIT_MASK_R_MAC_DBG_SHIFT_8822B 0x7 -#define BIT_R_MAC_DBG_SHIFT_8822B(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822B) << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) -#define BIT_GET_R_MAC_DBG_SHIFT_8822B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) & BIT_MASK_R_MAC_DBG_SHIFT_8822B) - - +#define BIT_R_MAC_DBG_SHIFT_8822B(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822B) \ + << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) +#define BITS_R_MAC_DBG_SHIFT_8822B \ + (BIT_MASK_R_MAC_DBG_SHIFT_8822B << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) +#define BIT_CLEAR_R_MAC_DBG_SHIFT_8822B(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8822B)) +#define BIT_GET_R_MAC_DBG_SHIFT_8822B(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) & \ + BIT_MASK_R_MAC_DBG_SHIFT_8822B) +#define BIT_SET_R_MAC_DBG_SHIFT_8822B(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SHIFT_8822B(x) | BIT_R_MAC_DBG_SHIFT_8822B(v)) #define BIT_SHIFT_R_MAC_DBG_SEL_8822B 0 #define BIT_MASK_R_MAC_DBG_SEL_8822B 0x3 -#define BIT_R_MAC_DBG_SEL_8822B(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8822B) << BIT_SHIFT_R_MAC_DBG_SEL_8822B) -#define BIT_GET_R_MAC_DBG_SEL_8822B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822B) & BIT_MASK_R_MAC_DBG_SEL_8822B) - - +#define BIT_R_MAC_DBG_SEL_8822B(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SEL_8822B) << BIT_SHIFT_R_MAC_DBG_SEL_8822B) +#define BITS_R_MAC_DBG_SEL_8822B \ + (BIT_MASK_R_MAC_DBG_SEL_8822B << BIT_SHIFT_R_MAC_DBG_SEL_8822B) +#define BIT_CLEAR_R_MAC_DBG_SEL_8822B(x) ((x) & (~BITS_R_MAC_DBG_SEL_8822B)) +#define BIT_GET_R_MAC_DBG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822B) & BIT_MASK_R_MAC_DBG_SEL_8822B) +#define BIT_SET_R_MAC_DBG_SEL_8822B(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SEL_8822B(x) | BIT_R_MAC_DBG_SEL_8822B(v)) /* 2 REG_RTS_ADDRESS_0_8822B */ /* 2 REG_RTS_ADDRESS_1_8822B */ -/* 2 REG__RPFM_MAP1_8822B (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 1 */ +/* 2 REG_RPFM_MAP1_8822B */ #define BIT_DATA_RPFM15EN_8822B BIT(15) #define BIT_DATA_RPFM14EN_8822B BIT(14) #define BIT_DATA_RPFM13EN_8822B BIT(13) @@ -10807,35 +17325,69 @@ #define BIT_SHIFT_WRITE_BYTE_EN_V1_8822B 16 #define BIT_MASK_WRITE_BYTE_EN_V1_8822B 0xf -#define BIT_WRITE_BYTE_EN_V1_8822B(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822B) << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) -#define BIT_GET_WRITE_BYTE_EN_V1_8822B(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) & BIT_MASK_WRITE_BYTE_EN_V1_8822B) - - +#define BIT_WRITE_BYTE_EN_V1_8822B(x) \ + (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822B) \ + << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) +#define BITS_WRITE_BYTE_EN_V1_8822B \ + (BIT_MASK_WRITE_BYTE_EN_V1_8822B << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) +#define BIT_CLEAR_WRITE_BYTE_EN_V1_8822B(x) \ + ((x) & (~BITS_WRITE_BYTE_EN_V1_8822B)) +#define BIT_GET_WRITE_BYTE_EN_V1_8822B(x) \ + (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) & \ + BIT_MASK_WRITE_BYTE_EN_V1_8822B) +#define BIT_SET_WRITE_BYTE_EN_V1_8822B(x, v) \ + (BIT_CLEAR_WRITE_BYTE_EN_V1_8822B(x) | BIT_WRITE_BYTE_EN_V1_8822B(v)) #define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B 0 #define BIT_MASK_LTECOEX_REG_ADDR_V1_8822B 0xffff -#define BIT_LTECOEX_REG_ADDR_V1_8822B(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) -#define BIT_GET_LTECOEX_REG_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) - - +#define BIT_LTECOEX_REG_ADDR_V1_8822B(x) \ + (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) +#define BITS_LTECOEX_REG_ADDR_V1_8822B \ + (BIT_MASK_LTECOEX_REG_ADDR_V1_8822B \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) +#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822B(x) \ + ((x) & (~BITS_LTECOEX_REG_ADDR_V1_8822B)) +#define BIT_GET_LTECOEX_REG_ADDR_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) & \ + BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) +#define BIT_SET_LTECOEX_REG_ADDR_V1_8822B(x, v) \ + (BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822B(x) | \ + BIT_LTECOEX_REG_ADDR_V1_8822B(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B */ #define BIT_SHIFT_LTECOEX_W_DATA_V1_8822B 0 #define BIT_MASK_LTECOEX_W_DATA_V1_8822B 0xffffffffL -#define BIT_LTECOEX_W_DATA_V1_8822B(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822B) << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) -#define BIT_GET_LTECOEX_W_DATA_V1_8822B(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) & BIT_MASK_LTECOEX_W_DATA_V1_8822B) - - +#define BIT_LTECOEX_W_DATA_V1_8822B(x) \ + (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822B) \ + << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) +#define BITS_LTECOEX_W_DATA_V1_8822B \ + (BIT_MASK_LTECOEX_W_DATA_V1_8822B << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) +#define BIT_CLEAR_LTECOEX_W_DATA_V1_8822B(x) \ + ((x) & (~BITS_LTECOEX_W_DATA_V1_8822B)) +#define BIT_GET_LTECOEX_W_DATA_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) & \ + BIT_MASK_LTECOEX_W_DATA_V1_8822B) +#define BIT_SET_LTECOEX_W_DATA_V1_8822B(x, v) \ + (BIT_CLEAR_LTECOEX_W_DATA_V1_8822B(x) | BIT_LTECOEX_W_DATA_V1_8822B(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B */ #define BIT_SHIFT_LTECOEX_R_DATA_V1_8822B 0 #define BIT_MASK_LTECOEX_R_DATA_V1_8822B 0xffffffffL -#define BIT_LTECOEX_R_DATA_V1_8822B(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822B) << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) -#define BIT_GET_LTECOEX_R_DATA_V1_8822B(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) & BIT_MASK_LTECOEX_R_DATA_V1_8822B) - - +#define BIT_LTECOEX_R_DATA_V1_8822B(x) \ + (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822B) \ + << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) +#define BITS_LTECOEX_R_DATA_V1_8822B \ + (BIT_MASK_LTECOEX_R_DATA_V1_8822B << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) +#define BIT_CLEAR_LTECOEX_R_DATA_V1_8822B(x) \ + ((x) & (~BITS_LTECOEX_R_DATA_V1_8822B)) +#define BIT_GET_LTECOEX_R_DATA_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) & \ + BIT_MASK_LTECOEX_R_DATA_V1_8822B) +#define BIT_SET_LTECOEX_R_DATA_V1_8822B(x, v) \ + (BIT_CLEAR_LTECOEX_R_DATA_V1_8822B(x) | BIT_LTECOEX_R_DATA_V1_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -10843,16 +17395,26 @@ #define BIT_SHIFT_SDIO_INT_TIMEOUT_8822B 16 #define BIT_MASK_SDIO_INT_TIMEOUT_8822B 0xffff -#define BIT_SDIO_INT_TIMEOUT_8822B(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822B) << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) -#define BIT_GET_SDIO_INT_TIMEOUT_8822B(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) & BIT_MASK_SDIO_INT_TIMEOUT_8822B) - +#define BIT_SDIO_INT_TIMEOUT_8822B(x) \ + (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822B) \ + << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) +#define BITS_SDIO_INT_TIMEOUT_8822B \ + (BIT_MASK_SDIO_INT_TIMEOUT_8822B << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) +#define BIT_CLEAR_SDIO_INT_TIMEOUT_8822B(x) \ + ((x) & (~BITS_SDIO_INT_TIMEOUT_8822B)) +#define BIT_GET_SDIO_INT_TIMEOUT_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) & \ + BIT_MASK_SDIO_INT_TIMEOUT_8822B) +#define BIT_SET_SDIO_INT_TIMEOUT_8822B(x, v) \ + (BIT_CLEAR_SDIO_INT_TIMEOUT_8822B(x) | BIT_SDIO_INT_TIMEOUT_8822B(v)) #define BIT_IO_ERR_STATUS_8822B BIT(15) #define BIT_REPLY_ERRCRC_IN_DATA_8822B BIT(9) #define BIT_EN_CMD53_OVERLAP_8822B BIT(8) #define BIT_REPLY_ERR_IN_R5_8822B BIT(7) #define BIT_R18A_EN_8822B BIT(6) -#define BIT_INIT_CMD_EN_8822B BIT(5) +#define BIT_SDIO_CMD_FORCE_VLD_8822B BIT(5) +#define BIT_INIT_CMD_EN_8822B BIT(4) #define BIT_EN_RXDMA_MASK_INT_8822B BIT(2) #define BIT_EN_MASK_TIMER_8822B BIT(1) #define BIT_CMD_ERR_STOP_INT_EN_8822B BIT(0) @@ -10913,95 +17475,155 @@ #define BIT_SHIFT_RX_REQ_LEN_V1_8822B 0 #define BIT_MASK_RX_REQ_LEN_V1_8822B 0x3ffff -#define BIT_RX_REQ_LEN_V1_8822B(x) (((x) & BIT_MASK_RX_REQ_LEN_V1_8822B) << BIT_SHIFT_RX_REQ_LEN_V1_8822B) -#define BIT_GET_RX_REQ_LEN_V1_8822B(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822B) & BIT_MASK_RX_REQ_LEN_V1_8822B) - - +#define BIT_RX_REQ_LEN_V1_8822B(x) \ + (((x) & BIT_MASK_RX_REQ_LEN_V1_8822B) << BIT_SHIFT_RX_REQ_LEN_V1_8822B) +#define BITS_RX_REQ_LEN_V1_8822B \ + (BIT_MASK_RX_REQ_LEN_V1_8822B << BIT_SHIFT_RX_REQ_LEN_V1_8822B) +#define BIT_CLEAR_RX_REQ_LEN_V1_8822B(x) ((x) & (~BITS_RX_REQ_LEN_V1_8822B)) +#define BIT_GET_RX_REQ_LEN_V1_8822B(x) \ + (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822B) & BIT_MASK_RX_REQ_LEN_V1_8822B) +#define BIT_SET_RX_REQ_LEN_V1_8822B(x, v) \ + (BIT_CLEAR_RX_REQ_LEN_V1_8822B(x) | BIT_RX_REQ_LEN_V1_8822B(v)) /* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8822B */ #define BIT_SHIFT_FREE_TXPG_SEQ_8822B 0 #define BIT_MASK_FREE_TXPG_SEQ_8822B 0xff -#define BIT_FREE_TXPG_SEQ_8822B(x) (((x) & BIT_MASK_FREE_TXPG_SEQ_8822B) << BIT_SHIFT_FREE_TXPG_SEQ_8822B) -#define BIT_GET_FREE_TXPG_SEQ_8822B(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822B) & BIT_MASK_FREE_TXPG_SEQ_8822B) - - +#define BIT_FREE_TXPG_SEQ_8822B(x) \ + (((x) & BIT_MASK_FREE_TXPG_SEQ_8822B) << BIT_SHIFT_FREE_TXPG_SEQ_8822B) +#define BITS_FREE_TXPG_SEQ_8822B \ + (BIT_MASK_FREE_TXPG_SEQ_8822B << BIT_SHIFT_FREE_TXPG_SEQ_8822B) +#define BIT_CLEAR_FREE_TXPG_SEQ_8822B(x) ((x) & (~BITS_FREE_TXPG_SEQ_8822B)) +#define BIT_GET_FREE_TXPG_SEQ_8822B(x) \ + (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822B) & BIT_MASK_FREE_TXPG_SEQ_8822B) +#define BIT_SET_FREE_TXPG_SEQ_8822B(x, v) \ + (BIT_CLEAR_FREE_TXPG_SEQ_8822B(x) | BIT_FREE_TXPG_SEQ_8822B(v)) /* 2 REG_SDIO_FREE_TXPG_8822B */ #define BIT_SHIFT_MID_FREEPG_V1_8822B 16 #define BIT_MASK_MID_FREEPG_V1_8822B 0xfff -#define BIT_MID_FREEPG_V1_8822B(x) (((x) & BIT_MASK_MID_FREEPG_V1_8822B) << BIT_SHIFT_MID_FREEPG_V1_8822B) -#define BIT_GET_MID_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1_8822B) & BIT_MASK_MID_FREEPG_V1_8822B) - - +#define BIT_MID_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_MID_FREEPG_V1_8822B) << BIT_SHIFT_MID_FREEPG_V1_8822B) +#define BITS_MID_FREEPG_V1_8822B \ + (BIT_MASK_MID_FREEPG_V1_8822B << BIT_SHIFT_MID_FREEPG_V1_8822B) +#define BIT_CLEAR_MID_FREEPG_V1_8822B(x) ((x) & (~BITS_MID_FREEPG_V1_8822B)) +#define BIT_GET_MID_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_MID_FREEPG_V1_8822B) & BIT_MASK_MID_FREEPG_V1_8822B) +#define BIT_SET_MID_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_MID_FREEPG_V1_8822B(x) | BIT_MID_FREEPG_V1_8822B(v)) #define BIT_SHIFT_HIQ_FREEPG_V1_8822B 0 #define BIT_MASK_HIQ_FREEPG_V1_8822B 0xfff -#define BIT_HIQ_FREEPG_V1_8822B(x) (((x) & BIT_MASK_HIQ_FREEPG_V1_8822B) << BIT_SHIFT_HIQ_FREEPG_V1_8822B) -#define BIT_GET_HIQ_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822B) & BIT_MASK_HIQ_FREEPG_V1_8822B) - - +#define BIT_HIQ_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_HIQ_FREEPG_V1_8822B) << BIT_SHIFT_HIQ_FREEPG_V1_8822B) +#define BITS_HIQ_FREEPG_V1_8822B \ + (BIT_MASK_HIQ_FREEPG_V1_8822B << BIT_SHIFT_HIQ_FREEPG_V1_8822B) +#define BIT_CLEAR_HIQ_FREEPG_V1_8822B(x) ((x) & (~BITS_HIQ_FREEPG_V1_8822B)) +#define BIT_GET_HIQ_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822B) & BIT_MASK_HIQ_FREEPG_V1_8822B) +#define BIT_SET_HIQ_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_HIQ_FREEPG_V1_8822B(x) | BIT_HIQ_FREEPG_V1_8822B(v)) /* 2 REG_SDIO_FREE_TXPG2_8822B */ #define BIT_SHIFT_PUB_FREEPG_V1_8822B 16 #define BIT_MASK_PUB_FREEPG_V1_8822B 0xfff -#define BIT_PUB_FREEPG_V1_8822B(x) (((x) & BIT_MASK_PUB_FREEPG_V1_8822B) << BIT_SHIFT_PUB_FREEPG_V1_8822B) -#define BIT_GET_PUB_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822B) & BIT_MASK_PUB_FREEPG_V1_8822B) - - +#define BIT_PUB_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_PUB_FREEPG_V1_8822B) << BIT_SHIFT_PUB_FREEPG_V1_8822B) +#define BITS_PUB_FREEPG_V1_8822B \ + (BIT_MASK_PUB_FREEPG_V1_8822B << BIT_SHIFT_PUB_FREEPG_V1_8822B) +#define BIT_CLEAR_PUB_FREEPG_V1_8822B(x) ((x) & (~BITS_PUB_FREEPG_V1_8822B)) +#define BIT_GET_PUB_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822B) & BIT_MASK_PUB_FREEPG_V1_8822B) +#define BIT_SET_PUB_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_PUB_FREEPG_V1_8822B(x) | BIT_PUB_FREEPG_V1_8822B(v)) #define BIT_SHIFT_LOW_FREEPG_V1_8822B 0 #define BIT_MASK_LOW_FREEPG_V1_8822B 0xfff -#define BIT_LOW_FREEPG_V1_8822B(x) (((x) & BIT_MASK_LOW_FREEPG_V1_8822B) << BIT_SHIFT_LOW_FREEPG_V1_8822B) -#define BIT_GET_LOW_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822B) & BIT_MASK_LOW_FREEPG_V1_8822B) - - +#define BIT_LOW_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_LOW_FREEPG_V1_8822B) << BIT_SHIFT_LOW_FREEPG_V1_8822B) +#define BITS_LOW_FREEPG_V1_8822B \ + (BIT_MASK_LOW_FREEPG_V1_8822B << BIT_SHIFT_LOW_FREEPG_V1_8822B) +#define BIT_CLEAR_LOW_FREEPG_V1_8822B(x) ((x) & (~BITS_LOW_FREEPG_V1_8822B)) +#define BIT_GET_LOW_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822B) & BIT_MASK_LOW_FREEPG_V1_8822B) +#define BIT_SET_LOW_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_LOW_FREEPG_V1_8822B(x) | BIT_LOW_FREEPG_V1_8822B(v)) /* 2 REG_SDIO_OQT_FREE_TXPG_V1_8822B */ #define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B 24 #define BIT_MASK_NOAC_OQT_FREEPG_V1_8822B 0xff -#define BIT_NOAC_OQT_FREEPG_V1_8822B(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B) << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) -#define BIT_GET_NOAC_OQT_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B) - - +#define BIT_NOAC_OQT_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B) \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) +#define BITS_NOAC_OQT_FREEPG_V1_8822B \ + (BIT_MASK_NOAC_OQT_FREEPG_V1_8822B \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) +#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822B(x) \ + ((x) & (~BITS_NOAC_OQT_FREEPG_V1_8822B)) +#define BIT_GET_NOAC_OQT_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) & \ + BIT_MASK_NOAC_OQT_FREEPG_V1_8822B) +#define BIT_SET_NOAC_OQT_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822B(x) | \ + BIT_NOAC_OQT_FREEPG_V1_8822B(v)) #define BIT_SHIFT_AC_OQT_FREEPG_V1_8822B 16 #define BIT_MASK_AC_OQT_FREEPG_V1_8822B 0xff -#define BIT_AC_OQT_FREEPG_V1_8822B(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822B) << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) -#define BIT_GET_AC_OQT_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) & BIT_MASK_AC_OQT_FREEPG_V1_8822B) - - +#define BIT_AC_OQT_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822B) \ + << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) +#define BITS_AC_OQT_FREEPG_V1_8822B \ + (BIT_MASK_AC_OQT_FREEPG_V1_8822B << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) +#define BIT_CLEAR_AC_OQT_FREEPG_V1_8822B(x) \ + ((x) & (~BITS_AC_OQT_FREEPG_V1_8822B)) +#define BIT_GET_AC_OQT_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) & \ + BIT_MASK_AC_OQT_FREEPG_V1_8822B) +#define BIT_SET_AC_OQT_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_AC_OQT_FREEPG_V1_8822B(x) | BIT_AC_OQT_FREEPG_V1_8822B(v)) #define BIT_SHIFT_EXQ_FREEPG_V1_8822B 0 #define BIT_MASK_EXQ_FREEPG_V1_8822B 0xfff -#define BIT_EXQ_FREEPG_V1_8822B(x) (((x) & BIT_MASK_EXQ_FREEPG_V1_8822B) << BIT_SHIFT_EXQ_FREEPG_V1_8822B) -#define BIT_GET_EXQ_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822B) & BIT_MASK_EXQ_FREEPG_V1_8822B) - - +#define BIT_EXQ_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_EXQ_FREEPG_V1_8822B) << BIT_SHIFT_EXQ_FREEPG_V1_8822B) +#define BITS_EXQ_FREEPG_V1_8822B \ + (BIT_MASK_EXQ_FREEPG_V1_8822B << BIT_SHIFT_EXQ_FREEPG_V1_8822B) +#define BIT_CLEAR_EXQ_FREEPG_V1_8822B(x) ((x) & (~BITS_EXQ_FREEPG_V1_8822B)) +#define BIT_GET_EXQ_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822B) & BIT_MASK_EXQ_FREEPG_V1_8822B) +#define BIT_SET_EXQ_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_EXQ_FREEPG_V1_8822B(x) | BIT_EXQ_FREEPG_V1_8822B(v)) /* 2 REG_SDIO_HTSFR_INFO_8822B */ #define BIT_SHIFT_HTSFR1_8822B 16 #define BIT_MASK_HTSFR1_8822B 0xffff -#define BIT_HTSFR1_8822B(x) (((x) & BIT_MASK_HTSFR1_8822B) << BIT_SHIFT_HTSFR1_8822B) -#define BIT_GET_HTSFR1_8822B(x) (((x) >> BIT_SHIFT_HTSFR1_8822B) & BIT_MASK_HTSFR1_8822B) - - +#define BIT_HTSFR1_8822B(x) \ + (((x) & BIT_MASK_HTSFR1_8822B) << BIT_SHIFT_HTSFR1_8822B) +#define BITS_HTSFR1_8822B (BIT_MASK_HTSFR1_8822B << BIT_SHIFT_HTSFR1_8822B) +#define BIT_CLEAR_HTSFR1_8822B(x) ((x) & (~BITS_HTSFR1_8822B)) +#define BIT_GET_HTSFR1_8822B(x) \ + (((x) >> BIT_SHIFT_HTSFR1_8822B) & BIT_MASK_HTSFR1_8822B) +#define BIT_SET_HTSFR1_8822B(x, v) \ + (BIT_CLEAR_HTSFR1_8822B(x) | BIT_HTSFR1_8822B(v)) #define BIT_SHIFT_HTSFR0_8822B 0 #define BIT_MASK_HTSFR0_8822B 0xffff -#define BIT_HTSFR0_8822B(x) (((x) & BIT_MASK_HTSFR0_8822B) << BIT_SHIFT_HTSFR0_8822B) -#define BIT_GET_HTSFR0_8822B(x) (((x) >> BIT_SHIFT_HTSFR0_8822B) & BIT_MASK_HTSFR0_8822B) - - +#define BIT_HTSFR0_8822B(x) \ + (((x) & BIT_MASK_HTSFR0_8822B) << BIT_SHIFT_HTSFR0_8822B) +#define BITS_HTSFR0_8822B (BIT_MASK_HTSFR0_8822B << BIT_SHIFT_HTSFR0_8822B) +#define BIT_CLEAR_HTSFR0_8822B(x) ((x) & (~BITS_HTSFR0_8822B)) +#define BIT_GET_HTSFR0_8822B(x) \ + (((x) >> BIT_SHIFT_HTSFR0_8822B) & BIT_MASK_HTSFR0_8822B) +#define BIT_SET_HTSFR0_8822B(x, v) \ + (BIT_CLEAR_HTSFR0_8822B(x) | BIT_HTSFR0_8822B(v)) /* 2 REG_SDIO_HCPWM1_V2_8822B */ -#define BIT_TOGGLING_8822B BIT(7) -#define BIT_ACK_8822B BIT(6) -#define BIT_SYS_CLK_8822B BIT(0) +#define BIT_TOGGLE_8822B BIT(7) +#define BIT_CUR_PS_8822B BIT(0) /* 2 REG_SDIO_HCPWM2_V2_8822B */ @@ -11012,49 +17634,83 @@ #define BIT_SHIFT_INDIRECT_REG_SIZE_8822B 16 #define BIT_MASK_INDIRECT_REG_SIZE_8822B 0x3 -#define BIT_INDIRECT_REG_SIZE_8822B(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE_8822B) << BIT_SHIFT_INDIRECT_REG_SIZE_8822B) -#define BIT_GET_INDIRECT_REG_SIZE_8822B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822B) & BIT_MASK_INDIRECT_REG_SIZE_8822B) - - +#define BIT_INDIRECT_REG_SIZE_8822B(x) \ + (((x) & BIT_MASK_INDIRECT_REG_SIZE_8822B) \ + << BIT_SHIFT_INDIRECT_REG_SIZE_8822B) +#define BITS_INDIRECT_REG_SIZE_8822B \ + (BIT_MASK_INDIRECT_REG_SIZE_8822B << BIT_SHIFT_INDIRECT_REG_SIZE_8822B) +#define BIT_CLEAR_INDIRECT_REG_SIZE_8822B(x) \ + ((x) & (~BITS_INDIRECT_REG_SIZE_8822B)) +#define BIT_GET_INDIRECT_REG_SIZE_8822B(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822B) & \ + BIT_MASK_INDIRECT_REG_SIZE_8822B) +#define BIT_SET_INDIRECT_REG_SIZE_8822B(x, v) \ + (BIT_CLEAR_INDIRECT_REG_SIZE_8822B(x) | BIT_INDIRECT_REG_SIZE_8822B(v)) #define BIT_SHIFT_INDIRECT_REG_ADDR_8822B 0 #define BIT_MASK_INDIRECT_REG_ADDR_8822B 0xffff -#define BIT_INDIRECT_REG_ADDR_8822B(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR_8822B) << BIT_SHIFT_INDIRECT_REG_ADDR_8822B) -#define BIT_GET_INDIRECT_REG_ADDR_8822B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822B) & BIT_MASK_INDIRECT_REG_ADDR_8822B) - - +#define BIT_INDIRECT_REG_ADDR_8822B(x) \ + (((x) & BIT_MASK_INDIRECT_REG_ADDR_8822B) \ + << BIT_SHIFT_INDIRECT_REG_ADDR_8822B) +#define BITS_INDIRECT_REG_ADDR_8822B \ + (BIT_MASK_INDIRECT_REG_ADDR_8822B << BIT_SHIFT_INDIRECT_REG_ADDR_8822B) +#define BIT_CLEAR_INDIRECT_REG_ADDR_8822B(x) \ + ((x) & (~BITS_INDIRECT_REG_ADDR_8822B)) +#define BIT_GET_INDIRECT_REG_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822B) & \ + BIT_MASK_INDIRECT_REG_ADDR_8822B) +#define BIT_SET_INDIRECT_REG_ADDR_8822B(x, v) \ + (BIT_CLEAR_INDIRECT_REG_ADDR_8822B(x) | BIT_INDIRECT_REG_ADDR_8822B(v)) /* 2 REG_SDIO_INDIRECT_REG_DATA_8822B */ #define BIT_SHIFT_INDIRECT_REG_DATA_8822B 0 #define BIT_MASK_INDIRECT_REG_DATA_8822B 0xffffffffL -#define BIT_INDIRECT_REG_DATA_8822B(x) (((x) & BIT_MASK_INDIRECT_REG_DATA_8822B) << BIT_SHIFT_INDIRECT_REG_DATA_8822B) -#define BIT_GET_INDIRECT_REG_DATA_8822B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822B) & BIT_MASK_INDIRECT_REG_DATA_8822B) - - +#define BIT_INDIRECT_REG_DATA_8822B(x) \ + (((x) & BIT_MASK_INDIRECT_REG_DATA_8822B) \ + << BIT_SHIFT_INDIRECT_REG_DATA_8822B) +#define BITS_INDIRECT_REG_DATA_8822B \ + (BIT_MASK_INDIRECT_REG_DATA_8822B << BIT_SHIFT_INDIRECT_REG_DATA_8822B) +#define BIT_CLEAR_INDIRECT_REG_DATA_8822B(x) \ + ((x) & (~BITS_INDIRECT_REG_DATA_8822B)) +#define BIT_GET_INDIRECT_REG_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822B) & \ + BIT_MASK_INDIRECT_REG_DATA_8822B) +#define BIT_SET_INDIRECT_REG_DATA_8822B(x, v) \ + (BIT_CLEAR_INDIRECT_REG_DATA_8822B(x) | BIT_INDIRECT_REG_DATA_8822B(v)) /* 2 REG_SDIO_H2C_8822B */ #define BIT_SHIFT_SDIO_H2C_MSG_8822B 0 #define BIT_MASK_SDIO_H2C_MSG_8822B 0xffffffffL -#define BIT_SDIO_H2C_MSG_8822B(x) (((x) & BIT_MASK_SDIO_H2C_MSG_8822B) << BIT_SHIFT_SDIO_H2C_MSG_8822B) -#define BIT_GET_SDIO_H2C_MSG_8822B(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822B) & BIT_MASK_SDIO_H2C_MSG_8822B) - - +#define BIT_SDIO_H2C_MSG_8822B(x) \ + (((x) & BIT_MASK_SDIO_H2C_MSG_8822B) << BIT_SHIFT_SDIO_H2C_MSG_8822B) +#define BITS_SDIO_H2C_MSG_8822B \ + (BIT_MASK_SDIO_H2C_MSG_8822B << BIT_SHIFT_SDIO_H2C_MSG_8822B) +#define BIT_CLEAR_SDIO_H2C_MSG_8822B(x) ((x) & (~BITS_SDIO_H2C_MSG_8822B)) +#define BIT_GET_SDIO_H2C_MSG_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822B) & BIT_MASK_SDIO_H2C_MSG_8822B) +#define BIT_SET_SDIO_H2C_MSG_8822B(x, v) \ + (BIT_CLEAR_SDIO_H2C_MSG_8822B(x) | BIT_SDIO_H2C_MSG_8822B(v)) /* 2 REG_SDIO_C2H_8822B */ #define BIT_SHIFT_SDIO_C2H_MSG_8822B 0 #define BIT_MASK_SDIO_C2H_MSG_8822B 0xffffffffL -#define BIT_SDIO_C2H_MSG_8822B(x) (((x) & BIT_MASK_SDIO_C2H_MSG_8822B) << BIT_SHIFT_SDIO_C2H_MSG_8822B) -#define BIT_GET_SDIO_C2H_MSG_8822B(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822B) & BIT_MASK_SDIO_C2H_MSG_8822B) - - +#define BIT_SDIO_C2H_MSG_8822B(x) \ + (((x) & BIT_MASK_SDIO_C2H_MSG_8822B) << BIT_SHIFT_SDIO_C2H_MSG_8822B) +#define BITS_SDIO_C2H_MSG_8822B \ + (BIT_MASK_SDIO_C2H_MSG_8822B << BIT_SHIFT_SDIO_C2H_MSG_8822B) +#define BIT_CLEAR_SDIO_C2H_MSG_8822B(x) ((x) & (~BITS_SDIO_C2H_MSG_8822B)) +#define BIT_GET_SDIO_C2H_MSG_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822B) & BIT_MASK_SDIO_C2H_MSG_8822B) +#define BIT_SET_SDIO_C2H_MSG_8822B(x, v) \ + (BIT_CLEAR_SDIO_C2H_MSG_8822B(x) | BIT_SDIO_C2H_MSG_8822B(v)) /* 2 REG_SDIO_HRPWM1_8822B */ -#define BIT_TOGGLING_8822B BIT(7) +#define BIT_TOGGLE_8822B BIT(7) #define BIT_ACK_8822B BIT(6) -#define BIT_32K_PERMISSION_8822B BIT(0) +#define BIT_REQ_PS_8822B BIT(0) /* 2 REG_SDIO_HRPWM2_8822B */ @@ -11077,27 +17733,39 @@ #define BIT_SHIFT_CMDIN_2RESP_TIMER_8822B 0 #define BIT_MASK_CMDIN_2RESP_TIMER_8822B 0xffff -#define BIT_CMDIN_2RESP_TIMER_8822B(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822B) << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) -#define BIT_GET_CMDIN_2RESP_TIMER_8822B(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) & BIT_MASK_CMDIN_2RESP_TIMER_8822B) - - +#define BIT_CMDIN_2RESP_TIMER_8822B(x) \ + (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822B) \ + << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) +#define BITS_CMDIN_2RESP_TIMER_8822B \ + (BIT_MASK_CMDIN_2RESP_TIMER_8822B << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) +#define BIT_CLEAR_CMDIN_2RESP_TIMER_8822B(x) \ + ((x) & (~BITS_CMDIN_2RESP_TIMER_8822B)) +#define BIT_GET_CMDIN_2RESP_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) & \ + BIT_MASK_CMDIN_2RESP_TIMER_8822B) +#define BIT_SET_CMDIN_2RESP_TIMER_8822B(x, v) \ + (BIT_CLEAR_CMDIN_2RESP_TIMER_8822B(x) | BIT_CMDIN_2RESP_TIMER_8822B(v)) /* 2 REG_SDIO_CMD_CRC_8822B */ #define BIT_SHIFT_SDIO_CMD_CRC_V1_8822B 0 #define BIT_MASK_SDIO_CMD_CRC_V1_8822B 0xff -#define BIT_SDIO_CMD_CRC_V1_8822B(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822B) << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) -#define BIT_GET_SDIO_CMD_CRC_V1_8822B(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) & BIT_MASK_SDIO_CMD_CRC_V1_8822B) - - +#define BIT_SDIO_CMD_CRC_V1_8822B(x) \ + (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822B) \ + << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) +#define BITS_SDIO_CMD_CRC_V1_8822B \ + (BIT_MASK_SDIO_CMD_CRC_V1_8822B << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) +#define BIT_CLEAR_SDIO_CMD_CRC_V1_8822B(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8822B)) +#define BIT_GET_SDIO_CMD_CRC_V1_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) & \ + BIT_MASK_SDIO_CMD_CRC_V1_8822B) +#define BIT_SET_SDIO_CMD_CRC_V1_8822B(x, v) \ + (BIT_CLEAR_SDIO_CMD_CRC_V1_8822B(x) | BIT_SDIO_CMD_CRC_V1_8822B(v)) /* 2 REG_SDIO_HSISR_8822B */ #define BIT_DRV_WLAN_INT_CLR_8822B BIT(1) #define BIT_DRV_WLAN_INT_8822B BIT(0) -/* 2 REG_SDIO_HSIMR_8822B */ -#define BIT_HISR_MASK_8822B BIT(0) - /* 2 REG_SDIO_ERR_RPT_8822B */ #define BIT_HR_FF_OVF_8822B BIT(6) #define BIT_HR_FF_UDN_8822B BIT(5) @@ -11111,28 +17779,53 @@ #define BIT_SHIFT_CMD_CRC_ERR_CNT_8822B 0 #define BIT_MASK_CMD_CRC_ERR_CNT_8822B 0xff -#define BIT_CMD_CRC_ERR_CNT_8822B(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822B) << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) -#define BIT_GET_CMD_CRC_ERR_CNT_8822B(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) & BIT_MASK_CMD_CRC_ERR_CNT_8822B) - - +#define BIT_CMD_CRC_ERR_CNT_8822B(x) \ + (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822B) \ + << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) +#define BITS_CMD_CRC_ERR_CNT_8822B \ + (BIT_MASK_CMD_CRC_ERR_CNT_8822B << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) +#define BIT_CLEAR_CMD_CRC_ERR_CNT_8822B(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8822B)) +#define BIT_GET_CMD_CRC_ERR_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) & \ + BIT_MASK_CMD_CRC_ERR_CNT_8822B) +#define BIT_SET_CMD_CRC_ERR_CNT_8822B(x, v) \ + (BIT_CLEAR_CMD_CRC_ERR_CNT_8822B(x) | BIT_CMD_CRC_ERR_CNT_8822B(v)) /* 2 REG_SDIO_DATA_ERRCNT_8822B */ #define BIT_SHIFT_DATA_CRC_ERR_CNT_8822B 0 #define BIT_MASK_DATA_CRC_ERR_CNT_8822B 0xff -#define BIT_DATA_CRC_ERR_CNT_8822B(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822B) << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) -#define BIT_GET_DATA_CRC_ERR_CNT_8822B(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) & BIT_MASK_DATA_CRC_ERR_CNT_8822B) - - +#define BIT_DATA_CRC_ERR_CNT_8822B(x) \ + (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822B) \ + << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) +#define BITS_DATA_CRC_ERR_CNT_8822B \ + (BIT_MASK_DATA_CRC_ERR_CNT_8822B << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) +#define BIT_CLEAR_DATA_CRC_ERR_CNT_8822B(x) \ + ((x) & (~BITS_DATA_CRC_ERR_CNT_8822B)) +#define BIT_GET_DATA_CRC_ERR_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) & \ + BIT_MASK_DATA_CRC_ERR_CNT_8822B) +#define BIT_SET_DATA_CRC_ERR_CNT_8822B(x, v) \ + (BIT_CLEAR_DATA_CRC_ERR_CNT_8822B(x) | BIT_DATA_CRC_ERR_CNT_8822B(v)) /* 2 REG_SDIO_CMD_ERR_CONTENT_8822B */ #define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B 0 #define BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B 0xffffffffffL -#define BIT_SDIO_CMD_ERR_CONTENT_8822B(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) -#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822B(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B) - - +#define BIT_SDIO_CMD_ERR_CONTENT_8822B(x) \ + (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B) \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) +#define BITS_SDIO_CMD_ERR_CONTENT_8822B \ + (BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) +#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822B(x) \ + ((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8822B)) +#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) & \ + BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B) +#define BIT_SET_SDIO_CMD_ERR_CONTENT_8822B(x, v) \ + (BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822B(x) | \ + BIT_SDIO_CMD_ERR_CONTENT_8822B(v)) /* 2 REG_SDIO_CRC_ERR_IDX_8822B */ #define BIT_D3_CRC_ERR_8822B BIT(4) @@ -11144,19 +17837,34 @@ /* 2 REG_SDIO_DATA_CRC_8822B */ #define BIT_SHIFT_SDIO_DATA_CRC_8822B 0 -#define BIT_MASK_SDIO_DATA_CRC_8822B 0xff -#define BIT_SDIO_DATA_CRC_8822B(x) (((x) & BIT_MASK_SDIO_DATA_CRC_8822B) << BIT_SHIFT_SDIO_DATA_CRC_8822B) -#define BIT_GET_SDIO_DATA_CRC_8822B(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822B) & BIT_MASK_SDIO_DATA_CRC_8822B) - - +#define BIT_MASK_SDIO_DATA_CRC_8822B 0xffff +#define BIT_SDIO_DATA_CRC_8822B(x) \ + (((x) & BIT_MASK_SDIO_DATA_CRC_8822B) << BIT_SHIFT_SDIO_DATA_CRC_8822B) +#define BITS_SDIO_DATA_CRC_8822B \ + (BIT_MASK_SDIO_DATA_CRC_8822B << BIT_SHIFT_SDIO_DATA_CRC_8822B) +#define BIT_CLEAR_SDIO_DATA_CRC_8822B(x) ((x) & (~BITS_SDIO_DATA_CRC_8822B)) +#define BIT_GET_SDIO_DATA_CRC_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822B) & BIT_MASK_SDIO_DATA_CRC_8822B) +#define BIT_SET_SDIO_DATA_CRC_8822B(x, v) \ + (BIT_CLEAR_SDIO_DATA_CRC_8822B(x) | BIT_SDIO_DATA_CRC_8822B(v)) /* 2 REG_SDIO_DATA_REPLY_TIME_8822B */ #define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B 0 #define BIT_MASK_SDIO_DATA_REPLY_TIME_8822B 0x7 -#define BIT_SDIO_DATA_REPLY_TIME_8822B(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B) << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) -#define BIT_GET_SDIO_DATA_REPLY_TIME_8822B(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B) - - +#define BIT_SDIO_DATA_REPLY_TIME_8822B(x) \ + (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B) \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) +#define BITS_SDIO_DATA_REPLY_TIME_8822B \ + (BIT_MASK_SDIO_DATA_REPLY_TIME_8822B \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) +#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8822B(x) \ + ((x) & (~BITS_SDIO_DATA_REPLY_TIME_8822B)) +#define BIT_GET_SDIO_DATA_REPLY_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) & \ + BIT_MASK_SDIO_DATA_REPLY_TIME_8822B) +#define BIT_SET_SDIO_DATA_REPLY_TIME_8822B(x, v) \ + (BIT_CLEAR_SDIO_DATA_REPLY_TIME_8822B(x) | \ + BIT_SDIO_DATA_REPLY_TIME_8822B(v)) #endif diff --git a/hal/halmac/halmac_fw_info.h b/hal/halmac/halmac_fw_info.h index 5d2a0a7..1da64fb 100644 --- a/hal/halmac/halmac_fw_info.h +++ b/hal/halmac/halmac_fw_info.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,22 +16,41 @@ #ifndef _HALMAC_FW_INFO_H_ #define _HALMAC_FW_INFO_H_ -#define H2C_FORMAT_VERSION 6 - -#define H2C_ACK_HDR_CONTENT_LENGTH 8 -#define CFG_PARAMETER_ACK_CONTENT_LENGTH 16 -#define SCAN_STATUS_RPT_CONTENT_LENGTH 4 -#define C2H_DBG_HEADER_LENGTH 4 -#define C2H_DBG_CONTENT_MAX_LENGTH 228 - -#define C2H_DBG_CONTENT_SEQ_OFFSET 1 +#define H2C_FORMAT_VERSION 11 + +/* FW bin information */ +#define WLAN_FW_HDR_SIZE 64 +#define WLAN_FW_HDR_CHKSUM_SIZE 8 + +#define WLAN_FW_HDR_VERSION 4 +#define WLAN_FW_HDR_SUBVERSION 6 +#define WLAN_FW_HDR_SUBINDEX 7 +#define WLAN_FW_HDR_MONTH 16 +#define WLAN_FW_HDR_DATE 17 +#define WLAN_FW_HDR_HOUR 18 +#define WLAN_FW_HDR_MIN 19 +#define WLAN_FW_HDR_YEAR 20 +#define WLAN_FW_HDR_MEM_USAGE 24 +#define WLAN_FW_HDR_H2C_FMT_VER 28 +#define WLAN_FW_HDR_DMEM_ADDR 32 +#define WLAN_FW_HDR_DMEM_SIZE 36 +#define WLAN_FW_HDR_IMEM_SIZE 48 +#define WLAN_FW_HDR_EMEM_SIZE 52 +#define WLAN_FW_HDR_EMEM_ADDR 56 +#define WLAN_FW_HDR_IMEM_ADDR 60 + +#define H2C_ACK_HDR_CONTENT_LENGTH 8 +#define CFG_PARAMETER_ACK_CONTENT_LENGTH 16 +#define SCAN_STATUS_RPT_CONTENT_LENGTH 4 +#define C2H_DBG_HDR_LEN 4 +#define C2H_DBG_CONTENT_MAX_LENGTH 228 +#define C2H_DBG_CONTENT_SEQ_OFFSET 1 /* Rename from FW SysHalCom_Debug_RAM.h */ -#define FW_REG_H2CPKT_DONE_SEQ 0x1C8 -#define FW_REG_WoW_REASON 0x1C7 - +#define FW_REG_H2CPKT_DONE_SEQ 0x1C8 +#define FW_REG_WOW_REASON 0x1C7 -typedef enum _HALMAC_DATA_TYPE { +enum halmac_data_type { HALMAC_DATA_TYPE_MAC_REG = 0x00, HALMAC_DATA_TYPE_BB_REG = 0x01, HALMAC_DATA_TYPE_RADIO_A = 0x02, @@ -44,73 +63,57 @@ typedef enum _HALMAC_DATA_TYPE { HALMAC_DATA_TYPE_DRV_DEFINE_2 = 0x82, HALMAC_DATA_TYPE_DRV_DEFINE_3 = 0x83, HALMAC_DATA_TYPE_UNDEFINE = 0x7FFFFFFF, -} HALMAC_DATA_TYPE; +}; -typedef enum _HALMAC_PACKET_ID { +enum halmac_packet_id { HALMAC_PACKET_PROBE_REQ = 0x00, HALMAC_PACKET_SYNC_BCN = 0x01, HALMAC_PACKET_DISCOVERY_BCN = 0x02, - HALMAC_PACKET_UNDEFINE = 0x7FFFFFFF, -} HALMAC_PACKET_ID; +}; -/* Channel Switch Action ID */ -typedef enum _HALMAC_CS_ACTION_ID { +enum halmac_cs_action_id { HALMAC_CS_ACTION_NONE = 0x00, HALMAC_CS_ACTIVE_SCAN = 0x01, HALMAC_CS_NAN_NONMASTER_DW = 0x02, HALMAC_CS_NAN_NONMASTER_NONDW = 0x03, HALMAC_CS_NAN_MASTER_NONDW = 0x04, HALMAC_CS_NAN_MASTER_DW = 0x05, - HALMAC_CS_ACTION_UNDEFINE = 0x7FFFFFFF, -} HALMAC_CS_ACTION_ID; +}; -/* Channel Switch Extra Action ID */ -typedef enum _HALMAC_CS_EXTRA_ACTION_ID { +enum halmac_cs_extra_action_id { HALMAC_CS_EXTRA_ACTION_NONE = 0x00, HALMAC_CS_EXTRA_UPDATE_PROBE = 0x01, HALMAC_CS_EXTRA_UPDATE_BEACON = 0x02, - - HALMAC_CS_EXTRA_ACTION_UNDEFINE = 0x7FFFFFFF, -} HALMAC_CS_EXTRA_ACTION_ID; +}; -typedef enum _HALMAC_H2C_RETURN_CODE { +enum halmac_h2c_return_code { HALMAC_H2C_RETURN_SUCCESS = 0x00, HALMAC_H2C_RETURN_CFG_ERR_LEN = 0x01, HALMAC_H2C_RETURN_CFG_ERR_CMD = 0x02, - HALMAC_H2C_RETURN_EFUSE_ERR_DUMP = 0x03, - - HALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04, /* DMEM buffer full */ - HALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05, /* Invalid pack id */ - - HALMAC_H2C_RETURN_RUN_ERR_EMPTY = 0x06, /* No data in dedicated buffer */ + HALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04, + HALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05, + HALMAC_H2C_RETURN_RUN_ERR_EMPTY = 0x06, HALMAC_H2C_RETURN_RUN_ERR_LEN = 0x07, HALMAC_H2C_RETURN_RUN_ERR_CMD = 0x08, - HALMAC_H2C_RETURN_RUN_ERR_ID = 0x09, /* Invalid pack id */ - - HALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A, /* DMEM buffer full */ - HALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B, /* Invalid packet id */ - - HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C, /* DMEM buffer full */ - HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D, /* PHYDM API return fail */ - - HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E, /* Invalid original H2C cmd id */ - + HALMAC_H2C_RETURN_RUN_ERR_ID = 0x09, + HALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A, + HALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B, + HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C, + HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D, + HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E, HALMAC_H2C_RETURN_UNDEFINE = 0x7FFFFFFF, -} HALMAC_H2C_RETURN_CODE; - -typedef enum _HALMAC_SCAN_REPORT_CODE { - HALMAC_SCAN_REPORT_DONE = 0x00, - HALMAC_SCAN_REPORT_ERR_PHYDM = 0x01, /* PHYDM API return fail */ - HALMAC_SCAN_REPORT_ERR_ID = 0x02, /* Invalid ActionID */ - HALMAC_SCAN_REPORT_ERR_TX = 0x03, /* Tx RsvdPage fail */ +}; +enum halmac_scan_report_code { + HALMAC_SCAN_REPORT_DONE = 0x00, + HALMAC_SCAN_REPORT_ERR_PHYDM = 0x01, + HALMAC_SCAN_REPORT_ERR_ID = 0x02, + HALMAC_SCAN_REPORT_ERR_TX = 0x03, HALMAC_SCAN_REPORT_UNDEFINE = 0x7FFFFFFF, -} HALMAC_SCAN_REPORT_CODE; - - +}; #endif diff --git a/hal/halmac/halmac_fw_offload_c2h_ap.h b/hal/halmac/halmac_fw_offload_c2h_ap.h index ddd3fbe..635443e 100644 --- a/hal/halmac/halmac_fw_offload_c2h_ap.h +++ b/hal/halmac/halmac_fw_offload_c2h_ap.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,158 +15,492 @@ #ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_ #define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_ -#define C2H_SUB_CMD_ID_C2H_DBG 0X00 -#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02 -#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03 -#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01 -#define C2H_SUB_CMD_ID_CFG_PARAMETER_ACK 0X01 -#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01 -#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01 -#define C2H_SUB_CMD_ID_UPDATE_PACKET_ACK 0X01 -#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01 -#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01 -#define C2H_SUB_CMD_ID_CHANNEL_SWITCH_ACK 0X01 -#define C2H_SUB_CMD_ID_IQK_ACK 0X01 -#define C2H_SUB_CMD_ID_POWER_TRACKING_ACK 0X01 -#define C2H_SUB_CMD_ID_PSD_ACK 0X01 -#define C2H_SUB_CMD_ID_PSD_DATA 0X04 -#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05 -#define C2H_SUB_CMD_ID_IQK_DATA 0X06 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A -#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B -#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C -#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E -#define C2H_SUB_CMD_ID_CCX_RPT 0X0F -#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10 -#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11 -#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C -#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D -#define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER +#define C2H_SUB_CMD_ID_C2H_DBG 0X00 +#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02 +#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03 +#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01 +#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01 +#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01 +#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01 +#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01 +#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01 +#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01 +#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01 +#define C2H_SUB_CMD_ID_IQK_ACK 0X01 +#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01 +#define C2H_SUB_CMD_ID_PSD_ACK 0X01 +#define C2H_SUB_CMD_ID_PSD_DATA 0X04 +#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05 +#define C2H_SUB_CMD_ID_IQK_DATA 0X06 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A +#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B +#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C +#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E +#define C2H_SUB_CMD_ID_CCX_RPT 0X0F +#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10 +#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11 +#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C +#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D +#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF +#define C2H_SUB_CMD_ID_FW_SNDING_ACK 0X01 +#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F +#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20 +#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21 +#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM #define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX #define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE -#define H2C_SUB_CMD_ID_UPDATE_PACKET_ACK SUB_CMD_ID_UPDATE_PACKET +#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT #define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK #define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK -#define H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK SUB_CMD_ID_CHANNEL_SWITCH +#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH #define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK -#define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING +#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK #define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD #define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT -#define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF -#define H2C_CMD_ID_BT_COEX_ACK 0XFF -#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF -#define H2C_CMD_ID_UPDATE_PACKET_ACK 0XFF -#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF -#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF -#define H2C_CMD_ID_CHANNEL_SWITCH_ACK 0XFF -#define H2C_CMD_ID_IQK_ACK 0XFF -#define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF -#define H2C_CMD_ID_PSD_ACK 0XFF -#define H2C_CMD_ID_CCX_RPT 0XFF -#define C2H_HDR_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_HDR_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_HDR_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_HDR_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_HDR_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_HDR_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_HDR_GET_C2H_SUB_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) -#define C2H_HDR_SET_C2H_SUB_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_HDR_SET_C2H_SUB_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_HDR_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define C2H_HDR_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_HDR_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_DBG_GET_DBG_MSG(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define C2H_DBG_SET_DBG_MSG(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_DBG_SET_DBG_MSG_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define BT_COEX_INFO_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define BT_COEX_INFO_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define BT_COEX_INFO_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define SCAN_STATUS_RPT_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) -#define SCAN_STATUS_RPT_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) -#define SCAN_STATUS_RPT_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) -#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define H2C_ACK_HDR_SET_H2C_RETURN_CODE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define H2C_ACK_HDR_GET_H2C_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define H2C_ACK_HDR_SET_H2C_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define H2C_ACK_HDR_SET_H2C_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) -#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) -#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) -#define H2C_ACK_HDR_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 16) -#define H2C_ACK_HDR_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 16, __Value) -#define H2C_ACK_HDR_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 16, __Value) -#define CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(__pC2H) GET_C2H_FIELD(__pC2H + 0XC, 0, 32) -#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0XC, 0, 32, __Value) -#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0XC, 0, 32, __Value) -#define CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(__pC2H) GET_C2H_FIELD(__pC2H + 0X10, 0, 32) -#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X10, 0, 32, __Value) -#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X10, 0, 32, __Value) -#define BT_COEX_ACK_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0XC, 0, 8) -#define BT_COEX_ACK_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0XC, 0, 8, __Value) -#define BT_COEX_ACK_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0XC, 0, 8, __Value) -#define PSD_DATA_GET_SEGMENT_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 7) -#define PSD_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 7, __Value) -#define PSD_DATA_SET_SEGMENT_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 7, __Value) -#define PSD_DATA_GET_END_SEGMENT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 7, 1) -#define PSD_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 7, 1, __Value) -#define PSD_DATA_SET_END_SEGMENT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 7, 1, __Value) -#define PSD_DATA_GET_SEGMENT_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define PSD_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define PSD_DATA_SET_SEGMENT_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define PSD_DATA_GET_TOTAL_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) -#define PSD_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) -#define PSD_DATA_SET_TOTAL_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) -#define PSD_DATA_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 0, 16) -#define PSD_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 0, 16, __Value) -#define PSD_DATA_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 0, 16, __Value) -#define PSD_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8) -#define PSD_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value) -#define PSD_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value) -#define EFUSE_DATA_GET_SEGMENT_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 7) -#define EFUSE_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 7, __Value) -#define EFUSE_DATA_SET_SEGMENT_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 7, __Value) -#define EFUSE_DATA_GET_END_SEGMENT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 7, 1) -#define EFUSE_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 7, 1, __Value) -#define EFUSE_DATA_SET_END_SEGMENT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 7, 1, __Value) -#define EFUSE_DATA_GET_SEGMENT_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define EFUSE_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define EFUSE_DATA_SET_SEGMENT_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define EFUSE_DATA_GET_TOTAL_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) -#define EFUSE_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) -#define EFUSE_DATA_SET_TOTAL_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) -#define EFUSE_DATA_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 0, 16) -#define EFUSE_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 0, 16, __Value) -#define EFUSE_DATA_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 0, 16, __Value) -#define EFUSE_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8) -#define EFUSE_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value) -#define EFUSE_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value) -#define IQK_DATA_GET_SEGMENT_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 7) -#define IQK_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 7, __Value) -#define IQK_DATA_SET_SEGMENT_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 7, __Value) -#define IQK_DATA_GET_END_SEGMENT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 7, 1) -#define IQK_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 7, 1, __Value) -#define IQK_DATA_SET_END_SEGMENT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 7, 1, __Value) -#define IQK_DATA_GET_SEGMENT_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define IQK_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define IQK_DATA_SET_SEGMENT_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define IQK_DATA_GET_TOTAL_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) -#define IQK_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) -#define IQK_DATA_SET_TOTAL_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) -#define IQK_DATA_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 0, 16) -#define IQK_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 0, 16, __Value) -#define IQK_DATA_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 0, 16, __Value) -#define IQK_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8) -#define IQK_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value) -#define IQK_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value) -#define CCX_RPT_GET_CCX_RPT(__pC2H) GET_C2H_FIELD(__pC2H + 0X4, 0, 129) -#define CCX_RPT_SET_CCX_RPT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X4, 0, 129, __Value) -#define CCX_RPT_SET_CCX_RPT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X4, 0, 129, __Value) +#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG +#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING +#define H2C_SUB_CMD_ID_FW_FWCTRL_RPT SUB_CMD_ID_FW_FWCTRL_RPT +#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK +#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK +#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF +#define H2C_CMD_ID_BT_COEX_ACK 0XFF +#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF +#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF +#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF +#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF +#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF +#define H2C_CMD_ID_IQK_ACK 0XFF +#define H2C_CMD_ID_PWR_TRK_ACK 0XFF +#define H2C_CMD_ID_PSD_ACK 0XFF +#define H2C_CMD_ID_CCX_RPT 0XFF +#define H2C_CMD_ID_FW_DBG_MSG 0XFF +#define H2C_CMD_ID_FW_SNDING_ACK 0XFF +#define H2C_CMD_ID_FW_FWCTRL_RPT 0XFF +#define H2C_CMD_ID_H2C_LOOPBACK_ACK 0XFF +#define H2C_CMD_ID_FWCMD_LOOPBACK_ACK 0XFF +#define C2H_HDR_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_HDR_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_HDR_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_HDR_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_HDR_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_HDR_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define C2H_HDR_SET_C2H_SUB_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_HDR_SET_C2H_SUB_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_HDR_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define C2H_HDR_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_HDR_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_DBG_GET_DBG_MSG(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define C2H_DBG_SET_DBG_MSG(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_DBG_SET_DBG_MSG_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define BT_COEX_INFO_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define BT_COEX_INFO_SET_DATA_START(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define BT_COEX_INFO_SET_DATA_START_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define SCAN_STATUS_RPT_GET_H2C_SEQ(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16) +#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value) +#define SCAN_STATUS_RPT_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value) +#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define H2C_ACK_HDR_SET_H2C_RETURN_CODE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define H2C_ACK_HDR_SET_H2C_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define H2C_ACK_HDR_SET_H2C_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16) +#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value) +#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value) +#define H2C_ACK_HDR_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 16) +#define H2C_ACK_HDR_SET_H2C_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 16, value) +#define H2C_ACK_HDR_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 16, value) +#define CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0XC, 0, 32) +#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 32, value) +#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 32, value) +#define CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X10, 0, 32) +#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 0, 32, value) +#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 0, 32, value) +#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 8) +#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 8, value) +#define BT_COEX_ACK_SET_DATA_START_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 8, value) +#define PSD_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7) +#define PSD_DATA_SET_SEGMENT_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value) +#define PSD_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value) +#define PSD_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1) +#define PSD_DATA_SET_END_SEGMENT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value) +#define PSD_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value) +#define PSD_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define PSD_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define PSD_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define PSD_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16) +#define PSD_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value) +#define PSD_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value) +#define PSD_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16) +#define PSD_DATA_SET_H2C_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value) +#define PSD_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value) +#define PSD_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8) +#define PSD_DATA_SET_DATA_START(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value) +#define PSD_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value) +#define EFUSE_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7) +#define EFUSE_DATA_SET_SEGMENT_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value) +#define EFUSE_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value) +#define EFUSE_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1) +#define EFUSE_DATA_SET_END_SEGMENT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value) +#define EFUSE_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value) +#define EFUSE_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define EFUSE_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define EFUSE_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define EFUSE_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16) +#define EFUSE_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value) +#define EFUSE_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value) +#define EFUSE_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16) +#define EFUSE_DATA_SET_H2C_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value) +#define EFUSE_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value) +#define EFUSE_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8) +#define EFUSE_DATA_SET_DATA_START(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value) +#define EFUSE_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value) +#define IQK_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7) +#define IQK_DATA_SET_SEGMENT_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value) +#define IQK_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value) +#define IQK_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1) +#define IQK_DATA_SET_END_SEGMENT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value) +#define IQK_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value) +#define IQK_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define IQK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define IQK_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define IQK_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16) +#define IQK_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value) +#define IQK_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value) +#define IQK_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16) +#define IQK_DATA_SET_H2C_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value) +#define IQK_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value) +#define IQK_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8) +#define IQK_DATA_SET_DATA_START(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value) +#define IQK_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value) +#define CCX_RPT_GET_POLLUTED(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 0, 1) +#define CCX_RPT_SET_POLLUTED(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 0, 1, value) +#define CCX_RPT_SET_POLLUTED_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 0, 1, value) +#define CCX_RPT_GET_RPT_SEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 5, 3) +#define CCX_RPT_SET_RPT_SEL(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 5, 3, value) +#define CCX_RPT_SET_RPT_SEL_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 5, 3, value) +#define CCX_RPT_GET_QSEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 8, 5) +#define CCX_RPT_SET_QSEL(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 8, 5, value) +#define CCX_RPT_SET_QSEL_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 8, 5, value) +#define CCX_RPT_GET_MISSED_RPT_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 13, 3) +#define CCX_RPT_SET_MISSED_RPT_NUM(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 13, 3, value) +#define CCX_RPT_SET_MISSED_RPT_NUM_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 13, 3, value) +#define CCX_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 16, 7) +#define CCX_RPT_SET_MACID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 16, 7, value) +#define CCX_RPT_SET_MACID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 16, 7, value) +#define CCX_RPT_GET_INITIAL_DATA_RATE(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X4, 24, 7) +#define CCX_RPT_SET_INITIAL_DATA_RATE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 24, 7, value) +#define CCX_RPT_SET_INITIAL_DATA_RATE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 24, 7, value) +#define CCX_RPT_GET_INITIAL_SGI(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 31, 1) +#define CCX_RPT_SET_INITIAL_SGI(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 31, 1, value) +#define CCX_RPT_SET_INITIAL_SGI_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 31, 1, value) +#define CCX_RPT_GET_QUEUE_TIME(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16) +#define CCX_RPT_SET_QUEUE_TIME(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value) +#define CCX_RPT_SET_QUEUE_TIME_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value) +#define CCX_RPT_GET_SW_DEFINE_BYTE0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8) +#define CCX_RPT_SET_SW_DEFINE_BYTE0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value) +#define CCX_RPT_SET_SW_DEFINE_BYTE0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value) +#define CCX_RPT_GET_RTS_RETRY_COUNT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 24, 4) +#define CCX_RPT_SET_RTS_RETRY_COUNT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 4, value) +#define CCX_RPT_SET_RTS_RETRY_COUNT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 4, value) +#define CCX_RPT_GET_BMC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 29, 1) +#define CCX_RPT_SET_BMC(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 29, 1, value) +#define CCX_RPT_SET_BMC_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 29, 1, value) +#define CCX_RPT_GET_TX_STATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 30, 2) +#define CCX_RPT_SET_TX_STATE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 30, 2, value) +#define CCX_RPT_SET_TX_STATE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 30, 2, value) +#define CCX_RPT_GET_DATA_RETRY_COUNT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 6) +#define CCX_RPT_SET_DATA_RETRY_COUNT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 6, value) +#define CCX_RPT_SET_DATA_RETRY_COUNT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 6, value) +#define CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 8, 7) +#define CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 8, 7, value) +#define CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 8, 7, value) +#define CCX_RPT_GET_FINAL_SGI(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 15, 1) +#define CCX_RPT_SET_FINAL_SGI(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 15, 1, value) +#define CCX_RPT_SET_FINAL_SGI_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 15, 1, value) +#define CCX_RPT_GET_RF_CH_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 16, 10) +#define CCX_RPT_SET_RF_CH_NUM(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 16, 10, value) +#define CCX_RPT_SET_RF_CH_NUM_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 16, 10, value) +#define CCX_RPT_GET_SC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 26, 4) +#define CCX_RPT_SET_SC(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 26, 4, value) +#define CCX_RPT_SET_SC_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 26, 4, value) +#define CCX_RPT_GET_BW(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 30, 2) +#define CCX_RPT_SET_BW(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 30, 2, value) +#define CCX_RPT_SET_BW_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 30, 2, value) +#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define FW_DBG_MSG_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define FW_DBG_MSG_GET_C2H_SUB_CMD_ID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define FW_DBG_MSG_GET_FULL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 1) +#define FW_DBG_MSG_SET_FULL(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 1, value) +#define FW_DBG_MSG_SET_FULL_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 1, value) +#define FW_DBG_MSG_GET_OWN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 31, 1) +#define FW_DBG_MSG_SET_OWN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 31, 1, value) +#define FW_DBG_MSG_SET_OWN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 31, 1, value) +#define FW_FWCTRL_RPT_GET_EVT_TYPE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define FW_FWCTRL_RPT_SET_EVT_TYPE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define FW_FWCTRL_RPT_SET_EVT_TYPE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define FW_FWCTRL_RPT_GET_LENGTH(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define FW_FWCTRL_RPT_SET_LENGTH(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define FW_FWCTRL_RPT_SET_LENGTH_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define FW_FWCTRL_RPT_GET_SEQ_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define FW_FWCTRL_RPT_SET_SEQ_NUM(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define FW_FWCTRL_RPT_SET_SEQ_NUM_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define FW_FWCTRL_RPT_GET_IS_ACK(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 1) +#define FW_FWCTRL_RPT_SET_IS_ACK(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 1, value) +#define FW_FWCTRL_RPT_SET_IS_ACK_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 1, value) +#define FW_FWCTRL_RPT_GET_MORE_CONTENT(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 25, 1) +#define FW_FWCTRL_RPT_SET_MORE_CONTENT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 25, 1, value) +#define FW_FWCTRL_RPT_SET_MORE_CONTENT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 25, 1, value) +#define FW_FWCTRL_RPT_GET_CONTENT_IDX(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 26, 6) +#define FW_FWCTRL_RPT_SET_CONTENT_IDX(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 26, 6, value) +#define FW_FWCTRL_RPT_SET_CONTENT_IDX_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 26, 6, value) +#define FW_FWCTRL_RPT_GET_CLASS_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define FW_FWCTRL_RPT_SET_CLASS_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define FW_FWCTRL_RPT_SET_CLASS_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define FW_FWCTRL_RPT_GET_CONTENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16) +#define FW_FWCTRL_RPT_SET_CONTENT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value) +#define FW_FWCTRL_RPT_SET_CONTENT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 0, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 8, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 8, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 8, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 24, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 0, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 8, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 8, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 8, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 24, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value) #endif diff --git a/hal/halmac/halmac_fw_offload_c2h_nic.h b/hal/halmac/halmac_fw_offload_c2h_nic.h index cbef4dd..b87e341 100644 --- a/hal/halmac/halmac_fw_offload_c2h_nic.h +++ b/hal/halmac/halmac_fw_offload_c2h_nic.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,124 +15,357 @@ #ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_ #define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_ -#define C2H_SUB_CMD_ID_C2H_DBG 0X00 -#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02 -#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03 -#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01 -#define C2H_SUB_CMD_ID_CFG_PARAMETER_ACK 0X01 -#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01 -#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01 -#define C2H_SUB_CMD_ID_UPDATE_PACKET_ACK 0X01 -#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01 -#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01 -#define C2H_SUB_CMD_ID_CHANNEL_SWITCH_ACK 0X01 -#define C2H_SUB_CMD_ID_IQK_ACK 0X01 -#define C2H_SUB_CMD_ID_POWER_TRACKING_ACK 0X01 -#define C2H_SUB_CMD_ID_PSD_ACK 0X01 -#define C2H_SUB_CMD_ID_PSD_DATA 0X04 -#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05 -#define C2H_SUB_CMD_ID_IQK_DATA 0X06 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A -#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B -#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C -#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E -#define C2H_SUB_CMD_ID_CCX_RPT 0X0F -#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10 -#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11 -#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C -#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D -#define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER +#define C2H_SUB_CMD_ID_C2H_DBG 0X00 +#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02 +#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03 +#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01 +#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01 +#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01 +#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01 +#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01 +#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01 +#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01 +#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01 +#define C2H_SUB_CMD_ID_IQK_ACK 0X01 +#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01 +#define C2H_SUB_CMD_ID_PSD_ACK 0X01 +#define C2H_SUB_CMD_ID_PSD_DATA 0X04 +#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05 +#define C2H_SUB_CMD_ID_IQK_DATA 0X06 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A +#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B +#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C +#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E +#define C2H_SUB_CMD_ID_CCX_RPT 0X0F +#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10 +#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11 +#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C +#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D +#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF +#define C2H_SUB_CMD_ID_FW_SNDING_ACK 0X01 +#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F +#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20 +#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21 +#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM #define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX #define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE -#define H2C_SUB_CMD_ID_UPDATE_PACKET_ACK SUB_CMD_ID_UPDATE_PACKET +#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT #define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK #define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK -#define H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK SUB_CMD_ID_CHANNEL_SWITCH +#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH #define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK -#define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING +#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK #define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD #define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT -#define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF -#define H2C_CMD_ID_BT_COEX_ACK 0XFF -#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF -#define H2C_CMD_ID_UPDATE_PACKET_ACK 0XFF -#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF -#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF -#define H2C_CMD_ID_CHANNEL_SWITCH_ACK 0XFF -#define H2C_CMD_ID_IQK_ACK 0XFF -#define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF -#define H2C_CMD_ID_PSD_ACK 0XFF -#define H2C_CMD_ID_CCX_RPT 0XFF -#define C2H_HDR_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_HDR_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_HDR_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_HDR_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_HDR_GET_C2H_SUB_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) -#define C2H_HDR_SET_C2H_SUB_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) -#define C2H_HDR_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define C2H_HDR_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define C2H_DBG_GET_DBG_MSG(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define C2H_DBG_SET_DBG_MSG(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define BT_COEX_INFO_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define BT_COEX_INFO_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define SCAN_STATUS_RPT_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) -#define SCAN_STATUS_RPT_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) -#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define H2C_ACK_HDR_GET_H2C_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define H2C_ACK_HDR_SET_H2C_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) -#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) -#define H2C_ACK_HDR_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 16) -#define H2C_ACK_HDR_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 16, __Value) -#define CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0XC, 0, 32) -#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0XC, 0, 32, __Value) -#define CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X10, 0, 32) -#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X10, 0, 32, __Value) -#define BT_COEX_ACK_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0XC, 0, 8) -#define BT_COEX_ACK_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0XC, 0, 8, __Value) -#define PSD_DATA_GET_SEGMENT_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 7) -#define PSD_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 7, __Value) -#define PSD_DATA_GET_END_SEGMENT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 7, 1) -#define PSD_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 7, 1, __Value) -#define PSD_DATA_GET_SEGMENT_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define PSD_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define PSD_DATA_GET_TOTAL_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) -#define PSD_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) -#define PSD_DATA_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 0, 16) -#define PSD_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value) -#define PSD_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8) -#define PSD_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value) -#define EFUSE_DATA_GET_SEGMENT_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 7) -#define EFUSE_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 7, __Value) -#define EFUSE_DATA_GET_END_SEGMENT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 7, 1) -#define EFUSE_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 7, 1, __Value) -#define EFUSE_DATA_GET_SEGMENT_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define EFUSE_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define EFUSE_DATA_GET_TOTAL_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) -#define EFUSE_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) -#define EFUSE_DATA_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 0, 16) -#define EFUSE_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value) -#define EFUSE_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8) -#define EFUSE_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value) -#define IQK_DATA_GET_SEGMENT_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 7) -#define IQK_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 7, __Value) -#define IQK_DATA_GET_END_SEGMENT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 7, 1) -#define IQK_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 7, 1, __Value) -#define IQK_DATA_GET_SEGMENT_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define IQK_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define IQK_DATA_GET_TOTAL_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) -#define IQK_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) -#define IQK_DATA_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 0, 16) -#define IQK_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value) -#define IQK_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8) -#define IQK_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value) -#define CCX_RPT_GET_CCX_RPT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X4, 0, 129) -#define CCX_RPT_SET_CCX_RPT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X4, 0, 129, __Value) +#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG +#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING +#define H2C_SUB_CMD_ID_FW_FWCTRL_RPT SUB_CMD_ID_FW_FWCTRL_RPT +#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK +#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK +#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF +#define H2C_CMD_ID_BT_COEX_ACK 0XFF +#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF +#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF +#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF +#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF +#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF +#define H2C_CMD_ID_IQK_ACK 0XFF +#define H2C_CMD_ID_PWR_TRK_ACK 0XFF +#define H2C_CMD_ID_PSD_ACK 0XFF +#define H2C_CMD_ID_CCX_RPT 0XFF +#define H2C_CMD_ID_FW_DBG_MSG 0XFF +#define H2C_CMD_ID_FW_SNDING_ACK 0XFF +#define H2C_CMD_ID_FW_FWCTRL_RPT 0XFF +#define H2C_CMD_ID_H2C_LOOPBACK_ACK 0XFF +#define H2C_CMD_ID_FWCMD_LOOPBACK_ACK 0XFF +#define C2H_HDR_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_HDR_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_HDR_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_HDR_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define C2H_HDR_SET_C2H_SUB_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define C2H_HDR_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define C2H_HDR_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define C2H_DBG_GET_DBG_MSG(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define C2H_DBG_SET_DBG_MSG(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define BT_COEX_INFO_GET_DATA_START(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define BT_COEX_INFO_SET_DATA_START(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define SCAN_STATUS_RPT_GET_H2C_SEQ(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16) +#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value) +#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define H2C_ACK_HDR_SET_H2C_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16) +#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value) +#define H2C_ACK_HDR_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 16) +#define H2C_ACK_HDR_SET_H2C_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 16, value) +#define CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 32) +#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 32, value) +#define CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 0, 32) +#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 0, 32, value) +#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 8) +#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 8, value) +#define PSD_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7) +#define PSD_DATA_SET_SEGMENT_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value) +#define PSD_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1) +#define PSD_DATA_SET_END_SEGMENT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value) +#define PSD_DATA_GET_SEGMENT_SIZE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define PSD_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define PSD_DATA_GET_TOTAL_SIZE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16) +#define PSD_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value) +#define PSD_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16) +#define PSD_DATA_SET_H2C_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value) +#define PSD_DATA_GET_DATA_START(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8) +#define PSD_DATA_SET_DATA_START(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value) +#define EFUSE_DATA_GET_SEGMENT_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7) +#define EFUSE_DATA_SET_SEGMENT_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value) +#define EFUSE_DATA_GET_END_SEGMENT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1) +#define EFUSE_DATA_SET_END_SEGMENT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value) +#define EFUSE_DATA_GET_SEGMENT_SIZE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define EFUSE_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define EFUSE_DATA_GET_TOTAL_SIZE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16) +#define EFUSE_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value) +#define EFUSE_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16) +#define EFUSE_DATA_SET_H2C_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value) +#define EFUSE_DATA_GET_DATA_START(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8) +#define EFUSE_DATA_SET_DATA_START(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value) +#define IQK_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7) +#define IQK_DATA_SET_SEGMENT_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value) +#define IQK_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1) +#define IQK_DATA_SET_END_SEGMENT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value) +#define IQK_DATA_GET_SEGMENT_SIZE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define IQK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define IQK_DATA_GET_TOTAL_SIZE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16) +#define IQK_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value) +#define IQK_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16) +#define IQK_DATA_SET_H2C_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value) +#define IQK_DATA_GET_DATA_START(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8) +#define IQK_DATA_SET_DATA_START(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value) +#define CCX_RPT_GET_POLLUTED(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 0, 1) +#define CCX_RPT_SET_POLLUTED(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 0, 1, value) +#define CCX_RPT_GET_RPT_SEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 5, 3) +#define CCX_RPT_SET_RPT_SEL(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 5, 3, value) +#define CCX_RPT_GET_QSEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 8, 5) +#define CCX_RPT_SET_QSEL(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 8, 5, value) +#define CCX_RPT_GET_MISSED_RPT_NUM(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 13, 3) +#define CCX_RPT_SET_MISSED_RPT_NUM(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 13, 3, value) +#define CCX_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 16, 7) +#define CCX_RPT_SET_MACID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 16, 7, value) +#define CCX_RPT_GET_INITIAL_DATA_RATE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 24, 7) +#define CCX_RPT_SET_INITIAL_DATA_RATE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 24, 7, value) +#define CCX_RPT_GET_INITIAL_SGI(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 31, 1) +#define CCX_RPT_SET_INITIAL_SGI(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 31, 1, value) +#define CCX_RPT_GET_QUEUE_TIME(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16) +#define CCX_RPT_SET_QUEUE_TIME(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value) +#define CCX_RPT_GET_SW_DEFINE_BYTE0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8) +#define CCX_RPT_SET_SW_DEFINE_BYTE0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value) +#define CCX_RPT_GET_RTS_RETRY_COUNT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 4) +#define CCX_RPT_SET_RTS_RETRY_COUNT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 4, value) +#define CCX_RPT_GET_BMC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 29, 1) +#define CCX_RPT_SET_BMC(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 29, 1, value) +#define CCX_RPT_GET_TX_STATE(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 30, 2) +#define CCX_RPT_SET_TX_STATE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 30, 2, value) +#define CCX_RPT_GET_DATA_RETRY_COUNT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 6) +#define CCX_RPT_SET_DATA_RETRY_COUNT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 6, value) +#define CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 8, 7) +#define CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 8, 7, value) +#define CCX_RPT_GET_FINAL_SGI(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 15, 1) +#define CCX_RPT_SET_FINAL_SGI(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 15, 1, value) +#define CCX_RPT_GET_RF_CH_NUM(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 16, 10) +#define CCX_RPT_SET_RF_CH_NUM(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 16, 10, value) +#define CCX_RPT_GET_SC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 26, 4) +#define CCX_RPT_SET_SC(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 26, 4, value) +#define CCX_RPT_GET_BW(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 30, 2) +#define CCX_RPT_SET_BW(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 30, 2, value) +#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define FW_DBG_MSG_GET_C2H_SUB_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define FW_DBG_MSG_GET_FULL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 1) +#define FW_DBG_MSG_SET_FULL(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 1, value) +#define FW_DBG_MSG_GET_OWN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 31, 1) +#define FW_DBG_MSG_SET_OWN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 31, 1, value) +#define FW_FWCTRL_RPT_GET_EVT_TYPE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define FW_FWCTRL_RPT_SET_EVT_TYPE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define FW_FWCTRL_RPT_GET_LENGTH(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define FW_FWCTRL_RPT_SET_LENGTH(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define FW_FWCTRL_RPT_GET_SEQ_NUM(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define FW_FWCTRL_RPT_SET_SEQ_NUM(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define FW_FWCTRL_RPT_GET_IS_ACK(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 1) +#define FW_FWCTRL_RPT_SET_IS_ACK(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 1, value) +#define FW_FWCTRL_RPT_GET_MORE_CONTENT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 25, 1) +#define FW_FWCTRL_RPT_SET_MORE_CONTENT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 25, 1, value) +#define FW_FWCTRL_RPT_GET_CONTENT_IDX(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 26, 6) +#define FW_FWCTRL_RPT_SET_CONTENT_IDX(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 26, 6, value) +#define FW_FWCTRL_RPT_GET_CLASS_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define FW_FWCTRL_RPT_SET_CLASS_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define FW_FWCTRL_RPT_GET_CONTENT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16) +#define FW_FWCTRL_RPT_SET_CONTENT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 8, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 8, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 8, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 8, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value) #endif diff --git a/hal/halmac/halmac_fw_offload_h2c_ap.h b/hal/halmac/halmac_fw_offload_h2c_ap.h index e7caaab..9ef85ce 100644 --- a/hal/halmac/halmac_fw_offload_h2c_ap.h +++ b/hal/halmac/halmac_fw_offload_h2c_ap.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,421 +15,975 @@ #ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_ #define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_ -#define CMD_ID_FW_OFFLOAD_H2C 0XFF -#define CMD_ID_CHANNEL_SWITCH 0XFF -#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF -#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF -#define CMD_ID_CFG_PARAMETER 0XFF -#define CMD_ID_UPDATE_DATAPACK 0XFF -#define CMD_ID_RUN_DATAPACK 0XFF -#define CMD_ID_DOWNLOAD_FLASH 0XFF -#define CMD_ID_UPDATE_PACKET 0XFF -#define CMD_ID_GENERAL_INFO 0XFF -#define CMD_ID_IQK 0XFF -#define CMD_ID_POWER_TRACKING 0XFF -#define CMD_ID_PSD 0XFF -#define CMD_ID_P2PPS 0XFF -#define CMD_ID_BT_COEX 0XFF -#define CMD_ID_NAN_CTRL 0XFF -#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF -#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF -#define CATEGORY_H2C_CMD_HEADER 0X00 -#define CATEGORY_FW_OFFLOAD_H2C 0X01 -#define CATEGORY_CHANNEL_SWITCH 0X01 -#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01 -#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01 -#define CATEGORY_CFG_PARAMETER 0X01 -#define CATEGORY_UPDATE_DATAPACK 0X01 -#define CATEGORY_RUN_DATAPACK 0X01 -#define CATEGORY_DOWNLOAD_FLASH 0X01 -#define CATEGORY_UPDATE_PACKET 0X01 -#define CATEGORY_GENERAL_INFO 0X01 -#define CATEGORY_IQK 0X01 -#define CATEGORY_POWER_TRACKING 0X01 -#define CATEGORY_PSD 0X01 -#define CATEGORY_P2PPS 0X01 -#define CATEGORY_BT_COEX 0X01 -#define CATEGORY_NAN_CTRL 0X01 -#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01 -#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01 -#define SUB_CMD_ID_CHANNEL_SWITCH 0X02 -#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03 -#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05 -#define SUB_CMD_ID_CFG_PARAMETER 0X08 -#define SUB_CMD_ID_UPDATE_DATAPACK 0X09 -#define SUB_CMD_ID_RUN_DATAPACK 0X0A -#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B -#define SUB_CMD_ID_UPDATE_PACKET 0X0C -#define SUB_CMD_ID_GENERAL_INFO 0X0D -#define SUB_CMD_ID_IQK 0X0E -#define SUB_CMD_ID_POWER_TRACKING 0X0F -#define SUB_CMD_ID_PSD 0X10 -#define SUB_CMD_ID_P2PPS 0X24 -#define SUB_CMD_ID_BT_COEX 0X60 -#define SUB_CMD_ID_NAN_CTRL 0XB2 -#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4 -#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5 -#define H2C_CMD_HEADER_GET_CATEGORY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 7) -#define H2C_CMD_HEADER_SET_CATEGORY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 7, __Value) -#define H2C_CMD_HEADER_SET_CATEGORY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 7, __Value) -#define H2C_CMD_HEADER_GET_ACK(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 7, 1) -#define H2C_CMD_HEADER_SET_ACK(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 7, 1, __Value) -#define H2C_CMD_HEADER_SET_ACK_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 7, 1, __Value) -#define H2C_CMD_HEADER_GET_TOTAL_LEN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 16) -#define H2C_CMD_HEADER_SET_TOTAL_LEN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 16, __Value) -#define H2C_CMD_HEADER_SET_TOTAL_LEN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 16, __Value) -#define H2C_CMD_HEADER_GET_SEQ_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 16) -#define H2C_CMD_HEADER_SET_SEQ_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 16, __Value) -#define H2C_CMD_HEADER_SET_SEQ_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 16, __Value) -#define FW_OFFLOAD_H2C_GET_CATEGORY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 7) -#define FW_OFFLOAD_H2C_SET_CATEGORY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 7, __Value) -#define FW_OFFLOAD_H2C_SET_CATEGORY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 7, __Value) -#define FW_OFFLOAD_H2C_GET_ACK(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 7, 1) -#define FW_OFFLOAD_H2C_SET_ACK(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 7, 1, __Value) -#define FW_OFFLOAD_H2C_SET_ACK_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 7, 1, __Value) -#define FW_OFFLOAD_H2C_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define FW_OFFLOAD_H2C_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define FW_OFFLOAD_H2C_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 16) -#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 16, __Value) -#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 16, __Value) -#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 16) -#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 16, __Value) -#define FW_OFFLOAD_H2C_SET_TOTAL_LEN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 16, __Value) -#define FW_OFFLOAD_H2C_GET_SEQ_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 16) -#define FW_OFFLOAD_H2C_SET_SEQ_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 16, __Value) -#define FW_OFFLOAD_H2C_SET_SEQ_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 16, __Value) -#define CHANNEL_SWITCH_GET_SWITCH_START(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) -#define CHANNEL_SWITCH_SET_SWITCH_START(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) -#define CHANNEL_SWITCH_SET_SWITCH_START_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) -#define CHANNEL_SWITCH_GET_DEST_CH_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) -#define CHANNEL_SWITCH_SET_DEST_CH_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) -#define CHANNEL_SWITCH_SET_DEST_CH_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) -#define CHANNEL_SWITCH_GET_ABSOLUTE_TIME(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 2, 1) -#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 2, 1, __Value) -#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 2, 1, __Value) -#define CHANNEL_SWITCH_GET_PERIODIC_OPTION(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 3, 2) -#define CHANNEL_SWITCH_SET_PERIODIC_OPTION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 3, 2, __Value) -#define CHANNEL_SWITCH_SET_PERIODIC_OPTION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 3, 2, __Value) -#define CHANNEL_SWITCH_GET_CHANNEL_INFO_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) -#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) -#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) -#define CHANNEL_SWITCH_GET_CHANNEL_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) -#define CHANNEL_SWITCH_SET_CHANNEL_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) -#define CHANNEL_SWITCH_SET_CHANNEL_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) -#define CHANNEL_SWITCH_GET_PRI_CH_IDX(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 4) -#define CHANNEL_SWITCH_SET_PRI_CH_IDX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 4, __Value) -#define CHANNEL_SWITCH_SET_PRI_CH_IDX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 4, __Value) -#define CHANNEL_SWITCH_GET_DEST_BW(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 28, 4) -#define CHANNEL_SWITCH_SET_DEST_BW(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 28, 4, __Value) -#define CHANNEL_SWITCH_SET_DEST_BW_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 28, 4, __Value) -#define CHANNEL_SWITCH_GET_DEST_CH(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) -#define CHANNEL_SWITCH_SET_DEST_CH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define CHANNEL_SWITCH_SET_DEST_CH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define CHANNEL_SWITCH_GET_NORMAL_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 8, 8) -#define CHANNEL_SWITCH_SET_NORMAL_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 8, 8, __Value) -#define CHANNEL_SWITCH_SET_NORMAL_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 8, 8, __Value) -#define CHANNEL_SWITCH_GET_SLOW_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 8) -#define CHANNEL_SWITCH_SET_SLOW_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 8, __Value) -#define CHANNEL_SWITCH_SET_SLOW_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 8, __Value) -#define CHANNEL_SWITCH_GET_NORMAL_CYCLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 24, 8) -#define CHANNEL_SWITCH_SET_NORMAL_CYCLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 24, 8, __Value) -#define CHANNEL_SWITCH_SET_NORMAL_CYCLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 24, 8, __Value) -#define CHANNEL_SWITCH_GET_TSF_HIGH(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) -#define CHANNEL_SWITCH_SET_TSF_HIGH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) -#define CHANNEL_SWITCH_SET_TSF_HIGH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) -#define CHANNEL_SWITCH_GET_TSF_LOW(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 32) -#define CHANNEL_SWITCH_SET_TSF_LOW(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 32, __Value) -#define CHANNEL_SWITCH_SET_TSF_LOW_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 32, __Value) -#define CHANNEL_SWITCH_GET_CHANNEL_INFO_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 16) -#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 16, __Value) -#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 16, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) -#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 4) -#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 4, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 4, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 12, 4) -#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 12, 4, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 12, 4, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 32, __Value) -#define CFG_PARAMETER_GET_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) -#define CFG_PARAMETER_SET_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) -#define CFG_PARAMETER_SET_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) -#define CFG_PARAMETER_GET_INIT_CASE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 1) -#define CFG_PARAMETER_SET_INIT_CASE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 1, __Value) -#define CFG_PARAMETER_SET_INIT_CASE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 1, __Value) -#define CFG_PARAMETER_GET_PHY_PARAMETER_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) -#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) -#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) -#define UPDATE_DATAPACK_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) -#define UPDATE_DATAPACK_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) -#define UPDATE_DATAPACK_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) -#define UPDATE_DATAPACK_GET_DATAPACK_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) -#define UPDATE_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) -#define UPDATE_DATAPACK_SET_DATAPACK_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) -#define UPDATE_DATAPACK_GET_DATAPACK_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) -#define UPDATE_DATAPACK_SET_DATAPACK_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) -#define UPDATE_DATAPACK_SET_DATAPACK_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) -#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) -#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define UPDATE_DATAPACK_GET_END_SEGMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 8, 1) -#define UPDATE_DATAPACK_SET_END_SEGMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 8, 1, __Value) -#define UPDATE_DATAPACK_SET_END_SEGMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 8, 1, __Value) -#define RUN_DATAPACK_GET_DATAPACK_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) -#define RUN_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) -#define RUN_DATAPACK_SET_DATAPACK_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) -#define DOWNLOAD_FLASH_GET_SPI_CMD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) -#define DOWNLOAD_FLASH_SET_SPI_CMD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) -#define DOWNLOAD_FLASH_SET_SPI_CMD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) -#define DOWNLOAD_FLASH_GET_LOCATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 16) -#define DOWNLOAD_FLASH_SET_LOCATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 16, __Value) -#define DOWNLOAD_FLASH_SET_LOCATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 16, __Value) -#define DOWNLOAD_FLASH_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 32) -#define DOWNLOAD_FLASH_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 32, __Value) -#define DOWNLOAD_FLASH_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 32, __Value) -#define DOWNLOAD_FLASH_GET_START_ADDR(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) -#define DOWNLOAD_FLASH_SET_START_ADDR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) -#define DOWNLOAD_FLASH_SET_START_ADDR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) -#define UPDATE_PACKET_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) -#define UPDATE_PACKET_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) -#define UPDATE_PACKET_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) -#define UPDATE_PACKET_GET_PACKET_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) -#define UPDATE_PACKET_SET_PACKET_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) -#define UPDATE_PACKET_SET_PACKET_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) -#define UPDATE_PACKET_GET_PACKET_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) -#define UPDATE_PACKET_SET_PACKET_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) -#define UPDATE_PACKET_SET_PACKET_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) -#define GENERAL_INFO_GET_REF_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) -#define GENERAL_INFO_SET_REF_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) -#define GENERAL_INFO_SET_REF_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) -#define GENERAL_INFO_GET_RF_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 9) -#define GENERAL_INFO_SET_RF_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 9, __Value) -#define GENERAL_INFO_SET_RF_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 9, __Value) -#define GENERAL_INFO_GET_FW_TX_BOUNDARY(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) -#define GENERAL_INFO_SET_FW_TX_BOUNDARY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) -#define GENERAL_INFO_SET_FW_TX_BOUNDARY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) -#define IQK_GET_CLEAR(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) -#define IQK_SET_CLEAR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) -#define IQK_SET_CLEAR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) -#define IQK_GET_SEGMENT_IQK(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) -#define IQK_SET_SEGMENT_IQK(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) -#define IQK_SET_SEGMENT_IQK_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) -#define POWER_TRACKING_SET_ENABLE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) -#define POWER_TRACKING_SET_ENABLE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) -#define POWER_TRACKING_SET_ENABLE_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) -#define POWER_TRACKING_SET_ENABLE_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 2, 1) -#define POWER_TRACKING_SET_ENABLE_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 2, 1, __Value) -#define POWER_TRACKING_SET_ENABLE_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 2, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 3, 1) -#define POWER_TRACKING_SET_ENABLE_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 3, 1, __Value) -#define POWER_TRACKING_SET_ENABLE_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 3, 1, __Value) -#define POWER_TRACKING_GET_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 4, 3) -#define POWER_TRACKING_SET_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 4, 3, __Value) -#define POWER_TRACKING_SET_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 4, 3, __Value) -#define POWER_TRACKING_GET_BBSWING_INDEX(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) -#define POWER_TRACKING_SET_BBSWING_INDEX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) -#define POWER_TRACKING_SET_BBSWING_INDEX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define POWER_TRACKING_SET_TX_PWR_INDEX_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 8, 8, __Value) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 8, __Value) -#define POWER_TRACKING_SET_TSSI_VALUE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 8, __Value) -#define POWER_TRACKING_SET_TX_PWR_INDEX_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 8, 8, __Value) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 16, 8, __Value) -#define POWER_TRACKING_SET_TSSI_VALUE_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 16, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 8, __Value) -#define POWER_TRACKING_SET_TX_PWR_INDEX_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 8, 8, __Value) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 16, 8, __Value) -#define POWER_TRACKING_SET_TSSI_VALUE_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 16, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 8, __Value) -#define POWER_TRACKING_SET_TX_PWR_INDEX_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 8, 8, __Value) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 16, 8, __Value) -#define POWER_TRACKING_SET_TSSI_VALUE_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 16, 8, __Value) -#define PSD_GET_START_PSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) -#define PSD_SET_START_PSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) -#define PSD_SET_START_PSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) -#define PSD_GET_END_PSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 16) -#define PSD_SET_END_PSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 16, __Value) -#define PSD_SET_END_PSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 16, __Value) -#define P2PPS_GET_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) -#define P2PPS_SET_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) -#define P2PPS_SET_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) -#define P2PPS_GET_ROLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) -#define P2PPS_SET_ROLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) -#define P2PPS_SET_ROLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) -#define P2PPS_GET_CTWINDOW_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 2, 1) -#define P2PPS_SET_CTWINDOW_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 2, 1, __Value) -#define P2PPS_SET_CTWINDOW_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 2, 1, __Value) -#define P2PPS_GET_NOA_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 3, 1) -#define P2PPS_SET_NOA_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 3, 1, __Value) -#define P2PPS_SET_NOA_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 3, 1, __Value) -#define P2PPS_GET_NOA_SEL(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 4, 1) -#define P2PPS_SET_NOA_SEL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 4, 1, __Value) -#define P2PPS_SET_NOA_SEL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 4, 1, __Value) -#define P2PPS_GET_ALLSTASLEEP(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 5, 1) -#define P2PPS_SET_ALLSTASLEEP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 5, 1, __Value) -#define P2PPS_SET_ALLSTASLEEP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 5, 1, __Value) -#define P2PPS_GET_DISCOVERY(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 6, 1) -#define P2PPS_SET_DISCOVERY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 6, 1, __Value) -#define P2PPS_SET_DISCOVERY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 6, 1, __Value) -#define P2PPS_GET_P2P_PORT_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) -#define P2PPS_SET_P2P_PORT_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) -#define P2PPS_SET_P2P_PORT_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) -#define P2PPS_GET_P2P_GROUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) -#define P2PPS_SET_P2P_GROUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) -#define P2PPS_SET_P2P_GROUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) -#define P2PPS_GET_P2P_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) -#define P2PPS_SET_P2P_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) -#define P2PPS_SET_P2P_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) -#define P2PPS_GET_CTWINDOW_LENGTH(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) -#define P2PPS_SET_CTWINDOW_LENGTH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define P2PPS_SET_CTWINDOW_LENGTH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define P2PPS_GET_NOA_DURATION_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) -#define P2PPS_SET_NOA_DURATION_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) -#define P2PPS_SET_NOA_DURATION_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) -#define P2PPS_GET_NOA_INTERVAL_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 32) -#define P2PPS_SET_NOA_INTERVAL_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 32, __Value) -#define P2PPS_SET_NOA_INTERVAL_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 32, __Value) -#define P2PPS_GET_NOA_START_TIME_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 32) -#define P2PPS_SET_NOA_START_TIME_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 32, __Value) -#define P2PPS_SET_NOA_START_TIME_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 32, __Value) -#define P2PPS_GET_NOA_COUNT_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 32) -#define P2PPS_SET_NOA_COUNT_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 32, __Value) -#define P2PPS_SET_NOA_COUNT_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 32, __Value) -#define BT_COEX_GET_DATA_START(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) -#define BT_COEX_SET_DATA_START(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) -#define BT_COEX_SET_DATA_START_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CTRL_GET_NAN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 2) -#define NAN_CTRL_SET_NAN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 2, __Value) -#define NAN_CTRL_SET_NAN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 2, __Value) -#define NAN_CTRL_GET_SUPPORT_BAND(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 2) -#define NAN_CTRL_SET_SUPPORT_BAND(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 2, __Value) -#define NAN_CTRL_SET_SUPPORT_BAND_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 2, __Value) -#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 10, 1) -#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 10, 1, __Value) -#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 10, 1, __Value) -#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 11, 1) -#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 11, 1, __Value) -#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 11, 1, __Value) -#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) -#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) -#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) -#define NAN_CTRL_GET_CHANNEL_2G(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) -#define NAN_CTRL_SET_CHANNEL_2G(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) -#define NAN_CTRL_SET_CHANNEL_2G_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) -#define NAN_CTRL_GET_CHANNEL_5G(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) -#define NAN_CTRL_SET_CHANNEL_5G(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define NAN_CTRL_SET_CHANNEL_5G_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 16) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 16) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 8) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 8, 8) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 16) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 16, 16) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 8) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 8, 8) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 16) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 16, 16) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 16) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 16) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 8) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 8, 8) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 16) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 16, 16) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 8) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 8, 8) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 16) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 16, 16) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 16, 16, __Value) +#define CMD_ID_FW_OFFLOAD_H2C 0XFF +#define CMD_ID_CH_SWITCH 0XFF +#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF +#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF +#define CMD_ID_CFG_PARAM 0XFF +#define CMD_ID_UPDATE_DATAPACK 0XFF +#define CMD_ID_RUN_DATAPACK 0XFF +#define CMD_ID_DOWNLOAD_FLASH 0XFF +#define CMD_ID_UPDATE_PKT 0XFF +#define CMD_ID_GENERAL_INFO 0XFF +#define CMD_ID_IQK 0XFF +#define CMD_ID_PWR_TRK 0XFF +#define CMD_ID_PSD 0XFF +#define CMD_ID_P2PPS 0XFF +#define CMD_ID_BT_COEX 0XFF +#define CMD_ID_NAN_CTRL 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF +#define CMD_ID_FW_ACCESS_TEST 0XFF +#define CMD_ID_PHYDM_INFO 0XFF +#define CMD_ID_FW_SNDING 0XFF +#define CMD_ID_H2C_LOOPBACK 0XFF +#define CMD_ID_FWCMD_LOOPBACK 0XFF +#define CMD_ID_FW_FWCTRL 0XFF +#define CATEGORY_H2C_CMD_HEADER 0X00 +#define CATEGORY_FW_OFFLOAD_H2C 0X01 +#define CATEGORY_CH_SWITCH 0X01 +#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01 +#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01 +#define CATEGORY_CFG_PARAM 0X01 +#define CATEGORY_UPDATE_DATAPACK 0X01 +#define CATEGORY_RUN_DATAPACK 0X01 +#define CATEGORY_DOWNLOAD_FLASH 0X01 +#define CATEGORY_UPDATE_PKT 0X01 +#define CATEGORY_GENERAL_INFO 0X01 +#define CATEGORY_IQK 0X01 +#define CATEGORY_PWR_TRK 0X01 +#define CATEGORY_PSD 0X01 +#define CATEGORY_P2PPS 0X01 +#define CATEGORY_BT_COEX 0X01 +#define CATEGORY_NAN_CTRL 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01 +#define CATEGORY_FW_ACCESS_TEST 0X01 +#define CATEGORY_PHYDM_INFO 0X01 +#define CATEGORY_FW_SNDING 0X01 +#define CATEGORY_H2C_LOOPBACK 0X01 +#define CATEGORY_FWCMD_LOOPBACK 0X01 +#define CATEGORY_FW_FWCTRL 0X01 +#define SUB_CMD_ID_CH_SWITCH 0X02 +#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03 +#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05 +#define SUB_CMD_ID_CFG_PARAM 0X08 +#define SUB_CMD_ID_UPDATE_DATAPACK 0X09 +#define SUB_CMD_ID_RUN_DATAPACK 0X0A +#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B +#define SUB_CMD_ID_UPDATE_PKT 0X0C +#define SUB_CMD_ID_GENERAL_INFO 0X0D +#define SUB_CMD_ID_IQK 0X0E +#define SUB_CMD_ID_PWR_TRK 0X0F +#define SUB_CMD_ID_PSD 0X10 +#define SUB_CMD_ID_P2PPS 0X24 +#define SUB_CMD_ID_BT_COEX 0X60 +#define SUB_CMD_ID_NAN_CTRL 0XB2 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5 +#define SUB_CMD_ID_FW_ACCESS_TEST 0X00 +#define SUB_CMD_ID_PHYDM_INFO 0X11 +#define SUB_CMD_ID_FW_SNDING 0X12 +#define SUB_CMD_ID_H2C_LOOPBACK 0X14 +#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15 +#define SUB_CMD_ID_FW_FWCTRL 0X13 +#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7) +#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value) +#define H2C_CMD_HEADER_SET_CATEGORY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 7, value) +#define H2C_CMD_HEADER_GET_ACK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 7, 1) +#define H2C_CMD_HEADER_SET_ACK(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 7, 1, value) +#define H2C_CMD_HEADER_SET_ACK_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 7, 1, value) +#define H2C_CMD_HEADER_GET_TOTAL_LEN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 16) +#define H2C_CMD_HEADER_SET_TOTAL_LEN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 16, value) +#define H2C_CMD_HEADER_SET_TOTAL_LEN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 16, value) +#define H2C_CMD_HEADER_GET_SEQ_NUM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 16) +#define H2C_CMD_HEADER_SET_SEQ_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value) +#define H2C_CMD_HEADER_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value) +#define FW_OFFLOAD_H2C_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7) +#define FW_OFFLOAD_H2C_SET_CATEGORY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value) +#define FW_OFFLOAD_H2C_SET_CATEGORY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 7, value) +#define FW_OFFLOAD_H2C_GET_ACK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 7, 1) +#define FW_OFFLOAD_H2C_SET_ACK(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 7, 1, value) +#define FW_OFFLOAD_H2C_SET_ACK_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 7, 1, value) +#define FW_OFFLOAD_H2C_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define FW_OFFLOAD_H2C_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define FW_OFFLOAD_H2C_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 16) +#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 16, value) +#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 16, value) +#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 16) +#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 16, value) +#define FW_OFFLOAD_H2C_SET_TOTAL_LEN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 16, value) +#define FW_OFFLOAD_H2C_GET_SEQ_NUM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 16) +#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value) +#define FW_OFFLOAD_H2C_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value) +#define CH_SWITCH_GET_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define CH_SWITCH_SET_START(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define CH_SWITCH_SET_START_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define CH_SWITCH_GET_DEST_CH_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1) +#define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value) +#define CH_SWITCH_SET_DEST_CH_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value) +#define CH_SWITCH_GET_ABSOLUTE_TIME(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1) +#define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value) +#define CH_SWITCH_SET_ABSOLUTE_TIME_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value) +#define CH_SWITCH_GET_PERIODIC_OPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 2) +#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 2, value) +#define CH_SWITCH_SET_PERIODIC_OPT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 2, value) +#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define CH_SWITCH_SET_INFO_LOC_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define CH_SWITCH_GET_CH_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define CH_SWITCH_SET_CH_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define CH_SWITCH_GET_PRI_CH_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4) +#define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value) +#define CH_SWITCH_SET_PRI_CH_IDX_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value) +#define CH_SWITCH_GET_DEST_BW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4) +#define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value) +#define CH_SWITCH_SET_DEST_BW_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value) +#define CH_SWITCH_GET_DEST_CH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8) +#define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define CH_SWITCH_SET_DEST_CH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define CH_SWITCH_GET_NORMAL_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 6) +#define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 6, value) +#define CH_SWITCH_SET_NORMAL_PERIOD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 6, value) +#define CH_SWITCH_GET_NORMAL_PERIOD_SEL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 14, 2) +#define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 14, 2, value) +#define CH_SWITCH_SET_NORMAL_PERIOD_SEL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 14, 2, value) +#define CH_SWITCH_GET_SLOW_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 6) +#define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 6, value) +#define CH_SWITCH_SET_SLOW_PERIOD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 6, value) +#define CH_SWITCH_GET_SLOW_PERIOD_SEL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 22, 2) +#define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 22, 2, value) +#define CH_SWITCH_SET_SLOW_PERIOD_SEL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 22, 2, value) +#define CH_SWITCH_GET_NORMAL_CYCLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 24, 8) +#define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 24, 8, value) +#define CH_SWITCH_SET_NORMAL_CYCLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 24, 8, value) +#define CH_SWITCH_GET_TSF_HIGH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32) +#define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value) +#define CH_SWITCH_SET_TSF_HIGH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value) +#define CH_SWITCH_GET_TSF_LOW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32) +#define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value) +#define CH_SWITCH_SET_TSF_LOW_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value) +#define CH_SWITCH_GET_INFO_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 0, 16) +#define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 16, value) +#define CH_SWITCH_SET_INFO_SIZE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 16, value) +#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 8, 4) +#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 4, value) +#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 4, value) +#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 12, 4) +#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 12, 4, value) +#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 12, 4, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X18, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 32, value) +#define CFG_PARAM_GET_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16) +#define CFG_PARAM_SET_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value) +#define CFG_PARAM_SET_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value) +#define CFG_PARAM_GET_INIT_CASE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1) +#define CFG_PARAM_SET_INIT_CASE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value) +#define CFG_PARAM_SET_INIT_CASE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value) +#define CFG_PARAM_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define CFG_PARAM_SET_LOC(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define CFG_PARAM_SET_LOC_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define UPDATE_DATAPACK_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16) +#define UPDATE_DATAPACK_SET_SIZE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value) +#define UPDATE_DATAPACK_SET_SIZE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value) +#define UPDATE_DATAPACK_GET_DATAPACK_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define UPDATE_DATAPACK_SET_DATAPACK_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define UPDATE_DATAPACK_GET_DATAPACK_LOC(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_LOC(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define UPDATE_DATAPACK_SET_DATAPACK_LOC_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define UPDATE_DATAPACK_GET_END_SEGMENT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 1) +#define UPDATE_DATAPACK_SET_END_SEGMENT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 1, value) +#define UPDATE_DATAPACK_SET_END_SEGMENT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 1, value) +#define RUN_DATAPACK_GET_DATAPACK_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define RUN_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define RUN_DATAPACK_SET_DATAPACK_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define DOWNLOAD_FLASH_GET_SPI_CMD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define DOWNLOAD_FLASH_SET_SPI_CMD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define DOWNLOAD_FLASH_SET_SPI_CMD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define DOWNLOAD_FLASH_GET_LOCATION(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 8, 16) +#define DOWNLOAD_FLASH_SET_LOCATION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 16, value) +#define DOWNLOAD_FLASH_SET_LOCATION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 16, value) +#define DOWNLOAD_FLASH_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32) +#define DOWNLOAD_FLASH_SET_SIZE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value) +#define DOWNLOAD_FLASH_SET_SIZE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value) +#define DOWNLOAD_FLASH_GET_START_ADDR(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32) +#define DOWNLOAD_FLASH_SET_START_ADDR(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value) +#define DOWNLOAD_FLASH_SET_START_ADDR_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value) +#define UPDATE_PKT_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16) +#define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value) +#define UPDATE_PKT_SET_SIZE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value) +#define UPDATE_PKT_GET_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define UPDATE_PKT_SET_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define UPDATE_PKT_SET_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define UPDATE_PKT_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define UPDATE_PKT_SET_LOC(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define UPDATE_PKT_SET_LOC_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define GENERAL_INFO_GET_FW_TX_BOUNDARY(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define GENERAL_INFO_SET_FW_TX_BOUNDARY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define IQK_GET_CLEAR(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define IQK_SET_CLEAR(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define IQK_SET_CLEAR_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define IQK_GET_SEGMENT_IQK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1) +#define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value) +#define IQK_SET_SEGMENT_IQK_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value) +#define PWR_TRK_GET_ENABLE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define PWR_TRK_SET_ENABLE_A(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define PWR_TRK_SET_ENABLE_A_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define PWR_TRK_GET_ENABLE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1) +#define PWR_TRK_SET_ENABLE_B(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value) +#define PWR_TRK_SET_ENABLE_B_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value) +#define PWR_TRK_GET_ENABLE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1) +#define PWR_TRK_SET_ENABLE_C(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value) +#define PWR_TRK_SET_ENABLE_C_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value) +#define PWR_TRK_GET_ENABLE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1) +#define PWR_TRK_SET_ENABLE_D(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value) +#define PWR_TRK_SET_ENABLE_D_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value) +#define PWR_TRK_GET_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 4, 3) +#define PWR_TRK_SET_TYPE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 3, value) +#define PWR_TRK_SET_TYPE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 3, value) +#define PWR_TRK_GET_BBSWING_INDEX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define PWR_TRK_SET_BBSWING_INDEX(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define PWR_TRK_SET_BBSWING_INDEX_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_A(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define PWR_TRK_SET_TX_PWR_INDEX_A_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_A(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value) +#define PWR_TRK_SET_OFFSET_VALUE_A_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_A(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 8, value) +#define PWR_TRK_SET_TSSI_VALUE_A_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_B(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value) +#define PWR_TRK_SET_TX_PWR_INDEX_B_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_B(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value) +#define PWR_TRK_SET_OFFSET_VALUE_B_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_B(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 16, 8, value) +#define PWR_TRK_SET_TSSI_VALUE_B_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 16, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_C(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 8, value) +#define PWR_TRK_SET_TX_PWR_INDEX_C_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_C(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 8, 8, value) +#define PWR_TRK_SET_OFFSET_VALUE_C_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_C(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 8, value) +#define PWR_TRK_SET_TSSI_VALUE_C_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_D(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value) +#define PWR_TRK_SET_TX_PWR_INDEX_D_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_D(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value) +#define PWR_TRK_SET_OFFSET_VALUE_D_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_D(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 16, 8, value) +#define PWR_TRK_SET_TSSI_VALUE_D_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 16, 8, value) +#define PSD_GET_START_PSD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16) +#define PSD_SET_START_PSD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value) +#define PSD_SET_START_PSD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value) +#define PSD_GET_END_PSD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 16) +#define PSD_SET_END_PSD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 16, value) +#define PSD_SET_END_PSD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 16, value) +#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define P2PPS_SET_OFFLOAD_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define P2PPS_GET_ROLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1) +#define P2PPS_SET_ROLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value) +#define P2PPS_SET_ROLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value) +#define P2PPS_GET_CTWINDOW_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1) +#define P2PPS_SET_CTWINDOW_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value) +#define P2PPS_SET_CTWINDOW_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value) +#define P2PPS_GET_NOA_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1) +#define P2PPS_SET_NOA_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value) +#define P2PPS_SET_NOA_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value) +#define P2PPS_GET_NOA_SEL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1) +#define P2PPS_SET_NOA_SEL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value) +#define P2PPS_SET_NOA_SEL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value) +#define P2PPS_GET_ALLSTASLEEP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1) +#define P2PPS_SET_ALLSTASLEEP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value) +#define P2PPS_SET_ALLSTASLEEP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value) +#define P2PPS_GET_DISCOVERY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1) +#define P2PPS_SET_DISCOVERY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value) +#define P2PPS_SET_DISCOVERY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value) +#define P2PPS_GET_DISABLE_CLOSERF(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1) +#define P2PPS_SET_DISABLE_CLOSERF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value) +#define P2PPS_SET_DISABLE_CLOSERF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value) +#define P2PPS_GET_P2P_PORT_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define P2PPS_SET_P2P_PORT_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define P2PPS_SET_P2P_PORT_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define P2PPS_GET_P2P_GROUP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define P2PPS_SET_P2P_GROUP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define P2PPS_SET_P2P_GROUP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define P2PPS_GET_P2P_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define P2PPS_SET_P2P_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define P2PPS_SET_P2P_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define P2PPS_GET_CTWINDOW_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8) +#define P2PPS_SET_CTWINDOW_LENGTH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define P2PPS_SET_CTWINDOW_LENGTH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define P2PPS_GET_NOA_DURATION_PARA(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32) +#define P2PPS_SET_NOA_DURATION_PARA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value) +#define P2PPS_SET_NOA_DURATION_PARA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value) +#define P2PPS_GET_NOA_INTERVAL_PARA(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32) +#define P2PPS_SET_NOA_INTERVAL_PARA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value) +#define P2PPS_SET_NOA_INTERVAL_PARA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value) +#define P2PPS_GET_NOA_START_TIME_PARA(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X18, 0, 32) +#define P2PPS_SET_NOA_START_TIME_PARA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 32, value) +#define P2PPS_SET_NOA_START_TIME_PARA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 32, value) +#define P2PPS_GET_NOA_COUNT_PARA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 32) +#define P2PPS_SET_NOA_COUNT_PARA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 32, value) +#define P2PPS_SET_NOA_COUNT_PARA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 32, value) +#define BT_COEX_GET_DATA_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define BT_COEX_SET_DATA_START(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define BT_COEX_SET_DATA_START_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CTRL_GET_NAN_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 2) +#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 2, value) +#define NAN_CTRL_SET_NAN_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 2, value) +#define NAN_CTRL_GET_WARMUP_TIMER_FLAG(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1) +#define NAN_CTRL_SET_WARMUP_TIMER_FLAG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value) +#define NAN_CTRL_SET_WARMUP_TIMER_FLAG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value) +#define NAN_CTRL_GET_SUPPORT_BAND(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 2) +#define NAN_CTRL_SET_SUPPORT_BAND(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 2, value) +#define NAN_CTRL_SET_SUPPORT_BAND_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 2, value) +#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 10, 1) +#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 10, 1, value) +#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 10, 1, value) +#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 11, 1) +#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 11, 1, value) +#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 11, 1, value) +#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define NAN_CTRL_GET_CHANNEL_2G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define NAN_CTRL_SET_CHANNEL_2G(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define NAN_CTRL_SET_CHANNEL_2G_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define NAN_CTRL_GET_CHANNEL_5G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8) +#define NAN_CTRL_SET_CHANNEL_5G(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define NAN_CTRL_SET_CHANNEL_5G_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define NAN_CTRL_GET_MASTERPREFERENCE_VALUE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8) +#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value) +#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value) +#define NAN_CTRL_GET_RANDOMFACTOR_VALUE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 8) +#define NAN_CTRL_SET_RANDOMFACTOR_VALUE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 8, value) +#define NAN_CTRL_SET_RANDOMFACTOR_VALUE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value) +#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_TXFF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1) +#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_RXFF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1) +#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_FWFF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PHYFF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1) +#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1) +#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_CAM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1) +#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1) +#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1) +#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 9, 1) +#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 17, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 17, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 17, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 18, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 18, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 18, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 19, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 19, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 19, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 20, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 20, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 20, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 21, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 21, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE5_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 21, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 22, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 22, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE6_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 22, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 23, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 23, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE7_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 23, 1, value) +#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define PHYDM_INFO_SET_REF_TYPE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define PHYDM_INFO_SET_RF_TYPE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define PHYDM_INFO_SET_CUT_VER_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4) +#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value) +#define PHYDM_INFO_SET_RX_ANT_STATUS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value) +#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4) +#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value) +#define PHYDM_INFO_SET_TX_ANT_STATUS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value) +#define FW_SNDING_GET_SU0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define FW_SNDING_SET_SU0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define FW_SNDING_SET_SU0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define FW_SNDING_GET_SU1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1) +#define FW_SNDING_SET_SU1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value) +#define FW_SNDING_SET_SU1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value) +#define FW_SNDING_GET_MU(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1) +#define FW_SNDING_SET_MU(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value) +#define FW_SNDING_SET_MU_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value) +#define FW_SNDING_GET_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define FW_SNDING_SET_PERIOD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define FW_SNDING_SET_NDPA0_HEAD_PG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define FW_SNDING_SET_NDPA1_HEAD_PG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0XC, 0, 8) +#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 0, 8, value) +#define FW_SNDING_SET_MU_NDPA_HEAD_PG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 0, 8, value) +#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 8, 8) +#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 8, 8, value) +#define FW_SNDING_SET_RPT0_HEAD_PG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 8, 8, value) +#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 16, 8) +#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 16, 8, value) +#define FW_SNDING_SET_RPT1_HEAD_PG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 16, 8, value) +#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 24, 8) +#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 24, 8, value) +#define FW_SNDING_SET_RPT2_HEAD_PG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 24, 8, value) +#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define FW_FWCTRL_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1) +#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value) +#define FW_FWCTRL_SET_MORE_CONTENT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value) +#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 9, 7) +#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 7, value) +#define FW_FWCTRL_SET_CONTENT_IDX_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 7, value) +#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define FW_FWCTRL_SET_CLASS_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define FW_FWCTRL_GET_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define FW_FWCTRL_SET_LENGTH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define FW_FWCTRL_GET_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32) +#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value) +#define FW_FWCTRL_SET_CONTENT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value) #endif diff --git a/hal/halmac/halmac_fw_offload_h2c_nic.h b/hal/halmac/halmac_fw_offload_h2c_nic.h index a885c85..525be7e 100644 --- a/hal/halmac/halmac_fw_offload_h2c_nic.h +++ b/hal/halmac/halmac_fw_offload_h2c_nic.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,300 +15,680 @@ #ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_ #define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_ -#define CMD_ID_FW_OFFLOAD_H2C 0XFF -#define CMD_ID_CHANNEL_SWITCH 0XFF -#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF -#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF -#define CMD_ID_CFG_PARAMETER 0XFF -#define CMD_ID_UPDATE_DATAPACK 0XFF -#define CMD_ID_RUN_DATAPACK 0XFF -#define CMD_ID_DOWNLOAD_FLASH 0XFF -#define CMD_ID_UPDATE_PACKET 0XFF -#define CMD_ID_GENERAL_INFO 0XFF -#define CMD_ID_IQK 0XFF -#define CMD_ID_POWER_TRACKING 0XFF -#define CMD_ID_PSD 0XFF -#define CMD_ID_P2PPS 0XFF -#define CMD_ID_BT_COEX 0XFF -#define CMD_ID_NAN_CTRL 0XFF -#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF -#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF -#define CATEGORY_H2C_CMD_HEADER 0X00 -#define CATEGORY_FW_OFFLOAD_H2C 0X01 -#define CATEGORY_CHANNEL_SWITCH 0X01 -#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01 -#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01 -#define CATEGORY_CFG_PARAMETER 0X01 -#define CATEGORY_UPDATE_DATAPACK 0X01 -#define CATEGORY_RUN_DATAPACK 0X01 -#define CATEGORY_DOWNLOAD_FLASH 0X01 -#define CATEGORY_UPDATE_PACKET 0X01 -#define CATEGORY_GENERAL_INFO 0X01 -#define CATEGORY_IQK 0X01 -#define CATEGORY_POWER_TRACKING 0X01 -#define CATEGORY_PSD 0X01 -#define CATEGORY_P2PPS 0X01 -#define CATEGORY_BT_COEX 0X01 -#define CATEGORY_NAN_CTRL 0X01 -#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01 -#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01 -#define SUB_CMD_ID_CHANNEL_SWITCH 0X02 -#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03 -#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05 -#define SUB_CMD_ID_CFG_PARAMETER 0X08 -#define SUB_CMD_ID_UPDATE_DATAPACK 0X09 -#define SUB_CMD_ID_RUN_DATAPACK 0X0A -#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B -#define SUB_CMD_ID_UPDATE_PACKET 0X0C -#define SUB_CMD_ID_GENERAL_INFO 0X0D -#define SUB_CMD_ID_IQK 0X0E -#define SUB_CMD_ID_POWER_TRACKING 0X0F -#define SUB_CMD_ID_PSD 0X10 -#define SUB_CMD_ID_P2PPS 0X24 -#define SUB_CMD_ID_BT_COEX 0X60 -#define SUB_CMD_ID_NAN_CTRL 0XB2 -#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4 -#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5 -#define H2C_CMD_HEADER_GET_CATEGORY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 7) -#define H2C_CMD_HEADER_SET_CATEGORY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 7, __Value) -#define H2C_CMD_HEADER_GET_ACK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 7, 1) -#define H2C_CMD_HEADER_SET_ACK(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 7, 1, __Value) -#define H2C_CMD_HEADER_GET_TOTAL_LEN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 16) -#define H2C_CMD_HEADER_SET_TOTAL_LEN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 16, __Value) -#define H2C_CMD_HEADER_GET_SEQ_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 16) -#define H2C_CMD_HEADER_SET_SEQ_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 16, __Value) -#define FW_OFFLOAD_H2C_GET_CATEGORY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 7) -#define FW_OFFLOAD_H2C_SET_CATEGORY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 7, __Value) -#define FW_OFFLOAD_H2C_GET_ACK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 7, 1) -#define FW_OFFLOAD_H2C_SET_ACK(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 7, 1, __Value) -#define FW_OFFLOAD_H2C_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define FW_OFFLOAD_H2C_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 16) -#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 16, __Value) -#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 16) -#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 16, __Value) -#define FW_OFFLOAD_H2C_GET_SEQ_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 16) -#define FW_OFFLOAD_H2C_SET_SEQ_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 16, __Value) -#define CHANNEL_SWITCH_GET_SWITCH_START(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) -#define CHANNEL_SWITCH_SET_SWITCH_START(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) -#define CHANNEL_SWITCH_GET_DEST_CH_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) -#define CHANNEL_SWITCH_SET_DEST_CH_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) -#define CHANNEL_SWITCH_GET_ABSOLUTE_TIME(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 2, 1) -#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 2, 1, __Value) -#define CHANNEL_SWITCH_GET_PERIODIC_OPTION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 3, 2) -#define CHANNEL_SWITCH_SET_PERIODIC_OPTION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 3, 2, __Value) -#define CHANNEL_SWITCH_GET_CHANNEL_INFO_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) -#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) -#define CHANNEL_SWITCH_GET_CHANNEL_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) -#define CHANNEL_SWITCH_SET_CHANNEL_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) -#define CHANNEL_SWITCH_GET_PRI_CH_IDX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 4) -#define CHANNEL_SWITCH_SET_PRI_CH_IDX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 4, __Value) -#define CHANNEL_SWITCH_GET_DEST_BW(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 28, 4) -#define CHANNEL_SWITCH_SET_DEST_BW(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 28, 4, __Value) -#define CHANNEL_SWITCH_GET_DEST_CH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) -#define CHANNEL_SWITCH_SET_DEST_CH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) -#define CHANNEL_SWITCH_GET_NORMAL_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 8, 8) -#define CHANNEL_SWITCH_SET_NORMAL_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 8, 8, __Value) -#define CHANNEL_SWITCH_GET_SLOW_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 8) -#define CHANNEL_SWITCH_SET_SLOW_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 8, __Value) -#define CHANNEL_SWITCH_GET_NORMAL_CYCLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 24, 8) -#define CHANNEL_SWITCH_SET_NORMAL_CYCLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 24, 8, __Value) -#define CHANNEL_SWITCH_GET_TSF_HIGH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) -#define CHANNEL_SWITCH_SET_TSF_HIGH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) -#define CHANNEL_SWITCH_GET_TSF_LOW(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 32) -#define CHANNEL_SWITCH_SET_TSF_LOW(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 32, __Value) -#define CHANNEL_SWITCH_GET_CHANNEL_INFO_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 16) -#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 16, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) -#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 4) -#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 4, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 12, 4) -#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 12, 4, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 32, __Value) -#define CFG_PARAMETER_GET_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16) -#define CFG_PARAMETER_SET_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) -#define CFG_PARAMETER_GET_INIT_CASE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 1) -#define CFG_PARAMETER_SET_INIT_CASE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 1, __Value) -#define CFG_PARAMETER_GET_PHY_PARAMETER_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) -#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) -#define UPDATE_DATAPACK_GET_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16) -#define UPDATE_DATAPACK_SET_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) -#define UPDATE_DATAPACK_GET_DATAPACK_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) -#define UPDATE_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) -#define UPDATE_DATAPACK_GET_DATAPACK_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) -#define UPDATE_DATAPACK_SET_DATAPACK_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) -#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) -#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) -#define UPDATE_DATAPACK_GET_END_SEGMENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 8, 1) -#define UPDATE_DATAPACK_SET_END_SEGMENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 8, 1, __Value) -#define RUN_DATAPACK_GET_DATAPACK_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) -#define RUN_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) -#define DOWNLOAD_FLASH_GET_SPI_CMD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) -#define DOWNLOAD_FLASH_SET_SPI_CMD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) -#define DOWNLOAD_FLASH_GET_LOCATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 16) -#define DOWNLOAD_FLASH_SET_LOCATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 16, __Value) -#define DOWNLOAD_FLASH_GET_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 32) -#define DOWNLOAD_FLASH_SET_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 32, __Value) -#define DOWNLOAD_FLASH_GET_START_ADDR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) -#define DOWNLOAD_FLASH_SET_START_ADDR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) -#define UPDATE_PACKET_GET_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16) -#define UPDATE_PACKET_SET_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) -#define UPDATE_PACKET_GET_PACKET_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) -#define UPDATE_PACKET_SET_PACKET_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) -#define UPDATE_PACKET_GET_PACKET_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) -#define UPDATE_PACKET_SET_PACKET_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) -#define GENERAL_INFO_GET_REF_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) -#define GENERAL_INFO_SET_REF_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) -#define GENERAL_INFO_GET_RF_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 9) -#define GENERAL_INFO_SET_RF_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 9, __Value) -#define GENERAL_INFO_GET_FW_TX_BOUNDARY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) -#define GENERAL_INFO_SET_FW_TX_BOUNDARY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) -#define IQK_GET_CLEAR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) -#define IQK_SET_CLEAR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) -#define IQK_GET_SEGMENT_IQK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) -#define IQK_SET_SEGMENT_IQK(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) -#define POWER_TRACKING_SET_ENABLE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) -#define POWER_TRACKING_SET_ENABLE_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 2, 1) -#define POWER_TRACKING_SET_ENABLE_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 2, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 3, 1) -#define POWER_TRACKING_SET_ENABLE_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 3, 1, __Value) -#define POWER_TRACKING_GET_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 4, 3) -#define POWER_TRACKING_SET_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 4, 3, __Value) -#define POWER_TRACKING_GET_BBSWING_INDEX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) -#define POWER_TRACKING_SET_BBSWING_INDEX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 16, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 16, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 16, 8, __Value) -#define PSD_GET_START_PSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16) -#define PSD_SET_START_PSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) -#define PSD_GET_END_PSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 16) -#define PSD_SET_END_PSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 16, __Value) -#define P2PPS_GET_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) -#define P2PPS_SET_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) -#define P2PPS_GET_ROLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) -#define P2PPS_SET_ROLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) -#define P2PPS_GET_CTWINDOW_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 2, 1) -#define P2PPS_SET_CTWINDOW_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 2, 1, __Value) -#define P2PPS_GET_NOA_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 3, 1) -#define P2PPS_SET_NOA_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 3, 1, __Value) -#define P2PPS_GET_NOA_SEL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 4, 1) -#define P2PPS_SET_NOA_SEL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 4, 1, __Value) -#define P2PPS_GET_ALLSTASLEEP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 5, 1) -#define P2PPS_SET_ALLSTASLEEP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 5, 1, __Value) -#define P2PPS_GET_DISCOVERY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 6, 1) -#define P2PPS_SET_DISCOVERY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 6, 1, __Value) -#define P2PPS_GET_P2P_PORT_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) -#define P2PPS_SET_P2P_PORT_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) -#define P2PPS_GET_P2P_GROUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) -#define P2PPS_SET_P2P_GROUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) -#define P2PPS_GET_P2P_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) -#define P2PPS_SET_P2P_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) -#define P2PPS_GET_CTWINDOW_LENGTH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) -#define P2PPS_SET_CTWINDOW_LENGTH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) -#define P2PPS_GET_NOA_DURATION_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) -#define P2PPS_SET_NOA_DURATION_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) -#define P2PPS_GET_NOA_INTERVAL_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 32) -#define P2PPS_SET_NOA_INTERVAL_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 32, __Value) -#define P2PPS_GET_NOA_START_TIME_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 32) -#define P2PPS_SET_NOA_START_TIME_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 32, __Value) -#define P2PPS_GET_NOA_COUNT_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 32) -#define P2PPS_SET_NOA_COUNT_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 32, __Value) -#define BT_COEX_GET_DATA_START(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) -#define BT_COEX_SET_DATA_START(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CTRL_GET_NAN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 2) -#define NAN_CTRL_SET_NAN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 2, __Value) -#define NAN_CTRL_GET_SUPPORT_BAND(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 2) -#define NAN_CTRL_SET_SUPPORT_BAND(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 2, __Value) -#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 10, 1) -#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 10, 1, __Value) -#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 11, 1) -#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 11, 1, __Value) -#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) -#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) -#define NAN_CTRL_GET_CHANNEL_2G(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) -#define NAN_CTRL_SET_CHANNEL_2G(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) -#define NAN_CTRL_GET_CHANNEL_5G(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) -#define NAN_CTRL_SET_CHANNEL_5G(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 16) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 16) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 8) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 8, 8) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 16) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 16, 16) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 8) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 8, 8) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 16) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 16, 16) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 16) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 16) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 8) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 8, 8) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 16) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 16, 16) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 8) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 8, 8) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 16) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 16, 16) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 16, 16, __Value) +#define CMD_ID_FW_OFFLOAD_H2C 0XFF +#define CMD_ID_CH_SWITCH 0XFF +#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF +#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF +#define CMD_ID_CFG_PARAM 0XFF +#define CMD_ID_UPDATE_DATAPACK 0XFF +#define CMD_ID_RUN_DATAPACK 0XFF +#define CMD_ID_DOWNLOAD_FLASH 0XFF +#define CMD_ID_UPDATE_PKT 0XFF +#define CMD_ID_GENERAL_INFO 0XFF +#define CMD_ID_IQK 0XFF +#define CMD_ID_PWR_TRK 0XFF +#define CMD_ID_PSD 0XFF +#define CMD_ID_P2PPS 0XFF +#define CMD_ID_BT_COEX 0XFF +#define CMD_ID_NAN_CTRL 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF +#define CMD_ID_FW_ACCESS_TEST 0XFF +#define CMD_ID_PHYDM_INFO 0XFF +#define CMD_ID_FW_SNDING 0XFF +#define CMD_ID_H2C_LOOPBACK 0XFF +#define CMD_ID_FWCMD_LOOPBACK 0XFF +#define CMD_ID_FW_FWCTRL 0XFF +#define CATEGORY_H2C_CMD_HEADER 0X00 +#define CATEGORY_FW_OFFLOAD_H2C 0X01 +#define CATEGORY_CH_SWITCH 0X01 +#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01 +#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01 +#define CATEGORY_CFG_PARAM 0X01 +#define CATEGORY_UPDATE_DATAPACK 0X01 +#define CATEGORY_RUN_DATAPACK 0X01 +#define CATEGORY_DOWNLOAD_FLASH 0X01 +#define CATEGORY_UPDATE_PKT 0X01 +#define CATEGORY_GENERAL_INFO 0X01 +#define CATEGORY_IQK 0X01 +#define CATEGORY_PWR_TRK 0X01 +#define CATEGORY_PSD 0X01 +#define CATEGORY_P2PPS 0X01 +#define CATEGORY_BT_COEX 0X01 +#define CATEGORY_NAN_CTRL 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01 +#define CATEGORY_FW_ACCESS_TEST 0X01 +#define CATEGORY_PHYDM_INFO 0X01 +#define CATEGORY_FW_SNDING 0X01 +#define CATEGORY_H2C_LOOPBACK 0X01 +#define CATEGORY_FWCMD_LOOPBACK 0X01 +#define CATEGORY_FW_FWCTRL 0X01 +#define SUB_CMD_ID_CH_SWITCH 0X02 +#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03 +#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05 +#define SUB_CMD_ID_CFG_PARAM 0X08 +#define SUB_CMD_ID_UPDATE_DATAPACK 0X09 +#define SUB_CMD_ID_RUN_DATAPACK 0X0A +#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B +#define SUB_CMD_ID_UPDATE_PKT 0X0C +#define SUB_CMD_ID_GENERAL_INFO 0X0D +#define SUB_CMD_ID_IQK 0X0E +#define SUB_CMD_ID_PWR_TRK 0X0F +#define SUB_CMD_ID_PSD 0X10 +#define SUB_CMD_ID_P2PPS 0X24 +#define SUB_CMD_ID_BT_COEX 0X60 +#define SUB_CMD_ID_NAN_CTRL 0XB2 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5 +#define SUB_CMD_ID_FW_ACCESS_TEST 0X00 +#define SUB_CMD_ID_PHYDM_INFO 0X11 +#define SUB_CMD_ID_FW_SNDING 0X12 +#define SUB_CMD_ID_FW_FWCTRL 0X13 +#define SUB_CMD_ID_H2C_LOOPBACK 0X14 +#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15 +#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7) +#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 7, value) +#define H2C_CMD_HEADER_GET_ACK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 7, 1) +#define H2C_CMD_HEADER_SET_ACK(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 7, 1, value) +#define H2C_CMD_HEADER_GET_TOTAL_LEN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 16) +#define H2C_CMD_HEADER_SET_TOTAL_LEN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 16, value) +#define H2C_CMD_HEADER_GET_SEQ_NUM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16) +#define H2C_CMD_HEADER_SET_SEQ_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value) +#define FW_OFFLOAD_H2C_GET_CATEGORY(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7) +#define FW_OFFLOAD_H2C_SET_CATEGORY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 7, value) +#define FW_OFFLOAD_H2C_GET_ACK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 7, 1) +#define FW_OFFLOAD_H2C_SET_ACK(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 7, 1, value) +#define FW_OFFLOAD_H2C_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define FW_OFFLOAD_H2C_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 16) +#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 16, value) +#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 16) +#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 16, value) +#define FW_OFFLOAD_H2C_GET_SEQ_NUM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16) +#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value) +#define CH_SWITCH_GET_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define CH_SWITCH_SET_START(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define CH_SWITCH_GET_DEST_CH_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1) +#define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value) +#define CH_SWITCH_GET_ABSOLUTE_TIME(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1) +#define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value) +#define CH_SWITCH_GET_PERIODIC_OPT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 2) +#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 2, value) +#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define CH_SWITCH_GET_CH_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define CH_SWITCH_GET_PRI_CH_IDX(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4) +#define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value) +#define CH_SWITCH_GET_DEST_BW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4) +#define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value) +#define CH_SWITCH_GET_DEST_CH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8) +#define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value) +#define CH_SWITCH_GET_NORMAL_PERIOD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 6) +#define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 6, value) +#define CH_SWITCH_GET_NORMAL_PERIOD_SEL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 14, 2) +#define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 14, 2, value) +#define CH_SWITCH_GET_SLOW_PERIOD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 6) +#define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 6, value) +#define CH_SWITCH_GET_SLOW_PERIOD_SEL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 22, 2) +#define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 22, 2, value) +#define CH_SWITCH_GET_NORMAL_CYCLE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 24, 8) +#define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 24, 8, value) +#define CH_SWITCH_GET_TSF_HIGH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32) +#define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value) +#define CH_SWITCH_GET_TSF_LOW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32) +#define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value) +#define CH_SWITCH_GET_INFO_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 16) +#define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 16, value) +#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 4) +#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 4, value) +#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 12, 4) +#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 12, 4, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 32, value) +#define CFG_PARAM_GET_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16) +#define CFG_PARAM_SET_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value) +#define CFG_PARAM_GET_INIT_CASE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1) +#define CFG_PARAM_SET_INIT_CASE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value) +#define CFG_PARAM_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define CFG_PARAM_SET_LOC(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define UPDATE_DATAPACK_GET_SIZE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16) +#define UPDATE_DATAPACK_SET_SIZE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value) +#define UPDATE_DATAPACK_GET_DATAPACK_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define UPDATE_DATAPACK_GET_DATAPACK_LOC(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_LOC(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value) +#define UPDATE_DATAPACK_GET_END_SEGMENT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 1) +#define UPDATE_DATAPACK_SET_END_SEGMENT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 1, value) +#define RUN_DATAPACK_GET_DATAPACK_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define RUN_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define DOWNLOAD_FLASH_GET_SPI_CMD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define DOWNLOAD_FLASH_SET_SPI_CMD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define DOWNLOAD_FLASH_GET_LOCATION(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 16) +#define DOWNLOAD_FLASH_SET_LOCATION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 16, value) +#define DOWNLOAD_FLASH_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32) +#define DOWNLOAD_FLASH_SET_SIZE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value) +#define DOWNLOAD_FLASH_GET_START_ADDR(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32) +#define DOWNLOAD_FLASH_SET_START_ADDR(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value) +#define UPDATE_PKT_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16) +#define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value) +#define UPDATE_PKT_GET_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define UPDATE_PKT_SET_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define UPDATE_PKT_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define UPDATE_PKT_SET_LOC(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define GENERAL_INFO_GET_FW_TX_BOUNDARY(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define IQK_GET_CLEAR(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define IQK_SET_CLEAR(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define IQK_GET_SEGMENT_IQK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1) +#define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value) +#define PWR_TRK_GET_ENABLE_A(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define PWR_TRK_SET_ENABLE_A(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define PWR_TRK_GET_ENABLE_B(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1) +#define PWR_TRK_SET_ENABLE_B(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value) +#define PWR_TRK_GET_ENABLE_C(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1) +#define PWR_TRK_SET_ENABLE_C(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value) +#define PWR_TRK_GET_ENABLE_D(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1) +#define PWR_TRK_SET_ENABLE_D(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value) +#define PWR_TRK_GET_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 3) +#define PWR_TRK_SET_TYPE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 3, value) +#define PWR_TRK_GET_BBSWING_INDEX(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define PWR_TRK_SET_BBSWING_INDEX(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_A(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_A(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_A(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_A(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_A(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_A(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_B(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_B(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_B(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_B(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_B(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_B(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 16, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_C(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_C(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_C(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_C(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_C(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_C(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_D(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_D(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_D(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_D(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_D(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_D(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 16, 8, value) +#define PSD_GET_START_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16) +#define PSD_SET_START_PSD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value) +#define PSD_GET_END_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 16) +#define PSD_SET_END_PSD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 16, value) +#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define P2PPS_GET_ROLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1) +#define P2PPS_SET_ROLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value) +#define P2PPS_GET_CTWINDOW_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1) +#define P2PPS_SET_CTWINDOW_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value) +#define P2PPS_GET_NOA_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1) +#define P2PPS_SET_NOA_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value) +#define P2PPS_GET_NOA_SEL(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1) +#define P2PPS_SET_NOA_SEL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value) +#define P2PPS_GET_ALLSTASLEEP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1) +#define P2PPS_SET_ALLSTASLEEP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value) +#define P2PPS_GET_DISCOVERY(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1) +#define P2PPS_SET_DISCOVERY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value) +#define P2PPS_GET_DISABLE_CLOSERF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1) +#define P2PPS_SET_DISABLE_CLOSERF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value) +#define P2PPS_GET_P2P_PORT_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define P2PPS_SET_P2P_PORT_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define P2PPS_GET_P2P_GROUP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define P2PPS_SET_P2P_GROUP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define P2PPS_GET_P2P_MACID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define P2PPS_SET_P2P_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define P2PPS_GET_CTWINDOW_LENGTH(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8) +#define P2PPS_SET_CTWINDOW_LENGTH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value) +#define P2PPS_GET_NOA_DURATION_PARA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32) +#define P2PPS_SET_NOA_DURATION_PARA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value) +#define P2PPS_GET_NOA_INTERVAL_PARA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32) +#define P2PPS_SET_NOA_INTERVAL_PARA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value) +#define P2PPS_GET_NOA_START_TIME_PARA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 32) +#define P2PPS_SET_NOA_START_TIME_PARA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 32, value) +#define P2PPS_GET_NOA_COUNT_PARA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 32) +#define P2PPS_SET_NOA_COUNT_PARA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 32, value) +#define BT_COEX_GET_DATA_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define BT_COEX_SET_DATA_START(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CTRL_GET_NAN_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 2) +#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 2, value) +#define NAN_CTRL_GET_WARMUP_TIMER_FLAG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1) +#define NAN_CTRL_SET_WARMUP_TIMER_FLAG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value) +#define NAN_CTRL_GET_SUPPORT_BAND(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 2) +#define NAN_CTRL_SET_SUPPORT_BAND(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 2, value) +#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 10, 1) +#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 10, 1, value) +#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 11, 1) +#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 11, 1, value) +#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define NAN_CTRL_GET_CHANNEL_2G(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define NAN_CTRL_SET_CHANNEL_2G(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define NAN_CTRL_GET_CHANNEL_5G(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8) +#define NAN_CTRL_SET_CHANNEL_5G(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value) +#define NAN_CTRL_GET_MASTERPREFERENCE_VALUE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8) +#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value) +#define NAN_CTRL_GET_RANDOMFACTOR_VALUE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 8) +#define NAN_CTRL_SET_RANDOMFACTOR_VALUE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value) +#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1) +#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1) +#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1) +#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1) +#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1) +#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1) +#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1) +#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 1) +#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 17, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 17, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 18, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 18, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 19, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 19, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 20, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 20, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 21, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 21, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 22, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 22, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 23, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 23, 1, value) +#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4) +#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value) +#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4) +#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value) +#define FW_SNDING_GET_SU0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define FW_SNDING_SET_SU0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define FW_SNDING_GET_SU1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1) +#define FW_SNDING_SET_SU1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value) +#define FW_SNDING_GET_MU(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1) +#define FW_SNDING_SET_MU(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value) +#define FW_SNDING_GET_PERIOD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 0, 8) +#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 0, 8, value) +#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 8, 8) +#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 8, 8, value) +#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 16, 8) +#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 16, 8, value) +#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 24, 8) +#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 24, 8, value) +#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1) +#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value) +#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 7) +#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 7, value) +#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define FW_FWCTRL_GET_LENGTH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define FW_FWCTRL_GET_CONTENT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32) +#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value) #endif diff --git a/hal/halmac/halmac_gpio_cmd.h b/hal/halmac/halmac_gpio_cmd.h index 27e1fb1..803458f 100644 --- a/hal/halmac/halmac_gpio_cmd.h +++ b/hal/halmac/halmac_gpio_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -38,47 +38,47 @@ #define HALMAC_GPIO_NUM 16 /* GPIO type */ -#define HALMAC_GPIO_IN 0 -#define HALMAC_GPIO_OUT 1 -#define HALMAC_GPIO_IN_OUT 2 +#define HALMAC_GPIO_IN 0 +#define HALMAC_GPIO_OUT 1 +#define HALMAC_GPIO_IN_OUT 2 /* Function name */ -#define HALMAC_WL_HWPDN 0 -#define HALMAC_BT_HWPDN 1 -#define HALMAC_BT_GPIO 2 -#define HALMAC_WL_HW_EXTWOL 3 -#define HALMAC_BT_HW_EXTWOL 4 -#define HALMAC_BT_SFLASH 5 -#define HALMAC_WL_SFLASH 6 -#define HALMAC_WL_LED 7 -#define HALMAC_SDIO_INT 8 -#define HALMAC_UART0 9 -#define HALMAC_EEPROM 10 -#define HALMAC_JTAG 11 -#define HALMAC_LTE_COEX_UART 12 -#define HALMAC_3W_LTE_WL_GPIO 13 -#define HALMAC_GPIO2_3_WL_CTRL_EN 14 -#define HALMAC_GPIO13_14_WL_CTRL_EN 15 -#define HALMAC_DBG_GNT_WL_BT 16 -#define HALMAC_BT_3DDLS_A 17 -#define HALMAC_BT_3DDLS_B 18 -#define HALMAC_BT_PTA 19 -#define HALMAC_WL_PTA 20 -#define HALMAC_WL_UART 21 -#define HALMAC_WLMAC_DBG 22 -#define HALMAC_WLPHY_DBG 23 -#define HALMAC_BT_DBG 24 -#define HALMAC_WLPHY_RFE_CTRL2GPIO 25 -#define HALMAC_EXT_XTAL 26 -#define HALMAC_SW_IO 27 +#define HALMAC_WL_HWPDN 0 +#define HALMAC_BT_HWPDN 1 +#define HALMAC_BT_GPIO 2 +#define HALMAC_WL_HW_EXTWOL 3 +#define HALMAC_BT_HW_EXTWOL 4 +#define HALMAC_BT_SFLASH 5 +#define HALMAC_WL_SFLASH 6 +#define HALMAC_WL_LED 7 +#define HALMAC_SDIO_INT 8 +#define HALMAC_UART0 9 +#define HALMAC_EEPROM 10 +#define HALMAC_JTAG 11 +#define HALMAC_LTE_COEX_UART 12 +#define HALMAC_3W_LTE_WL_GPIO 13 +#define HALMAC_GPIO2_3_WL_CTRL_EN 14 +#define HALMAC_GPIO13_14_WL_CTRL_EN 15 +#define HALMAC_DBG_GNT_WL_BT 16 +#define HALMAC_BT_3DDLS_A 17 +#define HALMAC_BT_3DDLS_B 18 +#define HALMAC_BT_PTA 19 +#define HALMAC_WL_PTA 20 +#define HALMAC_WL_UART 21 +#define HALMAC_WLMAC_DBG 22 +#define HALMAC_WLPHY_DBG 23 +#define HALMAC_BT_DBG 24 +#define HALMAC_WLPHY_RFE_CTRL2GPIO 25 +#define HALMAC_EXT_XTAL 26 +#define HALMAC_SW_IO 27 -typedef struct _HALMAC_GPIO_PIMUX_LIST { +struct halmac_gpio_pimux_list { u16 func; u8 id; u8 type; u16 offset; u8 msk; u8 value; -} HALMAC_GPIO_PIMUX_LIST, *PHALMAC_GPIO_PIMUX_LIST; +}; #endif diff --git a/hal/halmac/halmac_h2c_extra_info_ap.h b/hal/halmac/halmac_h2c_extra_info_ap.h index c9510f5..8362987 100644 --- a/hal/halmac/halmac_h2c_extra_info_ap.h +++ b/hal/halmac/halmac_h2c_extra_info_ap.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,70 +15,206 @@ #ifndef _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_ #define _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_ -#define PHY_PARAMETER_INFO_GET_LENGTH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 8) -#define PHY_PARAMETER_INFO_SET_LENGTH(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 0, 8, __Value) -#define PHY_PARAMETER_INFO_SET_LENGTH_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 0, 8, __Value) -#define PHY_PARAMETER_INFO_GET_IO_CMD(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 8, 7) -#define PHY_PARAMETER_INFO_SET_IO_CMD(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 8, 7, __Value) -#define PHY_PARAMETER_INFO_SET_IO_CMD_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 8, 7, __Value) -#define PHY_PARAMETER_INFO_GET_MSK_EN(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 15, 1) -#define PHY_PARAMETER_INFO_SET_MSK_EN(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 15, 1, __Value) -#define PHY_PARAMETER_INFO_SET_MSK_EN_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 15, 1, __Value) -#define PHY_PARAMETER_INFO_GET_LLT_PG_BNDY(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_EFUSE_RSVDPAGE_LOC(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_EFUSE_PATCH_EN(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_RF_ADDR(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_RF_ADDR(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_SET_RF_ADDR_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_IO_ADDR(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 16) -#define PHY_PARAMETER_INFO_SET_IO_ADDR(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 16, __Value) -#define PHY_PARAMETER_INFO_SET_IO_ADDR_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 16, __Value) -#define PHY_PARAMETER_INFO_GET_DELAY_VALUE(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 16) -#define PHY_PARAMETER_INFO_SET_DELAY_VALUE(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 16, __Value) -#define PHY_PARAMETER_INFO_SET_DELAY_VALUE_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 16, __Value) -#define PHY_PARAMETER_INFO_GET_RF_PATH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 24, 8) -#define PHY_PARAMETER_INFO_SET_RF_PATH(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 24, 8, __Value) -#define PHY_PARAMETER_INFO_SET_RF_PATH_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 24, 8, __Value) -#define PHY_PARAMETER_INFO_GET_DATA(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X04, 0, 32) -#define PHY_PARAMETER_INFO_SET_DATA(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X04, 0, 32, __Value) -#define PHY_PARAMETER_INFO_SET_DATA_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X04, 0, 32, __Value) -#define PHY_PARAMETER_INFO_GET_MASK(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X08, 0, 32) -#define PHY_PARAMETER_INFO_SET_MASK(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X08, 0, 32, __Value) -#define PHY_PARAMETER_INFO_SET_MASK_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X08, 0, 32, __Value) -#define CHANNEL_INFO_GET_CHANNEL(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 8) -#define CHANNEL_INFO_SET_CHANNEL(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 0, 8, __Value) -#define CHANNEL_INFO_SET_CHANNEL_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 0, 8, __Value) -#define CHANNEL_INFO_GET_PRI_CH_IDX(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 8, 4) -#define CHANNEL_INFO_SET_PRI_CH_IDX(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 8, 4, __Value) -#define CHANNEL_INFO_SET_PRI_CH_IDX_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 8, 4, __Value) -#define CHANNEL_INFO_GET_BANDWIDTH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 12, 4) -#define CHANNEL_INFO_SET_BANDWIDTH(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 12, 4, __Value) -#define CHANNEL_INFO_SET_BANDWIDTH_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 12, 4, __Value) -#define CHANNEL_INFO_GET_TIMEOUT(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) -#define CHANNEL_INFO_SET_TIMEOUT(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define CHANNEL_INFO_SET_TIMEOUT_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define CHANNEL_INFO_GET_ACTION_ID(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 24, 7) -#define CHANNEL_INFO_SET_ACTION_ID(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 24, 7, __Value) -#define CHANNEL_INFO_SET_ACTION_ID_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 24, 7, __Value) -#define CHANNEL_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 31, 1) -#define CHANNEL_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 31, 1, __Value) -#define CHANNEL_INFO_SET_CH_EXTRA_INFO_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 31, 1, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_ID(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 7) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 0, 7, __Value) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 0, 7, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 7, 1) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 7, 1, __Value) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 7, 1, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_SIZE(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 8, 8) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 8, 8, __Value) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 8, 8, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_DATA(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 1) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 1, __Value) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 1, __Value) +#define PARAM_INFO_GET_LEN(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8) +#define PARAM_INFO_SET_LEN(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value) +#define PARAM_INFO_SET_LEN_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 8, value) +#define PARAM_INFO_GET_IO_CMD(extra_info) GET_C2H_FIELD(extra_info + 0X00, 8, 7) +#define PARAM_INFO_SET_IO_CMD(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 7, value) +#define PARAM_INFO_SET_IO_CMD_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 7, value) +#define PARAM_INFO_GET_MSK_EN(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 15, 1) +#define PARAM_INFO_SET_MSK_EN(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 15, 1, value) +#define PARAM_INFO_SET_MSK_EN_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 15, 1, value) +#define PARAM_INFO_GET_LLT_PG_BNDY(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_LLT_PG_BNDY(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_SET_LLT_PG_BNDY_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_EFUSE_RSVDPAGE_LOC(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_EFUSE_PATCH_EN(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_EFUSE_PATCH_EN(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_SET_EFUSE_PATCH_EN_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_RF_ADDR(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_RF_ADDR(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_SET_RF_ADDR_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_IO_ADDR(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 16) +#define PARAM_INFO_SET_IO_ADDR(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value) +#define PARAM_INFO_SET_IO_ADDR_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value) +#define PARAM_INFO_GET_DELAY_VAL(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 16) +#define PARAM_INFO_SET_DELAY_VAL(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value) +#define PARAM_INFO_SET_DELAY_VAL_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value) +#define PARAM_INFO_GET_RF_PATH(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 24, 8) +#define PARAM_INFO_SET_RF_PATH(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 24, 8, value) +#define PARAM_INFO_SET_RF_PATH_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 24, 8, value) +#define PARAM_INFO_GET_DATA(extra_info) GET_C2H_FIELD(extra_info + 0X04, 0, 32) +#define PARAM_INFO_SET_DATA(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 32, value) +#define PARAM_INFO_SET_DATA_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 32, value) +#define PARAM_INFO_GET_MASK(extra_info) GET_C2H_FIELD(extra_info + 0X08, 0, 32) +#define PARAM_INFO_SET_MASK(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X08, 0, 32, value) +#define PARAM_INFO_SET_MASK_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X08, 0, 32, value) +#define CH_INFO_GET_CH(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8) +#define CH_INFO_SET_CH(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value) +#define CH_INFO_SET_CH_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 8, value) +#define CH_INFO_GET_PRI_CH_IDX(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 8, 4) +#define CH_INFO_SET_PRI_CH_IDX(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 4, value) +#define CH_INFO_SET_PRI_CH_IDX_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 4, value) +#define CH_INFO_GET_BW(extra_info) GET_C2H_FIELD(extra_info + 0X00, 12, 4) +#define CH_INFO_SET_BW(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 12, 4, value) +#define CH_INFO_SET_BW_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 12, 4, value) +#define CH_INFO_GET_TIMEOUT(extra_info) GET_C2H_FIELD(extra_info + 0X00, 16, 8) +#define CH_INFO_SET_TIMEOUT(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value) +#define CH_INFO_SET_TIMEOUT_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value) +#define CH_INFO_GET_ACTION_ID(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 24, 7) +#define CH_INFO_SET_ACTION_ID(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 24, 7, value) +#define CH_INFO_SET_ACTION_ID_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 24, 7, value) +#define CH_INFO_GET_EXTRA_INFO(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 31, 1) +#define CH_INFO_SET_EXTRA_INFO(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 31, 1, value) +#define CH_INFO_SET_EXTRA_INFO_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 31, 1, value) +#define CH_EXTRA_INFO_GET_ID(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 7) +#define CH_EXTRA_INFO_SET_ID(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 7, value) +#define CH_EXTRA_INFO_SET_ID_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 7, value) +#define CH_EXTRA_INFO_GET_INFO(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 7, 1) +#define CH_EXTRA_INFO_SET_INFO(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 7, 1, value) +#define CH_EXTRA_INFO_SET_INFO_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 7, 1, value) +#define CH_EXTRA_INFO_GET_SIZE(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 8, 8) +#define CH_EXTRA_INFO_SET_SIZE(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 8, value) +#define CH_EXTRA_INFO_SET_SIZE_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 8, value) +#define CH_EXTRA_INFO_GET_DATA(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 1) +#define CH_EXTRA_INFO_SET_DATA(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 1, value) +#define CH_EXTRA_INFO_SET_DATA_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_L(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 0, 16) +#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 16, value) +#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_BITDATA(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 0, 16) +#define HIOE_INSTRUCTION_INFO_SET_BITDATA(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 16, value) +#define HIOE_INSTRUCTION_INFO_SET_BITDATA_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_H(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 16) +#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value) +#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_BITMASK(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 16) +#define HIOE_INSTRUCTION_INFO_SET_BITMASK(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value) +#define HIOE_INSTRUCTION_INFO_SET_BITMASK_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_REG_ADDR(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 0, 22) +#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 22, value) +#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 22, value) +#define HIOE_INSTRUCTION_INFO_GET_DELAY_VALUE(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 0, 22) +#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 22, value) +#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 22, value) +#define HIOE_INSTRUCTION_INFO_GET_MODE_SELECT(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 22, 1) +#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 22, 1, value) +#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 22, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_IO_DELAY(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 23, 1) +#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 23, 1, value) +#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 23, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_BYTEMASK(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 24, 4) +#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 24, 4, value) +#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 24, 4, value) +#define HIOE_INSTRUCTION_INFO_GET_RD_EN(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 28, 1) +#define HIOE_INSTRUCTION_INFO_SET_RD_EN(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 28, 1, value) +#define HIOE_INSTRUCTION_INFO_SET_RD_EN_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 28, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_WR_EN(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 29, 1) +#define HIOE_INSTRUCTION_INFO_SET_WR_EN(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 29, 1, value) +#define HIOE_INSTRUCTION_INFO_SET_WR_EN_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 29, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_RAW_R(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 30, 1) +#define HIOE_INSTRUCTION_INFO_SET_RAW_R(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 30, 1, value) +#define HIOE_INSTRUCTION_INFO_SET_RAW_R_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 30, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_RAW(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 31, 1) +#define HIOE_INSTRUCTION_INFO_SET_RAW(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 31, 1, value) +#define HIOE_INSTRUCTION_INFO_SET_RAW_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 31, 1, value) #endif diff --git a/hal/halmac/halmac_h2c_extra_info_nic.h b/hal/halmac/halmac_h2c_extra_info_nic.h index 41e4e96..d48a683 100644 --- a/hal/halmac/halmac_h2c_extra_info_nic.h +++ b/hal/halmac/halmac_h2c_extra_info_nic.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,48 +15,157 @@ #ifndef _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_ #define _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_ -#define PHY_PARAMETER_INFO_GET_LENGTH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 8) -#define PHY_PARAMETER_INFO_SET_LENGTH(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 0, 8, __Value) -#define PHY_PARAMETER_INFO_GET_IO_CMD(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 8, 7) -#define PHY_PARAMETER_INFO_SET_IO_CMD(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 8, 7, __Value) -#define PHY_PARAMETER_INFO_GET_MSK_EN(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 15, 1) -#define PHY_PARAMETER_INFO_SET_MSK_EN(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 15, 1, __Value) -#define PHY_PARAMETER_INFO_GET_LLT_PG_BNDY(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_EFUSE_RSVDPAGE_LOC(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_EFUSE_PATCH_EN(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_RF_ADDR(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_RF_ADDR(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_IO_ADDR(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 16) -#define PHY_PARAMETER_INFO_SET_IO_ADDR(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 16, __Value) -#define PHY_PARAMETER_INFO_GET_DELAY_VALUE(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 16) -#define PHY_PARAMETER_INFO_SET_DELAY_VALUE(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 16, __Value) -#define PHY_PARAMETER_INFO_GET_RF_PATH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 24, 8) -#define PHY_PARAMETER_INFO_SET_RF_PATH(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 24, 8, __Value) -#define PHY_PARAMETER_INFO_GET_DATA(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X04, 0, 32) -#define PHY_PARAMETER_INFO_SET_DATA(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X04, 0, 32, __Value) -#define PHY_PARAMETER_INFO_GET_MASK(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X08, 0, 32) -#define PHY_PARAMETER_INFO_SET_MASK(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X08, 0, 32, __Value) -#define CHANNEL_INFO_GET_CHANNEL(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 8) -#define CHANNEL_INFO_SET_CHANNEL(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 0, 8, __Value) -#define CHANNEL_INFO_GET_PRI_CH_IDX(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 8, 4) -#define CHANNEL_INFO_SET_PRI_CH_IDX(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 8, 4, __Value) -#define CHANNEL_INFO_GET_BANDWIDTH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 12, 4) -#define CHANNEL_INFO_SET_BANDWIDTH(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 12, 4, __Value) -#define CHANNEL_INFO_GET_TIMEOUT(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) -#define CHANNEL_INFO_SET_TIMEOUT(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) -#define CHANNEL_INFO_GET_ACTION_ID(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 24, 7) -#define CHANNEL_INFO_SET_ACTION_ID(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 24, 7, __Value) -#define CHANNEL_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 31, 1) -#define CHANNEL_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 31, 1, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_ID(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 7) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 0, 7, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 7, 1) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 7, 1, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_SIZE(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 8, 8) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 8, 8, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_DATA(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 1) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 1, __Value) + +/* H2C extra info (rsvd page) usage, unit : page (128byte)*/ +/* dlfw : not include txdesc size*/ +/* update pkt : not include txdesc size*/ +/* cfg param : not include txdesc size*/ +/* scan info : not include txdesc size*/ +/* dl flash : not include txdesc size*/ +#define DLFW_RSVDPG_SIZE 2048 +#define UPDATE_PKT_RSVDPG_SIZE 2048 +#define CFG_PARAM_RSVDPG_SIZE 2048 +#define SCAN_INFO_RSVDPG_SIZE 256 +#define DL_FLASH_RSVDPG_SIZE 2048 +/* su0 snding pkt : include txdesc size */ +#define SU0_SNDING_PKT_OFFSET 0 +#define SU0_SNDING_PKT_RSVDPG_SIZE 128 + +#define PARAM_INFO_GET_LEN(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 8) +#define PARAM_INFO_SET_LEN(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 8, value) +#define PARAM_INFO_GET_IO_CMD(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 7) +#define PARAM_INFO_SET_IO_CMD(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 7, value) +#define PARAM_INFO_GET_MSK_EN(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 15, 1) +#define PARAM_INFO_SET_MSK_EN(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 15, 1, value) +#define PARAM_INFO_GET_LLT_PG_BNDY(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_LLT_PG_BNDY(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_EFUSE_RSVDPAGE_LOC(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_EFUSE_PATCH_EN(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_EFUSE_PATCH_EN(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_RF_ADDR(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_RF_ADDR(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_IO_ADDR(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16) +#define PARAM_INFO_SET_IO_ADDR(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value) +#define PARAM_INFO_GET_DELAY_VAL(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16) +#define PARAM_INFO_SET_DELAY_VAL(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value) +#define PARAM_INFO_GET_RF_PATH(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 24, 8) +#define PARAM_INFO_SET_RF_PATH(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 24, 8, value) +#define PARAM_INFO_GET_DATA(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 32) +#define PARAM_INFO_SET_DATA(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 32, value) +#define PARAM_INFO_GET_MASK(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X08, 0, 32) +#define PARAM_INFO_SET_MASK(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X08, 0, 32, value) +#define CH_INFO_GET_CH(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 8) +#define CH_INFO_SET_CH(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 8, value) +#define CH_INFO_GET_PRI_CH_IDX(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 4) +#define CH_INFO_SET_PRI_CH_IDX(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 4, value) +#define CH_INFO_GET_BW(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 12, 4) +#define CH_INFO_SET_BW(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 12, 4, value) +#define CH_INFO_GET_TIMEOUT(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8) +#define CH_INFO_SET_TIMEOUT(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value) +#define CH_INFO_GET_ACTION_ID(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 24, 7) +#define CH_INFO_SET_ACTION_ID(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 24, 7, value) +#define CH_INFO_GET_EXTRA_INFO(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 31, 1) +#define CH_INFO_SET_EXTRA_INFO(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 31, 1, value) +#define CH_EXTRA_INFO_GET_ID(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 7) +#define CH_EXTRA_INFO_SET_ID(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 7, value) +#define CH_EXTRA_INFO_GET_INFO(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 7, 1) +#define CH_EXTRA_INFO_SET_INFO(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 7, 1, value) +#define CH_EXTRA_INFO_GET_SIZE(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 8) +#define CH_EXTRA_INFO_SET_SIZE(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 8, value) +#define CH_EXTRA_INFO_GET_DATA(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 1) +#define CH_EXTRA_INFO_SET_DATA(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_L(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 16) +#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_BITDATA(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 16) +#define HIOE_INSTRUCTION_INFO_SET_BITDATA(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_H(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16) +#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_BITMASK(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16) +#define HIOE_INSTRUCTION_INFO_SET_BITMASK(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_REG_ADDR(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 22) +#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 22, value) +#define HIOE_INSTRUCTION_INFO_GET_DELAY_VALUE(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 22) +#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 22, value) +#define HIOE_INSTRUCTION_INFO_GET_MODE_SELECT(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 22, 1) +#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 22, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_IO_DELAY(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 23, 1) +#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 23, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_BYTEMASK(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 24, 4) +#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 24, 4, value) +#define HIOE_INSTRUCTION_INFO_GET_RD_EN(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 28, 1) +#define HIOE_INSTRUCTION_INFO_SET_RD_EN(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 28, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_WR_EN(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 29, 1) +#define HIOE_INSTRUCTION_INFO_SET_WR_EN(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 29, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_RAW_R(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 30, 1) +#define HIOE_INSTRUCTION_INFO_SET_RAW_R(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 30, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_RAW(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 31, 1) +#define HIOE_INSTRUCTION_INFO_SET_RAW(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 31, 1, value) #endif diff --git a/hal/halmac/halmac_hw_cfg.h b/hal/halmac/halmac_hw_cfg.h index b63cf18..8d64a83 100644 --- a/hal/halmac/halmac_hw_cfg.h +++ b/hal/halmac/halmac_hw_cfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -18,10 +18,6 @@ #include /* CONFIG_[IC] */ -#ifndef BIT - #define BIT(x) (1 << (x)) -#endif - #ifdef CONFIG_RTL8723A #define HALMAC_8723A_SUPPORT 1 #else @@ -76,12 +72,6 @@ #define HALMAC_8814A_SUPPORT 0 #endif -#ifdef CONFIG_RTL8814B -#define HALMAC_8814B_SUPPORT 1 -#else -#define HALMAC_8814B_SUPPORT 0 -#endif - #ifdef CONFIG_RTL8881A #define HALMAC_8881A_SUPPORT 1 #else @@ -142,6 +132,21 @@ #define HALMAC_8197F_SUPPORT 0 #endif +#ifdef CONFIG_RTL8198F +#define HALMAC_8198F_SUPPORT 1 +#else +#define HALMAC_8198F_SUPPORT 0 +#endif + + +/* Halmac support IC version */ + +#ifdef CONFIG_RTL8814B +#define HALMAC_8814B_SUPPORT 1 +#else +#define HALMAC_8814B_SUPPORT 0 +#endif + #ifdef CONFIG_RTL8821C #define HALMAC_8821C_SUPPORT 1 #else @@ -154,6 +159,12 @@ #define HALMAC_8822B_SUPPORT 0 #endif +#ifdef CONFIG_RTL8822C +#define HALMAC_8822C_SUPPORT 1 +#else +#define HALMAC_8822C_SUPPORT 0 +#endif + #endif /* __HALMAC__HW_CFG_H__ */ diff --git a/hal/halmac/halmac_intf_phy_cmd.h b/hal/halmac/halmac_intf_phy_cmd.h index a4be694..f44bfa1 100644 --- a/hal/halmac/halmac_intf_phy_cmd.h +++ b/hal/halmac/halmac_intf_phy_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -17,7 +17,7 @@ #define HALMAC_INTF_PHY_CMD /* Cut mask */ -typedef enum _HALMAC_INTF_PHY_CUT { +enum halmac_intf_phy_cut { HALMAC_INTF_PHY_CUT_TESTCHIP = BIT(0), HALMAC_INTF_PHY_CUT_A = BIT(1), HALMAC_INTF_PHY_CUT_B = BIT(2), @@ -27,19 +27,19 @@ typedef enum _HALMAC_INTF_PHY_CUT { HALMAC_INTF_PHY_CUT_F = BIT(6), HALMAC_INTF_PHY_CUT_G = BIT(7), HALMAC_INTF_PHY_CUT_ALL = 0x7FFF, -} HALMAC_INTF_PHY_CUT; +}; /* IP selection */ -typedef enum _HALMAC_IP_SEL { - HALMAC_IP_SEL_INTF_PHY = 0, +enum halmac_ip_sel { + HALMAC_IP_INTF_PHY = 0, HALMAC_IP_SEL_MAC = 1, - HALMAC_IP_SEL_PCIE_DBI = 2, + HALMAC_IP_PCIE_DBI = 2, HALMAC_IP_SEL_UNDEFINE = 0x7FFF, -} HALMAC_IP_SEL; +}; /* Platform mask */ -typedef enum _HALMAC_INTF_PHY_PLATFORM { +enum halmac_intf_phy_platform { HALMAC_INTF_PHY_PLATFORM_ALL = 0x7FFF, -} HALMAC_INTF_PHY_PLATFORM; +}; #endif diff --git a/hal/halmac/halmac_original_c2h_ap.h b/hal/halmac/halmac_original_c2h_ap.h index 731702a..bb4bda1 100644 --- a/hal/halmac/halmac_original_c2h_ap.h +++ b/hal/halmac/halmac_original_c2h_ap.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,337 +15,598 @@ #ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_ #define _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_ -#define CMD_ID_C2H 0X00 -#define CMD_ID_DBG 0X00 -#define CMD_ID_C2H_LB 0X01 -#define CMD_ID_C2H_SND_TXBF 0X02 -#define CMD_ID_C2H_CCX_RPT 0X03 -#define CMD_ID_C2H_AP_REQ_TXRPT 0X04 -#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05 -#define CMD_ID_C2H_RA_RPT 0X0C -#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D -#define CMD_ID_C2H_RA_PARA_RPT 0X0E -#define CMD_ID_C2H_CUR_CHANNEL 0X10 -#define CMD_ID_C2H_GPIO_WAKEUP 0X14 -#define C2H_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define DBG_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define DBG_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define DBG_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define DBG_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define DBG_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define DBG_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define DBG_GET_DBG_STR1(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) -#define DBG_SET_DBG_STR1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) -#define DBG_SET_DBG_STR1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) -#define DBG_GET_DBG_STR2(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define DBG_SET_DBG_STR2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define DBG_SET_DBG_STR2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define DBG_GET_DBG_STR3(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define DBG_SET_DBG_STR3(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define DBG_SET_DBG_STR3_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define DBG_GET_DBG_STR4(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define DBG_SET_DBG_STR4(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define DBG_SET_DBG_STR4_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define DBG_GET_DBG_STR5(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) -#define DBG_SET_DBG_STR5(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) -#define DBG_SET_DBG_STR5_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) -#define DBG_GET_DBG_STR6(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) -#define DBG_SET_DBG_STR6(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) -#define DBG_SET_DBG_STR6_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) -#define DBG_GET_DBG_STR7(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) -#define DBG_SET_DBG_STR7(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) -#define DBG_SET_DBG_STR7_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) -#define DBG_GET_DBG_STR8(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8) -#define DBG_SET_DBG_STR8(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value) -#define DBG_SET_DBG_STR8_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value) -#define DBG_GET_DBG_STR9(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 16, 8) -#define DBG_SET_DBG_STR9(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 16, 8, __Value) -#define DBG_SET_DBG_STR9_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 16, 8, __Value) -#define DBG_GET_DBG_STR10(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 24, 8) -#define DBG_SET_DBG_STR10(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 24, 8, __Value) -#define DBG_SET_DBG_STR10_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 24, 8, __Value) -#define DBG_GET_DBG_STR11(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 0, 8) -#define DBG_SET_DBG_STR11(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 0, 8, __Value) -#define DBG_SET_DBG_STR11_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 0, 8, __Value) -#define DBG_GET_DBG_STR12(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 8, 8) -#define DBG_SET_DBG_STR12(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 8, 8, __Value) -#define DBG_SET_DBG_STR12_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 8, 8, __Value) -#define DBG_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define DBG_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define DBG_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define DBG_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define DBG_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define DBG_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_LB_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_LB_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_LB_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_LB_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_LB_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_LB_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_LB_GET_PAYLOAD1(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 16) -#define C2H_LB_SET_PAYLOAD1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 16, __Value) -#define C2H_LB_SET_PAYLOAD1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 16, __Value) -#define C2H_LB_GET_PAYLOAD2(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 32) -#define C2H_LB_SET_PAYLOAD2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 32, __Value) -#define C2H_LB_SET_PAYLOAD2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 32, __Value) -#define C2H_LB_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_LB_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_LB_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_LB_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_LB_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_LB_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_SND_TXBF_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_SND_TXBF_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SND_TXBF_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SND_TXBF_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_SND_TXBF_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SND_TXBF_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SND_TXBF_GET_SND_RESULT(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 1) -#define C2H_SND_TXBF_SET_SND_RESULT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 1, __Value) -#define C2H_SND_TXBF_SET_SND_RESULT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 1, __Value) -#define C2H_SND_TXBF_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_SND_TXBF_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_SND_TXBF_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_SND_TXBF_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_SND_TXBF_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_SND_TXBF_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_CCX_RPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_CCX_RPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_CCX_RPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_CCX_RPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_CCX_RPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_CCX_RPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_CCX_RPT_GET_QSEL(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 5) -#define C2H_CCX_RPT_SET_QSEL(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 5, __Value) -#define C2H_CCX_RPT_SET_QSEL_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 5, __Value) -#define C2H_CCX_RPT_GET_BMC(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 21, 1) -#define C2H_CCX_RPT_SET_BMC(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 21, 1, __Value) -#define C2H_CCX_RPT_SET_BMC_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 21, 1, __Value) -#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 22, 1) -#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 22, 1, __Value) -#define C2H_CCX_RPT_SET_LIFE_TIME_OVER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 22, 1, __Value) -#define C2H_CCX_RPT_GET_RETRY_OVER(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 23, 1) -#define C2H_CCX_RPT_SET_RETRY_OVER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 23, 1, __Value) -#define C2H_CCX_RPT_SET_RETRY_OVER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 23, 1, __Value) -#define C2H_CCX_RPT_GET_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define C2H_CCX_RPT_SET_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_CCX_RPT_SET_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 6) -#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 6, __Value) -#define C2H_CCX_RPT_SET_DATA_RETRY_CNT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 6, __Value) -#define C2H_CCX_RPT_GET_QUEUE7_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define C2H_CCX_RPT_SET_QUEUE7_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_CCX_RPT_SET_QUEUE7_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_CCX_RPT_GET_QUEUE15_8(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) -#define C2H_CCX_RPT_SET_QUEUE15_8(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_CCX_RPT_SET_QUEUE15_8_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) -#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_CCX_RPT_GET_SW_DEFINE_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) -#define C2H_CCX_RPT_SET_SW_DEFINE_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_CCX_RPT_SET_SW_DEFINE_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_CCX_RPT_GET_SW_DEFINE_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 4) -#define C2H_CCX_RPT_SET_SW_DEFINE_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 4, __Value) -#define C2H_CCX_RPT_SET_SW_DEFINE_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 4, __Value) -#define C2H_CCX_RPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_CCX_RPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_CCX_RPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_CCX_RPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_CCX_RPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_CCX_RPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 7) -#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 7, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 7, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_RA_RPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_RA_RPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_RA_RPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_RA_RPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_RA_RPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_RA_RPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_RA_RPT_GET_RATE(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) -#define C2H_RA_RPT_SET_RATE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_RA_RPT_SET_RATE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_RA_RPT_GET_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define C2H_RA_RPT_SET_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_RA_RPT_SET_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_RA_RPT_GET_USE_LDPC(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 1) -#define C2H_RA_RPT_SET_USE_LDPC(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 1, __Value) -#define C2H_RA_RPT_SET_USE_LDPC_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 1, __Value) -#define C2H_RA_RPT_GET_USE_TXBF(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 1, 1) -#define C2H_RA_RPT_SET_USE_TXBF(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 1, 1, __Value) -#define C2H_RA_RPT_SET_USE_TXBF_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 1, 1, __Value) -#define C2H_RA_RPT_GET_COLLISION_STATE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define C2H_RA_RPT_SET_COLLISION_STATE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_RA_RPT_SET_COLLISION_STATE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_RA_RPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_RA_RPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_RA_RPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_RA_RPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_RA_RPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_RA_RPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_SPECIAL_STATISTICS_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA0(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA2(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA3(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA3(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA3_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA4(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA4(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA4_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA5(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA5(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA5_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA6(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA6(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA6_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA7(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA7(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA7_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_RA_PARA_RPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_RA_PARA_RPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_RA_PARA_RPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_RA_PARA_RPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_RA_PARA_RPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_RA_PARA_RPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_RA_PARA_RPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_RA_PARA_RPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_RA_PARA_RPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_RA_PARA_RPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_RA_PARA_RPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_RA_PARA_RPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_CUR_CHANNEL_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_CUR_CHANNEL_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_CUR_CHANNEL_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_CUR_CHANNEL_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_CUR_CHANNEL_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_CUR_CHANNEL_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) -#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_CUR_CHANNEL_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_CUR_CHANNEL_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_CUR_CHANNEL_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_CUR_CHANNEL_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_CUR_CHANNEL_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_CUR_CHANNEL_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_GPIO_WAKEUP_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_GPIO_WAKEUP_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_GPIO_WAKEUP_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_GPIO_WAKEUP_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_GPIO_WAKEUP_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_GPIO_WAKEUP_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_GPIO_WAKEUP_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_GPIO_WAKEUP_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define CMD_ID_C2H 0X00 +#define CMD_ID_DBG 0X00 +#define CMD_ID_C2H_LB 0X01 +#define CMD_ID_C2H_SND_TXBF 0X02 +#define CMD_ID_C2H_CCX_RPT 0X03 +#define CMD_ID_C2H_AP_REQ_TXRPT 0X04 +#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05 +#define CMD_ID_C2H_RA_RPT 0X0C +#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D +#define CMD_ID_C2H_RA_PARA_RPT 0X0E +#define CMD_ID_C2H_CUR_CHANNEL 0X10 +#define CMD_ID_C2H_GPIO_WAKEUP 0X14 +#define C2H_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define DBG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define DBG_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define DBG_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define DBG_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define DBG_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define DBG_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define DBG_GET_DBG_STR1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define DBG_SET_DBG_STR1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define DBG_SET_DBG_STR1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define DBG_GET_DBG_STR2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define DBG_SET_DBG_STR2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define DBG_SET_DBG_STR2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define DBG_GET_DBG_STR3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define DBG_SET_DBG_STR3(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define DBG_SET_DBG_STR3_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define DBG_GET_DBG_STR4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define DBG_SET_DBG_STR4(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define DBG_SET_DBG_STR4_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define DBG_GET_DBG_STR5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define DBG_SET_DBG_STR5(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define DBG_SET_DBG_STR5_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define DBG_GET_DBG_STR6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define DBG_SET_DBG_STR6(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define DBG_SET_DBG_STR6_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define DBG_GET_DBG_STR7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8) +#define DBG_SET_DBG_STR7(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value) +#define DBG_SET_DBG_STR7_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value) +#define DBG_GET_DBG_STR8(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8) +#define DBG_SET_DBG_STR8(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value) +#define DBG_SET_DBG_STR8_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value) +#define DBG_GET_DBG_STR9(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8) +#define DBG_SET_DBG_STR9(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value) +#define DBG_SET_DBG_STR9_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value) +#define DBG_GET_DBG_STR10(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8) +#define DBG_SET_DBG_STR10(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value) +#define DBG_SET_DBG_STR10_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value) +#define DBG_GET_DBG_STR11(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8) +#define DBG_SET_DBG_STR11(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value) +#define DBG_SET_DBG_STR11_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value) +#define DBG_GET_DBG_STR12(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8) +#define DBG_SET_DBG_STR12(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value) +#define DBG_SET_DBG_STR12_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value) +#define DBG_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define DBG_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define DBG_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define DBG_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define DBG_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define DBG_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_LB_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_LB_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_LB_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_LB_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_LB_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_LB_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_LB_GET_PAYLOAD1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 16) +#define C2H_LB_SET_PAYLOAD1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 16, value) +#define C2H_LB_SET_PAYLOAD1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 16, value) +#define C2H_LB_GET_PAYLOAD2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 32) +#define C2H_LB_SET_PAYLOAD2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 32, value) +#define C2H_LB_SET_PAYLOAD2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 32, value) +#define C2H_LB_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_LB_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_LB_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_LB_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_LB_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_LB_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_SND_TXBF_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_SND_TXBF_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SND_TXBF_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SND_TXBF_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_SND_TXBF_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SND_TXBF_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SND_TXBF_GET_SND_RESULT(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 1) +#define C2H_SND_TXBF_SET_SND_RESULT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 1, value) +#define C2H_SND_TXBF_SET_SND_RESULT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 1, value) +#define C2H_SND_TXBF_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_SND_TXBF_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_SND_TXBF_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_SND_TXBF_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_SND_TXBF_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_SND_TXBF_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_CCX_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_CCX_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_CCX_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_CCX_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_CCX_RPT_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_CCX_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_CCX_RPT_GET_QSEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 5) +#define C2H_CCX_RPT_SET_QSEL(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 5, value) +#define C2H_CCX_RPT_SET_QSEL_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 5, value) +#define C2H_CCX_RPT_GET_BMC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 21, 1) +#define C2H_CCX_RPT_SET_BMC(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 21, 1, value) +#define C2H_CCX_RPT_SET_BMC_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 21, 1, value) +#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 22, 1) +#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 22, 1, value) +#define C2H_CCX_RPT_SET_LIFE_TIME_OVER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 22, 1, value) +#define C2H_CCX_RPT_GET_RETRY_OVER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 23, 1) +#define C2H_CCX_RPT_SET_RETRY_OVER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 23, 1, value) +#define C2H_CCX_RPT_SET_RETRY_OVER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 23, 1, value) +#define C2H_CCX_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define C2H_CCX_RPT_SET_MACID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_CCX_RPT_SET_MACID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 6) +#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 6, value) +#define C2H_CCX_RPT_SET_DATA_RETRY_CNT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 6, value) +#define C2H_CCX_RPT_GET_QUEUE7_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define C2H_CCX_RPT_SET_QUEUE7_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_CCX_RPT_SET_QUEUE7_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_CCX_RPT_GET_QUEUE15_8(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define C2H_CCX_RPT_SET_QUEUE15_8(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_CCX_RPT_SET_QUEUE15_8_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_CCX_RPT_GET_SW_DEFINE_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8) +#define C2H_CCX_RPT_SET_SW_DEFINE_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_CCX_RPT_SET_SW_DEFINE_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_CCX_RPT_GET_SW_DEFINE_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 4) +#define C2H_CCX_RPT_SET_SW_DEFINE_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 4, value) +#define C2H_CCX_RPT_SET_SW_DEFINE_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 4, value) +#define C2H_CCX_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_CCX_RPT_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_CCX_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_CCX_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_CCX_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_CCX_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_AP_REQ_TXRPT_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_AP_REQ_TXRPT_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TRIGGER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 7) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 7, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 7, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_RA_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_RA_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_RA_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_RA_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_RA_RPT_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_RA_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_RA_RPT_GET_RATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define C2H_RA_RPT_SET_RATE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_RA_RPT_SET_RATE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_RA_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define C2H_RA_RPT_SET_MACID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_RA_RPT_SET_MACID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_RA_RPT_GET_USE_LDPC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 1) +#define C2H_RA_RPT_SET_USE_LDPC(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 1, value) +#define C2H_RA_RPT_SET_USE_LDPC_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 1, value) +#define C2H_RA_RPT_GET_USE_TXBF(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 1, 1) +#define C2H_RA_RPT_SET_USE_TXBF(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 1, 1, value) +#define C2H_RA_RPT_SET_USE_TXBF_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 1, 1, value) +#define C2H_RA_RPT_GET_COLLISION_STATE(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define C2H_RA_RPT_SET_COLLISION_STATE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_RA_RPT_SET_COLLISION_STATE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_RA_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_RA_RPT_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_RA_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_RA_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_RA_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_RA_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_SEQ(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA2(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA3(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA3(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA3_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA4(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA4(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA4_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA5(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA5(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA5_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA6(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA6(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA6_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA7(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA7(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA7_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_LEN(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_RA_PARA_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_RA_PARA_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_RA_PARA_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_RA_PARA_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_RA_PARA_RPT_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_RA_PARA_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_RA_PARA_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_RA_PARA_RPT_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_RA_PARA_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_RA_PARA_RPT_GET_TRIGGER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_RA_PARA_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_RA_PARA_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_CUR_CHANNEL_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_CUR_CHANNEL_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_CUR_CHANNEL_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_CUR_CHANNEL_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_CUR_CHANNEL_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_CUR_CHANNEL_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_CUR_CHANNEL_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_CUR_CHANNEL_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_CUR_CHANNEL_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_CUR_CHANNEL_GET_TRIGGER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_CUR_CHANNEL_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_CUR_CHANNEL_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_GPIO_WAKEUP_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_GPIO_WAKEUP_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_GPIO_WAKEUP_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_GPIO_WAKEUP_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_GPIO_WAKEUP_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_GPIO_WAKEUP_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_GPIO_WAKEUP_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_GPIO_WAKEUP_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_GPIO_WAKEUP_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_GPIO_WAKEUP_GET_TRIGGER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_GPIO_WAKEUP_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) #endif diff --git a/hal/halmac/halmac_original_c2h_nic.h b/hal/halmac/halmac_original_c2h_nic.h index cd587da..18cc2c7 100644 --- a/hal/halmac/halmac_original_c2h_nic.h +++ b/hal/halmac/halmac_original_c2h_nic.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,230 +15,394 @@ #ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_ #define _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_ -#define CMD_ID_C2H 0X00 -#define CMD_ID_DBG 0X00 -#define CMD_ID_C2H_LB 0X01 -#define CMD_ID_C2H_SND_TXBF 0X02 -#define CMD_ID_C2H_CCX_RPT 0X03 -#define CMD_ID_C2H_AP_REQ_TXRPT 0X04 -#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05 -#define CMD_ID_C2H_RA_RPT 0X0C -#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D -#define CMD_ID_C2H_RA_PARA_RPT 0X0E -#define CMD_ID_C2H_CUR_CHANNEL 0X10 -#define CMD_ID_C2H_GPIO_WAKEUP 0X14 -#define C2H_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define DBG_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define DBG_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define DBG_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define DBG_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define DBG_GET_DBG_STR1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) -#define DBG_SET_DBG_STR1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) -#define DBG_GET_DBG_STR2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define DBG_SET_DBG_STR2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define DBG_GET_DBG_STR3(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define DBG_SET_DBG_STR3(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define DBG_GET_DBG_STR4(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define DBG_SET_DBG_STR4(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define DBG_GET_DBG_STR5(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) -#define DBG_SET_DBG_STR5(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) -#define DBG_GET_DBG_STR6(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) -#define DBG_SET_DBG_STR6(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) -#define DBG_GET_DBG_STR7(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) -#define DBG_SET_DBG_STR7(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) -#define DBG_GET_DBG_STR8(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8) -#define DBG_SET_DBG_STR8(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value) -#define DBG_GET_DBG_STR9(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 16, 8) -#define DBG_SET_DBG_STR9(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 16, 8, __Value) -#define DBG_GET_DBG_STR10(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 24, 8) -#define DBG_SET_DBG_STR10(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 24, 8, __Value) -#define DBG_GET_DBG_STR11(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 0, 8) -#define DBG_SET_DBG_STR11(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 0, 8, __Value) -#define DBG_GET_DBG_STR12(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 8, 8) -#define DBG_SET_DBG_STR12(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 8, 8, __Value) -#define DBG_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define DBG_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define DBG_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define DBG_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_LB_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_LB_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_LB_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_LB_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_LB_GET_PAYLOAD1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 16) -#define C2H_LB_SET_PAYLOAD1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 16, __Value) -#define C2H_LB_GET_PAYLOAD2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 32) -#define C2H_LB_SET_PAYLOAD2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 32, __Value) -#define C2H_LB_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_LB_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_LB_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_LB_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_SND_TXBF_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_SND_TXBF_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SND_TXBF_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_SND_TXBF_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SND_TXBF_GET_SND_RESULT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 1) -#define C2H_SND_TXBF_SET_SND_RESULT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 1, __Value) -#define C2H_SND_TXBF_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_SND_TXBF_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_SND_TXBF_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_SND_TXBF_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_CCX_RPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_CCX_RPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_CCX_RPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_CCX_RPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_CCX_RPT_GET_QSEL(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 5) -#define C2H_CCX_RPT_SET_QSEL(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 5, __Value) -#define C2H_CCX_RPT_GET_BMC(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 21, 1) -#define C2H_CCX_RPT_SET_BMC(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 21, 1, __Value) -#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 22, 1) -#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 22, 1, __Value) -#define C2H_CCX_RPT_GET_RETRY_OVER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 23, 1) -#define C2H_CCX_RPT_SET_RETRY_OVER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 23, 1, __Value) -#define C2H_CCX_RPT_GET_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define C2H_CCX_RPT_SET_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 6) -#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 6, __Value) -#define C2H_CCX_RPT_GET_QUEUE7_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define C2H_CCX_RPT_SET_QUEUE7_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define C2H_CCX_RPT_GET_QUEUE15_8(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) -#define C2H_CCX_RPT_SET_QUEUE15_8(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) -#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) -#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) -#define C2H_CCX_RPT_GET_SW_DEFINE_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) -#define C2H_CCX_RPT_SET_SW_DEFINE_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) -#define C2H_CCX_RPT_GET_SW_DEFINE_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 4) -#define C2H_CCX_RPT_SET_SW_DEFINE_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 4, __Value) -#define C2H_CCX_RPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_CCX_RPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_CCX_RPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_CCX_RPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 7) -#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 7, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_RA_RPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_RA_RPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_RA_RPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_RA_RPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_RA_RPT_GET_RATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) -#define C2H_RA_RPT_SET_RATE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) -#define C2H_RA_RPT_GET_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define C2H_RA_RPT_SET_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define C2H_RA_RPT_GET_USE_LDPC(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 1) -#define C2H_RA_RPT_SET_USE_LDPC(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 1, __Value) -#define C2H_RA_RPT_GET_USE_TXBF(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 1, 1) -#define C2H_RA_RPT_SET_USE_TXBF(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 1, 1, __Value) -#define C2H_RA_RPT_GET_COLLISION_STATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define C2H_RA_RPT_SET_COLLISION_STATE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define C2H_RA_RPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_RA_RPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_RA_RPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_RA_RPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_SPECIAL_STATISTICS_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA3(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA3(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA4(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA4(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA5(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA5(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA6(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA6(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA7(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA7(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_RA_PARA_RPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_RA_PARA_RPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_RA_PARA_RPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_RA_PARA_RPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_RA_PARA_RPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_RA_PARA_RPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_RA_PARA_RPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_RA_PARA_RPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_CUR_CHANNEL_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_CUR_CHANNEL_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_CUR_CHANNEL_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_CUR_CHANNEL_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) -#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) -#define C2H_CUR_CHANNEL_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_CUR_CHANNEL_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_CUR_CHANNEL_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_CUR_CHANNEL_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_GPIO_WAKEUP_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_GPIO_WAKEUP_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_GPIO_WAKEUP_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_GPIO_WAKEUP_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#define CMD_ID_C2H 0X00 +#define CMD_ID_DBG 0X00 +#define CMD_ID_C2H_LB 0X01 +#define CMD_ID_C2H_SND_TXBF 0X02 +#define CMD_ID_C2H_CCX_RPT 0X03 +#define CMD_ID_C2H_AP_REQ_TXRPT 0X04 +#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05 +#define CMD_ID_C2H_RA_RPT 0X0C +#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D +#define CMD_ID_C2H_RA_PARA_RPT 0X0E +#define CMD_ID_C2H_CUR_CHANNEL 0X10 +#define CMD_ID_C2H_GPIO_WAKEUP 0X14 +#define C2H_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define DBG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define DBG_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define DBG_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define DBG_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define DBG_GET_DBG_STR1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define DBG_SET_DBG_STR1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define DBG_GET_DBG_STR2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define DBG_SET_DBG_STR2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define DBG_GET_DBG_STR3(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define DBG_SET_DBG_STR3(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define DBG_GET_DBG_STR4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define DBG_SET_DBG_STR4(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define DBG_GET_DBG_STR5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define DBG_SET_DBG_STR5(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define DBG_GET_DBG_STR6(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define DBG_SET_DBG_STR6(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define DBG_GET_DBG_STR7(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8) +#define DBG_SET_DBG_STR7(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value) +#define DBG_GET_DBG_STR8(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8) +#define DBG_SET_DBG_STR8(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value) +#define DBG_GET_DBG_STR9(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8) +#define DBG_SET_DBG_STR9(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value) +#define DBG_GET_DBG_STR10(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8) +#define DBG_SET_DBG_STR10(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value) +#define DBG_GET_DBG_STR11(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8) +#define DBG_SET_DBG_STR11(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value) +#define DBG_GET_DBG_STR12(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8) +#define DBG_SET_DBG_STR12(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value) +#define DBG_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define DBG_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define DBG_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define DBG_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_LB_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_LB_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_LB_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_LB_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_LB_GET_PAYLOAD1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 16) +#define C2H_LB_SET_PAYLOAD1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 16, value) +#define C2H_LB_GET_PAYLOAD2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 32) +#define C2H_LB_SET_PAYLOAD2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 32, value) +#define C2H_LB_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_LB_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_LB_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_LB_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_SND_TXBF_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_SND_TXBF_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SND_TXBF_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_SND_TXBF_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SND_TXBF_GET_SND_RESULT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 1) +#define C2H_SND_TXBF_SET_SND_RESULT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 1, value) +#define C2H_SND_TXBF_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_SND_TXBF_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_SND_TXBF_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_SND_TXBF_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_CCX_RPT_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_CCX_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_CCX_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_CCX_RPT_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_CCX_RPT_GET_QSEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 5) +#define C2H_CCX_RPT_SET_QSEL(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 5, value) +#define C2H_CCX_RPT_GET_BMC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 21, 1) +#define C2H_CCX_RPT_SET_BMC(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 21, 1, value) +#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 22, 1) +#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 22, 1, value) +#define C2H_CCX_RPT_GET_RETRY_OVER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 23, 1) +#define C2H_CCX_RPT_SET_RETRY_OVER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 23, 1, value) +#define C2H_CCX_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define C2H_CCX_RPT_SET_MACID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 6) +#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 6, value) +#define C2H_CCX_RPT_GET_QUEUE7_0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define C2H_CCX_RPT_SET_QUEUE7_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define C2H_CCX_RPT_GET_QUEUE15_8(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define C2H_CCX_RPT_SET_QUEUE15_8(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define C2H_CCX_RPT_GET_SW_DEFINE_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8) +#define C2H_CCX_RPT_SET_SW_DEFINE_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value) +#define C2H_CCX_RPT_GET_SW_DEFINE_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 4) +#define C2H_CCX_RPT_SET_SW_DEFINE_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 4, value) +#define C2H_CCX_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_CCX_RPT_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_CCX_RPT_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_CCX_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_LEN(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 7) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 7, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_RA_RPT_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_RA_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_RA_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_RA_RPT_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_RA_RPT_GET_RATE(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define C2H_RA_RPT_SET_RATE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define C2H_RA_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define C2H_RA_RPT_SET_MACID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define C2H_RA_RPT_GET_USE_LDPC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 1) +#define C2H_RA_RPT_SET_USE_LDPC(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 1, value) +#define C2H_RA_RPT_GET_USE_TXBF(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 1, 1) +#define C2H_RA_RPT_SET_USE_TXBF(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 1, 1, value) +#define C2H_RA_RPT_GET_COLLISION_STATE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define C2H_RA_RPT_SET_COLLISION_STATE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define C2H_RA_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_RA_RPT_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_RA_RPT_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_RA_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_SEQ(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA2(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA3(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA3(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA4(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA4(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA5(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA5(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA6(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA6(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA7(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA7(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_LEN(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_RA_PARA_RPT_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_RA_PARA_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_RA_PARA_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_RA_PARA_RPT_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_RA_PARA_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_RA_PARA_RPT_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_RA_PARA_RPT_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_RA_PARA_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_CUR_CHANNEL_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_CUR_CHANNEL_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_CUR_CHANNEL_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_CUR_CHANNEL_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define C2H_CUR_CHANNEL_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_CUR_CHANNEL_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_CUR_CHANNEL_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_CUR_CHANNEL_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_GPIO_WAKEUP_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_GPIO_WAKEUP_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_GPIO_WAKEUP_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_GPIO_WAKEUP_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_GPIO_WAKEUP_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_GPIO_WAKEUP_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_GPIO_WAKEUP_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) #endif diff --git a/hal/halmac/halmac_original_h2c_ap.h b/hal/halmac/halmac_original_h2c_ap.h index c5100a7..b28c995 100644 --- a/hal/halmac/halmac_original_h2c_ap.h +++ b/hal/halmac/halmac_original_h2c_ap.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,40 +15,43 @@ #ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_ #define _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_ -#define CMD_ID_ORIGINAL_H2C 0X00 -#define CMD_ID_H2C2H_LB 0X0 -#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06 -#define CMD_ID_RSVD_PAGE 0X0 -#define CMD_ID_MEDIA_STATUS_RPT 0X01 -#define CMD_ID_KEEP_ALIVE 0X03 -#define CMD_ID_DISCONNECT_DECISION 0X04 -#define CMD_ID_AP_OFFLOAD 0X08 -#define CMD_ID_BCN_RSVDPAGE 0X09 -#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A -#define CMD_ID_SET_PWR_MODE 0X00 -#define CMD_ID_PS_TUNING_PARA 0X01 -#define CMD_ID_PS_TUNING_PARA_II 0X02 -#define CMD_ID_PS_LPS_PARA 0X03 -#define CMD_ID_P2P_PS_OFFLOAD 0X04 -#define CMD_ID_PS_SCAN_EN 0X05 -#define CMD_ID_SAP_PS 0X06 -#define CMD_ID_INACTIVE_PS 0X07 -#define CMD_ID_MACID_CFG 0X00 -#define CMD_ID_TXBF 0X01 -#define CMD_ID_RSSI_SETTING 0X02 -#define CMD_ID_AP_REQ_TXRPT 0X03 -#define CMD_ID_INIT_RATE_COLLECTION 0X04 -#define CMD_ID_IQK_OFFLOAD 0X05 -#define CMD_ID_MACID_CFG_3SS 0X06 -#define CMD_ID_RA_PARA_ADJUST 0X07 -#define CMD_ID_WWLAN 0X00 -#define CMD_ID_REMOTE_WAKE_CTRL 0X01 -#define CMD_ID_AOAC_GLOBAL_INFO 0X02 -#define CMD_ID_AOAC_RSVD_PAGE 0X03 -#define CMD_ID_AOAC_RSVD_PAGE2 0X04 -#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05 -#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07 -#define CMD_ID_AOAC_RSVD_PAGE3 0X08 +#define CMD_ID_ORIGINAL_H2C 0X00 +#define CMD_ID_H2C2H_LB 0X0 +#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06 +#define CMD_ID_RSVD_PAGE 0X0 +#define CMD_ID_MEDIA_STATUS_RPT 0X01 +#define CMD_ID_KEEP_ALIVE 0X03 +#define CMD_ID_DISCONNECT_DECISION 0X04 +#define CMD_ID_AP_OFFLOAD 0X08 +#define CMD_ID_BCN_RSVDPAGE 0X09 +#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A +#define CMD_ID_SINGLE_CHANNELSWITCH 0X1C +#define CMD_ID_SINGLE_CHANNELSWITCH_V2 0X1D +#define CMD_ID_SET_PWR_MODE 0X00 +#define CMD_ID_PS_TUNING_PARA 0X01 +#define CMD_ID_PS_TUNING_PARA_II 0X02 +#define CMD_ID_PS_LPS_PARA 0X03 +#define CMD_ID_P2P_PS_OFFLOAD 0X04 +#define CMD_ID_PS_SCAN_EN 0X05 +#define CMD_ID_SAP_PS 0X06 +#define CMD_ID_INACTIVE_PS 0X07 +#define CMD_ID_MACID_CFG 0X00 +#define CMD_ID_TXBF 0X01 +#define CMD_ID_RSSI_SETTING 0X02 +#define CMD_ID_AP_REQ_TXRPT 0X03 +#define CMD_ID_INIT_RATE_COLLECTION 0X04 +#define CMD_ID_IQK_OFFLOAD 0X05 +#define CMD_ID_MACID_CFG_3SS 0X06 +#define CMD_ID_RA_PARA_ADJUST 0X07 +#define CMD_ID_WWLAN 0X00 +#define CMD_ID_REMOTE_WAKE_CTRL 0X01 +#define CMD_ID_AOAC_GLOBAL_INFO 0X02 +#define CMD_ID_AOAC_RSVD_PAGE 0X03 +#define CMD_ID_AOAC_RSVD_PAGE2 0X04 +#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05 +#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07 +#define CMD_ID_AOAC_RSVD_PAGE3 0X08 +#define CMD_ID_DBG_MSG_CTRL 0X1E #define CLASS_ORIGINAL_H2C 0X00 #define CLASS_H2C2H_LB 0X07 #define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04 @@ -59,6 +62,8 @@ #define CLASS_AP_OFFLOAD 0X0 #define CLASS_BCN_RSVDPAGE 0X0 #define CLASS_PROBE_RSP_RSVDPAGE 0X0 +#define CLASS_SINGLE_CHANNELSWITCH 0X0 +#define CLASS_SINGLE_CHANNELSWITCH_V2 0X0 #define CLASS_SET_PWR_MODE 0X01 #define CLASS_PS_TUNING_PARA 0X01 #define CLASS_PS_TUNING_PARA_II 0X01 @@ -83,811 +88,1574 @@ #define CLASS_D0_SCAN_OFFLOAD_INFO 0X04 #define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04 #define CLASS_AOAC_RSVD_PAGE3 0X04 -#define ORIGINAL_H2C_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define ORIGINAL_H2C_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define ORIGINAL_H2C_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define ORIGINAL_H2C_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define ORIGINAL_H2C_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define ORIGINAL_H2C_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define H2C2H_LB_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define H2C2H_LB_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define H2C2H_LB_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define H2C2H_LB_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define H2C2H_LB_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define H2C2H_LB_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define H2C2H_LB_GET_SEQ(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define H2C2H_LB_SET_SEQ(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define H2C2H_LB_SET_SEQ_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define H2C2H_LB_GET_PAYLOAD1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 16) -#define H2C2H_LB_SET_PAYLOAD1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 16, __Value) -#define H2C2H_LB_SET_PAYLOAD1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 16, __Value) -#define H2C2H_LB_GET_PAYLOAD2(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 32) -#define H2C2H_LB_SET_PAYLOAD2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 32, __Value) -#define H2C2H_LB_SET_PAYLOAD2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 32, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 17) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 17, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 17, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RSVD_PAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define RSVD_PAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define RSVD_PAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define RSVD_PAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define RSVD_PAGE_GET_LOC_PROBE_RSP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define RSVD_PAGE_SET_LOC_PROBE_RSP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define RSVD_PAGE_SET_LOC_PROBE_RSP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define RSVD_PAGE_GET_LOC_PS_POLL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define RSVD_PAGE_SET_LOC_PS_POLL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define RSVD_PAGE_SET_LOC_PS_POLL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define RSVD_PAGE_GET_LOC_NULL_DATA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define RSVD_PAGE_SET_LOC_NULL_DATA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define RSVD_PAGE_SET_LOC_NULL_DATA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define RSVD_PAGE_GET_LOC_QOS_NULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define RSVD_PAGE_SET_LOC_QOS_NULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RSVD_PAGE_SET_LOC_QOS_NULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define RSVD_PAGE_SET_LOC_BT_QOS_NULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define RSVD_PAGE_GET_LOC_CTS2SELF(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define RSVD_PAGE_SET_LOC_CTS2SELF(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define RSVD_PAGE_SET_LOC_CTS2SELF_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) -#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) -#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define MEDIA_STATUS_RPT_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define MEDIA_STATUS_RPT_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define MEDIA_STATUS_RPT_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define MEDIA_STATUS_RPT_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define MEDIA_STATUS_RPT_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define MEDIA_STATUS_RPT_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define MEDIA_STATUS_RPT_GET_OP_MODE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define MEDIA_STATUS_RPT_SET_OP_MODE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define MEDIA_STATUS_RPT_SET_OP_MODE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define MEDIA_STATUS_RPT_GET_MACID_IN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define MEDIA_STATUS_RPT_SET_MACID_IN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define MEDIA_STATUS_RPT_SET_MACID_IN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define MEDIA_STATUS_RPT_GET_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define MEDIA_STATUS_RPT_SET_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define MEDIA_STATUS_RPT_SET_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define MEDIA_STATUS_RPT_GET_MACID_END(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define MEDIA_STATUS_RPT_SET_MACID_END(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define MEDIA_STATUS_RPT_SET_MACID_END_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define KEEP_ALIVE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define KEEP_ALIVE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define KEEP_ALIVE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define KEEP_ALIVE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define KEEP_ALIVE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define KEEP_ALIVE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define KEEP_ALIVE_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define KEEP_ALIVE_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define KEEP_ALIVE_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define KEEP_ALIVE_SET_ADOPT_USER_SETTING_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define KEEP_ALIVE_GET_PKT_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define KEEP_ALIVE_SET_PKT_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define KEEP_ALIVE_SET_PKT_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define DISCONNECT_DECISION_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define DISCONNECT_DECISION_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define DISCONNECT_DECISION_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define DISCONNECT_DECISION_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define DISCONNECT_DECISION_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define DISCONNECT_DECISION_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define DISCONNECT_DECISION_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define DISCONNECT_DECISION_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define DISCONNECT_DECISION_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define DISCONNECT_DECISION_GET_DISCONNECT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define DISCONNECT_DECISION_SET_DISCONNECT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define DISCONNECT_DECISION_SET_DISCONNECT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define DISCONNECT_DECISION_SET_TRY_PKT_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AP_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define AP_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AP_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AP_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AP_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AP_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AP_OFFLOAD_GET_ON(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define AP_OFFLOAD_SET_ON(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define AP_OFFLOAD_SET_ON_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define AP_OFFLOAD_GET_LINKED(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define AP_OFFLOAD_SET_LINKED(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define AP_OFFLOAD_SET_LINKED_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define AP_OFFLOAD_GET_EN_AUTO_WAKE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define AP_OFFLOAD_SET_EN_AUTO_WAKE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define AP_OFFLOAD_SET_EN_AUTO_WAKE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define AP_OFFLOAD_GET_WAKE_FLAG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) -#define AP_OFFLOAD_SET_WAKE_FLAG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) -#define AP_OFFLOAD_SET_WAKE_FLAG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 1) -#define AP_OFFLOAD_SET_HIDDEN_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 1, __Value) -#define AP_OFFLOAD_SET_HIDDEN_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 17, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 17, 1, __Value) -#define AP_OFFLOAD_SET_HIDDEN_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 17, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 18, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 18, 1, __Value) -#define AP_OFFLOAD_SET_HIDDEN_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 18, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 19, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 19, 1, __Value) -#define AP_OFFLOAD_SET_HIDDEN_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 19, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 20, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 20, 1, __Value) -#define AP_OFFLOAD_SET_HIDDEN_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 20, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 1) -#define AP_OFFLOAD_SET_DENYANY_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 1, __Value) -#define AP_OFFLOAD_SET_DENYANY_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 25, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 25, 1, __Value) -#define AP_OFFLOAD_SET_DENYANY_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 25, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 26, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 26, 1, __Value) -#define AP_OFFLOAD_SET_DENYANY_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 26, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 27, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 27, 1, __Value) -#define AP_OFFLOAD_SET_DENYANY_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 27, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 28, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 28, 1, __Value) -#define AP_OFFLOAD_SET_DENYANY_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 28, 1, __Value) -#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AP_OFFLOAD_SET_WAIT_TBTT_CNT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AP_OFFLOAD_GET_WAKE_TIMEOUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define AP_OFFLOAD_SET_WAKE_TIMEOUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define AP_OFFLOAD_SET_WAKE_TIMEOUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define AP_OFFLOAD_GET_LEN_IV_PAIR(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define AP_OFFLOAD_SET_LEN_IV_PAIR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define AP_OFFLOAD_SET_LEN_IV_PAIR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define AP_OFFLOAD_GET_LEN_IV_GRP(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) -#define AP_OFFLOAD_SET_LEN_IV_GRP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) -#define AP_OFFLOAD_SET_LEN_IV_GRP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define BCN_RSVDPAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define BCN_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define BCN_RSVDPAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define BCN_RSVDPAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define BCN_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define BCN_RSVDPAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define BCN_RSVDPAGE_GET_LOC_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define BCN_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define BCN_RSVDPAGE_SET_LOC_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define BCN_RSVDPAGE_SET_LOC_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define BCN_RSVDPAGE_SET_LOC_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define BCN_RSVDPAGE_SET_LOC_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define BCN_RSVDPAGE_SET_LOC_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PROBE_RSP_RSVDPAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PROBE_RSP_RSVDPAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define PROBE_RSP_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PROBE_RSP_RSVDPAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define SET_PWR_MODE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define SET_PWR_MODE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define SET_PWR_MODE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define SET_PWR_MODE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define SET_PWR_MODE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define SET_PWR_MODE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define SET_PWR_MODE_GET_MODE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 7) -#define SET_PWR_MODE_SET_MODE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 7, __Value) -#define SET_PWR_MODE_SET_MODE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 7, __Value) -#define SET_PWR_MODE_GET_CLK_REQUEST(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) -#define SET_PWR_MODE_SET_CLK_REQUEST(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) -#define SET_PWR_MODE_SET_CLK_REQUEST_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) -#define SET_PWR_MODE_GET_RLBM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 4) -#define SET_PWR_MODE_SET_RLBM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 4, __Value) -#define SET_PWR_MODE_SET_RLBM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 4, __Value) -#define SET_PWR_MODE_GET_SMART_PS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 20, 4) -#define SET_PWR_MODE_SET_SMART_PS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 20, 4, __Value) -#define SET_PWR_MODE_SET_SMART_PS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 20, 4, __Value) -#define SET_PWR_MODE_GET_AWAKE_INTERVAL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define SET_PWR_MODE_SET_AWAKE_INTERVAL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define SET_PWR_MODE_SET_AWAKE_INTERVAL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 1) -#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 1, __Value) -#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 1, __Value) -#define SET_PWR_MODE_GET_BCN_EARLY_RPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 2, 1) -#define SET_PWR_MODE_SET_BCN_EARLY_RPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 2, 1, __Value) -#define SET_PWR_MODE_SET_BCN_EARLY_RPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 2, 1, __Value) -#define SET_PWR_MODE_GET_PORT_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 5, 3) -#define SET_PWR_MODE_SET_PORT_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 5, 3, __Value) -#define SET_PWR_MODE_SET_PORT_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 5, 3, __Value) -#define SET_PWR_MODE_GET_PWR_STATE(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define SET_PWR_MODE_SET_PWR_STATE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define SET_PWR_MODE_SET_PWR_STATE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 1) -#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 1, __Value) -#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 1, __Value) -#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 17, 1) -#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 17, 1, __Value) -#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 17, 1, __Value) -#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 18, 1) -#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 18, 1, __Value) -#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 18, 1, __Value) -#define SET_PWR_MODE_GET_PROTECT_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 19, 1) -#define SET_PWR_MODE_SET_PROTECT_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 19, 1, __Value) -#define SET_PWR_MODE_SET_PROTECT_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 19, 1, __Value) -#define SET_PWR_MODE_GET_SILENCE_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 20, 1) -#define SET_PWR_MODE_SET_SILENCE_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 20, 1, __Value) -#define SET_PWR_MODE_SET_SILENCE_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 20, 1, __Value) -#define SET_PWR_MODE_GET_FAST_BT_CONNECT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 21, 1) -#define SET_PWR_MODE_SET_FAST_BT_CONNECT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 21, 1, __Value) -#define SET_PWR_MODE_SET_FAST_BT_CONNECT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 21, 1, __Value) -#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 22, 1) -#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 22, 1, __Value) -#define SET_PWR_MODE_SET_TWO_ANTENNA_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 22, 1, __Value) -#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 1) -#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 1, __Value) -#define SET_PWR_MODE_SET_ADOPT_USER_SETTING_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 1, __Value) -#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 25, 3) -#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 25, 3, __Value) -#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 25, 3, __Value) -#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 28, 4) -#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 28, 4, __Value) -#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 28, 4, __Value) -#define PS_TUNING_PARA_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define PS_TUNING_PARA_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_TUNING_PARA_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_TUNING_PARA_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define PS_TUNING_PARA_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_TUNING_PARA_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 7) -#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 7, __Value) -#define PS_TUNING_PARA_SET_BCN_TO_LIMIT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 7, __Value) -#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) -#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) -#define PS_TUNING_PARA_SET_DTIM_TIME_OUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) -#define PS_TUNING_PARA_GET_PS_TIME_OUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 4) -#define PS_TUNING_PARA_SET_PS_TIME_OUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 4, __Value) -#define PS_TUNING_PARA_SET_PS_TIME_OUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 4, __Value) -#define PS_TUNING_PARA_GET_ADOPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define PS_TUNING_PARA_SET_ADOPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define PS_TUNING_PARA_SET_ADOPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define PS_TUNING_PARA_II_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define PS_TUNING_PARA_II_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_TUNING_PARA_II_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_TUNING_PARA_II_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define PS_TUNING_PARA_II_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_TUNING_PARA_II_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 7) -#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 7, __Value) -#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 7, __Value) -#define PS_TUNING_PARA_II_GET_ADOPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) -#define PS_TUNING_PARA_II_SET_ADOPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) -#define PS_TUNING_PARA_II_SET_ADOPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) -#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define PS_LPS_PARA_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define PS_LPS_PARA_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_LPS_PARA_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_LPS_PARA_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define PS_LPS_PARA_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_LPS_PARA_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_LPS_PARA_GET_LPS_CONTROL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define PS_LPS_PARA_SET_LPS_CONTROL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define PS_LPS_PARA_SET_LPS_CONTROL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define P2P_PS_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define P2P_PS_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define P2P_PS_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define P2P_PS_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define P2P_PS_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define P2P_PS_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define P2P_PS_OFFLOAD_GET_ROLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define P2P_PS_OFFLOAD_SET_ROLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define P2P_PS_OFFLOAD_SET_ROLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define P2P_PS_OFFLOAD_GET_NOA0_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define P2P_PS_OFFLOAD_SET_NOA0_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define P2P_PS_OFFLOAD_SET_NOA0_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define P2P_PS_OFFLOAD_GET_NOA1_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) -#define P2P_PS_OFFLOAD_SET_NOA1_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) -#define P2P_PS_OFFLOAD_SET_NOA1_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) -#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 13, 1) -#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 13, 1, __Value) -#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 13, 1, __Value) -#define P2P_PS_OFFLOAD_GET_DISCOVERY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1) -#define P2P_PS_OFFLOAD_SET_DISCOVERY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value) -#define P2P_PS_OFFLOAD_SET_DISCOVERY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value) -#define PS_SCAN_EN_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define PS_SCAN_EN_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_SCAN_EN_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_SCAN_EN_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define PS_SCAN_EN_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_SCAN_EN_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_SCAN_EN_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define PS_SCAN_EN_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define PS_SCAN_EN_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define SAP_PS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define SAP_PS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define SAP_PS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define SAP_PS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define SAP_PS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define SAP_PS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define SAP_PS_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define SAP_PS_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define SAP_PS_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define SAP_PS_GET_EN_PS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define SAP_PS_SET_EN_PS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define SAP_PS_SET_EN_PS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define SAP_PS_GET_EN_LP_RX(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define SAP_PS_SET_EN_LP_RX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define SAP_PS_SET_EN_LP_RX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define SAP_PS_GET_MANUAL_32K(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define SAP_PS_SET_MANUAL_32K(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define SAP_PS_SET_MANUAL_32K_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define SAP_PS_GET_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define SAP_PS_SET_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define SAP_PS_SET_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define INACTIVE_PS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define INACTIVE_PS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define INACTIVE_PS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define INACTIVE_PS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define INACTIVE_PS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define INACTIVE_PS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define INACTIVE_PS_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define INACTIVE_PS_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define INACTIVE_PS_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define INACTIVE_PS_SET_IGNORE_PS_CONDITION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define INACTIVE_PS_GET_FREQUENCY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define INACTIVE_PS_SET_FREQUENCY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define INACTIVE_PS_SET_FREQUENCY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define INACTIVE_PS_GET_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define INACTIVE_PS_SET_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define INACTIVE_PS_SET_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define MACID_CFG_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define MACID_CFG_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define MACID_CFG_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define MACID_CFG_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define MACID_CFG_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define MACID_CFG_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define MACID_CFG_GET_MAC_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define MACID_CFG_SET_MAC_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define MACID_CFG_SET_MAC_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define MACID_CFG_GET_RATE_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 5) -#define MACID_CFG_SET_RATE_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 5, __Value) -#define MACID_CFG_SET_RATE_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 5, __Value) -#define MACID_CFG_GET_INIT_RATE_LV(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 21, 2) -#define MACID_CFG_SET_INIT_RATE_LV(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 21, 2, __Value) -#define MACID_CFG_SET_INIT_RATE_LV_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 21, 2, __Value) -#define MACID_CFG_GET_SGI(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 23, 1) -#define MACID_CFG_SET_SGI(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 23, 1, __Value) -#define MACID_CFG_SET_SGI_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 23, 1, __Value) -#define MACID_CFG_GET_BW(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 2) -#define MACID_CFG_SET_BW(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 2, __Value) -#define MACID_CFG_SET_BW_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 2, __Value) -#define MACID_CFG_GET_LDPC_CAP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 26, 1) -#define MACID_CFG_SET_LDPC_CAP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 26, 1, __Value) -#define MACID_CFG_SET_LDPC_CAP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 26, 1, __Value) -#define MACID_CFG_GET_NO_UPDATE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 27, 1) -#define MACID_CFG_SET_NO_UPDATE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 27, 1, __Value) -#define MACID_CFG_SET_NO_UPDATE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 27, 1, __Value) -#define MACID_CFG_GET_WHT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 28, 2) -#define MACID_CFG_SET_WHT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 28, 2, __Value) -#define MACID_CFG_SET_WHT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 28, 2, __Value) -#define MACID_CFG_GET_DISPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 30, 1) -#define MACID_CFG_SET_DISPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 30, 1, __Value) -#define MACID_CFG_SET_DISPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 30, 1, __Value) -#define MACID_CFG_GET_DISRA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 31, 1) -#define MACID_CFG_SET_DISRA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 31, 1, __Value) -#define MACID_CFG_SET_DISRA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 31, 1, __Value) -#define MACID_CFG_GET_RATE_MASK7_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define MACID_CFG_SET_RATE_MASK7_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define MACID_CFG_SET_RATE_MASK7_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define MACID_CFG_GET_RATE_MASK15_8(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define MACID_CFG_SET_RATE_MASK15_8(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define MACID_CFG_SET_RATE_MASK15_8_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define MACID_CFG_GET_RATE_MASK23_16(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define MACID_CFG_SET_RATE_MASK23_16(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define MACID_CFG_SET_RATE_MASK23_16_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define MACID_CFG_GET_RATE_MASK31_24(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) -#define MACID_CFG_SET_RATE_MASK31_24(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) -#define MACID_CFG_SET_RATE_MASK31_24_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define TXBF_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define TXBF_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define TXBF_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define TXBF_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define TXBF_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define TXBF_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define TXBF_GET_NDPA0_HEAD_PAGE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define TXBF_SET_NDPA0_HEAD_PAGE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define TXBF_SET_NDPA0_HEAD_PAGE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define TXBF_GET_NDPA1_HEAD_PAGE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define TXBF_SET_NDPA1_HEAD_PAGE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define TXBF_SET_NDPA1_HEAD_PAGE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define TXBF_GET_PERIOD_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define TXBF_SET_PERIOD_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define TXBF_SET_PERIOD_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define RSSI_SETTING_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define RSSI_SETTING_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define RSSI_SETTING_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define RSSI_SETTING_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define RSSI_SETTING_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define RSSI_SETTING_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define RSSI_SETTING_GET_MAC_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define RSSI_SETTING_SET_MAC_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define RSSI_SETTING_SET_MAC_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define RSSI_SETTING_GET_RSSI(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 7) -#define RSSI_SETTING_SET_RSSI(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 7, __Value) -#define RSSI_SETTING_SET_RSSI_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 7, __Value) -#define RSSI_SETTING_GET_RA_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define RSSI_SETTING_SET_RA_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RSSI_SETTING_SET_RA_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AP_REQ_TXRPT_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define AP_REQ_TXRPT_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AP_REQ_TXRPT_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AP_REQ_TXRPT_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AP_REQ_TXRPT_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AP_REQ_TXRPT_GET_STA1_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define AP_REQ_TXRPT_SET_STA1_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AP_REQ_TXRPT_GET_STA2_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define AP_REQ_TXRPT_SET_STA2_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 1) -#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 1, __Value) -#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 1, __Value) -#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 25, 1) -#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 25, 1, __Value) -#define AP_REQ_TXRPT_SET_RTY_CNT_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 25, 1, __Value) -#define INIT_RATE_COLLECTION_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define INIT_RATE_COLLECTION_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define INIT_RATE_COLLECTION_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define INIT_RATE_COLLECTION_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define INIT_RATE_COLLECTION_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define INIT_RATE_COLLECTION_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define INIT_RATE_COLLECTION_GET_STA1_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define INIT_RATE_COLLECTION_SET_STA1_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA1_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA2_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define INIT_RATE_COLLECTION_SET_STA2_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA2_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA3_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define INIT_RATE_COLLECTION_SET_STA3_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA3_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA4_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define INIT_RATE_COLLECTION_SET_STA4_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA4_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA5_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define INIT_RATE_COLLECTION_SET_STA5_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA5_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA6_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define INIT_RATE_COLLECTION_SET_STA6_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA6_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA7_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) -#define INIT_RATE_COLLECTION_SET_STA7_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA7_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define IQK_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define IQK_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define IQK_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define IQK_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define IQK_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define IQK_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define IQK_OFFLOAD_GET_CHANNEL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define IQK_OFFLOAD_SET_CHANNEL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define IQK_OFFLOAD_SET_CHANNEL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define IQK_OFFLOAD_GET_BWBAND(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define IQK_OFFLOAD_SET_BWBAND(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define IQK_OFFLOAD_SET_BWBAND_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define IQK_OFFLOAD_GET_EXTPALNA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define IQK_OFFLOAD_SET_EXTPALNA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define IQK_OFFLOAD_SET_EXTPALNA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define MACID_CFG_3SS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define MACID_CFG_3SS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define MACID_CFG_3SS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define MACID_CFG_3SS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define MACID_CFG_3SS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define MACID_CFG_3SS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define MACID_CFG_3SS_GET_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define MACID_CFG_3SS_SET_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define MACID_CFG_3SS_SET_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define MACID_CFG_3SS_GET_RATE_MASK_39_32(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define MACID_CFG_3SS_SET_RATE_MASK_39_32(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define MACID_CFG_3SS_SET_RATE_MASK_39_32_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define MACID_CFG_3SS_GET_RATE_MASK_47_40(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define MACID_CFG_3SS_SET_RATE_MASK_47_40(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define MACID_CFG_3SS_SET_RATE_MASK_47_40_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define RA_PARA_ADJUST_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define RA_PARA_ADJUST_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define RA_PARA_ADJUST_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define RA_PARA_ADJUST_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define RA_PARA_ADJUST_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define RA_PARA_ADJUST_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define RA_PARA_ADJUST_GET_MAC_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define RA_PARA_ADJUST_SET_MAC_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define RA_PARA_ADJUST_SET_MAC_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define RA_PARA_ADJUST_SET_PARAMETER_INDEX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define RA_PARA_ADJUST_GET_RATE_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define RA_PARA_ADJUST_SET_RATE_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define RA_PARA_ADJUST_SET_RATE_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define RA_PARA_ADJUST_GET_VALUE_BYTE0(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define RA_PARA_ADJUST_SET_VALUE_BYTE0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RA_PARA_ADJUST_SET_VALUE_BYTE0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RA_PARA_ADJUST_GET_VALUE_BYTE1(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define RA_PARA_ADJUST_SET_VALUE_BYTE1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define RA_PARA_ADJUST_SET_VALUE_BYTE1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define WWLAN_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define WWLAN_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define WWLAN_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define WWLAN_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define WWLAN_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define WWLAN_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define WWLAN_GET_FUNC_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define WWLAN_SET_FUNC_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define WWLAN_SET_FUNC_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define WWLAN_GET_PATTERM_MAT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define WWLAN_SET_PATTERM_MAT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define WWLAN_SET_PATTERM_MAT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define WWLAN_GET_MAGIC_PKT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define WWLAN_SET_MAGIC_PKT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define WWLAN_SET_MAGIC_PKT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define WWLAN_GET_UNICAST_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define WWLAN_SET_UNICAST_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define WWLAN_SET_UNICAST_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define WWLAN_GET_ALL_PKT_DROP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) -#define WWLAN_SET_ALL_PKT_DROP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) -#define WWLAN_SET_ALL_PKT_DROP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) -#define WWLAN_GET_GPIO_ACTIVE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 13, 1) -#define WWLAN_SET_GPIO_ACTIVE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 13, 1, __Value) -#define WWLAN_SET_GPIO_ACTIVE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 13, 1, __Value) -#define WWLAN_GET_REKEY_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1) -#define WWLAN_SET_REKEY_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value) -#define WWLAN_SET_REKEY_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value) -#define WWLAN_GET_DEAUTH_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) -#define WWLAN_SET_DEAUTH_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) -#define WWLAN_SET_DEAUTH_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) -#define WWLAN_GET_GPIO_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 7) -#define WWLAN_SET_GPIO_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 7, __Value) -#define WWLAN_SET_GPIO_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 7, __Value) -#define WWLAN_GET_DATAPIN_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 23, 1) -#define WWLAN_SET_DATAPIN_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 23, 1, __Value) -#define WWLAN_SET_DATAPIN_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 23, 1, __Value) -#define WWLAN_GET_GPIO_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define WWLAN_SET_GPIO_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define WWLAN_SET_GPIO_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define WWLAN_GET_GPIO_PLUS_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 1) -#define WWLAN_SET_GPIO_PLUS_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 1, __Value) -#define WWLAN_SET_GPIO_PLUS_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 1, __Value) -#define WWLAN_GET_GPIO_PULSE_COUNT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 1, 7) -#define WWLAN_SET_GPIO_PULSE_COUNT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 1, 7, __Value) -#define WWLAN_SET_GPIO_PULSE_COUNT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 1, 7, __Value) -#define WWLAN_GET_DISABLE_UPHY(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 1) -#define WWLAN_SET_DISABLE_UPHY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 1, __Value) -#define WWLAN_SET_DISABLE_UPHY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 1, __Value) -#define WWLAN_GET_HST2DEV_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 9, 1) -#define WWLAN_SET_HST2DEV_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 9, 1, __Value) -#define WWLAN_SET_HST2DEV_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 9, 1, __Value) -#define WWLAN_GET_GPIO_DURATION_MS(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 10, 1) -#define WWLAN_SET_GPIO_DURATION_MS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 10, 1, __Value) -#define WWLAN_SET_GPIO_DURATION_MS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 10, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define REMOTE_WAKE_CTRL_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define REMOTE_WAKE_CTRL_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define REMOTE_WAKE_CTRL_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define REMOTE_WAKE_CTRL_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define REMOTE_WAKE_CTRL_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_ARP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define REMOTE_WAKE_CTRL_SET_ARP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_ARP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_NDP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define REMOTE_WAKE_CTRL_SET_NDP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_NDP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_GTK_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define REMOTE_WAKE_CTRL_SET_GTK_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_GTK_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) -#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 13, 1) -#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 13, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 13, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1) -#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) -#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_FW_UNICAST_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 1) -#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 17, 1) -#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 17, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 17, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 18, 1) -#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 18, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 18, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 1) -#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_ARP_ACTION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 28, 1) -#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 28, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 28, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 29, 1) -#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 29, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 29, 1, __Value) -#define AOAC_GLOBAL_INFO_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define AOAC_GLOBAL_INFO_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_GLOBAL_INFO_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_GLOBAL_INFO_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AOAC_GLOBAL_INFO_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_GLOBAL_INFO_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define AOAC_RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AOAC_RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) -#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define AOAC_RSVD_PAGE2_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE2_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE2_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AOAC_RSVD_PAGE2_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE2_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define D0_SCAN_OFFLOAD_INFO_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE3_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define AOAC_RSVD_PAGE3_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE3_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE3_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AOAC_RSVD_PAGE3_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE3_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define CLASS_DBG_MSG_CTRL 0X07 +#define ORIGINAL_H2C_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define ORIGINAL_H2C_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define ORIGINAL_H2C_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define ORIGINAL_H2C_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define ORIGINAL_H2C_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define ORIGINAL_H2C_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define H2C2H_LB_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define H2C2H_LB_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define H2C2H_LB_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define H2C2H_LB_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define H2C2H_LB_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define H2C2H_LB_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define H2C2H_LB_GET_SEQ(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define H2C2H_LB_SET_SEQ(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define H2C2H_LB_SET_SEQ_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define H2C2H_LB_GET_PAYLOAD1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 16) +#define H2C2H_LB_SET_PAYLOAD1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 16, value) +#define H2C2H_LB_SET_PAYLOAD1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 16, value) +#define H2C2H_LB_GET_PAYLOAD2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 32) +#define H2C2H_LB_SET_PAYLOAD2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 32, value) +#define H2C2H_LB_SET_PAYLOAD2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 32, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 17) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 17, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 17, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define RSVD_PAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define RSVD_PAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define RSVD_PAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define RSVD_PAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define RSVD_PAGE_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define RSVD_PAGE_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define RSVD_PAGE_GET_LOC_PROBE_RSP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define RSVD_PAGE_SET_LOC_PROBE_RSP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define RSVD_PAGE_SET_LOC_PROBE_RSP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define RSVD_PAGE_GET_LOC_PS_POLL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define RSVD_PAGE_SET_LOC_PS_POLL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define RSVD_PAGE_SET_LOC_PS_POLL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define RSVD_PAGE_GET_LOC_NULL_DATA(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define RSVD_PAGE_SET_LOC_NULL_DATA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define RSVD_PAGE_SET_LOC_NULL_DATA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define RSVD_PAGE_GET_LOC_QOS_NULL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define RSVD_PAGE_SET_LOC_QOS_NULL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define RSVD_PAGE_SET_LOC_QOS_NULL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define RSVD_PAGE_SET_LOC_BT_QOS_NULL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define RSVD_PAGE_GET_LOC_CTS2SELF(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define RSVD_PAGE_SET_LOC_CTS2SELF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define RSVD_PAGE_SET_LOC_CTS2SELF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8) +#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value) +#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value) +#define MEDIA_STATUS_RPT_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define MEDIA_STATUS_RPT_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define MEDIA_STATUS_RPT_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define MEDIA_STATUS_RPT_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define MEDIA_STATUS_RPT_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define MEDIA_STATUS_RPT_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define MEDIA_STATUS_RPT_GET_OP_MODE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define MEDIA_STATUS_RPT_SET_OP_MODE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define MEDIA_STATUS_RPT_GET_MACID_IN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define MEDIA_STATUS_RPT_SET_MACID_IN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define MEDIA_STATUS_RPT_SET_MACID_IN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define MEDIA_STATUS_RPT_GET_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define MEDIA_STATUS_RPT_SET_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define MEDIA_STATUS_RPT_GET_MACID_END(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define MEDIA_STATUS_RPT_SET_MACID_END(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define MEDIA_STATUS_RPT_SET_MACID_END_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define KEEP_ALIVE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define KEEP_ALIVE_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define KEEP_ALIVE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define KEEP_ALIVE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define KEEP_ALIVE_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define KEEP_ALIVE_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define KEEP_ALIVE_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define KEEP_ALIVE_SET_ENABLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define KEEP_ALIVE_SET_ENABLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define KEEP_ALIVE_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define KEEP_ALIVE_GET_PKT_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define KEEP_ALIVE_SET_PKT_TYPE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define KEEP_ALIVE_SET_PKT_TYPE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define DISCONNECT_DECISION_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define DISCONNECT_DECISION_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define DISCONNECT_DECISION_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define DISCONNECT_DECISION_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define DISCONNECT_DECISION_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define DISCONNECT_DECISION_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define DISCONNECT_DECISION_GET_ENABLE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define DISCONNECT_DECISION_SET_ENABLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define DISCONNECT_DECISION_SET_ENABLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN_NO_CLR(h2c_pkt, \ + value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define DISCONNECT_DECISION_GET_DISCONNECT_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define DISCONNECT_DECISION_SET_DISCONNECT_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define DISCONNECT_DECISION_SET_DISCONNECT_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD_NO_CLR(h2c_pkt, \ + value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define DISCONNECT_DECISION_SET_TRY_PKT_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT_NO_CLR(h2c_pkt, \ + value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AP_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define AP_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AP_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AP_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define AP_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AP_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AP_OFFLOAD_GET_ON(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define AP_OFFLOAD_SET_ON(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define AP_OFFLOAD_SET_ON_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define AP_OFFLOAD_GET_LINKED(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define AP_OFFLOAD_SET_LINKED(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define AP_OFFLOAD_SET_LINKED_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define AP_OFFLOAD_GET_EN_AUTO_WAKE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define AP_OFFLOAD_SET_EN_AUTO_WAKE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define AP_OFFLOAD_SET_EN_AUTO_WAKE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define AP_OFFLOAD_GET_WAKE_FLAG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1) +#define AP_OFFLOAD_SET_WAKE_FLAG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value) +#define AP_OFFLOAD_SET_WAKE_FLAG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_ROOT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 1) +#define AP_OFFLOAD_SET_HIDDEN_ROOT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 1, value) +#define AP_OFFLOAD_SET_HIDDEN_ROOT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 17, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 17, 1, value) +#define AP_OFFLOAD_SET_HIDDEN_VAP1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 17, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 18, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 1, value) +#define AP_OFFLOAD_SET_HIDDEN_VAP2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP3(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 19, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 19, 1, value) +#define AP_OFFLOAD_SET_HIDDEN_VAP3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 19, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP4(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 20, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 1, value) +#define AP_OFFLOAD_SET_HIDDEN_VAP4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 1, value) +#define AP_OFFLOAD_GET_DENYANY_ROOT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 1) +#define AP_OFFLOAD_SET_DENYANY_ROOT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value) +#define AP_OFFLOAD_SET_DENYANY_ROOT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 25, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 25, 1, value) +#define AP_OFFLOAD_SET_DENYANY_VAP1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 25, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 26, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 26, 1, value) +#define AP_OFFLOAD_SET_DENYANY_VAP2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 26, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 27, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 27, 1, value) +#define AP_OFFLOAD_SET_DENYANY_VAP3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 27, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 28, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 1, value) +#define AP_OFFLOAD_SET_DENYANY_VAP4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 1, value) +#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AP_OFFLOAD_SET_WAIT_TBTT_CNT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AP_OFFLOAD_GET_WAKE_TIMEOUT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define AP_OFFLOAD_SET_WAKE_TIMEOUT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define AP_OFFLOAD_SET_WAKE_TIMEOUT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define AP_OFFLOAD_GET_LEN_IV_PAIR(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define AP_OFFLOAD_SET_LEN_IV_PAIR(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define AP_OFFLOAD_SET_LEN_IV_PAIR_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define AP_OFFLOAD_GET_LEN_IV_GRP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8) +#define AP_OFFLOAD_SET_LEN_IV_GRP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value) +#define AP_OFFLOAD_SET_LEN_IV_GRP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value) +#define BCN_RSVDPAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define BCN_RSVDPAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define BCN_RSVDPAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define BCN_RSVDPAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define BCN_RSVDPAGE_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define BCN_RSVDPAGE_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define BCN_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define BCN_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define BCN_RSVDPAGE_SET_LOC_ROOT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define BCN_RSVDPAGE_SET_LOC_VAP1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define BCN_RSVDPAGE_SET_LOC_VAP2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define BCN_RSVDPAGE_SET_LOC_VAP3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define BCN_RSVDPAGE_SET_LOC_VAP4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PROBE_RSP_RSVDPAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PROBE_RSP_RSVDPAGE_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define PROBE_RSP_RSVDPAGE_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PROBE_RSP_RSVDPAGE_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define SINGLE_CHANNELSWITCH_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define SINGLE_CHANNELSWITCH_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SINGLE_CHANNELSWITCH_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SINGLE_CHANNELSWITCH_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define SINGLE_CHANNELSWITCH_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SINGLE_CHANNELSWITCH_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SINGLE_CHANNELSWITCH_GET_CHANNEL_NUM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define SINGLE_CHANNELSWITCH_GET_BW(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 2) +#define SINGLE_CHANNELSWITCH_SET_BW(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 2, value) +#define SINGLE_CHANNELSWITCH_SET_BW_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 2, value) +#define SINGLE_CHANNELSWITCH_GET_BW40SC(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 18, 3) +#define SINGLE_CHANNELSWITCH_SET_BW40SC(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 3, value) +#define SINGLE_CHANNELSWITCH_SET_BW40SC_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 3, value) +#define SINGLE_CHANNELSWITCH_GET_BW80SC(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 21, 3) +#define SINGLE_CHANNELSWITCH_SET_BW80SC(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 21, 3, value) +#define SINGLE_CHANNELSWITCH_SET_BW80SC_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 21, 3, value) +#define SINGLE_CHANNELSWITCH_GET_RFE_TYPE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 4) +#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 4, value) +#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 4, value) +#define SINGLE_CHANNELSWITCH_V2_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SINGLE_CHANNELSWITCH_V2_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define SINGLE_CHANNELSWITCH_V2_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SINGLE_CHANNELSWITCH_V2_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SINGLE_CHANNELSWITCH_V2_GET_CENTRAL_CH(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define SINGLE_CHANNELSWITCH_V2_GET_PRIMARY_CH_IDX(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4) +#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value) +#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value) +#define SINGLE_CHANNELSWITCH_V2_GET_BW(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 20, 4) +#define SINGLE_CHANNELSWITCH_V2_SET_BW(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 4, value) +#define SINGLE_CHANNELSWITCH_V2_SET_BW_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 4, value) +#define SET_PWR_MODE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define SET_PWR_MODE_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SET_PWR_MODE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SET_PWR_MODE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define SET_PWR_MODE_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SET_PWR_MODE_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SET_PWR_MODE_GET_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7) +#define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value) +#define SET_PWR_MODE_SET_MODE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value) +#define SET_PWR_MODE_GET_CLK_REQUEST(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1) +#define SET_PWR_MODE_SET_CLK_REQUEST(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value) +#define SET_PWR_MODE_SET_CLK_REQUEST_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value) +#define SET_PWR_MODE_GET_RLBM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4) +#define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value) +#define SET_PWR_MODE_SET_RLBM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value) +#define SET_PWR_MODE_GET_SMART_PS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 20, 4) +#define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 4, value) +#define SET_PWR_MODE_SET_SMART_PS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 4, value) +#define SET_PWR_MODE_GET_AWAKE_INTERVAL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define SET_PWR_MODE_SET_AWAKE_INTERVAL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 1) +#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 1, value) +#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 1, value) +#define SET_PWR_MODE_GET_BCN_EARLY_RPT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 2, 1) +#define SET_PWR_MODE_SET_BCN_EARLY_RPT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 2, 1, value) +#define SET_PWR_MODE_SET_BCN_EARLY_RPT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 2, 1, value) +#define SET_PWR_MODE_GET_PORT_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 5, 3) +#define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 5, 3, value) +#define SET_PWR_MODE_SET_PORT_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 5, 3, value) +#define SET_PWR_MODE_GET_PWR_STATE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define SET_PWR_MODE_SET_PWR_STATE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 1) +#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 1, value) +#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 1, value) +#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 17, 1) +#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 17, 1, value) +#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 17, 1, value) +#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 18, 1) +#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 18, 1, value) +#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 18, 1, value) +#define SET_PWR_MODE_GET_PROTECT_BCN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 19, 1) +#define SET_PWR_MODE_SET_PROTECT_BCN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 19, 1, value) +#define SET_PWR_MODE_SET_PROTECT_BCN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 19, 1, value) +#define SET_PWR_MODE_GET_SILENCE_PERIOD(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 20, 1) +#define SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 20, 1, value) +#define SET_PWR_MODE_SET_SILENCE_PERIOD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 20, 1, value) +#define SET_PWR_MODE_GET_FAST_BT_CONNECT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 21, 1) +#define SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 21, 1, value) +#define SET_PWR_MODE_SET_FAST_BT_CONNECT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 21, 1, value) +#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 22, 1) +#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 22, 1, value) +#define SET_PWR_MODE_SET_TWO_ANTENNA_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 22, 1, value) +#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 24, 1) +#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 1, value) +#define SET_PWR_MODE_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 1, value) +#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 25, 3) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 25, 3, value) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 25, 3, value) +#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 28, 4) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 28, 4, value) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 28, 4, value) +#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_TUNING_PARA_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_TUNING_PARA_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define PS_TUNING_PARA_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_TUNING_PARA_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7) +#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value) +#define PS_TUNING_PARA_SET_BCN_TO_LIMIT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value) +#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1) +#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value) +#define PS_TUNING_PARA_SET_DTIM_TIME_OUT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value) +#define PS_TUNING_PARA_GET_PS_TIME_OUT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4) +#define PS_TUNING_PARA_SET_PS_TIME_OUT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value) +#define PS_TUNING_PARA_SET_PS_TIME_OUT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value) +#define PS_TUNING_PARA_GET_ADOPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define PS_TUNING_PARA_SET_ADOPT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define PS_TUNING_PARA_SET_ADOPT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define PS_TUNING_PARA_II_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define PS_TUNING_PARA_II_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_TUNING_PARA_II_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_TUNING_PARA_II_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define PS_TUNING_PARA_II_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_TUNING_PARA_II_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7) +#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value) +#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value) +#define PS_TUNING_PARA_II_GET_ADOPT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1) +#define PS_TUNING_PARA_II_SET_ADOPT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value) +#define PS_TUNING_PARA_II_SET_ADOPT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value) +#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define PS_LPS_PARA_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define PS_LPS_PARA_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_LPS_PARA_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_LPS_PARA_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define PS_LPS_PARA_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_LPS_PARA_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_LPS_PARA_GET_LPS_CONTROL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define PS_LPS_PARA_SET_LPS_CONTROL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define PS_LPS_PARA_SET_LPS_CONTROL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define P2P_PS_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define P2P_PS_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define P2P_PS_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define P2P_PS_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define P2P_PS_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define P2P_PS_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define P2P_PS_OFFLOAD_GET_ROLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define P2P_PS_OFFLOAD_SET_ROLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define P2P_PS_OFFLOAD_SET_ROLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define P2P_PS_OFFLOAD_GET_NOA0_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define P2P_PS_OFFLOAD_SET_NOA0_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define P2P_PS_OFFLOAD_SET_NOA0_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define P2P_PS_OFFLOAD_GET_NOA1_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1) +#define P2P_PS_OFFLOAD_SET_NOA1_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value) +#define P2P_PS_OFFLOAD_SET_NOA1_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value) +#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1) +#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value) +#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value) +#define P2P_PS_OFFLOAD_GET_DISCOVERY(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1) +#define P2P_PS_OFFLOAD_SET_DISCOVERY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value) +#define P2P_PS_OFFLOAD_SET_DISCOVERY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value) +#define PS_SCAN_EN_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define PS_SCAN_EN_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_SCAN_EN_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_SCAN_EN_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define PS_SCAN_EN_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_SCAN_EN_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_SCAN_EN_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define PS_SCAN_EN_SET_ENABLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define PS_SCAN_EN_SET_ENABLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define SAP_PS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define SAP_PS_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SAP_PS_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SAP_PS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define SAP_PS_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SAP_PS_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SAP_PS_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define SAP_PS_SET_ENABLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define SAP_PS_SET_ENABLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define SAP_PS_GET_EN_PS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define SAP_PS_SET_EN_PS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define SAP_PS_SET_EN_PS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define SAP_PS_GET_EN_LP_RX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define SAP_PS_SET_EN_LP_RX(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define SAP_PS_SET_EN_LP_RX_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define SAP_PS_GET_MANUAL_32K(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define SAP_PS_SET_MANUAL_32K(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define SAP_PS_SET_MANUAL_32K_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define SAP_PS_GET_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define SAP_PS_SET_DURATION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define SAP_PS_SET_DURATION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define INACTIVE_PS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define INACTIVE_PS_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define INACTIVE_PS_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define INACTIVE_PS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define INACTIVE_PS_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define INACTIVE_PS_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define INACTIVE_PS_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define INACTIVE_PS_SET_ENABLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define INACTIVE_PS_SET_ENABLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define INACTIVE_PS_SET_IGNORE_PS_CONDITION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define INACTIVE_PS_GET_FREQUENCY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define INACTIVE_PS_SET_FREQUENCY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define INACTIVE_PS_SET_FREQUENCY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define INACTIVE_PS_GET_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define INACTIVE_PS_SET_DURATION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define INACTIVE_PS_SET_DURATION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define MACID_CFG_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define MACID_CFG_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define MACID_CFG_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define MACID_CFG_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define MACID_CFG_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define MACID_CFG_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define MACID_CFG_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define MACID_CFG_SET_MAC_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define MACID_CFG_SET_MAC_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define MACID_CFG_GET_RATE_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 5) +#define MACID_CFG_SET_RATE_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 5, value) +#define MACID_CFG_SET_RATE_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 5, value) +#define MACID_CFG_GET_INIT_RATE_LV(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 21, 2) +#define MACID_CFG_SET_INIT_RATE_LV(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 21, 2, value) +#define MACID_CFG_SET_INIT_RATE_LV_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 21, 2, value) +#define MACID_CFG_GET_SGI(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 23, 1) +#define MACID_CFG_SET_SGI(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 23, 1, value) +#define MACID_CFG_SET_SGI_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 23, 1, value) +#define MACID_CFG_GET_BW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 2) +#define MACID_CFG_SET_BW(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 2, value) +#define MACID_CFG_SET_BW_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 2, value) +#define MACID_CFG_GET_LDPC_CAP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 26, 1) +#define MACID_CFG_SET_LDPC_CAP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 26, 1, value) +#define MACID_CFG_SET_LDPC_CAP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 26, 1, value) +#define MACID_CFG_GET_NO_UPDATE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 27, 1) +#define MACID_CFG_SET_NO_UPDATE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 27, 1, value) +#define MACID_CFG_SET_NO_UPDATE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 27, 1, value) +#define MACID_CFG_GET_WHT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 28, 2) +#define MACID_CFG_SET_WHT_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 2, value) +#define MACID_CFG_SET_WHT_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 2, value) +#define MACID_CFG_GET_DISPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 30, 1) +#define MACID_CFG_SET_DISPT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 30, 1, value) +#define MACID_CFG_SET_DISPT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 30, 1, value) +#define MACID_CFG_GET_DISRA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 31, 1) +#define MACID_CFG_SET_DISRA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 31, 1, value) +#define MACID_CFG_SET_DISRA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 31, 1, value) +#define MACID_CFG_GET_RATE_MASK7_0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define MACID_CFG_SET_RATE_MASK7_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define MACID_CFG_SET_RATE_MASK7_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define MACID_CFG_GET_RATE_MASK15_8(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define MACID_CFG_SET_RATE_MASK15_8(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define MACID_CFG_SET_RATE_MASK15_8_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define MACID_CFG_GET_RATE_MASK23_16(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define MACID_CFG_SET_RATE_MASK23_16(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define MACID_CFG_SET_RATE_MASK23_16_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define MACID_CFG_GET_RATE_MASK31_24(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8) +#define MACID_CFG_SET_RATE_MASK31_24(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value) +#define MACID_CFG_SET_RATE_MASK31_24_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value) +#define TXBF_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define TXBF_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define TXBF_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define TXBF_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define TXBF_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define TXBF_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define TXBF_GET_NDPA0_HEAD_PAGE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define TXBF_SET_NDPA0_HEAD_PAGE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define TXBF_SET_NDPA0_HEAD_PAGE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define TXBF_GET_NDPA1_HEAD_PAGE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define TXBF_SET_NDPA1_HEAD_PAGE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define TXBF_SET_NDPA1_HEAD_PAGE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define TXBF_GET_PERIOD_0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define TXBF_SET_PERIOD_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define TXBF_SET_PERIOD_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define RSSI_SETTING_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define RSSI_SETTING_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define RSSI_SETTING_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define RSSI_SETTING_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define RSSI_SETTING_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define RSSI_SETTING_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define RSSI_SETTING_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define RSSI_SETTING_SET_MAC_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define RSSI_SETTING_SET_MAC_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define RSSI_SETTING_GET_RSSI(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 7) +#define RSSI_SETTING_SET_RSSI(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 7, value) +#define RSSI_SETTING_SET_RSSI_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 7, value) +#define RSSI_SETTING_GET_RA_INFO(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define RSSI_SETTING_SET_RA_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define RSSI_SETTING_SET_RA_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AP_REQ_TXRPT_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define AP_REQ_TXRPT_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AP_REQ_TXRPT_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define AP_REQ_TXRPT_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AP_REQ_TXRPT_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AP_REQ_TXRPT_GET_STA1_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define AP_REQ_TXRPT_SET_STA1_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AP_REQ_TXRPT_GET_STA2_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define AP_REQ_TXRPT_SET_STA2_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 1) +#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value) +#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value) +#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 25, 1) +#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 25, 1, value) +#define AP_REQ_TXRPT_SET_RTY_CNT_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 25, 1, value) +#define INIT_RATE_COLLECTION_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define INIT_RATE_COLLECTION_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define INIT_RATE_COLLECTION_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define INIT_RATE_COLLECTION_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define INIT_RATE_COLLECTION_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define INIT_RATE_COLLECTION_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define INIT_RATE_COLLECTION_GET_STA1_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define INIT_RATE_COLLECTION_SET_STA1_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define INIT_RATE_COLLECTION_SET_STA1_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define INIT_RATE_COLLECTION_GET_STA2_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define INIT_RATE_COLLECTION_SET_STA2_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define INIT_RATE_COLLECTION_SET_STA2_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define INIT_RATE_COLLECTION_GET_STA3_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define INIT_RATE_COLLECTION_SET_STA3_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define INIT_RATE_COLLECTION_SET_STA3_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define INIT_RATE_COLLECTION_GET_STA4_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define INIT_RATE_COLLECTION_SET_STA4_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define INIT_RATE_COLLECTION_SET_STA4_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define INIT_RATE_COLLECTION_GET_STA5_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define INIT_RATE_COLLECTION_SET_STA5_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define INIT_RATE_COLLECTION_SET_STA5_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define INIT_RATE_COLLECTION_GET_STA6_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define INIT_RATE_COLLECTION_SET_STA6_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define INIT_RATE_COLLECTION_SET_STA6_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define INIT_RATE_COLLECTION_GET_STA7_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8) +#define INIT_RATE_COLLECTION_SET_STA7_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value) +#define INIT_RATE_COLLECTION_SET_STA7_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value) +#define IQK_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define IQK_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define IQK_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define IQK_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define IQK_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define IQK_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define IQK_OFFLOAD_GET_CHANNEL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define IQK_OFFLOAD_SET_CHANNEL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define IQK_OFFLOAD_SET_CHANNEL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define IQK_OFFLOAD_GET_BWBAND(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define IQK_OFFLOAD_SET_BWBAND(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define IQK_OFFLOAD_SET_BWBAND_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define IQK_OFFLOAD_GET_EXTPALNA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define IQK_OFFLOAD_SET_EXTPALNA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define IQK_OFFLOAD_SET_EXTPALNA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define MACID_CFG_3SS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define MACID_CFG_3SS_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define MACID_CFG_3SS_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define MACID_CFG_3SS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define MACID_CFG_3SS_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define MACID_CFG_3SS_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define MACID_CFG_3SS_GET_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define MACID_CFG_3SS_SET_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define MACID_CFG_3SS_SET_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define MACID_CFG_3SS_GET_RATE_MASK_39_32(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_39_32(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define MACID_CFG_3SS_SET_RATE_MASK_39_32_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define MACID_CFG_3SS_GET_RATE_MASK_47_40(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_47_40(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define MACID_CFG_3SS_SET_RATE_MASK_47_40_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define RA_PARA_ADJUST_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define RA_PARA_ADJUST_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define RA_PARA_ADJUST_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define RA_PARA_ADJUST_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define RA_PARA_ADJUST_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define RA_PARA_ADJUST_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define RA_PARA_ADJUST_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define RA_PARA_ADJUST_SET_MAC_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define RA_PARA_ADJUST_SET_MAC_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define RA_PARA_ADJUST_SET_PARAMETER_INDEX_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define RA_PARA_ADJUST_GET_RATE_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define RA_PARA_ADJUST_SET_RATE_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define RA_PARA_ADJUST_SET_RATE_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define RA_PARA_ADJUST_GET_VALUE_BYTE0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define RA_PARA_ADJUST_SET_VALUE_BYTE0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define RA_PARA_ADJUST_SET_VALUE_BYTE0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define RA_PARA_ADJUST_GET_VALUE_BYTE1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define RA_PARA_ADJUST_SET_VALUE_BYTE1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define RA_PARA_ADJUST_SET_VALUE_BYTE1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define WWLAN_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define WWLAN_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define WWLAN_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define WWLAN_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define WWLAN_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define WWLAN_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define WWLAN_GET_FUNC_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define WWLAN_SET_FUNC_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define WWLAN_SET_FUNC_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define WWLAN_GET_PATTERM_MAT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define WWLAN_SET_PATTERM_MAT_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define WWLAN_SET_PATTERM_MAT_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define WWLAN_GET_MAGIC_PKT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define WWLAN_SET_MAGIC_PKT_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define WWLAN_SET_MAGIC_PKT_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define WWLAN_GET_UNICAST_WAKEUP_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define WWLAN_SET_UNICAST_WAKEUP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define WWLAN_SET_UNICAST_WAKEUP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define WWLAN_GET_ALL_PKT_DROP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1) +#define WWLAN_SET_ALL_PKT_DROP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value) +#define WWLAN_SET_ALL_PKT_DROP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value) +#define WWLAN_GET_GPIO_ACTIVE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1) +#define WWLAN_SET_GPIO_ACTIVE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value) +#define WWLAN_SET_GPIO_ACTIVE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value) +#define WWLAN_GET_REKEY_WAKEUP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1) +#define WWLAN_SET_REKEY_WAKEUP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value) +#define WWLAN_SET_REKEY_WAKEUP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value) +#define WWLAN_GET_DEAUTH_WAKEUP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1) +#define WWLAN_SET_DEAUTH_WAKEUP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value) +#define WWLAN_SET_DEAUTH_WAKEUP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value) +#define WWLAN_GET_GPIO_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 7) +#define WWLAN_SET_GPIO_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 7, value) +#define WWLAN_SET_GPIO_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 7, value) +#define WWLAN_GET_DATAPIN_WAKEUP_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 23, 1) +#define WWLAN_SET_DATAPIN_WAKEUP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 23, 1, value) +#define WWLAN_SET_DATAPIN_WAKEUP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 23, 1, value) +#define WWLAN_GET_GPIO_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define WWLAN_SET_GPIO_DURATION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define WWLAN_SET_GPIO_DURATION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define WWLAN_GET_GPIO_PLUS_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 1) +#define WWLAN_SET_GPIO_PLUS_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 1, value) +#define WWLAN_SET_GPIO_PLUS_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 1, value) +#define WWLAN_GET_GPIO_PULSE_COUNT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 1, 7) +#define WWLAN_SET_GPIO_PULSE_COUNT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 1, 7, value) +#define WWLAN_SET_GPIO_PULSE_COUNT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 1, 7, value) +#define WWLAN_GET_DISABLE_UPHY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 1) +#define WWLAN_SET_DISABLE_UPHY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 1, value) +#define WWLAN_SET_DISABLE_UPHY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 1, value) +#define WWLAN_GET_HST2DEV_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 9, 1) +#define WWLAN_SET_HST2DEV_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 9, 1, value) +#define WWLAN_SET_HST2DEV_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 9, 1, value) +#define WWLAN_GET_GPIO_DURATION_MS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 10, 1) +#define WWLAN_SET_GPIO_DURATION_MS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 10, 1, value) +#define WWLAN_SET_GPIO_DURATION_MS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 10, 1, value) +#define REMOTE_WAKE_CTRL_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define REMOTE_WAKE_CTRL_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define REMOTE_WAKE_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define REMOTE_WAKE_CTRL_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define REMOTE_WAKE_CTRL_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define REMOTE_WAKE_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define REMOTE_WAKE_CTRL_GET_ARP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define REMOTE_WAKE_CTRL_SET_ARP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define REMOTE_WAKE_CTRL_SET_ARP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define REMOTE_WAKE_CTRL_GET_NDP_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define REMOTE_WAKE_CTRL_SET_NDP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define REMOTE_WAKE_CTRL_SET_NDP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define REMOTE_WAKE_CTRL_GET_GTK_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define REMOTE_WAKE_CTRL_SET_GTK_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define REMOTE_WAKE_CTRL_SET_GTK_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1) +#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value) +#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value) +#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value) +#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value) +#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1) +#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value) +#define REMOTE_WAKE_CTRL_SET_FW_UNICAST_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value) +#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 1) +#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 1, value) +#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 1, value) +#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 17, 1) +#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 17, 1, value) +#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 17, 1, value) +#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 18, 1) +#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 1, value) +#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 1, value) +#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 1) +#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value) +#define REMOTE_WAKE_CTRL_SET_ARP_ACTION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value) +#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 28, 1) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 1, value) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 1, value) +#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 29, 1) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 29, 1, value) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 29, 1, value) +#define AOAC_GLOBAL_INFO_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define AOAC_GLOBAL_INFO_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_GLOBAL_INFO_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_GLOBAL_INFO_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define AOAC_GLOBAL_INFO_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_GLOBAL_INFO_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define AOAC_RSVD_PAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define AOAC_RSVD_PAGE_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8) +#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value) +#define AOAC_RSVD_PAGE2_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define AOAC_RSVD_PAGE2_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE2_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE2_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define AOAC_RSVD_PAGE2_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE2_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value) +#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define D0_SCAN_OFFLOAD_INFO_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE3_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define AOAC_RSVD_PAGE3_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE3_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE3_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define AOAC_RSVD_PAGE3_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE3_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define DBG_MSG_CTRL_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define DBG_MSG_CTRL_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define DBG_MSG_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define DBG_MSG_CTRL_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define DBG_MSG_CTRL_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define DBG_MSG_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define DBG_MSG_CTRL_GET_FUN_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define DBG_MSG_CTRL_SET_FUN_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define DBG_MSG_CTRL_SET_FUN_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define DBG_MSG_CTRL_GET_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 4) +#define DBG_MSG_CTRL_SET_MODE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 4, value) +#define DBG_MSG_CTRL_SET_MODE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 4, value) #endif diff --git a/hal/halmac/halmac_original_h2c_nic.h b/hal/halmac/halmac_original_h2c_nic.h index b6ae5f0..3870ff4 100644 --- a/hal/halmac/halmac_original_h2c_nic.h +++ b/hal/halmac/halmac_original_h2c_nic.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,40 +15,43 @@ #ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_ #define _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_ -#define CMD_ID_ORIGINAL_H2C 0X00 -#define CMD_ID_H2C2H_LB 0X0 -#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06 -#define CMD_ID_RSVD_PAGE 0X0 -#define CMD_ID_MEDIA_STATUS_RPT 0X01 -#define CMD_ID_KEEP_ALIVE 0X03 -#define CMD_ID_DISCONNECT_DECISION 0X04 -#define CMD_ID_AP_OFFLOAD 0X08 -#define CMD_ID_BCN_RSVDPAGE 0X09 -#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A -#define CMD_ID_SET_PWR_MODE 0X00 -#define CMD_ID_PS_TUNING_PARA 0X01 -#define CMD_ID_PS_TUNING_PARA_II 0X02 -#define CMD_ID_PS_LPS_PARA 0X03 -#define CMD_ID_P2P_PS_OFFLOAD 0X04 -#define CMD_ID_PS_SCAN_EN 0X05 -#define CMD_ID_SAP_PS 0X06 -#define CMD_ID_INACTIVE_PS 0X07 -#define CMD_ID_MACID_CFG 0X00 -#define CMD_ID_TXBF 0X01 -#define CMD_ID_RSSI_SETTING 0X02 -#define CMD_ID_AP_REQ_TXRPT 0X03 -#define CMD_ID_INIT_RATE_COLLECTION 0X04 -#define CMD_ID_IQK_OFFLOAD 0X05 -#define CMD_ID_MACID_CFG_3SS 0X06 -#define CMD_ID_RA_PARA_ADJUST 0X07 -#define CMD_ID_WWLAN 0X00 -#define CMD_ID_REMOTE_WAKE_CTRL 0X01 -#define CMD_ID_AOAC_GLOBAL_INFO 0X02 -#define CMD_ID_AOAC_RSVD_PAGE 0X03 -#define CMD_ID_AOAC_RSVD_PAGE2 0X04 -#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05 -#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07 -#define CMD_ID_AOAC_RSVD_PAGE3 0X08 +#define CMD_ID_ORIGINAL_H2C 0X00 +#define CMD_ID_H2C2H_LB 0X0 +#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06 +#define CMD_ID_RSVD_PAGE 0X0 +#define CMD_ID_MEDIA_STATUS_RPT 0X01 +#define CMD_ID_KEEP_ALIVE 0X03 +#define CMD_ID_DISCONNECT_DECISION 0X04 +#define CMD_ID_AP_OFFLOAD 0X08 +#define CMD_ID_BCN_RSVDPAGE 0X09 +#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A +#define CMD_ID_SINGLE_CHANNELSWITCH 0X1C +#define CMD_ID_SINGLE_CHANNELSWITCH_V2 0X1D +#define CMD_ID_SET_PWR_MODE 0X00 +#define CMD_ID_PS_TUNING_PARA 0X01 +#define CMD_ID_PS_TUNING_PARA_II 0X02 +#define CMD_ID_PS_LPS_PARA 0X03 +#define CMD_ID_P2P_PS_OFFLOAD 0X04 +#define CMD_ID_PS_SCAN_EN 0X05 +#define CMD_ID_SAP_PS 0X06 +#define CMD_ID_INACTIVE_PS 0X07 +#define CMD_ID_MACID_CFG 0X00 +#define CMD_ID_TXBF 0X01 +#define CMD_ID_RSSI_SETTING 0X02 +#define CMD_ID_AP_REQ_TXRPT 0X03 +#define CMD_ID_INIT_RATE_COLLECTION 0X04 +#define CMD_ID_IQK_OFFLOAD 0X05 +#define CMD_ID_MACID_CFG_3SS 0X06 +#define CMD_ID_RA_PARA_ADJUST 0X07 +#define CMD_ID_WWLAN 0X00 +#define CMD_ID_REMOTE_WAKE_CTRL 0X01 +#define CMD_ID_AOAC_GLOBAL_INFO 0X02 +#define CMD_ID_AOAC_RSVD_PAGE 0X03 +#define CMD_ID_AOAC_RSVD_PAGE2 0X04 +#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05 +#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07 +#define CMD_ID_AOAC_RSVD_PAGE3 0X08 +#define CMD_ID_DBG_MSG_CTRL 0X1E #define CLASS_ORIGINAL_H2C 0X00 #define CLASS_H2C2H_LB 0X07 #define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04 @@ -59,6 +62,8 @@ #define CLASS_AP_OFFLOAD 0X0 #define CLASS_BCN_RSVDPAGE 0X0 #define CLASS_PROBE_RSP_RSVDPAGE 0X0 +#define CLASS_SINGLE_CHANNELSWITCH 0X0 +#define CLASS_SINGLE_CHANNELSWITCH_V2 0X0 #define CLASS_SET_PWR_MODE 0X01 #define CLASS_PS_TUNING_PARA 0X01 #define CLASS_PS_TUNING_PARA_II 0X01 @@ -83,540 +88,1056 @@ #define CLASS_D0_SCAN_OFFLOAD_INFO 0X04 #define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04 #define CLASS_AOAC_RSVD_PAGE3 0X04 -#define ORIGINAL_H2C_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define ORIGINAL_H2C_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define ORIGINAL_H2C_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define ORIGINAL_H2C_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define H2C2H_LB_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define H2C2H_LB_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define H2C2H_LB_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define H2C2H_LB_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define H2C2H_LB_GET_SEQ(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define H2C2H_LB_SET_SEQ(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define H2C2H_LB_GET_PAYLOAD1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 16) -#define H2C2H_LB_SET_PAYLOAD1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 16, __Value) -#define H2C2H_LB_GET_PAYLOAD2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 32) -#define H2C2H_LB_SET_PAYLOAD2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 32, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 17) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 17, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define RSVD_PAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define RSVD_PAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define RSVD_PAGE_GET_LOC_PROBE_RSP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define RSVD_PAGE_SET_LOC_PROBE_RSP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define RSVD_PAGE_GET_LOC_PS_POLL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define RSVD_PAGE_SET_LOC_PS_POLL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define RSVD_PAGE_GET_LOC_NULL_DATA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define RSVD_PAGE_SET_LOC_NULL_DATA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define RSVD_PAGE_GET_LOC_QOS_NULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define RSVD_PAGE_SET_LOC_QOS_NULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define RSVD_PAGE_GET_LOC_CTS2SELF(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define RSVD_PAGE_SET_LOC_CTS2SELF(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) -#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define MEDIA_STATUS_RPT_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define MEDIA_STATUS_RPT_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define MEDIA_STATUS_RPT_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define MEDIA_STATUS_RPT_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define MEDIA_STATUS_RPT_GET_OP_MODE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define MEDIA_STATUS_RPT_SET_OP_MODE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define MEDIA_STATUS_RPT_GET_MACID_IN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define MEDIA_STATUS_RPT_SET_MACID_IN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define MEDIA_STATUS_RPT_GET_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define MEDIA_STATUS_RPT_SET_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define MEDIA_STATUS_RPT_GET_MACID_END(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define MEDIA_STATUS_RPT_SET_MACID_END(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define KEEP_ALIVE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define KEEP_ALIVE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define KEEP_ALIVE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define KEEP_ALIVE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define KEEP_ALIVE_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define KEEP_ALIVE_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define KEEP_ALIVE_GET_PKT_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define KEEP_ALIVE_SET_PKT_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define DISCONNECT_DECISION_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define DISCONNECT_DECISION_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define DISCONNECT_DECISION_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define DISCONNECT_DECISION_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define DISCONNECT_DECISION_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define DISCONNECT_DECISION_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define DISCONNECT_DECISION_GET_DISCONNECT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define DISCONNECT_DECISION_SET_DISCONNECT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define AP_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define AP_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define AP_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AP_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AP_OFFLOAD_GET_ON(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define AP_OFFLOAD_SET_ON(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define AP_OFFLOAD_GET_LINKED(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define AP_OFFLOAD_SET_LINKED(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define AP_OFFLOAD_GET_EN_AUTO_WAKE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define AP_OFFLOAD_SET_EN_AUTO_WAKE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define AP_OFFLOAD_GET_WAKE_FLAG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) -#define AP_OFFLOAD_SET_WAKE_FLAG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 1) -#define AP_OFFLOAD_SET_HIDDEN_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 17, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 17, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 18, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 18, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 19, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 19, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 20, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 20, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 1) -#define AP_OFFLOAD_SET_DENYANY_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 25, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 25, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 26, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 26, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 27, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 27, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 28, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 1, __Value) -#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define AP_OFFLOAD_GET_WAKE_TIMEOUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define AP_OFFLOAD_SET_WAKE_TIMEOUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define AP_OFFLOAD_GET_LEN_IV_PAIR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define AP_OFFLOAD_SET_LEN_IV_PAIR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define AP_OFFLOAD_GET_LEN_IV_GRP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) -#define AP_OFFLOAD_SET_LEN_IV_GRP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define BCN_RSVDPAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define BCN_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define BCN_RSVDPAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define BCN_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define BCN_RSVDPAGE_GET_LOC_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define BCN_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define PROBE_RSP_RSVDPAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define PROBE_RSP_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define SET_PWR_MODE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define SET_PWR_MODE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define SET_PWR_MODE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define SET_PWR_MODE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define SET_PWR_MODE_GET_MODE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7) -#define SET_PWR_MODE_SET_MODE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 7, __Value) -#define SET_PWR_MODE_GET_CLK_REQUEST(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) -#define SET_PWR_MODE_SET_CLK_REQUEST(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) -#define SET_PWR_MODE_GET_RLBM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 4) -#define SET_PWR_MODE_SET_RLBM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 4, __Value) -#define SET_PWR_MODE_GET_SMART_PS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 20, 4) -#define SET_PWR_MODE_SET_SMART_PS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 20, 4, __Value) -#define SET_PWR_MODE_GET_AWAKE_INTERVAL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define SET_PWR_MODE_SET_AWAKE_INTERVAL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 1) -#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 1, __Value) -#define SET_PWR_MODE_GET_BCN_EARLY_RPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 2, 1) -#define SET_PWR_MODE_SET_BCN_EARLY_RPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 2, 1, __Value) -#define SET_PWR_MODE_GET_PORT_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 5, 3) -#define SET_PWR_MODE_SET_PORT_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 5, 3, __Value) -#define SET_PWR_MODE_GET_PWR_STATE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define SET_PWR_MODE_SET_PWR_STATE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 1) -#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 1, __Value) -#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 17, 1) -#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 17, 1, __Value) -#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 18, 1) -#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 18, 1, __Value) -#define SET_PWR_MODE_GET_PROTECT_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 19, 1) -#define SET_PWR_MODE_SET_PROTECT_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 19, 1, __Value) -#define SET_PWR_MODE_GET_SILENCE_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 20, 1) -#define SET_PWR_MODE_SET_SILENCE_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 20, 1, __Value) -#define SET_PWR_MODE_GET_FAST_BT_CONNECT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 21, 1) -#define SET_PWR_MODE_SET_FAST_BT_CONNECT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 21, 1, __Value) -#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 22, 1) -#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 22, 1, __Value) -#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 1) -#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 1, __Value) -#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 25, 3) -#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 25, 3, __Value) -#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 28, 4) -#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 28, 4, __Value) -#define PS_TUNING_PARA_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define PS_TUNING_PARA_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define PS_TUNING_PARA_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define PS_TUNING_PARA_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7) -#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 7, __Value) -#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) -#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) -#define PS_TUNING_PARA_GET_PS_TIME_OUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 4) -#define PS_TUNING_PARA_SET_PS_TIME_OUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 4, __Value) -#define PS_TUNING_PARA_GET_ADOPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define PS_TUNING_PARA_SET_ADOPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define PS_TUNING_PARA_II_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define PS_TUNING_PARA_II_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define PS_TUNING_PARA_II_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define PS_TUNING_PARA_II_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7) -#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 7, __Value) -#define PS_TUNING_PARA_II_GET_ADOPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) -#define PS_TUNING_PARA_II_SET_ADOPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) -#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define PS_LPS_PARA_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define PS_LPS_PARA_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define PS_LPS_PARA_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define PS_LPS_PARA_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define PS_LPS_PARA_GET_LPS_CONTROL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define PS_LPS_PARA_SET_LPS_CONTROL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define P2P_PS_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define P2P_PS_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define P2P_PS_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define P2P_PS_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define P2P_PS_OFFLOAD_GET_ROLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define P2P_PS_OFFLOAD_SET_ROLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define P2P_PS_OFFLOAD_GET_NOA0_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define P2P_PS_OFFLOAD_SET_NOA0_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define P2P_PS_OFFLOAD_GET_NOA1_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) -#define P2P_PS_OFFLOAD_SET_NOA1_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) -#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 13, 1) -#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value) -#define P2P_PS_OFFLOAD_GET_DISCOVERY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1) -#define P2P_PS_OFFLOAD_SET_DISCOVERY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value) -#define PS_SCAN_EN_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define PS_SCAN_EN_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define PS_SCAN_EN_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define PS_SCAN_EN_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define PS_SCAN_EN_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define PS_SCAN_EN_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define SAP_PS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define SAP_PS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define SAP_PS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define SAP_PS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define SAP_PS_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define SAP_PS_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define SAP_PS_GET_EN_PS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define SAP_PS_SET_EN_PS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define SAP_PS_GET_EN_LP_RX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define SAP_PS_SET_EN_LP_RX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define SAP_PS_GET_MANUAL_32K(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define SAP_PS_SET_MANUAL_32K(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define SAP_PS_GET_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define SAP_PS_SET_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define INACTIVE_PS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define INACTIVE_PS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define INACTIVE_PS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define INACTIVE_PS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define INACTIVE_PS_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define INACTIVE_PS_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define INACTIVE_PS_GET_FREQUENCY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define INACTIVE_PS_SET_FREQUENCY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define INACTIVE_PS_GET_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define INACTIVE_PS_SET_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define MACID_CFG_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define MACID_CFG_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define MACID_CFG_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define MACID_CFG_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define MACID_CFG_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define MACID_CFG_SET_MAC_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define MACID_CFG_GET_RATE_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 5) -#define MACID_CFG_SET_RATE_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 5, __Value) -#define MACID_CFG_GET_SGI(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 23, 1) -#define MACID_CFG_SET_SGI(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 23, 1, __Value) -#define MACID_CFG_GET_BW(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 2) -#define MACID_CFG_SET_BW(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 2, __Value) -#define MACID_CFG_GET_LDPC_CAP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 26, 1) -#define MACID_CFG_SET_LDPC_CAP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 26, 1, __Value) -#define MACID_CFG_GET_NO_UPDATE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 27, 1) -#define MACID_CFG_SET_NO_UPDATE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 27, 1, __Value) -#define MACID_CFG_GET_WHT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 28, 2) -#define MACID_CFG_SET_WHT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 2, __Value) -#define MACID_CFG_GET_DISPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 30, 1) -#define MACID_CFG_SET_DISPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 30, 1, __Value) -#define MACID_CFG_GET_DISRA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 31, 1) -#define MACID_CFG_SET_DISRA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 31, 1, __Value) -#define MACID_CFG_GET_RATE_MASK7_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define MACID_CFG_SET_RATE_MASK7_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define MACID_CFG_GET_RATE_MASK15_8(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define MACID_CFG_SET_RATE_MASK15_8(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define MACID_CFG_GET_RATE_MASK23_16(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define MACID_CFG_SET_RATE_MASK23_16(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define MACID_CFG_GET_RATE_MASK31_24(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) -#define MACID_CFG_SET_RATE_MASK31_24(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define TXBF_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define TXBF_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define TXBF_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define TXBF_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define TXBF_GET_NDPA0_HEAD_PAGE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define TXBF_SET_NDPA0_HEAD_PAGE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define TXBF_GET_NDPA1_HEAD_PAGE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define TXBF_SET_NDPA1_HEAD_PAGE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define TXBF_GET_PERIOD_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define TXBF_SET_PERIOD_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define RSSI_SETTING_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define RSSI_SETTING_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define RSSI_SETTING_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define RSSI_SETTING_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define RSSI_SETTING_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define RSSI_SETTING_SET_MAC_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define RSSI_SETTING_GET_RSSI(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 7) -#define RSSI_SETTING_SET_RSSI(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 7, __Value) -#define RSSI_SETTING_GET_RA_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define RSSI_SETTING_SET_RA_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define AP_REQ_TXRPT_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define AP_REQ_TXRPT_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define AP_REQ_TXRPT_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AP_REQ_TXRPT_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AP_REQ_TXRPT_GET_STA1_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define AP_REQ_TXRPT_SET_STA1_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define AP_REQ_TXRPT_GET_STA2_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define AP_REQ_TXRPT_SET_STA2_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 1) -#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value) -#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 25, 1) -#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 25, 1, __Value) -#define INIT_RATE_COLLECTION_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define INIT_RATE_COLLECTION_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define INIT_RATE_COLLECTION_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define INIT_RATE_COLLECTION_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define INIT_RATE_COLLECTION_GET_STA1_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define INIT_RATE_COLLECTION_SET_STA1_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA2_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define INIT_RATE_COLLECTION_SET_STA2_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA3_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define INIT_RATE_COLLECTION_SET_STA3_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA4_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define INIT_RATE_COLLECTION_SET_STA4_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA5_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define INIT_RATE_COLLECTION_SET_STA5_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA6_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define INIT_RATE_COLLECTION_SET_STA6_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA7_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) -#define INIT_RATE_COLLECTION_SET_STA7_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define IQK_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define IQK_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define IQK_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define IQK_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define IQK_OFFLOAD_GET_CHANNEL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define IQK_OFFLOAD_SET_CHANNEL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define IQK_OFFLOAD_GET_BWBAND(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define IQK_OFFLOAD_SET_BWBAND(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define IQK_OFFLOAD_GET_EXTPALNA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define IQK_OFFLOAD_SET_EXTPALNA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define MACID_CFG_3SS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define MACID_CFG_3SS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define MACID_CFG_3SS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define MACID_CFG_3SS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define MACID_CFG_3SS_GET_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define MACID_CFG_3SS_SET_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define MACID_CFG_3SS_GET_RATE_MASK_39_32(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define MACID_CFG_3SS_SET_RATE_MASK_39_32(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define MACID_CFG_3SS_GET_RATE_MASK_47_40(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define MACID_CFG_3SS_SET_RATE_MASK_47_40(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define RA_PARA_ADJUST_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define RA_PARA_ADJUST_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define RA_PARA_ADJUST_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define RA_PARA_ADJUST_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define RA_PARA_ADJUST_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define RA_PARA_ADJUST_SET_MAC_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define RA_PARA_ADJUST_GET_RATE_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define RA_PARA_ADJUST_SET_RATE_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define RA_PARA_ADJUST_GET_VALUE_BYTE0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define RA_PARA_ADJUST_SET_VALUE_BYTE0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define RA_PARA_ADJUST_GET_VALUE_BYTE1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define RA_PARA_ADJUST_SET_VALUE_BYTE1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define WWLAN_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define WWLAN_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define WWLAN_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define WWLAN_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define WWLAN_GET_FUNC_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define WWLAN_SET_FUNC_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define WWLAN_GET_PATTERM_MAT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define WWLAN_SET_PATTERM_MAT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define WWLAN_GET_MAGIC_PKT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define WWLAN_SET_MAGIC_PKT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define WWLAN_GET_UNICAST_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define WWLAN_SET_UNICAST_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define WWLAN_GET_ALL_PKT_DROP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) -#define WWLAN_SET_ALL_PKT_DROP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) -#define WWLAN_GET_GPIO_ACTIVE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 13, 1) -#define WWLAN_SET_GPIO_ACTIVE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value) -#define WWLAN_GET_REKEY_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1) -#define WWLAN_SET_REKEY_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value) -#define WWLAN_GET_DEAUTH_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) -#define WWLAN_SET_DEAUTH_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) -#define WWLAN_GET_GPIO_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 7) -#define WWLAN_SET_GPIO_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 7, __Value) -#define WWLAN_GET_DATAPIN_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 23, 1) -#define WWLAN_SET_DATAPIN_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 23, 1, __Value) -#define WWLAN_GET_GPIO_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define WWLAN_SET_GPIO_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define WWLAN_GET_GPIO_PLUS_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 1) -#define WWLAN_SET_GPIO_PLUS_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 1, __Value) -#define WWLAN_GET_GPIO_PULSE_COUNT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 1, 7) -#define WWLAN_SET_GPIO_PULSE_COUNT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 1, 7, __Value) -#define WWLAN_GET_DISABLE_UPHY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 1) -#define WWLAN_SET_DISABLE_UPHY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 1, __Value) -#define WWLAN_GET_HST2DEV_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 9, 1) -#define WWLAN_SET_HST2DEV_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 9, 1, __Value) -#define WWLAN_GET_GPIO_DURATION_MS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 10, 1) -#define WWLAN_SET_GPIO_DURATION_MS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 10, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define REMOTE_WAKE_CTRL_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define REMOTE_WAKE_CTRL_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define REMOTE_WAKE_CTRL_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_ARP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define REMOTE_WAKE_CTRL_SET_ARP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_NDP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define REMOTE_WAKE_CTRL_SET_NDP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_GTK_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define REMOTE_WAKE_CTRL_SET_GTK_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) -#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 13, 1) -#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1) -#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) -#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 1) -#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 17, 1) -#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 17, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 18, 1) -#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 18, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 1) -#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 28, 1) -#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 29, 1) -#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 29, 1, __Value) -#define AOAC_GLOBAL_INFO_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define AOAC_GLOBAL_INFO_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_GLOBAL_INFO_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AOAC_GLOBAL_INFO_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define AOAC_RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AOAC_RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) -#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define AOAC_RSVD_PAGE2_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE2_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AOAC_RSVD_PAGE2_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE3_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define AOAC_RSVD_PAGE3_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE3_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AOAC_RSVD_PAGE3_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define CLASS_DBG_MSG_CTRL 0X07 +#define ORIGINAL_H2C_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define ORIGINAL_H2C_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define ORIGINAL_H2C_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define ORIGINAL_H2C_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define H2C2H_LB_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define H2C2H_LB_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define H2C2H_LB_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define H2C2H_LB_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define H2C2H_LB_GET_SEQ(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define H2C2H_LB_SET_SEQ(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define H2C2H_LB_GET_PAYLOAD1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 16) +#define H2C2H_LB_SET_PAYLOAD1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 16, value) +#define H2C2H_LB_GET_PAYLOAD2(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 32) +#define H2C2H_LB_SET_PAYLOAD2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 32, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 17) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 17, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define RSVD_PAGE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define RSVD_PAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define RSVD_PAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define RSVD_PAGE_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define RSVD_PAGE_GET_LOC_PROBE_RSP(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define RSVD_PAGE_SET_LOC_PROBE_RSP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define RSVD_PAGE_GET_LOC_PS_POLL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define RSVD_PAGE_SET_LOC_PS_POLL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define RSVD_PAGE_GET_LOC_NULL_DATA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define RSVD_PAGE_SET_LOC_NULL_DATA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define RSVD_PAGE_GET_LOC_QOS_NULL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define RSVD_PAGE_SET_LOC_QOS_NULL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define RSVD_PAGE_GET_LOC_CTS2SELF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define RSVD_PAGE_SET_LOC_CTS2SELF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8) +#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value) +#define MEDIA_STATUS_RPT_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define MEDIA_STATUS_RPT_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define MEDIA_STATUS_RPT_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define MEDIA_STATUS_RPT_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define MEDIA_STATUS_RPT_GET_OP_MODE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define MEDIA_STATUS_RPT_GET_MACID_IN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define MEDIA_STATUS_RPT_SET_MACID_IN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define MEDIA_STATUS_RPT_GET_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define MEDIA_STATUS_RPT_GET_MACID_END(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define MEDIA_STATUS_RPT_SET_MACID_END(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define KEEP_ALIVE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define KEEP_ALIVE_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define KEEP_ALIVE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define KEEP_ALIVE_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define KEEP_ALIVE_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define KEEP_ALIVE_SET_ENABLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define KEEP_ALIVE_GET_PKT_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define KEEP_ALIVE_SET_PKT_TYPE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define DISCONNECT_DECISION_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define DISCONNECT_DECISION_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define DISCONNECT_DECISION_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define DISCONNECT_DECISION_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define DISCONNECT_DECISION_GET_ENABLE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define DISCONNECT_DECISION_SET_ENABLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define DISCONNECT_DECISION_GET_DISCONNECT_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define DISCONNECT_DECISION_SET_DISCONNECT_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define AP_OFFLOAD_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define AP_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define AP_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define AP_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define AP_OFFLOAD_GET_ON(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define AP_OFFLOAD_SET_ON(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define AP_OFFLOAD_GET_LINKED(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define AP_OFFLOAD_SET_LINKED(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define AP_OFFLOAD_GET_EN_AUTO_WAKE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define AP_OFFLOAD_SET_EN_AUTO_WAKE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define AP_OFFLOAD_GET_WAKE_FLAG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1) +#define AP_OFFLOAD_SET_WAKE_FLAG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_ROOT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 1) +#define AP_OFFLOAD_SET_HIDDEN_ROOT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 17, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 17, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 19, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 19, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 1, value) +#define AP_OFFLOAD_GET_DENYANY_ROOT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1) +#define AP_OFFLOAD_SET_DENYANY_ROOT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 25, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 25, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 26, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 26, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 27, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 27, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 1, value) +#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define AP_OFFLOAD_GET_WAKE_TIMEOUT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define AP_OFFLOAD_SET_WAKE_TIMEOUT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define AP_OFFLOAD_GET_LEN_IV_PAIR(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define AP_OFFLOAD_SET_LEN_IV_PAIR(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define AP_OFFLOAD_GET_LEN_IV_GRP(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8) +#define AP_OFFLOAD_SET_LEN_IV_GRP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value) +#define BCN_RSVDPAGE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define BCN_RSVDPAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define BCN_RSVDPAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define BCN_RSVDPAGE_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define BCN_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define BCN_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define PROBE_RSP_RSVDPAGE_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define PROBE_RSP_RSVDPAGE_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define SINGLE_CHANNELSWITCH_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define SINGLE_CHANNELSWITCH_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define SINGLE_CHANNELSWITCH_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define SINGLE_CHANNELSWITCH_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define SINGLE_CHANNELSWITCH_GET_CHANNEL_NUM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define SINGLE_CHANNELSWITCH_GET_BW(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 2) +#define SINGLE_CHANNELSWITCH_SET_BW(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 2, value) +#define SINGLE_CHANNELSWITCH_GET_BW40SC(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 3) +#define SINGLE_CHANNELSWITCH_SET_BW40SC(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 3, value) +#define SINGLE_CHANNELSWITCH_GET_BW80SC(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 21, 3) +#define SINGLE_CHANNELSWITCH_SET_BW80SC(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 21, 3, value) +#define SINGLE_CHANNELSWITCH_GET_RFE_TYPE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 4) +#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 4, value) +#define SINGLE_CHANNELSWITCH_V2_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define SINGLE_CHANNELSWITCH_V2_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define SINGLE_CHANNELSWITCH_V2_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define SINGLE_CHANNELSWITCH_V2_GET_CENTRAL_CH(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define SINGLE_CHANNELSWITCH_V2_GET_PRIMARY_CH_IDX(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4) +#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value) +#define SINGLE_CHANNELSWITCH_V2_GET_BW(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 4) +#define SINGLE_CHANNELSWITCH_V2_SET_BW(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 4, value) +#define SET_PWR_MODE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define SET_PWR_MODE_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define SET_PWR_MODE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define SET_PWR_MODE_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define SET_PWR_MODE_GET_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7) +#define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value) +#define SET_PWR_MODE_GET_CLK_REQUEST(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1) +#define SET_PWR_MODE_SET_CLK_REQUEST(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value) +#define SET_PWR_MODE_GET_RLBM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4) +#define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value) +#define SET_PWR_MODE_GET_SMART_PS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 4) +#define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 4, value) +#define SET_PWR_MODE_GET_AWAKE_INTERVAL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 1) +#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 1, value) +#define SET_PWR_MODE_GET_BCN_EARLY_RPT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 2, 1) +#define SET_PWR_MODE_SET_BCN_EARLY_RPT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 2, 1, value) +#define SET_PWR_MODE_GET_PORT_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 5, 3) +#define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 5, 3, value) +#define SET_PWR_MODE_GET_PWR_STATE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 1) +#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 1, value) +#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 17, 1) +#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 17, 1, value) +#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 18, 1) +#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 18, 1, value) +#define SET_PWR_MODE_GET_PROTECT_BCN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 19, 1) +#define SET_PWR_MODE_SET_PROTECT_BCN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 19, 1, value) +#define SET_PWR_MODE_GET_SILENCE_PERIOD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 20, 1) +#define SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 20, 1, value) +#define SET_PWR_MODE_GET_FAST_BT_CONNECT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 21, 1) +#define SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 21, 1, value) +#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 22, 1) +#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 22, 1, value) +#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 1) +#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 1, value) +#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 25, 3) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 25, 3, value) +#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 28, 4) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 28, 4, value) +#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define PS_TUNING_PARA_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define PS_TUNING_PARA_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7) +#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value) +#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1) +#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value) +#define PS_TUNING_PARA_GET_PS_TIME_OUT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4) +#define PS_TUNING_PARA_SET_PS_TIME_OUT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value) +#define PS_TUNING_PARA_GET_ADOPT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define PS_TUNING_PARA_SET_ADOPT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define PS_TUNING_PARA_II_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define PS_TUNING_PARA_II_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define PS_TUNING_PARA_II_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define PS_TUNING_PARA_II_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7) +#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value) +#define PS_TUNING_PARA_II_GET_ADOPT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1) +#define PS_TUNING_PARA_II_SET_ADOPT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value) +#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define PS_LPS_PARA_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define PS_LPS_PARA_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define PS_LPS_PARA_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define PS_LPS_PARA_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define PS_LPS_PARA_GET_LPS_CONTROL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define PS_LPS_PARA_SET_LPS_CONTROL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define P2P_PS_OFFLOAD_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define P2P_PS_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define P2P_PS_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define P2P_PS_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define P2P_PS_OFFLOAD_GET_ROLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define P2P_PS_OFFLOAD_SET_ROLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define P2P_PS_OFFLOAD_GET_NOA0_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define P2P_PS_OFFLOAD_SET_NOA0_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define P2P_PS_OFFLOAD_GET_NOA1_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1) +#define P2P_PS_OFFLOAD_SET_NOA1_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value) +#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1) +#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value) +#define P2P_PS_OFFLOAD_GET_DISCOVERY(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1) +#define P2P_PS_OFFLOAD_SET_DISCOVERY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value) +#define PS_SCAN_EN_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define PS_SCAN_EN_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define PS_SCAN_EN_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define PS_SCAN_EN_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define PS_SCAN_EN_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define PS_SCAN_EN_SET_ENABLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define SAP_PS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define SAP_PS_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define SAP_PS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define SAP_PS_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define SAP_PS_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define SAP_PS_SET_ENABLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define SAP_PS_GET_EN_PS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define SAP_PS_SET_EN_PS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define SAP_PS_GET_EN_LP_RX(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define SAP_PS_SET_EN_LP_RX(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define SAP_PS_GET_MANUAL_32K(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define SAP_PS_SET_MANUAL_32K(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define SAP_PS_GET_DURATION(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define SAP_PS_SET_DURATION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define INACTIVE_PS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define INACTIVE_PS_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define INACTIVE_PS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define INACTIVE_PS_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define INACTIVE_PS_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define INACTIVE_PS_SET_ENABLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define INACTIVE_PS_GET_FREQUENCY(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define INACTIVE_PS_SET_FREQUENCY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define INACTIVE_PS_GET_DURATION(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define INACTIVE_PS_SET_DURATION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define MACID_CFG_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define MACID_CFG_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define MACID_CFG_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define MACID_CFG_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define MACID_CFG_GET_MAC_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define MACID_CFG_SET_MAC_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define MACID_CFG_GET_RATE_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 5) +#define MACID_CFG_SET_RATE_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 5, value) +#define MACID_CFG_GET_INIT_RATE_LV(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 21, 2) +#define MACID_CFG_SET_INIT_RATE_LV(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 21, 2, value) +#define MACID_CFG_GET_SGI(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 23, 1) +#define MACID_CFG_SET_SGI(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 23, 1, value) +#define MACID_CFG_GET_BW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 2) +#define MACID_CFG_SET_BW(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 2, value) +#define MACID_CFG_GET_LDPC_CAP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 26, 1) +#define MACID_CFG_SET_LDPC_CAP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 26, 1, value) +#define MACID_CFG_GET_NO_UPDATE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 27, 1) +#define MACID_CFG_SET_NO_UPDATE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 27, 1, value) +#define MACID_CFG_GET_WHT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 2) +#define MACID_CFG_SET_WHT_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 2, value) +#define MACID_CFG_GET_DISPT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 30, 1) +#define MACID_CFG_SET_DISPT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 30, 1, value) +#define MACID_CFG_GET_DISRA(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 31, 1) +#define MACID_CFG_SET_DISRA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 31, 1, value) +#define MACID_CFG_GET_RATE_MASK7_0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define MACID_CFG_SET_RATE_MASK7_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define MACID_CFG_GET_RATE_MASK15_8(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define MACID_CFG_SET_RATE_MASK15_8(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define MACID_CFG_GET_RATE_MASK23_16(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define MACID_CFG_SET_RATE_MASK23_16(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define MACID_CFG_GET_RATE_MASK31_24(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8) +#define MACID_CFG_SET_RATE_MASK31_24(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value) +#define TXBF_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define TXBF_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define TXBF_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define TXBF_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define TXBF_GET_NDPA0_HEAD_PAGE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define TXBF_SET_NDPA0_HEAD_PAGE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define TXBF_GET_NDPA1_HEAD_PAGE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define TXBF_SET_NDPA1_HEAD_PAGE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define TXBF_GET_PERIOD_0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define TXBF_SET_PERIOD_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define RSSI_SETTING_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define RSSI_SETTING_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define RSSI_SETTING_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define RSSI_SETTING_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define RSSI_SETTING_GET_MAC_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define RSSI_SETTING_SET_MAC_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define RSSI_SETTING_GET_RSSI(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 7) +#define RSSI_SETTING_SET_RSSI(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 7, value) +#define RSSI_SETTING_GET_RA_INFO(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define RSSI_SETTING_SET_RA_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define AP_REQ_TXRPT_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define AP_REQ_TXRPT_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define AP_REQ_TXRPT_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define AP_REQ_TXRPT_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define AP_REQ_TXRPT_GET_STA1_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define AP_REQ_TXRPT_SET_STA1_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define AP_REQ_TXRPT_GET_STA2_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define AP_REQ_TXRPT_SET_STA2_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1) +#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value) +#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 25, 1) +#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 25, 1, value) +#define INIT_RATE_COLLECTION_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define INIT_RATE_COLLECTION_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define INIT_RATE_COLLECTION_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define INIT_RATE_COLLECTION_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define INIT_RATE_COLLECTION_GET_STA1_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define INIT_RATE_COLLECTION_SET_STA1_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define INIT_RATE_COLLECTION_GET_STA2_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define INIT_RATE_COLLECTION_SET_STA2_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define INIT_RATE_COLLECTION_GET_STA3_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define INIT_RATE_COLLECTION_SET_STA3_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define INIT_RATE_COLLECTION_GET_STA4_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define INIT_RATE_COLLECTION_SET_STA4_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define INIT_RATE_COLLECTION_GET_STA5_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define INIT_RATE_COLLECTION_SET_STA5_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define INIT_RATE_COLLECTION_GET_STA6_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define INIT_RATE_COLLECTION_SET_STA6_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define INIT_RATE_COLLECTION_GET_STA7_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8) +#define INIT_RATE_COLLECTION_SET_STA7_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value) +#define IQK_OFFLOAD_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define IQK_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define IQK_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define IQK_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define IQK_OFFLOAD_GET_CHANNEL(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define IQK_OFFLOAD_SET_CHANNEL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define IQK_OFFLOAD_GET_BWBAND(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define IQK_OFFLOAD_SET_BWBAND(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define IQK_OFFLOAD_GET_EXTPALNA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define IQK_OFFLOAD_SET_EXTPALNA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define MACID_CFG_3SS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define MACID_CFG_3SS_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define MACID_CFG_3SS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define MACID_CFG_3SS_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define MACID_CFG_3SS_GET_MACID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define MACID_CFG_3SS_SET_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define MACID_CFG_3SS_GET_RATE_MASK_39_32(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_39_32(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define MACID_CFG_3SS_GET_RATE_MASK_47_40(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_47_40(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define RA_PARA_ADJUST_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define RA_PARA_ADJUST_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define RA_PARA_ADJUST_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define RA_PARA_ADJUST_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define RA_PARA_ADJUST_GET_MAC_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define RA_PARA_ADJUST_SET_MAC_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define RA_PARA_ADJUST_GET_RATE_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define RA_PARA_ADJUST_SET_RATE_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define RA_PARA_ADJUST_GET_VALUE_BYTE0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define RA_PARA_ADJUST_SET_VALUE_BYTE0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define RA_PARA_ADJUST_GET_VALUE_BYTE1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define RA_PARA_ADJUST_SET_VALUE_BYTE1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define WWLAN_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define WWLAN_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define WWLAN_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define WWLAN_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define WWLAN_GET_FUNC_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define WWLAN_SET_FUNC_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define WWLAN_GET_PATTERM_MAT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define WWLAN_SET_PATTERM_MAT_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define WWLAN_GET_MAGIC_PKT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define WWLAN_SET_MAGIC_PKT_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define WWLAN_GET_UNICAST_WAKEUP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define WWLAN_SET_UNICAST_WAKEUP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define WWLAN_GET_ALL_PKT_DROP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1) +#define WWLAN_SET_ALL_PKT_DROP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value) +#define WWLAN_GET_GPIO_ACTIVE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1) +#define WWLAN_SET_GPIO_ACTIVE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value) +#define WWLAN_GET_REKEY_WAKEUP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1) +#define WWLAN_SET_REKEY_WAKEUP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value) +#define WWLAN_GET_DEAUTH_WAKEUP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1) +#define WWLAN_SET_DEAUTH_WAKEUP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value) +#define WWLAN_GET_GPIO_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 7) +#define WWLAN_SET_GPIO_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 7, value) +#define WWLAN_GET_DATAPIN_WAKEUP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 23, 1) +#define WWLAN_SET_DATAPIN_WAKEUP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 23, 1, value) +#define WWLAN_GET_GPIO_DURATION(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define WWLAN_SET_GPIO_DURATION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define WWLAN_GET_GPIO_PLUS_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 1) +#define WWLAN_SET_GPIO_PLUS_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 1, value) +#define WWLAN_GET_GPIO_PULSE_COUNT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 1, 7) +#define WWLAN_SET_GPIO_PULSE_COUNT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 1, 7, value) +#define WWLAN_GET_DISABLE_UPHY(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 1) +#define WWLAN_SET_DISABLE_UPHY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 1, value) +#define WWLAN_GET_HST2DEV_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 9, 1) +#define WWLAN_SET_HST2DEV_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 9, 1, value) +#define WWLAN_GET_GPIO_DURATION_MS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 10, 1) +#define WWLAN_SET_GPIO_DURATION_MS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 10, 1, value) +#define REMOTE_WAKE_CTRL_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define REMOTE_WAKE_CTRL_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define REMOTE_WAKE_CTRL_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define REMOTE_WAKE_CTRL_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define REMOTE_WAKE_CTRL_GET_ARP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define REMOTE_WAKE_CTRL_SET_ARP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define REMOTE_WAKE_CTRL_GET_NDP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define REMOTE_WAKE_CTRL_SET_NDP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define REMOTE_WAKE_CTRL_GET_GTK_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define REMOTE_WAKE_CTRL_SET_GTK_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1) +#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value) +#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value) +#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value) +#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1) +#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value) +#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 1) +#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 1, value) +#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 17, 1) +#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 17, 1, value) +#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 1) +#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 1, value) +#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1) +#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value) +#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 1) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 1, value) +#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 29, 1) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 29, 1, value) +#define AOAC_GLOBAL_INFO_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define AOAC_GLOBAL_INFO_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_GLOBAL_INFO_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define AOAC_GLOBAL_INFO_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define AOAC_RSVD_PAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define AOAC_RSVD_PAGE_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8) +#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value) +#define AOAC_RSVD_PAGE2_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define AOAC_RSVD_PAGE2_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE2_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define AOAC_RSVD_PAGE2_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value) +#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE3_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define AOAC_RSVD_PAGE3_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE3_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define AOAC_RSVD_PAGE3_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define DBG_MSG_CTRL_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define DBG_MSG_CTRL_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define DBG_MSG_CTRL_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define DBG_MSG_CTRL_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define DBG_MSG_CTRL_GET_FUN_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define DBG_MSG_CTRL_SET_FUN_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define DBG_MSG_CTRL_GET_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 4) +#define DBG_MSG_CTRL_SET_MODE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 4, value) #endif diff --git a/hal/halmac/halmac_pcie_reg.h b/hal/halmac/halmac_pcie_reg.h index a8a4ee4..a2406be 100644 --- a/hal/halmac/halmac_pcie_reg.h +++ b/hal/halmac/halmac_pcie_reg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -17,14 +17,20 @@ #define __HALMAC_PCIE_REG_H__ /* PCIE PHY register */ -#define CLKCAL_CTRL_PHYPARA 0x00 -#define CLKCAL_SET_PHYPARA 0x20 -#define CLKCAL_TRG_VAL_PHYPARA 0x21 +#define RAC_CTRL_PPR 0x00 +#define RAC_SET_PPR 0x20 +#define RAC_TRG_PPR 0x21 + +/* PCIE CFG register */ #define PCIE_L1_BACKDOOR 0x719 +#define PCIE_ASPM_CTRL 0x70F /* PCIE MAC register */ -#define LINK_CTRL2_REG_OFFSET 0xA0 +#define LINK_CTRL2_REG_OFFSET 0xA0 #define GEN2_CTRL_OFFSET 0x80C -#define LINK_STATUS_REG_OFFSET 0x82 +#define LINK_STATUS_REG_OFFSET 0x82 + +#define PCIE_GEN1_SPEED 0x01 +#define PCIE_GEN2_SPEED 0x02 #endif/* __HALMAC_PCIE_REG_H__ */ diff --git a/hal/halmac/halmac_pwr_seq_cmd.h b/hal/halmac/halmac_pwr_seq_cmd.h index 5834f01..23d5dbe 100644 --- a/hal/halmac/halmac_pwr_seq_cmd.h +++ b/hal/halmac/halmac_pwr_seq_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -17,80 +17,72 @@ #define HALMAC_POWER_SEQUENCE_CMD #include "halmac_2_platform.h" -#include "halmac_type.h" -#define HALMAC_POLLING_READY_TIMEOUT_COUNT 20000 +#define HALMAC_PWR_POLLING_CNT 20000 /* -* The value of cmd : 4 bits -*/ + * The value of cmd : 4 bits + */ /* -* offset : the read register offset -* msk : the mask of the read value -* value : N/A, left by 0 -* Note : dirver shall implement this function by read & msk -*/ + * offset : the read register offset + * msk : the mask of the read value + * value : N/A, left by 0 + * Note : dirver shall implement this function by read & msk + */ #define HALMAC_PWR_CMD_READ 0x00 /* -* offset: the read register offset -* msk: the mask of the write bits -* value: write value -* Note: driver shall implement this cmd by read & msk after write -*/ + * offset: the read register offset + * msk: the mask of the write bits + * value: write value + * Note: driver shall implement this cmd by read & msk after write + */ #define HALMAC_PWR_CMD_WRITE 0x01 /* -* offset: the read register offset -* msk: the mask of the polled value -* value: the value to be polled, masked by the msd field. -* Note: driver shall implement this cmd by -* do{ -* if( (Read(offset) & msk) == (value & msk) ) -* break; -* } while(not timeout); -*/ + * offset: the read register offset + * msk: the mask of the polled value + * value: the value to be polled, masked by the msd field. + * Note: driver shall implement this cmd by + * do{ + * if( (Read(offset) & msk) == (value & msk) ) + * break; + * } while(not timeout); + */ #define HALMAC_PWR_CMD_POLLING 0x02 /* -* offset: the value to delay -* msk: N/A -* value: the unit of delay, 0: us, 1: ms -*/ + * offset: the value to delay + * msk: N/A + * value: the unit of delay, 0: us, 1: ms + */ #define HALMAC_PWR_CMD_DELAY 0x03 /* -* offset: N/A -* msk: N/A -* value: N/A -*/ -#define HALMAC_PWR_CMD_END 0x04 + * offset: N/A + * msk: N/A + * value: N/A + */ +#define HALMAC_PWR_CMD_END 0x04 /* -* The value of base : 4 bits -*/ + * The value of base : 4 bits + */ /* define the base address of each block */ -#define HALMAC_PWR_BASEADDR_MAC 0x00 -#define HALMAC_PWR_BASEADDR_USB 0x01 -#define HALMAC_PWR_BASEADDR_PCIE 0x02 -#define HALMAC_PWR_BASEADDR_SDIO 0x03 +#define HALMAC_PWR_ADDR_MAC 0x00 +#define HALMAC_PWR_ADDR_USB 0x01 +#define HALMAC_PWR_ADDR_PCIE 0x02 +#define HALMAC_PWR_ADDR_SDIO 0x03 /* -* The value of interface_msk : 4 bits -*/ + * The value of interface_msk : 4 bits + */ #define HALMAC_PWR_INTF_SDIO_MSK BIT(0) #define HALMAC_PWR_INTF_USB_MSK BIT(1) #define HALMAC_PWR_INTF_PCI_MSK BIT(2) #define HALMAC_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) /* -* The value of fab_msk : 4 bits -*/ -#define HALMAC_PWR_FAB_TSMC_MSK BIT(0) -#define HALMAC_PWR_FAB_UMC_MSK BIT(1) -#define HALMAC_PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) - -/* -* The value of cut_msk : 8 bits -*/ + * The value of cut_msk : 8 bits + */ #define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0) #define HALMAC_PWR_CUT_A_MSK BIT(1) #define HALMAC_PWR_CUT_B_MSK BIT(2) @@ -101,21 +93,19 @@ #define HALMAC_PWR_CUT_G_MSK BIT(7) #define HALMAC_PWR_CUT_ALL_MSK 0xFF -typedef enum _HALMAC_PWRSEQ_CMD_DELAY_UNIT_ { - HALMAC_PWRSEQ_DELAY_US, - HALMAC_PWRSEQ_DELAY_MS, -} HALMAC_PWRSEQ_DELAY_UNIT; +enum halmac_pwrseq_cmd_delay_unit { + HALMAC_PWR_DELAY_US, + HALMAC_PWR_DELAY_MS, +}; -/* Don't care endian issue, because element of pwer seq vector is fixed address */ -typedef struct _HALMAC_WL_PWR_CFG_ { +struct halmac_wlan_pwr_cfg { u16 offset; - u8 cut_msk; - u8 fab_msk:4; - u8 interface_msk:4; - u8 base:4; - u8 cmd:4; - u8 msk; - u8 value; -} HALMAC_WLAN_PWR_CFG, *PHALMAC_WLAN_PWR_CFG; + u8 cut_msk; + u8 interface_msk; + u8 base:4; + u8 cmd:4; + u8 msk; + u8 value; +}; #endif diff --git a/hal/halmac/halmac_reg2.h b/hal/halmac/halmac_reg2.h index f04e7bc..f20eaa4 100644 --- a/hal/halmac/halmac_reg2.h +++ b/hal/halmac/halmac_reg2.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,3160 +15,6868 @@ #ifndef __HALMAC_COM_REG_H__ #define __HALMAC_COM_REG_H__ -/*-------------------------Modification Log----------------------------------- - For Page0, it is based on Combo_And_WL_Only_Page0_Reg.xls SVN524 - The supported IC are 8723A, 8881A, 8723B, 8192E, 8881A - 8812A and 8188E is not included in page0 register - For other pages, it is based on MAC_Register.doc SVN502 - Most IC is the same with 8812A --------------------------Modification Log-----------------------------------*/ - -/*--------------------------Include File--------------------------------------*/ #include "halmac_hw_cfg.h" -/*--------------------------Include File--------------------------------------*/ +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) +#define REG_SYS_ISO_CTRL 0x0000 +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define REG_SYS_ISO_CTRL 0x0000 +#define REG_SDIO_TX_CTRL 0x10250000 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_TX_CTRL 0x10250000 +#define REG_SYS_FUNC_EN 0x0002 +#define REG_SYS_PW_CTRL 0x0004 #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SYS_FUNC_EN 0x0002 -#define REG_SYS_PW_CTRL 0x0004 -#define REG_SYS_CLK_CTRL 0x0008 -#define REG_SYS_EEPROM_CTRL 0x000A -#define REG_EE_VPD 0x000C -#define REG_SYS_SWR_CTRL1 0x0010 -#define REG_SYS_SWR_CTRL2 0x0014 +#define REG_SDIO_CMD11_VOL_SWITCH 0x10250004 +#define REG_SDIO_DRIVING 0x10250006 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HIMR 0x10250014 +#define REG_SYS_CLK_CTRL 0x0008 #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SYS_SWR_CTRL3 0x0018 +#define REG_SDIO_MONITOR 0x10250008 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HISR 0x10250018 +#define REG_SYS_EEPROM_CTRL 0x000A +#define REG_EE_VPD 0x000C #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RSV_CTRL 0x001C +#define REG_SDIO_MONITOR_2 0x1025000C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_RX_REQ_LEN 0x1025001C +#define REG_SYS_SWR_CTRL1 0x0010 +#define REG_SYS_SWR_CTRL2 0x0014 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RF_CTRL 0x001F +#define REG_SDIO_HIMR 0x10250014 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_RF0_CTRL 0x001F +#define REG_SYS_SWR_CTRL3 0x0018 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F +#define REG_SDIO_HISR 0x10250018 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AFE_LDO_CTRL 0x0020 +#define REG_RSV_CTRL 0x001C #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_FREE_TXPG 0x10250020 +#define REG_SDIO_RX_REQ_LEN 0x1025001C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AFE_CTRL1 0x0024 +#define REG_RF_CTRL 0x001F #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_FREE_TXPG2 0x10250024 +#define REG_RF0_CTRL 0x001F #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AFE_CTRL2 0x0028 +#define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028 +#define REG_AFE_LDO_CTRL 0x0020 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AFE_CTRL3 0x002C -#define REG_EFUSE_CTRL 0x0030 +#define REG_SDIO_FREE_TXPG 0x10250020 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HTSFR_INFO 0x10250030 +#define REG_AFE_CTRL1 0x0024 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_LDO_EFUSE_CTRL 0x0034 -#define REG_PWR_OPTION_CTRL 0x0038 +#define REG_SDIO_FREE_TXPG2 0x10250024 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HCPWM1_V2 0x10250038 -#define REG_SDIO_HCPWM2_V2 0x1025003A +#define REG_AFE_CTRL2 0x0028 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028 + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define REG_CAL_TIMER 0x003C -#define REG_ACLK_MON 0x003E -#define REG_GPIO_MUXCFG 0x0040 +#define REG_ANAPARSW_POW_MAC 0x0028 +#define REG_ANAPARLDO_POW_MAC 0x0029 +#define REG_ANAPAR_POW_MAC 0x002A +#define REG_ANAPAR_POW_XTAL 0x002B #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_AFE_CTRL3 0x002C + +#endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define REG_SDIO_INDIRECT_REG_CFG 0x10250040 +#define REG_ANAPARLDO_MAC 0x002C #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define REG_SDIO_TXPKT_EMPTY 0x1025002C -#define REG_GPIO_PIN_CTRL 0x0044 +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_EFUSE_CTRL 0x0030 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SDIO_HTSFR_INFO 0x10250030 -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define REG_SDIO_INDIRECT_REG_DATA 0x10250044 +#define REG_LDO_EFUSE_CTRL 0x0034 +#define REG_PWR_OPTION_CTRL 0x0038 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SDIO_HCPWM1_V2 0x10250038 +#define REG_SDIO_HCPWM2_V2 0x1025003A + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define REG_GPIO_INTM 0x0048 -#define REG_LED_CFG 0x004C -#define REG_FSIMR 0x0050 -#define REG_FSISR 0x0054 -#define REG_HSIMR 0x0058 -#define REG_HSISR 0x005C -#define REG_GPIO_EXT_CTRL 0x0060 +#define REG_CAL_TIMER 0x003C +#define REG_ACLK_MON 0x003E #endif +#if (HALMAC_8822C_SUPPORT) + +#define REG_GPIO_MUXCFG_2 0x003F + +#endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define REG_SDIO_H2C 0x10250060 +#define REG_GPIO_MUXCFG 0x0040 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define REG_SDIO_INDIRECT_REG_CFG 0x10250040 -#define REG_PAD_CTRL1 0x0064 +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_GPIO_PIN_CTRL 0x0044 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SDIO_INDIRECT_REG_DATA 0x10250044 -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define REG_SDIO_C2H 0x10250064 +#define REG_GPIO_INTM 0x0048 +#define REG_LED_CFG 0x004C +#define REG_FSIMR 0x0050 +#define REG_FSISR 0x0054 +#define REG_HSIMR 0x0058 +#define REG_HSISR 0x005C +#define REG_GPIO_EXT_CTRL 0x0060 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SDIO_H2C 0x10250060 + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define REG_WL_BT_PWR_CTRL 0x0068 +#define REG_PAD_CTRL1 0x0064 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SDIO_C2H 0x10250064 + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define REG_SDM_DEBUG 0x006C +#define REG_WL_BT_PWR_CTRL 0x0068 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_SDM_DEBUG 0x006C + +#endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define REG_GSSR 0x006C +#define REG_GSSR 0x006C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SYS_SDIO_CTRL 0x0070 +#define REG_SYS_SDIO_CTRL 0x0070 #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define REG_SYS_CLKR 0x0070 +#define REG_SYS_CLKR 0x0070 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_HCI_OPT_CTRL 0x0074 +#define REG_HCI_OPT_CTRL 0x0074 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AFE_CTRL4 0x0078 +#define REG_AFE_CTRL4 0x0078 #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define REG_AFE_XTAL_CTRL_EXT 0x0078 +#define REG_AFE_XTAL_CTRL_EXT 0x0078 #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_LDO_SWR_CTRL 0x007C +#define REG_HCI_BG_CTRL 0x0078 +#define REG_HCI_LDO_CTRL 0x007A #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_LDO_SWR_CTRL 0x007C + +#endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_8051FW_CTRL 0x0080 +#define REG_8051FW_CTRL 0x0080 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_MCUFW_CTRL 0x0080 +#define REG_MCUFW_CTRL 0x0080 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HRPWM1 0x10250080 -#define REG_SDIO_HRPWM2 0x10250082 +#define REG_SDIO_HRPWM1 0x10250080 +#define REG_SDIO_HRPWM2 0x10250082 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MCU_TST_CFG 0x0084 +#define REG_MCU_TST_CFG 0x0084 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HPS_CLKR 0x10250084 -#define REG_SDIO_BUS_CTRL 0x10250085 +#define REG_SDIO_HPS_CLKR 0x10250084 +#define REG_SDIO_BUS_CTRL 0x10250085 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HSUS_CTRL 0x10250086 +#define REG_SDIO_HSUS_CTRL 0x10250086 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_HMEBOX_E0_E1 0x0088 +#define REG_HMEBOX_E0_E1 0x0088 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_RESPONSE_TIMER 0x10250088 +#define REG_SDIO_RESPONSE_TIMER 0x10250088 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_CMD_CRC 0x1025008A +#define REG_SDIO_CMD_CRC 0x1025008A #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_HMEBOX_E2_E3 0x008C -#define REG_WLLPS_CTRL 0x0090 +#define REG_HMEBOX_E2_E3 0x008C +#define REG_WLLPS_CTRL 0x0090 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HSISR 0x10250090 -#define REG_SDIO_HSIMR 0x10250091 +#define REG_SDIO_HSISR 0x10250090 #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_AFE_CTRL5 0x0094 +#define REG_SDIO_HSIMR 0x10250091 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_GPIO_DEBOUNCE_CTRL 0x0098 -#define REG_RPWM2 0x009C -#define REG_SYSON_FSM_MON 0x00A0 +#define REG_AFE_CTRL5 0x0094 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_AFE_CTRL6 0x00A4 +#define REG_GPIO_DEBOUNCE_CTRL 0x0098 +#define REG_RPWM2 0x009C +#define REG_SYSON_FSM_MON 0x00A0 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PMC_DBG_CTRL1 0x00A8 +#define REG_AFE_CTRL6 0x00A4 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_AFE_CTRL7 0x00AC +#define REG_PMC_DBG_CTRL1 0x00A8 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_HIMR0 0x00B0 -#define REG_HISR0 0x00B4 -#define REG_HIMR1 0x00B8 -#define REG_HISR1 0x00BC -#define REG_DBG_PORT_SEL 0x00C0 +#define REG_AFE_CTRL7 0x00AC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_ERR_RPT 0x102500C0 -#define REG_SDIO_CMD_ERRCNT 0x102500C1 -#define REG_SDIO_DATA_ERRCNT 0x102500C2 +#define REG_HIMR0 0x00B0 +#define REG_HISR0 0x00B4 +#define REG_HIMR1 0x00B8 +#define REG_HISR1 0x00BC +#define REG_DBG_PORT_SEL 0x00C0 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define REG_SDIO_ERR_RPT 0x102500C0 -#define REG_PAD_CTRL2 0x00C4 +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define REG_SDIO_DIOERR_RPT 0x102500C0 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SDIO_CMD_ERRCNT 0x102500C2 +#define REG_SDIO_DATA_ERRCNT 0x102500C3 -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define REG_SDIO_CMD_ERR_CONTENT 0x102500C4 +#define REG_PAD_CTRL2 0x00C4 #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SDIO_CMD_ERR_CONTENT 0x102500C4 + +#endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define REG_MEM_RMC 0x00C8 +#define REG_MEM_RMC 0x00C8 + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SDIO_CRC_ERR_IDX 0x102500C9 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_SDIO_DATA_CRC 0x102500CA + +#endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define REG_SDIO_CRC_ERR_IDX 0x102500C9 -#define REG_SDIO_DATA_CRC 0x102500CA -#define REG_SDIO_DATA_REPLY_TIME 0x102500CB +#define REG_SDIO_DATA_REPLY_TIME 0x102500CB #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_PMC_DBG_CTRL2 0x00CC + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8822C_SUPPORT) -#define REG_PMC_DBG_CTRL2 0x00CC -#define REG_BIST_CTRL 0x00D0 -#define REG_BIST_RPT 0x00D4 -#define REG_MEM_CTRL 0x00D8 +#define REG_SDIO_TRANS_FIFO_STATUS 0x102500CC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define REG_BIST_CTRL 0x00D0 +#define REG_BIST_RPT 0x00D4 -#define REG_AFE_CTRL8 0x00DC +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_MEM_CTRL 0x00D8 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) + +#define REG_AFE_CTRL8 0x00DC + +#endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define REG_WLAN_DBG 0x00DC +#define REG_WLAN_DBG 0x00DC #endif +#if (HALMAC_8814B_SUPPORT) + +#define REG_SYN_RFC_CTRL 0x00DC + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_USB_SIE_INTF 0x00E0 -#define REG_PCIE_MIO_INTF 0x00E4 -#define REG_PCIE_MIO_INTD 0x00E8 +#define REG_USB_SIE_INTF 0x00E0 #endif +#if (HALMAC_8198F_SUPPORT) + +#define REG_SYS_PINMUX 0x00E0 + +#endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define REG_WLRF1 0x00EC +#define REG_PCIE_MIO_INTF 0x00E4 +#define REG_PCIE_MIO_INTD 0x00E8 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_WLRF1 0x00EC + +#endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define REG_HPON_FSM 0x00EC +#define REG_HPON_FSM 0x00EC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SYS_CFG1 0x00F0 -#define REG_SYS_STATUS1 0x00F4 -#define REG_SYS_STATUS2 0x00F8 -#define REG_SYS_CFG2 0x00FC -#define REG_CR 0x0100 +#define REG_SYS_CFG1 0x00F0 +#define REG_SYS_STATUS1 0x00F4 +#define REG_SYS_STATUS2 0x00F8 +#define REG_SYS_CFG2 0x00FC +#define REG_CR 0x0100 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 +#define REG_PG_SIZE 0x0104 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TSF_CLK_STATE 0x0108 -#define REG_TXDMA_PQ_MAP 0x010C -#define REG_TRXFF_BNDY 0x0114 +#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PTA_I2C_MBOX 0x0118 +#define REG_TSF_CLK_STATE 0x0108 +#define REG_TXDMA_PQ_MAP 0x010C +#define REG_TRXFF_BNDY 0x0114 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PTA_I2C_MBOX 0x0118 + +#endif #if (HALMAC_8814A_SUPPORT) -#define REG_FF_STATUS 0x0118 +#define REG_FF_STATUS 0x0118 #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_RXFF_PTR 0x011C +#define REG_RXFF_PTR 0x011C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RXFF_BNDY 0x011C +#define REG_RXFF_BNDY 0x011C #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_FEIMR 0x0120 +#define REG_FEIMR 0x0120 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FE1IMR 0x0120 +#define REG_FE1IMR 0x0120 #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_FEISR 0x0124 +#define REG_FEISR 0x0124 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FE1ISR 0x0124 -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define REG_FE1ISR 0x0124 +#define REG_CPWM 0x012C +#define REG_FWIMR 0x0130 +#define REG_FWISR 0x0134 +#define REG_FTIMR 0x0138 +#define REG_FTISR 0x013C +#define REG_PKTBUF_DBG_CTRL 0x0140 +#define REG_PKTBUF_DBG_DATA_L 0x0144 +#define REG_PKTBUF_DBG_DATA_H 0x0148 +#define REG_CPWM2 0x014C +#define REG_TC0_CTRL 0x0150 +#define REG_TC1_CTRL 0x0154 +#define REG_TC2_CTRL 0x0158 +#define REG_TC3_CTRL 0x015C +#define REG_TC4_CTRL 0x0160 +#define REG_TCUNIT_BASE 0x0164 +#define REG_TC5_CTRL 0x0168 +#define REG_TC6_CTRL 0x016C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_MBIST_FAIL 0x0170 + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define REG_CPWM 0x012C -#define REG_FWIMR 0x0130 -#define REG_FWISR 0x0134 -#define REG_FTIMR 0x0138 -#define REG_FTISR 0x013C -#define REG_PKTBUF_DBG_CTRL 0x0140 -#define REG_PKTBUF_DBG_DATA_L 0x0144 -#define REG_PKTBUF_DBG_DATA_H 0x0148 -#define REG_CPWM2 0x014C -#define REG_TC0_CTRL 0x0150 -#define REG_TC1_CTRL 0x0154 -#define REG_TC2_CTRL 0x0158 -#define REG_TC3_CTRL 0x015C -#define REG_TC4_CTRL 0x0160 -#define REG_TCUNIT_BASE 0x0164 -#define REG_TC5_CTRL 0x0168 -#define REG_TC6_CTRL 0x016C -#define REG_MBIST_FAIL 0x0170 -#define REG_MBIST_START_PAUSE 0x0174 -#define REG_MBIST_DONE 0x0178 +#define REG_MBIST_DRF_FAIL 0x0170 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MBIST_START_PAUSE 0x0174 +#define REG_MBIST_DONE 0x0178 + +#endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_MBIST_ROM_CRC_DATA 0x017C +#define REG_MBIST_ROM_CRC_DATA 0x017C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_MBIST_FAIL_NRML 0x017C +#define REG_MBIST_FAIL_NRML 0x017C #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AES_DECRPT_DATA 0x0180 -#define REG_AES_DECRPT_CFG 0x0184 +#define REG_MBIST_READ_BIST_RPT 0x017C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_MACCLKFRQ 0x018C +#define REG_AES_DECRPT_DATA 0x0180 +#define REG_AES_DECRPT_CFG 0x0184 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_HIOE_CTRL 0x0188 -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define REG_TMETER 0x0190 -#define REG_OSC_32K_CTRL 0x0194 -#define REG_32K_CAL_REG1 0x0198 -#define REG_C2HEVT 0x01A0 +#define REG_MACCLKFRQ 0x018C #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define REG_HIOE_CFG_FILE 0x018C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define REG_C2HEVT_1 0x01A4 -#define REG_C2HEVT_2 0x01A8 -#define REG_C2HEVT_3 0x01AC +#define REG_TMETER 0x0190 +#define REG_OSC_32K_CTRL 0x0194 +#define REG_32K_CAL_REG1 0x0198 +#define REG_C2HEVT 0x01A0 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_C2HEVT_1 0x01A4 +#define REG_C2HEVT_2 0x01A8 +#define REG_C2HEVT_3 0x01AC + +#endif #if (HALMAC_8814A_SUPPORT) -#define REG_TC7_CTRL 0x01B0 -#define REG_TC8_CTRL 0x01B4 +#define REG_TC7_CTRL 0x01B0 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SW_DEFINED_PAGE1 0x01B8 +#define REG_RXDESC_BUFF_RPTR 0x01B0 #endif +#if (HALMAC_8814A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_SW_DEFINED_PAGE2 0x01BC +#define REG_TC8_CTRL 0x01B4 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MCUTST_I 0x01C0 -#define REG_MCUTST_II 0x01C4 -#define REG_FMETHR 0x01C8 -#define REG_HMETFR 0x01CC -#define REG_HMEBOX0 0x01D0 -#define REG_HMEBOX1 0x01D4 -#define REG_HMEBOX2 0x01D8 -#define REG_HMEBOX3 0x01DC -#define REG_LLT_INIT 0x01E0 +#define REG_RXDESC_BUFF_WPTR 0x01B4 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_GENTST 0x01E4 +#define REG_SW_DEFINED_PAGE1 0x01B8 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_LLT_INIT_ADDR 0x01E4 +#define REG_SW_DEFINED_PAGE2 0x01BC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BB_ACCESS_CTRL 0x01E8 -#define REG_BB_ACCESS_DATA 0x01EC -#define REG_HMEBOX_E0 0x01F0 -#define REG_HMEBOX_E1 0x01F4 -#define REG_HMEBOX_E2 0x01F8 -#define REG_HMEBOX_E3 0x01FC +#define REG_MCUTST_I 0x01C0 +#define REG_MCUTST_II 0x01C4 +#define REG_FMETHR 0x01C8 +#define REG_HMETFR 0x01CC +#define REG_HMEBOX0 0x01D0 +#define REG_HMEBOX1 0x01D4 +#define REG_HMEBOX2 0x01D8 +#define REG_HMEBOX3 0x01DC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RQPN_CTRL_HLPQ 0x0200 +#define REG_LLT_INIT 0x01E0 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FIFOPAGE_CTRL_1 0x0200 +#define REG_RXDESC_BUFF_BNDY 0x01E0 #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_FIFOPAGE_INFO 0x0204 +#define REG_GENTST 0x01E4 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FIFOPAGE_CTRL_2 0x0204 +#define REG_LLT_INIT_ADDR 0x01E4 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_BB_ACCESS_CTRL 0x01E8 +#define REG_BB_ACCESS_DATA 0x01EC +#define REG_HMEBOX_E0 0x01F0 +#define REG_HMEBOX_E1 0x01F4 +#define REG_HMEBOX_E2 0x01F8 +#define REG_HMEBOX_E3 0x01FC + +#endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_DWBCN0_CTRL 0x0208 +#define REG_RQPN_CTRL_HLPQ 0x0200 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_AUTO_LLT_V1 0x0208 +#define REG_FIFOPAGE_CTRL_1 0x0200 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TXDMA_OFFSET_CHK 0x020C -#define REG_TXDMA_STATUS 0x0210 +#define REG_BCN_CTRL_0 0x0200 #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_RQPN_NPQ 0x0214 +#define REG_FIFOPAGE_INFO 0x0204 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TX_DMA_DBG 0x0214 +#define REG_FIFOPAGE_CTRL_2 0x0204 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TQPNT1 0x0218 -#define REG_TQPNT2 0x021C +#define REG_BCN_CTRL_1 0x0204 #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_TDE_DEBUG 0x0220 +#define REG_DWBCN0_CTRL 0x0208 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TQPNT3 0x0220 +#define REG_AUTO_LLT_V1 0x0208 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_TXDMA_OFFSET_CHK 0x020C +#define REG_TXDMA_STATUS 0x0210 + +#endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_AUTO_LLT 0x0224 +#define REG_RQPN_NPQ 0x0214 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TQPNT4 0x0224 +#define REG_TX_DMA_DBG 0x0214 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_DWBCN1_CTRL 0x0228 +#define REG_TQPNT1 0x0218 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RQPN_CTRL_1 0x0228 -#define REG_RQPN_CTRL_2 0x022C -#define REG_FIFOPAGE_INFO_1 0x0230 -#define REG_FIFOPAGE_INFO_2 0x0234 -#define REG_FIFOPAGE_INFO_3 0x0238 -#define REG_FIFOPAGE_INFO_4 0x023C -#define REG_FIFOPAGE_INFO_5 0x0240 +#define REG_DMA_RQPN_INFO_PUB 0x0218 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_H2C_HEAD 0x0244 -#define REG_H2C_TAIL 0x0248 -#define REG_H2C_READ_ADDR 0x024C -#define REG_H2C_WR_ADDR 0x0250 -#define REG_H2C_INFO 0x0254 +#define REG_TQPNT2 0x021C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RXDMA_AGG_PG_TH 0x0280 -#define REG_RXPKT_NUM 0x0284 -#define REG_RXDMA_STATUS 0x0288 -#define REG_RXDMA_DPR 0x028C -#define REG_RXDMA_MODE 0x0290 -#define REG_C2H_PKT 0x0294 +#define REG_RQPN_CTRL_2_V1 0x021C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FWFF_C2H 0x0298 -#define REG_FWFF_CTRL 0x029C -#define REG_FWFF_PKT_INFO 0x02A0 +#define REG_TDE_DEBUG 0x0220 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_FC2H_INFO 0x02A6 +#define REG_TQPNT3 0x0220 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_PCIE_CTRL 0x0300 +#define REG_BCN_CTRL_2 0x0220 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_CTRL 0x0300 +#define REG_AUTO_LLT 0x0224 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_LX_CTRL1 0x0300 +#define REG_TQPNT4 0x0224 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_INT_MIG 0x0304 -#define REG_BCNQ_TXBD_DESA 0x0308 -#define REG_MGQ_TXBD_DESA 0x0310 -#define REG_VOQ_TXBD_DESA 0x0318 -#define REG_VIQ_TXBD_DESA 0x0320 -#define REG_BEQ_TXBD_DESA 0x0328 -#define REG_BKQ_TXBD_DESA 0x0330 -#define REG_RXQ_RXBD_DESA 0x0338 -#define REG_HI0Q_TXBD_DESA 0x0340 -#define REG_HI1Q_TXBD_DESA 0x0348 -#define REG_HI2Q_TXBD_DESA 0x0350 -#define REG_HI3Q_TXBD_DESA 0x0358 -#define REG_HI4Q_TXBD_DESA 0x0360 -#define REG_HI5Q_TXBD_DESA 0x0368 -#define REG_HI6Q_TXBD_DESA 0x0370 -#define REG_HI7Q_TXBD_DESA 0x0378 -#define REG_MGQ_TXBD_NUM 0x0380 -#define REG_RX_RXBD_NUM 0x0382 -#define REG_VOQ_TXBD_NUM 0x0384 -#define REG_VIQ_TXBD_NUM 0x0386 -#define REG_BEQ_TXBD_NUM 0x0388 -#define REG_BKQ_TXBD_NUM 0x038A -#define REG_HI0Q_TXBD_NUM 0x038C -#define REG_HI1Q_TXBD_NUM 0x038E -#define REG_HI2Q_TXBD_NUM 0x0390 -#define REG_HI3Q_TXBD_NUM 0x0392 -#define REG_HI4Q_TXBD_NUM 0x0394 -#define REG_HI5Q_TXBD_NUM 0x0396 -#define REG_HI6Q_TXBD_NUM 0x0398 -#define REG_HI7Q_TXBD_NUM 0x039A -#define REG_TSFTIMER_HCI 0x039C -#define REG_BD_RWPTR_CLR 0x039C -#define REG_VOQ_TXBD_IDX 0x03A0 -#define REG_VIQ_TXBD_IDX 0x03A4 -#define REG_BEQ_TXBD_IDX 0x03A8 -#define REG_BKQ_TXBD_IDX 0x03AC -#define REG_MGQ_TXBD_IDX 0x03B0 -#define REG_RXQ_RXBD_IDX 0x03B4 -#define REG_HI0Q_TXBD_IDX 0x03B8 -#define REG_HI1Q_TXBD_IDX 0x03BC -#define REG_HI2Q_TXBD_IDX 0x03C0 -#define REG_HI3Q_TXBD_IDX 0x03C4 -#define REG_HI4Q_TXBD_IDX 0x03C8 -#define REG_HI5Q_TXBD_IDX 0x03CC -#define REG_HI6Q_TXBD_IDX 0x03D0 -#define REG_HI7Q_TXBD_IDX 0x03D4 +#define REG_DWBCN1_CTRL 0x0228 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DBG_SEL_V1 0x03D8 +#define REG_RQPN_CTRL_1 0x0228 +#define REG_RQPN_CTRL_2 0x022C +#define REG_FIFOPAGE_INFO_1 0x0230 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PCIE_HRPWM1_V1 0x03D9 +#define REG_TXPKTNUM_0 0x0230 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_HRPWM1_V1 0x03D9 +#define REG_FIFOPAGE_INFO_2 0x0234 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PCIE_HCPWM1_V1 0x03DA +#define REG_TXPKTNUM_1 0x0234 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_HCPWM1_V1 0x03DA +#define REG_FIFOPAGE_INFO_3 0x0238 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_PCIE_CTRL2 0x03DB +#define REG_TXPKTNUM_2 0x0238 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_CTRL2 0x03DB +#define REG_FIFOPAGE_INFO_4 0x023C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_LX_CTRL2 0x03DB +#define REG_TXPKTNUM_3 0x023C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PCIE_HRPWM2_V1 0x03DC +#define REG_FIFOPAGE_INFO_5 0x0240 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_HRPWM2_V1 0x03DC +#define REG_TX_AGG_ALIGN 0x0240 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PCIE_HCPWM2_V1 0x03DE +#define REG_H2C_HEAD 0x0244 +#define REG_H2C_TAIL 0x0248 +#define REG_H2C_READ_ADDR 0x024C +#define REG_H2C_WR_ADDR 0x0250 +#define REG_H2C_INFO 0x0254 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_HCPWM2_V1 0x03DE +#define REG_TQPNT5 0x0260 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PCIE_H2C_MSG_V1 0x03E0 +#define REG_DMA_OQT_0 0x0260 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_H2C_MSG_V1 0x03E0 +#define REG_TQPNT6 0x0264 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PCIE_C2H_MSG_V1 0x03E4 +#define REG_DMA_OQT_1 0x0264 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_C2H_MSG_V1 0x03E4 +#define REG_FIFOPAGE_INFO_6 0x0268 +#define REG_FIFOPAGE_INFO_7 0x026C #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DBI_WDATA_V1 0x03E8 +#define REG_PGSUB_CNT 0x026C +#define REG_PGSUB_H 0x0270 +#define REG_PGSUB_N 0x0274 +#define REG_PGSUB_L 0x0278 +#define REG_PGSUB_E 0x027C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_LX_DMA_ISR 0x03E8 +#define REG_RXDMA_AGG_PG_TH 0x0280 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DBI_RDATA_V1 0x03EC +#define REG_RXPKT_NUM 0x0284 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_LX_DMA_IMR 0x03EC +#define REG_RXDMA_CTRL 0x0284 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DBI_FLAG_V1 0x03F0 +#define REG_RXDMA_STATUS 0x0288 +#define REG_RXDMA_DPR 0x028C +#define REG_RXDMA_MODE 0x0290 +#define REG_C2H_PKT 0x0294 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_STUCK_FLAG_V1 0x03F0 +#define REG_FWFF_C2H 0x0298 +#define REG_FWFF_CTRL 0x029C +#define REG_FWFF_PKT_INFO 0x02A0 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_LX_DMA_DBG 0x03F0 +#define REG_FC2H_INFO 0x02A4 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_MDIO_V1 0x03F4 +#define REG_FWFF_PKT_INFO2 0x02A4 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) - -#define REG_MDIO2_V1 0x03F8 +#define REG_RXPKTNUM 0x02B0 +#define REG_RXPKTNUM_TH 0x02B4 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_WDT_CFG 0x03F8 +#define REG_FW_UPD_RXDES_RDPTR 0x02B8 #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_PCIE_MIX_CFG 0x03F8 +#define REG_FW_MSG1 0x02E0 +#define REG_FW_MSG2 0x02E4 +#define REG_FW_MSG3 0x02E8 +#define REG_FW_MSG4 0x02EC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_BUS_MIX_CFG 0x03F8 +#define REG_PCIE_CTRL 0x0300 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_HCI_MIX_CFG 0x03FC +#define REG_HCI_CTRL 0x0300 #endif - #if (HALMAC_8881A_SUPPORT) -#define REG_BUS_MIX_CFG1 0x03FC +#define REG_LX_CTRL1 0x0300 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_Q0_INFO 0x0400 -#define REG_Q1_INFO 0x0404 -#define REG_Q2_INFO 0x0408 -#define REG_Q3_INFO 0x040C -#define REG_MGQ_INFO 0x0410 -#define REG_HIQ_INFO 0x0414 -#define REG_BCNQ_INFO 0x0418 -#define REG_TXPKT_EMPTY 0x041A -#define REG_CPU_MGQ_INFO 0x041C -#define REG_FWHW_TXQ_CTRL 0x0420 +#define REG_INT_MIG 0x0304 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_HWSEQ_CTRL 0x0423 +#define REG_ACH_CTRL 0x0304 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DATAFB_SEL 0x0423 +#define REG_BCNQ_TXBD_DESA 0x0308 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BCNQ_BDNY 0x0424 +#define REG_HIQ_CTRL 0x0308 +#define REG_INT_MIG_V1 0x030C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BCNQ_BDNY_V1 0x0424 +#define REG_MGQ_TXBD_DESA 0x0310 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MGQ_BDNY 0x0425 +#define REG_P0MGQ_TXBD_DESA_L 0x0310 +#define REG_P0MGQ_TXBD_DESA_H 0x0314 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_LIFETIME_EN 0x0426 +#define REG_VOQ_TXBD_DESA 0x0318 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_FW_FREE_TAIL 0x0427 +#define REG_ACH0_TXBD_DESA_L 0x0318 +#define REG_ACH0_TXBD_DESA_H 0x031C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SPEC_SIFS 0x0428 -#define REG_RETRY_LIMIT 0x042A -#define REG_TXBF_CTRL 0x042C -#define REG_DARFRC 0x0430 -#define REG_RARFRC 0x0438 -#define REG_RRSR 0x0440 -#define REG_ARFR0 0x0444 -#define REG_ARFR1_V1 0x044C -#define REG_CCK_CHECK 0x0454 +#define REG_VIQ_TXBD_DESA 0x0320 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AMPDU_BURST_CTRL 0x0455 +#define REG_ACH1_TXBD_DESA_L 0x0320 +#define REG_ACH1_TXBD_DESA_H 0x0324 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_AMPDU_MAX_TIME_V1 0x0455 +#define REG_BEQ_TXBD_DESA 0x0328 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AMPDU_MAX_TIME 0x0456 +#define REG_ACH2_TXBD_DESA_L 0x0328 +#define REG_ACH2_TXBD_DESA_H 0x032C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BCNQ1_BDNY_V1 0x0456 +#define REG_BKQ_TXBD_DESA 0x0330 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BCNQ1_BDNY 0x0457 +#define REG_ACH3_TXBD_DESA_L 0x0330 +#define REG_ACH3_TXBD_DESA_H 0x0334 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AMPDU_MAX_LENGTH 0x0458 -#define REG_ACQ_STOP 0x045C +#define REG_RXQ_RXBD_DESA 0x0338 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WMAC_LBK_BUF_HD 0x045D +#define REG_P0RXQ_RXBD_DESA_L 0x0338 +#define REG_P0RXQ_RXBD_DESA_H 0x033C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define REG_HI0Q_TXBD_DESA 0x0340 -#define REG_NDPA_RATE 0x045D +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0BCNQ_TXBD_DESA_L 0x0340 +#define REG_P0BCNQ_TXBD_DESA_H 0x0344 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI1Q_TXBD_DESA 0x0348 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_FWCMDQ_TXBD_DESA_L 0x0348 +#define REG_FWCMDQ_TXBD_DESA_H 0x034C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI2Q_TXBD_DESA 0x0350 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_HRPWM1_HCPWM1_DCPU 0x0354 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI3Q_TXBD_DESA 0x0358 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0_MPRT_BCNQ_TXBD_DESA_L 0x0358 +#define REG_P0_MPRT_BCNQ_TXBD_DESA_H 0x035C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI4Q_TXBD_DESA 0x0360 +#define REG_HI5Q_TXBD_DESA 0x0368 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0_MPRT_BCNQ_TXRXBD_NUM 0x036C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI6Q_TXBD_DESA 0x0370 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_BD_RWPTR_CLR2 0x0370 +#define REG_BD_RWPTR_CLR3 0x0374 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI7Q_TXBD_DESA 0x0378 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0MGQ_RXQ_TXRXBD_NUM 0x0378 +#define REG_CHNL_DMA_CFG 0x037C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MGQ_TXBD_NUM 0x0380 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_FWCMDQ_TXBD_NUM 0x0380 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RX_RXBD_NUM 0x0382 +#define REG_VOQ_TXBD_NUM 0x0384 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH0_ACH1_TXBD_NUM 0x0384 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_VIQ_TXBD_NUM 0x0386 +#define REG_BEQ_TXBD_NUM 0x0388 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH2_ACH3_TXBD_NUM 0x0388 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BKQ_TXBD_NUM 0x038A +#define REG_HI0Q_TXBD_NUM 0x038C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI0Q_HI1Q_TXBD_NUM 0x038C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI1Q_TXBD_NUM 0x038E +#define REG_HI2Q_TXBD_NUM 0x0390 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI2Q_HI3Q_TXBD_NUM 0x0390 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI3Q_TXBD_NUM 0x0392 +#define REG_HI4Q_TXBD_NUM 0x0394 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI4Q_HI5Q_TXBD_NUM 0x0394 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI5Q_TXBD_NUM 0x0396 +#define REG_HI6Q_TXBD_NUM 0x0398 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI6Q_HI7Q_TXBD_NUM 0x0398 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI7Q_TXBD_NUM 0x039A + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_TSFTIMER_HCI 0x039C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BD_RWPTR_CLR 0x039C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_BD_RWPTR_CLR1 0x039C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_VOQ_TXBD_IDX 0x03A0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH0_TXBD_IDX 0x03A0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_VIQ_TXBD_IDX 0x03A4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH1_TXBD_IDX 0x03A4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BEQ_TXBD_IDX 0x03A8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH2_TXBD_IDX 0x03A8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BKQ_TXBD_IDX 0x03AC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH3_TXBD_IDX 0x03AC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MGQ_TXBD_IDX 0x03B0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0MGQ_TXBD_IDX 0x03B0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RXQ_RXBD_IDX 0x03B4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0RXQ_RXBD_IDX 0x03B4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI0Q_TXBD_IDX 0x03B8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI0Q_TXBD_IDX 0x03B8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI1Q_TXBD_IDX 0x03BC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI1Q_TXBD_IDX 0x03BC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI2Q_TXBD_IDX 0x03C0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI2Q_TXBD_IDX 0x03C0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI3Q_TXBD_IDX 0x03C4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI3Q_TXBD_IDX 0x03C4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI4Q_TXBD_IDX 0x03C8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI4Q_TXBD_IDX 0x03C8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI5Q_TXBD_IDX 0x03CC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI5Q_TXBD_IDX 0x03CC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI6Q_TXBD_IDX 0x03D0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI6Q_TXBD_IDX 0x03D0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI7Q_TXBD_IDX 0x03D4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI7Q_TXBD_IDX 0x03D4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_DBG_SEL_V1 0x03D8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1 0x03D8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_PCIE_HRPWM1_V1 0x03D9 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_HRPWM1_V1 0x03D9 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_PCIE_HCPWM1_V1 0x03DA + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_HCPWM1_V1 0x03DA + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_PCIE_CTRL2 0x03DB + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_CTRL2 0x03DB + +#endif + +#if (HALMAC_8881A_SUPPORT) + +#define REG_LX_CTRL2 0x03DB + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_PCIE_HRPWM2_V1 0x03DC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_HRPWM2_V1 0x03DC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_HRPWM2_HCPWM2_V1 0x03DC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_PCIE_HCPWM2_V1 0x03DE + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_HCPWM2_V1 0x03DE + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PCIE_H2C_MSG_V1 0x03E0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_H2C_MSG_V1 0x03E0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PCIE_C2H_MSG_V1 0x03E4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_C2H_MSG_V1 0x03E4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_DBI_WDATA_V1 0x03E8 + +#endif + +#if (HALMAC_8881A_SUPPORT) + +#define REG_LX_DMA_ISR 0x03E8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_DBI_RDATA_V1 0x03EC + +#endif + +#if (HALMAC_8881A_SUPPORT) + +#define REG_LX_DMA_IMR 0x03EC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_DBI_FLAG_V1 0x03F0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_STUCK_FLAG_V1 0x03F0 + +#endif + +#if (HALMAC_8881A_SUPPORT) + +#define REG_LX_DMA_DBG 0x03F0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MDIO_V1 0x03F4 + +#endif + +#if (HALMAC_8192E_SUPPORT) + +#define REG_MDIO2_V1 0x03F8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_WDT_CFG 0x03F8 + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_PCIE_MIX_CFG 0x03F8 + +#endif + +#if (HALMAC_8881A_SUPPORT) + +#define REG_BUS_MIX_CFG 0x03F8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_HCI_MIX_CFG 0x03FC + +#endif + +#if (HALMAC_8881A_SUPPORT) + +#define REG_BUS_MIX_CFG1 0x03FC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_Q0_INFO 0x0400 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_QUEUE_INFO1 0x0400 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_QUEUELIST_INFO0 0x0400 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_Q1_INFO 0x0404 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_QUEUE_INFO2 0x0404 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_QUEUELIST_INFO1 0x0404 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_Q2_INFO 0x0408 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_QUEUE_INFO3 0x0408 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_QUEUELIST_INFO2 0x0408 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_Q3_INFO 0x040C + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_QINFO_INDEX 0x040C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_QUEUELIST_INFO3 0x040C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MGQ_INFO 0x0410 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_QUEUE_EMPTY 0x0410 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_QUEUELIST_INFO_EMPTY 0x0410 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HIQ_INFO 0x0414 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_ACQ_STOP_V1 0x0414 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_QUEUELIST_ACQ_EN 0x0414 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCNQ_INFO 0x0418 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_BCNQ_BDNY_V2 0x0418 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TXPKT_EMPTY 0x041A + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_CPU_MGQ_INFO 0x041C +#define REG_FWHW_TXQ_CTRL 0x0420 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HWSEQ_CTRL 0x0423 + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_DATAFB_SEL 0x0423 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCNQ_BDNY 0x0424 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BCNQ_BDNY_V1 0x0424 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TXBDNY 0x0424 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MGQ_BDNY 0x0425 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_LIFETIME_EN 0x0426 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_FW_FREE_TAIL 0x0427 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_SPEC_SIFS 0x0428 +#define REG_RETRY_LIMIT 0x042A +#define REG_TXBF_CTRL 0x042C +#define REG_DARFRC 0x0430 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_DARFRCH 0x0434 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_RARFRC 0x0438 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RARFRCH 0x043C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_RRSR 0x0440 +#define REG_ARFR0 0x0444 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ARFRH0 0x0448 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ARFR1_V1 0x044C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_REG_ARFR_WT0 0x044C +#define REG_REG_ARFR_WT1 0x0450 + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ARFRH1_V1 0x0450 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_CCK_CHECK 0x0454 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_AMPDU_BURST_CTRL 0x0455 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_AMPDU_MAX_TIME_V1 0x0455 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_AMPDU_MAX_TIME 0x0456 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BCNQ1_BDNY_V1 0x0456 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TAB_SEL 0x0456 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCNQ1_BDNY 0x0457 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_BCN_INVALID_CTRL 0x0457 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_AMPDU_MAX_LENGTH 0x0458 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_AMPDU_MAX_LENGTH_HT 0x0458 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ACQ_STOP 0x045C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WMAC_LBK_BUF_HD 0x045D + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_NDPA_RATE 0x045D + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_TX_HANG_CTRL 0x045E +#define REG_NDPA_OPT_CTRL 0x045F + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_FAST_EDCA_CTRL 0x0460 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_AMPDU_MAX_LENGTH_VHT 0x0460 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_RD_RESP_PKT_TH 0x0463 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_CMDQ_INFO 0x0464 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_NEW_EDCA_CTRL_V1 0x0464 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_Q4_INFO 0x0468 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACQ_STOP_V2 0x0468 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_Q5_INFO 0x046C +#define REG_Q6_INFO 0x0470 +#define REG_Q7_INFO 0x0474 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_LBK_BUF_HD_V1 0x0478 +#define REG_MGQ_BDNY_V1 0x047A + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_TXRPT_CTRL 0x047C +#define REG_INIRTS_RATE_SEL 0x0480 +#define REG_BASIC_CFEND_RATE 0x0481 +#define REG_STBC_CFEND_RATE 0x0482 +#define REG_DATA_SC 0x0483 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MACID_SLEEP3 0x0484 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_MOREDATA_V1 0x0484 +#define REG_DATA_SC1 0x0487 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MACID_SLEEP1 0x0488 +#define REG_ARFR2_V1 0x048C + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ARFRH2_V1 0x0490 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ARFR3_V1 0x0494 + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ARFRH3_V1 0x0498 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ARFR4 0x049C + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ARFRH4 0x04A0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ARFR5 0x04A4 + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ARFRH5 0x04A8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_TXRPT_START_OFFSET 0x04AC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TRYING_CNT_TH 0x04B0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_POWER_STAGE1 0x04B4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_POWER_STAGE2 0x04B8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC +#define REG_PKT_LIFE_TIME 0x04C0 +#define REG_STBC_SETTING 0x04C4 +#define REG_STBC_SETTING2 0x04C5 +#define REG_QUEUE_CTRL 0x04C6 +#define REG_SINGLE_AMPDU_CTRL 0x04C7 +#define REG_PROT_MODE_CTRL 0x04C8 +#define REG_BAR_MODE_CTRL 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT 0x04CF + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MACID_SLEEP2 0x04D0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_MACID_SLEEP_CTRL 0x04D0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MACID_SLEEP 0x04D4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_MACID_SLEEP_INFO 0x04D4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HW_SEQ0 0x04D8 +#define REG_HW_SEQ1 0x04DA +#define REG_HW_SEQ2 0x04DC +#define REG_HW_SEQ3 0x04DE + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +#define REG_CSI_SEQ 0x04DE + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_NULL_PKT_STATUS 0x04E0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_NULL_PKT_STATUS_V1 0x04E0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PTCL_ERR_STATUS 0x04E2 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PTCL_ERR_STATUS_V1 0x04E2 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PTCL_PKT_NUM 0x04E3 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_NULL_PKT_STATUS_EXTEND 0x04E3 + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +#define REG_TRXRPT_MISS_CNT 0x04E3 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_NULL_PKT_STATUS_V2 0x04E4 + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define REG_HQMGQ_DROP 0x04E4 + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_PRECNT_CTRL 0x04E5 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_NULL_PKT_STATUS_EXTEND_V1 0x04E7 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_POLLUTE_PKT_CNT 0x04E8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_PTCL_DBG 0x04EC + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_DROP_NUM 0x04EC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PTCL_DBG_V1 0x04EC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PTCL_TX_RPT 0x04F0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_TXOP_EXTRA_CTRL 0x04F0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_BT_POLLUTE_PKTCNT 0x04F0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_CPUMGQ_TIMER_CTRL2 0x04F4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PTCL_DBG_OUT 0x04F8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_DUMMY_PAGE4 0x04FC + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_DUMMY_PAGE4_V1 0x04FC + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MOREDATA 0x04FE + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_DUMMY_PAGE4_1 0x04FE + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_EDCA_VO_PARAM 0x0500 +#define REG_EDCA_VI_PARAM 0x0504 +#define REG_EDCA_BE_PARAM 0x0508 +#define REG_EDCA_BK_PARAM 0x050C +#define REG_BCNTCFG 0x0510 +#define REG_PIFS 0x0512 +#define REG_RDG_PIFS 0x0513 +#define REG_SIFS 0x0514 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TSFTR_SYN_OFFSET 0x0518 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_FORCE_BCN_IFS_V1 0x0518 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_AGGR_BREAK_TIME 0x051A +#define REG_SLOT 0x051B + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_EDCA_CPUMGQ_PARAM 0x051C + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_NOA_ON_ERLY_TIME 0x051C +#define REG_NOA_OFF_ERLY_TIME 0x051D + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_CPUMGQ_PAUSE 0x051E + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_TX_PTCL_CTRL 0x0520 +#define REG_TXPAUSE 0x0522 +#define REG_DIS_TXREQ_CLR 0x0523 +#define REG_RD_CTRL 0x0524 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MBSSID_CTRL 0x0526 +#define REG_P2PPS_CTRL 0x0527 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_PKT_LIFETIME_CTRL 0x0528 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_P2PPS_SPEC_STATE 0x052B + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_P2PPS0_SPEC_STATE 0x052B + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_TXOP_LIMIT_CTRL 0x052C + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BAR_TX_CTRL 0x0530 +#define REG_P2PON_DIS_TXTIME 0x0531 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_CCA_TXEN_CNT 0x0534 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_QUEUE_INCOL_THR 0x0538 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MAX_INTER_COLLISION 0x0538 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_QUEUE_INCOL_EN 0x053C + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MAX_INTER_COLLISION_CNT 0x053C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TBTT_PROHIBIT 0x0540 +#define REG_P2PPS_STATE 0x0543 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_RD_NAV_NXT 0x0544 +#define REG_NAV_PROT_LEN 0x0546 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_FTM_CTRL 0x0548 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FTM_PTT 0x0548 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_FTM_TSF_CNT 0x054C + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FTM_TSF 0x054C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCN_CTRL 0x0550 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCN_CTRL1 0x0551 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BCN_CTRL_CLINT0 0x0551 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MBID_NUM 0x0552 +#define REG_DUAL_TSF_RST 0x0553 +#define REG_MBSSID_BCN_SPACE 0x0554 +#define REG_DRVERLYINT 0x0558 +#define REG_BCNDMATIM 0x0559 +#define REG_ATIMWND 0x055A +#define REG_USTIME_TSF 0x055C +#define REG_BCN_MAX_ERR 0x055D +#define REG_RXTSF_OFFSET_CCK 0x055E +#define REG_RXTSF_OFFSET_OFDM 0x055F +#define REG_TSFTR 0x0560 + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_TSFTR_1 0x0564 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TSFTR1 0x0568 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_FREERUN_CNT 0x0568 + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FREERUN_CNT_1 0x056C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND1 0x0570 + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ATIMWND1_V1 0x0570 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_TBTT_PROHIBIT_INFRA 0x0571 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_CTWND 0x0572 +#define REG_BCNIVLCUNT 0x0573 +#define REG_BCNDROPCTRL 0x0574 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_HGQ_TIMEOUT_PERIOD 0x0575 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_TXCMD_TIMEOUT_PERIOD 0x0576 +#define REG_MISC_CTRL 0x0577 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BCN_CTRL_CLINT1 0x0578 +#define REG_BCN_CTRL_CLINT2 0x0579 +#define REG_BCN_CTRL_CLINT3 0x057A + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_EXTEND_CTRL 0x057B + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_P2PPS1_SPEC_STATE 0x057C +#define REG_P2PPS1_STATE 0x057D +#define REG_P2PPS2_SPEC_STATE 0x057E +#define REG_P2PPS2_STATE 0x057F + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PS_TIMER 0x0580 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_PS_TIMER0 0x0580 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TIMER0 0x0584 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_PS_TIMER1 0x0584 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TIMER1 0x0588 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_PS_TIMER2 0x0588 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TBTT_CTN_AREA 0x058C +#define REG_FORCE_BCN_IFS 0x058E + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_TXOP_MIN 0x0590 +#define REG_PRE_BKF_TIME 0x0592 +#define REG_CROSS_TXOP_CTRL 0x0593 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_TBTT_INT_SHIFT_CLI0 0x0594 +#define REG_TBTT_INT_SHIFT_CLI1 0x0595 +#define REG_TBTT_INT_SHIFT_CLI2 0x0596 +#define REG_TBTT_INT_SHIFT_CLI3 0x0597 +#define REG_TBTT_INT_SHIFT_ENABLE 0x0598 + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define REG_RX_TBTT_SHIFT_V1 0x0598 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND2 0x05A0 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_ATIMWND_GROUP1 0x05A0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND3 0x05A1 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_ATIMWND_GROUP2 0x05A1 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND4 0x05A2 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_ATIMWND_GROUP3 0x05A2 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND5 0x05A3 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_ATIMWND_GROUP4 0x05A3 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND6 0x05A4 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_DTIM_COUNT_GROUP1 0x05A4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND7 0x05A5 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_DTIM_COUNT_GROUP2 0x05A5 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ATIMUGT 0x05A6 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_DTIM_COUNT_GROUP3 0x05A6 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HIQ_NO_LMT_EN 0x05A7 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_DTIM_COUNT_GROUP4 0x05A7 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_DTIM_COUNTER_ROOT 0x05A8 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_HIQ_NO_LMT_EN_V2 0x05A8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_DTIM_COUNTER_VAP1 0x05A9 +#define REG_DTIM_COUNTER_VAP2 0x05AA +#define REG_DTIM_COUNTER_VAP3 0x05AB +#define REG_DTIM_COUNTER_VAP4 0x05AC + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_MBID_BCNQ_EN 0x05AC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_DTIM_COUNTER_VAP5 0x05AD +#define REG_DTIM_COUNTER_VAP6 0x05AE +#define REG_DTIM_COUNTER_VAP7 0x05AF +#define REG_DIS_ATIM 0x05B0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_EARLY_128US 0x05B1 +#define REG_P2PPS1_CTRL 0x05B2 +#define REG_P2PPS2_CTRL 0x05B3 +#define REG_TIMER0_SRC_SEL 0x05B4 +#define REG_NOA_UNIT_SEL 0x05B5 +#define REG_P2POFF_DIS_TXTIME 0x05B7 +#define REG_MBSSID_BCN_SPACE2 0x05B8 +#define REG_MBSSID_BCN_SPACE3 0x05BC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ACMHWCTRL 0x05C0 +#define REG_ACMRSTCTRL 0x05C1 +#define REG_ACMAVG 0x05C2 +#define REG_VO_ADMTIME 0x05C4 +#define REG_VI_ADMTIME 0x05C6 +#define REG_BE_ADMTIME 0x05C8 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MAC_HEADER_NAV_OFFSET 0x05CA +#define REG_DIS_NDPA_NAV_CHECK 0x05CB + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_EDCA_RANDOM_GEN 0x05CC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TXCMD_NOA_SEL 0x05CF + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TXCMD_SEL 0x05CF + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define REG_32K_CLK_SEL 0x05D0 +#define REG_EARLYINT_ADJUST 0x05D4 +#define REG_BCNERR_CNT 0x05D8 +#define REG_BCNERR_CNT_2 0x05DC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_NOA_PARAM 0x05E0 + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_NOA_PARAM_1 0x05E4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_MU_DBG_INFO 0x05E8 + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_NOA_PARAM_2 0x05E8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_MU_DBG_INFO_1 0x05EC + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_NOA_PARAM_3 0x05EC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_NOA_SUBIE 0x05ED + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_P2P_RST 0x05F0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_SCH_DBG_SEL 0x05F0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SCHEDULER_RST 0x05F1 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_MU_DBG_ERR_FLAG 0x05F2 +#define REG_TX_ERR_RECOVERY_RST 0x05F3 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SCH_DBG_VALUE 0x05F4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_SCH_TXCMD 0x05F8 +#define REG_PAGE5_DUMMY 0x05FC +#define REG_WMAC_CR 0x0600 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_FWPKT_CR 0x0601 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FW_STS_FILTER 0x0602 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_BWOPMODE 0x0603 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_TCR 0x0604 +#define REG_RCR 0x0608 +#define REG_RX_PKT_LIMIT 0x060C +#define REG_RX_DLK_TIME 0x060D +#define REG_RX_DRVINFO_SZ 0x060F +#define REG_MACID 0x0610 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MACID_H 0x0614 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_BSSID 0x0618 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BSSID_H 0x061C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_MAR 0x0620 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MAR_H 0x0624 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MBIDCAMCFG_1 0x0628 +#define REG_MBIDCAMCFG_2 0x062C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_WMAC_DEBUG_SEL 0x062C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MCU_TEST_1 0x0630 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_TCR_TSFT_OFS 0x0630 +#define REG_UDF_THSD 0x0632 +#define REG_ZLD_NUM 0x0633 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MCU_TEST_2 0x0634 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_STMP_THSD 0x0634 +#define REG_WMAC_TXTIMEOUT 0x0635 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) + +#define REG_MCU_TEST_2_V1 0x0636 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_USTIME_EDCA 0x0638 + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_ACKTO_CCK 0x0639 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_MAC_SPEC_SIFS 0x063A +#define REG_RESP_SIFS_CCK 0x063C +#define REG_RESP_SIFS_OFDM 0x063E +#define REG_ACKTO 0x0640 +#define REG_CTS2TO 0x0641 +#define REG_EIFS 0x0642 + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RPFM_MAP0 0x0644 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_RPFM_MAP1 0x0646 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RPFM_MAP1_V1 0x0646 + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RPFM_CAM_CMD 0x0648 +#define REG_RPFM_CAM_RWD 0x064C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_NAV_CTRL 0x0650 +#define REG_BACAMCMD 0x0654 +#define REG_BACAMCONTENT 0x0658 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BACAMCONTENT_H 0x065C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_LBDLY 0x0660 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_BACAM_RPMEN 0x0661 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_TX_RX 0x0662 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_BITMAP_CTL 0x0663 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_RXERR_RPT 0x0664 +#define REG_WMAC_TRXPTCL_CTL 0x0668 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_TRXPTCL_CTL_H 0x066C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_CAMCMD 0x0670 +#define REG_CAMWRITE 0x0674 +#define REG_CAMREAD 0x0678 +#define REG_CAMDBG 0x067C +#define REG_SECCFG 0x0680 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RXFILTER_CATEGORY_1 0x0682 +#define REG_RXFILTER_ACTION_1 0x0683 +#define REG_RXFILTER_CATEGORY_2 0x0684 +#define REG_RXFILTER_ACTION_2 0x0685 +#define REG_RXFILTER_CATEGORY_3 0x0686 +#define REG_RXFILTER_ACTION_3 0x0687 +#define REG_RXFLTMAP3 0x0688 +#define REG_RXFLTMAP4 0x068A +#define REG_RXFLTMAP5 0x068C +#define REG_RXFLTMAP6 0x068E + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_WOW_CTRL 0x0690 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_NAN_RX_TSF_FILTER 0x0691 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_PS_RX_INFO 0x0692 +#define REG_WMMPS_UAPSD_TID 0x0693 +#define REG_LPNAV_CTRL 0x0694 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WKFMCAM_NUM 0x0698 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WKFMCAM_CMD 0x0698 +#define REG_WKFMCAM_RWD 0x069C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_RXFLTMAP0 0x06A0 +#define REG_RXFLTMAP1 0x06A2 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RXFLTMAP 0x06A4 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RXFLTMAP2 0x06A4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_BCN_PSR_RPT 0x06A8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_FLC_RPC 0x06AC +#define REG_FLC_RPCT 0x06AD +#define REG_FLC_PTS 0x06AE +#define REG_FLC_TRPC 0x06AF + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RXPKTMON_CTRL 0x06B0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_STATE_MON 0x06B4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ERROR_MON 0x06B8 +#define REG_SEARCH_MACID 0x06BC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_BT_COEX_TABLE 0x06C0 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_COEX_TABLE2 0x06C4 +#define REG_BT_COEX_BREAK_TABLE 0x06C8 +#define REG_BT_COEX_TABLE_H 0x06CC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RXCMD_0 0x06D0 +#define REG_RXCMD_1 0x06D4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_WMAC_RESP_TXINFO 0x06D8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BBPSF_CTRL 0x06DC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_P2P_RX_BCN_NOA 0x06E0 +#define REG_ASSOCIATED_BFMER0_INFO 0x06E4 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ASSOCIATED_BFMER0_INFO_H 0x06E8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ASSOCIATED_BFMER1_INFO 0x06EC + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ASSOCIATED_BFMER1_INFO_H 0x06F0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4 +#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_CSI_RRSR_V1 0x06FC + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define REG_CSI_PTR 0x06FC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_MACID1 0x0700 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MACID1_1 0x0704 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BSSID1 0x0708 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_CFG_FORCE_LINK_L 0x0709 +#define REG_PCIE_CFG_FORCE_LINK_H 0x070A + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BSSID1_1 0x070C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0x070C +#define REG_PCIE_CFG_CX_NFTS 0x070D +#define REG_PCIE_CFG_DEFAULT_ENTR_LATENCY 0x070F + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_BCN_PSR_RPT1 0x0710 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_CFG_L1_MISC_SEL 0x0711 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ASSOCIATED_BFMEE_SEL 0x0714 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_ASSOCIATED_BFMEE_SEL_1 0x0714 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_SND_PTCL_CTRL 0x0718 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x0718 +#define REG_PCIE_CFG_FORCE_CLKREQ_N_PAD 0x0719 +#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY 0x071A +#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG 0x071B + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_RX_CSI_RPT_INFO 0x071C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_L 0x071C +#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_H 0x071D + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_NS_ARP_CTRL 0x0720 +#define REG_NS_ARP_INFO 0x0724 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_CFG_L1_UNIT_SEL 0x0724 +#define REG_PCIE_CFG_MIN_CLKREQ_SEL 0x0725 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_NS_ARP_IPADDR 0x0728 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BEAMFORMING_INFO_NSARP_V1 0x0728 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WRITE_RX_CSI_RPT_INFO 0x072C + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BEAMFORMING_INFO_NSARP 0x072C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_NS_ARP_IPV6_MYADDR 0x0730 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_IPV6 0x0730 +#define REG_IPV6_1 0x0734 +#define REG_IPV6_2 0x0738 +#define REG_IPV6_3 0x073C + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750 + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define REG_WMAC_SWAES_DIO_B63_B32 0x0754 +#define REG_WMAC_SWAES_DIO_B95_B64 0x0758 +#define REG_WMAC_SWAES_DIO_B127_B96 0x075C + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_SWAES_CFG 0x0760 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_COEX_V2 0x0762 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_BT_COEX 0x0764 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WLAN_ACT_MSK_CTRL 0x0768 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WLAN_ACT_MASK_CTRL 0x0768 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WLAN_ACT_MASK_CTRL_1 0x076C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_STATISTICS_CTRL 0x076E +#define REG_BT_COEX_ENH_INTF_CTRL 0x076E + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_BT_ACT_STATISTICS 0x0770 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_ACT_STATISTICS_1 0x0774 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_STATISTICS_OTH_CTRL 0x0778 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_CMD_ID 0x077C + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_STATUS_REPORT_REGISTER 0x077C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT__STATUS_RPT 0x077D +#define REG_BT_DATA 0x0780 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WLAN_RPT_ 0x0781 +#define REG_BT_ISR_CTRL 0x0783 +#define REG_WLAN_RPT_TO_CTR 0x0784 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_ISOLATION_TABLE 0x0785 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 0x0788 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 0x078C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_ISR_STA 0x078F + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TDMA_TIME_AND_RPT_SAM_SET 0x0790 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_TDMA_TIME_REGISTER 0x0790 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_CH_INFO 0x0794 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_ACT_REGISTER 0x0794 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_STATIC_INFO_EXT 0x0795 +#define REG_LTR_IDLE_LATENCY 0x0798 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_OBFF_CTRL_BASIC 0x0798 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_LTR_ACTIVE_LATENCY 0x079C + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_OBFF_CTRL2_TIMER 0x079C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_OBFF_CTRL 0x07A0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_LTR_CTRL_BASIC 0x07A0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_LTR_CTRL 0x07A4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_LTR_CTRL2 0x07A8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_LTR_IDLE_LATENCY_V1 0x07A8 +#define REG_LTR_ACTIVE_LATENCY_V1 0x07AC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ANTTRN_CTRL 0x07B0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_SMART_ANT_CONDITION 0x07B0 +#define REG_SMART_ANT_CTRL 0x07B4 + +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 0x07B4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WMAC_PKTCNT_RWD 0x07B8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_CONTROL_FRAME_REPORT 0x07B8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WMAC_PKTCNT_CTRL 0x07BC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_CONTROL_FRAME_CNT_CTRL 0x07BC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_IQ_DUMP 0x07C0 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_IQ_DUMP_1 0x07C4 +#define REG_IQ_DUMP_2 0x07C8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_FTM_CTL 0x07CC #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define REG_WMAC_IQ_MDPK_FUNC 0x07CE -#define REG_TX_HANG_CTRL 0x045E -#define REG_NDPA_OPT_CTRL 0x045F +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_IQ_DUMP_EXT 0x07CF #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#define REG_OFDM_CCK_LEN_MASK 0x07D0 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_WMAC_OPTION_FUNCTION 0x07D0 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_OPTION_FUNCTION_1 0x07D4 +#define REG_WMAC_OPTION_FUNCTION_2 0x07D8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RX_FILTER_FUNCTION 0x07DA + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_NDP_SIG 0x07E0 +#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4 + +#endif + +#if (HALMAC_8814AMP_SUPPORT) + +#define REG_SEC_OPT 0x07E8 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_TXCMD_INFO_FOR_RSP_PKT_1 0x07E8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_SEC_OPT_V2 0x07EC + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WSEC_OPTION 0x07EC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RTS_ADDRESS_0 0x07F0 + +#endif + +#if (HALMAC_8814AMP_SUPPORT) + +#define REG_RTS_ADDR0 0x07F0 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RTS_ADDRESS_0_1 0x07F4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RTS_ADDRESS_1 0x07F8 + +#endif + +#if (HALMAC_8814AMP_SUPPORT) + +#define REG_RTS_ADDR1 0x07F8 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RTS_ADDRESS_1_1 0x07FC + +#endif + +#if (HALMAC_8822B_SUPPORT) + +#define REG__RPFM_MAP1 0x07FE + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_SYS_CFG3 0x1000 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ANAPARSW_MAC_0 0x1010 +#define REG_ANAPARSW_MAC_1 0x1014 +#define REG_ANAPAR_MAC_0 0x1018 +#define REG_ANAPAR_MAC_1 0x101C +#define REG_ANAPAR_MAC_2 0x1020 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ANAPAR_MAC_3 0x1024 +#define REG_ANAPAR_MAC_4 0x1028 +#define REG_ANAPAR_MAC_5 0x102C +#define REG_ANAPAR_MAC_6 0x1030 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_SYS_CFG4 0x1034 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ANAPAR_MAC_7 0x1034 +#define REG_ANAPAR_MAC_8 0x1038 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ANAPAR_XTAL_0 0x1040 +#define REG_ANAPAR_XTAL_1 0x1044 +#define REG_ANAPAR_XTAL_2 0x1048 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ANAPAR_XTAL_AAC 0x104C + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define REG_ANAPAR_XTAL_3 0x104C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ANAPAR_XTAL_R_ONLY 0x1050 +#define REG_CPHY_LDO 0x1054 + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define REG_ANAPAR_XTAL_AACK_0 0x1054 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_CPHY_BG 0x1058 + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define REG_ANAPAR_XTAL_AACK_1 0x1058 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_HIMR_4 0x1060 +#define REG_HISR_4 0x1064 + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define REG_ANAPAR_XTAL_MODE_DECODER 0x1064 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_HIMR_5 0x1068 +#define REG_HISR_5 0x106C -#define REG_FAST_EDCA_CTRL 0x0460 +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_SYS_CFG5 0x1070 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_HIMR_6 0x1078 +#define REG_HISR_6 0x107C + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_CPU_DMEM_CON 0x1080 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BOOT_REASON 0x1088 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_HIMR4 0x1090 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_DATA_CPU_CTL0 0x1090 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_HISR4 0x1094 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_DATA_CPU_CTL1 0x1094 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_HIMR5 0x1098 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TXDMA_STOP_HIMR 0x1098 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_HISR5 0x109C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TXDMA_STOP_HISR 0x109C +#define REG_TXDMA_START_HIMR 0x10A0 +#define REG_TXDMA_START_HISR 0x10A4 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_NFCPAD_CTRL 0x10A8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_HIMR2 0x10B0 +#define REG_HISR2 0x10B4 +#define REG_HIMR3 0x10B8 +#define REG_HISR3 0x10BC +#define REG_SW_MDIO 0x10C0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_SW_FLUSH 0x10C4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_DBG_GPIO_BMUX 0x10C8 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define REG_HIMR_7 0x10C8 -#define REG_RD_RESP_PKT_TH 0x0463 -#define REG_CMDQ_INFO 0x0464 -#define REG_Q4_INFO 0x0468 -#define REG_Q5_INFO 0x046C -#define REG_Q6_INFO 0x0470 -#define REG_Q7_INFO 0x0474 +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_FPGA_TAG 0x10CC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_HISR_7 0x10CC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_WL_DSS_CTRL0 0x10D0 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_H2C_PKT_READADDR 0x10D0 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_WL_DSS_STATUS0 0x10D4 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_H2C_PKT_WRITEADDR 0x10D4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_WL_DSS_CTRL1 0x10D8 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_MEM_PWR_CRTL 0x10D8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_WL_DSS_STATUS1 0x10DC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_FW_DRV_HANDSHAKE 0x10DC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_FW_DBG0 0x10E0 +#define REG_FW_DBG1 0x10E4 +#define REG_FW_DBG2 0x10E8 +#define REG_FW_DBG3 0x10EC +#define REG_FW_DBG4 0x10F0 +#define REG_FW_DBG5 0x10F4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FW_DBG6 0x10F8 +#define REG_FW_DBG7 0x10FC +#define REG_CR_EXT 0x1100 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TC9_CTRL 0x1104 +#define REG_TC10_CTRL 0x1108 +#define REG_TC11_CTRL 0x110C +#define REG_TC12_CTRL 0x1110 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FWFF 0x1114 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RXFF_PTR_V1 0x1118 +#define REG_RXFF_WTR_V1 0x111C -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define REG_WMAC_LBK_BUF_HD_V1 0x0478 -#define REG_MGQ_BDNY_V1 0x047A +#define REG_FE2IMR 0x1120 +#define REG_FE2ISR 0x1124 +#define REG_FE3IMR 0x1128 +#define REG_FE3ISR 0x112C +#define REG_FE4IMR 0x1130 +#define REG_FE4ISR 0x1134 +#define REG_FT1IMR 0x1138 +#define REG_FT1ISR 0x113C +#define REG_SPWR0 0x1140 +#define REG_SPWR1 0x1144 +#define REG_SPWR2 0x1148 +#define REG_SPWR3 0x114C +#define REG_POWSEQ 0x1150 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_TC7_CTRL_V1 0x1158 +#define REG_TC8_CTRL_V1 0x115C + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define REG_TXRPT_CTRL 0x047C -#define REG_INIRTS_RATE_SEL 0x0480 -#define REG_BASIC_CFEND_RATE 0x0481 -#define REG_STBC_CFEND_RATE 0x0482 -#define REG_DATA_SC 0x0483 -#define REG_MACID_SLEEP3 0x0484 -#define REG_MACID_SLEEP1 0x0488 -#define REG_ARFR2_V1 0x048C -#define REG_ARFR3_V1 0x0494 -#define REG_ARFR4 0x049C -#define REG_ARFR5 0x04A4 -#define REG_TXRPT_START_OFFSET 0x04AC +#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3 0x1160 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RX_BCN_TBTT_ITVL0 0x1160 + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define REG_TRYING_CNT_TH 0x04B0 +#define REG_RXBCN_TBTT_INTERVAL_PORT4 0x1164 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_POWER_STAGE1 0x04B4 +#define REG_RX_BCN_TBTT_ITVL1 0x1164 #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_POWER_STAGE2 0x04B8 +#define REG_FWIMR1 0x1168 +#define REG_FWISR1 0x116C +#define REG_FWIMR2 0x1170 #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC -#define REG_PKT_LIFE_TIME 0x04C0 -#define REG_STBC_SETTING 0x04C4 -#define REG_STBC_SETTING2 0x04C5 -#define REG_QUEUE_CTRL 0x04C6 -#define REG_SINGLE_AMPDU_CTRL 0x04C7 -#define REG_PROT_MODE_CTRL 0x04C8 -#define REG_BAR_MODE_CTRL 0x04CC -#define REG_RA_TRY_RATE_AGG_LMT 0x04CF -#define REG_MACID_SLEEP2 0x04D0 -#define REG_MACID_SLEEP 0x04D4 +#define REG_IO_WRAP_ERR_FLAG 0x1170 #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_HW_SEQ0 0x04D8 -#define REG_HW_SEQ1 0x04DA -#define REG_HW_SEQ2 0x04DC -#define REG_HW_SEQ3 0x04DE +#define REG_FWISR2 0x1174 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_CSI_SEQ 0x04DE +#define REG_FWIMR3 0x1178 +#define REG_FWISR3 0x117C #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_NULL_PKT_STATUS 0x04E0 +#define REG_SPEED_SENSOR 0x1180 +#define REG_SPEED_SENSOR1 0x1184 +#define REG_SPEED_SENSOR2 0x1188 +#define REG_SPEED_SENSOR3 0x118C +#define REG_SPEED_SENSOR4 0x1190 +#define REG_SPEED_SENSOR5 0x1194 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_NULL_PKT_STATUS_V1 0x04E0 +#define REG_RXPKTBUF_1_MAX_ADDR 0x1198 +#define REG_RXFWBUF_1_MAX_ADDR 0x119C +#define REG_IO_WRAP_ERR_FLAG_V1 0x11A0 +#define REG_RXPKTBUF_1_READ 0x11A4 +#define REG_RXPKTBUF_1_WRITE 0x11A8 +#define REG_BUFF_DBGUG 0x11AC +#define REG_RFE_CTRL_PAD_E2 0x11B0 +#define REG_RFE_CTRL_PAD_SR 0x11B4 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PTCL_ERR_STATUS 0x04E2 +#define REG_EXT_QUEUE_REG 0x11C0 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PTCL_PKT_NUM 0x04E3 +#define REG_H2C_PRIORITY_SEL 0x11C0 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_NULL_PKT_STATUS_EXTEND 0x04E3 +#define REG_COUNTER_CONTROL 0x11C4 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_TRXRPT_MISS_CNT 0x04E3 +#define REG_COUNTER_CTRL 0x11C4 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4 +#define REG_COUNTER_TH 0x11C8 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_POLLUTE_PKT_CNT 0x04E8 -#define REG_PTCL_DBG 0x04EC +#define REG_COUNTER_THRESHOLD 0x11C8 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PTCL_TX_RPT 0x04F0 +#define REG_COUNTER_SET 0x11CC +#define REG_COUNTER_OVERFLOW 0x11D0 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_TXOP_EXTRA_CTRL 0x04F0 +#define REG_TDE_LEN_TH 0x11D4 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_CPUMGQ_TIMER_CTRL2 0x04F4 +#define REG_TXDMA_LEN_THRESHOLD 0x11D4 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_DUMMY_PAGE4 0x04FC +#define REG_RDE_LEN_TH 0x11D8 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DUMMY_PAGE4_V1 0x04FC -#define REG_MOREDATA 0x04FE +#define REG_RXDMA_LEN_THRESHOLD 0x11D8 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_EDCA_VO_PARAM 0x0500 -#define REG_EDCA_VI_PARAM 0x0504 -#define REG_EDCA_BE_PARAM 0x0508 -#define REG_EDCA_BK_PARAM 0x050C -#define REG_BCNTCFG 0x0510 -#define REG_PIFS 0x0512 -#define REG_RDG_PIFS 0x0513 -#define REG_SIFS 0x0514 -#define REG_TSFTR_SYN_OFFSET 0x0518 -#define REG_AGGR_BREAK_TIME 0x051A -#define REG_SLOT 0x051B -#define REG_TX_PTCL_CTRL 0x0520 -#define REG_TXPAUSE 0x0522 -#define REG_DIS_TXREQ_CLR 0x0523 -#define REG_RD_CTRL 0x0524 -#define REG_MBSSID_CTRL 0x0526 -#define REG_P2PPS_CTRL 0x0527 -#define REG_PKT_LIFETIME_CTRL 0x0528 -#define REG_P2PPS_SPEC_STATE 0x052B +#define REG_PCIE_EXEC_TIME 0x11DC #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BAR_TX_CTRL 0x0530 +#define REG_PCIE_EXEC_TIME_THRESHOLD 0x11DC #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_QUEUE_INCOL_THR 0x0538 -#define REG_QUEUE_INCOL_EN 0x053C +#define REG_FT2IMR 0x11E0 +#define REG_FT2ISR 0x11E4 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TBTT_PROHIBIT 0x0540 -#define REG_P2PPS_STATE 0x0543 -#define REG_RD_NAV_NXT 0x0544 -#define REG_NAV_PROT_LEN 0x0546 +#define REG_MSG2 0x11F0 +#define REG_MSG3 0x11F4 +#define REG_MSG4 0x11F8 +#define REG_MSG5 0x11FC +#define REG_DDMA_CH0SA 0x1200 +#define REG_DDMA_CH0DA 0x1204 +#define REG_DDMA_CH0CTRL 0x1208 +#define REG_DDMA_CH1SA 0x1210 +#define REG_DDMA_CH1DA 0x1214 +#define REG_DDMA_CH1CTRL 0x1218 +#define REG_DDMA_CH2SA 0x1220 +#define REG_DDMA_CH2DA 0x1224 +#define REG_DDMA_CH2CTRL 0x1228 +#define REG_DDMA_CH3SA 0x1230 +#define REG_DDMA_CH3DA 0x1234 +#define REG_DDMA_CH3CTRL 0x1238 +#define REG_DDMA_CH4SA 0x1240 +#define REG_DDMA_CH4DA 0x1244 +#define REG_DDMA_CH4CTRL 0x1248 +#define REG_DDMA_CH5SA 0x1250 +#define REG_DDMA_CH5DA 0x1254 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_FTM_CTRL 0x0548 -#define REG_FTM_TSF_CNT 0x054C +#define REG_REG_DDMA_CH5CTRL 0x1258 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BCN_CTRL 0x0550 +#define REG_DDMA_CH5CTRL 0x1258 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BCN_CTRL1 0x0551 +#define REG_DDMA_INT_MSK 0x12E0 +#define REG_DDMA_CHSTATUS 0x12E8 +#define REG_DDMA_CHKSUM 0x12F0 +#define REG_DDMA_MONITOR 0x12FC #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BCN_CTRL_CLINT0 0x0551 +#define REG_STC_INT_CS 0x1300 +#define REG_ST_INT_CFG 0x1304 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MBID_NUM 0x0552 -#define REG_DUAL_TSF_RST 0x0553 -#define REG_MBSSID_BCN_SPACE 0x0554 -#define REG_DRVERLYINT 0x0558 -#define REG_BCNDMATIM 0x0559 -#define REG_ATIMWND 0x055A -#define REG_USTIME_TSF 0x055C -#define REG_BCN_MAX_ERR 0x055D -#define REG_RXTSF_OFFSET_CCK 0x055E -#define REG_RXTSF_OFFSET_OFDM 0x055F -#define REG_TSFTR 0x0560 +#define REG_ACH4_ACH5_TXBD_NUM 0x130C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_TSFTR_1 0x0564 +#define REG_CMU_DLY_CTRL 0x1310 +#define REG_CMU_DLY_CFG 0x1314 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TSFTR1 0x0568 +#define REG_FWCMDQ_TXBD_IDX 0x1318 +#define REG_P0HI8Q_TXBD_IDX 0x131C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FREERUN_CNT 0x0568 +#define REG_H2CQ_TXBD_DESA 0x1320 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_FREERUN_CNT_1 0x056C +#define REG_H2CQ_TXBD_DESA_L 0x1320 +#define REG_H2CQ_TXBD_DESA_H 0x1324 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_ATIMWND1 0x0570 +#define REG_H2CQ_TXBD_NUM 0x1328 +#define REG_H2CQ_TXBD_IDX 0x132C +#define REG_H2CQ_CSR 0x1330 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_ATIMWND1_V1 0x0570 +#define REG_P0HI9Q_TXBD_IDX 0x1334 +#define REG_P0HI10Q_TXBD_IDX 0x1338 +#define REG_P0HI11Q_TXBD_IDX 0x133C +#define REG_P0HI12Q_TXBD_IDX 0x1340 +#define REG_P0HI13Q_TXBD_IDX 0x1344 +#define REG_P0HI14Q_TXBD_IDX 0x1348 +#define REG_P0HI15Q_TXBD_IDX 0x134C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TBTT_PROHIBIT_INFRA 0x0571 +#define REG_AXI_EXCEPT_CS 0x1350 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_CTWND 0x0572 -#define REG_BCNIVLCUNT 0x0573 -#define REG_BCNDROPCTRL 0x0574 -#define REG_HGQ_TIMEOUT_PERIOD 0x0575 +#define REG_CHANGE_PCIE_SPEED 0x1350 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TXCMD_TIMEOUT_PERIOD 0x0576 -#define REG_MISC_CTRL 0x0577 -#define REG_BCN_CTRL_CLINT1 0x0578 -#define REG_BCN_CTRL_CLINT2 0x0579 -#define REG_BCN_CTRL_CLINT3 0x057A +#define REG_AXI_EXCEPT_TIME 0x1354 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_EXTEND_CTRL 0x057B +#define REG_DEBUG_STATE1 0x1354 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_P2PPS1_SPEC_STATE 0x057C -#define REG_P2PPS1_STATE 0x057D -#define REG_P2PPS2_SPEC_STATE 0x057E -#define REG_P2PPS2_STATE 0x057F +#define REG_HI8Q_TXBD_IDX 0x1358 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PS_TIMER 0x0580 +#define REG_DEBUG_STATE2 0x1358 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_PS_TIMER0 0x0580 +#define REG_HI9Q_TXBD_IDX 0x135C #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TIMER0 0x0584 +#define REG_DEBUG_STATE3 0x135C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_PS_TIMER1 0x0584 +#define REG_HI10Q_TXBD_IDX 0x1360 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TIMER1 0x0588 +#define REG_ACH5_TXBD_DESA_L 0x1360 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_PS_TIMER2 0x0588 +#define REG_HI11Q_TXBD_IDX 0x1364 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TBTT_CTN_AREA 0x058C -#define REG_FORCE_BCN_IFS 0x058E -#define REG_TXOP_MIN 0x0590 -#define REG_PRE_BKF_TIME 0x0592 -#define REG_CROSS_TXOP_CTRL 0x0593 +#define REG_ACH5_TXBD_DESA_H 0x1364 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_TBTT_INT_SHIFT_CLI0 0x0594 -#define REG_TBTT_INT_SHIFT_CLI1 0x0595 -#define REG_TBTT_INT_SHIFT_CLI2 0x0596 -#define REG_TBTT_INT_SHIFT_CLI3 0x0597 -#define REG_TBTT_INT_SHIFT_ENABLE 0x0598 +#define REG_HI12Q_TXBD_IDX 0x1368 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_ATIMWND2 0x05A0 -#define REG_ATIMWND3 0x05A1 -#define REG_ATIMWND4 0x05A2 -#define REG_ATIMWND5 0x05A3 -#define REG_ATIMWND6 0x05A4 -#define REG_ATIMWND7 0x05A5 -#define REG_ATIMUGT 0x05A6 -#define REG_HIQ_NO_LMT_EN 0x05A7 -#define REG_DTIM_COUNTER_ROOT 0x05A8 -#define REG_DTIM_COUNTER_VAP1 0x05A9 -#define REG_DTIM_COUNTER_VAP2 0x05AA -#define REG_DTIM_COUNTER_VAP3 0x05AB -#define REG_DTIM_COUNTER_VAP4 0x05AC -#define REG_DTIM_COUNTER_VAP5 0x05AD -#define REG_DTIM_COUNTER_VAP6 0x05AE -#define REG_DTIM_COUNTER_VAP7 0x05AF -#define REG_DIS_ATIM 0x05B0 +#define REG_ACH6_TXBD_DESA_L 0x1368 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_EARLY_128US 0x05B1 -#define REG_P2PPS1_CTRL 0x05B2 -#define REG_P2PPS2_CTRL 0x05B3 -#define REG_TIMER0_SRC_SEL 0x05B4 -#define REG_NOA_UNIT_SEL 0x05B5 -#define REG_P2POFF_DIS_TXTIME 0x05B7 -#define REG_MBSSID_BCN_SPACE2 0x05B8 -#define REG_MBSSID_BCN_SPACE3 0x05BC +#define REG_HI13Q_TXBD_IDX 0x136C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_ACMHWCTRL 0x05C0 -#define REG_ACMRSTCTRL 0x05C1 -#define REG_ACMAVG 0x05C2 -#define REG_VO_ADMTIME 0x05C4 -#define REG_VI_ADMTIME 0x05C6 -#define REG_BE_ADMTIME 0x05C8 -#define REG_EDCA_RANDOM_GEN 0x05CC -#define REG_TXCMD_NOA_SEL 0x05CF -#define REG_NOA_PARAM 0x05E0 +#define REG_ACH6_TXBD_DESA_H 0x136C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_NOA_PARAM_1 0x05E4 -#define REG_NOA_PARAM_2 0x05E8 -#define REG_NOA_PARAM_3 0x05EC +#define REG_HI14Q_TXBD_IDX 0x1370 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_NOA_SUBIE 0x05ED +#define REG_ACH7_TXBD_DESA_L 0x1370 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_P2P_RST 0x05F0 -#define REG_SCHEDULER_RST 0x05F1 +#define REG_HI15Q_TXBD_IDX 0x1374 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SCH_TXCMD 0x05F8 -#define REG_PAGE5_DUMMY 0x05FC -#define REG_WMAC_CR 0x0600 +#define REG_ACH7_TXBD_DESA_H 0x1374 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_FWPKT_CR 0x0601 +#define REG_HI8Q_TXBD_DESA 0x1378 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_FW_STS_FILTER 0x0602 +#define REG_ACH8_TXBD_DESA_L 0x1378 +#define REG_ACH8_TXBD_DESA_H 0x137C #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BWOPMODE 0x0603 +#define REG_CHNL_DMA_CFG_V1 0x137C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TCR 0x0604 -#define REG_RCR 0x0608 -#define REG_RX_PKT_LIMIT 0x060C -#define REG_RX_DLK_TIME 0x060D -#define REG_RX_DRVINFO_SZ 0x060F -#define REG_MACID 0x0610 -#define REG_BSSID 0x0618 -#define REG_MAR 0x0620 -#define REG_MBIDCAMCFG_1 0x0628 -#define REG_MBIDCAMCFG_2 0x062C +#define REG_HI9Q_TXBD_DESA 0x1380 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MCU_TEST_1 0x0630 +#define REG_ACH9_TXBD_DESA_L 0x1380 +#define REG_ACH9_TXBD_DESA_H 0x1384 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_TCR_TSFT_OFS 0x0630 -#define REG_UDF_THSD 0x0632 -#define REG_ZLD_NUM 0x0633 +#define REG_HI10Q_TXBD_DESA 0x1388 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MCU_TEST_2 0x0634 +#define REG_ACH10_TXBD_DESA_L 0x1388 +#define REG_ACH10_TXBD_DESA_H 0x138C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_STMP_THSD 0x0634 -#define REG_WMAC_TXTIMEOUT 0x0635 -#define REG_MCU_TEST_2_V1 0x0636 +#define REG_HI11Q_TXBD_DESA 0x1390 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_USTIME_EDCA 0x0638 +#define REG_ACH11_TXBD_DESA_L 0x1390 +#define REG_ACH11_TXBD_DESA_H 0x1394 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_ACKTO_CCK 0x0639 +#define REG_HI12Q_TXBD_DESA 0x1398 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MAC_SPEC_SIFS 0x063A -#define REG_RESP_SIFS_CCK 0x063C -#define REG_RESP_SIFS_OFDM 0x063E -#define REG_ACKTO 0x0640 -#define REG_CTS2TO 0x0641 -#define REG_EIFS 0x0642 +#define REG_ACH12_TXBD_DESA_L 0x1398 +#define REG_ACH12_TXBD_DESA_H 0x139C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_RPFM_MAP0 0x0644 -#define REG_RPFM_MAP1 0x0646 -#define REG_RPFM_CAM_CMD 0x0648 -#define REG_RPFM_CAM_RWD 0x064C +#define REG_HI13Q_TXBD_DESA 0x13A0 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_NAV_CTRL 0x0650 -#define REG_BACAMCMD 0x0654 -#define REG_BACAMCONTENT 0x0658 -#define REG_LBDLY 0x0660 +#define REG_ACH13_TXBD_DESA_L 0x13A0 +#define REG_ACH13_TXBD_DESA_H 0x13A4 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_BACAM_RPMEN 0x0661 +#define REG_HI14Q_TXBD_DESA 0x13A8 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TX_RX 0x0662 +#define REG_HI0Q_TXBD_DESA_L 0x13A8 +#define REG_HI0Q_TXBD_DESA_H 0x13AC #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_BITMAP_CTL 0x0663 +#define REG_HI15Q_TXBD_DESA 0x13B0 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RXERR_RPT 0x0664 -#define REG_WMAC_TRXPTCL_CTL 0x0668 -#define REG_CAMCMD 0x0670 -#define REG_CAMWRITE 0x0674 -#define REG_CAMREAD 0x0678 -#define REG_CAMDBG 0x067C -#define REG_SECCFG 0x0680 +#define REG_HI1Q_TXBD_DESA_L 0x13B0 +#define REG_HI1Q_TXBD_DESA_H 0x13B4 #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RXFILTER_CATEGORY_1 0x0682 -#define REG_RXFILTER_ACTION_1 0x0683 -#define REG_RXFILTER_CATEGORY_2 0x0684 -#define REG_RXFILTER_ACTION_2 0x0685 -#define REG_RXFILTER_CATEGORY_3 0x0686 -#define REG_RXFILTER_ACTION_3 0x0687 -#define REG_RXFLTMAP3 0x0688 -#define REG_RXFLTMAP4 0x068A -#define REG_RXFLTMAP5 0x068C -#define REG_RXFLTMAP6 0x068E +#define REG_PCIE_HISR0_V1 0x13B4 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WOW_CTRL 0x0690 +#define REG_HI8Q_TXBD_NUM 0x13B8 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_NAN_RX_TSF_FILTER 0x0691 +#define REG_HI2Q_TXBD_DESA_L 0x13B8 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PS_RX_INFO 0x0692 -#define REG_WMMPS_UAPSD_TID 0x0693 -#define REG_LPNAV_CTRL 0x0694 +#define REG_HI9Q_TXBD_NUM 0x13BA +#define REG_HI10Q_TXBD_NUM 0x13BC #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WKFMCAM_NUM 0x0698 +#define REG_HI2Q_TXBD_DESA_H 0x13BC #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WKFMCAM_CMD 0x0698 -#define REG_WKFMCAM_RWD 0x069C +#define REG_PCIE_HISR1_V1 0x13BC #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RXFLTMAP0 0x06A0 -#define REG_RXFLTMAP1 0x06A2 -#define REG_RXFLTMAP 0x06A4 -#define REG_BCN_PSR_RPT 0x06A8 +#define REG_HI11Q_TXBD_NUM 0x13BE +#define REG_HI12Q_TXBD_NUM 0x13C0 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_FLC_RPC 0x06AC -#define REG_FLC_RPCT 0x06AD -#define REG_FLC_PTS 0x06AE -#define REG_FLC_TRPC 0x06AF +#define REG_HI3Q_TXBD_DESA_L 0x13C0 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RXPKTMON_CTRL 0x06B0 +#define REG_HI13Q_TXBD_NUM 0x13C2 +#define REG_HI14Q_TXBD_NUM 0x13C4 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_STATE_MON 0x06B4 +#define REG_HI3Q_TXBD_DESA_H 0x13C4 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_ERROR_MON 0x06B8 -#define REG_SEARCH_MACID 0x06BC +#define REG_HI15Q_TXBD_NUM 0x13C6 +#define REG_HIQ_DMA_STOP 0x13C8 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_COEX_TABLE 0x06C0 +#define REG_HI4Q_TXBD_DESA_L 0x13C8 +#define REG_HI4Q_TXBD_DESA_H 0x13CC +#define REG_HI5Q_TXBD_DESA_L 0x13D0 +#define REG_HI5Q_TXBD_DESA_H 0x13D4 +#define REG_HI6Q_TXBD_DESA_L 0x13D8 +#define REG_HI6Q_TXBD_DESA_H 0x13DC +#define REG_HI7Q_TXBD_DESA_L 0x13E0 +#define REG_HI7Q_TXBD_DESA_H 0x13E4 +#define REG_ACH8_ACH9_TXBD_NUM 0x13E8 +#define REG_ACH10_ACH11_TXBD_NUM 0x13EC +#define REG_ACH12_ACH13_TXBD_NUM 0x13F0 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RXCMD_0 0x06D0 -#define REG_RXCMD_1 0x06D4 +#define REG_OLD_DEHANG 0x13F4 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WMAC_RESP_TXINFO 0x06D8 +#define REG_ACH4_TXBD_DESA_L 0x13F8 +#define REG_ACH4_TXBD_DESA_H 0x13FC #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BBPSF_CTRL 0x06DC +#define REG_Q0_Q1_INFO 0x1400 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_P2P_RX_BCN_NOA 0x06E0 -#define REG_ASSOCIATED_BFMER0_INFO 0x06E4 -#define REG_ASSOCIATED_BFMER1_INFO 0x06EC -#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4 -#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8 -#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC -#define REG_MACID1 0x0700 +#define REG_ARFR6 0x1400 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_MACID1_1 0x0704 +#define REG_MU_OFFSET 0x1400 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BSSID1 0x0708 +#define REG_Q2_Q3_INFO 0x1404 +#define REG_Q4_Q5_INFO 0x1408 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_BSSID1_1 0x070C +#define REG_ARFR7 0x1408 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BCN_PSR_RPT1 0x0710 -#define REG_ASSOCIATED_BFMEE_SEL 0x0714 -#define REG_SND_PTCL_CTRL 0x0718 -#define REG_RX_CSI_RPT_INFO 0x071C -#define REG_NS_ARP_CTRL 0x0720 -#define REG_NS_ARP_INFO 0x0724 +#define REG_Q6_Q7_INFO 0x140C +#define REG_MGQ_HIQ_INFO 0x1410 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_NS_ARP_IPADDR 0x0728 +#define REG_ARFR8 0x1410 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BEAMFORMING_INFO_NSARP_V1 0x0728 +#define REG_CMDQ_BCNQ_INFO 0x1414 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WRITE_RX_CSI_RPT_INFO 0x072C +#define REG_USEREG_SETTING 0x1420 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BEAMFORMING_INFO_NSARP 0x072C +#define REG_AESIV_SETTING 0x1424 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_NS_ARP_IPV6_MYADDR 0x0730 +#define REG_BF0_TIME_SETTING 0x1428 +#define REG_BF1_TIME_SETTING 0x142C +#define REG_BF_TIMEOUT_EN 0x1430 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_IPV6 0x0730 -#define REG_IPV6_1 0x0734 -#define REG_IPV6_2 0x0738 -#define REG_IPV6_3 0x073C +#define REG_MACID_RELEASE0 0x1434 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750 +#define REG_MACID_RELEASE_INFO 0x1434 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_SWAES_CFG 0x0760 +#define REG_MACID_RELEASE1 0x1438 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_COEX_V2 0x0762 +#define REG_MACID_RELEASE_SUCCESS_INFO 0x1438 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_COEX 0x0764 +#define REG_MACID_RELEASE2 0x143C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WLAN_ACT_MSK_CTRL 0x0768 +#define REG_MACID_RELEASE_CTRL 0x143C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WLAN_ACT_MASK_CTRL 0x0768 +#define REG_MACID_RELEASE3 0x1440 +#define REG_MACID_RELEASE_SETTING 0x1444 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_WLAN_ACT_MASK_CTRL_1 0x076C +#define REG_FAST_EDCA_VOVI_SETTING 0x1448 +#define REG_FAST_EDCA_BEBK_SETTING 0x144C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_STATISTICS_CTRL 0x076E -#define REG_BT_COEX_ENH_INTF_CTRL 0x076E +#define REG_MACID_DROP0 0x1450 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E +#define REG_MACID_DROP_INFO 0x1450 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_ACT_STATISTICS 0x0770 +#define REG_MACID_DROP1 0x1454 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_BT_ACT_STATISTICS_1 0x0774 +#define REG_MACID_DROP_CTRL 0x1454 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_STATISTICS_OTH_CTRL 0x0778 +#define REG_MACID_DROP2 0x1458 +#define REG_MACID_DROP3 0x145C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778 +#define REG_R_MACID_RELEASE_SUCCESS_0 0x1460 +#define REG_R_MACID_RELEASE_SUCCESS_1 0x1464 +#define REG_R_MACID_RELEASE_SUCCESS_2 0x1468 +#define REG_R_MACID_RELEASE_SUCCESS_3 0x146C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_CMD_ID 0x077C +#define REG_MGG_FIFO_CRTL 0x1470 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_STATUS_REPORT_REGISTER 0x077C +#define REG_MGQ_FIFO_WRITE_POINTER 0x1470 +#define REG_MGQ_FIFO_READ_POINTER 0x1472 +#define REG_MGQ_FIFO_ENABLE 0x1472 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT__STATUS_RPT 0x077D -#define REG_BT_DATA 0x0780 +#define REG_MGG_FIFO_INT 0x1474 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780 +#define REG_MGQ_FIFO_RELEASE_INT_MASK 0x1474 +#define REG_MGQ_FIFO_RELEASE_INT_FLAG 0x1476 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WLAN_RPT_ 0x0781 -#define REG_BT_ISR_CTRL 0x0783 -#define REG_WLAN_RPT_TO_CTR 0x0784 +#define REG_MGG_FIFO_LIFETIME 0x1478 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784 +#define REG_MGQ_FIFO_VALID_MAP 0x1478 +#define REG_MGQ_FIFO_LIFETIME 0x147A #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_ISOLATION_TABLE 0x0785 +#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785 +#define REG_SHCUT_SETTING 0x1480 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 0x0788 -#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 0x078C +#define REG_PKT_TRANS 0x1480 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_ISR_STA 0x078F +#define REG_SHCUT_LLC_ETH_TYPE0 0x1484 +#define REG_SHCUT_LLC_ETH_TYPE1 0x1488 +#define REG_SHCUT_LLC_OUI0 0x148C +#define REG_SHCUT_LLC_OUI1 0x1490 +#define REG_SHCUT_LLC_OUI2 0x1494 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F +#define REG_SHCUT_LLC_OUI3 0x1498 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TDMA_TIME_AND_RPT_SAM_SET 0x0790 +#define REG_FWCMDQ_CTRL 0x14A0 +#define REG_FWCMDQ_PAGE 0x14A4 +#define REG_FWCMDQ_INFO 0x14A8 +#define REG_FWCMDQ_HOLD_PKTNUM 0x14AC +#define REG_MU_TX_CTRL 0x14C0 #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_TDMA_TIME_REGISTER 0x0790 +#define REG_MU_TX_CTL 0x14C0 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_CH_INFO 0x0794 +#define REG_MU_STA_GID_VLD 0x14C4 +#define REG_MU_STA_USER_POS_INFO 0x14C8 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_ACT_REGISTER 0x0794 +#define REG_MU_STA_USER_POS_INFO_H 0x14CC #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_STATIC_INFO_EXT 0x0795 -#define REG_LTR_IDLE_LATENCY 0x0798 +#define REG_CHNL_INFO_CTRL 0x14D0 #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_OBFF_CTRL_BASIC 0x0798 +#define REG_MU_TRX_DBG_CNT 0x14D0 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_LTR_ACTIVE_LATENCY 0x079C +#define REG_CHNL_IDLE_TIME 0x14D4 +#define REG_CHNL_BUSY_TIME 0x14D8 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_OBFF_CTRL2_TIMER 0x079C +#define REG_MU_TRX_DBG_CNT_V1 0x14DC #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_OBFF_CTRL 0x07A0 +#define REG_NEW_EDCA_CTRL 0x14F0 #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_LTR_CTRL_BASIC 0x07A0 +#define REG_SWPS_CTRL 0x14F4 +#define REG_SWPS_PKT_TH 0x14F6 +#define REG_SWPS_TIME_TH 0x14F8 +#define REG_MACID_SWPS_EN 0x14FC #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_LTR_CTRL 0x07A4 +#define REG_CPUMGQ_TX_TIMER 0x1500 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4 +#define REG_PORT_CTRL_SEL 0x1500 +#define REG_PORT_CTRL_CFG 0x1501 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_LTR_CTRL2 0x07A8 +#define REG_PS_TIMER_A 0x1504 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_LTR_IDLE_LATENCY_V1 0x07A8 -#define REG_LTR_ACTIVE_LATENCY_V1 0x07AC +#define REG_TBTT_PROHIBIT_CFG 0x1504 +#define REG_DRVERLYINT_CFG 0x1507 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_ANTTRN_CTRL 0x07B0 +#define REG_PS_TIMER_B 0x1508 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0 +#define REG_BCNDMATIM_CFG 0x1508 +#define REG_CTWND_CFG 0x1509 +#define REG_BCNIVLCUNT_CFG 0x150A +#define REG_EARLY_128US_CFG 0x150B #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 0x07B4 +#define REG_PS_TIMER_C 0x150C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WMAC_PKTCNT_RWD 0x07B8 -#define REG_WMAC_PKTCNT_CTRL 0x07BC +#define REG_TSFTR_SYNC_OFFSET_CFG 0x150C +#define REG_TSFTR_SYNC_CTRL_CFG 0x150F #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_IQ_DUMP 0x07C0 +#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_IQ_DUMP_1 0x07C4 -#define REG_IQ_DUMP_2 0x07C8 +#define REG_BCN_SPACE_CFG 0x1510 +#define REG_EARLY_INT_ADJUST_CFG 0x1512 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_FTM_CTL 0x07CC +#define REG_CPUMGQ_TX_TIMER_EARLY 0x1514 +#define REG_PS_TIMER_A_EARLY 0x1515 +#define REG_PS_TIMER_B_EARLY 0x1516 +#define REG_PS_TIMER_C_EARLY 0x1517 #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_IQ_MDPK_FUNC 0x07CE +#define REG_CPUMGQ_PARAMETER 0x1518 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_IQ_DUMP_EXT 0x07CF +#define REG_SW_TBTT_TSF_INFO 0x151C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_OFDM_CCK_LEN_MASK 0x07D0 +#define REG_TSF_SYN_CTRL0 0x1520 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_OPTION_FUNCTION 0x07D0 +#define REG_TSFTR_LOW 0x1520 #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_WMAC_OPTION_FUNCTION_1 0x07D4 -#define REG_WMAC_OPTION_FUNCTION_2 0x07D8 +#define REG_TSF_SYNC_ADJ 0x1520 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RX_FILTER_FUNCTION 0x07DA +#define REG_TSF_SYN_CTRL1 0x1521 +#define REG_TSF_SYN_OFFSET0 0x1522 +#define REG_TSF_SYN_OFFSET1 0x1524 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_NDP_SIG 0x07E0 -#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4 +#define REG_TSFTR_HIGH 0x1524 #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) - -#define REG_SEC_OPT 0x07E8 +#define REG_TSF_ADJ_VLAUE 0x1524 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_TXCMD_INFO_FOR_RSP_PKT_1 0x07E8 +#define REG_TSF_SYN_OFFSET2 0x1528 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_SEC_OPT_V2 0x07EC +#define REG_BCN_ERR_CNT_MAC 0x1528 #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_WSEC_OPTION 0x07EC +#define REG_TSF_ADJ_VLAUE_2 0x1528 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RTS_ADDRESS_0 0x07F0 +#define REG_BCN_ERR_CNT_EDCCA 0x1529 +#define REG_BCN_ERR_CNT_CCA 0x152A +#define REG_BCN_ERR_CNT_INVALID 0x152B +#define REG_BCN_ERR_CNT_OTHERS 0x152C +#define REG_RX_BCN_TIMER 0x152D #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) - -#define REG_RTS_ADDR0 0x07F0 +#define REG_TSF_SYN_COMPARE_VALUE 0x1530 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_RTS_ADDRESS_0_1 0x07F4 +#define REG_TBTT_CTN_AREA_V1 0x1530 +#define REG_BCN_MAX_ERR_V1 0x1531 +#define REG_RXTSF_OFFSET_CCK_V1 0x1532 +#define REG_RXTSF_OFFSET_OFDM_V1 0x1533 +#define REG_SUB_BCN_SPACE 0x1534 +#define REG_MBID_NUM_V1 0x1535 +#define REG_MBSSID_CTRL_V1 0x1536 +#define REG_USTIME_TSF_V1 0x1538 +#define REG_BW_CFG 0x1539 +#define REG_ATIMWND_CFG 0x153A +#define REG_DTIM_COUNTER_CFG 0x153B +#define REG_ATIM_DTIM_CTRL_SEL 0x153C +#define REG_ATIMUGT_V1 0x153D +#define REG_BCNDROPCTRL_V1 0x153E +#define REG_DIS_ATIM_V1 0x1540 +#define REG_HIQ_NO_LMT_EN_V1 0x1544 +#define REG_P2PPS_CTRL_V1 0x1548 +#define REG_P2PPS_SPEC_STATE_V1 0x154A +#define REG_P2PPS_STATE_V1 0x154B +#define REG_P2PPS1_CTRL_V1 0x154C +#define REG_P2PPS1_SPEC_STATE_V1 0x154E +#define REG_P2PPS1_STATE_V1 0x154F +#define REG_P2PPS2_CTRL_V1 0x1550 +#define REG_P2PPS2_SPEC_STATE_V1 0x1552 +#define REG_P2PPS2_STATE_V1 0x1553 +#define REG_P2PON_DIS_TXTIME_V1 0x1554 +#define REG_P2POFF_DIS_TXTIME_V1 0x1555 +#define REG_CHG_POWER_BCN_AREA 0x1556 +#define REG_NOA_SEL 0x1557 +#define REG_NOA_PARAM_V1 0x1558 +#define REG_NOA_PARAM_1_V1 0x155C +#define REG_NOA_PARAM_2_V1 0x1560 +#define REG_NOA_PARAM_3_V1 0x1564 +#define REG_NOA_ON_ERLY_TIME_V1 0x1568 +#define REG_NOA_OFF_ERLY_TIME_V1 0x1569 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RTS_ADDRESS_1 0x07F8 +#define REG_P2PPS_HW_AUTO_PAUSE_CTRL 0x156C +#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL 0x1570 +#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL 0x1574 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) - -#define REG_RTS_ADDR1 0x07F8 +#define REG_RX_TBTT_SHIFT 0x1578 +#define REG_FREERUN_CNT_LOW 0x1580 +#define REG_FREERUN_CNT_HIGH 0x1584 +#define REG_CPUMGQ_TX_TIMER_V1 0x1588 +#define REG_PS_TIMER_0 0x158C +#define REG_PS_TIMER_1 0x1590 +#define REG_PS_TIMER_2 0x1594 +#define REG_PS_TIMER_3 0x1598 +#define REG_PS_TIMER_4 0x159C +#define REG_PS_TIMER_5 0x15A0 +#define REG_PS_TIMER_01_CTRL 0x15A4 +#define REG_PS_TIMER_23_CTRL 0x15A8 +#define REG_PS_TIMER_45_CTRL 0x15AC +#define REG_CPUMGQ_FREERUN_TIMER_CTRL 0x15B0 +#define REG_CPUMGQ_PROHIBIT 0x15B4 +#define REG_TIMER_COMPARE 0x15C0 +#define REG_TIMER_COMPARE_VALUE_LOW 0x15C4 +#define REG_TIMER_COMPARE_VALUE_HIGH 0x15C8 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_RTS_ADDRESS_1_1 0x07FC +#define REG_BCN_PSR_RPT2 0x1600 +#define REG_BCN_PSR_RPT3 0x1604 +#define REG_BCN_PSR_RPT4 0x1608 +#define REG_A1_ADDR_MASK 0x160C #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) - -#define REG__RPFM_MAP1 0x07FE +#define REG_RXPSF_CTRL 0x1610 +#define REG_RXPSF_TYPE_CTRL 0x1614 +#define REG_CAM_ACCESS_CTRL 0x1618 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SYS_CFG3 0x1000 -#define REG_SYS_CFG4 0x1034 +#define REG_CUT_AMSDU_CTRL 0x161C #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SYS_CFG5 0x1070 +#define REG_HT_SND_REF_RATE 0x161C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_CPU_DMEM_CON 0x1080 +#define REG_MACID2 0x1620 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BOOT_REASON 0x1088 -#define REG_NFCPAD_CTRL 0x10A8 +#define REG_MACID2_H 0x1624 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_HIMR2 0x10B0 -#define REG_HISR2 0x10B4 -#define REG_HIMR3 0x10B8 -#define REG_HISR3 0x10BC -#define REG_SW_MDIO 0x10C0 -#define REG_SW_FLUSH 0x10C4 +#define REG_BSSID2 0x1628 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_DBG_GPIO_BMUX 0x10C8 -#define REG_FPGA_TAG 0x10CC -#define REG_WL_DSS_CTRL0 0x10D0 +#define REG_BSSID2_H 0x162C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_H2C_PKT_READADDR 0x10D0 -#define REG_H2C_PKT_WRITEADDR 0x10D4 +#define REG_MACID3 0x1630 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_WL_DSS_CTRL1 0x10D8 +#define REG_MACID3_H 0x1634 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_MEM_PWR_CRTL 0x10D8 +#define REG_BSSID3 0x1638 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_WL_DSS_STATUS1 0x10DC +#define REG_BSSID3_H 0x163C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FW_DBG0 0x10E0 -#define REG_FW_DBG1 0x10E4 -#define REG_FW_DBG2 0x10E8 -#define REG_FW_DBG3 0x10EC -#define REG_FW_DBG4 0x10F0 -#define REG_FW_DBG5 0x10F4 -#define REG_FW_DBG6 0x10F8 -#define REG_FW_DBG7 0x10FC -#define REG_CR_EXT 0x1100 -#define REG_FWFF 0x1114 +#define REG_MACID4 0x1640 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RXFF_PTR_V1 0x1118 -#define REG_RXFF_WTR_V1 0x111C +#define REG_MACID4_H 0x1644 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FE2IMR 0x1120 -#define REG_FE2ISR 0x1124 -#define REG_FE3IMR 0x1128 -#define REG_FE3ISR 0x112C -#define REG_FE4IMR 0x1130 -#define REG_FE4ISR 0x1134 -#define REG_FT1IMR 0x1138 -#define REG_FT1ISR 0x113C -#define REG_SPWR0 0x1140 -#define REG_SPWR1 0x1144 -#define REG_SPWR2 0x1148 -#define REG_SPWR3 0x114C -#define REG_POWSEQ 0x1150 +#define REG_BSSID4 0x1648 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TC7_CTRL_V1 0x1158 -#define REG_TC8_CTRL_V1 0x115C +#define REG_BSSID4_H 0x164C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3 0x1160 -#define REG_RXBCN_TBTT_INTERVAL_PORT4 0x1164 +#define REG_NOA_REPORT 0x1650 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_EXT_QUEUE_REG 0x11C0 -#define REG_COUNTER_CONTROL 0x11C4 -#define REG_COUNTER_TH 0x11C8 -#define REG_COUNTER_SET 0x11CC -#define REG_COUNTER_OVERFLOW 0x11D0 -#define REG_TDE_LEN_TH 0x11D4 -#define REG_RDE_LEN_TH 0x11D8 -#define REG_PCIE_EXEC_TIME 0x11DC +#define REG_NOA_REPORT_1 0x1654 +#define REG_NOA_REPORT_2 0x1658 +#define REG_NOA_REPORT_3 0x165C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FT2IMR 0x11E0 -#define REG_FT2ISR 0x11E4 +#define REG_PWRBIT_SETTING 0x1660 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_MSG2 0x11F0 -#define REG_MSG3 0x11F4 -#define REG_MSG4 0x11F8 -#define REG_MSG5 0x11FC -#define REG_DDMA_CH0SA 0x1200 -#define REG_DDMA_CH0DA 0x1204 -#define REG_DDMA_CH0CTRL 0x1208 -#define REG_DDMA_CH1SA 0x1210 -#define REG_DDMA_CH1DA 0x1214 -#define REG_DDMA_CH1CTRL 0x1218 -#define REG_DDMA_CH2SA 0x1220 -#define REG_DDMA_CH2DA 0x1224 -#define REG_DDMA_CH2CTRL 0x1228 -#define REG_DDMA_CH3SA 0x1230 -#define REG_DDMA_CH3DA 0x1234 -#define REG_DDMA_CH3CTRL 0x1238 -#define REG_DDMA_CH4SA 0x1240 -#define REG_DDMA_CH4DA 0x1244 -#define REG_DDMA_CH4CTRL 0x1248 -#define REG_DDMA_CH5SA 0x1250 -#define REG_DDMA_CH5DA 0x1254 +#define REG_GENERAL_OPTION 0x1664 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_REG_DDMA_CH5CTRL 0x1258 +#define REG_FWPHYFF_RCR 0x1668 +#define REG_ADDRCAM_WRITE_CONTENT 0x166C +#define REG_ADDRCAM_READ_CONTENT 0x1670 +#define REG_ADDRCAM_CFG 0x1674 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_DDMA_CH5CTRL 0x1258 +#define REG_WMAC_CSI_FRAME_RRSR_SETTING 0x1678 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DDMA_INT_MSK 0x12E0 -#define REG_DDMA_CHSTATUS 0x12E8 -#define REG_DDMA_CHKSUM 0x12F0 -#define REG_DDMA_MONITOR 0x12FC +#define REG_CSI_RRSR 0x1678 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_STC_INT_CS 0x1300 -#define REG_ST_INT_CFG 0x1304 -#define REG_CMU_DLY_CTRL 0x1310 -#define REG_CMU_DLY_CFG 0x1314 -#define REG_H2CQ_TXBD_DESA 0x1320 -#define REG_H2CQ_TXBD_NUM 0x1328 -#define REG_H2CQ_TXBD_IDX 0x132C -#define REG_H2CQ_CSR 0x1330 +#define REG_WMAC_MU_BF_OPTION 0x167C #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_AXI_EXCEPT_CS 0x1350 +#define REG_MU_BF_OPTION 0x167C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) - -#define REG_CHANGE_PCIE_SPEED 0x1350 +#define REG_WMAC_PAUSE_BB_CLR_TH 0x167D #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_AXI_EXCEPT_TIME 0x1354 +#define REG_WMAC_MU_ARB 0x167E #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) - -#define REG_OLD_DEHANG 0x13F4 +#define REG_WMAC_MULBK_BUF 0x167E #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_Q0_Q1_INFO 0x1400 -#define REG_Q2_Q3_INFO 0x1404 -#define REG_Q4_Q5_INFO 0x1408 -#define REG_Q6_Q7_INFO 0x140C -#define REG_MGQ_HIQ_INFO 0x1410 -#define REG_CMDQ_BCNQ_INFO 0x1414 -#define REG_USEREG_SETTING 0x1420 -#define REG_AESIV_SETTING 0x1424 -#define REG_BF0_TIME_SETTING 0x1428 -#define REG_BF1_TIME_SETTING 0x142C -#define REG_BF_TIMEOUT_EN 0x1430 -#define REG_MACID_RELEASE0 0x1434 -#define REG_MACID_RELEASE1 0x1438 -#define REG_MACID_RELEASE2 0x143C -#define REG_MACID_RELEASE3 0x1440 -#define REG_MACID_RELEASE_SETTING 0x1444 -#define REG_FAST_EDCA_VOVI_SETTING 0x1448 -#define REG_FAST_EDCA_BEBK_SETTING 0x144C -#define REG_MACID_DROP0 0x1450 -#define REG_MACID_DROP1 0x1454 -#define REG_MACID_DROP2 0x1458 -#define REG_MACID_DROP3 0x145C +#define REG__WMAC_MULBK_BUF 0x167E #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_R_MACID_RELEASE_SUCCESS_0 0x1460 -#define REG_R_MACID_RELEASE_SUCCESS_1 0x1464 -#define REG_R_MACID_RELEASE_SUCCESS_2 0x1468 -#define REG_R_MACID_RELEASE_SUCCESS_3 0x146C -#define REG_MGG_FIFO_CRTL 0x1470 -#define REG_MGG_FIFO_INT 0x1474 -#define REG_MGG_FIFO_LIFETIME 0x1478 -#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C +#define REG_WMAC_MU_OPTION 0x167F +#define REG_WMAC_MU_BF_CTL 0x1680 +#define REG_WMAC_MU_BFRPT_PARA 0x1682 +#define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684 +#define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686 +#define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688 +#define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A +#define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C +#define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_SHCUT_SETTING 0x1480 +#define REG_WMAC_BB_STOP_RX_COUNTER 0x1690 +#define REG_WMAC_PLCP_MONITOR 0x1694 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) - -#define REG_MACID_SHCUT_OFFSET 0x1480 +#define REG_WMAC_DEBUG_PORT 0x1698 #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_SHCUT_LLC_ETH_TYPE0 0x1484 -#define REG_SHCUT_LLC_ETH_TYPE1 0x1488 -#define REG_SHCUT_LLC_OUI0 0x148C -#define REG_SHCUT_LLC_OUI1 0x1490 -#define REG_SHCUT_LLC_OUI2 0x1494 -#define REG_SHCUT_LLC_OUI3 0x1498 +#define REG_WMAC_PLCP_MONITOR_MUTX 0x1698 #endif +#if (HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_MU_TX_CTL 0x14C0 -#define REG_MU_STA_GID_VLD 0x14C4 -#define REG_MU_STA_USER_POS_INFO 0x14C8 -#define REG_MU_TRX_DBG_CNT 0x14D0 +#define REG_WMAC_CSIDMA_CFG 0x169C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_CPUMGQ_TX_TIMER 0x1500 -#define REG_PS_TIMER_A 0x1504 -#define REG_PS_TIMER_B 0x1508 -#define REG_PS_TIMER_C 0x150C -#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510 -#define REG_CPUMGQ_TX_TIMER_EARLY 0x1514 -#define REG_PS_TIMER_A_EARLY 0x1515 -#define REG_PS_TIMER_B_EARLY 0x1516 -#define REG_PS_TIMER_C_EARLY 0x1517 +#define REG_TRANSMIT_ADDRSS_0 0x16A0 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BCN_PSR_RPT2 0x1600 -#define REG_BCN_PSR_RPT3 0x1604 -#define REG_BCN_PSR_RPT4 0x1608 -#define REG_A1_ADDR_MASK 0x160C -#define REG_MACID2 0x1620 -#define REG_BSSID2 0x1628 -#define REG_MACID3 0x1630 -#define REG_BSSID3 0x1638 -#define REG_MACID4 0x1640 -#define REG_BSSID4 0x1648 +#define REG_TRANSMIT_ADDRSS_0_H 0x16A4 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_NOA_REPORT 0x1650 -#define REG_PWRBIT_SETTING 0x1660 -#define REG_WMAC_MU_BF_OPTION 0x167C +#define REG_TRANSMIT_ADDRSS_1 0x16A8 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_WMAC_PAUSE_BB_CLR_TH 0x167D +#define REG_TRANSMIT_ADDRSS_1_H 0x16AC #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_MU_ARB 0x167E -#define REG_WMAC_MU_OPTION 0x167F -#define REG_WMAC_MU_BF_CTL 0x1680 +#define REG_TRANSMIT_ADDRSS_2 0x16B0 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_MU_BFRPT_PARA 0x1682 +#define REG_TRANSMIT_ADDRSS_2_H 0x16B4 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_WMAC_MU_BIT_BFRPT_PARA 0x1682 +#define REG_TRANSMIT_ADDRSS_3 0x16B8 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684 -#define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686 -#define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688 -#define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A -#define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C -#define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E +#define REG_TRANSMIT_ADDRSS_3_H 0x16BC #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_WMAC_BB_STOP_RX_COUNTER 0x1690 -#define REG_WMAC_PLCP_MONITOR 0x1694 -#define REG_WMAC_PLCP_MONITOR_MUTX 0x1698 +#define REG_TRANSMIT_ADDRSS_4 0x16C0 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TRANSMIT_ADDRSS_0 0x16A0 -#define REG_TRANSMIT_ADDRSS_1 0x16A8 -#define REG_TRANSMIT_ADDRSS_2 0x16B0 -#define REG_TRANSMIT_ADDRSS_3 0x16B8 -#define REG_TRANSMIT_ADDRSS_4 0x16C0 +#define REG_TRANSMIT_ADDRSS_4_H 0x16C4 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 -#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 -#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708 #endif +#if (HALMAC_8814B_SUPPORT) +#define REG_BIST_RSTN0 0x2100 +#define REG_BIST_RSTN2 0x2108 +#define REG_BIST_MODE_NRML0 0x2110 +#define REG_BIST_MODE_NRML1 0x2114 +#define REG_BIST_MODE_NRML2 0x2118 +#define REG_BIST_MODE_NRML3 0x211C +#define REG_BIST_DONE_NRML_MAC 0x2150 +#define REG_BIST_DONE_NRML1 0x2158 +#define REG_BIST_DONE_DRF_MAC 0x2160 +#define REG_BIST_DONE_DRF 0x2164 +#define REG_BIST_DONE_DRF1 0x2168 +#define REG_BIST_FAIL_NRML_MAC 0x2170 +#define REG_BIST_FAIL_NRML 0x2174 +#define REG_BIST_FAIL_NRML1 0x2178 +#define REG_BIST_FAIL_NRML_MAC_V1 0x2180 +#define REG_BIST_FAIL_NRML_V1 0x2184 +#define REG_BIST_FAIL_NRML1_V1 0x2188 +#define REG_BIST_MISR_DATAOUT 0x2190 +#define REG_BIST_MISR_DATAOUT1 0x2194 +#define REG_BIST_MISR_DATAOUT_CPU 0x2198 +#define REG_BIST_MISR_DATAOUT_CPU1 0x219C +#define REG_BIST_MISR_DATAOUT_CPU2 0x21A0 +#define REG_BIST_MISR_DATOUT_CPU3 0x21A4 +#define REG_DMA_RQPN_INFO_0 0x2200 +#define REG_DMA_RQPN_INFO_1 0x2204 +#define REG_DMA_RQPN_INFO_2 0x2208 +#define REG_DMA_RQPN_INFO_3 0x220C +#define REG_DMA_RQPN_INFO_4 0x2210 +#define REG_DMA_RQPN_INFO_5 0x2214 +#define REG_DMA_RQPN_INFO_6 0x2218 +#define REG_DMA_RQPN_INFO_7 0x221C +#define REG_DMA_RQPN_INFO_8 0x2220 +#define REG_DMA_RQPN_INFO_9 0x2224 +#define REG_DMA_RQPN_INFO_10 0x2228 +#define REG_DMA_RQPN_INFO_11 0x222C +#define REG_DMA_RQPN_INFO_12 0x2230 +#define REG_DMA_RQPN_INFO_13 0x2234 +#define REG_DMA_RQPN_INFO_14 0x2238 +#define REG_DMA_RQPN_INFO_15 0x223C +#define REG_DMA_RQPN_INFO_16 0x2240 +#define REG_HWAMSDU_CTL1 0x2250 +#define REG_HWAMSDU_CTL2 0x2254 +#define REG_HI8Q_TXBD_DESA_L 0x2300 +#define REG_HI8Q_TXBD_DESA_H 0x2304 +#define REG_HI9Q_TXBD_DESA_L 0x2308 +#define REG_HI9Q_TXBD_DESA_H 0x230C +#define REG_HI10Q_TXBD_DESA_L 0x2310 +#define REG_HI10Q_TXBD_DESA_H 0x2314 +#define REG_HI11Q_TXBD_DESA_L 0x2318 +#define REG_HI11Q_TXBD_DESA_H 0x231C +#define REG_HI12Q_TXBD_DESA_L 0x2320 +#define REG_HI12Q_TXBD_DESA_H 0x2324 +#define REG_HI13Q_TXBD_DESA_L 0x2328 +#define REG_HI13Q_TXBD_DESA_H 0x232C +#define REG_HI14Q_TXBD_DESA_L 0x2330 +#define REG_HI14Q_TXBD_DESA_H 0x2334 +#define REG_HI15Q_TXBD_DESA_L 0x2338 +#define REG_HI15Q_TXBD_DESA_H 0x233C +#define REG_HI16Q_TXBD_DESA_L 0x2340 +#define REG_HI16Q_TXBD_DESA_H 0x2344 +#define REG_HI17Q_TXBD_DESA_L 0x2348 +#define REG_HI17Q_TXBD_DESA_H 0x234C +#define REG_HI18Q_TXBD_DESA_L 0x2350 +#define REG_HI18Q_TXBD_DESA_H 0x2354 +#define REG_HI19Q_TXBD_DESA_L 0x2358 +#define REG_HI19Q_TXBD_DESA_H 0x235C +#define REG_BD_RWPTR_CLR6 0x2364 +#define REG_P0HI16Q_TXBD_IDX 0x2370 +#define REG_P0HI17Q_TXBD_IDX 0x2374 +#define REG_P0HI18Q_TXBD_IDX 0x2378 +#define REG_P0HI19Q_TXBD_IDX 0x237C +#define REG_P0HI16Q_HI17Q_TXBD_NUM 0x2380 +#define REG_P0HI18Q_HI19Q_TXBD_NUM 0x2384 +#define REG_PCIE_HISR0 0x23B4 + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define REG_PCIE_HISR2_V1 0x23B4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_HISR1 0x23BC + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define REG_PCIE_HISR3_V1 0x23BC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI8Q_HI9Q_TXBD_NUM 0x23C0 +#define REG_P0HI10Q_HI11Q_TXBD_NUM 0x23C4 +#define REG_P0HI12Q_HI13Q_TXBD_NUM 0x23C8 +#define REG_P0HI14Q_HI15Q_TXBD_NUM 0x23CC +#define REG_ACH6_ACH7_TXBD_NUM 0x23F0 +#define REG_TXPAGE_INT_CTRL_0 0x3200 +#define REG_TXPAGE_INT_CTRL_1 0x3204 +#define REG_TXPAGE_INT_CTRL_2 0x3208 +#define REG_TXPAGE_INT_CTRL_3 0x320C +#define REG_TXPAGE_INT_CTRL_4 0x3210 +#define REG_TXPAGE_INT_CTRL_5 0x3214 +#define REG_TXPAGE_INT_CTRL_6 0x3218 +#define REG_TXPAGE_INT_CTRL_7 0x321C +#define REG_TXPAGE_INT_CTRL_8 0x3220 +#define REG_TXPAGE_INT_CTRL_9 0x3224 +#define REG_TXPAGE_INT_CTRL_10 0x3228 +#define REG_TXPAGE_INT_CTRL_11 0x322C +#define REG_TXPAGE_INT_CTRL_12 0x3230 +#define REG_TXPAGE_INT_CTRL_13 0x3234 +#define REG_TXPAGE_INT_CTRL_14 0x3238 +#define REG_TXPAGE_INT_CTRL_15 0x323C +#define REG_TXPAGE_INT_CTRL_16 0x3240 +#define REG_ACH4_TXBD_IDX 0x3340 +#define REG_ACH5_TXBD_IDX 0x3344 +#define REG_ACH6_TXBD_IDX 0x3348 +#define REG_ACH7_TXBD_IDX 0x334C +#define REG_ACH8_TXBD_IDX 0x3350 +#define REG_ACH9_TXBD_IDX 0x3354 +#define REG_ACH10_TXBD_IDX 0x3358 +#define REG_ACH11_TXBD_IDX 0x335C +#define REG_ACH12_TXBD_IDX 0x3360 +#define REG_ACH13_TXBD_IDX 0x3364 +#define REG_AC_CHANNEL0_WEIGHT 0x3368 +#define REG_AC_CHANNEL1_WEIGHT 0x3369 +#define REG_AC_CHANNEL2_WEIGHT 0x336A +#define REG_AC_CHANNEL3_WEIGHT 0x336B +#define REG_AC_CHANNEL4_WEIGHT 0x336C +#define REG_AC_CHANNEL5_WEIGHT 0x336D +#define REG_AC_CHANNEL6_WEIGHT 0x336E +#define REG_AC_CHANNEL7_WEIGHT 0x336F +#define REG_AC_CHANNEL8_WEIGHT 0x3370 +#define REG_AC_CHANNEL9_WEIGHT 0x3371 +#define REG_AC_CHANNEL10_WEIGHT 0x3372 +#define REG_AC_CHANNEL11_WEIGHT 0x3373 +#define REG_AC_CHANNEL12_WEIGHT 0x3374 +#define REG_AC_CHANNEL13_WEIGHT 0x3375 +#define REG_PCIE_HISR2 0x33B4 +#define REG_PCIE_HISR3 0x33BC + +#endif /* ----------------------------------------------------- */ /* */ /* 0xFB00h ~ 0xFCFFh TX/RX packet buffer affress */ /* */ /* ----------------------------------------------------- */ -#define REG_RXPKTBUF_STARTADDR 0xFB00 -#define REG_TXPKTBUF_STARTADDR 0xFC00 +#define REG_RXPKTBUF_STARTADDR 0xFB00 +#define REG_TXPKTBUF_STARTADDR 0xFC00 /* ----------------------------------------------------- */ /* */ /* 0xFD00h ~ 0xFDFFh 8051 CPU Local REG */ /* */ /* ----------------------------------------------------- */ -#define REG_SYS_CTRL 0xFD00 -#define REG_PONSTS_RPT1 0xFD01 -#define REG_PONSTS_RPT2 0xFD02 -#define REG_PONSTS_RPT3 0xFD03 -#define REG_PONSTS_RPT4 0xFD04 /* 0x84 */ -#define REG_PONSTS_RPT5 0xFD05 /* 0x85 */ -#define REG_8051ERRFLAG 0xFD08 -#define REG_8051ERRFLAG_MASK 0xFD09 -#define REG_TXADDRH 0xFD10 /* Tx Packet High Address */ -#define REG_RXADDRH 0xFD11 /* Rx Packet High Address */ -#define REG_TXADDRH_EXT 0xFD12 /* 0xFD12[0] : for 8051 access txpktbuf high64k as external register */ - -#define REG_U3_STATE 0xFD48 /* (Read only) [7:4] : usb3 changed last state. [3:0] usb3 state */ +#define REG_SYS_CTRL 0xFD00 +#define REG_PONSTS_RPT1 0xFD01 +#define REG_PONSTS_RPT2 0xFD02 +#define REG_PONSTS_RPT3 0xFD03 +#define REG_PONSTS_RPT4 0xFD04 /* 0x84 */ +#define REG_PONSTS_RPT5 0xFD05 /* 0x85 */ +#define REG_8051ERRFLAG 0xFD08 +#define REG_8051ERRFLAG_MASK 0xFD09 +#define REG_TXADDRH 0xFD10 /* Tx Packet High Address */ +#define REG_RXADDRH 0xFD11 /* Rx Packet High Address */ +#define REG_TXADDRH_EXT 0xFD12 + +#define REG_U3_STATE 0xFD48 /* for MAILBOX */ -#define REG_OUTDATA0 0xFD50 -#define REG_OUTDATA1 0xFD54 -#define REG_OUTRDY 0xFD58 /* bit[0] : OutReady, bit[1] : OutEmptyIntEn */ +#define REG_OUTDATA0 0xFD50 +#define REG_OUTDATA1 0xFD54 +#define REG_OUTRDY 0xFD58 /* bit[0] : OutReady, bit[1] : OutEmptyIntEn */ -#define REG_INDATA0 0xFD60 -#define REG_INDATA1 0xFD64 -#define REG_INRDY 0xFD68 /* bit[0] : InReady, bit[1] : InRdyIntEn */ +#define REG_INDATA0 0xFD60 +#define REG_INDATA1 0xFD64 +#define REG_INRDY 0xFD68 /* bit[0] : InReady, bit[1] : InRdyIntEn */ /* MCU ERROR debug REG */ -#define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */ -#define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */ -#define REG_MCUERR_ACC 0xFD92 -#define REG_MCUERR_B 0xFD93 -#define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */ -#define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */ -#define REG_MCUERR_SP 0xFD96 /* SP[7:0] */ -#define REG_MCUERR_IE 0xFD97 /* IE[7:0] */ -#define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */ -#define REG_VERA_SIM 0xFD9F +#define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */ +#define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */ +#define REG_MCUERR_ACC 0xFD92 +#define REG_MCUERR_B 0xFD93 +#define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */ +#define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */ +#define REG_MCUERR_SP 0xFD96 /* SP[7:0] */ +#define REG_MCUERR_IE 0xFD97 /* IE[7:0] */ +#define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */ +#define REG_VERA_SIM 0xFD9F /* 0xFD99~0xFD9F are reserved.. */ /* ----------------------------------------------------- */ @@ -3178,70 +6886,69 @@ /* ----------------------------------------------------- */ /* RTS5101 USB Register Definition */ -#define REG_USB_SETUP_DEC_INT 0xFE00 -#define REG_USB_DMACTL 0xFE01 -#define REG_USB_IRQSTAT0 0xFE02 -#define REG_USB_IRQSTAT1 0xFE03 -#define REG_USB_IRQEN0 0xFE04 -#define REG_USB_IRQEN1 0xFE05 -#define REG_USB_AUTOPTRL 0xFE06 -#define REG_USB_AUTOPTRH 0xFE07 -#define REG_USB_AUTODAT 0xFE08 - -#define REG_USB_SCRATCH0 0xFE09 -#define REG_USB_SCRATCH1 0xFE0A -#define REG_USB_SEEPROM 0xFE0B -#define REG_USB_GPIO0 0xFE0C -#define REG_USB_GPIO0DIR 0xFE0D -#define REG_USB_CLKSEL 0xFE0E -#define REG_USB_BOOTCTL 0xFE0F - -#define REG_USB_USBCTL 0xFE10 -#define REG_USB_USBSTAT 0xFE11 -#define REG_USB_DEVADDR 0xFE12 -#define REG_USB_USBTEST 0xFE13 -#define REG_USB_FNUM0 0xFE14 -#define REG_USB_FNUM1 0xFE15 - -#define REG_USB_EP_IDX 0xFE20 -#define REG_USB_EP_CFG 0xFE21 -#define REG_USB_EP_CTL 0xFE22 -#define REG_USB_EP_STAT 0xFE23 -#define REG_USB_EP_IRQ 0xFE24 -#define REG_USB_EP_IRQEN 0xFE25 -#define REG_USB_EP_MAXPKT0 0xFE26 -#define REG_USB_EP_MAXPKT1 0xFE27 -#define REG_USB_EP_DAT 0xFE28 -#define REG_USB_EP_BC0 0xFE29 -#define REG_USB_EP_BC1 0xFE2A -#define REG_USB_EP_TC0 0xFE2B -#define REG_USB_EP_TC1 0xFE2C -#define REG_USB_EP_TC2 0xFE2D -#define REG_USB_EP_CTL2 0xFE2E - -#define REG_USB_INFO 0xFE17 -#define REG_USB_SPECIAL_OPTION 0xFE55 -#define REG_USB_DMA_AGG_TO 0xFE5B -#define REG_USB_AGG_TO 0xFE5C -#define REG_USB_AGG_TH 0xFE5D - -#define REG_USB_VID 0xFE60 -#define REG_USB_PID 0xFE62 -#define REG_USB_OPT 0xFE64 -#define REG_USB_CONFIG 0xFE65 /* RX EP setting. 0xFE65 Bit[3:0] : RXQ, Bit[7:4] : INTQ */ - /* TX EP setting. 0xFE66 Bit[3:0] : TXQ0, Bit[7:4] : TXQ1, 0xFE67 Bit[3:0] : TXQ2 */ -#define REG_USB_PHY_PARA1 0xFE68 /* Bit[7:4]: XCVR_SEN (USB PHY 0xE2[7:4]), Bit[3:0]: XCVR_SH (USB PHY 0xE2[3:0]) */ -#define REG_USB_PHY_PARA2 0xFE69 /* Bit[7:5]: XCVR_BG (USB PHY 0xE3[5:3]), Bit[4:2]: XCVR_DR (USB PHY 0xE3[2:0]), Bit[1]: SE0_LVL (USB PHY 0xE5[7]), Bit[0]: FORCE_XTL_ON (USB PHY 0xE5[1]) */ -#define REG_USB_PHY_PARA3 0xFE6A /* Bit[7:5]: XCVR_SRC (USB PHY 0xE5[4:2]), Bit[4]: LATE_DLLEN (USB PHY 0xF0[4]), Bit[3]: HS_LP_MODE (USB PHY 0xF0[3]), Bit[2]: UTMI_POS_OUT (USB PHY 0xF1 [7]), Bit[1:0]: TX_DELAY (USB PHY 0xF1 [2:1]) */ -#define REG_USB_PHY_PARA4 0xFE6B /* (USB PHY 0xE7[7:0]) */ -#define REG_USB_OPT2 0xFE6C -#define REG_USB_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ -#define REG_USB_MANUFACTURE_SETTING 0xFE80 /* 0xFE80~0xFE90 Max : 32 bytes */ -#define REG_USB_PRODUCT_STRING 0xFEA0 /* 0xFEA0~0xFECF Max : 48 bytes */ -#define REG_USB_SERIAL_NUMBER_STRING 0xFED0 /* 0xFED0~0xFEDF Max : 12 bytes */ - -#define REG_USB_ALTERNATE_SETTING 0xFE4F -#define REG_USB_INT_BINTERVAL 0xFE6E -#define REG_USB_GPS_EP_CONFIG 0xFE6D - -#endif /* __HALMAC_COM_REG_H__ */ +#define REG_USB_SETUP_DEC_INT 0xFE00 +#define REG_USB_DMACTL 0xFE01 +#define REG_USB_IRQSTAT0 0xFE02 +#define REG_USB_IRQSTAT1 0xFE03 +#define REG_USB_IRQEN0 0xFE04 +#define REG_USB_IRQEN1 0xFE05 +#define REG_USB_AUTOPTRL 0xFE06 +#define REG_USB_AUTOPTRH 0xFE07 +#define REG_USB_AUTODAT 0xFE08 + +#define REG_USB_SCRATCH0 0xFE09 +#define REG_USB_SCRATCH1 0xFE0A +#define REG_USB_SEEPROM 0xFE0B +#define REG_USB_GPIO0 0xFE0C +#define REG_USB_GPIO0DIR 0xFE0D +#define REG_USB_CLKSEL 0xFE0E +#define REG_USB_BOOTCTL 0xFE0F + +#define REG_USB_USBCTL 0xFE10 +#define REG_USB_USBSTAT 0xFE11 +#define REG_USB_DEVADDR 0xFE12 +#define REG_USB_USBTEST 0xFE13 +#define REG_USB_FNUM0 0xFE14 +#define REG_USB_FNUM1 0xFE15 + +#define REG_USB_EP_IDX 0xFE20 +#define REG_USB_EP_CFG 0xFE21 +#define REG_USB_EP_CTL 0xFE22 +#define REG_USB_EP_STAT 0xFE23 +#define REG_USB_EP_IRQ 0xFE24 +#define REG_USB_EP_IRQEN 0xFE25 +#define REG_USB_EP_MAXPKT0 0xFE26 +#define REG_USB_EP_MAXPKT1 0xFE27 +#define REG_USB_EP_DAT 0xFE28 +#define REG_USB_EP_BC0 0xFE29 +#define REG_USB_EP_BC1 0xFE2A +#define REG_USB_EP_TC0 0xFE2B +#define REG_USB_EP_TC1 0xFE2C +#define REG_USB_EP_TC2 0xFE2D +#define REG_USB_EP_CTL2 0xFE2E + +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +#define REG_USB_VID 0xFE60 +#define REG_USB_PID 0xFE62 +#define REG_USB_OPT 0xFE64 +#define REG_USB_CONFIG 0xFE65 + +#define REG_USB_PHY_PARA1 0xFE68 +#define REG_USB_PHY_PARA2 0xFE69 +#define REG_USB_PHY_PARA3 0xFE6A +#define REG_USB_OPT2 0xFE6C +#define REG_USB_MAC_ADDR 0xFE70 +#define REG_USB_MANUFACTURE_SETTING 0xFE80 +#define REG_USB_PRODUCT_STRING 0xFEA0 +#define REG_USB_SERIAL_NUMBER_STRING 0xFED0 + +#define REG_USB_ALTERNATE_SETTING 0xFE4F +#define REG_USB_INT_BINTERVAL 0xFE6E +#define REG_USB_GPS_EP_CONFIG 0xFE6D + +#endif /* __HALMAC_COM_REG_H__ */ diff --git a/hal/halmac/halmac_reg_8197f.h b/hal/halmac/halmac_reg_8197f.h index 997f6b0..6be0b3f 100644 --- a/hal/halmac/halmac_reg_8197f.h +++ b/hal/halmac/halmac_reg_8197f.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -224,7 +224,7 @@ #define REG_FWFF_C2H_8197F 0x0298 #define REG_FWFF_CTRL_8197F 0x029C #define REG_FWFF_PKT_INFO_8197F 0x02A0 -#define REG_FC2H_INFO_8197F 0x02A6 +#define REG_FC2H_INFO_8197F 0x02A4 #define REG_DDMA_CH0SA_8197F 0x1200 #define REG_DDMA_CH0DA_8197F 0x1204 #define REG_DDMA_CH0CTRL_8197F 0x1208 @@ -429,6 +429,9 @@ #define REG_SHCUT_LLC_OUI1_8197F 0x1490 #define REG_SHCUT_LLC_OUI2_8197F 0x1494 #define REG_SHCUT_LLC_OUI3_8197F 0x1498 +#define REG_CHNL_INFO_CTRL_8197F 0x14D0 +#define REG_CHNL_IDLE_TIME_8197F 0x14D4 +#define REG_CHNL_BUSY_TIME_8197F 0x14D8 #define REG_EDCA_VO_PARAM_8197F 0x0500 #define REG_EDCA_VI_PARAM_8197F 0x0504 #define REG_EDCA_BE_PARAM_8197F 0x0508 diff --git a/hal/halmac/halmac_reg_8814b.h b/hal/halmac/halmac_reg_8814b.h index ac587a5..9fb8ff5 100644 --- a/hal/halmac/halmac_reg_8814b.h +++ b/hal/halmac/halmac_reg_8814b.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -29,8 +29,11 @@ #define REG_RF_CTRL_8814B 0x001F #define REG_AFE_LDO_CTRL_8814B 0x0020 #define REG_AFE_CTRL1_8814B 0x0024 -#define REG_AFE_CTRL2_8814B 0x0028 -#define REG_AFE_CTRL3_8814B 0x002C +#define REG_ANAPARSW_POW_MAC_8814B 0x0028 +#define REG_ANAPARLDO_POW_MAC_8814B 0x0029 +#define REG_ANAPAR_POW_MAC_8814B 0x002A +#define REG_ANAPAR_POW_XTAL_8814B 0x002B +#define REG_ANAPARLDO_MAC_8814B 0x002C #define REG_EFUSE_CTRL_8814B 0x0030 #define REG_LDO_EFUSE_CTRL_8814B 0x0034 #define REG_PWR_OPTION_CTRL_8814B 0x0038 @@ -71,10 +74,8 @@ #define REG_DBG_PORT_SEL_8814B 0x00C0 #define REG_PAD_CTRL2_8814B 0x00C4 #define REG_PMC_DBG_CTRL2_8814B 0x00CC -#define REG_BIST_CTRL_8814B 0x00D0 -#define REG_BIST_RPT_8814B 0x00D4 #define REG_MEM_CTRL_8814B 0x00D8 -#define REG_AFE_CTRL8_8814B 0x00DC +#define REG_SYN_RFC_CTRL_8814B 0x00DC #define REG_USB_SIE_INTF_8814B 0x00E0 #define REG_PCIE_MIO_INTF_8814B 0x00E4 #define REG_PCIE_MIO_INTD_8814B 0x00E8 @@ -83,21 +84,51 @@ #define REG_SYS_STATUS1_8814B 0x00F4 #define REG_SYS_STATUS2_8814B 0x00F8 #define REG_SYS_CFG2_8814B 0x00FC -#define REG_SYS_CFG3_8814B 0x1000 -#define REG_SYS_CFG4_8814B 0x1034 +#define REG_ANAPARSW_MAC_0_8814B 0x1010 +#define REG_ANAPARSW_MAC_1_8814B 0x1014 +#define REG_ANAPAR_MAC_0_8814B 0x1018 +#define REG_ANAPAR_MAC_1_8814B 0x101C +#define REG_ANAPAR_MAC_2_8814B 0x1020 +#define REG_ANAPAR_MAC_3_8814B 0x1024 +#define REG_ANAPAR_MAC_4_8814B 0x1028 +#define REG_ANAPAR_MAC_5_8814B 0x102C +#define REG_ANAPAR_MAC_6_8814B 0x1030 +#define REG_ANAPAR_MAC_7_8814B 0x1034 +#define REG_ANAPAR_MAC_8_8814B 0x1038 +#define REG_ANAPAR_XTAL_0_8814B 0x1040 +#define REG_ANAPAR_XTAL_1_8814B 0x1044 +#define REG_ANAPAR_XTAL_2_8814B 0x1048 +#define REG_ANAPAR_XTAL_AAC_8814B 0x104C +#define REG_ANAPAR_XTAL_R_ONLY_8814B 0x1050 +#define REG_CPHY_LDO_8814B 0x1054 +#define REG_CPHY_BG_8814B 0x1058 +#define REG_HIMR_4_8814B 0x1060 +#define REG_HISR_4_8814B 0x1064 +#define REG_HIMR_5_8814B 0x1068 +#define REG_HISR_5_8814B 0x106C #define REG_SYS_CFG5_8814B 0x1070 +#define REG_HIMR_6_8814B 0x1078 +#define REG_HISR_6_8814B 0x107C #define REG_CPU_DMEM_CON_8814B 0x1080 #define REG_BOOT_REASON_8814B 0x1088 +#define REG_DATA_CPU_CTL0_8814B 0x1090 +#define REG_DATA_CPU_CTL1_8814B 0x1094 +#define REG_TXDMA_STOP_HIMR_8814B 0x1098 +#define REG_TXDMA_STOP_HISR_8814B 0x109C +#define REG_TXDMA_START_HIMR_8814B 0x10A0 +#define REG_TXDMA_START_HISR_8814B 0x10A4 #define REG_NFCPAD_CTRL_8814B 0x10A8 #define REG_HIMR2_8814B 0x10B0 #define REG_HISR2_8814B 0x10B4 #define REG_HIMR3_8814B 0x10B8 #define REG_HISR3_8814B 0x10BC #define REG_SW_MDIO_8814B 0x10C0 -#define REG_SW_FLUSH_8814B 0x10C4 +#define REG_HIMR_7_8814B 0x10C8 +#define REG_HISR_7_8814B 0x10CC #define REG_H2C_PKT_READADDR_8814B 0x10D0 #define REG_H2C_PKT_WRITEADDR_8814B 0x10D4 #define REG_MEM_PWR_CRTL_8814B 0x10D8 +#define REG_FW_DRV_HANDSHAKE_8814B 0x10DC #define REG_FW_DBG0_8814B 0x10E0 #define REG_FW_DBG1_8814B 0x10E4 #define REG_FW_DBG2_8814B 0x10E8 @@ -107,6 +138,7 @@ #define REG_FW_DBG6_8814B 0x10F8 #define REG_FW_DBG7_8814B 0x10FC #define REG_CR_8814B 0x0100 +#define REG_PG_SIZE_8814B 0x0104 #define REG_PKT_BUFF_ACCESS_CTRL_8814B 0x0106 #define REG_TSF_CLK_STATE_8814B 0x0108 #define REG_TXDMA_PQ_MAP_8814B 0x010C @@ -132,12 +164,10 @@ #define REG_TCUNIT_BASE_8814B 0x0164 #define REG_TC5_CTRL_8814B 0x0168 #define REG_TC6_CTRL_8814B 0x016C -#define REG_MBIST_FAIL_8814B 0x0170 -#define REG_MBIST_START_PAUSE_8814B 0x0174 -#define REG_MBIST_DONE_8814B 0x0178 -#define REG_MBIST_FAIL_NRML_8814B 0x017C #define REG_AES_DECRPT_DATA_8814B 0x0180 #define REG_AES_DECRPT_CFG_8814B 0x0184 +#define REG_HIOE_CTRL_8814B 0x0188 +#define REG_HIOE_CFG_FILE_8814B 0x018C #define REG_TMETER_8814B 0x0190 #define REG_OSC_32K_CTRL_8814B 0x0194 #define REG_32K_CAL_REG1_8814B 0x0198 @@ -145,6 +175,8 @@ #define REG_C2HEVT_1_8814B 0x01A4 #define REG_C2HEVT_2_8814B 0x01A8 #define REG_C2HEVT_3_8814B 0x01AC +#define REG_RXDESC_BUFF_RPTR_8814B 0x01B0 +#define REG_RXDESC_BUFF_WPTR_8814B 0x01B4 #define REG_SW_DEFINED_PAGE1_8814B 0x01B8 #define REG_SW_DEFINED_PAGE2_8814B 0x01BC #define REG_MCUTST_I_8814B 0x01C0 @@ -155,8 +187,7 @@ #define REG_HMEBOX1_8814B 0x01D4 #define REG_HMEBOX2_8814B 0x01D8 #define REG_HMEBOX3_8814B 0x01DC -#define REG_LLT_INIT_8814B 0x01E0 -#define REG_LLT_INIT_ADDR_8814B 0x01E4 +#define REG_RXDESC_BUFF_BNDY_8814B 0x01E0 #define REG_BB_ACCESS_CTRL_8814B 0x01E8 #define REG_BB_ACCESS_DATA_8814B 0x01EC #define REG_HMEBOX_E0_8814B 0x01F0 @@ -164,6 +195,10 @@ #define REG_HMEBOX_E2_8814B 0x01F8 #define REG_HMEBOX_E3_8814B 0x01FC #define REG_CR_EXT_8814B 0x1100 +#define REG_TC9_CTRL_8814B 0x1104 +#define REG_TC10_CTRL_8814B 0x1108 +#define REG_TC11_CTRL_8814B 0x110C +#define REG_TC12_CTRL_8814B 0x1110 #define REG_FWFF_8814B 0x1114 #define REG_RXFF_PTR_V1_8814B 0x1118 #define REG_RXFF_WTR_V1_8814B 0x111C @@ -182,36 +217,88 @@ #define REG_POWSEQ_8814B 0x1150 #define REG_TC7_CTRL_V1_8814B 0x1158 #define REG_TC8_CTRL_V1_8814B 0x115C +#define REG_RX_BCN_TBTT_ITVL0_8814B 0x1160 +#define REG_RX_BCN_TBTT_ITVL1_8814B 0x1164 +#define REG_FWIMR1_8814B 0x1168 +#define REG_FWISR1_8814B 0x116C +#define REG_FWIMR2_8814B 0x1170 +#define REG_FWISR2_8814B 0x1174 +#define REG_FWIMR3_8814B 0x1178 +#define REG_FWISR3_8814B 0x117C +#define REG_SPEED_SENSOR_8814B 0x1180 +#define REG_SPEED_SENSOR1_8814B 0x1184 +#define REG_SPEED_SENSOR2_8814B 0x1188 +#define REG_SPEED_SENSOR3_8814B 0x118C +#define REG_SPEED_SENSOR4_8814B 0x1190 +#define REG_SPEED_SENSOR5_8814B 0x1194 +#define REG_RXPKTBUF_1_MAX_ADDR_8814B 0x1198 +#define REG_RXFWBUF_1_MAX_ADDR_8814B 0x119C +#define REG_IO_WRAP_ERR_FLAG_V1_8814B 0x11A0 +#define REG_RXPKTBUF_1_READ_8814B 0x11A4 +#define REG_RXPKTBUF_1_WRITE_8814B 0x11A8 +#define REG_BUFF_DBGUG_8814B 0x11AC +#define REG_RFE_CTRL_PAD_E2_8814B 0x11B0 +#define REG_RFE_CTRL_PAD_SR_8814B 0x11B4 +#define REG_H2C_PRIORITY_SEL_8814B 0x11C0 +#define REG_COUNTER_CTRL_8814B 0x11C4 +#define REG_COUNTER_THRESHOLD_8814B 0x11C8 +#define REG_COUNTER_SET_8814B 0x11CC +#define REG_COUNTER_OVERFLOW_8814B 0x11D0 +#define REG_TXDMA_LEN_THRESHOLD_8814B 0x11D4 +#define REG_RXDMA_LEN_THRESHOLD_8814B 0x11D8 +#define REG_PCIE_EXEC_TIME_THRESHOLD_8814B 0x11DC #define REG_FT2IMR_8814B 0x11E0 #define REG_FT2ISR_8814B 0x11E4 #define REG_MSG2_8814B 0x11F0 #define REG_MSG3_8814B 0x11F4 #define REG_MSG4_8814B 0x11F8 #define REG_MSG5_8814B 0x11FC -#define REG_FIFOPAGE_CTRL_1_8814B 0x0200 -#define REG_FIFOPAGE_CTRL_2_8814B 0x0204 +#define REG_BIST_RSTN0_8814B 0x2100 +#define REG_BIST_RSTN2_8814B 0x2108 +#define REG_BIST_MODE_NRML0_8814B 0x2110 +#define REG_BIST_MODE_NRML1_8814B 0x2114 +#define REG_BIST_MODE_NRML2_8814B 0x2118 +#define REG_BIST_MODE_NRML3_8814B 0x211C +#define REG_BIST_DONE_NRML_MAC_8814B 0x2150 +#define REG_BIST_DONE_NRML1_8814B 0x2158 +#define REG_BIST_DONE_DRF_MAC_8814B 0x2160 +#define REG_BIST_DONE_DRF_8814B 0x2164 +#define REG_BIST_DONE_DRF1_8814B 0x2168 +#define REG_BIST_FAIL_NRML_MAC_8814B 0x2170 +#define REG_BIST_FAIL_NRML_8814B 0x2174 +#define REG_BIST_FAIL_NRML1_8814B 0x2178 +#define REG_BIST_FAIL_NRML_MAC_V1_8814B 0x2180 +#define REG_BIST_FAIL_NRML_V1_8814B 0x2184 +#define REG_BIST_FAIL_NRML1_V1_8814B 0x2188 +#define REG_BIST_MISR_DATAOUT_8814B 0x2190 +#define REG_BIST_MISR_DATAOUT1_8814B 0x2194 +#define REG_BIST_MISR_DATAOUT_CPU_8814B 0x2198 +#define REG_BIST_MISR_DATAOUT_CPU1_8814B 0x219C +#define REG_BIST_MISR_DATAOUT_CPU2_8814B 0x21A0 +#define REG_BIST_MISR_DATOUT_CPU3_8814B 0x21A4 +#define REG_BCN_CTRL_0_8814B 0x0200 +#define REG_BCN_CTRL_1_8814B 0x0204 #define REG_AUTO_LLT_V1_8814B 0x0208 #define REG_TXDMA_OFFSET_CHK_8814B 0x020C #define REG_TXDMA_STATUS_8814B 0x0210 #define REG_TX_DMA_DBG_8814B 0x0214 -#define REG_TQPNT1_8814B 0x0218 -#define REG_TQPNT2_8814B 0x021C -#define REG_TQPNT3_8814B 0x0220 -#define REG_TQPNT4_8814B 0x0224 -#define REG_RQPN_CTRL_1_8814B 0x0228 -#define REG_RQPN_CTRL_2_8814B 0x022C -#define REG_FIFOPAGE_INFO_1_8814B 0x0230 -#define REG_FIFOPAGE_INFO_2_8814B 0x0234 -#define REG_FIFOPAGE_INFO_3_8814B 0x0238 -#define REG_FIFOPAGE_INFO_4_8814B 0x023C -#define REG_FIFOPAGE_INFO_5_8814B 0x0240 +#define REG_DMA_RQPN_INFO_PUB_8814B 0x0218 +#define REG_RQPN_CTRL_2_V1_8814B 0x021C +#define REG_BCN_CTRL_2_8814B 0x0220 +#define REG_TXPKTNUM_0_8814B 0x0230 +#define REG_TXPKTNUM_1_8814B 0x0234 +#define REG_TXPKTNUM_2_8814B 0x0238 +#define REG_TXPKTNUM_3_8814B 0x023C +#define REG_TX_AGG_ALIGN_8814B 0x0240 #define REG_H2C_HEAD_8814B 0x0244 #define REG_H2C_TAIL_8814B 0x0248 #define REG_H2C_READ_ADDR_8814B 0x024C #define REG_H2C_WR_ADDR_8814B 0x0250 #define REG_H2C_INFO_8814B 0x0254 +#define REG_DMA_OQT_0_8814B 0x0260 +#define REG_DMA_OQT_1_8814B 0x0264 #define REG_RXDMA_AGG_PG_TH_8814B 0x0280 -#define REG_RXPKT_NUM_8814B 0x0284 +#define REG_RXDMA_CTRL_8814B 0x0284 #define REG_RXDMA_STATUS_8814B 0x0288 #define REG_RXDMA_DPR_8814B 0x028C #define REG_RXDMA_MODE_8814B 0x0290 @@ -219,6 +306,10 @@ #define REG_FWFF_C2H_8814B 0x0298 #define REG_FWFF_CTRL_8814B 0x029C #define REG_FWFF_PKT_INFO_8814B 0x02A0 +#define REG_FWFF_PKT_INFO2_8814B 0x02A4 +#define REG_RXPKTNUM_8814B 0x02B0 +#define REG_RXPKTNUM_TH_8814B 0x02B4 +#define REG_FW_UPD_RXDES_RDPTR_8814B 0x02B8 #define REG_DDMA_CH0SA_8814B 0x1200 #define REG_DDMA_CH0DA_8814B 0x1204 #define REG_DDMA_CH0CTRL_8814B 0x1208 @@ -241,59 +332,95 @@ #define REG_DDMA_CHSTATUS_8814B 0x12E8 #define REG_DDMA_CHKSUM_8814B 0x12F0 #define REG_DDMA_MONITOR_8814B 0x12FC +#define REG_DMA_RQPN_INFO_0_8814B 0x2200 +#define REG_DMA_RQPN_INFO_1_8814B 0x2204 +#define REG_DMA_RQPN_INFO_2_8814B 0x2208 +#define REG_DMA_RQPN_INFO_3_8814B 0x220C +#define REG_DMA_RQPN_INFO_4_8814B 0x2210 +#define REG_DMA_RQPN_INFO_5_8814B 0x2214 +#define REG_DMA_RQPN_INFO_6_8814B 0x2218 +#define REG_DMA_RQPN_INFO_7_8814B 0x221C +#define REG_DMA_RQPN_INFO_8_8814B 0x2220 +#define REG_DMA_RQPN_INFO_9_8814B 0x2224 +#define REG_DMA_RQPN_INFO_10_8814B 0x2228 +#define REG_DMA_RQPN_INFO_11_8814B 0x222C +#define REG_DMA_RQPN_INFO_12_8814B 0x2230 +#define REG_DMA_RQPN_INFO_13_8814B 0x2234 +#define REG_DMA_RQPN_INFO_14_8814B 0x2238 +#define REG_DMA_RQPN_INFO_15_8814B 0x223C +#define REG_DMA_RQPN_INFO_16_8814B 0x2240 +#define REG_HWAMSDU_CTL1_8814B 0x2250 +#define REG_HWAMSDU_CTL2_8814B 0x2254 +#define REG_TXPAGE_INT_CTRL_0_8814B 0x3200 +#define REG_TXPAGE_INT_CTRL_1_8814B 0x3204 +#define REG_TXPAGE_INT_CTRL_2_8814B 0x3208 +#define REG_TXPAGE_INT_CTRL_3_8814B 0x320C +#define REG_TXPAGE_INT_CTRL_4_8814B 0x3210 +#define REG_TXPAGE_INT_CTRL_5_8814B 0x3214 +#define REG_TXPAGE_INT_CTRL_6_8814B 0x3218 +#define REG_TXPAGE_INT_CTRL_7_8814B 0x321C +#define REG_TXPAGE_INT_CTRL_8_8814B 0x3220 +#define REG_TXPAGE_INT_CTRL_9_8814B 0x3224 +#define REG_TXPAGE_INT_CTRL_10_8814B 0x3228 +#define REG_TXPAGE_INT_CTRL_11_8814B 0x322C +#define REG_TXPAGE_INT_CTRL_12_8814B 0x3230 +#define REG_TXPAGE_INT_CTRL_13_8814B 0x3234 +#define REG_TXPAGE_INT_CTRL_14_8814B 0x3238 +#define REG_TXPAGE_INT_CTRL_15_8814B 0x323C +#define REG_TXPAGE_INT_CTRL_16_8814B 0x3240 #define REG_PCIE_CTRL_8814B 0x0300 -#define REG_INT_MIG_8814B 0x0304 -#define REG_BCNQ_TXBD_DESA_8814B 0x0308 -#define REG_MGQ_TXBD_DESA_8814B 0x0310 -#define REG_VOQ_TXBD_DESA_8814B 0x0318 -#define REG_VIQ_TXBD_DESA_8814B 0x0320 -#define REG_BEQ_TXBD_DESA_8814B 0x0328 -#define REG_BKQ_TXBD_DESA_8814B 0x0330 -#define REG_RXQ_RXBD_DESA_8814B 0x0338 -#define REG_HI0Q_TXBD_DESA_8814B 0x0340 -#define REG_HI1Q_TXBD_DESA_8814B 0x0348 -#define REG_HI2Q_TXBD_DESA_8814B 0x0350 -#define REG_HI3Q_TXBD_DESA_8814B 0x0358 -#define REG_HI4Q_TXBD_DESA_8814B 0x0360 -#define REG_HI5Q_TXBD_DESA_8814B 0x0368 -#define REG_HI6Q_TXBD_DESA_8814B 0x0370 -#define REG_HI7Q_TXBD_DESA_8814B 0x0378 -#define REG_MGQ_TXBD_NUM_8814B 0x0380 -#define REG_RX_RXBD_NUM_8814B 0x0382 -#define REG_VOQ_TXBD_NUM_8814B 0x0384 -#define REG_VIQ_TXBD_NUM_8814B 0x0386 -#define REG_BEQ_TXBD_NUM_8814B 0x0388 -#define REG_BKQ_TXBD_NUM_8814B 0x038A -#define REG_HI0Q_TXBD_NUM_8814B 0x038C -#define REG_HI1Q_TXBD_NUM_8814B 0x038E -#define REG_HI2Q_TXBD_NUM_8814B 0x0390 -#define REG_HI3Q_TXBD_NUM_8814B 0x0392 -#define REG_HI4Q_TXBD_NUM_8814B 0x0394 -#define REG_HI5Q_TXBD_NUM_8814B 0x0396 -#define REG_HI6Q_TXBD_NUM_8814B 0x0398 -#define REG_HI7Q_TXBD_NUM_8814B 0x039A +#define REG_ACH_CTRL_8814B 0x0304 +#define REG_HIQ_CTRL_8814B 0x0308 +#define REG_INT_MIG_V1_8814B 0x030C +#define REG_P0MGQ_TXBD_DESA_L_8814B 0x0310 +#define REG_P0MGQ_TXBD_DESA_H_8814B 0x0314 +#define REG_ACH0_TXBD_DESA_L_8814B 0x0318 +#define REG_ACH0_TXBD_DESA_H_8814B 0x031C +#define REG_ACH1_TXBD_DESA_L_8814B 0x0320 +#define REG_ACH1_TXBD_DESA_H_8814B 0x0324 +#define REG_ACH2_TXBD_DESA_L_8814B 0x0328 +#define REG_ACH2_TXBD_DESA_H_8814B 0x032C +#define REG_ACH3_TXBD_DESA_L_8814B 0x0330 +#define REG_ACH3_TXBD_DESA_H_8814B 0x0334 +#define REG_P0RXQ_RXBD_DESA_L_8814B 0x0338 +#define REG_P0RXQ_RXBD_DESA_H_8814B 0x033C +#define REG_P0BCNQ_TXBD_DESA_L_8814B 0x0340 +#define REG_P0BCNQ_TXBD_DESA_H_8814B 0x0344 +#define REG_FWCMDQ_TXBD_DESA_L_8814B 0x0348 +#define REG_FWCMDQ_TXBD_DESA_H_8814B 0x034C +#define REG_PCIE_HRPWM1_HCPWM1_DCPU_8814B 0x0354 +#define REG_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0x0358 +#define REG_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0x035C +#define REG_P0_MPRT_BCNQ_TXRXBD_NUM_8814B 0x036C +#define REG_BD_RWPTR_CLR2_8814B 0x0370 +#define REG_BD_RWPTR_CLR3_8814B 0x0374 +#define REG_P0MGQ_RXQ_TXRXBD_NUM_8814B 0x0378 +#define REG_CHNL_DMA_CFG_8814B 0x037C +#define REG_FWCMDQ_TXBD_NUM_8814B 0x0380 +#define REG_ACH0_ACH1_TXBD_NUM_8814B 0x0384 +#define REG_ACH2_ACH3_TXBD_NUM_8814B 0x0388 +#define REG_P0HI0Q_HI1Q_TXBD_NUM_8814B 0x038C +#define REG_P0HI2Q_HI3Q_TXBD_NUM_8814B 0x0390 +#define REG_P0HI4Q_HI5Q_TXBD_NUM_8814B 0x0394 +#define REG_P0HI6Q_HI7Q_TXBD_NUM_8814B 0x0398 +#define REG_BD_RWPTR_CLR1_8814B 0x039C #define REG_TSFTIMER_HCI_8814B 0x039C -#define REG_BD_RWPTR_CLR_8814B 0x039C -#define REG_VOQ_TXBD_IDX_8814B 0x03A0 -#define REG_VIQ_TXBD_IDX_8814B 0x03A4 -#define REG_BEQ_TXBD_IDX_8814B 0x03A8 -#define REG_BKQ_TXBD_IDX_8814B 0x03AC -#define REG_MGQ_TXBD_IDX_8814B 0x03B0 -#define REG_RXQ_RXBD_IDX_8814B 0x03B4 -#define REG_HI0Q_TXBD_IDX_8814B 0x03B8 -#define REG_HI1Q_TXBD_IDX_8814B 0x03BC -#define REG_HI2Q_TXBD_IDX_8814B 0x03C0 -#define REG_HI3Q_TXBD_IDX_8814B 0x03C4 -#define REG_HI4Q_TXBD_IDX_8814B 0x03C8 -#define REG_HI5Q_TXBD_IDX_8814B 0x03CC -#define REG_HI6Q_TXBD_IDX_8814B 0x03D0 -#define REG_HI7Q_TXBD_IDX_8814B 0x03D4 -#define REG_DBG_SEL_V1_8814B 0x03D8 -#define REG_PCIE_HRPWM1_V1_8814B 0x03D9 -#define REG_PCIE_HCPWM1_V1_8814B 0x03DA -#define REG_PCIE_CTRL2_8814B 0x03DB -#define REG_PCIE_HRPWM2_V1_8814B 0x03DC -#define REG_PCIE_HCPWM2_V1_8814B 0x03DE +#define REG_ACH0_TXBD_IDX_8814B 0x03A0 +#define REG_ACH1_TXBD_IDX_8814B 0x03A4 +#define REG_ACH2_TXBD_IDX_8814B 0x03A8 +#define REG_ACH3_TXBD_IDX_8814B 0x03AC +#define REG_P0MGQ_TXBD_IDX_8814B 0x03B0 +#define REG_P0RXQ_RXBD_IDX_8814B 0x03B4 +#define REG_P0HI0Q_TXBD_IDX_8814B 0x03B8 +#define REG_P0HI1Q_TXBD_IDX_8814B 0x03BC +#define REG_P0HI2Q_TXBD_IDX_8814B 0x03C0 +#define REG_P0HI3Q_TXBD_IDX_8814B 0x03C4 +#define REG_P0HI4Q_TXBD_IDX_8814B 0x03C8 +#define REG_P0HI5Q_TXBD_IDX_8814B 0x03CC +#define REG_P0HI6Q_TXBD_IDX_8814B 0x03D0 +#define REG_P0HI7Q_TXBD_IDX_8814B 0x03D4 +#define REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1_8814B 0x03D8 +#define REG_PCIE_HRPWM2_HCPWM2_V1_8814B 0x03DC #define REG_PCIE_H2C_MSG_V1_8814B 0x03E0 #define REG_PCIE_C2H_MSG_V1_8814B 0x03E4 #define REG_DBI_WDATA_V1_8814B 0x03E8 @@ -304,47 +431,165 @@ #define REG_HCI_MIX_CFG_8814B 0x03FC #define REG_STC_INT_CS_8814B 0x1300 #define REG_ST_INT_CFG_8814B 0x1304 -#define REG_CMU_DLY_CTRL_8814B 0x1310 -#define REG_CMU_DLY_CFG_8814B 0x1314 -#define REG_H2CQ_TXBD_DESA_8814B 0x1320 +#define REG_ACH4_ACH5_TXBD_NUM_8814B 0x130C +#define REG_FWCMDQ_TXBD_IDX_8814B 0x1318 +#define REG_P0HI8Q_TXBD_IDX_8814B 0x131C +#define REG_H2CQ_TXBD_DESA_L_8814B 0x1320 +#define REG_H2CQ_TXBD_DESA_H_8814B 0x1324 #define REG_H2CQ_TXBD_NUM_8814B 0x1328 #define REG_H2CQ_TXBD_IDX_8814B 0x132C #define REG_H2CQ_CSR_8814B 0x1330 -#define REG_Q0_INFO_8814B 0x0400 -#define REG_Q1_INFO_8814B 0x0404 -#define REG_Q2_INFO_8814B 0x0408 -#define REG_Q3_INFO_8814B 0x040C -#define REG_MGQ_INFO_8814B 0x0410 -#define REG_HIQ_INFO_8814B 0x0414 -#define REG_BCNQ_INFO_8814B 0x0418 -#define REG_TXPKT_EMPTY_8814B 0x041A +#define REG_P0HI9Q_TXBD_IDX_8814B 0x1334 +#define REG_P0HI10Q_TXBD_IDX_8814B 0x1338 +#define REG_P0HI11Q_TXBD_IDX_8814B 0x133C +#define REG_P0HI12Q_TXBD_IDX_8814B 0x1340 +#define REG_P0HI13Q_TXBD_IDX_8814B 0x1344 +#define REG_P0HI14Q_TXBD_IDX_8814B 0x1348 +#define REG_P0HI15Q_TXBD_IDX_8814B 0x134C +#define REG_CHANGE_PCIE_SPEED_8814B 0x1350 +#define REG_DEBUG_STATE1_8814B 0x1354 +#define REG_DEBUG_STATE2_8814B 0x1358 +#define REG_DEBUG_STATE3_8814B 0x135C +#define REG_ACH5_TXBD_DESA_L_8814B 0x1360 +#define REG_ACH5_TXBD_DESA_H_8814B 0x1364 +#define REG_ACH6_TXBD_DESA_L_8814B 0x1368 +#define REG_ACH6_TXBD_DESA_H_8814B 0x136C +#define REG_ACH7_TXBD_DESA_L_8814B 0x1370 +#define REG_ACH7_TXBD_DESA_H_8814B 0x1374 +#define REG_ACH8_TXBD_DESA_L_8814B 0x1378 +#define REG_ACH8_TXBD_DESA_H_8814B 0x137C +#define REG_ACH9_TXBD_DESA_L_8814B 0x1380 +#define REG_ACH9_TXBD_DESA_H_8814B 0x1384 +#define REG_ACH10_TXBD_DESA_L_8814B 0x1388 +#define REG_ACH10_TXBD_DESA_H_8814B 0x138C +#define REG_ACH11_TXBD_DESA_L_8814B 0x1390 +#define REG_ACH11_TXBD_DESA_H_8814B 0x1394 +#define REG_ACH12_TXBD_DESA_L_8814B 0x1398 +#define REG_ACH12_TXBD_DESA_H_8814B 0x139C +#define REG_ACH13_TXBD_DESA_L_8814B 0x13A0 +#define REG_ACH13_TXBD_DESA_H_8814B 0x13A4 +#define REG_HI0Q_TXBD_DESA_L_8814B 0x13A8 +#define REG_HI0Q_TXBD_DESA_H_8814B 0x13AC +#define REG_HI1Q_TXBD_DESA_L_8814B 0x13B0 +#define REG_HI1Q_TXBD_DESA_H_8814B 0x13B4 +#define REG_HI2Q_TXBD_DESA_L_8814B 0x13B8 +#define REG_HI2Q_TXBD_DESA_H_8814B 0x13BC +#define REG_HI3Q_TXBD_DESA_L_8814B 0x13C0 +#define REG_HI3Q_TXBD_DESA_H_8814B 0x13C4 +#define REG_HI4Q_TXBD_DESA_L_8814B 0x13C8 +#define REG_HI4Q_TXBD_DESA_H_8814B 0x13CC +#define REG_HI5Q_TXBD_DESA_L_8814B 0x13D0 +#define REG_HI5Q_TXBD_DESA_H_8814B 0x13D4 +#define REG_HI6Q_TXBD_DESA_L_8814B 0x13D8 +#define REG_HI6Q_TXBD_DESA_H_8814B 0x13DC +#define REG_HI7Q_TXBD_DESA_L_8814B 0x13E0 +#define REG_HI7Q_TXBD_DESA_H_8814B 0x13E4 +#define REG_ACH8_ACH9_TXBD_NUM_8814B 0x13E8 +#define REG_ACH10_ACH11_TXBD_NUM_8814B 0x13EC +#define REG_ACH12_ACH13_TXBD_NUM_8814B 0x13F0 +#define REG_OLD_DEHANG_8814B 0x13F4 +#define REG_ACH4_TXBD_DESA_L_8814B 0x13F8 +#define REG_ACH4_TXBD_DESA_H_8814B 0x13FC +#define REG_HI8Q_TXBD_DESA_L_8814B 0x2300 +#define REG_HI8Q_TXBD_DESA_H_8814B 0x2304 +#define REG_HI9Q_TXBD_DESA_L_8814B 0x2308 +#define REG_HI9Q_TXBD_DESA_H_8814B 0x230C +#define REG_HI10Q_TXBD_DESA_L_8814B 0x2310 +#define REG_HI10Q_TXBD_DESA_H_8814B 0x2314 +#define REG_HI11Q_TXBD_DESA_L_8814B 0x2318 +#define REG_HI11Q_TXBD_DESA_H_8814B 0x231C +#define REG_HI12Q_TXBD_DESA_L_8814B 0x2320 +#define REG_HI12Q_TXBD_DESA_H_8814B 0x2324 +#define REG_HI13Q_TXBD_DESA_L_8814B 0x2328 +#define REG_HI13Q_TXBD_DESA_H_8814B 0x232C +#define REG_HI14Q_TXBD_DESA_L_8814B 0x2330 +#define REG_HI14Q_TXBD_DESA_H_8814B 0x2334 +#define REG_HI15Q_TXBD_DESA_L_8814B 0x2338 +#define REG_HI15Q_TXBD_DESA_H_8814B 0x233C +#define REG_HI16Q_TXBD_DESA_L_8814B 0x2340 +#define REG_HI16Q_TXBD_DESA_H_8814B 0x2344 +#define REG_HI17Q_TXBD_DESA_L_8814B 0x2348 +#define REG_HI17Q_TXBD_DESA_H_8814B 0x234C +#define REG_HI18Q_TXBD_DESA_L_8814B 0x2350 +#define REG_HI18Q_TXBD_DESA_H_8814B 0x2354 +#define REG_HI19Q_TXBD_DESA_L_8814B 0x2358 +#define REG_HI19Q_TXBD_DESA_H_8814B 0x235C +#define REG_BD_RWPTR_CLR6_8814B 0x2364 +#define REG_P0HI16Q_TXBD_IDX_8814B 0x2370 +#define REG_P0HI17Q_TXBD_IDX_8814B 0x2374 +#define REG_P0HI18Q_TXBD_IDX_8814B 0x2378 +#define REG_P0HI19Q_TXBD_IDX_8814B 0x237C +#define REG_P0HI16Q_HI17Q_TXBD_NUM_8814B 0x2380 +#define REG_P0HI18Q_HI19Q_TXBD_NUM_8814B 0x2384 +#define REG_PCIE_HISR0_8814B 0x23B4 +#define REG_PCIE_HISR1_8814B 0x23BC +#define REG_P0HI8Q_HI9Q_TXBD_NUM_8814B 0x23C0 +#define REG_P0HI10Q_HI11Q_TXBD_NUM_8814B 0x23C4 +#define REG_P0HI12Q_HI13Q_TXBD_NUM_8814B 0x23C8 +#define REG_P0HI14Q_HI15Q_TXBD_NUM_8814B 0x23CC +#define REG_ACH6_ACH7_TXBD_NUM_8814B 0x23F0 +#define REG_ACH4_TXBD_IDX_8814B 0x3340 +#define REG_ACH5_TXBD_IDX_8814B 0x3344 +#define REG_ACH6_TXBD_IDX_8814B 0x3348 +#define REG_ACH7_TXBD_IDX_8814B 0x334C +#define REG_ACH8_TXBD_IDX_8814B 0x3350 +#define REG_ACH9_TXBD_IDX_8814B 0x3354 +#define REG_ACH10_TXBD_IDX_8814B 0x3358 +#define REG_ACH11_TXBD_IDX_8814B 0x335C +#define REG_ACH12_TXBD_IDX_8814B 0x3360 +#define REG_ACH13_TXBD_IDX_8814B 0x3364 +#define REG_AC_CHANNEL0_WEIGHT_8814B 0x3368 +#define REG_AC_CHANNEL1_WEIGHT_8814B 0x3369 +#define REG_AC_CHANNEL2_WEIGHT_8814B 0x336A +#define REG_AC_CHANNEL3_WEIGHT_8814B 0x336B +#define REG_AC_CHANNEL4_WEIGHT_8814B 0x336C +#define REG_AC_CHANNEL5_WEIGHT_8814B 0x336D +#define REG_AC_CHANNEL6_WEIGHT_8814B 0x336E +#define REG_AC_CHANNEL7_WEIGHT_8814B 0x336F +#define REG_AC_CHANNEL8_WEIGHT_8814B 0x3370 +#define REG_AC_CHANNEL9_WEIGHT_8814B 0x3371 +#define REG_AC_CHANNEL10_WEIGHT_8814B 0x3372 +#define REG_AC_CHANNEL11_WEIGHT_8814B 0x3373 +#define REG_AC_CHANNEL12_WEIGHT_8814B 0x3374 +#define REG_AC_CHANNEL13_WEIGHT_8814B 0x3375 +#define REG_PCIE_HISR2_8814B 0x33B4 +#define REG_PCIE_HISR3_8814B 0x33BC +#define REG_QUEUELIST_INFO0_8814B 0x0400 +#define REG_QUEUELIST_INFO1_8814B 0x0404 +#define REG_QUEUELIST_INFO2_8814B 0x0408 +#define REG_QUEUELIST_INFO3_8814B 0x040C +#define REG_QUEUELIST_INFO_EMPTY_8814B 0x0410 +#define REG_QUEUELIST_ACQ_EN_8814B 0x0414 +#define REG_BCNQ_BDNY_V2_8814B 0x0418 #define REG_CPU_MGQ_INFO_8814B 0x041C #define REG_FWHW_TXQ_CTRL_8814B 0x0420 #define REG_DATAFB_SEL_8814B 0x0423 -#define REG_BCNQ_BDNY_V1_8814B 0x0424 +#define REG_TXBDNY_8814B 0x0424 #define REG_LIFETIME_EN_8814B 0x0426 #define REG_SPEC_SIFS_8814B 0x0428 #define REG_RETRY_LIMIT_8814B 0x042A #define REG_TXBF_CTRL_8814B 0x042C #define REG_DARFRC_8814B 0x0430 +#define REG_DARFRCH_8814B 0x0434 #define REG_RARFRC_8814B 0x0438 +#define REG_RARFRCH_8814B 0x043C #define REG_RRSR_8814B 0x0440 #define REG_ARFR0_8814B 0x0444 -#define REG_ARFR1_V1_8814B 0x044C +#define REG_ARFRH0_8814B 0x0448 +#define REG_REG_ARFR_WT0_8814B 0x044C +#define REG_REG_ARFR_WT1_8814B 0x0450 #define REG_CCK_CHECK_8814B 0x0454 #define REG_AMPDU_MAX_TIME_V1_8814B 0x0455 -#define REG_BCNQ1_BDNY_V1_8814B 0x0456 -#define REG_AMPDU_MAX_LENGTH_8814B 0x0458 -#define REG_ACQ_STOP_8814B 0x045C +#define REG_TAB_SEL_8814B 0x0456 +#define REG_BCN_INVALID_CTRL_8814B 0x0457 +#define REG_AMPDU_MAX_LENGTH_HT_8814B 0x0458 #define REG_NDPA_RATE_8814B 0x045D #define REG_TX_HANG_CTRL_8814B 0x045E #define REG_NDPA_OPT_CTRL_8814B 0x045F +#define REG_AMPDU_MAX_LENGTH_VHT_8814B 0x0460 #define REG_RD_RESP_PKT_TH_8814B 0x0463 -#define REG_CMDQ_INFO_8814B 0x0464 -#define REG_Q4_INFO_8814B 0x0468 -#define REG_Q5_INFO_8814B 0x046C -#define REG_Q6_INFO_8814B 0x0470 -#define REG_Q7_INFO_8814B 0x0474 +#define REG_NEW_EDCA_CTRL_V1_8814B 0x0464 +#define REG_ACQ_STOP_V2_8814B 0x0468 #define REG_WMAC_LBK_BUF_HD_V1_8814B 0x0478 #define REG_MGQ_BDNY_V1_8814B 0x047A #define REG_TXRPT_CTRL_8814B 0x047C @@ -352,12 +597,8 @@ #define REG_BASIC_CFEND_RATE_8814B 0x0481 #define REG_STBC_CFEND_RATE_8814B 0x0482 #define REG_DATA_SC_8814B 0x0483 -#define REG_MACID_SLEEP3_8814B 0x0484 -#define REG_MACID_SLEEP1_8814B 0x0488 -#define REG_ARFR2_V1_8814B 0x048C -#define REG_ARFR3_V1_8814B 0x0494 -#define REG_ARFR4_8814B 0x049C -#define REG_ARFR5_8814B 0x04A4 +#define REG_MOREDATA_V1_8814B 0x0484 +#define REG_DATA_SC1_8814B 0x0487 #define REG_TXRPT_START_OFFSET_8814B 0x04AC #define REG_POWER_STAGE1_8814B 0x04B4 #define REG_POWER_STAGE2_8814B 0x04B8 @@ -370,55 +611,63 @@ #define REG_PROT_MODE_CTRL_8814B 0x04C8 #define REG_BAR_MODE_CTRL_8814B 0x04CC #define REG_RA_TRY_RATE_AGG_LMT_8814B 0x04CF -#define REG_MACID_SLEEP2_8814B 0x04D0 -#define REG_MACID_SLEEP_8814B 0x04D4 +#define REG_MACID_SLEEP_CTRL_8814B 0x04D0 +#define REG_MACID_SLEEP_INFO_8814B 0x04D4 #define REG_HW_SEQ0_8814B 0x04D8 #define REG_HW_SEQ1_8814B 0x04DA #define REG_HW_SEQ2_8814B 0x04DC #define REG_HW_SEQ3_8814B 0x04DE -#define REG_NULL_PKT_STATUS_V1_8814B 0x04E0 -#define REG_PTCL_ERR_STATUS_8814B 0x04E2 -#define REG_NULL_PKT_STATUS_EXTEND_8814B 0x04E3 -#define REG_VIDEO_ENHANCEMENT_FUN_8814B 0x04E4 -#define REG_BT_POLLUTE_PKT_CNT_8814B 0x04E8 -#define REG_PTCL_DBG_8814B 0x04EC +#define REG_PTCL_ERR_STATUS_V1_8814B 0x04E2 +#define REG_NULL_PKT_STATUS_V2_8814B 0x04E4 +#define REG_PRECNT_CTRL_8814B 0x04E5 +#define REG_NULL_PKT_STATUS_EXTEND_V1_8814B 0x04E7 +#define REG_PTCL_DBG_V1_8814B 0x04EC +#define REG_BT_POLLUTE_PKTCNT_8814B 0x04F0 #define REG_CPUMGQ_TIMER_CTRL2_8814B 0x04F4 +#define REG_PTCL_DBG_OUT_8814B 0x04F8 #define REG_DUMMY_PAGE4_V1_8814B 0x04FC -#define REG_MOREDATA_8814B 0x04FE -#define REG_Q0_Q1_INFO_8814B 0x1400 -#define REG_Q2_Q3_INFO_8814B 0x1404 -#define REG_Q4_Q5_INFO_8814B 0x1408 -#define REG_Q6_Q7_INFO_8814B 0x140C -#define REG_MGQ_HIQ_INFO_8814B 0x1410 -#define REG_CMDQ_BCNQ_INFO_8814B 0x1414 +#define REG_DUMMY_PAGE4_1_8814B 0x04FE +#define REG_MU_OFFSET_8814B 0x1400 #define REG_USEREG_SETTING_8814B 0x1420 -#define REG_AESIV_SETTING_8814B 0x1424 #define REG_BF0_TIME_SETTING_8814B 0x1428 #define REG_BF1_TIME_SETTING_8814B 0x142C #define REG_BF_TIMEOUT_EN_8814B 0x1430 -#define REG_MACID_RELEASE0_8814B 0x1434 -#define REG_MACID_RELEASE1_8814B 0x1438 -#define REG_MACID_RELEASE2_8814B 0x143C -#define REG_MACID_RELEASE3_8814B 0x1440 -#define REG_MACID_RELEASE_SETTING_8814B 0x1444 +#define REG_MACID_RELEASE_INFO_8814B 0x1434 +#define REG_MACID_RELEASE_SUCCESS_INFO_8814B 0x1438 +#define REG_MACID_RELEASE_CTRL_8814B 0x143C #define REG_FAST_EDCA_VOVI_SETTING_8814B 0x1448 #define REG_FAST_EDCA_BEBK_SETTING_8814B 0x144C -#define REG_MACID_DROP0_8814B 0x1450 -#define REG_MACID_DROP1_8814B 0x1454 -#define REG_MACID_DROP2_8814B 0x1458 -#define REG_MACID_DROP3_8814B 0x145C -#define REG_R_MACID_RELEASE_SUCCESS_0_8814B 0x1460 -#define REG_R_MACID_RELEASE_SUCCESS_1_8814B 0x1464 -#define REG_R_MACID_RELEASE_SUCCESS_2_8814B 0x1468 -#define REG_R_MACID_RELEASE_SUCCESS_3_8814B 0x146C -#define REG_MGG_FIFO_CRTL_8814B 0x1470 -#define REG_MGG_FIFO_INT_8814B 0x1474 -#define REG_MGG_FIFO_LIFETIME_8814B 0x1478 -#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B 0x147C -#define REG_MU_TX_CTL_8814B 0x14C0 +#define REG_MACID_DROP_INFO_8814B 0x1450 +#define REG_MACID_DROP_CTRL_8814B 0x1454 +#define REG_MGQ_FIFO_WRITE_POINTER_8814B 0x1470 +#define REG_MGQ_FIFO_READ_POINTER_8814B 0x1472 +#define REG_MGQ_FIFO_ENABLE_8814B 0x1472 +#define REG_MGQ_FIFO_RELEASE_INT_MASK_8814B 0x1474 +#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8814B 0x1476 +#define REG_MGQ_FIFO_VALID_MAP_8814B 0x1478 +#define REG_MGQ_FIFO_LIFETIME_8814B 0x147A +#define REG_PKT_TRANS_8814B 0x1480 +#define REG_SHCUT_LLC_ETH_TYPE0_8814B 0x1484 +#define REG_SHCUT_LLC_ETH_TYPE1_8814B 0x1488 +#define REG_SHCUT_LLC_OUI0_8814B 0x148C +#define REG_SHCUT_LLC_OUI1_8814B 0x1490 +#define REG_SHCUT_LLC_OUI2_8814B 0x1494 +#define REG_FWCMDQ_CTRL_8814B 0x14A0 +#define REG_FWCMDQ_PAGE_8814B 0x14A4 +#define REG_FWCMDQ_INFO_8814B 0x14A8 +#define REG_FWCMDQ_HOLD_PKTNUM_8814B 0x14AC +#define REG_MU_TX_CTRL_8814B 0x14C0 #define REG_MU_STA_GID_VLD_8814B 0x14C4 #define REG_MU_STA_USER_POS_INFO_8814B 0x14C8 -#define REG_MU_TRX_DBG_CNT_8814B 0x14D0 +#define REG_MU_STA_USER_POS_INFO_H_8814B 0x14CC +#define REG_CHNL_INFO_CTRL_8814B 0x14D0 +#define REG_CHNL_IDLE_TIME_8814B 0x14D4 +#define REG_CHNL_BUSY_TIME_8814B 0x14D8 +#define REG_MU_TRX_DBG_CNT_V1_8814B 0x14DC +#define REG_SWPS_CTRL_8814B 0x14F4 +#define REG_SWPS_PKT_TH_8814B 0x14F6 +#define REG_SWPS_TIME_TH_8814B 0x14F8 +#define REG_MACID_SWPS_EN_8814B 0x14FC #define REG_EDCA_VO_PARAM_8814B 0x0500 #define REG_EDCA_VI_PARAM_8814B 0x0504 #define REG_EDCA_BE_PARAM_8814B 0x0508 @@ -427,126 +676,141 @@ #define REG_PIFS_8814B 0x0512 #define REG_RDG_PIFS_8814B 0x0513 #define REG_SIFS_8814B 0x0514 -#define REG_TSFTR_SYN_OFFSET_8814B 0x0518 +#define REG_FORCE_BCN_IFS_V1_8814B 0x0518 #define REG_AGGR_BREAK_TIME_8814B 0x051A #define REG_SLOT_8814B 0x051B +#define REG_EDCA_CPUMGQ_PARAM_8814B 0x051C +#define REG_CPUMGQ_PAUSE_8814B 0x051E #define REG_TX_PTCL_CTRL_8814B 0x0520 #define REG_TXPAUSE_8814B 0x0522 #define REG_DIS_TXREQ_CLR_8814B 0x0523 #define REG_RD_CTRL_8814B 0x0524 -#define REG_MBSSID_CTRL_8814B 0x0526 -#define REG_P2PPS_CTRL_8814B 0x0527 #define REG_PKT_LIFETIME_CTRL_8814B 0x0528 -#define REG_P2PPS_SPEC_STATE_8814B 0x052B -#define REG_BAR_TX_CTRL_8814B 0x0530 -#define REG_TBTT_PROHIBIT_8814B 0x0540 -#define REG_P2PPS_STATE_8814B 0x0543 +#define REG_TXOP_LIMIT_CTRL_8814B 0x052C +#define REG_CCA_TXEN_CNT_8814B 0x0534 +#define REG_MAX_INTER_COLLISION_8814B 0x0538 +#define REG_MAX_INTER_COLLISION_CNT_8814B 0x053C #define REG_RD_NAV_NXT_8814B 0x0544 #define REG_NAV_PROT_LEN_8814B 0x0546 -#define REG_BCN_CTRL_8814B 0x0550 -#define REG_BCN_CTRL_CLINT0_8814B 0x0551 -#define REG_MBID_NUM_8814B 0x0552 -#define REG_DUAL_TSF_RST_8814B 0x0553 -#define REG_MBSSID_BCN_SPACE_8814B 0x0554 -#define REG_DRVERLYINT_8814B 0x0558 -#define REG_BCNDMATIM_8814B 0x0559 -#define REG_ATIMWND_8814B 0x055A -#define REG_USTIME_TSF_8814B 0x055C -#define REG_BCN_MAX_ERR_8814B 0x055D -#define REG_RXTSF_OFFSET_CCK_8814B 0x055E -#define REG_RXTSF_OFFSET_OFDM_8814B 0x055F -#define REG_TSFTR_8814B 0x0560 -#define REG_TSFTR_1_8814B 0x0564 -#define REG_FREERUN_CNT_8814B 0x0568 -#define REG_FREERUN_CNT_1_8814B 0x056C -#define REG_ATIMWND1_V1_8814B 0x0570 -#define REG_TBTT_PROHIBIT_INFRA_8814B 0x0571 -#define REG_CTWND_8814B 0x0572 -#define REG_BCNIVLCUNT_8814B 0x0573 -#define REG_BCNDROPCTRL_8814B 0x0574 +#define REG_FTM_PTT_8814B 0x0548 +#define REG_FTM_TSF_8814B 0x054C #define REG_HGQ_TIMEOUT_PERIOD_8814B 0x0575 #define REG_TXCMD_TIMEOUT_PERIOD_8814B 0x0576 #define REG_MISC_CTRL_8814B 0x0577 -#define REG_BCN_CTRL_CLINT1_8814B 0x0578 -#define REG_BCN_CTRL_CLINT2_8814B 0x0579 -#define REG_BCN_CTRL_CLINT3_8814B 0x057A -#define REG_EXTEND_CTRL_8814B 0x057B -#define REG_P2PPS1_SPEC_STATE_8814B 0x057C -#define REG_P2PPS1_STATE_8814B 0x057D -#define REG_P2PPS2_SPEC_STATE_8814B 0x057E -#define REG_P2PPS2_STATE_8814B 0x057F -#define REG_PS_TIMER0_8814B 0x0580 -#define REG_PS_TIMER1_8814B 0x0584 -#define REG_PS_TIMER2_8814B 0x0588 -#define REG_TBTT_CTN_AREA_8814B 0x058C -#define REG_FORCE_BCN_IFS_8814B 0x058E #define REG_TXOP_MIN_8814B 0x0590 #define REG_PRE_BKF_TIME_8814B 0x0592 #define REG_CROSS_TXOP_CTRL_8814B 0x0593 -#define REG_ATIMWND2_8814B 0x05A0 -#define REG_ATIMWND3_8814B 0x05A1 -#define REG_ATIMWND4_8814B 0x05A2 -#define REG_ATIMWND5_8814B 0x05A3 -#define REG_ATIMWND6_8814B 0x05A4 -#define REG_ATIMWND7_8814B 0x05A5 -#define REG_ATIMUGT_8814B 0x05A6 -#define REG_HIQ_NO_LMT_EN_8814B 0x05A7 -#define REG_DTIM_COUNTER_ROOT_8814B 0x05A8 -#define REG_DTIM_COUNTER_VAP1_8814B 0x05A9 -#define REG_DTIM_COUNTER_VAP2_8814B 0x05AA -#define REG_DTIM_COUNTER_VAP3_8814B 0x05AB -#define REG_DTIM_COUNTER_VAP4_8814B 0x05AC -#define REG_DTIM_COUNTER_VAP5_8814B 0x05AD -#define REG_DTIM_COUNTER_VAP6_8814B 0x05AE -#define REG_DTIM_COUNTER_VAP7_8814B 0x05AF -#define REG_DIS_ATIM_8814B 0x05B0 -#define REG_EARLY_128US_8814B 0x05B1 -#define REG_P2PPS1_CTRL_8814B 0x05B2 -#define REG_P2PPS2_CTRL_8814B 0x05B3 -#define REG_TIMER0_SRC_SEL_8814B 0x05B4 -#define REG_NOA_UNIT_SEL_8814B 0x05B5 -#define REG_P2POFF_DIS_TXTIME_8814B 0x05B7 -#define REG_MBSSID_BCN_SPACE2_8814B 0x05B8 -#define REG_MBSSID_BCN_SPACE3_8814B 0x05BC #define REG_ACMHWCTRL_8814B 0x05C0 #define REG_ACMRSTCTRL_8814B 0x05C1 #define REG_ACMAVG_8814B 0x05C2 #define REG_VO_ADMTIME_8814B 0x05C4 #define REG_VI_ADMTIME_8814B 0x05C6 #define REG_BE_ADMTIME_8814B 0x05C8 +#define REG_MAC_HEADER_NAV_OFFSET_8814B 0x05CA +#define REG_DIS_NDPA_NAV_CHECK_8814B 0x05CB #define REG_EDCA_RANDOM_GEN_8814B 0x05CC -#define REG_TXCMD_NOA_SEL_8814B 0x05CF -#define REG_NOA_PARAM_8814B 0x05E0 -#define REG_NOA_PARAM_1_8814B 0x05E4 -#define REG_NOA_PARAM_2_8814B 0x05E8 -#define REG_NOA_PARAM_3_8814B 0x05EC -#define REG_P2P_RST_8814B 0x05F0 +#define REG_TXCMD_SEL_8814B 0x05CF +#define REG_MU_DBG_INFO_8814B 0x05E8 +#define REG_MU_DBG_INFO_1_8814B 0x05EC +#define REG_SCH_DBG_SEL_8814B 0x05F0 #define REG_SCHEDULER_RST_8814B 0x05F1 +#define REG_MU_DBG_ERR_FLAG_8814B 0x05F2 +#define REG_TX_ERR_RECOVERY_RST_8814B 0x05F3 +#define REG_SCH_DBG_VALUE_8814B 0x05F4 #define REG_SCH_TXCMD_8814B 0x05F8 #define REG_PAGE5_DUMMY_8814B 0x05FC -#define REG_CPUMGQ_TX_TIMER_8814B 0x1500 -#define REG_PS_TIMER_A_8814B 0x1504 -#define REG_PS_TIMER_B_8814B 0x1508 -#define REG_PS_TIMER_C_8814B 0x150C -#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8814B 0x1510 -#define REG_CPUMGQ_TX_TIMER_EARLY_8814B 0x1514 -#define REG_PS_TIMER_A_EARLY_8814B 0x1515 -#define REG_PS_TIMER_B_EARLY_8814B 0x1516 -#define REG_PS_TIMER_C_EARLY_8814B 0x1517 +#define REG_PORT_CTRL_SEL_8814B 0x1500 +#define REG_PORT_CTRL_CFG_8814B 0x1501 +#define REG_TBTT_PROHIBIT_CFG_8814B 0x1504 +#define REG_DRVERLYINT_CFG_8814B 0x1507 +#define REG_BCNDMATIM_CFG_8814B 0x1508 +#define REG_CTWND_CFG_8814B 0x1509 +#define REG_BCNIVLCUNT_CFG_8814B 0x150A +#define REG_EARLY_128US_CFG_8814B 0x150B +#define REG_TSFTR_SYNC_OFFSET_CFG_8814B 0x150C +#define REG_TSFTR_SYNC_CTRL_CFG_8814B 0x150F +#define REG_BCN_SPACE_CFG_8814B 0x1510 +#define REG_EARLY_INT_ADJUST_CFG_8814B 0x1512 +#define REG_SW_TBTT_TSF_INFO_8814B 0x151C +#define REG_TSFTR_LOW_8814B 0x1520 +#define REG_TSFTR_HIGH_8814B 0x1524 +#define REG_BCN_ERR_CNT_MAC_8814B 0x1528 +#define REG_BCN_ERR_CNT_EDCCA_8814B 0x1529 +#define REG_BCN_ERR_CNT_CCA_8814B 0x152A +#define REG_BCN_ERR_CNT_INVALID_8814B 0x152B +#define REG_BCN_ERR_CNT_OTHERS_8814B 0x152C +#define REG_RX_BCN_TIMER_8814B 0x152D +#define REG_TBTT_CTN_AREA_V1_8814B 0x1530 +#define REG_BCN_MAX_ERR_V1_8814B 0x1531 +#define REG_RXTSF_OFFSET_CCK_V1_8814B 0x1532 +#define REG_RXTSF_OFFSET_OFDM_V1_8814B 0x1533 +#define REG_SUB_BCN_SPACE_8814B 0x1534 +#define REG_MBID_NUM_V1_8814B 0x1535 +#define REG_MBSSID_CTRL_V1_8814B 0x1536 +#define REG_USTIME_TSF_V1_8814B 0x1538 +#define REG_BW_CFG_8814B 0x1539 +#define REG_ATIMWND_CFG_8814B 0x153A +#define REG_DTIM_COUNTER_CFG_8814B 0x153B +#define REG_ATIM_DTIM_CTRL_SEL_8814B 0x153C +#define REG_ATIMUGT_V1_8814B 0x153D +#define REG_BCNDROPCTRL_V1_8814B 0x153E +#define REG_DIS_ATIM_V1_8814B 0x1540 +#define REG_HIQ_NO_LMT_EN_V1_8814B 0x1544 +#define REG_P2PPS_CTRL_V1_8814B 0x1548 +#define REG_P2PPS_SPEC_STATE_V1_8814B 0x154A +#define REG_P2PPS_STATE_V1_8814B 0x154B +#define REG_P2PPS1_CTRL_V1_8814B 0x154C +#define REG_P2PPS1_SPEC_STATE_V1_8814B 0x154E +#define REG_P2PPS1_STATE_V1_8814B 0x154F +#define REG_P2PPS2_CTRL_V1_8814B 0x1550 +#define REG_P2PPS2_SPEC_STATE_V1_8814B 0x1552 +#define REG_P2PPS2_STATE_V1_8814B 0x1553 +#define REG_P2PON_DIS_TXTIME_V1_8814B 0x1554 +#define REG_P2POFF_DIS_TXTIME_V1_8814B 0x1555 +#define REG_CHG_POWER_BCN_AREA_8814B 0x1556 +#define REG_NOA_SEL_8814B 0x1557 +#define REG_NOA_PARAM_V1_8814B 0x1558 +#define REG_NOA_PARAM_1_V1_8814B 0x155C +#define REG_NOA_PARAM_2_V1_8814B 0x1560 +#define REG_NOA_PARAM_3_V1_8814B 0x1564 +#define REG_NOA_ON_ERLY_TIME_V1_8814B 0x1568 +#define REG_NOA_OFF_ERLY_TIME_V1_8814B 0x1569 +#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8814B 0x156C +#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8814B 0x1570 +#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8814B 0x1574 +#define REG_RX_TBTT_SHIFT_8814B 0x1578 +#define REG_FREERUN_CNT_LOW_8814B 0x1580 +#define REG_FREERUN_CNT_HIGH_8814B 0x1584 +#define REG_CPUMGQ_TX_TIMER_V1_8814B 0x1588 +#define REG_PS_TIMER_0_8814B 0x158C +#define REG_PS_TIMER_1_8814B 0x1590 +#define REG_PS_TIMER_2_8814B 0x1594 +#define REG_PS_TIMER_3_8814B 0x1598 +#define REG_PS_TIMER_4_8814B 0x159C +#define REG_PS_TIMER_5_8814B 0x15A0 +#define REG_PS_TIMER_01_CTRL_8814B 0x15A4 +#define REG_PS_TIMER_23_CTRL_8814B 0x15A8 +#define REG_PS_TIMER_45_CTRL_8814B 0x15AC +#define REG_CPUMGQ_FREERUN_TIMER_CTRL_8814B 0x15B0 +#define REG_CPUMGQ_PROHIBIT_8814B 0x15B4 +#define REG_TIMER_COMPARE_8814B 0x15C0 +#define REG_TIMER_COMPARE_VALUE_LOW_8814B 0x15C4 +#define REG_TIMER_COMPARE_VALUE_HIGH_8814B 0x15C8 #define REG_WMAC_CR_8814B 0x0600 #define REG_WMAC_FWPKT_CR_8814B 0x0601 #define REG_FW_STS_FILTER_8814B 0x0602 -#define REG_BWOPMODE_8814B 0x0603 #define REG_TCR_8814B 0x0604 #define REG_RCR_8814B 0x0608 #define REG_RX_PKT_LIMIT_8814B 0x060C #define REG_RX_DLK_TIME_8814B 0x060D #define REG_RX_DRVINFO_SZ_8814B 0x060F #define REG_MACID_8814B 0x0610 +#define REG_MACID_H_8814B 0x0614 #define REG_BSSID_8814B 0x0618 +#define REG_BSSID_H_8814B 0x061C #define REG_MAR_8814B 0x0620 -#define REG_MBIDCAMCFG_1_8814B 0x0628 -#define REG_MBIDCAMCFG_2_8814B 0x062C +#define REG_MAR_H_8814B 0x0624 +#define REG_WMAC_DEBUG_SEL_8814B 0x062C #define REG_WMAC_TCR_TSFT_OFS_8814B 0x0630 #define REG_UDF_THSD_8814B 0x0632 #define REG_ZLD_NUM_8814B 0x0633 @@ -562,18 +826,20 @@ #define REG_CTS2TO_8814B 0x0641 #define REG_EIFS_8814B 0x0642 #define REG_RPFM_MAP0_8814B 0x0644 -#define REG_RPFM_MAP1_8814B 0x0646 +#define REG_RPFM_MAP1_V1_8814B 0x0646 #define REG_RPFM_CAM_CMD_8814B 0x0648 #define REG_RPFM_CAM_RWD_8814B 0x064C #define REG_NAV_CTRL_8814B 0x0650 #define REG_BACAMCMD_8814B 0x0654 #define REG_BACAMCONTENT_8814B 0x0658 +#define REG_BACAMCONTENT_H_8814B 0x065C #define REG_LBDLY_8814B 0x0660 #define REG_WMAC_BACAM_RPMEN_8814B 0x0661 #define REG_TX_RX_8814B 0x0662 #define REG_WMAC_BITMAP_CTL_8814B 0x0663 #define REG_RXERR_RPT_8814B 0x0664 #define REG_WMAC_TRXPTCL_CTL_8814B 0x0668 +#define REG_WMAC_TRXPTCL_CTL_H_8814B 0x066C #define REG_CAMCMD_8814B 0x0670 #define REG_CAMWRITE_8814B 0x0674 #define REG_CAMREAD_8814B 0x0678 @@ -598,7 +864,7 @@ #define REG_WKFMCAM_RWD_8814B 0x069C #define REG_RXFLTMAP0_8814B 0x06A0 #define REG_RXFLTMAP1_8814B 0x06A2 -#define REG_RXFLTMAP_8814B 0x06A4 +#define REG_RXFLTMAP2_8814B 0x06A4 #define REG_BCN_PSR_RPT_8814B 0x06A8 #define REG_FLC_RPC_8814B 0x06AC #define REG_FLC_RPCT_8814B 0x06AD @@ -609,34 +875,57 @@ #define REG_ERROR_MON_8814B 0x06B8 #define REG_SEARCH_MACID_8814B 0x06BC #define REG_BT_COEX_TABLE_8814B 0x06C0 +#define REG_BT_COEX_TABLE2_8814B 0x06C4 +#define REG_BT_COEX_BREAK_TABLE_8814B 0x06C8 +#define REG_BT_COEX_TABLE_H_8814B 0x06CC #define REG_RXCMD_0_8814B 0x06D0 #define REG_RXCMD_1_8814B 0x06D4 #define REG_WMAC_RESP_TXINFO_8814B 0x06D8 #define REG_BBPSF_CTRL_8814B 0x06DC #define REG_P2P_RX_BCN_NOA_8814B 0x06E0 #define REG_ASSOCIATED_BFMER0_INFO_8814B 0x06E4 +#define REG_ASSOCIATED_BFMER0_INFO_H_8814B 0x06E8 #define REG_ASSOCIATED_BFMER1_INFO_8814B 0x06EC +#define REG_ASSOCIATED_BFMER1_INFO_H_8814B 0x06F0 #define REG_TX_CSI_RPT_PARAM_BW20_8814B 0x06F4 #define REG_TX_CSI_RPT_PARAM_BW40_8814B 0x06F8 -#define REG_TX_CSI_RPT_PARAM_BW80_8814B 0x06FC #define REG_BCN_PSR_RPT2_8814B 0x1600 #define REG_BCN_PSR_RPT3_8814B 0x1604 #define REG_BCN_PSR_RPT4_8814B 0x1608 #define REG_A1_ADDR_MASK_8814B 0x160C +#define REG_RXPSF_CTRL_8814B 0x1610 +#define REG_RXPSF_TYPE_CTRL_8814B 0x1614 +#define REG_CAM_ACCESS_CTRL_8814B 0x1618 +#define REG_CUT_AMSDU_CTRL_8814B 0x161C #define REG_MACID2_8814B 0x1620 +#define REG_MACID2_H_8814B 0x1624 #define REG_BSSID2_8814B 0x1628 +#define REG_BSSID2_H_8814B 0x162C #define REG_MACID3_8814B 0x1630 +#define REG_MACID3_H_8814B 0x1634 #define REG_BSSID3_8814B 0x1638 +#define REG_BSSID3_H_8814B 0x163C #define REG_MACID4_8814B 0x1640 +#define REG_MACID4_H_8814B 0x1644 #define REG_BSSID4_8814B 0x1648 +#define REG_BSSID4_H_8814B 0x164C #define REG_NOA_REPORT_8814B 0x1650 +#define REG_NOA_REPORT_1_8814B 0x1654 +#define REG_NOA_REPORT_2_8814B 0x1658 +#define REG_NOA_REPORT_3_8814B 0x165C #define REG_PWRBIT_SETTING_8814B 0x1660 -#define REG_WMAC_MU_BF_OPTION_8814B 0x167C +#define REG_GENERAL_OPTION_8814B 0x1664 +#define REG_FWPHYFF_RCR_8814B 0x1668 +#define REG_ADDRCAM_WRITE_CONTENT_8814B 0x166C +#define REG_ADDRCAM_READ_CONTENT_8814B 0x1670 +#define REG_ADDRCAM_CFG_8814B 0x1674 +#define REG_CSI_RRSR_8814B 0x1678 +#define REG_MU_BF_OPTION_8814B 0x167C #define REG_WMAC_PAUSE_BB_CLR_TH_8814B 0x167D -#define REG_WMAC_MU_ARB_8814B 0x167E +#define REG_WMAC_MULBK_BUF_8814B 0x167E #define REG_WMAC_MU_OPTION_8814B 0x167F #define REG_WMAC_MU_BF_CTL_8814B 0x1680 -#define REG_WMAC_MU_BIT_BFRPT_PARA_8814B 0x1682 +#define REG_WMAC_MU_BFRPT_PARA_8814B 0x1682 #define REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B 0x1684 #define REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B 0x1686 #define REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B 0x1688 @@ -645,12 +934,17 @@ #define REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B 0x168E #define REG_WMAC_BB_STOP_RX_COUNTER_8814B 0x1690 #define REG_WMAC_PLCP_MONITOR_8814B 0x1694 -#define REG_WMAC_PLCP_MONITOR_MUTX_8814B 0x1698 +#define REG_WMAC_DEBUG_PORT_8814B 0x1698 #define REG_TRANSMIT_ADDRSS_0_8814B 0x16A0 +#define REG_TRANSMIT_ADDRSS_0_H_8814B 0x16A4 #define REG_TRANSMIT_ADDRSS_1_8814B 0x16A8 +#define REG_TRANSMIT_ADDRSS_1_H_8814B 0x16AC #define REG_TRANSMIT_ADDRSS_2_8814B 0x16B0 +#define REG_TRANSMIT_ADDRSS_2_H_8814B 0x16B4 #define REG_TRANSMIT_ADDRSS_3_8814B 0x16B8 +#define REG_TRANSMIT_ADDRSS_3_H_8814B 0x16BC #define REG_TRANSMIT_ADDRSS_4_8814B 0x16C0 +#define REG_TRANSMIT_ADDRSS_4_H_8814B 0x16C4 #define REG_MACID1_8814B 0x0700 #define REG_MACID1_1_8814B 0x0704 #define REG_BSSID1_8814B 0x0708 @@ -692,10 +986,10 @@ #define REG_LTR_CTRL2_TIMER_THRESHOLD_8814B 0x07A4 #define REG_LTR_IDLE_LATENCY_V1_8814B 0x07A8 #define REG_LTR_ACTIVE_LATENCY_V1_8814B 0x07AC -#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8814B 0x07B0 -#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8814B 0x07B4 -#define REG_WMAC_PKTCNT_RWD_8814B 0x07B8 -#define REG_WMAC_PKTCNT_CTRL_8814B 0x07BC +#define REG_SMART_ANT_CONDITION_8814B 0x07B0 +#define REG_SMART_ANT_CTRL_8814B 0x07B4 +#define REG_CONTROL_FRAME_REPORT_8814B 0x07B8 +#define REG_CONTROL_FRAME_CNT_CTRL_8814B 0x07BC #define REG_IQ_DUMP_8814B 0x07C0 #define REG_IQ_DUMP_1_8814B 0x07C4 #define REG_IQ_DUMP_2_8814B 0x07C8 @@ -716,6 +1010,20 @@ #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8814B 0x1700 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B 0x1704 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B 0x1708 +#define REG_PCIE_CFG_FORCE_LINK_L_8814B 0x0709 +#define REG_PCIE_CFG_FORCE_LINK_H_8814B 0x070A +#define REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0x070C +#define REG_PCIE_CFG_CX_NFTS_8814B 0x070D +#define REG_PCIE_CFG_DEFAULT_ENTR_LATENCY_8814B 0x070F +#define REG_PCIE_CFG_L1_MISC_SEL_8814B 0x0711 +#define REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF_8814B 0x0718 +#define REG_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B 0x0719 +#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY_8814B 0x071A +#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG_8814B 0x071B +#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0x071C +#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0x071D +#define REG_PCIE_CFG_L1_UNIT_SEL_8814B 0x0724 +#define REG_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0x0725 #define REG_SDIO_TX_CTRL_8814B 0x10250000 #define REG_SDIO_HIMR_8814B 0x10250014 #define REG_SDIO_HISR_8814B 0x10250018 @@ -739,10 +1047,9 @@ #define REG_SDIO_RESPONSE_TIMER_8814B 0x10250088 #define REG_SDIO_CMD_CRC_8814B 0x1025008A #define REG_SDIO_HSISR_8814B 0x10250090 -#define REG_SDIO_HSIMR_8814B 0x10250091 #define REG_SDIO_ERR_RPT_8814B 0x102500C0 -#define REG_SDIO_CMD_ERRCNT_8814B 0x102500C1 -#define REG_SDIO_DATA_ERRCNT_8814B 0x102500C2 +#define REG_SDIO_CMD_ERRCNT_8814B 0x102500C2 +#define REG_SDIO_DATA_ERRCNT_8814B 0x102500C3 #define REG_SDIO_CMD_ERR_CONTENT_8814B 0x102500C4 #define REG_SDIO_CRC_ERR_IDX_8814B 0x102500C9 #define REG_SDIO_DATA_CRC_8814B 0x102500CA diff --git a/hal/halmac/halmac_reg_8821c.h b/hal/halmac/halmac_reg_8821c.h index d7198fd..dd93baf 100644 --- a/hal/halmac/halmac_reg_8821c.h +++ b/hal/halmac/halmac_reg_8821c.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -84,7 +84,6 @@ #define REG_SYS_STATUS2_8821C 0x00F8 #define REG_SYS_CFG2_8821C 0x00FC #define REG_SYS_CFG3_8821C 0x1000 -#define REG_SYS_CFG4_8821C 0x1034 #define REG_SYS_CFG5_8821C 0x1070 #define REG_CPU_DMEM_CON_8821C 0x1080 #define REG_BOOT_REASON_8821C 0x1088 @@ -94,19 +93,13 @@ #define REG_HIMR3_8821C 0x10B8 #define REG_HISR3_8821C 0x10BC #define REG_SW_MDIO_8821C 0x10C0 -#define REG_SW_FLUSH_8821C 0x10C4 #define REG_H2C_PKT_READADDR_8821C 0x10D0 #define REG_H2C_PKT_WRITEADDR_8821C 0x10D4 #define REG_MEM_PWR_CRTL_8821C 0x10D8 -#define REG_FW_DBG0_8821C 0x10E0 -#define REG_FW_DBG1_8821C 0x10E4 -#define REG_FW_DBG2_8821C 0x10E8 -#define REG_FW_DBG3_8821C 0x10EC -#define REG_FW_DBG4_8821C 0x10F0 -#define REG_FW_DBG5_8821C 0x10F4 #define REG_FW_DBG6_8821C 0x10F8 #define REG_FW_DBG7_8821C 0x10FC #define REG_CR_8821C 0x0100 +#define REG_PG_SIZE_8821C 0x0104 #define REG_PKT_BUFF_ACCESS_CTRL_8821C 0x0106 #define REG_TSF_CLK_STATE_8821C 0x0108 #define REG_TXDMA_PQ_MAP_8821C 0x010C @@ -132,10 +125,10 @@ #define REG_TCUNIT_BASE_8821C 0x0164 #define REG_TC5_CTRL_8821C 0x0168 #define REG_TC6_CTRL_8821C 0x016C -#define REG_MBIST_FAIL_8821C 0x0170 +#define REG_MBIST_DRF_FAIL_8821C 0x0170 #define REG_MBIST_START_PAUSE_8821C 0x0174 #define REG_MBIST_DONE_8821C 0x0178 -#define REG_MBIST_FAIL_NRML_8821C 0x017C +#define REG_MBIST_READ_BIST_RPT_8821C 0x017C #define REG_AES_DECRPT_DATA_8821C 0x0180 #define REG_AES_DECRPT_CFG_8821C 0x0184 #define REG_TMETER_8821C 0x0190 @@ -155,8 +148,6 @@ #define REG_HMEBOX1_8821C 0x01D4 #define REG_HMEBOX2_8821C 0x01D8 #define REG_HMEBOX3_8821C 0x01DC -#define REG_LLT_INIT_8821C 0x01E0 -#define REG_LLT_INIT_ADDR_8821C 0x01E4 #define REG_BB_ACCESS_CTRL_8821C 0x01E8 #define REG_BB_ACCESS_DATA_8821C 0x01EC #define REG_HMEBOX_E0_8821C 0x01F0 @@ -182,6 +173,22 @@ #define REG_POWSEQ_8821C 0x1150 #define REG_TC7_CTRL_V1_8821C 0x1158 #define REG_TC8_CTRL_V1_8821C 0x115C +#define REG_RX_BCN_TBTT_ITVL0_8821C 0x1160 +#define REG_RX_BCN_TBTT_ITVL1_8821C 0x1164 +#define REG_IO_WRAP_ERR_FLAG_8821C 0x1170 +#define REG_SPEED_SENSOR_8821C 0x1180 +#define REG_SPEED_SENSOR1_8821C 0x1184 +#define REG_SPEED_SENSOR2_8821C 0x1188 +#define REG_SPEED_SENSOR3_8821C 0x118C +#define REG_SPEED_SENSOR4_8821C 0x1190 +#define REG_SPEED_SENSOR5_8821C 0x1194 +#define REG_COUNTER_CTRL_8821C 0x11C4 +#define REG_COUNTER_THRESHOLD_8821C 0x11C8 +#define REG_COUNTER_SET_8821C 0x11CC +#define REG_COUNTER_OVERFLOW_8821C 0x11D0 +#define REG_TXDMA_LEN_THRESHOLD_8821C 0x11D4 +#define REG_RXDMA_LEN_THRESHOLD_8821C 0x11D8 +#define REG_PCIE_EXEC_TIME_THRESHOLD_8821C 0x11DC #define REG_FT2IMR_8821C 0x11E0 #define REG_FT2ISR_8821C 0x11E4 #define REG_MSG2_8821C 0x11F0 @@ -327,10 +334,14 @@ #define REG_RETRY_LIMIT_8821C 0x042A #define REG_TXBF_CTRL_8821C 0x042C #define REG_DARFRC_8821C 0x0430 +#define REG_DARFRCH_8821C 0x0434 #define REG_RARFRC_8821C 0x0438 +#define REG_RARFRCH_8821C 0x043C #define REG_RRSR_8821C 0x0440 #define REG_ARFR0_8821C 0x0444 +#define REG_ARFRH0_8821C 0x0448 #define REG_ARFR1_V1_8821C 0x044C +#define REG_ARFRH1_V1_8821C 0x0450 #define REG_CCK_CHECK_8821C 0x0454 #define REG_AMPDU_MAX_TIME_V1_8821C 0x0455 #define REG_BCNQ1_BDNY_V1_8821C 0x0456 @@ -355,9 +366,13 @@ #define REG_MACID_SLEEP3_8821C 0x0484 #define REG_MACID_SLEEP1_8821C 0x0488 #define REG_ARFR2_V1_8821C 0x048C +#define REG_ARFRH2_V1_8821C 0x0490 #define REG_ARFR3_V1_8821C 0x0494 +#define REG_ARFRH3_V1_8821C 0x0498 #define REG_ARFR4_8821C 0x049C +#define REG_ARFRH4_8821C 0x04A0 #define REG_ARFR5_8821C 0x04A4 +#define REG_ARFRH5_8821C 0x04A8 #define REG_TXRPT_START_OFFSET_8821C 0x04AC #define REG_POWER_STAGE1_8821C 0x04B4 #define REG_POWER_STAGE2_8821C 0x04B8 @@ -380,6 +395,7 @@ #define REG_PTCL_ERR_STATUS_8821C 0x04E2 #define REG_NULL_PKT_STATUS_EXTEND_8821C 0x04E3 #define REG_VIDEO_ENHANCEMENT_FUN_8821C 0x04E4 +#define REG_PRECNT_CTRL_8821C 0x04E5 #define REG_BT_POLLUTE_PKT_CNT_8821C 0x04E8 #define REG_PTCL_DBG_8821C 0x04EC #define REG_CPUMGQ_TIMER_CTRL2_8821C 0x04F4 @@ -411,13 +427,24 @@ #define REG_R_MACID_RELEASE_SUCCESS_1_8821C 0x1464 #define REG_R_MACID_RELEASE_SUCCESS_2_8821C 0x1468 #define REG_R_MACID_RELEASE_SUCCESS_3_8821C 0x146C -#define REG_MGG_FIFO_CRTL_8821C 0x1470 -#define REG_MGG_FIFO_INT_8821C 0x1474 -#define REG_MGG_FIFO_LIFETIME_8821C 0x1478 +#define REG_MGQ_FIFO_WRITE_POINTER_8821C 0x1470 +#define REG_MGQ_FIFO_READ_POINTER_8821C 0x1472 +#define REG_MGQ_FIFO_ENABLE_8821C 0x1472 +#define REG_MGQ_FIFO_RELEASE_INT_MASK_8821C 0x1474 +#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8821C 0x1476 +#define REG_MGQ_FIFO_VALID_MAP_8821C 0x1478 +#define REG_MGQ_FIFO_LIFETIME_8821C 0x147A #define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x147C +#define REG_SHCUT_SETTING_8821C 0x1480 +#define REG_SHCUT_LLC_ETH_TYPE0_8821C 0x1484 +#define REG_SHCUT_LLC_ETH_TYPE1_8821C 0x1488 +#define REG_SHCUT_LLC_OUI0_8821C 0x148C +#define REG_SHCUT_LLC_OUI1_8821C 0x1490 +#define REG_SHCUT_LLC_OUI2_8821C 0x1494 #define REG_MU_TX_CTL_8821C 0x14C0 #define REG_MU_STA_GID_VLD_8821C 0x14C4 #define REG_MU_STA_USER_POS_INFO_8821C 0x14C8 +#define REG_MU_STA_USER_POS_INFO_H_8821C 0x14CC #define REG_MU_TRX_DBG_CNT_8821C 0x14D0 #define REG_EDCA_VO_PARAM_8821C 0x0500 #define REG_EDCA_VI_PARAM_8821C 0x0504 @@ -430,6 +457,8 @@ #define REG_TSFTR_SYN_OFFSET_8821C 0x0518 #define REG_AGGR_BREAK_TIME_8821C 0x051A #define REG_SLOT_8821C 0x051B +#define REG_NOA_ON_ERLY_TIME_8821C 0x051C +#define REG_NOA_OFF_ERLY_TIME_8821C 0x051D #define REG_TX_PTCL_CTRL_8821C 0x0520 #define REG_TXPAUSE_8821C 0x0522 #define REG_DIS_TXREQ_CLR_8821C 0x0523 @@ -439,6 +468,7 @@ #define REG_PKT_LIFETIME_CTRL_8821C 0x0528 #define REG_P2PPS_SPEC_STATE_8821C 0x052B #define REG_BAR_TX_CTRL_8821C 0x0530 +#define REG_P2PON_DIS_TXTIME_8821C 0x0531 #define REG_TBTT_PROHIBIT_8821C 0x0540 #define REG_P2PPS_STATE_8821C 0x0543 #define REG_RD_NAV_NXT_8821C 0x0544 @@ -533,18 +563,21 @@ #define REG_PS_TIMER_A_EARLY_8821C 0x1515 #define REG_PS_TIMER_B_EARLY_8821C 0x1516 #define REG_PS_TIMER_C_EARLY_8821C 0x1517 +#define REG_CPUMGQ_PARAMETER_8821C 0x1518 #define REG_WMAC_CR_8821C 0x0600 #define REG_WMAC_FWPKT_CR_8821C 0x0601 #define REG_FW_STS_FILTER_8821C 0x0602 -#define REG_BWOPMODE_8821C 0x0603 #define REG_TCR_8821C 0x0604 #define REG_RCR_8821C 0x0608 #define REG_RX_PKT_LIMIT_8821C 0x060C #define REG_RX_DLK_TIME_8821C 0x060D #define REG_RX_DRVINFO_SZ_8821C 0x060F #define REG_MACID_8821C 0x0610 +#define REG_MACID_H_8821C 0x0614 #define REG_BSSID_8821C 0x0618 +#define REG_BSSID_H_8821C 0x061C #define REG_MAR_8821C 0x0620 +#define REG_MAR_H_8821C 0x0624 #define REG_MBIDCAMCFG_1_8821C 0x0628 #define REG_MBIDCAMCFG_2_8821C 0x062C #define REG_WMAC_TCR_TSFT_OFS_8821C 0x0630 @@ -562,18 +595,20 @@ #define REG_CTS2TO_8821C 0x0641 #define REG_EIFS_8821C 0x0642 #define REG_RPFM_MAP0_8821C 0x0644 -#define REG_RPFM_MAP1_8821C 0x0646 +#define REG_RPFM_MAP1_V1_8821C 0x0646 #define REG_RPFM_CAM_CMD_8821C 0x0648 #define REG_RPFM_CAM_RWD_8821C 0x064C #define REG_NAV_CTRL_8821C 0x0650 #define REG_BACAMCMD_8821C 0x0654 #define REG_BACAMCONTENT_8821C 0x0658 +#define REG_BACAMCONTENT_H_8821C 0x065C #define REG_LBDLY_8821C 0x0660 #define REG_WMAC_BACAM_RPMEN_8821C 0x0661 #define REG_TX_RX_8821C 0x0662 #define REG_WMAC_BITMAP_CTL_8821C 0x0663 #define REG_RXERR_RPT_8821C 0x0664 #define REG_WMAC_TRXPTCL_CTL_8821C 0x0668 +#define REG_WMAC_TRXPTCL_CTL_H_8821C 0x066C #define REG_CAMCMD_8821C 0x0670 #define REG_CAMWRITE_8821C 0x0674 #define REG_CAMREAD_8821C 0x0678 @@ -598,7 +633,7 @@ #define REG_WKFMCAM_RWD_8821C 0x069C #define REG_RXFLTMAP0_8821C 0x06A0 #define REG_RXFLTMAP1_8821C 0x06A2 -#define REG_RXFLTMAP_8821C 0x06A4 +#define REG_RXFLTMAP2_8821C 0x06A4 #define REG_BCN_PSR_RPT_8821C 0x06A8 #define REG_FLC_RPC_8821C 0x06AC #define REG_FLC_RPCT_8821C 0x06AD @@ -609,34 +644,47 @@ #define REG_ERROR_MON_8821C 0x06B8 #define REG_SEARCH_MACID_8821C 0x06BC #define REG_BT_COEX_TABLE_8821C 0x06C0 +#define REG_BT_COEX_TABLE2_8821C 0x06C4 +#define REG_BT_COEX_BREAK_TABLE_8821C 0x06C8 +#define REG_BT_COEX_TABLE_H_8821C 0x06CC #define REG_RXCMD_0_8821C 0x06D0 #define REG_RXCMD_1_8821C 0x06D4 #define REG_WMAC_RESP_TXINFO_8821C 0x06D8 #define REG_BBPSF_CTRL_8821C 0x06DC #define REG_P2P_RX_BCN_NOA_8821C 0x06E0 #define REG_ASSOCIATED_BFMER0_INFO_8821C 0x06E4 +#define REG_ASSOCIATED_BFMER0_INFO_H_8821C 0x06E8 #define REG_ASSOCIATED_BFMER1_INFO_8821C 0x06EC +#define REG_ASSOCIATED_BFMER1_INFO_H_8821C 0x06F0 #define REG_TX_CSI_RPT_PARAM_BW20_8821C 0x06F4 #define REG_TX_CSI_RPT_PARAM_BW40_8821C 0x06F8 -#define REG_TX_CSI_RPT_PARAM_BW80_8821C 0x06FC #define REG_BCN_PSR_RPT2_8821C 0x1600 #define REG_BCN_PSR_RPT3_8821C 0x1604 #define REG_BCN_PSR_RPT4_8821C 0x1608 #define REG_A1_ADDR_MASK_8821C 0x160C #define REG_MACID2_8821C 0x1620 +#define REG_MACID2_H_8821C 0x1624 #define REG_BSSID2_8821C 0x1628 +#define REG_BSSID2_H_8821C 0x162C #define REG_MACID3_8821C 0x1630 +#define REG_MACID3_H_8821C 0x1634 #define REG_BSSID3_8821C 0x1638 +#define REG_BSSID3_H_8821C 0x163C #define REG_MACID4_8821C 0x1640 +#define REG_MACID4_H_8821C 0x1644 #define REG_BSSID4_8821C 0x1648 +#define REG_BSSID4_H_8821C 0x164C #define REG_NOA_REPORT_8821C 0x1650 +#define REG_NOA_REPORT_1_8821C 0x1654 +#define REG_NOA_REPORT_2_8821C 0x1658 +#define REG_NOA_REPORT_3_8821C 0x165C #define REG_PWRBIT_SETTING_8821C 0x1660 -#define REG_WMAC_MU_BF_OPTION_8821C 0x167C +#define REG_MU_BF_OPTION_8821C 0x167C #define REG_WMAC_PAUSE_BB_CLR_TH_8821C 0x167D #define REG_WMAC_MU_ARB_8821C 0x167E #define REG_WMAC_MU_OPTION_8821C 0x167F #define REG_WMAC_MU_BF_CTL_8821C 0x1680 -#define REG_WMAC_MU_BIT_BFRPT_PARA_8821C 0x1682 +#define REG_WMAC_MU_BFRPT_PARA_8821C 0x1682 #define REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C 0x1684 #define REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C 0x1686 #define REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C 0x1688 @@ -647,10 +695,15 @@ #define REG_WMAC_PLCP_MONITOR_8821C 0x1694 #define REG_WMAC_PLCP_MONITOR_MUTX_8821C 0x1698 #define REG_TRANSMIT_ADDRSS_0_8821C 0x16A0 +#define REG_TRANSMIT_ADDRSS_0_H_8821C 0x16A4 #define REG_TRANSMIT_ADDRSS_1_8821C 0x16A8 +#define REG_TRANSMIT_ADDRSS_1_H_8821C 0x16AC #define REG_TRANSMIT_ADDRSS_2_8821C 0x16B0 +#define REG_TRANSMIT_ADDRSS_2_H_8821C 0x16B4 #define REG_TRANSMIT_ADDRSS_3_8821C 0x16B8 +#define REG_TRANSMIT_ADDRSS_3_H_8821C 0x16BC #define REG_TRANSMIT_ADDRSS_4_8821C 0x16C0 +#define REG_TRANSMIT_ADDRSS_4_H_8821C 0x16C4 #define REG_MACID1_8821C 0x0700 #define REG_MACID1_1_8821C 0x0704 #define REG_BSSID1_8821C 0x0708 @@ -739,10 +792,9 @@ #define REG_SDIO_RESPONSE_TIMER_8821C 0x10250088 #define REG_SDIO_CMD_CRC_8821C 0x1025008A #define REG_SDIO_HSISR_8821C 0x10250090 -#define REG_SDIO_HSIMR_8821C 0x10250091 #define REG_SDIO_ERR_RPT_8821C 0x102500C0 -#define REG_SDIO_CMD_ERRCNT_8821C 0x102500C1 -#define REG_SDIO_DATA_ERRCNT_8821C 0x102500C2 +#define REG_SDIO_CMD_ERRCNT_8821C 0x102500C2 +#define REG_SDIO_DATA_ERRCNT_8821C 0x102500C3 #define REG_SDIO_CMD_ERR_CONTENT_8821C 0x102500C4 #define REG_SDIO_CRC_ERR_IDX_8821C 0x102500C9 #define REG_SDIO_DATA_CRC_8821C 0x102500CA diff --git a/hal/halmac/halmac_reg_8822b.h b/hal/halmac/halmac_reg_8822b.h index b2913c3..e06f67e 100644 --- a/hal/halmac/halmac_reg_8822b.h +++ b/hal/halmac/halmac_reg_8822b.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -107,7 +107,6 @@ #define REG_FW_DBG6_8822B 0x10F8 #define REG_FW_DBG7_8822B 0x10FC #define REG_CR_8822B 0x0100 -#define REG_PKT_BUFF_ACCESS_CTRL_8822B 0x0106 #define REG_TSF_CLK_STATE_8822B 0x0108 #define REG_TXDMA_PQ_MAP_8822B 0x010C #define REG_TRXFF_BNDY_8822B 0x0114 @@ -142,6 +141,9 @@ #define REG_OSC_32K_CTRL_8822B 0x0194 #define REG_32K_CAL_REG1_8822B 0x0198 #define REG_C2HEVT_8822B 0x01A0 +#define REG_C2HEVT_1_8822B 0x01A4 +#define REG_C2HEVT_2_8822B 0x01A8 +#define REG_C2HEVT_3_8822B 0x01AC #define REG_SW_DEFINED_PAGE1_8822B 0x01B8 #define REG_MCUTST_I_8822B 0x01C0 #define REG_MCUTST_II_8822B 0x01C4 @@ -413,10 +415,20 @@ #define REG_MGG_FIFO_INT_8822B 0x1474 #define REG_MGG_FIFO_LIFETIME_8822B 0x1478 #define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x147C -#define REG_MACID_SHCUT_OFFSET_8822B 0x1480 +#define REG_SHCUT_SETTING_8822B 0x1480 +#define REG_SHCUT_LLC_ETH_TYPE0_8822B 0x1484 +#define REG_SHCUT_LLC_ETH_TYPE1_8822B 0x1488 +#define REG_SHCUT_LLC_OUI0_8822B 0x148C +#define REG_SHCUT_LLC_OUI1_8822B 0x1490 +#define REG_SHCUT_LLC_OUI2_8822B 0x1494 +#define REG_SHCUT_LLC_OUI3_8822B 0x1498 #define REG_MU_TX_CTL_8822B 0x14C0 +#define REG_MU_TX_CTL_8822B 0x14C0 +#define REG_MU_STA_GID_VLD_8822B 0x14C4 #define REG_MU_STA_GID_VLD_8822B 0x14C4 #define REG_MU_STA_USER_POS_INFO_8822B 0x14C8 +#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8 +#define REG_MU_TRX_DBG_CNT_8822B 0x14D0 #define REG_MU_TRX_DBG_CNT_8822B 0x14D0 #define REG_EDCA_VO_PARAM_8822B 0x0500 #define REG_EDCA_VI_PARAM_8822B 0x0504 @@ -437,7 +449,9 @@ #define REG_P2PPS_CTRL_8822B 0x0527 #define REG_PKT_LIFETIME_CTRL_8822B 0x0528 #define REG_P2PPS_SPEC_STATE_8822B 0x052B +#define REG_TXOP_LIMIT_CTRL_8822B 0x052C #define REG_BAR_TX_CTRL_8822B 0x0530 +#define REG_P2PON_DIS_TXTIME_8822B 0x0531 #define REG_QUEUE_INCOL_THR_8822B 0x0538 #define REG_QUEUE_INCOL_EN_8822B 0x053C #define REG_TBTT_PROHIBIT_8822B 0x0540 @@ -529,6 +543,7 @@ #define REG_PS_TIMER_A_EARLY_8822B 0x1515 #define REG_PS_TIMER_B_EARLY_8822B 0x1516 #define REG_PS_TIMER_C_EARLY_8822B 0x1517 +#define REG_CPUMGQ_PARAMETER_8822B 0x1518 #define REG_WMAC_CR_8822B 0x0600 #define REG_WMAC_FWPKT_CR_8822B 0x0601 #define REG_BWOPMODE_8822B 0x0603 @@ -588,7 +603,7 @@ #define REG_WKFMCAM_RWD_8822B 0x069C #define REG_RXFLTMAP0_8822B 0x06A0 #define REG_RXFLTMAP1_8822B 0x06A2 -#define REG_RXFLTMAP_8822B 0x06A4 +#define REG_RXFLTMAP2_8822B 0x06A4 #define REG_BCN_PSR_RPT_8822B 0x06A8 #define REG_FLC_RPC_8822B 0x06AC #define REG_FLC_RPCT_8822B 0x06AD @@ -707,10 +722,9 @@ #define REG_SDIO_RESPONSE_TIMER_8822B 0x10250088 #define REG_SDIO_CMD_CRC_8822B 0x1025008A #define REG_SDIO_HSISR_8822B 0x10250090 -#define REG_SDIO_HSIMR_8822B 0x10250091 #define REG_SDIO_ERR_RPT_8822B 0x102500C0 -#define REG_SDIO_CMD_ERRCNT_8822B 0x102500C1 -#define REG_SDIO_DATA_ERRCNT_8822B 0x102500C2 +#define REG_SDIO_CMD_ERRCNT_8822B 0x102500C2 +#define REG_SDIO_DATA_ERRCNT_8822B 0x102500C3 #define REG_SDIO_CMD_ERR_CONTENT_8822B 0x102500C4 #define REG_SDIO_CRC_ERR_IDX_8822B 0x102500C9 #define REG_SDIO_DATA_CRC_8822B 0x102500CA diff --git a/hal/halmac/halmac_rx_bd_ap.h b/hal/halmac/halmac_rx_bd_ap.h deleted file mode 100644 index 6da7e4b..0000000 --- a/hal/halmac/halmac_rx_bd_ap.h +++ /dev/null @@ -1,40 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_RX_BD_AP_H_ -#define _HALMAC_RX_BD_AP_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) - -/*TXBD_DW0*/ - -#define GET_RX_BD_RXFAIL(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1, 31) -#define GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1fff, 16) -#define GET_RX_BD_RXTAG(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1fff, 16) -#define GET_RX_BD_FS(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1, 15) -#define GET_RX_BD_LS(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1, 14) -#define GET_RX_BD_RXBUFFSIZE(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x3fff, 0) - -/*TXBD_DW1*/ - -#define GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword1, 0xffffffff, 0) - -/*TXBD_DW2*/ - -#define GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword2, 0xffffffff, 0) - -#endif - - -#endif diff --git a/hal/halmac/halmac_rx_bd_chip.h b/hal/halmac/halmac_rx_bd_chip.h deleted file mode 100644 index 5270e07..0000000 --- a/hal/halmac/halmac_rx_bd_chip.h +++ /dev/null @@ -1,124 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_RX_BD_CHIP_H_ -#define _HALMAC_RX_BD_CHIP_H_ -#if (HALMAC_8814A_SUPPORT) - -/*TXBD_DW0*/ - -#define GET_RX_BD_RXFAIL_8814A(__pRxBd) GET_RX_BD_RXFAIL(__pRxBd) -#define GET_RX_BD_TOTALRXPKTSIZE_8814A(__pRxBd) GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) -#define GET_RX_BD_RXTAG_8814A(__pRxBd) GET_RX_BD_RXTAG(__pRxBd) -#define GET_RX_BD_FS_8814A(__pRxBd) GET_RX_BD_FS(__pRxBd) -#define GET_RX_BD_LS_8814A(__pRxBd) GET_RX_BD_LS(__pRxBd) -#define GET_RX_BD_RXBUFFSIZE_8814A(__pRxBd) GET_RX_BD_RXBUFFSIZE(__pRxBd) - -/*TXBD_DW1*/ - -#define GET_RX_BD_PHYSICAL_ADDR_LOW_8814A(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) - -/*TXBD_DW2*/ - -#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8814A(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) - -#endif - -#if (HALMAC_8822B_SUPPORT) - -/*TXBD_DW0*/ - -#define GET_RX_BD_RXFAIL_8822B(__pRxBd) GET_RX_BD_RXFAIL(__pRxBd) -#define GET_RX_BD_TOTALRXPKTSIZE_8822B(__pRxBd) GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) -#define GET_RX_BD_RXTAG_8822B(__pRxBd) GET_RX_BD_RXTAG(__pRxBd) -#define GET_RX_BD_FS_8822B(__pRxBd) GET_RX_BD_FS(__pRxBd) -#define GET_RX_BD_LS_8822B(__pRxBd) GET_RX_BD_LS(__pRxBd) -#define GET_RX_BD_RXBUFFSIZE_8822B(__pRxBd) GET_RX_BD_RXBUFFSIZE(__pRxBd) - -/*TXBD_DW1*/ - -#define GET_RX_BD_PHYSICAL_ADDR_LOW_8822B(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) - -/*TXBD_DW2*/ - -#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8822B(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) - -#endif - -#if (HALMAC_8197F_SUPPORT) - -/*TXBD_DW0*/ - -#define GET_RX_BD_RXFAIL_8197F(__pRxBd) GET_RX_BD_RXFAIL(__pRxBd) -#define GET_RX_BD_TOTALRXPKTSIZE_8197F(__pRxBd) GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) -#define GET_RX_BD_RXTAG_8197F(__pRxBd) GET_RX_BD_RXTAG(__pRxBd) -#define GET_RX_BD_FS_8197F(__pRxBd) GET_RX_BD_FS(__pRxBd) -#define GET_RX_BD_LS_8197F(__pRxBd) GET_RX_BD_LS(__pRxBd) -#define GET_RX_BD_RXBUFFSIZE_8197F(__pRxBd) GET_RX_BD_RXBUFFSIZE(__pRxBd) - -/*TXBD_DW1*/ - -#define GET_RX_BD_PHYSICAL_ADDR_LOW_8197F(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) - -/*TXBD_DW2*/ - -#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8197F(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) - -#endif - -#if (HALMAC_8821C_SUPPORT) - -/*TXBD_DW0*/ - -#define GET_RX_BD_RXFAIL_8821C(__pRxBd) GET_RX_BD_RXFAIL(__pRxBd) -#define GET_RX_BD_TOTALRXPKTSIZE_8821C(__pRxBd) GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) -#define GET_RX_BD_RXTAG_8821C(__pRxBd) GET_RX_BD_RXTAG(__pRxBd) -#define GET_RX_BD_FS_8821C(__pRxBd) GET_RX_BD_FS(__pRxBd) -#define GET_RX_BD_LS_8821C(__pRxBd) GET_RX_BD_LS(__pRxBd) -#define GET_RX_BD_RXBUFFSIZE_8821C(__pRxBd) GET_RX_BD_RXBUFFSIZE(__pRxBd) - -/*TXBD_DW1*/ - -#define GET_RX_BD_PHYSICAL_ADDR_LOW_8821C(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) - -/*TXBD_DW2*/ - -#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8821C(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) - -#endif - -#if (HALMAC_8188F_SUPPORT) - -/*TXBD_DW0*/ - -#define GET_RX_BD_RXFAIL_8188F(__pRxBd) GET_RX_BD_RXFAIL(__pRxBd) -#define GET_RX_BD_TOTALRXPKTSIZE_8188F(__pRxBd) GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) -#define GET_RX_BD_RXTAG_8188F(__pRxBd) GET_RX_BD_RXTAG(__pRxBd) -#define GET_RX_BD_FS_8188F(__pRxBd) GET_RX_BD_FS(__pRxBd) -#define GET_RX_BD_LS_8188F(__pRxBd) GET_RX_BD_LS(__pRxBd) -#define GET_RX_BD_RXBUFFSIZE_8188F(__pRxBd) GET_RX_BD_RXBUFFSIZE(__pRxBd) - -/*TXBD_DW1*/ - -#define GET_RX_BD_PHYSICAL_ADDR_LOW_8188F(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) - -/*TXBD_DW2*/ - -#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8188F(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) - -#endif - - -#endif diff --git a/hal/halmac/halmac_rx_bd_nic.h b/hal/halmac/halmac_rx_bd_nic.h index 73ce816..dae936a 100644 --- a/hal/halmac/halmac_rx_bd_nic.h +++ b/hal/halmac/halmac_rx_bd_nic.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,26 +15,26 @@ #ifndef _HALMAC_RX_BD_NIC_H_ #define _HALMAC_RX_BD_NIC_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /*TXBD_DW0*/ -#define GET_RX_BD_RXFAIL(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 31, 1) -#define GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 16, 13) -#define GET_RX_BD_RXTAG(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 16, 13) -#define GET_RX_BD_FS(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 15, 1) -#define GET_RX_BD_LS(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 14, 1) -#define GET_RX_BD_RXBUFFSIZE(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 0, 14) +#define GET_RX_BD_RXFAIL(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 31, 1) +#define GET_RX_BD_TOTALRXPKTSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13) +#define GET_RX_BD_RXTAG(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13) +#define GET_RX_BD_FS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 15, 1) +#define GET_RX_BD_LS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 14, 1) +#define GET_RX_BD_RXBUFFSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 0, 14) /*TXBD_DW1*/ -#define GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x04, 0, 32) +#define GET_RX_BD_PHYSICAL_ADDR_LOW(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x04, 0, 32) /*TXBD_DW2*/ -#define GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x08, 0, 32) +#define GET_RX_BD_PHYSICAL_ADDR_HIGH(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x08, 0, 32) #endif - #endif diff --git a/hal/halmac/halmac_rx_desc_ap.h b/hal/halmac/halmac_rx_desc_ap.h index 556a67c..1ba6b92 100644 --- a/hal/halmac/halmac_rx_desc_ap.h +++ b/hal/halmac/halmac_rx_desc_ap.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,133 +15,600 @@ #ifndef _HALMAC_RX_DESC_AP_H_ #define _HALMAC_RX_DESC_AP_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 30) -#define GET_RX_DESC_PHYPKTIDC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 28) -#define GET_RX_DESC_SWDEC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 27) -#define GET_RX_DESC_PHYST(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 26) -#define GET_RX_DESC_SHIFT(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x3, 24) -#define GET_RX_DESC_QOS(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 23) -#define GET_RX_DESC_SECURITY(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x7, 20) -#define GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0xf, 16) -#define GET_RX_DESC_ICV_ERR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 15) -#define GET_RX_DESC_CRC32(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 14) -#define GET_RX_DESC_PKT_LEN(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x3fff, 0) +#define GET_RX_DESC_EOR(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 30) +#define GET_RX_DESC_PHYPKTIDC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 28) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_EVT_PKT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 28) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_SWDEC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 27) +#define GET_RX_DESC_PHYST(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 26) +#define GET_RX_DESC_SHIFT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x3, \ + 24) +#define GET_RX_DESC_QOS(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 23) +#define GET_RX_DESC_SECURITY(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x7, \ + 20) +#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0xf, \ + 16) +#define GET_RX_DESC_ICV_ERR(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 15) +#define GET_RX_DESC_CRC32(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 14) +#define GET_RX_DESC_PKT_LEN(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, \ + 0x3fff, 0) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 31) -#define GET_RX_DESC_MC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 30) -#define GET_RX_DESC_TY_PE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x3, 28) -#define GET_RX_DESC_MF(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 27) -#define GET_RX_DESC_MD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 26) -#define GET_RX_DESC_PWR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 25) -#define GET_RX_DESC_PAM(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 24) -#define GET_RX_DESC_CHK_VLD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 23) -#define GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 22) -#define GET_RX_DESC_RX_IPV(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 21) -#define GET_RX_DESC_CHKERR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 20) -#define GET_RX_DESC_PAGGR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 15) -#define GET_RX_DESC_RXID_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 14) -#define GET_RX_DESC_AMSDU(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 13) -#define GET_RX_DESC_MACID_VLD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 12) -#define GET_RX_DESC_TID(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0xf, 8) +#define GET_RX_DESC_BC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 31) +#define GET_RX_DESC_MC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 30) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_TY_PE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3, \ + 28) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_TYPE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3, \ + 28) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_MF(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 27) +#define GET_RX_DESC_MD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 26) +#define GET_RX_DESC_PWR(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 25) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_PAM(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 24) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_A1_MATCH(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 24) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_CHK_VLD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 23) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 23) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 22) +#define GET_RX_DESC_RX_IPV(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 21) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_CHKERR(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 20) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 20) +#define GET_RX_DESC_PHY_PKT_IDC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 17) +#define GET_RX_DESC_FW_FIFO_FULL(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 16) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define GET_RX_DESC_EXT_SECTYPE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 7) +#define GET_RX_DESC_PAGGR(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 15) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define GET_RX_DESC_MACID(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x7f, 0) +#define GET_RX_DESC_AMPDU(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 15) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_RXID_MATCH(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 14) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_RXCMD_IDC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 14) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_AMSDU(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 13) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_MACID_VLD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 12) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_TID(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0xf, 8) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_MACID(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x7f, \ + 0) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 31) +#define GET_RX_DESC_FCS_OK(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 31) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define GET_RX_DESC_PPDU_CNT(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x3, 29) +#define GET_RX_DESC_AMSDU_CUT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 31) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_PPDU_CNT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3, \ + 29) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_C2H(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 28) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_HWRSVD_V1(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x7, \ + 25) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_HWRSVD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf, \ + 24) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_RXMAGPKT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 24) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3f, \ + 18) + +#endif -#define GET_RX_DESC_C2H(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 28) -#define GET_RX_DESC_HWRSVD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xf, 24) -#define GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x3f, 18) -#define GET_RX_DESC_RX_IS_QOS(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 16) -#define GET_RX_DESC_FRAG(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xf, 12) -#define GET_RX_DESC_SEQ(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xfff, 0) +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_LAST_MSDU(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 17) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_RX_STATISTICS(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 17) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_RX_IS_QOS(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 16) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_EXT_SEC_TYPE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 16) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_FRAG(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf, \ + 12) +#define GET_RX_DESC_SEQ(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, \ + 0xfff, 0) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 31) -#define GET_RX_DESC_UNICAST_WAKE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 30) -#define GET_RX_DESC_PATTERN_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 29) +#define GET_RX_DESC_MAGIC_WAKE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 31) +#define GET_RX_DESC_UNICAST_WAKE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 30) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_PATTERN_MATCH(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 29) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 28) -#define GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0xf, 24) +#define GET_RX_DESC_PATTERN_WAKE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 29) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0xff, 16) -#define GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x3, 12) -#define GET_RX_DESC_EOSP(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 11) -#define GET_RX_DESC_HTC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 10) +#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 28) +#define GET_RX_DESC_RXPAYLOAD_ID(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xf, \ + 24) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x7, 7) +#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xff, \ + 16) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x3, \ + 12) +#define GET_RX_DESC_EOSP(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 11) + +#endif -#define GET_RX_DESC_RX_RATE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x7f, 0) +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_BSSID_FIT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1f, \ + 11) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_HTC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 10) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_AMPDU_END_PKT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 9) +#define GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 8) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7, 7) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_EOSP_V1(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 7) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_RX_RATE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7f, \ + 0) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x1f, 24) +#define GET_RX_DESC_A1_FIT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \ + 24) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_ADDRESS_CAM(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \ + 24) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_A1_FIT_A1(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \ + 24) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_MACID_VLD_V1(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \ + 23) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \ + 17) +#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \ + 16) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_MACID_V1(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \ + 15) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \ + 9) +#define GET_RX_DESC_RX_EOF(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_FC_POWER(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 7) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x7f, 17) -#define GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x1, 16) -#define GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x7f, 9) -#define GET_RX_DESC_RX_EOF(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x1, 8) +#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 6) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT) -#define GET_RX_DESC_PATTERN_IDX(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0xff, 0) +#define GET_RX_DESC_SWPS_RPT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 5) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_PATTERN_IDX(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \ + 0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_PATTERN_IDX_V1(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \ + 0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_PATTERN_IDX_V2(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \ + 0) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword5, 0xffffffff, 0) +#define GET_RX_DESC_TSFL(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword5, \ + 0xffffffff, 0) #endif +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_FREERUN_CNT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword5, \ + 0xffffffff, 0) #endif +#endif diff --git a/hal/halmac/halmac_rx_desc_chip.h b/hal/halmac/halmac_rx_desc_chip.h index b2dfdf5..ac36d0a 100644 --- a/hal/halmac/halmac_rx_desc_chip.h +++ b/hal/halmac/halmac_rx_desc_chip.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -19,73 +19,80 @@ /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR_8814A(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc) -#define GET_RX_DESC_PHYPKTIDC_8814A(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc) -#define GET_RX_DESC_SWDEC_8814A(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc) -#define GET_RX_DESC_PHYST_8814A(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc) -#define GET_RX_DESC_SHIFT_8814A(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc) -#define GET_RX_DESC_QOS_8814A(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc) -#define GET_RX_DESC_SECURITY_8814A(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc) -#define GET_RX_DESC_DRV_INFO_SIZE_8814A(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) -#define GET_RX_DESC_ICV_ERR_8814A(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc) -#define GET_RX_DESC_CRC32_8814A(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc) -#define GET_RX_DESC_PKT_LEN_8814A(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc) +#define GET_RX_DESC_EOR_8814A(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8814A(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8814A(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8814A(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8814A(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8814A(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8814A(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8814A(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8814A(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8814A(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8814A(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC_8814A(__pRxDesc) GET_RX_DESC_BC(__pRxDesc) -#define GET_RX_DESC_MC_8814A(__pRxDesc) GET_RX_DESC_MC(__pRxDesc) -#define GET_RX_DESC_TY_PE_8814A(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc) -#define GET_RX_DESC_MF_8814A(__pRxDesc) GET_RX_DESC_MF(__pRxDesc) -#define GET_RX_DESC_MD_8814A(__pRxDesc) GET_RX_DESC_MD(__pRxDesc) -#define GET_RX_DESC_PWR_8814A(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc) -#define GET_RX_DESC_PAM_8814A(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc) -#define GET_RX_DESC_CHK_VLD_8814A(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc) -#define GET_RX_DESC_RX_IS_TCP_UDP_8814A(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) -#define GET_RX_DESC_RX_IPV_8814A(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc) -#define GET_RX_DESC_CHKERR_8814A(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc) -#define GET_RX_DESC_PAGGR_8814A(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc) -#define GET_RX_DESC_RXID_MATCH_8814A(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc) -#define GET_RX_DESC_AMSDU_8814A(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc) -#define GET_RX_DESC_MACID_VLD_8814A(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc) -#define GET_RX_DESC_TID_8814A(__pRxDesc) GET_RX_DESC_TID(__pRxDesc) -#define GET_RX_DESC_EXT_SECTYPE_8814A(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc) -#define GET_RX_DESC_MACID_8814A(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc) +#define GET_RX_DESC_BC_8814A(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8814A(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8814A(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8814A(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8814A(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8814A(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8814A(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8814A(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8814A(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8814A(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8814A(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8814A(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8814A(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8814A(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8814A(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8814A(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8814A(rxdesc) GET_RX_DESC_MACID(rxdesc) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK_8814A(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) -#define GET_RX_DESC_C2H_8814A(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) -#define GET_RX_DESC_HWRSVD_8814A(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) -#define GET_RX_DESC_WLANHD_IV_LEN_8814A(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) -#define GET_RX_DESC_RX_IS_QOS_8814A(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc) -#define GET_RX_DESC_FRAG_8814A(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc) -#define GET_RX_DESC_SEQ_8814A(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc) +#define GET_RX_DESC_FCS_OK_8814A(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_C2H_8814A(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8814A(rxdesc) GET_RX_DESC_HWRSVD(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8814A(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8814A(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8814A(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8814A(rxdesc) GET_RX_DESC_SEQ(rxdesc) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE_8814A(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) -#define GET_RX_DESC_UNICAST_WAKE_8814A(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) -#define GET_RX_DESC_PATTERN_MATCH_8814A(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) -#define GET_RX_DESC_DMA_AGG_NUM_8814A(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_1_0_8814A(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) -#define GET_RX_DESC_EOSP_8814A(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) -#define GET_RX_DESC_HTC_8814A(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_4_2_8814A(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) -#define GET_RX_DESC_RX_RATE_8814A(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc) +#define GET_RX_DESC_MAGIC_WAKE_8814A(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8814A(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8814A(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8814A(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8814A(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8814A(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8814A(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8814A(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8814A(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT_8814A(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc) -#define GET_RX_DESC_MACID_RPT_BUFF_8814A(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) -#define GET_RX_DESC_RX_PRE_NDP_VLD_8814A(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) -#define GET_RX_DESC_RX_SCRAMBLER_8814A(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) -#define GET_RX_DESC_RX_EOF_8814A(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc) -#define GET_RX_DESC_PATTERN_IDX_8814A(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc) +#define GET_RX_DESC_A1_FIT_8814A(rxdesc) GET_RX_DESC_A1_FIT(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8814A(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8814A(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8814A(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8814A(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8814A(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL_8814A(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc) +#define GET_RX_DESC_TSFL_8814A(rxdesc) GET_RX_DESC_TSFL(rxdesc) #endif @@ -93,76 +100,84 @@ /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR_8822B(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc) -#define GET_RX_DESC_PHYPKTIDC_8822B(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc) -#define GET_RX_DESC_SWDEC_8822B(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc) -#define GET_RX_DESC_PHYST_8822B(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc) -#define GET_RX_DESC_SHIFT_8822B(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc) -#define GET_RX_DESC_QOS_8822B(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc) -#define GET_RX_DESC_SECURITY_8822B(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc) -#define GET_RX_DESC_DRV_INFO_SIZE_8822B(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) -#define GET_RX_DESC_ICV_ERR_8822B(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc) -#define GET_RX_DESC_CRC32_8822B(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc) -#define GET_RX_DESC_PKT_LEN_8822B(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc) +#define GET_RX_DESC_EOR_8822B(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8822B(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8822B(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8822B(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8822B(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8822B(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8822B(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8822B(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8822B(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8822B(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8822B(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC_8822B(__pRxDesc) GET_RX_DESC_BC(__pRxDesc) -#define GET_RX_DESC_MC_8822B(__pRxDesc) GET_RX_DESC_MC(__pRxDesc) -#define GET_RX_DESC_TY_PE_8822B(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc) -#define GET_RX_DESC_MF_8822B(__pRxDesc) GET_RX_DESC_MF(__pRxDesc) -#define GET_RX_DESC_MD_8822B(__pRxDesc) GET_RX_DESC_MD(__pRxDesc) -#define GET_RX_DESC_PWR_8822B(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc) -#define GET_RX_DESC_PAM_8822B(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc) -#define GET_RX_DESC_CHK_VLD_8822B(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc) -#define GET_RX_DESC_RX_IS_TCP_UDP_8822B(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) -#define GET_RX_DESC_RX_IPV_8822B(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc) -#define GET_RX_DESC_CHKERR_8822B(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc) -#define GET_RX_DESC_PAGGR_8822B(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc) -#define GET_RX_DESC_RXID_MATCH_8822B(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc) -#define GET_RX_DESC_AMSDU_8822B(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc) -#define GET_RX_DESC_MACID_VLD_8822B(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc) -#define GET_RX_DESC_TID_8822B(__pRxDesc) GET_RX_DESC_TID(__pRxDesc) -#define GET_RX_DESC_EXT_SECTYPE_8822B(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc) -#define GET_RX_DESC_MACID_8822B(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc) +#define GET_RX_DESC_BC_8822B(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8822B(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8822B(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8822B(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8822B(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8822B(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8822B(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8822B(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8822B(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8822B(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8822B(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8822B(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8822B(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8822B(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8822B(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8822B(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8822B(rxdesc) GET_RX_DESC_MACID(rxdesc) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK_8822B(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) -#define GET_RX_DESC_PPDU_CNT_8822B(__pRxDesc) GET_RX_DESC_PPDU_CNT(__pRxDesc) -#define GET_RX_DESC_C2H_8822B(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) -#define GET_RX_DESC_HWRSVD_8822B(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) -#define GET_RX_DESC_WLANHD_IV_LEN_8822B(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) -#define GET_RX_DESC_RX_IS_QOS_8822B(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc) -#define GET_RX_DESC_FRAG_8822B(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc) -#define GET_RX_DESC_SEQ_8822B(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc) +#define GET_RX_DESC_FCS_OK_8822B(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_PPDU_CNT_8822B(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc) +#define GET_RX_DESC_C2H_8822B(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8822B(rxdesc) GET_RX_DESC_HWRSVD(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8822B(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8822B(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8822B(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8822B(rxdesc) GET_RX_DESC_SEQ(rxdesc) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE_8822B(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) -#define GET_RX_DESC_UNICAST_WAKE_8822B(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) -#define GET_RX_DESC_PATTERN_MATCH_8822B(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) -#define GET_RX_DESC_RXPAYLOAD_MATCH_8822B(__pRxDesc) GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) -#define GET_RX_DESC_RXPAYLOAD_ID_8822B(__pRxDesc) GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) -#define GET_RX_DESC_DMA_AGG_NUM_8822B(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_1_0_8822B(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) -#define GET_RX_DESC_EOSP_8822B(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) -#define GET_RX_DESC_HTC_8822B(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_4_2_8822B(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) -#define GET_RX_DESC_RX_RATE_8822B(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc) +#define GET_RX_DESC_MAGIC_WAKE_8822B(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8822B(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8822B(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8822B(rxdesc) \ + GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8822B(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8822B(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8822B(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8822B(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8822B(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8822B(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8822B(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT_8822B(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc) -#define GET_RX_DESC_MACID_RPT_BUFF_8822B(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) -#define GET_RX_DESC_RX_PRE_NDP_VLD_8822B(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) -#define GET_RX_DESC_RX_SCRAMBLER_8822B(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) -#define GET_RX_DESC_RX_EOF_8822B(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc) -#define GET_RX_DESC_PATTERN_IDX_8822B(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc) +#define GET_RX_DESC_A1_FIT_8822B(rxdesc) GET_RX_DESC_A1_FIT(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8822B(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8822B(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8822B(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8822B(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8822B(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL_8822B(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc) +#define GET_RX_DESC_TSFL_8822B(rxdesc) GET_RX_DESC_TSFL(rxdesc) #endif @@ -170,73 +185,81 @@ /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR_8197F(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc) -#define GET_RX_DESC_PHYPKTIDC_8197F(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc) -#define GET_RX_DESC_SWDEC_8197F(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc) -#define GET_RX_DESC_PHYST_8197F(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc) -#define GET_RX_DESC_SHIFT_8197F(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc) -#define GET_RX_DESC_QOS_8197F(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc) -#define GET_RX_DESC_SECURITY_8197F(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc) -#define GET_RX_DESC_DRV_INFO_SIZE_8197F(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) -#define GET_RX_DESC_ICV_ERR_8197F(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc) -#define GET_RX_DESC_CRC32_8197F(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc) -#define GET_RX_DESC_PKT_LEN_8197F(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc) +#define GET_RX_DESC_EOR_8197F(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8197F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8197F(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8197F(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8197F(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8197F(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8197F(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8197F(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8197F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8197F(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8197F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC_8197F(__pRxDesc) GET_RX_DESC_BC(__pRxDesc) -#define GET_RX_DESC_MC_8197F(__pRxDesc) GET_RX_DESC_MC(__pRxDesc) -#define GET_RX_DESC_TY_PE_8197F(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc) -#define GET_RX_DESC_MF_8197F(__pRxDesc) GET_RX_DESC_MF(__pRxDesc) -#define GET_RX_DESC_MD_8197F(__pRxDesc) GET_RX_DESC_MD(__pRxDesc) -#define GET_RX_DESC_PWR_8197F(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc) -#define GET_RX_DESC_PAM_8197F(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc) -#define GET_RX_DESC_CHK_VLD_8197F(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc) -#define GET_RX_DESC_RX_IS_TCP_UDP_8197F(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) -#define GET_RX_DESC_RX_IPV_8197F(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc) -#define GET_RX_DESC_CHKERR_8197F(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc) -#define GET_RX_DESC_PAGGR_8197F(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc) -#define GET_RX_DESC_RXID_MATCH_8197F(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc) -#define GET_RX_DESC_AMSDU_8197F(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc) -#define GET_RX_DESC_MACID_VLD_8197F(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc) -#define GET_RX_DESC_TID_8197F(__pRxDesc) GET_RX_DESC_TID(__pRxDesc) -#define GET_RX_DESC_EXT_SECTYPE_8197F(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc) -#define GET_RX_DESC_MACID_8197F(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc) +#define GET_RX_DESC_BC_8197F(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8197F(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8197F(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8197F(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8197F(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8197F(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8197F(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8197F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8197F(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8197F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8197F(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8197F(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8197F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8197F(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8197F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8197F(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8197F(rxdesc) GET_RX_DESC_MACID(rxdesc) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK_8197F(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) -#define GET_RX_DESC_C2H_8197F(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) -#define GET_RX_DESC_HWRSVD_8197F(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) -#define GET_RX_DESC_WLANHD_IV_LEN_8197F(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) -#define GET_RX_DESC_RX_IS_QOS_8197F(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc) -#define GET_RX_DESC_FRAG_8197F(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc) -#define GET_RX_DESC_SEQ_8197F(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc) +#define GET_RX_DESC_FCS_OK_8197F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_C2H_8197F(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8197F(rxdesc) GET_RX_DESC_HWRSVD(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8197F(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8197F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8197F(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8197F(rxdesc) GET_RX_DESC_SEQ(rxdesc) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE_8197F(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) -#define GET_RX_DESC_UNICAST_WAKE_8197F(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) -#define GET_RX_DESC_PATTERN_MATCH_8197F(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) -#define GET_RX_DESC_DMA_AGG_NUM_8197F(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_1_0_8197F(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) -#define GET_RX_DESC_EOSP_8197F(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) -#define GET_RX_DESC_HTC_8197F(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_4_2_8197F(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) -#define GET_RX_DESC_RX_RATE_8197F(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc) +#define GET_RX_DESC_MAGIC_WAKE_8197F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8197F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8197F(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8197F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8197F(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8197F(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8197F(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8197F(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8197F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT_8197F(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc) -#define GET_RX_DESC_MACID_RPT_BUFF_8197F(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) -#define GET_RX_DESC_RX_PRE_NDP_VLD_8197F(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) -#define GET_RX_DESC_RX_SCRAMBLER_8197F(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) -#define GET_RX_DESC_RX_EOF_8197F(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc) -#define GET_RX_DESC_PATTERN_IDX_8197F(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc) +#define GET_RX_DESC_A1_FIT_8197F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8197F(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8197F(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8197F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8197F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_FC_POWER_8197F(rxdesc) GET_RX_DESC_FC_POWER(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8197F(rxdesc) GET_RX_DESC_PATTERN_IDX_V1(rxdesc) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL_8197F(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc) +#define GET_RX_DESC_TSFL_8197F(rxdesc) GET_RX_DESC_TSFL(rxdesc) #endif @@ -244,147 +267,345 @@ /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR_8821C(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc) -#define GET_RX_DESC_PHYPKTIDC_8821C(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc) -#define GET_RX_DESC_SWDEC_8821C(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc) -#define GET_RX_DESC_PHYST_8821C(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc) -#define GET_RX_DESC_SHIFT_8821C(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc) -#define GET_RX_DESC_QOS_8821C(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc) -#define GET_RX_DESC_SECURITY_8821C(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc) -#define GET_RX_DESC_DRV_INFO_SIZE_8821C(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) -#define GET_RX_DESC_ICV_ERR_8821C(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc) -#define GET_RX_DESC_CRC32_8821C(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc) -#define GET_RX_DESC_PKT_LEN_8821C(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc) +#define GET_RX_DESC_EOR_8821C(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8821C(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8821C(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8821C(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8821C(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8821C(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8821C(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8821C(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8821C(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8821C(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8821C(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC_8821C(__pRxDesc) GET_RX_DESC_BC(__pRxDesc) -#define GET_RX_DESC_MC_8821C(__pRxDesc) GET_RX_DESC_MC(__pRxDesc) -#define GET_RX_DESC_TY_PE_8821C(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc) -#define GET_RX_DESC_MF_8821C(__pRxDesc) GET_RX_DESC_MF(__pRxDesc) -#define GET_RX_DESC_MD_8821C(__pRxDesc) GET_RX_DESC_MD(__pRxDesc) -#define GET_RX_DESC_PWR_8821C(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc) -#define GET_RX_DESC_PAM_8821C(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc) -#define GET_RX_DESC_CHK_VLD_8821C(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc) -#define GET_RX_DESC_RX_IS_TCP_UDP_8821C(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) -#define GET_RX_DESC_RX_IPV_8821C(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc) -#define GET_RX_DESC_CHKERR_8821C(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc) -#define GET_RX_DESC_PAGGR_8821C(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc) -#define GET_RX_DESC_RXID_MATCH_8821C(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc) -#define GET_RX_DESC_AMSDU_8821C(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc) -#define GET_RX_DESC_MACID_VLD_8821C(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc) -#define GET_RX_DESC_TID_8821C(__pRxDesc) GET_RX_DESC_TID(__pRxDesc) -#define GET_RX_DESC_EXT_SECTYPE_8821C(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc) -#define GET_RX_DESC_MACID_8821C(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc) +#define GET_RX_DESC_BC_8821C(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8821C(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8821C(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8821C(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8821C(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8821C(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8821C(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8821C(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8821C(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8821C(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8821C(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8821C(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8821C(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8821C(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8821C(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8821C(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8821C(rxdesc) GET_RX_DESC_MACID(rxdesc) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK_8821C(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) -#define GET_RX_DESC_PPDU_CNT_8821C(__pRxDesc) GET_RX_DESC_PPDU_CNT(__pRxDesc) -#define GET_RX_DESC_C2H_8821C(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) -#define GET_RX_DESC_HWRSVD_8821C(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) -#define GET_RX_DESC_WLANHD_IV_LEN_8821C(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) -#define GET_RX_DESC_RX_IS_QOS_8821C(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc) -#define GET_RX_DESC_FRAG_8821C(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc) -#define GET_RX_DESC_SEQ_8821C(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc) +#define GET_RX_DESC_FCS_OK_8821C(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_PPDU_CNT_8821C(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc) +#define GET_RX_DESC_C2H_8821C(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8821C(rxdesc) GET_RX_DESC_HWRSVD(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8821C(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8821C(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8821C(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8821C(rxdesc) GET_RX_DESC_SEQ(rxdesc) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE_8821C(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) -#define GET_RX_DESC_UNICAST_WAKE_8821C(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) -#define GET_RX_DESC_PATTERN_MATCH_8821C(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) -#define GET_RX_DESC_RXPAYLOAD_MATCH_8821C(__pRxDesc) GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) -#define GET_RX_DESC_RXPAYLOAD_ID_8821C(__pRxDesc) GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) -#define GET_RX_DESC_DMA_AGG_NUM_8821C(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_1_0_8821C(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) -#define GET_RX_DESC_EOSP_8821C(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) -#define GET_RX_DESC_HTC_8821C(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_4_2_8821C(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) -#define GET_RX_DESC_RX_RATE_8821C(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc) +#define GET_RX_DESC_MAGIC_WAKE_8821C(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8821C(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8821C(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8821C(rxdesc) \ + GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8821C(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8821C(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8821C(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8821C(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8821C(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8821C(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8821C(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT_8821C(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc) -#define GET_RX_DESC_MACID_RPT_BUFF_8821C(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) -#define GET_RX_DESC_RX_PRE_NDP_VLD_8821C(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) -#define GET_RX_DESC_RX_SCRAMBLER_8821C(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) -#define GET_RX_DESC_RX_EOF_8821C(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc) -#define GET_RX_DESC_PATTERN_IDX_8821C(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc) +#define GET_RX_DESC_A1_FIT_8821C(rxdesc) GET_RX_DESC_A1_FIT(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8821C(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8821C(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8821C(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8821C(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8821C(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL_8821C(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc) +#define GET_RX_DESC_TSFL_8821C(rxdesc) GET_RX_DESC_TSFL(rxdesc) #endif -#if (HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR_8188F(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc) -#define GET_RX_DESC_PHYPKTIDC_8188F(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc) -#define GET_RX_DESC_SWDEC_8188F(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc) -#define GET_RX_DESC_PHYST_8188F(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc) -#define GET_RX_DESC_SHIFT_8188F(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc) -#define GET_RX_DESC_QOS_8188F(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc) -#define GET_RX_DESC_SECURITY_8188F(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc) -#define GET_RX_DESC_DRV_INFO_SIZE_8188F(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) -#define GET_RX_DESC_ICV_ERR_8188F(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc) -#define GET_RX_DESC_CRC32_8188F(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc) -#define GET_RX_DESC_PKT_LEN_8188F(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc) +#define GET_RX_DESC_EVT_PKT_8814B(rxdesc) GET_RX_DESC_EVT_PKT(rxdesc) +#define GET_RX_DESC_SWDEC_8814B(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8814B(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8814B(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8814B(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8814B(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8814B(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8814B(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8814B(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8814B(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC_8188F(__pRxDesc) GET_RX_DESC_BC(__pRxDesc) -#define GET_RX_DESC_MC_8188F(__pRxDesc) GET_RX_DESC_MC(__pRxDesc) -#define GET_RX_DESC_TY_PE_8188F(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc) -#define GET_RX_DESC_MF_8188F(__pRxDesc) GET_RX_DESC_MF(__pRxDesc) -#define GET_RX_DESC_MD_8188F(__pRxDesc) GET_RX_DESC_MD(__pRxDesc) -#define GET_RX_DESC_PWR_8188F(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc) -#define GET_RX_DESC_PAM_8188F(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc) -#define GET_RX_DESC_CHK_VLD_8188F(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc) -#define GET_RX_DESC_RX_IS_TCP_UDP_8188F(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) -#define GET_RX_DESC_RX_IPV_8188F(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc) -#define GET_RX_DESC_CHKERR_8188F(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc) -#define GET_RX_DESC_PAGGR_8188F(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc) -#define GET_RX_DESC_RXID_MATCH_8188F(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc) -#define GET_RX_DESC_AMSDU_8188F(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc) -#define GET_RX_DESC_MACID_VLD_8188F(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc) -#define GET_RX_DESC_TID_8188F(__pRxDesc) GET_RX_DESC_TID(__pRxDesc) -#define GET_RX_DESC_MACID_8188F(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc) +#define GET_RX_DESC_BC_8814B(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8814B(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TYPE_8814B(rxdesc) GET_RX_DESC_TYPE(rxdesc) +#define GET_RX_DESC_MF_8814B(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8814B(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8814B(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_A1_MATCH_8814B(rxdesc) GET_RX_DESC_A1_MATCH(rxdesc) +#define GET_RX_DESC_TCP_CHKSUM_VLD_8814B(rxdesc) \ + GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8814B(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8814B(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_TCP_CHKSUM_ERR_8814B(rxdesc) \ + GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc) +#define GET_RX_DESC_PHY_PKT_IDC_8814B(rxdesc) GET_RX_DESC_PHY_PKT_IDC(rxdesc) +#define GET_RX_DESC_FW_FIFO_FULL_8814B(rxdesc) GET_RX_DESC_FW_FIFO_FULL(rxdesc) +#define GET_RX_DESC_AMPDU_8814B(rxdesc) GET_RX_DESC_AMPDU(rxdesc) +#define GET_RX_DESC_RXCMD_IDC_8814B(rxdesc) GET_RX_DESC_RXCMD_IDC(rxdesc) +#define GET_RX_DESC_AMSDU_8814B(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_TID_8814B(rxdesc) GET_RX_DESC_TID(rxdesc) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK_8188F(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) -#define GET_RX_DESC_C2H_8188F(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) -#define GET_RX_DESC_HWRSVD_8188F(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) -#define GET_RX_DESC_WLANHD_IV_LEN_8188F(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) -#define GET_RX_DESC_RX_IS_QOS_8188F(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc) -#define GET_RX_DESC_FRAG_8188F(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc) -#define GET_RX_DESC_SEQ_8188F(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc) +#define GET_RX_DESC_AMSDU_CUT_8814B(rxdesc) GET_RX_DESC_AMSDU_CUT(rxdesc) +#define GET_RX_DESC_PPDU_CNT_8814B(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc) +#define GET_RX_DESC_C2H_8814B(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8814B(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_LAST_MSDU_8814B(rxdesc) GET_RX_DESC_LAST_MSDU(rxdesc) +#define GET_RX_DESC_EXT_SEC_TYPE_8814B(rxdesc) GET_RX_DESC_EXT_SEC_TYPE(rxdesc) +#define GET_RX_DESC_FRAG_8814B(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8814B(rxdesc) GET_RX_DESC_SEQ(rxdesc) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE_8188F(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) -#define GET_RX_DESC_UNICAST_WAKE_8188F(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) -#define GET_RX_DESC_PATTERN_MATCH_8188F(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) -#define GET_RX_DESC_DMA_AGG_NUM_8188F(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_1_0_8188F(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) -#define GET_RX_DESC_EOSP_8188F(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) -#define GET_RX_DESC_HTC_8188F(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc) -#define GET_RX_DESC_RX_RATE_8188F(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc) +#define GET_RX_DESC_MAGIC_WAKE_8814B(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8814B(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_WAKE_8814B(rxdesc) GET_RX_DESC_PATTERN_WAKE(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8814B(rxdesc) \ + GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8814B(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8814B(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_8814B(rxdesc) GET_RX_DESC_BSSID_FIT(rxdesc) +#define GET_RX_DESC_HTC_8814B(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_AMPDU_END_PKT_8814B(rxdesc) \ + GET_RX_DESC_AMPDU_END_PKT(rxdesc) +#define GET_RX_DESC_ADDRESS_CAM_VLD_8814B(rxdesc) \ + GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc) +#define GET_RX_DESC_EOSP_8814B(rxdesc) GET_RX_DESC_EOSP_V1(rxdesc) +#define GET_RX_DESC_RX_RATE_8814B(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT_8188F(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc) -#define GET_RX_DESC_PATTERN_IDX_8188F(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc) +#define GET_RX_DESC_ADDRESS_CAM_8814B(rxdesc) GET_RX_DESC_ADDRESS_CAM(rxdesc) +#define GET_RX_DESC_MACID_VLD_8814B(rxdesc) GET_RX_DESC_MACID_VLD_V1(rxdesc) +#define GET_RX_DESC_MACID_8814B(rxdesc) GET_RX_DESC_MACID_V1(rxdesc) +#define GET_RX_DESC_SWPS_RPT_8814B(rxdesc) GET_RX_DESC_SWPS_RPT(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8814B(rxdesc) GET_RX_DESC_PATTERN_IDX_V2(rxdesc) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL_8188F(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc) +#define GET_RX_DESC_FREERUN_CNT_8814B(rxdesc) GET_RX_DESC_FREERUN_CNT(rxdesc) #endif +#if (HALMAC_8198F_SUPPORT) + +/*RXDESC_WORD0*/ + +#define GET_RX_DESC_EOR_8198F(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8198F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8198F(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8198F(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8198F(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8198F(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8198F(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8198F(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8198F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8198F(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8198F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) + +/*RXDESC_WORD1*/ + +#define GET_RX_DESC_BC_8198F(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8198F(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8198F(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8198F(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8198F(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8198F(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8198F(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8198F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8198F(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8198F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8198F(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8198F(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8198F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8198F(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8198F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8198F(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8198F(rxdesc) GET_RX_DESC_MACID(rxdesc) + +/*RXDESC_WORD2*/ + +#define GET_RX_DESC_FCS_OK_8198F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_PPDU_CNT_8198F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc) +#define GET_RX_DESC_C2H_8198F(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8198F(rxdesc) GET_RX_DESC_HWRSVD_V1(rxdesc) +#define GET_RX_DESC_RXMAGPKT_8198F(rxdesc) GET_RX_DESC_RXMAGPKT(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8198F(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8198F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8198F(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8198F(rxdesc) GET_RX_DESC_SEQ(rxdesc) + +/*RXDESC_WORD3*/ + +#define GET_RX_DESC_MAGIC_WAKE_8198F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8198F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8198F(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8198F(rxdesc) \ + GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8198F(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8198F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8198F(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8198F(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8198F(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8198F(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8198F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) + +/*RXDESC_WORD4*/ + +#define GET_RX_DESC_A1_FIT_A1_8198F(rxdesc) GET_RX_DESC_A1_FIT_A1(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8198F(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8198F(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8198F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8198F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_FC_POWER_8198F(rxdesc) GET_RX_DESC_FC_POWER(rxdesc) +#define GET_RX_DESC_TXRPTMID_CTL_MASK_8198F(rxdesc) \ + GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc) +#define GET_RX_DESC_SWPS_RPT_8198F(rxdesc) GET_RX_DESC_SWPS_RPT(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8198F(rxdesc) GET_RX_DESC_PATTERN_IDX_V1(rxdesc) + +/*RXDESC_WORD5*/ + +#define GET_RX_DESC_TSFL_8198F(rxdesc) GET_RX_DESC_TSFL(rxdesc) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +/*RXDESC_WORD0*/ + +#define GET_RX_DESC_EOR_8822C(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8822C(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8822C(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8822C(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8822C(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8822C(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8822C(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8822C(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8822C(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8822C(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8822C(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) + +/*RXDESC_WORD1*/ + +#define GET_RX_DESC_BC_8822C(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8822C(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8822C(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8822C(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8822C(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8822C(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8822C(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8822C(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8822C(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8822C(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8822C(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8822C(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8822C(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8822C(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8822C(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8822C(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8822C(rxdesc) GET_RX_DESC_MACID(rxdesc) + +/*RXDESC_WORD2*/ + +#define GET_RX_DESC_FCS_OK_8822C(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_PPDU_CNT_8822C(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc) +#define GET_RX_DESC_C2H_8822C(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8822C(rxdesc) GET_RX_DESC_HWRSVD(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8822C(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_STATISTICS_8822C(rxdesc) \ + GET_RX_DESC_RX_STATISTICS(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8822C(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8822C(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8822C(rxdesc) GET_RX_DESC_SEQ(rxdesc) + +/*RXDESC_WORD3*/ + +#define GET_RX_DESC_MAGIC_WAKE_8822C(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8822C(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8822C(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8822C(rxdesc) \ + GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8822C(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8822C(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8822C(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8822C(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8822C(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8822C(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8822C(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) + +/*RXDESC_WORD4*/ + +#define GET_RX_DESC_A1_FIT_8822C(rxdesc) GET_RX_DESC_A1_FIT(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8822C(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8822C(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8822C(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8822C(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8822C(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc) + +/*RXDESC_WORD5*/ + +#define GET_RX_DESC_TSFL_8822C(rxdesc) GET_RX_DESC_TSFL(rxdesc) #endif +#endif diff --git a/hal/halmac/halmac_rx_desc_nic.h b/hal/halmac/halmac_rx_desc_nic.h index 2e9209e..a3baf98 100644 --- a/hal/halmac/halmac_rx_desc_nic.h +++ b/hal/halmac/halmac_rx_desc_nic.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,133 +15,448 @@ #ifndef _HALMAC_RX_DESC_NIC_H_ #define _HALMAC_RX_DESC_NIC_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 30, 1) -#define GET_RX_DESC_PHYPKTIDC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 28, 1) -#define GET_RX_DESC_SWDEC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 27, 1) -#define GET_RX_DESC_PHYST(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 26, 1) -#define GET_RX_DESC_SHIFT(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 24, 2) -#define GET_RX_DESC_QOS(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 23, 1) -#define GET_RX_DESC_SECURITY(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 20, 3) -#define GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 16, 4) -#define GET_RX_DESC_ICV_ERR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 15, 1) -#define GET_RX_DESC_CRC32(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 14, 1) -#define GET_RX_DESC_PKT_LEN(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 0, 14) +#define GET_RX_DESC_EOR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 30, 1) +#define GET_RX_DESC_PHYPKTIDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_EVT_PKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_SWDEC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 27, 1) +#define GET_RX_DESC_PHYST(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 26, 1) +#define GET_RX_DESC_SHIFT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 24, 2) +#define GET_RX_DESC_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 23, 1) +#define GET_RX_DESC_SECURITY(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 20, 3) +#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 16, 4) +#define GET_RX_DESC_ICV_ERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 15, 1) +#define GET_RX_DESC_CRC32(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 14, 1) +#define GET_RX_DESC_PKT_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 0, 14) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 31, 1) -#define GET_RX_DESC_MC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 30, 1) -#define GET_RX_DESC_TY_PE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 28, 2) -#define GET_RX_DESC_MF(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 27, 1) -#define GET_RX_DESC_MD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 26, 1) -#define GET_RX_DESC_PWR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 25, 1) -#define GET_RX_DESC_PAM(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 24, 1) -#define GET_RX_DESC_CHK_VLD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 23, 1) -#define GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 22, 1) -#define GET_RX_DESC_RX_IPV(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 21, 1) -#define GET_RX_DESC_CHKERR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 20, 1) -#define GET_RX_DESC_PAGGR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 15, 1) -#define GET_RX_DESC_RXID_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 14, 1) -#define GET_RX_DESC_AMSDU(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 13, 1) -#define GET_RX_DESC_MACID_VLD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 12, 1) -#define GET_RX_DESC_TID(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 8, 4) +#define GET_RX_DESC_BC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 31, 1) +#define GET_RX_DESC_MC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 30, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_TY_PE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_TYPE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_MF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 27, 1) +#define GET_RX_DESC_MD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 26, 1) +#define GET_RX_DESC_PWR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 25, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_PAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_A1_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_CHK_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 22, 1) +#define GET_RX_DESC_RX_IPV(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 21, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_CHKERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1) +#define GET_RX_DESC_PHY_PKT_IDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 17, 1) +#define GET_RX_DESC_FW_FIFO_FULL(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 16, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_PAGGR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_AMPDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_RXID_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_RXCMD_IDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_AMSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 13, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define GET_RX_DESC_EXT_SECTYPE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 7, 1) +#define GET_RX_DESC_MACID_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 12, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_TID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 8, 4) + +#endif -#define GET_RX_DESC_MACID(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 0, 7) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_MACID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 0, 7) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 31, 1) +#define GET_RX_DESC_FCS_OK(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 31, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_AMSDU_CUT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 31, 1) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_PPDU_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 29, 2) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_C2H(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 28, 1) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_HWRSVD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 25, 3) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_HWRSVD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 4) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_RXMAGPKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 18, 6) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_LAST_MSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_RX_STATISTICS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_RX_IS_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define GET_RX_DESC_PPDU_CNT(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 29, 2) +#define GET_RX_DESC_EXT_SEC_TYPE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define GET_RX_DESC_C2H(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 28, 1) -#define GET_RX_DESC_HWRSVD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 24, 4) -#define GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 18, 6) -#define GET_RX_DESC_RX_IS_QOS(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 16, 1) -#define GET_RX_DESC_FRAG(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 12, 4) -#define GET_RX_DESC_SEQ(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 0, 12) +#define GET_RX_DESC_FRAG(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 12, 4) +#define GET_RX_DESC_SEQ(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 0, 12) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 31, 1) -#define GET_RX_DESC_UNICAST_WAKE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 30, 1) -#define GET_RX_DESC_PATTERN_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 29, 1) +#define GET_RX_DESC_MAGIC_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 31, 1) +#define GET_RX_DESC_UNICAST_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 30, 1) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 28, 1) -#define GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 24, 4) +#define GET_RX_DESC_PATTERN_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 16, 8) -#define GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 12, 2) -#define GET_RX_DESC_EOSP(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 11, 1) -#define GET_RX_DESC_HTC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 10, 1) +#define GET_RX_DESC_PATTERN_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 7, 3) +#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x0C, 28, 1) +#define GET_RX_DESC_RXPAYLOAD_ID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 24, 4) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 16, 8) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 12, 2) +#define GET_RX_DESC_EOSP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_BSSID_FIT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 5) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_HTC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 10, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_AMPDU_END_PKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 9, 1) +#define GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x0C, 8, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 3) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_EOSP_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_RX_RATE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 0, 7) -#define GET_RX_DESC_RX_RATE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 0, 7) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 24, 5) +#define GET_RX_DESC_A1_FIT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 5) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_ADDRESS_CAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 8) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_A1_FIT_A1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 7) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_MACID_VLD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 23, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x10, 17, 7) +#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x10, 16, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 17, 7) -#define GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 16, 1) -#define GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 9, 7) -#define GET_RX_DESC_RX_EOF(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 8, 1) +#define GET_RX_DESC_MACID_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 15, 8) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define GET_RX_DESC_PATTERN_IDX(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 0, 8) +#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 9, 7) +#define GET_RX_DESC_RX_EOF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 8, 1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_FC_POWER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 7, 1) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x10, 6, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_SWPS_RPT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 5, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define GET_RX_DESC_PATTERN_IDX(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_PATTERN_IDX_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 5) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_PATTERN_IDX_V2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 5) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x14, 0, 32) +#define GET_RX_DESC_TSFL(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x14, 0, 32) #endif +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_FREERUN_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x14, 0, 32) #endif +#endif diff --git a/hal/halmac/halmac_sdio_reg.h b/hal/halmac/halmac_sdio_reg.h index 2a47d6f..71f3de6 100644 --- a/hal/halmac/halmac_sdio_reg.h +++ b/hal/halmac/halmac_sdio_reg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -20,11 +20,11 @@ #define HALMAC_SDIO_4BYTE_LEN_MASK 0x1FFF #define HALMAC_SDIO_LOCAL_MSK 0x0FFF -#define HALMAC_WLAN_MAC_REG_MSK 0xFFFF -#define HALMAC_WLAN_IOREG_MSK 0xFFFF +#define HALMAC_WLAN_MAC_REG_MSK 0xFFFF +#define HALMAC_WLAN_IOREG_MSK 0xFFFF /* Sdio Address for SDIO Local Reg, TRX FIFO, MAC Reg */ -typedef enum { +enum halmac_sdio_cmd_addr { HALMAC_SDIO_CMD_ADDR_SDIO_REG = 0, HALMAC_SDIO_CMD_ADDR_MAC_REG = 8, HALMAC_SDIO_CMD_ADDR_TXFF_HIGH = 4, @@ -32,7 +32,7 @@ typedef enum { HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL = 5, HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA = 7, HALMAC_SDIO_CMD_ADDR_RXFF = 7, -} HALMAC_SDIO_CMD_ADDR; +}; /* IO Bus domain address mapping */ #define SDIO_LOCAL_OFFSET 0x10250000 @@ -46,8 +46,10 @@ typedef enum { /* Get TX WLAN FIFO information in CMD53 addr */ #if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) -#define GET_WLAN_TXFF_DEVICE_ID(__pCmd53_addr) LE_BITS_TO_4BYTE((u32 *)__pCmd53_addr, 13, 4) -#define GET_WLAN_TXFF_PKT_SIZE(__pCmd53_addr) (LE_BITS_TO_4BYTE((u32 *)__pCmd53_addr, 0, 13) << 2) +#define GET_WLAN_TXFF_DEVICE_ID(cmd53_addr) \ + LE_BITS_TO_4BYTE((u32 *)cmd53_addr, 13, 4) +#define GET_WLAN_TXFF_PKT_SIZE(cmd53_addr) \ + (LE_BITS_TO_4BYTE((u32 *)cmd53_addr, 0, 13) << 2) #endif #endif/* __HALMAC_SDIO_REG_H__ */ diff --git a/hal/halmac/halmac_tx_bd_ap.h b/hal/halmac/halmac_tx_bd_ap.h deleted file mode 100644 index 3b9c21a..0000000 --- a/hal/halmac/halmac_tx_bd_ap.h +++ /dev/null @@ -1,110 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_TX_BD_AP_H_ -#define _HALMAC_TX_BD_AP_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) - -/*TXBD_DW0*/ - -#define SET_TX_BD_OWN(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0x1, 31) -#define SET_TX_BD_OWN_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0x1, 31) -#define GET_TX_BD_OWN(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword0, 0x1, 31) -#define SET_TX_BD_PSB(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xff, 16) -#define SET_TX_BD_PSB_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xff, 16) -#define GET_TX_BD_PSB(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword0, 0xff, 16) -#define SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xffff, 0) -#define SET_TX_BD_TX_BUFF_SIZE0_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xffff, 0) -#define GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword0, 0xffff, 0) - -/*TXBD_DW1*/ - -#define SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword1, __Value, 0xffffffff, 0) -#define SET_TX_BD_PHYSICAL_ADDR0_LOW_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword1, __Value, 0xffffffff, 0) -#define GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword1, 0xffffffff, 0) - -/*TXBD_DW2*/ - -#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword2, __Value, 0xffffffff, 0) -#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword2, __Value, 0xffffffff, 0) -#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword2, 0xffffffff, 0) - -/*TXBD_DW4*/ - -#define SET_TX_BD_A1(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0x1, 31) -#define SET_TX_BD_A1_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0x1, 31) -#define GET_TX_BD_A1(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword4, 0x1, 31) -#define SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0xffff, 0) -#define SET_TX_BD_TX_BUFF_SIZE1_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0xffff, 0) -#define GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword4, 0xffff, 0) - -/*TXBD_DW5*/ - -#define SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword5, __Value, 0xffffffff, 0) -#define SET_TX_BD_PHYSICAL_ADDR1_LOW_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword5, __Value, 0xffffffff, 0) -#define GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword5, 0xffffffff, 0) - -/*TXBD_DW6*/ - -#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword6, __Value, 0xffffffff, 0) -#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword6, __Value, 0xffffffff, 0) -#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword6, 0xffffffff, 0) - -/*TXBD_DW8*/ - -#define SET_TX_BD_A2(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0x1, 31) -#define SET_TX_BD_A2_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0x1, 31) -#define GET_TX_BD_A2(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword8, 0x1, 31) -#define SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0xffff, 0) -#define SET_TX_BD_TX_BUFF_SIZE2_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0xffff, 0) -#define GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword8, 0xffff, 0) - -/*TXBD_DW9*/ - -#define SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword9, __Value, 0xffffffff, 0) -#define SET_TX_BD_PHYSICAL_ADDR2_LOW_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword9, __Value, 0xffffffff, 0) -#define GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword9, 0xffffffff, 0) - -/*TXBD_DW10*/ - -#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword10, __Value, 0xffffffff, 0) -#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword10, __Value, 0xffffffff, 0) -#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword10, 0xffffffff, 0) - -/*TXBD_DW12*/ - -#define SET_TX_BD_A3(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0x1, 31) -#define SET_TX_BD_A3_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0x1, 31) -#define GET_TX_BD_A3(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword12, 0x1, 31) -#define SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0xffff, 0) -#define SET_TX_BD_TX_BUFF_SIZE3_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0xffff, 0) -#define GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword12, 0xffff, 0) - -/*TXBD_DW13*/ - -#define SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword13, __Value, 0xffffffff, 0) -#define SET_TX_BD_PHYSICAL_ADDR3_LOW_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword13, __Value, 0xffffffff, 0) -#define GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword13, 0xffffffff, 0) - -/*TXBD_DW14*/ - -#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword14, __Value, 0xffffffff, 0) -#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword14, __Value, 0xffffffff, 0) -#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword14, 0xffffffff, 0) - -#endif - - -#endif diff --git a/hal/halmac/halmac_tx_bd_chip.h b/hal/halmac/halmac_tx_bd_chip.h deleted file mode 100644 index 0ebf93c..0000000 --- a/hal/halmac/halmac_tx_bd_chip.h +++ /dev/null @@ -1,389 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - ******************************************************************************/ - -#ifndef _HALMAC_TX_BD_CHIP_H_ -#define _HALMAC_TX_BD_CHIP_H_ -#if (HALMAC_8814A_SUPPORT) - -/*TXBD_DW0*/ - -#define SET_TX_BD_OWN_8814A(__pTxBd, __Value) SET_TX_BD_OWN(__pTxBd, __Value) -#define GET_TX_BD_OWN_8814A(__pTxBd) GET_TX_BD_OWN(__pTxBd) -#define SET_TX_BD_PSB_8814A(__pTxBd, __Value) SET_TX_BD_PSB(__pTxBd, __Value) -#define GET_TX_BD_PSB_8814A(__pTxBd) GET_TX_BD_PSB(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE0_8814A(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE0_8814A(__pTxBd) GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) - -/*TXBD_DW1*/ - -#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) - -/*TXBD_DW2*/ - -#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) - -/*TXBD_DW4*/ - -#define SET_TX_BD_A1_8814A(__pTxBd, __Value) SET_TX_BD_A1(__pTxBd, __Value) -#define GET_TX_BD_A1_8814A(__pTxBd) GET_TX_BD_A1(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE1_8814A(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE1_8814A(__pTxBd) GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) - -/*TXBD_DW5*/ - -#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) - -/*TXBD_DW6*/ - -#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) - -/*TXBD_DW8*/ - -#define SET_TX_BD_A2_8814A(__pTxBd, __Value) SET_TX_BD_A2(__pTxBd, __Value) -#define GET_TX_BD_A2_8814A(__pTxBd) GET_TX_BD_A2(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE2_8814A(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE2_8814A(__pTxBd) GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) - -/*TXBD_DW9*/ - -#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) - -/*TXBD_DW10*/ - -#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) - -/*TXBD_DW12*/ - -#define SET_TX_BD_A3_8814A(__pTxBd, __Value) SET_TX_BD_A3(__pTxBd, __Value) -#define GET_TX_BD_A3_8814A(__pTxBd) GET_TX_BD_A3(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE3_8814A(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE3_8814A(__pTxBd) GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) - -/*TXBD_DW13*/ - -#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) - -/*TXBD_DW14*/ - -#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) - -#endif - -#if (HALMAC_8822B_SUPPORT) - -/*TXBD_DW0*/ - -#define SET_TX_BD_OWN_8822B(__pTxBd, __Value) SET_TX_BD_OWN(__pTxBd, __Value) -#define GET_TX_BD_OWN_8822B(__pTxBd) GET_TX_BD_OWN(__pTxBd) -#define SET_TX_BD_PSB_8822B(__pTxBd, __Value) SET_TX_BD_PSB(__pTxBd, __Value) -#define GET_TX_BD_PSB_8822B(__pTxBd) GET_TX_BD_PSB(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE0_8822B(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE0_8822B(__pTxBd) GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) - -/*TXBD_DW1*/ - -#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) - -/*TXBD_DW2*/ - -#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) - -/*TXBD_DW4*/ - -#define SET_TX_BD_A1_8822B(__pTxBd, __Value) SET_TX_BD_A1(__pTxBd, __Value) -#define GET_TX_BD_A1_8822B(__pTxBd) GET_TX_BD_A1(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE1_8822B(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE1_8822B(__pTxBd) GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) - -/*TXBD_DW5*/ - -#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) - -/*TXBD_DW6*/ - -#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) - -/*TXBD_DW8*/ - -#define SET_TX_BD_A2_8822B(__pTxBd, __Value) SET_TX_BD_A2(__pTxBd, __Value) -#define GET_TX_BD_A2_8822B(__pTxBd) GET_TX_BD_A2(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE2_8822B(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE2_8822B(__pTxBd) GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) - -/*TXBD_DW9*/ - -#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) - -/*TXBD_DW10*/ - -#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) - -/*TXBD_DW12*/ - -#define SET_TX_BD_A3_8822B(__pTxBd, __Value) SET_TX_BD_A3(__pTxBd, __Value) -#define GET_TX_BD_A3_8822B(__pTxBd) GET_TX_BD_A3(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE3_8822B(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE3_8822B(__pTxBd) GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) - -/*TXBD_DW13*/ - -#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) - -/*TXBD_DW14*/ - -#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) - -#endif - -#if (HALMAC_8197F_SUPPORT) - -/*TXBD_DW0*/ - -#define SET_TX_BD_OWN_8197F(__pTxBd, __Value) SET_TX_BD_OWN(__pTxBd, __Value) -#define GET_TX_BD_OWN_8197F(__pTxBd) GET_TX_BD_OWN(__pTxBd) -#define SET_TX_BD_PSB_8197F(__pTxBd, __Value) SET_TX_BD_PSB(__pTxBd, __Value) -#define GET_TX_BD_PSB_8197F(__pTxBd) GET_TX_BD_PSB(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE0_8197F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE0_8197F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) - -/*TXBD_DW1*/ - -#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) - -/*TXBD_DW2*/ - -#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) - -/*TXBD_DW4*/ - -#define SET_TX_BD_A1_8197F(__pTxBd, __Value) SET_TX_BD_A1(__pTxBd, __Value) -#define GET_TX_BD_A1_8197F(__pTxBd) GET_TX_BD_A1(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE1_8197F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE1_8197F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) - -/*TXBD_DW5*/ - -#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) - -/*TXBD_DW6*/ - -#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) - -/*TXBD_DW8*/ - -#define SET_TX_BD_A2_8197F(__pTxBd, __Value) SET_TX_BD_A2(__pTxBd, __Value) -#define GET_TX_BD_A2_8197F(__pTxBd) GET_TX_BD_A2(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE2_8197F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE2_8197F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) - -/*TXBD_DW9*/ - -#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) - -/*TXBD_DW10*/ - -#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) - -/*TXBD_DW12*/ - -#define SET_TX_BD_A3_8197F(__pTxBd, __Value) SET_TX_BD_A3(__pTxBd, __Value) -#define GET_TX_BD_A3_8197F(__pTxBd) GET_TX_BD_A3(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE3_8197F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE3_8197F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) - -/*TXBD_DW13*/ - -#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) - -/*TXBD_DW14*/ - -#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) - -#endif - -#if (HALMAC_8821C_SUPPORT) - -/*TXBD_DW0*/ - -#define SET_TX_BD_OWN_8821C(__pTxBd, __Value) SET_TX_BD_OWN(__pTxBd, __Value) -#define GET_TX_BD_OWN_8821C(__pTxBd) GET_TX_BD_OWN(__pTxBd) -#define SET_TX_BD_PSB_8821C(__pTxBd, __Value) SET_TX_BD_PSB(__pTxBd, __Value) -#define GET_TX_BD_PSB_8821C(__pTxBd) GET_TX_BD_PSB(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE0_8821C(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE0_8821C(__pTxBd) GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) - -/*TXBD_DW1*/ - -#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) - -/*TXBD_DW2*/ - -#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) - -/*TXBD_DW4*/ - -#define SET_TX_BD_A1_8821C(__pTxBd, __Value) SET_TX_BD_A1(__pTxBd, __Value) -#define GET_TX_BD_A1_8821C(__pTxBd) GET_TX_BD_A1(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE1_8821C(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE1_8821C(__pTxBd) GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) - -/*TXBD_DW5*/ - -#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) - -/*TXBD_DW6*/ - -#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) - -/*TXBD_DW8*/ - -#define SET_TX_BD_A2_8821C(__pTxBd, __Value) SET_TX_BD_A2(__pTxBd, __Value) -#define GET_TX_BD_A2_8821C(__pTxBd) GET_TX_BD_A2(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE2_8821C(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE2_8821C(__pTxBd) GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) - -/*TXBD_DW9*/ - -#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) - -/*TXBD_DW10*/ - -#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) - -/*TXBD_DW12*/ - -#define SET_TX_BD_A3_8821C(__pTxBd, __Value) SET_TX_BD_A3(__pTxBd, __Value) -#define GET_TX_BD_A3_8821C(__pTxBd) GET_TX_BD_A3(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE3_8821C(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE3_8821C(__pTxBd) GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) - -/*TXBD_DW13*/ - -#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) - -/*TXBD_DW14*/ - -#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) - -#endif - -#if (HALMAC_8188F_SUPPORT) - -/*TXBD_DW0*/ - -#define SET_TX_BD_OWN_8188F(__pTxBd, __Value) SET_TX_BD_OWN(__pTxBd, __Value) -#define GET_TX_BD_OWN_8188F(__pTxBd) GET_TX_BD_OWN(__pTxBd) -#define SET_TX_BD_PSB_8188F(__pTxBd, __Value) SET_TX_BD_PSB(__pTxBd, __Value) -#define GET_TX_BD_PSB_8188F(__pTxBd) GET_TX_BD_PSB(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE0_8188F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE0_8188F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) - -/*TXBD_DW1*/ - -#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) - -/*TXBD_DW2*/ - -#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) - -/*TXBD_DW4*/ - -#define SET_TX_BD_A1_8188F(__pTxBd, __Value) SET_TX_BD_A1(__pTxBd, __Value) -#define GET_TX_BD_A1_8188F(__pTxBd) GET_TX_BD_A1(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE1_8188F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE1_8188F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) - -/*TXBD_DW5*/ - -#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) - -/*TXBD_DW6*/ - -#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) - -/*TXBD_DW8*/ - -#define SET_TX_BD_A2_8188F(__pTxBd, __Value) SET_TX_BD_A2(__pTxBd, __Value) -#define GET_TX_BD_A2_8188F(__pTxBd) GET_TX_BD_A2(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE2_8188F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE2_8188F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) - -/*TXBD_DW9*/ - -#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) - -/*TXBD_DW10*/ - -#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) - -/*TXBD_DW12*/ - -#define SET_TX_BD_A3_8188F(__pTxBd, __Value) SET_TX_BD_A3(__pTxBd, __Value) -#define GET_TX_BD_A3_8188F(__pTxBd) GET_TX_BD_A3(__pTxBd) -#define SET_TX_BD_TX_BUFF_SIZE3_8188F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) -#define GET_TX_BD_TX_BUFF_SIZE3_8188F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) - -/*TXBD_DW13*/ - -#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) - -/*TXBD_DW14*/ - -#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) - -#endif - - -#endif diff --git a/hal/halmac/halmac_tx_bd_nic.h b/hal/halmac/halmac_tx_bd_nic.h index 94e4480..5f312cf 100644 --- a/hal/halmac/halmac_tx_bd_nic.h +++ b/hal/halmac/halmac_tx_bd_nic.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,79 +15,96 @@ #ifndef _HALMAC_TX_BD_NIC_H_ #define _HALMAC_TX_BD_NIC_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /*TXBD_DW0*/ -#define SET_TX_BD_OWN(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x00, 31, 1, __Value) -#define GET_TX_BD_OWN(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x00, 31, 1) -#define SET_TX_BD_PSB(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x00, 16, 8, __Value) -#define GET_TX_BD_PSB(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x00, 16, 8) -#define SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x00, 0, 16, __Value) -#define GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x00, 0, 16) +#define SET_TX_BD_OWN(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x00, 31, 1, value) +#define GET_TX_BD_OWN(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 31, 1) +#define SET_TX_BD_PSB(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x00, 16, 8, value) +#define GET_TX_BD_PSB(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 16, 8) +#define SET_TX_BD_TX_BUFF_SIZE0(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x00, 0, 16, value) +#define GET_TX_BD_TX_BUFF_SIZE0(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 0, 16) /*TXBD_DW1*/ -#define SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x04, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x04, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x04, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x04, 0, 32) /*TXBD_DW2*/ -#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x08, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x08, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x08, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x08, 0, 32) /*TXBD_DW4*/ -#define SET_TX_BD_A1(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x10, 31, 1, __Value) -#define GET_TX_BD_A1(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x10, 31, 1) -#define SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x10, 0, 16, __Value) -#define GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x10, 0, 16) +#define SET_TX_BD_A1(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x10, 31, 1, value) +#define GET_TX_BD_A1(txbd) LE_BITS_TO_4BYTE(txbd + 0x10, 31, 1) +#define SET_TX_BD_TX_BUFF_SIZE1(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x10, 0, 16, value) +#define GET_TX_BD_TX_BUFF_SIZE1(txbd) LE_BITS_TO_4BYTE(txbd + 0x10, 0, 16) /*TXBD_DW5*/ -#define SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x14, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x14, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR1_LOW(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x14, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR1_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x14, 0, 32) /*TXBD_DW6*/ -#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x18, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x18, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x18, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x18, 0, 32) /*TXBD_DW8*/ -#define SET_TX_BD_A2(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x20, 31, 1, __Value) -#define GET_TX_BD_A2(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x20, 31, 1) -#define SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x20, 0, 16, __Value) -#define GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x20, 0, 16) +#define SET_TX_BD_A2(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x20, 31, 1, value) +#define GET_TX_BD_A2(txbd) LE_BITS_TO_4BYTE(txbd + 0x20, 31, 1) +#define SET_TX_BD_TX_BUFF_SIZE2(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x20, 0, 16, value) +#define GET_TX_BD_TX_BUFF_SIZE2(txbd) LE_BITS_TO_4BYTE(txbd + 0x20, 0, 16) /*TXBD_DW9*/ -#define SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x24, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x24, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR2_LOW(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x24, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR2_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x24, 0, 32) /*TXBD_DW10*/ -#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x28, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x28, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x28, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x28, 0, 32) /*TXBD_DW12*/ -#define SET_TX_BD_A3(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x30, 31, 1, __Value) -#define GET_TX_BD_A3(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x30, 31, 1) -#define SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x30, 0, 16, __Value) -#define GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x30, 0, 16) +#define SET_TX_BD_A3(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x30, 31, 1, value) +#define GET_TX_BD_A3(txbd) LE_BITS_TO_4BYTE(txbd + 0x30, 31, 1) +#define SET_TX_BD_TX_BUFF_SIZE3(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x30, 0, 16, value) +#define GET_TX_BD_TX_BUFF_SIZE3(txbd) LE_BITS_TO_4BYTE(txbd + 0x30, 0, 16) /*TXBD_DW13*/ -#define SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x34, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x34, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR3_LOW(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x34, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR3_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x34, 0, 32) /*TXBD_DW14*/ -#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x38, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x38, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x38, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x38, 0, 32) #endif - #endif diff --git a/hal/halmac/halmac_tx_desc_ap.h b/hal/halmac/halmac_tx_desc_ap.h index de2cdd6..c806492 100644 --- a/hal/halmac/halmac_tx_desc_ap.h +++ b/hal/halmac/halmac_tx_desc_ap.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,567 +15,1824 @@ #ifndef _HALMAC_TX_DESC_AP_H_ #define _HALMAC_TX_DESC_AP_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /*TXDESC_WORD0*/ -#define SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 31) -#define SET_TX_DESC_DISQSELSEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 31) -#define GET_TX_DESC_DISQSELSEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 31) +#define SET_TX_DESC_DISQSELSEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 31) +#define SET_TX_DESC_DISQSELSEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31) +#define GET_TX_DESC_DISQSELSEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 31) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_GF(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 30) -#define SET_TX_DESC_GF_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 30) -#define GET_TX_DESC_GF(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 30) -#define SET_TX_DESC_NO_ACM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 29) -#define SET_TX_DESC_NO_ACM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 29) -#define GET_TX_DESC_NO_ACM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 29) +#define SET_TX_DESC_IE_END_BODY(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 31) +#define SET_TX_DESC_IE_END_BODY_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31) +#define GET_TX_DESC_IE_END_BODY(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 31) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 28) -#define SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 28) -#define GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 28) +#define SET_TX_DESC_GF(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 30) +#define SET_TX_DESC_GF_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30) +#define GET_TX_DESC_GF(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 30) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 27) -#define SET_TX_DESC_AMSDU_PAD_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 27) -#define GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 27) +#define SET_TX_DESC_AGG_EN_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 30) +#define SET_TX_DESC_AGG_EN_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30) +#define GET_TX_DESC_AGG_EN_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 30) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_LS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 26) -#define SET_TX_DESC_LS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 26) -#define GET_TX_DESC_LS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 26) -#define SET_TX_DESC_HTC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 25) -#define SET_TX_DESC_HTC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 25) -#define GET_TX_DESC_HTC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 25) -#define SET_TX_DESC_BMC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 24) -#define SET_TX_DESC_BMC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 24) -#define GET_TX_DESC_BMC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 24) -#define SET_TX_DESC_OFFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xff, 16) -#define SET_TX_DESC_OFFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xff, 16) -#define GET_TX_DESC_OFFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0xff, 16) -#define SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xffff, 0) -#define SET_TX_DESC_TXPKTSIZE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xffff, 0) -#define GET_TX_DESC_TXPKTSIZE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0xffff, 0) +#define SET_TX_DESC_NO_ACM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 29) +#define SET_TX_DESC_NO_ACM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29) +#define GET_TX_DESC_NO_ACM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 29) -/*TXDESC_WORD1*/ +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_BK_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 29) +#define SET_TX_DESC_BK_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29) +#define GET_TX_DESC_BK_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 29) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 28) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 28) +#define GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 28) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 27) +#define SET_TX_DESC_AMSDU_PAD_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 27) +#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 27) +#define SET_TX_DESC_LS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 26) +#define SET_TX_DESC_LS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 26) +#define GET_TX_DESC_LS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 26) +#define SET_TX_DESC_HTC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 25) +#define SET_TX_DESC_HTC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 25) +#define GET_TX_DESC_HTC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 25) +#define SET_TX_DESC_BMC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 24) +#define SET_TX_DESC_BMC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 24) +#define GET_TX_DESC_BMC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 24) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_PKT_OFFSET_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1f, 24) +#define SET_TX_DESC_PKT_OFFSET_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1f, 24) +#define GET_TX_DESC_PKT_OFFSET_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1f, \ + 24) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_OFFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0xff, 16) +#define SET_TX_DESC_OFFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0xff, 16) +#define GET_TX_DESC_OFFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0xff, \ + 16) +#define SET_TX_DESC_TXPKTSIZE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0xffff, 0) +#define SET_TX_DESC_TXPKTSIZE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0xffff, 0) +#define GET_TX_DESC_TXPKTSIZE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, \ + 0xffff, 0) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/*WORD1*/ + +#define SET_TX_DESC_HW_AES_IV_V2(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 31) +#define SET_TX_DESC_HW_AES_IV_V2_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 31) +#define GET_TX_DESC_HW_AES_IV_V2(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 31) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_AMSDU(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 30) +#define SET_TX_DESC_AMSDU_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30) +#define GET_TX_DESC_AMSDU(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 30) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_FTM_EN_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 30) +#define SET_TX_DESC_FTM_EN_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30) +#define GET_TX_DESC_FTM_EN_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 30) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_MOREDATA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 29) +#define SET_TX_DESC_MOREDATA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29) +#define GET_TX_DESC_MOREDATA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 29) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_HW_AES_IV_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 29) +#define SET_TX_DESC_HW_AES_IV_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29) +#define GET_TX_DESC_HW_AES_IV_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 29) +#define SET_TX_DESC_MHR_CP(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 25) +#define SET_TX_DESC_MHR_CP_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 25) +#define GET_TX_DESC_MHR_CP(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 25) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_MOREDATA(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 29) -#define SET_TX_DESC_MOREDATA_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 29) -#define GET_TX_DESC_MOREDATA(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 29) -#define SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 24) -#define SET_TX_DESC_PKT_OFFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 24) -#define GET_TX_DESC_PKT_OFFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1f, 24) -#define SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x3, 22) -#define SET_TX_DESC_SEC_TYPE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x3, 22) -#define GET_TX_DESC_SEC_TYPE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x3, 22) -#define SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 21) -#define SET_TX_DESC_EN_DESC_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 21) -#define GET_TX_DESC_EN_DESC_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 21) -#define SET_TX_DESC_RATE_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 16) -#define SET_TX_DESC_RATE_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 16) -#define GET_TX_DESC_RATE_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1f, 16) -#define SET_TX_DESC_PIFS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 15) -#define SET_TX_DESC_PIFS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 15) -#define GET_TX_DESC_PIFS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 15) -#define SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 14) -#define SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 14) -#define GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 14) -#define SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 13) -#define SET_TX_DESC_RD_NAV_EXT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 13) -#define GET_TX_DESC_RD_NAV_EXT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 13) -#define SET_TX_DESC_QSEL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 8) -#define SET_TX_DESC_QSEL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 8) -#define GET_TX_DESC_QSEL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1f, 8) -#define SET_TX_DESC_MACID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x7f, 0) -#define SET_TX_DESC_MACID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x7f, 0) -#define GET_TX_DESC_MACID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x7f, 0) +#define SET_TX_DESC_PKT_OFFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1f, 24) +#define SET_TX_DESC_PKT_OFFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 24) +#define GET_TX_DESC_PKT_OFFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \ + 24) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) +#define SET_TX_DESC_SMH_EN_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 24) +#define SET_TX_DESC_SMH_EN_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 24) +#define GET_TX_DESC_SMH_EN_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 24) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_SEC_TYPE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x3, 22) +#define SET_TX_DESC_SEC_TYPE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x3, 22) +#define GET_TX_DESC_SEC_TYPE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x3, \ + 22) +#define SET_TX_DESC_EN_DESC_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 21) +#define SET_TX_DESC_EN_DESC_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 21) +#define GET_TX_DESC_EN_DESC_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 21) +#define SET_TX_DESC_RATE_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1f, 16) +#define SET_TX_DESC_RATE_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 16) +#define GET_TX_DESC_RATE_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \ + 16) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_SMH_CAM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0xff, 16) +#define SET_TX_DESC_SMH_CAM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0xff, 16) +#define GET_TX_DESC_SMH_CAM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0xff, \ + 16) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_PIFS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 15) +#define SET_TX_DESC_PIFS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 15) +#define GET_TX_DESC_PIFS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 15) +#define SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 14) +#define SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 14) +#define GET_TX_DESC_LSIG_TXOP_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 14) +#define SET_TX_DESC_RD_NAV_EXT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 13) +#define SET_TX_DESC_RD_NAV_EXT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13) +#define GET_TX_DESC_RD_NAV_EXT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 13) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_EXT_EDCA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 13) +#define SET_TX_DESC_EXT_EDCA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13) +#define GET_TX_DESC_EXT_EDCA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 13) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_QSEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1f, 8) +#define SET_TX_DESC_QSEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 8) +#define GET_TX_DESC_QSEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \ + 8) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_SPECIAL_CW(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 7) +#define SET_TX_DESC_SPECIAL_CW_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 7) +#define GET_TX_DESC_SPECIAL_CW(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, 7) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_MACID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x7f, 0) +#define SET_TX_DESC_MACID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x7f, 0) +#define GET_TX_DESC_MACID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x7f, \ + 0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_MACID_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x7f, 0) +#define SET_TX_DESC_MACID_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x7f, 0) +#define GET_TX_DESC_MACID_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x7f, \ + 0) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /*TXDESC_WORD2*/ -#define SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 31) -#define SET_TX_DESC_HW_AES_IV_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 31) -#define GET_TX_DESC_HW_AES_IV(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 31) +#define SET_TX_DESC_HW_AES_IV(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 31) +#define SET_TX_DESC_HW_AES_IV_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31) +#define GET_TX_DESC_HW_AES_IV(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 31) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_CHK_EN_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 31) +#define SET_TX_DESC_CHK_EN_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31) +#define GET_TX_DESC_CHK_EN_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 31) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_FTM_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 30) +#define SET_TX_DESC_FTM_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 30) +#define GET_TX_DESC_FTM_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 30) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTCEL_D_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0xf, 28) +#define SET_TX_DESC_ANTCEL_D_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xf, 28) +#define GET_TX_DESC_ANTCEL_D_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xf, \ + 28) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_DMA_PRI(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 27) +#define SET_TX_DESC_DMA_PRI_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 27) +#define GET_TX_DESC_DMA_PRI(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 27) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_G_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x3f, 24) +#define SET_TX_DESC_G_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3f, 24) +#define GET_TX_DESC_G_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3f, \ + 24) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x7, 24) +#define SET_TX_DESC_MAX_AMSDU_MODE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 24) +#define GET_TX_DESC_MAX_AMSDU_MODE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7, \ + 24) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTSEL_C_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0xf, 24) +#define SET_TX_DESC_ANTSEL_C_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xf, 24) +#define GET_TX_DESC_ANTSEL_C_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xf, \ + 24) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_BT_NULL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 23) +#define SET_TX_DESC_BT_NULL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 23) +#define GET_TX_DESC_BT_NULL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 23) +#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x7, 20) +#define SET_TX_DESC_AMPDU_DENSITY_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 20) +#define GET_TX_DESC_AMPDU_DENSITY(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7, \ + 20) +#define SET_TX_DESC_SPE_RPT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 19) +#define SET_TX_DESC_SPE_RPT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 19) +#define GET_TX_DESC_SPE_RPT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 19) +#define SET_TX_DESC_RAW(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 18) +#define SET_TX_DESC_RAW_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 18) +#define GET_TX_DESC_RAW(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 18) +#define SET_TX_DESC_MOREFRAG(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 17) +#define SET_TX_DESC_MOREFRAG_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 17) +#define GET_TX_DESC_MOREFRAG(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 17) +#define SET_TX_DESC_BK(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 16) +#define SET_TX_DESC_BK_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 16) +#define GET_TX_DESC_BK(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 16) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_FTM_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 30) -#define SET_TX_DESC_FTM_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 30) -#define GET_TX_DESC_FTM_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 30) +#define SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0xff, 16) +#define SET_TX_DESC_DMA_TXAGG_NUM_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xff, 16) +#define GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xff, \ + 16) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_NULL_1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 15) +#define SET_TX_DESC_NULL_1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 15) +#define GET_TX_DESC_NULL_1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 15) +#define SET_TX_DESC_NULL_0(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 14) +#define SET_TX_DESC_NULL_0_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 14) +#define GET_TX_DESC_NULL_0(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 14) +#define SET_TX_DESC_RDG_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 13) +#define SET_TX_DESC_RDG_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 13) +#define GET_TX_DESC_RDG_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 13) +#define SET_TX_DESC_AGG_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 12) +#define SET_TX_DESC_AGG_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 12) +#define GET_TX_DESC_AGG_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 12) +#define SET_TX_DESC_CCA_RTS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x3, 10) +#define SET_TX_DESC_CCA_RTS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3, 10) +#define GET_TX_DESC_CCA_RTS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3, \ + 10) -#define SET_TX_DESC_G_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3f, 24) -#define SET_TX_DESC_G_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3f, 24) -#define GET_TX_DESC_G_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x3f, 24) -#define SET_TX_DESC_BT_NULL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 23) -#define SET_TX_DESC_BT_NULL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 23) -#define GET_TX_DESC_BT_NULL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 23) -#define SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x7, 20) -#define SET_TX_DESC_AMPDU_DENSITY_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x7, 20) -#define GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x7, 20) -#define SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 19) -#define SET_TX_DESC_SPE_RPT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 19) -#define GET_TX_DESC_SPE_RPT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 19) -#define SET_TX_DESC_RAW(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 18) -#define SET_TX_DESC_RAW_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 18) -#define GET_TX_DESC_RAW(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 18) -#define SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 17) -#define SET_TX_DESC_MOREFRAG_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 17) -#define GET_TX_DESC_MOREFRAG(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 17) -#define SET_TX_DESC_BK(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 16) -#define SET_TX_DESC_BK_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 16) -#define GET_TX_DESC_BK(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 16) -#define SET_TX_DESC_NULL_1(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 15) -#define SET_TX_DESC_NULL_1_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 15) -#define GET_TX_DESC_NULL_1(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 15) -#define SET_TX_DESC_NULL_0(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 14) -#define SET_TX_DESC_NULL_0_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 14) -#define GET_TX_DESC_NULL_0(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 14) -#define SET_TX_DESC_RDG_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 13) -#define SET_TX_DESC_RDG_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 13) -#define GET_TX_DESC_RDG_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 13) -#define SET_TX_DESC_AGG_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 12) -#define SET_TX_DESC_AGG_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 12) -#define GET_TX_DESC_AGG_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 12) -#define SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3, 10) -#define SET_TX_DESC_CCA_RTS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3, 10) -#define GET_TX_DESC_CCA_RTS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x3, 10) +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_TRI_FRAME(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 9) +#define SET_TX_DESC_TRI_FRAME_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 9) +#define GET_TX_DESC_TRI_FRAME(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, 9) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 9) -#define SET_TX_DESC_TRI_FRAME_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 9) -#define GET_TX_DESC_TRI_FRAME(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 9) +#define SET_TX_DESC_P_AID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1ff, 0) +#define SET_TX_DESC_P_AID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1ff, 0) +#define GET_TX_DESC_P_AID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, \ + 0x1ff, 0) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0xffff, 0) +#define SET_TX_DESC_TXDESC_CHECKSUM_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xffff, 0) +#define GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, \ + 0xffff, 0) + +#endif -#define SET_TX_DESC_P_AID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1ff, 0) -#define SET_TX_DESC_P_AID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1ff, 0) -#define GET_TX_DESC_P_AID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1ff, 0) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0xff, 24) -#define SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0xff, 24) -#define GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0xff, 24) -#define SET_TX_DESC_NDPA(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 22) -#define SET_TX_DESC_NDPA_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 22) -#define GET_TX_DESC_NDPA(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x3, 22) -#define SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 17) -#define SET_TX_DESC_MAX_AGG_NUM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 17) -#define GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1f, 17) -#define SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 16) -#define SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 16) -#define GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 16) -#define SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 15) -#define SET_TX_DESC_NAVUSEHDR_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 15) -#define GET_TX_DESC_NAVUSEHDR(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 15) +#define SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0xff, 24) +#define SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0xff, 24) +#define GET_TX_DESC_AMPDU_MAX_TIME(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0xff, \ + 24) +#define SET_TX_DESC_NDPA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x3, 22) +#define SET_TX_DESC_NDPA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x3, 22) +#define GET_TX_DESC_NDPA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x3, \ + 22) +#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1f, 17) +#define SET_TX_DESC_MAX_AGG_NUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 17) +#define GET_TX_DESC_MAX_AGG_NUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \ + 17) +#define SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 16) +#define SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 16) +#define GET_TX_DESC_USE_MAX_TIME_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 16) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_CHK_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 14) -#define SET_TX_DESC_CHK_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 14) -#define GET_TX_DESC_CHK_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 14) +#define SET_TX_DESC_OFFLOAD_SIZE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x7fff, 16) +#define SET_TX_DESC_OFFLOAD_SIZE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7fff, 16) +#define GET_TX_DESC_OFFLOAD_SIZE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, \ + 0x7fff, 16) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 15) +#define SET_TX_DESC_NAVUSEHDR_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 15) +#define GET_TX_DESC_NAVUSEHDR(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 15) +#define SET_TX_DESC_CHK_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 14) +#define SET_TX_DESC_CHK_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 14) +#define GET_TX_DESC_CHK_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 14) +#define SET_TX_DESC_HW_RTS_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 13) +#define SET_TX_DESC_HW_RTS_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 13) +#define GET_TX_DESC_HW_RTS_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 13) +#define SET_TX_DESC_RTSEN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 12) +#define SET_TX_DESC_RTSEN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 12) +#define GET_TX_DESC_RTSEN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 12) +#define SET_TX_DESC_CTS2SELF(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 11) +#define SET_TX_DESC_CTS2SELF_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 11) +#define GET_TX_DESC_CTS2SELF(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 11) + +#endif -#define SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 13) -#define SET_TX_DESC_HW_RTS_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 13) -#define GET_TX_DESC_HW_RTS_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 13) -#define SET_TX_DESC_RTSEN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 12) -#define SET_TX_DESC_RTSEN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 12) -#define GET_TX_DESC_RTSEN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 12) -#define SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 11) -#define SET_TX_DESC_CTS2SELF_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 11) -#define GET_TX_DESC_CTS2SELF(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 11) -#define SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 10) -#define SET_TX_DESC_DISDATAFB_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 10) -#define GET_TX_DESC_DISDATAFB(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 10) -#define SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 9) -#define SET_TX_DESC_DISRTSFB_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 9) -#define GET_TX_DESC_DISRTSFB(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 9) -#define SET_TX_DESC_USE_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 8) -#define SET_TX_DESC_USE_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 8) -#define GET_TX_DESC_USE_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 8) -#define SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 6) -#define SET_TX_DESC_HW_SSN_SEL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 6) -#define GET_TX_DESC_HW_SSN_SEL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x3, 6) +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_CHANNEL_DMA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1f, 11) +#define SET_TX_DESC_CHANNEL_DMA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 11) +#define GET_TX_DESC_CHANNEL_DMA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \ + 11) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_DISDATAFB(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 10) +#define SET_TX_DESC_DISDATAFB_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 10) +#define GET_TX_DESC_DISDATAFB(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 10) +#define SET_TX_DESC_DISRTSFB(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 9) +#define SET_TX_DESC_DISRTSFB_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 9) +#define GET_TX_DESC_DISRTSFB(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 9) +#define SET_TX_DESC_USE_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 8) +#define SET_TX_DESC_USE_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 8) +#define GET_TX_DESC_USE_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 8) +#define SET_TX_DESC_HW_SSN_SEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x3, 6) +#define SET_TX_DESC_HW_SSN_SEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x3, 6) +#define GET_TX_DESC_HW_SSN_SEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x3, 6) + +#endif -#define SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 0) -#define SET_TX_DESC_WHEADER_LEN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 0) -#define GET_TX_DESC_WHEADER_LEN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1f, 0) +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_IE_CNT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x7, 6) +#define SET_TX_DESC_IE_CNT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7, 6) +#define GET_TX_DESC_IE_CNT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x7, 6) +#define SET_TX_DESC_IE_CNT_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 5) +#define SET_TX_DESC_IE_CNT_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 5) +#define GET_TX_DESC_IE_CNT_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 5) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) +#define SET_TX_DESC_WHEADER_LEN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1f, 0) +#define SET_TX_DESC_WHEADER_LEN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0) +#define GET_TX_DESC_WHEADER_LEN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \ + 0) -/*TXDESC_WORD4*/ +#endif -#define SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3, 30) -#define SET_TX_DESC_PCTS_MASK_IDX_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3, 30) -#define GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x3, 30) -#define SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 29) -#define SET_TX_DESC_PCTS_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 29) -#define GET_TX_DESC_PCTS_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1, 29) -#define SET_TX_DESC_RTSRATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 24) -#define SET_TX_DESC_RTSRATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 24) -#define GET_TX_DESC_RTSRATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1f, 24) -#define SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3f, 18) -#define SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3f, 18) -#define GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x3f, 18) -#define SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 17) -#define SET_TX_DESC_RTY_LMT_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 17) -#define GET_TX_DESC_RTY_LMT_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1, 17) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0xf, 13) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0xf, 13) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0xf, 13) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 8) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 8) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1f, 8) -#define SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 7) -#define SET_TX_DESC_TRY_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 7) -#define GET_TX_DESC_TRY_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1, 7) -#define SET_TX_DESC_DATARATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x7f, 0) -#define SET_TX_DESC_DATARATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x7f, 0) -#define GET_TX_DESC_DATARATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x7f, 0) - -#endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) +#define SET_TX_DESC_WHEADER_LEN_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1f, 0) +#define SET_TX_DESC_WHEADER_LEN_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0) +#define GET_TX_DESC_WHEADER_LEN_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \ + 0) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x3, 30) +#define SET_TX_DESC_PCTS_MASK_IDX_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3, 30) +#define GET_TX_DESC_PCTS_MASK_IDX(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3, \ + 30) +#define SET_TX_DESC_PCTS_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1, 29) +#define SET_TX_DESC_PCTS_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 29) +#define GET_TX_DESC_PCTS_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \ + 29) +#define SET_TX_DESC_RTSRATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1f, 24) +#define SET_TX_DESC_RTSRATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1f, 24) +#define GET_TX_DESC_RTSRATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1f, \ + 24) +#define SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x3f, 18) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3f, 18) +#define GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3f, \ + 18) +#define SET_TX_DESC_RTY_LMT_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1, 17) +#define SET_TX_DESC_RTY_LMT_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 17) +#define GET_TX_DESC_RTY_LMT_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \ + 17) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0xf, 13) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0xf, 13) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0xf, \ + 13) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1f, 8) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1f, 8) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1f, \ + 8) +#define SET_TX_DESC_TRY_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1, 7) +#define SET_TX_DESC_TRY_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 7) +#define GET_TX_DESC_TRY_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, 7) +#define SET_TX_DESC_DATARATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x7f, 0) +#define SET_TX_DESC_DATARATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7f, 0) +#define GET_TX_DESC_DATARATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x7f, \ + 0) /*TXDESC_WORD5*/ -#define SET_TX_DESC_POLLUTED(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 31) -#define SET_TX_DESC_POLLUTED_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 31) -#define GET_TX_DESC_POLLUTED(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 31) +#define SET_TX_DESC_POLLUTED(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 31) +#define SET_TX_DESC_POLLUTED_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 31) +#define GET_TX_DESC_POLLUTED(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 31) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 30) +#define SET_TX_DESC_ANTSEL_EN_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 30) +#define GET_TX_DESC_ANTSEL_EN_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 30) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 28) -#define SET_TX_DESC_TXPWR_OFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 28) -#define GET_TX_DESC_TXPWR_OFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x7, 28) -#define SET_TX_DESC_TX_ANT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 24) -#define SET_TX_DESC_TX_ANT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 24) -#define GET_TX_DESC_TX_ANT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0xf, 24) -#define SET_TX_DESC_PORT_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 21) -#define SET_TX_DESC_PORT_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 21) -#define GET_TX_DESC_PORT_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x7, 21) +#define SET_TX_DESC_TXPWR_OFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x7, 28) +#define SET_TX_DESC_TXPWR_OFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 28) +#define GET_TX_DESC_TXPWR_OFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7, \ + 28) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 18) -#define SET_TX_DESC_MULTIPLE_PORT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 18) -#define GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x7, 18) +#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3, 28) +#define SET_TX_DESC_TXPWR_OFSET_TYPE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 28) +#define GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, \ + 28) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 17) -#define SET_TX_DESC_SIGNALING_TAPKT_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 17) -#define GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 17) +#define SET_TX_DESC_TX_ANT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0xf, 24) +#define SET_TX_DESC_TX_ANT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 24) +#define GET_TX_DESC_TX_ANT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, \ + 24) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_RTS_SC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 13) -#define SET_TX_DESC_RTS_SC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 13) -#define GET_TX_DESC_RTS_SC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0xf, 13) -#define SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 12) -#define SET_TX_DESC_RTS_SHORT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 12) -#define GET_TX_DESC_RTS_SHORT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 12) +#define SET_TX_DESC_DROP_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3, 24) +#define SET_TX_DESC_DROP_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 24) +#define GET_TX_DESC_DROP_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, \ + 24) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10) -#define SET_TX_DESC_VCS_STBC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10) -#define GET_TX_DESC_VCS_STBC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 10) +#define SET_TX_DESC_PORT_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x7, 21) +#define SET_TX_DESC_PORT_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 21) +#define GET_TX_DESC_PORT_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7, \ + 21) #endif -#if (HALMAC_8188F_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_RTS_STBC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10) -#define SET_TX_DESC_RTS_STBC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10) -#define GET_TX_DESC_RTS_STBC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 10) +#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x7, 18) +#define SET_TX_DESC_MULTIPLE_PORT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 18) +#define GET_TX_DESC_MULTIPLE_PORT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7, \ + 18) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 8) -#define SET_TX_DESC_DATA_STBC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 8) -#define GET_TX_DESC_DATA_STBC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 8) +#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 17) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 17) +#define GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 17) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 7) -#define SET_TX_DESC_DATA_LDPC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 7) -#define GET_TX_DESC_DATA_LDPC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 7) +#define SET_TX_DESC_RTS_SC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0xf, 13) +#define SET_TX_DESC_RTS_SC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 13) +#define GET_TX_DESC_RTS_SC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, \ + 13) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_DATA_BW(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 5) -#define SET_TX_DESC_DATA_BW_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 5) -#define GET_TX_DESC_DATA_BW(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 5) -#define SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 4) -#define SET_TX_DESC_DATA_SHORT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 4) -#define GET_TX_DESC_DATA_SHORT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 4) -#define SET_TX_DESC_DATA_SC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 0) -#define SET_TX_DESC_DATA_SC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 0) -#define GET_TX_DESC_DATA_SC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0xf, 0) +#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0xf, 13) +#define SET_TX_DESC_SIGNALING_TA_PKT_SC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 13) +#define GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, \ + 13) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_RTS_SHORT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 12) +#define SET_TX_DESC_RTS_SHORT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 12) +#define GET_TX_DESC_RTS_SHORT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 12) +#define SET_TX_DESC_VCS_STBC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3, 10) +#define SET_TX_DESC_VCS_STBC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 10) +#define GET_TX_DESC_VCS_STBC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, \ + 10) +#define SET_TX_DESC_DATA_STBC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3, 8) +#define SET_TX_DESC_DATA_STBC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 8) +#define GET_TX_DESC_DATA_STBC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 8) +#define SET_TX_DESC_DATA_LDPC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 7) +#define SET_TX_DESC_DATA_LDPC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 7) +#define GET_TX_DESC_DATA_LDPC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 7) +#define SET_TX_DESC_DATA_BW(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3, 5) +#define SET_TX_DESC_DATA_BW_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 5) +#define GET_TX_DESC_DATA_BW(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 5) +#define SET_TX_DESC_DATA_SHORT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 4) +#define SET_TX_DESC_DATA_SHORT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 4) +#define GET_TX_DESC_DATA_SHORT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 4) +#define SET_TX_DESC_DATA_SC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0xf, 0) +#define SET_TX_DESC_DATA_SC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 0) +#define GET_TX_DESC_DATA_SC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, 0) + +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 30) -#define SET_TX_DESC_ANTSEL_D_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 30) -#define GET_TX_DESC_ANTSEL_D(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 30) -#define SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 28) -#define SET_TX_DESC_ANT_MAPD_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 28) -#define GET_TX_DESC_ANT_MAPD(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 28) -#define SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 26) -#define SET_TX_DESC_ANT_MAPC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 26) -#define GET_TX_DESC_ANT_MAPC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 26) -#define SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 24) -#define SET_TX_DESC_ANT_MAPB_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 24) -#define GET_TX_DESC_ANT_MAPB(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 24) -#define SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 22) -#define SET_TX_DESC_ANT_MAPA_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 22) -#define GET_TX_DESC_ANT_MAPA(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 22) -#define SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 20) -#define SET_TX_DESC_ANTSEL_C_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 20) -#define GET_TX_DESC_ANTSEL_C(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 20) -#define SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 18) -#define SET_TX_DESC_ANTSEL_B_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 18) -#define GET_TX_DESC_ANTSEL_B(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 18) - -#endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) - -#define SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 16) -#define SET_TX_DESC_ANTSEL_A_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 16) -#define GET_TX_DESC_ANTSEL_A(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 16) -#define SET_TX_DESC_MBSSID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xf, 12) -#define SET_TX_DESC_MBSSID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xf, 12) -#define GET_TX_DESC_MBSSID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0xf, 12) -#define SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xfff, 0) -#define SET_TX_DESC_SW_DEFINE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xfff, 0) -#define GET_TX_DESC_SW_DEFINE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0xfff, 0) +#define SET_TX_DESC_ANTSEL_D(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 30) +#define SET_TX_DESC_ANTSEL_D_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30) +#define GET_TX_DESC_ANTSEL_D(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 30) -/*TXDESC_WORD7*/ +#endif + +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24) -#define SET_TX_DESC_DMA_TXAGG_NUM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24) -#define GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xff, 24) +#define SET_TX_DESC_ANT_MAPD_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 30) +#define SET_TX_DESC_ANT_MAPD_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30) +#define GET_TX_DESC_ANT_MAPD_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 30) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24) -#define SET_TX_DESC_FINAL_DATA_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24) -#define GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xff, 24) -#define SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xf, 20) -#define SET_TX_DESC_NTX_MAP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xf, 20) -#define GET_TX_DESC_NTX_MAP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xf, 20) +#define SET_TX_DESC_ANT_MAPD(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 28) +#define SET_TX_DESC_ANT_MAPD_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28) +#define GET_TX_DESC_ANT_MAPD(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 28) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) -#define SET_TX_DESC_TX_BUFF_SIZE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) -#define GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xffff, 0) -#define SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) -#define SET_TX_DESC_TXDESC_CHECKSUM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) -#define GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xffff, 0) -#define SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) -#define SET_TX_DESC_TIMESTAMP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) -#define GET_TX_DESC_TIMESTAMP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xffff, 0) +#define SET_TX_DESC_ANT_MAPC_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 28) +#define SET_TX_DESC_ANT_MAPC_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28) +#define GET_TX_DESC_ANT_MAPC_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 28) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +#define SET_TX_DESC_ANT_MAPC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 26) +#define SET_TX_DESC_ANT_MAPC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26) +#define GET_TX_DESC_ANT_MAPC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 26) -/*TXDESC_WORD8*/ +#endif -#define SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 31) -#define SET_TX_DESC_TXWIFI_CP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 31) -#define GET_TX_DESC_TXWIFI_CP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 31) -#define SET_TX_DESC_MAC_CP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 30) -#define SET_TX_DESC_MAC_CP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 30) -#define GET_TX_DESC_MAC_CP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 30) -#define SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 29) -#define SET_TX_DESC_STW_PKTRE_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 29) -#define GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 29) -#define SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 28) -#define SET_TX_DESC_STW_RB_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 28) -#define GET_TX_DESC_STW_RB_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 28) -#define SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 27) -#define SET_TX_DESC_STW_RATE_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 27) -#define GET_TX_DESC_STW_RATE_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 27) -#define SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 26) -#define SET_TX_DESC_STW_ANT_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 26) -#define GET_TX_DESC_STW_ANT_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 26) -#define SET_TX_DESC_STW_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 25) -#define SET_TX_DESC_STW_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 25) -#define GET_TX_DESC_STW_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 25) -#define SET_TX_DESC_SMH_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 24) -#define SET_TX_DESC_SMH_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 24) -#define GET_TX_DESC_SMH_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 24) +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANT_MAPB_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 26) +#define SET_TX_DESC_ANT_MAPB_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26) +#define GET_TX_DESC_ANT_MAPB_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 26) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 24) -#define SET_TX_DESC_TAILPAGE_L_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 24) -#define GET_TX_DESC_TAILPAGE_L(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0xff, 24) +#define SET_TX_DESC_ANT_MAPB(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 24) +#define SET_TX_DESC_ANT_MAPB_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24) +#define GET_TX_DESC_ANT_MAPB(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 24) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16) -#define SET_TX_DESC_SDIO_DMASEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16) -#define GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0xff, 16) +#define SET_TX_DESC_ANT_MAPA_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 24) +#define SET_TX_DESC_ANT_MAPA_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24) +#define GET_TX_DESC_ANT_MAPA_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 24) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_ANT_MAPA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 22) +#define SET_TX_DESC_ANT_MAPA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 22) +#define GET_TX_DESC_ANT_MAPA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 22) +#define SET_TX_DESC_ANTSEL_C(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 20) +#define SET_TX_DESC_ANTSEL_C_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 20) +#define GET_TX_DESC_ANTSEL_C(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 20) + +#endif -#define SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16) -#define SET_TX_DESC_NEXTHEADPAGE_L_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16) -#define GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0xff, 16) -#define SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 15) -#define SET_TX_DESC_EN_HWSEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 15) -#define GET_TX_DESC_EN_HWSEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 15) +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTSEL_B_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0xf, 20) +#define SET_TX_DESC_ANTSEL_B_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 20) +#define GET_TX_DESC_ANTSEL_B_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf, \ + 20) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_ANTSEL_B(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 18) +#define SET_TX_DESC_ANTSEL_B_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 18) +#define GET_TX_DESC_ANTSEL_B(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 18) +#define SET_TX_DESC_ANTSEL_A(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 16) +#define SET_TX_DESC_ANTSEL_A_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 16) +#define GET_TX_DESC_ANTSEL_A(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 16) -#define SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 14) -#define SET_TX_DESC_EN_HWEXSEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 14) -#define GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 14) +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTSEL_A_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0xf, 16) +#define SET_TX_DESC_ANTSEL_A_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 16) +#define GET_TX_DESC_ANTSEL_A_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf, \ + 16) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_DATA_RC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 8) -#define SET_TX_DESC_DATA_RC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 8) -#define GET_TX_DESC_DATA_RC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x3f, 8) -#define SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3, 6) -#define SET_TX_DESC_BAR_RTY_TH_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3, 6) -#define GET_TX_DESC_BAR_RTY_TH(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x3, 6) -#define SET_TX_DESC_RTS_RC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 0) -#define SET_TX_DESC_RTS_RC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 0) -#define GET_TX_DESC_RTS_RC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x3f, 0) +#define SET_TX_DESC_MBSSID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0xf, 12) +#define SET_TX_DESC_MBSSID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 12) +#define GET_TX_DESC_MBSSID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf, \ + 12) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +#define SET_TX_DESC_SW_DEFINE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0xfff, 0) +#define SET_TX_DESC_SW_DEFINE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xfff, 0) +#define GET_TX_DESC_SW_DEFINE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, \ + 0xfff, 0) -/*TXDESC_WORD9*/ +#endif + +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 28) -#define SET_TX_DESC_TAILPAGE_H_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 28) -#define GET_TX_DESC_TAILPAGE_H(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xf, 28) -#define SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 24) -#define SET_TX_DESC_NEXTHEADPAGE_H_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 24) -#define GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xf, 24) +#define SET_TX_DESC_SWPS_SEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0xfff, 0) +#define SET_TX_DESC_SWPS_SEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xfff, 0) +#define GET_TX_DESC_SWPS_SEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, \ + 0xfff, 0) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xfff, 12) -#define SET_TX_DESC_SW_SEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xfff, 12) -#define GET_TX_DESC_SW_SEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xfff, 12) -#define SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x1, 11) -#define SET_TX_DESC_TXBF_PATH_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x1, 11) -#define GET_TX_DESC_TXBF_PATH(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0x1, 11) -#define SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x7ff, 0) -#define SET_TX_DESC_PADDING_LEN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x7ff, 0) -#define GET_TX_DESC_PADDING_LEN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0x7ff, 0) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xff, 0) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xff, 0) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xff, 0) +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xff, 24) +#define SET_TX_DESC_DMA_TXAGG_NUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xff, 24) +#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \ + 24) +#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xff, 24) +#define SET_TX_DESC_FINAL_DATA_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xff, 24) +#define GET_TX_DESC_FINAL_DATA_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \ + 24) +#define SET_TX_DESC_NTX_MAP(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xf, 20) +#define SET_TX_DESC_NTX_MAP_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xf, 20) +#define GET_TX_DESC_NTX_MAP(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xf, \ + 20) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTSEL_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0x1, 19) +#define SET_TX_DESC_ANTSEL_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 19) +#define GET_TX_DESC_ANTSEL_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1, \ + 19) +#define SET_TX_DESC_MBSSID_EX(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0x7, 16) +#define SET_TX_DESC_MBSSID_EX_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0x7, 16) +#define GET_TX_DESC_MBSSID_EX(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x7, \ + 16) +#endif -/*WORD10*/ +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xffff, 0) +#define SET_TX_DESC_TX_BUFF_SIZE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0) +#define GET_TX_DESC_TX_BUFF_SIZE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \ + 0xffff, 0) +#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xffff, 0) +#define SET_TX_DESC_TXDESC_CHECKSUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0) +#define GET_TX_DESC_TXDESC_CHECKSUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \ + 0xffff, 0) +#define SET_TX_DESC_TIMESTAMP(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xffff, 0) +#define SET_TX_DESC_TIMESTAMP_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0) +#define GET_TX_DESC_TIMESTAMP(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \ + 0xffff, 0) -#define SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xff, 8) -#define SET_TX_DESC_MU_DATARATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xff, 8) -#define GET_TX_DESC_MU_DATARATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, 0xff, 8) -#define SET_TX_DESC_MU_RC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xf, 4) -#define SET_TX_DESC_MU_RC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xf, 4) -#define GET_TX_DESC_MU_RC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, 0xf, 4) -#define SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0x3, 0) -#define SET_TX_DESC_SND_PKT_SEL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0x3, 0) -#define GET_TX_DESC_SND_PKT_SEL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, 0x3, 0) +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_TXWIFI_CP(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 31) +#define SET_TX_DESC_TXWIFI_CP_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 31) +#define GET_TX_DESC_TXWIFI_CP(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 31) +#define SET_TX_DESC_MAC_CP(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 30) +#define SET_TX_DESC_MAC_CP_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 30) +#define GET_TX_DESC_MAC_CP(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 30) +#define SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 29) +#define SET_TX_DESC_STW_PKTRE_DIS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 29) +#define GET_TX_DESC_STW_PKTRE_DIS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 29) +#define SET_TX_DESC_STW_RB_DIS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 28) +#define SET_TX_DESC_STW_RB_DIS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 28) +#define GET_TX_DESC_STW_RB_DIS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 28) +#define SET_TX_DESC_STW_RATE_DIS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 27) +#define SET_TX_DESC_STW_RATE_DIS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 27) +#define GET_TX_DESC_STW_RATE_DIS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 27) +#define SET_TX_DESC_STW_ANT_DIS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 26) +#define SET_TX_DESC_STW_ANT_DIS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 26) +#define GET_TX_DESC_STW_ANT_DIS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 26) +#define SET_TX_DESC_STW_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 25) +#define SET_TX_DESC_STW_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 25) +#define GET_TX_DESC_STW_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 25) +#define SET_TX_DESC_SMH_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 24) +#define SET_TX_DESC_SMH_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 24) +#define GET_TX_DESC_SMH_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 24) +#define SET_TX_DESC_TAILPAGE_L(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xff, 24) +#define SET_TX_DESC_TAILPAGE_L_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 24) +#define GET_TX_DESC_TAILPAGE_L(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \ + 24) +#define SET_TX_DESC_SDIO_DMASEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xff, 16) +#define SET_TX_DESC_SDIO_DMASEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 16) +#define GET_TX_DESC_SDIO_DMASEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \ + 16) +#define SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xff, 16) +#define SET_TX_DESC_NEXTHEADPAGE_L_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 16) +#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \ + 16) +#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 15) +#define SET_TX_DESC_EN_HWSEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 15) +#define GET_TX_DESC_EN_HWSEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 15) +#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 14) +#define SET_TX_DESC_EN_HWEXSEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 14) +#define GET_TX_DESC_EN_HWEXSEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 14) +#define SET_TX_DESC_DATA_RC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3f, 8) +#define SET_TX_DESC_DATA_RC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3f, 8) +#define GET_TX_DESC_DATA_RC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3f, \ + 8) +#define SET_TX_DESC_BAR_RTY_TH(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3, 6) +#define SET_TX_DESC_BAR_RTY_TH_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 6) +#define GET_TX_DESC_BAR_RTY_TH(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, 6) +#define SET_TX_DESC_RTS_RC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3f, 0) +#define SET_TX_DESC_RTS_RC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3f, 0) +#define GET_TX_DESC_RTS_RC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3f, \ + 0) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_TAILPAGE_H(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0xf, 28) +#define SET_TX_DESC_TAILPAGE_H_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 28) +#define GET_TX_DESC_TAILPAGE_H(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf, \ + 28) +#define SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0xf, 24) +#define SET_TX_DESC_NEXTHEADPAGE_H_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 24) +#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf, \ + 24) +#define SET_TX_DESC_SW_SEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0xfff, 12) +#define SET_TX_DESC_SW_SEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xfff, 12) +#define GET_TX_DESC_SW_SEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, \ + 0xfff, 12) +#define SET_TX_DESC_TXBF_PATH(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 11) +#define SET_TX_DESC_TXBF_PATH_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 11) +#define GET_TX_DESC_TXBF_PATH(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \ + 11) +#define SET_TX_DESC_PADDING_LEN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x7ff, 0) +#define SET_TX_DESC_PADDING_LEN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x7ff, 0) +#define GET_TX_DESC_PADDING_LEN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, \ + 0x7ff, 0) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0xff, 0) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 0) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \ + 0) #endif +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/*WORD10*/ + +#define SET_TX_DESC_MU_DATARATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0xff, 8) +#define SET_TX_DESC_MU_DATARATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 8) +#define GET_TX_DESC_MU_DATARATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \ + 0xff, 8) +#define SET_TX_DESC_MU_RC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0xf, 4) +#define SET_TX_DESC_MU_RC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0xf, 4) +#define GET_TX_DESC_MU_RC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0xf, \ + 4) +#define SET_TX_DESC_SND_PKT_SEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x3, 0) +#define SET_TX_DESC_SND_PKT_SEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3, 0) +#define GET_TX_DESC_SND_PKT_SEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x3, \ + 0) + +#endif #endif diff --git a/hal/halmac/halmac_tx_desc_chip.h b/hal/halmac/halmac_tx_desc_chip.h index e778594..514b187 100644 --- a/hal/halmac/halmac_tx_desc_chip.h +++ b/hal/halmac/halmac_tx_desc_chip.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -19,515 +19,741 @@ /*TXDESC_WORD0*/ -#define SET_TX_DESC_DISQSELSEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_DISQSELSEQ_8814A(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc) -#define SET_TX_DESC_GF_8814A(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value) -#define GET_TX_DESC_GF_8814A(__pTxDesc) GET_TX_DESC_GF(__pTxDesc) -#define SET_TX_DESC_NO_ACM_8814A(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value) -#define GET_TX_DESC_NO_ACM_8814A(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc) -#define SET_TX_DESC_AMSDU_PAD_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AMSDU_PAD_EN_8814A(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) -#define SET_TX_DESC_LS_8814A(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value) -#define GET_TX_DESC_LS_8814A(__pTxDesc) GET_TX_DESC_LS(__pTxDesc) -#define SET_TX_DESC_HTC_8814A(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value) -#define GET_TX_DESC_HTC_8814A(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc) -#define SET_TX_DESC_BMC_8814A(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value) -#define GET_TX_DESC_BMC_8814A(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc) -#define SET_TX_DESC_OFFSET_8814A(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_OFFSET_8814A(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc) -#define SET_TX_DESC_TXPKTSIZE_8814A(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TXPKTSIZE_8814A(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc) - -/*TXDESC_WORD1*/ - -#define SET_TX_DESC_MOREDATA_8814A(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value) -#define GET_TX_DESC_MOREDATA_8814A(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc) -#define SET_TX_DESC_PKT_OFFSET_8814A(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_PKT_OFFSET_8814A(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc) -#define SET_TX_DESC_SEC_TYPE_8814A(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) -#define GET_TX_DESC_SEC_TYPE_8814A(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc) -#define SET_TX_DESC_EN_DESC_ID_8814A(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) -#define GET_TX_DESC_EN_DESC_ID_8814A(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc) -#define SET_TX_DESC_RATE_ID_8814A(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value) -#define GET_TX_DESC_RATE_ID_8814A(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc) -#define SET_TX_DESC_PIFS_8814A(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value) -#define GET_TX_DESC_PIFS_8814A(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc) -#define SET_TX_DESC_LSIG_TXOP_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) -#define GET_TX_DESC_LSIG_TXOP_EN_8814A(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) -#define SET_TX_DESC_RD_NAV_EXT_8814A(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) -#define GET_TX_DESC_RD_NAV_EXT_8814A(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc) -#define SET_TX_DESC_QSEL_8814A(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value) -#define GET_TX_DESC_QSEL_8814A(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc) -#define SET_TX_DESC_MACID_8814A(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value) -#define GET_TX_DESC_MACID_8814A(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc) +#define SET_TX_DESC_DISQSELSEQ_8814A(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8814A(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8814A(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8814A(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8814A(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8814A(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8814A(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8814A(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8814A(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8814A(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8814A(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8814A(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8814A(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8814A(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8814A(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8814A(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8814A(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8814A(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_MOREDATA_8814A(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8814A(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8814A(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8814A(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8814A(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8814A(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8814A(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8814A(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8814A(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8814A(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8814A(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8814A(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8814A(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8814A(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8814A(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8814A(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8814A(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8814A(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8814A(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8814A(txdesc) GET_TX_DESC_MACID(txdesc) /*TXDESC_WORD2*/ -#define SET_TX_DESC_HW_AES_IV_8814A(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) -#define GET_TX_DESC_HW_AES_IV_8814A(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc) -#define SET_TX_DESC_G_ID_8814A(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value) -#define GET_TX_DESC_G_ID_8814A(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc) -#define SET_TX_DESC_BT_NULL_8814A(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value) -#define GET_TX_DESC_BT_NULL_8814A(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc) -#define SET_TX_DESC_AMPDU_DENSITY_8814A(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_DENSITY_8814A(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) -#define SET_TX_DESC_SPE_RPT_8814A(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) -#define GET_TX_DESC_SPE_RPT_8814A(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc) -#define SET_TX_DESC_RAW_8814A(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value) -#define GET_TX_DESC_RAW_8814A(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc) -#define SET_TX_DESC_MOREFRAG_8814A(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) -#define GET_TX_DESC_MOREFRAG_8814A(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc) -#define SET_TX_DESC_BK_8814A(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value) -#define GET_TX_DESC_BK_8814A(__pTxDesc) GET_TX_DESC_BK(__pTxDesc) -#define SET_TX_DESC_NULL_1_8814A(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_1_8814A(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc) -#define SET_TX_DESC_NULL_0_8814A(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_0_8814A(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc) -#define SET_TX_DESC_RDG_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RDG_EN_8814A(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc) -#define SET_TX_DESC_AGG_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AGG_EN_8814A(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc) -#define SET_TX_DESC_CCA_RTS_8814A(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) -#define GET_TX_DESC_CCA_RTS_8814A(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc) -#define SET_TX_DESC_P_AID_8814A(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value) -#define GET_TX_DESC_P_AID_8814A(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc) +#define SET_TX_DESC_HW_AES_IV_8814A(txdesc, value) \ + SET_TX_DESC_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8814A(txdesc) GET_TX_DESC_HW_AES_IV(txdesc) +#define SET_TX_DESC_G_ID_8814A(txdesc, value) SET_TX_DESC_G_ID(txdesc, value) +#define GET_TX_DESC_G_ID_8814A(txdesc) GET_TX_DESC_G_ID(txdesc) +#define SET_TX_DESC_BT_NULL_8814A(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8814A(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8814A(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8814A(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8814A(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8814A(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8814A(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8814A(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8814A(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8814A(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8814A(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8814A(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8814A(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8814A(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8814A(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8814A(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8814A(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8814A(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8814A(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8814A(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8814A(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8814A(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_P_AID_8814A(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8814A(txdesc) GET_TX_DESC_P_AID(txdesc) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_MAX_TIME_8814A(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) -#define SET_TX_DESC_NDPA_8814A(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value) -#define GET_TX_DESC_NDPA_8814A(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc) -#define SET_TX_DESC_MAX_AGG_NUM_8814A(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_MAX_AGG_NUM_8814A(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) -#define SET_TX_DESC_USE_MAX_TIME_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) -#define GET_TX_DESC_USE_MAX_TIME_EN_8814A(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) -#define SET_TX_DESC_NAVUSEHDR_8814A(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) -#define GET_TX_DESC_NAVUSEHDR_8814A(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc) -#define SET_TX_DESC_CHK_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value) -#define GET_TX_DESC_CHK_EN_8814A(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc) -#define SET_TX_DESC_HW_RTS_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_HW_RTS_EN_8814A(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSEN_8814A(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value) -#define GET_TX_DESC_RTSEN_8814A(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc) -#define SET_TX_DESC_CTS2SELF_8814A(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) -#define GET_TX_DESC_CTS2SELF_8814A(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc) -#define SET_TX_DESC_DISDATAFB_8814A(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISDATAFB_8814A(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc) -#define SET_TX_DESC_DISRTSFB_8814A(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISRTSFB_8814A(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc) -#define SET_TX_DESC_USE_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_USE_RATE_8814A(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc) -#define SET_TX_DESC_HW_SSN_SEL_8814A(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_HW_SSN_SEL_8814A(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc) -#define SET_TX_DESC_WHEADER_LEN_8814A(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_WHEADER_LEN_8814A(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc) +#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8814A(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8814A(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8814A(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8814A(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8814A(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8814A(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8814A(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8814A(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8814A(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8814A(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8814A(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8814A(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8814A(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8814A(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8814A(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8814A(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8814A(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8814A(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8814A(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8814A(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8814A(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8814A(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8814A(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8814A(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8814A(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8814A(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8814A(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) /*TXDESC_WORD4*/ -#define SET_TX_DESC_PCTS_MASK_IDX_8814A(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_MASK_IDX_8814A(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) -#define SET_TX_DESC_PCTS_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_EN_8814A(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSRATE_8814A(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTSRATE_8814A(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc) -#define SET_TX_DESC_RTS_DATA_RTY_LMT_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_DATA_RTY_LMT_8814A(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) -#define SET_TX_DESC_RTY_LMT_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RTY_LMT_EN_8814A(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_TRY_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_TRY_RATE_8814A(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc) -#define SET_TX_DESC_DATARATE_8814A(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATARATE_8814A(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc) +#define SET_TX_DESC_PCTS_MASK_IDX_8814A(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8814A(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8814A(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8814A(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8814A(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8814A(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8814A(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8814A(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8814A(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8814A(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8814A(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8814A(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8814A(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8814A(txdesc) GET_TX_DESC_DATARATE(txdesc) /*TXDESC_WORD5*/ -#define SET_TX_DESC_POLLUTED_8814A(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value) -#define GET_TX_DESC_POLLUTED_8814A(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc) -#define SET_TX_DESC_TXPWR_OFSET_8814A(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) -#define GET_TX_DESC_TXPWR_OFSET_8814A(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc) -#define SET_TX_DESC_TX_ANT_8814A(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value) -#define GET_TX_DESC_TX_ANT_8814A(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc) -#define SET_TX_DESC_PORT_ID_8814A(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value) -#define GET_TX_DESC_PORT_ID_8814A(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc) -#define SET_TX_DESC_SIGNALING_TAPKT_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SIGNALING_TAPKT_EN_8814A(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_SC_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SC_8814A(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc) -#define SET_TX_DESC_RTS_SHORT_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SHORT_8814A(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc) -#define SET_TX_DESC_VCS_STBC_8814A(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_VCS_STBC_8814A(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_STBC_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_STBC_8814A(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_LDPC_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_LDPC_8814A(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc) -#define SET_TX_DESC_DATA_BW_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_BW_8814A(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc) -#define SET_TX_DESC_DATA_SHORT_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SHORT_8814A(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc) -#define SET_TX_DESC_DATA_SC_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SC_8814A(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc) +#define SET_TX_DESC_POLLUTED_8814A(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8814A(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_8814A(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_8814A(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc) +#define SET_TX_DESC_TX_ANT_8814A(txdesc, value) \ + SET_TX_DESC_TX_ANT(txdesc, value) +#define GET_TX_DESC_TX_ANT_8814A(txdesc) GET_TX_DESC_TX_ANT(txdesc) +#define SET_TX_DESC_PORT_ID_8814A(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8814A(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8814A(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8814A(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_RTS_SC_8814A(txdesc, value) \ + SET_TX_DESC_RTS_SC(txdesc, value) +#define GET_TX_DESC_RTS_SC_8814A(txdesc) GET_TX_DESC_RTS_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8814A(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8814A(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8814A(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8814A(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8814A(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8814A(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8814A(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8814A(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8814A(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8814A(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8814A(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8814A(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8814A(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8814A(txdesc) GET_TX_DESC_DATA_SC(txdesc) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_D_8814A(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_D_8814A(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc) -#define SET_TX_DESC_ANT_MAPD_8814A(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPD_8814A(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc) -#define SET_TX_DESC_ANT_MAPC_8814A(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPC_8814A(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc) -#define SET_TX_DESC_ANT_MAPB_8814A(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPB_8814A(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc) -#define SET_TX_DESC_ANT_MAPA_8814A(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPA_8814A(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc) -#define SET_TX_DESC_ANTSEL_C_8814A(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_C_8814A(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc) -#define SET_TX_DESC_ANTSEL_B_8814A(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_B_8814A(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc) -#define SET_TX_DESC_ANTSEL_A_8814A(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_A_8814A(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc) -#define SET_TX_DESC_MBSSID_8814A(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value) -#define GET_TX_DESC_MBSSID_8814A(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc) -#define SET_TX_DESC_SW_DEFINE_8814A(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) -#define GET_TX_DESC_SW_DEFINE_8814A(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc) +#define SET_TX_DESC_ANTSEL_D_8814A(txdesc, value) \ + SET_TX_DESC_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_ANTSEL_D_8814A(txdesc) GET_TX_DESC_ANTSEL_D(txdesc) +#define SET_TX_DESC_ANT_MAPD_8814A(txdesc, value) \ + SET_TX_DESC_ANT_MAPD(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8814A(txdesc) GET_TX_DESC_ANT_MAPD(txdesc) +#define SET_TX_DESC_ANT_MAPC_8814A(txdesc, value) \ + SET_TX_DESC_ANT_MAPC(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8814A(txdesc) GET_TX_DESC_ANT_MAPC(txdesc) +#define SET_TX_DESC_ANT_MAPB_8814A(txdesc, value) \ + SET_TX_DESC_ANT_MAPB(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8814A(txdesc) GET_TX_DESC_ANT_MAPB(txdesc) +#define SET_TX_DESC_ANT_MAPA_8814A(txdesc, value) \ + SET_TX_DESC_ANT_MAPA(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8814A(txdesc) GET_TX_DESC_ANT_MAPA(txdesc) +#define SET_TX_DESC_ANTSEL_C_8814A(txdesc, value) \ + SET_TX_DESC_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8814A(txdesc) GET_TX_DESC_ANTSEL_C(txdesc) +#define SET_TX_DESC_ANTSEL_B_8814A(txdesc, value) \ + SET_TX_DESC_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8814A(txdesc) GET_TX_DESC_ANTSEL_B(txdesc) +#define SET_TX_DESC_ANTSEL_A_8814A(txdesc, value) \ + SET_TX_DESC_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8814A(txdesc) GET_TX_DESC_ANTSEL_A(txdesc) +#define SET_TX_DESC_MBSSID_8814A(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8814A(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SW_DEFINE_8814A(txdesc, value) \ + SET_TX_DESC_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_SW_DEFINE_8814A(txdesc) GET_TX_DESC_SW_DEFINE(txdesc) /*TXDESC_WORD7*/ -#define SET_TX_DESC_DMA_TXAGG_NUM_8814A(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_DMA_TXAGG_NUM_8814A(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) -#define SET_TX_DESC_FINAL_DATA_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_FINAL_DATA_RATE_8814A(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) -#define SET_TX_DESC_NTX_MAP_8814A(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) -#define GET_TX_DESC_NTX_MAP_8814A(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc) -#define SET_TX_DESC_TX_BUFF_SIZE_8814A(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TX_BUFF_SIZE_8814A(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) -#define SET_TX_DESC_TXDESC_CHECKSUM_8814A(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) -#define GET_TX_DESC_TXDESC_CHECKSUM_8814A(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) -#define SET_TX_DESC_TIMESTAMP_8814A(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) -#define GET_TX_DESC_TIMESTAMP_8814A(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc) +#define SET_TX_DESC_DMA_TXAGG_NUM_8814A(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8814A(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8814A(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8814A(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8814A(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8814A(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8814A(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8814A(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8814A(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8814A(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8814A(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8814A(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) /*TXDESC_WORD8*/ -#define SET_TX_DESC_TXWIFI_CP_8814A(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) -#define GET_TX_DESC_TXWIFI_CP_8814A(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc) -#define SET_TX_DESC_MAC_CP_8814A(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value) -#define GET_TX_DESC_MAC_CP_8814A(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc) -#define SET_TX_DESC_STW_PKTRE_DIS_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_PKTRE_DIS_8814A(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RB_DIS_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RB_DIS_8814A(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RATE_DIS_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RATE_DIS_8814A(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_ANT_DIS_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_ANT_DIS_8814A(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc) -#define SET_TX_DESC_STW_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value) -#define GET_TX_DESC_STW_EN_8814A(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc) -#define SET_TX_DESC_SMH_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SMH_EN_8814A(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc) -#define SET_TX_DESC_TAILPAGE_L_8814A(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_L_8814A(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc) -#define SET_TX_DESC_SDIO_DMASEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SDIO_DMASEQ_8814A(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_L_8814A(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_L_8814A(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) -#define SET_TX_DESC_EN_HWSEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWSEQ_8814A(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc) -#define SET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) -#define SET_TX_DESC_DATA_RC_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RC_8814A(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc) -#define SET_TX_DESC_BAR_RTY_TH_8814A(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) -#define GET_TX_DESC_BAR_RTY_TH_8814A(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc) -#define SET_TX_DESC_RTS_RC_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RC_8814A(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc) +#define SET_TX_DESC_TXWIFI_CP_8814A(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8814A(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8814A(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8814A(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8814A(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8814A(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8814A(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8814A(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8814A(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8814A(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8814A(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8814A(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8814A(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8814A(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8814A(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8814A(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8814A(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8814A(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8814A(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8814A(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8814A(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8814A(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_8814A(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_8814A(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc) +#define SET_TX_DESC_EN_HWEXSEQ_8814A(txdesc, value) \ + SET_TX_DESC_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWEXSEQ_8814A(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_DATA_RC_8814A(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8814A(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8814A(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8814A(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8814A(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8814A(txdesc) GET_TX_DESC_RTS_RC(txdesc) /*TXDESC_WORD9*/ -#define SET_TX_DESC_TAILPAGE_H_8814A(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_H_8814A(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_H_8814A(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_H_8814A(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) -#define SET_TX_DESC_SW_SEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SW_SEQ_8814A(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc) -#define SET_TX_DESC_TXBF_PATH_8814A(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) -#define GET_TX_DESC_TXBF_PATH_8814A(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc) -#define SET_TX_DESC_PADDING_LEN_8814A(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_PADDING_LEN_8814A(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) +#define SET_TX_DESC_TAILPAGE_H_8814A(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8814A(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8814A(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8814A(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8814A(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8814A(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8814A(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8814A(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8814A(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8814A(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) /*WORD10*/ - #endif #if (HALMAC_8822B_SUPPORT) /*TXDESC_WORD0*/ -#define SET_TX_DESC_DISQSELSEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_DISQSELSEQ_8822B(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc) -#define SET_TX_DESC_GF_8822B(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value) -#define GET_TX_DESC_GF_8822B(__pTxDesc) GET_TX_DESC_GF(__pTxDesc) -#define SET_TX_DESC_NO_ACM_8822B(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value) -#define GET_TX_DESC_NO_ACM_8822B(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc) -#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822B(__pTxDesc, __Value) SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) -#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822B(__pTxDesc) GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) -#define SET_TX_DESC_AMSDU_PAD_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AMSDU_PAD_EN_8822B(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) -#define SET_TX_DESC_LS_8822B(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value) -#define GET_TX_DESC_LS_8822B(__pTxDesc) GET_TX_DESC_LS(__pTxDesc) -#define SET_TX_DESC_HTC_8822B(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value) -#define GET_TX_DESC_HTC_8822B(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc) -#define SET_TX_DESC_BMC_8822B(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value) -#define GET_TX_DESC_BMC_8822B(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc) -#define SET_TX_DESC_OFFSET_8822B(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_OFFSET_8822B(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc) -#define SET_TX_DESC_TXPKTSIZE_8822B(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TXPKTSIZE_8822B(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc) - -/*TXDESC_WORD1*/ - -#define SET_TX_DESC_MOREDATA_8822B(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value) -#define GET_TX_DESC_MOREDATA_8822B(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc) -#define SET_TX_DESC_PKT_OFFSET_8822B(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_PKT_OFFSET_8822B(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc) -#define SET_TX_DESC_SEC_TYPE_8822B(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) -#define GET_TX_DESC_SEC_TYPE_8822B(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc) -#define SET_TX_DESC_EN_DESC_ID_8822B(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) -#define GET_TX_DESC_EN_DESC_ID_8822B(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc) -#define SET_TX_DESC_RATE_ID_8822B(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value) -#define GET_TX_DESC_RATE_ID_8822B(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc) -#define SET_TX_DESC_PIFS_8822B(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value) -#define GET_TX_DESC_PIFS_8822B(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc) -#define SET_TX_DESC_LSIG_TXOP_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) -#define GET_TX_DESC_LSIG_TXOP_EN_8822B(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) -#define SET_TX_DESC_RD_NAV_EXT_8822B(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) -#define GET_TX_DESC_RD_NAV_EXT_8822B(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc) -#define SET_TX_DESC_QSEL_8822B(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value) -#define GET_TX_DESC_QSEL_8822B(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc) -#define SET_TX_DESC_MACID_8822B(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value) -#define GET_TX_DESC_MACID_8822B(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc) +#define SET_TX_DESC_DISQSELSEQ_8822B(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8822B(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8822B(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8822B(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8822B(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8822B(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822B(txdesc, value) \ + SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822B(txdesc) \ + GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8822B(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8822B(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8822B(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8822B(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8822B(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8822B(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8822B(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8822B(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8822B(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8822B(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8822B(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8822B(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_MOREDATA_8822B(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8822B(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8822B(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8822B(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8822B(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8822B(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8822B(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8822B(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8822B(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8822B(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8822B(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8822B(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8822B(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8822B(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8822B(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8822B(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8822B(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8822B(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8822B(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8822B(txdesc) GET_TX_DESC_MACID(txdesc) /*TXDESC_WORD2*/ -#define SET_TX_DESC_HW_AES_IV_8822B(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) -#define GET_TX_DESC_HW_AES_IV_8822B(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc) -#define SET_TX_DESC_FTM_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value) -#define GET_TX_DESC_FTM_EN_8822B(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc) -#define SET_TX_DESC_G_ID_8822B(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value) -#define GET_TX_DESC_G_ID_8822B(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc) -#define SET_TX_DESC_BT_NULL_8822B(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value) -#define GET_TX_DESC_BT_NULL_8822B(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc) -#define SET_TX_DESC_AMPDU_DENSITY_8822B(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_DENSITY_8822B(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) -#define SET_TX_DESC_SPE_RPT_8822B(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) -#define GET_TX_DESC_SPE_RPT_8822B(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc) -#define SET_TX_DESC_RAW_8822B(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value) -#define GET_TX_DESC_RAW_8822B(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc) -#define SET_TX_DESC_MOREFRAG_8822B(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) -#define GET_TX_DESC_MOREFRAG_8822B(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc) -#define SET_TX_DESC_BK_8822B(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value) -#define GET_TX_DESC_BK_8822B(__pTxDesc) GET_TX_DESC_BK(__pTxDesc) -#define SET_TX_DESC_NULL_1_8822B(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_1_8822B(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc) -#define SET_TX_DESC_NULL_0_8822B(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_0_8822B(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc) -#define SET_TX_DESC_RDG_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RDG_EN_8822B(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc) -#define SET_TX_DESC_AGG_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AGG_EN_8822B(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc) -#define SET_TX_DESC_CCA_RTS_8822B(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) -#define GET_TX_DESC_CCA_RTS_8822B(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc) -#define SET_TX_DESC_TRI_FRAME_8822B(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) -#define GET_TX_DESC_TRI_FRAME_8822B(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc) -#define SET_TX_DESC_P_AID_8822B(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value) -#define GET_TX_DESC_P_AID_8822B(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc) +#define SET_TX_DESC_HW_AES_IV_8822B(txdesc, value) \ + SET_TX_DESC_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8822B(txdesc) GET_TX_DESC_HW_AES_IV(txdesc) +#define SET_TX_DESC_FTM_EN_8822B(txdesc, value) \ + SET_TX_DESC_FTM_EN(txdesc, value) +#define GET_TX_DESC_FTM_EN_8822B(txdesc) GET_TX_DESC_FTM_EN(txdesc) +#define SET_TX_DESC_G_ID_8822B(txdesc, value) SET_TX_DESC_G_ID(txdesc, value) +#define GET_TX_DESC_G_ID_8822B(txdesc) GET_TX_DESC_G_ID(txdesc) +#define SET_TX_DESC_BT_NULL_8822B(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8822B(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8822B(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8822B(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8822B(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8822B(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8822B(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8822B(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8822B(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8822B(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8822B(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8822B(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8822B(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8822B(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8822B(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8822B(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8822B(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8822B(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8822B(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8822B(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8822B(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8822B(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_TRI_FRAME_8822B(txdesc, value) \ + SET_TX_DESC_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_TRI_FRAME_8822B(txdesc) GET_TX_DESC_TRI_FRAME(txdesc) +#define SET_TX_DESC_P_AID_8822B(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8822B(txdesc) GET_TX_DESC_P_AID(txdesc) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME_8822B(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_MAX_TIME_8822B(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) -#define SET_TX_DESC_NDPA_8822B(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value) -#define GET_TX_DESC_NDPA_8822B(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc) -#define SET_TX_DESC_MAX_AGG_NUM_8822B(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_MAX_AGG_NUM_8822B(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) -#define SET_TX_DESC_USE_MAX_TIME_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) -#define GET_TX_DESC_USE_MAX_TIME_EN_8822B(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) -#define SET_TX_DESC_NAVUSEHDR_8822B(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) -#define GET_TX_DESC_NAVUSEHDR_8822B(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc) -#define SET_TX_DESC_CHK_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value) -#define GET_TX_DESC_CHK_EN_8822B(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc) -#define SET_TX_DESC_HW_RTS_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_HW_RTS_EN_8822B(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSEN_8822B(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value) -#define GET_TX_DESC_RTSEN_8822B(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc) -#define SET_TX_DESC_CTS2SELF_8822B(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) -#define GET_TX_DESC_CTS2SELF_8822B(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc) -#define SET_TX_DESC_DISDATAFB_8822B(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISDATAFB_8822B(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc) -#define SET_TX_DESC_DISRTSFB_8822B(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISRTSFB_8822B(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc) -#define SET_TX_DESC_USE_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_USE_RATE_8822B(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc) -#define SET_TX_DESC_HW_SSN_SEL_8822B(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_HW_SSN_SEL_8822B(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc) -#define SET_TX_DESC_WHEADER_LEN_8822B(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_WHEADER_LEN_8822B(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc) +#define SET_TX_DESC_AMPDU_MAX_TIME_8822B(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8822B(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8822B(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8822B(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8822B(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8822B(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8822B(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8822B(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8822B(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8822B(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8822B(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8822B(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8822B(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8822B(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8822B(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8822B(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8822B(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8822B(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8822B(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8822B(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8822B(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8822B(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8822B(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8822B(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8822B(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8822B(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8822B(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8822B(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) /*TXDESC_WORD4*/ -#define SET_TX_DESC_PCTS_MASK_IDX_8822B(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_MASK_IDX_8822B(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) -#define SET_TX_DESC_PCTS_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_EN_8822B(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSRATE_8822B(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTSRATE_8822B(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc) -#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822B(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) -#define SET_TX_DESC_RTY_LMT_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RTY_LMT_EN_8822B(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_TRY_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_TRY_RATE_8822B(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc) -#define SET_TX_DESC_DATARATE_8822B(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATARATE_8822B(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc) +#define SET_TX_DESC_PCTS_MASK_IDX_8822B(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8822B(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8822B(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8822B(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8822B(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8822B(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822B(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8822B(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8822B(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8822B(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8822B(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8822B(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8822B(txdesc) GET_TX_DESC_DATARATE(txdesc) /*TXDESC_WORD5*/ -#define SET_TX_DESC_POLLUTED_8822B(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value) -#define GET_TX_DESC_POLLUTED_8822B(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc) -#define SET_TX_DESC_TXPWR_OFSET_8822B(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) -#define GET_TX_DESC_TXPWR_OFSET_8822B(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc) -#define SET_TX_DESC_TX_ANT_8822B(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value) -#define GET_TX_DESC_TX_ANT_8822B(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc) -#define SET_TX_DESC_PORT_ID_8822B(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value) -#define GET_TX_DESC_PORT_ID_8822B(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc) -#define SET_TX_DESC_MULTIPLE_PORT_8822B(__pTxDesc, __Value) SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) -#define GET_TX_DESC_MULTIPLE_PORT_8822B(__pTxDesc) GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) -#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822B(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_SC_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SC_8822B(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc) -#define SET_TX_DESC_RTS_SHORT_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SHORT_8822B(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc) -#define SET_TX_DESC_VCS_STBC_8822B(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_VCS_STBC_8822B(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_STBC_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_STBC_8822B(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_LDPC_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_LDPC_8822B(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc) -#define SET_TX_DESC_DATA_BW_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_BW_8822B(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc) -#define SET_TX_DESC_DATA_SHORT_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SHORT_8822B(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc) -#define SET_TX_DESC_DATA_SC_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SC_8822B(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc) +#define SET_TX_DESC_POLLUTED_8822B(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8822B(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_8822B(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_8822B(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc) +#define SET_TX_DESC_TX_ANT_8822B(txdesc, value) \ + SET_TX_DESC_TX_ANT(txdesc, value) +#define GET_TX_DESC_TX_ANT_8822B(txdesc) GET_TX_DESC_TX_ANT(txdesc) +#define SET_TX_DESC_PORT_ID_8822B(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8822B(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_MULTIPLE_PORT_8822B(txdesc, value) \ + SET_TX_DESC_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_MULTIPLE_PORT_8822B(txdesc) \ + GET_TX_DESC_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822B(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822B(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8822B(txdesc, value) \ + SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) +#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8822B(txdesc) \ + GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8822B(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8822B(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8822B(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8822B(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8822B(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8822B(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8822B(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8822B(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8822B(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8822B(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8822B(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8822B(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8822B(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8822B(txdesc) GET_TX_DESC_DATA_SC(txdesc) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_D_8822B(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_D_8822B(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc) -#define SET_TX_DESC_ANT_MAPD_8822B(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPD_8822B(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc) -#define SET_TX_DESC_ANT_MAPC_8822B(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPC_8822B(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc) -#define SET_TX_DESC_ANT_MAPB_8822B(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPB_8822B(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc) -#define SET_TX_DESC_ANT_MAPA_8822B(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPA_8822B(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc) -#define SET_TX_DESC_ANTSEL_C_8822B(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_C_8822B(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc) -#define SET_TX_DESC_ANTSEL_B_8822B(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_B_8822B(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc) -#define SET_TX_DESC_ANTSEL_A_8822B(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_A_8822B(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc) -#define SET_TX_DESC_MBSSID_8822B(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value) -#define GET_TX_DESC_MBSSID_8822B(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc) -#define SET_TX_DESC_SW_DEFINE_8822B(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) -#define GET_TX_DESC_SW_DEFINE_8822B(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc) +#define SET_TX_DESC_ANTSEL_D_8822B(txdesc, value) \ + SET_TX_DESC_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_ANTSEL_D_8822B(txdesc) GET_TX_DESC_ANTSEL_D(txdesc) +#define SET_TX_DESC_ANT_MAPD_8822B(txdesc, value) \ + SET_TX_DESC_ANT_MAPD(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8822B(txdesc) GET_TX_DESC_ANT_MAPD(txdesc) +#define SET_TX_DESC_ANT_MAPC_8822B(txdesc, value) \ + SET_TX_DESC_ANT_MAPC(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8822B(txdesc) GET_TX_DESC_ANT_MAPC(txdesc) +#define SET_TX_DESC_ANT_MAPB_8822B(txdesc, value) \ + SET_TX_DESC_ANT_MAPB(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8822B(txdesc) GET_TX_DESC_ANT_MAPB(txdesc) +#define SET_TX_DESC_ANT_MAPA_8822B(txdesc, value) \ + SET_TX_DESC_ANT_MAPA(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8822B(txdesc) GET_TX_DESC_ANT_MAPA(txdesc) +#define SET_TX_DESC_ANTSEL_C_8822B(txdesc, value) \ + SET_TX_DESC_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8822B(txdesc) GET_TX_DESC_ANTSEL_C(txdesc) +#define SET_TX_DESC_ANTSEL_B_8822B(txdesc, value) \ + SET_TX_DESC_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8822B(txdesc) GET_TX_DESC_ANTSEL_B(txdesc) +#define SET_TX_DESC_ANTSEL_A_8822B(txdesc, value) \ + SET_TX_DESC_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8822B(txdesc) GET_TX_DESC_ANTSEL_A(txdesc) +#define SET_TX_DESC_MBSSID_8822B(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8822B(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SW_DEFINE_8822B(txdesc, value) \ + SET_TX_DESC_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_SW_DEFINE_8822B(txdesc) GET_TX_DESC_SW_DEFINE(txdesc) /*TXDESC_WORD7*/ -#define SET_TX_DESC_DMA_TXAGG_NUM_8822B(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_DMA_TXAGG_NUM_8822B(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) -#define SET_TX_DESC_FINAL_DATA_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_FINAL_DATA_RATE_8822B(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) -#define SET_TX_DESC_NTX_MAP_8822B(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) -#define GET_TX_DESC_NTX_MAP_8822B(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc) -#define SET_TX_DESC_TX_BUFF_SIZE_8822B(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TX_BUFF_SIZE_8822B(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) -#define SET_TX_DESC_TXDESC_CHECKSUM_8822B(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) -#define GET_TX_DESC_TXDESC_CHECKSUM_8822B(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) -#define SET_TX_DESC_TIMESTAMP_8822B(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) -#define GET_TX_DESC_TIMESTAMP_8822B(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc) +#define SET_TX_DESC_DMA_TXAGG_NUM_8822B(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8822B(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8822B(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8822B(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8822B(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8822B(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8822B(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8822B(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8822B(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8822B(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8822B(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8822B(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) /*TXDESC_WORD8*/ -#define SET_TX_DESC_TXWIFI_CP_8822B(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) -#define GET_TX_DESC_TXWIFI_CP_8822B(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc) -#define SET_TX_DESC_MAC_CP_8822B(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value) -#define GET_TX_DESC_MAC_CP_8822B(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc) -#define SET_TX_DESC_STW_PKTRE_DIS_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_PKTRE_DIS_8822B(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RB_DIS_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RB_DIS_8822B(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RATE_DIS_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RATE_DIS_8822B(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_ANT_DIS_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_ANT_DIS_8822B(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc) -#define SET_TX_DESC_STW_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value) -#define GET_TX_DESC_STW_EN_8822B(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc) -#define SET_TX_DESC_SMH_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SMH_EN_8822B(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc) -#define SET_TX_DESC_TAILPAGE_L_8822B(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_L_8822B(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc) -#define SET_TX_DESC_SDIO_DMASEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SDIO_DMASEQ_8822B(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_L_8822B(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_L_8822B(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) -#define SET_TX_DESC_EN_HWSEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWSEQ_8822B(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc) -#define SET_TX_DESC_EN_HWEXSEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWEXSEQ_8822B(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) -#define SET_TX_DESC_DATA_RC_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RC_8822B(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc) -#define SET_TX_DESC_BAR_RTY_TH_8822B(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) -#define GET_TX_DESC_BAR_RTY_TH_8822B(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc) -#define SET_TX_DESC_RTS_RC_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RC_8822B(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc) +#define SET_TX_DESC_TXWIFI_CP_8822B(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8822B(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8822B(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8822B(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8822B(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8822B(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8822B(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8822B(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8822B(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8822B(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8822B(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8822B(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8822B(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8822B(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8822B(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8822B(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8822B(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8822B(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8822B(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8822B(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8822B(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8822B(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_8822B(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_8822B(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc) +#define SET_TX_DESC_EN_HWEXSEQ_8822B(txdesc, value) \ + SET_TX_DESC_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWEXSEQ_8822B(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_DATA_RC_8822B(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8822B(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8822B(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8822B(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8822B(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8822B(txdesc) GET_TX_DESC_RTS_RC(txdesc) /*TXDESC_WORD9*/ -#define SET_TX_DESC_TAILPAGE_H_8822B(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_H_8822B(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_H_8822B(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_H_8822B(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) -#define SET_TX_DESC_SW_SEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SW_SEQ_8822B(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc) -#define SET_TX_DESC_TXBF_PATH_8822B(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) -#define GET_TX_DESC_TXBF_PATH_8822B(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc) -#define SET_TX_DESC_PADDING_LEN_8822B(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_PADDING_LEN_8822B(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) +#define SET_TX_DESC_TAILPAGE_H_8822B(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8822B(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8822B(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8822B(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8822B(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8822B(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8822B(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8822B(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8822B(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8822B(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) /*WORD10*/ -#define SET_TX_DESC_MU_DATARATE_8822B(__pTxDesc, __Value) SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_MU_DATARATE_8822B(__pTxDesc) GET_TX_DESC_MU_DATARATE(__pTxDesc) -#define SET_TX_DESC_MU_RC_8822B(__pTxDesc, __Value) SET_TX_DESC_MU_RC(__pTxDesc, __Value) -#define GET_TX_DESC_MU_RC_8822B(__pTxDesc) GET_TX_DESC_MU_RC(__pTxDesc) -#define SET_TX_DESC_SND_PKT_SEL_8822B(__pTxDesc, __Value) SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_SND_PKT_SEL_8822B(__pTxDesc) GET_TX_DESC_SND_PKT_SEL(__pTxDesc) +#define SET_TX_DESC_MU_DATARATE_8822B(txdesc, value) \ + SET_TX_DESC_MU_DATARATE(txdesc, value) +#define GET_TX_DESC_MU_DATARATE_8822B(txdesc) GET_TX_DESC_MU_DATARATE(txdesc) +#define SET_TX_DESC_MU_RC_8822B(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value) +#define GET_TX_DESC_MU_RC_8822B(txdesc) GET_TX_DESC_MU_RC(txdesc) +#define SET_TX_DESC_SND_PKT_SEL_8822B(txdesc, value) \ + SET_TX_DESC_SND_PKT_SEL(txdesc, value) +#define GET_TX_DESC_SND_PKT_SEL_8822B(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc) #endif @@ -535,728 +761,1625 @@ /*TXDESC_WORD0*/ -#define SET_TX_DESC_DISQSELSEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_DISQSELSEQ_8197F(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc) -#define SET_TX_DESC_GF_8197F(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value) -#define GET_TX_DESC_GF_8197F(__pTxDesc) GET_TX_DESC_GF(__pTxDesc) -#define SET_TX_DESC_NO_ACM_8197F(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value) -#define GET_TX_DESC_NO_ACM_8197F(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc) -#define SET_TX_DESC_BCNPKT_TSF_CTRL_8197F(__pTxDesc, __Value) SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) -#define GET_TX_DESC_BCNPKT_TSF_CTRL_8197F(__pTxDesc) GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) -#define SET_TX_DESC_AMSDU_PAD_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AMSDU_PAD_EN_8197F(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) -#define SET_TX_DESC_LS_8197F(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value) -#define GET_TX_DESC_LS_8197F(__pTxDesc) GET_TX_DESC_LS(__pTxDesc) -#define SET_TX_DESC_HTC_8197F(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value) -#define GET_TX_DESC_HTC_8197F(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc) -#define SET_TX_DESC_BMC_8197F(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value) -#define GET_TX_DESC_BMC_8197F(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc) -#define SET_TX_DESC_OFFSET_8197F(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_OFFSET_8197F(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc) -#define SET_TX_DESC_TXPKTSIZE_8197F(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TXPKTSIZE_8197F(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc) - -/*TXDESC_WORD1*/ - -#define SET_TX_DESC_MOREDATA_8197F(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value) -#define GET_TX_DESC_MOREDATA_8197F(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc) -#define SET_TX_DESC_PKT_OFFSET_8197F(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_PKT_OFFSET_8197F(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc) -#define SET_TX_DESC_SEC_TYPE_8197F(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) -#define GET_TX_DESC_SEC_TYPE_8197F(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc) -#define SET_TX_DESC_EN_DESC_ID_8197F(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) -#define GET_TX_DESC_EN_DESC_ID_8197F(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc) -#define SET_TX_DESC_RATE_ID_8197F(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value) -#define GET_TX_DESC_RATE_ID_8197F(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc) -#define SET_TX_DESC_PIFS_8197F(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value) -#define GET_TX_DESC_PIFS_8197F(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc) -#define SET_TX_DESC_LSIG_TXOP_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) -#define GET_TX_DESC_LSIG_TXOP_EN_8197F(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) -#define SET_TX_DESC_RD_NAV_EXT_8197F(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) -#define GET_TX_DESC_RD_NAV_EXT_8197F(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc) -#define SET_TX_DESC_QSEL_8197F(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value) -#define GET_TX_DESC_QSEL_8197F(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc) -#define SET_TX_DESC_MACID_8197F(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value) -#define GET_TX_DESC_MACID_8197F(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc) +#define SET_TX_DESC_DISQSELSEQ_8197F(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8197F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8197F(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8197F(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8197F(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8197F(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_8197F(txdesc, value) \ + SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL_8197F(txdesc) \ + GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8197F(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8197F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8197F(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8197F(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8197F(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8197F(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8197F(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8197F(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8197F(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8197F(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8197F(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8197F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_MOREDATA_8197F(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8197F(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8197F(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8197F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8197F(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8197F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8197F(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8197F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8197F(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8197F(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8197F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8197F(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8197F(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8197F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8197F(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8197F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8197F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8197F(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8197F(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8197F(txdesc) GET_TX_DESC_MACID(txdesc) /*TXDESC_WORD2*/ -#define SET_TX_DESC_HW_AES_IV_8197F(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) -#define GET_TX_DESC_HW_AES_IV_8197F(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc) -#define SET_TX_DESC_FTM_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value) -#define GET_TX_DESC_FTM_EN_8197F(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc) -#define SET_TX_DESC_G_ID_8197F(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value) -#define GET_TX_DESC_G_ID_8197F(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc) -#define SET_TX_DESC_BT_NULL_8197F(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value) -#define GET_TX_DESC_BT_NULL_8197F(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc) -#define SET_TX_DESC_AMPDU_DENSITY_8197F(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_DENSITY_8197F(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) -#define SET_TX_DESC_SPE_RPT_8197F(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) -#define GET_TX_DESC_SPE_RPT_8197F(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc) -#define SET_TX_DESC_RAW_8197F(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value) -#define GET_TX_DESC_RAW_8197F(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc) -#define SET_TX_DESC_MOREFRAG_8197F(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) -#define GET_TX_DESC_MOREFRAG_8197F(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc) -#define SET_TX_DESC_BK_8197F(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value) -#define GET_TX_DESC_BK_8197F(__pTxDesc) GET_TX_DESC_BK(__pTxDesc) -#define SET_TX_DESC_NULL_1_8197F(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_1_8197F(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc) -#define SET_TX_DESC_NULL_0_8197F(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_0_8197F(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc) -#define SET_TX_DESC_RDG_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RDG_EN_8197F(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc) -#define SET_TX_DESC_AGG_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AGG_EN_8197F(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc) -#define SET_TX_DESC_CCA_RTS_8197F(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) -#define GET_TX_DESC_CCA_RTS_8197F(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc) -#define SET_TX_DESC_TRI_FRAME_8197F(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) -#define GET_TX_DESC_TRI_FRAME_8197F(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc) -#define SET_TX_DESC_P_AID_8197F(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value) -#define GET_TX_DESC_P_AID_8197F(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc) +#define SET_TX_DESC_HW_AES_IV_8197F(txdesc, value) \ + SET_TX_DESC_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8197F(txdesc) GET_TX_DESC_HW_AES_IV(txdesc) +#define SET_TX_DESC_FTM_EN_8197F(txdesc, value) \ + SET_TX_DESC_FTM_EN(txdesc, value) +#define GET_TX_DESC_FTM_EN_8197F(txdesc) GET_TX_DESC_FTM_EN(txdesc) +#define SET_TX_DESC_G_ID_8197F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value) +#define GET_TX_DESC_G_ID_8197F(txdesc) GET_TX_DESC_G_ID(txdesc) +#define SET_TX_DESC_BT_NULL_8197F(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8197F(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8197F(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8197F(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8197F(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8197F(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8197F(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8197F(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8197F(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8197F(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8197F(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8197F(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8197F(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8197F(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8197F(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8197F(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8197F(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8197F(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8197F(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8197F(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8197F(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8197F(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_TRI_FRAME_8197F(txdesc, value) \ + SET_TX_DESC_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_TRI_FRAME_8197F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc) +#define SET_TX_DESC_P_AID_8197F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8197F(txdesc) GET_TX_DESC_P_AID(txdesc) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME_8197F(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_MAX_TIME_8197F(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) -#define SET_TX_DESC_NDPA_8197F(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value) -#define GET_TX_DESC_NDPA_8197F(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc) -#define SET_TX_DESC_MAX_AGG_NUM_8197F(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_MAX_AGG_NUM_8197F(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) -#define SET_TX_DESC_USE_MAX_TIME_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) -#define GET_TX_DESC_USE_MAX_TIME_EN_8197F(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) -#define SET_TX_DESC_NAVUSEHDR_8197F(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) -#define GET_TX_DESC_NAVUSEHDR_8197F(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc) -#define SET_TX_DESC_CHK_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value) -#define GET_TX_DESC_CHK_EN_8197F(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc) -#define SET_TX_DESC_HW_RTS_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_HW_RTS_EN_8197F(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSEN_8197F(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value) -#define GET_TX_DESC_RTSEN_8197F(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc) -#define SET_TX_DESC_CTS2SELF_8197F(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) -#define GET_TX_DESC_CTS2SELF_8197F(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc) -#define SET_TX_DESC_DISDATAFB_8197F(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISDATAFB_8197F(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc) -#define SET_TX_DESC_DISRTSFB_8197F(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISRTSFB_8197F(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc) -#define SET_TX_DESC_USE_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_USE_RATE_8197F(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc) -#define SET_TX_DESC_HW_SSN_SEL_8197F(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_HW_SSN_SEL_8197F(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc) -#define SET_TX_DESC_WHEADER_LEN_8197F(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_WHEADER_LEN_8197F(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc) +#define SET_TX_DESC_AMPDU_MAX_TIME_8197F(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8197F(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8197F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8197F(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8197F(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8197F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8197F(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8197F(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8197F(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8197F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8197F(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8197F(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8197F(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8197F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8197F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8197F(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8197F(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8197F(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8197F(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8197F(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8197F(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8197F(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8197F(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8197F(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8197F(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8197F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8197F(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8197F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) /*TXDESC_WORD4*/ -#define SET_TX_DESC_PCTS_MASK_IDX_8197F(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_MASK_IDX_8197F(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) -#define SET_TX_DESC_PCTS_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_EN_8197F(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSRATE_8197F(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTSRATE_8197F(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc) -#define SET_TX_DESC_RTS_DATA_RTY_LMT_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_DATA_RTY_LMT_8197F(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) -#define SET_TX_DESC_RTY_LMT_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RTY_LMT_EN_8197F(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_TRY_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_TRY_RATE_8197F(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc) -#define SET_TX_DESC_DATARATE_8197F(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATARATE_8197F(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc) +#define SET_TX_DESC_PCTS_MASK_IDX_8197F(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8197F(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8197F(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8197F(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8197F(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8197F(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8197F(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8197F(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8197F(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8197F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8197F(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8197F(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8197F(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8197F(txdesc) GET_TX_DESC_DATARATE(txdesc) /*TXDESC_WORD5*/ -#define SET_TX_DESC_POLLUTED_8197F(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value) -#define GET_TX_DESC_POLLUTED_8197F(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc) -#define SET_TX_DESC_TXPWR_OFSET_8197F(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) -#define GET_TX_DESC_TXPWR_OFSET_8197F(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc) -#define SET_TX_DESC_TX_ANT_8197F(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value) -#define GET_TX_DESC_TX_ANT_8197F(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc) -#define SET_TX_DESC_PORT_ID_8197F(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value) -#define GET_TX_DESC_PORT_ID_8197F(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc) -#define SET_TX_DESC_MULTIPLE_PORT_8197F(__pTxDesc, __Value) SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) -#define GET_TX_DESC_MULTIPLE_PORT_8197F(__pTxDesc) GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) -#define SET_TX_DESC_SIGNALING_TAPKT_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SIGNALING_TAPKT_EN_8197F(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_SC_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SC_8197F(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc) -#define SET_TX_DESC_RTS_SHORT_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SHORT_8197F(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc) -#define SET_TX_DESC_VCS_STBC_8197F(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_VCS_STBC_8197F(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_STBC_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_STBC_8197F(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_LDPC_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_LDPC_8197F(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc) -#define SET_TX_DESC_DATA_BW_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_BW_8197F(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc) -#define SET_TX_DESC_DATA_SHORT_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SHORT_8197F(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc) -#define SET_TX_DESC_DATA_SC_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SC_8197F(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc) +#define SET_TX_DESC_POLLUTED_8197F(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8197F(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_8197F(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_8197F(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc) +#define SET_TX_DESC_TX_ANT_8197F(txdesc, value) \ + SET_TX_DESC_TX_ANT(txdesc, value) +#define GET_TX_DESC_TX_ANT_8197F(txdesc) GET_TX_DESC_TX_ANT(txdesc) +#define SET_TX_DESC_PORT_ID_8197F(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8197F(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_MULTIPLE_PORT_8197F(txdesc, value) \ + SET_TX_DESC_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_MULTIPLE_PORT_8197F(txdesc) \ + GET_TX_DESC_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8197F(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8197F(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_RTS_SC_8197F(txdesc, value) \ + SET_TX_DESC_RTS_SC(txdesc, value) +#define GET_TX_DESC_RTS_SC_8197F(txdesc) GET_TX_DESC_RTS_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8197F(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8197F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8197F(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8197F(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8197F(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8197F(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8197F(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8197F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8197F(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8197F(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8197F(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8197F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8197F(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8197F(txdesc) GET_TX_DESC_DATA_SC(txdesc) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_D_8197F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_D_8197F(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc) -#define SET_TX_DESC_ANT_MAPD_8197F(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPD_8197F(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc) -#define SET_TX_DESC_ANT_MAPC_8197F(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPC_8197F(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc) -#define SET_TX_DESC_ANT_MAPB_8197F(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPB_8197F(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc) -#define SET_TX_DESC_ANT_MAPA_8197F(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPA_8197F(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc) -#define SET_TX_DESC_ANTSEL_C_8197F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_C_8197F(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc) -#define SET_TX_DESC_ANTSEL_B_8197F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_B_8197F(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc) -#define SET_TX_DESC_ANTSEL_A_8197F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_A_8197F(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc) -#define SET_TX_DESC_MBSSID_8197F(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value) -#define GET_TX_DESC_MBSSID_8197F(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc) -#define SET_TX_DESC_SW_DEFINE_8197F(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) -#define GET_TX_DESC_SW_DEFINE_8197F(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc) +#define SET_TX_DESC_ANTSEL_D_8197F(txdesc, value) \ + SET_TX_DESC_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_ANTSEL_D_8197F(txdesc) GET_TX_DESC_ANTSEL_D(txdesc) +#define SET_TX_DESC_ANT_MAPD_8197F(txdesc, value) \ + SET_TX_DESC_ANT_MAPD(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8197F(txdesc) GET_TX_DESC_ANT_MAPD(txdesc) +#define SET_TX_DESC_ANT_MAPC_8197F(txdesc, value) \ + SET_TX_DESC_ANT_MAPC(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8197F(txdesc) GET_TX_DESC_ANT_MAPC(txdesc) +#define SET_TX_DESC_ANT_MAPB_8197F(txdesc, value) \ + SET_TX_DESC_ANT_MAPB(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8197F(txdesc) GET_TX_DESC_ANT_MAPB(txdesc) +#define SET_TX_DESC_ANT_MAPA_8197F(txdesc, value) \ + SET_TX_DESC_ANT_MAPA(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8197F(txdesc) GET_TX_DESC_ANT_MAPA(txdesc) +#define SET_TX_DESC_ANTSEL_C_8197F(txdesc, value) \ + SET_TX_DESC_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8197F(txdesc) GET_TX_DESC_ANTSEL_C(txdesc) +#define SET_TX_DESC_ANTSEL_B_8197F(txdesc, value) \ + SET_TX_DESC_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8197F(txdesc) GET_TX_DESC_ANTSEL_B(txdesc) +#define SET_TX_DESC_ANTSEL_A_8197F(txdesc, value) \ + SET_TX_DESC_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8197F(txdesc) GET_TX_DESC_ANTSEL_A(txdesc) +#define SET_TX_DESC_MBSSID_8197F(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8197F(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SW_DEFINE_8197F(txdesc, value) \ + SET_TX_DESC_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_SW_DEFINE_8197F(txdesc) GET_TX_DESC_SW_DEFINE(txdesc) /*TXDESC_WORD7*/ -#define SET_TX_DESC_DMA_TXAGG_NUM_8197F(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_DMA_TXAGG_NUM_8197F(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) -#define SET_TX_DESC_FINAL_DATA_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_FINAL_DATA_RATE_8197F(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) -#define SET_TX_DESC_NTX_MAP_8197F(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) -#define GET_TX_DESC_NTX_MAP_8197F(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc) -#define SET_TX_DESC_TX_BUFF_SIZE_8197F(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TX_BUFF_SIZE_8197F(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) -#define SET_TX_DESC_TXDESC_CHECKSUM_8197F(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) -#define GET_TX_DESC_TXDESC_CHECKSUM_8197F(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) -#define SET_TX_DESC_TIMESTAMP_8197F(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) -#define GET_TX_DESC_TIMESTAMP_8197F(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc) +#define SET_TX_DESC_DMA_TXAGG_NUM_8197F(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8197F(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8197F(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8197F(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8197F(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8197F(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8197F(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8197F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8197F(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8197F(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8197F(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8197F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) /*TXDESC_WORD8*/ -#define SET_TX_DESC_TXWIFI_CP_8197F(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) -#define GET_TX_DESC_TXWIFI_CP_8197F(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc) -#define SET_TX_DESC_MAC_CP_8197F(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value) -#define GET_TX_DESC_MAC_CP_8197F(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc) -#define SET_TX_DESC_STW_PKTRE_DIS_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_PKTRE_DIS_8197F(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RB_DIS_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RB_DIS_8197F(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RATE_DIS_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RATE_DIS_8197F(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_ANT_DIS_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_ANT_DIS_8197F(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc) -#define SET_TX_DESC_STW_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value) -#define GET_TX_DESC_STW_EN_8197F(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc) -#define SET_TX_DESC_SMH_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SMH_EN_8197F(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc) -#define SET_TX_DESC_TAILPAGE_L_8197F(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_L_8197F(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc) -#define SET_TX_DESC_SDIO_DMASEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SDIO_DMASEQ_8197F(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_L_8197F(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_L_8197F(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) -#define SET_TX_DESC_EN_HWSEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWSEQ_8197F(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc) -#define SET_TX_DESC_EN_HWEXSEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWEXSEQ_8197F(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) -#define SET_TX_DESC_DATA_RC_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RC_8197F(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc) -#define SET_TX_DESC_BAR_RTY_TH_8197F(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) -#define GET_TX_DESC_BAR_RTY_TH_8197F(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc) -#define SET_TX_DESC_RTS_RC_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RC_8197F(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc) +#define SET_TX_DESC_TXWIFI_CP_8197F(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8197F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8197F(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8197F(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8197F(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8197F(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8197F(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8197F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8197F(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8197F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8197F(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8197F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8197F(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8197F(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8197F(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8197F(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8197F(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8197F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8197F(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8197F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8197F(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8197F(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_8197F(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_8197F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc) +#define SET_TX_DESC_EN_HWEXSEQ_8197F(txdesc, value) \ + SET_TX_DESC_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWEXSEQ_8197F(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_DATA_RC_8197F(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8197F(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8197F(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8197F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8197F(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8197F(txdesc) GET_TX_DESC_RTS_RC(txdesc) /*TXDESC_WORD9*/ -#define SET_TX_DESC_TAILPAGE_H_8197F(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_H_8197F(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_H_8197F(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_H_8197F(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) -#define SET_TX_DESC_SW_SEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SW_SEQ_8197F(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc) -#define SET_TX_DESC_TXBF_PATH_8197F(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) -#define GET_TX_DESC_TXBF_PATH_8197F(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc) -#define SET_TX_DESC_PADDING_LEN_8197F(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_PADDING_LEN_8197F(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) +#define SET_TX_DESC_TAILPAGE_H_8197F(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8197F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8197F(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8197F(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8197F(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8197F(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8197F(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8197F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8197F(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8197F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) /*WORD10*/ -#define SET_TX_DESC_MU_DATARATE_8197F(__pTxDesc, __Value) SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_MU_DATARATE_8197F(__pTxDesc) GET_TX_DESC_MU_DATARATE(__pTxDesc) -#define SET_TX_DESC_MU_RC_8197F(__pTxDesc, __Value) SET_TX_DESC_MU_RC(__pTxDesc, __Value) -#define GET_TX_DESC_MU_RC_8197F(__pTxDesc) GET_TX_DESC_MU_RC(__pTxDesc) -#define SET_TX_DESC_SND_PKT_SEL_8197F(__pTxDesc, __Value) SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_SND_PKT_SEL_8197F(__pTxDesc) GET_TX_DESC_SND_PKT_SEL(__pTxDesc) - #endif #if (HALMAC_8821C_SUPPORT) /*TXDESC_WORD0*/ -#define SET_TX_DESC_DISQSELSEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_DISQSELSEQ_8821C(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc) -#define SET_TX_DESC_GF_8821C(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value) -#define GET_TX_DESC_GF_8821C(__pTxDesc) GET_TX_DESC_GF(__pTxDesc) -#define SET_TX_DESC_NO_ACM_8821C(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value) -#define GET_TX_DESC_NO_ACM_8821C(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc) -#define SET_TX_DESC_BCNPKT_TSF_CTRL_8821C(__pTxDesc, __Value) SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) -#define GET_TX_DESC_BCNPKT_TSF_CTRL_8821C(__pTxDesc) GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) -#define SET_TX_DESC_AMSDU_PAD_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AMSDU_PAD_EN_8821C(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) -#define SET_TX_DESC_LS_8821C(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value) -#define GET_TX_DESC_LS_8821C(__pTxDesc) GET_TX_DESC_LS(__pTxDesc) -#define SET_TX_DESC_HTC_8821C(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value) -#define GET_TX_DESC_HTC_8821C(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc) -#define SET_TX_DESC_BMC_8821C(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value) -#define GET_TX_DESC_BMC_8821C(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc) -#define SET_TX_DESC_OFFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_OFFSET_8821C(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc) -#define SET_TX_DESC_TXPKTSIZE_8821C(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TXPKTSIZE_8821C(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc) - -/*TXDESC_WORD1*/ - -#define SET_TX_DESC_MOREDATA_8821C(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value) -#define GET_TX_DESC_MOREDATA_8821C(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc) -#define SET_TX_DESC_PKT_OFFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_PKT_OFFSET_8821C(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc) -#define SET_TX_DESC_SEC_TYPE_8821C(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) -#define GET_TX_DESC_SEC_TYPE_8821C(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc) -#define SET_TX_DESC_EN_DESC_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) -#define GET_TX_DESC_EN_DESC_ID_8821C(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc) -#define SET_TX_DESC_RATE_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value) -#define GET_TX_DESC_RATE_ID_8821C(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc) -#define SET_TX_DESC_PIFS_8821C(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value) -#define GET_TX_DESC_PIFS_8821C(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc) -#define SET_TX_DESC_LSIG_TXOP_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) -#define GET_TX_DESC_LSIG_TXOP_EN_8821C(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) -#define SET_TX_DESC_RD_NAV_EXT_8821C(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) -#define GET_TX_DESC_RD_NAV_EXT_8821C(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc) -#define SET_TX_DESC_QSEL_8821C(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value) -#define GET_TX_DESC_QSEL_8821C(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc) -#define SET_TX_DESC_MACID_8821C(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value) -#define GET_TX_DESC_MACID_8821C(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc) +#define SET_TX_DESC_DISQSELSEQ_8821C(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8821C(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8821C(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8821C(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8821C(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8821C(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_8821C(txdesc, value) \ + SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL_8821C(txdesc) \ + GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8821C(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8821C(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8821C(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8821C(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8821C(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8821C(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8821C(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8821C(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8821C(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8821C(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8821C(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8821C(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_MOREDATA_8821C(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8821C(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8821C(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8821C(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8821C(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8821C(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8821C(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8821C(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8821C(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8821C(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8821C(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8821C(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8821C(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8821C(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8821C(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8821C(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8821C(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8821C(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8821C(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8821C(txdesc) GET_TX_DESC_MACID(txdesc) /*TXDESC_WORD2*/ -#define SET_TX_DESC_HW_AES_IV_8821C(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) -#define GET_TX_DESC_HW_AES_IV_8821C(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc) -#define SET_TX_DESC_FTM_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value) -#define GET_TX_DESC_FTM_EN_8821C(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc) -#define SET_TX_DESC_G_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value) -#define GET_TX_DESC_G_ID_8821C(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc) -#define SET_TX_DESC_BT_NULL_8821C(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value) -#define GET_TX_DESC_BT_NULL_8821C(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc) -#define SET_TX_DESC_AMPDU_DENSITY_8821C(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_DENSITY_8821C(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) -#define SET_TX_DESC_SPE_RPT_8821C(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) -#define GET_TX_DESC_SPE_RPT_8821C(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc) -#define SET_TX_DESC_RAW_8821C(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value) -#define GET_TX_DESC_RAW_8821C(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc) -#define SET_TX_DESC_MOREFRAG_8821C(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) -#define GET_TX_DESC_MOREFRAG_8821C(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc) -#define SET_TX_DESC_BK_8821C(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value) -#define GET_TX_DESC_BK_8821C(__pTxDesc) GET_TX_DESC_BK(__pTxDesc) -#define SET_TX_DESC_NULL_1_8821C(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_1_8821C(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc) -#define SET_TX_DESC_NULL_0_8821C(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_0_8821C(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc) -#define SET_TX_DESC_RDG_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RDG_EN_8821C(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc) -#define SET_TX_DESC_AGG_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AGG_EN_8821C(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc) -#define SET_TX_DESC_CCA_RTS_8821C(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) -#define GET_TX_DESC_CCA_RTS_8821C(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc) -#define SET_TX_DESC_TRI_FRAME_8821C(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) -#define GET_TX_DESC_TRI_FRAME_8821C(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc) -#define SET_TX_DESC_P_AID_8821C(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value) -#define GET_TX_DESC_P_AID_8821C(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc) +#define SET_TX_DESC_HW_AES_IV_8821C(txdesc, value) \ + SET_TX_DESC_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8821C(txdesc) GET_TX_DESC_HW_AES_IV(txdesc) +#define SET_TX_DESC_FTM_EN_8821C(txdesc, value) \ + SET_TX_DESC_FTM_EN(txdesc, value) +#define GET_TX_DESC_FTM_EN_8821C(txdesc) GET_TX_DESC_FTM_EN(txdesc) +#define SET_TX_DESC_G_ID_8821C(txdesc, value) SET_TX_DESC_G_ID(txdesc, value) +#define GET_TX_DESC_G_ID_8821C(txdesc) GET_TX_DESC_G_ID(txdesc) +#define SET_TX_DESC_BT_NULL_8821C(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8821C(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8821C(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8821C(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8821C(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8821C(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8821C(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8821C(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8821C(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8821C(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8821C(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8821C(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8821C(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8821C(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8821C(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8821C(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8821C(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8821C(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8821C(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8821C(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8821C(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8821C(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_TRI_FRAME_8821C(txdesc, value) \ + SET_TX_DESC_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_TRI_FRAME_8821C(txdesc) GET_TX_DESC_TRI_FRAME(txdesc) +#define SET_TX_DESC_P_AID_8821C(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8821C(txdesc) GET_TX_DESC_P_AID(txdesc) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME_8821C(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_MAX_TIME_8821C(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) -#define SET_TX_DESC_NDPA_8821C(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value) -#define GET_TX_DESC_NDPA_8821C(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc) -#define SET_TX_DESC_MAX_AGG_NUM_8821C(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_MAX_AGG_NUM_8821C(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) -#define SET_TX_DESC_USE_MAX_TIME_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) -#define GET_TX_DESC_USE_MAX_TIME_EN_8821C(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) -#define SET_TX_DESC_NAVUSEHDR_8821C(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) -#define GET_TX_DESC_NAVUSEHDR_8821C(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc) -#define SET_TX_DESC_CHK_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value) -#define GET_TX_DESC_CHK_EN_8821C(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc) -#define SET_TX_DESC_HW_RTS_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_HW_RTS_EN_8821C(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSEN_8821C(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value) -#define GET_TX_DESC_RTSEN_8821C(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc) -#define SET_TX_DESC_CTS2SELF_8821C(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) -#define GET_TX_DESC_CTS2SELF_8821C(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc) -#define SET_TX_DESC_DISDATAFB_8821C(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISDATAFB_8821C(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc) -#define SET_TX_DESC_DISRTSFB_8821C(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISRTSFB_8821C(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc) -#define SET_TX_DESC_USE_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_USE_RATE_8821C(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc) -#define SET_TX_DESC_HW_SSN_SEL_8821C(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_HW_SSN_SEL_8821C(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc) -#define SET_TX_DESC_WHEADER_LEN_8821C(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_WHEADER_LEN_8821C(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc) +#define SET_TX_DESC_AMPDU_MAX_TIME_8821C(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8821C(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8821C(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8821C(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8821C(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8821C(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8821C(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8821C(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8821C(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8821C(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8821C(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8821C(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8821C(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8821C(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8821C(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8821C(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8821C(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8821C(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8821C(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8821C(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8821C(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8821C(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8821C(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8821C(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8821C(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8821C(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8821C(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8821C(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) /*TXDESC_WORD4*/ -#define SET_TX_DESC_PCTS_MASK_IDX_8821C(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_MASK_IDX_8821C(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) -#define SET_TX_DESC_PCTS_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_EN_8821C(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSRATE_8821C(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTSRATE_8821C(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc) -#define SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_DATA_RTY_LMT_8821C(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) -#define SET_TX_DESC_RTY_LMT_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RTY_LMT_EN_8821C(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_TRY_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_TRY_RATE_8821C(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc) -#define SET_TX_DESC_DATARATE_8821C(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATARATE_8821C(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc) +#define SET_TX_DESC_PCTS_MASK_IDX_8821C(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8821C(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8821C(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8821C(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8821C(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8821C(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8821C(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8821C(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8821C(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8821C(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8821C(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8821C(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8821C(txdesc) GET_TX_DESC_DATARATE(txdesc) /*TXDESC_WORD5*/ -#define SET_TX_DESC_POLLUTED_8821C(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value) -#define GET_TX_DESC_POLLUTED_8821C(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc) -#define SET_TX_DESC_TXPWR_OFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) -#define GET_TX_DESC_TXPWR_OFSET_8821C(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc) -#define SET_TX_DESC_TX_ANT_8821C(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value) -#define GET_TX_DESC_TX_ANT_8821C(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc) -#define SET_TX_DESC_PORT_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value) -#define GET_TX_DESC_PORT_ID_8821C(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc) -#define SET_TX_DESC_MULTIPLE_PORT_8821C(__pTxDesc, __Value) SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) -#define GET_TX_DESC_MULTIPLE_PORT_8821C(__pTxDesc) GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) -#define SET_TX_DESC_SIGNALING_TAPKT_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SIGNALING_TAPKT_EN_8821C(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_SC_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SC_8821C(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc) -#define SET_TX_DESC_RTS_SHORT_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SHORT_8821C(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc) -#define SET_TX_DESC_VCS_STBC_8821C(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_VCS_STBC_8821C(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_STBC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_STBC_8821C(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_LDPC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_LDPC_8821C(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc) -#define SET_TX_DESC_DATA_BW_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_BW_8821C(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc) -#define SET_TX_DESC_DATA_SHORT_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SHORT_8821C(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc) -#define SET_TX_DESC_DATA_SC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SC_8821C(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc) +#define SET_TX_DESC_POLLUTED_8821C(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8821C(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_8821C(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_8821C(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc) +#define SET_TX_DESC_TX_ANT_8821C(txdesc, value) \ + SET_TX_DESC_TX_ANT(txdesc, value) +#define GET_TX_DESC_TX_ANT_8821C(txdesc) GET_TX_DESC_TX_ANT(txdesc) +#define SET_TX_DESC_PORT_ID_8821C(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8821C(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_MULTIPLE_PORT_8821C(txdesc, value) \ + SET_TX_DESC_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_MULTIPLE_PORT_8821C(txdesc) \ + GET_TX_DESC_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8821C(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8821C(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8821C(txdesc, value) \ + SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) +#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8821C(txdesc) \ + GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8821C(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8821C(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8821C(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8821C(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8821C(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8821C(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8821C(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8821C(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8821C(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8821C(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8821C(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8821C(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8821C(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8821C(txdesc) GET_TX_DESC_DATA_SC(txdesc) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_D_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_D_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc) -#define SET_TX_DESC_ANT_MAPD_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPD_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc) -#define SET_TX_DESC_ANT_MAPC_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPC_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc) -#define SET_TX_DESC_ANT_MAPB_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPB_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc) -#define SET_TX_DESC_ANT_MAPA_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPA_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc) -#define SET_TX_DESC_ANTSEL_C_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_C_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc) -#define SET_TX_DESC_ANTSEL_B_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_B_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc) -#define SET_TX_DESC_ANTSEL_A_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_A_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc) -#define SET_TX_DESC_MBSSID_8821C(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value) -#define GET_TX_DESC_MBSSID_8821C(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc) -#define SET_TX_DESC_SW_DEFINE_8821C(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) -#define GET_TX_DESC_SW_DEFINE_8821C(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc) +#define SET_TX_DESC_ANTSEL_D_8821C(txdesc, value) \ + SET_TX_DESC_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_ANTSEL_D_8821C(txdesc) GET_TX_DESC_ANTSEL_D(txdesc) +#define SET_TX_DESC_ANT_MAPD_8821C(txdesc, value) \ + SET_TX_DESC_ANT_MAPD(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8821C(txdesc) GET_TX_DESC_ANT_MAPD(txdesc) +#define SET_TX_DESC_ANT_MAPC_8821C(txdesc, value) \ + SET_TX_DESC_ANT_MAPC(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8821C(txdesc) GET_TX_DESC_ANT_MAPC(txdesc) +#define SET_TX_DESC_ANT_MAPB_8821C(txdesc, value) \ + SET_TX_DESC_ANT_MAPB(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8821C(txdesc) GET_TX_DESC_ANT_MAPB(txdesc) +#define SET_TX_DESC_ANT_MAPA_8821C(txdesc, value) \ + SET_TX_DESC_ANT_MAPA(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8821C(txdesc) GET_TX_DESC_ANT_MAPA(txdesc) +#define SET_TX_DESC_ANTSEL_C_8821C(txdesc, value) \ + SET_TX_DESC_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8821C(txdesc) GET_TX_DESC_ANTSEL_C(txdesc) +#define SET_TX_DESC_ANTSEL_B_8821C(txdesc, value) \ + SET_TX_DESC_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8821C(txdesc) GET_TX_DESC_ANTSEL_B(txdesc) +#define SET_TX_DESC_ANTSEL_A_8821C(txdesc, value) \ + SET_TX_DESC_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8821C(txdesc) GET_TX_DESC_ANTSEL_A(txdesc) +#define SET_TX_DESC_MBSSID_8821C(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8821C(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SW_DEFINE_8821C(txdesc, value) \ + SET_TX_DESC_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_SW_DEFINE_8821C(txdesc) GET_TX_DESC_SW_DEFINE(txdesc) /*TXDESC_WORD7*/ -#define SET_TX_DESC_DMA_TXAGG_NUM_8821C(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_DMA_TXAGG_NUM_8821C(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) -#define SET_TX_DESC_FINAL_DATA_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_FINAL_DATA_RATE_8821C(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) -#define SET_TX_DESC_NTX_MAP_8821C(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) -#define GET_TX_DESC_NTX_MAP_8821C(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc) -#define SET_TX_DESC_TX_BUFF_SIZE_8821C(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TX_BUFF_SIZE_8821C(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) -#define SET_TX_DESC_TXDESC_CHECKSUM_8821C(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) -#define GET_TX_DESC_TXDESC_CHECKSUM_8821C(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) -#define SET_TX_DESC_TIMESTAMP_8821C(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) -#define GET_TX_DESC_TIMESTAMP_8821C(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc) +#define SET_TX_DESC_DMA_TXAGG_NUM_8821C(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8821C(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8821C(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8821C(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8821C(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8821C(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8821C(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8821C(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8821C(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8821C(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8821C(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8821C(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) /*TXDESC_WORD8*/ -#define SET_TX_DESC_TXWIFI_CP_8821C(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) -#define GET_TX_DESC_TXWIFI_CP_8821C(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc) -#define SET_TX_DESC_MAC_CP_8821C(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value) -#define GET_TX_DESC_MAC_CP_8821C(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc) -#define SET_TX_DESC_STW_PKTRE_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_PKTRE_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RB_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RB_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RATE_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RATE_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_ANT_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_ANT_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc) -#define SET_TX_DESC_STW_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value) -#define GET_TX_DESC_STW_EN_8821C(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc) -#define SET_TX_DESC_SMH_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SMH_EN_8821C(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc) -#define SET_TX_DESC_TAILPAGE_L_8821C(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_L_8821C(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc) -#define SET_TX_DESC_SDIO_DMASEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SDIO_DMASEQ_8821C(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_L_8821C(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_L_8821C(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) -#define SET_TX_DESC_EN_HWSEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWSEQ_8821C(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc) -#define SET_TX_DESC_EN_HWEXSEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWEXSEQ_8821C(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) -#define SET_TX_DESC_DATA_RC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RC_8821C(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc) -#define SET_TX_DESC_BAR_RTY_TH_8821C(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) -#define GET_TX_DESC_BAR_RTY_TH_8821C(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc) -#define SET_TX_DESC_RTS_RC_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RC_8821C(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc) +#define SET_TX_DESC_TXWIFI_CP_8821C(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8821C(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8821C(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8821C(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8821C(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8821C(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8821C(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8821C(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8821C(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8821C(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8821C(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8821C(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8821C(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8821C(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8821C(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8821C(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8821C(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8821C(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8821C(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8821C(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8821C(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8821C(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_8821C(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_8821C(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc) +#define SET_TX_DESC_EN_HWEXSEQ_8821C(txdesc, value) \ + SET_TX_DESC_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWEXSEQ_8821C(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_DATA_RC_8821C(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8821C(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8821C(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8821C(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8821C(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8821C(txdesc) GET_TX_DESC_RTS_RC(txdesc) /*TXDESC_WORD9*/ -#define SET_TX_DESC_TAILPAGE_H_8821C(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_H_8821C(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_H_8821C(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_H_8821C(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) -#define SET_TX_DESC_SW_SEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SW_SEQ_8821C(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc) -#define SET_TX_DESC_TXBF_PATH_8821C(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) -#define GET_TX_DESC_TXBF_PATH_8821C(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc) -#define SET_TX_DESC_PADDING_LEN_8821C(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_PADDING_LEN_8821C(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) +#define SET_TX_DESC_TAILPAGE_H_8821C(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8821C(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8821C(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8821C(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8821C(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8821C(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8821C(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8821C(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8821C(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8821C(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) /*WORD10*/ -#define SET_TX_DESC_MU_DATARATE_8821C(__pTxDesc, __Value) SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_MU_DATARATE_8821C(__pTxDesc) GET_TX_DESC_MU_DATARATE(__pTxDesc) -#define SET_TX_DESC_MU_RC_8821C(__pTxDesc, __Value) SET_TX_DESC_MU_RC(__pTxDesc, __Value) -#define GET_TX_DESC_MU_RC_8821C(__pTxDesc) GET_TX_DESC_MU_RC(__pTxDesc) -#define SET_TX_DESC_SND_PKT_SEL_8821C(__pTxDesc, __Value) SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_SND_PKT_SEL_8821C(__pTxDesc) GET_TX_DESC_SND_PKT_SEL(__pTxDesc) +#define SET_TX_DESC_MU_DATARATE_8821C(txdesc, value) \ + SET_TX_DESC_MU_DATARATE(txdesc, value) +#define GET_TX_DESC_MU_DATARATE_8821C(txdesc) GET_TX_DESC_MU_DATARATE(txdesc) +#define SET_TX_DESC_MU_RC_8821C(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value) +#define GET_TX_DESC_MU_RC_8821C(txdesc) GET_TX_DESC_MU_RC(txdesc) +#define SET_TX_DESC_SND_PKT_SEL_8821C(txdesc, value) \ + SET_TX_DESC_SND_PKT_SEL(txdesc, value) +#define GET_TX_DESC_SND_PKT_SEL_8821C(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc) #endif -#if (HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) /*TXDESC_WORD0*/ -#define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value) -#define GET_TX_DESC_GF_8188F(__pTxDesc) GET_TX_DESC_GF(__pTxDesc) -#define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value) -#define GET_TX_DESC_NO_ACM_8188F(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc) -#define SET_TX_DESC_LS_8188F(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value) -#define GET_TX_DESC_LS_8188F(__pTxDesc) GET_TX_DESC_LS(__pTxDesc) -#define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value) -#define GET_TX_DESC_HTC_8188F(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc) -#define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value) -#define GET_TX_DESC_BMC_8188F(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc) -#define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_OFFSET_8188F(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc) -#define SET_TX_DESC_TXPKTSIZE_8188F(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TXPKTSIZE_8188F(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc) - -/*TXDESC_WORD1*/ - -#define SET_TX_DESC_MOREDATA_8188F(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value) -#define GET_TX_DESC_MOREDATA_8188F(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc) -#define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc) -#define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) -#define GET_TX_DESC_SEC_TYPE_8188F(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc) -#define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) -#define GET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc) -#define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value) -#define GET_TX_DESC_RATE_ID_8188F(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc) -#define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value) -#define GET_TX_DESC_PIFS_8188F(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc) -#define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) -#define GET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) -#define SET_TX_DESC_RD_NAV_EXT_8188F(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) -#define GET_TX_DESC_RD_NAV_EXT_8188F(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc) -#define SET_TX_DESC_QSEL_8188F(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value) -#define GET_TX_DESC_QSEL_8188F(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc) -#define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value) -#define GET_TX_DESC_MACID_8188F(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc) +#define SET_TX_DESC_IE_END_BODY_8814B(txdesc, value) \ + SET_TX_DESC_IE_END_BODY(txdesc, value) +#define GET_TX_DESC_IE_END_BODY_8814B(txdesc) GET_TX_DESC_IE_END_BODY(txdesc) +#define SET_TX_DESC_AGG_EN_8814B(txdesc, value) \ + SET_TX_DESC_AGG_EN_V1(txdesc, value) +#define GET_TX_DESC_AGG_EN_8814B(txdesc) GET_TX_DESC_AGG_EN_V1(txdesc) +#define SET_TX_DESC_BK_8814B(txdesc, value) SET_TX_DESC_BK_V1(txdesc, value) +#define GET_TX_DESC_BK_8814B(txdesc) GET_TX_DESC_BK_V1(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8814B(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET_V1(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8814B(txdesc) GET_TX_DESC_PKT_OFFSET_V1(txdesc) +#define SET_TX_DESC_OFFSET_8814B(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8814B(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8814B(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8814B(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_AMSDU_8814B(txdesc, value) SET_TX_DESC_AMSDU(txdesc, value) +#define GET_TX_DESC_AMSDU_8814B(txdesc) GET_TX_DESC_AMSDU(txdesc) +#define SET_TX_DESC_HW_AES_IV_8814B(txdesc, value) \ + SET_TX_DESC_HW_AES_IV_V1(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8814B(txdesc) GET_TX_DESC_HW_AES_IV_V1(txdesc) +#define SET_TX_DESC_MHR_CP_8814B(txdesc, value) \ + SET_TX_DESC_MHR_CP(txdesc, value) +#define GET_TX_DESC_MHR_CP_8814B(txdesc) GET_TX_DESC_MHR_CP(txdesc) +#define SET_TX_DESC_SMH_EN_8814B(txdesc, value) \ + SET_TX_DESC_SMH_EN_V1(txdesc, value) +#define GET_TX_DESC_SMH_EN_8814B(txdesc) GET_TX_DESC_SMH_EN_V1(txdesc) +#define SET_TX_DESC_SMH_CAM_8814B(txdesc, value) \ + SET_TX_DESC_SMH_CAM(txdesc, value) +#define GET_TX_DESC_SMH_CAM_8814B(txdesc) GET_TX_DESC_SMH_CAM(txdesc) +#define SET_TX_DESC_EXT_EDCA_8814B(txdesc, value) \ + SET_TX_DESC_EXT_EDCA(txdesc, value) +#define GET_TX_DESC_EXT_EDCA_8814B(txdesc) GET_TX_DESC_EXT_EDCA(txdesc) +#define SET_TX_DESC_QSEL_8814B(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8814B(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8814B(txdesc, value) \ + SET_TX_DESC_MACID_V1(txdesc, value) +#define GET_TX_DESC_MACID_8814B(txdesc) GET_TX_DESC_MACID_V1(txdesc) /*TXDESC_WORD2*/ -#define SET_TX_DESC_FTM_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value) -#define GET_TX_DESC_FTM_EN_8188F(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc) -#define SET_TX_DESC_G_ID_8188F(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value) -#define GET_TX_DESC_G_ID_8188F(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc) -#define SET_TX_DESC_BT_NULL_8188F(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value) -#define GET_TX_DESC_BT_NULL_8188F(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc) -#define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) -#define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) -#define GET_TX_DESC_SPE_RPT_8188F(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc) -#define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value) -#define GET_TX_DESC_RAW_8188F(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc) -#define SET_TX_DESC_MOREFRAG_8188F(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) -#define GET_TX_DESC_MOREFRAG_8188F(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc) -#define SET_TX_DESC_BK_8188F(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value) -#define GET_TX_DESC_BK_8188F(__pTxDesc) GET_TX_DESC_BK(__pTxDesc) -#define SET_TX_DESC_NULL_1_8188F(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_1_8188F(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc) -#define SET_TX_DESC_NULL_0_8188F(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_0_8188F(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc) -#define SET_TX_DESC_RDG_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RDG_EN_8188F(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc) -#define SET_TX_DESC_AGG_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AGG_EN_8188F(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc) -#define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) -#define GET_TX_DESC_CCA_RTS_8188F(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc) -#define SET_TX_DESC_TRI_FRAME_8188F(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) -#define GET_TX_DESC_TRI_FRAME_8188F(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc) -#define SET_TX_DESC_P_AID_8188F(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value) -#define GET_TX_DESC_P_AID_8188F(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc) +#define SET_TX_DESC_CHK_EN_8814B(txdesc, value) \ + SET_TX_DESC_CHK_EN_V1(txdesc, value) +#define GET_TX_DESC_CHK_EN_8814B(txdesc) GET_TX_DESC_CHK_EN_V1(txdesc) +#define SET_TX_DESC_DMA_PRI_8814B(txdesc, value) \ + SET_TX_DESC_DMA_PRI(txdesc, value) +#define GET_TX_DESC_DMA_PRI_8814B(txdesc) GET_TX_DESC_DMA_PRI(txdesc) +#define SET_TX_DESC_MAX_AMSDU_MODE_8814B(txdesc, value) \ + SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value) +#define GET_TX_DESC_MAX_AMSDU_MODE_8814B(txdesc) \ + GET_TX_DESC_MAX_AMSDU_MODE(txdesc) +#define SET_TX_DESC_DMA_TXAGG_NUM_8814B(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8814B(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8814B(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8814B(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) -#define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value) -#define GET_TX_DESC_NDPA_8188F(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc) -#define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) -#define SET_TX_DESC_USE_MAX_TIME_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) -#define GET_TX_DESC_USE_MAX_TIME_EN_8188F(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) -#define SET_TX_DESC_NAVUSEHDR_8188F(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) -#define GET_TX_DESC_NAVUSEHDR_8188F(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc) -#define SET_TX_DESC_HW_RTS_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_HW_RTS_EN_8188F(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSEN_8188F(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value) -#define GET_TX_DESC_RTSEN_8188F(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc) -#define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) -#define GET_TX_DESC_CTS2SELF_8188F(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc) -#define SET_TX_DESC_DISDATAFB_8188F(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISDATAFB_8188F(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc) -#define SET_TX_DESC_DISRTSFB_8188F(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISRTSFB_8188F(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc) -#define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_USE_RATE_8188F(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc) -#define SET_TX_DESC_HW_SSN_SEL_8188F(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_HW_SSN_SEL_8188F(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc) +#define SET_TX_DESC_OFFLOAD_SIZE_8814B(txdesc, value) \ + SET_TX_DESC_OFFLOAD_SIZE(txdesc, value) +#define GET_TX_DESC_OFFLOAD_SIZE_8814B(txdesc) GET_TX_DESC_OFFLOAD_SIZE(txdesc) +#define SET_TX_DESC_CHANNEL_DMA_8814B(txdesc, value) \ + SET_TX_DESC_CHANNEL_DMA(txdesc, value) +#define GET_TX_DESC_CHANNEL_DMA_8814B(txdesc) GET_TX_DESC_CHANNEL_DMA(txdesc) +#define SET_TX_DESC_IE_CNT_8814B(txdesc, value) \ + SET_TX_DESC_IE_CNT(txdesc, value) +#define GET_TX_DESC_IE_CNT_8814B(txdesc) GET_TX_DESC_IE_CNT(txdesc) +#define SET_TX_DESC_IE_CNT_EN_8814B(txdesc, value) \ + SET_TX_DESC_IE_CNT_EN(txdesc, value) +#define GET_TX_DESC_IE_CNT_EN_8814B(txdesc) GET_TX_DESC_IE_CNT_EN(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8814B(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN_V1(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8814B(txdesc) GET_TX_DESC_WHEADER_LEN_V1(txdesc) /*TXDESC_WORD4*/ -#define SET_TX_DESC_PCTS_MASK_IDX_8188F(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_MASK_IDX_8188F(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) -#define SET_TX_DESC_PCTS_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_EN_8188F(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSRATE_8188F(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTSRATE_8188F(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc) -#define SET_TX_DESC_RTS_DATA_RTY_LMT_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_DATA_RTY_LMT_8188F(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) -#define SET_TX_DESC_RTY_LMT_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RTY_LMT_EN_8188F(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8188F(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8188F(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_TRY_RATE_8188F(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_TRY_RATE_8188F(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc) -#define SET_TX_DESC_DATARATE_8188F(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATARATE_8188F(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc) +/*TXDESC_WORD5*/ + +/*TXDESC_WORD6*/ + +/*TXDESC_WORD7*/ + +/*TXDESC_WORD8*/ + +/*TXDESC_WORD9*/ + +/*WORD10*/ + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_DISQSELSEQ_8198F(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8198F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8198F(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8198F(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8198F(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8198F(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_8198F(txdesc, value) \ + SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL_8198F(txdesc) \ + GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8198F(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8198F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8198F(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8198F(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8198F(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8198F(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8198F(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8198F(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8198F(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8198F(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8198F(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8198F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_HW_AES_IV_8198F(txdesc, value) \ + SET_TX_DESC_HW_AES_IV_V2(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8198F(txdesc) GET_TX_DESC_HW_AES_IV_V2(txdesc) +#define SET_TX_DESC_FTM_EN_8198F(txdesc, value) \ + SET_TX_DESC_FTM_EN_V1(txdesc, value) +#define GET_TX_DESC_FTM_EN_8198F(txdesc) GET_TX_DESC_FTM_EN_V1(txdesc) +#define SET_TX_DESC_MOREDATA_8198F(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8198F(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8198F(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8198F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8198F(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8198F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8198F(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8198F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8198F(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8198F(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8198F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8198F(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8198F(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8198F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8198F(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8198F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8198F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8198F(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_SPECIAL_CW_8198F(txdesc, value) \ + SET_TX_DESC_SPECIAL_CW(txdesc, value) +#define GET_TX_DESC_SPECIAL_CW_8198F(txdesc) GET_TX_DESC_SPECIAL_CW(txdesc) +#define SET_TX_DESC_MACID_8198F(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8198F(txdesc) GET_TX_DESC_MACID(txdesc) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_ANTCEL_D_8198F(txdesc, value) \ + SET_TX_DESC_ANTCEL_D_V1(txdesc, value) +#define GET_TX_DESC_ANTCEL_D_8198F(txdesc) GET_TX_DESC_ANTCEL_D_V1(txdesc) +#define SET_TX_DESC_ANTSEL_C_8198F(txdesc, value) \ + SET_TX_DESC_ANTSEL_C_V1(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8198F(txdesc) GET_TX_DESC_ANTSEL_C_V1(txdesc) +#define SET_TX_DESC_BT_NULL_8198F(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8198F(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8198F(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8198F(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8198F(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8198F(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8198F(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8198F(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8198F(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8198F(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8198F(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8198F(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8198F(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8198F(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8198F(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8198F(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8198F(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8198F(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8198F(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8198F(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8198F(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8198F(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_TRI_FRAME_8198F(txdesc, value) \ + SET_TX_DESC_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_TRI_FRAME_8198F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc) +#define SET_TX_DESC_P_AID_8198F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8198F(txdesc) GET_TX_DESC_P_AID(txdesc) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_AMPDU_MAX_TIME_8198F(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8198F(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8198F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8198F(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8198F(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8198F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8198F(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8198F(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8198F(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8198F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8198F(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8198F(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8198F(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8198F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8198F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8198F(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8198F(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8198F(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8198F(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8198F(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8198F(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8198F(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8198F(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8198F(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8198F(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8198F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8198F(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8198F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_PCTS_MASK_IDX_8198F(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8198F(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8198F(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8198F(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8198F(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8198F(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8198F(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8198F(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8198F(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8198F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8198F(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8198F(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8198F(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8198F(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8198F(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8198F(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8198F(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8198F(txdesc) GET_TX_DESC_DATARATE(txdesc) /*TXDESC_WORD5*/ -#define SET_TX_DESC_TXPWR_OFSET_8188F(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) -#define GET_TX_DESC_TXPWR_OFSET_8188F(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc) -#define SET_TX_DESC_TX_ANT_8188F(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value) -#define GET_TX_DESC_TX_ANT_8188F(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc) -#define SET_TX_DESC_PORT_ID_8188F(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value) -#define GET_TX_DESC_PORT_ID_8188F(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc) -#define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SC_8188F(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc) -#define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SHORT_8188F(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc) -#define SET_TX_DESC_RTS_STBC_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_STBC_8188F(__pTxDesc) GET_TX_DESC_RTS_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_STBC_8188F(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_BW_8188F(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc) -#define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SHORT_8188F(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc) -#define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SC_8188F(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc) +#define SET_TX_DESC_POLLUTED_8198F(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8198F(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_8198F(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_8198F(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc) +#define SET_TX_DESC_DROP_ID_8198F(txdesc, value) \ + SET_TX_DESC_DROP_ID(txdesc, value) +#define GET_TX_DESC_DROP_ID_8198F(txdesc) GET_TX_DESC_DROP_ID(txdesc) +#define SET_TX_DESC_PORT_ID_8198F(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8198F(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_MULTIPLE_PORT_8198F(txdesc, value) \ + SET_TX_DESC_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_MULTIPLE_PORT_8198F(txdesc) \ + GET_TX_DESC_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8198F(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8198F(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_RTS_SC_8198F(txdesc, value) \ + SET_TX_DESC_RTS_SC(txdesc, value) +#define GET_TX_DESC_RTS_SC_8198F(txdesc) GET_TX_DESC_RTS_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8198F(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8198F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8198F(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8198F(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8198F(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8198F(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8198F(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8198F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8198F(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8198F(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8198F(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8198F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8198F(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8198F(txdesc) GET_TX_DESC_DATA_SC(txdesc) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_A_8188F(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc) -#define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value) -#define GET_TX_DESC_MBSSID_8188F(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc) -#define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) -#define GET_TX_DESC_SW_DEFINE_8188F(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc) +#define SET_TX_DESC_ANT_MAPD_8198F(txdesc, value) \ + SET_TX_DESC_ANT_MAPD_V1(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8198F(txdesc) GET_TX_DESC_ANT_MAPD_V1(txdesc) +#define SET_TX_DESC_ANT_MAPC_8198F(txdesc, value) \ + SET_TX_DESC_ANT_MAPC_V1(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8198F(txdesc) GET_TX_DESC_ANT_MAPC_V1(txdesc) +#define SET_TX_DESC_ANT_MAPB_8198F(txdesc, value) \ + SET_TX_DESC_ANT_MAPB_V1(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8198F(txdesc) GET_TX_DESC_ANT_MAPB_V1(txdesc) +#define SET_TX_DESC_ANT_MAPA_8198F(txdesc, value) \ + SET_TX_DESC_ANT_MAPA_V1(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8198F(txdesc) GET_TX_DESC_ANT_MAPA_V1(txdesc) +#define SET_TX_DESC_ANTSEL_B_8198F(txdesc, value) \ + SET_TX_DESC_ANTSEL_B_V1(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8198F(txdesc) GET_TX_DESC_ANTSEL_B_V1(txdesc) +#define SET_TX_DESC_ANTSEL_A_8198F(txdesc, value) \ + SET_TX_DESC_ANTSEL_A_V1(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8198F(txdesc) GET_TX_DESC_ANTSEL_A_V1(txdesc) +#define SET_TX_DESC_MBSSID_8198F(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8198F(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SWPS_SEQ_8198F(txdesc, value) \ + SET_TX_DESC_SWPS_SEQ(txdesc, value) +#define GET_TX_DESC_SWPS_SEQ_8198F(txdesc) GET_TX_DESC_SWPS_SEQ(txdesc) /*TXDESC_WORD7*/ -#define SET_TX_DESC_DMA_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_DMA_TXAGG_NUM_8188F(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) -#define SET_TX_DESC_TX_BUFF_SIZE_8188F(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TX_BUFF_SIZE_8188F(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) -#define SET_TX_DESC_TXDESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) -#define GET_TX_DESC_TXDESC_CHECKSUM_8188F(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) -#define SET_TX_DESC_TIMESTAMP_8188F(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) -#define GET_TX_DESC_TIMESTAMP_8188F(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc) +#define SET_TX_DESC_DMA_TXAGG_NUM_8198F(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8198F(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8198F(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8198F(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8198F(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8198F(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_ANTSEL_EN_8198F(txdesc, value) \ + SET_TX_DESC_ANTSEL_EN(txdesc, value) +#define GET_TX_DESC_ANTSEL_EN_8198F(txdesc) GET_TX_DESC_ANTSEL_EN(txdesc) +#define SET_TX_DESC_MBSSID_EX_8198F(txdesc, value) \ + SET_TX_DESC_MBSSID_EX(txdesc, value) +#define GET_TX_DESC_MBSSID_EX_8198F(txdesc) GET_TX_DESC_MBSSID_EX(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8198F(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8198F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8198F(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8198F(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8198F(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8198F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) /*TXDESC_WORD8*/ -#define SET_TX_DESC_TAILPAGE_L_8188F(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_L_8188F(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_L_8188F(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_L_8188F(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) -#define SET_TX_DESC_EN_HWSEQ_8188F(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWSEQ_8188F(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc) -#define SET_TX_DESC_DATA_RC_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RC_8188F(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc) -#define SET_TX_DESC_BAR_RTY_TH_8188F(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) -#define GET_TX_DESC_BAR_RTY_TH_8188F(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc) -#define SET_TX_DESC_RTS_RC_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RC_8188F(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc) +#define SET_TX_DESC_TXWIFI_CP_8198F(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8198F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8198F(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8198F(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8198F(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8198F(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8198F(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8198F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8198F(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8198F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8198F(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8198F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8198F(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8198F(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8198F(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8198F(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8198F(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8198F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8198F(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8198F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8198F(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8198F(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_8198F(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_8198F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc) +#define SET_TX_DESC_EN_HWEXSEQ_8198F(txdesc, value) \ + SET_TX_DESC_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWEXSEQ_8198F(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_DATA_RC_8198F(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8198F(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8198F(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8198F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8198F(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8198F(txdesc) GET_TX_DESC_RTS_RC(txdesc) /*TXDESC_WORD9*/ -#define SET_TX_DESC_SW_SEQ_8188F(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SW_SEQ_8188F(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc) -#define SET_TX_DESC_TXBF_PATH_8188F(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) -#define GET_TX_DESC_TXBF_PATH_8188F(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc) -#define SET_TX_DESC_PADDING_LEN_8188F(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_PADDING_LEN_8188F(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8188F(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8188F(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) +#define SET_TX_DESC_TAILPAGE_H_8198F(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8198F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8198F(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8198F(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8198F(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8198F(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8198F(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8198F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8198F(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8198F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8198F(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8198F(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) /*WORD10*/ - #endif +#if (HALMAC_8822C_SUPPORT) + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_DISQSELSEQ_8822C(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8822C(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8822C(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8822C(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8822C(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8822C(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822C(txdesc, value) \ + SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822C(txdesc) \ + GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8822C(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8822C(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8822C(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8822C(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8822C(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8822C(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8822C(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8822C(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8822C(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8822C(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8822C(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8822C(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_MOREDATA_8822C(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8822C(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8822C(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8822C(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8822C(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8822C(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8822C(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8822C(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8822C(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8822C(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8822C(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8822C(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8822C(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8822C(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8822C(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8822C(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8822C(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8822C(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8822C(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8822C(txdesc) GET_TX_DESC_MACID(txdesc) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_HW_AES_IV_8822C(txdesc, value) \ + SET_TX_DESC_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8822C(txdesc) GET_TX_DESC_HW_AES_IV(txdesc) +#define SET_TX_DESC_FTM_EN_8822C(txdesc, value) \ + SET_TX_DESC_FTM_EN(txdesc, value) +#define GET_TX_DESC_FTM_EN_8822C(txdesc) GET_TX_DESC_FTM_EN(txdesc) +#define SET_TX_DESC_G_ID_8822C(txdesc, value) SET_TX_DESC_G_ID(txdesc, value) +#define GET_TX_DESC_G_ID_8822C(txdesc) GET_TX_DESC_G_ID(txdesc) +#define SET_TX_DESC_BT_NULL_8822C(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8822C(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8822C(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8822C(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8822C(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8822C(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8822C(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8822C(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8822C(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8822C(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8822C(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8822C(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8822C(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8822C(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8822C(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8822C(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8822C(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8822C(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8822C(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8822C(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8822C(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8822C(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_TRI_FRAME_8822C(txdesc, value) \ + SET_TX_DESC_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_TRI_FRAME_8822C(txdesc) GET_TX_DESC_TRI_FRAME(txdesc) +#define SET_TX_DESC_P_AID_8822C(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8822C(txdesc) GET_TX_DESC_P_AID(txdesc) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_AMPDU_MAX_TIME_8822C(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8822C(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8822C(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8822C(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8822C(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8822C(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8822C(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8822C(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8822C(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8822C(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8822C(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8822C(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8822C(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8822C(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8822C(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8822C(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8822C(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8822C(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8822C(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8822C(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8822C(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8822C(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8822C(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8822C(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8822C(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8822C(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8822C(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8822C(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_PCTS_MASK_IDX_8822C(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8822C(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8822C(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8822C(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8822C(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8822C(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822C(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822C(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8822C(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8822C(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8822C(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8822C(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8822C(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8822C(txdesc) GET_TX_DESC_DATARATE(txdesc) + +/*TXDESC_WORD5*/ + +#define SET_TX_DESC_POLLUTED_8822C(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8822C(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_ANTSEL_EN_8822C(txdesc, value) \ + SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) +#define GET_TX_DESC_ANTSEL_EN_8822C(txdesc) GET_TX_DESC_ANTSEL_EN_V1(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_TYPE_8822C(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_TYPE_8822C(txdesc) \ + GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc) +#define SET_TX_DESC_TX_ANT_8822C(txdesc, value) \ + SET_TX_DESC_TX_ANT(txdesc, value) +#define GET_TX_DESC_TX_ANT_8822C(txdesc) GET_TX_DESC_TX_ANT(txdesc) +#define SET_TX_DESC_PORT_ID_8822C(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8822C(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_MULTIPLE_PORT_8822C(txdesc, value) \ + SET_TX_DESC_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_MULTIPLE_PORT_8822C(txdesc) \ + GET_TX_DESC_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822C(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822C(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8822C(txdesc, value) \ + SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) +#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8822C(txdesc) \ + GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8822C(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8822C(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8822C(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8822C(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8822C(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8822C(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8822C(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8822C(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8822C(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8822C(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8822C(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8822C(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8822C(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8822C(txdesc) GET_TX_DESC_DATA_SC(txdesc) + +/*TXDESC_WORD6*/ + +#define SET_TX_DESC_ANTSEL_D_8822C(txdesc, value) \ + SET_TX_DESC_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_ANTSEL_D_8822C(txdesc) GET_TX_DESC_ANTSEL_D(txdesc) +#define SET_TX_DESC_ANT_MAPD_8822C(txdesc, value) \ + SET_TX_DESC_ANT_MAPD(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8822C(txdesc) GET_TX_DESC_ANT_MAPD(txdesc) +#define SET_TX_DESC_ANT_MAPC_8822C(txdesc, value) \ + SET_TX_DESC_ANT_MAPC(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8822C(txdesc) GET_TX_DESC_ANT_MAPC(txdesc) +#define SET_TX_DESC_ANT_MAPB_8822C(txdesc, value) \ + SET_TX_DESC_ANT_MAPB(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8822C(txdesc) GET_TX_DESC_ANT_MAPB(txdesc) +#define SET_TX_DESC_ANT_MAPA_8822C(txdesc, value) \ + SET_TX_DESC_ANT_MAPA(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8822C(txdesc) GET_TX_DESC_ANT_MAPA(txdesc) +#define SET_TX_DESC_ANTSEL_C_8822C(txdesc, value) \ + SET_TX_DESC_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8822C(txdesc) GET_TX_DESC_ANTSEL_C(txdesc) +#define SET_TX_DESC_ANTSEL_B_8822C(txdesc, value) \ + SET_TX_DESC_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8822C(txdesc) GET_TX_DESC_ANTSEL_B(txdesc) +#define SET_TX_DESC_ANTSEL_A_8822C(txdesc, value) \ + SET_TX_DESC_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8822C(txdesc) GET_TX_DESC_ANTSEL_A(txdesc) +#define SET_TX_DESC_MBSSID_8822C(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8822C(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SW_DEFINE_8822C(txdesc, value) \ + SET_TX_DESC_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_SW_DEFINE_8822C(txdesc) GET_TX_DESC_SW_DEFINE(txdesc) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_DMA_TXAGG_NUM_8822C(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8822C(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8822C(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8822C(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8822C(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8822C(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8822C(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8822C(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8822C(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8822C(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8822C(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8822C(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_TXWIFI_CP_8822C(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8822C(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8822C(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8822C(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8822C(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8822C(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8822C(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8822C(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8822C(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8822C(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8822C(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8822C(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8822C(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8822C(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8822C(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8822C(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8822C(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8822C(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8822C(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8822C(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8822C(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8822C(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_8822C(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_8822C(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc) +#define SET_TX_DESC_EN_HWEXSEQ_8822C(txdesc, value) \ + SET_TX_DESC_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWEXSEQ_8822C(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_DATA_RC_8822C(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8822C(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8822C(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8822C(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8822C(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8822C(txdesc) GET_TX_DESC_RTS_RC(txdesc) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_TAILPAGE_H_8822C(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8822C(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8822C(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8822C(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8822C(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8822C(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8822C(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8822C(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8822C(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8822C(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822C(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822C(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) + +/*WORD10*/ + +#define SET_TX_DESC_MU_DATARATE_8822C(txdesc, value) \ + SET_TX_DESC_MU_DATARATE(txdesc, value) +#define GET_TX_DESC_MU_DATARATE_8822C(txdesc) GET_TX_DESC_MU_DATARATE(txdesc) +#define SET_TX_DESC_MU_RC_8822C(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value) +#define GET_TX_DESC_MU_RC_8822C(txdesc) GET_TX_DESC_MU_RC(txdesc) +#define SET_TX_DESC_SND_PKT_SEL_8822C(txdesc, value) \ + SET_TX_DESC_SND_PKT_SEL(txdesc, value) +#define GET_TX_DESC_SND_PKT_SEL_8822C(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc) + +#endif #endif diff --git a/hal/halmac/halmac_tx_desc_nic.h b/hal/halmac/halmac_tx_desc_nic.h index 4e82378..59a614f 100644 --- a/hal/halmac/halmac_tx_desc_nic.h +++ b/hal/halmac/halmac_tx_desc_nic.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,452 +15,937 @@ #ifndef _HALMAC_TX_DESC_NIC_H_ #define _HALMAC_TX_DESC_NIC_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /*TXDESC_WORD0*/ -#define SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 31, 1, __Value) -#define GET_TX_DESC_DISQSELSEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 31, 1) +#define SET_TX_DESC_DISQSELSEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value) +#define GET_TX_DESC_DISQSELSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_GF(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 30, 1, __Value) -#define GET_TX_DESC_GF(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 30, 1) -#define SET_TX_DESC_NO_ACM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 29, 1, __Value) -#define GET_TX_DESC_NO_ACM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 29, 1) +#define SET_TX_DESC_IE_END_BODY(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value) +#define GET_TX_DESC_IE_END_BODY(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 28, 1, __Value) -#define GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 28, 1) +#define SET_TX_DESC_GF(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value) +#define GET_TX_DESC_GF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 27, 1, __Value) -#define GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 27, 1) +#define SET_TX_DESC_AGG_EN_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value) +#define GET_TX_DESC_AGG_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_LS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 26, 1, __Value) -#define GET_TX_DESC_LS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 26, 1) -#define SET_TX_DESC_HTC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 25, 1, __Value) -#define GET_TX_DESC_HTC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 25, 1) -#define SET_TX_DESC_BMC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 24, 1, __Value) -#define GET_TX_DESC_BMC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 24, 1) -#define SET_TX_DESC_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 16, 8, __Value) -#define GET_TX_DESC_OFFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 16, 8) -#define SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 0, 16, __Value) -#define GET_TX_DESC_TXPKTSIZE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 0, 16) +#define SET_TX_DESC_NO_ACM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value) +#define GET_TX_DESC_NO_ACM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1) -/*TXDESC_WORD1*/ +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_BK_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value) +#define GET_TX_DESC_BK_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 28, 1, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x00, 28, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 27, 1, value) +#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 27, 1) +#define SET_TX_DESC_LS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 26, 1, value) +#define GET_TX_DESC_LS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 26, 1) +#define SET_TX_DESC_HTC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 25, 1, value) +#define GET_TX_DESC_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 25, 1) +#define SET_TX_DESC_BMC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 1, value) +#define GET_TX_DESC_BMC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_PKT_OFFSET_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 5, value) +#define GET_TX_DESC_PKT_OFFSET_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 5) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_OFFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value) +#define GET_TX_DESC_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 16, 8) +#define SET_TX_DESC_TXPKTSIZE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 0, 16, value) +#define GET_TX_DESC_TXPKTSIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 0, 16) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/*WORD1*/ + +#define SET_TX_DESC_HW_AES_IV_V2(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 31, 1, value) +#define GET_TX_DESC_HW_AES_IV_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 31, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_AMSDU(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value) +#define GET_TX_DESC_AMSDU(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_FTM_EN_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value) +#define GET_TX_DESC_FTM_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_MOREDATA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value) +#define GET_TX_DESC_MOREDATA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_HW_AES_IV_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value) +#define GET_TX_DESC_HW_AES_IV_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1) +#define SET_TX_DESC_MHR_CP(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 25, 1, value) +#define GET_TX_DESC_MHR_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 25, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_PKT_OFFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 5, value) +#define GET_TX_DESC_PKT_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 24, 5) + +#endif + +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_MOREDATA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 29, 1, __Value) -#define GET_TX_DESC_MOREDATA(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 29, 1) -#define SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 24, 5, __Value) -#define GET_TX_DESC_PKT_OFFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 24, 5) -#define SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 22, 2, __Value) -#define GET_TX_DESC_SEC_TYPE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 22, 2) -#define SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 21, 1, __Value) -#define GET_TX_DESC_EN_DESC_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 21, 1) -#define SET_TX_DESC_RATE_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 16, 5, __Value) -#define GET_TX_DESC_RATE_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 16, 5) -#define SET_TX_DESC_PIFS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 15, 1, __Value) -#define GET_TX_DESC_PIFS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 15, 1) -#define SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 14, 1, __Value) -#define GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 14, 1) -#define SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 13, 1, __Value) -#define GET_TX_DESC_RD_NAV_EXT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 13, 1) -#define SET_TX_DESC_QSEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 8, 5, __Value) -#define GET_TX_DESC_QSEL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 8, 5) -#define SET_TX_DESC_MACID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 0, 7, __Value) -#define GET_TX_DESC_MACID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 0, 7) +#define SET_TX_DESC_SMH_EN_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 1, value) +#define GET_TX_DESC_SMH_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 24, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_SEC_TYPE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 22, 2, value) +#define GET_TX_DESC_SEC_TYPE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 22, 2) +#define SET_TX_DESC_EN_DESC_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 21, 1, value) +#define GET_TX_DESC_EN_DESC_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 21, 1) +#define SET_TX_DESC_RATE_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 5, value) +#define GET_TX_DESC_RATE_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 5) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_SMH_CAM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 8, value) +#define GET_TX_DESC_SMH_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 8) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_PIFS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 15, 1, value) +#define GET_TX_DESC_PIFS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 15, 1) +#define SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 14, 1, value) +#define GET_TX_DESC_LSIG_TXOP_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 14, 1) +#define SET_TX_DESC_RD_NAV_EXT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value) +#define GET_TX_DESC_RD_NAV_EXT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_EXT_EDCA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value) +#define GET_TX_DESC_EXT_EDCA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1) + +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_QSEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value) +#define GET_TX_DESC_QSEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 8, 5) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_SPECIAL_CW(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 7, 1, value) +#define GET_TX_DESC_SPECIAL_CW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 7, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_MACID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value) +#define GET_TX_DESC_MACID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 7) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_MACID_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value) +#define GET_TX_DESC_MACID_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 7) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /*TXDESC_WORD2*/ -#define SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 31, 1, __Value) -#define GET_TX_DESC_HW_AES_IV(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 31, 1) +#define SET_TX_DESC_HW_AES_IV(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value) +#define GET_TX_DESC_HW_AES_IV(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_CHK_EN_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value) +#define GET_TX_DESC_CHK_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_FTM_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 30, 1, __Value) -#define GET_TX_DESC_FTM_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 30, 1) +#define SET_TX_DESC_FTM_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value) +#define GET_TX_DESC_FTM_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 30, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_G_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 24, 6, __Value) -#define GET_TX_DESC_G_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 24, 6) -#define SET_TX_DESC_BT_NULL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 23, 1, __Value) -#define GET_TX_DESC_BT_NULL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 23, 1) -#define SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 20, 3, __Value) -#define GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 20, 3) -#define SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 19, 1, __Value) -#define GET_TX_DESC_SPE_RPT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 19, 1) -#define SET_TX_DESC_RAW(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 18, 1, __Value) -#define GET_TX_DESC_RAW(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 18, 1) -#define SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 17, 1, __Value) -#define GET_TX_DESC_MOREFRAG(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 17, 1) -#define SET_TX_DESC_BK(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 16, 1, __Value) -#define GET_TX_DESC_BK(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 16, 1) -#define SET_TX_DESC_NULL_1(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 15, 1, __Value) -#define GET_TX_DESC_NULL_1(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 15, 1) -#define SET_TX_DESC_NULL_0(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 14, 1, __Value) -#define GET_TX_DESC_NULL_0(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 14, 1) -#define SET_TX_DESC_RDG_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 13, 1, __Value) -#define GET_TX_DESC_RDG_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 13, 1) -#define SET_TX_DESC_AGG_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 12, 1, __Value) -#define GET_TX_DESC_AGG_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 12, 1) -#define SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 10, 2, __Value) -#define GET_TX_DESC_CCA_RTS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 10, 2) +#define SET_TX_DESC_ANTCEL_D_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 28, 4, value) +#define GET_TX_DESC_ANTCEL_D_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 28, 4) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 9, 1, __Value) -#define GET_TX_DESC_TRI_FRAME(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 9, 1) +#define SET_TX_DESC_DMA_PRI(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 27, 1, value) +#define GET_TX_DESC_DMA_PRI(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 27, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_P_AID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 0, 9, __Value) -#define GET_TX_DESC_P_AID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 0, 9) +#define SET_TX_DESC_G_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 6, value) +#define GET_TX_DESC_G_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 6) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 3, value) +#define GET_TX_DESC_MAX_AMSDU_MODE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 3) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTSEL_C_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 4, value) +#define GET_TX_DESC_ANTSEL_C_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 4) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_BT_NULL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 23, 1, value) +#define GET_TX_DESC_BT_NULL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 23, 1) +#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 20, 3, value) +#define GET_TX_DESC_AMPDU_DENSITY(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 20, 3) +#define SET_TX_DESC_SPE_RPT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 19, 1, value) +#define GET_TX_DESC_SPE_RPT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 19, 1) +#define SET_TX_DESC_RAW(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 18, 1, value) +#define GET_TX_DESC_RAW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 18, 1) +#define SET_TX_DESC_MOREFRAG(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 17, 1, value) +#define GET_TX_DESC_MOREFRAG(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 17, 1) +#define SET_TX_DESC_BK(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 1, value) +#define GET_TX_DESC_BK(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 8, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 8) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_NULL_1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 15, 1, value) +#define GET_TX_DESC_NULL_1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 15, 1) +#define SET_TX_DESC_NULL_0(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 14, 1, value) +#define GET_TX_DESC_NULL_0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 14, 1) +#define SET_TX_DESC_RDG_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 13, 1, value) +#define GET_TX_DESC_RDG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 13, 1) +#define SET_TX_DESC_AGG_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 12, 1, value) +#define GET_TX_DESC_AGG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 12, 1) +#define SET_TX_DESC_CCA_RTS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 10, 2, value) +#define GET_TX_DESC_CCA_RTS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 10, 2) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_TRI_FRAME(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 9, 1, value) +#define GET_TX_DESC_TRI_FRAME(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 9, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_P_AID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 9, value) +#define GET_TX_DESC_P_AID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 9) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 16, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 16) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 24, 8, __Value) -#define GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 24, 8) -#define SET_TX_DESC_NDPA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 22, 2, __Value) -#define GET_TX_DESC_NDPA(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 22, 2) -#define SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 17, 5, __Value) -#define GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 17, 5) -#define SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 16, 1, __Value) -#define GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 16, 1) -#define SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 15, 1, __Value) -#define GET_TX_DESC_NAVUSEHDR(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 15, 1) +#define SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 24, 8, value) +#define GET_TX_DESC_AMPDU_MAX_TIME(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x0C, 24, 8) +#define SET_TX_DESC_NDPA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 22, 2, value) +#define GET_TX_DESC_NDPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 22, 2) +#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 17, 5, value) +#define GET_TX_DESC_MAX_AGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 17, 5) +#define SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 1, value) +#define GET_TX_DESC_USE_MAX_TIME_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_CHK_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 14, 1, __Value) -#define GET_TX_DESC_CHK_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 14, 1) +#define SET_TX_DESC_OFFLOAD_SIZE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 15, value) +#define GET_TX_DESC_OFFLOAD_SIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 15) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 13, 1, __Value) -#define GET_TX_DESC_HW_RTS_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 13, 1) -#define SET_TX_DESC_RTSEN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 12, 1, __Value) -#define GET_TX_DESC_RTSEN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 12, 1) -#define SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 11, 1, __Value) -#define GET_TX_DESC_CTS2SELF(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 11, 1) -#define SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 10, 1, __Value) -#define GET_TX_DESC_DISDATAFB(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 10, 1) -#define SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 9, 1, __Value) -#define GET_TX_DESC_DISRTSFB(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 9, 1) -#define SET_TX_DESC_USE_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 8, 1, __Value) -#define GET_TX_DESC_USE_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 8, 1) -#define SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 6, 2, __Value) -#define GET_TX_DESC_HW_SSN_SEL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 6, 2) +#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 15, 1, value) +#define GET_TX_DESC_NAVUSEHDR(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 15, 1) +#define SET_TX_DESC_CHK_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 14, 1, value) +#define GET_TX_DESC_CHK_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 14, 1) +#define SET_TX_DESC_HW_RTS_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 13, 1, value) +#define GET_TX_DESC_HW_RTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 13, 1) +#define SET_TX_DESC_RTSEN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 12, 1, value) +#define GET_TX_DESC_RTSEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 12, 1) +#define SET_TX_DESC_CTS2SELF(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 1, value) +#define GET_TX_DESC_CTS2SELF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 0, 5, __Value) -#define GET_TX_DESC_WHEADER_LEN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 0, 5) +#define SET_TX_DESC_CHANNEL_DMA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 5, value) +#define GET_TX_DESC_CHANNEL_DMA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 5) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) +#define SET_TX_DESC_DISDATAFB(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 10, 1, value) +#define GET_TX_DESC_DISDATAFB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 10, 1) +#define SET_TX_DESC_DISRTSFB(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 9, 1, value) +#define GET_TX_DESC_DISRTSFB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 9, 1) +#define SET_TX_DESC_USE_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 8, 1, value) +#define GET_TX_DESC_USE_RATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 8, 1) +#define SET_TX_DESC_HW_SSN_SEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 2, value) +#define GET_TX_DESC_HW_SSN_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 2) -/*TXDESC_WORD4*/ +#endif + +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 30, 2, __Value) -#define GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 30, 2) -#define SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 29, 1, __Value) -#define GET_TX_DESC_PCTS_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 29, 1) -#define SET_TX_DESC_RTSRATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 24, 5, __Value) -#define GET_TX_DESC_RTSRATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 24, 5) -#define SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 18, 6, __Value) -#define GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 18, 6) -#define SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 17, 1, __Value) -#define GET_TX_DESC_RTY_LMT_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 17, 1) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 13, 4, __Value) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 13, 4) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 8, 5, __Value) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 8, 5) -#define SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 7, 1, __Value) -#define GET_TX_DESC_TRY_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 7, 1) -#define SET_TX_DESC_DATARATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 0, 7, __Value) -#define GET_TX_DESC_DATARATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 0, 7) +#define SET_TX_DESC_IE_CNT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 3, value) +#define GET_TX_DESC_IE_CNT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 3) +#define SET_TX_DESC_IE_CNT_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 5, 1, value) +#define GET_TX_DESC_IE_CNT_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 5, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_WHEADER_LEN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value) +#define GET_TX_DESC_WHEADER_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5) + +#endif +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_WHEADER_LEN_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value) +#define GET_TX_DESC_WHEADER_LEN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 30, 2, value) +#define GET_TX_DESC_PCTS_MASK_IDX(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 30, 2) +#define SET_TX_DESC_PCTS_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 29, 1, value) +#define GET_TX_DESC_PCTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 29, 1) +#define SET_TX_DESC_RTSRATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 24, 5, value) +#define GET_TX_DESC_RTSRATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 24, 5) +#define SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 18, 6, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 18, 6) +#define SET_TX_DESC_RTY_LMT_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 17, 1, value) +#define GET_TX_DESC_RTY_LMT_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 17, 1) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 13, 4, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 13, 4) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 8, 5, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 8, 5) +#define SET_TX_DESC_TRY_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 7, 1, value) +#define GET_TX_DESC_TRY_RATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 7, 1) +#define SET_TX_DESC_DATARATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 0, 7, value) +#define GET_TX_DESC_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 0, 7) /*TXDESC_WORD5*/ -#define SET_TX_DESC_POLLUTED(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 31, 1, __Value) -#define GET_TX_DESC_POLLUTED(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 31, 1) +#define SET_TX_DESC_POLLUTED(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 31, 1, value) +#define GET_TX_DESC_POLLUTED(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 31, 1) + +#endif + +#if (HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value) +#define GET_TX_DESC_ANTSEL_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 30, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 28, 3, __Value) -#define GET_TX_DESC_TXPWR_OFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 28, 3) -#define SET_TX_DESC_TX_ANT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 24, 4, __Value) -#define GET_TX_DESC_TX_ANT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 24, 4) -#define SET_TX_DESC_PORT_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 21, 3, __Value) -#define GET_TX_DESC_PORT_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 21, 3) +#define SET_TX_DESC_TXPWR_OFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 3, value) +#define GET_TX_DESC_TXPWR_OFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 3) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 18, 3, __Value) -#define GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 18, 3) +#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 2, value) +#define GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 17, 1, __Value) -#define GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 17, 1) +#define SET_TX_DESC_TX_ANT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value) +#define GET_TX_DESC_TX_ANT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 4) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_RTS_SC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 13, 4, __Value) -#define GET_TX_DESC_RTS_SC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 13, 4) -#define SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 12, 1, __Value) -#define GET_TX_DESC_RTS_SHORT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 12, 1) +#define SET_TX_DESC_DROP_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 2, value) +#define GET_TX_DESC_DROP_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 10, 2, __Value) -#define GET_TX_DESC_VCS_STBC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 10, 2) +#define SET_TX_DESC_PORT_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 21, 3, value) +#define GET_TX_DESC_PORT_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 21, 3) #endif -#if (HALMAC_8188F_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_RTS_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 10, 2, __Value) -#define GET_TX_DESC_RTS_STBC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 10, 2) +#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 18, 3, value) +#define GET_TX_DESC_MULTIPLE_PORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 18, 3) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 8, 2, __Value) -#define GET_TX_DESC_DATA_STBC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 8, 2) +#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 17, 1, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 17, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 7, 1, __Value) -#define GET_TX_DESC_DATA_LDPC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 7, 1) +#define SET_TX_DESC_RTS_SC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value) +#define GET_TX_DESC_RTS_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 13, 4) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_DATA_BW(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 5, 2, __Value) -#define GET_TX_DESC_DATA_BW(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 5, 2) -#define SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 4, 1, __Value) -#define GET_TX_DESC_DATA_SHORT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 4, 1) -#define SET_TX_DESC_DATA_SC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 0, 4, __Value) -#define GET_TX_DESC_DATA_SC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 0, 4) +#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value) +#define GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 13, 4) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_RTS_SHORT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 12, 1, value) +#define GET_TX_DESC_RTS_SHORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 12, 1) +#define SET_TX_DESC_VCS_STBC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 10, 2, value) +#define GET_TX_DESC_VCS_STBC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 10, 2) +#define SET_TX_DESC_DATA_STBC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 8, 2, value) +#define GET_TX_DESC_DATA_STBC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 8, 2) +#define SET_TX_DESC_DATA_LDPC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 7, 1, value) +#define GET_TX_DESC_DATA_LDPC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 7, 1) +#define SET_TX_DESC_DATA_BW(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 5, 2, value) +#define GET_TX_DESC_DATA_BW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 5, 2) +#define SET_TX_DESC_DATA_SHORT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 4, 1, value) +#define GET_TX_DESC_DATA_SHORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 4, 1) +#define SET_TX_DESC_DATA_SC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 0, 4, value) +#define GET_TX_DESC_DATA_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 0, 4) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 30, 2, __Value) -#define GET_TX_DESC_ANTSEL_D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 30, 2) -#define SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 28, 2, __Value) -#define GET_TX_DESC_ANT_MAPD(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 28, 2) -#define SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 26, 2, __Value) -#define GET_TX_DESC_ANT_MAPC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 26, 2) -#define SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 24, 2, __Value) -#define GET_TX_DESC_ANT_MAPB(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 24, 2) -#define SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 22, 2, __Value) -#define GET_TX_DESC_ANT_MAPA(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 22, 2) -#define SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 20, 2, __Value) -#define GET_TX_DESC_ANTSEL_C(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 20, 2) -#define SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 18, 2, __Value) -#define GET_TX_DESC_ANTSEL_B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 18, 2) +#define SET_TX_DESC_ANTSEL_D(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value) +#define GET_TX_DESC_ANTSEL_D(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 16, 2, __Value) -#define GET_TX_DESC_ANTSEL_A(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 16, 2) -#define SET_TX_DESC_MBSSID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 12, 4, __Value) -#define GET_TX_DESC_MBSSID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 12, 4) -#define SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 0, 12, __Value) -#define GET_TX_DESC_SW_DEFINE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 0, 12) +#define SET_TX_DESC_ANT_MAPD_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value) +#define GET_TX_DESC_ANT_MAPD_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2) -/*TXDESC_WORD7*/ +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 24, 8, __Value) -#define GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 24, 8) +#define SET_TX_DESC_ANT_MAPD(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value) +#define GET_TX_DESC_ANT_MAPD(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 24, 8, __Value) -#define GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 24, 8) -#define SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 20, 4, __Value) -#define GET_TX_DESC_NTX_MAP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 20, 4) +#define SET_TX_DESC_ANT_MAPC_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value) +#define GET_TX_DESC_ANT_MAPC_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 0, 16, __Value) -#define GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 0, 16) -#define SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 0, 16, __Value) -#define GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 0, 16) -#define SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 0, 16, __Value) -#define GET_TX_DESC_TIMESTAMP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 0, 16) +#define SET_TX_DESC_ANT_MAPC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value) +#define GET_TX_DESC_ANT_MAPC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8198F_SUPPORT) +#define SET_TX_DESC_ANT_MAPB_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value) +#define GET_TX_DESC_ANT_MAPB_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2) -/*TXDESC_WORD8*/ +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 31, 1, __Value) -#define GET_TX_DESC_TXWIFI_CP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 31, 1) -#define SET_TX_DESC_MAC_CP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 30, 1, __Value) -#define GET_TX_DESC_MAC_CP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 30, 1) -#define SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 29, 1, __Value) -#define GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 29, 1) -#define SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 28, 1, __Value) -#define GET_TX_DESC_STW_RB_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 28, 1) -#define SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 27, 1, __Value) -#define GET_TX_DESC_STW_RATE_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 27, 1) -#define SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 26, 1, __Value) -#define GET_TX_DESC_STW_ANT_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 26, 1) -#define SET_TX_DESC_STW_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 25, 1, __Value) -#define GET_TX_DESC_STW_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 25, 1) -#define SET_TX_DESC_SMH_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 24, 1, __Value) -#define GET_TX_DESC_SMH_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 24, 1) +#define SET_TX_DESC_ANT_MAPB(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value) +#define GET_TX_DESC_ANT_MAPB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 24, 8, __Value) -#define GET_TX_DESC_TAILPAGE_L(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 24, 8) +#define SET_TX_DESC_ANT_MAPA_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value) +#define GET_TX_DESC_ANT_MAPA_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 16, 8, __Value) -#define GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 16, 8) +#define SET_TX_DESC_ANT_MAPA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 22, 2, value) +#define GET_TX_DESC_ANT_MAPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 22, 2) +#define SET_TX_DESC_ANTSEL_C(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 2, value) +#define GET_TX_DESC_ANTSEL_C(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 16, 8, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 16, 8) -#define SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 15, 1, __Value) -#define GET_TX_DESC_EN_HWSEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 15, 1) +#define SET_TX_DESC_ANTSEL_B_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 4, value) +#define GET_TX_DESC_ANTSEL_B_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 4) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 14, 1, __Value) -#define GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 14, 1) +#define SET_TX_DESC_ANTSEL_B(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 18, 2, value) +#define GET_TX_DESC_ANTSEL_B(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 18, 2) +#define SET_TX_DESC_ANTSEL_A(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 2, value) +#define GET_TX_DESC_ANTSEL_A(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_DATA_RC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 8, 6, __Value) -#define GET_TX_DESC_DATA_RC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 8, 6) -#define SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 6, 2, __Value) -#define GET_TX_DESC_BAR_RTY_TH(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 6, 2) -#define SET_TX_DESC_RTS_RC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 0, 6, __Value) -#define GET_TX_DESC_RTS_RC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 0, 6) +#define SET_TX_DESC_ANTSEL_A_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 4, value) +#define GET_TX_DESC_ANTSEL_A_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 4) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) +#define SET_TX_DESC_MBSSID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 4, value) +#define GET_TX_DESC_MBSSID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 12, 4) -/*TXDESC_WORD9*/ +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 28, 4, __Value) -#define GET_TX_DESC_TAILPAGE_H(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 28, 4) -#define SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 24, 4, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 24, 4) +#define SET_TX_DESC_SW_DEFINE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value) +#define GET_TX_DESC_SW_DEFINE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 12) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 12, 12, __Value) -#define GET_TX_DESC_SW_SEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 12, 12) -#define SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 11, 1, __Value) -#define GET_TX_DESC_TXBF_PATH(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 11, 1) -#define SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 0, 11, __Value) -#define GET_TX_DESC_PADDING_LEN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 0, 11) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 0, 8, __Value) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 0, 8) +#define SET_TX_DESC_SWPS_SEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value) +#define GET_TX_DESC_SWPS_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 12) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) +/*TXDESC_WORD7*/ -/*WORD10*/ +#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value) +#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8) +#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value) +#define GET_TX_DESC_FINAL_DATA_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8) +#define SET_TX_DESC_NTX_MAP(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 20, 4, value) +#define GET_TX_DESC_NTX_MAP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 20, 4) -#define SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x28, 8, 8, __Value) -#define GET_TX_DESC_MU_DATARATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x28, 8, 8) -#define SET_TX_DESC_MU_RC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x28, 4, 4, __Value) -#define GET_TX_DESC_MU_RC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x28, 4, 4) -#define SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x28, 0, 2, __Value) -#define GET_TX_DESC_SND_PKT_SEL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x28, 0, 2) +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTSEL_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 19, 1, value) +#define GET_TX_DESC_ANTSEL_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 19, 1) +#define SET_TX_DESC_MBSSID_EX(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 3, value) +#define GET_TX_DESC_MBSSID_EX(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 3) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value) +#define GET_TX_DESC_TX_BUFF_SIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16) +#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value) +#define GET_TX_DESC_TXDESC_CHECKSUM(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16) +#define SET_TX_DESC_TIMESTAMP(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value) +#define GET_TX_DESC_TIMESTAMP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_TXWIFI_CP(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 31, 1, value) +#define GET_TX_DESC_TXWIFI_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 31, 1) +#define SET_TX_DESC_MAC_CP(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 30, 1, value) +#define GET_TX_DESC_MAC_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 30, 1) +#define SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 29, 1, value) +#define GET_TX_DESC_STW_PKTRE_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 29, 1) +#define SET_TX_DESC_STW_RB_DIS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 28, 1, value) +#define GET_TX_DESC_STW_RB_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 28, 1) +#define SET_TX_DESC_STW_RATE_DIS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 27, 1, value) +#define GET_TX_DESC_STW_RATE_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 27, 1) +#define SET_TX_DESC_STW_ANT_DIS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 26, 1, value) +#define GET_TX_DESC_STW_ANT_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 26, 1) +#define SET_TX_DESC_STW_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 25, 1, value) +#define GET_TX_DESC_STW_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 25, 1) +#define SET_TX_DESC_SMH_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 1, value) +#define GET_TX_DESC_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 1) +#define SET_TX_DESC_TAILPAGE_L(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 8, value) +#define GET_TX_DESC_TAILPAGE_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 8) +#define SET_TX_DESC_SDIO_DMASEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value) +#define GET_TX_DESC_SDIO_DMASEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8) +#define SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value) +#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8) +#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 15, 1, value) +#define GET_TX_DESC_EN_HWSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 15, 1) +#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 1, value) +#define GET_TX_DESC_EN_HWEXSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 1) +#define SET_TX_DESC_DATA_RC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 6, value) +#define GET_TX_DESC_DATA_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 6) +#define SET_TX_DESC_BAR_RTY_TH(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 6, 2, value) +#define GET_TX_DESC_BAR_RTY_TH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 6, 2) +#define SET_TX_DESC_RTS_RC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 6, value) +#define GET_TX_DESC_RTS_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 6) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_TAILPAGE_H(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 28, 4, value) +#define GET_TX_DESC_TAILPAGE_H(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 28, 4) +#define SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value) +#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4) +#define SET_TX_DESC_SW_SEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 12, 12, value) +#define GET_TX_DESC_SW_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 12, 12) +#define SET_TX_DESC_TXBF_PATH(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 11, 1, value) +#define GET_TX_DESC_TXBF_PATH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 11, 1) +#define SET_TX_DESC_PADDING_LEN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 11, value) +#define GET_TX_DESC_PADDING_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 11) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 8, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 8) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/*WORD10*/ + +#define SET_TX_DESC_MU_DATARATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value) +#define GET_TX_DESC_MU_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8) +#define SET_TX_DESC_MU_RC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 4, value) +#define GET_TX_DESC_MU_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 4) +#define SET_TX_DESC_SND_PKT_SEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value) +#define GET_TX_DESC_SND_PKT_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2) + +#endif #endif diff --git a/hal/halmac/halmac_type.h b/hal/halmac/halmac_type.h index 4f36f3e..8bfa449 100644 --- a/hal/halmac/halmac_type.h +++ b/hal/halmac/halmac_type.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -20,92 +20,185 @@ #include "halmac_hw_cfg.h" #include "halmac_fw_info.h" #include "halmac_intf_phy_cmd.h" +#include "halmac_state_machine.h" #define IN #define OUT #define INOUT -#define VOID void - -#define HALMAC_SCAN_CH_NUM_MAX 28 -#define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */ -#define HALMAC_PHY_PARAMETER_SIZE 12 -#define HALMAC_PHY_PARAMETER_MAX_NUM 128 -#define HALMAC_MAX_SSID_LEN 32 -#define HALMAC_SUPPORT_NLO_NUM 16 -#define HALMAC_SUPPORT_PROBE_REQ_NUM 8 -#define HALMC_DDMA_POLLING_COUNT 1000 -#define API_ARRAY_SIZE 32 + +#define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */ #ifndef HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE -#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 48 +#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 80 +#endif + +#ifndef HALMAC_MSG_LEVEL_TRACE +#define HALMAC_MSG_LEVEL_TRACE 3 +#endif + +#ifndef HALMAC_MSG_LEVEL_WARNING +#define HALMAC_MSG_LEVEL_WARNING 2 +#endif + +#ifndef HALMAC_MSG_LEVEL_ERR +#define HALMAC_MSG_LEVEL_ERR 1 +#endif + +#ifndef HALMAC_MSG_LEVEL_NO_LOG +#define HALMAC_MSG_LEVEL_NO_LOG 0 +#endif + +#ifndef HALMAC_MSG_LEVEL +#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE #endif /* platform api */ -#define PLATFORM_SDIO_CMD52_READ pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_READ -#define PLATFORM_SDIO_CMD53_READ_8 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_8 -#define PLATFORM_SDIO_CMD53_READ_16 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_16 -#define PLATFORM_SDIO_CMD53_READ_32 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_32 -#define PLATFORM_SDIO_CMD53_READ_N pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_N -#define PLATFORM_SDIO_CMD52_WRITE pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_WRITE -#define PLATFORM_SDIO_CMD53_WRITE_8 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_8 -#define PLATFORM_SDIO_CMD53_WRITE_16 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_16 -#define PLATFORM_SDIO_CMD53_WRITE_32 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_32 - -#define PLATFORM_REG_READ_8 pHalmac_adapter->pHalmac_platform_api->REG_READ_8 -#define PLATFORM_REG_READ_16 pHalmac_adapter->pHalmac_platform_api->REG_READ_16 -#define PLATFORM_REG_READ_32 pHalmac_adapter->pHalmac_platform_api->REG_READ_32 -#define PLATFORM_REG_WRITE_8 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_8 -#define PLATFORM_REG_WRITE_16 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_16 -#define PLATFORM_REG_WRITE_32 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_32 - -#define PLATFORM_SEND_RSVD_PAGE pHalmac_adapter->pHalmac_platform_api->SEND_RSVD_PAGE -#define PLATFORM_SEND_H2C_PKT pHalmac_adapter->pHalmac_platform_api->SEND_H2C_PKT - -#define PLATFORM_RTL_FREE pHalmac_adapter->pHalmac_platform_api->RTL_FREE -#define PLATFORM_RTL_MALLOC pHalmac_adapter->pHalmac_platform_api->RTL_MALLOC -#define PLATFORM_RTL_MEMCPY pHalmac_adapter->pHalmac_platform_api->RTL_MEMCPY -#define PLATFORM_RTL_MEMSET pHalmac_adapter->pHalmac_platform_api->RTL_MEMSET -#define PLATFORM_RTL_DELAY_US pHalmac_adapter->pHalmac_platform_api->RTL_DELAY_US - -#define PLATFORM_MUTEX_INIT pHalmac_adapter->pHalmac_platform_api->MUTEX_INIT -#define PLATFORM_MUTEX_DEINIT pHalmac_adapter->pHalmac_platform_api->MUTEX_DEINIT -#define PLATFORM_MUTEX_LOCK pHalmac_adapter->pHalmac_platform_api->MUTEX_LOCK -#define PLATFORM_MUTEX_UNLOCK pHalmac_adapter->pHalmac_platform_api->MUTEX_UNLOCK - -#define PLATFORM_EVENT_INDICATION pHalmac_adapter->pHalmac_platform_api->EVENT_INDICATION +#define PLTFM_SDIO_CMD52_R(offset) \ + adapter->pltfm_api->SDIO_CMD52_READ(adapter->drv_adapter, offset) +#define PLTFM_SDIO_CMD53_R8(offset) \ + adapter->pltfm_api->SDIO_CMD53_READ_8(adapter->drv_adapter, offset) +#define PLTFM_SDIO_CMD53_R16(offset) \ + adapter->pltfm_api->SDIO_CMD53_READ_16(adapter->drv_adapter, offset) +#define PLTFM_SDIO_CMD53_R32(offset) \ + adapter->pltfm_api->SDIO_CMD53_READ_32(adapter->drv_adapter, offset) +#define PLTFM_SDIO_CMD53_RN(offset, size, data) \ + adapter->pltfm_api->SDIO_CMD53_READ_N(adapter->drv_adapter, offset, \ + size, data) +#define PLTFM_SDIO_CMD52_W(offset, val) \ + adapter->pltfm_api->SDIO_CMD52_WRITE(adapter->drv_adapter, offset, val) +#define PLTFM_SDIO_CMD53_W8(offset, val) \ + adapter->pltfm_api->SDIO_CMD53_WRITE_8(adapter->drv_adapter, offset, \ + val) +#define PLTFM_SDIO_CMD53_W16(offset, val) \ + adapter->pltfm_api->SDIO_CMD53_WRITE_16(adapter->drv_adapter, offset, \ + val) +#define PLTFM_SDIO_CMD53_W32(offset, val) \ + adapter->pltfm_api->SDIO_CMD53_WRITE_32(adapter->drv_adapter, offset, \ + val) +#define PLTFM_SDIO_CMD52_CIA_R(offset) \ + adapter->pltfm_api->SDIO_CMD52_CIA_READ(adapter->drv_adapter, offset) + +#define PLTFM_REG_R8(offset) \ + adapter->pltfm_api->REG_READ_8(adapter->drv_adapter, offset) +#define PLTFM_REG_R16(offset) \ + adapter->pltfm_api->REG_READ_16(adapter->drv_adapter, offset) +#define PLTFM_REG_R32(offset) \ + adapter->pltfm_api->REG_READ_32(adapter->drv_adapter, offset) +#define PLTFM_REG_W8(offset, val) \ + adapter->pltfm_api->REG_WRITE_8(adapter->drv_adapter, offset, val) +#define PLTFM_REG_W16(offset, val) \ + adapter->pltfm_api->REG_WRITE_16(adapter->drv_adapter, offset, val) +#define PLTFM_REG_W32(offset, val) \ + adapter->pltfm_api->REG_WRITE_32(adapter->drv_adapter, offset, val) + +#define PLTFM_SEND_RSVD_PAGE(buf, size) \ + adapter->pltfm_api->SEND_RSVD_PAGE(adapter->drv_adapter, buf, size) +#define PLTFM_SEND_H2C_PKT(buf, size) \ + adapter->pltfm_api->SEND_H2C_PKT(adapter->drv_adapter, buf, size) + +#define PLTFM_FREE(buf, size) \ + adapter->pltfm_api->RTL_FREE(adapter->drv_adapter, buf, size) +#define PLTFM_MALLOC(size) \ + adapter->pltfm_api->RTL_MALLOC(adapter->drv_adapter, size) +#define PLTFM_MEMCPY(dest, src, size) \ + adapter->pltfm_api->RTL_MEMCPY(adapter->drv_adapter, dest, src, size) +#define PLTFM_MEMSET(addr, value, size) \ + adapter->pltfm_api->RTL_MEMSET(adapter->drv_adapter, addr, value, size) +#define PLTFM_DELAY_US(us) \ + adapter->pltfm_api->RTL_DELAY_US(adapter->drv_adapter, us) + +#define PLTFM_MUTEX_INIT(mutex) \ + adapter->pltfm_api->MUTEX_INIT(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_DEINIT(mutex) \ + adapter->pltfm_api->MUTEX_DEINIT(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_LOCK(mutex) \ + adapter->pltfm_api->MUTEX_LOCK(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_UNLOCK(mutex) \ + adapter->pltfm_api->MUTEX_UNLOCK(adapter->drv_adapter, mutex) + +#define PLTFM_EVENT_SIG(feature_id, proc_status, buf, size) \ + adapter->pltfm_api->EVENT_INDICATION(adapter->drv_adapter, feature_id, \ + proc_status, buf, size) + +#if HALMAC_PLATFORM_WINDOWS +#define PLTFM_MSG_PRINT adapter->pltfm_api->MSG_PRINT +#endif +#define PLTFM_MSG_ALWAYS(...) \ + adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \ + HALMAC_DBG_ALWAYS, __VA_ARGS__) #if HALMAC_DBG_MSG_ENABLE -#define PLATFORM_MSG_PRINT pHalmac_adapter->pHalmac_platform_api->MSG_PRINT + +/* Enable debug msg depends on HALMAC_MSG_LEVEL */ +#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_ERR) +#define PLTFM_MSG_ERR(...) \ + adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \ + HALMAC_DBG_ERR, __VA_ARGS__) #else -#define PLATFORM_MSG_PRINT(pDriver_adapter, msg_type, msg_level, fmt, ...) do {} while (0) +#define PLTFM_MSG_ERR(...) do {} while (0) #endif -#if HALMAC_PLATFORM_TESTPROGRAM -#define PLATFORM_WRITE_DATA_SDIO_ADDR pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_SDIO_ADDR -#define PLATFORM_WRITE_DATA_USB_BULKOUT_ID pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_USB_BULKOUT_ID -#define PLATFORM_WRITE_DATA_PCIE_QUEUE pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_PCIE_QUEUE -#define PLATFORM_READ_DATA pHalmac_adapter->pHalmac_platform_api->READ_DATA +#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_WARNING) +#define PLTFM_MSG_WARN(...) \ + adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \ + HALMAC_DBG_WARN, __VA_ARGS__) +#else +#define PLTFM_MSG_WARN(...) do {} while (0) +#endif + +#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_TRACE) +#define PLTFM_MSG_TRACE(...) \ + adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \ + HALMAC_DBG_TRACE, __VA_ARGS__) +#else +#define PLTFM_MSG_TRACE(...) do {} while (0) +#endif + +#else + +/* Disable debug msg */ +#define PLTFM_MSG_ERR(...) do {} while (0) +#define PLTFM_MSG_WARN(...) do {} while (0) +#define PLTFM_MSG_TRACE(...) do {} while (0) + #endif -#define HALMAC_REG_READ_8 pHalmac_api->halmac_reg_read_8 -#define HALMAC_REG_READ_16 pHalmac_api->halmac_reg_read_16 -#define HALMAC_REG_READ_32 pHalmac_api->halmac_reg_read_32 -#define HALMAC_REG_WRITE_8 pHalmac_api->halmac_reg_write_8 -#define HALMAC_REG_WRITE_16 pHalmac_api->halmac_reg_write_16 -#define HALMAC_REG_WRITE_32 pHalmac_api->halmac_reg_write_32 -#define HALMAC_REG_SDIO_CMD53_READ_N pHalmac_api->halmac_reg_sdio_cmd53_read_n +#define HALMAC_REG_R8(offset) api->halmac_reg_read_8(adapter, offset) +#define HALMAC_REG_R16(offset) api->halmac_reg_read_16(adapter, offset) +#define HALMAC_REG_R32(offset) api->halmac_reg_read_32(adapter, offset) +#define HALMAC_REG_W8(offset, val) api->halmac_reg_write_8(adapter, offset, val) +#define HALMAC_REG_W16(offset, val) \ + api->halmac_reg_write_16(adapter, offset, val) +#define HALMAC_REG_W32(offset, val) \ + api->halmac_reg_write_32(adapter, offset, val) +#define HALMAC_REG_SDIO_RN(offset, size, data) \ + api->halmac_reg_sdio_cmd53_read_n(adapter, offset, size, data) + +#define HALMAC_REG_W8_CLR(offset, mask) \ + HALMAC_REG_W8(offset, HALMAC_REG_R8(offset) & ~(mask)) +#define HALMAC_REG_W16_CLR(offset, mask) \ + HALMAC_REG_W16(offset, HALMAC_REG_R16(offset) & ~(mask)) +#define HALMAC_REG_W32_CLR(offset, mask) \ + HALMAC_REG_W32(offset, HALMAC_REG_R32(offset) & ~(mask)) + +#define HALMAC_REG_W8_SET(offset, mask) \ + HALMAC_REG_W8(offset, HALMAC_REG_R8(offset) | (mask)) +#define HALMAC_REG_W16_SET(offset, mask) \ + HALMAC_REG_W16(offset, HALMAC_REG_R16(offset) | (mask)) +#define HALMAC_REG_W32_SET(offset, mask) \ + HALMAC_REG_W32(offset, HALMAC_REG_R32(offset) | (mask)) /* Swap Little-endian <-> Big-endia*/ -#define SWAP32(x) ((u32)( \ - (((u32)(x) & (u32)0x000000ff) << 24) | \ - (((u32)(x) & (u32)0x0000ff00) << 8) | \ - (((u32)(x) & (u32)0x00ff0000) >> 8) | \ - (((u32)(x) & (u32)0xff000000) >> 24))) +#define SWAP32(x) \ + ((u32)((((u32)(x) & (u32)0x000000ff) << 24) | \ + (((u32)(x) & (u32)0x0000ff00) << 8) | \ + (((u32)(x) & (u32)0x00ff0000) >> 8) | \ + (((u32)(x) & (u32)0xff000000) >> 24))) -#define SWAP16(x) ((u16)( \ - (((u16)(x) & (u16)0x00ff) << 8) | \ - (((u16)(x) & (u16)0xff00) >> 8))) +#define SWAP16(x) \ + ((u16)((((u16)(x) & (u16)0x00ff) << 8) | \ + (((u16)(x) & (u16)0xff00) >> 8))) /*1->Little endian 0->Big endian*/ #if HALMAC_SYSTEM_ENDIAN @@ -139,16 +232,16 @@ #if !((HALMAC_PLATFORM_WINDOWS == 1) && (HALMAC_PLATFORM_TESTPROGRAM == 0)) /* Byte Swapping routine */ -#ifndef EF1Byte -#define EF1Byte (u8) +#ifndef EF1BYTE +#define EF1BYTE (u8) #endif -#ifndef EF2Byte -#define EF2Byte rtk_le16_to_cpu +#ifndef EF2BYTE +#define EF2BYTE rtk_le16_to_cpu #endif -#ifndef EF4Byte -#define EF4Byte rtk_le32_to_cpu +#ifndef EF4BYTE +#define EF4BYTE rtk_le32_to_cpu #endif /* Example: @@ -158,8 +251,7 @@ * BIT_LEN_MASK_32(32) => 0xFFFFFFFF */ #ifndef BIT_LEN_MASK_32 -#define BIT_LEN_MASK_32(__BitLen) \ - (0xFFFFFFFF >> (32 - (__BitLen))) +#define BIT_LEN_MASK_32(__bitlen) (0xFFFFFFFF >> (32 - (__bitlen))) #endif /* Example: @@ -167,29 +259,24 @@ * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 */ #ifndef BIT_OFFSET_LEN_MASK_32 -#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \ - (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) +#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ + (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) #endif /* Return 4-byte value in host byte ordering from * 4-byte pointer in litten-endian system */ #ifndef LE_P4BYTE_TO_HOST_4BYTE -#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ - (EF4Byte(*((u32 *)(__pStart)))) +#define LE_P4BYTE_TO_HOST_4BYTE(__start) (EF4BYTE(*((u32 *)(__start)))) #endif - /* Translate subfield (continuous bits in little-endian) of * 4-byte value in litten byte to 4-byte value in host byte ordering */ #ifndef LE_BITS_TO_4BYTE -#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - (LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) \ - & \ - BIT_LEN_MASK_32(__BitLen) \ - ) +#define LE_BITS_TO_4BYTE(__start, __bitoffset, __bitlen) \ + ((LE_P4BYTE_TO_HOST_4BYTE(__start) >> (__bitoffset)) & \ + BIT_LEN_MASK_32(__bitlen)) #endif /* Mask subfield (continuous bits in little-endian) of 4-byte @@ -197,50 +284,47 @@ * value in host byte ordering */ #ifndef LE_BITS_CLEARED_TO_4BYTE -#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ - & \ - (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)) \ - ) +#define LE_BITS_CLEARED_TO_4BYTE(__start, __bitoffset, __bitlen) \ + (LE_P4BYTE_TO_HOST_4BYTE(__start) & \ + (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen))) #endif /* Set subfield of little-endian 4-byte value to specified value */ #ifndef SET_BITS_TO_LE_4BYTE -#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ - do { \ - *((u32 *)(__pStart)) = \ - EF4Byte( \ - LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - | \ - ((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \ - ); \ +#define SET_BITS_TO_LE_4BYTE(__start, __bitoffset, __bitlen, __value) \ + do { \ + *((u32 *)(__start)) = \ + EF4BYTE( \ + LE_BITS_CLEARED_TO_4BYTE(__start, __bitoffset, __bitlen) | \ + ((((u32)__value) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset))\ + ); \ } while (0) #endif #ifndef HALMAC_BIT_OFFSET_VAL_MASK_32 -#define HALMAC_BIT_OFFSET_VAL_MASK_32(__BitVal, __BitOffset) \ - (__BitVal << (__BitOffset)) +#define HALMAC_BIT_OFFSET_VAL_MASK_32(__bitval, __bitoffset) \ + (__bitval << (__bitoffset)) #endif #ifndef SET_MEM_OP -#define SET_MEM_OP(Dw, Value32, Mask, Shift) \ - (((Dw) & ~((Mask) << (Shift))) | (((Value32) & (Mask)) << (Shift))) +#define SET_MEM_OP(dw, value32, mask, shift) \ + (((dw) & ~((mask) << (shift))) | (((value32) & (mask)) << (shift))) #endif #ifndef HALMAC_SET_DESC_FIELD_CLR -#define HALMAC_SET_DESC_FIELD_CLR(Dw, Value32, Mask, Shift) \ - (Dw = (rtk_cpu_to_le32(SET_MEM_OP(rtk_cpu_to_le32(Dw), Value32, Mask, Shift)))) +#define HALMAC_SET_DESC_FIELD_CLR(dw, value32, mask, shift) \ + (dw = (rtk_cpu_to_le32( \ + SET_MEM_OP(rtk_cpu_to_le32(dw), value32, mask, shift)))) #endif #ifndef HALMAC_SET_DESC_FIELD_NO_CLR -#define HALMAC_SET_DESC_FIELD_NO_CLR(Dw, Value32, Mask, Shift) \ - (Dw |= (rtk_cpu_to_le32(((Value32) & (Mask)) << (Shift)))) +#define HALMAC_SET_DESC_FIELD_NO_CLR(dw, value32, mask, shift) \ + (dw |= (rtk_cpu_to_le32(((value32) & (mask)) << (shift)))) #endif #ifndef HALMAC_GET_DESC_FIELD -#define HALMAC_GET_DESC_FIELD(Dw, Mask, Shift) \ - ((rtk_le32_to_cpu(Dw) >> (Shift)) & (Mask)) +#define HALMAC_GET_DESC_FIELD(dw, mask, shift) \ + ((rtk_le32_to_cpu(dw) >> (shift)) & (mask)) #endif #define HALMAC_SET_BD_FIELD_CLR HALMAC_SET_DESC_FIELD_CLR @@ -282,9 +366,10 @@ #endif /* HALMAC API return status*/ -typedef enum _HALMAC_RET_STATUS { +enum halmac_ret_status { HALMAC_RET_SUCCESS = 0x00, - HALMAC_RET_SUCCESS_ENQUEUE = 0x01, + HALMAC_RET_NOT_SUPPORT = 0x01, + HALMAC_RET_SUCCESS_ENQUEUE = 0x01, /*Don't use this return code!!*/ HALMAC_RET_PLATFORM_API_NULL = 0x02, HALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03, HALMAC_RET_MALLOC_FAIL = 0x04, @@ -292,7 +377,7 @@ typedef enum _HALMAC_RET_STATUS { HALMAC_RET_ITF_INCORRECT = 0x06, HALMAC_RET_DLFW_FAIL = 0x07, HALMAC_RET_PORT_NOT_SUPPORT = 0x08, - HALMAC_RET_TRXMODE_NOT_SUPPORT = 0x09, + HALMAC_RET_TXAGG_OVERFLOW = 0x09, HALMAC_RET_INIT_LLT_FAIL = 0x0A, HALMAC_RET_POWER_STATE_INVALID = 0x0B, HALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C, @@ -358,7 +443,6 @@ typedef enum _HALMAC_RET_STATUS { HALMAC_RET_EEPROM_PARSING_FAIL = 0x48, HALMAC_RET_EFUSE_NOT_ENOUGH = 0x49, HALMAC_RET_WRONG_ARGUMENT = 0x4A, - HALMAC_RET_NOT_SUPPORT = 0x4B, HALMAC_RET_C2H_NOT_HANDLED = 0x4C, HALMAC_RET_PARA_SENDING = 0x4D, HALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E, @@ -376,52 +460,37 @@ typedef enum _HALMAC_RET_STATUS { HALMAC_RET_OQT_NOT_ENOUGH = 0x5A, HALMAC_RET_PWR_UNCHANGE = 0x5B, HALMAC_RET_WRONG_INTF = 0x5C, + HALMAC_RET_POLLING_HIOE_REQ_FAIL = 0x5E, + HALMAC_RET_HIOE_CHKSUM_FAIL = 0x5F, + HALMAC_RET_HIOE_ERR = 0x60, HALMAC_RET_FW_NO_SUPPORT = 0x60, HALMAC_RET_TXFIFO_NO_EMPTY = 0x61, HALMAC_RET_SDIO_CLOCK_ERR = 0x62, HALMAC_RET_GET_PINMUX_ERR = 0x63, HALMAC_RET_PINMUX_USED = 0x64, HALMAC_RET_WRONG_GPIO = 0x65, -} HALMAC_RET_STATUS; - -typedef enum _HALMAC_MAC_CLOCK_HW_DEF { - HALMAC_MAC_CLOCK_HW_DEF_80M = 0, - HALMAC_MAC_CLOCK_HW_DEF_40M = 1, - HALMAC_MAC_CLOCK_HW_DEF_20M = 2, -} HALMAC_MAC_CLOCK_HW_DEF; - -/* Chip ID*/ -typedef enum _HALMAC_CHIP_ID { + HALMAC_RET_LTECOEX_READY_FAIL = 0x66, + HALMAC_RET_IDMEM_CHKSUM_FAIL = 0x67, + HALMAC_RET_ILLEGAL_KEY_FAIL = 0x68, + HALMAC_RET_FW_READY_CHK_FAIL = 0x69, + HALMAC_RET_RSVD_PG_OVERFLOW_FAIL = 0x70, + HALMAC_RET_THRESHOLD_FAIL = 0x71, + HALMAC_RET_SDIO_MIX_MODE = 0x72, + HALMAC_RET_TXDESC_SET_FAIL = 0x73, + HALMAC_RET_WLHDR_FAIL = 0x74, + HALMAC_RET_WLAN_MODE_FAIL = 0x75, +}; + +enum halmac_chip_id { HALMAC_CHIP_ID_8822B = 0, HALMAC_CHIP_ID_8821C = 1, HALMAC_CHIP_ID_8814B = 2, HALMAC_CHIP_ID_8197F = 3, + HALMAC_CHIP_ID_8822C = 4, HALMAC_CHIP_ID_UNDEFINE = 0x7F, -} HALMAC_CHIP_ID; - -typedef enum _HALMAC_CHIP_ID_HW_DEF { - HALMAC_CHIP_ID_HW_DEF_8723A = 0x01, - HALMAC_CHIP_ID_HW_DEF_8188E = 0x02, - HALMAC_CHIP_ID_HW_DEF_8881A = 0x03, - HALMAC_CHIP_ID_HW_DEF_8812A = 0x04, - HALMAC_CHIP_ID_HW_DEF_8821A = 0x05, - HALMAC_CHIP_ID_HW_DEF_8723B = 0x06, - HALMAC_CHIP_ID_HW_DEF_8192E = 0x07, - HALMAC_CHIP_ID_HW_DEF_8814A = 0x08, - HALMAC_CHIP_ID_HW_DEF_8821C = 0x09, - HALMAC_CHIP_ID_HW_DEF_8822B = 0x0A, - HALMAC_CHIP_ID_HW_DEF_8703B = 0x0B, - HALMAC_CHIP_ID_HW_DEF_8188F = 0x0C, - HALMAC_CHIP_ID_HW_DEF_8192F = 0x0D, - HALMAC_CHIP_ID_HW_DEF_8197F = 0x0E, - HALMAC_CHIP_ID_HW_DEF_8723D = 0x0F, - HALMAC_CHIP_ID_HW_DEF_8814B = 0x10, - HALMAC_CHIP_ID_HW_DEF_UNDEFINE = 0x7F, - HALMAC_CHIP_ID_HW_DEF_PS = 0xEA, -} HALMAC_CHIP_ID_HW_DEF; - -/* Chip Version*/ -typedef enum _HALMAC_CHIP_VER { +}; + +enum halmac_chip_ver { HALMAC_CHIP_VER_A_CUT = 0x00, HALMAC_CHIP_VER_B_CUT = 0x01, HALMAC_CHIP_VER_C_CUT = 0x02, @@ -430,33 +499,37 @@ typedef enum _HALMAC_CHIP_VER { HALMAC_CHIP_VER_F_CUT = 0x05, HALMAC_CHIP_VER_TEST = 0xFF, HALMAC_CHIP_VER_UNDEFINE = 0x7FFF, -} HALMAC_CHIP_VER; +}; -/* Network type select */ -typedef enum _HALMAC_NETWORK_TYPE_SELECT { +enum halmac_network_type_select { HALMAC_NETWORK_NO_LINK = 0, HALMAC_NETWORK_ADHOC = 1, HALMAC_NETWORK_INFRASTRUCTURE = 2, HALMAC_NETWORK_AP = 3, HALMAC_NETWORK_UNDEFINE = 0x7F, -} HALMAC_NETWORK_TYPE_SELECT; +}; -/* Transfer mode select */ -typedef enum _HALMAC_TRNSFER_MODE_SELECT { +enum halmac_transfer_mode_select { HALMAC_TRNSFER_NORMAL = 0x0, HALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB, HALMAC_TRNSFER_LOOPBACK_DELAY = 0x3, HALMAC_TRNSFER_UNDEFINE = 0x7F, -} HALMAC_TRNSFER_MODE_SELECT; +}; -/* Queue select */ -typedef enum _HALMAC_DMA_MAPPING { +enum halmac_dma_mapping { HALMAC_DMA_MAPPING_EXTRA = 0, HALMAC_DMA_MAPPING_LOW = 1, HALMAC_DMA_MAPPING_NORMAL = 2, HALMAC_DMA_MAPPING_HIGH = 3, HALMAC_DMA_MAPPING_UNDEFINE = 0x7F, -} HALMAC_DMA_MAPPING; +}; + +enum halmac_io_size { + HALMAC_IO_BYTE = 0x0, + HALMAC_IO_WORD = 0x1, + HALMAC_IO_DWORD = 0x2, + HALMAC_IO_UNDEFINE = 0x7F, +}; #define HALMAC_MAP2_HQ HALMAC_DMA_MAPPING_HIGH #define HALMAC_MAP2_NQ HALMAC_DMA_MAPPING_NORMAL @@ -464,8 +537,7 @@ typedef enum _HALMAC_DMA_MAPPING { #define HALMAC_MAP2_EXQ HALMAC_DMA_MAPPING_EXTRA #define HALMAC_MAP2_UNDEF HALMAC_DMA_MAPPING_UNDEFINE -/* TXDESC queue select TID */ -typedef enum _HALMAC_TXDESC_QUEUE_TID { +enum halmac_txdesc_queue_tid { HALMAC_TXDESC_QSEL_TID0 = 0, HALMAC_TXDESC_QSEL_TID1 = 1, HALMAC_TXDESC_QSEL_TID2 = 2, @@ -487,94 +559,143 @@ typedef enum _HALMAC_TXDESC_QUEUE_TID { HALMAC_TXDESC_QSEL_HIGH = 0x11, HALMAC_TXDESC_QSEL_MGT = 0x12, HALMAC_TXDESC_QSEL_H2C_CMD = 0x13, + HALMAC_TXDESC_QSEL_FWCMD = 0x14, HALMAC_TXDESC_QSEL_UNDEFINE = 0x7F, -} HALMAC_TXDESC_QUEUE_TID; - -typedef enum _HALMAC_PTCL_QUEUE { - HALMAC_PTCL_QUEUE_VO = 0x0, - HALMAC_PTCL_QUEUE_VI = 0x1, - HALMAC_PTCL_QUEUE_BE = 0x2, - HALMAC_PTCL_QUEUE_BK = 0x3, - HALMAC_PTCL_QUEUE_MG = 0x4, - HALMAC_PTCL_QUEUE_HI = 0x5, - HALMAC_PTCL_QUEUE_NUM = 0x6, - HALMAC_PTCL_QUEUE_UNDEFINE = 0x7F, -} HALMAC_PTCL_QUEUE; - -typedef enum { - HALMAC_QUEUE_SELECT_VO = HALMAC_TXDESC_QSEL_TID6, - HALMAC_QUEUE_SELECT_VI = HALMAC_TXDESC_QSEL_TID4, - HALMAC_QUEUE_SELECT_BE = HALMAC_TXDESC_QSEL_TID0, - HALMAC_QUEUE_SELECT_BK = HALMAC_TXDESC_QSEL_TID1, - HALMAC_QUEUE_SELECT_VO_V2 = HALMAC_TXDESC_QSEL_TID7, - HALMAC_QUEUE_SELECT_VI_V2 = HALMAC_TXDESC_QSEL_TID5, - HALMAC_QUEUE_SELECT_BE_V2 = HALMAC_TXDESC_QSEL_TID3, - HALMAC_QUEUE_SELECT_BK_V2 = HALMAC_TXDESC_QSEL_TID2, - HALMAC_QUEUE_SELECT_BCN = HALMAC_TXDESC_QSEL_BEACON, - HALMAC_QUEUE_SELECT_HIGH = HALMAC_TXDESC_QSEL_HIGH, - HALMAC_QUEUE_SELECT_MGNT = HALMAC_TXDESC_QSEL_MGT, - HALMAC_QUEUE_SELECT_CMD = HALMAC_TXDESC_QSEL_H2C_CMD, - HALMAC_QUEUE_SELECT_UNDEFINE = 0x7F, -} HALMAC_QUEUE_SELECT; - -typedef enum _HALMAC_ACQ_ID { +}; + +enum halmac_pq_map_id { + HALMAC_PQ_MAP_VO = 0x0, + HALMAC_PQ_MAP_VI = 0x1, + HALMAC_PQ_MAP_BE = 0x2, + HALMAC_PQ_MAP_BK = 0x3, + HALMAC_PQ_MAP_MG = 0x4, + HALMAC_PQ_MAP_HI = 0x5, + HALMAC_PQ_MAP_NUM = 0x6, + HALMAC_PQ_MAP_UNDEF = 0x7F, +}; + +enum halmac_qsel { + HALMAC_QSEL_VO = HALMAC_TXDESC_QSEL_TID6, + HALMAC_QSEL_VI = HALMAC_TXDESC_QSEL_TID4, + HALMAC_QSEL_BE = HALMAC_TXDESC_QSEL_TID0, + HALMAC_QSEL_BK = HALMAC_TXDESC_QSEL_TID1, + HALMAC_QSEL_VO_V2 = HALMAC_TXDESC_QSEL_TID7, + HALMAC_QSEL_VI_V2 = HALMAC_TXDESC_QSEL_TID5, + HALMAC_QSEL_BE_V2 = HALMAC_TXDESC_QSEL_TID3, + HALMAC_QSEL_BK_V2 = HALMAC_TXDESC_QSEL_TID2, + HALMAC_QSEL_TID8 = HALMAC_TXDESC_QSEL_TID8, + HALMAC_QSEL_TID9 = HALMAC_TXDESC_QSEL_TID9, + HALMAC_QSEL_TIDA = HALMAC_TXDESC_QSEL_TIDA, + HALMAC_QSEL_TIDB = HALMAC_TXDESC_QSEL_TIDB, + HALMAC_QSEL_TIDC = HALMAC_TXDESC_QSEL_TIDC, + HALMAC_QSEL_TIDD = HALMAC_TXDESC_QSEL_TIDD, + HALMAC_QSEL_TIDE = HALMAC_TXDESC_QSEL_TIDE, + HALMAC_QSEL_TIDF = HALMAC_TXDESC_QSEL_TIDF, + HALMAC_QSEL_BCN = HALMAC_TXDESC_QSEL_BEACON, + HALMAC_QSEL_HIGH = HALMAC_TXDESC_QSEL_HIGH, + HALMAC_QSEL_MGNT = HALMAC_TXDESC_QSEL_MGT, + HALMAC_QSEL_CMD = HALMAC_TXDESC_QSEL_H2C_CMD, + HALMAC_QSEL_FWCMD = HALMAC_TXDESC_QSEL_FWCMD, + HALMAC_QSEL_UNDEFINE = 0x7F, +}; + +enum halmac_acq_id { HALMAC_ACQ_ID_VO = 0, HALMAC_ACQ_ID_VI = 1, HALMAC_ACQ_ID_BE = 2, HALMAC_ACQ_ID_BK = 3, HALMAC_ACQ_ID_MAX = 0x7F, -} HALMAC_ACQ_ID; - -/* USB burst size */ -typedef enum _HALMAC_USB_BURST_SIZE { - HALMAC_USB_BURST_SIZE_3_0 = 0x0, - HALMAC_USB_BURST_SIZE_2_0_HSPEED = 0x1, - HALMAC_USB_BURST_SIZE_2_0_FSPEED = 0x2, - HALMAC_USB_BURST_SIZE_2_0_OTHERS = 0x3, - HALMAC_USB_BURST_SIZE_UNDEFINE = 0x7F, -} HALMAC_USB_BURST_SIZE; - -/* HAL API function parameters*/ -typedef enum _HALMAC_INTERFACE { +}; + +enum halmac_txdesc_dma_ch { + HALMAC_TXDESC_DMA_CH0 = 0, + HALMAC_TXDESC_DMA_CH1 = 1, + HALMAC_TXDESC_DMA_CH2 = 2, + HALMAC_TXDESC_DMA_CH3 = 3, + HALMAC_TXDESC_DMA_CH4 = 4, + HALMAC_TXDESC_DMA_CH5 = 5, + HALMAC_TXDESC_DMA_CH6 = 6, + HALMAC_TXDESC_DMA_CH7 = 7, + HALMAC_TXDESC_DMA_CH8 = 8, + HALMAC_TXDESC_DMA_CH9 = 9, + HALMAC_TXDESC_DMA_CH10 = 10, + HALMAC_TXDESC_DMA_CH11 = 11, + HALMAC_TXDESC_DMA_CH12 = 12, + HALMAC_TXDESC_DMA_CH13 = 13, + HALMAC_TXDESC_DMA_CH14 = 14, + HALMAC_TXDESC_DMA_CH15 = 15, + HALMAC_TXDESC_DMA_CH16 = 16, + HALMAC_TXDESC_DMA_CH17 = 17, + HALMAC_TXDESC_DMA_CH18 = 18, + HALMAC_TXDESC_DMA_CH19 = 19, + HALMAC_TXDESC_DMA_CH20 = 20, + HALMAC_TXDESC_DMA_CHMAX, + HALMAC_TXDESC_DMA_CHUNDEFINE = 0x7F, +}; + +enum halmac_dma_ch { + HALMAC_DMA_CH_0 = HALMAC_TXDESC_DMA_CH0, + HALMAC_DMA_CH_1 = HALMAC_TXDESC_DMA_CH1, + HALMAC_DMA_CH_2 = HALMAC_TXDESC_DMA_CH2, + HALMAC_DMA_CH_3 = HALMAC_TXDESC_DMA_CH3, + HALMAC_DMA_CH_4 = HALMAC_TXDESC_DMA_CH4, + HALMAC_DMA_CH_5 = HALMAC_TXDESC_DMA_CH5, + HALMAC_DMA_CH_6 = HALMAC_TXDESC_DMA_CH6, + HALMAC_DMA_CH_7 = HALMAC_TXDESC_DMA_CH7, + HALMAC_DMA_CH_8 = HALMAC_TXDESC_DMA_CH8, + HALMAC_DMA_CH_9 = HALMAC_TXDESC_DMA_CH9, + HALMAC_DMA_CH_10 = HALMAC_TXDESC_DMA_CH10, + HALMAC_DMA_CH_11 = HALMAC_TXDESC_DMA_CH11, + HALMAC_DMA_CH_S0 = HALMAC_TXDESC_DMA_CH12, + HALMAC_DMA_CH_S1 = HALMAC_TXDESC_DMA_CH13, + HALMAC_DMA_CH_MGQ = HALMAC_TXDESC_DMA_CH14, + HALMAC_DMA_CH_HIGH = HALMAC_TXDESC_DMA_CH15, + HALMAC_DMA_CH_FWCMD = HALMAC_TXDESC_DMA_CH16, + HALMAC_DMA_CH_MGQ_BAND1 = HALMAC_TXDESC_DMA_CH17, + HALMAC_DMA_CH_HIGH_BAND1 = HALMAC_TXDESC_DMA_CH18, + HALMAC_DMA_CH_BCN = HALMAC_TXDESC_DMA_CH19, + HALMAC_DMA_CH_H2C = HALMAC_TXDESC_DMA_CH20, + HALMAC_DMA_CH_MAX = HALMAC_TXDESC_DMA_CHMAX, + HALMAC_DMA_CH_UNDEFINE = 0x7F, +}; + +enum halmac_interface { HALMAC_INTERFACE_PCIE = 0x0, HALMAC_INTERFACE_USB = 0x1, HALMAC_INTERFACE_SDIO = 0x2, HALMAC_INTERFACE_AXI = 0x3, HALMAC_INTERFACE_UNDEFINE = 0x7F, -} HALMAC_INTERFACE; +}; -typedef enum _HALMAC_RX_AGG_MODE { +enum halmac_rx_agg_mode { HALMAC_RX_AGG_MODE_NONE = 0x0, HALMAC_RX_AGG_MODE_DMA = 0x1, HALMAC_RX_AGG_MODE_USB = 0x2, HALMAC_RX_AGG_MODE_UNDEFINE = 0x7F, -} HALMAC_RX_AGG_MODE; -typedef struct _HALMAC_RXAGG_TH { +}; + +struct halmac_rxagg_th { u8 drv_define; u8 timeout; u8 size; -} HALMAC_RXAGG_TH, *PHALMAC_RXAGG_TH; - -typedef struct _HALMAC_RXAGG_CFG { - HALMAC_RX_AGG_MODE mode; - HALMAC_RXAGG_TH threshold; -} HALMAC_RXAGG_CFG, *PHALMAC_RXAGG_CFG; - -typedef enum _HALMAC_MAC_POWER { - HALMAC_MAC_POWER_OFF = 0x0, - HALMAC_MAC_POWER_ON = 0x1, - HALMAC_MAC_POWER_UNDEFINE = 0x7F, -} HALMAC_MAC_POWER; - -typedef enum _HALMAC_PS_STATE { - HALMAC_PS_STATE_ACT = 0x0, - HALMAC_PS_STATE_LPS = 0x1, - HALMAC_PS_STATE_IPS = 0x2, - HALMAC_PS_STATE_UNDEFINE = 0x7F, -} HALMAC_PS_STATE; - -typedef enum _HALMAC_TRX_MODE { + u8 size_limit_en; +}; + +struct halmac_rxagg_cfg { + enum halmac_rx_agg_mode mode; + struct halmac_rxagg_th threshold; +}; + +struct halmac_api_registry { + u8 rx_exp_en:1; + u8 la_mode_en:1; + u8 cfg_drv_rsvd_pg_en:1; + u8 sdio_cmd53_4byte_en:1; + u8 rsvd:4; +}; + +enum halmac_trx_mode { HALMAC_TRX_MODE_NORMAL = 0x0, HALMAC_TRX_MODE_TRXSHARE = 0x1, HALMAC_TRX_MODE_WMM = 0x2, @@ -584,17 +705,17 @@ typedef enum _HALMAC_TRX_MODE { HALMAC_TRX_MODE_MAX = 0x6, HALMAC_TRX_MODE_WMM_LINUX = 0x7E, HALMAC_TRX_MODE_UNDEFINE = 0x7F, -} HALMAC_TRX_MODE; +}; -typedef enum _HALMAC_WIRELESS_MODE { +enum halmac_wireless_mode { HALMAC_WIRELESS_MODE_B = 0x0, HALMAC_WIRELESS_MODE_G = 0x1, HALMAC_WIRELESS_MODE_N = 0x2, HALMAC_WIRELESS_MODE_AC = 0x3, HALMAC_WIRELESS_MODE_UNDEFINE = 0x7F, -} HALMAC_WIRELESS_MODE; +}; -typedef enum _HALMAC_BW { +enum halmac_bw { HALMAC_BW_20 = 0x00, HALMAC_BW_40 = 0x01, HALMAC_BW_80 = 0x02, @@ -603,63 +724,56 @@ typedef enum _HALMAC_BW { HALMAC_BW_10 = 0x05, HALMAC_BW_MAX = 0x06, HALMAC_BW_UNDEFINE = 0x7F, -} HALMAC_BW; - +}; -typedef enum _HALMAC_EFUSE_READ_CFG { +enum halmac_efuse_read_cfg { HALMAC_EFUSE_R_AUTO = 0x00, HALMAC_EFUSE_R_DRV = 0x01, HALMAC_EFUSE_R_FW = 0x02, HALMAC_EFUSE_R_UNDEFINE = 0x7F, -} HALMAC_EFUSE_READ_CFG; +}; -typedef enum _HALMAC_DLFW_MEM { +enum halmac_dlfw_mem { HALMAC_DLFW_MEM_EMEM = 0x00, + HALMAC_DLFW_MEM_EMEM_RSVD_PG = 0x01, HALMAC_DLFW_MEM_UNDEFINE = 0x7F, -} HALMAC_DLFW_MEM; - -typedef struct _HALMAC_TX_DESC { - u32 Dword0; - u32 Dword1; - u32 Dword2; - u32 Dword3; - u32 Dword4; - u32 Dword5; - u32 Dword6; - u32 Dword7; - u32 Dword8; - u32 Dword9; - u32 Dword10; - u32 Dword11; -} HALMAC_TX_DESC, *PHALMAC_TX_DESC; - -typedef struct _HALMAC_RX_DESC { - u32 Dword0; - u32 Dword1; - u32 Dword2; - u32 Dword3; - u32 Dword4; - u32 Dword5; -} HALMAC_RX_DESC, *PHALMAC_RX_DESC; - -typedef struct _HALMAC_BCN_IE_INFO { - u8 func_en; - u8 size_th; - u8 timeout; - u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE]; -} HALMAC_BCN_IE_INFO, *PHALMAC_BCN_IE_INFO; - -typedef enum _HALMAC_REG_TYPE { - HALMAC_REG_TYPE_MAC = 0x0, - HALMAC_REG_TYPE_BB = 0x1, - HALMAC_REG_TYPE_RF = 0x2, - HALMAC_REG_TYPE_UNDEFINE = 0x7F, -} HALMAC_REG_TYPE; - -typedef enum _HALMAC_PARAMETER_CMD { - /* HALMAC_PARAMETER_CMD_LLT = 0x1, */ - /* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */ - /* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */ +}; + +struct halmac_tx_desc { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; + u32 dword9; + u32 dword10; + u32 dword11; +}; + +struct halmac_rx_desc { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; +}; + +struct halmac_bcn_ie_info { + u8 func_en; + u8 size_th; + u8 timeout; + u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE]; +}; + +enum halmac_parameter_cmd { + /* HALMAC_PARAMETER_CMD_LLT = 0x1, */ + /* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */ + /* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */ HALMAC_PARAMETER_CMD_MAC_W8 = 0x4, HALMAC_PARAMETER_CMD_MAC_W16 = 0x5, HALMAC_PARAMETER_CMD_MAC_W32 = 0x6, @@ -670,156 +784,159 @@ typedef enum _HALMAC_PARAMETER_CMD { HALMAC_PARAMETER_CMD_DELAY_US = 0X10, HALMAC_PARAMETER_CMD_DELAY_MS = 0X11, HALMAC_PARAMETER_CMD_END = 0XFF, -} HALMAC_PARAMETER_CMD; +}; -typedef union _HALMAC_PARAMETER_CONTENT { +union halmac_parameter_content { struct _MAC_REG_W { - u32 value; - u32 msk; - u16 offset; - u8 msk_en; + u32 value; + u32 msk; + u16 offset; + u8 msk_en; } MAC_REG_W; struct _BB_REG_W { - u32 value; - u32 msk; - u16 offset; - u8 msk_en; + u32 value; + u32 msk; + u16 offset; + u8 msk_en; } BB_REG_W; struct _RF_REG_W { - u32 value; - u32 msk; - u8 offset; - u8 msk_en; - u8 rf_path; + u32 value; + u32 msk; + u8 offset; + u8 msk_en; + u8 rf_path; } RF_REG_W; struct _DELAY_TIME { - u32 rsvd1; - u32 rsvd2; - u16 delay_time; - u8 rsvd3; + u32 rsvd1; + u32 rsvd2; + u16 delay_time; + u8 rsvd3; } DELAY_TIME; -} HALMAC_PARAMETER_CONTENT, *PHALMAC_PARAMETER_CONTENT; - -typedef struct _HALMAC_PHY_PARAMETER_INFO { - HALMAC_PARAMETER_CMD cmd_id; - HALMAC_PARAMETER_CONTENT content; -} HALMAC_PHY_PARAMETER_INFO, *PHALMAC_PHY_PARAMETER_INFO; - -typedef struct _HALMAC_H2C_INFO { - u16 h2c_seq_num; /* H2C sequence number */ - u8 in_use; /* 0 : empty 1 : used */ - HALMAC_H2C_RETURN_CODE status; -} HALMAC_H2C_INFO, *PHALMAC_H2C_INFO; - -typedef struct _HALMAC_PG_EFUSE_INFO { - u8 *pEfuse_map; - u32 efuse_map_size; - u8 *pEfuse_mask; +}; + +struct halmac_phy_parameter_info { + enum halmac_parameter_cmd cmd_id; + union halmac_parameter_content content; +}; + +struct halmac_pg_efuse_info { + u8 *efuse_map; + u32 efuse_map_size; + u8 *efuse_mask; u32 efuse_mask_size; -} HALMAC_PG_EFUSE_INFO, *PHALMAC_PG_EFUSE_INFO; - -typedef struct _HALMAC_TXAGG_BUFF_INFO { - u8 *pTx_agg_buf; - u8 *pCurr_pkt_buf; - u32 avai_buf_size; - u32 total_pkt_size; - u8 agg_num; -} HALMAC_TXAGG_BUFF_INFO, *PHALMAC_TXAGG_BUFF_INFO; - -typedef struct _HALMAC_CONFIG_PARA_INFO { - u32 para_buf_size; /* Parameter buffer size */ - u8 *pCfg_para_buf; /* Buffer for config parameter */ - u8 *pPara_buf_w; /* Write pointer of the parameter buffer */ - u32 para_num; /* Parameter numbers in parameter buffer */ - u32 avai_para_buf_size; /* Free size of parameter buffer */ - u32 offset_accumulation; - u32 value_accumulation; - HALMAC_DATA_TYPE data_type; /*DataType which is passed to FW*/ - u8 datapack_segment; /*DataPack Segment, from segment0...*/ - u8 full_fifo_mode; /* Used full tx fifo to save cfg parameter */ -} HALMAC_CONFIG_PARA_INFO, *PHALMAC_CONFIG_PARA_INFO; - -typedef struct _HALMAC_HW_CONFIG_INFO { - u32 efuse_size; /* Record efuse size */ - u32 eeprom_size; /* Record eeprom size */ - u32 bt_efuse_size; /* Record BT efuse size */ - u32 tx_fifo_size; /* Record tx fifo size */ - u32 rx_fifo_size; /* Record rx fifo size */ - u8 txdesc_size; /* Record tx desc size */ - u8 rxdesc_size; /* Record rx desc size */ - u32 page_size; /* Record page size */ +}; + +struct halmac_cfg_param_info { + u32 buf_size; + u8 *buf; + u8 *buf_wptr; + u32 num; + u32 avl_buf_size; + u32 offset_accum; + u32 value_accum; + enum halmac_data_type data_type; + u8 full_fifo_mode; +}; + +struct halmac_hw_cfg_info { + u32 efuse_size; + u32 eeprom_size; + u32 bt_efuse_size; + u32 tx_fifo_size; + u32 rx_fifo_size; + u32 rx_desc_fifo_size; + u32 page_size; u16 tx_align_size; - u8 page_size_2_power; - u8 cam_entry_num; /* Record CAM entry number */ + u8 txdesc_size; + u8 rxdesc_size; + u8 cam_entry_num; + u8 chk_security_keyid; + u8 txdesc_ie_max_num; + u8 txdesc_body_size; u8 ac_oqt_size; u8 non_ac_oqt_size; - u8 ac_queue_num; -} HALMAC_HW_CONFIG_INFO, *PHALMAC_HW_CONFIG_INFO; - -typedef struct _HALMAC_SDIO_FREE_SPACE { - u16 high_queue_number; /* Free space of HIQ */ - u16 normal_queue_number; /* Free space of MIDQ */ - u16 low_queue_number; /* Free space of LOWQ */ - u16 public_queue_number; /* Free space of PUBQ */ - u16 extra_queue_number; /* Free space of EXBQ */ - u8 ac_oqt_number; - u8 non_ac_oqt_number; + u8 acq_num; + u8 trx_mode; + u8 usb_txagg_num; +}; + +struct halmac_sdio_free_space { + u16 hiq_pg_num; + u16 miq_pg_num; + u16 lowq_pg_num; + u16 pubq_pg_num; + u16 exq_pg_num; + u8 ac_oqt_num; + u8 non_ac_oqt_num; u8 ac_empty; -} HALMAC_SDIO_FREE_SPACE, *PHALMAC_SDIO_FREE_SPACE; + u8 *macid_map; + u32 macid_map_size; +}; -typedef enum _HAL_FIFO_SEL { +enum hal_fifo_sel { HAL_FIFO_SEL_TX, HAL_FIFO_SEL_RX, HAL_FIFO_SEL_RSVD_PAGE, HAL_FIFO_SEL_REPORT, HAL_FIFO_SEL_LLT, HAL_FIFO_SEL_RXBUF_FW, -} HAL_FIFO_SEL; - -typedef enum _HALMAC_DRV_INFO { - HALMAC_DRV_INFO_NONE, /* No information is appended in rx_pkt */ - HALMAC_DRV_INFO_PHY_STATUS, /* PHY status is appended after rx_desc */ - HALMAC_DRV_INFO_PHY_SNIFFER, /* PHY status and sniffer info are appended after rx_desc */ - HALMAC_DRV_INFO_PHY_PLCP, /* PHY status and plcp header are appended after rx_desc */ + HAL_FIFO_SEL_RXBUF_PHY, + HAL_FIFO_SEL_RXDESC, + HAL_BUF_SECURITY_CAM, + HAL_BUF_WOW_CAM, + HAL_BUF_RX_FILTER_CAM, + HAL_BUF_BA_CAM, + HAL_BUF_MBSSID_CAM +}; + +enum halmac_drv_info { + /* No information is appended in rx_pkt */ + HALMAC_DRV_INFO_NONE, + /* PHY status is appended after rx_desc */ + HALMAC_DRV_INFO_PHY_STATUS, + /* PHY status and sniffer info are appended after rx_desc */ + HALMAC_DRV_INFO_PHY_SNIFFER, + /* PHY status and plcp header are appended after rx_desc */ + HALMAC_DRV_INFO_PHY_PLCP, HALMAC_DRV_INFO_UNDEFINE, -} HALMAC_DRV_INFO; +}; -typedef enum _HALMAC_PRI_CH_IDX { +enum halmac_pri_ch_idx { HALMAC_CH_IDX_UNDEFINE = 0, HALMAC_CH_IDX_1 = 1, HALMAC_CH_IDX_2 = 2, HALMAC_CH_IDX_3 = 3, HALMAC_CH_IDX_4 = 4, HALMAC_CH_IDX_MAX = 5, -} HALMAC_PRI_CH_IDX; +}; -typedef struct _HALMAC_CH_INFO { - HALMAC_CS_ACTION_ID action_id; - HALMAC_BW bw; - HALMAC_PRI_CH_IDX pri_ch_idx; +struct halmac_ch_info { + enum halmac_cs_action_id action_id; + enum halmac_bw bw; + enum halmac_pri_ch_idx pri_ch_idx; u8 channel; u8 timeout; u8 extra_info; -} HALMAC_CH_INFO, *PHALMAC_CH_INFO; +}; -typedef struct _HALMAC_CH_EXTRA_INFO { +struct halmac_ch_extra_info { u8 extra_info; - HALMAC_CS_EXTRA_ACTION_ID extra_action_id; + enum halmac_cs_extra_action_id extra_action_id; u8 extra_info_size; u8 *extra_info_data; -} HALMAC_CH_EXTRA_INFO, *PHALMAC_CH_EXTRA_INFO; +}; -typedef enum _HALMAC_CS_PERIODIC_OPTION { +enum halmac_cs_periodic_option { HALMAC_CS_PERIODIC_NONE, HALMAC_CS_PERIODIC_NORMAL, HALMAC_CS_PERIODIC_2_PHASE, HALMAC_CS_PERIODIC_SEAMLESS, -} HALMAC_CS_PERIODIC_OPTION; +}; -typedef struct _HALMAC_CH_SWITCH_OPTION { - HALMAC_BW dest_bw; - HALMAC_CS_PERIODIC_OPTION periodic_option; - HALMAC_PRI_CH_IDX dest_pri_ch_idx; +struct halmac_ch_switch_option { + enum halmac_bw dest_bw; + enum halmac_cs_periodic_option periodic_option; + enum halmac_pri_ch_idx dest_pri_ch_idx; /* u32 tsf_high; */ u32 tsf_low; u8 switch_en; @@ -827,27 +944,51 @@ typedef struct _HALMAC_CH_SWITCH_OPTION { u8 absolute_time_en; u8 dest_ch; u8 normal_period; + u8 normal_period_sel; u8 normal_cycle; u8 phase_2_period; -} HALMAC_CH_SWITCH_OPTION, *PHALMAC_CH_SWITCH_OPTION; + u8 phase_2_period_sel; +}; + +struct halmac_p2pps { + u8 offload_en:1; + u8 role:1; + u8 ctwindow_en:1; + u8 noa_en:1; + u8 noa_sel:1; + u8 all_sta_sleep:1; + u8 discovery:1; + u8 disable_close_rf:1; + u8 p2p_port_id; + u8 p2p_group; + u8 p2p_macid; + u8 ctwindow_length; + u8 rsvd3; + u8 rsvd4; + u8 rsvd5; + u32 noa_duration_para; + u32 noa_interval_para; + u32 noa_start_time_para; + u32 noa_count_para; +}; -typedef struct _HALMAC_FW_BUILD_TIME { +struct halmac_fw_build_time { u16 year; u8 month; u8 date; u8 hour; u8 min; -} HALMAC_FW_BUILD_TIME, *PHALMAC_FW_BUILD_TIME; +}; -typedef struct _HALMAC_FW_VERSION { +struct halmac_fw_version { u16 version; u8 sub_version; u8 sub_index; u16 h2c_version; - HALMAC_FW_BUILD_TIME build_time; -} HALMAC_FW_VERSION, *PHALMAC_FW_VERSION; + struct halmac_fw_build_time build_time; +}; -typedef enum _HALMAC_RF_TYPE { +enum halmac_rf_type { HALMAC_RF_1T2R = 0, HALMAC_RF_2T4R = 1, HALMAC_RF_2T2R = 2, @@ -858,43 +999,35 @@ typedef enum _HALMAC_RF_TYPE { HALMAC_RF_3T4R = 7, HALMAC_RF_4T4R = 8, HALMAC_RF_MAX_TYPE = 0xF, -} HALMAC_RF_TYPE; +}; -typedef struct _HALMAC_GENERAL_INFO { +struct halmac_general_info { u8 rfe_type; - HALMAC_RF_TYPE rf_type; -} HALMAC_GENERAL_INFO, *PHALMAC_GENERAL_INFO; + enum halmac_rf_type rf_type; + u8 tx_ant_status; + u8 rx_ant_status; +}; -typedef struct _HALMAC_PWR_TRACKING_PARA { +struct halmac_pwr_tracking_para { u8 enable; u8 tx_pwr_index; u8 pwr_tracking_offset_value; u8 tssi_value; -} HALMAC_PWR_TRACKING_PARA, *PHALMAC_PWR_TRACKING_PARA; +}; -typedef struct _HALMAC_PWR_TRACKING_OPTION { +struct halmac_pwr_tracking_option { u8 type; u8 bbswing_index; - HALMAC_PWR_TRACKING_PARA pwr_tracking_para[4]; /* pathA, pathB, pathC, pathD */ -} HALMAC_PWR_TRACKING_OPTION, *PHALMAC_PWR_TRACKING_OPTION; - -typedef struct _HALMAC_NLO_CFG { - u8 num_of_ssid; - u8 num_of_hidden_ap; - u8 rsvd[2]; - u32 pattern_check; - u32 rsvd1; - u32 rsvd2; - u8 ssid_len[HALMAC_SUPPORT_NLO_NUM]; - u8 ChiperType[HALMAC_SUPPORT_NLO_NUM]; - u8 rsvd3[HALMAC_SUPPORT_NLO_NUM]; - u8 loc_probeReq[HALMAC_SUPPORT_PROBE_REQ_NUM]; - u8 rsvd4[56]; - u8 ssid[HALMAC_SUPPORT_NLO_NUM][HALMAC_MAX_SSID_LEN]; -} HALMAC_NLO_CFG, *PHALMAC_NLO_CFG; - - -typedef enum _HALMAC_DATA_RATE { + /* pathA, pathB, pathC, pathD */ + struct halmac_pwr_tracking_para pwr_tracking_para[4]; +}; + +struct halmac_fast_edca_cfg { + enum halmac_acq_id acq_id; + u8 queue_to; /* unit : 32us*/ +}; + +enum halmac_data_rate { HALMAC_CCK1, HALMAC_CCK2, HALMAC_CCK5_5, @@ -978,24 +1111,22 @@ typedef enum _HALMAC_DATA_RATE { HALMAC_VHT_NSS4_MCS6, HALMAC_VHT_NSS4_MCS7, HALMAC_VHT_NSS4_MCS8, - HALMAC_VHT_NSS4_MCS9 -} HALMAC_DATA_RATE; - -typedef enum _HALMAC_RF_PATH { + HALMAC_VHT_NSS4_MCS9, + /*FPGA only*/ + HALMAC_VHT_NSS5_MCS0, + HALMAC_VHT_NSS6_MCS0, + HALMAC_VHT_NSS7_MCS0, + HALMAC_VHT_NSS8_MCS0 +}; + +enum halmac_rf_path { HALMAC_RF_PATH_A, HALMAC_RF_PATH_B, HALMAC_RF_PATH_C, HALMAC_RF_PATH_D -} HALMAC_RF_PATH; +}; -typedef enum _HALMAC_SND_PKT_SEL { - HALMAC_UNI_NDPA, - HALMAC_BMC_NDPA, - HALMAC_NON_FINAL_BFRPRPOLL, - HALMAC_FINAL_BFRPTPOLL, -} HALMAC_SND_PKT_SEL; - -typedef enum _HAL_SECURITY_TYPE { +enum hal_security_type { HAL_SECURITY_TYPE_NONE = 0, HAL_SECURITY_TYPE_WEP40 = 1, HAL_SECURITY_TYPE_WEP104 = 2, @@ -1008,158 +1139,32 @@ typedef enum _HAL_SECURITY_TYPE { HAL_SECURITY_TYPE_GCMSMS4 = 9, HAL_SECURITY_TYPE_BIP = 10, HAL_SECURITY_TYPE_UNDEFINE = 0x7F, -} HAL_SECURITY_TYPE; +}; -typedef enum _HAL_INTF_PHY { +enum hal_intf_phy { HAL_INTF_PHY_USB2 = 0, HAL_INTF_PHY_USB3 = 1, HAL_INTF_PHY_PCIE_GEN1 = 2, HAL_INTF_PHY_PCIE_GEN2 = 3, HAL_INTF_PHY_UNDEFINE = 0x7F, -} HAL_INTF_PHY; - -#if HALMAC_PLATFORM_TESTPROGRAM +}; -typedef enum _HALMAC_PWR_SEQ_ID { - HALMAC_PWR_SEQ_ENABLE, - HALMAC_PWR_SEQ_DISABLE, - HALMAC_PWR_SEQ_ENTER_LPS, - HALMAC_PWR_SEQ_ENTER_DEEP_LPS, - HALMAC_PWR_SEQ_LEAVE_LPS, - HALMAC_PWR_SEQ_MAX -} HALMAC_PWR_SEQ_ID; - -typedef enum _HAL_TX_ID { - HAL_TX_ID_VO, - HAL_TX_ID_VI, - HAL_TX_ID_BE, - HAL_TX_ID_BK, - HAL_TX_ID_BCN, - HAL_TX_ID_H2C, - HAL_TX_ID_MAX -} HAL_TX_ID; - -typedef enum _HAL_RTS_MODE { - HAL_RTS_MODE_NONE, - HAL_RTS_MODE_CTS2SELF, - HAL_RTS_MODE_RTS, -} HAL_RTS_MODE; - -typedef enum _HAL_DATA_BW { - HAL_DATA_BW_20M, - HAL_DATA_BW_40M, - HAL_DATA_BW_80M, - HAL_DATA_BW_160M, -} HAL_DATA_BW; - -typedef enum _HAL_RTS_SHORT { - HAL_RTS_SHORT_SHORT, - HAL_RTS_SHORT_LONG, -} HAL_RTS_SHORT; - -typedef enum _HAL_SECURITY_METHOD { - HAL_SECURITY_METHOD_HW = 0, - HAL_SECURITY_METHOD_SW = 1, - HAL_SECURITY_METHOD_UNDEFINE = 0x7F, -} HAL_SECURITY_METHOD; - -typedef struct _HAL_TXDESC_INFO { - u32 txdesc_length; - u32 packet_size; /* payload + wlheader */ - HAL_TX_ID tx_id; - HALMAC_DATA_RATE data_rate; - HAL_RTS_MODE rts_mode; - HAL_DATA_BW data_bw; - HAL_RTS_SHORT rts_short; - HAL_SECURITY_TYPE security_type; - HAL_SECURITY_METHOD encryption_method; - u16 seq_num; - u8 retry_limit_en; - u8 retry_limit_number; - u8 rts_threshold; - u8 qos; - u8 ht; - u8 ampdu; - u8 early_mode; - u8 bm_cast; - u8 data_short; - u8 mac_id; -} HAL_TXDESC_INFO, *PHAL_TXDESC_INFO; - -typedef struct _HAL_RXDESC_INFO { - u8 c2h; - u8 *pWifi_pkt; - u32 packet_size; - u8 crc_err; - u8 icv_err; -} HAL_RXDESC_INFO, *PHAL_RXDESC_INFO; - -typedef struct _HAL_TXDESC_PARSER { - u8 txdesc_len; - u16 txpkt_size; -} HAL_TXDESC_PARSER, *PHAL_TXDESC_PARSER; - -typedef struct _HAL_RXDESC_PARSER { - u32 driver_info_size; - u16 rxpkt_size; - u8 rxdesc_len; - u8 c2h; - u8 crc_err; - u8 icv_err; -} HAL_RXDESC_PARSER, *PHAL_RXDESC_PARSER; - -typedef struct _HAL_RF_REG_INFO { - HALMAC_RF_PATH rf_path; - u32 offset; - u32 bit_mask; - u32 data; -} HAL_RF_REG_INFO, *PHAL_RF_REG_INFO; - -typedef struct _HALMAC_SDIO_HIMR_INFO { - u8 rx_request; - u8 aval_msk; -} HALMAC_SDIO_HIMR_INFO, *PHALMAC_SDIO_HIMR_INFO; - -typedef struct _HALMAC_BEACON_INFO { -} HALMAC_BEACON_INFO, *PHALMAC_BEACON_INFO; - -typedef struct _HALMAC_MGNT_INFO { - u8 mu_enable; - u8 bip; - u8 unicast; - u32 packet_size; -} HALMAC_MGNT_INFO, *PHALMAC_MGNT_INFO; - -typedef struct _HALMAC_CTRL_INFO { - u8 snd_enable; - HALMAC_SND_PKT_SEL snd_pkt_sel; /* 0:unicast ndpa 1:broadcast ndpa 3:non-final BF Rpt Poll 4:final BF Rpt Poll */ - u8 *pPacket_desc; - u32 desc_size; - u16 seq_num; - u8 bw; - u16 paid; -} HALMAC_CTRL_INFO, *PHALMAC_CTRL_INFO; - -typedef struct _HALMAC_HIGH_QUEUE_INFO { - u8 *pPacket_desc; - u32 desc_size; -} HALMAC_HIGH_QUEUE_INFO, *PHALMAC_HIGH_QUEUE_INFO; - -typedef struct _HALMAC_CHIP_TYPE { - HALMAC_CHIP_ID chip_id; - HALMAC_CHIP_VER chip_version; -} HALMAC_CHIP_TYPE, *PHALMAC_CHIP_TYPE; +struct halmac_cut_amsdu_cfg { + u8 cut_amsdu_en; + u8 chk_len_en; + u8 chk_len_def_val; + u8 chk_len_l_th; + u16 chk_len_h_th; +}; -#endif /* End of test program */ - -typedef enum _HALMAC_DBG_MSG_INFO { +enum halmac_dbg_msg_info { HALMAC_DBG_ALWAYS, HALMAC_DBG_ERR, HALMAC_DBG_WARN, HALMAC_DBG_TRACE, -} HALMAC_DBG_MSG_INFO; +}; -typedef enum _HALMAC_DBG_MSG_TYPE { +enum halmac_dbg_msg_type { HALMAC_MSG_INIT, HALMAC_MSG_EFUSE, HALMAC_MSG_FW, @@ -1169,19 +1174,10 @@ typedef enum _HALMAC_DBG_MSG_TYPE { HALMAC_MSG_COMMON, HALMAC_MSG_DBI, HALMAC_MSG_MDIO, - HALMAC_MSG_USB -} HALMAC_DBG_MSG_TYPE; - -typedef enum _HALMAC_CMD_PROCESS_STATUS { - HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */ - HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */ - HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */ - HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */ - HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */ - HALMAC_CMD_PROCESS_UNDEFINE = 0x7F, -} HALMAC_CMD_PROCESS_STATUS; - -typedef enum _HALMAC_FEATURE_ID { + HALMAC_MSG_USB, +}; + +enum halmac_feature_id { HALMAC_FEATURE_CFG_PARA, /* Support */ HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, /* Support */ HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, /* Support */ @@ -1192,339 +1188,189 @@ typedef enum _HALMAC_FEATURE_ID { HALMAC_FEATURE_IQK, /* Support */ HALMAC_FEATURE_POWER_TRACKING, /* Support */ HALMAC_FEATURE_PSD, /* Support */ + HALMAC_FEATURE_FW_SNDING, /* Support */ HALMAC_FEATURE_ALL, /* Support, only for reset */ -} HALMAC_FEATURE_ID; +}; -typedef enum _HALMAC_DRV_RSVD_PG_NUM { +enum halmac_drv_rsvd_pg_num { + HALMAC_RSVD_PG_NUM8, /* 1K */ HALMAC_RSVD_PG_NUM16, /* 2K */ HALMAC_RSVD_PG_NUM24, /* 3K */ HALMAC_RSVD_PG_NUM32, /* 4K */ -} HALMAC_DRV_RSVD_PG_NUM; + HALMAC_RSVD_PG_NUM64, /* 8K */ + HALMAC_RSVD_PG_NUM128, /* 16K */ +}; -typedef enum _HALMAC_PCIE_CFG { +enum halmac_pcie_cfg { HALMAC_PCIE_GEN1, HALMAC_PCIE_GEN2, HALMAC_PCIE_CFG_UNDEFINE, -} HALMAC_PCIE_CFG; +}; -typedef enum _HALMAC_PORTID { +enum halmac_portid { HALMAC_PORTID0 = 0, HALMAC_PORTID1 = 1, HALMAC_PORTID2 = 2, HALMAC_PORTID3 = 3, HALMAC_PORTID4 = 4, - HALMAC_PORTIDMAX -} HALMAC_PORTID; - -typedef struct _HALMAC_P2PPS { - /*DW0*/ - u8 offload_en:1; - u8 role:1; - u8 ctwindow_en:1; - u8 noa_en:1; - u8 noa_sel:1; - u8 all_sta_sleep:1; - u8 discovery:1; - u8 rsvd2:1; - u8 p2p_port_id; - u8 p2p_group; - u8 p2p_macid; - - /*DW1*/ - u8 ctwindow_length; - u8 rsvd3; - u8 rsvd4; - u8 rsvd5; - - /*DW2*/ - u32 noa_duration_para; - - /*DW3*/ - u32 noa_interval_para; - - /*DW4*/ - u32 noa_start_time_para; - - /*DW5*/ - u32 noa_count_para; -} HALMAC_P2PPS, *PHALMAC_P2PPS; - - -/* Platform API setting */ -typedef struct _HALMAC_PLATFORM_API { - /* R/W register */ - u8 (*SDIO_CMD52_READ)(VOID *pDriver_adapter, u32 offset); - u8 (*SDIO_CMD53_READ_8)(VOID *pDriver_adapter, u32 offset); - u16 (*SDIO_CMD53_READ_16)(VOID *pDriver_adapter, u32 offset); - u32 (*SDIO_CMD53_READ_32)(VOID *pDriver_adapter, u32 offset); - u8 (*SDIO_CMD53_READ_N)(VOID *pDriver_adapter, u32 offset, u32 size, u8 *data); - VOID (*SDIO_CMD52_WRITE)(VOID *pDriver_adapter, u32 offset, u8 value); - VOID (*SDIO_CMD53_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value); - VOID (*SDIO_CMD53_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value); - VOID (*SDIO_CMD53_WRITE_32)(VOID *pDriver_adapter, u32 offset, u32 value); - u8 (*REG_READ_8)(VOID *pDriver_adapter, u32 offset); - u16 (*REG_READ_16)(VOID *pDriver_adapter, u32 offset); - u32 (*REG_READ_32)(VOID *pDriver_adapter, u32 offset); - VOID (*REG_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value); - VOID (*REG_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value); - VOID (*REG_WRITE_32)(VOID *pDriver_adapter, u32 offset, u32 value); - - /* send pBuf to reserved page, the tx_desc is not included in pBuf, driver need to fill tx_desc with qsel = bcn */ - u8 (*SEND_RSVD_PAGE)(VOID *pDriver_adapter, u8 *pBuf, u32 size); - /* send pBuf to h2c queue, the tx_desc is not included in pBuf, driver need to fill tx_desc with qsel = h2c */ - u8 (*SEND_H2C_PKT)(VOID *pDriver_adapter, u8 *pBuf, u32 size); - - u8 (*RTL_FREE)(VOID *pDriver_adapter, VOID *pBuf, u32 size); - VOID* (*RTL_MALLOC)(VOID *pDriver_adapter, u32 size); - u8 (*RTL_MEMCPY)(VOID *pDriver_adapter, VOID *dest, VOID *src, u32 size); - u8 (*RTL_MEMSET)(VOID *pDriver_adapter, VOID *pAddress, u8 value, u32 size); - VOID (*RTL_DELAY_US)(VOID *pDriver_adapter, u32 us); - - u8 (*MUTEX_INIT)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); - u8 (*MUTEX_DEINIT)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); - u8 (*MUTEX_LOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); - u8 (*MUTEX_UNLOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); - - u8 (*MSG_PRINT)(VOID *pDriver_adapter, u32 msg_type, u8 msg_level, s8 *fmt, ...); - u8 (*BUFF_PRINT)(VOID *pDriver_adapter, u32 msg_type, u8 msg_level, s8 *buf, u32 size); - - u8 (*EVENT_INDICATION)(VOID *pDriver_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS process_status, u8 *buf, u32 size); - -#if HALMAC_PLATFORM_TESTPROGRAM - VOID* (*PCI_ALLOC_COMM_BUFF)(VOID *pDriver_adapter, u32 size, u32 *physical_addr, u8 cache_en); - VOID (*PCI_FREE_COMM_BUFF)(VOID *pDriver_adapter, u32 size, u32 physical_addr, VOID *virtual_addr, u8 cache_en); - u8 (*WRITE_DATA_SDIO_ADDR)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u32 addr); - u8 (*WRITE_DATA_USB_BULKOUT_ID)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u8 bulkout_id); - u8 (*WRITE_DATA_PCIE_QUEUE)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u8 queue); - u8 (*READ_DATA)(VOID *pDriver_adapter, u8 *pBuf, u32 *read_length); -#endif -} HALMAC_PLATFORM_API, *PHALMAC_PLATFORM_API; - -/*1->Little endian 0->Big endian*/ -#if HALMAC_SYSTEM_ENDIAN - -#else - -#endif - -/* User can not use members in Address_L_H, use Address[6] is mandatory */ -typedef union _HALMAC_WLAN_ADDR { - u8 Address[6]; /* WLAN address (MACID, BSSID, Brodcast ID). Address[0] is lowest, Address[5] is highest*/ + HALMAC_PORTID_NUM = 5, +}; + +struct halmac_bcn_ctrl { + u8 dis_rx_bssid_fit; + u8 en_txbcn_rpt; + u8 dis_tsf_udt; + u8 en_bcn; + u8 en_rxbcn_rpt; + u8 en_p2p_ctwin; + u8 en_p2p_bcn_area; +}; + +/* User only can use Address[6]*/ +/* Address[0] is lowest, Address[5] is highest */ +union halmac_wlan_addr { + u8 addr[6]; struct { union { - u32 Address_Low; - u8 Address_Low_B[4]; + u32 low; + u8 low_byte[4]; }; union { - u16 Address_High; - u8 Address_High_B[2]; + u16 high; + u8 high_byte[2]; }; - } Address_L_H; -} HALMAC_WLAN_ADDR, *PHALMAC_WLAN_ADDR; + } addr_l_h; +}; + +struct halmac_platform_api { + /* R/W register */ + u8 (*SDIO_CMD52_READ)(void *drv_adapter, u32 offset); + u8 (*SDIO_CMD53_READ_8)(void *drv_adapter, u32 offset); + u16 (*SDIO_CMD53_READ_16)(void *drv_adapter, u32 offset); + u32 (*SDIO_CMD53_READ_32)(void *drv_adapter, u32 offset); + u8 (*SDIO_CMD53_READ_N)(void *drv_adapter, u32 offset, u32 size, + u8 *data); + void (*SDIO_CMD52_WRITE)(void *drv_adapter, u32 offset, u8 value); + void (*SDIO_CMD53_WRITE_8)(void *drv_adapter, u32 offset, u8 value); + void (*SDIO_CMD53_WRITE_16)(void *drv_adapter, u32 offset, u16 value); + void (*SDIO_CMD53_WRITE_32)(void *drv_adapter, u32 offset, u32 value); + u8 (*REG_READ_8)(void *drv_adapter, u32 offset); + u16 (*REG_READ_16)(void *drv_adapter, u32 offset); + u32 (*REG_READ_32)(void *drv_adapter, u32 offset); + void (*REG_WRITE_8)(void *drv_adapter, u32 offset, u8 value); + void (*REG_WRITE_16)(void *drv_adapter, u32 offset, u16 value); + void (*REG_WRITE_32)(void *drv_adapter, u32 offset, u32 value); + u8 (*SDIO_CMD52_CIA_READ)(void *drv_adapter, u32 offset); + + /* send pBuf to reserved page, the tx_desc is not included in pBuf */ + /* driver need to fill tx_desc with qsel = bcn */ + u8 (*SEND_RSVD_PAGE)(void *drv_adapter, u8 *buf, u32 size); + /* send pBuf to h2c queue, the tx_desc is not included in pBuf */ + /* driver need to fill tx_desc with qsel = h2c */ + u8 (*SEND_H2C_PKT)(void *drv_adapter, u8 *buf, u32 size); + /* send pBuf to fw cmd queue, the tx_desc is not included in pBuf */ + /*driver need to fill tx_desc with qsel = h2c */ + u8 (*SEND_FWCMD)(void *drv_adapter, u8 *buf, u32 size); + + u8 (*RTL_FREE)(void *drv_adapter, void *buf, u32 size); + void* (*RTL_MALLOC)(void *drv_adapter, u32 size); + u8 (*RTL_MEMCPY)(void *drv_adapter, void *dest, void *src, u32 size); + u8 (*RTL_MEMSET)(void *drv_adapter, void *addr, u8 value, u32 size); + void (*RTL_DELAY_US)(void *drv_adapter, u32 us); + + u8 (*MUTEX_INIT)(void *drv_adapter, HALMAC_MUTEX *mutex); + u8 (*MUTEX_DEINIT)(void *drv_adapter, HALMAC_MUTEX *mutex); + u8 (*MUTEX_LOCK)(void *drv_adapter, HALMAC_MUTEX *mutex); + u8 (*MUTEX_UNLOCK)(void *drv_adapter, HALMAC_MUTEX *mutex); + + u8 (*MSG_PRINT)(void *drv_adapter, u32 msg_type, u8 msg_level, + s8 *fmt, ...); + u8 (*BUFF_PRINT)(void *drv_adapter, u32 msg_type, u8 msg_level, s8 *buf, + u32 size); + + u8 (*EVENT_INDICATION)(void *drv_adapter, + enum halmac_feature_id feature_id, + enum halmac_cmd_process_status process_status, + u8 *buf, u32 size); + +#if HALMAC_PLATFORM_TESTPROGRAM + struct halmisc_platform_api *halmisc_pltfm_api; +#endif +}; -typedef enum _HALMAC_SND_ROLE { +enum halmac_snd_role { HAL_BFER = 0, HAL_BFEE = 1, -} HALMAC_SND_ROLE; +}; -typedef enum _HALMAC_CSI_SEG_LEN { +enum halmac_csi_seg_len { HAL_CSI_SEG_4K = 0, HAL_CSI_SEG_8K = 1, HAL_CSI_SEG_11K = 2, -} HALMAC_CSI_SEG_LEN; +}; -typedef struct _HALMAC_CFG_MUMIMO_PARA { - HALMAC_SND_ROLE role; +struct halmac_cfg_mumimo_para { + enum halmac_snd_role role; u8 sounding_sts[6]; u16 grouping_bitmap; u8 mu_tx_en; u32 given_gid_tab[2]; u32 given_user_pos[4]; -} HALMAC_CFG_MUMIMO_PARA, *PHALMAC_CFG_MUMIMO_PARA; +}; -typedef struct _HALMAC_SU_BFER_INIT_PARA { +struct halmac_su_bfer_init_para { u8 userid; u16 paid; u16 csi_para; - HALMAC_WLAN_ADDR bfer_address; -} HALMAC_SU_BFER_INIT_PARA, *PHALMAC_SU_BFER_INIT_PARA; + union halmac_wlan_addr bfer_address; +}; -typedef struct _HALMAC_MU_BFEE_INIT_PARA { +struct halmac_mu_bfee_init_para { u8 userid; u16 paid; - u32 user_position_l; - u32 user_position_h; -} HALMAC_MU_BFEE_INIT_PARA, *PHALMAC_MU_BFEE_INIT_PARA; + u32 user_position_l; /*for gid 0~15*/ + u32 user_position_h; /*for gid 16~31*/ + u32 user_position_l_1; /*for gid 32~47*/ + u32 user_position_h_1; /*for gid 48~63*/ +}; -typedef struct _HALMAC_MU_BFER_INIT_PARA { +struct halmac_mu_bfer_init_para { u16 paid; u16 csi_para; u16 my_aid; - HALMAC_CSI_SEG_LEN csi_length_sel; - HALMAC_WLAN_ADDR bfer_address; -} HALMAC_MU_BFER_INIT_PARA, *PHALMAC_MU_BFER_INIT_PARA; + enum halmac_csi_seg_len csi_length_sel; + union halmac_wlan_addr bfer_address; +}; -typedef struct _HALMAC_SND_INFO { - u16 paid; - u8 userid; - HALMAC_DATA_RATE ndpa_rate; - u16 csi_para; - u16 my_aid; - HALMAC_DATA_RATE csi_rate; - HALMAC_CSI_SEG_LEN csi_length_sel; - HALMAC_SND_ROLE role; - HALMAC_WLAN_ADDR bfer_address; - HALMAC_BW bw; - u8 txbf_en; - PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init; - PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init; - PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init; -} HALMAC_SND_INFO, *PHALMAC_SND_INFO; - -typedef struct _HALMAC_CS_INFO { - u8 *ch_info_buf; - u8 *ch_info_buf_w; +struct halmac_ch_sw_info { + u8 *buf; + u8 *buf_wptr; u8 extra_info_en; - u32 buf_size; /* buffer size */ - u32 avai_buf_size; /* buffer size */ - u32 total_size; - u32 accu_timeout; - u32 ch_num; -} HALMAC_CS_INFO, *PHALMAC_CS_INFO; - -typedef struct _HALMAC_RESTORE_INFO { - u32 mac_register; - u32 value; - u8 length; -} HALMAC_RESTORE_INFO, *PHALMAC_RESTORE_INFO; - -typedef struct _HALMAC_EVENT_TRIGGER { - u32 physical_efuse_map : 1; - u32 logical_efuse_map : 1; - u32 rsvd1 : 28; -} HALMAC_EVENT_TRIGGER, *PHALMAC_EVENT_TRIGGER; - -typedef struct _HALMAC_H2C_HEADER_INFO { - u16 sub_cmd_id; - u16 content_size; + u32 buf_size; + u32 avl_buf_size; + u32 total_size; + u32 ch_num; +}; + +struct halmac_event_trigger { + u32 phy_efuse_map : 1; + u32 log_efuse_map : 1; + u32 rsvd1 : 28; +}; + +struct halmac_h2c_header_info { + u16 sub_cmd_id; + u16 content_size; u8 ack; -} HALMAC_H2C_HEADER_INFO, *PHALMAC_H2C_HEADER_INFO; - -typedef enum _HALMAC_DLFW_STATE { - HALMAC_DLFW_NONE = 0, - HALMAC_DLFW_DONE = 1, - HALMAC_GEN_INFO_SENT = 2, - HALMAC_DLFW_UNDEFINED = 0x7F, -} HALMAC_DLFW_STATE; - -typedef enum _HALMAC_GPIO_CFG_STATE { - HALMAC_GPIO_CFG_STATE_IDLE = 0, - HALMAC_GPIO_CFG_STATE_BUSY = 1, - HALMAC_GPIO_CFG_STATE_UNDEFINED = 0x7F, -} HALMAC_GPIO_CFG_STATE; - -typedef enum _HALMAC_EFUSE_CMD_CONSTRUCT_STATE { - HALMAC_EFUSE_CMD_CONSTRUCT_IDLE = 0, - HALMAC_EFUSE_CMD_CONSTRUCT_BUSY = 1, - HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT = 2, - HALMAC_EFUSE_CMD_CONSTRUCT_STATE_NUM = 3, - HALMAC_EFUSE_CMD_CONSTRUCT_UNDEFINED = 0x7F, -} HALMAC_EFUSE_CMD_CONSTRUCT_STATE; - -typedef enum _HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE { - HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE = 0, - HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING = 1, - HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT = 2, - HALMAC_CFG_PARA_CMD_CONSTRUCT_NUM = 3, - HALMAC_CFG_PARA_CMD_CONSTRUCT_UNDEFINED = 0x7F, -} HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE; - -typedef enum _HALMAC_SCAN_CMD_CONSTRUCT_STATE { - HALMAC_SCAN_CMD_CONSTRUCT_IDLE = 0, - HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED = 1, - HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING = 2, - HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT = 3, - HALMAC_SCAN_CMD_CONSTRUCT_STATE_NUM = 4, - HALMAC_SCAN_CMD_CONSTRUCT_UNDEFINED = 0x7F, -} HALMAC_SCAN_CMD_CONSTRUCT_STATE; - -typedef enum _HALMAC_API_STATE { - HALMAC_API_STATE_INIT = 0, - HALMAC_API_STATE_HALT = 1, - HALMAC_API_STATE_UNDEFINED = 0x7F, -} HALMAC_API_STATE; - -typedef struct _HALMAC_EFUSE_STATE_SET { - HALMAC_EFUSE_CMD_CONSTRUCT_STATE efuse_cmd_construct_state; - HALMAC_CMD_PROCESS_STATUS process_status; - u8 fw_return_code; - u16 seq_num; -} HALMAC_EFUSE_STATE_SET, *PHALMAC_EFUSE_STATE_SET; - -typedef struct _HALMAC_CFG_PARA_STATE_SET { - HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE cfg_para_cmd_construct_state; - HALMAC_CMD_PROCESS_STATUS process_status; - u8 fw_return_code; - u16 seq_num; -} HALMAC_CFG_PARA_STATE_SET, *PHALMAC_CFG_PARA_STATE_SET; - -typedef struct _HALMAC_SCAN_STATE_SET { - HALMAC_SCAN_CMD_CONSTRUCT_STATE scan_cmd_construct_state; - HALMAC_CMD_PROCESS_STATUS process_status; - u8 fw_return_code; - u16 seq_num; -} HALMAC_SCAN_STATE_SET, *PHALMAC_SCAN_STATE_SET; - -typedef struct _HALMAC_UPDATE_PACKET_STATE_SET { - HALMAC_CMD_PROCESS_STATUS process_status; - u8 fw_return_code; - u16 seq_num; -} HALMAC_UPDATE_PACKET_STATE_SET, *PHALMAC_UPDATE_PACKET_STATE_SET; - -typedef struct _HALMAC_IQK_STATE_SET { - HALMAC_CMD_PROCESS_STATUS process_status; - u8 fw_return_code; - u16 seq_num; -} HALMAC_IQK_STATE_SET, *PHALMAC_IQK_STATE_SET; - -typedef struct _HALMAC_POWER_TRACKING_STATE_SET { - HALMAC_CMD_PROCESS_STATUS process_status; - u8 fw_return_code; - u16 seq_num; -} HALMAC_POWER_TRACKING_STATE_SET, *PHALMAC_POWER_TRACKING_STATE_SET; - -typedef struct _HALMAC_PSD_STATE_SET { - HALMAC_CMD_PROCESS_STATUS process_status; - u16 data_size; - u16 segment_size; - u8 *pData; - u8 fw_return_code; - u16 seq_num; -} HALMAC_PSD_STATE_SET, *PHALMAC_PSD_STATE_SET; - -typedef struct _HALMAC_STATE { - HALMAC_EFUSE_STATE_SET efuse_state_set; /* State machine + cmd process status */ - HALMAC_CFG_PARA_STATE_SET cfg_para_state_set; /* State machine + cmd process status */ - HALMAC_SCAN_STATE_SET scan_state_set; /* State machine + cmd process status */ - HALMAC_UPDATE_PACKET_STATE_SET update_packet_set; /* cmd process status */ - HALMAC_IQK_STATE_SET iqk_set; /* cmd process status */ - HALMAC_POWER_TRACKING_STATE_SET power_tracking_set; /* cmd process status */ - HALMAC_PSD_STATE_SET psd_set; /* cmd process status */ - HALMAC_API_STATE api_state; /* Halmac api state */ - HALMAC_MAC_POWER mac_power; /* 0 : power off, 1 : power on*/ - HALMAC_PS_STATE ps_state; /* power saving state */ - HALMAC_DLFW_STATE dlfw_state; /* download FW state */ - HALMAC_GPIO_CFG_STATE gpio_cfg_state; /* gpio state */ -} HALMAC_STATE, *PHALMAC_STATE; - -typedef struct _HALMAC_VER { +}; + +struct halmac_ver { u8 major_ver; u8 prototype_ver; u8 minor_ver; -} HALMAC_VER, *PHALMAC_VER; +}; - -typedef enum _HALMAC_API_ID { +enum halmac_api_id { /*stuff, need to be the 1st*/ HALMAC_API_STUFF = 0x0, /*stuff, need to be the 1st*/ @@ -1554,8 +1400,6 @@ typedef enum _HALMAC_API_ID { HALMAC_API_DEINIT_INTERFACE_CFG = 0x18, HALMAC_API_GET_EFUSE_SIZE = 0x19, HALMAC_API_DUMP_EFUSE_MAP = 0x1A, - HALMAC_API_WRITE_EFUSE = 0x1B, - HALMAC_API_READ_EFUSE = 0x1C, HALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D, HALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E, HALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F, @@ -1625,7 +1469,6 @@ typedef enum _HALMAC_API_ID { HALMAC_API_GET_HW_VALUE = 0x5F, HALMAC_API_SET_HW_VALUE = 0x60, HALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61, - HALMAC_API_SWITCH_EFUSE_BANK = 0x62, HALMAC_API_WRITE_EFUSE_BT = 0x63, HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64, HALMAC_API_DL_DRV_RSVD_PG = 0x65, @@ -1664,38 +1507,56 @@ typedef enum _HALMAC_API_ID { HALMAC_API_CFG_PINMUX_SDIO_INT_POLARITY = 0x88, HALMAC_API_CFG_PINMUX_GPIO_MODE = 0x89, HALMAC_API_CFG_PINMUX_GPIO_OUTPUT = 0x90, + HALMAC_API_REG_READ_INDIRECT_32 = 0x91, + HALMAC_API_REG_SDIO_CMD53_READ_N = 0x92, + HALMAC_API_PINMUX_PIN_STATUS = 0x94, + HALMAC_API_OFLD_FUNC_CFG = 0x95, + HALMAC_API_MASK_LOGICAL_EFUSE = 0x96, + HALMAC_API_RX_CUT_AMSDU_CFG = 0x97, + HALMAC_API_FW_SNDING = 0x98, + HALMAC_API_ENTER_CPU_SLEEP_MODE = 0x99, + HALMAC_API_GET_CPU_MODE = 0x9A, + HALMAC_API_DRV_FWCTRL = 0x9B, + HALMAC_API_EN_REF_AUTOK = 0x9C, HALMAC_API_MAX -} HALMAC_API_ID; +}; -typedef enum _HALMAC_LA_MODE { +enum halmac_la_mode { HALMAC_LA_MODE_DISABLE = 0, HALMAC_LA_MODE_PARTIAL = 1, HALMAC_LA_MODE_FULL = 2, HALMAC_LA_MODE_UNDEFINE = 0x7F, -} HALMAC_LA_MODE; +}; -typedef enum _HALMAC_RX_FIFO_EXPANDING_MODE { +enum halmac_rx_fifo_expanding_mode { HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE = 0, HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK = 1, HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK = 2, HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK = 3, + HALMAC_RX_FIFO_EXPANDING_MODE_4_BLOCK = 4, HALMAC_RX_FIFO_EXPANDING_MODE_UNDEFINE = 0x7F, -} HALMAC_RX_FIFO_EXPANDING_MODE; +}; -typedef enum _HALMAC_SDIO_CMD53_4BYTE_MODE { +enum halmac_sdio_cmd53_4byte_mode { HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE = 0, HALMAC_SDIO_CMD53_4BYTE_MODE_RW = 1, HALMAC_SDIO_CMD53_4BYTE_MODE_R = 2, HALMAC_SDIO_CMD53_4BYTE_MODE_W = 3, HALMAC_SDIO_CMD53_4BYTE_MODE_UNDEFINE = 0x7F, -} HALMAC_SDIO_CMD53_4BYTE_MODE; +}; -typedef enum _HALMAC_USB_MODE { +enum halmac_usb_mode { HALMAC_USB_MODE_U2 = 1, HALMAC_USB_MODE_U3 = 2, -} HALMAC_USB_MODE; +}; + +enum halmac_sdio_tx_format { + HALMAC_SDIO_AGG_MODE = 1, + HALMAC_SDIO_DUMMY_BLOCK_MODE = 2, + HALMAC_SDIO_DUMMY_AUTO_MODE = 3, +}; -typedef enum _HALMAC_HW_ID { +enum halmac_hw_id { /* Get HW value */ HALMAC_HW_RQPN_MAPPING = 0x00, HALMAC_HW_EFUSE_SIZE = 0x01, @@ -1704,22 +1565,32 @@ typedef enum _HALMAC_HW_ID { HALMAC_HW_BT_BANK1_EFUSE_SIZE = 0x04, HALMAC_HW_BT_BANK2_EFUSE_SIZE = 0x05, HALMAC_HW_TXFIFO_SIZE = 0x06, - HALMAC_HW_RSVD_PG_BNDY = 0x07, - HALMAC_HW_CAM_ENTRY_NUM = 0x08, - HALMAC_HW_IC_VERSION = 0x09, - HALMAC_HW_PAGE_SIZE = 0x0A, - HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0B, - HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0C, - HALMAC_HW_DRV_INFO_SIZE = 0x0D, - HALMAC_HW_TXFF_ALLOCATION = 0x0E, - HALMAC_HW_RSVD_EFUSE_SIZE = 0x0F, - HALMAC_HW_FW_HDR_SIZE = 0x10, - HALMAC_HW_TX_DESC_SIZE = 0x11, - HALMAC_HW_RX_DESC_SIZE = 0x12, - HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x13, - HALMAC_HW_AC_OQT_SIZE = 0x14, - HALMAC_HW_NON_AC_OQT_SIZE = 0x15, - HALMAC_HW_AC_QUEUE_NUM = 0x16, + HALMAC_HW_RXFIFO_SIZE = 0x07, + HALMAC_HW_RSVD_PG_BNDY = 0x08, + HALMAC_HW_CAM_ENTRY_NUM = 0x09, + HALMAC_HW_IC_VERSION = 0x0A, + HALMAC_HW_PAGE_SIZE = 0x0B, + HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0C, + HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0D, + HALMAC_HW_DRV_INFO_SIZE = 0x0E, + HALMAC_HW_TXFF_ALLOCATION = 0x0F, + HALMAC_HW_RSVD_EFUSE_SIZE = 0x10, + HALMAC_HW_FW_HDR_SIZE = 0x11, + HALMAC_HW_TX_DESC_SIZE = 0x12, + HALMAC_HW_RX_DESC_SIZE = 0x13, + HALMAC_HW_FW_MAX_SIZE = 0x14, + HALMAC_HW_ORI_H2C_SIZE = 0x15, + HALMAC_HW_RSVD_DRV_PGNUM = 0x16, + HALMAC_HW_TX_PAGE_SIZE = 0x17, + HALMAC_HW_USB_TXAGG_DESC_NUM = 0x18, + HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x19, + HALMAC_HW_HIOE_INST_START = 0x1A, + HALMAC_HW_HIOE_INST_END = 0x1B, + HALMAC_HW_AC_OQT_SIZE = 0x1C, + HALMAC_HW_NON_AC_OQT_SIZE = 0x1D, + HALMAC_HW_AC_QUEUE_NUM = 0x1E, + HALMAC_HW_RQPN_CH_MAPPING = 0x1F, + HALMAC_HW_PWR_STATE = 0x20, /* Set HW value */ HALMAC_HW_USB_MODE = 0x60, HALMAC_HW_SEQ_EN = 0x61, @@ -1730,25 +1601,33 @@ typedef enum _HALMAC_HW_ID { HALMAC_HW_SDIO_TX_PAGE_THRESHOLD = 0x66, HALMAC_HW_AMPDU_CONFIG = 0x67, HALMAC_HW_RX_SHIFT = 0x68, - + HALMAC_HW_TXDESC_CHECKSUM = 0x69, + HALMAC_HW_RX_CLK_GATE = 0x6A, + HALMAC_HW_RXGCK_FIFO = 0x6B, + HALMAC_HW_RX_IGNORE = 0x6C, + HALMAC_HW_SDIO_TX_FORMAT = 0x6D, + HALMAC_HW_FAST_EDCA = 0x6E, + HALMAC_HW_LDO25_EN = 0x6F, + HALMAC_HW_PCIE_REF_AUTOK = 0x70, HALMAC_HW_ID_UNDEFINE = 0x7F, -} HALMAC_HW_ID; -typedef enum _HALMAC_EFUSE_BANK { +}; + +enum halmac_efuse_bank { HALMAC_EFUSE_BANK_WIFI = 0, HALMAC_EFUSE_BANK_BT = 1, HALMAC_EFUSE_BANK_BT_1 = 2, HALMAC_EFUSE_BANK_BT_2 = 3, HALMAC_EFUSE_BANK_MAX, HALMAC_EFUSE_BANK_UNDEFINE = 0X7F, -} HALMAC_EFUSE_BANK; +}; -typedef enum _HALMAC_SDIO_SPEC_VER { +enum halmac_sdio_spec_ver { HALMAC_SDIO_SPEC_VER_2_00 = 0, HALMAC_SDIO_SPEC_VER_3_00 = 1, HALMAC_SDIO_SPEC_VER_UNDEFINE = 0X7F, -} HALMAC_SDIO_SPEC_VER; +}; -typedef enum _HALMAC_GPIO_FUNC { +enum halmac_gpio_func { HALMAC_GPIO_FUNC_WL_LED = 0, HALMAC_GPIO_FUNC_SDIO_INT = 1, HALMAC_GPIO_FUNC_SW_IO_0 = 2, @@ -1768,132 +1647,191 @@ typedef enum _HALMAC_GPIO_FUNC { HALMAC_GPIO_FUNC_SW_IO_14 = 16, HALMAC_GPIO_FUNC_SW_IO_15 = 17, HALMAC_GPIO_FUNC_UNDEFINE = 0X7F, -} HALMAC_GPIO_FUNC; +}; -typedef enum _HALMAC_WLLED_MODE { +enum halmac_wlled_mode { HALMAC_WLLED_MODE_TRX = 0, HALMAC_WLLED_MODE_TX = 1, HALMAC_WLLED_MODE_RX = 2, HALMAC_WLLED_MODE_SW_CTRL = 3, HALMAC_WLLED_MODE_UNDEFINE = 0X7F, -} HALMAC_WLLED_MODE; - -typedef struct _HALMAC_TXFF_ALLOCATION { +}; + +enum halmac_psf_fcs_chk_thr { + HALMAC_PSF_FCS_CHK_THR_1 = 0, + HALMAC_PSF_FCS_CHK_THR_4 = 1, + HALMAC_PSF_FCS_CHK_THR_8 = 2, + HALMAC_PSF_FCS_CHK_THR_12 = 3, + HALMAC_PSF_FCS_CHK_THR_16 = 4, + HALMAC_PSF_FCS_CHK_THR_20 = 5, + HALMAC_PSF_FCS_CHK_THR_24 = 6, + HALMAC_PSF_FCS_CHK_THR_28 = 7, +}; + +struct halmac_txff_allocation { u16 tx_fifo_pg_num; u16 rsvd_pg_num; u16 rsvd_drv_pg_num; - u16 ac_q_pg_num; + u16 acq_pg_num; u16 high_queue_pg_num; u16 low_queue_pg_num; u16 normal_queue_pg_num; u16 extra_queue_pg_num; u16 pub_queue_pg_num; - u16 rsvd_pg_bndy; - u16 rsvd_drv_pg_bndy; - u16 rsvd_h2c_extra_info_pg_bndy; - u16 rsvd_h2c_queue_pg_bndy; - u16 rsvd_cpu_instr_pg_bndy; - u16 rsvd_fw_txbuff_pg_bndy; - HALMAC_LA_MODE la_mode; - HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode; -} HALMAC_TXFF_ALLOCATION, *PHALMAC_TXFF_ALLOCATION; - -typedef struct _HALMAC_RQPN_MAP { - HALMAC_DMA_MAPPING dma_map_vo; - HALMAC_DMA_MAPPING dma_map_vi; - HALMAC_DMA_MAPPING dma_map_be; - HALMAC_DMA_MAPPING dma_map_bk; - HALMAC_DMA_MAPPING dma_map_mg; - HALMAC_DMA_MAPPING dma_map_hi; -} HALMAC_RQPN_MAP, *PHALMAC_RQPN_MAP; - -typedef struct _HALMAC_SECURITY_SETTING { + u16 rsvd_boundary; + u16 rsvd_drv_addr; + u16 rsvd_h2c_info_addr; + u16 rsvd_h2c_sta_info_addr; + u16 rsvd_h2cq_addr; + u16 rsvd_cpu_instr_addr; + u16 rsvd_fw_txbuf_addr; + u16 rsvd_csibuf_addr; + enum halmac_la_mode la_mode; + enum halmac_rx_fifo_expanding_mode rx_fifo_exp_mode; +}; + +struct halmac_rqpn_map { + enum halmac_dma_mapping dma_map_vo; + enum halmac_dma_mapping dma_map_vi; + enum halmac_dma_mapping dma_map_be; + enum halmac_dma_mapping dma_map_bk; + enum halmac_dma_mapping dma_map_mg; + enum halmac_dma_mapping dma_map_hi; +}; + +struct halmac_rqpn_ch_map { + enum halmac_dma_ch dma_map_vo; + enum halmac_dma_ch dma_map_vi; + enum halmac_dma_ch dma_map_be; + enum halmac_dma_ch dma_map_bk; + enum halmac_dma_ch dma_map_mg; + enum halmac_dma_ch dma_map_hi; +}; + +struct halmac_security_setting { u8 tx_encryption; u8 rx_decryption; u8 bip_enable; -} HALMAC_SECURITY_SETTING, *PHALMAC_SECURITY_SETTING; + u8 compare_keyid; +}; -typedef struct _HALMAC_CAM_ENTRY_INFO { - HAL_SECURITY_TYPE security_type; +struct halmac_cam_entry_info { + enum hal_security_type security_type; u32 key[4]; u32 key_ext[4]; u8 mac_address[6]; u8 unicast; u8 key_id; u8 valid; -} HALMAC_CAM_ENTRY_INFO, *PHALMAC_CAM_ENTRY_INFO; - -typedef struct _HALMAC_CAM_ENTRY_FORMAT { - u16 key_id : 2; - u16 type : 3; - u16 mic : 1; - u16 grp : 1; - u16 spp_mode : 1; - u16 rpt_md : 1; - u16 ext_sectype : 1; +}; + +struct halmac_cam_entry_format { + u16 key_id : 2; + u16 type : 3; + u16 mic : 1; + u16 grp : 1; + u16 spp_mode : 1; + u16 rpt_md : 1; + u16 ext_sectype : 1; u16 mgnt : 1; - u16 rsvd1 : 4; + u16 rsvd1 : 4; u16 valid : 1; u8 mac_address[6]; - u32 key[4]; - u32 rsvd[2]; -} HALMAC_CAM_ENTRY_FORMAT, *PHALMAC_CAM_ENTRY_FORMAT; + u32 key[4]; + u32 rsvd[2]; +}; -typedef struct _HALMAC_TX_PAGE_THRESHOLD_INFO { +struct halmac_tx_page_threshold_info { u32 threshold; - HALMAC_DMA_MAPPING dma_queue_sel; + enum halmac_dma_mapping dma_queue_sel; u8 enable; -} HALMAC_TX_PAGE_THRESHOLD_INFO, *PHALMAC_TX_PAGE_THRESHOLD_INFO; +}; -typedef struct _HALMAC_AMPDU_CONFIG { +struct halmac_ampdu_config { u8 max_agg_num; -} HALMAC_AMPDU_CONFIG, *PHALMAC_AMPDU_CONFIG; - -typedef struct _HALMAC_RQPN_ { - HALMAC_TRX_MODE mode; - HALMAC_DMA_MAPPING dma_map_vo; - HALMAC_DMA_MAPPING dma_map_vi; - HALMAC_DMA_MAPPING dma_map_be; - HALMAC_DMA_MAPPING dma_map_bk; - HALMAC_DMA_MAPPING dma_map_mg; - HALMAC_DMA_MAPPING dma_map_hi; -} HALMAC_RQPN, *PHALMAC_RQPN; - -typedef struct _HALMAC_PG_NUM_ { - HALMAC_TRX_MODE mode; - u16 hq_num; + u8 max_len_en; + u32 ht_max_len; + u32 vht_max_len; +}; + +struct halmac_rqpn { + enum halmac_trx_mode mode; + enum halmac_dma_mapping dma_map_vo; + enum halmac_dma_mapping dma_map_vi; + enum halmac_dma_mapping dma_map_be; + enum halmac_dma_mapping dma_map_bk; + enum halmac_dma_mapping dma_map_mg; + enum halmac_dma_mapping dma_map_hi; +}; + +struct halmac_ch_mapping { + enum halmac_trx_mode mode; + enum halmac_dma_ch dma_map_vo; + enum halmac_dma_ch dma_map_vi; + enum halmac_dma_ch dma_map_be; + enum halmac_dma_ch dma_map_bk; + enum halmac_dma_ch dma_map_mg; + enum halmac_dma_ch dma_map_hi; +}; + +struct halmac_pg_num { + enum halmac_trx_mode mode; + u16 hq_num; u16 nq_num; u16 lq_num; u16 exq_num; u16 gap_num;/*used for loopback mode*/ -} HALMAC_PG_NUM, *PHALMAC_PG_NUM; +}; + +struct halmac_ch_pg_num { + enum halmac_trx_mode mode; + u16 ch_num[HALMAC_TXDESC_DMA_CH16 + 1]; + u16 gap_num; +}; -typedef struct _HALMAC_INTF_PHY_PARA_ { +struct halmac_intf_phy_para { u16 offset; u16 value; u16 ip_sel; u16 cut; u16 plaform; -} HALMAC_INTF_PHY_PARA, *PHALMAC_INTF_PHY_PARA; +}; -typedef struct _HALMAC_IQK_PARA_ { +struct halmac_iqk_para { u8 clear; u8 segment_iqk; -} HALMAC_IQK_PARA, *PHALMAC_IQK_PARA; +}; -typedef struct _HALMAC_SDIO_HW_INFO { - HALMAC_SDIO_SPEC_VER spec_ver; +struct halmac_txdesc_ie_param { + u8 *start_offset; + u8 *end_offset; + u8 *ie_offset; + u8 *ie_exist; +}; + +struct halmac_sdio_hw_info { + enum halmac_sdio_spec_ver spec_ver; u32 clock_speed; u8 io_hi_speed_flag; /* Halmac internal use */ -} HALMAC_SDIO_HW_INFO, *PHALMAC_SDIO_HW_INFO; + enum halmac_sdio_tx_format tx_addr_format; + u16 block_size; + u8 tx_seq; + u8 io_indir_flag; /* Halmac internal use */ +}; -typedef struct _HALMAC_EDCA_PARA { +struct halmac_edca_para { u8 aifs; u8 cw; u16 txop_limit; -} HALMAC_EDCA_PARA, *PHALMAC_EDCA_PARA; +}; + +struct halmac_mac_rx_ignore_cfg { + u8 hdr_chk_en; + u8 fcs_chk_en; + enum halmac_psf_fcs_chk_thr fcs_chk_thr; +}; -typedef struct _HALMAC_PINMUX_INFO { +struct halmac_pinmux_info { /* byte0 */ u8 wl_led:1; u8 sdio_int:1; @@ -1916,265 +1854,499 @@ typedef struct _HALMAC_PINMUX_INFO { u8 sw_io_13:1; u8 sw_io_14:1; u8 sw_io_15:1; -} HALMAC_PINMUX_INFO, *PHALMAC_PINMUX_INFO; - -/* Hal mac adapter */ -typedef struct _HALMAC_ADAPTER { - HALMAC_DMA_MAPPING halmac_ptcl_queue[HALMAC_PTCL_QUEUE_NUM]; /* Dma mapping of protocol queues */ - HALMAC_WLAN_ADDR pHal_mac_addr[HALMAC_PORTIDMAX]; /* mac address information, suppot 2 ports */ - HALMAC_WLAN_ADDR pHal_bss_addr[HALMAC_PORTIDMAX]; /* bss address information, suppot 2 ports */ - HALMAC_MUTEX h2c_seq_mutex; /* Protect h2c_packet_seq packet*/ - HALMAC_MUTEX EfuseMutex; /* Protect Efuse map memory of halmac_adapter */ - HALMAC_CONFIG_PARA_INFO config_para_info; - HALMAC_CS_INFO ch_sw_info; - HALMAC_EVENT_TRIGGER event_trigger; - HALMAC_HW_CONFIG_INFO hw_config_info; /* HW related information */ - HALMAC_SDIO_FREE_SPACE sdio_free_space; - HALMAC_SND_INFO snd_info; - HALMAC_PINMUX_INFO pinmux_info; - VOID *pHalAdapter_backup; /* Backup HalAdapter address */ - VOID *pDriver_adapter; /* Driver or FW adapter address. Do not write this memory*/ - u8 *pHalEfuse_map; - VOID *pHalmac_api; /* Record function pointer of halmac api */ - PHALMAC_PLATFORM_API pHalmac_platform_api; /* Record function pointer of platform api */ - u32 efuse_end; /* Record efuse used memory */ - u32 h2c_buf_free_space; - u32 h2c_buff_size; - u32 max_download_size; - HALMAC_CHIP_ID chip_id; /* Chip ID, 8822B, 8821C... */ - HALMAC_CHIP_VER chip_version; /* A cut, B cut... */ - HALMAC_FW_VERSION fw_version; - HALMAC_STATE halmac_state; - HALMAC_INTERFACE halmac_interface; /* Interface information, get from driver */ - HALMAC_TRX_MODE trx_mode; /* Noraml, WMM, P2P, LoopBack... */ - HALMAC_TXFF_ALLOCATION txff_allocation; - u8 h2c_packet_seq; /* current h2c packet sequence number */ - u16 ack_h2c_packet_seq; /*the acked h2c packet sequence number */ - u8 hal_efuse_map_valid; - u8 efuse_segment_size; - u8 rpwm_record; /* record rpwm value */ - u8 low_clk; /*LPS 32K or IPS 32K*/ - u8 halmac_bulkout_num; /* USB bulkout num */ - u8 gen_info_valid; - HALMAC_GENERAL_INFO general_info; +}; + +struct halmac_ofld_func_info { + u32 halmac_malloc_max_sz; + u32 rsvd_pg_drv_buf_max_sz; +}; + +struct halmac_pltfm_cfg_info { + u32 malloc_size; + u32 rsvd_pg_size; +}; + +struct halmac_su_snding_info { + u8 su0_en; + u8 *su0_ndpa_pkt; + u32 su0_pkt_sz; +}; + +struct halmac_mu_snding_info { + u8 tmp; +}; + +struct halmac_h2c_info { + u32 buf_fs; + u32 buf_size; + u8 seq_num; +}; + +struct halmac_adapter { + enum halmac_dma_mapping pq_map[HALMAC_PQ_MAP_NUM]; + enum halmac_dma_ch ch_map[HALMAC_PQ_MAP_NUM]; + HALMAC_MUTEX h2c_seq_mutex; + HALMAC_MUTEX efuse_mutex; + HALMAC_MUTEX sdio_indir_mutex; /*Protect sdio indirect access */ + struct halmac_cfg_param_info cfg_param_info; + struct halmac_ch_sw_info ch_sw_info; + struct halmac_event_trigger evnt; + struct halmac_hw_cfg_info hw_cfg_info; + struct halmac_sdio_free_space sdio_fs; + struct halmac_api_registry api_registry; + struct halmac_pinmux_info pinmux_info; + struct halmac_pltfm_cfg_info pltfm_info; + struct halmac_h2c_info h2c_info; + void *drv_adapter; + u8 *efuse_map; + void *halmac_api; + struct halmac_platform_api *pltfm_api; + u32 efuse_end; + u32 dlfw_pkt_size; + enum halmac_chip_id chip_id; + enum halmac_chip_ver chip_ver; + struct halmac_fw_version fw_ver; + struct halmac_state halmac_state; + enum halmac_interface intf; + enum halmac_trx_mode trx_mode; + struct halmac_txff_allocation txff_alloc; + u8 efuse_map_valid; + u8 efuse_seg_size; + u8 rpwm; + u8 bulkout_num; u8 drv_info_size; - HALMAC_SDIO_CMD53_4BYTE_MODE sdio_cmd53_4byte; - HALMAC_SDIO_HW_INFO sdio_hw_info; + enum halmac_sdio_cmd53_4byte_mode sdio_cmd53_4byte; + struct halmac_sdio_hw_info sdio_hw_info; + u8 tx_desc_transfer; + u8 tx_desc_checksum; u8 efuse_auto_check_en; + u8 pcie_refautok_en; + u8 pwr_off_flow_flag; + #if HALMAC_PLATFORM_TESTPROGRAM - HALMAC_TXAGG_BUFF_INFO halmac_tx_buf_info[4]; - HALMAC_MUTEX agg_buff_mutex; /*used for tx_agg_buffer */ - u8 max_agg_num; - u8 send_bcn_reg_cr_backup; + struct halmisc_adapter *halmisc_adapter; #endif -} HALMAC_ADAPTER, *PHALMAC_ADAPTER; - - -/* Function pointer of Hal mac API */ -typedef struct _HALMAC_API { - HALMAC_RET_STATUS (*halmac_mac_power_switch)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_MAC_POWER halmac_power); - HALMAC_RET_STATUS (*halmac_download_firmware)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size); - HALMAC_RET_STATUS (*halmac_free_download_firmware)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DLFW_MEM dlfw_mem, u8 *pHamacl_fw, u32 halmac_fw_size); - HALMAC_RET_STATUS (*halmac_get_fw_version)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FW_VERSION pFw_version); - HALMAC_RET_STATUS (*halmac_cfg_mac_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address); - HALMAC_RET_STATUS (*halmac_cfg_bssid)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address); - HALMAC_RET_STATUS (*halmac_cfg_multicast_addr)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_WLAN_ADDR pHal_address); - HALMAC_RET_STATUS (*halmac_pre_init_system_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_init_system_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_init_trx_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_TRX_MODE Mode); - HALMAC_RET_STATUS (*halmac_init_h2c)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_cfg_rx_aggregation)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_RXAGG_CFG phalmac_rxagg_cfg); - HALMAC_RET_STATUS (*halmac_init_protocol_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_init_edca_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_cfg_operation_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_WIRELESS_MODE wireless_mode); - HALMAC_RET_STATUS (*halmac_cfg_ch_bw)(PHALMAC_ADAPTER pHalmac_adapter, u8 channel, HALMAC_PRI_CH_IDX pri_ch_idx, HALMAC_BW bw); - HALMAC_RET_STATUS (*halmac_cfg_bw)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_BW bw); - HALMAC_RET_STATUS (*halmac_init_wmac_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_init_mac_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_TRX_MODE Mode); - HALMAC_RET_STATUS (*halmac_init_sdio_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_init_usb_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_init_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_init_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_deinit_sdio_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_deinit_usb_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_deinit_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_deinit_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_get_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size); - HALMAC_RET_STATUS (*halmac_get_efuse_available_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size); - HALMAC_RET_STATUS (*halmac_dump_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg); - HALMAC_RET_STATUS (*halmac_dump_efuse_map_bt)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank, u32 bt_efuse_map_size, u8 *pBT_efuse_map); - HALMAC_RET_STATUS (*halmac_write_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value); - HALMAC_RET_STATUS (*halmac_read_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue); - HALMAC_RET_STATUS (*halmac_switch_efuse_bank)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank); - HALMAC_RET_STATUS (*halmac_write_efuse_bt)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value, HALMAC_EFUSE_BANK halmac_efues_bank); - HALMAC_RET_STATUS (*halmac_read_efuse_bt)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue, HALMAC_EFUSE_BANK halmac_efues_bank); - HALMAC_RET_STATUS (*halmac_cfg_efuse_auto_check)(PHALMAC_ADAPTER pHalmac_adapter, u8 enable); - HALMAC_RET_STATUS (*halmac_get_logical_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size); - HALMAC_RET_STATUS (*halmac_dump_logical_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg); - HALMAC_RET_STATUS (*halmac_write_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value); - HALMAC_RET_STATUS (*halmac_read_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue); - HALMAC_RET_STATUS (*halmac_pg_efuse_by_map)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PG_EFUSE_INFO pPg_efuse_info, HALMAC_EFUSE_READ_CFG cfg); - HALMAC_RET_STATUS (*halmac_get_c2h_info)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size); - HALMAC_RET_STATUS (*halmac_h2c_lb)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_debug)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_cfg_parameter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PHY_PARAMETER_INFO para_info, u8 full_fifo); - HALMAC_RET_STATUS (*halmac_update_packet)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PACKET_ID pkt_id, u8 *pkt, u32 pkt_size); - HALMAC_RET_STATUS (*halmac_bcn_ie_filter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_BCN_IE_INFO pBcn_ie_info); - u8 (*halmac_reg_read_8)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); - HALMAC_RET_STATUS (*halmac_reg_write_8)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_data); - u16 (*halmac_reg_read_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); - HALMAC_RET_STATUS (*halmac_reg_write_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u16 halmac_data); - u32 (*halmac_reg_read_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); - u32 (*halmac_reg_read_indirect_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); - u8 (*halmac_reg_sdio_cmd53_read_n)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_size, u8 *halmac_data); - HALMAC_RET_STATUS (*halmac_reg_write_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_data); - HALMAC_RET_STATUS (*halmac_tx_allowed_sdio)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size); - HALMAC_RET_STATUS (*halmac_set_bulkout_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 bulkout_num); - HALMAC_RET_STATUS (*halmac_get_sdio_tx_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size, u32 *pcmd53_addr); - HALMAC_RET_STATUS (*halmac_get_usb_bulkout_id)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size, u8 *bulkout_id); - HALMAC_RET_STATUS (*halmac_timer_2s)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_fill_txdesc_checksum)(PHALMAC_ADAPTER pHalmac_adapter, u8 *cur_desc); - HALMAC_RET_STATUS (*halmac_update_datapack)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DATA_TYPE halmac_data_type, PHALMAC_PHY_PARAMETER_INFO para_info); - HALMAC_RET_STATUS (*halmac_run_datapack)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DATA_TYPE halmac_data_type); - HALMAC_RET_STATUS (*halmac_cfg_drv_info)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_INFO halmac_drv_info); - HALMAC_RET_STATUS (*halmac_send_bt_coex)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBt_buf, u32 bt_size, u8 ack); - HALMAC_RET_STATUS (*halmac_verify_platform_api)(PHALMAC_ADAPTER pHalmac_adapte); - u32 (*halmac_get_fifo_size)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel); - HALMAC_RET_STATUS (*halmac_dump_fifo)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel, u32 halmac_start_addr, u32 halmac_fifo_dump_size, u8 *pFifo_map); - HALMAC_RET_STATUS (*halmac_cfg_txbf)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, HALMAC_BW bw, u8 txbf_en); - HALMAC_RET_STATUS (*halmac_cfg_mumimo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CFG_MUMIMO_PARA pCfgmu); - HALMAC_RET_STATUS (*halmac_cfg_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role, HALMAC_DATA_RATE datarate); - HALMAC_RET_STATUS (*halmac_del_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role); - HALMAC_RET_STATUS (*halmac_su_bfer_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init); - HALMAC_RET_STATUS (*halmac_su_bfee_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, u16 paid); - HALMAC_RET_STATUS (*halmac_mu_bfer_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init); - HALMAC_RET_STATUS (*halmac_mu_bfee_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init); - HALMAC_RET_STATUS (*halmac_su_bfer_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid); - HALMAC_RET_STATUS (*halmac_su_bfee_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid); - HALMAC_RET_STATUS (*halmac_mu_bfer_entry_del)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_mu_bfee_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid); - HALMAC_RET_STATUS (*halmac_add_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_INFO pCh_info); - HALMAC_RET_STATUS (*halmac_add_extra_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_EXTRA_INFO pCh_extra_info); - HALMAC_RET_STATUS (*halmac_ctrl_ch_switch)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_SWITCH_OPTION pCs_option); - HALMAC_RET_STATUS (*halmac_p2pps)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_P2PPS pP2PPS); - HALMAC_RET_STATUS (*halmac_clear_ch_info)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_send_general_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_GENERAL_INFO pgGeneral_info); - HALMAC_RET_STATUS (*halmac_start_iqk)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_IQK_PARA pIqk_para); - HALMAC_RET_STATUS (*halmac_ctrl_pwr_tracking)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt); - HALMAC_RET_STATUS (*halmac_psd)(PHALMAC_ADAPTER pHalmac_adapter, u16 start_psd, u16 end_psd); - HALMAC_RET_STATUS (*halmac_cfg_tx_agg_align)(PHALMAC_ADAPTER pHalmac_adapter, u8 enable, u16 align_size); - HALMAC_RET_STATUS (*halmac_query_status)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS *pProcess_status, u8 *data, u32 *size); - HALMAC_RET_STATUS (*halmac_reset_feature)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_FEATURE_ID feature_id); - HALMAC_RET_STATUS (*halmac_check_fw_status)(PHALMAC_ADAPTER pHalmac_adapter, u8 *fw_status); - HALMAC_RET_STATUS (*halmac_dump_fw_dmem)(PHALMAC_ADAPTER pHalmac_adapter, u8 *dmem, u32 *size); - HALMAC_RET_STATUS (*halmac_cfg_max_dl_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 size); - HALMAC_RET_STATUS (*halmac_cfg_la_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_LA_MODE la_mode); - HALMAC_RET_STATUS (*halmac_cfg_rx_fifo_expanding_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode); - HALMAC_RET_STATUS (*halmac_config_security)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SECURITY_SETTING pSec_setting); - u8 (*halmac_get_used_cam_entry_num)(PHALMAC_ADAPTER pHalmac_adapter, HAL_SECURITY_TYPE sec_type); - HALMAC_RET_STATUS (*halmac_write_cam)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_INFO pCam_entry_info); - HALMAC_RET_STATUS (*halmac_read_cam_entry)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_FORMAT pContent); - HALMAC_RET_STATUS (*halmac_clear_cam_entry)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index); - HALMAC_RET_STATUS (*halmac_get_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue); - HALMAC_RET_STATUS (*halmac_set_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue); - HALMAC_RET_STATUS (*halmac_cfg_drv_rsvd_pg_num)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_RSVD_PG_NUM pg_num); - HALMAC_RET_STATUS (*halmac_get_chip_version)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_VER version); - HALMAC_RET_STATUS (*halmac_chk_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size); - HALMAC_RET_STATUS (*halmac_dl_drv_rsvd_page)(PHALMAC_ADAPTER pHalmac_adapter, u8 pg_offset, u8 *pHal_buf, u32 size); - HALMAC_RET_STATUS (*halmac_pcie_switch)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PCIE_CFG pcie_cfg); - HALMAC_RET_STATUS (*halmac_phy_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_INTF_PHY_PLATFORM platform); - HALMAC_RET_STATUS (*halmac_cfg_csi_rate)(PHALMAC_ADAPTER pHalmac_adapter, u8 rssi, u8 current_rate, u8 fixrate_en, u8 *new_rate); - HALMAC_RET_STATUS (*halmac_sdio_cmd53_4byte)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SDIO_CMD53_4BYTE_MODE cmd53_4byte_mode); - HALMAC_RET_STATUS (*halmac_sdio_hw_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SDIO_HW_INFO pSdio_hw_info); - HALMAC_RET_STATUS (*halmac_interface_integration_tuning)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_txfifo_is_empty)(PHALMAC_ADAPTER pHalmac_adapter, u32 chk_num); - HALMAC_RET_STATUS (*halmac_download_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address); - HALMAC_RET_STATUS (*halmac_read_flash)(PHALMAC_ADAPTER pHalmac_adapter, u32 addr); - HALMAC_RET_STATUS (*halmac_erase_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 erase_cmd, u32 addr); - HALMAC_RET_STATUS (*halmac_check_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_fw, u32 halmac_fw_size, u32 addr); - HALMAC_RET_STATUS (*halmac_cfg_edca_para)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_ACQ_ID acq_id, PHALMAC_EDCA_PARA pEdca_para); - HALMAC_RET_STATUS (*halmac_pinmux_get_func)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_GPIO_FUNC gpio_func, u8 *pEnable); - HALMAC_RET_STATUS (*halmac_pinmux_set_func)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_GPIO_FUNC gpio_func); - HALMAC_RET_STATUS (*halmac_pinmux_free_func)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_GPIO_FUNC gpio_func); - HALMAC_RET_STATUS (*halmac_pinmux_wl_led_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_WLLED_MODE wlled_mode); - VOID (*halmac_pinmux_wl_led_sw_ctrl)(PHALMAC_ADAPTER pHalmac_adapter, u8 led_on); - VOID (*halmac_pinmux_sdio_int_polarity)(PHALMAC_ADAPTER pHalmac_adapter, u8 low_active); - HALMAC_RET_STATUS (*halmac_pinmux_gpio_mode)(PHALMAC_ADAPTER pHalmac_adapter, u8 gpio_id, u8 output); - HALMAC_RET_STATUS (*halmac_pinmux_gpio_output)(PHALMAC_ADAPTER pHalmac_adapter, u8 gpio_id, u8 high); - HALMAC_RET_STATUS (*halmac_pinmux_pin_status)(PHALMAC_ADAPTER pHalmac_adapter, u8 gpio_id, u8 *pHigh); +}; + +struct halmac_api { + enum halmac_ret_status + (*halmac_register_api)(struct halmac_adapter *adapter, + struct halmac_api_registry *registry); + enum halmac_ret_status + (*halmac_mac_power_switch)(struct halmac_adapter *adapter, + enum halmac_mac_power pwr); + enum halmac_ret_status + (*halmac_download_firmware)(struct halmac_adapter *adapter, u8 *fw_bin, + u32 size); + enum halmac_ret_status + (*halmac_free_download_firmware)(struct halmac_adapter *adapter, + enum halmac_dlfw_mem mem_sel, + u8 *fw_bin, u32 size); + enum halmac_ret_status + (*halmac_get_fw_version)(struct halmac_adapter *adapter, + struct halmac_fw_version *ver); + enum halmac_ret_status + (*halmac_cfg_mac_addr)(struct halmac_adapter *adapter, + u8 port, union halmac_wlan_addr *addr); + enum halmac_ret_status + (*halmac_cfg_bssid)(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + enum halmac_ret_status + (*halmac_cfg_multicast_addr)(struct halmac_adapter *adapter, + union halmac_wlan_addr *addr); + enum halmac_ret_status + (*halmac_pre_init_system_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_system_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_trx_cfg)(struct halmac_adapter *adapter, + enum halmac_trx_mode mode); + enum halmac_ret_status + (*halmac_init_h2c)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_cfg_rx_aggregation)(struct halmac_adapter *adapter, + struct halmac_rxagg_cfg *cfg); + enum halmac_ret_status + (*halmac_init_protocol_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_edca_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_cfg_operation_mode)(struct halmac_adapter *adapter, + enum halmac_wireless_mode mode); + enum halmac_ret_status + (*halmac_cfg_ch_bw)(struct halmac_adapter *adapter, u8 ch, + enum halmac_pri_ch_idx idx, enum halmac_bw bw); + enum halmac_ret_status + (*halmac_cfg_bw)(struct halmac_adapter *adapter, enum halmac_bw bw); + enum halmac_ret_status + (*halmac_init_wmac_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_mac_cfg)(struct halmac_adapter *adapter, + enum halmac_trx_mode mode); + enum halmac_ret_status + (*halmac_init_interface_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_deinit_interface_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_sdio_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_usb_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_pcie_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_deinit_sdio_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_deinit_usb_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_deinit_pcie_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_get_efuse_size)(struct halmac_adapter *adapter, u32 *size); + enum halmac_ret_status + (*halmac_get_efuse_available_size)(struct halmac_adapter *adapter, + u32 *size); + enum halmac_ret_status + (*halmac_dump_efuse_map)(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg); + enum halmac_ret_status + (*halmac_dump_efuse_map_bt)(struct halmac_adapter *adapter, + enum halmac_efuse_bank bank, u32 size, + u8 *map); + enum halmac_ret_status + (*halmac_write_efuse_bt)(struct halmac_adapter *adapter, u32 offset, + u8 value, enum halmac_efuse_bank bank); + enum halmac_ret_status + (*halmac_read_efuse_bt)(struct halmac_adapter *adapter, u32 offset, + u8 *value, enum halmac_efuse_bank bank); + enum halmac_ret_status + (*halmac_cfg_efuse_auto_check)(struct halmac_adapter *adapter, + u8 enable); + enum halmac_ret_status + (*halmac_get_logical_efuse_size)(struct halmac_adapter *adapter, + u32 *size); + enum halmac_ret_status + (*halmac_dump_logical_efuse_map)(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg); + enum halmac_ret_status + (*halmac_write_logical_efuse)(struct halmac_adapter *adapter, + u32 offset, u8 value); + enum halmac_ret_status + (*halmac_read_logical_efuse)(struct halmac_adapter *adapter, u32 offset, + u8 *value); + enum halmac_ret_status + (*halmac_pg_efuse_by_map)(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, + enum halmac_efuse_read_cfg cfg); + enum halmac_ret_status + (*halmac_mask_logical_efuse)(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info); + enum halmac_ret_status + (*halmac_get_c2h_info)(struct halmac_adapter *adapter, u8 *buf, + u32 size); + enum halmac_ret_status + (*halmac_h2c_lb)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_debug)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_cfg_parameter)(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *info, + u8 full_fifo); + enum halmac_ret_status + (*halmac_update_packet)(struct halmac_adapter *adapter, + enum halmac_packet_id pkt_id, u8 *pkt, + u32 size); + enum halmac_ret_status + (*halmac_bcn_ie_filter)(struct halmac_adapter *adapter, + struct halmac_bcn_ie_info *info); + u8 + (*halmac_reg_read_8)(struct halmac_adapter *adapter, u32 offset); + enum halmac_ret_status + (*halmac_reg_write_8)(struct halmac_adapter *adapter, u32 offset, + u8 value); + u16 + (*halmac_reg_read_16)(struct halmac_adapter *adapter, u32 offset); + enum halmac_ret_status + (*halmac_reg_write_16)(struct halmac_adapter *adapter, u32 offset, + u16 value); + u32 + (*halmac_reg_read_32)(struct halmac_adapter *adapter, u32 offset); + enum halmac_ret_status + (*halmac_reg_write_32)(struct halmac_adapter *adapter, u32 offset, + u32 value); + u32 + (*halmac_reg_read_indirect_32)(struct halmac_adapter *adapter, + u32 offset); + enum halmac_ret_status + (*halmac_reg_sdio_cmd53_read_n)(struct halmac_adapter *adapter, + u32 offset, u32 size, u8 *value); + enum halmac_ret_status + (*halmac_tx_allowed_sdio)(struct halmac_adapter *adapter, u8 *buf, + u32 size); + enum halmac_ret_status + (*halmac_set_bulkout_num)(struct halmac_adapter *adapter, u8 num); + enum halmac_ret_status + (*halmac_get_sdio_tx_addr)(struct halmac_adapter *adapter, u8 *buf, + u32 size, u32 *cmd53_addr); + enum halmac_ret_status + (*halmac_get_usb_bulkout_id)(struct halmac_adapter *adapter, u8 *buf, + u32 size, u8 *id); + enum halmac_ret_status + (*halmac_fill_txdesc_checksum)(struct halmac_adapter *adapter, + u8 *txdesc); + enum halmac_ret_status + (*halmac_update_datapack)(struct halmac_adapter *adapter, + enum halmac_data_type data_type, + struct halmac_phy_parameter_info *info); + enum halmac_ret_status + (*halmac_run_datapack)(struct halmac_adapter *adapter, + enum halmac_data_type data_type); + enum halmac_ret_status + (*halmac_cfg_drv_info)(struct halmac_adapter *adapter, + enum halmac_drv_info drv_info); + enum halmac_ret_status + (*halmac_send_bt_coex)(struct halmac_adapter *adapter, u8 *buf, + u32 size, u8 ack); + enum halmac_ret_status + (*halmac_verify_platform_api)(struct halmac_adapter *adapter); + u32 + (*halmac_get_fifo_size)(struct halmac_adapter *adapter, + enum hal_fifo_sel sel); + enum halmac_ret_status + (*halmac_dump_fifo)(struct halmac_adapter *adapter, + enum hal_fifo_sel sel, u32 start_addr, u32 size, + u8 *data); + enum halmac_ret_status + (*halmac_cfg_txbf)(struct halmac_adapter *adapter, u8 userid, + enum halmac_bw bw, u8 txbf_en); + enum halmac_ret_status + (*halmac_cfg_mumimo)(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param); + enum halmac_ret_status + (*halmac_cfg_sounding)(struct halmac_adapter *adapter, + enum halmac_snd_role role, + enum halmac_data_rate rate); + enum halmac_ret_status + (*halmac_del_sounding)(struct halmac_adapter *adapter, + enum halmac_snd_role role); + enum halmac_ret_status + (*halmac_su_bfer_entry_init)(struct halmac_adapter *adapter, + struct halmac_su_bfer_init_para *param); + enum halmac_ret_status + (*halmac_su_bfee_entry_init)(struct halmac_adapter *adapter, u8 userid, + u16 paid); + enum halmac_ret_status + (*halmac_mu_bfer_entry_init)(struct halmac_adapter *adapter, + struct halmac_mu_bfer_init_para *param); + enum halmac_ret_status + (*halmac_mu_bfee_entry_init)(struct halmac_adapter *adapter, + struct halmac_mu_bfee_init_para *param); + enum halmac_ret_status + (*halmac_su_bfer_entry_del)(struct halmac_adapter *adapter, u8 userid); + enum halmac_ret_status + (*halmac_su_bfee_entry_del)(struct halmac_adapter *adapter, u8 userid); + enum halmac_ret_status + (*halmac_mu_bfer_entry_del)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_mu_bfee_entry_del)(struct halmac_adapter *adapter, u8 userid); + enum halmac_ret_status + (*halmac_add_ch_info)(struct halmac_adapter *adapter, + struct halmac_ch_info *info); + enum halmac_ret_status + (*halmac_add_extra_ch_info)(struct halmac_adapter *adapter, + struct halmac_ch_extra_info *info); + enum halmac_ret_status + (*halmac_ctrl_ch_switch)(struct halmac_adapter *adapter, + struct halmac_ch_switch_option *opt); + enum halmac_ret_status + (*halmac_p2pps)(struct halmac_adapter *adapter, + struct halmac_p2pps *info); + enum halmac_ret_status + (*halmac_clear_ch_info)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_send_general_info)(struct halmac_adapter *adapter, + struct halmac_general_info *info); + enum halmac_ret_status + (*halmac_start_iqk)(struct halmac_adapter *adapter, + struct halmac_iqk_para *param); + enum halmac_ret_status + (*halmac_ctrl_pwr_tracking)(struct halmac_adapter *adapter, + struct halmac_pwr_tracking_option *opt); + enum halmac_ret_status + (*halmac_psd)(struct halmac_adapter *adapter, u16 start_psd, + u16 end_psd); + enum halmac_ret_status + (*halmac_cfg_tx_agg_align)(struct halmac_adapter *adapter, u8 enable, + u16 align_size); + enum halmac_ret_status + (*halmac_query_status)(struct halmac_adapter *adapter, + enum halmac_feature_id feature_id, + enum halmac_cmd_process_status *proc_status, + u8 *data, u32 *size); + enum halmac_ret_status + (*halmac_reset_feature)(struct halmac_adapter *adapter, + enum halmac_feature_id feature_id); + enum halmac_ret_status + (*halmac_check_fw_status)(struct halmac_adapter *adapter, + u8 *fw_status); + enum halmac_ret_status + (*halmac_dump_fw_dmem)(struct halmac_adapter *adapter, u8 *dmem, + u32 *size); + enum halmac_ret_status + (*halmac_cfg_max_dl_size)(struct halmac_adapter *adapter, u32 size); + enum halmac_ret_status + (*halmac_cfg_la_mode)(struct halmac_adapter *adapter, + enum halmac_la_mode mode); + enum halmac_ret_status + (*halmac_cfg_rxff_expand_mode)(struct halmac_adapter *adapter, + enum halmac_rx_fifo_expanding_mode mode); + enum halmac_ret_status + (*halmac_config_security)(struct halmac_adapter *adapter, + struct halmac_security_setting *setting); + u8 + (*halmac_get_used_cam_entry_num)(struct halmac_adapter *adapter, + enum hal_security_type sec_type); + enum halmac_ret_status + (*halmac_write_cam)(struct halmac_adapter *adapter, u32 idx, + struct halmac_cam_entry_info *info); + enum halmac_ret_status + (*halmac_read_cam_entry)(struct halmac_adapter *adapter, u32 idx, + struct halmac_cam_entry_format *content); + enum halmac_ret_status + (*halmac_clear_cam_entry)(struct halmac_adapter *adapter, u32 idx); + enum halmac_ret_status + (*halmac_get_hw_value)(struct halmac_adapter *adapter, + enum halmac_hw_id hw_id, void *value); + enum halmac_ret_status + (*halmac_set_hw_value)(struct halmac_adapter *adapter, + enum halmac_hw_id hw_id, void *value); + enum halmac_ret_status + (*halmac_cfg_drv_rsvd_pg_num)(struct halmac_adapter *adapter, + enum halmac_drv_rsvd_pg_num pg_num); + enum halmac_ret_status + (*halmac_get_chip_version)(struct halmac_adapter *adapter, + struct halmac_ver *ver); + enum halmac_ret_status + (*halmac_chk_txdesc)(struct halmac_adapter *adapter, u8 *buf, u32 size); + enum halmac_ret_status + (*halmac_dl_drv_rsvd_page)(struct halmac_adapter *adapter, u8 pg_offset, + u8 *buf, u32 size); + enum halmac_ret_status + (*halmac_pcie_switch)(struct halmac_adapter *adapter, + enum halmac_pcie_cfg cfg); + enum halmac_ret_status + (*halmac_phy_cfg)(struct halmac_adapter *adapter, + enum halmac_intf_phy_platform pltfm); + enum halmac_ret_status + (*halmac_cfg_csi_rate)(struct halmac_adapter *adapter, u8 rssi, + u8 cur_rate, u8 fixrate_en, u8 *new_rate); + enum halmac_ret_status + (*halmac_sdio_cmd53_4byte)(struct halmac_adapter *adapter, + enum halmac_sdio_cmd53_4byte_mode mode); + enum halmac_ret_status + (*halmac_sdio_hw_info)(struct halmac_adapter *adapter, + struct halmac_sdio_hw_info *info); + enum halmac_ret_status + (*halmac_cfg_transmitter_addr)(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + enum halmac_ret_status + (*halmac_cfg_net_type)(struct halmac_adapter *adapter, u8 port, + enum halmac_network_type_select net_type); + enum halmac_ret_status + (*halmac_cfg_tsf_rst)(struct halmac_adapter *adapter, u8 port); + enum halmac_ret_status + (*halmac_cfg_bcn_space)(struct halmac_adapter *adapter, u8 port, + u32 bcn_space); + enum halmac_ret_status + (*halmac_rw_bcn_ctrl)(struct halmac_adapter *adapter, u8 port, + u8 write_en, struct halmac_bcn_ctrl *ctrl); + enum halmac_ret_status + (*halmac_interface_integration_tuning)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_txfifo_is_empty)(struct halmac_adapter *adapter, u32 chk_num); + enum halmac_ret_status + (*halmac_download_flash)(struct halmac_adapter *adapter, u8 *fw_bin, + u32 size, u32 rom_addr); + enum halmac_ret_status + (*halmac_read_flash)(struct halmac_adapter *adapter, u32 addr); + enum halmac_ret_status + (*halmac_erase_flash)(struct halmac_adapter *adapter, u8 erase_cmd, + u32 addr); + enum halmac_ret_status + (*halmac_check_flash)(struct halmac_adapter *adapter, u8 *fw_bin, + u32 size, u32 addr); + enum halmac_ret_status + (*halmac_cfg_edca_para)(struct halmac_adapter *adapter, + enum halmac_acq_id acq_id, + struct halmac_edca_para *param); + enum halmac_ret_status + (*halmac_pinmux_get_func)(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, u8 *enable); + enum halmac_ret_status + (*halmac_pinmux_set_func)(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func); + enum halmac_ret_status + (*halmac_pinmux_free_func)(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func); + enum halmac_ret_status + (*halmac_pinmux_wl_led_mode)(struct halmac_adapter *adapter, + enum halmac_wlled_mode mode); + void + (*halmac_pinmux_wl_led_sw_ctrl)(struct halmac_adapter *adapter, u8 on); + void + (*halmac_pinmux_sdio_int_polarity)(struct halmac_adapter *adapter, + u8 low_active); + enum halmac_ret_status + (*halmac_pinmux_gpio_mode)(struct halmac_adapter *adapter, u8 gpio_id, + u8 output); + enum halmac_ret_status + (*halmac_pinmux_gpio_output)(struct halmac_adapter *adapter, u8 gpio_id, + u8 high); + enum halmac_ret_status + (*halmac_pinmux_pin_status)(struct halmac_adapter *adapter, u8 pin_id, + u8 *high); + enum halmac_ret_status + (*halmac_ofld_func_cfg)(struct halmac_adapter *adapter, + struct halmac_ofld_func_info *info); + enum halmac_ret_status + (*halmac_rx_cut_amsdu_cfg)(struct halmac_adapter *adapter, + struct halmac_cut_amsdu_cfg *cfg); + enum halmac_ret_status + (*halmac_fw_snding)(struct halmac_adapter *adapter, + struct halmac_su_snding_info *su_info, + struct halmac_mu_snding_info *mu_info, u8 period); + enum halmac_ret_status + (*halmac_get_mac_addr)(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + enum halmac_ret_status + (*halmac_init_low_pwr)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_enter_cpu_sleep_mode)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_get_cpu_mode)(struct halmac_adapter *adapter, + enum halmac_wlcpu_mode *mode); + enum halmac_ret_status + (*halmac_drv_fwctrl)(struct halmac_adapter *adapter, u8 *payload, + u32 size, u8 ack); + enum halmac_ret_status + (*halmac_read_efuse)(struct halmac_adapter *adapter, u32 offset, + u8 *value); + enum halmac_ret_status + (*halmac_write_efuse)(struct halmac_adapter *adapter, u32 offset, + u8 value); + VOID + (*halmac_en_ref_autok_pcie)(struct halmac_adapter *adapter, u8 en); #if HALMAC_PLATFORM_TESTPROGRAM - HALMAC_RET_STATUS (*halmac_gen_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pPcket_buffer, PHAL_TXDESC_INFO pTxdesc_info); - HALMAC_RET_STATUS (*halmac_txdesc_parser)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pTxdesc, PHAL_TXDESC_PARSER pTxdesc_parser); - HALMAC_RET_STATUS (*halmac_rxdesc_parser)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pRxdesc, PHAL_RXDESC_PARSER pRxdesc_parser); - HALMAC_RET_STATUS (*halmac_get_txdesc_size)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_TXDESC_INFO pTxdesc_info, u32 *size); - HALMAC_RET_STATUS (*halmac_send_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHAL_TXDESC_INFO pTxdesc_Info); - HALMAC_RET_STATUS (*halmac_get_pcie_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 *size); - HALMAC_RET_STATUS (*halmac_gen_txagg_desc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pPcket_buffer, u32 agg_num); - HALMAC_RET_STATUS (*halmac_parse_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, PHAL_RXDESC_INFO pRxdesc_info, u8 **next_pkt); - u32 (*halmac_bb_reg_read)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 len); - HALMAC_RET_STATUS (*halmac_bb_reg_write)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_data, u8 len); - u32 (*halmac_rf_reg_read)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_RF_REG_INFO pRf_reg_info); - HALMAC_RET_STATUS (*halmac_rf_reg_write)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_RF_REG_INFO pRf_reg_info); - HALMAC_RET_STATUS (*halmac_init_antenna_selection)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_bb_preconfig)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_init_crystal_capacity)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_trx_antenna_setting)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_himr_setting_sdio)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SDIO_HIMR_INFO sdio_himr_sdio); - HALMAC_RET_STATUS (*halmac_dump_cam_table)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_num, PHALMAC_CAM_ENTRY_FORMAT pCam_table); - HALMAC_RET_STATUS (*halmac_load_cam_table)(PHALMAC_ADAPTER pHalmac_adapter, u8 entry_num, PHALMAC_CAM_ENTRY_FORMAT pCam_table); - HALMAC_RET_STATUS (*halmac_send_beacon)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_BEACON_INFO pbeacon_info); - HALMAC_RET_STATUS (*halmac_get_management_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 *pSize, PHALMAC_MGNT_INFO pmgnt_info); - HALMAC_RET_STATUS (*halmac_send_control)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_CTRL_INFO pctrl_info); - HALMAC_RET_STATUS (*halmac_send_hiqueue)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_HIGH_QUEUE_INFO pHigh_info); - HALMAC_RET_STATUS (*halmac_run_pwrseq)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PWR_SEQ_ID seq); - HALMAC_RET_STATUS (*halmac_stop_beacon)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_check_trx_status)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_set_agg_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 agg_num); - HALMAC_RET_STATUS (*halmac_timer_10ms)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_download_firmware_fpag)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 iram_address); - HALMAC_RET_STATUS (*halmac_download_rom_fpga)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address); - HALMAC_RET_STATUS (*halmac_send_nlo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_NLO_CFG pNlo_cfg); - HALMAC_RET_STATUS (*halmac_get_chip_type)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CHIP_TYPE pChip_type); - u32 (*halmac_get_rx_agg_num)(PHALMAC_ADAPTER pHalmac_adapter, u32 pkt_size, u8 *pPkt_buff); - u8 (*halmac_check_rx_scsi_resp)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pRxdesc, PHAL_RXDESC_PARSER pRxdesc_parser); - VOID (*halmac_get_hcpwm)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHcpwm); - VOID (*halmac_get_hcpwm2)(PHALMAC_ADAPTER pHalmac_adapter, u16 *pHcpwm2); - VOID (*halmac_set_hrpwm)(PHALMAC_ADAPTER pHalmac_adapter, u8 hrpwm); - VOID (*halmac_set_hrpwm2)(PHALMAC_ADAPTER pHalmac_adapter, u16 hrpwm2); - HALMAC_RET_STATUS (*halmac_coex_cfg)(PHALMAC_ADAPTER pHalmac_adapter); + struct halmisc_api *halmisc_api; #endif -} HALMAC_API, *PHALMAC_API; - -#define HALMAC_GET_API(phalmac_adapter) ((PHALMAC_API)phalmac_adapter->pHalmac_api) - -static HALMAC_INLINE HALMAC_RET_STATUS -halmac_adapter_validate( - PHALMAC_ADAPTER pHalmac_adapter -) -{ - if ((pHalmac_adapter == NULL) || (pHalmac_adapter->pHalAdapter_backup != pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; +}; - return HALMAC_RET_SUCCESS; -} - -static HALMAC_INLINE HALMAC_RET_STATUS -halmac_api_validate( - PHALMAC_ADAPTER pHalmac_adapter -) -{ - if (pHalmac_adapter->halmac_state.api_state != HALMAC_API_STATE_INIT) - return HALMAC_RET_API_INVALID; - - return HALMAC_RET_SUCCESS; -} +#define HALMAC_GET_API(halmac_adapter) \ + ((struct halmac_api *)halmac_adapter->halmac_api) -static HALMAC_INLINE HALMAC_RET_STATUS -halmac_fw_validate( - PHALMAC_ADAPTER pHalmac_adapter -) +static HALMAC_INLINE enum halmac_ret_status +halmac_fw_validate(struct halmac_adapter *adapter) { - if (pHalmac_adapter->halmac_state.dlfw_state != HALMAC_DLFW_DONE && pHalmac_adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT) + if (adapter->halmac_state.dlfw_state != HALMAC_DLFW_DONE && + adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT) return HALMAC_RET_NO_DLFW; return HALMAC_RET_SUCCESS; diff --git a/hal/halmac/halmac_usb_reg.h b/hal/halmac/halmac_usb_reg.h index b984670..b856c55 100644 --- a/hal/halmac/halmac_usb_reg.h +++ b/hal/halmac/halmac_usb_reg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -16,8 +16,4 @@ #ifndef __HALMAC_USB_REG_H__ #define __HALMAC_USB_REG_H__ - - - - #endif/* __HALMAC_USB_REG_H__ */ diff --git a/hal/led/hal_usb_led.c b/hal/led/hal_usb_led.c index 41f1f6a..19505b1 100644 --- a/hal/led/hal_usb_led.c +++ b/hal/led/hal_usb_led.c @@ -15,6 +15,7 @@ #include #include +#ifdef CONFIG_RTW_SW_LED /* * Description: @@ -118,7 +119,7 @@ SwLedBlink1( { _adapter *padapter = pLed->padapter; PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); PLED_USB pLed1 = &(ledpriv->SwLed1); u8 bStopBlinking = _FALSE; @@ -506,7 +507,7 @@ SwLedBlink4( ) { _adapter *padapter = pLed->padapter; - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); PLED_USB pLed1 = &(ledpriv->SwLed1); u8 bStopBlinking = _FALSE; @@ -1732,7 +1733,7 @@ SwLedBlink15( void BlinkHandler(PLED_USB pLed) { _adapter *padapter = pLed->padapter; - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); /* RTW_INFO("%s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); */ @@ -1745,6 +1746,12 @@ void BlinkHandler(PLED_USB pLed) } switch (ledpriv->LedStrategy) { + #if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY + case SW_LED_MODE_UC_TRX_ONLY: + rtw_sw_led_blink_uc_trx_only(pLed); + break; + #endif + case SW_LED_MODE0: SwLedBlink(pLed); break; @@ -1835,7 +1842,7 @@ void BlinkTimerCallback(void *data) return; } -#ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD +#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD rtw_led_blink_cmd(padapter, (PVOID)pLed); #else _set_workitem(&(pLed->BlinkWorkItem)); @@ -1859,7 +1866,7 @@ SwLedControlMode0( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); PLED_USB pLed = &(ledpriv->SwLed1); /* Decide led state */ @@ -1961,7 +1968,7 @@ SwLedControlMode1( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); PLED_USB pLed = &(ledpriv->SwLed0); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); @@ -2198,7 +2205,7 @@ SwLedControlMode2( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; PLED_USB pLed = &(ledpriv->SwLed0); @@ -2337,7 +2344,7 @@ SwLedControlMode3( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; PLED_USB pLed = &(ledpriv->SwLed0); @@ -2492,7 +2499,7 @@ SwLedControlMode4( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; PLED_USB pLed = &(ledpriv->SwLed0); PLED_USB pLed1 = &(ledpriv->SwLed1); @@ -2797,7 +2804,7 @@ SwLedControlMode5( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); PLED_USB pLed = &(ledpriv->SwLed0); @@ -2876,7 +2883,7 @@ SwLedControlMode6( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; PLED_USB pLed0 = &(ledpriv->SwLed0); @@ -2907,7 +2914,7 @@ SwLedControlMode7( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; PLED_USB pLed = &(ledpriv->SwLed0); @@ -3046,7 +3053,7 @@ SwLedControlMode8( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; PLED_USB pLed0 = &(ledpriv->SwLed0); @@ -3083,7 +3090,7 @@ SwLedControlMode9( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; PLED_USB pLed = &(ledpriv->SwLed0); PLED_USB pLed1 = &(ledpriv->SwLed1); @@ -3386,7 +3393,7 @@ SwLedControlMode10( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; PLED_USB pLed = &(ledpriv->SwLed0); PLED_USB pLed1 = &(ledpriv->SwLed1); @@ -3583,7 +3590,7 @@ SwLedControlMode11( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; PLED_USB pLed = &(ledpriv->SwLed0); @@ -3682,7 +3689,7 @@ SwLedControlMode12( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; PLED_USB pLed = &(ledpriv->SwLed0); @@ -3763,7 +3770,7 @@ SwLedControlMode13( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; PLED_USB pLed = &(ledpriv->SwLed0); @@ -3909,7 +3916,7 @@ SwLedControlMode14( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); PLED_USB pLed = &(ledpriv->SwLed0); switch (LedAction) { @@ -3968,7 +3975,7 @@ SwLedControlMode15( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; PLED_USB pLed = &(ledpriv->SwLed0); @@ -4117,7 +4124,7 @@ LedControlUSB( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); #if (MP_DRIVER == 1) if (padapter->registrypriv.mp_mode == 1) @@ -4138,12 +4145,6 @@ LedControlUSB( /* if(priv->bInHctTest) */ /* return; */ -#ifdef CONFIG_CONCURRENT_MODE - /* Only do led action for PRIMARY_ADAPTER */ - if (padapter->adapter_type != PRIMARY_ADAPTER) - return; -#endif - if ((adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) && (LedAction == LED_CTL_TX || LedAction == LED_CTL_RX || @@ -4154,6 +4155,12 @@ LedControlUSB( return; switch (ledpriv->LedStrategy) { + #if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY + case SW_LED_MODE_UC_TRX_ONLY: + rtw_sw_led_ctl_mode_uc_trx_only(padapter, LedAction); + break; + #endif + case SW_LED_MODE0: SwLedControlMode0(padapter, LedAction); break; @@ -4280,3 +4287,4 @@ DeInitLed( _cancel_timer_ex(&(pLed->BlinkTimer)); ResetLedStatus(pLed); } +#endif diff --git a/hal/phydm/ap_makefile.mk b/hal/phydm/ap_makefile.mk index 5731398..d578c8e 100644 --- a/hal/phydm/ap_makefile.mk +++ b/hal/phydm/ap_makefile.mk @@ -3,24 +3,34 @@ _PHYDM_FILES :=\ phydm/phydm.o \ phydm/phydm_dig.o\ phydm/phydm_antdiv.o\ - phydm/phydm_dynamicbbpowersaving.o\ + phydm/phydm_soml.o\ + phydm/phydm_smt_ant.o\ phydm/phydm_pathdiv.o\ phydm/phydm_rainfo.o\ phydm/phydm_dynamictxpower.o\ phydm/phydm_adaptivity.o\ phydm/phydm_debug.o\ phydm/phydm_interface.o\ + phydm/phydm_phystatus.o\ phydm/phydm_hwconfig.o\ phydm/phydm_dfs.o\ phydm/phydm_cfotracking.o\ - phydm/phydm_acs.o\ phydm/phydm_adc_sampling.o\ phydm/phydm_ccx.o\ + phydm/phydm_primary_cca.o\ + phydm/phydm_cck_pd.o\ + phydm/phydm_rssi_monitor.o\ + phydm/phydm_auto_dbg.o\ + phydm/phydm_math_lib.o\ + phydm/phydm_noisemonitor.o\ + phydm/phydm_api.o\ + phydm/phydm_pow_train.o\ phydm/txbf/phydm_hal_txbf_api.o\ EdcaTurboCheck.o\ phydm/halrf/halrf.o\ phydm/halrf/halphyrf_ap.o\ phydm/halrf/halrf_powertracking_ap.o\ + phydm/halrf/halrf_powertracking.o\ phydm/halrf/halrf_kfree.o ifeq ($(CONFIG_RTL_88E_SUPPORT),y) @@ -73,7 +83,6 @@ ifeq ($(CONFIG_WLAN_HAL_8822BE),y) phydm/rtl8822b/halhwimg8822b_bb.o\ phydm/rtl8822b/halhwimg8822b_mac.o\ phydm/rtl8822b/halhwimg8822b_rf.o\ - phydm/rtl8822b/halhwimg8822b_fw.o\ phydm/rtl8822b/phydm_regconfig8822b.o\ phydm/rtl8822b/phydm_hal_api8822b.o\ phydm/rtl8822b/phydm_rtl8822b.o diff --git a/hal/phydm/halphyrf_ap.c b/hal/phydm/halphyrf_ap.c deleted file mode 100644 index 6cb87f8..0000000 --- a/hal/phydm/halphyrf_ap.c +++ /dev/null @@ -1,2790 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - #include "mp_precomp.h" - #include "phydm_precomp.h" - -#ifndef index_mapping_NUM_88E - #define index_mapping_NUM_88E 15 -#endif - -//#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) - -#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ - do {\ - for(_offset = 0; _offset < _size; _offset++)\ - {\ - if(_deltaThermal < thermalThreshold[_direction][_offset])\ - {\ - if(_offset != 0)\ - _offset--;\ - break;\ - }\ - } \ - if(_offset >= _size)\ - _offset = _size-1;\ - } while(0) - - -void ConfigureTxpowerTrack( - IN PVOID pDM_VOID, - OUT PTXPWRTRACK_CFG pConfig - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if RTL8812A_SUPPORT -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - //if (IS_HARDWARE_TYPE_8812(pDM_Odm->Adapter)) - if(pDM_Odm->SupportICType==ODM_RTL8812) - ConfigureTxpowerTrack_8812A(pConfig); - //else -#endif -#endif - -#if RTL8814A_SUPPORT - if(pDM_Odm->SupportICType== ODM_RTL8814A) - ConfigureTxpowerTrack_8814A(pConfig); -#endif - - -#if RTL8188E_SUPPORT - if(pDM_Odm->SupportICType==ODM_RTL8188E) - ConfigureTxpowerTrack_8188E(pConfig); -#endif - -#if RTL8197F_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8197F) - ConfigureTxpowerTrack_8197F(pConfig); -#endif - -#if RTL8822B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8822B) - ConfigureTxpowerTrack_8822B(pConfig); -#endif - - -} - -#if (RTL8192E_SUPPORT==1) -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte ThermalValue = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode; - u1Byte ThermalValue_AVG_count = 0; - u1Byte OFDM_min_index = 10; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur - s1Byte OFDM_index[2], index ; - u4Byte ThermalValue_AVG = 0, Reg0x18; - u4Byte i = 0, j = 0, rf; - s4Byte value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y; - prtl8192cd_priv priv = pDM_Odm->priv; - - rf_mimo_mode = pDM_Odm->RFType; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode)); - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - channel = priv->pshare->working_channel; - if (priv->pshare->mp_txpwr_tracking == FALSE) - return; - } else -#endif - { - channel = (priv->pmib->dot11RFEntry.dot11channel); - } - - ThermalValue = (unsigned char)ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00); //0x42: RF Reg[15:10] 88E - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); - - - switch (rf_mimo_mode) { - case MIMO_1T1R: - rf = 1; - break; - case MIMO_2T2R: - rf = 2; - break; - default: - rf = 2; - break; - } - - //Query OFDM path A default setting Bit[31:21] - ele_D = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskOFDM_D); - for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { - if (ele_D == (OFDMSwingTable_92E[i] >> 22)) { - OFDM_index[0] = (unsigned char)i; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0])); - break; - } - } - - //Query OFDM path B default setting - if (rf_mimo_mode == MIMO_2T2R) { - ele_D = PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskOFDM_D); - for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { - if (ele_D == (OFDMSwingTable_92E[i] >> 22)) { - OFDM_index[1] = (unsigned char)i; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1])); - break; - } - } - } - - /* calculate average thermal meter */ - { - priv->pshare->ThermalValue_AVG_88XX[priv->pshare->ThermalValue_AVG_index_88XX] = ThermalValue; - priv->pshare->ThermalValue_AVG_index_88XX++; - if (priv->pshare->ThermalValue_AVG_index_88XX == AVG_THERMAL_NUM_88XX) - priv->pshare->ThermalValue_AVG_index_88XX = 0; - - for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) { - if (priv->pshare->ThermalValue_AVG_88XX[i]) { - ThermalValue_AVG += priv->pshare->ThermalValue_AVG_88XX[i]; - ThermalValue_AVG_count++; - } - } - - if (ThermalValue_AVG_count) { - ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue)); - } - } - - /* Initialize */ - if (!priv->pshare->ThermalValue) { - priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; - priv->pshare->ThermalValue_IQK = ThermalValue; - priv->pshare->ThermalValue_LCK = ThermalValue; - } - - if (ThermalValue != priv->pshare->ThermalValue) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** START POWER TRACKING ********\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); - - delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); - delta_IQK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_IQK); - delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK); - is_decrease = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 1 : 0); - -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Diff: (%s)%d ==> get index from table : %d)\n", (is_decrease?"-":"+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); - - if (is_decrease) { - for (i = 0; i < rf; i++) { - OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); - OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); - CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); - CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1))); - } - } else { - for (i = 0; i < rf; i++) { - OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); - OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); - CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); - CCK_index = ((CCK_index < 0 )? 0 : CCK_index); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1))); - } - } - } -#endif //CFG_TRACKING_TABLE_FILE - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] = %x \n",OFDMSwingTable_92E[(unsigned int)OFDM_index[0]])); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] = %x \n",OFDMSwingTable_92E[(unsigned int)OFDM_index[1]])); - - //Adujst OFDM Ant_A according to IQK result - ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22; - X = priv->pshare->RegE94; - Y = priv->pshare->RegE9C; - - if (X != 0) { - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D) >> 8) & 0x000003FF; - - //new element C = element D x Y - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D) >> 8) & 0x000003FF; - - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C&0x000003C0)>>6; - PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, value32); - - value32 = ((X * ele_D)>>7)&0x01; - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), value32); - } else { - PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_92E[(unsigned int)OFDM_index[0]]); - PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), 0x00); - } - - set_CCK_swing_index(priv, CCK_index); - - if (rf == 2) { - ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22; - X = priv->pshare->RegEB4; - Y = priv->pshare->RegEBC; - - if (X != 0) { - if ((X & 0x00000200) != 0) //consider minus - X = X | 0xFFFFFC00; - ele_A = ((X * ele_D) >> 8) & 0x000003FF; - - //new element C = element D x Y - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - ele_C = ((Y * ele_D) >> 8) & 0x00003FF; - - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 - value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); - - value32 = (ele_C & 0x000003C0) >> 6; - PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, value32); - - value32 = ((X * ele_D) >> 7) & 0x01; - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), value32); - } else { - PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_92E[(unsigned int)OFDM_index[1]]); - PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); - PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), 0x00); - } - - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc80 = 0x%x \n", PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc88 = 0x%x \n", PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord))); - - if (delta_IQK > 3) { - priv->pshare->ThermalValue_IQK = ThermalValue; -#ifdef MP_TEST - if (!(priv->pshare->rf_ft_var.mp_specific && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET)))) -#endif - PHY_IQCalibrate_8192E(pDM_Odm,false); - } - - if (delta_LCK > 8) { - RTL_W8(0x522, 0xff); - Reg0x18 = PHY_QueryRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, 1); - PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 1); - PHY_SetRFReg(priv, RF_PATH_A, 0x18, BIT(15), 1); - delay_ms(1); - PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 0); - PHY_SetRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, Reg0x18); - RTL_W8(0x522, 0x0); - priv->pshare->ThermalValue_LCK = ThermalValue; - } - } - - //update thermal meter value - priv->pshare->ThermalValue = ThermalValue; - for (i = 0 ; i < rf ; i++) - priv->pshare->OFDM_index[i] = OFDM_index[i]; - priv->pshare->CCK_index = CCK_index; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__)); -} -#endif - - - -#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ) -{ -#if 1 - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, channel, is_increase; - u1Byte ThermalValue_AVG_count = 0, p = 0, i = 0; - u4Byte ThermalValue_AVG = 0; - prtl8192cd_priv priv = pDM_Odm->priv; - TXPWRTRACK_CFG c; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - /*4 1. The following TWO tables decide the final index of OFDM/CCK swing table.*/ - pu1Byte deltaSwingTableIdx_TUP_A = NULL, deltaSwingTableIdx_TDOWN_A = NULL; - pu1Byte deltaSwingTableIdx_TUP_B = NULL, deltaSwingTableIdx_TDOWN_B = NULL; - pu1Byte deltaSwingTableIdx_TUP_CCK_A = NULL, deltaSwingTableIdx_TDOWN_CCK_A = NULL; - pu1Byte deltaSwingTableIdx_TUP_CCK_B = NULL, deltaSwingTableIdx_TDOWN_CCK_B = NULL; - /*for 8814 add by Yu Chen*/ - pu1Byte deltaSwingTableIdx_TUP_C = NULL, deltaSwingTableIdx_TDOWN_C = NULL; - pu1Byte deltaSwingTableIdx_TUP_D = NULL, deltaSwingTableIdx_TDOWN_D = NULL; - pu1Byte deltaSwingTableIdx_TUP_CCK_C = NULL, deltaSwingTableIdx_TDOWN_CCK_C = NULL; - pu1Byte deltaSwingTableIdx_TUP_CCK_D = NULL, deltaSwingTableIdx_TDOWN_CCK_D = NULL; - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - channel = priv->pshare->working_channel; - if (priv->pshare->mp_txpwr_tracking == FALSE) - return; - } else -#endif - { - channel = (priv->pmib->dot11RFEntry.dot11channel); - } - - ConfigureTxpowerTrack(pDM_Odm, &c); - - (*c.GetDeltaAllSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A, - (pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B, - (pu1Byte *)&deltaSwingTableIdx_TUP_CCK_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_CCK_A, - (pu1Byte *)&deltaSwingTableIdx_TUP_CCK_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_CCK_B); - - ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); /*0x42: RF Reg[15:10] 88E*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Readback Thermal Meter = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n" - , ThermalValue, ThermalValue, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther)); - - /* Initialize */ - if (!pDM_Odm->RFCalibrateInfo.ThermalValue) - pDM_Odm->RFCalibrateInfo.ThermalValue = priv->pmib->dot11RFEntry.ther; - - if (!pDM_Odm->RFCalibrateInfo.ThermalValue_LCK) - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = priv->pmib->dot11RFEntry.ther; - - if (!pDM_Odm->RFCalibrateInfo.ThermalValue_IQK) - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = priv->pmib->dot11RFEntry.ther; - - /* calculate average thermal meter */ - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; - - if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/ - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; - - for (i = 0; i < c.AverageThermalNum; i++) { - if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) { - ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; - ThermalValue_AVG_count++; - } - } - - if (ThermalValue_AVG_count) {/*Calculate Average ThermalValue after average enough times*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("ThermalValue_AVG=0x%x(%d) ThermalValue_AVG_count = %d\n" - , ThermalValue_AVG, ThermalValue_AVG, ThermalValue_AVG_count)); - - ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", ThermalValue, ThermalValue, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther)); - } - - /*4 Calculate delta, delta_LCK, delta_IQK.*/ - delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); - delta_LCK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_LCK); - delta_IQK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_IQK); - is_increase = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 0 : 1); - - if (delta > 29) { /* power track table index(thermal diff.) upper bound*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta(%d) > 29, set delta to 29\n", delta)); - delta = 29; - } - - - /*4 if necessary, do LCK.*/ - - if (delta_LCK > c.Threshold_IQK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; - if (c.PHY_LCCalibrate) - (*c.PHY_LCCalibrate)(pDM_Odm); - } - - if (delta_IQK > c.Threshold_IQK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; - if (c.DoIQK) - (*c.DoIQK)(pDM_Odm, TRUE, 0, 0); - } - - if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ - return; - - /*4 Do Power Tracking*/ - - if (ThermalValue != pDM_Odm->RFCalibrateInfo.ThermalValue) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n******** START POWER TRACKING ********\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", - ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther)); - -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) { - if (is_increase) { /*thermal is higher than base*/ - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_B[%d] = %d deltaSwingTableIdx_TUP_CCK_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta], delta, deltaSwingTableIdx_TUP_CCK_B[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_B[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_C[%d] = %d deltaSwingTableIdx_TUP_CCK_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta], delta, deltaSwingTableIdx_TUP_CCK_C[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_C[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_D[%d] = %d deltaSwingTableIdx_TUP_CCK_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta], delta, deltaSwingTableIdx_TUP_CCK_D[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_D[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_A[%d] = %d deltaSwingTableIdx_TUP_CCK_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta], delta, deltaSwingTableIdx_TUP_CCK_A[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_A[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - } - } - } else { /* thermal is lower than base*/ - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_B[%d] = %d deltaSwingTableIdx_TDOWN_CCK_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta], delta, deltaSwingTableIdx_TDOWN_CCK_B[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_B[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_C[%d] = %d deltaSwingTableIdx_TDOWN_CCK_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta], delta, deltaSwingTableIdx_TDOWN_CCK_C[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_C[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_D[%d] = %d deltaSwingTableIdx_TDOWN_CCK_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta], delta, deltaSwingTableIdx_TDOWN_CCK_D[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_D[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_A[%d] = %d deltaSwingTableIdx_TDOWN_CCK_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta], delta, deltaSwingTableIdx_TDOWN_CCK_A[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; - pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_A[delta]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p])); - break; - } - } - } - - if (is_increase) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power --->\n")); - if (GET_CHIP_VER(priv) == VERSION_8197F) { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, 0); - } else if (GET_CHIP_VER(priv) == VERSION_8822B) { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power --->\n")); - if (GET_CHIP_VER(priv) == VERSION_8197F) { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, 0); - } else if (GET_CHIP_VER(priv) == VERSION_8822B) { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } - } - } -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n\n", __func__)); - /*update thermal meter value*/ - pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; - - } - -#endif -} -#endif - -/*#if (RTL8814A_SUPPORT == 1)*/ -#if (RTL8814A_SUPPORT == 1) - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, channel, is_increase; - u1Byte ThermalValue_AVG_count = 0, p = 0, i = 0; - u4Byte ThermalValue_AVG = 0, Reg0x18; - u4Byte BBSwingReg[4] = {rA_TxScale_Jaguar,rB_TxScale_Jaguar,rC_TxScale_Jaguar2,rD_TxScale_Jaguar2}; - s4Byte ele_D; - u4Byte BBswingIdx; - prtl8192cd_priv priv = pDM_Odm->priv; - TXPWRTRACK_CFG c; - BOOLEAN bTSSIenable = FALSE; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. - pu1Byte deltaSwingTableIdx_TUP_A = NULL, deltaSwingTableIdx_TDOWN_A = NULL; - pu1Byte deltaSwingTableIdx_TUP_B = NULL, deltaSwingTableIdx_TDOWN_B = NULL; - //for 8814 add by Yu Chen - pu1Byte deltaSwingTableIdx_TUP_C = NULL, deltaSwingTableIdx_TDOWN_C = NULL; - pu1Byte deltaSwingTableIdx_TUP_D = NULL, deltaSwingTableIdx_TDOWN_D = NULL; - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - channel = priv->pshare->working_channel; - if (priv->pshare->mp_txpwr_tracking == FALSE) - return; - } else -#endif - { - channel = (priv->pmib->dot11RFEntry.dot11channel); - } - - ConfigureTxpowerTrack(pDM_Odm, &c); - pRFCalibrateInfo->DefaultOfdmIndex = priv->pshare->OFDM_index0[ODM_RF_PATH_A]; - - (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_A, (pu1Byte*)&deltaSwingTableIdx_TDOWN_A, - (pu1Byte*)&deltaSwingTableIdx_TUP_B, (pu1Byte*)&deltaSwingTableIdx_TDOWN_B); - - if(pDM_Odm->SupportICType & ODM_RTL8814A) // for 8814 path C & D - (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_C, (pu1Byte*)&deltaSwingTableIdx_TDOWN_C, - (pu1Byte*)&deltaSwingTableIdx_TUP_D, (pu1Byte*)&deltaSwingTableIdx_TDOWN_D); - - ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther)); - - /* Initialize */ - if (!pDM_Odm->RFCalibrateInfo.ThermalValue) { - pDM_Odm->RFCalibrateInfo.ThermalValue = priv->pmib->dot11RFEntry.ther; - } - - if (!pDM_Odm->RFCalibrateInfo.ThermalValue_LCK) { - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = priv->pmib->dot11RFEntry.ther; - } - - if (!pDM_Odm->RFCalibrateInfo.ThermalValue_IQK) { - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = priv->pmib->dot11RFEntry.ther; - } - - bTSSIenable = (BOOLEAN)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, rRF_TxGainOffset, BIT7); // check TSSI enable - - //4 Query OFDM BB swing default setting Bit[31:21] - for(p = ODM_RF_PATH_A ; p < c.RfPathCount ; p++) - { - ele_D = ODM_GetBBReg(pDM_Odm, BBSwingReg[p], 0xffe00000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("0x%x:0x%x ([31:21] = 0x%x)\n", BBSwingReg[p], ODM_GetBBReg(pDM_Odm, BBSwingReg[p], bMaskDWord), ele_D)); - - for (BBswingIdx = 0; BBswingIdx < TXSCALE_TABLE_SIZE; BBswingIdx++) {//4 - if (ele_D == TxScalingTable_Jaguar[BBswingIdx]) { - pDM_Odm->RFCalibrateInfo.OFDM_index[p] = (u1Byte)BBswingIdx; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("OFDM_index[%d]=%d\n",p, pDM_Odm->RFCalibrateInfo.OFDM_index[p])); - break; - } - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("KfreeOffset[%d]=%d\n",p, pRFCalibrateInfo->KfreeOffset[p])); - - } - - /* calculate average thermal meter */ - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; - if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) //Average times = c.AverageThermalNum - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; - - for(i = 0; i < c.AverageThermalNum; i++) - { - if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) - { - ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; - ThermalValue_AVG_count++; - } - } - - if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times - { - ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", ThermalValue, priv->pmib->dot11RFEntry.ther)); - } - - //4 Calculate delta, delta_LCK, delta_IQK. - delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); - delta_LCK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_LCK); - delta_IQK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_IQK); - is_increase = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 0 : 1); - - //4 if necessary, do LCK. - if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { - if (delta_LCK > c.Threshold_IQK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; - - /*Use RTLCK, so close power tracking driver LCK*/ - #if (RTL8814A_SUPPORT != 1) - if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { - if (c.PHY_LCCalibrate) - (*c.PHY_LCCalibrate)(pDM_Odm); - } - #endif - } - } - - if (delta_IQK > c.Threshold_IQK) - { - panic_printk("%s(%d)\n", __FUNCTION__, __LINE__); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; - if(c.DoIQK) - (*c.DoIQK)(pDM_Odm, TRUE, 0, 0); - } - - if(!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ - return; - - //4 Do Power Tracking - - if(bTSSIenable == TRUE) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter PURE TSSI MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0); - } - else if (ThermalValue != pDM_Odm->RFCalibrateInfo.ThermalValue) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n******** START POWER TRACKING ********\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther)); - -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) - { - if (is_increase) // thermal is higher than base - { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - { - switch(p) - { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - } - } - } - else // thermal is lower than base - { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - { - switch(p) - { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta])); - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; // Record delta swing for mix mode power tracking - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - } - } - } - - if (is_increase) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> increse power ---> \n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power --->\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } - } -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** END:%s() ********\n", __FUNCTION__)); - //update thermal meter value - pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; - - } -} -#endif - -#if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1) -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - unsigned char ThermalValue = 0, delta, delta_LCK, channel, is_decrease; - unsigned char ThermalValue_AVG_count = 0; - unsigned int ThermalValue_AVG = 0, Reg0x18; - unsigned int BBSwingReg[4]={0xc1c,0xe1c,0x181c,0x1a1c}; - int ele_D, value32; - char OFDM_index[2], index; - unsigned int i = 0, j = 0, rf_path, max_rf_path =2 ,rf; - prtl8192cd_priv priv = pDM_Odm->priv; - unsigned char OFDM_min_index = 7; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic - - - -#ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { - channel = priv->pshare->working_channel; - if (priv->pshare->mp_txpwr_tracking == FALSE) - return; - } else -#endif - { - channel = (priv->pmib->dot11RFEntry.dot11channel); - } - -#if RTL8881A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8881A) { - max_rf_path = 1; - if ((get_bonding_type_8881A() == BOND_8881AM ||get_bonding_type_8881A() == BOND_8881AN) - && priv->pshare->rf_ft_var.use_intpa8881A && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)) - OFDM_min_index = 6; // intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phyBandSelect == PHY_BAND_2G)) - else - OFDM_min_index = 10; //OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic - } -#endif - - - ThermalValue = (unsigned char)PHY_QueryRFReg(priv, RF_PATH_A, 0x42, 0xfc00, 1); //0x42: RF Reg[15:10] 88E - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); - - - //4 Query OFDM BB swing default setting Bit[31:21] - for(rf_path = 0 ; rf_path < max_rf_path ; rf_path++){ - ele_D = PHY_QueryBBReg(priv, BBSwingReg[rf_path], 0xffe00000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0x%x:0x%x ([31:21] = 0x%x)\n",BBSwingReg[rf_path], PHY_QueryBBReg(priv, BBSwingReg[rf_path], bMaskDWord),ele_D)); - for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {//4 - if (ele_D == OFDMSwingTable_8812[i]) { - OFDM_index[rf_path] = (unsigned char)i; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[%d]=%d\n",rf_path, OFDM_index[rf_path])); - break; - } - } - } -#if 0 - //Query OFDM path A default setting Bit[31:21] - ele_D = PHY_QueryBBReg(priv, 0xc1c, 0xffe00000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0xc1c:0x%x ([31:21] = 0x%x)\n", PHY_QueryBBReg(priv, 0xc1c, bMaskDWord),ele_D)); - for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {//4 - if (ele_D == OFDMSwingTable_8812[i]) { - OFDM_index[0] = (unsigned char)i; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[0]=%d\n", OFDM_index[0])); - break; - } - } - //Query OFDM path B default setting - if (rf == 2) { - ele_D = PHY_QueryBBReg(priv, 0xe1c, 0xffe00000); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0xe1c:0x%x ([32:21] = 0x%x)\n", PHY_QueryBBReg(priv, 0xe1c, bMaskDWord),ele_D)); - for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) { - if (ele_D == OFDMSwingTable_8812[i]) { - OFDM_index[1] = (unsigned char)i; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[1]=%d\n", OFDM_index[1])); - break; - } - } - } -#endif - /* Initialize */ - if (!priv->pshare->ThermalValue) { - priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; - priv->pshare->ThermalValue_LCK = ThermalValue; - } - - /* calculate average thermal meter */ - { - priv->pshare->ThermalValue_AVG_8812[priv->pshare->ThermalValue_AVG_index_8812] = ThermalValue; - priv->pshare->ThermalValue_AVG_index_8812++; - if (priv->pshare->ThermalValue_AVG_index_8812 == AVG_THERMAL_NUM_8812) - priv->pshare->ThermalValue_AVG_index_8812 = 0; - - for (i = 0; i < AVG_THERMAL_NUM_8812; i++) { - if (priv->pshare->ThermalValue_AVG_8812[i]) { - ThermalValue_AVG += priv->pshare->ThermalValue_AVG_8812[i]; - ThermalValue_AVG_count++; - } - } - - if (ThermalValue_AVG_count) { - ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); - //printk("AVG Thermal Meter = 0x%x \n", ThermalValue); - } - } - - - //4 If necessary, do power tracking - - if(!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ - return; - - if (ThermalValue != priv->pshare->ThermalValue) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** START POWER TRACKING ********\n")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); - delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); - delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK); - is_decrease = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 1 : 0); - //if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) - { -#ifdef _TRACKING_TABLE_FILE - if (priv->pshare->rf_ft_var.pwr_track_file) { - for (rf_path = 0; rf_path < max_rf_path; rf_path++) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Diff: (%s)%d ==> get index from table : %d)\n", (is_decrease?"-":"+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); - if (is_decrease) { - OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); - OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); -#if 0// RTL8881A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8881A){ - if(priv->pshare->rf_ft_var.pwrtrk_TxAGC_enable){ - if(priv->pshare->AddTxAGC){//TxAGC has been added - AddTxPower88XX_AC(priv,0); - priv->pshare->AddTxAGC = 0; - priv->pshare->AddTxAGC_index = 0; - } - } - } -#endif - } else { - - OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); -#if 0// RTL8881A_SUPPORT - if(pDM_Odm->SupportICType == ODM_RTL8881A){ - if(priv->pshare->rf_ft_var.pwrtrk_TxAGC_enable){ - if(OFDM_index[i] < OFDM_min_index){ - priv->pshare->AddTxAGC_index = (OFDM_min_index - OFDM_index[i])/2; // Calculate Remnant TxAGC Value, 2 index for 1 TxAGC - AddTxPower88XX_AC(priv,priv->pshare->AddTxAGC_index); - priv->pshare->AddTxAGC = 1; //AddTxAGC Flag = 1 - OFDM_index[i] = OFDM_min_index; - } - else{ - if(priv->pshare->AddTxAGC){// TxAGC been added - priv->pshare->AddTxAGC = 0; - priv->pshare->AddTxAGC_index = 0; - AddTxPower88XX_AC(priv,0); //minus the added TPI - } - } - } - } -#else - OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ? OFDM_min_index : OFDM_index[rf_path]); -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); - } - } - } -#endif - //4 Set new BB swing index - for (rf_path = 0; rf_path < max_rf_path; rf_path++) { - PHY_SetBBReg(priv, BBSwingReg[rf_path], 0xffe00000, OFDMSwingTable_8812[(unsigned int)OFDM_index[rf_path]]); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n",BBSwingReg[rf_path], PHY_QueryBBReg(priv, BBSwingReg[rf_path], 0xffe00000), OFDM_index[rf_path])); - } - - } - if (delta_LCK > 8) { - RTL_W8(0x522, 0xff); - Reg0x18 = PHY_QueryRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, 1); - PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 1); - PHY_SetRFReg(priv, RF_PATH_A, 0x18, BIT(15), 1); - delay_ms(200); // frequency deviation - PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 0); - PHY_SetRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, Reg0x18); - #ifdef CONFIG_RTL_8812_SUPPORT - if (GET_CHIP_VER(priv)== VERSION_8812E) - UpdateBBRFVal8812(priv, priv->pmib->dot11RFEntry.dot11channel); - #endif - RTL_W8(0x522, 0x0); - priv->pshare->ThermalValue_LCK = ThermalValue; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** END:%s() ********\n", __FUNCTION__)); - - //update thermal meter value - priv->pshare->ThermalValue = ThermalValue; - for (rf_path = 0; rf_path < max_rf_path; rf_path++) - priv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path]; - } -} - -#endif - - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - -#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8197F || pDM_Odm->SupportICType == ODM_RTL8822B) { - ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3(pDM_Odm); - return; - } -#endif -#if (RTL8814A_SUPPORT == 1) /*use this function to do power tracking after 8814 by YuChen*/ - if (pDM_Odm->SupportICType & ODM_RTL8814A) { - ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2(pDM_Odm); - return; - } -#endif -#if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8812 || pDM_Odm->SupportICType & ODM_RTL8881A) { - ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries(pDM_Odm); - return; - } -#endif - -#if (RTL8192E_SUPPORT == 1) - if (pDM_Odm->SupportICType==ODM_RTL8192E) { - ODM_TXPowerTrackingCallback_ThermalMeter_92E(pDM_Odm); - return; - } -#endif - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; -#endif - - - u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, offset; - u1Byte ThermalValue_AVG_count = 0; - u4Byte ThermalValue_AVG = 0; -// s4Byte ele_A=0, ele_D, TempCCk, X, value32; -// s4Byte Y, ele_C=0; -// s1Byte OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index; -// s1Byte deltaPowerIndex = 0; - u4Byte i = 0;//, j = 0; - BOOLEAN is2T = FALSE; -// BOOLEAN bInteralPA = FALSE; - - u1Byte OFDM_max_index = 34, rf = (is2T) ? 2 : 1; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur - u1Byte Indexforchannel = 0;/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/ - enum _POWER_DEC_INC { POWER_DEC, POWER_INC }; - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif - - TXPWRTRACK_CFG c; - - - //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. - s1Byte deltaSwingTableIdx[2][index_mapping_NUM_88E] = { - // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} - {0,0,2,3,4,4,5,6,7,7,8,9,10,10,11}, {0,0,1,2,3,4,4,4,4,5,7,8,9,9,10} - }; - u1Byte thermalThreshold[2][index_mapping_NUM_88E]={ - // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} - {0,2,4,6,8,10,12,14,16,18,20,22,24,26,27}, {0,2,4,6,8,10,12,14,16,18,20,22,25,25,25} - }; - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - prtl8192cd_priv priv = pDM_Odm->priv; -#endif - - //4 2. Initilization ( 7 steps in total ) - - ConfigureTxpowerTrack(pDM_Odm, &c); - - pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug - pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE; - -#if (MP_DRIVER == 1) - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = pHalData->TxPowerTrackControl; // We should keep updating the control variable according to HalData. - // RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. - pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317; -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST) - if ((OPMODE & WIFI_MP_STATE) || pDM_Odm->priv->pshare->rf_ft_var.mp_specific) { - if(pDM_Odm->priv->pshare->mp_txpwr_tracking == FALSE) - return; - } -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>odm_TXPowerTrackingCallback_ThermalMeter_8188E, pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase: %d \n", pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase)); -/* - if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { - ODM_SetRFReg(pDM_Odm, RF_PATH_A, c.ThermalRegAddr, BIT17 | BIT16, 0x3); - pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; - return; - } -*/ - ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if( ! ThermalValue || ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) -#else - if( ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) -#endif - return; - - //4 3. Initialize ThermalValues of RFCalibrateInfo - - if( ! pDM_Odm->RFCalibrateInfo.ThermalValue) - { - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; - } - - if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); - } - - //4 4. Calculate average thermal meter - - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; - if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) - pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; - - for(i = 0; i < c.AverageThermalNum; i++) - { - if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) - { - ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; - ThermalValue_AVG_count++; - } - } - - if(ThermalValue_AVG_count) - { - // Give the new thermo value a weighting - ThermalValue_AVG += (ThermalValue*4); - - ThermalValue = (u1Byte)(ThermalValue_AVG / (ThermalValue_AVG_count+4)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue)); - } - - //4 5. Calculate delta, delta_LCK, delta_IQK. - - delta = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue):(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue); - delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue); - delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue); - - //4 6. If necessary, do LCK. - if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { - /*if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0))*/ - if (delta_LCK >= c.Threshold_IQK) { - /*Delta temperature is equal to or larger than 20 centigrade.*/ - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; - (*c.PHY_LCCalibrate)(pDM_Odm); - } - } - - //3 7. If necessary, move the index of swing table to adjust Tx power. - - if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) - { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); -#else - delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); -#endif - - - //4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(ThermalValue > pHalData->EEPROMThermalMeter) { -#else - if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { -#endif - CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta); - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex; - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = deltaSwingTableIdx[POWER_INC][offset]; - - } else { - - CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta); - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex; - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = (-1)*deltaSwingTableIdx[POWER_DEC][offset]; - } - - if (pDM_Odm->RFCalibrateInfo.DeltaPowerIndex == pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast) - pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; - else - pDM_Odm->RFCalibrateInfo.PowerIndexOffset = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast; - - for(i = 0; i < rf; i++) - pDM_Odm->RFCalibrateInfo.OFDM_index[i] = pRFCalibrateInfo->BbSwingIdxOfdmBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset; - pDM_Odm->RFCalibrateInfo.CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset; - - pRFCalibrateInfo->BbSwingIdxCck = pDM_Odm->RFCalibrateInfo.CCK_index; - pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A] = pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A]; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'OFDM' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A], pRFCalibrateInfo->BbSwingIdxOfdmBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset)); - - //4 7.1 Handle boundary conditions of index. - - - for(i = 0; i < rf; i++) - { - if(pDM_Odm->RFCalibrateInfo.OFDM_index[i] > OFDM_max_index) - { - pDM_Odm->RFCalibrateInfo.OFDM_index[i] = OFDM_max_index; - } - else if (pDM_Odm->RFCalibrateInfo.OFDM_index[i] < 0) - { - pDM_Odm->RFCalibrateInfo.OFDM_index[i] = 0; - } - } - - if(pDM_Odm->RFCalibrateInfo.CCK_index > c.SwingTableSize_CCK-1) - pDM_Odm->RFCalibrateInfo.CCK_index = c.SwingTableSize_CCK-1; - else if (pDM_Odm->RFCalibrateInfo.CCK_index < 0) - pDM_Odm->RFCalibrateInfo.CCK_index = 0; - } - else - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The thermal meter is unchanged or TxPowerTracking OFF: ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d)\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue)); - pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", pDM_Odm->RFCalibrateInfo.CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index: %d\n", pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A], pRFCalibrateInfo->BbSwingIdxOfdmBase)); - - if (pDM_Odm->RFCalibrateInfo.PowerIndexOffset != 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) - { - //4 7.2 Configure the Swing Table to adjust Tx Power. - - pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking. - // - // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital - // to increase TX power. Otherwise, EVM will be bad. - // - // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. - if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue) - { - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - // ("Temperature Increasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - // pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); - } - else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue)// Low temperature - { - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - // ("Temperature Decreasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - // pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); - } -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (ThermalValue > pHalData->EEPROMThermalMeter) -#else - if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) -#endif - { -// ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) hugher than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter)); - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TXAGC, 0, 0); - } - else - { - // ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) lower than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter)); - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, RF_PATH_A, Indexforchannel); - if(is2T) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, RF_PATH_B, Indexforchannel); - } - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; - pRFCalibrateInfo->BbSwingIdxOfdmBase = pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A]; - pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; - - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - // if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) - if ((delta_IQK >= 8)) // Delta temperature is equal to or larger than 20 centigrade. - (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8); -#endif - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n")); - - pDM_Odm->RFCalibrateInfo.TXPowercount = 0; -} - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - -VOID -phy_PathAStandBy( - IN PADAPTER pAdapter - ) -{ - RTPRINT(FINIT, INIT_IQK, ("Path-A standby mode!\n")); - - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x0); - PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000); - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x808000); -} - -//1 7. IQK -//#define MAX_TOLERANCE 5 -//#define IQK_DELAY_TIME 1 //ms - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathA_IQK_8192C( - IN PADAPTER pAdapter, - IN BOOLEAN configPathB - ) -{ - - u4Byte regEAC, regE94, regE9C, regEA4; - u1Byte result = 0x00; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n")); - - //path-A IQK setting - RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n")); - if(pAdapter->interfaceIndex == 0) - { - PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1f); - PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); - } - else - { - PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c22); - PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c22); - } - - PHY_SetBBReg(pAdapter, rTx_IQK_PI_A, bMaskDWord, 0x82140102); - - PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 : - IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502); - - //path-B IQK setting - if(configPathB) - { - PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22); - PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22); - PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102); - PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202); - } - - //LO calibration setting - RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n")); - PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1); - - //One shot, path A LOK & IQK - RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); - PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); - PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - - // delay x ms - RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME)); - PlatformStallExecution(IQK_DELAY_TIME*1000); - - // Check failed - regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); - regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94)); - regE9C= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C)); - regEA4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4)); - - if(!(regEAC & BIT28) && - (((regE94 & 0x03FF0000)>>16) != 0x142) && - (((regE9C & 0x03FF0000)>>16) != 0x42) ) - result |= 0x01; - else //if Tx not OK, ignore Rx - return result; - - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK - (((regEA4 & 0x03FF0000)>>16) != 0x132) && - (((regEAC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); - - return result; - - -} - -u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK -phy_PathB_IQK_8192C( - IN PADAPTER pAdapter - ) -{ - u4Byte regEAC, regEB4, regEBC, regEC4, regECC; - u1Byte result = 0x00; - RTPRINT(FINIT, INIT_IQK, ("Path B IQK!\n")); - - //One shot, path B LOK & IQK - RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); - PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000002); - PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000000); - - // delay x ms - RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME)); - PlatformStallExecution(IQK_DELAY_TIME*1000); - - // Check failed - regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); - regEB4 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regEB4)); - regEBC= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xebc = 0x%x\n", regEBC)); - regEC4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regEC4)); - regECC= PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord); - RTPRINT(FINIT, INIT_IQK, ("0xecc = 0x%x\n", regECC)); - - if(!(regEAC & BIT31) && - (((regEB4 & 0x03FF0000)>>16) != 0x142) && - (((regEBC & 0x03FF0000)>>16) != 0x42)) - result |= 0x01; - else - return result; - - if(!(regEAC & BIT30) && - (((regEC4 & 0x03FF0000)>>16) != 0x132) && - (((regECC & 0x03FF0000)>>16) != 0x36)) - result |= 0x02; - else - RTPRINT(FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n")); - - - return result; - -} - -VOID -phy_PathAFillIQKMatrix( - IN PADAPTER pAdapter, - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly - ) -{ - u4Byte Oldval_0, X, TX0_A, reg; - s4Byte Y, TX0_C; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - RTPRINT(FINIT, INIT_IQK, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_0 = (PHY_QueryBBReg(pAdapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][0]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX0_A = (X * Oldval_0) >> 8; - RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); - PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); - PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0>>7) & 0x1)); - - Y = result[final_candidate][1]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - - //path B IQK result + 3 - if(pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType == BAND_ON_5G) - Y += 3; - - TX0_C = (Y * Oldval_0) >> 8; - RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); - PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); - PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); - PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0>>7) & 0x1)); - - if(bTxOnly) - { - RTPRINT(FINIT, INIT_IQK, ("phy_PathAFillIQKMatrix only Tx OK\n")); - return; - } - - reg = result[final_candidate][2]; - PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][3] & 0x3F; - PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][3] >> 6) & 0xF; - PHY_SetBBReg(pAdapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg); - } -} - -VOID -phy_PathBFillIQKMatrix( - IN PADAPTER pAdapter, - IN BOOLEAN bIQKOK, - IN s4Byte result[][8], - IN u1Byte final_candidate, - IN BOOLEAN bTxOnly //do Tx only - ) -{ - u4Byte Oldval_1, X, TX1_A, reg; - s4Byte Y, TX1_C; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - RTPRINT(FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); - - if(final_candidate == 0xFF) - return; - - else if(bIQKOK) - { - Oldval_1 = (PHY_QueryBBReg(pAdapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; - - X = result[final_candidate][4]; - if ((X & 0x00000200) != 0) - X = X | 0xFFFFFC00; - TX1_A = (X * Oldval_1) >> 8; - RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); - PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); - PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1>>7) & 0x1)); - - Y = result[final_candidate][5]; - if ((Y & 0x00000200) != 0) - Y = Y | 0xFFFFFC00; - if(pHalData->CurrentBandType == BAND_ON_5G) - Y += 3; //temp modify for preformance - TX1_C = (Y * Oldval_1) >> 8; - RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); - PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); - PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); - PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1>>7) & 0x1)); - - if(bTxOnly) - return; - - reg = result[final_candidate][6]; - PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg); - - reg = result[final_candidate][7] & 0x3F; - PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg); - - reg = (result[final_candidate][7] >> 6) & 0xF; - PHY_SetBBReg(pAdapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); - } -} - - -BOOLEAN -phy_SimularityCompare_92C( - IN PADAPTER pAdapter, - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 - ) -{ - u4Byte i, j, diff, SimularityBitMap, bound = 0; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B - BOOLEAN bResult = TRUE, is2T = IS_92C_SERIAL( pHalData->VersionID); - - if(is2T) - bound = 8; - else - bound = 4; - - SimularityBitMap = 0; - - for( i = 0; i < bound; i++ ) - { - diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); - if (diff > MAX_TOLERANCE) - { - if((i == 2 || i == 6) && !SimularityBitMap) - { - if(result[c1][i]+result[c1][i+1] == 0) - final_candidate[(i/4)] = c2; - else if (result[c2][i]+result[c2][i+1] == 0) - final_candidate[(i/4)] = c1; - else - SimularityBitMap = SimularityBitMap|(1< do IQK again -*/ -BOOLEAN -phy_SimularityCompare( - IN PADAPTER pAdapter, - IN s4Byte result[][8], - IN u1Byte c1, - IN u1Byte c2 - ) -{ - return phy_SimularityCompare_92C(pAdapter, result, c1, c2); - -} - -VOID -phy_IQCalibrate_8192C( - IN PADAPTER pAdapter, - IN s4Byte result[][8], - IN u1Byte t, - IN BOOLEAN is2T - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u4Byte i; - u1Byte PathAOK, PathBOK; - u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - //since 92C & 92D have the different define in IQK_BB_REG - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, /*rFPGA0_RFMOD*/ rCCK0_AFESetting - }; - - u4Byte IQK_BB_REG_92D[IQK_BB_REG_NUM_92D] = { //for normal - rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, - rFPGA0_XB_RFInterfaceOE, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rOFDM0_TRxPathEnable, - /*rFPGA0_RFMOD*/ rCCK0_AFESetting, rFPGA0_AnalogParameter4, - rOFDM0_XAAGCCore1, rOFDM0_XBAGCCore1 - }; -#if MP_DRIVER - const u4Byte retryCount = 9; -#else - const u4Byte retryCount = 2; -#endif - //Neil Chen--2011--05--19-- - //3 Path Div - u1Byte rfPathSwitch=0x0; - - // Note: IQ calibration must be performed after loading - // PHY_REG.txt , and radio_a, radio_b.txt - - u4Byte bbvalue; - - if(t==0) - { - //bbvalue = PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bMaskDWord); - // RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C()==>0x%08x\n",bbvalue)); - - RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - - // Save ADDA parameters, turn Path A ADDA on - phy_SaveADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM); - phy_SaveMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); - phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM); - } - - phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); - - if(t==0) - { - pHalData->bRfPiEnable = (u1Byte)PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, BIT(8)); - } - - if(!pHalData->bRfPiEnable){ - // Switch BB to PI mode to do IQ Calibration. - phy_PIModeSwitch(pAdapter, TRUE); - } - - //MAC settings - phy_MACSettingCalibration(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); - - //PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT24, 0x00); - PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskDWord, (0x0f000000 | (PHY_QueryBBReg(pAdapter, rCCK0_AFESetting, bMaskDWord))) ); - PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); - PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); - PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); - { - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); - PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); - PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); - } - - if(is2T) - { - PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); - PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); - } - - { - //Page B init - PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000); - - if(is2T) - { - PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000); - } - } - // IQ calibration setting - RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n")); - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x808000); - PHY_SetBBReg(pAdapter, rTx_IQK, bMaskDWord, 0x01007c00); - PHY_SetBBReg(pAdapter, rRx_IQK, bMaskDWord, 0x01004800); - - for(i = 0 ; i < retryCount ; i++){ - PathAOK = phy_PathA_IQK_8192C(pAdapter, is2T); - if(PathAOK == 0x03){ - RTPRINT(FINIT, INIT_IQK, ("Path A IQK Success!!\n")); - result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][2] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - result[t][3] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK - { - RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); - - result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; - result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; - } - } - - if(0x00 == PathAOK){ - RTPRINT(FINIT, INIT_IQK, ("Path A IQK failed!!\n")); - } - - if(is2T){ - phy_PathAStandBy(pAdapter); - - // Turn Path B ADDA on - phy_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); - - for(i = 0 ; i < retryCount ; i++){ - PathBOK = phy_PathB_IQK_8192C(pAdapter); - if(PathBOK == 0x03){ - RTPRINT(FINIT, INIT_IQK, ("Path B IQK Success!!\n")); - result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][6] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; - result[t][7] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; - break; - } - else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK - { - RTPRINT(FINIT, INIT_IQK, ("Path B Only Tx IQK Success!!\n")); - result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; - result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; - } - } - - if(0x00 == PathBOK){ - RTPRINT(FINIT, INIT_IQK, ("Path B IQK failed!!\n")); - } - } - - //Back to BB mode, load original value - RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n")); - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); - - if(t!=0) - { - if(!pHalData->bRfPiEnable){ - // Switch back BB to SI mode after finish IQ Calibration. - phy_PIModeSwitch(pAdapter, FALSE); - } - - // Reload ADDA power saving parameters - phy_ReloadADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM); - - // Reload MAC parameters - phy_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); - - // Reload BB parameters - phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM); - - /*Restore RX initial gain*/ - PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); - if (is2T) - PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); - //load 0xe30 IQC default value - PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - - } - RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C() <==\n")); - -} - - -VOID -phy_LCCalibrate92C( - IN PADAPTER pAdapter, - IN BOOLEAN is2T - ) -{ - u1Byte tmpReg; - u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; -// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - //Check continuous TX and Packet TX - tmpReg = PlatformEFIORead1Byte(pAdapter, 0xd03); - - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg&0x8F); //disable all continuous TX - else // Deal with Packet TX case - PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0xFF); // block all queues - - if((tmpReg&0x70) != 0) - { - //1. Read original RF mode - //Path-A - RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits); - - //Path-B - if(is2T) - RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits); - - //2. Set RF mode = standby mode - //Path-A - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); - - //Path-B - if(is2T) - PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); - } - - //3. Read RF reg18 - LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); - - //4. Set LC calibration begin bit15 - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); - - delay_ms(100); - - - //Restore original situation - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - { - //Path-A - PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg); - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - - //Path-B - if(is2T) - PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); - } - else // Deal with Packet TX case - { - PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0x00); - } -} - - -VOID -phy_LCCalibrate( - IN PADAPTER pAdapter, - IN BOOLEAN is2T - ) -{ - phy_LCCalibrate92C(pAdapter, is2T); -} - - - -//Analog Pre-distortion calibration -#define APK_BB_REG_NUM 8 -#define APK_CURVE_REG_NUM 4 -#define PATH_NUM 2 - -VOID -phy_APCalibrate_8192C( - IN PADAPTER pAdapter, - IN s1Byte delta, - IN BOOLEAN is2T - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - u4Byte regD[PATH_NUM]; - u4Byte tmpReg, index, offset, i, apkbound; - u1Byte path, pathbound = PATH_NUM; - u4Byte BB_backup[APK_BB_REG_NUM]; - u4Byte BB_REG[APK_BB_REG_NUM] = { - rFPGA1_TxBlock, rOFDM0_TRxPathEnable, - rFPGA0_RFMOD, rOFDM0_TRMuxPar, - rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, - rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; - u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x00204000 }; - u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { - 0x00000020, 0x00a05430, 0x02040000, - 0x000800e4, 0x22204000 }; - - u4Byte AFE_backup[IQK_ADDA_REG_NUM]; - u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { - rFPGA0_XCD_SwitchControl, rBlue_Tooth, - rRx_Wait_CCA, rTx_CCK_RFON, - rTx_CCK_BBON, rTx_OFDM_RFON, - rTx_OFDM_BBON, rTx_To_Rx, - rTx_To_Tx, rRx_CCK, - rRx_OFDM, rRx_Wait_RIFS, - rRx_TO_Rx, rStandby, - rSleep, rPMPD_ANAEN }; - - u4Byte MAC_backup[IQK_MAC_REG_NUM]; - u4Byte MAC_REG[IQK_MAC_REG_NUM] = { - REG_TXPAUSE, REG_BCN_CTRL, - REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - - u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, - {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} - }; - - u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings - {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} - }; - - u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, - {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} - }; - - u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} - }; -#if 0 - u4Byte APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = { - {0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80}, - {0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80} - }; -#endif - u4Byte AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on - - u4Byte APK_offset[PATH_NUM] = { - rConfig_AntA, rConfig_AntB}; - - u4Byte APK_normal_offset[PATH_NUM] = { - rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; - - u4Byte APK_value[PATH_NUM] = { - 0x92fc0000, 0x12fc0000}; - - u4Byte APK_normal_value[PATH_NUM] = { - 0x92680000, 0x12680000}; - - s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, - {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} - }; - - u4Byte APK_normal_setting_value_1[13] = { - 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, - 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, - 0x12680000, 0x00880000, 0x00880000 - }; - - u4Byte APK_normal_setting_value_2[16] = { - 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, - 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, - 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, - 0x00050006 - }; - - u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a -// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; - - s4Byte BB_offset, delta_V, delta_offset; - -#if MP_DRIVER == 1 - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - - pMptCtx->APK_bound[0] = 45; - pMptCtx->APK_bound[1] = 52; -#endif - - RTPRINT(FINIT, INIT_IQK, ("==>phy_APCalibrate_8192C() delta %d\n", delta)); - RTPRINT(FINIT, INIT_IQK, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); - if(!is2T) - pathbound = 1; - - //2 FOR NORMAL CHIP SETTINGS - -// Temporarily do not allow normal driver to do the following settings because these offset -// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal -// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the -// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. -#if MP_DRIVER != 1 - return; -#endif - //settings adjust for normal chip - for(index = 0; index < PATH_NUM; index ++) - { - APK_offset[index] = APK_normal_offset[index]; - APK_value[index] = APK_normal_value[index]; - AFE_on_off[index] = 0x6fdb25a4; - } - - for(index = 0; index < APK_BB_REG_NUM; index ++) - { - for(path = 0; path < pathbound; path++) - { - APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; - APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; - } - BB_AP_MODE[index] = BB_normal_AP_MODE[index]; - } - - apkbound = 6; - - //save BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - if(index == 0) //skip - continue; - BB_backup[index] = PHY_QueryBBReg(pAdapter, BB_REG[index], bMaskDWord); - } - - //save MAC default value - phy_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); - - //save AFE default value - phy_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - for(path = 0; path < pathbound; path++) - { - - - if(path == RF_PATH_A) - { - //path A APK - //load APK setting - //path-A - offset = rPdp_AntA; - for(index = 0; index < 11; index ++) - { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); - - offset += 0x04; - } - - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - for(; index < 13; index ++) - { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path A - offset = rPdp_AntA; - for(index = 0; index < 16; index++) - { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); - - offset += 0x04; - } - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); - } - else if(path == RF_PATH_B) - { - //path B APK - //load APK setting - //path-B - offset = rPdp_AntB; - for(index = 0; index < 10; index ++) - { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); - - offset += 0x04; - } - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); - - PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); - - offset = rConfig_AntA; - index = 11; - for(; index < 13; index ++) //offset 0xb68, 0xb6c - { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); - - offset += 0x04; - } - - //page-B1 - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x400000); - - //path B - offset = 0xb60; - for(index = 0; index < 16; index++) - { - PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); - - offset += 0x04; - } - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); - } - - //save RF default value - regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask); - - //Path A AFE all on, path B AFE All off or vise versa - for(index = 0; index < IQK_ADDA_REG_NUM ; index++) - PHY_SetBBReg(pAdapter, AFE_REG[index], bMaskDWord, AFE_on_off[path]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xe70 %x\n", PHY_QueryBBReg(pAdapter, rRx_Wait_CCA, bMaskDWord))); - - //BB to AP mode - if(path == 0) - { - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - else if (index < 5) - PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); - else if (BB_REG[index] == 0x870) - PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); - else - PHY_SetBBReg(pAdapter, BB_REG[index], BIT10, 0x0); - } - - PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); - PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); - } - else //path B - { - PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); - PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); - - } - - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x800 %x\n", PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord))); - - //MAC settings - phy_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); - - if(path == RF_PATH_A) //Path B to standby mode - { - PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bRFRegOffsetMask, 0x10000); - } - else //Path A to standby mode - { - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x10000); - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f); - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20103); - } - - delta_offset = ((delta+14)/2); - if(delta_offset < 0) - delta_offset = 0; - else if (delta_offset > 12) - delta_offset = 12; - - //AP calibration - for(index = 0; index < APK_BB_REG_NUM; index++) - { - if(index != 1) //only DO PA11+PAD01001, AP RF setting - continue; - - tmpReg = APK_RF_init_value[path][index]; -#if 1 - if(!pHalData->bAPKThermalMeterIgnore) - { - BB_offset = (tmpReg & 0xF0000) >> 16; - - if(!(tmpReg & BIT15)) //sign bit 0 - { - BB_offset = -BB_offset; - } - - delta_V = APK_delta_mapping[index][delta_offset]; - - BB_offset += delta_V; - - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); - - if(BB_offset < 0) - { - tmpReg = tmpReg & (~BIT15); - BB_offset = -BB_offset; - } - else - { - tmpReg = tmpReg | BIT15; - } - tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); - } -#endif - -#if DEV_BUS_TYPE==RT_PCI_INTERFACE - if(IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)) - PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x894ae); - else -#endif - PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x8992e); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask))); - PHY_SetRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask, APK_RF_value_0[path][index]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask))); - PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, tmpReg); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask))); - - // PA11+PAD01111, one shot - i = 0; - do - { - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x800000); - { - PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[0]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); - delay_ms(3); - PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[1]); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); - - delay_ms(20); - } - PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); - - if(path == RF_PATH_A) - tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0x03E00000); - else - tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0xF8000000); - RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xbd8[25:21] %x\n", tmpReg)); - - - i++; - } - while(tmpReg > apkbound && i < 4); - - APK_result[path][index] = tmpReg; - } - } - - //reload MAC default value - phy_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); - - //reload BB default value - for(index = 0; index < APK_BB_REG_NUM ; index++) - { - - if(index == 0) //skip - continue; - PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]); - } - - //reload AFE default value - phy_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - - //reload RF path default value - for(path = 0; path < pathbound; path++) - { - PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, regD[path]); - if(path == RF_PATH_B) - { - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f); - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20101); - } - - //note no index == 0 - if (APK_result[path][1] > 6) - APK_result[path][1] = 6; - RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); - } - - RTPRINT(FINIT, INIT_IQK, ("\n")); - - - for(path = 0; path < pathbound; path++) - { - PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G1_G4, bRFRegOffsetMask, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); - if(path == RF_PATH_A) - PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); - else - PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask, - ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); - - PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G9_G11, bRFRegOffsetMask, ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); - } - - pHalData->bAPKdone = TRUE; - - RTPRINT(FINIT, INIT_IQK, ("<==phy_APCalibrate_8192C()\n")); -} - - -VOID -PHY_IQCalibrate_8192C( - IN PADAPTER pAdapter, - IN BOOLEAN bReCovery - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - s4Byte result[4][8]; //last is final result - u1Byte i, final_candidate, Indexforchannel; - BOOLEAN bPathAOK, bPathBOK; - s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; - BOOLEAN is12simular, is13simular, is23simular; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { - rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, - rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, - rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, - rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, - rOFDM0_RxIQExtAnta}; - - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; - -#if MP_DRIVER == 1 - bStartContTx = pAdapter->MptCtx.bStartContTx; - bSingleTone = pAdapter->MptCtx.bSingleTone; - bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression; -#endif - - //ignore IQK when continuous Tx - if(bStartContTx || bSingleTone || bCarrierSuppression) - return; - -#ifdef DISABLE_BB_RF - return; -#endif - if(pAdapter->bSlaveOfDMSP) - return; - - if (bReCovery) - { - phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9); - return; - - } - - RTPRINT(FINIT, INIT_IQK, ("IQK:Start!!!\n")); - - for(i = 0; i < 8; i++) - { - result[0][i] = 0; - result[1][i] = 0; - result[2][i] = 0; - result[3][i] = 0; - } - final_candidate = 0xff; - bPathAOK = FALSE; - bPathBOK = FALSE; - is12simular = FALSE; - is23simular = FALSE; - is13simular = FALSE; - - AcquireCCKAndRWPageAControl(pAdapter); - /*RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate\n"));*/ - for (i=0; i<3; i++) - { - /*For 88C 1T1R*/ - phy_IQCalibrate_8192C(pAdapter, result, i, FALSE); - - if(i == 1) - { - is12simular = phy_SimularityCompare(pAdapter, result, 0, 1); - if(is12simular) - { - final_candidate = 0; - break; - } - } - - if(i == 2) - { - is13simular = phy_SimularityCompare(pAdapter, result, 0, 2); - if(is13simular) - { - final_candidate = 0; - break; - } - - is23simular = phy_SimularityCompare(pAdapter, result, 1, 2); - if(is23simular) - final_candidate = 1; - else - { - for(i = 0; i < 8; i++) - RegTmp += result[3][i]; - - if(RegTmp != 0) - final_candidate = 3; - else - final_candidate = 0xFF; - } - } - } -// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); - ReleaseCCKAndRWPageAControl(pAdapter); - - for (i=0; i<4; i++) - { - RegE94 = result[i][0]; - RegE9C = result[i][1]; - RegEA4 = result[i][2]; - RegEAC = result[i][3]; - RegEB4 = result[i][4]; - RegEBC = result[i][5]; - RegEC4 = result[i][6]; - RegECC = result[i][7]; - RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - } - - if(final_candidate != 0xff) - { - pHalData->RegE94 = RegE94 = result[final_candidate][0]; - pHalData->RegE9C = RegE9C = result[final_candidate][1]; - RegEA4 = result[final_candidate][2]; - RegEAC = result[final_candidate][3]; - pHalData->RegEB4 = RegEB4 = result[final_candidate][4]; - pHalData->RegEBC = RegEBC = result[final_candidate][5]; - RegEC4 = result[final_candidate][6]; - RegECC = result[final_candidate][7]; - RTPRINT(FINIT, INIT_IQK, ("IQK: final_candidate is %x\n",final_candidate)); - RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); - bPathAOK = bPathBOK = TRUE; - } - else - { - RegE94 = RegEB4 = pHalData->RegE94 = pHalData->RegEB4 = 0x100; //X default value - RegE9C = RegEBC = pHalData->RegE9C = pHalData->RegEBC = 0x0; //Y default value - } - - if((RegE94 != 0)/*&&(RegEA4 != 0)*/) - { - if(pHalData->CurrentBandType == BAND_ON_5G) - phy_PathAFillIQKMatrix_5G_Normal(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); - else - phy_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); - - } - - if (IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID)) - { - if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) - { - if(pHalData->CurrentBandType == BAND_ON_5G) - phy_PathBFillIQKMatrix_5G_Normal(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); - else - phy_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); - } - } - - phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9); - -} - - -VOID -PHY_LCCalibrate_8192C( - IN PADAPTER pAdapter - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - PMGNT_INFO pMgntInfo=&pAdapter->MgntInfo; - PMGNT_INFO pMgntInfoBuddyAdapter; - u4Byte timeout = 2000, timecount = 0; - PADAPTER BuddyAdapter = pAdapter->BuddyAdapter; - -#if MP_DRIVER == 1 - bStartContTx = pAdapter->MptCtx.bStartContTx; - bSingleTone = pAdapter->MptCtx.bSingleTone; - bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression; -#endif - -#ifdef DISABLE_BB_RF - return; -#endif - - //ignore LCK when continuous Tx - if(bStartContTx || bSingleTone || bCarrierSuppression) - return; - - if(BuddyAdapter != NULL && - ((pAdapter->interfaceIndex == 0 && pHalData->CurrentBandType == BAND_ON_2_4G) || - (pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType == BAND_ON_5G))) - { - pMgntInfoBuddyAdapter=&BuddyAdapter->MgntInfo; - while(pMgntInfoBuddyAdapter->bScanInProgress && timecount < timeout) - { - delay_ms(50); - timecount += 50; - } - } - - while(pMgntInfo->bScanInProgress && timecount < timeout) - { - delay_ms(50); - timecount += 50; - } - - pHalData->bLCKInProgress = TRUE; - - RTPRINT(FINIT, INIT_IQK, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pAdapter->interfaceIndex, pHalData->CurrentBandType, timecount)); - - //if(IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID)) - if(IS_2T2R(pHalData->VersionID)) - { - phy_LCCalibrate(pAdapter, TRUE); - } - else{ - // For 88C 1T1R - phy_LCCalibrate(pAdapter, FALSE); - } - - pHalData->bLCKInProgress = FALSE; - - RTPRINT(FINIT, INIT_IQK, ("LCK:Finish!!!interface %d\n", pAdapter->interfaceIndex)); - - -} - -VOID -PHY_APCalibrate_8192C( - IN PADAPTER pAdapter, - IN s1Byte delta - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - //default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25 - return; - -#ifdef DISABLE_BB_RF - return; -#endif - -#if FOR_BRAZIL_PRETEST != 1 - if(pHalData->bAPKdone) -#endif - return; - - if(IS_92C_SERIAL( pHalData->VersionID)){ - phy_APCalibrate_8192C(pAdapter, delta, TRUE); - } - else{ - // For 88C 1T1R - phy_APCalibrate_8192C(pAdapter, delta, FALSE); - } -} - - -#endif - - -//3============================================================ -//3 IQ Calibration -//3============================================================ - -VOID -ODM_ResetIQKResult( - IN PVOID pDM_VOID -) -{ - return; -} -#if 1//!(DM_ODM_SUPPORT_TYPE & ODM_AP) -u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) -{ - u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = - {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; - u1Byte place = chnl; - - - if(chnl > 14) - { - for(place = 14; placeAdapter; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (*pDM_Odm->pIsFcsModeEnable) - return; -#endif - - - - if (pDM_Odm->bLinked) { - if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) { - pDM_Odm->preChannel = *pDM_Odm->pChannel; - pDM_Odm->LinkedInterval = 0; - } - - if (pDM_Odm->LinkedInterval < 3) - pDM_Odm->LinkedInterval++; - - if (pDM_Odm->LinkedInterval == 2) { - - #if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8814A) - PHY_IQCalibrate_8814A(pDM_Odm, FALSE); - #endif - - #if (RTL8822B_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8822B) - PHY_IQCalibrate_8822B(pDM_Odm, FALSE); - #endif - - #if (RTL8821C_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821C) - PHY_IQCalibrate_8821C(pDM_Odm, FALSE); - #endif - - #if (RTL8821A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8821) - PHY_IQCalibrate_8821A(pDM_Odm, FALSE); - #endif - - #if (RTL8812A_SUPPORT == 1) - if (pDM_Odm->SupportICType == ODM_RTL8812) - phy_IQCalibrate_8812A(pDM_Odm, FALSE); - #endif - } - } else - pDM_Odm->LinkedInterval = 0; - -} - -void phydm_rf_init(IN PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - odm_TXPowerTrackingInit(pDM_Odm); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - ODM_ClearTxPowerTrackingState(pDM_Odm); -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8814A) - PHY_IQCalibrate_8814A_Init(pDM_Odm); -#endif -#endif - -} - -void phydm_rf_watchdog(IN PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - ODM_TXPowerTrackingCheck(pDM_Odm); - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - odm_IQCalibrate(pDM_Odm); -#endif -} diff --git a/hal/phydm/halphyrf_ap.h b/hal/phydm/halphyrf_ap.h deleted file mode 100644 index 8281e55..0000000 --- a/hal/phydm/halphyrf_ap.h +++ /dev/null @@ -1,179 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - #ifndef __HAL_PHY_RF_H__ - #define __HAL_PHY_RF_H__ - -#include "phydm_powertracking_ap.h" -#if (RTL8814A_SUPPORT == 1) -#include "rtl8814a/phydm_iqk_8814a.h" -#endif - -#if (RTL8822B_SUPPORT == 1) -#include "rtl8822b/phydm_iqk_8822b.h" -#endif - -#if (RTL8821C_SUPPORT == 1) -#include "rtl8822b/phydm_iqk_8821c.h" -#endif - -typedef enum _PWRTRACK_CONTROL_METHOD { - BBSWING, - TXAGC, - MIX_MODE, - TSSI_MODE -} PWRTRACK_METHOD; - -typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); -typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); -typedef VOID (*FuncLCK)(PVOID); - //refine by YuChen for 8814A -typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); -typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); -typedef VOID (*FuncAllSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); - - -typedef struct _TXPWRTRACK_CFG { - u1Byte SwingTableSize_CCK; - u1Byte SwingTableSize_OFDM; - u1Byte Threshold_IQK; - u1Byte Threshold_DPK; - u1Byte AverageThermalNum; - u1Byte RfPathCount; - u4Byte ThermalRegAddr; - FuncSetPwr ODM_TxPwrTrackSetPwr; - FuncIQK DoIQK; - FuncLCK PHY_LCCalibrate; - FuncSwing GetDeltaSwingTable; - FuncSwing8814only GetDeltaSwingTable8814only; - FuncAllSwing GetDeltaAllSwingTable; -} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; - -VOID -ConfigureTxpowerTrack( - IN PVOID pDM_VOID, - OUT PTXPWRTRACK_CFG pConfig - ); - - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ); - -#if (RTL8192E_SUPPORT==1) -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_92E( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ); -#endif - -#if (RTL8814A_SUPPORT == 1) -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ); - -#elif ODM_IC_11AC_SERIES_SUPPORT -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ); - -#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) -VOID -ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ); - -#endif - -#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M ) - - -#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) -#define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms - - // -// BB/MAC/RF other monitor API -// - -void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter, - IN BOOLEAN bEnableMonitorMode ); - -// -// IQ calibrate -// -void -PHY_IQCalibrate_8192C( IN PADAPTER pAdapter, - IN BOOLEAN bReCovery); - -// -// LC calibrate -// -void -PHY_LCCalibrate_8192C( IN PADAPTER pAdapter); - -// -// AP calibrate -// -void -PHY_APCalibrate_8192C( IN PADAPTER pAdapter, - IN s1Byte delta); -#endif - -#define ODM_TARGET_CHNL_NUM_2G_5G 59 - - -VOID -ODM_ResetIQKResult( - IN PVOID pDM_VOID -); -u1Byte -ODM_GetRightChnlPlaceforIQK( - IN u1Byte chnl -); - -void phydm_rf_init(IN PVOID pDM_VOID); -void phydm_rf_watchdog(IN PVOID pDM_VOID); - -#endif // #ifndef __HAL_PHY_RF_H__ - diff --git a/hal/phydm/halphyrf_ce.c b/hal/phydm/halphyrf_ce.c deleted file mode 100644 index 8b7322e..0000000 --- a/hal/phydm/halphyrf_ce.c +++ /dev/null @@ -1,801 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ - do {\ - for(_offset = 0; _offset < _size; _offset++)\ - {\ - if(_deltaThermal < thermalThreshold[_direction][_offset])\ - {\ - if(_offset != 0)\ - _offset--;\ - break;\ - }\ - } \ - if(_offset >= _size)\ - _offset = _size-1;\ - } while(0) - -void ConfigureTxpowerTrack( - IN PVOID pDM_VOID, - OUT PTXPWRTRACK_CFG pConfig - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - -#if RTL8192E_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8192E) - ConfigureTxpowerTrack_8192E(pConfig); -#endif -#if RTL8821A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8821) - ConfigureTxpowerTrack_8821A(pConfig); -#endif -#if RTL8812A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8812) - ConfigureTxpowerTrack_8812A(pConfig); -#endif -#if RTL8188E_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8188E) - ConfigureTxpowerTrack_8188E(pConfig); -#endif - -#if RTL8723B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8723B) - ConfigureTxpowerTrack_8723B(pConfig); -#endif - -#if RTL8814A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8814A) - ConfigureTxpowerTrack_8814A(pConfig); -#endif - -#if RTL8703B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8703B) - ConfigureTxpowerTrack_8703B(pConfig); -#endif - -#if RTL8188F_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8188F) - ConfigureTxpowerTrack_8188F(pConfig); -#endif -#if RTL8723D_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8723D) - ConfigureTxpowerTrack_8723D(pConfig); -#endif -#if RTL8822B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8822B) - ConfigureTxpowerTrack_8822B(pConfig); -#endif - -} - -//====================================================================== -// <20121113, Kordan> This function should be called when TxAGC changed. -// Otherwise the previous compensation is gone, because we record the -// delta of temperature between two TxPowerTracking watch dogs. -// -// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still -// need to call this function. -//====================================================================== -VOID -ODM_ClearTxPowerTrackingState( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter); - u1Byte p = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; - pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex; - pDM_Odm->RFCalibrateInfo.CCK_index = 0; - - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) - { - pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; - - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - pRFCalibrateInfo->DeltaPowerIndex[p] = 0; - pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = 0; /* Initial Mix mode power tracking*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[p] = 0; - pRFCalibrateInfo->KfreeOffset[p] = 0; - } - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathC = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathD = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; - - pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //modify by Mingzhi.Guo - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //modify by Mingzhi.Guo - -} - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER Adapter -#endif - ) -{ - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif -#endif - - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; - s1Byte diff_DPK[4] = {0}; - u1Byte ThermalValue_AVG_count = 0; - u4Byte ThermalValue_AVG = 0, RegC80, RegCd0, RegCd4, Regab4; - - u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur - u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel) - u1Byte PowerTrackingType = pHalData->RfPowerTrackingType; - u1Byte XtalOffsetEanble = 0; - - TXPWRTRACK_CFG c; - - //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. - pu1Byte deltaSwingTableIdx_TUP_A = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_A = NULL; - pu1Byte deltaSwingTableIdx_TUP_B = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_B = NULL; - /*for 8814 add by Yu Chen*/ - pu1Byte deltaSwingTableIdx_TUP_C = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_C = NULL; - pu1Byte deltaSwingTableIdx_TUP_D = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_D = NULL; - /*for Xtal Offset by James.Tung*/ - ps1Byte deltaSwingTableXtal_UP = NULL; - ps1Byte deltaSwingTableXtal_DOWN = NULL; - - //4 2. Initilization ( 7 steps in total ) - - ConfigureTxpowerTrack(pDM_Odm, &c); - - (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A, - (pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B); - - if (pDM_Odm->SupportICType & ODM_RTL8814A) /*for 8814 path C & D*/ - (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_C, (pu1Byte *)&deltaSwingTableIdx_TDOWN_C, - (pu1Byte *)&deltaSwingTableIdx_TUP_D, (pu1Byte *)&deltaSwingTableIdx_TDOWN_D); - - if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/ - (*c.GetDeltaSwingXtalTable)(pDM_Odm, (ps1Byte *)&deltaSwingTableXtal_UP, (ps1Byte *)&deltaSwingTableXtal_DOWN); - - pRFCalibrateInfo->TXPowerTrackingCallbackCnt++; /*cosa add for debug*/ - pRFCalibrateInfo->bTXPowerTrackingInit = TRUE; - - /*pRFCalibrateInfo->TxPowerTrackControl = pHalData->TxPowerTrackControl; - We should keep updating the control variable according to HalData. - RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */ - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - pRFCalibrateInfo->RegA24 = 0x090e1317; - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->mp_mode == TRUE) - pRFCalibrateInfo->RegA24 = 0x090e1317; - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("===>ODM_TXPowerTrackingCallback_ThermalMeter\n pRFCalibrateInfo->BbSwingIdxCckBase: %d, pRFCalibrateInfo->BbSwingIdxOfdmBase[A]: %d, pRFCalibrateInfo->DefaultOfdmIndex: %d\n", - pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pRFCalibrateInfo->DefaultOfdmIndex)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->TxPowerTrackControl=%d, pHalData->EEPROMThermalMeter %d\n", pRFCalibrateInfo->TxPowerTrackControl, pHalData->EEPROMThermalMeter)); - ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E - - /*add log by zhao he, check c80/c94/c14/ca0 value*/ - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - RegC80 = ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord); - RegCd0 = ODM_GetBBReg(pDM_Odm, 0xcd0, bMaskDWord); - RegCd4 = ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord); - Regab4 = ODM_GetBBReg(pDM_Odm, 0xab4, 0x000007FF); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", RegC80, RegCd0, RegCd4, Regab4)); - } - - if (!pRFCalibrateInfo->TxPowerTrackControl) - return; - - - /*4 3. Initialize ThermalValues of RFCalibrateInfo*/ - - if (pRFCalibrateInfo->bReloadtxpowerindex) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); - - /*4 4. Calculate average thermal meter*/ - - pRFCalibrateInfo->ThermalValue_AVG[pRFCalibrateInfo->ThermalValue_AVG_index] = ThermalValue; - pRFCalibrateInfo->ThermalValue_AVG_index++; - if (pRFCalibrateInfo->ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/ - pRFCalibrateInfo->ThermalValue_AVG_index = 0; - - for(i = 0; i < c.AverageThermalNum; i++) - { - if (pRFCalibrateInfo->ThermalValue_AVG[i]) { - ThermalValue_AVG += pRFCalibrateInfo->ThermalValue_AVG[i]; - ThermalValue_AVG_count++; - } - } - - if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times - { - ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter)); - } - - //4 5. Calculate delta, delta_LCK, delta_IQK. - - //"delta" here is used to determine whether thermal value changes or not. - delta = (ThermalValue > pRFCalibrateInfo->ThermalValue)?(ThermalValue - pRFCalibrateInfo->ThermalValue):(pRFCalibrateInfo->ThermalValue - ThermalValue); - delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); - delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); - - if (pRFCalibrateInfo->ThermalValue_IQK == 0xff) { /*no PG, use thermal value for IQK*/ - pRFCalibrateInfo->ThermalValue_IQK = ThermalValue; - delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use ThermalValue for IQK\n")); - } - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - diff_DPK[p] = (s1Byte)ThermalValue - (s1Byte)pRFCalibrateInfo->DpkThermal[p]; - - /*4 6. If necessary, do LCK.*/ - - if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { /*no PG , do LCK at initial status*/ - if (pRFCalibrateInfo->ThermalValue_LCK == 0xff) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); - pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; - - /*Use RTLCK, so close power tracking driver LCK*/ - if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { - if (c.PHY_LCCalibrate) - (*c.PHY_LCCalibrate)(pDM_Odm); - } - - delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); - - /* Delta temperature is equal to or larger than 20 centigrade.*/ - if (delta_LCK >= c.Threshold_IQK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); - pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; - - /*Use RTLCK, so close power tracking driver LCK*/ - if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { - if (c.PHY_LCCalibrate) - (*c.PHY_LCCalibrate)(pDM_Odm); - } - } - } - - /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ - - if (delta > 0 && pRFCalibrateInfo->TxPowerTrackControl) - { - //"delta" here is used to record the absolute value of differrence. -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); -#else - delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); -#endif - if (delta >= TXPWR_TRACK_TABLE_SIZE) - delta = TXPWR_TRACK_TABLE_SIZE - 1; - - /*4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(ThermalValue > pHalData->EEPROMThermalMeter) { -#else - if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { -#endif - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/ - switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_B[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_C[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_D[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_A[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - } - } - - if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) { - /*Save XtalOffset from Xtal table*/ - pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Xtal] deltaSwingTableXtal_UP[%d] = %d\n", delta, deltaSwingTableXtal_UP[delta])); - pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_UP[delta]; - - if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset) - XtalOffsetEanble = 0; - else - XtalOffsetEanble = 1; - } - - } else { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/ - - switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - } - } - - if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) { - /*Save XtalOffset from Xtal table*/ - pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Xtal] deltaSwingTableXtal_DOWN[%d] = %d\n", delta, deltaSwingTableXtal_DOWN[delta])); - pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_DOWN[delta]; - - if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset) - XtalOffsetEanble = 0; - else - XtalOffsetEanble = 1; - } - - } - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n=========================== [Path-%d] Calculating PowerIndexOffset===========================\n", p)); - - if (pRFCalibrateInfo->DeltaPowerIndex[p] == pRFCalibrateInfo->DeltaPowerIndexLast[p]) /*If Thermal value changes but lookup table value still the same*/ - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - else - pRFCalibrateInfo->PowerIndexOffset[p] = pRFCalibrateInfo->DeltaPowerIndex[p] - pRFCalibrateInfo->DeltaPowerIndexLast[p]; /*Power Index Diff between 2 times Power Tracking*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Path-%d] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n", p, pRFCalibrateInfo->PowerIndexOffset[p], pRFCalibrateInfo->DeltaPowerIndex[p], pRFCalibrateInfo->DeltaPowerIndexLast[p])); - - pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->BbSwingIdxOfdmBase[p] + pRFCalibrateInfo->PowerIndexOffset[p]; - pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pRFCalibrateInfo->PowerIndexOffset[p]; - - pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->CCK_index; - pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->OFDM_index[p]; - - /*************Print BB Swing Base and Index Offset*************/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->PowerIndexOffset[p])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p], pRFCalibrateInfo->PowerIndexOffset[p])); - - /*4 7.1 Handle boundary conditions of index.*/ - - if (pRFCalibrateInfo->OFDM_index[p] > c.SwingTableSize_OFDM-1) - pRFCalibrateInfo->OFDM_index[p] = c.SwingTableSize_OFDM-1; - else if (pRFCalibrateInfo->OFDM_index[p] <= OFDM_min_index) - pRFCalibrateInfo->OFDM_index[p] = OFDM_min_index; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n========================================================================================================\n")); - - if (pRFCalibrateInfo->CCK_index > c.SwingTableSize_CCK-1) - pRFCalibrateInfo->CCK_index = c.SwingTableSize_CCK-1; - else if (pRFCalibrateInfo->CCK_index <= 0) - pRFCalibrateInfo->CCK_index = 0; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pRFCalibrateInfo->ThermalValue: %d\n", - pRFCalibrateInfo->TxPowerTrackControl, ThermalValue, pRFCalibrateInfo->ThermalValue)); - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", - pRFCalibrateInfo->CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); /*Print Swing base & current*/ - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%d]: %d\n", - pRFCalibrateInfo->OFDM_index[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p])); - } - - if ((pDM_Odm->SupportICType & ODM_RTL8814A)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PowerTrackingType=%d\n", PowerTrackingType)); - - if (PowerTrackingType == 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } else if (PowerTrackingType == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_2G_TSSI_5G_MODE, p, 0); - } else if (PowerTrackingType == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_5G_TSSI_2G_MODE, p, 0); - } else if (PowerTrackingType == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0); - } - pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ - - } else if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) && - pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { - //4 7.2 Configure the Swing Table to adjust Tx Power. - - pRFCalibrateInfo->bTxPowerChanged = TRUE; /*Always TRUE after Tx Power is adjusted by power tracking.*/ - // - // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital - // to increase TX power. Otherwise, EVM will be bad. - // - // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. - if (ThermalValue > pRFCalibrateInfo->ThermalValue) { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Increasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); - } - } else if (ThermalValue < pRFCalibrateInfo->ThermalValue) { /*Low temperature*/ - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Decreasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); - } - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (ThermalValue > pHalData->EEPROMThermalMeter) -#else - if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) -#endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || - pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || - pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || pDM_Odm->SupportICType == ODM_RTL8723D) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); - } - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || - pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || - pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || pDM_Odm->SupportICType == ODM_RTL8723D) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); - } - - } - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; /*Record last time Power Tracking result as base.*/ - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->BbSwingIdxOfdm[p]; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->ThermalValue = %d ThermalValue= %d\n", pRFCalibrateInfo->ThermalValue, ThermalValue)); - - pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ - - } - - - if (pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8723D) { - - if (XtalOffsetEanble != 0 && pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n")); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (ThermalValue > pHalData->EEPROMThermalMeter) { -#else - if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm); - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n")); - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if (!IS_HARDWARE_TYPE_8723B(Adapter)) { - /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ - if (delta_IQK >= c.Threshold_IQK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); - if (!pRFCalibrateInfo->bIQKInProgress) - (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8); - } - } - if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] != 0) { - if (diff_DPK[ODM_RF_PATH_A] >= c.Threshold_DPK) { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK)); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.Threshold_DPK)) { - s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, value); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } - } - if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] != 0) { - if (diff_DPK[ODM_RF_PATH_B] >= c.Threshold_DPK) { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK)); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.Threshold_DPK)) { - s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, value); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } - } - -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===ODM_TXPowerTrackingCallback_ThermalMeter\n")); - - pRFCalibrateInfo->TXPowercount = 0; -} - - - -//3============================================================ -//3 IQ Calibration -//3============================================================ - -VOID -ODM_ResetIQKResult( - IN PVOID pDM_VOID -) -{ - return; -} -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) -{ - u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = - {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; - u1Byte place = chnl; - - - if(chnl > 14) - { - for(place = 14; placeAdapter; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (*pDM_Odm->pIsFcsModeEnable) - return; -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - if (IS_HARDWARE_TYPE_8812AU(Adapter)) - return; -#endif - - if (pDM_Odm->bLinked) { - if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) { - pDM_Odm->preChannel = *pDM_Odm->pChannel; - pDM_Odm->LinkedInterval = 0; - } - - if (pDM_Odm->LinkedInterval < 3) - pDM_Odm->LinkedInterval++; - - if (pDM_Odm->LinkedInterval == 2) { - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - #if (RTL8814A_SUPPORT == 1) - PHY_IQCalibrate_8814A(pDM_Odm, FALSE); - #endif - } - - #if (RTL8822B_SUPPORT == 1) - else if (IS_HARDWARE_TYPE_8822B(Adapter)) - PHY_IQCalibrate_8822B(pDM_Odm, FALSE); - #endif - - #if (RTL8821C_SUPPORT == 1) - else if (IS_HARDWARE_TYPE_8821C(Adapter)) - PHY_IQCalibrate_8821C(pDM_Odm, FALSE); - #endif - - #if (RTL8821A_SUPPORT == 1) - else if (IS_HARDWARE_TYPE_8821(Adapter)) - PHY_IQCalibrate_8821A(pDM_Odm, FALSE); - #endif - } - } else - pDM_Odm->LinkedInterval = 0; -} - -void phydm_rf_init(IN PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - odm_TXPowerTrackingInit(pDM_Odm); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - ODM_ClearTxPowerTrackingState(pDM_Odm); -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8814A) - PHY_IQCalibrate_8814A_Init(pDM_Odm); -#endif -#endif - -} - -void phydm_rf_watchdog(IN PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - ODM_TXPowerTrackingCheck(pDM_Odm); - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - odm_IQCalibrate(pDM_Odm); -#endif -} diff --git a/hal/phydm/halphyrf_ce.h b/hal/phydm/halphyrf_ce.h deleted file mode 100644 index a0ed5dc..0000000 --- a/hal/phydm/halphyrf_ce.h +++ /dev/null @@ -1,118 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - #ifndef __HAL_PHY_RF_H__ - #define __HAL_PHY_RF_H__ - -#include "phydm_kfree.h" -#if (RTL8814A_SUPPORT == 1) -#include "rtl8814a/phydm_iqk_8814a.h" -#endif - -#if (RTL8822B_SUPPORT == 1) -#include "rtl8822b/phydm_iqk_8822b.h" -#endif - -#if (RTL8821C_SUPPORT == 1) -#include "rtl8821c/phydm_iqk_8821c.h" -#endif - -#include "phydm_powertracking_ce.h" - - -typedef enum _SPUR_CAL_METHOD { - PLL_RESET, - AFE_PHASE_SEL -} SPUR_CAL_METHOD; - -typedef enum _PWRTRACK_CONTROL_METHOD { - BBSWING, - TXAGC, - MIX_MODE, - TSSI_MODE, - MIX_2G_TSSI_5G_MODE, - MIX_5G_TSSI_2G_MODE -} PWRTRACK_METHOD; - -typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); -typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); -typedef VOID (*FuncLCK)(PVOID); -typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); -typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); -typedef VOID(*FuncSwingXtal)(PVOID, ps1Byte*, ps1Byte*); -typedef VOID(*FuncSetXtal)(PVOID); - -typedef struct _TXPWRTRACK_CFG { - u1Byte SwingTableSize_CCK; - u1Byte SwingTableSize_OFDM; - u1Byte Threshold_IQK; - u1Byte Threshold_DPK; - u1Byte AverageThermalNum; - u1Byte RfPathCount; - u4Byte ThermalRegAddr; - FuncSetPwr ODM_TxPwrTrackSetPwr; - FuncIQK DoIQK; - FuncLCK PHY_LCCalibrate; - FuncSwing GetDeltaSwingTable; - FuncSwing8814only GetDeltaSwingTable8814only; - FuncSwingXtal GetDeltaSwingXtalTable; - FuncSetXtal ODM_TxXtalTrackSetXtal; -} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; - -VOID -ConfigureTxpowerTrack( - IN PVOID pDM_VOID, - OUT PTXPWRTRACK_CFG pConfig - ); - - -VOID -ODM_ClearTxPowerTrackingState( - IN PVOID pDM_VOID - ); - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PVOID pDM_VOID -#else - IN PADAPTER Adapter -#endif - ); - - - -#define ODM_TARGET_CHNL_NUM_2G_5G 59 - - -VOID -ODM_ResetIQKResult( - IN PVOID pDM_VOID -); -u1Byte -ODM_GetRightChnlPlaceforIQK( - IN u1Byte chnl -); - -void phydm_rf_init( IN PVOID pDM_VOID); -void phydm_rf_watchdog( IN PVOID pDM_VOID); - -#endif // #ifndef __HAL_PHY_RF_H__ - diff --git a/hal/phydm/halphyrf_win.c b/hal/phydm/halphyrf_win.c deleted file mode 100644 index a93860f..0000000 --- a/hal/phydm/halphyrf_win.c +++ /dev/null @@ -1,780 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ - do {\ - for(_offset = 0; _offset < _size; _offset++)\ - {\ - if(_deltaThermal < thermalThreshold[_direction][_offset])\ - {\ - if(_offset != 0)\ - _offset--;\ - break;\ - }\ - } \ - if(_offset >= _size)\ - _offset = _size-1;\ - } while(0) - -void ConfigureTxpowerTrack( - IN PDM_ODM_T pDM_Odm, - OUT PTXPWRTRACK_CFG pConfig - ) -{ -#if RTL8192E_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8192E) - ConfigureTxpowerTrack_8192E(pConfig); -#endif -#if RTL8821A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8821) - ConfigureTxpowerTrack_8821A(pConfig); -#endif -#if RTL8812A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8812) - ConfigureTxpowerTrack_8812A(pConfig); -#endif -#if RTL8188E_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8188E) - ConfigureTxpowerTrack_8188E(pConfig); -#endif - -#if RTL8188F_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8188F) - ConfigureTxpowerTrack_8188F(pConfig); -#endif - -#if RTL8723B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8723B) - ConfigureTxpowerTrack_8723B(pConfig); -#endif - -#if RTL8814A_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8814A) - ConfigureTxpowerTrack_8814A(pConfig); -#endif - -#if RTL8703B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8703B) - ConfigureTxpowerTrack_8703B(pConfig); -#endif - -#if RTL8822B_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8822B) - ConfigureTxpowerTrack_8822B(pConfig); -#endif - -#if RTL8723D_SUPPORT - if (pDM_Odm->SupportICType == ODM_RTL8723D) - ConfigureTxpowerTrack_8723D(pConfig); -#endif -} - -//====================================================================== -// <20121113, Kordan> This function should be called when TxAGC changed. -// Otherwise the previous compensation is gone, because we record the -// delta of temperature between two TxPowerTracking watch dogs. -// -// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still -// need to call this function. -//====================================================================== -VOID -ODM_ClearTxPowerTrackingState( - IN PDM_ODM_T pDM_Odm - ) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter); - u1Byte p = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; - pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex; - pRFCalibrateInfo->CCK_index = 0; - - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) - { - pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; - - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - pRFCalibrateInfo->DeltaPowerIndex[p] = 0; - pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = 0; /* Initial Mix mode power tracking*/ - pRFCalibrateInfo->Remnant_OFDMSwingIdx[p] = 0; - pRFCalibrateInfo->KfreeOffset[p] = 0; - } - - pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathC = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Modify_TxAGC_Flag_PathD = FALSE; /*Initial at Modify Tx Scaling Mode*/ - pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; - pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; - - pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //modify by Mingzhi.Guo - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //modify by Mingzhi.Guo - -} - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER Adapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; -#endif -#endif - - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; - s1Byte diff_DPK[4] = {0}; - u1Byte ThermalValue_AVG_count = 0; - u4Byte ThermalValue_AVG = 0, RegC80, RegCd0, RegCd4, Regab4; - - u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur - u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel) - u1Byte PowerTrackingType = pHalData->RfPowerTrackingType; - u1Byte XtalOffsetEanble = 0; - - TXPWRTRACK_CFG c; - - //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. - pu1Byte deltaSwingTableIdx_TUP_A = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_A = NULL; - pu1Byte deltaSwingTableIdx_TUP_B = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_B = NULL; - /*for 8814 add by Yu Chen*/ - pu1Byte deltaSwingTableIdx_TUP_C = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_C = NULL; - pu1Byte deltaSwingTableIdx_TUP_D = NULL; - pu1Byte deltaSwingTableIdx_TDOWN_D = NULL; - /*for Xtal Offset by James.Tung*/ - ps1Byte deltaSwingTableXtal_UP = NULL; - ps1Byte deltaSwingTableXtal_DOWN = NULL; - - //4 2. Initilization ( 7 steps in total ) - - ConfigureTxpowerTrack(pDM_Odm, &c); - - (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A, - (pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B); - - if (pDM_Odm->SupportICType & ODM_RTL8814A) /*for 8814 path C & D*/ - (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_C, (pu1Byte *)&deltaSwingTableIdx_TDOWN_C, - (pu1Byte *)&deltaSwingTableIdx_TUP_D, (pu1Byte *)&deltaSwingTableIdx_TDOWN_D); - - if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/ - (*c.GetDeltaSwingXtalTable)(pDM_Odm, (ps1Byte *)&deltaSwingTableXtal_UP, (ps1Byte *)&deltaSwingTableXtal_DOWN); - - - pRFCalibrateInfo->TXPowerTrackingCallbackCnt++; /*cosa add for debug*/ - pRFCalibrateInfo->bTXPowerTrackingInit = TRUE; - - /*pRFCalibrateInfo->TxPowerTrackControl = pHalData->TxPowerTrackControl; - We should keep updating the control variable according to HalData. - RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */ - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - pRFCalibrateInfo->RegA24 = 0x090e1317; - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->mp_mode == TRUE) - pRFCalibrateInfo->RegA24 = 0x090e1317; - #endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("===>ODM_TXPowerTrackingCallback_ThermalMeter\n pRFCalibrateInfo->BbSwingIdxCckBase: %d, pRFCalibrateInfo->BbSwingIdxOfdmBase[A]: %d, pRFCalibrateInfo->DefaultOfdmIndex: %d\n", - pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pRFCalibrateInfo->DefaultOfdmIndex)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->TxPowerTrackControl=%d, pHalData->EEPROMThermalMeter %d\n", pRFCalibrateInfo->TxPowerTrackControl, pHalData->EEPROMThermalMeter)); - ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E - - /*add log by zhao he, check c80/c94/c14/ca0 value*/ - if (pDM_Odm->SupportICType == ODM_RTL8723D) { - RegC80 = ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord); - RegCd0 = ODM_GetBBReg(pDM_Odm, 0xcd0, bMaskDWord); - RegCd4 = ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord); - Regab4 = ODM_GetBBReg(pDM_Odm, 0xab4, 0x000007FF); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", RegC80, RegCd0, RegCd4, Regab4)); - } - - if (!pRFCalibrateInfo->TxPowerTrackControl) - return; - - - /*4 3. Initialize ThermalValues of RFCalibrateInfo*/ - - if (pRFCalibrateInfo->bReloadtxpowerindex) - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); - - /*4 4. Calculate average thermal meter*/ - - pRFCalibrateInfo->ThermalValue_AVG[pRFCalibrateInfo->ThermalValue_AVG_index] = ThermalValue; - pRFCalibrateInfo->ThermalValue_AVG_index++; - if (pRFCalibrateInfo->ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/ - pRFCalibrateInfo->ThermalValue_AVG_index = 0; - - for(i = 0; i < c.AverageThermalNum; i++) - { - if (pRFCalibrateInfo->ThermalValue_AVG[i]) { - ThermalValue_AVG += pRFCalibrateInfo->ThermalValue_AVG[i]; - ThermalValue_AVG_count++; - } - } - - if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times - { - ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter)); - } - - //4 5. Calculate delta, delta_LCK, delta_IQK. - - //"delta" here is used to determine whether thermal value changes or not. - delta = (ThermalValue > pRFCalibrateInfo->ThermalValue)?(ThermalValue - pRFCalibrateInfo->ThermalValue):(pRFCalibrateInfo->ThermalValue - ThermalValue); - delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); - delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); - - if (pRFCalibrateInfo->ThermalValue_IQK == 0xff) { /*no PG, use thermal value for IQK*/ - pRFCalibrateInfo->ThermalValue_IQK = ThermalValue; - delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use ThermalValue for IQK\n")); - } - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - diff_DPK[p] = (s1Byte)ThermalValue - (s1Byte)pRFCalibrateInfo->DpkThermal[p]; - - /*4 6. If necessary, do LCK.*/ - - if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { /*no PG , do LCK at initial status*/ - if (pRFCalibrateInfo->ThermalValue_LCK == 0xff) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); - pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; - - /*Use RTLCK, so close power tracking driver LCK*/ - if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { - if (c.PHY_LCCalibrate) - (*c.PHY_LCCalibrate)(pDM_Odm); - } - - delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); - - /* Delta temperature is equal to or larger than 20 centigrade.*/ - if (delta_LCK >= c.Threshold_IQK) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); - pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; - - /*Use RTLCK, so close power tracking driver LCK*/ - if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { - if (c.PHY_LCCalibrate) - (*c.PHY_LCCalibrate)(pDM_Odm); - } - } - } - - /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ - - if (delta > 0 && pRFCalibrateInfo->TxPowerTrackControl) - { - //"delta" here is used to record the absolute value of differrence. -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); -#else - delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); -#endif - if (delta >= TXPWR_TRACK_TABLE_SIZE) - delta = TXPWR_TRACK_TABLE_SIZE - 1; - - /*4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - if(ThermalValue > pHalData->EEPROMThermalMeter) { -#else - if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { -#endif - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/ - switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_B[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_C[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_D[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta])); - - pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_A[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - } - } - - if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) { - /*Save XtalOffset from Xtal table*/ - pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Xtal] deltaSwingTableXtal_UP[%d] = %d\n", delta, deltaSwingTableXtal_UP[delta])); - pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_UP[delta]; - - if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset) - XtalOffsetEanble = 0; - else - XtalOffsetEanble = 1; - } - - } else { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/ - - switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_C: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - case ODM_RF_PATH_D: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - - default: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta])); - pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; - pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); - break; - } - } - - if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) { - /*Save XtalOffset from Xtal table*/ - pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Xtal] deltaSwingTableXtal_DOWN[%d] = %d\n", delta, deltaSwingTableXtal_DOWN[delta])); - pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_DOWN[delta]; - - if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset) - XtalOffsetEanble = 0; - else - XtalOffsetEanble = 1; - } - - } - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n=========================== [Path-%d] Calculating PowerIndexOffset===========================\n", p)); - - if (pRFCalibrateInfo->DeltaPowerIndex[p] == pRFCalibrateInfo->DeltaPowerIndexLast[p]) /*If Thermal value changes but lookup table value still the same*/ - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - else - pRFCalibrateInfo->PowerIndexOffset[p] = pRFCalibrateInfo->DeltaPowerIndex[p] - pRFCalibrateInfo->DeltaPowerIndexLast[p]; /*Power Index Diff between 2 times Power Tracking*/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Path-%d] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n", p, pRFCalibrateInfo->PowerIndexOffset[p], pRFCalibrateInfo->DeltaPowerIndex[p], pRFCalibrateInfo->DeltaPowerIndexLast[p])); - - pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->BbSwingIdxOfdmBase[p] + pRFCalibrateInfo->PowerIndexOffset[p]; - pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pRFCalibrateInfo->PowerIndexOffset[p]; - - pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->CCK_index; - pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->OFDM_index[p]; - - /*************Print BB Swing Base and Index Offset*************/ - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->PowerIndexOffset[p])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p], pRFCalibrateInfo->PowerIndexOffset[p])); - - /*4 7.1 Handle boundary conditions of index.*/ - - if (pRFCalibrateInfo->OFDM_index[p] > c.SwingTableSize_OFDM-1) - pRFCalibrateInfo->OFDM_index[p] = c.SwingTableSize_OFDM-1; - else if (pRFCalibrateInfo->OFDM_index[p] <= OFDM_min_index) - pRFCalibrateInfo->OFDM_index[p] = OFDM_min_index; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n========================================================================================================\n")); - - if (pRFCalibrateInfo->CCK_index > c.SwingTableSize_CCK-1) - pRFCalibrateInfo->CCK_index = c.SwingTableSize_CCK-1; - else if (pRFCalibrateInfo->CCK_index <= 0) - pRFCalibrateInfo->CCK_index = 0; - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pRFCalibrateInfo->ThermalValue: %d\n", - pRFCalibrateInfo->TxPowerTrackControl, ThermalValue, pRFCalibrateInfo->ThermalValue)); - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", - pRFCalibrateInfo->CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); /*Print Swing base & current*/ - - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%d]: %d\n", - pRFCalibrateInfo->OFDM_index[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p])); - } - - if ((pDM_Odm->SupportICType & ODM_RTL8814A)) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PowerTrackingType=%d\n", PowerTrackingType)); - - if (PowerTrackingType == 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } else if (PowerTrackingType == 1) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_2G_TSSI_5G_MODE, p, 0); - } else if (PowerTrackingType == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_5G_TSSI_2G_MODE, p, 0); - } else if (PowerTrackingType == 3) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0); - } - pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ - - } else if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 || - pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) && - pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { - //4 7.2 Configure the Swing Table to adjust Tx Power. - - pRFCalibrateInfo->bTxPowerChanged = TRUE; /*Always TRUE after Tx Power is adjusted by power tracking.*/ - // - // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital - // to increase TX power. Otherwise, EVM will be bad. - // - // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. - if (ThermalValue > pRFCalibrateInfo->ThermalValue) { - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Increasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); - } - } else if (ThermalValue < pRFCalibrateInfo->ThermalValue) { /*Low temperature*/ - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Decreasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); - } - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (ThermalValue > pHalData->EEPROMThermalMeter) -#else - if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) -#endif - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || - pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || - pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || - pDM_Odm->SupportICType == ODM_RTL8723D) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); - } - } - else - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || - pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || - pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || - pDM_Odm->SupportICType == ODM_RTL8723D) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); - } - - } - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; /*Record last time Power Tracking result as base.*/ - for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) - pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->BbSwingIdxOfdm[p]; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRFCalibrateInfo->ThermalValue = %d ThermalValue= %d\n", pRFCalibrateInfo->ThermalValue, ThermalValue)); - - pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ - - } - - - if (pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8723D) { - - if (XtalOffsetEanble != 0 && pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) { - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n")); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (ThermalValue > pHalData->EEPROMThermalMeter) { -#else - if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { -#endif - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); - (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm); - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n")); - } - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - - if (!IS_HARDWARE_TYPE_8723B(Adapter)) { - /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ - if (delta_IQK >= c.Threshold_IQK) { - pRFCalibrateInfo->ThermalValue_IQK = ThermalValue; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); - if (!pRFCalibrateInfo->bIQKInProgress) - (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8); - } - } - if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] != 0) { - if (diff_DPK[ODM_RF_PATH_A] >= c.Threshold_DPK) { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK)); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.Threshold_DPK)) { - s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, value); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } - } - if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] != 0) { - if (diff_DPK[ODM_RF_PATH_B] >= c.Threshold_DPK) { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK)); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.Threshold_DPK)) { - s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK); - - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, value); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } else { - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); - ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); - ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); - } - } - -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===ODM_TXPowerTrackingCallback_ThermalMeter\n")); - - pRFCalibrateInfo->TXPowercount = 0; -} - - - -//3============================================================ -//3 IQ Calibration -//3============================================================ - -VOID -ODM_ResetIQKResult( - IN PDM_ODM_T pDM_Odm -) -{ - return; -} -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) -{ - u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = - {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; - u1Byte place = chnl; - - - if(chnl > 14) - { - for(place = 14; placeAdapter; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (*pDM_Odm->pIsFcsModeEnable) - return; -#endif - - if (pDM_Odm->bLinked) { - - if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) { - pDM_Odm->preChannel = *pDM_Odm->pChannel; - pDM_Odm->LinkedInterval = 0; - } - - if (pDM_Odm->LinkedInterval < 3) - pDM_Odm->LinkedInterval++; - - if (pDM_Odm->LinkedInterval == 2) { - PHY_IQCalibrate(Adapter, FALSE); - } - } else - pDM_Odm->LinkedInterval = 0; - -} - -void phydm_rf_init(IN PDM_ODM_T pDM_Odm) -{ - - odm_TXPowerTrackingInit(pDM_Odm); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - ODM_ClearTxPowerTrackingState(pDM_Odm); -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -#if (RTL8814A_SUPPORT == 1) - if (pDM_Odm->SupportICType & ODM_RTL8814A) - PHY_IQCalibrate_8814A_Init(pDM_Odm); -#endif -#endif - -} - -void phydm_rf_watchdog(IN PDM_ODM_T pDM_Odm) -{ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - ODM_TXPowerTrackingCheck(pDM_Odm); - if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - odm_IQCalibrate(pDM_Odm); -#endif -} diff --git a/hal/phydm/halphyrf_win.h b/hal/phydm/halphyrf_win.h deleted file mode 100644 index 783643b..0000000 --- a/hal/phydm/halphyrf_win.h +++ /dev/null @@ -1,120 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - #ifndef __HAL_PHY_RF_H__ - #define __HAL_PHY_RF_H__ - -#include "phydm_kfree.h" -#if (RTL8814A_SUPPORT == 1) -#include "rtl8814a/phydm_iqk_8814a.h" -#endif - -#if (RTL8822B_SUPPORT == 1) -#include "rtl8822b/phydm_iqk_8822b.h" -#include "../mac/Halmac_type.h" -#endif -#include "phydm_powertracking_win.h" - -#if (RTL8821C_SUPPORT == 1) -#include "rtl8821c/phydm_iqk_8821c.h" -#endif - -typedef enum _SPUR_CAL_METHOD { - PLL_RESET, - AFE_PHASE_SEL -} SPUR_CAL_METHOD; - -typedef enum _PWRTRACK_CONTROL_METHOD { - BBSWING, - TXAGC, - MIX_MODE, - TSSI_MODE, - MIX_2G_TSSI_5G_MODE, - MIX_5G_TSSI_2G_MODE -} PWRTRACK_METHOD; - -typedef VOID(*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); -typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); -typedef VOID(*FuncLCK)(PVOID); -typedef VOID(*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); -typedef VOID(*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); -typedef VOID (*FuncSwingXtal)(PVOID, ps1Byte*, ps1Byte*); -typedef VOID (*FuncSetXtal)(PVOID); -typedef VOID(*FuncAllSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); - -typedef struct _TXPWRTRACK_CFG { - u1Byte SwingTableSize_CCK; - u1Byte SwingTableSize_OFDM; - u1Byte Threshold_IQK; - u1Byte Threshold_DPK; - u1Byte AverageThermalNum; - u1Byte RfPathCount; - u4Byte ThermalRegAddr; - FuncSetPwr ODM_TxPwrTrackSetPwr; - FuncIQK DoIQK; - FuncLCK PHY_LCCalibrate; - FuncSwing GetDeltaSwingTable; - FuncSwing8814only GetDeltaSwingTable8814only; - FuncSwingXtal GetDeltaSwingXtalTable; - FuncSetXtal ODM_TxXtalTrackSetXtal; - FuncAllSwing GetDeltaAllSwingTable; -} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; - -VOID -ConfigureTxpowerTrack( - IN PDM_ODM_T pDM_Odm, - OUT PTXPWRTRACK_CFG pConfig - ); - - -VOID -ODM_ClearTxPowerTrackingState( - IN PDM_ODM_T pDM_Odm - ); - -VOID -ODM_TXPowerTrackingCallback_ThermalMeter( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm -#else - IN PADAPTER Adapter -#endif - ); - - - -#define ODM_TARGET_CHNL_NUM_2G_5G 59 - - -VOID -ODM_ResetIQKResult( - IN PDM_ODM_T pDM_Odm -); -u1Byte -ODM_GetRightChnlPlaceforIQK( - IN u1Byte chnl -); - -VOID odm_IQCalibrate(IN PDM_ODM_T pDM_Odm); -VOID phydm_rf_init( IN PDM_ODM_T pDM_Odm); -VOID phydm_rf_watchdog( IN PDM_ODM_T pDM_Odm); - -#endif // #ifndef __HAL_PHY_RF_H__ - diff --git a/hal/phydm/halrf/halphyrf_ap.c b/hal/phydm/halrf/halphyrf_ap.c index 22d6e53..e6b07a1 100644 --- a/hal/phydm/halrf/halphyrf_ap.c +++ b/hal/phydm/halrf/halphyrf_ap.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" @@ -44,39 +39,39 @@ void configure_txpower_track( - void *p_dm_void, - struct _TXPWRTRACK_CFG *p_config + void *dm_void, + struct txpwrtrack_cfg *config ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if RTL8812A_SUPPORT #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* if (IS_HARDWARE_TYPE_8812(p_dm_odm->adapter)) */ - if (p_dm_odm->support_ic_type == ODM_RTL8812) - configure_txpower_track_8812a(p_config); + /* if (IS_HARDWARE_TYPE_8812(dm->adapter)) */ + if (dm->support_ic_type == ODM_RTL8812) + configure_txpower_track_8812a(config); /* else */ #endif #endif #if RTL8814A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8814A) - configure_txpower_track_8814a(p_config); + if (dm->support_ic_type == ODM_RTL8814A) + configure_txpower_track_8814a(config); #endif #if RTL8188E_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - configure_txpower_track_8188e(p_config); + if (dm->support_ic_type == ODM_RTL8188E) + configure_txpower_track_8188e(config); #endif #if RTL8197F_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8197F) - configure_txpower_track_8197f(p_config); + if (dm->support_ic_type == ODM_RTL8197F) + configure_txpower_track_8197f(config); #endif #if RTL8822B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8822B) - configure_txpower_track_8822b(p_config); + if (dm->support_ic_type == ODM_RTL8822B) + configure_txpower_track_8822b(config); #endif @@ -85,10 +80,11 @@ void configure_txpower_track( #if (RTL8192E_SUPPORT == 1) void odm_txpowertracking_callback_thermal_meter_92e( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; u8 thermal_value = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode; u8 thermal_value_avg_count = 0; u8 OFDM_min_index = 10; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur */ @@ -96,13 +92,13 @@ odm_txpowertracking_callback_thermal_meter_92e( u32 thermal_value_avg = 0, reg0x18; u32 i = 0, j = 0, rf; s32 value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y; - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; - rf_mimo_mode = p_dm_odm->rf_type; - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode)); */ + rf_mimo_mode = dm->rf_type; + /* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK,"%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode); */ #ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || *(p_dm_odm->p_mp_mode)) { + if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) { channel = priv->pshare->working_channel; if (priv->pshare->mp_txpwr_tracking == false) return; @@ -112,15 +108,15 @@ odm_txpowertracking_callback_thermal_meter_92e( channel = (priv->pmib->dot11RFEntry.dot11channel); } - thermal_value = (unsigned char)odm_get_rf_reg(p_dm_odm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther)); + thermal_value = (unsigned char)odm_get_rf_reg(dm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther); switch (rf_mimo_mode) { - case MIMO_1T1R: + case RF_1T1R: rf = 1; break; - case MIMO_2T2R: + case RF_2T2R: rf = 2; break; default: @@ -133,18 +129,18 @@ odm_txpowertracking_callback_thermal_meter_92e( for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { if (ele_D == (ofdm_swing_table_92e[i] >> 22)) { OFDM_index[0] = (unsigned char)i; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]); break; } } /* Query OFDM path B default setting */ - if (rf_mimo_mode == MIMO_2T2R) { + if (rf_mimo_mode == RF_2T2R) { ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKOFDM_D); for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { if (ele_D == (ofdm_swing_table_92e[i] >> 22)) { OFDM_index[1] = (unsigned char)i; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]); break; } } @@ -166,7 +162,7 @@ odm_txpowertracking_callback_thermal_meter_92e( if (thermal_value_avg_count) { thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("AVG Thermal Meter = 0x%x\n", thermal_value)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value); } } @@ -178,8 +174,8 @@ odm_txpowertracking_callback_thermal_meter_92e( } if (thermal_value != priv->pshare->thermal_value) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** START POWER TRACKING ********\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n"); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther); delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther); delta_IQK = RTL_ABS(thermal_value, priv->pshare->thermal_value_iqk); @@ -188,32 +184,32 @@ odm_txpowertracking_callback_thermal_meter_92e( #ifdef _TRACKING_TABLE_FILE if (priv->pshare->rf_ft_var.pwr_track_file) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)); if (is_decrease) { for (i = 0; i < rf; i++) { OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)); CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1))); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1)); } } else { for (i = 0; i < rf; i++) { OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)); CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); CCK_index = ((CCK_index < 0) ? 0 : CCK_index); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1))); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1)); } } } #endif /* CFG_TRACKING_TABLE_FILE */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]); /* Adujst OFDM Ant_A according to IQK result */ ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22; @@ -279,18 +275,18 @@ odm_txpowertracking_callback_thermal_meter_92e( } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD))); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD))); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD)); - if (delta_IQK > 3) { + if ((delta_IQK > 3) && (!iqk_info->rfk_forbidden)) { priv->pshare->thermal_value_iqk = thermal_value; #ifdef MP_TEST -#endif if (!(*(p_dm_odm->p_mp_mode) && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET)))) +#endif if (!(*(dm->mp_mode) && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET)))) - phy_iq_calibrate_8192e(p_dm_odm, false); + halrf_iqk_trigger(dm, false); } - if (delta_LCK > 8) { + if ((delta_LCK > 8) && (!iqk_info->rfk_forbidden)) { RTL_W8(0x522, 0xff); reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1); phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1); @@ -309,27 +305,27 @@ odm_txpowertracking_callback_thermal_meter_92e( priv->pshare->OFDM_index[i] = OFDM_index[i]; priv->pshare->CCK_index = CCK_index; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__); } #endif -#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) +#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) void odm_txpowertracking_callback_thermal_meter_jaguar_series3( - void *p_dm_void + void *dm_void ) { #if 1 - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase; u8 thermal_value_avg_count = 0, p = 0, i = 0; u32 thermal_value_avg = 0; - struct rtl8192cd_priv *priv = p_dm_odm->priv; - struct _TXPWRTRACK_CFG c; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - + struct rtl8192cd_priv *priv = dm->priv; + struct txpwrtrack_cfg c; + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + struct dm_iqk_info *iqk_info = &dm->IQK_info; /*4 1. The following TWO tables decide the final index of OFDM/CCK swing table.*/ u8 *delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL; u8 *delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL; @@ -342,7 +338,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3( u8 *delta_swing_table_idx_tup_cck_d = NULL, *delta_swing_table_idx_tdown_cck_d = NULL; #ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || *(p_dm_odm->p_mp_mode)) { + if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) { channel = priv->pshare->working_channel; if (priv->pshare->mp_txpwr_tracking == false) return; @@ -352,90 +348,88 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3( channel = (priv->pmib->dot11RFEntry.dot11channel); } - configure_txpower_track(p_dm_odm, &c); + configure_txpower_track(dm, &c); - (*c.get_delta_all_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, + (*c.get_delta_all_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b, (u8 **)&delta_swing_table_idx_tup_cck_a, (u8 **)&delta_swing_table_idx_tdown_cck_a, (u8 **)&delta_swing_table_idx_tup_cck_b, (u8 **)&delta_swing_table_idx_tdown_cck_b); - thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /*0x42: RF Reg[15:10] 88E*/ + thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /*0x42: RF Reg[15:10] 88E*/ #ifdef THER_TRIM if (GET_CHIP_VER(priv) == VERSION_8197F) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("orig thermal_value=%d, ther_trim_val=%d\n", thermal_value, priv->pshare->rf_ft_var.ther_trim_val)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"orig thermal_value=%d, ther_trim_val=%d\n", thermal_value, priv->pshare->rf_ft_var.ther_trim_val); thermal_value += priv->pshare->rf_ft_var.ther_trim_val; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("after thermal trim, thermal_value=%d\n", thermal_value)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"after thermal trim, thermal_value=%d\n", thermal_value); } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Readback Thermal Meter = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n" - , thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n" + , thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther); /* Initialize */ - if (!p_dm_odm->rf_calibrate_info.thermal_value) - p_dm_odm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther; + if (!dm->rf_calibrate_info.thermal_value) + dm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther; - if (!p_dm_odm->rf_calibrate_info.thermal_value_lck) - p_dm_odm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther; + if (!dm->rf_calibrate_info.thermal_value_lck) + dm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther; - if (!p_dm_odm->rf_calibrate_info.thermal_value_iqk) - p_dm_odm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther; + if (!dm->rf_calibrate_info.thermal_value_iqk) + dm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther; /* calculate average thermal meter */ - p_dm_odm->rf_calibrate_info.thermal_value_avg[p_dm_odm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; - p_dm_odm->rf_calibrate_info.thermal_value_avg_index++; + dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; + dm->rf_calibrate_info.thermal_value_avg_index++; - if (p_dm_odm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ - p_dm_odm->rf_calibrate_info.thermal_value_avg_index = 0; + if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ + dm->rf_calibrate_info.thermal_value_avg_index = 0; for (i = 0; i < c.average_thermal_num; i++) { - if (p_dm_odm->rf_calibrate_info.thermal_value_avg[i]) { - thermal_value_avg += p_dm_odm->rf_calibrate_info.thermal_value_avg[i]; + if (dm->rf_calibrate_info.thermal_value_avg[i]) { + thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i]; thermal_value_avg_count++; } } if (thermal_value_avg_count) {/*Calculate Average thermal_value after average enough times*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("thermal_value_avg=0x%x(%d) thermal_value_avg_count = %d\n" - , thermal_value_avg, thermal_value_avg, thermal_value_avg_count)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"thermal_value_avg=0x%x(%d) thermal_value_avg_count = %d\n" + , thermal_value_avg, thermal_value_avg, thermal_value_avg_count); thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther); } /*4 Calculate delta, delta_LCK, delta_IQK.*/ delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther); - delta_LCK = RTL_ABS(thermal_value, p_dm_odm->rf_calibrate_info.thermal_value_lck); - delta_IQK = RTL_ABS(thermal_value, p_dm_odm->rf_calibrate_info.thermal_value_iqk); + delta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck); + delta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk); is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1); if (delta > 29) { /* power track table index(thermal diff.) upper bound*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta(%d) > 29, set delta to 29\n", delta)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta(%d) > 29, set delta to 29\n", delta); delta = 29; } /*4 if necessary, do LCK.*/ - - if (delta_LCK > c.threshold_iqk) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk)); - p_dm_odm->rf_calibrate_info.thermal_value_lck = thermal_value; + if ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk); + dm->rf_calibrate_info.thermal_value_lck = thermal_value; +#if (RTL8822B_SUPPORT != 1) + if (!(dm->support_ic_type & ODM_RTL8822B)) { if (c.phy_lc_calibrate) - (*c.phy_lc_calibrate)(p_dm_odm); + (*c.phy_lc_calibrate)(dm); + } +#endif } - if (delta_IQK > c.threshold_iqk) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk)); - p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value; + if ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk); + dm->rf_calibrate_info.thermal_value_iqk = thermal_value; if (c.do_iqk) - (*c.do_iqk)(p_dm_odm, true, 0, 0); + (*c.do_iqk)(dm, true, 0, 0); } if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ @@ -443,121 +437,109 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3( /*4 Do Power Tracking*/ - if (thermal_value != p_dm_odm->rf_calibrate_info.thermal_value) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n******** START POWER TRACKING ********\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", - thermal_value, p_dm_odm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther)); + if (thermal_value != dm->rf_calibrate_info.thermal_value) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\n\n******** START POWER TRACKING ********\n"); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", + thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther); #ifdef _TRACKING_TABLE_FILE if (priv->pshare->rf_ft_var.pwr_track_file) { if (is_increase) { /*thermal is higher than base*/ - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_b[%d] = %d delta_swing_table_idx_tup_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta], delta, delta_swing_table_idx_tup_cck_b[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; - p_rf_calibrate_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_b[delta]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + case RF_PATH_B: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d delta_swing_table_idx_tup_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta], delta, delta_swing_table_idx_tup_cck_b[delta]); + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; + cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_b[delta]; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); break; - case ODM_RF_PATH_C: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_c[%d] = %d delta_swing_table_idx_tup_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta], delta, delta_swing_table_idx_tup_cck_c[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; - p_rf_calibrate_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_c[delta]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + case RF_PATH_C: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d delta_swing_table_idx_tup_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta], delta, delta_swing_table_idx_tup_cck_c[delta]); + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; + cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_c[delta]; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); break; - case ODM_RF_PATH_D: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_d[%d] = %d delta_swing_table_idx_tup_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta], delta, delta_swing_table_idx_tup_cck_d[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; - p_rf_calibrate_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_d[delta]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + case RF_PATH_D: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d delta_swing_table_idx_tup_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta], delta, delta_swing_table_idx_tup_cck_d[delta]); + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; + cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_d[delta]; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); break; default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_a[%d] = %d delta_swing_table_idx_tup_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta], delta, delta_swing_table_idx_tup_cck_a[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; - p_rf_calibrate_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_a[delta]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d delta_swing_table_idx_tup_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta], delta, delta_swing_table_idx_tup_cck_a[delta]); + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; + cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_a[delta]; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); break; } } } else { /* thermal is lower than base*/ - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_b[%d] = %d delta_swing_table_idx_tdown_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta], delta, delta_swing_table_idx_tdown_cck_b[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; - p_rf_calibrate_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_b[delta]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + case RF_PATH_B: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d delta_swing_table_idx_tdown_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta], delta, delta_swing_table_idx_tdown_cck_b[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; + cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_b[delta]; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); break; - case ODM_RF_PATH_C: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_c[%d] = %d delta_swing_table_idx_tdown_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta], delta, delta_swing_table_idx_tdown_cck_c[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; - p_rf_calibrate_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_c[delta]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + case RF_PATH_C: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d delta_swing_table_idx_tdown_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta], delta, delta_swing_table_idx_tdown_cck_c[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; + cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_c[delta]; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); break; - case ODM_RF_PATH_D: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_d[%d] = %d delta_swing_table_idx_tdown_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta], delta, delta_swing_table_idx_tdown_cck_d[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; - p_rf_calibrate_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_d[delta]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + case RF_PATH_D: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d delta_swing_table_idx_tdown_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta], delta, delta_swing_table_idx_tdown_cck_d[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; + cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_d[delta]; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); break; default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_a[%d] = %d delta_swing_table_idx_tdown_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta], delta, delta_swing_table_idx_tdown_cck_a[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; - p_rf_calibrate_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_a[delta]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d delta_swing_table_idx_tdown_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta], delta, delta_swing_table_idx_tdown_cck_a[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; + cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_a[delta]; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); break; } } } if (is_increase) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power --->\n")); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> increse power --->\n"); if (GET_CHIP_VER(priv) == VERSION_8197F) { - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, 0); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0); } else if (GET_CHIP_VER(priv) == VERSION_8822B) { - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else if (GET_CHIP_VER(priv) == VERSION_8821C) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); } } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power --->\n")); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power --->\n"); if (GET_CHIP_VER(priv) == VERSION_8197F) { - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, 0); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0); } else if (GET_CHIP_VER(priv) == VERSION_8822B) { - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else if (GET_CHIP_VER(priv) == VERSION_8821C) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); } } } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n\n", __func__)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n\n", __func__); /*update thermal meter value*/ - p_dm_odm->rf_calibrate_info.thermal_value = thermal_value; + dm->rf_calibrate_info.thermal_value = thermal_value; } @@ -570,20 +552,21 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3( void odm_txpowertracking_callback_thermal_meter_jaguar_series2( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase; u8 thermal_value_avg_count = 0, p = 0, i = 0; u32 thermal_value_avg = 0, reg0x18; u32 bb_swing_reg[4] = {REG_A_TX_SCALE_JAGUAR, REG_B_TX_SCALE_JAGUAR, REG_C_TX_SCALE_JAGUAR2, REG_D_TX_SCALE_JAGUAR2}; s32 ele_D; u32 bb_swing_idx; - struct rtl8192cd_priv *priv = p_dm_odm->priv; - struct _TXPWRTRACK_CFG c; + struct rtl8192cd_priv *priv = dm->priv; + struct txpwrtrack_cfg c; boolean is_tssi_enable = false; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + struct dm_iqk_info *iqk_info = &dm->IQK_info; /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ u8 *delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL; @@ -593,7 +576,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2( u8 *delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL; #ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || *(p_dm_odm->p_mp_mode)) { + if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) { channel = priv->pshare->working_channel; if (priv->pshare->mp_txpwr_tracking == false) return; @@ -603,97 +586,93 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2( channel = (priv->pmib->dot11RFEntry.dot11channel); } - configure_txpower_track(p_dm_odm, &c); - p_rf_calibrate_info->default_ofdm_index = priv->pshare->OFDM_index0[ODM_RF_PATH_A]; + configure_txpower_track(dm, &c); + cali_info->default_ofdm_index = priv->pshare->OFDM_index0[RF_PATH_A]; - (*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, + (*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b); - if (p_dm_odm->support_ic_type & ODM_RTL8814A) /* for 8814 path C & D */ - (*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c, + if (dm->support_ic_type & ODM_RTL8814A) /* for 8814 path C & D */ + (*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c, (u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d); - thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, p_dm_odm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther)); + thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther); /* Initialize */ - if (!p_dm_odm->rf_calibrate_info.thermal_value) - p_dm_odm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther; + if (!dm->rf_calibrate_info.thermal_value) + dm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther; - if (!p_dm_odm->rf_calibrate_info.thermal_value_lck) - p_dm_odm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther; + if (!dm->rf_calibrate_info.thermal_value_lck) + dm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther; - if (!p_dm_odm->rf_calibrate_info.thermal_value_iqk) - p_dm_odm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther; + if (!dm->rf_calibrate_info.thermal_value_iqk) + dm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther; - is_tssi_enable = (boolean)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, REG_RF_TX_GAIN_OFFSET, BIT(7)); /* check TSSI enable */ + is_tssi_enable = (boolean)odm_get_rf_reg(dm, RF_PATH_A, REG_RF_TX_GAIN_OFFSET, BIT(7)); /* check TSSI enable */ /* 4 Query OFDM BB swing default setting Bit[31:21] */ - for (p = ODM_RF_PATH_A ; p < c.rf_path_count ; p++) { - ele_D = odm_get_bb_reg(p_dm_odm, bb_swing_reg[p], 0xffe00000); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(p_dm_odm, bb_swing_reg[p], MASKDWORD), ele_D)); + for (p = RF_PATH_A ; p < c.rf_path_count ; p++) { + ele_D = odm_get_bb_reg(dm, bb_swing_reg[p], 0xffe00000); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(dm, bb_swing_reg[p], MASKDWORD), ele_D); for (bb_swing_idx = 0; bb_swing_idx < TXSCALE_TABLE_SIZE; bb_swing_idx++) {/* 4 */ if (ele_D == tx_scaling_table_jaguar[bb_swing_idx]) { - p_dm_odm->rf_calibrate_info.OFDM_index[p] = (u8)bb_swing_idx; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("OFDM_index[%d]=%d\n", p, p_dm_odm->rf_calibrate_info.OFDM_index[p])); + dm->rf_calibrate_info.OFDM_index[p] = (u8)bb_swing_idx; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"OFDM_index[%d]=%d\n", p, dm->rf_calibrate_info.OFDM_index[p]); break; } } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("kfree_offset[%d]=%d\n", p, p_rf_calibrate_info->kfree_offset[p])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "kfree_offset[%d]=%d\n", p, cali_info->kfree_offset[p]); } /* calculate average thermal meter */ - p_dm_odm->rf_calibrate_info.thermal_value_avg[p_dm_odm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; - p_dm_odm->rf_calibrate_info.thermal_value_avg_index++; - if (p_dm_odm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) /* Average times = c.average_thermal_num */ - p_dm_odm->rf_calibrate_info.thermal_value_avg_index = 0; + dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; + dm->rf_calibrate_info.thermal_value_avg_index++; + if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) /* Average times = c.average_thermal_num */ + dm->rf_calibrate_info.thermal_value_avg_index = 0; for (i = 0; i < c.average_thermal_num; i++) { - if (p_dm_odm->rf_calibrate_info.thermal_value_avg[i]) { - thermal_value_avg += p_dm_odm->rf_calibrate_info.thermal_value_avg[i]; + if (dm->rf_calibrate_info.thermal_value_avg[i]) { + thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i]; thermal_value_avg_count++; } } if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */ thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther); } /* 4 Calculate delta, delta_LCK, delta_IQK. */ delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther); - delta_LCK = RTL_ABS(thermal_value, p_dm_odm->rf_calibrate_info.thermal_value_lck); - delta_IQK = RTL_ABS(thermal_value, p_dm_odm->rf_calibrate_info.thermal_value_iqk); + delta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck); + delta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk); is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1); /* 4 if necessary, do LCK. */ - if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) { - if (delta_LCK > c.threshold_iqk) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk)); - p_dm_odm->rf_calibrate_info.thermal_value_lck = thermal_value; + if (!(dm->support_ic_type & ODM_RTL8821)) { + if ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk); + dm->rf_calibrate_info.thermal_value_lck = thermal_value; /*Use RTLCK, so close power tracking driver LCK*/ #if (RTL8814A_SUPPORT != 1) - if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) { + if (!(dm->support_ic_type & ODM_RTL8814A)) { if (c.phy_lc_calibrate) - (*c.phy_lc_calibrate)(p_dm_odm); + (*c.phy_lc_calibrate)(dm); } #endif } } - if (delta_IQK > c.threshold_iqk) { + if ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) { panic_printk("%s(%d)\n", __FUNCTION__, __LINE__); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk)); - p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk); + dm->rf_calibrate_info.thermal_value_iqk = thermal_value; if (c.do_iqk) - (*c.do_iqk)(p_dm_odm, true, 0, 0); + (*c.do_iqk)(dm, true, 0, 0); } if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ @@ -702,106 +681,88 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2( /* 4 Do Power Tracking */ if (is_tssi_enable == true) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter PURE TSSI MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0); - } else if (thermal_value != p_dm_odm->rf_calibrate_info.thermal_value) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n******** START POWER TRACKING ********\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, p_dm_odm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter PURE TSSI MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0); + } else if (thermal_value != dm->rf_calibrate_info.thermal_value) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\n******** START POWER TRACKING ********\n"); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther); #ifdef _TRACKING_TABLE_FILE if (priv->pshare->rf_ft_var.pwr_track_file) { if (is_increase) { /* thermal is higher than base */ - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /* Record delta swing for mix mode power tracking */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_B: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]); + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /* Record delta swing for mix mode power tracking */ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; - case ODM_RF_PATH_C: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /* Record delta swing for mix mode power tracking */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_C: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]); + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /* Record delta swing for mix mode power tracking */ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; - case ODM_RF_PATH_D: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /* Record delta swing for mix mode power tracking */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_D: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]); + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /* Record delta swing for mix mode power tracking */ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /* Record delta swing for mix mode power tracking */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]); + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /* Record delta swing for mix mode power tracking */ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; } } } else { /* thermal is lower than base */ - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /* Record delta swing for mix mode power tracking */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_B: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /* Record delta swing for mix mode power tracking */ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; - case ODM_RF_PATH_C: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /* Record delta swing for mix mode power tracking */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_C: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /* Record delta swing for mix mode power tracking */ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; - case ODM_RF_PATH_D: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /* Record delta swing for mix mode power tracking */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_D: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /* Record delta swing for mix mode power tracking */ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta])); - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /* Record delta swing for mix mode power tracking */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /* Record delta swing for mix mode power tracking */ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; } } } if (is_increase) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power --->\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> increse power --->\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power --->\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power --->\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); } } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__); /* update thermal meter value */ - p_dm_odm->rf_calibrate_info.thermal_value = thermal_value; + dm->rf_calibrate_info.thermal_value = thermal_value; } } @@ -810,10 +771,10 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2( #if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1) void odm_txpowertracking_callback_thermal_meter_jaguar_series( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; unsigned char thermal_value = 0, delta, delta_LCK, channel, is_decrease; unsigned char thermal_value_avg_count = 0; unsigned int thermal_value_avg = 0, reg0x18; @@ -821,13 +782,13 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series( int ele_D, value32; char OFDM_index[2], index; unsigned int i = 0, j = 0, rf_path, max_rf_path = 2, rf; - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; unsigned char OFDM_min_index = 7; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic */ - + struct dm_iqk_info *iqk_info = &dm->IQK_info; #ifdef MP_TEST - if ((OPMODE & WIFI_MP_STATE) || *(p_dm_odm->p_mp_mode)) { + if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) { channel = priv->pshare->working_channel; if (priv->pshare->mp_txpwr_tracking == false) return; @@ -838,10 +799,10 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series( } #if RTL8881A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8881A) { + if (dm->support_ic_type == ODM_RTL8881A) { max_rf_path = 1; if ((get_bonding_type_8881A() == BOND_8881AM || get_bonding_type_8881A() == BOND_8881AN) - && priv->pshare->rf_ft_var.use_intpa8881A && (*p_dm_odm->p_band_type == ODM_BAND_2_4G)) + && priv->pshare->rf_ft_var.use_intpa8881A && (*dm->band_type == ODM_BAND_2_4G)) OFDM_min_index = 6; /* intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phy_band_select == PHY_BAND_2G)) */ else OFDM_min_index = 10; /* OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic */ @@ -850,17 +811,17 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series( thermal_value = (unsigned char)phy_query_rf_reg(priv, RF_PATH_A, 0x42, 0xfc00, 1); /* 0x42: RF Reg[15:10] 88E */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther); /* 4 Query OFDM BB swing default setting Bit[31:21] */ for (rf_path = 0 ; rf_path < max_rf_path ; rf_path++) { ele_D = phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D); for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */ if (ele_D == ofdm_swing_table_8812[i]) { OFDM_index[rf_path] = (unsigned char)i; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path]); break; } } @@ -868,22 +829,22 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series( #if 0 /* Query OFDM path A default setting Bit[31:21] */ ele_D = phy_query_bb_reg(priv, 0xc1c, 0xffe00000); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D); for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */ if (ele_D == ofdm_swing_table_8812[i]) { OFDM_index[0] = (unsigned char)i; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("OFDM_index[0]=%d\n", OFDM_index[0])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "OFDM_index[0]=%d\n", OFDM_index[0]); break; } } /* Query OFDM path B default setting */ if (rf == 2) { ele_D = phy_query_bb_reg(priv, 0xe1c, 0xffe00000); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D); for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) { if (ele_D == ofdm_swing_table_8812[i]) { OFDM_index[1] = (unsigned char)i; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("OFDM_index[1]=%d\n", OFDM_index[1])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "OFDM_index[1]=%d\n", OFDM_index[1]); break; } } @@ -922,23 +883,23 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series( return; if (thermal_value != priv->pshare->thermal_value) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** START POWER TRACKING ********\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n"); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther); delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther); delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck); is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0); - /* if (*p_dm_odm->p_band_type == ODM_BAND_5G) */ + /* if (*dm->band_type == ODM_BAND_5G) */ { #ifdef _TRACKING_TABLE_FILE if (priv->pshare->rf_ft_var.pwr_track_file) { for (rf_path = 0; rf_path < max_rf_path; rf_path++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0)); if (is_decrease) { OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0)); #if 0/* RTL8881A_SUPPORT */ - if (p_dm_odm->support_ic_type == ODM_RTL8881A) { + if (dm->support_ic_type == ODM_RTL8881A) { if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) { if (priv->pshare->add_tx_agc) { /* tx_agc has been added */ add_tx_power88xx_ac(priv, 0); @@ -952,7 +913,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series( OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); #if 0/* RTL8881A_SUPPORT */ - if (p_dm_odm->support_ic_type == ODM_RTL8881A) { + if (dm->support_ic_type == ODM_RTL8881A) { if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) { if (OFDM_index[i] < OFDM_min_index) { priv->pshare->add_tx_agc_index = (OFDM_min_index - OFDM_index[i]) / 2; /* Calculate Remnant tx_agc value, 2 index for 1 tx_agc */ @@ -971,7 +932,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series( #else OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ? OFDM_min_index : OFDM_index[rf_path]); #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0)); } } } @@ -979,11 +940,11 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series( /* 4 Set new BB swing index */ for (rf_path = 0; rf_path < max_rf_path; rf_path++) { phy_set_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000, ofdm_swing_table_8812[(unsigned int)OFDM_index[rf_path]]); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path]); } } - if (delta_LCK > 8) { + if ((delta_LCK > 8) && (!iqk_info->rfk_forbidden)) { RTL_W8(0x522, 0xff); reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1); phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1); @@ -998,7 +959,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series( RTL_W8(0x522, 0x0); priv->pshare->thermal_value_lck = thermal_value; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__); /* update thermal meter value */ priv->pshare->thermal_value = thermal_value; @@ -1012,42 +973,43 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series( void odm_txpowertracking_callback_thermal_meter( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - - -#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8197F || p_dm_odm->support_ic_type == ODM_RTL8822B) { - odm_txpowertracking_callback_thermal_meter_jaguar_series3(p_dm_odm); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + struct dm_iqk_info *iqk_info = &dm->IQK_info; + +#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F || dm->support_ic_type == ODM_RTL8822B + || dm->support_ic_type == ODM_RTL8821C) { + odm_txpowertracking_callback_thermal_meter_jaguar_series3(dm); return; } #endif #if (RTL8814A_SUPPORT == 1) /*use this function to do power tracking after 8814 by YuChen*/ - if (p_dm_odm->support_ic_type & ODM_RTL8814A) { - odm_txpowertracking_callback_thermal_meter_jaguar_series2(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8814A) { + odm_txpowertracking_callback_thermal_meter_jaguar_series2(dm); return; } #endif #if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8812 || p_dm_odm->support_ic_type & ODM_RTL8881A) { - odm_txpowertracking_callback_thermal_meter_jaguar_series(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8812 || dm->support_ic_type & ODM_RTL8881A) { + odm_txpowertracking_callback_thermal_meter_jaguar_series(dm); return; } #endif #if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_txpowertracking_callback_thermal_meter_92e(p_dm_odm); + if (dm->support_ic_type == ODM_RTL8192E) { + odm_txpowertracking_callback_thermal_meter_92e(dm); return; } #endif #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - /* PMGNT_INFO p_mgnt_info = &adapter->mgnt_info; */ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + /* PMGNT_INFO mgnt_info = &adapter->mgnt_info; */ #endif @@ -1063,10 +1025,10 @@ odm_txpowertracking_callback_thermal_meter( /* bool bInteralPA = false; */ u8 OFDM_max_index = 34, rf = (is2T) ? 2 : 1; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ - u8 indexforchannel = 0;/*get_right_chnl_place_for_iqk(p_hal_data->current_channel)*/ + u8 indexforchannel = 0;/*get_right_chnl_place_for_iqk(hal_data->current_channel)*/ enum _POWER_DEC_INC { POWER_DEC, POWER_INC }; - struct _TXPWRTRACK_CFG c; + struct txpwrtrack_cfg c; /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ @@ -1080,64 +1042,64 @@ odm_txpowertracking_callback_thermal_meter( }; #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; #endif /* 4 2. Initilization ( 7 steps in total ) */ - configure_txpower_track(p_dm_odm, &c); + configure_txpower_track(dm, &c); - p_dm_odm->rf_calibrate_info.txpowertracking_callback_cnt++; /* cosa add for debug */ - p_dm_odm->rf_calibrate_info.is_txpowertracking_init = true; + dm->rf_calibrate_info.txpowertracking_callback_cnt++; /* cosa add for debug */ + dm->rf_calibrate_info.is_txpowertracking_init = true; #if (MP_DRIVER == 1) - p_dm_odm->rf_calibrate_info.txpowertrack_control = p_hal_data->txpowertrack_control; /* We should keep updating the control variable according to HalData. + dm->rf_calibrate_info.txpowertrack_control = hal_data->txpowertrack_control; /* We should keep updating the control variable according to HalData. * rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */ - p_dm_odm->rf_calibrate_info.rega24 = 0x090e1317; + dm->rf_calibrate_info.rega24 = 0x090e1317; #endif #if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST) - if ((OPMODE & WIFI_MP_STATE) || *(p_dm_odm->p_mp_mode)) { - if (p_dm_odm->priv->pshare->mp_txpwr_tracking == false) + if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) { + if (dm->priv->pshare->mp_txpwr_tracking == false) return; } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>odm_txpowertracking_callback_thermal_meter_8188e, p_dm_odm->bb_swing_idx_cck_base: %d, p_dm_odm->bb_swing_idx_ofdm_base: %d\n", p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "===>odm_txpowertracking_callback_thermal_meter_8188e, dm->bb_swing_idx_cck_base: %d, dm->bb_swing_idx_ofdm_base: %d\n", cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base); /* - if (!p_dm_odm->rf_calibrate_info.tm_trigger) { - odm_set_rf_reg(p_dm_odm, RF_PATH_A, c.thermal_reg_addr, BIT(17) | BIT(16), 0x3); - p_dm_odm->rf_calibrate_info.tm_trigger = 1; + if (!dm->rf_calibrate_info.tm_trigger) { + odm_set_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, BIT(17) | BIT(16), 0x3); + dm->rf_calibrate_info.tm_trigger = 1; return; } */ - thermal_value = (u8)odm_get_rf_reg(p_dm_odm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (!thermal_value || !p_dm_odm->rf_calibrate_info.txpowertrack_control) + if (!thermal_value || !dm->rf_calibrate_info.txpowertrack_control) #else - if (!p_dm_odm->rf_calibrate_info.txpowertrack_control) + if (!dm->rf_calibrate_info.txpowertrack_control) #endif return; /* 4 3. Initialize ThermalValues of rf_calibrate_info */ - if (!p_dm_odm->rf_calibrate_info.thermal_value) { - p_dm_odm->rf_calibrate_info.thermal_value_lck = thermal_value; - p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value; + if (!dm->rf_calibrate_info.thermal_value) { + dm->rf_calibrate_info.thermal_value_lck = thermal_value; + dm->rf_calibrate_info.thermal_value_iqk = thermal_value; } - if (p_dm_odm->rf_calibrate_info.is_reloadtxpowerindex) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n")); + if (dm->rf_calibrate_info.is_reloadtxpowerindex) + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "reload ofdm index for band switch\n"); /* 4 4. Calculate average thermal meter */ - p_dm_odm->rf_calibrate_info.thermal_value_avg[p_dm_odm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; - p_dm_odm->rf_calibrate_info.thermal_value_avg_index++; - if (p_dm_odm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) - p_dm_odm->rf_calibrate_info.thermal_value_avg_index = 0; + dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; + dm->rf_calibrate_info.thermal_value_avg_index++; + if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) + dm->rf_calibrate_info.thermal_value_avg_index = 0; for (i = 0; i < c.average_thermal_num; i++) { - if (p_dm_odm->rf_calibrate_info.thermal_value_avg[i]) { - thermal_value_avg += p_dm_odm->rf_calibrate_info.thermal_value_avg[i]; + if (dm->rf_calibrate_info.thermal_value_avg[i]) { + thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i]; thermal_value_avg_count++; } } @@ -1147,124 +1109,121 @@ odm_txpowertracking_callback_thermal_meter( thermal_value_avg += (thermal_value * 4); thermal_value = (u8)(thermal_value_avg / (thermal_value_avg_count + 4)); - p_rf_calibrate_info->thermal_value_delta = thermal_value - priv->pmib->dot11RFEntry.ther; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("AVG Thermal Meter = 0x%x\n", thermal_value)); + cali_info->thermal_value_delta = thermal_value - priv->pmib->dot11RFEntry.ther; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value); } /* 4 5. Calculate delta, delta_LCK, delta_IQK. */ - delta = (thermal_value > p_dm_odm->rf_calibrate_info.thermal_value) ? (thermal_value - p_dm_odm->rf_calibrate_info.thermal_value) : (p_dm_odm->rf_calibrate_info.thermal_value - thermal_value); - delta_LCK = (thermal_value > p_dm_odm->rf_calibrate_info.thermal_value_lck) ? (thermal_value - p_dm_odm->rf_calibrate_info.thermal_value_lck) : (p_dm_odm->rf_calibrate_info.thermal_value_lck - thermal_value); - delta_IQK = (thermal_value > p_dm_odm->rf_calibrate_info.thermal_value_iqk) ? (thermal_value - p_dm_odm->rf_calibrate_info.thermal_value_iqk) : (p_dm_odm->rf_calibrate_info.thermal_value_iqk - thermal_value); + delta = (thermal_value > dm->rf_calibrate_info.thermal_value) ? (thermal_value - dm->rf_calibrate_info.thermal_value) : (dm->rf_calibrate_info.thermal_value - thermal_value); + delta_LCK = (thermal_value > dm->rf_calibrate_info.thermal_value_lck) ? (thermal_value - dm->rf_calibrate_info.thermal_value_lck) : (dm->rf_calibrate_info.thermal_value_lck - thermal_value); + delta_IQK = (thermal_value > dm->rf_calibrate_info.thermal_value_iqk) ? (thermal_value - dm->rf_calibrate_info.thermal_value_iqk) : (dm->rf_calibrate_info.thermal_value_iqk - thermal_value); /* 4 6. If necessary, do LCK. */ - if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) { - /*if((delta_LCK > p_hal_data->delta_lck) && (p_hal_data->delta_lck != 0))*/ - if (delta_LCK >= c.threshold_iqk) { + if (!(dm->support_ic_type & ODM_RTL8821)) { + /*if((delta_LCK > hal_data->delta_lck) && (hal_data->delta_lck != 0))*/ + if ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) { /*Delta temperature is equal to or larger than 20 centigrade.*/ - p_dm_odm->rf_calibrate_info.thermal_value_lck = thermal_value; - (*c.phy_lc_calibrate)(p_dm_odm); + dm->rf_calibrate_info.thermal_value_lck = thermal_value; + (*c.phy_lc_calibrate)(dm); } } /* 3 7. If necessary, move the index of swing table to adjust Tx power. */ - if (delta > 0 && p_dm_odm->rf_calibrate_info.txpowertrack_control) { + if (delta > 0 && dm->rf_calibrate_info.txpowertrack_control) { - delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value); + delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value); /* 4 7.1 The Final Power index = BaseIndex + power_index_offset */ - if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) { + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) { CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta); - p_dm_odm->rf_calibrate_info.delta_power_index_last = p_dm_odm->rf_calibrate_info.delta_power_index; - p_dm_odm->rf_calibrate_info.delta_power_index = delta_swing_table_idx[POWER_INC][offset]; + dm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index; + dm->rf_calibrate_info.delta_power_index = delta_swing_table_idx[POWER_INC][offset]; } else { CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta); - p_dm_odm->rf_calibrate_info.delta_power_index_last = p_dm_odm->rf_calibrate_info.delta_power_index; - p_dm_odm->rf_calibrate_info.delta_power_index = (-1) * delta_swing_table_idx[POWER_DEC][offset]; + dm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index; + dm->rf_calibrate_info.delta_power_index = (-1) * delta_swing_table_idx[POWER_DEC][offset]; } - if (p_dm_odm->rf_calibrate_info.delta_power_index == p_dm_odm->rf_calibrate_info.delta_power_index_last) - p_dm_odm->rf_calibrate_info.power_index_offset = 0; + if (dm->rf_calibrate_info.delta_power_index == dm->rf_calibrate_info.delta_power_index_last) + dm->rf_calibrate_info.power_index_offset = 0; else - p_dm_odm->rf_calibrate_info.power_index_offset = p_dm_odm->rf_calibrate_info.delta_power_index - p_dm_odm->rf_calibrate_info.delta_power_index_last; + dm->rf_calibrate_info.power_index_offset = dm->rf_calibrate_info.delta_power_index - dm->rf_calibrate_info.delta_power_index_last; for (i = 0; i < rf; i++) - p_dm_odm->rf_calibrate_info.OFDM_index[i] = p_rf_calibrate_info->bb_swing_idx_ofdm_base + p_dm_odm->rf_calibrate_info.power_index_offset; - p_dm_odm->rf_calibrate_info.CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_dm_odm->rf_calibrate_info.power_index_offset; + dm->rf_calibrate_info.OFDM_index[i] = cali_info->bb_swing_idx_ofdm_base + dm->rf_calibrate_info.power_index_offset; + dm->rf_calibrate_info.CCK_index = cali_info->bb_swing_idx_cck_base + dm->rf_calibrate_info.power_index_offset; - p_rf_calibrate_info->bb_swing_idx_cck = p_dm_odm->rf_calibrate_info.CCK_index; - p_rf_calibrate_info->bb_swing_idx_ofdm[RF_PATH_A] = p_dm_odm->rf_calibrate_info.OFDM_index[RF_PATH_A]; + cali_info->bb_swing_idx_cck = dm->rf_calibrate_info.CCK_index; + cali_info->bb_swing_idx_ofdm[RF_PATH_A] = dm->rf_calibrate_info.OFDM_index[RF_PATH_A]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_dm_odm->rf_calibrate_info.power_index_offset)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[RF_PATH_A], p_rf_calibrate_info->bb_swing_idx_ofdm_base, p_dm_odm->rf_calibrate_info.power_index_offset)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, dm->rf_calibrate_info.power_index_offset); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base, dm->rf_calibrate_info.power_index_offset); /* 4 7.1 Handle boundary conditions of index. */ for (i = 0; i < rf; i++) { - if (p_dm_odm->rf_calibrate_info.OFDM_index[i] > OFDM_max_index) - p_dm_odm->rf_calibrate_info.OFDM_index[i] = OFDM_max_index; - else if (p_dm_odm->rf_calibrate_info.OFDM_index[i] < 0) - p_dm_odm->rf_calibrate_info.OFDM_index[i] = 0; + if (dm->rf_calibrate_info.OFDM_index[i] > OFDM_max_index) + dm->rf_calibrate_info.OFDM_index[i] = OFDM_max_index; + else if (dm->rf_calibrate_info.OFDM_index[i] < 0) + dm->rf_calibrate_info.OFDM_index[i] = 0; } - if (p_dm_odm->rf_calibrate_info.CCK_index > c.swing_table_size_cck - 1) - p_dm_odm->rf_calibrate_info.CCK_index = c.swing_table_size_cck - 1; - else if (p_dm_odm->rf_calibrate_info.CCK_index < 0) - p_dm_odm->rf_calibrate_info.CCK_index = 0; + if (dm->rf_calibrate_info.CCK_index > c.swing_table_size_cck - 1) + dm->rf_calibrate_info.CCK_index = c.swing_table_size_cck - 1; + else if (dm->rf_calibrate_info.CCK_index < 0) + dm->rf_calibrate_info.CCK_index = 0; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, p_dm_odm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, p_dm_odm->rf_calibrate_info.thermal_value)); - p_dm_odm->rf_calibrate_info.power_index_offset = 0; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, dm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, dm->rf_calibrate_info.thermal_value); + dm->rf_calibrate_info.power_index_offset = 0; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", p_dm_odm->rf_calibrate_info.CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.CCK_index, cali_info->bb_swing_idx_cck_base); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", p_dm_odm->rf_calibrate_info.OFDM_index[RF_PATH_A], p_rf_calibrate_info->bb_swing_idx_ofdm_base)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.OFDM_index[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base); - if (p_dm_odm->rf_calibrate_info.power_index_offset != 0 && p_dm_odm->rf_calibrate_info.txpowertrack_control) { + if (dm->rf_calibrate_info.power_index_offset != 0 && dm->rf_calibrate_info.txpowertrack_control) { /* 4 7.2 Configure the Swing Table to adjust Tx Power. */ - p_dm_odm->rf_calibrate_info.is_tx_power_changed = true; /* Always true after Tx Power is adjusted by power tracking. */ + dm->rf_calibrate_info.is_tx_power_changed = true; /* Always true after Tx Power is adjusted by power tracking. */ /* */ /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */ /* to increase TX power. Otherwise, EVM will be bad. */ /* */ /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ - if (thermal_value > p_dm_odm->rf_calibrate_info.thermal_value) { - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, */ - /* ("Temperature Increasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */ - /* p_dm_odm->rf_calibrate_info.power_index_offset, delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_dm_odm->rf_calibrate_info.thermal_value)); */ - } else if (thermal_value < p_dm_odm->rf_calibrate_info.thermal_value) { /* Low temperature */ - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, */ - /* ("Temperature Decreasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */ - /* p_dm_odm->rf_calibrate_info.power_index_offset, delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_dm_odm->rf_calibrate_info.thermal_value)); */ + if (thermal_value > dm->rf_calibrate_info.thermal_value) { + /* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK, */ + /* "Temperature Increasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */ + /* dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */ + } else if (thermal_value < dm->rf_calibrate_info.thermal_value) { /* Low temperature */ + /* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK, */ + /* "Temperature Decreasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */ + /* dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */ } - if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) { - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, p_hal_data->eeprom_thermal_meter)); */ - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TXAGC, 0, 0); + /* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK,"Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */ + (*c.odm_tx_pwr_track_set_pwr)(dm, TXAGC, 0, 0); } else { - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, p_hal_data->eeprom_thermal_meter)); */ - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, RF_PATH_A, indexforchannel); + /* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK,"Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */ + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_A, indexforchannel); if (is2T) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, RF_PATH_B, indexforchannel); + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_B, indexforchannel); } - p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck; - p_rf_calibrate_info->bb_swing_idx_ofdm_base = p_rf_calibrate_info->bb_swing_idx_ofdm[RF_PATH_A]; - p_dm_odm->rf_calibrate_info.thermal_value = thermal_value; + cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; + cali_info->bb_swing_idx_ofdm_base = cali_info->bb_swing_idx_ofdm[RF_PATH_A]; + dm->rf_calibrate_info.thermal_value = thermal_value; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n")); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n"); - p_dm_odm->rf_calibrate_info.tx_powercount = 0; + dm->rf_calibrate_info.tx_powercount = 0; } /* 3============================================================ @@ -1273,7 +1232,7 @@ odm_txpowertracking_callback_thermal_meter( void odm_reset_iqk_result( - void *p_dm_void + void *dm_void ) { return; @@ -1300,70 +1259,47 @@ u8 odm_get_right_chnl_place_for_iqk(u8 chnl) void odm_iq_calibrate( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - if (p_dm_odm->is_linked) { - if ((*p_dm_odm->p_channel != p_dm_odm->pre_channel) && (!*p_dm_odm->p_is_scan_in_process)) { - p_dm_odm->pre_channel = *p_dm_odm->p_channel; - p_dm_odm->linked_interval = 0; - } - - if (p_dm_odm->linked_interval < 3) - p_dm_odm->linked_interval++; + struct dm_iqk_info *iqk_info = &dm->IQK_info; - if (p_dm_odm->linked_interval == 2) { - -#if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) - phy_iq_calibrate_8814a(p_dm_odm, false); -#endif - -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) - phy_iq_calibrate_8822b(p_dm_odm, false); -#endif - -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - phy_iq_calibrate_8821c(p_dm_odm, false); -#endif + if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) { + if ((*dm->channel != dm->pre_channel) && (!*dm->is_scan_in_process)) { + dm->pre_channel = *dm->channel; + dm->linked_interval = 0; + } -#if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821) - phy_iq_calibrate_8821a(p_dm_odm, false); -#endif + if (dm->linked_interval < 3) + dm->linked_interval++; -#if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - _phy_iq_calibrate_8812a(p_dm_odm, false); -#endif - } + if (dm->linked_interval == 2) + halrf_iqk_trigger(dm, false); } else - p_dm_odm->linked_interval = 0; + dm->linked_interval = 0; } -void phydm_rf_init(void *p_dm_void) +void phydm_rf_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - odm_txpowertracking_init(p_dm_odm); + struct dm_struct *dm = (struct dm_struct *)dm_void; + odm_txpowertracking_init(dm); #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - phy_iq_calibrate_8814a_init(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8814A) + phy_iq_calibrate_8814a_init(dm); #endif #endif } -void phydm_rf_watchdog(void *p_dm_void) +void phydm_rf_watchdog(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - odm_txpowertracking_check(p_dm_odm); - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - odm_iq_calibrate(p_dm_odm); + odm_txpowertracking_check(dm); + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + odm_iq_calibrate(dm); #endif } diff --git a/hal/phydm/halrf/halphyrf_ap.h b/hal/phydm/halrf/halphyrf_ap.h index f3e2eb6..6c6d629 100644 --- a/hal/phydm/halrf/halphyrf_ap.h +++ b/hal/phydm/halrf/halphyrf_ap.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_PHY_RF_H__ #define __HAL_PHY_RF_H__ @@ -33,7 +28,7 @@ #endif #if (RTL8821C_SUPPORT == 1) - #include "halrf/rtl8822b/halrf_iqk_8821c.h" + #include "halrf/rtl8821c/halrf_iqk_8821c.h" #endif enum pwrtrack_method { @@ -52,7 +47,7 @@ typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **); typedef void (*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **); -struct _TXPWRTRACK_CFG { +struct txpwrtrack_cfg { u8 swing_table_size_cck; u8 swing_table_size_ofdm; u8 threshold_iqk; @@ -70,39 +65,39 @@ struct _TXPWRTRACK_CFG { void configure_txpower_track( - void *p_dm_void, - struct _TXPWRTRACK_CFG *p_config + void *dm_void, + struct txpwrtrack_cfg *config ); void odm_txpowertracking_callback_thermal_meter( - void *p_dm_void + void *dm_void ); #if (RTL8192E_SUPPORT == 1) void odm_txpowertracking_callback_thermal_meter_92e( - void *p_dm_void + void *dm_void ); #endif #if (RTL8814A_SUPPORT == 1) void odm_txpowertracking_callback_thermal_meter_jaguar_series2( - void *p_dm_void + void *dm_void ); #elif ODM_IC_11AC_SERIES_SUPPORT void odm_txpowertracking_callback_thermal_meter_jaguar_series( - void *p_dm_void + void *dm_void ); #elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) void odm_txpowertracking_callback_thermal_meter_jaguar_series3( - void *p_dm_void + void *dm_void ); #endif @@ -114,14 +109,14 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3( void odm_reset_iqk_result( - void *p_dm_void + void *dm_void ); u8 odm_get_right_chnl_place_for_iqk( u8 chnl ); -void phydm_rf_init(void *p_dm_void); -void phydm_rf_watchdog(void *p_dm_void); +void phydm_rf_init(void *dm_void); +void phydm_rf_watchdog(void *dm_void); #endif /* #ifndef __HAL_PHY_RF_H__ */ diff --git a/hal/phydm/halrf/halphyrf_ce.c b/hal/phydm/halrf/halphyrf_ce.c index dcb2e87..847a685 100644 --- a/hal/phydm/halrf/halphyrf_ce.c +++ b/hal/phydm/halrf/halphyrf_ce.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" @@ -24,9 +29,7 @@ #define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \ do {\ for (_offset = 0; _offset < _size; _offset++) { \ - \ if (_delta_thermal < thermal_threshold[_direction][_offset]) { \ - \ if (_offset != 0)\ _offset--;\ break;\ @@ -37,65 +40,65 @@ } while (0) void configure_txpower_track( - void *p_dm_void, - struct _TXPWRTRACK_CFG *p_config + void *dm_void, + struct txpwrtrack_cfg *config ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if RTL8192E_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8192E) - configure_txpower_track_8192e(p_config); + if (dm->support_ic_type == ODM_RTL8192E) + configure_txpower_track_8192e(config); #endif #if RTL8821A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8821) - configure_txpower_track_8821a(p_config); + if (dm->support_ic_type == ODM_RTL8821) + configure_txpower_track_8821a(config); #endif #if RTL8812A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8812) - configure_txpower_track_8812a(p_config); + if (dm->support_ic_type == ODM_RTL8812) + configure_txpower_track_8812a(config); #endif #if RTL8188E_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - configure_txpower_track_8188e(p_config); + if (dm->support_ic_type == ODM_RTL8188E) + configure_txpower_track_8188e(config); #endif #if RTL8723B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8723B) - configure_txpower_track_8723b(p_config); + if (dm->support_ic_type == ODM_RTL8723B) + configure_txpower_track_8723b(config); #endif #if RTL8814A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8814A) - configure_txpower_track_8814a(p_config); + if (dm->support_ic_type == ODM_RTL8814A) + configure_txpower_track_8814a(config); #endif #if RTL8703B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8703B) - configure_txpower_track_8703b(p_config); + if (dm->support_ic_type == ODM_RTL8703B) + configure_txpower_track_8703b(config); #endif #if RTL8188F_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8188F) - configure_txpower_track_8188f(p_config); + if (dm->support_ic_type == ODM_RTL8188F) + configure_txpower_track_8188f(config); #endif #if RTL8723D_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8723D) - configure_txpower_track_8723d(p_config); + if (dm->support_ic_type == ODM_RTL8723D) + configure_txpower_track_8723d(config); #endif /* JJ ADD 20161014 */ #if RTL8710B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8710B) - configure_txpower_track_8710b(p_config); + if (dm->support_ic_type == ODM_RTL8710B) + configure_txpower_track_8710b(config); #endif #if RTL8822B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8822B) - configure_txpower_track_8822b(p_config); + if (dm->support_ic_type == ODM_RTL8822B) + configure_txpower_track_8822b(config); #endif #if RTL8821C_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - configure_txpower_track_8821c(p_config); + if (dm->support_ic_type == ODM_RTL8821C) + configure_txpower_track_8821c(config); #endif } @@ -110,80 +113,82 @@ void configure_txpower_track( * ********************************************************************** */ void odm_clear_txpowertracking_state( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv); #else - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(dm->adapter); #endif u8 p = 0; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index; - p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index; - p_dm_odm->rf_calibrate_info.CCK_index = 0; + cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index; + cali_info->bb_swing_idx_cck = cali_info->default_cck_index; + dm->rf_calibrate_info.CCK_index = 0; - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) { - p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index; - p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index; - p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index; + for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) { + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index; + cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index; + cali_info->OFDM_index[p] = cali_info->default_ofdm_index; - p_rf_calibrate_info->power_index_offset[p] = 0; - p_rf_calibrate_info->delta_power_index[p] = 0; - p_rf_calibrate_info->delta_power_index_last[p] = 0; + cali_info->power_index_offset[p] = 0; + cali_info->delta_power_index[p] = 0; + cali_info->delta_power_index_last[p] = 0; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/ - p_rf_calibrate_info->remnant_ofdm_swing_idx[p] = 0; - p_rf_calibrate_info->kfree_offset[p] = 0; + cali_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/ + cali_info->remnant_ofdm_swing_idx[p] = 0; + cali_info->kfree_offset[p] = 0; } - p_rf_calibrate_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/ - p_rf_calibrate_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/ - p_rf_calibrate_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/ - p_rf_calibrate_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/ - p_rf_calibrate_info->remnant_cck_swing_idx = 0; + cali_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/ + cali_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/ + cali_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/ + cali_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/ + cali_info->remnant_cck_swing_idx = 0; #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - p_rf_calibrate_info->thermal_value = rtlefu->eeprom_thermalmeter; + cali_info->thermal_value = rtlefu->eeprom_thermalmeter; #else - p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter; + cali_info->thermal_value = hal_data->eeprom_thermal_meter; #endif - p_rf_calibrate_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */ - p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */ + cali_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */ + cali_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */ } void odm_txpowertracking_callback_thermal_meter( #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct PHY_DM_STRUCT *p_dm_odm -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - void *p_dm_void + struct dm_struct *dm +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + void *dm_void #else - struct _ADAPTER *adapter + void *adapter #endif ) { - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv); - void *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; #elif !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); #endif #endif - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + struct dm_iqk_info *iqk_info = &dm->IQK_info; u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; s8 diff_DPK[4] = {0}; @@ -191,16 +196,16 @@ odm_txpowertracking_callback_thermal_meter( u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4; u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ - u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(p_hal_data->current_channel) */ + u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) u8 power_tracking_type = 0; /* no specify type */ #else - u8 power_tracking_type = p_hal_data->rf_power_tracking_type; + u8 power_tracking_type = hal_data->rf_power_tracking_type; #endif u8 xtal_offset_eanble = 0; s8 thermal_value_temp = 0; - struct _TXPWRTRACK_CFG c; + struct txpwrtrack_cfg c = {0}; /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ u8 *delta_swing_table_idx_tup_a = NULL; @@ -218,51 +223,51 @@ odm_txpowertracking_callback_thermal_meter( /* 4 2. Initilization ( 7 steps in total ) */ - configure_txpower_track(p_dm_odm, &c); + configure_txpower_track(dm, &c); - (*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, + (*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b); - if (p_dm_odm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/ - (*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c, + if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/ + (*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c, (u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d); /* JJ ADD 20161014 */ - if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/ - (*c.get_delta_swing_xtal_table)(p_dm_odm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down); + if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/ + (*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down); - p_rf_calibrate_info->txpowertracking_callback_cnt++; /*cosa add for debug*/ - p_rf_calibrate_info->is_txpowertracking_init = true; + cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/ + cali_info->is_txpowertracking_init = true; - /*p_rf_calibrate_info->txpowertrack_control = p_hal_data->txpowertrack_control; + /*cali_info->txpowertrack_control = hal_data->txpowertrack_control; We should keep updating the control variable according to HalData. rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */ #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) #if (MP_DRIVER == 1) - p_rf_calibrate_info->rega24 = 0x090e1317; + cali_info->rega24 = 0x090e1317; #endif #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (*(p_dm_odm->p_mp_mode) == true) - p_rf_calibrate_info->rega24 = 0x090e1317; + if (*(dm->mp_mode) == true) + cali_info->rega24 = 0x090e1317; #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("===>odm_txpowertracking_callback_thermal_meter\n p_rf_calibrate_info->bb_swing_idx_cck_base: %d, p_rf_calibrate_info->bb_swing_idx_ofdm_base[A]: %d, p_rf_calibrate_info->default_ofdm_index: %d\n", - p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A], p_rf_calibrate_info->default_ofdm_index)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n", + cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index); #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("p_rf_calibrate_info->txpowertrack_control=%d, rtlefu->eeprom_thermalmeter %d\n", p_rf_calibrate_info->txpowertrack_control, rtlefu->eeprom_thermalmeter)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "cali_info->txpowertrack_control=%d, rtlefu->eeprom_thermalmeter %d\n", cali_info->txpowertrack_control, rtlefu->eeprom_thermalmeter); #else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("p_rf_calibrate_info->txpowertrack_control=%d, p_hal_data->eeprom_thermal_meter %d\n", p_rf_calibrate_info->txpowertrack_control, p_hal_data->eeprom_thermal_meter)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "cali_info->txpowertrack_control=%d, hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control, hal_data->eeprom_thermal_meter); #endif - thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ - thermal_value_temp = thermal_value + phydm_get_thermal_offset(p_dm_odm); + thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("thermal_value_temp(%d) = thermal_value(%d) + power_trim_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(p_dm_odm))); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "thermal_value_temp(%d) = thermal_value(%d) + power_trim_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm)); if (thermal_value_temp > 63) thermal_value = 63; @@ -272,45 +277,52 @@ odm_txpowertracking_callback_thermal_meter( thermal_value = thermal_value_temp; /*add log by zhao he, check c80/c94/c14/ca0 value*/ - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD); - regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD); - regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD); - regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4)); + if (dm->support_ic_type == ODM_RTL8723D) { + regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4); } /* JJ ADD 20161014 */ - if (p_dm_odm->support_ic_type == ODM_RTL8710B) { - regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD); - regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD); - regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD); - regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4)); + if (dm->support_ic_type == ODM_RTL8710B) { + regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4); } - if (!p_rf_calibrate_info->txpowertrack_control) + if (!cali_info->txpowertrack_control) return; - if (p_hal_data->eeprom_thermal_meter == 0xff) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no pg, p_hal_data->eeprom_thermal_meter = 0x%x\n", p_hal_data->eeprom_thermal_meter)); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + if (rtlefu->eeprom_thermalmeter == 0xff) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", rtlefu->eeprom_thermalmeter); return; } +#else + if (hal_data->eeprom_thermal_meter == 0xff) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter); + return; + } +#endif /*4 3. Initialize ThermalValues of rf_calibrate_info*/ - if (p_rf_calibrate_info->is_reloadtxpowerindex) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n")); + if (cali_info->is_reloadtxpowerindex) + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "reload ofdm index for band switch\n"); /*4 4. Calculate average thermal meter*/ - p_rf_calibrate_info->thermal_value_avg[p_rf_calibrate_info->thermal_value_avg_index] = thermal_value; - p_rf_calibrate_info->thermal_value_avg_index++; - if (p_rf_calibrate_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ - p_rf_calibrate_info->thermal_value_avg_index = 0; + cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value; + cali_info->thermal_value_avg_index++; + if (cali_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ + cali_info->thermal_value_avg_index = 0; for (i = 0; i < c.average_thermal_num; i++) { - if (p_rf_calibrate_info->thermal_value_avg[i]) { - thermal_value_avg += p_rf_calibrate_info->thermal_value_avg[i]; + if (cali_info->thermal_value_avg[i]) { + thermal_value_avg += cali_info->thermal_value_avg[i]; thermal_value_avg_count++; } } @@ -318,74 +330,74 @@ odm_txpowertracking_callback_thermal_meter( if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */ thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - p_rf_calibrate_info->thermal_value_delta = thermal_value - rtlefu->eeprom_thermalmeter; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, rtlefu->eeprom_thermalmeter)); + cali_info->thermal_value_delta = thermal_value - rtlefu->eeprom_thermalmeter; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, rtlefu->eeprom_thermalmeter); #else - p_rf_calibrate_info->thermal_value_delta = thermal_value - p_hal_data->eeprom_thermal_meter; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + cali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, hal_data->eeprom_thermal_meter); #endif } /* 4 5. Calculate delta, delta_LCK, delta_IQK. */ /* "delta" here is used to determine whether thermal value changes or not. */ - delta = (thermal_value > p_rf_calibrate_info->thermal_value) ? (thermal_value - p_rf_calibrate_info->thermal_value) : (p_rf_calibrate_info->thermal_value - thermal_value); - delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value); - delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value); - - if (p_rf_calibrate_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/ - p_rf_calibrate_info->thermal_value_iqk = thermal_value; - delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use thermal_value for IQK\n")); + delta = (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value); + delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value); + delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value); + + if (cali_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/ + cali_info->thermal_value_iqk = thermal_value; + delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n"); } - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - diff_DPK[p] = (s8)thermal_value - (s8)p_rf_calibrate_info->dpk_thermal[p]; + for (p = RF_PATH_A; p < c.rf_path_count; p++) + diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p]; /*4 6. If necessary, do LCK.*/ - if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/ - if (p_rf_calibrate_info->thermal_value_lck == 0xff) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); - p_rf_calibrate_info->thermal_value_lck = thermal_value; + if (!(dm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/ + if (cali_info->thermal_value_lck == 0xff) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, do LCK\n"); + cali_info->thermal_value_lck = thermal_value; /*Use RTLCK, so close power tracking driver LCK*/ - if (!(p_dm_odm->support_ic_type & ODM_RTL8814A) && c.phy_lc_calibrate) - (*c.phy_lc_calibrate)(p_dm_odm); + if (!(dm->support_ic_type & ODM_RTL8814A) && !(dm->support_ic_type & ODM_RTL8822B) && c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(dm); - delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value); + delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK); /* Wait sacn to do LCK by RF Jenyu*/ - if (*p_dm_odm->p_is_scan_in_process == false) { + if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) { /* Delta temperature is equal to or larger than 20 centigrade.*/ if (delta_LCK >= c.threshold_iqk) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk)); - p_rf_calibrate_info->thermal_value_lck = thermal_value; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk); + cali_info->thermal_value_lck = thermal_value; /*Use RTLCK, so close power tracking driver LCK*/ - if (!(p_dm_odm->support_ic_type & ODM_RTL8814A) && c.phy_lc_calibrate) - (*c.phy_lc_calibrate)(p_dm_odm); + if (!(dm->support_ic_type & ODM_RTL8814A) && !(dm->support_ic_type & ODM_RTL8822B) && c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(dm); } } } /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ - if (delta > 0 && p_rf_calibrate_info->txpowertrack_control) { + if (delta > 0 && cali_info->txpowertrack_control) { /* "delta" here is used to record the absolute value of differrence. */ #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) delta = thermal_value > rtlefu->eeprom_thermalmeter ? (thermal_value - rtlefu->eeprom_thermalmeter) : (rtlefu->eeprom_thermalmeter - thermal_value); #else - delta = thermal_value > p_hal_data->eeprom_thermal_meter ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value); + delta = thermal_value > hal_data->eeprom_thermal_meter ? (thermal_value - hal_data->eeprom_thermal_meter) : (hal_data->eeprom_thermal_meter - thermal_value); #endif #else - delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value); + delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value); #endif if (delta >= TXPWR_TRACK_TABLE_SIZE) delta = TXPWR_TRACK_TABLE_SIZE - 1; @@ -396,240 +408,240 @@ odm_txpowertracking_callback_thermal_meter( #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) if (thermal_value > rtlefu->eeprom_thermalmeter) { #else - if (thermal_value > p_hal_data->eeprom_thermal_meter) { + if (thermal_value > hal_data->eeprom_thermal_meter) { #endif #else - if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) { + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) { #endif - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { - p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/ switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta])); - - p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_B: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]); + + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; - case ODM_RF_PATH_C: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta])); + case RF_PATH_C: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]); - p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; - case ODM_RF_PATH_D: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta])); + case RF_PATH_D: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]); - p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]); - p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; } } /* JJ ADD 20161014 */ - if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { /*Save xtal_offset from Xtal table*/ - p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta])); - p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_up[delta]; - xtal_offset_eanble = (p_rf_calibrate_info->xtal_offset_last != p_rf_calibrate_info->xtal_offset); + cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]); + cali_info->xtal_offset = delta_swing_table_xtal_up[delta]; + xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset); } } else { - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { - p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/ switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta])); - p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_B: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; - case ODM_RF_PATH_C: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta])); - p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_C: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; - case ODM_RF_PATH_D: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta])); - p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_D: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta])); - p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; } } /* JJ ADD 20161014 */ - if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { /*Save xtal_offset from Xtal table*/ - p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta])); - p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_down[delta]; - xtal_offset_eanble = (p_rf_calibrate_info->xtal_offset_last != p_rf_calibrate_info->xtal_offset); + cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]); + cali_info->xtal_offset = delta_swing_table_xtal_down[delta]; + xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset); } } - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p)); + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p); - if (p_rf_calibrate_info->delta_power_index[p] == p_rf_calibrate_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/ - p_rf_calibrate_info->power_index_offset[p] = 0; + if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/ + cali_info->power_index_offset[p] = 0; else - p_rf_calibrate_info->power_index_offset[p] = p_rf_calibrate_info->delta_power_index[p] - p_rf_calibrate_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/ + cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, p_rf_calibrate_info->power_index_offset[p], p_rf_calibrate_info->delta_power_index[p], p_rf_calibrate_info->delta_power_index_last[p])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]); - p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] + p_rf_calibrate_info->power_index_offset[p]; - p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_rf_calibrate_info->power_index_offset[p]; + cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p]; + cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p]; - p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->CCK_index; - p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->OFDM_index[p]; + cali_info->bb_swing_idx_cck = cali_info->CCK_index; + cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p]; /*************Print BB Swing base and index Offset*************/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->power_index_offset[p])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p], p_rf_calibrate_info->power_index_offset[p])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]); /*4 7.1 Handle boundary conditions of index.*/ - if (p_rf_calibrate_info->OFDM_index[p] > c.swing_table_size_ofdm - 1) - p_rf_calibrate_info->OFDM_index[p] = c.swing_table_size_ofdm - 1; - else if (p_rf_calibrate_info->OFDM_index[p] <= OFDM_min_index) - p_rf_calibrate_info->OFDM_index[p] = OFDM_min_index; + if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1) + cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1; + else if (cali_info->OFDM_index[p] <= OFDM_min_index) + cali_info->OFDM_index[p] = OFDM_min_index; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n========================================================================================================\n")); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "\n\n========================================================================================================\n"); - if (p_rf_calibrate_info->CCK_index > c.swing_table_size_cck - 1) - p_rf_calibrate_info->CCK_index = c.swing_table_size_cck - 1; - else if (p_rf_calibrate_info->CCK_index <= 0) - p_rf_calibrate_info->CCK_index = 0; + if (cali_info->CCK_index > c.swing_table_size_cck - 1) + cali_info->CCK_index = c.swing_table_size_cck - 1; + else if (cali_info->CCK_index <= 0) + cali_info->CCK_index = 0; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, p_rf_calibrate_info->thermal_value: %d\n", - p_rf_calibrate_info->txpowertrack_control, thermal_value, p_rf_calibrate_info->thermal_value)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n", + cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - p_rf_calibrate_info->power_index_offset[p] = 0; + for (p = RF_PATH_A; p < c.rf_path_count; p++) + cali_info->power_index_offset[p] = 0; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", - p_rf_calibrate_info->CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base)); /*Print Swing base & current*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", + cali_info->CCK_index, cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/ - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n", - p_rf_calibrate_info->OFDM_index[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p])); + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n", + cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]); } - if ((p_dm_odm->support_ic_type & ODM_RTL8814A)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("power_tracking_type=%d\n", power_tracking_type)); + if ((dm->support_ic_type & ODM_RTL8814A)) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type); if (power_tracking_type == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); } else if (power_tracking_type == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_2G_TSSI_5G_MODE, p, 0); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0); } else if (power_tracking_type == 2) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_5G_TSSI_2G_MODE, p, 0); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0); } else if (power_tracking_type == 3) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0); } - p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ - } else if ((p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_A] != 0 || - p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_B] != 0 || - p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_C] != 0 || - p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_D] != 0) && + } else if ((cali_info->power_index_offset[RF_PATH_A] != 0 || + cali_info->power_index_offset[RF_PATH_B] != 0 || + cali_info->power_index_offset[RF_PATH_C] != 0 || + cali_info->power_index_offset[RF_PATH_D] != 0) && #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - p_rf_calibrate_info->txpowertrack_control && (rtlefu->eeprom_thermalmeter != 0xff)) { + cali_info->txpowertrack_control && (rtlefu->eeprom_thermalmeter != 0xff)) { #else - p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) { + cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) { #endif /* 4 7.2 Configure the Swing Table to adjust Tx Power. */ - p_rf_calibrate_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/ + cali_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/ /* */ /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */ /* to increase TX power. Otherwise, EVM will be bad. */ /* */ /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ - if (thermal_value > p_rf_calibrate_info->thermal_value) { - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + if (thermal_value > cali_info->thermal_value) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, rtlefu->eeprom_thermalmeter, p_rf_calibrate_info->thermal_value)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, cali_info->power_index_offset[p], delta, thermal_value, rtlefu->eeprom_thermalmeter, cali_info->thermal_value); #else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value); #endif } - } else if (thermal_value < p_rf_calibrate_info->thermal_value) { /*Low temperature*/ - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + } else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) { #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, rtlefu->eeprom_thermalmeter, p_rf_calibrate_info->thermal_value)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, cali_info->power_index_offset[p], delta, thermal_value, rtlefu->eeprom_thermalmeter, cali_info->thermal_value); #else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value); #endif } } @@ -638,166 +650,166 @@ odm_txpowertracking_callback_thermal_meter( #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) if (thermal_value > rtlefu->eeprom_thermalmeter) #else - if (thermal_value > p_hal_data->eeprom_thermal_meter) + if (thermal_value > hal_data->eeprom_thermal_meter) #endif #else - if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) #endif { #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature(%d) higher than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter); #else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter); #endif - if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 || - p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A || - p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B || - p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 || + dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A || + dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B || + dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel); } } else { #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature(%d) lower than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter); #else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter); #endif - if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 || - p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A || - p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B || - p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 || + dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A || + dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B || + dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, indexforchannel); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel); } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel); } } - p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/ - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->bb_swing_idx_ofdm[p]; + cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("p_rf_calibrate_info->thermal_value = %d thermal_value= %d\n", p_rf_calibrate_info->thermal_value, thermal_value)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value); - p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ } - if (p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - if (xtal_offset_eanble != 0 && p_rf_calibrate_info->txpowertrack_control && (rtlefu->eeprom_thermalmeter != 0xff)) { + if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (rtlefu->eeprom_thermalmeter != 0xff)) { #else - if (xtal_offset_eanble != 0 && p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) { + if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) { #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n")); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n"); #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) if (thermal_value > rtlefu->eeprom_thermalmeter) { #else - if (thermal_value > p_hal_data->eeprom_thermal_meter) { + if (thermal_value > hal_data->eeprom_thermal_meter) { #endif #else - if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) { + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) { #endif #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature(%d) higher than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter); #else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter); #endif - (*c.odm_txxtaltrack_set_xtal)(p_dm_odm); + (*c.odm_txxtaltrack_set_xtal)(dm); } else { #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature(%d) lower than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter); #else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter); #endif - (*c.odm_txxtaltrack_set_xtal)(p_dm_odm); + (*c.odm_txxtaltrack_set_xtal)(dm); } } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n")); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********End Xtal Tracking**********\n"); } #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) /* Wait sacn to do IQK by RF Jenyu*/ - if (*p_dm_odm->p_is_scan_in_process == false) { + if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) { if (!IS_HARDWARE_TYPE_8723B(adapter)) { /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ if (delta_IQK >= c.threshold_iqk) { - p_rf_calibrate_info->thermal_value_iqk = thermal_value; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk)); - if (!p_rf_calibrate_info->is_iqk_in_progress) - (*c.do_iqk)(p_dm_odm, delta_IQK, thermal_value, 8); + cali_info->thermal_value_iqk = thermal_value; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk); + if (!cali_info->is_iqk_in_progress) + (*c.do_iqk)(dm, delta_IQK, thermal_value, 8); } } } - if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_A] != 0) { - if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) { - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk)); - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); - } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) { - s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk); - - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + if (cali_info->dpk_thermal[RF_PATH_A] != 0) { + if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) { + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk)); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk); + + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); } else { - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); } } - if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_B] != 0) { - if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) { - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk)); - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); - } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) { - s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk); - - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + if (cali_info->dpk_thermal[RF_PATH_B] != 0) { + if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) { + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk)); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk); + + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); } else { - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); } } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===odm_txpowertracking_callback_thermal_meter\n")); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n"); - p_rf_calibrate_info->tx_powercount = 0; + cali_info->tx_powercount = 0; } @@ -808,7 +820,7 @@ odm_txpowertracking_callback_thermal_meter( void odm_reset_iqk_result( - void *p_dm_void + void *dm_void ) { return; @@ -835,13 +847,14 @@ u8 odm_get_right_chnl_place_for_iqk(u8 chnl) void odm_iq_calibrate( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; + struct dm_iqk_info *iqk_info = &dm->IQK_info; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (*p_dm_odm->p_is_fcs_mode_enable) + if (*dm->is_fcs_mode_enable) return; #endif @@ -850,65 +863,45 @@ odm_iq_calibrate( return; #endif - if (p_dm_odm->is_linked) { - if ((*p_dm_odm->p_channel != p_dm_odm->pre_channel) && (!*p_dm_odm->p_is_scan_in_process)) { - p_dm_odm->pre_channel = *p_dm_odm->p_channel; - p_dm_odm->linked_interval = 0; + if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) { + if ((*dm->channel != dm->pre_channel) && (!*dm->is_scan_in_process)) { + dm->pre_channel = *dm->channel; + dm->linked_interval = 0; } - if (p_dm_odm->linked_interval < 3) - p_dm_odm->linked_interval++; - - if (p_dm_odm->linked_interval == 2) { - if (IS_HARDWARE_TYPE_8814A(adapter)) { -#if (RTL8814A_SUPPORT == 1) - phy_iq_calibrate_8814a(p_dm_odm, false); -#endif - } - -#if (RTL8822B_SUPPORT == 1) - else if (IS_HARDWARE_TYPE_8822B(adapter)) - phy_iq_calibrate_8822b(p_dm_odm, false); -#endif + if (dm->linked_interval < 3) + dm->linked_interval++; -#if (RTL8821C_SUPPORT == 1) - else if (IS_HARDWARE_TYPE_8821C(adapter)) - phy_iq_calibrate_8821c(p_dm_odm, false); -#endif - -#if (RTL8821A_SUPPORT == 1) - else if (IS_HARDWARE_TYPE_8821(adapter)) - phy_iq_calibrate_8821a(p_dm_odm, false); -#endif - } + if (dm->linked_interval == 2) + halrf_iqk_trigger(dm, false); } else - p_dm_odm->linked_interval = 0; + dm->linked_interval = 0; } -void phydm_rf_init(void *p_dm_void) +void phydm_rf_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - odm_txpowertracking_init(p_dm_odm); + struct dm_struct *dm = (struct dm_struct *)dm_void; + odm_txpowertracking_init(dm); #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - odm_clear_txpowertracking_state(p_dm_odm); + odm_clear_txpowertracking_state(dm); #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - phy_iq_calibrate_8814a_init(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8814A) + phy_iq_calibrate_8814a_init(dm); #endif #endif } -void phydm_rf_watchdog(void *p_dm_void) +void phydm_rf_watchdog(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - odm_txpowertracking_check(p_dm_odm); - /*if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)*/ - /*odm_iq_calibrate(p_dm_odm);*/ + odm_txpowertracking_check(dm); + /*if (dm->support_ic_type & ODM_IC_11AC_SERIES)*/ + /*odm_iq_calibrate(dm);*/ #endif } diff --git a/hal/phydm/halrf/halphyrf_ce.h b/hal/phydm/halrf/halphyrf_ce.h index 731842f..a4a8938 100644 --- a/hal/phydm/halrf/halphyrf_ce.h +++ b/hal/phydm/halrf/halphyrf_ce.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #ifndef __HAL_PHY_RF_H__ #define __HAL_PHY_RF_H__ @@ -59,7 +64,7 @@ typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **); typedef void(*func_swing_xtal)(void *, s8 **, s8 **); typedef void(*func_set_xtal)(void *); -struct _TXPWRTRACK_CFG { +struct txpwrtrack_cfg { u8 swing_table_size_cck; u8 swing_table_size_ofdm; u8 threshold_iqk; @@ -78,24 +83,24 @@ struct _TXPWRTRACK_CFG { void configure_txpower_track( - void *p_dm_void, - struct _TXPWRTRACK_CFG *p_config + void *dm_void, + struct txpwrtrack_cfg *config ); void odm_clear_txpowertracking_state( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_callback_thermal_meter( #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - void *p_dm_void -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - void *p_dm_odm + void *dm_void +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + void *dm #else - struct _ADAPTER *adapter + void *adapter #endif ); @@ -106,14 +111,14 @@ odm_txpowertracking_callback_thermal_meter( void odm_reset_iqk_result( - void *p_dm_void + void *dm_void ); u8 odm_get_right_chnl_place_for_iqk( u8 chnl ); -void phydm_rf_init(void *p_dm_void); -void phydm_rf_watchdog(void *p_dm_void); +void phydm_rf_init(void *dm_void); +void phydm_rf_watchdog(void *dm_void); #endif /* #ifndef __HAL_PHY_RF_H__ */ diff --git a/hal/phydm/halrf/halphyrf_win.c b/hal/phydm/halrf/halphyrf_win.c index 980e0a8..bb4c000 100644 --- a/hal/phydm/halrf/halphyrf_win.c +++ b/hal/phydm/halrf/halphyrf_win.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" @@ -37,66 +32,66 @@ } while (0) void configure_txpower_track( - struct PHY_DM_STRUCT *p_dm_odm, - struct _TXPWRTRACK_CFG *p_config + struct dm_struct *dm, + struct txpwrtrack_cfg *config ) { #if RTL8192E_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8192E) - configure_txpower_track_8192e(p_config); + if (dm->support_ic_type == ODM_RTL8192E) + configure_txpower_track_8192e(config); #endif #if RTL8821A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8821) - configure_txpower_track_8821a(p_config); + if (dm->support_ic_type == ODM_RTL8821) + configure_txpower_track_8821a(config); #endif #if RTL8812A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8812) - configure_txpower_track_8812a(p_config); + if (dm->support_ic_type == ODM_RTL8812) + configure_txpower_track_8812a(config); #endif #if RTL8188E_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - configure_txpower_track_8188e(p_config); + if (dm->support_ic_type == ODM_RTL8188E) + configure_txpower_track_8188e(config); #endif #if RTL8188F_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8188F) - configure_txpower_track_8188f(p_config); + if (dm->support_ic_type == ODM_RTL8188F) + configure_txpower_track_8188f(config); #endif #if RTL8723B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8723B) - configure_txpower_track_8723b(p_config); + if (dm->support_ic_type == ODM_RTL8723B) + configure_txpower_track_8723b(config); #endif #if RTL8814A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8814A) - configure_txpower_track_8814a(p_config); + if (dm->support_ic_type == ODM_RTL8814A) + configure_txpower_track_8814a(config); #endif #if RTL8703B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8703B) - configure_txpower_track_8703b(p_config); + if (dm->support_ic_type == ODM_RTL8703B) + configure_txpower_track_8703b(config); #endif #if RTL8822B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8822B) - configure_txpower_track_8822b(p_config); + if (dm->support_ic_type == ODM_RTL8822B) + configure_txpower_track_8822b(config); #endif #if RTL8723D_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8723D) - configure_txpower_track_8723d(p_config); + if (dm->support_ic_type == ODM_RTL8723D) + configure_txpower_track_8723d(config); #endif /* JJ ADD 20161014 */ #if RTL8710B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8710B) - configure_txpower_track_8710b(p_config); + if (dm->support_ic_type == ODM_RTL8710B) + configure_txpower_track_8710b(config); #endif #if RTL8821C_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - configure_txpower_track_8821c(p_config); + if (dm->support_ic_type == ODM_RTL8821C) + configure_txpower_track_8821c(config); #endif } @@ -111,75 +106,75 @@ void configure_txpower_track( * ********************************************************************** */ void odm_clear_txpowertracking_state( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); + PHAL_DATA_TYPE hal_data = GET_HAL_DATA((PADAPTER)(dm->adapter)); u8 p = 0; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); - p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index; - p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index; - p_rf_calibrate_info->CCK_index = 0; + cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index; + cali_info->bb_swing_idx_cck = cali_info->default_cck_index; + cali_info->CCK_index = 0; - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) { - p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index; - p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index; - p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index; + for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) { + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index; + cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index; + cali_info->OFDM_index[p] = cali_info->default_ofdm_index; - p_rf_calibrate_info->power_index_offset[p] = 0; - p_rf_calibrate_info->delta_power_index[p] = 0; - p_rf_calibrate_info->delta_power_index_last[p] = 0; + cali_info->power_index_offset[p] = 0; + cali_info->delta_power_index[p] = 0; + cali_info->delta_power_index_last[p] = 0; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/ - p_rf_calibrate_info->remnant_ofdm_swing_idx[p] = 0; - p_rf_calibrate_info->kfree_offset[p] = 0; + cali_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/ + cali_info->remnant_ofdm_swing_idx[p] = 0; + cali_info->kfree_offset[p] = 0; } - p_rf_calibrate_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/ - p_rf_calibrate_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/ - p_rf_calibrate_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/ - p_rf_calibrate_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/ - p_rf_calibrate_info->remnant_cck_swing_idx = 0; - p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter; + cali_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/ + cali_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/ + cali_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/ + cali_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/ + cali_info->remnant_cck_swing_idx = 0; + cali_info->thermal_value = hal_data->eeprom_thermal_meter; - p_rf_calibrate_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */ - p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */ + cali_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */ + cali_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */ } void odm_txpowertracking_callback_thermal_meter( #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm #else - struct _ADAPTER *adapter + void *adapter #endif ) { #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + struct dm_struct *dm = &hal_data->DM_OutSrc; #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; + struct dm_struct *dm = &hal_data->odmpriv; #endif #endif - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + struct dm_iqk_info *iqk_info = &dm->IQK_info; u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; s8 diff_DPK[4] = {0}; u8 thermal_value_avg_count = 0; u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4; u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ - u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(p_hal_data->current_channel) */ - u8 power_tracking_type = p_hal_data->RfPowerTrackingType; + u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */ + u8 power_tracking_type = hal_data->RfPowerTrackingType; u8 xtal_offset_eanble = 0; s8 thermal_value_temp = 0; - struct _TXPWRTRACK_CFG c; + struct txpwrtrack_cfg c; /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ u8 *delta_swing_table_idx_tup_a = NULL; @@ -197,46 +192,46 @@ odm_txpowertracking_callback_thermal_meter( /* 4 2. Initilization ( 7 steps in total ) */ - configure_txpower_track(p_dm_odm, &c); + configure_txpower_track(dm, &c); - (*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, + (*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b); - if (p_dm_odm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/ - (*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c, + if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/ + (*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c, (u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d); /* JJ ADD 20161014 */ - if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/ - (*c.get_delta_swing_xtal_table)(p_dm_odm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down); + if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/ + (*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down); - p_rf_calibrate_info->txpowertracking_callback_cnt++; /*cosa add for debug*/ - p_rf_calibrate_info->is_txpowertracking_init = true; + cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/ + cali_info->is_txpowertracking_init = true; - /*p_rf_calibrate_info->txpowertrack_control = p_hal_data->txpowertrack_control; + /*cali_info->txpowertrack_control = hal_data->txpowertrack_control; We should keep updating the control variable according to HalData. rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */ #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) #if (MP_DRIVER == 1) - p_rf_calibrate_info->rega24 = 0x090e1317; + cali_info->rega24 = 0x090e1317; #endif #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (*(p_dm_odm->p_mp_mode) == true) - p_rf_calibrate_info->rega24 = 0x090e1317; + if (*(dm->mp_mode) == true) + cali_info->rega24 = 0x090e1317; #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("===>odm_txpowertracking_callback_thermal_meter\n p_rf_calibrate_info->bb_swing_idx_cck_base: %d, p_rf_calibrate_info->bb_swing_idx_ofdm_base[A]: %d, p_rf_calibrate_info->default_ofdm_index: %d\n", - p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A], p_rf_calibrate_info->default_ofdm_index)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n", + cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("p_rf_calibrate_info->txpowertrack_control=%d, p_hal_data->eeprom_thermal_meter %d\n", p_rf_calibrate_info->txpowertrack_control, p_hal_data->eeprom_thermal_meter)); - thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "cali_info->txpowertrack_control=%d, hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control, hal_data->eeprom_thermal_meter); + thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ - thermal_value_temp = thermal_value + phydm_get_thermal_offset(p_dm_odm); + thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("thermal_value_temp(%d) = thermal_value(%d) + power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(p_dm_odm))); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "thermal_value_temp(%d) = thermal_value(%d) + power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm)); if (thermal_value_temp > 63) thermal_value = 63; @@ -246,102 +241,102 @@ odm_txpowertracking_callback_thermal_meter( thermal_value = thermal_value_temp; /*add log by zhao he, check c80/c94/c14/ca0 value*/ - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD); - regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD); - regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD); - regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4)); + if (dm->support_ic_type == ODM_RTL8723D) { + regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4); } /* JJ ADD 20161014 */ - if (p_dm_odm->support_ic_type == ODM_RTL8710B) { - regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD); - regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD); - regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD); - regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4)); + if (dm->support_ic_type == ODM_RTL8710B) { + regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4); } - if (!p_rf_calibrate_info->txpowertrack_control) + if (!cali_info->txpowertrack_control) return; - if (p_hal_data->eeprom_thermal_meter == 0xff) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no pg, p_hal_data->eeprom_thermal_meter = 0x%x\n", p_hal_data->eeprom_thermal_meter)); + if (hal_data->eeprom_thermal_meter == 0xff) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter); return; } /*4 3. Initialize ThermalValues of rf_calibrate_info*/ - if (p_rf_calibrate_info->is_reloadtxpowerindex) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n")); + if (cali_info->is_reloadtxpowerindex) + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "reload ofdm index for band switch\n"); /*4 4. Calculate average thermal meter*/ - p_rf_calibrate_info->thermal_value_avg[p_rf_calibrate_info->thermal_value_avg_index] = thermal_value; - p_rf_calibrate_info->thermal_value_avg_index++; - if (p_rf_calibrate_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ - p_rf_calibrate_info->thermal_value_avg_index = 0; + cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value; + cali_info->thermal_value_avg_index++; + if (cali_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ + cali_info->thermal_value_avg_index = 0; for (i = 0; i < c.average_thermal_num; i++) { - if (p_rf_calibrate_info->thermal_value_avg[i]) { - thermal_value_avg += p_rf_calibrate_info->thermal_value_avg[i]; + if (cali_info->thermal_value_avg[i]) { + thermal_value_avg += cali_info->thermal_value_avg[i]; thermal_value_avg_count++; } } if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */ thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); - p_rf_calibrate_info->thermal_value_delta = thermal_value - p_hal_data->eeprom_thermal_meter; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + cali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, hal_data->eeprom_thermal_meter); } /* 4 5. Calculate delta, delta_LCK, delta_IQK. */ /* "delta" here is used to determine whether thermal value changes or not. */ - delta = (thermal_value > p_rf_calibrate_info->thermal_value) ? (thermal_value - p_rf_calibrate_info->thermal_value) : (p_rf_calibrate_info->thermal_value - thermal_value); - delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value); - delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value); - - if (p_rf_calibrate_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/ - p_rf_calibrate_info->thermal_value_iqk = thermal_value; - delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use thermal_value for IQK\n")); + delta = (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value); + delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value); + delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value); + + if (cali_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/ + cali_info->thermal_value_iqk = thermal_value; + delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n"); } - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - diff_DPK[p] = (s8)thermal_value - (s8)p_rf_calibrate_info->dpk_thermal[p]; + for (p = RF_PATH_A; p < c.rf_path_count; p++) + diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p]; /*4 6. If necessary, do LCK.*/ - if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/ - if (p_rf_calibrate_info->thermal_value_lck == 0xff) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); - p_rf_calibrate_info->thermal_value_lck = thermal_value; + if (!(dm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/ + if (cali_info->thermal_value_lck == 0xff) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, do LCK\n"); + cali_info->thermal_value_lck = thermal_value; /*Use RTLCK, so close power tracking driver LCK*/ - if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) { + if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) { if (c.phy_lc_calibrate) - (*c.phy_lc_calibrate)(p_dm_odm); + (*c.phy_lc_calibrate)(dm); } - delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value); + delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK); /* Wait sacn to do LCK by RF Jenyu*/ - if (*p_dm_odm->p_is_scan_in_process == false) { + if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) { /* Delta temperature is equal to or larger than 20 centigrade.*/ if (delta_LCK >= c.threshold_iqk) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk)); - p_rf_calibrate_info->thermal_value_lck = thermal_value; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk); + cali_info->thermal_value_lck = thermal_value; /*Use RTLCK, so close power tracking driver LCK*/ - if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) { + if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) { if (c.phy_lc_calibrate) - (*c.phy_lc_calibrate)(p_dm_odm); + (*c.phy_lc_calibrate)(dm); } } } @@ -349,12 +344,12 @@ odm_txpowertracking_callback_thermal_meter( /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ - if (delta > 0 && p_rf_calibrate_info->txpowertrack_control) { + if (delta > 0 && cali_info->txpowertrack_control) { /* "delta" here is used to record the absolute value of differrence. */ #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - delta = thermal_value > p_hal_data->eeprom_thermal_meter ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value); + delta = thermal_value > hal_data->eeprom_thermal_meter ? (thermal_value - hal_data->eeprom_thermal_meter) : (hal_data->eeprom_thermal_meter - thermal_value); #else - delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value); + delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value); #endif if (delta >= TXPWR_TRACK_TABLE_SIZE) delta = TXPWR_TRACK_TABLE_SIZE - 1; @@ -362,120 +357,120 @@ odm_txpowertracking_callback_thermal_meter( /*4 7.1 The Final Power index = BaseIndex + power_index_offset*/ #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (thermal_value > p_hal_data->eeprom_thermal_meter) { + if (thermal_value > hal_data->eeprom_thermal_meter) { #else - if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) { + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) { #endif - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { - p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/ switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta])); - - p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_B: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]); + + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; - case ODM_RF_PATH_C: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta])); + case RF_PATH_C: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]); - p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; - case ODM_RF_PATH_D: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta])); + case RF_PATH_D: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]); - p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]); - p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; } } /* JJ ADD 20161014 */ - if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { /*Save xtal_offset from Xtal table*/ - p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta])); - p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_up[delta]; + cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]); + cali_info->xtal_offset = delta_swing_table_xtal_up[delta]; - if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset) + if (cali_info->xtal_offset_last == cali_info->xtal_offset) xtal_offset_eanble = 0; else xtal_offset_eanble = 1; } } else { - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { - p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/ switch (p) { - case ODM_RF_PATH_B: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta])); - p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_B: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; - case ODM_RF_PATH_C: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta])); - p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_C: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; - case ODM_RF_PATH_D: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta])); - p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + case RF_PATH_D: + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta])); - p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta]; - p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); break; } } /* JJ ADD 20161014 */ - if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { /*Save xtal_offset from Xtal table*/ - p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta])); - p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_down[delta]; + cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]); + cali_info->xtal_offset = delta_swing_table_xtal_down[delta]; - if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset) + if (cali_info->xtal_offset_last == cali_info->xtal_offset) xtal_offset_eanble = 0; else xtal_offset_eanble = 1; @@ -483,245 +478,245 @@ odm_txpowertracking_callback_thermal_meter( } - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p)); + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p); - if (p_rf_calibrate_info->delta_power_index[p] == p_rf_calibrate_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/ - p_rf_calibrate_info->power_index_offset[p] = 0; + if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/ + cali_info->power_index_offset[p] = 0; else - p_rf_calibrate_info->power_index_offset[p] = p_rf_calibrate_info->delta_power_index[p] - p_rf_calibrate_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/ + cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, p_rf_calibrate_info->power_index_offset[p], p_rf_calibrate_info->delta_power_index[p], p_rf_calibrate_info->delta_power_index_last[p])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]); - p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] + p_rf_calibrate_info->power_index_offset[p]; - p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_rf_calibrate_info->power_index_offset[p]; + cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p]; + cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p]; - p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->CCK_index; - p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->OFDM_index[p]; + cali_info->bb_swing_idx_cck = cali_info->CCK_index; + cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p]; /*************Print BB Swing base and index Offset*************/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->power_index_offset[p])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p], p_rf_calibrate_info->power_index_offset[p])); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]); /*4 7.1 Handle boundary conditions of index.*/ - if (p_rf_calibrate_info->OFDM_index[p] > c.swing_table_size_ofdm - 1) - p_rf_calibrate_info->OFDM_index[p] = c.swing_table_size_ofdm - 1; - else if (p_rf_calibrate_info->OFDM_index[p] <= OFDM_min_index) - p_rf_calibrate_info->OFDM_index[p] = OFDM_min_index; + if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1) + cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1; + else if (cali_info->OFDM_index[p] <= OFDM_min_index) + cali_info->OFDM_index[p] = OFDM_min_index; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("\n\n========================================================================================================\n")); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "\n\n========================================================================================================\n"); - if (p_rf_calibrate_info->CCK_index > c.swing_table_size_cck - 1) - p_rf_calibrate_info->CCK_index = c.swing_table_size_cck - 1; - else if (p_rf_calibrate_info->CCK_index <= 0) - p_rf_calibrate_info->CCK_index = 0; + if (cali_info->CCK_index > c.swing_table_size_cck - 1) + cali_info->CCK_index = c.swing_table_size_cck - 1; + else if (cali_info->CCK_index <= 0) + cali_info->CCK_index = 0; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, p_rf_calibrate_info->thermal_value: %d\n", - p_rf_calibrate_info->txpowertrack_control, thermal_value, p_rf_calibrate_info->thermal_value)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n", + cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - p_rf_calibrate_info->power_index_offset[p] = 0; + for (p = RF_PATH_A; p < c.rf_path_count; p++) + cali_info->power_index_offset[p] = 0; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", - p_rf_calibrate_info->CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base)); /*Print Swing base & current*/ + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", + cali_info->CCK_index, cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/ - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n", - p_rf_calibrate_info->OFDM_index[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p])); + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n", + cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]); } - if ((p_dm_odm->support_ic_type & ODM_RTL8814A)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("power_tracking_type=%d\n", power_tracking_type)); + if ((dm->support_ic_type & ODM_RTL8814A)) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type); if (power_tracking_type == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); } else if (power_tracking_type == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_2G_TSSI_5G_MODE, p, 0); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0); } else if (power_tracking_type == 2) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_5G_TSSI_2G_MODE, p, 0); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0); } else if (power_tracking_type == 3) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0); } - p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ - } else if ((p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_A] != 0 || - p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_B] != 0 || - p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_C] != 0 || - p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_D] != 0) && - p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) { + } else if ((cali_info->power_index_offset[RF_PATH_A] != 0 || + cali_info->power_index_offset[RF_PATH_B] != 0 || + cali_info->power_index_offset[RF_PATH_C] != 0 || + cali_info->power_index_offset[RF_PATH_D] != 0) && + cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) { /* 4 7.2 Configure the Swing Table to adjust Tx Power. */ - p_rf_calibrate_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/ + cali_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/ /* */ /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */ /* to increase TX power. Otherwise, EVM will be bad. */ /* */ /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ - if (thermal_value > p_rf_calibrate_info->thermal_value) { - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value)); + if (thermal_value > cali_info->thermal_value) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value); } - } else if (thermal_value < p_rf_calibrate_info->thermal_value) { /*Low temperature*/ - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", - p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value)); + } else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value); } } #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (thermal_value > p_hal_data->eeprom_thermal_meter) + if (thermal_value > hal_data->eeprom_thermal_meter) #else - if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) #endif { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter); - if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 || - p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A || - p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B || - p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 || + dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A || + dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B || + dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel); } } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter); - if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 || - p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A || - p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B || - p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 || + dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A || + dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B || + dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, indexforchannel); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel); } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel); } } - p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/ - for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) - p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->bb_swing_idx_ofdm[p]; + cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("p_rf_calibrate_info->thermal_value = %d thermal_value= %d\n", p_rf_calibrate_info->thermal_value, thermal_value)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value); - p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ } - if (p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ - if (xtal_offset_eanble != 0 && p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) { + if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n")); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n"); #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - if (thermal_value > p_hal_data->eeprom_thermal_meter) { + if (thermal_value > hal_data->eeprom_thermal_meter) { #else - if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) { + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) { #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); - (*c.odm_txxtaltrack_set_xtal)(p_dm_odm); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter); + (*c.odm_txxtaltrack_set_xtal)(dm); } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); - (*c.odm_txxtaltrack_set_xtal)(p_dm_odm); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter); + (*c.odm_txxtaltrack_set_xtal)(dm); } } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n")); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********End Xtal Tracking**********\n"); } #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) /* Wait sacn to do IQK by RF Jenyu*/ - if (*p_dm_odm->p_is_scan_in_process == false) { + if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) { if (!IS_HARDWARE_TYPE_8723B(adapter)) { /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ if (delta_IQK >= c.threshold_iqk) { - p_rf_calibrate_info->thermal_value_iqk = thermal_value; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk)); - if (!p_rf_calibrate_info->is_iqk_in_progress) - (*c.do_iqk)(p_dm_odm, delta_IQK, thermal_value, 8); + cali_info->thermal_value_iqk = thermal_value; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk); + if (!cali_info->is_iqk_in_progress) + (*c.do_iqk)(dm, delta_IQK, thermal_value, 8); } } } - if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_A] != 0) { - if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) { - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk)); - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); - } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) { - s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk); - - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + if (cali_info->dpk_thermal[RF_PATH_A] != 0) { + if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) { + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk)); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk); + + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); } else { - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); } } - if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_B] != 0) { - if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) { - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk)); - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); - } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) { - s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk); - - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + if (cali_info->dpk_thermal[RF_PATH_B] != 0) { + if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) { + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk)); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk); + + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); } else { - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); } } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===odm_txpowertracking_callback_thermal_meter\n")); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n"); - p_rf_calibrate_info->tx_powercount = 0; + cali_info->tx_powercount = 0; } @@ -732,7 +727,7 @@ odm_txpowertracking_callback_thermal_meter( void odm_reset_iqk_result( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { return; @@ -759,69 +754,64 @@ u8 odm_get_right_chnl_place_for_iqk(u8 chnl) void odm_iq_calibrate( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - + void *adapter = dm->adapter; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("=>%s\n" , __FUNCTION__)); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (*p_dm_odm->p_is_fcs_mode_enable) + if (*dm->is_fcs_mode_enable) return; #endif - if (p_dm_odm->is_linked) { - RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("interval=%d ch=%d prech=%d scan=%s\n", p_dm_odm->linked_interval, - *p_dm_odm->p_channel, p_dm_odm->pre_channel, *p_dm_odm->p_is_scan_in_process == TRUE ? "TRUE":"FALSE")); + if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) { + RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("interval=%d ch=%d prech=%d scan=%s\n", dm->linked_interval, + *dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE")); - if (*p_dm_odm->p_channel != p_dm_odm->pre_channel) { - p_dm_odm->pre_channel = *p_dm_odm->p_channel; - p_dm_odm->linked_interval = 0; + if (*dm->channel != dm->pre_channel) { + dm->pre_channel = *dm->channel; + dm->linked_interval = 0; } - if ((p_dm_odm->linked_interval < 3) && (!*p_dm_odm->p_is_scan_in_process)) - p_dm_odm->linked_interval++; + if ((dm->linked_interval < 3) && (!*dm->is_scan_in_process)) + dm->linked_interval++; - if (p_dm_odm->linked_interval == 2) - PHY_IQCalibrate(adapter, false); + if (dm->linked_interval == 2) + PHY_IQCalibrate((PADAPTER)adapter, false); } else - p_dm_odm->linked_interval = 0; + dm->linked_interval = 0; - RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, p_dm_odm->linked_interval, - *p_dm_odm->p_channel, p_dm_odm->pre_channel, *p_dm_odm->p_is_scan_in_process == TRUE?"TRUE":"FALSE")); + RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, dm->linked_interval, + *dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE?"TRUE":"FALSE")); } -void phydm_rf_init(struct PHY_DM_STRUCT *p_dm_odm) +void phydm_rf_init(struct dm_struct *dm) { - odm_txpowertracking_init(p_dm_odm); + odm_txpowertracking_init(dm); #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - odm_clear_txpowertracking_state(p_dm_odm); + odm_clear_txpowertracking_state(dm); #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - phy_iq_calibrate_8814a_init(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8814A) + phy_iq_calibrate_8814a_init(dm); #endif #endif } -void phydm_rf_watchdog(struct PHY_DM_STRUCT *p_dm_odm) +void phydm_rf_watchdog(struct dm_struct *dm) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct _ADAPTER *adapter = p_dm_odm->adapter; - - odm_txpowertracking_check(p_dm_odm); - - if(!adapter->MgntInfo.IQKBeforeConnection) { - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - odm_iq_calibrate(p_dm_odm); - } + odm_txpowertracking_check(dm); + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + odm_iq_calibrate(dm); #endif } diff --git a/hal/phydm/halrf/halphyrf_win.h b/hal/phydm/halrf/halphyrf_win.h index e11433a..0d36a75 100644 --- a/hal/phydm/halrf/halphyrf_win.h +++ b/hal/phydm/halrf/halphyrf_win.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,28 +11,45 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_PHY_RF_H__ #define __HAL_PHY_RF_H__ #if (RTL8814A_SUPPORT == 1) - #include "halrf/rtl8814a/halrf_iqk_8814a.h" + #if RT_PLATFORM == PLATFORM_MACOSX + #include "rtl8814a/halrf_iqk_8814a.h" + #else + #include "halrf/rtl8814a/halrf_iqk_8814a.h" + #endif #endif #if (RTL8822B_SUPPORT == 1) - #include "halrf/rtl8822b/halrf_iqk_8822b.h" - #include "../mac/Halmac_type.h" + #if RT_PLATFORM == PLATFORM_MACOSX + #include "rtl8822b/halrf_iqk_8822b.h" + #include "../../MAC/Halmac_type.h" + #else + #include "halrf/rtl8822b/halrf_iqk_8822b.h" + #include "../mac/Halmac_type.h" + #endif +#endif + +#if RT_PLATFORM == PLATFORM_MACOSX + #include "halrf_powertracking_win.h" + #include "halrf_kfree.h" + #include "halrf_txgapcal.h" +#else + #include "halrf/halrf_powertracking_win.h" + #include "halrf/halrf_kfree.h" + #include "halrf/halrf_txgapcal.h" #endif -#include "halrf/halrf_powertracking_win.h" -#include "halrf/halrf_kfree.h" + #if (RTL8821C_SUPPORT == 1) - #include "halrf/rtl8821c/halrf_iqk_8821c.h" + #if RT_PLATFORM == PLATFORM_MACOSX + #include "rtl8821c/halrf_iqk_8821c.h" + #else + #include "halrf/rtl8821c/halrf_iqk_8821c.h" + #endif #endif enum spur_cal_method { @@ -58,7 +75,7 @@ typedef void (*func_swing_xtal)(void *, s8 **, s8 **); typedef void (*func_set_xtal)(void *); typedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **); -struct _TXPWRTRACK_CFG { +struct txpwrtrack_cfg { u8 swing_table_size_cck; u8 swing_table_size_ofdm; u8 threshold_iqk; @@ -78,22 +95,22 @@ struct _TXPWRTRACK_CFG { void configure_txpower_track( - struct PHY_DM_STRUCT *p_dm_odm, - struct _TXPWRTRACK_CFG *p_config + struct dm_struct *dm, + struct txpwrtrack_cfg *config ); void odm_clear_txpowertracking_state( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); void odm_txpowertracking_callback_thermal_meter( #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm #else - struct _ADAPTER *adapter + void *adapter #endif ); @@ -104,15 +121,15 @@ odm_txpowertracking_callback_thermal_meter( void odm_reset_iqk_result( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u8 odm_get_right_chnl_place_for_iqk( u8 chnl ); -void odm_iq_calibrate(struct PHY_DM_STRUCT *p_dm_odm); -void phydm_rf_init(struct PHY_DM_STRUCT *p_dm_odm); -void phydm_rf_watchdog(struct PHY_DM_STRUCT *p_dm_odm); +void odm_iq_calibrate(struct dm_struct *dm); +void phydm_rf_init(struct dm_struct *dm); +void phydm_rf_watchdog(struct dm_struct *dm); #endif /* #ifndef __HAL_PHY_RF_H__ */ diff --git a/hal/phydm/halrf/halrf.c b/hal/phydm/halrf/halrf.c index 1e33d9d..9760014 100644 --- a/hal/phydm/halrf/halrf.c +++ b/hal/phydm/halrf/halrf.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ /* ************************************************************ * include files @@ -25,41 +30,935 @@ #include "mp_precomp.h" #include "phydm_precomp.h" -void phydm_rf_basic_profile( - void *p_dm_void, +void halrf_basic_profile( + void *dm_void, u32 *_used, char *output, u32 *_out_len ) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 used = *_used; u32 out_len = *_out_len; /* HAL RF version List */ - PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% HAL RF version %")); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Power Tracking", HALRF_POWRTRACKING_VER)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "IQK", HALRF_IQK_VER)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "LCK", HALRF_LCK_VER)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "DPK", HALRF_DPK_VER)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-35s\n", "% HAL RF version %"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "Power Tracking", + HALRF_POWRTRACKING_VER); + + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s %s\n", "IQK", + (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD)? "FW" : HALRF_IQK_VER, + (halrf_match_iqk_version(dm_void))? "(match)" : "(mismatch)"); + + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "LCK", HALRF_LCK_VER); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "DPK", HALRF_DPK_VER); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "KFREE", HALRF_KFREE_VER); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "TX 2G Current Calibration", + HALRF_PABIASK_VER); *_used = used; *_out_len = out_len; -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +#endif } +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) +void +_iqk_page_switch( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + if (dm->support_ic_type == ODM_RTL8821C) + odm_write_4byte(dm, 0x1b00, 0xf8000008); + else + odm_write_4byte(dm, 0x1b00, 0xf800000a); +} + +u32 halrf_psd_log2base(u32 val) +{ + u8 j; + u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0; + u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200, + 174, 151, 132, 115, 100, 86, 74, 62, 51, 42, + 32, 23, 15, 7, 0 + }; + + if (val == 0) + return 0; + + tmp = val; + + while (1) { + if (tmp == 1) + break; + + tmp = (tmp >> 1); + shiftcount++; + } + + + val_integerd_b = shiftcount + 1; + + tmp2 = 1; + for (j = 1; j <= val_integerd_b; j++) + tmp2 = tmp2 * 2; + + tmp = (val * 100) / tmp2; + tindex = tmp / 5; + + if (tindex > 20) + tindex = 20; + + val_fractiond_b = table_fraction[tindex]; + + result = val_integerd_b * 100 - val_fractiond_b; + + return result; + + +} + +void phydm_get_iqk_cfir( + void *dm_void, + u8 idx, + u8 path, + boolean debug +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + u8 i, ch; + u32 tmp; + + if (debug) + ch = 2; + else + ch = 0; + odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1); + if (idx == 0) + odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x3); + else + odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x1); + odm_set_bb_reg(dm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10); + for (i = 0; i < 8; i++) { + odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0xe0000001 + (i * 4)); + tmp = odm_get_bb_reg(dm, 0x1bfc, MASKDWORD); + iqk_info->iqk_cfir_real[ch][path][idx][i] = (tmp & 0x0fff0000) >> 16; + iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0xfff; + } + odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0); + odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0); +} + +void +halrf_iqk_xym_enable( + struct dm_struct *dm, + u8 xym_enable + ) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (xym_enable == 0) + iqk_info->xym_read = false; + else + iqk_info->xym_read = true; + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s %s\n", "xym_read = ", (iqk_info->xym_read ? "true": "false")); +} + +void +halrf_iqk_xym_read( + void *dm_void, + u8 path, + u8 xym_type /*0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/ + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 i, start, num; + u32 tmp1, tmp2; + + if (!iqk_info->xym_read) + return; + + if (*dm->band_width == 0) { + start = 3; + num = 4; + }else if (*dm->band_width == 1) { + start = 2; + num = 6; + }else { + start = 0; + num = 10; + } + + odm_write_4byte(dm, 0x1b00, 0xf8000008); + tmp1 = odm_read_4byte(dm, 0x1b1c); + odm_write_4byte(dm, 0x1b1c, 0xa2193c32); + + odm_write_4byte(dm, 0x1b00, 0xf800000a); + tmp2 = odm_read_4byte(dm, 0x1b1c); + odm_write_4byte(dm, 0x1b1c, 0xa2193c32); + + for (path = 0; path < 2; path ++) { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + switch(xym_type){ + case 0: + for (i = 0; i < num ;i++) { + odm_write_4byte(dm, 0x1b14, 0xe6+start+i); + odm_write_4byte(dm, 0x1b14, 0x0); + iqk_info->rx_xym[path][i] = odm_read_4byte(dm, 0x1b38); + } + break; + case 1: + for (i = 0; i < num ;i++) { + odm_write_4byte(dm, 0x1b14, 0xe6+start+i); + odm_write_4byte(dm, 0x1b14, 0x0); + iqk_info->tx_xym[path][i] = odm_read_4byte(dm, 0x1b38); + } + break; + case 2: + for (i = 0; i < 6 ;i++) { + odm_write_4byte(dm, 0x1b14, 0xe0+i); + odm_write_4byte(dm, 0x1b14, 0x0); + iqk_info->gs1_xym[path][i] = odm_read_4byte(dm, 0x1b38); + } + break; + case 3: + for (i = 0; i < 6 ;i++) { + odm_write_4byte(dm, 0x1b14, 0xe0+i); + odm_write_4byte(dm, 0x1b14, 0x0); + iqk_info->gs2_xym[path][i] = odm_read_4byte(dm, 0x1b38); + } + break; + case 4: + for (i = 0; i < 6 ;i++) { + odm_write_4byte(dm, 0x1b14, 0xe0+i); + odm_write_4byte(dm, 0x1b14, 0x0); + iqk_info->rxk1_xym[path][i] = odm_read_4byte(dm, 0x1b38); + } + break; + + } + odm_write_4byte(dm, 0x1b38, 0x20000000); + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1b1c, tmp1); + odm_write_4byte(dm, 0x1b00, 0xf800000a); + odm_write_4byte(dm, 0x1b1c, tmp2); + _iqk_page_switch(dm); + } +} + +void halrf_iqk_xym_show( + struct dm_struct *dm, + u8 xym_type /*0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/ + ) +{ + u8 num, path, path_num, i; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (dm->rf_type ==RF_1T1R) + path_num = 0x1; + else if (dm->rf_type ==RF_2T2R) + path_num = 0x2; + else + path_num = 0x4; + + if (*dm->band_width == CHANNEL_WIDTH_20) + num = 4; + else if (*dm->band_width == CHANNEL_WIDTH_40) + num = 6; + else + num = 10; + + for (path = 0; path < path_num; path ++) { + switch (xym_type){ + case 0: + for (i = 0 ; i < num; i ++) + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s %-2d: 0x%x\n", + (path == 0) ? "PATH A RX-XYM ": "PATH B RX-XYM", i, iqk_info->rx_xym[path][i]); + break; + case 1: + for (i = 0 ; i < num; i ++) + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s %-2d: 0x%x\n", + (path == 0) ? "PATH A TX-XYM ": "PATH B TX-XYM", i, iqk_info->tx_xym[path][i]); + break; + case 2: + for (i = 0 ; i < 6; i ++) + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s %-2d: 0x%x\n", + (path == 0) ? "PATH A GS1-XYM ": "PATH B GS1-XYM", i, iqk_info->gs1_xym[path][i]); + break; + case 3: + for (i = 0 ; i < 6; i ++) + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s %-2d: 0x%x\n", + (path == 0) ? "PATH A GS2-XYM ": "PATH B GS2-XYM", i, iqk_info->gs2_xym[path][i]); + break; + case 4: + for (i = 0 ; i < 6; i ++) + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s %-2d: 0x%x\n", + (path == 0) ? "PATH A RXK1-XYM ": "PATH B RXK1-XYM", i, iqk_info->rxk1_xym[path][i]); + break; + } + } +} + + +void +halrf_iqk_xym_dump( + void *dm_void + ) +{ + u32 tmp1, tmp2; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_write_4byte(dm, 0x1b00, 0xf8000008); + tmp1 = odm_read_4byte(dm, 0x1b1c); + odm_write_4byte(dm, 0x1b00, 0xf800000a); + tmp2 = odm_read_4byte(dm, 0x1b1c); + /*halrf_iqk_xym_read(dm, xym_type);*/ + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1b1c, tmp1); + odm_write_4byte(dm, 0x1b00, 0xf800000a); + odm_write_4byte(dm, 0x1b1c, tmp2); + _iqk_page_switch(dm); +} + +void halrf_iqk_info_dump( + void *dm_void, + u32 *_used, + char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u8 path, num, i; + + u8 rf_path, j, reload_iqk = 0; + u32 tmp; + boolean iqk_result[2][NUM][2]; /*two channel, PATH, TX/RX, 0:pass 1 :fail*/ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + /* IQK INFO */ + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s\n", "% IQK Info %"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s\n", + (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" : "Driver-IQK"); + + reload_iqk = (u8)odm_get_bb_reg(dm, 0x1bf0, BIT(16)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", + "reload", (reload_iqk) ? "True" : "False"); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", + "rfk_forbidden", (iqk_info->rfk_forbidden) ? "True" : "False"); +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", + "segment_iqk", (iqk_info->segment_iqk) ? "True" : "False"); +#endif + + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s:%d %d\n", + "iqk count / fail count", dm->n_iqk_cnt, dm->n_iqk_fail_cnt); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %d\n", + "channel", *dm->channel); + + if (*dm->band_width == CHANNEL_WIDTH_20) + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", + "bandwidth", "BW_20"); + else if (*dm->band_width == CHANNEL_WIDTH_40) + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", + "bandwidth", "BW_40"); + else if (*dm->band_width == CHANNEL_WIDTH_80) + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", + "bandwidth", "BW_80"); + else if (*dm->band_width == CHANNEL_WIDTH_160) + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", + "bandwidth", "BW_160"); + else + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", + "bandwidth", "BW_UNKNOW"); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %llu %s\n", + "progressing_time", dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)"); + + tmp = odm_read_4byte(dm, 0x1bf0); + for(rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) + for(j = 0; j < 2; j++) + iqk_result[0][rf_path][j] = (boolean)(tmp & BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: 0x%08x\n","Reg0x1bf0", tmp); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", + "PATH_A-Tx result", (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", + "PATH_A-Rx result", (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass"); +#if (RTL8822B_SUPPORT == 1) + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", + "PATH_B-Tx result", (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", + "PATH_B-Rx result", (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass"); +#endif + *_used = used; + *_out_len = out_len; + +} + +void halrf_get_fw_version(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + { + void *adapter = dm->adapter; + + rf->fw_ver = (((PADAPTER)adapter)->MgntInfo.FirmwareVersion << 16) | ((PADAPTER)adapter)->MgntInfo.FirmwareSubVersion; + } +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) + { + struct rtl8192cd_priv *priv = dm->priv; + + rf->fw_ver = (priv->pshare->fw_version << 16) | priv->pshare->fw_sub_version; + } +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + { + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + struct rtl_hal *rtlhal = rtl_hal(rtlpriv); + + rf->fw_ver = (rtlhal->fw_version << 16) | rtlhal->fw_subversion; + } +#else + { + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + rf->fw_ver = (hal_data->firmware_version << 16) | hal_data->firmware_sub_version; + } +#endif +} + + + +void halrf_iqk_dbg(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rf_path, j, reload_iqk = 0; + u8 path, num, i; + u32 tmp; + boolean iqk_result[2][NUM][2]; /*two channel, PATH, TX/RX, 0:pass 1 :fail*/ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + struct _hal_rf_ *rf = &dm->rf_table; + + /* IQK INFO */ + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s\n", "====== IQK Info ======"); + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s\n", + (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" : "Driver-IQK"); + + if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) { + halrf_get_fw_version(dm); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: 0x%x\n", + "FW_VER", rf->fw_ver); + } else + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n", + "IQK_VER", HALRF_IQK_VER); + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"%-20s: %s\n", + "reload", (iqk_info->is_reload) ? "True" : "False"); + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %d %d\n", + "iqk count / fail count", dm->n_iqk_cnt, dm->n_iqk_fail_cnt); + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %d\n", + "channel", *dm->channel); + + if (*dm->band_width == CHANNEL_WIDTH_20) + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n", + "bandwidth", "BW_20"); + else if (*dm->band_width == CHANNEL_WIDTH_40) + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n", + "bandwidth", "BW_40"); + else if (*dm->band_width == CHANNEL_WIDTH_80) + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n", + "bandwidth", "BW_80"); + else if (*dm->band_width == CHANNEL_WIDTH_160) + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n", + "bandwidth", "BW_160"); + else + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n", + "bandwidth", "BW_UNKNOW"); +/* + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %llu %s\n", + "progressing_time", dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)"); +*/ + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n", + "rfk_forbidden", (iqk_info->rfk_forbidden) ? "True" : "False"); +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n", + "segment_iqk", (iqk_info->segment_iqk) ? "True" : "False"); +#endif + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %llu %s\n", + "progressing_time", dm->rf_calibrate_info.iqk_progressing_time, "(ms)"); + + + + + tmp = odm_read_4byte(dm, 0x1bf0); + for(rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) + for(j = 0; j < 2; j++) + iqk_result[0][rf_path][j] = (boolean)(tmp & BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))); + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: 0x%08x\n", "Reg0x1bf0", tmp); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: 0x%08x\n", "Reg0x1be8", odm_read_4byte(dm, 0x1be8)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n", + "PATH_A-Tx result", (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass"); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n", + "PATH_A-Rx result", (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass"); +#if (RTL8822B_SUPPORT == 1) + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n", + "PATH_B-Tx result", (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass"); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n", + "PATH_B-Rx result", (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass"); +#endif + + +} +void halrf_lck_dbg(struct dm_struct *dm) +{ + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s\n", "====== LCK Info ======"); + /*PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s\n", + (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "LCK" : "RTK"));*/ + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %llu %s\n", + "progressing_time", dm->rf_calibrate_info.lck_progressing_time, "(ms)"); +} + +void +halrf_iqk_dbg_cfir_backup(struct dm_struct *dm) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 path, idx, i; + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s\n", "backup TX/RX CFIR"); + + for (path = 0; path < 2; path ++) { + for (idx = 0; idx < 2; idx++) { + phydm_get_iqk_cfir(dm, idx, path, true); + } + } + + for (path = 0; path < 2; path ++) { + for (idx = 0; idx < 2; idx++) { + for(i = 0; i < 8; i++) { + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-7s %-3s CFIR_real: %-2d: 0x%x\n", + (path == 0) ? "PATH A": "PATH B", (idx == 0) ? "TX": "RX", i, iqk_info->iqk_cfir_real[2][path][idx][i]); + } + for(i = 0; i < 8; i++) { + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-7s %-3s CFIR_img:%-2d: 0x%x\n", + (path == 0) ? "PATH A": "PATH B", (idx == 0) ? "TX": "RX", i, iqk_info->iqk_cfir_imag[2][path][idx][i]); + } + } + } +} + + +void +halrf_iqk_dbg_cfir_backup_update( + struct dm_struct *dm +) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 i, path, idx; + + if(iqk_info->iqk_cfir_real[2][0][0][0] == 0) { + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s\n", "CFIR is invalid"); + return; + } + for (path = 0; path < 2; path++) { + for (idx = 0; idx < 2; idx++) { + odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1); + odm_set_bb_reg(dm, 0x1b2c, MASKDWORD, 0x7); + odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x20000000); + odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, 0x20000000); + odm_set_bb_reg(dm, 0x1bcc, MASKDWORD, 0x00000000); + if (idx == 0) + odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x3); + else + odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x1); + odm_set_bb_reg(dm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10); + for (i = 0; i < 8; i++) { + odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x3) + (i * 4) + (iqk_info->iqk_cfir_real[2][path][idx][i] << 9)); + odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (iqk_info->iqk_cfir_imag[2][path][idx][i] << 9)); + /*odm_write_4byte(dm, 0x1bd8, iqk_info->iqk_cfir_real[2][path][idx][i]);*/ + /*odm_write_4byte(dm, 0x1bd8, iqk_info->iqk_cfir_imag[2][path][idx][i]);*/ + } + } + odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0); + odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0); + } + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s\n", "update new CFIR"); +} + + +void +halrf_iqk_dbg_cfir_reload( + struct dm_struct *dm +) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 i, path, idx; + + if(iqk_info->iqk_cfir_real[0][0][0][0] == 0) { + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s\n", "CFIR is invalid"); + return; + } + for (path = 0; path < 2; path++) { + for (idx = 0; idx < 2; idx++) { + odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1); + odm_set_bb_reg(dm, 0x1b2c, MASKDWORD, 0x7); + odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x20000000); + odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, 0x20000000); + odm_set_bb_reg(dm, 0x1bcc, MASKDWORD, 0x00000000); + if (idx == 0) + odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x3); + else + odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x1); + odm_set_bb_reg(dm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10); + for (i = 0; i < 8; i++) { + /*odm_write_4byte(dm, 0x1bd8, iqk_info->iqk_cfir_real[0][path][idx][i]);*/ + /*odm_write_4byte(dm, 0x1bd8, iqk_info->iqk_cfir_imag[0][path][idx][i]);*/ + odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x3) + (i * 4) + (iqk_info->iqk_cfir_real[0][path][idx][i] << 9)); + odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (iqk_info->iqk_cfir_imag[0][path][idx][i] << 9)); + } + } + odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0); + odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0); + } + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s\n", "write CFIR with default value"); +} + +void +halrf_iqk_dbg_cfir_write( + struct dm_struct *dm, + u8 type, + u32 path, + u32 idx, + u32 i, + u32 data +) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + if (type == 0) + iqk_info->iqk_cfir_real[2][path][idx][i] = data; + else + iqk_info->iqk_cfir_imag[2][path][idx][i] = data; +} + +void +halrf_iqk_dbg_cfir_backup_show(struct dm_struct *dm) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 path, idx, i; + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s\n", "backup TX/RX CFIR"); + + for (path = 0; path < 2; path ++) { + for (idx = 0; idx < 2; idx++) { + for(i = 0; i < 8; i++) { + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-10s %-3s CFIR_real: %-2d: 0x%x\n", + (path == 0) ? "PATH A": "PATH B", (idx == 0) ? "TX": "RX", i, iqk_info->iqk_cfir_real[2][path][idx][i]); + } + for(i = 0; i < 8; i++) { + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-10s %-3s CFIR_img:%-2d: 0x%x\n", + (path == 0) ? "PATH A": "PATH B", (idx == 0) ? "TX": "RX", i, iqk_info->iqk_cfir_imag[2][path][idx][i]); + } + } + } +} + +void +halrf_do_imr_test( + void *dm_void, + u8 flag_imr_test +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (flag_imr_test != 0x0) + switch (dm->support_ic_type) { +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + do_imr_test_8822b(dm); + break; +#endif +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + do_imr_test_8821c(dm); + break; +#endif + default: + break; + } +} + +void halrf_iqk_debug( + void *dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + /*dm_value[0]=0x0: backup from SRAM & show*/ + /*dm_value[0]=0x1: write backup CFIR to SRAM*/ + /*dm_value[0]=0x2: reload default CFIR to SRAM*/ + /*dm_value[0]=0x3: show backup*/ + /*dm_value[0]=0x10: write backup CFIR real part*/ + /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/ + /*dm_value[0]=0x11: write backup CFIR imag*/ + /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/ + /*dm_value[0]=0x20 :xym_read enable*/ + /*--> dm_value[1]:0:disable, 1:enable*/ + /*if dm_value[0]=0x20 = enable, */ + /*0x1:show rx_sym; 0x2: tx_xym; 0x3:gs1_xym; 0x4:gs2_sym; 0x5:rxk1_xym*/ + + if (dm_value[0] == 0x0) + halrf_iqk_dbg_cfir_backup(dm); + else if (dm_value[0] == 0x1) + halrf_iqk_dbg_cfir_backup_update(dm); + else if (dm_value[0] == 0x2) + halrf_iqk_dbg_cfir_reload(dm); + else if (dm_value[0] == 0x3) + halrf_iqk_dbg_cfir_backup_show(dm); + else if (dm_value[0] == 0x10) + halrf_iqk_dbg_cfir_write(dm, 0, dm_value[1], dm_value[2], dm_value[3], dm_value[4]); + else if (dm_value[0] == 0x11) + halrf_iqk_dbg_cfir_write(dm, 1, dm_value[1], dm_value[2], dm_value[3], dm_value[4]); + else if (dm_value[0] == 0x20) + halrf_iqk_xym_enable(dm, (u8)dm_value[1]); + else if (dm_value[0] == 0x21) + halrf_iqk_xym_show(dm,(u8)dm_value[1]); + else if (dm_value[0] == 0x30) + halrf_do_imr_test(dm, (u8)dm_value[1]); +} + +void +halrf_iqk_hwtx_check( + void *dm_void, + boolean is_check +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u32 tmp_b04; + + if (is_check) + iqk_info->is_hwtx = (boolean)odm_get_bb_reg(dm, 0xb00, BIT(8)); + else { + if (iqk_info->is_hwtx) { + tmp_b04 = odm_read_4byte(dm, 0xb04); + odm_set_bb_reg(dm, 0xb04, BIT(3) | BIT (2), 0x0); + odm_write_4byte(dm, 0xb04, tmp_b04); + } + } +} + +void +halrf_segment_iqk_trigger( + void *dm_void, + boolean clear, + boolean segment_iqk +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + struct _hal_rf_ *rf = &dm->rf_table; + u64 start_time; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if (odm_check_power_status(dm) == false) + return; +#endif + + if ((dm->mp_mode != NULL) && (rf->is_con_tx != NULL) && (rf->is_single_tone != NULL) && (rf->is_carrier_suppresion != NULL)) + if (*dm->mp_mode && ((*rf->is_con_tx || *rf->is_single_tone || *rf->is_carrier_suppresion))) + return; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(rf->rf_supportability & HAL_RF_IQK)) + return; +#endif + +#if DISABLE_BB_RF + return; +#endif + if (iqk_info->rfk_forbidden) + return; + + if (!dm->rf_calibrate_info.is_iqk_in_progress) { + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = true; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + start_time = odm_get_current_time(dm); + dm->IQK_info.segment_iqk = segment_iqk; + + switch (dm->support_ic_type) { +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + phy_iq_calibrate_8822b(dm, clear, segment_iqk); + break; +#endif +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + phy_iq_calibrate_8821c(dm, clear, segment_iqk); + break; +#endif +#if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + break; +#endif + default: + break; + } + dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, start_time); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]IQK progressing_time = %lld ms\n", dm->rf_calibrate_info.iqk_progressing_time); + + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + } else + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "== Return the IQK CMD, because RFKs in Progress ==\n"); +} + + + +#endif + + + +u8 halrf_match_iqk_version(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + u32 iqk_version = 0; + char temp[10] = {0}; + + odm_move_memory(dm, temp, (PVOID)(HALRF_IQK_VER), sizeof(temp)); + PHYDM_SSCANF(temp + 2, DCMD_HEX, &iqk_version); + + if (dm->support_ic_type == ODM_RTL8822B) { + if ((iqk_version >= 0x24) && (odm_get_hw_img_version(dm) >= 72)) + return 1; + else if ((iqk_version <= 0x23) && (odm_get_hw_img_version(dm) <= 71)) + return 1; + else + return 0; + } + + if (dm->support_ic_type == ODM_RTL8821C) { + if ((iqk_version >= 0x18) && (odm_get_hw_img_version(dm) >= 37)) + return 1; + else + return 0; + } + + return 1; +} + + + +void +halrf_rf_lna_setting( + void *dm_void, + enum phydm_lna_set type +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + switch (dm->support_ic_type) { +#if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: + halrf_rf_lna_setting_8188e(dm, type); + break; +#endif +#if (RTL8192E_SUPPORT == 1) + case ODM_RTL8192E: + halrf_rf_lna_setting_8192e(dm, type); + break; +#endif +#if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: + halrf_rf_lna_setting_8723b(dm, type); + break; +#endif +#if (RTL8812A_SUPPORT == 1) + case ODM_RTL8812: + halrf_rf_lna_setting_8812a(dm, type); + break; +#endif +#if ((RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1)) + case ODM_RTL8881A: + case ODM_RTL8821: + halrf_rf_lna_setting_8821a(dm, type); + break; +#endif +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + halrf_rf_lna_setting_8822b(dm, type); + break; +#endif +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + halrf_rf_lna_setting_8821c(dm, type); + break; +#endif + default: + break; + } + + } + + void halrf_support_ability_debug( - void *p_dm_void, + void *dm_void, char input[][16], u32 *_used, char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; u32 dm_value[10] = {0}; u32 used = *_used; u32 out_len = *_out_len; @@ -71,33 +970,107 @@ halrf_support_ability_debug( } } - PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); + PDM_SNPF(out_len, used, output + used, out_len - used, "\n%s\n", + "================================"); if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output + used, out_len - used, "[RF Supportability]\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))Power Tracking\n", ((p_rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))IQK\n", ((p_rf->rf_supportability & HAL_RF_IQK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))LCK\n", ((p_rf->rf_supportability & HAL_RF_LCK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))DPK\n", ((p_rf->rf_supportability & HAL_RF_DPK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[RF Supportability]\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s\n", "================================"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))Power Tracking\n", + ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "01. (( %s ))IQK\n", + ((rf->rf_supportability & HAL_RF_IQK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "02. (( %s ))LCK\n", + ((rf->rf_supportability & HAL_RF_LCK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "03. (( %s ))DPK\n", + ((rf->rf_supportability & HAL_RF_DPK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "04. (( %s ))HAL_RF_TXGAPK\n", + ((rf->rf_supportability & HAL_RF_TXGAPK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s\n", "================================"); } else { - if (dm_value[1] == 1) { /* enable */ - p_rf->rf_supportability |= BIT(dm_value[0]) ; + rf->rf_supportability |= BIT(dm_value[0]) ; } else if (dm_value[1] == 2) /* disable */ - p_rf->rf_supportability &= ~(BIT(dm_value[0])) ; + rf->rf_supportability &= ~(BIT(dm_value[0])) ; else { - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); + PDM_SNPF(out_len, used, output + used, + out_len - used, "%s\n", + "[Warning!!!] 1:enable, 2:disable"); } } - PHYDM_SNPRINTF((output + used, out_len - used, "Curr-RF_supportability = 0x%x\n", p_rf->rf_supportability)); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Curr-RF_supportability = 0x%x\n", + rf->rf_supportability); + PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n", + "================================"); + + *_used = used; + *_out_len = out_len; +} + +void +halrf_cmn_info_init( + void *dm_void, +enum halrf_cmninfo_init cmn_info, + u32 value +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + switch (cmn_info) { + case HALRF_CMNINFO_EEPROM_THERMAL_VALUE: + rf->eeprom_thermal = (u8)value; + break; + case HALRF_CMNINFO_FW_VER: + rf->fw_ver = (u32)value; + break; + default: + break; + } +} + + +void +halrf_cmn_info_hook( + void *dm_void, +enum halrf_cmninfo_hook cmn_info, + void *value +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + switch (cmn_info) { + case HALRF_CMNINFO_CON_TX: + rf->is_con_tx = (boolean *)value; + break; + case HALRF_CMNINFO_SINGLE_TONE: + rf->is_single_tone = (boolean *)value; + break; + case HALRF_CMNINFO_CARRIER_SUPPRESSION: + rf->is_carrier_suppresion = (boolean *)value; + break; + case HALRF_CMNINFO_MP_RATE_INDEX: + rf->mp_rate_index = (u8 *)value; + break; + default: + /*do nothing*/ + break; + } } void halrf_cmn_info_set( - void *p_dm_void, + void *dm_void, u32 cmn_info, u64 value ) @@ -105,19 +1078,42 @@ halrf_cmn_info_set( /* */ /* This init variable may be changed in run time. */ /* */ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; switch (cmn_info) { - case HALRF_CMNINFO_ABILITY: - p_rf->rf_supportability = (u32)value; + rf->rf_supportability = (u32)value; break; - case ODM_CMNINFO_DPK_EN: - p_rf->dpk_en = (u1Byte)value; + case HALRF_CMNINFO_DPK_EN: + rf->dpk_en = (u8)value; break; - + case HALRF_CMNINFO_RFK_FORBIDDEN : + dm->IQK_info.rfk_forbidden = (boolean)value; + break; + #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + case HALRF_CMNINFO_IQK_SEGMENT: + dm->IQK_info.segment_iqk = (boolean)value; + break; + #endif + case HALRF_CMNINFO_RATE_INDEX: + rf->p_rate_index = (u32)value; + break; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + case HALRF_CMNINFO_MP_PSD_POINT: + rf->halrf_psd_data.point = (u32)value; + break; + case HALRF_CMNINFO_MP_PSD_START_POINT: + rf->halrf_psd_data.start_point = (u32)value; + break; + case HALRF_CMNINFO_MP_PSD_STOP_POINT: + rf->halrf_psd_data.stop_point = (u32)value; + break; + case HALRF_CMNINFO_MP_PSD_AVERAGE: + rf->halrf_psd_data.average = (u32)value; + break; +#endif default: /* do nothing */ break; @@ -126,22 +1122,29 @@ halrf_cmn_info_set( u64 halrf_cmn_info_get( - void *p_dm_void, + void *dm_void, u32 cmn_info ) { /* */ /* This init variable may be changed in run time. */ /* */ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; u64 return_value = 0; switch (cmn_info) { - case HALRF_CMNINFO_ABILITY: - return_value = (u32)p_rf->rf_supportability; + return_value = (u32)rf->rf_supportability; break; + case HALRF_CMNINFO_RFK_FORBIDDEN : + return_value = dm->IQK_info.rfk_forbidden; + break; + #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + case HALRF_CMNINFO_IQK_SEGMENT: + return_value = dm->IQK_info.segment_iqk; + break; + #endif default: /* do nothing */ break; @@ -152,17 +1155,16 @@ halrf_cmn_info_get( void halrf_supportability_init_mp( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); - - switch (p_dm_odm->support_ic_type) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + switch (dm->support_ic_type) { case ODM_RTL8814B: #if (RTL8814B_SUPPORT == 1) - p_rf->rf_supportability = + rf->rf_supportability = HAL_RF_TX_PWR_TRACK | HAL_RF_IQK | HAL_RF_LCK | @@ -172,7 +1174,7 @@ halrf_supportability_init_mp( break; #if (RTL8822B_SUPPORT == 1) case ODM_RTL8822B: - p_rf->rf_supportability = + rf->rf_supportability = HAL_RF_TX_PWR_TRACK | HAL_RF_IQK | HAL_RF_LCK | @@ -183,42 +1185,43 @@ halrf_supportability_init_mp( #if (RTL8821C_SUPPORT == 1) case ODM_RTL8821C: - p_rf->rf_supportability = + rf->rf_supportability = HAL_RF_TX_PWR_TRACK | HAL_RF_IQK | HAL_RF_LCK | /*HAL_RF_DPK |*/ + /*HAL_RF_TXGAPK |*/ 0; break; #endif default: - p_rf->rf_supportability = + rf->rf_supportability = HAL_RF_TX_PWR_TRACK | HAL_RF_IQK | HAL_RF_LCK | /*HAL_RF_DPK |*/ + /*HAL_RF_TXGAPK |*/ 0; break; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\n", p_dm_odm->support_ic_type, p_rf->rf_supportability)); + PHYDM_DBG(dm, ODM_COMP_INIT, "IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\n", dm->support_ic_type, rf->rf_supportability); } void halrf_supportability_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); - - switch (p_dm_odm->support_ic_type) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + switch (dm->support_ic_type) { case ODM_RTL8814B: #if (RTL8814B_SUPPORT == 1) - p_rf->rf_supportability = + rf->rf_supportability = HAL_RF_TX_PWR_TRACK | HAL_RF_IQK | HAL_RF_LCK | @@ -228,7 +1231,7 @@ halrf_supportability_init( break; #if (RTL8822B_SUPPORT == 1) case ODM_RTL8822B: - p_rf->rf_supportability = + rf->rf_supportability = HAL_RF_TX_PWR_TRACK | HAL_RF_IQK | HAL_RF_LCK | @@ -239,17 +1242,18 @@ halrf_supportability_init( #if (RTL8821C_SUPPORT == 1) case ODM_RTL8821C: - p_rf->rf_supportability = + rf->rf_supportability = HAL_RF_TX_PWR_TRACK | HAL_RF_IQK | HAL_RF_LCK | - /*HAL_RF_DPK |*/ + /*HAL_RF_DPK |*/ + /*HAL_RF_TXGAPK |*/ 0; break; #endif default: - p_rf->rf_supportability = + rf->rf_supportability = HAL_RF_TX_PWR_TRACK | HAL_RF_IQK | HAL_RF_LCK | @@ -259,31 +1263,311 @@ halrf_supportability_init( } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IC = ((0x%x)), RF_Supportability Init = ((0x%x))\n", p_dm_odm->support_ic_type, p_rf->rf_supportability)); + PHYDM_DBG(dm, ODM_COMP_INIT, "IC = ((0x%x)), RF_Supportability Init = ((0x%x))\n", dm->support_ic_type, rf->rf_supportability); } void halrf_watchdog( - void *p_dm_void + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + phydm_rf_watchdog(dm); +} +#if 0 +void +halrf_iqk_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &(dm->rf_table); + + switch (dm->support_ic_type) { + #if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + break; + #endif + #if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + _iq_calibrate_8822b_init(dm); + break; + #endif + #if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + break; + #endif + + default: + break; + } +} +#endif + + +void +halrf_iqk_trigger( + void *dm_void, + boolean is_recovery +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + struct _hal_rf_ *rf = &dm->rf_table; + u64 start_time; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if (odm_check_power_status(dm) == false) + return; +#endif + + if ((dm->mp_mode != NULL) && (rf->is_con_tx != NULL) && (rf->is_single_tone != NULL) && (rf->is_carrier_suppresion != NULL)) + if (*dm->mp_mode && ((*rf->is_con_tx || *rf->is_single_tone || *rf->is_carrier_suppresion))) + return; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(rf->rf_supportability & HAL_RF_IQK)) + return; +#endif + +#if DISABLE_BB_RF + return; +#endif + + if (iqk_info->rfk_forbidden) + return; + + if (!dm->rf_calibrate_info.is_iqk_in_progress) { + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = true; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + start_time = odm_get_current_time(dm); + switch (dm->support_ic_type) { +#if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: + phy_iq_calibrate_8188e(dm, is_recovery); + break; +#endif +#if (RTL8188F_SUPPORT == 1) + case ODM_RTL8188F: + phy_iq_calibrate_8188f(dm, is_recovery); + break; +#endif +#if (RTL8192E_SUPPORT == 1) + case ODM_RTL8192E: + phy_iq_calibrate_8192e(dm, is_recovery); + break; +#endif +#if (RTL8197F_SUPPORT == 1) + case ODM_RTL8197F: + phy_iq_calibrate_8197f(dm, is_recovery); + break; +#endif +#if (RTL8703B_SUPPORT == 1) + case ODM_RTL8703B: + phy_iq_calibrate_8703b(dm, is_recovery); + break; +#endif +#if (RTL8710B_SUPPORT == 1) + case ODM_RTL8710B: + phy_iq_calibrate_8710b(dm, is_recovery); + break; +#endif +#if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: + phy_iq_calibrate_8723b(dm, is_recovery); + break; +#endif +#if (RTL8723D_SUPPORT == 1) + case ODM_RTL8723D: + phy_iq_calibrate_8723d(dm, is_recovery); + break; +#endif +#if (RTL8812A_SUPPORT == 1) + case ODM_RTL8812: + phy_iq_calibrate_8812a(dm, is_recovery); + break; +#endif +#if (RTL8821A_SUPPORT == 1) + case ODM_RTL8821: + phy_iq_calibrate_8821a(dm, is_recovery); + break; +#endif +#if (RTL8814A_SUPPORT == 1) + case ODM_RTL8814A: + phy_iq_calibrate_8814a(dm, is_recovery); + break; +#endif +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + phy_iq_calibrate_8822b(dm, false, false); + break; +#endif +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + phy_iq_calibrate_8821c(dm, false, false); + break; +#endif +#if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + break; +#endif + default: + break; + } + dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, start_time); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]IQK progressing_time = %lld ms\n", dm->rf_calibrate_info.iqk_progressing_time); + + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + } else + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "== Return the IQK CMD, because RFKs in Progress ==\n"); +} + + + +void +halrf_lck_trigger( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - phydm_rf_watchdog(p_dm_odm); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + struct _hal_rf_ *rf = &dm->rf_table; + u64 start_time; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if (odm_check_power_status(dm) == false) + return; +#endif + + if ((dm->mp_mode != NULL) && (rf->is_con_tx != NULL) && (rf->is_single_tone != NULL) && (rf->is_carrier_suppresion != NULL)) + if (*dm->mp_mode && ((*rf->is_con_tx || *rf->is_single_tone || *rf->is_carrier_suppresion))) + return; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(rf->rf_supportability & HAL_RF_LCK)) + return; +#endif + +#if DISABLE_BB_RF + return; +#endif + if (iqk_info->rfk_forbidden) + return; + while (*dm->is_scan_in_process) { + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[LCK]scan is in process, bypass LCK\n"); + return; + } + + if (!dm->rf_calibrate_info.is_lck_in_progress) { + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_lck_in_progress = true; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + start_time = odm_get_current_time(dm); + switch (dm->support_ic_type) { +#if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: + phy_lc_calibrate_8188e(dm); + break; +#endif +#if (RTL8188F_SUPPORT == 1) + case ODM_RTL8188F: + phy_lc_calibrate_8188f(dm); + break; +#endif +#if (RTL8192E_SUPPORT == 1) + case ODM_RTL8192E: + phy_lc_calibrate_8192e(dm); + break; +#endif +#if (RTL8197F_SUPPORT == 1) + case ODM_RTL8197F: + phy_lc_calibrate_8197f(dm); + break; +#endif +#if (RTL8703B_SUPPORT == 1) + case ODM_RTL8703B: + phy_lc_calibrate_8703b(dm); + break; +#endif +#if (RTL8710B_SUPPORT == 1) + case ODM_RTL8710B: + phy_lc_calibrate_8710b(dm); + break; +#endif +#if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: + phy_lc_calibrate_8723b(dm); + break; +#endif +#if (RTL8723D_SUPPORT == 1) + case ODM_RTL8723D: + phy_lc_calibrate_8723d(dm); + break; +#endif +#if (RTL8812A_SUPPORT == 1) + case ODM_RTL8812: + phy_lc_calibrate_8812a(dm); + break; +#endif +#if (RTL8821A_SUPPORT == 1) + case ODM_RTL8821: + phy_lc_calibrate_8821a(dm); + break; +#endif +#if (RTL8814A_SUPPORT == 1) + case ODM_RTL8814A: + phy_lc_calibrate_8814a(dm); + break; +#endif +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + phy_lc_calibrate_8822b(dm); + break; +#endif +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + phy_lc_calibrate_8821c(dm); + break; +#endif +#if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + break; +#endif + default: + break; + } + dm->rf_calibrate_info.lck_progressing_time = odm_get_progressing_time(dm, start_time); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]LCK progressing_time = %lld ms\n", dm->rf_calibrate_info.lck_progressing_time); +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + halrf_lck_dbg(dm); +#endif + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_lck_in_progress = false; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + }else + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "== Return the LCK CMD, because RFK is in Progress ==\n"); } void halrf_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("HALRF_Init\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "HALRF_Init\n"); - if (*(p_dm_odm->p_mp_mode) == true) - halrf_supportability_init_mp(p_dm_odm); + if (*dm->mp_mode == true) + halrf_supportability_init_mp(dm); else - halrf_supportability_init(p_dm_odm); + halrf_supportability_init(dm); + + /*Init all RF funciton*/ + /*iqk_init();*/ + /*dpk_init();*/ } diff --git a/hal/phydm/halrf/halrf.h b/hal/phydm/halrf/halrf.h index cc28aff..7240397 100644 --- a/hal/phydm/halrf/halrf.h +++ b/hal/phydm/halrf/halrf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #ifndef _HALRF_H__ @@ -25,101 +30,426 @@ /*============================================================*/ /*include files*/ /*============================================================*/ - +#include "halrf/halrf_psd.h" /*============================================================*/ /*Definition */ /*============================================================*/ +/*IQK version*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +#define IQK_VERSION_8188E "0x14" +#define IQK_VERSION_8192E "0x01" +#define IQK_VERSION_8723B "0x1e" +#define IQK_VERSION_8812A "0x01" +#define IQK_VERSION_8821A "0x01" +#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +#define IQK_VERSION_8188E "0x01" +#define IQK_VERSION_8192E "0x01" +#define IQK_VERSION_8723B "0x1e" +#define IQK_VERSION_8812A "0x01" +#define IQK_VERSION_8821A "0x01" +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#define IQK_VERSION_8188E "0x01" +#define IQK_VERSION_8192E "0x01" +#define IQK_VERSION_8723B "0x1e" +#define IQK_VERSION_8812A "0x01" +#define IQK_VERSION_8821A "0x01" +#endif +#define IQK_VERSION_8814A "0x0f" +#define IQK_VERSION_8188F "0x01" +#define IQK_VERSION_8197F "0x01" +#define IQK_VERSION_8703B "0x05" +#define IQK_VERSION_8710B "0x01" +#define IQK_VERSION_8723D "0x02" +#define IQK_VERSION_8822B "0x2f" +#define IQK_VERSION_8821C "0x23" + +/*LCK version*/ +#define LCK_VERSION_8188E "0x01" +#define LCK_VERSION_8192E "0x01" +#define LCK_VERSION_8723B "0x01" +#define LCK_VERSION_8812A "0x01" +#define LCK_VERSION_8821A "0x01" +#define LCK_VERSION_8814A "0x01" +#define LCK_VERSION_8188F "0x01" +#define LCK_VERSION_8197F "0x01" +#define LCK_VERSION_8703B "0x01" +#define LCK_VERSION_8710B "0x01" +#define LCK_VERSION_8723D "0x01" +#define LCK_VERSION_8822B "0x01" +#define LCK_VERSION_8821C "0x01" + +/*power tracking version*/ +#define POWERTRACKING_VERSION_8188E "0x01" +#define POWERTRACKING_VERSION_8192E "0x01" +#define POWERTRACKING_VERSION_8723B "0x01" +#define POWERTRACKING_VERSION_8812A "0x01" +#define POWERTRACKING_VERSION_8821A "0x01" +#define POWERTRACKING_VERSION_8814A "0x01" +#define POWERTRACKING_VERSION_8188F "0x01" +#define POWERTRACKING_VERSION_8197F "0x01" +#define POWERTRACKING_VERSION_8703B "0x01" +#define POWERTRACKING_VERSION_8710B "0x01" +#define POWERTRACKING_VERSION_8723D "0x01" +#define POWERTRACKING_VERSION_8822B "0x01" +#define POWERTRACKING_VERSION_8821C "0x01" + +/*DPK tracking version*/ +#define DPK_VERSION_8188E "NONE" +#define DPK_VERSION_8192E "NONE" +#define DPK_VERSION_8723B "NONE" +#define DPK_VERSION_8812A "NONE" +#define DPK_VERSION_8821A "NONE" +#define DPK_VERSION_8814A "NONE" +#define DPK_VERSION_8188F "NONE" +#define DPK_VERSION_8197F "NONE" +#define DPK_VERSION_8703B "NONE" +#define DPK_VERSION_8710B "NONE" +#define DPK_VERSION_8723D "NONE" +#define DPK_VERSION_8822B "NONE" +#define DPK_VERSION_8821C "NONE" + +/*Kfree tracking version*/ +#define KFREE_VERSION_8188E (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" +#define KFREE_VERSION_8192E (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" +#define KFREE_VERSION_8723B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" +#define KFREE_VERSION_8812A (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" +#define KFREE_VERSION_8821A (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" +#define KFREE_VERSION_8814A (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" +#define KFREE_VERSION_8188F (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" +#define KFREE_VERSION_8197F (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" +#define KFREE_VERSION_8703B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" +#define KFREE_VERSION_8710B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" +#define KFREE_VERSION_8723D (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" +#define KFREE_VERSION_8822B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" +#define KFREE_VERSION_8821C (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE" + +/*PA Bias Calibration version*/ +#define PABIASK_VERSION_8188E (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" +#define PABIASK_VERSION_8192E (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" +#define PABIASK_VERSION_8723B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" +#define PABIASK_VERSION_8812A (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" +#define PABIASK_VERSION_8821A (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" +#define PABIASK_VERSION_8814A (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" +#define PABIASK_VERSION_8188F (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" +#define PABIASK_VERSION_8197F (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" +#define PABIASK_VERSION_8703B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" +#define PABIASK_VERSION_8710B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" +#define PABIASK_VERSION_8723D (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" +#define PABIASK_VERSION_8822B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" +#define PABIASK_VERSION_8821C (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE" + + + +#define HALRF_IQK_VER (dm->support_ic_type == ODM_RTL8188E)? IQK_VERSION_8188E :\ + (dm->support_ic_type == ODM_RTL8192E)? IQK_VERSION_8192E :\ + (dm->support_ic_type == ODM_RTL8723B)? IQK_VERSION_8723B :\ + (dm->support_ic_type == ODM_RTL8812)? IQK_VERSION_8812A :\ + (dm->support_ic_type == ODM_RTL8821)? IQK_VERSION_8821A :\ + (dm->support_ic_type == ODM_RTL8814A)? IQK_VERSION_8814A :\ + (dm->support_ic_type == ODM_RTL8188F)? IQK_VERSION_8188F :\ + (dm->support_ic_type == ODM_RTL8197F)? IQK_VERSION_8197F :\ + (dm->support_ic_type == ODM_RTL8703B)? IQK_VERSION_8703B :\ + (dm->support_ic_type == ODM_RTL8710B)? IQK_VERSION_8710B :\ + (dm->support_ic_type == ODM_RTL8723D)? IQK_VERSION_8723D :\ + (dm->support_ic_type == ODM_RTL8822B)? IQK_VERSION_8822B :\ + (dm->support_ic_type == ODM_RTL8821C)? IQK_VERSION_8821C :"unknown" + + +#define HALRF_LCK_VER (dm->support_ic_type == ODM_RTL8188E)? LCK_VERSION_8188E :\ + (dm->support_ic_type == ODM_RTL8192E)? LCK_VERSION_8192E :\ + (dm->support_ic_type == ODM_RTL8723B)? LCK_VERSION_8723B :\ + (dm->support_ic_type == ODM_RTL8812)? LCK_VERSION_8812A :\ + (dm->support_ic_type == ODM_RTL8821)? LCK_VERSION_8821A :\ + (dm->support_ic_type == ODM_RTL8814A)? LCK_VERSION_8814A :\ + (dm->support_ic_type == ODM_RTL8188F)? LCK_VERSION_8188F :\ + (dm->support_ic_type == ODM_RTL8197F)? LCK_VERSION_8197F :\ + (dm->support_ic_type == ODM_RTL8703B)? LCK_VERSION_8703B :\ + (dm->support_ic_type == ODM_RTL8710B)? LCK_VERSION_8710B :\ + (dm->support_ic_type == ODM_RTL8723D)? LCK_VERSION_8723D :\ + (dm->support_ic_type == ODM_RTL8822B)? LCK_VERSION_8822B :\ + (dm->support_ic_type == ODM_RTL8821C)? LCK_VERSION_8821C :"unknown" + + +#define HALRF_POWRTRACKING_VER (dm->support_ic_type == ODM_RTL8188E)? POWERTRACKING_VERSION_8188E :\ + (dm->support_ic_type == ODM_RTL8192E)? POWERTRACKING_VERSION_8192E :\ + (dm->support_ic_type == ODM_RTL8723B)? POWERTRACKING_VERSION_8723B :\ + (dm->support_ic_type == ODM_RTL8812)? POWERTRACKING_VERSION_8812A :\ + (dm->support_ic_type == ODM_RTL8821)? POWERTRACKING_VERSION_8821A :\ + (dm->support_ic_type == ODM_RTL8814A)? POWERTRACKING_VERSION_8814A :\ + (dm->support_ic_type == ODM_RTL8188F)? POWERTRACKING_VERSION_8188F :\ + (dm->support_ic_type == ODM_RTL8197F)? POWERTRACKING_VERSION_8197F :\ + (dm->support_ic_type == ODM_RTL8703B)? POWERTRACKING_VERSION_8703B :\ + (dm->support_ic_type == ODM_RTL8710B)? POWERTRACKING_VERSION_8710B :\ + (dm->support_ic_type == ODM_RTL8723D)? POWERTRACKING_VERSION_8723D :\ + (dm->support_ic_type == ODM_RTL8822B)? POWERTRACKING_VERSION_8822B :\ + (dm->support_ic_type == ODM_RTL8821C)? POWERTRACKING_VERSION_8821C :"unknown" + +#define HALRF_DPK_VER (dm->support_ic_type == ODM_RTL8188E)? DPK_VERSION_8188E :\ + (dm->support_ic_type == ODM_RTL8192E)? DPK_VERSION_8192E :\ + (dm->support_ic_type == ODM_RTL8723B)? DPK_VERSION_8723B :\ + (dm->support_ic_type == ODM_RTL8812)? DPK_VERSION_8812A :\ + (dm->support_ic_type == ODM_RTL8821)? DPK_VERSION_8821A :\ + (dm->support_ic_type == ODM_RTL8814A)? DPK_VERSION_8814A :\ + (dm->support_ic_type == ODM_RTL8188F)? DPK_VERSION_8188F :\ + (dm->support_ic_type == ODM_RTL8197F)? DPK_VERSION_8197F :\ + (dm->support_ic_type == ODM_RTL8703B)? DPK_VERSION_8703B :\ + (dm->support_ic_type == ODM_RTL8710B)? DPK_VERSION_8710B :\ + (dm->support_ic_type == ODM_RTL8723D)? DPK_VERSION_8723D :\ + (dm->support_ic_type == ODM_RTL8822B)? DPK_VERSION_8822B :\ + (dm->support_ic_type == ODM_RTL8821C)? DPK_VERSION_8821C :"unknown" + +#define HALRF_KFREE_VER (dm->support_ic_type == ODM_RTL8188E)? KFREE_VERSION_8188E :\ + (dm->support_ic_type == ODM_RTL8192E)? KFREE_VERSION_8192E :\ + (dm->support_ic_type == ODM_RTL8723B)? KFREE_VERSION_8723B :\ + (dm->support_ic_type == ODM_RTL8812)? KFREE_VERSION_8812A :\ + (dm->support_ic_type == ODM_RTL8821)? KFREE_VERSION_8821A :\ + (dm->support_ic_type == ODM_RTL8814A)? KFREE_VERSION_8814A :\ + (dm->support_ic_type == ODM_RTL8188F)? KFREE_VERSION_8188F :\ + (dm->support_ic_type == ODM_RTL8197F)? KFREE_VERSION_8197F :\ + (dm->support_ic_type == ODM_RTL8703B)? KFREE_VERSION_8703B :\ + (dm->support_ic_type == ODM_RTL8710B)? KFREE_VERSION_8710B :\ + (dm->support_ic_type == ODM_RTL8723D)? KFREE_VERSION_8723D :\ + (dm->support_ic_type == ODM_RTL8822B)? KFREE_VERSION_8822B :\ + (dm->support_ic_type == ODM_RTL8821C)? KFREE_VERSION_8821C :"unknown" + +#define HALRF_PABIASK_VER (dm->support_ic_type == ODM_RTL8188E)? PABIASK_VERSION_8188E :\ + (dm->support_ic_type == ODM_RTL8192E)? PABIASK_VERSION_8192E :\ + (dm->support_ic_type == ODM_RTL8723B)? PABIASK_VERSION_8723B :\ + (dm->support_ic_type == ODM_RTL8812)? PABIASK_VERSION_8812A :\ + (dm->support_ic_type == ODM_RTL8821)? PABIASK_VERSION_8821A :\ + (dm->support_ic_type == ODM_RTL8814A)? PABIASK_VERSION_8814A :\ + (dm->support_ic_type == ODM_RTL8188F)? PABIASK_VERSION_8188F :\ + (dm->support_ic_type == ODM_RTL8197F)? PABIASK_VERSION_8197F :\ + (dm->support_ic_type == ODM_RTL8703B)? PABIASK_VERSION_8703B :\ + (dm->support_ic_type == ODM_RTL8710B)? PABIASK_VERSION_8710B :\ + (dm->support_ic_type == ODM_RTL8723D)? PABIASK_VERSION_8723D :\ + (dm->support_ic_type == ODM_RTL8822B)? PABIASK_VERSION_8822B :\ + (dm->support_ic_type == ODM_RTL8821C)? PABIASK_VERSION_8821C :"unknown" -#if 0/*(RTL8821C_SUPPORT == 1)*/ -#define HALRF_IQK_VER IQK_VERSION -#define HALRF_LCK_VER LCK_VERSION -#define HALRF_DPK_VER DPK_VERSION -#else -#define HALRF_IQK_VER "1.0" -#define HALRF_LCK_VER "1.0" -#define HALRF_DPK_VER "1.0" -#endif + +#define IQK_THRESHOLD 8 +#define DPK_THRESHOLD 4 + +/*===========================================================*/ +/*AGC RX High Power mode*/ +/*===========================================================*/ +#define lna_low_gain_1 0x64 +#define lna_low_gain_2 0x5A +#define lna_low_gain_3 0x58 /*============================================================*/ /* enumeration */ /*============================================================*/ -enum halrf_ability_e { - +enum halrf_ability { HAL_RF_TX_PWR_TRACK = BIT(0), HAL_RF_IQK = BIT(1), HAL_RF_LCK = BIT(2), - HAL_RF_DPK = BIT(3) + HAL_RF_DPK = BIT(3), + HAL_RF_TXGAPK = BIT(4) }; -enum halrf_cmninfo_e { - +enum halrf_cmninfo_init { HALRF_CMNINFO_ABILITY = 0, HALRF_CMNINFO_DPK_EN = 1, - HALRF_CMNINFO_tmp + HALRF_CMNINFO_EEPROM_THERMAL_VALUE, + HALRF_CMNINFO_FW_VER, + HALRF_CMNINFO_RFK_FORBIDDEN, + HALRF_CMNINFO_IQK_SEGMENT, + HALRF_CMNINFO_RATE_INDEX, + HALRF_CMNINFO_MP_PSD_POINT, + HALRF_CMNINFO_MP_PSD_START_POINT, + HALRF_CMNINFO_MP_PSD_STOP_POINT, + HALRF_CMNINFO_MP_PSD_AVERAGE +}; + +enum halrf_cmninfo_hook { + HALRF_CMNINFO_CON_TX, + HALRF_CMNINFO_SINGLE_TONE, + HALRF_CMNINFO_CARRIER_SUPPRESSION, + HALRF_CMNINFO_MP_RATE_INDEX }; +enum phydm_lna_set { + phydm_lna_disable = 0, + phydm_lna_enable = 1, +}; + + /*============================================================*/ /* structure */ /*============================================================*/ struct _hal_rf_ { + /*hook*/ + u8 *test1; + + /*update*/ u32 rf_supportability; + + u8 eeprom_thermal; u8 dpk_en; /*Enable Function DPK OFF/ON = 0/1*/ boolean dpk_done; + u32 fw_ver; + + boolean *is_con_tx; + boolean *is_single_tone; + boolean *is_carrier_suppresion; + u8 *mp_rate_index; + u32 p_rate_index; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _halrf_psd_data halrf_psd_data; +#endif }; /*============================================================*/ /* function prototype */ /*============================================================*/ -void phydm_rf_basic_profile( - void *p_dm_void, +void halrf_basic_profile( + void *dm_void, u32 *_used, char *output, u32 *_out_len ); +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) +void halrf_iqk_info_dump( + void *dm_void, + u32 *_used, + char *output, + u32 *_out_len +); + +void +halrf_iqk_hwtx_check( + void *dm_void, + boolean is_check +); +#endif + +u8 +halrf_match_iqk_version( + void *dm_void +); void halrf_support_ability_debug( - void *p_dm_void, + void *dm_void, char input[][16], u32 *_used, char *output, u32 *_out_len ); +void +halrf_cmn_info_init( + void *dm_void, + enum halrf_cmninfo_init cmn_info, + u32 value +); + +void +halrf_cmn_info_hook( + void *dm_void, + u32 cmn_info, + void *value +); + void halrf_cmn_info_set( - void *p_dm_void, + void *dm_void, u32 cmn_info, u64 value ); u64 halrf_cmn_info_get( - void *p_dm_void, + void *dm_void, u32 cmn_info ); void halrf_watchdog( - void *p_dm_void + void *dm_void ); void halrf_supportability_init( - void *p_dm_void + void *dm_void ); void halrf_init( - void *p_dm_void + void *dm_void ); +void +halrf_iqk_trigger( + void *dm_void, + boolean is_recovery +); +void +halrf_segment_iqk_trigger( + void *dm_void, + boolean clear, + boolean segment_iqk +); +void +halrf_lck_trigger( + void *dm_void +); + +void +halrf_iqk_debug( + void *dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +void +phydm_get_iqk_cfir( + void *dm_void, + u8 idx, + u8 path, + boolean debug +); + +void +halrf_iqk_xym_read( + void *dm_void, + u8 path, + u8 xym_type + ); + +void +halrf_rf_lna_setting( + void *dm_void, + enum phydm_lna_set type +); + + +void +halrf_do_imr_test( + void *dm_void, + u8 data +); + +u32 +halrf_psd_log2base( + u32 val +); + + +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) +void halrf_iqk_dbg(void *dm_void); +#endif #endif + + diff --git a/hal/phydm/halrf/halrf_features.h b/hal/phydm/halrf/halrf_features.h index f8edbfd..c6ef3e6 100644 --- a/hal/phydm/halrf/halrf_features.h +++ b/hal/phydm/halrf/halrf_features.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #ifndef __HALRF_FEATURES_H__ #define __HALRF_FEATURES diff --git a/hal/phydm/halrf/halrf_iqk.h b/hal/phydm/halrf/halrf_iqk.h index 006b554..846feb1 100644 --- a/hal/phydm/halrf/halrf_iqk.h +++ b/hal/phydm/halrf/halrf_iqk.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #ifndef __PHYDMIQK_H__ #define __PHYDMIQK_H__ @@ -31,14 +36,14 @@ #define RXIQK2 2 #define kcount_limit_80m 2 #define kcount_limit_others 4 -#define rxiqk_gs_limit 4 +#define rxiqk_gs_limit 10 #define NUM 4 /*---------------------------End Define Parameters-------------------------------*/ -struct _IQK_INFORMATION { - boolean LOK_fail[NUM]; - boolean IQK_fail[2][NUM]; +struct dm_iqk_info { + boolean lok_fail[NUM]; + boolean iqk_fail[2][NUM]; u32 iqc_matrix[2][NUM]; u8 iqk_times; u32 rf_reg18; @@ -46,20 +51,35 @@ struct _IQK_INFORMATION { u8 rxiqk_step; u8 tmp1bcc; u8 kcount; - + u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/ + boolean rfk_forbidden; +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) u32 iqk_channel[2]; - boolean IQK_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */ - u32 IQK_CFIR_real[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ - u32 IQK_CFIR_imag[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ + boolean iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */ + u32 iqk_cfir_real[3][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ /*channel index = 2 is just for debug*/ + u32 iqk_cfir_imag[3][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ /*channel index = 2 is just for debug*/ u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */ u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */ - u8 RXIQK_fail_code[2][4]; /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */ - u32 LOK_IDAC[2][4]; /*channel / path*/ - u16 RXIQK_AGC[2][4]; /*channel / path*/ + u8 rxiqk_fail_code[2][4]; /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */ + u32 lok_idac[2][4]; /*channel / path*/ + u16 rxiqk_agc[2][4]; /*channel / path*/ u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/ - u32 tmp_GNTWL; - boolean is_BTG; + u32 txgap_result[8]; /*txagpK result */ + u32 tmp_gntwl; + boolean is_btg; boolean isbnd; + boolean is_reload; + boolean segment_iqk; + boolean is_hwtx; + + boolean xym_read; + boolean trximr_enable; + u32 rx_xym[2][10]; + u32 tx_xym[2][10]; + u32 gs1_xym[2][6]; + u32 gs2_xym[2][6]; + u32 rxk1_xym[2][6]; +#endif }; #endif diff --git a/hal/phydm/halrf/halrf_kfree.c b/hal/phydm/halrf/halrf_kfree.c index 1e67dc0..acc705f 100644 --- a/hal/phydm/halrf/halrf_kfree.c +++ b/hal/phydm/halrf/halrf_kfree.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ /*============================================================*/ /*include files*/ @@ -30,79 +35,79 @@ void phydm_set_kfree_to_rf_8814a( - void *p_dm_void, + void *dm_void, u8 e_rf_path, u8 data ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; boolean is_odd; if ((data % 2) != 0) { /*odd->positive*/ data = data - 1; - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 1); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 1); is_odd = true; } else { /*even->negative*/ - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 0); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 0); is_odd = false; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", is_odd)); + PHYDM_DBG(dm, ODM_COMP_MP, "phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", is_odd); switch (data) { case 0: - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0); - p_rf_calibrate_info->kfree_offset[e_rf_path] = 0; + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0); + cali_info->kfree_offset[e_rf_path] = 0; break; case 2: - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0); - p_rf_calibrate_info->kfree_offset[e_rf_path] = 0; + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0); + cali_info->kfree_offset[e_rf_path] = 0; break; case 4: - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1); - p_rf_calibrate_info->kfree_offset[e_rf_path] = 1; + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1); + cali_info->kfree_offset[e_rf_path] = 1; break; case 6: - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1); - p_rf_calibrate_info->kfree_offset[e_rf_path] = 1; + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1); + cali_info->kfree_offset[e_rf_path] = 1; break; case 8: - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2); - p_rf_calibrate_info->kfree_offset[e_rf_path] = 2; + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2); + cali_info->kfree_offset[e_rf_path] = 2; break; case 10: - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2); - p_rf_calibrate_info->kfree_offset[e_rf_path] = 2; + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2); + cali_info->kfree_offset[e_rf_path] = 2; break; case 12: - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3); - p_rf_calibrate_info->kfree_offset[e_rf_path] = 3; + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3); + cali_info->kfree_offset[e_rf_path] = 3; break; case 14: - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3); - p_rf_calibrate_info->kfree_offset[e_rf_path] = 3; + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3); + cali_info->kfree_offset[e_rf_path] = 3; break; case 16: - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4); - p_rf_calibrate_info->kfree_offset[e_rf_path] = 4; + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4); + cali_info->kfree_offset[e_rf_path] = 4; break; case 18: - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4); - p_rf_calibrate_info->kfree_offset[e_rf_path] = 4; + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4); + cali_info->kfree_offset[e_rf_path] = 4; break; case 20: - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); - odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 5); - p_rf_calibrate_info->kfree_offset[e_rf_path] = 5; + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 5); + cali_info->kfree_offset[e_rf_path] = 5; break; default: @@ -111,10 +116,10 @@ phydm_set_kfree_to_rf_8814a( if (is_odd == false) { /*that means Kfree offset is negative, we need to record it.*/ - p_rf_calibrate_info->kfree_offset[e_rf_path] = (-1) * p_rf_calibrate_info->kfree_offset[e_rf_path]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): kfree_offset = %d\n", p_rf_calibrate_info->kfree_offset[e_rf_path])); + cali_info->kfree_offset[e_rf_path] = (-1) * cali_info->kfree_offset[e_rf_path]; + PHYDM_DBG(dm, ODM_COMP_MP, "phy_ConfigKFree8814A(): kfree_offset = %d\n", cali_info->kfree_offset[e_rf_path]); } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): kfree_offset = %d\n", p_rf_calibrate_info->kfree_offset[e_rf_path])); + PHYDM_DBG(dm, ODM_COMP_MP, "phy_ConfigKFree8814A(): kfree_offset = %d\n", cali_info->kfree_offset[e_rf_path]); } @@ -125,66 +130,66 @@ phydm_set_kfree_to_rf_8814a( // void phydm_get_thermal_trim_offset_8821c( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; u8 pg_therm = 0xff; - odm_efuse_one_byte_read(p_dm_odm, PPG_THERMAL_OFFSET_8821C, &pg_therm, false); + odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_8821C, &pg_therm, false); if (pg_therm != 0xff) { pg_therm = pg_therm & 0x1f; - if ((pg_therm & BIT0) == 0) - p_power_trim_info->thermal = (-1 * (pg_therm >> 1)); + if ((pg_therm & BIT(0)) == 0) + power_trim_info->thermal = (-1 * (pg_therm >> 1)); else - p_power_trim_info->thermal = (pg_therm >> 1); + power_trim_info->thermal = (pg_therm >> 1); - p_power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON; + power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8821c thermal trim flag:0x%02x\n", p_power_trim_info->flag)); + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8821c thermal trim flag:0x%02x\n", power_trim_info->flag); - if (p_power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8821c thermal:%d\n", p_power_trim_info->thermal)); + if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8821c thermal:%d\n", power_trim_info->thermal); } void phydm_get_power_trim_offset_8821c( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; u8 pg_power = 0xff, i; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_2G_TXAB_OFFSET_8821C, &pg_power, false); + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_2G_TXAB_OFFSET_8821C, &pg_power, false); if (pg_power != 0xff) { - p_power_trim_info->bb_gain[0][0] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C, &pg_power, false); - p_power_trim_info->bb_gain[1][0] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C, &pg_power, false); - p_power_trim_info->bb_gain[2][0] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C, &pg_power, false); - p_power_trim_info->bb_gain[3][0] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C, &pg_power, false); - p_power_trim_info->bb_gain[4][0] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C, &pg_power, false); - p_power_trim_info->bb_gain[5][0] = pg_power; - p_power_trim_info->flag = p_power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G | KFREE_FLAG_ON_5G; + power_trim_info->bb_gain[0][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C, &pg_power, false); + power_trim_info->bb_gain[1][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C, &pg_power, false); + power_trim_info->bb_gain[2][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C, &pg_power, false); + power_trim_info->bb_gain[3][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C, &pg_power, false); + power_trim_info->bb_gain[4][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C, &pg_power, false); + power_trim_info->bb_gain[5][0] = pg_power; + power_trim_info->flag = power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G | KFREE_FLAG_ON_5G; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8821c power trim flag:0x%02x\n", p_power_trim_info->flag)); + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8821c power trim flag:0x%02x\n", power_trim_info->flag); - if (p_power_trim_info->flag & KFREE_FLAG_ON) { - for (i = 0; i < 6; i++) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8821c power_trim_data->bb_gain[%d][0]=0x%X\n", i, p_power_trim_info->bb_gain[i][0])); + if (power_trim_info->flag & KFREE_FLAG_ON) { + for (i = 0; i < KFREE_BAND_NUM; i++) + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8821c power_trim_data->bb_gain[%d][0]=0x%X\n", i, power_trim_info->bb_gain[i][0]); } } @@ -192,86 +197,119 @@ phydm_get_power_trim_offset_8821c( void phydm_set_kfree_to_rf_8821c( - void *p_dm_void, + void *dm_void, u8 e_rf_path, boolean wlg_btg, u8 data ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - boolean is_odd; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; u8 wlg, btg; - odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(0), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(5), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(6), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, BIT(6), 1); + odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 1); + odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(5), 1); + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(6), 1); + odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(6), 1); if (wlg_btg == true) { wlg = data & 0xf; btg = (data & 0xf0) >> 4; - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(19), (wlg & BIT(0))); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (wlg >> 1)); + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (wlg & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (wlg >> 1)); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, BIT(19), (btg & BIT(0))); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (btg >> 1)); + odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(19), (btg & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, 0x65, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (btg >> 1)); } else { - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1)); + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1)); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, - ("[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n", - odm_get_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), - odm_get_rf_reg(p_dm_odm, e_rf_path, 0x65, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))) - )); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n", + odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), + odm_get_rf_reg(dm, e_rf_path, 0x65, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))) + ); +} + + + +void +phydm_clear_kfree_to_rf_8821c( + void *dm_void, + u8 e_rf_path, + u8 data +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 1); + odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(5), 1); + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(6), 1); + odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(6), 1); + + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (data >> 1)); + + odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, 0x65, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (data >> 1)); + + odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 0); + odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(5), 0); + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(6), 0); + odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(6), 0); + + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n", + odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), + odm_get_rf_reg(dm, e_rf_path, 0x65, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))) + ); } void phydm_get_thermal_trim_offset_8822b( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; - u8 pg_therm = 0xff, i; + u8 pg_therm = 0xff; #if 0 u32 thermal_trim_enable = 0xff; - odm_efuse_logical_map_read(p_dm_odm, 1, 0xc8, &thermal_trim_enable); + odm_efuse_logical_map_read(dm, 1, 0xc8, &thermal_trim_enable); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b 0xc8:0x%2x\n", thermal_trim_enable)); + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 0xc8:0x%2x\n", thermal_trim_enable); thermal_trim_enable = (thermal_trim_enable & BIT(5)) >> 5; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b thermal trim Enable:%d\n", thermal_trim_enable)); + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b thermal trim Enable:%d\n", thermal_trim_enable); - if ((p_rf_calibrate_info->reg_rf_kfree_enable == 0 && thermal_trim_enable == 1) || - p_rf_calibrate_info->reg_rf_kfree_enable == 1) { + if ((cali_info->reg_rf_kfree_enable == 0 && thermal_trim_enable == 1) || + cali_info->reg_rf_kfree_enable == 1) { #endif - odm_efuse_one_byte_read(p_dm_odm, PPG_THERMAL_OFFSET, &pg_therm, false); + odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET, &pg_therm, false); if (pg_therm != 0xff) { pg_therm = pg_therm & 0x1f; - if ((pg_therm & BIT0) == 0) - p_power_trim_info->thermal = (-1 * (pg_therm >> 1)); + if ((pg_therm & BIT(0)) == 0) + power_trim_info->thermal = (-1 * (pg_therm >> 1)); else - p_power_trim_info->thermal = (pg_therm >> 1); + power_trim_info->thermal = (pg_therm >> 1); - p_power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON; + power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b thermal trim flag:0x%02x\n", p_power_trim_info->flag)); + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b thermal trim flag:0x%02x\n", power_trim_info->flag); - if (p_power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b thermal:%d\n", p_power_trim_info->thermal)); + if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b thermal:%d\n", power_trim_info->thermal); #if 0 } else return; @@ -283,83 +321,84 @@ phydm_get_thermal_trim_offset_8822b( void phydm_get_power_trim_offset_8822b( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; u8 pg_power = 0xff, i, j; #if 0 u32 power_trim_enable = 0xff; - odm_efuse_logical_map_read(p_dm_odm, 1, 0xc8, &power_trim_enable); + odm_efuse_logical_map_read(dm, 1, 0xc8, &power_trim_enable); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b 0xc8:0x%2x\n", power_trim_enable)); + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 0xc8:0x%2x\n", power_trim_enable); power_trim_enable = (power_trim_enable & BIT(4)) >> 4; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b power trim Enable:%d\n", power_trim_enable)); + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b power trim Enable:%d\n", power_trim_enable); - if ((p_rf_calibrate_info->reg_rf_kfree_enable == 0 && power_trim_enable == 1) || - p_rf_calibrate_info->reg_rf_kfree_enable == 1) { + if ((cali_info->reg_rf_kfree_enable == 0 && power_trim_enable == 1) || + cali_info->reg_rf_kfree_enable == 1) { #endif - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false); + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false); if (pg_power != 0xff) { /*Path A*/ - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false); - p_power_trim_info->bb_gain[0][0] = (pg_power & 0xf); + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false); + power_trim_info->bb_gain[0][0] = (pg_power & 0xf); /*Path B*/ - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false); - p_power_trim_info->bb_gain[0][1] = ((pg_power & 0xf0) >> 4); + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false); + power_trim_info->bb_gain[0][1] = ((pg_power & 0xf0) >> 4); - p_power_trim_info->flag |= KFREE_FLAG_ON_2G; - p_power_trim_info->flag |= KFREE_FLAG_ON; + power_trim_info->flag |= KFREE_FLAG_ON_2G; + power_trim_info->flag |= KFREE_FLAG_ON; } - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL1_TXA_OFFSET, &pg_power, false); + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL1_TXA_OFFSET, &pg_power, false); if (pg_power != 0xff) { /*Path A*/ - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL1_TXA_OFFSET, &pg_power, false); - p_power_trim_info->bb_gain[1][0] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL2_TXA_OFFSET, &pg_power, false); - p_power_trim_info->bb_gain[2][0] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM1_TXA_OFFSET, &pg_power, false); - p_power_trim_info->bb_gain[3][0] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM2_TXA_OFFSET, &pg_power, false); - p_power_trim_info->bb_gain[4][0] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GH1_TXA_OFFSET, &pg_power, false); - p_power_trim_info->bb_gain[5][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL1_TXA_OFFSET, &pg_power, false); + power_trim_info->bb_gain[1][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL2_TXA_OFFSET, &pg_power, false); + power_trim_info->bb_gain[2][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM1_TXA_OFFSET, &pg_power, false); + power_trim_info->bb_gain[3][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM2_TXA_OFFSET, &pg_power, false); + power_trim_info->bb_gain[4][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GH1_TXA_OFFSET, &pg_power, false); + power_trim_info->bb_gain[5][0] = pg_power; /*Path B*/ - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL1_TXB_OFFSET, &pg_power, false); - p_power_trim_info->bb_gain[1][1] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL2_TXB_OFFSET, &pg_power, false); - p_power_trim_info->bb_gain[2][1] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM1_TXB_OFFSET, &pg_power, false); - p_power_trim_info->bb_gain[3][1] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM2_TXB_OFFSET, &pg_power, false); - p_power_trim_info->bb_gain[4][1] = pg_power; - odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GH1_TXB_OFFSET, &pg_power, false); - p_power_trim_info->bb_gain[5][1] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL1_TXB_OFFSET, &pg_power, false); + power_trim_info->bb_gain[1][1] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL2_TXB_OFFSET, &pg_power, false); + power_trim_info->bb_gain[2][1] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM1_TXB_OFFSET, &pg_power, false); + power_trim_info->bb_gain[3][1] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM2_TXB_OFFSET, &pg_power, false); + power_trim_info->bb_gain[4][1] = pg_power; + odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GH1_TXB_OFFSET, &pg_power, false); + power_trim_info->bb_gain[5][1] = pg_power; - p_power_trim_info->flag |= KFREE_FLAG_ON_5G; - p_power_trim_info->flag |= KFREE_FLAG_ON; + power_trim_info->flag |= KFREE_FLAG_ON_5G; + power_trim_info->flag |= KFREE_FLAG_ON; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b power trim flag:0x%02x\n", p_power_trim_info->flag)); + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b power trim flag:0x%02x\n", power_trim_info->flag); - if (p_power_trim_info->flag & KFREE_FLAG_ON) { - for (i = 0; i < 6; i++) { - for (j = 0; j < 2; j++) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b power_trim_data->bb_gain[%d][%d]=0x%X\n", i, j, p_power_trim_info->bb_gain[i][j])); - } + if (!(power_trim_info->flag & KFREE_FLAG_ON)) + return; + + for (i = 0; i < KFREE_BAND_NUM; i++) { + for (j = 0; j < 2; j++) + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b power_trim_data->bb_gain[%d][%d]=0x%X\n", i, j, power_trim_info->bb_gain[i][j]); } #if 0 } else @@ -371,179 +410,303 @@ phydm_get_power_trim_offset_8822b( void phydm_set_pa_bias_to_rf_8822b( - void *p_dm_void, + void *dm_void, u8 e_rf_path, s8 tx_pa_bias ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + u32 rf_reg_51 = 0, rf_reg_52 = 0, rf_reg_3f = 0; + + rf_reg_51 = odm_get_rf_reg(dm, e_rf_path, 0x51, RFREGOFFSETMASK); + rf_reg_52 = odm_get_rf_reg(dm, e_rf_path, 0x52, RFREGOFFSETMASK); - tx_pa_bias = tx_pa_bias + (u8)odm_get_rf_reg(p_dm_odm, e_rf_path, 0x51, (BIT(6) | BIT(5) | BIT(4) | BIT(3))); + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 2g rf(0x51)=0x%X rf(0x52)=0x%X path=%d\n", + rf_reg_51, rf_reg_52, e_rf_path); + + /*rf3f => rf52[19:17] = rf3f[2:0] rf52[16:15] = rf3f[4:3] rf52[3:0] = rf3f[8:5]*/ + /*rf3f => rf51[6:3] = rf3f[12:9] rf52[13] = rf3f[13]*/ + rf_reg_3f = ((rf_reg_52 & 0xe0000) >> 17) | + (((rf_reg_52 & 0x18000) >> 15) << 3) | + ((rf_reg_52 & 0xf) << 5) | + (((rf_reg_51 & 0x78) >> 3) << 9) | + (((rf_reg_52 & 0x2000) >> 13) << 13); + + PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b 2g original tx_pa_bias=%d rf_reg_3f=0x%X path=%d\n", + tx_pa_bias, rf_reg_3f, e_rf_path); + + tx_pa_bias = (s8)((rf_reg_3f & (BIT(12) | BIT(11) | BIT(10) | BIT(9))) >> 9) + tx_pa_bias; if (tx_pa_bias < 0) tx_pa_bias = 0; else if (tx_pa_bias > 7) tx_pa_bias = 7; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b 2g tx pa bias=0x%X rf 0x51=0x%X path=%d\n", tx_pa_bias, - odm_get_rf_reg(p_dm_odm, e_rf_path, 0x51, (BIT(6) | BIT(5) | BIT(4) | BIT(3))), e_rf_path)); + rf_reg_3f = ((rf_reg_3f & 0xfe1ff) | (tx_pa_bias << 9)); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0xef, BIT(10), 0x1); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x33, RFREGOFFSETMASK, 0x0); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9)), tx_pa_bias); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x33, BIT(0), 0x1); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9)), tx_pa_bias); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x33, BIT(1), 0x1); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9)), tx_pa_bias); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x33, (BIT(1) | BIT(0)), 0x3); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9)), tx_pa_bias); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0xef, BIT(10), 0x0); + PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b 2g offset efuse 0x3d5 0x3d6 tx_pa_bias=%d rf_reg_3f=0x%X path=%d\n", + tx_pa_bias, rf_reg_3f, e_rf_path); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b 2g tx pa bias rf_0x3f(0x%X) path=%d\n", - odm_get_rf_reg(p_dm_odm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9))), e_rf_path)); + odm_set_rf_reg(dm, e_rf_path, 0xef, BIT(10), 0x1); + odm_set_rf_reg(dm, e_rf_path, 0x33, RFREGOFFSETMASK, 0x0); + odm_set_rf_reg(dm, e_rf_path, 0x3f, RFREGOFFSETMASK, rf_reg_3f); + odm_set_rf_reg(dm, e_rf_path, 0x33, BIT(0), 0x1); + odm_set_rf_reg(dm, e_rf_path, 0x3f, RFREGOFFSETMASK, rf_reg_3f); + odm_set_rf_reg(dm, e_rf_path, 0x33, BIT(1), 0x1); + odm_set_rf_reg(dm, e_rf_path, 0x3f, RFREGOFFSETMASK, rf_reg_3f); + odm_set_rf_reg(dm, e_rf_path, 0x33, (BIT(1) | BIT(0)), 0x3); + odm_set_rf_reg(dm, e_rf_path, 0x3f, RFREGOFFSETMASK, rf_reg_3f); + odm_set_rf_reg(dm, e_rf_path, 0xef, BIT(10), 0x0); + PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b 2g tx pa bias rf_0x3f(0x%X) path=%d\n", + odm_get_rf_reg(dm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9))), e_rf_path); } void phydm_get_pa_bias_offset_8822b( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; u8 pg_pa_bias = 0xff, e_rf_path = 0; s8 tx_pa_bias[2] = {0}; - odm_efuse_one_byte_read(p_dm_odm, PPG_PA_BIAS_2G_TXA_OFFSET, &pg_pa_bias, false); + odm_efuse_one_byte_read(dm, PPG_PA_BIAS_2G_TXA_OFFSET, &pg_pa_bias, false); if (pg_pa_bias != 0xff) { /*paht a*/ - odm_efuse_one_byte_read(p_dm_odm, PPG_PA_BIAS_2G_TXA_OFFSET, &pg_pa_bias, false); + odm_efuse_one_byte_read(dm, PPG_PA_BIAS_2G_TXA_OFFSET, &pg_pa_bias, false); pg_pa_bias = pg_pa_bias & 0xf; - if ((pg_pa_bias & BIT0) == 0) + if ((pg_pa_bias & BIT(0)) == 0) tx_pa_bias[0] = (-1 * (pg_pa_bias >> 1)); else tx_pa_bias[0] = (pg_pa_bias >> 1); /*paht b*/ - odm_efuse_one_byte_read(p_dm_odm, PPG_PA_BIAS_2G_TXB_OFFSET, &pg_pa_bias, false); + odm_efuse_one_byte_read(dm, PPG_PA_BIAS_2G_TXB_OFFSET, &pg_pa_bias, false); pg_pa_bias = pg_pa_bias & 0xf; - if ((pg_pa_bias & BIT0) == 0) + if ((pg_pa_bias & BIT(0)) == 0) tx_pa_bias[1] = (-1 * (pg_pa_bias >> 1)); else tx_pa_bias[1] = (pg_pa_bias >> 1); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b 2g tx_patha_pa_bias:%d tx_pathb_pa_bias:%d\n", tx_pa_bias[0], tx_pa_bias[1])); + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 2g tx_patha_pa_bias:%d tx_pathb_pa_bias:%d\n", tx_pa_bias[0], tx_pa_bias[1]); - for (e_rf_path = ODM_RF_PATH_A; e_rf_path < 2; e_rf_path++) - phydm_set_pa_bias_to_rf_8822b(p_dm_odm, e_rf_path, tx_pa_bias[e_rf_path]); + for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++) + phydm_set_pa_bias_to_rf_8822b(dm, e_rf_path, tx_pa_bias[e_rf_path]); + + power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON; } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8822b 2g tx pa bias no pg\n")); + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 2g tx pa bias no pg\n"); } void phydm_set_kfree_to_rf_8822b( - void *p_dm_void, + void *dm_void, u8 e_rf_path, u8 data ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(0), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(4), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, bMaskLWord, 0x9000); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(5), 1); + odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 1); + odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(4), 1); + odm_set_rf_reg(dm, e_rf_path, 0x65, MASKLWORD, 0x9000); + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(5), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1)); + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, - ("[kfree] 8822b 0x55[19:14]=0x%X path=%d\n", - odm_get_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), + PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b 0x55[19:14]=0x%X path=%d\n", + odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), e_rf_path - )); + ); } void phydm_clear_kfree_to_rf_8822b( - void *p_dm_void, + void *dm_void, + u8 e_rf_path, + u8 data +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 1); + odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(4), 1); + odm_set_rf_reg(dm, e_rf_path, 0x65, MASKLWORD, 0x9000); + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(5), 1); + + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1)); + + odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 0); + odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(4), 1); + odm_set_rf_reg(dm, e_rf_path, 0x65, MASKLWORD, 0x9000); + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(5), 0); + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(7), 0); + + PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b clear power trim 0x55[19:14]=0x%X path=%d\n", + odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), + e_rf_path + ); +} + +void +phydm_get_thermal_trim_offset_8710b( +void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &(dm->power_trim_data); + + u8 pg_therm = 0xff; + + odm_efuse_one_byte_read(dm, 0x0EF, &pg_therm, false); + + if (pg_therm != 0xff) { + pg_therm = pg_therm & 0x1f; + if ((pg_therm & BIT(0)) == 0) + power_trim_info->thermal = (-1 * (pg_therm >> 1)); + else + power_trim_info->thermal = (pg_therm >> 1); + + power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON; + } + + ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8710b thermal trim flag:0x%02x\n", power_trim_info->flag)); + + if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8710b thermal:%d\n", power_trim_info->thermal)); + +} + +void +phydm_get_power_trim_offset_8710b( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &(dm->power_trim_data); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + u8 pg_power = 0xff; + + odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false); + + if (pg_power != 0xff) { + /*Path A*/ + odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false); + power_trim_info->bb_gain[0][0] = (pg_power & 0xf); + + power_trim_info->flag |= KFREE_FLAG_ON_2G; + power_trim_info->flag |= KFREE_FLAG_ON; + } + + + ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8710b power trim flag:0x%02x\n", power_trim_info->flag)); + + if (power_trim_info->flag & KFREE_FLAG_ON) + + ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8710b power_trim_data->bb_gain[0][0]=0x%X\n", power_trim_info->bb_gain[0][0])); + +} +void +phydm_set_kfree_to_rf_8710b( + void *dm_void, u8 e_rf_path, u8 data ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - - odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(0), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(4), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, bMaskLWord, 0x9000); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(5), 1); - - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1)); - - odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(0), 0); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(4), 1); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, bMaskLWord, 0x9000); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(5), 0); - odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(7), 0); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, - ("[kfree] 8822b clear power trim 0x55[19:14]=0x%X path=%d\n", - odm_get_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15)), ((data & 0xf) >> 1)); + + ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, + ("[kfree] 8710b 0x55[19:14]=0x%X path=%d\n", + odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), e_rf_path )); } +void +phydm_clear_kfree_to_rf_8710b( + void *dm_void, + u8 e_rf_path, + u8 data +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1)); + + ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, + ("[kfree] 8710b clear power trim 0x55[19:14]=0x%X path=%d\n", + odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), + e_rf_path + )); +} void phydm_set_kfree_to_rf( - void *p_dm_void, + void *dm_void, u8 e_rf_path, u8 data ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - phydm_set_kfree_to_rf_8814a(p_dm_odm, e_rf_path, data); + if (dm->support_ic_type & ODM_RTL8814A) + phydm_set_kfree_to_rf_8814a(dm, e_rf_path, data); - if ((p_dm_odm->support_ic_type & ODM_RTL8821C) && (*p_dm_odm->p_band_type == ODM_BAND_2_4G)) - phydm_set_kfree_to_rf_8821c(p_dm_odm, e_rf_path, true, data); - else if (p_dm_odm->support_ic_type & ODM_RTL8821C) - phydm_set_kfree_to_rf_8821c(p_dm_odm, e_rf_path, false, data); + if ((dm->support_ic_type & ODM_RTL8821C) && (*dm->band_type == ODM_BAND_2_4G)) + phydm_set_kfree_to_rf_8821c(dm, e_rf_path, true, data); + else if (dm->support_ic_type & ODM_RTL8821C) + phydm_set_kfree_to_rf_8821c(dm, e_rf_path, false, data); - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - phydm_set_kfree_to_rf_8822b(p_dm_odm, e_rf_path, data); + if (dm->support_ic_type & ODM_RTL8822B) + phydm_set_kfree_to_rf_8822b(dm, e_rf_path, data); + if (dm->support_ic_type & ODM_RTL8710B) + phydm_set_kfree_to_rf_8710b(dm, e_rf_path, data); } void phydm_clear_kfree_to_rf( - void *p_dm_void, + void *dm_void, u8 e_rf_path, u8 data ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_RTL8822B) + phydm_clear_kfree_to_rf_8822b(dm, e_rf_path, 1); + + if (dm->support_ic_type & ODM_RTL8821C) + phydm_clear_kfree_to_rf_8821c(dm, e_rf_path, 1); - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - phydm_clear_kfree_to_rf_8822b(p_dm_odm, e_rf_path, 1); + if (dm->support_ic_type & ODM_RTL8710B) + phydm_set_kfree_to_rf_8710b(dm, e_rf_path, data); } @@ -551,87 +714,92 @@ phydm_clear_kfree_to_rf( void phydm_get_thermal_trim_offset( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - PEFUSE_HAL pEfuseHal = &(p_hal_data->EfuseHal); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal; u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2]; - if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] dump efuse fail !!!\n")); + if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS) + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] dump efuse fail !!!\n"); #endif - if (p_dm_odm->support_ic_type & ODM_RTL8821C) - phydm_get_thermal_trim_offset_8821c(p_dm_void); - else if (p_dm_odm->support_ic_type & ODM_RTL8822B) - phydm_get_thermal_trim_offset_8822b(p_dm_void); + if (dm->support_ic_type & ODM_RTL8821C) + phydm_get_thermal_trim_offset_8821c(dm_void); + else if (dm->support_ic_type & ODM_RTL8822B) + phydm_get_thermal_trim_offset_8822b(dm_void); + else if (dm->support_ic_type & ODM_RTL8710B) + phydm_get_thermal_trim_offset_8710b(dm_void); } void phydm_get_power_trim_offset( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - PEFUSE_HAL pEfuseHal = &(p_hal_data->EfuseHal); +#if 0 //(DM_ODM_SUPPORT_TYPE & ODM_WIN) // 2017 MH DM Should use the same code.s + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal; u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2]; if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] dump efuse fail !!!\n")); + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] dump efuse fail !!!\n"); #endif - if (p_dm_odm->support_ic_type & ODM_RTL8821C) - phydm_get_power_trim_offset_8821c(p_dm_void); - else if (p_dm_odm->support_ic_type & ODM_RTL8822B) - phydm_get_power_trim_offset_8822b(p_dm_void); + if (dm->support_ic_type & ODM_RTL8821C) + phydm_get_power_trim_offset_8821c(dm_void); + else if (dm->support_ic_type & ODM_RTL8822B) + phydm_get_power_trim_offset_8822b(dm_void); + else if (dm->support_ic_type & ODM_RTL8710B) + phydm_get_power_trim_offset_8710b(dm_void); + } void phydm_get_pa_bias_offset( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - PEFUSE_HAL pEfuseHal = &(p_hal_data->EfuseHal); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal; u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2]; - if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] dump efuse fail !!!\n")); + if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS) + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] dump efuse fail !!!\n"); #endif - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - phydm_get_pa_bias_offset_8822b(p_dm_void); + if (dm->support_ic_type & ODM_RTL8822B) + phydm_get_pa_bias_offset_8822b(dm_void); } s8 phydm_get_thermal_offset( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; - if (p_power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) - return p_power_trim_info->thermal; + if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + return power_trim_info->thermal; else return 0; } @@ -640,77 +808,76 @@ phydm_get_thermal_offset( void phydm_config_kfree( - void *p_dm_void, + void *dm_void, u8 channel_to_sw ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; u8 rfpath = 0, max_rf_path = 0; u8 channel_idx = 0, i, j; - if (p_dm_odm->support_ic_type & ODM_RTL8814A) + if (dm->support_ic_type & ODM_RTL8814A) max_rf_path = 4; /*0~3*/ - else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B)) + else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B)) max_rf_path = 2; /*0~1*/ - else if (p_dm_odm->support_ic_type & ODM_RTL8821C) + else if (dm->support_ic_type & (ODM_RTL8821C| ODM_RTL8710B)) max_rf_path = 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("===>[kfree] phy_ConfigKFree()\n")); + PHYDM_DBG(dm, ODM_COMP_MP, "===>[kfree] phy_ConfigKFree()\n"); - if (p_rf_calibrate_info->reg_rf_kfree_enable == 2) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == 2, Disable\n")); + if (cali_info->reg_rf_kfree_enable == 2) { + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == 2, Disable\n"); return; - } else if (p_rf_calibrate_info->reg_rf_kfree_enable == 1 || p_rf_calibrate_info->reg_rf_kfree_enable == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == true\n")); + } else if (cali_info->reg_rf_kfree_enable == 1 || cali_info->reg_rf_kfree_enable == 0) { + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == true\n"); /*Make sure the targetval is defined*/ - if (p_power_trim_info->flag & KFREE_FLAG_ON) { - /*if kfree_table[0] == 0xff, means no Kfree*/ - - for (i = 0; i < BB_GAIN_NUM; i++) { - for (j = 0; j < max_rf_path; j++) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] power_trim_data->bb_gain[%d][%d]=0x%X\n", i, j, p_power_trim_info->bb_gain[i][j])); + if (!(power_trim_info->flag & KFREE_FLAG_ON)) { + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phy_ConfigKFree(): targetval not defined, Don't execute KFree Process.\n"); + return; + } + /*if kfree_table[0] == 0xff, means no Kfree*/ + if (dm->support_ic_type &ODM_RTL8710B) + ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] power_trim_data->bb_gain[0][0]=0x%X\n", power_trim_info->bb_gain[0][0])); + else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B |ODM_RTL8821C | ODM_RTL8814A)){ + for (i = 0; i < KFREE_BAND_NUM; i++) { + for (j = 0; j < max_rf_path; j++) + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] power_trim_data->bb_gain[%d][%d]=0x%X\n", i, j, power_trim_info->bb_gain[i][j]); + } } + if (*dm->band_type == ODM_BAND_2_4G && power_trim_info->flag & KFREE_FLAG_ON_2G) { + if (channel_to_sw >= 1 && channel_to_sw <= 14) + channel_idx = PHYDM_2G; - if (*p_dm_odm->p_band_type == ODM_BAND_2_4G && p_power_trim_info->flag & KFREE_FLAG_ON_2G) { - - if (channel_to_sw >= 1 && channel_to_sw <= 14) - channel_idx = PHYDM_2G; - - for (rfpath = ODM_RF_PATH_A; rfpath < max_rf_path; rfpath++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phydm_kfree(): channel_to_sw=%d PATH_%d bb_gain:0x%X\n", channel_to_sw, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath])); - phydm_set_kfree_to_rf(p_dm_odm, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath]); - } - - } else if (*p_dm_odm->p_band_type == ODM_BAND_5G && p_power_trim_info->flag & KFREE_FLAG_ON_5G) { - - if (channel_to_sw >= 36 && channel_to_sw <= 48) - channel_idx = PHYDM_5GLB1; - if (channel_to_sw >= 52 && channel_to_sw <= 64) - channel_idx = PHYDM_5GLB2; - if (channel_to_sw >= 100 && channel_to_sw <= 120) - channel_idx = PHYDM_5GMB1; - if (channel_to_sw >= 122 && channel_to_sw <= 144) - channel_idx = PHYDM_5GMB2; - if (channel_to_sw >= 149 && channel_to_sw <= 177) - channel_idx = PHYDM_5GHB; - - for (rfpath = ODM_RF_PATH_A; rfpath < max_rf_path; rfpath++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phydm_kfree(): channel_to_sw=%d PATH_%d bb_gain:0x%X\n", channel_to_sw, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath])); - phydm_set_kfree_to_rf(p_dm_odm, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath]); - } + for (rfpath = RF_PATH_A; rfpath < max_rf_path; rfpath++) { + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phydm_kfree(): channel_to_sw=%d PATH_%d bb_gain:0x%X\n", channel_to_sw, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]); + phydm_set_kfree_to_rf(dm, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]); } - else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] Set default Register\n")); - for (rfpath = ODM_RF_PATH_A; rfpath < max_rf_path; rfpath++) - phydm_clear_kfree_to_rf(p_dm_odm, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath]); + + } else if (*dm->band_type == ODM_BAND_5G && power_trim_info->flag & KFREE_FLAG_ON_5G) { + if (channel_to_sw >= 36 && channel_to_sw <= 48) + channel_idx = PHYDM_5GLB1; + if (channel_to_sw >= 52 && channel_to_sw <= 64) + channel_idx = PHYDM_5GLB2; + if (channel_to_sw >= 100 && channel_to_sw <= 120) + channel_idx = PHYDM_5GMB1; + if (channel_to_sw >= 122 && channel_to_sw <= 144) + channel_idx = PHYDM_5GMB2; + if (channel_to_sw >= 149 && channel_to_sw <= 177) + channel_idx = PHYDM_5GHB; + + for (rfpath = RF_PATH_A; rfpath < max_rf_path; rfpath++) { + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phydm_kfree(): channel_to_sw=%d PATH_%d bb_gain:0x%X\n", channel_to_sw, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]); + phydm_set_kfree_to_rf(dm, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]); } } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phy_ConfigKFree(): targetval not defined, Don't execute KFree Process.\n")); - return; + PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] Set default Register\n"); + for (rfpath = RF_PATH_A; rfpath < max_rf_path; rfpath++) + phydm_clear_kfree_to_rf(dm, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]); } } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("<===[kfree] phy_ConfigKFree()\n")); + + PHYDM_DBG(dm, ODM_COMP_MP, "<===[kfree] phy_ConfigKFree()\n"); } diff --git a/hal/phydm/halrf/halrf_kfree.h b/hal/phydm/halrf/halrf_kfree.h index 5bdc8a0..a5159d1 100644 --- a/hal/phydm/halrf/halrf_kfree.h +++ b/hal/phydm/halrf/halrf_kfree.h @@ -1,7 +1,6 @@ - /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -9,32 +8,43 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * + * Larry Finger * - ******************************************************************************/ + *****************************************************************************/ + #ifndef __PHYDMKFREE_H__ #define __PHYDKFREE_H__ #define KFREE_VERSION "1.0" +#define KFREE_BAND_NUM 6 + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP)) #define BB_GAIN_NUM 6 -#define KFREE_FLAG_ON BIT(0) -#define KFREE_FLAG_THERMAL_K_ON BIT(1) #endif +#define KFREE_FLAG_ON BIT(0) +#define KFREE_FLAG_THERMAL_K_ON BIT(1) + #define KFREE_FLAG_ON_2G BIT(2) #define KFREE_FLAG_ON_5G BIT(3) +#define PA_BIAS_FLAG_ON BIT(4) + #define PPG_THERMAL_OFFSET_8821C 0x1EF #define PPG_BB_GAIN_2G_TXAB_OFFSET_8821C 0x1EE #define PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C 0x1EC @@ -76,7 +86,8 @@ struct odm_power_trim_data { u8 flag; - s8 bb_gain[BB_GAIN_NUM][MAX_RF_PATH]; + u8 pa_bias_flag; + s8 bb_gain[KFREE_BAND_NUM][MAX_RF_PATH]; s8 thermal; }; @@ -95,27 +106,35 @@ enum phydm_kfree_channeltosw { void phydm_get_thermal_trim_offset( - void *p_dm_void + void *dm_void ); void phydm_get_power_trim_offset( - void *p_dm_void + void *dm_void ); void phydm_get_pa_bias_offset( - void *p_dm_void + void *dm_void ); s8 phydm_get_thermal_offset( - void *p_dm_void + void *dm_void ); +void +phydm_clear_kfree_to_rf( + void *dm_void, + u8 e_rf_path, + u8 data +); + + void phydm_config_kfree( - void *p_dm_void, + void *dm_void, u8 channel_to_sw ); diff --git a/hal/phydm/halrf/halrf_powertracking_ap.c b/hal/phydm/halrf/halrf_powertracking_ap.c index 3868182..4e4e6a7 100644 --- a/hal/phydm/halrf/halrf_powertracking_ap.c +++ b/hal/phydm/halrf/halrf_powertracking_ap.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* ************************************************************ * include files @@ -697,7 +692,7 @@ u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = { }; #endif -#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1) +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = { 0x081, /* 0, -12.0dB */ 0x088, /* 1, -11.5dB */ @@ -881,35 +876,35 @@ u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = { void odm_txpowertracking_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - if (!(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES))) + if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES))) return; #endif - odm_txpowertracking_thermal_meter_init(p_dm_odm); + odm_txpowertracking_thermal_meter_init(dm); } u8 get_swing_index( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0, bb_swing_mask = 0; u32 bb_swing = 0; u32 swing_table_size = 0; - u32 *p_swing_table = 0; - struct rtl8192cd_priv *priv = p_dm_odm->priv; + u32 *swing_table = 0; + struct rtl8192cd_priv *priv = dm->priv; #if (RTL8197F_SUPPORT == 1) if (GET_CHIP_VER(priv) == VERSION_8197F) { bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D); - p_swing_table = ofdm_swing_table_new; + swing_table = ofdm_swing_table_new; swing_table_size = OFDM_TABLE_SIZE_92D; bb_swing_mask = 22; } @@ -918,20 +913,20 @@ get_swing_index( #if (RTL8822B_SUPPORT == 1) if (GET_CHIP_VER(priv) == VERSION_8822B) { bb_swing = phy_query_bb_reg(priv, REG_A_TX_SCALE_JAGUAR, 0xFFE00000); - p_swing_table = tx_scaling_table_jaguar; + swing_table = tx_scaling_table_jaguar; swing_table_size = TXSCALE_TABLE_SIZE; bb_swing_mask = 0; } #endif for (i = 0; i < swing_table_size - 1; i++) { - u32 table_value = p_swing_table[i] >> bb_swing_mask; + u32 table_value = swing_table[i] >> bb_swing_mask; if (bb_swing == table_value) break; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("bb_swing=0x%x bbswing_index=%d\n", bb_swing, i)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "bb_swing=0x%x bbswing_index=%d\n", bb_swing, i); return i; @@ -940,59 +935,56 @@ get_swing_index( void odm_txpowertracking_thermal_meter_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + struct rtl8192cd_priv *priv = dm->priv; u8 p; u8 default_swing_index; #if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B)) - default_swing_index = get_swing_index(p_dm_odm); + default_swing_index = get_swing_index(dm); #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &adapter->MgntInfo; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - p_mgnt_info->is_txpowertracking = true; - p_hal_data->tx_powercount = 0; - p_hal_data->is_txpowertracking_init = false; + mgnt_info->is_txpowertracking = true; + hal_data->tx_powercount = 0; + hal_data->is_txpowertracking_init = false; - if (*(p_dm_odm->p_mp_mode) == false) - p_hal_data->txpowertrack_control = true; - ODM_RT_TRACE(p_dm_odm, COMP_POWER_TRACKING, DBG_LOUD, ("p_mgnt_info->is_txpowertracking = %d\n", p_mgnt_info->is_txpowertracking)); + if (*(dm->mp_mode) == false) + hal_data->txpowertrack_control = true; + PHYDM_DBG(dm, COMP_POWER_TRACKING, "mgnt_info->is_txpowertracking = %d\n", mgnt_info->is_txpowertracking); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) #ifdef CONFIG_RTL8188E { - p_dm_odm->rf_calibrate_info.is_txpowertracking = _TRUE; - p_dm_odm->rf_calibrate_info.tx_powercount = 0; - p_dm_odm->rf_calibrate_info.is_txpowertracking_init = _FALSE; + dm->rf_calibrate_info.is_txpowertracking = true; + dm->rf_calibrate_info.tx_powercount = 0; + dm->rf_calibrate_info.is_txpowertracking_init = false; - if (*(p_dm_odm->p_mp_mode) == false) - p_dm_odm->rf_calibrate_info.txpowertrack_control = _TRUE; + if (*(dm->mp_mode) == false) + dm->rf_calibrate_info.txpowertrack_control = true; - MSG_8192C("p_dm_odm txpowertrack_control = %d\n", p_dm_odm->rf_calibrate_info.txpowertrack_control); + MSG_8192C("dm txpowertrack_control = %d\n", dm->rf_calibrate_info.txpowertrack_control); } #else { - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct dm_priv *pdmpriv = &p_hal_data->dmpriv; + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_priv *pdmpriv = &hal_data->dmpriv; + + pdmpriv->is_txpowertracking = true; + pdmpriv->tx_powercount = 0; + pdmpriv->is_txpowertracking_init = false; - /* if(IS_HARDWARE_TYPE_8192C(p_hal_data)) */ - { - pdmpriv->is_txpowertracking = _TRUE; - pdmpriv->tx_powercount = 0; - pdmpriv->is_txpowertracking_init = _FALSE; + if (*(dm->mp_mode) == false) /* for mp driver, turn off txpwrtracking as default */ + pdmpriv->txpowertrack_control = true; - if (*(p_dm_odm->p_mp_mode) == false) /* for mp driver, turn off txpwrtracking as default */ - pdmpriv->txpowertrack_control = _TRUE; - - } MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control); } @@ -1001,73 +993,73 @@ odm_txpowertracking_thermal_meter_init( #ifdef RTL8188E_SUPPORT { - p_dm_odm->rf_calibrate_info.is_txpowertracking = _TRUE; - p_dm_odm->rf_calibrate_info.tx_powercount = 0; - p_dm_odm->rf_calibrate_info.is_txpowertracking_init = _FALSE; - p_dm_odm->rf_calibrate_info.txpowertrack_control = _TRUE; - p_dm_odm->rf_calibrate_info.tm_trigger = 0; + dm->rf_calibrate_info.is_txpowertracking = true; + dm->rf_calibrate_info.tx_powercount = 0; + dm->rf_calibrate_info.is_txpowertracking_init = false; + dm->rf_calibrate_info.txpowertrack_control = true; + dm->rf_calibrate_info.tm_trigger = 0; } #endif #endif - p_dm_odm->rf_calibrate_info.txpowertrack_control = true; - p_dm_odm->rf_calibrate_info.delta_power_index = 0; - p_dm_odm->rf_calibrate_info.delta_power_index_last = 0; - p_dm_odm->rf_calibrate_info.power_index_offset = 0; - p_dm_odm->rf_calibrate_info.thermal_value = 0; - p_rf_calibrate_info->default_ofdm_index = 28; + dm->rf_calibrate_info.txpowertrack_control = true; + dm->rf_calibrate_info.delta_power_index = 0; + dm->rf_calibrate_info.delta_power_index_last = 0; + dm->rf_calibrate_info.power_index_offset = 0; + dm->rf_calibrate_info.thermal_value = 0; + cali_info->default_ofdm_index = 28; #if (RTL8197F_SUPPORT == 1) if (GET_CHIP_VER(priv) == VERSION_8197F) { - p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index; - p_rf_calibrate_info->default_cck_index = 28; + cali_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index; + cali_info->default_cck_index = 28; } #endif #if (RTL8822B_SUPPORT == 1) if (GET_CHIP_VER(priv) == VERSION_8822B) { - p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : default_swing_index; - p_rf_calibrate_info->default_cck_index = 20; + cali_info->default_ofdm_index = (default_swing_index >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : default_swing_index; + cali_info->default_cck_index = 20; } #endif #if RTL8188E_SUPPORT - p_rf_calibrate_info->default_cck_index = 20; /* -6 dB */ + cali_info->default_cck_index = 20; /* -6 dB */ #elif RTL8192E_SUPPORT - p_rf_calibrate_info->default_cck_index = 8; /* -12 dB */ + cali_info->default_cck_index = 8; /* -12 dB */ #endif - p_rf_calibrate_info->bb_swing_idx_ofdm_base = p_rf_calibrate_info->default_ofdm_index; - p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index; - p_dm_odm->rf_calibrate_info.CCK_index = p_rf_calibrate_info->default_cck_index; + cali_info->bb_swing_idx_ofdm_base = cali_info->default_ofdm_index; + cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index; + dm->rf_calibrate_info.CCK_index = cali_info->default_cck_index; for (p = 0; p < MAX_RF_PATH; p++) { - p_dm_odm->rf_calibrate_info.OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index; - p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index; - p_rf_calibrate_info->kfree_offset[p] = 0; /* for 8814 kfree*/ + dm->rf_calibrate_info.OFDM_index[p] = cali_info->default_ofdm_index; + cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index; + cali_info->kfree_offset[p] = 0; /* for 8814 kfree*/ } - p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("p_rf_calibrate_info->default_ofdm_index=%d p_rf_calibrate_info->default_cck_index=%d\n", p_rf_calibrate_info->default_ofdm_index, p_rf_calibrate_info->default_cck_index)); + cali_info->bb_swing_idx_cck = cali_info->default_cck_index; + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "cali_info->default_ofdm_index=%d cali_info->default_cck_index=%d\n", cali_info->default_ofdm_index, cali_info->default_cck_index); + cali_info->tm_trigger = 0; } void odm_txpowertracking_check( - void *p_dm_void + void *dm_void ) { /* */ /* For AP/ADSL use struct rtl8192cd_priv* */ - /* For CE/NIC use struct _ADAPTER* */ + /* For CE/NIC use struct void* */ /* */ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &(dm->rf_table); - if (!(p_rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) return; /* */ @@ -1075,17 +1067,17 @@ odm_txpowertracking_check( /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ /* HW dynamic mechanism. */ /* */ - switch (p_dm_odm->support_platform) { + switch (dm->support_platform) { case ODM_WIN: - odm_txpowertracking_check_mp(p_dm_odm); + odm_txpowertracking_check_mp(dm); break; case ODM_CE: - odm_txpowertracking_check_ce(p_dm_odm); + odm_txpowertracking_check_ce(dm); break; case ODM_AP: - odm_txpowertracking_check_ap(p_dm_odm); + odm_txpowertracking_check_ap(dm); break; } @@ -1093,33 +1085,33 @@ odm_txpowertracking_check( void odm_txpowertracking_check_ce( - void *p_dm_void + void *dm_void ) { #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + struct _hal_rf_ *rf = &(dm->rf_table); #if (RTL8188E_SUPPORT == 1) - /* if(!p_mgnt_info->is_txpowertracking || (!pdmpriv->txpowertrack_control && pdmpriv->is_ap_kdone)) */ + /* if(!mgnt_info->is_txpowertracking || (!pdmpriv->txpowertrack_control && pdmpriv->is_ap_kdone)) */ - if (!(p_rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) return; - if (!p_dm_odm->rf_calibrate_info.tm_trigger) { /* at least delay 1 sec */ - /* p_hal_data->TxPowerCheckCnt++; */ /* cosa add for debug */ - odm_set_rf_reg(p_dm_odm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60); + if (!dm->rf_calibrate_info.tm_trigger) { /* at least delay 1 sec */ + /* hal_data->TxPowerCheckCnt++; */ /* cosa add for debug */ + odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60); /* DBG_8192C("Trigger 92C Thermal Meter!!\n"); */ - p_dm_odm->rf_calibrate_info.tm_trigger = 1; + dm->rf_calibrate_info.tm_trigger = 1; return; } else { /* DBG_8192C("Schedule TxPowerTracking direct call!!\n"); */ odm_txpowertracking_callback_thermal_meter_8188e(adapter); - p_dm_odm->rf_calibrate_info.tm_trigger = 0; + dm->rf_calibrate_info.tm_trigger = 0; } #endif @@ -1128,12 +1120,12 @@ odm_txpowertracking_check_ce( void odm_txpowertracking_check_mp( - void *p_dm_void + void *dm_void ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; if (odm_check_power_status(adapter) == false) return; @@ -1147,16 +1139,16 @@ odm_txpowertracking_check_mp( void odm_txpowertracking_check_ap( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; #if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B)) - odm_txpowertracking_callback_thermal_meter(p_dm_odm); + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8821C)) + odm_txpowertracking_callback_thermal_meter(dm); else #endif { diff --git a/hal/phydm/halrf/halrf_powertracking_ap.h b/hal/phydm/halrf/halrf_powertracking_ap.h index e2324d4..703b876 100644 --- a/hal/phydm/halrf/halrf_powertracking_ap.h +++ b/hal/phydm/halrf/halrf_powertracking_ap.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,18 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PHYDMPOWERTRACKING_H__ #define __PHYDMPOWERTRACKING_H__ -#define HALRF_POWRTRACKING_VER "1.1" - #if (DM_ODM_SUPPORT_TYPE == ODM_AP) #ifdef RTK_AC_SUPPORT #define ODM_IC_11AC_SERIES_SUPPORT 1 @@ -50,8 +43,6 @@ #define IQK_BB_REG_NUM 9 -#define HP_THERMAL_NUM 8 - #define AVG_THERMAL_NUM 8 #define iqk_matrix_reg_num 8 /* #define IQK_MATRIX_SETTINGS_NUM 1+24+21 */ @@ -105,7 +96,7 @@ static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4 #define OFDM_TABLE_SIZE_8812 43 #define AVG_THERMAL_NUM_8812 4 -#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1) +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE]; #elif(ODM_IC_11AC_SERIES_SUPPORT) extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812]; @@ -117,12 +108,12 @@ extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B]; #define dm_check_txpowertracking odm_txpowertracking_check -struct _IQK_MATRIX_REGS_SETTING { +struct iqk_matrix_regs_setting { boolean is_iqk_done; s32 value[1][iqk_matrix_reg_num]; }; -struct odm_rf_calibration_structure { +struct dm_rf_calibration_struct { /* for tx power tracking */ u32 rega24; /* for TempCCK */ @@ -166,9 +157,7 @@ struct odm_rf_calibration_structure { s8 delta_power_index_last; boolean is_tx_power_changed; - u8 thermal_value_hp[HP_THERMAL_NUM]; - u8 thermal_value_hp_index; - struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; + struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; u8 delta_lck; u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; @@ -268,6 +257,7 @@ struct odm_rf_calibration_structure { u64 iqk_start_time; u64 iqk_total_progressing_time; u64 iqk_progressing_time; + u64 lck_progressing_time; u32 lok_result; u8 iqk_step; u8 kcount; @@ -290,34 +280,34 @@ struct odm_rf_calibration_structure { void odm_txpowertracking_check_ap( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_check( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_thermal_meter_init( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_init( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_check_mp( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_check_ce( - void *p_dm_void + void *dm_void ); @@ -325,27 +315,27 @@ odm_txpowertracking_check_ce( void odm_txpowertracking_callback_thermal_meter92c( - struct _ADAPTER *adapter + void *adapter ); void odm_txpowertracking_callback_rx_gain_thermal_meter92d( - struct _ADAPTER *adapter + void *adapter ); void odm_txpowertracking_callback_thermal_meter92d( - struct _ADAPTER *adapter + void *adapter ); void odm_txpowertracking_direct_call92c( - struct _ADAPTER *adapter + void *adapter ); void odm_txpowertracking_thermal_meter_check( - struct _ADAPTER *adapter + void *adapter ); #endif diff --git a/hal/phydm/halrf/halrf_powertracking_ce.c b/hal/phydm/halrf/halrf_powertracking_ce.c index 5bc1b5f..6b8402e 100644 --- a/hal/phydm/halrf/halrf_powertracking_ce.c +++ b/hal/phydm/halrf/halrf_powertracking_ce.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ /*============================================================ */ /* include files */ @@ -467,57 +472,57 @@ u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = { void odm_txpowertracking_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - if (!(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B))) + if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B))) return; #endif - odm_txpowertracking_thermal_meter_init(p_dm_odm); + odm_txpowertracking_thermal_meter_init(dm); } u8 get_swing_index( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); #endif u8 i = 0; u32 bb_swing; u32 swing_table_size; - u32 *p_swing_table; + u32 *swing_table; - if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B - || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B + || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B ) { - bb_swing = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000); + bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000); - p_swing_table = ofdm_swing_table_new; + swing_table = ofdm_swing_table_new; swing_table_size = OFDM_TABLE_SIZE; } else { #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) - if (p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8821) { - bb_swing = phy_get_tx_bb_swing_8812a(adapter, p_hal_data->current_band_type, ODM_RF_PATH_A); - p_swing_table = tx_scaling_table_jaguar; + if (dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8821) { + bb_swing = phy_get_tx_bb_swing_8812a(adapter, hal_data->current_band_type, RF_PATH_A); + swing_table = tx_scaling_table_jaguar; swing_table_size = TXSCALE_TABLE_SIZE; } else #endif { bb_swing = 0; - p_swing_table = ofdm_swing_table; + swing_table = ofdm_swing_table; swing_table_size = OFDM_TABLE_SIZE; } } for (i = 0; i < swing_table_size; ++i) { - u32 table_value = p_swing_table[i]; + u32 table_value = swing_table[i]; if (table_value >= 0x100000) table_value >>= 22; @@ -529,24 +534,24 @@ get_swing_index( u8 get_cck_swing_index( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; u32 bb_cck_swing; - if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B || - p_dm_odm->support_ic_type == ODM_RTL8192E) { - bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22); + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B || + dm->support_ic_type == ODM_RTL8192E) { + bb_cck_swing = odm_read_1byte(dm, 0xa22); for (i = 0; i < CCK_TABLE_SIZE; i++) { if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0]) break; } - } else if (p_dm_odm->support_ic_type == ODM_RTL8703B) { - bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22); + } else if (dm->support_ic_type == ODM_RTL8703B) { + bb_cck_swing = odm_read_1byte(dm, 0xa22); for (i = 0; i < CCK_TABLE_SIZE_88F; i++) { if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0]) @@ -560,123 +565,123 @@ get_cck_swing_index( void odm_txpowertracking_thermal_meter_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 default_swing_index = get_swing_index(p_dm_odm); - u8 default_cck_swing_index = get_cck_swing_index(p_dm_odm); + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 default_swing_index = get_swing_index(dm); + u8 default_cck_swing_index = get_cck_swing_index(dm); u8 p = 0; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - if (*(p_dm_odm->p_mp_mode) == false) - p_hal_data->txpowertrack_control = true; + if (*dm->mp_mode == false) + hal_data->txpowertrack_control = true; #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) #ifdef DM_ODM_CE_MAC80211 - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv); #else - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); #endif - p_rf_calibrate_info->is_txpowertracking = _TRUE; - p_rf_calibrate_info->tx_powercount = 0; - p_rf_calibrate_info->is_txpowertracking_init = _FALSE; + cali_info->is_txpowertracking = true; + cali_info->tx_powercount = 0; + cali_info->is_txpowertracking_init = false; - if (*(p_dm_odm->p_mp_mode) == false) - p_rf_calibrate_info->txpowertrack_control = _TRUE; + if (*dm->mp_mode == false) + cali_info->txpowertrack_control = true; else - p_rf_calibrate_info->txpowertrack_control = _FALSE; + cali_info->txpowertrack_control = false; - if (*(p_dm_odm->p_mp_mode) == false) - p_rf_calibrate_info->txpowertrack_control = _TRUE; + if (*dm->mp_mode == false) + cali_info->txpowertrack_control = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("p_dm_odm txpowertrack_control = %d\n", p_rf_calibrate_info->txpowertrack_control)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "dm txpowertrack_control = %d\n", cali_info->txpowertrack_control); #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) #ifdef RTL8188E_SUPPORT { - p_rf_calibrate_info->is_txpowertracking = _TRUE; - p_rf_calibrate_info->tx_powercount = 0; - p_rf_calibrate_info->is_txpowertracking_init = _FALSE; - p_rf_calibrate_info->txpowertrack_control = _TRUE; + cali_info->is_txpowertracking = true; + cali_info->tx_powercount = 0; + cali_info->is_txpowertracking_init = false; + cali_info->txpowertrack_control = true; } #endif #endif - /* p_dm_odm->rf_calibrate_info.txpowertrack_control = true; */ + /* dm->rf_calibrate_info.txpowertrack_control = true; */ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - p_rf_calibrate_info->thermal_value = rtlefu->eeprom_thermalmeter; - p_rf_calibrate_info->thermal_value_iqk = rtlefu->eeprom_thermalmeter; - p_rf_calibrate_info->thermal_value_lck = rtlefu->eeprom_thermalmeter; + cali_info->thermal_value = rtlefu->eeprom_thermalmeter; + cali_info->thermal_value_iqk = rtlefu->eeprom_thermalmeter; + cali_info->thermal_value_lck = rtlefu->eeprom_thermalmeter; #else - p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter; - p_rf_calibrate_info->thermal_value_iqk = p_hal_data->eeprom_thermal_meter; - p_rf_calibrate_info->thermal_value_lck = p_hal_data->eeprom_thermal_meter; + cali_info->thermal_value = hal_data->eeprom_thermal_meter; + cali_info->thermal_value_iqk = hal_data->eeprom_thermal_meter; + cali_info->thermal_value_lck = hal_data->eeprom_thermal_meter; #endif - if (p_rf_calibrate_info->default_bb_swing_index_flag != true) { + if (cali_info->default_bb_swing_index_flag != true) { /*The index of "0 dB" in SwingTable.*/ - if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B || - p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8703B) { - p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index; - p_rf_calibrate_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index; - } else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ - p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ - p_rf_calibrate_info->default_cck_index = 20; /*CCK:-6dB*/ - } else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ - p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ - p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/ - } else if (p_dm_odm->support_ic_type == ODM_RTL8710B) { /* JJ ADD 20161014 */ - p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ - p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/ + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B || + dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B) { + cali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index; + cali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index; + } else if (dm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ + cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + cali_info->default_cck_index = 20; /*CCK:-6dB*/ + } else if (dm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ + cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + cali_info->default_cck_index = 28; /*CCK: -6dB*/ + } else if (dm->support_ic_type == ODM_RTL8710B) { /* JJ ADD 20161014 */ + cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + cali_info->default_cck_index = 28; /*CCK: -6dB*/ } else { - p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index; - p_rf_calibrate_info->default_cck_index = 24; + cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index; + cali_info->default_cck_index = 24; } - p_rf_calibrate_info->default_bb_swing_index_flag = true; + cali_info->default_bb_swing_index_flag = true; } - p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index; - p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->default_cck_index; + cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index; + cali_info->CCK_index = cali_info->default_cck_index; - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) { - p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index; - p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index; - p_rf_calibrate_info->delta_power_index[p] = 0; - p_rf_calibrate_info->delta_power_index_last[p] = 0; - p_rf_calibrate_info->power_index_offset[p] = 0; + for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) { + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index; + cali_info->OFDM_index[p] = cali_info->default_ofdm_index; + cali_info->delta_power_index[p] = 0; + cali_info->delta_power_index_last[p] = 0; + cali_info->power_index_offset[p] = 0; } - p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; - p_rf_calibrate_info->modify_tx_agc_value_cck = 0; - + cali_info->modify_tx_agc_value_ofdm = 0; + cali_info->modify_tx_agc_value_cck = 0; + cali_info->tm_trigger = 0; } void odm_txpowertracking_check( - void *p_dm_void + void *dm_void ) { /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate at the same time. In the stage2/3, we need to prive universal interface and merge all HW dynamic mechanism. */ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - switch (p_dm_odm->support_platform) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + switch (dm->support_platform) { case ODM_WIN: - odm_txpowertracking_check_mp(p_dm_odm); + odm_txpowertracking_check_mp(dm); break; case ODM_CE: - odm_txpowertracking_check_ce(p_dm_odm); + odm_txpowertracking_check_ce(dm); break; case ODM_AP: - odm_txpowertracking_check_ap(p_dm_odm); + odm_txpowertracking_check_ap(dm); break; default: @@ -687,41 +692,35 @@ odm_txpowertracking_check( void odm_txpowertracking_check_ce( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; - if (!(p_rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) return; - if (!p_dm_odm->rf_calibrate_info.tm_trigger) { - + if (!dm->rf_calibrate_info.tm_trigger) { if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8703B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8822B(adapter) - || IS_HARDWARE_TYPE_8821C(adapter) || (p_dm_odm->support_ic_type == ODM_RTL8710B) + || IS_HARDWARE_TYPE_8821C(adapter) || (dm->support_ic_type == ODM_RTL8710B) )/* JJ ADD 20161014 */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03); + odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03); else - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60); + odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60); - p_dm_odm->rf_calibrate_info.tm_trigger = 1; + dm->rf_calibrate_info.tm_trigger = 1; return; } else { - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - odm_txpowertracking_callback_thermal_meter(p_dm_odm); -#else - odm_txpowertracking_callback_thermal_meter(adapter); -#endif - p_dm_odm->rf_calibrate_info.tm_trigger = 0; + odm_txpowertracking_callback_thermal_meter(dm); + dm->rf_calibrate_info.tm_trigger = 0; } #endif @@ -729,15 +728,15 @@ odm_txpowertracking_check_ce( void odm_txpowertracking_check_mp( - void *p_dm_void + void *dm_void ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; if (odm_check_power_status(adapter) == false) { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>odm_check_power_status() return false\n")); + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status, return false\n")); return; } @@ -749,12 +748,12 @@ odm_txpowertracking_check_mp( void odm_txpowertracking_check_ap( - void *p_dm_void + void *dm_void ) { #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rtl8192cd_priv *priv = dm->priv; return; diff --git a/hal/phydm/halrf/halrf_powertracking_ce.h b/hal/phydm/halrf/halrf_powertracking_ce.h index c3d4fe0..1fef265 100644 --- a/hal/phydm/halrf/halrf_powertracking_ce.h +++ b/hal/phydm/halrf/halrf_powertracking_ce.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,21 +8,24 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #ifndef __PHYDMPOWERTRACKING_H__ #define __PHYDMPOWERTRACKING_H__ -#define HALRF_POWRTRACKING_VER "1.1" - #define DPK_DELTA_MAPPING_NUM 13 #define index_mapping_HP_NUM 15 #define OFDM_TABLE_SIZE 43 @@ -39,7 +42,6 @@ #define BAND_NUM 4 #define AVG_THERMAL_NUM 8 -#define HP_THERMAL_NUM 8 #define IQK_MAC_REG_NUM 4 #define IQK_ADDA_REG_NUM 16 #define IQK_BB_REG_NUM_MAX 10 @@ -79,13 +81,13 @@ static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4 #define dm_check_txpowertracking odm_txpowertracking_check -struct _IQK_MATRIX_REGS_SETTING { +struct iqk_matrix_regs_setting { boolean is_iqk_done; s32 value[3][iqk_matrix_reg_num]; boolean is_bw_iqk_result_saved[3]; }; -struct odm_rf_calibration_structure { +struct dm_rf_calibration_struct { /* for tx power tracking */ u32 rega24; /* for TempCCK */ @@ -131,9 +133,7 @@ struct odm_rf_calibration_structure { s8 xtal_offset; s8 xtal_offset_last; - u8 thermal_value_hp[HP_THERMAL_NUM]; - u8 thermal_value_hp_index; - struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; + struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; u8 delta_lck; s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */ u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; @@ -250,6 +250,7 @@ struct odm_rf_calibration_structure { u64 iqk_start_time; u64 iqk_progressing_time; u64 iqk_total_progressing_time; + u64 lck_progressing_time; u32 lok_result; @@ -280,66 +281,66 @@ struct odm_rf_calibration_structure { void odm_txpowertracking_check( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_init( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_check_ap( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_thermal_meter_init( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_init( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_check_mp( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_check_ce( - void *p_dm_void + void *dm_void ); #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) void odm_txpowertracking_callback_thermal_meter92c( - struct _ADAPTER *adapter + void *adapter ); void odm_txpowertracking_callback_rx_gain_thermal_meter92d( - struct _ADAPTER *adapter + void *adapter ); void odm_txpowertracking_callback_thermal_meter92d( - struct _ADAPTER *adapter + void *adapter ); void odm_txpowertracking_direct_call92c( - struct _ADAPTER *adapter + void *adapter ); void odm_txpowertracking_thermal_meter_check( - struct _ADAPTER *adapter + void *adapter ); #endif diff --git a/hal/phydm/halrf/halrf_powertracking_win.c b/hal/phydm/halrf/halrf_powertracking_win.c index ba11f51..5705259 100644 --- a/hal/phydm/halrf/halrf_powertracking_win.c +++ b/hal/phydm/halrf/halrf_powertracking_win.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /*============================================================ */ /* include files */ @@ -467,45 +462,45 @@ u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = { void odm_txpowertracking_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - if (!(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B))) + if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B))) return; #endif - odm_txpowertracking_thermal_meter_init(p_dm_odm); + odm_txpowertracking_thermal_meter_init(dm); } u8 get_swing_index( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); u8 i = 0; u32 bb_swing; u32 swing_table_size; - u32 *p_swing_table; + u32 *swing_table; - if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B || - p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B) { - bb_swing = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000); + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B || + dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B) { + bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000); - p_swing_table = ofdm_swing_table_new; + swing_table = ofdm_swing_table_new; swing_table_size = OFDM_TABLE_SIZE; } else { - bb_swing = PHY_GetTxBBSwing_8812A(adapter, p_hal_data->CurrentBandType, ODM_RF_PATH_A); - p_swing_table = tx_scaling_table_jaguar; + bb_swing = PHY_GetTxBBSwing_8812A((PADAPTER)adapter, hal_data->CurrentBandType, RF_PATH_A); + swing_table = tx_scaling_table_jaguar; swing_table_size = TXSCALE_TABLE_SIZE; } for (i = 0; i < swing_table_size; ++i) { - u32 table_value = p_swing_table[i]; + u32 table_value = swing_table[i]; if (table_value >= 0x100000) table_value >>= 22; @@ -517,24 +512,24 @@ get_swing_index( u8 get_cck_swing_index( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; u32 bb_cck_swing; - if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B || - p_dm_odm->support_ic_type == ODM_RTL8192E) { - bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22); + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B || + dm->support_ic_type == ODM_RTL8192E) { + bb_cck_swing = odm_read_1byte(dm, 0xa22); for (i = 0; i < CCK_TABLE_SIZE; i++) { if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0]) break; } - } else if (p_dm_odm->support_ic_type == ODM_RTL8703B) { - bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22); + } else if (dm->support_ic_type == ODM_RTL8703B) { + bb_cck_swing = odm_read_1byte(dm, 0xa22); for (i = 0; i < CCK_TABLE_SIZE_88F; i++) { if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0]) @@ -548,45 +543,45 @@ get_cck_swing_index( void odm_txpowertracking_thermal_meter_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 default_swing_index = get_swing_index(p_dm_odm); - u8 default_cck_swing_index = get_cck_swing_index(p_dm_odm); - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 default_swing_index = get_swing_index(dm); + u8 default_cck_swing_index = get_cck_swing_index(dm); + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); u8 p = 0; - if (*(p_dm_odm->p_mp_mode) == false) - p_rf_calibrate_info->txpowertrack_control = true; + if (*(dm->mp_mode) == false) + cali_info->txpowertrack_control = true; #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) #ifdef CONFIG_RTL8188E { - p_rf_calibrate_info->is_txpowertracking = _TRUE; - p_rf_calibrate_info->tx_powercount = 0; - p_rf_calibrate_info->is_txpowertracking_init = _FALSE; + cali_info->is_txpowertracking = true; + cali_info->tx_powercount = 0; + cali_info->is_txpowertracking_init = false; - if (*(p_dm_odm->p_mp_mode) == false) - p_rf_calibrate_info->txpowertrack_control = _TRUE; + if (*(dm->mp_mode) == false) + cali_info->txpowertrack_control = true; - MSG_8192C("p_dm_odm txpowertrack_control = %d\n", p_rf_calibrate_info->txpowertrack_control); + MSG_8192C("dm txpowertrack_control = %d\n", cali_info->txpowertrack_control); } #else { - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct dm_priv *pdmpriv = &p_hal_data->dmpriv; + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_priv *pdmpriv = &hal_data->dmpriv; - pdmpriv->is_txpowertracking = _TRUE; + pdmpriv->is_txpowertracking = true; pdmpriv->tx_powercount = 0; - pdmpriv->is_txpowertracking_init = _FALSE; + pdmpriv->is_txpowertracking_init = false; - if (*(p_dm_odm->p_mp_mode) == false) - pdmpriv->txpowertrack_control = _TRUE; + if (*(dm->mp_mode) == false) + pdmpriv->txpowertrack_control = true; MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control); @@ -595,71 +590,71 @@ odm_txpowertracking_thermal_meter_init( #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) #ifdef RTL8188E_SUPPORT { - p_rf_calibrate_info->is_txpowertracking = _TRUE; - p_rf_calibrate_info->tx_powercount = 0; - p_rf_calibrate_info->is_txpowertracking_init = _FALSE; - p_rf_calibrate_info->txpowertrack_control = _TRUE; + cali_info->is_txpowertracking = true; + cali_info->tx_powercount = 0; + cali_info->is_txpowertracking_init = false; + cali_info->txpowertrack_control = true; } #endif #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #if (MP_DRIVER == 1) - p_rf_calibrate_info->txpowertrack_control = false; + cali_info->txpowertrack_control = false; #else - p_rf_calibrate_info->txpowertrack_control = true; + cali_info->txpowertrack_control = true; #endif #else - p_rf_calibrate_info->txpowertrack_control = true; + cali_info->txpowertrack_control = true; #endif - p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter; - p_rf_calibrate_info->thermal_value_iqk = p_hal_data->eeprom_thermal_meter; - p_rf_calibrate_info->thermal_value_lck = p_hal_data->eeprom_thermal_meter; + cali_info->thermal_value = hal_data->eeprom_thermal_meter; + cali_info->thermal_value_iqk = hal_data->eeprom_thermal_meter; + cali_info->thermal_value_lck = hal_data->eeprom_thermal_meter; - if (p_rf_calibrate_info->default_bb_swing_index_flag != true) { + if (cali_info->default_bb_swing_index_flag != true) { /*The index of "0 dB" in SwingTable.*/ - if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B || - p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8703B) { - p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index; - p_rf_calibrate_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index; - } else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ - p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ - p_rf_calibrate_info->default_cck_index = 20; /*CCK:-6dB*/ - } else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ - p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ - p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/ + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B || + dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B) { + cali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index; + cali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index; + } else if (dm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ + cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + cali_info->default_cck_index = 20; /*CCK:-6dB*/ + } else if (dm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ + cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + cali_info->default_cck_index = 28; /*CCK: -6dB*/ /* JJ ADD 20161014 */ - } else if (p_dm_odm->support_ic_type == ODM_RTL8710B) { - p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ - p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/ + } else if (dm->support_ic_type == ODM_RTL8710B) { + cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + cali_info->default_cck_index = 28; /*CCK: -6dB*/ } else { - p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index; - p_rf_calibrate_info->default_cck_index = 24; + cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index; + cali_info->default_cck_index = 24; } - p_rf_calibrate_info->default_bb_swing_index_flag = true; + cali_info->default_bb_swing_index_flag = true; } - p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index; - p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->default_cck_index; + cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index; + cali_info->CCK_index = cali_info->default_cck_index; - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) { - p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index; - p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index; - p_rf_calibrate_info->delta_power_index[p] = 0; - p_rf_calibrate_info->delta_power_index_last[p] = 0; - p_rf_calibrate_info->power_index_offset[p] = 0; - p_rf_calibrate_info->kfree_offset[p] = 0; + for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) { + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index; + cali_info->OFDM_index[p] = cali_info->default_ofdm_index; + cali_info->delta_power_index[p] = 0; + cali_info->delta_power_index_last[p] = 0; + cali_info->power_index_offset[p] = 0; + cali_info->kfree_offset[p] = 0; } - p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; - p_rf_calibrate_info->modify_tx_agc_value_cck = 0; - + cali_info->modify_tx_agc_value_ofdm = 0; + cali_info->modify_tx_agc_value_cck = 0; + cali_info->tm_trigger = 0; } void odm_txpowertracking_check( - void *p_dm_void + void *dm_void ) { @@ -669,18 +664,18 @@ odm_txpowertracking_check( /* HW dynamic mechanism. */ #endif - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - switch (p_dm_odm->support_platform) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + switch (dm->support_platform) { case ODM_WIN: - odm_txpowertracking_check_mp(p_dm_odm); + odm_txpowertracking_check_mp(dm); break; case ODM_CE: - odm_txpowertracking_check_ce(p_dm_odm); + odm_txpowertracking_check_ce(dm); break; case ODM_AP: - odm_txpowertracking_check_ap(p_dm_odm); + odm_txpowertracking_check_ap(dm); break; default: @@ -691,33 +686,33 @@ odm_txpowertracking_check( void odm_txpowertracking_check_ce( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &(dm->rf_table); #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; #if ((RTL8188F_SUPPORT == 1)) rtl8192c_odm_check_txpowertracking(adapter); #endif #if (RTL8188E_SUPPORT == 1) - if (!(p_rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) return; - if (!p_rf_calibrate_info->tm_trigger) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60); + if (!cali_info->tm_trigger) { + odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60); /*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/ - p_rf_calibrate_info->tm_trigger = 1; + cali_info->tm_trigger = 1; return; } else { /*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/ odm_txpowertracking_callback_thermal_meter_8188e(adapter); - p_rf_calibrate_info->tm_trigger = 0; + cali_info->tm_trigger = 0; } #endif #endif @@ -725,18 +720,18 @@ odm_txpowertracking_check_ce( void odm_txpowertracking_check_mp( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; - if (*p_dm_odm->p_is_fcs_mode_enable) + if (*dm->is_fcs_mode_enable) return; - if (odm_check_power_status(adapter) == false) { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>odm_check_power_status() return false\n")); + if (odm_check_power_status(dm) == false) { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status return false\n")); return; } @@ -753,7 +748,7 @@ odm_txpowertracking_check_mp( void odm_txpowertracking_check_ap( - void *p_dm_void + void *dm_void ) { return; @@ -764,28 +759,28 @@ odm_txpowertracking_check_ap( void odm_txpowertracking_direct_call( - struct _ADAPTER *adapter + void *adapter ) { - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; odm_txpowertracking_callback_thermal_meter(adapter); } void odm_txpowertracking_thermal_meter_check( - struct _ADAPTER *adapter + void *adapter ) { static u8 tm_trigger = 0; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &(pHalData->DM_OutSrc); - struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &(pHalData->DM_OutSrc); + struct _hal_rf_ *rf = &(dm->rf_table); - if (!(p_rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) { + if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) { RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, - ("===>odm_txpowertracking_thermal_meter_check(),p_mgnt_info->is_txpowertracking is false, return!!\n")); + ("===>odm_txpowertracking_thermal_meter_check(),mgnt_info->is_txpowertracking is false, return!!\n")); return; } @@ -793,9 +788,9 @@ odm_txpowertracking_thermal_meter_check( if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter) || IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter))/* JJ ADD 20161014 */ - PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03); + PHY_SetRFReg((PADAPTER)adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03); else - PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60); + PHY_SetRFReg((PADAPTER)adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60); RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n")); diff --git a/hal/phydm/halrf/halrf_powertracking_win.h b/hal/phydm/halrf/halrf_powertracking_win.h index 88356c4..19b27c0 100644 --- a/hal/phydm/halrf/halrf_powertracking_win.h +++ b/hal/phydm/halrf/halrf_powertracking_win.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,18 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PHYDMPOWERTRACKING_H__ #define __PHYDMPOWERTRACKING_H__ -#define HALRF_POWRTRACKING_VER "1.1" - #define DPK_DELTA_MAPPING_NUM 13 #define index_mapping_HP_NUM 15 #define TXSCALE_TABLE_SIZE 37 @@ -43,7 +36,6 @@ #define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */ #define AVG_THERMAL_NUM 8 -#define HP_THERMAL_NUM 8 #define iqk_matrix_reg_num 8 #define IQK_MAC_REG_NUM 4 #define IQK_ADDA_REG_NUM 16 @@ -73,33 +65,33 @@ static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4 void odm_txpowertracking_check( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_check_ap( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_thermal_meter_init( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_init( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_check_mp( - void *p_dm_void + void *dm_void ); void odm_txpowertracking_check_ce( - void *p_dm_void + void *dm_void ); #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) @@ -107,18 +99,18 @@ odm_txpowertracking_check_ce( void odm_txpowertracking_thermal_meter_check( - struct _ADAPTER *adapter + void *adapter ); #endif -struct _IQK_MATRIX_REGS_SETTING { +struct iqk_matrix_regs_setting { boolean is_iqk_done; s32 value[3][iqk_matrix_reg_num]; boolean is_bw_iqk_result_saved[3]; }; -struct odm_rf_calibration_structure { +struct dm_rf_calibration_struct { /* for tx power tracking */ u32 rega24; /* for TempCCK */ @@ -161,9 +153,7 @@ struct odm_rf_calibration_structure { s8 xtal_offset; s8 xtal_offset_last; - u8 thermal_value_hp[HP_THERMAL_NUM]; - u8 thermal_value_hp_index; - struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; + struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; u8 delta_lck; s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */ u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; @@ -272,6 +262,7 @@ struct odm_rf_calibration_structure { u64 iqk_start_time; u64 iqk_total_progressing_time; u64 iqk_progressing_time; + u64 lck_progressing_time; u32 lok_result; u8 iqk_step; u8 kcount; @@ -300,8 +291,6 @@ struct odm_rf_calibration_structure { /*Add by Yuchen for Kfree Phydm*/ u8 reg_rf_kfree_enable; /*for registry*/ u8 rf_kfree_enable; /*for efuse enable check*/ - - HALMAC_PWR_TRACKING_OPTION HALMAC_PWR_TRACKING_INFO; }; diff --git a/hal/phydm/halrf/rtl8822b/halrf_8822b.c b/hal/phydm/halrf/rtl8822b/halrf_8822b.c index d22e88c..eb28312 100644 --- a/hal/phydm/halrf/rtl8822b/halrf_8822b.c +++ b/hal/phydm/halrf/rtl8822b/halrf_8822b.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,64 +8,98 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #include "mp_precomp.h" #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#include "../phydm_precomp.h" + #if RT_PLATFORM==PLATFORM_MACOSX + #include "phydm_precomp.h" + #else + #include "../phydm_precomp.h" + #endif #else #include "../../phydm_precomp.h" #endif #if (RTL8822B_SUPPORT == 1) +void +halrf_rf_lna_setting_8822b( + struct dm_struct *dm_void, + enum phydm_lna_set type +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 path = 0x0; + + for (path = 0x0; path < 2; path++) + if (type == phydm_lna_disable) { + /*S0*/ + odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, 0x33, RFREGOFFSETMASK, 0x00003); + odm_set_rf_reg(dm, (enum rf_path)path, 0x3e, RFREGOFFSETMASK, 0x00064); + odm_set_rf_reg(dm, (enum rf_path)path, 0x3f, RFREGOFFSETMASK, 0x0afce); + odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x0); + } else if (type == phydm_lna_enable) { + /*S0*/ + odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, 0x33, RFREGOFFSETMASK, 0x00003); + odm_set_rf_reg(dm, (enum rf_path)path, 0x3e, RFREGOFFSETMASK, 0x00064); + odm_set_rf_reg(dm, (enum rf_path)path, 0x3f, RFREGOFFSETMASK, 0x1afce); + odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x0); + } +} boolean get_mix_mode_tx_agc_bb_swing_offset_8822b( - void *p_dm_void, + void *dm_void, enum pwrtrack_method method, u8 rf_path, u8 tx_power_index_offest ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - u8 bb_swing_upper_bound = p_rf_calibrate_info->default_ofdm_index + 10; + u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10; u8 bb_swing_lower_bound = 0; s8 tx_agc_index = 0; - u8 tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index; + u8 tx_bb_swing_index = cali_info->default_ofdm_index; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Path_%d p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest=%d\n", - rf_path, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], tx_power_index_offest)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest=%d\n", + rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], tx_power_index_offest); if (tx_power_index_offest > 0XF) tx_power_index_offest = 0XF; - if (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] >= 0 && p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest) { - tx_agc_index = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]; - tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index; - } else if (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest) { + if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 && cali_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest) { + tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path]; + tx_bb_swing_index = cali_info->default_ofdm_index; + } else if (cali_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest) { tx_agc_index = tx_power_index_offest; - p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest; - tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index + p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path]; + cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest; + tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->remnant_ofdm_swing_idx[rf_path]; if (tx_bb_swing_index > bb_swing_upper_bound) tx_bb_swing_index = bb_swing_upper_bound; } else { tx_agc_index = 0; - if (p_rf_calibrate_info->default_ofdm_index > (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] * (-1))) - tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]; + if (cali_info->default_ofdm_index > (cali_info->absolute_ofdm_swing_idx[rf_path] * (-1))) + tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path]; else tx_bb_swing_index = bb_swing_lower_bound; @@ -73,12 +107,11 @@ get_mix_mode_tx_agc_bb_swing_offset_8822b( tx_bb_swing_index = bb_swing_lower_bound; } - p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index; - p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index; + cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index; + cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("MixMode Offset Path_%d p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]=%d p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]=%d tx_power_index_offest=%d\n", - rf_path, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path], tx_power_index_offest)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"MixMode Offset Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d cali_info->bb_swing_idx_ofdm[rf_path]=%d tx_power_index_offest=%d\n", + rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path], tx_power_index_offest); return true; } @@ -86,27 +119,26 @@ get_mix_mode_tx_agc_bb_swing_offset_8822b( void odm_tx_pwr_track_set_pwr8822b( - void *p_dm_void, + void *dm_void, enum pwrtrack_method method, u8 rf_path, u8 channel_mapped_index ) { - #if 0 - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); - u8 channel = *p_dm_odm->p_channel; - u8 band_width = p_hal_data->current_channel_bw; + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + u8 channel = *dm->channel; + u8 band_width = hal_data->current_channel_bw; u8 tx_power_index = 0; u8 tx_rate = 0xFF; enum rt_status status = RT_STATUS_SUCCESS; - PHALMAC_PWR_TRACKING_OPTION p_pwr_tracking_opt = &(p_rf_calibrate_info->HALMAC_PWR_TRACKING_INFO); + PHALMAC_PWR_TRACKING_OPTION p_pwr_tracking_opt = &(cali_info->HALMAC_PWR_TRACKING_INFO); - if (*(p_dm_odm->p_mp_mode) == true) { + if (*(dm->mp_mode) == true) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) #if (MP_DRIVER == 1) @@ -121,31 +153,31 @@ odm_tx_pwr_track_set_pwr8822b( #endif #endif } else { - u16 rate = *(p_dm_odm->p_forced_data_rate); + u16 rate = *(dm->forced_data_rate); if (!rate) { /*auto rate*/ #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate); + tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (p_dm_odm->number_linked_client != 0) - tx_rate = hw_rate_to_m_rate(p_dm_odm->tx_rate); + if (dm->number_linked_client != 0) + tx_rate = hw_rate_to_m_rate(dm->tx_rate); #endif } else /*force rate*/ tx_rate = (u8) rate; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s tx_rate=0x%X\n", __func__, tx_rate)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate); - tx_power_index = phy_get_tx_power_index(adapter, (enum odm_rf_radio_path_e) rf_path, tx_rate, band_width, channel); + tx_power_index = phy_get_tx_power_index(adapter, (enum rf_path) rf_path, tx_rate, band_width, channel); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("type=%d tx_power_index=%d p_rf_calibrate_info->absolute_ofdm_swing_idx=%d p_rf_calibrate_info->default_ofdm_index=%d rf_path=%d\n", method, tx_power_index, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], p_rf_calibrate_info->default_ofdm_index, rf_path)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "type=%d tx_power_index=%d cali_info->absolute_ofdm_swing_idx=%d cali_info->default_ofdm_index=%d rf_path=%d\n", method, tx_power_index, cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->default_ofdm_index, rf_path); p_pwr_tracking_opt->type = method; - p_pwr_tracking_opt->bbswing_index = p_rf_calibrate_info->default_ofdm_index; + p_pwr_tracking_opt->bbswing_index = cali_info->default_ofdm_index; p_pwr_tracking_opt->pwr_tracking_para[rf_path].enable = 1; p_pwr_tracking_opt->pwr_tracking_para[rf_path].tx_pwr_index = tx_power_index; - p_pwr_tracking_opt->pwr_tracking_para[rf_path].pwr_tracking_offset_value = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]; + p_pwr_tracking_opt->pwr_tracking_para[rf_path].pwr_tracking_offset_value = cali_info->absolute_ofdm_swing_idx[rf_path]; p_pwr_tracking_opt->pwr_tracking_para[rf_path].tssi_value = 0; @@ -153,98 +185,92 @@ odm_tx_pwr_track_set_pwr8822b( status = hal_mac_send_power_tracking_info(&GET_HAL_MAC_INFO(adapter), p_pwr_tracking_opt); if (status == RT_STATUS_SUCCESS) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("path A 0xC94=0x%X 0xC1C=0x%X\n", - odm_get_bb_reg(p_dm_odm, 0xC94, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), - odm_get_bb_reg(p_dm_odm, 0xC1C, 0xFFE00000) - )); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("path B 0xE94=0x%X 0xE1C=0x%X\n", - odm_get_bb_reg(p_dm_odm, 0xE94, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), - odm_get_bb_reg(p_dm_odm, 0xE1C, 0xFFE00000) - )); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "path A 0xC94=0x%X 0xC1C=0x%X\n", + odm_get_bb_reg(dm, 0xC94, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), + odm_get_bb_reg(dm, 0xC1C, 0xFFE00000) + ); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "path B 0xE94=0x%X 0xE1C=0x%X\n", + odm_get_bb_reg(dm, 0xE94, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), + odm_get_bb_reg(dm, 0xE1C, 0xFFE00000) + ); } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Power Tracking to FW Fail ret code = %d\n", status)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, + "Power Tracking to FW Fail ret code = %d\n", status); } } #endif - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + struct _hal_rf_ *rf = &dm->rf_table; u8 tx_power_index_offest = 0; u8 tx_power_index = 0; - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; - struct rtl_phy *rtlphy = &(rtlpriv->phy); + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + struct rtl_phy *rtlphy = &rtlpriv->phy; u8 channel = rtlphy->current_channel; u8 band_width = rtlphy->current_chan_bw; #else - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - u8 channel = *p_dm_odm->p_channel; - u8 band_width = *p_dm_odm->p_band_width; + struct _ADAPTER *adapter = (PADAPTER)dm->adapter; + u8 channel = *dm->channel; + u8 band_width = *dm->band_width; #endif u8 tx_rate = 0xFF; - if (*(p_dm_odm->p_mp_mode) == true) { + if (*dm->mp_mode == true) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) #if (MP_DRIVER == 1) - PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx); + PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx; tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex); #endif #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) -#if (MP_DRIVER == 1) - PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx); +#ifdef CONFIG_MP_INCLUDED + PMPT_CONTEXT p_mpt_ctx = &adapter->mppriv.mpt_ctx; tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index); #endif #endif #endif } else { - u16 rate = *(p_dm_odm->p_forced_data_rate); + u16 rate = *dm->forced_data_rate; if (!rate) { /*auto rate*/ #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate); + tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - tx_rate = p_dm_odm->tx_rate; + tx_rate = dm->tx_rate; #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (p_dm_odm->number_linked_client != 0) - tx_rate = hw_rate_to_m_rate(p_dm_odm->tx_rate); + if (dm->number_linked_client != 0) + tx_rate = hw_rate_to_m_rate(dm->tx_rate); + else + tx_rate = rf->p_rate_index; #endif } else /*force rate*/ tx_rate = (u8) rate; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s tx_rate=0x%X\n", __func__, tx_rate)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate); #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n", p_rf_calibrate_info->default_ofdm_index, p_rf_calibrate_info->default_cck_index)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n", cali_info->default_ofdm_index, cali_info->default_cck_index); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRF->absolute_ofdm_swing_idx=%d pRF->remnant_ofdm_swing_idx=%d pRF->absolute_cck_swing_idx=%d pRF->remnant_cck_swing_idx=%d rf_path=%d\n", - p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path], p_rf_calibrate_info->absolute_cck_swing_idx[rf_path], p_rf_calibrate_info->remnant_cck_swing_idx, rf_path)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"pRF->absolute_ofdm_swing_idx=%d pRF->remnant_ofdm_swing_idx=%d pRF->absolute_cck_swing_idx=%d pRF->remnant_cck_swing_idx=%d rf_path=%d\n", + cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->remnant_ofdm_swing_idx[rf_path], cali_info->absolute_cck_swing_idx[rf_path], cali_info->remnant_cck_swing_idx, rf_path); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - tx_power_index = odm_get_tx_power_index(p_dm_odm, (enum odm_rf_radio_path_e) rf_path, tx_rate, (CHANNEL_WIDTH)band_width, channel); + tx_power_index = odm_get_tx_power_index(dm, (enum rf_path) rf_path, tx_rate, (enum channel_width)band_width, channel); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (*(p_dm_odm->p_mp_mode) == true) - tx_power_index = odm_get_tx_power_index(p_dm_odm, (enum odm_rf_radio_path_e) rf_path, tx_rate, (CHANNEL_WIDTH)band_width, channel); - else { - if (p_dm_odm->number_linked_client != 0) - tx_power_index = odm_get_tx_power_index(p_dm_odm, (enum odm_rf_radio_path_e) rf_path, tx_rate, (CHANNEL_WIDTH)band_width, channel); - } + tx_power_index = odm_get_tx_power_index(dm, (enum rf_path) rf_path, tx_rate, band_width, channel); #else - tx_power_index = config_phydm_read_txagc_8822b(p_dm_odm, rf_path, 0x04); /*0x04(TX_AGC_OFDM_6M)*/ + tx_power_index = config_phydm_read_txagc_8822b(dm, rf_path, 0x04); /*0x04(TX_AGC_OFDM_6M)*/ #endif if (tx_power_index >= 63) @@ -252,18 +278,17 @@ odm_tx_pwr_track_set_pwr8822b( tx_power_index_offest = 63 - tx_power_index; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("tx_power_index=%d tx_power_index_offest=%d rf_path=%d\n", tx_power_index, tx_power_index_offest, rf_path)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"tx_power_index=%d tx_power_index_offest=%d rf_path=%d\n", tx_power_index, tx_power_index_offest, rf_path); if (method == BBSWING) { /*use for mp driver clean power tracking status*/ switch (rf_path) { - case ODM_RF_PATH_A: - odm_set_bb_reg(p_dm_odm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]); - odm_set_bb_reg(p_dm_odm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]]); + case RF_PATH_A: + odm_set_bb_reg(dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]); + odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); break; - case ODM_RF_PATH_B: - odm_set_bb_reg(p_dm_odm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]); - odm_set_bb_reg(p_dm_odm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]]); + case RF_PATH_B: + odm_set_bb_reg(dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]); + odm_set_bb_reg(dm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); break; default: @@ -271,28 +296,26 @@ odm_tx_pwr_track_set_pwr8822b( } } else if (method == MIX_MODE) { switch (rf_path) { - case ODM_RF_PATH_A: - get_mix_mode_tx_agc_bb_swing_offset_8822b(p_dm_odm, method, rf_path, tx_power_index_offest); - odm_set_bb_reg(p_dm_odm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]); - odm_set_bb_reg(p_dm_odm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]]); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n", - odm_get_bb_reg(p_dm_odm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))), - odm_get_bb_reg(p_dm_odm, 0xc1c, 0xFFE00000), - p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path], rf_path)); + case RF_PATH_A: + get_mix_mode_tx_agc_bb_swing_offset_8822b(dm, method, rf_path, tx_power_index_offest); + odm_set_bb_reg(dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]); + odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); + + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n", + odm_get_bb_reg(dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))), + odm_get_bb_reg(dm, 0xc1c, 0xFFE00000), + cali_info->bb_swing_idx_ofdm[rf_path], rf_path); break; - case ODM_RF_PATH_B: - get_mix_mode_tx_agc_bb_swing_offset_8822b(p_dm_odm, method, rf_path, tx_power_index_offest); - odm_set_bb_reg(p_dm_odm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]); - odm_set_bb_reg(p_dm_odm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]]); + case RF_PATH_B: + get_mix_mode_tx_agc_bb_swing_offset_8822b(dm, method, rf_path, tx_power_index_offest); + odm_set_bb_reg(dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]); + odm_set_bb_reg(dm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC(0xE94)=0x%x BBSwing(0xe1c)=0x%x BBSwingIndex=%d rf_path=%d\n", - odm_get_bb_reg(p_dm_odm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))), - odm_get_bb_reg(p_dm_odm, 0xe1c, 0xFFE00000), - p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path], rf_path)); + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TXAGC(0xE94)=0x%x BBSwing(0xe1c)=0x%x BBSwingIndex=%d rf_path=%d\n", + odm_get_bb_reg(dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))), + odm_get_bb_reg(dm, 0xe1c, 0xFFE00000), + cali_info->bb_swing_idx_ofdm[rf_path], rf_path); break; default: @@ -304,7 +327,7 @@ odm_tx_pwr_track_set_pwr8822b( void get_delta_swing_table_8822b( - void *p_dm_void, + void *dm_void, #if (DM_ODM_SUPPORT_TYPE & ODM_AP) u8 **temperature_up_a, u8 **temperature_down_a, @@ -322,240 +345,185 @@ get_delta_swing_table_8822b( #endif ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - u8 channel = *(p_dm_odm->p_channel); + u8 channel = *(dm->channel); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; struct rtl_phy *rtlphy = &(rtlpriv->phy); u8 channel = rtlphy->current_channel; #else - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - u8 channel = *p_dm_odm->p_channel; + void *adapter = dm->adapter; + u8 channel = *dm->channel; #endif #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - *temperature_up_cck_a = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p; - *temperature_down_cck_a = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n; - *temperature_up_cck_b = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p; - *temperature_down_cck_b = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n; + *temperature_up_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_p; + *temperature_down_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_n; + *temperature_up_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_p; + *temperature_down_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_n; #endif - *temperature_up_a = p_rf_calibrate_info->delta_swing_table_idx_2ga_p; - *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_2ga_n; - *temperature_up_b = p_rf_calibrate_info->delta_swing_table_idx_2gb_p; - *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_2gb_n; + *temperature_up_a = cali_info->delta_swing_table_idx_2ga_p; + *temperature_down_a = cali_info->delta_swing_table_idx_2ga_n; + *temperature_up_b = cali_info->delta_swing_table_idx_2gb_p; + *temperature_down_b = cali_info->delta_swing_table_idx_2gb_n; if (36 <= channel && channel <= 64) { - *temperature_up_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[0]; - *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[0]; - *temperature_up_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[0]; - *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[0]; + *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0]; + *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0]; + *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0]; + *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0]; } else if (100 <= channel && channel <= 144) { - *temperature_up_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[1]; - *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[1]; - *temperature_up_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[1]; - *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[1]; + *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1]; + *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1]; + *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1]; + *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1]; } else if (149 <= channel && channel <= 177) { - *temperature_up_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[2]; - *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[2]; - *temperature_up_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[2]; - *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[2]; + *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2]; + *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2]; + *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2]; + *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2]; } } void _phy_lc_calibrate_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 lc_cal = 0, cnt = 0,tmp0xc00, tmp0xe00; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK start!!!!!!!\n")); - tmp0xc00 = odm_read_4byte(p_dm_odm, 0xc00); - tmp0xe00 = odm_read_4byte(p_dm_odm, 0xe00); - odm_write_4byte(p_dm_odm, 0xc00, 0x4); - odm_write_4byte(p_dm_odm, 0xe00, 0x4); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, bRFRegOffsetMask, 0x10000); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0, bRFRegOffsetMask, 0x10000); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[LCK]LCK start!!!!!!!\n"); + tmp0xc00 = odm_read_4byte(dm, 0xc00); + tmp0xe00 = odm_read_4byte(dm, 0xe00); + odm_write_4byte(dm, 0xc00, 0x4); + odm_write_4byte(dm, 0xe00, 0x4); + odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000); + odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000); /*backup RF0x18*/ - lc_cal = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK); + lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK); /*disable RTK*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xc4, RFREGOFFSETMASK, 0x01402); + odm_set_rf_reg(dm, RF_PATH_A, 0xc4, RFREGOFFSETMASK, 0x01402); /*Start LCK*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000); + odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000); ODM_delay_ms(100); for (cnt = 0; cnt < 100; cnt++) { - if (odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) + if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) break; ODM_delay_ms(10); } /*Recover channel number*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal); + odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal); /*enable RTK*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xc4, RFREGOFFSETMASK, 0x81402); + odm_set_rf_reg(dm, RF_PATH_A, 0xc4, RFREGOFFSETMASK, 0x81402); /**restore*/ - odm_write_4byte(p_dm_odm, 0xc00, tmp0xc00); - odm_write_4byte(p_dm_odm, 0xe00, tmp0xe00); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, bRFRegOffsetMask, 0x3ffff); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0, bRFRegOffsetMask, 0x3ffff); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK end!!!!!!!\n")); + odm_write_4byte(dm, 0xc00, tmp0xc00); + odm_write_4byte(dm, 0xe00, tmp0xe00); + odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x3ffff); + odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x3ffff); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[LCK]LCK end!!!!!!!\n"); } /*LCK VERSION:0x1*/ void phy_lc_calibrate_8822b( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - boolean is_start_cont_tx = false, is_single_tone = false, is_carrier_suppression = false; - u64 start_time; - u64 progressing_time; - - struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -#if (MP_DRIVER == 1) - struct _ADAPTER *p_adapter = p_dm_odm->adapter; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT p_mpt_ctx = &(p_adapter->MptCtx); - is_start_cont_tx = p_mpt_ctx->bStartContTx; - is_single_tone = p_mpt_ctx->bSingleTone; - is_carrier_suppression = p_mpt_ctx->bCarrierSuppression; -#else - PMPT_CONTEXT p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx); - is_start_cont_tx = p_mpt_ctx->is_start_cont_tx; - is_single_tone = p_mpt_ctx->is_single_tone; - is_carrier_suppression = p_mpt_ctx->is_carrier_suppression; -#endif -#endif -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(p_rf->rf_supportability & HAL_RF_LCK)) - return; -#endif - - if (is_start_cont_tx || is_single_tone || is_carrier_suppression) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]continues TX ing !!! LCK return\n")); - return; - } - - while (*(p_dm_odm->p_is_scan_in_process)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]scan is in process, bypass LCK\n")); - return; - } + struct dm_struct *dm = (struct dm_struct *)dm_void; - start_time = odm_get_current_time(p_dm_odm); - p_dm_odm->rf_calibrate_info.is_lck_in_progress = true; - _phy_lc_calibrate_8822b(p_dm_odm); - p_dm_odm->rf_calibrate_info.is_lck_in_progress = false; - progressing_time = odm_get_progressing_time(p_dm_odm, start_time); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK progressing_time = %lld\n", progressing_time)); + _phy_lc_calibrate_8822b(dm); } void configure_txpower_track_8822b( - struct _TXPWRTRACK_CFG *p_config + struct txpwrtrack_cfg *config ) { - p_config->swing_table_size_cck = TXSCALE_TABLE_SIZE; - p_config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE; - p_config->threshold_iqk = IQK_THRESHOLD; - p_config->threshold_dpk = DPK_THRESHOLD; - p_config->average_thermal_num = AVG_THERMAL_NUM_8822B; - p_config->rf_path_count = MAX_PATH_NUM_8822B; - p_config->thermal_reg_addr = RF_T_METER_8822B; - - p_config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8822b; - p_config->do_iqk = do_iqk_8822b; - p_config->phy_lc_calibrate = phy_lc_calibrate_8822b; + config->swing_table_size_cck = TXSCALE_TABLE_SIZE; + config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE; + config->threshold_iqk = IQK_THRESHOLD; + config->threshold_dpk = DPK_THRESHOLD; + config->average_thermal_num = AVG_THERMAL_NUM_8822B; + config->rf_path_count = MAX_PATH_NUM_8822B; + config->thermal_reg_addr = RF_T_METER_8822B; + + config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8822b; + config->do_iqk = do_iqk_8822b; + config->phy_lc_calibrate = halrf_lck_trigger; #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - p_config->get_delta_all_swing_table = get_delta_swing_table_8822b; + config->get_delta_all_swing_table = get_delta_swing_table_8822b; #else - p_config->get_delta_swing_table = get_delta_swing_table_8822b; + config->get_delta_swing_table = get_delta_swing_table_8822b; #endif } void phy_set_rf_path_switch_8822b( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct PHY_DM_STRUCT *p_dm_odm, -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct PHY_DM_STRUCT *p_dm_odm, +#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE)) + struct dm_struct *dm, #else - struct _ADAPTER *p_adapter, + void *adapter, #endif boolean is_main ) { -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) -#elif !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; -#endif +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #endif #endif /*BY SY Request */ - odm_set_bb_reg(p_dm_odm, 0x4C, (BIT(24) | BIT(23)), 0x2); + odm_set_bb_reg(dm, 0x4C, (BIT(24) | BIT(23)), 0x2); - odm_set_bb_reg(p_dm_odm, 0x974, 0xff, 0xff); + odm_set_bb_reg(dm, 0x974, 0xff, 0xff); - /*odm_set_bb_reg(p_dm_odm, 0x1991, 0x3, 0x0);*/ - odm_set_bb_reg(p_dm_odm, 0x1990, (BIT(9) | BIT(8)), 0x0); + /*odm_set_bb_reg(dm, 0x1991, 0x3, 0x0);*/ + odm_set_bb_reg(dm, 0x1990, (BIT(9) | BIT(8)), 0x0); - /*odm_set_bb_reg(p_dm_odm, 0xCBE, 0x8, 0x0);*/ - odm_set_bb_reg(p_dm_odm, 0xCBC, BIT(19), 0x0); + /*odm_set_bb_reg(dm, 0xCBE, 0x8, 0x0);*/ + odm_set_bb_reg(dm, 0xCBC, BIT(19), 0x0); - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xff, 0x77); + odm_set_bb_reg(dm, 0xCB4, 0xff, 0x77); - odm_set_bb_reg(p_dm_odm, 0x70, MASKBYTE3, 0x0e); - odm_set_bb_reg(p_dm_odm, 0x1704, MASKDWORD, 0x0000ff00); - odm_set_bb_reg(p_dm_odm, 0x1700, MASKDWORD, 0xc00f0038); + odm_set_bb_reg(dm, 0x70, MASKBYTE3, 0x0e); + odm_set_bb_reg(dm, 0x1704, MASKDWORD, 0x0000ff00); + odm_set_bb_reg(dm, 0x1700, MASKDWORD, 0xc00f0038); if (is_main) { - /*odm_set_bb_reg(p_dm_odm, 0xCBD, 0x3, 0x2); WiFi */ - odm_set_bb_reg(p_dm_odm, 0xCBC, (BIT(9) | BIT(8)), 0x2); /*WiFi */ + /*odm_set_bb_reg(dm, 0xCBD, 0x3, 0x2); WiFi */ + odm_set_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8)), 0x2); /*WiFi */ } else { - /*odm_set_bb_reg(p_dm_odm, 0xCBD, 0x3, 0x1); BT*/ - odm_set_bb_reg(p_dm_odm, 0xCBC, (BIT(9) | BIT(8)), 0x1); /*BT*/ + /*odm_set_bb_reg(dm, 0xCBD, 0x3, 0x1); BT*/ + odm_set_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8)), 0x1); /*BT*/ } } boolean _phy_query_rf_path_switch_8822b( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct PHY_DM_STRUCT *p_dm_odm -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct PHY_DM_STRUCT *p_dm_odm +#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE)) + struct dm_struct *dm #else - struct _ADAPTER *p_adapter + void *adapter #endif ) { -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) -#elif !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; -#endif +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #endif #endif - if (odm_get_bb_reg(p_dm_odm, 0xCBC, (BIT(9) | BIT(8))) == 0x2) /*WiFi */ + if (odm_get_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8))) == 0x2) /*WiFi */ return true; else return false; @@ -563,26 +531,21 @@ _phy_query_rf_path_switch_8822b( boolean phy_query_rf_path_switch_8822b( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct PHY_DM_STRUCT *p_dm_odm -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct PHY_DM_STRUCT *p_dm_odm +#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE)) + struct dm_struct *dm #else - struct _ADAPTER *p_adapter + void *adapter #endif ) { - #if DISABLE_BB_RF return true; #endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - return _phy_query_rf_path_switch_8822b(p_dm_odm); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - return _phy_query_rf_path_switch_8822b(p_dm_odm); +#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE)) + return _phy_query_rf_path_switch_8822b(dm); #else - return _phy_query_rf_path_switch_8822b(p_adapter); + return _phy_query_rf_path_switch_8822b(adapter); #endif } diff --git a/hal/phydm/halrf/rtl8822b/halrf_8822b.h b/hal/phydm/halrf/rtl8822b/halrf_8822b.h index a0fce9d..ea1c115 100644 --- a/hal/phydm/halrf/rtl8822b/halrf_8822b.h +++ b/hal/phydm/halrf/rtl8822b/halrf_8822b.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #ifndef __HAL_PHY_RF_8822B_H__ #define __HAL_PHY_RF_8822B_H__ @@ -24,16 +29,13 @@ #define AVG_THERMAL_NUM_8822B 4 #define RF_T_METER_8822B 0x42 -#define LCK_VERSION "0x2" - - void configure_txpower_track_8822b( - struct _TXPWRTRACK_CFG *p_config + struct txpwrtrack_cfg *config ); void odm_tx_pwr_track_set_pwr8822b( - void *p_dm_void, + void *dm_void, enum pwrtrack_method method, u8 rf_path, u8 channel_mapped_index @@ -41,7 +43,7 @@ odm_tx_pwr_track_set_pwr8822b( void get_delta_swing_table_8822b( - void *p_dm_void, + void *dm_void, #if (DM_ODM_SUPPORT_TYPE & ODM_AP) u8 **temperature_up_a, u8 **temperature_down_a, @@ -61,18 +63,21 @@ get_delta_swing_table_8822b( void phy_lc_calibrate_8822b( - void *p_dm_void + void *dm_void ); +void +halrf_rf_lna_setting_8822b( + struct dm_struct *dm, + enum phydm_lna_set type +); void phy_set_rf_path_switch_8822b( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct PHY_DM_STRUCT *p_dm_odm, -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct PHY_DM_STRUCT *p_dm_odm, +#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE)) + struct dm_struct *dm, #else - struct _ADAPTER *p_adapter, + void *adapter, #endif boolean is_main ); diff --git a/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c index 8258445..0c4813d 100644 --- a/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c +++ b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,19 +8,28 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #include "mp_precomp.h" #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#include "../phydm_precomp.h" + #if RT_PLATFORM==PLATFORM_MACOSX + #include "phydm_precomp.h" + #else + #include "../phydm_precomp.h" + #endif #else #include "../../phydm_precomp.h" #endif @@ -30,39 +39,19 @@ /*---------------------------Define Local Constant---------------------------*/ -void phydm_set_iqk_cfir(struct PHY_DM_STRUCT *p_dm_odm, struct _IQK_INFORMATION *p_iqk_info, u8 idx, u8 path) -{ - u8 i; - u32 tmp; - - odm_set_bb_reg(p_dm_odm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1); - if (idx == 0) - odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x3); - else - odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x1); - odm_set_bb_reg(p_dm_odm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10); - for (i = 0; i < 8; i++) { - odm_set_bb_reg(p_dm_odm, 0x1bd8, MASKDWORD, 0xe0000001 + (i * 4)); - tmp = odm_get_bb_reg(p_dm_odm, 0x1bfc, MASKDWORD); - p_iqk_info->IQK_CFIR_real[0][path][idx][i] = (tmp & 0x0fff0000) >> 16; - p_iqk_info->IQK_CFIR_imag[0][path][idx][i] = tmp & 0xfff; - } - odm_set_bb_reg(p_dm_odm, 0x1bd8, MASKDWORD, 0x0); - odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x0); -} -void phydm_get_read_counter(struct PHY_DM_STRUCT *p_dm_odm) +void phydm_get_read_counter(struct dm_struct *dm) { u32 counter = 0x0; while (1) { - if ((odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x8, RFREGOFFSETMASK) == 0xabcde) || (counter > 300)) + if ((odm_get_rf_reg(dm, RF_PATH_A, 0x8, RFREGOFFSETMASK) == 0xabcde) || (counter > 300)) break; counter++; ODM_delay_ms(1); }; - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x8, RFREGOFFSETMASK, 0x0); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]counter = %d\n", counter)); + odm_set_rf_reg(dm, RF_PATH_A, 0x8, RFREGOFFSETMASK, 0x0); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]counter = %d\n", counter); } /*---------------------------Define Local Constant---------------------------*/ @@ -70,97 +59,137 @@ void phydm_get_read_counter(struct PHY_DM_STRUCT *p_dm_odm) #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) void do_iqk_8822b( - void *p_dm_void, + void *dm_void, u8 delta_thermal_index, u8 thermal_value, u8 threshold ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) -#else - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); -#endif - - odm_reset_iqk_result(p_dm_odm); - - p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value; - - phy_iq_calibrate_8822b(p_dm_odm, true); - + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + dm->rf_calibrate_info.thermal_value_iqk = thermal_value; + halrf_segment_iqk_trigger(dm, true, iqk_info->segment_iqk); } #else -/*Originally p_config->do_iqk is hooked phy_iq_calibrate_8822b, but do_iqk_8822b and phy_iq_calibrate_8822b have different arguments*/ +/*Originally config->do_iqk is hooked phy_iq_calibrate_8822b, but do_iqk_8822b and phy_iq_calibrate_8822b have different arguments*/ void do_iqk_8822b( - void *p_dm_void, + void *dm_void, u8 delta_thermal_index, u8 thermal_value, u8 threshold ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; boolean is_recovery = (boolean) delta_thermal_index; - phy_iq_calibrate_8822b(p_dm_odm, true); + halrf_segment_iqk_trigger(dm, true, iqk_info->segment_iqk); } #endif + + +void +_iqk_rf_set_check( + struct dm_struct *dm, + u8 path, + u16 add, + u32 data + ) +{ + u32 i; + + odm_set_rf_reg(dm, (enum rf_path)path, add, RFREGOFFSETMASK, data); + + for (i = 0; i < 100; i++) { + if (odm_get_rf_reg(dm, (enum rf_path)path, add, RFREGOFFSETMASK) == data) + break; + else { + ODM_delay_us(10); + odm_set_rf_reg(dm, (enum rf_path)path, add, RFREGOFFSETMASK, data); + } + } +} + + void _iqk_rf0xb0_workaround( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { /*add 0xb8 control for the bad phase noise after switching channel*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)0x0, 0xb8, RFREGOFFSETMASK, 0x00a00); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)0x0, 0xb8, RFREGOFFSETMASK, 0x80a00); + odm_set_rf_reg(dm, (enum rf_path)0x0, 0xb8, RFREGOFFSETMASK, 0x00a00); + odm_set_rf_reg(dm, (enum rf_path)0x0, 0xb8, RFREGOFFSETMASK, 0x80a00); } void _iqk_fill_iqk_report_8822b( - void *p_dm_void, + void *dm_void, u8 channel ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; u32 tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0; u8 i; for (i = 0; i < SS_8822B; i++) { - tmp1 = tmp1 + ((p_iqk_info->IQK_fail_report[channel][i][TX_IQK] & 0x1) << i); - tmp2 = tmp2 + ((p_iqk_info->IQK_fail_report[channel][i][RX_IQK] & 0x1) << (i + 4)); - tmp3 = tmp3 + ((p_iqk_info->RXIQK_fail_code[channel][i] & 0x3) << (i * 2 + 8)); + tmp1 = tmp1 + ((iqk_info->iqk_fail_report[channel][i][TX_IQK] & 0x1) << i); + tmp2 = tmp2 + ((iqk_info->iqk_fail_report[channel][i][RX_IQK] & 0x1) << (i + 4)); + tmp3 = tmp3 + ((iqk_info->rxiqk_fail_code[channel][i] & 0x3) << (i * 2 + 8)); } - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); - odm_set_bb_reg(p_dm_odm, 0x1bf0, 0x0000ffff, tmp1 | tmp2 | tmp3); + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_set_bb_reg(dm, 0x1bf0, 0x0000ffff, tmp1 | tmp2 | tmp3); for (i = 0; i < 2; i++) - odm_write_4byte(p_dm_odm, 0x1be8 + (i * 4), (p_iqk_info->RXIQK_AGC[channel][(i * 2) + 1] << 16) | p_iqk_info->RXIQK_AGC[channel][i * 2]); + odm_write_4byte(dm, 0x1be8 + (i * 4), (iqk_info->rxiqk_agc[channel][(i * 2) + 1] << 16) | iqk_info->rxiqk_agc[channel][i * 2]); } +void +_iqk_fail_count_8822b( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 i; + + dm->n_iqk_cnt++; + if (odm_get_rf_reg(dm, RF_PATH_A, 0x1bf0, BIT(16)) == 1) + iqk_info->is_reload = true; + else + iqk_info->is_reload = false; + + if (!iqk_info->is_reload) { + for (i = 0; i < 8; i++) { + if (odm_get_bb_reg(dm, 0x1bf0, BIT(i)) == 1) + dm->n_iqk_fail_cnt++; + } + } + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]All/Fail = %d %d\n", dm->n_iqk_cnt, dm->n_iqk_fail_cnt); +} void _iqk_iqk_fail_report_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 tmp1bf0 = 0x0; u8 i; - tmp1bf0 = odm_read_4byte(p_dm_odm, 0x1bf0); + tmp1bf0 = odm_read_4byte(dm, 0x1bf0); for (i = 0; i < 4; i++) { if (tmp1bf0 & (0x1 << i)) #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] please check S%d TXIQK\n", i)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK] please check S%d TXIQK\n", i); #else panic_printk("[IQK] please check S%d TXIQK\n", i); #endif if (tmp1bf0 & (0x1 << (i + 12))) #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] please check S%d RXIQK\n", i)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK] please check S%d RXIQK\n", i); #else panic_printk("[IQK] please check S%d RXIQK\n", i); #endif @@ -171,7 +200,7 @@ _iqk_iqk_fail_report_8822b( void _iqk_backup_mac_bb_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 *MAC_backup, u32 *BB_backup, u32 *backup_mac_reg, @@ -180,18 +209,18 @@ _iqk_backup_mac_bb_8822b( { u32 i; for (i = 0; i < MAC_REG_NUM_8822B; i++) - MAC_backup[i] = odm_read_4byte(p_dm_odm, backup_mac_reg[i]); + MAC_backup[i] = odm_read_4byte(dm, backup_mac_reg[i]); for (i = 0; i < BB_REG_NUM_8822B; i++) - BB_backup[i] = odm_read_4byte(p_dm_odm, backup_bb_reg[i]); + BB_backup[i] = odm_read_4byte(dm, backup_bb_reg[i]); - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BackupMacBB Success!!!!\n")); */ + /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]BackupMacBB Success!!!!\n"); */ } void _iqk_backup_rf_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 RF_backup[][2], u32 *backup_rf_reg ) @@ -199,44 +228,44 @@ _iqk_backup_rf_8822b( u32 i; for (i = 0; i < RF_REG_NUM_8822B; i++) { - RF_backup[i][ODM_RF_PATH_A] = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK); - RF_backup[i][ODM_RF_PATH_B] = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_B, backup_rf_reg[i], RFREGOFFSETMASK); + RF_backup[i][RF_PATH_A] = odm_get_rf_reg(dm, RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK); + RF_backup[i][RF_PATH_B] = odm_get_rf_reg(dm, RF_PATH_B, backup_rf_reg[i], RFREGOFFSETMASK); } - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BackupRF Success!!!!\n")); */ + /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]BackupRF Success!!!!\n"); */ } void _iqk_agc_bnd_int_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { /*initialize RX AGC bnd, it must do after bbreset*/ - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); - odm_write_4byte(p_dm_odm, 0x1b00, 0xf80a7008); - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8015008); - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]init. rx agc bnd\n"));*/ + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1b00, 0xf80a7008); + odm_write_4byte(dm, 0x1b00, 0xf8015008); + odm_write_4byte(dm, 0x1b00, 0xf8000008); + /*PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]init. rx agc bnd\n");*/ } void _iqk_bb_reset_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { boolean cca_ing = false; u32 count = 0; - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000); + odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000); + odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000); /*reset BB report*/ - odm_set_bb_reg(p_dm_odm, 0x8f8, 0x0ff00000, 0x0); + odm_set_bb_reg(dm, 0x8f8, 0x0ff00000, 0x0); while (1) { - odm_write_4byte(p_dm_odm, 0x8fc, 0x0); - odm_set_bb_reg(p_dm_odm, 0x198c, 0x7, 0x7); - cca_ing = (boolean) odm_get_bb_reg(p_dm_odm, 0xfa0, BIT(3)); + odm_write_4byte(dm, 0x8fc, 0x0); + odm_set_bb_reg(dm, 0x198c, 0x7, 0x7); + cca_ing = (boolean) odm_get_bb_reg(dm, 0xfa0, BIT(3)); if (count > 30) cca_ing = false; @@ -245,16 +274,16 @@ _iqk_bb_reset_8822b( ODM_delay_ms(1); count++; } else { - odm_write_1byte(p_dm_odm, 0x808, 0x0); /*RX ant off*/ - odm_set_bb_reg(p_dm_odm, 0xa04, BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x0); /*CCK RX path off*/ + odm_write_1byte(dm, 0x808, 0x0); /*RX ant off*/ + odm_set_bb_reg(dm, 0xa04, BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x0); /*CCK RX path off*/ /*BBreset*/ - odm_set_bb_reg(p_dm_odm, 0x0, BIT(16), 0x0); - odm_set_bb_reg(p_dm_odm, 0x0, BIT(16), 0x1); + odm_set_bb_reg(dm, 0x0, BIT(16), 0x0); + odm_set_bb_reg(dm, 0x0, BIT(16), 0x1); - if (odm_get_bb_reg(p_dm_odm, 0x660, BIT(16))) - odm_write_4byte(p_dm_odm, 0x6b4, 0x89000006); - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BBreset!!!!\n"));*/ + if (odm_get_bb_reg(dm, 0x660, BIT(16))) + odm_write_4byte(dm, 0x6b4, 0x89000006); + /*PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]BBreset!!!!\n");*/ break; } } @@ -262,43 +291,43 @@ _iqk_bb_reset_8822b( void _iqk_afe_setting_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, boolean do_iqk ) { if (do_iqk) { - odm_write_4byte(p_dm_odm, 0xc60, 0x50000000); - odm_write_4byte(p_dm_odm, 0xc60, 0x70070040); - odm_write_4byte(p_dm_odm, 0xe60, 0x50000000); - odm_write_4byte(p_dm_odm, 0xe60, 0x70070040); - - odm_write_4byte(p_dm_odm, 0xc58, 0xd8000402); - odm_write_4byte(p_dm_odm, 0xc5c, 0xd1000120); - odm_write_4byte(p_dm_odm, 0xc6c, 0x00000a15); - odm_write_4byte(p_dm_odm, 0xe58, 0xd8000402); - odm_write_4byte(p_dm_odm, 0xe5c, 0xd1000120); - odm_write_4byte(p_dm_odm, 0xe6c, 0x00000a15); - _iqk_bb_reset_8822b(p_dm_odm); - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]AFE setting for IQK mode!!!!\n")); */ + odm_write_4byte(dm, 0xc60, 0x50000000); + odm_write_4byte(dm, 0xc60, 0x70070040); + odm_write_4byte(dm, 0xe60, 0x50000000); + odm_write_4byte(dm, 0xe60, 0x70070040); + odm_write_4byte(dm, 0xc58, 0xd8000402); + odm_write_4byte(dm, 0xc5c, 0xd1000120); + odm_write_4byte(dm, 0xc6c, 0x00000a15); + odm_write_4byte(dm, 0xe58, 0xd8000402); + odm_write_4byte(dm, 0xe5c, 0xd1000120); + odm_write_4byte(dm, 0xe6c, 0x00000a15); + _iqk_bb_reset_8822b(dm); + /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]AFE setting for IQK mode!!!!\n"); */ } else { - odm_write_4byte(p_dm_odm, 0xc60, 0x50000000); - odm_write_4byte(p_dm_odm, 0xc60, 0x70038040); - odm_write_4byte(p_dm_odm, 0xe60, 0x50000000); - odm_write_4byte(p_dm_odm, 0xe60, 0x70038040); - - odm_write_4byte(p_dm_odm, 0xc58, 0xd8020402); - odm_write_4byte(p_dm_odm, 0xc5c, 0xde000120); - odm_write_4byte(p_dm_odm, 0xc6c, 0x0000122a); - odm_write_4byte(p_dm_odm, 0xe58, 0xd8020402); - odm_write_4byte(p_dm_odm, 0xe5c, 0xde000120); - odm_write_4byte(p_dm_odm, 0xe6c, 0x0000122a); - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]AFE setting for Normal mode!!!!\n")); */ + odm_write_4byte(dm, 0xc60, 0x50000000); + odm_write_4byte(dm, 0xc60, 0x70038040); + odm_write_4byte(dm, 0xe60, 0x50000000); + odm_write_4byte(dm, 0xe60, 0x70038040); + odm_write_4byte(dm, 0xc58, 0xd8020402); + odm_write_4byte(dm, 0xc5c, 0xde000120); + odm_write_4byte(dm, 0xc6c, 0x0000122a); + odm_write_4byte(dm, 0xe58, 0xd8020402); + odm_write_4byte(dm, 0xe5c, 0xde000120); + odm_write_4byte(dm, 0xe6c, 0x0000122a); + /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]AFE setting for Normal mode!!!!\n"); */ } + /*0x9a4[31]=0: Select da clock*/ + odm_set_bb_reg(dm, 0x9a4, BIT(31), 0x0); } void _iqk_restore_mac_bb_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 *MAC_backup, u32 *BB_backup, u32 *backup_mac_reg, @@ -308,222 +337,228 @@ _iqk_restore_mac_bb_8822b( u32 i; for (i = 0; i < MAC_REG_NUM_8822B; i++) - odm_write_4byte(p_dm_odm, backup_mac_reg[i], MAC_backup[i]); + odm_write_4byte(dm, backup_mac_reg[i], MAC_backup[i]); for (i = 0; i < BB_REG_NUM_8822B; i++) - odm_write_4byte(p_dm_odm, backup_bb_reg[i], BB_backup[i]); - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RestoreMacBB Success!!!!\n")); */ + odm_write_4byte(dm, backup_bb_reg[i], BB_backup[i]); + /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]RestoreMacBB Success!!!!\n"); */ } void _iqk_restore_rf_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 *backup_rf_reg, u32 RF_backup[][2] ) { u32 i; - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x0); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, RFREGOFFSETMASK, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x0); + odm_set_rf_reg(dm, RF_PATH_B, 0xef, RFREGOFFSETMASK, 0x0); /*0xdf[4]=0*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, RFREGOFFSETMASK, RF_backup[0][ODM_RF_PATH_A] & (~BIT(4))); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xdf, RFREGOFFSETMASK, RF_backup[0][ODM_RF_PATH_B] & (~BIT(4))); + _iqk_rf_set_check(dm, RF_PATH_A, 0xdf, RF_backup[0][RF_PATH_A] & (~BIT(4))); + _iqk_rf_set_check(dm, RF_PATH_B, 0xdf, RF_backup[0][RF_PATH_B] & (~BIT(4))); + + /*odm_set_rf_reg(dm, RF_PATH_A, 0xdf, RFREGOFFSETMASK, RF_backup[0][RF_PATH_A] & (~BIT(4)));*/ + /*odm_set_rf_reg(dm, RF_PATH_B, 0xdf, RFREGOFFSETMASK, RF_backup[0][RF_PATH_B] & (~BIT(4)));*/ for (i = 1; i < RF_REG_NUM_8822B; i++) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][ODM_RF_PATH_A]); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][ODM_RF_PATH_B]); + odm_set_rf_reg(dm, RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][RF_PATH_A]); + odm_set_rf_reg(dm, RF_PATH_B, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][RF_PATH_B]); } - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RestoreRF Success!!!!\n")); */ + /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]RestoreRF Success!!!!\n"); */ } void _iqk_backup_iqk_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 step, u8 path ) { - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_iqk_info *iqk_info = &dm->IQK_info; u8 i, j, k; - u16 iqk_apply[2] = {0xc94, 0xe94}; switch (step) { case 0: - p_iqk_info->iqk_channel[1] = p_iqk_info->iqk_channel[0]; + iqk_info->iqk_channel[1] = iqk_info->iqk_channel[0]; for (i = 0; i < 2; i++) { - p_iqk_info->LOK_IDAC[1][i] = p_iqk_info->LOK_IDAC[0][i]; - p_iqk_info->RXIQK_AGC[1][i] = p_iqk_info->RXIQK_AGC[0][i]; - p_iqk_info->bypass_iqk[1][i] = p_iqk_info->bypass_iqk[0][i]; - p_iqk_info->RXIQK_fail_code[1][i] = p_iqk_info->RXIQK_fail_code[0][i]; + iqk_info->lok_idac[1][i] = iqk_info->lok_idac[0][i]; + iqk_info->rxiqk_agc[1][i] = iqk_info->rxiqk_agc[0][i]; + iqk_info->bypass_iqk[1][i] = iqk_info->bypass_iqk[0][i]; + iqk_info->rxiqk_fail_code[1][i] = iqk_info->rxiqk_fail_code[0][i]; for (j = 0; j < 2; j++) { - p_iqk_info->IQK_fail_report[1][i][j] = p_iqk_info->IQK_fail_report[0][i][j]; + iqk_info->iqk_fail_report[1][i][j] = iqk_info->iqk_fail_report[0][i][j]; for (k = 0; k < 8; k++) { - p_iqk_info->IQK_CFIR_real[1][i][j][k] = p_iqk_info->IQK_CFIR_real[0][i][j][k]; - p_iqk_info->IQK_CFIR_imag[1][i][j][k] = p_iqk_info->IQK_CFIR_imag[0][i][j][k]; + iqk_info->iqk_cfir_real[1][i][j][k] = iqk_info->iqk_cfir_real[0][i][j][k]; + iqk_info->iqk_cfir_imag[1][i][j][k] = iqk_info->iqk_cfir_imag[0][i][j][k]; } } } for (i = 0; i < 4; i++) { - p_iqk_info->RXIQK_fail_code[0][i] = 0x0; - p_iqk_info->RXIQK_AGC[0][i] = 0x0; + iqk_info->rxiqk_fail_code[0][i] = 0x0; + iqk_info->rxiqk_agc[0][i] = 0x0; for (j = 0; j < 2; j++) { - p_iqk_info->IQK_fail_report[0][i][j] = true; - p_iqk_info->gs_retry_count[0][i][j] = 0x0; + iqk_info->iqk_fail_report[0][i][j] = true; + iqk_info->gs_retry_count[0][i][j] = 0x0; } for (j = 0; j < 3; j++) - p_iqk_info->retry_count[0][i][j] = 0x0; + iqk_info->retry_count[0][i][j] = 0x0; } /*backup channel*/ - p_iqk_info->iqk_channel[0] = p_iqk_info->rf_reg18; + iqk_info->iqk_channel[0] = iqk_info->rf_reg18; break; case 1: /*LOK backup*/ - p_iqk_info->LOK_IDAC[0][path] = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x58, RFREGOFFSETMASK); + iqk_info->lok_idac[0][path] = odm_get_rf_reg(dm, (enum rf_path)path, 0x58, RFREGOFFSETMASK); break; case 2: /*TXIQK backup*/ case 3: /*RXIQK backup*/ - phydm_set_iqk_cfir(p_dm_odm, p_iqk_info, (step-2), path); + phydm_get_iqk_cfir(dm, (step-2), path, false); break; } } void _iqk_reload_iqk_setting_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 channel, u8 reload_idx /*1: reload TX, 2: reload LO, TX, RX*/ ) { - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_iqk_info *iqk_info = &dm->IQK_info; u8 i, path, idx; - u16 iqk_apply[2] = {0xc94, 0xe94}; + u16 iqk_apply[2] = {0xc94, 0xe94}; + u32 tmp; for (path = 0; path < 2; path++) { if (reload_idx == 2) { - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xdf, BIT(4), 0x1); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x58, RFREGOFFSETMASK, p_iqk_info->LOK_IDAC[channel][path]); + /*odm_set_rf_reg(dm, (enum rf_path)path, 0xdf, BIT(4), 0x1);*/ + tmp = odm_get_rf_reg(dm, (enum rf_path)path, 0xdf, RFREGOFFSETMASK) | BIT(4); + _iqk_rf_set_check(dm, (enum rf_path)path, 0xdf, tmp); + odm_set_rf_reg(dm, (enum rf_path)path, 0x58, RFREGOFFSETMASK, iqk_info->lok_idac[channel][path]); } for (idx = 0; idx < reload_idx; idx++) { - odm_set_bb_reg(p_dm_odm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1); - odm_set_bb_reg(p_dm_odm, 0x1b2c, MASKDWORD, 0x7); - odm_set_bb_reg(p_dm_odm, 0x1b38, MASKDWORD, 0x20000000); - odm_set_bb_reg(p_dm_odm, 0x1b3c, MASKDWORD, 0x20000000); - odm_set_bb_reg(p_dm_odm, 0x1bcc, MASKDWORD, 0x00000000); + odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1); + odm_set_bb_reg(dm, 0x1b2c, MASKDWORD, 0x7); + odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x20000000); + odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, 0x20000000); + odm_set_bb_reg(dm, 0x1bcc, MASKDWORD, 0x00000000); if (idx == 0) - odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x3); + odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x3); else - odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x1); - odm_set_bb_reg(p_dm_odm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10); + odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x1); + odm_set_bb_reg(dm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10); for (i = 0; i < 8; i++) { - odm_write_4byte(p_dm_odm, 0x1bd8, ((0xc0000000 >> idx) + 0x3) + (i * 4) + (p_iqk_info->IQK_CFIR_real[channel][path][idx][i] << 9)); - odm_write_4byte(p_dm_odm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (p_iqk_info->IQK_CFIR_imag[channel][path][idx][i] << 9)); + odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x3) + (i * 4) + (iqk_info->iqk_cfir_real[channel][path][idx][i] << 9)); + odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (iqk_info->iqk_cfir_imag[channel][path][idx][i] << 9)); } if (idx == 0) - odm_set_bb_reg(p_dm_odm, iqk_apply[path], BIT(0), ~(p_iqk_info->IQK_fail_report[channel][path][idx])); + odm_set_bb_reg(dm, iqk_apply[path], BIT(0), ~(iqk_info->iqk_fail_report[channel][path][idx])); else - odm_set_bb_reg(p_dm_odm, iqk_apply[path], BIT(10), ~(p_iqk_info->IQK_fail_report[channel][path][idx])); + odm_set_bb_reg(dm, iqk_apply[path], BIT(10), ~(iqk_info->iqk_fail_report[channel][path][idx])); } - odm_set_bb_reg(p_dm_odm, 0x1bd8, MASKDWORD, 0x0); - odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x0); + odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0); + odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0); } } boolean _iqk_reload_iqk_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, boolean reset ) { - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_iqk_info *iqk_info = &dm->IQK_info; u8 i; - boolean reload = false; + iqk_info->is_reload = false; if (reset) { for (i = 0; i < 2; i++) - p_iqk_info->iqk_channel[i] = 0x0; + iqk_info->iqk_channel[i] = 0x0; } else { - p_iqk_info->rf_reg18 = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + iqk_info->rf_reg18 = odm_get_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK); for (i = 0; i < 2; i++) { - if (p_iqk_info->rf_reg18 == p_iqk_info->iqk_channel[i]) { - _iqk_reload_iqk_setting_8822b(p_dm_odm, i, 2); - _iqk_fill_iqk_report_8822b(p_dm_odm, i); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]reload IQK result before!!!!\n")); - reload = true; + if (iqk_info->rf_reg18 == iqk_info->iqk_channel[i]) { + _iqk_reload_iqk_setting_8822b(dm, i, 2); + _iqk_fill_iqk_report_8822b(dm, i); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]reload IQK result before!!!!\n"); + iqk_info->is_reload = true; } } } /*report*/ - odm_set_bb_reg(p_dm_odm, 0x1bf0, BIT(16), (u8)reload); - return reload; + odm_set_bb_reg(dm, 0x1bf0, BIT(16), (u8) iqk_info->is_reload); + return iqk_info->is_reload; } void _iqk_rfe_setting_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, boolean ext_pa_on ) { if (ext_pa_on) { /*RFE setting*/ - odm_write_4byte(p_dm_odm, 0xcb0, 0x77777777); - odm_write_4byte(p_dm_odm, 0xcb4, 0x00007777); - odm_write_4byte(p_dm_odm, 0xcbc, 0x0000083B); - odm_write_4byte(p_dm_odm, 0xeb0, 0x77777777); - odm_write_4byte(p_dm_odm, 0xeb4, 0x00007777); - odm_write_4byte(p_dm_odm, 0xebc, 0x0000083B); - /*odm_write_4byte(p_dm_odm, 0x1990, 0x00000c30);*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]external PA on!!!!\n")); + odm_write_4byte(dm, 0xcb0, 0x77777777); + odm_write_4byte(dm, 0xcb4, 0x00007777); + odm_write_4byte(dm, 0xcbc, 0x0000083B); + odm_write_4byte(dm, 0xeb0, 0x77777777); + odm_write_4byte(dm, 0xeb4, 0x00007777); + odm_write_4byte(dm, 0xebc, 0x0000083B); + /*odm_write_4byte(dm, 0x1990, 0x00000c30);*/ + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]external PA on!!!!\n"); } else { /*RFE setting*/ - odm_write_4byte(p_dm_odm, 0xcb0, 0x77777777); - odm_write_4byte(p_dm_odm, 0xcb4, 0x00007777); - odm_write_4byte(p_dm_odm, 0xcbc, 0x00000100); - odm_write_4byte(p_dm_odm, 0xeb0, 0x77777777); - odm_write_4byte(p_dm_odm, 0xeb4, 0x00007777); - odm_write_4byte(p_dm_odm, 0xebc, 0x00000100); - /*odm_write_4byte(p_dm_odm, 0x1990, 0x00000c30);*/ - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]external PA off!!!!\n"));*/ + odm_write_4byte(dm, 0xcb0, 0x77777777); + odm_write_4byte(dm, 0xcb4, 0x00007777); + odm_write_4byte(dm, 0xcbc, 0x00000100); + odm_write_4byte(dm, 0xeb0, 0x77777777); + odm_write_4byte(dm, 0xeb4, 0x00007777); + odm_write_4byte(dm, 0xebc, 0x00000100); + /*odm_write_4byte(dm, 0x1990, 0x00000c30);*/ + /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]external PA off!!!!\n");*/ } } void _iqk_rf_setting_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u8 path; u32 tmp; - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); - odm_write_4byte(p_dm_odm, 0x1bb8, 0x00000000); + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1bb8, 0x00000000); for (path = 0; path < 2; path++) { /*0xdf:B11 = 1,B4 = 0, B1 = 1*/ - tmp = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xdf, RFREGOFFSETMASK); + tmp = odm_get_rf_reg(dm, (enum rf_path)path, 0xdf, RFREGOFFSETMASK); tmp = (tmp & (~BIT(4))) | BIT(1) | BIT(11); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xdf, RFREGOFFSETMASK, tmp); + _iqk_rf_set_check(dm, (enum rf_path)path, 0xdf, tmp); + /*odm_set_rf_reg(dm, (enum rf_path)path, 0xdf, RFREGOFFSETMASK, tmp);*/ /*release 0x56 TXBB*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x65, RFREGOFFSETMASK, 0x09000); - - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x1); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, RFREGOFFSETMASK, 0x00026); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3e, RFREGOFFSETMASK, 0x00037); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3f, RFREGOFFSETMASK, 0xdefce); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x0); + odm_set_rf_reg(dm, (enum rf_path)path, 0x65, RFREGOFFSETMASK, 0x09000); + + if (*dm->band_type == ODM_BAND_5G) { + odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, 0x33, RFREGOFFSETMASK, 0x00026); + odm_set_rf_reg(dm, (enum rf_path)path, 0x3e, RFREGOFFSETMASK, 0x00037); + odm_set_rf_reg(dm, (enum rf_path)path, 0x3f, RFREGOFFSETMASK, 0xdefce); + odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x0); } else { - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x1); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, RFREGOFFSETMASK, 0x00026); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3e, RFREGOFFSETMASK, 0x00037); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3f, RFREGOFFSETMASK, 0x5efce); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x0); + odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, 0x33, RFREGOFFSETMASK, 0x00026); + odm_set_rf_reg(dm, (enum rf_path)path, 0x3e, RFREGOFFSETMASK, 0x00037); + odm_set_rf_reg(dm, (enum rf_path)path, 0x3f, RFREGOFFSETMASK, 0x5efce); + odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x0); } } } @@ -532,187 +567,201 @@ _iqk_rf_setting_8822b( void _iqk_configure_macbb_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { /*MACBB register setting*/ - odm_write_1byte(p_dm_odm, 0x522, 0x7f); - odm_set_bb_reg(p_dm_odm, 0x550, BIT(11) | BIT(3), 0x0); - odm_set_bb_reg(p_dm_odm, 0x90c, BIT(15), 0x1); /*0x90c[15]=1: dac_buf reset selection*/ - odm_set_bb_reg(p_dm_odm, 0x9a4, BIT(31), 0x0); /*0x9a4[31]=0: Select da clock*/ - /*0xc94[0]=1, 0xe94[0]=1: Åýtx±qiqk¥´¥X¨Ó*/ - odm_set_bb_reg(p_dm_odm, 0xc94, BIT(0), 0x1); - odm_set_bb_reg(p_dm_odm, 0xe94, BIT(0), 0x1); - odm_set_bb_reg(p_dm_odm, 0xc94, (BIT(11) | BIT(10)), 0x1); - odm_set_bb_reg(p_dm_odm, 0xe94, (BIT(11) | BIT(10)), 0x1); + odm_write_1byte(dm, 0x522, 0x7f); + odm_set_bb_reg(dm, 0x550, BIT(11) | BIT(3), 0x0); + odm_set_bb_reg(dm, 0x90c, BIT(15), 0x1); /*0x90c[15]=1: dac_buf reset selection*/ + /*0xc94[0]=1, 0xe94[0]=1: Let tx from IQK*/ + odm_set_bb_reg(dm, 0xc94, BIT(0), 0x1); + odm_set_bb_reg(dm, 0xe94, BIT(0), 0x1); + odm_set_bb_reg(dm, 0xc94, (BIT(11) | BIT(10)), 0x1); + odm_set_bb_reg(dm, 0xe94, (BIT(11) | BIT(10)), 0x1); /* 3-wire off*/ - odm_write_4byte(p_dm_odm, 0xc00, 0x00000004); - odm_write_4byte(p_dm_odm, 0xe00, 0x00000004); + odm_write_4byte(dm, 0xc00, 0x00000004); + odm_write_4byte(dm, 0xe00, 0x00000004); /*disable PMAC*/ - odm_set_bb_reg(p_dm_odm, 0xb00, BIT(8), 0x0); - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set MACBB setting for IQK!!!!\n"));*/ + odm_set_bb_reg(dm, 0xb00, BIT(8), 0x0); + /*disable CCK block*/ + odm_set_bb_reg(dm, 0x808, BIT(28), 0x0); + /*disable OFDM CCA*/ + odm_set_bb_reg(dm, 0x838, BIT(3) | BIT(2) | BIT(1), 0x7); + /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]Set MACBB setting for IQK!!!!\n");*/ } void _iqk_lok_setting_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 path ) { - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); - odm_write_4byte(p_dm_odm, 0x1bcc, 0x9); - odm_write_1byte(p_dm_odm, 0x1b23, 0x00); + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1bcc, 0x9); + odm_write_1byte(dm, 0x1b23, 0x00); - switch (*p_dm_odm->p_band_type) { + switch (*dm->band_type) { case ODM_BAND_2_4G: - odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x50df2); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xadc00); + odm_write_1byte(dm, 0x1b2b, 0x00); + odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x50df2); + odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xadc00); /* WE_LUT_TX_LOK*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(4), 0x1); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, BIT(1) | BIT(0), 0x0); + odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(4), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, 0x33, BIT(1) | BIT(0), 0x0); break; case ODM_BAND_5G: - odm_write_1byte(p_dm_odm, 0x1b2b, 0x80); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x5086c); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xa9c00); + odm_write_1byte(dm, 0x1b2b, 0x80); + odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x5086c); + odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xa9c00); /* WE_LUT_TX_LOK*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(4), 0x1); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, BIT(1) | BIT(0), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(4), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, 0x33, BIT(1) | BIT(0), 0x1); break; } - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set LOK setting!!!!\n"));*/ + /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]Set LOK setting!!!!\n");*/ } void _iqk_txk_setting_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 path ) { - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); - odm_write_4byte(p_dm_odm, 0x1bcc, 0x9); - odm_write_4byte(p_dm_odm, 0x1b20, 0x01440008); + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1bcc, 0x9); + odm_write_4byte(dm, 0x1b20, 0x01440008); if (path == 0x0) - odm_write_4byte(p_dm_odm, 0x1b00, 0xf800000a); + odm_write_4byte(dm, 0x1b00, 0xf800000a); else - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); - odm_write_4byte(p_dm_odm, 0x1bcc, 0x3f); + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1bcc, 0x3f); - switch (*p_dm_odm->p_band_type) { + switch (*dm->band_type) { case ODM_BAND_2_4G: - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x50df2); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xadc00); - odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x50df2); + odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xadc00); + odm_write_1byte(dm, 0x1b2b, 0x00); break; case ODM_BAND_5G: - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x500ef); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xa9c00); - odm_write_1byte(p_dm_odm, 0x1b2b, 0x80); + odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x500ef); + odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xa9c00); + odm_write_1byte(dm, 0x1b2b, 0x80); break; } - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set TXK setting!!!!\n"));*/ + /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]Set TXK setting!!!!\n");*/ } void _iqk_rxk1_setting_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 path ) { - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); - switch (*p_dm_odm->p_band_type) { + switch (*dm->band_type) { case ODM_BAND_2_4G: - odm_write_1byte(p_dm_odm, 0x1bcc, 0x9); - odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); - odm_write_4byte(p_dm_odm, 0x1b20, 0x01450008); - odm_write_4byte(p_dm_odm, 0x1b24, 0x01460c88); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x510e0); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xacc00); + odm_write_1byte(dm, 0x1bcc, 0x9); + odm_write_1byte(dm, 0x1b2b, 0x00); + odm_write_4byte(dm, 0x1b20, 0x01450008); + odm_write_4byte(dm, 0x1b24, 0x01460c88); + odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x510e0); + odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xacc00); break; case ODM_BAND_5G: - odm_write_1byte(p_dm_odm, 0x1bcc, 0x09); - odm_write_1byte(p_dm_odm, 0x1b2b, 0x80); - odm_write_4byte(p_dm_odm, 0x1b20, 0x00850008); - odm_write_4byte(p_dm_odm, 0x1b24, 0x00460048); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x510e0); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xadc00); + odm_write_1byte(dm, 0x1bcc, 0x09); + odm_write_1byte(dm, 0x1b2b, 0x80); + odm_write_4byte(dm, 0x1b20, 0x00850008); + odm_write_4byte(dm, 0x1b24, 0x00460048); + odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x510e0); + odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xadc00); break; } - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set RXK setting!!!!\n"));*/ + /*PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]Set RXK setting!!!!\n");*/ } void _iqk_rxk2_setting_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 path, boolean is_gs ) { - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_iqk_info *iqk_info = &dm->IQK_info; - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); - switch (*p_dm_odm->p_band_type) { + switch (*dm->band_type) { case ODM_BAND_2_4G: if (is_gs) - p_iqk_info->tmp1bcc = 0x12; - odm_write_1byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc); - odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); - odm_write_4byte(p_dm_odm, 0x1b20, 0x01450008); - odm_write_4byte(p_dm_odm, 0x1b24, 0x01460848); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x510e0); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xa9c00); + iqk_info->tmp1bcc = 0x12; + odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc); + odm_write_1byte(dm, 0x1b2b, 0x00); + odm_write_4byte(dm, 0x1b20, 0x01450008); + odm_write_4byte(dm, 0x1b24, 0x01460848); + odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x510e0); + odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xa9c00); break; case ODM_BAND_5G: if (is_gs) { - if (path == ODM_RF_PATH_A) - p_iqk_info->tmp1bcc = 0x12; + if (path == RF_PATH_A) + iqk_info->tmp1bcc = 0x12; else - p_iqk_info->tmp1bcc = 0x09; + iqk_info->tmp1bcc = 0x09; } - odm_write_1byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc); - odm_write_1byte(p_dm_odm, 0x1b2b, 0x80); - odm_write_4byte(p_dm_odm, 0x1b20, 0x00850008); - odm_write_4byte(p_dm_odm, 0x1b24, 0x00460848); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK, 0x51060); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8f, RFREGOFFSETMASK, 0xa9c00); + odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc); + odm_write_1byte(dm, 0x1b2b, 0x80); + odm_write_4byte(dm, 0x1b20, 0x00850008); + odm_write_4byte(dm, 0x1b24, 0x00460848); + odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x51060); + odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xa9c00); break; } - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set RXK setting!!!!\n"));*/ + /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]Set RXK setting!!!!\n");*/ } void halrf_iqk_set_rf0x8( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 path ) { u16 c = 0x0; while (c < 30000) { - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, RFREGOFFSETMASK, 0x0); - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8, RFREGOFFSETMASK, 0x0); - if (odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8, RFREGOFFSETMASK) == 0x0) + odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x0); + odm_set_rf_reg(dm, (enum rf_path)path, 0x8, RFREGOFFSETMASK, 0x0); + if (odm_get_rf_reg(dm, (enum rf_path)path, 0x8, RFREGOFFSETMASK) == 0x0) break; c++; } } +void +halrf_iqk_check_if_reload( + struct dm_struct *dm +) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + iqk_info->is_reload = (boolean)odm_get_bb_reg(dm, 0x1bf0, BIT(16)); +} + + boolean _iqk_check_cal_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 path, u8 cmd ) @@ -721,11 +770,11 @@ _iqk_check_cal_8822b( u32 delay_count = 0x0; while (notready) { - if (odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8, RFREGOFFSETMASK) == 0x12345) { + if (odm_get_rf_reg(dm, (enum rf_path)path, 0x8, RFREGOFFSETMASK) == 0x12345) { if (cmd == 0x0)/*LOK*/ fail = false; else - fail = (boolean) odm_get_bb_reg(p_dm_odm, 0x1b08, BIT(26)); + fail = (boolean) odm_get_bb_reg(dm, 0x1b08, BIT(26)); notready = false; } else { ODM_delay_ms(1); @@ -734,141 +783,124 @@ _iqk_check_cal_8822b( if (delay_count >= 50) { fail = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]IQK timeout!!!\n")); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]IQK timeout!!!\n"); break; } } - halrf_iqk_set_rf0x8(p_dm_odm, path); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]delay count = 0x%x!!!\n", delay_count)); + halrf_iqk_set_rf0x8(dm, path); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]delay count = 0x%x!!!\n", delay_count); return fail; } boolean _iqk_rx_iqk_gain_search_fail_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 path, u8 step ) { - - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_iqk_info *iqk_info = &dm->IQK_info; boolean fail = true; u32 IQK_CMD = 0x0, rf_reg0, tmp, bb_idx; u8 IQMUX[4] = {0x9, 0x12, 0x1b, 0x24}; u8 idx; - for (idx = 0; idx < 4; idx++) - if (p_iqk_info->tmp1bcc == IQMUX[idx]) - break; - - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); - odm_write_4byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc); - if (step == RXIQK1) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d RXIQK GainSearch ============\n", path)); - - if (step == RXIQK1) + if (step == RXIQK1) { + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]============ S%d RXIQK GainSearch ============\n", path); IQK_CMD = 0xf8000208 | (1 << (path + 4)); - else - IQK_CMD = 0xf8000308 | (1 << (path + 4)); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S%d GS%d_Trigger = 0x%x\n", path, step, IQK_CMD)); - - odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD); - odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD + 0x1); - ODM_delay_ms(GS_delay_8822B); - fail = _iqk_check_cal_8822b(p_dm_odm, path, 0x1); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]S%d GS%d_Trigger = 0x%x\n", path, step, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1); + ODM_delay_ms(GS_delay_8822B); + fail = _iqk_check_cal_8822b(dm, path, 0x1); + } else if (step == RXIQK2) { + for (idx = 0; idx < 4; idx++) { + if (iqk_info->tmp1bcc == IQMUX[idx]) + break; + } + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc); - if (step == RXIQK2) { - rf_reg0 = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x0, RFREGOFFSETMASK); - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]S%d ==> RF0x0 = 0x%x, tmp1bcc = 0x%x, idx = %d, 0x1b3c = 0x%x\n", path, rf_reg0, p_iqk_info->tmp1bcc, idx, odm_read_4byte(p_dm_odm, 0x1b3c))); + IQK_CMD = 0xf8000308 | (1 << (path + 4)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]S%d GS%d_Trigger = 0x%x\n", path, step, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1); + ODM_delay_ms(GS_delay_8822B); + fail = _iqk_check_cal_8822b(dm, path, 0x1); + + rf_reg0 = odm_get_rf_reg(dm, (enum rf_path)path, 0x0, RFREGOFFSETMASK); + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]S%d ==> RF0x0 = 0x%x, tmp1bcc = 0x%x, idx = %d, 0x1b3c = 0x%x\n", path, rf_reg0, iqk_info->tmp1bcc, idx, odm_read_4byte(dm, 0x1b3c)); tmp = (rf_reg0 & 0x1fe0) >> 5; - p_iqk_info->lna_idx = tmp >> 5; + iqk_info->lna_idx = tmp >> 5; bb_idx = tmp & 0x1f; -#if 1 + if (bb_idx == 0x1) { - if (p_iqk_info->lna_idx != 0x0) - p_iqk_info->lna_idx--; + if (iqk_info->lna_idx != 0x0) + iqk_info->lna_idx--; else if (idx != 3) idx++; else - p_iqk_info->isbnd = true; + iqk_info->isbnd = true; fail = true; } else if (bb_idx == 0xa) { if (idx != 0) idx--; - else if (p_iqk_info->lna_idx != 0x7) - p_iqk_info->lna_idx++; + else if (iqk_info->lna_idx != 0x7) + iqk_info->lna_idx++; else - p_iqk_info->isbnd = true; + iqk_info->isbnd = true; fail = true; } else fail = false; - if (p_iqk_info->isbnd == true) + if (iqk_info->isbnd == true) fail = false; - p_iqk_info->tmp1bcc = IQMUX[idx]; -#endif + iqk_info->tmp1bcc = IQMUX[idx]; -#if 0 - if (bb_idx == 0x1) { - if (p_iqk_info->lna_idx != 0x0) - p_iqk_info->lna_idx--; - fail = true; - } else if (bb_idx == 0xa) { - if (p_iqk_info->lna_idx != 0x7) - p_iqk_info->lna_idx++; - fail = true; - } else - fail = false; -#endif if (fail) { - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); - odm_write_4byte(p_dm_odm, 0x1b24, (odm_read_4byte(p_dm_odm, 0x1b24) & 0xffffe3ff) | (p_iqk_info->lna_idx << 10)); + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0xffffe3ff) | (iqk_info->lna_idx << 10)); } } - return fail; } boolean _lok_one_shot_8822b( - void *p_dm_void, + void *dm_void, u8 path ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; u8 delay_count = 0; boolean LOK_notready = false; u32 LOK_temp = 0; u32 IQK_CMD = 0x0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]==========S%d LOK ==========\n", path)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]==========S%d LOK ==========\n", path); IQK_CMD = 0xf8000008 | (1 << (4 + path)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]LOK_Trigger = 0x%x\n", IQK_CMD)); - odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD); - odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD + 1); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]LOK_Trigger = 0x%x\n", IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD + 1); /*LOK: CMD ID = 0 {0xf8000018, 0xf8000028}*/ /*LOK: CMD ID = 0 {0xf8000019, 0xf8000029}*/ ODM_delay_ms(LOK_delay_8822B); - LOK_notready = _iqk_check_cal_8822b(p_dm_odm, path, 0x0); + LOK_notready = _iqk_check_cal_8822b(dm, path, 0x0); if (!LOK_notready) - _iqk_backup_iqk_8822b(p_dm_odm, 0x1, path); + _iqk_backup_iqk_8822b(dm, 0x1, path); if (ODM_COMP_CALIBRATION) { if (!LOK_notready) { - LOK_temp = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x58, RFREGOFFSETMASK); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]0x58 = 0x%x\n", LOK_temp)); + LOK_temp = odm_get_rf_reg(dm, (enum rf_path)path, 0x58, RFREGOFFSETMASK); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]0x58 = 0x%x\n", LOK_temp); } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]==>S%d LOK Fail!!!\n", path)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]==>S%d LOK Fail!!!\n", path); } - p_iqk_info->LOK_fail[path] = LOK_notready; + iqk_info->lok_fail[path] = LOK_notready; return LOK_notready; } @@ -877,92 +909,89 @@ _lok_one_shot_8822b( boolean _iqk_one_shot_8822b( - void *p_dm_void, + void *dm_void, u8 path, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; u8 delay_count = 0; boolean notready = true, fail = true; u32 IQK_CMD = 0x0; u16 iqk_apply[2] = {0xc94, 0xe94}; if (idx == TXIQK) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBTXIQK ============\n", path)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]============ S%d WBTXIQK ============\n", path); else if (idx == RXIQK1) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBRXIQK STEP1============\n", path)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]============ S%d WBRXIQK STEP1============\n", path); else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBRXIQK STEP2============\n", path)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]============ S%d WBRXIQK STEP2============\n", path); if (idx == TXIQK) { - IQK_CMD = 0xf8000008 | ((*p_dm_odm->p_band_width + 4) << 8) | (1 << (path + 4)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]TXK_Trigger = 0x%x\n", IQK_CMD)); + IQK_CMD = 0xf8000008 | ((*dm->band_width + 4) << 8) | (1 << (path + 4)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]TXK_Trigger = 0x%x\n", IQK_CMD); /*{0xf8000418, 0xf800042a} ==> 20 WBTXK (CMD = 4)*/ /*{0xf8000518, 0xf800052a} ==> 40 WBTXK (CMD = 5)*/ /*{0xf8000618, 0xf800062a} ==> 80 WBTXK (CMD = 6)*/ } else if (idx == RXIQK1) { - if (*p_dm_odm->p_band_width == 2) + if (*dm->band_width == 2) IQK_CMD = 0xf8000808 | (1 << (path + 4)); else IQK_CMD = 0xf8000708 | (1 << (path + 4)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]RXK1_Trigger = 0x%x\n", IQK_CMD)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]RXK1_Trigger = 0x%x\n", IQK_CMD); /*{0xf8000718, 0xf800072a} ==> 20 WBTXK (CMD = 7)*/ /*{0xf8000718, 0xf800072a} ==> 40 WBTXK (CMD = 7)*/ /*{0xf8000818, 0xf800082a} ==> 80 WBTXK (CMD = 8)*/ } else if (idx == RXIQK2) { - IQK_CMD = 0xf8000008 | ((*p_dm_odm->p_band_width + 9) << 8) | (1 << (path + 4)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]RXK2_Trigger = 0x%x\n", IQK_CMD)); + IQK_CMD = 0xf8000008 | ((*dm->band_width + 9) << 8) | (1 << (path + 4)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]RXK2_Trigger = 0x%x\n", IQK_CMD); /*{0xf8000918, 0xf800092a} ==> 20 WBRXK (CMD = 9)*/ /*{0xf8000a18, 0xf8000a2a} ==> 40 WBRXK (CMD = 10)*/ /*{0xf8000b18, 0xf8000b2a} ==> 80 WBRXK (CMD = 11)*/ - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); - odm_write_4byte(p_dm_odm, 0x1b24, (odm_read_4byte(p_dm_odm, 0x1b24) & 0xffffe3ff) | ((p_iqk_info->lna_idx & 0x7) << 10)); + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0xffffe3ff) | ((iqk_info->lna_idx & 0x7) << 10)); } - odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD); - odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD + 0x1); + odm_write_4byte(dm, 0x1b00, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1); ODM_delay_ms(WBIQK_delay_8822B); - fail = _iqk_check_cal_8822b(p_dm_odm, path, 0x1); - - if (p_dm_odm->debug_components && ODM_COMP_CALIBRATION) { - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]S%d ==> 0x1b00 = 0x%x, 0x1b08 = 0x%x\n", path, odm_read_4byte(p_dm_odm, 0x1b00), odm_read_4byte(p_dm_odm, 0x1b08))); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]S%d ==> delay_count = 0x%x\n", path, delay_count)); + fail = _iqk_check_cal_8822b(dm, path, 0x1); + + if (dm->debug_components & ODM_COMP_CALIBRATION) { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]S%d ==> 0x1b00 = 0x%x, 0x1b08 = 0x%x\n", path, odm_read_4byte(dm, 0x1b00), odm_read_4byte(dm, 0x1b08)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]S%d ==> delay_count = 0x%x\n", path, delay_count); if (idx != TXIQK) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]S%d ==> RF0x0 = 0x%x, RF0x56 = 0x%x\n", path, odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x0, RFREGOFFSETMASK), - odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK))); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]S%d ==> RF0x0 = 0x%x, RF0x56 = 0x%x\n", path, odm_get_rf_reg(dm, (enum rf_path)path, 0x0, RFREGOFFSETMASK), + odm_get_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK)); } - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); if (idx == TXIQK) { if (fail) - odm_set_bb_reg(p_dm_odm, iqk_apply[path], BIT(0), 0x0); + odm_set_bb_reg(dm, iqk_apply[path], BIT(0), 0x0); else - _iqk_backup_iqk_8822b(p_dm_odm, 0x2, path); + _iqk_backup_iqk_8822b(dm, 0x2, path); } if (idx == RXIQK2) { - p_iqk_info->RXIQK_AGC[0][path] = - (u16)(((odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x0, RFREGOFFSETMASK) >> 5) & 0xff) | - (p_iqk_info->tmp1bcc << 8)); + iqk_info->rxiqk_agc[0][path] = + (u16)(((odm_get_rf_reg(dm, (enum rf_path)path, 0x0, RFREGOFFSETMASK) >> 5) & 0xff) | + (iqk_info->tmp1bcc << 8)); - odm_write_4byte(p_dm_odm, 0x1b38, 0x20000000); + odm_write_4byte(dm, 0x1b38, 0x20000000); if (fail) - odm_set_bb_reg(p_dm_odm, iqk_apply[path], (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(dm, iqk_apply[path], (BIT(11) | BIT(10)), 0x0); else - _iqk_backup_iqk_8822b(p_dm_odm, 0x3, path); + _iqk_backup_iqk_8822b(dm, 0x3, path); } if (idx == TXIQK) - p_iqk_info->IQK_fail_report[0][path][TXIQK] = fail; + iqk_info->iqk_fail_report[0][path][TXIQK] = fail; else - p_iqk_info->IQK_fail_report[0][path][RXIQK] = fail; + iqk_info->iqk_fail_report[0][path][RXIQK] = fail; return fail; } @@ -970,85 +999,89 @@ _iqk_one_shot_8822b( boolean _iqk_rx_iqk_by_path_8822b( - void *p_dm_void, + void *dm_void, u8 path ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; boolean KFAIL = true, gonext; #if 1 - switch (p_iqk_info->rxiqk_step) { + switch (iqk_info->rxiqk_step) { case 1: /*gain search_RXK1*/ - _iqk_rxk1_setting_8822b(p_dm_odm, path); + _iqk_rxk1_setting_8822b(dm, path); gonext = false; while (1) { - KFAIL = _iqk_rx_iqk_gain_search_fail_8822b(p_dm_odm, path, RXIQK1); - if (KFAIL && (p_iqk_info->gs_retry_count[0][path][RXIQK1] < 2)) - p_iqk_info->gs_retry_count[0][path][RXIQK1]++; + KFAIL = _iqk_rx_iqk_gain_search_fail_8822b(dm, path, RXIQK1); + if (KFAIL && (iqk_info->gs_retry_count[0][path][0] < 2)) + iqk_info->gs_retry_count[0][path][0]++; else if (KFAIL) { - p_iqk_info->RXIQK_fail_code[0][path] = 0; - p_iqk_info->rxiqk_step = 5; + iqk_info->rxiqk_fail_code[0][path] = 0; + iqk_info->rxiqk_step = 5; gonext = true; } else { - p_iqk_info->rxiqk_step++; + iqk_info->rxiqk_step++; gonext = true; } if (gonext) break; } + halrf_iqk_xym_read(dm, path, 0x2); break; case 2: /*gain search_RXK2*/ - _iqk_rxk2_setting_8822b(p_dm_odm, path, true); - p_iqk_info->isbnd = false; + _iqk_rxk2_setting_8822b(dm, path, true); + iqk_info->isbnd = false; while (1) { - KFAIL = _iqk_rx_iqk_gain_search_fail_8822b(p_dm_odm, path, RXIQK2); - if (KFAIL && (p_iqk_info->gs_retry_count[0][path][RXIQK2] < rxiqk_gs_limit)) - p_iqk_info->gs_retry_count[0][path][RXIQK2]++; + KFAIL = _iqk_rx_iqk_gain_search_fail_8822b(dm, path, RXIQK2); + if (KFAIL && (iqk_info->gs_retry_count[0][path][1] < rxiqk_gs_limit)) + iqk_info->gs_retry_count[0][path][1]++; else { - p_iqk_info->rxiqk_step++; + iqk_info->rxiqk_step++; break; } } + halrf_iqk_xym_read(dm, path, 0x3); break; case 3: /*RXK1*/ - _iqk_rxk1_setting_8822b(p_dm_odm, path); + _iqk_rxk1_setting_8822b(dm, path); gonext = false; while (1) { - KFAIL = _iqk_one_shot_8822b(p_dm_odm, path, RXIQK1); - if (KFAIL && (p_iqk_info->retry_count[0][path][RXIQK1] < 2)) - p_iqk_info->retry_count[0][path][RXIQK1]++; + KFAIL = _iqk_one_shot_8822b(dm, path, RXIQK1); + if (KFAIL && (iqk_info->retry_count[0][path][RXIQK1] < 2)) + iqk_info->retry_count[0][path][RXIQK1]++; else if (KFAIL) { - p_iqk_info->RXIQK_fail_code[0][path] = 1; - p_iqk_info->rxiqk_step = 5; + iqk_info->rxiqk_fail_code[0][path] = 1; + iqk_info->rxiqk_step = 5; gonext = true; } else { - p_iqk_info->rxiqk_step++; + iqk_info->rxiqk_step++; gonext = true; } if (gonext) break; } + halrf_iqk_xym_read(dm, path, 0x4); break; case 4: /*RXK2*/ - _iqk_rxk2_setting_8822b(p_dm_odm, path, false); + _iqk_rxk2_setting_8822b(dm, path, false); gonext = false; while (1) { - KFAIL = _iqk_one_shot_8822b(p_dm_odm, path, RXIQK2); - if (KFAIL && (p_iqk_info->retry_count[0][path][RXIQK2] < 2)) - p_iqk_info->retry_count[0][path][RXIQK2]++; + KFAIL = _iqk_one_shot_8822b(dm, path, RXIQK2); + if (KFAIL && (iqk_info->retry_count[0][path][RXIQK2] < 2)) + iqk_info->retry_count[0][path][RXIQK2]++; else if (KFAIL) { - p_iqk_info->RXIQK_fail_code[0][path] = 2; - p_iqk_info->rxiqk_step = 5; + iqk_info->rxiqk_fail_code[0][path] = 2; + iqk_info->rxiqk_step = 5; gonext = true; } else { - p_iqk_info->rxiqk_step++; + iqk_info->rxiqk_step++; gonext = true; } if (gonext) break; } + halrf_iqk_xym_read(dm, path, 0x0); break; } return KFAIL; @@ -1058,131 +1091,123 @@ _iqk_rx_iqk_by_path_8822b( void _iqk_iqk_by_path_8822b( - void *p_dm_void, + void *dm_void, boolean segment_iqk ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; boolean KFAIL = true; u8 i, kcount_limit; - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]iqk_step = 0x%x\n", p_dm_odm->rf_calibrate_info.iqk_step)); */ + /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]iqk_step = 0x%x\n", dm->rf_calibrate_info.iqk_step); */ - if (*p_dm_odm->p_band_width == 2) + if (*dm->band_width == 2) kcount_limit = kcount_limit_80m; else kcount_limit = kcount_limit_others; while (1) { #if 1 - switch (p_dm_odm->rf_calibrate_info.iqk_step) { + switch (dm->rf_calibrate_info.iqk_step) { case 1: /*S0 LOK*/ #if 1 - _iqk_lok_setting_8822b(p_dm_odm, ODM_RF_PATH_A); - _lok_one_shot_8822b(p_dm_odm, ODM_RF_PATH_A); + _iqk_lok_setting_8822b(dm, RF_PATH_A); + _lok_one_shot_8822b(dm, RF_PATH_A); #endif - p_dm_odm->rf_calibrate_info.iqk_step++; + dm->rf_calibrate_info.iqk_step++; break; case 2: /*S1 LOK*/ #if 1 - _iqk_lok_setting_8822b(p_dm_odm, ODM_RF_PATH_B); - _lok_one_shot_8822b(p_dm_odm, ODM_RF_PATH_B); + _iqk_lok_setting_8822b(dm, RF_PATH_B); + _lok_one_shot_8822b(dm, RF_PATH_B); #endif - p_dm_odm->rf_calibrate_info.iqk_step++; + dm->rf_calibrate_info.iqk_step++; break; case 3: /*S0 TXIQK*/ #if 1 - _iqk_txk_setting_8822b(p_dm_odm, ODM_RF_PATH_A); - KFAIL = _iqk_one_shot_8822b(p_dm_odm, ODM_RF_PATH_A, TXIQK); - p_iqk_info->kcount++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S0TXK KFail = 0x%x\n", KFAIL)); + _iqk_txk_setting_8822b(dm, RF_PATH_A); + KFAIL = _iqk_one_shot_8822b(dm, RF_PATH_A, TXIQK); + iqk_info->kcount++; + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]S0TXK KFail = 0x%x\n", KFAIL); - if (KFAIL && (p_iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK] < 3)) - p_iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK]++; + if (KFAIL && (iqk_info->retry_count[0][RF_PATH_A][TXIQK] < 3)) + iqk_info->retry_count[0][RF_PATH_A][TXIQK]++; else #endif - p_dm_odm->rf_calibrate_info.iqk_step++; + dm->rf_calibrate_info.iqk_step++; + halrf_iqk_xym_read(dm, RF_PATH_A, 0x1); break; case 4: /*S1 TXIQK*/ #if 1 - _iqk_txk_setting_8822b(p_dm_odm, ODM_RF_PATH_B); - KFAIL = _iqk_one_shot_8822b(p_dm_odm, ODM_RF_PATH_B, TXIQK); - p_iqk_info->kcount++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S1TXK KFail = 0x%x\n", KFAIL)); - if (KFAIL && p_iqk_info->retry_count[0][ODM_RF_PATH_B][TXIQK] < 3) - p_iqk_info->retry_count[0][ODM_RF_PATH_B][TXIQK]++; + _iqk_txk_setting_8822b(dm, RF_PATH_B); + KFAIL = _iqk_one_shot_8822b(dm, RF_PATH_B, TXIQK); + iqk_info->kcount++; + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]S1TXK KFail = 0x%x\n", KFAIL); + if (KFAIL && iqk_info->retry_count[0][RF_PATH_B][TXIQK] < 3) + iqk_info->retry_count[0][RF_PATH_B][TXIQK]++; else #endif - p_dm_odm->rf_calibrate_info.iqk_step++; + dm->rf_calibrate_info.iqk_step++; + halrf_iqk_xym_read(dm, RF_PATH_B, 0x1); break; case 5: /*S0 RXIQK*/ while (1) { - KFAIL = _iqk_rx_iqk_by_path_8822b(p_dm_odm, ODM_RF_PATH_A); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S0RXK KFail = 0x%x\n", KFAIL)); - if (p_iqk_info->rxiqk_step == 5) { - p_dm_odm->rf_calibrate_info.iqk_step++; - p_iqk_info->rxiqk_step = 1; + KFAIL = _iqk_rx_iqk_by_path_8822b(dm, RF_PATH_A); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]S0RXK KFail = 0x%x\n", KFAIL); + if (iqk_info->rxiqk_step == 5) { + dm->rf_calibrate_info.iqk_step++; + iqk_info->rxiqk_step = 1; if (KFAIL) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]S0RXK fail code: %d!!!\n", p_iqk_info->RXIQK_fail_code[0][ODM_RF_PATH_A])); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]S0RXK fail code: %d!!!\n", iqk_info->rxiqk_fail_code[0][RF_PATH_A]); break; } } - p_iqk_info->kcount++; + iqk_info->kcount++; break; case 6: /*S1 RXIQK*/ while (1) { - KFAIL = _iqk_rx_iqk_by_path_8822b(p_dm_odm, ODM_RF_PATH_B); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S1RXK KFail = 0x%x\n", KFAIL)); - if (p_iqk_info->rxiqk_step == 5) { - p_dm_odm->rf_calibrate_info.iqk_step++; - p_iqk_info->rxiqk_step = 1; + KFAIL = _iqk_rx_iqk_by_path_8822b(dm, RF_PATH_B); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]S1RXK KFail = 0x%x\n", KFAIL); + if (iqk_info->rxiqk_step == 5) { + dm->rf_calibrate_info.iqk_step++; + iqk_info->rxiqk_step = 1; if (KFAIL) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]S1RXK fail code: %d!!!\n", p_iqk_info->RXIQK_fail_code[0][ODM_RF_PATH_B])); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]S1RXK fail code: %d!!!\n", iqk_info->rxiqk_fail_code[0][RF_PATH_B]); break; } } - p_iqk_info->kcount++; + iqk_info->kcount++; break; } - if (p_dm_odm->rf_calibrate_info.iqk_step == 7) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]==========LOK summary ==========\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]PathA_LOK_notready = %d, PathB_LOK1_notready = %d\n", - p_iqk_info->LOK_fail[ODM_RF_PATH_A], p_iqk_info->LOK_fail[ODM_RF_PATH_B])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]==========IQK summary ==========\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]PathA_TXIQK_fail = %d, PathB_TXIQK_fail = %d\n", - p_iqk_info->IQK_fail_report[0][ODM_RF_PATH_A][TXIQK], p_iqk_info->IQK_fail_report[0][ODM_RF_PATH_B][TXIQK])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]PathA_RXIQK_fail = %d, PathB_RXIQK_fail = %d\n", - p_iqk_info->IQK_fail_report[0][ODM_RF_PATH_A][RXIQK], p_iqk_info->IQK_fail_report[0][ODM_RF_PATH_B][RXIQK])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]PathA_TXIQK_retry = %d, PathB_TXIQK_retry = %d\n", - p_iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK], p_iqk_info->retry_count[0][ODM_RF_PATH_B][TXIQK])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]PathA_RXK1_retry = %d, PathA_RXK2_retry = %d, PathB_RXK1_retry = %d, PathB_RXK2_retry = %d\n", - p_iqk_info->retry_count[0][ODM_RF_PATH_A][RXIQK1], p_iqk_info->retry_count[0][ODM_RF_PATH_A][RXIQK2], - p_iqk_info->retry_count[0][ODM_RF_PATH_B][RXIQK1], p_iqk_info->retry_count[0][ODM_RF_PATH_B][RXIQK2])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]PathA_GS1_retry = %d, PathA_GS2_retry = %d, PathB_GS1_retry = %d, PathB_GS2_retry = %d\n", - p_iqk_info->gs_retry_count[0][ODM_RF_PATH_A][RXIQK1], p_iqk_info->gs_retry_count[0][ODM_RF_PATH_A][RXIQK2], - p_iqk_info->gs_retry_count[0][ODM_RF_PATH_B][RXIQK1], p_iqk_info->gs_retry_count[0][ODM_RF_PATH_B][RXIQK2])); + if (dm->rf_calibrate_info.iqk_step == 7) { + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]==========LOK summary ==========\n"); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]PathA_LOK_notready = %d, PathB_LOK1_notready = %d\n", + iqk_info->lok_fail[RF_PATH_A], iqk_info->lok_fail[RF_PATH_B]); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]==========IQK summary ==========\n"); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]PathA_TXIQK_fail = %d, PathB_TXIQK_fail = %d\n", + iqk_info->iqk_fail_report[0][RF_PATH_A][TXIQK], iqk_info->iqk_fail_report[0][RF_PATH_B][TXIQK]); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]PathA_RXIQK_fail = %d, PathB_RXIQK_fail = %d\n", + iqk_info->iqk_fail_report[0][RF_PATH_A][RXIQK], iqk_info->iqk_fail_report[0][RF_PATH_B][RXIQK]); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]PathA_TXIQK_retry = %d, PathB_TXIQK_retry = %d\n", + iqk_info->retry_count[0][RF_PATH_A][TXIQK], iqk_info->retry_count[0][RF_PATH_B][TXIQK]); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]PathA_RXK1_retry = %d, PathA_RXK2_retry = %d, PathB_RXK1_retry = %d, PathB_RXK2_retry = %d\n", + iqk_info->retry_count[0][RF_PATH_A][RXIQK1], iqk_info->retry_count[0][RF_PATH_A][RXIQK2], + iqk_info->retry_count[0][RF_PATH_B][RXIQK1], iqk_info->retry_count[0][RF_PATH_B][RXIQK2]); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]PathA_GS1_retry = %d, PathA_GS2_retry = %d, PathB_GS1_retry = %d, PathB_GS2_retry = %d\n", + iqk_info->gs_retry_count[0][RF_PATH_A][0], iqk_info->gs_retry_count[0][RF_PATH_A][1], + iqk_info->gs_retry_count[0][RF_PATH_B][0], iqk_info->gs_retry_count[0][RF_PATH_B][1]); for (i = 0; i < 2; i++) { - odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | i << 1); - odm_write_4byte(p_dm_odm, 0x1b2c, 0x7); - odm_write_4byte(p_dm_odm, 0x1bcc, 0x0); - odm_write_4byte(p_dm_odm, 0x1b38, 0x20000000); + odm_write_4byte(dm, 0x1b00, 0xf8000008 | i << 1); + odm_write_4byte(dm, 0x1b2c, 0x7); + odm_write_4byte(dm, 0x1bcc, 0x0); + odm_write_4byte(dm, 0x1b38, 0x20000000); } break; } - if ((segment_iqk == true) && (p_iqk_info->kcount == kcount_limit)) + if (segment_iqk && (iqk_info->kcount == kcount_limit)) break; #endif } @@ -1190,294 +1215,597 @@ _iqk_iqk_by_path_8822b( void _iqk_start_iqk_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, boolean segment_iqk ) { u32 tmp; /*GNT_WL = 1*/ - tmp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK); + tmp = odm_get_rf_reg(dm, RF_PATH_A, 0x1, RFREGOFFSETMASK); tmp = tmp | BIT(5) | BIT(0); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK, tmp); + odm_set_rf_reg(dm, RF_PATH_A, 0x1, RFREGOFFSETMASK, tmp); - tmp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x1, RFREGOFFSETMASK); + tmp = odm_get_rf_reg(dm, RF_PATH_B, 0x1, RFREGOFFSETMASK); tmp = tmp | BIT(5) | BIT(0); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x1, RFREGOFFSETMASK, tmp); + odm_set_rf_reg(dm, RF_PATH_B, 0x1, RFREGOFFSETMASK, tmp); - _iqk_iqk_by_path_8822b(p_dm_odm, segment_iqk); + _iqk_iqk_by_path_8822b(dm, segment_iqk); } void _iq_calibrate_8822b_init( - void *p_dm_void + struct dm_struct *dm ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_iqk_info *iqk_info = &dm->IQK_info; u8 i, j, k, m; + static boolean firstrun = true; - if (p_iqk_info->iqk_times == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]=====>PHY_IQCalibrate_8822B_Init\n")); + if (firstrun) { + firstrun = false; + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]=====>PHY_IQCalibrate_8822B_Init\n"); for (i = 0; i < SS_8822B; i++) { for (j = 0; j < 2; j++) { - p_iqk_info->LOK_fail[i] = true; - p_iqk_info->IQK_fail[j][i] = true; - p_iqk_info->iqc_matrix[j][i] = 0x20000000; + iqk_info->lok_fail[i] = true; + iqk_info->iqk_fail[j][i] = true; + iqk_info->iqc_matrix[j][i] = 0x20000000; } } for (i = 0; i < 2; i++) { - p_iqk_info->iqk_channel[i] = 0x0; + iqk_info->iqk_channel[i] = 0x0; for (j = 0; j < SS_8822B; j++) { - p_iqk_info->LOK_IDAC[i][j] = 0x0; - p_iqk_info->RXIQK_AGC[i][j] = 0x0; - p_iqk_info->bypass_iqk[i][j] = 0x0; + iqk_info->lok_idac[i][j] = 0x0; + iqk_info->rxiqk_agc[i][j] = 0x0; + iqk_info->bypass_iqk[i][j] = 0x0; for (k = 0; k < 2; k++) { - p_iqk_info->IQK_fail_report[i][j][k] = true; + iqk_info->iqk_fail_report[i][j][k] = true; for (m = 0; m < 8; m++) { - p_iqk_info->IQK_CFIR_real[i][j][k][m] = 0x0; - p_iqk_info->IQK_CFIR_imag[i][j][k][m] = 0x0; + iqk_info->iqk_cfir_real[i][j][k][m] = 0x0; + iqk_info->iqk_cfir_imag[i][j][k][m] = 0x0; } } for (k = 0; k < 3; k++) - p_iqk_info->retry_count[i][j][k] = 0x0; + iqk_info->retry_count[i][j][k] = 0x0; } } } + /*parameters init.*/ /*cu_distance (IQK result variation)=111*/ - odm_write_4byte(p_dm_odm, 0x1b10, 0x88011c00); + odm_write_4byte(dm, 0x1b10, 0x88011c00); +} + + + +boolean +_iqk_rximr_rxk1_test_8822b( + struct dm_struct *dm, + u8 path, + u32 tone_index +) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + boolean fail = true; + u32 IQK_CMD ; + + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1b20, (odm_read_4byte(dm, 0x1b20) & 0x000fffff) | ((tone_index & 0xfff)<<20)); + odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0x000fffff) | ((tone_index & 0xfff)<<20)); + + IQK_CMD = 0xf8000208 | (1 << (path + 4)); + odm_write_4byte(dm, 0x1b00, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1); + + ODM_delay_ms(GS_delay_8822B); + fail = _iqk_check_cal_8822b(dm, path, 0x1); + return fail; } +u32 +_iqk_tximr_selfcheck_8822b( + void *dm_void, + u8 tone_index, + u8 path +) +{ + u32 tx_ini_power_H[2], tx_ini_power_L[2]; + u32 tmp1, tmp2, tmp3, tmp4, tmp5; + u32 IQK_CMD; + u32 tximr = 0x0; + u8 i; + + struct dm_struct *dm = (struct dm_struct *)dm_void; +/*backup*/ + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1bc8, 0x80000000); + odm_write_4byte(dm, 0x8f8, 0x41400080); + tmp1 = odm_read_4byte(dm, 0x1b0c); + tmp2 = odm_read_4byte(dm, 0x1b14); + tmp3 = odm_read_4byte(dm, 0x1b1c); + tmp4 = odm_read_4byte(dm, 0x1b20); + tmp5 = odm_read_4byte(dm, 0x1b24); +/*setup*/ + odm_write_4byte(dm, 0x1b0c, 0x00003000); + odm_write_4byte(dm, 0x1b1c, 0xA2193C32); + odm_write_1byte(dm, 0x1b15, 0x00); + odm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008)); + odm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060008)); + odm_write_4byte(dm, 0x1b2c, 0x07); + odm_write_4byte(dm, 0x1b38, 0x20000000); + odm_write_4byte(dm, 0x1b3c, 0x20000000); +/* ======derive pwr1========*/ + for (i = 0; i < 2; i++) { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + if (i == 0) + odm_write_4byte(dm, 0x1bcc, 0x0f); + else + odm_write_4byte(dm, 0x1bcc, 0x09); +/* One Shot*/ + IQK_CMD = 0x00000800; + odm_write_4byte(dm, 0x1b34, IQK_CMD+1); + odm_write_4byte(dm, 0x1b34, IQK_CMD); + ODM_delay_ms(1); + odm_write_4byte(dm, 0x1bd4, 0x00040001); + tx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc); + odm_write_4byte(dm, 0x1bd4, 0x000C0001); + tx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc); + } +/*restore*/ + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1b0c, tmp1); + odm_write_4byte(dm, 0x1b14, tmp2); + odm_write_4byte(dm, 0x1b1c, tmp3); + odm_write_4byte(dm, 0x1b20, tmp4); + odm_write_4byte(dm, 0x1b24, tmp5); + + if (tx_ini_power_H[1] == tx_ini_power_H[0]) + tximr = (3*(halrf_psd_log2base(tx_ini_power_L[0] << 2) - halrf_psd_log2base(tx_ini_power_L[1])))/100; + else + tximr = 0; + return tximr; +} void -_phy_iq_calibrate_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - boolean reset +_iqk_start_tximr_test_8822b( + struct dm_struct *dm, + u8 imr_limit + ) +{ + boolean KFAIL; + u8 path, i, tone_index; + u32 imr_result; + + for (path = 0; path < 2; path++) { + _iqk_txk_setting_8822b(dm, path); + KFAIL = _iqk_one_shot_8822b(dm, path, TXIQK); + for (i = 0x0; i < imr_limit; i++) { + tone_index = (u8)(0x08|i<<4); + imr_result = _iqk_tximr_selfcheck_8822b(dm, tone_index, path); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]path=%x, toneindex = %x, TXIMR = %d\n", path, tone_index, imr_result); + } + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "\n"); + } +} + +u32 +_iqk_rximr_selfcheck_8822b( + void *dm_void, + u32 tone_index, + u8 path, + u32 tmp1b38 ) { + u32 rx_ini_power_H[2], rx_ini_power_L[2];/*[0]: psd tone; [1]: image tone*/ + u32 tmp1, tmp2, tmp3, tmp4, tmp5; + u32 IQK_CMD, tmp1bcc; + u8 i, num_k1, rximr_step, count = 0x0; + u32 rximr = 0x0; + boolean KFAIL = true; + + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + /*backup*/ + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + tmp1 = odm_read_4byte(dm, 0x1b0c); + tmp2 = odm_read_4byte(dm, 0x1b14); + tmp3 = odm_read_4byte(dm, 0x1b1c); + tmp4 = odm_read_4byte(dm, 0x1b20); + tmp5 = odm_read_4byte(dm, 0x1b24); + + odm_write_4byte(dm, 0x1b0c, 0x00001000); + odm_write_1byte(dm, 0x1b15, 0x00); + odm_write_4byte(dm, 0x1b1c, 0x82193d31); + odm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008)); + odm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060048)); + odm_write_4byte(dm, 0x1b2c, 0x07); + odm_write_4byte(dm, 0x1b38, tmp1b38); + odm_write_4byte(dm, 0x1b3c, 0x20000000); + + for (i = 0; i < 2; i++) { + if (i == 0) + odm_write_4byte(dm, 0x1b1c, 0x82193d31); + else + odm_write_4byte(dm, 0x1b1c, 0xa2193d31); + IQK_CMD = 0x00000800; + odm_write_4byte(dm, 0x1b34, IQK_CMD + 1); + odm_write_4byte(dm, 0x1b34, IQK_CMD); + ODM_delay_ms(2); + odm_write_1byte(dm, 0x1bd6, 0xb); + while (count < 100) { + count++; + if(odm_get_bb_reg(dm, 0x1bfc, BIT(1)) == 1) + break; + else + ODM_delay_ms(1); + } + if (1) { + odm_write_1byte(dm, 0x1bd6, 0x5); + rx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc); + odm_write_1byte(dm, 0x1bd6, 0xe); + rx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc); + } else { + rx_ini_power_H[i] = 0x0; + rx_ini_power_L[i] = 0x0; + } + } + /*restore*/ + odm_write_4byte(dm, 0x1b0c, tmp1); + odm_write_4byte(dm, 0x1b14, tmp2); + odm_write_4byte(dm, 0x1b1c, tmp3); + odm_write_4byte(dm, 0x1b20, tmp4); + odm_write_4byte(dm, 0x1b24, tmp5); + for (i = 0 ; i < 2; i++) + rx_ini_power_H[i] = (rx_ini_power_H[i] & 0xf8000000)>>27; + + if (rx_ini_power_H[0] != rx_ini_power_H[1]) { + switch (rx_ini_power_H[0]) { + case 1: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>1) | 0x80000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>1; + break; + case 2: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>2) | 0x80000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>2; + break; + case 3: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>2) | 0xc0000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>2; + break; + case 4: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>3) | 0x80000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>3; + break; + case 5: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>3) | 0xa0000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>3; + break; + case 6: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>3) | 0xc0000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>3; + break; + case 7: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>3) | 0xe0000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>3; + break; + default: + break; + } + } + rximr = (u32)(3*((halrf_psd_log2base(rx_ini_power_L[0]/100) - halrf_psd_log2base(rx_ini_power_L[1]/100)))/100); + return rximr; +} + + +void +_iqk_rximr_test_8822b( + struct dm_struct *dm, + u8 path, + u8 imr_limit + ) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + boolean kfail; + u8 i, step, count, side; + u32 imr_result = 0, tone_index; + u32 temp = 0, temp1b38[2][15]; + char *freq[15]= {"1.25MHz", "3.75MHz", "6.25MHz", "8.75MHz", "11.25MHz", + "13.75MHz", "16.25MHz", "18.75MHz", "21.25MHz", "23.75MHz", + "26.25MHz", "28.75MHz", "31.25MHz", "33.75MHz", "36.25MHz"}; + + for (step = 1; step < 5; step++) { + count = 0; + switch (step) { + case 1: /*gain search_RXK1*/ + _iqk_rxk1_setting_8822b(dm, path); + while (count < 3) { + kfail = _iqk_rx_iqk_gain_search_fail_8822b(dm, path, RXIQK1); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]path = %x, kfail = %x\n", path, kfail); + if (kfail) { + count++; + if (count == 3) + step = 5; + } else { + break; + } + } + break; + case 2: /*gain search_RXK2*/ + _iqk_rxk2_setting_8822b(dm, path, true); + iqk_info->isbnd = false; + while (count < 8) { + kfail = _iqk_rx_iqk_gain_search_fail_8822b(dm, path, RXIQK2); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]path = %x, kfail = %x\n", path, kfail); + if (kfail) { + count++; + if (count == 8) + step = 5; + } else { + break; + } + } + break; + case 3: /*get RXK1 IQC*/ + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + temp = odm_read_4byte(dm, 0x1b1c); + for (side =0; side < 2; side++) { + for (i = 0; i < imr_limit; i++) { + if (side ==0) + tone_index = 0xff8 -(i<<4); + else + tone_index = 0x08 | (i<<4); + while (count < 3) { + _iqk_rxk1_setting_8822b(dm, path); + kfail = _iqk_rximr_rxk1_test_8822b(dm, path, tone_index); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]path = %x, kfail = %x\n", path, kfail); + if (kfail) { + count++; + if (count == 3) { + step = 5; + temp1b38[side][i] = 0x20000000; + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]path = %x, toneindex = %x rxk1 fail\n", path, tone_index); + } + } else { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1b1c, 0xa2193c32); + odm_write_4byte(dm, 0x1b14, 0xe5); + odm_write_4byte(dm, 0x1b14, 0x0); + temp1b38[side][i] = odm_read_4byte(dm, 0x1b38); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]path = 0x%x, tone_idx = 0x%x, tmp1b38 = 0x%x\n", path, tone_index, temp1b38[side][i]); + break; + } + } + } + } + break; + case 4: /*get RX IMR*/ + for (side =0; side < 2; side++) { + for (i = 0x0; i < imr_limit; i++) { + if (side ==0) + tone_index = 0xff8 -(i<<4); + else + tone_index = 0x08 | (i<<4); + _iqk_rxk2_setting_8822b(dm, path, false); + imr_result = _iqk_rximr_selfcheck_8822b(dm, tone_index, path, temp1b38[side][i]); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]tone_idx = 0x%5x, freq = %s%10s, RXIMR = %5d dB\n", tone_index, (side ==0)?"-":" ", freq[i], imr_result); + } + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1b1c, temp); + odm_write_4byte(dm, 0x1b38, 0x20000000); + } + break; + } + } +} + + +void +_iqk_start_rximr_test_8822b( + struct dm_struct *dm, + u8 imr_limit + ) +{ + u8 path; + + for (path = 0; path < 2; path++) + _iqk_rximr_test_8822b(dm, path, imr_limit); +} + +void +_iqk_start_imr_test_8822b( + void *dm_void + ) +{ + u8 imr_limit; + + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (*dm->band_width == 2) + imr_limit = 0xf; + else if (*dm->band_width == 1) + imr_limit = 0x8; + else + imr_limit = 0x4; +// _iqk_start_tximr_test_8822b(dm, imr_limit); + _iqk_start_rximr_test_8822b(dm, imr_limit); +} + + +void +_phy_iq_calibrate_8822b( + struct dm_struct *dm, + boolean reset, + boolean segment_iqk +) +{ u32 MAC_backup[MAC_REG_NUM_8822B], BB_backup[BB_REG_NUM_8822B], RF_backup[RF_REG_NUM_8822B][SS_8822B]; u32 backup_mac_reg[MAC_REG_NUM_8822B] = {0x520, 0x550}; - u32 backup_bb_reg[BB_REG_NUM_8822B] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00, 0xeb0, 0xeb4, 0xebc, 0x1990, 0x9a4, 0xa04, 0xb00}; + u32 backup_bb_reg[BB_REG_NUM_8822B] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00, 0xeb0, 0xeb4, 0xebc, 0x1990, 0x9a4, 0xa04, 0xb00, 0x838}; u32 backup_rf_reg[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1}; - boolean segment_iqk = false, is_mp = false; + boolean is_mp = false; - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_iqk_info *iqk_info = &dm->IQK_info; - if (*(p_dm_odm->p_mp_mode)) + if (*dm->mp_mode) is_mp = true; - else if (p_dm_odm->is_linked) - segment_iqk = false; if (!is_mp) - if (_iqk_reload_iqk_8822b(p_dm_odm, reset)) + if (_iqk_reload_iqk_8822b(dm, reset)) return; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]==========IQK strat!!!!!==========\n")); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]p_band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n", (*p_dm_odm->p_band_type == ODM_BAND_5G) ? "5G" : "2G", *p_dm_odm->p_band_width, p_dm_odm->ext_pa, p_dm_odm->ext_pa_5g)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]Interface = %d, cut_version = %x\n", p_dm_odm->support_interface, p_dm_odm->cut_version)); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]==========IQK strat!!!!!==========\n"); - p_iqk_info->iqk_times++; + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n", (*dm->band_type == ODM_BAND_5G) ? "5G" : "2G", *dm->band_width, dm->ext_pa, dm->ext_pa_5g); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]Interface = %d, cut_version = %x\n", dm->support_interface, dm->cut_version); - p_iqk_info->kcount = 0; - p_dm_odm->rf_calibrate_info.iqk_total_progressing_time = 0; - p_dm_odm->rf_calibrate_info.iqk_step = 1; - p_iqk_info->rxiqk_step = 1; + iqk_info->iqk_times++; + iqk_info->kcount = 0; + dm->rf_calibrate_info.iqk_step = 1; + iqk_info->rxiqk_step = 1; - _iqk_backup_iqk_8822b(p_dm_odm, 0x0, 0x0); - _iqk_backup_mac_bb_8822b(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg); - _iqk_backup_rf_8822b(p_dm_odm, RF_backup, backup_rf_reg); + _iqk_backup_iqk_8822b(dm, 0x0, 0x0); + _iqk_backup_mac_bb_8822b(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg); + _iqk_backup_rf_8822b(dm, RF_backup, backup_rf_reg); #if 0 - _iqk_configure_macbb_8822b(p_dm_odm); - _iqk_afe_setting_8822b(p_dm_odm, true); - _iqk_rfe_setting_8822b(p_dm_odm, false); - _iqk_agc_bnd_int_8822b(p_dm_odm); - _iqk_rf_setting_8822b(p_dm_odm); + _iqk_configure_macbb_8822b(dm); + _iqk_afe_setting_8822b(dm, true); + _iqk_rfe_setting_8822b(dm, false); + _iqk_agc_bnd_int_8822b(dm); + _iqk_rf_setting_8822b(dm); #endif while (1) { - if (!is_mp) - p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm); - - _iqk_configure_macbb_8822b(p_dm_odm); - _iqk_afe_setting_8822b(p_dm_odm, true); - _iqk_rfe_setting_8822b(p_dm_odm, false); - _iqk_agc_bnd_int_8822b(p_dm_odm); - _iqk_rf_setting_8822b(p_dm_odm); - - _iqk_start_iqk_8822b(p_dm_odm, segment_iqk); - - _iqk_afe_setting_8822b(p_dm_odm, false); - _iqk_restore_mac_bb_8822b(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg); - _iqk_restore_rf_8822b(p_dm_odm, backup_rf_reg, RF_backup); - - if (!is_mp) { - p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); - p_dm_odm->rf_calibrate_info.iqk_total_progressing_time += odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]IQK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_progressing_time)); - } - - if (p_dm_odm->rf_calibrate_info.iqk_step == 7) + _iqk_configure_macbb_8822b(dm); + _iqk_afe_setting_8822b(dm, true); + _iqk_rfe_setting_8822b(dm, false); + _iqk_agc_bnd_int_8822b(dm); + _iqk_rf_setting_8822b(dm); + _iqk_start_iqk_8822b(dm, segment_iqk); + _iqk_afe_setting_8822b(dm, false); + _iqk_restore_mac_bb_8822b(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg); + _iqk_restore_rf_8822b(dm, backup_rf_reg, RF_backup); + if (dm->rf_calibrate_info.iqk_step == 7) break; - - p_iqk_info->kcount = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]delay 50ms!!!\n")); + iqk_info->kcount = 0; + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]delay 50ms!!!\n"); ODM_delay_ms(50); }; - if (segment_iqk) - _iqk_reload_iqk_setting_8822b(p_dm_odm, 0x0, 0x1); + _iqk_reload_iqk_setting_8822b(dm, 0x0, 0x1); #if 0 - _iqk_afe_setting_8822b(p_dm_odm, false); - _iqk_restore_mac_bb_8822b(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg); - _iqk_restore_rf_8822b(p_dm_odm, backup_rf_reg, RF_backup); + _iqk_afe_setting_8822b(dm, false); + _iqk_restore_mac_bb_8822b(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg); + _iqk_restore_rf_8822b(dm, backup_rf_reg, RF_backup); #endif - _iqk_fill_iqk_report_8822b(p_dm_odm, 0); - - _iqk_rf0xb0_workaround(p_dm_odm); - - if (!is_mp) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Total IQK progressing_time = %lld ms\n", - p_dm_odm->rf_calibrate_info.iqk_total_progressing_time)); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]==========IQK end!!!!!==========\n")); + _iqk_fill_iqk_report_8822b(dm, 0); + _iqk_rf0xb0_workaround(dm); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]==========IQK end!!!!!==========\n"); } void _phy_iq_calibrate_by_fw_8822b( - void *p_dm_void, - u8 clear + void *dm_void, + u8 clear, + u8 segment_iqk ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; enum hal_status status = HAL_STATUS_FAILURE; - u8 segment_iqk = 0x0; - - if (*(p_dm_odm->p_mp_mode)) + + if (*dm->mp_mode) clear = 0x1; - else if (p_dm_odm->is_linked) - segment_iqk = 0x0; +// else if (dm->is_linked) +// segment_iqk = 0x1; - p_iqk_info->iqk_times++; - status = odm_iq_calibrate_by_fw(p_dm_odm, clear, segment_iqk); + iqk_info->iqk_times++; + status = odm_iq_calibrate_by_fw(dm, clear, segment_iqk); if (status == HAL_STATUS_SUCCESS) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]FWIQK OK!!!\n")); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]FWIQK OK!!!\n"); else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]FWIQK fail!!!\n")); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]FWIQK fail!!!\n"); } -/*IQK_version:0x29 NCTL:0x8*/ -/*1.reset bb report*/ -/*2.check if rf0x8 is expected*/ +/*IQK_version:0x2f, NCTL:0x8*/ +/*1.disable CCK block and OFDM CCA block while IQKing*/ void phy_iq_calibrate_8822b( - void *p_dm_void, - boolean clear + void *dm_void, + boolean clear, + boolean segment_iqk ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _hal_rf_ *p_rf = &(p_dm_odm->rf_table); -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) -#else - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); -#endif + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; -#if (MP_DRIVER == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT p_mpt_ctx = &(p_adapter->MptCtx); -#else - PMPT_CONTEXT p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx); -#endif -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (!(p_rf->rf_supportability & HAL_RF_IQK)) - return; -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - if (odm_check_power_status(p_adapter) == false) - return; -#endif - -#if MP_DRIVER == 1 -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (p_mpt_ctx->bSingleTone || p_mpt_ctx->bCarrierSuppression) - return; -#else - if (p_mpt_ctx->is_single_tone || p_mpt_ctx->is_carrier_suppression) - return; -#endif -#endif -#endif - /*p_dm_odm->iqk_fw_offload = 0;*/ + if (*dm->mp_mode) + halrf_iqk_hwtx_check(dm, true); /*FW IQK*/ - if (p_dm_odm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) { - if (!p_dm_odm->rf_calibrate_info.is_iqk_in_progress) { - odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); - p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true; - odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); - - p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm); - _phy_iq_calibrate_by_fw_8822b(p_dm_odm, clear); - phydm_get_read_counter(p_dm_odm); - p_dm_odm->rf_calibrate_info.iqk_total_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_total_progressing_time)); - - odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); - p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false; - odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); - } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); - + if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) { + _phy_iq_calibrate_by_fw_8822b(dm, clear, (u8)(segment_iqk)); + phydm_get_read_counter(dm); + halrf_iqk_check_if_reload(dm); } else { - _iq_calibrate_8822b_init(p_dm_void); - if (!p_dm_odm->rf_calibrate_info.is_iqk_in_progress) { - odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); - p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true; - odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); - - if (*(p_dm_odm->p_mp_mode)) - p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm); -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - _phy_iq_calibrate_8822b(p_dm_odm, clear); - /*DBG_871X("%s,%d, do IQK %u ms\n", __func__, __LINE__, rtw_get_passing_time_ms(time_iqk));*/ -#else - _phy_iq_calibrate_8822b(p_dm_odm, clear); -#endif - if (*(p_dm_odm->p_mp_mode)) { - p_dm_odm->rf_calibrate_info.iqk_total_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_total_progressing_time)); - } - - odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); - p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false; - odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); - } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]== Return the IQK CMD, because the IQK in Progress ==\n")); + _iq_calibrate_8822b_init(dm); + _phy_iq_calibrate_8822b(dm, clear, segment_iqk); } + _iqk_fail_count_8822b(dm); + if (*dm->mp_mode) + halrf_iqk_hwtx_check(dm, false); #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - _iqk_iqk_fail_report_8822b(p_dm_odm); + _iqk_iqk_fail_report_8822b(dm); #endif + halrf_iqk_dbg(dm); } +void +_phy_imr_measure( + struct dm_struct *dm +) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u32 MAC_backup[MAC_REG_NUM_8822B], BB_backup[BB_REG_NUM_8822B], RF_backup[RF_REG_NUM_8822B][SS_8822B]; + u32 backup_mac_reg[MAC_REG_NUM_8822B] = {0x520, 0x550}; + u32 backup_bb_reg[BB_REG_NUM_8822B] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00, 0xeb0, 0xeb4, 0xebc, 0x1990, 0x9a4, 0xa04, 0xb00}; + u32 backup_rf_reg[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1}; + + _iqk_backup_iqk_8822b(dm, 0x0, 0x0); + _iqk_backup_mac_bb_8822b(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg); + _iqk_backup_rf_8822b(dm, RF_backup, backup_rf_reg); + _iqk_configure_macbb_8822b(dm); + _iqk_afe_setting_8822b(dm, true); + _iqk_rfe_setting_8822b(dm, false); + _iqk_agc_bnd_int_8822b(dm); + _iqk_rf_setting_8822b(dm); + + _iqk_start_imr_test_8822b(dm); + + _iqk_afe_setting_8822b(dm, false); + _iqk_restore_mac_bb_8822b(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg); + _iqk_restore_rf_8822b(dm, backup_rf_reg, RF_backup); +} + +void +do_imr_test_8822b( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK] ************IMR Test *****************\n"); + _phy_imr_measure(dm); + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK] **********End IMR Test *******************\n"); +} #endif diff --git a/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h index 9f5de92..3ec83e3 100644 --- a/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h +++ b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,24 +8,28 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ + #ifndef __PHYDM_IQK_8822B_H__ #define __PHYDM_IQK_8822B_H__ #if (RTL8822B_SUPPORT == 1) - -#define IQK_VERSION_8822B "0x28" /*--------------------------Define Parameters-------------------------------*/ #define MAC_REG_NUM_8822B 2 -#define BB_REG_NUM_8822B 14 +#define BB_REG_NUM_8822B 15 #define RF_REG_NUM_8822B 5 #define LOK_delay_8822B 2 #define GS_delay_8822B 2 @@ -38,7 +42,7 @@ #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) void do_iqk_8822b( - void *p_dm_void, + void *dm_void, u8 delta_thermal_index, u8 thermal_value, u8 threshold @@ -46,7 +50,7 @@ do_iqk_8822b( #else void do_iqk_8822b( - void *p_dm_void, + void *dm_void, u8 delta_thermal_index, u8 thermal_value, u8 threshold @@ -55,13 +59,19 @@ do_iqk_8822b( void phy_iq_calibrate_8822b( - void *p_dm_void, - boolean clear + void *dm_void, + boolean clear, + boolean segment_iqk +); + +void +do_imr_test_8822b( + void *dm_void ); #else /* (RTL8822B_SUPPORT == 0)*/ -#define phy_iq_calibrate_8822b(_pdm_void, clear) +#define phy_iq_calibrate_8822b(_pdm_void, clear, segment_iqk) #endif /* RTL8822B_SUPPORT */ diff --git a/hal/phydm/mp_precomp.h b/hal/phydm/mp_precomp.h index 99ca5f4..897adc1 100644 --- a/hal/phydm/mp_precomp.h +++ b/hal/phydm/mp_precomp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,7 +8,17 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ diff --git a/hal/phydm/phydm.c b/hal/phydm/phydm.c index e8b6983..77c044a 100644 --- a/hal/phydm/phydm.c +++ b/hal/phydm/phydm.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -20,20 +30,6 @@ #include "mp_precomp.h" #include "phydm_precomp.h" -const u16 db_invert_table[12][8] = { - { 1, 1, 1, 2, 2, 2, 2, 3}, - { 3, 3, 4, 4, 4, 5, 6, 6}, - { 7, 8, 9, 10, 11, 13, 14, 16}, - { 18, 20, 22, 25, 28, 32, 35, 40}, - { 45, 50, 56, 63, 71, 79, 89, 100}, - { 112, 126, 141, 158, 178, 200, 224, 251}, - { 282, 316, 355, 398, 447, 501, 562, 631}, - { 708, 794, 891, 1000, 1122, 1259, 1413, 1585}, - { 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, - { 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000}, - { 11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119}, - { 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} -}; const u16 phy_rate_table[] = { /*20M*/ 1, 2, 5, 11, @@ -42,727 +38,381 @@ const u16 phy_rate_table[] = { /*20M*/ 13, 26, 39, 52, 78, 104, 117, 130 /*MCS8~15*/ }; -/* ************************************************************ - * Local Function predefine. - * ************************************************************ */ - -/* START------------COMMON INFO RELATED--------------- */ - -void -odm_global_adapter_check( - void -); - -/* move to odm_PowerTacking.h by YuChen */ - - - -void -odm_update_power_training_state( - struct PHY_DM_STRUCT *p_dm_odm -); - -/* ************************************************************ - * 3 Export Interface - * ************************************************************ */ - -/*Y = 10*log(X)*/ -s32 -odm_pwdb_conversion( - s32 X, - u32 total_bit, - u32 decimal_bit -) -{ - s32 Y, integer = 0, decimal = 0; - u32 i; - - if (X == 0) - X = 1; /* log2(x), x can't be 0 */ - - for (i = (total_bit - 1); i > 0; i--) { - if (X & BIT(i)) { - integer = i; - if (i > 0) - decimal = (X & BIT(i - 1)) ? 2 : 0; /* decimal is 0.5dB*3=1.5dB~=2dB */ - break; - } - } - - Y = 3 * (integer - decimal_bit) + decimal; /* 10*log(x)=3*log2(x), */ - - return Y; -} - -s32 -odm_sign_conversion( - s32 value, - u32 total_bit -) -{ - if (value & BIT(total_bit - 1)) - value -= BIT(total_bit); - return value; -} - -void -phydm_seq_sorting( - void *p_dm_void, - u32 *p_value, - u32 *rank_idx, - u32 *p_idx_out, - u8 seq_length -) -{ - u8 i = 0, j = 0; - u32 tmp_a, tmp_b; - u32 tmp_idx_a, tmp_idx_b; - - for (i = 0; i < seq_length; i++) { - rank_idx[i] = i; - /**/ - } - - for (i = 0; i < (seq_length - 1); i++) { - - for (j = 0; j < (seq_length - 1 - i); j++) { - - tmp_a = p_value[j]; - tmp_b = p_value[j + 1]; - - tmp_idx_a = rank_idx[j]; - tmp_idx_b = rank_idx[j + 1]; - - if (tmp_a < tmp_b) { - p_value[j] = tmp_b; - p_value[j + 1] = tmp_a; - - rank_idx[j] = tmp_idx_b; - rank_idx[j + 1] = tmp_idx_a; - } - } - } - - for (i = 0; i < seq_length; i++) { - p_idx_out[rank_idx[i]] = i + 1; - /**/ - } - - - -} - -#if 0/*(DM_ODM_SUPPORT_TYPE & ODM_WIN)*/ -void -odm_init_mp_driver_status( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - /* Decide when compile time */ - #if (MP_DRIVER == 1) - p_dm_odm->mp_mode = true; - #else - p_dm_odm->mp_mode = false; - #endif - - odm_cmn_info_hook(p_dm_odm, ODM_CMNINFO_MP_MODE, &(p_dm_odm->mp_mode)); -} -#endif - -void -phydm_init_trx_antenna_setting( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - /*#if (RTL8814A_SUPPORT == 1)*/ - - if (p_dm_odm->support_ic_type & (ODM_RTL8814A)) { - u8 rx_ant = 0, tx_ant = 0; - - rx_ant = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_RX_PATH, p_dm_odm), ODM_BIT(BB_RX_PATH, p_dm_odm)); - tx_ant = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_TX_PATH, p_dm_odm), ODM_BIT(BB_TX_PATH, p_dm_odm)); - p_dm_odm->tx_ant_status = (tx_ant & 0xf); - p_dm_odm->rx_ant_status = (rx_ant & 0xf); - } else if (p_dm_odm->support_ic_type & (ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B)) {/* JJ ADD 20161014 */ - p_dm_odm->tx_ant_status = 0x1; - p_dm_odm->rx_ant_status = 0x1; - - } - /*#endif*/ -} - void phydm_traffic_load_decision( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 bit_shift_num = 0; /*---TP & Trafic-load calculation---*/ - if (p_dm_odm->last_tx_ok_cnt > (*(p_dm_odm->p_num_tx_bytes_unicast))) - p_dm_odm->last_tx_ok_cnt = (*(p_dm_odm->p_num_tx_bytes_unicast)); + if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast) + dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast; - if (p_dm_odm->last_rx_ok_cnt > (*(p_dm_odm->p_num_rx_bytes_unicast))) - p_dm_odm->last_rx_ok_cnt = (*(p_dm_odm->p_num_rx_bytes_unicast)); + if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast) + dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast; - p_dm_odm->cur_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast) - p_dm_odm->last_tx_ok_cnt; - p_dm_odm->cur_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast) - p_dm_odm->last_rx_ok_cnt; - p_dm_odm->last_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast); - p_dm_odm->last_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast); + dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt; + dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt; + dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast; + dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - p_dm_odm->tx_tp = ((p_dm_odm->tx_tp) >> 1) + (u32)(((p_dm_odm->cur_tx_ok_cnt) >> 17) >> 1); /* <<3(8bit), >>20(10^6,M)*/ - p_dm_odm->rx_tp = ((p_dm_odm->rx_tp) >> 1) + (u32)(((p_dm_odm->cur_rx_ok_cnt) >> 17) >> 1); /* <<3(8bit), >>20(10^6,M)*/ -#else - p_dm_odm->tx_tp = ((p_dm_odm->tx_tp) >> 1) + (u32)(((p_dm_odm->cur_tx_ok_cnt) >> 18) >> 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ - p_dm_odm->rx_tp = ((p_dm_odm->rx_tp) >> 1) + (u32)(((p_dm_odm->cur_rx_ok_cnt) >> 18) >> 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ -#endif - p_dm_odm->total_tp = p_dm_odm->tx_tp + p_dm_odm->rx_tp; + bit_shift_num = 17 + (PHYDM_WATCH_DOG_PERIOD - 1); /*AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/ + /*WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/ - if (p_dm_odm->total_tp == 0) - p_dm_odm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD; + dm->tx_tp = ((dm->tx_tp) >> 1) + (u32)(((dm->cur_tx_ok_cnt) >> bit_shift_num) >> 1); + dm->rx_tp = ((dm->rx_tp) >> 1) + (u32)(((dm->cur_rx_ok_cnt) >> bit_shift_num) >> 1); + + dm->total_tp = dm->tx_tp + dm->rx_tp; + + /*[Calculate TX/RX state]*/ + if (dm->tx_tp > (dm->rx_tp << 1)) + dm->txrx_state_all = TX_STATE; + else if (dm->rx_tp > (dm->tx_tp << 1)) + dm->txrx_state_all = RX_STATE; else - p_dm_odm->consecutive_idlel_time = 0; - /* - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n", - p_dm_odm->cur_tx_ok_cnt, p_dm_odm->cur_rx_ok_cnt, p_dm_odm->last_tx_ok_cnt, p_dm_odm->last_rx_ok_cnt)); + dm->txrx_state_all = BI_DIRECTION_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("tx_tp = %d, rx_tp = %d\n", - p_dm_odm->tx_tp, p_dm_odm->rx_tp)); - */ + /*[Calculate consecutive idlel time]*/ + if (dm->total_tp == 0) + dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD; + else + dm->consecutive_idlel_time = 0; - p_dm_odm->pre_traffic_load = p_dm_odm->traffic_load; + /*[Traffic load decision]*/ + dm->pre_traffic_load = dm->traffic_load; - if (p_dm_odm->cur_tx_ok_cnt > 1875000 || p_dm_odm->cur_rx_ok_cnt > 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/ + if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/ - p_dm_odm->traffic_load = TRAFFIC_HIGH; + dm->traffic_load = TRAFFIC_HIGH; /**/ - } else if (p_dm_odm->cur_tx_ok_cnt > 500000 || p_dm_odm->cur_rx_ok_cnt > 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/ + } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/ - p_dm_odm->traffic_load = TRAFFIC_MID; + dm->traffic_load = TRAFFIC_MID; /**/ - } else if (p_dm_odm->cur_tx_ok_cnt > 100000 || p_dm_odm->cur_rx_ok_cnt > 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/ + } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/ - p_dm_odm->traffic_load = TRAFFIC_LOW; + dm->traffic_load = TRAFFIC_LOW; /**/ } else { - - p_dm_odm->traffic_load = TRAFFIC_ULTRA_LOW; + dm->traffic_load = TRAFFIC_ULTRA_LOW; /**/ } + + /* + PHYDM_DBG(dm, DBG_COMMON_FLOW, "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n", + dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt, dm->last_rx_ok_cnt); + + PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", + dm->tx_tp, dm->rx_tp); + */ + } void -phydm_config_ofdm_tx_path( - struct PHY_DM_STRUCT *p_dm_odm, - u32 path +phydm_init_cck_setting( + struct dm_struct *dm ) { -#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) - u8 ofdm_tx_path = 0x33; -#endif - #if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { - - if (path == PHYDM_A) { - odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x81121111); - /**/ - } else if (path == PHYDM_B) { - odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x82221222); - /**/ - } else if (path == PHYDM_AB) { - odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x83321333); - /**/ - } + u32 value_824, value_82c; +#endif + dm->is_cck_high_power = (boolean) odm_get_bb_reg(dm, ODM_REG(CCK_RPT_FORMAT, dm), ODM_BIT(CCK_RPT_FORMAT, dm)); - } -#endif + phydm_config_cck_rx_antenna_init(dm); + phydm_config_cck_rx_path(dm, BB_PATH_A); -#if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & (ODM_RTL8812)) { +#if (RTL8192E_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8192E)) { + /* 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting should be equal or CCK RSSI report may be incorrect */ + value_824 = odm_get_bb_reg(dm, 0x824, BIT(9)); + value_82c = odm_get_bb_reg(dm, 0x82c, BIT(9)); - if (path == PHYDM_A) { - ofdm_tx_path = 0x11; - /**/ - } else if (path == PHYDM_B) { - ofdm_tx_path = 0x22; - /**/ - } else if (path == PHYDM_AB) { - ofdm_tx_path = 0x33; - /**/ - } + if (value_824 != value_82c) + odm_set_bb_reg(dm, 0x82c, BIT(9), value_824); + odm_set_bb_reg(dm, 0xa80, BIT(7), value_824); + dm->cck_agc_report_type = (boolean)value_824; - odm_set_bb_reg(p_dm_odm, 0x80c, 0xff00, ofdm_tx_path); + PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type = (( %d )), ext_lna_gain = (( %d ))\n", dm->cck_agc_report_type, dm->ext_lna_gain); } #endif -} - -void -phydm_config_ofdm_rx_path( - struct PHY_DM_STRUCT *p_dm_odm, - u32 path -) -{ - u8 ofdm_rx_path = 0; - - - if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { -#if (RTL8192E_SUPPORT == 1) - if (path == PHYDM_A) { - ofdm_rx_path = 1; - /**/ - } else if (path == PHYDM_B) { - ofdm_rx_path = 2; - /**/ - } else if (path == PHYDM_AB) { - ofdm_rx_path = 3; - /**/ - } - odm_set_bb_reg(p_dm_odm, 0xC04, 0xff, (((ofdm_rx_path) << 4) | ofdm_rx_path)); - odm_set_bb_reg(p_dm_odm, 0xD04, 0xf, ofdm_rx_path); -#endif - } -#if (RTL8812A_SUPPORT || RTL8822B_SUPPORT) - else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) { +#if ((RTL8703B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8710B_SUPPORT == 1)) + if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + dm->cck_agc_report_type = odm_get_bb_reg(dm, 0x950, BIT(11)) ? 1 : 0; /*1: 4bit LNA, 0: 3bit LNA */ - if (path == PHYDM_A) { - ofdm_rx_path = 1; - /**/ - } else if (path == PHYDM_B) { - ofdm_rx_path = 2; - /**/ - } else if (path == PHYDM_AB) { - ofdm_rx_path = 3; + if (dm->cck_agc_report_type != 1) { + pr_debug("[Warning] 8703B/8723D/8710B CCK should be 4bit LNA, ie. 0x950[11] = 1\n"); /**/ } - - odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, ((ofdm_rx_path << 4) | ofdm_rx_path)); } #endif -} -void -phydm_config_cck_rx_antenna_init( - struct PHY_DM_STRUCT *p_dm_odm -) -{ -#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) { - - /*CCK 2R CCA parameters*/ - odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(18), 1); /*enable 2R Rx path*/ - odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(22), 1); /*enable 2R MRC*/ - odm_set_bb_reg(p_dm_odm, 0xa84, BIT(28), 1); /*1. pdx1[5:0] > 2*PD_lim 2. RXIQ_3 = 0 ( signed )*/ - odm_set_bb_reg(p_dm_odm, 0xa70, BIT(7), 0); /*Concurrent CCA at LSB & USB*/ - odm_set_bb_reg(p_dm_odm, 0xa74, BIT(8), 0); /*RX path diversity enable*/ - odm_set_bb_reg(p_dm_odm, 0xa08, BIT(28), 1); /* r_cck_2nd_sel_eco*/ - odm_set_bb_reg(p_dm_odm, 0xa14, BIT(7), 0); /* r_en_mrc_antsel*/ +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821C) { + dm->cck_new_agc = odm_get_bb_reg(dm, 0xa9c, BIT(17)) ? true : false; /*1: new agc 0: old agc*/ + if (dm->cck_new_agc == 0 && dm->default_rf_set_8821c == SWITCH_TO_BTG) + dm->cck_agc_report_type = 1; } #endif -} - -void -phydm_config_cck_rx_path( - struct PHY_DM_STRUCT *p_dm_odm, - u8 path, - u8 path_div_en -) -{ -#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) - u8 path_div_select = 0; - u8 cck_1_path = 0, cck_2_path = 0; -#endif - -#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) { - - if (path == PHYDM_A) { - path_div_select = 0; - cck_1_path = 0; - cck_2_path = 0; - } else if (path == PHYDM_B) { - path_div_select = 0; - cck_1_path = 1; - cck_2_path = 1; - } else if (path == PHYDM_AB) { - - if (path_div_en == CCA_PATHDIV_ENABLE) - path_div_select = 1; - - cck_1_path = 0; - cck_2_path = 1; - } - - odm_set_bb_reg(p_dm_odm, 0xa04, (BIT(27) | BIT(26)), cck_1_path); - odm_set_bb_reg(p_dm_odm, 0xa04, (BIT(25) | BIT(24)), cck_2_path); - odm_set_bb_reg(p_dm_odm, 0xa74, BIT(8), path_div_select); - - } +#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8710B_SUPPORT == 1)) + if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8710B)) + dm->cck_new_agc = odm_get_bb_reg(dm, 0xa9c, BIT(17)) ? true : false; /*1: new agc 0: old agc*/ + else #endif -} - -void -phydm_config_trx_path( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 used = *_used; - u32 out_len = *_out_len; - - /* CCK */ - if (dm_value[0] == 0) { - - if (dm_value[1] == 1) { /*TX*/ - if (dm_value[2] == 1) - odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x8); - else if (dm_value[2] == 2) - odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x4); - else if (dm_value[2] == 3) - odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0xc); - } else if (dm_value[1] == 2) { /*RX*/ - - phydm_config_cck_rx_antenna_init(p_dm_odm); - - if (dm_value[2] == 1) - phydm_config_cck_rx_path(p_dm_odm, PHYDM_A, CCA_PATHDIV_DISABLE); - else if (dm_value[2] == 2) - phydm_config_cck_rx_path(p_dm_odm, PHYDM_B, CCA_PATHDIV_DISABLE); - else if (dm_value[2] == 3) { - if (dm_value[3] == 1) /*enable path diversity*/ - phydm_config_cck_rx_path(p_dm_odm, PHYDM_AB, CCA_PATHDIV_ENABLE); - else - phydm_config_cck_rx_path(p_dm_odm, PHYDM_B, CCA_PATHDIV_DISABLE); - } - } - } - /* OFDM */ - else if (dm_value[0] == 1) { - - if (dm_value[1] == 1) { /*TX*/ - phydm_config_ofdm_tx_path(p_dm_odm, dm_value[2]); - /**/ - } else if (dm_value[1] == 2) { /*RX*/ - phydm_config_ofdm_rx_path(p_dm_odm, dm_value[2]); - /**/ - } + { + dm->cck_new_agc = false; + /**/ } - PHYDM_SNPRINTF((output + used, out_len - used, "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n", - (dm_value[0] == 1) ? "OFDM" : "CCK", - (dm_value[1] == 1) ? "TX" : "RX", - (dm_value[2] & 0x1) ? "A" : "", - (dm_value[2] & 0x2) ? "B" : "", - (dm_value[2] & 0x4) ? "C" : "", - (dm_value[2] & 0x8) ? "D" : "" - )); + phydm_get_cck_rssi_table_from_reg(dm); } void -phydm_init_cck_setting( - struct PHY_DM_STRUCT *p_dm_odm +phydm_init_hw_info_by_rfe( + struct dm_struct *dm ) { -#if (RTL8192E_SUPPORT == 1) - u32 value_824, value_82c; -#endif - - p_dm_odm->is_cck_high_power = (boolean) odm_get_bb_reg(p_dm_odm, ODM_REG(CCK_RPT_FORMAT, p_dm_odm), ODM_BIT(CCK_RPT_FORMAT, p_dm_odm)); - -#if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - phydm_config_cck_rx_antenna_init(p_dm_odm); - phydm_config_cck_rx_path(p_dm_odm, PHYDM_A, CCA_PATHDIV_DISABLE); -#endif - - /* 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting should be equal or CCK RSSI report may be incorrect */ - value_824 = odm_get_bb_reg(p_dm_odm, 0x824, BIT(9)); - value_82c = odm_get_bb_reg(p_dm_odm, 0x82c, BIT(9)); - - if (value_824 != value_82c) - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(9), value_824); - odm_set_bb_reg(p_dm_odm, 0xa80, BIT(7), value_824); - p_dm_odm->cck_agc_report_type = (boolean)value_824; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("cck_agc_report_type = (( %d )), ext_lna_gain = (( %d ))\n", p_dm_odm->cck_agc_report_type, p_dm_odm->ext_lna_gain)); - } +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8822B) + phydm_init_hw_info_by_rfe_type_8822b(dm); #endif -/* JJ ADD 20161014 */ -#if ((RTL8703B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8710B_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { - - p_dm_odm->cck_agc_report_type = odm_get_bb_reg(p_dm_odm, 0x950, BIT(11)) ? 1 : 0; /*1: 4bit LNA, 0: 3bit LNA */ - - if (p_dm_odm->cck_agc_report_type != 1) { - dbg_print("[Warning] 8703B/8723D/8710B CCK should be 4bit LNA, ie. 0x950[11] = 1\n"); - /**/ - } - } +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821C) + phydm_init_hw_info_by_rfe_type_8821c(dm); #endif -/* JJ ADD 20161014 */ -#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8710B_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8710B)) - p_dm_odm->cck_new_agc = odm_get_bb_reg(p_dm_odm, 0xa9c, BIT(17)) ? true : false; /*1: new agc 0: old agc*/ - else +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8197F) + phydm_init_hw_info_by_rfe_type_8197f(dm); #endif - p_dm_odm->cck_new_agc = false; - } - void -phydm_dynamicsoftmletting( - struct PHY_DM_STRUCT *p_dm_odm +phydm_common_info_self_init( + struct dm_struct *dm ) { + phydm_init_cck_setting(dm); + dm->rf_path_rx_enable = (u8) odm_get_bb_reg(dm, ODM_REG(BB_RX_PATH, dm), ODM_BIT(BB_RX_PATH, dm)); +#if (DM_ODM_SUPPORT_TYPE != ODM_CE) + dm->is_net_closed = &dm->BOOLEAN_temp; - u32 ret_val; - -#if (RTL8822B_SUPPORT == 1) - if (*(p_dm_odm->p_mp_mode) == false) { - if (p_dm_odm->support_ic_type & ODM_RTL8822B) { - - if ((!p_dm_odm->is_linked)|(p_dm_odm->bLinkedcmw500)) - return; - - if (true == p_dm_odm->bsomlenabled) { - ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_TRACE,("PHYDM_DynamicSoftMLSetting(): SoML has been enable, skip dynamic SoML switch\n")); - return; - } + phydm_init_debug_setting(dm); +#endif + phydm_init_trx_antenna_setting(dm); + phydm_init_soft_ml_setting(dm); - ret_val = odm_get_bb_reg(p_dm_odm, 0xf8c, MASKBYTE0); - ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_TRACE,("PHYDM_DynamicSoftMLSetting(): Read 0xF8C = 0x%08X\n",ret_val)); + dm->phydm_sys_up_time = 0; - if (ret_val < 0x16) { - ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_LOUD,("PHYDM_DynamicSoftMLSetting(): 0xF8C(== 0x%08X) < 0x16, enable SoML\n",ret_val)); - phydm_somlrxhp_setting(p_dm_odm, true); - /* odm_set_bb_reg(p_dm_odm, 0x19a8, MASKDWORD, 0xc10a0000); */ - p_dm_odm->bsomlenabled = true; - } - } - } -#endif + if (dm->support_ic_type & ODM_IC_1SS) + dm->num_rf_path = 1; + else if (dm->support_ic_type & ODM_IC_2SS) + dm->num_rf_path = 2; + else if (dm->support_ic_type & ODM_IC_3SS) + dm->num_rf_path = 3; + else if (dm->support_ic_type & ODM_IC_4SS) + dm->num_rf_path = 4; + else + dm->num_rf_path = 1; + + dm->tx_rate = 0xFF; + dm->rssi_min_by_path = 0xFF; + + dm->number_linked_client = 0; + dm->pre_number_linked_client = 0; + dm->number_active_client = 0; + dm->pre_number_active_client = 0; + + dm->last_tx_ok_cnt = 0; + dm->last_rx_ok_cnt = 0; + dm->tx_tp = 0; + dm->rx_tp = 0; + dm->total_tp = 0; + dm->traffic_load = TRAFFIC_LOW; + + dm->nbi_set_result = 0; + dm->is_init_hw_info_by_rfe = false; + dm->pre_dbg_priority = BB_DBGPORT_RELEASE; + dm->tp_active_th = 5; + dm->disable_phydm_watchdog = 0; + + dm->u8_dummy = 0xf; + dm->u16_dummy = 0xffff; + dm->u32_dummy = 0xffffffff; + + /*odm_memory_set(dm, &(dm->pause_lv_table.lv_dig), 0, sizeof(struct phydm_pause_lv));*/ + dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE; + dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE; } - void -phydm_init_soft_ml_setting( - struct PHY_DM_STRUCT *p_dm_odm +phydm_cmn_sta_info_update( + void *dm_void, + u8 macid ) { -#if (RTL8822B_SUPPORT == 1) - if (*(p_dm_odm->p_mp_mode) == false) { - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - /*odm_set_bb_reg(p_dm_odm, 0x19a8, MASKDWORD, 0xd10a0000);*/ - phydm_somlrxhp_setting(p_dm_odm, true); - p_dm_odm->bsomlenabled = true; - } -#endif -#if (RTL8821C_SUPPORT == 1) - if (*(p_dm_odm->p_mp_mode) == false) { - if (p_dm_odm->support_ic_type & ODM_RTL8821C) - odm_set_bb_reg(p_dm_odm, 0x19a8, BIT(31)|BIT(30)|BIT(29)|BIT(28), 0xd); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct ra_sta_info *ra = NULL; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n", __func__); + return; } -#endif -} -void -phydm_init_hw_info_by_rfe( - struct PHY_DM_STRUCT *p_dm_odm -) -{ -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - phydm_init_hw_info_by_rfe_type_8822b(p_dm_odm); -#endif -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8821C) - phydm_init_hw_info_by_rfe_type_8821c(p_dm_odm); -#endif -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - phydm_init_hw_info_by_rfe_type_8197f(p_dm_odm); -#endif -} + PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id); -void -odm_common_info_self_init( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - phydm_init_cck_setting(p_dm_odm); - p_dm_odm->rf_path_rx_enable = (u8) odm_get_bb_reg(p_dm_odm, ODM_REG(BB_RX_PATH, p_dm_odm), ODM_BIT(BB_RX_PATH, p_dm_odm)); -#if (DM_ODM_SUPPORT_TYPE != ODM_CE) - p_dm_odm->p_is_net_closed = &p_dm_odm->BOOLEAN_temp; + /*[Calculate TX/RX state]*/ + if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1)) + ra->txrx_state= TX_STATE; + else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1)) + ra->txrx_state = RX_STATE; + else + ra->txrx_state = BI_DIRECTION_STATE; - phydm_init_debug_setting(p_dm_odm); -#endif - phydm_init_trx_antenna_setting(p_dm_odm); - phydm_init_soft_ml_setting(p_dm_odm); - - p_dm_odm->phydm_period = PHYDM_WATCH_DOG_PERIOD; - p_dm_odm->phydm_sys_up_time = 0; - - if (p_dm_odm->support_ic_type & ODM_IC_1SS) - p_dm_odm->num_rf_path = 1; - else if (p_dm_odm->support_ic_type & ODM_IC_2SS) - p_dm_odm->num_rf_path = 2; - else if (p_dm_odm->support_ic_type & ODM_IC_3SS) - p_dm_odm->num_rf_path = 3; - else if (p_dm_odm->support_ic_type & ODM_IC_4SS) - p_dm_odm->num_rf_path = 4; - - p_dm_odm->tx_rate = 0xFF; - p_dm_odm->rssi_min_by_path = 0xFF; - - p_dm_odm->number_linked_client = 0; - p_dm_odm->pre_number_linked_client = 0; - p_dm_odm->number_active_client = 0; - p_dm_odm->pre_number_active_client = 0; - - p_dm_odm->last_tx_ok_cnt = 0; - p_dm_odm->last_rx_ok_cnt = 0; - p_dm_odm->tx_tp = 0; - p_dm_odm->rx_tp = 0; - p_dm_odm->total_tp = 0; - p_dm_odm->traffic_load = TRAFFIC_LOW; - - p_dm_odm->nbi_set_result = 0; - p_dm_odm->is_init_hw_info_by_rfe = false; - p_dm_odm->pre_dbg_priority = BB_DBGPORT_RELEASE; - p_dm_odm->tp_active_th = 5; + ra->is_noisy = dm->noisy_decision; } void -odm_common_info_self_update( - struct PHY_DM_STRUCT *p_dm_odm +phydm_common_info_self_update( + struct dm_struct *dm ) { - u8 entry_cnt = 0, num_active_client = 0; + u8 sta_cnt = 0, num_active_client = 0; u32 i, one_entry_macid = 0; u32 ma_rx_tp = 0; - struct sta_info *p_entry; + struct cmn_sta_info *sta; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; + PADAPTER adapter = (PADAPTER)dm->adapter; - p_entry = p_dm_odm->p_odm_sta_info[0]; - if (p_mgnt_info->mAssoc) { - p_entry->bUsed = true; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; + + sta = dm->phydm_sta_info[0]; + if (mgnt_info->mAssoc) { + sta->dm_ctrl |= STA_DM_CTRL_ACTIVE; for (i = 0; i < 6; i++) - p_entry->MacAddr[i] = p_mgnt_info->Bssid[i]; + sta->mac_addr[i] = mgnt_info->Bssid[i]; } else if (GetFirstClientPort(adapter)) { - struct _ADAPTER *p_client_adapter = GetFirstClientPort(adapter); + //void *client_adapter = GetFirstClientPort(adapter); + struct _ADAPTER *client_adapter = GetFirstClientPort(adapter); - p_entry->bUsed = true; + sta->dm_ctrl |= STA_DM_CTRL_ACTIVE; for (i = 0; i < 6; i++) - p_entry->MacAddr[i] = p_client_adapter->MgntInfo.Bssid[i]; + sta->mac_addr[i] = client_adapter->MgntInfo.Bssid[i]; } else { - p_entry->bUsed = false; + sta->dm_ctrl = sta->dm_ctrl & (~STA_DM_CTRL_ACTIVE); for (i = 0; i < 6; i++) - p_entry->MacAddr[i] = 0; + sta->mac_addr[i] = 0; } /* STA mode is linked to AP */ - if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[0]) && !ACTING_AS_AP(adapter)) - p_dm_odm->bsta_state = true; + if (is_sta_active(sta) && !ACTING_AS_AP(adapter)) + dm->bsta_state = true; else - p_dm_odm->bsta_state = false; + dm->bsta_state = false; #endif for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { - entry_cnt++; - if (entry_cnt == 1) + sta = dm->phydm_sta_info[i]; + if (is_sta_active(sta)) { + sta_cnt++; + + if (sta_cnt == 1) one_entry_macid = i; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - ma_rx_tp = (p_entry->rx_byte_cnt_low_maw) >> 17; /* low moving average RX TP ( bit /sec), , <<3(8bit), >>20(10^6,M)*/ + phydm_cmn_sta_info_update(dm, (u8)i); + #if (BEAMFORMING_SUPPORT == 1) + //phydm_get_txbf_device_num(dm, (u8)i); + #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("ClientTP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp)); + ma_rx_tp = sta->rx_moving_average_tp + sta->tx_moving_average_tp; + PHYDM_DBG(dm, DBG_COMMON_FLOW, "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp); if (ma_rx_tp > ACTIVE_TP_THRESHOLD) num_active_client++; -#endif } } - if (entry_cnt == 1) { - p_dm_odm->is_one_entry_only = true; - p_dm_odm->one_entry_macid = one_entry_macid; - p_dm_odm->one_entry_tp = ma_rx_tp; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + dm->is_linked = (sta_cnt != 0) ? true : false; +#endif + + if (sta_cnt == 1) { + dm->is_one_entry_only = true; + dm->one_entry_macid = one_entry_macid; + dm->one_entry_tp = ma_rx_tp; - p_dm_odm->tp_active_occur = 0; + dm->tp_active_occur = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n", - p_dm_odm->one_entry_tp, p_dm_odm->pre_one_entry_tp)); + PHYDM_DBG(dm, DBG_COMMON_FLOW, "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n", + dm->one_entry_tp, dm->pre_one_entry_tp); - if ((p_dm_odm->one_entry_tp > p_dm_odm->pre_one_entry_tp) && (p_dm_odm->pre_one_entry_tp <= 2)) { - if ((p_dm_odm->one_entry_tp - p_dm_odm->pre_one_entry_tp) > p_dm_odm->tp_active_th) - p_dm_odm->tp_active_occur = 1; + if ((dm->one_entry_tp > dm->pre_one_entry_tp) && (dm->pre_one_entry_tp <= 2)) { + if ((dm->one_entry_tp - dm->pre_one_entry_tp) > dm->tp_active_th) + dm->tp_active_occur = 1; } - p_dm_odm->pre_one_entry_tp = p_dm_odm->one_entry_tp; + dm->pre_one_entry_tp = dm->one_entry_tp; } else - p_dm_odm->is_one_entry_only = false; + dm->is_one_entry_only = false; - p_dm_odm->pre_number_linked_client = p_dm_odm->number_linked_client; - p_dm_odm->pre_number_active_client = p_dm_odm->number_active_client; + dm->pre_number_linked_client = dm->number_linked_client; + dm->pre_number_active_client = dm->number_active_client; - p_dm_odm->number_linked_client = entry_cnt; - p_dm_odm->number_active_client = num_active_client; + dm->number_linked_client = sta_cnt; + dm->number_active_client = num_active_client; /*Traffic load information update*/ - phydm_traffic_load_decision(p_dm_odm); + phydm_traffic_load_decision(dm); + + dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD; + + dm->is_dfs_band = phydm_is_dfs_band(dm); + dm->phy_dbg_info.show_phy_sts_cnt = 0; - p_dm_odm->phydm_sys_up_time += p_dm_odm->phydm_period; } void -odm_common_info_self_reset( - struct PHY_DM_STRUCT *p_dm_odm +phydm_common_info_self_reset( + struct dm_struct *dm ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_dm_odm->phy_dbg_info.num_qry_beacon_pkt = 0; + dm->phy_dbg_info.num_qry_beacon_pkt = 0; #endif } void * phydm_get_structure( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 structure_type ) { - void *p_struct = NULL; + void *structure = NULL; #if RTL8195A_SUPPORT switch (structure_type) { case PHYDM_FALSEALMCNT: - p_struct = &false_alm_cnt; + structure = &false_alm_cnt; break; case PHYDM_CFOTRACK: - p_struct = &dm_cfo_track; + structure = &dm_cfo_track; break; case PHYDM_ADAPTIVITY: - p_struct = &(p_dm_odm->adaptivity); + structure = &dm->adaptivity; break; default: @@ -772,15 +422,19 @@ phydm_get_structure( #else switch (structure_type) { case PHYDM_FALSEALMCNT: - p_struct = &(p_dm_odm->false_alm_cnt); + structure = &dm->false_alm_cnt; break; case PHYDM_CFOTRACK: - p_struct = &(p_dm_odm->dm_cfo_track); + structure = &dm->dm_cfo_track; break; case PHYDM_ADAPTIVITY: - p_struct = &(p_dm_odm->adaptivity); + structure = &dm->adaptivity; + break; + + case PHYDM_DFS: + structure = &dm->dfs; break; default: @@ -788,47 +442,51 @@ phydm_get_structure( } #endif - return p_struct; + return structure; } void -odm_hw_setting( - struct PHY_DM_STRUCT *p_dm_odm +phydm_hw_setting( + struct dm_struct *dm ) { #if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8821) - odm_hw_setting_8821a(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8821) + odm_hw_setting_8821a(dm); #endif #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - phydm_hwsetting_8814a(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8814A) + phydm_hwsetting_8814a(dm); #endif #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - phydm_hwsetting_8822b(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8822B) + phydm_hwsetting_8822b(dm); +#endif + +#if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8812) + phydm_hwsetting_8812a(dm); #endif #if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - phydm_hwsetting_8197f(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8197F) + phydm_hwsetting_8197f(dm); #endif } #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) -u32 +u64 phydm_supportability_init_win( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 support_ability = 0; - - switch (p_dm_odm->support_ic_type) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability = 0; + switch (dm->support_ic_type) { /*---------------N Series--------------------*/ #if (RTL8188E_SUPPORT == 1) case ODM_RTL8188E: @@ -842,7 +500,7 @@ phydm_supportability_init_win( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT | + ODM_BB_ENV_MONITOR | ODM_BB_PRIMARY_CCA; break; #endif @@ -859,7 +517,7 @@ phydm_supportability_init_win( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT | + ODM_BB_ENV_MONITOR | ODM_BB_PRIMARY_CCA; break; #endif @@ -876,7 +534,8 @@ phydm_supportability_init_win( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; break; #endif @@ -892,7 +551,7 @@ phydm_supportability_init_win( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -908,7 +567,7 @@ phydm_supportability_init_win( /* ODM_BB_PWR_TRAIN | */ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -924,7 +583,7 @@ phydm_supportability_init_win( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -940,7 +599,7 @@ phydm_supportability_init_win( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -959,7 +618,7 @@ phydm_supportability_init_win( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -975,7 +634,7 @@ phydm_supportability_init_win( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -991,7 +650,7 @@ phydm_supportability_init_win( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1007,8 +666,8 @@ phydm_supportability_init_win( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT | - ODM_BB_DYNAMIC_PSDTOOL; + ODM_BB_ENV_MONITOR | + ODM_BB_ADAPTIVE_SOML; break; #endif @@ -1024,7 +683,7 @@ phydm_supportability_init_win( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1039,36 +698,27 @@ phydm_supportability_init_win( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; - dbg_print("[Warning] Supportability Init Warning !!!\n"); + pr_debug("[Warning] Supportability Init Warning !!!\n"); break; } - /*[Config Antenna Diveristy]*/ - if (*(p_dm_odm->p_enable_antdiv)) - support_ability |= ODM_BB_ANT_DIV; - - /*[Config Adaptivity]*/ - if (*(p_dm_odm->p_enable_adaptivity)) - support_ability |= ODM_BB_ADAPTIVITY; - return support_ability; } #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -u32 +u64 phydm_supportability_init_ce( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 support_ability = 0; - - switch (p_dm_odm->support_ic_type) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability = 0; + switch (dm->support_ic_type) { /*---------------N Series--------------------*/ #if (RTL8188E_SUPPORT == 1) case ODM_RTL8188E: @@ -1082,7 +732,7 @@ phydm_supportability_init_ce( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT | + ODM_BB_ENV_MONITOR | ODM_BB_PRIMARY_CCA; break; #endif @@ -1099,7 +749,8 @@ phydm_supportability_init_ce( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; break; #endif @@ -1115,7 +766,8 @@ phydm_supportability_init_ce( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; break; #endif @@ -1131,7 +783,7 @@ phydm_supportability_init_ce( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1147,7 +799,7 @@ phydm_supportability_init_ce( /* ODM_BB_PWR_TRAIN | */ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1163,7 +815,7 @@ phydm_supportability_init_ce( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1179,7 +831,7 @@ phydm_supportability_init_ce( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1198,7 +850,7 @@ phydm_supportability_init_ce( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1214,7 +866,7 @@ phydm_supportability_init_ce( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1230,7 +882,7 @@ phydm_supportability_init_ce( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1246,8 +898,7 @@ phydm_supportability_init_ce( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT | - ODM_BB_DYNAMIC_PSDTOOL; + ODM_BB_ENV_MONITOR; break; #endif @@ -1263,7 +914,7 @@ phydm_supportability_init_ce( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1278,50 +929,40 @@ phydm_supportability_init_ce( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; - dbg_print("[Warning] Supportability Init Warning !!!\n"); + pr_debug("[Warning] Supportability Init Warning !!!\n"); break; } - - /*[Config Antenna Diveristy]*/ - if (*(p_dm_odm->p_enable_antdiv)) - support_ability |= ODM_BB_ANT_DIV; - - /*[Config Adaptivity]*/ - if (*(p_dm_odm->p_enable_adaptivity)) - support_ability |= ODM_BB_ADAPTIVITY; - + return support_ability; } #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -u32 +u64 phydm_supportability_init_ap( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 support_ability = 0; - - switch (p_dm_odm->support_ic_type) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability = 0; + switch (dm->support_ic_type) { /*---------------N Series--------------------*/ #if (RTL8188E_SUPPORT == 1) case ODM_RTL8188E: support_ability |= ODM_BB_DIG | ODM_BB_RA_MASK | - ODM_BB_DYNAMIC_TXPWR | ODM_BB_FA_CNT | ODM_BB_RSSI_MONITOR | ODM_BB_CCK_PD | /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT | + ODM_BB_ENV_MONITOR | ODM_BB_PRIMARY_CCA; break; #endif @@ -1331,14 +972,14 @@ phydm_supportability_init_ap( support_ability |= ODM_BB_DIG | ODM_BB_RA_MASK | - ODM_BB_DYNAMIC_TXPWR | ODM_BB_FA_CNT | ODM_BB_RSSI_MONITOR | ODM_BB_CCK_PD | /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; break; #endif @@ -1347,14 +988,13 @@ phydm_supportability_init_ap( support_ability |= ODM_BB_DIG | ODM_BB_RA_MASK | - ODM_BB_DYNAMIC_TXPWR | ODM_BB_FA_CNT | ODM_BB_RSSI_MONITOR | ODM_BB_CCK_PD | /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1364,14 +1004,16 @@ phydm_supportability_init_ap( support_ability |= ODM_BB_DIG | ODM_BB_RA_MASK | - ODM_BB_DYNAMIC_TXPWR | ODM_BB_FA_CNT | ODM_BB_RSSI_MONITOR | ODM_BB_CCK_PD | /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ADAPTIVE_SOML | + ODM_BB_ENV_MONITOR | + ODM_BB_LNA_SAT_CHK | + ODM_BB_PRIMARY_CCA; break; #endif @@ -1382,14 +1024,13 @@ phydm_supportability_init_ap( support_ability |= ODM_BB_DIG | ODM_BB_RA_MASK | - ODM_BB_DYNAMIC_TXPWR | ODM_BB_FA_CNT | ODM_BB_RSSI_MONITOR | ODM_BB_CCK_PD | /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1398,14 +1039,13 @@ phydm_supportability_init_ap( support_ability |= ODM_BB_DIG | ODM_BB_RA_MASK | - ODM_BB_DYNAMIC_TXPWR | ODM_BB_FA_CNT | ODM_BB_RSSI_MONITOR | ODM_BB_CCK_PD | /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1414,14 +1054,13 @@ phydm_supportability_init_ap( support_ability |= ODM_BB_DIG | ODM_BB_RA_MASK | - ODM_BB_DYNAMIC_TXPWR | ODM_BB_FA_CNT | ODM_BB_RSSI_MONITOR | ODM_BB_CCK_PD | /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1430,15 +1069,14 @@ phydm_supportability_init_ap( support_ability |= ODM_BB_DIG | ODM_BB_RA_MASK | - ODM_BB_DYNAMIC_TXPWR | ODM_BB_FA_CNT | ODM_BB_RSSI_MONITOR | ODM_BB_CCK_PD | /*ODM_BB_PWR_TRAIN |*/ + /*ODM_BB_ADAPTIVE_SOML |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT | - ODM_BB_DYNAMIC_PSDTOOL; + ODM_BB_ENV_MONITOR ; break; #endif @@ -1447,14 +1085,13 @@ phydm_supportability_init_ap( support_ability |= ODM_BB_DIG | ODM_BB_RA_MASK | - ODM_BB_DYNAMIC_TXPWR | ODM_BB_FA_CNT | ODM_BB_RSSI_MONITOR | ODM_BB_CCK_PD | /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1463,27 +1100,26 @@ phydm_supportability_init_ap( support_ability |= ODM_BB_DIG | ODM_BB_RA_MASK | - ODM_BB_DYNAMIC_TXPWR | ODM_BB_FA_CNT | ODM_BB_RSSI_MONITOR | ODM_BB_CCK_PD | /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; - dbg_print("[Warning] Supportability Init Warning !!!\n"); + pr_debug("[Warning] Supportability Init Warning !!!\n"); break; } #if 0 /*[Config Antenna Diveristy]*/ - if (*(p_dm_odm->p_enable_antdiv)) + if (*(dm->enable_antdiv)) support_ability |= ODM_BB_ANT_DIV; /*[Config Adaptivity]*/ - if (*(p_dm_odm->p_enable_adaptivity)) + if (*(dm->enable_adaptivity)) support_ability |= ODM_BB_ADAPTIVITY; #endif @@ -1492,16 +1128,15 @@ phydm_supportability_init_ap( #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT)) -u32 +u64 phydm_supportability_init_iot( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 support_ability = 0; - - switch (p_dm_odm->support_ic_type) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability = 0; + switch (dm->support_ic_type) { #if (RTL8710B_SUPPORT == 1) case ODM_RTL8710B: support_ability |= @@ -1514,7 +1149,7 @@ phydm_supportability_init_iot( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1530,7 +1165,7 @@ phydm_supportability_init_iot( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; break; #endif @@ -1545,398 +1180,708 @@ phydm_supportability_init_iot( /*ODM_BB_PWR_TRAIN |*/ ODM_BB_RATE_ADAPTIVE | ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT; + ODM_BB_ENV_MONITOR; - dbg_print("[Warning] Supportability Init Warning !!!\n"); + pr_debug("[Warning] Supportability Init Warning !!!\n"); break; } - - /*[Config Antenna Diveristy]*/ - if (*(p_dm_odm->p_enable_antdiv)) - support_ability |= ODM_BB_ANT_DIV; - - /*[Config Adaptivity]*/ - if (*(p_dm_odm->p_enable_adaptivity)) - support_ability |= ODM_BB_ADAPTIVITY; - + return support_ability; } #endif void phydm_fwoffload_ability_init( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum phydm_offload_ability offload_ability ) { - switch (offload_ability) { - case PHYDM_PHY_PARAM_OFFLOAD: - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - p_dm_odm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD; + if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) + dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD; break; case PHYDM_RF_IQK_OFFLOAD: - p_dm_odm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD; + dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD; break; default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("fwofflad, wrong init type!!\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n"); break; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("fw_offload_ability = %x\n", p_dm_odm->fw_offload_ability)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "fw_offload_ability = %x\n", dm->fw_offload_ability); } void phydm_fwoffload_ability_clear( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum phydm_offload_ability offload_ability ) { - switch (offload_ability) { - case PHYDM_PHY_PARAM_OFFLOAD: - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - p_dm_odm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD); + if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) + dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD); break; case PHYDM_RF_IQK_OFFLOAD: - p_dm_odm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD); + dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD); break; default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("fwofflad, wrong init type!!\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n"); break; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("fw_offload_ability = %x\n", p_dm_odm->fw_offload_ability)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "fw_offload_ability = %x\n", dm->fw_offload_ability); } void phydm_supportability_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 support_ability; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability; - if (*(p_dm_odm->p_mp_mode) == true) { + if (*dm->mp_mode == true) { support_ability = 0; + /**/ } else { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - support_ability = phydm_supportability_init_win(p_dm_odm); + support_ability = phydm_supportability_init_win(dm); #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - support_ability = phydm_supportability_init_ap(p_dm_odm); + support_ability = phydm_supportability_init_ap(dm); #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) - support_ability = phydm_supportability_init_ce(p_dm_odm); + support_ability = phydm_supportability_init_ce(dm); #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) - support_ability = phydm_supportability_init_iot(p_dm_odm); + support_ability = phydm_supportability_init_iot(dm); #endif + + /*[Config Antenna Diveristy]*/ + if (IS_FUNC_EN(dm->enable_antdiv)) + support_ability |= ODM_BB_ANT_DIV; + + /*[Config Adaptive SOML]*/ + if (IS_FUNC_EN(dm->en_adap_soml)) + support_ability |= ODM_BB_ADAPTIVE_SOML; + + /*[Config Adaptivity]*/ + if (IS_FUNC_EN(dm->enable_adaptivity)) + support_ability |= ODM_BB_ADAPTIVITY; } - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ABILITY, support_ability); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IC = ((0x%x)), Supportability Init = ((0x%x))\n", p_dm_odm->support_ic_type, p_dm_odm->support_ability)); + odm_cmn_info_init(dm, ODM_CMNINFO_ABILITY, support_ability); + PHYDM_DBG(dm, ODM_COMP_INIT, "IC = ((0x%x)), Supportability Init = ((0x%llx))\n", dm->support_ic_type, dm->support_ability); } +void +phydm_rfe_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n"); +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + phydm_rfe_8822b_init(dm); + /**/ + } +#endif +} void phydm_dm_early_init( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - /*odm_init_mp_driver_status(p_dm_odm);*/ - halrf_init(p_dm_odm); + halrf_init(dm); #endif } void odm_dm_init( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); -#endif - - halrf_init(p_dm_odm); - phydm_supportability_init(p_dm_odm); - odm_common_info_self_init(p_dm_odm); - odm_dig_init(p_dm_odm); - phydm_nhm_counter_statistics_init(p_dm_odm); - phydm_adaptivity_init(p_dm_odm); - phydm_ra_info_init(p_dm_odm); - odm_rate_adaptive_mask_init(p_dm_odm); - odm_cfo_tracking_init(p_dm_odm); - odm_rssi_monitor_init(p_dm_odm); - phydm_rf_init(p_dm_odm); - odm_txpowertracking_init(p_dm_odm); - phydm_dc_cancellation(p_dm_odm); -#if (PHYDM_TXA_CALIBRATION == 1) - phydm_txcurrentcalibration(p_dm_odm); - phydm_get_pa_bias_offset(p_dm_odm); -#endif - odm_antenna_diversity_init(p_dm_odm); -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_dynamic_rx_path_init(p_dm_odm); -#endif - odm_auto_channel_select_init(p_dm_odm); - odm_path_diversity_init(p_dm_odm); - odm_dynamic_tx_power_init(p_dm_odm); - phydm_init_ra_info(p_dm_odm); + halrf_init(dm); + phydm_supportability_init(dm); + phydm_rfe_init(dm); + phydm_common_info_self_init(dm); + phydm_rx_phy_status_init(dm); + phydm_auto_dbg_engine_init(dm); + phydm_dig_init(dm); + phydm_cck_pd_init(dm); + phydm_env_monitor_init(dm); + phydm_adaptivity_init(dm); + phydm_ra_info_init(dm); + phydm_rssi_monitor_init(dm); + phydm_cfo_tracking_init(dm); + phydm_rf_init(dm); + phydm_dc_cancellation(dm); +#ifdef PHYDM_TXA_CALIBRATION + phydm_txcurrentcalibration(dm); + phydm_get_pa_bias_offset(dm); +#endif + odm_antenna_diversity_init(dm); + phydm_adaptive_soml_init(dm); +#ifdef CONFIG_DYNAMIC_RX_PATH + phydm_dynamic_rx_path_init(dm); +#endif + phydm_path_diversity_init(dm); + phydm_pow_train_init(dm); + phydm_dynamic_tx_power_init(dm); #if (PHYDM_LA_MODE_SUPPORT == 1) - adc_smp_init(p_dm_odm); + adc_smp_init(dm); #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #ifdef BEAMFORMING_VERSION_1 - if (p_hal_data->beamforming_version == BEAMFORMING_VERSION_1) - #endif - { - phydm_beamforming_init(p_dm_odm); - } + phydm_beamforming_init(dm); #endif - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - #if (defined(CONFIG_BB_POWER_SAVING)) - odm_dynamic_bb_power_saving_init(p_dm_odm); - #endif - - #if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - odm_primary_cca_init(p_dm_odm); - odm_ra_info_init_all(p_dm_odm); - } - #endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - - #if (RTL8723B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) - odm_sw_ant_detect_init(p_dm_odm); - #endif - - #if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) - odm_primary_cca_check_init(p_dm_odm); - #endif - +#if (RTL8188E_SUPPORT == 1) + odm_ra_info_init_all(dm); #endif - } + phydm_primary_cca_init(dm); - #if (CONFIG_PSD_TOOL == 1) - phydm_psd_init(p_dm_odm); + #ifdef CONFIG_PSD_TOOL + phydm_psd_init(dm); + #endif + + #ifdef CONFIG_SMART_ANTENNA + phydm_smt_ant_init(dm); #endif } void odm_dm_reset( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - - odm_ant_div_reset(p_dm_odm); - phydm_set_edcca_threshold_api(p_dm_odm, p_dm_dig_table->cur_ig_value); -} - -void -phydm_primary_cca( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { -#if PHYDM_PRIMARY_CCA + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - #if (RTL8188E_SUPPORT == 1) - odm_dynamic_primary_cca_8188e(p_dm_odm); - #endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - #if (RTL8192E_SUPPORT == 1) - odm_dynamic_primary_cca_check_8192e(p_dm_odm); - #endif - } - -#endif + odm_ant_div_reset(dm); + phydm_set_edcca_threshold_api(dm, dig_t->cur_ig_value); } void phydm_support_ability_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 pre_support_ability; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 pre_support_ability, one = 1; u32 used = *_used; u32 out_len = *_out_len; - pre_support_ability = p_dm_odm->support_ability ; - PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); + pre_support_ability = dm->support_ability; + + PDM_SNPF(out_len, used, output + used, out_len - used, "\n%s\n", + "================================"); if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output + used, out_len - used, "[Supportability] PhyDM Selection\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((p_dm_odm->support_ability & ODM_BB_DIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((p_dm_odm->support_ability & ODM_BB_RA_MASK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((p_dm_odm->support_ability & ODM_BB_FA_CNT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))CCK_PD\n", ((p_dm_odm->support_ability & ODM_BB_CCK_PD) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))PWR_TRAIN\n", ((p_dm_odm->support_ability & ODM_BB_PWR_TRAIN) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((p_dm_odm->support_ability & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((p_dm_odm->support_ability & ODM_BB_PATH_DIV) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "13. (( %s ))ADAPTIVITY\n", ((p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))struct _CFO_TRACKING_\n", ((p_dm_odm->support_ability & ODM_BB_CFO_TRACKING) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))NHM_CNT\n", ((p_dm_odm->support_ability & ODM_BB_NHM_CNT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))PRIMARY_CCA\n", ((p_dm_odm->support_ability & ODM_BB_PRIMARY_CCA) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))TXBF\n", ((p_dm_odm->support_ability & ODM_BB_TXBF) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))DYNAMIC_ARFR\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "19. (( %s ))DYNAMIC_PSD_TOOL\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_PSDTOOL) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "20. (( %s ))EDCA_TURBO\n", ((p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "21. (( %s ))DYNAMIC_RX_PATH\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Supportability] PhyDM Selection\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s\n", "================================"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))DIG\n", + ((dm->support_ability & ODM_BB_DIG) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "01. (( %s ))RA_MASK\n", + ((dm->support_ability & ODM_BB_RA_MASK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "02. (( %s ))DYN_TXPWR\n", + ((dm->support_ability & ODM_BB_DYNAMIC_TXPWR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "03. (( %s ))FA_CNT\n", + ((dm->support_ability & ODM_BB_FA_CNT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "04. (( %s ))RSSI_MNTR\n", + ((dm->support_ability & ODM_BB_RSSI_MONITOR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "05. (( %s ))CCK_PD\n", + ((dm->support_ability & ODM_BB_CCK_PD) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "06. (( %s ))ANT_DIV\n", + ((dm->support_ability & ODM_BB_ANT_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "07. (( %s ))SMT_ANT\n", + ((dm->support_ability & ODM_BB_SMT_ANT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "08. (( %s ))PWR_TRAIN\n", + ((dm->support_ability & ODM_BB_PWR_TRAIN) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "09. (( %s ))RA\n", + ((dm->support_ability & ODM_BB_RATE_ADAPTIVE) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "10. (( %s ))PATH_DIV\n", + ((dm->support_ability & ODM_BB_PATH_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "11. (( %s ))DFS\n", + ((dm->support_ability & ODM_BB_DFS) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "12. (( %s ))DYN_ARFR\n", + ((dm->support_ability & ODM_BB_DYNAMIC_ARFR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "13. (( %s ))ADAPTIVITY\n", + ((dm->support_ability & ODM_BB_ADAPTIVITY) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "14. (( %s ))CFO_TRACK\n", + ((dm->support_ability & ODM_BB_CFO_TRACKING) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "15. (( %s ))ENV_MONITOR\n", + ((dm->support_ability & ODM_BB_ENV_MONITOR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "16. (( %s ))PRI_CCA\n", + ((dm->support_ability & ODM_BB_PRIMARY_CCA) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "17. (( %s ))ADPTV_SOML\n", + ((dm->support_ability & ODM_BB_ADAPTIVE_SOML) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "18. (( %s ))NA_SAT_CHK\n", + ((dm->support_ability & ODM_BB_LNA_SAT_CHK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "19. (( %s ))DYN_RX_PATH\n", + ((dm->support_ability & ODM_BB_DYNAMIC_RX_PATH) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s\n", "================================"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Supportability] PhyDM offload ability\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s\n", "================================"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))PHY PARAM OFFLOAD\n", + ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "01. (( %s ))RF IQK OFFLOAD\n", + ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s\n", "================================"); + } /* else if(dm_value[0] == 101) { - p_dm_odm->support_ability = 0 ; + dm->support_ability = 0 ; dbg_print("Disable all support_ability components\n"); - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "Disable all support_ability components")); + PDM_SNPF((output+used, out_len-used,"%s\n", "Disable all support_ability components")); } */ else { - if (dm_value[1] == 1) { /* enable */ - p_dm_odm->support_ability |= BIT(dm_value[0]) ; + dm->support_ability |= (one << dm_value[0]); if (BIT(dm_value[0]) & ODM_BB_PATH_DIV) - odm_path_diversity_init(p_dm_odm); - } else if (dm_value[1] == 2) /* disable */ - p_dm_odm->support_ability &= ~(BIT(dm_value[0])) ; - else { - /* dbg_print("\n[Warning!!!] 1:enable, 2:disable \n\n"); */ - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); - } - } - PHYDM_SNPRINTF((output + used, out_len - used, "pre-support_ability = 0x%x\n", pre_support_ability)); - PHYDM_SNPRINTF((output + used, out_len - used, "Curr-support_ability = 0x%x\n", p_dm_odm->support_ability)); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + phydm_path_diversity_init(dm); + } else if (dm_value[1] == 2) /* disable */ + dm->support_ability &= ~(one << dm_value[0]); + else + PDM_SNPF(out_len, used, output + used, + out_len - used, "%s\n", + "[Warning!!!] 1:enable, 2:disable"); + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "pre-support_ability = 0x%llx\n", + pre_support_ability); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Curr-support_ability = 0x%llx\n", + dm->support_ability); + PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n", + "================================"); + + *_used = used; + *_out_len = out_len; } -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -/* - * tmp modify for LC Only - * */ void -odm_dm_watchdog_lps( - struct PHY_DM_STRUCT *p_dm_odm +phydm_watchdog_lps_32k( + struct dm_struct *dm ) { - odm_common_info_self_update(p_dm_odm); - odm_false_alarm_counter_statistics(p_dm_odm); - odm_rssi_monitor_check(p_dm_odm); - odm_dig_by_rssi_lps(p_dm_odm); -#if PHYDM_SUPPORT_CCKPD - odm_cck_packet_detection_thresh(p_dm_odm); -#endif - odm_common_info_self_reset(p_dm_odm); + PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__); - if (*(p_dm_odm->p_is_power_saving) == true) - return; + phydm_common_info_self_update(dm); + phydm_rssi_monitor_check(dm); + phydm_dig_lps_32k(dm); + phydm_common_info_self_reset(dm); } + +void +phydm_watchdog_lps( + struct dm_struct *dm +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__); + + phydm_common_info_self_update(dm); + phydm_rssi_monitor_check(dm); + phydm_basic_dbg_message(dm); + phydm_receiver_blocking(dm); + odm_false_alarm_counter_statistics(dm); + phydm_dig_by_rssi_lps(dm); + phydm_cck_pd_th(dm); + phydm_adaptivity(dm); + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + odm_antenna_diversity(dm); /*enable AntDiv in PS mode, request from SD4 Jeff*/ + #endif + phydm_common_info_self_reset(dm); #endif +} void phydm_watchdog_mp( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_dynamic_rx_path_caller(p_dm_odm); +#ifdef CONFIG_DYNAMIC_RX_PATH + phydm_dynamic_rx_path_caller(dm); #endif } -/* - * 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. - * You can not add any dummy function here, be care, you can only use DM structure - * to perform any new ODM_DM. - * */ + void -odm_dm_watchdog( - struct PHY_DM_STRUCT *p_dm_odm +phydm_pause_dm_watchdog( + void *dm_void, + enum phydm_pause_type pause_type ) { - odm_common_info_self_update(p_dm_odm); - phydm_basic_dbg_message(p_dm_odm); - odm_hw_setting(p_dm_odm); + struct dm_struct *dm = (struct dm_struct *)dm_void; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - { - struct rtl8192cd_priv *priv = p_dm_odm->priv; - if ((priv->auto_channel != 0) && (priv->auto_channel != 2)) /* if struct _ACS_ running, do not do FA/CCA counter read */ - return; + if (pause_type == PHYDM_PAUSE) { + dm->disable_phydm_watchdog = 1; + PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n"); + } else { + dm->disable_phydm_watchdog = 0; + PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n"); } +} + +u8 +phydm_pause_func( + void *dm_void, + enum phydm_func_idx pause_func, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_lv, + u8 val_lehgth, + u32 *val_buf +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + s8 *pause_lv_pre = &dm->s8_dummy; + u32 *bkp_val = &dm->u32_dummy; + u32 ori_val[5] = {0}; + u64 pause_func_bitmap = (u64)BIT(pause_func); + u8 i; + + + + PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__, + ((pause_type == PHYDM_PAUSE) ? "Pause" : "Resume"), pause_lv, val_lehgth); + + if (pause_lv >= PHYDM_PAUSE_MAX_NUM) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] Wrong LV=%d\n", pause_lv); + return PAUSE_FAIL; + } + + if (pause_func == F00_DIG) { + PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n"); + + if (val_lehgth != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] val_length != 1\n"); + return PAUSE_FAIL; + } + + ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value); /*0xc50*/ + pause_lv_pre = &dm->pause_lv_table.lv_dig; + bkp_val = (u32*)(&dm->dm_dig_table.rvrt_val); + dm->phydm_func_handler.pause_phydm_handler = phydm_set_dig_val; /*function pointer hook*/ + + } else + +#ifdef PHYDM_SUPPORT_CCKPD + if (pause_func == F05_CCK_PD) { + + PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n"); + + if (val_lehgth != 2) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] val_length != 2\n"); + return PAUSE_FAIL; + } + + ori_val[0] = dm->dm_cckpd_table.cur_cck_cca_thres; /*0xa0a*/ + ori_val[1] = dm->dm_cckpd_table.cck_cca_th_aaa; /*0xaaa*/ + pause_lv_pre = &dm->pause_lv_table.lv_cckpd; + bkp_val = &dm->dm_cckpd_table.rvrt_val[0]; + dm->phydm_func_handler.pause_phydm_handler = phydm_set_cckpd_val; /*function pointer hook*/ + + } else #endif - odm_false_alarm_counter_statistics(p_dm_odm); - phydm_noisy_detection(p_dm_odm); - odm_rssi_monitor_check(p_dm_odm); +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + if (pause_func == F06_ANT_DIV) { + PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n"); - if (*(p_dm_odm->p_is_power_saving) == true) { - odm_dig_by_rssi_lps(p_dm_odm); - phydm_adaptivity(p_dm_odm); -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - odm_antenna_diversity(p_dm_odm); /*enable AntDiv in PS mode, request from SD4 Jeff*/ + if (val_lehgth != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] val_length != 1\n"); + return PAUSE_FAIL; + } + + ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant); /*default antenna*/ + pause_lv_pre = &dm->pause_lv_table.lv_antdiv; + bkp_val = (u32*)(&dm->dm_fat_table.rvrt_val); + dm->phydm_func_handler.pause_phydm_handler = phydm_set_antdiv_val; /*function pointer hook*/ + + } else #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("DMWatchdog in power saving mode\n")); + + if (pause_func == F13_ADPTVTY) { + PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n"); + + if (val_lehgth != 2) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] val_length != 2\n"); + return PAUSE_FAIL; + } + + ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/ + ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/ + pause_lv_pre = &dm->pause_lv_table.lv_adapt; + bkp_val = (u32 *)(&dm->adaptivity.rvrt_val); + dm->phydm_func_handler.pause_phydm_handler = phydm_set_edcca_val; /*function pointer hook*/ + + } else + + { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n"); + return PAUSE_FAIL; + } + + PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n", pause_lv, *pause_lv_pre); + + if ((pause_type == PHYDM_PAUSE) || (pause_type == PHYDM_PAUSE_NO_SET)) { + if (pause_lv <= *pause_lv_pre) { + PHYDM_DBG(dm, ODM_COMP_API, "[PAUSE FAIL] Pre_LV >= Curr_LV\n"); + return PAUSE_FAIL; + } + + if (!(dm->pause_ability & pause_func_bitmap)) { + for (i = 0; i < val_lehgth; i ++) + bkp_val[i] = ori_val[i]; + } + + dm->pause_ability |= pause_func_bitmap; + PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n", dm->pause_ability); + + if (pause_type == PHYDM_PAUSE) { + for (i = 0; i < val_lehgth; i ++) { + PHYDM_DBG(dm, ODM_COMP_API, "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",i, val_buf[i], bkp_val[i]); + /**/ + } + dm->phydm_func_handler.pause_phydm_handler(dm, val_buf, val_lehgth); + } else { + for (i = 0; i < val_lehgth; i ++) { + PHYDM_DBG(dm, ODM_COMP_API, "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",i, bkp_val[i]); + /**/ + } + } + + *pause_lv_pre = pause_lv; + return PAUSE_SUCCESS; + + } else if (pause_type == PHYDM_RESUME) { + dm->pause_ability &= ~pause_func_bitmap; + PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n", dm->pause_ability); + + *pause_lv_pre = PHYDM_PAUSE_RELEASE; + + for (i = 0; i < val_lehgth; i ++) { + PHYDM_DBG(dm, ODM_COMP_API, "[RESUME] val_idx[%d]={0x%x}\n", i, bkp_val[i]); + } + + dm->phydm_func_handler.pause_phydm_handler(dm, bkp_val, val_lehgth); + + return PAUSE_SUCCESS; + } else { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n"); + return PAUSE_FAIL; + } + +} + +void +phydm_pause_func_console( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 i; + u8 val_length = 0; + u32 val_buf[5] = {0}; + u8 set_result = 0; + enum phydm_func_idx func = (enum phydm_func_idx)0; + enum phydm_pause_type pause_type = (enum phydm_pause_type)0; + enum phydm_pause_level pause_lv = (enum phydm_pause_level)0; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, "{Func} {1:pause, 2:Resume} {lv} Val[5:0]\n"); + + } else { + for (i = 0; i < 10; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + } + } + + func = (enum phydm_func_idx)var1[0]; + pause_type = (enum phydm_pause_type)var1[1]; + pause_lv = (enum phydm_pause_level)var1[2]; + + + for (i = 0; i < 5; i++) { + val_buf[i] = var1[3 + i]; + } + + if (func == F00_DIG) { + PDM_SNPF(out_len, used, output + used, out_len - used, "[DIG]\n"); + val_length = 1; + + } else if (func == F05_CCK_PD) { + PDM_SNPF(out_len, used, output + used, out_len - used, "[CCK_PD]\n"); + val_length = 2; + } else if (func == F06_ANT_DIV) { + PDM_SNPF(out_len, used, output + used, out_len - used, "[Ant_Div]\n"); + val_length = 1; + } else if (func == F13_ADPTVTY) { + PDM_SNPF(out_len, used, output + used, out_len - used, "[Adaptivity]\n"); + val_length = 2; + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, "[Set Function Error]\n"); + val_length = 0; + } + + if (val_length != 0) { + + PDM_SNPF(out_len, used, output + used, out_len - used, "{%s, lv=%d} val = %d, %d}\n", + ((pause_type == PHYDM_PAUSE) ? "Pause" : "Resume"), + pause_lv, var1[3], var1[4]); + + set_result= phydm_pause_func(dm, func, pause_type, pause_lv, val_length, val_buf); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, "set_result = %d\n", + set_result); + } + + + *_used = used; + *_out_len = out_len; +} + +u8 +phydm_stop_dm_watchdog_check( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->disable_phydm_watchdog == 1) { + PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n"); + return true; + } else + return false; + +} + +/* + * 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. + * You can not add any dummy function here, be care, you can only use DM structure + * to perform any new ODM_DM. + * */ +void +phydm_watchdog( + struct dm_struct *dm +) +{ + PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__); + + phydm_common_info_self_update(dm); + phydm_rssi_monitor_check(dm); + phydm_basic_dbg_message(dm); + phydm_auto_dbg_engine(dm); + phydm_receiver_blocking(dm); + + if (phydm_stop_dm_watchdog_check(dm) == true) return; + + phydm_hw_setting(dm); + + #ifdef PHYDM_TDMA_DIG_SUPPORT + if (dm->original_dig_restore == 0) + phydm_tdma_dig_timer_check(dm); + else + #endif + { + odm_false_alarm_counter_statistics(dm); + phydm_noisy_detection(dm); + phydm_dig(dm); + phydm_cck_pd_th(dm); } - phydm_check_adaptivity(p_dm_odm); - odm_update_power_training_state(p_dm_odm); - odm_DIG(p_dm_odm); - phydm_adaptivity(p_dm_odm); -#if PHYDM_SUPPORT_CCKPD - odm_cck_packet_detection_thresh(p_dm_odm); +#ifdef PHYDM_POWER_TRAINING_SUPPORT + phydm_update_power_training_state(dm); #endif - - phydm_ra_info_watchdog(p_dm_odm); - phydm_receiver_blocking(p_dm_odm); - odm_path_diversity(p_dm_odm); - odm_cfo_tracking(p_dm_odm); - odm_dynamic_tx_power(p_dm_odm); - odm_antenna_diversity(p_dm_odm); -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_dynamic_rx_path(p_dm_odm); + phydm_adaptivity(dm); + phydm_ra_info_watchdog(dm); + odm_path_diversity(dm); + phydm_cfo_tracking(dm); + /* odm_dynamic_tx_power(dm); */ + phydm_dynamic_tx_power(dm); + odm_antenna_diversity(dm); + phydm_adaptive_soml(dm); +#ifdef CONFIG_DYNAMIC_RX_PATH + phydm_dynamic_rx_path(dm); #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - phydm_beamforming_watchdog(p_dm_odm); + phydm_beamforming_watchdog(dm); #endif - halrf_watchdog(p_dm_odm); - phydm_primary_cca(p_dm_odm); + halrf_watchdog(dm); + phydm_primary_cca(dm); #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - odm_dtc(p_dm_odm); + odm_dtc(dm); +#endif + + phydm_env_mntr_watchdog(dm); + +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + phydm_lna_sat_chk_watchdog(dm); #endif - odm_common_info_self_reset(p_dm_odm); + phydm_common_info_self_reset(dm); } @@ -1946,9 +1891,9 @@ odm_dm_watchdog( * */ void odm_cmn_info_init( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_cmninfo_e cmn_info, - u32 value + struct dm_struct *dm, + enum odm_cmninfo cmn_info, + u64 value ) { /* */ @@ -1959,172 +1904,177 @@ odm_cmn_info_init( /* Fixed ODM value. */ /* */ case ODM_CMNINFO_ABILITY: - p_dm_odm->support_ability = (u32)value; + dm->support_ability = (u64)value; break; case ODM_CMNINFO_RF_TYPE: - p_dm_odm->rf_type = (u8)value; + dm->rf_type = (u8)value; break; case ODM_CMNINFO_PLATFORM: - p_dm_odm->support_platform = (u8)value; + dm->support_platform = (u8)value; break; case ODM_CMNINFO_INTERFACE: - p_dm_odm->support_interface = (u8)value; + dm->support_interface = (u8)value; break; case ODM_CMNINFO_MP_TEST_CHIP: - p_dm_odm->is_mp_chip = (u8)value; + dm->is_mp_chip = (u8)value; break; case ODM_CMNINFO_IC_TYPE: - p_dm_odm->support_ic_type = value; + dm->support_ic_type = (u32)value; break; case ODM_CMNINFO_CUT_VER: - p_dm_odm->cut_version = (u8)value; + dm->cut_version = (u8)value; break; case ODM_CMNINFO_FAB_VER: - p_dm_odm->fab_version = (u8)value; + dm->fab_version = (u8)value; break; case ODM_CMNINFO_RFE_TYPE: - p_dm_odm->rfe_type = (u8)value; - phydm_init_hw_info_by_rfe(p_dm_odm); + #if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821C) + dm->rfe_type_expand = (u8)value; /**/ + else + #endif + dm->rfe_type = (u8)value; + phydm_init_hw_info_by_rfe(dm); break; case ODM_CMNINFO_RF_ANTENNA_TYPE: - p_dm_odm->ant_div_type = (u8)value; + dm->ant_div_type = (u8)value; break; case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH: - p_dm_odm->with_extenal_ant_switch = (u8)value; + dm->with_extenal_ant_switch = (u8)value; break; case ODM_CMNINFO_BE_FIX_TX_ANT: - p_dm_odm->dm_fat_table.b_fix_tx_ant = (u8)value; + dm->dm_fat_table.b_fix_tx_ant = (u8)value; break; case ODM_CMNINFO_BOARD_TYPE: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->board_type = (u8)value; + if (!dm->is_init_hw_info_by_rfe) + dm->board_type = (u8)value; break; case ODM_CMNINFO_PACKAGE_TYPE: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->package_type = (u8)value; + if (!dm->is_init_hw_info_by_rfe) + dm->package_type = (u8)value; break; case ODM_CMNINFO_EXT_LNA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->ext_lna = (u8)value; + if (!dm->is_init_hw_info_by_rfe) + dm->ext_lna = (u8)value; break; case ODM_CMNINFO_5G_EXT_LNA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->ext_lna_5g = (u8)value; + if (!dm->is_init_hw_info_by_rfe) + dm->ext_lna_5g = (u8)value; break; case ODM_CMNINFO_EXT_PA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->ext_pa = (u8)value; + if (!dm->is_init_hw_info_by_rfe) + dm->ext_pa = (u8)value; break; case ODM_CMNINFO_5G_EXT_PA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->ext_pa_5g = (u8)value; + if (!dm->is_init_hw_info_by_rfe) + dm->ext_pa_5g = (u8)value; break; case ODM_CMNINFO_GPA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->type_gpa = (u16)value; + if (!dm->is_init_hw_info_by_rfe) + dm->type_gpa = (u16)value; break; case ODM_CMNINFO_APA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->type_apa = (u16)value; + if (!dm->is_init_hw_info_by_rfe) + dm->type_apa = (u16)value; break; case ODM_CMNINFO_GLNA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->type_glna = (u16)value; + if (!dm->is_init_hw_info_by_rfe) + dm->type_glna = (u16)value; break; case ODM_CMNINFO_ALNA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->type_alna = (u16)value; + if (!dm->is_init_hw_info_by_rfe) + dm->type_alna = (u16)value; break; case ODM_CMNINFO_EXT_TRSW: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->ext_trsw = (u8)value; + if (!dm->is_init_hw_info_by_rfe) + dm->ext_trsw = (u8)value; break; case ODM_CMNINFO_EXT_LNA_GAIN: - p_dm_odm->ext_lna_gain = (u8)value; + dm->ext_lna_gain = (u8)value; break; case ODM_CMNINFO_PATCH_ID: - p_dm_odm->patch_id = (u8)value; + dm->iot_table.win_patch_id = (u8)value; break; case ODM_CMNINFO_BINHCT_TEST: - p_dm_odm->is_in_hct_test = (boolean)value; + dm->is_in_hct_test = (boolean)value; break; case ODM_CMNINFO_BWIFI_TEST: - p_dm_odm->wifi_test = (u8)value; + dm->wifi_test = (u8)value; break; case ODM_CMNINFO_SMART_CONCURRENT: - p_dm_odm->is_dual_mac_smart_concurrent = (boolean)value; + dm->is_dual_mac_smart_concurrent = (boolean)value; break; case ODM_CMNINFO_DOMAIN_CODE_2G: - p_dm_odm->odm_regulation_2_4g = (u8)value; + dm->odm_regulation_2_4g = (u8)value; break; case ODM_CMNINFO_DOMAIN_CODE_5G: - p_dm_odm->odm_regulation_5g = (u8)value; + dm->odm_regulation_5g = (u8)value; break; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) case ODM_CMNINFO_CONFIG_BB_RF: - p_dm_odm->config_bbrf = (boolean)value; - break; - case ODM_CMNINFO_IQKFWOFFLOAD: - p_dm_odm->iqk_fw_offload = (u8)value; + dm->config_bbrf = (boolean)value; break; +#endif case ODM_CMNINFO_IQKPAOFF: - p_dm_odm->rf_calibrate_info.is_iqk_pa_off = (boolean)value; + dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value; break; case ODM_CMNINFO_REGRFKFREEENABLE: - p_dm_odm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value; + dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value; break; case ODM_CMNINFO_RFKFREEENABLE: - p_dm_odm->rf_calibrate_info.rf_kfree_enable = (u8)value; + dm->rf_calibrate_info.rf_kfree_enable = (u8)value; break; case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE: - p_dm_odm->normal_rx_path = (u8)value; + dm->normal_rx_path = (u8)value; break; case ODM_CMNINFO_EFUSE0X3D8: - p_dm_odm->efuse0x3d8 = (u8)value; + dm->efuse0x3d8 = (u8)value; break; case ODM_CMNINFO_EFUSE0X3D7: - p_dm_odm->efuse0x3d7 = (u8)value; + dm->efuse0x3d7 = (u8)value; break; case ODM_CMNINFO_ADVANCE_OTA: - p_dm_odm->p_advance_ota = (u8)value; + dm->p_advance_ota = (u8)value; break; + #ifdef CONFIG_PHYDM_DFS_MASTER case ODM_CMNINFO_DFS_REGION_DOMAIN: - p_dm_odm->dfs_region_domain = (u8)value; + dm->dfs_region_domain = (u8)value; break; #endif case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING: - p_dm_odm->soft_ap_special_setting = (u32)value; + dm->soft_ap_special_setting = (u32)value; break; case ODM_CMNINFO_DPK_EN: - /*p_dm_odm->dpk_en = (u1Byte)value;*/ - halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_DPK_EN, (u64)value); + /*dm->dpk_en = (u1Byte)value;*/ + halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value); break; case ODM_CMNINFO_HP_HWID: - p_dm_odm->is_hp_hw_id = (boolean)value; + dm->hp_hw_id = (boolean)value; break; /* To remove the compiler warning, must add an empty default statement to handle the other values. */ default: @@ -2138,9 +2088,9 @@ odm_cmn_info_init( void odm_cmn_info_hook( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_cmninfo_e cmn_info, - void *p_value + struct dm_struct *dm, + enum odm_cmninfo cmn_info, + void *value ) { /* */ @@ -2150,147 +2100,139 @@ odm_cmn_info_hook( /* */ /* Dynamic call by reference pointer. */ /* */ - case ODM_CMNINFO_MAC_PHY_MODE: - p_dm_odm->p_mac_phy_mode = (u8 *)p_value; - break; - case ODM_CMNINFO_TX_UNI: - p_dm_odm->p_num_tx_bytes_unicast = (u64 *)p_value; + dm->num_tx_bytes_unicast = (u64 *)value; break; case ODM_CMNINFO_RX_UNI: - p_dm_odm->p_num_rx_bytes_unicast = (u64 *)p_value; - break; - - case ODM_CMNINFO_WM_MODE: - p_dm_odm->p_wireless_mode = (u8 *)p_value; + dm->num_rx_bytes_unicast = (u64 *)value; break; case ODM_CMNINFO_BAND: - p_dm_odm->p_band_type = (u8 *)p_value; + dm->band_type = (u8 *)value; break; case ODM_CMNINFO_SEC_CHNL_OFFSET: - p_dm_odm->p_sec_ch_offset = (u8 *)p_value; + dm->sec_ch_offset = (u8 *)value; break; case ODM_CMNINFO_SEC_MODE: - p_dm_odm->p_security = (u8 *)p_value; + dm->security = (u8 *)value; break; case ODM_CMNINFO_BW: - p_dm_odm->p_band_width = (u8 *)p_value; + dm->band_width = (u8 *)value; break; case ODM_CMNINFO_CHNL: - p_dm_odm->p_channel = (u8 *)p_value; - break; - - case ODM_CMNINFO_DMSP_GET_VALUE: - p_dm_odm->p_is_get_value_from_other_mac = (boolean *)p_value; - break; - - case ODM_CMNINFO_BUDDY_ADAPTOR: - p_dm_odm->p_buddy_adapter = (struct _ADAPTER **)p_value; - break; - - case ODM_CMNINFO_DMSP_IS_MASTER: - p_dm_odm->p_is_master_of_dmsp = (boolean *)p_value; + dm->channel = (u8 *)value; break; case ODM_CMNINFO_SCAN: - p_dm_odm->p_is_scan_in_process = (boolean *)p_value; + dm->is_scan_in_process = (boolean *)value; break; case ODM_CMNINFO_POWER_SAVING: - p_dm_odm->p_is_power_saving = (boolean *)p_value; + dm->is_power_saving = (boolean *)value; break; case ODM_CMNINFO_ONE_PATH_CCA: - p_dm_odm->p_one_path_cca = (u8 *)p_value; + dm->one_path_cca = (u8 *)value; break; case ODM_CMNINFO_DRV_STOP: - p_dm_odm->p_is_driver_stopped = (boolean *)p_value; + dm->is_driver_stopped = (boolean *)value; break; case ODM_CMNINFO_PNP_IN: - p_dm_odm->p_is_driver_is_going_to_pnp_set_power_sleep = (boolean *)p_value; + dm->is_driver_is_going_to_pnp_set_power_sleep = (boolean *)value; break; case ODM_CMNINFO_INIT_ON: - p_dm_odm->pinit_adpt_in_progress = (boolean *)p_value; + dm->pinit_adpt_in_progress = (boolean *)value; break; case ODM_CMNINFO_ANT_TEST: - p_dm_odm->p_antenna_test = (u8 *)p_value; + dm->antenna_test = (u8 *)value; break; case ODM_CMNINFO_NET_CLOSED: - p_dm_odm->p_is_net_closed = (boolean *)p_value; + dm->is_net_closed = (boolean *)value; break; case ODM_CMNINFO_FORCED_RATE: - p_dm_odm->p_forced_data_rate = (u16 *)p_value; + dm->forced_data_rate = (u16 *)value; break; - case ODM_CMNINFO_ANT_DIV: - p_dm_odm->p_enable_antdiv = (u8 *)p_value; + case ODM_CMNINFO_ANT_DIV: + dm->enable_antdiv = (u8 *)value; break; - case ODM_CMNINFO_ADAPTIVITY: - p_dm_odm->p_enable_adaptivity = (u8 *)p_value; + + case ODM_CMNINFO_ADAPTIVE_SOML: + dm->en_adap_soml = (u8 *)value; break; - case ODM_CMNINFO_FORCED_IGI_LB: - p_dm_odm->pu1_forced_igi_lb = (u8 *)p_value; + + case ODM_CMNINFO_ADAPTIVITY: + dm->enable_adaptivity = (u8 *)value; break; case ODM_CMNINFO_P2P_LINK: - p_dm_odm->dm_dig_table.is_p2p_in_process = (u8 *)p_value; + dm->dm_dig_table.is_p2p_in_process = (u8 *)value; break; case ODM_CMNINFO_IS1ANTENNA: - p_dm_odm->p_is_1_antenna = (boolean *)p_value; + dm->is_1_antenna = (boolean *)value; break; case ODM_CMNINFO_RFDEFAULTPATH: - p_dm_odm->p_rf_default_path = (u8 *)p_value; + dm->rf_default_path = (u8 *)value; break; case ODM_CMNINFO_FCS_MODE: - p_dm_odm->p_is_fcs_mode_enable = (boolean *)p_value; + dm->is_fcs_mode_enable = (boolean *)value; break; /*add by YuChen for beamforming PhyDM*/ case ODM_CMNINFO_HUBUSBMODE: - p_dm_odm->hub_usb_mode = (u8 *)p_value; + dm->hub_usb_mode = (u8 *)value; break; case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS: - p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = (boolean *)p_value; + dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value; break; case ODM_CMNINFO_TX_TP: - p_dm_odm->p_current_tx_tp = (u32 *)p_value; + dm->current_tx_tp = (u32 *)value; break; case ODM_CMNINFO_RX_TP: - p_dm_odm->p_current_rx_tp = (u32 *)p_value; + dm->current_rx_tp = (u32 *)value; break; case ODM_CMNINFO_SOUNDING_SEQ: - p_dm_odm->p_sounding_seq = (u8 *)p_value; + dm->sounding_seq = (u8 *)value; break; #ifdef CONFIG_PHYDM_DFS_MASTER case ODM_CMNINFO_DFS_MASTER_ENABLE: - p_dm_odm->dfs_master_enabled = (u8 *)p_value; + dm->dfs_master_enabled = (u8 *)value; break; #endif case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC: - p_dm_odm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)p_value; + dm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)value; break; case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA: - p_dm_odm->dm_fat_table.p_default_s0_s1 = (u8 *)p_value; + dm->dm_fat_table.p_default_s0_s1 = (u8 *)value; break; case ODM_CMNINFO_SOFT_AP_MODE: - p_dm_odm->p_soft_ap_mode = (u32 *)p_value; + dm->soft_ap_mode = (u32 *)value; break; case ODM_CMNINFO_MP_MODE: - p_dm_odm->p_mp_mode = (u8 *)p_value; + dm->mp_mode = (u8 *)value; + break; + case ODM_CMNINFO_INTERRUPT_MASK: + dm->interrupt_mask = (u32 *)value; + break; + case ODM_CMNINFO_BB_OPERATION_MODE: + dm->bb_op_mode = (u8 *)value; break; + case ODM_CMNINFO_BF_ANTDIV_DECISION: + dm->dm_fat_table.is_no_csi_feedback = (boolean *)value; + break; + default: /*do nothing*/ break; @@ -2303,7 +2245,7 @@ odm_cmn_info_hook( * */ void odm_cmn_info_update( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 cmn_info, u64 value ) @@ -2313,139 +2255,113 @@ odm_cmn_info_update( /* */ switch (cmn_info) { case ODM_CMNINFO_LINK_IN_PROGRESS: - p_dm_odm->is_link_in_process = (boolean)value; + dm->is_link_in_process = (boolean)value; break; case ODM_CMNINFO_ABILITY: - p_dm_odm->support_ability = (u32)value; + dm->support_ability = (u64)value; break; case ODM_CMNINFO_RF_TYPE: - p_dm_odm->rf_type = (u8)value; + dm->rf_type = (u8)value; break; case ODM_CMNINFO_WIFI_DIRECT: - p_dm_odm->is_wifi_direct = (boolean)value; + dm->is_wifi_direct = (boolean)value; break; case ODM_CMNINFO_WIFI_DISPLAY: - p_dm_odm->is_wifi_display = (boolean)value; + dm->is_wifi_display = (boolean)value; break; case ODM_CMNINFO_LINK: - p_dm_odm->is_linked = (boolean)value; - break; - - case ODM_CMNINFO_CMW500LINK: - p_dm_odm->bLinkedcmw500 = (boolean)value; + dm->is_linked = (boolean)value; break; - case ODM_CMNINFO_LPSPG: - p_dm_odm->is_in_lps_pg = (boolean)value; + case ODM_CMNINFO_CMW500LINK: + dm->iot_table.is_linked_cmw500 = (boolean)value; break; case ODM_CMNINFO_STATION_STATE: - p_dm_odm->bsta_state = (boolean)value; + dm->bsta_state = (boolean)value; break; case ODM_CMNINFO_RSSI_MIN: - p_dm_odm->rssi_min = (u8)value; + dm->rssi_min = (u8)value; break; case ODM_CMNINFO_RSSI_MIN_BY_PATH: - p_dm_odm->rssi_min_by_path = (u8)value; + dm->rssi_min_by_path = (u8)value; break; case ODM_CMNINFO_DBG_COMP: - p_dm_odm->debug_components = (u32)value; + dm->debug_components = (u64)value; break; case ODM_CMNINFO_DBG_LEVEL: - p_dm_odm->debug_level = (u32)value; - break; - case ODM_CMNINFO_RA_THRESHOLD_HIGH: - p_dm_odm->rate_adaptive.high_rssi_thresh = (u8)value; + dm->debug_level = (u32)value; break; - case ODM_CMNINFO_RA_THRESHOLD_LOW: - p_dm_odm->rate_adaptive.low_rssi_thresh = (u8)value; - break; -#if defined(BT_SUPPORT) && (BT_SUPPORT == 1) +#ifdef ODM_CONFIG_BT_COEXIST /* The following is for BT HS mode and BT coexist mechanism. */ case ODM_CMNINFO_BT_ENABLED: - p_dm_odm->is_bt_enabled = (boolean)value; + dm->bt_info_table.is_bt_enabled = (boolean)value; break; case ODM_CMNINFO_BT_HS_CONNECT_PROCESS: - p_dm_odm->is_bt_connect_process = (boolean)value; + dm->bt_info_table.is_bt_connect_process = (boolean)value; break; case ODM_CMNINFO_BT_HS_RSSI: - p_dm_odm->bt_hs_rssi = (u8)value; + dm->bt_info_table.bt_hs_rssi = (u8)value; break; case ODM_CMNINFO_BT_OPERATION: - p_dm_odm->is_bt_hs_operation = (boolean)value; + dm->bt_info_table.is_bt_hs_operation = (boolean)value; break; case ODM_CMNINFO_BT_LIMITED_DIG: - p_dm_odm->is_bt_limited_dig = (boolean)value; + dm->bt_info_table.is_bt_limited_dig = (boolean)value; break; +#endif - case ODM_CMNINFO_BT_DIG: - p_dm_odm->bt_hs_dig_val = (u8)value; + case ODM_CMNINFO_AP_TOTAL_NUM: + dm->ap_total_num = (u8)value; break; - case ODM_CMNINFO_BT_BUSY: - p_dm_odm->is_bt_busy = (boolean)value; +#ifdef CONFIG_PHYDM_DFS_MASTER + case ODM_CMNINFO_DFS_REGION_DOMAIN: + dm->dfs_region_domain = (u8)value; break; +#endif - case ODM_CMNINFO_BT_DISABLE_EDCA: - p_dm_odm->is_bt_disable_edca_turbo = (boolean)value; + case ODM_CMNINFO_BT_CONTINUOUS_TURN: + dm->is_bt_continuous_turn = (boolean)value; break; -#endif - - case ODM_CMNINFO_AP_TOTAL_NUM: - p_dm_odm->ap_total_num = (u8)value; - break; - - case ODM_CMNINFO_POWER_TRAINING: - p_dm_odm->is_disable_power_training = (boolean)value; - break; - -#ifdef CONFIG_PHYDM_DFS_MASTER - case ODM_CMNINFO_DFS_REGION_DOMAIN: - p_dm_odm->dfs_region_domain = (u8)value; - break; -#endif #if 0 case ODM_CMNINFO_OP_MODE: - p_dm_odm->op_mode = (u8)value; - break; - - case ODM_CMNINFO_WM_MODE: - p_dm_odm->wireless_mode = (u8)value; + dm->op_mode = (u8)value; break; case ODM_CMNINFO_BAND: - p_dm_odm->band_type = (u8)value; + dm->band_type = (u8)value; break; case ODM_CMNINFO_SEC_CHNL_OFFSET: - p_dm_odm->sec_ch_offset = (u8)value; + dm->sec_ch_offset = (u8)value; break; case ODM_CMNINFO_SEC_MODE: - p_dm_odm->security = (u8)value; + dm->security = (u8)value; break; case ODM_CMNINFO_BW: - p_dm_odm->band_width = (u8)value; + dm->band_width = (u8)value; break; case ODM_CMNINFO_CHNL: - p_dm_odm->channel = (u8)value; + dm->channel = (u8)value; break; #endif default: @@ -2458,74 +2374,92 @@ odm_cmn_info_update( u32 phydm_cmn_info_query( - struct PHY_DM_STRUCT *p_dm_odm, - enum phydm_info_query_e info_type + struct dm_struct *dm, + enum phydm_info_query info_type ) { - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct ccx_info *ccx_info = &dm->dm_ccx_info; switch (info_type) { + /*=== [FA Relative] ===========================================*/ case PHYDM_INFO_FA_OFDM: - return false_alm_cnt->cnt_ofdm_fail; + return fa_t->cnt_ofdm_fail; case PHYDM_INFO_FA_CCK: - return false_alm_cnt->cnt_cck_fail; + return fa_t->cnt_cck_fail; case PHYDM_INFO_FA_TOTAL: - return false_alm_cnt->cnt_all; + return fa_t->cnt_all; case PHYDM_INFO_CCA_OFDM: - return false_alm_cnt->cnt_ofdm_cca; + return fa_t->cnt_ofdm_cca; case PHYDM_INFO_CCA_CCK: - return false_alm_cnt->cnt_cck_cca; + return fa_t->cnt_cck_cca; case PHYDM_INFO_CCA_ALL: - return false_alm_cnt->cnt_cca_all; + return fa_t->cnt_cca_all; case PHYDM_INFO_CRC32_OK_VHT: - return false_alm_cnt->cnt_vht_crc32_ok; + return fa_t->cnt_vht_crc32_ok; case PHYDM_INFO_CRC32_OK_HT: - return false_alm_cnt->cnt_ht_crc32_ok; + return fa_t->cnt_ht_crc32_ok; case PHYDM_INFO_CRC32_OK_LEGACY: - return false_alm_cnt->cnt_ofdm_crc32_ok; + return fa_t->cnt_ofdm_crc32_ok; case PHYDM_INFO_CRC32_OK_CCK: - return false_alm_cnt->cnt_cck_crc32_ok; + return fa_t->cnt_cck_crc32_ok; case PHYDM_INFO_CRC32_ERROR_VHT: - return false_alm_cnt->cnt_vht_crc32_error; + return fa_t->cnt_vht_crc32_error; case PHYDM_INFO_CRC32_ERROR_HT: - return false_alm_cnt->cnt_ht_crc32_error; + return fa_t->cnt_ht_crc32_error; case PHYDM_INFO_CRC32_ERROR_LEGACY: - return false_alm_cnt->cnt_ofdm_crc32_error; + return fa_t->cnt_ofdm_crc32_error; case PHYDM_INFO_CRC32_ERROR_CCK: - return false_alm_cnt->cnt_cck_crc32_error; + return fa_t->cnt_cck_crc32_error; case PHYDM_INFO_EDCCA_FLAG: - return false_alm_cnt->edcca_flag; + return fa_t->edcca_flag; case PHYDM_INFO_OFDM_ENABLE: - return false_alm_cnt->ofdm_block_enable; + return fa_t->ofdm_block_enable; case PHYDM_INFO_CCK_ENABLE: - return false_alm_cnt->cck_block_enable; + return fa_t->cck_block_enable; case PHYDM_INFO_DBG_PORT_0: - return false_alm_cnt->dbg_port0; + return fa_t->dbg_port0; case PHYDM_INFO_CRC32_OK_HT_AGG: - return false_alm_cnt->cnt_ht_crc32_ok_agg; + return fa_t->cnt_ht_crc32_ok_agg; case PHYDM_INFO_CRC32_ERROR_HT_AGG: - return false_alm_cnt->cnt_ht_crc32_error_agg; - + return fa_t->cnt_ht_crc32_error_agg; + + /*=== [DIG] ================================================*/ + + case PHYDM_INFO_CURR_IGI: + return dig_t->cur_ig_value; + /*=== [RSSI] ===============================================*/ + case PHYDM_INFO_RSSI_MIN: + return (u32)dm->rssi_min; + + case PHYDM_INFO_RSSI_MAX: + return (u32)dm->rssi_max; + + case PHYDM_INFO_CLM_RATIO : + return (u32)ccx_info->clm_ratio; + case PHYDM_INFO_NHM_RATIO : + return (u32)ccx_info->nhm_ratio; default: return 0xffffffff; @@ -2535,75 +2469,76 @@ phydm_cmn_info_query( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void -odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm) +odm_init_all_work_items(struct dm_struct *dm) { - - struct _ADAPTER *p_adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; #if USE_WORKITEM -#if CONFIG_DYNAMIC_RX_PATH - odm_initialize_work_item(p_dm_odm, - &p_dm_odm->dm_drp_table.phydm_dynamic_rx_path_workitem, +#ifdef CONFIG_DYNAMIC_RX_PATH + odm_initialize_work_item(dm, + &dm->dm_drp_table.phydm_dynamic_rx_path_workitem, (RT_WORKITEM_CALL_BACK)phydm_dynamic_rx_path_workitem_callback, - (void *)p_adapter, + (void *)adapter, "DynamicRxPathWorkitem"); #endif + +#ifdef CONFIG_ADAPTIVE_SOML + odm_initialize_work_item(dm, + &dm->dm_soml_table.phydm_adaptive_soml_workitem, + (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback, + (void *)adapter, + "AdaptiveSOMLWorkitem"); +#endif + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_initialize_work_item(p_dm_odm, - &p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_workitem, + odm_initialize_work_item(dm, + &dm->dm_swat_table.phydm_sw_antenna_switch_workitem, (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback, - (void *)p_adapter, + (void *)adapter, "AntennaSwitchWorkitem"); #endif -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) - odm_initialize_work_item(p_dm_odm, - &p_dm_odm->dm_sat_table.hl_smart_antenna_workitem, +#if (defined(CONFIG_HL_SMART_ANTENNA)) + odm_initialize_work_item(dm, + &dm->dm_sat_table.hl_smart_antenna_workitem, (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback, - (void *)p_adapter, + (void *)adapter, "hl_smart_ant_workitem"); - odm_initialize_work_item(p_dm_odm, - &p_dm_odm->dm_sat_table.hl_smart_antenna_decision_workitem, + odm_initialize_work_item(dm, + &dm->dm_sat_table.hl_smart_antenna_decision_workitem, (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback, - (void *)p_adapter, + (void *)adapter, "hl_smart_ant_decision_workitem"); #endif odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->path_div_switch_workitem), + dm, + &dm->path_div_switch_workitem, (RT_WORKITEM_CALL_BACK)odm_path_div_chk_ant_switch_workitem_callback, - (void *)p_adapter, + (void *)adapter, "SWAS_WorkItem"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->cck_path_diversity_workitem), + dm, + &dm->cck_path_diversity_workitem, (RT_WORKITEM_CALL_BACK)odm_cck_tx_path_diversity_work_item_callback, - (void *)p_adapter, + (void *)adapter, "CCKTXPathDiversityWorkItem"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->mpt_dig_workitem), - (RT_WORKITEM_CALL_BACK)odm_mpt_dig_work_item_callback, - (void *)p_adapter, - "mpt_dig_workitem"); - - odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->ra_rpt_workitem), - (RT_WORKITEM_CALL_BACK)odm_update_init_rate_work_item_callback, - (void *)p_adapter, + dm, + &dm->ra_rpt_workitem, + (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback, + (void *)adapter, "ra_rpt_workitem"); #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->fast_ant_training_workitem), + dm, + &dm->fast_ant_training_workitem, (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback, - (void *)p_adapter, + (void *)adapter, "fast_ant_training_workitem"); #endif @@ -2611,227 +2546,183 @@ odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm) #if (BEAMFORMING_SUPPORT == 1) odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_enter_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_enter_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_enter_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_leave_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_leave_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_leave_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_fw_ndpa_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_clk_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_clk_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_clk_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_rate_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_rate_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_rate_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_status_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_status_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_status_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_reset_tx_path_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_get_tx_rate_work_item"); #endif odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->adaptivity.phydm_pause_edcca_work_item), + dm, + &dm->adaptivity.phydm_pause_edcca_work_item, (RT_WORKITEM_CALL_BACK)phydm_pause_edcca_work_item_callback, - (void *)p_adapter, + (void *)adapter, "phydm_pause_edcca_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->adaptivity.phydm_resume_edcca_work_item), + dm, + &dm->adaptivity.phydm_resume_edcca_work_item, (RT_WORKITEM_CALL_BACK)phydm_resume_edcca_work_item_callback, - (void *)p_adapter, + (void *)adapter, "phydm_resume_edcca_work_item"); #if (PHYDM_LA_MODE_SUPPORT == 1) odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->adcsmp.adc_smp_work_item), + dm, + &dm->adcsmp.adc_smp_work_item, (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback, - (void *)p_adapter, + (void *)adapter, "adc_smp_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->adcsmp.adc_smp_work_item_1), + dm, + &dm->adcsmp.adc_smp_work_item_1, (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback, - (void *)p_adapter, + (void *)adapter, "adc_smp_work_item_1"); #endif } void -odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm_odm) +odm_free_all_work_items(struct dm_struct *dm) { #if USE_WORKITEM #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_free_work_item(&(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_workitem)); + odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem); #endif -#if CONFIG_DYNAMIC_RX_PATH - odm_free_work_item(&(p_dm_odm->dm_drp_table.phydm_dynamic_rx_path_workitem)); +#ifdef CONFIG_DYNAMIC_RX_PATH + odm_free_work_item(&dm->dm_drp_table.phydm_dynamic_rx_path_workitem); #endif +#ifdef CONFIG_ADAPTIVE_SOML + odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem); +#endif -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) - odm_free_work_item(&(p_dm_odm->dm_sat_table.hl_smart_antenna_workitem)); - odm_free_work_item(&(p_dm_odm->dm_sat_table.hl_smart_antenna_decision_workitem)); +#if (defined(CONFIG_HL_SMART_ANTENNA)) + odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem); + odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem); #endif - odm_free_work_item(&(p_dm_odm->path_div_switch_workitem)); - odm_free_work_item(&(p_dm_odm->cck_path_diversity_workitem)); + odm_free_work_item(&dm->path_div_switch_workitem); + odm_free_work_item(&dm->cck_path_diversity_workitem); #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - odm_free_work_item(&(p_dm_odm->fast_ant_training_workitem)); + odm_free_work_item(&dm->fast_ant_training_workitem); #endif - odm_free_work_item(&(p_dm_odm->mpt_dig_workitem)); - odm_free_work_item(&(p_dm_odm->ra_rpt_workitem)); - /*odm_free_work_item((&p_dm_odm->sbdcnt_workitem));*/ + odm_free_work_item(&dm->ra_rpt_workitem); + /*odm_free_work_item((&dm->sbdcnt_workitem));*/ #endif #if (BEAMFORMING_SUPPORT == 1) - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_enter_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_leave_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_clk_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_rate_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_status_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item)); #endif - odm_free_work_item((&p_dm_odm->adaptivity.phydm_pause_edcca_work_item)); - odm_free_work_item((&p_dm_odm->adaptivity.phydm_resume_edcca_work_item)); + odm_free_work_item((&dm->adaptivity.phydm_pause_edcca_work_item)); + odm_free_work_item((&dm->adaptivity.phydm_resume_edcca_work_item)); #if (PHYDM_LA_MODE_SUPPORT == 1) - odm_free_work_item((&p_dm_odm->adcsmp.adc_smp_work_item)); - odm_free_work_item((&p_dm_odm->adcsmp.adc_smp_work_item_1)); + odm_free_work_item((&dm->adcsmp.adc_smp_work_item)); + odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1)); #endif } #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ -#if 0 -void -odm_FindMinimumRSSI( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - u32 i; - u8 rssi_min = 0xFF; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - /* if(p_dm_odm->p_odm_sta_info[i] != NULL) */ - if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[i])) { - if (p_dm_odm->p_odm_sta_info[i]->rssi_ave < rssi_min) - rssi_min = p_dm_odm->p_odm_sta_info[i]->rssi_ave; - } - } - - p_dm_odm->rssi_min = rssi_min; - -} - -void -odm_IsLinked( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - u32 i; - boolean Linked = false; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[i])) { - Linked = true; - break; - } - - } - - p_dm_odm->is_linked = Linked; -} -#endif - void odm_init_all_timers( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - odm_ant_div_timers(p_dm_odm, INIT_ANTDIV_TIMMER); + odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER); #endif -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_dynamic_rx_path_timers(p_dm_odm, INIT_DRP_TIMMER); -#endif + phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER); -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#ifdef MP_TEST - if (*(p_dm_odm->p_mp_mode)) - odm_initialize_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer, - (void *)odm_mpt_dig_callback, NULL, "mpt_dig_timer"); +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER); #endif -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - odm_initialize_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer, - (void *)odm_mpt_dig_callback, NULL, "mpt_dig_timer"); + +#ifdef CONFIG_DYNAMIC_RX_PATH + phydm_dynamic_rx_path_timers(dm, INIT_DRP_TIMMER); #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - odm_initialize_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer, + odm_initialize_timer(dm, &dm->path_div_switch_timer, (void *)odm_path_div_chk_ant_switch_callback, NULL, "PathDivTimer"); - odm_initialize_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer, + odm_initialize_timer(dm, &dm->cck_path_diversity_timer, (void *)odm_cck_tx_path_diversity_callback, NULL, "cck_path_diversity_timer"); - odm_initialize_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer, + odm_initialize_timer(dm, &dm->sbdcnt_timer, (void *)phydm_sbd_callback, NULL, "SbdTimer"); #if (BEAMFORMING_SUPPORT == 1) - odm_initialize_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer, + odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer, (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL, "txbf_fw_ndpa_timer"); #endif #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (BEAMFORMING_SUPPORT == 1) - odm_initialize_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer, + odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer, (void *)beamforming_sw_timer_callback, NULL, "beamforming_timer"); #endif #endif @@ -2839,47 +2730,42 @@ odm_init_all_timers( void odm_cancel_all_timers( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* */ - /* 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in */ - /* win7 platform. */ - /* */ - HAL_ADAPTER_STS_CHK(p_dm_odm); + /* 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/ + if (dm->adapter == NULL) + return; #endif #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - odm_ant_div_timers(p_dm_odm, CANCEL_ANTDIV_TIMMER); + odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER); #endif -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_dynamic_rx_path_timers(p_dm_odm, CANCEL_DRP_TIMMER); -#endif + phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER); -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#ifdef MP_TEST - if (*(p_dm_odm->p_mp_mode)) - odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER); #endif -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); + + +#ifdef CONFIG_DYNAMIC_RX_PATH + phydm_dynamic_rx_path_timers(dm, CANCEL_DRP_TIMMER); #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - odm_cancel_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer); - odm_cancel_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer); - odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); - odm_cancel_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer); + odm_cancel_timer(dm, &dm->path_div_switch_timer); + odm_cancel_timer(dm, &dm->cck_path_diversity_timer); + odm_cancel_timer(dm, &dm->sbdcnt_timer); #if (BEAMFORMING_SUPPORT == 1) - odm_cancel_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer); + odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer); #endif #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (BEAMFORMING_SUPPORT == 1) - odm_cancel_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer); + odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer); #endif #endif @@ -2888,191 +2774,63 @@ odm_cancel_all_timers( void odm_release_all_timers( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - odm_ant_div_timers(p_dm_odm, RELEASE_ANTDIV_TIMMER); + odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER); #endif + phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER); -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_dynamic_rx_path_timers(p_dm_odm, RELEASE_DRP_TIMMER); +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER); #endif -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#ifdef MP_TEST - if (*(p_dm_odm->p_mp_mode)) - odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); -#endif -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); +#ifdef CONFIG_DYNAMIC_RX_PATH + phydm_dynamic_rx_path_timers(dm, RELEASE_DRP_TIMMER); #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - odm_release_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer); - odm_release_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer); - odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); - odm_release_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer); + odm_release_timer(dm, &dm->path_div_switch_timer); + odm_release_timer(dm, &dm->cck_path_diversity_timer); + odm_release_timer(dm, &dm->sbdcnt_timer); #if (BEAMFORMING_SUPPORT == 1) - odm_release_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer); + odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer); #endif #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (BEAMFORMING_SUPPORT == 1) - odm_release_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer); + odm_release_timer(dm, &dm->beamforming_info.beamforming_timer); #endif #endif } - -/* 3============================================================ - * 3 Tx Power Tracking - * 3============================================================ */ - - - - #if (DM_ODM_SUPPORT_TYPE == ODM_AP) void odm_init_all_threads( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { #ifdef TPT_THREAD - k_tpt_task_init(p_dm_odm->priv); + k_tpt_task_init(dm->priv); #endif } void odm_stop_all_threads( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { #ifdef TPT_THREAD - k_tpt_task_stop(p_dm_odm->priv); -#endif -} -#endif - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -/* - * 2011/07/26 MH Add an API for testing IQK fail case. - * */ -boolean -odm_check_power_status( - struct _ADAPTER *adapter) -{ - - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - RT_RF_POWER_STATE rt_state; - PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); - - /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */ - if (p_mgnt_info->init_adpt_in_progress == true) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("odm_check_power_status Return true, due to initadapter\n")); - return true; - } - - /* */ - /* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */ - /* */ - adapter->HalFunc.GetHwRegHandler(adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state)); - if (adapter->bDriverStopped || adapter->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n", - adapter->bDriverStopped, adapter->bDriverIsGoingToPnpSetPowerSleep, rt_state)); - return false; - } - return true; -} -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) -boolean -odm_check_power_status( - struct _ADAPTER *adapter) -{ -#if 0 - /* HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); */ - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - RT_RF_POWER_STATE rt_state; - PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); - - /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */ - if (p_mgnt_info->init_adpt_in_progress == true) { - ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return true, due to initadapter")); - return true; - } - - /* */ - /* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */ - /* */ - phydm_get_hw_reg_interface(p_dm_odm, HW_VAR_RF_STATE, (u8 *)(&rt_state)); - if (adapter->is_driver_stopped || adapter->is_driver_is_going_to_pnp_set_power_sleep || rt_state == eRfOff) { - ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n", - adapter->is_driver_stopped, adapter->is_driver_is_going_to_pnp_set_power_sleep, rt_state)); - return false; - } + k_tpt_task_stop(dm->priv); #endif - return true; } #endif -/* need to ODM CE Platform - * move to here for ANT detection mechanism using */ - -u32 -odm_convert_to_db( - u32 value) -{ - u8 i; - u8 j; - u32 dB; - - value = value & 0xFFFF; - - for (i = 0; i < 12; i++) { - if (value <= db_invert_table[i][7]) - break; - } - - if (i >= 12) { - return 96; /* maximum 96 dB */ - } - - for (j = 0; j < 8; j++) { - if (value <= db_invert_table[i][j]) - break; - } - - dB = (i << 3) + j + 1; - - return dB; -} - -u32 -odm_convert_to_linear( - u32 value) -{ - u8 i; - u8 j; - u32 linear; - - /* 1dB~96dB */ - - value = value & 0xFF; - - i = (u8)((value - 1) >> 3); - j = (u8)(value - 1) - (i << 3); - - linear = db_invert_table[i][j]; - - return linear; -} - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */ -void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm) +void odm_dtc(struct dm_struct *dm) { #ifdef CONFIG_DM_RESP_TXAGC #define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */ @@ -3110,27 +2868,27 @@ void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm) #if 0 /* As DIG is disabled, DTC is also disable */ - if (!(p_dm_odm->support_ability & ODM_XXXXXX)) + if (!(dm->support_ability & ODM_XXXXXX)) return; #endif - if (DTC_BASE < p_dm_odm->rssi_min) { + if (dm->rssi_min > DTC_BASE) { /* need to decade the CTS TX power */ sign = 1; for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) { - if ((dtc_table_down[i] >= p_dm_odm->rssi_min) || (dtc_steps >= 6)) + if ((dtc_table_down[i] >= dm->rssi_min) || (dtc_steps >= 6)) break; else dtc_steps++; } } #if 0 - else if (DTC_DWN_BASE > p_dm_odm->rssi_min) { + else if (dm->rssi_min > DTC_DWN_BASE) { /* needs to increase the CTS TX power */ sign = 0; dtc_steps = 1; for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) { - if ((dtc_table_up[i] <= p_dm_odm->rssi_min) || (dtc_steps >= 10)) + if ((dtc_table_up[i] <= dm->rssi_min) || (dtc_steps >= 10)) break; else dtc_steps++; @@ -3144,922 +2902,99 @@ void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm) resp_txagc = dtc_steps | (sign << 4); resp_txagc = resp_txagc | (resp_txagc << 5); - odm_write_1byte(p_dm_odm, 0x06d9, resp_txagc); + odm_write_1byte(dm, 0x06d9, resp_txagc); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PWR_TRAIN, ODM_DBG_LOUD, ("%s rssi_min:%u, set RESP_TXAGC to %s %u\n", - __func__, p_dm_odm->rssi_min, sign ? "minus" : "plus", dtc_steps)); + PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN, "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", + __func__, dm->rssi_min, sign ? "minus" : "plus", dtc_steps); #endif /* CONFIG_RESP_TXAGC_ADJUST */ } #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ -void -odm_update_power_training_state( - struct PHY_DM_STRUCT *p_dm_odm -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u32 score = 0; - - if (!(p_dm_odm->support_ability & ODM_BB_PWR_TRAIN)) - return; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state()============>\n")); - p_dm_odm->is_change_state = false; - - /* Debug command */ - if (p_dm_odm->force_power_training_state) { - if (p_dm_odm->force_power_training_state == 1 && !p_dm_odm->is_disable_power_training) { - p_dm_odm->is_change_state = true; - p_dm_odm->is_disable_power_training = true; - } else if (p_dm_odm->force_power_training_state == 2 && p_dm_odm->is_disable_power_training) { - p_dm_odm->is_change_state = true; - p_dm_odm->is_disable_power_training = false; - } - - p_dm_odm->PT_score = 0; - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): force_power_training_state = %d\n", - p_dm_odm->force_power_training_state)); - return; - } - - if (!p_dm_odm->is_linked) - return; - - /* First connect */ - if ((p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == false)) { - p_dm_odm->PT_score = 0; - p_dm_odm->is_change_state = true; - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): First Connect\n")); - return; - } - - /* Compute score */ - if (p_dm_odm->nhm_cnt_0 >= 215) - score = 2; - else if (p_dm_odm->nhm_cnt_0 >= 190) - score = 1; /* unknow state */ - else { - u32 rx_pkt_cnt; - - rx_pkt_cnt = (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm) + (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_cck); - - if ((false_alm_cnt->cnt_cca_all > 31 && rx_pkt_cnt > 31) && (false_alm_cnt->cnt_cca_all >= rx_pkt_cnt)) { - if ((rx_pkt_cnt + (rx_pkt_cnt >> 1)) <= false_alm_cnt->cnt_cca_all) - score = 0; - else if ((rx_pkt_cnt + (rx_pkt_cnt >> 2)) <= false_alm_cnt->cnt_cca_all) - score = 1; - else - score = 2; - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): rx_pkt_cnt = %d, cnt_cca_all = %d\n", - rx_pkt_cnt, false_alm_cnt->cnt_cca_all)); - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): num_qry_phy_status_ofdm = %d, num_qry_phy_status_cck = %d\n", - (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm), (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_cck))); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): nhm_cnt_0 = %d, score = %d\n", - p_dm_odm->nhm_cnt_0, score)); - - /* smoothing */ - p_dm_odm->PT_score = (score << 4) + (p_dm_odm->PT_score >> 1) + (p_dm_odm->PT_score >> 2); - score = (p_dm_odm->PT_score + 32) >> 6; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): PT_score = %d, score after smoothing = %d\n", - p_dm_odm->PT_score, score)); - - /* mode decision */ - if (score == 2) { - if (p_dm_odm->is_disable_power_training) { - p_dm_odm->is_change_state = true; - p_dm_odm->is_disable_power_training = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Change state\n")); - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Enable Power Training\n")); - } else if (score == 0) { - if (!p_dm_odm->is_disable_power_training) { - p_dm_odm->is_change_state = true; - p_dm_odm->is_disable_power_training = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Change state\n")); - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Disable Power Training\n")); - } - - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; -#endif -} - - - -/*===========================================================*/ -/* The following is for compile only*/ -/*===========================================================*/ -/*#define TARGET_CHNL_NUM_2G_5G 59*/ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -u8 get_right_chnl_place_for_iqk(u8 chnl) -{ - u8 channel_all[TARGET_CHNL_NUM_2G_5G] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, - 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165 - }; - u8 place = chnl; - - - if (chnl > 14) { - for (place = 14; place < sizeof(channel_all); place++) { - if (channel_all[place] == chnl) - return place - 13; - } - } - - return 0; -} - -#endif -/*===========================================================*/ - -void -phydm_noisy_detection( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - u32 total_fa_cnt, total_cca_cnt; - u32 score = 0, i, score_smooth; - - total_cca_cnt = p_dm_odm->false_alm_cnt.cnt_cca_all; - total_fa_cnt = p_dm_odm->false_alm_cnt.cnt_all; - -#if 0 - if (total_fa_cnt * 16 >= total_cca_cnt * 14) /* 87.5 */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /* 75 */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /* 56.25 */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /* 50 */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /* 43.75 */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /* 37.5 */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /* 31.25% */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /* 25% */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /* 18.75% */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /* 12.5% */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /* 6.25% */ - ; -#endif - for (i = 0; i <= 16; i++) { - if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) { - score = 16 - i; - break; - } - } - - /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */ - p_dm_odm->noisy_decision_smooth = (p_dm_odm->noisy_decision_smooth >> 1) + (score << 2); - - /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */ - score_smooth = (total_cca_cnt >= 300) ? ((p_dm_odm->noisy_decision_smooth + 3) >> 3) : 0; - - p_dm_odm->noisy_decision = (score_smooth >= 3) ? 1 : 0; -#if 0 - switch (score_smooth) { - case 0: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=0%%\n")); - break; - case 1: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=6.25%%\n")); - break; - case 2: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=12.5%%\n")); - break; - case 3: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=18.75%%\n")); - break; - case 4: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=25%%\n")); - break; - case 5: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=31.25%%\n")); - break; - case 6: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=37.5%%\n")); - break; - case 7: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=43.75%%\n")); - break; - case 8: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=50%%\n")); - break; - case 9: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=56.25%%\n")); - break; - case 10: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=62.5%%\n")); - break; - case 11: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=68.75%%\n")); - break; - case 12: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=75%%\n")); - break; - case 13: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=81.25%%\n")); - break; - case 14: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=87.5%%\n")); - break; - case 15: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=93.75%%\n")); - break; - case 16: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=100%%\n")); - break; - default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Unknown value!! Need Check!!\n")); - } -#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, - ("[NoisyDetection] total_cca_cnt=%d, total_fa_cnt=%d, noisy_decision_smooth=%d, score=%d, score_smooth=%d, p_dm_odm->noisy_decision=%d\n", - total_cca_cnt, total_fa_cnt, p_dm_odm->noisy_decision_smooth, score, score_smooth, p_dm_odm->noisy_decision)); - -} - -void -phydm_set_ext_switch( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 ext_ant_switch = dm_value[0]; - - if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { - - /*Output Pin Settings*/ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /*select DPDT_P and DPDT_N as output pin*/ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /*by WLAN control*/ - - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/ - - if (ext_ant_switch == MAIN_ANT) { - odm_set_bb_reg(p_dm_odm, 0xCB4, (BIT(29) | BIT(28)), 1); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("***8821A set ant switch = 2b'01 (Main)\n")); - } else if (ext_ant_switch == AUX_ANT) { - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29) | BIT(28), 2); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("***8821A set ant switch = 2b'10 (Aux)\n")); - } - } -} - -void -phydm_csi_mask_enable( - void *p_dm_void, - u32 enable -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 reg_value = 0; - - reg_value = (enable == CSI_MASK_ENABLE) ? 1 : 0; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0xD2C, BIT(28), reg_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", reg_value)); - - } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0x874, BIT(0), reg_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", reg_value)); - } - -} - -void -phydm_clean_all_csi_mask( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0xD40, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0xD44, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0xD48, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0xD4c, MASKDWORD, 0); - - } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0x880, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x884, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x888, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x88c, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x890, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x894, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x898, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x89c, MASKDWORD, 0); - } -} - -void -phydm_set_csi_mask_reg( - void *p_dm_void, - u32 tone_idx_tmp, - u8 tone_direction -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 byte_offset, bit_offset; - u32 target_reg; - u8 reg_tmp_value; - u32 tone_num = 64; - u32 tone_num_shift = 0; - u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0; - - /* calculate real tone idx*/ - if ((tone_idx_tmp % 10) >= 5) - tone_idx_tmp += 10; - - tone_idx_tmp = (tone_idx_tmp / 10); - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - - tone_num = 64; - csi_mask_reg_p = 0xD40; - csi_mask_reg_n = 0xD48; - - } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - tone_num = 128; - csi_mask_reg_p = 0x880; - csi_mask_reg_n = 0x890; - } - - if (tone_direction == FREQ_POSITIVE) { - - if (tone_idx_tmp >= (tone_num - 1)) - tone_idx_tmp = (tone_num - 1); - - byte_offset = (u8)(tone_idx_tmp >> 3); - bit_offset = (u8)(tone_idx_tmp & 0x7); - target_reg = csi_mask_reg_p + byte_offset; - - } else { - tone_num_shift = tone_num; - - if (tone_idx_tmp >= tone_num) - tone_idx_tmp = tone_num; - - tone_idx_tmp = tone_num - tone_idx_tmp; - - byte_offset = (u8)(tone_idx_tmp >> 3); - bit_offset = (u8)(tone_idx_tmp & 0x7); - target_reg = csi_mask_reg_n + byte_offset; - } - - reg_tmp_value = odm_read_1byte(p_dm_odm, target_reg); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); - reg_tmp_value |= BIT(bit_offset); - odm_write_1byte(p_dm_odm, target_reg, reg_tmp_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); -} - -void -phydm_set_nbi_reg( - void *p_dm_void, - u32 tone_idx_tmp, - u32 bw -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 nbi_table_128[NBI_TABLE_SIZE_128] = {25, 55, 85, 115, 135, 155, 185, 205, 225, 245, /*1~10*/ /*tone_idx X 10*/ - 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/ - 485, 505, 525, 555, 585, 615, 635 - }; /*21~27*/ - - u32 nbi_table_256[NBI_TABLE_SIZE_256] = { 25, 55, 85, 115, 135, 155, 175, 195, 225, 245, /*1~10*/ - 265, 285, 305, 325, 345, 365, 385, 405, 425, 445, /*11~20*/ - 465, 485, 505, 525, 545, 565, 585, 605, 625, 645, /*21~30*/ - 665, 695, 715, 735, 755, 775, 795, 815, 835, 855, /*31~40*/ - 875, 895, 915, 935, 955, 975, 995, 1015, 1035, 1055, /*41~50*/ - 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275 - }; /*51~59*/ - - u32 reg_idx = 0; - u32 i; - u8 nbi_table_idx = FFT_128_TYPE; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - - nbi_table_idx = FFT_128_TYPE; - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_1_SERIES) - - nbi_table_idx = FFT_256_TYPE; - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_2_SERIES) { - - if (bw == 80) - nbi_table_idx = FFT_256_TYPE; - else /*20M, 40M*/ - nbi_table_idx = FFT_128_TYPE; - } - - if (nbi_table_idx == FFT_128_TYPE) { - - for (i = 0; i < NBI_TABLE_SIZE_128; i++) { - if (tone_idx_tmp < nbi_table_128[i]) { - reg_idx = i + 1; - break; - } - } - - } else if (nbi_table_idx == FFT_256_TYPE) { - - for (i = 0; i < NBI_TABLE_SIZE_256; i++) { - if (tone_idx_tmp < nbi_table_256[i]) { - reg_idx = i + 1; - break; - } - } - } - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - odm_set_bb_reg(p_dm_odm, 0xc40, 0x1f000000, reg_idx); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", reg_idx)); - /**/ - } else { - odm_set_bb_reg(p_dm_odm, 0x87c, 0xfc000, reg_idx); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", reg_idx)); - /**/ - } -} - - -void -phydm_nbi_enable( - void *p_dm_void, - u32 enable -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 reg_value = 0; - - reg_value = (enable == NBI_ENABLE) ? 1 : 0; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0xc40, BIT(9), reg_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value)); - - } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - if (p_dm_odm->support_ic_type & (ODM_RTL8822B|ODM_RTL8821C)) { - odm_set_bb_reg(p_dm_odm, 0xc20, BIT(28), reg_value); - if (p_dm_odm->rf_type > ODM_1T1R) - odm_set_bb_reg(p_dm_odm, 0xe20, BIT(28), reg_value); - } else - odm_set_bb_reg(p_dm_odm, 0x87c, BIT(13), reg_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value)); - } -} - -u8 -phydm_calculate_fc( - void *p_dm_void, - u32 channel, - u32 bw, - u32 second_ch, - u32 *fc_in -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 fc = *fc_in; - u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173}; - u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, 149, 165}; - u32 *p_start_ch = &(start_ch_per_40m[0]); - u32 num_start_channel = NUM_START_CH_40M; - u32 channel_offset = 0; - u32 i; - - /*2.4G*/ - if (channel <= 14 && channel > 0) { - - if (bw == 80) - return SET_ERROR; - - fc = 2412 + (channel - 1) * 5; - - if (bw == 40 && (second_ch == PHYDM_ABOVE)) { - - if (channel >= 10) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch)); - return SET_ERROR; - } - fc += 10; - } else if (bw == 40 && (second_ch == PHYDM_BELOW)) { - - if (channel <= 2) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch)); - return SET_ERROR; - } - fc -= 10; - } - } - /*5G*/ - else if (channel >= 36 && channel <= 177) { - - if (bw != 20) { - - if (bw == 40) { - num_start_channel = NUM_START_CH_40M; - p_start_ch = &(start_ch_per_40m[0]); - channel_offset = CH_OFFSET_40M; - } else if (bw == 80) { - num_start_channel = NUM_START_CH_80M; - p_start_ch = &(start_ch_per_80m[0]); - channel_offset = CH_OFFSET_80M; - } - - for (i = 0; i < num_start_channel; i++) { - - if (channel < p_start_ch[i + 1]) { - channel = p_start_ch[i] + channel_offset; - break; - } - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Mod_CH = ((%d))\n", channel)); - } - - fc = 5180 + (channel - 36) * 5; - - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)) Error setting\n", channel)); - return SET_ERROR; - } - - *fc_in = fc; - - return SET_SUCCESS; -} - - -u8 -phydm_calculate_intf_distance( - void *p_dm_void, - u32 bw, - u32 fc, - u32 f_interference, - u32 *p_tone_idx_tmp_in -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 bw_up, bw_low; - u32 int_distance; - u32 tone_idx_tmp; - u8 set_result = SET_NO_NEED; - - bw_up = fc + bw / 2; - bw_low = fc - bw / 2; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, fc, bw_up, f_interference)); - - if ((f_interference >= bw_low) && (f_interference <= bw_up)) { - - int_distance = (fc >= f_interference) ? (fc - f_interference) : (f_interference - fc); - tone_idx_tmp = (int_distance << 5); /* =10*(int_distance /0.3125) */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", int_distance, (tone_idx_tmp / 10), (tone_idx_tmp % 10))); - *p_tone_idx_tmp_in = tone_idx_tmp; - set_result = SET_SUCCESS; - } - - return set_result; - -} - - -u8 -phydm_csi_mask_setting( - void *p_dm_void, - u32 enable, - u32 channel, - u32 bw, - u32 f_interference, - u32 second_ch -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 fc; - u8 tone_direction; - u32 tone_idx_tmp; - u8 set_result = SET_SUCCESS; - - if (enable == CSI_MASK_DISABLE) { - set_result = SET_SUCCESS; - phydm_clean_all_csi_mask(p_dm_odm); - - } else { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, (((bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L"))); - - /*calculate fc*/ - if (phydm_calculate_fc(p_dm_odm, channel, bw, second_ch, &fc) == SET_ERROR) - set_result = SET_ERROR; - - else { - /*calculate interference distance*/ - if (phydm_calculate_intf_distance(p_dm_odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { - - tone_direction = (f_interference >= fc) ? FREQ_POSITIVE : FREQ_NEGATIVE; - phydm_set_csi_mask_reg(p_dm_odm, tone_idx_tmp, tone_direction); - set_result = SET_SUCCESS; - } else - set_result = SET_NO_NEED; - } - } - - if (set_result == SET_SUCCESS) - phydm_csi_mask_enable(p_dm_odm, enable); - else - phydm_csi_mask_enable(p_dm_odm, CSI_MASK_DISABLE); - - return set_result; -} - -u8 -phydm_nbi_setting( - void *p_dm_void, - u32 enable, - u32 channel, - u32 bw, - u32 f_interference, - u32 second_ch -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 fc; - u32 tone_idx_tmp; - u8 set_result = SET_SUCCESS; - - if (enable == NBI_DISABLE) - set_result = SET_SUCCESS; - - else { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L"))); - - /*calculate fc*/ - if (phydm_calculate_fc(p_dm_odm, channel, bw, second_ch, &fc) == SET_ERROR) - set_result = SET_ERROR; - - else { - /*calculate interference distance*/ - if (phydm_calculate_intf_distance(p_dm_odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { - - phydm_set_nbi_reg(p_dm_odm, tone_idx_tmp, bw); - set_result = SET_SUCCESS; - } else - set_result = SET_NO_NEED; - } - } - - if (set_result == SET_SUCCESS) - phydm_nbi_enable(p_dm_odm, enable); - else - phydm_nbi_enable(p_dm_odm, NBI_DISABLE); - - return set_result; -} - -void -phydm_api_debug( - void *p_dm_void, - u32 function_map, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 used = *_used; - u32 out_len = *_out_len; - u32 channel = dm_value[1]; - u32 bw = dm_value[2]; - u32 f_interference = dm_value[3]; - u32 second_ch = dm_value[4]; - u8 set_result = 0; - - /*PHYDM_API_NBI*/ - /*-------------------------------------------------------------------------------------------------------------------------------*/ - if (function_map == PHYDM_API_NBI) { - - if (dm_value[0] == 100) { - - PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); - return; - - } else if (dm_value[0] == NBI_ENABLE) { - - PHYDM_SNPRINTF((output + used, out_len - used, "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, ((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : ((second_ch == PHYDM_ABOVE) ? "H" : "L"))); - set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, bw, f_interference, second_ch); - - } else if (dm_value[0] == NBI_DISABLE) { - - PHYDM_SNPRINTF((output + used, out_len - used, "[Disable NBI]\n")); - set_result = phydm_nbi_setting(p_dm_odm, NBI_DISABLE, channel, bw, f_interference, second_ch); - - } else - - set_result = SET_ERROR; - PHYDM_SNPRINTF((output + used, out_len - used, "[NBI set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); - - } - - /*PHYDM_CSI_MASK*/ - /*-------------------------------------------------------------------------------------------------------------------------------*/ - else if (function_map == PHYDM_API_CSI_MASK) { - - if (dm_value[0] == 100) { - - PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); - return; - - } else if (dm_value[0] == CSI_MASK_ENABLE) { - - PHYDM_SNPRINTF((output + used, out_len - used, "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, (channel > 14) ? "Don't care" : (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "H" : "L"))); - set_result = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, channel, bw, f_interference, second_ch); - - } else if (dm_value[0] == CSI_MASK_DISABLE) { - - PHYDM_SNPRINTF((output + used, out_len - used, "[Disable CSI MASK]\n")); - set_result = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_DISABLE, channel, bw, f_interference, second_ch); - - } else - - set_result = SET_ERROR; - PHYDM_SNPRINTF((output + used, out_len - used, "[CSI MASK set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); - } -} - -void -phydm_stop_ck320( - void *p_dm_void, - u8 enable -) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 reg_value = (enable == true) ? 1 : 0; - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, 0x8b4, BIT(6), reg_value); - /**/ - } else { - - if (p_dm_odm->support_ic_type & ODM_IC_N_2SS) { /*N-2SS*/ - odm_set_bb_reg(p_dm_odm, 0x87c, BIT(29), reg_value); - /**/ - } else { /*N-1SS*/ - odm_set_bb_reg(p_dm_odm, 0x87c, BIT(31), reg_value); - /**/ - } - } -} - /*<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/ void phydm_dc_cancellation( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { -#if PHYDM_DC_CANCELLATION - u32 offset_i_hex[ODM_RF_PATH_MAX] = {0}; - u32 offset_q_hex[ODM_RF_PATH_MAX] = {0}; - u32 reg_value32[ODM_RF_PATH_MAX] = {0}; - u8 det_num = 0; +#ifdef PHYDM_DC_CANCELLATION + u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0}; + u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0}; + u32 reg_value32[PHYDM_MAX_RF_PATH] = {0}; + u8 path = RF_PATH_A; - if (!(p_dm_odm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT)) + if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT)) return; - + + if ((dm->support_ic_type & ODM_RTL8188F) && (dm->cut_version < ODM_CUT_D)) + return; + /*DC_Estimation (only for 2x2 ic now) */ -for (det_num = 0; det_num < ODM_RF_PATH_MAX; det_num++) { - if (p_dm_odm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) { - if (!phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_2, 0x235)) {/*set debug port to 0x235*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[DC Cancellation] Set Debug port Fail")); - return; - } - } else if (p_dm_odm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) { - /* Path-a */ - if (det_num == 0) { - if (!phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_2, 0x200)) {/*set debug port to 0x200*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[DC Cancellation] Set Debug port Fail")); + for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) { + if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) { + if (!phydm_set_bb_dbg_port(dm, + BB_DBGPORT_PRIORITY_2, 0x235)) {/*set debug port to 0x235*/ + PHYDM_DBG(dm, ODM_COMP_API, + "[DC Cancellation] Set Debug port Fail"); return; } - phydm_bb_dbg_port_header_sel(p_dm_odm, 0x0); - /* Path-b */ - } else if (det_num == 1) { - - if (!(p_dm_odm->support_ic_type & ODM_RTL8822B)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[DC Cancellation] Only one-path now")); - break; - } - - if (!phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_2, 0x202)) {/*set debug port to 0x200*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[DC Cancellation] Set Debug port Fail")); + } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) { + if (!phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_2, 0x200)) { + /*set debug port to 0x200*/ + PHYDM_DBG(dm, ODM_COMP_API, + "[DC Cancellation] Set Debug port Fail"); + return; + } + phydm_bb_dbg_port_header_sel(dm, 0x0); + if (dm->rf_type > RF_1T1R) { + if (!phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_2, 0x202)) { + /*set debug port to 0x200*/ + PHYDM_DBG(dm, ODM_COMP_API, + "[DC Cancellation] Set Debug port Fail"); return; } - phydm_bb_dbg_port_header_sel(p_dm_odm, 0x0); - } - } - - //odm_set_bb_reg(p_dm_odm, 0x908, bMaskDWord, 0x235); - //odm_set_bb_reg(p_dm_odm, 0xa78, BIT(3), 0x1); - odm_write_dig(p_dm_odm, 0x7E); - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - odm_set_bb_reg(p_dm_odm, 0x88c, BIT(21)|BIT(20), 0x3); - } else { - odm_set_bb_reg(p_dm_odm, 0xc00, BIT(1)|BIT(0), 0x0); - odm_set_bb_reg(p_dm_odm, 0xe00, BIT(1)|BIT(0), 0x0); - } - odm_set_bb_reg(p_dm_odm, 0xa78, MASKBYTE1, 0x0); /*disable CCK DCNF*/ + phydm_bb_dbg_port_header_sel(dm, 0x0); + } + } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, (" DC cancellation Begin!!!")); + odm_write_dig(dm, 0x7E); -#if 0 - - odm_set_bb_reg(p_dm_odm, 0x87c, BIT(31), 0x1); /*stop ck320*/ - offset_i_hex = odm_get_bb_reg(p_dm_odm, 0xDF4, 0xffc0000); - offset_q_hex = odm_get_bb_reg(p_dm_odm, 0xDF4, 0x3ff00); - odm_set_bb_reg(p_dm_odm, 0x87c, BIT(31), 0x0); /*start ck320*/ + if (dm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(dm, 0x88c, BIT(21)|BIT(20), 0x3); + else { + odm_set_bb_reg(dm, 0xc00, BIT(1)|BIT(0), 0x0); + if (dm->rf_type > RF_1T1R) + odm_set_bb_reg(dm, 0xe00, BIT(1)|BIT(0), 0x0); + } + odm_set_bb_reg(dm, 0xa78, MASKBYTE1, 0x0); /*disable CCK DCNF*/ -#else + PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!"); - phydm_stop_ck320(p_dm_odm, true); /*stop ck320*/ + phydm_stop_ck320(dm, true); /*stop ck320*/ /* the same debug port both for path-a and path-b*/ - if (det_num == 0) - reg_value32[det_num] = phydm_get_bb_dbg_port_value(p_dm_odm); - else if (det_num == 1) - reg_value32[det_num] = phydm_get_bb_dbg_port_value(p_dm_odm); - - phydm_stop_ck320(p_dm_odm, false); /*start ck320*/ + reg_value32[path] = phydm_get_bb_dbg_port_value(dm); -#endif + phydm_stop_ck320(dm, false); /*start ck320*/ - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - odm_set_bb_reg(p_dm_odm, 0x88c, BIT(21)|BIT(20), 0x0); + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, 0x88c, BIT(21)|BIT(20), 0x0); } else { - odm_set_bb_reg(p_dm_odm, 0xc00, BIT(1)|BIT(0), 0x3); - odm_set_bb_reg(p_dm_odm, 0xe00, BIT(1)|BIT(0), 0x3); + odm_set_bb_reg(dm, 0xc00, BIT(1)|BIT(0), 0x3); + odm_set_bb_reg(dm, 0xe00, BIT(1)|BIT(0), 0x3); } - odm_write_dig(p_dm_odm, 0x20); - phydm_release_bb_dbg_port(p_dm_odm); + odm_write_dig(dm, 0x20); + phydm_release_bb_dbg_port(dm); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, (" DC cancellation OK!!!")); -} + PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!"); + } /*DC_Cancellation*/ - odm_set_bb_reg(p_dm_odm, 0xa9c, BIT(20), 0x1); /*DC compensation to CCK data path*/ - if (p_dm_odm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) { + odm_set_bb_reg(dm, 0xa9c, BIT(20), 0x1); /*DC compensation to CCK data path*/ + if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) { offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18; offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8; @@ -4067,9 +3002,9 @@ for (det_num = 0; det_num < ODM_RF_PATH_MAX; det_num++) { offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ? (0x400 - offset_i_hex[1]) : (0x1ff - offset_i_hex[1]); offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ? (0x400 - offset_q_hex[1]) : (0x1ff - offset_q_hex[1]); - odm_set_bb_reg(p_dm_odm, 0x950, 0x1ff, offset_i_hex[1]); - odm_set_bb_reg(p_dm_odm, 0x950, 0x1ff0000, offset_q_hex[1]); - } else if (p_dm_odm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) { + odm_set_bb_reg(dm, 0x950, 0x1ff, offset_i_hex[1]); + odm_set_bb_reg(dm, 0x950, 0x1ff0000, offset_q_hex[1]); + } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) { /* Path-a */ offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10; @@ -4079,13 +3014,13 @@ for (det_num = 0; det_num < ODM_RF_PATH_MAX; det_num++) { offset_i_hex[0] = 0x400 - offset_i_hex[0]; offset_q_hex[0] = 0x400 - offset_q_hex[0]; - odm_set_bb_reg(p_dm_odm, 0xc10, 0x3c000000, ((0x3c0 & offset_i_hex[0]) >> 6)); - odm_set_bb_reg(p_dm_odm, 0xc10, 0xfc00, (0x3f & offset_i_hex[0])); - odm_set_bb_reg(p_dm_odm, 0xc14, 0x3c000000, ((0x3c0 & offset_q_hex[0]) >> 6)); - odm_set_bb_reg(p_dm_odm, 0xc14, 0xfc00, (0x3f & offset_q_hex[0])); + odm_set_bb_reg(dm, 0xc10, 0x3c000000, ((0x3c0 & offset_i_hex[0]) >> 6)); + odm_set_bb_reg(dm, 0xc10, 0xfc00, (0x3f & offset_i_hex[0])); + odm_set_bb_reg(dm, 0xc14, 0x3c000000, ((0x3c0 & offset_q_hex[0]) >> 6)); + odm_set_bb_reg(dm, 0xc14, 0xfc00, (0x3f & offset_q_hex[0])); /* Path-b */ - if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + if (dm->rf_type > RF_1T1R) { offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10; offset_q_hex[1] = reg_value32[1] & 0x3ff; @@ -4094,10 +3029,10 @@ for (det_num = 0; det_num < ODM_RF_PATH_MAX; det_num++) { offset_i_hex[1] = 0x400 - offset_i_hex[1]; offset_q_hex[1] = 0x400 - offset_q_hex[1]; - odm_set_bb_reg(p_dm_odm, 0xe10, 0x3c000000, ((0x3c0 & offset_i_hex[1]) >> 6)); - odm_set_bb_reg(p_dm_odm, 0xe10, 0xfc00, (0x3f & offset_i_hex[1])); - odm_set_bb_reg(p_dm_odm, 0xe14, 0x3c000000, ((0x3c0 & offset_q_hex[1]) >> 6)); - odm_set_bb_reg(p_dm_odm, 0xe14, 0xfc00, (0x3f & offset_q_hex[1])); + odm_set_bb_reg(dm, 0xe10, 0x3c000000, ((0x3c0 & offset_i_hex[1]) >> 6)); + odm_set_bb_reg(dm, 0xe10, 0xfc00, (0x3f & offset_i_hex[1])); + odm_set_bb_reg(dm, 0xe14, 0x3c000000, ((0x3c0 & offset_q_hex[1]) >> 6)); + odm_set_bb_reg(dm, 0xe14, 0xfc00, (0x3f & offset_q_hex[1])); } } #endif @@ -4105,39 +3040,53 @@ for (det_num = 0; det_num < ODM_RF_PATH_MAX; det_num++) { void phydm_receiver_blocking( - void *p_dm_void + void *dm_void ) { #ifdef CONFIG_RECEIVER_BLOCKING - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 channel = *p_dm_odm->p_channel; - u8 bw = *p_dm_odm->p_band_width; - u8 set_result = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 channel = *dm->channel; + u8 bw = *dm->band_width; + u32 bb_regf0 = odm_get_bb_reg(dm, 0xf0, MASKDWORD); - if (!(p_dm_odm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT)) + if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT)) return; - - if (p_dm_odm->consecutive_idlel_time > 10 && *p_dm_odm->p_mp_mode == false && p_dm_odm->adaptivity_enable == true) { - if ((bw == ODM_BW20M) && (channel == 1) && !p_dm_odm->is_nbi_enable) { - set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 2410, PHYDM_DONT_CARE); - p_dm_odm->is_nbi_enable = true; - } else if ((bw == ODM_BW20M) && (channel == 13) && !p_dm_odm->is_nbi_enable) { - set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 2473, PHYDM_DONT_CARE); - p_dm_odm->is_nbi_enable = true; - } else { - if (p_dm_odm->is_nbi_enable && channel != 1 && channel != 13) { - phydm_nbi_enable(p_dm_odm, NBI_DISABLE); - p_dm_odm->is_nbi_enable = false; + + if ((dm->support_ic_type & ODM_RTL8188E && ((bb_regf0 & 0xf000) >> 12) < 8) || + dm->support_ic_type & ODM_RTL8192E) { /*8188E_T version*/ + if (dm->consecutive_idlel_time > 10 && *dm->mp_mode == false && dm->adaptivity_enable == true) { + if ((bw == CHANNEL_WIDTH_20) && (channel == 1)) { + phydm_nbi_setting(dm, FUNC_ENABLE, channel, 20, 2410, PHYDM_DONT_CARE); + dm->is_receiver_blocking_en = true; + } else if ((bw == CHANNEL_WIDTH_20) && (channel == 13)) { + phydm_nbi_setting(dm, FUNC_ENABLE, channel, 20, 2473, PHYDM_DONT_CARE); + dm->is_receiver_blocking_en = true; + } else if (dm->is_receiver_blocking_en && channel != 1 && channel != 13) { + phydm_nbi_enable(dm, FUNC_DISABLE); + odm_set_bb_reg(dm, 0xc40, 0x1f000000, 0x1f); + dm->is_receiver_blocking_en = false; } + return; } - } else { - if (p_dm_odm->is_nbi_enable) { - phydm_nbi_enable(p_dm_odm, NBI_DISABLE); - p_dm_odm->is_nbi_enable = false; + } else if ((dm->support_ic_type & ODM_RTL8188E && ((bb_regf0 & 0xf000) >> 12) >= 8)) { /*8188E_S version*/ + if (dm->consecutive_idlel_time > 10 && *dm->mp_mode == false && dm->adaptivity_enable == true) { + if ((bw == CHANNEL_WIDTH_20) && (channel == 13)) { + phydm_nbi_setting(dm, FUNC_ENABLE, channel, 20, 2473, PHYDM_DONT_CARE); + dm->is_receiver_blocking_en = true; + } else if (dm->is_receiver_blocking_en && channel != 13) { + phydm_nbi_enable(dm, FUNC_DISABLE); + odm_set_bb_reg(dm, 0xc40, 0x1f000000, 0x1f); + dm->is_receiver_blocking_en = false; + } + return; } } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, - ("[NBI set result: %s]\n", (set_result == SET_SUCCESS ? "Success" : (set_result == SET_NO_NEED ? "No need" : "Error")))); + + if (dm->is_receiver_blocking_en) { + phydm_nbi_enable(dm, FUNC_DISABLE); + odm_set_bb_reg(dm, 0xc40, 0x1f000000, 0x1f); + dm->is_receiver_blocking_en = false; + } + #endif } - diff --git a/hal/phydm/phydm.h b/hal/phydm/phydm.h index 25aff31..602b663 100644 --- a/hal/phydm/phydm.h +++ b/hal/phydm/phydm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ @@ -20,44 +30,49 @@ /*============================================================*/ /*include files*/ /*============================================================*/ +/*PHYDM header*/ #include "phydm_pre_define.h" #include "phydm_dig.h" #include "phydm_pathdiv.h" #include "phydm_antdiv.h" +#include "phydm_soml.h" +#include "phydm_smt_ant.h" #include "phydm_antdect.h" -#include "phydm_dynamicbbpowersaving.h" #include "phydm_rainfo.h" #include "phydm_dynamictxpower.h" #include "phydm_cfotracking.h" -#include "phydm_acs.h" #include "phydm_adaptivity.h" #include "phydm_dfs.h" #include "phydm_ccx.h" #include "txbf/phydm_hal_txbf_api.h" - #include "phydm_adc_sampling.h" #include "phydm_dynamic_rx_path.h" #include "phydm_psd.h" -#include "halrf/halrf_iqk.h" -#include "halrf/halrf.h" - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) +#include "phydm_primary_cca.h" +#include "phydm_cck_pd.h" +#include "phydm_rssi_monitor.h" +#include "phydm_auto_dbg.h" +#include "phydm_math_lib.h" +#include "phydm_noisemonitor.h" +#include "phydm_api.h" +#include "phydm_pow_train.h" +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) #include "phydm_beamforming.h" #endif +/* reg naming transfer */ +#include "phydm_regtable.h" + +/*HALRF header*/ +#include "halrf/halrf_iqk.h" +#include "halrf/halrf.h" +#include "halrf/halrf_powertracking.h" #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) #include "halrf/halphyrf_ap.h" -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - #include "phydm_noisemonitor.h" +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) #include "halrf/halphyrf_ce.h" -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) #include "halrf/halphyrf_win.h" - #include "phydm_noisemonitor.h" #endif extern const u16 phy_rate_table[28]; @@ -74,195 +89,139 @@ extern const u16 phy_rate_table[28]; #define NONE 0 -/*NBI API------------------------------------*/ -#define NBI_ENABLE 1 -#define NBI_DISABLE 2 - -#define NBI_TABLE_SIZE_128 27 -#define NBI_TABLE_SIZE_256 59 - -#define NUM_START_CH_80M 7 -#define NUM_START_CH_40M 14 +#define MAX_2(_x_, _y_) (((_x_)>(_y_))? (_x_) : (_y_)) +#define MIN_2(_x_, _y_) (((_x_)<(_y_))? (_x_) : (_y_)) +#define DIFF_2(_x_,_y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_)) -#define CH_OFFSET_40M 2 -#define CH_OFFSET_80M 6 +#define BYTE_2_DWORD(B3, B2, B1, B0) ((B3 << 24) | (B2 << 16) | (B1 << 8) | B0) +#define BIT_2_BYTE(B3, B2, B1, B0) ((B3 << 3) | (B2 << 2) | (B1 << 1) | B0) -/*CSI MASK API------------------------------------*/ -#define CSI_MASK_ENABLE 1 -#define CSI_MASK_DISABLE 2 - -/*------------------------------------------------*/ - -#define FFT_128_TYPE 1 -#define FFT_256_TYPE 2 - -#define SET_SUCCESS 1 -#define SET_ERROR 2 -#define SET_NO_NEED 3 - -#define FREQ_POSITIVE 1 -#define FREQ_NEGATIVE 2 +/*For cmn sta info*/ +#define is_sta_active(sta) ((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE)) +#define IS_FUNC_EN(name) ((name) && (*name)) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - #define PHYDM_WATCH_DOG_PERIOD 1 + #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/ #else - #define PHYDM_WATCH_DOG_PERIOD 2 + #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/ #endif /*============================================================*/ /*structure and define*/ /*============================================================*/ -struct _dynamic_primary_cca { - u8 pri_cca_flag; - u8 intf_flag; - u8 intf_type; - u8 dup_rts_flag; - u8 monitor_flag; - u8 ch_offset; - u8 mf_state; -}; - #define dm_type_by_fw 0 #define dm_type_by_driver 1 -/*Declare for common info*/ - -#define IQK_THRESHOLD 8 -#define DPK_THRESHOLD 4 - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -__PACK struct _odm_phy_status_info_ { - u8 rx_pwdb_all; - u8 signal_quality; /* in 0-100 index. */ - u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ - u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */ - s8 rx_mimo_signal_quality[4]; /* EVM */ - s8 rx_snr[4]; /* per-path's SNR */ -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u8 rx_count:2; /* RX path counter---*/ - u8 band_width:2; - u8 rxsc:4; /* sub-channel---*/ -#else - u8 band_width; -#endif -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u8 channel; /* channel number---*/ - boolean is_mu_packet; /* is MU packet or not---*/ - boolean is_beamformed; /* BF packet---*/ -#endif -}; - -struct _odm_phy_status_info_append_ { - u8 MAC_CRC32; - -}; - -#else - -struct _odm_phy_status_info_ { - /* */ - /* Be care, if you want to add any element please both add at outer_driver & phydm */ - - /* WIN in _RT_RFD_STATUS*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - u32 rx_pwdb_all; /*in new Phy-status IC, represent the max PWDB among all path*/ -#else - u8 rx_pwdb_all; -#endif - u8 signal_quality; /* in 0-100 index. */ - s8 rx_mimo_signal_quality[4]; /* per-path's EVM translate to 0~100% */ - u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */ - u8 rx_mimo_signal_strength[4]; /* RSSI in 0~100 index */ - s16 cfo_short[4]; /* per-path's cfo_short */ - s16 cfo_tail[4]; /* per-path's cfo_tail */ - s8 rx_power; /* in dBm Translate from PWdB */ - s8 recv_signal_power; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ - u8 bt_rx_rssi_percentage; - u8 signal_strength; /* in 0-100 index. */ - s8 rx_pwr[4]; /* per-path's pwdb */ - s8 rx_snr[4]; /* per-path's SNR */ - /* s8 BB_Backup[13]; backup reg. */ -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u8 rx_count:2; /* RX path counter---*/ - u8 band_width:2; - u8 rxsc:4; /* sub-channel---*/ -#else - u8 band_width; -#endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - u8 bt_coex_pwr_adjust; -#endif -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u8 channel; /* channel number---*/ - boolean is_mu_packet; /* is MU packet or not---*/ - boolean is_beamformed; /* BF packet---*/ -#endif +struct phydm_phystatus_statistic { + + /*[CCK]*/ + u32 rssi_cck_sum; + u32 rssi_cck_cnt; + /*[OFDM]*/ + u32 rssi_ofdm_sum; + u32 rssi_ofdm_cnt; + u32 evm_ofdm_sum; + u32 snr_ofdm_sum; + /*[1SS]*/ + u32 rssi_1ss_cnt; + u32 rssi_1ss_sum; + u32 evm_1ss_sum; + u32 snr_1ss_sum; + /*[2SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + u32 rssi_2ss_cnt; + u32 rssi_2ss_sum[2]; + u32 evm_2ss_sum[2]; + u32 snr_2ss_sum[2]; + #endif + /*[3SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + u32 rssi_3ss_cnt; + u32 rssi_3ss_sum[3]; + u32 evm_3ss_sum[3]; + u32 snr_3ss_sum[3]; + #endif + /*[4SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + u32 rssi_4ss_cnt; + u32 rssi_4ss_sum[4]; + u32 evm_4ss_sum[4]; + u32 snr_4ss_sum[4]; + #endif }; -#endif -struct _odm_per_pkt_info_ { - u8 data_rate; - u8 station_id; - boolean is_packet_match_bssid; - boolean is_packet_to_self; - boolean is_packet_beacon; - boolean is_to_self; - u8 ppdu_cnt; +struct phydm_phystatus_avg { + + /*[CCK]*/ + u8 rssi_cck_avg; + /*[OFDM]*/ + u8 rssi_ofdm_avg; + u8 evm_ofdm_avg; + u8 snr_ofdm_avg; + /*[1SS]*/ + u8 rssi_1ss_avg; + u8 evm_1ss_avg; + u8 snr_1ss_avg; + /*[2SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + u8 rssi_2ss_avg[2]; + u8 evm_2ss_avg[2]; + u8 snr_2ss_avg[2]; + #endif + /*[3SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + u8 rssi_3ss_avg[3]; + u8 evm_3ss_avg[3]; + u8 snr_3ss_avg[3]; + #endif + /*[4SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + u8 rssi_4ss_avg[4]; + u8 evm_4ss_avg[4]; + u8 snr_4ss_avg[4]; + #endif }; - -struct _odm_phy_dbg_info_ { +struct odm_phy_dbg_info { /*ODM Write,debug info*/ - s8 rx_snr_db[4]; - u32 num_qry_phy_status; + u32 num_qry_phy_status_cck; u32 num_qry_phy_status_ofdm; #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) u32 num_qry_mu_pkt; u32 num_qry_bf_pkt; - u32 num_qry_mu_vht_pkt[40]; + u32 num_qry_mu_vht_pkt[VHT_RATE_NUM]; boolean is_ldpc_pkt; boolean is_stbc_pkt; u8 num_of_ppdu[4]; u8 gid_num[4]; #endif u8 num_qry_beacon_pkt; + u8 show_phy_sts_all_pkt; /*Show phy status witch not match BSSID*/ + u16 show_phy_sts_max_cnt; /*show number of phy-status row data per PHYDM watchdog*/ + u16 show_phy_sts_cnt; /* Others */ - s32 rx_evm[4]; - - u16 num_qry_legacy_pkt[12]; - u16 num_qry_ht_pkt[32]; - u8 ht_pkt_not_zero; + /*s32 rx_evm[4];*/ + /*s8 rx_snr_db[4];*/ + + u16 num_qry_legacy_pkt[LEGACY_RATE_NUM]; + u16 num_qry_ht_pkt[HT_RATE_NUM]; + u16 num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*for 20M SC*/ + boolean ht_pkt_not_zero; + boolean low_bw_20_occur; #if ODM_IC_11AC_SERIES_SUPPORT - u16 num_qry_vht_pkt[40]; - u8 vht_pkt_not_zero; + u16 num_qry_vht_pkt[VHT_RATE_NUM]; + u16 num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*for 40M SC*/ + boolean vht_pkt_not_zero; + boolean low_bw_40_occur; #endif - - u8 rssi_cck_avg; - u32 rssi_cck_sum; - u32 rssi_cck_cnt; - u8 rssi_ofdm_avg; - u32 rssi_ofdm_sum; - u32 rssi_ofdm_cnt; - u8 rssi_1ss_avg; - u32 rssi_1ss_sum; - u32 rssi_1ss_cnt; - u8 rssi_2ss_avg[2]; - u32 rssi_2ss_sum[2]; - u32 rssi_2ss_cnt; - u8 rssi_3ss_avg[3]; - u32 rssi_3ss_sum[3]; - u32 rssi_3ss_cnt; - u8 rssi_4ss_avg[4]; - u32 rssi_4ss_sum[4]; - u32 rssi_4ss_cnt; - + struct phydm_phystatus_statistic phystatus_statistic_info; + struct phydm_phystatus_avg phystatus_statistic_avg; }; -enum odm_cmninfo_e { +enum odm_cmninfo { /*Fixed value*/ /*-----------HOOK BEFORE REG INIT-----------*/ ODM_CMNINFO_PLATFORM = 0, @@ -294,7 +253,6 @@ enum odm_cmninfo_e { ODM_CMNINFO_CONFIG_BB_RF, ODM_CMNINFO_DOMAIN_CODE_2G, ODM_CMNINFO_DOMAIN_CODE_5G, - ODM_CMNINFO_IQKFWOFFLOAD, ODM_CMNINFO_IQKPAOFF, ODM_CMNINFO_HUBUSBMODE, ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, @@ -307,17 +265,15 @@ enum odm_cmninfo_e { ODM_CMNINFO_EFUSE0X3D8, ODM_CMNINFO_EFUSE0X3D7, ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING, + ODM_CMNINFO_ADVANCE_OTA, ODM_CMNINFO_HP_HWID, - ODM_CMNINFO_ADVANCE_OTA, /*-----------HOOK BEFORE REG INIT-----------*/ /*Dynamic value:*/ /*--------- POINTER REFERENCE-----------*/ - ODM_CMNINFO_MAC_PHY_MODE, ODM_CMNINFO_TX_UNI, ODM_CMNINFO_RX_UNI, - ODM_CMNINFO_WM_MODE, ODM_CMNINFO_BAND, ODM_CMNINFO_SEC_CHNL_OFFSET, ODM_CMNINFO_SEC_MODE, @@ -325,10 +281,8 @@ enum odm_cmninfo_e { ODM_CMNINFO_CHNL, ODM_CMNINFO_FORCED_RATE, ODM_CMNINFO_ANT_DIV, + ODM_CMNINFO_ADAPTIVE_SOML, ODM_CMNINFO_ADAPTIVITY, - ODM_CMNINFO_DMSP_GET_VALUE, - ODM_CMNINFO_BUDDY_ADAPTOR, - ODM_CMNINFO_DMSP_IS_MASTER, ODM_CMNINFO_SCAN, ODM_CMNINFO_POWER_SAVING, ODM_CMNINFO_ONE_PATH_CCA, @@ -337,7 +291,6 @@ enum odm_cmninfo_e { ODM_CMNINFO_INIT_ON, ODM_CMNINFO_ANT_TEST, ODM_CMNINFO_NET_CLOSED, - ODM_CMNINFO_FORCED_IGI_LB, ODM_CMNINFO_P2P_LINK, ODM_CMNINFO_FCS_MODE, ODM_CMNINFO_IS1ANTENNA, @@ -347,6 +300,9 @@ enum odm_cmninfo_e { ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA, ODM_CMNINFO_SOFT_AP_MODE, ODM_CMNINFO_MP_MODE, + ODM_CMNINFO_INTERRUPT_MASK, + ODM_CMNINFO_BB_OPERATION_MODE, + ODM_CMNINFO_BF_ANTDIV_DECISION, /*--------- POINTER REFERENCE-----------*/ /*------------CALL BY VALUE-------------*/ @@ -355,14 +311,13 @@ enum odm_cmninfo_e { ODM_CMNINFO_LINK_IN_PROGRESS, ODM_CMNINFO_LINK, ODM_CMNINFO_CMW500LINK, - ODM_CMNINFO_LPSPG, ODM_CMNINFO_STATION_STATE, ODM_CMNINFO_RSSI_MIN, ODM_CMNINFO_RSSI_MIN_BY_PATH, ODM_CMNINFO_DBG_COMP, ODM_CMNINFO_DBG_LEVEL, - ODM_CMNINFO_RA_THRESHOLD_HIGH, - ODM_CMNINFO_RA_THRESHOLD_LOW, + ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/ + ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/ ODM_CMNINFO_RF_ANTENNA_TYPE, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, ODM_CMNINFO_BE_FIX_TX_ANT, @@ -371,12 +326,10 @@ enum odm_cmninfo_e { ODM_CMNINFO_BT_HS_RSSI, ODM_CMNINFO_BT_OPERATION, ODM_CMNINFO_BT_LIMITED_DIG, - ODM_CMNINFO_BT_DIG, - ODM_CMNINFO_BT_BUSY, - ODM_CMNINFO_BT_DISABLE_EDCA, ODM_CMNINFO_AP_TOTAL_NUM, ODM_CMNINFO_POWER_TRAINING, ODM_CMNINFO_DFS_REGION_DOMAIN, + ODM_CMNINFO_BT_CONTINUOUS_TURN, /*------------CALL BY VALUE-------------*/ /*Dynamic ptr array hook itms.*/ @@ -385,8 +338,26 @@ enum odm_cmninfo_e { }; +enum phydm_rfe_bb_source_sel { + PAPE_2G = 0, + PAPE_5G = 1, + LNA0N_2G = 2, + LNAON_5G = 3, + TRSW = 4, + TRSW_B = 5, + GNT_BT = 6, + ZERO = 7, + ANTSEL_0 = 8, + ANTSEL_1 = 9, + ANTSEL_2 = 0xa, + ANTSEL_3 = 0xb, + ANTSEL_4 = 0xc, + ANTSEL_5 = 0xd, + ANTSEL_6 = 0xe, + ANTSEL_7 = 0xf +}; -enum phydm_info_query_e { +enum phydm_info_query { PHYDM_INFO_FA_OFDM, PHYDM_INFO_FA_CCK, PHYDM_INFO_FA_TOTAL, @@ -406,53 +377,118 @@ enum phydm_info_query_e { PHYDM_INFO_CCK_ENABLE, PHYDM_INFO_CRC32_OK_HT_AGG, PHYDM_INFO_CRC32_ERROR_HT_AGG, - PHYDM_INFO_DBG_PORT_0 + PHYDM_INFO_DBG_PORT_0, + PHYDM_INFO_CURR_IGI, + PHYDM_INFO_RSSI_MIN, + PHYDM_INFO_RSSI_MAX, + PHYDM_INFO_CLM_RATIO, + PHYDM_INFO_NHM_RATIO, }; -enum phydm_api_e { - +enum phydm_api { PHYDM_API_NBI = 1, PHYDM_API_CSI_MASK, }; -enum odm_ability_e { - - ODM_BB_DIG = BIT(0), - ODM_BB_RA_MASK = BIT(1), - ODM_BB_DYNAMIC_TXPWR = BIT(2), - ODM_BB_FA_CNT = BIT(3), - ODM_BB_RSSI_MONITOR = BIT(4), - ODM_BB_CCK_PD = BIT(5), - ODM_BB_ANT_DIV = BIT(6), - /*BIT(7),*/ - ODM_BB_PWR_TRAIN = BIT(8), - ODM_BB_RATE_ADAPTIVE = BIT(9), - ODM_BB_PATH_DIV = BIT(10), - /*BIT(11),*/ - /*BIT(12),*/ - ODM_BB_ADAPTIVITY = BIT(13), - ODM_BB_CFO_TRACKING = BIT(14), - ODM_BB_NHM_CNT = BIT(15), - ODM_BB_PRIMARY_CCA = BIT(16), - ODM_BB_TXBF = BIT(17), - ODM_BB_DYNAMIC_ARFR = BIT(18), - ODM_BB_DYNAMIC_PSDTOOL = BIT(19), - ODM_MAC_EDCA_TURBO = BIT(20), - ODM_BB_DYNAMIC_RX_PATH = BIT(21), +enum phydm_func_idx { /*F_XXX = PHYDM XXX function*/ + + F00_DIG = 0, + F01_RA_MASK = 1, + F02_DYN_TXPWR = 2, + F03_FA_CNT = 3, + F04_RSSI_MNTR = 4, + F05_CCK_PD = 5, + F06_ANT_DIV = 6, + F07_SMT_ANT = 7, + F08_PWR_TRAIN = 8, + F09_RA = 9, + F10_PATH_DIV = 10, + F11_DFS = 11, + F12_DYN_ARFR = 12, + F13_ADPTVTY = 13, + F14_CFO_TRK = 14, + F15_ENV_MNTR = 15, + F16_PRI_CCA = 16, + F17_ADPTV_SOML = 17, + F18_LNA_SAT_CHK = 18, + F19_DYN_RX_PATH = 19 }; +/*=[PHYDM supportability]==========================================*/ +enum odm_ability { + ODM_BB_DIG = BIT(F00_DIG), + ODM_BB_RA_MASK = BIT(F01_RA_MASK), + ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR), + ODM_BB_FA_CNT = BIT(F03_FA_CNT), + ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR), + ODM_BB_CCK_PD = BIT(F05_CCK_PD), + ODM_BB_ANT_DIV = BIT(F06_ANT_DIV), + ODM_BB_SMT_ANT = BIT(F07_SMT_ANT), + ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN), + ODM_BB_RATE_ADAPTIVE = BIT(F09_RA), + ODM_BB_PATH_DIV = BIT(F10_PATH_DIV), + ODM_BB_DFS = BIT(F11_DFS), + ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR), + ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY), + ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK), + ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR), + ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA), + ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML), + ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), + ODM_BB_DYNAMIC_RX_PATH = BIT(F19_DYN_RX_PATH) +}; + +/*=[PHYDM Debug Component]=====================================*/ +enum phydm_dbg_comp { + /*BB Driver Functions*/ + DBG_DIG = BIT(F00_DIG), + DBG_RA_MASK = BIT(F01_RA_MASK), + DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR), + DBG_FA_CNT = BIT(F03_FA_CNT), + DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR), + DBG_CCKPD = BIT(F05_CCK_PD), + DBG_ANT_DIV = BIT(F06_ANT_DIV), + DBG_SMT_ANT = BIT(F07_SMT_ANT), + DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN), + DBG_RA = BIT(F09_RA), + DBG_PATH_DIV = BIT(F10_PATH_DIV), + DBG_DFS = BIT(F11_DFS), + DBG_DYN_ARFR = BIT(F12_DYN_ARFR), + DBG_ADPTVTY = BIT(F13_ADPTVTY), + DBG_CFO_TRK = BIT(F14_CFO_TRK), + DBG_ENV_MNTR = BIT(F15_ENV_MNTR), + DBG_PRI_CCA = BIT(F16_PRI_CCA), + DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML), + DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), + DBG_DYN_RX_PATH = BIT(F19_DYN_RX_PATH), + /*Neet to re-arrange*/ + DBG_PHY_STATUS = BIT(20), + DBG_TMP = BIT(21), + DBG_FW_TRACE = BIT(22), + DBG_TXBF = BIT(23), + DBG_COMMON_FLOW = BIT(24), + ODM_COMP_TX_PWR_TRACK = BIT(25), + ODM_COMP_CALIBRATION = BIT(26), + ODM_COMP_MP = BIT(27), + ODM_PHY_CONFIG = BIT(28), + ODM_COMP_INIT = BIT(29), + ODM_COMP_COMMON = BIT(30), + ODM_COMP_API = BIT(31) +}; + +/*=========================================================*/ + /*ODM_CMNINFO_ONE_PATH_CCA*/ -enum odm_cca_path_e { +enum odm_cca_path { ODM_CCA_2R = 0, ODM_CCA_1R_A = 1, ODM_CCA_1R_B = 2, }; -enum cca_pathdiv_en_e { - CCA_PATHDIV_DISABLE = 0, - CCA_PATHDIV_ENABLE = 1, - +enum phy_reg_pg_type { + PHY_REG_PG_RELATIVE_VALUE = 0, + PHY_REG_PG_EXACT_VALUE = 1 }; enum phydm_offload_ability { @@ -460,10 +496,39 @@ enum phydm_offload_ability { PHYDM_RF_IQK_OFFLOAD = BIT(1), }; +struct phydm_pause_lv { + s8 lv_dig; + s8 lv_cckpd; + s8 lv_antdiv; + s8 lv_adapt; +}; + +struct phydm_func_poiner { + void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len); +}; + +struct pkt_process_info { + u8 phystatus_smp_mode_en; /*send phystatus every sampling time*/ + u8 pre_ppdu_cnt; + u8 lna_idx; + u8 vga_idx; +}; + +#ifdef ODM_CONFIG_BT_COEXIST +struct phydm_bt_info { + boolean is_bt_enabled; /*BT is enabled*/ + boolean is_bt_connect_process; /*BT HS is under connection progress.*/ + u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/ + boolean is_bt_hs_operation; /*BT HS mode is under progress*/ + boolean is_bt_limited_dig; /*BT is busy.*/ +}; +#endif + +struct phydm_iot_center { + boolean is_linked_cmw500; + u8 win_patch_id; /*Customer ID*/ + u32 phydm_patch_id; -enum phy_reg_pg_type { - PHY_REG_PG_RELATIVE_VALUE = 0, - PHY_REG_PG_EXACT_VALUE = 1 }; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) @@ -471,25 +536,28 @@ enum phy_reg_pg_type { typedef #endif - struct PHY_DM_STRUCT -#else/*for AP,ADSL,CE Team*/ - struct PHY_DM_STRUCT + struct dm_struct +#else/*for AP, CE Team*/ + struct dm_struct #endif { /*Add for different team use temporarily*/ - struct _ADAPTER *adapter; /*For CE/NIC team*/ - struct rtl8192cd_priv *priv; /*For AP/ADSL team*/ + void *adapter; /*For CE/NIC team*/ + struct rtl8192cd_priv *priv; /*For AP team*/ /*WHen you use adapter or priv pointer, you must make sure the pointer is ready.*/ boolean odm_ready; enum phy_reg_pg_type phy_reg_pg_value_type; u8 phy_reg_pg_version; - u32 debug_components; + u64 support_ability; /*PHYDM function Supportability*/ + u64 pause_ability; /*PHYDM function pause Supportability*/ + u64 debug_components; + u8 cmn_dbg_msg_period; + u8 cmn_dbg_msg_cnt; u32 fw_debug_components; u32 debug_level; u32 num_qry_phy_status_all; /*CCK + OFDM*/ u32 last_num_qry_phy_status_all; u32 rx_pwdb_ave; - u8 times_2g; boolean is_init_hw_info_by_rfe; /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ @@ -503,8 +571,8 @@ enum phy_reg_pg_type { /*-----------HOOK BEFORE REG INIT-----------*/ u8 support_platform;/*PHYDM Platform info WIN/AP/CE = 1/2/3 */ - u8 normal_rx_path; - u32 support_ability; /*PHYDM function Supportability*/ + u8 normal_rx_path; + boolean brxagcswitch; /* for rx AGC table switch in Microsoft case */ u8 support_interface;/*PHYDM PCIE/USB/SDIO = 1/2/3*/ u32 support_ic_type; /*PHYDM supported IC*/ u8 cut_version; /*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ @@ -525,82 +593,78 @@ enum phy_reg_pg_type { u8 efuse0x3d8; u8 ext_trsw; /*with external TRSW NO/Yes = 0/1*/ u8 ext_lna_gain; /*gain of external lna*/ - u8 patch_id; /*Customer ID*/ boolean is_in_hct_test; u8 wifi_test; boolean is_dual_mac_smart_concurrent; - u32 bk_support_ability; /*SD4 only*/ + u32 bk_support_ability; /*SD4 only*/ u8 with_extenal_ant_switch; - boolean config_bbrf; - u8 odm_regulation_2_4g; - u8 odm_regulation_5g; - u8 iqk_fw_offload; + /*cck agc relative*/ boolean cck_new_agc; - u8 phydm_period; + s8 cck_lna_gain_table[8]; + /*-------------------------------------*/ u32 phydm_sys_up_time; - u8 num_rf_path; + u8 num_rf_path; /*ex: 8821C=1, 8192E=2, 8814B=4*/ u32 soft_ap_special_setting; + s8 s8_dummy; + u8 u8_dummy; + u16 u16_dummy; + u32 u32_dummy; u8 rfe_hwsetting_band; u8 p_advance_ota; - u8 u1_byte_temp; - boolean is_hp_hw_id; + boolean hp_hw_id; boolean BOOLEAN_temp; - u8 is_nbi_enable; + boolean is_dfs_band; + u8 is_receiver_blocking_en; u16 fw_offload_ability; /*-----------HOOK BEFORE REG INIT-----------*/ /*===========================================================*/ /*====[ CALL BY Reference ]=========================================*/ /*===========================================================*/ - - struct _ADAPTER *PADAPTER_temp; - - u8 *p_mac_phy_mode; /*MAC PHY mode SMSP/DMSP/DMDP = 0/1/2*/ - u64 *p_num_tx_bytes_unicast; /*TX Unicast byte count*/ - u64 *p_num_rx_bytes_unicast; /*RX Unicast byte count*/ - u8 *p_wireless_mode; /*Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3*/ - u8 *p_band_type; /*Frequence band 2.4G/5G = 0/1*/ - u8 *p_sec_ch_offset; /*Secondary channel offset don't_care/below/above = 0/1/2*/ - u8 *p_security; /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/ - u8 *p_band_width; /*BW info 20M/40M/80M = 0/1/2*/ - u8 *p_channel; /*central channel number*/ - boolean *p_is_get_value_from_other_mac; /*Common info for 92D DMSP*/ - struct _ADAPTER **p_buddy_adapter; - boolean *p_is_master_of_dmsp; /* MAC0: master, MAC1: slave */ - boolean *p_is_scan_in_process; /*Common info for status*/ - boolean *p_is_power_saving; - u8 *p_one_path_cca; /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path_e.*/ - u8 *p_antenna_test; - boolean *p_is_net_closed; - u8 *pu1_forced_igi_lb; - boolean *p_is_fcs_mode_enable; + + u64 *num_tx_bytes_unicast; /*TX Unicast byte count*/ + u64 *num_rx_bytes_unicast; /*RX Unicast byte count*/ + u8 *band_type; /*Frequence band 2.4G/5G = 0/1*/ + u8 *sec_ch_offset; /*Secondary channel offset don't_care/below/above = 0/1/2*/ + u8 *security; /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/ + u8 *band_width; /*BW info 20M/40M/80M = 0/1/2*/ + u8 *channel; /*central channel number*/ + boolean *is_scan_in_process; /*Common info for status*/ + boolean *is_power_saving; + u8 *one_path_cca; /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/ + u8 *antenna_test; + boolean *is_net_closed; + boolean *is_fcs_mode_enable; /*--------- For 8723B IQK-------------------------------------*/ - boolean *p_is_1_antenna; - u8 *p_rf_default_path; /* 0:S1, 1:S0 */ + boolean *is_1_antenna; + u8 *rf_default_path; /* 0:S1, 1:S0 */ /*-----------------------------------------------------------*/ - u16 *p_forced_data_rate; - u8 *p_enable_antdiv; - u8 *p_enable_adaptivity; + u16 *forced_data_rate; + u8 *enable_antdiv; + u8 *en_adap_soml; + u8 *enable_adaptivity; u8 *hub_usb_mode; /*1: USB 2.0, 2: USB 3.0*/ - boolean *p_is_fw_dw_rsvd_page_in_progress; - u32 *p_current_tx_tp; - u32 *p_current_rx_tp; - u8 *p_sounding_seq; - u32 *p_soft_ap_mode; - u8 *p_mp_mode; - + boolean *is_fw_dw_rsvd_page_in_progress; + u32 *current_tx_tp; + u32 *current_rx_tp; + u8 *sounding_seq; + u32 *soft_ap_mode; + u8 *mp_mode; + u32 *interrupt_mask; + u8 *bb_op_mode; /*===========================================================*/ /*====[ CALL BY VALUE ]===========================================*/ /*===========================================================*/ - + + u8 disable_phydm_watchdog; boolean is_link_in_process; boolean is_wifi_direct; boolean is_wifi_display; boolean is_linked; - boolean bLinkedcmw500; - boolean is_in_lps_pg; boolean bsta_state; u8 rssi_min; + u8 pre_rssi_min; + u8 rssi_max; u8 rssi_min_by_path; boolean is_mp_chip; boolean is_one_entry_only; @@ -611,26 +675,15 @@ enum phy_reg_pg_type { u8 number_linked_client; u8 pre_number_active_client; u8 number_active_client; - - /*---Common info for BTDM-------------------------------------*/ - boolean is_bt_enabled; /*BT is enabled*/ - boolean is_bt_connect_process; /*BT HS is under connection progress.*/ - u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/ - boolean is_bt_hs_operation; /*BT HS mode is under progress*/ - u8 bt_hs_dig_val; /*use BT rssi to decide the DIG value*/ - boolean is_bt_disable_edca_turbo; /*Under some condition, don't enable the EDCA Turbo*/ - boolean is_bt_busy; /*BT is busy.*/ - boolean is_bt_limited_dig; /*BT is busy.*/ boolean is_disable_phy_api; - /*-----------------------------------------------------------*/ - u8 RSSI_A; - u8 RSSI_B; - u8 RSSI_C; - u8 RSSI_D; - u64 RSSI_TRSW; - u64 RSSI_TRSW_H; - u64 RSSI_TRSW_L; - u64 RSSI_TRSW_iso; + u8 rssi_a; + u8 rssi_b; + u8 rssi_c; + u8 rssi_d; + u64 rssi_trsw; + u64 rssi_trsw_h; + u64 rssi_trsw_l; + u64 rssi_trsw_iso; u8 tx_ant_status; u8 rx_ant_status; u8 cck_lna_idx; @@ -649,27 +702,29 @@ enum phy_reg_pg_type { /*[traffic]*/ u8 traffic_load; u8 pre_traffic_load; - u32 tx_tp; - u32 rx_tp; - u32 total_tp; + u32 tx_tp; /*Mbps*/ + u32 rx_tp; /*Mbps*/ + u32 total_tp;/*Mbps*/ + u8 txrx_state_all; /*0: tx, 1:rx, 2:bi-direction*/ u64 cur_tx_ok_cnt; u64 cur_rx_ok_cnt; u64 last_tx_ok_cnt; u64 last_rx_ok_cnt; u16 consecutive_idlel_time; /*unit: second*/ /*---------------------------*/ - u32 bb_swing_offset_a; boolean is_bb_swing_offset_positive_a; - u32 bb_swing_offset_b; boolean is_bb_swing_offset_positive_b; /*[DIG]*/ boolean MPDIG_2G; /*off MPDIG*/ - u8 igi_lower_bound; - u8 igi_upper_bound; - u8 dm_dig_max_TH; - u8 dm_dig_min_TH; - boolean is_dm_initial_gain_enable; + u8 times_2g; /*for MP DIG*/ + + /*[TDMA-DIG]*/ + u8 tdma_dig_timer_ms; + u8 tdma_dig_state_number; + u8 tdma_dig_low_upper_bond; + u8 fix_expire_to_zero; + boolean original_dig_restore; /*---------------------------*/ /*[AntDiv]*/ @@ -705,10 +760,9 @@ enum phy_reg_pg_type { u8 default_rf_set_8821c; u8 current_ant_num_8821c; u8 default_ant_num_8821c; + u8 rfe_type_expand; /*-----------------------------------------------------------*/ /*---For Adaptivtiy---------------------------------------------*/ - u16 nhm_cnt_0; - u16 nhm_cnt_1; s8 TH_L2H_default; s8 th_edcca_hl_diff_default; s8 th_l2h_ini; @@ -716,19 +770,17 @@ enum phy_reg_pg_type { s8 th_l2h_ini_mode2; s8 th_edcca_hl_diff_mode2; boolean carrier_sense_enable; - u8 adaptivity_igi_upper; - boolean adaptivity_flag; + boolean adaptivity_flag; /*Limit IGI upper bound for Adaptivity*/ u8 dc_backoff; boolean adaptivity_enable; u8 ap_total_num; boolean edcca_enable; + u8 odm_regulation_2_4g; + u8 odm_regulation_5g; /*-----------------------------------------------------------*/ u8 pre_dbg_priority; u8 nbi_set_result; - u8 csi_set_result; - u8 csi_set_result_2; - u8 c2h_cmd_start; u8 fw_debug_trace[60]; u8 pre_c2h_seq; @@ -740,17 +792,18 @@ enum phy_reg_pg_type { boolean noisy_decision; /*b_noisy*/ boolean pre_b_noisy; u32 noisy_decision_smooth; + u8 lna_sat_chk_cnt; + u8 lna_sat_chk_duty_cycle; + u32 lna_sat_chk_period_ms; + boolean is_disable_lna_sat_chk; + boolean is_disable_gain_table_switch; /*-----------------------------------------------------------*/ boolean is_disable_dym_ecs; boolean is_disable_dym_ant_weighting; - struct sta_info *p_odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];/*_ODM_STA_INFO, 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??*/ - struct cmn_sta_info *p_phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; - u16 platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/* platform_macid_table[platform_macid] = phydm_macid */ - -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - s32 accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM]; -#endif + struct sta_info *odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];/*odm_sta_info, 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??*/ + struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; + u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; #if (RATE_ADAPTIVE_SUPPORT == 1) u16 currmin_rpt_time; @@ -758,8 +811,8 @@ enum phy_reg_pg_type { /*Use mac_id as array index. STA mac_id=0, VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/ #endif boolean ra_support88e; /*2012/02/14 MH Add to share 88E ra with other SW team.We need to colelct all support abilit to a proper area.*/ - boolean *p_is_driver_stopped; - boolean *p_is_driver_is_going_to_pnp_set_power_sleep; + boolean *is_driver_stopped; + boolean *is_driver_is_going_to_pnp_set_power_sleep; boolean *pinit_adpt_in_progress; boolean is_user_assign_level; u8 RSSI_BT; /*come from BT*/ @@ -769,23 +822,21 @@ enum phy_reg_pg_type { boolean is_psd_active; /*-----------------------------------------------------------*/ - u8 is_use_ra_mask; /*for rate adaptive, in fact, 88c/92c fw will handle this*/ boolean bsomlenabled; /* for dynamic SoML control */ - boolean bhtstfenabled; /* for dynamic HTSTF gain control */ + boolean bhtstfdisabled; /* for dynamic HTSTF gain control */ + boolean disrxhpsoml; /* for dynamic RxHP control with SoML on/off */ u32 n_iqk_cnt; u32 n_iqk_ok_cnt; u32 n_iqk_fail_cnt; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - u8 force_power_training_state; /*Power Training*/ - boolean is_change_state; - u32 PT_score; - u64 ofdm_rx_cnt; - u64 cck_rx_cnt; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + boolean config_bbrf; #endif boolean is_disable_power_training; + boolean is_bt_continuous_turn; u8 dynamic_tx_high_power_lvl; u8 last_dtp_lvl; + u8 min_power_index; u32 tx_agc_ofdm_18_6; u8 rx_pkt_type; @@ -803,14 +854,14 @@ enum phy_reg_pg_type { /*=== PHYDM Timer ========================================== (start)*/ - struct timer_list mpt_dig_timer; /*MPT DIG timer*/ - struct timer_list path_div_switch_timer; - struct timer_list cck_path_diversity_timer; /*2011.09.27 add for path Diversity*/ - struct timer_list fast_ant_training_timer; + struct phydm_timer_list mpt_dig_timer; /*MPT DIG timer*/ + struct phydm_timer_list path_div_switch_timer; + struct phydm_timer_list cck_path_diversity_timer; /*2011.09.27 add for path Diversity*/ + struct phydm_timer_list fast_ant_training_timer; #ifdef ODM_EVM_ENHANCE_ANTDIV - struct timer_list evm_fast_ant_training_timer; + struct phydm_timer_list evm_fast_ant_training_timer; #endif - struct timer_list sbdcnt_timer; + struct phydm_timer_list sbdcnt_timer; /*=== PHYDM Workitem ======================================= (start)*/ @@ -820,7 +871,6 @@ enum phy_reg_pg_type { RT_WORK_ITEM path_div_switch_workitem; RT_WORK_ITEM cck_path_diversity_workitem; RT_WORK_ITEM fast_ant_training_workitem; - RT_WORK_ITEM mpt_dig_workitem; RT_WORK_ITEM ra_rpt_workitem; RT_WORK_ITEM sbdcnt_workitem; #endif @@ -828,59 +878,79 @@ enum phy_reg_pg_type { /*=== PHYDM Structure ======================================== (start)*/ - struct _ADAPTIVITY_STATISTICS adaptivity; -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) - struct _ODM_NOISE_MONITOR_ noise_level; + struct phydm_func_poiner phydm_func_handler; + struct phydm_iot_center iot_table; + +#ifdef ODM_CONFIG_BT_COEXIST + struct phydm_bt_info bt_info_table; +#endif + + struct pkt_process_info pkt_proc_struct; + struct phydm_adaptivity_struct adaptivity; + struct _DFS_STATISTICS dfs; + + struct odm_noise_monitor noise_level; + + struct odm_phy_dbg_info phy_dbg_info; + +#ifdef CONFIG_ADAPTIVE_SOML + struct adaptive_soml dm_soml_table; #endif - struct _odm_phy_dbg_info_ phy_dbg_info; #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) struct _BF_DIV_COEX_ dm_bdc_table; + #endif + + #if (defined(CONFIG_HL_SMART_ANTENNA)) + struct smt_ant_honbo dm_sat_table; + #endif #endif -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) - struct _SMART_ANTENNA_TRAINNING_ dm_sat_table; +#if (defined(CONFIG_SMART_ANTENNA)) + struct smt_ant smtant_table; #endif + struct phydm_fat_struct dm_fat_table; + struct phydm_dig_struct dm_dig_table; + struct phydm_lna_sat_info_struct dm_lna_sat_info; + +#ifdef PHYDM_SUPPORT_CCKPD + struct phydm_cckpd_struct dm_cckpd_table; #endif - struct _FAST_ANTENNA_TRAINNING_ dm_fat_table; - struct _dynamic_initial_gain_threshold_ dm_dig_table; -#if (defined(CONFIG_BB_POWER_SAVING)) - struct _dynamic_power_saving dm_ps_table; +#ifdef PHYDM_PRIMARY_CCA + struct phydm_pricca_struct dm_pri_cca; #endif - struct _dynamic_primary_cca dm_pri_cca; - struct _rate_adaptive_table_ dm_ra_table; - struct _FALSE_ALARM_STATISTICS false_alm_cnt; - struct _FALSE_ALARM_STATISTICS flase_alm_cnt_buddy_adapter; - struct _sw_antenna_switch_ dm_swat_table; - struct _CFO_TRACKING_ dm_cfo_track; - struct _ACS_ dm_acs; - struct _CCX_INFO dm_ccx_info; + struct ra_table dm_ra_table; + struct phydm_fa_struct false_alm_cnt; +#ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_fa_acc_struct false_alm_cnt_acc; +#endif + struct sw_antenna_switch dm_swat_table; + struct phydm_cfo_track_struct dm_cfo_track; + struct ccx_info dm_ccx_info; struct _hal_rf_ rf_table; /*for HALRF function*/ - struct _ODM_RATE_ADAPTIVE rate_adaptive; - struct odm_rf_calibration_structure rf_calibrate_info; + struct dm_rf_calibration_struct rf_calibrate_info; struct odm_power_trim_data power_trim_data; #if (RTL8822B_SUPPORT == 1) - struct phydm_rtl8822b_struct phydm_rtl8822b; -#endif -#if (CONFIG_PSD_TOOL == 1) - struct _PHYDM_PSD_ dm_psd_table; + struct drp_rtl8822b_struct phydm_rtl8822b; +#endif + +#ifdef CONFIG_PSD_TOOL + struct psd_info dm_psd_table; #endif #if (PHYDM_LA_MODE_SUPPORT == 1) - struct _RT_ADCSMP adcsmp; + struct rt_adcsmp adcsmp; #endif -#if (CONFIG_DYNAMIC_RX_PATH == 1) +#ifdef CONFIG_DYNAMIC_RX_PATH struct _DYNAMIC_RX_PATH_ dm_drp_table; #endif -#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - struct _IQK_INFORMATION IQK_info; -#endif + struct dm_iqk_info IQK_info; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) struct _path_div_parameter_define_ path_iqk; @@ -898,14 +968,22 @@ enum phy_reg_pg_type { #if (BEAMFORMING_SUPPORT == 1) struct _RT_BEAMFORMING_INFO beamforming_info; #endif +#endif +#ifdef PHYDM_AUTO_DEGBUG + struct phydm_auto_dbg_struc auto_dbg_table; #endif + struct phydm_pause_lv pause_lv_table; + struct phydm_api_stuc api_table; +#ifdef PHYDM_POWER_TRAINING_SUPPORT + struct phydm_pow_train_stuc pow_train_table; +#endif /*==========================================================*/ #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) #if (RT_PLATFORM != PLATFORM_LINUX) -}PHY_DM_STRUCT; /*DM_Dynamic_Mechanism_Structure*/ +}dm_struct; /*DM_Dynamic_Mechanism_Structure*/ #else }; #endif @@ -914,31 +992,31 @@ enum phy_reg_pg_type { }; #endif - enum phydm_adv_ota { PHYDM_PATHB_1RCCA = BIT(0), PHYDM_HP_OTA_SETTING_A = BIT(1), PHYDM_HP_OTA_SETTING_B = BIT(2), PHYDM_ASUS_OTA_SETTING = BIT(3), PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4), + PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5), + PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6), + +}; +enum phydm_bb_op_mode { + PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/ + PHYDM_BALANCE_MODE = 1, /*Service more than one device*/ }; enum phydm_structure_type { PHYDM_FALSEALMCNT, PHYDM_CFOTRACK, PHYDM_ADAPTIVITY, + PHYDM_DFS, PHYDM_ROMINFO, }; -enum odm_rf_content { - odm_radioa_txt = 0x1000, - odm_radiob_txt = 0x1001, - odm_radioc_txt = 0x1002, - odm_radiod_txt = 0x1003 -}; - enum odm_bb_config_type { CONFIG_BB_PHY_REG, CONFIG_BB_AGC_TAB, @@ -980,121 +1058,51 @@ enum rt_status { }; #endif /*end of enum rt_status definition*/ -#ifdef REMOVE_PACK - #pragma pack() -#endif - -/*===========================================================*/ -/*AGC RX High Power mode*/ -/*===========================================================*/ -#define lna_low_gain_1 0x64 -#define lna_low_gain_2 0x5A -#define lna_low_gain_3 0x58 - -#define FA_RXHP_TH1 5000 -#define FA_RXHP_TH2 1500 -#define FA_RXHP_TH3 800 -#define FA_RXHP_TH4 600 -#define FA_RXHP_TH5 500 - -enum dm_1r_cca_e { - CCA_1R = 0, - CCA_2R = 1, - CCA_MAX = 2, -}; - -enum dm_rf_e { - rf_save = 0, - rf_normal = 1, - RF_MAX = 2, -}; - -/*check Sta pointer valid or not*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #define IS_STA_VALID(p_sta) (p_sta && p_sta->expire_to) -#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #define IS_STA_VALID(p_sta) (p_sta && p_sta->bUsed) -#else - #define IS_STA_VALID(p_sta) (p_sta) -#endif - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP)) -boolean -odm_check_power_status( - struct _ADAPTER *adapter -); -#endif - -u32 odm_convert_to_db(u32 value); - -u32 odm_convert_to_linear(u32 value); - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) void -odm_dm_watchdog_lps( - struct PHY_DM_STRUCT *p_dm_odm -); -#endif - -s32 -odm_pwdb_conversion( - s32 X, - u32 total_bit, - u32 decimal_bit +phydm_watchdog_lps( + struct dm_struct *dm ); -s32 -odm_sign_conversion( - s32 value, - u32 total_bit +void +phydm_watchdog_lps_32k( + struct dm_struct *dm ); void phydm_txcurrentcalibration( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); -void -phydm_seq_sorting( - void *p_dm_void, - u32 *p_value, - u32 *rank_idx, - u32 *p_idx_out, - u8 seq_length -); - void phydm_dm_early_init( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); void odm_dm_init( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); void odm_dm_reset( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); void phydm_fwoffload_ability_init( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum phydm_offload_ability offload_ability ); void phydm_fwoffload_ability_clear( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum phydm_offload_ability offload_ability ); - void phydm_support_ability_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, char *output, @@ -1102,220 +1110,128 @@ phydm_support_ability_debug( ); void -phydm_config_ofdm_rx_path( - struct PHY_DM_STRUCT *p_dm_odm, - u32 path +phydm_pause_dm_watchdog( + void *dm_void, + enum phydm_pause_type pause_type ); void -phydm_config_trx_path( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len +phydm_watchdog( + struct dm_struct *dm ); void -odm_dm_watchdog( - struct PHY_DM_STRUCT *p_dm_odm +phydm_watchdog_mp( + struct dm_struct *dm +); + +u8 +phydm_pause_func( + void *dm_void, + enum phydm_func_idx pause_func, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_lv, + u8 val_lehgth, + u32 *val_buf + ); void -phydm_watchdog_mp( - struct PHY_DM_STRUCT *p_dm_odm +phydm_pause_func_console( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num ); void odm_cmn_info_init( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_cmninfo_e cmn_info, - u32 value + struct dm_struct *dm, + enum odm_cmninfo cmn_info, + u64 value ); void odm_cmn_info_hook( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_cmninfo_e cmn_info, - void *p_value + struct dm_struct *dm, + enum odm_cmninfo cmn_info, + void *value ); void odm_cmn_info_update( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 cmn_info, u64 value ); u32 phydm_cmn_info_query( - struct PHY_DM_STRUCT *p_dm_odm, - enum phydm_info_query_e info_type + struct dm_struct *dm, + enum phydm_info_query info_type ); -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -void -odm_init_all_threads( - struct PHY_DM_STRUCT *p_dm_odm -); - -void -odm_stop_all_threads( - struct PHY_DM_STRUCT *p_dm_odm -); -#endif - void odm_init_all_timers( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); void odm_cancel_all_timers( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); void odm_release_all_timers( - struct PHY_DM_STRUCT *p_dm_odm -); - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm); -void odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm_odm); - -u64 -platform_division64( - u64 x, - u64 y + struct dm_struct *dm ); -#define dm_change_dynamic_init_gain_thresh odm_change_dynamic_init_gain_thresh - -enum dm_dig_connect_e { - DIG_STA_DISCONNECT = 0, - DIG_STA_CONNECT = 1, - DIG_STA_BEFORE_CONNECT = 2, - DIG_MULTI_STA_DISCONNECT = 3, - DIG_MULTI_STA_CONNECT = 4, - DIG_CONNECT_MAX -}; - -/*2012/01/12 MH Check afapter status. Temp fix BSOD.*/ - -#define HAL_ADAPTER_STS_CHK(p_dm_odm) do {\ - if (p_dm_odm->adapter == NULL) { \ - \ - return;\ - } \ - } while (0) - -#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ - void * phydm_get_structure( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 structure_type ); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) || (DM_ODM_SUPPORT_TYPE == ODM_CE) - /*===========================================================*/ - /* The following is for compile only*/ - /*===========================================================*/ - - #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - #define IS_HARDWARE_TYPE_8188E(_adapter) false - #define IS_HARDWARE_TYPE_8188F(_adapter) false - #define IS_HARDWARE_TYPE_8703B(_adapter) false - #define IS_HARDWARE_TYPE_8723D(_adapter) false - #define IS_HARDWARE_TYPE_8821C(_adapter) false - #define IS_HARDWARE_TYPE_8812AU(_adapter) false - #define IS_HARDWARE_TYPE_8814A(_adapter) false - #define IS_HARDWARE_TYPE_8814AU(_adapter) false - #define IS_HARDWARE_TYPE_8814AE(_adapter) false - #define IS_HARDWARE_TYPE_8814AS(_adapter) false - #define IS_HARDWARE_TYPE_8723BU(_adapter) false - #define IS_HARDWARE_TYPE_8822BU(_adapter) false - #define IS_HARDWARE_TYPE_8822BS(_adapter) false - #define IS_HARDWARE_TYPE_JAGUAR(_Adapter) \ - (IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter)) - #else - #define IS_HARDWARE_TYPE_8723A(_adapter) false - #endif - #define IS_HARDWARE_TYPE_8723AE(_adapter) false - #define IS_HARDWARE_TYPE_8192C(_adapter) false - #define IS_HARDWARE_TYPE_8192D(_adapter) false - #define RF_T_METER_92D 0x42 - - - #define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc) LE_BITS_TO_1BYTE(__prx_status_desc+12, 0, 6) - - #define REG_CONFIG_RAM64X16 0xb2c - - #define TARGET_CHNL_NUM_2G_5G 59 - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - u8 get_right_chnl_place_for_iqk(u8 chnl); - #endif - - /* *********************************************************** */ -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm); -#endif - -void phydm_noisy_detection( - struct PHY_DM_STRUCT *p_dm_odm -); - void -phydm_set_ext_switch( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len +phydm_dc_cancellation( + struct dm_struct *dm ); void -phydm_api_debug( - void *p_dm_void, - u32 function_map, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len +phydm_receiver_blocking( + void *dm_void ); -u8 -phydm_csi_mask_setting( - void *p_dm_void, - u32 enable, - u32 channel, - u32 bw, - u32 f_interference, - u32 Second_ch +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void +odm_init_all_work_items( + struct dm_struct *dm ); +void +odm_free_all_work_items( + struct dm_struct *dm +); +#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ -u8 -phydm_nbi_setting( - void *p_dm_void, - u32 enable, - u32 channel, - u32 bw, - u32 f_interference, - u32 second_ch +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +void +odm_dtc( + struct dm_struct *dm ); +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) void -phydm_dc_cancellation( - struct PHY_DM_STRUCT *p_dm_odm +odm_init_all_threads( + struct dm_struct *dm ); void -phydm_receiver_blocking( - void *p_dm_void +odm_stop_all_threads( + struct dm_struct *dm ); #endif + +#endif diff --git a/hal/phydm/phydm.mk b/hal/phydm/phydm.mk index 499a7b0..1b9ade7 100644 --- a/hal/phydm/phydm.mk +++ b/hal/phydm/phydm.mk @@ -2,19 +2,20 @@ EXTRA_CFLAGS += -I$(src)/hal/phydm _PHYDM_FILES := hal/phydm/phydm_debug.o \ hal/phydm/phydm_antdiv.o\ + hal/phydm/phydm_soml.o\ + hal/phydm/phydm_smt_ant.o\ hal/phydm/phydm_antdect.o\ hal/phydm/phydm_interface.o\ + hal/phydm/phydm_phystatus.o\ hal/phydm/phydm_hwconfig.o\ hal/phydm/phydm.o\ hal/phydm/phydm_dig.o\ hal/phydm/phydm_pathdiv.o\ hal/phydm/phydm_rainfo.o\ - hal/phydm/phydm_dynamicbbpowersaving.o\ hal/phydm/phydm_dynamictxpower.o\ hal/phydm/phydm_adaptivity.o\ hal/phydm/phydm_cfotracking.o\ hal/phydm/phydm_noisemonitor.o\ - hal/phydm/phydm_acs.o\ hal/phydm/phydm_beamforming.o\ hal/phydm/phydm_dfs.o\ hal/phydm/txbf/halcomtxbf.o\ @@ -23,9 +24,17 @@ _PHYDM_FILES := hal/phydm/phydm_debug.o \ hal/phydm/phydm_adc_sampling.o\ hal/phydm/phydm_ccx.o\ hal/phydm/phydm_psd.o\ + hal/phydm/phydm_primary_cca.o\ + hal/phydm/phydm_cck_pd.o\ + hal/phydm/phydm_rssi_monitor.o\ + hal/phydm/phydm_auto_dbg.o\ + hal/phydm/phydm_math_lib.o\ + hal/phydm/phydm_api.o\ + hal/phydm/phydm_pow_train.o\ hal/phydm/halrf/halrf.o\ hal/phydm/halrf/halphyrf_ce.o\ hal/phydm/halrf/halrf_powertracking_ce.o\ + hal/phydm/halrf/halrf_powertracking.o\ hal/phydm/halrf/halrf_kfree.o ifeq ($(CONFIG_RTL8188E), y) diff --git a/hal/phydm/phydm_acs.c b/hal/phydm/phydm_acs.c index 47f2ebf..de49bb3 100644 --- a/hal/phydm/phydm_acs.c +++ b/hal/phydm/phydm_acs.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -22,88 +32,59 @@ u8 odm_get_auto_channel_select_result( - void *p_dm_void, + void *dm_void, u8 band ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct acs_info *acs = &dm->dm_acs; + + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__); #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) if (band == ODM_BAND_2_4G) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[struct _ACS_] odm_get_auto_channel_select_result(): clean_channel_2g(%d)\n", p_acs->clean_channel_2g)); - return (u8)p_acs->clean_channel_2g; + PHYDM_DBG(dm, ODM_COMP_API, "clean_CH_2g=%d\n", acs->clean_channel_2g); + return (u8)acs->clean_channel_2g; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[struct _ACS_] odm_get_auto_channel_select_result(): clean_channel_5g(%d)\n", p_acs->clean_channel_5g)); - return (u8)p_acs->clean_channel_5g; + PHYDM_DBG(dm, ODM_COMP_API, "clean_CH_5g=%d\n", acs->clean_channel_5g); + return (u8)acs->clean_channel_5g; } #else - return (u8)p_acs->clean_channel_2g; + return (u8)acs->clean_channel_2g; #endif } -void -odm_auto_channel_select_setting( - void *p_dm_void, - boolean is_enable -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u16 period = 0x2710;/* 40ms in default */ - u16 nhm_type = 0x7; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select_setting()=========>\n")); - - if (is_enable) { - /* 20 ms */ - period = 0x1388; - nhm_type = 0x1; - } - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - /* PHY parameters initialize for ac series */ - odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, period); /* 0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms */ - /* odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8)|BIT9|BIT10, nhm_type); */ /* 0x994[9:8]=3 enable CCX */ - } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - /* PHY parameters initialize for n series */ - odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11N + 2, period); /* 0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms */ - /* odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10)|BIT9|BIT8, nhm_type); */ /* 0x890[9:8]=3 enable CCX */ - } -#endif -} - void odm_auto_channel_select_init( - void *p_dm_void + void *dm_void ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct acs_info *acs = &dm->dm_acs; u8 i; - if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) + if (!(dm->support_ability & ODM_BB_ENV_MONITOR)) return; - if (p_acs->is_force_acs_result) + if (acs->is_force_acs_result) return; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select_init()=========>\n")); + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__); - p_acs->clean_channel_2g = 1; - p_acs->clean_channel_5g = 36; + acs->clean_channel_2g = 1; + acs->clean_channel_5g = 36; for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) { - p_acs->channel_info_2g[0][i] = 0; - p_acs->channel_info_2g[1][i] = 0; + acs->channel_info_2g[0][i] = 0; + acs->channel_info_2g[1][i] = 0; } - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) { - p_acs->channel_info_5g[0][i] = 0; - p_acs->channel_info_5g[1][i] = 0; + acs->channel_info_5g[0][i] = 0; + acs->channel_info_5g[1][i] = 0; } } #endif @@ -111,200 +92,233 @@ odm_auto_channel_select_init( void odm_auto_channel_select_reset( - void *p_dm_void + void *dm_void ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct acs_info *acs = &dm->dm_acs; + struct ccx_info *ccx_info = &dm->dm_ccx_info; - if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) + if (!(dm->support_ability & ODM_BB_ENV_MONITOR)) return; - if (p_acs->is_force_acs_result) + if (acs->is_force_acs_result) return; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select_reset()=========>\n")); + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__); - odm_auto_channel_select_setting(p_dm_odm, true); /* for 20ms measurement */ - phydm_nhm_counter_statistics_reset(p_dm_odm); + ccx_info->nhm_period = 0x1388; /*20ms*/ + phydm_nhm_setting(dm, SET_NHM_SETTING); + phydm_nhm_trigger(dm); #endif } void odm_auto_channel_select( - void *p_dm_void, + void *dm_void, u8 channel ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct acs_info *acs = &dm->dm_acs; + struct ccx_info *ccx_info = &dm->dm_ccx_info; u8 channel_idx = 0, search_idx = 0; + u8 noisy_nhm_th = 0x52; + u8 i, noisy_nhm_th_index, low_pwr_cnt = 0; u16 max_score = 0; - if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_auto_channel_select(): Return: support_ability ODM_BB_NHM_CNT is disabled\n")); + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__); + + if (!(dm->support_ability & ODM_BB_ENV_MONITOR)) { + PHYDM_DBG(dm, DBG_DIG, "Return: Not support\n"); return; } - if (p_acs->is_force_acs_result) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_auto_channel_select(): Force 2G clean channel = %d, 5G clean channel = %d\n", - p_acs->clean_channel_2g, p_acs->clean_channel_5g)); + if (acs->is_force_acs_result) { + PHYDM_DBG(dm, DBG_DIG, "Force clean CH{2G,5G}={%d,%d}\n", + acs->clean_channel_2g, acs->clean_channel_5g); return; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select(): channel = %d=========>\n", channel)); + PHYDM_DBG(dm, ODM_COMP_API, "CH=%d\n", channel); - phydm_get_nhm_counter_statistics(p_dm_odm); - odm_auto_channel_select_setting(p_dm_odm, false); + phydm_get_nhm_result(dm); + noisy_nhm_th_index = (noisy_nhm_th - ccx_info->nhm_th[0]) << 2; + + for (i = 0; i <= 11; i++) { + if (i <= noisy_nhm_th_index) + low_pwr_cnt += ccx_info->nhm_result[i]; + } + + ccx_info->nhm_period = 0x2710; + phydm_nhm_setting(dm, SET_NHM_SETTING); if (channel >= 1 && channel <= 14) { channel_idx = channel - 1; - p_acs->channel_info_2g[1][channel_idx]++; + acs->channel_info_2g[1][channel_idx]++; - if (p_acs->channel_info_2g[1][channel_idx] >= 2) - p_acs->channel_info_2g[0][channel_idx] = (p_acs->channel_info_2g[0][channel_idx] >> 1) + - (p_acs->channel_info_2g[0][channel_idx] >> 2) + (p_dm_odm->nhm_cnt_0 >> 2); + if (acs->channel_info_2g[1][channel_idx] >= 2) + acs->channel_info_2g[0][channel_idx] = (acs->channel_info_2g[0][channel_idx] >> 1) + + (acs->channel_info_2g[0][channel_idx] >> 2) + (low_pwr_cnt >> 2); else - p_acs->channel_info_2g[0][channel_idx] = p_dm_odm->nhm_cnt_0; + acs->channel_info_2g[0][channel_idx] = low_pwr_cnt; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select(): nhm_cnt_0 = %d\n", p_dm_odm->nhm_cnt_0)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", channel_idx, p_acs->channel_info_2g[0][channel_idx], channel_idx, p_acs->channel_info_2g[1][channel_idx])); + PHYDM_DBG(dm, ODM_COMP_API, "low_pwr_cnt = %d\n", low_pwr_cnt); + PHYDM_DBG(dm, ODM_COMP_API, "CH_Info[0][%d]=%d, CH_Info[1][%d]=%d\n", channel_idx, acs->channel_info_2g[0][channel_idx], channel_idx, acs->channel_info_2g[1][channel_idx]); for (search_idx = 0; search_idx < ODM_MAX_CHANNEL_2G; search_idx++) { - if (p_acs->channel_info_2g[1][search_idx] != 0 && p_acs->channel_info_2g[0][search_idx] >= max_score) { - max_score = p_acs->channel_info_2g[0][search_idx]; - p_acs->clean_channel_2g = search_idx + 1; + if (acs->channel_info_2g[1][search_idx] != 0 && acs->channel_info_2g[0][search_idx] >= max_score) { + max_score = acs->channel_info_2g[0][search_idx]; + acs->clean_channel_2g = search_idx + 1; } } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_auto_channel_select(): 2G: clean_channel_2g = %d, max_score = %d\n", - p_acs->clean_channel_2g, max_score)); + PHYDM_DBG(dm, ODM_COMP_API, "clean_CH_2g=%d, max_score=%d\n", + acs->clean_channel_2g, max_score); } else if (channel >= 36) { /* Need to do */ - p_acs->clean_channel_5g = channel; + acs->clean_channel_5g = channel; } #endif } +boolean +phydm_acs_check( + void *dm_void +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rtl8192cd_priv *priv = dm->priv; + + if ((priv->auto_channel != 0) && (priv->auto_channel != 2)) /* if struct acs_info running, do not do FA/CCA counter read */ + return true; + else + return false; +#else + return false; +#endif +} + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) void phydm_auto_channel_select_setting_ap( - void *p_dm_void, + void *dm_void, u32 setting, /* 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING */ u32 acs_step ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct rtl8192cd_priv *priv = p_dm_odm->priv; - struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rtl8192cd_priv *priv = dm->priv; + struct acs_info *acs = &dm->dm_acs; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSettingAP()=========>\n")); + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__); /* 3 Store Default setting */ if (setting == STORE_DEFAULT_NHM_SETTING) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("STORE_DEFAULT_NHM_SETTING\n")); - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { /* store reg0x990, reg0x994, reg0x998, reg0x99c, Reg0x9a0 */ - p_acs->reg0x990 = odm_read_4byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC); /* reg0x990 */ - p_acs->reg0x994 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC); /* reg0x994 */ - p_acs->reg0x998 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC); /* reg0x998 */ - p_acs->reg0x99c = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC); /* Reg0x99c */ - p_acs->reg0x9a0 = odm_read_1byte(p_dm_odm, ODM_REG_NHM_TH8_11AC); /* Reg0x9a0, u8 */ - } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - p_acs->reg0x890 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N); /* reg0x890 */ - p_acs->reg0x894 = odm_read_4byte(p_dm_odm, ODM_REG_CCX_PERIOD_11N); /* reg0x894 */ - p_acs->reg0x898 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N); /* reg0x898 */ - p_acs->reg0x89c = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N); /* Reg0x89c */ - p_acs->reg0xe28 = odm_read_1byte(p_dm_odm, ODM_REG_NHM_TH8_11N); /* Reg0xe28, u8 */ + PHYDM_DBG(dm, ODM_COMP_API, "STORE_DEFAULT_NHM_SETTING\n"); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { /* store reg0x990, reg0x994, reg0x998, reg0x99c, Reg0x9a0 */ + acs->reg0x990 = odm_read_4byte(dm, ODM_REG_CCX_PERIOD_11AC); /* reg0x990 */ + acs->reg0x994 = odm_read_4byte(dm, ODM_REG_NHM_TH9_TH10_11AC); /* reg0x994 */ + acs->reg0x998 = odm_read_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11AC); /* reg0x998 */ + acs->reg0x99c = odm_read_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11AC); /* Reg0x99c */ + acs->reg0x9a0 = odm_read_1byte(dm, ODM_REG_NHM_TH8_11AC); /* Reg0x9a0, u8 */ + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + acs->reg0x890 = odm_read_4byte(dm, ODM_REG_NHM_TH9_TH10_11N); /* reg0x890 */ + acs->reg0x894 = odm_read_4byte(dm, ODM_REG_CCX_PERIOD_11N); /* reg0x894 */ + acs->reg0x898 = odm_read_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11N); /* reg0x898 */ + acs->reg0x89c = odm_read_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11N); /* Reg0x89c */ + acs->reg0xe28 = odm_read_1byte(dm, ODM_REG_NHM_TH8_11N); /* Reg0xe28, u8 */ } } /* 3 Restore Default setting */ else if (setting == RESTORE_DEFAULT_NHM_SETTING) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("RESTORE_DEFAULT_NHM_SETTING\n")); - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { /* store reg0x990, reg0x994, reg0x998, reg0x99c, Reg0x9a0 */ - odm_write_4byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, p_acs->reg0x990); - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, p_acs->reg0x994); - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, p_acs->reg0x998); - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, p_acs->reg0x99c); - odm_write_1byte(p_dm_odm, ODM_REG_NHM_TH8_11AC, p_acs->reg0x9a0); - } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, p_acs->reg0x890); - odm_write_4byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, p_acs->reg0x894); - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, p_acs->reg0x898); - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, p_acs->reg0x89c); - odm_write_1byte(p_dm_odm, ODM_REG_NHM_TH8_11N, p_acs->reg0xe28); + PHYDM_DBG(dm, ODM_COMP_API, "RESTORE_DEFAULT_NHM_SETTING\n"); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { /* store reg0x990, reg0x994, reg0x998, reg0x99c, Reg0x9a0 */ + odm_write_4byte(dm, ODM_REG_CCX_PERIOD_11AC, acs->reg0x990); + odm_write_4byte(dm, ODM_REG_NHM_TH9_TH10_11AC, acs->reg0x994); + odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, acs->reg0x998); + odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, acs->reg0x99c); + odm_write_1byte(dm, ODM_REG_NHM_TH8_11AC, acs->reg0x9a0); + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_write_4byte(dm, ODM_REG_NHM_TH9_TH10_11N, acs->reg0x890); + odm_write_4byte(dm, ODM_REG_CCX_PERIOD_11AC, acs->reg0x894); + odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11N, acs->reg0x898); + odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11N, acs->reg0x89c); + odm_write_1byte(dm, ODM_REG_NHM_TH8_11N, acs->reg0xe28); } } - /* 3 struct _ACS_ setting */ + /* 3 struct acs_info setting */ else if (setting == ACS_NHM_SETTING) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("ACS_NHM_SETTING\n")); + PHYDM_DBG(dm, ODM_COMP_API, "ACS_NHM_SETTING\n"); u16 period; period = 0x61a8; - p_acs->acs_step = acs_step; + acs->acs_step = acs_step; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { /* 4 Set NHM period, 0x990[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms */ - odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, period); + odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11AC + 2, period); /* 4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 */ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8) | BIT(9) | BIT(10), 3); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8) | BIT(9) | BIT(10), 3); - if (p_acs->acs_step == 0) { + if (acs->acs_step == 0) { /* 4 Set IGI */ - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E); - if (get_rf_mimo_mode(priv) != MIMO_1T1R) - odm_set_bb_reg(p_dm_odm, 0xe50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E); + odm_set_bb_reg(dm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E); + if (get_rf_mimo_mode(priv) != RF_1T1R) + odm_set_bb_reg(dm, 0xe50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E); - /* 4 Set struct _ACS_ NHM threshold */ - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x82786e64); - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff8c); - odm_write_1byte(p_dm_odm, ODM_REG_NHM_TH8_11AC, 0xff); - odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); + /* 4 Set struct acs_info NHM threshold */ + odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x82786e64); + odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff8c); + odm_write_1byte(dm, ODM_REG_NHM_TH8_11AC, 0xff); + odm_write_2byte(dm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); - } else if (p_acs->acs_step == 1) { + } else if (acs->acs_step == 1) { /* 4 Set IGI */ - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A); - if (get_rf_mimo_mode(priv) != MIMO_1T1R) - odm_set_bb_reg(p_dm_odm, 0xe50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A); + odm_set_bb_reg(dm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A); + if (get_rf_mimo_mode(priv) != RF_1T1R) + odm_set_bb_reg(dm, 0xe50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A); - /* 4 Set struct _ACS_ NHM threshold */ - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x5a50463c); - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff64); + /* 4 Set struct acs_info NHM threshold */ + odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x5a50463c); + odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff64); } - } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { /* 4 Set NHM period, 0x894[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms */ - odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, period); + odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11AC + 2, period); /* 4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 */ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(8) | BIT(9) | BIT(10), 3); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(8) | BIT(9) | BIT(10), 3); - if (p_acs->acs_step == 0) { + if (acs->acs_step == 0) { /* 4 Set IGI */ - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E); - if (get_rf_mimo_mode(priv) != MIMO_1T1R) - odm_set_bb_reg(p_dm_odm, 0xc58, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E); + odm_set_bb_reg(dm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E); + if (get_rf_mimo_mode(priv) != RF_1T1R) + odm_set_bb_reg(dm, 0xc58, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E); - /* 4 Set struct _ACS_ NHM threshold */ - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x82786e64); - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff8c); - odm_write_1byte(p_dm_odm, ODM_REG_NHM_TH8_11N, 0xff); - odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); + /* 4 Set struct acs_info NHM threshold */ + odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x82786e64); + odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff8c); + odm_write_1byte(dm, ODM_REG_NHM_TH8_11N, 0xff); + odm_write_2byte(dm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); - } else if (p_acs->acs_step == 1) { + } else if (acs->acs_step == 1) { /* 4 Set IGI */ - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A); - if (get_rf_mimo_mode(priv) != MIMO_1T1R) - odm_set_bb_reg(p_dm_odm, 0xc58, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A); + odm_set_bb_reg(dm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A); + if (get_rf_mimo_mode(priv) != RF_1T1R) + odm_set_bb_reg(dm, 0xc58, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A); - /* 4 Set struct _ACS_ NHM threshold */ - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x5a50463c); - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff64); + /* 4 Set struct acs_info NHM threshold */ + odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x5a50463c); + odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff64); } } @@ -314,83 +328,77 @@ phydm_auto_channel_select_setting_ap( void phydm_get_nhm_statistics_ap( - void *p_dm_void, + void *dm_void, u32 idx, /* @ 2G, Real channel number = idx+1 */ u32 acs_step ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct rtl8192cd_priv *priv = p_dm_odm->priv; - struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rtl8192cd_priv *priv = dm->priv; + struct acs_info *acs = &dm->dm_acs; u32 value32 = 0; u8 i; - p_acs->acs_step = acs_step; + acs->acs_step = acs_step; - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + if (dm->support_ic_type & ODM_IC_11N_SERIES) { /* 4 Check if NHM result is ready */ for (i = 0; i < 20; i++) { - ODM_delay_ms(1); - if (odm_get_bb_reg(p_dm_odm, REG_FPGA0_PSD_REPORT, BIT(17))) + if (odm_get_bb_reg(dm, REG_FPGA0_PSD_REPORT, BIT(17))) break; } /* 4 Get NHM Statistics */ - if (p_acs->acs_step == 1) { + if (acs->acs_step == 1) { + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11N); - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); + acs->nhm_cnt[idx][9] = (value32 & MASKBYTE1) >> 8; + acs->nhm_cnt[idx][8] = (value32 & MASKBYTE0); - p_acs->nhm_cnt[idx][9] = (value32 & MASKBYTE1) >> 8; - p_acs->nhm_cnt[idx][8] = (value32 & MASKBYTE0); + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11N); /* ODM_REG_NHM_CNT3_TO_CNT0_11N */ - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11N); /* ODM_REG_NHM_CNT3_TO_CNT0_11N */ + acs->nhm_cnt[idx][7] = (value32 & MASKBYTE3) >> 24; + acs->nhm_cnt[idx][6] = (value32 & MASKBYTE2) >> 16; + acs->nhm_cnt[idx][5] = (value32 & MASKBYTE1) >> 8; - p_acs->nhm_cnt[idx][7] = (value32 & MASKBYTE3) >> 24; - p_acs->nhm_cnt[idx][6] = (value32 & MASKBYTE2) >> 16; - p_acs->nhm_cnt[idx][5] = (value32 & MASKBYTE1) >> 8; + } else if (acs->acs_step == 2) { + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11N); /* ODM_REG_NHM_CNT3_TO_CNT0_11N */ - } else if (p_acs->acs_step == 2) { - - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11N); /* ODM_REG_NHM_CNT3_TO_CNT0_11N */ - - p_acs->nhm_cnt[idx][4] = odm_read_1byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); - p_acs->nhm_cnt[idx][3] = (value32 & MASKBYTE3) >> 24; - p_acs->nhm_cnt[idx][2] = (value32 & MASKBYTE2) >> 16; - p_acs->nhm_cnt[idx][1] = (value32 & MASKBYTE1) >> 8; - p_acs->nhm_cnt[idx][0] = (value32 & MASKBYTE0); + acs->nhm_cnt[idx][4] = odm_read_1byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11N); + acs->nhm_cnt[idx][3] = (value32 & MASKBYTE3) >> 24; + acs->nhm_cnt[idx][2] = (value32 & MASKBYTE2) >> 16; + acs->nhm_cnt[idx][1] = (value32 & MASKBYTE1) >> 8; + acs->nhm_cnt[idx][0] = (value32 & MASKBYTE0); } - } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { /* 4 Check if NHM result is ready */ for (i = 0; i < 20; i++) { - ODM_delay_ms(1); - if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(16))) + if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC, BIT(16))) break; } - if (p_acs->acs_step == 1) { - - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); + if (acs->acs_step == 1) { + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); - p_acs->nhm_cnt[idx][9] = (value32 & MASKBYTE1) >> 8; - p_acs->nhm_cnt[idx][8] = (value32 & MASKBYTE0); + acs->nhm_cnt[idx][9] = (value32 & MASKBYTE1) >> 8; + acs->nhm_cnt[idx][8] = (value32 & MASKBYTE0); - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11AC); /* ODM_REG_NHM_CNT3_TO_CNT0_11AC */ + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11AC); /* ODM_REG_NHM_CNT3_TO_CNT0_11AC */ - p_acs->nhm_cnt[idx][7] = (value32 & MASKBYTE3) >> 24; - p_acs->nhm_cnt[idx][6] = (value32 & MASKBYTE2) >> 16; - p_acs->nhm_cnt[idx][5] = (value32 & MASKBYTE1) >> 8; + acs->nhm_cnt[idx][7] = (value32 & MASKBYTE3) >> 24; + acs->nhm_cnt[idx][6] = (value32 & MASKBYTE2) >> 16; + acs->nhm_cnt[idx][5] = (value32 & MASKBYTE1) >> 8; - } else if (p_acs->acs_step == 2) { + } else if (acs->acs_step == 2) { + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11AC); /* ODM_REG_NHM_CNT3_TO_CNT0_11AC */ - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11AC); /* ODM_REG_NHM_CNT3_TO_CNT0_11AC */ - - p_acs->nhm_cnt[idx][4] = odm_read_1byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); - p_acs->nhm_cnt[idx][3] = (value32 & MASKBYTE3) >> 24; - p_acs->nhm_cnt[idx][2] = (value32 & MASKBYTE2) >> 16; - p_acs->nhm_cnt[idx][1] = (value32 & MASKBYTE1) >> 8; - p_acs->nhm_cnt[idx][0] = (value32 & MASKBYTE0); + acs->nhm_cnt[idx][4] = odm_read_1byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); + acs->nhm_cnt[idx][3] = (value32 & MASKBYTE3) >> 24; + acs->nhm_cnt[idx][2] = (value32 & MASKBYTE2) >> 16; + acs->nhm_cnt[idx][1] = (value32 & MASKBYTE1) >> 8; + acs->nhm_cnt[idx][0] = (value32 & MASKBYTE0); } } @@ -400,14 +408,14 @@ phydm_get_nhm_statistics_ap( /* #define ACS_DEBUG_INFO */ /* acs debug default off */ #if 0 int phydm_AutoChannelSelectAP( - void *p_dm_void, + void *dm_void, u32 ACS_Type, /* 0: RXCount_Type, 1:NHM_Type */ u32 available_chnl_num /* amount of all channels */ ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ACS_ *p_acs = &p_dm_odm->dm_acs; - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct acs_info *acs = &dm->dm_acs; + struct rtl8192cd_priv *priv = dm->priv; static u32 score2G[MAX_2G_CHANNEL_NUM], score5G[MAX_5G_CHANNEL_NUM]; u32 score[MAX_BSS_NUM], use_nhm = 0; @@ -487,7 +495,7 @@ int phydm_AutoChannelSelectAP( #endif #if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_WLAN_HAL_8192EE) - if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E) && priv->pmib->dot11RFEntry.acs_type) { + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E) && priv->pmib->dot11RFEntry.acs_type) { u32 tmp_score[MAX_BSS_NUM]; memcpy(tmp_score, score, sizeof(score)); if (find_clean_channel(priv, ch_begin, ch_end, tmp_score)) { @@ -537,7 +545,7 @@ int phydm_AutoChannelSelectAP( traffic_check = 1; #ifdef RTK_5G_SUPPORT - if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) + if (*dm->band_type == ODM_BAND_2_4G) #endif { if ((int)(y - 4) >= (int)ch_begin) @@ -581,7 +589,7 @@ int phydm_AutoChannelSelectAP( traffic_check = 1; #ifdef RTK_5G_SUPPORT - if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) + if (*dm->band_type == ODM_BAND_2_4G) #endif { if ((int)(y - 6) >= (int)ch_begin) @@ -887,8 +895,8 @@ int phydm_AutoChannelSelectAP( #endif - if ((*p_dm_odm->p_band_type == ODM_BAND_5G) - && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) { + if ((*dm->band_type == ODM_BAND_5G) + && (priv->pmib->dot11nConfigEntry.dot11nUse40M == CHANNEL_WIDTH_80)) { for (i = 0; i < priv->available_chnl_num; i++) { if (is80MChannel(priv->available_chnl, priv->available_chnl_num, priv->available_chnl[i])) { tmpScore = 0; @@ -917,7 +925,7 @@ int phydm_AutoChannelSelectAP( } if (minScore == 0xffffffff) { /* there is no 80M channels */ - priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; + priv->pshare->is_40m_bw = CHANNEL_WIDTH_20; for (i = 0; i < priv->available_chnl_num; i++) { if (score[i] < minScore) { minScore = score[i]; @@ -925,8 +933,8 @@ int phydm_AutoChannelSelectAP( } } } - } else if ((*p_dm_odm->p_band_type == ODM_BAND_5G) - && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40)) { + } else if ((*dm->band_type == ODM_BAND_5G) + && (priv->pmib->dot11nConfigEntry.dot11nUse40M == CHANNEL_WIDTH_40)) { for (i = 0; i < priv->available_chnl_num; i++) { if (is40MChannel(priv->available_chnl, priv->available_chnl_num, priv->available_chnl[i])) { tmpScore = 0; @@ -955,7 +963,7 @@ int phydm_AutoChannelSelectAP( } if (minScore == 0xffffffff) { /* there is no 40M channels */ - priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; + priv->pshare->is_40m_bw = CHANNEL_WIDTH_20; for (i = 0; i < priv->available_chnl_num; i++) { if (score[i] < minScore) { minScore = score[i]; @@ -963,8 +971,8 @@ int phydm_AutoChannelSelectAP( } } } - } else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) - && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) + } else if ((*dm->band_type == ODM_BAND_2_4G) + && (priv->pmib->dot11nConfigEntry.dot11nUse40M == CHANNEL_WIDTH_40) && (priv->available_chnl_num >= 8)) { u32 groupScore[14]; @@ -1018,7 +1026,7 @@ int phydm_AutoChannelSelectAP( } if (IS_A_CUT_8881A(priv) && - (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) { + (priv->pmib->dot11nConfigEntry.dot11nUse40M == CHANNEL_WIDTH_80)) { if ((priv->available_chnl[idx] == 36) || (priv->available_chnl[idx] == 52) || (priv->available_chnl[idx] == 100) || @@ -1056,20 +1064,18 @@ int phydm_AutoChannelSelectAP( #if 0 /* Check if selected channel available for 80M/40M BW or NOT ? */ - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { - if (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80) { + if (*dm->band_type == ODM_BAND_5G) { + if (priv->pmib->dot11nConfigEntry.dot11nUse40M == CHANNEL_WIDTH_80) { if (!is80MChannel(priv->available_chnl, priv->available_chnl_num, minChan)) { - - /* priv->pmib->dot11n_config_entry.dot11nUse40M = HT_CHANNEL_WIDTH_20_40; */ - priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20_40; + /* priv->pmib->dot11n_config_entry.dot11nUse40M = CHANNEL_WIDTH_40; */ + priv->pshare->is_40m_bw = CHANNEL_WIDTH_40; } } - if (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) { + if (priv->pmib->dot11nConfigEntry.dot11nUse40M == CHANNEL_WIDTH_40) { if (!is40MChannel(priv->available_chnl, priv->available_chnl_num, minChan)) { - - /* priv->pmib->dot11n_config_entry.dot11nUse40M = HT_CHANNEL_WIDTH_20; */ - priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; + /* priv->pmib->dot11n_config_entry.dot11nUse40M = CHANNEL_WIDTH_20; */ + priv->pshare->is_40m_bw = CHANNEL_WIDTH_20; } } } @@ -1082,9 +1088,8 @@ int phydm_AutoChannelSelectAP( /* auto adjust contro-sideband */ if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && (priv->pshare->is_40m_bw == 1 || priv->pshare->is_40m_bw == 2)) { - #ifdef RTK_5G_SUPPORT - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + if (*dm->band_type == ODM_BAND_5G) { if ((minChan > 144) ? ((minChan - 1) % 8) : (minChan % 8)) { GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; diff --git a/hal/phydm/phydm_acs.h b/hal/phydm/phydm_acs.h index e54d686..61bdecc 100644 --- a/hal/phydm/phydm_acs.h +++ b/hal/phydm/phydm_acs.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __PHYDMACS_H__ @@ -27,7 +37,7 @@ #define RESTORE_DEFAULT_NHM_SETTING 1 #define ACS_NHM_SETTING 2 -struct _ACS_ { +struct acs_info { boolean is_force_acs_result; u8 clean_channel_2g; u8 clean_channel_5g; @@ -59,38 +69,43 @@ struct _ACS_ { void odm_auto_channel_select_init( - void *p_dm_void + void *dm_void ); void odm_auto_channel_select_reset( - void *p_dm_void + void *dm_void ); void odm_auto_channel_select( - void *p_dm_void, + void *dm_void, u8 channel ); u8 odm_get_auto_channel_select_result( - void *p_dm_void, + void *dm_void, u8 band ); +boolean +phydm_acs_check( + void *dm_void +); + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) void phydm_auto_channel_select_setting_ap( - void *p_dm_void, + void *dm_void, u32 setting, /* 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING */ u32 acs_step ); void phydm_get_nhm_statistics_ap( - void *p_dm_void, + void *dm_void, u32 idx, /* @ 2G, Real channel number = idx+1 */ u32 acs_step ); diff --git a/hal/phydm/phydm_adaptivity.c b/hal/phydm/phydm_adaptivity.c index 8cf5e5c..fafe2d5 100644 --- a/hal/phydm/phydm_adaptivity.c +++ b/hal/phydm/phydm_adaptivity.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -25,97 +35,116 @@ #endif #endif +void +phydm_dig_up_bound_lmt_en( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); + + if (!(dm->support_ability & ODM_BB_ADAPTIVITY) || + (!dm->adaptivity_flag) || + (!dm->is_linked) || + (!dm->adaptivity_enable) + ) { + adaptivity->igi_up_bound_lmt_cnt = 0; + adaptivity->igi_lmt_en = false; + return; + } + + if (dm->total_tp > 1) { + adaptivity->igi_lmt_en = true; + adaptivity->igi_up_bound_lmt_cnt = adaptivity->igi_up_bound_lmt_val; + PHYDM_DBG(dm, DBG_ADPTVTY, "TP >1, Start limit IGI upper bound\n"); + } else { + if (adaptivity->igi_up_bound_lmt_cnt == 0) + adaptivity->igi_lmt_en = false; + else + adaptivity->igi_up_bound_lmt_cnt--; + } + + PHYDM_DBG(dm, DBG_ADPTVTY, "IGI_lmt_cnt = %d\n", adaptivity->igi_up_bound_lmt_cnt); +} void phydm_check_adaptivity( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); - if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (p_dm_odm->ap_total_num > adaptivity->ap_num_th) { - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", adaptivity->ap_num_th)); - } else { -#endif - if (adaptivity->dynamic_link_adaptivity || adaptivity->acs_for_adaptivity) { - if (p_dm_odm->is_linked && adaptivity->is_check == false) { - phydm_nhm_counter_statistics(p_dm_odm); - phydm_check_environment(p_dm_odm); - } else if (!p_dm_odm->is_linked) - adaptivity->is_check = false; - } else { - p_dm_odm->adaptivity_enable = true; - - if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) - p_dm_odm->adaptivity_flag = false; - else - p_dm_odm->adaptivity_flag = true; - } + if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) { + dm->adaptivity_enable = false; + return; + } + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - } -#endif - } else { - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; + if (dm->ap_total_num > adaptivity->ap_num_th) { + dm->adaptivity_enable = false; + PHYDM_DBG(dm, DBG_ADPTVTY, "AP total num > %d!!, disable adaptivity\n", adaptivity->ap_num_th); + return; + } +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (adaptivity->dynamic_link_adaptivity) { + if (dm->is_linked && adaptivity->is_check == false) { + phydm_check_environment(dm); + } else if (!dm->is_linked) + adaptivity->is_check = false; + + return; } +#endif + + dm->adaptivity_enable = true; } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) boolean phydm_check_channel_plan( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &(p_adapter->MgntInfo); - - if (p_mgnt_info->RegEnableAdaptivity == 2) { - if (p_dm_odm->carrier_sense_enable == false) { /*check domain Code for adaptivity or CarrierSense*/ - if ((*p_dm_odm->p_band_type == ODM_BAND_5G) && - !(p_dm_odm->odm_regulation_5g == REGULATION_ETSI || p_dm_odm->odm_regulation_5g == REGULATION_WW)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity skip 5G domain code : %d\n", p_dm_odm->odm_regulation_5g)); - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; + + if (mgnt_info->RegEnableAdaptivity == 2) { + if (dm->carrier_sense_enable == false) { /*check domain Code for adaptivity or CarrierSense*/ + if ((*dm->band_type == ODM_BAND_5G) && + !(dm->odm_regulation_5g == REGULATION_ETSI || dm->odm_regulation_5g == REGULATION_WW)) { + PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity skip 5G domain code : %d\n", dm->odm_regulation_5g); + dm->adaptivity_enable = false; return true; - } else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) && - !(p_dm_odm->odm_regulation_2_4g == REGULATION_ETSI || p_dm_odm->odm_regulation_2_4g == REGULATION_WW)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity skip 2.4G domain code : %d\n", p_dm_odm->odm_regulation_2_4g)); - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; + } else if ((*dm->band_type == ODM_BAND_2_4G) && + !(dm->odm_regulation_2_4g == REGULATION_ETSI || dm->odm_regulation_2_4g == REGULATION_WW)) { + PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity skip 2.4G domain code : %d\n", dm->odm_regulation_2_4g); + dm->adaptivity_enable = false; return true; - } else if ((*p_dm_odm->p_band_type != ODM_BAND_2_4G) && (*p_dm_odm->p_band_type != ODM_BAND_5G)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity neither 2G nor 5G band, return\n")); - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; + } else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) { + PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity neither 2G nor 5G band, return\n"); + dm->adaptivity_enable = false; return true; } } else { - if ((*p_dm_odm->p_band_type == ODM_BAND_5G) && - !(p_dm_odm->odm_regulation_5g == REGULATION_MKK || p_dm_odm->odm_regulation_5g == REGULATION_WW)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", p_dm_odm->odm_regulation_5g)); - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; + if ((*dm->band_type == ODM_BAND_5G) && + !(dm->odm_regulation_5g == REGULATION_MKK || dm->odm_regulation_5g == REGULATION_WW)) { + PHYDM_DBG(dm, DBG_ADPTVTY, "CarrierSense skip 5G domain code : %d\n", dm->odm_regulation_5g); + dm->adaptivity_enable = false; return true; } - else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) && - !(p_dm_odm->odm_regulation_2_4g == REGULATION_MKK || p_dm_odm->odm_regulation_2_4g == REGULATION_WW)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", p_dm_odm->odm_regulation_2_4g)); - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; + else if ((*dm->band_type == ODM_BAND_2_4G) && + !(dm->odm_regulation_2_4g == REGULATION_MKK || dm->odm_regulation_2_4g == REGULATION_WW)) { + PHYDM_DBG(dm, DBG_ADPTVTY, "CarrierSense skip 2.4G domain code : %d\n", dm->odm_regulation_2_4g); + dm->adaptivity_enable = false; return true; - } else if ((*p_dm_odm->p_band_type != ODM_BAND_2_4G) && (*p_dm_odm->p_band_type != ODM_BAND_5G)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n")); - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; + } else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) { + PHYDM_DBG(dm, DBG_ADPTVTY, "CarrierSense neither 2G nor 5G band, return\n"); + dm->adaptivity_enable = false; return true; } } @@ -128,124 +157,124 @@ phydm_check_channel_plan( void phydm_set_edcca_threshold( - void *p_dm_void, + void *dm_void, s8 H2L, s8 L2H ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)L2H | (u8)H2L << 16)); + if (dm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)L2H | (u8)H2L << 16)); #if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)L2H | (u8)H2L << 8)); + else if (dm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)L2H | (u8)H2L << 8)); #endif } void phydm_set_lna( - void *p_dm_void, + void *dm_void, enum phydm_set_lna type ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E)) { + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E)) { if (type == phydm_disable_lna) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - if (p_dm_odm->rf_type > ODM_1T1R) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0000f); + odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/ + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0); + if (dm->rf_type > RF_1T1R) { + odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0xfffff, 0x18000); + odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x0000f); + odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0x37f82); + odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x0); } } else if (type == phydm_enable_lna) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - if (p_dm_odm->rf_type > ODM_1T1R) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0000f); + odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/ + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0); + if (dm->rf_type > RF_1T1R) { + odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0xfffff, 0x18000); + odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x0000f); + odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0x77f82); + odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x0); } } - } else if (p_dm_odm->support_ic_type & ODM_RTL8723B) { + } else if (dm->support_ic_type & ODM_RTL8723B) { if (type == phydm_disable_lna) { /*S0*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0001f); + odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/ + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0); /*S1*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xed, 0x00020, 0x1); + odm_set_rf_reg(dm, RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/ + odm_set_rf_reg(dm, RF_PATH_A, 0xed, 0x00020, 0x0); } else if (type == phydm_enable_lna) { /*S0*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0001f); + odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/ + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0); /*S1*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xed, 0x00020, 0x1); + odm_set_rf_reg(dm, RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/ + odm_set_rf_reg(dm, RF_PATH_A, 0xed, 0x00020, 0x0); } - } else if (p_dm_odm->support_ic_type & ODM_RTL8812) { + } else if (dm->support_ic_type & ODM_RTL8812) { if (type == phydm_disable_lna) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - if (p_dm_odm->rf_type > ODM_1T1R) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); + odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0); + if (dm->rf_type > RF_1T1R) { + odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); + odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ + odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x0); } } else if (type == phydm_enable_lna) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - if (p_dm_odm->rf_type > ODM_1T1R) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); + odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0); + if (dm->rf_type > RF_1T1R) { + odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); + odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ + odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x0); } } - } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { + } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { if (type == phydm_disable_lna) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0002f); + odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/ + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0); } else if (type == phydm_enable_lna) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0002f); + odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/ + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0); } } } @@ -254,28 +283,28 @@ phydm_set_lna( void phydm_set_trx_mux( - void *p_dm_void, + void *dm_void, enum phydm_trx_mux_type tx_mode, enum phydm_trx_mux_type rx_mode ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(3) | BIT(2) | BIT(1), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(22) | BIT(21) | BIT(20), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ - if (p_dm_odm->rf_type > ODM_1T1R) { - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(3) | BIT(2) | BIT(1), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(22) | BIT(21) | BIT(20), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(3) | BIT(2) | BIT(1), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ + odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(22) | BIT(21) | BIT(20), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ + if (dm->rf_type > RF_1T1R) { + odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(3) | BIT(2) | BIT(1), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ + odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(22) | BIT(21) | BIT(20), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ } } #if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ - if (p_dm_odm->rf_type > ODM_1T1R) { - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC_B, BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC_B, BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ + else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ + if (dm->rf_type > RF_1T1R) { + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC_B, BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC_B, BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ } } #endif @@ -284,134 +313,71 @@ phydm_set_trx_mux( void phydm_mac_edcca_state( - void *p_dm_void, + void *dm_void, enum phydm_mac_edcca_type state ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (state == phydm_ignore_edcca) { - odm_set_mac_reg(p_dm_odm, REG_TX_PTCL_CTRL, BIT(15), 1); /*ignore EDCCA reg520[15]=1*/ - /* odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 0); */ /*reg524[11]=0*/ + odm_set_mac_reg(dm, REG_TX_PTCL_CTRL, BIT(15), 1); /*ignore EDCCA reg520[15]=1*/ + /* odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 0); */ /*reg524[11]=0*/ } else { /*don't set MAC ignore EDCCA signal*/ - odm_set_mac_reg(p_dm_odm, REG_TX_PTCL_CTRL, BIT(15), 0); /*don't ignore EDCCA reg520[15]=0*/ - /* odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 1); */ /*reg524[11]=1 */ - } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable state = %d\n", state)); - -} - -void -phydm_check_environment( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); - boolean is_clean_environment = false; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct rtl8192cd_priv *priv = p_dm_odm->priv; -#endif - - if (adaptivity->is_first_link == true) { - if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) - p_dm_odm->adaptivity_flag = false; - else - p_dm_odm->adaptivity_flag = true; - - adaptivity->is_first_link = false; - return; - } - - if (adaptivity->nhm_wait < 3) { /*Start enter NHM after 4 nhm_wait*/ - adaptivity->nhm_wait++; - phydm_nhm_counter_statistics(p_dm_odm); - return; - } - - phydm_nhm_counter_statistics(p_dm_odm); - is_clean_environment = phydm_cal_nhm_cnt(p_dm_odm); - - if (is_clean_environment == true) { - p_dm_odm->th_l2h_ini = adaptivity->th_l2h_ini_backup; /*adaptivity mode*/ - p_dm_odm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup; - - p_dm_odm->adaptivity_enable = true; - - if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) - p_dm_odm->adaptivity_flag = false; - else - p_dm_odm->adaptivity_flag = true; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - priv->pshare->rf_ft_var.is_clean_environment = true; -#endif - } else { - if (!adaptivity->acs_for_adaptivity) { - p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2; /*mode2*/ - p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2; - - p_dm_odm->adaptivity_flag = false; - p_dm_odm->adaptivity_enable = false; - } -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - priv->pshare->rf_ft_var.is_clean_environment = false; -#endif + odm_set_mac_reg(dm, REG_TX_PTCL_CTRL, BIT(15), 0); /*don't ignore EDCCA reg520[15]=0*/ + /* odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1); */ /*reg524[11]=1 */ } - - adaptivity->nhm_wait = 0; - adaptivity->is_first_link = true; - adaptivity->is_check = true; + PHYDM_DBG(dm, DBG_ADPTVTY, "EDCCA enable state = %d\n", state); } void phydm_search_pwdb_lower_bound( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); u32 value32 = 0, reg_value32 = 0; u8 cnt, try_count = 0; u8 tx_edcca1 = 0; boolean is_adjust = true; s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32; s8 diff; - u8 IGI = adaptivity->igi_base + 30 + (u8)p_dm_odm->th_l2h_ini - (u8)p_dm_odm->th_edcca_hl_diff; + u8 IGI = adaptivity->igi_base + 30 + (u8)dm->th_l2h_ini - (u8)dm->th_edcca_hl_diff; - if (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) - phydm_set_lna(p_dm_odm, phydm_disable_lna); + if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) + phydm_set_lna(dm, phydm_disable_lna); diff = igi_target - (s8)IGI; - th_l2h_dmc = p_dm_odm->th_l2h_ini + diff; + th_l2h_dmc = dm->th_l2h_ini + diff; if (th_l2h_dmc > 10) th_l2h_dmc = 10; - th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; - phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff; + phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc); ODM_delay_ms(30); while (is_adjust) { - - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/ - reg_value32 = phydm_get_bb_dbg_port_value(p_dm_odm); + /*check CCA status*/ + if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/ + reg_value32 = phydm_get_bb_dbg_port_value(dm); while (reg_value32 & BIT(3) && try_count < 3) { ODM_delay_ms(3); try_count = try_count + 1; - reg_value32 = phydm_get_bb_dbg_port_value(p_dm_odm); + reg_value32 = phydm_get_bb_dbg_port_value(dm); } - phydm_release_bb_dbg_port(p_dm_odm); + phydm_release_bb_dbg_port(dm); try_count = 0; } + /*count EDCCA signal = 1 times*/ for (cnt = 0; cnt < 20; cnt++) { - - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) { - value32 = phydm_get_bb_dbg_port_value(p_dm_odm); - phydm_release_bb_dbg_port(p_dm_odm); + if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) { + value32 = phydm_get_bb_dbg_port_value(dm); + phydm_release_bb_dbg_port(dm); } - if (value32 & BIT(30) && (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))) + if (value32 & BIT(30) && (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))) tx_edcca1 = tx_edcca1 + 1; else if (value32 & BIT(29)) tx_edcca1 = tx_edcca1 + 1; @@ -423,8 +389,8 @@ phydm_search_pwdb_lower_bound( if (th_l2h_dmc > 10) th_l2h_dmc = 10; - th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; - phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff; + phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc); tx_edcca1 = 0; if (th_l2h_dmc == 10) is_adjust = false; @@ -434,31 +400,30 @@ phydm_search_pwdb_lower_bound( } - p_dm_odm->adaptivity_igi_upper = IGI - p_dm_odm->dc_backoff; - adaptivity->h2l_lb = th_h2l_dmc + p_dm_odm->dc_backoff; - adaptivity->l2h_lb = th_l2h_dmc + p_dm_odm->dc_backoff; + adaptivity->adapt_igi_up = IGI - dm->dc_backoff; + adaptivity->h2l_lb = th_h2l_dmc + dm->dc_backoff; + adaptivity->l2h_lb = th_l2h_dmc + dm->dc_backoff; - if (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) - phydm_set_lna(p_dm_odm, phydm_enable_lna); + if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) + phydm_set_lna(dm, phydm_enable_lna); - phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f); /*resume to no link state*/ + phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/ } boolean phydm_re_search_condition( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 adaptivity_igi_upper; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); + u8 adaptivity_igi_upper = adaptivity->adapt_igi_up + dm->dc_backoff; /*s8 TH_L2H_dmc, IGI_target = 0x32;*/ /*s8 diff;*/ - adaptivity_igi_upper = p_dm_odm->adaptivity_igi_upper + p_dm_odm->dc_backoff; - /*TH_L2H_dmc = 10;*/ - /*diff = TH_L2H_dmc - p_dm_odm->TH_L2H_ini;*/ + /*diff = TH_L2H_dmc - dm->TH_L2H_ini;*/ /*lowest_IGI_upper = IGI_target - diff;*/ /*if ((adaptivity_igi_upper - lowest_IGI_upper) <= 5)*/ @@ -470,21 +435,21 @@ phydm_re_search_condition( void phydm_adaptivity_info_init( - void *p_dm_void, - enum phydm_adapinfo_e cmn_info, + void *dm_void, + enum phydm_adapinfo cmn_info, u32 value ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); switch (cmn_info) { case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE: - p_dm_odm->carrier_sense_enable = (boolean)value; + dm->carrier_sense_enable = (boolean)value; break; case PHYDM_ADAPINFO_DCBACKOFF: - p_dm_odm->dc_backoff = (u8)value; + dm->dc_backoff = (u8)value; break; case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY: @@ -492,11 +457,11 @@ phydm_adaptivity_info_init( break; case PHYDM_ADAPINFO_TH_L2H_INI: - p_dm_odm->th_l2h_ini = (s8)value; + dm->th_l2h_ini = (s8)value; break; case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF: - p_dm_odm->th_edcca_hl_diff = (s8)value; + dm->th_edcca_hl_diff = (s8)value; break; case PHYDM_ADAPINFO_AP_NUM_TH: @@ -510,223 +475,223 @@ phydm_adaptivity_info_init( } - - void phydm_adaptivity_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); s8 igi_target = 0x32; - /*struct _dynamic_initial_gain_threshold_* p_dm_dig_table = &p_dm_odm->dm_dig_table;*/ + /*struct phydm_dig_struct* dig_t = &dm->dm_dig_table;*/ #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) - if (p_dm_odm->carrier_sense_enable == false) { - if (p_dm_odm->th_l2h_ini == 0) - phydm_set_l2h_th_ini(p_dm_odm); + if (dm->carrier_sense_enable == false) { + if (dm->th_l2h_ini == 0) + phydm_set_l2h_th_ini(dm); } else - p_dm_odm->th_l2h_ini = 0xa; + dm->th_l2h_ini = 0xa; - if (p_dm_odm->th_edcca_hl_diff == 0) - p_dm_odm->th_edcca_hl_diff = 7; + if (dm->th_edcca_hl_diff == 0) + dm->th_edcca_hl_diff = 7; #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - if (p_dm_odm->wifi_test == true || *(p_dm_odm->p_mp_mode) == true) + if (dm->wifi_test == true || *dm->mp_mode == true) #else - if ((p_dm_odm->wifi_test & RT_WIFI_LOGO) == true) + if ((dm->wifi_test & RT_WIFI_LOGO) == true) #endif - p_dm_odm->edcca_enable = false; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/ + dm->edcca_enable = false; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/ else - p_dm_odm->edcca_enable = true; + dm->edcca_enable = true; #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; - if (p_dm_odm->carrier_sense_enable) { - p_dm_odm->th_l2h_ini = 0xa; - p_dm_odm->th_edcca_hl_diff = 7; + if (dm->carrier_sense_enable) { + dm->th_l2h_ini = 0xa; + dm->th_edcca_hl_diff = 7; } else { - p_dm_odm->th_l2h_ini = p_dm_odm->TH_L2H_default; /*set by mib*/ - p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_default; + dm->th_l2h_ini = dm->TH_L2H_default; /*set by mib*/ + dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_default; } - if (priv->pshare->rf_ft_var.adaptivity_enable == 3) - adaptivity->acs_for_adaptivity = true; - else - adaptivity->acs_for_adaptivity = false; - if (priv->pshare->rf_ft_var.adaptivity_enable == 2) adaptivity->dynamic_link_adaptivity = true; else adaptivity->dynamic_link_adaptivity = false; - priv->pshare->rf_ft_var.is_clean_environment = false; - #endif - p_dm_odm->adaptivity_igi_upper = 0; - p_dm_odm->adaptivity_enable = false; /*use this flag to decide enable or disable*/ + adaptivity->adapt_igi_up = 0; + dm->adaptivity_enable = false; /*use this flag to decide enable or disable*/ - p_dm_odm->th_l2h_ini_mode2 = 20; - p_dm_odm->th_edcca_hl_diff_mode2 = 8; + dm->th_l2h_ini_mode2 = 20; + dm->th_edcca_hl_diff_mode2 = 8; adaptivity->debug_mode = false; - adaptivity->th_l2h_ini_backup = p_dm_odm->th_l2h_ini; - adaptivity->th_edcca_hl_diff_backup = p_dm_odm->th_edcca_hl_diff; + adaptivity->th_l2h_ini_backup = dm->th_l2h_ini; + adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff; adaptivity->igi_base = 0x32; adaptivity->igi_target = 0x1c; adaptivity->h2l_lb = 0; adaptivity->l2h_lb = 0; - adaptivity->nhm_wait = 0; adaptivity->is_check = false; - adaptivity->is_first_link = true; adaptivity->adajust_igi_level = 0; adaptivity->is_stop_edcca = false; adaptivity->backup_h2l = 0; adaptivity->backup_l2h = 0; - adaptivity->adaptivity_dbg_port = (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) ? 0x208 : 0x209; - - phydm_mac_edcca_state(p_dm_odm, phydm_dont_ignore_edcca); - - if (p_dm_odm->support_ic_type & ODM_IC_11N_GAIN_IDX_EDCCA) { - /*odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT(12) | BIT(11) | BIT(10), 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ - if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1); /*set to page B1*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DCNF_97F, BIT(27) | BIT(26), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0); -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - if (priv->pshare->rf_ft_var.adaptivity_enable == 1) - odm_set_bb_reg(p_dm_odm, 0xce8, BIT(13), 0x1); /*0: mean, 1:max pwdB*/ -#endif + adaptivity->adaptivity_dbg_port = (dm->support_ic_type & ODM_IC_11N_SERIES) ? 0x208 : 0x209; + + phydm_mac_edcca_state(dm, phydm_dont_ignore_edcca); + + if (dm->support_ic_type & ODM_IC_11N_GAIN_IDX_EDCCA) { + /*odm_set_bb_reg(dm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT(12) | BIT(11) | BIT(10), 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ + if (dm->support_ic_type & ODM_RTL8197F) { + odm_set_bb_reg(dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1); /*set to page B1*/ + odm_set_bb_reg(dm, ODM_REG_EDCCA_DCNF_97F, BIT(27) | BIT(26), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + odm_set_bb_reg(dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0); } else - odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DCNF_11N, BIT(21) | BIT(20), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + odm_set_bb_reg(dm, ODM_REG_EDCCA_DCNF_11N, BIT(21) | BIT(20), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ } #if (RTL8195A_SUPPORT == 0) - if (p_dm_odm->support_ic_type & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/ - /*odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DOWN_OPT, BIT(30) | BIT(29) | BIT(28), 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT(29) | BIT(28), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + if (dm->support_ic_type & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/ + /*odm_set_bb_reg(dm, ODM_REG_EDCCA_DOWN_OPT, BIT(30) | BIT(29) | BIT(28), 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ + odm_set_bb_reg(dm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT(29) | BIT(28), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ } - if (!(p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) { - phydm_search_pwdb_lower_bound(p_dm_odm); - if (phydm_re_search_condition(p_dm_odm)) - phydm_search_pwdb_lower_bound(p_dm_odm); + if (!(dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) { + phydm_search_pwdb_lower_bound(dm); + if (phydm_re_search_condition(dm)) + phydm_search_pwdb_lower_bound(dm); } else - phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f); /*resume to no link state*/ + phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/ #endif /*forgetting factor setting*/ - phydm_set_forgetting_factor(p_dm_odm); + phydm_set_forgetting_factor(dm); - /*we need to consider PwdB upper bound for 8814 later IC*/ - adaptivity->adajust_igi_level = (u8)((p_dm_odm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/ + /*pwdb mode setting with 0: mean, 1:max*/ + phydm_set_pwdb_mode(dm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("th_l2h_ini = 0x%x, th_edcca_hl_diff = 0x%x, adaptivity->adajust_igi_level = 0x%x\n", p_dm_odm->th_l2h_ini, p_dm_odm->th_edcca_hl_diff, adaptivity->adajust_igi_level)); + /*we need to consider PwdB upper bound for 8814 later IC*/ + adaptivity->adajust_igi_level = (u8)((dm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/ /*Check this later on Windows*/ - /*phydm_set_edcca_threshold_api(p_dm_odm, p_dm_dig_table->cur_ig_value);*/ + /*phydm_set_edcca_threshold_api(dm, dig_t->cur_ig_value);*/ + + dm->adaptivity_flag = (dm->support_ic_type & ODM_IC_GAIN_IDX_EDCCA) ? false : true; + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + adaptivity->igi_up_bound_lmt_val = 180; +#else + adaptivity->igi_up_bound_lmt_val = 90; +#endif + adaptivity->igi_up_bound_lmt_cnt = 0; + adaptivity->igi_lmt_en = false; } void phydm_adaptivity( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 igi = p_dm_dig_table->cur_ig_value; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 igi = dig_t->cur_ig_value; s8 th_l2h_dmc, th_h2l_dmc; s8 diff = 0, igi_target = 0x32; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - boolean is_fw_current_in_ps_mode = false; + PADAPTER adapter = (PADAPTER)dm->adapter; + u32 is_fw_current_in_ps_mode = false; u8 disable_ap_adapt_setting; - p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_FW_PSMODE_STATUS, (u8 *)(&is_fw_current_in_ps_mode)); + adapter->HalFunc.GetHwRegHandler(adapter, HW_VAR_FW_PSMODE_STATUS, (u8 *)(&is_fw_current_in_ps_mode)); /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/ if (is_fw_current_in_ps_mode) return; #endif - if ((p_dm_odm->edcca_enable == false) || (adaptivity->is_stop_edcca == true)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n")); + if (!dm->edcca_enable || adaptivity->is_stop_edcca) { + PHYDM_DBG(dm, DBG_ADPTVTY, "Disable EDCCA!!!\n"); return; } - if ((!(p_dm_odm->support_ability & ODM_BB_ADAPTIVITY)) && adaptivity->debug_mode == false) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n")); - p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2; - p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2; + phydm_check_adaptivity(dm); /*Check adaptivity enable*/ + phydm_dig_up_bound_lmt_en(dm); + + if ((!(dm->support_ability & ODM_BB_ADAPTIVITY)) && adaptivity->debug_mode == false) { + PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity disable, enable EDCCA mode!!!\n"); + dm->th_l2h_ini = dm->th_l2h_ini_mode2; + dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_mode2; } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) else if (adaptivity->debug_mode == false) { disable_ap_adapt_setting = false; - if (p_dm_odm->p_soft_ap_mode != NULL) { - if (*(p_dm_odm->p_soft_ap_mode) != 0 && (p_dm_odm->soft_ap_special_setting & BIT(0))) + if (dm->soft_ap_mode != NULL) { + if (*dm->soft_ap_mode != 0 && (dm->soft_ap_special_setting & BIT(0))) disable_ap_adapt_setting = true; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("p_dm_odm->soft_ap_special_setting = %x, *(p_dm_odm->p_soft_ap_mode) = %d, disable_ap_adapt_setting = %d\n", p_dm_odm->soft_ap_special_setting, *(p_dm_odm->p_soft_ap_mode), disable_ap_adapt_setting)); + PHYDM_DBG(dm, DBG_ADPTVTY, "soft_ap_setting = %x, soft_ap = %d, dis_ap_adapt = %d\n", + dm->soft_ap_special_setting, *dm->soft_ap_mode, disable_ap_adapt_setting); } - if (phydm_check_channel_plan(p_dm_odm) || (p_dm_odm->ap_total_num > adaptivity->ap_num_th) || disable_ap_adapt_setting) { - p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2; - p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2; + if (phydm_check_channel_plan(dm) || (dm->ap_total_num > adaptivity->ap_num_th) || disable_ap_adapt_setting) { + dm->th_l2h_ini = dm->th_l2h_ini_mode2; + dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_mode2; } else { - p_dm_odm->th_l2h_ini = adaptivity->th_l2h_ini_backup; - p_dm_odm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup; + dm->th_l2h_ini = adaptivity->th_l2h_ini_backup; + dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup; } } #endif else if (adaptivity->debug_mode == true) { - p_dm_odm->th_l2h_ini = adaptivity->th_l2h_ini_debug; - p_dm_odm->th_edcca_hl_diff = 7; - adaptivity->adajust_igi_level = (u8)((p_dm_odm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/ + dm->th_l2h_ini = adaptivity->th_l2h_ini_debug; + dm->th_edcca_hl_diff = 7; + adaptivity->adajust_igi_level = (u8)((dm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/ } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n")); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n", - adaptivity->igi_base, p_dm_odm->th_l2h_ini, p_dm_odm->th_edcca_hl_diff)); + PHYDM_DBG(dm, DBG_ADPTVTY, "odm_Adaptivity() =====>\n"); + PHYDM_DBG(dm, DBG_ADPTVTY, "igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n", + adaptivity->igi_base, dm->th_l2h_ini, dm->th_edcca_hl_diff); #if (RTL8195A_SUPPORT == 0) - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { /*fix AC series when enable EDCCA hang issue*/ - odm_set_bb_reg(p_dm_odm, 0x800, BIT(10), 1); /*ADC_mask disable*/ - odm_set_bb_reg(p_dm_odm, 0x800, BIT(10), 0); /*ADC_mask enable*/ + odm_set_bb_reg(dm, 0x800, BIT(10), 1); /*ADC_mask disable*/ + odm_set_bb_reg(dm, 0x800, BIT(10), 0); /*ADC_mask enable*/ } #endif igi_target = adaptivity->igi_base; adaptivity->igi_target = (u8) igi_target; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("band_width=%s, igi_target=0x%x, dynamic_link_adaptivity = %d, acs_for_adaptivity = %d\n", - (*p_dm_odm->p_band_width == ODM_BW80M) ? "80M" : ((*p_dm_odm->p_band_width == ODM_BW40M) ? "40M" : "20M"), igi_target, adaptivity->dynamic_link_adaptivity, adaptivity->acs_for_adaptivity)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, adaptivity->adajust_igi_level= 0x%x, adaptivity_flag = %d, adaptivity_enable = %d\n", - p_dm_odm->rssi_min, adaptivity->adajust_igi_level, p_dm_odm->adaptivity_flag, p_dm_odm->adaptivity_enable)); + PHYDM_DBG(dm, DBG_ADPTVTY, "band_width=%s, igi_target=0x%x, dynamic_link_adaptivity = %d\n", + (*dm->band_width == CHANNEL_WIDTH_80) ? "80M" : ((*dm->band_width == CHANNEL_WIDTH_40) ? "40M" : "20M"), igi_target, adaptivity->dynamic_link_adaptivity); + PHYDM_DBG(dm, DBG_ADPTVTY, "adajust_igi_level= 0x%x, adaptivity_flag = %d, adaptivity_enable = %d\n", + adaptivity->adajust_igi_level, dm->adaptivity_flag, dm->adaptivity_enable); - if ((adaptivity->dynamic_link_adaptivity == true) && (!p_dm_odm->is_linked) && (p_dm_odm->adaptivity_enable == false)) { - phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n")); + if (adaptivity->dynamic_link_adaptivity && (!dm->is_linked) && !dm->adaptivity_enable) { + phydm_set_edcca_threshold(dm, 0x7f, 0x7f); + PHYDM_DBG(dm, DBG_ADPTVTY, "In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n"); return; } - if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { - if ((adaptivity->adajust_igi_level > igi) && (p_dm_odm->adaptivity_enable == true)) + if (dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { + if ((adaptivity->adajust_igi_level > igi) && dm->adaptivity_enable) diff = adaptivity->adajust_igi_level - igi; - else if (p_dm_odm->adaptivity_enable == false) + else if (dm->adaptivity_enable == false) diff = 0x3e - igi; - th_l2h_dmc = p_dm_odm->th_l2h_ini - diff + igi_target; - th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + th_l2h_dmc = dm->th_l2h_ini - diff + igi_target; + th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff; } #if (RTL8195A_SUPPORT == 0) else { diff = igi_target - (s8)igi; - th_l2h_dmc = p_dm_odm->th_l2h_ini + diff; - if (th_l2h_dmc > 10 && (p_dm_odm->adaptivity_enable == true)) + th_l2h_dmc = dm->th_l2h_ini + diff; + if (th_l2h_dmc > 10 && dm->adaptivity_enable) th_l2h_dmc = 10; - th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff; /*replace lower bound to prevent EDCCA always equal 1*/ if (th_h2l_dmc < adaptivity->h2l_lb) @@ -735,13 +700,15 @@ phydm_adaptivity( th_l2h_dmc = adaptivity->l2h_lb; } #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", igi, th_l2h_dmc, th_h2l_dmc)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", p_dm_odm->adaptivity_igi_upper, adaptivity->h2l_lb, adaptivity->l2h_lb)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("debug_mode = %d\n", adaptivity->debug_mode)); - phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + adaptivity->th_l2h = th_l2h_dmc; + adaptivity->th_h2l = th_h2l_dmc; + PHYDM_DBG(dm, DBG_ADPTVTY, "IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", igi, th_l2h_dmc, th_h2l_dmc); + PHYDM_DBG(dm, DBG_ADPTVTY, "adapt_igi_up=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", adaptivity->adapt_igi_up, adaptivity->h2l_lb, adaptivity->l2h_lb); + PHYDM_DBG(dm, DBG_ADPTVTY, "debug_mode = %d\n", adaptivity->debug_mode); + phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc); - if (p_dm_odm->adaptivity_enable == true) - odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 1); + if (dm->adaptivity_enable == true) + odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1); return; } @@ -749,34 +716,34 @@ phydm_adaptivity( /*This API is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/ void phydm_pause_edcca( - void *p_dm_void, + void *dm_void, boolean is_pasue_edcca ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 IGI = p_dm_dig_table->cur_ig_value; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 IGI = dig_t->cur_ig_value; s8 diff = 0; if (is_pasue_edcca) { adaptivity->is_stop_edcca = true; - if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { + if (dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { if (adaptivity->adajust_igi_level > IGI) diff = adaptivity->adajust_igi_level - IGI; - adaptivity->backup_l2h = p_dm_odm->th_l2h_ini - diff + adaptivity->igi_target; - adaptivity->backup_h2l = adaptivity->backup_l2h - p_dm_odm->th_edcca_hl_diff; + adaptivity->backup_l2h = dm->th_l2h_ini - diff + adaptivity->igi_target; + adaptivity->backup_h2l = adaptivity->backup_l2h - dm->th_edcca_hl_diff; } #if (RTL8195A_SUPPORT == 0) else { diff = adaptivity->igi_target - (s8)IGI; - adaptivity->backup_l2h = p_dm_odm->th_l2h_ini + diff; + adaptivity->backup_l2h = dm->th_l2h_ini + diff; if (adaptivity->backup_l2h > 10) adaptivity->backup_l2h = 10; - adaptivity->backup_h2l = adaptivity->backup_l2h - p_dm_odm->th_edcca_hl_diff; + adaptivity->backup_h2l = adaptivity->backup_l2h - dm->th_edcca_hl_diff; /*replace lower bound to prevent EDCCA always equal 1*/ if (adaptivity->backup_h2l < adaptivity->h2l_lb) @@ -785,26 +752,25 @@ phydm_pause_edcca( adaptivity->backup_l2h = adaptivity->l2h_lb; } #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI)); + PHYDM_DBG(dm, DBG_ADPTVTY, "pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI); /*Disable EDCCA*/ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (odm_is_work_item_scheduled(&(adaptivity->phydm_pause_edcca_work_item)) == false) - odm_schedule_work_item(&(adaptivity->phydm_pause_edcca_work_item)); + if (odm_is_work_item_scheduled(&adaptivity->phydm_pause_edcca_work_item) == false) + odm_schedule_work_item(&adaptivity->phydm_pause_edcca_work_item); #else - phydm_pause_edcca_work_item_callback(p_dm_odm); + phydm_pause_edcca_work_item_callback(dm); #endif } else { - adaptivity->is_stop_edcca = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI)); + PHYDM_DBG(dm, DBG_ADPTVTY, "resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI); /*Resume EDCCA*/ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (odm_is_work_item_scheduled(&(adaptivity->phydm_resume_edcca_work_item)) == false) - odm_schedule_work_item(&(adaptivity->phydm_resume_edcca_work_item)); + if (odm_is_work_item_scheduled(&adaptivity->phydm_resume_edcca_work_item) == false) + odm_schedule_work_item(&adaptivity->phydm_resume_edcca_work_item); #else - phydm_resume_edcca_work_item_callback(p_dm_odm); + phydm_resume_edcca_work_item_callback(dm); #endif } @@ -815,24 +781,24 @@ phydm_pause_edcca( void phydm_pause_edcca_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16)); + if (dm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16)); #if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)(0x7f | 0x7f << 8)); + else if (dm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)(0x7f | 0x7f << 8)); #endif } @@ -840,25 +806,25 @@ phydm_pause_edcca_work_item_callback( void phydm_resume_edcca_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 16)); + if (dm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 16)); #if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 8)); + else if (dm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 8)); #endif } @@ -866,31 +832,31 @@ phydm_resume_edcca_work_item_callback( void phydm_set_edcca_threshold_api( - void *p_dm_void, + void *dm_void, u8 IGI ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); s8 th_l2h_dmc, th_h2l_dmc; s8 diff = 0, igi_target = 0x32; - if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) { - if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { + if (dm->support_ability & ODM_BB_ADAPTIVITY) { + if (dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { if (adaptivity->adajust_igi_level > IGI) diff = adaptivity->adajust_igi_level - IGI; - th_l2h_dmc = p_dm_odm->th_l2h_ini - diff + igi_target; - th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + th_l2h_dmc = dm->th_l2h_ini - diff + igi_target; + th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff; } #if (RTL8195A_SUPPORT == 0) else { diff = igi_target - (s8)IGI; - th_l2h_dmc = p_dm_odm->th_l2h_ini + diff; + th_l2h_dmc = dm->th_l2h_ini + diff; if (th_l2h_dmc > 10) th_l2h_dmc = 10; - th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff; /*replace lower bound to prevent EDCCA always equal 1*/ if (th_h2l_dmc < adaptivity->h2l_lb) @@ -899,80 +865,141 @@ phydm_set_edcca_threshold_api( th_l2h_dmc = adaptivity->l2h_lb; } #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI, th_l2h_dmc, th_h2l_dmc)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", p_dm_odm->adaptivity_igi_upper, adaptivity->h2l_lb, adaptivity->l2h_lb)); + PHYDM_DBG(dm, DBG_ADPTVTY, "API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI, th_l2h_dmc, th_h2l_dmc); + PHYDM_DBG(dm, DBG_ADPTVTY, "API :adapt_igi_up=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", adaptivity->adapt_igi_up, adaptivity->h2l_lb, adaptivity->l2h_lb); - phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc); } } void phydm_adaptivity_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); u32 used = *_used; u32 out_len = *_out_len; u32 reg_value32; s8 h2l_diff = 0; if (dm_value[0] == PHYDM_ADAPT_DEBUG) { - PHYDM_SNPRINTF((output + used, out_len - used, "Adaptivity Debug Mode ===>\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Adaptivity Debug Mode ===>\n"); adaptivity->debug_mode = true; adaptivity->th_l2h_ini_debug = (s8)dm_value[1]; - PHYDM_SNPRINTF((output + used, out_len - used, "th_l2h_ini_debug = %d\n", adaptivity->th_l2h_ini_debug)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "th_l2h_ini_debug = %d\n", + adaptivity->th_l2h_ini_debug); } else if (dm_value[0] == PHYDM_ADAPT_RESUME) { - PHYDM_SNPRINTF((output + used, out_len - used, "===> Adaptivity Resume\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "===> Adaptivity Resume\n"); adaptivity->debug_mode = false; + } else if (dm_value[0] == PHYDM_EDCCA_TH_PAUSE) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "EDCCA Threshold Pause\n"); + dm->edcca_enable = false; + } else if (dm_value[0] == PHYDM_EDCCA_RESUME) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "EDCCA Resume\n"); + dm->edcca_enable = true; } else if (dm_value[0] == PHYDM_ADAPT_MSG) { - PHYDM_SNPRINTF((output + used, out_len - used, "debug_mode = %s, th_l2h_ini = %d\n", (adaptivity->debug_mode ? "TRUE" : "FALSE"), p_dm_odm->th_l2h_ini)); - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - reg_value32 = odm_get_bb_reg(p_dm_odm, 0xc4c, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "debug_mode = %s, th_l2h_ini = %d\n", + (adaptivity->debug_mode ? "TRUE" : "FALSE"), + dm->th_l2h_ini); + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + reg_value32 = odm_get_bb_reg(dm, 0xc4c, MASKDWORD); h2l_diff = (s8)(0x000000ff & reg_value32) - (s8)((0x00ff0000 & reg_value32)>>16); } #if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - reg_value32 = odm_get_bb_reg(p_dm_odm, 0x8a4, MASKDWORD); + else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg_value32 = odm_get_bb_reg(dm, 0x8a4, MASKDWORD); h2l_diff = (s8)(0x000000ff & reg_value32) - (s8)((0x0000ff00 & reg_value32)>>8); } #endif if (h2l_diff == 7) - PHYDM_SNPRINTF((output + used, out_len - used, "adaptivity is enabled\n")); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "adaptivity is enabled\n"); else - PHYDM_SNPRINTF((output + used, out_len - used, "adaptivity is disabled\n")); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "adaptivity is disabled\n"); } - + *_used = used; + *_out_len = out_len; } void phydm_set_l2h_th_ini( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - if (p_dm_odm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) - p_dm_odm->th_l2h_ini = 0xf2; + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) + dm->th_l2h_ini = 0xf2; else - p_dm_odm->th_l2h_ini = 0xef; + dm->th_l2h_ini = 0xef; } else - p_dm_odm->th_l2h_ini = 0xf5; + dm->th_l2h_ini = 0xf5; } void phydm_set_forgetting_factor( - void *p_dm_void + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) + odm_set_bb_reg(dm, 0x8a0, BIT(1) | BIT(0), 0); +} + +void +phydm_set_pwdb_mode( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ability & ODM_BB_ADAPTIVITY) { + if (dm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(dm, 0x8dc, BIT(5), 0x1); + else if (dm->support_ic_type & ODM_RTL8197F) + odm_set_bb_reg(dm, 0xce8, BIT(13), 0x1); + } else { + if (dm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(dm, 0x8dc, BIT(5), 0x0); + else if (dm->support_ic_type & ODM_RTL8197F) + odm_set_bb_reg(dm, 0xce8, BIT(13), 0x0); + } +} + +void +phydm_set_edcca_val( + void *dm_void, + u32 *val_buf, + u8 val_len +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (val_len != 2) { + PHYDM_DBG(dm, ODM_COMP_API, "[Error][adaptivity]Need val_len = 2\n"); + return; + } + if (dm->pause_ability & BIT(F13_ADPTVTY)) + dm->adaptivity.is_stop_edcca = true; + else + dm->adaptivity.is_stop_edcca = false; - if (p_dm_odm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) - odm_set_bb_reg(p_dm_odm, 0x8a0, BIT(1) | BIT(0), 0); + phydm_set_edcca_threshold(dm, (s8)val_buf[1], (s8)val_buf[0]); } diff --git a/hal/phydm/phydm_adaptivity.h b/hal/phydm/phydm_adaptivity.h index 05e7923..f1edb5c 100644 --- a/hal/phydm/phydm_adaptivity.h +++ b/hal/phydm/phydm_adaptivity.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,48 +8,54 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ + #ifndef __PHYDMADAPTIVITY_H__ #define __PHYDMADAPTIVITY_H__ -#define ADAPTIVITY_VERSION "9.5.2" /*20170330 changed by Kevin, change th_l2h_ini setting for 5G: v2.1.0*/ +#define ADAPTIVITY_VERSION "9.5.7" /*20170627 changed by Kevin, move adapt_igi_up from phydm.h to phydm_adaptivity.h*/ #define pwdb_upper_bound 7 #define dfir_loss 7 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) enum phydm_regulation_type { - REGULATION_FCC = 0, - REGULATION_MKK = 1, - REGULATION_ETSI = 2, - REGULATION_WW = 3, - - MAX_REGULATION_NUM = 4 + REGULATION_FCC = 0, + REGULATION_MKK = 1, + REGULATION_ETSI = 2, + REGULATION_WW = 3, + MAX_REGULATION_NUM = 4 }; #endif -enum phydm_adapinfo_e { +enum phydm_adapinfo { PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0, PHYDM_ADAPINFO_DCBACKOFF, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, PHYDM_ADAPINFO_TH_L2H_INI, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, PHYDM_ADAPINFO_AP_NUM_TH - }; - - enum phydm_set_lna { phydm_disable_lna = 0, phydm_enable_lna = 1, }; - enum phydm_trx_mux_type { phydm_shutdown = 0, phydm_standby_mode = 1, @@ -59,29 +65,28 @@ enum phydm_trx_mux_type { enum phydm_mac_edcca_type { phydm_ignore_edcca = 0, - phydm_dont_ignore_edcca = 1 + phydm_dont_ignore_edcca = 1 }; enum phydm_adaptivity_mode { - PHYDM_ADAPT_MSG = 0, - PHYDM_ADAPT_DEBUG = 1, - PHYDM_ADAPT_RESUME = 2 + PHYDM_ADAPT_MSG = 0, + PHYDM_ADAPT_DEBUG = 1, + PHYDM_ADAPT_RESUME = 2, + PHYDM_EDCCA_TH_PAUSE = 3, + PHYDM_EDCCA_RESUME = 4 }; -struct _ADAPTIVITY_STATISTICS { +struct phydm_adaptivity_struct { s8 th_l2h_ini_backup; s8 th_edcca_hl_diff_backup; s8 igi_base; u8 igi_target; - u8 nhm_wait; s8 h2l_lb; s8 l2h_lb; - boolean is_first_link; - boolean is_check; - boolean dynamic_link_adaptivity; + boolean is_check; + boolean dynamic_link_adaptivity; u8 ap_num_th; u8 adajust_igi_level; - boolean acs_for_adaptivity; s8 backup_l2h; s8 backup_h2l; boolean is_stop_edcca; @@ -92,93 +97,95 @@ struct _ADAPTIVITY_STATISTICS { u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/ u8 debug_mode; s8 th_l2h_ini_debug; + u16 igi_up_bound_lmt_cnt; /*When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/ + u16 igi_up_bound_lmt_val; /*max value of igi_up_bound_lmt_cnt*/ + boolean igi_lmt_en; + u8 adapt_igi_up; + s8 rvrt_val[2]; + s8 th_l2h; + s8 th_h2l; }; void phydm_pause_edcca( - void *p_dm_void, + void *dm_void, boolean is_pasue_edcca ); -void -phydm_check_adaptivity( - void *p_dm_void -); - void phydm_check_environment( - void *p_dm_void + void *dm_void ); void phydm_mac_edcca_state( - void *p_dm_void, + void *dm_void, enum phydm_mac_edcca_type state ); void phydm_set_edcca_threshold( - void *p_dm_void, + void *dm_void, s8 H2L, s8 L2H ); void phydm_set_trx_mux( - void *p_dm_void, + void *dm_void, enum phydm_trx_mux_type tx_mode, enum phydm_trx_mux_type rx_mode ); void phydm_search_pwdb_lower_bound( - void *p_dm_void + void *dm_void ); void phydm_adaptivity_info_init( - void *p_dm_void, - enum phydm_adapinfo_e cmn_info, + void *dm_void, + enum phydm_adapinfo cmn_info, u32 value ); void phydm_adaptivity_init( - void *p_dm_void + void *dm_void ); void phydm_adaptivity( - void *p_dm_void + void *dm_void ); void phydm_set_edcca_threshold_api( - void *p_dm_void, + void *dm_void, u8 IGI ); void phydm_pause_edcca_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ); void phydm_resume_edcca_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ); void phydm_adaptivity_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, char *output, @@ -187,12 +194,24 @@ phydm_adaptivity_debug( void phydm_set_l2h_th_ini( - void *p_dm_void + void *dm_void ); void phydm_set_forgetting_factor( - void *p_dm_void + void *dm_void +); + +void +phydm_set_pwdb_mode( + void *dm_void +); + +void +phydm_set_edcca_val( + void *dm_void, + u32 *val_buf, + u8 val_len ); #endif diff --git a/hal/phydm/phydm_adc_sampling.c b/hal/phydm/phydm_adc_sampling.c index 0e7cf21..55bb013 100644 --- a/hal/phydm/phydm_adc_sampling.c +++ b/hal/phydm/phydm_adc_sampling.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,10 +8,21 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ + #include "mp_precomp.h" #include "phydm_precomp.h" @@ -37,31 +48,32 @@ #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) boolean phydm_la_buffer_allocate( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; #endif - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); - boolean ret = false; + struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf; + boolean ret = true; - dbg_print("[LA mode BufferAllocate]\n"); + pr_debug("[LA mode BufferAllocate]\n"); if (adc_smp_buf->length == 0) { - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (PlatformAllocateMemoryWithZero(adapter, (void **)&(adc_smp_buf->octet), adc_smp_buf->buffer_size) != RT_STATUS_SUCCESS) { + if (PlatformAllocateMemoryWithZero(adapter, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size) != RT_STATUS_SUCCESS) + ret = false; #else - odm_allocate_memory(p_dm_odm, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size); - if (!adc_smp_buf->octet) { -#endif + odm_allocate_memory(dm, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size); + + if (!adc_smp_buf->octet) ret = false; - } else +#endif + + if (ret) adc_smp_buf->length = adc_smp_buf->buffer_size; - ret = true; } return ret; @@ -70,12 +82,12 @@ phydm_la_buffer_allocate( void phydm_la_get_tx_pkt_buf( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; + struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf; u32 i = 0, value32, data_l = 0, data_h = 0; u32 addr, finish_addr; u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) - 1; /*end_addr = 0x3ffff;*/ @@ -84,36 +96,36 @@ phydm_la_get_tx_pkt_buf( u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0; u8 backup_dma = 0; - odm_memory_set(p_dm_odm, adc_smp_buf->octet, 0, adc_smp_buf->length); - odm_write_1byte(p_dm_odm, 0x0106, 0x69); + odm_memory_set(dm, adc_smp_buf->octet, 0, adc_smp_buf->length); + odm_write_1byte(dm, 0x0106, 0x69); - dbg_print("GetTxPktBuf\n"); + pr_debug("GetTxPktBuf\n"); - value32 = odm_read_4byte(p_dm_odm, 0x7c0); + value32 = odm_read_4byte(dm, 0x7c0); is_round_up = (boolean)((value32 & BIT(31)) >> 31); finish_addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/ #if (DM_ODM_SUPPORT_TYPE & ODM_AP) #if (RTL8197F_SUPPORT) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - odm_set_bb_reg(p_dm_odm, 0x7c0, BIT(0), 0x0); + if (dm->support_ic_type & ODM_RTL8197F) { + odm_set_bb_reg(dm, 0x7c0, BIT(0), 0x0); /*Stop DMA*/ - backup_dma = odm_get_mac_reg(p_dm_odm, 0x300, MASKLWORD); - odm_set_mac_reg(p_dm_odm, 0x300, 0x7fff, 0x7fff); + backup_dma = odm_get_mac_reg(dm, 0x300, MASKLWORD); + odm_set_mac_reg(dm, 0x300, 0x7fff, 0x7fff); /*move LA mode content from IMEM to TxPktBuffer Source : OCPBASE_IMEM 0x00000000 Destination : OCPBASE_TXBUF 0x18780000 Length : 64K*/ - GET_HAL_INTERFACE(p_dm_odm->priv)->init_ddma_handler(p_dm_odm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000); + GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000); } #endif #endif if (is_round_up) { addr = (finish_addr + 1) << 3; - dbg_print("is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n", is_round_up, finish_addr, value32); + pr_debug("is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n", is_round_up, finish_addr, value32); smp_number = ((adc_smp_buf->buffer_size) >> 3); /*Byte to 8Byte (64bit)*/ } else { addr = adc_smp_buf->start_pos; @@ -124,7 +136,7 @@ phydm_la_get_tx_pkt_buf( else smp_number = finish_addr - addr_8byte; - dbg_print("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", is_round_up, finish_addr, addr_8byte, smp_number); + pr_debug("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", is_round_up, finish_addr, addr_8byte, smp_number); } /* @@ -132,14 +144,14 @@ phydm_la_get_tx_pkt_buf( dbg_print("end_addr = %x, adc_smp_buf->start_pos = 0x%x, adc_smp_buf->buffer_size = 0x%x\n", end_addr, adc_smp_buf->start_pos, adc_smp_buf->buffer_size); */ - if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + if (dm->support_ic_type & ODM_RTL8197F) { for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) { /*64K byte*/ if ((addr & 0xfff) == 0) - odm_set_bb_reg(p_dm_odm, 0x0140, MASKLWORD, 0x780 + (addr >> 12)); - data_l = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff), MASKDWORD); - data_h = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD); + odm_set_bb_reg(dm, 0x0140, MASKLWORD, 0x780 + (addr >> 12)); + data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff), MASKDWORD); + data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD); - dbg_print("%08x%08x\n", data_h, data_l); + pr_debug("%08x%08x\n", data_h, data_l); } } else { @@ -149,11 +161,11 @@ phydm_la_get_tx_pkt_buf( /*Reg140=0x780+(addr>>12), addr=0x30~0x3F, total 16 pages*/ page = (addr >> 12); } - odm_set_bb_reg(p_dm_odm, 0x0140, MASKLWORD, 0x780 + page); + odm_set_bb_reg(dm, 0x0140, MASKLWORD, 0x780 + page); /*pDataL = 0x8000+(addr&0xfff);*/ - data_l = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff), MASKDWORD); - data_h = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD); + data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff), MASKDWORD); + data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD); #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) adc_smp_buf->octet[i] = data_h; @@ -161,7 +173,7 @@ phydm_la_get_tx_pkt_buf( #endif #if DBG /*WIN driver check build*/ - dbg_print("%08x%08x\n", data_h, data_l); + pr_debug("%08x%08x\n", data_h, data_l); #else /*WIN driver free build*/ #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1])); @@ -179,7 +191,7 @@ phydm_la_get_tx_pkt_buf( if (smp_cnt >= (smp_number - 1)) break; } - dbg_print("smp_cnt = ((%d))\n", smp_cnt); + pr_debug("smp_cnt = ((%d))\n", smp_cnt); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("smp_cnt = ((%d))\n", smp_cnt)); @@ -188,54 +200,51 @@ phydm_la_get_tx_pkt_buf( #if (DM_ODM_SUPPORT_TYPE & ODM_AP) #if (RTL8197F_SUPPORT) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - odm_set_mac_reg(p_dm_odm, 0x300, 0x7fff, backup_dma); /*Resume DMA*/ + if (dm->support_ic_type & ODM_RTL8197F) + odm_set_mac_reg(dm, 0x300, 0x7fff, backup_dma); /*Resume DMA*/ #endif #endif } void phydm_la_mode_set_mac_iq_dump( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; u32 reg_value; - odm_write_1byte(p_dm_odm, 0x7c0, 0); /*clear all 0x7c0*/ - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/ + odm_write_1byte(dm, 0x7c0, 0); /*clear all 0x7c0*/ + odm_set_mac_reg(dm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/ if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) { - adc_smp->is_bb_trigger = 0; - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(2), 1); /*polling bit for MAC mode*/ - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(4) | BIT(3), adc_smp->la_trigger_edge); /*trigger mode for MAC*/ + odm_set_mac_reg(dm, 0x7c0, BIT(2), 1); /*polling bit for MAC mode*/ + odm_set_mac_reg(dm, 0x7c0, BIT(4) | BIT(3), adc_smp->la_trigger_edge); /*trigger mode for MAC*/ - dbg_print("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n", adc_smp->la_mac_mask_or_hdr_sel, adc_smp->la_trig_sig_sel, adc_smp->la_dbg_port); + pr_debug("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n", adc_smp->la_mac_mask_or_hdr_sel, adc_smp->la_trig_sig_sel, adc_smp->la_dbg_port); /*[Set MAC Debug Port]*/ - odm_set_mac_reg(p_dm_odm, 0xF4, BIT(16), 1); - odm_set_mac_reg(p_dm_odm, 0x38, 0xff0000, adc_smp->la_dbg_port); - odm_set_mac_reg(p_dm_odm, 0x7c4, MASKDWORD, adc_smp->la_mac_mask_or_hdr_sel); - odm_set_mac_reg(p_dm_odm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel); + odm_set_mac_reg(dm, 0xF4, BIT(16), 1); + odm_set_mac_reg(dm, 0x38, 0xff0000, adc_smp->la_dbg_port); + odm_set_mac_reg(dm, 0x7c4, MASKDWORD, adc_smp->la_mac_mask_or_hdr_sel); + odm_set_mac_reg(dm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel); } else { - adc_smp->is_bb_trigger = 1; - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(1), 1); /*polling bit for BB ADC mode*/ + odm_set_mac_reg(dm, 0x7c0, BIT(1), 1); /*polling bit for BB ADC mode*/ if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) { - - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(3), 1); /*polling bit for MAC trigger event*/ - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(7) | BIT(6), adc_smp->la_trig_sig_sel); + odm_set_mac_reg(dm, 0x7c0, BIT(3), 1); /*polling bit for MAC trigger event*/ + odm_set_mac_reg(dm, 0x7c0, BIT(7) | BIT(6), adc_smp->la_trig_sig_sel); if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG) - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(5), 1); /* manual trigger 0x7C0[5] = 0->1*/ + odm_set_mac_reg(dm, 0x7c0, BIT(5), 1); /* manual trigger 0x7C0[5] = 0->1*/ } } - reg_value = odm_get_bb_reg(p_dm_odm, 0x7c0, 0xff); - dbg_print("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value); + reg_value = odm_get_bb_reg(dm, 0x7c0, 0xff); + pr_debug("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value)); #endif @@ -244,37 +253,37 @@ phydm_la_mode_set_mac_iq_dump( void phydm_adc_smp_start( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; u8 tmp_u1b; u8 while_cnt = 0; u8 polling_ok = false, target_polling_bit; - phydm_la_mode_bb_setting(p_dm_odm); - phydm_la_mode_set_trigger_time(p_dm_odm, adc_smp->la_trigger_time); + phydm_la_mode_bb_setting(dm); + phydm_la_mode_set_trigger_time(dm, adc_smp->la_trigger_time); - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - odm_set_bb_reg(p_dm_odm, 0xd00, BIT(26), 0x1); + if (dm->support_ic_type & ODM_RTL8197F) + odm_set_bb_reg(dm, 0xd00, BIT(26), 0x1); else { /*for 8814A and 8822B?*/ - odm_write_1byte(p_dm_odm, 0x8b4, 0x80); - /* odm_set_bb_reg(p_dm_odm, 0x8b4, BIT(7), 1); */ + odm_write_1byte(dm, 0x8b4, 0x80); + /* odm_set_bb_reg(dm, 0x8b4, BIT(7), 1); */ } - phydm_la_mode_set_mac_iq_dump(p_dm_odm); + phydm_la_mode_set_mac_iq_dump(dm); #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - watchdog_stop(p_dm_odm->priv); + watchdog_stop(dm->priv); #endif target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2); do { /*Polling time always use 100ms, when it exceed 2s, break while loop*/ - tmp_u1b = odm_read_1byte(p_dm_odm, 0x7c0); + tmp_u1b = odm_read_1byte(dm, 0x7c0); if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) { - dbg_print("[state Error] adc_smp_state != ADCSMP_STATE_SET\n"); + pr_debug("[state Error] adc_smp_state != ADCSMP_STATE_SET\n"); break; } else if (tmp_u1b & target_polling_bit) { @@ -282,22 +291,21 @@ phydm_adc_smp_start( while_cnt = while_cnt + 1; continue; } else { - dbg_print("[LA Query OK] polling_bit=((0x%x))\n", target_polling_bit); + pr_debug("[LA Query OK] polling_bit=((0x%x))\n", target_polling_bit); polling_ok = true; break; } } while (while_cnt < 20); if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) { - if (polling_ok) - phydm_la_get_tx_pkt_buf(p_dm_odm); + phydm_la_get_tx_pkt_buf(dm); else - dbg_print("[Polling timeout]\n"); + pr_debug("[Polling timeout]\n"); } #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - watchdog_resume(p_dm_odm->priv); + watchdog_resume(dm->priv); #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) @@ -305,26 +313,25 @@ phydm_adc_smp_start( adc_smp->adc_smp_state = ADCSMP_STATE_QUERY; #endif - dbg_print("[LA mode] LA_pattern_count = ((%d))\n", adc_smp->la_count); + pr_debug("[LA mode] LA_pattern_count = ((%d))\n", adc_smp->la_count); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("[LA mode] la_count = ((%d))\n", adc_smp->la_count)); #endif - adc_smp_stop(p_dm_odm); + adc_smp_stop(dm); if (adc_smp->la_count == 0) { - dbg_print("LA Dump finished ---------->\n\n\n"); - phydm_release_bb_dbg_port(p_dm_odm); + pr_debug("LA Dump finished ---------->\n\n\n"); + phydm_release_bb_dbg_port(dm); - if ((p_dm_odm->support_ic_type & ODM_RTL8821C) && (p_dm_odm->cut_version >= ODM_CUT_B)) { - odm_set_bb_reg(p_dm_odm, 0x95c, BIT(23), 0); - } + if ((dm->support_ic_type & ODM_RTL8821C) && (dm->cut_version >= ODM_CUT_B)) + odm_set_bb_reg(dm, 0x95c, BIT(23), 0); } else { adc_smp->la_count--; - dbg_print("LA Dump more ---------->\n\n\n"); - adc_smp_set(p_dm_odm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel, adc_smp->la_dma_type, adc_smp->la_trigger_time, 0); + pr_debug("LA Dump more ---------->\n\n\n"); + adc_smp_set(dm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel, adc_smp->la_dma_type, adc_smp->la_trigger_time, 0); } } @@ -332,22 +339,22 @@ phydm_adc_smp_start( #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) void adc_smp_work_item_callback( - void *p_context + void *context ) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_context; - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + void *adapter = (void *)context; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct rt_adcsmp *adc_smp = &dm->adcsmp; - dbg_print("[WorkItem Call back] LA_State=((%d))\n", adc_smp->adc_smp_state); - phydm_adc_smp_start(p_dm_odm); + pr_debug("[WorkItem Call back] LA_State=((%d))\n", adc_smp->adc_smp_state); + phydm_adc_smp_start(dm); } #endif void adc_smp_set( - void *p_dm_void, + void *dm_void, u8 trig_mode, u32 trig_sig_sel, u8 dma_data_sig_sel, @@ -355,9 +362,9 @@ adc_smp_set( u16 polling_time ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; boolean is_set_success = true; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct rt_adcsmp *adc_smp = &dm->adcsmp; adc_smp->la_trig_mode = trig_mode; adc_smp->la_trig_sig_sel = trig_sig_sel; @@ -368,29 +375,29 @@ adc_smp_set( if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE) is_set_success = false; else if (adc_smp->adc_smp_buf.length == 0) - is_set_success = phydm_la_buffer_allocate(p_dm_odm); + is_set_success = phydm_la_buffer_allocate(dm); #endif if (is_set_success) { adc_smp->adc_smp_state = ADCSMP_STATE_SET; - dbg_print("[LA Set Success] LA_State=((%d))\n", adc_smp->adc_smp_state); + pr_debug("[LA Set Success] LA_State=((%d))\n", adc_smp->adc_smp_state); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - dbg_print("ADCSmp_work_item_index = ((%d))\n", adc_smp->la_work_item_index); + pr_debug("ADCSmp_work_item_index = ((%d))\n", adc_smp->la_work_item_index); if (adc_smp->la_work_item_index != 0) { - odm_schedule_work_item(&(adc_smp->adc_smp_work_item_1)); + odm_schedule_work_item(&adc_smp->adc_smp_work_item_1); adc_smp->la_work_item_index = 0; } else { - odm_schedule_work_item(&(adc_smp->adc_smp_work_item)); + odm_schedule_work_item(&adc_smp->adc_smp_work_item); adc_smp->la_work_item_index = 1; } #else - phydm_adc_smp_start(p_dm_odm); + phydm_adc_smp_start(dm); #endif } else - dbg_print("[LA Set Fail] LA_State=((%d))\n", adc_smp->adc_smp_state); + pr_debug("[LA Set Fail] LA_State=((%d))\n", adc_smp->adc_smp_state); } @@ -398,18 +405,18 @@ adc_smp_set( #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) enum rt_status adc_smp_query( - void *p_dm_void, + void *dm_void, ULONG information_buffer_length, void *information_buffer, PULONG bytes_written ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; enum rt_status ret_status = RT_STATUS_SUCCESS; - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf; - dbg_print("[%s] LA_State=((%d))", __func__, adc_smp->adc_smp_state); + pr_debug("[%s] LA_State=((%d))", __func__, adc_smp->adc_smp_state); if (information_buffer_length != adc_smp_buf->buffer_size) { *bytes_written = 0; @@ -421,13 +428,13 @@ adc_smp_query( *bytes_written = 0; ret_status = RT_STATUS_PENDING; } else { - odm_move_memory(p_dm_odm, information_buffer, adc_smp_buf->octet, adc_smp_buf->buffer_size); + odm_move_memory(dm, information_buffer, adc_smp_buf->octet, adc_smp_buf->buffer_size); *bytes_written = adc_smp_buf->buffer_size; adc_smp->adc_smp_state = ADCSMP_STATE_IDLE; } - dbg_print("Return status %d\n", ret_status); + pr_debug("Return status %d\n", ret_status); return ret_status; } @@ -435,67 +442,70 @@ adc_smp_query( void adc_smp_query( - void *p_dm_void, + void *dm_void, void *output, u32 out_len, u32 *pused ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; + struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf; u32 used = *pused; u32 i; /* struct timespec t; */ /* rtw_get_current_timespec(&t); */ - dbg_print("%s adc_smp_state %d", __func__, adc_smp->adc_smp_state); + pr_debug("%s adc_smp_state %d", __func__, adc_smp->adc_smp_state); for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) { - PHYDM_SNPRINTF((output + used, out_len - used, - "%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1])); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%08x%08x\n", adc_smp_buf->octet[i], + adc_smp_buf->octet[i + 1]); } - PHYDM_SNPRINTF((output + used, out_len - used, "\n")); - /* PHYDM_SNPRINTF((output+used, out_len-used, "\n[%lu.%06lu]\n", t.tv_sec, t.tv_nsec)); */ + PDM_SNPF(out_len, used, output + used, out_len - used, "\n"); + /* PDM_SNPF((output+used, out_len-used, "\n[%lu.%06lu]\n", t.tv_sec, t.tv_nsec)); */ *pused = used; } s32 adc_smp_get_sample_counts( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; + struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf; return (adc_smp_buf->length >> 2) - 2; } s32 adc_smp_query_single_data( - void *p_dm_void, + void *dm_void, void *output, u32 out_len, u32 index ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; + struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf; u32 used = 0; /* dbg_print("%s adc_smp_state %d\n", __func__, adc_smp->adc_smp_state); */ if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) { - PHYDM_SNPRINTF((output + used, out_len - used, - "Error: la data is not ready yet ...\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Error: la data is not ready yet ...\n"); return -1; } if (index < ((adc_smp_buf->length >> 2) - 2)) { - PHYDM_SNPRINTF((output + used, out_len - used, "%08x%08x\n", - adc_smp_buf->octet[index], adc_smp_buf->octet[index + 1])); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%08x%08x\n", + adc_smp_buf->octet[index], + adc_smp_buf->octet[index + 1]); } return 0; } @@ -504,37 +514,37 @@ adc_smp_query_single_data( void adc_smp_stop( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; adc_smp->adc_smp_state = ADCSMP_STATE_IDLE; - dbg_print("[LA_Stop] LA_state = ((%d))\n", adc_smp->adc_smp_state); + pr_debug("[LA_Stop] LA_state = ((%d))\n", adc_smp->adc_smp_state); } void adc_smp_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; + struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf; adc_smp->adc_smp_state = ADCSMP_STATE_IDLE; - if (p_dm_odm->support_ic_type & ODM_RTL8814A) { + if (dm->support_ic_type & ODM_RTL8814A) { adc_smp_buf->start_pos = 0x30000; adc_smp_buf->buffer_size = 0x10000; - } else if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + } else if (dm->support_ic_type & ODM_RTL8822B) { adc_smp_buf->start_pos = 0x20000; adc_smp_buf->buffer_size = 0x20000; - } else if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + } else if (dm->support_ic_type & ODM_RTL8197F) { adc_smp_buf->start_pos = 0x00000; adc_smp_buf->buffer_size = 0x10000; - } else if (p_dm_odm->support_ic_type & ODM_RTL8821C) { + } else if (dm->support_ic_type & ODM_RTL8821C) { adc_smp_buf->start_pos = 0x8000; adc_smp_buf->buffer_size = 0x8000; } @@ -544,17 +554,17 @@ adc_smp_init( #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) void adc_smp_de_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; + struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf; - adc_smp_stop(p_dm_odm); + adc_smp_stop(dm); if (adc_smp_buf->length != 0x0) { - odm_free_memory(p_dm_odm, adc_smp_buf->octet, adc_smp_buf->length); + odm_free_memory(dm, adc_smp_buf->octet, adc_smp_buf->length); adc_smp_buf->length = 0x0; } } @@ -564,11 +574,11 @@ adc_smp_de_init( void phydm_la_mode_bb_setting( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; u8 trig_mode = adc_smp->la_trig_mode; u32 trig_sig_sel = adc_smp->la_trig_sig_sel; @@ -578,7 +588,7 @@ phydm_la_mode_bb_setting( u8 la_dma_type = adc_smp->la_dma_type; u32 dbg_port_header_sel = 0; - dbg_print("1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n", + pr_debug("1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n", trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel, la_dma_type); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) @@ -590,12 +600,11 @@ phydm_la_mode_bb_setting( trig_sig_sel = 0; /*ignore this setting*/ /*set BB debug port*/ - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_3, dbg_port)) { - dbg_print("Set dbg_port((0x%x)) success\n", dbg_port); + if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3, dbg_port)) { + pr_debug("Set dbg_port((0x%x)) success\n", dbg_port); } - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { if (trig_mode == PHYDM_ADC_RF0_TRIG) dbg_port_header_sel = 9; /*DBGOUT_RFC_a[31:0]*/ else if (trig_mode == PHYDM_ADC_RF1_TRIG) @@ -609,12 +618,12 @@ phydm_la_mode_bb_setting( } } - phydm_bb_dbg_port_header_sel(p_dm_odm, dbg_port_header_sel); + phydm_bb_dbg_port_header_sel(dm, dbg_port_header_sel); - odm_set_bb_reg(p_dm_odm, 0x95c, 0xf00, la_dma_type); /*0x95C[11:8]*/ - odm_set_bb_reg(p_dm_odm, 0x95C, 0x1f, trig_sig_sel); /*0x95C[4:0], BB debug port bit*/ - odm_set_bb_reg(p_dm_odm, 0x95C, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/ - odm_set_bb_reg(p_dm_odm, 0x95c, 0xe0, sampling_rate); + odm_set_bb_reg(dm, 0x95c, 0xf00, la_dma_type); /*0x95C[11:8]*/ + odm_set_bb_reg(dm, 0x95C, 0x1f, trig_sig_sel); /*0x95C[4:0], BB debug port bit*/ + odm_set_bb_reg(dm, 0x95C, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/ + odm_set_bb_reg(dm, 0x95c, 0xe0, sampling_rate); /* (0:) '80MHz' (1:) '40MHz' (2:) '20MHz' @@ -624,15 +633,14 @@ phydm_la_mode_bb_setting( (6:) '1.25MHz' (7:) '160MHz (for BW160 ic)' */ - if ((p_dm_odm->support_ic_type & ODM_RTL8821C) && (p_dm_odm->cut_version >= ODM_CUT_B)) { - odm_set_bb_reg(p_dm_odm, 0x95c, BIT(23), 1); + if ((dm->support_ic_type & ODM_RTL8821C) && (dm->cut_version >= ODM_CUT_B)) { + odm_set_bb_reg(dm, 0x95c, BIT(23), 1); } } else { - - odm_set_bb_reg(p_dm_odm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/ - odm_set_bb_reg(p_dm_odm, 0x9a0, 0x1f, trig_sig_sel); /*0x9A0[4:0], BB debug port bit*/ - odm_set_bb_reg(p_dm_odm, 0x9A0, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/ - odm_set_bb_reg(p_dm_odm, 0x9A0, 0xe0, sampling_rate); + odm_set_bb_reg(dm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/ + odm_set_bb_reg(dm, 0x9a0, 0x1f, trig_sig_sel); /*0x9A0[4:0], BB debug port bit*/ + odm_set_bb_reg(dm, 0x9A0, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/ + odm_set_bb_reg(dm, 0x9A0, 0xe0, sampling_rate); /* (0:) '80MHz' (1:) '40MHz' (2:) '20MHz' @@ -647,11 +655,11 @@ phydm_la_mode_bb_setting( void phydm_la_mode_set_trigger_time( - void *p_dm_void, + void *dm_void, u32 trigger_time_mu_sec ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 trigger_time_unit_num; u32 time_unit = 0; @@ -673,29 +681,29 @@ phydm_la_mode_set_trigger_time( trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit); - dbg_print("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit); + pr_debug("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit)); #endif - odm_set_mac_reg(p_dm_odm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit); - odm_set_mac_reg(p_dm_odm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f)); + odm_set_mac_reg(dm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit); + odm_set_mac_reg(dm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f)); } void phydm_lamode_trigger_setting( - void *p_dm_void, - char input[][16], + void *dm_void, + char input[][16], u32 *_used, - char *output, + char *output, u32 *_out_len, u32 input_num ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *adc_smp = &dm->adcsmp; u8 trig_mode, dma_data_sig_sel; u32 trig_sig_sel; boolean is_enable_la_mode; @@ -705,17 +713,17 @@ phydm_lamode_trigger_setting( u32 used = *_used; u32 out_len = *_out_len; - if (p_dm_odm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) { - + if (dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) { PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); is_enable_la_mode = (boolean)var1[0]; /*dbg_print("echo cmd input_num = %d\n", input_num);*/ if ((strcmp(input[1], help) == 0)) { - PHYDM_SNPRINTF((output + used, out_len - used, "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n")); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n"); /**/ } else if ((is_enable_la_mode == 1)) { - PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); trig_mode = (u8)var1[1]; @@ -744,22 +752,39 @@ phydm_lamode_trigger_setting( adc_smp->la_count = var1[9]; - dbg_print("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]); + pr_debug("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9])); #endif - PHYDM_SNPRINTF((output + used, out_len - used, "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n", trig_mode, trig_sig_sel, dma_data_sig_sel)); - PHYDM_SNPRINTF((output + used, out_len - used, "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n", trigger_time_mu_sec, adc_smp->la_mac_mask_or_hdr_sel, adc_smp->la_dbg_port)); - PHYDM_SNPRINTF((output + used, out_len - used, "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n", adc_smp->la_trigger_edge, (80 >> adc_smp->la_smp_rate), adc_smp->la_count)); - - adc_smp_set(p_dm_odm, trig_mode, trig_sig_sel, dma_data_sig_sel, trigger_time_mu_sec, 0); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n", + trig_mode, trig_sig_sel, + dma_data_sig_sel); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n", + trigger_time_mu_sec, + adc_smp->la_mac_mask_or_hdr_sel, + adc_smp->la_dbg_port); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n", + adc_smp->la_trigger_edge, + (80 >> adc_smp->la_smp_rate), + adc_smp->la_count); + + adc_smp_set(dm, trig_mode, trig_sig_sel, dma_data_sig_sel, trigger_time_mu_sec, 0); } else { - adc_smp_stop(p_dm_odm); - PHYDM_SNPRINTF((output + used, out_len - used, "Disable LA mode\n")); + adc_smp_stop(dm); + PDM_SNPF(out_len, used, output + used, + out_len - used, "Disable LA mode\n"); } } + *_used = used; + *_out_len = out_len; } #endif /*endif PHYDM_LA_MODE_SUPPORT == 1*/ diff --git a/hal/phydm/phydm_adc_sampling.h b/hal/phydm/phydm_adc_sampling.h index ecc9701..9e9fc59 100644 --- a/hal/phydm/phydm_adc_sampling.h +++ b/hal/phydm/phydm_adc_sampling.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,10 +8,21 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ + #ifndef __INC_ADCSMP_H #define __INC_ADCSMP_H @@ -19,7 +30,7 @@ #if (PHYDM_LA_MODE_SUPPORT == 1) -struct _RT_ADCSMP_STRING { +struct rt_adcsmp_string { u32 *octet; u32 length; u32 buffer_size; @@ -51,8 +62,8 @@ enum rt_adcsmp_state { }; -struct _RT_ADCSMP { - struct _RT_ADCSMP_STRING adc_smp_buf; +struct rt_adcsmp { + struct rt_adcsmp_string adc_smp_buf; enum rt_adcsmp_state adc_smp_state; u8 la_trig_mode; u32 la_trig_sig_sel; @@ -75,13 +86,13 @@ struct _RT_ADCSMP { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) void adc_smp_work_item_callback( - void *p_context + void *context ); #endif void adc_smp_set( - void *p_dm_void, + void *dm_void, u8 trig_mode, u32 trig_sig_sel, u8 dma_data_sig_sel, @@ -92,7 +103,7 @@ adc_smp_set( #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) enum rt_status adc_smp_query( - void *p_dm_void, + void *dm_void, ULONG information_buffer_length, void *information_buffer, PULONG bytes_written @@ -100,7 +111,7 @@ adc_smp_query( #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) void adc_smp_query( - void *p_dm_void, + void *dm_void, void *output, u32 out_len, u32 *pused @@ -108,12 +119,12 @@ adc_smp_query( s32 adc_smp_get_sample_counts( - void *p_dm_void + void *dm_void ); s32 adc_smp_query_single_data( - void *p_dm_void, + void *dm_void, void *output, u32 out_len, u32 index @@ -122,35 +133,35 @@ adc_smp_query_single_data( #endif void adc_smp_stop( - void *p_dm_void + void *dm_void ); void adc_smp_init( - void *p_dm_void + void *dm_void ); #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) void adc_smp_de_init( - void *p_dm_void + void *dm_void ); #endif void phydm_la_mode_bb_setting( - void *p_dm_void + void *dm_void ); void phydm_la_mode_set_trigger_time( - void *p_dm_void, + void *dm_void, u32 trigger_time_mu_sec ); void phydm_lamode_trigger_setting( - void *p_dm_void, + void *dm_void, char input[][16], u32 *_used, char *output, diff --git a/hal/phydm/phydm_antdect.c b/hal/phydm/phydm_antdect.c index 7980967..1d96aa9 100644 --- a/hal/phydm/phydm_antdect.c +++ b/hal/phydm/phydm_antdect.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -37,23 +47,23 @@ * */ void odm_single_dual_antenna_default_setting( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + void *adapter = dm->adapter; - u8 bt_ant_num = BT_GetPgAntNum(p_adapter); + u8 bt_ant_num = BT_GetPgAntNum(adapter); /* Set default antenna A and B status */ if (bt_ant_num == 2) { - p_dm_swat_table->ANTA_ON = true; - p_dm_swat_table->ANTB_ON = true; + dm_swat_table->ANTA_ON = true; + dm_swat_table->ANTB_ON = true; } else if (bt_ant_num == 1) { /* Set antenna A as default */ - p_dm_swat_table->ANTA_ON = true; - p_dm_swat_table->ANTB_ON = false; + dm_swat_table->ANTA_ON = true; + dm_swat_table->ANTB_ON = false; } else RT_ASSERT(false, ("Incorrect antenna number!!\n")); @@ -70,13 +80,13 @@ odm_single_dual_antenna_default_setting( * */ boolean odm_single_dual_antenna_detection( - void *p_dm_void, + void *dm_void, u8 mode ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; u32 current_channel, rf_loop_reg; u8 n; u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca; @@ -84,179 +94,168 @@ odm_single_dual_antenna_detection( u32 PSD_report_tmp; u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0; boolean is_result = true; - u32 afe_backup[16]; - u32 AFE_REG_8723A[16] = { - REG_RX_WAIT_CCA, REG_TX_CCK_RFON, - REG_TX_CCK_BBON, REG_TX_OFDM_RFON, - REG_TX_OFDM_BBON, REG_TX_TO_RX, - REG_TX_TO_TX, REG_RX_CCK, - REG_RX_OFDM, REG_RX_WAIT_RIFS, - REG_RX_TO_RX, REG_STANDBY, - REG_SLEEP, REG_PMPD_ANAEN, - REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH - }; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection()============>\n")); - - - if (!(p_dm_odm->support_ic_type & ODM_RTL8723B)) + + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection()============>\n"); + + + if (!(dm->support_ic_type & ODM_RTL8723B)) return is_result; /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */ - if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(p_adapter)) + if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(((PADAPTER)adapter))) return is_result; /* 1 Backup Current RF/BB Settings */ - current_channel = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK); - rf_loop_reg = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK); - if (p_dm_odm->support_ic_type & ODM_RTL8723B) { - reg92c = odm_get_bb_reg(p_dm_odm, REG_DPDT_CONTROL, MASKDWORD); - reg930 = odm_get_bb_reg(p_dm_odm, rfe_ctrl_anta_src, MASKDWORD); - reg948 = odm_get_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD); - regb2c = odm_get_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD); - reg064 = odm_get_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29)); - odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, 0x3, 0x1); - odm_set_bb_reg(p_dm_odm, rfe_ctrl_anta_src, 0xff, 0x77); - odm_set_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* dbg 7 */ - odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0);/* dbg 8 */ - odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x0); + current_channel = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK); + rf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, 0x00, RFREGOFFSETMASK); + if (dm->support_ic_type & ODM_RTL8723B) { + reg92c = odm_get_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD); + reg930 = odm_get_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD); + reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD); + regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD); + reg064 = odm_get_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29)); + odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x1); + odm_set_bb_reg(dm, rfe_ctrl_anta_src, 0xff, 0x77); + odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* dbg 7 */ + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0);/* dbg 8 */ + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x0); } - odm_stall_execution(10); + ODM_delay_us(10); /* Store A path Register 88c, c08, 874, c50 */ - reg88c = odm_get_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD); - regc08 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD); - reg874 = odm_get_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD); - regc50 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD); + reg88c = odm_get_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD); + regc08 = odm_get_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD); + reg874 = odm_get_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD); + regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD); /* Store AFE Registers */ - if (p_dm_odm->support_ic_type & ODM_RTL8723B) - afe_rrx_wait_cca = odm_get_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD); + if (dm->support_ic_type & ODM_RTL8723B) + afe_rrx_wait_cca = odm_get_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD); /* Set PSD 128 pts */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pts */ + odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pts */ /* To SET CH1 to do */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* channel 1 */ + odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* channel 1 */ /* AFE all on step */ - if (p_dm_odm->support_ic_type & ODM_RTL8723B) - odm_set_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016); + if (dm->support_ic_type & ODM_RTL8723B) + odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016); /* 3 wire Disable */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0); + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0); /* BB IQK setting */ - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4); - odm_set_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000); + odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4); + odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000); /* IQK setting tone@ 4.34Mhz */ - odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C); - odm_set_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD, 0x01007c00); + odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C); + odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00); /* Page B init */ - odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000); - odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000); - odm_set_bb_reg(p_dm_odm, REG_RX_IQK, MASKDWORD, 0x01004800); - odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f); - if (p_dm_odm->support_ic_type & ODM_RTL8723B) { - odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016); - odm_set_bb_reg(p_dm_odm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016); + odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000); + odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000); + odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800); + odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f); + if (dm->support_ic_type & ODM_RTL8723B) { + odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016); + odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016); } - odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0); - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain); + odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0); + odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain); /* IQK Single tone start */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x808000); - odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000); - odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000); + odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); + odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000); + odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000); - odm_stall_execution(10000); + ODM_delay_us(10000); /* PSD report of antenna A */ PSD_report_tmp = 0x0; for (n = 0; n < 2; n++) { - PSD_report_tmp = phydm_get_psd_data(p_dm_odm, 14, initial_gain); + PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain); if (PSD_report_tmp > ant_a_report) ant_a_report = PSD_report_tmp; } /* change to Antenna B */ - if (p_dm_odm->support_ic_type & ODM_RTL8723B) { - /* odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, 0x3, 0x2); */ - odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280); - odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x1); + if (dm->support_ic_type & ODM_RTL8723B) { + /* odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x2); */ + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280); + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1); } - odm_stall_execution(10); + ODM_delay_us(10); /* PSD report of antenna B */ PSD_report_tmp = 0x0; for (n = 0; n < 2; n++) { - PSD_report_tmp = phydm_get_psd_data(p_dm_odm, 14, initial_gain); + PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain); if (PSD_report_tmp > ant_b_report) ant_b_report = PSD_report_tmp; } /* Close IQK Single Tone function */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000); + odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); /* 1 Return to antanna A */ - if (p_dm_odm->support_ic_type & ODM_RTL8723B) { + if (dm->support_ic_type & ODM_RTL8723B) { /* external DPDT */ - odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, MASKDWORD, reg92c); + odm_set_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD, reg92c); /* internal S0/S1 */ - odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948); - odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c); - odm_set_bb_reg(p_dm_odm, rfe_ctrl_anta_src, MASKDWORD, reg930); - odm_set_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064); + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948); + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c); + odm_set_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD, reg930); + odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064); } - odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c); - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08); - odm_set_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874); - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40); - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_loop_reg); + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c); + odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08); + odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874); + odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40); + odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50); + odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel); + odm_set_rf_reg(dm, RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_loop_reg); /* Reload AFE Registers */ - if (p_dm_odm->support_ic_type & ODM_RTL8723B) - odm_set_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca); + if (dm->support_ic_type & ODM_RTL8723B) + odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca); - if (p_dm_odm->support_ic_type & ODM_RTL8723B) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, ant_a_report)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, ant_b_report)); + if (dm->support_ic_type & ODM_RTL8723B) { + PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_A[%d]= %d\n", 2416, ant_a_report); + PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_B[%d]= %d\n", 2416, ant_b_report); /* 2 Test ant B based on ant A is ON */ if ((ant_a_report >= 100) && (ant_b_report >= 100) && (ant_a_report <= 135) && (ant_b_report <= 135)) { u8 TH1 = 2, TH2 = 6; if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) { - p_dm_swat_table->ANTA_ON = true; - p_dm_swat_table->ANTB_ON = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Dual Antenna\n")); + dm_swat_table->ANTA_ON = true; + dm_swat_table->ANTB_ON = true; + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection(): Dual Antenna\n"); } else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) || ((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) { - p_dm_swat_table->ANTA_ON = false; - p_dm_swat_table->ANTB_ON = false; + dm_swat_table->ANTA_ON = false; + dm_swat_table->ANTB_ON = false; is_result = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Need to check again\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection(): Need to check again\n"); } else { - p_dm_swat_table->ANTA_ON = true; - p_dm_swat_table->ANTB_ON = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Single Antenna\n")); + dm_swat_table->ANTA_ON = true; + dm_swat_table->ANTB_ON = false; + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection(): Single Antenna\n"); } - p_dm_odm->ant_detected_info.is_ant_detected = true; - p_dm_odm->ant_detected_info.db_for_ant_a = ant_a_report; - p_dm_odm->ant_detected_info.db_for_ant_b = ant_b_report; - p_dm_odm->ant_detected_info.db_for_ant_o = ant_0_report; + dm->ant_detected_info.is_ant_detected = true; + dm->ant_detected_info.db_for_ant_a = ant_a_report; + dm->ant_detected_info.db_for_ant_b = ant_b_report; + dm->ant_detected_info.db_for_ant_o = ant_0_report; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("return false!!\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "return false!!\n"); is_result = false; } } @@ -273,18 +272,18 @@ odm_single_dual_antenna_detection( boolean odm_sw_ant_div_check_before_link( - void *p_dm_void + void *dm_void ) { - #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + //PMGNT_INFO mgnt_info = &adapter->MgntInfo; + PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo); + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; s8 score = 0; PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc; u8 power_target_L = 9, power_target_H = 16; @@ -293,317 +292,317 @@ odm_sw_ant_div_check_before_link( static u8 scan_channel; u32 tmp_swas_no_link_bk_reg948; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", p_dm_odm->dm_swat_table.ANTA_ON, p_dm_odm->dm_swat_table.ANTB_ON)); + PHYDM_DBG(dm, DBG_ANT_DIV, "ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON); /* if(HP id) */ { - if (p_dm_odm->dm_swat_table.rssi_ant_dect_result == true && p_dm_odm->support_ic_type == ODM_RTL8723B) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n")); + if (dm->dm_swat_table.rssi_ant_dect_result == true && dm->support_ic_type == ODM_RTL8723B) { + PHYDM_DBG(dm, DBG_ANT_DIV, "8723B RSSI-based Antenna Detection is done\n"); return false; } - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - if (p_dm_swat_table->swas_no_link_bk_reg948 == 0xff) - p_dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(p_dm_odm, REG_S0_S1_PATH_SWITCH); + if (dm->support_ic_type == ODM_RTL8723B) { + if (dm_swat_table->swas_no_link_bk_reg948 == 0xff) + dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH); } } - if (p_dm_odm->adapter == NULL) { /* For BSOD when plug/unplug fast. //By YJ,120413 */ + if (dm->adapter == NULL) { /* For BSOD when plug/unplug fast. //By YJ,120413 */ /* The ODM structure is not initialized. */ return false; } /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */ - if (!IS_ANT_DETECT_SUPPORT_RSSI(adapter)) + if (!IS_ANT_DETECT_SUPPORT_RSSI(((PADAPTER)adapter))) return false; else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI method\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "Antenna Detection: RSSI method\n"); /* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */ - odm_acquire_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK); - if (p_hal_data->eRFPowerState != eRfOn || p_mgnt_info->RFChangeInProgress || p_mgnt_info->bMediaConnect) { - odm_release_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK); + odm_acquire_spin_lock(dm, RT_RF_STATE_SPINLOCK); + if (hal_data->eRFPowerState != eRfOn || mgnt_info->RFChangeInProgress || mgnt_info->bMediaConnect) { + odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("odm_sw_ant_div_check_before_link(): rf_change_in_progress(%x), e_rf_power_state(%x)\n", - p_mgnt_info->RFChangeInProgress, p_hal_data->eRFPowerState)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_sw_ant_div_check_before_link(): rf_change_in_progress(%x), e_rf_power_state(%x)\n", + mgnt_info->RFChangeInProgress, hal_data->eRFPowerState); - p_dm_swat_table->swas_no_link_state = 0; + dm_swat_table->swas_no_link_state = 0; return false; } else - odm_release_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->swas_no_link_state = %d\n", p_dm_swat_table->swas_no_link_state)); + odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK); + PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->swas_no_link_state = %d\n", dm_swat_table->swas_no_link_state); /* 1 Run AntDiv mechanism "Before Link" part. */ - if (p_dm_swat_table->swas_no_link_state == 0) { + if (dm_swat_table->swas_no_link_state == 0) { /* 1 Prepare to do Scan again to check current antenna state. */ /* Set check state to next step. */ - p_dm_swat_table->swas_no_link_state = 1; + dm_swat_table->swas_no_link_state = 1; /* Copy Current Scan list. */ - p_mgnt_info->tmpNumBssDesc = p_mgnt_info->NumBssDesc; - PlatformMoveMemory((void *)adapter->MgntInfo.tmpbssDesc, (void *)p_mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC); + mgnt_info->tmpNumBssDesc = mgnt_info->NumBssDesc; + PlatformMoveMemory((void *)mgnt_info->tmpbssDesc, (void *)mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC); /* Go back to scan function again. */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Scan one more time\n")); - p_mgnt_info->ScanStep = 0; - p_mgnt_info->bScanAntDetect = true; + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Scan one more time\n"); + mgnt_info->ScanStep = 0; + mgnt_info->bScanAntDetect = true; scan_channel = odm_sw_ant_div_select_scan_chnl(adapter); - if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) { - if (p_dm_fat_table->rx_idle_ant == MAIN_ANT) - odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) { + if (fat_tab->rx_idle_ant == MAIN_ANT) + odm_update_rx_idle_ant(dm, AUX_ANT); else - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); + odm_update_rx_idle_ant(dm, MAIN_ANT); if (scan_channel == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("odm_sw_ant_div_check_before_link(): No AP List Avaiable, Using ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_sw_ant_div_check_before_link(): No AP List Avaiable, Using ant(%s)\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT"); - if (IS_5G_WIRELESS_MODE(p_mgnt_info->dot11CurrentWirelessMode)) { - p_dm_swat_table->ant_5g = p_dm_fat_table->rx_idle_ant; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_5g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) { + dm_swat_table->ant_5g = fat_tab->rx_idle_ant; + PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); } else { - p_dm_swat_table->ant_2g = p_dm_fat_table->rx_idle_ant; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_2g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + dm_swat_table->ant_2g = fat_tab->rx_idle_ant; + PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); } return false; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("odm_sw_ant_div_check_before_link: Change to %s for testing.\n", ((p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"))); - } else if (p_dm_odm->support_ic_type & (ODM_RTL8723B)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_sw_ant_div_check_before_link: Change to %s for testing.\n", ((fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + } else if (dm->support_ic_type & (ODM_RTL8723B)) { /*Switch Antenna to another one.*/ - tmp_swas_no_link_bk_reg948 = odm_read_4byte(p_dm_odm, REG_S0_S1_PATH_SWITCH); + tmp_swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH); - if ((p_dm_swat_table->cur_antenna == MAIN_ANT) && (tmp_swas_no_link_bk_reg948 == 0x200)) { - odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280); - odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x1); - p_dm_swat_table->cur_antenna = AUX_ANT; + if ((dm_swat_table->cur_antenna == MAIN_ANT) && (tmp_swas_no_link_bk_reg948 == 0x200)) { + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280); + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1); + dm_swat_table->cur_antenna = AUX_ANT; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_swas_no_link_bk_reg948)); + PHYDM_DBG(dm, DBG_ANT_DIV, "Reg[948]= (( %x )) was in wrong state\n", tmp_swas_no_link_bk_reg948); return false; } - odm_stall_execution(10); + ODM_delay_us(10); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Change to (( %s-ant)) for testing.\n", (p_dm_swat_table->cur_antenna == MAIN_ANT) ? "MAIN" : "AUX")); + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Change to (( %s-ant)) for testing.\n", (dm_swat_table->cur_antenna == MAIN_ANT) ? "MAIN" : "AUX"); } odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel); - PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5); + PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5); return true; - } else { /* p_dm_swat_table->swas_no_link_state == 1 */ + } else { /* dm_swat_table->swas_no_link_state == 1 */ /* 1 ScanComple() is called after antenna swiched. */ /* 1 Check scan result and determine which antenna is going */ /* 1 to be used. */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" tmp_num_bss_desc= (( %d ))\n", p_mgnt_info->tmpNumBssDesc)); /* debug for Dino */ + PHYDM_DBG(dm, DBG_ANT_DIV, " tmp_num_bss_desc= (( %d ))\n", mgnt_info->tmpNumBssDesc); /* debug for Dino */ - for (index = 0; index < p_mgnt_info->tmpNumBssDesc; index++) { - p_tmp_bss_desc = &(p_mgnt_info->tmpbssDesc[index]); /* Antenna 1 */ - p_test_bss_desc = &(p_mgnt_info->bssDesc[index]); /* Antenna 2 */ + for (index = 0; index < mgnt_info->tmpNumBssDesc; index++) { + p_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* Antenna 1 */ + p_test_bss_desc = &mgnt_info->bssDesc[index]; /* Antenna 2 */ if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): ERROR!! This shall not happen.\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): ERROR!! This shall not happen.\n"); continue; } - if (p_dm_odm->support_ic_type != ODM_RTL8723B) { + if (dm->support_ic_type != ODM_RTL8723B) { if (p_tmp_bss_desc->ChannelNumber == scan_channel) { if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Compare scan entry: score++\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Compare scan entry: score++\n"); RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); + PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); score++; PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS)); } else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Compare scan entry: score--\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Compare scan entry: score--\n"); RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); + PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); score--; } else { if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) { RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("The 2nd Antenna didn't get this AP\n\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + PHYDM_DBG(dm, DBG_ANT_DIV, "The 2nd Antenna didn't get this AP\n\n"); } } } } else { /* 8723B */ if (p_tmp_bss_desc->ChannelNumber == scan_channel) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber)); + PHYDM_DBG(dm, DBG_ANT_DIV, "channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber); if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */ counter++; tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower); power_diff = power_diff + tmp_power_diff; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf); - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf); + PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf); - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff)); */ + /* PHYDM_DBG(dm,DBG_ANT_DIV, "tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff); */ if (tmp_power_diff > max_power_diff) max_power_diff = tmp_power_diff; if (tmp_power_diff < min_power_diff) min_power_diff = tmp_power_diff; - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff)); */ + /* PHYDM_DBG(dm,DBG_ANT_DIV, "max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff); */ PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS)); } else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */ counter++; tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower); power_diff = power_diff + tmp_power_diff; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf); - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf); + PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf); if (tmp_power_diff > max_power_diff) max_power_diff = tmp_power_diff; if (tmp_power_diff < min_power_diff) min_power_diff = tmp_power_diff; } else { /* Pow(Ant1) = Pow(Ant2) */ if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000)); + PHYDM_DBG(dm, DBG_ANT_DIV, "time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000); if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) { counter++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf); - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf); + PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf); min_power_diff = 0; } } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000)); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000); } } } } - if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) { - if (p_mgnt_info->NumBssDesc != 0 && score < 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("odm_sw_ant_div_check_before_link(): Using ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) { + if (mgnt_info->NumBssDesc != 0 && score < 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_sw_ant_div_check_before_link(): Using ant(%s)\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("odm_sw_ant_div_check_before_link(): Remain ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_sw_ant_div_check_before_link(): Remain ant(%s)\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT"); - if (p_dm_fat_table->rx_idle_ant == MAIN_ANT) - odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); + if (fat_tab->rx_idle_ant == MAIN_ANT) + odm_update_rx_idle_ant(dm, AUX_ANT); else - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); + odm_update_rx_idle_ant(dm, MAIN_ANT); } - if (IS_5G_WIRELESS_MODE(p_mgnt_info->dot11CurrentWirelessMode)) { - p_dm_swat_table->ant_5g = p_dm_fat_table->rx_idle_ant; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_5g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) { + dm_swat_table->ant_5g = fat_tab->rx_idle_ant; + PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); } else { - p_dm_swat_table->ant_2g = p_dm_fat_table->rx_idle_ant; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_2g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + dm_swat_table->ant_2g = fat_tab->rx_idle_ant; + PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); } - } else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + } else if (dm->support_ic_type == ODM_RTL8723B) { if (counter == 0) { - if (p_dm_odm->dm_swat_table.pre_aux_fail_detec == false) { - p_dm_odm->dm_swat_table.pre_aux_fail_detec = true; - p_dm_odm->dm_swat_table.rssi_ant_dect_result = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n")); + if (dm->dm_swat_table.pre_aux_fail_detec == false) { + dm->dm_swat_table.pre_aux_fail_detec = true; + dm->dm_swat_table.rssi_ant_dect_result = false; + PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n"); /* 3 [ Scan again ] */ odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel); - PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5); + PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5); return true; } else { /* pre_aux_fail_detec == true */ /* 2 [ Single Antenna ] */ - p_dm_odm->dm_swat_table.pre_aux_fail_detec = false; - p_dm_odm->dm_swat_table.rssi_ant_dect_result = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter=(( 0 )) , [[ Still cannot find any AP ]]\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n")); + dm->dm_swat_table.pre_aux_fail_detec = false; + dm->dm_swat_table.rssi_ant_dect_result = true; + PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Still cannot find any AP ]]\n"); + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n"); } - p_dm_odm->dm_swat_table.aux_fail_detec_counter++; + dm->dm_swat_table.aux_fail_detec_counter++; } else { - p_dm_odm->dm_swat_table.pre_aux_fail_detec = false; + dm->dm_swat_table.pre_aux_fail_detec = false; if (counter == 3) { avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff)); + PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff); } else if (counter >= 4) { avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff)); + PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff); } else { /* counter==1,2 */ avg_power_diff = power_diff / counter; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff)); + PHYDM_DBG(dm, DBG_ANT_DIV, "avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff); } /* 2 [ Retry ] */ if ((avg_power_diff >= power_target_L) && (avg_power_diff <= power_target_H)) { - p_dm_odm->dm_swat_table.retry_counter++; + dm->dm_swat_table.retry_counter++; - if (p_dm_odm->dm_swat_table.retry_counter <= 3) { - p_dm_odm->dm_swat_table.rssi_ant_dect_result = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff)); + if (dm->dm_swat_table.retry_counter <= 3) { + dm->dm_swat_table.rssi_ant_dect_result = false; + PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff); /* 3 [ Scan again ] */ odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel); - PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5); + PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5); return true; } else { - p_dm_odm->dm_swat_table.rssi_ant_dect_result = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( retry_counter > 3 ))\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n")); + dm->dm_swat_table.rssi_ant_dect_result = true; + PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Still Low confidence result ]] (( retry_counter > 3 ))\n"); + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n"); } } /* 2 [ Dual Antenna ] */ - else if ((p_mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) { - p_dm_odm->dm_swat_table.rssi_ant_dect_result = true; - if (p_dm_odm->dm_swat_table.ANTB_ON == false) { - p_dm_odm->dm_swat_table.ANTA_ON = true; - p_dm_odm->dm_swat_table.ANTB_ON = true; + else if ((mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) { + dm->dm_swat_table.rssi_ant_dect_result = true; + if (dm->dm_swat_table.ANTB_ON == false) { + dm->dm_swat_table.ANTA_ON = true; + dm->dm_swat_table.ANTB_ON = true; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Dual antenna\n")); - p_dm_odm->dm_swat_table.dual_ant_counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Dual antenna\n"); + dm->dm_swat_table.dual_ant_counter++; /* set bt coexDM from 1ant coexDM to 2ant coexDM */ BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); /* 3 [ Init antenna diversity ] */ - p_dm_odm->support_ability |= ODM_BB_ANT_DIV; - odm_ant_div_init(p_dm_odm); + dm->support_ability |= ODM_BB_ANT_DIV; + odm_ant_div_init(dm); } /* 2 [ Single Antenna ] */ else if (avg_power_diff > power_target_H) { - p_dm_odm->dm_swat_table.rssi_ant_dect_result = true; - if (p_dm_odm->dm_swat_table.ANTB_ON == true) { - p_dm_odm->dm_swat_table.ANTA_ON = true; - p_dm_odm->dm_swat_table.ANTB_ON = false; + dm->dm_swat_table.rssi_ant_dect_result = true; + if (dm->dm_swat_table.ANTB_ON == true) { + dm->dm_swat_table.ANTA_ON = true; + dm->dm_swat_table.ANTB_ON = false; /* bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */ } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n")); - p_dm_odm->dm_swat_table.single_ant_counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n"); + dm->dm_swat_table.single_ant_counter++; } } - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_result=(( %d ))\n",p_dm_odm->dm_swat_table.rssi_ant_dect_result)); */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n", - p_dm_odm->dm_swat_table.dual_ant_counter, p_dm_odm->dm_swat_table.single_ant_counter, p_dm_odm->dm_swat_table.retry_counter, p_dm_odm->dm_swat_table.aux_fail_detec_counter)); + /* PHYDM_DBG(dm,DBG_ANT_DIV, "is_result=(( %d ))\n",dm->dm_swat_table.rssi_ant_dect_result); */ + PHYDM_DBG(dm, DBG_ANT_DIV, "dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n", + dm->dm_swat_table.dual_ant_counter, dm->dm_swat_table.single_ant_counter, dm->dm_swat_table.retry_counter, dm->dm_swat_table.aux_fail_detec_counter); /* 2 recover the antenna setting */ - if (p_dm_odm->dm_swat_table.ANTB_ON == false) - odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, (p_dm_swat_table->swas_no_link_bk_reg948)); + if (dm->dm_swat_table.ANTB_ON == false) + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, (dm_swat_table->swas_no_link_bk_reg948)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_result=(( %d )), Recover Reg[948]= (( %x )) \n\n", p_dm_odm->dm_swat_table.rssi_ant_dect_result, p_dm_swat_table->swas_no_link_bk_reg948)); + PHYDM_DBG(dm, DBG_ANT_DIV, "is_result=(( %d )), Recover Reg[948]= (( %x ))\n\n", dm->dm_swat_table.rssi_ant_dect_result, dm_swat_table->swas_no_link_bk_reg948); } /* Check state reset to default and wait for next time. */ - p_dm_swat_table->swas_no_link_state = 0; - p_mgnt_info->bScanAntDetect = false; + dm_swat_table->swas_no_link_state = 0; + mgnt_info->bScanAntDetect = false; return false; } @@ -623,10 +622,10 @@ odm_sw_ant_div_check_before_link( /* 1 [3. PSD method] ========================================================== */ void odm_single_dual_antenna_detection_psd( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 channel_ori; u8 initial_gain = 0x36; u8 tone_idx; @@ -646,99 +645,99 @@ odm_single_dual_antenna_detection_psd( u32 i = 0, test_num = 8; - if (p_dm_odm->support_ic_type != ODM_RTL8723B) + if (dm->support_ic_type != ODM_RTL8723B) return; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection_psd()============>\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection_psd()============>\n"); /* 2 [ Backup Current RF/BB Settings ] */ - channel_ori = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK); - reg948 = odm_get_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD); - regb2c = odm_get_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD); - regc50 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD); - regc14 = odm_get_bb_reg(p_dm_odm, 0xc14, MASKDWORD); - reg908 = odm_get_bb_reg(p_dm_odm, 0x908, MASKDWORD); + channel_ori = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK); + reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD); + regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD); + regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD); + regc14 = odm_get_bb_reg(dm, 0xc14, MASKDWORD); + reg908 = odm_get_bb_reg(dm, 0x908, MASKDWORD); /* 2 [ setting for doing PSD function (CH4)] */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_RFMOD, BIT(24), 0); /* disable whole CCK block */ - odm_write_1byte(p_dm_odm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */ - odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */ + odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* disable whole CCK block */ + odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */ + odm_set_bb_reg(dm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */ /* PHYTXON while loop */ - odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, 0x803); - while (odm_get_bb_reg(p_dm_odm, 0xdf4, BIT(6))) { + odm_set_bb_reg(dm, 0x908, MASKDWORD, 0x803); + while (odm_get_bb_reg(dm, 0xdf4, BIT(6))) { i++; if (i > 1000000) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i)); + PHYDM_DBG(dm, DBG_ANT_DIV, "Wait in %s() more than %d times!\n", __FUNCTION__, i); break; } } - odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, initial_gain); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */ - odm_stall_execution(3000); + odm_set_bb_reg(dm, 0xc50, 0x7f, initial_gain); + odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */ + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ + odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */ + ODM_delay_us(3000); /* 2 [ Doing PSD Function in (CH4)] */ /* Antenna A */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n")); - odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x200); - odm_stall_execution(10); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH4)\n"); + odm_set_bb_reg(dm, 0x948, 0xfff, 0x200); + ODM_delay_us(10); + PHYDM_DBG(dm, DBG_ANT_DIV, "dbg\n"); for (i = 0; i < test_num; i++) { for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) { - PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_1[tone_idx], initial_gain); + PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain); /* if( PSD_report_temp>psd_report_main[tone_idx] ) */ psd_report_main[tone_idx] += PSD_report_temp; } } /* Antenna B */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n")); - odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x280); - odm_stall_execution(10); + PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH4)\n"); + odm_set_bb_reg(dm, 0x948, 0xfff, 0x280); + ODM_delay_us(10); for (i = 0; i < test_num; i++) { for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) { - PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_1[tone_idx], initial_gain); + PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain); /* if( PSD_report_temp>psd_report_aux[tone_idx] ) */ psd_report_aux[tone_idx] += PSD_report_temp; } } /* 2 [ Doing PSD Function in (CH8)] */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ - odm_stall_execution(3000); + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ + ODM_delay_us(3000); - odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, initial_gain); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */ + odm_set_bb_reg(dm, 0xc50, 0x7f, initial_gain); + odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ - odm_stall_execution(3000); + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ + ODM_delay_us(3000); /* Antenna A */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n")); - odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x200); - odm_stall_execution(10); + PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH8)\n"); + odm_set_bb_reg(dm, 0x948, 0xfff, 0x200); + ODM_delay_us(10); for (i = 0; i < test_num; i++) { for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) { - PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_2[tone_idx], initial_gain); + PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain); /* if( PSD_report_temp>psd_report_main[tone_idx] ) */ psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp; } } /* Antenna B */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n")); - odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x280); - odm_stall_execution(10); + PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH8)\n"); + odm_set_bb_reg(dm, 0x948, 0xfff, 0x280); + ODM_delay_us(10); for (i = 0; i < test_num; i++) { for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) { - PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_2[tone_idx], initial_gain); + PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain); /* if( PSD_report_temp>psd_report_aux[tone_idx] ) */ psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp; } @@ -746,70 +745,70 @@ odm_single_dual_antenna_detection_psd( /* 2 [ Calculate Result ] */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL)\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "\nMain PSD Result: (ALL)\n"); for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_main[tone_idx])); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_main[tone_idx]); main_psd_result += psd_report_main[tone_idx]; if (psd_report_main[tone_idx] > max_psd_report_main) max_psd_report_main = psd_report_main[tone_idx]; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", main_psd_result)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", max_psd_report_main)); + PHYDM_DBG(dm, DBG_ANT_DIV, "--------------------------- \nTotal_Main= (( %d ))\n", main_psd_result); + PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Main = (( %d ))\n", max_psd_report_main); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL)\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "\nAux PSD Result: (ALL)\n"); for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_aux[tone_idx])); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_aux[tone_idx]); aux_psd_result += psd_report_aux[tone_idx]; if (psd_report_aux[tone_idx] > max_psd_report_aux) max_psd_report_aux = psd_report_aux[tone_idx]; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", aux_psd_result)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", max_psd_report_aux)); + PHYDM_DBG(dm, DBG_ANT_DIV, "--------------------------- \nTotal_Aux= (( %d ))\n", aux_psd_result); + PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Aux = (( %d ))\n\n", max_psd_report_aux); /* main_psd_result=main_psd_result-max_psd_report_main; */ /* aux_psd_result=aux_psd_result-max_psd_report_aux; */ PSD_power_threshold = (main_psd_result * 7) >> 3; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", main_psd_result, aux_psd_result, PSD_power_threshold)); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", main_psd_result, aux_psd_result, PSD_power_threshold); /* 3 [ Dual Antenna ] */ if (aux_psd_result >= PSD_power_threshold) { - if (p_dm_odm->dm_swat_table.ANTB_ON == false) { - p_dm_odm->dm_swat_table.ANTA_ON = true; - p_dm_odm->dm_swat_table.ANTB_ON = true; + if (dm->dm_swat_table.ANTB_ON == false) { + dm->dm_swat_table.ANTA_ON = true; + dm->dm_swat_table.ANTB_ON = true; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Dual antenna\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Dual antenna\n"); /* set bt coexDM from 1ant coexDM to 2ant coexDM */ - /* bt_set_bt_coex_ant_num(p_adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */ + /* bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */ /* Init antenna diversity */ - p_dm_odm->support_ability |= ODM_BB_ANT_DIV; - odm_ant_div_init(p_dm_odm); + dm->support_ability |= ODM_BB_ANT_DIV; + odm_ant_div_init(dm); } /* 3 [ Single Antenna ] */ else { - if (p_dm_odm->dm_swat_table.ANTB_ON == true) { - p_dm_odm->dm_swat_table.ANTA_ON = true; - p_dm_odm->dm_swat_table.ANTB_ON = false; + if (dm->dm_swat_table.ANTB_ON == true) { + dm->dm_swat_table.ANTA_ON = true; + dm->dm_swat_table.ANTB_ON = false; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n"); } /* 2 [ Recover all parameters ] */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori); - odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ - odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, regc50); + odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori); + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ + odm_set_bb_reg(dm, 0xc50, 0x7f, regc50); - odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948); - odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c); + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948); + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c); - odm_set_bb_reg(p_dm_odm, REG_FPGA0_RFMOD, BIT(24), 1); /* enable whole CCK block */ - odm_write_1byte(p_dm_odm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */ - odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, regc14); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */ - odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, reg908); + odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* enable whole CCK block */ + odm_write_1byte(dm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */ + odm_set_bb_reg(dm, 0xC14, MASKDWORD, regc14); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */ + odm_set_bb_reg(dm, 0x908, MASKDWORD, reg908); return; @@ -818,21 +817,27 @@ odm_single_dual_antenna_detection_psd( #endif void odm_sw_ant_detect_init( - void *p_dm_void + void *dm_void ) { #if (defined(CONFIG_ANT_DETECTION)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; +#if (RTL8723B_SUPPORT == 1) + + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; - /* p_dm_swat_table->pre_antenna = MAIN_ANT; */ - /* p_dm_swat_table->cur_antenna = MAIN_ANT; */ - p_dm_swat_table->swas_no_link_state = 0; - p_dm_swat_table->pre_aux_fail_detec = false; - p_dm_swat_table->swas_no_link_bk_reg948 = 0xff; + if (dm->support_ic_type != ODM_RTL8723B) + return; - #if (CONFIG_PSD_TOOL == 1) - phydm_psd_init(p_dm_odm); + /* dm_swat_table->pre_antenna = MAIN_ANT; */ + /* dm_swat_table->cur_antenna = MAIN_ANT; */ + dm_swat_table->swas_no_link_state = 0; + dm_swat_table->pre_aux_fail_detec = false; + dm_swat_table->swas_no_link_bk_reg948 = 0xff; + + #ifdef CONFIG_PSD_TOOL + phydm_psd_init(dm); #endif #endif +#endif } diff --git a/hal/phydm/phydm_antdect.h b/hal/phydm/phydm_antdect.h index 74627fc..bf85c9b 100644 --- a/hal/phydm/phydm_antdect.h +++ b/hal/phydm/phydm_antdect.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __PHYDMANTDECT_H__ @@ -36,7 +46,7 @@ struct _ANT_DETECTED_INFO { }; -enum dm_swas_e { +enum dm_swas { antenna_a = 1, antenna_b = 2, antenna_max = 3, @@ -50,12 +60,12 @@ enum dm_swas_e { void odm_single_dual_antenna_default_setting( - void *p_dm_void + void *dm_void ); boolean odm_single_dual_antenna_detection( - void *p_dm_void, + void *dm_void, u8 mode ); @@ -65,7 +75,7 @@ odm_single_dual_antenna_detection( boolean odm_sw_ant_div_check_before_link( - void *p_dm_void + void *dm_void ); @@ -76,14 +86,14 @@ odm_sw_ant_div_check_before_link( void odm_single_dual_antenna_detection_psd( - void *p_dm_void + void *dm_void ); #endif void odm_sw_ant_detect_init( - void *p_dm_void + void *dm_void ); diff --git a/hal/phydm/phydm_antdiv.c b/hal/phydm/phydm_antdiv.c index 0d79db8..ffa3ec4 100644 --- a/hal/phydm/phydm_antdiv.c +++ b/hal/phydm/phydm_antdiv.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -26,44 +36,47 @@ * ****************************************************** */ void odm_stop_antenna_switch_dm( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; /* disable ODM antenna diversity */ - p_dm_odm->support_ability &= ~ODM_BB_ANT_DIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("STOP Antenna Diversity\n")); + dm->support_ability &= ~ODM_BB_ANT_DIV; + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + PHYDM_DBG(dm, DBG_ANT_DIV, "STOP Antenna Diversity\n"); } void phydm_enable_antenna_diversity( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - p_dm_odm->support_ability |= ODM_BB_ANT_DIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AntDiv is enabled & Re-Init AntDiv\n")); - odm_antenna_diversity_init(p_dm_odm); + dm->support_ability |= ODM_BB_ANT_DIV; + dm->antdiv_select = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "AntDiv is enabled & Re-Init AntDiv\n"); + odm_antenna_diversity_init(dm); } void odm_set_ant_config( - void *p_dm_void, + void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */ ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + if (dm->support_ic_type == ODM_RTL8723B) { if (ant_setting == 0) /* ant A*/ - odm_set_bb_reg(p_dm_odm, 0x948, MASKDWORD, 0x00000000); + odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000000); else if (ant_setting == 1) - odm_set_bb_reg(p_dm_odm, 0x948, MASKDWORD, 0x00000280); - } else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000280); + } else if (dm->support_ic_type == ODM_RTL8723D) { if (ant_setting == 0) /* ant A*/ - odm_set_bb_reg(p_dm_odm, 0x948, MASKLWORD, 0x0000); + odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0000); else if (ant_setting == 1) - odm_set_bb_reg(p_dm_odm, 0x948, MASKLWORD, 0x0280); + odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0280); } } @@ -72,112 +85,136 @@ odm_set_ant_config( void odm_sw_ant_div_rest_after_link( - void *p_dm_void + void *dm_void ) { #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; u32 i; - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { - - p_dm_swat_table->try_flag = SWAW_STEP_INIT; - p_dm_swat_table->rssi_trying = 0; - p_dm_swat_table->double_chk_flag = 0; - p_dm_fat_table->rx_idle_ant = MAIN_ANT; + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->rssi_trying = 0; + dm_swat_table->double_chk_flag = 0; + fat_tab->rx_idle_ant = MAIN_ANT; for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) - phydm_antdiv_reset_statistic(p_dm_odm, i); + phydm_antdiv_reset_statistic(dm, i); } #endif } - -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) -void -phydm_antdiv_reset_statistic( - void *p_dm_void, - u32 macid -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - - p_dm_fat_table->main_ant_sum[macid] = 0; - p_dm_fat_table->aux_ant_sum[macid] = 0; - p_dm_fat_table->main_ant_cnt[macid] = 0; - p_dm_fat_table->aux_ant_cnt[macid] = 0; - p_dm_fat_table->main_ant_sum_cck[macid] = 0; - p_dm_fat_table->aux_ant_sum_cck[macid] = 0; - p_dm_fat_table->main_ant_cnt_cck[macid] = 0; - p_dm_fat_table->aux_ant_cnt_cck[macid] = 0; -} - void odm_ant_div_on_off( - void *p_dm_void, + void *dm_void, u8 swch ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - if (p_dm_fat_table->ant_div_on_off != swch) { - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) + if (fat_tab->ant_div_on_off != swch) { + if (dm->ant_div_type == S0S1_SW_ANTDIV) return; - if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF")); - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(7), swch); - odm_set_bb_reg(p_dm_odm, 0xa00, BIT(15), swch); + if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { + PHYDM_DBG(dm, DBG_ANT_DIV, "(( Turn %s )) N-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF"); + odm_set_bb_reg(dm, 0xc50, BIT(7), swch); + odm_set_bb_reg(dm, 0xa00, BIT(15), swch); #if (RTL8723D_SUPPORT == 1) /*Mingzhi 2017-05-08*/ - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (dm->support_ic_type == ODM_RTL8723D) { if (swch == ANTDIV_ON) { - odm_set_bb_reg(p_dm_odm, 0xce0, BIT(1), 1); - odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 1); /*1:HW ctrl 0:SW ctrl*/ - } else { - odm_set_bb_reg(p_dm_odm, 0xce0, BIT(1), 0); - odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0); /*1:HW ctrl 0:SW ctrl*/ - } + odm_set_bb_reg(dm, 0xce0, BIT(1), 1); + odm_set_bb_reg(dm, 0x948, BIT(6), 1); /*1:HW ctrl 0:SW ctrl*/ + } + else{ + odm_set_bb_reg(dm, 0xce0, BIT(1), 0); + odm_set_bb_reg(dm, 0x948, BIT(6), 0); /*1:HW ctrl 0:SW ctrl*/ + } } #endif - } else if (p_dm_odm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF")); - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) { - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(7), swch); /* OFDM AntDiv function block enable */ - odm_set_bb_reg(p_dm_odm, 0xa00, BIT(15), swch); /* CCK AntDiv function block enable */ + } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { + PHYDM_DBG(dm, DBG_ANT_DIV, "(( Turn %s )) AC-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF"); + if (dm->support_ic_type & ODM_RTL8812) { + odm_set_bb_reg(dm, 0xc50, BIT(7), swch); /* OFDM AntDiv function block enable */ + odm_set_bb_reg(dm, 0xa00, BIT(15), swch); /* CCK AntDiv function block enable */ } else { - odm_set_bb_reg(p_dm_odm, 0x8D4, BIT(24), swch); /* OFDM AntDiv function block enable */ - - if ((p_dm_odm->cut_version >= ODM_CUT_C) && (p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->ant_div_type != S0S1_SW_ANTDIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF")); - odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), swch); - odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */ - } else if (p_dm_odm->support_ic_type == ODM_RTL8821C) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF")); - odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), swch); - odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */ + odm_set_bb_reg(dm, 0x8D4, BIT(24), swch); /* OFDM AntDiv function block enable */ + + if ((dm->cut_version >= ODM_CUT_C) && (dm->support_ic_type == ODM_RTL8821) && (dm->ant_div_type != S0S1_SW_ANTDIV)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF"); + odm_set_bb_reg(dm, 0x800, BIT(25), swch); + odm_set_bb_reg(dm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */ + } else if (dm->support_ic_type == ODM_RTL8821C) { + PHYDM_DBG(dm, DBG_ANT_DIV, "(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF"); + odm_set_bb_reg(dm, 0x800, BIT(25), swch); + odm_set_bb_reg(dm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */ } } } } - p_dm_fat_table->ant_div_on_off = swch; + fat_tab->ant_div_on_off = swch; + +} + +void +odm_tx_by_tx_desc_or_reg( + void *dm_void, + u8 swch +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 enable; + + if (fat_tab->b_fix_tx_ant == NO_FIX_TX_ANT) + enable = (swch == TX_BY_DESC) ? 1 : 0; + else + enable = 0;/*Force TX by Reg*/ + + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) { + if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) + odm_set_bb_reg(dm, 0x80c, BIT(21), enable); + else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) + odm_set_bb_reg(dm, 0x900, BIT(18), enable); + + PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv] TX_Ant_BY (( %s ))\n", (enable == TX_BY_DESC) ? "DESC" : "REG"); + } +} +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) +void +phydm_antdiv_reset_statistic( + void *dm_void, + u32 macid +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + fat_tab->main_ant_sum[macid] = 0; + fat_tab->aux_ant_sum[macid] = 0; + fat_tab->main_ant_cnt[macid] = 0; + fat_tab->aux_ant_cnt[macid] = 0; + fat_tab->main_ant_sum_cck[macid] = 0; + fat_tab->aux_ant_sum_cck[macid] = 0; + fat_tab->main_ant_cnt_cck[macid] = 0; + fat_tab->aux_ant_cnt_cck[macid] = 0; } void phydm_fast_training_enable( - void *p_dm_void, + void *dm_void, u8 swch ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 enable; if (swch == FAT_ON) @@ -185,80 +222,53 @@ phydm_fast_training_enable( else enable = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fast ant Training_en = ((%d))\n", enable)); + PHYDM_DBG(dm, DBG_ANT_DIV, "Fast ant Training_en = ((%d))\n", enable); - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - odm_set_bb_reg(p_dm_odm, 0xe08, BIT(16), enable); /*enable fast training*/ + if (dm->support_ic_type == ODM_RTL8188E) { + odm_set_bb_reg(dm, 0xe08, BIT(16), enable); /*enable fast training*/ /**/ - } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_bb_reg(p_dm_odm, 0xB34, BIT(28), enable); /*enable fast training (path-A)*/ - /*odm_set_bb_reg(p_dm_odm, 0xB34, BIT(29), enable);*/ /*enable fast training (path-B)*/ - } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) { - odm_set_bb_reg(p_dm_odm, 0x900, BIT(19), enable); /*enable fast training */ + } else if (dm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(dm, 0xB34, BIT(28), enable); /*enable fast training (path-A)*/ + /*odm_set_bb_reg(dm, 0xB34, BIT(29), enable);*/ /*enable fast training (path-B)*/ + } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) { + odm_set_bb_reg(dm, 0x900, BIT(19), enable); /*enable fast training */ /**/ } } void phydm_keep_rx_ack_ant_by_tx_ant_time( - void *p_dm_void, + void *dm_void, u32 time ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/ - if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { - - odm_set_bb_reg(p_dm_odm, 0xE20, BIT(23) | BIT(22) | BIT(21) | BIT(20), time); + if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { + odm_set_bb_reg(dm, 0xE20, BIT(23) | BIT(22) | BIT(21) | BIT(20), time); /**/ - } else if (p_dm_odm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { - - odm_set_bb_reg(p_dm_odm, 0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), time); + } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { + odm_set_bb_reg(dm, 0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), time); /**/ } } -void -odm_tx_by_tx_desc_or_reg( - void *p_dm_void, - u8 swch -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u8 enable; - - if (p_dm_fat_table->b_fix_tx_ant == NO_FIX_TX_ANT) - enable = (swch == TX_BY_DESC) ? 1 : 0; - else - enable = 0;/*Force TX by Reg*/ - - if (p_dm_odm->ant_div_type != CGCS_RX_HW_ANTDIV) { - if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) - odm_set_bb_reg(p_dm_odm, 0x80c, BIT(21), enable); - else if (p_dm_odm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) - odm_set_bb_reg(p_dm_odm, 0x900, BIT(18), enable); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv] TX_Ant_BY (( %s ))\n", (enable == TX_BY_DESC) ? "DESC" : "REG")); - } -} - void odm_update_rx_idle_ant( - void *p_dm_void, + void *dm_void, u8 ant ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; u32 default_ant, optional_ant, value32, default_tx_ant; - if (p_dm_fat_table->rx_idle_ant != ant) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + if (fat_tab->rx_idle_ant != ant) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); - if (!(p_dm_odm->support_ic_type & ODM_RTL8723B)) - p_dm_fat_table->rx_idle_ant = ant; + if (!(dm->support_ic_type & ODM_RTL8723B)) + fat_tab->rx_idle_ant = ant; if (ant == MAIN_ANT) { default_ant = ANT1_2G; @@ -268,47 +278,57 @@ odm_update_rx_idle_ant( optional_ant = ANT1_2G; } - if (p_dm_fat_table->b_fix_tx_ant != NO_FIX_TX_ANT) - default_tx_ant = (p_dm_fat_table->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1; + if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT) + default_tx_ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1; else default_tx_ant = default_ant; - if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(5) | BIT4 | BIT3, default_ant); /* Default RX */ - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(8) | BIT7 | BIT6, optional_ant); /* Optional RX */ - odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, default_ant); /* Default TX */ + if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { + if (dm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(dm, 0xB38, BIT(5) | BIT(4) | BIT(3), default_ant); /* Default RX */ + odm_set_bb_reg(dm, 0xB38, BIT(8) | BIT(7) | BIT(6), optional_ant); /* Optional RX */ + odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /* Default TX */ } #if (RTL8723B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - - value32 = odm_get_bb_reg(p_dm_odm, 0x948, 0xFFF); + else if (dm->support_ic_type == ODM_RTL8723B) { + value32 = odm_get_bb_reg(dm, 0x948, 0xFFF); if (value32 != 0x280) - odm_update_rx_idle_ant_8723b(p_dm_odm, ant, default_ant, optional_ant); + odm_update_rx_idle_ant_8723b(dm, ant, default_ant, optional_ant); else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n"); } #endif + #if (RTL8723D_SUPPORT == 1) /*Mingzhi 2017-05-08*/ - else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - phydm_set_tx_ant_pwr_8723d(p_dm_odm, ant); - odm_update_rx_idle_ant_8723d(p_dm_odm, ant, default_ant, optional_ant); + else if (dm->support_ic_type == ODM_RTL8723D) { + phydm_set_tx_ant_pwr_8723d(dm, ant); + odm_update_rx_idle_ant_8723d(dm, ant, default_ant, optional_ant); + } -#endif +#endif + else { /*8188E & 8188F*/ +/* + if (dm->support_ic_type == ODM_RTL8723D) { +#if (RTL8723D_SUPPORT == 1) + phydm_set_tx_ant_pwr_8723d(dm, ant); +#endif + } +*/ #if (RTL8188F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - phydm_update_rx_idle_antenna_8188F(p_dm_odm, default_ant); + if (dm->support_ic_type == ODM_RTL8188F) { + phydm_update_rx_idle_antenna_8188F(dm, default_ant); + /**/ } #endif - odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT4 | BIT3, default_ant); /*Default RX*/ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT7 | BIT6, optional_ant); /*Optional RX*/ - odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, default_tx_ant); /*Default TX*/ + odm_set_bb_reg(dm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/ + odm_set_bb_reg(dm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/ + odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_tx_ant); /*Default TX*/ } - } else if (p_dm_odm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { - u16 value16 = odm_read_2byte(p_dm_odm, ODM_REG_TRMUX_11AC + 2); + } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { + u16 value16 = odm_read_2byte(dm, ODM_REG_TRMUX_11AC + 2); /* */ /* 2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt */ /* incorrect 0xc08 bit0-15 .We still not know why it is changed. */ @@ -317,43 +337,63 @@ odm_update_rx_idle_ant( value16 |= ((u16)default_ant << 3); value16 |= ((u16)optional_ant << 6); value16 |= ((u16)default_ant << 9); - odm_write_2byte(p_dm_odm, ODM_REG_TRMUX_11AC + 2, value16); + odm_write_2byte(dm, ODM_REG_TRMUX_11AC + 2, value16); #if 0 - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(21) | BIT20 | BIT19, default_ant); /* Default RX */ - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(24) | BIT23 | BIT22, optional_ant); /* Optional RX */ - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(27) | BIT26 | BIT25, default_ant); /* Default TX */ + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(21) | BIT20 | BIT19, default_ant); /* Default RX */ + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(24) | BIT23 | BIT22, optional_ant); /* Optional RX */ + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(27) | BIT26 | BIT25, default_ant); /* Default TX */ #endif } - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(7) | BIT6, default_tx_ant); /*PathA Resp Tx*/ + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) { + odm_set_mac_reg(dm, 0x6D8, 0x7, default_tx_ant); /*PathA Resp Tx*/ + /**/ + } else if (dm->support_ic_type == ODM_RTL8188E) { + odm_set_mac_reg(dm, 0x6D8, BIT(7) | BIT(6), default_tx_ant); /*PathA Resp Tx*/ /**/ } else { - odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(10) | BIT9 | BIT8, default_tx_ant); /*PathA Resp Tx*/ + odm_set_mac_reg(dm, 0x6D8, BIT(10) | BIT(9) | BIT(8), default_tx_ant); /*PathA Resp Tx*/ /**/ } - } else { /* p_dm_fat_table->rx_idle_ant == ant */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Stay in Ori-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - p_dm_fat_table->rx_idle_ant = ant; + } else { /* fat_tab->rx_idle_ant == ant */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Stay in Ori-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + fat_tab->rx_idle_ant = ant; + } +} + +void +phydm_set_antdiv_val( + void *dm_void, + u32 *val_buf, + u8 val_len +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (val_len != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[Error][antdiv]Need val_len=1\n"); + return; } + + odm_update_rx_idle_ant(dm, (u8)(*val_buf)); } void odm_update_tx_ant( - void *p_dm_void, + void *dm_void, u8 ant, u32 mac_id ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; u8 tx_ant; - if (p_dm_fat_table->b_fix_tx_ant != NO_FIX_TX_ANT) - ant = (p_dm_fat_table->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT; + if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT) + ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT; - if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) + if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) tx_ant = ant; else { if (ant == MAIN_ANT) @@ -362,12 +402,12 @@ odm_update_tx_ant( tx_ant = ANT2_2G; } - p_dm_fat_table->antsel_a[mac_id] = tx_ant & BIT(0); - p_dm_fat_table->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1; - p_dm_fat_table->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2; + fat_tab->antsel_a[mac_id] = tx_ant & BIT(0); + fat_tab->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1; + fat_tab->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Set TX-DESC value]: mac_id:(( %d )), tx_ant = (( %s ))\n", mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",p_dm_fat_table->antsel_c[mac_id] , p_dm_fat_table->antsel_b[mac_id] , p_dm_fat_table->antsel_a[mac_id] )); */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[Set TX-DESC value]: mac_id:(( %d )), tx_ant = (( %s ))\n", mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + /* PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=(( 3'b%d%d%d ))\n",fat_tab->antsel_c[mac_id] , fat_tab->antsel_b[mac_id] , fat_tab->antsel_a[mac_id] ); */ } @@ -376,25 +416,25 @@ odm_update_tx_ant( void odm_bdc_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[ BDC Initialization......]\n")); - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - p_dm_bdc_table->bdc_mode = BDC_MODE_NULL; - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->bd_ccoex_type_wbfer = 0; - p_dm_odm->bdc_holdstate = 0xff; - - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_bb_reg(p_dm_odm, 0xd7c, 0x0FFFFFFF, 0x1081008); - odm_set_bb_reg(p_dm_odm, 0xd80, 0x0FFFFFFF, 0); - } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { - odm_set_bb_reg(p_dm_odm, 0x9b0, 0x0FFFFFFF, 0x1081008); /* 0x9b0[30:0] = 01081008 */ - odm_set_bb_reg(p_dm_odm, 0x9b4, 0x0FFFFFFF, 0); /* 0x9b4[31:0] = 00000000 */ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "\n[ BDC Initialization......]\n"); + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + dm_bdc_table->bdc_mode = BDC_MODE_NULL; + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->bd_ccoex_type_wbfer = 0; + dm->bdc_holdstate = 0xff; + + if (dm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(dm, 0xd7c, 0x0FFFFFFF, 0x1081008); + odm_set_bb_reg(dm, 0xd80, 0x0FFFFFFF, 0); + } else if (dm->support_ic_type == ODM_RTL8812) { + odm_set_bb_reg(dm, 0x9b0, 0x0FFFFFFF, 0x1081008); /* 0x9b0[30:0] = 01081008 */ + odm_set_bb_reg(dm, 0x9b4, 0x0FFFFFFF, 0); /* 0x9b4[31:0] = 00000000 */ } } @@ -402,121 +442,119 @@ odm_bdc_init( void odm_CSI_on_off( - void *p_dm_void, + void *dm_void, u8 CSI_en ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (CSI_en == CSI_ON) { - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_mac_reg(p_dm_odm, 0xd84, BIT(11), 1); /* 0xd84[11]=1 */ - } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { - odm_set_mac_reg(p_dm_odm, 0x9b0, BIT(31), 1); /* 0x9b0[31]=1 */ - } + if (dm->support_ic_type == ODM_RTL8192E) + odm_set_mac_reg(dm, 0xd84, BIT(11), 1); /* 0xd84[11]=1 */ + else if (dm->support_ic_type == ODM_RTL8812) + odm_set_mac_reg(dm, 0x9b0, BIT(31), 1); /* 0x9b0[31]=1 */ } else if (CSI_en == CSI_OFF) { - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_mac_reg(p_dm_odm, 0xd84, BIT(11), 0); /* 0xd84[11]=0 */ - } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { - odm_set_mac_reg(p_dm_odm, 0x9b0, BIT(31), 0); /* 0x9b0[31]=0 */ - } + if (dm->support_ic_type == ODM_RTL8192E) + odm_set_mac_reg(dm, 0xd84, BIT(11), 0); /* 0xd84[11]=0 */ + else if (dm->support_ic_type == ODM_RTL8812) + odm_set_mac_reg(dm, 0x9b0, BIT(31), 0); /* 0x9b0[31]=0 */ } } void odm_bd_ccoex_type_with_bfer_client( - void *p_dm_void, + void *dm_void, u8 swch ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; u8 bd_ccoex_type_wbfer; if (swch == DIVON_CSIOFF) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 1] {DIV,CSI} ={1,0}\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[BDCcoexType: 1] {DIV,CSI} ={1,0}\n"); bd_ccoex_type_wbfer = 1; - if (bd_ccoex_type_wbfer != p_dm_bdc_table->bd_ccoex_type_wbfer) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - odm_CSI_on_off(p_dm_odm, CSI_OFF); - p_dm_bdc_table->bd_ccoex_type_wbfer = 1; + if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) { + odm_ant_div_on_off(dm, ANTDIV_ON); + odm_CSI_on_off(dm, CSI_OFF); + dm_bdc_table->bd_ccoex_type_wbfer = 1; } } else if (swch == DIVOFF_CSION) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 2] {DIV,CSI} ={0,1}\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[BDCcoexType: 2] {DIV,CSI} ={0,1}\n"); bd_ccoex_type_wbfer = 2; - if (bd_ccoex_type_wbfer != p_dm_bdc_table->bd_ccoex_type_wbfer) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - odm_CSI_on_off(p_dm_odm, CSI_ON); - p_dm_bdc_table->bd_ccoex_type_wbfer = 2; + if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_CSI_on_off(dm, CSI_ON); + dm_bdc_table->bd_ccoex_type_wbfer = 2; } } } void odm_bf_ant_div_mode_arbitration( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; u8 current_bdc_mode; #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "\n"); /* 2 mode 1 */ - if ((p_dm_bdc_table->num_txbfee_client != 0) && (p_dm_bdc_table->num_txbfer_client == 0)) { + if ((dm_bdc_table->num_txbfee_client != 0) && (dm_bdc_table->num_txbfer_client == 0)) { current_bdc_mode = BDC_MODE_1; - if (current_bdc_mode != p_dm_bdc_table->bdc_mode) { - p_dm_bdc_table->bdc_mode = BDC_MODE_1; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); - p_dm_bdc_table->bdc_rx_idle_update_counter = 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode1 ))\n")); + if (current_bdc_mode != dm_bdc_table->bdc_mode) { + dm_bdc_table->bdc_mode = BDC_MODE_1; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + dm_bdc_table->bdc_rx_idle_update_counter = 1; + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode1 ))\n"); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance mode] : (( Mode1 ))\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv + BF coextance mode] : (( Mode1 ))\n"); } /* 2 mode 2 */ - else if ((p_dm_bdc_table->num_txbfee_client == 0) && (p_dm_bdc_table->num_txbfer_client != 0)) { + else if ((dm_bdc_table->num_txbfee_client == 0) && (dm_bdc_table->num_txbfer_client != 0)) { current_bdc_mode = BDC_MODE_2; - if (current_bdc_mode != p_dm_bdc_table->bdc_mode) { - p_dm_bdc_table->bdc_mode = BDC_MODE_2; - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - p_dm_bdc_table->bdc_try_flag = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode2 ))\n")); + if (current_bdc_mode != dm_bdc_table->bdc_mode) { + dm_bdc_table->bdc_mode = BDC_MODE_2; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + dm_bdc_table->bdc_try_flag = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode2 ))\n"); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance mode] : (( Mode2 ))\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv + BF coextance mode] : (( Mode2 ))\n"); } /* 2 mode 3 */ - else if ((p_dm_bdc_table->num_txbfee_client != 0) && (p_dm_bdc_table->num_txbfer_client != 0)) { + else if ((dm_bdc_table->num_txbfee_client != 0) && (dm_bdc_table->num_txbfer_client != 0)) { current_bdc_mode = BDC_MODE_3; - if (current_bdc_mode != p_dm_bdc_table->bdc_mode) { - p_dm_bdc_table->bdc_mode = BDC_MODE_3; - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->bdc_rx_idle_update_counter = 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode3 ))\n")); + if (current_bdc_mode != dm_bdc_table->bdc_mode) { + dm_bdc_table->bdc_mode = BDC_MODE_3; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->bdc_rx_idle_update_counter = 1; + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode3 ))\n"); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance mode] : (( Mode3 ))\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv + BF coextance mode] : (( Mode3 ))\n"); } /* 2 mode 4 */ - else if ((p_dm_bdc_table->num_txbfee_client == 0) && (p_dm_bdc_table->num_txbfer_client == 0)) { + else if ((dm_bdc_table->num_txbfee_client == 0) && (dm_bdc_table->num_txbfer_client == 0)) { current_bdc_mode = BDC_MODE_4; - if (current_bdc_mode != p_dm_bdc_table->bdc_mode) { - p_dm_bdc_table->bdc_mode = BDC_MODE_4; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode4 ))\n")); + if (current_bdc_mode != dm_bdc_table->bdc_mode) { + dm_bdc_table->bdc_mode = BDC_MODE_4; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode4 ))\n"); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance mode] : (( Mode4 ))\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv + BF coextance mode] : (( Mode4 ))\n"); } #endif @@ -524,45 +562,45 @@ odm_bf_ant_div_mode_arbitration( void odm_div_train_state_setting( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE]\n")); - p_dm_bdc_table->bdc_try_counter = 2; - p_dm_bdc_table->bdc_try_flag = 1; - p_dm_bdc_table->BDC_state = bdc_bfer_train_state; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE]\n"); + dm_bdc_table->bdc_try_counter = 2; + dm_bdc_table->bdc_try_flag = 1; + dm_bdc_table->BDC_state = bdc_bfer_train_state; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); } void odm_bd_ccoex_bfee_rx_div_arbitration( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; boolean stop_bf_flag; u8 bdc_active_mode; #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BFee, num_BFer, num_client} = (( %d , %d , %d))\n", p_dm_bdc_table->num_txbfee_client, p_dm_bdc_table->num_txbfer_client, p_dm_bdc_table->num_client)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BF_tars, num_DIV_tars } = (( %d , %d ))\n", p_dm_bdc_table->num_bf_tar, p_dm_bdc_table->num_div_tar)); + PHYDM_DBG(dm, DBG_ANT_DIV, "***{ num_BFee, num_BFer, num_client} = (( %d , %d , %d))\n", dm_bdc_table->num_txbfee_client, dm_bdc_table->num_txbfer_client, dm_bdc_table->num_client); + PHYDM_DBG(dm, DBG_ANT_DIV, "***{ num_BF_tars, num_DIV_tars } = (( %d , %d ))\n", dm_bdc_table->num_bf_tar, dm_bdc_table->num_div_tar); /* 2 [ MIB control ] */ - if (p_dm_odm->bdc_holdstate == 2) { - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); - p_dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ BF STATE]\n")); + if (dm->bdc_holdstate == 2) { + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ BF STATE]\n"); return; - } else if (p_dm_odm->bdc_holdstate == 1) { - p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE]\n")); + } else if (dm->bdc_holdstate == 1) { + dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n"); return; } @@ -571,190 +609,189 @@ odm_bd_ccoex_bfee_rx_div_arbitration( /* 2 mode 2 & 3 */ - if (p_dm_bdc_table->bdc_mode == BDC_MODE_2 || p_dm_bdc_table->bdc_mode == BDC_MODE_3) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n{ Try_flag, Try_counter } = { %d , %d }\n", p_dm_bdc_table->bdc_try_flag, p_dm_bdc_table->bdc_try_counter)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDCcoexType = (( %d )) \n\n", p_dm_bdc_table->bd_ccoex_type_wbfer)); + if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) { + PHYDM_DBG(dm, DBG_ANT_DIV, "\n{ Try_flag, Try_counter } = { %d , %d }\n", dm_bdc_table->bdc_try_flag, dm_bdc_table->bdc_try_counter); + PHYDM_DBG(dm, DBG_ANT_DIV, "BDCcoexType = (( %d ))\n\n", dm_bdc_table->bd_ccoex_type_wbfer); /* All Client have Bfer-Cap------------------------------- */ - if (p_dm_bdc_table->num_txbfer_client == p_dm_bdc_table->num_client) { /* BFer STA Only?: yes */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( Yes ))\n")); - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); + if (dm_bdc_table->num_txbfer_client == dm_bdc_table->num_client) { /* BFer STA Only?: yes */ + PHYDM_DBG(dm, DBG_ANT_DIV, "BFer STA only? (( Yes ))\n"); + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); return; } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( No ))\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "BFer STA only? (( No ))\n"); /* */ - if (p_dm_bdc_table->is_all_bf_sta_idle == false && p_dm_bdc_table->is_all_div_sta_idle == true) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All DIV-STA are idle, but BF-STA not\n")); - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->BDC_state = bdc_bfer_train_state; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); + if (dm_bdc_table->is_all_bf_sta_idle == false && dm_bdc_table->is_all_div_sta_idle == true) { + PHYDM_DBG(dm, DBG_ANT_DIV, "All DIV-STA are idle, but BF-STA not\n"); + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = bdc_bfer_train_state; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); return; - } else if (p_dm_bdc_table->is_all_bf_sta_idle == true && p_dm_bdc_table->is_all_div_sta_idle == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All BF-STA are idle, but DIV-STA not\n")); - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + } else if (dm_bdc_table->is_all_bf_sta_idle == true && dm_bdc_table->is_all_div_sta_idle == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "All BF-STA are idle, but DIV-STA not\n"); + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); return; } /* Select active mode-------------------------------------- */ - if (p_dm_bdc_table->num_bf_tar == 0) { /* Selsect_1, Selsect_2 */ - if (p_dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 1 ))\n")); - p_dm_bdc_table->bdc_active_mode = 1; + if (dm_bdc_table->num_bf_tar == 0) { /* Selsect_1, Selsect_2 */ + if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */ + PHYDM_DBG(dm, DBG_ANT_DIV, "Select active mode (( 1 ))\n"); + dm_bdc_table->bdc_active_mode = 1; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 2 ))\n")); - p_dm_bdc_table->bdc_active_mode = 2; + PHYDM_DBG(dm, DBG_ANT_DIV, "Select active mode (( 2 ))\n"); + dm_bdc_table->bdc_active_mode = 2; } - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); return; } else { /* num_bf_tar > 0 */ - if (p_dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 3 ))\n")); - p_dm_bdc_table->bdc_active_mode = 3; - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->BDC_state = bdc_bfer_train_state; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); + if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */ + PHYDM_DBG(dm, DBG_ANT_DIV, "Select active mode (( 3 ))\n"); + dm_bdc_table->bdc_active_mode = 3; + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = bdc_bfer_train_state; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); return; } else { /* Selsect_4 */ bdc_active_mode = 4; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 4 ))\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "Select active mode (( 4 ))\n"); - if (bdc_active_mode != p_dm_bdc_table->bdc_active_mode) { - p_dm_bdc_table->bdc_active_mode = 4; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to active mode (( 4 )) & return!!!\n")); + if (bdc_active_mode != dm_bdc_table->bdc_active_mode) { + dm_bdc_table->bdc_active_mode = 4; + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to active mode (( 4 )) & return!!!\n"); return; } } } #if 1 - if (p_dm_odm->bdc_holdstate == 0xff) { - p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE]\n")); + if (dm->bdc_holdstate == 0xff) { + dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n"); return; } #endif /* Does Client number changed ? ------------------------------- */ - if (p_dm_bdc_table->num_client != p_dm_bdc_table->pre_num_client) { - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE ))\n")); + if (dm_bdc_table->num_client != dm_bdc_table->pre_num_client) { + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE ))\n"); } - p_dm_bdc_table->pre_num_client = p_dm_bdc_table->num_client; + dm_bdc_table->pre_num_client = dm_bdc_table->num_client; - if (p_dm_bdc_table->bdc_try_flag == 0) { + if (dm_bdc_table->bdc_try_flag == 0) { /* 2 DIV_TRAIN_STATE (mode 2-0) */ - if (p_dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE) - odm_div_train_state_setting(p_dm_odm); + if (dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE) + odm_div_train_state_setting(dm); /* 2 BFer_TRAIN_STATE (mode 2-1) */ - else if (p_dm_bdc_table->BDC_state == bdc_bfer_train_state) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-1. BFer_TRAIN_STATE ]*****\n")); + else if (dm_bdc_table->BDC_state == bdc_bfer_train_state) { + PHYDM_DBG(dm, DBG_ANT_DIV, "*****[2-1. BFer_TRAIN_STATE ]*****\n"); - /* if(p_dm_bdc_table->num_bf_tar==0) */ + /* if(dm_bdc_table->num_bf_tar==0) */ /* { */ - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n")); */ - /* odm_div_train_state_setting( p_dm_odm); */ + /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n"); */ + /* odm_div_train_state_setting( dm); */ /* } */ /* else */ /* num_bf_tar != 0 */ /* { */ - p_dm_bdc_table->bdc_try_counter = 2; - p_dm_bdc_table->bdc_try_flag = 1; - p_dm_bdc_table->BDC_state = BDC_DECISION_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n")); + dm_bdc_table->bdc_try_counter = 2; + dm_bdc_table->bdc_try_flag = 1; + dm_bdc_table->BDC_state = BDC_DECISION_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + PHYDM_DBG(dm, DBG_ANT_DIV, "BF_tars exist? : (( Yes )), [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n"); /* } */ } /* 2 DECISION_STATE (mode 2-2) */ - else if (p_dm_bdc_table->BDC_state == BDC_DECISION_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-2. DECISION_STATE]*****\n")); - /* if(p_dm_bdc_table->num_bf_tar==0) */ + else if (dm_bdc_table->BDC_state == BDC_DECISION_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "*****[2-2. DECISION_STATE]*****\n"); + /* if(dm_bdc_table->num_bf_tar==0) */ /* { */ /* ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */ - /* odm_div_train_state_setting( p_dm_odm); */ + /* odm_div_train_state_setting( dm); */ /* } */ /* else */ /* num_bf_tar != 0 */ /* { */ - if (p_dm_bdc_table->BF_pass == false || p_dm_bdc_table->DIV_pass == false) + if (dm_bdc_table->BF_pass == false || dm_bdc_table->DIV_pass == false) stop_bf_flag = true; else stop_bf_flag = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, stop_bf_flag } = { %d, %d, %d }\n", p_dm_bdc_table->BF_pass, p_dm_bdc_table->DIV_pass, stop_bf_flag)); + PHYDM_DBG(dm, DBG_ANT_DIV, "BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, stop_bf_flag } = { %d, %d, %d }\n", dm_bdc_table->BF_pass, dm_bdc_table->DIV_pass, stop_bf_flag); if (stop_bf_flag == true) { /* DIV_en */ - p_dm_bdc_table->bdc_hold_counter = 10; /* 20 */ - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); - p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ stop_bf_flag= ((true)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n")); + dm_bdc_table->bdc_hold_counter = 10; /* 20 */ + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ stop_bf_flag= ((true)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n"); } else { /* BF_en */ - p_dm_bdc_table->bdc_hold_counter = 10; /* 20 */ - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); - p_dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[stop_bf_flag= ((false)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n")); + dm_bdc_table->bdc_hold_counter = 10; /* 20 */ + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "[stop_bf_flag= ((false)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n"); } /* } */ } /* 2 BF-HOLD_STATE (mode 2-3) */ - else if (p_dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-3. BF_HOLD_STATE ]*****\n")); + else if (dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "*****[2-3. BF_HOLD_STATE ]*****\n"); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bdc_hold_counter = (( %d ))\n", p_dm_bdc_table->bdc_hold_counter)); + PHYDM_DBG(dm, DBG_ANT_DIV, "bdc_hold_counter = (( %d ))\n", dm_bdc_table->bdc_hold_counter); - if (p_dm_bdc_table->bdc_hold_counter == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); - odm_div_train_state_setting(p_dm_odm); + if (dm_bdc_table->bdc_hold_counter == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); + odm_div_train_state_setting(dm); } else { - p_dm_bdc_table->bdc_hold_counter--; + dm_bdc_table->bdc_hold_counter--; - /* if(p_dm_bdc_table->num_bf_tar==0) */ + /* if(dm_bdc_table->num_bf_tar==0) */ /* { */ - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */ - /* odm_div_train_state_setting( p_dm_odm); */ + /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); */ + /* odm_div_train_state_setting( dm); */ /* } */ /* else */ /* num_bf_tar != 0 */ /* { */ - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes ))\n")); */ - p_dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n")); + /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( Yes ))\n"); */ + dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n"); /* } */ } } /* 2 DIV-HOLD_STATE (mode 2-4) */ - else if (p_dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-4. DIV_HOLD_STATE ]*****\n")); + else if (dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "*****[2-4. DIV_HOLD_STATE ]*****\n"); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bdc_hold_counter = (( %d ))\n", p_dm_bdc_table->bdc_hold_counter)); + PHYDM_DBG(dm, DBG_ANT_DIV, "bdc_hold_counter = (( %d ))\n", dm_bdc_table->bdc_hold_counter); - if (p_dm_bdc_table->bdc_hold_counter == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); - odm_div_train_state_setting(p_dm_odm); + if (dm_bdc_table->bdc_hold_counter == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); + odm_div_train_state_setting(dm); } else { - p_dm_bdc_table->bdc_hold_counter--; - p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n")); + dm_bdc_table->bdc_hold_counter--; + dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n"); } } - } else if (p_dm_bdc_table->bdc_try_flag == 1) { + } else if (dm_bdc_table->bdc_try_flag == 1) { /* 2 Set Training counter */ - if (p_dm_bdc_table->bdc_try_counter > 1) { - p_dm_bdc_table->bdc_try_counter--; - if (p_dm_bdc_table->bdc_try_counter == 1) - p_dm_bdc_table->bdc_try_flag = 0; + if (dm_bdc_table->bdc_try_counter > 1) { + dm_bdc_table->bdc_try_counter--; + if (dm_bdc_table->bdc_try_counter == 1) + dm_bdc_table->bdc_try_flag = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training !!\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "Training !!\n"); /* return ; */ } @@ -762,7 +799,7 @@ odm_bd_ccoex_bfee_rx_div_arbitration( } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[end]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "\n[end]\n"); #endif /* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ @@ -782,176 +819,176 @@ odm_bd_ccoex_bfee_rx_div_arbitration( void odm_rx_hw_ant_div_init_88e( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 value32; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; #if 0 - if (*(p_dm_odm->p_mp_mode) == true) { - odm_set_bb_reg(p_dm_odm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */ - odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* 1:CG, 0:CS */ + if (*(dm->mp_mode) == true) { + odm_set_bb_reg(dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* 1:CG, 0:CS */ return; } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***8188E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n"); /* MAC setting */ - value32 = odm_get_mac_reg(p_dm_odm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD); - odm_set_mac_reg(p_dm_odm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD); + odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ /* Pin Settings */ - odm_set_bb_reg(p_dm_odm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT8, 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ - odm_set_bb_reg(p_dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ - odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ - odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */ + odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ + odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */ /* OFDM Settings */ - odm_set_bb_reg(p_dm_odm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); + odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); /* CCK Settings */ - odm_set_bb_reg(p_dm_odm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ - odm_set_bb_reg(p_dm_odm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001); /* antenna mapping table */ + odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001); /* antenna mapping table */ - p_dm_fat_table->enable_ctrl_frame_antdiv = 1; + fat_tab->enable_ctrl_frame_antdiv = 1; } void odm_trx_hw_ant_div_init_88e( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 value32; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; #if 0 - if (*(p_dm_odm->p_mp_mode) == true) { - odm_set_bb_reg(p_dm_odm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */ - odm_set_bb_reg(p_dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT4 | BIT3, 0); /* Default RX (0/1) */ + if (*(dm->mp_mode) == true) { + odm_set_bb_reg(dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */ + odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT4 | BIT3, 0); /* Default RX (0/1) */ return; } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV (SPDT)]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***8188E AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV (SPDT)]\n"); /* MAC setting */ - value32 = odm_get_mac_reg(p_dm_odm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD); - odm_set_mac_reg(p_dm_odm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD); + odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ /* Pin Settings */ - odm_set_bb_reg(p_dm_odm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT8, 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ - odm_set_bb_reg(p_dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ - odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ - odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */ + odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ + odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */ /* OFDM Settings */ - odm_set_bb_reg(p_dm_odm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); + odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); /* CCK Settings */ - odm_set_bb_reg(p_dm_odm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ /* antenna mapping table */ - if (!p_dm_odm->is_mp_chip) { /* testchip */ - odm_set_bb_reg(p_dm_odm, ODM_REG_RX_DEFUALT_A_11N, BIT(10) | BIT9 | BIT8, 1); /* Reg858[10:8]=3'b001 */ - odm_set_bb_reg(p_dm_odm, ODM_REG_RX_DEFUALT_A_11N, BIT(13) | BIT12 | BIT11, 2); /* Reg858[13:11]=3'b010 */ + if (!dm->is_mp_chip) { /* testchip */ + odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */ + odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */ } else /* MPchip */ - odm_set_bb_reg(p_dm_odm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/ + odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/ - p_dm_fat_table->enable_ctrl_frame_antdiv = 1; + fat_tab->enable_ctrl_frame_antdiv = 1; } #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) void odm_smart_hw_ant_div_init_88e( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 value32, i; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***8188E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n"); #if 0 - if (*(p_dm_odm->p_mp_mode) == true) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("p_dm_odm->ant_div_type: %d\n", p_dm_odm->ant_div_type)); + if (*(dm->mp_mode) == true) { + PHYDM_DBG(dm, ODM_COMP_INIT, "dm->ant_div_type: %d\n", dm->ant_div_type); return; } #endif - p_dm_fat_table->train_idx = 0; - p_dm_fat_table->fat_state = FAT_PREPARE_STATE; + fat_tab->train_idx = 0; + fat_tab->fat_state = FAT_PREPARE_STATE; - p_dm_odm->fat_comb_a = 5; - p_dm_odm->antdiv_intvl = 0x64; /* 100ms */ + dm->fat_comb_a = 5; + dm->antdiv_intvl = 0x64; /* 100ms */ for (i = 0; i < 6; i++) - p_dm_fat_table->bssid[i] = 0; - for (i = 0; i < (p_dm_odm->fat_comb_a) ; i++) { - p_dm_fat_table->ant_sum_rssi[i] = 0; - p_dm_fat_table->ant_rssi_cnt[i] = 0; - p_dm_fat_table->ant_ave_rssi[i] = 0; + fat_tab->bssid[i] = 0; + for (i = 0; i < (dm->fat_comb_a) ; i++) { + fat_tab->ant_sum_rssi[i] = 0; + fat_tab->ant_rssi_cnt[i] = 0; + fat_tab->ant_ave_rssi[i] = 0; } /* MAC setting */ - value32 = odm_get_mac_reg(p_dm_odm, 0x4c, MASKDWORD); - odm_set_mac_reg(p_dm_odm, 0x4c, MASKDWORD, value32 | (BIT(23) | BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ - value32 = odm_get_mac_reg(p_dm_odm, 0x7B4, MASKDWORD); - odm_set_mac_reg(p_dm_odm, 0x7b4, MASKDWORD, value32 | (BIT(16) | BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */ + value32 = odm_get_mac_reg(dm, 0x4c, MASKDWORD); + odm_set_mac_reg(dm, 0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + value32 = odm_get_mac_reg(dm, 0x7B4, MASKDWORD); + odm_set_mac_reg(dm, 0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */ /* value32 = platform_efio_read_4byte(adapter, 0x7B4); */ /* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18)); */ /* append MACID in reponse packet */ /* Match MAC ADDR */ - odm_set_mac_reg(p_dm_odm, 0x7b4, 0xFFFF, 0); - odm_set_mac_reg(p_dm_odm, 0x7b0, MASKDWORD, 0); + odm_set_mac_reg(dm, 0x7b4, 0xFFFF, 0); + odm_set_mac_reg(dm, 0x7b0, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x870, BIT(9) | BIT8, 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ - odm_set_bb_reg(p_dm_odm, 0xb2c, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ - odm_set_bb_reg(p_dm_odm, 0xb2c, BIT(31), 0); /* regb2c[31]=1'b1 */ /* output at CS only */ - odm_set_bb_reg(p_dm_odm, 0xca4, MASKDWORD, 0x000000a0); + odm_set_bb_reg(dm, 0x870, BIT(9) | BIT(8), 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ + odm_set_bb_reg(dm, 0x864, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ + odm_set_bb_reg(dm, 0xb2c, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ + odm_set_bb_reg(dm, 0xb2c, BIT(31), 0); /* regb2c[31]=1'b1 */ /* output at CS only */ + odm_set_bb_reg(dm, 0xca4, MASKDWORD, 0x000000a0); /* antenna mapping table */ - if (p_dm_odm->fat_comb_a == 2) { - if (!p_dm_odm->is_mp_chip) { /* testchip */ - odm_set_bb_reg(p_dm_odm, 0x858, BIT(10) | BIT9 | BIT8, 1); /* Reg858[10:8]=3'b001 */ - odm_set_bb_reg(p_dm_odm, 0x858, BIT(13) | BIT12 | BIT11, 2); /* Reg858[13:11]=3'b010 */ + if (dm->fat_comb_a == 2) { + if (!dm->is_mp_chip) { /* testchip */ + odm_set_bb_reg(dm, 0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */ + odm_set_bb_reg(dm, 0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */ } else { /* MPchip */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 1); - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 2); + odm_set_bb_reg(dm, 0x914, MASKBYTE0, 1); + odm_set_bb_reg(dm, 0x914, MASKBYTE1, 2); } } else { - if (!p_dm_odm->is_mp_chip) { /* testchip */ - odm_set_bb_reg(p_dm_odm, 0x858, BIT(10) | BIT9 | BIT8, 0); /* Reg858[10:8]=3'b000 */ - odm_set_bb_reg(p_dm_odm, 0x858, BIT(13) | BIT12 | BIT11, 1); /* Reg858[13:11]=3'b001 */ - odm_set_bb_reg(p_dm_odm, 0x878, BIT(16), 0); - odm_set_bb_reg(p_dm_odm, 0x858, BIT(15) | BIT14, 2); /* (Reg878[0],Reg858[14:15])=3'b010 */ - odm_set_bb_reg(p_dm_odm, 0x878, BIT(19) | BIT18 | BIT17, 3); /* Reg878[3:1]=3b'011 */ - odm_set_bb_reg(p_dm_odm, 0x878, BIT(22) | BIT21 | BIT20, 4); /* Reg878[6:4]=3b'100 */ - odm_set_bb_reg(p_dm_odm, 0x878, BIT(25) | BIT24 | BIT23, 5); /* Reg878[9:7]=3b'101 */ - odm_set_bb_reg(p_dm_odm, 0x878, BIT(28) | BIT27 | BIT26, 6); /* Reg878[12:10]=3b'110 */ - odm_set_bb_reg(p_dm_odm, 0x878, BIT(31) | BIT30 | BIT29, 7); /* Reg878[15:13]=3b'111 */ + if (!dm->is_mp_chip) { /* testchip */ + odm_set_bb_reg(dm, 0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */ + odm_set_bb_reg(dm, 0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */ + odm_set_bb_reg(dm, 0x878, BIT(16), 0); + odm_set_bb_reg(dm, 0x858, BIT(15) | BIT(14), 2); /* (Reg878[0],Reg858[14:15])=3'b010 */ + odm_set_bb_reg(dm, 0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */ + odm_set_bb_reg(dm, 0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */ + odm_set_bb_reg(dm, 0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */ + odm_set_bb_reg(dm, 0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */ + odm_set_bb_reg(dm, 0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */ } else { /* MPchip */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 4); /* 0: 3b'000 */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 2); /* 1: 3b'001 */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE2, 0); /* 2: 3b'010 */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE3, 1); /* 3: 3b'011 */ - odm_set_bb_reg(p_dm_odm, 0x918, MASKBYTE0, 3); /* 4: 3b'100 */ - odm_set_bb_reg(p_dm_odm, 0x918, MASKBYTE1, 5); /* 5: 3b'101 */ - odm_set_bb_reg(p_dm_odm, 0x918, MASKBYTE2, 6); /* 6: 3b'110 */ - odm_set_bb_reg(p_dm_odm, 0x918, MASKBYTE3, 255); /* 7: 3b'111 */ + odm_set_bb_reg(dm, 0x914, MASKBYTE0, 4); /* 0: 3b'000 */ + odm_set_bb_reg(dm, 0x914, MASKBYTE1, 2); /* 1: 3b'001 */ + odm_set_bb_reg(dm, 0x914, MASKBYTE2, 0); /* 2: 3b'010 */ + odm_set_bb_reg(dm, 0x914, MASKBYTE3, 1); /* 3: 3b'011 */ + odm_set_bb_reg(dm, 0x918, MASKBYTE0, 3); /* 4: 3b'100 */ + odm_set_bb_reg(dm, 0x918, MASKBYTE1, 5); /* 5: 3b'101 */ + odm_set_bb_reg(dm, 0x918, MASKBYTE2, 6); /* 6: 3b'110 */ + odm_set_bb_reg(dm, 0x918, MASKBYTE3, 255); /* 7: 3b'111 */ } } /* Default ant setting when no fast training */ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT4 | BIT3, 0); /* Default RX */ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT7 | BIT6, 1); /* Optional RX */ - odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, 0); /* Default TX */ + odm_set_bb_reg(dm, 0x864, BIT(5) | BIT(4) | BIT(3), 0); /* Default RX */ + odm_set_bb_reg(dm, 0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */ + odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), 0); /* Default TX */ /* Enter Traing state */ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(2) | BIT1 | BIT0, (p_dm_odm->fat_comb_a - 1)); /* reg864[2:0]=3'd6 */ /* ant combination=reg864[2:0]+1 */ + odm_set_bb_reg(dm, 0x864, BIT(2) | BIT(1) | BIT(0), (dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6 */ /* ant combination=reg864[2:0]+1 */ /* SW Control */ /* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */ @@ -969,122 +1006,122 @@ odm_smart_hw_ant_div_init_88e( #if (RTL8192E_SUPPORT == 1) void odm_rx_hw_ant_div_init_92e( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; #if 0 - if (*(p_dm_odm->p_mp_mode) == true) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(9), 1); /* 1:CG, 0:CS */ + if (*(dm->mp_mode) == true) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_set_bb_reg(dm, 0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ + odm_set_bb_reg(dm, 0xc50, BIT(9), 1); /* 1:CG, 0:CS */ return; } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***8192E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n"); /* Pin Settings */ - odm_set_bb_reg(p_dm_odm, 0x870, BIT(8), 0);/* reg870[8]=1'b0, */ /* "antsel" is controled by HWs */ - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(8), 1); /* regc50[8]=1'b1 */ /* " CS/CG switching" is controled by HWs */ + odm_set_bb_reg(dm, 0x870, BIT(8), 0);/* reg870[8]=1'b0, */ /* "antsel" is controled by HWs */ + odm_set_bb_reg(dm, 0xc50, BIT(8), 1); /* regc50[8]=1'b1 */ /* " CS/CG switching" is controled by HWs */ /* Mapping table */ - odm_set_bb_reg(p_dm_odm, 0x914, 0xFFFF, 0x0100); /* antenna mapping table */ + odm_set_bb_reg(dm, 0x914, 0xFFFF, 0x0100); /* antenna mapping table */ /* OFDM Settings */ - odm_set_bb_reg(p_dm_odm, 0xca4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0xca4, 0x7FF000, 0x0); /* bias */ + odm_set_bb_reg(dm, 0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, 0xca4, 0x7FF000, 0x0); /* bias */ /* CCK Settings */ - odm_set_bb_reg(p_dm_odm, 0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ - odm_set_bb_reg(p_dm_odm, 0xb34, BIT(30), 0); /* (92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ - odm_set_bb_reg(p_dm_odm, 0xa74, BIT(7), 1); /* Fix CCK PHY status report issue */ - odm_set_bb_reg(p_dm_odm, 0xa0c, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + odm_set_bb_reg(dm, 0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, 0xb34, BIT(30), 0); /* (92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(dm, 0xa74, BIT(7), 1); /* Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, 0xa0c, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ #ifdef ODM_EVM_ENHANCE_ANTDIV - phydm_evm_sw_antdiv_init(p_dm_odm); + phydm_evm_sw_antdiv_init(dm); #endif } void odm_trx_hw_ant_div_init_92e( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if 0 - if (*(p_dm_odm->p_mp_mode) == true) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(9), 1); /* 1:CG, 0:CS */ + if (*(dm->mp_mode) == true) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_set_bb_reg(dm, 0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ + odm_set_bb_reg(dm, 0xc50, BIT(9), 1); /* 1:CG, 0:CS */ return; } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => ant_div_type=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***8192E AntDiv_Init => ant_div_type=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n"); /* 3 --RFE pin setting--------- */ /* [MAC] */ - odm_set_mac_reg(p_dm_odm, 0x38, BIT(11), 1); /* DBG PAD Driving control (GPIO 8) */ - odm_set_mac_reg(p_dm_odm, 0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */ - odm_set_mac_reg(p_dm_odm, 0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */ + odm_set_mac_reg(dm, 0x38, BIT(11), 1); /* DBG PAD Driving control (GPIO 8) */ + odm_set_mac_reg(dm, 0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */ + odm_set_mac_reg(dm, 0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */ /* [BB] */ - odm_set_bb_reg(p_dm_odm, 0x944, BIT(3), 1); /* RFE_buffer */ - odm_set_bb_reg(p_dm_odm, 0x944, BIT(8), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(7) | BIT6, 0x0); /* r_rfe_path_sel_ (RFE_CTRL_3) */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(17) | BIT16, 0x0); /* r_rfe_path_sel_ (RFE_CTRL_8) */ - odm_set_bb_reg(p_dm_odm, 0x944, BIT(31), 0); /* RFE_buffer */ - odm_set_bb_reg(p_dm_odm, 0x92C, BIT(3), 0); /* rfe_inv (RFE_CTRL_3) */ - odm_set_bb_reg(p_dm_odm, 0x92C, BIT(8), 1); /* rfe_inv (RFE_CTRL_8) */ - odm_set_bb_reg(p_dm_odm, 0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */ - odm_set_bb_reg(p_dm_odm, 0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */ + odm_set_bb_reg(dm, 0x944, BIT(3), 1); /* RFE_buffer */ + odm_set_bb_reg(dm, 0x944, BIT(8), 1); + odm_set_bb_reg(dm, 0x940, BIT(7) | BIT(6), 0x0); /* r_rfe_path_sel_ (RFE_CTRL_3) */ + odm_set_bb_reg(dm, 0x940, BIT(17) | BIT(16), 0x0); /* r_rfe_path_sel_ (RFE_CTRL_8) */ + odm_set_bb_reg(dm, 0x944, BIT(31), 0); /* RFE_buffer */ + odm_set_bb_reg(dm, 0x92C, BIT(3), 0); /* rfe_inv (RFE_CTRL_3) */ + odm_set_bb_reg(dm, 0x92C, BIT(8), 1); /* rfe_inv (RFE_CTRL_8) */ + odm_set_bb_reg(dm, 0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */ + odm_set_bb_reg(dm, 0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */ /* 3 ------------------------- */ /* Pin Settings */ - odm_set_bb_reg(p_dm_odm, 0xC50, BIT(8), 0); /* path-A */ /* disable CS/CG switch */ + odm_set_bb_reg(dm, 0xC50, BIT(8), 0); /* path-A */ /* disable CS/CG switch */ #if 0 /* Let it follows PHY_REG for bit9 setting */ - if (p_dm_odm->priv->pshare->rf_ft_var.use_ext_pa || p_dm_odm->priv->pshare->rf_ft_var.use_ext_lna) - odm_set_bb_reg(p_dm_odm, 0xC50, BIT(9), 1);/* path-A //output at CS */ + if (dm->priv->pshare->rf_ft_var.use_ext_pa || dm->priv->pshare->rf_ft_var.use_ext_lna) + odm_set_bb_reg(dm, 0xC50, BIT(9), 1); /* path-A output at CS */ else - odm_set_bb_reg(p_dm_odm, 0xC50, BIT(9), 0); /* path-A //output at CG ->normal power */ + odm_set_bb_reg(dm, 0xC50, BIT(9), 0); /* path-A output at CG ->normal power */ #endif - odm_set_bb_reg(p_dm_odm, 0x870, BIT(9) | BIT8, 0); /* path-A */ /* antsel antselb by HW */ - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(10), 0); /* path-A */ /* antsel2 by HW */ + odm_set_bb_reg(dm, 0x870, BIT(9) | BIT(8), 0); /* path-A*/ /* antsel antselb by HW */ + odm_set_bb_reg(dm, 0xB38, BIT(10), 0); /* path-A */ /* antsel2 by HW */ /* Mapping table */ - odm_set_bb_reg(p_dm_odm, 0x914, 0xFFFF, 0x0100); /* antenna mapping table */ + odm_set_bb_reg(dm, 0x914, 0xFFFF, 0x0100); /* antenna mapping table */ /* OFDM Settings */ - odm_set_bb_reg(p_dm_odm, 0xca4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0xca4, 0x7FF000, 0x0); /* bias */ + odm_set_bb_reg(dm, 0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, 0xca4, 0x7FF000, 0x0); /* bias */ /* CCK Settings */ - odm_set_bb_reg(p_dm_odm, 0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ - odm_set_bb_reg(p_dm_odm, 0xb34, BIT(30), 0); /* (92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ - odm_set_bb_reg(p_dm_odm, 0xa74, BIT(7), 1); /* Fix CCK PHY status report issue */ - odm_set_bb_reg(p_dm_odm, 0xa0c, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + odm_set_bb_reg(dm, 0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, 0xb34, BIT(30), 0); /* (92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(dm, 0xa74, BIT(7), 1); /* Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, 0xa0c, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ #ifdef ODM_EVM_ENHANCE_ANTDIV - phydm_evm_sw_antdiv_init(p_dm_odm); + phydm_evm_sw_antdiv_init(dm); #endif } #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) void odm_smart_hw_ant_div_init_92e( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "***8192E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n"); } #endif @@ -1093,112 +1130,110 @@ odm_smart_hw_ant_div_init_92e( #if (RTL8723D_SUPPORT == 1) void odm_trx_hw_ant_div_init_8723d( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723D] AntDiv_Init => ant_div_type=[S0S1_HW_TRX_AntDiv]\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[8723D] AntDiv_Init => ant_div_type=[S0S1_HW_TRX_AntDiv]\n"); /*BT Coexistence*/ /*keep antsel_map when GNT_BT = 1*/ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(12), 1); + odm_set_bb_reg(dm, 0x864, BIT(12), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ - odm_set_bb_reg(p_dm_odm, 0x874, BIT(23), 0); + odm_set_bb_reg(dm, 0x874, BIT(23), 0); /* Disable hw antsw & fast_train.antsw when BT TX/RX */ - odm_set_bb_reg(p_dm_odm, 0xE64, 0xFFFF0000, 0x000c); + odm_set_bb_reg(dm, 0xE64, 0xFFFF0000, 0x000c); - odm_set_bb_reg(p_dm_odm, 0x870, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, 0x870, BIT(9) | BIT(8), 0); /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/ - /*odm_set_bb_reg(p_dm_odm, 0x948, BIT6, 0);*/ - /*odm_set_bb_reg(p_dm_odm, 0x948, BIT8, 0);*/ + /*odm_set_bb_reg(dm, 0x948, BIT6, 0);*/ + /*odm_set_bb_reg(dm, 0x948, BIT8, 0);*/ /*GNT_WL tx*/ - odm_set_bb_reg(p_dm_odm, 0x950, BIT(29), 0); + odm_set_bb_reg(dm, 0x950, BIT(29), 0); /*Mapping Table*/ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 3); - /* odm_set_bb_reg(p_dm_odm, 0x864, BIT5|BIT4|BIT3, 0); */ - /* odm_set_bb_reg(p_dm_odm, 0x864, BIT8|BIT7|BIT6, 1); */ + odm_set_bb_reg(dm, 0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, 0x914, MASKBYTE1, 3); + /* odm_set_bb_reg(dm, 0x864, BIT5|BIT4|BIT3, 0); */ + /* odm_set_bb_reg(dm, 0x864, BIT8|BIT7|BIT6, 1); */ /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */ - odm_set_bb_reg(p_dm_odm, 0xCcc, BIT(12), 0); + odm_set_bb_reg(dm, 0xCcc, BIT(12), 0); /* Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */ - odm_set_bb_reg(p_dm_odm, 0xCcc, 0x0F, 0x01); + odm_set_bb_reg(dm, 0xCcc, 0x0F, 0x01); /* High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */ - odm_set_bb_reg(p_dm_odm, 0xCcc, 0xF0, 0x0); + odm_set_bb_reg(dm, 0xCcc, 0xF0, 0x0); /* b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */ - odm_set_bb_reg(p_dm_odm, 0xAbc, 0xFF, 0x06); + odm_set_bb_reg(dm, 0xAbc, 0xFF, 0x06); /* High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */ - odm_set_bb_reg(p_dm_odm, 0xAbc, 0xFF00, 0x00); + odm_set_bb_reg(dm, 0xAbc, 0xFF00, 0x00); /*OFDM HW AntDiv Parameters*/ - odm_set_bb_reg(p_dm_odm, 0xCA4, 0x7FF, 0xa0); - odm_set_bb_reg(p_dm_odm, 0xCA4, 0x7FF000, 0x00); - odm_set_bb_reg(p_dm_odm, 0xC5C, BIT(20) | BIT(19) | BIT(18), 0x04); + odm_set_bb_reg(dm, 0xCA4, 0x7FF, 0xa0); + odm_set_bb_reg(dm, 0xCA4, 0x7FF000, 0x00); + odm_set_bb_reg(dm, 0xC5C, BIT(20) | BIT(19) | BIT(18), 0x04); /*CCK HW AntDiv Parameters*/ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); - odm_set_bb_reg(p_dm_odm, 0xAA8, BIT(8), 0); + odm_set_bb_reg(dm, 0xA74, BIT(7), 1); + odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); + odm_set_bb_reg(dm, 0xAA8, BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0xA0C, 0x0F, 0xf); - odm_set_bb_reg(p_dm_odm, 0xA14, 0x1F, 0x8); - odm_set_bb_reg(p_dm_odm, 0xA10, BIT(13), 0x1); - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(8), 0x0); - odm_set_bb_reg(p_dm_odm, 0xB34, BIT(30), 0x1); + odm_set_bb_reg(dm, 0xA0C, 0x0F, 0xf); + odm_set_bb_reg(dm, 0xA14, 0x1F, 0x8); + odm_set_bb_reg(dm, 0xA10, BIT(13), 0x1); + odm_set_bb_reg(dm, 0xA74, BIT(8), 0x0); + odm_set_bb_reg(dm, 0xB34, BIT(30), 0x1); /*disable antenna training */ - odm_set_bb_reg(p_dm_odm, 0xE08, BIT(16), 0); - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(8), 0); + odm_set_bb_reg(dm, 0xE08, BIT(16), 0); + odm_set_bb_reg(dm, 0xc50, BIT(8), 0); } - /*Mingzhi 2017-05-08*/ + void odm_update_rx_idle_ant_8723d( - void *p_dm_void, + void *dm_void, u8 ant, u32 default_ant, u32 optional_ant ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + void *adapter = dm->adapter; u8 count = 0; - u8 u1_temp; - u8 h2c_parameter; -/* odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0x1); */ - odm_set_bb_reg(p_dm_odm, 0x948, BIT(7), default_ant); - odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/ - odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*Default TX*/ - p_dm_fat_table->rx_idle_ant = ant; +/* odm_set_bb_reg(dm, 0x948, BIT(6), 0x1); */ + odm_set_bb_reg(dm, 0x948, BIT(7), default_ant); + odm_set_bb_reg(dm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/ + odm_set_bb_reg(dm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/ + odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*Default TX*/ + fat_tab->rx_idle_ant = ant; + } void phydm_set_tx_ant_pwr_8723d( - void *p_dm_void, + void *dm_void, u8 ant ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + PADAPTER adapter = (PADAPTER)dm->adapter; - p_dm_fat_table->rx_idle_ant = ant; + fat_tab->rx_idle_ant = ant; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_adapter->HalFunc.SetTxPowerLevelHandler(p_adapter, *p_dm_odm->p_channel); + adapter->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - rtw_hal_set_tx_power_level(p_adapter, *p_dm_odm->p_channel); + rtw_hal_set_tx_power_level(adapter, *dm->channel); #endif } @@ -1207,50 +1242,51 @@ phydm_set_tx_ant_pwr_8723d( #if (RTL8723B_SUPPORT == 1) void odm_trx_hw_ant_div_init_8723b( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "***8723B AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n"); /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 1); + odm_set_bb_reg(dm, 0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, 0x914, MASKBYTE1, 1); /* OFDM HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xCA4, 0x7FF, 0xa0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0xCA4, 0x7FF000, 0x00); /* bias */ + odm_set_bb_reg(dm, 0xCA4, 0x7FF, 0xa0); /* thershold */ + odm_set_bb_reg(dm, 0xCA4, 0x7FF000, 0x00); /* bias */ /* CCK HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */ /* BT Coexistence */ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(12), 0); /* keep antsel_map when GNT_BT = 1 */ - odm_set_bb_reg(p_dm_odm, 0x874, BIT(23), 0); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, 0x864, BIT(12), 0); /* keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, 0x874, BIT(23), 0); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ /* Output Pin Settings */ - odm_set_bb_reg(p_dm_odm, 0x870, BIT(8), 0); + odm_set_bb_reg(dm, 0x870, BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0); /* WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) */ - odm_set_bb_reg(p_dm_odm, 0x948, BIT(7), 0); + odm_set_bb_reg(dm, 0x948, BIT(6), 0); /* WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) */ + odm_set_bb_reg(dm, 0x948, BIT(7), 0); - odm_set_mac_reg(p_dm_odm, 0x40, BIT(3), 1); - odm_set_mac_reg(p_dm_odm, 0x38, BIT(11), 1); - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24) | BIT23, 2); /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, 0x40, BIT(3), 1); + odm_set_mac_reg(dm, 0x38, BIT(11), 1); + odm_set_mac_reg(dm, 0x4C, BIT(24) | BIT(23), 2); /* select DPDT_P and DPDT_N as output pin */ - odm_set_bb_reg(p_dm_odm, 0x944, BIT(0) | BIT1, 3); /* in/out */ - odm_set_bb_reg(p_dm_odm, 0x944, BIT(31), 0); + odm_set_bb_reg(dm, 0x944, BIT(0) | BIT(1), 3); /* in/out */ + odm_set_bb_reg(dm, 0x944, BIT(31), 0); - odm_set_bb_reg(p_dm_odm, 0x92C, BIT(1), 0); /* DPDT_P non-inverse */ - odm_set_bb_reg(p_dm_odm, 0x92C, BIT(0), 1); /* DPDT_N inverse */ + odm_set_bb_reg(dm, 0x92C, BIT(1), 0); /* DPDT_P non-inverse */ + odm_set_bb_reg(dm, 0x92C, BIT(0), 1); /* DPDT_N inverse */ - odm_set_bb_reg(p_dm_odm, 0x930, 0xF0, 8); /* DPDT_P = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0x930, 0xF, 8); /* DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, 0x930, 0xF0, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, 0x930, 0xF, 8); /* DPDT_N = ANTSEL[0] */ /* 2 [--For HW Bug setting] */ - if (p_dm_odm->ant_type == ODM_AUTO_ANT) - odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ + if (dm->ant_type == ODM_AUTO_ANT) + odm_set_bb_reg(dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ } @@ -1258,50 +1294,49 @@ odm_trx_hw_ant_div_init_8723b( void odm_s0s1_sw_ant_div_init_8723b( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"); /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 1); + odm_set_bb_reg(dm, 0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, 0x914, MASKBYTE1, 1); /* Output Pin Settings */ - /* odm_set_bb_reg(p_dm_odm, 0x948, BIT6, 0x1); */ - odm_set_bb_reg(p_dm_odm, 0x870, BIT(9) | BIT(8), 0); + /* odm_set_bb_reg(dm, 0x948, BIT6, 0x1); */ + odm_set_bb_reg(dm, 0x870, BIT(9) | BIT(8), 0); - p_dm_fat_table->is_become_linked = false; - p_dm_swat_table->try_flag = SWAW_STEP_INIT; - p_dm_swat_table->double_chk_flag = 0; + fat_tab->is_become_linked = false; + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->double_chk_flag = 0; /* 2 [--For HW Bug setting] */ - odm_set_bb_reg(p_dm_odm, 0x80C, BIT(21), 0); /* TX ant by Reg */ + odm_set_bb_reg(dm, 0x80C, BIT(21), 0); /* TX ant by Reg */ } void odm_update_rx_idle_ant_8723b( - void *p_dm_void, + void *dm_void, u8 ant, u32 default_ant, u32 optional_ant ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + PADAPTER adapter = (PADAPTER)dm->adapter; u8 count = 0; - u8 u1_temp; - u8 h2c_parameter; + /*u8 u1_temp;*/ + /*u8 h2c_parameter;*/ - if ((!p_dm_odm->is_linked) && (p_dm_odm->ant_type == ODM_AUTO_ANT)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n")); + if ((!dm->is_linked) && (dm->ant_type == ODM_AUTO_ANT)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n"); return; } @@ -1309,94 +1344,94 @@ odm_update_rx_idle_ant_8723b( /* Send H2C command to FW */ /* Enable wifi calibration */ h2c_parameter = true; - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); + odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); /* Check if H2C command sucess or not (0x1e6) */ - u1_temp = odm_read_1byte(p_dm_odm, 0x1e6); + u1_temp = odm_read_1byte(dm, 0x1e6); while ((u1_temp != 0x1) && (count < 100)) { ODM_delay_us(10); - u1_temp = odm_read_1byte(p_dm_odm, 0x1e6); + u1_temp = odm_read_1byte(dm, 0x1e6); count++; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n", u1_temp, count)); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n", u1_temp, count); if (u1_temp == 0x1) { /* Check if BT is doing IQK (0x1e7) */ count = 0; - u1_temp = odm_read_1byte(p_dm_odm, 0x1e7); + u1_temp = odm_read_1byte(dm, 0x1e7); while ((!(u1_temp & BIT(0))) && (count < 100)) { ODM_delay_us(50); - u1_temp = odm_read_1byte(p_dm_odm, 0x1e7); + u1_temp = odm_read_1byte(dm, 0x1e7); count++; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n", u1_temp, count)); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n", u1_temp, count); if (u1_temp & BIT(0)) { - odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0x1); - odm_set_bb_reg(p_dm_odm, 0x948, BIT(9), default_ant); - odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT4 | BIT3, default_ant); /* Default RX */ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT7 | BIT6, optional_ant); /* Optional RX */ - odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, default_ant); /* Default TX */ - p_dm_fat_table->rx_idle_ant = ant; + odm_set_bb_reg(dm, 0x948, BIT(6), 0x1); + odm_set_bb_reg(dm, 0x948, BIT(9), default_ant); + odm_set_bb_reg(dm, 0x864, BIT(5) | BIT4 | BIT3, default_ant); /* Default RX */ + odm_set_bb_reg(dm, 0x864, BIT(8) | BIT7 | BIT6, optional_ant); /* Optional RX */ + odm_set_bb_reg(dm, 0x860, BIT(14) | BIT13 | BIT12, default_ant); /* Default TX */ + fat_tab->rx_idle_ant = ant; /* Set TX AGC by S0/S1 */ /* Need to consider Linux driver */ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_adapter->hal_func.set_tx_power_level_handler(p_adapter, *p_dm_odm->p_channel); + adapter->hal_func.set_tx_power_level_handler(adapter, *dm->channel); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - rtw_hal_set_tx_power_level(p_adapter, *p_dm_odm->p_channel); + rtw_hal_set_tx_power_level(adapter, *dm->channel); #endif /* Set IQC by S0/S1 */ - odm_set_iqc_by_rfpath(p_dm_odm, default_ant); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Sucess to set RX antenna\n")); + odm_set_iqc_by_rfpath(dm, default_ant); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n"); } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n"); } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n"); /* Send H2C command to FW */ /* Disable wifi calibration */ h2c_parameter = false; - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); + odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); #else - odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0x1); - odm_set_bb_reg(p_dm_odm, 0x948, BIT(9), default_ant); - odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT4 | BIT3, default_ant); /*Default RX*/ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT7 | BIT6, optional_ant); /*Optional RX*/ - odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, default_ant); /*Default TX*/ - p_dm_fat_table->rx_idle_ant = ant; + odm_set_bb_reg(dm, 0x948, BIT(6), 0x1); + odm_set_bb_reg(dm, 0x948, BIT(9), default_ant); + odm_set_bb_reg(dm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/ + odm_set_bb_reg(dm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/ + odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*Default TX*/ + fat_tab->rx_idle_ant = ant; /* Set TX AGC by S0/S1 */ /* Need to consider Linux driver */ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_adapter->HalFunc.SetTxPowerLevelHandler(p_adapter, *p_dm_odm->p_channel); + adapter->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - rtw_hal_set_tx_power_level(p_adapter, *p_dm_odm->p_channel); + rtw_hal_set_tx_power_level(adapter, *dm->channel); #endif /* Set IQC by S0/S1 */ - odm_set_iqc_by_rfpath(p_dm_odm, default_ant); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n")); + odm_set_iqc_by_rfpath(dm, default_ant); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n"); #endif } boolean phydm_is_bt_enable_8723b( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 bt_state; /*u32 reg75;*/ - /*reg75 = odm_get_bb_reg(p_dm_odm, 0x74, BIT8);*/ - /*odm_set_bb_reg(p_dm_odm, 0x74, BIT8, 0x0);*/ - odm_set_bb_reg(p_dm_odm, 0xa0, BIT(24) | BIT(25) | BIT(26), 0x5); - bt_state = odm_get_bb_reg(p_dm_odm, 0xa0, (BIT(3) | BIT(2) | BIT(1) | BIT(0))); - /*odm_set_bb_reg(p_dm_odm, 0x74, BIT8, reg75);*/ + /*reg75 = odm_get_bb_reg(dm, 0x74, BIT8);*/ + /*odm_set_bb_reg(dm, 0x74, BIT8, 0x0);*/ + odm_set_bb_reg(dm, 0xa0, BIT(24) | BIT(25) | BIT(26), 0x5); + bt_state = odm_get_bb_reg(dm, 0xa0, (BIT(3) | BIT(2) | BIT(1) | BIT(0))); + /*odm_set_bb_reg(dm, 0x74, BIT8, reg75);*/ if ((bt_state == 4) || (bt_state == 7) || (bt_state == 9) || (bt_state == 13)) return true; @@ -1406,392 +1441,227 @@ phydm_is_bt_enable_8723b( #endif /* #if (RTL8723B_SUPPORT == 1) */ #if (RTL8821A_SUPPORT == 1) -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 -void -phydm_hl_smart_ant_type1_init_8821a( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u32 value32; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A SmartAnt_Init => ant_div_type=[Hong-Lin Smart ant Type1]\n")); - -#if 0 - /* ---------------------------------------- */ - /* GPIO 2-3 for Beam control */ - /* reg0x66[2]=0 */ - /* reg0x44[27:26] = 0 */ - /* reg0x44[23:16] enable_output for P_GPIO[7:0] */ - /* reg0x44[15:8] output_value for P_GPIO[7:0] */ - /* reg0x40[1:0] = 0 GPIO function */ - /* ------------------------------------------ */ -#endif - - /*GPIO setting*/ - odm_set_mac_reg(p_dm_odm, 0x64, BIT(18), 0); - odm_set_mac_reg(p_dm_odm, 0x44, BIT(27) | BIT(26), 0); - odm_set_mac_reg(p_dm_odm, 0x44, BIT(19) | BIT18, 0x3); /*enable_output for P_GPIO[3:2]*/ - /*odm_set_mac_reg(p_dm_odm, 0x44, BIT(11)|BIT10, 0);*/ /*output value*/ - odm_set_mac_reg(p_dm_odm, 0x40, BIT(1) | BIT0, 0); /*GPIO function*/ - - /*Hong_lin smart antenna HW setting*/ - pdm_sat_table->rfu_codeword_total_bit_num = 24;/*max=32*/ - pdm_sat_table->rfu_each_ant_bit_num = 4; - pdm_sat_table->beam_patten_num_each_ant = 4; - -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE - pdm_sat_table->latch_time = 100; /*mu sec*/ -#elif DEV_BUS_TYPE == RT_USB_INTERFACE - pdm_sat_table->latch_time = 100; /*mu sec*/ -#endif - pdm_sat_table->pkt_skip_statistic_en = 0; - - pdm_sat_table->ant_num = 1;/*max=8*/ - pdm_sat_table->ant_num_total = NUM_ANTENNA_8821A; - pdm_sat_table->first_train_ant = MAIN_ANT; - - pdm_sat_table->rfu_codeword_table[0] = 0x0; - pdm_sat_table->rfu_codeword_table[1] = 0x4; - pdm_sat_table->rfu_codeword_table[2] = 0x8; - pdm_sat_table->rfu_codeword_table[3] = 0xc; - - pdm_sat_table->rfu_codeword_table_5g[0] = 0x1; - pdm_sat_table->rfu_codeword_table_5g[1] = 0x2; - pdm_sat_table->rfu_codeword_table_5g[2] = 0x4; - pdm_sat_table->rfu_codeword_table_5g[3] = 0x8; - - pdm_sat_table->fix_beam_pattern_en = 0; - pdm_sat_table->decision_holding_period = 0; - - /*beam training setting*/ - pdm_sat_table->pkt_counter = 0; - pdm_sat_table->per_beam_training_pkt_num = 10; - - /*set default beam*/ - pdm_sat_table->fast_training_beam_num = 0; - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - phydm_set_all_ant_same_beam_num(p_dm_odm); - - p_dm_fat_table->fat_state = FAT_BEFORE_LINK_STATE; - - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKDWORD, 0x01000100); - odm_set_bb_reg(p_dm_odm, 0xCA8, MASKDWORD, 0x01000100); - - /*[BB] FAT setting*/ - odm_set_bb_reg(p_dm_odm, 0xc08, BIT(18) | BIT(17) | BIT(16), pdm_sat_table->ant_num); - odm_set_bb_reg(p_dm_odm, 0xc08, BIT(31), 0); /*increase ant num every FAT period 0:+1, 1+2*/ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(2) | BIT1, 1); /*change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(0), 1); /*FAT_watchdog_en*/ - - value32 = odm_get_mac_reg(p_dm_odm, 0x7B4, MASKDWORD); - odm_set_mac_reg(p_dm_odm, 0x7b4, MASKDWORD, value32 | (BIT(16) | BIT17)); /*Reg7B4[16]=1 enable antenna training */ - /*Reg7B4[17]=1 enable match MAC addr*/ - odm_set_mac_reg(p_dm_odm, 0x7b4, 0xFFFF, 0);/*Match MAC ADDR*/ - odm_set_mac_reg(p_dm_odm, 0x7b0, MASKDWORD, 0); - -} -#endif void odm_trx_hw_ant_div_init_8821a( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***8821A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n"); /* Output Pin Settings */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(25), 0); + odm_set_mac_reg(dm, 0x4C, BIT(25), 0); - odm_set_mac_reg(p_dm_odm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ - odm_set_mac_reg(p_dm_odm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ + odm_set_mac_reg(dm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(dm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ - odm_set_bb_reg(p_dm_odm, 0xCB8, BIT(16), 0); + odm_set_bb_reg(dm, 0xCB8, BIT(16), 0); - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /* by WLAN control */ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ + odm_set_mac_reg(dm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /* by WLAN control */ + odm_set_bb_reg(dm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ + odm_set_bb_reg(dm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); + odm_set_bb_reg(dm, 0xCA4, MASKBYTE0, 0); + odm_set_bb_reg(dm, 0xCA4, MASKBYTE1, 1); /* OFDM HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x10); /* bias */ + odm_set_bb_reg(dm, 0x8D4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, 0x8D4, 0x7FF000, 0x10); /* bias */ /* CCK HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */ - odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ - odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ + odm_set_bb_reg(dm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ /* BT Coexistence */ - odm_set_bb_reg(p_dm_odm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ - odm_set_bb_reg(p_dm_odm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ - odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ + odm_set_bb_reg(dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */ /* response TX ant by RX ant */ - odm_set_mac_reg(p_dm_odm, 0x668, BIT(3), 1); + odm_set_mac_reg(dm, 0x668, BIT(3), 1); } void odm_s0s1_sw_ant_div_init_8821a( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***8821A AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"); /* Output Pin Settings */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(25), 0); + odm_set_mac_reg(dm, 0x4C, BIT(25), 0); - odm_set_mac_reg(p_dm_odm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ - odm_set_mac_reg(p_dm_odm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ + odm_set_mac_reg(dm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(dm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ - odm_set_bb_reg(p_dm_odm, 0xCB8, BIT(16), 0); + odm_set_bb_reg(dm, 0xCB8, BIT(16), 0); - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /* by WLAN control */ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ + odm_set_mac_reg(dm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /* by WLAN control */ + odm_set_bb_reg(dm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ + odm_set_bb_reg(dm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); + odm_set_bb_reg(dm, 0xCA4, MASKBYTE0, 0); + odm_set_bb_reg(dm, 0xCA4, MASKBYTE1, 1); /* OFDM HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x10); /* bias */ + odm_set_bb_reg(dm, 0x8D4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, 0x8D4, 0x7FF000, 0x10); /* bias */ /* CCK HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */ - odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ - odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ + odm_set_bb_reg(dm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ /* BT Coexistence */ - odm_set_bb_reg(p_dm_odm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ - odm_set_bb_reg(p_dm_odm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ - odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ + odm_set_bb_reg(dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */ /* response TX ant by RX ant */ - odm_set_mac_reg(p_dm_odm, 0x668, BIT(3), 1); + odm_set_mac_reg(dm, 0x668, BIT(3), 1); - odm_set_bb_reg(p_dm_odm, 0x900, BIT(18), 0); + odm_set_bb_reg(dm, 0x900, BIT(18), 0); - p_dm_swat_table->try_flag = SWAW_STEP_INIT; - p_dm_swat_table->double_chk_flag = 0; - p_dm_swat_table->cur_antenna = MAIN_ANT; - p_dm_swat_table->pre_antenna = MAIN_ANT; - p_dm_swat_table->swas_no_link_state = 0; + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->double_chk_flag = 0; + dm_swat_table->cur_antenna = MAIN_ANT; + dm_swat_table->pre_antenna = MAIN_ANT; + dm_swat_table->swas_no_link_state = 0; } #endif /* #if (RTL8821A_SUPPORT == 1) */ -#if (RTL8822B_SUPPORT == 1) -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 +#if (RTL8821C_SUPPORT == 1) void -phydm_hl_smart_ant_type2_init_8822b( - void *p_dm_void +odm_trx_hw_ant_div_init_8821c( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u8 j; - u8 rfu_codeword_table_init_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = { - {1, 1},/*0*/ - {1, 2}, - {2, 1}, - {2, 2}, - {4, 0}, - {5, 0}, - {6, 0}, - {7, 0}, - {8, 0},/*8*/ - {9, 0}, - {0xa, 0}, - {0xb, 0}, - {0xc, 0}, - {0xd, 0}, - {0xe, 0}, - {0xf, 0} - }; - u8 rfu_codeword_table_init_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] ={ - #if 1 - {9, 1},/*0*/ - {9, 9}, - {1, 9}, - {9, 6}, - {2, 1}, - {2, 9}, - {9, 2}, - {2, 2},/*8*/ - {6, 1}, - {6, 9}, - {2, 9}, - {2, 2}, - {6, 2}, - {6, 6}, - {2, 6}, - {1, 1} - #else - {1, 1},/*0*/ - {9, 1}, - {9, 9}, - {1, 9}, - {1, 2}, - {9, 2}, - {9, 6}, - {1, 6}, - {2, 1},/*8*/ - {6, 1}, - {6, 9}, - {2, 9}, - {2, 2}, - {6, 2}, - {6, 6}, - {2, 6} - #endif - }; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***RTK 8822B SmartAnt_Init: Hong-Bo SmrtAnt Type2]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***8821C AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n"); + /* Output Pin Settings */ + odm_set_mac_reg(dm, 0x4C, BIT(25), 0); - /* ---------------------------------------- */ - /* GPIO 0-1 for Beam control */ - /* reg0x66[2:0]=0 */ - /* reg0x44[25:24] = 0 */ - /* reg0x44[23:16] enable_output for P_GPIO[7:0] */ - /* reg0x44[15:8] output_value for P_GPIO[7:0] */ - /* reg0x40[1:0] = 0 GPIO function */ - /* ------------------------------------------ */ + odm_set_mac_reg(dm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(dm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ - odm_move_memory(p_dm_odm, pdm_sat_table->rfu_codeword_table_2g, rfu_codeword_table_init_2g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B)); - odm_move_memory(p_dm_odm, pdm_sat_table->rfu_codeword_table_5g, rfu_codeword_table_init_5g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B)); + odm_set_bb_reg(dm, 0xCB8, BIT(16), 0); - /*GPIO setting*/ - odm_set_mac_reg(p_dm_odm, 0x64, (BIT(18) | BIT(17) | BIT(16)), 0); - odm_set_mac_reg(p_dm_odm, 0x44, BIT(25) | BIT24, 0); /*config P_GPIO[3:2] to data port*/ - odm_set_mac_reg(p_dm_odm, 0x44, BIT(17) | BIT16, 0x3); /*enable_output for P_GPIO[3:2]*/ - /*odm_set_mac_reg(p_dm_odm, 0x44, BIT(9)|BIT8, 0);*/ /*P_GPIO[3:2] output value*/ - odm_set_mac_reg(p_dm_odm, 0x40, BIT(1) | BIT0, 0); /*GPIO function*/ - - /*Hong_lin smart antenna HW setting*/ - pdm_sat_table->rfu_protocol_type = 2; - pdm_sat_table->rfu_protocol_delay_time = 45; - - pdm_sat_table->rfu_codeword_total_bit_num = 16;/*max=32bit*/ - pdm_sat_table->rfu_each_ant_bit_num = 4; - - pdm_sat_table->total_beam_set_num = 4; - pdm_sat_table->total_beam_set_num_2g = 4; - pdm_sat_table->total_beam_set_num_5g = 8; - -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE - pdm_sat_table->latch_time = 100; /*mu sec*/ -#elif DEV_BUS_TYPE == RT_USB_INTERFACE - pdm_sat_table->latch_time = 100; /*mu sec*/ -#endif - pdm_sat_table->pkt_skip_statistic_en = 0; + odm_set_mac_reg(dm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /* by WLAN control */ + odm_set_bb_reg(dm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ + odm_set_bb_reg(dm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ - pdm_sat_table->ant_num = 2; - pdm_sat_table->ant_num_total = MAX_PATH_NUM_8822B; - pdm_sat_table->first_train_ant = MAIN_ANT; + /* Mapping Table */ + odm_set_bb_reg(dm, 0xCA4, MASKBYTE0, 0); + odm_set_bb_reg(dm, 0xCA4, MASKBYTE1, 1); + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(dm, 0x8D4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, 0x8D4, 0x7FF000, 0x10); /* bias */ + /* CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */ - pdm_sat_table->fix_beam_pattern_en = 0; - pdm_sat_table->decision_holding_period = 0; + odm_set_bb_reg(dm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ - /*beam training setting*/ - pdm_sat_table->pkt_counter = 0; - pdm_sat_table->per_beam_training_pkt_num = 10; + /* BT Coexistence */ + odm_set_bb_reg(dm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ - /*set default beam*/ - pdm_sat_table->fast_training_beam_num = 0; - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; + /* Timming issue */ + odm_set_bb_reg(dm, 0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0); /*keep antidx after tx for ACK ( unit x 3.2 mu sec)*/ + odm_set_bb_reg(dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */ - for (j = 0; j < SUPPORT_BEAM_SET_PATTERN_NUM; j++) { - - pdm_sat_table->beam_set_avg_rssi_pre[j] = 0; - pdm_sat_table->beam_set_train_val_diff[j] = 0; - pdm_sat_table->beam_set_train_cnt[j] = 0; - } - phydm_set_rfu_beam_pattern_type2(p_dm_odm); - p_dm_fat_table->fat_state = FAT_BEFORE_LINK_STATE; - -} -#endif -#endif + /* response TX ant by RX ant */ + odm_set_mac_reg(dm, 0x668, BIT(3), 1); +} -#if (RTL8821C_SUPPORT == 1) void -odm_trx_hw_ant_div_init_8821c( - void *p_dm_void +phydm_s0s1_sw_ant_div_init_8821c( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "***8821C AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821C AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n")); /* Output Pin Settings */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(25), 0); + odm_set_mac_reg(dm, 0x4C, BIT(25), 0); - odm_set_mac_reg(p_dm_odm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ - odm_set_mac_reg(p_dm_odm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ + odm_set_mac_reg(dm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(dm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ - odm_set_bb_reg(p_dm_odm, 0xCB8, BIT(16), 0); + odm_set_bb_reg(dm, 0xCB8, BIT(16), 0); - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /* by WLAN control */ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ + odm_set_mac_reg(dm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /* by WLAN control */ + odm_set_bb_reg(dm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ + odm_set_bb_reg(dm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); + odm_set_bb_reg(dm, 0xCA4, MASKBYTE0, 0); + odm_set_bb_reg(dm, 0xCA4, MASKBYTE1, 1); /* OFDM HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x10); /* bias */ + odm_set_bb_reg(dm, 0x8D4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, 0x8D4, 0x7FF000, 0x00); /* bias */ /* CCK HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */ - odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ - odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ + odm_set_bb_reg(dm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ /* BT Coexistence */ - odm_set_bb_reg(p_dm_odm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ - odm_set_bb_reg(p_dm_odm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ - /* Timming issue */ - odm_set_bb_reg(p_dm_odm, 0x818, BIT(23) | BIT22 | BIT21 | BIT20, 0); /*keep antidx after tx for ACK ( unit x 3.2 mu sec)*/ - odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ + odm_set_bb_reg(dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */ /* response TX ant by RX ant */ - odm_set_mac_reg(p_dm_odm, 0x668, BIT(3), 1); + odm_set_mac_reg(dm, 0x668, BIT(3), 1); + + + odm_set_bb_reg(dm, 0x900, BIT(18), 0); + + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->double_chk_flag = 0; + dm_swat_table->cur_antenna = MAIN_ANT; + dm_swat_table->pre_antenna = MAIN_ANT; + dm_swat_table->swas_no_link_state = 0; } #endif /* #if (RTL8821C_SUPPORT == 1) */ @@ -1800,39 +1670,39 @@ odm_trx_hw_ant_div_init_8821c( #if (RTL8881A_SUPPORT == 1) void odm_trx_hw_ant_div_init_8881a( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***8881A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n"); /* Output Pin Settings */ /* [SPDT related] */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(25), 0); - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(26), 0); - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(31), 0); /* delay buffer */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(22), 0); - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(24), 1); - odm_set_bb_reg(p_dm_odm, 0xCB0, 0xF00, 8); /* DPDT_P = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB0, 0xF0000, 8); /* DPDT_N = ANTSEL[0] */ + odm_set_mac_reg(dm, 0x4C, BIT(25), 0); + odm_set_mac_reg(dm, 0x4C, BIT(26), 0); + odm_set_bb_reg(dm, 0xCB4, BIT(31), 0); /* delay buffer */ + odm_set_bb_reg(dm, 0xCB4, BIT(22), 0); + odm_set_bb_reg(dm, 0xCB4, BIT(24), 1); + odm_set_bb_reg(dm, 0xCB0, 0xF00, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, 0xCB0, 0xF0000, 8); /* DPDT_N = ANTSEL[0] */ /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); + odm_set_bb_reg(dm, 0xCA4, MASKBYTE0, 0); + odm_set_bb_reg(dm, 0xCA4, MASKBYTE1, 1); /* OFDM HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x0); /* bias */ - odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ + odm_set_bb_reg(dm, 0x8D4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, 0x8D4, 0x7FF000, 0x0); /* bias */ + odm_set_bb_reg(dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */ /* CCK HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */ /* 2 [--For HW Bug setting] */ - odm_set_bb_reg(p_dm_odm, 0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */ + odm_set_bb_reg(dm, 0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */ } #endif /* #if (RTL8881A_SUPPORT == 1) */ @@ -1841,40 +1711,41 @@ odm_trx_hw_ant_div_init_8881a( #if (RTL8812A_SUPPORT == 1) void odm_trx_hw_ant_div_init_8812a( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "***8812A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n"); /* 3 */ /* 3 --RFE pin setting--------- */ /* [BB] */ - odm_set_bb_reg(p_dm_odm, 0x900, BIT(10) | BIT9 | BIT8, 0x0); /* disable SW switch */ - odm_set_bb_reg(p_dm_odm, 0x900, BIT(17) | BIT(16), 0x0); - odm_set_bb_reg(p_dm_odm, 0x974, BIT(7) | BIT6, 0x3); /* in/out */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(31), 0); /* delay buffer */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(26), 0); - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(27), 1); - odm_set_bb_reg(p_dm_odm, 0xCB0, 0xF000000, 8); /* DPDT_P = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB0, 0xF0000000, 8); /* DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, 0x900, BIT(10) | BIT(9) | BIT(8), 0x0); /* disable SW switch */ + odm_set_bb_reg(dm, 0x900, BIT(17) | BIT(16), 0x0); + odm_set_bb_reg(dm, 0x974, BIT(7) | BIT(6), 0x3); /* in/out */ + odm_set_bb_reg(dm, 0xCB4, BIT(31), 0); /* delay buffer */ + odm_set_bb_reg(dm, 0xCB4, BIT(26), 0); + odm_set_bb_reg(dm, 0xCB4, BIT(27), 1); + odm_set_bb_reg(dm, 0xCB0, 0xF000000, 8); /* DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, 0xCB0, 0xF0000000, 8); /* DPDT_N = ANTSEL[0] */ /* 3 ------------------------- */ /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); + odm_set_bb_reg(dm, 0xCA4, MASKBYTE0, 0); + odm_set_bb_reg(dm, 0xCA4, MASKBYTE1, 1); /* OFDM HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x0); /* bias */ - odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ + odm_set_bb_reg(dm, 0x8D4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, 0x8D4, 0x7FF000, 0x0); /* bias */ + odm_set_bb_reg(dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */ /* CCK HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */ /* 2 [--For HW Bug setting] */ - odm_set_bb_reg(p_dm_odm, 0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */ + odm_set_bb_reg(dm, 0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */ } @@ -1883,62 +1754,62 @@ odm_trx_hw_ant_div_init_8812a( #if (RTL8188F_SUPPORT == 1) void odm_s0s1_sw_ant_div_init_8188f( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188F AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***8188F AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"); /*GPIO setting*/ - /*odm_set_mac_reg(p_dm_odm, 0x64, BIT18, 0); */ - /*odm_set_mac_reg(p_dm_odm, 0x44, BIT28|BIT27, 0);*/ - /*odm_set_mac_reg(p_dm_odm, 0x44, BIT(20) | BIT19, 0x3);*/ /*enable_output for P_GPIO[4:3]*/ - /*odm_set_mac_reg(p_dm_odm, 0x44, BIT(12)|BIT11, 0);*/ /*output value*/ - /*odm_set_mac_reg(p_dm_odm, 0x40, BIT(1)|BIT0, 0);*/ /*GPIO function*/ - - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - if (p_dm_odm->support_interface == ODM_ITRF_USB) - odm_set_mac_reg(p_dm_odm, 0x44, BIT(20) | BIT19, 0x3); /*enable_output for P_GPIO[4:3]*/ - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) - odm_set_mac_reg(p_dm_odm, 0x44, BIT(18), 0x1); /*enable_output for P_GPIO[2]*/ + /*odm_set_mac_reg(dm, 0x64, BIT(18), 0); */ + /*odm_set_mac_reg(dm, 0x44, BIT(28)|BIT(27), 0);*/ + /*odm_set_mac_reg(dm, 0x44, BIT(20) | BIT(19), 0x3);*/ /*enable_output for P_GPIO[4:3]*/ + /*odm_set_mac_reg(dm, 0x44, BIT(12)|BIT(11), 0);*/ /*output value*/ + /*odm_set_mac_reg(dm, 0x40, BIT(1)|BIT(0), 0);*/ /*GPIO function*/ + + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_USB) + odm_set_mac_reg(dm, 0x44, BIT(20) | BIT(19), 0x3); /*enable_output for P_GPIO[4:3]*/ + else if (dm->support_interface == ODM_ITRF_SDIO) + odm_set_mac_reg(dm, 0x44, BIT(18), 0x1); /*enable_output for P_GPIO[2]*/ } - p_dm_fat_table->is_become_linked = false; - p_dm_swat_table->try_flag = SWAW_STEP_INIT; - p_dm_swat_table->double_chk_flag = 0; + fat_tab->is_become_linked = false; + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->double_chk_flag = 0; } void phydm_update_rx_idle_antenna_8188F( - void *p_dm_void, + void *dm_void, u32 default_ant ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 codeword; - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - if (p_dm_odm->support_interface == ODM_ITRF_USB) { + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_USB) { if (default_ant == ANT1_2G) codeword = 1; /*2'b01*/ else codeword = 2;/*2'b10*/ - odm_set_mac_reg(p_dm_odm, 0x44, (BIT(12) | BIT11), codeword); /*GPIO[4:3] output value*/ - } else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) { + odm_set_mac_reg(dm, 0x44, (BIT(12) | BIT(11)), codeword); /*GPIO[4:3] output value*/ + } else if (dm->support_interface == ODM_ITRF_SDIO) { if (default_ant == ANT1_2G) { codeword = 0; /*1'b0*/ - odm_set_bb_reg(p_dm_odm, 0x870, BIT(9)|BIT8, 0x3); - odm_set_bb_reg(p_dm_odm, 0x860, BIT(9)|BIT8, 0x1); + odm_set_bb_reg(dm, 0x870, BIT(9)|BIT(8), 0x3); + odm_set_bb_reg(dm, 0x860, BIT(9)|BIT(8), 0x1); } else { codeword = 1;/*1'b1*/ - odm_set_bb_reg(p_dm_odm, 0x870, BIT(9)|BIT8, 0x3); - odm_set_bb_reg(p_dm_odm, 0x860, BIT(9)|BIT8, 0x2); + odm_set_bb_reg(dm, 0x870, BIT(9)|BIT(8), 0x3); + odm_set_bb_reg(dm, 0x860, BIT(9)|BIT(8), 0x2); } - odm_set_mac_reg(p_dm_odm, 0x44, BIT(10), codeword); /*GPIO[2] output value*/ + odm_set_mac_reg(dm, 0x44, BIT(10), codeword); /*GPIO[2] output value*/ } } } @@ -1949,53 +1820,53 @@ phydm_update_rx_idle_antenna_8188F( #ifdef ODM_EVM_ENHANCE_ANTDIV void phydm_evm_sw_antdiv_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; /*EVM enhance AntDiv method init----------------------------------------------------------------------*/ - p_dm_fat_table->EVM_method_enable = 0; - p_dm_fat_table->fat_state = NORMAL_STATE_MIAN; - p_dm_fat_table->fat_state_cnt = 0; - p_dm_fat_table->pre_antdiv_rssi = 0; - - p_dm_odm->antdiv_intvl = 30; - p_dm_odm->antdiv_train_num = 2; - odm_set_bb_reg(p_dm_odm, 0x910, 0x3f, 0xf); - p_dm_odm->antdiv_evm_en = 1; - /*p_dm_odm->antdiv_period=1;*/ - p_dm_odm->evm_antdiv_period = 3; - p_dm_odm->stop_antdiv_rssi_th = 3; - p_dm_odm->stop_antdiv_tp_th = 80; - p_dm_odm->antdiv_tp_period = 3; - p_dm_odm->stop_antdiv_tp_diff_th = 5; + fat_tab->evm_method_enable = 0; + fat_tab->fat_state = NORMAL_STATE_MIAN; + fat_tab->fat_state_cnt = 0; + fat_tab->pre_antdiv_rssi = 0; + + dm->antdiv_intvl = 30; + dm->antdiv_train_num = 2; + odm_set_bb_reg(dm, 0x910, 0x3f, 0xf); + dm->antdiv_evm_en = 1; + /*dm->antdiv_period=1;*/ + dm->evm_antdiv_period = 3; + dm->stop_antdiv_rssi_th = 3; + dm->stop_antdiv_tp_th = 80; + dm->antdiv_tp_period = 3; + dm->stop_antdiv_tp_diff_th = 5; } void odm_evm_fast_ant_reset( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - - p_dm_fat_table->EVM_method_enable = 0; - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - p_dm_fat_table->fat_state = NORMAL_STATE_MIAN; - p_dm_fat_table->fat_state_cnt = 0; - p_dm_odm->antdiv_period = 0; - odm_set_mac_reg(p_dm_odm, 0x608, BIT(8), 0); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + fat_tab->evm_method_enable = 0; + odm_ant_div_on_off(dm, ANTDIV_ON); + fat_tab->fat_state = NORMAL_STATE_MIAN; + fat_tab->fat_state_cnt = 0; + dm->antdiv_period = 0; + odm_set_mac_reg(dm, 0x608, BIT(8), 0); } void odm_evm_enhance_ant_div( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 main_rssi, aux_rssi ; u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1; u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0; @@ -2004,11 +1875,11 @@ odm_evm_enhance_ant_div( u32 main_2ss_evm_sum, aux_2ss_evm_sum; u8 score_EVM = 0, score_CRC = 0; u8 rssi_larger_ant = 0; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; u32 value32, i; boolean main_above1 = false, aux_above1 = false; boolean force_antenna = false; - struct sta_info *p_entry; + struct cmn_sta_info *sta; u32 antdiv_tp_main_avg, antdiv_tp_aux_avg; u8 curr_rssi, rssi_diff; u32 tp_diff; @@ -2017,16 +1888,16 @@ odm_evm_enhance_ant_div( u8 decision_evm_ss; u8 next_ant; - p_dm_fat_table->target_ant_enhance = 0xFF; + fat_tab->target_ant_enhance = 0xFF; - if ((p_dm_odm->support_ic_type & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) { - if (p_dm_odm->is_one_entry_only) { - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[One Client only]\n")); */ - i = p_dm_odm->one_entry_macid; - p_entry = p_dm_odm->p_odm_sta_info[i]; + if ((dm->support_ic_type & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) { + if (dm->is_one_entry_only) { + /* PHYDM_DBG(dm,DBG_ANT_DIV, "[One Client only]\n"); */ + i = dm->one_entry_macid; + sta = dm->phydm_sta_info[i]; - main_rssi = (p_dm_fat_table->main_ant_cnt[i] != 0) ? (p_dm_fat_table->main_ant_sum[i] / p_dm_fat_table->main_ant_cnt[i]) : 0; - aux_rssi = (p_dm_fat_table->aux_ant_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_sum[i] / p_dm_fat_table->aux_ant_cnt[i]) : 0; + main_rssi = (fat_tab->main_ant_cnt[i] != 0) ? (fat_tab->main_ant_sum[i] / fat_tab->main_ant_cnt[i]) : 0; + aux_rssi = (fat_tab->aux_ant_cnt[i] != 0) ? (fat_tab->aux_ant_sum[i] / fat_tab->aux_ant_cnt[i]) : 0; if ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF)) diff_rssi = FORCE_RSSI_DIFF; @@ -2038,139 +1909,136 @@ odm_evm_enhance_ant_div( else rssi_larger_ant = AUX_ANT; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Main_Cnt=(( %d )), main_rssi=(( %d ))\n", p_dm_fat_table->main_ant_cnt[i], main_rssi)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n", p_dm_fat_table->aux_ant_cnt[i], aux_rssi)); + PHYDM_DBG(dm, DBG_ANT_DIV, "Main_Cnt=(( %d )), main_rssi=(( %d ))\n", fat_tab->main_ant_cnt[i], main_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, "Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n", fat_tab->aux_ant_cnt[i], aux_rssi); - if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || (p_dm_fat_table->EVM_method_enable == 1)) + if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || (fat_tab->evm_method_enable == 1)) /* && (diff_rssi <= FORCE_RSSI_DIFF + 1) */ ) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("> TH_H || EVM_method_enable==1\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "> TH_H || evm_method_enable==1\n"); if (((main_rssi >= evm_rssi_th_low) || (aux_rssi >= evm_rssi_th_low))) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("> TH_L, fat_state_cnt =((%d))\n", p_dm_fat_table->fat_state_cnt)); + PHYDM_DBG(dm, DBG_ANT_DIV, "> TH_L, fat_state_cnt =((%d))\n", fat_tab->fat_state_cnt); /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/ - if (p_dm_fat_table->fat_state_cnt < ((p_dm_odm->antdiv_train_num)<<1)) { - - if (p_dm_fat_table->fat_state_cnt == 0) { + if (fat_tab->fat_state_cnt < ((dm->antdiv_train_num)<<1)) { + if (fat_tab->fat_state_cnt == 0) { /*Reset EVM 1SS Method */ - p_dm_fat_table->main_ant_evm_sum[i] = 0; - p_dm_fat_table->aux_ant_evm_sum[i] = 0; - p_dm_fat_table->main_ant_evm_cnt[i] = 0; - p_dm_fat_table->aux_ant_evm_cnt[i] = 0; + fat_tab->main_ant_evm_sum[i] = 0; + fat_tab->aux_ant_evm_sum[i] = 0; + fat_tab->main_ant_evm_cnt[i] = 0; + fat_tab->aux_ant_evm_cnt[i] = 0; /*Reset EVM 2SS Method */ - p_dm_fat_table->main_ant_evm_2ss_sum[i][0] = 0; - p_dm_fat_table->main_ant_evm_2ss_sum[i][1] = 0; - p_dm_fat_table->aux_ant_evm_2ss_sum[i][0] = 0; - p_dm_fat_table->aux_ant_evm_2ss_sum[i][1] = 0; - p_dm_fat_table->main_ant_evm_2ss_cnt[i] = 0; - p_dm_fat_table->aux_ant_evm_2ss_cnt[i] = 0; + fat_tab->main_ant_evm_2ss_sum[i][0] = 0; + fat_tab->main_ant_evm_2ss_sum[i][1] = 0; + fat_tab->aux_ant_evm_2ss_sum[i][0] = 0; + fat_tab->aux_ant_evm_2ss_sum[i][1] = 0; + fat_tab->main_ant_evm_2ss_cnt[i] = 0; + fat_tab->aux_ant_evm_2ss_cnt[i] = 0; #if 0 /*Reset TP Method */ - p_dm_fat_table->antdiv_tp_main = 0; - p_dm_fat_table->antdiv_tp_aux = 0; - p_dm_fat_table->antdiv_tp_main_cnt = 0; - p_dm_fat_table->antdiv_tp_aux_cnt = 0; + fat_tab->antdiv_tp_main = 0; + fat_tab->antdiv_tp_aux = 0; + fat_tab->antdiv_tp_main_cnt = 0; + fat_tab->antdiv_tp_aux_cnt = 0; #endif /*Reset CRC Method */ - p_dm_fat_table->main_crc32_ok_cnt = 0; - p_dm_fat_table->main_crc32_fail_cnt = 0; - p_dm_fat_table->aux_crc32_ok_cnt = 0; - p_dm_fat_table->aux_crc32_fail_cnt = 0; + fat_tab->main_crc32_ok_cnt = 0; + fat_tab->main_crc32_fail_cnt = 0; + fat_tab->aux_crc32_ok_cnt = 0; + fat_tab->aux_crc32_fail_cnt = 0; - #if SKIP_EVM_ANTDIV_TRAINING_PATCH - if ((*p_dm_odm->p_band_width == ODM_BW20M) && (p_entry->rf_mimo_mode == MIMO_2T2R)) { + #ifdef SKIP_EVM_ANTDIV_TRAINING_PATCH + if ((*dm->band_width == CHANNEL_WIDTH_20) && (sta->mimo_type == RF_2T2R)) { /*1. Skip training: RSSI*/ - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt)); - curr_rssi = (u8)((p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi); - rssi_diff = (curr_rssi > p_dm_fat_table->pre_antdiv_rssi) ? (curr_rssi - p_dm_fat_table->pre_antdiv_rssi) : (p_dm_fat_table->pre_antdiv_rssi - curr_rssi); + /*PHYDM_DBG(pDM_Odm,DBG_ANT_DIV, "TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt);*/ + curr_rssi = (u8)((fat_tab->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi); + rssi_diff = (curr_rssi > fat_tab->pre_antdiv_rssi) ? (curr_rssi - fat_tab->pre_antdiv_rssi) : (fat_tab->pre_antdiv_rssi - curr_rssi); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, p_dm_fat_table->pre_antdiv_rssi)); + PHYDM_DBG(dm, DBG_ANT_DIV, "[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, fat_tab->pre_antdiv_rssi); - p_dm_fat_table->pre_antdiv_rssi = curr_rssi; - if ((rssi_diff < (p_dm_odm->stop_antdiv_rssi_th)) && (curr_rssi != 0)) + fat_tab->pre_antdiv_rssi = curr_rssi; + if ((rssi_diff < (dm->stop_antdiv_rssi_th)) && (curr_rssi != 0)) rssi_return = 1; /*2. Skip training: TP Diff*/ - tp_diff = (p_dm_odm->rx_tp > p_dm_fat_table->pre_antdiv_tp) ? (p_dm_odm->rx_tp - p_dm_fat_table->pre_antdiv_tp) : (p_dm_fat_table->pre_antdiv_tp - p_dm_odm->rx_tp); + tp_diff = (dm->rx_tp > fat_tab->pre_antdiv_tp) ? (dm->rx_tp - fat_tab->pre_antdiv_tp) : (fat_tab->pre_antdiv_tp - dm->rx_tp); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", p_dm_odm->rx_tp, p_dm_fat_table->pre_antdiv_tp)); - p_dm_fat_table->pre_antdiv_tp = p_dm_odm->rx_tp; - if ((tp_diff < (u32)(p_dm_odm->stop_antdiv_tp_diff_th) && (p_dm_odm->rx_tp != 0))) + PHYDM_DBG(dm, DBG_ANT_DIV, "[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", dm->rx_tp, fat_tab->pre_antdiv_tp); + fat_tab->pre_antdiv_tp = dm->rx_tp; + if ((tp_diff < (u32)(dm->stop_antdiv_tp_diff_th) && (dm->rx_tp != 0))) tp_diff_return = 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[3] tp_return, curr_rx_tp=((%d))\n", p_dm_odm->rx_tp)); + PHYDM_DBG(dm, DBG_ANT_DIV, "[3] tp_return, curr_rx_tp=((%d))\n", dm->rx_tp); /*3. Skip training: TP*/ - if (p_dm_odm->rx_tp >= (u32)(p_dm_odm->stop_antdiv_tp_th)) + if (dm->rx_tp >= (u32)(dm->stop_antdiv_tp_th)) tp_return = 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return)); + PHYDM_DBG(dm, DBG_ANT_DIV, "[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return); /*4. Joint Return Decision*/ if (tp_return) { if (tp_diff_return || rssi_diff) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***Return EVM SW AntDiv\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***Return EVM SW AntDiv\n"); return; } } } #endif - p_dm_fat_table->EVM_method_enable = 1; - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - p_dm_odm->antdiv_period = p_dm_odm->evm_antdiv_period; - odm_set_mac_reg(p_dm_odm, 0x608, BIT8, 1); /*RCR accepts CRC32-Error packets*/ + fat_tab->evm_method_enable = 1; + odm_ant_div_on_off(dm, ANTDIV_OFF); + dm->antdiv_period = dm->evm_antdiv_period; + odm_set_mac_reg(dm, 0x608, BIT(8), 1); /*RCR accepts CRC32-Error packets*/ } - p_dm_fat_table->fat_state_cnt++; - next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - odm_update_rx_idle_ant(p_dm_odm, next_ant); - odm_set_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer, p_dm_odm->antdiv_intvl); //ms + fat_tab->fat_state_cnt++; + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + odm_update_rx_idle_ant(dm, next_ant); + odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_intvl); //ms } /*Decision state: 4==============================================================*/ else { - - p_dm_fat_table->fat_state_cnt = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Decisoin state ]\n")); + fat_tab->fat_state_cnt = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "[Decisoin state ]\n"); /* 3 [CRC32 statistic] */ #if 0 - if ((p_dm_fat_table->main_crc32_ok_cnt > ((p_dm_fat_table->aux_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == MAIN_ANT))) { - p_dm_fat_table->target_ant_crc32 = MAIN_ANT; + if ((fat_tab->main_crc32_ok_cnt > ((fat_tab->aux_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == MAIN_ANT))) { + fat_tab->target_ant_crc32 = MAIN_ANT; force_antenna = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Main\n")); - } else if ((p_dm_fat_table->aux_crc32_ok_cnt > ((p_dm_fat_table->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) { - p_dm_fat_table->target_ant_crc32 = AUX_ANT; + PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Main\n"); + } else if ((fat_tab->aux_crc32_ok_cnt > ((fat_tab->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) { + fat_tab->target_ant_crc32 = AUX_ANT; force_antenna = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Aux\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Aux\n"); } else #endif { - if (p_dm_fat_table->main_crc32_fail_cnt <= 5) - p_dm_fat_table->main_crc32_fail_cnt = 5; + if (fat_tab->main_crc32_fail_cnt <= 5) + fat_tab->main_crc32_fail_cnt = 5; - if (p_dm_fat_table->aux_crc32_fail_cnt <= 5) - p_dm_fat_table->aux_crc32_fail_cnt = 5; + if (fat_tab->aux_crc32_fail_cnt <= 5) + fat_tab->aux_crc32_fail_cnt = 5; - if (p_dm_fat_table->main_crc32_ok_cnt > p_dm_fat_table->main_crc32_fail_cnt) + if (fat_tab->main_crc32_ok_cnt > fat_tab->main_crc32_fail_cnt) main_above1 = true; - if (p_dm_fat_table->aux_crc32_ok_cnt > p_dm_fat_table->aux_crc32_fail_cnt) + if (fat_tab->aux_crc32_ok_cnt > fat_tab->aux_crc32_fail_cnt) aux_above1 = true; if (main_above1 == true && aux_above1 == false) { force_antenna = true; - p_dm_fat_table->target_ant_crc32 = MAIN_ANT; + fat_tab->target_ant_crc32 = MAIN_ANT; } else if (main_above1 == false && aux_above1 == true) { force_antenna = true; - p_dm_fat_table->target_ant_crc32 = AUX_ANT; + fat_tab->target_ant_crc32 = AUX_ANT; } else if (main_above1 == true && aux_above1 == true) { - main_crc_utility = ((p_dm_fat_table->main_crc32_ok_cnt) << 7) / p_dm_fat_table->main_crc32_fail_cnt; - aux_crc_utility = ((p_dm_fat_table->aux_crc32_ok_cnt) << 7) / p_dm_fat_table->aux_crc32_fail_cnt; - p_dm_fat_table->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT); + main_crc_utility = ((fat_tab->main_crc32_ok_cnt) << 7) / fat_tab->main_crc32_fail_cnt; + aux_crc_utility = ((fat_tab->aux_crc32_ok_cnt) << 7) / fat_tab->aux_crc32_fail_cnt; + fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT); if (main_crc_utility != 0 && aux_crc_utility != 0) { if (main_crc_utility >= aux_crc_utility) @@ -2179,14 +2047,14 @@ odm_evm_enhance_ant_div( utility_ratio = (aux_crc_utility << 1) / main_crc_utility; } } else if (main_above1 == false && aux_above1 == false) { - if (p_dm_fat_table->main_crc32_ok_cnt == 0) - p_dm_fat_table->main_crc32_ok_cnt = 1; - if (p_dm_fat_table->aux_crc32_ok_cnt == 0) - p_dm_fat_table->aux_crc32_ok_cnt = 1; + if (fat_tab->main_crc32_ok_cnt == 0) + fat_tab->main_crc32_ok_cnt = 1; + if (fat_tab->aux_crc32_ok_cnt == 0) + fat_tab->aux_crc32_ok_cnt = 1; - main_crc_utility = ((p_dm_fat_table->main_crc32_fail_cnt) << 7) / p_dm_fat_table->main_crc32_ok_cnt; - aux_crc_utility = ((p_dm_fat_table->aux_crc32_fail_cnt) << 7) / p_dm_fat_table->aux_crc32_ok_cnt; - p_dm_fat_table->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT); + main_crc_utility = ((fat_tab->main_crc32_fail_cnt) << 7) / fat_tab->main_crc32_ok_cnt; + aux_crc_utility = ((fat_tab->aux_crc32_fail_cnt) << 7) / fat_tab->aux_crc32_ok_cnt; + fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT); if (main_crc_utility != 0 && aux_crc_utility != 0) { if (main_crc_utility >= aux_crc_utility) @@ -2196,46 +2064,46 @@ odm_evm_enhance_ant_div( } } } - odm_set_mac_reg(p_dm_odm, 0x608, BIT(8), 0);/* NOT Accept CRC32 Error packets. */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", p_dm_fat_table->main_crc32_ok_cnt, p_dm_fat_table->main_crc32_fail_cnt, main_crc_utility)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", p_dm_fat_table->aux_crc32_ok_cnt, p_dm_fat_table->aux_crc32_fail_cnt, aux_crc_utility)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***1.TargetAnt_CRC32 = ((%s))\n", (p_dm_fat_table->target_ant_crc32 == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + odm_set_mac_reg(dm, 0x608, BIT(8), 0);/* NOT Accept CRC32 Error packets. */ + PHYDM_DBG(dm, DBG_ANT_DIV, "MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->main_crc32_ok_cnt, fat_tab->main_crc32_fail_cnt, main_crc_utility); + PHYDM_DBG(dm, DBG_ANT_DIV, "AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->aux_crc32_ok_cnt, fat_tab->aux_crc32_fail_cnt, aux_crc_utility); + PHYDM_DBG(dm, DBG_ANT_DIV, "***1.TargetAnt_CRC32 = ((%s))\n", (fat_tab->target_ant_crc32 == MAIN_ANT)?"MAIN_ANT":"AUX_ANT"); /* 3 [EVM statistic] */ /*1SS EVM*/ - main_1ss_evm = (p_dm_fat_table->main_ant_evm_cnt[i] != 0) ? (p_dm_fat_table->main_ant_evm_sum[i] / p_dm_fat_table->main_ant_evm_cnt[i]) : 0; - aux_1ss_evm = (p_dm_fat_table->aux_ant_evm_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_evm_sum[i] / p_dm_fat_table->aux_ant_evm_cnt[i]) : 0; - target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT); + main_1ss_evm = (fat_tab->main_ant_evm_cnt[i] != 0) ? (fat_tab->main_ant_evm_sum[i] / fat_tab->main_ant_evm_cnt[i]) : 0; + aux_1ss_evm = (fat_tab->aux_ant_evm_cnt[i] != 0) ? (fat_tab->aux_ant_evm_sum[i] / fat_tab->aux_ant_evm_cnt[i]) : 0; + target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (fat_tab->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Main1ss_EVM= (( %d ))\n", p_dm_fat_table->main_ant_evm_cnt[i], main_1ss_evm)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Aux_1ss_EVM = (( %d ))\n", p_dm_fat_table->main_ant_evm_cnt[i], aux_1ss_evm)); + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main1ss_EVM= (( %d ))\n", fat_tab->main_ant_evm_cnt[i], main_1ss_evm); + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_1ss_EVM = (( %d ))\n", fat_tab->main_ant_evm_cnt[i], aux_1ss_evm); /*2SS EVM*/ - main_2ss_evm[0] = (p_dm_fat_table->main_ant_evm_2ss_cnt[i] != 0) ? (p_dm_fat_table->main_ant_evm_2ss_sum[i][0] / p_dm_fat_table->main_ant_evm_2ss_cnt[i]) : 0; - main_2ss_evm[1] = (p_dm_fat_table->main_ant_evm_2ss_cnt[i] != 0) ? (p_dm_fat_table->main_ant_evm_2ss_sum[i][1] / p_dm_fat_table->main_ant_evm_2ss_cnt[i]) : 0; + main_2ss_evm[0] = (fat_tab->main_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->main_ant_evm_2ss_sum[i][0] / fat_tab->main_ant_evm_2ss_cnt[i]) : 0; + main_2ss_evm[1] = (fat_tab->main_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->main_ant_evm_2ss_sum[i][1] / fat_tab->main_ant_evm_2ss_cnt[i]) : 0; main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1]; - aux_2ss_evm[0] = (p_dm_fat_table->aux_ant_evm_2ss_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_evm_2ss_sum[i][0] / p_dm_fat_table->aux_ant_evm_2ss_cnt[i]) : 0; - aux_2ss_evm[1] = (p_dm_fat_table->aux_ant_evm_2ss_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_evm_2ss_sum[i][1] / p_dm_fat_table->aux_ant_evm_2ss_cnt[i]) : 0; + aux_2ss_evm[0] = (fat_tab->aux_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->aux_ant_evm_2ss_sum[i][0] / fat_tab->aux_ant_evm_2ss_cnt[i]) : 0; + aux_2ss_evm[1] = (fat_tab->aux_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->aux_ant_evm_2ss_sum[i][1] / fat_tab->aux_ant_evm_2ss_cnt[i]) : 0; aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1]; - target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT); + target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (fat_tab->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", - p_dm_fat_table->main_ant_evm_2ss_cnt[i], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", - p_dm_fat_table->aux_ant_evm_2ss_cnt[i], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum)); + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", + fat_tab->main_ant_evm_2ss_cnt[i], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum); + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", + fat_tab->aux_ant_evm_2ss_cnt[i], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum); if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) { decision_evm_ss = 2; main_evm = main_2ss_evm_sum; aux_evm = aux_2ss_evm_sum; - p_dm_fat_table->target_ant_evm = target_ant_evm_2ss; + fat_tab->target_ant_evm = target_ant_evm_2ss; } else { decision_evm_ss = 1; main_evm = main_1ss_evm; aux_evm = aux_1ss_evm; - p_dm_fat_table->target_ant_evm = target_ant_evm_1ss; + fat_tab->target_ant_evm = target_ant_evm_1ss; } if ((main_evm == 0 || aux_evm == 0)) @@ -2245,47 +2113,47 @@ odm_evm_enhance_ant_div( else diff_EVM = aux_evm - main_evm; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (p_dm_fat_table->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (fat_tab->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); //3 [TP statistic] - antdiv_tp_main_avg = (p_dm_fat_table->antdiv_tp_main_cnt != 0) ? (p_dm_fat_table->antdiv_tp_main / p_dm_fat_table->antdiv_tp_main_cnt) : 0; - antdiv_tp_aux_avg = (p_dm_fat_table->antdiv_tp_aux_cnt != 0) ? (p_dm_fat_table->antdiv_tp_aux / p_dm_fat_table->antdiv_tp_aux_cnt) : 0; - p_dm_fat_table->target_ant_tp = (antdiv_tp_main_avg == antdiv_tp_aux_avg) ? (p_dm_fat_table->pre_target_ant_enhance) : ((antdiv_tp_main_avg >= antdiv_tp_aux_avg) ? MAIN_ANT : AUX_ANT); + antdiv_tp_main_avg = (fat_tab->antdiv_tp_main_cnt != 0) ? (fat_tab->antdiv_tp_main / fat_tab->antdiv_tp_main_cnt) : 0; + antdiv_tp_aux_avg = (fat_tab->antdiv_tp_aux_cnt != 0) ? (fat_tab->antdiv_tp_aux / fat_tab->antdiv_tp_aux_cnt) : 0; + fat_tab->target_ant_tp = (antdiv_tp_main_avg == antdiv_tp_aux_avg) ? (fat_tab->pre_target_ant_enhance) : ((antdiv_tp_main_avg >= antdiv_tp_aux_avg) ? MAIN_ANT : AUX_ANT); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Main_TP = ((%d))\n", p_dm_fat_table->antdiv_tp_main_cnt, antdiv_tp_main_avg)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Cnt = ((%d)), Aux_TP = ((%d))\n", p_dm_fat_table->antdiv_tp_aux_cnt, antdiv_tp_aux_avg)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***3.TargetAnt_TP = ((%s))\n", (p_dm_fat_table->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main_TP = ((%d))\n", fat_tab->antdiv_tp_main_cnt, antdiv_tp_main_avg); + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_TP = ((%d))\n", fat_tab->antdiv_tp_aux_cnt, antdiv_tp_aux_avg); + PHYDM_DBG(dm, DBG_ANT_DIV, "***3.TargetAnt_TP = ((%s))\n", (fat_tab->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); /*Reset TP Method */ - p_dm_fat_table->antdiv_tp_main = 0; - p_dm_fat_table->antdiv_tp_aux = 0; - p_dm_fat_table->antdiv_tp_main_cnt = 0; - p_dm_fat_table->antdiv_tp_aux_cnt = 0; + fat_tab->antdiv_tp_main = 0; + fat_tab->antdiv_tp_aux = 0; + fat_tab->antdiv_tp_main_cnt = 0; + fat_tab->antdiv_tp_aux_cnt = 0; /* 2 [ Decision state ] */ - if (p_dm_fat_table->target_ant_evm == p_dm_fat_table->target_ant_crc32) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + if (fat_tab->target_ant_evm == fat_tab->target_ant_crc32) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); if ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30) - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->pre_target_ant_enhance; + fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance; else - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_evm; + fat_tab->target_ant_enhance = fat_tab->target_ant_evm; } #if 0 else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_crc32; + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); + fat_tab->target_ant_enhance = fat_tab->target_ant_crc32; } #endif else if (diff_EVM >= 20) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_evm; + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); + fat_tab->target_ant_enhance = fat_tab->target_ant_evm; } else if (utility_ratio >= 6 && force_antenna == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_crc32; + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); + fat_tab->target_ant_enhance = fat_tab->target_ant_crc32; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); if (force_antenna == true) score_CRC = 2; @@ -2306,170 +2174,171 @@ odm_evm_enhance_ant_div( score_EVM = 0; if (score_CRC > score_EVM) - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_crc32; + fat_tab->target_ant_enhance = fat_tab->target_ant_crc32; else if (score_CRC < score_EVM) - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_evm; + fat_tab->target_ant_enhance = fat_tab->target_ant_evm; else - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->pre_target_ant_enhance; + fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance; } - p_dm_fat_table->pre_target_ant_enhance = p_dm_fat_table->target_ant_enhance; + fat_tab->pre_target_ant_enhance = fat_tab->target_ant_enhance; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** 4.TargetAnt_enhance = (( %s ))******\n", (p_dm_fat_table->target_ant_enhance == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** 4.TargetAnt_enhance = (( %s ))******\n", (fat_tab->target_ant_enhance == MAIN_ANT)?"MAIN_ANT":"AUX_ANT"); } } else { /* RSSI< = evm_rssi_th_low */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ TH_L ]\n")); - odm_evm_fast_ant_reset(p_dm_odm); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ TH_L ]\n"); + odm_evm_fast_ant_reset(dm); } } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[escape from> TH_H || EVM_method_enable==1]\n")); - odm_evm_fast_ant_reset(p_dm_odm); + PHYDM_DBG(dm, DBG_ANT_DIV, "[escape from> TH_H || evm_method_enable==1]\n"); + odm_evm_fast_ant_reset(dm); } } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[multi-Client]\n")); - odm_evm_fast_ant_reset(p_dm_odm); + PHYDM_DBG(dm, DBG_ANT_DIV, "[multi-Client]\n"); + odm_evm_fast_ant_reset(dm); } } } void odm_evm_fast_ant_training_callback( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******AntDiv_Callback******\n")); - odm_hw_ant_div(p_dm_odm); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "******AntDiv_Callback******\n"); + odm_hw_ant_div(dm); } #endif void odm_hw_ant_div( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0, local_max_rssi; u32 main_rssi, aux_rssi, mian_cnt, aux_cnt; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u8 rx_idle_ant = p_dm_fat_table->rx_idle_ant, target_ant = 7; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct sta_info *p_entry; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 rx_idle_ant = fat_tab->rx_idle_ant, target_ant = 7; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct cmn_sta_info *sta; #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; u32 TH1 = 500000; u32 TH2 = 10000000; u32 ma_rx_temp, degrade_TP_temp, improve_TP_temp; u8 monitor_rssi_threshold = 30; - p_dm_bdc_table->BF_pass = true; - p_dm_bdc_table->DIV_pass = true; - p_dm_bdc_table->is_all_div_sta_idle = true; - p_dm_bdc_table->is_all_bf_sta_idle = true; - p_dm_bdc_table->num_bf_tar = 0 ; - p_dm_bdc_table->num_div_tar = 0; - p_dm_bdc_table->num_client = 0; + dm_bdc_table->BF_pass = true; + dm_bdc_table->DIV_pass = true; + dm_bdc_table->is_all_div_sta_idle = true; + dm_bdc_table->is_all_bf_sta_idle = true; + dm_bdc_table->num_bf_tar = 0 ; + dm_bdc_table->num_div_tar = 0; + dm_bdc_table->num_client = 0; #endif #endif - if (!p_dm_odm->is_linked) { /* is_linked==False */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + if (!dm->is_linked) { /* is_linked==False */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); - if (p_dm_fat_table->is_become_linked == true) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); - p_dm_odm->antdiv_period = 0; + if (fat_tab->is_become_linked == true) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_update_rx_idle_ant(dm, MAIN_ANT); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + dm->antdiv_period = 0; - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + fat_tab->is_become_linked = dm->is_linked; } return; } else { - if (p_dm_fat_table->is_become_linked == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - /*odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC);*/ + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n"); + odm_ant_div_on_off(dm, ANTDIV_ON); + /*odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);*/ - /* if(p_dm_odm->support_ic_type == ODM_RTL8821 ) */ - /* odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); */ /* CCK AntDiv function disable */ + /* if(dm->support_ic_type == ODM_RTL8821 ) */ + /* odm_set_bb_reg(dm, 0x800, BIT(25), 0); */ /* CCK AntDiv function disable */ /* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ - /* else if(p_dm_odm->support_ic_type == ODM_RTL8881A) */ - /* odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); */ /* CCK AntDiv function disable */ + /* else if(dm->support_ic_type == ODM_RTL8881A) */ + /* odm_set_bb_reg(dm, 0x800, BIT(25), 0); */ /* CCK AntDiv function disable */ /* #endif */ - /* else if(p_dm_odm->support_ic_type == ODM_RTL8723B ||p_dm_odm->support_ic_type == ODM_RTL8812) */ - /* odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); */ /* CCK AntDiv function disable */ + /* else if(dm->support_ic_type == ODM_RTL8723B ||dm->support_ic_type == ODM_RTL8812) */ + /* odm_set_bb_reg(dm, 0xA00, BIT(15), 0); */ /* CCK AntDiv function disable */ - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + fat_tab->is_become_linked = dm->is_linked; - if (p_dm_odm->support_ic_type == ODM_RTL8723B && p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) { - odm_set_bb_reg(p_dm_odm, 0x930, 0xF0, 8); /* DPDT_P = ANTSEL[0] */ /* for 8723B AntDiv function patch. BB Dino 130412 */ - odm_set_bb_reg(p_dm_odm, 0x930, 0xF, 8); /* DPDT_N = ANTSEL[0] */ + if (dm->support_ic_type == ODM_RTL8723B && dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_set_bb_reg(dm, 0x930, 0xF0, 8); /* DPDT_P = ANTSEL[0] */ /* for 8723B AntDiv function patch. BB Dino 130412 */ + odm_set_bb_reg(dm, 0x930, 0xF, 8); /* DPDT_N = ANTSEL[0] */ } /* 2 BDC Init */ #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - odm_bdc_init(p_dm_odm); + odm_bdc_init(dm); #endif #endif #ifdef ODM_EVM_ENHANCE_ANTDIV - odm_evm_fast_ant_reset(p_dm_odm); + odm_evm_fast_ant_reset(dm); #endif } } - if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) { - if (p_dm_odm->is_one_entry_only == true) - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + if (*fat_tab->p_force_tx_ant_by_desc == false) { + if (dm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); else - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); } #ifdef ODM_EVM_ENHANCE_ANTDIV - if (p_dm_odm->antdiv_evm_en == 1) { - odm_evm_enhance_ant_div(p_dm_odm); - if (p_dm_fat_table->fat_state_cnt != 0) + if (dm->antdiv_evm_en == 1) { + odm_evm_enhance_ant_div(dm); + if (fat_tab->fat_state_cnt != 0) return; } else - odm_evm_fast_ant_reset(p_dm_odm); + odm_evm_fast_ant_reset(dm); #endif /* 2 BDC mode Arbitration */ #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (p_dm_odm->antdiv_evm_en == 0 || p_dm_fat_table->EVM_method_enable == 0) - odm_bf_ant_div_mode_arbitration(p_dm_odm); + if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0) + odm_bf_ant_div_mode_arbitration(dm); #endif #endif for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { + sta = dm->phydm_sta_info[i]; + if (is_sta_active(sta)) { /* 2 Caculate RSSI per Antenna */ - if ((p_dm_fat_table->main_ant_cnt[i] != 0) || (p_dm_fat_table->aux_ant_cnt[i] != 0)) { - mian_cnt = p_dm_fat_table->main_ant_cnt[i]; - aux_cnt = p_dm_fat_table->aux_ant_cnt[i]; - main_rssi = (mian_cnt != 0) ? (p_dm_fat_table->main_ant_sum[i] / mian_cnt) : 0; - aux_rssi = (aux_cnt != 0) ? (p_dm_fat_table->aux_ant_sum[i] / aux_cnt) : 0; - target_ant = (mian_cnt == aux_cnt) ? p_dm_fat_table->rx_idle_ant : ((mian_cnt >= aux_cnt) ? MAIN_ANT : AUX_ANT); /*Use counter number for OFDM*/ + if ((fat_tab->main_ant_cnt[i] != 0) || (fat_tab->aux_ant_cnt[i] != 0)) { + mian_cnt = fat_tab->main_ant_cnt[i]; + aux_cnt = fat_tab->aux_ant_cnt[i]; + main_rssi = (mian_cnt != 0) ? (fat_tab->main_ant_sum[i] / mian_cnt) : 0; + aux_rssi = (aux_cnt != 0) ? (fat_tab->aux_ant_sum[i] / aux_cnt) : 0; + target_ant = (mian_cnt == aux_cnt) ? fat_tab->rx_idle_ant : ((mian_cnt >= aux_cnt) ? MAIN_ANT : AUX_ANT); /*Use counter number for OFDM*/ } else { /*CCK only case*/ - mian_cnt = p_dm_fat_table->main_ant_cnt_cck[i]; - aux_cnt = p_dm_fat_table->aux_ant_cnt_cck[i]; - main_rssi = (mian_cnt != 0) ? (p_dm_fat_table->main_ant_sum_cck[i] / mian_cnt) : 0; - aux_rssi = (aux_cnt != 0) ? (p_dm_fat_table->aux_ant_sum_cck[i] / aux_cnt) : 0; - target_ant = (main_rssi == aux_rssi) ? p_dm_fat_table->rx_idle_ant : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); /*Use RSSI for CCK only case*/ + mian_cnt = fat_tab->main_ant_cnt_cck[i]; + aux_cnt = fat_tab->aux_ant_cnt_cck[i]; + main_rssi = (mian_cnt != 0) ? (fat_tab->main_ant_sum_cck[i] / mian_cnt) : 0; + aux_rssi = (aux_cnt != 0) ? (fat_tab->aux_ant_sum_cck[i] / aux_cnt) : 0; + target_ant = (main_rssi == aux_rssi) ? fat_tab->rx_idle_ant : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); /*Use RSSI for CCK only case*/ } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Main_Cnt = (( %d )) , CCK_Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", i, p_dm_fat_table->main_ant_cnt[i], p_dm_fat_table->main_ant_cnt_cck[i], main_rssi)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Aux_Cnt = (( %d )) , CCK_Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", i, p_dm_fat_table->aux_ant_cnt[i], p_dm_fat_table->aux_ant_cnt_cck[i], aux_rssi)); - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i ,( target_ant ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); */ + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : Main_Cnt = (( %d )) , CCK_Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", i, fat_tab->main_ant_cnt[i], fat_tab->main_ant_cnt_cck[i], main_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : Aux_Cnt = (( %d )) , CCK_Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", i, fat_tab->aux_ant_cnt[i], fat_tab->aux_ant_cnt_cck[i], aux_rssi); + /* PHYDM_DBG(dm,DBG_ANT_DIV, "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i ,( target_ant ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"); */ local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi; /* 2 Select max_rssi for DIG */ @@ -2485,23 +2354,23 @@ odm_hw_ant_div( } #ifdef ODM_EVM_ENHANCE_ANTDIV - if (p_dm_odm->antdiv_evm_en == 1) { - if (p_dm_fat_table->target_ant_enhance != 0xFF) { - target_ant = p_dm_fat_table->target_ant_enhance; - rx_idle_ant = p_dm_fat_table->target_ant_enhance; + if (dm->antdiv_evm_en == 1) { + if (fat_tab->target_ant_enhance != 0xFF) { + target_ant = fat_tab->target_ant_enhance; + rx_idle_ant = fat_tab->target_ant_enhance; } } #endif /* 2 Select TX Antenna */ - if (p_dm_odm->ant_div_type != CGCS_RX_HW_ANTDIV) { + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) { #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (p_dm_bdc_table->w_bfee_client[i] == 0) + if (dm_bdc_table->w_bfee_client[i] == 0) #endif #endif { - odm_update_tx_ant(p_dm_odm, target_ant, i); + odm_update_tx_ant(dm, target_ant, i); } } @@ -2510,52 +2379,52 @@ odm_hw_ant_div( #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - p_dm_bdc_table->num_client++; + dm_bdc_table->num_client++; - if (p_dm_bdc_table->bdc_mode == BDC_MODE_2 || p_dm_bdc_table->bdc_mode == BDC_MODE_3) { + if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) { /* 2 Byte counter */ - ma_rx_temp = (p_entry->rx_byte_cnt_low_maw) << 3 ; /* RX TP ( bit /sec) */ + ma_rx_temp = sta->rx_moving_average_tp; /* RX TP ( bit /sec) */ - if (p_dm_bdc_table->BDC_state == bdc_bfer_train_state) - p_dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp ; + if (dm_bdc_table->BDC_state == bdc_bfer_train_state) + dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp ; else - p_dm_bdc_table->MA_rx_TP[i] = ma_rx_temp ; + dm_bdc_table->MA_rx_TP[i] = ma_rx_temp ; if ((ma_rx_temp < TH2) && (ma_rx_temp > TH1) && (local_max_rssi <= monitor_rssi_threshold)) { - if (p_dm_bdc_table->w_bfer_client[i] == 1) { /* Bfer_Target */ - p_dm_bdc_table->num_bf_tar++; + if (dm_bdc_table->w_bfer_client[i] == 1) { /* Bfer_Target */ + dm_bdc_table->num_bf_tar++; - if (p_dm_bdc_table->BDC_state == BDC_DECISION_STATE && p_dm_bdc_table->bdc_try_flag == 0) { - improve_TP_temp = (p_dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3 ; /* * 1.125 */ - p_dm_bdc_table->BF_pass = (p_dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d }\n", i, p_dm_bdc_table->MA_rx_TP[i], improve_TP_temp, p_dm_bdc_table->MA_rx_TP_DIV[i], p_dm_bdc_table->BF_pass)); + if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) { + improve_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3 ; /* * 1.125 */ + dm_bdc_table->BF_pass = (dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false; + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], improve_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->BF_pass); } } else { /* DIV_Target */ - p_dm_bdc_table->num_div_tar++; + dm_bdc_table->num_div_tar++; - if (p_dm_bdc_table->BDC_state == BDC_DECISION_STATE && p_dm_bdc_table->bdc_try_flag == 0) { - degrade_TP_temp = (p_dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* * 0.625 */ - p_dm_bdc_table->DIV_pass = (p_dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d }\n", i, p_dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, p_dm_bdc_table->MA_rx_TP_DIV[i], p_dm_bdc_table->DIV_pass)); + if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) { + degrade_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* * 0.625 */ + dm_bdc_table->DIV_pass = (dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false; + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->DIV_pass); } } } if (ma_rx_temp > TH1) { - if (p_dm_bdc_table->w_bfer_client[i] == 1) /* Bfer_Target */ - p_dm_bdc_table->is_all_bf_sta_idle = false; + if (dm_bdc_table->w_bfer_client[i] == 1) /* Bfer_Target */ + dm_bdc_table->is_all_bf_sta_idle = false; else/* DIV_Target */ - p_dm_bdc_table->is_all_div_sta_idle = false; + dm_bdc_table->is_all_div_sta_idle = false; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { BFmeeCap, BFmerCap} = { %d , %d }\n", i, p_dm_bdc_table->w_bfee_client[i], p_dm_bdc_table->w_bfer_client[i])); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : { BFmeeCap, BFmerCap} = { %d , %d }\n", i, dm_bdc_table->w_bfee_client[i], dm_bdc_table->w_bfer_client[i]); - if (p_dm_bdc_table->BDC_state == bdc_bfer_train_state) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP_DIV = (( %d ))\n", i, p_dm_bdc_table->MA_rx_TP_DIV[i])); + if (dm_bdc_table->BDC_state == bdc_bfer_train_state) + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : MA_rx_TP_DIV = (( %d ))\n", i, dm_bdc_table->MA_rx_TP_DIV[i]); else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP = (( %d ))\n", i, p_dm_bdc_table->MA_rx_TP[i])); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : MA_rx_TP = (( %d ))\n", i, dm_bdc_table->MA_rx_TP[i]); } #endif @@ -2565,11 +2434,11 @@ odm_hw_ant_div( #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (p_dm_bdc_table->bdc_try_flag == 0) + if (dm_bdc_table->bdc_try_flag == 0) #endif #endif { - phydm_antdiv_reset_statistic(p_dm_odm, i); + phydm_antdiv_reset_statistic(dm, i); } } @@ -2577,28 +2446,28 @@ odm_hw_ant_div( /* 2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */ #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** rx_idle_ant = (( %s ))\n", (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** rx_idle_ant = (( %s ))\n", (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (p_dm_bdc_table->bdc_mode == BDC_MODE_1 || p_dm_bdc_table->bdc_mode == BDC_MODE_3) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** bdc_rx_idle_update_counter = (( %d ))\n", p_dm_bdc_table->bdc_rx_idle_update_counter)); + if (dm_bdc_table->bdc_mode == BDC_MODE_1 || dm_bdc_table->bdc_mode == BDC_MODE_3) { + PHYDM_DBG(dm, DBG_ANT_DIV, "*** bdc_rx_idle_update_counter = (( %d ))\n", dm_bdc_table->bdc_rx_idle_update_counter); - if (p_dm_bdc_table->bdc_rx_idle_update_counter == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***Update RxIdle Antenna!!!\n")); - p_dm_bdc_table->bdc_rx_idle_update_counter = 30; - odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); + if (dm_bdc_table->bdc_rx_idle_update_counter == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, "***Update RxIdle Antenna!!!\n"); + dm_bdc_table->bdc_rx_idle_update_counter = 30; + odm_update_rx_idle_ant(dm, rx_idle_ant); } else { - p_dm_bdc_table->bdc_rx_idle_update_counter--; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n")); + dm_bdc_table->bdc_rx_idle_update_counter--; + PHYDM_DBG(dm, DBG_ANT_DIV, "***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n"); } } else #endif #endif - odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); + odm_update_rx_idle_ant(dm, rx_idle_ant); #else - odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); + odm_update_rx_idle_ant(dm, rx_idle_ant); #endif/* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ @@ -2607,18 +2476,20 @@ odm_hw_ant_div( /* 2 BDC Main Algorithm */ #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (p_dm_odm->antdiv_evm_en == 0 || p_dm_fat_table->EVM_method_enable == 0) - odm_bd_ccoex_bfee_rx_div_arbitration(p_dm_odm); + if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0) + odm_bd_ccoex_bfee_rx_div_arbitration(dm); + + dm_bdc_table->num_txbfee_client = 0; + dm_bdc_table->num_txbfer_client = 0; #endif #endif if (ant_div_max_rssi == 0) - p_dm_dig_table->ant_div_rssi_max = p_dm_odm->rssi_min; + dig_t->ant_div_rssi_max = dm->rssi_min; else - p_dm_dig_table->ant_div_rssi_max = ant_div_max_rssi; + dig_t->ant_div_rssi_max = ant_div_max_rssi; - p_dm_dig_table->RSSI_max = max_rssi; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***AntDiv End***\n\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "***AntDiv End***\n\n"); } @@ -2627,109 +2498,105 @@ odm_hw_ant_div( void odm_s0s1_sw_ant_div_reset( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - p_dm_fat_table->is_become_linked = false; - p_dm_swat_table->try_flag = SWAW_STEP_INIT; - p_dm_swat_table->double_chk_flag = 0; + fat_tab->is_become_linked = false; + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->double_chk_flag = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_s0s1_sw_ant_div_reset(): p_dm_fat_table->is_become_linked = %d\n", p_dm_fat_table->is_become_linked)); + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_s0s1_sw_ant_div_reset(): fat_tab->is_become_linked = %d\n", fat_tab->is_become_linked); } void odm_s0s1_sw_ant_div( - void *p_dm_void, + void *dm_void, u8 step ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; u32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi; u32 main_rssi, aux_rssi; u8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0, train_time_temp; u8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0; - u8 rx_idle_ant = p_dm_swat_table->pre_antenna, target_ant, next_ant = 0; - struct sta_info *p_entry = NULL; + u8 rx_idle_ant = dm_swat_table->pre_antenna, target_ant, next_ant = 0; + struct cmn_sta_info *entry = NULL; u32 value32; - u32 main_ant_sum; - u32 aux_ant_sum; - u32 main_ant_cnt; - u32 aux_ant_cnt; - - - if (!p_dm_odm->is_linked) { /* is_linked==False */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - if (p_dm_fat_table->is_become_linked == true) { - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); - odm_set_bb_reg(p_dm_odm, 0x948, (BIT(9) | BIT(8) | BIT(7) | BIT(6)), 0x0); + u32 main_ant_sum = 0; + u32 aux_ant_sum = 0; + u32 main_ant_cnt = 0; + u32 aux_ant_cnt = 0; + + + if (!dm->is_linked) { /* is_linked==False */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); + if (fat_tab->is_become_linked == true) { + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + if (dm->support_ic_type == ODM_RTL8723B) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Set REG 948[9:6]=0x0\n"); + odm_set_bb_reg(dm, 0x948, (BIT(9) | BIT(8) | BIT(7) | BIT(6)), 0x0); } - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + fat_tab->is_become_linked = dm->is_linked; } return; } else { - if (p_dm_fat_table->is_become_linked == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n"); - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - value32 = odm_get_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT(4) | BIT(3)); + if (dm->support_ic_type == ODM_RTL8723B) { + value32 = odm_get_bb_reg(dm, 0x864, BIT(5) | BIT(4) | BIT(3)); #if (RTL8723B_SUPPORT == 1) if (value32 == 0x0) - odm_update_rx_idle_ant_8723b(p_dm_odm, MAIN_ANT, ANT1_2G, ANT2_2G); + odm_update_rx_idle_ant_8723b(dm, MAIN_ANT, ANT1_2G, ANT2_2G); else if (value32 == 0x1) - odm_update_rx_idle_ant_8723b(p_dm_odm, AUX_ANT, ANT2_2G, ANT1_2G); + odm_update_rx_idle_ant_8723b(dm, AUX_ANT, ANT2_2G, ANT1_2G); #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B: First link! Force antenna to %s\n", (value32 == 0x0 ? "MAIN" : "AUX"))); + PHYDM_DBG(dm, DBG_ANT_DIV, "8723B: First link! Force antenna to %s\n", (value32 == 0x0 ? "MAIN" : "AUX")); } - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + fat_tab->is_become_linked = dm->is_linked; } } - if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) { - if (p_dm_odm->is_one_entry_only == true) - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + if (*fat_tab->p_force_tx_ant_by_desc == false) { + if (dm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); else - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n", - __LINE__, p_dm_swat_table->try_flag, step, p_dm_swat_table->double_chk_flag)); + PHYDM_DBG(dm, DBG_ANT_DIV, "[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n", + __LINE__, dm_swat_table->try_flag, step, dm_swat_table->double_chk_flag); /* Handling step mismatch condition. */ /* Peak step is not finished at last time. Recover the variable and check again. */ - if (step != p_dm_swat_table->try_flag) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[step != try_flag] Need to Reset After Link\n")); - odm_sw_ant_div_rest_after_link(p_dm_odm); + if (step != dm_swat_table->try_flag) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[step != try_flag] Need to Reset After Link\n"); + odm_sw_ant_div_rest_after_link(dm); } - if (p_dm_swat_table->try_flag == SWAW_STEP_INIT) { - - p_dm_swat_table->try_flag = SWAW_STEP_PEEK; - p_dm_swat_table->train_time_flag = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag = 0] Prepare for peek!\n\n")); + if (dm_swat_table->try_flag == SWAW_STEP_INIT) { + dm_swat_table->try_flag = SWAW_STEP_PEEK; + dm_swat_table->train_time_flag = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "[set try_flag = 0] Prepare for peek!\n\n"); return; } else { - /* 1 Normal state (Begin Trying) */ - if (p_dm_swat_table->try_flag == SWAW_STEP_PEEK) { + if (dm_swat_table->try_flag == SWAW_STEP_PEEK) { + PHYDM_DBG(dm, DBG_ANT_DIV, "TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n", dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->traffic_load); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n", p_dm_odm->cur_tx_ok_cnt, p_dm_odm->cur_rx_ok_cnt, p_dm_odm->traffic_load)); + if (dm->traffic_load == TRAFFIC_HIGH) { + train_time_temp = dm_swat_table->train_time ; - if (p_dm_odm->traffic_load == TRAFFIC_HIGH) { - train_time_temp = p_dm_swat_table->train_time ; - - if (p_dm_swat_table->train_time_flag == 3) { + if (dm_swat_table->train_time_flag == 3) { high_traffic_train_time_l = 0xa; if (train_time_temp <= 16) @@ -2737,23 +2604,23 @@ odm_s0s1_sw_ant_div( else train_time_temp -= 16; - } else if (p_dm_swat_table->train_time_flag == 2) { + } else if (dm_swat_table->train_time_flag == 2) { train_time_temp -= 8; high_traffic_train_time_l = 0xf; - } else if (p_dm_swat_table->train_time_flag == 1) { + } else if (dm_swat_table->train_time_flag == 1) { train_time_temp -= 4; high_traffic_train_time_l = 0x1e; - } else if (p_dm_swat_table->train_time_flag == 0) { + } else if (dm_swat_table->train_time_flag == 0) { train_time_temp += 8; high_traffic_train_time_l = 0x28; } - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_SDIO) high_traffic_train_time_l += 0xa; } - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** train_time_temp = ((%d))\n",train_time_temp)); */ + /* PHYDM_DBG(dm,DBG_ANT_DIV, "*** train_time_temp = ((%d))\n",train_time_temp); */ /* -- */ if (train_time_temp > high_traffic_train_time_u) @@ -2762,34 +2629,32 @@ odm_s0s1_sw_ant_div( else if (train_time_temp < high_traffic_train_time_l) train_time_temp = high_traffic_train_time_l; - p_dm_swat_table->train_time = train_time_temp; /*10ms~200ms*/ - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("train_time_flag=((%d)), train_time=((%d))\n", p_dm_swat_table->train_time_flag, p_dm_swat_table->train_time)); + dm_swat_table->train_time = train_time_temp; /*10ms~200ms*/ - } else if ((p_dm_odm->traffic_load == TRAFFIC_MID) || (p_dm_odm->traffic_load == TRAFFIC_LOW)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "train_time_flag=((%d)), train_time=((%d))\n", dm_swat_table->train_time_flag, dm_swat_table->train_time); - train_time_temp = p_dm_swat_table->train_time ; + } else if ((dm->traffic_load == TRAFFIC_MID) || (dm->traffic_load == TRAFFIC_LOW)) { + train_time_temp = dm_swat_table->train_time ; - if (p_dm_swat_table->train_time_flag == 3) { + if (dm_swat_table->train_time_flag == 3) { low_traffic_train_time_l = 10; if (train_time_temp < 50) train_time_temp = low_traffic_train_time_l; else train_time_temp -= 50; - } else if (p_dm_swat_table->train_time_flag == 2) { + } else if (dm_swat_table->train_time_flag == 2) { train_time_temp -= 30; low_traffic_train_time_l = 36; - } else if (p_dm_swat_table->train_time_flag == 1) { + } else if (dm_swat_table->train_time_flag == 1) { train_time_temp -= 10; low_traffic_train_time_l = 40; } else { - train_time_temp += 10; low_traffic_train_time_l = 50; } - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_SDIO) low_traffic_train_time_l += 10; } @@ -2800,208 +2665,226 @@ odm_s0s1_sw_ant_div( else if (train_time_temp <= low_traffic_train_time_l) train_time_temp = low_traffic_train_time_l; - p_dm_swat_table->train_time = train_time_temp; /*10ms~200ms*/ + dm_swat_table->train_time = train_time_temp; /*10ms~200ms*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("train_time_flag=((%d)) , train_time=((%d))\n", p_dm_swat_table->train_time_flag, p_dm_swat_table->train_time)); + PHYDM_DBG(dm, DBG_ANT_DIV, "train_time_flag=((%d)) , train_time=((%d))\n", dm_swat_table->train_time_flag, dm_swat_table->train_time); } else { - p_dm_swat_table->train_time = 0xc8; /*200ms*/ + dm_swat_table->train_time = 0xc8; /*200ms*/ } /* ----------------- */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Current min_max_rssi is ((%d))\n", p_dm_fat_table->min_max_rssi)); + PHYDM_DBG(dm, DBG_ANT_DIV, "Current min_max_rssi is ((%d))\n", fat_tab->min_max_rssi); /* ---reset index--- */ - if (p_dm_swat_table->reset_idx >= RSSI_CHECK_RESET_PERIOD) { - - p_dm_fat_table->min_max_rssi = 0; - p_dm_swat_table->reset_idx = 0; + if (dm_swat_table->reset_idx >= RSSI_CHECK_RESET_PERIOD) { + fat_tab->min_max_rssi = 0; + dm_swat_table->reset_idx = 0; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reset_idx = (( %d ))\n", p_dm_swat_table->reset_idx)); + PHYDM_DBG(dm, DBG_ANT_DIV, "reset_idx = (( %d ))\n", dm_swat_table->reset_idx); - p_dm_swat_table->reset_idx++; + dm_swat_table->reset_idx++; /* ---double check flag--- */ - if ((p_dm_fat_table->min_max_rssi > RSSI_CHECK_THRESHOLD) && (p_dm_swat_table->double_chk_flag == 0)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" min_max_rssi is ((%d)), and > %d\n", - p_dm_fat_table->min_max_rssi, RSSI_CHECK_THRESHOLD)); - - p_dm_swat_table->double_chk_flag = 1; - p_dm_swat_table->try_flag = SWAW_STEP_DETERMINE; - p_dm_swat_table->rssi_trying = 0; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Test the current ant for (( %d )) ms again\n", p_dm_swat_table->train_time)); - odm_update_rx_idle_ant(p_dm_odm, p_dm_fat_table->rx_idle_ant); - odm_set_timer(p_dm_odm, &(p_dm_swat_table->phydm_sw_antenna_switch_timer), p_dm_swat_table->train_time); /*ms*/ + if ((fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD) && (dm_swat_table->double_chk_flag == 0)) { + PHYDM_DBG(dm, DBG_ANT_DIV, " min_max_rssi is ((%d)), and > %d\n", + fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD); + + dm_swat_table->double_chk_flag = 1; + dm_swat_table->try_flag = SWAW_STEP_DETERMINE; + dm_swat_table->rssi_trying = 0; + + PHYDM_DBG(dm, DBG_ANT_DIV, "Test the current ant for (( %d )) ms again\n", dm_swat_table->train_time); + odm_update_rx_idle_ant(dm, fat_tab->rx_idle_ant); + odm_set_timer(dm, + &dm_swat_table->phydm_sw_antenna_switch_timer, + dm_swat_table->train_time); /*ms*/ return; } - next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - p_dm_swat_table->try_flag = SWAW_STEP_DETERMINE; + dm_swat_table->try_flag = SWAW_STEP_DETERMINE; - if (p_dm_swat_table->reset_idx <= 1) - p_dm_swat_table->rssi_trying = 2; + if (dm_swat_table->reset_idx <= 1) + dm_swat_table->rssi_trying = 2; else - p_dm_swat_table->rssi_trying = 1; + dm_swat_table->rssi_trying = 1; - odm_s0s1_sw_ant_div_by_ctrl_frame(p_dm_odm, SWAW_STEP_PEEK); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=1] Normal state: Begin Trying!!\n")); + odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_PEEK); + PHYDM_DBG(dm, DBG_ANT_DIV, "[set try_flag=1] Normal state: Begin Trying!!\n"); - } else if ((p_dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (p_dm_swat_table->double_chk_flag == 0)) { - - next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - p_dm_swat_table->rssi_trying--; + } else if ((dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (dm_swat_table->double_chk_flag == 0)) { + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + dm_swat_table->rssi_trying--; } /* 1 Decision state */ - if ((p_dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (p_dm_swat_table->rssi_trying == 0)) { - + if ((dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (dm_swat_table->rssi_trying == 0)) { boolean is_by_ctrl_frame = false; u64 pkt_cnt_total = 0; for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { + entry = dm->phydm_sta_info[i]; + if (is_sta_active(entry)) { /* 2 Caculate RSSI per Antenna */ - - main_ant_sum = (u32)p_dm_fat_table->main_ant_sum[i] + (u32)p_dm_fat_table->main_ant_sum_cck[i]; - aux_ant_sum = (u32)p_dm_fat_table->aux_ant_sum[i] + (u32)p_dm_fat_table->aux_ant_sum_cck[i]; - main_ant_cnt = (u32)p_dm_fat_table->main_ant_cnt[i] + (u32)p_dm_fat_table->main_ant_cnt_cck[i]; - aux_ant_cnt = (u32)p_dm_fat_table->aux_ant_cnt[i] + (u32)p_dm_fat_table->aux_ant_cnt_cck[i]; + #if 0 + main_ant_sum = (u32)fat_tab->main_ant_sum[i] + (u32)fat_tab->main_ant_sum_cck[i]; + aux_ant_sum = (u32)fat_tab->aux_ant_sum[i] + (u32)fat_tab->aux_ant_sum_cck[i]; + main_ant_cnt = (u32)fat_tab->main_ant_cnt[i] + (u32)fat_tab->main_ant_cnt_cck[i]; + aux_ant_cnt = (u32)fat_tab->aux_ant_cnt[i] + (u32)fat_tab->aux_ant_cnt_cck[i]; main_rssi = (main_ant_cnt != 0) ? (main_ant_sum / main_ant_cnt) : 0; aux_rssi = (aux_ant_cnt != 0) ? (aux_ant_sum / aux_ant_cnt) : 0; - if (p_dm_fat_table->main_ant_cnt[i] <= 1 && p_dm_fat_table->main_ant_cnt_cck[i] >= 1) + if (fat_tab->main_ant_cnt[i] <= 1 && fat_tab->main_ant_cnt_cck[i] >= 1) main_rssi = 0; - if (p_dm_fat_table->aux_ant_cnt[i] <= 1 && p_dm_fat_table->aux_ant_cnt_cck[i] >= 1) + if (fat_tab->aux_ant_cnt[i] <= 1 && fat_tab->aux_ant_cnt_cck[i] >= 1) aux_rssi = 0; + #endif + if ((fat_tab->main_ant_cnt[i] != 0) || (fat_tab->aux_ant_cnt[i] != 0)) { + main_ant_cnt = (u32)fat_tab->main_ant_cnt[i]; + aux_ant_cnt = (u32)fat_tab->aux_ant_cnt[i]; + main_rssi = (main_ant_cnt != 0) ? (fat_tab->main_ant_sum[i] / main_ant_cnt) : 0; + aux_rssi = (aux_ant_cnt != 0) ? (fat_tab->aux_ant_sum[i] / aux_ant_cnt) : 0; + if (dm_swat_table->pre_antenna == MAIN_ANT) { + target_ant = ((aux_ant_cnt > main_ant_cnt) && (aux_rssi >= main_rssi)) ? AUX_ANT : dm_swat_table->pre_antenna; + } else { + target_ant = ((main_ant_cnt > aux_ant_cnt) && (main_rssi >= aux_rssi)) ? MAIN_ANT : dm_swat_table->pre_antenna; + } - target_ant = (main_rssi == aux_rssi) ? p_dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); + } else { /*CCK only case*/ + main_ant_cnt = fat_tab->main_ant_cnt_cck[i]; + aux_ant_cnt = fat_tab->aux_ant_cnt_cck[i]; + main_rssi = (main_ant_cnt != 0) ? (fat_tab->main_ant_sum_cck[i] / main_ant_cnt) : 0; + aux_rssi = (aux_ant_cnt != 0) ? (fat_tab->aux_ant_sum_cck[i] / aux_ant_cnt) : 0; + target_ant = (main_rssi == aux_rssi) ? fat_tab->rx_idle_ant : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); /*Use RSSI for CCK only case*/ + } + #if 0 + target_ant = (main_rssi == aux_rssi) ? dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); + #endif local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi; local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d ))\n", p_dm_fat_table->main_ant_cnt_cck[i], p_dm_fat_table->aux_ant_cnt_cck[i])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d ))\n", p_dm_fat_table->main_ant_cnt[i], p_dm_fat_table->aux_ant_cnt[i])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", main_ant_cnt, main_rssi)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", aux_ant_cnt, aux_rssi)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i, (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d ))\n", fat_tab->main_ant_cnt_cck[i], fat_tab->aux_ant_cnt_cck[i]); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d ))\n", fat_tab->main_ant_cnt[i], fat_tab->aux_ant_cnt[i]); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", main_ant_cnt, main_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", aux_ant_cnt, aux_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i, (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); /* 2 Select RX Idle Antenna */ if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) { rx_idle_ant = target_ant; min_max_rssi = local_max_rssi; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** local_max_rssi-local_min_rssi = ((%d))\n", (local_max_rssi - local_min_rssi))); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** local_max_rssi-local_min_rssi = ((%d))\n", (local_max_rssi - local_min_rssi)); if ((local_max_rssi - local_min_rssi) > 8) { if (local_min_rssi != 0) - p_dm_swat_table->train_time_flag = 3; + dm_swat_table->train_time_flag = 3; else { if (min_max_rssi > RSSI_CHECK_THRESHOLD) - p_dm_swat_table->train_time_flag = 0; + dm_swat_table->train_time_flag = 0; else - p_dm_swat_table->train_time_flag = 3; + dm_swat_table->train_time_flag = 3; } } else if ((local_max_rssi - local_min_rssi) > 5) - p_dm_swat_table->train_time_flag = 2; + dm_swat_table->train_time_flag = 2; else if ((local_max_rssi - local_min_rssi) > 2) - p_dm_swat_table->train_time_flag = 1; + dm_swat_table->train_time_flag = 1; else - p_dm_swat_table->train_time_flag = 0; + dm_swat_table->train_time_flag = 0; } /* 2 Select TX Antenna */ if (target_ant == MAIN_ANT) - p_dm_fat_table->antsel_a[i] = ANT1_2G; + fat_tab->antsel_a[i] = ANT1_2G; else - p_dm_fat_table->antsel_a[i] = ANT2_2G; + fat_tab->antsel_a[i] = ANT2_2G; } - phydm_antdiv_reset_statistic(p_dm_odm, i); + phydm_antdiv_reset_statistic(dm, i); pkt_cnt_total += (main_ant_cnt + aux_ant_cnt); } - if (p_dm_swat_table->is_sw_ant_div_by_ctrl_frame) { - odm_s0s1_sw_ant_div_by_ctrl_frame(p_dm_odm, SWAW_STEP_DETERMINE); + if (dm_swat_table->is_sw_ant_div_by_ctrl_frame) { + odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_DETERMINE); is_by_ctrl_frame = true; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Control frame packet counter = %d, data frame packet counter = %llu\n", - p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame, pkt_cnt_total)); + PHYDM_DBG(dm, DBG_ANT_DIV, "Control frame packet counter = %d, data frame packet counter = %llu\n", + dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame, pkt_cnt_total); - if (min_max_rssi == 0xff || ((pkt_cnt_total < (p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) && p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 2)) { + if (min_max_rssi == 0xff || ((pkt_cnt_total < (dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) && dm->phy_dbg_info.num_qry_beacon_pkt < 2)) { min_max_rssi = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Check RSSI of control frame because min_max_rssi == 0xff\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_by_ctrl_frame = %d\n", is_by_ctrl_frame)); + PHYDM_DBG(dm, DBG_ANT_DIV, "Check RSSI of control frame because min_max_rssi == 0xff\n"); + PHYDM_DBG(dm, DBG_ANT_DIV, "is_by_ctrl_frame = %d\n", is_by_ctrl_frame); if (is_by_ctrl_frame) { - main_rssi = (p_dm_fat_table->main_ant_ctrl_frame_cnt != 0) ? (p_dm_fat_table->main_ant_ctrl_frame_sum / p_dm_fat_table->main_ant_ctrl_frame_cnt) : 0; - aux_rssi = (p_dm_fat_table->aux_ant_ctrl_frame_cnt != 0) ? (p_dm_fat_table->aux_ant_ctrl_frame_sum / p_dm_fat_table->aux_ant_ctrl_frame_cnt) : 0; + main_rssi = (fat_tab->main_ant_ctrl_frame_cnt != 0) ? (fat_tab->main_ant_ctrl_frame_sum / fat_tab->main_ant_ctrl_frame_cnt) : 0; + aux_rssi = (fat_tab->aux_ant_ctrl_frame_cnt != 0) ? (fat_tab->aux_ant_ctrl_frame_sum / fat_tab->aux_ant_ctrl_frame_cnt) : 0; - if (p_dm_fat_table->main_ant_ctrl_frame_cnt <= 1 && p_dm_fat_table->cck_ctrl_frame_cnt_main >= 1) + if (fat_tab->main_ant_ctrl_frame_cnt <= 1 && fat_tab->cck_ctrl_frame_cnt_main >= 1) main_rssi = 0; - if (p_dm_fat_table->aux_ant_ctrl_frame_cnt <= 1 && p_dm_fat_table->cck_ctrl_frame_cnt_aux >= 1) + if (fat_tab->aux_ant_ctrl_frame_cnt <= 1 && fat_tab->cck_ctrl_frame_cnt_aux >= 1) aux_rssi = 0; if (main_rssi != 0 || aux_rssi != 0) { - rx_idle_ant = (main_rssi == aux_rssi) ? p_dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); + rx_idle_ant = (main_rssi == aux_rssi) ? dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi; local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi; if ((local_max_rssi - local_min_rssi) > 8) - p_dm_swat_table->train_time_flag = 3; + dm_swat_table->train_time_flag = 3; else if ((local_max_rssi - local_min_rssi) > 5) - p_dm_swat_table->train_time_flag = 2; + dm_swat_table->train_time_flag = 2; else if ((local_max_rssi - local_min_rssi) > 2) - p_dm_swat_table->train_time_flag = 1; + dm_swat_table->train_time_flag = 1; else - p_dm_swat_table->train_time_flag = 0; + dm_swat_table->train_time_flag = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Control frame: main_rssi = %d, aux_rssi = %d\n", main_rssi, aux_rssi)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("rx_idle_ant decided by control frame = %s\n", (rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"))); + PHYDM_DBG(dm, DBG_ANT_DIV, "Control frame: main_rssi = %d, aux_rssi = %d\n", main_rssi, aux_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, "rx_idle_ant decided by control frame = %s\n", (rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX")); } } } - p_dm_fat_table->min_max_rssi = min_max_rssi; - p_dm_swat_table->try_flag = SWAW_STEP_PEEK; + fat_tab->min_max_rssi = min_max_rssi; + dm_swat_table->try_flag = SWAW_STEP_PEEK; - if (p_dm_swat_table->double_chk_flag == 1) { - p_dm_swat_table->double_chk_flag = 0; + if (dm_swat_table->double_chk_flag == 1) { + dm_swat_table->double_chk_flag = 0; - if (p_dm_fat_table->min_max_rssi > RSSI_CHECK_THRESHOLD) { + if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD) { + PHYDM_DBG(dm, DBG_ANT_DIV, " [Double check] min_max_rssi ((%d)) > %d again!!\n", + fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] min_max_rssi ((%d)) > %d again!!\n", - p_dm_fat_table->min_max_rssi, RSSI_CHECK_THRESHOLD)); + odm_update_rx_idle_ant(dm, rx_idle_ant); - odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[reset try_flag = 0] Training accomplished !!!]\n\n\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[reset try_flag = 0] Training accomplished !!!]\n\n\n"); return; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] min_max_rssi ((%d)) <= %d !!\n", - p_dm_fat_table->min_max_rssi, RSSI_CHECK_THRESHOLD)); + PHYDM_DBG(dm, DBG_ANT_DIV, " [Double check] min_max_rssi ((%d)) <= %d !!\n", + fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD); - next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - p_dm_swat_table->try_flag = SWAW_STEP_PEEK; - p_dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=0] Normal state: Need to tryg again!!\n\n\n")); + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + dm_swat_table->try_flag = SWAW_STEP_PEEK; + dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD; + PHYDM_DBG(dm, DBG_ANT_DIV, "[set try_flag=0] Normal state: Need to tryg again!!\n\n\n"); return; } } else { - if (p_dm_fat_table->min_max_rssi < RSSI_CHECK_THRESHOLD) - p_dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD; + if (fat_tab->min_max_rssi < RSSI_CHECK_THRESHOLD) + dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD; - p_dm_swat_table->pre_antenna = rx_idle_ant; - odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[reset try_flag = 0] Training accomplished !!!] \n\n\n")); + dm_swat_table->pre_antenna = rx_idle_ant; + odm_update_rx_idle_ant(dm, rx_idle_ant); + PHYDM_DBG(dm, DBG_ANT_DIV, "[reset try_flag = 0] Training accomplished !!!]\n\n\n"); return; } @@ -3011,102 +2894,102 @@ odm_s0s1_sw_ant_div( /* 1 4.Change TRX antenna */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("rssi_trying = (( %d )), ant: (( %s )) >>> (( %s ))\n", - p_dm_swat_table->rssi_trying, (p_dm_fat_table->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"), (next_ant == MAIN_ANT ? "MAIN" : "AUX"))); + PHYDM_DBG(dm, DBG_ANT_DIV, "rssi_trying = (( %d )), ant: (( %s )) >>> (( %s ))\n", + dm_swat_table->rssi_trying, (fat_tab->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"), (next_ant == MAIN_ANT ? "MAIN" : "AUX")); - odm_update_rx_idle_ant(p_dm_odm, next_ant); + odm_update_rx_idle_ant(dm, next_ant); /* 1 5.Reset Statistics */ - p_dm_fat_table->rx_idle_ant = next_ant; - - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - if (p_dm_odm->support_interface == ODM_ITRF_SDIO) { + fat_tab->rx_idle_ant = next_ant; + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_SDIO) { ODM_delay_us(200); - if (p_dm_fat_table->rx_idle_ant == MAIN_ANT) { - p_dm_fat_table->main_ant_sum[0] = 0; - p_dm_fat_table->main_ant_cnt[0] = 0; - p_dm_fat_table->main_ant_sum_cck[0] = 0; - p_dm_fat_table->main_ant_cnt_cck[0] = 0; + if (fat_tab->rx_idle_ant == MAIN_ANT) { + fat_tab->main_ant_sum[0] = 0; + fat_tab->main_ant_cnt[0] = 0; + fat_tab->main_ant_sum_cck[0] = 0; + fat_tab->main_ant_cnt_cck[0] = 0; } else { - p_dm_fat_table->aux_ant_sum[0] = 0; - p_dm_fat_table->aux_ant_cnt[0] = 0; - p_dm_fat_table->aux_ant_sum_cck[0] = 0; - p_dm_fat_table->aux_ant_cnt_cck[0] = 0; + fat_tab->aux_ant_sum[0] = 0; + fat_tab->aux_ant_cnt[0] = 0; + fat_tab->aux_ant_sum_cck[0] = 0; + fat_tab->aux_ant_cnt_cck[0] = 0; } } } /* 1 6.Set next timer (Trying state) */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test ((%s)) ant for (( %d )) ms\n", (next_ant == MAIN_ANT ? "MAIN" : "AUX"), p_dm_swat_table->train_time)); - odm_set_timer(p_dm_odm, &(p_dm_swat_table->phydm_sw_antenna_switch_timer), p_dm_swat_table->train_time); /*ms*/ + PHYDM_DBG(dm, DBG_ANT_DIV, " Test ((%s)) ant for (( %d )) ms\n", (next_ant == MAIN_ANT ? "MAIN" : "AUX"), dm_swat_table->train_time); + odm_set_timer(dm, &dm_swat_table->phydm_sw_antenna_switch_timer, + dm_swat_table->train_time); /*ms*/ } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void odm_sw_antdiv_callback( - struct timer_list *p_timer + struct phydm_timer_list *timer ) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct _sw_antenna_switch_ *p_dm_swat_table = &p_hal_data->DM_OutSrc.dm_swat_table; + void *adapter = (void *)timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct sw_antenna_switch *dm_swat_table = &hal_data->DM_OutSrc.dm_swat_table; #if DEV_BUS_TYPE == RT_PCI_INTERFACE #if USE_WORKITEM - odm_schedule_work_item(&p_dm_swat_table->phydm_sw_antenna_switch_workitem); + odm_schedule_work_item(&dm_swat_table->phydm_sw_antenna_switch_workitem); #else { /* dbg_print("SW_antdiv_Callback"); */ - odm_s0s1_sw_ant_div(&p_hal_data->DM_OutSrc, SWAW_STEP_DETERMINE); + odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE); } #endif #else - odm_schedule_work_item(&p_dm_swat_table->phydm_sw_antenna_switch_workitem); + odm_schedule_work_item(&dm_swat_table->phydm_sw_antenna_switch_workitem); #endif } void odm_sw_antdiv_workitem_callback( - void *p_context + void *context ) { - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); /* dbg_print("SW_antdiv_Workitem_Callback"); */ - odm_s0s1_sw_ant_div(&p_hal_data->DM_OutSrc, SWAW_STEP_DETERMINE); + odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE); } #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) void odm_sw_antdiv_workitem_callback( - void *p_context + void *context ) { - struct _ADAPTER * - p_adapter = (struct _ADAPTER *)p_context; + void * + adapter = (void *)context; HAL_DATA_TYPE - *p_hal_data = GET_HAL_DATA(p_adapter); + *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); /*dbg_print("SW_antdiv_Workitem_Callback");*/ - odm_s0s1_sw_ant_div(&p_hal_data->odmpriv, SWAW_STEP_DETERMINE); + odm_s0s1_sw_ant_div(&hal_data->odmpriv, SWAW_STEP_DETERMINE); } void odm_sw_antdiv_callback(void *function_context) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)function_context; - struct _ADAPTER *padapter = p_dm_odm->adapter; - if (padapter->net_closed == _TRUE) + struct dm_struct *dm = (struct dm_struct *)function_context; + void *padapter = dm->adapter; + if (*(dm->is_net_closed) == true) return; #if 0 /* Can't do I/O in timer callback*/ - odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_DETERMINE); + odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE); #else rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter); #endif @@ -3117,109 +3000,107 @@ odm_sw_antdiv_callback(void *function_context) void odm_s0s1_sw_ant_div_by_ctrl_frame( - void *p_dm_void, + void *dm_void, u8 step ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; switch (step) { case SWAW_STEP_PEEK: - p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame = 0; - p_dm_swat_table->is_sw_ant_div_by_ctrl_frame = true; - p_dm_fat_table->main_ant_ctrl_frame_cnt = 0; - p_dm_fat_table->aux_ant_ctrl_frame_cnt = 0; - p_dm_fat_table->main_ant_ctrl_frame_sum = 0; - p_dm_fat_table->aux_ant_ctrl_frame_sum = 0; - p_dm_fat_table->cck_ctrl_frame_cnt_main = 0; - p_dm_fat_table->cck_ctrl_frame_cnt_aux = 0; - p_dm_fat_table->ofdm_ctrl_frame_cnt_main = 0; - p_dm_fat_table->ofdm_ctrl_frame_cnt_aux = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n")); + dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame = 0; + dm_swat_table->is_sw_ant_div_by_ctrl_frame = true; + fat_tab->main_ant_ctrl_frame_cnt = 0; + fat_tab->aux_ant_ctrl_frame_cnt = 0; + fat_tab->main_ant_ctrl_frame_sum = 0; + fat_tab->aux_ant_ctrl_frame_sum = 0; + fat_tab->cck_ctrl_frame_cnt_main = 0; + fat_tab->cck_ctrl_frame_cnt_aux = 0; + fat_tab->ofdm_ctrl_frame_cnt_main = 0; + fat_tab->ofdm_ctrl_frame_cnt_aux = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n"); break; case SWAW_STEP_DETERMINE: - p_dm_swat_table->is_sw_ant_div_by_ctrl_frame = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Stop peek\n")); + dm_swat_table->is_sw_ant_div_by_ctrl_frame = false; + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_S0S1_SwAntDivForAPMode(): Stop peek\n"); break; default: - p_dm_swat_table->is_sw_ant_div_by_ctrl_frame = false; + dm_swat_table->is_sw_ant_div_by_ctrl_frame = false; break; } } void odm_antsel_statistics_of_ctrl_frame( - void *p_dm_void, + void *dm_void, u8 antsel_tr_mux, u32 rx_pwdb_all ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; if (antsel_tr_mux == ANT1_2G) { - p_dm_fat_table->main_ant_ctrl_frame_sum += rx_pwdb_all; - p_dm_fat_table->main_ant_ctrl_frame_cnt++; + fat_tab->main_ant_ctrl_frame_sum += rx_pwdb_all; + fat_tab->main_ant_ctrl_frame_cnt++; } else { - p_dm_fat_table->aux_ant_ctrl_frame_sum += rx_pwdb_all; - p_dm_fat_table->aux_ant_ctrl_frame_cnt++; + fat_tab->aux_ant_ctrl_frame_sum += rx_pwdb_all; + fat_tab->aux_ant_ctrl_frame_cnt++; } } void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void - /* struct _odm_phy_status_info_* p_phy_info, */ - /* struct _odm_per_pkt_info_* p_pktinfo */ + void *dm_void, + void *phy_info_void, + void *pkt_info_void + /* struct phydm_phyinfo_struct* phy_info, */ + /* struct phydm_perpkt_info_struct* pktinfo */ ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; - struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - boolean is_cck_rate; - - if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + if (!(dm->support_ability & ODM_BB_ANT_DIV)) return; - if (p_dm_odm->ant_div_type != S0S1_SW_ANTDIV) + if (dm->ant_div_type != S0S1_SW_ANTDIV) return; /* In try state */ - if (!p_dm_swat_table->is_sw_ant_div_by_ctrl_frame) + if (!dm_swat_table->is_sw_ant_div_by_ctrl_frame) return; /* No HW error and match receiver address */ - if (!p_pktinfo->is_to_self) + if (!pktinfo->is_to_self) return; - p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame++; - is_cck_rate = ((p_pktinfo->data_rate >= DESC_RATE1M) && (p_pktinfo->data_rate <= DESC_RATE11M)) ? true : false; + dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame++; - if (is_cck_rate) { - p_dm_fat_table->antsel_rx_keep_0 = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; + if (pktinfo->is_cck_rate) { + fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; - if (p_dm_fat_table->antsel_rx_keep_0 == ANT1_2G) - p_dm_fat_table->cck_ctrl_frame_cnt_main++; + if (fat_tab->antsel_rx_keep_0 == ANT1_2G) + fat_tab->cck_ctrl_frame_cnt_main++; else - p_dm_fat_table->cck_ctrl_frame_cnt_aux++; + fat_tab->cck_ctrl_frame_cnt_aux++; - odm_antsel_statistics_of_ctrl_frame(p_dm_odm, p_dm_fat_table->antsel_rx_keep_0, p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]); + odm_antsel_statistics_of_ctrl_frame(dm, fat_tab->antsel_rx_keep_0, phy_info->rx_mimo_signal_strength[RF_PATH_A]); } else { - p_dm_fat_table->antsel_rx_keep_0 = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; + fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; - if (p_dm_fat_table->antsel_rx_keep_0 == ANT1_2G) - p_dm_fat_table->ofdm_ctrl_frame_cnt_main++; + if (fat_tab->antsel_rx_keep_0 == ANT1_2G) + fat_tab->ofdm_ctrl_frame_cnt_main++; else - p_dm_fat_table->ofdm_ctrl_frame_cnt_aux++; + fat_tab->ofdm_ctrl_frame_cnt_aux++; - odm_antsel_statistics_of_ctrl_frame(p_dm_odm, p_dm_fat_table->antsel_rx_keep_0, p_phy_info->rx_pwdb_all); + odm_antsel_statistics_of_ctrl_frame(dm, fat_tab->antsel_rx_keep_0, phy_info->rx_pwdb_all); } } @@ -3230,106 +3111,56 @@ odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi( void odm_set_next_mac_addr_target( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct sta_info *p_entry; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct cmn_sta_info *entry; u32 value32, i; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_set_next_mac_addr_target() ==>\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "odm_set_next_mac_addr_target() ==>\n"); - if (p_dm_odm->is_linked) { + if (dm->is_linked) { for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - - if ((p_dm_fat_table->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM) - p_dm_fat_table->train_idx = 0; + if ((fat_tab->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM) + fat_tab->train_idx = 0; else - p_dm_fat_table->train_idx++; + fat_tab->train_idx++; - p_entry = p_dm_odm->p_odm_sta_info[p_dm_fat_table->train_idx]; - - if (IS_STA_VALID(p_entry)) { + entry = dm->phydm_sta_info[fat_tab->train_idx]; + if (is_sta_active(entry)) { /*Match MAC ADDR*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - value32 = (p_entry->hwaddr[5] << 8) | p_entry->hwaddr[4]; -#else - value32 = (p_entry->MacAddr[5] << 8) | p_entry->MacAddr[4]; -#endif + value32 = (entry->mac_addr[5] << 8) | entry->mac_addr[4]; - odm_set_mac_reg(p_dm_odm, 0x7b4, 0xFFFF, value32);/*0x7b4~0x7b5*/ + odm_set_mac_reg(dm, 0x7b4, 0xFFFF, value32);/*0x7b4~0x7b5*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - value32 = (p_entry->hwaddr[3] << 24) | (p_entry->hwaddr[2] << 16) | (p_entry->hwaddr[1] << 8) | p_entry->hwaddr[0]; -#else - value32 = (p_entry->MacAddr[3] << 24) | (p_entry->MacAddr[2] << 16) | (p_entry->MacAddr[1] << 8) | p_entry->MacAddr[0]; -#endif - odm_set_mac_reg(p_dm_odm, 0x7b0, MASKDWORD, value32);/*0x7b0~0x7b3*/ + value32 = (entry->mac_addr[3] << 24) | (entry->mac_addr[2] << 16) | (entry->mac_addr[1] << 8) | entry->mac_addr[0]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_fat_table->train_idx=%d\n", p_dm_fat_table->train_idx)); + odm_set_mac_reg(dm, 0x7b0, MASKDWORD, value32);/*0x7b0~0x7b3*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC addr = %x:%x:%x:%x:%x:%x\n", - p_entry->hwaddr[5], p_entry->hwaddr[4], p_entry->hwaddr[3], p_entry->hwaddr[2], p_entry->hwaddr[1], p_entry->hwaddr[0])); -#else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC addr = %x:%x:%x:%x:%x:%x\n", - p_entry->MacAddr[5], p_entry->MacAddr[4], p_entry->MacAddr[3], p_entry->MacAddr[2], p_entry->MacAddr[1], p_entry->MacAddr[0])); -#endif + PHYDM_DBG(dm, DBG_ANT_DIV, "fat_tab->train_idx=%d\n", fat_tab->train_idx); + + PHYDM_DBG(dm, DBG_ANT_DIV, "Training MAC addr = %x:%x:%x:%x:%x:%x\n", + entry->mac_addr[5], entry->mac_addr[4], entry->mac_addr[3], entry->mac_addr[2], entry->mac_addr[1], entry->mac_addr[0]); break; } } } -#if 0 - /* */ - /* 2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn */ - /* */ -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - { - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; - - for (i = 0; i < 6; i++) { - bssid[i] = p_mgnt_info->bssid[i]; - /* dbg_print("bssid[%d]=%x\n", i, bssid[i]); */ - } - } -#endif - - /* odm_set_next_mac_addr_target(p_dm_odm); */ - - /* 1 Select MAC Address Filter */ - for (i = 0; i < 6; i++) { - if (bssid[i] != p_dm_fat_table->bssid[i]) { - is_match_bssid = false; - break; - } - } - if (is_match_bssid == false) { - /* Match MAC ADDR */ - value32 = (bssid[5] << 8) | bssid[4]; - odm_set_mac_reg(p_dm_odm, 0x7b4, 0xFFFF, value32); - value32 = (bssid[3] << 24) | (bssid[2] << 16) | (bssid[1] << 8) | bssid[0]; - odm_set_mac_reg(p_dm_odm, 0x7b0, MASKDWORD, value32); - } - - return is_match_bssid; -#endif - } #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) void odm_fast_ant_training( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; u32 max_rssi_path_a = 0, pckcnt_path_a = 0; u8 i, target_ant_path_a = 0; @@ -3341,95 +3172,95 @@ odm_fast_ant_training( #endif - if (!p_dm_odm->is_linked) { /* is_linked==False */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + if (!dm->is_linked) { /* is_linked==False */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); - if (p_dm_fat_table->is_become_linked == true) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - phydm_fast_training_enable(p_dm_odm, FAT_OFF); - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + if (fat_tab->is_become_linked == true) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + phydm_fast_training_enable(dm, FAT_OFF); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + fat_tab->is_become_linked = dm->is_linked; } return; } else { - if (p_dm_fat_table->is_become_linked == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked!!!]\n")); - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked!!!]\n"); + fat_tab->is_become_linked = dm->is_linked; } } - if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) { - if (p_dm_odm->is_one_entry_only == true) - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + if (*fat_tab->p_force_tx_ant_by_desc == false) { + if (dm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); else - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); } - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - odm_set_bb_reg(p_dm_odm, 0x864, BIT(2) | BIT(1) | BIT(0), ((p_dm_odm->fat_comb_a) - 1)); + if (dm->support_ic_type == ODM_RTL8188E) + odm_set_bb_reg(dm, 0x864, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); #if (RTL8192E_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(2) | BIT1 | BIT0, ((p_dm_odm->fat_comb_a) - 1)); /* path-A */ /* ant combination=regB38[2:0]+1 */ - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(18) | BIT17 | BIT16, ((p_dm_odm->fat_comb_b) - 1)); /* path-B */ /* ant combination=regB38[18:16]+1 */ + else if (dm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(dm, 0xB38, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); /* path-A */ /* ant combination=regB38[2:0]+1 */ + odm_set_bb_reg(dm, 0xB38, BIT(18) | BIT(17) | BIT(16), ((dm->fat_comb_b) - 1)); /* path-B */ /* ant combination=regB38[18:16]+1 */ } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_fast_ant_training()\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "==>odm_fast_ant_training()\n"); /* 1 TRAINING STATE */ - if (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) { + if (fat_tab->fat_state == FAT_TRAINING_STATE) { /* 2 Caculate RSSI per Antenna */ /* 3 [path-A]--------------------------- */ - for (i = 0; i < (p_dm_odm->fat_comb_a); i++) { /* i : antenna index */ - if (p_dm_fat_table->ant_rssi_cnt[i] == 0) - p_dm_fat_table->ant_ave_rssi[i] = 0; + for (i = 0; i < (dm->fat_comb_a); i++) { /* i : antenna index */ + if (fat_tab->ant_rssi_cnt[i] == 0) + fat_tab->ant_ave_rssi[i] = 0; else { - p_dm_fat_table->ant_ave_rssi[i] = p_dm_fat_table->ant_sum_rssi[i] / p_dm_fat_table->ant_rssi_cnt[i]; + fat_tab->ant_ave_rssi[i] = fat_tab->ant_sum_rssi[i] / fat_tab->ant_rssi_cnt[i]; is_pkt_filter_macth_path_a = true; } - if (p_dm_fat_table->ant_ave_rssi[i] > max_rssi_path_a) { - max_rssi_path_a = p_dm_fat_table->ant_ave_rssi[i]; - pckcnt_path_a = p_dm_fat_table->ant_rssi_cnt[i]; + if (fat_tab->ant_ave_rssi[i] > max_rssi_path_a) { + max_rssi_path_a = fat_tab->ant_ave_rssi[i]; + pckcnt_path_a = fat_tab->ant_rssi_cnt[i]; target_ant_path_a = i ; - } else if (p_dm_fat_table->ant_ave_rssi[i] == max_rssi_path_a) { - if ((p_dm_fat_table->ant_rssi_cnt[i]) > pckcnt_path_a) { - max_rssi_path_a = p_dm_fat_table->ant_ave_rssi[i]; - pckcnt_path_a = p_dm_fat_table->ant_rssi_cnt[i]; + } else if (fat_tab->ant_ave_rssi[i] == max_rssi_path_a) { + if ((fat_tab->ant_rssi_cnt[i]) > pckcnt_path_a) { + max_rssi_path_a = fat_tab->ant_ave_rssi[i]; + pckcnt_path_a = fat_tab->ant_rssi_cnt[i]; target_ant_path_a = i ; } } - ODM_RT_TRACE("*** ant-index : [ %d ], counter = (( %d )), Avg RSSI = (( %d ))\n", i, p_dm_fat_table->ant_rssi_cnt[i], p_dm_fat_table->ant_ave_rssi[i]); + PHYDM_DBG("*** ant-index : [ %d ], counter = (( %d )), Avg RSSI = (( %d ))\n", i, fat_tab->ant_rssi_cnt[i], fat_tab->ant_ave_rssi[i]); } #if 0 #if (RTL8192E_SUPPORT == 1) /* 3 [path-B]--------------------------- */ - for (i = 0; i < (p_dm_odm->fat_comb_b); i++) { - if (p_dm_fat_table->antRSSIcnt_pathB[i] == 0) - p_dm_fat_table->antAveRSSI_pathB[i] = 0; + for (i = 0; i < (dm->fat_comb_b); i++) { + if (fat_tab->antRSSIcnt_pathB[i] == 0) + fat_tab->antAveRSSI_pathB[i] = 0; else { /* (ant_rssi_cnt[i] != 0) */ - p_dm_fat_table->antAveRSSI_pathB[i] = p_dm_fat_table->antSumRSSI_pathB[i] / p_dm_fat_table->antRSSIcnt_pathB[i]; + fat_tab->antAveRSSI_pathB[i] = fat_tab->antSumRSSI_pathB[i] / fat_tab->antRSSIcnt_pathB[i]; is_pkt_filter_macth_path_b = true; } - if (p_dm_fat_table->antAveRSSI_pathB[i] > max_rssi_path_b) { - max_rssi_path_b = p_dm_fat_table->antAveRSSI_pathB[i]; - pckcnt_path_b = p_dm_fat_table->antRSSIcnt_pathB[i]; + if (fat_tab->antAveRSSI_pathB[i] > max_rssi_path_b) { + max_rssi_path_b = fat_tab->antAveRSSI_pathB[i]; + pckcnt_path_b = fat_tab->antRSSIcnt_pathB[i]; target_ant_path_b = (u8) i; } - if (p_dm_fat_table->antAveRSSI_pathB[i] == max_rssi_path_b) { - if (p_dm_fat_table->antRSSIcnt_pathB > pckcnt_path_b) { - max_rssi_path_b = p_dm_fat_table->antAveRSSI_pathB[i]; + if (fat_tab->antAveRSSI_pathB[i] == max_rssi_path_b) { + if (fat_tab->antRSSIcnt_pathB > pckcnt_path_b) { + max_rssi_path_b = fat_tab->antAveRSSI_pathB[i]; target_ant_path_b = (u8) i; } } - if (p_dm_odm->fat_print_rssi == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d ))\n", - i, p_dm_fat_table->antSumRSSI_pathB[i], i, p_dm_fat_table->antRSSIcnt_pathB[i], i, p_dm_fat_table->antAveRSSI_pathB[i])); + if (dm->fat_print_rssi == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, "***{path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d ))\n", + i, fat_tab->antSumRSSI_pathB[i], i, fat_tab->antRSSIcnt_pathB[i], i, fat_tab->antAveRSSI_pathB[i]); } } #endif @@ -3439,1619 +3270,233 @@ odm_fast_ant_training( /* 2 Select TRX Antenna */ - phydm_fast_training_enable(p_dm_odm, FAT_OFF); + phydm_fast_training_enable(dm, FAT_OFF); /* 3 [path-A]--------------------------- */ if (is_pkt_filter_macth_path_a == false) { - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{path-A}: None Packet is matched\n")); */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{path-A}: None Packet is matched\n")); - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + /* PHYDM_DBG(dm,DBG_ANT_DIV, "{path-A}: None Packet is matched\n"); */ + PHYDM_DBG(dm, DBG_ANT_DIV, "{path-A}: None Packet is matched\n"); + odm_ant_div_on_off(dm, ANTDIV_OFF); } else { - ODM_RT_TRACE("target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n", target_ant_path_a, max_rssi_path_a); + PHYDM_DBG("target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n", target_ant_path_a, max_rssi_path_a); /* 3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT */ - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); - else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(8) | BIT7 | BIT6, target_ant_path_a); /* Optional RX [pth-A] */ - } + if (dm->support_ic_type == ODM_RTL8188E) + odm_set_bb_reg(dm, 0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); + else if (dm->support_ic_type == ODM_RTL8192E) + odm_set_bb_reg(dm, 0xB38, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); /* Optional RX [pth-A] */ + /* 3 [ update TX ant ] */ - odm_update_tx_ant(p_dm_odm, target_ant_path_a, (p_dm_fat_table->train_idx)); + odm_update_tx_ant(dm, target_ant_path_a, (fat_tab->train_idx)); if (target_ant_path_a == 0) - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + odm_ant_div_on_off(dm, ANTDIV_OFF); } #if 0 #if (RTL8192E_SUPPORT == 1) /* 3 [path-B]--------------------------- */ if (is_pkt_filter_macth_path_b == false) { - if (p_dm_odm->fat_print_rssi == 1) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***[%d]{path-B}: None Packet is matched\n\n\n", __LINE__)); + if (dm->fat_print_rssi == 1) + PHYDM_DBG(dm, DBG_ANT_DIV, "***[%d]{path-B}: None Packet is matched\n\n\n", __LINE__); } else { - if (p_dm_odm->fat_print_rssi == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - (" ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n", target_ant_path_b, max_rssi_path_b)); + if (dm->fat_print_rssi == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, + " ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n", target_ant_path_b, max_rssi_path_b); } - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(21) | BIT20 | BIT19, target_ant_path_b); /* Default RX is Omni, Optional RX is the best decision by FAT */ - odm_set_bb_reg(p_dm_odm, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 //from TX Info */ + odm_set_bb_reg(dm, 0xB38, BIT(21) | BIT20 | BIT19, target_ant_path_b); /* Default RX is Omni, Optional RX is the best decision by FAT */ + odm_set_bb_reg(dm, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 //from TX Info */ - p_dm_fat_table->antsel_pathB[p_dm_fat_table->train_idx] = target_ant_path_b; + fat_tab->antsel_pathB[fat_tab->train_idx] = target_ant_path_b; } #endif #endif /* 2 Reset counter */ - for (i = 0; i < (p_dm_odm->fat_comb_a); i++) { - p_dm_fat_table->ant_sum_rssi[i] = 0; - p_dm_fat_table->ant_rssi_cnt[i] = 0; + for (i = 0; i < (dm->fat_comb_a); i++) { + fat_tab->ant_sum_rssi[i] = 0; + fat_tab->ant_rssi_cnt[i] = 0; } /* #if (RTL8192E_SUPPORT == 1) - for(i=0; i<=(p_dm_odm->fat_comb_b); i++) + for(i=0; i<=(dm->fat_comb_b); i++) { - p_dm_fat_table->antSumRSSI_pathB[i] = 0; - p_dm_fat_table->antRSSIcnt_pathB[i] = 0; + fat_tab->antSumRSSI_pathB[i] = 0; + fat_tab->antRSSIcnt_pathB[i] = 0; } #endif */ - p_dm_fat_table->fat_state = FAT_PREPARE_STATE; + fat_tab->fat_state = FAT_PREPARE_STATE; return; } /* 1 NORMAL STATE */ - if (p_dm_fat_table->fat_state == FAT_PREPARE_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Start Prepare state ]\n")); + if (fat_tab->fat_state == FAT_PREPARE_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Start Prepare state ]\n"); - odm_set_next_mac_addr_target(p_dm_odm); + odm_set_next_mac_addr_target(dm); /* 2 Prepare Training */ - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - phydm_fast_training_enable(p_dm_odm, FAT_ON); - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); /* enable HW AntDiv */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Start Training state]\n")); + fat_tab->fat_state = FAT_TRAINING_STATE; + phydm_fast_training_enable(dm, FAT_ON); + odm_ant_div_on_off(dm, ANTDIV_ON); /* enable HW AntDiv */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[Start Training state]\n"); - odm_set_timer(p_dm_odm, &p_dm_odm->fast_ant_training_timer, p_dm_odm->antdiv_intvl); /* ms */ + odm_set_timer(dm, &dm->fast_ant_training_timer, dm->antdiv_intvl); /* ms */ } } void odm_fast_ant_training_callback( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct _ADAPTER *padapter = p_dm_odm->adapter; - if (padapter->net_closed == _TRUE) + if (*(dm->is_net_closed) == true) return; - /* if(*p_dm_odm->p_is_net_closed == true) */ - /* return; */ #endif #if USE_WORKITEM - odm_schedule_work_item(&p_dm_odm->fast_ant_training_workitem); + odm_schedule_work_item(&dm->fast_ant_training_workitem); #else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_fast_ant_training_callback******\n")); - odm_fast_ant_training(p_dm_odm); + PHYDM_DBG(dm, DBG_ANT_DIV, "******odm_fast_ant_training_callback******\n"); + odm_fast_ant_training(dm); #endif } void odm_fast_ant_training_work_item_callback( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_fast_ant_training_work_item_callback******\n")); - odm_fast_ant_training(p_dm_odm); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "******odm_fast_ant_training_work_item_callback******\n"); + odm_fast_ant_training(dm); } #endif -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - -u32 -phydm_construct_hb_rfu_codeword_type2( - void *p_dm_void, - u32 beam_set_idx +void +odm_ant_div_init( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 sync_codeword = 0x7f; - u32 codeword = 0; - u32 data_tmp = 0; - u32 i; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; - for (i = 0; i < pdm_sat_table->ant_num_total; i++) { - if (*p_dm_odm->p_band_type == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[beam_set_idx][i]; - else - data_tmp = pdm_sat_table->rfu_codeword_table_2g[beam_set_idx][i]; - - codeword |= (data_tmp << (i * pdm_sat_table->rfu_each_ant_bit_num)); + if (!(dm->support_ability & ODM_BB_ANT_DIV)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Return!!!] Not Support Antenna Diversity Function\n"); + return; } + /* --- */ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n"); + if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)) + return; + } else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n"); + if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)) + return; + } else if (fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G)) + PHYDM_DBG(dm, DBG_ANT_DIV, "[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n"); - codeword = (codeword<<8) | sync_codeword; - - return codeword; -} +#endif + /* --- */ -void -phydm_update_beam_pattern_type2( - void *p_dm_void, - u32 codeword, - u32 codeword_length -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u8 i; - boolean beam_ctrl_signal; - u32 one = 0x1; - u32 reg44_tmp_p, reg44_tmp_n, reg44_ori; - u8 devide_num = 4; + /* 2 [--General---] */ + dm->antdiv_period = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set codeword = ((0x%x))\n", codeword)); + fat_tab->is_become_linked = false; + fat_tab->ant_div_on_off = 0xff; - reg44_ori = odm_get_mac_reg(p_dm_odm, 0x44, MASKDWORD); - reg44_tmp_p = reg44_ori; - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_ori =0x%x\n", reg44_ori));*/ + /* 3 - AP - */ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - /*devide_num = (pdm_sat_table->rfu_protocol_type == 2) ? 8 : 4;*/ +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + odm_bdc_init(dm); +#endif +#endif - for (i = 0; i <= (codeword_length - 1); i++) { - beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i); - - #if 1 - if (p_dm_odm->debug_components & ODM_COMP_ANT_DIV) { - - if (i == (codeword_length - 1)) { - dbg_print("%d ]\n", beam_ctrl_signal); - /**/ - } else if (i == 0) { - dbg_print("Start sending codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal); - /**/ - } else if ((i % devide_num) == (devide_num-1)) { - dbg_print("%d | ", beam_ctrl_signal); - /**/ - } else { - dbg_print("%d ", beam_ctrl_signal); - /**/ - } - } - #endif - - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - #if (RTL8821A_SUPPORT == 1) - reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT10)); /*clean bit 10 & 11*/ - reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10)); - reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10))); - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n));*/ - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_n); - #endif - } - #if (RTL8822B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + /* 3 - WIN - */ +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + dm_swat_table->ant_5g = MAIN_ANT; + dm_swat_table->ant_2g = MAIN_ANT; +#endif - if (pdm_sat_table->rfu_protocol_type == 2) { + /* 2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */ + odm_ant_div_on_off(dm, ANTDIV_OFF); - reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*clean bit 8*/ - reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*get new clk high/low, exclusive-or*/ + dm->ant_type = ODM_AUTO_ANT; - - reg44_tmp_p |= (beam_ctrl_signal << 8); - - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); - ODM_delay_us(pdm_sat_table->rfu_protocol_delay_time); - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal));*/ - - } else { - reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT8)); /*clean bit 9 & 8*/ - reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8)); - reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8))); - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n)); */ - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); - ODM_delay_us(10); - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_n); - ODM_delay_us(10); - } - } - #endif + fat_tab->rx_idle_ant = 0xff; /*to make RX-idle-antenna will be updated absolutly*/ + odm_update_rx_idle_ant(dm, MAIN_ANT); + phydm_keep_rx_ack_ant_by_tx_ant_time(dm, 0); /* Timming issue: keep Rx ant after tx for ACK ( 5 x 3.2 mu = 16mu sec)*/ + + /* 2 [---Set TX Antenna---] */ + if (fat_tab->p_force_tx_ant_by_desc == NULL) { + fat_tab->force_tx_ant_by_desc = 0; + fat_tab->p_force_tx_ant_by_desc = &fat_tab->force_tx_ant_by_desc; } -} + PHYDM_DBG(dm, DBG_ANT_DIV, "p_force_tx_ant_by_desc = %d\n", *fat_tab->p_force_tx_ant_by_desc); -void -phydm_update_rx_idle_beam_type2( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 i; + if (*fat_tab->p_force_tx_ant_by_desc == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + else + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); - pdm_sat_table->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(p_dm_odm, pdm_sat_table->rx_idle_beam_set_idx); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Beam ] BeamSet idx = ((%d))\n", pdm_sat_table->rx_idle_beam_set_idx)); -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern_type2(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); -#else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); - /*odm_stall_execution(1);*/ -#endif + /* 2 [--88E---] */ + if (dm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + /* dm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + /* dm->ant_div_type = CG_TRX_SMART_ANTDIV; */ - pdm_sat_table->pre_codeword = pdm_sat_table->update_beam_codeword; -} + if ((dm->ant_div_type != CGCS_RX_HW_ANTDIV) && (dm->ant_div_type != CG_TRX_HW_ANTDIV) && (dm->ant_div_type != CG_TRX_SMART_ANTDIV)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Return!!!] 88E Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } - -void -phydm_hl_smart_ant_debug_type2( - void *p_dm_void, - char input[][16], - u32 *_used, - char *output, - u32 *_out_len, - u32 input_num -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 used = *_used; - u32 out_len = *_out_len; - u32 one = 0x1; - u32 codeword_length = pdm_sat_table->rfu_codeword_total_bit_num; - u32 beam_ctrl_signal, i; - u8 devide_num = 4; - char help[] = "-h"; - u32 dm_value[10] = {0}; - - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]); - PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]); - PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]); - PHYDM_SSCANF(input[4], DCMD_DECIMAL, &dm_value[3]); - PHYDM_SSCANF(input[5], DCMD_DECIMAL, &dm_value[4]); - - - if (strcmp(input[1], help) == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, " 1 {fix_en} {codeword(Hex)}\n")); - PHYDM_SNPRINTF((output + used, out_len - used, " 3 {Fix_training_num_en} {Per_beam_training_pkt_num} {Decision_holding_period}\n")); - PHYDM_SNPRINTF((output + used, out_len - used, " 5 {0:show, 1:2G, 2:5G} {beam_num} {idxA(Hex)} {idxB(Hex)}\n")); - PHYDM_SNPRINTF((output + used, out_len - used, " 7 {0:show, 1:2G, 2:5G} {total_beam_set_num}\n")); - PHYDM_SNPRINTF((output + used, out_len - used, " 8 {0:show, 1:set} {RFU delay time(us)}\n")); - - } else if (dm_value[0] == 1) { /*fix beam pattern*/ - - pdm_sat_table->fix_beam_pattern_en = dm_value[1]; - - if (pdm_sat_table->fix_beam_pattern_en == 1) { - - PHYDM_SSCANF(input[3], DCMD_HEX, &dm_value[2]); - pdm_sat_table->fix_beam_pattern_codeword = dm_value[2]; - - if (pdm_sat_table->fix_beam_pattern_codeword > (one << codeword_length)) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n", - pdm_sat_table->fix_beam_pattern_codeword, codeword_length)); - - (pdm_sat_table->fix_beam_pattern_codeword) &= 0xffffff; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Auto modify to (0x%x)\n", pdm_sat_table->fix_beam_pattern_codeword)); - } - - pdm_sat_table->update_beam_codeword = pdm_sat_table->fix_beam_pattern_codeword; - - /*---------------------------------------------------------*/ - PHYDM_SNPRINTF((output + used, out_len - used, "Fix Beam Pattern\n")); - - /*devide_num = (pdm_sat_table->rfu_protocol_type == 2) ? 8 : 4;*/ - - for (i = 0; i <= (codeword_length - 1); i++) { - beam_ctrl_signal = (boolean)((pdm_sat_table->update_beam_codeword & BIT(i)) >> i); - - if (i == (codeword_length - 1)) { - PHYDM_SNPRINTF((output + used, out_len - used, "%d]\n", beam_ctrl_signal)); - /**/ - } else if (i == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "Send Codeword[1:%d] to RFU -> [%d", pdm_sat_table->rfu_codeword_total_bit_num, beam_ctrl_signal)); - /**/ - } else if ((i % devide_num) == (devide_num-1)) { - PHYDM_SNPRINTF((output + used, out_len - used, "%d|", beam_ctrl_signal)); - /**/ - } else { - PHYDM_SNPRINTF((output + used, out_len - used, "%d", beam_ctrl_signal)); - /**/ - } - } - /*---------------------------------------------------------*/ - - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern_type2(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); - #else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); - /*odm_stall_execution(1);*/ - #endif - } else if (pdm_sat_table->fix_beam_pattern_en == 0) - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Smart Antenna: Enable\n")); - - } else if (dm_value[0] == 2) { /*set latch time*/ - - pdm_sat_table->latch_time = dm_value[1]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] latch_time =0x%x\n", pdm_sat_table->latch_time)); - } else if (dm_value[0] == 3) { - - pdm_sat_table->fix_training_num_en = dm_value[1]; - - if (pdm_sat_table->fix_training_num_en == 1) { - pdm_sat_table->per_beam_training_pkt_num = (u8)dm_value[2]; - pdm_sat_table->decision_holding_period = (u8)dm_value[3]; - - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", - pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); - - } else if (pdm_sat_table->fix_training_num_en == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] AUTO per_beam_training_pkt_num\n")); - /**/ - } - } else if (dm_value[0] == 4) { - #if 0 - if (dm_value[1] == 1) { - pdm_sat_table->ant_num = 1; - pdm_sat_table->first_train_ant = MAIN_ANT; - - } else if (dm_value[1] == 2) { - pdm_sat_table->ant_num = 1; - pdm_sat_table->first_train_ant = AUX_ANT; - - } else if (dm_value[1] == 3) { - pdm_sat_table->ant_num = 2; - pdm_sat_table->first_train_ant = MAIN_ANT; - } - - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set ant Num = (( %d )), first_train_ant = (( %d ))\n", - pdm_sat_table->ant_num, (pdm_sat_table->first_train_ant - 1))); - #endif - } else if (dm_value[0] == 5) { /*set beam set table*/ - - PHYDM_SSCANF(input[4], DCMD_HEX, &dm_value[3]); - PHYDM_SSCANF(input[5], DCMD_HEX, &dm_value[4]); - - if (dm_value[1] == 1) { /*2G*/ - if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { - pdm_sat_table->rfu_codeword_table_2g[dm_value[2] ][0] = (u8)dm_value[3]; - pdm_sat_table->rfu_codeword_table_2g[dm_value[2] ][1] = (u8)dm_value[4]; - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Set 2G Table[%d] = [A:0x%x, B:0x%x]\n",dm_value[2], dm_value[3], dm_value[4])); - } - - } else if (dm_value[1] == 2) { /*5G*/ - if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { - pdm_sat_table->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3]; - pdm_sat_table->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4]; - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",dm_value[2], dm_value[3], dm_value[4])); - } - } else if (dm_value[1] == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] 2G Beam Table==============>\n")); - for (i = 0; i < pdm_sat_table->total_beam_set_num_2g; i++) { - PHYDM_SNPRINTF((output + used, out_len - used, "2G Table[%d] = [A:0x%x, B:0x%x]\n", - i, pdm_sat_table->rfu_codeword_table_2g[i][0], pdm_sat_table->rfu_codeword_table_2g[i][1])); - } - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] 5G Beam Table==============>\n")); - for (i = 0; i < pdm_sat_table->total_beam_set_num_5g; i++) { - PHYDM_SNPRINTF((output + used, out_len - used, "5G Table[%d] = [A:0x%x, B:0x%x]\n", - i, pdm_sat_table->rfu_codeword_table_5g[i][0], pdm_sat_table->rfu_codeword_table_5g[i][1])); - } - } - - } else if (dm_value[0] == 6) { - #if 0 - if (dm_value[1] == 0) { - if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { - pdm_sat_table->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3]; - pdm_sat_table->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4]; - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",dm_value[2], dm_value[3], dm_value[4])); - } - } else { - for (i = 0; i < pdm_sat_table->total_beam_set_num_5g; i++) { - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Read 5G Table[%d] = [A:0x%x, B:0x%x]\n", - i, pdm_sat_table->rfu_codeword_table_5g[i][0], pdm_sat_table->rfu_codeword_table_5g[i][1])); - } - } - #endif - } else if (dm_value[0] == 7) { - - if (dm_value[1] == 1) { - - pdm_sat_table->total_beam_set_num_2g = (u8)(dm_value[2]); - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] total_beam_set_num_2g = ((%d))\n", pdm_sat_table->total_beam_set_num_2g)); - - } else if (dm_value[1] == 2) { - - pdm_sat_table->total_beam_set_num_5g = (u8)(dm_value[2]); - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] total_beam_set_num_5g = ((%d))\n", pdm_sat_table->total_beam_set_num_5g)); - } else if (dm_value[1] == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Show total_beam_set_num{2g,5g} = {%d,%d}\n", - pdm_sat_table->total_beam_set_num_2g, pdm_sat_table->total_beam_set_num_5g)); - } - - } else if (dm_value[0] == 8) { - - if (dm_value[1] == 1) { - pdm_sat_table->rfu_protocol_delay_time = (u16)(dm_value[2]); - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Set rfu_protocol_delay_time = ((%d))\n", pdm_sat_table->rfu_protocol_delay_time)); - } else if (dm_value[1] == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Read rfu_protocol_delay_time = ((%d))\n", pdm_sat_table->rfu_protocol_delay_time)); - } - } - -} - -void -phydm_set_rfu_beam_pattern_type2( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - - if (p_dm_odm->ant_div_type != HL_SW_SMART_ANT_TYPE2) - return; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training beam_set index = (( 0x%x ))\n", pdm_sat_table->fast_training_beam_num)); - pdm_sat_table->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(p_dm_odm, pdm_sat_table->fast_training_beam_num); - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern_type2(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); - #else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); - /*odm_stall_execution(1);*/ - #endif -} - -void -phydm_fast_ant_training_hl_smart_antenna_type2( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &(p_dm_odm->dm_fat_table); - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - u32 codeword = 0; - u8 i = 0, j=0; - u8 avg_rssi_tmp; - u8 avg_rssi_tmp_ma; - u8 max_beam_ant_rssi = 0; - u8 rssi_target_beam = 0, target_beam_max_rssi = 0; - u8 evm1ss_target_beam = 0, evm2ss_target_beam = 0; - u32 target_beam_max_evm1ss = 0, target_beam_max_evm2ss = 0; - u32 beam_tmp; - u8 per_beam_val_diff_tmp = 0, training_pkt_num_offset; - u32 avg_evm2ss[2] = {0}, avg_evm2ss_sum = 0; - u32 avg_evm1ss = 0; - u32 beam_path_evm_2ss_cnt_all = 0; /*sum of all 2SS-pattern cnt*/ - u32 beam_path_evm_1ss_cnt_all = 0; /*sum of all 1SS-pattern cnt*/ - u8 decision_type; - - if (!p_dm_odm->is_linked) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - - if (p_dm_fat_table->is_become_linked == true) { - - pdm_sat_table->decision_holding_period = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Link->no Link\n")); - p_dm_fat_table->fat_state = FAT_BEFORE_LINK_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", p_dm_fat_table->fat_state)); - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; - } - return; - - } else { - if (p_dm_fat_table->is_become_linked == false) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); - - p_dm_fat_table->fat_state = FAT_PREPARE_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", p_dm_fat_table->fat_state)); - - /*pdm_sat_table->fast_training_beam_num = 0;*/ - /*phydm_set_rfu_beam_pattern_type2(p_dm_odm);*/ - - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; - } - } - - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("HL Smart ant Training: state (( %d ))\n", p_dm_fat_table->fat_state));*/ - - /* [DECISION STATE] */ - /*=======================================================================================*/ - if (p_dm_fat_table->fat_state == FAT_DECISION_STATE) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 3. In Decision state]\n")); - - /*compute target beam in each antenna*/ - - for (j = 0; j < (pdm_sat_table->total_beam_set_num); j++) { - - /*[Decision1: RSSI]-------------------------------------------------------------------*/ - if (pdm_sat_table->statistic_pkt_cnt[j] == 0) { /*if new RSSI = 0 -> MA_RSSI-=2*/ - avg_rssi_tmp = pdm_sat_table->beam_set_avg_rssi_pre[j]; - avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; - avg_rssi_tmp_ma = avg_rssi_tmp; - } else { - avg_rssi_tmp = (u8)((pdm_sat_table->beam_set_rssi_avg_sum[j]) / (pdm_sat_table->statistic_pkt_cnt[j])); - avg_rssi_tmp_ma = (avg_rssi_tmp + pdm_sat_table->beam_set_avg_rssi_pre[j]) >> 1; - } - - pdm_sat_table->beam_set_avg_rssi_pre[j] = avg_rssi_tmp; - - if (avg_rssi_tmp > target_beam_max_rssi) { - rssi_target_beam = j; - target_beam_max_rssi = avg_rssi_tmp; - } - - /*[Decision2: EVM 2ss]-------------------------------------------------------------------*/ - if (pdm_sat_table->beam_path_evm_2ss_cnt[j] != 0) { - avg_evm2ss[0] = pdm_sat_table->beam_path_evm_2ss_sum[j][0] / pdm_sat_table->beam_path_evm_2ss_cnt[j]; - avg_evm2ss[1] = pdm_sat_table->beam_path_evm_2ss_sum[j][1] / pdm_sat_table->beam_path_evm_2ss_cnt[j]; - avg_evm2ss_sum = avg_evm2ss[0] + avg_evm2ss[1]; - beam_path_evm_2ss_cnt_all += pdm_sat_table->beam_path_evm_2ss_cnt[j]; - - pdm_sat_table->beam_set_avg_evm_2ss_pre[j] = (u8)avg_evm2ss_sum; - } - - if (avg_evm2ss_sum > target_beam_max_evm2ss) { - evm2ss_target_beam = j; - target_beam_max_evm2ss = avg_evm2ss_sum; - } - - /*[Decision3: EVM 1ss]-------------------------------------------------------------------*/ - if (pdm_sat_table->beam_path_evm_1ss_cnt[j] != 0) { - avg_evm1ss = pdm_sat_table->beam_path_evm_1ss_sum[j] / pdm_sat_table->beam_path_evm_1ss_cnt[j]; - beam_path_evm_1ss_cnt_all += pdm_sat_table->beam_path_evm_1ss_cnt[j]; - - pdm_sat_table->beam_set_avg_evm_1ss_pre[j] = (u8)avg_evm1ss; - } - - if (avg_evm1ss > target_beam_max_evm1ss) { - evm1ss_target_beam = j; - target_beam_max_evm1ss = avg_evm1ss; - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Beam[%d] Pkt_cnt=(( %d )), avg{MA,rssi}={%d, %d}, EVM1={%d}, EVM2={%d, %d, %d}\n", - j, pdm_sat_table->statistic_pkt_cnt[j], avg_rssi_tmp_ma, avg_rssi_tmp, avg_evm1ss, avg_evm2ss[0], avg_evm2ss[1], avg_evm2ss_sum)); - - /*reset counter value*/ - pdm_sat_table->beam_set_rssi_avg_sum[j] = 0; - pdm_sat_table->beam_path_rssi_sum[j][0] = 0; - pdm_sat_table->beam_path_rssi_sum[j][1] = 0; - pdm_sat_table->statistic_pkt_cnt[j] = 0; - - pdm_sat_table->beam_path_evm_2ss_sum[j][0] = 0; - pdm_sat_table->beam_path_evm_2ss_sum[j][1] = 0; - pdm_sat_table->beam_path_evm_2ss_cnt[j] = 0; - - pdm_sat_table->beam_path_evm_1ss_sum[j] = 0; - pdm_sat_table->beam_path_evm_1ss_cnt[j] = 0; - } - - /*[Joint Decision]-------------------------------------------------------------------*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--->1.[RSSI] Target Beam(( %d )) RSSI_max=((%d))\n", rssi_target_beam, target_beam_max_rssi)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--->2.[Evm2SS] Target Beam(( %d )) EVM2SS_max=((%d))\n", evm2ss_target_beam, target_beam_max_evm2ss)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--->3.[Evm1SS] Target Beam(( %d )) EVM1SS_max=((%d))\n", evm1ss_target_beam, target_beam_max_evm1ss)); - - if (target_beam_max_rssi <= 10) { - pdm_sat_table->rx_idle_beam_set_idx = rssi_target_beam; - decision_type = 1; - } else { - if (beam_path_evm_2ss_cnt_all != 0) { - pdm_sat_table->rx_idle_beam_set_idx = evm2ss_target_beam; - decision_type = 2; - } else if (beam_path_evm_1ss_cnt_all != 0) { - pdm_sat_table->rx_idle_beam_set_idx = evm1ss_target_beam; - decision_type = 3; - } else { - pdm_sat_table->rx_idle_beam_set_idx = rssi_target_beam; - decision_type = 1; - } - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("---> Decision_type=((%d)), Final Target Beam(( %d ))\n", decision_type, pdm_sat_table->rx_idle_beam_set_idx )); - - /*Calculate packet counter offset*/ - for (j = 0; j < (pdm_sat_table->total_beam_set_num); j++) { - - if (decision_type == 1) { - per_beam_val_diff_tmp = target_beam_max_rssi - pdm_sat_table->beam_set_avg_rssi_pre[j]; - - } else if (decision_type == 2) { - per_beam_val_diff_tmp = ((u8)target_beam_max_evm2ss - pdm_sat_table->beam_set_avg_evm_2ss_pre[j]) >> 1; - } else if (decision_type == 3) { - per_beam_val_diff_tmp = (u8)target_beam_max_evm1ss - pdm_sat_table->beam_set_avg_evm_1ss_pre[j]; - } - pdm_sat_table->beam_set_train_val_diff[j] = per_beam_val_diff_tmp; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Beam_Set[%d]: diff= ((%d))\n", j, per_beam_val_diff_tmp)); - } - - /*set beam in each antenna*/ - phydm_update_rx_idle_beam_type2(p_dm_odm); - p_dm_fat_table->fat_state = FAT_PREPARE_STATE; - - } - /* [TRAINING STATE] */ - else if (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2. In Training state]\n")); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("curr_beam_idx = (( %d )), pre_beam_idx = (( %d ))\n", - pdm_sat_table->fast_training_beam_num, pdm_sat_table->pre_fast_training_beam_num)); - - if (pdm_sat_table->fast_training_beam_num > pdm_sat_table->pre_fast_training_beam_num) - - pdm_sat_table->force_update_beam_en = 0; - - else { - - pdm_sat_table->force_update_beam_en = 1; - - pdm_sat_table->pkt_counter = 0; - beam_tmp = pdm_sat_table->fast_training_beam_num; - if (pdm_sat_table->fast_training_beam_num >= ((u32)pdm_sat_table->total_beam_set_num - 1)) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", pdm_sat_table->fast_training_beam_num)); - p_dm_fat_table->fat_state = FAT_DECISION_STATE; - phydm_fast_ant_training_hl_smart_antenna_type2(p_dm_odm); - - } else { - pdm_sat_table->fast_training_beam_num++; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - phydm_set_rfu_beam_pattern_type2(p_dm_odm); - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - - } - } - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Pre_Beam =(( %d ))\n", pdm_sat_table->pre_fast_training_beam_num)); - } - /* [Prepare state] */ - /*=======================================================================================*/ - else if (p_dm_fat_table->fat_state == FAT_PREPARE_STATE) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n\n[ 1. In Prepare state]\n")); - - if (p_dm_odm->pre_traffic_load == (p_dm_odm->traffic_load)) { - if (pdm_sat_table->decision_holding_period != 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Holding_period = (( %d )), return!!!\n", pdm_sat_table->decision_holding_period)); - pdm_sat_table->decision_holding_period--; - return; - } - } - - /* Set training packet number*/ - if (pdm_sat_table->fix_training_num_en == 0) { - - switch (p_dm_odm->traffic_load) { - - case TRAFFIC_HIGH: - pdm_sat_table->per_beam_training_pkt_num = 8; - pdm_sat_table->decision_holding_period = 2; - break; - case TRAFFIC_MID: - pdm_sat_table->per_beam_training_pkt_num = 6; - pdm_sat_table->decision_holding_period = 3; - break; - case TRAFFIC_LOW: - pdm_sat_table->per_beam_training_pkt_num = 3; /*ping 60000*/ - pdm_sat_table->decision_holding_period = 4; - break; - case TRAFFIC_ULTRA_LOW: - pdm_sat_table->per_beam_training_pkt_num = 1; - pdm_sat_table->decision_holding_period = 6; - break; - default: - break; - } - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TrafficLoad = (( %d )), Fix_beam = (( %d )), per_beam_training_pkt_num = (( %d )), decision_holding_period = ((%d))\n", - p_dm_odm->traffic_load, pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); - - /*Beam_set number*/ - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { - pdm_sat_table->total_beam_set_num = pdm_sat_table->total_beam_set_num_5g; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("5G beam_set num = ((%d))\n", pdm_sat_table->total_beam_set_num)); - } else { - pdm_sat_table->total_beam_set_num = pdm_sat_table->total_beam_set_num_2g; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("2G beam_set num = ((%d))\n", pdm_sat_table->total_beam_set_num)); - } - - for (j = 0; j < (pdm_sat_table->total_beam_set_num); j++) { - - training_pkt_num_offset = pdm_sat_table->beam_set_train_val_diff[j]; - - if ((pdm_sat_table->per_beam_training_pkt_num) > training_pkt_num_offset) - pdm_sat_table->beam_set_train_cnt[j] = pdm_sat_table->per_beam_training_pkt_num - training_pkt_num_offset; - else - pdm_sat_table->beam_set_train_cnt[j] = 1; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Beam_Set[ %d ] training_pkt_offset = ((%d)), training_pkt_num = ((%d))\n", - j, pdm_sat_table->beam_set_train_val_diff[j], pdm_sat_table->beam_set_train_cnt[j])); - } - - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->update_beam_idx = 0; - pdm_sat_table->pkt_counter = 0; - - pdm_sat_table->fast_training_beam_num = 0; - phydm_set_rfu_beam_pattern_type2(p_dm_odm); - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - } - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -void -phydm_beam_switch_workitem_callback( - void *p_context -) -{ - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - -#if DEV_BUS_TYPE != RT_PCI_INTERFACE - pdm_sat_table->pkt_skip_statistic_en = 1; -#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en)); - - phydm_update_beam_pattern_type2(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); - -#if DEV_BUS_TYPE != RT_PCI_INTERFACE - /*odm_stall_execution(pdm_sat_table->latch_time);*/ - pdm_sat_table->pkt_skip_statistic_en = 0; -#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en, pdm_sat_table->latch_time)); -} - -void -phydm_beam_decision_workitem_callback( - void *p_context -) -{ - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam decision Workitem Callback\n")); - phydm_fast_ant_training_hl_smart_antenna_type2(p_dm_odm); -} -#endif - -#elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) - -u32 -phydm_construct_hl_beam_codeword( - void *p_dm_void, - u32 *beam_pattern_idx, - u32 ant_num -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 codeword = 0; - u32 data_tmp; - u32 i; - u32 break_counter = 0; - - if (ant_num < 8) { - for (i = 0; i < (pdm_sat_table->ant_num_total); i++) { - /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] ));*/ - if ((i < (pdm_sat_table->first_train_ant - 1)) || (break_counter >= (pdm_sat_table->ant_num))) { - data_tmp = 0; - /**/ - } else { - - break_counter++; - - if (beam_pattern_idx[i] == 0) { - - if (*p_dm_odm->p_band_type == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[0]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[0]; - - } else if (beam_pattern_idx[i] == 1) { - - - if (*p_dm_odm->p_band_type == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[1]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[1]; - - } else if (beam_pattern_idx[i] == 2) { - - if (*p_dm_odm->p_band_type == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[2]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[2]; - - } else if (beam_pattern_idx[i] == 3) { - - if (*p_dm_odm->p_band_type == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[3]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[3]; - } - } - - - codeword |= (data_tmp << (i * 4)); - - } - } - - return codeword; -} - -void -phydm_update_beam_pattern( - void *p_dm_void, - u32 codeword, - u32 codeword_length -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u8 i; - boolean beam_ctrl_signal; - u32 one = 0x1; - u32 reg44_tmp_p, reg44_tmp_n, reg44_ori; - u8 devide_num = 4; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set Beam Pattern =0x%x\n", codeword)); - - reg44_ori = odm_get_mac_reg(p_dm_odm, 0x44, MASKDWORD); - reg44_tmp_p = reg44_ori; - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_ori =0x%x\n", reg44_ori));*/ - - devide_num = (pdm_sat_table->rfu_protocol_type == 2) ? 6 : 4; - - for (i = 0; i <= (codeword_length - 1); i++) { - beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i); - - if (p_dm_odm->debug_components & ODM_COMP_ANT_DIV) { - - if (i == (codeword_length - 1)) { - dbg_print("%d ]\n", beam_ctrl_signal); - /**/ - } else if (i == 0) { - dbg_print("Send codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal); - /**/ - } else if ((i % devide_num) == (devide_num-1)) { - dbg_print("%d | ", beam_ctrl_signal); - /**/ - } else { - dbg_print("%d ", beam_ctrl_signal); - /**/ - } - } - - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - #if (RTL8821A_SUPPORT == 1) - reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT10)); /*clean bit 10 & 11*/ - reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10)); - reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10))); - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n));*/ - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_n); - #endif - } - #if (RTL8822B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - - if (pdm_sat_table->rfu_protocol_type == 2) { - - reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*clean bit 8*/ - reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*get new clk high/low, exclusive-or*/ - - - reg44_tmp_p |= (beam_ctrl_signal << 8); - - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); - ODM_delay_us(10); - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal));*/ - - } else { - reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT8)); /*clean bit 9 & 8*/ - reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8)); - reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8))); - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n)); */ - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); - ODM_delay_us(10); - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_n); - ODM_delay_us(10); - } - } - #endif - } -} - -void -phydm_update_rx_idle_beam( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 i; - - pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(p_dm_odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set target beam_pattern codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); - - for (i = 0; i < (pdm_sat_table->ant_num); i++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i, pdm_sat_table->rx_idle_beam[i])); - /**/ - } - -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); -#else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); - /*odm_stall_execution(1);*/ -#endif - - pdm_sat_table->pre_codeword = pdm_sat_table->update_beam_codeword; -} - -void -phydm_hl_smart_ant_debug( - void *p_dm_void, - char input[][16], - u32 *_used, - char *output, - u32 *_out_len, - u32 input_num -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 used = *_used; - u32 out_len = *_out_len; - u32 one = 0x1; - u32 codeword_length = pdm_sat_table->rfu_codeword_total_bit_num; - u32 beam_ctrl_signal, i; - u8 devide_num = 4; - - if (dm_value[0] == 1) { /*fix beam pattern*/ - - pdm_sat_table->fix_beam_pattern_en = dm_value[1]; - - if (pdm_sat_table->fix_beam_pattern_en == 1) { - - pdm_sat_table->fix_beam_pattern_codeword = dm_value[2]; - - if (pdm_sat_table->fix_beam_pattern_codeword > (one << codeword_length)) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n", - pdm_sat_table->fix_beam_pattern_codeword, codeword_length)); - - (pdm_sat_table->fix_beam_pattern_codeword) &= 0xffffff; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Auto modify to (0x%x)\n", pdm_sat_table->fix_beam_pattern_codeword)); - } - - pdm_sat_table->update_beam_codeword = pdm_sat_table->fix_beam_pattern_codeword; - - /*---------------------------------------------------------*/ - PHYDM_SNPRINTF((output + used, out_len - used, "Fix Beam Pattern\n")); - - devide_num = (pdm_sat_table->rfu_protocol_type == 2) ? 6 : 4; - - for (i = 0; i <= (codeword_length - 1); i++) { - beam_ctrl_signal = (boolean)((pdm_sat_table->update_beam_codeword & BIT(i)) >> i); - - if (i == (codeword_length - 1)) { - PHYDM_SNPRINTF((output + used, out_len - used, "%d]\n", beam_ctrl_signal)); - /**/ - } else if (i == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "Send Codeword[1:24] to RFU -> [%d", beam_ctrl_signal)); - /**/ - } else if ((i % devide_num) == (devide_num-1)) { - PHYDM_SNPRINTF((output + used, out_len - used, "%d|", beam_ctrl_signal)); - /**/ - } else { - PHYDM_SNPRINTF((output + used, out_len - used, "%d", beam_ctrl_signal)); - /**/ - } - } - /*---------------------------------------------------------*/ - - -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); -#else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); - /*odm_stall_execution(1);*/ -#endif - } else if (pdm_sat_table->fix_beam_pattern_en == 0) - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Smart Antenna: Enable\n")); - - } else if (dm_value[0] == 2) { /*set latch time*/ - - pdm_sat_table->latch_time = dm_value[1]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] latch_time =0x%x\n", pdm_sat_table->latch_time)); - } else if (dm_value[0] == 3) { - - pdm_sat_table->fix_training_num_en = dm_value[1]; - - if (pdm_sat_table->fix_training_num_en == 1) { - pdm_sat_table->per_beam_training_pkt_num = (u8)dm_value[2]; - pdm_sat_table->decision_holding_period = (u8)dm_value[3]; - - PHYDM_SNPRINTF((output + used, out_len - used, "[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", - pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); - - } else if (pdm_sat_table->fix_training_num_en == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] AUTO per_beam_training_pkt_num\n")); - /**/ - } - } else if (dm_value[0] == 4) { - - if (dm_value[1] == 1) { - pdm_sat_table->ant_num = 1; - pdm_sat_table->first_train_ant = MAIN_ANT; - - } else if (dm_value[1] == 2) { - pdm_sat_table->ant_num = 1; - pdm_sat_table->first_train_ant = AUX_ANT; - - } else if (dm_value[1] == 3) { - pdm_sat_table->ant_num = 2; - pdm_sat_table->first_train_ant = MAIN_ANT; - } - - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set ant Num = (( %d )), first_train_ant = (( %d ))\n", - pdm_sat_table->ant_num, (pdm_sat_table->first_train_ant - 1))); - } else if (dm_value[0] == 5) { - - if (dm_value[1] <= 3) { - pdm_sat_table->rfu_codeword_table[dm_value[1]] = dm_value[2]; - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", - dm_value[1], dm_value[2])); - } else { - for (i = 0; i < 4; i++) { - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", - i, pdm_sat_table->rfu_codeword_table[i])); - } - } - } else if (dm_value[0] == 6) { - - if (dm_value[1] <= 3) { - pdm_sat_table->rfu_codeword_table_5g[dm_value[1]] = dm_value[2]; - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", - dm_value[1], dm_value[2])); - } else { - for (i = 0; i < 4; i++) { - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", - i, pdm_sat_table->rfu_codeword_table_5g[i])); - } - } - } else if (dm_value[0] == 7) { - - if (dm_value[1] <= 4) { - - pdm_sat_table->beam_patten_num_each_ant = dm_value[1]; - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set Beam number = (( %d ))\n", - pdm_sat_table->beam_patten_num_each_ant)); - } else { - - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Show Beam number = (( %d ))\n", - pdm_sat_table->beam_patten_num_each_ant)); - } - } - -} - - -void -phydm_set_all_ant_same_beam_num( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - - if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { /*2ant for 8821A*/ - - pdm_sat_table->rx_idle_beam[0] = pdm_sat_table->fast_training_beam_num; - pdm_sat_table->rx_idle_beam[1] = pdm_sat_table->fast_training_beam_num; - } - - pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(p_dm_odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); - -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); -#else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); - /*odm_stall_execution(1);*/ -#endif -} - -void -odm_fast_ant_training_hl_smart_antenna_type1( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &(p_dm_odm->dm_fat_table); - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - u32 codeword = 0, i, j; - u32 target_ant; - u32 avg_rssi_tmp, avg_rssi_tmp_ma; - u32 target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0}; - u32 max_beam_ant_rssi = 0; - u32 target_ant_beam[SUPPORT_RF_PATH_NUM] = {0}; - u32 beam_tmp; - u8 next_ant; - u32 rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; - u32 rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; - u32 rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0}; - u8 per_beam_rssi_diff_tmp = 0, training_pkt_num_offset; - u32 break_counter = 0; - u32 used_ant; - - - if (!p_dm_odm->is_linked) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - - if (p_dm_fat_table->is_become_linked == true) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Link->no Link\n")); - p_dm_fat_table->fat_state = FAT_BEFORE_LINK_STATE; - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", p_dm_fat_table->fat_state)); - - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; - } - return; - - } else { - if (p_dm_fat_table->is_become_linked == false) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); - - p_dm_fat_table->fat_state = FAT_PREPARE_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", p_dm_fat_table->fat_state)); - - /*pdm_sat_table->fast_training_beam_num = 0;*/ - /*phydm_set_all_ant_same_beam_num(p_dm_odm);*/ - - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; - } - } - - if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) { - if (p_dm_odm->is_one_entry_only == true) - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); - else - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); - } - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("HL Smart ant Training: state (( %d ))\n", p_dm_fat_table->fat_state));*/ - - /* [DECISION STATE] */ - /*=======================================================================================*/ - if (p_dm_fat_table->fat_state == FAT_DECISION_STATE) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 3. In Decision state]\n")); - phydm_fast_training_enable(p_dm_odm, FAT_OFF); - - break_counter = 0; - /*compute target beam in each antenna*/ - for (i = (pdm_sat_table->first_train_ant - 1); i < pdm_sat_table->ant_num_total; i++) { - for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { - - if (pdm_sat_table->pkt_rssi_cnt[i][j] == 0) { - avg_rssi_tmp = pdm_sat_table->pkt_rssi_pre[i][j]; - avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; - avg_rssi_tmp_ma = avg_rssi_tmp; - } else { - avg_rssi_tmp = (pdm_sat_table->pkt_rssi_sum[i][j]) / (pdm_sat_table->pkt_rssi_cnt[i][j]); - avg_rssi_tmp_ma = (avg_rssi_tmp + pdm_sat_table->pkt_rssi_pre[i][j]) >> 1; - } - - rssi_sorting_seq[j] = avg_rssi_tmp; - pdm_sat_table->pkt_rssi_pre[i][j] = avg_rssi_tmp; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n", - i, j, pdm_sat_table->pkt_rssi_cnt[i][j], avg_rssi_tmp_ma, avg_rssi_tmp)); - - if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) { - target_ant_beam[i] = j; - target_ant_beam_max_rssi[i] = avg_rssi_tmp; - } - - /*reset counter value*/ - pdm_sat_table->pkt_rssi_sum[i][j] = 0; - pdm_sat_table->pkt_rssi_cnt[i][j] = 0; - - } - pdm_sat_table->rx_idle_beam[i] = target_ant_beam[i]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("---------> Target of ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n", - i, target_ant_beam[i], target_ant_beam_max_rssi[i])); - - /*sorting*/ - /* - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3])); - */ - - /*phydm_seq_sorting(p_dm_odm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/ - - /* - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rank_idx_seq = [%d, %d, %d, %d]\n", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rank_idx_out = [%d, %d, %d, %d]\n", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3])); - */ - - if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) { - target_ant = i; - max_beam_ant_rssi = target_ant_beam_max_rssi[i]; - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Target of ant = (( %d )) max_beam_ant_rssi = (( %d ))\n", - target_ant, max_beam_ant_rssi));*/ - } - break_counter++; - if (break_counter >= (pdm_sat_table->ant_num)) - break; - } - -#ifdef CONFIG_FAT_PATCH - break_counter = 0; - for (i = (pdm_sat_table->first_train_ant - 1); i < pdm_sat_table->ant_num_total; i++) { - for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { - - per_beam_rssi_diff_tmp = (u8)(max_beam_ant_rssi - pdm_sat_table->pkt_rssi_pre[i][j]); - pdm_sat_table->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ant[%d], Beam[%d]: RSSI_diff= ((%d))\n", - i, j, per_beam_rssi_diff_tmp)); - } - break_counter++; - if (break_counter >= (pdm_sat_table->ant_num)) - break; - } -#endif - - if (target_ant == 0) - target_ant = MAIN_ANT; - else if (target_ant == 1) - target_ant = AUX_ANT; - - if (pdm_sat_table->ant_num > 1) { - /* [ update RX ant ]*/ - odm_update_rx_idle_ant(p_dm_odm, (u8)target_ant); - - /* [ update TX ant ]*/ - odm_update_tx_ant(p_dm_odm, (u8)target_ant, (p_dm_fat_table->train_idx)); - } - - /*set beam in each antenna*/ - phydm_update_rx_idle_beam(p_dm_odm); - - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - p_dm_fat_table->fat_state = FAT_PREPARE_STATE; - return; - - } - /* [TRAINING STATE] */ - else if (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2. In Training state]\n")); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n", - pdm_sat_table->fast_training_beam_num, pdm_sat_table->pre_fast_training_beam_num)); - - if (pdm_sat_table->fast_training_beam_num > pdm_sat_table->pre_fast_training_beam_num) - - pdm_sat_table->force_update_beam_en = 0; - - else { - - pdm_sat_table->force_update_beam_en = 1; - - pdm_sat_table->pkt_counter = 0; - beam_tmp = pdm_sat_table->fast_training_beam_num; - if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant - 1)) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", pdm_sat_table->fast_training_beam_num)); - p_dm_fat_table->fat_state = FAT_DECISION_STATE; - odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); - - } else { - pdm_sat_table->fast_training_beam_num++; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - phydm_set_all_ant_same_beam_num(p_dm_odm); - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - - } - } - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[prepare state] Update Pre_Beam =(( %d ))\n", pdm_sat_table->pre_fast_training_beam_num)); - } - /* [Prepare state] */ - /*=======================================================================================*/ - else if (p_dm_fat_table->fat_state == FAT_PREPARE_STATE) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n\n[ 1. In Prepare state]\n")); - - if (p_dm_odm->pre_traffic_load == (p_dm_odm->traffic_load)) { - if (pdm_sat_table->decision_holding_period != 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Holding_period = (( %d )), return!!!\n", pdm_sat_table->decision_holding_period)); - pdm_sat_table->decision_holding_period--; - return; - } - } - - - /* Set training packet number*/ - if (pdm_sat_table->fix_training_num_en == 0) { - - switch (p_dm_odm->traffic_load) { - - case TRAFFIC_HIGH: - pdm_sat_table->per_beam_training_pkt_num = 8; - pdm_sat_table->decision_holding_period = 2; - break; - case TRAFFIC_MID: - pdm_sat_table->per_beam_training_pkt_num = 6; - pdm_sat_table->decision_holding_period = 3; - break; - case TRAFFIC_LOW: - pdm_sat_table->per_beam_training_pkt_num = 3; /*ping 60000*/ - pdm_sat_table->decision_holding_period = 4; - break; - case TRAFFIC_ULTRA_LOW: - pdm_sat_table->per_beam_training_pkt_num = 1; - pdm_sat_table->decision_holding_period = 6; - break; - default: - break; - } - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\n", - pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); - - -#ifdef CONFIG_FAT_PATCH - break_counter = 0; - for (i = (pdm_sat_table->first_train_ant - 1); i < pdm_sat_table->ant_num_total; i++) { - for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { - - per_beam_rssi_diff_tmp = pdm_sat_table->beam_train_rssi_diff[i][j]; - training_pkt_num_offset = per_beam_rssi_diff_tmp; - - if ((pdm_sat_table->per_beam_training_pkt_num) > training_pkt_num_offset) - pdm_sat_table->beam_train_cnt[i][j] = pdm_sat_table->per_beam_training_pkt_num - training_pkt_num_offset; - else - pdm_sat_table->beam_train_cnt[i][j] = 1; - - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ant[%d]: Beam_num-(( %d )) training_pkt_num = ((%d))\n", - i, j, pdm_sat_table->beam_train_cnt[i][j])); - } - break_counter++; - if (break_counter >= (pdm_sat_table->ant_num)) - break; - } - - - phydm_fast_training_enable(p_dm_odm, FAT_OFF); - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->update_beam_idx = 0; - - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set 5G ant\n")); - /*used_ant = (pdm_sat_table->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/ - used_ant = pdm_sat_table->first_train_ant; - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set 2.4G ant\n")); - used_ant = pdm_sat_table->first_train_ant; - } - - odm_update_rx_idle_ant(p_dm_odm, (u8)used_ant); - -#else - /* Set training MAC addr. of target */ - odm_set_next_mac_addr_target(p_dm_odm); - phydm_fast_training_enable(p_dm_odm, FAT_ON); -#endif - - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - pdm_sat_table->pkt_counter = 0; - pdm_sat_table->fast_training_beam_num = 0; - phydm_set_all_ant_same_beam_num(p_dm_odm); - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - } - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -void -phydm_beam_switch_workitem_callback( - void *p_context -) -{ - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - -#if DEV_BUS_TYPE != RT_PCI_INTERFACE - pdm_sat_table->pkt_skip_statistic_en = 1; -#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en)); - - phydm_update_beam_pattern(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); - -#if DEV_BUS_TYPE != RT_PCI_INTERFACE - /*odm_stall_execution(pdm_sat_table->latch_time);*/ - pdm_sat_table->pkt_skip_statistic_en = 0; -#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en, pdm_sat_table->latch_time)); -} - -void -phydm_beam_decision_workitem_callback( - void *p_context -) -{ - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam decision Workitem Callback\n")); - odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); -} -#endif - -#endif /*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ - -void -odm_ant_div_init( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - - - if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] Not Support Antenna Diversity Function\n")); - return; - } - /* --- */ -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_2G) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n")); - if (!(p_dm_odm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)) - return; - } else if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_5G) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n")); - if (!(p_dm_odm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)) - return; - } else if (p_dm_fat_table->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n")); - -#endif - /* --- */ - - /* 2 [--General---] */ - p_dm_odm->antdiv_period = 0; - - p_dm_fat_table->is_become_linked = false; - p_dm_fat_table->ant_div_on_off = 0xff; - - /* 3 - AP - */ -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - -#if (BEAMFORMING_SUPPORT == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - odm_bdc_init(p_dm_odm); -#endif -#endif - - /* 3 - WIN - */ -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_dm_swat_table->ant_5g = MAIN_ANT; - p_dm_swat_table->ant_2g = MAIN_ANT; -#endif - - /* 2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */ - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - - p_dm_odm->ant_type = ODM_AUTO_ANT; - - p_dm_fat_table->rx_idle_ant = 0xff; /*to make RX-idle-antenna will be updated absolutly*/ - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); - phydm_keep_rx_ack_ant_by_tx_ant_time(p_dm_odm, 0); /* Timming issue: keep Rx ant after tx for ACK ( 5 x 3.2 mu = 16mu sec)*/ - - /* 2 [---Set TX Antenna---] */ - if (p_dm_fat_table->p_force_tx_ant_by_desc == NULL) { - p_dm_fat_table->force_tx_ant_by_desc = 0; - p_dm_fat_table->p_force_tx_ant_by_desc = &(p_dm_fat_table->force_tx_ant_by_desc); - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_force_tx_ant_by_desc = %d\n", *p_dm_fat_table->p_force_tx_ant_by_desc)); - - if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == true) - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); - else - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); - - - /* 2 [--88E---] */ - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { -#if (RTL8188E_SUPPORT == 1) - /* p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; */ - /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ - /* p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; */ - - if ((p_dm_odm->ant_div_type != CGCS_RX_HW_ANTDIV) && (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) && (p_dm_odm->ant_div_type != CG_TRX_SMART_ANTDIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 88E Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); - return; - } - - if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) - odm_rx_hw_ant_div_init_88e(p_dm_odm); - else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_trx_hw_ant_div_init_88e(p_dm_odm); -#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - else if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) - odm_smart_hw_ant_div_init_88e(p_dm_odm); -#endif -#endif - } + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_rx_hw_ant_div_init_88e(dm); + else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_88e(dm); +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_smart_hw_ant_div_init_88e(dm); +#endif +#endif + } /* 2 [--92E---] */ #if (RTL8192E_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - /* p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; */ - /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ - /* p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; */ - - if ((p_dm_odm->ant_div_type != CGCS_RX_HW_ANTDIV) && (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) && (p_dm_odm->ant_div_type != CG_TRX_SMART_ANTDIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8192E Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + else if (dm->support_ic_type == ODM_RTL8192E) { + /* dm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + /* dm->ant_div_type = CG_TRX_SMART_ANTDIV; */ + + if ((dm->ant_div_type != CGCS_RX_HW_ANTDIV) && (dm->ant_div_type != CG_TRX_HW_ANTDIV) && (dm->ant_div_type != CG_TRX_SMART_ANTDIV)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Return!!!] 8192E Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); return; } - if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) - odm_rx_hw_ant_div_init_92e(p_dm_odm); - else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_trx_hw_ant_div_init_92e(p_dm_odm); + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_rx_hw_ant_div_init_92e(dm); + else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_92e(dm); #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - else if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) - odm_smart_hw_ant_div_init_92e(p_dm_odm); + else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_smart_hw_ant_div_init_92e(dm); #endif } @@ -5059,41 +3504,41 @@ odm_ant_div_init( /* 2 [--8723B---] */ #if (RTL8723B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ + else if (dm->support_ic_type == ODM_RTL8723B) { + dm->ant_div_type = S0S1_SW_ANTDIV; + /* dm->ant_div_type = CG_TRX_HW_ANTDIV; */ - if (p_dm_odm->ant_div_type != S0S1_SW_ANTDIV && p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8723B Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + if (dm->ant_div_type != S0S1_SW_ANTDIV && dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Return!!!] 8723B Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); return; } - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) - odm_s0s1_sw_ant_div_init_8723b(p_dm_odm); - else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_trx_hw_ant_div_init_8723b(p_dm_odm); + if (dm->ant_div_type == S0S1_SW_ANTDIV) + odm_s0s1_sw_ant_div_init_8723b(dm); + else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8723b(dm); } #endif /*2 [--8723D---]*/ #if (RTL8723D_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - if (p_dm_fat_table->p_default_s0_s1 == NULL) { - p_dm_fat_table->default_s0_s1 = 1; - p_dm_fat_table->p_default_s0_s1 = &(p_dm_fat_table->default_s0_s1); + else if (dm->support_ic_type == ODM_RTL8723D) { + if (fat_tab->p_default_s0_s1 == NULL) { + fat_tab->default_s0_s1 = 1; + fat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("default_s0_s1 = %d\n", *p_dm_fat_table->p_default_s0_s1)); + PHYDM_DBG(dm, DBG_ANT_DIV, "default_s0_s1 = %d\n", *fat_tab->p_default_s0_s1); - if (*(p_dm_fat_table->p_default_s0_s1) == true) - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); + if (*fat_tab->p_default_s0_s1 == true) + odm_update_rx_idle_ant(dm, MAIN_ANT); else - odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); + odm_update_rx_idle_ant(dm, AUX_ANT); - if (p_dm_odm->ant_div_type == S0S1_TRX_HW_ANTDIV) - odm_trx_hw_ant_div_init_8723d(p_dm_odm); + if (dm->ant_div_type == S0S1_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8723d(dm); else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8723D Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Return!!!] 8723D Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); return; } @@ -5101,261 +3546,269 @@ odm_ant_div_init( #endif /* 2 [--8811A 8821A---] */ #if (RTL8821A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8821) { + else if (dm->support_ic_type == ODM_RTL8821) { #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - p_dm_odm->ant_div_type = HL_SW_SMART_ANT_TYPE1; + dm->ant_div_type = HL_SW_SMART_ANT_TYPE1; - if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { - - odm_trx_hw_ant_div_init_8821a(p_dm_odm); - phydm_hl_smart_ant_type1_init_8821a(p_dm_odm); + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { + odm_trx_hw_ant_div_init_8821a(dm); + phydm_hl_smart_ant_type1_init_8821a(dm); } else #endif { - /*p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV;*/ - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; + #ifdef ODM_CONFIG_BT_COEXIST + dm->ant_div_type = S0S1_SW_ANTDIV; + #else + dm->ant_div_type = CG_TRX_HW_ANTDIV; + #endif - if (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV && p_dm_odm->ant_div_type != S0S1_SW_ANTDIV) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821A & 8811A Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + if (dm->ant_div_type != CG_TRX_HW_ANTDIV && dm->ant_div_type != S0S1_SW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Return!!!] 8821A & 8811A Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); return; } - if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_trx_hw_ant_div_init_8821a(p_dm_odm); - else if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) - odm_s0s1_sw_ant_div_init_8821a(p_dm_odm); + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8821a(dm); + else if (dm->ant_div_type == S0S1_SW_ANTDIV) + odm_s0s1_sw_ant_div_init_8821a(dm); } } #endif /* 2 [--8821C---] */ #if (RTL8821C_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8821C) { - p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; - if (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821C Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + else if (dm->support_ic_type == ODM_RTL8821C) { + dm->ant_div_type = S0S1_SW_ANTDIV; + if (dm->ant_div_type != S0S1_SW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Return!!!] 8821C Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); return; } - odm_trx_hw_ant_div_init_8821c(p_dm_odm); + phydm_s0s1_sw_ant_div_init_8821c(dm); + odm_trx_hw_ant_div_init_8821c(dm); } #endif /* 2 [--8881A---] */ #if (RTL8881A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8881A) { - /* p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; */ - /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ - - if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) { + else if (dm->support_ic_type == ODM_RTL8881A) { + /* dm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* dm->ant_div_type = CG_TRX_HW_ANTDIV; */ - odm_trx_hw_ant_div_init_8881a(p_dm_odm); + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_trx_hw_ant_div_init_8881a(dm); /**/ } else { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8881A Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Return!!!] 8881A Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); return; } - odm_trx_hw_ant_div_init_8881a(p_dm_odm); + odm_trx_hw_ant_div_init_8881a(dm); } #endif /* 2 [--8812---] */ #if (RTL8812A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8812) { - /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ + else if (dm->support_ic_type == ODM_RTL8812) { + /* dm->ant_div_type = CG_TRX_HW_ANTDIV; */ - if (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8812A Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + if (dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Return!!!] 8812A Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); return; } - odm_trx_hw_ant_div_init_8812a(p_dm_odm); + odm_trx_hw_ant_div_init_8812a(dm); } #endif /*[--8188F---]*/ #if (RTL8188F_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - odm_s0s1_sw_ant_div_init_8188f(p_dm_odm); + else if (dm->support_ic_type == ODM_RTL8188F) { + dm->ant_div_type = S0S1_SW_ANTDIV; + odm_s0s1_sw_ant_div_init_8188f(dm); } #endif /*[--8822B---]*/ #if (RTL8822B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + else if (dm->support_ic_type == ODM_RTL8822B) { #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - p_dm_odm->ant_div_type = HL_SW_SMART_ANT_TYPE2; + dm->ant_div_type = HL_SW_SMART_ANT_TYPE2; - if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE2) - phydm_hl_smart_ant_type2_init_8822b(p_dm_odm); + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) + phydm_hl_smart_ant_type2_init_8822b(dm); #endif } #endif /* - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** support_ic_type=[%lu]\n",p_dm_odm->support_ic_type)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv support_ability=[%lu]\n",(p_dm_odm->support_ability & ODM_BB_ANT_DIV)>>6)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv type=[%d]\n",p_dm_odm->ant_div_type)); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** support_ic_type=[%lu]\n",dm->support_ic_type); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv support_ability=[%lu]\n",(dm->support_ability & ODM_BB_ANT_DIV)>>6); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv type=[%d]\n",dm->ant_div_type); */ } void odm_ant_div( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; +#if (defined(CONFIG_HL_SMART_ANTENNA)) + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; #endif #ifdef ODM_EVM_ENHANCE_ANTDIV - if (p_dm_odm->is_linked) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tp_active_occur=((%d)), EVM_method_enable=((%d))\n", - p_dm_odm->tp_active_occur, p_dm_fat_table->EVM_method_enable)); + if (dm->is_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, "tp_active_occur=((%d)), evm_method_enable=((%d))\n", + dm->tp_active_occur, fat_tab->evm_method_enable); - if ((p_dm_odm->tp_active_occur == 1) && (p_dm_fat_table->EVM_method_enable == 1)) { - - p_dm_fat_table->idx_ant_div_counter_5g = p_dm_odm->antdiv_period; - p_dm_fat_table->idx_ant_div_counter_2g = p_dm_odm->antdiv_period; + if ((dm->tp_active_occur == 1) && (fat_tab->evm_method_enable == 1)) { + fat_tab->idx_ant_div_counter_5g = dm->antdiv_period; + fat_tab->idx_ant_div_counter_2g = dm->antdiv_period; } } #endif - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { - if (p_dm_fat_table->idx_ant_div_counter_5g < p_dm_odm->antdiv_period) { - p_dm_fat_table->idx_ant_div_counter_5g++; + if (*dm->band_type == ODM_BAND_5G) { + if (fat_tab->idx_ant_div_counter_5g < dm->antdiv_period) { + fat_tab->idx_ant_div_counter_5g++; return; } else - p_dm_fat_table->idx_ant_div_counter_5g = 0; - } else if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { - if (p_dm_fat_table->idx_ant_div_counter_2g < p_dm_odm->antdiv_period) { - p_dm_fat_table->idx_ant_div_counter_2g++; + fat_tab->idx_ant_div_counter_5g = 0; + } else if (*dm->band_type == ODM_BAND_2_4G) { + if (fat_tab->idx_ant_div_counter_2g < dm->antdiv_period) { + fat_tab->idx_ant_div_counter_2g++; return; } else - p_dm_fat_table->idx_ant_div_counter_2g = 0; + fat_tab->idx_ant_div_counter_2g = 0; } /* ---------- */ - if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] Not Support Antenna Diversity Function\n")); - return; - } /* ---------- */ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE) - if (p_dm_fat_table->enable_ctrl_frame_antdiv) { - - if ((p_dm_odm->data_frame_num <= 10) && (p_dm_odm->is_linked)) - p_dm_fat_table->use_ctrl_frame_antdiv = 1; + if (fat_tab->enable_ctrl_frame_antdiv) { + if ((dm->data_frame_num <= 10) && (dm->is_linked)) + fat_tab->use_ctrl_frame_antdiv = 1; else - p_dm_fat_table->use_ctrl_frame_antdiv = 0; + fat_tab->use_ctrl_frame_antdiv = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n", p_dm_fat_table->use_ctrl_frame_antdiv, p_dm_odm->data_frame_num)); - p_dm_odm->data_frame_num = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n", fat_tab->use_ctrl_frame_antdiv, dm->data_frame_num); + dm->data_frame_num = 0; } - if (p_adapter->MgntInfo.AntennaTest) - return; - { #if (BEAMFORMING_SUPPORT == 1) - enum beamforming_cap beamform_cap = (p_dm_odm->beamforming_info.beamform_cap); - - if (beamform_cap & BEAMFORMEE_CAP) { /* BFmee On && Div On->Div Off */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ AntDiv : OFF ] BFmee ==1\n")); - if (p_dm_fat_table->fix_ant_bfee == 0) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - p_dm_fat_table->fix_ant_bfee = 1; - } - return; - } else { /* BFmee Off && Div Off->Div On */ - if ((p_dm_fat_table->fix_ant_bfee == 1) && p_dm_odm->is_linked) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ AntDiv : ON ] BFmee ==0\n")); - if ((p_dm_odm->ant_div_type != S0S1_SW_ANTDIV)) - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - p_dm_fat_table->fix_ant_bfee = 0; + enum beamforming_cap beamform_cap = phydm_get_beamform_cap(dm); + PHYDM_DBG(dm, DBG_ANT_DIV, "is_bt_continuous_turn = ((%d))\n", dm->is_bt_continuous_turn); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ AntDiv Beam Cap ] cap= ((%d))\n", beamform_cap); + if (!dm->is_bt_continuous_turn) { + if ((beamform_cap & BEAMFORMEE_CAP) && (!(*fat_tab->is_no_csi_feedback))) { /* BFmee On && Div On->Div Off */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[ AntDiv : OFF ] BFmee ==1; cap= ((%d))\n", beamform_cap); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ AntDiv BF] is_no_csi_feedback= ((%d))\n", *(fat_tab->is_no_csi_feedback)); + if (fat_tab->fix_ant_bfee == 0) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + fat_tab->fix_ant_bfee = 1; + } + return; + } else { /* BFmee Off && Div Off->Div On */ + if ((fat_tab->fix_ant_bfee == 1) && dm->is_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ AntDiv : ON ] BFmee ==0; cap=((%d))\n", beamform_cap); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ AntDiv BF] is_no_csi_feedback= ((%d))\n", *(fat_tab->is_no_csi_feedback)); + if (dm->ant_div_type != S0S1_SW_ANTDIV) + odm_ant_div_on_off(dm, ANTDIV_ON); + + fat_tab->fix_ant_bfee = 0; + } } + } else { + odm_ant_div_on_off(dm, ANTDIV_ON); } #endif } #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) /* ----------just for fool proof */ - if (p_dm_odm->antdiv_rssi) - p_dm_odm->debug_components |= ODM_COMP_ANT_DIV; + if (dm->antdiv_rssi) + dm->debug_components |= DBG_ANT_DIV; else - p_dm_odm->debug_components &= ~ODM_COMP_ANT_DIV; + dm->debug_components &= ~DBG_ANT_DIV; - if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_2G) { - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G AntDiv Running ]\n")); */ - if (!(p_dm_odm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)) + if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) { + /* PHYDM_DBG(dm, DBG_ANT_DIV,"[ 2G AntDiv Running ]\n"); */ + if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)) return; - } else if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_5G) { - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 5G AntDiv Running ]\n")); */ - if (!(p_dm_odm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)) + } else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) { + /* PHYDM_DBG(dm, DBG_ANT_DIV,"[ 5G AntDiv Running ]\n"); */ + if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)) return; } - /* else if(p_dm_fat_table->ant_div_2g_5g == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) */ + /* else if(fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) */ /* { */ - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G & 5G AntDiv Running ]\n")); */ + /* PHYDM_DBG(dm, DBG_ANT_DIV,"[ 2G & 5G AntDiv Running ]\n"); */ /* } */ #endif /* ---------- */ - if (p_dm_odm->antdiv_select == 1) - p_dm_odm->ant_type = ODM_FIX_MAIN_ANT; - else if (p_dm_odm->antdiv_select == 2) - p_dm_odm->ant_type = ODM_FIX_AUX_ANT; - else /* if (p_dm_odm->antdiv_select==0) */ - p_dm_odm->ant_type = ODM_AUTO_ANT; + if (dm->antdiv_select == 1) + dm->ant_type = ODM_FIX_MAIN_ANT; + else if (dm->antdiv_select == 2) + dm->ant_type = ODM_FIX_AUX_ANT; + else { /* if (dm->antdiv_select==0) */ + dm->ant_type = ODM_AUTO_ANT; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /*Stop Antenna diversity for CMW500 testing case*/ + if (dm->consecutive_idlel_time >= 10) { + dm->ant_type = ODM_FIX_MAIN_ANT; + PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv: OFF] No TP case, consecutive_idlel_time=((%d))\n", dm->consecutive_idlel_time); + } + #endif + } - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("ant_type= (( %d )) , pre_ant_type= (( %d ))\n",p_dm_odm->ant_type,p_dm_odm->pre_ant_type)); */ + /* PHYDM_DBG(dm, DBG_ANT_DIV,"ant_type= (( %d )) , pre_ant_type= (( %d ))\n",dm->ant_type,dm->pre_ant_type); */ - if (p_dm_odm->ant_type != ODM_AUTO_ANT) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix Antenna at (( %s ))\n", (p_dm_odm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX")); + if (dm->ant_type != ODM_AUTO_ANT) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Fix Antenna at (( %s ))\n", (dm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX"); - if (p_dm_odm->ant_type != p_dm_odm->pre_ant_type) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + if (dm->ant_type != dm->pre_ant_type) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); - if (p_dm_odm->ant_type == ODM_FIX_MAIN_ANT) - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); - else if (p_dm_odm->ant_type == ODM_FIX_AUX_ANT) - odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); + if (dm->ant_type == ODM_FIX_MAIN_ANT) + odm_update_rx_idle_ant(dm, MAIN_ANT); + else if (dm->ant_type == ODM_FIX_AUX_ANT) + odm_update_rx_idle_ant(dm, AUX_ANT); } - p_dm_odm->pre_ant_type = p_dm_odm->ant_type; + dm->pre_ant_type = dm->ant_type; return; } else { - if (p_dm_odm->ant_type != p_dm_odm->pre_ant_type) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); + if (dm->ant_type != dm->pre_ant_type) { + odm_ant_div_on_off(dm, ANTDIV_ON); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); } - p_dm_odm->pre_ant_type = p_dm_odm->ant_type; + dm->pre_ant_type = dm->ant_type; } /* 3 ----------------------------------------------------------------------------------------------------------- */ /* 2 [--88E---] */ - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + if (dm->support_ic_type == ODM_RTL8188E) { #if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV || p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) - odm_hw_ant_div(p_dm_odm); + if (dm->ant_div_type == CG_TRX_HW_ANTDIV || dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_hw_ant_div(dm); #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - else if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) - odm_fast_ant_training(p_dm_odm); + else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_fast_ant_training(dm); #endif #endif @@ -5363,13 +3816,13 @@ odm_ant_div( } /* 2 [--92E---] */ #if (RTL8192E_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV || p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_hw_ant_div(p_dm_odm); + else if (dm->support_ic_type == ODM_RTL8192E) { + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV || dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(dm); #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - else if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) - odm_fast_ant_training(p_dm_odm); + else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_fast_ant_training(dm); #endif } @@ -5377,122 +3830,133 @@ odm_ant_div( #if (RTL8723B_SUPPORT == 1) /* 2 [--8723B---] */ - else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - if (phydm_is_bt_enable_8723b(p_dm_odm)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BT is enable!!!]\n")); - if (p_dm_fat_table->is_become_linked == true) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); - if (p_dm_odm->support_ic_type == ODM_RTL8723B) - odm_set_bb_reg(p_dm_odm, 0x948, BIT(9) | BIT(8) | BIT(7) | BIT(6), 0x0); - - p_dm_fat_table->is_become_linked = false; + else if (dm->support_ic_type == ODM_RTL8723B) { + if (phydm_is_bt_enable_8723b(dm)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[BT is enable!!!]\n"); + if (fat_tab->is_become_linked == true) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Set REG 948[9:6]=0x0\n"); + if (dm->support_ic_type == ODM_RTL8723B) + odm_set_bb_reg(dm, 0x948, BIT(9) | BIT(8) | BIT(7) | BIT(6), 0x0); + + fat_tab->is_become_linked = false; } } else { - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { - + if (dm->ant_div_type == S0S1_SW_ANTDIV) { #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_PEEK); + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); #endif - } else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_hw_ant_div(p_dm_odm); + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(dm); } } #endif /*8723D*/ #if (RTL8723D_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - - odm_hw_ant_div(p_dm_odm); + else if (dm->support_ic_type == ODM_RTL8723D) { + odm_hw_ant_div(dm); /**/ } #endif /* 2 [--8821A---] */ #if (RTL8821A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8821) { + else if (dm->support_ic_type == ODM_RTL8821) { #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { - - if (pdm_sat_table->fix_beam_pattern_en != 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", pdm_sat_table->fix_beam_pattern_codeword)); + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { + if (sat_tab->fix_beam_pattern_en != 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", sat_tab->fix_beam_pattern_codeword); /*return;*/ } else { - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] ant_div_type = HL_SW_SMART_ANT_TYPE1\n"));*/ - odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); + /*PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] ant_div_type = HL_SW_SMART_ANT_TYPE1\n");*/ + odm_fast_ant_training_hl_smart_antenna_type1(dm); } } else #endif { - - if (!p_dm_odm->is_bt_enabled) { /*BT disabled*/ - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { - p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n")); - /*odm_set_bb_reg(p_dm_odm, 0x8D4, BIT24, 1); */ - if (p_dm_fat_table->is_become_linked == true) - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); + #ifdef ODM_CONFIG_BT_COEXIST + if (!dm->bt_info_table.is_bt_enabled) { /*BT disabled*/ + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, " [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n"); + /*odm_set_bb_reg(dm, 0x8D4, BIT24, 1); */ + if (fat_tab->is_become_linked == true) + odm_ant_div_on_off(dm, ANTDIV_ON); } } else { /*BT enabled*/ - if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) { - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n")); - /*odm_set_bb_reg(p_dm_odm, 0x8D4, BIT24, 0);*/ - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, " [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n"); + /*odm_set_bb_reg(dm, 0x8D4, BIT24, 0);*/ + odm_ant_div_on_off(dm, ANTDIV_OFF); } } + #endif - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { - -#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_PEEK); -#endif - } else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_hw_ant_div(p_dm_odm); + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); + #endif + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(dm); } } #endif /* 2 [--8821C---] */ #if (RTL8821C_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8821C) - odm_hw_ant_div(p_dm_odm); + else if (dm->support_ic_type == ODM_RTL8821C) { + if (!dm->is_bt_continuous_turn) { + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "is_bt_continuous_turn = ((%d)) ==> SW AntDiv\n", dm->is_bt_continuous_turn); + + } else { + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "is_bt_continuous_turn = ((%d)) ==> HW AntDiv\n", dm->is_bt_continuous_turn); + odm_ant_div_on_off(dm, ANTDIV_ON); + } + + if (dm->ant_div_type == S0S1_SW_ANTDIV) { +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); +#endif + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(dm); + } #endif /* 2 [--8881A---] */ #if (RTL8881A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8881A) - odm_hw_ant_div(p_dm_odm); + else if (dm->support_ic_type == ODM_RTL8881A) + odm_hw_ant_div(dm); #endif /* 2 [--8812A---] */ #if (RTL8812A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8812) - odm_hw_ant_div(p_dm_odm); + else if (dm->support_ic_type == ODM_RTL8812) + odm_hw_ant_div(dm); #endif #if (RTL8188F_SUPPORT == 1) /* [--8188F---]*/ - else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - + else if (dm->support_ic_type == ODM_RTL8188F) { #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_PEEK); + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); #endif } #endif /* [--8822B---]*/ #if (RTL8822B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + else if (dm->support_ic_type == ODM_RTL8822B) { #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE2) { - - if (pdm_sat_table->fix_beam_pattern_en != 0) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", pdm_sat_table->fix_beam_pattern_codeword)); + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) { + if (sat_tab->fix_beam_pattern_en != 0) + PHYDM_DBG(dm, DBG_ANT_DIV, " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", sat_tab->fix_beam_pattern_codeword); else - phydm_fast_ant_training_hl_smart_antenna_type2(p_dm_odm); + phydm_fast_ant_training_hl_smart_antenna_type2(dm); } #endif } @@ -5504,8 +3968,8 @@ odm_ant_div( void odm_antsel_statistics( - void *p_dm_void, - void *p_phy_info_void, + void *dm_void, + void *phy_info_void, u8 antsel_tr_mux, u32 mac_id, u32 utility, @@ -5514,398 +3978,259 @@ odm_antsel_statistics( ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void; if (method == RSSI_METHOD) { - if (is_cck_rate) { if (antsel_tr_mux == ANT1_2G) { - if (p_dm_fat_table->main_ant_sum_cck[mac_id] > 65435) /*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/ + if (fat_tab->main_ant_sum_cck[mac_id] > 65435) /*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/ return; - p_dm_fat_table->main_ant_sum_cck[mac_id] += (u16)utility; - p_dm_fat_table->main_ant_cnt_cck[mac_id]++; + fat_tab->main_ant_sum_cck[mac_id] += (u16)utility; + fat_tab->main_ant_cnt_cck[mac_id]++; } else { - if (p_dm_fat_table->aux_ant_sum_cck[mac_id] > 65435) + if (fat_tab->aux_ant_sum_cck[mac_id] > 65435) return; - p_dm_fat_table->aux_ant_sum_cck[mac_id] += (u16)utility; - p_dm_fat_table->aux_ant_cnt_cck[mac_id]++; + fat_tab->aux_ant_sum_cck[mac_id] += (u16)utility; + fat_tab->aux_ant_cnt_cck[mac_id]++; } } else { /*ofdm rate*/ if (antsel_tr_mux == ANT1_2G) { - if (p_dm_fat_table->main_ant_sum[mac_id] > 65435) + if (fat_tab->main_ant_sum[mac_id] > 65435) return; - p_dm_fat_table->main_ant_sum[mac_id] += (u16)utility; - p_dm_fat_table->main_ant_cnt[mac_id]++; + fat_tab->main_ant_sum[mac_id] += (u16)utility; + fat_tab->main_ant_cnt[mac_id]++; } else { - if (p_dm_fat_table->aux_ant_sum[mac_id] > 65435) + if (fat_tab->aux_ant_sum[mac_id] > 65435) return; - p_dm_fat_table->aux_ant_sum[mac_id] += (u16)utility; - p_dm_fat_table->aux_ant_cnt[mac_id]++; + fat_tab->aux_ant_sum[mac_id] += (u16)utility; + fat_tab->aux_ant_cnt[mac_id]++; } } } #ifdef ODM_EVM_ENHANCE_ANTDIV else if (method == EVM_METHOD) { - if (p_dm_odm->rate_ss == 1) { - + if (dm->rate_ss == 1) { if (antsel_tr_mux == ANT1_2G) { - p_dm_fat_table->main_ant_evm_sum[mac_id] += ((p_phy_info->rx_mimo_evm_dbm[0])<<5); - p_dm_fat_table->main_ant_evm_cnt[mac_id]++; + fat_tab->main_ant_evm_sum[mac_id] += ((phy_info->rx_mimo_evm_dbm[0])<<5); + fat_tab->main_ant_evm_cnt[mac_id]++; } else { - p_dm_fat_table->aux_ant_evm_sum[mac_id] += ((p_phy_info->rx_mimo_evm_dbm[0])<<5); - p_dm_fat_table->aux_ant_evm_cnt[mac_id]++; + fat_tab->aux_ant_evm_sum[mac_id] += ((phy_info->rx_mimo_evm_dbm[0])<<5); + fat_tab->aux_ant_evm_cnt[mac_id]++; } } else {/*>= 2SS*/ if (antsel_tr_mux == ANT1_2G) { - - p_dm_fat_table->main_ant_evm_2ss_sum[mac_id][0] += (p_phy_info->rx_mimo_evm_dbm[0]<<5); - p_dm_fat_table->main_ant_evm_2ss_sum[mac_id][1] += (p_phy_info->rx_mimo_evm_dbm[1]<<5); - p_dm_fat_table->main_ant_evm_2ss_cnt[mac_id]++; + fat_tab->main_ant_evm_2ss_sum[mac_id][0] += (phy_info->rx_mimo_evm_dbm[0]<<5); + fat_tab->main_ant_evm_2ss_sum[mac_id][1] += (phy_info->rx_mimo_evm_dbm[1]<<5); + fat_tab->main_ant_evm_2ss_cnt[mac_id]++; } else { - - p_dm_fat_table->aux_ant_evm_2ss_sum[mac_id][0] += (p_phy_info->rx_mimo_evm_dbm[0]<<5); - p_dm_fat_table->aux_ant_evm_2ss_sum[mac_id][1] += (p_phy_info->rx_mimo_evm_dbm[1]<<5); - p_dm_fat_table->aux_ant_evm_2ss_cnt[mac_id]++; + fat_tab->aux_ant_evm_2ss_sum[mac_id][0] += (phy_info->rx_mimo_evm_dbm[0]<<5); + fat_tab->aux_ant_evm_2ss_sum[mac_id][1] += (phy_info->rx_mimo_evm_dbm[1]<<5); + fat_tab->aux_ant_evm_2ss_cnt[mac_id]++; } } } else if (method == CRC32_METHOD) { - if (antsel_tr_mux == ANT1_2G) { - p_dm_fat_table->main_crc32_ok_cnt += utility; - p_dm_fat_table->main_crc32_fail_cnt++; + fat_tab->main_crc32_ok_cnt += utility; + fat_tab->main_crc32_fail_cnt++; } else { - p_dm_fat_table->aux_crc32_ok_cnt += utility; - p_dm_fat_table->aux_crc32_fail_cnt++; + fat_tab->aux_crc32_ok_cnt += utility; + fat_tab->aux_crc32_fail_cnt++; } } else if (method == TP_METHOD) { if (((utility <= ODM_RATEMCS15) && (utility >= ODM_RATEMCS0)) && - (p_dm_fat_table->fat_state_cnt <= p_dm_odm->antdiv_tp_period) + (fat_tab->fat_state_cnt <= dm->antdiv_tp_period) ) { - if (antsel_tr_mux == ANT1_2G) { - p_dm_fat_table->antdiv_tp_main += (phy_rate_table[utility])<<5; - p_dm_fat_table->antdiv_tp_main_cnt++; + fat_tab->antdiv_tp_main += (phy_rate_table[utility])<<5; + fat_tab->antdiv_tp_main_cnt++; } else { - p_dm_fat_table->antdiv_tp_aux += (phy_rate_table[utility])<<5; - p_dm_fat_table->antdiv_tp_aux_cnt++; + fat_tab->antdiv_tp_aux += (phy_rate_table[utility])<<5; + fat_tab->antdiv_tp_aux_cnt++; } } } #endif } -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 -void -phydm_process_rssi_for_hb_smtant_type2( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void, - u8 rssi_avg -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; - struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u8 train_pkt_number; - u32 beam_tmp; - u8 is_cck_rate; - u8 rx_power_ant0 = p_phy_info->rx_mimo_signal_strength[0]; - u8 rx_power_ant1 = p_phy_info->rx_mimo_signal_strength[1]; - u8 rx_evm_ant0 = p_phy_info->rx_mimo_evm_dbm[0]; - u8 rx_evm_ant1 = p_phy_info->rx_mimo_evm_dbm[1]; - u8 rate_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); - - is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? TRUE : FALSE; - - - /*[Beacon]*/ - if (p_pktinfo->is_packet_beacon) { - - pdm_sat_table->beacon_counter++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MatchBSSID_beacon_counter = ((%d))\n", pdm_sat_table->beacon_counter)); - - if (pdm_sat_table->beacon_counter >= pdm_sat_table->pre_beacon_counter + 2) { - - pdm_sat_table->update_beam_idx++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", - pdm_sat_table->pre_beacon_counter, pdm_sat_table->pkt_counter, pdm_sat_table->update_beam_idx)); - - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->pkt_counter = 0; - } - } - /*[data]*/ - else if (p_pktinfo->is_packet_to_self) { - - if (pdm_sat_table->pkt_skip_statistic_en == 0) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ID[%d] pkt_cnt=((%d)): Beam_set = ((%d)), RSSI{A,B,avg} = {%d, %d, %d}\n", - p_pktinfo->station_id, pdm_sat_table->pkt_counter, pdm_sat_table->fast_training_beam_num, rx_power_ant0, rx_power_ant1, rssi_avg)); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Rate_ss = ((%d)), EVM{A,B} = {%d, %d}, RX Rate =", rate_ss, rx_evm_ant0, rx_evm_ant1)); - phydm_print_rate(p_dm_odm, p_dm_odm->rx_rate, ODM_COMP_ANT_DIV); - - - if (pdm_sat_table->pkt_counter >= 1) /*packet skip count*/ - { - pdm_sat_table->beam_set_rssi_avg_sum[pdm_sat_table->fast_training_beam_num] += rssi_avg; - pdm_sat_table->statistic_pkt_cnt[pdm_sat_table->fast_training_beam_num]++; - - pdm_sat_table->beam_path_rssi_sum[pdm_sat_table->fast_training_beam_num][0] += rx_power_ant0; - pdm_sat_table->beam_path_rssi_sum[pdm_sat_table->fast_training_beam_num][1] += rx_power_ant1; - - if (rate_ss == 2) { - pdm_sat_table->beam_path_evm_2ss_sum[pdm_sat_table->fast_training_beam_num][0] += rx_evm_ant0; - pdm_sat_table->beam_path_evm_2ss_sum[pdm_sat_table->fast_training_beam_num][1] += rx_evm_ant1; - pdm_sat_table->beam_path_evm_2ss_cnt[pdm_sat_table->fast_training_beam_num]++; - } else { - pdm_sat_table->beam_path_evm_1ss_sum[pdm_sat_table->fast_training_beam_num] += rx_evm_ant0; - pdm_sat_table->beam_path_evm_1ss_cnt[pdm_sat_table->fast_training_beam_num]++; - } - } - - pdm_sat_table->pkt_counter++; - - train_pkt_number = pdm_sat_table->beam_set_train_cnt[pdm_sat_table->fast_training_beam_num]; - - if (pdm_sat_table->pkt_counter >= train_pkt_number) { - - pdm_sat_table->update_beam_idx++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), Update_new_beam = ((%d))\n", - pdm_sat_table->pre_beacon_counter, pdm_sat_table->update_beam_idx)); - - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->pkt_counter = 0; - } - } - } - - if (pdm_sat_table->update_beam_idx > 0) { - - pdm_sat_table->update_beam_idx = 0; - - if (pdm_sat_table->fast_training_beam_num >= ((u32)pdm_sat_table->total_beam_set_num - 1)) { - - p_dm_fat_table->fat_state = FAT_DECISION_STATE; - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_fast_ant_training_hl_smart_antenna_type2(p_dm_odm); /*go to make decision*/ - #else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_decision_workitem); - #endif - - - } else { - beam_tmp = pdm_sat_table->fast_training_beam_num; - pdm_sat_table->fast_training_beam_num++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - phydm_set_rfu_beam_pattern_type2(p_dm_odm); - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - } - } - -} -#endif - void odm_process_rssi_for_ant_div( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void + void *dm_void, + void *phy_info_void, + void *pkt_info_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; - struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; +#if (defined(CONFIG_HL_SMART_ANTENNA)) + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; u32 beam_tmp; u8 next_ant; u8 train_pkt_number; #endif - u8 is_cck_rate = FALSE; - u8 rx_power_ant0 = p_phy_info->rx_mimo_signal_strength[0]; - u8 rx_power_ant1 = p_phy_info->rx_mimo_signal_strength[1]; - u8 rx_evm_ant0 = p_phy_info->rx_mimo_signal_quality[0]; - u8 rx_evm_ant1 = p_phy_info->rx_mimo_signal_quality[1]; + u8 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0]; + u8 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1]; + u8 rx_evm_ant0 = phy_info->rx_mimo_signal_quality[0]; + u8 rx_evm_ant1 = phy_info->rx_mimo_signal_quality[1]; u8 rssi_avg; - is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? TRUE : FALSE; - - if ((p_dm_odm->support_ic_type & ODM_IC_2SS) && (!is_cck_rate)) { - + if ((dm->support_ic_type & ODM_IC_2SS) && (!pktinfo->is_cck_rate)) { if (rx_power_ant1 < 100) rssi_avg = (u8)odm_convert_to_db((odm_convert_to_linear(rx_power_ant0) + odm_convert_to_linear(rx_power_ant1))>>1); /*averaged PWDB*/ } else { - rx_power_ant0 = (u8)p_phy_info->rx_pwdb_all; + rx_power_ant0 = (u8)phy_info->rx_pwdb_all; rssi_avg = rx_power_ant0; } #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - if ((p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) { - /*for 8822B*/ - phydm_process_rssi_for_hb_smtant_type2(p_dm_odm, p_phy_info, p_pktinfo, rssi_avg); - } else + if ((dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (fat_tab->fat_state == FAT_TRAINING_STATE)) + phydm_process_rssi_for_hb_smtant_type2(dm, phy_info, pktinfo, rssi_avg); /*for 8822B*/ + else #endif #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 #ifdef CONFIG_FAT_PATCH - if ((p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) && (p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) { - + if ((dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) && (fat_tab->fat_state == FAT_TRAINING_STATE)) { /*[Beacon]*/ - if (p_pktinfo->is_packet_beacon) { - - pdm_sat_table->beacon_counter++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MatchBSSID_beacon_counter = ((%d))\n", pdm_sat_table->beacon_counter)); - - if (pdm_sat_table->beacon_counter >= pdm_sat_table->pre_beacon_counter + 2) { - - if (pdm_sat_table->ant_num > 1) { - next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - odm_update_rx_idle_ant(p_dm_odm, next_ant); + if (pktinfo->is_packet_beacon) { + sat_tab->beacon_counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, "MatchBSSID_beacon_counter = ((%d))\n", sat_tab->beacon_counter); + + if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) { + if (sat_tab->ant_num > 1) { + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + odm_update_rx_idle_ant(dm, next_ant); } - pdm_sat_table->update_beam_idx++; + sat_tab->update_beam_idx++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", - pdm_sat_table->pre_beacon_counter, pdm_sat_table->pkt_counter, pdm_sat_table->update_beam_idx)); + PHYDM_DBG(dm, DBG_ANT_DIV, "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", + sat_tab->pre_beacon_counter, sat_tab->pkt_counter, sat_tab->update_beam_idx); - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->pkt_counter = 0; + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->pkt_counter = 0; } } /*[data]*/ - else if (p_pktinfo->is_packet_to_self) { - - if (pdm_sat_table->pkt_skip_statistic_en == 0) { + else if (pktinfo->is_packet_to_self) { + if (sat_tab->pkt_skip_statistic_en == 0) { /* - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", - p_pktinfo->station_id, p_dm_fat_table->antsel_rx_keep_0, p_dm_fat_table->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, rx_power_ant0)); + PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0); */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n", - p_pktinfo->station_id, pdm_sat_table->pkt_counter, p_dm_fat_table->antsel_rx_keep_0, pdm_sat_table->fast_training_beam_num, rx_power_ant0)); + PHYDM_DBG(dm, DBG_ANT_DIV, "ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n", + pktinfo->station_id, sat_tab->pkt_counter, fat_tab->antsel_rx_keep_0, sat_tab->fast_training_beam_num, rx_power_ant0); - pdm_sat_table->pkt_rssi_sum[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += rx_power_ant0; - pdm_sat_table->pkt_rssi_cnt[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; - pdm_sat_table->pkt_counter++; + sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0; + sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++; + sat_tab->pkt_counter++; #if 1 - train_pkt_number = pdm_sat_table->beam_train_cnt[p_dm_fat_table->rx_idle_ant - 1][pdm_sat_table->fast_training_beam_num]; + train_pkt_number = sat_tab->beam_train_cnt[fat_tab->rx_idle_ant - 1][sat_tab->fast_training_beam_num]; #else - train_pkt_number = pdm_sat_table->per_beam_training_pkt_num; + train_pkt_number = sat_tab->per_beam_training_pkt_num; #endif /*Swich Antenna erery N pkts*/ - if (pdm_sat_table->pkt_counter == train_pkt_number) { - - if (pdm_sat_table->ant_num > 1) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number)); - next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - odm_update_rx_idle_ant(p_dm_odm, next_ant); + if (sat_tab->pkt_counter == train_pkt_number) { + if (sat_tab->ant_num > 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, "packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number); + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + odm_update_rx_idle_ant(dm, next_ant); } - pdm_sat_table->update_beam_idx++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n", - pdm_sat_table->pre_beacon_counter, pdm_sat_table->update_beam_idx)); + sat_tab->update_beam_idx++; + PHYDM_DBG(dm, DBG_ANT_DIV, "pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n", + sat_tab->pre_beacon_counter, sat_tab->update_beam_idx); - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->pkt_counter = 0; + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->pkt_counter = 0; } } } - /*Swich Beam after switch "pdm_sat_table->ant_num" antennas*/ - if (pdm_sat_table->update_beam_idx == pdm_sat_table->ant_num) { - - pdm_sat_table->update_beam_idx = 0; - pdm_sat_table->pkt_counter = 0; - beam_tmp = pdm_sat_table->fast_training_beam_num; - - if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant - 1)) { + /*Swich Beam after switch "sat_tab->ant_num" antennas*/ + if (sat_tab->update_beam_idx == sat_tab->ant_num) { + sat_tab->update_beam_idx = 0; + sat_tab->pkt_counter = 0; + beam_tmp = sat_tab->fast_training_beam_num; - p_dm_fat_table->fat_state = FAT_DECISION_STATE; + if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) { + fat_tab->fat_state = FAT_DECISION_STATE; #if DEV_BUS_TYPE == RT_PCI_INTERFACE - odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); + odm_fast_ant_training_hl_smart_antenna_type1(dm); #else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_decision_workitem); + odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem); #endif } else { - pdm_sat_table->fast_training_beam_num++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - phydm_set_all_ant_same_beam_num(p_dm_odm); + sat_tab->fast_training_beam_num++; + PHYDM_DBG(dm, DBG_ANT_DIV, "Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num); + phydm_set_all_ant_same_beam_num(dm); - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; + fat_tab->fat_state = FAT_TRAINING_STATE; } } } #else - if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { - if ((p_dm_odm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) && - (p_pktinfo->is_packet_to_self) && - (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { + if ((dm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) && + (pktinfo->is_packet_to_self) && + (fat_tab->fat_state == FAT_TRAINING_STATE) ) { - - if (pdm_sat_table->pkt_skip_statistic_en == 0) { + if (sat_tab->pkt_skip_statistic_en == 0) { /* - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", - p_pktinfo->station_id, p_dm_fat_table->antsel_rx_keep_0, p_dm_fat_table->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, rx_power_ant0)); + PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0); */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", - p_pktinfo->station_id, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->is_packet_to_self, pdm_sat_table->fast_training_beam_num, rx_power_ant0)); + PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]: antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pktinfo->station_id, fat_tab->antsel_rx_keep_0, pktinfo->is_packet_to_self, sat_tab->fast_training_beam_num, rx_power_ant0); - pdm_sat_table->pkt_rssi_sum[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += rx_power_ant0; - pdm_sat_table->pkt_rssi_cnt[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; - pdm_sat_table->pkt_counter++; + sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0; + sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++; + sat_tab->pkt_counter++; /*swich beam every N pkt*/ - if ((pdm_sat_table->pkt_counter) >= (pdm_sat_table->per_beam_training_pkt_num)) { - - pdm_sat_table->pkt_counter = 0; - beam_tmp = pdm_sat_table->fast_training_beam_num; + if ((sat_tab->pkt_counter) >= (sat_tab->per_beam_training_pkt_num)) { + sat_tab->pkt_counter = 0; + beam_tmp = sat_tab->fast_training_beam_num; - if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant - 1)) { - - p_dm_fat_table->fat_state = FAT_DECISION_STATE; + if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) { + fat_tab->fat_state = FAT_DECISION_STATE; #if DEV_BUS_TYPE == RT_PCI_INTERFACE - odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); + odm_fast_ant_training_hl_smart_antenna_type1(dm); #else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_decision_workitem); + odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem); #endif } else { - pdm_sat_table->fast_training_beam_num++; - phydm_set_all_ant_same_beam_num(p_dm_odm); + sat_tab->fast_training_beam_num++; + phydm_set_all_ant_same_beam_num(dm); - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); + fat_tab->fat_state = FAT_TRAINING_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num); } } } @@ -5914,32 +4239,30 @@ odm_process_rssi_for_ant_div( #endif else #endif - if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) { - if ((p_dm_odm->support_ic_type & ODM_SMART_ANT_SUPPORT) && (p_pktinfo->is_packet_to_self) && (p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) { /* (p_pktinfo->is_packet_match_bssid && (!p_pktinfo->is_packet_beacon)) */ + if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) { + if ((dm->support_ic_type & ODM_SMART_ANT_SUPPORT) && (pktinfo->is_packet_to_self) && (fat_tab->fat_state == FAT_TRAINING_STATE)) { /* (pktinfo->is_packet_match_bssid && (!pktinfo->is_packet_beacon)) */ u8 antsel_tr_mux; - antsel_tr_mux = (p_dm_fat_table->antsel_rx_keep_2 << 2) | (p_dm_fat_table->antsel_rx_keep_1 << 1) | p_dm_fat_table->antsel_rx_keep_0; - p_dm_fat_table->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0; - p_dm_fat_table->ant_rssi_cnt[antsel_tr_mux]++; + antsel_tr_mux = (fat_tab->antsel_rx_keep_2 << 2) | (fat_tab->antsel_rx_keep_1 << 1) | fat_tab->antsel_rx_keep_0; + fat_tab->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0; + fat_tab->ant_rssi_cnt[antsel_tr_mux]++; } } else { /* ant_div_type != CG_TRX_SMART_ANTDIV */ - if ((p_dm_odm->support_ic_type & ODM_ANTDIV_SUPPORT) && (p_pktinfo->is_packet_to_self || p_dm_fat_table->use_ctrl_frame_antdiv)) { - - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { + if ((dm->support_ic_type & ODM_ANTDIV_SUPPORT) && (pktinfo->is_packet_to_self || fat_tab->use_ctrl_frame_antdiv)) { + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + if (pktinfo->is_cck_rate || (dm->support_ic_type == ODM_RTL8188F)) + fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; - if (is_cck_rate || (p_dm_odm->support_ic_type == ODM_RTL8188F)) - p_dm_fat_table->antsel_rx_keep_0 = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; - - odm_antsel_statistics(p_dm_odm, p_phy_info, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_power_ant0, RSSI_METHOD, is_cck_rate); + odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_power_ant0, RSSI_METHOD, pktinfo->is_cck_rate); } else { - odm_antsel_statistics(p_dm_odm, p_phy_info, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_power_ant0, RSSI_METHOD, is_cck_rate); + odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_power_ant0, RSSI_METHOD, pktinfo->is_cck_rate); #ifdef ODM_EVM_ENHANCE_ANTDIV - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - if (!is_cck_rate) { - odm_antsel_statistics(p_dm_odm, p_phy_info, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_evm_ant0, EVM_METHOD, is_cck_rate); - odm_antsel_statistics(p_dm_odm, p_phy_info, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_evm_ant0, TP_METHOD, is_cck_rate); + if (dm->support_ic_type == ODM_RTL8192E) { + if (!pktinfo->is_cck_rate) { + odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_evm_ant0, EVM_METHOD, pktinfo->is_cck_rate); + odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_evm_ant0, TP_METHOD, pktinfo->is_cck_rate); } } @@ -5947,54 +4270,54 @@ odm_process_rssi_for_ant_div( } } } - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("is_cck_rate=%d, PWDB_ALL=%d\n",is_cck_rate, p_phy_info->rx_pwdb_all)); */ - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",p_dm_fat_table->antsel_rx_keep_2, p_dm_fat_table->antsel_rx_keep_1, p_dm_fat_table->antsel_rx_keep_0)); */ + /* PHYDM_DBG(dm,DBG_ANT_DIV,"is_cck_rate=%d, pwdb_all=%d\n",pktinfo->is_cck_rate, phy_info->rx_pwdb_all); */ + /* PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=3'b%d%d%d\n",fat_tab->antsel_rx_keep_2, fat_tab->antsel_rx_keep_1, fat_tab->antsel_rx_keep_0); */ } #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) void odm_set_tx_ant_by_tx_info( - void *p_dm_void, - u8 *p_desc, + void *dm_void, + u8 *desc, u8 mac_id ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) + if (!(dm->support_ability & ODM_BB_ANT_DIV)) return; - if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) return; - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (dm->support_ic_type == ODM_RTL8723B) { #if (RTL8723B_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_8723B(p_desc, p_dm_fat_table->antsel_a[mac_id]); - /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", - mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/ + SET_TX_DESC_ANTSEL_A_8723B(desc, fat_tab->antsel_a[mac_id]); + /*PHYDM_DBG(dm,DBG_ANT_DIV, "[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/ #endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8821) { + } else if (dm->support_ic_type == ODM_RTL8821) { #if (RTL8821A_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_8812(p_desc, p_dm_fat_table->antsel_a[mac_id]); - /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", - mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/ + SET_TX_DESC_ANTSEL_A_8812(desc, fat_tab->antsel_a[mac_id]); + /*PHYDM_DBG(dm,DBG_ANT_DIV, "[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/ #endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + } else if (dm->support_ic_type == ODM_RTL8188E) { #if (RTL8188E_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_88E(p_desc, p_dm_fat_table->antsel_a[mac_id]); - SET_TX_DESC_ANTSEL_B_88E(p_desc, p_dm_fat_table->antsel_b[mac_id]); - SET_TX_DESC_ANTSEL_C_88E(p_desc, p_dm_fat_table->antsel_c[mac_id]); - /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", - mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/ + SET_TX_DESC_ANTSEL_A_88E(desc, fat_tab->antsel_a[mac_id]); + SET_TX_DESC_ANTSEL_B_88E(desc, fat_tab->antsel_b[mac_id]); + SET_TX_DESC_ANTSEL_C_88E(desc, fat_tab->antsel_c[mac_id]); + /*PHYDM_DBG(dm,DBG_ANT_DIV, "[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/ #endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + } else if (dm->support_ic_type == ODM_RTL8821C) { #if (RTL8821C_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_8821C(p_desc, p_dm_fat_table->antsel_a[mac_id]); - /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", - mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/ + SET_TX_DESC_ANTSEL_A_8821C(desc, fat_tab->antsel_a[mac_id]); + /*PHYDM_DBG(dm,DBG_ANT_DIV, "[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/ #endif } } @@ -6007,35 +4330,35 @@ odm_set_tx_ant_by_tx_info( unsigned short aid ) { - struct PHY_DM_STRUCT *p_dm_odm = GET_PDM_ODM(priv);/*&(priv->pshare->_dmODM);*/ - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &(p_dm_odm->dm_fat_table); + struct dm_struct *dm = GET_PDM_ODM(priv);/*&(priv->pshare->_dmODM);*/ + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) + if (!(dm->support_ability & ODM_BB_ANT_DIV)) return; - if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) return; - if (p_dm_odm->support_ic_type == ODM_RTL8881A) { + if (dm->support_ic_type == ODM_RTL8881A) { /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__); */ pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16))); - pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_a[aid] << 16); - } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + } else if (dm->support_ic_type == ODM_RTL8192E) { /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */ pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16))); - pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_a[aid] << 16); - } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + } else if (dm->support_ic_type == ODM_RTL8188E) { /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/ pdesc->Dword2 &= set_desc(~BIT(24)); pdesc->Dword2 &= set_desc(~BIT(25)); pdesc->Dword7 &= set_desc(~BIT(29)); - pdesc->Dword2 |= set_desc(p_dm_fat_table->antsel_a[aid] << 24); - pdesc->Dword2 |= set_desc(p_dm_fat_table->antsel_b[aid] << 25); - pdesc->Dword7 |= set_desc(p_dm_fat_table->antsel_c[aid] << 29); + pdesc->Dword2 |= set_desc(fat_tab->antsel_a[aid] << 24); + pdesc->Dword2 |= set_desc(fat_tab->antsel_b[aid] << 25); + pdesc->Dword7 |= set_desc(fat_tab->antsel_c[aid] << 29); - } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { + } else if (dm->support_ic_type == ODM_RTL8812) { /*[path-A]*/ /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/ @@ -6043,9 +4366,9 @@ odm_set_tx_ant_by_tx_info( pdesc->Dword6 &= set_desc(~BIT(17)); pdesc->Dword6 &= set_desc(~BIT(18)); - pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_a[aid] << 16); - pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_b[aid] << 17); - pdesc->Dword6 |= set_desc(p_dm_fat_table->antsel_c[aid] << 18); + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + pdesc->Dword6 |= set_desc(fat_tab->antsel_b[aid] << 17); + pdesc->Dword6 |= set_desc(fat_tab->antsel_c[aid] << 18); } } @@ -6059,20 +4382,20 @@ odm_set_tx_ant_by_tx_info_hal( u16 aid ) { - struct PHY_DM_STRUCT *p_dm_odm = GET_PDM_ODM(priv);/*&(priv->pshare->_dmODM);*/ - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &(p_dm_odm->dm_fat_table); + struct dm_struct *dm = GET_PDM_ODM(priv);/*&(priv->pshare->_dmODM);*/ + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data; - if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) + if (!(dm->support_ability & ODM_BB_ANT_DIV)) return; - if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) return; - if (p_dm_odm->support_ic_type & (ODM_RTL8881A |ODM_RTL8192E |ODM_RTL8814A)) { + if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8814A)) { /*panic_printk("[%s] [%d] ******odm_set_tx_ant_by_tx_info_hal******\n",__FUNCTION__,__LINE__);*/ pdescdata->ant_sel = 1; - pdescdata->ant_sel_a = p_dm_fat_table->antsel_a[aid]; + pdescdata->ant_sel_a = fat_tab->antsel_a[aid]; } } #endif /*#ifdef CONFIG_WLAN_HAL*/ @@ -6082,182 +4405,185 @@ odm_set_tx_ant_by_tx_info_hal( void odm_ant_div_config( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("WIN Config Antenna Diversity\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "WIN Config Antenna Diversity\n"); /* - if(p_dm_odm->support_ic_type==ODM_RTL8723B) + if(dm->support_ic_type==ODM_RTL8723B) { - if((!p_dm_odm->dm_swat_table.ANTA_ON || !p_dm_odm->dm_swat_table.ANTB_ON)) - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + if((!dm->dm_swat_table.ANTA_ON || !dm->dm_swat_table.ANTB_ON)) + dm->support_ability &= ~(ODM_BB_ANT_DIV); } */ - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - - p_dm_odm->ant_div_type = S0S1_TRX_HW_ANTDIV; + if (dm->support_ic_type == ODM_RTL8723D) { + dm->ant_div_type = S0S1_TRX_HW_ANTDIV; /**/ } #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CE Config Antenna Diversity\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "CE Config Antenna Diversity\n"); - if (p_dm_odm->support_ic_type == ODM_RTL8723B) - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; + if (dm->support_ic_type == ODM_RTL8723B) + dm->ant_div_type = S0S1_SW_ANTDIV; #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AP Config Antenna Diversity\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "AP Config Antenna Diversity\n"); /* 2 [ NOT_SUPPORT_ANTDIV ] */ #if (defined(CONFIG_NOT_SUPPORT_ANTDIV)) - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n")); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n"); /* 2 [ 2G&5G_SUPPORT_ANTDIV ] */ #elif (defined(CONFIG_2G5G_SUPPORT_ANTDIV)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n")); - p_dm_fat_table->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n"); + fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G); - if (p_dm_odm->support_ic_type & ODM_ANTDIV_SUPPORT) - p_dm_odm->support_ability |= ODM_BB_ANT_DIV; - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + if (dm->support_ic_type & ODM_ANTDIV_SUPPORT) + dm->support_ability |= ODM_BB_ANT_DIV; + if (*dm->band_type == ODM_BAND_5G) { #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY)) - p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n")); + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) - p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n")); + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CG_SMART_ANTDIV\n")); + dm->ant_div_type = CG_TRX_SMART_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n"); #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n")); + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n"); #endif - } else if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { + } else if (*dm->band_type == ODM_BAND_2_4G) { #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY)) - p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n")); + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) - p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n")); + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n")); + dm->ant_div_type = CG_TRX_SMART_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n"); #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n")); + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n"); #endif } /* 2 [ 5G_SUPPORT_ANTDIV ] */ #elif (defined(CONFIG_5G_SUPPORT_ANTDIV)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"); panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"); - p_dm_fat_table->ant_div_2g_5g = (ODM_ANTDIV_5G); - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { - if (p_dm_odm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC) - p_dm_odm->support_ability |= ODM_BB_ANT_DIV; + fat_tab->ant_div_2g_5g = (ODM_ANTDIV_5G); + if (*dm->band_type == ODM_BAND_5G) { + if (dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC) + dm->support_ability |= ODM_BB_ANT_DIV; #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY)) - p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n")); + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY)) - p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; + dm->ant_div_type = CG_TRX_HW_ANTDIV; panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CG_SMART_ANTDIV\n")); + dm->ant_div_type = CG_TRX_SMART_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n"); #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n")); + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n"); #endif - } else if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Not Support 2G ant_div_type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + } else if (*dm->band_type == ODM_BAND_2_4G) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 2G ant_div_type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); } /* 2 [ 2G_SUPPORT_ANTDIV ] */ #elif (defined(CONFIG_2G_SUPPORT_ANTDIV)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n")); - p_dm_fat_table->ant_div_2g_5g = (ODM_ANTDIV_2G); - if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { - if (p_dm_odm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC) - p_dm_odm->support_ability |= ODM_BB_ANT_DIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n"); + fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G); + if (*dm->band_type == ODM_BAND_2_4G) { + if (dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC) + dm->support_ability |= ODM_BB_ANT_DIV; #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY)) - p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n")); + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY)) - p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n")); + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n")); + dm->ant_div_type = CG_TRX_SMART_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n"); #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n")); + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n"); #endif - } else if (*p_dm_odm->p_band_type == ODM_BAND_5G) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Not Support 5G ant_div_type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + } else if (*dm->band_type == ODM_BAND_5G) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 5G ant_div_type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); } #endif #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n", ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0))); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv Config Info] be_fix_tx_ant = ((%d))\n", p_dm_odm->dm_fat_table.b_fix_tx_ant)); + PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n", ((dm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0)); + PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv Config Info] be_fix_tx_ant = ((%d))\n", dm->dm_fat_table.b_fix_tx_ant); } void odm_ant_div_timers( - void *p_dm_void, + void *dm_void, u8 state ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (state == INIT_ANTDIV_TIMMER) { #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_initialize_timer(p_dm_odm, &(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_timer), - (void *)odm_sw_antdiv_callback, NULL, "phydm_sw_antenna_switch_timer"); + odm_initialize_timer(dm, + &dm->dm_swat_table.phydm_sw_antenna_switch_timer, + (void *)odm_sw_antdiv_callback, NULL, + "phydm_sw_antenna_switch_timer"); #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - odm_initialize_timer(p_dm_odm, &p_dm_odm->fast_ant_training_timer, + odm_initialize_timer(dm, &dm->fast_ant_training_timer, (void *)odm_fast_ant_training_callback, NULL, "fast_ant_training_timer"); #endif #ifdef ODM_EVM_ENHANCE_ANTDIV - odm_initialize_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer, + odm_initialize_timer(dm, &dm->evm_fast_ant_training_timer, (void *)odm_evm_fast_ant_training_callback, NULL, "evm_fast_ant_training_timer"); #endif } else if (state == CANCEL_ANTDIV_TIMMER) { #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_cancel_timer(p_dm_odm, &(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_timer)); + odm_cancel_timer(dm, + &dm->dm_swat_table.phydm_sw_antenna_switch_timer); #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - odm_cancel_timer(p_dm_odm, &p_dm_odm->fast_ant_training_timer); + odm_cancel_timer(dm, &dm->fast_ant_training_timer); #endif #ifdef ODM_EVM_ENHANCE_ANTDIV - odm_cancel_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer); + odm_cancel_timer(dm, &dm->evm_fast_ant_training_timer); #endif } else if (state == RELEASE_ANTDIV_TIMMER) { #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_release_timer(p_dm_odm, &(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_timer)); + odm_release_timer(dm, + &dm->dm_swat_table.phydm_sw_antenna_switch_timer); #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - odm_release_timer(p_dm_odm, &p_dm_odm->fast_ant_training_timer); + odm_release_timer(dm, &dm->fast_ant_training_timer); #endif #ifdef ODM_EVM_ENHANCE_ANTDIV - odm_release_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer); + odm_release_timer(dm, &dm->evm_fast_ant_training_timer); #endif } @@ -6265,49 +4591,66 @@ odm_ant_div_timers( void phydm_antdiv_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - /*struct _FAST_ANTENNA_TRAINNING_* p_dm_fat_table = &p_dm_odm->dm_fat_table;*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + /*struct phydm_fat_struct* fat_tab = &dm->dm_fat_table;*/ u32 used = *_used; u32 out_len = *_out_len; if (dm_value[0] == 1) { /*fixed or auto antenna*/ if (dm_value[1] == 0) { - p_dm_odm->antdiv_select = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv: Auto\n")); + dm->ant_type = ODM_AUTO_ANT; + PDM_SNPF(out_len, used, output + used, + out_len - used, "AntDiv: Auto\n"); } else if (dm_value[1] == 1) { - p_dm_odm->antdiv_select = 1; - PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv: Fix MAin\n")); + dm->ant_type = ODM_FIX_MAIN_ANT; + PDM_SNPF(out_len, used, output + used, + out_len - used, "AntDiv: Fix Main\n"); } else if (dm_value[1] == 2) { - p_dm_odm->antdiv_select = 2; - PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv: Fix Aux\n")); + dm->ant_type = ODM_FIX_AUX_ANT; + PDM_SNPF(out_len, used, output + used, + out_len - used, "AntDiv: Fix Aux\n"); + } + + if (dm->ant_type != ODM_AUTO_ANT) { + odm_stop_antenna_switch_dm(dm); + if (dm->ant_type == ODM_FIX_MAIN_ANT) + odm_update_rx_idle_ant(dm, MAIN_ANT); + else if (dm->ant_type == ODM_FIX_AUX_ANT) + odm_update_rx_idle_ant(dm, AUX_ANT); + } else { + phydm_enable_antenna_diversity(dm); } + dm->pre_ant_type = dm->ant_type; } else if (dm_value[0] == 2) { /*dynamic period for AntDiv*/ - p_dm_odm->antdiv_period = (u8)dm_value[1]; - PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv_period = ((%d))\n", p_dm_odm->antdiv_period)); + dm->antdiv_period = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv_period = ((%d))\n", dm->antdiv_period); } + *_used = used; + *_out_len = out_len; } #endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/ void odm_ant_div_reset( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { + if (dm->ant_div_type == S0S1_SW_ANTDIV) { #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_s0s1_sw_ant_div_reset(p_dm_odm); + odm_s0s1_sw_ant_div_reset(dm); #endif } @@ -6315,32 +4658,45 @@ odm_ant_div_reset( void odm_antenna_diversity_init( - void *p_dm_void + void *dm_void ) { #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if 0 - if (*(p_dm_odm->p_mp_mode) == true) + if (*(dm->mp_mode) == true) return; #endif - odm_ant_div_config(p_dm_odm); - odm_ant_div_init(p_dm_odm); + odm_ant_div_config(dm); + odm_ant_div_init(dm); #endif } void odm_antenna_diversity( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (*(p_dm_odm->p_mp_mode) == true) +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (*dm->mp_mode == true) return; -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - odm_ant_div(p_dm_odm); + if (!(dm->support_ability & ODM_BB_ANT_DIV)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Return!!!] Not Support Antenna Diversity Function\n"); + return; + } + + if (dm->pause_ability & ODM_BB_ANT_DIV) { + + PHYDM_DBG(dm, DBG_ANT_DIV, "Return: Pause AntDIv in LV=%d\n", dm->pause_lv_table.lv_antdiv); + return; + } + + odm_ant_div(dm); #endif } diff --git a/hal/phydm/phydm_antdiv.h b/hal/phydm/phydm_antdiv.h index 175b59d..0918afc 100644 --- a/hal/phydm/phydm_antdiv.h +++ b/hal/phydm/phydm_antdiv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __PHYDMANTDIV_H__ @@ -28,7 +38,8 @@ /*#define ANTDIV_VERSION "3.6"*/ /*2015.11.16 Stanley */ /*#define ANTDIV_VERSION "3.7"*/ /*2015.11.20 Dino Add SmartAnt FAT Patch */ /*#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */ -#define ANTDIV_VERSION "3.9" /*2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */ +/*#define ANTDIV_VERSION "3.9" 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */ +#define ANTDIV_VERSION "4.0" /*2017.05.25 Mark, Add SW antenna diversity for 8821c because HW transient issue */ /* 1 ============================================================ * 1 Definition @@ -135,7 +146,7 @@ * 1 ============================================================ */ -struct _sw_antenna_switch_ { +struct sw_antenna_switch { u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/ u8 try_flag; s32 pre_rssi; @@ -145,7 +156,7 @@ struct _sw_antenna_switch_ { u8 reset_idx; u8 train_time; u8 train_time_flag; /*base on RSSI difference between two antennas*/ - struct timer_list phydm_sw_antenna_switch_timer; + struct phydm_timer_list phydm_sw_antenna_switch_timer; u32 pkt_cnt_sw_ant_div_by_ctrl_frame; boolean is_sw_ant_div_by_ctrl_frame; @@ -204,84 +215,8 @@ struct _BF_DIV_COEX_ { #endif #endif -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) -struct _SMART_ANTENNA_TRAINNING_ { - u32 latch_time; - boolean pkt_skip_statistic_en; - u32 fix_beam_pattern_en; - u32 fix_training_num_en; - u32 fix_beam_pattern_codeword; - u32 update_beam_codeword; - u32 ant_num; /*number of "used" smart beam antenna*/ - u32 ant_num_total;/*number of "total" smart beam antenna*/ - u32 first_train_ant; /*decide witch antenna to train first*/ - - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - u32 pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];/*rssi of each path with a certain beam pattern*/ - u8 beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; - u8 beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; - u32 rfu_codeword_table[4]; /*2G beam truth table*/ - u32 rfu_codeword_table_5g[4]; /*5G beam truth table*/ - u32 beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/ - u32 rx_idle_beam[SUPPORT_RF_PATH_NUM]; - u32 pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM]; - u32 pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM]; - #endif - - u32 fast_training_beam_num;/*current training beam_set index*/ - u32 pre_fast_training_beam_num;/*pre training beam_set index*/ - u32 rfu_codeword_total_bit_num; /* total bit number of RFU protocol*/ - u32 rfu_each_ant_bit_num; /* bit number of RFU protocol for each ant*/ - u8 per_beam_training_pkt_num; - u8 decision_holding_period; - - - u32 pre_codeword; - boolean force_update_beam_en; - u32 beacon_counter; - u32 pre_beacon_counter; - u8 pkt_counter; /*packet number that each beam-set should be colected in training state*/ - u8 update_beam_idx; /*the index announce that the beam can be updated*/ - u8 rfu_protocol_type; - u16 rfu_protocol_delay_time; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_WORK_ITEM hl_smart_antenna_workitem; - RT_WORK_ITEM hl_smart_antenna_decision_workitem; - #endif - - - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - u8 beam_set_avg_rssi_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; /*avg pre_rssi of each beam set*/ - u8 beam_set_train_val_diff[SUPPORT_BEAM_SET_PATTERN_NUM]; /*rssi of a beam pattern set, ex: a set = {ant1_beam=1, ant2_beam=3}*/ - u8 beam_set_train_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*training pkt num of each beam set*/ - u32 beam_set_rssi_avg_sum[SUPPORT_BEAM_SET_PATTERN_NUM]; /*RSSI_sum of avg(pathA,pathB) for each beam-set)*/ - u32 beam_path_rssi_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*RSSI_sum of each path for each beam-set)*/ - - u8 beam_set_avg_evm_2ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; - u32 beam_path_evm_2ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*2SS evm_sum of each path for each beam-set)*/ - u32 beam_path_evm_2ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; - - u8 beam_set_avg_evm_1ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; - u32 beam_path_evm_1ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM];/*1SS evm_sum of each path for each beam-set)*/ - u32 beam_path_evm_1ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; - - u32 statistic_pkt_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*statistic_pkt_cnt for SmtAnt make decision*/ - - u8 total_beam_set_num; /*number of beam set can be switched*/ - u8 total_beam_set_num_2g;/*number of beam set can be switched in 2G*/ - u8 total_beam_set_num_5g;/*number of beam set can be switched in 5G*/ - - u8 rfu_codeword_table_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*2G beam truth table*/ - u8 rfu_codeword_table_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*5G beam truth table*/ - u8 rx_idle_beam_set_idx; /*the filanl decsion result*/ - #endif - -}; -#endif - -struct _FAST_ANTENNA_TRAINNING_ { +struct phydm_fat_struct { u8 bssid[6]; u8 antsel_rx_keep_0; u8 antsel_rx_keep_1; @@ -305,6 +240,7 @@ struct _FAST_ANTENNA_TRAINNING_ { u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; u8 rx_idle_ant; + u8 rvrt_val; u8 ant_div_on_off; boolean is_become_linked; u32 min_max_rssi; @@ -325,7 +261,7 @@ struct _FAST_ANTENNA_TRAINNING_ { u32 main_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; u32 aux_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; - boolean EVM_method_enable; + boolean evm_method_enable; u8 target_ant_evm; u8 target_ant_crc32; u8 target_ant_tp; @@ -363,6 +299,7 @@ struct _FAST_ANTENNA_TRAINNING_ { boolean fix_ant_bfee; boolean enable_ctrl_frame_antdiv; boolean use_ctrl_frame_antdiv; + boolean *is_no_csi_feedback; u8 hw_antsw_occur; u8 *p_force_tx_ant_by_desc; u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's outer parameter later*/ @@ -377,7 +314,7 @@ struct _FAST_ANTENNA_TRAINNING_ { -enum fat_state_e /*Fast antenna training*/ +enum fat_state /*Fast antenna training*/ { FAT_BEFORE_LINK_STATE = 0, FAT_PREPARE_STATE = 1, @@ -385,7 +322,7 @@ enum fat_state_e /*Fast antenna training*/ FAT_DECISION_STATE = 3 }; -enum ant_div_type_e { +enum ant_div_type { NO_ANTDIV = 0xFF, CG_TRX_HW_ANTDIV = 0x01, CGCS_RX_HW_ANTDIV = 0x02, @@ -406,17 +343,17 @@ enum ant_div_type_e { void odm_stop_antenna_switch_dm( - void *p_dm_void + void *dm_void ); void phydm_enable_antenna_diversity( - void *p_dm_void + void *dm_void ); void odm_set_ant_config( - void *p_dm_void, + void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */ ); @@ -424,27 +361,46 @@ odm_set_ant_config( #define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link void odm_sw_ant_div_rest_after_link( - void *p_dm_void + void *dm_void +); + +void +odm_ant_div_on_off( + void *dm_void, + u8 swch +); + +void +odm_tx_by_tx_desc_or_reg( + void *dm_void, + u8 swch ); #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) void phydm_antdiv_reset_statistic( - void *p_dm_void, + void *dm_void, u32 macid ); void odm_update_rx_idle_ant( - void *p_dm_void, + void *dm_void, u8 ant ); +void +phydm_set_antdiv_val( + void *dm_void, + u32 *val_buf, + u8 val_len +); + #if (RTL8723B_SUPPORT == 1) void odm_update_rx_idle_ant_8723b( - void *p_dm_void, + void *dm_void, u8 ant, u32 default_ant, u32 optional_ant @@ -454,7 +410,7 @@ odm_update_rx_idle_ant_8723b( #if (RTL8188F_SUPPORT == 1) void phydm_update_rx_idle_antenna_8188F( - void *p_dm_void, + void *dm_void, u32 default_ant ); #endif @@ -463,13 +419,13 @@ phydm_update_rx_idle_antenna_8188F( void phydm_set_tx_ant_pwr_8723d( - void *p_dm_void, + void *dm_void, u8 ant ); void odm_update_rx_idle_ant_8723d( - void *p_dm_void, + void *dm_void, u8 ant, u32 default_ant, u32 optional_ant @@ -482,12 +438,12 @@ odm_update_rx_idle_ant_8723d( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void odm_sw_antdiv_callback( - struct timer_list *p_timer + struct phydm_timer_list *timer ); void odm_sw_antdiv_workitem_callback( - void *p_context + void *context ); @@ -495,7 +451,7 @@ odm_sw_antdiv_workitem_callback( void odm_sw_antdiv_workitem_callback( - void *p_context + void *context ); void @@ -507,145 +463,74 @@ odm_sw_antdiv_callback( void odm_s0s1_sw_ant_div_by_ctrl_frame( - void *p_dm_void, + void *dm_void, u8 step ); void odm_antsel_statistics_of_ctrl_frame( - void *p_dm_void, + void *dm_void, u8 antsel_tr_mux, u32 rx_pwdb_all ); void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void + void *dm_void, + void *phy_info_void, + void *pkt_info_void ); #endif #ifdef ODM_EVM_ENHANCE_ANTDIV -VOID +void phydm_evm_sw_antdiv_init( - void *p_dm_void + void *dm_void ); void odm_evm_fast_ant_training_callback( - void *p_dm_void + void *dm_void ); #endif void odm_hw_ant_div( - void *p_dm_void + void *dm_void ); #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) void odm_fast_ant_training( - void *p_dm_void + void *dm_void ); void odm_fast_ant_training_callback( - void *p_dm_void + void *dm_void ); void odm_fast_ant_training_work_item_callback( - void *p_dm_void -); -#endif - - -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -phydm_beam_switch_workitem_callback( - void *p_context + void *dm_void ); - -void -phydm_beam_decision_workitem_callback( - void *p_context -); - #endif - - -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - -void -phydm_update_beam_pattern_type2( - void *p_dm_void, - u32 codeword, - u32 codeword_length -); - -void -phydm_set_rfu_beam_pattern_type2( - void *p_dm_void -); - -void -phydm_hl_smart_ant_debug_type2( - void *p_dm_void, - char input[][16], - u32 *_used, - char *output, - u32 *_out_len, - u32 input_num -); - -#elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) - -void -phydm_update_beam_pattern( - void *p_dm_void, - u32 codeword, - u32 codeword_length -); - -void -phydm_set_all_ant_same_beam_num( - void *p_dm_void -); - -void -phydm_hl_smart_ant_debug( - void *p_dm_void, - char input[][16], - u32 *_used, - char *output, - u32 *_out_len, - u32 input_num -); - -#endif - - -#endif/*#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))*/ - void odm_ant_div_init( - void *p_dm_void + void *dm_void ); void odm_ant_div( - void *p_dm_void + void *dm_void ); void odm_antsel_statistics( - void *p_dm_void, - void *p_phy_info_void, + void *dm_void, + void *phy_info_void, u8 antsel_tr_mux, u32 mac_id, u32 utility, @@ -655,9 +540,9 @@ odm_antsel_statistics( void odm_process_rssi_for_ant_div( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void + void *dm_void, + void *phy_info_void, + void *pkt_info_void ); @@ -665,8 +550,8 @@ odm_process_rssi_for_ant_div( #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) void odm_set_tx_ant_by_tx_info( - void *p_dm_void, - u8 *p_desc, + void *dm_void, + u8 *desc, u8 mac_id ); @@ -694,18 +579,18 @@ odm_set_tx_ant_by_tx_info_hal( void odm_ant_div_config( - void *p_dm_void + void *dm_void ); void odm_ant_div_timers( - void *p_dm_void, + void *dm_void, u8 state ); void phydm_antdiv_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, char *output, @@ -716,17 +601,17 @@ phydm_antdiv_debug( void odm_ant_div_reset( - void *p_dm_void + void *dm_void ); void odm_antenna_diversity_init( - void *p_dm_void + void *dm_void ); void odm_antenna_diversity( - void *p_dm_void + void *dm_void ); #endif /*#ifndef __ODMANTDIV_H__*/ diff --git a/hal/phydm/phydm_beamforming.c b/hal/phydm/phydm_beamforming.c index 0587e3b..4b84d1b 100644 --- a/hal/phydm/phydm_beamforming.c +++ b/hal/phydm/phydm_beamforming.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,10 +8,21 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ + #include "mp_precomp.h" #include "phydm_precomp.h" @@ -23,118 +34,157 @@ #if (BEAMFORMING_SUPPORT == 1) +void +phydm_get_txbf_device_num( + void *dm_void, + u8 macid +) +{ +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*For BDC*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct bf_cmn_info *bf = NULL; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + u8 act_as_bfer = 0; + u8 act_as_bfee = 0; + + if (is_sta_active(sta)) { + bf = &(sta->bf_info); + } else { + PHYDM_DBG(dm, DBG_TXBF, "[Warning] %s invalid sta_info\n", __func__); + return; + } + + if (sta->support_wireless_set & WIRELESS_VHT) { + if (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE) + act_as_bfer = 1; + + if (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMER_ENABLE) + act_as_bfee = 1; + + } else if (sta->support_wireless_set & WIRELESS_HT) { + if (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE) + act_as_bfer = 1; + + if (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMER_ENABLE) + act_as_bfee = 1; + + } + + if (act_as_bfer)) { /* Our Device act as BFer */ + dm_bdc_table->w_bfee_client[macid] = true; + dm_bdc_table->num_txbfee_client++; + } else + dm_bdc_table->w_bfee_client[macid] = false; + + if (act_as_bfee)) { /* Our Device act as BFee */ + dm_bdc_table->w_bfer_client[macid] = true; + dm_bdc_table->num_txbfer_client++; + } else + dm_bdc_table->w_bfer_client[macid] = false; + +#endif +#endif +} + struct _RT_BEAMFORM_STAINFO * phydm_sta_info_init( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u16 sta_idx ) { - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORM_STAINFO *p_entry = &(p_beam_info->beamform_sta_info); - struct sta_info *p_sta = p_dm_odm->p_odm_sta_info[sta_idx]; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORM_STAINFO *entry = &beam_info->beamform_sta_info; + struct sta_info *sta = dm->odm_sta_info[sta_idx]; + struct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx]; + //void *adapter = dm->adapter; + PADAPTER adapter = (PADAPTER)dm->adapter; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMGNT_INFO p_MgntInfo = &adapter->MgntInfo; + PMGNT_INFO p_MgntInfo = &((adapter)->MgntInfo); PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo); PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo); - u1Byte iotpeer = 0; - - iotpeer = p_MgntInfo->IOTPeer; - odm_move_memory(p_dm_odm, p_entry->my_mac_addr, adapter->CurrentAddress, 6); - - p_entry->ht_beamform_cap = p_ht_info->HtBeamformCap; - p_entry->vht_beamform_cap = p_vht_info->VhtBeamformCap; - - /*IBSS, AP mode*/ - if (sta_idx != 0) { - p_entry->aid = p_sta->AID; - p_entry->ra = p_sta->MacAddr; - p_entry->mac_id = p_sta->AssociatedMacId; - p_entry->wireless_mode = p_sta->WirelessMode; - p_entry->bw = p_sta->BandWidth; - p_entry->cur_beamform = p_sta->HTInfo.HtCurBeamform; - } else {/*client mode*/ - p_entry->aid = p_MgntInfo->mAId; - p_entry->ra = p_MgntInfo->Bssid; - p_entry->mac_id = p_MgntInfo->mMacId; - p_entry->wireless_mode = p_MgntInfo->dot11CurrentWirelessMode; - p_entry->bw = p_MgntInfo->dot11CurrentChannelBandWidth; - p_entry->cur_beamform = p_ht_info->HtCurBeamform; - } +#endif - if ((p_entry->wireless_mode & WIRELESS_MODE_AC_5G) || (p_entry->wireless_mode & WIRELESS_MODE_AC_24G)) { - if (sta_idx != 0) - p_entry->cur_beamform_vht = p_sta->VHTInfo.VhtCurBeamform; - else - p_entry->cur_beamform_vht = p_vht_info->VhtCurBeamform; + if (!is_sta_active(cmn_sta)) { + + PHYDM_DBG(dm, DBG_TXBF, "%s => sta_info(mac_id:%d) failed\n", __func__, sta_idx); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_warn_on(1); + #endif + + return entry; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("p_sta->wireless_mode = 0x%x, staidx = %d\n", p_sta->WirelessMode, sta_idx)); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + odm_move_memory(dm, (PVOID)(entry->my_mac_addr), (PVOID)(adapter->CurrentAddress), 6); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + odm_move_memory(dm, entry->my_mac_addr, adapter_mac_addr(sta->padapter), 6); +#endif - if (!IS_STA_VALID(p_sta)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s => sta_info(mac_id:%d) failed\n", __func__, sta_idx)); - rtw_warn_on(1); - return p_entry; + entry->aid = cmn_sta->aid; + entry->ra = cmn_sta->mac_addr; + entry->mac_id = cmn_sta->mac_id; + entry->bw = cmn_sta->bw_mode; + entry->cur_beamform = cmn_sta->bf_info.ht_beamform_cap; + entry->ht_beamform_cap = cmn_sta->bf_info.ht_beamform_cap; + +#if ODM_IC_11AC_SERIES_SUPPORT + if (cmn_sta->support_wireless_set & WIRELESS_VHT) { + entry->cur_beamform_vht = cmn_sta->bf_info.vht_beamform_cap; + entry->vht_beamform_cap = cmn_sta->bf_info.vht_beamform_cap; } +#endif - odm_move_memory(p_dm_odm, p_entry->my_mac_addr, adapter_mac_addr(p_sta->padapter), 6); - #ifdef CONFIG_80211N_HT - p_entry->ht_beamform_cap = p_sta->htpriv.beamform_cap; - #endif - p_entry->aid = p_sta->aid; - p_entry->ra = p_sta->hwaddr; - p_entry->mac_id = p_sta->mac_id; - p_entry->wireless_mode = p_sta->wireless_mode; - p_entry->bw = p_sta->bw_mode; - #ifdef CONFIG_80211N_HT - p_entry->cur_beamform = p_sta->htpriv.beamform_cap; - #endif -#if ODM_IC_11AC_SERIES_SUPPORT - if ((p_entry->wireless_mode & WIRELESS_MODE_AC_5G) || (p_entry->wireless_mode & WIRELESS_MODE_AC_24G)) { - p_entry->cur_beamform_vht = p_sta->vhtpriv.beamform_cap; - p_entry->vht_beamform_cap = p_sta->vhtpriv.beamform_cap; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*To Be Removed */ + entry->ht_beamform_cap = p_ht_info->HtBeamformCap; /*To Be Removed*/ + entry->vht_beamform_cap = p_vht_info->VhtBeamformCap; /*To Be Removed*/ + + if (sta_idx == 0) { /*client mode*/ + #if ODM_IC_11AC_SERIES_SUPPORT + if (cmn_sta->support_wireless_set & WIRELESS_VHT) + entry->cur_beamform_vht = p_vht_info->VhtCurBeamform; + #endif } #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("p_sta->wireless_mode = 0x%x, staidx = %d\n", p_sta->wireless_mode, sta_idx)); -#endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("p_entry->cur_beamform = 0x%x, p_entry->cur_beamform_vht = 0x%x\n", p_entry->cur_beamform, p_entry->cur_beamform_vht)); - return p_entry; + + PHYDM_DBG(dm, DBG_TXBF, "wireless_set = 0x%x, staidx = %d\n", cmn_sta->support_wireless_set, sta_idx); + PHYDM_DBG(dm, DBG_TXBF, "entry->cur_beamform = 0x%x, entry->cur_beamform_vht = 0x%x\n", entry->cur_beamform, entry->cur_beamform_vht); + return entry; } void phydm_sta_info_update( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u16 sta_idx, - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry + struct _RT_BEAMFORMEE_ENTRY *beamform_entry ) { - struct sta_info *p_sta = p_dm_odm->p_odm_sta_info[sta_idx]; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; - if (!IS_STA_VALID(p_sta)) + if (!is_sta_active(sta)) return; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - p_sta->txbf_paid = p_beamform_entry->p_aid; - p_sta->txbf_gid = p_beamform_entry->g_id; -#endif + sta->bf_info.p_aid = beamform_entry->p_aid; + sta->bf_info.g_id = beamform_entry->g_id; } struct _RT_BEAMFORMEE_ENTRY * phydm_beamforming_get_bfee_entry_by_addr( - void *p_dm_void, + void *dm_void, u8 *RA, u8 *idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (p_beam_info->beamformee_entry[i].is_used && (eq_mac_addr(RA, p_beam_info->beamformee_entry[i].mac_addr))) { + if (beam_info->beamformee_entry[i].is_used && (eq_mac_addr(RA, beam_info->beamformee_entry[i].mac_addr))) { *idx = i; - return &(p_beam_info->beamformee_entry[i]); + return &beam_info->beamformee_entry[i]; } } @@ -143,19 +193,19 @@ phydm_beamforming_get_bfee_entry_by_addr( struct _RT_BEAMFORMER_ENTRY * phydm_beamforming_get_bfer_entry_by_addr( - void *p_dm_void, + void *dm_void, u8 *TA, u8 *idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { - if (p_beam_info->beamformer_entry[i].is_used && (eq_mac_addr(TA, p_beam_info->beamformer_entry[i].mac_addr))) { + if (beam_info->beamformer_entry[i].is_used && (eq_mac_addr(TA, beam_info->beamformer_entry[i].mac_addr))) { *idx = i; - return &(p_beam_info->beamformer_entry[i]); + return &beam_info->beamformer_entry[i]; } } @@ -165,19 +215,19 @@ phydm_beamforming_get_bfer_entry_by_addr( struct _RT_BEAMFORMEE_ENTRY * phydm_beamforming_get_entry_by_mac_id( - void *p_dm_void, + void *dm_void, u8 mac_id, u8 *idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (p_beam_info->beamformee_entry[i].is_used && (mac_id == p_beam_info->beamformee_entry[i].mac_id)) { + if (beam_info->beamformee_entry[i].is_used && (mac_id == beam_info->beamformee_entry[i].mac_id)) { *idx = i; - return &(p_beam_info->beamformee_entry[i]); + return &beam_info->beamformee_entry[i]; } } @@ -187,18 +237,18 @@ phydm_beamforming_get_entry_by_mac_id( enum beamforming_cap phydm_beamforming_get_entry_beam_cap_by_mac_id( - void *p_dm_void, + void *dm_void, u8 mac_id ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; enum beamforming_cap beamform_entry_cap = BEAMFORMING_CAP_NONE; for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (p_beam_info->beamformee_entry[i].is_used && (mac_id == p_beam_info->beamformee_entry[i].mac_id)) { - beamform_entry_cap = p_beam_info->beamformee_entry[i].beamform_entry_cap; + if (beam_info->beamformee_entry[i].is_used && (mac_id == beam_info->beamformee_entry[i].mac_id)) { + beamform_entry_cap = beam_info->beamformee_entry[i].beamform_entry_cap; i = BEAMFORMEE_ENTRY_NUM; } } @@ -209,18 +259,18 @@ phydm_beamforming_get_entry_beam_cap_by_mac_id( struct _RT_BEAMFORMEE_ENTRY * phydm_beamforming_get_free_bfee_entry( - void *p_dm_void, + void *dm_void, u8 *idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (p_beam_info->beamformee_entry[i].is_used == false) { + if (beam_info->beamformee_entry[i].is_used == false) { *idx = i; - return &(p_beam_info->beamformee_entry[i]); + return &beam_info->beamformee_entry[i]; } } return NULL; @@ -228,20 +278,20 @@ phydm_beamforming_get_free_bfee_entry( struct _RT_BEAMFORMER_ENTRY * phydm_beamforming_get_free_bfer_entry( - void *p_dm_void, + void *dm_void, u8 *idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s ===>\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s ===>\n", __func__); for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { - if (p_beam_info->beamformer_entry[i].is_used == false) { + if (beam_info->beamformer_entry[i].is_used == false) { *idx = i; - return &(p_beam_info->beamformer_entry[i]); + return &beam_info->beamformer_entry[i]; } } return NULL; @@ -257,17 +307,17 @@ phydm_beamforming_get_free_bfer_entry( */ u8 phydm_beamforming_get_first_mu_bfee_entry_idx( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 idx = 0xFF; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; boolean is_found = false; for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].is_mu_sta) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d!\n", __func__, idx)); + if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].is_mu_sta) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] idx=%d!\n", __func__, idx); is_found = true; break; } @@ -283,72 +333,72 @@ phydm_beamforming_get_first_mu_bfee_entry_idx( /*Add SU BFee and MU BFee*/ struct _RT_BEAMFORMEE_ENTRY * beamforming_add_bfee_entry( - void *p_dm_void, - struct _RT_BEAMFORM_STAINFO *p_sta, + void *dm_void, + struct _RT_BEAMFORM_STAINFO *sta, enum beamforming_cap beamform_cap, u8 num_of_sounding_dim, u8 comp_steering_num_of_bfer, u8 *idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMEE_ENTRY *p_entry = phydm_beamforming_get_free_bfee_entry(p_dm_odm, idx); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMEE_ENTRY *entry = phydm_beamforming_get_free_bfee_entry(dm, idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - if (p_entry != NULL) { - p_entry->is_used = true; - p_entry->aid = p_sta->aid; - p_entry->mac_id = p_sta->mac_id; - p_entry->sound_bw = p_sta->bw; - odm_move_memory(p_dm_odm, p_entry->my_mac_addr, p_sta->my_mac_addr, 6); + if (entry != NULL) { + entry->is_used = true; + entry->aid = sta->aid; + entry->mac_id = sta->mac_id; + entry->sound_bw = sta->bw; + odm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6); - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ap)) { + if (phydm_acting_determine(dm, phydm_acting_as_ap)) { /*BSSID[44:47] xor BSSID[40:43]*/ - u16 bssid = ((p_sta->my_mac_addr[5] & 0xf0) >> 4) ^ (p_sta->my_mac_addr[5] & 0xf); + u16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf); /*(dec(A) + dec(B)*32) mod 512*/ - p_entry->p_aid = (p_sta->aid + bssid * 32) & 0x1ff; - p_entry->g_id = 63; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to STA=%d\n", __func__, p_entry->p_aid)); - } else if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) { + entry->p_aid = (sta->aid + bssid * 32) & 0x1ff; + entry->g_id = 63; + PHYDM_DBG(dm, DBG_TXBF, "%s: BFee P_AID addressed to STA=%d\n", __func__, entry->p_aid); + } else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) { /*ad hoc mode*/ - p_entry->p_aid = 0; - p_entry->g_id = 63; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID as IBSS=%d\n", __func__, p_entry->p_aid)); + entry->p_aid = 0; + entry->g_id = 63; + PHYDM_DBG(dm, DBG_TXBF, "%s: BFee P_AID as IBSS=%d\n", __func__, entry->p_aid); } else { /*client mode*/ - p_entry->p_aid = p_sta->ra[5]; + entry->p_aid = sta->ra[5]; /*BSSID[39:47]*/ - p_entry->p_aid = (p_entry->p_aid << 1) | (p_sta->ra[4] >> 7); - p_entry->g_id = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to AP=0x%X\n", __func__, p_entry->p_aid)); + entry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7); + entry->g_id = 0; + PHYDM_DBG(dm, DBG_TXBF, "%s: BFee P_AID addressed to AP=0x%X\n", __func__, entry->p_aid); } - cp_mac_addr(p_entry->mac_addr, p_sta->ra); - p_entry->is_txbf = false; - p_entry->is_sound = false; - p_entry->sound_period = 400; - p_entry->beamform_entry_cap = beamform_cap; - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + cp_mac_addr(entry->mac_addr, sta->ra); + entry->is_txbf = false; + entry->is_sound = false; + entry->sound_period = 400; + entry->beamform_entry_cap = beamform_cap; + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - /* p_entry->log_seq = 0xff; Move to beamforming_add_bfer_entry*/ - /* p_entry->log_retry_cnt = 0; Move to beamforming_add_bfer_entry*/ - /* p_entry->LogSuccessCnt = 0; Move to beamforming_add_bfer_entry*/ + /* entry->log_seq = 0xff; Move to beamforming_add_bfer_entry*/ + /* entry->log_retry_cnt = 0; Move to beamforming_add_bfer_entry*/ + /* entry->LogSuccessCnt = 0; Move to beamforming_add_bfer_entry*/ - p_entry->log_status_fail_cnt = 0; + entry->log_status_fail_cnt = 0; - p_entry->num_of_sounding_dim = num_of_sounding_dim; - p_entry->comp_steering_num_of_bfer = comp_steering_num_of_bfer; + entry->num_of_sounding_dim = num_of_sounding_dim; + entry->comp_steering_num_of_bfer = comp_steering_num_of_bfer; if (beamform_cap & BEAMFORMER_CAP_VHT_MU) { - p_dm_odm->beamforming_info.beamformee_mu_cnt += 1; - p_entry->is_mu_sta = true; - p_dm_odm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(p_dm_odm); + dm->beamforming_info.beamformee_mu_cnt += 1; + entry->is_mu_sta = true; + dm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm); } else if (beamform_cap & (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) { - p_dm_odm->beamforming_info.beamformee_su_cnt += 1; - p_entry->is_mu_sta = false; + dm->beamforming_info.beamformee_su_cnt += 1; + entry->is_mu_sta = false; } - return p_entry; + return entry; } else return NULL; } @@ -356,60 +406,60 @@ beamforming_add_bfee_entry( /*Add SU BFee and MU BFer*/ struct _RT_BEAMFORMER_ENTRY * beamforming_add_bfer_entry( - void *p_dm_void, - struct _RT_BEAMFORM_STAINFO *p_sta, + void *dm_void, + struct _RT_BEAMFORM_STAINFO *sta, enum beamforming_cap beamform_cap, u8 num_of_sounding_dim, u8 *idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMER_ENTRY *p_entry = phydm_beamforming_get_free_bfer_entry(p_dm_odm, idx); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMER_ENTRY *entry = phydm_beamforming_get_free_bfer_entry(dm, idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - if (p_entry != NULL) { - p_entry->is_used = true; - odm_move_memory(p_dm_odm, p_entry->my_mac_addr, p_sta->my_mac_addr, 6); - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ap)) { + if (entry != NULL) { + entry->is_used = true; + odm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6); + if (phydm_acting_determine(dm, phydm_acting_as_ap)) { /*BSSID[44:47] xor BSSID[40:43]*/ - u16 bssid = ((p_sta->my_mac_addr[5] & 0xf0) >> 4) ^ (p_sta->my_mac_addr[5] & 0xf); + u16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf); - p_entry->p_aid = (p_sta->aid + bssid * 32) & 0x1ff; - p_entry->g_id = 63; + entry->p_aid = (sta->aid + bssid * 32) & 0x1ff; + entry->g_id = 63; /*(dec(A) + dec(B)*32) mod 512*/ - } else if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) { - p_entry->p_aid = 0; - p_entry->g_id = 63; + } else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) { + entry->p_aid = 0; + entry->g_id = 63; } else { - p_entry->p_aid = p_sta->ra[5]; + entry->p_aid = sta->ra[5]; /*BSSID[39:47]*/ - p_entry->p_aid = (p_entry->p_aid << 1) | (p_sta->ra[4] >> 7); - p_entry->g_id = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: P_AID addressed to AP=0x%X\n", __func__, p_entry->p_aid)); + entry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7); + entry->g_id = 0; + PHYDM_DBG(dm, DBG_TXBF, "%s: P_AID addressed to AP=0x%X\n", __func__, entry->p_aid); } - cp_mac_addr(p_entry->mac_addr, p_sta->ra); - p_entry->beamform_entry_cap = beamform_cap; + cp_mac_addr(entry->mac_addr, sta->ra); + entry->beamform_entry_cap = beamform_cap; - p_entry->pre_log_seq = 0; /*Modified by Jeffery @2015-04-13*/ - p_entry->log_seq = 0; /*Modified by Jeffery @2014-10-29*/ - p_entry->log_retry_cnt = 0; /*Modified by Jeffery @2014-10-29*/ - p_entry->log_success = 0; /*log_success is NOT needed to be accumulated, so LogSuccessCnt->log_success, 2015-04-13, Jeffery*/ - p_entry->clock_reset_times = 0; /*Modified by Jeffery @2015-04-13*/ + entry->pre_log_seq = 0; /*Modified by Jeffery @2015-04-13*/ + entry->log_seq = 0; /*Modified by Jeffery @2014-10-29*/ + entry->log_retry_cnt = 0; /*Modified by Jeffery @2014-10-29*/ + entry->log_success = 0; /*log_success is NOT needed to be accumulated, so LogSuccessCnt->log_success, 2015-04-13, Jeffery*/ + entry->clock_reset_times = 0; /*Modified by Jeffery @2015-04-13*/ - p_entry->num_of_sounding_dim = num_of_sounding_dim; + entry->num_of_sounding_dim = num_of_sounding_dim; if (beamform_cap & BEAMFORMEE_CAP_VHT_MU) { - p_dm_odm->beamforming_info.beamformer_mu_cnt += 1; - p_entry->is_mu_ap = true; - p_entry->aid = p_sta->aid; + dm->beamforming_info.beamformer_mu_cnt += 1; + entry->is_mu_ap = true; + entry->aid = sta->aid; } else if (beamform_cap & (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) { - p_dm_odm->beamforming_info.beamformer_su_cnt += 1; - p_entry->is_mu_ap = false; + dm->beamforming_info.beamformer_su_cnt += 1; + entry->is_mu_ap = false; } - return p_entry; + return entry; } else return NULL; } @@ -417,32 +467,32 @@ beamforming_add_bfer_entry( #if 0 boolean beamforming_remove_entry( - struct _ADAPTER *adapter, + void *adapter, u8 *RA, u8 *idx ) { - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; - struct _RT_BEAMFORMER_ENTRY *p_bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(p_dm_odm, RA, idx); - struct _RT_BEAMFORMEE_ENTRY *p_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, idx); + struct _RT_BEAMFORMER_ENTRY *bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, RA, idx); + struct _RT_BEAMFORMEE_ENTRY *entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, idx); boolean ret = false; RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s Start!\n", __func__)); - RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, p_bfer_entry=0x%x\n", __func__, p_bfer_entry)); - RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, p_entry=0x%x\n", __func__, p_entry)); - - if (p_entry != NULL) { - p_entry->is_used = false; - p_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; - /*p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/ - p_entry->is_beamforming_in_progress = false; + RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, bfer_entry=0x%x\n", __func__, bfer_entry)); + RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, entry=0x%x\n", __func__, entry)); + + if (entry != NULL) { + entry->is_used = false; + entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + /*entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/ + entry->is_beamforming_in_progress = false; ret = true; } - if (p_bfer_entry != NULL) { - p_bfer_entry->is_used = false; - p_bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + if (bfer_entry != NULL) { + bfer_entry->is_used = false; + bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; ret = true; } return ret; @@ -453,28 +503,28 @@ beamforming_remove_entry( /* Used for beamforming_start_v1 */ void phydm_beamforming_ndpa_rate( - void *p_dm_void, - CHANNEL_WIDTH BW, + void *dm_void, + enum channel_width BW, u8 rate ) { u16 ndpa_rate = rate; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); if (ndpa_rate == 0) { - if (p_dm_odm->rssi_min > 30) /* link RSSI > 30% */ + if (dm->rssi_min > 30) /* link RSSI > 30% */ ndpa_rate = ODM_RATE24M; else ndpa_rate = ODM_RATE6M; } if (ndpa_rate < ODM_RATEMCS0) - BW = (CHANNEL_WIDTH)ODM_BW20M; + BW = (enum channel_width)CHANNEL_WIDTH_20; ndpa_rate = (ndpa_rate << 8) | BW; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate); } @@ -482,18 +532,18 @@ phydm_beamforming_ndpa_rate( /* Used for beamforming_start_sw and beamforming_start_fw */ void phydm_beamforming_dym_ndpa_rate( - void *p_dm_void + void *dm_void ) { u16 ndpa_rate = ODM_RATE6M, BW; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; ndpa_rate = ODM_RATE6M; - BW = ODM_BW20M; + BW = CHANNEL_WIDTH_20; ndpa_rate = ndpa_rate << 8 | BW; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, NDPA rate = 0x%X\n", __func__, ndpa_rate)); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate); + PHYDM_DBG(dm, DBG_TXBF, "%s End, NDPA rate = 0x%X\n", __func__, ndpa_rate); } /* @@ -503,57 +553,58 @@ phydm_beamforming_dym_ndpa_rate( */ void beamforming_dym_period( - void *p_dm_void, + void *dm_void, u8 status ) { u8 idx; boolean is_change_period = false; u16 sound_period_sw, sound_period_fw; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; - struct _RT_BEAMFORMEE_ENTRY *p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); + struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx]; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); /* 3 TODO per-client throughput caculation. */ - if ((*(p_dm_odm->p_current_tx_tp) + *(p_dm_odm->p_current_rx_tp) > 2) && ((p_entry->log_status_fail_cnt <= 20) || status)) { + if ((*dm->current_tx_tp + *dm->current_rx_tp > 2) && ((entry->log_status_fail_cnt <= 20) || status)) { sound_period_sw = 40; /* 40ms */ sound_period_fw = 40; /* From H2C cmd, unit = 10ms */ } else { sound_period_sw = 4000;/* 4s */ sound_period_fw = 400; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]sound_period_sw=%d, sound_period_fw=%d\n", __func__, sound_period_sw, sound_period_fw)); + PHYDM_DBG(dm, DBG_TXBF, "[%s]sound_period_sw=%d, sound_period_fw=%d\n", __func__, sound_period_sw, sound_period_fw); for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_beamform_entry = p_beam_info->beamformee_entry + idx; + beamform_entry = beam_info->beamformee_entry + idx; - if (p_beamform_entry->default_csi_cnt > 20) { + if (beamform_entry->default_csi_cnt > 20) { /*Modified by David*/ sound_period_sw = 4000; sound_period_fw = 400; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] period = %d\n", __func__, sound_period_sw)); - if (p_beamform_entry->beamform_entry_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { - if (p_sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_FW_HT_TIMER) { - if (p_beamform_entry->sound_period != sound_period_fw) { - p_beamform_entry->sound_period = sound_period_fw; - is_change_period = true; /*Only FW sounding need to send H2C packet to change sound period. */ - } - } else if (p_beamform_entry->sound_period != sound_period_sw) - p_beamform_entry->sound_period = sound_period_sw; - } + PHYDM_DBG(dm, DBG_TXBF, "[%s] period = %d\n", __func__, sound_period_sw); + if ((beamform_entry->beamform_entry_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) == 0) + continue; + + if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER) { + if (beamform_entry->sound_period != sound_period_fw) { + beamform_entry->sound_period = sound_period_fw; + is_change_period = true; /*Only FW sounding need to send H2C packet to change sound period. */ + } + } else if (beamform_entry->sound_period != sound_period_sw) + beamform_entry->sound_period = sound_period_sw; } if (is_change_period) - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); } @@ -561,19 +612,19 @@ beamforming_dym_period( boolean beamforming_send_ht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, - CHANNEL_WIDTH BW, + enum channel_width BW, u8 q_idx ) { boolean ret = true; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (q_idx == BEACON_QUEUE) - ret = send_fw_ht_ndpa_packet(p_dm_odm, RA, BW); + ret = send_fw_ht_ndpa_packet(dm, RA, BW); else - ret = send_sw_ht_ndpa_packet(p_dm_odm, RA, BW); + ret = send_sw_ht_ndpa_packet(dm, RA, BW); return ret; } @@ -582,37 +633,37 @@ beamforming_send_ht_ndpa_packet( boolean beamforming_send_vht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, u16 AID, - CHANNEL_WIDTH BW, + enum channel_width BW, u8 q_idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; boolean ret = true; - hal_com_txbf_set(p_dm_odm, TXBF_SET_GET_TX_RATE, NULL); + hal_com_txbf_set(dm, TXBF_SET_GET_TX_RATE, NULL); - if ((p_beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7) && (p_beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9) && (p_beam_info->snding3ss == false)) - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: 3SS VHT 789 don't sounding\n", __func__)); + if ((beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7) && (beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9) && (!beam_info->snding3ss)) + PHYDM_DBG(dm, DBG_TXBF, "@%s: 3SS VHT 789 don't sounding\n", __func__); else { if (q_idx == BEACON_QUEUE) /* Send to reserved page => FW NDPA */ - ret = send_fw_vht_ndpa_packet(p_dm_odm, RA, AID, BW); + ret = send_fw_vht_ndpa_packet(dm, RA, AID, BW); else { #ifdef SUPPORT_MU_BF #if (SUPPORT_MU_BF == 1) - p_beam_info->is_mu_sounding = true; - ret = send_sw_vht_mu_ndpa_packet(p_dm_odm, BW); + beam_info->is_mu_sounding = true; + ret = send_sw_vht_mu_ndpa_packet(dm, BW); #else - p_beam_info->is_mu_sounding = false; - ret = send_sw_vht_ndpa_packet(p_dm_odm, RA, AID, BW); + beam_info->is_mu_sounding = false; + ret = send_sw_vht_ndpa_packet(dm, RA, AID, BW); #endif #else - p_beam_info->is_mu_sounding = false; - ret = send_sw_vht_ndpa_packet(p_dm_odm, RA, AID, BW); + beam_info->is_mu_sounding = false; + ret = send_sw_vht_ndpa_packet(dm, RA, AID, BW); #endif } } @@ -622,47 +673,48 @@ beamforming_send_vht_ndpa_packet( enum beamforming_notify_state phydm_beamfomring_is_sounding( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info, + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info, u8 *idx ) { enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE; - struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - /*if(( Beamforming_GetBeamCap(p_beam_info) & BEAMFORMER_CAP) == 0)*/ + /*if(( Beamforming_GetBeamCap(beam_info) & BEAMFORMER_CAP) == 0)*/ /*is_sounding = BEAMFORMING_NOTIFY_RESET;*/ - if (beam_oid_info.sound_oid_mode == sounding_stop_all_timer) + if (beam_oid_info.sound_oid_mode == sounding_stop_all_timer) { is_sounding = BEAMFORMING_NOTIFY_RESET; - else { - u8 i; + goto out; + } for (i = 0 ; i < BEAMFORMEE_ENTRY_NUM ; i++) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: BFee Entry %d is_used=%d, is_sound=%d\n", __func__, i, p_beam_info->beamformee_entry[i].is_used, p_beam_info->beamformee_entry[i].is_sound)); - if (p_beam_info->beamformee_entry[i].is_used && (!p_beam_info->beamformee_entry[i].is_sound)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Add BFee entry %d\n", __func__, i)); + PHYDM_DBG(dm, DBG_TXBF, "@%s: BFee Entry %d is_used=%d, is_sound=%d\n", __func__, i, beam_info->beamformee_entry[i].is_used, beam_info->beamformee_entry[i].is_sound); + if (beam_info->beamformee_entry[i].is_used && (!beam_info->beamformee_entry[i].is_sound)) { + PHYDM_DBG(dm, DBG_TXBF, "%s: Add BFee entry %d\n", __func__, i); *idx = i; - if (p_beam_info->beamformee_entry[i].is_mu_sta) + if (beam_info->beamformee_entry[i].is_mu_sta) is_sounding = BEAMFORMEE_NOTIFY_ADD_MU; else is_sounding = BEAMFORMEE_NOTIFY_ADD_SU; } - if ((!p_beam_info->beamformee_entry[i].is_used) && p_beam_info->beamformee_entry[i].is_sound) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Delete BFee entry %d\n", __func__, i)); + if ((!beam_info->beamformee_entry[i].is_used) && beam_info->beamformee_entry[i].is_sound) { + PHYDM_DBG(dm, DBG_TXBF, "%s: Delete BFee entry %d\n", __func__, i); *idx = i; - if (p_beam_info->beamformee_entry[i].is_mu_sta) + if (beam_info->beamformee_entry[i].is_mu_sta) is_sounding = BEAMFORMEE_NOTIFY_DELETE_MU; else is_sounding = BEAMFORMEE_NOTIFY_DELETE_SU; } } - } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, is_sounding = %d\n", __func__, is_sounding)); +out: + PHYDM_DBG(dm, DBG_TXBF, "%s End, is_sounding = %d\n", __func__, is_sounding); return is_sounding; } @@ -670,15 +722,15 @@ phydm_beamfomring_is_sounding( /* This function is unused */ u8 phydm_beamforming_sounding_idx( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info ) { u8 idx = 0; - struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER) @@ -686,7 +738,7 @@ phydm_beamforming_sounding_idx( else { u8 i; for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (p_beam_info->beamformee_entry[i].is_used && (false == p_beam_info->beamformee_entry[i].is_sound)) { + if (beam_info->beamformee_entry[i].is_used && (!beam_info->beamformee_entry[i].is_sound)) { idx = i; break; } @@ -699,16 +751,16 @@ phydm_beamforming_sounding_idx( enum sounding_mode phydm_beamforming_sounding_mode( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info, + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 support_interface = p_dm_odm->support_interface; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 support_interface = dm->support_interface; - struct _RT_BEAMFORMEE_ENTRY beam_entry = p_beam_info->beamformee_entry[idx]; - struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; + struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; enum sounding_mode mode = beam_oid_info.sound_oid_mode; if (beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER) { @@ -722,19 +774,19 @@ phydm_beamforming_sounding_mode( else mode = sounding_stop_all_timer; } else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) { - if ((support_interface == ODM_ITRF_USB) && !(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) + if ((support_interface == ODM_ITRF_USB) && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) mode = SOUNDING_FW_VHT_TIMER; else mode = SOUNDING_SW_VHT_TIMER; } else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) { - if ((support_interface == ODM_ITRF_USB) && !(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) + if ((support_interface == ODM_ITRF_USB) && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) mode = SOUNDING_FW_HT_TIMER; else mode = SOUNDING_SW_HT_TIMER; } else mode = sounding_stop_all_timer; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] support_interface=%d, mode=%d\n", __func__, support_interface, mode)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] support_interface=%d, mode=%d\n", __func__, support_interface, mode); return mode; } @@ -742,18 +794,18 @@ phydm_beamforming_sounding_mode( u16 phydm_beamforming_sounding_time( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info, + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info, enum sounding_mode mode, u8 idx ) { u16 sounding_time = 0xffff; - struct _RT_BEAMFORMEE_ENTRY beam_entry = p_beam_info->beamformee_entry[idx]; - struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER) sounding_time = beam_oid_info.sound_oid_period * 32; @@ -767,18 +819,18 @@ phydm_beamforming_sounding_time( } -CHANNEL_WIDTH +enum channel_width phydm_beamforming_sounding_bw( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info, + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info, enum sounding_mode mode, u8 idx ) { - CHANNEL_WIDTH sounding_bw = CHANNEL_WIDTH_20; - struct _RT_BEAMFORMEE_ENTRY beam_entry = p_beam_info->beamformee_entry[idx]; - struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + enum channel_width sounding_bw = CHANNEL_WIDTH_20; + struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER) sounding_bw = beam_oid_info.sound_oid_bw; @@ -788,7 +840,7 @@ phydm_beamforming_sounding_bw( else sounding_bw = beam_entry.sound_bw; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, sounding_bw=0x%X\n", __func__, sounding_bw)); + PHYDM_DBG(dm, DBG_TXBF, "%s, sounding_bw=0x%X\n", __func__, sounding_bw); return sounding_bw; } @@ -796,29 +848,29 @@ phydm_beamforming_sounding_bw( boolean phydm_beamforming_select_beam_entry( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info ) { - struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; - /*p_entry.is_sound is different between first and latter NDPA, and should not be used as BFee entry selection*/ + /*entry.is_sound is different between first and latter NDPA, and should not be used as BFee entry selection*/ /*BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed sound_idx.*/ - p_sound_info->sound_idx = phydm_beamforming_sounding_idx(p_dm_odm, p_beam_info); - /*p_sound_info->sound_idx = 0;*/ + sound_info->sound_idx = phydm_beamforming_sounding_idx(dm, beam_info); + /*sound_info->sound_idx = 0;*/ - if (p_sound_info->sound_idx < BEAMFORMEE_ENTRY_NUM) - p_sound_info->sound_mode = phydm_beamforming_sounding_mode(p_dm_odm, p_beam_info, p_sound_info->sound_idx); + if (sound_info->sound_idx < BEAMFORMEE_ENTRY_NUM) + sound_info->sound_mode = phydm_beamforming_sounding_mode(dm, beam_info, sound_info->sound_idx); else - p_sound_info->sound_mode = sounding_stop_all_timer; + sound_info->sound_mode = sounding_stop_all_timer; - if (sounding_stop_all_timer == p_sound_info->sound_mode) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Return because of sounding_stop_all_timer\n", __func__)); + if (sounding_stop_all_timer == sound_info->sound_mode) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] Return because of sounding_stop_all_timer\n", __func__); return false; } else { - p_sound_info->sound_bw = phydm_beamforming_sounding_bw(p_dm_odm, p_beam_info, p_sound_info->sound_mode, p_sound_info->sound_idx); - p_sound_info->sound_period = phydm_beamforming_sounding_time(p_dm_odm, p_beam_info, p_sound_info->sound_mode, p_sound_info->sound_idx); + sound_info->sound_bw = phydm_beamforming_sounding_bw(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx); + sound_info->sound_period = phydm_beamforming_sounding_time(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx); return true; } } @@ -826,43 +878,42 @@ phydm_beamforming_select_beam_entry( /*SU BFee Entry Only*/ boolean phydm_beamforming_start_period( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; boolean ret = true; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; - phydm_beamforming_dym_ndpa_rate(p_dm_odm); + phydm_beamforming_dym_ndpa_rate(dm); - phydm_beamforming_select_beam_entry(p_dm_odm, p_beam_info); /* Modified */ + phydm_beamforming_select_beam_entry(dm, beam_info); /* Modified */ - if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER) - odm_set_timer(p_dm_odm, &p_beam_info->beamforming_timer, p_sound_info->sound_period); - else if (p_sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_HW_HT_TIMER || - p_sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) { + if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period); + else if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER || + sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) { HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF; - u32 val = (p_sound_info->sound_period | (timer_type << 16)); + u32 val = (sound_info->sound_period | (timer_type << 16)); /* HW timer stop: All IC has the same setting */ - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type)); - /* odm_write_1byte(p_dm_odm, 0x15F, 0); */ + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type)); + /* odm_write_1byte(dm, 0x15F, 0); */ /* HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes */ - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_INIT, (u8 *)(&val)); - /* odm_write_1byte(p_dm_odm, 0x164, 1); */ - /* odm_write_4byte(p_dm_odm, 0x15C, val); */ + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_INIT, (u8 *)(&val)); + /* odm_write_1byte(dm, 0x164, 1); */ + /* odm_write_4byte(dm, 0x15C, val); */ /* HW timer start: All IC has the same setting */ - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_START, (u8 *)(&timer_type)); - /* odm_write_1byte(p_dm_odm, 0x15F, 0x5); */ - } else if (p_sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_FW_HT_TIMER) - ret = beamforming_start_fw(p_dm_odm, p_sound_info->sound_idx); + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_START, (u8 *)(&timer_type)); + /* odm_write_1byte(dm, 0x15F, 0x5); */ + } else if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER) + ret = beamforming_start_fw(dm, sound_info->sound_idx); else ret = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] sound_idx=%d, sound_mode=%d, sound_bw=%d, sound_period=%d\n", __func__, - p_sound_info->sound_idx, p_sound_info->sound_mode, p_sound_info->sound_bw, p_sound_info->sound_period)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] sound_idx=%d, sound_mode=%d, sound_bw=%d, sound_period=%d\n", __func__, + sound_info->sound_idx, sound_info->sound_mode, sound_info->sound_bw, sound_info->sound_period); return ret; } @@ -871,136 +922,138 @@ phydm_beamforming_start_period( *SU BFee Entry Only*/ void phydm_beamforming_end_period_sw( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + /*void *adapter = dm->adapter;*/ + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER) - odm_cancel_timer(p_dm_odm, &p_beam_info->beamforming_timer); - else if (p_sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_HW_HT_TIMER || - p_sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) + if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_cancel_timer(dm, &beam_info->beamforming_timer); + else if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER || + sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) /*HW timer stop: All IC has the same setting*/ - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type)); - /*odm_write_1byte(p_dm_odm, 0x15F, 0);*/ + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type)); + /*odm_write_1byte(dm, 0x15F, 0);*/ } void phydm_beamforming_end_period_fw( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 idx = 0; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]\n", __func__)); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); + PHYDM_DBG(dm, DBG_TXBF, "[%s]\n", __func__); } /*SU BFee Entry Only*/ void phydm_beamforming_clear_entry_sw( - void *p_dm_void, + void *dm_void, boolean is_delete, u8 delete_idx ) { u8 idx = 0; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; if (is_delete) { if (delete_idx < BEAMFORMEE_ENTRY_NUM) { - p_beamform_entry = p_beam_info->beamformee_entry + delete_idx; - if (!((!p_beamform_entry->is_used) && p_beamform_entry->is_sound)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW delete_idx is wrong!!!!!\n", __func__)); + beamform_entry = beam_info->beamformee_entry + delete_idx; + if (!((!beamform_entry->is_used) && beamform_entry->is_sound)) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] SW delete_idx is wrong!!!!!\n", __func__); return; } } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW delete BFee entry %d\n", __func__, delete_idx)); - if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) { - p_beamform_entry->is_beamforming_in_progress = false; - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - } else if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&delete_idx); + PHYDM_DBG(dm, DBG_TXBF, "[%s] SW delete BFee entry %d\n", __func__, delete_idx); + if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) { + beamform_entry->is_beamforming_in_progress = false; + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + } else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&delete_idx); } - p_beamform_entry->is_sound = false; - } else { - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_beamform_entry = p_beam_info->beamformee_entry + idx; - - /*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ - /*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/ - /*However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/ - - if (p_beamform_entry->is_sound) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW reset BFee entry %d\n", __func__, idx)); - /* - * If End procedure is - * 1. Between (Send NDPA, C2H packet return), reset state to initialized. - * After C2H packet return , status bit will be set to zero. - * - * 2. After C2H packet, then reset state to initialized and clear status bit. - */ - - if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) - phydm_beamforming_end_sw(p_dm_odm, 0); - else if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx); - } + beamform_entry->is_sound = false; + return; + } - p_beamform_entry->is_sound = false; - } + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + beamform_entry = beam_info->beamformee_entry + idx; + + /*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ + /*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/ + /*However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/ + + if (!beamform_entry->is_sound) + continue; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] SW reset BFee entry %d\n", __func__, idx); + /* + * If End procedure is + * 1. Between (Send NDPA, C2H packet return), reset state to initialized. + * After C2H packet return , status bit will be set to zero. + * + * 2. After C2H packet, then reset state to initialized and clear status bit. + */ + + if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) + phydm_beamforming_end_sw(dm, 0); + else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx); } + + beamform_entry->is_sound = false; } } void phydm_beamforming_clear_entry_fw( - void *p_dm_void, + void *dm_void, boolean is_delete, u8 delete_idx ) { u8 idx = 0; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; if (is_delete) { if (delete_idx < BEAMFORMEE_ENTRY_NUM) { - p_beamform_entry = p_beam_info->beamformee_entry + delete_idx; + beamform_entry = beam_info->beamformee_entry + delete_idx; - if (!((!p_beamform_entry->is_used) && p_beamform_entry->is_sound)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] FW delete_idx is wrong!!!!!\n", __func__)); + if (!((!beamform_entry->is_used) && beamform_entry->is_sound)) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] FW delete_idx is wrong!!!!!\n", __func__); return; } } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: FW delete BFee entry %d\n", __func__, delete_idx)); - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - p_beamform_entry->is_sound = false; + PHYDM_DBG(dm, DBG_TXBF, "%s: FW delete BFee entry %d\n", __func__, delete_idx); + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + beamform_entry->is_sound = false; } else { for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_beamform_entry = p_beam_info->beamformee_entry + idx; + beamform_entry = beam_info->beamformee_entry + idx; /*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ /*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/ /*However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/ - if (p_beamform_entry->is_sound) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]FW reset BFee entry %d\n", __func__, idx)); + if (beamform_entry->is_sound) { + PHYDM_DBG(dm, DBG_TXBF, "[%s]FW reset BFee entry %d\n", __func__, idx); /* * If End procedure is * 1. Between (Send NDPA, C2H packet return), reset state to initialized. @@ -1009,8 +1062,8 @@ phydm_beamforming_clear_entry_fw( * 2. After C2H packet, then reset state to initialized and clear status bit. */ - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; - p_beamform_entry->is_sound = false; + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + beamform_entry->is_sound = false; } } } @@ -1024,73 +1077,73 @@ phydm_beamforming_clear_entry_fw( */ void phydm_beamforming_notify( - void *p_dm_void + void *dm_void ) { u8 idx = BEAMFORMEE_ENTRY_NUM; enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - is_sounding = phydm_beamfomring_is_sounding(p_dm_odm, p_beam_info, &idx); + is_sounding = phydm_beamfomring_is_sounding(dm, beam_info, &idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Before notify, is_sounding=%d, idx=%d\n", __func__, is_sounding, idx)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: p_beam_info->beamformee_su_cnt = %d\n", __func__, p_beam_info->beamformee_su_cnt)); + PHYDM_DBG(dm, DBG_TXBF, "%s, Before notify, is_sounding=%d, idx=%d\n", __func__, is_sounding, idx); + PHYDM_DBG(dm, DBG_TXBF, "%s: beam_info->beamformee_su_cnt = %d\n", __func__, beam_info->beamformee_su_cnt); switch (is_sounding) { case BEAMFORMEE_NOTIFY_ADD_SU: - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_SU\n", __func__)); - phydm_beamforming_start_period(p_dm_odm); + PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_ADD_SU\n", __func__); + phydm_beamforming_start_period(dm); break; case BEAMFORMEE_NOTIFY_DELETE_SU: - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_SU\n", __func__)); - if (p_sound_info->sound_mode == SOUNDING_FW_HT_TIMER || p_sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) { - phydm_beamforming_clear_entry_fw(p_dm_odm, true, idx); - if (p_beam_info->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ - phydm_beamforming_end_period_fw(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_DELETE_SU\n", __func__); + if (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) { + phydm_beamforming_clear_entry_fw(dm, true, idx); + if (beam_info->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ + phydm_beamforming_end_period_fw(dm); + PHYDM_DBG(dm, DBG_TXBF, "%s: No BFee left\n", __func__); } } else { - phydm_beamforming_clear_entry_sw(p_dm_odm, true, idx); - if (p_beam_info->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ - phydm_beamforming_end_period_sw(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); + phydm_beamforming_clear_entry_sw(dm, true, idx); + if (beam_info->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ + phydm_beamforming_end_period_sw(dm); + PHYDM_DBG(dm, DBG_TXBF, "%s: No BFee left\n", __func__); } } break; case BEAMFORMEE_NOTIFY_ADD_MU: - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_MU\n", __func__)); - if (p_beam_info->beamformee_mu_cnt == 2) { - /*if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER) - odm_set_timer(p_dm_odm, &p_beam_info->beamforming_timer, p_sound_info->sound_period);*/ - odm_set_timer(p_dm_odm, &p_beam_info->beamforming_timer, 1000); /*Do MU sounding every 1sec*/ + PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_ADD_MU\n", __func__); + if (beam_info->beamformee_mu_cnt == 2) { + /*if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);*/ + odm_set_timer(dm, &beam_info->beamforming_timer, 1000); /*Do MU sounding every 1sec*/ } else - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less or larger than 2 MU STAs, not to set timer\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s: Less or larger than 2 MU STAs, not to set timer\n", __func__); break; case BEAMFORMEE_NOTIFY_DELETE_MU: - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_MU\n", __func__)); - if (p_beam_info->beamformee_mu_cnt == 1) { - /*if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER)*/{ - odm_cancel_timer(p_dm_odm, &p_beam_info->beamforming_timer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less than 2 MU STAs, stop sounding\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_DELETE_MU\n", __func__); + if (beam_info->beamformee_mu_cnt == 1) { + /*if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)*/{ + odm_cancel_timer(dm, &beam_info->beamforming_timer); + PHYDM_DBG(dm, DBG_TXBF, "%s: Less than 2 MU STAs, stop sounding\n", __func__); } } break; case BEAMFORMING_NOTIFY_RESET: - if (p_sound_info->sound_mode == SOUNDING_FW_HT_TIMER || p_sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) { - phydm_beamforming_clear_entry_fw(p_dm_odm, false, idx); - phydm_beamforming_end_period_fw(p_dm_odm); + if (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) { + phydm_beamforming_clear_entry_fw(dm, false, idx); + phydm_beamforming_end_period_fw(dm); } else { - phydm_beamforming_clear_entry_sw(p_dm_odm, false, idx); - phydm_beamforming_end_period_sw(p_dm_odm); + phydm_beamforming_clear_entry_sw(dm, false, idx); + phydm_beamforming_end_period_sw(dm); } break; @@ -1105,73 +1158,74 @@ phydm_beamforming_notify( boolean beamforming_init_entry( - void *p_dm_void, + void *dm_void, u16 sta_idx, u8 *bfer_bfee_idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; - struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry = NULL; - struct _RT_BEAMFORM_STAINFO *p_sta = NULL; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx]; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; + struct _RT_BEAMFORM_STAINFO *sta = NULL; enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; u8 bfer_idx = 0xF, bfee_idx = 0xF; u8 num_of_sounding_dim = 0, comp_steering_num_of_bfer = 0; - p_sta = phydm_sta_info_init(p_dm_odm, sta_idx); + sta = phydm_sta_info_init(dm, sta_idx); /*The current setting does not support Beaforming*/ - if (BEAMFORMING_CAP_NONE == p_sta->ht_beamform_cap && BEAMFORMING_CAP_NONE == p_sta->vht_beamform_cap) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("The configuration disabled Beamforming! Skip...\n")); + if (BEAMFORMING_CAP_NONE == sta->ht_beamform_cap && BEAMFORMING_CAP_NONE == sta->vht_beamform_cap) { + PHYDM_DBG(dm, DBG_TXBF, "The configuration disabled Beamforming! Skip...\n"); return false; } - if (p_sta->wireless_mode < WIRELESS_MODE_N_24G) + if (!(cmn_sta->support_wireless_set & (WIRELESS_VHT | WIRELESS_HT))) return false; else { - if (p_sta->wireless_mode & WIRELESS_MODE_N_5G || p_sta->wireless_mode & WIRELESS_MODE_N_24G) {/*HT*/ - if (TEST_FLAG(p_sta->cur_beamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {/*We are Beamformee because the STA is Beamformer*/ - beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_HT_EXPLICIT); - num_of_sounding_dim = (p_sta->cur_beamform & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6; + if (cmn_sta->support_wireless_set & WIRELESS_HT) {/*HT*/ + if (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {/*We are Beamformee because the STA is Beamformer*/ + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_HT_EXPLICIT); + num_of_sounding_dim = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6; } /*We are Beamformer because the STA is Beamformee*/ - if (TEST_FLAG(p_sta->cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) || - TEST_FLAG(p_sta->ht_beamform_cap, BEAMFORMING_HT_BEAMFORMER_TEST)) { - beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT); - comp_steering_num_of_bfer = (p_sta->cur_beamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4; + if (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) || + TEST_FLAG(sta->ht_beamform_cap, BEAMFORMING_HT_BEAMFORMER_TEST)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT); + comp_steering_num_of_bfer = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT cur_beamform=0x%X, beamform_cap=0x%X\n", __func__, p_sta->cur_beamform, beamform_cap)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT num_of_sounding_dim=%d, comp_steering_num_of_bfer=%d\n", __func__, num_of_sounding_dim, comp_steering_num_of_bfer)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] HT cur_beamform=0x%X, beamform_cap=0x%X\n", __func__, sta->cur_beamform, beamform_cap); + PHYDM_DBG(dm, DBG_TXBF, "[%s] HT num_of_sounding_dim=%d, comp_steering_num_of_bfer=%d\n", __func__, num_of_sounding_dim, comp_steering_num_of_bfer); } #if (ODM_IC_11AC_SERIES_SUPPORT == 1) - if (p_sta->wireless_mode & WIRELESS_MODE_AC_5G || p_sta->wireless_mode & WIRELESS_MODE_AC_24G) { /*VHT*/ + if (cmn_sta->support_wireless_set & WIRELESS_VHT) { /*VHT*/ - /* We are Beamformee because the STA is SU Beamformer*/ - if (TEST_FLAG(p_sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { - beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_SU); - num_of_sounding_dim = (p_sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; - } - /* We are Beamformer because the STA is SU Beamformee*/ - if (TEST_FLAG(p_sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) || - TEST_FLAG(p_sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { - beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_SU); - comp_steering_num_of_bfer = (p_sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; - } - /* We are Beamformee because the STA is MU Beamformer*/ - if (TEST_FLAG(p_sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { - beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_MU); - num_of_sounding_dim = (p_sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; - } - /* We are Beamformer because the STA is MU Beamformee*/ - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ap)) { /* Only AP mode supports to act an MU beamformer */ - if (TEST_FLAG(p_sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) || - TEST_FLAG(p_sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { - beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_MU); - comp_steering_num_of_bfer = (p_sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; - } + /* We are Beamformee because the STA is SU Beamformer*/ + if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_SU); + num_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; + } + /* We are Beamformer because the STA is SU Beamformee*/ + if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) || + TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_SU); + comp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; + } + /* We are Beamformee because the STA is MU Beamformer*/ + if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_MU); + num_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; + } + /* We are Beamformer because the STA is MU Beamformee*/ + if (phydm_acting_determine(dm, phydm_acting_as_ap)) { /* Only AP mode supports to act an MU beamformer */ + if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) || + TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_MU); + comp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT cur_beamform_vht=0x%X, beamform_cap=0x%X\n", __func__, p_sta->cur_beamform_vht, beamform_cap)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT num_of_sounding_dim=0x%X, comp_steering_num_of_bfer=0x%X\n", __func__, num_of_sounding_dim, comp_steering_num_of_bfer)); + } + PHYDM_DBG(dm, DBG_TXBF, "[%s]VHT cur_beamform_vht=0x%X, beamform_cap=0x%X\n", __func__, sta->cur_beamform_vht, beamform_cap); + PHYDM_DBG(dm, DBG_TXBF, "[%s]VHT num_of_sounding_dim=0x%X, comp_steering_num_of_bfer=0x%X\n", __func__, num_of_sounding_dim, comp_steering_num_of_bfer); } #endif @@ -1181,49 +1235,49 @@ beamforming_init_entry( if (beamform_cap == BEAMFORMING_CAP_NONE) return false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Self BF Entry Cap = 0x%02X\n", __func__, beamform_cap)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Self BF Entry Cap = 0x%02X\n", __func__, beamform_cap); /*We are BFee, so the entry is BFer*/ if (beamform_cap & (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) { - p_beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(p_dm_odm, p_sta->ra, &bfer_idx); + beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, sta->ra, &bfer_idx); - if (p_beamformer_entry == NULL) { - p_beamformer_entry = beamforming_add_bfer_entry(p_dm_odm, p_sta, beamform_cap, num_of_sounding_dim, &bfer_idx); - if (p_beamformer_entry == NULL) - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Not enough BFer entry!!!!!\n", __func__)); + if (beamformer_entry == NULL) { + beamformer_entry = beamforming_add_bfer_entry(dm, sta, beamform_cap, num_of_sounding_dim, &bfer_idx); + if (beamformer_entry == NULL) + PHYDM_DBG(dm, DBG_TXBF, "[%s]Not enough BFer entry!!!!!\n", __func__); } } /*We are BFer, so the entry is BFee*/ if (beamform_cap & (BEAMFORMER_CAP_VHT_MU | BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) { - p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, p_sta->ra, &bfee_idx); + beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, sta->ra, &bfee_idx); /*¦pªGBFeeIdx = 0xF «h¥Nªí¥Ø«eentry·í¤¤¨S¦³¬Û¦PªºMACID¦b¤º*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BFee entry 0x%X by address\n", __func__, bfee_idx)); - if (p_beamform_entry == NULL) { - p_beamform_entry = beamforming_add_bfee_entry(p_dm_odm, p_sta, beamform_cap, num_of_sounding_dim, comp_steering_num_of_bfer, &bfee_idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: p_sta->AID=%d, p_sta->mac_id=%d\n", __func__, p_sta->aid, p_sta->mac_id)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Get BFee entry 0x%X by address\n", __func__, bfee_idx); + if (beamform_entry == NULL) { + beamform_entry = beamforming_add_bfee_entry(dm, sta, beamform_cap, num_of_sounding_dim, comp_steering_num_of_bfer, &bfee_idx); + PHYDM_DBG(dm, DBG_TXBF, "[%s]: sta->AID=%d, sta->mac_id=%d\n", __func__, sta->aid, sta->mac_id); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: Add BFee entry %d\n", __func__, bfee_idx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s]: Add BFee entry %d\n", __func__, bfee_idx); - if (p_beamform_entry == NULL) + if (beamform_entry == NULL) return false; else - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; } else { /*Entry has been created. If entry is initialing or progressing then errors occur.*/ - if (p_beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && - p_beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) + if (beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && + beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) return false; else - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; } - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; - phydm_sta_info_update(p_dm_odm, sta_idx, p_beamform_entry); + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + phydm_sta_info_update(dm, sta_idx, beamform_entry); } *bfer_bfee_idx = (bfer_idx << 4) | bfee_idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End: bfer_idx=0x%X, bfee_idx=0x%X, bfer_bfee_idx=0x%X\n", __func__, bfer_idx, bfee_idx, *bfer_bfee_idx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] End: bfer_idx=0x%X, bfee_idx=0x%X, bfer_bfee_idx=0x%X\n", __func__, bfer_idx, bfee_idx, *bfer_bfee_idx); return true; } @@ -1231,190 +1285,196 @@ beamforming_init_entry( void beamforming_deinit_entry( - void *p_dm_void, + void *dm_void, u8 *RA ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 idx = 0; - struct _RT_BEAMFORMER_ENTRY *p_bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(p_dm_odm, RA, &idx); - struct _RT_BEAMFORMEE_ENTRY *p_bfee_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct _RT_BEAMFORMER_ENTRY *bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, RA, &idx); + struct _RT_BEAMFORMEE_ENTRY *bfee_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); boolean ret = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - if (p_bfee_entry != NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, p_bfee_entry\n", __func__)); - p_bfee_entry->is_used = false; - p_bfee_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; - p_bfee_entry->is_beamforming_in_progress = false; - if (p_bfee_entry->is_mu_sta) { - p_dm_odm->beamforming_info.beamformee_mu_cnt -= 1; - p_dm_odm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(p_dm_odm); + if (bfee_entry != NULL) { + PHYDM_DBG(dm, DBG_TXBF, "%s, bfee_entry\n", __func__); + bfee_entry->is_used = false; + bfee_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + bfee_entry->is_beamforming_in_progress = false; + if (bfee_entry->is_mu_sta) { + dm->beamforming_info.beamformee_mu_cnt -= 1; + dm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm); } else - p_dm_odm->beamforming_info.beamformee_su_cnt -= 1; + dm->beamforming_info.beamformee_su_cnt -= 1; ret = true; } - if (p_bfer_entry != NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, p_bfer_entry\n", __func__)); - p_bfer_entry->is_used = false; - p_bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; - if (p_bfer_entry->is_mu_ap) - p_dm_odm->beamforming_info.beamformer_mu_cnt -= 1; + if (bfer_entry != NULL) { + PHYDM_DBG(dm, DBG_TXBF, "%s, bfer_entry\n", __func__); + bfer_entry->is_used = false; + bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + if (bfer_entry->is_mu_ap) + dm->beamforming_info.beamformer_mu_cnt -= 1; else - p_dm_odm->beamforming_info.beamformer_su_cnt -= 1; + dm->beamforming_info.beamformer_su_cnt -= 1; ret = true; } if (ret == true) - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_LEAVE, (u8 *)&idx); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_LEAVE, (u8 *)&idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, idx = 0x%X\n", __func__, idx)); + PHYDM_DBG(dm, DBG_TXBF, "%s End, idx = 0x%X\n", __func__, idx); } boolean beamforming_start_v1( - void *p_dm_void, + void *dm_void, u8 *RA, boolean mode, - CHANNEL_WIDTH BW, + enum channel_width BW, u8 rate ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 idx = 0; - struct _RT_BEAMFORMEE_ENTRY *p_entry; + struct _RT_BEAMFORMEE_ENTRY *entry; boolean ret = true; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; - p_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); - if (p_entry->is_used == false) { - p_entry->is_beamforming_in_progress = false; + if (entry->is_used == false) { + entry->is_beamforming_in_progress = false; return false; } else { - if (p_entry->is_beamforming_in_progress) + if (entry->is_beamforming_in_progress) return false; - p_entry->is_beamforming_in_progress = true; + entry->is_beamforming_in_progress = true; if (mode == 1) { - if (!(p_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) { - p_entry->is_beamforming_in_progress = false; + if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) { + entry->is_beamforming_in_progress = false; return false; } } else if (mode == 0) { - if (!(p_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) { - p_entry->is_beamforming_in_progress = false; + if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) { + entry->is_beamforming_in_progress = false; return false; } } - if (p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { - p_entry->is_beamforming_in_progress = false; + if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + entry->is_beamforming_in_progress = false; return false; } else { - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; - p_entry->is_sound = true; + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + entry->is_sound = true; } } - p_entry->sound_bw = BW; - p_beam_info->beamformee_cur_idx = idx; - phydm_beamforming_ndpa_rate(p_dm_odm, BW, rate); - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx); + entry->sound_bw = BW; + beam_info->beamformee_cur_idx = idx; + phydm_beamforming_ndpa_rate(dm, BW, rate); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx); if (mode == 1) - ret = beamforming_send_ht_ndpa_packet(p_dm_odm, RA, BW, NORMAL_QUEUE); + ret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE); else - ret = beamforming_send_vht_ndpa_packet(p_dm_odm, RA, p_entry->aid, BW, NORMAL_QUEUE); + ret = beamforming_send_vht_ndpa_packet(dm, RA, entry->aid, BW, NORMAL_QUEUE); if (ret == false) { - beamforming_leave(p_dm_odm, RA); - p_entry->is_beamforming_in_progress = false; + beamforming_leave(dm, RA); + entry->is_beamforming_in_progress = false; return false; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s idx %d\n", __func__, idx)); + PHYDM_DBG(dm, DBG_TXBF, "%s idx %d\n", __func__, idx); return true; } boolean beamforming_start_sw( - void *p_dm_void, + void *dm_void, u8 idx, u8 mode, - CHANNEL_WIDTH BW + enum channel_width BW ) { u8 *ra = NULL; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMEE_ENTRY *p_entry; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMEE_ENTRY *entry; boolean ret = true; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; +#ifdef SUPPORT_MU_BF +#if (SUPPORT_MU_BF == 1) + u8 i, poll_sta_cnt = 0; + boolean is_get_first_bfee = false; +#endif +#endif - if (p_beam_info->is_mu_sounding) { - p_beam_info->is_mu_sounding_in_progress = true; - p_entry = &(p_beam_info->beamformee_entry[idx]); - ra = p_entry->mac_addr; + if (beam_info->is_mu_sounding) { + beam_info->is_mu_sounding_in_progress = true; + entry = &beam_info->beamformee_entry[idx]; + ra = entry->mac_addr; } else { - p_entry = &(p_beam_info->beamformee_entry[idx]); + entry = &beam_info->beamformee_entry[idx]; - if (p_entry->is_used == false) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for idx =%d\n", idx)); - p_entry->is_beamforming_in_progress = false; + if (entry->is_used == false) { + PHYDM_DBG(dm, DBG_TXBF, "Skip Beamforming, no entry for idx =%d\n", idx); + entry->is_beamforming_in_progress = false; return false; - } else { - if (p_entry->is_beamforming_in_progress) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("is_beamforming_in_progress, skip...\n")); - return false; - } + } + + if (entry->is_beamforming_in_progress) { + PHYDM_DBG(dm, DBG_TXBF, "is_beamforming_in_progress, skip...\n"); + return false; + } + + entry->is_beamforming_in_progress = true; + ra = entry->mac_addr; - p_entry->is_beamforming_in_progress = true; - ra = p_entry->mac_addr; - - if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) { - if (!(p_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) { - p_entry->is_beamforming_in_progress = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n", __func__)); - return false; - } - } else if (mode == SOUNDING_SW_VHT_TIMER || mode == SOUNDING_HW_VHT_TIMER || mode == SOUNDING_AUTO_VHT_TIMER) { - if (!(p_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) { - p_entry->is_beamforming_in_progress = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n", __func__)); - return false; - } + if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) { + if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) { + entry->is_beamforming_in_progress = false; + PHYDM_DBG(dm, DBG_TXBF, "%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n", __func__); + return false; } - if (p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { - p_entry->is_beamforming_in_progress = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by incorrect beamform_entry_state(%d) <==\n", __func__, p_entry->beamform_entry_state)); + } else if (mode == SOUNDING_SW_VHT_TIMER || mode == SOUNDING_HW_VHT_TIMER || mode == SOUNDING_AUTO_VHT_TIMER) { + if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) { + entry->is_beamforming_in_progress = false; + PHYDM_DBG(dm, DBG_TXBF, "%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n", __func__); return false; - } else { - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; - p_entry->is_sound = true; } } + if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + entry->is_beamforming_in_progress = false; + PHYDM_DBG(dm, DBG_TXBF, "%s Return by incorrect beamform_entry_state(%d) <==\n", __func__, entry->beamform_entry_state); + return false; + } else { + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + entry->is_sound = true; + } - p_beam_info->beamformee_cur_idx = idx; + beam_info->beamformee_cur_idx = idx; } /*2014.12.22 Luke: Need to be checked*/ /*GET_TXBF_INFO(adapter)->fTxbfSet(adapter, TXBF_SET_SOUNDING_STATUS, (u8*)&idx);*/ if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) - ret = beamforming_send_ht_ndpa_packet(p_dm_odm, ra, BW, NORMAL_QUEUE); + ret = beamforming_send_ht_ndpa_packet(dm, ra, BW, NORMAL_QUEUE); else - ret = beamforming_send_vht_ndpa_packet(p_dm_odm, ra, p_entry->aid, BW, NORMAL_QUEUE); + ret = beamforming_send_vht_ndpa_packet(dm, ra, entry->aid, BW, NORMAL_QUEUE); if (ret == false) { - beamforming_leave(p_dm_odm, ra); - p_entry->is_beamforming_in_progress = false; + beamforming_leave(dm, ra); + entry->is_beamforming_in_progress = false; return false; } @@ -1424,27 +1484,27 @@ beamforming_start_sw( --------------------------*/ #ifdef SUPPORT_MU_BF #if (SUPPORT_MU_BF == 1) - { - u8 idx, poll_sta_cnt = 0; - boolean is_get_first_bfee = false; - - if (p_beam_info->beamformee_mu_cnt > 1) { /* More than 1 MU STA*/ - - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_entry = &(p_beam_info->beamformee_entry[idx]); - if (p_entry->is_mu_sta) { - if (is_get_first_bfee) { - poll_sta_cnt++; - if (poll_sta_cnt == (p_beam_info->beamformee_mu_cnt - 1))/* The last STA*/ - send_sw_vht_bf_report_poll(p_dm_odm, p_entry->mac_addr, true); - else - send_sw_vht_bf_report_poll(p_dm_odm, p_entry->mac_addr, false); - } else - is_get_first_bfee = true; - } - } + if (beam_info->beamformee_mu_cnt <= 1) + goto out; + + /* More than 1 MU STA*/ + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + entry = &beam_info->beamformee_entry[i]; + if (!entry->is_mu_sta) + continue; + + if (!is_get_first_bfee) { + is_get_first_bfee = true; + continue; } + + poll_sta_cnt++; + if (poll_sta_cnt == (beam_info->beamformee_mu_cnt - 1))/* The last STA*/ + send_sw_vht_bf_report_poll(dm, entry->mac_addr, true); + else + send_sw_vht_bf_report_poll(dm, entry->mac_addr, false); } +out: #endif #endif return true; @@ -1453,158 +1513,161 @@ beamforming_start_sw( boolean beamforming_start_fw( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMEE_ENTRY *p_entry; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMEE_ENTRY *entry; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; - p_entry = &(p_beam_info->beamformee_entry[idx]); - if (p_entry->is_used == false) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for idx =%d\n", idx)); + entry = &beam_info->beamformee_entry[idx]; + if (entry->is_used == false) { + PHYDM_DBG(dm, DBG_TXBF, "Skip Beamforming, no entry for idx =%d\n", idx); return false; } - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; - p_entry->is_sound = true; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + entry->is_sound = true; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, idx=0x%X\n", __func__, idx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] End, idx=0x%X\n", __func__, idx); return true; } void beamforming_check_sounding_success( - void *p_dm_void, + void *dm_void, boolean status ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx]; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[David]@%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[David]@%s Start!\n", __func__); if (status == 1) { - if (p_entry->log_status_fail_cnt == 21) - beamforming_dym_period(p_dm_odm, status); - p_entry->log_status_fail_cnt = 0; - } else if (p_entry->log_status_fail_cnt <= 20) { - p_entry->log_status_fail_cnt++; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s log_status_fail_cnt %d\n", __func__, p_entry->log_status_fail_cnt)); + if (entry->log_status_fail_cnt == 21) + beamforming_dym_period(dm, status); + entry->log_status_fail_cnt = 0; + } else if (entry->log_status_fail_cnt <= 20) { + entry->log_status_fail_cnt++; + PHYDM_DBG(dm, DBG_TXBF, "%s log_status_fail_cnt %d\n", __func__, entry->log_status_fail_cnt); } - if (p_entry->log_status_fail_cnt > 20) { - p_entry->log_status_fail_cnt = 21; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s log_status_fail_cnt > 20, Stop SOUNDING\n", __func__)); - beamforming_dym_period(p_dm_odm, status); + if (entry->log_status_fail_cnt > 20) { + entry->log_status_fail_cnt = 21; + PHYDM_DBG(dm, DBG_TXBF, "%s log_status_fail_cnt > 20, Stop SOUNDING\n", __func__); + beamforming_dym_period(dm, status); } } void phydm_beamforming_end_sw( - void *p_dm_void, + void *dm_void, boolean status ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); - - if (p_beam_info->is_mu_sounding) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: MU sounding done\n", __func__)); - p_beam_info->is_mu_sounding_in_progress = false; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&(p_beam_info->beamformee_cur_idx)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx]; + + if (beam_info->is_mu_sounding) { + PHYDM_DBG(dm, DBG_TXBF, "%s: MU sounding done\n", __func__); + beam_info->is_mu_sounding_in_progress = false; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, + (u8 *)&beam_info->beamformee_cur_idx); } else { - if (p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSING) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamformStatus %d\n", __func__, p_entry->beamform_entry_state)); + if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSING) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] BeamformStatus %d\n", __func__, entry->beamform_entry_state); return; } - if ((p_beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7) && (p_beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9) && (p_beam_info->snding3ss == false)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] VHT3SS 7,8,9, do not apply V matrix.\n", __func__)); - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&(p_beam_info->beamformee_cur_idx)); + if ((beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7) && (beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9) && (!beam_info->snding3ss)) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] VHT3SS 7,8,9, do not apply V matrix.\n", __func__); + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, + (u8 *)&beam_info->beamformee_cur_idx); } else if (status == 1) { - p_entry->log_status_fail_cnt = 0; - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&(p_beam_info->beamformee_cur_idx)); + entry->log_status_fail_cnt = 0; + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, + (u8 *)&beam_info->beamformee_cur_idx); } else { - p_entry->log_status_fail_cnt++; - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; - hal_com_txbf_set(p_dm_odm, TXBF_SET_TX_PATH_RESET, (u8 *)&(p_beam_info->beamformee_cur_idx)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] log_status_fail_cnt %d\n", __func__, p_entry->log_status_fail_cnt)); + entry->log_status_fail_cnt++; + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + hal_com_txbf_set(dm, TXBF_SET_TX_PATH_RESET, + (u8 *)&beam_info->beamformee_cur_idx); + PHYDM_DBG(dm, DBG_TXBF, "[%s] log_status_fail_cnt %d\n", __func__, entry->log_status_fail_cnt); } - if (p_entry->log_status_fail_cnt > 50) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s log_status_fail_cnt > 50, Stop SOUNDING\n", __func__)); - p_entry->is_sound = false; - beamforming_deinit_entry(p_dm_odm, p_entry->mac_addr); + if (entry->log_status_fail_cnt > 50) { + PHYDM_DBG(dm, DBG_TXBF, "%s log_status_fail_cnt > 50, Stop SOUNDING\n", __func__); + entry->is_sound = false; + beamforming_deinit_entry(dm, entry->mac_addr); /*Modified by David - Every action of deleting entry should follow by Notify*/ - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); } - p_entry->is_beamforming_in_progress = false; + entry->is_beamforming_in_progress = false; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: status=%d\n", __func__, status)); + PHYDM_DBG(dm, DBG_TXBF, "%s: status=%d\n", __func__, status); } void beamforming_timer_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - void *p_dm_void + void *dm_void #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - void *p_context + void *context #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct _ADAPTER *adapter = (struct _ADAPTER *)p_context; - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; + void *adapter = (void *)context; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->odmpriv; #endif boolean ret = false; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); - struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]); + struct _RT_SOUNDING_INFO *sound_info = &(beam_info->sounding_info); boolean is_beamforming_in_progress; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - if (p_beam_info->is_mu_sounding) - is_beamforming_in_progress = p_beam_info->is_mu_sounding_in_progress; + if (beam_info->is_mu_sounding) + is_beamforming_in_progress = beam_info->is_mu_sounding_in_progress; else - is_beamforming_in_progress = p_entry->is_beamforming_in_progress; + is_beamforming_in_progress = entry->is_beamforming_in_progress; if (is_beamforming_in_progress) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("is_beamforming_in_progress, reset it\n")); - phydm_beamforming_end_sw(p_dm_odm, 0); + PHYDM_DBG(dm, DBG_TXBF, "is_beamforming_in_progress, reset it\n"); + phydm_beamforming_end_sw(dm, 0); } - ret = phydm_beamforming_select_beam_entry(p_dm_odm, p_beam_info); + ret = phydm_beamforming_select_beam_entry(dm, beam_info); #if (SUPPORT_MU_BF == 1) - if (ret && p_beam_info->beamformee_mu_cnt > 1) + if (ret && beam_info->beamformee_mu_cnt > 1) ret = 1; else ret = 0; #endif if (ret) - ret = beamforming_start_sw(p_dm_odm, p_sound_info->sound_idx, p_sound_info->sound_mode, p_sound_info->sound_bw); + ret = beamforming_start_sw(dm, sound_info->sound_idx, sound_info->sound_mode, sound_info->sound_bw); else - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Error value return from BeamformingStart_V2\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s, Error value return from BeamformingStart_V2\n", __func__); - if ((p_beam_info->beamformee_su_cnt != 0) || (p_beam_info->beamformee_mu_cnt > 1)) { - if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER) - odm_set_timer(p_dm_odm, &p_beam_info->beamforming_timer, p_sound_info->sound_period); + if ((beam_info->beamformee_su_cnt != 0) || (beam_info->beamformee_mu_cnt > 1)) { + if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period); else { - u32 val = (p_sound_info->sound_period << 16) | HAL_TIMER_TXBF; - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_RESTART, (u8 *)(&val)); + u32 val = (sound_info->sound_period << 16) | HAL_TIMER_TXBF; + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_RESTART, (u8 *)(&val)); } } } @@ -1613,24 +1676,24 @@ beamforming_timer_callback( void beamforming_sw_timer_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct timer_list *p_timer + struct phydm_timer_list *timer #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) void *function_context #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + void *adapter = (void *)timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - beamforming_timer_callback(p_dm_odm); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + beamforming_timer_callback(dm); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)function_context; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)function_context; + void *adapter = dm->adapter; - if (adapter->net_closed == true) + if (*(dm->is_net_closed) == true) return; rtw_run_in_thread_cmd(adapter, beamforming_timer_callback, adapter); #endif @@ -1640,55 +1703,65 @@ beamforming_sw_timer_callback( void phydm_beamforming_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMING_OID_INFO *p_beam_oid_info = &(p_beam_info->beamforming_oid_info); - - p_beam_oid_info->sound_oid_mode = SOUNDING_STOP_OID_TIMER; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s mode (%d)\n", __func__, p_beam_oid_info->sound_oid_mode)); - - p_beam_info->beamformee_su_cnt = 0; - p_beam_info->beamformer_su_cnt = 0; - p_beam_info->beamformee_mu_cnt = 0; - p_beam_info->beamformer_mu_cnt = 0; - p_beam_info->beamformee_mu_reg_maping = 0; - p_beam_info->mu_ap_index = 0; - p_beam_info->is_mu_sounding = false; - p_beam_info->first_mu_bfee_index = 0xFF; - p_beam_info->apply_v_matrix = true; - p_beam_info->snding3ss = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info; + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + #ifdef BEAMFORMING_VERSION_1 + if (hal_data->beamforming_version != BEAMFORMING_VERSION_1) { + return; + } + #endif + #endif + + beam_oid_info->sound_oid_mode = SOUNDING_STOP_OID_TIMER; + PHYDM_DBG(dm, DBG_TXBF, "%s mode (%d)\n", __func__, beam_oid_info->sound_oid_mode); + + beam_info->beamformee_su_cnt = 0; + beam_info->beamformer_su_cnt = 0; + beam_info->beamformee_mu_cnt = 0; + beam_info->beamformer_mu_cnt = 0; + beam_info->beamformee_mu_reg_maping = 0; + beam_info->mu_ap_index = 0; + beam_info->is_mu_sounding = false; + beam_info->first_mu_bfee_index = 0xFF; + beam_info->apply_v_matrix = true; + beam_info->snding3ss = false; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_beam_info->source_adapter = p_dm_odm->adapter; + beam_info->source_adapter = dm->adapter; #endif - hal_com_txbf_beamform_init(p_dm_odm); + hal_com_txbf_beamform_init(dm); } boolean phydm_acting_determine( - void *p_dm_void, + void *dm_void, enum phydm_acting_type type ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; boolean ret = false; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->beamforming_info.source_adapter; + PADAPTER adapter = (PADAPTER)dm->beamforming_info.source_adapter; #else - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _ADAPTER *adapter = dm->adapter; #endif #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) if (type == phydm_acting_as_ap) ret = ACTING_AS_AP(adapter); else if (type == phydm_acting_as_ibss) - ret = ACTING_AS_IBSS(adapter); + ret = ACTING_AS_IBSS(((PADAPTER)(adapter))); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; if (type == phydm_acting_as_ap) ret = check_fwstate(pmlmepriv, WIFI_AP_STATE); @@ -1702,68 +1775,68 @@ phydm_acting_determine( void beamforming_enter( - void *p_dm_void, + void *dm_void, u16 sta_idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 bfer_bfee_idx = 0xff; - if (beamforming_init_entry(p_dm_odm, sta_idx, &bfer_bfee_idx)) - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_ENTER, (u8 *)&bfer_bfee_idx); + if (beamforming_init_entry(dm, sta_idx, &bfer_bfee_idx)) + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_ENTER, (u8 *)&bfer_bfee_idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] End!\n", __func__); } void beamforming_leave( - void *p_dm_void, + void *dm_void, u8 *RA ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (RA != NULL) { - beamforming_deinit_entry(p_dm_odm, RA); - phydm_beamforming_notify(p_dm_odm); + beamforming_deinit_entry(dm, RA); + phydm_beamforming_notify(dm); } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] End!!\n", __func__); } #if 0 /* Nobody calls this function */ void phydm_beamforming_set_txbf_en( - void *p_dm_void, + void *dm_void, u8 mac_id, boolean is_txbf ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 idx = 0; - struct _RT_BEAMFORMEE_ENTRY *p_entry; + struct _RT_BEAMFORMEE_ENTRY *entry; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - p_entry = phydm_beamforming_get_entry_by_mac_id(p_dm_odm, mac_id, &idx); + entry = phydm_beamforming_get_entry_by_mac_id(dm, mac_id, &idx); - if (p_entry == NULL) + if (entry == NULL) return; else - p_entry->is_txbf = is_txbf; + entry->is_txbf = is_txbf; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s mac_id %d TxBF %d\n", __func__, p_entry->mac_id, p_entry->is_txbf)); + PHYDM_DBG(dm, DBG_TXBF, "%s mac_id %d TxBF %d\n", __func__, entry->mac_id, entry->is_txbf); - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); } #endif enum beamforming_cap phydm_beamforming_get_beam_cap( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info ) { u8 i; @@ -1772,26 +1845,26 @@ phydm_beamforming_get_beam_cap( struct _RT_BEAMFORMEE_ENTRY beamformee_entry; struct _RT_BEAMFORMER_ENTRY beamformer_entry; enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - beamformee_entry = p_beam_info->beamformee_entry[i]; + beamformee_entry = beam_info->beamformee_entry[i]; if (beamformee_entry.is_used) { is_self_beamformer = true; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFee entry %d is_used=true\n", __func__, i)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] BFee entry %d is_used=true\n", __func__, i); break; } } for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { - beamformer_entry = p_beam_info->beamformer_entry[i]; + beamformer_entry = beam_info->beamformer_entry[i]; if (beamformer_entry.is_used) { is_self_beamformee = true; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: BFer entry %d is_used=true\n", __func__, i)); + PHYDM_DBG(dm, DBG_TXBF, "[%s]: BFer entry %d is_used=true\n", __func__, i); break; } } @@ -1807,35 +1880,35 @@ phydm_beamforming_get_beam_cap( boolean beamforming_control_v1( - void *p_dm_void, + void *dm_void, u8 *RA, u8 AID, u8 mode, - CHANNEL_WIDTH BW, + enum channel_width BW, u8 rate ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; boolean ret = true; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("AID (%d), mode (%d), BW (%d)\n", AID, mode, BW)); + PHYDM_DBG(dm, DBG_TXBF, "AID (%d), mode (%d), BW (%d)\n", AID, mode, BW); switch (mode) { case 0: - ret = beamforming_start_v1(p_dm_odm, RA, 0, BW, rate); + ret = beamforming_start_v1(dm, RA, 0, BW, rate); break; case 1: - ret = beamforming_start_v1(p_dm_odm, RA, 1, BW, rate); + ret = beamforming_start_v1(dm, RA, 1, BW, rate); break; case 2: - phydm_beamforming_ndpa_rate(p_dm_odm, BW, rate); - ret = beamforming_send_vht_ndpa_packet(p_dm_odm, RA, AID, BW, NORMAL_QUEUE); + phydm_beamforming_ndpa_rate(dm, BW, rate); + ret = beamforming_send_vht_ndpa_packet(dm, RA, AID, BW, NORMAL_QUEUE); break; case 3: - phydm_beamforming_ndpa_rate(p_dm_odm, BW, rate); - ret = beamforming_send_ht_ndpa_packet(p_dm_odm, RA, BW, NORMAL_QUEUE); + phydm_beamforming_ndpa_rate(dm, BW, rate); + ret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE); break; } return ret; @@ -1844,26 +1917,26 @@ beamforming_control_v1( /*Only OID uses this function*/ boolean phydm_beamforming_control_v2( - void *p_dm_void, + void *dm_void, u8 idx, u8 mode, - CHANNEL_WIDTH BW, + enum channel_width BW, u16 period ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMING_OID_INFO *p_beam_oid_info = &(p_beam_info->beamforming_oid_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("idx (%d), mode (%d), BW (%d), period (%d)\n", idx, mode, BW, period)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + PHYDM_DBG(dm, DBG_TXBF, "idx (%d), mode (%d), BW (%d), period (%d)\n", idx, mode, BW, period); - p_beam_oid_info->sound_oid_idx = idx; - p_beam_oid_info->sound_oid_mode = (enum sounding_mode) mode; - p_beam_oid_info->sound_oid_bw = BW; - p_beam_oid_info->sound_oid_period = period; + beam_oid_info->sound_oid_idx = idx; + beam_oid_info->sound_oid_mode = (enum sounding_mode) mode; + beam_oid_info->sound_oid_bw = BW; + beam_oid_info->sound_oid_period = period; - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); return true; } @@ -1871,19 +1944,106 @@ phydm_beamforming_control_v2( void phydm_beamforming_watchdog( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - if (p_beam_info->beamformee_su_cnt == 0) + if (beam_info->beamformee_su_cnt == 0) return; - beamforming_dym_period(p_dm_odm, 0); + beamforming_dym_period(dm, 0); +} +enum beamforming_cap +phydm_get_beamform_cap( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + struct bf_cmn_info *bf_info = NULL; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + void *adapter = dm->adapter; + enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; + u8 macid; + u8 ht_curbeamformcap = 0; + u16 vht_curbeamformcap = 0; + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMGNT_INFO p_MgntInfo = &(((PADAPTER)(adapter))->MgntInfo); + PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo); + PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo); + + ht_curbeamformcap = p_ht_info->HtCurBeamform; + vht_curbeamformcap = p_vht_info->VhtCurBeamform; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s] WIN ht_curcap = %d ; vht_curcap = %d\n", __func__, ht_curbeamformcap, vht_curbeamformcap); + + if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/ + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP)); + + /*We are Beamformer because the STA is Beamformee*/ + if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP)); + + #if (ODM_IC_11AC_SERIES_SUPPORT == 1) + + /* We are Beamformee because the STA is SU Beamformer*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP)); + + /* We are Beamformer because the STA is SU Beamformee*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP)); + + /* We are Beamformee because the STA is MU Beamformer*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP)); + #endif +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + sta = dm->phydm_sta_info[macid]; + + if (!is_sta_active(sta)) + continue; + + bf_info = &sta->bf_info; + vht_curbeamformcap = bf_info->vht_beamform_cap; + ht_curbeamformcap = bf_info->ht_beamform_cap; + + if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/ + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP)); + + /*We are Beamformer because the STA is Beamformee*/ + if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP)); + + #if (ODM_IC_11AC_SERIES_SUPPORT == 1) + /* We are Beamformee because the STA is SU Beamformer*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP)); + + /* We are Beamformer because the STA is SU Beamformee*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP)); + + /* We are Beamformee because the STA is MU Beamformer*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP)); + #endif } + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s] CE ht_curcap = %d ; vht_curcap = %d\n", __func__, ht_curbeamformcap, vht_curbeamformcap); +#endif + +return beamform_cap; + +} #endif diff --git a/hal/phydm/phydm_beamforming.h b/hal/phydm/phydm_beamforming.h index 2d3479b..9537a0a 100644 --- a/hal/phydm/phydm_beamforming.h +++ b/hal/phydm/phydm_beamforming.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,10 +8,21 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ + #ifndef __INC_PHYDM_BEAMFORMING_H #define __INC_PHYDM_BEAMFORMING_H @@ -108,8 +119,8 @@ struct _RT_BEAMFORM_STAINFO { u16 aid; u16 mac_id; u8 my_mac_addr[6]; - WIRELESS_MODE wireless_mode; - CHANNEL_WIDTH bw; + /*WIRELESS_MODE wireless_mode;*/ + enum channel_width bw; enum beamforming_cap beamform_cap; u8 ht_beamform_cap; u16 vht_beamform_cap; @@ -125,10 +136,10 @@ struct _RT_BEAMFORMEE_ENTRY { u16 aid; /*Used to construct AID field of NDPA packet.*/ u16 mac_id; /*Used to Set Reg42C in IBSS mode. */ u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ - u16 g_id; /*Used to fill Tx DESC*/ + u8 g_id; /*Used to fill Tx DESC*/ u8 my_mac_addr[6]; u8 mac_addr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/ - CHANNEL_WIDTH sound_bw; /*Sounding band_width*/ + enum channel_width sound_bw; /*Sounding band_width*/ u16 sound_period; enum beamforming_cap beamform_entry_cap; enum beamforming_entry_state beamform_entry_state; @@ -154,7 +165,7 @@ struct _RT_BEAMFORMER_ENTRY { boolean is_used; /*P_AID of BFer entry is probably not used*/ u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ - u16 g_id; + u8 g_id; u8 my_mac_addr[6]; u8 mac_addr[6]; enum beamforming_cap beamform_entry_cap; @@ -174,7 +185,7 @@ struct _RT_BEAMFORMER_ENTRY { struct _RT_SOUNDING_INFO { u8 sound_idx; - CHANNEL_WIDTH sound_bw; + enum channel_width sound_bw; enum sounding_mode sound_mode; u16 sound_period; }; @@ -183,7 +194,7 @@ struct _RT_SOUNDING_INFO { struct _RT_BEAMFORMING_OID_INFO { u8 sound_oid_idx; - CHANNEL_WIDTH sound_oid_bw; + enum channel_width sound_oid_bw; enum sounding_mode sound_oid_mode; u16 sound_oid_period; }; @@ -195,13 +206,8 @@ struct _RT_BEAMFORMING_INFO { struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM]; struct _RT_BEAMFORM_STAINFO beamform_sta_info; u8 beamformee_cur_idx; - #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) - struct legacy_timer_emu beamforming_timer; - struct legacy_timer_emu mu_timer; - #else - struct timer_list beamforming_timer; - struct timer_list mu_timer;i - #endif + struct phydm_timer_list beamforming_timer; + struct phydm_timer_list mu_timer; struct _RT_SOUNDING_INFO sounding_info; struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info; struct _HAL_TXBF_INFO txbf_info; @@ -222,7 +228,7 @@ struct _RT_BEAMFORMING_INFO { boolean apply_v_matrix; boolean snding3ss; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *source_adapter; + void *source_adapter; #endif /* Control register */ u32 reg_mu_tx_ctrl; /* For USB/SDIO interfaces aync I/O */ @@ -231,6 +237,12 @@ struct _RT_BEAMFORMING_INFO { }; +void +phydm_get_txbf_device_num( + void *dm_void, + u8 macid +); + struct _RT_NDPA_STA_INFO { u16 aid:12; u16 feedback_type:1; @@ -245,113 +257,117 @@ enum phydm_acting_type { enum beamforming_cap phydm_beamforming_get_entry_beam_cap_by_mac_id( - void *p_dm_void, + void *dm_void, u8 mac_id ); struct _RT_BEAMFORMEE_ENTRY * phydm_beamforming_get_bfee_entry_by_addr( - void *p_dm_void, + void *dm_void, u8 *RA, u8 *idx ); struct _RT_BEAMFORMER_ENTRY * phydm_beamforming_get_bfer_entry_by_addr( - void *p_dm_void, + void *dm_void, u8 *TA, u8 *idx ); void phydm_beamforming_notify( - void *p_dm_void + void *dm_void ); boolean phydm_acting_determine( - void *p_dm_void, + void *dm_void, enum phydm_acting_type type ); void beamforming_enter( - void *p_dm_void, + void *dm_void, u16 sta_idx ); void beamforming_leave( - void *p_dm_void, + void *dm_void, u8 *RA ); boolean beamforming_start_fw( - void *p_dm_void, + void *dm_void, u8 idx ); void beamforming_check_sounding_success( - void *p_dm_void, + void *dm_void, boolean status ); void phydm_beamforming_end_sw( - void *p_dm_void, + void *dm_void, boolean status ); void beamforming_timer_callback( - void *p_dm_void + void *dm_void ); void phydm_beamforming_init( - void *p_dm_void + void *dm_void ); enum beamforming_cap phydm_beamforming_get_beam_cap( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info ); +enum beamforming_cap +phydm_get_beamform_cap( + void *dm_void +); boolean beamforming_control_v1( - void *p_dm_void, + void *dm_void, u8 *RA, u8 AID, u8 mode, - CHANNEL_WIDTH BW, + enum channel_width BW, u8 rate ); boolean phydm_beamforming_control_v2( - void *p_dm_void, + void *dm_void, u8 idx, u8 mode, - CHANNEL_WIDTH BW, + enum channel_width BW, u16 period ); void phydm_beamforming_watchdog( - void *p_dm_void + void *dm_void ); void beamforming_sw_timer_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct timer_list *p_timer + struct phydm_timer_list *timer #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) void *function_context #endif @@ -359,36 +375,36 @@ beamforming_sw_timer_callback( boolean beamforming_send_ht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, - CHANNEL_WIDTH BW, + enum channel_width BW, u8 q_idx ); boolean beamforming_send_vht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, u16 AID, - CHANNEL_WIDTH BW, + enum channel_width BW, u8 q_idx ); #else -#define beamforming_gid_paid(adapter, p_tcb) -#define phydm_acting_determine(p_dm_odm, type) false -#define beamforming_enter(p_dm_odm, sta_idx) -#define beamforming_leave(p_dm_odm, RA) -#define beamforming_end_fw(p_dm_odm) -#define beamforming_control_v1(p_dm_odm, RA, AID, mode, BW, rate) true -#define beamforming_control_v2(p_dm_odm, idx, mode, BW, period) true -#define phydm_beamforming_end_sw(p_dm_odm, _status) -#define beamforming_timer_callback(p_dm_odm) -#define phydm_beamforming_init(p_dm_odm) -#define phydm_beamforming_control_v2(p_dm_odm, _idx, _mode, _BW, _period) false -#define beamforming_watchdog(p_dm_odm) -#define phydm_beamforming_watchdog(p_dm_odm) +#define beamforming_gid_paid(adapter, tcb) +#define phydm_acting_determine(dm, type) false +#define beamforming_enter(dm, sta_idx) +#define beamforming_leave(dm, RA) +#define beamforming_end_fw(dm) +#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true +#define beamforming_control_v2(dm, idx, mode, BW, period) true +#define phydm_beamforming_end_sw(dm, _status) +#define beamforming_timer_callback(dm) +#define phydm_beamforming_init(dm) +#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false +#define beamforming_watchdog(dm) +#define phydm_beamforming_watchdog(dm) #endif diff --git a/hal/phydm/phydm_ccx.c b/hal/phydm/phydm_ccx.c index 388a2a4..8335b1d 100644 --- a/hal/phydm/phydm_ccx.c +++ b/hal/phydm/phydm_ccx.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,274 +8,1128 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ + #include "mp_precomp.h" #include "phydm_precomp.h" -/*Set NHM period, threshold, disable ignore cca or not, disable ignore txon or not*/ void -phydm_nhm_counter_statistics_init( - void *p_dm_void +phydm_ccx_hw_restart( + void *dm_void +)/*Will Restart NHM/CLM/FAHM simultaneously*/ +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg1 = (dm->support_ic_type & ODM_IC_11AC_SERIES) ? R_0x994 : R_0x890; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + odm_set_bb_reg(dm, reg1, 0x7, 0x0); /*disable NHM,CLM, FAHM*/ + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x994, BIT(8), 0x0); + odm_set_bb_reg(dm, R_0x994, BIT(8), 0x1); + + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0x890, BIT(8), 0x0); + odm_set_bb_reg(dm, R_0x890, BIT(8), 0x1); + } +} + +#ifdef FAHM_SUPPORT + +u16 +phydm_hw_divider( + void *dm_void, + u16 numerator, + u16 denumerator ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 result = DEVIDER_ERROR; + u32 tmp_u32 = ((numerator << 16) | denumerator); + u32 reg_devider_input; + u32 reg_devider_rpt; + u8 i; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __FUNCTION__); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg_devider_input = 0x1cbc; + reg_devider_rpt = 0x1f98; + } else { + reg_devider_input = 0x980; + reg_devider_rpt = 0x9f0; + } - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - /*PHY parameters initialize for n series*/ - odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11N + 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ - odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/ - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/ - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_FPGA0_IQK_11N, MASKBYTE0, 0xff); /*0xe28[7:0]=0xff th_8*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10) | BIT(9) | BIT(8), 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(7), 0x1); /*0xc0c[7]=1 max power among all RX ants*/ + odm_set_bb_reg(dm, reg_devider_input, MASKDWORD, tmp_u32); + + for (i = 0; i < 10; i++) { + ODM_delay_ms(1); + if (odm_get_bb_reg(dm, reg_devider_rpt, BIT(24))) { /*Chk HW rpt is ready*/ + + result = (u16)odm_get_bb_reg(dm, reg_devider_rpt, MASKBYTE2); + break; + } } -#if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - /*PHY parameters initialize for ac series*/ - odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ - odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/ - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/ - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, 0xff); /*0x9a0[7:0]=0xff th_8*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8) | BIT(9) | BIT(10), 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_9E8_11AC, BIT(0), 0x1); /*0x9e8[7]=1 max power among all RX ants*/ + return result; +} +void +phydm_fahm_trigger( + void *dm_void, + u16 trigger_period /*unit (4us)*/ +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u32 fahm_reg1; + u32 fahm_reg2; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x1cf8, 0xffff00, trigger_period); + + fahm_reg1 = 0x994; + } else { + + odm_set_bb_reg(dm, R_0x978, 0xff000000, (trigger_period & 0xff)); + odm_set_bb_reg(dm, R_0x97c, 0xff, (trigger_period & 0xff00)>>8); + + fahm_reg1 = 0x890; } -#endif + + odm_set_bb_reg(dm, fahm_reg1, BIT(2), 0); + odm_set_bb_reg(dm, fahm_reg1, BIT(2), 1); } void -phydm_nhm_counter_statistics( - void *p_dm_void +phydm_fahm_set_valid_cnt( + void *dm_void, + u8 numerator_sel, + u8 denumerator_sel ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u32 fahm_reg1; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __FUNCTION__); - if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) + if ((ccx_info->fahm_nume_sel == numerator_sel) && + (ccx_info->fahm_denum_sel == denumerator_sel)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "no need to update\n"); return; + } - /*Get NHM report*/ - phydm_get_nhm_counter_statistics(p_dm_odm); + ccx_info->fahm_nume_sel = numerator_sel; + ccx_info->fahm_denum_sel = denumerator_sel; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + fahm_reg1 = 0x994; + } else { + fahm_reg1 = 0x890; + } - /*Reset NHM counter*/ - phydm_nhm_counter_statistics_reset(p_dm_odm); + odm_set_bb_reg(dm, fahm_reg1, 0xe0, numerator_sel); + odm_set_bb_reg(dm, fahm_reg1, 0x7000, denumerator_sel); } void -phydm_get_nhm_counter_statistics( - void *p_dm_void +phydm_fahm_get_result( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 value32 = 0; -#if (RTL8195A_SUPPORT == 0) - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_CNT_11AC, MASKDWORD); - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) -#endif - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_CNT_11N, MASKDWORD); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u16 fahm_rpt_cnt[12]; /*packet count*/ + u16 fahm_rpt[12]; /*percentage*/ + u16 fahm_denumerator; /*packet count*/ + u32 reg_rpt, reg_rpt_2; + u32 reg_val_tmp; + boolean is_ready = false; + u8 i; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __FUNCTION__); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg_rpt = 0x1f80; + reg_rpt_2 = 0x1f98; + } else { + reg_rpt = 0x9d8; + reg_rpt_2 = 0x9f0; + } + + for (i = 0; i < 3; i++) { + + if (odm_get_bb_reg(dm, reg_rpt_2, BIT(31))) { /*Chk HW rpt is ready*/ + + is_ready = true; + break; + } + ODM_delay_ms(1); + } + + if (is_ready == false) + return; - p_dm_odm->nhm_cnt_0 = (u8)(value32 & MASKBYTE0); - p_dm_odm->nhm_cnt_1 = (u8)((value32 & MASKBYTE1) >> 8); + /*Get Denumerator*/ + fahm_denumerator = (u16)odm_get_bb_reg(dm, reg_rpt_2, MASKLWORD); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Reg[0x%x] fahm_denmrtr = %d\n", reg_rpt_2, fahm_denumerator); + + + /*Get nemerator*/ + for (i = 0; i<6; i++) { + reg_val_tmp = odm_get_bb_reg(dm, reg_rpt + (i<<2), MASKDWORD); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "Reg[0x%x] fahm_denmrtr = %d\n", reg_rpt + (i*4), reg_val_tmp); + + fahm_rpt_cnt[i*2] = (u16)(reg_val_tmp & MASKLWORD); + fahm_rpt_cnt[i*2 +1] = (u16)((reg_val_tmp & MASKHWORD)>>16); + } + + for (i = 0; i<12; i++) { + fahm_rpt[i] = phydm_hw_divider(dm, fahm_rpt_cnt[i], fahm_denumerator); + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "FAHM_RPT_cnt[10:0]=[%d, %d, %d, %d, %d(IGI), %d, %d, %d, %d, %d, %d, %d]\n", + fahm_rpt_cnt[11], fahm_rpt_cnt[10], fahm_rpt_cnt[9], + fahm_rpt_cnt[8], fahm_rpt_cnt[7], fahm_rpt_cnt[6], + fahm_rpt_cnt[5], fahm_rpt_cnt[4], fahm_rpt_cnt[3], + fahm_rpt_cnt[2], fahm_rpt_cnt[1], fahm_rpt_cnt[0]); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "FAHM_RPT[10:0]=[%d, %d, %d, %d, %d(IGI), %d, %d, %d, %d, %d, %d, %d]\n", + fahm_rpt[11], fahm_rpt[10], fahm_rpt[9], fahm_rpt[8], + fahm_rpt[7], fahm_rpt[6], + fahm_rpt[5], fahm_rpt[4], fahm_rpt[3], fahm_rpt[2], + fahm_rpt[1], fahm_rpt[0]); + } void -phydm_nhm_counter_statistics_reset( - void *p_dm_void +phydm_fahm_set_th_by_igi( + void *dm_void, + u8 igi ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u8 fahm_th[11]; + u8 rssi_th[11]; /*in RSSI scale*/ + u8 th_gap = 2 * IGI_TO_NHM_TH_MULTIPLIER; /*beacuse unit is 0.5dB for FAHM*/ + u8 i; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __FUNCTION__); - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1); + if (ccx_info->env_mntr_igi == igi) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "No need to update FAHM_th, IGI=0x%x\n", ccx_info->env_mntr_igi); + return; } -#if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1); + + ccx_info->env_mntr_igi = igi; /*bkp IGI*/ + + if (igi >= CCA_CAP) + fahm_th[0] = (igi - CCA_CAP) * IGI_TO_NHM_TH_MULTIPLIER; + else + fahm_th[0] = 0; + + rssi_th[0] = igi -10 - CCA_CAP; + + for (i = 1; i <= 10; i++) { + fahm_th[i] = fahm_th[0] + th_gap * i; + rssi_th[i] = rssi_th[0] + (i<<1); } -#endif + PHYDM_DBG(dm, DBG_ENV_MNTR, + "FAHM_RSSI_th[10:0]=[%d, %d, %d, (IGI)%d, %d, %d, %d, %d, %d, %d, %d]\n", + rssi_th[10], rssi_th[9], rssi_th[8], rssi_th[7], rssi_th[6], + rssi_th[5], rssi_th[4], rssi_th[3], rssi_th[2], rssi_th[1], + rssi_th[0]); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + + odm_set_bb_reg(dm, R_0x1c38, 0xffffff00, ((fahm_th[2]<<24) |(fahm_th[1]<<16) | (fahm_th[0]<<8))); + odm_set_bb_reg(dm, R_0x1c78, 0xffffff00, ((fahm_th[5]<<24) |(fahm_th[4]<<16) | (fahm_th[3]<<8))); + odm_set_bb_reg(dm, R_0x1c7c, 0xffffff00, ((fahm_th[7]<<24) |(fahm_th[6]<<16))); + odm_set_bb_reg(dm, R_0x1cb8, 0xffffff00, ((fahm_th[10]<<24) |(fahm_th[9]<<16) | (fahm_th[8]<<8))); + } else { + odm_set_bb_reg(dm, R_0x970, MASKDWORD, ((fahm_th[3]<<24) |(fahm_th[2]<<16) | (fahm_th[1]<<8) | fahm_th[0])); + odm_set_bb_reg(dm, R_0x974, MASKDWORD, ((fahm_th[7]<<24) |(fahm_th[6]<<16) | (fahm_th[5]<<8) | fahm_th[4])); + odm_set_bb_reg(dm, R_0x978, MASKDWORD, ((fahm_th[10]<<16) | (fahm_th[9]<<8) | fahm_th[8])); + } +} + +void +phydm_fahm_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u32 fahm_reg1; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __FUNCTION__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "IGI=0x%x\n", dm->dm_dig_table.cur_ig_value); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + fahm_reg1 = 0x994; + } else { + fahm_reg1 = 0x890; + } + + ccx_info->fahm_period = 65535; + + odm_set_bb_reg(dm, fahm_reg1, 0x6, 3); /*FAHM HW block enable*/ + + phydm_fahm_set_valid_cnt(dm, FAHM_INCLD_FA, (FAHM_INCLD_FA| FAHM_INCLD_CRC_OK |FAHM_INCLD_CRC_ER)); + phydm_fahm_set_th_by_igi(dm, dm->dm_dig_table.cur_ig_value); +} + +void +phydm_fahm_dbg( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 i; + + for (i = 0; i < 2; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, "{1: trigger, 2:get result}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, "{3: MNTR mode sel} {1: driver, 2. FW}\n"); + return; + } else if (var1[0] == 1) { /* Set & trigger CLM */ + + phydm_fahm_set_th_by_igi(dm, dm->dm_dig_table.cur_ig_value); + phydm_fahm_trigger(dm, ccx_info->fahm_period); + PDM_SNPF(out_len, used, output + used, out_len - used, "Monitor FAHM for %d * 4us\n", + ccx_info->fahm_period); + + } else if (var1[0] == 2) { /* Get CLM results */ + + phydm_fahm_get_result(dm); + PDM_SNPF(out_len, used, output + used, out_len - used,"FAHM_result=%d us\n", + (ccx_info->clm_result<<2)); + + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, "Error\n"); + } + + *_used = used; + *_out_len = out_len; +} + + +#endif /*#ifdef FAHM_SUPPORT*/ + +#ifdef NHM_SUPPORT + +void +phydm_nhm_racing_release( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 value32; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "lv:(%d)->(0)\n", ccx->nhm_set_lv); + + ccx->nhm_ongoing = false; + ccx->nhm_set_lv = NHM_RELEASE; + + if (!((ccx->nhm_app == NHM_BACKGROUND) || (ccx->nhm_app == NHM_ACS))) + phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, 1, &value32); + + ccx->nhm_app = NHM_BACKGROUND; +} + +u8 +phydm_nhm_racing_ctrl( + void *dm_void, + enum phydm_nhm_level nhm_lv +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 set_result = PHYDM_SET_SUCCESS; + /*acquire to control NHM API*/ + + PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_ongoing=%d, lv:(%d)->(%d)\n", + ccx->nhm_ongoing, ccx->nhm_set_lv, nhm_lv); + if (ccx->nhm_ongoing) { + if (nhm_lv <= ccx->nhm_set_lv) { + set_result = PHYDM_SET_FAIL; + } else { + phydm_ccx_hw_restart(dm); + ccx->nhm_ongoing = false; + } + } + + if (set_result) + ccx->nhm_set_lv = nhm_lv; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm racing success=%d\n", set_result); + return set_result; +} + + +void +phydm_nhm_trigger( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 nhm_reg1 = (dm->support_ic_type & ODM_IC_11AC_SERIES) ? 0x994 : 0x890; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + /*Trigger NHM*/ + pdm_set_reg(dm, nhm_reg1, BIT(1), 0); + pdm_set_reg(dm, nhm_reg1, BIT(1), 1); + ccx->nhm_trigger_time = dm->phydm_sys_up_time; + ccx->nhm_rpt_stamp++; + ccx->nhm_ongoing = true; +} + +boolean +phydm_nhm_check_rdy( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean is_ready = false; + u32 reg1 = 0, reg1_bit = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg1 = 0xfb4; + reg1_bit = 16; + } else { + reg1 = 0x8b4; + if (dm->support_ic_type == ODM_RTL8710B) { + reg1_bit = 25; + } else { + reg1_bit = 17; + } + } + + if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) + is_ready = true; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d\n", is_ready); + return is_ready; +} + +void +phydm_nhm_get_utility( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + if (ccx->nhm_rpt_sum >= ccx->nhm_result[0]) + ccx->nhm_ratio = (u8)(((ccx->nhm_rpt_sum - ccx->nhm_result[0]) * 100) >> 8); + else { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] nhm_rpt_sum invalid\n"); + ccx->nhm_ratio = 0; + } + PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_ratio=%d\n", ccx->nhm_ratio); } boolean -phydm_cal_nhm_cnt( - void *p_dm_void +phydm_nhm_get_result( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u16 base = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 value32; + u8 i; + u32 nhm_reg1 = (dm->support_ic_type & ODM_IC_11AC_SERIES) ? 0x994 : 0x890; + u16 nhm_rpt_sum_tmp = 0; - base = p_dm_odm->nhm_cnt_0 + p_dm_odm->nhm_cnt_1; + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + pdm_set_reg(dm, nhm_reg1, BIT(1), 0); - if (base != 0) { - p_dm_odm->nhm_cnt_0 = ((p_dm_odm->nhm_cnt_0) << 8) / base; - p_dm_odm->nhm_cnt_1 = ((p_dm_odm->nhm_cnt_1) << 8) / base; + if (phydm_nhm_check_rdy(dm) == false) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM report Fail\n"); + phydm_nhm_racing_release(dm); + return false; } - if ((p_dm_odm->nhm_cnt_0 - p_dm_odm->nhm_cnt_1) >= 100) - return true; /*clean environment*/ + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + value32 = odm_read_4byte(dm, 0xfa8); + odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4); + + value32 = odm_read_4byte(dm, 0xfac); + odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4); + + value32 = odm_read_4byte(dm, 0xfb0); + odm_move_memory(dm, &ccx->nhm_result[8], &value32, 4); + + /*Get NHM duration*/ + value32 = odm_read_4byte(dm, 0xfb4); + ccx->nhm_duration = (u16)(value32 & MASKLWORD); + } else { + value32 = odm_read_4byte(dm, 0x8d8); + odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4); + + value32 = odm_read_4byte(dm, 0x8dc); + odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4); + + value32 = odm_get_bb_reg(dm, R_0x8d0, 0xffff0000); + odm_move_memory(dm, &ccx->nhm_result[8], &value32, 2); + + value32 = odm_read_4byte(dm, 0x8d4); + /*odm_move_memory(dm, &ccx->nhm_result[10], (&value32 + 2), 2);*/ + ccx->nhm_result[10] = (u8)((value32 & MASKBYTE2) >> 16); + ccx->nhm_result[11] = (u8)((value32 & MASKBYTE3) >> 24); + + /*Get NHM duration*/ + ccx->nhm_duration = (u16)(value32 & MASKLWORD); + } + + /* sum all nhm_result */ + if (ccx->nhm_period >= 65530) { + value32 = (ccx->nhm_duration * 100) >> 16; + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM valid time = %d, valid: %d percent\n", ccx->nhm_duration, value32); + } + + for (i = 0; i < NHM_RPT_NUM; i++) + nhm_rpt_sum_tmp += (u16)ccx->nhm_result[i]; + + ccx->nhm_rpt_sum = (u8)nhm_rpt_sum_tmp; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM_Rpt[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n", + ccx->nhm_rpt_stamp, + ccx->nhm_result[11], ccx->nhm_result[10], ccx->nhm_result[9], + ccx->nhm_result[8], ccx->nhm_result[7], ccx->nhm_result[6], + ccx->nhm_result[5], ccx->nhm_result[4], ccx->nhm_result[3], + ccx->nhm_result[2], ccx->nhm_result[1], ccx->nhm_result[0]); + + phydm_nhm_racing_release(dm); + + if (nhm_rpt_sum_tmp > 255) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[Warning] Invalid NHM RPT, total=%d\n", + nhm_rpt_sum_tmp); + return false; + } + + return true; +} + +void +phydm_nhm_set_th_reg( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 reg1 = 0, reg2 = 0, reg3 = 0, reg4 = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg1 = 0x994; + reg2 = 0x998; + reg3 = 0x99c; + reg4 = 0x9a0; + } else { + reg1 = 0x890; + reg2 = 0x898; + reg3 = 0x89c; + reg4 = 0xe28; + } + + /*Set NHM threshold*/ /*Unit: PWdB U(8,1)*/ + pdm_set_reg(dm, reg2, MASKDWORD, BYTE_2_DWORD(ccx->nhm_th[3], ccx->nhm_th[2], ccx->nhm_th[1], ccx->nhm_th[0])); + pdm_set_reg(dm, reg3, MASKDWORD, BYTE_2_DWORD(ccx->nhm_th[7], ccx->nhm_th[6], ccx->nhm_th[5], ccx->nhm_th[4])); + pdm_set_reg(dm, reg4, MASKBYTE0, ccx->nhm_th[8]); + pdm_set_reg(dm, reg1, 0xffff0000, BYTE_2_DWORD(0, 0, ccx->nhm_th[10], ccx->nhm_th[9])); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "Update NHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\n", + ccx->nhm_th[10], ccx->nhm_th[9], ccx->nhm_th[8],ccx->nhm_th[7], + ccx->nhm_th[6], ccx->nhm_th[5],ccx->nhm_th[4], ccx->nhm_th[3], + ccx->nhm_th[2], ccx->nhm_th[1], ccx->nhm_th[0]); +} + +boolean +phydm_nhm_th_update_chk( + void *dm_void, + enum nhm_application nhm_app, + u8 *nhm_th, + u32 *igi_new +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean is_update = false; + u8 igi_curr = dm->dm_dig_table.cur_ig_value; + u8 nhm_igi_th_11k_low[NHM_TH_NUM] = {0x12, 0x15, 0x18, 0x1b, 0x1e, 0x23, 0x28, 0x2c, 0x78, 0x78, 0x78}; + u8 nhm_igi_th_11k_high[NHM_TH_NUM] = {0x1e, 0x23, 0x28, 0x2d, 0x32, 0x37, 0x78, 0x78, 0x78, 0x78, 0x78}; + u8 nhm_igi_th_xbox[NHM_TH_NUM] = {0x1a, 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3d}; + u8 i; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "App=%d, nhm_igi=0x%x, igi_curr=0x%x\n", nhm_app, ccx->nhm_igi, igi_curr); + + if (igi_curr < 0x10)/* Protect for invalid IGI*/ + return false; + + switch (nhm_app) { + + case NHM_BACKGROUND: /*Get IGI form driver parameter(cur_ig_value)*/ + case NHM_ACS: + if ((ccx->nhm_igi != igi_curr) || (ccx->nhm_app != nhm_app)) { + is_update = true; + *igi_new = (u32)igi_curr; + nhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP); + for (i = 1; i <= 10; i++) + nhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(2 * i); + } + break; + + case IEEE_11K_HIGH: + is_update = true; + *igi_new = 0x2c; + for (i = 0; i < NHM_TH_NUM; i++) + nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_high[i]); + break; + + case IEEE_11K_LOW: + is_update = true; + *igi_new = 0x20; + for (i = 0; i < NHM_TH_NUM; i++) + nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_low[i]); + break; + + case INTEL_XBOX: + is_update = true; + *igi_new = 0x36; + for (i = 0; i < NHM_TH_NUM; i++) + nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_xbox[i]); + break; + + case NHM_DBG: /*Get IGI form register*/ + igi_curr = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0); + if ((ccx->nhm_igi != igi_curr) || (ccx->nhm_app != nhm_app)) { + is_update = true; + *igi_new = (u32)igi_curr; + nhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP); + for (i = 1; i <= 10; i++) + nhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(2 * i); + } + break; + } + + if (is_update) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[Update NHM_TH] igi_RSSI=%d\n", + IGI_2_RSSI(*igi_new)); + + for (i = 0; i < NHM_TH_NUM; i++) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM_th[%d](RSSI) = %d\n", + i, NTH_TH_2_RSSI(nhm_th[i])); + } + } else { + PHYDM_DBG(dm, DBG_ENV_MNTR, "No need to update NHM_TH\n"); + } + return is_update; +} + +void +phydm_nhm_set( + void *dm_void, + enum nhm_inexclude_txon_all include_tx, + enum nhm_inexclude_cca_all include_cca, + enum nhm_divider_opt_all divi_opt, + enum nhm_application nhm_app, + u16 period +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 nhm_th[NHM_TH_NUM] = {0}; + u8 i = 0; + u32 igi = 0x20; + u32 reg1 = 0, reg2 = 0; + u32 val_tmp = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "incld{tx, cca}={%d, %d}, divi_opt=%d, period=%d\n", + include_tx, include_cca, divi_opt, period); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg1 = 0x994; + reg2 = 0x990; + } else { + reg1 = 0x890; + reg2 = 0x894; + } + + /*Set disable_ignore_cca, disable_ignore_txon, ccx_en*/ + if ((include_tx != ccx->nhm_include_txon) || + (include_cca != ccx->nhm_include_cca) || + (divi_opt != ccx->nhm_divider_opt)) { + + val_tmp = (u32)BIT_2_BYTE(divi_opt, include_tx, include_cca, 1); + pdm_set_reg(dm, reg1, 0xf00, val_tmp); + + ccx->nhm_include_txon = include_tx; + ccx->nhm_include_cca = include_cca; + ccx->nhm_divider_opt = divi_opt; + /* + PHYDM_DBG(dm, DBG_ENV_MNTR, "val_tmp=%d, incld{tx, cca}={%d, %d}, divi_opt=%d, period=%d\n", + val_tmp, include_tx, include_cca, divi_opt, period); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "0x994=0x%x\n", odm_get_bb_reg(dm, 0x994, 0xf00)); + */ + + } + + /*Set NHM period*/ + if (period != ccx->nhm_period) { + pdm_set_reg(dm, reg2, MASKHWORD, period); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Update NHM period ((%d)) -> ((%d))\n", + ccx->nhm_period, period); + + ccx->nhm_period = period; + } + + /*Set NHM threshold*/ + if (phydm_nhm_th_update_chk(dm, nhm_app, &(nhm_th[0]), &igi)) { + + /*Pause IGI*/ + if ((nhm_app == NHM_BACKGROUND) || (nhm_app == NHM_ACS)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "DIG Free Run\n"); + } else if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, 1, &igi) == PAUSE_FAIL) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG Fail\n"); + return; + } else { + PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG=0x%x\n", igi); + } + ccx->nhm_app = nhm_app; + ccx->nhm_igi = (u8)igi; + odm_move_memory(dm, &ccx->nhm_th[0], &nhm_th, NHM_TH_NUM); + + /*Set NHM th*/ + phydm_nhm_set_th_reg(dm); + } +} + +u8 +phydm_nhm_mntr_set( + void *dm_void, + struct nhm_para_info *nhm_para +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 nhm_time = 0; /*unit: 4us*/ + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (nhm_para->mntr_time == 0) + return PHYDM_SET_FAIL; + + if (nhm_para->nhm_lv >= NHM_MAX_NUM) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Wrong LV=%d\n", nhm_para->nhm_lv); + return PHYDM_SET_FAIL; + } + + if (phydm_nhm_racing_ctrl(dm, nhm_para->nhm_lv) == PHYDM_SET_FAIL) + return PHYDM_SET_FAIL; + + if (nhm_para->mntr_time >= 262) + nhm_time = NHM_PERIOD_MAX; else - return false; /*noisy environment*/ + nhm_time = nhm_para->mntr_time * MS_TO_4US_RATIO; + + phydm_nhm_set(dm, nhm_para->incld_txon, nhm_para->incld_cca, nhm_para->div_opt, nhm_para->nhm_app, nhm_time); + + return PHYDM_SET_SUCCESS; +} + +/*Environment Monitor*/ +boolean +phydm_nhm_mntr_chk( + void *dm_void, + u16 monitor_time /*unit ms*/ +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct nhm_para_info nhm_para = {0}; + boolean nhm_chk_result = false; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (ccx->nhm_manual_ctrl) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM in manual ctrl\n"); + return nhm_chk_result; + } + + if (ccx->nhm_app != NHM_BACKGROUND && + ((ccx->nhm_trigger_time + MAX_ENV_MNTR_TIME) > dm->phydm_sys_up_time)) { + + PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_app=%d, trigger_time %d, sys_time=%d\n", + ccx->nhm_app, ccx->nhm_trigger_time, dm->phydm_sys_up_time); + + return nhm_chk_result; + } + + /*[NHM get result & calculate Utility----------------------------*/ + if (phydm_nhm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n"); + phydm_nhm_get_utility(dm); + } + + /*[NHM trigger]-------------------------------------------------*/ + nhm_para.incld_txon = NHM_EXCLUDE_TXON; + nhm_para.incld_cca = NHM_EXCLUDE_CCA; + nhm_para.div_opt = NHM_CNT_ALL; + nhm_para.nhm_app = NHM_BACKGROUND; + nhm_para.nhm_lv = NHM_LV_1; + nhm_para.mntr_time = monitor_time; + + nhm_chk_result = phydm_nhm_mntr_set(dm, &nhm_para); + + return nhm_chk_result; +} + +void +phydm_nhm_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __FUNCTION__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "cur_igi=0x%x\n", dm->dm_dig_table.cur_ig_value); + + ccx->nhm_app = NHM_BACKGROUND; + ccx->nhm_igi = 0xff; + + /*Set NHM threshold*/ + ccx->nhm_ongoing = false; + ccx->nhm_set_lv = NHM_RELEASE; + + if (phydm_nhm_th_update_chk(dm, ccx->nhm_app, &(ccx->nhm_th[0]), (u32*)(&ccx->nhm_igi))) { + phydm_nhm_set_th_reg(dm); + } + ccx->nhm_period = 0; + + ccx->nhm_include_cca = NHM_CCA_INIT; + ccx->nhm_include_txon = NHM_TXON_INIT; + ccx->nhm_divider_opt = NHM_CNT_INIT; + + ccx->nhm_manual_ctrl = 0; + ccx->nhm_rpt_stamp = 0; +} + +void +phydm_nhm_dbg( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct nhm_para_info nhm_para; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + boolean nhm_rpt_success = true; + u8 i; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, "NHM Basic-Trigger 262ms: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, "NHM Adv-Trigger: {2} {Include TXON} {Include CCA}\n{0:Cnt_all, 1:Cnt valid} {App} {LV} {0~262ms}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, "NHM Get Result: {100}\n"); + } else if (var1[0] == 100) { /*Get NHM results*/ + + PDM_SNPF(out_len, used, output + used, out_len - used, "IGI=0x%x, rpt_stamp=%d\n", ccx->nhm_igi, ccx->nhm_rpt_stamp); + + nhm_rpt_success = phydm_nhm_get_result(dm); + + if (nhm_rpt_success) { + for (i = 0; i <= 11; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, "nhm_rpt[%d] = %d (%d percent)\n", + i, ccx->nhm_result[i], + (((ccx->nhm_result[i] * 100) + 128) >> 8)); + } + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, "Get NHM_rpt Fail\n"); + } + ccx->nhm_manual_ctrl = 0; + + } else { /* NMH trigger */ + + ccx->nhm_manual_ctrl = 1; + + if (var1[0] == 1) { + nhm_para.incld_txon = NHM_EXCLUDE_TXON; + nhm_para.incld_cca = NHM_EXCLUDE_CCA; + nhm_para.div_opt = NHM_CNT_ALL; + nhm_para.nhm_app = NHM_DBG; + nhm_para.nhm_lv = NHM_LV_4; + nhm_para.mntr_time = 262; + } else { + for (i = 1; i < 7; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + } + nhm_para.incld_txon = (enum nhm_inexclude_txon_all)var1[1]; + nhm_para.incld_cca = (enum nhm_inexclude_cca_all)var1[2]; + nhm_para.div_opt = (enum nhm_divider_opt_all)var1[3]; + nhm_para.nhm_app = (enum nhm_application)var1[4]; + nhm_para.nhm_lv = (enum phydm_nhm_level)var1[5]; + nhm_para.mntr_time = (u16)var1[6]; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, " txon=%d, cca=%d, dev=%d, app=%d, lv=%d, time=%d ms\n", + nhm_para.incld_txon, nhm_para.incld_cca, + nhm_para.div_opt, nhm_para.nhm_app, nhm_para.nhm_lv, + nhm_para.mntr_time); + + if (phydm_nhm_mntr_set(dm, &nhm_para) == PHYDM_SET_SUCCESS) { + phydm_nhm_trigger(dm); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, "IGI=0x%x, rpt_stamp=%d\n", + ccx->nhm_igi, ccx->nhm_rpt_stamp); + + for (i = 0; i <= 10; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, "NHM_th[%d] RSSI = %d\n", + i, NTH_TH_2_RSSI(ccx->nhm_th[i])); + } + } + + *_used = used; + *_out_len = out_len; } +#endif /*#ifdef NHM_SUPPORT*/ + +#if 1 + +void +phydm_set_nhm_th_by_igi( + void *dm_void, + u8 igi +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u8 th_gap = 2 * IGI_TO_NHM_TH_MULTIPLIER; + u8 i; + + ccx_info->echo_igi = igi; + ccx_info->nhm_th[0] = (ccx_info->echo_igi - CCA_CAP) * IGI_TO_NHM_TH_MULTIPLIER; + for (i = 1; i <= 10; i++) + ccx_info->nhm_th[i] = ccx_info->nhm_th[0] + th_gap * i; +} + + void phydm_nhm_setting( - void *p_dm_void, + void *dm_void, u8 nhm_setting ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __FUNCTION__); + + + PHYDM_DBG(dm, DBG_ENV_MNTR, "IGI=0x%x\n", ccx_info->echo_igi); + + if (nhm_setting == SET_NHM_SETTING) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "NHM_th[H->L]=[0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x]\n", + ccx_info->nhm_th[10], ccx_info->nhm_th[9], ccx_info->nhm_th[8], + ccx_info->nhm_th[7], ccx_info->nhm_th[6], ccx_info->nhm_th[5], + ccx_info->nhm_th[4], ccx_info->nhm_th[3], ccx_info->nhm_th[2], + ccx_info->nhm_th[1], ccx_info->nhm_th[0]); + } + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { if (nhm_setting == SET_NHM_SETTING) { - /*Set inexclude_cca, inexclude_txon*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->nhm_inexclude_cca); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->nhm_inexclude_txon); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->nhm_include_cca); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->nhm_include_txon); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(11), ccx_info->nhm_divider_opt); /*Set NHM period*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->NHM_period); - - /*Set NHM threshold*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->NHM_th[0]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->NHM_th[1]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->NHM_th[2]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->NHM_th[3]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->NHM_th[4]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->NHM_th[5]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->NHM_th[6]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->NHM_th[7]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->NHM_th[8]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->NHM_th[9]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->NHM_th[10]); + odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->nhm_period); + + /*Set NHM threshold*/ /*Unit: PWdB U(8,1)*/ + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->nhm_th[0]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->nhm_th[1]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->nhm_th[2]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->nhm_th[3]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->nhm_th[4]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->nhm_th[5]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->nhm_th[6]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->nhm_th[7]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->nhm_th[8]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->nhm_th[9]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->nhm_th[10]); /*CCX EN*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8), CCX_EN); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8), CCX_EN); } else if (nhm_setting == STORE_NHM_SETTING) { - /*Store pervious disable_ignore_cca, disable_ignore_txon*/ - ccx_info->NHM_inexclude_cca_restore = (enum nhm_inexclude_cca)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9)); - ccx_info->NHM_inexclude_txon_restore = (enum nhm_inexclude_txon)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10)); + ccx_info->nhm_inexclude_cca_restore = (enum nhm_inexclude_cca_all)odm_get_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9)); + ccx_info->nhm_inexclude_txon_restore = (enum nhm_inexclude_txon_all)odm_get_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10)); /*Store pervious NHM period*/ - ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD); + ccx_info->nhm_period_restore = (u16)odm_get_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD); /*Store NHM threshold*/ - ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0); - ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1); - ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2); - ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3); - ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0); - ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1); - ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2); - ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3); - ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0); - ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2); - ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3); + ccx_info->nhm_th_restore[0] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0); + ccx_info->nhm_th_restore[1] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1); + ccx_info->nhm_th_restore[2] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2); + ccx_info->nhm_th_restore[3] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3); + ccx_info->nhm_th_restore[4] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0); + ccx_info->nhm_th_restore[5] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1); + ccx_info->nhm_th_restore[6] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2); + ccx_info->nhm_th_restore[7] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3); + ccx_info->nhm_th_restore[8] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0); + ccx_info->nhm_th_restore[9] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2); + ccx_info->nhm_th_restore[10] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3); } else if (nhm_setting == RESTORE_NHM_SETTING) { - /*Set disable_ignore_cca, disable_ignore_txon*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->NHM_inexclude_cca_restore); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->NHM_inexclude_txon_restore); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->nhm_inexclude_cca_restore); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->nhm_inexclude_txon_restore); /*Set NHM period*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->NHM_period); + odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->nhm_period); /*Set NHM threshold*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->NHM_th_restore[0]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->NHM_th_restore[1]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->NHM_th_restore[2]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->NHM_th_restore[3]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->NHM_th_restore[4]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->NHM_th_restore[5]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->NHM_th_restore[6]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->NHM_th_restore[7]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->NHM_th_restore[8]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->NHM_th_restore[9]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->NHM_th_restore[10]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->nhm_th_restore[0]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->nhm_th_restore[1]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->nhm_th_restore[2]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->nhm_th_restore[3]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->nhm_th_restore[4]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->nhm_th_restore[5]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->nhm_th_restore[6]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->nhm_th_restore[7]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->nhm_th_restore[8]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->nhm_th_restore[9]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->nhm_th_restore[10]); } else return; } - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - + else if (dm->support_ic_type & ODM_IC_11N_SERIES) { if (nhm_setting == SET_NHM_SETTING) { - /*Set disable_ignore_cca, disable_ignore_txon*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->nhm_inexclude_cca); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->nhm_inexclude_txon); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->nhm_include_cca); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->nhm_include_txon); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(11), ccx_info->nhm_divider_opt); /*Set NHM period*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->NHM_period); + odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->nhm_period); /*Set NHM threshold*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->NHM_th[0]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->NHM_th[1]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->NHM_th[2]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->NHM_th[3]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->NHM_th[4]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->NHM_th[5]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->NHM_th[6]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->NHM_th[7]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->NHM_th[8]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->NHM_th[9]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->NHM_th[10]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->nhm_th[0]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->nhm_th[1]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->nhm_th[2]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->nhm_th[3]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->nhm_th[4]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->nhm_th[5]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->nhm_th[6]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->nhm_th[7]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->nhm_th[8]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->nhm_th[9]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->nhm_th[10]); /*CCX EN*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(8), CCX_EN); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(8), CCX_EN); } else if (nhm_setting == STORE_NHM_SETTING) { - /*Store pervious disable_ignore_cca, disable_ignore_txon*/ - ccx_info->NHM_inexclude_cca_restore = (enum nhm_inexclude_cca)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9)); - ccx_info->NHM_inexclude_txon_restore = (enum nhm_inexclude_txon)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10)); + ccx_info->nhm_inexclude_cca_restore = (enum nhm_inexclude_cca_all)odm_get_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9)); + ccx_info->nhm_inexclude_txon_restore = (enum nhm_inexclude_txon_all)odm_get_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10)); /*Store pervious NHM period*/ - ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD); + ccx_info->nhm_period_restore = (u16)odm_get_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD); /*Store NHM threshold*/ - ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0); - ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1); - ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2); - ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3); - ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0); - ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1); - ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2); - ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3); - ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0); - ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2); - ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3); + ccx_info->nhm_th_restore[0] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0); + ccx_info->nhm_th_restore[1] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1); + ccx_info->nhm_th_restore[2] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2); + ccx_info->nhm_th_restore[3] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3); + ccx_info->nhm_th_restore[4] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0); + ccx_info->nhm_th_restore[5] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1); + ccx_info->nhm_th_restore[6] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2); + ccx_info->nhm_th_restore[7] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3); + ccx_info->nhm_th_restore[8] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0); + ccx_info->nhm_th_restore[9] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2); + ccx_info->nhm_th_restore[10] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3); } else if (nhm_setting == RESTORE_NHM_SETTING) { - /*Set disable_ignore_cca, disable_ignore_txon*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->NHM_inexclude_cca_restore); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->NHM_inexclude_txon_restore); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->nhm_inexclude_cca_restore); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->nhm_inexclude_txon_restore); /*Set NHM period*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->NHM_period_restore); + odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->nhm_period_restore); /*Set NHM threshold*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->NHM_th_restore[0]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->NHM_th_restore[1]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->NHM_th_restore[2]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->NHM_th_restore[3]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->NHM_th_restore[4]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->NHM_th_restore[5]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->NHM_th_restore[6]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->NHM_th_restore[7]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->NHM_th_restore[8]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->NHM_th_restore[9]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->NHM_th_restore[10]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->nhm_th_restore[0]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->nhm_th_restore[1]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->nhm_th_restore[2]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->nhm_th_restore[3]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->nhm_th_restore[4]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->nhm_th_restore[5]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->nhm_th_restore[6]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->nhm_th_restore[7]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->nhm_th_restore[8]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->nhm_th_restore[9]); + odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->nhm_th_restore[10]); } else return; @@ -283,230 +1137,945 @@ phydm_nhm_setting( } void -phydm_nhm_trigger( - void *p_dm_void +phydm_get_nhm_result( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u32 value32; + u8 i; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11AC); + ccx_info->nhm_result[0] = (u8)(value32 & MASKBYTE0); + ccx_info->nhm_result[1] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->nhm_result[2] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->nhm_result[3] = (u8)((value32 & MASKBYTE3) >> 24); + + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); + ccx_info->nhm_result[4] = (u8)(value32 & MASKBYTE0); + ccx_info->nhm_result[5] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->nhm_result[6] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->nhm_result[7] = (u8)((value32 & MASKBYTE3) >> 24); + + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT11_TO_CNT8_11AC); + ccx_info->nhm_result[8] = (u8)(value32 & MASKBYTE0); + ccx_info->nhm_result[9] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->nhm_result[10] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->nhm_result[11] = (u8)((value32 & MASKBYTE3) >> 24); - /*Trigger NHM*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1); - } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + /*Get NHM duration*/ + value32 = odm_read_4byte(dm, ODM_REG_NHM_DUR_READY_11AC); + ccx_info->nhm_duration = (u16)(value32 & MASKLWORD); - /*Trigger NHM*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1); } -} -void -phydm_get_nhm_result( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 value32; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11N); + ccx_info->nhm_result[0] = (u8)(value32 & MASKBYTE0); + ccx_info->nhm_result[1] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->nhm_result[2] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->nhm_result[3] = (u8)((value32 & MASKBYTE3) >> 24); - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11AC); - ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0); - ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8); - ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24); + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11N); + ccx_info->nhm_result[4] = (u8)(value32 & MASKBYTE0); + ccx_info->nhm_result[5] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->nhm_result[6] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->nhm_result[7] = (u8)((value32 & MASKBYTE3) >> 24); - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); - ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0); - ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8); - ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24); + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT9_TO_CNT8_11N); + ccx_info->nhm_result[8] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->nhm_result[9] = (u8)((value32 & MASKBYTE3) >> 24); - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT11_TO_CNT8_11AC); - ccx_info->NHM_result[8] = (u8)(value32 & MASKBYTE0); - ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE1) >> 8); - ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24); + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N); + ccx_info->nhm_result[10] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->nhm_result[11] = (u8)((value32 & MASKBYTE3) >> 24); /*Get NHM duration*/ - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC); - ccx_info->NHM_duration = (u16)(value32 & MASKLWORD); + value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N); + ccx_info->nhm_duration = (u16)(value32 & MASKLWORD); } - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + /* sum all nhm_result */ + ccx_info->nhm_rpt_sum = 0; + for (i = 0; i <= 11; i++) + ccx_info->nhm_rpt_sum += ccx_info->nhm_result[i]; - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11N); - ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0); - ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8); - ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "NHM_result=(H->L)[%d %d %d %d (igi) %d %d %d %d %d %d %d %d]\n", + ccx_info->nhm_result[11], ccx_info->nhm_result[10], ccx_info->nhm_result[9], + ccx_info->nhm_result[8], ccx_info->nhm_result[7], ccx_info->nhm_result[6], + ccx_info->nhm_result[5], ccx_info->nhm_result[4], ccx_info->nhm_result[3], + ccx_info->nhm_result[2], ccx_info->nhm_result[1], ccx_info->nhm_result[0]); + +} + +boolean +phydm_check_nhm_rdy( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i; + boolean is_ready = false; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC, BIT(16))) + is_ready = 1; + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + + if (dm->support_ic_type == ODM_RTL8710B) { + if (odm_get_bb_reg(dm, R_0x8b4, BIT(25))) + is_ready = 1; + } else { + if (odm_get_bb_reg(dm, R_0x8b4, BIT(17))) + is_ready = 1; + } + } + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d\n", is_ready); + return is_ready; +} - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); - ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0); - ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8); - ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24); +void +phydm_ccx_monitor_trigger( + void *dm_void, + u16 monitor_time /*unit ms*/ +) +{ + u8 nhm_th[11], i, igi; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u16 monitor_time_4us = 0; - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT9_TO_CNT8_11N); - ccx_info->NHM_result[8] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE3) >> 24); + if (!(dm->support_ability & ODM_BB_ENV_MONITOR)) + return; - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); - ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24); + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __FUNCTION__); - /*Get NHM duration*/ - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); - ccx_info->NHM_duration = (u16)(value32 & MASKLWORD); + if (monitor_time == 0) + return; + if (monitor_time >= 262) + monitor_time_4us = 65534; + else + monitor_time_4us = monitor_time * MS_TO_4US_RATIO; + + /* check if NHM threshold is changed */ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + + nhm_th[0] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0); + nhm_th[1] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1); + nhm_th[2] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2); + nhm_th[3] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3); + nhm_th[4] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0); + nhm_th[5] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1); + nhm_th[6] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2); + nhm_th[7] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3); + nhm_th[8] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0); + nhm_th[9] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2); + nhm_th[10] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3); + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + + nhm_th[0] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0); + nhm_th[1] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1); + nhm_th[2] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2); + nhm_th[3] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3); + nhm_th[4] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0); + nhm_th[5] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1); + nhm_th[6] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2); + nhm_th[7] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3); + nhm_th[8] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0); + nhm_th[9] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2); + nhm_th[10] = (u8)odm_get_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3); + } + + for (i = 0; i <= 10; i++) { + + if (nhm_th[i] != ccx_info->nhm_th[i]) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "nhm_th[%d] != ccx_info->nhm_th[%d]!!\n", i, i); + } + } + /*[NHM]*/ + igi = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0); + phydm_set_nhm_th_by_igi(dm, igi); + + ccx_info->nhm_period = monitor_time_4us; + ccx_info->nhm_include_cca = NHM_EXCLUDE_CCA; + ccx_info->nhm_include_txon = NHM_EXCLUDE_TXON; + ccx_info->nhm_divider_opt = NHM_CNT_ALL; + + phydm_nhm_setting(dm, SET_NHM_SETTING); + phydm_nhm_trigger(dm); + + /*[CLM]*/ + ccx_info->clm_period = monitor_time_4us; + + if (ccx_info->clm_mntr_mode == CLM_DRIVER_MNTR) { + phydm_clm_setting(dm, ccx_info->clm_period); + phydm_clm_trigger(dm); + } else if (ccx_info->clm_mntr_mode == CLM_FW_MNTR){ + phydm_clm_h2c(dm, monitor_time_4us, true); } } -boolean -phydm_check_nhm_ready( - void *p_dm_void +void +phydm_ccx_monitor_result( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 value32 = 0; - u8 i; - boolean ret = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u32 clm_result_tmp = 0; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (!(dm->support_ability & ODM_BB_ENV_MONITOR)) + return; - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); + PHYDM_DBG(dm, DBG_ENV_MNTR, "%s ======>\n", __func__); - for (i = 0; i < 200; i++) { + if (phydm_check_nhm_rdy(dm)) { + phydm_get_nhm_result(dm); - ODM_delay_ms(1); - if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(17))) { - ret = 1; - break; - } + if (ccx_info->nhm_rpt_sum != 0) + ccx_info->nhm_ratio = (u8)(((ccx_info->nhm_rpt_sum - ccx_info->nhm_result[0])*100) >> 8); + } + + if (ccx_info->clm_mntr_mode == CLM_DRIVER_MNTR) { + + if (!phydm_clm_check_rdy(dm)) + goto out; + + phydm_clm_get_result(dm); + + if (ccx_info->clm_period != 0) { + if (ccx_info->clm_period == 64000) + ccx_info->clm_ratio = (u8)(((ccx_info->clm_result >> 6) + 5) /10); + else if (ccx_info->clm_period == 65535) { + clm_result_tmp = (u32)(ccx_info->clm_result * 100); + ccx_info->clm_ratio = (u8)((clm_result_tmp + (1<<15)) >> 16); + } else + ccx_info->clm_ratio = (u8)((ccx_info->clm_result*100) / ccx_info->clm_period); } + + } else { + if (ccx_info->clm_fw_result_cnt != 0) + ccx_info->clm_ratio = (u8)(ccx_info->clm_fw_result_acc /ccx_info->clm_fw_result_cnt); + else + ccx_info->clm_ratio = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n", + ccx_info->clm_fw_result_acc, ccx_info->clm_fw_result_cnt); + + ccx_info->clm_fw_result_acc = 0; + ccx_info->clm_fw_result_cnt = 0; } - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { +out: + PHYDM_DBG(dm, DBG_ENV_MNTR, "IGI=0x%x, nhm_ratio=%d, clm_ratio=%d\n\n", + ccx_info->echo_igi, ccx_info->nhm_ratio, ccx_info->clm_ratio); + +} + - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_READY_11N, MASKDWORD); +#endif - for (i = 0; i < 200; i++) { - ODM_delay_ms(1); - if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(17))) { - ret = 1; - break; - } +#ifdef CLM_SUPPORT + +void +phydm_clm_racing_release( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 value32; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "lv:(%d)->(0)\n", ccx->clm_set_lv); + + ccx->clm_ongoing = false; + ccx->clm_set_lv = CLM_RELEASE; + ccx->clm_app = CLM_BACKGROUND; +} + +u8 +phydm_clm_racing_ctrl( + void *dm_void, + enum phydm_nhm_level clm_lv +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 set_result = PHYDM_SET_SUCCESS; + /*acquire to control CLM API*/ + + PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_ongoing=%d, lv:(%d)->(%d)\n", + ccx->clm_ongoing, ccx->clm_set_lv, clm_lv); + if (ccx->clm_ongoing) { + if (clm_lv <= ccx->clm_set_lv) { + set_result = PHYDM_SET_FAIL; + } else { + phydm_ccx_hw_restart(dm); + ccx->clm_ongoing = false; } } - return ret; + + if (set_result) + ccx->clm_set_lv = clm_lv; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "clm racing success=%d\n", set_result); + return set_result; } + void -phydm_store_nhm_setting( - void *p_dm_void +phydm_clm_c2h_report_handler( + void *dm_void, + u8 *cmd_buf, + u8 cmd_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u8 clm_report = cmd_buf[0]; + u8 clm_report_idx = cmd_buf[1]; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (cmd_len >=12) + return; + + ccx_info->clm_fw_result_acc += clm_report; + ccx_info->clm_fw_result_cnt++; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%d] clm_report= %d\n", ccx_info->clm_fw_result_cnt, clm_report); + +} + +void +phydm_clm_h2c( + void *dm_void, + u16 obs_time, + u8 fw_clm_en +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 h2c_val[H2C_MAX_LENGTH] = {0}; + u8 i = 0; + u8 obs_time_idx = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "obs_time_index=%d *4 us\n", obs_time); + + for (i =1; i<=16; i++) { + if (obs_time & BIT(16 -i)) { + obs_time_idx = 16-i; + break; + } + } + + /* + obs_time =(2^16 -1) ~ (2^15) => obs_time_idx = 15 (65535 ~ 32768) + obs_time =(2^15 -1) ~ (2^14) => obs_time_idx = 14 + ... + ... + ... + obs_time =(2^1 -1) ~ (2^0) => obs_time_idx = 0 + */ - } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + h2c_val[0] = obs_time_idx | (((fw_clm_en) ? 1 : 0)<< 7); + h2c_val[1] = CLM_MAX_REPORT_TIME; + PHYDM_DBG(dm, DBG_ENV_MNTR, "PHYDM h2c[0x4d]=0x%x %x %x %x %x %x %x\n", + h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2], h2c_val[1], h2c_val[0]); + odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_CLM_MNTR, H2C_MAX_LENGTH, h2c_val); - } } void phydm_clm_setting( - void *p_dm_void + void *dm_void, + u16 clm_period /*4us sample 1 time*/ ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; - + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (ccx->clm_period != clm_period) { - odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKLWORD, ccx_info->CLM_period); /*4us sample 1 time*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(8), 0x1); /*Enable CCX for CLM*/ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x990, MASKLWORD, clm_period); - } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0x894, MASKLWORD, clm_period); + } - odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKLWORD, ccx_info->CLM_period); /*4us sample 1 time*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(8), 0x1); /*Enable CCX for CLM*/ + ccx->clm_period = clm_period; + PHYDM_DBG(dm, DBG_ENV_MNTR, "Update CLM period ((%d)) -> ((%d))\n", + ccx->clm_period, clm_period); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM period = %dus\n", __func__, ccx_info->CLM_period * 4)); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Set CLM period=%d * 4us\n", ccx->clm_period); } void phydm_clm_trigger( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 reg1 = (dm->support_ic_type & ODM_IC_11AC_SERIES) ? R_0x994 : R_0x890; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + odm_set_bb_reg(dm, reg1, BIT(0), 0x0); + odm_set_bb_reg(dm, reg1, BIT(0), 0x1); + + ccx->clm_trigger_time = dm->phydm_sys_up_time; + ccx->clm_rpt_stamp++; + ccx->clm_ongoing = true; +} - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(0), 0x0); /*Trigger CLM*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(0), 0x1); - } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(0), 0x0); /*Trigger CLM*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(0), 0x1); +boolean +phydm_clm_check_rdy( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean is_ready = false; + u32 reg1 = 0, reg1_bit = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg1 = ODM_REG_CLM_RESULT_11AC; + reg1_bit = 16; + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (dm->support_ic_type == ODM_RTL8710B) { + reg1 = R_0x8b4; + reg1_bit = 24; + } else { + reg1 = R_0x8b4; + reg1_bit = 16; + } } + PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM rdy=%d\n", is_ready); + return is_ready; +} + +void +phydm_clm_get_utility( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 clm_result_tmp; + + if (ccx->clm_period == 0) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] clm_period = 0\n"); + ccx->clm_ratio = 0; + } else if (ccx->clm_period >= 65530) { + clm_result_tmp = (u32)(ccx->clm_result * 100); + ccx->clm_ratio = (u8)((clm_result_tmp + (1<<15)) >> 16); + } else + ccx->clm_ratio = (u8)((ccx->clm_result*100) / ccx->clm_period); } boolean -phydm_check_clm_ready( - void *p_dm_void +phydm_clm_get_result( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u32 reg1 = (dm->support_ic_type & ODM_IC_11AC_SERIES) ? R_0x994 : R_0x890; + + odm_set_bb_reg(dm, reg1, BIT(0), 0x0); + if (phydm_clm_check_rdy(dm) == false) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM report Fail\n"); + phydm_clm_racing_release(dm); + return false; + } + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + ccx_info->clm_result = (u16)odm_get_bb_reg(dm, R_0xfa4, MASKLWORD); + else if (dm->support_ic_type & ODM_IC_11N_SERIES) + ccx_info->clm_result = (u16)odm_get_bb_reg(dm, R_0x8d0, MASKLWORD); + + + PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM result = %d *4 us\n", ccx_info->clm_result); + phydm_clm_racing_release(dm); + return true; +} + +void +phydm_clm_mntr_fw( + void *dm_void, + u16 monitor_time /*unit ms*/ ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 value32 = 0; - boolean ret = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 clm_result_tmp = 0; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); /*make sure CLM calc is ready*/ - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_READY_11N, MASKDWORD); /*make sure CLM calc is ready*/ + /*[Get CLM report]*/ + if (ccx->clm_fw_result_cnt != 0) + ccx->clm_ratio = (u8)(ccx->clm_fw_result_acc /ccx->clm_fw_result_cnt); + else + ccx->clm_ratio = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n", + ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt); + + ccx->clm_fw_result_acc = 0; + ccx->clm_fw_result_cnt = 0; + + + /*[CLM trigger]*/ + if (monitor_time >= 262) + ccx->clm_period = 65535; + else + ccx->clm_period = monitor_time * MS_TO_4US_RATIO; + + phydm_clm_h2c(dm, monitor_time, true); + +} - if ((p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) && (value32 & BIT(16))) - ret = true; - else if ((p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) && (value32 & BIT(16))) - ret = true; +u8 +phydm_clm_mntr_set( + void *dm_void, + struct clm_para_info *clm_para +) +{ + /*Driver Monitor CLM*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u16 clm_period = 0; + + + if (clm_para->mntr_time == 0) + return PHYDM_SET_FAIL; + + if (clm_para->clm_lv >= CLM_MAX_NUM) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[WARNING] Wrong LV=%d\n", clm_para->clm_lv); + return PHYDM_SET_FAIL; + } + + if (phydm_clm_racing_ctrl(dm, clm_para->clm_lv) == PHYDM_SET_FAIL) + return PHYDM_SET_FAIL; + + if (clm_para->mntr_time >= 262) + clm_period = CLM_PERIOD_MAX; else - ret = false; + clm_period = clm_para->mntr_time * MS_TO_4US_RATIO; + + ccx->clm_app = clm_para->clm_app; + phydm_clm_setting(dm, clm_period); + + return PHYDM_SET_SUCCESS; +} + +boolean +phydm_clm_mntr_chk( + void *dm_void, + u16 monitor_time /*unit ms*/ +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct clm_para_info clm_para = {0}; + u32 clm_result_tmp = 0; + boolean clm_chk_result = false; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + + if (ccx->clm_manual_ctrl) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM in manual ctrl\n"); + return clm_chk_result; + } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM ready = %d\n", __func__, ret)); + if ((ccx->clm_app != CLM_BACKGROUND) && + (ccx->clm_trigger_time + MAX_ENV_MNTR_TIME) > dm->phydm_sys_up_time) { + + PHYDM_DBG(dm, DBG_ENV_MNTR, "trigger_time %d, sys_time=%d\n", + ccx->clm_trigger_time, dm->phydm_sys_up_time); + + return clm_chk_result; + } + + clm_para.clm_app = CLM_BACKGROUND; + clm_para.clm_lv = CLM_LV_1; + clm_para.mntr_time = monitor_time; + + if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) { + + /*[Get CLM report]*/ + if (phydm_clm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n"); + phydm_clm_get_utility(dm); + } - return ret; + /*[CLM trigger]-------------------------------------------------*/ + if (phydm_clm_mntr_set(dm, &clm_para) == PHYDM_SET_SUCCESS) { + clm_chk_result = true; + } + } else { + phydm_clm_mntr_fw(dm, monitor_time); + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_ratio=%d\n", ccx->clm_ratio); + return clm_chk_result; } void -phydm_get_clm_result( - void *p_dm_void +phydm_set_clm_mntr_mode( + void *dm_void, + enum clm_monitor_mode mode ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + + if (ccx_info->clm_mntr_mode != mode) { + + ccx_info->clm_mntr_mode = mode; + phydm_ccx_hw_restart(dm); + + if (mode == CLM_DRIVER_MNTR) + phydm_clm_h2c(dm,0, 0); + } +} - u32 value32 = 0; +void +phydm_clm_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __FUNCTION__); + + ccx->clm_ongoing = false; + ccx->clm_manual_ctrl = 0; + ccx->clm_mntr_mode = CLM_DRIVER_MNTR; + ccx->clm_period = 0; + ccx->clm_rpt_stamp = 0; + phydm_clm_setting(dm, 65535); +} - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); /*read CLM calc result*/ - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11N, MASKDWORD); /*read CLM calc result*/ +void +phydm_clm_dbg( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + struct clm_para_info clm_para = {0}; + u32 i; + + for (i = 0; i < 4; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + } - ccx_info->CLM_result = (u16)(value32 & MASKLWORD); + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, "CLM Driver Basic-Trigger 262ms: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, "CLM Driver Adv-Trigger: {2} {app} {LV} {0~262ms}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, "CLM FW Trigger: {3}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, "CLM Get Result: {100}\n"); + } else if (var1[0] == 100) { /* Get CLM results */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM result = %dus\n", __func__, ccx_info->CLM_result * 4)); + if (phydm_clm_get_result(dm)) { + phydm_clm_get_utility(dm); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, "clm_rpt_stamp=%d\n", + ccx->clm_rpt_stamp); + + PDM_SNPF(out_len, used, output + used, out_len - used, "clm_ratio:((%d percent)) = (%d us/ %d us)\n", + ccx->clm_ratio, ccx->clm_result<<2, ccx->clm_period<<2); + + ccx->clm_manual_ctrl = 0; + + } else { /* Set & trigger CLM */ + ccx->clm_manual_ctrl = 1; + + if (var1[0] == 1) { + clm_para.clm_app = CLM_BACKGROUND; + clm_para.clm_lv = CLM_LV_4; + clm_para.mntr_time = 262; + ccx->clm_mntr_mode = CLM_DRIVER_MNTR; + + } else if (var1[0] == 2) { + clm_para.clm_app = (enum clm_application )var1[1]; + clm_para.clm_lv = (enum phydm_clm_level )var1[2]; + ccx->clm_mntr_mode = CLM_DRIVER_MNTR; + clm_para.mntr_time = (u16)var1[3]; + + } else if (var1[0] == 3) { + clm_para.clm_app = CLM_BACKGROUND; + clm_para.clm_lv = CLM_LV_4; + ccx->clm_mntr_mode = CLM_FW_MNTR; + clm_para.mntr_time = 262; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, "app=%d, lv=%d, mode=%s, time=%d ms\n", + clm_para.clm_app, clm_para.clm_lv, + ((ccx->clm_mntr_mode == CLM_FW_MNTR) ? "FW" : "driver"), + clm_para.mntr_time); + + if (phydm_clm_mntr_set(dm, &clm_para) == PHYDM_SET_SUCCESS) { + phydm_clm_trigger(dm); + /**/ + } + PDM_SNPF(out_len, used, output + used, out_len - used, "clm_rpt_stamp=%d\n", + ccx->clm_rpt_stamp); + + } + + *_used = used; + *_out_len = out_len; } + + +#endif /*#ifdef CLM_SUPPORT*/ + +u8 +phydm_env_mntr_trigger( + void *dm_void, + struct nhm_para_info *nhm_para, + struct clm_para_info *clm_para, + struct env_trig_rpt *trig_rpt +) +{ +#if(defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean nhm_set_ok = false; + boolean clm_set_ok = false; + u8 trigger_result = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + /*[NHM]*/ + nhm_set_ok = phydm_nhm_mntr_set(dm, nhm_para); + + /*[CLM]*/ + if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) { + clm_set_ok = phydm_clm_mntr_set(dm, clm_para); + } else if (ccx->clm_mntr_mode == CLM_FW_MNTR){ + phydm_clm_h2c(dm, CLM_PERIOD_MAX, true); + trigger_result |= CLM_SUCCESS; + } + + if (nhm_set_ok) { + phydm_nhm_trigger(dm); + trigger_result |= NHM_SUCCESS; + } + + if (clm_set_ok) { + phydm_clm_trigger(dm); + trigger_result |= CLM_SUCCESS; + } + + trig_rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp; + trig_rpt->clm_rpt_stamp = ccx->clm_rpt_stamp; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\n\n", + trig_rpt->nhm_rpt_stamp, trig_rpt->clm_rpt_stamp); + + return trigger_result; +#endif +} + +u8 +phydm_env_mntr_result( + void *dm_void, + struct env_mntr_rpt *rpt +) +{ +#if(defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 env_mntr_rpt = 0; + u32 clm_result_tmp = 0; + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + /*Get NHM result*/ + if (phydm_nhm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n"); + phydm_nhm_get_utility(dm); + rpt->nhm_ratio = ccx->nhm_ratio; + env_mntr_rpt |= NHM_SUCCESS; + odm_move_memory(dm, &rpt->nhm_result[0], &ccx->nhm_result[0], NHM_RPT_NUM); + } else { + rpt->nhm_ratio = ENV_MNTR_FAIL; + } + + /*Get CLM result*/ + if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) { + + if (phydm_clm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n"); + phydm_clm_get_utility(dm); + env_mntr_rpt |= CLM_SUCCESS; + rpt->clm_ratio = ccx->clm_ratio; + } else { + rpt->clm_ratio = ENV_MNTR_FAIL; + } + + } else { + if (ccx->clm_fw_result_cnt != 0) + ccx->clm_ratio = (u8)(ccx->clm_fw_result_acc /ccx->clm_fw_result_cnt); + else + ccx->clm_ratio = 0; + + rpt->clm_ratio = ccx->clm_ratio; + PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n", + ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt); + + ccx->clm_fw_result_acc = 0; + ccx->clm_fw_result_cnt = 0; + env_mntr_rpt |= CLM_SUCCESS; + } + + rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp; + rpt->clm_rpt_stamp = ccx->clm_rpt_stamp; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "IGI=0x%x, nhm_ratio=%d, clm_ratio=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\n\n", + ccx->nhm_igi, rpt->nhm_ratio, rpt->clm_ratio, rpt->nhm_rpt_stamp, rpt->clm_rpt_stamp); + + return env_mntr_rpt; +#endif +} + +/*Environment Monitor*/ +void +phydm_env_mntr_watchdog( + void *dm_void +) +{ +#if(defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean nhm_chk_ok = false; + boolean clm_chk_ok = false; + + if (!(dm->support_ability & ODM_BB_ENV_MONITOR)) + return; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + nhm_chk_ok = phydm_nhm_mntr_chk(dm, 262);/*monitor 262ms*/ + clm_chk_ok = phydm_clm_mntr_chk(dm, 262); /*monitor 262ms*/ + + if (nhm_chk_ok) + phydm_nhm_trigger(dm); + + if (clm_chk_ok) + phydm_clm_trigger(dm); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "Summary: nhm_ratio=((%d)) clm_ratio=((%d))\n\n", + ccx->nhm_ratio, ccx->clm_ratio); +#endif +} + + +void +phydm_env_monitor_init( + void *dm_void +) +{ +#if(defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_ENV_MONITOR)) + return; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __FUNCTION__); + + phydm_ccx_hw_restart(dm); + phydm_nhm_init(dm); + phydm_clm_init(dm); +#endif +} + +void +phydm_env_mntr_dbg( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + struct clm_para_info clm_para = {0}; + struct nhm_para_info nhm_para = {0}; + struct env_mntr_rpt rpt = {0}; + struct env_trig_rpt trig_rpt = {0}; + u8 set_result; + u8 i; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, "Basic-Trigger 262ms: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, "Get Result: {100}\n"); + } else if (var1[0] == 100) { /* Get CLM results */ + + set_result = phydm_env_mntr_result(dm, &rpt); + + PDM_SNPF(out_len, used, output + used, out_len - used, "Set Result=%d\n nhm_ratio=%d clm_ratio=%d\n nhm_rpt_stamp=%d, clm_rpt_stamp=%d, \n", + set_result, rpt.nhm_ratio, rpt.clm_ratio, rpt.nhm_rpt_stamp, rpt.clm_rpt_stamp); + + for (i = 0; i <= 11; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, "nhm_rpt[%d] = %d (%d percent)\n", + i, rpt.nhm_result[i], + (((rpt.nhm_result[i] * 100) + 128) >> 8)); + } + + } else { /* Set & trigger CLM */ + /*nhm para*/ + nhm_para.incld_txon = NHM_EXCLUDE_TXON; + nhm_para.incld_cca = NHM_EXCLUDE_CCA; + nhm_para.div_opt = NHM_CNT_ALL; + nhm_para.nhm_app = NHM_ACS; + nhm_para.nhm_lv = NHM_LV_2; + nhm_para.mntr_time = 262; + + /*clm para*/ + clm_para.clm_app = CLM_ACS; + clm_para.clm_lv = CLM_LV_2; + clm_para.mntr_time = 262; + + set_result = phydm_env_mntr_trigger(dm, &nhm_para, &clm_para, &trig_rpt); + + PDM_SNPF(out_len, used, output + used, out_len - used, "Set Result=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\n", + set_result, trig_rpt.nhm_rpt_stamp, trig_rpt.clm_rpt_stamp); + } + + *_used = used; + *_out_len = out_len; +} \ No newline at end of file diff --git a/hal/phydm/phydm_ccx.h b/hal/phydm/phydm_ccx.h index af0a617..f55f6f8 100644 --- a/hal/phydm/phydm_ccx.h +++ b/hal/phydm/phydm_ccx.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,134 +8,377 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ + #ifndef __PHYDMCCX_H__ -#define __PHYDMCCX_H__ +#define __PHYDMCCX_H__ + +/* 1 ============================================================ + * 1 Definition + * 1 ============================================================ */ #define CCX_EN 1 -#define SET_NHM_SETTING 0 -#define STORE_NHM_SETTING 1 -#define RESTORE_NHM_SETTING 2 +#define MAX_ENV_MNTR_TIME 8 /*second*/ +#define IGI_TO_NHM_TH_MULTIPLIER 2 +#define MS_TO_4US_RATIO 250 +#define CCA_CAP 14 +#define CLM_MAX_REPORT_TIME 10 +#define DEVIDER_ERROR 0xffff +#define CLM_PERIOD_MAX 65535 +#define NHM_PERIOD_MAX 65534 +#define NHM_TH_NUM 11 /*threshold number of NHM*/ +#define NHM_RPT_NUM 12 + +#define IGI_2_NHM_TH(igi) ((igi) << 1)/*NHM_threshold = IGI * 2*/ +#define NTH_TH_2_RSSI(th) ((th >> 1) - 10) -/* -#define NHM_EXCLUDE_CCA 0 -#define NHM_INCLUDE_CCA 1 -#define NHM_EXCLUDE_TXON 0 -#define NHM_INCLUDE_TXON 1 -*/ +/*FAHM*/ +#define FAHM_INCLD_FA BIT(0) +#define FAHM_INCLD_CRC_OK BIT(1) +#define FAHM_INCLD_CRC_ER BIT(2) -enum nhm_inexclude_cca { - NHM_EXCLUDE_CCA, - NHM_INCLUDE_CCA +#define NHM_SUCCESS BIT(0) +#define CLM_SUCCESS BIT(1) +#define FAHM_SUCCESS BIT(2) +#define ENV_MNTR_FAIL 0xff + +/* 1 ============================================================ + * 1 enumrate + * 1 ============================================================ */ +enum phydm_clm_level { + CLM_RELEASE = 0, + CLM_LV_1 = 1, /* Low Priority function */ + CLM_LV_2 = 2, /* Middle Priority function */ + CLM_LV_3 = 3, /* High priority function (ex: Check hang function) */ + CLM_LV_4 = 4, /* Debug function (the highest priority) */ + CLM_MAX_NUM = 5 }; -enum nhm_inexclude_txon { - NHM_EXCLUDE_TXON, - NHM_INCLUDE_TXON +enum phydm_nhm_level { + NHM_RELEASE = 0, + NHM_LV_1 = 1, /* Low Priority function */ + NHM_LV_2 = 2, /* Middle Priority function */ + NHM_LV_3 = 3, /* High priority function (ex: Check hang function) */ + NHM_LV_4 = 4, /* Debug function (the highest priority) */ + NHM_MAX_NUM = 5 }; +enum nhm_divider_opt_all { + NHM_CNT_ALL = 0, /*nhm SUM report <= 255*/ + NHM_VALID = 1, /*nhm SUM report = 255*/ + NHM_CNT_INIT +}; -struct _CCX_INFO { +enum nhm_setting { + SET_NHM_SETTING, + STORE_NHM_SETTING, + RESTORE_NHM_SETTING +}; - /*Settings*/ - u8 NHM_th[11]; - u16 NHM_period; /* 4us per unit */ - u16 CLM_period; /* 4us per unit */ - enum nhm_inexclude_txon nhm_inexclude_txon; - enum nhm_inexclude_cca nhm_inexclude_cca; +enum nhm_inexclude_cca_all { + NHM_EXCLUDE_CCA = 0, + NHM_INCLUDE_CCA = 1, + NHM_CCA_INIT +}; - /*Previous Settings*/ - u8 NHM_th_restore[11]; - u16 NHM_period_restore; /* 4us per unit */ - u16 CLM_period_restore; /* 4us per unit */ - enum nhm_inexclude_txon NHM_inexclude_txon_restore; - enum nhm_inexclude_cca NHM_inexclude_cca_restore; +enum nhm_inexclude_txon_all { + NHM_EXCLUDE_TXON = 0, + NHM_INCLUDE_TXON = 1, + NHM_TXON_INIT +}; - /*Report*/ - u8 NHM_result[12]; - u16 NHM_duration; - u16 CLM_result; +enum nhm_application { + NHM_BACKGROUND = 0,/*default*/ + NHM_ACS = 1, + IEEE_11K_HIGH = 2, + IEEE_11K_LOW = 3, + INTEL_XBOX = 4, + NHM_DBG = 5, /*manual trigger*/ +}; + +enum clm_application { + CLM_BACKGROUND = 0,/*default*/ + CLM_ACS = 1, +}; +enum clm_monitor_mode { + CLM_DRIVER_MNTR = 1, + CLM_FW_MNTR = 2 +}; + +/* 1 ============================================================ + * 1 structure + * 1 ============================================================ */ +struct env_trig_rpt { + u8 nhm_rpt_stamp; + u8 clm_rpt_stamp; +}; - boolean echo_NHM_en; - boolean echo_CLM_en; - u8 echo_IGI; +struct env_mntr_rpt { + u8 nhm_ratio; + u8 nhm_result[NHM_RPT_NUM]; + u8 clm_ratio; + u8 nhm_rpt_stamp; + u8 clm_rpt_stamp; }; -/*NHM*/ +struct nhm_para_info { + enum nhm_inexclude_txon_all incld_txon; /*Include TX on*/ + enum nhm_inexclude_cca_all incld_cca; /*Include CCA*/ + enum nhm_divider_opt_all div_opt; /*divider option*/ + enum nhm_application nhm_app; + enum phydm_nhm_level nhm_lv; + u16 mntr_time; /*0~262 unit ms*/ + +}; + +struct clm_para_info { + enum clm_application clm_app; + enum phydm_clm_level clm_lv; + u16 mntr_time; /*0~262 unit ms*/ +}; + +struct ccx_info { + u32 nhm_trigger_time; + u32 clm_trigger_time; +#ifdef NHM_SUPPORT + enum nhm_application nhm_app; + enum nhm_inexclude_txon_all nhm_include_txon; + enum nhm_inexclude_cca_all nhm_include_cca; + enum nhm_divider_opt_all nhm_divider_opt; + /*Report*/ + u8 nhm_th[NHM_TH_NUM]; + u8 nhm_result[NHM_RPT_NUM]; + u16 nhm_period; /* 4us per unit */ + u8 nhm_igi; + u8 nhm_manual_ctrl; + u8 nhm_ratio; /*1% per nuit, it means the interference igi can't overcome.*/ + u8 nhm_rpt_sum; + u16 nhm_duration; /*Real time of NHM_VALID */ + u8 nhm_set_lv; + boolean nhm_ongoing; + u8 nhm_rpt_stamp; +#endif +#ifdef CLM_SUPPORT + enum clm_application clm_app; + u8 clm_manual_ctrl; + u8 clm_set_lv; + boolean clm_ongoing; + u16 clm_period; /* 4us per unit */ + u16 clm_result; + u8 clm_ratio; + u32 clm_fw_result_acc; + u8 clm_fw_result_cnt; + enum clm_monitor_mode clm_mntr_mode; + u8 clm_rpt_stamp; +#endif +#ifdef FAHM_SUPPORT + boolean fahm_ongoing; + u8 env_mntr_igi; + u8 fahm_nume_sel; /*fahm_numerator_sel: select {FA, CRCOK, CRC_fail} */ + u8 fahm_denum_sel; /*fahm_denumerator_sel: select {FA, CRCOK, CRC_fail} */ + u16 fahm_period; /*unit: 4us*/ +#endif +#if 1 /*Will remove*/ + /*Previous Settings*/ + enum nhm_inexclude_txon_all nhm_inexclude_txon_restore; + enum nhm_inexclude_cca_all nhm_inexclude_cca_restore; + u8 nhm_th_restore[NHM_TH_NUM]; + u16 nhm_period_restore;/* 4us per unit */ + u8 echo_igi; /* nhm_result comes from this igi */ +#endif +}; + +/* 1 ============================================================ + * 1 structure + * 1 ============================================================ */ void -phydm_nhm_counter_statistics_init( - void *p_dm_void +phydm_get_nhm_result( + void *dm_void ); void -phydm_nhm_counter_statistics( - void *p_dm_void +phydm_set_nhm_th_by_igi( + void *dm_void, + u8 igi ); void -phydm_nhm_counter_statistics_reset( - void *p_dm_void +phydm_nhm_setting( + void *dm_void, + u8 nhm_setting ); void -phydm_get_nhm_counter_statistics( - void *p_dm_void +phydm_ccx_monitor_trigger( + void *dm_void, + u16 monitor_time ); -boolean -phydm_cal_nhm_cnt( - void *p_dm_void +void +phydm_ccx_monitor_result( + void *dm_void ); + +#ifdef FAHM_SUPPORT + void -phydm_nhm_setting( - void *p_dm_void, - u8 nhm_setting +phydm_fahm_init( + void *dm_void ); +void +phydm_fahm_dbg( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); + +#endif + + +/*NHM*/ +#ifdef NHM_SUPPORT void phydm_nhm_trigger( - void *p_dm_void + void *dm_void ); void -phydm_get_nhm_result( - void *p_dm_void +phydm_nhm_init( + void *dm_void ); -boolean -phydm_check_nhm_ready( - void *p_dm_void +void +phydm_nhm_dbg( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num ); +#endif /*CLM*/ +#ifdef CLM_SUPPORT +void +phydm_clm_c2h_report_handler( + void *dm_void, + u8 *cmd_buf, + u8 cmd_len +); + +void +phydm_clm_h2c( + void *dm_void, + u16 obs_time, + u8 fw_clm_en +); + void phydm_clm_setting( - void *p_dm_void + void *dm_void, + u16 clm_period ); void phydm_clm_trigger( - void *p_dm_void + void *dm_void +); + +boolean +phydm_clm_check_rdy( + void *dm_void +); + +void +phydm_clm_get_utility( + void *dm_void ); boolean -phydm_check_clm_ready( - void *p_dm_void +phydm_clm_get_result( + void *dm_void +); + +u8 +phydm_clm_mntr_set( + void *dm_void, + struct clm_para_info *clm_para +); + +void +phydm_set_clm_mntr_mode( + void *dm_void, + enum clm_monitor_mode mode +); + +void +phydm_clm_dbg( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); +#endif + +u8 +phydm_env_mntr_trigger( + void *dm_void, + struct nhm_para_info *nhm_para, + struct clm_para_info *clm_para, + struct env_trig_rpt *rpt +); + +u8 +phydm_env_mntr_result( + void *dm_void, + struct env_mntr_rpt *rpt +); + +void +phydm_env_mntr_watchdog( + void *dm_void ); + void -phydm_get_clm_result( - void *p_dm_void +phydm_env_monitor_init( + void *dm_void ); +void +phydm_env_mntr_dbg( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); #endif diff --git a/hal/phydm/phydm_cfotracking.c b/hal/phydm/phydm_cfotracking.c index 40c5a02..abef19b 100644 --- a/hal/phydm/phydm_cfotracking.c +++ b/hal/phydm/phydm_cfotracking.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,100 +8,110 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" void phydm_set_crystal_cap( - void *p_dm_void, + void *dm_void, u8 crystal_cap ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK); - if (p_cfo_track->crystal_cap == crystal_cap) + if (cfo_track->crystal_cap == crystal_cap) return; crystal_cap = crystal_cap & 0x3F; - p_cfo_track->crystal_cap = crystal_cap; + cfo_track->crystal_cap = crystal_cap; - if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) { + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) { #if (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) /* write 0x24[22:17] = 0x24[16:11] = crystal_cap */ - odm_set_bb_reg(p_dm_odm, REG_AFE_XTAL_CTRL, 0x007ff800, (crystal_cap | (crystal_cap << 6))); + odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x007ff800, (crystal_cap | (crystal_cap << 6))); #endif } #if (RTL8812A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & ODM_RTL8812) { + else if (dm->support_ic_type & ODM_RTL8812) { /* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */ - odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6))); + odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6))); } #endif #if (RTL8703B_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) - else if ((p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8723D))) { + else if ((dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8723D))) { /* 0x2C[23:18] = 0x2C[17:12] = crystal_cap */ - odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6))); + odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6))); } #endif #if (RTL8814A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & ODM_RTL8814A) { + else if (dm->support_ic_type & ODM_RTL8814A) { /* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */ - odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6))); + odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6))); } #endif #if (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8197F)) { + else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8197F)) { /* write 0x24[30:25] = 0x28[6:1] = crystal_cap */ - odm_set_bb_reg(p_dm_odm, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); - odm_set_bb_reg(p_dm_odm, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); + odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); + odm_set_bb_reg(dm, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); } #endif #if (RTL8710B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & (ODM_RTL8710B)) { + else if (dm->support_ic_type & (ODM_RTL8710B)) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) /* write 0x60[29:24] = 0x60[23:18] = crystal_cap */ - HAL_SetSYSOnReg(p_dm_odm->adapter, REG_SYS_XTAL_CTRL0, 0x3FFC0000, (crystal_cap | (crystal_cap << 6))); + HAL_SetSYSOnReg((PADAPTER)dm->adapter, REG_SYS_XTAL_CTRL0, 0x3FFC0000, (crystal_cap | (crystal_cap << 6))); #endif } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("Set rystal_cap = 0x%x\n", p_cfo_track->crystal_cap)); + PHYDM_DBG(dm, DBG_CFO_TRK, "Set rystal_cap = 0x%x\n", cfo_track->crystal_cap); } u8 -odm_get_default_crytaltal_cap( - void *p_dm_void +phydm_get_default_crytaltal_cap( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 crystal_cap = 0x20; #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); crystal_cap = rtlefuse->crystalcap; #elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - crystal_cap = p_hal_data->crystal_cap; + crystal_cap = hal_data->crystal_cap; #else - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; if (priv->pmib->dot11RFEntry.xcap > 0) crystal_cap = priv->pmib->dot11RFEntry.xcap; @@ -113,270 +123,249 @@ odm_get_default_crytaltal_cap( } void -odm_set_atc_status( - void *p_dm_void, +phydm_set_atc_status( + void *dm_void, boolean atc_status ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK); - if (p_cfo_track->is_atc_status == atc_status) + if (cfo_track->is_atc_status == atc_status) return; - odm_set_bb_reg(p_dm_odm, ODM_REG(BB_ATC, p_dm_odm), ODM_BIT(BB_ATC, p_dm_odm), atc_status); - p_cfo_track->is_atc_status = atc_status; + odm_set_bb_reg(dm, ODM_REG(BB_ATC, dm), ODM_BIT(BB_ATC, dm), atc_status); + cfo_track->is_atc_status = atc_status; } boolean -odm_get_atc_status( - void *p_dm_void +phydm_get_atc_status( + void *dm_void ) { boolean atc_status; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - atc_status = (boolean)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_ATC, p_dm_odm), ODM_BIT(BB_ATC, p_dm_odm)); + atc_status = (boolean)odm_get_bb_reg(dm, ODM_REG(BB_ATC, dm), ODM_BIT(BB_ATC, dm)); return atc_status; } void -odm_cfo_tracking_reset( - void *p_dm_void +phydm_cfo_tracking_reset( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); - - p_cfo_track->def_x_cap = odm_get_default_crytaltal_cap(p_dm_odm); - p_cfo_track->is_adjust = true; - - if (p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) { - phydm_set_crystal_cap(p_dm_odm, p_cfo_track->crystal_cap - 1); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, - ("odm_cfo_tracking_reset(): approch default value (0x%x)\n", p_cfo_track->crystal_cap)); - } else if (p_cfo_track->crystal_cap < p_cfo_track->def_x_cap) { - phydm_set_crystal_cap(p_dm_odm, p_cfo_track->crystal_cap + 1); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, - ("odm_cfo_tracking_reset(): approch default value (0x%x)\n", p_cfo_track->crystal_cap)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK); + + PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__); + + cfo_track->def_x_cap = phydm_get_default_crytaltal_cap(dm); + cfo_track->is_adjust = true; + + if (cfo_track->crystal_cap > cfo_track->def_x_cap) { + + phydm_set_crystal_cap(dm, cfo_track->crystal_cap - 1); + PHYDM_DBG(dm, DBG_CFO_TRK, "approch to Init-val (0x%x)\n", cfo_track->crystal_cap); + + } else if (cfo_track->crystal_cap < cfo_track->def_x_cap) { + + phydm_set_crystal_cap(dm, cfo_track->crystal_cap + 1); + PHYDM_DBG(dm, DBG_CFO_TRK, "approch to init-val 0x%x\n", cfo_track->crystal_cap); } #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - odm_set_atc_status(p_dm_odm, true); + phydm_set_atc_status(dm, true); #endif } void -odm_cfo_tracking_init( - void *p_dm_void +phydm_cfo_tracking_init( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK); - p_cfo_track->def_x_cap = p_cfo_track->crystal_cap = odm_get_default_crytaltal_cap(p_dm_odm); - p_cfo_track->is_atc_status = odm_get_atc_status(p_dm_odm); - p_cfo_track->is_adjust = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========>\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): is_atc_status = %d, crystal_cap = 0x%x\n", p_cfo_track->is_atc_status, p_cfo_track->def_x_cap)); + cfo_track->def_x_cap = cfo_track->crystal_cap = phydm_get_default_crytaltal_cap(dm); + cfo_track->is_atc_status = phydm_get_atc_status(dm); + cfo_track->is_adjust = true; + PHYDM_DBG(dm, DBG_CFO_TRK, "ODM_CfoTracking_init()=========>\n"); + PHYDM_DBG(dm, DBG_CFO_TRK, "ODM_CfoTracking_init(): is_atc_status = %d, crystal_cap = 0x%x\n", cfo_track->is_atc_status, cfo_track->def_x_cap); #if RTL8822B_SUPPORT /* Crystal cap. control by WiFi */ - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - odm_set_bb_reg(p_dm_odm, 0x10, 0x40, 0x1); + if (dm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(dm, 0x10, 0x40, 0x1); #endif #if RTL8821C_SUPPORT /* Crystal cap. control by WiFi */ - if (p_dm_odm->support_ic_type & ODM_RTL8821C) - odm_set_bb_reg(p_dm_odm, 0x10, 0x40, 0x1); + if (dm->support_ic_type & ODM_RTL8821C) + odm_set_bb_reg(dm, 0x10, 0x40, 0x1); #endif } void -odm_cfo_tracking( - void *p_dm_void +phydm_cfo_tracking( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); - s32 CFO_ave = 0; - u32 CFO_rpt_sum, cfo_khz_avg[4] = {0}; - s32 CFO_ave_diff; - s8 crystal_cap = p_cfo_track->crystal_cap; - u8 adjust_xtal = 1, i, valid_path_cnt = 0; - - /* 4 Support ability */ - if (!(p_dm_odm->support_ability & ODM_BB_CFO_TRACKING)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Return: support_ability ODM_BB_CFO_TRACKING is disabled\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK); + s32 cfo_avg = 0, cfo_path_sum = 0; /*avg among each path*/ + u32 cfo_rpt_sum, cfo_khz_avg[4] = {0}; + s8 crystal_cap = cfo_track->crystal_cap; + u8 i, valid_path_cnt = 0; + + if (!(dm->support_ability & ODM_BB_CFO_TRACKING)) { return; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking()=========>\n")); + PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__); - if (!p_dm_odm->is_linked || !p_dm_odm->is_one_entry_only) { - /* 4 No link or more than one entry */ - odm_cfo_tracking_reset(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Reset: is_linked = %d, is_one_entry_only = %d\n", - p_dm_odm->is_linked, p_dm_odm->is_one_entry_only)); + if (!dm->is_linked || !dm->is_one_entry_only) { + phydm_cfo_tracking_reset(dm); + PHYDM_DBG(dm, DBG_CFO_TRK, "is_linked = %d, one_entry_only = %d\n", + dm->is_linked, dm->is_one_entry_only); + } else { - /* 3 1. CFO Tracking */ - /* 4 1.1 No new packet */ - if (p_cfo_track->packet_count == p_cfo_track->packet_count_pre) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): packet counter doesn't change\n")); + + /* No new packet */ + if (cfo_track->packet_count == cfo_track->packet_count_pre) { + PHYDM_DBG(dm, DBG_CFO_TRK, "Pkt cnt doesn't change\n"); return; } - p_cfo_track->packet_count_pre = p_cfo_track->packet_count; - - /* 4 1.2 Calculate CFO */ - for (i = 0; i < p_dm_odm->num_rf_path; i++) { + cfo_track->packet_count_pre = cfo_track->packet_count; - if (p_cfo_track->CFO_cnt[i] == 0) + /*Calculate CFO */ + for (i = 0; i < dm->num_rf_path; i++) { + if (cfo_track->CFO_cnt[i] == 0) continue; valid_path_cnt++; - CFO_rpt_sum = (u32)((p_cfo_track->CFO_tail[i] < 0) ? (0 - p_cfo_track->CFO_tail[i]) : p_cfo_track->CFO_tail[i]); - cfo_khz_avg[i] = CFO_HW_RPT_2_MHZ(CFO_rpt_sum) / p_cfo_track->CFO_cnt[i]; + cfo_rpt_sum = (u32)CFO_HW_RPT_2_KHZ(((cfo_track->CFO_tail[i] < 0) ? (0 - cfo_track->CFO_tail[i]) : cfo_track->CFO_tail[i])); + cfo_khz_avg[i] = cfo_rpt_sum / cfo_track->CFO_cnt[i]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[path %d] CFO_rpt_sum = (( %d )), CFO_cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n", - i, CFO_rpt_sum, p_cfo_track->CFO_cnt[i], ((p_cfo_track->CFO_tail[i] < 0) ? "-" : " "), cfo_khz_avg[i])); + PHYDM_DBG(dm, DBG_CFO_TRK, "[Path-%d] CFO_sum = (( %d )), cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n", + i, cfo_rpt_sum, cfo_track->CFO_cnt[i], ((cfo_track->CFO_tail[i] < 0) ? "-" : " "), cfo_khz_avg[i]); } for (i = 0; i < valid_path_cnt; i++) { - - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("path [%d], p_cfo_track->CFO_tail = %d\n", i, p_cfo_track->CFO_tail[i])); */ - if (p_cfo_track->CFO_tail[i] < 0) { - CFO_ave += (0 - (s32)cfo_khz_avg[i]); - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("CFO_ave = %d\n", CFO_ave)); */ + if (cfo_track->CFO_tail[i] < 0) { + cfo_path_sum += (0 - (s32)cfo_khz_avg[i]); } else - CFO_ave += (s32)cfo_khz_avg[i]; + cfo_path_sum += (s32)cfo_khz_avg[i]; } if (valid_path_cnt >= 2) - CFO_ave = CFO_ave / valid_path_cnt; + cfo_avg = cfo_path_sum / valid_path_cnt; + else + cfo_avg = cfo_path_sum; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("valid_path_cnt = ((%d)), CFO_ave = ((%d kHz))\n", valid_path_cnt, CFO_ave)); + cfo_track->CFO_ave_pre = cfo_avg; + + PHYDM_DBG(dm, DBG_CFO_TRK, "path_cnt = ((%d)), CFO_avg_path=((%d kHz))\n", valid_path_cnt, cfo_avg); /*reset counter*/ - for (i = 0; i < p_dm_odm->num_rf_path; i++) { - p_cfo_track->CFO_tail[i] = 0; - p_cfo_track->CFO_cnt[i] = 0; + for (i = 0; i < dm->num_rf_path; i++) { + cfo_track->CFO_tail[i] = 0; + cfo_track->CFO_cnt[i] = 0; } - /* 4 1.3 Avoid abnormal large CFO */ - CFO_ave_diff = (p_cfo_track->CFO_ave_pre >= CFO_ave) ? (p_cfo_track->CFO_ave_pre - CFO_ave) : (CFO_ave - p_cfo_track->CFO_ave_pre); - if (CFO_ave_diff > 20 && p_cfo_track->large_cfo_hit == 0 && !p_cfo_track->is_adjust) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): first large CFO hit\n")); - p_cfo_track->large_cfo_hit = 1; - return; - } else - p_cfo_track->large_cfo_hit = 0; - p_cfo_track->CFO_ave_pre = CFO_ave; - - /* 4 1.4 Dynamic Xtal threshold */ - if (p_cfo_track->is_adjust == false) { - if (CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH)) - p_cfo_track->is_adjust = true; + /* To adjust crystal cap or not */ + if (cfo_track->is_adjust == false) { + if (cfo_avg > CFO_TRK_ENABLE_TH || cfo_avg < (-CFO_TRK_ENABLE_TH)) + cfo_track->is_adjust = true; } else { - if (CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW)) - p_cfo_track->is_adjust = false; + if (cfo_avg < CFO_TRK_STOP_TH && cfo_avg > (-CFO_TRK_STOP_TH)) + cfo_track->is_adjust = false; } -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - /* 4 1.5 BT case: Disable CFO tracking */ - if (p_dm_odm->is_bt_enabled) { - p_cfo_track->is_adjust = false; - phydm_set_crystal_cap(p_dm_odm, p_cfo_track->def_x_cap); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Disable CFO tracking for BT!!\n")); - } -#if 0 - /* 4 1.6 Big jump */ - if (p_cfo_track->is_adjust) { - if (CFO_ave > CFO_TH_XTAL_LOW) - adjust_xtal = adjust_xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2); - else if (CFO_ave < (-CFO_TH_XTAL_LOW)) - adjust_xtal = adjust_xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Crystal cap offset = %d\n", adjust_xtal)); + #ifdef ODM_CONFIG_BT_COEXIST + /*BT case: Disable CFO tracking */ + if (dm->bt_info_table.is_bt_enabled) { + cfo_track->is_adjust = false; + phydm_set_crystal_cap(dm, cfo_track->def_x_cap); + PHYDM_DBG(dm, DBG_CFO_TRK, "Disable CFO tracking for BT\n"); } -#endif -#endif - - /* 4 1.7 Adjust Crystal Cap. */ - if (p_cfo_track->is_adjust) { - if (CFO_ave > CFO_TH_XTAL_LOW) - crystal_cap = crystal_cap + adjust_xtal; - else if (CFO_ave < (-CFO_TH_XTAL_LOW)) - crystal_cap = crystal_cap - adjust_xtal; + #endif + + /*Adjust Crystal Cap. */ + if (cfo_track->is_adjust) { + if (cfo_avg > CFO_TRK_STOP_TH) + crystal_cap += 1; + else if (cfo_avg < (-CFO_TRK_STOP_TH)) + crystal_cap -=1; if (crystal_cap > 0x3f) crystal_cap = 0x3f; else if (crystal_cap < 0) crystal_cap = 0; - phydm_set_crystal_cap(p_dm_odm, (u8)crystal_cap); + phydm_set_crystal_cap(dm, (u8)crystal_cap); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n", - p_cfo_track->crystal_cap, p_cfo_track->def_x_cap)); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - return; - - /* 3 2. Dynamic ATC switch */ - if (CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC) { - odm_set_atc_status(p_dm_odm, false); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Disable ATC!!\n")); - } else { - odm_set_atc_status(p_dm_odm, true); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Enable ATC!!\n")); + + PHYDM_DBG(dm, DBG_CFO_TRK, "Crystal cap{Current, Default}={0x%x, 0x%x}\n\n", + cfo_track->crystal_cap, cfo_track->def_x_cap); + + /* Dynamic ATC switch */ + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (cfo_avg < CFO_TH_ATC && cfo_avg > -CFO_TH_ATC) { + phydm_set_atc_status(dm, false); + PHYDM_DBG(dm, DBG_CFO_TRK, "Disable ATC\n"); + } else { + phydm_set_atc_status(dm, true); + PHYDM_DBG(dm, DBG_CFO_TRK, "Enable ATC\n"); + } } -#endif + #endif } } void -odm_parsing_cfo( - void *p_dm_void, - void *p_pktinfo_void, +phydm_parsing_cfo( + void *dm_void, + void *pktinfo_void, s8 *pcfotail, u8 num_ss ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pktinfo_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void; + struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK); u8 i; - if (!(p_dm_odm->support_ability & ODM_BB_CFO_TRACKING)) + if (!(dm->support_ability & ODM_BB_CFO_TRACKING)) return; #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (p_pktinfo->is_packet_match_bssid) + if (pktinfo->is_packet_match_bssid) #else - if (p_pktinfo->station_id != 0) + if (pktinfo->station_id != 0) #endif { - if (num_ss > p_dm_odm->num_rf_path) /*For fool proof*/ - num_ss = p_dm_odm->num_rf_path; + if (num_ss > dm->num_rf_path) /*For fool proof*/ + num_ss = dm->num_rf_path; - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("num_ss = ((%d)), p_dm_odm->num_rf_path = ((%d))\n", num_ss, p_dm_odm->num_rf_path));*/ + /*PHYDM_DBG(dm, DBG_CFO_TRK, "num_ss = ((%d)), dm->num_rf_path = ((%d))\n", num_ss, dm->num_rf_path);*/ /* 3 Update CFO report for path-A & path-B */ /* Only paht-A and path-B have CFO tail and short CFO */ for (i = 0; i < num_ss; i++) { - p_cfo_track->CFO_tail[i] += pcfotail[i]; - p_cfo_track->CFO_cnt[i]++; - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n", - p_pktinfo->station_id, i, p_pktinfo->data_rate, pcfotail[i], p_cfo_track->CFO_tail[i], p_cfo_track->CFO_cnt[i])); + cfo_track->CFO_tail[i] += pcfotail[i]; + cfo_track->CFO_cnt[i]++; + /*PHYDM_DBG(dm, DBG_CFO_TRK, "[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n", + pktinfo->station_id, i, pktinfo->data_rate, pcfotail[i], cfo_track->CFO_tail[i], cfo_track->CFO_cnt[i]); */ } /* 3 Update packet counter */ - if (p_cfo_track->packet_count == 0xffffffff) - p_cfo_track->packet_count = 0; + if (cfo_track->packet_count == 0xffffffff) + cfo_track->packet_count = 0; else - p_cfo_track->packet_count++; + cfo_track->packet_count++; } } diff --git a/hal/phydm/phydm_cfotracking.h b/hal/phydm/phydm_cfotracking.h index 4dbaeb7..9324489 100644 --- a/hal/phydm/phydm_cfotracking.h +++ b/hal/phydm/phydm_cfotracking.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __PHYDMCFOTRACK_H__ @@ -18,14 +28,13 @@ #define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/ -#define CFO_TH_XTAL_HIGH 20 /* kHz */ -#define CFO_TH_XTAL_LOW 10 /* kHz */ -#define CFO_TH_ATC 80 /* kHz */ +#define CFO_TRK_ENABLE_TH 20 /* (kHz) enable CFO Tracking threshold*/ +#define CFO_TRK_STOP_TH 10 /* (kHz) disable CFO Tracking threshold*/ +#define CFO_TH_ATC 80 /* kHz */ -struct _CFO_TRACKING_ { - boolean is_atc_status; - boolean large_cfo_hit; - boolean is_adjust; +struct phydm_cfo_track_struct { + boolean is_atc_status; + boolean is_adjust; /*already modify crystal cap*/ u8 crystal_cap; u8 def_x_cap; s32 CFO_tail[4]; @@ -33,36 +42,28 @@ struct _CFO_TRACKING_ { s32 CFO_ave_pre; u32 packet_count; u32 packet_count_pre; - - boolean is_force_xtal_cap; - boolean is_reset; }; void phydm_set_crystal_cap( - void *p_dm_void, + void *dm_void, u8 crystal_cap ); void -odm_cfo_tracking_reset( - void *p_dm_void -); - -void -odm_cfo_tracking_init( - void *p_dm_void +phydm_cfo_tracking_init( + void *dm_void ); void -odm_cfo_tracking( - void *p_dm_void +phydm_cfo_tracking( + void *dm_void ); void -odm_parsing_cfo( - void *p_dm_void, - void *p_pktinfo_void, +phydm_parsing_cfo( + void *dm_void, + void *pktinfo_void, s8 *pcfotail, u8 num_ss ); diff --git a/hal/phydm/phydm_debug.c b/hal/phydm/phydm_debug.c index 31958ce..3599e65 100644 --- a/hal/phydm/phydm_debug.c +++ b/hal/phydm/phydm_debug.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -22,67 +32,70 @@ void phydm_init_debug_setting( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - p_dm_odm->debug_level = ODM_DBG_TRACE; + dm->debug_level = ODM_DBG_TRACE; - p_dm_odm->fw_debug_components = 0; - p_dm_odm->debug_components = + dm->fw_debug_components = 0; + dm->debug_components = \ #if DBG /*BB Functions*/ - /* ODM_COMP_DIG |*/ - /* ODM_COMP_RA_MASK |*/ - /* ODM_COMP_DYNAMIC_TXPWR |*/ - /* ODM_COMP_FA_CNT |*/ - /* ODM_COMP_RSSI_MONITOR |*/ - /* ODM_COMP_SNIFFER |*/ - /* ODM_COMP_ANT_DIV |*/ - /* ODM_COMP_NOISY_DETECT |*/ - /* ODM_COMP_RATE_ADAPTIVE |*/ - /* ODM_COMP_PATH_DIV |*/ - /* ODM_COMP_DYNAMIC_PRICCA |*/ - /* ODM_COMP_MP |*/ - /* ODM_COMP_CFO_TRACKING |*/ - /* ODM_COMP_ACS |*/ - /* PHYDM_COMP_ADAPTIVITY |*/ - /* PHYDM_COMP_RA_DBG |*/ - /* PHYDM_COMP_TXBF |*/ - - /*MAC Functions*/ - /* ODM_COMP_EDCA_TURBO |*/ - /* ODM_COMP_DYNAMIC_RX_PATH |*/ - /* ODM_FW_DEBUG_TRACE |*/ - - /*RF Functions*/ - /* ODM_COMP_TX_PWR_TRACK |*/ + /* DBG_DIG |*/ + /* DBG_RA_MASK |*/ + /* DBG_DYN_TXPWR |*/ + /* DBG_FA_CNT |*/ + /* DBG_RSSI_MNTR |*/ + /* DBG_CCKPD |*/ + /* DBG_ANT_DIV |*/ + /* DBG_SMT_ANT |*/ + /* DBG_PWR_TRAIN |*/ + /* DBG_RA |*/ + /* DBG_PATH_DIV |*/ + /* DBG_DFS |*/ + /* DBG_DYN_ARFR |*/ + /* DBG_ADPTVTY |*/ + /* DBG_CFO_TRK |*/ + /* DBG_ENV_MNTR |*/ + /* DBG_PRI_CCA |*/ + /* DBG_ADPTV_SOML |*/ + /* DBG_LNA_SAT_CHK |*/ + /* DBG_DYN_RX_PATH |*/ + /* DBG_PHY_STATUS |*/ + /* DBG_TMP |*/ + /* DBG_FW_TRACE |*/ + /* DBG_TXBF |*/ + /* DBG_COMMON_FLOW |*/ + /* ODM_COMP_TX_PWR_TRACK |*/ /* ODM_COMP_CALIBRATION |*/ - - /*Common*/ + /* ODM_COMP_MP |*/ /* ODM_PHY_CONFIG |*/ /* ODM_COMP_INIT |*/ /* ODM_COMP_COMMON |*/ - /* ODM_COMP_API |*/ + /* ODM_COMP_API |*/ #endif 0; - p_dm_odm->fw_buff_is_enpty = true; - p_dm_odm->pre_c2h_seq = 0; + dm->fw_buff_is_enpty = true; + dm->pre_c2h_seq = 0; + dm->c2h_cmd_start = 0; + dm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD; + dm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD; } void phydm_bb_dbg_port_header_sel( - void *p_dm_void, + void *dm_void, u32 header_idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, 0x8f8, (BIT(25) | BIT(24) | BIT(23) | BIT(22)), header_idx); + odm_set_bb_reg(dm, 0x8f8, (BIT(25) | BIT(24) | BIT(23) | BIT(22)), header_idx); /* header_idx: @@ -104,43 +117,42 @@ phydm_bb_dbg_port_header_sel( void phydm_bb_dbg_port_clock_en( - void *p_dm_void, + void *dm_void, u8 enable ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 reg_value = 0; - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814A | ODM_RTL8814B)) { + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814A | ODM_RTL8814B)) { - reg_value = (enable == true) ? 0x7 : 0; - odm_set_bb_reg(p_dm_odm, 0x198c, 0x7, reg_value); /*enable/disable debug port clock, for power saving*/ + reg_value = enable ? 0x7 : 0; + odm_set_bb_reg(dm, 0x198c, 0x7, reg_value); /*enable/disable debug port clock, for power saving*/ } } u8 phydm_set_bb_dbg_port( - void *p_dm_void, + void *dm_void, u8 curr_dbg_priority, u32 debug_port ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 dbg_port_result = false; - if (curr_dbg_priority > p_dm_odm->pre_dbg_priority) { - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (curr_dbg_priority > dm->pre_dbg_priority) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { - phydm_bb_dbg_port_clock_en(p_dm_odm, TRUE); + phydm_bb_dbg_port_clock_en(dm, true); - odm_set_bb_reg(p_dm_odm, 0x8fc, MASKDWORD, debug_port); + odm_set_bb_reg(dm, 0x8fc, MASKDWORD, debug_port); /**/ - } else /*if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)*/ { - odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, debug_port); + } else /*if (dm->support_ic_type & ODM_IC_11N_SERIES)*/ { + odm_set_bb_reg(dm, 0x908, MASKDWORD, debug_port); /**/ } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("DbgPort set success, Reg((0x%x)), Cur_priority=((%d)), Pre_priority=((%d))\n", debug_port, curr_dbg_priority, p_dm_odm->pre_dbg_priority)); - p_dm_odm->pre_dbg_priority = curr_dbg_priority; + PHYDM_DBG(dm, ODM_COMP_API, "DbgPort ((0x%x)) set success, Cur_priority=((%d)), Pre_priority=((%d))\n", debug_port, curr_dbg_priority, dm->pre_dbg_priority); + dm->pre_dbg_priority = curr_dbg_priority; dbg_port_result = true; } @@ -149,224 +161,48 @@ phydm_set_bb_dbg_port( void phydm_release_bb_dbg_port( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - phydm_bb_dbg_port_clock_en(p_dm_odm, FALSE); - phydm_bb_dbg_port_header_sel(p_dm_odm, 0); + phydm_bb_dbg_port_clock_en(dm, false); + phydm_bb_dbg_port_header_sel(dm, 0); - p_dm_odm->pre_dbg_priority = BB_DBGPORT_RELEASE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Release BB dbg_port\n")); + dm->pre_dbg_priority = BB_DBGPORT_RELEASE; + PHYDM_DBG(dm, ODM_COMP_API, "Release BB dbg_port\n"); } u32 phydm_get_bb_dbg_port_value( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 dbg_port_value = 0; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - dbg_port_value = odm_get_bb_reg(p_dm_odm, 0xfa0, MASKDWORD); + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + dbg_port_value = odm_get_bb_reg(dm, 0xfa0, MASKDWORD); /**/ - } else /*if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)*/ { - dbg_port_value = odm_get_bb_reg(p_dm_odm, 0xdf4, MASKDWORD); + } else /*if (dm->support_ic_type & ODM_IC_11N_SERIES)*/ { + dbg_port_value = odm_get_bb_reg(dm, 0xdf4, MASKDWORD); /**/ } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("dbg_port_value = 0x%x\n", dbg_port_value)); + PHYDM_DBG(dm, ODM_COMP_API, "dbg_port_value = 0x%x\n", dbg_port_value); return dbg_port_value; } -#if CONFIG_PHYDM_DEBUG_FUNCTION -void -phydm_bb_rx_hang_info( - void *p_dm_void, - u32 *_used, - char *output, - u32 *_out_len -) -{ - u32 value32 = 0; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 used = *_used; - u32 out_len = *_out_len; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - return; - - value32 = odm_get_bb_reg(p_dm_odm, 0xF80, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32)); - - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - odm_set_bb_reg(p_dm_odm, 0x198c, BIT(2) | BIT(1) | BIT(0), 7); - - /* dbg_port = basic state machine */ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "basic state machine", value32)); - } - - /* dbg_port = state machine */ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "state machine", value32)); - } - - /* dbg_port = CCA-related*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "CCA-related", value32)); - } - - - /* dbg_port = edcca/rxd*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "edcca/rxd", value32)); - } - - /* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx_state/mux_state/ADC_MASK_OFDM", value32)); - } - - /* dbg_port = bf-related*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "bf-related", value32)); - } - - /* dbg_port = bf-related*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "bf-related", value32)); - } - - /* dbg_port = txon/rxd*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "txon/rxd", value32)); - } - - /* dbg_port = l_rate/l_length*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "l_rate/l_length", value32)); - } - - /* dbg_port = rxd/rxd_hit*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32)); - } - - /* dbg_port = dis_cca*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "dis_cca", value32)); - } - - - /* dbg_port = tx*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "tx", value32)); - } - - /* dbg_port = rx plcp*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - } - -} +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION void phydm_bb_debug_info_n_series( - void *p_dm_void, + void *dm_void, u32 *_used, char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 used = *_used; u32 out_len = *_out_len; @@ -379,10 +215,11 @@ phydm_bb_debug_info_n_series( s32 scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0; s32 cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a = 0, acq_cfo_b = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s\n", "BB Report Info")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s\n", "BB Report Info"); /*AGC result*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xdd0, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xdd0, MASKDWORD); rf_gain_a = (u8)(value32 & 0x3f); rf_gain_a = rf_gain_a << 1; @@ -395,10 +232,13 @@ phydm_bb_debug_info_n_series( rf_gain_d = (u8)((value32 >> 24) & 0x3f); rf_gain_d = rf_gain_d << 1; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", rf_gain_a, rf_gain_b, rf_gain_c, rf_gain_d)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d / %d", + "OFDM RX RF Gain(A/B/C/D)", rf_gain_a, rf_gain_b, + rf_gain_c, rf_gain_d); /*SNR report*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xdd4, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xdd4, MASKDWORD); rx_snr_a = (u8)(value32 & 0xff); rx_snr_a = rx_snr_a >> 1; @@ -411,10 +251,12 @@ phydm_bb_debug_info_n_series( rx_snr_d = (u8)((value32 >> 24) & 0xff); rx_snr_d = rx_snr_d >> 1; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", + rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d); /* PostFFT related info*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xdd8, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xdd8, MASKDWORD); rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); rxevm_0 /= 2; @@ -426,14 +268,16 @@ phydm_bb_debug_info_n_series( if (rxevm_1 < -63) rxevm_1 = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "RXEVM (1ss/2ss)", rxevm_0, rxevm_1)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "RXEVM (1ss/2ss)", rxevm_0, + rxevm_1); /*CFO Report Info*/ - odm_set_bb_reg(p_dm_odm, 0xd00, BIT(26), 1); + odm_set_bb_reg(dm, 0xd00, BIT(26), 1); /*Short CFO*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xdac, MASKDWORD); - value32_1 = odm_get_bb_reg(p_dm_odm, 0xdb0, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xdac, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, 0xdb0, MASKDWORD); short_cfo_b = (s32)(value32 & 0xfff); /*S(12,11)*/ short_cfo_a = (s32)((value32 & 0x0fff0000) >> 16); @@ -461,13 +305,18 @@ phydm_bb_debug_info_n_series( long_cfo_a = long_cfo_a * 312500 / 4096; long_cfo_b = long_cfo_b * 312500 / 4096; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "CFO Report Info")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Short CFO(Hz) ", short_cfo_a, short_cfo_b)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Long CFO(Hz) ", long_cfo_a, long_cfo_b)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "CFO Report Info"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "Short CFO(Hz) ", + short_cfo_a, short_cfo_b); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "Long CFO(Hz) ", + long_cfo_a, long_cfo_b); /*SCFO*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xdb8, MASKDWORD); - value32_1 = odm_get_bb_reg(p_dm_odm, 0xdb4, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xdb8, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, 0xdb4, MASKDWORD); scfo_b = (s32)(value32 & 0x7ff); /*S(11,10)*/ scfo_a = (s32)((value32 & 0x07ff0000) >> 16); @@ -493,11 +342,15 @@ phydm_bb_debug_info_n_series( avg_cfo_a = avg_cfo_a * 312500 / 4096; avg_cfo_b = avg_cfo_b * 312500 / 4096; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "value SCFO(Hz) ", scfo_a, scfo_b)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Avg CFO(Hz) ", avg_cfo_a, avg_cfo_b)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "value SCFO(Hz) ", scfo_a, + scfo_b); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "Avg CFO(Hz) ", avg_cfo_a, + avg_cfo_b); - value32 = odm_get_bb_reg(p_dm_odm, 0xdbc, MASKDWORD); - value32_1 = odm_get_bb_reg(p_dm_odm, 0xde0, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xdbc, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, 0xde0, MASKDWORD); cfo_end_b = (s32)(value32 & 0x1fff); /*S(13,12)*/ cfo_end_a = (s32)((value32 & 0x1fff0000) >> 16); @@ -523,39 +376,43 @@ phydm_bb_debug_info_n_series( acq_cfo_a = acq_cfo_a * 312500 / 4096; acq_cfo_b = acq_cfo_b * 312500 / 4096; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "End CFO(Hz) ", cfo_end_a, cfo_end_b)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "ACQ CFO(Hz) ", acq_cfo_a, acq_cfo_b)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "End CFO(Hz) ", cfo_end_a, + cfo_end_b); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "ACQ CFO(Hz) ", acq_cfo_a, + acq_cfo_b); } void phydm_bb_debug_info( - void *p_dm_void, + void *dm_void, u32 *_used, - char *output, + char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 used = *_used; u32 out_len = *_out_len; char *tmp_string = NULL; - u8 RX_HT_BW, RX_VHT_BW, RXSC, RX_HT, RX_BW; + u8 rx_ht_bw, rx_vht_bw, rxsc, rx_ht, rx_bw; static u8 v_rx_bw ; u32 value32, value32_1, value32_2, value32_3; - s32 SFO_A, SFO_B, SFO_C, SFO_D; - s32 LFO_A, LFO_B, LFO_C, LFO_D; + s32 sfo_a, sfo_b, sfo_c, sfo_d; + s32 lfo_a, lfo_b, lfo_c, lfo_d; static u8 MCSS, tail, parity, rsv, vrsv, idx, smooth, htsound, agg, stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts, vtxops, vrsv2, vbrsv, bf, vbcrc; static u16 h_length, htcrc8, length; static u16 vpaid; static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail; - static u8 HMCSS, HRX_BW; + static u8 hmcss, hrx_bw; u8 pwdb; - s8 RXEVM_0, RXEVM_1, RXEVM_2 ; + s8 rxevm_0, rxevm_1, rxevm_2 ; u8 rf_gain_path_a, rf_gain_path_b, rf_gain_path_c, rf_gain_path_d; u8 rx_snr_path_a, rx_snr_path_b, rx_snr_path_c, rx_snr_path_d; s32 sig_power; @@ -569,275 +426,317 @@ phydm_bb_debug_info( const double evm_comp_160M = 0.244245993314183; /* 10*log10(512.0/484.0) */ #endif - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - phydm_bb_debug_info_n_series(p_dm_odm, &used, output, &out_len); + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + phydm_bb_debug_info_n_series(dm, &used, output, &out_len); return; } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s\n", "BB Report Info")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s\n", "BB Report Info"); /*BW & mode Detection*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xf80, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xf80, MASKDWORD); value32_2 = value32; - RX_HT_BW = (u8)(value32 & 0x1); - RX_VHT_BW = (u8)((value32 >> 1) & 0x3); - RXSC = (u8)(value32 & 0x78); + rx_ht_bw = (u8)(value32 & 0x1); + rx_vht_bw = (u8)((value32 >> 1) & 0x3); + rxsc = (u8)(value32 & 0x78); value32_1 = (value32 & 0x180) >> 7; - RX_HT = (u8)(value32_1); + rx_ht = (u8)(value32_1); - RX_BW = 0; + rx_bw = 0; - if (RX_HT == 2) { - if (RX_VHT_BW == 0) + if (rx_ht == 2) { + if (rx_vht_bw == 0) tmp_string = "20M"; - else if (RX_VHT_BW == 1) + else if (rx_vht_bw == 1) tmp_string = "40M"; else tmp_string = "80M"; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s %s", "mode", "VHT", tmp_string)); - RX_BW = RX_VHT_BW; - } else if (RX_HT == 1) { - if (RX_HT_BW == 0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s %s %s", "mode", "VHT", tmp_string); + rx_bw = rx_vht_bw; + } else if (rx_ht == 1) { + if (rx_ht_bw == 0) tmp_string = "20M"; - else if (RX_HT_BW == 1) + else if (rx_ht_bw == 1) tmp_string = "40M"; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s %s", "mode", "HT", tmp_string)); - RX_BW = RX_HT_BW; + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s %s %s", "mode", "HT", tmp_string); + rx_bw = rx_ht_bw; } else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s", "mode", "Legacy")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s %s", "mode", "Legacy"); - if (RX_HT != 0) { - if (RXSC == 0) + if (rx_ht != 0) { + if (rxsc == 0) tmp_string = "duplicate/full bw"; - else if (RXSC == 1) + else if (rxsc == 1) tmp_string = "usc20-1"; - else if (RXSC == 2) + else if (rxsc == 2) tmp_string = "lsc20-1"; - else if (RXSC == 3) + else if (rxsc == 3) tmp_string = "usc20-2"; - else if (RXSC == 4) + else if (rxsc == 4) tmp_string = "lsc20-2"; - else if (RXSC == 9) + else if (rxsc == 9) tmp_string = "usc40"; - else if (RXSC == 10) + else if (rxsc == 10) tmp_string = "lsc40"; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s", tmp_string)); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s", tmp_string); } /* RX signal power and AGC related info*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xF90, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xF90, MASKDWORD); pwdb = (u8)((value32 & MASKBYTE1) >> 8); pwdb = pwdb >> 1; sig_power = -110 + pwdb; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", sig_power)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", + sig_power); - value32 = odm_get_bb_reg(p_dm_odm, 0xd14, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xd14, MASKDWORD); rx_snr_path_a = (u8)(value32 & 0xFF) >> 1; rf_gain_path_a = (s8)((value32 & MASKBYTE1) >> 8); rf_gain_path_a *= 2; - value32 = odm_get_bb_reg(p_dm_odm, 0xd54, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xd54, MASKDWORD); rx_snr_path_b = (u8)(value32 & 0xFF) >> 1; rf_gain_path_b = (s8)((value32 & MASKBYTE1) >> 8); rf_gain_path_b *= 2; - value32 = odm_get_bb_reg(p_dm_odm, 0xd94, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xd94, MASKDWORD); rx_snr_path_c = (u8)(value32 & 0xFF) >> 1; rf_gain_path_c = (s8)((value32 & MASKBYTE1) >> 8); rf_gain_path_c *= 2; - value32 = odm_get_bb_reg(p_dm_odm, 0xdd4, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xdd4, MASKDWORD); rx_snr_path_d = (u8)(value32 & 0xFF) >> 1; rf_gain_path_d = (s8)((value32 & MASKBYTE1) >> 8); rf_gain_path_d *= 2; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", rf_gain_path_a, rf_gain_path_b, rf_gain_path_c, rf_gain_path_d)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d / %d", + "OFDM RX RF Gain(A/B/C/D)", rf_gain_path_a, + rf_gain_path_b, rf_gain_path_c, rf_gain_path_d); /* RX counter related info*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xF08, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM CCA counter", ((value32 & 0xFFFF0000) >> 16))); - - value32 = odm_get_bb_reg(p_dm_odm, 0xFD0, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM SBD Fail counter", value32 & 0xFFFF)); - - value32 = odm_get_bb_reg(p_dm_odm, 0xFC4, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail counter", value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16))); - - value32 = odm_get_bb_reg(p_dm_odm, 0xFCC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "CCK CCA counter", value32 & 0xFFFF)); - - value32 = odm_get_bb_reg(p_dm_odm, 0xFBC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "LSIG (parity Fail/rate Illegal) counter", value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16))); - - value32_1 = odm_get_bb_reg(p_dm_odm, 0xFC8, MASKDWORD); - value32_2 = odm_get_bb_reg(p_dm_odm, 0xFC0, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT counter", ((value32_2 & 0xFFFF0000) >> 16), value32_1 & 0xFFFF)); + value32 = odm_get_bb_reg(dm, 0xF08, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM CCA counter", + ((value32 & 0xFFFF0000) >> 16)); + + value32 = odm_get_bb_reg(dm, 0xFD0, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM SBD Fail counter", + value32 & 0xFFFF); + + value32 = odm_get_bb_reg(dm, 0xFC4, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", + "VHT SIGA/SIGB CRC8 Fail counter", value32 & 0xFFFF, + ((value32 & 0xFFFF0000) >> 16)); + + value32 = odm_get_bb_reg(dm, 0xFCC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "CCK CCA counter", value32 & 0xFFFF); + + value32 = odm_get_bb_reg(dm, 0xFBC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", + "LSIG (parity Fail/rate Illegal) counter", + value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16)); + + value32_1 = odm_get_bb_reg(dm, 0xFC8, MASKDWORD); + value32_2 = odm_get_bb_reg(dm, 0xFC0, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", + "HT/VHT MCS NOT SUPPORT counter", + ((value32_2 & 0xFFFF0000) >> 16), value32_1 & 0xFFFF); /* PostFFT related info*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xF8c, MASKDWORD); - RXEVM_0 = (s8)((value32 & MASKBYTE2) >> 16); - RXEVM_0 /= 2; - if (RXEVM_0 < -63) - RXEVM_0 = 0; - - RXEVM_1 = (s8)((value32 & MASKBYTE3) >> 24); - RXEVM_1 /= 2; - value32 = odm_get_bb_reg(p_dm_odm, 0xF88, MASKDWORD); - RXEVM_2 = (s8)((value32 & MASKBYTE2) >> 16); - RXEVM_2 /= 2; - - if (RXEVM_1 < -63) - RXEVM_1 = 0; - if (RXEVM_2 < -63) - RXEVM_2 = 0; + value32 = odm_get_bb_reg(dm, 0xF8c, MASKDWORD); + rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_0 /= 2; + if (rxevm_0 < -63) + rxevm_0 = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", RXEVM_0, RXEVM_1, RXEVM_2)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", rx_snr_path_a, rx_snr_path_b, rx_snr_path_c, rx_snr_path_d)); + rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24); + rxevm_1 /= 2; + value32 = odm_get_bb_reg(dm, 0xF88, MASKDWORD); + rxevm_2 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_2 /= 2; - value32 = odm_get_bb_reg(p_dm_odm, 0xF8C, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16))); + if (rxevm_1 < -63) + rxevm_1 = 0; + if (rxevm_2 < -63) + rxevm_2 = 0; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", + rxevm_0, rxevm_1, rxevm_2); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", + rx_snr_path_a, rx_snr_path_b, rx_snr_path_c, + rx_snr_path_d); + + value32 = odm_get_bb_reg(dm, 0xF8C, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", + value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16)); /*BW & mode Detection*/ /*Reset Page F counter*/ - odm_set_bb_reg(p_dm_odm, 0xB58, BIT(0), 1); - odm_set_bb_reg(p_dm_odm, 0xB58, BIT(0), 0); + odm_set_bb_reg(dm, 0xB58, BIT(0), 1); + odm_set_bb_reg(dm, 0xB58, BIT(0), 0); /*CFO Report Info*/ /*Short CFO*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xd0c, MASKDWORD); - value32_1 = odm_get_bb_reg(p_dm_odm, 0xd4c, MASKDWORD); - value32_2 = odm_get_bb_reg(p_dm_odm, 0xd8c, MASKDWORD); - value32_3 = odm_get_bb_reg(p_dm_odm, 0xdcc, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xd0c, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, 0xd4c, MASKDWORD); + value32_2 = odm_get_bb_reg(dm, 0xd8c, MASKDWORD); + value32_3 = odm_get_bb_reg(dm, 0xdcc, MASKDWORD); - SFO_A = (s32)(value32 & 0xfff); - SFO_B = (s32)(value32_1 & 0xfff); - SFO_C = (s32)(value32_2 & 0xfff); - SFO_D = (s32)(value32_3 & 0xfff); + sfo_a = (s32)(value32 & 0xfff); + sfo_b = (s32)(value32_1 & 0xfff); + sfo_c = (s32)(value32_2 & 0xfff); + sfo_d = (s32)(value32_3 & 0xfff); - LFO_A = (s32)(value32 >> 16); - LFO_B = (s32)(value32_1 >> 16); - LFO_C = (s32)(value32_2 >> 16); - LFO_D = (s32)(value32_3 >> 16); + lfo_a = (s32)(value32 >> 16); + lfo_b = (s32)(value32_1 >> 16); + lfo_c = (s32)(value32_2 >> 16); + lfo_d = (s32)(value32_3 >> 16); /*SFO 2's to dec*/ - if (SFO_A > 2047) - SFO_A = SFO_A - 4096; - SFO_A = (SFO_A * 312500) / 2048; - if (SFO_B > 2047) - SFO_B = SFO_B - 4096; - SFO_B = (SFO_B * 312500) / 2048; - if (SFO_C > 2047) - SFO_C = SFO_C - 4096; - SFO_C = (SFO_C * 312500) / 2048; - if (SFO_D > 2047) - SFO_D = SFO_D - 4096; - SFO_D = (SFO_D * 312500) / 2048; + if (sfo_a > 2047) + sfo_a = sfo_a - 4096; + sfo_a = (sfo_a * 312500) / 2048; + if (sfo_b > 2047) + sfo_b = sfo_b - 4096; + sfo_b = (sfo_b * 312500) / 2048; + if (sfo_c > 2047) + sfo_c = sfo_c - 4096; + sfo_c = (sfo_c * 312500) / 2048; + if (sfo_d > 2047) + sfo_d = sfo_d - 4096; + sfo_d = (sfo_d * 312500) / 2048; /*LFO 2's to dec*/ - if (LFO_A > 4095) - LFO_A = LFO_A - 8192; - - if (LFO_B > 4095) - LFO_B = LFO_B - 8192; - - if (LFO_C > 4095) - LFO_C = LFO_C - 8192; - - if (LFO_D > 4095) - LFO_D = LFO_D - 8192; - LFO_A = LFO_A * 312500 / 4096; - LFO_B = LFO_B * 312500 / 4096; - LFO_C = LFO_C * 312500 / 4096; - LFO_D = LFO_D * 312500 / 4096; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "CFO Report Info")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "Short CFO(Hz) ", SFO_A, SFO_B, SFO_C, SFO_D)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "Long CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); + if (lfo_a > 4095) + lfo_a = lfo_a - 8192; + + if (lfo_b > 4095) + lfo_b = lfo_b - 8192; + + if (lfo_c > 4095) + lfo_c = lfo_c - 8192; + + if (lfo_d > 4095) + lfo_d = lfo_d - 8192; + lfo_a = lfo_a * 312500 / 4096; + lfo_b = lfo_b * 312500 / 4096; + lfo_c = lfo_c * 312500 / 4096; + lfo_d = lfo_d * 312500 / 4096; + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "CFO Report Info"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d /%d", + "Short CFO(Hz) ", sfo_a, sfo_b, sfo_c, sfo_d); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d /%d", + "Long CFO(Hz) ", lfo_a, lfo_b, lfo_c, lfo_d); /*SCFO*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xd10, MASKDWORD); - value32_1 = odm_get_bb_reg(p_dm_odm, 0xd50, MASKDWORD); - value32_2 = odm_get_bb_reg(p_dm_odm, 0xd90, MASKDWORD); - value32_3 = odm_get_bb_reg(p_dm_odm, 0xdd0, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xd10, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, 0xd50, MASKDWORD); + value32_2 = odm_get_bb_reg(dm, 0xd90, MASKDWORD); + value32_3 = odm_get_bb_reg(dm, 0xdd0, MASKDWORD); - SFO_A = (s32)(value32 & 0x7ff); - SFO_B = (s32)(value32_1 & 0x7ff); - SFO_C = (s32)(value32_2 & 0x7ff); - SFO_D = (s32)(value32_3 & 0x7ff); + sfo_a = (s32)(value32 & 0x7ff); + sfo_b = (s32)(value32_1 & 0x7ff); + sfo_c = (s32)(value32_2 & 0x7ff); + sfo_d = (s32)(value32_3 & 0x7ff); - if (SFO_A > 1023) - SFO_A = SFO_A - 2048; + if (sfo_a > 1023) + sfo_a = sfo_a - 2048; - if (SFO_B > 2047) - SFO_B = SFO_B - 4096; + if (sfo_b > 2047) + sfo_b = sfo_b - 4096; - if (SFO_C > 2047) - SFO_C = SFO_C - 4096; + if (sfo_c > 2047) + sfo_c = sfo_c - 4096; - if (SFO_D > 2047) - SFO_D = SFO_D - 4096; + if (sfo_d > 2047) + sfo_d = sfo_d - 4096; - SFO_A = SFO_A * 312500 / 1024; - SFO_B = SFO_B * 312500 / 1024; - SFO_C = SFO_C * 312500 / 1024; - SFO_D = SFO_D * 312500 / 1024; + sfo_a = sfo_a * 312500 / 1024; + sfo_b = sfo_b * 312500 / 1024; + sfo_c = sfo_c * 312500 / 1024; + sfo_d = sfo_d * 312500 / 1024; - LFO_A = (s32)(value32 >> 16); - LFO_B = (s32)(value32_1 >> 16); - LFO_C = (s32)(value32_2 >> 16); - LFO_D = (s32)(value32_3 >> 16); + lfo_a = (s32)(value32 >> 16); + lfo_b = (s32)(value32_1 >> 16); + lfo_c = (s32)(value32_2 >> 16); + lfo_d = (s32)(value32_3 >> 16); - if (LFO_A > 4095) - LFO_A = LFO_A - 8192; + if (lfo_a > 4095) + lfo_a = lfo_a - 8192; - if (LFO_B > 4095) - LFO_B = LFO_B - 8192; + if (lfo_b > 4095) + lfo_b = lfo_b - 8192; - if (LFO_C > 4095) - LFO_C = LFO_C - 8192; + if (lfo_c > 4095) + lfo_c = lfo_c - 8192; - if (LFO_D > 4095) - LFO_D = LFO_D - 8192; - LFO_A = LFO_A * 312500 / 4096; - LFO_B = LFO_B * 312500 / 4096; - LFO_C = LFO_C * 312500 / 4096; - LFO_D = LFO_D * 312500 / 4096; + if (lfo_d > 4095) + lfo_d = lfo_d - 8192; + lfo_a = lfo_a * 312500 / 4096; + lfo_b = lfo_b * 312500 / 4096; + lfo_c = lfo_c * 312500 / 4096; + lfo_d = lfo_d * 312500 / 4096; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "value SCFO(Hz) ", SFO_A, SFO_B, SFO_C, SFO_D)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "ACQ CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d /%d", + "value SCFO(Hz) ", sfo_a, sfo_b, sfo_c, sfo_d); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d /%d", + "ACQ CFO(Hz) ", lfo_a, lfo_b, lfo_c, lfo_d); - value32 = odm_get_bb_reg(p_dm_odm, 0xd14, MASKDWORD); - value32_1 = odm_get_bb_reg(p_dm_odm, 0xd54, MASKDWORD); - value32_2 = odm_get_bb_reg(p_dm_odm, 0xd94, MASKDWORD); - value32_3 = odm_get_bb_reg(p_dm_odm, 0xdd4, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xd14, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, 0xd54, MASKDWORD); + value32_2 = odm_get_bb_reg(dm, 0xd94, MASKDWORD); + value32_3 = odm_get_bb_reg(dm, 0xdd4, MASKDWORD); - LFO_A = (s32)(value32 >> 16); - LFO_B = (s32)(value32_1 >> 16); - LFO_C = (s32)(value32_2 >> 16); - LFO_D = (s32)(value32_3 >> 16); + lfo_a = (s32)(value32 >> 16); + lfo_b = (s32)(value32_1 >> 16); + lfo_c = (s32)(value32_2 >> 16); + lfo_d = (s32)(value32_3 >> 16); - if (LFO_A > 4095) - LFO_A = LFO_A - 8192; + if (lfo_a > 4095) + lfo_a = lfo_a - 8192; - if (LFO_B > 4095) - LFO_B = LFO_B - 8192; + if (lfo_b > 4095) + lfo_b = lfo_b - 8192; - if (LFO_C > 4095) - LFO_C = LFO_C - 8192; + if (lfo_c > 4095) + lfo_c = lfo_c - 8192; - if (LFO_D > 4095) - LFO_D = LFO_D - 8192; + if (lfo_d > 4095) + lfo_d = lfo_d - 8192; - LFO_A = LFO_A * 312500 / 4096; - LFO_B = LFO_B * 312500 / 4096; - LFO_C = LFO_C * 312500 / 4096; - LFO_D = LFO_D * 312500 / 4096; + lfo_a = lfo_a * 312500 / 4096; + lfo_b = lfo_b * 312500 / 4096; + lfo_c = lfo_c * 312500 / 4096; + lfo_d = lfo_d * 312500 / 4096; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "End CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d /%d", + "End CFO(Hz) ", lfo_a, lfo_b, lfo_c, lfo_d); - value32 = odm_get_bb_reg(p_dm_odm, 0xf20, MASKDWORD); /*L SIG*/ + value32 = odm_get_bb_reg(dm, 0xf20, MASKDWORD); /*L SIG*/ tail = (u8)((value32 & 0xfc0000) >> 16); parity = (u8)((value32 & 0x20000) >> 16); @@ -873,23 +772,29 @@ phydm_bb_debug_info( } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "L-SIG")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s : %s", "rate", L_rate[idx])); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x", "Rsv/length/parity", rsv, RX_BW, length)); - - value32 = odm_get_bb_reg(p_dm_odm, 0xf2c, MASKDWORD); /*HT SIG*/ - if (RX_HT == 1) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "L-SIG"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s : %s", "rate", L_rate[idx]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x", "Rsv/length/parity", rsv, + rx_bw, length); - HMCSS = (u8)(value32 & 0x7F); - HRX_BW = (u8)(value32 & 0x80); + value32 = odm_get_bb_reg(dm, 0xf2c, MASKDWORD); /*HT SIG*/ + if (rx_ht == 1) { + hmcss = (u8)(value32 & 0x7F); + hrx_bw = (u8)(value32 & 0x80); h_length = (u16)((value32 >> 8) & 0xffff); } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "HT-SIG1")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x", "MCS/BW/length", HMCSS, HRX_BW, h_length)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "HT-SIG1"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x", "MCS/BW/length", hmcss, + hrx_bw, h_length); - value32 = odm_get_bb_reg(p_dm_odm, 0xf30, MASKDWORD); /*HT SIG*/ + value32 = odm_get_bb_reg(dm, 0xf30, MASKDWORD); /*HT SIG*/ - if (RX_HT == 1) { + if (rx_ht == 1) { smooth = (u8)(value32 & 0x01); htsound = (u8)(value32 & 0x02); rsv = (u8)(value32 & 0x04); @@ -901,13 +806,19 @@ phydm_bb_debug_info( htcrc8 = (u16)((value32 & 0x3fc00) >> 8); tail = (u8)((value32 & 0xfc0000) >> 16); } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "HT-SIG2")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x", "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", smooth, htsound, rsv, agg, stbc, fec)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x", "SGI/E-HT-LTFs/CRC/tail", sgi, htltf, htcrc8, tail)); - - value32 = odm_get_bb_reg(p_dm_odm, 0xf2c, MASKDWORD); /*VHT SIG A1*/ - if (RX_HT == 2) { - /* value32 = odm_get_bb_reg(p_dm_odm, 0xf2c,MASKDWORD);*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "HT-SIG2"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x", + "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", smooth, + htsound, rsv, agg, stbc, fec); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x", + "SGI/E-HT-LTFs/CRC/tail", sgi, htltf, htcrc8, tail); + + value32 = odm_get_bb_reg(dm, 0xf2c, MASKDWORD); /*VHT SIG A1*/ + if (rx_ht == 2) { + /* value32 = odm_get_bb_reg(dm, 0xf2c,MASKDWORD);*/ v_rx_bw = (u8)(value32 & 0x03); vrsv = (u8)(value32 & 0x04); vstbc = (u8)(value32 & 0x08); @@ -917,13 +828,17 @@ phydm_bb_debug_info( vtxops = (u8)((value32 & 0x400000) >> 20); vrsv2 = (u8)((value32 & 0x800000) >> 20); } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-A1")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x", "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw, vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "VHT-SIG-A1"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x", + "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw, + vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2); - value32 = odm_get_bb_reg(p_dm_odm, 0xf30, MASKDWORD); /*VHT SIG*/ + value32 = odm_get_bb_reg(dm, 0xf30, MASKDWORD); /*VHT SIG*/ - if (RX_HT == 2) { - /*value32 = odm_get_bb_reg(p_dm_odm, 0xf30,MASKDWORD); */ /*VHT SIG*/ + if (rx_ht == 2) { + /*value32 = odm_get_bb_reg(dm, 0xf30,MASKDWORD); */ /*VHT SIG*/ /* sgi=(u8)(value32&0x01); */ sgiext = (u8)(value32 & 0x03); @@ -936,10 +851,14 @@ phydm_bb_debug_info( vhtcrc8 = (u16)((value32 & 0x3fc00) >> 8); v_tail = (u8)((value32 & 0xfc0000) >> 16); } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-A2")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x", "SGI/FEC/MCS/BF/Rsv/CRC/tail", sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "VHT-SIG-A2"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x", + "SGI/FEC/MCS/BF/Rsv/CRC/tail", sgiext, fecext, v_mcss, + bf, vrsv, vhtcrc8, v_tail); - value32 = odm_get_bb_reg(p_dm_odm, 0xf34, MASKDWORD); /*VHT SIG*/ + value32 = odm_get_bb_reg(dm, 0xf34, MASKDWORD); /*VHT SIG*/ { v_length = (u16)(value32 & 0x1fffff); vbrsv = (u8)((value32 & 0x600000) >> 20); @@ -947,44 +866,49 @@ phydm_bb_debug_info( vbcrc = (u8)((value32 & 0x80000000) >> 28); } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-B")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x", "length/Rsv/tail/CRC", v_length, vbrsv, vb_tail, vbcrc)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "VHT-SIG-B"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x", + "length/Rsv/tail/CRC", v_length, vbrsv, vb_tail, vbcrc); /*for Condition number*/ - if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + if (dm->support_ic_type & ODM_RTL8822B) { s32 condition_num = 0; char *factor = NULL; - odm_set_bb_reg(p_dm_odm, 0x1988, BIT(22), 0x1); /*enable report condition number*/ + odm_set_bb_reg(dm, 0x1988, BIT(22), 0x1); /*enable report condition number*/ - condition_num = odm_get_bb_reg(p_dm_odm, 0xf84, MASKDWORD); + condition_num = odm_get_bb_reg(dm, 0xf84, MASKDWORD); condition_num = (condition_num & 0x3ffff) >> 4; - if (*p_dm_odm->p_band_width == ODM_BW80M) + if (*dm->band_width == CHANNEL_WIDTH_80) factor = "256/234"; - else if (*p_dm_odm->p_band_width == ODM_BW40M) + else if (*dm->band_width == CHANNEL_WIDTH_40) factor = "128/108"; - else if (*p_dm_odm->p_band_width == ODM_BW20M) { - if (RX_HT != 2 || RX_HT != 1) + else if (*dm->band_width == CHANNEL_WIDTH_20) { + if (rx_ht != 2 || rx_ht != 1) factor = "64/52"; /*HT or VHT*/ else factor = "64/48"; /*legacy*/ } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d (factor = %s)", "Condition number", condition_num, factor)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d (factor = %s)", + "Condition number", condition_num, factor); } *_used = used; - *_out_len = out_len; + *_out_len = out_len; } -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +#endif /*#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if CONFIG_PHYDM_DEBUG_FUNCTION +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION void phydm_sbd_check( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { static u32 pkt_cnt = 0; @@ -994,131 +918,180 @@ void phydm_sbd_check( if (sbd_state == 0) { pkt_cnt++; if (pkt_cnt % 5 == 0) { /*read SBD conter once every 5 packets*/ - odm_set_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer, 0); /*ms*/ + odm_set_timer(dm, &dm->sbdcnt_timer, 0); /*ms*/ sbd_state = 1; } } else { /*read counter*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xF98, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0xF98, MASKDWORD); sym_count = (value32 & 0x7C000000) >> 26; count = (value32 & 0x3F00000) >> 20; - dbg_print("#SBD# sym_count %d count %d\n", sym_count, count); + pr_debug("#SBD# sym_count %d count %d\n", sym_count, count); sbd_state = 0; } } -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +#endif void phydm_sbd_callback( - struct timer_list *p_timer + struct phydm_timer_list *timer ) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - -#if USE_WORKITEM - odm_schedule_work_item(&p_dm_odm->sbdcnt_workitem); -#else - phydm_sbd_check(p_dm_odm); +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + void *adapter = timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + #if USE_WORKITEM + odm_schedule_work_item(&dm->sbdcnt_workitem); + #else + phydm_sbd_check(dm); + #endif #endif -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ } void phydm_sbd_workitem_callback( - void *p_context + void *context ) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + struct dm_struct *dm = &hal_data->DM_OutSrc; - phydm_sbd_check(p_dm_odm); -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ + phydm_sbd_check(dm); +#endif } #endif +void +phydm_reset_rx_rate_distribution( + struct dm_struct *dm +) +{ + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + + odm_memory_set(dm, &dbg->num_qry_legacy_pkt[0], 0, + (LEGACY_RATE_NUM * 2)); + odm_memory_set(dm, &dbg->num_qry_ht_pkt[0], 0, + (HT_RATE_NUM * 2)); + odm_memory_set(dm, &dbg->num_qry_pkt_sc_20m[0], 0, + (LOW_BW_RATE_NUM * 2)); + + dbg->ht_pkt_not_zero = false; + dbg->low_bw_20_occur = false; + +#if ODM_IC_11AC_SERIES_SUPPORT + odm_memory_set(dm, &dbg->num_qry_vht_pkt[0], 0, + (VHT_RATE_NUM * 2)); + odm_memory_set(dm, &dbg->num_qry_pkt_sc_40m[0], 0, + (LOW_BW_RATE_NUM * 2)); + + dbg->vht_pkt_not_zero = false; + dbg->low_bw_40_occur = false; +#endif +} + void phydm_rx_rate_distribution ( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_phy_dbg_info_ *p_dbg = &(p_dm_odm->phy_dbg_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; u8 i = 0, j = 0; - u8 rate_num = 1, rate_ss_shift = 0; - - if (p_dm_odm->support_ic_type & ODM_IC_4SS) - rate_num = 4; - else if (p_dm_odm->support_ic_type & ODM_IC_3SS) - rate_num = 3; - else if (p_dm_odm->support_ic_type & ODM_IC_2SS) - rate_num = 2; + u8 rate_num = dm->num_rf_path, rate_ss_shift = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[RxRate Cnt] =============> \n")); + PHYDM_DBG(dm, ODM_COMP_COMMON, "[RxRate Cnt] =============>\n"); /*======CCK=============================================================*/ - if (*(p_dm_odm->p_channel) <= 14) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* CCK = {%d, %d, %d, %d}\n", - p_dbg->num_qry_legacy_pkt[0], - p_dbg->num_qry_legacy_pkt[1], - p_dbg->num_qry_legacy_pkt[2], - p_dbg->num_qry_legacy_pkt[3] - )); + if (*dm->channel <= 14) { + PHYDM_DBG(dm, ODM_COMP_COMMON, "* CCK = {%d, %d, %d, %d}\n", + dbg->num_qry_legacy_pkt[0], + dbg->num_qry_legacy_pkt[1], + dbg->num_qry_legacy_pkt[2], + dbg->num_qry_legacy_pkt[3] + ); } /*======OFDM============================================================*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}\n", - p_dbg->num_qry_legacy_pkt[4], p_dbg->num_qry_legacy_pkt[5], - p_dbg->num_qry_legacy_pkt[6], p_dbg->num_qry_legacy_pkt[7], - p_dbg->num_qry_legacy_pkt[8], p_dbg->num_qry_legacy_pkt[9], - p_dbg->num_qry_legacy_pkt[10], p_dbg->num_qry_legacy_pkt[11])); + PHYDM_DBG(dm, ODM_COMP_COMMON, "* OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5], + dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7], + dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9], + dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]); - for (j = 0; j < 11; j++) { - p_dbg->num_qry_legacy_pkt[j] = 0; - } - /*======HT==============================================================*/ - if (p_dbg->ht_pkt_not_zero) { + if (dbg->ht_pkt_not_zero) { for (i = 0; i < rate_num; i++) { rate_ss_shift = (i << 3); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + PHYDM_DBG(dm, ODM_COMP_COMMON, "* HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", (rate_ss_shift), (rate_ss_shift+7), - p_dbg->num_qry_ht_pkt[rate_ss_shift + 0], p_dbg->num_qry_ht_pkt[rate_ss_shift + 1], - p_dbg->num_qry_ht_pkt[rate_ss_shift + 2], p_dbg->num_qry_ht_pkt[rate_ss_shift + 3], - p_dbg->num_qry_ht_pkt[rate_ss_shift + 4], p_dbg->num_qry_ht_pkt[rate_ss_shift + 5], - p_dbg->num_qry_ht_pkt[rate_ss_shift + 6], p_dbg->num_qry_ht_pkt[rate_ss_shift + 7])); + dbg->num_qry_ht_pkt[rate_ss_shift + 0], dbg->num_qry_ht_pkt[rate_ss_shift + 1], + dbg->num_qry_ht_pkt[rate_ss_shift + 2], dbg->num_qry_ht_pkt[rate_ss_shift + 3], + dbg->num_qry_ht_pkt[rate_ss_shift + 4], dbg->num_qry_ht_pkt[rate_ss_shift + 5], + dbg->num_qry_ht_pkt[rate_ss_shift + 6], dbg->num_qry_ht_pkt[rate_ss_shift + 7]); + } - for (j = 0; j < 8; j++) { - p_dbg->num_qry_ht_pkt[rate_ss_shift + j] = 0; + if (dbg->low_bw_20_occur) { + for (i = 0; i < rate_num; i++) { + + rate_ss_shift = (i << 3); + + PHYDM_DBG(dm, ODM_COMP_COMMON, "* [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (rate_ss_shift), (rate_ss_shift+7), + dbg->num_qry_pkt_sc_20m[rate_ss_shift + 0], dbg->num_qry_pkt_sc_20m[rate_ss_shift + 1], + dbg->num_qry_pkt_sc_20m[rate_ss_shift + 2], dbg->num_qry_pkt_sc_20m[rate_ss_shift + 3], + dbg->num_qry_pkt_sc_20m[rate_ss_shift + 4], dbg->num_qry_pkt_sc_20m[rate_ss_shift + 5], + dbg->num_qry_pkt_sc_20m[rate_ss_shift + 6], dbg->num_qry_pkt_sc_20m[rate_ss_shift + 7]); } - p_dbg->ht_pkt_not_zero = false; - } + } } + + #if ODM_IC_11AC_SERIES_SUPPORT /*======VHT=============================================================*/ - if (p_dbg->vht_pkt_not_zero){ - + if (dbg->vht_pkt_not_zero) { for (i = 0; i < rate_num; i++) { - rate_ss_shift = 10 * i; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + + PHYDM_DBG(dm, ODM_COMP_COMMON, "* VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", (i + 1), - p_dbg->num_qry_vht_pkt[rate_ss_shift + 0], p_dbg->num_qry_vht_pkt[rate_ss_shift + 1], - p_dbg->num_qry_vht_pkt[rate_ss_shift + 2], p_dbg->num_qry_vht_pkt[rate_ss_shift + 3], - p_dbg->num_qry_vht_pkt[rate_ss_shift + 4], p_dbg->num_qry_vht_pkt[rate_ss_shift + 5], - p_dbg->num_qry_vht_pkt[rate_ss_shift + 6], p_dbg->num_qry_vht_pkt[rate_ss_shift + 7], - p_dbg->num_qry_vht_pkt[rate_ss_shift + 8], p_dbg->num_qry_vht_pkt[rate_ss_shift + 9])); - - for (j = 0; j < 10; j++) { - p_dbg->num_qry_vht_pkt[rate_ss_shift + j] = 0; + dbg->num_qry_vht_pkt[rate_ss_shift + 0], dbg->num_qry_vht_pkt[rate_ss_shift + 1], + dbg->num_qry_vht_pkt[rate_ss_shift + 2], dbg->num_qry_vht_pkt[rate_ss_shift + 3], + dbg->num_qry_vht_pkt[rate_ss_shift + 4], dbg->num_qry_vht_pkt[rate_ss_shift + 5], + dbg->num_qry_vht_pkt[rate_ss_shift + 6], dbg->num_qry_vht_pkt[rate_ss_shift + 7], + dbg->num_qry_vht_pkt[rate_ss_shift + 8], dbg->num_qry_vht_pkt[rate_ss_shift + 9]); + } + + if (dbg->low_bw_20_occur) { + for (i = 0; i < rate_num; i++) { + rate_ss_shift = 10 * i; + + PHYDM_DBG(dm, ODM_COMP_COMMON, "*[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + dbg->num_qry_pkt_sc_20m[rate_ss_shift + 0], dbg->num_qry_pkt_sc_20m[rate_ss_shift + 1], + dbg->num_qry_pkt_sc_20m[rate_ss_shift + 2], dbg->num_qry_pkt_sc_20m[rate_ss_shift + 3], + dbg->num_qry_pkt_sc_20m[rate_ss_shift + 4], dbg->num_qry_pkt_sc_20m[rate_ss_shift + 5], + dbg->num_qry_pkt_sc_20m[rate_ss_shift + 6], dbg->num_qry_pkt_sc_20m[rate_ss_shift + 7], + dbg->num_qry_pkt_sc_20m[rate_ss_shift + 8], dbg->num_qry_pkt_sc_20m[rate_ss_shift + 9]); + } + } + + if (dbg->low_bw_40_occur) { + for (i = 0; i < rate_num; i++) { + rate_ss_shift = 10 * i; + + PHYDM_DBG(dm, ODM_COMP_COMMON, "*[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + dbg->num_qry_pkt_sc_40m[rate_ss_shift + 0], dbg->num_qry_pkt_sc_40m[rate_ss_shift + 1], + dbg->num_qry_pkt_sc_40m[rate_ss_shift + 2], dbg->num_qry_pkt_sc_40m[rate_ss_shift + 3], + dbg->num_qry_pkt_sc_40m[rate_ss_shift + 4], dbg->num_qry_pkt_sc_40m[rate_ss_shift + 5], + dbg->num_qry_pkt_sc_40m[rate_ss_shift + 6], dbg->num_qry_pkt_sc_40m[rate_ss_shift + 7], + dbg->num_qry_pkt_sc_40m[rate_ss_shift + 8], dbg->num_qry_pkt_sc_40m[rate_ss_shift + 9]); } - p_dbg->vht_pkt_not_zero = false; } } #endif @@ -1126,172 +1099,256 @@ phydm_rx_rate_distribution } void -phydm_show_avg_rssi +phydm_get_avg_phystatus_val ( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_phy_dbg_info_ *p_dbg = &(p_dm_odm->phy_dbg_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phystatus_statistic *dbg_statistic = &dm->phy_dbg_info.phystatus_statistic_info; + struct phydm_phystatus_avg *dbg_avg = &dm->phy_dbg_info.phystatus_statistic_avg; + + PHYDM_DBG(dm, ODM_COMP_COMMON, "[Avg PHY Statistic] ==============>\n"); + + phydm_reset_phystatus_avg(dm); + + /*CCK*/ + dbg_avg->rssi_cck_avg = (u8)((dbg_statistic->rssi_cck_cnt != 0) ? (dbg_statistic->rssi_cck_sum/dbg_statistic->rssi_cck_cnt) : 0); + PHYDM_DBG(dm, ODM_COMP_COMMON, "* cck Cnt= ((%d)) RSSI:{%d}\n", dbg_statistic->rssi_cck_cnt, dbg_avg->rssi_cck_avg); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[Avg RSSI] ==============> \n")); + /*OFDM*/ + if (dbg_statistic->rssi_ofdm_cnt != 0) { + dbg_avg->rssi_ofdm_avg = (u8)(dbg_statistic->rssi_ofdm_sum/dbg_statistic->rssi_ofdm_cnt); + dbg_avg->evm_ofdm_avg = (u8)(dbg_statistic->evm_ofdm_sum/dbg_statistic->rssi_ofdm_cnt); + dbg_avg->snr_ofdm_avg = (u8)(dbg_statistic->snr_ofdm_sum/dbg_statistic->rssi_ofdm_cnt); + } - p_dbg->rssi_cck_avg = (u8)((p_dbg->rssi_cck_cnt != 0) ? (p_dbg->rssi_cck_sum/p_dbg->rssi_cck_cnt) : 0); - p_dbg->rssi_ofdm_avg = (u8)((p_dbg->rssi_ofdm_cnt != 0) ? (p_dbg->rssi_ofdm_sum/p_dbg->rssi_ofdm_cnt) : 0); - p_dbg->rssi_1ss_avg = (u8)((p_dbg->rssi_1ss_cnt != 0) ? (p_dbg->rssi_1ss_sum/p_dbg->rssi_1ss_cnt) : 0); + PHYDM_DBG(dm, ODM_COMP_COMMON, "* ofdm Cnt= ((%d)) RSSI:{%d} EVM:{%d} SNR:{%d}\n", + dbg_statistic->rssi_ofdm_cnt, dbg_avg->rssi_ofdm_avg, dbg_avg->evm_ofdm_avg, dbg_avg->snr_ofdm_avg); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* cck Cnt= ((%d)) avg_RSSI:{%d}\n", p_dbg->rssi_cck_cnt, p_dbg->rssi_cck_avg)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* ofdm Cnt= ((%d)) avg_RSSI:{%d}\n", p_dbg->rssi_ofdm_cnt, p_dbg->rssi_ofdm_avg)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* 1-ss Cnt= ((%d)) avg_RSSI:{%d}\n", p_dbg->rssi_1ss_cnt, p_dbg->rssi_1ss_avg)); + if (dbg_statistic->rssi_1ss_cnt != 0) { + dbg_avg->rssi_1ss_avg = (u8)(dbg_statistic->rssi_1ss_sum/dbg_statistic->rssi_1ss_cnt); + dbg_avg->evm_1ss_avg = (u8)(dbg_statistic->evm_1ss_sum/dbg_statistic->rssi_1ss_cnt); + dbg_avg->snr_1ss_avg = (u8)(dbg_statistic->snr_1ss_sum/dbg_statistic->rssi_1ss_cnt); + } - if (p_dm_odm->support_ic_type & (ODM_IC_2SS |ODM_IC_3SS |ODM_IC_4SS)) { + PHYDM_DBG(dm, ODM_COMP_COMMON, "* 1-ss Cnt= ((%d)) RSSI:{%d} EVM:{%d} SNR:{%d}\n", + dbg_statistic->rssi_1ss_cnt, dbg_avg->rssi_1ss_avg, dbg_avg->evm_1ss_avg, dbg_avg->snr_1ss_avg); - p_dbg->rssi_2ss_avg[0] = (u8)((p_dbg->rssi_2ss_cnt != 0) ? (p_dbg->rssi_2ss_sum[0] /p_dbg->rssi_2ss_cnt) : 0); - p_dbg->rssi_2ss_avg[1] = (u8)((p_dbg->rssi_2ss_cnt != 0) ? (p_dbg->rssi_2ss_sum[1] /p_dbg->rssi_2ss_cnt) : 0); + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) { + if (dbg_statistic->rssi_2ss_cnt != 0) { + dbg_avg->rssi_2ss_avg[0] = (u8)(dbg_statistic->rssi_2ss_sum[0] /dbg_statistic->rssi_2ss_cnt); + dbg_avg->rssi_2ss_avg[1] = (u8)(dbg_statistic->rssi_2ss_sum[1] /dbg_statistic->rssi_2ss_cnt); + + dbg_avg->evm_2ss_avg[0] = (u8)(dbg_statistic->evm_2ss_sum[0] /dbg_statistic->rssi_2ss_cnt); + dbg_avg->evm_2ss_avg[1] = (u8)(dbg_statistic->evm_2ss_sum[1] /dbg_statistic->rssi_2ss_cnt); + + dbg_avg->snr_2ss_avg[0] = (u8)(dbg_statistic->snr_2ss_sum[0] /dbg_statistic->rssi_2ss_cnt); + dbg_avg->snr_2ss_avg[1] = (u8)(dbg_statistic->snr_2ss_sum[1] /dbg_statistic->rssi_2ss_cnt); + } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* 2-ss Cnt= ((%d)) avg_RSSI:{%d, %d}\n", - p_dbg->rssi_2ss_cnt, p_dbg->rssi_2ss_avg[0], p_dbg->rssi_2ss_avg[1])); + PHYDM_DBG(dm, ODM_COMP_COMMON, "* 2-ss Cnt= ((%d)) RSSI:{%d, %d}, EVM:{%d, %d}, SNR:{%d, %d}\n", + dbg_statistic->rssi_2ss_cnt, + dbg_avg->rssi_2ss_avg[0], dbg_avg->rssi_2ss_avg[1], + dbg_avg->evm_2ss_avg[0], dbg_avg->evm_2ss_avg[1], + dbg_avg->snr_2ss_avg[0], dbg_avg->snr_2ss_avg[1]); } - if (p_dm_odm->support_ic_type & (ODM_IC_3SS |ODM_IC_4SS)) { + #endif - p_dbg->rssi_3ss_avg[0] = (u8)((p_dbg->rssi_3ss_cnt != 0) ? (p_dbg->rssi_3ss_sum[0] /p_dbg->rssi_3ss_cnt) : 0); - p_dbg->rssi_3ss_avg[1] = (u8)((p_dbg->rssi_3ss_cnt != 0) ? (p_dbg->rssi_3ss_sum[1] /p_dbg->rssi_3ss_cnt) : 0); - p_dbg->rssi_3ss_avg[2] = (u8)((p_dbg->rssi_3ss_cnt != 0) ? (p_dbg->rssi_3ss_sum[2] /p_dbg->rssi_3ss_cnt) : 0); + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) { + if (dbg_statistic->rssi_3ss_cnt != 0) { + dbg_avg->rssi_3ss_avg[0] = (u8)(dbg_statistic->rssi_3ss_sum[0] /dbg_statistic->rssi_3ss_cnt); + dbg_avg->rssi_3ss_avg[1] = (u8)(dbg_statistic->rssi_3ss_sum[1] /dbg_statistic->rssi_3ss_cnt); + dbg_avg->rssi_3ss_avg[2] = (u8)(dbg_statistic->rssi_3ss_sum[2] /dbg_statistic->rssi_3ss_cnt); + + dbg_avg->evm_3ss_avg[0] = (u8)(dbg_statistic->evm_3ss_sum[0] /dbg_statistic->rssi_3ss_cnt); + dbg_avg->evm_3ss_avg[1] = (u8)(dbg_statistic->evm_3ss_sum[1] /dbg_statistic->rssi_3ss_cnt); + dbg_avg->evm_3ss_avg[2] = (u8)(dbg_statistic->evm_3ss_sum[2] /dbg_statistic->rssi_3ss_cnt); + + dbg_avg->snr_3ss_avg[0] = (u8)(dbg_statistic->snr_3ss_sum[0] /dbg_statistic->rssi_3ss_cnt); + dbg_avg->snr_3ss_avg[1] = (u8)(dbg_statistic->snr_3ss_sum[1] /dbg_statistic->rssi_3ss_cnt); + dbg_avg->snr_3ss_avg[2] = (u8)(dbg_statistic->snr_3ss_sum[2] /dbg_statistic->rssi_3ss_cnt); + } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* 3-ss Cnt= ((%d)) avg_RSSI:{%d, %d, %d}\n", - p_dbg->rssi_3ss_cnt, p_dbg->rssi_3ss_avg[0], p_dbg->rssi_3ss_avg[1], p_dbg->rssi_3ss_avg[2])); + PHYDM_DBG(dm, ODM_COMP_COMMON, "* 3-ss Cnt= ((%d)) RSSI:{%d, %d, %d} EVM:{%d, %d, %d} SNR:{%d, %d, %d}\n", + dbg_statistic->rssi_3ss_cnt, + dbg_avg->rssi_3ss_avg[0], dbg_avg->rssi_3ss_avg[1], dbg_avg->rssi_3ss_avg[2], + dbg_avg->evm_3ss_avg[0], dbg_avg->evm_3ss_avg[1], dbg_avg->evm_3ss_avg[2], + dbg_avg->snr_3ss_avg[0], dbg_avg->snr_3ss_avg[1], dbg_avg->snr_3ss_avg[2]); } - if (p_dm_odm->support_ic_type & ODM_IC_4SS) { + #endif - p_dbg->rssi_4ss_avg[0] = (u8)((p_dbg->rssi_4ss_cnt != 0) ? (p_dbg->rssi_4ss_sum[0] /p_dbg->rssi_4ss_cnt) : 0); - p_dbg->rssi_4ss_avg[1] = (u8)((p_dbg->rssi_4ss_cnt != 0) ? (p_dbg->rssi_4ss_sum[1] /p_dbg->rssi_4ss_cnt) : 0); - p_dbg->rssi_4ss_avg[2] = (u8)((p_dbg->rssi_4ss_cnt != 0) ? (p_dbg->rssi_4ss_sum[2] /p_dbg->rssi_4ss_cnt) : 0); - p_dbg->rssi_4ss_avg[3] = (u8)((p_dbg->rssi_4ss_cnt != 0) ? (p_dbg->rssi_4ss_sum[3] /p_dbg->rssi_4ss_cnt) : 0); + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + if (dbg_statistic->rssi_4ss_cnt != 0) { + dbg_avg->rssi_4ss_avg[0] = (u8)(dbg_statistic->rssi_4ss_sum[0] /dbg_statistic->rssi_4ss_cnt); + dbg_avg->rssi_4ss_avg[1] = (u8)(dbg_statistic->rssi_4ss_sum[1] /dbg_statistic->rssi_4ss_cnt); + dbg_avg->rssi_4ss_avg[2] = (u8)(dbg_statistic->rssi_4ss_sum[2] /dbg_statistic->rssi_4ss_cnt); + dbg_avg->rssi_4ss_avg[3] = (u8)(dbg_statistic->rssi_4ss_sum[3] /dbg_statistic->rssi_4ss_cnt); + + dbg_avg->evm_4ss_avg[0] = (u8)(dbg_statistic->evm_4ss_sum[0] /dbg_statistic->rssi_4ss_cnt); + dbg_avg->evm_4ss_avg[1] = (u8)(dbg_statistic->evm_4ss_sum[1] /dbg_statistic->rssi_4ss_cnt); + dbg_avg->evm_4ss_avg[2] = (u8)(dbg_statistic->evm_4ss_sum[2] /dbg_statistic->rssi_4ss_cnt); + dbg_avg->evm_4ss_avg[3] = (u8)(dbg_statistic->evm_4ss_sum[3] /dbg_statistic->rssi_4ss_cnt); + + dbg_avg->snr_4ss_avg[0] = (u8)(dbg_statistic->snr_4ss_sum[0] /dbg_statistic->rssi_4ss_cnt); + dbg_avg->snr_4ss_avg[1] = (u8)(dbg_statistic->snr_4ss_sum[1] /dbg_statistic->rssi_4ss_cnt); + dbg_avg->snr_4ss_avg[2] = (u8)(dbg_statistic->snr_4ss_sum[2] /dbg_statistic->rssi_4ss_cnt); + dbg_avg->snr_4ss_avg[3] = (u8)(dbg_statistic->snr_4ss_sum[3] /dbg_statistic->rssi_4ss_cnt); + } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("* 4-ss Cnt= ((%d)) avg_RSSI:{%d, %d, %d, %d}\n", - p_dbg->rssi_4ss_cnt, p_dbg->rssi_4ss_avg[0], p_dbg->rssi_4ss_avg[1], p_dbg->rssi_4ss_avg[2], p_dbg->rssi_4ss_avg[3])); + PHYDM_DBG(dm, ODM_COMP_COMMON, "* 4-ss Cnt= ((%d)) RSSI:{%d, %d, %d, %d} EVM:{%d, %d, %d, %d} SNR:{%d, %d, %d, %d}\n", + dbg_statistic->rssi_4ss_cnt, + dbg_avg->rssi_4ss_avg[0], dbg_avg->rssi_4ss_avg[1], dbg_avg->rssi_4ss_avg[2], dbg_avg->rssi_4ss_avg[3], + dbg_avg->evm_4ss_avg[0], dbg_avg->evm_4ss_avg[1], dbg_avg->evm_4ss_avg[2], dbg_avg->evm_4ss_avg[3], + dbg_avg->snr_4ss_avg[0], dbg_avg->snr_4ss_avg[1], dbg_avg->snr_4ss_avg[2], dbg_avg->snr_4ss_avg[3]); } + #endif + + - phydm_reset_avg_rssi_for_ss(p_dm_odm); } +void +phydm_get_phy_statistic( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + phydm_rx_rate_distribution(dm); + phydm_reset_rx_rate_distribution(dm); + + phydm_get_avg_phystatus_val(dm); + phydm_reset_phystatus_statistic(dm); +}; + void phydm_basic_dbg_message ( - void *p_dm_void + void *dm_void ) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT); + struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK); + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct ra_table *ra_tab = &dm->dm_ra_table; u16 macid, phydm_macid, client_cnt = 0; - struct sta_info *p_entry; + struct cmn_sta_info *entry = NULL; s32 tmp_val = 0; u8 tmp_val_u1 = 0; - if (!(ODM_COMP_COMMON & p_dm_odm->debug_components)) + if (!(dm->debug_components & ODM_COMP_COMMON)) + return; + + if (dm->cmn_dbg_msg_cnt < dm->cmn_dbg_msg_period) { + dm->cmn_dbg_msg_cnt += PHYDM_WATCH_DOG_PERIOD; return; + } else { + dm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD; + } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[PHYDM Common MSG] System up time: ((%d sec))----->\n", p_dm_odm->phydm_sys_up_time)); + PHYDM_DBG(dm, ODM_COMP_COMMON, "[PHYDM Common MSG] System up time: ((%d sec))----->\n", dm->phydm_sys_up_time); - if (p_dm_odm->is_linked) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ID=((%d)), BW=((%d)), CH=((%d))\n", p_dm_odm->curr_station_id, 20<<(*(p_dm_odm->p_band_width)), *(p_dm_odm->p_channel))); + if (dm->is_linked) { + PHYDM_DBG(dm, ODM_COMP_COMMON, + "ID=((%d)), BW=((%d)), fc=((CH-%d))\n", dm->curr_station_id, 20<<*dm->band_width, *dm->channel); + if ((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) { + PHYDM_DBG(dm, ODM_COMP_COMMON, "Primary CCA at ((%s SB))\n", + ((*dm->sec_ch_offset == SECOND_CH_AT_LSB)?"U":"L")); + } - if ((p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) || p_dm_odm->rx_rate > ODM_RATE11M) { + if ((dm->support_ic_type & PHYSTS_2ND_TYPE_IC) || dm->rx_rate > ODM_RATE11M) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}\n", - p_dm_odm->ofdm_agc_idx[0], p_dm_odm->ofdm_agc_idx[1], p_dm_odm->ofdm_agc_idx[2], p_dm_odm->ofdm_agc_idx[3])); + PHYDM_DBG(dm, ODM_COMP_COMMON, "[AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}\n", + dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1], dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]); } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCK AGC Idx] {LNA, VGA}={0x%x, 0x%x}\n", - p_dm_odm->cck_lna_idx, p_dm_odm->cck_vga_idx)); + PHYDM_DBG(dm, ODM_COMP_COMMON, "[CCK AGC Idx] {LNA, VGA}={0x%x, 0x%x}\n", + dm->cck_lna_idx, dm->cck_vga_idx); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI:{%d, %d, %d, %d}, RxRate:", - (p_dm_odm->RSSI_A == 0xff) ? 0 : p_dm_odm->RSSI_A, - (p_dm_odm->RSSI_B == 0xff) ? 0 : p_dm_odm->RSSI_B, - (p_dm_odm->RSSI_C == 0xff) ? 0 : p_dm_odm->RSSI_C, - (p_dm_odm->RSSI_D == 0xff) ? 0 : p_dm_odm->RSSI_D)); + PHYDM_DBG(dm, ODM_COMP_COMMON, "RSSI:{%d, %d, %d, %d}, RxRate:", + (dm->rssi_a == 0xff) ? 0 : dm->rssi_a, + (dm->rssi_b == 0xff) ? 0 : dm->rssi_b, + (dm->rssi_c == 0xff) ? 0 : dm->rssi_c, + (dm->rssi_d == 0xff) ? 0 : dm->rssi_d); - phydm_print_rate(p_dm_odm, p_dm_odm->rx_rate, ODM_COMP_COMMON); + phydm_print_rate(dm, dm->rx_rate, ODM_COMP_COMMON); - phydm_rx_rate_distribution(p_dm_odm); - phydm_show_avg_rssi(p_dm_odm); + phydm_get_phy_statistic(dm); /*Print TX rate*/ for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { - - p_entry = p_dm_odm->p_odm_sta_info[macid]; - if (!IS_STA_VALID(p_entry)) { + entry = dm->phydm_sta_info[macid]; + if (!is_sta_active(entry)) { continue; } - phydm_macid = (p_dm_odm->platform2phydm_macid_table[macid]); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TxRate[%d]:", macid)); - phydm_print_rate(p_dm_odm, p_ra_table->link_tx_rate[macid], ODM_COMP_COMMON); + phydm_macid = (dm->phydm_macid_table[macid]); + PHYDM_DBG(dm, ODM_COMP_COMMON, "TxRate[%d]:", macid); + phydm_print_rate(dm, entry->ra_info.curr_tx_rate, ODM_COMP_COMMON); client_cnt++; - if (client_cnt >= p_dm_odm->number_linked_client) + if (client_cnt >= dm->number_linked_client) break; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))\n", - p_dm_odm->tx_tp, p_dm_odm->rx_tp, p_dm_odm->total_tp, p_dm_odm->traffic_load)); + PHYDM_DBG(dm, ODM_COMP_COMMON, "TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))\n", + dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load); - tmp_val_u1 = (p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) ? (p_cfo_track->crystal_cap - p_cfo_track->def_x_cap) : (p_cfo_track->def_x_cap - p_cfo_track->crystal_cap); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CFO_avg = ((%d kHz)) , CFO_tracking = ((%s%d))\n", - p_cfo_track->CFO_ave_pre, ((p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) ? "+" : "-"), tmp_val_u1)); + tmp_val_u1 = (cfo_track->crystal_cap > cfo_track->def_x_cap) ? (cfo_track->crystal_cap - cfo_track->def_x_cap) : (cfo_track->def_x_cap - cfo_track->crystal_cap); + PHYDM_DBG(dm, ODM_COMP_COMMON, "CFO_avg = ((%d kHz)) , CFO_tracking = ((%s%d))\n", + cfo_track->CFO_ave_pre, ((cfo_track->crystal_cap > cfo_track->def_x_cap) ? "+" : "-"), tmp_val_u1); /* Condition number */ #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - tmp_val = phydm_get_condition_number_8822B(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Condi_Num=((%d))\n", tmp_val)); + if (dm->support_ic_type == ODM_RTL8822B) { + tmp_val = phydm_get_condition_number_8822B(dm); + PHYDM_DBG(dm, ODM_COMP_COMMON, "Condi_Num=((%d))\n", tmp_val); } #endif #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) /*STBC or LDPC pkt*/ - if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Coding: LDPC=((%s)), STBC=((%s))\n", (p_dm_odm->phy_dbg_info.is_ldpc_pkt) ? "Y" : "N", (p_dm_odm->phy_dbg_info.is_stbc_pkt) ? "Y" : "N")); + if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) + PHYDM_DBG(dm, ODM_COMP_COMMON, "Coding: LDPC=((%s)), STBC=((%s))\n", (dm->phy_dbg_info.is_ldpc_pkt) ? "Y" : "N", (dm->phy_dbg_info.is_stbc_pkt) ? "Y" : "N"); #endif } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("No Link !!!\n")); + PHYDM_DBG(dm, ODM_COMP_COMMON, "No Link !!!\n"); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all)); + PHYDM_DBG(dm, ODM_COMP_COMMON, "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all)); + PHYDM_DBG(dm, ODM_COMP_COMMON, "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all); #if (ODM_IC_11N_SERIES_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n", - false_alm_cnt->cnt_parity_fail, false_alm_cnt->cnt_rate_illegal, false_alm_cnt->cnt_crc8_fail, false_alm_cnt->cnt_mcs_fail, false_alm_cnt->cnt_fast_fsync, false_alm_cnt->cnt_sb_search_fail)); + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + PHYDM_DBG(dm, ODM_COMP_COMMON, "[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n", + false_alm_cnt->cnt_parity_fail, false_alm_cnt->cnt_rate_illegal, false_alm_cnt->cnt_crc8_fail, false_alm_cnt->cnt_mcs_fail, false_alm_cnt->cnt_fast_fsync, false_alm_cnt->cnt_sb_search_fail); } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\n\n", - p_dm_odm->is_linked, p_dm_odm->number_linked_client, p_dm_odm->rssi_min, p_dm_dig_table->cur_ig_value, p_dm_odm->noisy_decision)); - -#endif + PHYDM_DBG(dm, ODM_COMP_COMMON, "is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\n\n", + dm->is_linked, dm->number_linked_client, dm->rssi_min, dig_t->cur_ig_value, dm->noisy_decision); } void phydm_basic_profile( - void *p_dm_void, + void *dm_void, u32 *_used, char *output, u32 *_out_len ) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; char *cut = NULL; char *ic_type = NULL; u32 used = *_used; @@ -1300,9 +1357,10 @@ void phydm_basic_profile( char *commit_by = NULL; u32 release_ver = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% Basic Profile %")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-35s\n", "% Basic Profile %"); - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + if (dm->support_ic_type == ODM_RTL8188E) { #if (RTL8188E_SUPPORT == 1) ic_type = "RTL8188E"; date = RELEASE_DATE_8188E; @@ -1311,7 +1369,7 @@ void phydm_basic_profile( #endif } #if (RTL8812A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8812) { + else if (dm->support_ic_type == ODM_RTL8812) { ic_type = "RTL8812A"; date = RELEASE_DATE_8812A; commit_by = COMMIT_BY_8812A; @@ -1319,7 +1377,7 @@ void phydm_basic_profile( } #endif #if (RTL8821A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8821) { + else if (dm->support_ic_type == ODM_RTL8821) { ic_type = "RTL8821A"; date = RELEASE_DATE_8821A; commit_by = COMMIT_BY_8821A; @@ -1327,7 +1385,7 @@ void phydm_basic_profile( } #endif #if (RTL8192E_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + else if (dm->support_ic_type == ODM_RTL8192E) { ic_type = "RTL8192E"; date = RELEASE_DATE_8192E; commit_by = COMMIT_BY_8192E; @@ -1335,7 +1393,7 @@ void phydm_basic_profile( } #endif #if (RTL8723B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + else if (dm->support_ic_type == ODM_RTL8723B) { ic_type = "RTL8723B"; date = RELEASE_DATE_8723B; commit_by = COMMIT_BY_8723B; @@ -1343,7 +1401,7 @@ void phydm_basic_profile( } #endif #if (RTL8814A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8814A) { + else if (dm->support_ic_type == ODM_RTL8814A) { ic_type = "RTL8814A"; date = RELEASE_DATE_8814A; commit_by = COMMIT_BY_8814A; @@ -1351,13 +1409,13 @@ void phydm_basic_profile( } #endif #if (RTL8881A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8881A) { + else if (dm->support_ic_type == ODM_RTL8881A) { ic_type = "RTL8881A"; /**/ } #endif #if (RTL8822B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + else if (dm->support_ic_type == ODM_RTL8822B) { ic_type = "RTL8822B"; date = RELEASE_DATE_8822B; commit_by = COMMIT_BY_8822B; @@ -1365,7 +1423,7 @@ void phydm_basic_profile( } #endif #if (RTL8197F_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8197F) { + else if (dm->support_ic_type == ODM_RTL8197F) { ic_type = "RTL8197F"; date = RELEASE_DATE_8197F; commit_by = COMMIT_BY_8197F; @@ -1374,8 +1432,7 @@ void phydm_basic_profile( #endif #if (RTL8703B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8703B) { - + else if (dm->support_ic_type == ODM_RTL8703B) { ic_type = "RTL8703B"; date = RELEASE_DATE_8703B; commit_by = COMMIT_BY_8703B; @@ -1384,13 +1441,13 @@ void phydm_basic_profile( } #endif #if (RTL8195A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8195A) { + else if (dm->support_ic_type == ODM_RTL8195A) { ic_type = "RTL8195A"; /**/ } #endif #if (RTL8188F_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + else if (dm->support_ic_type == ODM_RTL8188F) { ic_type = "RTL8188F"; date = RELEASE_DATE_8188F; commit_by = COMMIT_BY_8188F; @@ -1398,7 +1455,7 @@ void phydm_basic_profile( } #endif #if (RTL8723D_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + else if (dm->support_ic_type == ODM_RTL8723D) { ic_type = "RTL8723D"; date = RELEASE_DATE_8723D; commit_by = COMMIT_BY_8723D; @@ -1409,7 +1466,7 @@ void phydm_basic_profile( /* JJ ADD 20161014 */ #if (RTL8710B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + else if (dm->support_ic_type == ODM_RTL8710B) { ic_type = "RTL8710B"; date = RELEASE_DATE_8710B; commit_by = COMMIT_BY_8710B; @@ -1419,108 +1476,152 @@ void phydm_basic_profile( #endif #if (RTL8821C_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + else if (dm->support_ic_type == ODM_RTL8821C) { ic_type = "RTL8821C"; date = RELEASE_DATE_8821C; commit_by = COMMIT_BY_8821C; release_ver = RELEASE_VERSION_8821C; } #endif - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s (MP Chip: %s)\n", "IC type", ic_type, p_dm_odm->is_mp_chip ? "Yes" : "No")); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s (MP Chip: %s)\n", "IC type", ic_type, + dm->is_mp_chip ? "Yes" : "No"); - if (p_dm_odm->cut_version == ODM_CUT_A) + if (dm->cut_version == ODM_CUT_A) cut = "A"; - else if (p_dm_odm->cut_version == ODM_CUT_B) + else if (dm->cut_version == ODM_CUT_B) cut = "B"; - else if (p_dm_odm->cut_version == ODM_CUT_C) + else if (dm->cut_version == ODM_CUT_C) cut = "C"; - else if (p_dm_odm->cut_version == ODM_CUT_D) + else if (dm->cut_version == ODM_CUT_D) cut = "D"; - else if (p_dm_odm->cut_version == ODM_CUT_E) + else if (dm->cut_version == ODM_CUT_E) cut = "E"; - else if (p_dm_odm->cut_version == ODM_CUT_F) + else if (dm->cut_version == ODM_CUT_F) cut = "F"; - else if (p_dm_odm->cut_version == ODM_CUT_I) + else if (dm->cut_version == ODM_CUT_I) cut = "I"; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "cut version", cut)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter version", odm_get_hw_img_version(p_dm_odm))); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Commit date", date)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY Parameter Commit by", commit_by)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Release version", release_ver)); + + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %d\n", "RFE type", dm->rfe_type); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "Cut Ver", cut); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %d\n", "PHY Para Ver", + odm_get_hw_img_version(dm)); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %d\n", "PHY Para Commit date", date); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "PHY Para Commit by", commit_by); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %d\n", "PHY Para Release Ver", release_ver); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) { - struct _ADAPTER *adapter = p_dm_odm->adapter; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", adapter->MgntInfo.FirmwareVersion, adapter->MgntInfo.FirmwareSubVersion)); + void *adapter = dm->adapter; + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %d (Subversion: %d)\n", "FW Ver", + ((PADAPTER)adapter)->MgntInfo.FirmwareVersion, + ((PADAPTER)adapter)->MgntInfo.FirmwareSubVersion); } #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) { - struct rtl8192cd_priv *priv = p_dm_odm->priv; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", priv->pshare->fw_version, priv->pshare->fw_sub_version)); + struct rtl8192cd_priv *priv = dm->priv; + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %d (Subversion: %d)\n", "FW Ver", + priv->pshare->fw_version, + priv->pshare->fw_sub_version); } #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) { - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; struct rtl_hal *rtlhal = rtl_hal(rtlpriv); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", rtlhal->fw_version, rtlhal->fw_subversion)); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %d (Subversion: %d)\n", "FW Ver", + rtlhal->fw_version, rtlhal->fw_subversion); } #else { - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", p_hal_data->firmware_version, p_hal_data->firmware_sub_version)); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %d (Subversion: %d)\n", "FW Ver", + hal_data->firmware_version, + hal_data->firmware_sub_version); } #endif /* 1 PHY DM version List */ - PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% PHYDM version %")); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Code base", PHYDM_CODE_BASE)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Release Date", PHYDM_RELEASE_DATE)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "adaptivity", ADAPTIVITY_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "DIG", DIG_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic BB PowerSaving", DYNAMIC_BBPWRSAV_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "CFO Tracking", CFO_TRACKING_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Diversity", ANTDIV_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic TxPower", DYNAMIC_TXPWR_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "RA Info", RAINFO_VERSION)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-35s\n", "% PHYDM version %"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "Code base", PHYDM_CODE_BASE); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "Release Date", PHYDM_RELEASE_DATE); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "Adaptivity", ADAPTIVITY_VERSION); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "DIG", DIG_VERSION); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "CFO Tracking", CFO_TRACKING_VERSION); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "AntDiv", ANTDIV_VERSION); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "Dynamic TxPower", + DYNAMIC_TXPWR_VERSION); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "RA Info", RAINFO_VERSION); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Detection", ANTDECT_VERSION)); -#endif - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Auto channel Selection", ACS_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "path Diversity", PATHDIV_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "LA mode", DYNAMIC_LA_MODE)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic RX path", DYNAMIC_RX_PATH_VERSION)); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "AntDetect", ANTDECT_VERSION); +#endif + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "PathDiv", PATHDIV_VERSION); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "LA mode", DYNAMIC_LA_MODE); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "Primary CCA", PRIMARYCCA_VERSION); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "DFS", DFS_VERSION); #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8822B", PHY_CONFIG_VERSION_8822B)); + if (dm->support_ic_type & ODM_RTL8822B) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "PHY config 8822B", + PHY_CONFIG_VERSION_8822B); #endif #if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8197F", PHY_CONFIG_VERSION_8197F)); + if (dm->support_ic_type & ODM_RTL8197F) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "PHY config 8197F", + PHY_CONFIG_VERSION_8197F); #endif + *_used = used; *_out_len = out_len; + + /* RF Function version List */ + halrf_basic_profile(dm_void, &used, output, &out_len); + #endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ } -#if CONFIG_PHYDM_DEBUG_FUNCTION +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION void phydm_fw_trace_en_h2c( - void *p_dm_void, + void *dm_void, boolean enable, u32 fw_debug_component, u32 monitor_mode, u32 macid ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 h2c_parameter[7] = {0}; u8 cmd_length; - if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { - + if (dm->support_ic_type & PHYDM_IC_3081_SERIES) { h2c_parameter[0] = enable; h2c_parameter[1] = (u8)(fw_debug_component & MASKBYTE0); h2c_parameter[2] = (u8)((fw_debug_component & MASKBYTE1) >> 8); @@ -1531,7 +1632,6 @@ phydm_fw_trace_en_h2c( cmd_length = 7; } else { - h2c_parameter[0] = enable; h2c_parameter[1] = (u8)monitor_mode; h2c_parameter[2] = (u8)macid; @@ -1539,411 +1639,416 @@ phydm_fw_trace_en_h2c( } - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("---->\n")); + PHYDM_DBG(dm, DBG_FW_TRACE, "---->\n"); if (monitor_mode == 0) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d ))\n", enable)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[H2C] FW_debug_en: (( %d ))\n", enable); else - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n", enable, monitor_mode, macid)); - odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter); + PHYDM_DBG(dm, DBG_FW_TRACE, "[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n", enable, monitor_mode, macid); + odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter); } - -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) -boolean -phydm_api_set_txagc( - struct PHY_DM_STRUCT *p_dm_odm, - u32 power_index, - enum odm_rf_radio_path_e path, - u8 hw_rate, - boolean is_single_rate +void +phydm_get_per_path_txagc( + void *dm_void, + u8 path, + u32 *_used, + char *output, + u32 *_out_len ) { - boolean ret = false; - #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - u8 i; - #endif - -#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { - if (is_single_rate) { -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) - ret = phydm_write_txagc_1byte_8822b(p_dm_odm, power_index, path, hw_rate); -#endif -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - ret = phydm_write_txagc_1byte_8821c(p_dm_odm, power_index, path, hw_rate); -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - set_current_tx_agc(p_dm_odm->priv, path, hw_rate, (u8)power_index); -#endif + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rate_idx; + u8 txagc; + u32 used = *_used; + u32 out_len = *_out_len; - } else { +#ifdef PHYDM_COMMON_API_SUPPORT + if (((dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) && (path <= RF_PATH_B)) || + ((dm->support_ic_type & (ODM_RTL8821C)) && (path <= RF_PATH_A))) { + for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) { + if (rate_idx == ODM_RATE1M) + PDM_SNPF(out_len, used, output + used, + out_len - used, " %-35s\n", + "CCK====>"); + else if (rate_idx == ODM_RATE6M) + PDM_SNPF(out_len, used, output + used, + out_len - used, "\n %-35s\n", + "OFDM====>"); + else if (rate_idx == ODM_RATEMCS0) + PDM_SNPF(out_len, used, output + used, + out_len - used, "\n %-35s\n", + "HT 1ss====>"); + else if (rate_idx == ODM_RATEMCS8) + PDM_SNPF(out_len, used, output + used, + out_len - used, "\n %-35s\n", + "HT 2ss====>"); + else if (rate_idx == ODM_RATEMCS16) + PDM_SNPF(out_len, used, output + used, + out_len - used, "\n %-35s\n", + "HT 3ss====>"); + else if (rate_idx == ODM_RATEMCS24) + PDM_SNPF(out_len, used, output + used, + out_len - used, "\n %-35s\n", + "HT 4ss====>"); + else if (rate_idx == ODM_RATEVHTSS1MCS0) + PDM_SNPF(out_len, used, output + used, + out_len - used, "\n %-35s\n", + "VHT 1ss====>"); + else if (rate_idx == ODM_RATEVHTSS2MCS0) + PDM_SNPF(out_len, used, output + used, + out_len - used, "\n %-35s\n", + "VHT 2ss====>"); + else if (rate_idx == ODM_RATEVHTSS3MCS0) + PDM_SNPF(out_len, used, output + used, + out_len - used, "\n %-35s\n", + "VHT 3ss====>"); + else if (rate_idx == ODM_RATEVHTSS4MCS0) + PDM_SNPF(out_len, used, output + used, + out_len - used, "\n %-35s\n", + "VHT 4ss====>"); -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) - ret = config_phydm_write_txagc_8822b(p_dm_odm, power_index, path, hw_rate); -#endif -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - ret = config_phydm_write_txagc_8821c(p_dm_odm, power_index, path, hw_rate); -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - for (i = 0; i < 4; i++) - set_current_tx_agc(p_dm_odm->priv, path, (hw_rate + i), (u8)power_index); -#endif + txagc = phydm_api_get_txagc(dm, (enum rf_path) path, rate_idx); + if (config_phydm_read_txagc_check(txagc)) + PDM_SNPF(out_len, used, output + used, + out_len - used, " 0x%02x ", + txagc); + else + PDM_SNPF(out_len, used, output + used, + out_len - used, " 0x%s ", + "xx"); } } #endif + *_used = used; + *_out_len = out_len; -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - ret = config_phydm_write_txagc_8197f(p_dm_odm, power_index, path, hw_rate); -#endif - - return ret; } -u8 -phydm_api_get_txagc( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e path, - u8 hw_rate + +void +phydm_get_txagc( + void *dm_void, + u32 *_used, + char *output, + u32 *_out_len ) { - u8 ret = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - ret = config_phydm_read_txagc_8822b(p_dm_odm, path, hw_rate); -#endif + /* path-A */ + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-35s\n", "path-A===================="); + phydm_get_per_path_txagc(dm, RF_PATH_A, &used, output, &out_len); -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - ret = config_phydm_read_txagc_8197f(p_dm_odm, path, hw_rate); -#endif + /* path-B */ + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n%-35s\n", "path-B===================="); + phydm_get_per_path_txagc(dm, RF_PATH_B, &used, output, &out_len); -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8821C) - ret = config_phydm_read_txagc_8821c(p_dm_odm, path, hw_rate); -#endif + /* path-C */ + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n%-35s\n", "path-C===================="); + phydm_get_per_path_txagc(dm, RF_PATH_C, &used, output, &out_len); - return ret; -} + /* path-D */ + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n%-35s\n", "path-D===================="); + phydm_get_per_path_txagc(dm, RF_PATH_D, &used, output, &out_len); + *_used = used; + *_out_len = out_len; -boolean -phydm_api_switch_bw_channel( - struct PHY_DM_STRUCT *p_dm_odm, - u8 central_ch, - u8 primary_ch_idx, - enum odm_bw_e bandwidth -) -{ - boolean ret = false; - -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - ret = config_phydm_switch_channel_bw_8822b(p_dm_odm, central_ch, primary_ch_idx, bandwidth); -#endif - -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - ret = config_phydm_switch_channel_bw_8197f(p_dm_odm, central_ch, primary_ch_idx, bandwidth); -#endif - -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8821C) - ret = config_phydm_switch_channel_bw_8821c(p_dm_odm, central_ch, primary_ch_idx, bandwidth); -#endif - - return ret; -} - -boolean -phydm_api_trx_mode( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_path_e tx_path, - enum odm_rf_path_e rx_path, - boolean is_tx2_path -) -{ - boolean ret = false; - -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - ret = config_phydm_trx_mode_8822b(p_dm_odm, tx_path, rx_path, is_tx2_path); -#endif - -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - ret = config_phydm_trx_mode_8197f(p_dm_odm, tx_path, rx_path, is_tx2_path); -#endif - - return ret; -} -#endif - -void -phydm_get_per_path_txagc( - void *p_dm_void, - u8 path, - u32 *_used, - char *output, - u32 *_out_len -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 rate_idx; - u8 txagc; - u32 used = *_used; - u32 out_len = *_out_len; - -#if ((RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - if (((p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) && (path <= ODM_RF_PATH_B)) || - ((p_dm_odm->support_ic_type & (ODM_RTL8821C)) && (path <= ODM_RF_PATH_A))) { - for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) { - if (rate_idx == ODM_RATE1M) - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s\n", "CCK====>")); - else if (rate_idx == ODM_RATE6M) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "OFDM====>")); - else if (rate_idx == ODM_RATEMCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 1ss====>")); - else if (rate_idx == ODM_RATEMCS8) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 2ss====>")); - else if (rate_idx == ODM_RATEMCS16) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 3ss====>")); - else if (rate_idx == ODM_RATEMCS24) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 4ss====>")); - else if (rate_idx == ODM_RATEVHTSS1MCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 1ss====>")); - else if (rate_idx == ODM_RATEVHTSS2MCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 2ss====>")); - else if (rate_idx == ODM_RATEVHTSS3MCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 3ss====>")); - else if (rate_idx == ODM_RATEVHTSS4MCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 4ss====>")); - - txagc = phydm_api_get_txagc(p_dm_odm, (enum odm_rf_radio_path_e) path, rate_idx); - if (config_phydm_read_txagc_check(txagc)) - PHYDM_SNPRINTF((output + used, out_len - used, " 0x%02x ", txagc)); - else - PHYDM_SNPRINTF((output + used, out_len - used, " 0x%s ", "xx")); - } - } -#endif -} - - -void -phydm_get_txagc( - void *p_dm_void, - u32 *_used, - char *output, - u32 *_out_len -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 used = *_used; - u32 out_len = *_out_len; - - /* path-A */ - PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "path-A====================")); - phydm_get_per_path_txagc(p_dm_odm, ODM_RF_PATH_A, _used, output, _out_len); - - /* path-B */ - PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "path-B====================")); - phydm_get_per_path_txagc(p_dm_odm, ODM_RF_PATH_B, _used, output, _out_len); - - /* path-C */ - PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "path-C====================")); - phydm_get_per_path_txagc(p_dm_odm, ODM_RF_PATH_C, _used, output, _out_len); - - /* path-D */ - PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "path-D====================")); - phydm_get_per_path_txagc(p_dm_odm, ODM_RF_PATH_D, _used, output, _out_len); - -} +} void phydm_set_txagc( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, - char *output, + char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 used = *_used; u32 out_len = *_out_len; + u8 i; + u32 power_index; + boolean status = true; /*dm_value[1] = path*/ /*dm_value[2] = hw_rate*/ /*dm_value[3] = power_index*/ -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)) { - if (dm_value[1] <= 1) { - if ((u8)dm_value[2] != 0xff) { - if (phydm_api_set_txagc(p_dm_odm, dm_value[3], (enum odm_rf_radio_path_e) dm_value[1], (u8)dm_value[2], true)) - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s%x\n", "Write path-", dm_value[1], "rate index-0x", dm_value[2], " = 0x", dm_value[3])); - else - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s\n", "Write path-", (dm_value[1] & 0x1), "rate index-0x", (dm_value[2] & 0x7f), " fail")); - } else { - u8 i; - u32 power_index; - boolean status = true; - - power_index = (dm_value[3] & 0x3f); +#ifdef PHYDM_COMMON_API_SUPPORT + if ((dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)) == 0) + return; + + if (dm_value[1] >= dm->num_rf_path) { + PDM_SNPF(out_len, used, output + used, out_len - used, + " %s%d %s%x%s\n", "Write path-", + (dm_value[1] & 0x1), "rate index-0x", + (dm_value[2] & 0x7f), " fail"); + } else if ((u8)dm_value[2] != 0xff) { + if (phydm_api_set_txagc(dm, dm_value[3], (enum rf_path) dm_value[1], (u8)dm_value[2], true)) + PDM_SNPF(out_len, used, output + used, + out_len - used, " %s%d %s%x%s%x\n", + "Write path-", dm_value[1], + "rate index-0x", dm_value[2], " = 0x", + dm_value[3]); + else + PDM_SNPF(out_len, used, output + used, + out_len - used, " %s%d %s%x%s\n", + "Write path-", (dm_value[1] & 0x1), + "rate index-0x", (dm_value[2] & 0x7f), + " fail"); + } else { + power_index = (dm_value[3] & 0x3f); - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { - power_index = (power_index << 24) | (power_index << 16) | (power_index << 8) | (power_index); + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + power_index = (power_index << 24) | (power_index << 16) | (power_index << 8) | (power_index); - for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4) - status = (status & phydm_api_set_txagc(p_dm_odm, power_index, (enum odm_rf_radio_path_e) dm_value[1], i, false)); - } else if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - for (i = 0; i <= ODM_RATEMCS15; i++) - status = (status & phydm_api_set_txagc(p_dm_odm, power_index, (enum odm_rf_radio_path_e) dm_value[1], i, false)); - } + for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4) + status = (status & phydm_api_set_txagc(dm, power_index, (enum rf_path) dm_value[1], i, false)); + } else if (dm->support_ic_type & ODM_RTL8197F) { + for (i = 0; i <= ODM_RATEMCS15; i++) + status = (status & phydm_api_set_txagc(dm, power_index, (enum rf_path) dm_value[1], i, false)); + } - if (status) - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x\n", "Write all TXAGC of path-", dm_value[1], " = 0x", dm_value[3])); - else - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s\n", "Write all TXAGC of path-", dm_value[1], " fail")); - } - } else - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s\n", "Write path-", (dm_value[1] & 0x1), "rate index-0x", (dm_value[2] & 0x7f), " fail")); + if (status) + PDM_SNPF(out_len, used, output + used, + out_len - used, " %s%d %s%x\n", + "Write all TXAGC of path-", + dm_value[1], " = 0x", dm_value[3]); + else + PDM_SNPF(out_len, used, output + used, + out_len - used, " %s%d %s\n", + "Write all TXAGC of path-", + dm_value[1], " fail"); } + #endif + *_used = used; + *_out_len = out_len; } void phydm_debug_trace( - void *p_dm_void, - u32 *const dm_value, + void *dm_void, + char input[][16], u32 *_used, char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 pre_debug_components, one = 1; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 pre_debug_components, one = 1; u32 used = *_used; u32 out_len = *_out_len; + u32 dm_value[10] = {0}; + + u8 i; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]); + } + } - pre_debug_components = p_dm_odm->debug_components; + pre_debug_components = dm->debug_components; - PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); + PDM_SNPF(out_len, used, output + used, out_len - used, "\n================================\n"); if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Debug Message] PhyDM Selection")); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((p_dm_odm->debug_components & ODM_COMP_DIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((p_dm_odm->debug_components & ODM_COMP_RA_MASK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((p_dm_odm->debug_components & ODM_COMP_DYNAMIC_TXPWR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((p_dm_odm->debug_components & ODM_COMP_FA_CNT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((p_dm_odm->debug_components & ODM_COMP_RSSI_MONITOR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))SNIFFER\n", ((p_dm_odm->debug_components & ODM_COMP_SNIFFER) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((p_dm_odm->debug_components & ODM_COMP_ANT_DIV) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "07. (( %s ))DFS\n", ((p_dm_odm->debug_components & ODM_COMP_DFS) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))NOISY_DETECT\n", ((p_dm_odm->debug_components & ODM_COMP_NOISY_DETECT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((p_dm_odm->debug_components & ODM_COMP_RATE_ADAPTIVE) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((p_dm_odm->debug_components & ODM_COMP_PATH_DIV) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "12. (( %s ))DYNAMIC_PRICCA\n", ((p_dm_odm->debug_components & ODM_COMP_DYNAMIC_PRICCA) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))MP\n", ((p_dm_odm->debug_components & ODM_COMP_MP) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))CFO_TRACKING\n", ((p_dm_odm->debug_components & ODM_COMP_CFO_TRACKING) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))ACS\n", ((p_dm_odm->debug_components & ODM_COMP_ACS) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))ADAPTIVITY\n", ((p_dm_odm->debug_components & PHYDM_COMP_ADAPTIVITY) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))RA_DBG\n", ((p_dm_odm->debug_components & PHYDM_COMP_RA_DBG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "19. (( %s ))TXBF\n", ((p_dm_odm->debug_components & PHYDM_COMP_TXBF) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "22. (( %s ))FW_DEBUG_TRACE\n", ((p_dm_odm->debug_components & ODM_FW_DEBUG_TRACE) ? ("V") : (".")))); - - PHYDM_SNPRINTF((output + used, out_len - used, "24. (( %s ))TX_PWR_TRACK\n", ((p_dm_odm->debug_components & ODM_COMP_TX_PWR_TRACK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "26. (( %s ))CALIBRATION\n", ((p_dm_odm->debug_components & ODM_COMP_CALIBRATION) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "28. (( %s ))PHY_CONFIG\n", ((p_dm_odm->debug_components & ODM_PHY_CONFIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "29. (( %s ))INIT\n", ((p_dm_odm->debug_components & ODM_COMP_INIT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "30. (( %s ))COMMON\n", ((p_dm_odm->debug_components & ODM_COMP_COMMON) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "31. (( %s ))API\n", ((p_dm_odm->debug_components & ODM_COMP_API) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PDM_SNPF(out_len, used, output + used, out_len - used, "[DBG MSG] Component Selection\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, "================================\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, "00. (( %s ))DIG\n", + ((dm->debug_components & DBG_DIG) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "01. (( %s ))RA_MASK\n", + ((dm->debug_components & DBG_RA_MASK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "02. (( %s ))DYN_TXPWR\n", + ((dm->debug_components & DBG_DYN_TXPWR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "03. (( %s ))FA_CNT\n", + ((dm->debug_components & DBG_FA_CNT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "04. (( %s ))RSSI_MNTR\n", + ((dm->debug_components & DBG_RSSI_MNTR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "05. (( %s ))CCKPD\n", + ((dm->debug_components & DBG_CCKPD) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "06. (( %s ))ANT_DIV\n", + ((dm->debug_components & DBG_ANT_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "07. (( %s ))SMT_ANT\n", + ((dm->debug_components & DBG_SMT_ANT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "08. (( %s ))PWR_TRAIN\n", + ((dm->debug_components & F08_PWR_TRAIN) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "09. (( %s ))RA\n", + ((dm->debug_components & DBG_RA) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "10. (( %s ))PATH_DIV\n", + ((dm->debug_components & DBG_PATH_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "11. (( %s ))DFS\n", + ((dm->debug_components & DBG_DFS) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "12. (( %s ))DYN_ARFR\n", + ((dm->debug_components & DBG_DYN_ARFR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "13. (( %s ))ADAPTIVITY\n", + ((dm->debug_components & DBG_ADPTVTY) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "14. (( %s ))CFO_TRK\n", + ((dm->debug_components & DBG_CFO_TRK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "15. (( %s ))ENV_MNTR\n", + ((dm->debug_components & DBG_ENV_MNTR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "16. (( %s ))PRI_CCA\n", + ((dm->debug_components & DBG_PRI_CCA) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "17. (( %s ))ADPTV_SOML\n", + ((dm->debug_components & DBG_ADPTV_SOML) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "18. (( %s ))LNA_SAT_CHK\n", + ((dm->debug_components & DBG_LNA_SAT_CHK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "19. (( %s ))DRP\n", + ((dm->debug_components & DBG_DYN_RX_PATH) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "20. (( %s ))PHY_STATUS\n", + ((dm->debug_components & DBG_PHY_STATUS) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "21. (( %s ))TMP\n", + ((dm->debug_components & DBG_TMP) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "22. (( %s ))FW_DBG_TRACE\n", + ((dm->debug_components & DBG_FW_TRACE) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "23. (( %s ))TXBF\n", + ((dm->debug_components & DBG_TXBF) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "24. (( %s ))COMMON_FLOW\n", + ((dm->debug_components & DBG_COMMON_FLOW) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "25. (( %s ))TX_PWR_TRK\n", + ((dm->debug_components & ODM_COMP_TX_PWR_TRACK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "26. (( %s ))CALIBRATION\n", + ((dm->debug_components & ODM_COMP_CALIBRATION) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "27. (( %s ))MP\n", + ((dm->debug_components & ODM_COMP_MP) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "28. (( %s ))PHY_CONFIG\n", + ((dm->debug_components & ODM_PHY_CONFIG) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "29. (( %s ))INIT\n", + ((dm->debug_components & ODM_COMP_INIT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "30. (( %s ))COMMON\n", + ((dm->debug_components & ODM_COMP_COMMON) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "31. (( %s ))API\n", + ((dm->debug_components & ODM_COMP_API) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, "================================\n"); } else if (dm_value[0] == 101) { - p_dm_odm->debug_components = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Disable all debug components")); + dm->debug_components = 0; + PDM_SNPF(out_len, used, output + used, out_len - used, "Disable all debug components\n"); } else { if (dm_value[1] == 1) /*enable*/ - p_dm_odm->debug_components |= (one << dm_value[0]); + dm->debug_components |= (one << dm_value[0]); else if (dm_value[1] == 2) /*disable*/ - p_dm_odm->debug_components &= ~(one << dm_value[0]); + dm->debug_components &= ~(one << dm_value[0]); else - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); + PDM_SNPF(out_len, used, output + used, out_len - used, "[Warning] 1:on, 2:off\n"); + + if ((BIT(dm_value[0]) == DBG_PHY_STATUS) && (dm_value[1] == 1)) { + + dm->phy_dbg_info.show_phy_sts_all_pkt = (u8)dm_value[2]; + dm->phy_dbg_info.show_phy_sts_max_cnt = (u16)dm_value[3]; + + PDM_SNPF(out_len, used, output + used, out_len - used, "show_phy_sts_all_pkt=%d, show_phy_sts_max=%d\n\n", + dm->phy_dbg_info.show_phy_sts_all_pkt, + dm->phy_dbg_info.show_phy_sts_max_cnt); + + } else if ((BIT(dm_value[0]) == ODM_COMP_COMMON) && (dm_value[1] == 1)) { + dm->cmn_dbg_msg_period = (u8)dm_value[2]; + + if (dm->cmn_dbg_msg_period < PHYDM_WATCH_DOG_PERIOD) + dm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD; + + PDM_SNPF(out_len, used, output + used, out_len - used, "cmn_dbg_msg_period=%d\n", + dm->cmn_dbg_msg_period); + } } - PHYDM_SNPRINTF((output + used, out_len - used, "pre-DbgComponents = 0x%x\n", pre_debug_components)); - PHYDM_SNPRINTF((output + used, out_len - used, "Curr-DbgComponents = 0x%x\n", p_dm_odm->debug_components)); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "pre-DbgComponents = 0x%llx\n", pre_debug_components); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Curr-DbgComponents = 0x%llx\n", dm->debug_components); + PDM_SNPF(out_len, used, output + used, out_len - used, "================================\n"); + + *_used = used; + *_out_len = out_len; } void phydm_fw_debug_trace( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 pre_fw_debug_components, one = 1; u32 used = *_used; u32 out_len = *_out_len; - pre_fw_debug_components = p_dm_odm->fw_debug_components; + pre_fw_debug_components = dm->fw_debug_components; - PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); + PDM_SNPF(out_len, used, output + used, out_len - used, "\n%s\n", + "================================"); if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[FW Debug Component]")); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))RA\n", ((p_dm_odm->fw_debug_components & PHYDM_FW_COMP_RA) ? ("V") : (".")))); - - if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { - PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))MU\n", ((p_dm_odm->fw_debug_components & PHYDM_FW_COMP_MU) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))path Div\n", ((p_dm_odm->fw_debug_components & PHYDM_FW_COMP_PHY_CONFIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))Phy Config\n", ((p_dm_odm->fw_debug_components & PHYDM_FW_COMP_PHY_CONFIG) ? ("V") : (".")))); - } - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s\n", "[FW Debug Component]"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s\n", "================================"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))RA\n", + ((dm->fw_debug_components & PHYDM_FW_COMP_RA) ? ("V") : ("."))); + + if (dm->support_ic_type & PHYDM_IC_3081_SERIES) { + PDM_SNPF(out_len, used, output + used, + out_len - used, "01. (( %s ))MU\n", + ((dm->fw_debug_components & PHYDM_FW_COMP_MU) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "02. (( %s ))path Div\n", + ((dm->fw_debug_components & PHYDM_FW_COMP_PATH_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "03. (( %s ))Power training\n", + ((dm->fw_debug_components & PHYDM_FW_COMP_PT) ? ("V") : ("."))); + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s\n", "================================"); } else { if (dm_value[0] == 101) { - p_dm_odm->fw_debug_components = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Clear all fw debug components")); + dm->fw_debug_components = 0; + PDM_SNPF(out_len, used, output + used, + out_len - used, "%s\n", + "Clear all fw debug components"); } else { if (dm_value[1] == 1) /*enable*/ - p_dm_odm->fw_debug_components |= (one << dm_value[0]); + dm->fw_debug_components |= (one << dm_value[0]); else if (dm_value[1] == 2) /*disable*/ - p_dm_odm->fw_debug_components &= ~(one << dm_value[0]); + dm->fw_debug_components &= ~(one << dm_value[0]); else - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); + PDM_SNPF(out_len, used, output + used, + out_len - used, "%s\n", + "[Warning!!!] 1:enable, 2:disable"); } - if (p_dm_odm->fw_debug_components == 0) { - p_dm_odm->debug_components &= ~ODM_FW_DEBUG_TRACE; - phydm_fw_trace_en_h2c(p_dm_odm, false, p_dm_odm->fw_debug_components, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ + if (dm->fw_debug_components == 0) { + dm->debug_components &= ~DBG_FW_TRACE; + phydm_fw_trace_en_h2c(dm, false, dm->fw_debug_components, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ } else { - p_dm_odm->debug_components |= ODM_FW_DEBUG_TRACE; - phydm_fw_trace_en_h2c(p_dm_odm, true, p_dm_odm->fw_debug_components, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ + dm->debug_components |= DBG_FW_TRACE; + phydm_fw_trace_en_h2c(dm, true, dm->fw_debug_components, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ } } } void phydm_dump_bb_reg( - void *p_dm_void, + void *dm_void, u32 *_used, char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 addr = 0; u32 used = *_used; u32 out_len = *_out_len; @@ -1951,98 +2056,141 @@ phydm_dump_bb_reg( /* BB Reg, For Nseries IC we only need to dump page8 to pageF using 3 digits*/ for (addr = 0x800; addr < 0xfff; addr += 4) { - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%03x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + if (dm->support_ic_type & ODM_IC_11N_SERIES) + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, + out_len - used, + "0x%03x 0x%08x\n", addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); else - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, + out_len - used, + "0x%04x 0x%08x\n", addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); } - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C)) { - - if (p_dm_odm->rf_type > ODM_2T2R) { + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C)) { + if (dm->rf_type > RF_2T2R) { for (addr = 0x1800; addr < 0x18ff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, + out_len - used, + "0x%04x 0x%08x\n", + addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); } - if (p_dm_odm->rf_type > ODM_3T3R) { + if (dm->rf_type > RF_3T3R) { for (addr = 0x1a00; addr < 0x1aff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, + out_len - used, + "0x%04x 0x%08x\n", + addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); } for (addr = 0x1900; addr < 0x19ff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, + out_len - used, + "0x%04x 0x%08x\n", addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); for (addr = 0x1c00; addr < 0x1cff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, + out_len - used, + "0x%04x 0x%08x\n", addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); for (addr = 0x1f00; addr < 0x1fff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, + out_len - used, + "0x%04x 0x%08x\n", addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); } + + *_used = used; + *_out_len = out_len; } void phydm_dump_all_reg( - void *p_dm_void, + void *dm_void, u32 *_used, char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 addr = 0; u32 used = *_used; u32 out_len = *_out_len; /* dump MAC register */ - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "MAC==========\n")); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, out_len - used, + "MAC==========\n"); for (addr = 0; addr < 0x7ff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, out_len - used, "0x%04x 0x%08x\n", + addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); for (addr = 0x1000; addr < 0x17ff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, out_len - used, "0x%04x 0x%08x\n", + addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); /* dump BB register */ - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "BB==========\n")); - phydm_dump_bb_reg(p_dm_odm, &used, output, &out_len); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, out_len - used, + "BB==========\n"); + phydm_dump_bb_reg(dm, &used, output, &out_len); /* dump RF register */ - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "RF-A==========\n")); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, out_len - used, + "RF-A==========\n"); for (addr = 0; addr < 0xFF; addr++) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%02x 0x%05x\n", addr, odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, addr, RFREGOFFSETMASK))); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, out_len - used, "0x%02x 0x%05x\n", + addr, + odm_get_rf_reg(dm, RF_PATH_A, addr, RFREGOFFSETMASK)); - if (p_dm_odm->rf_type > ODM_1T1R) { - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "RF-B==========\n")); + if (dm->rf_type > RF_1T1R) { + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, out_len - used, "RF-B==========\n"); for (addr = 0; addr < 0xFF; addr++) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%02x 0x%05x\n", addr, odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_B, addr, RFREGOFFSETMASK))); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, out_len - used, + "0x%02x 0x%05x\n", addr, + odm_get_rf_reg(dm, RF_PATH_B, addr, RFREGOFFSETMASK)); } - if (p_dm_odm->rf_type > ODM_2T2R) { - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "RF-C==========\n")); + if (dm->rf_type > RF_2T2R) { + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, out_len - used, "RF-C==========\n"); for (addr = 0; addr < 0xFF; addr++) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%02x 0x%05x\n", addr, odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_C, addr, RFREGOFFSETMASK))); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, out_len - used, + "0x%02x 0x%05x\n", addr, + odm_get_rf_reg(dm, RF_PATH_C, addr, RFREGOFFSETMASK)); } - if (p_dm_odm->rf_type > ODM_3T3R) { - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "RF-D==========\n")); + if (dm->rf_type > RF_3T3R) { + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, out_len - used, "RF-D==========\n"); for (addr = 0; addr < 0xFF; addr++) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%02x 0x%05x\n", addr, odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_D, addr, RFREGOFFSETMASK))); + PHYDM_VAST_INFO_SNPRINTF(out_len, used, output + used, out_len - used, + "0x%02x 0x%05x\n", addr, + odm_get_rf_reg(dm, RF_PATH_D, addr, RFREGOFFSETMASK)); } + + *_used = used; + *_out_len = out_len; } void phydm_enable_big_jump( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, boolean state ) { #if (RTL8822B_SUPPORT == 1) - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; if (state == false) { - p_dm_odm->dm_dig_table.enable_adjust_big_jump = false; - odm_set_bb_reg(p_dm_odm, 0x8c8, 0xfe, ((p_dm_dig_table->big_jump_step3 << 5) | (p_dm_dig_table->big_jump_step2 << 3) | p_dm_dig_table->big_jump_step1)); + dm->dm_dig_table.enable_adjust_big_jump = false; + odm_set_bb_reg(dm, 0x8c8, 0xfe, ((dig_t->big_jump_step3 << 5) | (dig_t->big_jump_step2 << 3) | dig_t->big_jump_step1)); } else - p_dm_odm->dm_dig_table.enable_adjust_big_jump = true; + dm->dm_dig_table.enable_adjust_big_jump = true; #endif } @@ -2050,50 +2198,372 @@ phydm_enable_big_jump( void phydm_show_rx_rate( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 *_used, - char *output, + char *output, u32 *_out_len ) { u32 used = *_used; u32 out_len = *_out_len; - PHYDM_SNPRINTF((output + used, out_len - used, "=====Rx SU rate Statistics=====\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[0], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[1], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[2], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[3])); - PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[4], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[5], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[6], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[7])); - PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS8 = %d, 1SS MCS9 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[8], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[9])); - PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[10], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[11], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[12], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[13])); - PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[14], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[15], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[16], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[17])); - PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS8 = %d, 2SS MCS9 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[18], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[19])); - - PHYDM_SNPRINTF((output + used, out_len - used, "=====Rx MU rate Statistics=====\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[0], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[1], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[2], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[3])); - PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[4], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[5], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[6], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[7])); - PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS8 = %d, 1SS MCS9 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[8], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[9])); - PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[10], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[11], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[12], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[13])); - PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[14], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[15], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[16], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[17])); - PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS8 = %d, 2SS MCS9 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[18], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[19])); + PDM_SNPF(out_len, used, output + used, out_len - used, + "=====Rx SU rate Statistics=====\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", + dm->phy_dbg_info.num_qry_vht_pkt[0], + dm->phy_dbg_info.num_qry_vht_pkt[1], + dm->phy_dbg_info.num_qry_vht_pkt[2], + dm->phy_dbg_info.num_qry_vht_pkt[3]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", + dm->phy_dbg_info.num_qry_vht_pkt[4], + dm->phy_dbg_info.num_qry_vht_pkt[5], + dm->phy_dbg_info.num_qry_vht_pkt[6], + dm->phy_dbg_info.num_qry_vht_pkt[7]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "1SS MCS8 = %d, 1SS MCS9 = %d\n", + dm->phy_dbg_info.num_qry_vht_pkt[8], + dm->phy_dbg_info.num_qry_vht_pkt[9]); + +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", + dm->phy_dbg_info.num_qry_vht_pkt[10], + dm->phy_dbg_info.num_qry_vht_pkt[11], + dm->phy_dbg_info.num_qry_vht_pkt[12], + dm->phy_dbg_info.num_qry_vht_pkt[13]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", + dm->phy_dbg_info.num_qry_vht_pkt[14], + dm->phy_dbg_info.num_qry_vht_pkt[15], + dm->phy_dbg_info.num_qry_vht_pkt[16], + dm->phy_dbg_info.num_qry_vht_pkt[17]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "2SS MCS8 = %d, 2SS MCS9 = %d\n", + dm->phy_dbg_info.num_qry_vht_pkt[18], + dm->phy_dbg_info.num_qry_vht_pkt[19]); + } +#endif + + PDM_SNPF(out_len, used, output + used, out_len - used, + "=====Rx MU rate Statistics=====\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", + dm->phy_dbg_info.num_qry_mu_vht_pkt[0], + dm->phy_dbg_info.num_qry_mu_vht_pkt[1], + dm->phy_dbg_info.num_qry_mu_vht_pkt[2], + dm->phy_dbg_info.num_qry_mu_vht_pkt[3]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", + dm->phy_dbg_info.num_qry_mu_vht_pkt[4], + dm->phy_dbg_info.num_qry_mu_vht_pkt[5], + dm->phy_dbg_info.num_qry_mu_vht_pkt[6], + dm->phy_dbg_info.num_qry_mu_vht_pkt[7]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "1SS MCS8 = %d, 1SS MCS9 = %d\n", + dm->phy_dbg_info.num_qry_mu_vht_pkt[8], + dm->phy_dbg_info.num_qry_mu_vht_pkt[9]); + +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", + dm->phy_dbg_info.num_qry_mu_vht_pkt[10], + dm->phy_dbg_info.num_qry_mu_vht_pkt[11], + dm->phy_dbg_info.num_qry_mu_vht_pkt[12], + dm->phy_dbg_info.num_qry_mu_vht_pkt[13]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", + dm->phy_dbg_info.num_qry_mu_vht_pkt[14], + dm->phy_dbg_info.num_qry_mu_vht_pkt[15], + dm->phy_dbg_info.num_qry_mu_vht_pkt[16], + dm->phy_dbg_info.num_qry_mu_vht_pkt[17]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "2SS MCS8 = %d, 2SS MCS9 = %d\n", + dm->phy_dbg_info.num_qry_mu_vht_pkt[18], + dm->phy_dbg_info.num_qry_mu_vht_pkt[19]); + } +#endif + *_used = used; + *_out_len = out_len; } #endif +void +phydm_per_tone_evm( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i, j; + u32 used = *_used; + u32 out_len = *_out_len; + u32 var1[4] = {0}; + u32 value32, tone_num, round; + s8 rxevm_0, rxevm_1; + s32 avg_num, evm_tone_0[256] = {0}, evm_tone_1[256] = {0}; + s32 rxevm_sum_0, rxevm_sum_1; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + pr_debug("n series not support yet !\n"); + return; + } + + for (i = 0; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + avg_num = var1[0]; + round = var1[1]; + + if (dm->is_linked) { + pr_debug("ID=((%d)), BW=((%d)), fc=((CH-%d))\n", dm->curr_station_id, + 20<<*dm->band_width, *dm->channel); + pr_debug("avg_num =((%d)), round =((%d))\n", avg_num, round); + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + watchdog_stop(dm->priv); + #endif + for (j = 0; j < round; j++) { + pr_debug("\nround((%d))\n", (j + 1)); + if (*dm->band_width == CHANNEL_WIDTH_20) { + for (tone_num = 228; tone_num <= 255; tone_num++) { + odm_set_bb_reg(dm, 0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + value32 = odm_get_bb_reg(dm, 0xF8c, MASKDWORD); + + rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone((-%-3d)) RXEVM (1ss/2ss) =%d , %d\n", (256 - tone_num), evm_tone_0[tone_num], evm_tone_1[tone_num]); + } + + for (tone_num = 1; tone_num <= 28; tone_num++) { + odm_set_bb_reg(dm, 0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + value32 = odm_get_bb_reg(dm, 0xF8c, MASKDWORD); + + rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(( %-3d)) RXEVM (1ss/2ss) =%d , %d\n", tone_num, evm_tone_0[tone_num], evm_tone_1[tone_num]); + } + } else if (*dm->band_width == CHANNEL_WIDTH_40) { + for (tone_num = 198; tone_num <= 254; tone_num++) { + odm_set_bb_reg(dm, 0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + value32 = odm_get_bb_reg(dm, 0xF8c, MASKDWORD); + + rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone((-%-3d)) RXEVM (1ss/2ss) =%d , %d\n", (256 - tone_num), evm_tone_0[tone_num], evm_tone_1[tone_num]); + } + + for (tone_num = 2; tone_num <= 58; tone_num++) { + odm_set_bb_reg(dm, 0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + value32 = odm_get_bb_reg(dm, 0xF8c, MASKDWORD); + + rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(( %-3d)) RXEVM (1ss/2ss) =%d , %d\n", tone_num, evm_tone_0[tone_num], evm_tone_1[tone_num]); + } + } else if (*dm->band_width == CHANNEL_WIDTH_80) { + for (tone_num = 134; tone_num <= 254; tone_num++) { + odm_set_bb_reg(dm, 0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + value32 = odm_get_bb_reg(dm, 0xF8c, MASKDWORD); + + rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone((-%-3d)) RXEVM (1ss/2ss) =%d , %d\n", (256 - tone_num), evm_tone_0[tone_num], evm_tone_1[tone_num]); + } + + for (tone_num = 2; tone_num <= 122; tone_num++) { + odm_set_bb_reg(dm, 0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + value32 = odm_get_bb_reg(dm, 0xF8c, MASKDWORD); + + rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(( %-3d)) RXEVM (1ss/2ss) =%d , %d\n", tone_num, evm_tone_0[tone_num], evm_tone_1[tone_num]); + } + } + } + } else + PDM_SNPF(out_len, used, output + used, out_len - used, + "No Link !!\n"); + +} + +void +phydm_api_adjust( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + boolean is_enable_dbg_mode; + u8 central_ch, primary_ch_idx; + enum channel_width bandwidth; + +#ifdef PHYDM_COMMON_API_SUPPORT + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en} {ch_num} {prm_ch 1/2/3/4/9/10} {0:20M, 1:40M, 2:80M}\n"); + goto out; + + } + + if ((dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)) == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "This IC doesn't support PHYDM API function\n"); + /**/ + goto out; + } + + for (i = 0; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + is_enable_dbg_mode = (boolean)var1[0]; + central_ch = (u8) var1[1]; + primary_ch_idx = (u8) var1[2]; + bandwidth = (enum channel_width)var1[3]; + + if (is_enable_dbg_mode) { + dm->is_disable_phy_api = false; + phydm_api_switch_bw_channel(dm, central_ch, primary_ch_idx, bandwidth); + dm->is_disable_phy_api = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "central_ch = %d, primary_ch_idx = %d, bandwidth = %d\n", + central_ch, primary_ch_idx, bandwidth); + } else { + dm->is_disable_phy_api = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable API debug mode\n"); + } +out: +#else + PDM_SNPF(out_len, used, output + used, out_len - used, + "This IC doesn't support PHYDM API function\n"); +#endif + + *_used = used; + *_out_len = out_len; +} + void phydm_parameter_adjust( - void *p_dm_void, + void *dm_void, char input[][16], u32 *_used, char *output, @@ -2101,8 +2571,8 @@ phydm_parameter_adjust( u32 input_num ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK); char help[] = "-h"; u32 var1[10] = {0}; u32 used = *_used; @@ -2110,22 +2580,27 @@ phydm_parameter_adjust( u8 i; if ((strcmp(input[1], help) == 0)) { - PHYDM_SNPRINTF((output + used, out_len - used, "1. X_cap = ((0x%x))\n", p_cfo_track->crystal_cap)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "1. X_cap = ((0x%x))\n", + cfo_track->crystal_cap); } else { PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); if (var1[0] == 0) { - PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]); - phydm_set_crystal_cap(p_dm_odm, (u8)var1[1]); - PHYDM_SNPRINTF((output + used, out_len - used, "X_cap = ((0x%x))\n", p_cfo_track->crystal_cap)); + phydm_set_crystal_cap(dm, (u8)var1[1]); + PDM_SNPF(out_len, used, output + used, + out_len - used, "X_cap = ((0x%x))\n", + cfo_track->crystal_cap); } } + *_used = used; + *_out_len = out_len; } -struct _PHYDM_COMMAND { +struct phydm_command { char name[16]; u8 id; }; @@ -2133,6 +2608,7 @@ struct _PHYDM_COMMAND { enum PHYDM_CMD_ID { PHYDM_HELP, PHYDM_DEMO, + PHYDM_DIG, PHYDM_RA, PHYDM_PROFILE, PHYDM_ANTDIV, @@ -2142,6 +2618,9 @@ enum PHYDM_CMD_ID { PHYDM_SUPPORT_ABILITY, PHYDM_RF_SUPPORTABILITY, PHYDM_RF_PROFILE, + PHYDM_RF_IQK_INFO, + PHYDM_IQK, + PHYDM_IQK_DEBUG, PHYDM_GET_TXAGC, PHYDM_SET_TXAGC, PHYDM_SMART_ANT, @@ -2149,31 +2628,39 @@ enum PHYDM_CMD_ID { PHYDM_TRX_PATH, PHYDM_LA_MODE, PHYDM_DUMP_REG, - PHYDM_HANG, + PHYDM_AUTO_DBG, PHYDM_BIG_JUMP, PHYDM_SHOW_RXRATE, PHYDM_NBI_EN, PHYDM_CSI_MASK_EN, - PHYDM_DFS, - PHYDM_IQK, + PHYDM_DFS_DEBUG, PHYDM_NHM, PHYDM_CLM, + PHYDM_FAHM, + PHYDM_ENV_MNTR, PHYDM_BB_INFO, PHYDM_TXBF, - PHYDM_PAUSE_DIG_EN, PHYDM_H2C, PHYDM_ANT_SWITCH, PHYDM_DYNAMIC_RA_PATH, + PHYDM_ADAPTIVE_SOML, PHYDM_PSD, PHYDM_DEBUG_PORT, - PHYDM_HTSTF_CONTROL, + PHYDM_DIS_HTSTF_CONTROL, PHYDM_TUNE_PARAMETER, - PHYDM_ADAPTIVITY_DEBUG + PHYDM_ADAPTIVITY_DEBUG, + PHYDM_DIS_DYM_ANT_WEIGHTING, + PHYDM_FORECE_PT_STATE, + PHYDM_DIS_RXHP_CTR, + PHYDM_STA_INFO, + PHYDM_PAUSE_FUNC, + PHYDM_PER_TONE_EVM }; -struct _PHYDM_COMMAND phy_dm_ary[] = { +struct phydm_command phy_dm_ary[] = { {"-h", PHYDM_HELP}, /*do not move this element to other position*/ {"demo", PHYDM_DEMO}, /*do not move this element to other position*/ + {"dig", PHYDM_DIG}, {"ra", PHYDM_RA}, {"profile", PHYDM_PROFILE}, {"antdiv", PHYDM_ANTDIV}, @@ -2183,6 +2670,9 @@ struct _PHYDM_COMMAND phy_dm_ary[] = { {"ability", PHYDM_SUPPORT_ABILITY}, {"rf_ability", PHYDM_RF_SUPPORTABILITY}, {"rf_profile", PHYDM_RF_PROFILE}, + {"iqk_info", PHYDM_RF_IQK_INFO}, + {"iqk", PHYDM_IQK}, + {"iqk_dbg", PHYDM_IQK_DEBUG}, {"get_txagc", PHYDM_GET_TXAGC}, {"set_txagc", PHYDM_SET_TXAGC}, {"smtant", PHYDM_SMART_ANT}, @@ -2190,33 +2680,40 @@ struct _PHYDM_COMMAND phy_dm_ary[] = { {"trxpath", PHYDM_TRX_PATH}, {"lamode", PHYDM_LA_MODE}, {"dumpreg", PHYDM_DUMP_REG}, - {"hang", PHYDM_HANG}, + {"auto_dbg", PHYDM_AUTO_DBG}, {"bigjump", PHYDM_BIG_JUMP}, {"rxrate", PHYDM_SHOW_RXRATE}, {"nbi", PHYDM_NBI_EN}, {"csi_mask", PHYDM_CSI_MASK_EN}, - {"dfs", PHYDM_DFS}, - {"iqk", PHYDM_IQK}, + {"dfs", PHYDM_DFS_DEBUG}, {"nhm", PHYDM_NHM}, {"clm", PHYDM_CLM}, + {"fahm", PHYDM_FAHM}, + {"env_mntr", PHYDM_ENV_MNTR}, {"bbinfo", PHYDM_BB_INFO}, {"txbf", PHYDM_TXBF}, - {"pause_dig", PHYDM_PAUSE_DIG_EN}, {"h2c", PHYDM_H2C}, {"ant_switch", PHYDM_ANT_SWITCH}, {"drp", PHYDM_DYNAMIC_RA_PATH}, + {"soml", PHYDM_ADAPTIVE_SOML}, {"psd", PHYDM_PSD}, {"dbgport", PHYDM_DEBUG_PORT}, - {"htstf", PHYDM_HTSTF_CONTROL}, + {"dis_htstf", PHYDM_DIS_HTSTF_CONTROL}, {"tune_para", PHYDM_TUNE_PARAMETER}, - {"adapt_debug", PHYDM_ADAPTIVITY_DEBUG} + {"adapt_debug", PHYDM_ADAPTIVITY_DEBUG}, + {"dis_dym_ant_wgt", PHYDM_DIS_DYM_ANT_WEIGHTING}, + {"force_pt_state", PHYDM_FORECE_PT_STATE}, + {"dis_drxhp", PHYDM_DIS_RXHP_CTR}, + {"sta_info", PHYDM_STA_INFO}, + {"pause", PHYDM_PAUSE_FUNC}, + {"evm", PHYDM_PER_TONE_EVM} }; -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +#endif /*#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ void phydm_cmd_parser( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, char input[][MAX_ARGV], u32 input_num, u8 flag, @@ -2224,24 +2721,22 @@ phydm_cmd_parser( u32 out_len ) { -#if CONFIG_PHYDM_DEBUG_FUNCTION +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION u32 used = 0; u8 id = 0; int var1[10] = {0}; - int i, input_idx = 0, phydm_ary_size; + int i, input_idx = 0, phydm_ary_size = sizeof(phy_dm_ary) / sizeof(struct phydm_command); char help[] = "-h"; if (flag == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "GET, nothing to print\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, "GET, nothing to print\n"); return; } - PHYDM_SNPRINTF((output + used, out_len - used, "\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, "\n"); /* Parsing Cmd ID */ if (input_num) { - - phydm_ary_size = sizeof(phy_dm_ary) / sizeof(struct _PHYDM_COMMAND); for (i = 0; i < phydm_ary_size; i++) { if (strcmp(phy_dm_ary[i].name, input[0]) == 0) { id = phy_dm_ary[i].id; @@ -2249,19 +2744,19 @@ phydm_cmd_parser( } } if (i == phydm_ary_size) { - PHYDM_SNPRINTF((output + used, out_len - used, "SET, command not found!\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, "SET, command not found!\n"); return; } } switch (id) { - case PHYDM_HELP: { - PHYDM_SNPRINTF((output + used, out_len - used, "BB cmd ==>\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "BB cmd ==>\n"); for (i = 0; i < phydm_ary_size - 2; i++) { - - PHYDM_SNPRINTF((output + used, out_len - used, " %-5d: %s\n", i, phy_dm_ary[i + 2].name)); + PDM_SNPF(out_len, used, output + used, + out_len - used, " %-5d: %s\n", i, phy_dm_ary[i + 2].name); /**/ } } @@ -2277,36 +2772,26 @@ phydm_cmd_parser( #endif PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory); - PHYDM_SNPRINTF((output + used, out_len - used, "Decimal value = %d\n", directory)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Decimal value = %d\n", directory); PHYDM_SSCANF(input[2], DCMD_HEX, &directory); - PHYDM_SNPRINTF((output + used, out_len - used, "Hex value = 0x%x\n", directory)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Hex value = 0x%x\n", directory); PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp); - PHYDM_SNPRINTF((output + used, out_len - used, "Char = %c\n", char_temp)); - PHYDM_SNPRINTF((output + used, out_len - used, "String = %s\n", input[4])); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Char = %c\n", char_temp); + PDM_SNPF(out_len, used, output + used, out_len - used, + "String = %s\n", input[4]); } break; + + case PHYDM_DIG: - case PHYDM_RA: - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - - /*PHYDM_SNPRINTF((output + used, out_len - used, "new SET, RA_var[%d]= (( %d ))\n", i, var1[i]));*/ - input_idx++; - } - } - - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_RA_debug\n"));*/ -#if (defined(CONFIG_RA_DBG_CMD)) - odm_RA_debug((void *)p_dm_odm, (u32 *) var1); -#else - phydm_RA_debug_PCR(p_dm_odm, (u32 *)var1, &used, output, &out_len); -#endif - } - + phydm_dig_debug(dm, &input[0], &used, output, &out_len, input_num); + break; + case PHYDM_RA: + phydm_ra_debug(dm, &input[0], &used, output, &out_len); break; case PHYDM_ANTDIV: @@ -2315,15 +2800,15 @@ phydm_cmd_parser( if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i, var1[i]));*/ + /*PDM_SNPF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i, var1[i]));*/ input_idx++; } } if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ + /*PDM_SNPF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - phydm_antdiv_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); + phydm_antdiv_debug(dm, (u32 *)var1, &used, output, &out_len); #endif } @@ -2335,15 +2820,15 @@ phydm_cmd_parser( if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i, var1[i]));*/ + /*PDM_SNPF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i, var1[i]));*/ input_idx++; } } if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ + /*PDM_SNPF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ #if (defined(CONFIG_PATH_DIVERSITY)) - odm_pathdiv_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); + odm_pathdiv_debug(dm, (u32 *)var1, &used, output, &out_len); #endif } @@ -2351,20 +2836,7 @@ phydm_cmd_parser( case PHYDM_DEBUG: - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, Debug_var[%d]= (( %d ))\n", i, var1[i]));*/ - input_idx++; - } - } - - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_debug_comp\n"));*/ - phydm_debug_trace(p_dm_odm, (u32 *)var1, &used, output, &out_len); - } - + phydm_debug_trace(dm, &input[0], &used, output, &out_len); break; @@ -2378,7 +2850,7 @@ phydm_cmd_parser( } if (input_idx >= 1) - phydm_fw_debug_trace(p_dm_odm, (u32 *)var1, &used, output, &out_len); + phydm_fw_debug_trace(dm, (u32 *)var1, &used, output, &out_len); break; @@ -2388,24 +2860,61 @@ phydm_cmd_parser( if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, support ablity_var[%d]= (( %d ))\n", i, var1[i]));*/ + /*PDM_SNPF((output+used, out_len-used, "new SET, support ablity_var[%d]= (( %d ))\n", i, var1[i]));*/ input_idx++; } } if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "support ablity\n"));*/ - phydm_support_ability_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); + /*PDM_SNPF((output+used, out_len-used, "support ablity\n"));*/ + phydm_support_ability_debug(dm, (u32 *)var1, &used, output, &out_len); } break; case PHYDM_RF_SUPPORTABILITY: - halrf_support_ability_debug(p_dm_odm, &input[0], &used, output, &out_len); + halrf_support_ability_debug(dm, &input[0], &used, output, &out_len); break; case PHYDM_RF_PROFILE: - phydm_rf_basic_profile(p_dm_odm, &used, output, &out_len); + halrf_basic_profile(dm, &used, output, &out_len); + break; + + case PHYDM_RF_IQK_INFO: + #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) + halrf_iqk_info_dump(dm, &used, output, &out_len); + #endif + break; + + case PHYDM_IQK: + + PDM_SNPF(out_len, used, output + used, out_len - used, + "TRX IQK Trigger\n"); + halrf_iqk_trigger(dm, false); + + #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) + halrf_iqk_info_dump(dm, &used, output, &out_len); + #endif + + break; + + case PHYDM_IQK_DEBUG: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) { + #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) + halrf_iqk_debug(dm, (u32 *)var1, &used, output, &out_len); + #endif + } break; case PHYDM_SMART_ANT: @@ -2418,58 +2927,33 @@ phydm_cmd_parser( } if (input_idx >= 1) { -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - phydm_hl_smart_ant_debug_type2(p_dm_odm, &input[0], &used, output, &out_len, input_num); - #elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) - phydm_hl_smart_ant_debug(p_dm_odm, &input[0], &used, output, &out_len, input_num); + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + phydm_hl_smart_ant_debug_type2(dm, &input[0], &used, output, &out_len, input_num); + #elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) + phydm_hl_smart_ant_debug(dm, &input[0], &used, output, &out_len, input_num); + #endif + + #endif + + #if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) + phydm_cumitek_smt_ant_debug(dm, &input[0], &used, output, &out_len, input_num); #endif -#endif } break; case PHYDM_API: -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - { - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)) { - boolean is_enable_dbg_mode; - u8 central_ch, primary_ch_idx, bandwidth; - - for (i = 0; i < 4; i++) { - if (input[i + 1]) - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - } - - is_enable_dbg_mode = (boolean)var1[0]; - central_ch = (u8) var1[1]; - primary_ch_idx = (u8) var1[2]; - bandwidth = (enum odm_bw_e) var1[3]; - - if (is_enable_dbg_mode) { - p_dm_odm->is_disable_phy_api = false; - phydm_api_switch_bw_channel(p_dm_odm, central_ch, primary_ch_idx, (enum odm_bw_e) bandwidth); - p_dm_odm->is_disable_phy_api = true; - PHYDM_SNPRINTF((output + used, out_len - used, "central_ch = %d, primary_ch_idx = %d, bandwidth = %d\n", central_ch, primary_ch_idx, bandwidth)); - } else { - p_dm_odm->is_disable_phy_api = false; - PHYDM_SNPRINTF((output + used, out_len - used, "Disable API debug mode\n")); - } - } else - PHYDM_SNPRINTF((output + used, out_len - used, "This IC doesn't support PHYDM API function\n")); - } -#else - PHYDM_SNPRINTF((output + used, out_len - used, "This IC doesn't support PHYDM API function\n")); -#endif + phydm_api_adjust(dm, &input[0], &used, output, &out_len, input_num); break; case PHYDM_PROFILE: - phydm_basic_profile(p_dm_odm, &used, output, &out_len); + phydm_basic_profile(dm, &used, output, &out_len); break; case PHYDM_GET_TXAGC: - phydm_get_txagc(p_dm_odm, &used, output, &out_len); + phydm_get_txagc(dm, &used, output, &out_len); break; case PHYDM_SET_TXAGC: @@ -2484,19 +2968,22 @@ phydm_cmd_parser( } if ((strcmp(input[1], help) == 0)) { - PHYDM_SNPRINTF((output + used, out_len - used, "{En} {pathA~D(0~3)} {rate_idx(Hex), All_rate:0xff} {txagc_idx (Hex)}\n")); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "{En} {pathA~D(0~3)} {rate_idx(Hex), All_rate:0xff} {txagc_idx (Hex)}\n"); /**/ } else { - is_enable_dbg_mode = (boolean)var1[0]; if (is_enable_dbg_mode) { - p_dm_odm->is_disable_phy_api = false; - phydm_set_txagc(p_dm_odm, (u32 *)var1, &used, output, &out_len); - p_dm_odm->is_disable_phy_api = true; + dm->is_disable_phy_api = false; + phydm_set_txagc(dm, (u32 *)var1, &used, output, &out_len); + dm->is_disable_phy_api = true; } else { - p_dm_odm->is_disable_phy_api = false; - PHYDM_SNPRINTF((output + used, out_len - used, "Disable API debug mode\n")); + dm->is_disable_phy_api = false; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Disable API debug mode\n"); } } } @@ -2509,7 +2996,7 @@ phydm_cmd_parser( PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); } #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) { + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) { u8 tx_path, rx_path; boolean is_enable_dbg_mode, is_tx2_path; @@ -2519,29 +3006,33 @@ phydm_cmd_parser( is_tx2_path = (boolean) var1[3]; if (is_enable_dbg_mode) { - p_dm_odm->is_disable_phy_api = false; - phydm_api_trx_mode(p_dm_odm, (enum odm_rf_path_e) tx_path, (enum odm_rf_path_e) rx_path, is_tx2_path); - p_dm_odm->is_disable_phy_api = true; - PHYDM_SNPRINTF((output + used, out_len - used, "tx_path = 0x%x, rx_path = 0x%x, is_tx2_path = %d\n", tx_path, rx_path, is_tx2_path)); + dm->is_disable_phy_api = false; + phydm_api_trx_mode(dm, (enum bb_path) tx_path, (enum bb_path) rx_path, is_tx2_path); + dm->is_disable_phy_api = true; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "tx_path = 0x%x, rx_path = 0x%x, is_tx2_path = %d\n", + tx_path, rx_path, is_tx2_path); } else { - p_dm_odm->is_disable_phy_api = false; - PHYDM_SNPRINTF((output + used, out_len - used, "Disable API debug mode\n")); + dm->is_disable_phy_api = false; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Disable API debug mode\n"); } } else #endif - phydm_config_trx_path(p_dm_odm, (u32 *)var1, &used, output, &out_len); + phydm_config_trx_path(dm, (u32 *)var1, &used, output, &out_len); break; case PHYDM_LA_MODE: -#if (PHYDM_LA_MODE_SUPPORT == 1) - p_dm_odm->support_ability &= ~(ODM_BB_FA_CNT); - phydm_lamode_trigger_setting(p_dm_odm, &input[0], &used, output, &out_len, input_num); - p_dm_odm->support_ability |= ODM_BB_FA_CNT; -#else - PHYDM_SNPRINTF((output + used, out_len - used, "This IC doesn't support LA mode\n")); -#endif + #if (PHYDM_LA_MODE_SUPPORT == 1) + phydm_lamode_trigger_setting(dm, &input[0], &used, output, &out_len, input_num); + #else + PDM_SNPF(out_len, used, output + used, out_len - used, + "This IC doesn't support LA mode\n"); + #endif break; @@ -2555,52 +3046,62 @@ phydm_cmd_parser( } if (type == 0) - phydm_dump_bb_reg(p_dm_odm, &used, output, &out_len); + phydm_dump_bb_reg(dm, &used, output, &out_len); else if (type == 1) - phydm_dump_all_reg(p_dm_odm, &used, output, &out_len); + phydm_dump_all_reg(dm, &used, output, &out_len); } break; case PHYDM_BIG_JUMP: { #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + if (dm->support_ic_type & ODM_RTL8822B) { if (input[1]) { PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - phydm_enable_big_jump(p_dm_odm, (boolean)(var1[0])); + phydm_enable_big_jump(dm, (boolean)(var1[0])); } else - PHYDM_SNPRINTF((output + used, out_len - used, "unknown command!\n")); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "unknown command!\n"); } else - PHYDM_SNPRINTF((output + used, out_len - used, "The command is only for 8822B!\n")); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "The command is only for 8822B!\n"); #endif break; } - case PHYDM_HANG: - phydm_bb_rx_hang_info(p_dm_odm, &used, output, &out_len); + case PHYDM_AUTO_DBG: + #ifdef PHYDM_AUTO_DEGBUG + phydm_auto_dbg_console(dm, &input[0], &used, output, &out_len, input_num); + #endif break; case PHYDM_SHOW_RXRATE: + { #if (RTL8822B_SUPPORT == 1 | RTL8821C_SUPPORT == 1 | RTL8814B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & PHYDM_IC_SUPPORT_MU_BFEE) { - u8 rate_idx; + u8 rate_idx; + if ((dm->support_ic_type & PHYDM_IC_SUPPORT_MU_BFEE) == 0) + break; - if (input[1]) - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + if (input[1]) + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - if (var1[0] == 1) - phydm_show_rx_rate(p_dm_odm, &used, output, &out_len); - else { - PHYDM_SNPRINTF((output + used, out_len - used, "Reset Rx rate counter\n")); + if (var1[0] == 1) + phydm_show_rx_rate(dm, &used, output, &out_len); + else { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Reset Rx rate counter\n"); - for (rate_idx = 0; rate_idx < 40; rate_idx++) { - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[rate_idx] = 0; - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[rate_idx] = 0; - } + for (rate_idx = 0; rate_idx < VHT_RATE_NUM; rate_idx++) { + dm->phy_dbg_info.num_qry_vht_pkt[rate_idx] = 0; + dm->phy_dbg_info.num_qry_mu_vht_pkt[rate_idx] = 0; } } #endif break; + } case PHYDM_NBI_EN: @@ -2612,8 +3113,7 @@ phydm_cmd_parser( } if (input_idx >= 1) { - - phydm_api_debug(p_dm_odm, PHYDM_API_NBI, (u32 *)var1, &used, output, &out_len); + phydm_api_debug(dm, PHYDM_API_NBI, (u32 *)var1, &used, output, &out_len); /**/ } @@ -2630,199 +3130,71 @@ phydm_cmd_parser( } if (input_idx >= 1) { - - phydm_api_debug(p_dm_odm, PHYDM_API_CSI_MASK, (u32 *)var1, &used, output, &out_len); + phydm_api_debug(dm, PHYDM_API_CSI_MASK, (u32 *)var1, &used, output, &out_len); /**/ } break; - case PHYDM_DFS: -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - { - u32 var[6] = {0}; + case PHYDM_DFS_DEBUG: + { +#ifdef CONFIG_PHYDM_DFS_MASTER + u32 var[4] = {0}; - for (i = 0; i < 6; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var[i]); - input_idx++; - } + for (i = 0; i < 4; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var[i]); + input_idx++; } - - if (input_idx >= 1) - phydm_dfs_debug(p_dm_odm, var, &used, output, &out_len); } -#endif - break; - case PHYDM_IQK: -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_iq_calibrate(p_dm_odm->priv); - PHYDM_SNPRINTF((output + used, out_len - used, "IQK !!\n")); -#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PHY_IQCalibrate(p_dm_odm->adapter, false); - PHYDM_SNPRINTF((output + used, out_len - used, "IQK !!\n")); + if (input_idx >= 1) + phydm_dfs_debug(dm, var, &used, output, &out_len); #endif break; + } case PHYDM_NHM: - { - u8 target_rssi; - u16 nhm_period = 0xC350; /* 200ms */ - u8 IGI; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; - - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - - if (input_num == 1) { - - ccx_info->echo_NHM_en = false; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger NHM: echo nhm 1\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r (Exclude CCA)\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger NHM: echo nhm 2\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r (Include CCA)\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Get NHM results: echo nhm 3\n")); - - return; - } - - /* NMH trigger */ - if ((var1[0] <= 2) && (var1[0] != 0)) { - - ccx_info->echo_NHM_en = true; - ccx_info->echo_IGI = (u8)odm_get_bb_reg(p_dm_odm, 0xC50, MASKBYTE0); - - target_rssi = ccx_info->echo_IGI - 10; - - ccx_info->NHM_th[0] = (target_rssi - 15 + 10) * 2; - - for (i = 1; i <= 10; i++) - ccx_info->NHM_th[i] = ccx_info->NHM_th[0] + 6 * i; - - /* 4 1. store previous NHM setting */ - phydm_nhm_setting(p_dm_odm, STORE_NHM_SETTING); - - /* 4 2. Set NHM period, 0x990[31:16]=0xC350, Time duration for NHM unit: 4us, 0xC350=200ms */ - ccx_info->NHM_period = nhm_period; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Monitor NHM for %d us", nhm_period * 4)); - - /* 4 3. Set NHM inexclude_txon, inexclude_cca, ccx_en */ - - - ccx_info->nhm_inexclude_cca = (var1[0] == 1) ? NHM_EXCLUDE_CCA : NHM_INCLUDE_CCA; - ccx_info->nhm_inexclude_txon = NHM_EXCLUDE_TXON; - - phydm_nhm_setting(p_dm_odm, SET_NHM_SETTING); - - for (i = 0; i <= 10; i++) { - - if (i == 5) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x, echo_IGI = 0x%x", i, ccx_info->NHM_th[i], ccx_info->echo_IGI)); - else if (i == 10) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x\n", i, ccx_info->NHM_th[i])); - else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x", i, ccx_info->NHM_th[i])); - } - - /* 4 4. Trigger NHM */ - phydm_nhm_trigger(p_dm_odm); - - } - - /*Get NHM results*/ - else if (var1[0] == 3) { - - IGI = (u8)odm_get_bb_reg(p_dm_odm, 0xC50, MASKBYTE0); - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Cur_IGI = 0x%x", IGI)); - - phydm_get_nhm_result(p_dm_odm); - - /* 4 Resotre NHM setting */ - phydm_nhm_setting(p_dm_odm, RESTORE_NHM_SETTING); - - for (i = 0; i <= 11; i++) { - - if (i == 5) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d, echo_IGI = 0x%x", i, ccx_info->NHM_result[i], ccx_info->echo_IGI)); - else if (i == 11) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d\n", i, ccx_info->NHM_result[i])); - else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d", i, ccx_info->NHM_result[i])); - } - - ccx_info->echo_NHM_en = false; - } else { - - ccx_info->echo_NHM_en = false; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger NHM: echo nhm 1\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r (Exclude CCA)\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger NHM: echo nhm 2\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r (Include CCA)\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Get NHM results: echo nhm 3\n")); - - return; - } - } - break; + #ifdef NHM_SUPPORT + phydm_nhm_dbg(dm, &input[0], &used, output, &out_len, input_num); + #endif + break; case PHYDM_CLM: - { - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - - /* PHYDM_SNPRINTF((output + used, out_len - used, "\r\n input_num = %d\n", input_num)); */ - - if (input_num == 1) { - - ccx_info->echo_CLM_en = false; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger CLM: echo clm 1\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Get CLM results: echo clm 2\n")); - return; - } - - /* Set & trigger CLM */ - if (var1[0] == 1) { - - ccx_info->echo_CLM_en = true; - ccx_info->CLM_period = 0xC350; /*100ms*/ - phydm_clm_setting(p_dm_odm); - phydm_clm_trigger(p_dm_odm); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Monitor CLM for 200ms\n")); - } - - /* Get CLM results */ - else if (var1[0] == 2) { - - ccx_info->echo_CLM_en = false; - phydm_get_clm_result(p_dm_odm); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n CLM_result = %d us\n", ccx_info->CLM_result * 4)); + #ifdef CLM_SUPPORT + phydm_clm_dbg(dm, &input[0], &used, output, &out_len, input_num); + #endif + break; - } else { + #ifdef FAHM_SUPPORT + case PHYDM_FAHM: + phydm_fahm_dbg(dm, &input[0], &used, output, &out_len, input_num); + break; + #endif - ccx_info->echo_CLM_en = false; - PHYDM_SNPRINTF((output + used, out_len - used, "\n\r Error command !\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger CLM: echo clm 1\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Get CLM results: echo clm 2\n")); - } - } - break; + case PHYDM_ENV_MNTR: + phydm_env_mntr_dbg(dm, &input[0], &used, output, &out_len, input_num); + break; + case PHYDM_BB_INFO: { s32 value32 = 0; - phydm_bb_debug_info(p_dm_odm, &used, output, &out_len); + phydm_bb_debug_info(dm, &used, output, &out_len); - if (p_dm_odm->support_ic_type & ODM_RTL8822B && input[1]) { + if (dm->support_ic_type & ODM_RTL8822B && input[1]) { PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - odm_set_bb_reg(p_dm_odm, 0x1988, 0x003fff00, var1[0]); - value32 = odm_get_bb_reg(p_dm_odm, 0xf84, MASKDWORD); + odm_set_bb_reg(dm, 0x1988, 0x003fff00, var1[0]); + value32 = odm_get_bb_reg(dm, 0xf84, MASKDWORD); value32 = (value32 & 0xff000000) >> 24; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = condition num = %d, subcarriers = %d\n", "Over condition num subcarrier", var1[0], value32)); - odm_set_bb_reg(p_dm_odm, 0x1988, BIT(22), 0x0); /*disable report condition number*/ + PDM_SNPF(out_len, used, output + used, + out_len - used, + "\r\n %-35s = condition num = %d, subcarriers = %d\n", + "Over condition num subcarrier", + var1[0], value32); + odm_set_bb_reg(dm, 0x1988, BIT(22), 0x0); /*disable report condition number*/ } } break; @@ -2831,70 +3203,77 @@ phydm_cmd_parser( { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (BEAMFORMING_SUPPORT == 1) - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); if (var1[0] == 0) { - p_beamforming_info->apply_v_matrix = false; - p_beamforming_info->snding3ss = true; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n dont apply V matrix and 3SS 789 snding\n")); + beamforming_info->apply_v_matrix = false; + beamforming_info->snding3ss = true; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "\r\n dont apply V matrix and 3SS 789 snding\n"); } else if (var1[0] == 1) { - p_beamforming_info->apply_v_matrix = true; - p_beamforming_info->snding3ss = true; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n apply V matrix and 3SS 789 snding\n")); + beamforming_info->apply_v_matrix = true; + beamforming_info->snding3ss = true; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "\r\n apply V matrix and 3SS 789 snding\n"); } else if (var1[0] == 2) { - p_beamforming_info->apply_v_matrix = true; - p_beamforming_info->snding3ss = false; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n default txbf setting\n")); + beamforming_info->apply_v_matrix = true; + beamforming_info->snding3ss = false; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "\r\n default txbf setting\n"); } else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n unknown cmd!!\n")); + PDM_SNPF(out_len, used, output + used, + out_len - used, "\r\n unknown cmd!!\n"); #else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n no TxBF !!\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n no TxBF !!\n"); #endif #endif } - break; - - case PHYDM_PAUSE_DIG_EN: + break; + case PHYDM_H2C: - for (i = 0; i < 5; i++) { + for (i = 0; i < 8; i++) { if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); input_idx++; } } - if (input_idx >= 1) { - if (var1[0] == 0) { - odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_7, (u8)var1[1]); - PHYDM_SNPRINTF((output + used, out_len - used, "Set IGI_value = ((%x))\n", var1[1])); - } else if (var1[0] == 1) { - odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_7, (u8)var1[1]); - PHYDM_SNPRINTF((output + used, out_len - used, "Resume IGI_value\n")); - } else - PHYDM_SNPRINTF((output + used, out_len - used, "echo (1:pause, 2resume) (IGI_value)\n")); - } + if (input_idx >= 1) + phydm_h2C_debug(dm, (u32 *)var1, &used, output, &out_len); + break; - case PHYDM_H2C: + case PHYDM_ANT_SWITCH: for (i = 0; i < 8; i++) { if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); input_idx++; } } - if (input_idx >= 1) - phydm_h2C_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); + if (input_idx >= 1) { +#if (RTL8821A_SUPPORT == 1) + phydm_set_ext_switch(dm, (u32 *)var1, &used, output, &out_len); +#else + PDM_SNPF(out_len, used, output + used, + out_len - used, "Not Support IC"); +#endif + } break; - case PHYDM_ANT_SWITCH: + case PHYDM_DYNAMIC_RA_PATH: +#ifdef CONFIG_DYNAMIC_RX_PATH for (i = 0; i < 8; i++) { if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); @@ -2902,21 +3281,19 @@ phydm_cmd_parser( } } - if (input_idx >= 1) { + if (input_idx >= 1) + phydm_drp_debug(dm, (u32 *)var1, &used, output, &out_len); -#if (RTL8821A_SUPPORT == 1) - phydm_set_ext_switch(p_dm_odm, (u32 *)var1, &used, output, &out_len); #else - PHYDM_SNPRINTF((output + used, out_len - used, "Not Support IC")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Not Support IC"); #endif - } - break; - case PHYDM_DYNAMIC_RA_PATH: + case PHYDM_ADAPTIVE_SOML: -#if (CONFIG_DYNAMIC_RX_PATH == 1) +#ifdef CONFIG_ADAPTIVE_SOML for (i = 0; i < 8; i++) { if (input[i + 1]) { PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); @@ -2925,18 +3302,19 @@ phydm_cmd_parser( } if (input_idx >= 1) - phydm_drp_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); + phydm_soml_debug(dm, (u32 *)var1, &used, output, &out_len); #else - PHYDM_SNPRINTF((output + used, out_len - used, "Not Support IC")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Not Support IC"); #endif break; case PHYDM_PSD: - #if (CONFIG_PSD_TOOL== 1) - phydm_psd_debug(p_dm_odm, &input[0], &used, output, &out_len, input_num); + #ifdef CONFIG_PSD_TOOL + phydm_psd_debug(dm, &input[0], &used, output, &out_len, input_num); #endif break; @@ -2946,36 +3324,48 @@ phydm_cmd_parser( u32 dbg_port_value; PHYDM_SSCANF(input[1], DCMD_HEX, &var1[0]); - - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_3, var1[0])) {/*set debug port to 0x0*/ - dbg_port_value = phydm_get_bb_dbg_port_value(p_dm_odm); - phydm_release_bb_dbg_port(p_dm_odm); + dm->debug_components |= ODM_COMP_API; + if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3, var1[0])) {/*set debug port to 0x0*/ + + dbg_port_value = phydm_get_bb_dbg_port_value(dm); + phydm_release_bb_dbg_port(dm); - PHYDM_SNPRINTF((output + used, out_len - used, "Debug Port[0x%x] = ((0x%x))\n", var1[1], dbg_port_value)); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Dbg Port[0x%x] = ((0x%x))\n", + var1[0], dbg_port_value); } + dm->debug_components &= (~ODM_COMP_API); } break; - case PHYDM_HTSTF_CONTROL: + case PHYDM_DIS_HTSTF_CONTROL: { if (input[1]) PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); if (var1[0] == 1) { - /* phydm_dynamic_switch_htstf_mumimo_8822b(p_dm_odm);*/ - p_dm_odm->bhtstfenabled = TRUE; - PHYDM_SNPRINTF((output + used, out_len - used, "Dynamic HT-STF Gain Control is Enable\n")); + + /* setting being false is for debug */ + dm->bhtstfdisabled = true; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Dynamic HT-STF Gain Control is Disable\n"); } else { - p_dm_odm->bhtstfenabled = FALSE; - PHYDM_SNPRINTF((output + used, out_len - used, "Dynamic HT-STF Gain Control is Disable\n")); + + /* default setting should be true, always be dynamic control*/ + dm->bhtstfdisabled = false; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Dynamic HT-STF Gain Control is Enable\n"); } } break; case PHYDM_TUNE_PARAMETER: - phydm_parameter_adjust(p_dm_odm, &input[0], &used, output, &out_len, input_num); + phydm_parameter_adjust(dm, &input[0], &used, output, &out_len, input_num); break; case PHYDM_ADAPTIVITY_DEBUG: @@ -2988,16 +3378,74 @@ phydm_cmd_parser( } if (input_idx >= 1) - phydm_adaptivity_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); + phydm_adaptivity_debug(dm, (u32 *)var1, &used, output, &out_len); + + break; + + case PHYDM_DIS_DYM_ANT_WEIGHTING: + #ifdef DYN_ANT_WEIGHTING_SUPPORT + phydm_dyn_ant_weight_dbg(dm, &input[0], &used, output, &out_len, input_num); + #endif + break; + case PHYDM_FORECE_PT_STATE: + { + #ifdef PHYDM_POWER_TRAINING_SUPPORT + phydm_pow_train_debug(dm, &input[0], &used, output, &out_len, input_num); + #else + PDM_SNPF(out_len, used, output + used, out_len - used, "Pow training: Not Support\n"); + #endif + + break; + } + + case PHYDM_DIS_RXHP_CTR: + { + if (input[1]) + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 1) { + /* the setting being on is at debug mode to disconnect RxHP seeting with SoML on/odd */ + dm->disrxhpsoml = true; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Dynamic RxHP Control with SoML on/off is Disable\n"); + } + else if (var1[0] == 0) { + /* default setting, RxHP setting will follow SoML on/off setting */ + dm->disrxhpsoml = false; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Dynamic RxHP Control with SoML on/off is Enable\n"); + } + else { + dm->disrxhpsoml = false; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Default Setting, Dynamic RxHP Control with SoML on/off is Enable\n"); + } + } + break; + + case PHYDM_STA_INFO: + phydm_show_sta_info(dm, &input[0], &used, output, &out_len, input_num); + break; + + case PHYDM_PAUSE_FUNC: + phydm_pause_func_console(dm, &input[0], &used, output, &out_len, input_num); + break; + + case PHYDM_PER_TONE_EVM: + phydm_per_tone_evm(dm, &input[0], &used, output, &out_len, input_num); break; default: - PHYDM_SNPRINTF((output + used, out_len - used, "SET, unknown command!\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "SET, unknown command!\n"); break; } -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +#endif /*#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ } #ifdef __ECOS @@ -3020,7 +3468,7 @@ char *strsep(char **s, const char *ct) #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) s32 phydm_cmd( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, char *input, u32 in_len, u8 flag, @@ -3044,7 +3492,7 @@ phydm_cmd( if (argc == 1) argv[0][strlen(argv[0]) - 1] = '\0'; - phydm_cmd_parser(p_dm_odm, argv, argc, flag, output, out_len); + phydm_cmd_parser(dm, argv, argc, flag, output, out_len); return 0; } @@ -3053,81 +3501,85 @@ phydm_cmd( void phydm_fw_trace_handler( - void *p_dm_void, + void *dm_void, u8 *cmd_buf, u8 cmd_len ) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; /*u8 debug_trace_11byte[60];*/ u8 freg_num, c2h_seq, buf_0 = 0; - if (!(p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES)) + + if (!(dm->support_ic_type & PHYDM_IC_3081_SERIES)) return; - if (cmd_len > 12) + if ((cmd_len > 12) || (cmd_len == 0)) { + pr_debug("[Warning] Error C2H cmd_len=%d\n", cmd_len); return; + } buf_0 = cmd_buf[0]; freg_num = (buf_0 & 0xf); c2h_seq = (buf_0 & 0xf0) >> 4; - /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] freg_num = (( %d )), c2h_seq = (( %d ))\n", freg_num,c2h_seq ));*/ + /*PHYDM_DBG(dm, DBG_FW_TRACE,"[FW debug message] freg_num = (( %d )), c2h_seq = (( %d ))\n", freg_num,c2h_seq );*/ /*strncpy(debug_trace_11byte,&cmd_buf[1],(cmd_len-1));*/ /*debug_trace_11byte[cmd_len-1] = '\0';*/ - /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] %s\n", debug_trace_11byte));*/ - /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] cmd_len = (( %d ))\n", cmd_len));*/ - /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] c2h_cmd_start = (( %d ))\n", p_dm_odm->c2h_cmd_start));*/ + /*PHYDM_DBG(dm, DBG_FW_TRACE,"[FW debug message] %s\n", debug_trace_11byte);*/ + /*PHYDM_DBG(dm, DBG_FW_TRACE,"[FW debug message] cmd_len = (( %d ))\n", cmd_len);*/ + /*PHYDM_DBG(dm, DBG_FW_TRACE,"[FW debug message] c2h_cmd_start = (( %d ))\n", dm->c2h_cmd_start);*/ - /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("pre_seq = (( %d )), current_seq = (( %d ))\n", p_dm_odm->pre_c2h_seq, c2h_seq));*/ - /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("fw_buff_is_enpty = (( %d ))\n", p_dm_odm->fw_buff_is_enpty));*/ + /*PHYDM_DBG(dm, DBG_FW_TRACE,"pre_seq = (( %d )), current_seq = (( %d ))\n", dm->pre_c2h_seq, c2h_seq);*/ + /*PHYDM_DBG(dm, DBG_FW_TRACE,"fw_buff_is_enpty = (( %d ))\n", dm->fw_buff_is_enpty);*/ - if ((c2h_seq != p_dm_odm->pre_c2h_seq) && p_dm_odm->fw_buff_is_enpty == false) { - p_dm_odm->fw_debug_trace[p_dm_odm->c2h_cmd_start] = '\0'; - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue Overflow] %s\n", p_dm_odm->fw_debug_trace)); - p_dm_odm->c2h_cmd_start = 0; + if ((c2h_seq != dm->pre_c2h_seq) && dm->fw_buff_is_enpty == false) { + dm->fw_debug_trace[dm->c2h_cmd_start] = '\0'; + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW Dbg Queue Overflow] %s\n", dm->fw_debug_trace); + dm->c2h_cmd_start = 0; } - if ((cmd_len - 1) > (60 - p_dm_odm->c2h_cmd_start)) { - p_dm_odm->fw_debug_trace[p_dm_odm->c2h_cmd_start] = '\0'; - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue error: wrong C2H length] %s\n", p_dm_odm->fw_debug_trace)); - p_dm_odm->c2h_cmd_start = 0; + if ((cmd_len - 1) > (60 - dm->c2h_cmd_start)) { + dm->fw_debug_trace[dm->c2h_cmd_start] = '\0'; + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW Dbg Queue error: wrong C2H length] %s\n", dm->fw_debug_trace); + dm->c2h_cmd_start = 0; return; } - strncpy((char *)&(p_dm_odm->fw_debug_trace[p_dm_odm->c2h_cmd_start]), (char *)&cmd_buf[1], (cmd_len - 1)); - p_dm_odm->c2h_cmd_start += (cmd_len - 1); - p_dm_odm->fw_buff_is_enpty = false; + strncpy((char *)&dm->fw_debug_trace[dm->c2h_cmd_start], + (char *)&cmd_buf[1], (cmd_len - 1)); + dm->c2h_cmd_start += (cmd_len - 1); + dm->fw_buff_is_enpty = false; - if (freg_num == 0 || p_dm_odm->c2h_cmd_start >= 60) { - if (p_dm_odm->c2h_cmd_start < 60) - p_dm_odm->fw_debug_trace[p_dm_odm->c2h_cmd_start] = '\0'; + if (freg_num == 0 || dm->c2h_cmd_start >= 60) { + if (dm->c2h_cmd_start < 60) + dm->fw_debug_trace[dm->c2h_cmd_start] = '\0'; else - p_dm_odm->fw_debug_trace[59] = '\0'; + dm->fw_debug_trace[59] = '\0'; - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", p_dm_odm->fw_debug_trace)); - /*dbg_print("[FW DBG Msg] %s\n", p_dm_odm->fw_debug_trace);*/ - p_dm_odm->c2h_cmd_start = 0; - p_dm_odm->fw_buff_is_enpty = true; + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s\n", dm->fw_debug_trace); + /*dbg_print("[FW DBG Msg] %s\n", dm->fw_debug_trace);*/ + dm->c2h_cmd_start = 0; + dm->fw_buff_is_enpty = true; } - p_dm_odm->pre_c2h_seq = c2h_seq; -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ + dm->pre_c2h_seq = c2h_seq; +#endif /*#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ } void phydm_fw_trace_handler_code( - void *p_dm_void, + void *dm_void, u8 *buffer, u8 cmd_len ) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 function = buffer[0]; u8 dbg_num = buffer[1]; u16 content_0 = (((u16)buffer[3]) << 8) | ((u16)buffer[2]); @@ -3137,184 +3589,151 @@ phydm_fw_trace_handler_code( u16 content_4 = (((u16)buffer[11]) << 8) | ((u16)buffer[10]); if (cmd_len > 12) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Msg] Invalid cmd length (( %d )) >12\n", cmd_len)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW Msg] Invalid cmd length (( %d )) >12\n", cmd_len); - /* ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW Msg] Func=((%d)), num=((%d)), ct_0=((%d)), ct_1=((%d)), ct_2=((%d)), ct_3=((%d)), ct_4=((%d))\n", */ - /* function, dbg_num, content_0, content_1, content_2, content_3, content_4)); */ + /* PHYDM_DBG(dm, DBG_FW_TRACE,"[FW Msg] Func=((%d)), num=((%d)), ct_0=((%d)), ct_1=((%d)), ct_2=((%d)), ct_3=((%d)), ct_4=((%d))\n", */ + /* function, dbg_num, content_0, content_1, content_2, content_3, content_4); */ /*--------------------------------------------*/ -#if (CONFIG_RA_FW_DBG_CODE) +#ifdef CONFIG_RA_FW_DBG_CODE if (function == RATE_DECISION) { if (dbg_num == 0) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RA_CNT=((%d)) Max_device=((%d))--------------------------->\n", content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] RA_CNT=((%d)) Max_device=((%d))--------------------------->\n", content_1, content_2); else if (content_0 == 2) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)), try_bit=((0x%x))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)), try_bit=((0x%x))\n", content_1, content_2, content_3, content_4); else if (content_0 == 3) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Check RA total=((%d)), drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] Check RA total=((%d)), drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n", content_1, content_2, content_3, content_4); } else if (dbg_num == 1) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\n", content_1, content_2, content_3, content_4); else if (content_0 == 2) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))", content_1, content_2, content_3, content_4)); - phydm_print_rate(p_dm_odm, (u8)content_4, ODM_FW_DEBUG_TRACE); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))", content_1, content_2, content_3, content_4); + phydm_print_rate(dm, (u8)content_4, DBG_FW_TRACE); } else if (content_0 == 3) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] penality_idx=(( %d ))\n", content_1)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] penality_idx=(( %d ))\n", content_1); else if (content_0 == 4) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RSSI=(( %d )), ra_stage = (( %d ))\n", content_1, content_2)); - } - - else if (dbg_num == 3) { + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] RSSI=(( %d )), ra_stage = (( %d ))\n", content_1, content_2); + } else if (dbg_num == 3) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( DOWN )) total=((%d)), total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] Fast_RA (( DOWN )) total=((%d)), total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4); else if (content_0 == 2) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) total_acc=((%d)), total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] Fast_RA (( UP )) total_acc=((%d)), total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4); else if (content_0 == 3) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) ((rate Down Hold)) RA_CNT=((%d))\n", content_1)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] Fast_RA (( UP )) ((rate Down Hold)) RA_CNT=((%d))\n", content_1); else if (content_0 == 4) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) ((tota_accl<5 skip)) RA_CNT=((%d))\n", content_1)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] Fast_RA (( UP )) ((tota_accl<5 skip)) RA_CNT=((%d))\n", content_1); else if (content_0 == 8) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n", content_1)); - } - - else if (dbg_num == 4) { + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n", content_1); + } else if (dbg_num == 4) { if (content_0 == 3) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RER_CNT PCR_ori =(( %d )), ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] RER_CNT PCR_ori =(( %d )), ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\n", content_1, content_2, content_3, content_4); /**/ } else if (content_0 == 4) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\n", ((content_1) ? "+" : "-"), content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\n", ((content_1) ? "+" : "-"), content_2, content_3, content_4); /**/ } else if (content_0 == 5) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\n", content_1, content_2, content_3, content_4); /**/ } - } - - else if (dbg_num == 5) { + } else if (dbg_num == 5) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] (( UP)) Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] (( UP)) Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\n", content_1, content_2, content_3, content_4); else if (content_0 == 2) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((DOWN)) Nsc=(( %d )), N_Low=(( %d ))\n", content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] ((DOWN)) Nsc=(( %d )), N_Low=(( %d ))\n", content_1, content_2); else if (content_0 == 3) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((HOLD)) Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] ((HOLD)) Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n", content_1, content_2, content_3, content_4); } else if (dbg_num == 0x60) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) macid=((%d)), BUPDATE[macid]=((%d))\n", content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] ((AP RPT)) macid=((%d)), BUPDATE[macid]=((%d))\n", content_1, content_2); else if (content_0 == 4) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] ((AP RPT)) pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n", content_1, content_2, content_3, content_4); else if (content_0 == 5) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW] ((AP RPT)) PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n", content_1, content_2, content_3, content_4); } - } - /*--------------------------------------------*/ - else if (function == INIT_RA_TABLE) { + } else if (function == INIT_RA_TABLE) { if (dbg_num == 3) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n", content_0)); - - } - /*--------------------------------------------*/ - else if (function == RATE_UP) { + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n", content_0); + } else if (function == RATE_UP) { if (dbg_num == 2) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Highest rate->return)), macid=((%d)) Nsc=((%d))\n", content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][RateUp] ((Highest rate->return)), macid=((%d)) Nsc=((%d))\n", content_1, content_2); } else if (dbg_num == 5) { if (content_0 == 0) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)), SGI=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][RateUp] ((rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)), SGI=((%d))\n", content_1, content_2, content_3, content_4); else if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][RateUp] ((rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n", content_1, content_2, content_3, content_4); } - - } - /*--------------------------------------------*/ - else if (function == RATE_DOWN) { + } else if (function == RATE_DOWN) { if (dbg_num == 5) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDownStep] ((rate Down)), macid=((%d)), rate1=((0x%x)), rate2=((0x%x)), BW=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][RateDownStep] ((rate Down)), macid=((%d)), rate1=((0x%x)), rate2=((0x%x)), BW=((%d))\n", content_1, content_2, content_3, content_4); } } else if (function == TRY_DONE) { if (dbg_num == 1) { if (content_0 == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n", content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][Try Done] ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n", content_1, content_2); /**/ } } else if (dbg_num == 2) { if (content_0 == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try)) macid=((%d)), Try_Done_cnt=((%d)), rate_2=((%d)), try_succes=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][Try Done] ((try)) macid=((%d)), Try_Done_cnt=((%d)), rate_2=((%d)), try_succes=((%d))\n", content_1, content_2, content_3, content_4); /**/ } } - } - /*--------------------------------------------*/ - else if (function == RA_H2C) { + } else if (function == RA_H2C) { if (dbg_num == 1) { if (content_0 == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x49] fw_trace_en=((%d)), mode =((%d)), macid=((%d))\n", content_1, content_2, content_3)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][H2C=0x49] fw_trace_en=((%d)), mode =((%d)), macid=((%d))\n", content_1, content_2, content_3); /**/ - /*C2H_RA_Dbg_code(F_RA_H2C,1,0, SysMib.ODM.DEBUG.fw_trace_en, mode, macid, 0); //RA MASK*/ - } -#if 0 - else if (dbg_num == 2) { - - if (content_0 == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] MACID=((%d)), rate ID=((%d)), SGI=((%d)), BW=((%d))\n", content_1, content_2, content_3, content_4)); - /**/ - } else if (content_0 == 2) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] VHT_en=((%d)), Disable_PowerTraining=((%d)), Disable_RA=((%d)), No_Update=((%d))\n", content_1, content_2, content_3, content_4)); - /**/ - } else if (content_0 == 3) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] RA_MSK=[%x | %x | %x | %x ]\n", content_1, content_2, content_3, content_4)); - /**/ - } } -#endif } - } - /*--------------------------------------------*/ - else if (function == F_RATE_AP_RPT) { + } else if (function == F_RATE_AP_RPT) { if (dbg_num == 1) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] ((1)), SPE_STATIS=((0x%x))---------->\n", content_3)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][AP RPT] ((1)), SPE_STATIS=((0x%x))---------->\n", content_3); } else if (dbg_num == 2) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] RTY_all=((%d))\n", content_1)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][AP RPT] RTY_all=((%d))\n", content_1); } else if (dbg_num == 3) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][AP RPT] MACID1[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2); } else if (dbg_num == 4) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][AP RPT] MACID2[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2); } else if (dbg_num == 5) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][AP RPT] MACID1[%d], PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2); } else if (dbg_num == 6) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d],, PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][AP RPT] MACID2[%d],, PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2); } + } else if (function == DBC_FW_CLM) { + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][CLM][%d, %d] = {%d, %d, %d, %d}\n", dbg_num, content_0, content_1, content_2, content_3, content_4); } else { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4)); - /**/ + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4); } #else - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4); #endif /*--------------------------------------------*/ -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +#endif /*#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ } void phydm_fw_trace_handler_8051( - void *p_dm_void, + void *dm_void, u8 *buffer, u8 cmd_len ) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; #if 0 if (cmd_len >= 3) cmd_buf[cmd_len - 1] = '\0'; - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", &(cmd_buf[3]))); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s\n", &(cmd_buf[3])); #else int i = 0; @@ -3349,11 +3768,13 @@ phydm_fw_trace_handler_8051( fw_debug_trace[i] = extend_c2h_dbg_content[i]; if (extend_c2h_dbg_content[i + 1] == '\0') { fw_debug_trace[i + 1] = '\0'; - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW DBG Msg] %s", &fw_debug_trace[0]); break; } else if (extend_c2h_dbg_content[i] == '\n') { fw_debug_trace[i + 1] = '\0'; - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW DBG Msg] %s", &fw_debug_trace[0]); buffer = extend_c2h_dbg_content + i + 3; goto go_backfor_aggre_dbg_pkt; } @@ -3361,5 +3782,5 @@ phydm_fw_trace_handler_8051( #endif -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +#endif /*#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ } diff --git a/hal/phydm/phydm_debug.h b/hal/phydm/phydm_debug.h index 5cd1ecf..67e190e 100644 --- a/hal/phydm/phydm_debug.h +++ b/hal/phydm/phydm_debug.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,18 +8,29 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ - #ifndef __ODM_DBG_H__ #define __ODM_DBG_H__ /*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/ /*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/ -#define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/ +/*#define DEBUG_VERSION "1.3"*/ /*2016.04.28 YuChen*/ +#define DEBUG_VERSION "1.4" /*2017.03.13 Dino*/ + /* ----------------------------------------------------------------------------- * Define the debug levels * @@ -63,13 +74,14 @@ #define ODM_DBG_TRACE 5 /*FW DBG MSG*/ -#define RATE_DECISION BIT(0) -#define INIT_RA_TABLE BIT(1) -#define RATE_UP BIT(2) -#define RATE_DOWN BIT(3) -#define TRY_DONE BIT(4) -#define RA_H2C BIT(5) -#define F_RATE_AP_RPT BIT(7) +#define RATE_DECISION 1 +#define INIT_RA_TABLE 2 +#define RATE_UP 4 +#define RATE_DOWN 8 +#define TRY_DONE 16 +#define RA_H2C 32 +#define F_RATE_AP_RPT 64 +#define DBC_FW_CLM 9 /* ----------------------------------------------------------------------------- * Define the tracing components @@ -79,71 +91,33 @@ #define PHYDM_FW_COMP_RA BIT(0) #define PHYDM_FW_COMP_MU BIT(1) #define PHYDM_FW_COMP_PATH_DIV BIT(2) -#define PHYDM_FW_COMP_PHY_CONFIG BIT(3) - - -/*BB Driver Functions*/ -#define ODM_COMP_DIG BIT(0) -#define ODM_COMP_RA_MASK BIT(1) -#define ODM_COMP_DYNAMIC_TXPWR BIT(2) -#define ODM_COMP_FA_CNT BIT(3) -#define ODM_COMP_RSSI_MONITOR BIT(4) -#define ODM_COMP_SNIFFER BIT(5) -#define ODM_COMP_ANT_DIV BIT(6) -#define ODM_COMP_DFS BIT(7) -#define ODM_COMP_NOISY_DETECT BIT(8) -#define ODM_COMP_RATE_ADAPTIVE BIT(9) -#define ODM_COMP_PATH_DIV BIT(10) -#define ODM_COMP_CCX BIT(11) - -#define ODM_COMP_DYNAMIC_PRICCA BIT(12) -/*BIT13 TBD*/ -#define ODM_COMP_MP BIT(14) -#define ODM_COMP_CFO_TRACKING BIT(15) -#define ODM_COMP_ACS BIT(16) -#define PHYDM_COMP_ADAPTIVITY BIT(17) -#define PHYDM_COMP_RA_DBG BIT(18) -#define PHYDM_COMP_TXBF BIT(19) -/* MAC Functions */ -#define ODM_COMP_EDCA_TURBO BIT(20) -#define ODM_COMP_DYNAMIC_RX_PATH BIT(21) -#define ODM_FW_DEBUG_TRACE BIT(22) -/* RF Functions */ -/*BIT23 TBD*/ -#define ODM_COMP_TX_PWR_TRACK BIT(24) -/*BIT25 TBD*/ -#define ODM_COMP_CALIBRATION BIT(26) -/* Common Functions */ -/*BIT27 TBD*/ -#define ODM_PHY_CONFIG BIT(28) -#define ODM_COMP_INIT BIT(29) -#define ODM_COMP_COMMON BIT(30) -#define ODM_COMP_API BIT(31) - +#define PHYDM_FW_COMP_PT BIT(3) /*------------------------Export Marco Definition---------------------------*/ #define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define dbg_print DbgPrint + extern VOID DCMD_Printf(const char *pMsg); + + #define pr_debug DbgPrint #define dcmd_printf DCMD_Printf #define dcmd_scanf DCMD_Scanf - #define RT_PRINTK dbg_print + #define RT_PRINTK pr_debug + #define PRINT_MAX_SIZE 512 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - #define dbg_print(args...) - #define RT_PRINTK(fmt, args...) \ - RT_TRACE(((struct rtl_priv *)p_dm_odm->adapter), \ - COMP_PHYDM, DBG_DMESG, fmt, ## args) - #define RT_DISP(dbgtype, dbgflag, printstr) + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #define dbg_print printk - #define RT_PRINTK(fmt, args...) dbg_print(fmt, ## args) + #undef pr_debug + #define pr_debug printk + #define RT_PRINTK(fmt, args...) pr_debug(fmt, ## args) #define RT_DISP(dbgtype, dbgflag, printstr) + #define RT_TRACE(adapter, comp, drv_level, fmt, args...) \ + RTW_INFO(fmt, ## args) #else - #define dbg_print panic_printk - /*#define RT_PRINTK(fmt, args...) dbg_print("%s(): " fmt, __FUNCTION__, ## args);*/ - #define RT_PRINTK(args...) dbg_print(args) + #define pr_debug panic_printk + /*#define RT_PRINTK(fmt, args...) pr_debug("%s(): " fmt, __FUNCTION__, ## args);*/ + #define RT_PRINTK(fmt, args...) pr_debug(fmt, ## args) #endif #ifndef ASSERT @@ -151,73 +125,142 @@ #endif #if DBG -#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt) \ - do { \ - if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level || level == ODM_DBG_SERIOUS)) { \ - \ - if (p_dm_odm->support_ic_type == ODM_RTL8188E) \ - dbg_print("[PhyDM-8188E] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8192E) \ - dbg_print("[PhyDM-8192E] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8812) \ - dbg_print("[PhyDM-8812A] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8821) \ - dbg_print("[PhyDM-8821A] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8814A) \ - dbg_print("[PhyDM-8814A] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8703B) \ - dbg_print("[PhyDM-8703B] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) \ - dbg_print("[PhyDM-8822B] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8188F) \ - dbg_print("[PhyDM-8188F] "); \ - RT_PRINTK fmt; \ - } \ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#define PHYDM_DBG(dm, comp, fmt, args...) \ + do { \ + if ((comp) & (dm->debug_components)) { \ + pr_debug("[PHYDM] "); \ + RT_PRINTK(fmt, ## args); \ + } \ } while (0) -#define ODM_RT_TRACE_F(p_dm_odm, comp, level, fmt) do {\ - if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level)) { \ - \ - RT_PRINTK fmt; \ - } \ +#define PHYDM_DBG_F(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->debug_components) { \ + RT_PRINTK(fmt, ## args); \ + } \ } while (0) - -#define ODM_RT_ASSERT(p_dm_odm, expr, fmt) do {\ - if (!(expr)) { \ - dbg_print("Assertion failed! %s at ......\n", #expr); \ - dbg_print(" ......%s,%s, line=%d\n", __FILE__, __FUNCTION__, __LINE__); \ - RT_PRINTK fmt; \ - ASSERT(false); \ - } \ +#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \ + do { \ + if ((comp) & dm->debug_components) { \ + int __i; \ + u8 *__ptr = (u8 *)addr; \ + pr_debug("[PHYDM] "); \ + pr_debug(title_str); \ + pr_debug(" "); \ + for (__i = 0; __i < 6; __i++) \ + pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");\ + pr_debug("\n"); \ + } \ } while (0) +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +static __inline void PHYDM_DBG(PDM_ODM_T dm, int comp, char *fmt, ...) +{ + + RT_STATUS rt_status; + va_list args; + char buf[PRINT_MAX_SIZE] = {0}; + + if ((comp & dm->debug_components) == 0) + return; + + if (fmt == NULL) + return; + + va_start(args, fmt); + rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args); + va_end(args); + + if (rt_status != RT_STATUS_SUCCESS) { + DbgPrint("Failed (%d) to print message to buffer\n", rt_status); + return; + } + + DbgPrint("[PHYDM] %s", buf); +} -#define ODM_dbg_enter() { dbg_print(" == > %s\n", __FUNCTION__); } -#define ODM_dbg_exit() { dbg_print("< == %s\n", __FUNCTION__); } -#define ODM_dbg_trace(str) { dbg_print("%s:%s\n", __FUNCTION__, str); } +static __inline void PHYDM_DBG_F(PDM_ODM_T dm, int comp, char *fmt, ...) +{ -#define ODM_PRINT_ADDR(p_dm_odm, comp, level, title_str, ptr) do {\ - if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level)) { \ + RT_STATUS rt_status; + va_list args; + char buf[PRINT_MAX_SIZE] = {0}; + + if ((comp & dm->debug_components) == 0) + return; + + if (fmt == NULL) + return; + + va_start(args, fmt); + rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args); + va_end(args); + + if (rt_status != RT_STATUS_SUCCESS) { + /*DbgPrint("DM Print Fail\n");*/ + return; + } + + DbgPrint("%s", buf); +} + +#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr) do {\ + if ((comp) & p_dm->debug_components) { \ \ int __i; \ u8 *__ptr = (u8 *)ptr; \ - dbg_print("[ODM] "); \ - dbg_print(title_str); \ - dbg_print(" "); \ + pr_debug("[PHYDM] "); \ + pr_debug(title_str); \ + pr_debug(" "); \ for (__i = 0; __i < 6; __i++) \ - dbg_print("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \ - dbg_print("\n"); \ + pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \ + pr_debug("\n"); \ } \ } while (0) #else -#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt) -#define ODM_RT_TRACE_F(p_dm_odm, comp, level, fmt) -#define ODM_RT_ASSERT(p_dm_odm, expr, fmt) -#define ODM_dbg_enter() -#define ODM_dbg_exit() -#define ODM_dbg_trace(str) -#define ODM_PRINT_ADDR(p_dm_odm, comp, level, title_str, ptr) +#define PHYDM_DBG(dm, comp, fmt, args...) \ + do { \ + if ((comp) & (dm->debug_components)) { \ + RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \ + DBG_DMESG, "[PHYDM] " fmt, ##args); \ + } \ + } while (0) + +#define PHYDM_DBG_F(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->debug_components) { \ + RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \ + DBG_DMESG, fmt, ##args); \ + } \ + } while (0) + +#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \ + do { \ + if ((comp) & dm->debug_components) { \ + RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \ + DBG_DMESG, "[PHYDM] " title_str "%pM\n", \ + addr); \ + } \ + } while (0) +#endif + +#define ODM_RT_TRACE(dm, comp, level, fmt) + +#else +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +static __inline void PHYDM_DBG(struct dm_struct *dm, int comp, char *fmt, ...) +{} +static __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...) +{} +#else +#define PHYDM_DBG(dm, comp, fmt) +#define PHYDM_DBG_F(dm, comp, fmt) +#endif +#define PHYDM_PRINT_ADDR(dm, comp, title_str, ptr) +#define ODM_RT_TRACE(dm, comp, level, fmt) #endif #define BB_DBGPORT_PRIORITY_3 3 /*Debug function (the highest priority)*/ @@ -225,57 +268,46 @@ #define BB_DBGPORT_PRIORITY_1 1 /*Watch dog function*/ #define BB_DBGPORT_RELEASE 0 /*Init value (the lowest priority)*/ -void -phydm_init_debug_setting(struct PHY_DM_STRUCT *p_dm_odm); - -void -phydm_bb_dbg_port_header_sel( - void *p_dm_void, - u32 header_idx -); - -u8 -phydm_set_bb_dbg_port( - void *p_dm_void, - u8 curr_dbg_priority, - u32 debug_port -); - -void -phydm_release_bb_dbg_port( - void *p_dm_void -); - -u32 -phydm_get_bb_dbg_port_value( - void *p_dm_void -); - -void phydm_basic_dbg_message(void *p_dm_void); - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #define PHYDM_DBGPRINT 0 #define PHYDM_SSCANF(x, y, z) dcmd_scanf(x, y, z) -#define PHYDM_VAST_INFO_SNPRINTF PHYDM_SNPRINTF +#define PHYDM_VAST_INFO_SNPRINTF PDM_SNPF #if (PHYDM_DBGPRINT == 1) -#define PHYDM_SNPRINTF(msg) \ +#define PDM_SNPF(msg) \ do {\ rsprintf msg;\ - dbg_print(output);\ + pr_debug("%s", output);\ } while (0) #else -#define PHYDM_SNPRINTF(msg) \ - do {\ - rsprintf msg;\ - dcmd_printf(output);\ - } while (0) -#endif -#else -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__) + +static __inline void PDM_SNPF(u32 out_len, u32 used, char * buff, int len, char *fmt, ...) +{ + RT_STATUS rt_status; + va_list args; + char buf[PRINT_MAX_SIZE] = {0}; + + if (fmt == NULL) + return; + + va_start(args, fmt); + rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args); + va_end(args); + + if (rt_status != RT_STATUS_SUCCESS) { + /*DbgPrint("DM Print Fail\n");*/ + return; + } + + DCMD_Printf(buf); +} + +#endif /*#if (PHYDM_DBGPRINT == 1)*/ +#else /*(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/ + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__) #define PHYDM_DBGPRINT 0 -#else + #else #define PHYDM_DBGPRINT 1 -#endif + #endif #define MAX_ARGC 20 #define MAX_ARGV 16 #define DCMD_DECIMAL "%d" @@ -284,105 +316,77 @@ void phydm_basic_dbg_message(void *p_dm_void); #define PHYDM_SSCANF(x, y, z) sscanf(x, y, z) -#define PHYDM_VAST_INFO_SNPRINTF(msg)\ - do {\ - snprintf msg;\ - dbg_print(output);\ +#define PHYDM_VAST_INFO_SNPRINTF(out_len, used, buff, len, fmt, args...) \ + do { \ + RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \ + DBG_DMESG, fmt, ##args); \ } while (0) #if (PHYDM_DBGPRINT == 1) -#define PHYDM_SNPRINTF(msg)\ - do {\ - snprintf msg;\ - dbg_print(output);\ +#define PDM_SNPF(out_len, used, buff, len, fmt, args...) \ + do { \ + snprintf(buff, len, fmt, ##args); \ + pr_debug("%s", output); \ } while (0) #else -#define PHYDM_SNPRINTF(msg)\ - do {\ - if (out_len > used)\ - used += snprintf msg;\ +#define PDM_SNPF(out_len, used, buff, len, fmt, args...) \ + do { \ + if (out_len > used) \ + used += snprintf(buff, len, fmt, ##args); \ } while (0) #endif #endif +void phydm_init_debug_setting(struct dm_struct *dm); -void phydm_basic_profile( - void *p_dm_void, - u32 *_used, - char *output, - u32 *_out_len -); +void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx); + +u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port); + +void phydm_release_bb_dbg_port(void *dm_void); + +u32 phydm_get_bb_dbg_port_value(void *dm_void); + +void phydm_reset_rx_rate_distribution(struct dm_struct *dm); + +void phydm_rx_rate_distribution(void *dm_void); + +void phydm_get_avg_phystatus_val(void *dm_void); + +void phydm_get_phy_statistic(void *dm_void); + +void phydm_basic_dbg_message(void *dm_void); + +void phydm_basic_profile(void *dm_void, u32 *_used, char *output, + u32 *_out_len); #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) -s32 -phydm_cmd( - struct PHY_DM_STRUCT *p_dm_odm, - char *input, - u32 in_len, - u8 flag, - char *output, - u32 out_len -); +s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag, + char *output, u32 out_len); #endif -void -phydm_cmd_parser( - struct PHY_DM_STRUCT *p_dm_odm, - char input[][16], - u32 input_num, - u8 flag, - char *output, - u32 out_len -); - -boolean -phydm_api_trx_mode( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_path_e tx_path, - enum odm_rf_path_e rx_path, - boolean is_tx2_path -); +void phydm_cmd_parser(struct dm_struct *dm, char input[][16], u32 input_num, + u8 flag, char *output, u32 out_len); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void phydm_sbd_check( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); void phydm_sbd_callback( - struct timer_list *p_timer + struct phydm_timer_list *timer ); void phydm_sbd_workitem_callback( - void *p_context + void *context ); #endif -void -phydm_fw_trace_en_h2c( - void *p_dm_void, - boolean enable, - u32 fw_debug_component, - u32 monitor_mode, - u32 macid -); +void phydm_fw_trace_en_h2c(void *dm_void, boolean enable, + u32 fw_debug_component, u32 monitor_mode, u32 macid); -void -phydm_fw_trace_handler( - void *p_dm_void, - u8 *cmd_buf, - u8 cmd_len -); +void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); -void -phydm_fw_trace_handler_code( - void *p_dm_void, - u8 *buffer, - u8 cmd_len -); +void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len); -void -phydm_fw_trace_handler_8051( - void *p_dm_void, - u8 *cmd_buf, - u8 cmd_len -); +void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len); #endif /* __ODM_DBG_H__ */ diff --git a/hal/phydm/phydm_dfs.c b/hal/phydm/phydm_dfs.c index 297f973..2ca538d 100644 --- a/hal/phydm/phydm_dfs.c +++ b/hal/phydm/phydm_dfs.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* @@ -23,247 +33,657 @@ #include "phydm_precomp.h" #if defined(CONFIG_PHYDM_DFS_MASTER) -void phydm_radar_detect_reset(void *p_dm_void) + +boolean phydm_dfs_is_meteorology_channel(void *dm_void){ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + u8 c_channel = *dm->channel; + u8 band_width = *dm->band_width; + + return ( (band_width == CHANNEL_WIDTH_80 && (c_channel) >= 116 && (c_channel) <= 128) || + (band_width == CHANNEL_WIDTH_40 && (c_channel) >= 116 && (c_channel) <= 128) || + (band_width == CHANNEL_WIDTH_20 && (c_channel) >= 120 && (c_channel) <= 128) ); +} + +void phydm_radar_detect_reset(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 0); - odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 1); + odm_set_bb_reg(dm, 0x924, BIT(15), 0); + odm_set_bb_reg(dm, 0x924, BIT(15), 1); } -void phydm_radar_detect_disable(void *p_dm_void) +void phydm_radar_detect_disable(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 0); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("\n")); + odm_set_bb_reg(dm, 0x924, BIT(15), 0); + PHYDM_DBG(dm, DBG_DFS, "\n"); } -static void phydm_radar_detect_with_dbg_parm(void *p_dm_void) +static void phydm_radar_detect_with_dbg_parm(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, p_dm_odm->radar_detect_reg_918); - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, p_dm_odm->radar_detect_reg_91c); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, p_dm_odm->radar_detect_reg_920); - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, p_dm_odm->radar_detect_reg_924); + odm_set_bb_reg(dm, 0x918, MASKDWORD, dm->radar_detect_reg_918); + odm_set_bb_reg(dm, 0x91c, MASKDWORD, dm->radar_detect_reg_91c); + odm_set_bb_reg(dm, 0x920, MASKDWORD, dm->radar_detect_reg_920); + odm_set_bb_reg(dm, 0x924, MASKDWORD, dm->radar_detect_reg_924); } /* Init radar detection parameters, called after ch, bw is set */ -void phydm_radar_detect_enable(void *p_dm_void) +void phydm_radar_detect_enable(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 region_domain = p_dm_odm->dfs_region_domain; - u8 c_channel = *(p_dm_odm->p_channel); - u8 band_width = *(p_dm_odm->p_band_width); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = (struct _DFS_STATISTICS *)phydm_get_structure(dm, PHYDM_DFS); + u8 region_domain = dm->dfs_region_domain; + u8 c_channel = *dm->channel; + u8 band_width = *dm->band_width; u8 enable = 0; + PHYDM_DBG(dm, DBG_DFS, "test, region_domain = %d\n", region_domain); if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n")); + PHYDM_DBG(dm, DBG_DFS, "PHYDM_DFS_DOMAIN_UNKNOWN\n"); goto exit; } - if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) { + if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) { + odm_set_bb_reg(dm, 0x814, 0x3fffffff, 0x04cc4d10); + odm_set_bb_reg(dm, 0x834, MASKBYTE0, 0x06); - odm_set_bb_reg(p_dm_odm, 0x814, 0x3fffffff, 0x04cc4d10); - odm_set_bb_reg(p_dm_odm, 0x834, MASKBYTE0, 0x06); - - if (p_dm_odm->radar_detect_dbg_parm_en) { - phydm_radar_detect_with_dbg_parm(p_dm_odm); + if (dm->radar_detect_dbg_parm_en) { + phydm_radar_detect_with_dbg_parm(dm); enable = 1; goto exit; } if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c17ecdf); - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x01528500); - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0fa21a20); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0f69204); + odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c17ecdf); + odm_set_bb_reg(dm, 0x924, MASKDWORD, 0x01528500); + odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x0fa21a20); + odm_set_bb_reg(dm, 0x920, MASKDWORD, 0xe0f69204); } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) { - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x01528500); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67234); + odm_set_bb_reg(dm, 0x924, MASKDWORD, 0x01528500); + odm_set_bb_reg(dm, 0x920, MASKDWORD, 0xe0d67234); if (c_channel >= 52 && c_channel <= 64) { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16ecdf); - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0f141a20); + odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c16ecdf); + odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x0f141a20); } else { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16acdf); - if (band_width == ODM_BW20M) - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64721a20); + odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c16acdf); + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x64721a20); else - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68721a20); + odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x68721a20); } } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16acdf); - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x01528500); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67231); - if (band_width == ODM_BW20M) - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64741a20); + odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c16acdf); + odm_set_bb_reg(dm, 0x924, MASKDWORD, 0x01528500); + odm_set_bb_reg(dm, 0x920, MASKDWORD, 0xe0d67231); + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x64741a20); else - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68741a20); + odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x68741a20); } else { /* not supported */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported dfs_region_domain:%d\n", region_domain)); + PHYDM_DBG(dm, DBG_DFS, "Unsupported dfs_region_domain:%d\n", region_domain); goto exit; } - } else if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) { - - odm_set_bb_reg(p_dm_odm, 0x814, 0x3fffffff, 0x04cc4d10); - odm_set_bb_reg(p_dm_odm, 0x834, MASKBYTE0, 0x06); + } else if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) { + odm_set_bb_reg(dm, 0x814, 0x3fffffff, 0x04cc4d10); + odm_set_bb_reg(dm, 0x834, MASKBYTE0, 0x06); /* 8822B only, when BW = 20M, DFIR output is 40Mhz, but DFS input is 80MMHz, so it need to upgrade to 80MHz */ - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { - if (band_width == ODM_BW20M) - odm_set_bb_reg(p_dm_odm, 0x1984, BIT(26), 1); + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, 0x1984, BIT(26), 1); else - odm_set_bb_reg(p_dm_odm, 0x1984, BIT(26), 0); + odm_set_bb_reg(dm, 0x1984, BIT(26), 0); } - if (p_dm_odm->radar_detect_dbg_parm_en) { - phydm_radar_detect_with_dbg_parm(p_dm_odm); + if (dm->radar_detect_dbg_parm_en) { + phydm_radar_detect_with_dbg_parm(dm); enable = 1; goto exit; } if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16acdf); - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x095a8500); - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0fa21a20); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0f57204); + odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c16acdf); + odm_set_bb_reg(dm, 0x924, MASKDWORD, 0x095a8500); + odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x0fa21a20); + odm_set_bb_reg(dm, 0x920, MASKDWORD, 0xe0f57204); } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) { - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x095a8500); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67234); + odm_set_bb_reg(dm, 0x924, MASKDWORD, 0x095a8500); + odm_set_bb_reg(dm, 0x920, MASKDWORD, 0xe0d67234); if (c_channel >= 52 && c_channel <= 64) { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16ecdf); - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0f141a20); + odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c16ecdf); + odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x0f141a20); } else { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c166cdf); - if (band_width == ODM_BW20M) - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64721a20); + odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c166cdf); + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x64721a20); else - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68721a20); + odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x68721a20); } } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c166cdf); - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x095a8500); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67231); - if (band_width == ODM_BW20M) - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64741a20); + odm_set_bb_reg(dm, 0x918, MASKDWORD, 0x1c166cdf); + odm_set_bb_reg(dm, 0x924, MASKDWORD, 0x095a8500); + odm_set_bb_reg(dm, 0x920, MASKDWORD, 0xe0d67231); + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x64741a20); else - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68741a20); + odm_set_bb_reg(dm, 0x91c, MASKDWORD, 0x68741a20); } else { /* not supported */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported dfs_region_domain:%d\n", region_domain)); + PHYDM_DBG(dm, DBG_DFS, "Unsupported dfs_region_domain:%d\n", region_domain); goto exit; } } else { /* not supported IC type*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported IC type:%d\n", p_dm_odm->support_ic_type)); + PHYDM_DBG(dm, DBG_DFS, "Unsupported IC type:%d\n", dm->support_ic_type); goto exit; } enable = 1; + dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, 0x91c, 0x000000ff); + dfs->pwdb_th = (u8)odm_get_bb_reg(dm, 0x918, 0x00001f00); + dfs->peak_th = (u8)odm_get_bb_reg(dm, 0x918, 0x00030000); + dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, 0x920, 0x000f0000); + dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, 0x920, 0x00f00000); + dfs->peak_window = (u8)odm_get_bb_reg(dm, 0x920, 0x00000300); + dfs->nb2wb_th = (u8)odm_get_bb_reg(dm, 0x920, 0x0000e000); + + phydm_dfs_parameter_init(dm); + exit: if (enable) { - phydm_radar_detect_reset(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("on cch:%u, bw:%u\n", c_channel, band_width)); + phydm_radar_detect_reset(dm); + PHYDM_DBG(dm, DBG_DFS, "on cch:%u, bw:%u\n", c_channel, band_width); } else - phydm_radar_detect_disable(p_dm_odm); + phydm_radar_detect_disable(dm); } -boolean phydm_radar_detect(void *p_dm_void) +void phydm_dfs_parameter_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - boolean enable_DFS = false; - boolean radar_detected = false; - u8 region_domain = p_dm_odm->dfs_region_domain; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = (struct _DFS_STATISTICS *)phydm_get_structure(dm, PHYDM_DFS); + + u8 i; + + dfs->fa_mask_th = 30; + dfs->det_print = 1; + dfs->det_print2 = 0; + dfs->st_l2h_min = 0x20; + dfs->st_l2h_max = 0x4e; + dfs->pwdb_scalar_factor = 12; + dfs->pwdb_th = 8; + for (i = 0 ; i < 5 ; i++) { + dfs->pulse_flag_hist[i] = 0; + dfs->radar_det_mask_hist[i] = 0; + dfs->fa_inc_hist[i] = 0; + } - if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n")); - return false; +} + +void phydm_dfs_dynamic_setting( + void *dm_void +){ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = (struct _DFS_STATISTICS *)phydm_get_structure(dm, PHYDM_DFS); + + u8 peak_th_cur=0, short_pulse_cnt_th_cur=0, long_pulse_cnt_th_cur=0, three_peak_opt_cur=0, three_peak_th2_cur=0; + u8 peak_window_cur=0, nb2wb_th_cur=0; + u8 region_domain = dm->dfs_region_domain; + u8 c_channel = *dm->channel; + + if (dm->rx_tp <= 2) { + dfs->idle_mode = 1; + if(dfs->force_TP_mode) + dfs->idle_mode = 0; + } else{ + dfs->idle_mode = 0; } - if (odm_get_bb_reg(p_dm_odm, 0x924, BIT(15))) - enable_DFS = true; + if ((dfs->idle_mode == 1)) { /*idle (no traffic)*/ + peak_th_cur = 3; + short_pulse_cnt_th_cur = 6; + long_pulse_cnt_th_cur = 13; + peak_window_cur = 2; + nb2wb_th_cur = 6; + three_peak_opt_cur = 1; + three_peak_th2_cur = 2; + if (region_domain == PHYDM_DFS_DOMAIN_MKK) { + if ((c_channel >= 52) && (c_channel <= 64)) { + short_pulse_cnt_th_cur = 14; + long_pulse_cnt_th_cur = 15; + nb2wb_th_cur = 3; + three_peak_th2_cur = 0; + } else { + short_pulse_cnt_th_cur = 6; + nb2wb_th_cur = 3; + three_peak_th2_cur = 0; + long_pulse_cnt_th_cur = 10; + } + } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { + three_peak_th2_cur = 0; + } else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { + long_pulse_cnt_th_cur = 15; + if (phydm_dfs_is_meteorology_channel(dm)) {/*need to add check cac end condition*/ + peak_th_cur = 2; + nb2wb_th_cur = 3; + three_peak_opt_cur = 1; + three_peak_th2_cur = 0; + short_pulse_cnt_th_cur = 7; + } else { + three_peak_opt_cur = 1; + three_peak_th2_cur = 0; + short_pulse_cnt_th_cur = 7; + nb2wb_th_cur = 3; + } + } else /*default: FCC*/ + three_peak_th2_cur = 0; + + } else { /*in service (with TP)*/ + peak_th_cur = 2; + short_pulse_cnt_th_cur = 6; + long_pulse_cnt_th_cur = 9; + peak_window_cur = 2; + nb2wb_th_cur = 3; + three_peak_opt_cur = 1; + three_peak_th2_cur = 2; + if(region_domain == PHYDM_DFS_DOMAIN_MKK){ + if ((c_channel >= 52) && (c_channel <= 64)) { + long_pulse_cnt_th_cur = 15; + short_pulse_cnt_th_cur = 5; /*for high duty cycle*/ + three_peak_th2_cur = 0; + } + else { + three_peak_opt_cur = 0; + three_peak_th2_cur = 0; + long_pulse_cnt_th_cur = 8; + } + } + else if(region_domain == PHYDM_DFS_DOMAIN_FCC){ + } + else if(region_domain == PHYDM_DFS_DOMAIN_ETSI){ + long_pulse_cnt_th_cur = 15; + short_pulse_cnt_th_cur = 5; + three_peak_opt_cur = 0; + } + } - if ((odm_get_bb_reg(p_dm_odm, 0xf98, BIT(17))) - || (!(region_domain == PHYDM_DFS_DOMAIN_ETSI) && (odm_get_bb_reg(p_dm_odm, 0xf98, BIT(19))))) - radar_detected = true; +} - if (enable_DFS && radar_detected) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD - , ("Radar detect: enable_DFS:%d, radar_detected:%d\n" - , enable_DFS, radar_detected)); - phydm_radar_detect_reset(p_dm_odm); +boolean +phydm_radar_detect_dm_check( + void *dm_void +){ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = (struct _DFS_STATISTICS *)phydm_get_structure(dm, PHYDM_DFS); + u8 region_domain = dm->dfs_region_domain, index = 0; + + u16 i = 0, k = 0, fa_count_cur = 0, fa_count_inc = 0, total_fa_in_hist = 0, pre_post_now_acc_fa_in_hist = 0, max_fa_in_hist = 0, vht_crc_ok_cnt_cur = 0; + u16 vht_crc_ok_cnt_inc = 0, ht_crc_ok_cnt_cur = 0, ht_crc_ok_cnt_inc = 0, leg_crc_ok_cnt_cur = 0, leg_crc_ok_cnt_inc = 0; + u16 total_crc_ok_cnt_inc = 0, short_pulse_cnt_cur = 0, short_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0, long_pulse_cnt_inc = 0, total_pulse_count_inc = 0; + u32 regf98_value = 0, reg918_value = 0, reg91c_value = 0, reg920_value = 0, reg924_value = 0; + boolean tri_short_pulse = 0, tri_long_pulse = 0, radar_type = 0, fault_flag_det = 0, fault_flag_psd = 0, fa_flag = 0, radar_detected = 0; + u8 st_l2h_new = 0, fa_mask_th = 0, sum = 0; + u8 c_channel = *dm->channel; + + /*Get FA count during past 100ms*/ + fa_count_cur = (u16)odm_get_bb_reg(dm, 0xf48, 0x0000ffff); + + if (dfs->fa_count_pre == 0) + fa_count_inc = 0; + else if (fa_count_cur >= dfs->fa_count_pre) + fa_count_inc = fa_count_cur - dfs->fa_count_pre; + else + fa_count_inc = fa_count_cur; + dfs->fa_count_pre = fa_count_cur; + + dfs->fa_inc_hist[dfs->mask_idx] = fa_count_inc; + + for (i=0; i<5; i++) { + total_fa_in_hist = total_fa_in_hist + dfs->fa_inc_hist[i]; + if (dfs->fa_inc_hist[i] > max_fa_in_hist) + max_fa_in_hist = dfs->fa_inc_hist[i]; + } + if (dfs->mask_idx >= 2) + index = dfs->mask_idx - 2; + else + index = 5 + dfs->mask_idx - 2; + if (index == 0) + pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] + dfs->fa_inc_hist[index+1] + dfs->fa_inc_hist[4]; + else if (index == 4) + pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] + dfs->fa_inc_hist[0] + dfs->fa_inc_hist[index-1]; + else + pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] + dfs->fa_inc_hist[index+1] + dfs->fa_inc_hist[index-1]; + + /*Get VHT CRC32 ok count during past 100ms*/ + vht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, 0xf0c, 0x00003fff); + if (vht_crc_ok_cnt_cur >= dfs->vht_crc_ok_cnt_pre) + vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur - dfs->vht_crc_ok_cnt_pre; + else + vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur; + dfs->vht_crc_ok_cnt_pre = vht_crc_ok_cnt_cur; + + /*Get HT CRC32 ok count during past 100ms*/ + ht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, 0xf10, 0x00003fff); + if (ht_crc_ok_cnt_cur >= dfs->ht_crc_ok_cnt_pre) + ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur - dfs->ht_crc_ok_cnt_pre; + else + ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur; + dfs->ht_crc_ok_cnt_pre = ht_crc_ok_cnt_cur; + + /*Get Legacy CRC32 ok count during past 100ms*/ + leg_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, 0xf14, 0x00003fff); + if (leg_crc_ok_cnt_cur >= dfs->leg_crc_ok_cnt_pre) + leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur - dfs->leg_crc_ok_cnt_pre; + else + leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur; + dfs->leg_crc_ok_cnt_pre = leg_crc_ok_cnt_cur; + + if ((vht_crc_ok_cnt_cur == 0x3fff) || + (ht_crc_ok_cnt_cur == 0x3fff) || + (leg_crc_ok_cnt_cur == 0x3fff)) { + odm_set_bb_reg(dm, 0xb58, BIT(0), 1); + odm_set_bb_reg(dm, 0xb58, BIT(0), 0); } -exit: - return enable_DFS && radar_detected; + total_crc_ok_cnt_inc = vht_crc_ok_cnt_inc + ht_crc_ok_cnt_inc + leg_crc_ok_cnt_inc; + + /*Get short pulse count, need carefully handle the counter overflow*/ + regf98_value = odm_get_bb_reg(dm, 0xf98, 0xffffffff); + short_pulse_cnt_cur = (u16)(regf98_value & 0x000000ff); + if (short_pulse_cnt_cur >= dfs->short_pulse_cnt_pre) + short_pulse_cnt_inc = short_pulse_cnt_cur - dfs->short_pulse_cnt_pre; + else + short_pulse_cnt_inc = short_pulse_cnt_cur; + dfs->short_pulse_cnt_pre = short_pulse_cnt_cur; + + /*Get long pulse count, need carefully handle the counter overflow*/ + long_pulse_cnt_cur = (u16)((regf98_value & 0x0000ff00) >> 8); + if (long_pulse_cnt_cur >= dfs->long_pulse_cnt_pre) + long_pulse_cnt_inc = long_pulse_cnt_cur - dfs->long_pulse_cnt_pre; + else + long_pulse_cnt_inc = long_pulse_cnt_cur; + dfs->long_pulse_cnt_pre = long_pulse_cnt_cur; + + total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc; + + if (dfs->det_print){ + PHYDM_DBG(dm, DBG_DFS, "=====================================================================\n"); + PHYDM_DBG(dm, DBG_DFS, "Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d]\n", + total_crc_ok_cnt_inc, vht_crc_ok_cnt_inc, ht_crc_ok_cnt_inc, leg_crc_ok_cnt_inc, fa_count_inc); + PHYDM_DBG(dm, DBG_DFS, "Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n", + dfs->igi_cur, dfs->st_l2h_cur, regf98_value, short_pulse_cnt_inc, long_pulse_cnt_inc); + PHYDM_DBG(dm, DBG_DFS, "Throughput: %dMbps\n", dm->rx_tp); + reg918_value = odm_get_bb_reg(dm, 0x918, 0xffffffff); + reg91c_value = odm_get_bb_reg(dm, 0x91c, 0xffffffff); + reg920_value = odm_get_bb_reg(dm, 0x920, 0xffffffff); + reg924_value = odm_get_bb_reg(dm, 0x924, 0xffffffff); + PHYDM_DBG(dm, DBG_DFS, "0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n", reg918_value, reg91c_value, reg920_value, reg924_value); + PHYDM_DBG(dm, DBG_DFS, "dfs_regdomain = %d, dbg_mode = %d, idle_mode = %d\n", region_domain, dfs->dbg_mode, dfs->idle_mode); + } + tri_short_pulse = (regf98_value & BIT(17))? 1 : 0; + tri_long_pulse = (regf98_value & BIT(19))? 1 : 0; + + if(tri_short_pulse) + radar_type = 0; + else if(tri_long_pulse) + radar_type = 1; + + if (tri_short_pulse) { + odm_set_bb_reg(dm, 0x924, BIT(15), 0); + odm_set_bb_reg(dm, 0x924, BIT(15), 1); + } + if (tri_long_pulse) { + odm_set_bb_reg(dm, 0x924, BIT(15), 0); + odm_set_bb_reg(dm, 0x924, BIT(15), 1); + if (region_domain == PHYDM_DFS_DOMAIN_MKK) { + if ((c_channel >= 52) && (c_channel <= 64)) { + tri_long_pulse = 0; + } + } + if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { + tri_long_pulse = 0; + } + } + + st_l2h_new = dfs->st_l2h_cur; + dfs->pulse_flag_hist[dfs->mask_idx] = tri_short_pulse | tri_long_pulse; + + /* PSD(not ready) */ + + fault_flag_det = 0; + fault_flag_psd = 0; + fa_flag = 0; + if(region_domain == PHYDM_DFS_DOMAIN_ETSI){ + fa_mask_th = dfs->fa_mask_th + 20; + } + else{ + fa_mask_th = dfs->fa_mask_th; + } + if (max_fa_in_hist >= fa_mask_th || total_fa_in_hist >= fa_mask_th || pre_post_now_acc_fa_in_hist >= fa_mask_th || (dfs->igi_cur >= 0x30)){ + st_l2h_new = dfs->st_l2h_max; + dfs->radar_det_mask_hist[index] = 1; + if (dfs->pulse_flag_hist[index] == 1){ + dfs->pulse_flag_hist[index] = 0; + if (dfs->det_print2){ + PHYDM_DBG(dm, DBG_DFS, "Radar is masked : FA mask\n"); + } + } + fa_flag = 1; + } else { + dfs->radar_det_mask_hist[index] = 0; + } + + if (dfs->det_print) { + PHYDM_DBG(dm, DBG_DFS, "mask_idx: %d\n", dfs->mask_idx); + PHYDM_DBG(dm, DBG_DFS, "radar_det_mask_hist: "); + for (i=0; i<5; i++) + PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->radar_det_mask_hist[i]); + PHYDM_DBG(dm, DBG_DFS, "pulse_flag_hist: "); + for (i=0; i<5; i++) + PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->pulse_flag_hist[i]); + PHYDM_DBG(dm, DBG_DFS, "fa_inc_hist: "); + for (i=0; i<5; i++) + PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->fa_inc_hist[i]); + PHYDM_DBG(dm, DBG_DFS, + "\nfa_mask_th: %d max_fa_in_hist: %d total_fa_in_hist: %d pre_post_now_acc_fa_in_hist: %d ", fa_mask_th, max_fa_in_hist, total_fa_in_hist, pre_post_now_acc_fa_in_hist); + } + + sum = 0; + for (k=0; k<5; k++) { + if (dfs->radar_det_mask_hist[k] == 1) + sum++; + } + + if (dfs->mask_hist_checked <= 5) + dfs->mask_hist_checked++; + + if ((dfs->mask_hist_checked >= 5) && dfs->pulse_flag_hist[index]) + { + if (sum <= 2) + { + radar_detected = 1 ; + PHYDM_DBG(dm, DBG_DFS, "Detected type %d radar signal!\n", radar_type); + } + else { + fault_flag_det = 1; + if (dfs->det_print2){ + PHYDM_DBG(dm, DBG_DFS, "Radar is masked : mask_hist large than thd\n"); + } + } + } + + dfs->mask_idx++; + if (dfs->mask_idx == 5) + dfs->mask_idx = 0; + + if ((fault_flag_det == 0) && (fault_flag_psd == 0) && (fa_flag ==0)) { + if (dfs->igi_cur < 0x30) { + st_l2h_new = dfs->st_l2h_min; + } + } + + if ((st_l2h_new != dfs->st_l2h_cur)) { + if (st_l2h_new < dfs->st_l2h_min) { + dfs->st_l2h_cur = dfs->st_l2h_min; + } + else if (st_l2h_new > dfs->st_l2h_max) + dfs->st_l2h_cur = dfs->st_l2h_max; + else + dfs->st_l2h_cur = st_l2h_new; + odm_set_bb_reg(dm, 0x91c, 0xff, dfs->st_l2h_cur); + + dfs->pwdb_th = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)/2 + dfs->pwdb_scalar_factor; + dfs->pwdb_th = MAX_2(dfs->pwdb_th, (int)dfs->pwdb_th); /*limit the pwdb value to absoulte lower bound 8*/ + dfs->pwdb_th = MIN_2(dfs->pwdb_th, 0x1f); /*limit the pwdb value to absoulte upper bound 0x1f*/ + odm_set_bb_reg(dm, 0x918, 0x00001f00, dfs->pwdb_th); + } + + if (dfs->det_print) { + PHYDM_DBG(dm, DBG_DFS, + "fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n", fault_flag_det, fault_flag_psd, radar_detected); + } + + return radar_detected; + } -#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ -boolean -phydm_dfs_master_enabled( - void *p_dm_void -) +boolean phydm_radar_detect(void *dm_void) { -#ifdef CONFIG_PHYDM_DFS_MASTER - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = (struct _DFS_STATISTICS *)phydm_get_structure(dm, PHYDM_DFS); + boolean enable_DFS = false; + boolean radar_detected = false; - return *p_dm_odm->dfs_master_enabled ? true : false; -#else - return false; -#endif + dfs->igi_cur = (u8)odm_get_bb_reg(dm, 0xc50, 0x0000007f); + + dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, 0x91c, 0x000000ff); + + /* dynamic pwdb calibration */ + if (dfs->igi_pre != dfs->igi_cur) { + dfs->pwdb_th = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)/2 + dfs->pwdb_scalar_factor; + dfs->pwdb_th = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th); /* limit the pwdb value to absoulte lower bound 0xa */ + dfs->pwdb_th = MIN_2(dfs->pwdb_th_cur, 0x1f); /* limit the pwdb value to absoulte upper bound 0x1f */ + odm_set_bb_reg(dm, 0x918, 0x00001f00, dfs->pwdb_th); + } + + dfs->igi_pre = dfs->igi_cur; + + phydm_dfs_dynamic_setting(dm); + radar_detected = phydm_radar_detect_dm_check(dm); + + if (odm_get_bb_reg(dm, 0x924, BIT(15))) + enable_DFS = true; + + if (enable_DFS && radar_detected) { + PHYDM_DBG(dm, DBG_DFS, "Radar detect: enable_DFS:%d, radar_detected:%d\n", enable_DFS, radar_detected); + phydm_radar_detect_reset(dm); + if (dfs->dbg_mode == 1){ + PHYDM_DBG(dm, DBG_DFS, "Radar is detected in DFS dbg mode.\n"); + radar_detected = 0; + } + } + + return enable_DFS && radar_detected; } + void phydm_dfs_debug( - void *p_dm_void, + void *dm_void, u32 *const argv, u32 *_used, char *output, u32 *_out_len ) { -#if defined(CONFIG_PHYDM_DFS_MASTER) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = (struct _DFS_STATISTICS *)phydm_get_structure(dm, PHYDM_DFS); u32 used = *_used; u32 out_len = *_out_len; - switch (argv[0]) { + dfs->dbg_mode = (boolean)argv[0]; + dfs->force_TP_mode = (boolean)argv[1]; + dfs->det_print = (boolean)argv[2]; + dfs->det_print2 = (boolean)argv[3]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "dbg_mode: %d, force_TP_mode: %d, det_print: %d, det_print2: %d\n", + dfs->dbg_mode, dfs->force_TP_mode, dfs->det_print, + dfs->det_print2); + + /*switch (argv[0]) { case 1: - /* set dbg parameters for radar detection instead of the default value */ +#if defined(CONFIG_PHYDM_DFS_MASTER) + set dbg parameters for radar detection instead of the default value if (argv[1] == 1) { - p_dm_odm->radar_detect_reg_918 = argv[2]; - p_dm_odm->radar_detect_reg_91c = argv[3]; - p_dm_odm->radar_detect_reg_920 = argv[4]; - p_dm_odm->radar_detect_reg_924 = argv[5]; - p_dm_odm->radar_detect_dbg_parm_en = 1; - - PHYDM_SNPRINTF((output + used, out_len - used, "Radar detection with dbg parameter\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "reg918:0x%08X\n", p_dm_odm->radar_detect_reg_918)); - PHYDM_SNPRINTF((output + used, out_len - used, "reg91c:0x%08X\n", p_dm_odm->radar_detect_reg_91c)); - PHYDM_SNPRINTF((output + used, out_len - used, "reg920:0x%08X\n", p_dm_odm->radar_detect_reg_920)); - PHYDM_SNPRINTF((output + used, out_len - used, "reg924:0x%08X\n", p_dm_odm->radar_detect_reg_924)); + dm->radar_detect_reg_918 = argv[2]; + dm->radar_detect_reg_91c = argv[3]; + dm->radar_detect_reg_920 = argv[4]; + dm->radar_detect_reg_924 = argv[5]; + dm->radar_detect_dbg_parm_en = 1; + + PDM_SNPF((output + used, out_len - used, "Radar detection with dbg parameter\n")); + PDM_SNPF((output + used, out_len - used, "reg918:0x%08X\n", dm->radar_detect_reg_918)); + PDM_SNPF((output + used, out_len - used, "reg91c:0x%08X\n", dm->radar_detect_reg_91c)); + PDM_SNPF((output + used, out_len - used, "reg920:0x%08X\n", dm->radar_detect_reg_920)); + PDM_SNPF((output + used, out_len - used, "reg924:0x%08X\n", dm->radar_detect_reg_924)); } else { - p_dm_odm->radar_detect_dbg_parm_en = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "Radar detection with default parameter\n")); + dm->radar_detect_dbg_parm_en = 0; + PDM_SNPF((output + used, out_len - used, "Radar detection with default parameter\n")); } - phydm_radar_detect_enable(p_dm_odm); + phydm_radar_detect_enable(dm); +#endif defined(CONFIG_PHYDM_DFS_MASTER) break; default: break; - } + }*/ +} + + + #endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ + +boolean +phydm_is_dfs_band( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (((*dm->channel >= 52) && (*dm->channel <= 64)) || + ((*dm->channel >= 100) && (*dm->channel <= 140))) + return true; + else + return false; } + +boolean +phydm_dfs_master_enabled( + void *dm_void +) +{ +#ifdef CONFIG_PHYDM_DFS_MASTER + struct dm_struct *dm = (struct dm_struct *)dm_void; + + return *dm->dfs_master_enabled ? true : false; +#else + return false; +#endif +} + diff --git a/hal/phydm/phydm_dfs.h b/hal/phydm/phydm_dfs.h index 6856e25..c46da12 100644 --- a/hal/phydm/phydm_dfs.h +++ b/hal/phydm/phydm_dfs.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,25 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __PHYDM_DFS_H__ #define __PHYDM_DFS_H__ -#define DFS_VERSION "0.0" +#define DFS_VERSION "1.1" /* ============================================================ Definition @@ -29,6 +39,41 @@ ============================================================ */ +struct _DFS_STATISTICS { + u8 mask_idx; + u8 igi_cur; + u8 igi_pre; + u8 st_l2h_cur; + u16 fa_count_pre; + u16 fa_inc_hist[5]; + u16 vht_crc_ok_cnt_pre; + u16 ht_crc_ok_cnt_pre; + u16 leg_crc_ok_cnt_pre; + u16 short_pulse_cnt_pre; + u16 long_pulse_cnt_pre; + u8 pwdb_th; + u8 pwdb_th_cur; + u8 pwdb_scalar_factor; + u8 peak_th; + u8 short_pulse_cnt_th; + u8 long_pulse_cnt_th; + u8 peak_window; + u8 nb2wb_th; + u8 fa_mask_th; + u8 det_flag_offset; + u8 st_l2h_max; + u8 st_l2h_min; + u8 mask_hist_checked; + boolean pulse_flag_hist[5]; + boolean radar_det_mask_hist[5]; + boolean idle_mode; + boolean force_TP_mode; + boolean dbg_mode; + boolean det_print; + boolean det_print2; +}; + + /* ============================================================ enumeration ============================================================ @@ -47,24 +92,27 @@ enum phydm_dfs_region_domain { ============================================================ */ #if defined(CONFIG_PHYDM_DFS_MASTER) - void phydm_radar_detect_reset(void *p_dm_void); - void phydm_radar_detect_disable(void *p_dm_void); - void phydm_radar_detect_enable(void *p_dm_void); - boolean phydm_radar_detect(void *p_dm_void); +void phydm_radar_detect_reset(void *dm_void); +void phydm_radar_detect_disable(void *dm_void); +void phydm_radar_detect_enable(void *dm_void); +boolean phydm_radar_detect(void *dm_void); +void phydm_dfs_parameter_init(void *dm_void); +void phydm_dfs_debug(void *dm_void, u32 *const argv, u32 *_used, char *output, u32 *_out_len); #endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ +boolean +phydm_dfs_is_meteorology_channel( + void *dm_void +); + boolean -phydm_dfs_master_enabled( - void *p_dm_void +phydm_is_dfs_band( + void *dm_void ); -void -phydm_dfs_debug( - void *p_dm_void, - u32 *const argv, - u32 *_used, - char *output, - u32 *_out_len +boolean +phydm_dfs_master_enabled( + void *dm_void ); #endif /*#ifndef __PHYDM_DFS_H__ */ diff --git a/hal/phydm/phydm_dig.c b/hal/phydm/phydm_dig.c index ccaae50..25786fc 100644 --- a/hal/phydm/phydm_dig.c +++ b/hal/phydm/phydm_dig.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -20,1432 +30,1016 @@ #include "phydm_precomp.h" -void -odm_change_dynamic_init_gain_thresh( - void *p_dm_void, - u32 dm_type, - u32 dm_value -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - - if (dm_type == DIG_TYPE_THRESH_HIGH) - p_dm_dig_table->rssi_high_thresh = dm_value; - else if (dm_type == DIG_TYPE_THRESH_LOW) - p_dm_dig_table->rssi_low_thresh = dm_value; - else if (dm_type == DIG_TYPE_ENABLE) - p_dm_dig_table->dig_enable_flag = true; - else if (dm_type == DIG_TYPE_DISABLE) - p_dm_dig_table->dig_enable_flag = false; - else if (dm_type == DIG_TYPE_BACKOFF) { - if (dm_value > 30) - dm_value = 30; - p_dm_dig_table->backoff_val = (u8)dm_value; - } else if (dm_type == DIG_TYPE_RX_GAIN_MIN) { - if (dm_value == 0) - dm_value = 0x1; - p_dm_dig_table->rx_gain_range_min = (u8)dm_value; - } else if (dm_type == DIG_TYPE_RX_GAIN_MAX) { - if (dm_value > 0x50) - dm_value = 0x50; - p_dm_dig_table->rx_gain_range_max = (u8)dm_value; - } -} /* dm_change_dynamic_init_gain_thresh */ - -int -get_igi_for_diff(int value_IGI) -{ -#define ONERCCA_LOW_TH 0x30 -#define ONERCCA_LOW_DIFF 8 - - if (value_IGI < ONERCCA_LOW_TH) { - if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) - return ONERCCA_LOW_TH; - else - return value_IGI + ONERCCA_LOW_DIFF; - } else - return value_IGI; -} - -void -odm_fa_threshold_check( - void *p_dm_void, - boolean is_dfs_band, - boolean is_performance, - u32 rx_tp, - u32 tx_tp, - u32 *dm_FA_thres -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (p_dm_odm->is_linked && (is_performance || is_dfs_band)) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - /*For AP*/ -#if (DIG_HW == 1) - dm_FA_thres[0] = p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_th1; - dm_FA_thres[1] = p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_th2; - dm_FA_thres[2] = p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_th3; -#else - if ((rx_tp >> 2) > tx_tp && rx_tp < 10000 && rx_tp > 500) { /*10Mbps & 0.5Mbps*/ - dm_FA_thres[0] = 0x080; - dm_FA_thres[1] = 0x100; - dm_FA_thres[2] = 0x200; - } else { - dm_FA_thres[0] = 0x100; - dm_FA_thres[1] = 0x200; - dm_FA_thres[2] = 0x300; - } -#endif -#else - /*For NIC*/ - dm_FA_thres[0] = DM_DIG_FA_TH0; - dm_FA_thres[1] = DM_DIG_FA_TH1; - dm_FA_thres[2] = DM_DIG_FA_TH2; -#endif - } else { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - if (is_dfs_band) { - /* For DFS band and no link */ - dm_FA_thres[0] = 250; - dm_FA_thres[1] = 1000; - dm_FA_thres[2] = 2000; - } else -#endif - { - dm_FA_thres[0] = 2000; - dm_FA_thres[1] = 4000; - dm_FA_thres[2] = 5000; - } - } - return; -} - -u8 -odm_forbidden_igi_check( - void *p_dm_void, - u8 dig_dynamic_min, - u8 current_igi +boolean +phydm_dig_go_up_check( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - u8 rx_gain_range_min = p_dm_dig_table->rx_gain_range_min; - - if (p_dm_dig_table->large_fa_timeout) { - if (--p_dm_dig_table->large_fa_timeout == 0) - p_dm_dig_table->large_fa_hit = 0; - } - - if (p_false_alm_cnt->cnt_all > 10000) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case.\n")); - - if (p_dm_dig_table->large_fa_hit != 3) - p_dm_dig_table->large_fa_hit++; - - if (p_dm_dig_table->forbidden_igi < current_igi) { /* if(p_dm_dig_table->forbidden_igi < p_dm_dig_table->cur_ig_value) */ - p_dm_dig_table->forbidden_igi = current_igi;/* p_dm_dig_table->forbidden_igi = p_dm_dig_table->cur_ig_value; */ - p_dm_dig_table->large_fa_hit = 1; - p_dm_dig_table->large_fa_timeout = LARGE_FA_TIMEOUT; - } - - if (p_dm_dig_table->large_fa_hit >= 3) { - if ((p_dm_dig_table->forbidden_igi + 2) > p_dm_dig_table->rx_gain_range_max) - rx_gain_range_min = p_dm_dig_table->rx_gain_range_max; - else - rx_gain_range_min = (p_dm_dig_table->forbidden_igi + 2); - p_dm_dig_table->recover_cnt = 1800; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case: recover_cnt = %d\n", p_dm_dig_table->recover_cnt)); - } - } - - else if (p_false_alm_cnt->cnt_all > 2000) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnormally false alarm case.\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("cnt_all=%d, cnt_all_pre=%d, current_igi=0x%x, pre_ig_value=0x%x\n", - p_false_alm_cnt->cnt_all, p_false_alm_cnt->cnt_all_pre, current_igi, p_dm_dig_table->pre_ig_value)); - - /* p_false_alm_cnt->cnt_all = 1.1875*p_false_alm_cnt->cnt_all_pre */ - if ((p_false_alm_cnt->cnt_all > (p_false_alm_cnt->cnt_all_pre + (p_false_alm_cnt->cnt_all_pre >> 3) + (p_false_alm_cnt->cnt_all_pre >> 4))) && (current_igi < p_dm_dig_table->pre_ig_value)) { - if (p_dm_dig_table->large_fa_hit != 3) - p_dm_dig_table->large_fa_hit++; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 cur_ig_value = dig_t->cur_ig_value; + u8 max_cover_bond; + u8 rx_gain_range_max = dig_t->rx_gain_range_max; + u8 i = 0, j = 0; + u8 total_nhm_cnt = ccx_info->nhm_rpt_sum; + u32 dig_cover_cnt = 0; + u32 over_dig_cover_cnt = 0; + boolean ret = true; + + if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) + return ret; + + max_cover_bond = DIG_MAX_BALANCE_MODE - dig_t->dig_upcheck_initial_value; + + if (cur_ig_value < max_cover_bond - 6) + dig_t->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_0; + else if (cur_ig_value <= DIG_MAX_BALANCE_MODE) + dig_t->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_1; + else /* cur_ig_value > DM_DIG_MAX_AP, foolproof */ + dig_t->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_2; + - if (p_dm_dig_table->forbidden_igi < current_igi) { /*if(p_dm_dig_table->forbidden_igi < p_dm_dig_table->cur_ig_value)*/ + PHYDM_DBG(dm, DBG_DIG, "check_lv = %d, max_cover_bond = 0x%x\n", + dig_t->dig_go_up_check_level, + max_cover_bond); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Updating forbidden_igi by current_igi, forbidden_igi=0x%x, current_igi=0x%x\n", - p_dm_dig_table->forbidden_igi, current_igi)); + if (total_nhm_cnt == 0) + return true; - p_dm_dig_table->forbidden_igi = current_igi; /*p_dm_dig_table->forbidden_igi = p_dm_dig_table->cur_ig_value;*/ - p_dm_dig_table->large_fa_hit = 1; - p_dm_dig_table->large_fa_timeout = LARGE_FA_TIMEOUT; + if (dig_t->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_0) { + for (i = 3; i<=11; i++) + dig_cover_cnt += ccx_info->nhm_result[i]; + ret = ((dig_t->dig_level0_ratio_reciprocal * dig_cover_cnt) >= total_nhm_cnt) ? true : false; + } else if (dig_t->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_1) { + + /* search index */ + for (i = 0; i<=10; i++) { + if ((max_cover_bond * 2) == ccx_info->nhm_th[i]) { + for(j =(i+1); j <= 11; j++) + over_dig_cover_cnt += ccx_info->nhm_result[j]; + break; } - - } - - if (p_dm_dig_table->large_fa_hit >= 3) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("FaHit is greater than 3, rx_gain_range_max=0x%x, rx_gain_range_min=0x%x, forbidden_igi=0x%x\n", - p_dm_dig_table->rx_gain_range_max, rx_gain_range_min, p_dm_dig_table->forbidden_igi)); - - if ((p_dm_dig_table->forbidden_igi + 1) > p_dm_dig_table->rx_gain_range_max) - rx_gain_range_min = p_dm_dig_table->rx_gain_range_max; - else - rx_gain_range_min = (p_dm_dig_table->forbidden_igi + 1); - - p_dm_dig_table->recover_cnt = 1200; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnormally false alarm case: recover_cnt = %d, rx_gain_range_min = 0x%x\n", p_dm_dig_table->recover_cnt, rx_gain_range_min)); } - } + ret = (dig_t->dig_level1_ratio_reciprocal * over_dig_cover_cnt < total_nhm_cnt) ? true : false; - else { - if (p_dm_dig_table->recover_cnt != 0) { + if (!ret) { + /* update dig_t->rx_gain_range_max */ + dig_t->rx_gain_range_max = (rx_gain_range_max >= max_cover_bond - 6) ? (max_cover_bond - 6) : rx_gain_range_max; - p_dm_dig_table->recover_cnt--; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: recover_cnt = %d\n", p_dm_dig_table->recover_cnt)); - } else { - if (p_dm_dig_table->large_fa_hit < 3) { - if ((p_dm_dig_table->forbidden_igi - 2) < dig_dynamic_min) { /* DM_DIG_MIN) */ - p_dm_dig_table->forbidden_igi = dig_dynamic_min; /* DM_DIG_MIN; */ - rx_gain_range_min = dig_dynamic_min; /* DM_DIG_MIN; */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); - } else { - if (p_dm_dig_table->large_fa_hit == 0) { - p_dm_dig_table->forbidden_igi -= 2; - rx_gain_range_min = (p_dm_dig_table->forbidden_igi + 2); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); - } - } - } else - p_dm_dig_table->large_fa_hit = 0; + PHYDM_DBG(dm, DBG_DIG, + "Noise pwr over DIG can filter, lock rx_gain_range_max to 0x%x\n", + dig_t->rx_gain_range_max); } + } else if (dig_t->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_2) { + /* cur_ig_value > DM_DIG_MAX_AP, foolproof */ + ret = true; } - return rx_gain_range_min; - + return ret; } void -odm_inband_noise_calculate( - void *p_dm_void +odm_fa_threshold_check( + void *dm_void, + boolean is_dfs_band, + boolean is_performance ) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 igi_backup, time_cnt = 0, valid_cnt = 0; - boolean is_timeout = true; - s8 s_noise_a, s_noise_b; - s32 noise_rpt_a = 0, noise_rpt_b = 0; - u32 tmp = 0; - static u8 fail_cnt = 0; - - if (!(p_dm_odm->support_ic_type & (ODM_RTL8192E))) - return; - - if (p_dm_odm->rf_type == ODM_1T1R || *(p_dm_odm->p_one_path_cca) != ODM_CCA_2R) - return; - - if (!p_dm_dig_table->is_noise_est) - return; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_InbandNoiseEstimate()========>\n")); - - /* 1 Set initial gain. */ - igi_backup = p_dm_dig_table->cur_ig_value; - p_dm_dig_table->igi_offset_a = 0; - p_dm_dig_table->igi_offset_b = 0; - odm_write_dig(p_dm_odm, 0x24); - - /* 1 Update idle time power report */ - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - odm_set_bb_reg(p_dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT(25), 0x0); - - delay_ms(2); - - /* 1 Get noise power level */ - while (1) { - /* 2 Read Noise Floor Report */ - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - tmp = odm_get_bb_reg(p_dm_odm, 0x8f8, MASKLWORD); - - s_noise_a = (s8)(tmp & 0xff); - s_noise_b = (s8)((tmp & 0xff00) >> 8); - - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("s_noise_a = %d, s_noise_b = %d\n",s_noise_a, s_noise_b)); */ - - if ((s_noise_a < 20 && s_noise_a >= -70) && (s_noise_b < 20 && s_noise_b >= -70)) { - valid_cnt++; - noise_rpt_a += s_noise_a; - noise_rpt_b += s_noise_b; - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("s_noise_a = %d, s_noise_b = %d\n",s_noise_a, s_noise_b)); */ - } + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; - time_cnt++; - is_timeout = (time_cnt >= 150) ? true : false; - - if (valid_cnt == 20 || is_timeout) - break; - - delay_ms(2); - - } - - /* 1 Keep idle time power report */ - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - odm_set_bb_reg(p_dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT(25), 0x1); - - /* 1 Recover IGI */ - odm_write_dig(p_dm_odm, igi_backup); - - /* 1 Calculate Noise Floor */ - if (valid_cnt != 0) { - noise_rpt_a /= (valid_cnt << 1); - noise_rpt_b /= (valid_cnt << 1); - } - - if (is_timeout) { - noise_rpt_a = 0; - noise_rpt_b = 0; - - fail_cnt++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Noise estimate fail time = %d\n", fail_cnt)); - - if (fail_cnt == 3) { - fail_cnt = 0; - p_dm_dig_table->is_noise_est = false; + if (dig_t->is_dbg_fa_th) { + + PHYDM_DBG(dm, DBG_DIG, "Manual Fix FA_th\n"); + + } else if (dm->is_linked && (is_performance || is_dfs_band)) { + if (dm->rssi_min < 20) { /*[PHYDM-252]*/ + dig_t->fa_th[0] = 500; + dig_t->fa_th[1] = 750; + dig_t->fa_th[2] = 1000; + } else if (((dm->rx_tp >> 2) > dm->tx_tp) && /*Test RX TP*/ + (dm->rx_tp < 10) && (dm->rx_tp > 1)) { /*RXTP = 1 ~ 10Mbps*/ + dig_t->fa_th[0] = 125; + dig_t->fa_th[1] = 250; + dig_t->fa_th[2] = 500; + } else { + dig_t->fa_th[0] = 250; + dig_t->fa_th[1] = 500; + dig_t->fa_th[2] = 750; } } else { - noise_rpt_a = -110 + 0x24 + noise_rpt_a - 6; - noise_rpt_b = -110 + 0x24 + noise_rpt_b - 6; - p_dm_dig_table->is_noise_est = false; - fail_cnt = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("noise_rpt_a = %d, noise_rpt_b = %d\n", noise_rpt_a, noise_rpt_b)); - } - - /* 1 Calculate IGI Offset */ - if (noise_rpt_a > noise_rpt_b) { - p_dm_dig_table->igi_offset_a = noise_rpt_a - noise_rpt_b; - p_dm_dig_table->igi_offset_b = 0; - } else { - p_dm_dig_table->igi_offset_a = 0; - p_dm_dig_table->igi_offset_b = noise_rpt_b - noise_rpt_a; + if (is_dfs_band) { /* For DFS band and no link */ + + dig_t->fa_th[0] = 250; + dig_t->fa_th[1] = 1000; + dig_t->fa_th[2] = 2000; + } else { + dig_t->fa_th[0] = 2000; + dig_t->fa_th[1] = 4000; + dig_t->fa_th[2] = 5000; + } } -#endif - return; -} - -void -odm_dig_for_bt_hs_mode( - void *p_dm_void -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 dig_for_bt_hs = 0; - u8 dig_up_bound = 0x5a; + PHYDM_DBG(dm, DBG_DIG, "FA_th={%d,%d,%d}\n", + dig_t->fa_th[0], dig_t->fa_th[1], dig_t->fa_th[2]); - if (p_dm_odm->is_bt_connect_process) - dig_for_bt_hs = 0x22; - else { - /* */ - /* Decide DIG value by BT HS RSSI. */ - /* */ - dig_for_bt_hs = p_dm_odm->bt_hs_rssi + 4; - - /* DIG Bound */ - if (dig_for_bt_hs > dig_up_bound) - dig_for_bt_hs = dig_up_bound; - if (dig_for_bt_hs < 0x1c) - dig_for_bt_hs = 0x1c; - - /* update Current IGI */ - p_dm_dig_table->bt30_cur_igi = dig_for_bt_hs; - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_for_bt_hs_mode() : set DigValue=0x%x\n", dig_for_bt_hs)); -#endif } void phydm_set_big_jump_step( - void *p_dm_void, + void *dm_void, u8 current_igi ) { #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90}; - u8 i; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90}; + u8 i; - if (p_dm_dig_table->enable_adjust_big_jump == 0) + if (dig_t->enable_adjust_big_jump == 0) return; - for (i = 0; i <= p_dm_dig_table->big_jump_step1; i++) { - if ((current_igi + step1[i]) > p_dm_dig_table->big_jump_lmt[p_dm_dig_table->agc_table_idx]) { + for (i = 0; i <= dig_t->big_jump_step1; i++) { + if ((current_igi + step1[i]) > dig_t->big_jump_lmt[dig_t->agc_table_idx]) { if (i != 0) i = i - 1; break; - } else if (i == p_dm_dig_table->big_jump_step1) + } else if (i == dig_t->big_jump_step1) break; } - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - odm_set_bb_reg(p_dm_odm, 0x8c8, 0xe, i); - else if (p_dm_odm->support_ic_type & ODM_RTL8197F) - odm_set_bb_reg(p_dm_odm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i); + if (dm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(dm, 0x8c8, 0xe, i); + else if (dm->support_ic_type & ODM_RTL8197F) + odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_set_big_jump_step(): bigjump = %d (ori = 0x%x), LMT=0x%x\n", i, p_dm_dig_table->big_jump_step1, p_dm_dig_table->big_jump_lmt[p_dm_dig_table->agc_table_idx])); + PHYDM_DBG(dm, DBG_DIG, + "phydm_set_big_jump_step(): bigjump = %d (ori = 0x%x), LMT=0x%x\n", + i, dig_t->big_jump_step1, dig_t->big_jump_lmt[dig_t->agc_table_idx]); #endif } void odm_write_dig( - void *p_dm_void, + void *dm_void, u8 current_igi ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - - if (p_dm_dig_table->is_stop_dig) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_write_dig(): Stop Writing IGI\n")); - return; - } + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("odm_write_dig(): ODM_REG(IGI_A,p_dm_odm)=0x%x, ODM_BIT(IGI,p_dm_odm)=0x%x\n", - ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm))); + PHYDM_DBG(dm, DBG_DIG, "odm_write_dig===>\n"); - /* 1 Check initial gain by upper bound */ - if ((!p_dm_dig_table->is_psd_in_progress) && p_dm_odm->is_linked) { - if (current_igi > p_dm_dig_table->rx_gain_range_max) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("odm_write_dig(): current_igi(0x%02x) is larger than upper bound !!\n", current_igi)); - current_igi = p_dm_dig_table->rx_gain_range_max; - } - if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY && p_dm_odm->adaptivity_flag == true) { - if (current_igi > p_dm_odm->adaptivity_igi_upper) - current_igi = p_dm_odm->adaptivity_igi_upper; + /* 1 Check IGI by upper bound */ + if (adaptivity->igi_lmt_en && + (current_igi > adaptivity->adapt_igi_up) && dm->is_linked) { + + current_igi = adaptivity->adapt_igi_up; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_write_dig(): adaptivity case: Force upper bound to 0x%x !!!!!!\n", current_igi)); - } + PHYDM_DBG(dm, DBG_DIG, + "Force to Adaptivity Upper bound=((0x%x))\n", current_igi); } - if (p_dm_dig_table->cur_ig_value != current_igi) { - -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + if (dig_t->cur_ig_value != current_igi) { + #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) /* Modify big jump step for 8822B and 8197F */ - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) - phydm_set_big_jump_step(p_dm_odm, current_igi); -#endif + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) + phydm_set_big_jump_step(dm, current_igi); + #endif -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) /* Set IGI value of CCK for new CCK AGC */ - if (p_dm_odm->cck_new_agc) { - if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) - odm_set_bb_reg(p_dm_odm, 0xa0c, 0x00003f00, (current_igi >> 1)); - } -#endif + if (dm->cck_new_agc && (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)) + odm_set_bb_reg(dm, 0xa0c, 0x3f00, (current_igi >> 1)); + #endif /*Add by YuChen for USB IO too slow issue*/ - if ((p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) && (current_igi > p_dm_dig_table->cur_ig_value)) { - p_dm_dig_table->cur_ig_value = current_igi; - phydm_adaptivity(p_dm_odm); + if (dm->support_ic_type & + (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { + if ((dm->support_ability & ODM_BB_ADAPTIVITY) && + (current_igi < dig_t->cur_ig_value)) { + dig_t->cur_ig_value = current_igi; + phydm_adaptivity(dm); + } + } else { + if ((dm->support_ability & ODM_BB_ADAPTIVITY) && + (current_igi > dig_t->cur_ig_value)) { + dig_t->cur_ig_value = current_igi; + phydm_adaptivity(dm); + } } - /* 1 Set IGI value */ - if (p_dm_odm->support_platform & (ODM_WIN | ODM_CE)) { - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + /* Set IGI value */ + odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), current_igi); - if (p_dm_odm->rf_type > ODM_1T1R) - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) + odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), current_igi); + #endif -#if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) { - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_C, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_D, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - } -#endif - } else if (p_dm_odm->support_platform & (ODM_AP)) { - switch (*(p_dm_odm->p_one_path_cca)) { - case ODM_CCA_2R: - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - - if (p_dm_odm->rf_type > ODM_1T1R) - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); -#if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) { - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_C, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_D, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - } -#endif - break; - case ODM_CCA_1R_A: - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - if (p_dm_odm->rf_type != ODM_1T1R) - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), get_igi_for_diff(current_igi)); - break; - case ODM_CCA_1R_B: - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), get_igi_for_diff(current_igi)); - if (p_dm_odm->rf_type != ODM_1T1R) - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - break; - } + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + odm_set_bb_reg(dm, ODM_REG(IGI_C, dm), ODM_BIT(IGI, dm), current_igi); + odm_set_bb_reg(dm, ODM_REG(IGI_D, dm), ODM_BIT(IGI, dm), current_igi); } - - p_dm_dig_table->cur_ig_value = current_igi; + #endif + + dig_t->cur_ig_value = current_igi; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("odm_write_dig(): current_igi(0x%02x).\n", current_igi)); - + PHYDM_DBG(dm, DBG_DIG, "New_igi=((0x%x))\n\n", current_igi); } void -odm_pause_dig( - void *p_dm_void, - enum phydm_pause_type pause_type, - enum phydm_pause_level pause_level, - u8 igi_value +phydm_set_dig_val( + void *dm_void, + u32 *val_buf, + u8 val_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig()=========> level = %d\n", pause_level)); - - if ((p_dm_dig_table->pause_dig_level == 0) && (!(p_dm_odm->support_ability & ODM_BB_DIG) || !(p_dm_odm->support_ability & ODM_BB_FA_CNT))) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_pause_dig(): Return: support_ability DIG or FA is disabled !!\n")); + if (val_len != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[Error][DIG]Need val_len=1\n"); return; } + + odm_write_dig(dm, (u8)(*val_buf)); +} - if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_pause_dig(): Return: Wrong pause level !!\n")); - return; - } +void +odm_pause_dig( + void *dm_void, + enum phydm_pause_type type, + enum phydm_pause_level lv, + u8 igi_input +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rpt = false; + u32 igi = (u32)igi_input; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_dig_level, igi_value)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - p_dm_dig_table->pause_dig_value[7], p_dm_dig_table->pause_dig_value[6], p_dm_dig_table->pause_dig_value[5], p_dm_dig_table->pause_dig_value[4], - p_dm_dig_table->pause_dig_value[3], p_dm_dig_table->pause_dig_value[2], p_dm_dig_table->pause_dig_value[1], p_dm_dig_table->pause_dig_value[0])); + PHYDM_DBG(dm, DBG_DIG, "[%s]type = %s, LV = %d, igi = 0x%x\n", + __func__, + ((type == PHYDM_PAUSE) ? "Pause" : ((type == PHYDM_RESUME) ? "Resume" : "PauseNoSet")), + lv, igi); - switch (pause_type) { - /* Pause DIG */ + switch (type) { + case PHYDM_PAUSE: + case PHYDM_PAUSE_NO_SET: { - /* Disable DIG */ - p_dm_odm->support_ability &= ~ODM_BB_DIG; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Pause DIG !!\n")); - - /* Backup IGI value */ - if (p_dm_dig_table->pause_dig_level == 0) { - p_dm_dig_table->igi_backup = p_dm_dig_table->cur_ig_value; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Backup IGI = 0x%x, new IGI = 0x%x\n", p_dm_dig_table->igi_backup, igi_value)); - } - - /* Record IGI value */ - p_dm_dig_table->pause_dig_value[pause_level] = igi_value; - - /* Update pause level */ - p_dm_dig_table->pause_dig_level = (p_dm_dig_table->pause_dig_level | BIT(pause_level)); - - /* Write new IGI value */ - if (BIT(pause_level + 1) > p_dm_dig_table->pause_dig_level) { - odm_write_dig(p_dm_odm, igi_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): IGI of higher level = 0x%x\n", igi_value)); - } + rpt = phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, lv, 1, &igi); break; } - /* Resume DIG */ + case PHYDM_RESUME: { - /* check if the level is illegal or not */ - if ((p_dm_dig_table->pause_dig_level & (BIT(pause_level))) != 0) { - p_dm_dig_table->pause_dig_level = p_dm_dig_table->pause_dig_level & (~(BIT(pause_level))); - p_dm_dig_table->pause_dig_value[pause_level] = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Resume DIG !!\n")); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Wrong resume level !!\n")); - break; - } - - /* Resume DIG */ - if (p_dm_dig_table->pause_dig_level == 0) { - /* Write backup IGI value */ - odm_write_dig(p_dm_odm, p_dm_dig_table->igi_backup); - p_dm_dig_table->is_ignore_dig = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Write original IGI = 0x%x\n", p_dm_dig_table->igi_backup)); - - /* Enable DIG */ - p_dm_odm->support_ability |= ODM_BB_DIG; - break; - } - - if (BIT(pause_level) > p_dm_dig_table->pause_dig_level) { - s8 max_level; - - /* Calculate the maximum level now */ - for (max_level = (pause_level - 1); max_level >= 0; max_level--) { - if ((p_dm_dig_table->pause_dig_level & BIT(max_level)) > 0) - break; - } - - /* write IGI of lower level */ - odm_write_dig(p_dm_odm, p_dm_dig_table->pause_dig_value[max_level]); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Write IGI (0x%x) of level (%d)\n", - p_dm_dig_table->pause_dig_value[max_level], max_level)); - break; - } + rpt = phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, lv, 1, &igi); break; } default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Wrong type !!\n")); + PHYDM_DBG(dm, DBG_DIG, "Wrong type\n"); break; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_dig_level, igi_value)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - p_dm_dig_table->pause_dig_value[7], p_dm_dig_table->pause_dig_value[6], p_dm_dig_table->pause_dig_value[5], p_dm_dig_table->pause_dig_value[4], - p_dm_dig_table->pause_dig_value[3], p_dm_dig_table->pause_dig_value[2], p_dm_dig_table->pause_dig_value[1], p_dm_dig_table->pause_dig_value[0])); - + PHYDM_DBG(dm, DBG_DIG, "pause_result=%d\n", rpt); } + boolean odm_dig_abort( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; -#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *p_adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; #endif /* support_ability */ - if (!(p_dm_odm->support_ability & ODM_BB_FA_CNT)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: support_ability ODM_BB_FA_CNT is disabled\n")); - return true; - } - - /* support_ability */ - if (!(p_dm_odm->support_ability & ODM_BB_DIG)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: support_ability ODM_BB_DIG is disabled\n")); - return true; + if ((!(dm->support_ability & ODM_BB_FA_CNT)) || + (!(dm->support_ability & ODM_BB_DIG)) || + *dm->is_scan_in_process) { + PHYDM_DBG(dm, DBG_DIG, "Not Support\n"); + return true; } - /* ScanInProcess */ - if (*(p_dm_odm->p_is_scan_in_process)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: In Scan Progress\n")); - return true; - } - - if (p_dm_dig_table->is_ignore_dig) { - p_dm_dig_table->is_ignore_dig = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Ignore DIG\n")); - return true; + if (dm->pause_ability & ODM_BB_DIG) { + + PHYDM_DBG(dm, DBG_DIG, "Return: Pause DIG in LV=%d\n", dm->pause_lv_table.lv_dig); + return true; } - - /* add by Neil Chen to avoid PSD is processing */ - if (p_dm_odm->is_dm_initial_gain_enable == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: PSD is Processing\n")); - return true; + + if (dig_t->is_ignore_dig) { + dig_t->is_ignore_dig = false; + PHYDM_DBG(dm, DBG_DIG, "Return: Ignore DIG\n"); + return true; } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #if OS_WIN_FROM_WIN7(OS_VERSION) - if (IsAPModeExist(p_adapter) && p_adapter->bInHctTest) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Is AP mode or In HCT Test\n")); - return true; + if (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) { + PHYDM_DBG(dm, DBG_DIG, " Return: Is AP mode or In HCT Test\n"); + return true; } #endif - - if (p_dm_odm->is_bt_hs_operation) - odm_dig_for_bt_hs_mode(p_dm_odm); - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - if ((p_dm_odm->is_linked) && (p_dm_odm->adapter->registrypriv.force_igi != 0)) { - printk("p_dm_odm->rssi_min=%d\n", p_dm_odm->rssi_min); - odm_write_dig(p_dm_odm, p_dm_odm->adapter->registrypriv.force_igi); - return true; - } -#endif -#else - if (!(priv->up_time > 5)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Not In DIG operation period\n")); - return true; - } #endif - return false; + return false; } void -odm_dig_init( - void *p_dm_void +phydm_dig_init( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT); #endif - u32 ret_value; - u8 i; - - p_dm_dig_table->is_stop_dig = false; - p_dm_dig_table->is_ignore_dig = false; - p_dm_dig_table->is_psd_in_progress = false; - p_dm_dig_table->cur_ig_value = (u8) odm_get_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm)); - p_dm_dig_table->pre_ig_value = 0; - p_dm_dig_table->rssi_low_thresh = DM_DIG_THRESH_LOW; - p_dm_dig_table->rssi_high_thresh = DM_DIG_THRESH_HIGH; - p_dm_dig_table->fa_low_thresh = DM_FALSEALARM_THRESH_LOW; - p_dm_dig_table->fa_high_thresh = DM_FALSEALARM_THRESH_HIGH; - p_dm_dig_table->backoff_val = DM_DIG_BACKOFF_DEFAULT; - p_dm_dig_table->backoff_val_range_max = DM_DIG_BACKOFF_MAX; - p_dm_dig_table->backoff_val_range_min = DM_DIG_BACKOFF_MIN; - #if PHYDM_SUPPORT_CCKPD - p_dm_dig_table->pre_cck_cca_thres = 0xFF; - p_dm_dig_table->cur_cck_cca_thres = 0x83; - #endif - p_dm_dig_table->forbidden_igi = DM_DIG_MIN_NIC; - p_dm_dig_table->large_fa_hit = 0; - p_dm_dig_table->large_fa_timeout = 0; - p_dm_dig_table->recover_cnt = 0; - p_dm_dig_table->is_media_connect_0 = false; - p_dm_dig_table->is_media_connect_1 = false; - - /* To Initialize p_dm_odm->is_dm_initial_gain_enable == false to avoid DIG error */ - p_dm_odm->is_dm_initial_gain_enable = true; + u32 ret_value = 0; + u8 i; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - p_dm_dig_table->dig_dynamic_min_0 = 0x25; - p_dm_dig_table->dig_dynamic_min_1 = 0x25; + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; - /* For AP\ ADSL modified DIG */ - p_dm_dig_table->is_tp_target = false; - p_dm_dig_table->is_noise_est = true; - p_dm_dig_table->igi_offset_a = 0; - p_dm_dig_table->igi_offset_b = 0; - p_dm_dig_table->tp_train_th_min = 0; + dig_t->is_ignore_dig = false; + dig_t->cur_ig_value = (u8) odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm)); + dig_t->is_media_connect = false; + dig_t->fa_th[0] = 250; + dig_t->fa_th[1] = 500; + dig_t->fa_th[2] = 750; + dig_t->is_dbg_fa_th = false; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) /* For RTL8881A */ false_alm_cnt->cnt_ofdm_fail_pre = 0; - - /* Dyanmic EDCCA */ - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - odm_set_bb_reg(p_dm_odm, 0xC50, 0xFFFF0000, 0xfafd); -#else - p_dm_dig_table->dig_dynamic_min_0 = DM_DIG_MIN_NIC; - p_dm_dig_table->dig_dynamic_min_1 = DM_DIG_MIN_NIC; - - /* To Initi BT30 IGI */ - p_dm_dig_table->bt30_cur_igi = 0x32; - - odm_memory_set(p_dm_odm, p_dm_dig_table->pause_dig_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); - p_dm_dig_table->pause_dig_level = 0; - #if PHYDM_SUPPORT_CCKPD - odm_memory_set(p_dm_odm, p_dm_dig_table->pause_cckpd_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); - p_dm_dig_table->pause_cckpd_level = 0; - #endif #endif - if (p_dm_odm->board_type & (ODM_BOARD_EXT_PA | ODM_BOARD_EXT_LNA)) { - p_dm_dig_table->rx_gain_range_max = DM_DIG_MAX_NIC; - p_dm_dig_table->rx_gain_range_min = DM_DIG_MIN_NIC; - } else { - p_dm_dig_table->rx_gain_range_max = DM_DIG_MAX_NIC; - p_dm_dig_table->rx_gain_range_min = DM_DIG_MIN_NIC; - } + odm_memory_set(dm, dig_t->pause_dig_value, 0, PHYDM_PAUSE_MAX_NUM); + dig_t->pause_lv_bitmap = 0; + + dig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE; + dig_t->rx_gain_range_min = dig_t->cur_ig_value; #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - p_dm_dig_table->enable_adjust_big_jump = 1; - if (p_dm_odm->support_ic_type & ODM_RTL8822B) { - ret_value = odm_get_bb_reg(p_dm_odm, 0x8c8, MASKLWORD); - p_dm_dig_table->big_jump_step1 = (u8)(ret_value & 0xe) >> 1; - p_dm_dig_table->big_jump_step2 = (u8)(ret_value & 0x30) >> 4; - p_dm_dig_table->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6; - - } else if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_BB_AGC_SET_2_11N, MASKLWORD); - p_dm_dig_table->big_jump_step1 = (u8)(ret_value & 0xe) >> 1; - p_dm_dig_table->big_jump_step2 = (u8)(ret_value & 0x30) >> 4; - p_dm_dig_table->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6; - } - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) { - for (i = 0; i < sizeof(p_dm_dig_table->big_jump_lmt); i++) { - if (p_dm_dig_table->big_jump_lmt[i] == 0) - p_dm_dig_table->big_jump_lmt[i] = 0x64; /* Set -10dBm as default value */ + dig_t->enable_adjust_big_jump = 1; + if (dm->support_ic_type & ODM_RTL8822B) + ret_value = odm_get_bb_reg(dm, 0x8c8, MASKLWORD); + else if (dm->support_ic_type & ODM_RTL8197F) + ret_value = odm_get_bb_reg(dm, 0xc74, MASKLWORD); + + dig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1; + dig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4; + dig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6; + + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) { + for (i = 0; i < sizeof(dig_t->big_jump_lmt); i++) { + if (dig_t->big_jump_lmt[i] == 0) + dig_t->big_jump_lmt[i] = 0x64; /* Set -10dBm as default value */ } } #endif + dm->pre_rssi_min = 0; -#if (DIG_HW == 1) - p_dm_dig_table->pre_rssi_min = 0; +#ifdef PHYDM_TDMA_DIG_SUPPORT + dm->original_dig_restore = 1; #endif } - -void -odm_DIG( - void *p_dm_void +boolean +phydm_dig_performance_mode_decision( + struct dm_struct *dm ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; - struct sta_info *p_entry; -#endif + boolean is_performance = true; - /* Common parameters */ - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - boolean first_connect, first_dis_connect; - u8 dig_max_of_min, dig_dynamic_min; - u8 dm_dig_max, dm_dig_min; - u8 current_igi = p_dm_dig_table->cur_ig_value; - u8 offset; - u32 dm_FA_thres[3]; - u32 tx_tp = 0, rx_tp = 0; - boolean is_dfs_band = false; - boolean is_performance = true, is_first_tp_target = false, is_first_coverage = false; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u32 tp_train_th_min = dm_dig_tp_target_th0; - static u8 time_cnt = 0; - u8 i; -#endif -#if (DIG_HW == 1) - boolean dig_go_up_check = true; - u8 step_size_1 = 0, step_size_2 = 0, step_size_3 = 0; -#endif - - if (odm_dig_abort(p_dm_odm) == true) - return; +#ifdef PHYDM_DIG_MODE_DECISION_SUPPORT + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG Start===>\n")); - -#if (DIG_HW == 1) - if (p_dm_odm->is_linked) { - if (p_dm_dig_table->pre_rssi_min <= p_dm_odm->rssi_min) { - step_size_1 = 2; - step_size_2 = 1; - step_size_3 = 2; - } else { - step_size_1 = 4; - step_size_2 = 2; - step_size_3 = 2; - } - p_dm_dig_table->pre_rssi_min = p_dm_odm->rssi_min; - } else { - step_size_1 = 2; - step_size_2 = 1; - step_size_3 = 2; + switch (dig_t->dig_mode_decision) { + case PHYDM_DIG_PERFORAMNCE_MODE: + is_performance = true; + break; + case PHYDM_DIG_COVERAGE_MODE: + is_performance = false; + break; + default: + is_performance = true; + break; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("rssi_min = %d, pre_rssi_min = %d\n", p_dm_odm->rssi_min, p_dm_dig_table->pre_rssi_min)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("step_size_1 = %d, step_size_2 = %d, step_size_3 = %d\n", step_size_1, step_size_2, step_size_3)); #endif - /* 1 Update status */ - { - dig_dynamic_min = p_dm_dig_table->dig_dynamic_min_0; - first_connect = (p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == false); - first_dis_connect = (!p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == true); - } + return is_performance; +} -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - /* 1 Noise Floor Estimate */ - /* p_dm_dig_table->is_noise_est = (first_connect)?true:p_dm_dig_table->is_noise_est; */ - /* odm_inband_noise_calculate (p_dm_odm); */ - - /* 1 mode decision */ - if (p_dm_odm->is_linked) { - /* 2 Calculate total TP */ - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { - rx_tp += (u32)(p_entry->rx_byte_cnt_low_maw >> 7); - tx_tp += (u32)(p_entry->tx_byte_cnt_low_maw >> 7); /* Kbps */ - } +void +phydm_dig_abs_boundary_decision( + struct dm_struct *dm, + boolean is_performance, + boolean is_dfs_band +) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + if (!dm->is_linked) { + dig_t->dm_dig_max = DIG_MAX_COVERAGR; + dig_t->dm_dig_min = DIG_MIN_COVERAGE; + } else if (is_dfs_band == true) { + if (*dm->band_width == CHANNEL_WIDTH_20) + dig_t->dm_dig_min = DIG_MIN_DFS + 2; + else + dig_t->dm_dig_min = DIG_MIN_DFS; + + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + + } else if (!is_performance) { + dig_t->dm_dig_max = DIG_MAX_COVERAGR; + dig_t->dm_dig_min = DIG_MIN_COVERAGE; + #if (DIG_HW == 1) + dig_t->dig_max_of_min = DIG_MIN_COVERAGE; + #else + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE; + #endif + } else { + if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) { /*service > 2 devices*/ + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + #if (DIG_HW == 1) + dig_t->dig_max_of_min = DIG_MIN_COVERAGE; + #else + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; + #endif + } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) { /*service 1 devices*/ + dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE; + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: TX TP = %dkbps, RX TP = %dkbps\n", tx_tp, rx_tp)); - } - switch (p_dm_odm->priv->pshare->rf_ft_var.dig_cov_enable) { - case 0: - { - is_performance = true; - break; + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)) + dig_t->dm_dig_min = 0x1c; + else if (dm->support_ic_type & ODM_RTL8197F) + dig_t->dm_dig_min = 0x1e; /*For HW setting*/ + else + dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; } - case 1: - { - is_performance = false; - break; + + PHYDM_DBG(dm, DBG_DIG, + "Abs-bound{Max, Min}={0x%x, 0x%x}, Max_of_min = 0x%x\n", + dig_t->dm_dig_max, + dig_t->dm_dig_min, + dig_t->dig_max_of_min); + +} + +void +phydm_dig_dym_boundary_decision( + struct dm_struct *dm, + boolean is_performance +) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 offset = 15, tmp_max = 0; + u8 max_of_rssi_min = 0; + + PHYDM_DBG(dm, DBG_DIG, + "Offset=((%d))\n", offset); + + /* DIG lower bound */ + if (dm->rssi_min > dig_t->dig_max_of_min) + dig_t->rx_gain_range_min = dig_t->dig_max_of_min; + else if (dm->rssi_min < dig_t->dm_dig_min) + dig_t->rx_gain_range_min = dig_t->dm_dig_min; + else + dig_t->rx_gain_range_min = dm->rssi_min; + + /* DIG upper bound */ + tmp_max = dig_t->rx_gain_range_min + offset; + if (dig_t->rx_gain_range_min != dm->rssi_min) { + max_of_rssi_min = dm->rssi_min + offset; + if (tmp_max > max_of_rssi_min) + tmp_max = max_of_rssi_min; } - case 2: - { - if (p_dm_odm->is_linked) { - if (p_dm_dig_table->tp_train_th_min > dm_dig_tp_target_th0) - tp_train_th_min = p_dm_dig_table->tp_train_th_min; - - if (p_dm_dig_table->tp_train_th_min > dm_dig_tp_target_th1) - tp_train_th_min = dm_dig_tp_target_th1; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: TP training mode lower bound = %dkbps\n", tp_train_th_min)); - - /* 2 Decide DIG mode by total TP */ - if ((tx_tp + rx_tp) > dm_dig_tp_target_th1) { /* change to performance mode */ - is_first_tp_target = (!p_dm_dig_table->is_tp_target) ? true : false; - p_dm_dig_table->is_tp_target = true; - is_performance = true; - } else if ((tx_tp + rx_tp) < tp_train_th_min) { /* change to coverage mode */ - is_first_coverage = (p_dm_dig_table->is_tp_target) ? true : false; - - if (time_cnt < dm_dig_tp_training_period) { - p_dm_dig_table->is_tp_target = false; - is_performance = false; - time_cnt++; - } else { - p_dm_dig_table->is_tp_target = true; - is_performance = true; - is_first_tp_target = true; - time_cnt = 0; - } - } else { /* remain previous mode */ - is_performance = p_dm_dig_table->is_tp_target; - - if (!is_performance) { - if (time_cnt < dm_dig_tp_training_period) - time_cnt++; - else { - p_dm_dig_table->is_tp_target = true; - is_performance = true; - is_first_tp_target = true; - time_cnt = 0; - } - } - } - if (!is_performance) - p_dm_dig_table->tp_train_th_min = rx_tp + tx_tp; + if (tmp_max > dig_t->dm_dig_max) + dig_t->rx_gain_range_max = dig_t->dm_dig_max; + else + dig_t->rx_gain_range_max = tmp_max; - } else { - is_performance = false; - p_dm_dig_table->tp_train_th_min = 0; + /* 1 Force Lower Bound for AntDiv */ + if (dm->is_one_entry_only != 0) + goto out; + + if ((dm->support_ic_type & ODM_ANTDIV_SUPPORT) && (dm->support_ability & ODM_BB_ANT_DIV)) { + if (dm->ant_div_type == CG_TRX_HW_ANTDIV || dm->ant_div_type == CG_TRX_SMART_ANTDIV) { + if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min) + dig_t->rx_gain_range_min = dig_t->dig_max_of_min; + else + dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max; + + PHYDM_DBG(dm, DBG_DIG, + "AntDiv: Force Dyn-Min = 0x%x, RSSI_max = 0x%x\n", + dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max); } - break; - } - default: - is_performance = true; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("====== DIG mode = %d ======\n", p_dm_odm->priv->pshare->rf_ft_var.dig_cov_enable)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("====== is_performance = %d ======\n", is_performance)); -#endif +out: + PHYDM_DBG(dm, DBG_DIG, + "Dym-bound{Max, Min}={0x%x, 0x%x}\n", + dig_t->rx_gain_range_max, dig_t->rx_gain_range_min); +} - /* 1 Boundary Decision */ - { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - /* 2 For AP\ADSL */ - if (!is_performance) { - dm_dig_max = DM_DIG_MAX_AP_COVERAGR; - dm_dig_min = DM_DIG_MIN_AP_COVERAGE; -#if (DIG_HW == 1) - dig_max_of_min = DM_DIG_MIN_AP_COVERAGE; -#else - dig_max_of_min = DM_DIG_MAX_OF_MIN_COVERAGE; -#endif +void +phydm_dig_abnormal_case( + struct dm_struct *dm, + u8 current_igi, + boolean is_performance, + boolean is_dfs_band +) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + boolean first_connect = false, first_dis_connect = false; - } else { - if (p_dm_odm->rf_type == ODM_1T1R) - dm_dig_max = DM_DIG_MAX_AP - 6; - else - dm_dig_max = DM_DIG_MAX_AP; + first_connect = (dm->is_linked) && !dig_t->is_media_connect; + first_dis_connect = (!dm->is_linked) && dig_t->is_media_connect; - if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) && (p_dm_odm->support_ic_type & ODM_RTL8814A)) /* for 2G 8814 */ - dm_dig_min = 0x1c; - else if (p_dm_odm->support_ic_type & ODM_RTL8197F) - dm_dig_min = 0x1e; - else - dm_dig_min = DM_DIG_MIN_AP; + /* Modify DIG lower bound, deal with abnormal case */ + if (!dm->is_linked && is_dfs_band && is_performance) { + dig_t->rx_gain_range_max = DIG_MAX_DFS; + PHYDM_DBG(dm, DBG_DIG, + "DFS band: Force max to 0x%x before link\n", dig_t->rx_gain_range_max); + } -#if (DIG_HW == 1) - dig_max_of_min = DM_DIG_MIN_AP_COVERAGE; -#else - dig_max_of_min = DM_DIG_MAX_OF_MIN; -#endif + if (is_dfs_band) + dig_t->rx_gain_range_min = dig_t->dm_dig_min; - } + /* Abnormal lower bound case */ + if (dig_t->rx_gain_range_min > dig_t->rx_gain_range_max) + dig_t->rx_gain_range_min = dig_t->rx_gain_range_max; - /* 4 TX2path */ - if (priv->pmib->dot11RFEntry.tx2path && !is_dfs_band && (*(p_dm_odm->p_wireless_mode) == ODM_WM_B)) - dm_dig_max = 0x2A; + PHYDM_DBG(dm, DBG_DIG, + "Abnoraml checked {Max, Min}={0x%x, 0x%x}\n", + dig_t->rx_gain_range_max, dig_t->rx_gain_range_min); -#if RTL8192E_SUPPORT -#ifdef HIGH_POWER_EXT_LNA - if ((p_dm_odm->support_ic_type & (ODM_RTL8192E)) && (p_dm_odm->ext_lna)) - dm_dig_max = 0x42; -#endif -#endif - if (p_dm_odm->igi_lower_bound) { - if (dm_dig_min < p_dm_odm->igi_lower_bound) - dm_dig_min = p_dm_odm->igi_lower_bound; - if (dig_max_of_min < p_dm_odm->igi_lower_bound) - dig_max_of_min = p_dm_odm->igi_lower_bound; - } - if (p_dm_odm->igi_upper_bound) { - if (dm_dig_max > p_dm_odm->igi_upper_bound) - dm_dig_max = p_dm_odm->igi_upper_bound; - if (dig_max_of_min > p_dm_odm->igi_upper_bound) - dig_max_of_min = p_dm_odm->igi_upper_bound; - } -#else - /* 2 For WIN\CE */ - if (p_dm_odm->support_ic_type >= ODM_RTL8188E) - dm_dig_max = 0x5A; - else - dm_dig_max = DM_DIG_MAX_NIC; +} - if (p_dm_odm->support_ic_type != ODM_RTL8821) - dm_dig_min = DM_DIG_MIN_NIC; - else - dm_dig_min = 0x1C; +u8 +phydm_dig_current_igi_by_fa_th( + struct dm_struct *dm, + u8 current_igi, + u32 false_alm_cnt, + u8 *step_size +) +{ + boolean dig_go_up_check = true; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + dig_go_up_check = phydm_dig_go_up_check(dm); - dig_max_of_min = DM_DIG_MAX_AP; -#endif + if ((false_alm_cnt > dig_t->fa_th[2]) && dig_go_up_check) + current_igi = current_igi + step_size[0]; + else if ((false_alm_cnt > dig_t->fa_th[1]) && dig_go_up_check) + current_igi = current_igi + step_size[1]; + else if (false_alm_cnt < dig_t->fa_th[0]) + current_igi = current_igi - step_size[2]; + return current_igi; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - /* Modify lower bound for DFS band */ - if ((((*p_dm_odm->p_channel >= 52) && (*p_dm_odm->p_channel <= 64)) || - ((*p_dm_odm->p_channel >= 100) && (*p_dm_odm->p_channel <= 140))) -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - && phydm_dfs_master_enabled(p_dm_odm) == true -#endif - ) { - is_dfs_band = true; - if (*p_dm_odm->p_band_width == ODM_BW20M) - dm_dig_min = DM_DIG_MIN_AP_DFS + 2; - else - dm_dig_min = DM_DIG_MIN_AP_DFS; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: ====== In DFS band ======\n")); - } -#endif - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Absolutly upper bound = 0x%x, lower bound = 0x%x\n", dm_dig_max, dm_dig_min)); +} -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (p_dm_odm->pu1_forced_igi_lb && (0 < *p_dm_odm->pu1_forced_igi_lb)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Force IGI lb to: 0x%02x\n", *p_dm_odm->pu1_forced_igi_lb)); - dm_dig_min = *p_dm_odm->pu1_forced_igi_lb; - dm_dig_max = (dm_dig_min <= dm_dig_max) ? (dm_dig_max) : (dm_dig_min + 1); +u8 +phydm_dig_igi_start_value( + struct dm_struct *dm, + boolean is_performance, + u8 current_igi, + u32 false_alm_cnt, + boolean is_dfs_band +) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 step_size[3] = {0}; + boolean first_connect = false, first_dis_connect = false; + + first_connect = (dm->is_linked) && !dig_t->is_media_connect; + first_dis_connect = (!dm->is_linked) && dig_t->is_media_connect; + + if (dm->is_linked) { + if (dm->pre_rssi_min <= dm->rssi_min) { + step_size[0] = 2; + step_size[1] = 1; + step_size[2] = 2; + } else { + step_size[0] = 4; + step_size[1] = 2; + step_size[2] = 2; + } + dm->pre_rssi_min = dm->rssi_min; + } else { + step_size[0] = 2; + step_size[1] = 1; + step_size[2] = 2; } -#endif - - /* 1 Adjust boundary by RSSI */ - if (p_dm_odm->is_linked && is_performance) { - /* 2 Modify DIG upper bound */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - offset = 15; -#else - /* 4 Modify DIG upper bound for 92E, 8723A\B, 8821 & 8812 BT */ - if ((p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821)) && (p_dm_odm->is_bt_limited_dig == 1)) { - offset = 10; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Coex. case: Force upper bound to RSSI + %d\n", offset)); - } else - offset = 15; -#endif + + PHYDM_DBG(dm, DBG_DIG, + "step_size = {-%d, +%d, +%d}\n", step_size[2], step_size[1], step_size[0]); - if ((p_dm_odm->rssi_min + offset) > dm_dig_max) - p_dm_dig_table->rx_gain_range_max = dm_dig_max; - else if ((p_dm_odm->rssi_min + offset) < dm_dig_min) - p_dm_dig_table->rx_gain_range_max = dm_dig_min; - else - p_dm_dig_table->rx_gain_range_max = p_dm_odm->rssi_min + offset; + PHYDM_DBG(dm, DBG_DIG, + "rssi_min = %d, pre_rssi_min = %d\n", dm->rssi_min, dm->pre_rssi_min); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - /* 2 Modify DIG lower bound */ - /* if(p_dm_odm->is_one_entry_only) */ - { - if (p_dm_odm->rssi_min < dm_dig_min) - dig_dynamic_min = dm_dig_min; - else if (p_dm_odm->rssi_min > dig_max_of_min) - dig_dynamic_min = dig_max_of_min; - else - dig_dynamic_min = p_dm_odm->rssi_min; + if (dm->is_linked && is_performance) { + /* 2 After link */ + PHYDM_DBG(dm, DBG_DIG, "Adjust IGI after link\n"); -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (first_connect && is_performance) { if (is_dfs_band) { - dig_dynamic_min = dm_dig_min; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); - } -#endif - } -#else - { - /* 4 For AP */ -#ifdef __ECOS - HAL_REORDER_BARRIER(); -#else - rmb(); -#endif - if (is_dfs_band) { - dig_dynamic_min = dm_dig_min; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); - } else { - if (p_dm_odm->rssi_min < dm_dig_min) - dig_dynamic_min = dm_dig_min; - else if (p_dm_odm->rssi_min > dig_max_of_min) - dig_dynamic_min = dig_max_of_min; + if (dm->rssi_min > DIG_MAX_DFS) + current_igi = DIG_MAX_DFS; else - dig_dynamic_min = p_dm_odm->rssi_min; - } - } + current_igi = dm->rssi_min; + PHYDM_DBG(dm, DBG_DIG, + "DFS band: one shot IGI to 0x%x most\n", dig_t->rx_gain_range_max); + } else + current_igi = dig_t->rx_gain_range_min; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8812) + odm_config_bb_with_header_file(dm, CONFIG_BB_AGC_TAB_DIFF); #endif - } else { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - if (is_performance && is_dfs_band) { - p_dm_dig_table->rx_gain_range_max = 0x28; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: Force upper bound to 0x%x before link\n", p_dm_dig_table->rx_gain_range_max)); - } else #endif - { - if (is_performance) - p_dm_dig_table->rx_gain_range_max = DM_DIG_MAX_OF_MIN; - else - p_dm_dig_table->rx_gain_range_max = dm_dig_max; + PHYDM_DBG(dm, DBG_DIG, + "First connect case: IGI does on-shot to 0x%x\n", current_igi); + } else { + /* 4 Abnormal # beacon case */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if ((dm->phy_dbg_info.num_qry_beacon_pkt < 5) && + (false_alm_cnt < DM_DIG_FA_TH1) && (dm->bsta_state)) { + if (dm->support_ic_type != ODM_RTL8723D) { + dig_t->rx_gain_range_min = 0x1c; + current_igi = dig_t->rx_gain_range_min; + PHYDM_DBG(dm, DBG_DIG, + "Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n", + dm->phy_dbg_info.num_qry_beacon_pkt, current_igi); + } + } else +#endif + current_igi = phydm_dig_current_igi_by_fa_th(dm, + current_igi, false_alm_cnt, step_size); } - dig_dynamic_min = dm_dig_min; - } + } else { + /* 2 Before link */ + PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n"); - /* 1 Force Lower Bound for AntDiv */ - if (p_dm_odm->is_linked && !p_dm_odm->is_one_entry_only) { - if ((p_dm_odm->support_ic_type & ODM_ANTDIV_SUPPORT) && (p_dm_odm->support_ability & ODM_BB_ANT_DIV)) { - if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV || p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) { - if (p_dm_dig_table->ant_div_rssi_max > dig_max_of_min) - dig_dynamic_min = dig_max_of_min; - else - dig_dynamic_min = (u8) p_dm_dig_table->ant_div_rssi_max; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: AntDiv case: Force lower bound to 0x%x\n", dig_dynamic_min)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: AntDiv case: RSSI_max = 0x%x\n", p_dm_dig_table->ant_div_rssi_max)); - } + if (first_dis_connect) { + current_igi = dig_t->dm_dig_min; + PHYDM_DBG(dm, DBG_DIG, "First disconnect case: IGI does on-shot to lower bound\n"); + } else { + PHYDM_DBG(dm, DBG_DIG, + "Pre_IGI=((0x%x)), FA=((%d))\n", current_igi, false_alm_cnt); + + current_igi = phydm_dig_current_igi_by_fa_th(dm, + current_igi, false_alm_cnt, step_size); } } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Adjust boundary by RSSI Upper bound = 0x%x, Lower bound = 0x%x\n", - p_dm_dig_table->rx_gain_range_max, dig_dynamic_min)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Link status: is_linked = %d, RSSI = %d, bFirstConnect = %d, bFirsrDisConnect = %d\n", - p_dm_odm->is_linked, p_dm_odm->rssi_min, first_connect, first_dis_connect)); - /* 1 Modify DIG lower bound, deal with abnormal case */ - /* 2 Abnormal false alarm case */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - if (is_dfs_band) - p_dm_dig_table->rx_gain_range_min = dig_dynamic_min; - else -#endif - { - if (!p_dm_odm->is_linked) { - p_dm_dig_table->rx_gain_range_min = dig_dynamic_min; + return current_igi; - if (first_dis_connect) - p_dm_dig_table->forbidden_igi = dig_dynamic_min; - } else - p_dm_dig_table->rx_gain_range_min = odm_forbidden_igi_check(p_dm_odm, dig_dynamic_min, current_igi); - } +} - /* 2 Abnormal # beacon case */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (p_dm_odm->is_linked && !first_connect) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Beacon Num (%d)\n", p_dm_odm->phy_dbg_info.num_qry_beacon_pkt)); -#if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type != ODM_RTL8723D) { - if ((p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 5) && (p_dm_odm->bsta_state)) { - p_dm_dig_table->rx_gain_range_min = 0x1c; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnrormal #beacon (%d) case in STA mode: Force lower bound to 0x%x\n", - p_dm_odm->phy_dbg_info.num_qry_beacon_pkt, p_dm_dig_table->rx_gain_range_min)); - } - } -#endif +void +phydm_dig( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; +#ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc; +#endif + boolean first_connect, first_dis_connect; + u8 current_igi = dig_t->cur_ig_value; + u32 false_alm_cnt= falm_cnt->cnt_all; + boolean is_dfs_band = false, is_performance = true; + +#ifdef PHYDM_TDMA_DIG_SUPPORT + if (dm->original_dig_restore == 0) { + if (dig_t->cur_ig_value_tdma == 0) + dig_t->cur_ig_value_tdma = dig_t->cur_ig_value; + + current_igi = dig_t->cur_ig_value_tdma; + false_alm_cnt = falm_cnt_acc->cnt_all_1sec; } #endif - /* 2 Abnormal lower bound case */ - if (p_dm_dig_table->rx_gain_range_min > p_dm_dig_table->rx_gain_range_max) { - p_dm_dig_table->rx_gain_range_min = p_dm_dig_table->rx_gain_range_max; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnrormal lower bound case: Force lower bound to 0x%x\n", p_dm_dig_table->rx_gain_range_min)); + if (odm_dig_abort(dm) == true) { + dig_t->cur_ig_value = (u8)odm_get_bb_reg(dm, 0xc50, 0x7f); + return; } + PHYDM_DBG(dm, DBG_DIG, "%s Start===>\n", __func__); - /* 1 False alarm threshold decision */ - odm_fa_threshold_check(p_dm_odm, is_dfs_band, is_performance, rx_tp, tx_tp, dm_FA_thres); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: False alarm threshold = %d, %d, %d\n", dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); - - /* 1 Adjust initial gain by false alarm */ - if (p_dm_odm->is_linked && is_performance) { - /* 2 After link */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Adjust IGI after link\n")); + /* 1 Update status */ + first_connect = (dm->is_linked) && !dig_t->is_media_connect; + first_dis_connect = (!dm->is_linked) && dig_t->is_media_connect; - if (is_first_tp_target || (first_connect && is_performance)) { - p_dm_dig_table->large_fa_hit = 0; + PHYDM_DBG(dm, DBG_DIG, + "is_linked = %d, RSSI = %d, 1stConnect = %d, 1stDisconnect = %d\n", + dm->is_linked, dm->rssi_min, first_connect, first_dis_connect); #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - if (is_dfs_band) { - if (p_dm_odm->rssi_min > 0x28) - current_igi = 0x28; - else - current_igi = p_dm_odm->rssi_min; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: One-shot to 0x28 upmost\n")); - } else -#endif - { - if (p_dm_odm->rssi_min < dig_max_of_min) { - if (current_igi < p_dm_odm->rssi_min) - current_igi = p_dm_odm->rssi_min; - } else { - if (current_igi < dig_max_of_min) - current_igi = dig_max_of_min; - } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - odm_config_bb_with_header_file(p_dm_odm, CONFIG_BB_AGC_TAB_DIFF); -#endif + /* Modify lower bound for DFS band */ + if (dm->is_dfs_band) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + if (phydm_dfs_master_enabled(dm)) + #endif + is_dfs_band = true; + + PHYDM_DBG(dm, DBG_DIG, "In DFS band\n"); + } #endif - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First connect case: IGI does on-shot to 0x%x\n", current_igi)); + is_performance = phydm_dig_performance_mode_decision(dm); + PHYDM_DBG(dm, DBG_DIG, + "DIG ((%s)) mode\n", (is_performance ? "Performance" : "Coverage")); - } else { + /* Boundary Decision */ + phydm_dig_abs_boundary_decision(dm, is_performance, is_dfs_band); -#if ((DM_ODM_SUPPORT_TYPE & (ODM_AP)) && (DIG_HW == 1)) - if (priv->pshare->rf_ft_var.dig_upcheck_enable) - dig_go_up_check = phydm_dig_go_up_check(p_dm_odm); -#endif + /*init dym boundary*/ + dig_t->rx_gain_range_max = dig_t->dig_max_of_min; /*if no link, always stay at lower bound*/ + dig_t->rx_gain_range_min = dig_t->dm_dig_min; -#if (DIG_HW == 1) - if ((p_false_alm_cnt->cnt_all > dm_FA_thres[2]) && dig_go_up_check) - current_igi = current_igi + step_size_1; - else if ((p_false_alm_cnt->cnt_all > dm_FA_thres[1]) && dig_go_up_check) - current_igi = current_igi + step_size_2; - else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) - current_igi = current_igi - step_size_3; -#else - if (p_false_alm_cnt->cnt_all > dm_FA_thres[2]) - current_igi = current_igi + 4; - else if (p_false_alm_cnt->cnt_all > dm_FA_thres[1]) - current_igi = current_igi + 2; - else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) - current_igi = current_igi - 2; -#endif + /* Adjust boundary by RSSI */ + if (dm->is_linked) + phydm_dig_dym_boundary_decision(dm, is_performance); - /* 4 Abnormal # beacon case */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if ((p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 5) && (p_false_alm_cnt->cnt_all < DM_DIG_FA_TH1) && (p_dm_odm->bsta_state)) { - current_igi = p_dm_dig_table->rx_gain_range_min; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n", - p_dm_odm->phy_dbg_info.num_qry_beacon_pkt, current_igi)); - } -#endif - } - } else { - /* 2 Before link */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Adjust IGI before link\n")); - - if (first_dis_connect || is_first_coverage) { - current_igi = dm_dig_min; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First disconnect case: IGI does on-shot to lower bound\n")); - } else { + /*Abnormal case check*/ + phydm_dig_abnormal_case(dm, current_igi, is_performance, is_dfs_band); -#if ((DM_ODM_SUPPORT_TYPE & (ODM_AP)) && (DIG_HW == 1)) - if (priv->pshare->rf_ft_var.dig_upcheck_enable) - dig_go_up_check = phydm_dig_go_up_check(p_dm_odm); -#endif + /* False alarm threshold decision */ + odm_fa_threshold_check(dm, is_dfs_band, is_performance); -#if (DIG_HW == 1) - if ((p_false_alm_cnt->cnt_all > dm_FA_thres[2]) && dig_go_up_check) - current_igi = current_igi + step_size_1; - else if ((p_false_alm_cnt->cnt_all > dm_FA_thres[1]) && dig_go_up_check) - current_igi = current_igi + step_size_2; - else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) - current_igi = current_igi - step_size_3; -#else - if (p_false_alm_cnt->cnt_all > dm_FA_thres[2]) - current_igi = current_igi + 4; - else if (p_false_alm_cnt->cnt_all > dm_FA_thres[1]) - current_igi = current_igi + 2; - else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) - current_igi = current_igi - 2; -#endif - } - } + /* 1 Adjust initial gain by false alarm */ + current_igi = phydm_dig_igi_start_value(dm, + is_performance, current_igi, false_alm_cnt, is_dfs_band); /* 1 Check initial gain by upper/lower bound */ - if (current_igi < p_dm_dig_table->rx_gain_range_min) - current_igi = p_dm_dig_table->rx_gain_range_min; + if (current_igi < dig_t->rx_gain_range_min) + current_igi = dig_t->rx_gain_range_min; - if (current_igi > p_dm_dig_table->rx_gain_range_max) - current_igi = p_dm_dig_table->rx_gain_range_max; + if (current_igi > dig_t->rx_gain_range_max) + current_igi = dig_t->rx_gain_range_max; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: cur_ig_value=0x%x, TotalFA = %d\n", current_igi, p_false_alm_cnt->cnt_all)); + PHYDM_DBG(dm, DBG_DIG, "New_IGI=((0x%x))\n", current_igi); /* 1 Update status */ - { -#if ((DM_ODM_SUPPORT_TYPE & ODM_WIN) || ((DM_ODM_SUPPORT_TYPE & ODM_CE) && (ODM_CONFIG_BT_COEXIST == 1))) - if (p_dm_odm->is_bt_hs_operation) { - if (p_dm_odm->is_linked) { - if (p_dm_dig_table->bt30_cur_igi > (current_igi)) - odm_write_dig(p_dm_odm, current_igi); - else - odm_write_dig(p_dm_odm, p_dm_dig_table->bt30_cur_igi); - - p_dm_dig_table->is_media_connect_0 = p_dm_odm->is_linked; - p_dm_dig_table->dig_dynamic_min_0 = dig_dynamic_min; - } else { - if (p_dm_odm->is_link_in_process) - odm_write_dig(p_dm_odm, 0x1c); - else if (p_dm_odm->is_bt_connect_process) - odm_write_dig(p_dm_odm, 0x28); - else - odm_write_dig(p_dm_odm, p_dm_dig_table->bt30_cur_igi);/* odm_write_dig(p_dm_odm, p_dm_dig_table->cur_ig_value); */ - } - } else /* BT is not using */ -#endif - { - odm_write_dig(p_dm_odm, current_igi);/* odm_write_dig(p_dm_odm, p_dm_dig_table->cur_ig_value); */ - p_dm_dig_table->is_media_connect_0 = p_dm_odm->is_linked; - p_dm_dig_table->dig_dynamic_min_0 = dig_dynamic_min; - } - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG end\n")); +#ifdef PHYDM_TDMA_DIG_SUPPORT + if (dm->original_dig_restore == 0) { + dig_t->cur_ig_value_tdma = current_igi; + /*It is possible fa_acc_1sec_tsf >= */ + /*1sec while tdma_dig_state == 0*/ + if (dig_t->tdma_dig_state != 0) + odm_write_dig(dm, dig_t->cur_ig_value_tdma); + } else +#endif + odm_write_dig(dm, current_igi); + + dig_t->is_media_connect = dm->is_linked; + + PHYDM_DBG(dm, DBG_DIG, "DIG end\n"); } void -odm_dig_by_rssi_lps( - void *p_dm_void +phydm_dig_lps_32k( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 current_igi = dm->rssi_min; + + + odm_write_dig(dm, current_igi); +} + +void +phydm_dig_by_rssi_lps( + void *dm_void ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt; - u8 rssi_lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */ - u8 current_igi = p_dm_odm->rssi_min; + u8 rssi_lower = DIG_MIN_LPS; /* 0x1E or 0x1C */ + u8 current_igi = dm->rssi_min; - if (odm_dig_abort(p_dm_odm) == true) + falm_cnt = &dm->false_alm_cnt; + if (odm_dig_abort(dm) == true) return; - current_igi = current_igi + RSSI_OFFSET_DIG; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps()==>\n")); + current_igi = current_igi + RSSI_OFFSET_DIG_LPS; + PHYDM_DBG(dm, DBG_DIG, "%s==>\n", __func__); /* Using FW PS mode to make IGI */ /* Adjust by FA in LPS MODE */ - if (p_false_alm_cnt->cnt_all > DM_DIG_FA_TH2_LPS) + if (falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS) current_igi = current_igi + 4; - else if (p_false_alm_cnt->cnt_all > DM_DIG_FA_TH1_LPS) + else if (falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS) current_igi = current_igi + 2; - else if (p_false_alm_cnt->cnt_all < DM_DIG_FA_TH0_LPS) + else if (falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS) current_igi = current_igi - 2; /* Lower bound checking */ /* RSSI Lower bound check */ - if ((p_dm_odm->rssi_min - 10) > DM_DIG_MIN_NIC) - rssi_lower = (p_dm_odm->rssi_min - 10); + if ((dm->rssi_min - 10) > DIG_MIN_LPS) + rssi_lower = (dm->rssi_min - 10); else - rssi_lower = DM_DIG_MIN_NIC; + rssi_lower = DIG_MIN_LPS; /* Upper and Lower Bound checking */ - if (current_igi > DM_DIG_MAX_NIC) - current_igi = DM_DIG_MAX_NIC; + if (current_igi > DIG_MAX_LPS) + current_igi = DIG_MAX_LPS; else if (current_igi < rssi_lower) current_igi = rssi_lower; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps(): p_false_alm_cnt->cnt_all = %d\n", p_false_alm_cnt->cnt_all)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps(): p_dm_odm->rssi_min = %d\n", p_dm_odm->rssi_min)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps(): current_igi = 0x%x\n", current_igi)); + PHYDM_DBG(dm, DBG_DIG, + "%s falm_cnt->cnt_all = %d\n", __func__, + falm_cnt->cnt_all); + PHYDM_DBG(dm, DBG_DIG, + "%s dm->rssi_min = %d\n", __func__, + dm->rssi_min); + PHYDM_DBG(dm, DBG_DIG, + "%s current_igi = 0x%x\n", __func__, + current_igi); - odm_write_dig(p_dm_odm, current_igi);/* odm_write_dig(p_dm_odm, p_dm_dig_table->cur_ig_value); */ + /* odm_write_dig(dm, dig_t->cur_ig_value); */ + odm_write_dig(dm, current_igi); #endif } /* 3============================================================ * 3 FASLE ALARM CHECK * 3============================================================ */ +void +phydm_false_alarm_counter_reg_reset( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; +#ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc; +#endif + u32 false_alm_cnt; + +#ifdef PHYDM_TDMA_DIG_SUPPORT + if (dm->original_dig_restore == 0) { + if (dig_t->cur_ig_value_tdma == 0) + dig_t->cur_ig_value_tdma = dig_t->cur_ig_value; + + false_alm_cnt = falm_cnt_acc->cnt_all_1sec; + } else +#endif + { + false_alm_cnt = falm_cnt->cnt_all; + } + +#if (ODM_IC_11N_SERIES_SUPPORT == 1) + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + /*reset false alarm counter registers*/ + odm_set_bb_reg(dm, 0xC0C, BIT(31), 1); + odm_set_bb_reg(dm, 0xC0C, BIT(31), 0); + odm_set_bb_reg(dm, 0xD00, BIT(27), 1); + odm_set_bb_reg(dm, 0xD00, BIT(27), 0); + + /*update ofdm counter*/ + /*update page C counter*/ + odm_set_bb_reg(dm, 0xD00, BIT(31), 0); + /*update page D counter*/ + odm_set_bb_reg(dm, 0xD00, BIT(31), 0); + + /*reset CCK CCA counter*/ + odm_set_bb_reg(dm, 0xA2C, BIT(13) | BIT(12), 0); + odm_set_bb_reg(dm, 0xA2C, BIT(13) | BIT(12), 2); + + /*reset CCK FA counter*/ + odm_set_bb_reg(dm, 0xA2C, BIT(15) | BIT(14), 0); + odm_set_bb_reg(dm, 0xA2C, BIT(15) | BIT(14), 2); + + /*reset CRC32 counter*/ + odm_set_bb_reg(dm, 0xF14, BIT(16), 1); + odm_set_bb_reg(dm, 0xF14, BIT(16), 0); + } +#endif /* #if (ODM_IC_11N_SERIES_SUPPORT == 1) */ + +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + #if (RTL8881A_SUPPORT == 1) + /* Reset FA counter by enable/disable OFDM */ + if (false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) { + /* reset OFDM */ + odm_set_bb_reg(dm, 0x808, BIT(29), 0); + odm_set_bb_reg(dm, 0x808, BIT(29), 1); + false_alm_cnt->cnt_ofdm_fail_pre = 0; + PHYDM_DBG(dm, DBG_FA_CNT, "Reset FA_cnt\n"); + } + #endif /* #if (RTL8881A_SUPPORT == 1) */ + /* reset OFDM FA countner */ + odm_set_bb_reg(dm, 0x9A4, BIT(17), 1); + odm_set_bb_reg(dm, 0x9A4, BIT(17), 0); + + /* reset CCK FA counter */ + odm_set_bb_reg(dm, 0xA2C, BIT(15), 0); + odm_set_bb_reg(dm, 0xA2C, BIT(15), 1); + + /* reset CCA counter */ + odm_set_bb_reg(dm, 0xB58, BIT(0), 1); + odm_set_bb_reg(dm, 0xB58, BIT(0), 0); + } +#endif /* #if (ODM_IC_11AC_SERIES_SUPPORT == 1) */ +} + +void +phydm_false_alarm_counter_reg_hold( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + /*hold ofdm counter*/ + /*hold page C counter*/ + odm_set_bb_reg(dm, 0xC00, BIT(31), 1); + /*hold page D counter*/ + odm_set_bb_reg(dm, 0xD00, BIT(31), 1); + + //hold cck counter + odm_set_bb_reg(dm, 0xA2C, BIT(12), 1); + odm_set_bb_reg(dm, 0xA2C, BIT(14), 1); + } +} void odm_false_alarm_counter_statistics( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT); + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); u32 ret_value; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - /* Mark there, and check this in odm_DMWatchDog */ -#if 0 /* (DM_ODM_SUPPORT_TYPE == ODM_AP) */ - struct rtl8192cd_priv *priv = p_dm_odm->priv; - if ((priv->auto_channel != 0) && (priv->auto_channel != 2)) - return; -#endif -#endif - - if (!(p_dm_odm->support_ability & ODM_BB_FA_CNT)) + if (!(dm->support_ability & ODM_BB_FA_CNT)) return; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("FA_Counter()======>\n")); + PHYDM_DBG(dm, DBG_FA_CNT, "FA_Counter()======>\n"); #if (ODM_IC_11N_SERIES_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - - /* hold ofdm counter */ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */ + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + /* hold ofdm & cck counter */ + phydm_false_alarm_counter_reg_hold(dm); - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD); false_alm_cnt->cnt_fast_fsync = (ret_value & 0xffff); false_alm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD); false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff); false_alm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD); false_alm_cnt->cnt_rate_illegal = (ret_value & 0xffff); false_alm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD); false_alm_cnt->cnt_mcs_fail = (ret_value & 0xffff); - false_alm_cnt->cnt_ofdm_fail = false_alm_cnt->cnt_parity_fail + false_alm_cnt->cnt_rate_illegal + + false_alm_cnt->cnt_ofdm_fail = + false_alm_cnt->cnt_parity_fail + false_alm_cnt->cnt_rate_illegal + false_alm_cnt->cnt_crc8_fail + false_alm_cnt->cnt_mcs_fail + false_alm_cnt->cnt_fast_fsync + false_alm_cnt->cnt_sb_search_fail; /* read CCK CRC32 counter */ - false_alm_cnt->cnt_cck_crc32_error = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CRC32_ERROR_CNT_11N, MASKDWORD); - false_alm_cnt->cnt_cck_crc32_ok = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CRC32_OK_CNT_11N, MASKDWORD); + false_alm_cnt->cnt_cck_crc32_error = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_ERROR_CNT_11N, MASKDWORD); + false_alm_cnt->cnt_cck_crc32_ok = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_OK_CNT_11N, MASKDWORD); /* read OFDM CRC32 counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD); false_alm_cnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff; /* read HT CRC32 counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD); false_alm_cnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff; @@ -1454,40 +1048,41 @@ odm_false_alarm_counter_statistics( false_alm_cnt->cnt_vht_crc32_ok = 0; #if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (dm->support_ic_type == ODM_RTL8723D) { /* read HT CRC32 agg counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_HT_CRC32_CNT_11N_AGG, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N_AGG, MASKDWORD); false_alm_cnt->cnt_ht_crc32_error_agg = (ret_value & 0xffff0000) >> 16; false_alm_cnt->cnt_ht_crc32_ok_agg= ret_value & 0xffff; } #endif - #if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_SC_CNT_11N, MASKDWORD); + if (dm->support_ic_type == ODM_RTL8188E) { + ret_value = odm_get_bb_reg(dm, ODM_REG_SC_CNT_11N, MASKDWORD); false_alm_cnt->cnt_bw_lsc = (ret_value & 0xffff); false_alm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16); } #endif { - /* hold cck counter */ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1); - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1); - - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0); + ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0); false_alm_cnt->cnt_cck_fail = ret_value; - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3); + ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3); false_alm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD); false_alm_cnt->cnt_cck_cca = ((ret_value & 0xFF) << 8) | ((ret_value & 0xFF00) >> 8); } false_alm_cnt->cnt_all_pre = false_alm_cnt->cnt_all; + false_alm_cnt->time_fa_all = (false_alm_cnt->cnt_fast_fsync + false_alm_cnt->cnt_sb_search_fail) * 12 + + (false_alm_cnt->cnt_parity_fail + false_alm_cnt->cnt_rate_illegal) * 28 + + false_alm_cnt->cnt_crc8_fail * 36 + + false_alm_cnt->cnt_mcs_fail * 32 + + false_alm_cnt->cnt_cck_fail * 80; + false_alm_cnt->cnt_all = (false_alm_cnt->cnt_fast_fsync + false_alm_cnt->cnt_sb_search_fail + false_alm_cnt->cnt_parity_fail + @@ -1498,74 +1093,71 @@ odm_false_alarm_counter_statistics( false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_ofdm_cca + false_alm_cnt->cnt_cck_cca; - if (p_dm_odm->support_ic_type >= ODM_RTL8188E) { - /*reset false alarm counter registers*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1); - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1); - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0); - - /*update ofdm counter*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0); /*update page C counter*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0); /*update page D counter*/ - - /*reset CCK CCA counter*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 2); - - /*reset CCK FA counter*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2); - - /*reset CRC32 counter*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_F_RST_11N, BIT(16), 1); - odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_F_RST_11N, BIT(16), 0); - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n", - false_alm_cnt->cnt_parity_fail, false_alm_cnt->cnt_rate_illegal, false_alm_cnt->cnt_crc8_fail, false_alm_cnt->cnt_mcs_fail, false_alm_cnt->cnt_fast_fsync, false_alm_cnt->cnt_sb_search_fail)); + PHYDM_DBG(dm, DBG_FA_CNT, + "[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n", + false_alm_cnt->cnt_parity_fail, false_alm_cnt->cnt_rate_illegal, false_alm_cnt->cnt_crc8_fail, false_alm_cnt->cnt_mcs_fail, false_alm_cnt->cnt_fast_fsync, false_alm_cnt->cnt_sb_search_fail); } #endif #if (ODM_IC_11AC_SERIES_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { u32 cck_enable; + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD); + false_alm_cnt->cnt_fast_fsync = ((ret_value & 0xffff0000) >> 16); + + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD); + false_alm_cnt->cnt_sb_search_fail = (ret_value & 0xffff); + + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD); + false_alm_cnt->cnt_parity_fail = (ret_value & 0xffff); + false_alm_cnt->cnt_rate_illegal = ((ret_value & 0xffff0000) >> 16); + + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD); + false_alm_cnt->cnt_crc8_fail = (ret_value & 0xffff); + false_alm_cnt->cnt_mcs_fail = ((ret_value & 0xffff0000) >> 16); + + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD); + false_alm_cnt->cnt_crc8_fail_vht = (ret_value & 0xffff); + + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD); + false_alm_cnt->cnt_mcs_fail_vht = (ret_value & 0xffff); + /* read OFDM FA counter */ - false_alm_cnt->cnt_ofdm_fail = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_11AC, MASKLWORD); + false_alm_cnt->cnt_ofdm_fail = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_11AC, MASKLWORD); /* Read CCK FA counter */ - false_alm_cnt->cnt_cck_fail = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_FA_11AC, MASKLWORD); + false_alm_cnt->cnt_cck_fail = odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD); /* read CCK/OFDM CCA counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD); false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16; false_alm_cnt->cnt_cck_cca = ret_value & 0xffff; /* read CCK CRC32 counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD); false_alm_cnt->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16; false_alm_cnt->cnt_cck_crc32_ok = ret_value & 0xffff; /* read OFDM CRC32 counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD); false_alm_cnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff; /* read HT CRC32 counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD); false_alm_cnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff; /* read VHT CRC32 counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD); false_alm_cnt->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16; false_alm_cnt->cnt_vht_crc32_ok = ret_value & 0xffff; #if (RTL8881A_SUPPORT == 1) /* For 8881A */ - if (p_dm_odm->support_ic_type == ODM_RTL8881A) { + if (dm->support_ic_type == ODM_RTL8881A) { u32 cnt_ofdm_fail_temp = 0; if (false_alm_cnt->cnt_ofdm_fail >= false_alm_cnt->cnt_ofdm_fail_pre) { @@ -1574,34 +1166,12 @@ odm_false_alarm_counter_statistics( false_alm_cnt->cnt_ofdm_fail = false_alm_cnt->cnt_ofdm_fail - cnt_ofdm_fail_temp; } else false_alm_cnt->cnt_ofdm_fail_pre = false_alm_cnt->cnt_ofdm_fail; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_false_alarm_counter_statistics(): cnt_ofdm_fail=%d\n", false_alm_cnt->cnt_ofdm_fail_pre)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_false_alarm_counter_statistics(): cnt_ofdm_fail_pre=%d\n", cnt_ofdm_fail_temp)); - - /* Reset FA counter by enable/disable OFDM */ - if (false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) { - /* reset OFDM */ - odm_set_bb_reg(p_dm_odm, ODM_REG_BB_RX_PATH_11AC, BIT(29), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_BB_RX_PATH_11AC, BIT(29), 1); - false_alm_cnt->cnt_ofdm_fail_pre = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_false_alarm_counter_statistics(): Reset false alarm counter\n")); - } + PHYDM_DBG(dm, DBG_FA_CNT, "odm_false_alarm_counter_statistics(): cnt_ofdm_fail=%d\n", false_alm_cnt->cnt_ofdm_fail_pre); + PHYDM_DBG(dm, DBG_FA_CNT, "odm_false_alarm_counter_statistics(): cnt_ofdm_fail_pre=%d\n", cnt_ofdm_fail_temp); } #endif - - /* reset OFDM FA coutner */ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 1); - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 0); - - /* reset CCK FA counter */ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 1); - - /* reset CCA counter */ - odm_set_bb_reg(p_dm_odm, ODM_REG_RST_RPT_11AC, BIT(0), 1); - odm_set_bb_reg(p_dm_odm, ODM_REG_RST_RPT_11AC, BIT(0), 0); - - cck_enable = odm_get_bb_reg(p_dm_odm, ODM_REG_BB_RX_PATH_11AC, BIT(28)); - if (cck_enable) { /* if(*p_dm_odm->p_band_type == ODM_BAND_2_4G) */ + cck_enable = odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28)); + if (cck_enable) { /* if(*dm->band_type == ODM_BAND_2_4G) */ false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail + false_alm_cnt->cnt_cck_fail; false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_cck_cca + false_alm_cnt->cnt_ofdm_cca; } else { @@ -1610,694 +1180,689 @@ odm_false_alarm_counter_statistics( } } #endif - if (p_dm_odm->support_ic_type != ODM_RTL8723D) { - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/ - false_alm_cnt->dbg_port0 = phydm_get_bb_dbg_port_value(p_dm_odm); - phydm_release_bb_dbg_port(p_dm_odm); + + if (dm->support_ic_type != ODM_RTL8723D) { + if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/ + false_alm_cnt->dbg_port0 = phydm_get_bb_dbg_port_value(dm); + phydm_release_bb_dbg_port(dm); } - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) { - if (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E)) - false_alm_cnt->edcca_flag = (boolean)((phydm_get_bb_dbg_port_value(p_dm_odm) & BIT(30)) >> 30); + if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) { + if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E)) + false_alm_cnt->edcca_flag = (boolean)((phydm_get_bb_dbg_port_value(dm) & BIT(30)) >> 30); else - false_alm_cnt->edcca_flag = (boolean)((phydm_get_bb_dbg_port_value(p_dm_odm) & BIT(29)) >> 29); - phydm_release_bb_dbg_port(p_dm_odm); + false_alm_cnt->edcca_flag = (boolean)((phydm_get_bb_dbg_port_value(dm) & BIT(29)) >> 29); + phydm_release_bb_dbg_port(dm); } + } else { + false_alm_cnt->edcca_flag = (boolean)(odm_get_bb_reg(dm, 0x9a0, BIT(29))); } - false_alm_cnt->cnt_crc32_error_all = false_alm_cnt->cnt_vht_crc32_error + false_alm_cnt->cnt_ht_crc32_error + false_alm_cnt->cnt_ofdm_crc32_error + false_alm_cnt->cnt_cck_crc32_error; - false_alm_cnt->cnt_crc32_ok_all = false_alm_cnt->cnt_vht_crc32_ok + false_alm_cnt->cnt_ht_crc32_ok + false_alm_cnt->cnt_ofdm_crc32_ok + false_alm_cnt->cnt_cck_crc32_ok; + phydm_false_alarm_counter_reg_reset(dm_void); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all)); + false_alm_cnt->time_fa_all = (false_alm_cnt->cnt_fast_fsync + false_alm_cnt->cnt_sb_search_fail) * 12 + + (false_alm_cnt->cnt_parity_fail + false_alm_cnt->cnt_rate_illegal) * 28 + + (false_alm_cnt->cnt_crc8_fail + false_alm_cnt->cnt_crc8_fail_vht + false_alm_cnt->cnt_mcs_fail_vht) * 36 + + false_alm_cnt->cnt_mcs_fail * 32 + + false_alm_cnt->cnt_cck_fail * 80; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all)); + false_alm_cnt->cnt_crc32_error_all = false_alm_cnt->cnt_vht_crc32_error + false_alm_cnt->cnt_ht_crc32_error + false_alm_cnt->cnt_ofdm_crc32_error + false_alm_cnt->cnt_cck_crc32_error; + false_alm_cnt->cnt_crc32_ok_all = false_alm_cnt->cnt_vht_crc32_ok + false_alm_cnt->cnt_ht_crc32_ok + false_alm_cnt->cnt_ofdm_crc32_ok + false_alm_cnt->cnt_cck_crc32_ok; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[CCK] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_cck_crc32_error, false_alm_cnt->cnt_cck_crc32_ok)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[OFDM]CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_ofdm_crc32_error, false_alm_cnt->cnt_ofdm_crc32_ok)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[ HT ] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_ht_crc32_error, false_alm_cnt->cnt_ht_crc32_ok)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[VHT] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_vht_crc32_error, false_alm_cnt->cnt_vht_crc32_ok)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[VHT] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_crc32_error_all, false_alm_cnt->cnt_crc32_ok_all)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n\n", false_alm_cnt->dbg_port0, false_alm_cnt->edcca_flag)); + PHYDM_DBG(dm, DBG_FA_CNT, + "[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), HT_CRC8_fail = (( %d )), HT_Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d )), VHT_CRC8_fail = (( %d )), VHT_Mcs_fail = (( %d ))\n", + false_alm_cnt->cnt_parity_fail, false_alm_cnt->cnt_rate_illegal, false_alm_cnt->cnt_crc8_fail, false_alm_cnt->cnt_mcs_fail, false_alm_cnt->cnt_fast_fsync, false_alm_cnt->cnt_sb_search_fail, false_alm_cnt->cnt_crc8_fail_vht, false_alm_cnt->cnt_mcs_fail_vht); + PHYDM_DBG(dm, DBG_FA_CNT, "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all); + + PHYDM_DBG(dm, DBG_FA_CNT, "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all); + + PHYDM_DBG(dm, DBG_FA_CNT, "[CCK] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_cck_crc32_error, false_alm_cnt->cnt_cck_crc32_ok); + PHYDM_DBG(dm, DBG_FA_CNT, "[OFDM]CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_ofdm_crc32_error, false_alm_cnt->cnt_ofdm_crc32_ok); + PHYDM_DBG(dm, DBG_FA_CNT, "[ HT ] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_ht_crc32_error, false_alm_cnt->cnt_ht_crc32_ok); + PHYDM_DBG(dm, DBG_FA_CNT, "[VHT] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_vht_crc32_error, false_alm_cnt->cnt_vht_crc32_ok); + PHYDM_DBG(dm, DBG_FA_CNT, "[TOTAL] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_crc32_error_all, false_alm_cnt->cnt_crc32_ok_all); + PHYDM_DBG(dm, DBG_FA_CNT, "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n\n", false_alm_cnt->dbg_port0, false_alm_cnt->edcca_flag); } -/* 3============================================================ - * 3 CCK Packet Detect threshold - * 3============================================================ */ - +#ifdef PHYDM_TDMA_DIG_SUPPORT void -odm_pause_cck_packet_detection( - void *p_dm_void, - enum phydm_pause_type pause_type, - enum phydm_pause_level pause_level, - u8 cck_pd_threshold -) +phydm_set_tdma_dig_timer( + void *dm_void + ) { -#if PHYDM_SUPPORT_CCKPD - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection()=========> level = %d\n", pause_level)); - - if ((p_dm_dig_table->pause_cckpd_level == 0) && (!(p_dm_odm->support_ability & ODM_BB_CCK_PD) || !(p_dm_odm->support_ability & ODM_BB_FA_CNT))) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Return: support_ability ODM_BB_CCK_PD or ODM_BB_FA_CNT is disabled\n")); - return; - } - - if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_pause_cck_packet_detection(): Return: Wrong pause level !!\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 delta_time_us = dm->tdma_dig_timer_ms * 1000; + struct phydm_dig_struct *dig_t; + u32 timeout; + u32 current_time_stamp, diff_time_stamp, regb0; + + dig_t = &dm->dm_dig_table; + /*some IC has no FREERUN_CUNT register, like 92E*/ + if (dm->support_ic_type & ODM_RTL8197F) + current_time_stamp = odm_get_bb_reg(dm, 0x568, bMaskDWord); + else return; - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_cckpd_level, cck_pd_threshold)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - p_dm_dig_table->pause_cckpd_value[7], p_dm_dig_table->pause_cckpd_value[6], p_dm_dig_table->pause_cckpd_value[5], p_dm_dig_table->pause_cckpd_value[4], - p_dm_dig_table->pause_cckpd_value[3], p_dm_dig_table->pause_cckpd_value[2], p_dm_dig_table->pause_cckpd_value[1], p_dm_dig_table->pause_cckpd_value[0])); + timeout = current_time_stamp + delta_time_us; - switch (pause_type) { - /* Pause CCK Packet Detection threshold */ - case PHYDM_PAUSE: - { - /* Disable CCK PD */ - p_dm_odm->support_ability &= ~ODM_BB_CCK_PD; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Pause CCK packet detection threshold !!\n")); - - /* Backup original CCK PD threshold decided by CCK PD mechanism */ - if (p_dm_dig_table->pause_cckpd_level == 0) { - p_dm_dig_table->cck_pd_backup = p_dm_dig_table->cur_cck_cca_thres; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_pause_cck_packet_detection(): Backup CCKPD = 0x%x, new CCKPD = 0x%x\n", p_dm_dig_table->cck_pd_backup, cck_pd_threshold)); - } + diff_time_stamp = current_time_stamp - dig_t->cur_timestamp; + dig_t->pre_timestamp = dig_t->cur_timestamp; + dig_t->cur_timestamp = current_time_stamp; - /* Update pause level */ - p_dm_dig_table->pause_cckpd_level = (p_dm_dig_table->pause_cckpd_level | BIT(pause_level)); + /*HIMR0, it shows HW interrupt mask*/ + regb0 = odm_get_bb_reg(dm, 0xb0, bMaskDWord); - /* Record CCK PD threshold */ - p_dm_dig_table->pause_cckpd_value[pause_level] = cck_pd_threshold; + PHYDM_DBG(dm, DBG_DIG, + "Set next tdma_dig_timer\n"); + PHYDM_DBG(dm, DBG_DIG, + "current_time_stamp=%d, delta_time_us=%d, timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\n", + current_time_stamp, + delta_time_us, + timeout, + diff_time_stamp, + regb0); - /* Write new CCK PD threshold */ - if (BIT(pause_level + 1) > p_dm_dig_table->pause_cckpd_level) { - odm_write_cck_cca_thres(p_dm_odm, cck_pd_threshold); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): CCKPD of higher level = 0x%x\n", cck_pd_threshold)); - } - break; + if (dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/ + odm_set_bb_reg(dm, 0x588, bMaskDWord, timeout); + else { + PHYDM_DBG(dm, DBG_DIG, + "NOT 97F, TDMA-DIG timer does NOT start!\n"); + return; } - /* Resume CCK Packet Detection threshold */ - case PHYDM_RESUME: - { - /* check if the level is illegal or not */ - if ((p_dm_dig_table->pause_cckpd_level & (BIT(pause_level))) != 0) { - p_dm_dig_table->pause_cckpd_level = p_dm_dig_table->pause_cckpd_level & (~(BIT(pause_level))); - p_dm_dig_table->pause_cckpd_value[pause_level] = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Resume CCK PD !!\n")); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Wrong resume level !!\n")); - break; - } - - /* Resume DIG */ - if (p_dm_dig_table->pause_cckpd_level == 0) { - /* Write backup IGI value */ - odm_write_cck_cca_thres(p_dm_odm, p_dm_dig_table->cck_pd_backup); - /* p_dm_dig_table->is_ignore_dig = true; */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Write original CCKPD = 0x%x\n", p_dm_dig_table->cck_pd_backup)); - - /* Enable DIG */ - p_dm_odm->support_ability |= ODM_BB_CCK_PD; - break; - } - - if (BIT(pause_level) > p_dm_dig_table->pause_cckpd_level) { - s8 max_level; +} - /* Calculate the maximum level now */ - for (max_level = (pause_level - 1); max_level >= 0; max_level--) { - if ((p_dm_dig_table->pause_cckpd_level & BIT(max_level)) > 0) - break; - } +void +phydm_tdma_dig_timer_check( + void *dm_void + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t; - /* write CCKPD of lower level */ - odm_write_cck_cca_thres(p_dm_odm, p_dm_dig_table->pause_cckpd_value[max_level]); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Write CCKPD (0x%x) of level (%d)\n", - p_dm_dig_table->pause_cckpd_value[max_level], max_level)); - break; + dig_t = &dm->dm_dig_table; + + PHYDM_DBG(dm, DBG_DIG, + "tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\n", + dig_t->tdma_dig_cnt, + dig_t->pre_tdma_dig_cnt); + + if ((dig_t->tdma_dig_cnt == 0) || + (dig_t->tdma_dig_cnt == dig_t->pre_tdma_dig_cnt)) { + if (dm->support_ability & ODM_BB_DIG) { + /*if interrupt mask info is got.*/ + /*Reg0xb0 is no longer needed*/ + /*regb0 = odm_get_bb_reg(dm, 0xb0, bMaskDWord);*/ + PHYDM_DBG(dm, DBG_DIG, + "Check fail, IntMask[0]=0x%x, restart tdma_dig_timer !!!\n", + *dm->interrupt_mask); + + phydm_tdma_dig_add_interrupt_mask_handler(dm); + phydm_enable_rx_related_interrupt_handler(dm); + phydm_set_tdma_dig_timer(dm); } - break; - } - default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Wrong type !!\n")); - break; - } + } else + PHYDM_DBG(dm, DBG_DIG, + "Check pass, update pre_tdma_dig_cnt\n"); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_cckpd_level, cck_pd_threshold)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - p_dm_dig_table->pause_cckpd_value[7], p_dm_dig_table->pause_cckpd_value[6], p_dm_dig_table->pause_cckpd_value[5], p_dm_dig_table->pause_cckpd_value[4], - p_dm_dig_table->pause_cckpd_value[3], p_dm_dig_table->pause_cckpd_value[2], p_dm_dig_table->pause_cckpd_value[1], p_dm_dig_table->pause_cckpd_value[0])); -#endif + dig_t->pre_tdma_dig_cnt = dig_t->tdma_dig_cnt; } -#if PHYDM_SUPPORT_CCKPD +/*different IC/team may use different timer for tdma-dig*/ void -odm_cck_packet_detection_thresh( - void *p_dm_void -) +phydm_tdma_dig_add_interrupt_mask_handler( + void *dm_void + ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - u8 cur_cck_cca_thres = p_dm_dig_table->cur_cck_cca_thres, RSSI_thd = 35; -#if (RTL8197F_SUPPORT == 1) - u8 pd_th = 0, cs_ration = 0; -#endif - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* modify by Guo.Mingzhi 2011-12-29 */ - if (p_dm_odm->is_dual_mac_smart_concurrent == true) - return; - - if (p_dm_odm->is_bt_hs_operation) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: 0xcd for BT HS mode!!\n")); - odm_write_cck_cca_thres(p_dm_odm, 0xcd); - return; - } -#endif + struct dm_struct *dm = (struct dm_struct *)dm_void; - if ((!(p_dm_odm->support_ability & ODM_BB_CCK_PD)) || (!(p_dm_odm->support_ability & ODM_BB_FA_CNT))) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: return==========\n")); - #ifdef MCR_WIRELESS_EXTEND - odm_write_cck_cca_thres(p_dm_odm, 0x43); - #endif - return; - } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (p_dm_odm->ext_lna) - return; +#if (DM_ODM_SUPPORT_TYPE == (ODM_AP)) + if (dm->support_ic_type & ODM_RTL8197F) + phydm_add_interrupt_mask_handler(dm, HAL_INT_TYPE_PSTIMEOUT2); /*HAL_INT_TYPE_PSTIMEOUT2*/ +#elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN)) +#elif (DM_ODM_SUPPORT_TYPE == (ODM_CE)) #endif +} - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: ==========>\n")); - - if (p_dm_dig_table->cck_fa_ma == 0xffffffff) - p_dm_dig_table->cck_fa_ma = false_alm_cnt->cnt_cck_fail; - else - p_dm_dig_table->cck_fa_ma = ((p_dm_dig_table->cck_fa_ma << 1) + p_dm_dig_table->cck_fa_ma + false_alm_cnt->cnt_cck_fail) >> 2; +void +phydm_tdma_dig( + void *dm_void + ) +{ + struct dm_struct *dm; + struct phydm_dig_struct *dig_t; + struct phydm_fa_struct *falm_cnt; + u32 reg_c50; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: CCK FA moving average = %d\n", p_dm_dig_table->cck_fa_ma)); - - if (p_dm_odm->is_linked) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - - #if 0 /*for [PCIE-1596]*/ - if (p_dm_odm->rssi_min > (RSSI_thd + 14)) - cur_cck_cca_thres = 0xed; - else if (p_dm_odm->rssi_min > (RSSI_thd + 6)) - cur_cck_cca_thres = 0xdd; + dm = (struct dm_struct *)dm_void; + dig_t = &dm->dm_dig_table; + falm_cnt = &dm->false_alm_cnt; + reg_c50 = odm_get_bb_reg(dm, 0xc50, MASKBYTE0); + + dig_t->tdma_dig_state = + dig_t->tdma_dig_cnt % dm->tdma_dig_state_number; + + PHYDM_DBG(dm, DBG_DIG, + "tdma_dig_state=%d, regc50=0x%x\n", + dig_t->tdma_dig_state, + reg_c50); + + dig_t->tdma_dig_cnt++; + + if (dig_t->tdma_dig_state == 1) { + // update IGI from tdma_dig_state == 0 + if (dig_t->cur_ig_value_tdma == 0) + dig_t->cur_ig_value_tdma = dig_t->cur_ig_value; + + odm_write_dig(dm, dig_t->cur_ig_value_tdma); + phydm_tdma_false_alarm_counter_check(dm); + PHYDM_DBG(dm, DBG_DIG, + "tdma_dig_state=%d, reset FA counter !!!\n", + dig_t->tdma_dig_state); + + } else if (dig_t->tdma_dig_state == 0) { + /* update dig_t->CurIGValue,*/ + /* it may different from dig_t->cur_ig_value_tdma */ + /* TDMA IGI upperbond @ L-state = */ + /* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */ + + if (dig_t->cur_ig_value >= dm->tdma_dig_low_upper_bond) + dig_t->low_ig_value = dm->tdma_dig_low_upper_bond; else - #endif - /*Add hp_hw_id condition due to 22B LPS power consumption issue and [PCIE-1596]*/ - if (p_dm_odm->is_hp_hw_id && (p_dm_odm->traffic_load == TRAFFIC_ULTRA_LOW)) - cur_cck_cca_thres = 0x40; - else { - if (p_dm_odm->rssi_min > RSSI_thd) - cur_cck_cca_thres = 0xcd; - else if (p_dm_odm->rssi_min > 20) { - if (p_dm_dig_table->cck_fa_ma > ((DM_DIG_FA_TH1 >> 1) + (DM_DIG_FA_TH1 >> 3))) - cur_cck_cca_thres = 0xcd; - else if (p_dm_dig_table->cck_fa_ma < (DM_DIG_FA_TH0 >> 1)) - cur_cck_cca_thres = 0x83; - } else if (p_dm_odm->rssi_min > 3) { - if(p_dm_odm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) { /*for ASUS OTA test*/ - if (p_dm_dig_table->cck_fa_ma > 200) - cur_cck_cca_thres = 0xc3; - else - cur_cck_cca_thres = 0x83; - } else if (p_dm_odm->rssi_min > 7) - cur_cck_cca_thres = 0x83; - } else - cur_cck_cca_thres = 0x40; - } - -#else /*ODM_AP*/ - - if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - if ((p_dm_dig_table->cur_ig_value > (0x24 + 14)) || (p_dm_odm->rssi_min > 32)) - cur_cck_cca_thres = 0xed; - else if ((p_dm_dig_table->cur_ig_value > (0x24 + 6)) || (p_dm_odm->rssi_min > 32)) - cur_cck_cca_thres = 0xdd; - else if ((p_dm_dig_table->cur_ig_value > 0x24) || (p_dm_odm->rssi_min > 24 && p_dm_odm->rssi_min <= 30)) - cur_cck_cca_thres = 0xcd; - else if ((p_dm_dig_table->cur_ig_value <= 0x24) || (p_dm_odm->rssi_min < 22)) { - if (p_dm_dig_table->cck_fa_ma > 0x400) - cur_cck_cca_thres = 0x83; - else if (p_dm_dig_table->cck_fa_ma < 0x200) - cur_cck_cca_thres = 0x40; - } - } else { - if (p_dm_dig_table->cur_ig_value > (0x24 + 14)) - cur_cck_cca_thres = 0xed; - else if (p_dm_dig_table->cur_ig_value > (0x24 + 6)) - cur_cck_cca_thres = 0xdd; - else if (p_dm_dig_table->cur_ig_value > 0x24) - cur_cck_cca_thres = 0xcd; - else { - #if 0 - if (p_dm_dig_table->cck_fa_ma > 0x400) - cur_cck_cca_thres = 0x83; - else if (p_dm_dig_table->cck_fa_ma < 0x200) - cur_cck_cca_thres = 0x40; - #else - cur_cck_cca_thres = 0x83; - #endif - } - } - -#endif - } else { - - if (p_dm_dig_table->cck_fa_ma > 0x400) - cur_cck_cca_thres = 0x83; - else if (p_dm_dig_table->cck_fa_ma < 0x200) - cur_cck_cca_thres = 0x40; - } - - #if (RTL8197F_SUPPORT == 1) - /*Add by Yu Chen 20160902, pd_th for 0xa0a, cs_ration for 0xaaa*/ - if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - switch (cur_cck_cca_thres) { - case 0xed: - cs_ration = p_dm_dig_table->aaa_default + AAA_BASE + AAA_STEP*2; - pd_th = 0xd; - break; - - case 0xdd: - cs_ration = p_dm_dig_table->aaa_default + AAA_BASE + AAA_STEP; - pd_th = 0xd; - break; + dig_t->low_ig_value = dig_t->cur_ig_value; - case 0xcd: - cs_ration = p_dm_dig_table->aaa_default + AAA_BASE; - pd_th = 0xd; - break; - - case 0x83: - cs_ration = p_dm_dig_table->aaa_default + AAA_STEP; - pd_th = 0x7; - break; + odm_write_dig(dm, dig_t->low_ig_value); + phydm_tdma_false_alarm_counter_check(dm); + } else + phydm_tdma_false_alarm_counter_check(dm); +} - case 0x40: - cs_ration = p_dm_dig_table->aaa_default; - pd_th = 0x3; - break; +/*============================================================*/ +/*FASLE ALARM CHECK*/ +/*============================================================*/ - default: - cs_ration = p_dm_dig_table->aaa_default; - pd_th = 0x3; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("cck pd use default\n")); - break; +void +phydm_tdma_false_alarm_counter_check( + void *dm_void + ) +{ + struct dm_struct *dm; + struct phydm_fa_struct *falm_cnt; + struct phydm_fa_acc_struct *falm_cnt_acc; + struct phydm_dig_struct *dig_t; + boolean rssi_dump_en = 0; + u32 timestamp; + u8 tdma_dig_state_number; + + dm = (struct dm_struct *)dm_void; + falm_cnt = &dm->false_alm_cnt; + falm_cnt_acc = &dm->false_alm_cnt_acc; + dig_t = &dm->dm_dig_table; + + if (dig_t->tdma_dig_state == 1) + phydm_false_alarm_counter_reset(dm); + /* Reset FalseAlarmCounterStatistics */ + /* fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */ + /* fa_end_tsf = fa_start_tsf = TSF */ + else { + odm_false_alarm_counter_statistics(dm); + if (dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/ + timestamp = odm_get_bb_reg(dm, 0x568, bMaskDWord); + else { + PHYDM_DBG(dm, DBG_DIG, + "Caution! NOT 97F! TDMA-DIG timer does NOT start!!!\n"); + return; } + dig_t->fa_end_timestamp = timestamp; + dig_t->fa_acc_1sec_timestamp += + (dig_t->fa_end_timestamp - dig_t->fa_start_timestamp); + + /*prevent dumb*/ + if (dm->tdma_dig_state_number == 1) + dm->tdma_dig_state_number = 2; + + tdma_dig_state_number = dm->tdma_dig_state_number; + dig_t->sec_factor = + tdma_dig_state_number / (tdma_dig_state_number - 1); + + /*1sec = 1000000us*/ + if (dig_t->fa_acc_1sec_timestamp >= (u32)(1000000 / dig_t->sec_factor)) { + rssi_dump_en = 1; + phydm_false_alarm_counter_acc(dm, rssi_dump_en); + PHYDM_DBG(dm, DBG_DIG, + "sec_factor = %u, total FA = %u, is_linked=%u\n", + dig_t->sec_factor, + falm_cnt_acc->cnt_all, + dm->is_linked); + + phydm_noisy_detection(dm); + phydm_cck_pd_th(dm); + phydm_dig(dm); + phydm_false_alarm_counter_acc_reset(dm); + + /* Reset FalseAlarmCounterStatistics */ + /* fa_end_tsf = fa_start_tsf = TSF, keep */ + /* fa_acc_1sec_tsf = 0 */ + phydm_false_alarm_counter_reset(dm); + } else + phydm_false_alarm_counter_acc(dm, rssi_dump_en); } - #endif /*#if (RTL8197F_SUPPORT == 1)*/ - - #if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - odm_set_bb_reg(p_dm_odm, 0xa08, 0xf0000, pd_th); - odm_set_bb_reg(p_dm_odm, 0xaa8, 0x1f0000, cs_ration); - } else - #endif - { - odm_write_cck_cca_thres(p_dm_odm, cur_cck_cca_thres); - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: cck_cca_th=((0x%x))\n\n", cur_cck_cca_thres)); } -#endif void -odm_write_cck_cca_thres( - void *p_dm_void, - u8 cur_cck_cca_thres -) +phydm_false_alarm_counter_acc( + void *dm_void, + boolean rssi_dump_en + ) { -#if PHYDM_SUPPORT_CCKPD - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - - if (p_dm_dig_table->cur_cck_cca_thres != cur_cck_cca_thres) { /* modify by Guo.Mingzhi 2012-01-03 */ - odm_write_1byte(p_dm_odm, ODM_REG(CCK_CCA, p_dm_odm), cur_cck_cca_thres); - p_dm_dig_table->cck_fa_ma = 0xffffffff; - -#if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8723D) { /* modify by David_Ding for 8723D no Beacon issue */ - if (cur_cck_cca_thres == 0x40) - odm_write_1byte(p_dm_odm, 0xAAA, 0x0C); - else - odm_write_1byte(p_dm_odm, 0xAAA, 0x10); - } -#endif + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt; + struct phydm_fa_acc_struct *falm_cnt_acc; + struct phydm_dig_struct *dig_t; + + falm_cnt = &dm->false_alm_cnt; + falm_cnt_acc = &dm->false_alm_cnt_acc; + dig_t = &dm->dm_dig_table; + + falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail; + falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal; + falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail; + falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail; + falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail; + falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail; + falm_cnt_acc->cnt_all += falm_cnt->cnt_all; + falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync; + falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail; + falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca; + falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca; + falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all; + falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error; + falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok; + falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error; + falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok; + falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error; + falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok; + falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error; + falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok; + falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all; + falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all; + + if (rssi_dump_en == 1) { + falm_cnt_acc->cnt_all_1sec = + falm_cnt_acc->cnt_all * dig_t->sec_factor; + falm_cnt_acc->cnt_cca_all_1sec = + falm_cnt_acc->cnt_cca_all * dig_t->sec_factor; + falm_cnt_acc->cnt_cck_fail_1sec = + falm_cnt_acc->cnt_cck_fail * dig_t->sec_factor; } - p_dm_dig_table->pre_cck_cca_thres = p_dm_dig_table->cur_cck_cca_thres; - p_dm_dig_table->cur_cck_cca_thres = cur_cck_cca_thres; -#endif } -boolean -phydm_dig_go_up_check( - void *p_dm_void -) +void +phydm_false_alarm_counter_acc_reset( + void *dm_void + ) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 cur_ig_value = p_dm_dig_table->cur_ig_value; - u8 max_DIG_cover_bond; - u8 current_igi_max_up_resolution; - u8 rx_gain_range_max; - u8 i = 0; - - u32 total_NHM_cnt; - u32 DIG_cover_cnt; - u32 over_DIG_cover_cnt; -#endif - boolean ret = true; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; - - max_DIG_cover_bond = DM_DIG_MAX_AP - priv->pshare->rf_ft_var.dig_upcheck_initial_value; - current_igi_max_up_resolution = cur_ig_value + 6; - rx_gain_range_max = p_dm_dig_table->rx_gain_range_max; - - phydm_get_nhm_result(p_dm_odm); - - total_NHM_cnt = ccx_info->NHM_result[0] + ccx_info->NHM_result[1]; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): *****Get NHM results*****\n")); - - if (total_NHM_cnt != 0) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_acc_struct *falm_cnt_acc; - /* cur_ig_value < max_DIG_cover_bond - 6 */ - if (p_dm_dig_table->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_0) { - DIG_cover_cnt = ccx_info->NHM_result[1]; - ret = ((priv->pshare->rf_ft_var.dig_level0_ratio_reciprocal * DIG_cover_cnt) >= total_NHM_cnt) ? true : false; - } - - /* (max_DIG_cover_bond - 6) <= cur_ig_value < DM_DIG_MAX_AP */ - else if (p_dm_dig_table->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_1) { - over_DIG_cover_cnt = ccx_info->NHM_result[1]; - ret = (priv->pshare->rf_ft_var.dig_level1_ratio_reciprocal * over_DIG_cover_cnt < total_NHM_cnt) ? true : false; + falm_cnt_acc = &dm->false_alm_cnt_acc; - if (!ret) { - /* update p_dm_dig_table->rx_gain_range_max */ - p_dm_dig_table->rx_gain_range_max = (rx_gain_range_max >= max_DIG_cover_bond - 6) ? (max_DIG_cover_bond - 6) : rx_gain_range_max; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): Noise power is beyond DIG can filter, lock rx_gain_range_max to 0x%x\n", - p_dm_dig_table->rx_gain_range_max)); - } - } + /* Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */ + /* do NOT need to be reset */ + odm_memory_set(dm, falm_cnt_acc, 0, sizeof(falm_cnt_acc)); +} - /* cur_ig_value > DM_DIG_MAX_AP, foolproof */ - else if (p_dm_dig_table->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_2) - ret = true; +void +phydm_false_alarm_counter_reset( + void *dm_void + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt; + struct phydm_dig_struct *dig_t; + u32 timestamp; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): DIG_GoUpCheck_level = %d\n, current_igi_max_up_resolution = 0x%x\n, max_DIG_cover_bond = 0x%x\n, rx_gain_range_max = 0x%x, ret = %d\n", - p_dm_dig_table->dig_go_up_check_level, - current_igi_max_up_resolution, - max_DIG_cover_bond, - p_dm_dig_table->rx_gain_range_max, - ret)); + falm_cnt = &dm->false_alm_cnt; + dig_t = &dm->dm_dig_table; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): NHM_result = %d, %d, %d, %d\n", - ccx_info->NHM_result[0], ccx_info->NHM_result[1], ccx_info->NHM_result[2], ccx_info->NHM_result[3])); + memset(falm_cnt, 0, sizeof(dm->false_alm_cnt)); + phydm_false_alarm_counter_reg_reset(dm); - } else - ret = true; + if (dig_t->tdma_dig_state != 1) + dig_t->fa_acc_1sec_timestamp = 0; + else + dig_t->fa_acc_1sec_timestamp = dig_t->fa_acc_1sec_timestamp; - for (i = 0 ; i <= 10 ; i++) - ccx_info->NHM_th[i] = 0xFF; + /*REG_FREERUN_CNT*/ + timestamp = odm_get_bb_reg(dm, 0x568, bMaskDWord); + dig_t->fa_start_timestamp = timestamp; + dig_t->fa_end_timestamp = timestamp; +} - if (cur_ig_value < max_DIG_cover_bond - 6) { - ccx_info->NHM_th[0] = 2 * (cur_ig_value - priv->pshare->rf_ft_var.dig_upcheck_initial_value); - p_dm_dig_table->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_0; - } else if (cur_ig_value <= DM_DIG_MAX_AP) { - ccx_info->NHM_th[0] = 2 * max_DIG_cover_bond; - p_dm_dig_table->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_1; - } - /* cur_ig_value > DM_DIG_MAX_AP, foolproof */ - else { - p_dm_dig_table->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_2; - ret = true; - } +#endif /*#ifdef PHYDM_TDMA_DIG_SUPPORT*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): *****Set NHM settings*****\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): DIG_GoUpCheck_level = %d\n", - p_dm_dig_table->dig_go_up_check_level)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): NHM_th = 0x%x, 0x%x, 0x%x\n", - ccx_info->NHM_th[0], ccx_info->NHM_th[1], ccx_info->NHM_th[2])); +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT +void +phydm_lna_sat_chk_init( + void *dm_void + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; - ccx_info->nhm_inexclude_cca = NHM_EXCLUDE_CCA; - ccx_info->nhm_inexclude_txon = NHM_EXCLUDE_TXON; - ccx_info->NHM_period = 0xC350; + struct phydm_lna_sat_info_struct *lna_info = &dm->dm_lna_sat_info; - phydm_nhm_setting(p_dm_odm, SET_NHM_SETTING); - phydm_nhm_trigger(p_dm_odm); -#endif + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __FUNCTION__); - return ret; + lna_info->check_time = 0; + lna_info->sat_cnt_acc_patha = 0; + lna_info->sat_cnt_acc_pathb = 0; + lna_info->cur_sat_status = 0; + lna_info->pre_sat_status = 0; + lna_info->cur_timer_check_cnt = 0; + lna_info->pre_timer_check_cnt = 0; } -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -/* <20130108, Kordan> E.g., With LNA used, we make the Rx power smaller to have a better EVM. (Asked by Willis) */ void -odm_rfe_control( - struct PHY_DM_STRUCT *p_dm_odm, - u64 rssi_val +phydm_set_ofdm_agc_tab( + void *dm_void, + u8 tab_sel ) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - static u8 trsw_high_pwr = 0; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> odm_rfe_control, RSSI = %d, trsw_high_pwr = 0x%X, p_dm_odm->rfe_type = %d\n", - rssi_val, trsw_high_pwr, p_dm_odm->rfe_type)); + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->rfe_type == 3) { - - p_dm_odm->RSSI_TRSW = rssi_val; - - if (p_dm_odm->RSSI_TRSW >= p_dm_odm->RSSI_TRSW_H) { - trsw_high_pwr = 1; /* Switch to */ - odm_set_bb_reg(p_dm_odm, REG_ANTSEL_SW_JAGUAR, BIT(1) | BIT0, 0x1); /* Set ANTSW=1/ANTSWB=0 for SW control */ - odm_set_bb_reg(p_dm_odm, REG_ANTSEL_SW_JAGUAR, BIT(9) | BIT8, 0x3); /* Set ANTSW=1/ANTSWB=0 for SW control */ - - } else if (p_dm_odm->RSSI_TRSW <= p_dm_odm->RSSI_TRSW_L) { - trsw_high_pwr = 0; /* Switched back */ - odm_set_bb_reg(p_dm_odm, REG_ANTSEL_SW_JAGUAR, BIT(1) | BIT0, 0x1); /* Set ANTSW=1/ANTSWB=0 for SW control */ - odm_set_bb_reg(p_dm_odm, REG_ANTSEL_SW_JAGUAR, BIT(9) | BIT8, 0x0); /* Set ANTSW=1/ANTSWB=0 for SW control */ - - } - } - - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(p_dm_odm->RSSI_TRSW_H, p_dm_odm->RSSI_TRSW_L) = (%d, %d)\n", p_dm_odm->RSSI_TRSW_H, p_dm_odm->RSSI_TRSW_L)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(rssi_val, rssi_val, p_dm_odm->RSSI_TRSW_iso) = (%d, %d, %d)\n", - rssi_val, p_dm_odm->RSSI_TRSW_iso, p_dm_odm->RSSI_TRSW)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("<=== odm_rfe_control, RSSI = %d, trsw_high_pwr = 0x%X\n", rssi_val, trsw_high_pwr)); + /* table sel:0/2, 1 is used for CCK */ + if (tab_sel == OFDM_AGC_TAB_0) + odm_set_bb_reg(dm, 0xc70, 0x1e00, OFDM_AGC_TAB_0); + else if (tab_sel == OFDM_AGC_TAB_2) + odm_set_bb_reg(dm, 0xc70, 0x1e00, OFDM_AGC_TAB_2); + else + odm_set_bb_reg(dm, 0xc70, 0x1e00, OFDM_AGC_TAB_0); } -void -odm_mpt_dig_work_item_callback( - void *p_context +u8 +phydm_get_ofdm_agc_tab( + void *dm_void ) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_MPT_DIG(p_dm_odm); + return (u1Byte)odm_get_bb_reg(dm, 0xc70, 0x1e00); } void -odm_mpt_dig_callback( - struct timer_list *p_timer -) +phydm_lna_sat_chk( + void *dm_void + ) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_lna_sat_info_struct *lna_info = &dm->dm_lna_sat_info; + + u1Byte igi_rssi_min, rssi_min = dm->rssi_min; + u4Byte sat_status_patha, sat_status_pathb; + u1Byte igi_restore = dig_t->cur_ig_value; + u1Byte i, lna_sat_chk_cnt = dm->lna_sat_chk_cnt; + u4Byte lna_sat_cnt_thd = 0; + u1Byte agc_tab; + u4Byte max_check_time = 0; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __FUNCTION__); + + if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "support ability is disabled, return.\n"); + return; + } + + if (dm->is_disable_lna_sat_chk) { + phydm_lna_sat_chk_init(dm); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "is_disable_lna_sat_chk=%d, return.\n", dm->is_disable_lna_sat_chk); + return; + } + //func_start = ODM_GetBBReg(pDM_Odm, 0x560, bMaskDWord); -#if DEV_BUS_TYPE == RT_PCI_INTERFACE -#if USE_WORKITEM - odm_schedule_work_item(&p_dm_odm->mpt_dig_workitem); -#else - ODM_MPT_DIG(p_dm_odm); -#endif -#else - odm_schedule_work_item(&p_dm_odm->mpt_dig_workitem); -#endif + // move igi to target pin of rssi_min + if ((rssi_min == 0) || (rssi_min == 0xff)) { + // adapt agc table 0 + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0); + phydm_lna_sat_chk_init(dm); + return; + } else if (rssi_min % 2 != 0) + igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI - 1; + else + igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI; + if ((dm->lna_sat_chk_period_ms > 0) && (dm->lna_sat_chk_period_ms <= ONE_SEC_MS)) + max_check_time = lna_sat_chk_cnt*(ONE_SEC_MS/(dm->lna_sat_chk_period_ms))*5; + else + max_check_time = lna_sat_chk_cnt * 5; + + lna_sat_cnt_thd = (max_check_time * dm->lna_sat_chk_duty_cycle)/100; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "check_time=%d, rssi_min=%d, igi_rssi_min=0x%x\nlna_sat_chk_cnt=%d, lna_sat_chk_period_ms=%d, max_check_time=%d, lna_sat_cnt_thd=%d\n", + lna_info->check_time, + rssi_min, + igi_rssi_min, + lna_sat_chk_cnt, + dm->lna_sat_chk_period_ms, + max_check_time, + lna_sat_cnt_thd); + + odm_write_dig(dm, igi_rssi_min); + + // adapt agc table 0 check saturation status + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0); + // open rf power detection ckt & set detection range + odm_set_rf_reg(dm, RF_PATH_A, 0x86, 0x1f, 0x10); + odm_set_rf_reg(dm, RF_PATH_B, 0x86, 0x1f, 0x10); + + // check saturation status + for (i = 0; i < lna_sat_chk_cnt; i++) { + sat_status_patha = odm_get_rf_reg(dm, RF_PATH_A, 0xae, 0xc0000); + sat_status_pathb = odm_get_rf_reg(dm, RF_PATH_B, 0xae, 0xc0000); + if (sat_status_patha != 0) + lna_info->sat_cnt_acc_patha++; + if (sat_status_pathb != 0) + lna_info->sat_cnt_acc_pathb++; + + if ((lna_info->sat_cnt_acc_patha >= lna_sat_cnt_thd) || + (lna_info->sat_cnt_acc_pathb >= lna_sat_cnt_thd)) { + lna_info->cur_sat_status = 1; + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "cur_sat_status=%d, check_time=%d\n", + lna_info->cur_sat_status, + lna_info->check_time); + break; + } else + lna_info->cur_sat_status = 0; + } + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_patha=%d, sat_cnt_acc_pathb=%d\n", + lna_info->cur_sat_status, + lna_info->pre_sat_status, + lna_info->sat_cnt_acc_patha, + lna_info->sat_cnt_acc_pathb); + + // agc table decision + if (lna_info->cur_sat_status) { + if (!dm->is_disable_gain_table_switch) + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2); + lna_info->check_time = 0; + lna_info->sat_cnt_acc_patha = 0; + lna_info->sat_cnt_acc_pathb = 0; + lna_info->pre_sat_status = lna_info->cur_sat_status; + + } else if (lna_info->check_time <= (max_check_time - 1)) { + if (lna_info->pre_sat_status && (!dm->is_disable_gain_table_switch)) + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2); + lna_info->check_time++; + + } else if (lna_info->check_time == max_check_time) { + if (!dm->is_disable_gain_table_switch && (lna_info->pre_sat_status == 1)) + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0); + lna_info->check_time = 0; + lna_info->sat_cnt_acc_patha = 0; + lna_info->sat_cnt_acc_pathb = 0; + lna_info->pre_sat_status = lna_info->cur_sat_status; + } + + agc_tab = phydm_get_ofdm_agc_tab(dm); + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "use AGC tab %d\n", agc_tab); + //func_end = ODM_GetBBReg(pDM_Odm, 0x560, bMaskDWord); + + //PHYDM_DBG(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("function process time=%d\n", + // func_end - func_start)); + + // restore previous igi + odm_write_dig(dm, igi_restore); + lna_info->cur_timer_check_cnt++; + odm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer, dm->lna_sat_chk_period_ms); } -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) void -odm_mpt_dig_callback( - void *p_dm_void -) +phydm_lna_sat_chk_callback( + void *dm_void + + ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -#if USE_WORKITEM - odm_schedule_work_item(&p_dm_odm->mpt_dig_workitem); -#else - ODM_MPT_DIG(p_dm_odm); -#endif + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __FUNCTION__); + phydm_lna_sat_chk(dm); } -#endif -#if (DM_ODM_SUPPORT_TYPE != ODM_CE) void -odm_mpt_write_dig( - void *p_dm_void, - u8 cur_ig_value -) +phydm_lna_sat_chk_timers( + void *dm_void, + u8 state + ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - - odm_write_1byte(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), cur_ig_value); - -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - /* Set IGI value of CCK for new CCK AGC */ - if (p_dm_odm->cck_new_agc) { - if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) - odm_set_bb_reg(p_dm_odm, 0xa0c, 0x00003f00, (cur_ig_value >> 1)); - } - -#endif - - if (p_dm_odm->rf_type > ODM_1T1R) - odm_write_1byte(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), cur_ig_value); - - if ((p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) && (p_dm_odm->rf_type > ODM_2T2R)) { - odm_write_1byte(p_dm_odm, ODM_REG(IGI_C, p_dm_odm), cur_ig_value); - odm_write_1byte(p_dm_odm, ODM_REG(IGI_D, p_dm_odm), cur_ig_value); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_info_struct *lna_info = &dm->dm_lna_sat_info; + + if (state == INIT_LNA_SAT_CHK_TIMMER) { + odm_initialize_timer(dm, + &lna_info->phydm_lna_sat_chk_timer, + (void *)phydm_lna_sat_chk_callback, NULL, + "phydm_lna_sat_chk_timer"); + } else if (state == CANCEL_LNA_SAT_CHK_TIMMER) { + odm_cancel_timer(dm, &lna_info->phydm_lna_sat_chk_timer); + } else if (state == RELEASE_LNA_SAT_CHK_TIMMER) { + odm_release_timer(dm, &lna_info->phydm_lna_sat_chk_timer); } - - p_dm_dig_table->cur_ig_value = cur_ig_value; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("cur_ig_value = 0x%x\n", cur_ig_value)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("p_dm_odm->rf_type = 0x%x\n", p_dm_odm->rf_type)); } void -ODM_MPT_DIG( - void *p_dm_void -) +phydm_lna_sat_chk_watchdog( + void *dm_void + ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - u8 current_igi = p_dm_dig_table->cur_ig_value; - u8 dig_upper = 0x40, dig_lower = 0x20; - u32 rx_ok_cal; - u32 rx_pwdb_ave_final; - u8 IGI_A = 0x20, IGI_B = 0x20; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_info_struct *lna_info = &dm->dm_lna_sat_info; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + u1Byte rssi_min = dm->rssi_min; -#if ODM_FIX_2G_DIG - IGI_A = 0x22; - IGI_B = 0x24; -#endif + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __FUNCTION__); -#else - if (!(*(p_dm_odm->p_mp_mode) && p_dm_odm->priv->pshare->mp_dig_on)) + if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "support ability is disabled, return.\n"); return; + } - if (*p_dm_odm->p_band_type == ODM_BAND_5G) - dig_lower = 0x22; -#endif - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> ODM_MPT_DIG, p_band_type = %d\n", *p_dm_odm->p_band_type)); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "pre_timer_check_cnt=%d, cur_timer_check_cnt=%d\n", + lna_info->pre_timer_check_cnt, + lna_info->cur_timer_check_cnt); -#if (ODM_FIX_2G_DIG || (DM_ODM_SUPPORT_TYPE & ODM_AP)) - if (*p_dm_odm->p_band_type == ODM_BAND_5G || (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) /* for 5G or 8814 */ -#else - if (1) /* for both 2G/5G */ -#endif - { - odm_false_alarm_counter_statistics(p_dm_odm); + if (dm->is_disable_lna_sat_chk) { + phydm_lna_sat_chk_init(dm); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "is_disable_lna_sat_chk=%d, return.\n", dm->is_disable_lna_sat_chk); + return; + } - rx_ok_cal = p_dm_odm->phy_dbg_info.num_qry_phy_status_cck + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm; - rx_pwdb_ave_final = (rx_ok_cal != 0) ? p_dm_odm->rx_pwdb_ave / rx_ok_cal : 0; + if ((dm->support_ic_type & ODM_RTL8197F) == 0) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "SupportICType != ODM_RTL8197F, return.\n"); + return; + } - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; - p_dm_odm->rx_pwdb_ave = 0; - p_dm_odm->MPDIG_2G = false; + if ((rssi_min == 0) || (rssi_min == 0xff)) { + // adapt agc table 0 + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0); + phydm_lna_sat_chk_init(dm); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "rssi_min=%d, return.\n", rssi_min); + return; + } -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_dm_odm->times_2g = 0; -#endif + if (lna_info->cur_timer_check_cnt == lna_info->pre_timer_check_cnt) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Timer check fail, restart timer.\n"); + phydm_lna_sat_chk(dm); + } else { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Timer check pass.\n"); + } + lna_info->pre_timer_check_cnt = lna_info->cur_timer_check_cnt; +} +#endif /*#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("RX OK = %d\n", rx_ok_cal)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("RSSI = %d\n", rx_pwdb_ave_final)); +void +phydm_dig_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + char help[] = "-h"; + char monitor[] = "-m"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + if ((strcmp(input[1], help) == 0)) + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0} fa[0] fa[1] fa[2]\n"); + else if ((strcmp(input[1], monitor) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Read DIG fa_th[0:2]= {%d, %d, %d}\n", + dig_t->fa_th[0], dig_t->fa_th[1], + dig_t->fa_th[2]); - if (rx_ok_cal >= 70 && rx_pwdb_ave_final <= 40) { - if (current_igi > 0x24) - odm_mpt_write_dig(p_dm_odm, 0x24); - } else { - if (p_false_alm_cnt->cnt_all > 1000) - current_igi = current_igi + 8; - else if (p_false_alm_cnt->cnt_all > 200) - current_igi = current_igi + 4; - else if (p_false_alm_cnt->cnt_all > 50) - current_igi = current_igi + 2; - else if (p_false_alm_cnt->cnt_all < 2) - current_igi = current_igi - 2; - - if (current_igi < dig_lower) - current_igi = dig_lower; - - if (current_igi > dig_upper) - current_igi = dig_upper; - - odm_mpt_write_dig(p_dm_odm, current_igi); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG = 0x%x, cnt_all = %d, cnt_ofdm_fail = %d, cnt_cck_fail = %d\n", - current_igi, p_false_alm_cnt->cnt_all, p_false_alm_cnt->cnt_ofdm_fail, p_false_alm_cnt->cnt_cck_fail)); - } } else { - if (p_dm_odm->MPDIG_2G == false) { - if ((p_dm_odm->support_platform & ODM_WIN) && !(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> Fix IGI\n")); - odm_write_1byte(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), IGI_A); - odm_write_1byte(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), IGI_B); - p_dm_dig_table->cur_ig_value = IGI_B; - } else - odm_mpt_write_dig(p_dm_odm, IGI_A); - } + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_dm_odm->times_2g++; - - if (p_dm_odm->times_2g == 3) -#endif - { - p_dm_odm->MPDIG_2G = true; + for (i = 1; i < 10; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); } - } - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - odm_rfe_control(p_dm_odm, rx_pwdb_ave_final); -#endif - odm_set_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer, 700); + if (var1[0] == 0) { + dig_t->is_dbg_fa_th = true; + dig_t->fa_th[0] = (u16)var1[1]; + dig_t->fa_th[1] = (u16)var1[2]; + dig_t->fa_th[2] = (u16)var1[3]; + + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Set DIG fa_th[0:2]= {%d, %d, %d}\n", + dig_t->fa_th[0], dig_t->fa_th[1], + dig_t->fa_th[2]); + } else + dig_t->is_dbg_fa_th = false; + } + *_used = used; + *_out_len = out_len; } -#endif + diff --git a/hal/phydm/phydm_dig.h b/hal/phydm/phydm_dig.h index 77ece7c..553093e 100644 --- a/hal/phydm/phydm_dig.h +++ b/hal/phydm/phydm_dig.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,99 +8,118 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __PHYDMDIG_H__ -#define __PHYDMDIG_H__ +#define __PHYDMDIG_H__ + +/*#define DIG_VERSION "1.4"*/ /* 2017.04.18 YuChen. refine DIG code structure*/ +/*#define DIG_VERSION "2.0"*/ /* 2017.05.09 Dino. Move CCKPD to new files*/ +/*#define DIG_VERSION "2.1"*/ /* 2017.06.01 YuChen. Refine DFS condition*/ +#define DIG_VERSION "2.2" /* 2017.06.13 YuChen. Remove MP dig*/ -#define DIG_VERSION "1.32" /* 2016.09.02 YuChen. add CCK PD for 8197F*/ #define DIG_HW 0 -/* Pause DIG & CCKPD */ -#define DM_DIG_MAX_PAUSE_TYPE 0x7 +/*--------------------Define ---------------------------------------*/ -enum dig_goupcheck_level { +/*=== [DIG Boundary] ========================================*/ +/*DIG coverage mode*/ +#define DIG_MAX_COVERAGR 0x26 +#define DIG_MIN_COVERAGE 0x1c +#define DIG_MAX_OF_MIN_COVERAGE 0x22 +/*DIG performance mode*/ +#if (DIG_HW == 1) +#define DIG_MAX_BALANCE_MODE 0x32 +#else +#define DIG_MAX_BALANCE_MODE 0x3e +#endif +#define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a - DIG_GOUPCHECK_LEVEL_0, - DIG_GOUPCHECK_LEVEL_1, - DIG_GOUPCHECK_LEVEL_2 +#define DIG_MAX_PERFORMANCE_MODE 0x5a +#define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*from 3E -> 2A, refine by YuChen 2017/04/18*/ -}; +#define DIG_MIN_PERFORMANCE 0x20 -struct _dynamic_initial_gain_threshold_ { - boolean is_stop_dig; /* for debug */ - boolean is_ignore_dig; - boolean is_psd_in_progress; +/*DIG DFS function*/ +#define DIG_MAX_DFS 0x28 +#define DIG_MIN_DFS 0x20 - u8 dig_enable_flag; - u8 dig_ext_port_stage; +/*DIG LPS function*/ +#define DIG_MAX_LPS 0x3e +#define DIG_MIN_LPS 0x20 - int rssi_low_thresh; - int rssi_high_thresh; +/*=== [DIG FA Threshold] ======================================*/ - u32 fa_low_thresh; - u32 fa_high_thresh; +/*Normal*/ +#define DM_DIG_FA_TH0 500 +#define DM_DIG_FA_TH1 750 - u8 cur_sta_connect_state; - u8 pre_sta_connect_state; - u8 cur_multi_sta_connect_state; +/*LPS*/ +#define DM_DIG_FA_TH0_LPS 4 /* -> 4 lps */ +#define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */ +#define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */ - u8 pre_ig_value; - u8 cur_ig_value; - u8 backup_ig_value; /* MP DIG */ - u8 bt30_cur_igi; - u8 igi_backup; +#define RSSI_OFFSET_DIG_LPS 5 - s8 backoff_val; - s8 backoff_val_range_max; - s8 backoff_val_range_min; - u8 rx_gain_range_max; - u8 rx_gain_range_min; - u8 rssi_val_min; - -#if PHYDM_SUPPORT_CCKPD - u8 pre_cck_cca_thres; - u8 cur_cck_cca_thres; - u32 cck_fa_ma; - u8 pre_cck_pd_state; - u8 cur_cck_pd_state; - u8 cck_pd_backup; - u8 pause_cckpd_level; - u8 pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1]; -#endif +/*LNA saturation check*/ +#define OFDM_AGC_TAB_0 0 +#define OFDM_AGC_TAB_2 2 +#define DIFF_RSSI_TO_IGI 10 +#define ONE_SEC_MS 1000 - u8 large_fa_hit; - u8 large_fa_timeout; /*if (large_fa_hit), monitor "large_fa_timeout" sec, if timeout, large_fa_hit=0*/ - u8 forbidden_igi; - u32 recover_cnt; +/*--------------------Enum-----------------------------------*/ +enum dig_goupcheck_level { + DIG_GOUPCHECK_LEVEL_0, + DIG_GOUPCHECK_LEVEL_1, + DIG_GOUPCHECK_LEVEL_2 +}; - u8 dig_dynamic_min_0; - u8 dig_dynamic_min_1; - boolean is_media_connect_0; - boolean is_media_connect_1; +enum phydm_dig_mode { + PHYDM_DIG_PERFORAMNCE_MODE = 0, + PHYDM_DIG_COVERAGE_MODE = 1, +}; - u32 ant_div_rssi_max; - u32 RSSI_max; +enum lna_sat_timer_state { + INIT_LNA_SAT_CHK_TIMMER, + CANCEL_LNA_SAT_CHK_TIMMER, + RELEASE_LNA_SAT_CHK_TIMMER +}; +/*--------------------Define Struct-----------------------------------*/ +struct phydm_dig_struct { + boolean is_ignore_dig; /*for old pause function*/ + boolean is_dbg_fa_th; + u8 dig_mode_decision; + u8 cur_ig_value; + u8 rvrt_val; + u8 igi_backup; + u8 rx_gain_range_max; /*dig_dynamic_max*/ + u8 rx_gain_range_min; /*dig_dynamic_min*/ + u8 dm_dig_max; /*Absolutly upper bound*/ + u8 dm_dig_min; /*Absolutly lower bound*/ + u8 dig_max_of_min; /*Absolutly max of min*/ + boolean is_media_connect; + u32 ant_div_rssi_max; u8 *is_p2p_in_process; - - u8 pause_dig_level; - u8 pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1]; - + u8 pause_lv_bitmap; /*bit-map of pause level*/ + u8 pause_dig_value[PHYDM_PAUSE_MAX_NUM]; enum dig_goupcheck_level dig_go_up_check_level; u8 aaa_default; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - boolean is_tp_target; - boolean is_noise_est; - u32 tp_train_th_min; - u8 igi_offset_a; - u8 igi_offset_b; -#endif - + u8 a0a_default; + u16 fa_th[3]; #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) u8 rf_gain_idx; u8 agc_table_idx; @@ -110,17 +129,31 @@ struct _dynamic_initial_gain_threshold_ { u8 big_jump_step2:2; u8 big_jump_step3:2; #endif - -#if (DIG_HW == 1) - u8 pre_rssi_min; -#endif + u8 dig_upcheck_initial_value; + u8 dig_level0_ratio_reciprocal; + u8 dig_level1_ratio_reciprocal; +#ifdef PHYDM_TDMA_DIG_SUPPORT + u8 cur_ig_value_tdma; + u8 low_ig_value; + u8 tdma_dig_state; /*To distinguish which state is now.(L-sate or H-state)*/ + u8 tdma_dig_cnt; /*for phydm_tdma_dig_timer_check use*/ + u8 pre_tdma_dig_cnt; + u8 sec_factor; + u32 cur_timestamp; + u32 pre_timestamp; + u32 fa_start_timestamp; + u32 fa_end_timestamp; + u32 fa_acc_1sec_timestamp; +#endif }; -struct _FALSE_ALARM_STATISTICS { +struct phydm_fa_struct { u32 cnt_parity_fail; u32 cnt_rate_illegal; u32 cnt_crc8_fail; + u32 cnt_crc8_fail_vht; u32 cnt_mcs_fail; + u32 cnt_mcs_fail_vht; u32 cnt_ofdm_fail; u32 cnt_ofdm_fail_pre; /* For RTL8881A */ u32 cnt_cck_fail; @@ -131,8 +164,8 @@ struct _FALSE_ALARM_STATISTICS { u32 cnt_ofdm_cca; u32 cnt_cck_cca; u32 cnt_cca_all; - u32 cnt_bw_usc; /* Gary */ - u32 cnt_bw_lsc; /* Gary */ + u32 cnt_bw_usc; + u32 cnt_bw_lsc; u32 cnt_cck_crc32_error; u32 cnt_cck_crc32_ok; u32 cnt_ofdm_crc32_error; @@ -145,246 +178,186 @@ struct _FALSE_ALARM_STATISTICS { u32 cnt_vht_crc32_ok; u32 cnt_crc32_error_all; u32 cnt_crc32_ok_all; - boolean cck_block_enable; - boolean ofdm_block_enable; + u32 time_fa_all; + boolean cck_block_enable; + boolean ofdm_block_enable; u32 dbg_port0; - boolean edcca_flag; -}; - -enum dm_dig_op_e { - DIG_TYPE_THRESH_HIGH = 0, - DIG_TYPE_THRESH_LOW = 1, - DIG_TYPE_BACKOFF = 2, - DIG_TYPE_RX_GAIN_MIN = 3, - DIG_TYPE_RX_GAIN_MAX = 4, - DIG_TYPE_ENABLE = 5, - DIG_TYPE_DISABLE = 6, - DIG_OP_TYPE_MAX -}; - -/* -enum dm_cck_pdth_e -{ - CCK_PD_STAGE_LowRssi = 0, - CCK_PD_STAGE_HighRssi = 1, - CCK_PD_STAGE_MAX = 3, + boolean edcca_flag; }; -enum dm_dig_ext_port_alg_e -{ - DIG_EXT_PORT_STAGE_0 = 0, - DIG_EXT_PORT_STAGE_1 = 1, - DIG_EXT_PORT_STAGE_2 = 2, - DIG_EXT_PORT_STAGE_3 = 3, - DIG_EXT_PORT_STAGE_MAX = 4, -}; - -enum dm_dig_connect_e -{ - DIG_STA_DISCONNECT = 0, - DIG_STA_CONNECT = 1, - DIG_STA_BEFORE_CONNECT = 2, - dig_multi_sta_disconnect = 3, - dig_multi_sta_connect = 4, - DIG_CONNECT_MAX -}; - - -#define DM_MultiSTA_InitGainChangeNotify(Event) {dm_dig_table.cur_multi_sta_connect_state = Event;} - -#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \ - DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_connect) - -#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \ - DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_disconnect) -*/ - -enum phydm_pause_type { - PHYDM_PAUSE = BIT(0), - PHYDM_RESUME = BIT(1) +#ifdef PHYDM_TDMA_DIG_SUPPORT +struct phydm_fa_acc_struct { + u32 cnt_parity_fail; + u32 cnt_rate_illegal; + u32 cnt_crc8_fail; + u32 cnt_mcs_fail; + u32 cnt_ofdm_fail; + u32 cnt_ofdm_fail_pre; /*For RTL8881A*/ + u32 cnt_cck_fail; + u32 cnt_all; + u32 cnt_all_pre; + u32 cnt_fast_fsync; + u32 cnt_sb_search_fail; + u32 cnt_ofdm_cca; + u32 cnt_cck_cca; + u32 cnt_cca_all; + u32 cnt_cck_crc32_error; + u32 cnt_cck_crc32_ok; + u32 cnt_ofdm_crc32_error; + u32 cnt_ofdm_crc32_ok; + u32 cnt_ht_crc32_error; + u32 cnt_ht_crc32_ok; + u32 cnt_vht_crc32_error; + u32 cnt_vht_crc32_ok; + u32 cnt_crc32_error_all; + u32 cnt_crc32_ok_all; + u32 cnt_all_1sec; + u32 cnt_cca_all_1sec; + u32 cnt_cck_fail_1sec; }; -enum phydm_pause_level { - /* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */ - PHYDM_PAUSE_LEVEL_0 = 0, - PHYDM_PAUSE_LEVEL_1 = 1, - PHYDM_PAUSE_LEVEL_2 = 2, - PHYDM_PAUSE_LEVEL_3 = 3, - PHYDM_PAUSE_LEVEL_4 = 4, - PHYDM_PAUSE_LEVEL_5 = 5, - PHYDM_PAUSE_LEVEL_6 = 6, - PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */ +#endif /*#ifdef PHYDM_TDMA_DIG_SUPPORT*/ + +struct phydm_lna_sat_info_struct { + u32 sat_cnt_acc_patha; + u32 sat_cnt_acc_pathb; + u32 check_time; + boolean pre_sat_status; + boolean cur_sat_status; + struct phydm_timer_list phydm_lna_sat_chk_timer; + u32 cur_timer_check_cnt; + u32 pre_timer_check_cnt; }; -/*CCK PD*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #if (RTL8197F_SUPPORT == 1) - #define AAA_BASE p_dm_odm->priv->pshare->rf_ft_var.dbg_aaa_base /*4*/ - #define AAA_STEP p_dm_odm->priv->pshare->rf_ft_var.dbg_aaa_step /*2*/ - #endif -#endif - -#define DM_DIG_THRESH_HIGH 40 -#define DM_DIG_THRESH_LOW 35 - -#define DM_FALSEALARM_THRESH_LOW 400 -#define DM_FALSEALARM_THRESH_HIGH 1000 - -#define DM_DIG_MAX_NIC 0x3e -#define DM_DIG_MIN_NIC 0x20 -#define DM_DIG_MAX_OF_MIN_NIC 0x3e - -#if (DIG_HW == 1) -#define DM_DIG_MAX_AP p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_upper /* 0x3e */ -#define DM_DIG_MIN_AP ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) ? 0x1c : 0x20)/* 0x1c */ -#else -#define DM_DIG_MAX_AP 0x3e -#define DM_DIG_MIN_AP 0x20 -#endif -#define DM_DIG_MAX_OF_MIN 0x2A /* 0x32 */ -#define DM_DIG_MIN_AP_DFS 0x20 - -#define DM_DIG_MAX_NIC_HP 0x46 -#define DM_DIG_MIN_NIC_HP 0x2e - -#define DM_DIG_MAX_AP_HP 0x42 -#define DM_DIG_MIN_AP_HP 0x30 - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #define DM_DIG_MAX_AP_COVERAGR 0x26 -#if (DIG_HW == 1) - #define DM_DIG_MIN_AP_COVERAGE ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) ? 0x1c : 0x20) -#else - #define DM_DIG_MIN_AP_COVERAGE 0x1c -#endif - #define DM_DIG_MAX_OF_MIN_COVERAGE 0x22 - - #define dm_dig_tp_target_th0 500 - #define dm_dig_tp_target_th1 1000 - #define dm_dig_tp_training_period 10 -#endif - -/* vivi 92c&92d has different definition, 20110504 - * this is for 92c */ -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - #define DM_DIG_FA_TH0 0x80/* 0x20 */ - #else - #define DM_DIG_FA_TH0 0x200/* 0x20 */ - #endif -#else - #define DM_DIG_FA_TH0 0x200/* 0x20 */ -#endif - -#define DM_DIG_FA_TH1 0x300 -#define DM_DIG_FA_TH2 0x400 -/* this is for 92d */ -#define DM_DIG_FA_TH0_92D 0x100 -#define DM_DIG_FA_TH1_92D 0x400 -#define DM_DIG_FA_TH2_92D 0x600 - -#define DM_DIG_BACKOFF_MAX 12 -#define DM_DIG_BACKOFF_MIN -4 -#define DM_DIG_BACKOFF_DEFAULT 10 - -#define DM_DIG_FA_TH0_LPS 4 /* -> 4 in lps */ -#define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */ -#define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */ -#define RSSI_OFFSET_DIG 0x05 -#define LARGE_FA_TIMEOUT 60 - - +/*--------------------Function declaration-----------------------------*/ void -odm_change_dynamic_init_gain_thresh( - void *p_dm_void, - u32 dm_type, - u32 dm_value +odm_write_dig( + void *dm_void, + u8 current_igi ); void -odm_write_dig( - void *p_dm_void, - u8 current_igi +phydm_set_dig_val( + void *dm_void, + u32 *val_buf, + u8 val_len ); void odm_pause_dig( - void *p_dm_void, + void *dm_void, enum phydm_pause_type pause_type, enum phydm_pause_level pause_level, u8 igi_value ); void -odm_dig_init( - void *p_dm_void +phydm_dig_init( + void *dm_void ); void -odm_DIG( - void *p_dm_void +phydm_dig( + void *dm_void ); void -odm_dig_by_rssi_lps( - void *p_dm_void +phydm_dig_lps_32k( + void *dm_void +); + +void +phydm_dig_by_rssi_lps( + void *dm_void ); void odm_false_alarm_counter_statistics( - void *p_dm_void + void *dm_void ); +#ifdef PHYDM_TDMA_DIG_SUPPORT void -odm_pause_cck_packet_detection( - void *p_dm_void, - enum phydm_pause_type pause_type, - enum phydm_pause_level pause_level, - u8 cck_pd_threshold +phydm_set_tdma_dig_timer( + void *dm_void ); void -odm_cck_packet_detection_thresh( - void *p_dm_void +phydm_tdma_dig_timer_check( + void *dm_void ); void -odm_write_cck_cca_thres( - void *p_dm_void, - u8 cur_cck_cca_thres +phydm_tdma_dig( + void *dm_void ); -boolean -phydm_dig_go_up_check( - void *p_dm_void +void +phydm_tdma_false_alarm_counter_check( + void *dm_void ); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void -odm_mpt_dig_callback( - struct timer_list *p_timer +phydm_tdma_dig_add_interrupt_mask_handler( + void *dm_void ); void -odm_mpt_dig_work_item_callback( - void *p_context +phydm_false_alarm_counter_reset( + void *dm_void ); -#endif +void +phydm_false_alarm_counter_acc( + void *dm_void, + boolean rssi_dump_en + ); + +void +phydm_false_alarm_counter_acc_reset( + void *dm_void + ); + +#endif /*#ifdef PHYDM_TDMA_DIG_SUPPORT*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) void -odm_mpt_dig_callback( - void *p_dm_void +phydm_set_ofdm_agc_tab( + void *dm_void, + u8 tab_sel +); + +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT +u8 +phydm_get_ofdm_agc_tab( + void *dm_void ); -#endif -#if (DM_ODM_SUPPORT_TYPE != ODM_CE) void -ODM_MPT_DIG( - void *p_dm_void +phydm_lna_sat_chk( + void *dm_void ); -#endif +void +phydm_lna_sat_chk_timers( + void *dm_void, + u8 state +); + +void +phydm_lna_sat_chk_watchdog( + void *dm_void +); + +#endif /*#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/ + +void +phydm_dig_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); #endif diff --git a/hal/phydm/phydm_dynamic_rx_path.c b/hal/phydm/phydm_dynamic_rx_path.c index ed32eed..b5b90b0 100644 --- a/hal/phydm/phydm_dynamic_rx_path.c +++ b/hal/phydm/phydm_dynamic_rx_path.c @@ -19,94 +19,90 @@ #include "mp_precomp.h" #include "phydm_precomp.h" -#if (CONFIG_DYNAMIC_RX_PATH == 1) +#ifdef CONFIG_DYNAMIC_RX_PATH void phydm_process_phy_status_for_dynamic_rx_path( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void + void *dm_void, + void *phy_info_void, + void *pkt_info_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; - struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; - struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); - /*u8 is_cck_rate=0;*/ - - - + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table); } void phydm_drp_get_statistic( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table); + struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT); - odm_false_alarm_counter_statistics(p_dm_odm); + odm_false_alarm_counter_statistics(dm); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all)); + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all)); + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all); } void phydm_dynamic_rx_path( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table); u8 training_set_timmer_en; u8 curr_drp_state; u32 rx_ok_cal; u32 RSSI = 0; - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT); - if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Return Init] Not Support Dynamic RX PAth\n")); + if (!(dm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) { + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Return Init] Not Support Dynamic RX PAth\n"); return; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("Current drp_state = ((%d))\n", p_dm_drp_table->drp_state)); + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "Current drp_state = ((%d))\n", p_dm_drp_table->drp_state); curr_drp_state = p_dm_drp_table->drp_state; if (p_dm_drp_table->drp_state == DRP_INIT_STATE) { - phydm_drp_get_statistic(p_dm_odm); + phydm_drp_get_statistic(dm); - if (false_alm_cnt->cnt_crc32_ok_all > 20) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Stop DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all)); + if (false_alm_cnt->cnt_crc32_ok_all > 20) { /*Signal + Interference*/ + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Stop DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all); p_dm_drp_table->drp_state = DRP_INIT_STATE; training_set_timmer_en = false; - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Start DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all)); + } else {/*Interference only*/ + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Start DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all); p_dm_drp_table->drp_state = DRP_TRAINING_STATE_0; - p_dm_drp_table->curr_rx_path = PHYDM_AB; + p_dm_drp_table->curr_rx_path = BB_PATH_AB; training_set_timmer_en = true; } } else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_0) { - phydm_drp_get_statistic(p_dm_odm); + phydm_drp_get_statistic(dm); p_dm_drp_table->curr_cca_all_cnt_0 = false_alm_cnt->cnt_cca_all; p_dm_drp_table->curr_fa_all_cnt_0 = false_alm_cnt->cnt_all; p_dm_drp_table->drp_state = DRP_TRAINING_STATE_1; - p_dm_drp_table->curr_rx_path = PHYDM_B; + p_dm_drp_table->curr_rx_path = BB_PATH_B; training_set_timmer_en = true; } else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_1) { - phydm_drp_get_statistic(p_dm_odm); + phydm_drp_get_statistic(dm); p_dm_drp_table->curr_cca_all_cnt_1 = false_alm_cnt->cnt_cca_all; p_dm_drp_table->curr_fa_all_cnt_1 = false_alm_cnt->cnt_all; @@ -115,10 +111,10 @@ phydm_dynamic_rx_path( p_dm_drp_table->drp_state = DRP_DECISION_STATE; #else - if (*(p_dm_odm->p_mp_mode)) { - rx_ok_cal = p_dm_odm->phy_dbg_info.num_qry_phy_status_cck + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm; - RSSI = (rx_ok_cal != 0) ? p_dm_odm->rx_pwdb_ave / rx_ok_cal : 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("MP RSSI = ((%d))\n", RSSI)); + if (*(dm->mp_mode)) { + rx_ok_cal = dm->phy_dbg_info.num_qry_phy_status_cck + dm->phy_dbg_info.num_qry_phy_status_ofdm; + RSSI = (rx_ok_cal != 0) ? dm->rx_pwdb_ave / rx_ok_cal : 0; + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "MP RSSI = ((%d))\n", RSSI); } if (RSSI > p_dm_drp_table->rssi_threshold) @@ -128,13 +124,13 @@ phydm_dynamic_rx_path( else { p_dm_drp_table->drp_state = DRP_TRAINING_STATE_2; - p_dm_drp_table->curr_rx_path = PHYDM_A; + p_dm_drp_table->curr_rx_path = BB_PATH_A; training_set_timmer_en = true; } #endif } else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_2) { - phydm_drp_get_statistic(p_dm_odm); + phydm_drp_get_statistic(dm); p_dm_drp_table->curr_cca_all_cnt_2 = false_alm_cnt->cnt_cca_all; p_dm_drp_table->curr_fa_all_cnt_2 = false_alm_cnt->cnt_all; @@ -143,53 +139,53 @@ phydm_dynamic_rx_path( if (p_dm_drp_table->drp_state == DRP_DECISION_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("Current drp_state = ((%d))\n", p_dm_drp_table->drp_state)); + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "Current drp_state = ((%d))\n", p_dm_drp_table->drp_state); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[0] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_0, p_dm_drp_table->curr_fa_all_cnt_0)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[1] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_1, p_dm_drp_table->curr_fa_all_cnt_1)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[2] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_2, p_dm_drp_table->curr_fa_all_cnt_2)); + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[0] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_0, p_dm_drp_table->curr_fa_all_cnt_0); + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[1] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_1, p_dm_drp_table->curr_fa_all_cnt_1); + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[2] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_2, p_dm_drp_table->curr_fa_all_cnt_2); if (p_dm_drp_table->curr_fa_all_cnt_1 < p_dm_drp_table->curr_fa_all_cnt_0) { if ((p_dm_drp_table->curr_fa_all_cnt_0 - p_dm_drp_table->curr_fa_all_cnt_1) > p_dm_drp_table->fa_diff_threshold) - p_dm_drp_table->curr_rx_path = PHYDM_B; + p_dm_drp_table->curr_rx_path = BB_PATH_B; else - p_dm_drp_table->curr_rx_path = PHYDM_AB; + p_dm_drp_table->curr_rx_path = BB_PATH_AB; } else - p_dm_drp_table->curr_rx_path = PHYDM_AB; + p_dm_drp_table->curr_rx_path = BB_PATH_AB; - phydm_config_ofdm_rx_path(p_dm_odm, p_dm_drp_table->curr_rx_path); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Training Result] curr_rx_path = ((%s%s)),\n", - ((p_dm_drp_table->curr_rx_path & PHYDM_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & PHYDM_B) ? "B" : " "))); + phydm_config_ofdm_rx_path(dm, p_dm_drp_table->curr_rx_path); + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Training Result] curr_rx_path = ((%s%s)),\n", + ((p_dm_drp_table->curr_rx_path & BB_PATH_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & BB_PATH_B) ? "B" : " ")); p_dm_drp_table->drp_state = DRP_INIT_STATE; training_set_timmer_en = false; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("DRP_state: ((%d)) -> ((%d))\n", curr_drp_state, p_dm_drp_table->drp_state)); + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "DRP_state: ((%d)) -> ((%d))\n", curr_drp_state, p_dm_drp_table->drp_state); if (training_set_timmer_en) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Training en] curr_rx_path = ((%s%s)), training_time = ((%d ms))\n", - ((p_dm_drp_table->curr_rx_path & PHYDM_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & PHYDM_B) ? "B" : " "), p_dm_drp_table->training_time)); + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Training en] curr_rx_path = ((%s%s)), training_time = ((%d ms))\n", + ((p_dm_drp_table->curr_rx_path & BB_PATH_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & BB_PATH_B) ? "B" : " "), p_dm_drp_table->training_time); - phydm_config_ofdm_rx_path(p_dm_odm, p_dm_drp_table->curr_rx_path); - odm_set_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer), p_dm_drp_table->training_time); /*ms*/ + phydm_config_ofdm_rx_path(dm, p_dm_drp_table->curr_rx_path); + odm_set_timer(dm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer), p_dm_drp_table->training_time); /*ms*/ } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("DRP period end\n\n", curr_drp_state, p_dm_drp_table->drp_state)); + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "DRP period end\n\n", curr_drp_state, p_dm_drp_table->drp_state); } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void phydm_dynamic_rx_path_callback( - struct timer_list *p_timer + struct phydm_timer_list *timer ) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &(p_hal_data->DM_OutSrc); - struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + void *adapter = (void *)timer->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &(hal_data->DM_OutSrc); + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table); #if DEV_BUS_TYPE == RT_PCI_INTERFACE #if USE_WORKITEM @@ -197,7 +193,7 @@ phydm_dynamic_rx_path_callback( #else { /* dbg_print("phydm_dynamic_rx_path\n"); */ - phydm_dynamic_rx_path(p_dm_odm); + phydm_dynamic_rx_path(dm); } #endif #else @@ -207,15 +203,15 @@ phydm_dynamic_rx_path_callback( void phydm_dynamic_rx_path_workitem_callback( - void *p_context + void *context ) { - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &(p_hal_data->DM_OutSrc); + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &(hal_data->DM_OutSrc); /* dbg_print("phydm_dynamic_rx_path\n"); */ - phydm_dynamic_rx_path(p_dm_odm); + phydm_dynamic_rx_path(dm); } #else if (DM_ODM_SUPPORT_TYPE == ODM_CE) @@ -224,14 +220,14 @@ phydm_dynamic_rx_path_callback( void *function_context ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)function_context; - struct _ADAPTER *padapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)function_context; + void *padapter = dm->adapter; - if (padapter->net_closed == _TRUE) + if (*(dm->is_net_closed) == true) return; #if 0 /* Can't do I/O in timer callback*/ - odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_DETERMINE); + odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE); #else /*rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter);*/ #endif @@ -241,41 +237,41 @@ phydm_dynamic_rx_path_callback( void phydm_dynamic_rx_path_timers( - void *p_dm_void, + void *dm_void, u8 state ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table); if (state == INIT_DRP_TIMMER) { - odm_initialize_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer), + odm_initialize_timer(dm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer), (void *)phydm_dynamic_rx_path_callback, NULL, "phydm_sw_antenna_switch_timer"); } else if (state == CANCEL_DRP_TIMMER) - odm_cancel_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer)); + odm_cancel_timer(dm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer)); else if (state == RELEASE_DRP_TIMMER) - odm_release_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer)); + odm_release_timer(dm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer)); } void phydm_dynamic_rx_path_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table); boolean ret_value; - if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Return] Not Support Dynamic RX PAth\n")); + if (!(dm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) { + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Return] Not Support Dynamic RX PAth\n"); return; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("phydm_dynamic_rx_path_init\n")); + PHYDM_DBG(dm, DBG_DYN_RX_PATH, "phydm_dynamic_rx_path_init\n"); p_dm_drp_table->drp_state = DRP_INIT_STATE; p_dm_drp_table->rssi_threshold = DRP_RSSI_TH; @@ -286,23 +282,23 @@ phydm_dynamic_rx_path_init( p_dm_drp_table->drp_period = 0; p_dm_drp_table->drp_init_finished = true; - ret_value = phydm_api_trx_mode(p_dm_odm, (enum odm_rf_path_e)(ODM_RF_A | ODM_RF_B), (enum odm_rf_path_e)(ODM_RF_A | ODM_RF_B), true); + ret_value = phydm_api_trx_mode(dm, (enum bb_path)BB_PATH_AB, (enum bb_path)BB_PATH_AB, true); } void phydm_drp_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, - char *output, + char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 used = *_used; u32 out_len = *_out_len; - struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table); switch (dm_value[0]) { @@ -322,18 +318,22 @@ phydm_drp_debug( p_dm_drp_table->fa_diff_threshold = dm_value[1]; break; default: - PHYDM_SNPRINTF((output + used, out_len - used, "[DRP] unknown command\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[DRP] unknown command\n"); break; -} + } + + *_used = used; + *_out_len = out_len; } void phydm_dynamic_rx_path_caller( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table); if (p_dm_drp_table->drp_skip_counter < p_dm_drp_table->drp_period) p_dm_drp_table->drp_skip_counter++; @@ -346,7 +346,7 @@ phydm_dynamic_rx_path_caller( if (p_dm_drp_table->drp_init_finished != true) return; - phydm_dynamic_rx_path(p_dm_odm); + phydm_dynamic_rx_path(dm); } #endif diff --git a/hal/phydm/phydm_dynamic_rx_path.h b/hal/phydm/phydm_dynamic_rx_path.h index fa9e794..4d0b142 100644 --- a/hal/phydm/phydm_dynamic_rx_path.h +++ b/hal/phydm/phydm_dynamic_rx_path.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __PHYDMDYMICRXPATH_H__ @@ -26,17 +36,17 @@ #define RELEASE_DRP_TIMMER 2 #if (RTL8822B_SUPPORT == 1) -struct phydm_rtl8822b_struct { - enum odm_rf_path_e path_judge; +struct drp_rtl8822b_struct { + enum bb_path path_judge; u16 path_a_cck_fa; u16 path_b_cck_fa; }; #endif -#if (CONFIG_DYNAMIC_RX_PATH == 1) +#ifdef CONFIG_DYNAMIC_RX_PATH -enum drp_state_e { +enum drp_state { DRP_INIT_STATE = 0, DRP_TRAINING_STATE_0 = 1, DRP_TRAINING_STATE_1 = 2, @@ -44,7 +54,7 @@ enum drp_state_e { DRP_DECISION_STATE = 4 }; -enum adjustable_value_e { +enum adjustable_value { DRP_TRAINING_TIME = 0, DRP_TRAINING_PERIOD = 1, DRP_RSSI_THRESHOLD = 2, @@ -74,7 +84,7 @@ struct _DYNAMIC_RX_PATH_ { RT_WORK_ITEM phydm_dynamic_rx_path_workitem; #endif #endif - struct timer_list phydm_dynamic_rx_path_timer; + struct phydm_timer_list phydm_dynamic_rx_path_timer; }; @@ -82,25 +92,25 @@ struct _DYNAMIC_RX_PATH_ { void phydm_process_phy_status_for_dynamic_rx_path( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void + void *dm_void, + void *phy_info_void, + void *pkt_info_void ); void phydm_dynamic_rx_path( - void *p_dm_void + void *dm_void ); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void phydm_dynamic_rx_path_callback( - struct timer_list *p_timer + struct phydm_timer_list *timer ); void phydm_dynamic_rx_path_workitem_callback( - void *p_context + void *context ); #else if (DM_ODM_SUPPORT_TYPE == ODM_CE) @@ -114,18 +124,18 @@ phydm_dynamic_rx_path_callback( void phydm_dynamic_rx_path_timers( - void *p_dm_void, + void *dm_void, u8 state ); void phydm_dynamic_rx_path_init( - void *p_dm_void + void *dm_void ); void phydm_drp_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, char *output, @@ -134,7 +144,7 @@ phydm_drp_debug( void phydm_dynamic_rx_path_caller( - void *p_dm_void + void *dm_void ); #endif diff --git a/hal/phydm/phydm_dynamicbbpowersaving.c b/hal/phydm/phydm_dynamicbbpowersaving.c deleted file mode 100644 index fc2ec27..0000000 --- a/hal/phydm/phydm_dynamicbbpowersaving.c +++ /dev/null @@ -1,106 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -/* ************************************************************ - * include files - * ************************************************************ */ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#if (defined(CONFIG_BB_POWER_SAVING)) - -void -odm_dynamic_bb_power_saving_init( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_power_saving *p_dm_ps_table = &p_dm_odm->dm_ps_table; - - p_dm_ps_table->pre_cca_state = CCA_MAX; - p_dm_ps_table->cur_cca_state = CCA_MAX; - p_dm_ps_table->pre_rf_state = RF_MAX; - p_dm_ps_table->cur_rf_state = RF_MAX; - p_dm_ps_table->rssi_val_min = 0; - p_dm_ps_table->initialize = 0; -} - -void -odm_rf_saving( - void *p_dm_void, - u8 is_force_in_normal -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - struct _dynamic_power_saving *p_dm_ps_table = &p_dm_odm->dm_ps_table; - u8 rssi_up_bound = 30 ; - u8 rssi_low_bound = 25; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (p_dm_odm->patch_id == 40) { /* RT_CID_819x_FUNAI_TV */ - rssi_up_bound = 50 ; - rssi_low_bound = 45; - } -#endif - if (p_dm_ps_table->initialize == 0) { - - p_dm_ps_table->reg874 = (odm_get_bb_reg(p_dm_odm, 0x874, MASKDWORD) & 0x1CC000) >> 14; - p_dm_ps_table->regc70 = (odm_get_bb_reg(p_dm_odm, 0xc70, MASKDWORD) & BIT(3)) >> 3; - p_dm_ps_table->reg85c = (odm_get_bb_reg(p_dm_odm, 0x85c, MASKDWORD) & 0xFF000000) >> 24; - p_dm_ps_table->rega74 = (odm_get_bb_reg(p_dm_odm, 0xa74, MASKDWORD) & 0xF000) >> 12; - /* Reg818 = phy_query_bb_reg(p_adapter, 0x818, MASKDWORD); */ - p_dm_ps_table->initialize = 1; - } - - if (!is_force_in_normal) { - if (p_dm_odm->rssi_min != 0xFF) { - if (p_dm_ps_table->pre_rf_state == rf_normal) { - if (p_dm_odm->rssi_min >= rssi_up_bound) - p_dm_ps_table->cur_rf_state = rf_save; - else - p_dm_ps_table->cur_rf_state = rf_normal; - } else { - if (p_dm_odm->rssi_min <= rssi_low_bound) - p_dm_ps_table->cur_rf_state = rf_normal; - else - p_dm_ps_table->cur_rf_state = rf_save; - } - } else - p_dm_ps_table->cur_rf_state = RF_MAX; - } else - p_dm_ps_table->cur_rf_state = rf_normal; - - if (p_dm_ps_table->pre_rf_state != p_dm_ps_table->cur_rf_state) { - if (p_dm_ps_table->cur_rf_state == rf_save) { - odm_set_bb_reg(p_dm_odm, 0x874, 0x1C0000, 0x2); /* reg874[20:18]=3'b010 */ - odm_set_bb_reg(p_dm_odm, 0xc70, BIT(3), 0); /* regc70[3]=1'b0 */ - odm_set_bb_reg(p_dm_odm, 0x85c, 0xFF000000, 0x63); /* reg85c[31:24]=0x63 */ - odm_set_bb_reg(p_dm_odm, 0x874, 0xC000, 0x2); /* reg874[15:14]=2'b10 */ - odm_set_bb_reg(p_dm_odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ - odm_set_bb_reg(p_dm_odm, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */ - odm_set_bb_reg(p_dm_odm, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */ - } else { - odm_set_bb_reg(p_dm_odm, 0x874, 0x1CC000, p_dm_ps_table->reg874); - odm_set_bb_reg(p_dm_odm, 0xc70, BIT(3), p_dm_ps_table->regc70); - odm_set_bb_reg(p_dm_odm, 0x85c, 0xFF000000, p_dm_ps_table->reg85c); - odm_set_bb_reg(p_dm_odm, 0xa74, 0xF000, p_dm_ps_table->rega74); - odm_set_bb_reg(p_dm_odm, 0x818, BIT(28), 0x0); - } - p_dm_ps_table->pre_rf_state = p_dm_ps_table->cur_rf_state; - } -#endif -} - -#endif diff --git a/hal/phydm/phydm_dynamicbbpowersaving.h b/hal/phydm/phydm_dynamicbbpowersaving.h deleted file mode 100644 index 0c4a236..0000000 --- a/hal/phydm/phydm_dynamicbbpowersaving.h +++ /dev/null @@ -1,52 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ - -#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__ -#define __PHYDMDYNAMICBBPOWERSAVING_H__ - -#define DYNAMIC_BBPWRSAV_VERSION "1.1" - -#if (defined(CONFIG_BB_POWER_SAVING)) - -struct _dynamic_power_saving { - u8 pre_cca_state; - u8 cur_cca_state; - - u8 pre_rf_state; - u8 cur_rf_state; - - int rssi_val_min; - - u8 initialize; - u32 reg874, regc70, reg85c, rega74; - -}; - -#define dm_rf_saving odm_rf_saving - -void odm_rf_saving( - void *p_dm_void, - u8 is_force_in_normal -); - -void -odm_dynamic_bb_power_saving_init( - void *p_dm_void -); -#else -#define dm_rf_saving(p_dm_void, is_force_in_normal) -#endif - -#endif diff --git a/hal/phydm/phydm_dynamictxpower.c b/hal/phydm/phydm_dynamictxpower.c index 3474fa6..1b68fc6 100644 --- a/hal/phydm/phydm_dynamictxpower.c +++ b/hal/phydm/phydm_dynamictxpower.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -19,67 +29,45 @@ #include "mp_precomp.h" #include "phydm_precomp.h" -void -odm_dynamic_tx_power_init( - void *p_dm_void +/* *********************Power training init************************ */ +void phydm_pow_train_init( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - - /*if (!IS_HARDWARE_TYPE_8814A(adapter)) {*/ - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, */ - /* ("odm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->is_dynamic_tx_power_enable));*/ - /* return;*/ - /*} else*/ - { - p_mgnt_info->bDynamicTxPowerEnable = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, - ("odm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->bDynamicTxPowerEnable)); + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + /* This is for power training init @ 11N serious */ + #if DEV_BUS_TYPE == RT_USB_INTERFACE + if (RT_GetInterfaceSelection((PADAPTER)adapter) == INTF_SEL1_USB_High_Power) { + odm_dynamic_tx_power_save_power_index(dm); } + #else -#if DEV_BUS_TYPE == RT_USB_INTERFACE - if (RT_GetInterfaceSelection(adapter) == INTF_SEL1_USB_High_Power) { - odm_dynamic_tx_power_save_power_index(p_dm_odm); - p_mgnt_info->bDynamicTxPowerEnable = true; - } else -#else - /* so 92c pci do not need dynamic tx power? vivi check it later */ - p_mgnt_info->bDynamicTxPowerEnable = false; -#endif - - - p_hal_data->LastDTPLvl = tx_high_pwr_level_normal; - p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - p_dm_odm->last_dtp_lvl = tx_high_pwr_level_normal; - p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal; - p_dm_odm->tx_agc_ofdm_18_6 = odm_get_bb_reg(p_dm_odm, 0xC24, MASKDWORD); /*TXAGC {18M 12M 9M 6M}*/ - + /* so 92c pci do not need dynamic tx power? vivi check it later */ + #endif #endif } void odm_dynamic_tx_power_save_power_index( - void *p_dm_void + void *dm_void ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 index; u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + /* Save PT index, but nothing used?? */ + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); for (index = 0; index < 6; index++) - p_hal_data->PowerIndex_backup[index] = PlatformEFIORead1Byte(adapter, power_index_reg[index]); + hal_data->PowerIndex_backup[index] = PlatformEFIORead1Byte((PADAPTER)adapter, power_index_reg[index]); #endif @@ -88,18 +76,18 @@ odm_dynamic_tx_power_save_power_index( void odm_dynamic_tx_power_restore_power_index( - void *p_dm_void + void *dm_void ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 index; - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; for (index = 0; index < 6; index++) - PlatformEFIOWrite1Byte(adapter, power_index_reg[index], p_hal_data->PowerIndex_backup[index]); + PlatformEFIOWrite1Byte(adapter, power_index_reg[index], hal_data->PowerIndex_backup[index]); @@ -108,78 +96,330 @@ odm_dynamic_tx_power_restore_power_index( void odm_dynamic_tx_power_write_power_index( - void *p_dm_void, + void *dm_void, u8 value) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 index; u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; for (index = 0; index < 6; index++) /* platform_efio_write_1byte(adapter, power_index_reg[index], value); */ - odm_write_1byte(p_dm_odm, power_index_reg[index], value); + odm_write_1byte(dm, power_index_reg[index], value); + +} + +/* ************************************************************ */ + +#ifdef CONFIG_DYNAMIC_TX_TWR + +boolean +phydm_check_rates( + void *dm_void, + u8 rate_idx +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 check_rate_bitmap0 = 0x08080808; /* check CCK11M, OFDM54M, MCS7, MCS15*/ + u32 check_rate_bitmap1 = 0x80200808; /* check MCS23, MCS31, VHT1SS M9, VHT2SS M9*/ + u32 check_rate_bitmap2 = 0x00080200; /* check VHT3SS M9, VHT4SS M9*/ + u32 bitmap_result; + +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8822B) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0xfffff000; + check_rate_bitmap0 &= 0x0fffffff; + } +#endif + + +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8197F) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0; + check_rate_bitmap0 &= 0x0fffffff; + } +#endif + +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821C) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0x003ff000; + check_rate_bitmap0 &= 0x000fffff; + } +#endif + + + if (rate_idx >= 64) + bitmap_result = BIT(rate_idx-64) & check_rate_bitmap2; + else if (rate_idx >= 32) + bitmap_result = BIT(rate_idx-32) & check_rate_bitmap1; + else if (rate_idx <= 31) + bitmap_result = BIT(rate_idx) & check_rate_bitmap0; + + if (bitmap_result!=0) + return true; + else + return false; +} + +enum rf_path +phydm_check_paths( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum rf_path max_path; +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8822B) + max_path = RF_PATH_B; +#endif + + +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8197F) + max_path = RF_PATH_B; +#endif + +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821C) + max_path = RF_PATH_A; +#endif + return max_path; +} + +u8 +phydm_search_min_power_index( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum rf_path path; + enum rf_path max_path; + u8 min_gain_index = 0x3f; + u8 gain_index; + u8 rate_idx; + + PHYDM_DBG(dm, DBG_DYN_TXPWR, "phydm_search_min_power_index\n"); + max_path = phydm_check_paths(dm); + for (path = 0; path <= max_path; path++) + for (rate_idx = 0; rate_idx < 84; rate_idx++) + if (phydm_check_rates(dm, rate_idx)) { + gain_index = phydm_api_get_txagc(dm, path, rate_idx); + PHYDM_DBG(dm, DBG_DYN_TXPWR, "Support Rate: ((%d)) -> Gain index: ((%d))\n", rate_idx, gain_index); + if (gain_index < min_gain_index) + min_gain_index = gain_index; + } + + return min_gain_index; +} + + +void +phydm_dynamic_tx_power_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + dm->last_dtp_lvl = tx_high_pwr_level_normal; + dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal; + dm->min_power_index = phydm_search_min_power_index(dm); + PHYDM_DBG(dm, DBG_DYN_TXPWR, "DTP init: Min Gain index: ((%d))\n", dm->min_power_index); +} + +u8 +phydm_pwr_lvl_check( + void *dm_void, + u8 input_rssi +) +{ + if (input_rssi >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { + return tx_high_pwr_level_level2; + /**/ + } else if (input_rssi >= TX_POWER_NEAR_FIELD_THRESH_LVL1) { + return tx_high_pwr_level_level1; + /**/ + } else if (input_rssi < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { + return tx_high_pwr_level_normal; + /**/ + } + else { + return tx_high_pwr_level_normal; + } +} + +void +phydm_dynamic_response_power( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 now_pwr_lvl; + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; + if (dm->last_dtp_lvl != dm->dynamic_tx_high_power_lvl) { + PHYDM_DBG(dm, DBG_DYN_TXPWR, "Response Power update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl, dm->dynamic_tx_high_power_lvl); + dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl; + now_pwr_lvl = dm->dynamic_tx_high_power_lvl; + if (now_pwr_lvl == tx_high_pwr_level_level2 || now_pwr_lvl == tx_high_pwr_level_level1) { + odm_set_mac_reg(dm, 0x6D8, BIT(20) | BIT(19) | BIT(18), 1); /* Resp TXAGC offset = -3dB*/ + PHYDM_DBG(dm, DBG_DYN_TXPWR, "Response Power Set TX power: level 1\n"); + } else if (now_pwr_lvl == tx_high_pwr_level_normal) { + odm_set_mac_reg(dm, 0x6D8, BIT(20) | BIT(19) | BIT(18), 0); /* Resp TXAGC offset = 0dB*/ + PHYDM_DBG(dm, DBG_DYN_TXPWR, "Response Power Set TX power: normal\n"); + } + } +} + +void +phydm_dtp_fill_cmninfo( + void *dm_void, + u8 macid, + u8 dtp_lvl +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dtp_info *dtp= NULL; + dtp = &dm->phydm_sta_info[macid]->dtp_stat; + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; + if (dtp_lvl == tx_high_pwr_level_level2) + dtp->dyn_tx_power = PHYDM_OFFSET_MINUS_7DB; + else if (dtp_lvl == tx_high_pwr_level_level1) + dtp->dyn_tx_power = PHYDM_OFFSET_MINUS_3DB; + else + dtp->dyn_tx_power = PHYDM_OFFSET_ZERO; + +} +void +phydm_dtp_per_sta( + void *dm_void, + u8 macid +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct dtp_info *dtp = NULL; + struct rssi_info *rssi = NULL; + if (is_sta_active(sta)) { + dtp = &sta->dtp_stat; + rssi = &sta->rssi_stat; + dtp->sta_tx_high_power_lvl = phydm_pwr_lvl_check(dm,rssi->rssi); + if (dtp->sta_tx_high_power_lvl != dtp->sta_last_dtp_lvl) { + PHYDM_DBG(dm, DBG_DYN_TXPWR, "STA=%d : update_DTP_lv: ((%d)) -> ((%d))\n", macid, dm->last_dtp_lvl, dm->dynamic_tx_high_power_lvl); + dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl; + phydm_dtp_fill_cmninfo(dm, macid, dm->dynamic_tx_high_power_lvl); + } + } } + +#else +void +phydm_dynamic_tx_power_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + + /*if (!IS_HARDWARE_TYPE_8814A(adapter)) {*/ + /* PHYDM_DBG(dm,DBG_DYN_TXPWR, */ + /* ("DynamicTxPowerEnable=%d\n", mgnt_info->is_dynamic_tx_power_enable));*/ + /* return;*/ + /*} else*/ + { + mgnt_info->bDynamicTxPowerEnable = true; + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "DynamicTxPowerEnable=%d\n", mgnt_info->bDynamicTxPowerEnable); + } + +#if DEV_BUS_TYPE == RT_USB_INTERFACE + if (RT_GetInterfaceSelection((PADAPTER)adapter) == INTF_SEL1_USB_High_Power) { + mgnt_info->bDynamicTxPowerEnable = true; + } else +#else + /* so 92c pci do not need dynamic tx power? vivi check it later */ + mgnt_info->bDynamicTxPowerEnable = false; +#endif + + + hal_data->LastDTPLvl = tx_high_pwr_level_normal; + hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + dm->last_dtp_lvl = tx_high_pwr_level_normal; + dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal; + dm->tx_agc_ofdm_18_6 = odm_get_bb_reg(dm, 0xC24, MASKDWORD); /*TXAGC {18M 12M 9M 6M}*/ + +#endif + +} + + + void odm_dynamic_tx_power_nic_ce( - void *p_dm_void + void *dm_void ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) #if (RTL8821A_SUPPORT == 1) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 val; - u8 rssi_tmp = p_dm_odm->rssi_min; + u8 rssi_tmp = dm->rssi_min; - if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) return; if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { - p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level2; + dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level2; /**/ } else if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL1) { - p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level1; + dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level1; /**/ } else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { - p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal; + dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal; /**/ } - if (p_dm_odm->last_dtp_lvl != p_dm_odm->dynamic_tx_high_power_lvl) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("update_DTP_lv: ((%d)) -> ((%d))\n", p_dm_odm->last_dtp_lvl, p_dm_odm->dynamic_tx_high_power_lvl)); - - p_dm_odm->last_dtp_lvl = p_dm_odm->dynamic_tx_high_power_lvl; - - if (p_dm_odm->support_ic_type & (ODM_RTL8821)) { - - if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level2) { + if (dm->last_dtp_lvl == dm->dynamic_tx_high_power_lvl) + return; - odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/ + PHYDM_DBG(dm, DBG_DYN_TXPWR, "update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl, dm->dynamic_tx_high_power_lvl); - val = p_dm_odm->tx_agc_ofdm_18_6 & 0xff; - if (val >= 0x20) - val -= 0x16; + dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl; - odm_set_bb_reg(p_dm_odm, 0xC24, 0xff, val); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 2\n")); - } else if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level1) { + if (dm->support_ic_type & (ODM_RTL8821)) { + if (dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level2) { + odm_set_mac_reg(dm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/ - odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/ + val = dm->tx_agc_ofdm_18_6 & 0xff; + if (val >= 0x20) + val -= 0x16; - val = p_dm_odm->tx_agc_ofdm_18_6 & 0xff; - if (val >= 0x20) - val -= 0x10; + odm_set_bb_reg(dm, 0xC24, 0xff, val); + PHYDM_DBG(dm, DBG_DYN_TXPWR, "Set TX power: level 2\n"); + } else if (dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level1) { + odm_set_mac_reg(dm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/ - odm_set_bb_reg(p_dm_odm, 0xC24, 0xff, val); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 1\n")); - } else if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_normal) { + val = dm->tx_agc_ofdm_18_6 & 0xff; + if (val >= 0x20) + val -= 0x10; - odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 0); /* Resp TXAGC offset = 0dB*/ - odm_set_bb_reg(p_dm_odm, 0xC24, MASKDWORD, p_dm_odm->tx_agc_ofdm_18_6); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: normal\n")); - } + odm_set_bb_reg(dm, 0xC24, 0xff, val); + PHYDM_DBG(dm, DBG_DYN_TXPWR, "Set TX power: level 1\n"); + } else if (dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_normal) { + odm_set_mac_reg(dm, 0x6D8, BIT(20) | BIT19 | BIT18, 0); /* Resp TXAGC offset = 0dB*/ + odm_set_bb_reg(dm, 0xC24, MASKDWORD, dm->tx_agc_ofdm_18_6); + PHYDM_DBG(dm, DBG_DYN_TXPWR, "Set TX power: normal\n"); } } @@ -190,32 +430,30 @@ odm_dynamic_tx_power_nic_ce( void odm_dynamic_tx_power( - void *p_dm_void + void *dm_void ) { /* */ /* For AP/ADSL use struct rtl8192cd_priv* */ - /* For CE/NIC use struct _ADAPTER* */ + /* For CE/NIC use struct void* */ /* */ - /* struct _ADAPTER* p_adapter = p_dm_odm->adapter; - * struct rtl8192cd_priv* priv = p_dm_odm->priv; */ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + /* struct void* adapter = dm->adapter; + * struct rtl8192cd_priv* priv = dm->priv; */ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) return; /* */ /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ /* HW dynamic mechanism. */ /* */ - switch (p_dm_odm->support_platform) { + switch (dm->support_platform) { case ODM_WIN: - odm_dynamic_tx_power_nic(p_dm_odm); + odm_dynamic_tx_power_nic(dm); break; case ODM_CE: - odm_dynamic_tx_power_nic_ce(p_dm_odm); - break; - case ODM_AP: - odm_dynamic_tx_power_ap(p_dm_odm); + odm_dynamic_tx_power_nic_ce(dm); break; default: break; @@ -227,127 +465,54 @@ odm_dynamic_tx_power( void odm_dynamic_tx_power_nic( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) return; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) - odm_dynamic_tx_power_8814a(p_dm_odm); - else if (p_dm_odm->support_ic_type & ODM_RTL8821) { - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(adapter); - - if (p_mgnt_info->RegRspPwr == 1) { - if (p_dm_odm->rssi_min > 60) - odm_set_mac_reg(p_dm_odm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 1); /*Resp TXAGC offset = -3dB*/ - else if (p_dm_odm->rssi_min < 55) - odm_set_mac_reg(p_dm_odm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 0); /*Resp TXAGC offset = 0dB*/ + if (dm->support_ic_type == ODM_RTL8814A) + odm_dynamic_tx_power_8814a(dm); + else if (dm->support_ic_type & ODM_RTL8821) { + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = GetDefaultMgntInfo((PADAPTER)adapter); + + if (mgnt_info->RegRspPwr == 1) { + if (dm->rssi_min > 60) + odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 1); /*Resp TXAGC offset = -3dB*/ + else if (dm->rssi_min < 55) + odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 0); /*Resp TXAGC offset = 0dB*/ } } #endif } -void -odm_dynamic_tx_power_ap( - void *p_dm_void - -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - /* #if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1)) */ - - - struct rtl8192cd_priv *priv = p_dm_odm->priv; - s32 i; - s16 pwr_thd = 63; - - if (!priv->pshare->rf_ft_var.tx_pwr_ctrl) - return; - -#if ((RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8822B)) - pwr_thd = TX_POWER_NEAR_FIELD_THRESH_LVL1; -#endif - - /* - * Check if station is near by to use lower tx power - */ - - if ((priv->up_time % 3) == 0) { - int disable_pwr_ctrl = ((p_dm_odm->false_alm_cnt.cnt_all > 1000) || ((p_dm_odm->false_alm_cnt.cnt_all > 300) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - struct sta_info *pstat = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(pstat)) { - if (disable_pwr_ctrl) - pstat->hp_level = 0; - else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd)) - pstat->hp_level = 1; - else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd - 8))) - pstat->hp_level = 0; - } - } - -#if defined(CONFIG_WLAN_HAL_8192EE) - if (GET_CHIP_VER(priv) == VERSION_8192E) { - if (!disable_pwr_ctrl && (p_dm_odm->rssi_min != 0xff)) { - if (p_dm_odm->rssi_min > pwr_thd) - RRSR_power_control_11n(priv, 1); - else if (p_dm_odm->rssi_min < (pwr_thd - 8)) - RRSR_power_control_11n(priv, 0); - } else - RRSR_power_control_11n(priv, 0); - } -#endif - -#ifdef CONFIG_WLAN_HAL_8814AE - if (GET_CHIP_VER(priv) == VERSION_8814A) { - if (!disable_pwr_ctrl && (p_dm_odm->rssi_min != 0xff)) { - if (p_dm_odm->rssi_min > pwr_thd) - RRSR_power_control_14(priv, 1); - else if (p_dm_odm->rssi_min < (pwr_thd - 8)) - RRSR_power_control_14(priv, 0); - } else - RRSR_power_control_14(priv, 0); - } -#endif - - } - /* #endif */ - -#endif -} void odm_dynamic_tx_power_8821( - void *p_dm_void, - u8 *p_desc, + void *dm_void, + u8 *desc, u8 mac_id ) { #if (RTL8821A_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct sta_info *p_entry; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *entry; u8 reg0xc56_byte; u8 txpwr_offset = 0; - p_entry = p_dm_odm->p_odm_sta_info[mac_id]; + entry = dm->phydm_sta_info[mac_id]; - reg0xc56_byte = odm_read_1byte(p_dm_odm, 0xc56); + reg0xc56_byte = odm_read_1byte(dm, 0xc56); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("reg0xc56_byte=%d\n", reg0xc56_byte)); - - if (p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb > 85) { + PHYDM_DBG(dm, DBG_DYN_TXPWR, "reg0xc56_byte=%d\n", reg0xc56_byte); + if (entry[mac_id].rssi_stat.rssi > 85) { /* Avoid TXAGC error after TX power offset is applied. For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB ) Total power = 6-11= -5( overflow!! ), PA may be burned ! @@ -360,12 +525,12 @@ odm_dynamic_tx_power_8821( else txpwr_offset = 3; - SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb, txpwr_offset)); + SET_TX_DESC_TX_POWER_OFFSET_8812(desc, txpwr_offset); + PHYDM_DBG(dm, DBG_DYN_TXPWR, "odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", entry[mac_id].rssi_stat.rssi, txpwr_offset); } else { - SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb, txpwr_offset)); + SET_TX_DESC_TX_POWER_OFFSET_8812(desc, txpwr_offset); + PHYDM_DBG(dm, DBG_DYN_TXPWR, "odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", entry[mac_id].rssi_stat.rssi, txpwr_offset); } #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ @@ -375,70 +540,59 @@ odm_dynamic_tx_power_8821( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void odm_dynamic_tx_power_8814a( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - s32 undecorated_smoothed_pwdb; + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + s32 undecorated_smoothed_pwdb = dm->rssi_min; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, - ("TxLevel=%d p_mgnt_info->iot_action=%x p_mgnt_info->is_dynamic_tx_power_enable=%d\n", - p_hal_data->DynamicTxHighPowerLvl, p_mgnt_info->IOTAction, p_mgnt_info->bDynamicTxPowerEnable)); + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "TxLevel=%d mgnt_info->iot_action=%x mgnt_info->is_dynamic_tx_power_enable=%d\n", + hal_data->DynamicTxHighPowerLvl, mgnt_info->IOTAction, mgnt_info->bDynamicTxPowerEnable); /*STA not connected and AP not connected*/ - if ((!p_mgnt_info->bMediaConnect) && (p_hal_data->EntryMinUndecoratedSmoothedPWDB == 0)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any reset power lvl\n")); - p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; + if ((!mgnt_info->bMediaConnect) && (hal_data->EntryMinUndecoratedSmoothedPWDB == 0)) { + PHYDM_DBG(dm, DBG_DYN_TXPWR, "Not connected to any reset power lvl\n"); + hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; return; } - if ((p_mgnt_info->bDynamicTxPowerEnable != true) || p_mgnt_info->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) - p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; + if (!mgnt_info->bDynamicTxPowerEnable || mgnt_info->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) + hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; else { - if (p_mgnt_info->bMediaConnect) { /*Default port*/ - if (ACTING_AS_AP(adapter) || ACTING_AS_IBSS(adapter)) { - undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", undecorated_smoothed_pwdb)); - } else { - undecorated_smoothed_pwdb = p_hal_data->UndecoratedSmoothedPWDB; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", undecorated_smoothed_pwdb)); - } - } else {/*associated entry pwdb*/ - undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", undecorated_smoothed_pwdb)); - } /*Should we separate as 2.4G/5G band?*/ + PHYDM_DBG(dm, DBG_DYN_TXPWR, "rssi_tmp = %d\n", undecorated_smoothed_pwdb); if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { - p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_level1 (TxPwr=0x0)\n")); + hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level2; + PHYDM_DBG(dm, DBG_DYN_TXPWR, "tx_high_pwr_level_level1 (TxPwr=0x0)\n"); } else if ((undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) && (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) { - p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_level1 (TxPwr=0x10)\n")); + hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level1; + PHYDM_DBG(dm, DBG_DYN_TXPWR, "tx_high_pwr_level_level1 (TxPwr=0x10)\n"); } else if (undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { - p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_normal\n")); + hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; + PHYDM_DBG(dm, DBG_DYN_TXPWR, "tx_high_pwr_level_normal\n"); } } - if (p_hal_data->DynamicTxHighPowerLvl != p_hal_data->LastDTPLvl) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8814a() channel = %d\n", p_hal_data->CurrentChannel)); - odm_set_tx_power_level8814(adapter, p_hal_data->CurrentChannel, p_hal_data->DynamicTxHighPowerLvl); + if (hal_data->DynamicTxHighPowerLvl != hal_data->LastDTPLvl) { + PHYDM_DBG(dm, DBG_DYN_TXPWR, "odm_dynamic_tx_power_8814a() channel = %d\n", hal_data->CurrentChannel); + odm_set_tx_power_level8814(adapter, hal_data->CurrentChannel, hal_data->DynamicTxHighPowerLvl); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, - ("odm_dynamic_tx_power_8814a() channel = %d TXpower lvl=%d/%d\n", - p_hal_data->CurrentChannel, p_hal_data->LastDTPLvl, p_hal_data->DynamicTxHighPowerLvl)); + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "odm_dynamic_tx_power_8814a() channel = %d TXpower lvl=%d/%d\n", + hal_data->CurrentChannel, hal_data->LastDTPLvl, hal_data->DynamicTxHighPowerLvl); - p_hal_data->LastDTPLvl = p_hal_data->DynamicTxHighPowerLvl; + hal_data->LastDTPLvl = hal_data->DynamicTxHighPowerLvl; } @@ -450,7 +604,7 @@ odm_dynamic_tx_power_8814a( /**/ void odm_set_tx_power_level8814( - struct _ADAPTER *adapter, + void *adapter, u8 channel, u8 pwr_lvl ) @@ -460,7 +614,7 @@ odm_set_tx_power_level8814( u32 value[264] = {0}; u32 path = 0, power_index, txagc_table_wd = 0x00801000; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); u8 jaguar2_rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}, {MGN_6M, MGN_9M, MGN_12M, MGN_18M}, @@ -481,11 +635,10 @@ odm_set_tx_power_level8814( {MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0} }; - for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) { - - u8 usb_host = UsbModeQueryHubUsbType(adapter); - u8 usb_rfset = UsbModeQueryRfSet(adapter); - u8 usb_rf_type = RT_GetRFType(adapter); + for (path = RF_PATH_A; path <= RF_PATH_D; ++path) { + u8 usb_host = UsbModeQueryHubUsbType((PADAPTER)adapter); + u8 usb_rfset = UsbModeQueryRfSet((PADAPTER)adapter); + u8 usb_rf_type = RT_GetRFType((PADAPTER)adapter); for (i = 0; i <= 16; i++) { for (j = 0; j <= 3; j++) { @@ -493,7 +646,7 @@ odm_set_tx_power_level8814( continue; txagc_table_wd = 0x00801000; - power_index = (u32) PHY_GetTxPowerIndex(adapter, (u8)path, jaguar2_rates[i][j], p_hal_data->CurrentChannelBW, channel); + power_index = (u32) PHY_GetTxPowerIndex((PADAPTER)adapter, (u8)path, jaguar2_rates[i][j], hal_data->CurrentChannelBW, channel); /*for Query bus type to recude tx power.*/ if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(adapter) && usb_rf_type == RF_3T3R) { @@ -516,15 +669,44 @@ odm_set_tx_power_level8814( txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2_rates[i][j]) | (power_index << 24); - PHY_SetTxPowerIndexShadow(adapter, (u8)power_index, (u8)path, jaguar2_rates[i][j]); + PHY_SetTxPowerIndexShadow((PADAPTER)adapter, (u8)power_index, (u8)path, jaguar2_rates[i][j]); value[k++] = txagc_table_wd; } } } - if (adapter->MgntInfo.bScanInProgress == false && adapter->MgntInfo.RegFWOffload == 2) - HalDownloadTxPowerLevel8814(adapter, value); + if (((PADAPTER)adapter)->MgntInfo.bScanInProgress == false && ((PADAPTER)adapter)->MgntInfo.RegFWOffload == 2) + HalDownloadTxPowerLevel8814((PADAPTER)adapter, value); #endif } #endif + +#endif /* #ifdef CONFIG_DYNAMIC_TX_TWR */ + +void +phydm_dynamic_tx_power( + void *dm_void +) +{ +#ifdef CONFIG_DYNAMIC_TX_TWR + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + u8 i; + u8 cnt = 0; + u8 rssi_min = dm->rssi_min; + u8 rssi_tmp; + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; + /* Response Power */ + dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm, rssi_min); + phydm_dynamic_response_power(dm); + /* Per STA Tx power */ + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + phydm_dtp_per_sta(dm, i); + cnt++; + if (cnt >= dm->number_linked_client) + break; + } +#endif +} \ No newline at end of file diff --git a/hal/phydm/phydm_dynamictxpower.h b/hal/phydm/phydm_dynamictxpower.h index 36b004c..4698cb2 100644 --- a/hal/phydm/phydm_dynamictxpower.h +++ b/hal/phydm/phydm_dynamictxpower.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __PHYDMDYNAMICTXPOWER_H__ @@ -44,48 +54,62 @@ #define tx_high_pwr_level_70 8 #define tx_high_pwr_level_100 9 +enum phydm_dtp_power_offset { + PHYDM_OFFSET_ZERO = 0, + PHYDM_OFFSET_MINUS_3DB = 1, + PHYDM_OFFSET_MINUS_7DB = 2, + PHYDM_OFFSET_MINUS_11DB = 3, + PHYDM_OFFSET_ADD_3DB = 4, + PHYDM_OFFSET_ADD_6DB = 5 +}; + +void +phydm_pow_train_init( + void *dm_void +); + void -odm_dynamic_tx_power_init( - void *p_dm_void +phydm_dynamic_tx_power( + void *dm_void ); void odm_dynamic_tx_power_restore_power_index( - void *p_dm_void + void *dm_void ); void odm_dynamic_tx_power_nic( - void *p_dm_void + void *dm_void ); #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) void odm_dynamic_tx_power_save_power_index( - void *p_dm_void + void *dm_void ); void odm_dynamic_tx_power_write_power_index( - void *p_dm_void, + void *dm_void, u8 value); void odm_dynamic_tx_power_8821( - void *p_dm_void, - u8 *p_desc, + void *dm_void, + u8 *desc, u8 mac_id ); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void odm_dynamic_tx_power_8814a( - void *p_dm_void + void *dm_void ); void odm_set_tx_power_level8814( - struct _ADAPTER *adapter, + void *adapter, u8 channel, u8 pwr_lvl ); @@ -94,12 +118,17 @@ odm_set_tx_power_level8814( void odm_dynamic_tx_power( - void *p_dm_void + void *dm_void +); + +void +phydm_dynamic_tx_power( + void *dm_void ); void -odm_dynamic_tx_power_ap( - void *p_dm_void +phydm_dynamic_tx_power_init( + void *dm_void ); #endif diff --git a/hal/phydm/phydm_edcaturbocheck.c b/hal/phydm/phydm_edcaturbocheck.c deleted file mode 100644 index 7662e76..0000000 --- a/hal/phydm/phydm_edcaturbocheck.c +++ /dev/null @@ -1,763 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -VOID -ODM_EdcaTurboInit( - IN PVOID pDM_VOID) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - -#if (DM_ODM_SUPPORT_TYPE==ODM_WIN) - PADAPTER Adapter = NULL; - HAL_DATA_TYPE *pHalData = NULL; - - if(pDM_Odm->Adapter==NULL) { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EdcaTurboInit fail!!!\n")); - return; - } - - Adapter=pDM_Odm->Adapter; - pHalData=GET_HAL_DATA(Adapter); - - pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; - pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE; - pHalData->bIsAnyNonBEPkts = FALSE; - -#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; - pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE; - Adapter->recvpriv.bIsAnyNonBEPkts =FALSE; - -#endif - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VO_PARAM))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM))); - - -} // ODM_InitEdcaTurbo - -VOID -odm_EdcaTurboCheck( - IN PVOID pDM_VOID - ) -{ - // - // For AP/ADSL use prtl8192cd_priv - // For CE/NIC use PADAPTER - // - - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n")); - - if(!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO )) - return; - - switch (pDM_Odm->SupportPlatform) - { - case ODM_WIN: - -#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) - odm_EdcaTurboCheckMP(pDM_Odm); -#endif - break; - - case ODM_CE: -#if(DM_ODM_SUPPORT_TYPE==ODM_CE) - odm_EdcaTurboCheckCE(pDM_Odm); -#endif - break; - } - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n")); - -} // odm_CheckEdcaTurbo - -#if(DM_ODM_SUPPORT_TYPE==ODM_CE) - - -VOID -odm_EdcaTurboCheckCE( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - u32 EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer]; - u32 EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer]; - u32 ICType=pDM_Odm->SupportICType; - u32 IOTPeer=0; - u8 WirelessMode=0xFF; //invalid value - u32 trafficIndex; - u32 edca_param; - u64 cur_tx_bytes = 0; - u64 cur_rx_bytes = 0; - u8 bbtchange = _FALSE; - u8 bBiasOnRx = _FALSE; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); - struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); - struct recv_priv *precvpriv = &(Adapter->recvpriv); - struct registry_priv *pregpriv = &Adapter->registrypriv; - struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - if(pDM_Odm->bLinked != _TRUE) - { - precvpriv->bIsAnyNonBEPkts = _FALSE; - return; - } - - if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0)) - { - precvpriv->bIsAnyNonBEPkts = _FALSE; - return; - } - - if(pDM_Odm->pWirelessMode!=NULL) - WirelessMode=*(pDM_Odm->pWirelessMode); - - IOTPeer = pmlmeinfo->assoc_AP_vendor; - - if (IOTPeer >= HT_IOT_PEER_MAX) - { - precvpriv->bIsAnyNonBEPkts = _FALSE; - return; - } - - if (pDM_Odm->SupportICType & ODM_RTL8188E) { - if((IOTPeer == HT_IOT_PEER_RALINK)||(IOTPeer == HT_IOT_PEER_ATHEROS)) - bBiasOnRx = _TRUE; - } - - // Check if the status needs to be changed. - if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) ) - { - cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes; - cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes; - - //traffic, TX or RX - if(bBiasOnRx) - { - if (cur_tx_bytes > (cur_rx_bytes << 2)) - { // Uplink TP is present. - trafficIndex = UP_LINK; - } - else - { // Balance TP is present. - trafficIndex = DOWN_LINK; - } - } - else - { - if (cur_rx_bytes > (cur_tx_bytes << 2)) - { // Downlink TP is present. - trafficIndex = DOWN_LINK; - } - else - { // Balance TP is present. - trafficIndex = UP_LINK; - } - } - - //if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) - { - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) { - EDCA_BE_UL = 0x6ea42b; - EDCA_BE_DL = 0x6ea42b; - } - - //92D txop can't be set to 0x3e for cisco1250 - if ((IOTPeer == HT_IOT_PEER_CISCO) && (WirelessMode == ODM_WM_N24G)) - { - EDCA_BE_DL = edca_setting_DL[IOTPeer]; - EDCA_BE_UL = edca_setting_UL[IOTPeer]; - } - //merge from 92s_92c_merge temp brunch v2445 20120215 - else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B))) - { - EDCA_BE_DL = edca_setting_DL_GMode[IOTPeer]; - } - else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A))) - { - EDCA_BE_DL = 0xa630; - } - else if(IOTPeer == HT_IOT_PEER_MARVELL) - { - EDCA_BE_DL = edca_setting_DL[IOTPeer]; - EDCA_BE_UL = edca_setting_UL[IOTPeer]; - } - else if(IOTPeer == HT_IOT_PEER_ATHEROS) - { - // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. - EDCA_BE_DL = edca_setting_DL[IOTPeer]; - } - - if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8821)||(ICType==ODM_RTL8192E)) //add 8812AU/8812AE - { - EDCA_BE_UL = 0x5ea42b; - EDCA_BE_DL = 0x5ea42b; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x",EDCA_BE_UL,EDCA_BE_DL)); - } - - if (trafficIndex == DOWN_LINK) - edca_param = EDCA_BE_DL; - else - edca_param = EDCA_BE_UL; - - rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); - - pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; - } - - pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _TRUE; - } - else - { - // - // Turn Off EDCA turbo here. - // Restore original EDCA according to the declaration of AP. - // - if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) - { - rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); - pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _FALSE; - } - } - -} - - -#elif(DM_ODM_SUPPORT_TYPE==ODM_WIN) -VOID -odm_EdcaTurboCheckMP( - IN PVOID pDM_VOID - ) -{ - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - PADAPTER pDefaultAdapter = GetDefaultAdapter(Adapter); - PADAPTER pExtAdapter = GetFirstExtAdapter(Adapter);//NULL; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos; - //[Win7 Count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's Adapter is always Default. 2009.08.20, by Bohn - u8Byte Ext_curTxOkCnt = 0; - u8Byte Ext_curRxOkCnt = 0; - //For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. - u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE; - - // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. - u8Byte curTxOkCnt = 0; - u8Byte curRxOkCnt = 0; - u4Byte EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer]; - u4Byte EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer]; - u4Byte EDCA_BE = 0x5ea42b; - u1Byte IOTPeer=0; - BOOLEAN *pbIsCurRDLState=NULL; - BOOLEAN bLastIsCurRDLState=FALSE; - BOOLEAN bBiasOnRx=FALSE; - BOOLEAN bEdcaTurboOn=FALSE; - u1Byte TxRate = 0xFF; - u8Byte value64; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheckMP========================>")); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); - -////=============================== -////list paramter for different platform -////=============================== - bLastIsCurRDLState=pDM_Odm->DM_EDCA_Table.bIsCurRDLState; - pbIsCurRDLState=&(pDM_Odm->DM_EDCA_Table.bIsCurRDLState); - - //2012/09/14 MH Add - if (pMgntInfo->NumNonBePkt > pMgntInfo->RegEdcaThresh && !(Adapter->MgntInfo.bWiFiConfg & RT_WIFI_LOGO)) - pHalData->bIsAnyNonBEPkts = TRUE; - - pMgntInfo->NumNonBePkt = 0; - - // Caculate TX/RX TP: - curTxOkCnt = pDM_Odm->curTxOkCnt; - curRxOkCnt = pDM_Odm->curRxOkCnt; - - - if(pExtAdapter == NULL) - pExtAdapter = pDefaultAdapter; - - Ext_curTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->Ext_lastTxOkCnt; - Ext_curRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->Ext_lastRxOkCnt; - GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus); - //For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. - if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY) - { - curTxOkCnt = Ext_curTxOkCnt ; - curRxOkCnt = Ext_curRxOkCnt ; - } - // - IOTPeer=pMgntInfo->IOTPeer; - bBiasOnRx=(pMgntInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)?TRUE:FALSE; - bEdcaTurboOn=((!pHalData->bIsAnyNonBEPkts))?TRUE:FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bIsAnyNonBEPkts : 0x%lx \n",pHalData->bIsAnyNonBEPkts)); - - -////=============================== -////check if edca turbo is disabled -////=============================== - if(odm_IsEdcaTurboDisable(pDM_Odm)) - { - pHalData->bIsAnyNonBEPkts = FALSE; - pMgntInfo->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; - pMgntInfo->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; - pMgntInfo->Ext_lastTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast; - pMgntInfo->Ext_lastRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast; - - } - -////=============================== -////remove iot case out -////=============================== - ODM_EdcaParaSelByIot(pDM_Odm, &EDCA_BE_UL, &EDCA_BE_DL); - - -////=============================== -////Check if the status needs to be changed. -////=============================== - if(bEdcaTurboOn) - { - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",bEdcaTurboOn,bBiasOnRx)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curTxOkCnt : 0x%lx \n",curTxOkCnt)); - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curRxOkCnt : 0x%lx \n",curRxOkCnt)); - if(bBiasOnRx) - odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, TRUE, pbIsCurRDLState); - else - odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, FALSE, pbIsCurRDLState); - -//modify by Guo.Mingzhi 2011-12-29 - EDCA_BE=((*pbIsCurRDLState)==TRUE)?EDCA_BE_DL:EDCA_BE_UL; - if(IS_HARDWARE_TYPE_8821U(Adapter)) - { - if(pMgntInfo->RegTxDutyEnable) - { - //2013.01.23 LukeLee: debug for 8811AU thermal issue (reduce Tx duty cycle) - if(!pMgntInfo->ForcedDataRate) //auto rate - { - if(pDM_Odm->TxRate != 0xFF) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - } - else //force rate - { - TxRate = (u1Byte) pMgntInfo->ForcedDataRate; - } - - value64 = (curRxOkCnt<<2); - if(curTxOkCnt < value64) //Downlink - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - else //Uplink - { - /*DbgPrint("pRFCalibrateInfo->ThermalValue = 0x%X\n", pRFCalibrateInfo->ThermalValue);*/ - /*if(pRFCalibrateInfo->ThermalValue < pHalData->EEPROMThermalMeter)*/ - if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G)) - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - else - { - switch (TxRate) - { - case MGN_VHT1SS_MCS6: - case MGN_VHT1SS_MCS5: - case MGN_MCS6: - case MGN_MCS5: - case MGN_48M: - case MGN_54M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea42b); - break; - case MGN_VHT1SS_MCS4: - case MGN_MCS4: - case MGN_36M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa42b); - break; - case MGN_VHT1SS_MCS3: - case MGN_MCS3: - case MGN_24M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa47f); - break; - case MGN_VHT1SS_MCS2: - case MGN_MCS2: - case MGN_18M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa57f); - break; - case MGN_VHT1SS_MCS1: - case MGN_MCS1: - case MGN_9M: - case MGN_12M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa77f); - break; - case MGN_VHT1SS_MCS0: - case MGN_MCS0: - case MGN_6M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f); - break; - default: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - break; - } - } - } - } - else - { - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - } - - } - else if (IS_HARDWARE_TYPE_8812AU(Adapter)){ - if(pMgntInfo->RegTxDutyEnable) - { - //2013.07.26 Wilson: debug for 8812AU thermal issue (reduce Tx duty cycle) - // it;s the same issue as 8811AU - if(!pMgntInfo->ForcedDataRate) //auto rate - { - if(pDM_Odm->TxRate != 0xFF) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - } - else //force rate - { - TxRate = (u1Byte) pMgntInfo->ForcedDataRate; - } - - value64 = (curRxOkCnt<<2); - if(curTxOkCnt < value64) //Downlink - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - else //Uplink - { - /*DbgPrint("pRFCalibrateInfo->ThermalValue = 0x%X\n", pRFCalibrateInfo->ThermalValue);*/ - /*if(pRFCalibrateInfo->ThermalValue < pHalData->EEPROMThermalMeter)*/ - if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G)) - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - else - { - switch (TxRate) - { - case MGN_VHT2SS_MCS9: - case MGN_VHT1SS_MCS9: - case MGN_VHT1SS_MCS8: - case MGN_MCS15: - case MGN_MCS7: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea44f); - case MGN_VHT2SS_MCS8: - case MGN_VHT1SS_MCS7: - case MGN_MCS14: - case MGN_MCS6: - case MGN_54M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa44f); - case MGN_VHT2SS_MCS7: - case MGN_VHT2SS_MCS6: - case MGN_VHT1SS_MCS6: - case MGN_VHT1SS_MCS5: - case MGN_MCS13: - case MGN_MCS5: - case MGN_48M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa630); - break; - case MGN_VHT2SS_MCS5: - case MGN_VHT2SS_MCS4: - case MGN_VHT1SS_MCS4: - case MGN_VHT1SS_MCS3: - case MGN_MCS12: - case MGN_MCS4: - case MGN_MCS3: - case MGN_36M: - case MGN_24M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa730); - break; - case MGN_VHT2SS_MCS3: - case MGN_VHT2SS_MCS2: - case MGN_VHT2SS_MCS1: - case MGN_VHT1SS_MCS2: - case MGN_VHT1SS_MCS1: - case MGN_MCS11: - case MGN_MCS10: - case MGN_MCS9: - case MGN_MCS2: - case MGN_MCS1: - case MGN_18M: - case MGN_12M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa830); - break; - case MGN_VHT2SS_MCS0: - case MGN_VHT1SS_MCS0: - case MGN_MCS0: - case MGN_MCS8: - case MGN_9M: - case MGN_6M: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f); - break; - default: - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - break; - } - } - } - } - else - { - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - } - } - else - ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA Turbo on: EDCA_BE:0x%lx\n",EDCA_BE)); - - pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = TRUE; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA_BE_DL : 0x%lx EDCA_BE_UL : 0x%lx EDCA_BE : 0x%lx \n",EDCA_BE_DL,EDCA_BE_UL,EDCA_BE)); - - } - else - { - // Turn Off EDCA turbo here. - // Restore original EDCA according to the declaration of AP. - if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) - { - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(pStaQos->WMMParamEle, AC0_BE) ); - - pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Restore EDCA BE: 0x%lx \n",pDM_Odm->WMMEDCA_BE)); - - } - } - -} - - -//check if edca turbo is disabled -BOOLEAN -odm_IsEdcaTurboDisable( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - u4Byte IOTPeer=pMgntInfo->IOTPeer; - - if(pDM_Odm->bBtDisableEdcaTurbo) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n")); - return TRUE; - } - - if((!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))|| - (pDM_Odm->WIFITest & RT_WIFI_LOGO)|| - (IOTPeer>= HT_IOT_PEER_MAX)) - { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable\n")); - return TRUE; - } - - - // 1. We do not turn on EDCA turbo mode for some AP that has IOT issue - // 2. User may disable EDCA Turbo mode with OID settings. - if(pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO){ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("IOTAction:EdcaTurboDisable\n")); - return TRUE; - } - - return FALSE; - - -} - -//add iot case here: for MP/CE -VOID -ODM_EdcaParaSelByIot( - IN PVOID pDM_VOID, - OUT u4Byte *EDCA_BE_UL, - OUT u4Byte *EDCA_BE_DL - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - u4Byte IOTPeer=0; - u4Byte ICType=pDM_Odm->SupportICType; - u1Byte WirelessMode=0xFF; //invalid value - u4Byte IOTPeerSubType = 0; - - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE; - - if(pDM_Odm->pWirelessMode!=NULL) - WirelessMode=*(pDM_Odm->pWirelessMode); - -/////////////////////////////////////////////////////////// -////list paramter for different platform - - IOTPeer=pMgntInfo->IOTPeer; - IOTPeerSubType=pMgntInfo->IOTPeerSubtype; - GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus); - -////============================ -/// IOT case for MP -////============================ - if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) { - (*EDCA_BE_UL) = 0x6ea42b; - (*EDCA_BE_DL) = 0x6ea42b; - } - - if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY) - { - (*EDCA_BE_UL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[ExtAdapter->MgntInfo.IOTPeer]; - (*EDCA_BE_DL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[ExtAdapter->MgntInfo.IOTPeer]; - } - - #if (INTEL_PROXIMITY_SUPPORT == 1) - if(pMgntInfo->IntelClassModeInfo.bEnableCA == TRUE) - { - (*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f; - } - else - #endif - { - if((pMgntInfo->IOTAction & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP|HT_IOT_ACT_AMSDU_ENABLE))) - {// To check whether we shall force turn on TXOP configuration. - if(!((*EDCA_BE_UL) & 0xffff0000)) - (*EDCA_BE_UL) |= 0x005e0000; // Force TxOP limit to 0x005e for UL. - if(!((*EDCA_BE_DL) & 0xffff0000)) - (*EDCA_BE_DL) |= 0x005e0000; // Force TxOP limit to 0x005e for DL. - } - - //92D txop can't be set to 0x3e for cisco1250 - if ((IOTPeer == HT_IOT_PEER_CISCO) && (WirelessMode == ODM_WM_N24G)) - { - (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; - (*EDCA_BE_UL) = edca_setting_UL[IOTPeer]; - } - //merge from 92s_92c_merge temp brunch v2445 20120215 - else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B))) - { - (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer]; - } - else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A))) - { - (*EDCA_BE_DL) = 0xa630; - } - - else if(IOTPeer == HT_IOT_PEER_MARVELL) - { - (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; - (*EDCA_BE_UL) = edca_setting_UL[IOTPeer]; - } - else if(IOTPeer == HT_IOT_PEER_ATHEROS && IOTPeerSubType != HT_IOT_PEER_TPLINK_AC1750) - { - // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. - if(WirelessMode==ODM_WM_G) - (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer]; - else - (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; - - if(ICType == ODM_RTL8821) - (*EDCA_BE_DL) = 0x5ea630; - - } - } - - if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8192E)) //add 8812AU/8812AE - { - (*EDCA_BE_UL) = 0x5ea42b; - (*EDCA_BE_DL) = 0x5ea42b; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n",(*EDCA_BE_UL),(*EDCA_BE_DL))); - } - - if((ICType==ODM_RTL8814A) && (IOTPeer == HT_IOT_PEER_REALTEK)) /*8814AU and 8814AR*/ - { - (*EDCA_BE_UL) = 0x5ea42b; - (*EDCA_BE_DL) = 0xa42b; - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8814A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n",(*EDCA_BE_UL),(*EDCA_BE_DL))); - } - - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx, IOTPeer = %d\n",(*EDCA_BE_UL),(*EDCA_BE_DL), IOTPeer)); - -} - - -VOID -odm_EdcaChooseTrafficIdx( - IN PVOID pDM_VOID, - IN u8Byte cur_tx_bytes, - IN u8Byte cur_rx_bytes, - IN BOOLEAN bBiasOnRx, - OUT BOOLEAN *pbIsCurRDLState - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if(bBiasOnRx) - { - - if(cur_tx_bytes>(cur_rx_bytes*4)) - { - *pbIsCurRDLState=FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Uplink Traffic\n ")); - - } - else - { - *pbIsCurRDLState=TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n")); - - } - } - else - { - if(cur_rx_bytes>(cur_tx_bytes*4)) - { - *pbIsCurRDLState=TRUE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Downlink Traffic\n")); - - } - else - { - *pbIsCurRDLState=FALSE; - ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n")); - } - } - - return ; -} - -#endif - - diff --git a/hal/phydm/phydm_edcaturbocheck.h b/hal/phydm/phydm_edcaturbocheck.h deleted file mode 100644 index 7dd0997..0000000 --- a/hal/phydm/phydm_edcaturbocheck.h +++ /dev/null @@ -1,100 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMEDCATURBOCHECK_H__ -#define __PHYDMEDCATURBOCHECK_H__ - -/*#define EDCATURBO_VERSION "2.1"*/ -#define EDCATURBO_VERSION "2.3" /*2015.07.29 by YuChen*/ - -typedef struct _EDCA_TURBO_ -{ - BOOLEAN bCurrentTurboEDCA; - BOOLEAN bIsCurRDLState; - - #if(DM_ODM_SUPPORT_TYPE == ODM_CE ) - u4Byte prv_traffic_idx; // edca turbo - #endif - -}EDCA_T,*pEDCA_T; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) -static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] = -// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx) -{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322}; - - -static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] = -// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP(UpLink/Rx) -{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b}; - -static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] = -// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP -{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b}; - -#endif - - - -VOID -odm_EdcaTurboCheck( - IN PVOID pDM_VOID - ); -VOID -ODM_EdcaTurboInit( - IN PVOID pDM_VOID -); - -#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) -VOID -odm_EdcaTurboCheckMP( - IN PVOID pDM_VOID - ); - -//check if edca turbo is disabled -BOOLEAN -odm_IsEdcaTurboDisable( - IN PVOID pDM_VOID -); -//choose edca paramter for special IOT case -VOID -ODM_EdcaParaSelByIot( - IN PVOID pDM_VOID, - OUT u4Byte *EDCA_BE_UL, - OUT u4Byte *EDCA_BE_DL - ); -//check if it is UL or DL -VOID -odm_EdcaChooseTrafficIdx( - IN PVOID pDM_VOID, - IN u8Byte cur_tx_bytes, - IN u8Byte cur_rx_bytes, - IN BOOLEAN bBiasOnRx, - OUT BOOLEAN *pbIsCurRDLState - ); - -#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) -VOID -odm_EdcaTurboCheckCE( - IN PVOID pDM_VOID - ); -#endif - -#endif diff --git a/hal/phydm/phydm_features.h b/hal/phydm/phydm_features.h index 325e7c1..7710703 100644 --- a/hal/phydm/phydm_features.h +++ b/hal/phydm/phydm_features.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,13 +8,23 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __PHYDM_FEATURES_H__ -#define __PHYDM_FEATURES +#define __PHYDM_FEATURES_H__ #define ODM_DC_CANCELLATION_SUPPORT (ODM_RTL8188F | ODM_RTL8710B) #define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E) @@ -25,227 +35,18 @@ #define PHYDM_LA_MODE_SUPPORT 0 #endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - - #if (RTL8822B_SUPPORT == 1) - #define PHYDM_TXA_CALIBRATION 1 - #else - #define PHYDM_TXA_CALIBRATION 0 - #endif - - #if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) - #define PHYDM_PRIMARY_CCA 1 - #else - #define PHYDM_PRIMARY_CCA 0 - #endif - - - #if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822B_SUPPORT == 1) - #define PHYDM_DC_CANCELLATION 1 - #else - #define PHYDM_DC_CANCELLATION 0 - #endif - - #define CONFIG_PSD_TOOL 1 - /*phydm debyg report & tools*/ - #define CONFIG_PHYDM_DEBUG_FUNCTION 1 - - /*Antenna Diversity*/ - #define CONFIG_PHYDM_ANTENNA_DIVERSITY - #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY - - #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) - #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY - #endif - - #if (RTL8821A_SUPPORT == 1) - /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ - #define CONFIG_FAT_PATCH - #endif - - #if (RTL8822B_SUPPORT == 1) - /*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ - #endif - - #endif - - #if (RTL8822B_SUPPORT == 1) - #define CONFIG_DYNAMIC_RX_PATH 0 - #else - #define CONFIG_DYNAMIC_RX_PATH 0 - #endif - - #if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) - #define CONFIG_RECEIVER_BLOCKING - #endif - #define PHYDM_SUPPORT_CCKPD 1 - #define RA_MASK_PHYDMLIZE_WIN 1 - /*#define CONFIG_PATH_DIVERSITY*/ - /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ - #define CONFIG_ANT_DETECTION - /*#define CONFIG_RA_DBG_CMD*/ - #define CONFIG_RA_FW_DBG_CODE 1 - /*#define CONFIG_PHYDM_RX_SNIFFER_PARSING*/ - #define CONFIG_BB_POWER_SAVING - #define CONFIG_BB_TXBF_API - -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - #if (RTL8822B_SUPPORT == 1) - #define PHYDM_TXA_CALIBRATION 1 - #else - #define PHYDM_TXA_CALIBRATION 0 - #endif - - #if (RTL8188E_SUPPORT == 1) - #define PHYDM_PRIMARY_CCA 1 - #else - #define PHYDM_PRIMARY_CCA 0 - #endif - - #define CONFIG_PSD_TOOL 0 - /*phydm debyg report & tools*/ - #if defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION) - #define CONFIG_PHYDM_DEBUG_FUNCTION 0 - #else - #define CONFIG_PHYDM_DEBUG_FUNCTION 1 - #endif - - #if (RTL8822B_SUPPORT == 1) - #define CONFIG_DYNAMIC_RX_PATH 0 - #else - #define CONFIG_DYNAMIC_RX_PATH 0 - #endif - - #define PHYDM_SUPPORT_CCKPD 1 - #define RA_MASK_PHYDMLIZE_AP 1 - - /* #define CONFIG_RA_DBG_CMD*/ - #define CONFIG_RA_FW_DBG_CODE 0 - - /*#define CONFIG_PATH_DIVERSITY*/ - /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ - #define CONFIG_RA_DYNAMIC_RATE_ID - /*#define CONFIG_BB_POWER_SAVING*/ - #define CONFIG_BB_TXBF_API - - /* [ Configure Antenna Diversity ] */ - #if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) - #define CONFIG_PHYDM_ANTENNA_DIVERSITY - #define ODM_EVM_ENHANCE_ANTDIV - #define SKIP_EVM_ANTDIV_TRAINING_PATCH 1 - - /*----------*/ - - #if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - #define CONFIG_NO_2G_DIVERSITY - #endif - - #ifdef CONFIG_NO_5G_DIVERSITY_8881A - #define CONFIG_NO_5G_DIVERSITY - #elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A) - #define CONFIG_5G_CGCS_RX_DIVERSITY - #elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A) - #define CONFIG_5G_CG_TRX_DIVERSITY - #elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) - #define CONFIG_2G5G_CG_TRX_DIVERSITY - #endif - #if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) - #define CONFIG_NO_5G_DIVERSITY - #endif - /*----------*/ - #if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) - #define CONFIG_NOT_SUPPORT_ANTDIV - #elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) - #define CONFIG_2G_SUPPORT_ANTDIV - #elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) - #define CONFIG_5G_SUPPORT_ANTDIV - #elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY)) - #define CONFIG_2G5G_SUPPORT_ANTDIV - #endif - /*----------*/ - #endif +/*20170103 YuChen add for FW API*/ +#define PHYDM_FW_API_ENABLE_8822B 1 +#define PHYDM_FW_API_FUNC_ENABLE_8822B 1 +#define PHYDM_FW_API_ENABLE_8821C 1 +#define PHYDM_FW_API_FUNC_ENABLE_8821C 1 +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "phydm_features_win.h" #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - #if (RTL8822B_SUPPORT == 1) - #define PHYDM_TXA_CALIBRATION 1 - #else - #define PHYDM_TXA_CALIBRATION 0 - #endif - - #if (RTL8192E_SUPPORT == 1) - #define PHYDM_PRIMARY_CCA 1 - #else - #define PHYDM_PRIMARY_CCA 0 - #endif - - #if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - #define PHYDM_DC_CANCELLATION 1 - #else - #define PHYDM_DC_CANCELLATION 0 - #endif - - #define CONFIG_PSD_TOOL 1 - /*phydm debyg report & tools*/ - #define CONFIG_PHYDM_DEBUG_FUNCTION 1 - - #if (RTL8822B_SUPPORT == 1) - #define CONFIG_DYNAMIC_RX_PATH 0 - #else - #define CONFIG_DYNAMIC_RX_PATH 0 - #endif - - #define PHYDM_SUPPORT_CCKPD 1 - #define RA_MASK_PHYDMLIZE_CE 1 - - /*Antenna Diversity*/ - #ifdef CONFIG_ANTENNA_DIVERSITY - #define CONFIG_PHYDM_ANTENNA_DIVERSITY - - #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY - - #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) - #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY - #endif - - #if (RTL8821A_SUPPORT == 1) - /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ - #endif - - #if (RTL8822B_SUPPORT == 1) - /*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ - #endif - #endif - #endif - - #ifdef CONFIG_DFS_MASTER - #define CONFIG_PHYDM_DFS_MASTER - #endif - - #if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) - #define CONFIG_RECEIVER_BLOCKING - #endif - /*#define CONFIG_RA_DBG_CMD*/ - #define CONFIG_RA_FW_DBG_CODE 0 - /*#define CONFIG_ANT_DETECTION*/ - /*#define CONFIG_PATH_DIVERSITY*/ - /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ - #define CONFIG_BB_POWER_SAVING - #define CONFIG_BB_TXBF_API - - #ifdef CONFIG_BT_COEXIST - #define BT_SUPPORT 1 - #endif - - + #include "phydm_features_ce.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "phydm_features_ap.h" #endif - - /*20170103 YuChen add for FW API*/ - #define PHYDM_FW_API_ENABLE_8822B 1 - #define PHYDM_FW_API_FUNC_ENABLE_8822B 1 - #define PHYDM_FW_API_ENABLE_8821C 1 - #define PHYDM_FW_API_FUNC_ENABLE_8821C 1 - #endif diff --git a/hal/phydm/phydm_hwconfig.c b/hal/phydm/phydm_hwconfig.c index 1aa3a94..9e4a6fd 100644 --- a/hal/phydm/phydm_hwconfig.c +++ b/hal/phydm/phydm_hwconfig.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -20,13 +30,13 @@ #include "mp_precomp.h" #include "phydm_precomp.h" -#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(p_dm_odm)) -#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(p_dm_odm)) +#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(dm)) +#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(dm)) #if (PHYDM_TESTCHIP_SUPPORT == 1) #define READ_AND_CONFIG(ic, txt) do {\ - if (p_dm_odm->is_mp_chip)\ + if (dm->is_mp_chip)\ READ_AND_CONFIG_MP(ic, txt);\ else\ READ_AND_CONFIG_TC(ic, txt);\ @@ -35,2088 +45,49 @@ #define READ_AND_CONFIG READ_AND_CONFIG_MP #endif - -#define READ_FIRMWARE_MP(ic, txt) (odm_read_firmware_mp_##ic##txt(p_dm_odm, p_firmware, p_size)) -#define READ_FIRMWARE_TC(ic, txt) (odm_read_firmware_tc_##ic##txt(p_dm_odm, p_firmware, p_size)) - -#if (PHYDM_TESTCHIP_SUPPORT == 1) -#define READ_FIRMWARE(ic, txt) do {\ - if (p_dm_odm->is_mp_chip)\ - READ_FIRMWARE_MP(ic, txt);\ - else\ - READ_FIRMWARE_TC(ic, txt);\ - } while (0) -#else -#define READ_FIRMWARE READ_FIRMWARE_MP -#endif - #define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt()) #define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt()) -#if (PHYDM_TESTCHIP_SUPPORT == 1) - #define GET_VERSION(ic, txt) (p_dm_odm->is_mp_chip ? GET_VERSION_MP(ic, txt) : GET_VERSION_TC(ic, txt)) -#else - #define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt) -#endif - -void -phydm_rx_statistic_cal( - struct PHY_DM_STRUCT *p_phydm, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - struct _phy_status_rpt_jaguar2_type1 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type1 *)p_phy_status; -#endif - u8 date_rate = (p_pktinfo->data_rate & 0x7f); - - if (date_rate <= ODM_RATE54M) { - - p_phydm->phy_dbg_info.num_qry_legacy_pkt[date_rate]++; - /**/ - } else if (date_rate <= ODM_RATEMCS31) { - - p_phydm->phy_dbg_info.num_qry_ht_pkt[date_rate - ODM_RATEMCS0]++; - p_phydm->phy_dbg_info.ht_pkt_not_zero = true; - - } - #if ODM_IC_11AC_SERIES_SUPPORT - else if (date_rate <= ODM_RATEVHTSS4MCS9) { - - #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63) && (p_phydm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE)) { - - p_phydm->phy_dbg_info.num_qry_mu_vht_pkt[date_rate - ODM_RATEVHTSS1MCS0]++; - p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate | BIT(7); - p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid; - - } else - #endif - { - p_phydm->phy_dbg_info.num_qry_vht_pkt[date_rate - ODM_RATEVHTSS1MCS0]++; - p_phydm->phy_dbg_info.vht_pkt_not_zero = true; - #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate; - p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid; - #endif - } - } - #endif -} - -void -phydm_reset_avg_rssi_for_ss( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - p_dm_odm->phy_dbg_info.rssi_cck_sum = 0; - p_dm_odm->phy_dbg_info.rssi_cck_cnt = 0; - - p_dm_odm->phy_dbg_info.rssi_ofdm_sum = 0; - p_dm_odm->phy_dbg_info.rssi_ofdm_cnt = 0; - - p_dm_odm->phy_dbg_info.rssi_1ss_sum = 0; - p_dm_odm->phy_dbg_info.rssi_1ss_cnt = 0; - - p_dm_odm->phy_dbg_info.rssi_2ss_sum[0] = 0; - p_dm_odm->phy_dbg_info.rssi_2ss_sum[1] = 0; - p_dm_odm->phy_dbg_info.rssi_2ss_cnt = 0; - - p_dm_odm->phy_dbg_info.rssi_3ss_sum[0] = 0; - p_dm_odm->phy_dbg_info.rssi_3ss_sum[1] = 0; - p_dm_odm->phy_dbg_info.rssi_3ss_sum[2] = 0; - p_dm_odm->phy_dbg_info.rssi_3ss_cnt = 0; - - p_dm_odm->phy_dbg_info.rssi_4ss_sum[0] = 0; - p_dm_odm->phy_dbg_info.rssi_4ss_sum[1] = 0; - p_dm_odm->phy_dbg_info.rssi_4ss_sum[2] = 0; - p_dm_odm->phy_dbg_info.rssi_4ss_sum[3] = 0; - p_dm_odm->phy_dbg_info.rssi_4ss_cnt = 0; - -} - -void -phydm_avg_rssi_for_ss( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - u8 rate_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); - - if (p_pktinfo->data_rate <= ODM_RATE11M) { - p_dm_odm->phy_dbg_info.rssi_cck_sum += p_phy_info->rx_mimo_signal_strength[0]; - p_dm_odm->phy_dbg_info.rssi_cck_cnt++; - } else if (p_pktinfo->data_rate <= ODM_RATE54M) { - p_dm_odm->phy_dbg_info.rssi_ofdm_sum += p_phy_info->rx_mimo_signal_strength[0]; - p_dm_odm->phy_dbg_info.rssi_ofdm_cnt++; - } else if (rate_ss == 1) { - p_dm_odm->phy_dbg_info.rssi_1ss_sum += p_phy_info->rx_mimo_signal_strength[0]; - p_dm_odm->phy_dbg_info.rssi_1ss_cnt++; - } else if (rate_ss == 2) { - p_dm_odm->phy_dbg_info.rssi_2ss_sum[0] += p_phy_info->rx_mimo_signal_strength[0]; - p_dm_odm->phy_dbg_info.rssi_2ss_sum[1] += p_phy_info->rx_mimo_signal_strength[1]; - p_dm_odm->phy_dbg_info.rssi_2ss_cnt++; - } else if (rate_ss == 3) { - p_dm_odm->phy_dbg_info.rssi_3ss_sum[0] += p_phy_info->rx_mimo_signal_strength[0]; - p_dm_odm->phy_dbg_info.rssi_3ss_sum[1] += p_phy_info->rx_mimo_signal_strength[1]; - p_dm_odm->phy_dbg_info.rssi_3ss_sum[2] += p_phy_info->rx_mimo_signal_strength[2]; - p_dm_odm->phy_dbg_info.rssi_3ss_cnt++; - } else if (rate_ss == 4) { - p_dm_odm->phy_dbg_info.rssi_4ss_sum[0] += p_phy_info->rx_mimo_signal_strength[0]; - p_dm_odm->phy_dbg_info.rssi_4ss_sum[1] += p_phy_info->rx_mimo_signal_strength[1]; - p_dm_odm->phy_dbg_info.rssi_4ss_sum[2] += p_phy_info->rx_mimo_signal_strength[2]; - p_dm_odm->phy_dbg_info.rssi_4ss_sum[3] += p_phy_info->rx_mimo_signal_strength[3]; - p_dm_odm->phy_dbg_info.rssi_4ss_cnt++; - } -} - -u8 phydm_get_signal_quality(struct _odm_phy_status_info_ *p_phy_info,struct PHY_DM_STRUCT *p_dm_odm, struct _phy_status_rpt_8192cd *p_phy_sta_rpt) -{ - u8 SQ_rpt; - if (p_phy_info->rx_pwdb_all > 40 && !p_dm_odm->is_in_hct_test) - return 100; - else { - SQ_rpt = p_phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all; - - if (SQ_rpt > 64) - return 0; - else if (SQ_rpt < 20) - return 100; - else - return ((64 - SQ_rpt) * 100) / 44; - - } -} - -u8 -odm_query_rx_pwr_percentage( - s8 ant_power -) -{ - if ((ant_power <= -100) || (ant_power >= 20)) - return 0; - else if (ant_power >= 0) - return 100; - else - return 100 + ant_power; -} - - -/* - * 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. - * IF other SW team do not support the feature, remove this section.?? - * */ -s32 -odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_lenovo( - struct PHY_DM_STRUCT *p_dm_odm, - s32 curr_sig -) -{ - s32 ret_sig = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* if(p_dm_odm->support_interface == ODM_ITRF_PCIE) */ - { - /* step 1. Scale mapping. */ - /* 20100611 Joseph: Re-tunning RSSI presentation for Lenovo. */ - /* 20100426 Joseph: Modify Signal strength mapping. */ - /* This modification makes the RSSI indication similar to Intel solution. */ - /* 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE. */ - if (curr_sig >= 54 && curr_sig <= 100) - ret_sig = 100; - else if (curr_sig >= 42 && curr_sig <= 53) - ret_sig = 95; - else if (curr_sig >= 36 && curr_sig <= 41) - ret_sig = 74 + ((curr_sig - 36) * 20) / 6; - else if (curr_sig >= 33 && curr_sig <= 35) - ret_sig = 65 + ((curr_sig - 33) * 8) / 2; - else if (curr_sig >= 18 && curr_sig <= 32) - ret_sig = 62 + ((curr_sig - 18) * 2) / 15; - else if (curr_sig >= 15 && curr_sig <= 17) - ret_sig = 33 + ((curr_sig - 15) * 28) / 2; - else if (curr_sig >= 10 && curr_sig <= 14) - ret_sig = 39; - else if (curr_sig >= 8 && curr_sig <= 9) - ret_sig = 33; - else if (curr_sig <= 8) - ret_sig = 19; - } -#endif /* ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ - return ret_sig; -} - -s32 -odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_netcore( - struct PHY_DM_STRUCT *p_dm_odm, - s32 curr_sig -) -{ - s32 ret_sig = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* if(p_dm_odm->support_interface == ODM_ITRF_USB) */ - { - /* Netcore request this modification because 2009.04.13 SU driver use it. */ - if (curr_sig >= 31 && curr_sig <= 100) - ret_sig = 100; - else if (curr_sig >= 21 && curr_sig <= 30) - ret_sig = 90 + ((curr_sig - 20) / 1); - else if (curr_sig >= 11 && curr_sig <= 20) - ret_sig = 80 + ((curr_sig - 10) / 1); - else if (curr_sig >= 7 && curr_sig <= 10) - ret_sig = 69 + (curr_sig - 7); - else if (curr_sig == 6) - ret_sig = 54; - else if (curr_sig == 5) - ret_sig = 45; - else if (curr_sig == 4) - ret_sig = 36; - else if (curr_sig == 3) - ret_sig = 27; - else if (curr_sig == 2) - ret_sig = 18; - else if (curr_sig == 1) - ret_sig = 9; - else - ret_sig = curr_sig; - } -#endif /* ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ - return ret_sig; -} - - -s32 -odm_signal_scale_mapping_92c_series( - struct PHY_DM_STRUCT *p_dm_odm, - s32 curr_sig -) -{ - s32 ret_sig = 0; -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) { - /* step 1. Scale mapping. */ - if (curr_sig >= 61 && curr_sig <= 100) - ret_sig = 90 + ((curr_sig - 60) / 4); - else if (curr_sig >= 41 && curr_sig <= 60) - ret_sig = 78 + ((curr_sig - 40) / 2); - else if (curr_sig >= 31 && curr_sig <= 40) - ret_sig = 66 + (curr_sig - 30); - else if (curr_sig >= 21 && curr_sig <= 30) - ret_sig = 54 + (curr_sig - 20); - else if (curr_sig >= 5 && curr_sig <= 20) - ret_sig = 42 + (((curr_sig - 5) * 2) / 3); - else if (curr_sig == 4) - ret_sig = 36; - else if (curr_sig == 3) - ret_sig = 27; - else if (curr_sig == 2) - ret_sig = 18; - else if (curr_sig == 1) - ret_sig = 9; - else - ret_sig = curr_sig; - } -#endif - -#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - if ((p_dm_odm->support_interface == ODM_ITRF_USB) || (p_dm_odm->support_interface == ODM_ITRF_SDIO)) { - if (curr_sig >= 51 && curr_sig <= 100) - ret_sig = 100; - else if (curr_sig >= 41 && curr_sig <= 50) - ret_sig = 80 + ((curr_sig - 40) * 2); - else if (curr_sig >= 31 && curr_sig <= 40) - ret_sig = 66 + (curr_sig - 30); - else if (curr_sig >= 21 && curr_sig <= 30) - ret_sig = 54 + (curr_sig - 20); - else if (curr_sig >= 10 && curr_sig <= 20) - ret_sig = 42 + (((curr_sig - 10) * 2) / 3); - else if (curr_sig >= 5 && curr_sig <= 9) - ret_sig = 22 + (((curr_sig - 5) * 3) / 2); - else if (curr_sig >= 1 && curr_sig <= 4) - ret_sig = 6 + (((curr_sig - 1) * 3) / 2); - else - ret_sig = curr_sig; - } - -#endif - return ret_sig; -} -s32 -odm_signal_scale_mapping( - struct PHY_DM_STRUCT *p_dm_odm, - s32 curr_sig -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->support_interface != ODM_ITRF_PCIE) && /* USB & SDIO */ - (p_dm_odm->patch_id == 10)) /* p_mgnt_info->customer_id == RT_CID_819x_Netcore */ - return odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_netcore(p_dm_odm, curr_sig); - else if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->support_interface == ODM_ITRF_PCIE) && - (p_dm_odm->patch_id == 19)) /* p_mgnt_info->customer_id == RT_CID_819X_LENOVO) */ - return odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_lenovo(p_dm_odm, curr_sig); - else -#endif - { -#ifdef CONFIG_SIGNAL_SCALE_MAPPING - return odm_signal_scale_mapping_92c_series(p_dm_odm, curr_sig); -#else - return curr_sig; -#endif - } - -} - - - -static u8 odm_sq_process_patch_rt_cid_819x_lenovo( - struct PHY_DM_STRUCT *p_dm_odm, - u8 is_cck_rate, - u8 PWDB_ALL, - u8 path, - u8 RSSI -) -{ - u8 SQ = 0; -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - if (is_cck_rate) { - - if (IS_HARDWARE_TYPE_8192E(p_dm_odm->adapter)) { - - /* */ - /* Expected signal strength and bars indication at Lenovo lab. 2013.04.11 */ - /* 802.11n, 802.11b, 802.11g only at channel 6 */ - /* */ - /* Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm) */ - /* 50 5 -49 */ - /* 55 5 -49 */ - /* 60 5 -50 */ - /* 65 5 -51 */ - /* 70 5 -52 */ - /* 75 5 -54 */ - /* 80 5 -55 */ - /* 85 4 -60 */ - /* 90 3 -63 */ - /* 95 3 -65 */ - /* 100 2 -67 */ - /* 102 2 -67 */ - /* 104 1 -70 */ - /* */ - - if (PWDB_ALL >= 50) - SQ = 100; - else if (PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if (PWDB_ALL >= 31 && PWDB_ALL < 35) - SQ = 60; - else if (PWDB_ALL >= 22 && PWDB_ALL < 31) - SQ = 40; - else if (PWDB_ALL >= 18 && PWDB_ALL < 22) - SQ = 20; - else - SQ = 10; - } else { - if (PWDB_ALL >= 50) - SQ = 100; - else if (PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if (PWDB_ALL >= 22 && PWDB_ALL < 35) - SQ = 60; - else if (PWDB_ALL >= 18 && PWDB_ALL < 22) - SQ = 40; - else - SQ = 10; - } - - } else { - /* OFDM rate */ - - if (IS_HARDWARE_TYPE_8192E(p_dm_odm->adapter)) { - if (RSSI >= 45) - SQ = 100; - else if (RSSI >= 22 && RSSI < 45) - SQ = 80; - else if (RSSI >= 18 && RSSI < 22) - SQ = 40; - else - SQ = 20; - } else { - if (RSSI >= 45) - SQ = 100; - else if (RSSI >= 22 && RSSI < 45) - SQ = 80; - else if (RSSI >= 18 && RSSI < 22) - SQ = 40; - else - SQ = 20; - } - } - - RT_TRACE(COMP_DBG, DBG_TRACE, ("is_cck_rate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", is_cck_rate, PWDB_ALL, RSSI, SQ)); - -#endif - return SQ; -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -static u8 odm_sq_process_patch_rt_cid_819x_acer( - struct PHY_DM_STRUCT *p_dm_odm, - u8 is_cck_rate, - u8 PWDB_ALL, - u8 path, - u8 RSSI -) -{ - u8 SQ = 0; - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - if (is_cck_rate) { - - RT_TRACE(COMP_DBG, DBG_WARNING, ("odm_SQ_process_patch_RT_Acer\n")); - -#if OS_WIN_FROM_WIN8(OS_VERSION) - - if (PWDB_ALL >= 50) - SQ = 100; - else if (PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if (PWDB_ALL >= 30 && PWDB_ALL < 35) - SQ = 60; - else if (PWDB_ALL >= 25 && PWDB_ALL < 30) - SQ = 40; - else if (PWDB_ALL >= 20 && PWDB_ALL < 25) - SQ = 20; - else - SQ = 10; -#else - if (PWDB_ALL >= 50) - SQ = 100; - else if (PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if (PWDB_ALL >= 30 && PWDB_ALL < 35) - SQ = 60; - else if (PWDB_ALL >= 25 && PWDB_ALL < 30) - SQ = 40; - else if (PWDB_ALL >= 20 && PWDB_ALL < 25) - SQ = 20; - else - SQ = 10; - - if (PWDB_ALL == 0) /* Abnormal case, do not indicate the value above 20 on Win7 */ - SQ = 20; -#endif - - - - } else { - /* OFDM rate */ - - if (IS_HARDWARE_TYPE_8192E(p_dm_odm->adapter)) { - if (RSSI >= 45) - SQ = 100; - else if (RSSI >= 22 && RSSI < 45) - SQ = 80; - else if (RSSI >= 18 && RSSI < 22) - SQ = 40; - else - SQ = 20; - } else { - if (RSSI >= 35) - SQ = 100; - else if (RSSI >= 30 && RSSI < 35) - SQ = 80; - else if (RSSI >= 25 && RSSI < 30) - SQ = 40; - else - SQ = 20; - } - } - - RT_TRACE(COMP_DBG, DBG_LOUD, ("is_cck_rate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", is_cck_rate, PWDB_ALL, RSSI, SQ)); - -#endif - return SQ; -} -#endif - -static u8 -odm_evm_db_to_percentage( - s8 value -) -{ - /* */ - /* -33dB~0dB to 0%~99% */ - /* */ - s8 ret_val; - - ret_val = value; - ret_val /= 2; - - /*dbg_print("value=%d\n", value);*/ - /*ODM_RT_DISP(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C value=%d / %x\n", ret_val, ret_val));*/ -#ifdef ODM_EVM_ENHANCE_ANTDIV - if (ret_val >= 0) - ret_val = 0; - - if (ret_val <= -40) - ret_val = -40; - - ret_val = 0 - ret_val; - ret_val *= 3; -#else - if (ret_val >= 0) - ret_val = 0; - - if (ret_val <= -33) - ret_val = -33; - - ret_val = 0 - ret_val; - ret_val *= 3; - - if (ret_val == 99) - ret_val = 100; -#endif - - return (u8)ret_val; -} - -static u8 -odm_evm_dbm_jaguar_series( - s8 value -) -{ - s8 ret_val = value; - - /* -33dB~0dB to 33dB ~ 0dB */ - if (ret_val == -128) - ret_val = 127; - else if (ret_val < 0) - ret_val = 0 - ret_val; - - ret_val = ret_val >> 1; - return (u8)ret_val; -} - -static s16 -odm_cfo( - s8 value -) -{ - s16 ret_val; - - if (value < 0) { - ret_val = 0 - value; - ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */ - ret_val = ret_val | BIT(12); /* set bit12 as 1 for negative cfo */ - } else { - ret_val = value; - ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */ - } - return ret_val; -} - -u8 -phydm_rate_to_num_ss( - struct PHY_DM_STRUCT *p_dm_odm, - u8 data_rate -) -{ - u8 num_ss = 1; - - if (data_rate <= ODM_RATE54M) - num_ss = 1; - else if (data_rate <= ODM_RATEMCS31) - num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1; - else if (data_rate <= ODM_RATEVHTSS1MCS9) - num_ss = 1; - else if (data_rate <= ODM_RATEVHTSS2MCS9) - num_ss = 2; - else if (data_rate <= ODM_RATEVHTSS3MCS9) - num_ss = 3; - else if (data_rate <= ODM_RATEVHTSS4MCS9) - num_ss = 4; - - return num_ss; -} - -#if (ODM_IC_11N_SERIES_SUPPORT == 1) - -#if (RTL8703B_SUPPORT == 1) -s8 -odm_CCKRSSI_8703B( - u16 LNA_idx, - u8 VGA_idx -) -{ - s8 rx_pwr_all = 0x00; - - switch (LNA_idx) { - case 0xf: - rx_pwr_all = -48 - (2 * VGA_idx); - break; - case 0xb: - rx_pwr_all = -42 - (2 * VGA_idx); /*TBD*/ - break; - case 0xa: - rx_pwr_all = -36 - (2 * VGA_idx); - break; - case 8: - rx_pwr_all = -32 - (2 * VGA_idx); - break; - case 7: - rx_pwr_all = -19 - (2 * VGA_idx); - break; - case 4: - rx_pwr_all = -6 - (2 * VGA_idx); - break; - case 0: - rx_pwr_all = -2 - (2 * VGA_idx); - break; - default: - /*rx_pwr_all = -53+(2*(31-VGA_idx));*/ - /*dbg_print("wrong LNA index\n");*/ - break; - - } - return rx_pwr_all; -} -#endif - -#if (RTL8195A_SUPPORT == 1) -s8 -odm_CCKRSSI_8195A( - struct PHY_DM_STRUCT *p_dm_odm, - u16 LNA_idx, - u8 VGA_idx -) -{ - s8 rx_pwr_all = 0; - s8 lna_gain = 0; - s8 lna_gain_table_0[8] = {0, -8, -15, -22, -29, -36, -45, -54}; - s8 lna_gain_table_1[8] = {0, -8, -15, -22, -29, -36, -45, -54};/*use 8195A to calibrate this table. 2016.06.24, Dino*/ - - if (p_dm_odm->cck_agc_report_type == 0) - lna_gain = lna_gain_table_0[LNA_idx]; - else - lna_gain = lna_gain_table_1[LNA_idx]; - - rx_pwr_all = lna_gain - (2 * VGA_idx); - - return rx_pwr_all; -} -#endif - -#if (RTL8192E_SUPPORT == 1) -s8 -odm_CCKRSSI_8192E( - struct PHY_DM_STRUCT *p_dm_odm, - u16 LNA_idx, - u8 VGA_idx -) -{ - s8 rx_pwr_all = 0; - s8 lna_gain = 0; - s8 lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44}; - s8 lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36};/*use 8192EU to calibrate this table. 2015.12.15, Dino*/ - - if (p_dm_odm->cck_agc_report_type == 0) - lna_gain = lna_gain_table_0[LNA_idx]; - else - lna_gain = lna_gain_table_1[LNA_idx]; - - rx_pwr_all = lna_gain - (2 * VGA_idx); - - return rx_pwr_all; -} -#endif - -#if (RTL8188E_SUPPORT == 1) -s8 -odm_CCKRSSI_8188E( - struct PHY_DM_STRUCT *p_dm_odm, - u16 LNA_idx, - u8 VGA_idx -) -{ - s8 rx_pwr_all = 0; - s8 lna_gain = 0; - s8 lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41};/*only use lna0/1/2/3/7*/ - s8 lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; /*only use lna3 /7*/ - - if (p_dm_odm->cut_version >= ODM_CUT_I) /*SMIC*/ - lna_gain = lna_gain_table_0[LNA_idx]; - else /*TSMC*/ - lna_gain = lna_gain_table_1[LNA_idx]; - - rx_pwr_all = lna_gain - (2 * VGA_idx); - - return rx_pwr_all; -} -#endif - -void -odm_rx_phy_status92c_series_parsing( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - u8 i, max_spatial_stream; - s8 rx_pwr[4], rx_pwr_all = 0; - u8 EVM, PWDB_ALL = 0, PWDB_ALL_BT; - u8 RSSI, total_rssi = 0; - boolean is_cck_rate = false; - u8 rf_rx_num = 0; - u8 LNA_idx = 0; - u8 VGA_idx = 0; - u8 cck_agc_rpt; - u8 num_ss; - u8 stream_rxevm_tmp = 0; - struct _phy_status_rpt_8192cd *p_phy_sta_rpt = (struct _phy_status_rpt_8192cd *)p_phy_status; - - is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false; - p_dm_odm->rate_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); - - if (p_pktinfo->is_to_self) - p_dm_odm->curr_station_id = p_pktinfo->station_id; - - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1; - - - if (is_cck_rate) { - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++; - cck_agc_rpt = p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a ; - - if (p_dm_odm->support_ic_type & (ODM_RTL8703B)) { - -#if (RTL8703B_SUPPORT == 1) - if (p_dm_odm->cck_agc_report_type == 1) { /*4 bit LNA*/ - - u8 cck_agc_rpt_b = (p_phy_sta_rpt->cck_rpt_b_ofdm_cfosho_b & BIT(7)) ? 1 : 0; - - LNA_idx = (cck_agc_rpt_b << 3) | ((cck_agc_rpt & 0xE0) >> 5); - VGA_idx = (cck_agc_rpt & 0x1F); - - rx_pwr_all = odm_CCKRSSI_8703B(LNA_idx, VGA_idx); - } -#endif - } else { /*3 bit LNA*/ - - LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); - VGA_idx = (cck_agc_rpt & 0x1F); - - if (p_dm_odm->support_ic_type & (ODM_RTL8188E)) { - -#if (RTL8188E_SUPPORT == 1) - rx_pwr_all = odm_CCKRSSI_8188E(p_dm_odm, LNA_idx, VGA_idx); - /**/ -#endif - } -#if (RTL8192E_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { - - rx_pwr_all = odm_CCKRSSI_8192E(p_dm_odm, LNA_idx, VGA_idx); - /**/ - } -#endif -#if (RTL8723B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & (ODM_RTL8723B)) { - - rx_pwr_all = odm_CCKRSSI_8723B(LNA_idx, VGA_idx); - /**/ - } -#endif -#if (RTL8188F_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & (ODM_RTL8188F)) { - - rx_pwr_all = odm_CCKRSSI_8188F(LNA_idx, VGA_idx); - /**/ - } -#endif -#if (RTL8195A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & (ODM_RTL8195A)) { - - rx_pwr_all = odm_CCKRSSI_8195A(LNA_idx, VGA_idx); - /**/ - } -#endif - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ext_lna_gain (( %d )), LNA_idx: (( 0x%x )), VGA_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n", - p_dm_odm->ext_lna_gain, LNA_idx, VGA_idx, rx_pwr_all)); - - if (p_dm_odm->board_type & ODM_BOARD_EXT_LNA) - rx_pwr_all -= p_dm_odm->ext_lna_gain; - - PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - - if (p_pktinfo->is_to_self) { - p_dm_odm->cck_lna_idx = LNA_idx; - p_dm_odm->cck_vga_idx = VGA_idx; - } - p_phy_info->rx_pwdb_all = PWDB_ALL; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->bt_rx_rssi_percentage = PWDB_ALL; - p_phy_info->recv_signal_power = rx_pwr_all; -#endif - /* */ - /* (3) Get Signal Quality (EVM) */ - /* */ - /* if(p_pktinfo->is_packet_match_bssid) */ - { - u8 SQ; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) - SQ = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, 0, 0); - else if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->patch_id == RT_CID_819X_ACER)) - SQ = odm_sq_process_patch_rt_cid_819x_acer(p_dm_odm, is_cck_rate, PWDB_ALL, 0, 0); - else -#endif - SQ = phydm_get_signal_quality(p_phy_info, p_dm_odm, p_phy_sta_rpt); - - /* dbg_print("cck SQ = %d\n", SQ); */ - p_phy_info->signal_quality = SQ; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = SQ; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1; - } - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) { - if (i == 0) - p_phy_info->rx_mimo_signal_strength[0] = PWDB_ALL; - else - p_phy_info->rx_mimo_signal_strength[1] = 0; - } - } else { /* 2 is OFDM rate */ - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; - - /* */ - /* (1)Get RSSI for HT rate */ - /* */ - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) { - /* 2008/01/30 MH we will judge RF RX path now. */ - if (p_dm_odm->rf_path_rx_enable & BIT(i)) - rf_rx_num++; - /* else */ - /* continue; */ - - rx_pwr[i] = ((p_phy_sta_rpt->path_agc[i].gain & 0x3F) * 2) - 110; - - if (p_pktinfo->is_to_self) { - p_dm_odm->ofdm_agc_idx[i] = (p_phy_sta_rpt->path_agc[i].gain & 0x3F); - /**/ - } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->rx_pwr[i] = rx_pwr[i]; -#endif - - /* Translate DBM to percentage. */ - RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]); - total_rssi += RSSI; - /* RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); */ - - p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI; - -#if (DM_ODM_SUPPORT_TYPE & (/*ODM_WIN|*/ODM_CE|ODM_AP)) - /* Get Rx snr value in DB */ - p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = (s32)(p_phy_sta_rpt->path_rxsnr[i] / 2); -#endif - - /* Record Signal Strength for next packet */ - /* if(p_pktinfo->is_packet_match_bssid) */ - { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) { - if (i == ODM_RF_PATH_A) - p_phy_info->signal_quality = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, i, RSSI); - - } else if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->patch_id == RT_CID_819X_ACER)) - p_phy_info->signal_quality = odm_sq_process_patch_rt_cid_819x_acer(p_dm_odm, is_cck_rate, PWDB_ALL, 0, RSSI); -#endif - } - } - - - /* */ - /* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */ - /* */ - rx_pwr_all = (((p_phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all) >> 1) & 0x7f) - 110; - - PWDB_ALL_BT = PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - - - p_phy_info->rx_pwdb_all = PWDB_ALL; - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all)); */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->bt_rx_rssi_percentage = PWDB_ALL_BT; - p_phy_info->rx_power = rx_pwr_all; - p_phy_info->recv_signal_power = rx_pwr_all; -#endif - - if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 19)) { - /* do nothing */ - } else if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 25)) { - /* do nothing */ - } else { /* p_mgnt_info->customer_id != RT_CID_819X_LENOVO */ - /* */ - /* (3)EVM of HT rate */ - /* */ - if (p_pktinfo->data_rate >= ODM_RATEMCS8 && p_pktinfo->data_rate <= ODM_RATEMCS15) - max_spatial_stream = 2; /* both spatial stream make sense */ - else - max_spatial_stream = 1; /* only spatial stream 1 makes sense */ - - for (i = 0; i < max_spatial_stream; i++) { - /* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */ - /* fill most significant bit to "zero" when doing shifting operation which may change a negative */ - /* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */ - EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->stream_rxevm[i])); /* dbm */ - - /* GET_RX_STATUS_DESC_RX_MCS(p_desc), p_drv_info->rxevm[i], "%", EVM)); */ -#if 0 - /* if(p_pktinfo->is_packet_match_bssid) */ - { -#endif - if (i == ODM_RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */ - p_phy_info->signal_quality = (u8)(EVM & 0xff); - p_phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff); - - if (p_phy_sta_rpt->stream_rxevm[i] < 0) - stream_rxevm_tmp = (u8)(0 - (p_phy_sta_rpt->stream_rxevm[i])); - - if (stream_rxevm_tmp == 64) - stream_rxevm_tmp = 0; - - p_phy_info->rx_mimo_evm_dbm[i] = stream_rxevm_tmp; -#if 0 - } -#endif - } - } - - num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); - odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->path_cfotail, num_ss); - - } -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - /* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */ - /* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */ - if (is_cck_rate) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */ - p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, PWDB_ALL, true, true); -#else - p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, PWDB_ALL));/*PWDB_ALL;*/ -#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ - } else { - if (rf_rx_num != 0) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */ - p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, (total_rssi /= rf_rx_num), true, false); -#else - p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, total_rssi /= rf_rx_num)); -#endif - } - } -#endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))*/ - - /* dbg_print("is_cck_rate = %d, p_phy_info->rx_pwdb_all = %d, p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a = 0x%x\n", */ - /* is_cck_rate, p_phy_info->rx_pwdb_all, p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a); */ - - /* For 92C/92D HW (Hybrid) Antenna Diversity */ -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - /* For 88E HW Antenna Diversity */ - p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->ant_sel; - p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->ant_sel_b; - p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antsel_rx_keep_2; -#endif - - if (p_pktinfo->is_packet_match_bssid) { - phydm_avg_rssi_for_ss(p_dm_odm, p_phy_info, p_pktinfo); - phydm_rx_statistic_cal(p_dm_odm, p_phy_status, p_pktinfo); - } - -} -#endif - -#if ODM_IC_11AC_SERIES_SUPPORT - -void -odm_rx_phy_bw_jaguar_series_parsing( - struct _odm_phy_status_info_ *p_phy_info, - struct _odm_per_pkt_info_ *p_pktinfo, - struct _phy_status_rpt_8812 *p_phy_sta_rpt -) -{ - - if (p_pktinfo->data_rate <= ODM_RATE54M) { - switch (p_phy_sta_rpt->r_RFMOD) { - case 1: - if (p_phy_sta_rpt->sub_chnl == 0) - p_phy_info->band_width = 1; - else - p_phy_info->band_width = 0; - break; - - case 2: - if (p_phy_sta_rpt->sub_chnl == 0) - p_phy_info->band_width = 2; - else if (p_phy_sta_rpt->sub_chnl == 9 || p_phy_sta_rpt->sub_chnl == 10) - p_phy_info->band_width = 1; - else - p_phy_info->band_width = 0; - break; - - default: - case 0: - p_phy_info->band_width = 0; - break; - } - } - -} - -void -odm_rx_phy_status_jaguar_series_parsing( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - u8 i, max_spatial_stream; - s8 rx_pwr[4], rx_pwr_all = 0; - u8 EVM = 0, evm_dbm, PWDB_ALL = 0, PWDB_ALL_BT; - u8 RSSI, avg_rssi = 0, best_rssi = 0, second_rssi = 0; - u8 is_cck_rate = 0; - u8 rf_rx_num = 0; - u8 cck_highpwr = 0; - u8 LNA_idx, VGA_idx; - struct _phy_status_rpt_8812 *p_phy_sta_rpt = (struct _phy_status_rpt_8812 *)p_phy_status; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u8 num_ss; - - odm_rx_phy_bw_jaguar_series_parsing(p_phy_info, p_pktinfo, p_phy_sta_rpt); - - is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false; - p_dm_odm->rate_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); - - if (p_pktinfo->is_to_self) - p_dm_odm->curr_station_id = p_pktinfo->station_id; - else - p_dm_odm->curr_station_id = 0xff; - - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_C] = -1; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_D] = -1; - - if (is_cck_rate) { - u8 cck_agc_rpt; - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++; - - /*(1)Hardware does not provide RSSI for CCK*/ - /*(2)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ - - /*if(p_hal_data->e_rf_power_state == e_rf_on)*/ - cck_highpwr = p_dm_odm->is_cck_high_power; - /*else*/ - /*cck_highpwr = false;*/ - - cck_agc_rpt = p_phy_sta_rpt->cfosho[0] ; - LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); - VGA_idx = (cck_agc_rpt & 0x1F); - - if (p_dm_odm->support_ic_type == ODM_RTL8812) { - switch (LNA_idx) { - case 7: - if (VGA_idx <= 27) - rx_pwr_all = -100 + 2 * (27 - VGA_idx); /*VGA_idx = 27~2*/ - else - rx_pwr_all = -100; - break; - case 6: - rx_pwr_all = -48 + 2 * (2 - VGA_idx); /*VGA_idx = 2~0*/ - break; - case 5: - rx_pwr_all = -42 + 2 * (7 - VGA_idx); /*VGA_idx = 7~5*/ - break; - case 4: - rx_pwr_all = -36 + 2 * (7 - VGA_idx); /*VGA_idx = 7~4*/ - break; - case 3: - /*rx_pwr_all = -28 + 2*(7-VGA_idx); VGA_idx = 7~0*/ - rx_pwr_all = -24 + 2 * (7 - VGA_idx); /*VGA_idx = 7~0*/ - break; - case 2: - if (cck_highpwr) - rx_pwr_all = -12 + 2 * (5 - VGA_idx); /*VGA_idx = 5~0*/ - else - rx_pwr_all = -6 + 2 * (5 - VGA_idx); - break; - case 1: - rx_pwr_all = 8 - 2 * VGA_idx; - break; - case 0: - rx_pwr_all = 14 - 2 * VGA_idx; - break; - default: - /*dbg_print("CCK Exception default\n");*/ - break; - } - rx_pwr_all += 6; - PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - - if (cck_highpwr == false) { - if (PWDB_ALL >= 80) - PWDB_ALL = ((PWDB_ALL - 80) << 1) + ((PWDB_ALL - 80) >> 1) + 80; - else if ((PWDB_ALL <= 78) && (PWDB_ALL >= 20)) - PWDB_ALL += 3; - if (PWDB_ALL > 100) - PWDB_ALL = 100; - } - } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { - s8 pout = -6; - - switch (LNA_idx) { - case 5: - rx_pwr_all = pout - 32 - (2 * VGA_idx); - break; - case 4: - rx_pwr_all = pout - 24 - (2 * VGA_idx); - break; - case 2: - rx_pwr_all = pout - 11 - (2 * VGA_idx); - break; - case 1: - rx_pwr_all = pout + 5 - (2 * VGA_idx); - break; - case 0: - rx_pwr_all = pout + 21 - (2 * VGA_idx); - break; - } - PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - } else if (p_dm_odm->support_ic_type == ODM_RTL8814A || p_dm_odm->support_ic_type == ODM_RTL8822B) { - s8 pout = -6; - - switch (LNA_idx) { - /*CCK only use LNA: 2, 3, 5, 7*/ - case 7: - rx_pwr_all = pout - 32 - (2 * VGA_idx); - break; - case 5: - rx_pwr_all = pout - 22 - (2 * VGA_idx); - break; - case 3: - rx_pwr_all = pout - 2 - (2 * VGA_idx); - break; - case 2: - rx_pwr_all = pout + 5 - (2 * VGA_idx); - break; - /*case 6:*/ - /*rx_pwr_all = pout -26 - (2*VGA_idx);*/ - /*break;*/ - /*case 4:*/ - /*rx_pwr_all = pout - 8 - (2*VGA_idx);*/ - /*break;*/ - /*case 1:*/ - /*rx_pwr_all = pout + 21 - (2*VGA_idx);*/ - /*break;*/ - /*case 0:*/ - /*rx_pwr_all = pout + 10 - (2*VGA_idx);*/ - /* break; */ - default: - /* dbg_print("CCK Exception default\n"); */ - break; - } - PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - } - - p_dm_odm->cck_lna_idx = LNA_idx; - p_dm_odm->cck_vga_idx = VGA_idx; - p_phy_info->rx_pwdb_all = PWDB_ALL; - /* if(p_pktinfo->station_id == 0) */ - /* { */ - /* dbg_print("CCK: LNA_idx = %d, VGA_idx = %d, p_phy_info->rx_pwdb_all = %d\n", */ - /* LNA_idx, VGA_idx, p_phy_info->rx_pwdb_all); */ - /* } */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->bt_rx_rssi_percentage = PWDB_ALL; - p_phy_info->recv_signal_power = rx_pwr_all; -#endif - /*(3) Get Signal Quality (EVM)*/ - /*if (p_pktinfo->is_packet_match_bssid)*/ - { - u8 SQ, SQ_rpt; - - if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) - SQ = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, 0, 0); - else if (p_phy_info->rx_pwdb_all > 40 && !p_dm_odm->is_in_hct_test) - SQ = 100; - else { - SQ_rpt = p_phy_sta_rpt->pwdb_all; - - if (SQ_rpt > 64) - SQ = 0; - else if (SQ_rpt < 20) - SQ = 100; - else - SQ = ((64 - SQ_rpt) * 100) / 44; - } - - /* dbg_print("cck SQ = %d\n", SQ); */ - p_phy_info->signal_quality = SQ; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = SQ; - } - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (i == 0) - p_phy_info->rx_mimo_signal_strength[0] = PWDB_ALL; - else - p_phy_info->rx_mimo_signal_strength[i] = 0; - } - } else { - /*is OFDM rate*/ - p_dm_fat_table->hw_antsw_occur = p_phy_sta_rpt->hw_antsw_occur; - - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; - - /*(1)Get RSSI for OFDM rate*/ - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - /*2008/01/30 MH we will judge RF RX path now.*/ - /* dbg_print("p_dm_odm->rf_path_rx_enable = %x\n", p_dm_odm->rf_path_rx_enable); */ - if (p_dm_odm->rf_path_rx_enable & BIT(i)) - rf_rx_num++; - /* else */ - /* continue; */ - /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ - /* if((p_dm_odm->support_ic_type & (ODM_RTL8812|ODM_RTL8821)) && (!p_dm_odm->is_mp_chip)) */ - if (i < ODM_RF_PATH_C) { - rx_pwr[i] = (p_phy_sta_rpt->gain_trsw[i] & 0x7F) - 110; - - if (p_pktinfo->is_to_self) - p_dm_odm->ofdm_agc_idx[i] = p_phy_sta_rpt->gain_trsw[i]; - - } else - rx_pwr[i] = (p_phy_sta_rpt->gain_trsw_cd[i - 2] & 0x7F) - 110; - /* else */ - /*rx_pwr[i] = ((p_phy_sta_rpt->gain_trsw[i]& 0x3F)*2) - 110; OLD FORMULA*/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->rx_pwr[i] = rx_pwr[i]; -#endif - - /* Translate DBM to percentage. */ - RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]); - - /*total_rssi += RSSI;*/ - /*Get the best two RSSI*/ - if (RSSI > best_rssi && RSSI > second_rssi) { - second_rssi = best_rssi; - best_rssi = RSSI; - } else if (RSSI > second_rssi && RSSI <= best_rssi) - second_rssi = RSSI; - - /*RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI));*/ - - p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI; - - - /*Get Rx snr value in DB*/ - if (i < ODM_RF_PATH_C) - p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->rxsnr[i] / 2; - else if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) - p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->csi_current[i - 2] / 2; - -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - /*(2) CFO_short & CFO_tail*/ - if (i < ODM_RF_PATH_C) { - p_phy_info->cfo_short[i] = odm_cfo((p_phy_sta_rpt->cfosho[i])); - p_phy_info->cfo_tail[i] = odm_cfo((p_phy_sta_rpt->cfotail[i])); - } -#endif - /* Record Signal Strength for next packet */ - if (p_pktinfo->is_packet_match_bssid) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) { - if (i == ODM_RF_PATH_A) - p_phy_info->signal_quality = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, i, RSSI); - - } -#endif - } - } - - /*(3)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ - - /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ - if ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) && (!p_dm_odm->is_mp_chip)) - rx_pwr_all = (p_phy_sta_rpt->pwdb_all & 0x7f) - 110; - else - rx_pwr_all = (((p_phy_sta_rpt->pwdb_all) >> 1) & 0x7f) - 110; /*OLD FORMULA*/ - - PWDB_ALL_BT = PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - - p_phy_info->rx_pwdb_all = PWDB_ALL; - /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all));*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->bt_rx_rssi_percentage = PWDB_ALL_BT; - p_phy_info->rx_power = rx_pwr_all; - p_phy_info->recv_signal_power = rx_pwr_all; -#endif - - if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 19)) { - /*do nothing*/ - } else { - /*p_mgnt_info->customer_id != RT_CID_819X_LENOVO*/ - - /*(4)EVM of OFDM rate*/ - - if ((p_pktinfo->data_rate >= ODM_RATEMCS8) && - (p_pktinfo->data_rate <= ODM_RATEMCS15)) - max_spatial_stream = 2; - else if ((p_pktinfo->data_rate >= ODM_RATEVHTSS2MCS0) && - (p_pktinfo->data_rate <= ODM_RATEVHTSS2MCS9)) - max_spatial_stream = 2; - else if ((p_pktinfo->data_rate >= ODM_RATEMCS16) && - (p_pktinfo->data_rate <= ODM_RATEMCS23)) - max_spatial_stream = 3; - else if ((p_pktinfo->data_rate >= ODM_RATEVHTSS3MCS0) && - (p_pktinfo->data_rate <= ODM_RATEVHTSS3MCS9)) - max_spatial_stream = 3; - else - max_spatial_stream = 1; - - /*if (p_pktinfo->is_packet_match_bssid) */ - { - /*dbg_print("p_pktinfo->data_rate = %d\n", p_pktinfo->data_rate);*/ - - for (i = 0; i < max_spatial_stream; i++) { - /*Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment*/ - /*fill most significant bit to "zero" when doing shifting operation which may change a negative*/ - /*value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.*/ - - if (p_pktinfo->data_rate >= ODM_RATE6M && p_pktinfo->data_rate <= ODM_RATE54M) { - if (i == ODM_RF_PATH_A) { - EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->sigevm)); /*dbm*/ - EVM += 20; - if (EVM > 100) - EVM = 100; - } - } else { - if (i < ODM_RF_PATH_C) { - if (p_phy_sta_rpt->rxevm[i] == -128) - p_phy_sta_rpt->rxevm[i] = -25; - EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->rxevm[i])); /*dbm*/ - } else { - if (p_phy_sta_rpt->rxevm_cd[i - 2] == -128) - p_phy_sta_rpt->rxevm_cd[i - 2] = -25; - EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->rxevm_cd[i - 2])); /*dbm*/ - } - } - - if (i < ODM_RF_PATH_C) - evm_dbm = odm_evm_dbm_jaguar_series(p_phy_sta_rpt->rxevm[i]); - else - evm_dbm = odm_evm_dbm_jaguar_series(p_phy_sta_rpt->rxevm_cd[i - 2]); - /*RT_DISP(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",*/ - /*p_pktinfo->data_rate, p_phy_sta_rpt->rxevm[i], "%", EVM));*/ - - { - if (i == ODM_RF_PATH_A) { - /*Fill value in RFD, Get the first spatial stream only*/ - p_phy_info->signal_quality = EVM; - } - p_phy_info->rx_mimo_signal_quality[i] = EVM; -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - p_phy_info->rx_mimo_evm_dbm[i] = evm_dbm; -#endif - } - } - } - } - - num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); - odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->cfotail, num_ss); - - } - /* dbg_print("is_cck_rate= %d, p_phy_info->signal_strength=%d % PWDB_AL=%d rf_rx_num=%d\n", is_cck_rate, p_phy_info->signal_strength, PWDB_ALL, rf_rx_num); */ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - /*UI BSS List signal strength(in percentage), make it good looking, from 0~100.*/ - /*It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().*/ - if (is_cck_rate) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /*2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ - p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, PWDB_ALL, false, true); -#else - p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, PWDB_ALL));/*PWDB_ALL;*/ -#endif - } else { - if (rf_rx_num != 0) { - /* 2015/01 Sean, use the best two RSSI only, suggested by Ynlin and ChenYu.*/ - if (rf_rx_num == 1) - avg_rssi = best_rssi; - else - avg_rssi = (best_rssi + second_rssi) / 2; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ - p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, avg_rssi, false, false); -#else - p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, avg_rssi)); -#endif - } - } -#endif - p_dm_odm->rx_pwdb_ave = p_dm_odm->rx_pwdb_ave + p_phy_info->rx_pwdb_all; - - p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_anta; - p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_antb; - p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_antc; - p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_antd; - - if (p_pktinfo->is_packet_match_bssid) { - phydm_avg_rssi_for_ss(p_dm_odm, p_phy_info, p_pktinfo); - phydm_rx_statistic_cal(p_dm_odm, p_phy_status, p_pktinfo); - } - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antidx_anta = ((%d)), MatchBSSID = ((%d))\n", p_pktinfo->station_id, p_phy_sta_rpt->antidx_anta, p_pktinfo->is_packet_match_bssid));*/ - - - /* dbg_print("p_phy_sta_rpt->antidx_anta = %d, p_phy_sta_rpt->antidx_antb = %d\n",*/ - /* p_phy_sta_rpt->antidx_anta, p_phy_sta_rpt->antidx_antb);*/ - /* dbg_print("----------------------------\n");*/ - /* dbg_print("p_pktinfo->station_id=%d, p_pktinfo->data_rate=0x%x\n",p_pktinfo->station_id, p_pktinfo->data_rate);*/ - /* dbg_print("p_phy_sta_rpt->r_RFMOD = %d\n", p_phy_sta_rpt->r_RFMOD);*/ - /* dbg_print("p_phy_sta_rpt->gain_trsw[0]=0x%x, p_phy_sta_rpt->gain_trsw[1]=0x%x\n",*/ - /* p_phy_sta_rpt->gain_trsw[0],p_phy_sta_rpt->gain_trsw[1]);*/ - /* dbg_print("p_phy_sta_rpt->gain_trsw[2]=0x%x, p_phy_sta_rpt->gain_trsw[3]=0x%x\n",*/ - /* p_phy_sta_rpt->gain_trsw_cd[0],p_phy_sta_rpt->gain_trsw_cd[1]);*/ - /* dbg_print("p_phy_sta_rpt->pwdb_all = 0x%x, p_phy_info->rx_pwdb_all = %d\n", p_phy_sta_rpt->pwdb_all, p_phy_info->rx_pwdb_all);*/ - /* dbg_print("p_phy_sta_rpt->cfotail[i] = 0x%x, p_phy_sta_rpt->CFO_tail[i] = 0x%x\n", p_phy_sta_rpt->cfotail[0], p_phy_sta_rpt->cfotail[1]);*/ - /* dbg_print("p_phy_sta_rpt->rxevm[0] = %d, p_phy_sta_rpt->rxevm[1] = %d\n", p_phy_sta_rpt->rxevm[0], p_phy_sta_rpt->rxevm[1]);*/ - /* dbg_print("p_phy_sta_rpt->rxevm[2] = %d, p_phy_sta_rpt->rxevm[3] = %d\n", p_phy_sta_rpt->rxevm_cd[0], p_phy_sta_rpt->rxevm_cd[1]);*/ - /* dbg_print("p_phy_info->rx_mimo_signal_strength[0]=%d, p_phy_info->rx_mimo_signal_strength[1]=%d, rx_pwdb_all=%d\n",*/ - /* p_phy_info->rx_mimo_signal_strength[0], p_phy_info->rx_mimo_signal_strength[1], p_phy_info->rx_pwdb_all);*/ - /* dbg_print("p_phy_info->rx_mimo_signal_strength[2]=%d, p_phy_info->rx_mimo_signal_strength[3]=%d\n",*/ - /* p_phy_info->rx_mimo_signal_strength[2], p_phy_info->rx_mimo_signal_strength[3]);*/ - /* dbg_print("ppPhyInfo->rx_mimo_signal_quality[0]=%d, p_phy_info->rx_mimo_signal_quality[1]=%d\n",*/ - /* p_phy_info->rx_mimo_signal_quality[0], p_phy_info->rx_mimo_signal_quality[1]);*/ - /* dbg_print("ppPhyInfo->rx_mimo_signal_quality[2]=%d, p_phy_info->rx_mimo_signal_quality[3]=%d\n",*/ - /* p_phy_info->rx_mimo_signal_quality[2], p_phy_info->rx_mimo_signal_quality[3]);*/ - -} - -#endif - -void -phydm_reset_rssi_for_dm( - struct PHY_DM_STRUCT *p_dm_odm, - u8 station_id -) -{ - struct sta_info *p_entry; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); -#endif - - p_entry = p_dm_odm->p_odm_sta_info[station_id]; - - if (!IS_STA_VALID(p_entry)) { - /**/ - return; - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("Reset RSSI for macid = (( %d ))\n", station_id)); - - - p_entry->rssi_stat.undecorated_smoothed_cck = -1; - p_entry->rssi_stat.undecorated_smoothed_ofdm = -1; - p_entry->rssi_stat.undecorated_smoothed_pwdb = -1; - p_entry->rssi_stat.ofdm_pkt = 0; - p_entry->rssi_stat.cck_pkt = 0; - p_entry->rssi_stat.cck_sum_power = 0; - p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT; - p_entry->rssi_stat.packet_map = 0; - p_entry->rssi_stat.valid_bit = 0; - - /*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - p_entry->bUsed = 0; - if (station_id == 0) { - - p_hal_data->UndecoratedSmoothedPWDB = -1; - /**/ - } -#endif - -} - -void -odm_init_rssi_for_dm( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - -} - -void -odm_process_rssi_for_dm( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - - s32 undecorated_smoothed_pwdb, undecorated_smoothed_cck, undecorated_smoothed_ofdm, rssi_ave; - u8 i, is_cck_rate = 0; - u8 RSSI_max, RSSI_min; - u32 weighting = 0; - u8 send_rssi_2_fw = 0; - struct sta_info *p_entry; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); -#endif - - if (p_pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) - return; - -#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(p_dm_odm, p_phy_info, p_pktinfo); -#endif - - /* */ - /* 2012/05/30 MH/Luke.Lee Add some description */ - /* In windows driver: AP/IBSS mode STA */ - /* */ - /* if (p_dm_odm->support_platform == ODM_WIN) */ - /* { */ - /* p_entry = p_dm_odm->p_odm_sta_info[p_dm_odm->pAidMap[p_pktinfo->station_id-1]]; */ - /* } */ - /* else */ - p_entry = p_dm_odm->p_odm_sta_info[p_pktinfo->station_id]; - - if (!IS_STA_VALID(p_entry)) { - return; - /**/ - } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - if ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) && - (p_dm_fat_table->enable_ctrl_frame_antdiv) - ) { - if (p_pktinfo->is_packet_match_bssid) - p_dm_odm->data_frame_num++; - - if ((p_dm_fat_table->use_ctrl_frame_antdiv)) { - if (!p_pktinfo->is_to_self)/*data frame + CTRL frame*/ - return; - } else { - if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/ - return; - } - } else -#endif - { - if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/ - return; - } - - if (p_pktinfo->is_packet_beacon) - p_dm_odm->phy_dbg_info.num_qry_beacon_pkt++; - - is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false; - p_dm_odm->rx_rate = p_pktinfo->data_rate; - - /* --------------Statistic for antenna/path diversity------------------ */ - if (p_dm_odm->support_ability & ODM_BB_ANT_DIV) { -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - odm_process_rssi_for_ant_div(p_dm_odm, p_phy_info, p_pktinfo); -#endif - } -#if (defined(CONFIG_PATH_DIVERSITY)) - else if (p_dm_odm->support_ability & ODM_BB_PATH_DIV) - phydm_process_rssi_for_path_div(p_dm_odm, p_phy_info, p_pktinfo); -#endif - /* -----------------Smart Antenna Debug Message------------------ */ - - undecorated_smoothed_cck = p_entry->rssi_stat.undecorated_smoothed_cck; - undecorated_smoothed_ofdm = p_entry->rssi_stat.undecorated_smoothed_ofdm; - undecorated_smoothed_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - - if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_beacon) { - - if (!is_cck_rate) { /* ofdm rate */ -#if (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) { - u8 RX_count = 0; - u32 RSSI_linear = 0; - - if (p_dm_odm->rx_ant_status & ODM_RF_A) { - p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - RX_count++; - RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]); - } else - p_dm_odm->RSSI_A = 0; - - if (p_dm_odm->rx_ant_status & ODM_RF_B) { - p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; - RX_count++; - RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]); - } else - p_dm_odm->RSSI_B = 0; - - if (p_dm_odm->rx_ant_status & ODM_RF_C) { - p_dm_odm->RSSI_C = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C]; - RX_count++; - RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C]); - } else - p_dm_odm->RSSI_C = 0; - - if (p_dm_odm->rx_ant_status & ODM_RF_D) { - p_dm_odm->RSSI_D = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D]; - RX_count++; - RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D]); - } else - p_dm_odm->RSSI_D = 0; - - /* Calculate average RSSI */ - switch (RX_count) { - case 2: - RSSI_linear = (RSSI_linear >> 1); - break; - case 3: - RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */ - break; - case 4: - RSSI_linear = (RSSI_linear >> 2); - break; - } - rssi_ave = odm_convert_to_db(RSSI_linear); - } else -#endif - { - if (p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B] == 0) { - rssi_ave = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - p_dm_odm->RSSI_B = 0; - } else { - /*dbg_print("p_rfd->status.rx_mimo_signal_strength[0] = %d, p_rfd->status.rx_mimo_signal_strength[1] = %d\n",*/ - /*p_rfd->status.rx_mimo_signal_strength[0], p_rfd->status.rx_mimo_signal_strength[1]);*/ - p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; - - if (p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A] > p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]) { - RSSI_max = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - RSSI_min = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; - } else { - RSSI_max = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; - RSSI_min = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - } - if ((RSSI_max - RSSI_min) < 3) - rssi_ave = RSSI_max; - else if ((RSSI_max - RSSI_min) < 6) - rssi_ave = RSSI_max - 1; - else if ((RSSI_max - RSSI_min) < 10) - rssi_ave = RSSI_max - 2; - else - rssi_ave = RSSI_max - 3; - } - } - - /* 1 Process OFDM RSSI */ - if (undecorated_smoothed_ofdm <= 0) { /* initialize */ - undecorated_smoothed_ofdm = p_phy_info->rx_pwdb_all; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_INIT: (( %d ))\n", undecorated_smoothed_ofdm)); - } else { - if (p_phy_info->rx_pwdb_all > (u32)undecorated_smoothed_ofdm) { - undecorated_smoothed_ofdm = - (((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) + - (rssi_ave)) / (RX_SMOOTH_FACTOR); - undecorated_smoothed_ofdm = undecorated_smoothed_ofdm + 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_1: (( %d ))\n", undecorated_smoothed_ofdm)); - } else { - undecorated_smoothed_ofdm = - (((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) + - (rssi_ave)) / (RX_SMOOTH_FACTOR); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_2: (( %d ))\n", undecorated_smoothed_ofdm)); - } - } - if (p_entry->rssi_stat.ofdm_pkt != 64) { - i = 63; - p_entry->rssi_stat.ofdm_pkt -= (u8)(((p_entry->rssi_stat.packet_map >> i) & BIT(0)) - 1); - } - p_entry->rssi_stat.packet_map = (p_entry->rssi_stat.packet_map << 1) | BIT(0); - - } else { - rssi_ave = p_phy_info->rx_pwdb_all; - p_dm_odm->RSSI_A = (u8) p_phy_info->rx_pwdb_all; - p_dm_odm->RSSI_B = 0xFF; - p_dm_odm->RSSI_C = 0xFF; - p_dm_odm->RSSI_D = 0xFF; - - if (p_entry->rssi_stat.cck_pkt <= 63) - p_entry->rssi_stat.cck_pkt++; - - /* 1 Process CCK RSSI */ - if (undecorated_smoothed_cck <= 0) { /* initialize */ - undecorated_smoothed_cck = p_phy_info->rx_pwdb_all; - p_entry->rssi_stat.cck_sum_power = (u16)p_phy_info->rx_pwdb_all ; /*reset*/ - p_entry->rssi_stat.cck_pkt = 1; /*reset*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_INIT: (( %d ))\n", undecorated_smoothed_cck)); - } else if (p_entry->rssi_stat.cck_pkt <= CCK_RSSI_INIT_COUNT) { - - p_entry->rssi_stat.cck_sum_power = p_entry->rssi_stat.cck_sum_power + (u16)p_phy_info->rx_pwdb_all; - undecorated_smoothed_cck = p_entry->rssi_stat.cck_sum_power / p_entry->rssi_stat.cck_pkt; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_0: (( %d )), SumPow = (( %d )), cck_pkt = (( %d ))\n", - undecorated_smoothed_cck, p_entry->rssi_stat.cck_sum_power, p_entry->rssi_stat.cck_pkt)); - } else { - if (p_phy_info->rx_pwdb_all > (u32)undecorated_smoothed_cck) { - undecorated_smoothed_cck = - (((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) + - (p_phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); - undecorated_smoothed_cck = undecorated_smoothed_cck + 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_1: (( %d ))\n", undecorated_smoothed_cck)); - } else { - undecorated_smoothed_cck = - (((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) + - (p_phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_2: (( %d ))\n", undecorated_smoothed_cck)); - } - } - i = 63; - p_entry->rssi_stat.ofdm_pkt -= (u8)((p_entry->rssi_stat.packet_map >> i) & BIT(0)); - p_entry->rssi_stat.packet_map = p_entry->rssi_stat.packet_map << 1; - } - - /* if(p_entry) */ - { - /* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */ - if (p_entry->rssi_stat.ofdm_pkt == 64) { /* speed up when all packets are OFDM*/ - undecorated_smoothed_pwdb = undecorated_smoothed_ofdm; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_0[%d] = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck)); - } else { - if (p_entry->rssi_stat.valid_bit < 64) - p_entry->rssi_stat.valid_bit++; - - if (p_entry->rssi_stat.valid_bit == 64) { - weighting = ((p_entry->rssi_stat.ofdm_pkt) > 4) ? 64 : (p_entry->rssi_stat.ofdm_pkt << 4); - undecorated_smoothed_pwdb = (weighting * undecorated_smoothed_ofdm + (64 - weighting) * undecorated_smoothed_cck) >> 6; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_1[%d] = (( %d )), W = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck, weighting)); - } else { - if (p_entry->rssi_stat.valid_bit != 0) - undecorated_smoothed_pwdb = (p_entry->rssi_stat.ofdm_pkt * undecorated_smoothed_ofdm + (p_entry->rssi_stat.valid_bit - p_entry->rssi_stat.ofdm_pkt) * undecorated_smoothed_cck) / p_entry->rssi_stat.valid_bit; - else - undecorated_smoothed_pwdb = 0; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_2[%d] = (( %d )), ofdm_pkt = (( %d )), Valid_Bit = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck, p_entry->rssi_stat.ofdm_pkt, p_entry->rssi_stat.valid_bit)); - } - } - - - if ((p_entry->rssi_stat.ofdm_pkt >= 1 || p_entry->rssi_stat.cck_pkt >= 5) && (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_INIT)) { - - send_rssi_2_fw = 1; - p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_SEND; - } - - p_entry->rssi_stat.undecorated_smoothed_cck = undecorated_smoothed_cck; - p_entry->rssi_stat.undecorated_smoothed_ofdm = undecorated_smoothed_ofdm; - p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb; - - - - if (send_rssi_2_fw) { /* Trigger init rate by RSSI */ - - if (p_entry->rssi_stat.ofdm_pkt != 0) - p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_ofdm; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("[Send to FW] PWDB = (( %d )), ofdm_pkt = (( %d )), cck_pkt = (( %d ))\n", - undecorated_smoothed_pwdb, p_entry->rssi_stat.ofdm_pkt, p_entry->rssi_stat.cck_pkt)); - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -#ifndef DM_ODM_CE_MAC80211 - phydm_ra_rssi_rpt_wk(p_dm_odm); -#endif -#endif - } - - - /*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - - if (p_pktinfo->station_id == 0) { - /**/ - p_hal_data->UndecoratedSmoothedPWDB = undecorated_smoothed_pwdb; - } -#endif - - /* dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt, weighting); */ - /* dbg_print("undecorated_smoothed_ofdm=%d, undecorated_smoothed_pwdb=%d, undecorated_smoothed_cck=%d\n", */ - /* undecorated_smoothed_ofdm, undecorated_smoothed_pwdb, undecorated_smoothed_cck); */ - - } - - } -} - - -#if (ODM_IC_11N_SERIES_SUPPORT == 1) -/* - * Endianness before calling this API - * */ -void -odm_phy_status_query_92c_series( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - odm_rx_phy_status92c_series_parsing(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); - odm_process_rssi_for_dm(p_dm_odm, p_phy_info, p_pktinfo); -} -#endif - - -/* - * Endianness before calling this API - * */ -#if ODM_IC_11AC_SERIES_SUPPORT - -void -odm_phy_status_query_jaguar_series( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - odm_rx_phy_status_jaguar_series_parsing(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); - odm_process_rssi_for_dm(p_dm_odm, p_phy_info, p_pktinfo); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /*phydm_sbd_check(p_dm_odm);*/ -#endif -} -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -phydm_normal_driver_rx_sniffer( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_desc, - PRT_RFD_STATUS p_rt_rfd_status, - u8 *p_drv_info, - u8 phy_status -) -{ -#if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING)) - u32 *p_msg; - u16 seq_num; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - - if (p_rt_rfd_status->packet_report_type != NORMAL_RX) - return; - - if (!p_dm_odm->is_linked) { - if (p_rt_rfd_status->is_hw_error) - return; - } - - if (!(p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) - return; - - if (phy_status == true) { - - if ((p_dm_odm->rx_pkt_type == type_block_ack) || (p_dm_odm->rx_pkt_type == type_rts) || (p_dm_odm->rx_pkt_type == type_cts)) - seq_num = 0; - else - seq_num = p_rt_rfd_status->seq_num; - - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s, rate=0x%02x, L=%04d , %s , %s", - seq_num, - /*p_rt_rfd_status->mac_id,*/ - ((p_rt_rfd_status->is_crc) ? "C" : (p_rt_rfd_status->is_ampdu) ? "A" : "_"), - p_rt_rfd_status->data_rate, - p_rt_rfd_status->length, - ((p_rt_rfd_status->band_width == 0) ? "20M" : ((p_rt_rfd_status->band_width == 1) ? "40M" : "80M")), - ((p_rt_rfd_status->is_ldpc) ? "LDP" : "BCC") - )); - - if (p_dm_odm->rx_pkt_type == type_asoc_req) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_REQ")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_asoc_rsp) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_RSP")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_probe_req) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_REQ")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_probe_rsp) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_RSP")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_deauth) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "DEAUTH")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_beacon) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BEACON")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_block_ack_req) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BA_REQ")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_rts) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__RTS_")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_cts) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__CTS_")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_ack) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__ACK_")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_block_ack) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__BA__")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_data) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "_DATA_")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_data_ack) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "Data_Ack")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_qos_data) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "QoS_Data")); - /**/ - } else { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [0x%x]", p_dm_odm->rx_pkt_type)); - /**/ - } - - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [RSSI=%d,%d,%d,%d ]", - p_dm_odm->RSSI_A, - p_dm_odm->RSSI_B, - p_dm_odm->RSSI_C, - p_dm_odm->RSSI_D - )); - - p_msg = (u32 *)p_drv_info; - - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n", - p_msg[6], p_msg[5], p_msg[4], p_msg[3], p_msg[2], p_msg[1], p_msg[1])); - } else { - - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n", - p_rt_rfd_status->seq_num, - /*p_rt_rfd_status->mac_id,*/ - ((p_rt_rfd_status->is_crc) ? "C" : (p_rt_rfd_status->is_ampdu) ? "A" : "_"), - p_rt_rfd_status->data_rate, - p_rt_rfd_status->length, - ((p_rt_rfd_status->band_width == 0) ? "20M" : ((p_rt_rfd_status->band_width == 1) ? "40M" : "80M")), - ((p_rt_rfd_status->is_ldpc) ? "LDP" : "BCC") - )); - } - - -#endif -} -#endif - -void -odm_phy_status_query( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - - if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) { - #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - phydm_rx_phy_status_new_type(p_dm_odm, p_phy_status, p_pktinfo, p_phy_info); - #endif - } - - #if ODM_IC_11AC_SERIES_SUPPORT - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - odm_phy_status_query_jaguar_series(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); - #endif - - #if ODM_IC_11N_SERIES_SUPPORT - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - odm_phy_status_query_92c_series(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); - #endif -} - -/* For future use. */ -void -odm_mac_status_query( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_mac_status, - u8 mac_id, - boolean is_packet_match_bssid, - boolean is_packet_to_self, - boolean is_packet_beacon -) -{ - /* 2011/10/19 Driver team will handle in the future. */ - -} - - -/* - * If you want to add a new IC, Please follow below template and generate a new one. - * - * */ +#if (PHYDM_TESTCHIP_SUPPORT == 1) + #define GET_VERSION(ic, txt) (dm->is_mp_chip ? GET_VERSION_MP(ic, txt) : GET_VERSION_TC(ic, txt)) +#else + #define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt) +#endif enum hal_status odm_config_rf_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum odm_rf_config_type config_type, - enum odm_rf_radio_path_e e_rf_path + u8 e_rf_path ) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; #endif enum hal_status result = HAL_STATUS_SUCCESS; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===>odm_config_rf_with_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", - p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===>odm_config_rf_with_header_file (%s)\n", (dm->is_mp_chip) ? "MPChip" : "TestChip"); + PHYDM_DBG(dm, ODM_COMP_INIT, + "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", + dm->support_platform, dm->support_interface, dm->board_type); /* 1 AP doesn't use PHYDM power tracking table in these ICs */ #if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) { + if (dm->support_ic_type == ODM_RTL8812) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8812a, _radioa); - else if (e_rf_path == ODM_RF_PATH_B) + else if (e_rf_path == RF_PATH_B) READ_AND_CONFIG_MP(8812a, _radiob); } else if (config_type == CONFIG_RF_TXPWR_LMT) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - if ((p_hal_data->EEPROMSVID == 0x17AA && p_hal_data->EEPROMSMID == 0xA811) || - (p_hal_data->EEPROMSVID == 0x10EC && p_hal_data->EEPROMSMID == 0xA812) || - (p_hal_data->EEPROMSVID == 0x10EC && p_hal_data->EEPROMSMID == 0x8812)) + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + if ((hal_data->EEPROMSVID == 0x17AA && hal_data->EEPROMSMID == 0xA811) || + (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0xA812) || + (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0x8812)) READ_AND_CONFIG_MP(8812a, _txpwr_lmt_hm812a03); else #endif @@ -2125,43 +96,42 @@ odm_config_rf_with_header_file( } #endif #if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821) { + if (dm->support_ic_type == ODM_RTL8821) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8821a, _radioa); } else if (config_type == CONFIG_RF_TXPWR_LMT) { - if (p_dm_odm->support_interface == ODM_ITRF_USB) { - if (p_dm_odm->ext_pa_5g || p_dm_odm->ext_lna_5g) + if (dm->support_interface == ODM_ITRF_USB) { + if (dm->ext_pa_5g || dm->ext_lna_5g) READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_fem); else READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_ipa); } else { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_mgnt_info->CustomerID == RT_CID_8821AE_ASUS_MB) + if (mgnt_info->CustomerID == RT_CID_8821AE_ASUS_MB) READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_8mm); - else if (p_mgnt_info->CustomerID == RT_CID_ASUS_NB) + else if (mgnt_info->CustomerID == RT_CID_ASUS_NB) READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_5mm); else #endif READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a); } } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigRFWithHeaderFile\n")); } #endif #if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + if (dm->support_ic_type == ODM_RTL8192E) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8192e, _radioa); - else if (e_rf_path == ODM_RF_PATH_B) + else if (e_rf_path == RF_PATH_B) READ_AND_CONFIG_MP(8192e, _radiob); } else if (config_type == CONFIG_RF_TXPWR_LMT) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) /*Refine by Vincent Lan for 5mm SAR pwr limit*/ - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - if ((p_hal_data->EEPROMSVID == 0x11AD && p_hal_data->EEPROMSMID == 0x8192) || - (p_hal_data->EEPROMSVID == 0x11AD && p_hal_data->EEPROMSMID == 0x8193)) + if ((hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8192) || + (hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8193)) READ_AND_CONFIG_MP(8192e, _txpwr_lmt_8192e_sar_5mm); else #endif @@ -2170,9 +140,9 @@ odm_config_rf_with_header_file( } #endif #if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (dm->support_ic_type == ODM_RTL8723D) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8723d, _radioa); } else if (config_type == CONFIG_RF_TXPWR_LMT) READ_AND_CONFIG_MP(8723d, _txpwr_lmt); @@ -2180,9 +150,9 @@ odm_config_rf_with_header_file( #endif /* JJ ADD 20161014 */ #if (RTL8710B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + if (dm->support_ic_type == ODM_RTL8710B) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8710b, _radioa); } else if (config_type == CONFIG_RF_TXPWR_LMT) READ_AND_CONFIG_MP(8710b, _txpwr_lmt); @@ -2193,16 +163,16 @@ odm_config_rf_with_header_file( /* 1 All platforms support */ #if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + if (dm->support_ic_type == ODM_RTL8188E) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8188e, _radioa); } else if (config_type == CONFIG_RF_TXPWR_LMT) READ_AND_CONFIG_MP(8188e, _txpwr_lmt); } #endif #if (RTL8723B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (dm->support_ic_type == ODM_RTL8723B) { if (config_type == CONFIG_RF_RADIO) READ_AND_CONFIG_MP(8723b, _radioa); else if (config_type == CONFIG_RF_TXPWR_LMT) @@ -2210,82 +180,99 @@ odm_config_rf_with_header_file( } #endif #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) { + if (dm->support_ic_type == ODM_RTL8814A) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8814a, _radioa); - else if (e_rf_path == ODM_RF_PATH_B) + else if (e_rf_path == RF_PATH_B) READ_AND_CONFIG_MP(8814a, _radiob); - else if (e_rf_path == ODM_RF_PATH_C) + else if (e_rf_path == RF_PATH_C) READ_AND_CONFIG_MP(8814a, _radioc); - else if (e_rf_path == ODM_RF_PATH_D) + else if (e_rf_path == RF_PATH_D) READ_AND_CONFIG_MP(8814a, _radiod); } else if (config_type == CONFIG_RF_TXPWR_LMT) { - if (p_dm_odm->rfe_type == 0) + if (dm->rfe_type == 0) READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type0); - else if (p_dm_odm->rfe_type == 1) + else if (dm->rfe_type == 1) READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type1); - else if (p_dm_odm->rfe_type == 2) + else if (dm->rfe_type == 2) READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type2); - else if (p_dm_odm->rfe_type == 3) + else if (dm->rfe_type == 3) READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type3); - else if (p_dm_odm->rfe_type == 5) + else if (dm->rfe_type == 5) READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type5); - else if (p_dm_odm->rfe_type == 7) - READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type7); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type8); else READ_AND_CONFIG_MP(8814a,_txpwr_lmt); } } #endif #if (RTL8703B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8703B) { + if (dm->support_ic_type == ODM_RTL8703B) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8703b, _radioa); } } #endif #if (RTL8188F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (dm->support_ic_type == ODM_RTL8188F) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8188f, _radioa); } else if (config_type == CONFIG_RF_TXPWR_LMT) READ_AND_CONFIG_MP(8188f, _txpwr_lmt); } #endif #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + if (dm->support_ic_type == ODM_RTL8822B) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8822b, _radioa); - else if (e_rf_path == ODM_RF_PATH_B) + else if (e_rf_path == RF_PATH_B) READ_AND_CONFIG_MP(8822b, _radiob); } else if (config_type == CONFIG_RF_TXPWR_LMT) { - if (p_dm_odm->rfe_type == 5) + if (dm->rfe_type == 5) READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type5); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type4); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type12); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type17); else READ_AND_CONFIG_MP(8822b, _txpwr_lmt); + } } #endif #if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8197F) { + if (dm->support_ic_type == ODM_RTL8197F) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8197f, _radioa); - else if (e_rf_path == ODM_RF_PATH_B) + else if (e_rf_path == RF_PATH_B) READ_AND_CONFIG_MP(8197f, _radiob); } } #endif #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + if (dm->support_ic_type == ODM_RTL8821C) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG(8821c, _radioa); } else if (config_type == CONFIG_RF_TXPWR_LMT) READ_AND_CONFIG(8821c, _txpwr_lmt); @@ -2293,17 +280,16 @@ odm_config_rf_with_header_file( #endif if (config_type == CONFIG_RF_RADIO) { - if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { - - result = phydm_set_reg_by_fw(p_dm_odm, + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + result = phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_END, 0, 0, 0, - 0, + (enum rf_path)0, 0); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("rf param offload end!result = %d", result)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "rf param offload end!result = %d", result); } } @@ -2312,34 +298,34 @@ odm_config_rf_with_header_file( enum hal_status odm_config_rf_with_tx_pwr_track_header_file( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===>odm_config_rf_with_tx_pwr_track_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n", - p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===>odm_config_rf_with_tx_pwr_track_header_file (%s)\n", (dm->is_mp_chip) ? "MPChip" : "TestChip"); + PHYDM_DBG(dm, ODM_COMP_INIT, + "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", + dm->support_platform, dm->support_interface, dm->board_type); /* 1 AP doesn't use PHYDM power tracking table in these ICs */ #if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if RTL8821A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_ic_type == ODM_RTL8821) { + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8821a, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) + else if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8821a, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8821a, _txpowertrack_sdio); } #endif #if RTL8812A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8812) { - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_ic_type == ODM_RTL8812) { + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8812a, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) { - if (p_dm_odm->rfe_type == 3 && p_dm_odm->is_mp_chip) + else if (dm->support_interface == ODM_ITRF_USB) { + if (dm->rfe_type == 3 && dm->is_mp_chip) READ_AND_CONFIG_MP(8812a, _txpowertrack_rfe3); else READ_AND_CONFIG_MP(8812a, _txpowertrack_usb); @@ -2348,22 +334,22 @@ odm_config_rf_with_tx_pwr_track_header_file( } #endif #if RTL8192E_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_ic_type == ODM_RTL8192E) { + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8192e, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) + else if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8192e, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8192e, _txpowertrack_sdio); } #endif #if RTL8723D_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_ic_type == ODM_RTL8723D) { + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8723d, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) + else if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8723d, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8723d, _txpowertrack_sdio); READ_AND_CONFIG_MP(8723d, _txxtaltrack); @@ -2371,33 +357,31 @@ odm_config_rf_with_tx_pwr_track_header_file( #endif /* JJ ADD 20161014 */ #if RTL8710B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8710B) { - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8710b, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8710b, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8710b, _txpowertrack_sdio); - + if (dm->support_ic_type == ODM_RTL8710B) { + if (dm->package_type == 1) + READ_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_smic); + else if (dm->package_type == 5) + READ_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_umc); + READ_AND_CONFIG_MP(8710b, _txxtaltrack); } #endif #if RTL8188E_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - if (odm_get_mac_reg(p_dm_odm, 0xF0, 0xF000) >= 8) { /*if 0xF0[15:12] >= 8, SMIC*/ - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_ic_type == ODM_RTL8188E) { + if (odm_get_mac_reg(dm, 0xF0, 0xF000) >= 8) { /*if 0xF0[15:12] >= 8, SMIC*/ + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie_icut); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) + else if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8188e, _txpowertrack_usb_icut); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio_icut); } else { /*else 0xF0[15:12] < 8, TSMC*/ - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) + else if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8188e, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio); } @@ -2407,23 +391,27 @@ odm_config_rf_with_tx_pwr_track_header_file( /* 1 All platforms support */ #if RTL8723B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_ic_type == ODM_RTL8723B) { + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8723b, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) + else if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8723b, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8723b, _txpowertrack_sdio); } #endif #if RTL8814A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8814A) { - if (p_dm_odm->rfe_type == 0) + if (dm->support_ic_type == ODM_RTL8814A) { + if (dm->rfe_type == 0) READ_AND_CONFIG_MP(8814a, _txpowertrack_type0); - else if (p_dm_odm->rfe_type == 2) + else if (dm->rfe_type == 2) READ_AND_CONFIG_MP(8814a, _txpowertrack_type2); - else if (p_dm_odm->rfe_type == 5) + else if (dm->rfe_type == 5) READ_AND_CONFIG_MP(8814a, _txpowertrack_type5); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8814a, _txpowertrack_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8814a, _txpowertrack_type8); else READ_AND_CONFIG_MP(8814a, _txpowertrack); @@ -2431,10 +419,10 @@ odm_config_rf_with_tx_pwr_track_header_file( } #endif #if RTL8703B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8703B) { - if (p_dm_odm->support_interface == ODM_ITRF_USB) + if (dm->support_ic_type == ODM_RTL8703B) { + if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8703b, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8703b, _txpowertrack_sdio); READ_AND_CONFIG_MP(8703b, _txxtaltrack); @@ -2442,50 +430,60 @@ odm_config_rf_with_tx_pwr_track_header_file( #endif #if RTL8188F_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - if (p_dm_odm->support_interface == ODM_ITRF_USB) + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8188f, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8188f, _txpowertrack_sdio); } #endif #if RTL8822B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - if (p_dm_odm->rfe_type == 0) + if (dm->support_ic_type == ODM_RTL8822B) { + if (dm->rfe_type == 0) READ_AND_CONFIG_MP(8822b, _txpowertrack_type0); - else if (p_dm_odm->rfe_type == 1) + else if (dm->rfe_type == 1) READ_AND_CONFIG_MP(8822b, _txpowertrack_type1); - else if (p_dm_odm->rfe_type == 2) + else if (dm->rfe_type == 2) READ_AND_CONFIG_MP(8822b, _txpowertrack_type2); - else if ((p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5)) + else if ((dm->rfe_type == 3) || (dm->rfe_type == 5)) READ_AND_CONFIG_MP(8822b, _txpowertrack_type3_type5); - else if (p_dm_odm->rfe_type == 4) + else if (dm->rfe_type == 4) READ_AND_CONFIG_MP(8822b, _txpowertrack_type4); - else if (p_dm_odm->rfe_type == 6) + else if (dm->rfe_type == 6) READ_AND_CONFIG_MP(8822b, _txpowertrack_type6); - else if (p_dm_odm->rfe_type == 7) + else if (dm->rfe_type == 7) READ_AND_CONFIG_MP(8822b, _txpowertrack_type7); - else if (p_dm_odm->rfe_type == 8) + else if (dm->rfe_type == 8) READ_AND_CONFIG_MP(8822b, _txpowertrack_type8); - else if (p_dm_odm->rfe_type == 9) + else if (dm->rfe_type == 9) READ_AND_CONFIG_MP(8822b, _txpowertrack_type9); - else if (p_dm_odm->rfe_type == 10) + else if (dm->rfe_type == 10) READ_AND_CONFIG_MP(8822b, _txpowertrack_type10); - else if (p_dm_odm->rfe_type == 11) + else if (dm->rfe_type == 11) READ_AND_CONFIG_MP(8822b, _txpowertrack_type11); - else if (p_dm_odm->rfe_type == 12) + else if (dm->rfe_type == 12) READ_AND_CONFIG_MP(8822b, _txpowertrack_type12); + else if (dm->rfe_type == 13) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type13); + else if (dm->rfe_type == 14) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type14); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type17); else READ_AND_CONFIG_MP(8822b, _txpowertrack); } #endif #if RTL8197F_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8197F) { - if (p_dm_odm->rfe_type == 0) + if (dm->support_ic_type == ODM_RTL8197F) { + if (dm->rfe_type == 0) READ_AND_CONFIG_MP(8197f, _txpowertrack_type0); - else if (p_dm_odm->rfe_type == 1) + else if (dm->rfe_type == 1) READ_AND_CONFIG_MP(8197f, _txpowertrack_type1); else READ_AND_CONFIG_MP(8197f, _txpowertrack); @@ -2493,8 +491,14 @@ odm_config_rf_with_tx_pwr_track_header_file( #endif #if RTL8821C_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - READ_AND_CONFIG(8821c, _txpowertrack); + if (dm->support_ic_type == ODM_RTL8821C) { + if (dm->rfe_type == 0x5) + READ_AND_CONFIG(8821c, _txpowertrack_type0x28); + else if (dm->rfe_type == 0x4) + READ_AND_CONFIG(8821c, _txpowertrack_type0x20); + else + READ_AND_CONFIG(8821c, _txpowertrack); + } #endif return HAL_STATUS_SUCCESS; @@ -2502,37 +506,37 @@ odm_config_rf_with_tx_pwr_track_header_file( enum hal_status odm_config_bb_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum odm_bb_config_type config_type ) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; #endif enum hal_status result = HAL_STATUS_SUCCESS; /* 1 AP doesn't use PHYDM initialization in these ICs */ #if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) { + if (dm->support_ic_type == ODM_RTL8812) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8812a, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) READ_AND_CONFIG_MP(8812a, _agc_tab); else if (config_type == CONFIG_BB_PHY_REG_PG) { - if (p_dm_odm->rfe_type == 3 && p_dm_odm->is_mp_chip) + if (dm->rfe_type == 3 && dm->is_mp_chip) READ_AND_CONFIG_MP(8812a, _phy_reg_pg_asus); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - else if (p_mgnt_info->CustomerID == RT_CID_WNC_NEC && p_dm_odm->is_mp_chip) + else if (mgnt_info->CustomerID == RT_CID_WNC_NEC && dm->is_mp_chip) READ_AND_CONFIG_MP(8812a, _phy_reg_pg_nec); #if RT_PLATFORM == PLATFORM_MACOSX /*{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/ - else if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) + else if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) READ_AND_CONFIG_MP(8812a, _phy_reg_pg_dni); /* TP-Link T4UH, Isaiah 2015-03-16*/ - else if (p_mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) { - dbg_print("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n"); + else if (mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) { + pr_debug("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n"); READ_AND_CONFIG_MP(8812a, _phy_reg_pg_tplink); } #endif @@ -2542,17 +546,17 @@ odm_config_bb_with_header_file( } else if (config_type == CONFIG_BB_PHY_REG_MP) READ_AND_CONFIG_MP(8812a, _phy_reg_mp); else if (config_type == CONFIG_BB_AGC_TAB_DIFF) { - p_dm_odm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD; + dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD; /*AGC_TAB DIFF dont support FW offload*/ - if ((36 <= *p_dm_odm->p_channel) && (*p_dm_odm->p_channel <= 64)) + if ((*dm->channel >= 36) && (*dm->channel <= 64)) AGC_DIFF_CONFIG_MP(8812a, lb); - else if (100 <= *p_dm_odm->p_channel) + else if (*dm->channel >= 100) AGC_DIFF_CONFIG_MP(8812a, hb); } } #endif #if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821) { + if (dm->support_ic_type == ODM_RTL8821) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8821a, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2560,17 +564,17 @@ odm_config_bb_with_header_file( else if (config_type == CONFIG_BB_PHY_REG_PG) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - if ((p_hal_data->EEPROMSVID == 0x1043 && p_hal_data->EEPROMSMID == 0x207F)) + if ((hal_data->EEPROMSVID == 0x1043 && hal_data->EEPROMSMID == 0x207F)) READ_AND_CONFIG_MP(8821a, _phy_reg_pg_e202_sa); else #endif #if (RT_PLATFORM == PLATFORM_MACOSX) /*{1827}{1022} for BUFFALO power by rate table. Isaiah 2013-10-18*/ - if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) { + if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) { /*{1024} for BUFFALO power by rate table. (JP/US)*/ - if (p_mgnt_info->channel_plan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G) + if (mgnt_info->ChannelPlan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G) READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us); else READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp); @@ -2582,7 +586,7 @@ odm_config_bb_with_header_file( } #endif #if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + if (dm->support_ic_type == ODM_RTL8192E) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8192e, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2592,7 +596,7 @@ odm_config_bb_with_header_file( } #endif #if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (dm->support_ic_type == ODM_RTL8723D) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8723d, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2603,7 +607,7 @@ odm_config_bb_with_header_file( #endif /* JJ ADD 20161014 */ #if (RTL8710B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + if (dm->support_ic_type == ODM_RTL8710B) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8710b, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2618,7 +622,7 @@ odm_config_bb_with_header_file( /* 1 All platforms support */ #if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + if (dm->support_ic_type == ODM_RTL8188E) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8188e, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2628,7 +632,7 @@ odm_config_bb_with_header_file( } #endif #if (RTL8723B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (dm->support_ic_type == ODM_RTL8723B) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8723b, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2638,24 +642,26 @@ odm_config_bb_with_header_file( } #endif #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) { + if (dm->support_ic_type == ODM_RTL8814A) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8814a, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) READ_AND_CONFIG_MP(8814a, _agc_tab); else if (config_type == CONFIG_BB_PHY_REG_PG) { - if (p_dm_odm->rfe_type == 0) + if (dm->rfe_type == 0) READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type0); - else if (p_dm_odm->rfe_type == 2) + else if (dm->rfe_type == 2) READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type2); - else if (p_dm_odm->rfe_type == 3) + else if (dm->rfe_type == 3) READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type3); - else if (p_dm_odm->rfe_type == 4) + else if (dm->rfe_type == 4) READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type4); - else if (p_dm_odm->rfe_type == 5) + else if (dm->rfe_type == 5) READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type5); - else if (p_dm_odm->rfe_type == 7) - READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type7); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type8); else READ_AND_CONFIG_MP(8814a,_phy_reg_pg); } @@ -2664,7 +670,7 @@ odm_config_bb_with_header_file( } #endif #if (RTL8703B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8703B) { + if (dm->support_ic_type == ODM_RTL8703B) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8703b, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2674,7 +680,7 @@ odm_config_bb_with_header_file( } #endif #if (RTL8188F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (dm->support_ic_type == ODM_RTL8188F) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8188f, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2684,51 +690,73 @@ odm_config_bb_with_header_file( } #endif #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + if (dm->support_ic_type == ODM_RTL8822B) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8822b, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) READ_AND_CONFIG_MP(8822b, _agc_tab); - else if (config_type == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8822b, _phy_reg_pg); + else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type4); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type5); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type12); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type17); + else + READ_AND_CONFIG_MP(8822b, _phy_reg_pg); + } } #endif #if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8197F) { + if (dm->support_ic_type == ODM_RTL8197F) { if (config_type == CONFIG_BB_PHY_REG) { READ_AND_CONFIG_MP(8197f, _phy_reg); - if (p_dm_odm->cut_version == ODM_CUT_A) - phydm_phypara_a_cut(p_dm_odm); + if (dm->cut_version == ODM_CUT_A) + phydm_phypara_a_cut(dm); } else if (config_type == CONFIG_BB_AGC_TAB) READ_AND_CONFIG_MP(8197f, _agc_tab); } #endif #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + if (dm->support_ic_type == ODM_RTL8821C) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG(8821c, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) { READ_AND_CONFIG(8821c, _agc_tab); /* According to RFEtype, choosing correct AGC table*/ - if (p_dm_odm->default_rf_set_8821c == SWITCH_TO_BTG) + if (dm->default_rf_set_8821c == SWITCH_TO_BTG) AGC_DIFF_CONFIG_MP(8821c, btg); - } else if (config_type == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG(8821c, _phy_reg_pg); - else if (config_type == CONFIG_BB_AGC_TAB_DIFF) { - p_dm_odm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD; + } else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (dm->rfe_type == 0x5) + READ_AND_CONFIG(8821c, _phy_reg_pg_type0x28); + else + READ_AND_CONFIG(8821c, _phy_reg_pg); + } else if (config_type == CONFIG_BB_AGC_TAB_DIFF) { + dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD; /*AGC_TAB DIFF dont support FW offload*/ - if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_BTG) + if (dm->current_rf_set_8821c == SWITCH_TO_BTG) AGC_DIFF_CONFIG_MP(8821c, btg); - else if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_WLG) + else if (dm->current_rf_set_8821c == SWITCH_TO_WLG) AGC_DIFF_CONFIG_MP(8821c, wlg); - } + } else if (config_type == CONFIG_BB_PHY_REG_MP) + READ_AND_CONFIG(8821c, _phy_reg_mp); } #endif #if (RTL8195A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8195A) { + if (dm->support_ic_type == ODM_RTL8195A) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG(8195a, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2739,17 +767,16 @@ odm_config_bb_with_header_file( #endif if (config_type == CONFIG_BB_PHY_REG || config_type == CONFIG_BB_AGC_TAB) - if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { - - result = phydm_set_reg_by_fw(p_dm_odm, + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + result = phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_END, 0, 0, 0, - 0, + (enum rf_path)0, 0); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("phy param offload end!result = %d", result)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "phy param offload end!result = %d", result); } return result; @@ -2757,37 +784,37 @@ odm_config_bb_with_header_file( enum hal_status odm_config_mac_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { enum hal_status result = HAL_STATUS_SUCCESS; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===>odm_config_mac_with_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", - p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===>odm_config_mac_with_header_file (%s)\n", (dm->is_mp_chip) ? "MPChip" : "TestChip"); + PHYDM_DBG(dm, ODM_COMP_INIT, + "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", + dm->support_platform, dm->support_interface, dm->board_type); /* 1 AP doesn't use PHYDM initialization in these ICs */ #if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) + if (dm->support_ic_type == ODM_RTL8812) READ_AND_CONFIG_MP(8812a, _mac_reg); #endif #if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821) + if (dm->support_ic_type == ODM_RTL8821) READ_AND_CONFIG_MP(8821a, _mac_reg); #endif #if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) + if (dm->support_ic_type == ODM_RTL8192E) READ_AND_CONFIG_MP(8192e, _mac_reg); #endif #if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723D) + if (dm->support_ic_type == ODM_RTL8723D) READ_AND_CONFIG_MP(8723d, _mac_reg); #endif /* JJ ADD 20161014 */ #if (RTL8710B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8710B) + if (dm->support_ic_type == ODM_RTL8710B) READ_AND_CONFIG_MP(8710b, _mac_reg); #endif @@ -2795,267 +822,63 @@ odm_config_mac_with_header_file( /* 1 All platforms support */ #if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) + if (dm->support_ic_type == ODM_RTL8188E) READ_AND_CONFIG_MP(8188e, _mac_reg); #endif #if (RTL8723B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) + if (dm->support_ic_type == ODM_RTL8723B) READ_AND_CONFIG_MP(8723b, _mac_reg); #endif #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) + if (dm->support_ic_type == ODM_RTL8814A) READ_AND_CONFIG_MP(8814a, _mac_reg); #endif #if (RTL8703B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8703B) + if (dm->support_ic_type == ODM_RTL8703B) READ_AND_CONFIG_MP(8703b, _mac_reg); #endif #if (RTL8188F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188F) + if (dm->support_ic_type == ODM_RTL8188F) READ_AND_CONFIG_MP(8188f, _mac_reg); #endif #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) + if (dm->support_ic_type == ODM_RTL8822B) READ_AND_CONFIG_MP(8822b, _mac_reg); #endif #if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8197F) + if (dm->support_ic_type == ODM_RTL8197F) READ_AND_CONFIG_MP(8197f, _mac_reg); #endif #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) + if (dm->support_ic_type == ODM_RTL8821C) READ_AND_CONFIG(8821c, _mac_reg); #endif #if (RTL8195A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8195A) + if (dm->support_ic_type == ODM_RTL8195A) READ_AND_CONFIG_MP(8195a, _mac_reg); #endif - if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { - - result = phydm_set_reg_by_fw(p_dm_odm, + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + result = phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_END, 0, 0, 0, - 0, + (enum rf_path)0, 0); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("mac param offload end!result = %d", result)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "mac param offload end!result = %d", result); } return result; } -enum hal_status -odm_config_fw_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_fw_config_type config_type, - u8 *p_firmware, - u32 *p_size -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -#if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { -#ifdef CONFIG_SFW_SUPPORTED - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8188e_t, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8188e_t, _fw_wowlan); - else if (config_type == CONFIG_FW_NIC_2) - READ_FIRMWARE_MP(8188e_s, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN_2) - READ_FIRMWARE_MP(8188e_s, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - if (config_type == CONFIG_FW_AP) - READ_FIRMWARE_MP(8188e_t, _fw_ap); - else if (config_type == CONFIG_FW_AP_2) - READ_FIRMWARE_MP(8188e_s, _fw_ap); -#endif /* CONFIG_AP_WOWLAN */ -#else - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8188e_t, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8188e_t, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == CONFIG_FW_AP) - READ_FIRMWARE_MP(8188e_t, _fw_ap); -#endif /* CONFIG_AP_WOWLAN */ -#endif - } -#endif -#if (RTL8723B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8723b, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8723b, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE(8723b, _fw_ap); -#endif - - } -#endif /* #if (RTL8723B_SUPPORT == 1) */ -#if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8812a, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8812a, _fw_wowlan); - else if (config_type == CONFIG_FW_BT) - READ_FIRMWARE_MP(8812a, _fw_nic_bt); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE(8812a, _fw_ap); -#endif - } -#endif -#if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8821a, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8821a, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8821a, _fw_ap); -#endif /*CONFIG_AP_WOWLAN*/ - else if (config_type == CONFIG_FW_BT) - READ_FIRMWARE_MP(8821a, _fw_nic_bt); - } -#endif -#if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8192e, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8192e, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8192e, _fw_ap); -#endif - } -#endif -#if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8723d, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) { - READ_FIRMWARE_MP(8723d, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8723d, _fw_ap); -#endif - } - } -#endif -/* JJ ADD 20161014 */ -#if (RTL8710B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8710B) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8710b, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) { - READ_FIRMWARE_MP(8710b, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8710b, _fw_ap); -#endif - } - } -#endif - -#if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8814a, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8814a, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8814a, _fw_ap); -#endif - } -#endif - -#if (RTL8703B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8703B) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8703b, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8703b, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE(8703b, _fw_ap); -#endif - } -#endif - -#if (RTL8188F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8188f, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8188f, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == CONFIG_FW_AP) - READ_FIRMWARE_MP(8188f, _fw_ap); -#endif - } -#endif - -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8822b, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8822b, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE(8822b, _fw_ap); -#endif - } -#endif - -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8197F) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8197f, _fw_nic); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE(8197f, _fw_ap); -#endif - } -#endif - -#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN)) -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8821c, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8821c, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8821c, _fw_ap); -#endif /*CONFIG_AP_WOWLAN*/ - } -#endif -#endif - -#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ - return HAL_STATUS_SUCCESS; -} - u32 odm_get_hw_img_version( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 version = 0; @@ -3063,24 +886,24 @@ odm_get_hw_img_version( /* 1 AP doesn't use PHYDM initialization in these ICs */ #if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821) + if (dm->support_ic_type == ODM_RTL8821) version = GET_VERSION_MP(8821a, _mac_reg); #endif #if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) + if (dm->support_ic_type == ODM_RTL8192E) version = GET_VERSION_MP(8192e, _mac_reg); #endif #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) + if (dm->support_ic_type == ODM_RTL8812) version = GET_VERSION_MP(8812a, _mac_reg); #endif #if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723D) + if (dm->support_ic_type == ODM_RTL8723D) version = GET_VERSION_MP(8723d, _mac_reg); #endif /* JJ ADD 20161014 */ #if (RTL8710B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8710B) + if (dm->support_ic_type == ODM_RTL8710B) version = GET_VERSION_MP(8710b, _mac_reg); #endif @@ -3088,725 +911,54 @@ odm_get_hw_img_version( /*1 All platforms support*/ #if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) + if (dm->support_ic_type == ODM_RTL8188E) version = GET_VERSION_MP(8188e, _mac_reg); #endif #if (RTL8723B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) + if (dm->support_ic_type == ODM_RTL8723B) version = GET_VERSION_MP(8723b, _mac_reg); #endif #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) + if (dm->support_ic_type == ODM_RTL8814A) version = GET_VERSION_MP(8814a, _mac_reg); #endif #if (RTL8703B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8703B) + if (dm->support_ic_type == ODM_RTL8703B) version = GET_VERSION_MP(8703b, _mac_reg); #endif #if (RTL8188F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188F) + if (dm->support_ic_type == ODM_RTL8188F) version = GET_VERSION_MP(8188f, _mac_reg); #endif #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) + if (dm->support_ic_type == ODM_RTL8822B) version = GET_VERSION_MP(8822b, _mac_reg); #endif #if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8197F) + if (dm->support_ic_type == ODM_RTL8197F) version = GET_VERSION_MP(8197f, _mac_reg); #endif #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) + if (dm->support_ic_type == ODM_RTL8821C) version = GET_VERSION(8821c, _mac_reg); #endif return version; } -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) -/* For 8822B only!! need to move to FW finally */ -/*==============================================*/ - -boolean -phydm_query_is_mu_api( - struct PHY_DM_STRUCT *p_phydm, - u8 ppdu_idx, - u8 *p_data_rate, - u8 *p_gid -) -{ - u8 data_rate = 0, gid = 0; - boolean is_mu = false; - - data_rate = p_phydm->phy_dbg_info.num_of_ppdu[ppdu_idx]; - gid = p_phydm->phy_dbg_info.gid_num[ppdu_idx]; - - if (data_rate & BIT(7)) { - is_mu = true; - data_rate = data_rate & ~(BIT(7)); - } else - is_mu = false; - - *p_data_rate = data_rate; - *p_gid = gid; - - return is_mu; - -} - -void -phydm_reset_phy_info( - struct PHY_DM_STRUCT *p_phydm, - struct _odm_phy_status_info_ *p_phy_info -) -{ - p_phy_info->rx_pwdb_all = 0; - p_phy_info->signal_quality = 0; - p_phy_info->band_width = 0; - p_phy_info->rx_count = 0; - odm_memory_set(p_phydm, p_phy_info->rx_mimo_signal_quality, 0, 4); - odm_memory_set(p_phydm, p_phy_info->rx_mimo_signal_strength, 0, 4); - odm_memory_set(p_phydm, p_phy_info->rx_snr, 0, 4); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->rx_power = -110; - p_phy_info->recv_signal_power = -110; - p_phy_info->bt_rx_rssi_percentage = 0; - p_phy_info->signal_strength = 0; - p_phy_info->bt_coex_pwr_adjust = 0; - p_phy_info->channel = 0; - p_phy_info->is_mu_packet = 0; - p_phy_info->is_beamformed = 0; - p_phy_info->rxsc = 0; - odm_memory_set(p_phydm, p_phy_info->rx_pwr, -110, 4); - /*odm_memory_set(p_phydm, p_phy_info->rx_mimo_evm_dbm, 0, 4);*/ - odm_memory_set(p_phydm, p_phy_info->cfo_short, 0, 8); - odm_memory_set(p_phydm, p_phy_info->cfo_tail, 0, 8); -#endif - odm_memory_set(p_phydm, p_phy_info->rx_mimo_evm_dbm, 0, 4); -} - -void -phydm_set_per_path_phy_info( - u8 rx_path, - s8 rx_pwr, - s8 rx_evm, - s8 cfo_tail, - s8 rx_snr, - struct _odm_phy_status_info_ *p_phy_info -) -{ - u8 evm_dbm = 0; - u8 evm_percentage = 0; - - /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */ - - if (rx_evm < 0) { - /* Calculate EVM in dBm */ - evm_dbm = ((u8)(0 - rx_evm) >> 1); - - /* Calculate EVM in percentage */ - if (evm_dbm >= 34) - evm_percentage = 100; - else - evm_percentage = (evm_dbm << 1) + (evm_dbm); - } - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->rx_pwr[rx_path] = rx_pwr; - - /* CFO = CFO_tail * 312.5 / 2^7 ~= CFO tail * 39/512 (kHz)*/ - p_phy_info->cfo_tail[rx_path] = cfo_tail; - p_phy_info->cfo_tail[rx_path] = ((p_phy_info->cfo_tail[rx_path] << 5) + (p_phy_info->cfo_tail[rx_path] << 2) + - (p_phy_info->cfo_tail[rx_path] << 1) + (p_phy_info->cfo_tail[rx_path])) >> 9; -#endif - if (evm_dbm == 64) - evm_dbm = 0; /*if 1SS rate, evm_dbm [2nd stream] =64*/ - - p_phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm; - - p_phy_info->rx_mimo_signal_strength[rx_path] = odm_query_rx_pwr_percentage(rx_pwr); - p_phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage; - p_phy_info->rx_snr[rx_path] = rx_snr >> 1; - -#if 0 - /* if (p_pktinfo->is_packet_match_bssid) */ - { - dbg_print("path (%d)--------\n", rx_path); - dbg_print("rx_pwr = %d, Signal strength = %d\n", p_phy_info->rx_pwr[rx_path], p_phy_info->rx_mimo_signal_strength[rx_path]); - dbg_print("evm_dbm = %d, Signal quality = %d\n", p_phy_info->rx_mimo_evm_dbm[rx_path], p_phy_info->rx_mimo_signal_quality[rx_path]); - dbg_print("CFO = %d, SNR = %d\n", p_phy_info->cfo_tail[rx_path], p_phy_info->rx_snr[rx_path]); - } -#endif -} - -void -phydm_set_common_phy_info( - s8 rx_power, - u8 channel, - boolean is_beamformed, - boolean is_mu_packet, - u8 bandwidth, - u8 signal_quality, - u8 rxsc, - struct _odm_phy_status_info_ *p_phy_info -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->rx_power = rx_power; /* RSSI in dB */ - p_phy_info->recv_signal_power = rx_power; /* RSSI in dB */ - p_phy_info->channel = channel; /* channel number */ - p_phy_info->is_beamformed = is_beamformed; /* apply BF */ - p_phy_info->is_mu_packet = is_mu_packet; /* MU packet */ - p_phy_info->rxsc = rxsc; -#endif - p_phy_info->rx_pwdb_all = odm_query_rx_pwr_percentage(rx_power); /* RSSI in percentage */ - p_phy_info->signal_quality = signal_quality; /* signal quality */ - p_phy_info->band_width = bandwidth; /* bandwidth */ - -#if 0 - /* if (p_pktinfo->is_packet_match_bssid) */ - { - dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", p_phy_info->rx_pwdb_all, p_phy_info->rx_power, p_phy_info->recv_signal_power); - dbg_print("signal_quality = %d\n", p_phy_info->signal_quality); - dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", p_phy_info->is_beamformed, p_phy_info->is_mu_packet, p_phy_info->rx_count + 1); - dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel, rxsc, bandwidth); - } -#endif -} - -void -phydm_get_rx_phy_status_type0( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo, - struct _odm_phy_status_info_ *p_phy_info -) -{ - /* type 0 is used for cck packet */ - - struct _phy_status_rpt_jaguar2_type0 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type0 *)p_phy_status; - u8 SQ = 0; - s8 rx_power = p_phy_sta_rpt->pwdb - 110; - - - - if (p_dm_odm->support_ic_type & ODM_RTL8723D) { -#if (RTL8723D_SUPPORT == 1) - rx_power = p_phy_sta_rpt->pwdb - 97; -#endif - } -#if (RTL8710B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & ODM_RTL8710B) - rx_power = p_phy_sta_rpt->pwdb - 97; -#endif - -#if (RTL8821C_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & ODM_RTL8821C) { - if (p_phy_sta_rpt->pwdb >= -57) - rx_power = p_phy_sta_rpt->pwdb - 100; - else - rx_power = p_phy_sta_rpt->pwdb - 102; - } -#endif - - if (p_pktinfo->is_to_self) { - p_dm_odm->ofdm_agc_idx[0] = p_phy_sta_rpt->pwdb; - p_dm_odm->ofdm_agc_idx[1] = 0; - p_dm_odm->ofdm_agc_idx[2] = 0; - p_dm_odm->ofdm_agc_idx[3] = 0; - } - - - /* Calculate Signal Quality*/ - if (p_pktinfo->is_packet_match_bssid) { - if (p_phy_sta_rpt->signal_quality >= 64) - SQ = 0; - else if (p_phy_sta_rpt->signal_quality <= 20) - SQ = 100; - else { - /* mapping to 2~99% */ - SQ = 64 - p_phy_sta_rpt->signal_quality; - SQ = ((SQ << 3) + SQ) >> 2; - } - } - - /* Modify CCK PWDB if old AGC */ - if (p_dm_odm->cck_new_agc == false) { - u8 lna_idx, vga_idx; - -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - lna_idx = p_phy_sta_rpt->lna_l; - else -#endif - lna_idx = ((p_phy_sta_rpt->lna_h << 3) | p_phy_sta_rpt->lna_l); - vga_idx = p_phy_sta_rpt->vga; - -#if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8723D) - rx_power = odm_cckrssi_8723d(lna_idx, vga_idx); -#endif -/* JJ ADD 20161014 */ -#if (RTL8710B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8710B) - rx_power = odm_cckrssi_8710b(lna_idx, vga_idx); -#endif - -#if (RTL8822B_SUPPORT == 1) - /* Need to do !! */ - /*if (p_dm_odm->support_ic_type & ODM_RTL8822B) */ - /*rx_power = odm_CCKRSSI_8822B(LNA_idx, VGA_idx);*/ -#endif -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - rx_power = odm_cckrssi_8197f(p_dm_odm, lna_idx, vga_idx); -#endif - } - - /* Update CCK packet counter */ - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++; - - /*CCK no STBC and LDPC*/ - p_dm_odm->phy_dbg_info.is_ldpc_pkt = false; - p_dm_odm->phy_dbg_info.is_stbc_pkt = false; - - /* Update Common information */ - phydm_set_common_phy_info(rx_power, p_phy_sta_rpt->channel, false, - false, ODM_BW20M, SQ, p_phy_sta_rpt->rxsc, p_phy_info); - - /* Update CCK pwdb */ - phydm_set_per_path_phy_info(ODM_RF_PATH_A, rx_power, 0, 0, 0, p_phy_info); /* Update per-path information */ - - p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_a; - p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b; - p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c; - p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d; -#if 0 - /* if (p_pktinfo->is_packet_match_bssid) */ - { - dbg_print("pwdb = 0x%x, MP gain index = 0x%x, TRSW = 0x%x\n", p_phy_sta_rpt->pwdb, p_phy_sta_rpt->gain, p_phy_sta_rpt->trsw); - dbg_print("channel = %d, band = %d, rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->rxsc); - dbg_print("agc_table = 0x%x, agc_rpt 0x%x, bb_power = 0x%x\n", p_phy_sta_rpt->agc_table, p_phy_sta_rpt->agc_rpt, p_phy_sta_rpt->bb_power); - dbg_print("length = %d, SQ = %d\n", p_phy_sta_rpt->length, p_phy_sta_rpt->signal_quality); - dbg_print("antidx a = 0x%x, b = 0x%x, c = 0x%x, d = 0x%x\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d); - dbg_print("rsvd_0 = 0x%x, rsvd_1 = 0x%x, rsvd_2 = 0x%x\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2); - dbg_print("rsvd_3 = 0x%x, rsvd_4 = 0x%x, rsvd_5 = 0x%x\n", p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5); - dbg_print("rsvd_6 = 0x%x, rsvd_7 = 0x%x, rsvd_8 = 0x%x\n", p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7, p_phy_sta_rpt->rsvd_8); - } -#endif -} - -void -phydm_get_rx_phy_status_type1( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo, - struct _odm_phy_status_info_ *p_phy_info -) -{ - /* type 1 is used for ofdm packet */ - - struct _phy_status_rpt_jaguar2_type1 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type1 *)p_phy_status; - s8 rx_pwr_db = -120; - u8 i, rxsc, bw = ODM_BW20M, rx_count = 0; - boolean is_mu; - u8 num_ss; - - /* Update OFDM packet counter */ - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; - - /* Update per-path information */ - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (p_dm_odm->rx_ant_status & BIT(i)) { - s8 rx_path_pwr_db; - - /* RX path counter */ - rx_count++; - - /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ - /* EVM report is reported by stream, not path */ - rx_path_pwr_db = p_phy_sta_rpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ - - if (p_pktinfo->is_to_self) - p_dm_odm->ofdm_agc_idx[i] = p_phy_sta_rpt->pwdb[i]; - - phydm_set_per_path_phy_info(i, rx_path_pwr_db, p_phy_sta_rpt->rxevm[rx_count - 1], - p_phy_sta_rpt->cfo_tail[i], p_phy_sta_rpt->rxsnr[i], p_phy_info); - - /* search maximum pwdb */ - if (rx_path_pwr_db > rx_pwr_db) - rx_pwr_db = rx_path_pwr_db; - } - } - - /* mapping RX counter from 1~4 to 0~3 */ - if (rx_count > 0) - p_phy_info->rx_count = rx_count - 1; - - /* Check if MU packet or not */ - if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63)) { - is_mu = true; - p_dm_odm->phy_dbg_info.num_qry_mu_pkt++; - } else - is_mu = false; - - /* count BF packet */ - p_dm_odm->phy_dbg_info.num_qry_bf_pkt = p_dm_odm->phy_dbg_info.num_qry_bf_pkt + p_phy_sta_rpt->beamformed; - - /*STBC or LDPC pkt*/ - p_dm_odm->phy_dbg_info.is_ldpc_pkt = p_phy_sta_rpt->ldpc; - p_dm_odm->phy_dbg_info.is_stbc_pkt = p_phy_sta_rpt->stbc; - - /* Check sub-channel */ - if ((p_pktinfo->data_rate > ODM_RATE11M) && (p_pktinfo->data_rate < ODM_RATEMCS0)) - rxsc = p_phy_sta_rpt->l_rxsc; - else - rxsc = p_phy_sta_rpt->ht_rxsc; - - /* Check RX bandwidth */ - if (p_dm_odm->support_ic_type & ODM_RTL8822B) { - if ((rxsc >= 1) && (rxsc <= 8)) - bw = ODM_BW20M; - else if ((rxsc >= 9) && (rxsc <= 12)) - bw = ODM_BW40M; - else if (rxsc >= 13) - bw = ODM_BW80M; - else - bw = p_phy_sta_rpt->rf_mode; - } else if (p_dm_odm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D | ODM_RTL8710B)) {/* JJ ADD 20161014 */ - if (p_phy_sta_rpt->rf_mode == 0) - bw = ODM_BW20M; - else if ((rxsc == 1) || (rxsc == 2)) - bw = ODM_BW20M; - else - bw = ODM_BW40M; - } - - /* Update packet information */ - phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (boolean)p_phy_sta_rpt->beamformed, - is_mu, bw, odm_evm_db_to_percentage(p_phy_sta_rpt->rxevm[0]), rxsc, p_phy_info); - - num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); - - odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->cfo_tail, num_ss); - p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_a; - p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b; - p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c; - p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d; - - #if 0 - if (p_pktinfo->is_packet_match_bssid) { - - dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d, rf_mode = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc, p_phy_sta_rpt->rf_mode); - dbg_print("Antidx A = %d, B = %d, C = %d, D = %d\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d); - dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]); - dbg_print("EVM A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->rxevm[0], p_phy_sta_rpt->rxevm[1], p_phy_sta_rpt->rxevm[2], p_phy_sta_rpt->rxevm[3]); - dbg_print("SNR A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->rxsnr[0], p_phy_sta_rpt->rxsnr[1], p_phy_sta_rpt->rxsnr[2], p_phy_sta_rpt->rxsnr[3]); - dbg_print("CFO A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->cfo_tail[0], p_phy_sta_rpt->cfo_tail[1], p_phy_sta_rpt->cfo_tail[2], p_phy_sta_rpt->cfo_tail[3]); - dbg_print("paid = %d, gid = %d, length = %d\n", (p_phy_sta_rpt->paid + (p_phy_sta_rpt->paid_msb<<8)), p_phy_sta_rpt->gid, p_phy_sta_rpt->lsig_length); - dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu); - dbg_print("NBI: %d, pos: %d\n", p_phy_sta_rpt->nb_intf_flag, (p_phy_sta_rpt->intf_pos + (p_phy_sta_rpt->intf_pos_msb<<8))); - dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5); - - } - - dbg_print("phydm_get_rx_phy_status_type1 p_pktinfo->is_packet_match_bssid = %d\n", p_pktinfo->is_packet_match_bssid); - dbg_print("p_pktinfo->data_rate = 0x%x\n", p_pktinfo->data_rate); - #endif -} - -void -phydm_get_rx_phy_status_type2( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo, - struct _odm_phy_status_info_ *p_phy_info -) -{ - struct _phy_status_rpt_jaguar2_type2 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type2 *)p_phy_status; - s8 rx_pwr_db = -120; - u8 i, rxsc, bw = ODM_BW20M, rx_count = 0; - - /* Update OFDM packet counter */ - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; - - /* Update per-path information */ - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (p_dm_odm->rx_ant_status & BIT(i)) { - s8 rx_path_pwr_db; - - /* RX path counter */ - rx_count++; - - /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ -#if (RTL8197F_SUPPORT == 1) - if ((p_dm_odm->support_ic_type & ODM_RTL8197F) && (p_phy_sta_rpt->pwdb[i] == 0x7f)) { /*for 97f workaround*/ - - if (i == ODM_RF_PATH_A) { - rx_path_pwr_db = (p_phy_sta_rpt->gain_a) << 1; - rx_path_pwr_db = rx_path_pwr_db - 110; - } else if (i == ODM_RF_PATH_B) { - rx_path_pwr_db = (p_phy_sta_rpt->gain_b) << 1; - rx_path_pwr_db = rx_path_pwr_db - 110; - } else - rx_path_pwr_db = 0; - } else -#endif - rx_path_pwr_db = p_phy_sta_rpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ - - phydm_set_per_path_phy_info(i, rx_path_pwr_db, 0, 0, 0, p_phy_info); - - /* search maximum pwdb */ - if (rx_path_pwr_db > rx_pwr_db) - rx_pwr_db = rx_path_pwr_db; - } - } - - /* mapping RX counter from 1~4 to 0~3 */ - if (rx_count > 0) - p_phy_info->rx_count = rx_count - 1; - - /* Check RX sub-channel */ - if ((p_pktinfo->data_rate > ODM_RATE11M) && (p_pktinfo->data_rate < ODM_RATEMCS0)) - rxsc = p_phy_sta_rpt->l_rxsc; - else - rxsc = p_phy_sta_rpt->ht_rxsc; - - /*STBC or LDPC pkt*/ - p_dm_odm->phy_dbg_info.is_ldpc_pkt = p_phy_sta_rpt->ldpc; - p_dm_odm->phy_dbg_info.is_stbc_pkt = p_phy_sta_rpt->stbc; - - /* Check RX bandwidth */ - /* the BW information of sc=0 is useless, because there is no information of RF mode*/ - - if (p_dm_odm->support_ic_type & ODM_RTL8822B) { - if ((rxsc >= 1) && (rxsc <= 8)) - bw = ODM_BW20M; - else if ((rxsc >= 9) && (rxsc <= 12)) - bw = ODM_BW40M; - else if (rxsc >= 13) - bw = ODM_BW80M; - else - bw = ODM_BW20M; - } else if (p_dm_odm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D | ODM_RTL8710B)) {/* JJ ADD 20161014 */ - if (rxsc == 3) - bw = ODM_BW40M; - else if ((rxsc == 1) || (rxsc == 2)) - bw = ODM_BW20M; - else - bw = ODM_BW20M; - } - - /* Update packet information */ - phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (boolean)p_phy_sta_rpt->beamformed, - false, bw, 0, rxsc, p_phy_info); - -#if 0 - /* if (p_pktinfo->is_packet_match_bssid) */ - { - dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc); - dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]); - dbg_print("Agc table A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->agc_table_a, p_phy_sta_rpt->agc_table_b, p_phy_sta_rpt->agc_table_c, p_phy_sta_rpt->agc_table_d); - dbg_print("Gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->gain_a, p_phy_sta_rpt->gain_b, p_phy_sta_rpt->gain_c, p_phy_sta_rpt->gain_d); - dbg_print("TRSW A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->trsw_a, p_phy_sta_rpt->trsw_b, p_phy_sta_rpt->trsw_c, p_phy_sta_rpt->trsw_d); - dbg_print("AAGC step A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->aagc_step_a, p_phy_sta_rpt->aagc_step_b, p_phy_sta_rpt->aagc_step_c, p_phy_sta_rpt->aagc_step_d); - dbg_print("HT AAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->ht_aagc_gain[0], p_phy_sta_rpt->ht_aagc_gain[1], p_phy_sta_rpt->ht_aagc_gain[2], p_phy_sta_rpt->ht_aagc_gain[3]); - dbg_print("DAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->dagc_gain[0], p_phy_sta_rpt->dagc_gain[1], p_phy_sta_rpt->dagc_gain[2], p_phy_sta_rpt->dagc_gain[3]); - dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu); - dbg_print("counter: %d, syn_count: %d\n", p_phy_sta_rpt->counter, p_phy_sta_rpt->syn_count); - dbg_print("cnt_cca2agc_rdy: %d, cnt_pw2cca: %d, shift_l_map\n", p_phy_sta_rpt->cnt_cca2agc_rdy, p_phy_sta_rpt->cnt_pw2cca, p_phy_sta_rpt->shift_l_map); - dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4); - dbg_print("rsvd_5 = %d, rsvd_6 = %d, rsvd_6 = %d\n", p_phy_sta_rpt->rsvd_5, p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7); - } -#endif -} - -void -phydm_get_rx_phy_status_type5( - u8 *p_phy_status -) -{ - /* - dbg_print("DW0: 0x%02x%02x%02x%02x\n", *(p_phy_status + 3), *(p_phy_status + 2), *(p_phy_status + 1), *(p_phy_status + 0)); - dbg_print("DW1: 0x%02x%02x%02x%02x\n", *(p_phy_status + 7), *(p_phy_status + 6), *(p_phy_status + 5), *(p_phy_status + 4)); - dbg_print("DW2: 0x%02x%02x%02x%02x\n", *(p_phy_status + 11), *(p_phy_status + 10), *(p_phy_status + 9), *(p_phy_status + 8)); - dbg_print("DW3: 0x%02x%02x%02x%02x\n", *(p_phy_status + 15), *(p_phy_status + 14), *(p_phy_status + 13), *(p_phy_status + 12)); - dbg_print("DW4: 0x%02x%02x%02x%02x\n", *(p_phy_status + 19), *(p_phy_status + 18), *(p_phy_status + 17), *(p_phy_status + 16)); - dbg_print("DW5: 0x%02x%02x%02x%02x\n", *(p_phy_status + 23), *(p_phy_status + 22), *(p_phy_status + 21), *(p_phy_status + 20)); - dbg_print("DW6: 0x%02x%02x%02x%02x\n", *(p_phy_status + 27), *(p_phy_status + 26), *(p_phy_status + 25), *(p_phy_status + 24)); - */ -} - -void -phydm_process_rssi_for_dm_new_type( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - s32 undecorated_smoothed_pwdb, accumulate_pwdb; - u32 rssi_ave; - u8 i; - struct sta_info *p_entry; - u8 scaling_factor = 4; - - if (p_pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) - return; - - p_entry = p_dm_odm->p_odm_sta_info[p_pktinfo->station_id]; - - if (!IS_STA_VALID(p_entry)) - return; - - if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/ - return; - - if (p_pktinfo->is_packet_beacon) - p_dm_odm->phy_dbg_info.num_qry_beacon_pkt++; - -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - if (p_dm_odm->support_ability & ODM_BB_ANT_DIV) - odm_process_rssi_for_ant_div(p_dm_odm, p_phy_info, p_pktinfo); -#endif - -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_process_phy_status_for_dynamic_rx_path(p_dm_odm, p_phy_info, p_pktinfo); - dbg_print("====>\n"); -#endif - - if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_beacon) { - u32 RSSI_linear = 0; - - p_dm_odm->rx_rate = p_pktinfo->data_rate; - undecorated_smoothed_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - accumulate_pwdb = p_dm_odm->accumulate_pwdb[p_pktinfo->station_id]; - p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; - p_dm_odm->RSSI_C = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C]; - p_dm_odm->RSSI_D = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D]; - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (p_phy_info->rx_mimo_signal_strength[i] != 0) - RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[i]); - } - - switch (p_phy_info->rx_count + 1) { - case 2: - RSSI_linear = (RSSI_linear >> 1); - break; - case 3: - RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */ - break; - case 4: - RSSI_linear = (RSSI_linear >> 2); - break; - } - rssi_ave = odm_convert_to_db(RSSI_linear); - - if (undecorated_smoothed_pwdb <= 0) { - accumulate_pwdb = (p_phy_info->rx_pwdb_all << scaling_factor); - undecorated_smoothed_pwdb = p_phy_info->rx_pwdb_all; - } else { - accumulate_pwdb = accumulate_pwdb - (accumulate_pwdb >> scaling_factor) + rssi_ave; - undecorated_smoothed_pwdb = (accumulate_pwdb + (1 << (scaling_factor - 1))) >> scaling_factor; - } - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -#ifndef DM_ODM_CE_MAC80211 - if (p_entry->rssi_stat.undecorated_smoothed_pwdb == -1) - phydm_ra_rssi_rpt_wk(p_dm_odm); -#endif -#endif - p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb; - p_dm_odm->accumulate_pwdb[p_pktinfo->station_id] = accumulate_pwdb; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - if (p_pktinfo->station_id == 0) { - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); - - p_hal_data->UndecoratedSmoothedPWDB = undecorated_smoothed_pwdb; - } -#endif - } -} - -void -phydm_rx_phy_status_new_type( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo, - struct _odm_phy_status_info_ *p_phy_info -) -{ - u8 phy_status_type = (*p_phy_status & 0xf); - - /*dbg_print("phydm_rx_phy_status_new_type================> (page: %d)\n", phy_status_type);*/ - - /* Memory reset */ - phydm_reset_phy_info(p_dm_odm, p_phy_info); - p_dm_odm->rate_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); - - /* Phy status parsing */ - switch (phy_status_type) { - case 0: - { - phydm_get_rx_phy_status_type0(p_dm_odm, p_phy_status, p_pktinfo, p_phy_info); - break; - } - case 1: - { - phydm_get_rx_phy_status_type1(p_dm_odm, p_phy_status, p_pktinfo, p_phy_info); - break; - } - case 2: - { - phydm_get_rx_phy_status_type2(p_dm_odm, p_phy_status, p_pktinfo, p_phy_info); - break; - } -#if 0 - case 5: - { - phydm_get_rx_phy_status_type5(p_phy_status); - return; - } -#endif - default: - return; - } - - if (p_pktinfo->is_packet_match_bssid) { - phydm_avg_rssi_for_ss(p_dm_odm, p_phy_info, p_pktinfo); - phydm_rx_statistic_cal(p_dm_odm, p_phy_status, p_pktinfo); - } - - /* Update signal strength to UI, and p_phy_info->rx_pwdb_all is the maximum RSSI of all path */ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, p_phy_info->rx_pwdb_all, false, false); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, p_phy_info->rx_pwdb_all)); -#endif - - /* Calculate average RSSI and smoothed RSSI */ - phydm_process_rssi_for_dm_new_type(p_dm_odm, p_phy_info, p_pktinfo); - -} -/*==============================================*/ -#endif u32 query_phydm_trx_capability( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 value32 = 0xFFFFFFFF; #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - value32 = query_phydm_trx_capability_8821c(p_dm_odm); + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_trx_capability_8821c(dm); #endif return value32; @@ -3814,14 +966,14 @@ query_phydm_trx_capability( u32 query_phydm_stbc_capability( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 value32 = 0xFFFFFFFF; #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - value32 = query_phydm_stbc_capability_8821c(p_dm_odm); + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_stbc_capability_8821c(dm); #endif return value32; @@ -3829,14 +981,14 @@ query_phydm_stbc_capability( u32 query_phydm_ldpc_capability( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 value32 = 0xFFFFFFFF; #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - value32 = query_phydm_ldpc_capability_8821c(p_dm_odm); + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_ldpc_capability_8821c(dm); #endif return value32; @@ -3844,14 +996,14 @@ query_phydm_ldpc_capability( u32 query_phydm_txbf_parameters( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 value32 = 0xFFFFFFFF; #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - value32 = query_phydm_txbf_parameters_8821c(p_dm_odm); + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_txbf_parameters_8821c(dm); #endif return value32; @@ -3859,14 +1011,14 @@ query_phydm_txbf_parameters( u32 query_phydm_txbf_capability( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 value32 = 0xFFFFFFFF; #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - value32 = query_phydm_txbf_capability_8821c(p_dm_odm); + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_txbf_capability_8821c(dm); #endif return value32; diff --git a/hal/phydm/phydm_hwconfig.h b/hal/phydm/phydm_hwconfig.h index ff317f0..a695f69 100644 --- a/hal/phydm/phydm_hwconfig.h +++ b/hal/phydm/phydm_hwconfig.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ @@ -19,22 +29,13 @@ /*--------------------------Define -------------------------------------------*/ -#define CCK_RSSI_INIT_COUNT 5 - -#define RA_RSSI_STATE_INIT 0 -#define RA_RSSI_STATE_SEND 1 -#define RA_RSSI_STATE_HOLD 2 - -#define CFO_HW_RPT_2_MHZ(val) ((val<<1) + (val>>1)) -/* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */ - -#define AGC_DIFF_CONFIG_MP(ic, band) (odm_read_and_config_mp_##ic##_agc_tab_diff(p_dm_odm, array_mp_##ic##_agc_tab_diff_##band, \ +#define AGC_DIFF_CONFIG_MP(ic, band) (odm_read_and_config_mp_##ic##_agc_tab_diff(dm, array_mp_##ic##_agc_tab_diff_##band, \ sizeof(array_mp_##ic##_agc_tab_diff_##band)/sizeof(u32))) -#define AGC_DIFF_CONFIG_TC(ic, band) (odm_read_and_config_tc_##ic##_agc_tab_diff(p_dm_odm, array_tc_##ic##_agc_tab_diff_##band, \ +#define AGC_DIFF_CONFIG_TC(ic, band) (odm_read_and_config_tc_##ic##_agc_tab_diff(dm, array_tc_##ic##_agc_tab_diff_##band, \ sizeof(array_tc_##ic##_agc_tab_diff_##band)/sizeof(u32))) #define AGC_DIFF_CONFIG(ic, band) do {\ - if (p_dm_odm->is_mp_chip)\ + if (dm->is_mp_chip)\ AGC_DIFF_CONFIG_MP(ic, band);\ else\ AGC_DIFF_CONFIG_TC(ic, band);\ @@ -45,536 +46,58 @@ * structure and define * ************************************************************ */ -__PACK struct _phy_rx_agc_info { -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 gain: 7, trsw: 1; -#else - u8 trsw: 1, gain: 7; -#endif -}; - -__PACK struct _phy_status_rpt_8192cd { - struct _phy_rx_agc_info path_agc[2]; - u8 ch_corr[2]; - u8 cck_sig_qual_ofdm_pwdb_all; - u8 cck_agc_rpt_ofdm_cfosho_a; - u8 cck_rpt_b_ofdm_cfosho_b; - u8 rsvd_1;/*ch_corr_msb;*/ - u8 noise_power_db_msb; - s8 path_cfotail[2]; - u8 pcts_mask[2]; - s8 stream_rxevm[2]; - u8 path_rxsnr[2]; - u8 noise_power_db_lsb; - u8 rsvd_2[3]; - u8 stream_csi[2]; - u8 stream_target_csi[2]; - s8 sig_evm; - u8 rsvd_3; - -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/ - u8 sgi_en: 1; - u8 rxsc: 2; - u8 idle_long: 1; - u8 r_ant_train_en: 1; - u8 ant_sel_b: 1; - u8 ant_sel: 1; -#else /*_BIG_ENDIAN_ */ - u8 ant_sel: 1; - u8 ant_sel_b: 1; - u8 r_ant_train_en: 1; - u8 idle_long: 1; - u8 rxsc: 2; - u8 sgi_en: 1; - u8 antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/ -#endif -}; - - -struct _phy_status_rpt_8812 { - /* DWORD 0*/ - u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ - u8 chl_num_LSB; /*channel number[7:0]*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 chl_num_MSB: 2; /*channel number[9:8]*/ - u8 sub_chnl: 4; /*sub-channel location[3:0]*/ - u8 r_RFMOD: 2; /*RF mode[1:0]*/ -#else /*_BIG_ENDIAN_ */ - u8 r_RFMOD: 2; - u8 sub_chnl: 4; - u8 chl_num_MSB: 2; -#endif - - /* DWORD 1*/ - u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/ - s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - /*this should be checked again because the definition of 8812 and 8814 is different*/ - /* u8 r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/ - /* u8 cck_rx_path:4; cck rx path[3:0]*/ - u8 resvd_0: 6; - u8 bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/ -#else /*_BIG_ENDIAN_*/ - u8 bt_RF_ch_MSB: 2; - u8 resvd_0: 6; -#endif - - /* DWORD 2*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/ - u8 ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/ - u8 bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ -#else /*_BIG_ENDIAN_ */ - u8 bt_RF_ch_LSB: 6; - u8 ant_div_sw_b: 1; - u8 ant_div_sw_a: 1; -#endif - s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ - u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ - u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ - - /* DWORD 3*/ - s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ - s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ - - /* DWORD 4*/ - u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/ - u8 pcts_rpt_valid: 1; /*pcts_rpt_valid*/ - u8 resvd_1: 1; /*1'b0*/ -#else /*_BIG_ENDIAN_*/ - u8 resvd_1: 1; - u8 pcts_rpt_valid: 1; - u8 PCTS_MSK_RPT_3: 6; -#endif - s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/ - - /* DWORD 5*/ - u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/ - u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/ - - /* DWORD 6*/ - s8 sigevm; /*signal field EVM*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/ - u8 antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/ - u8 dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/ - u8 GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/ -#else /*_BIG_ENDIAN_*/ - u8 GNT_BT_keep: 1; - u8 dpdt_ctrl_keep: 1; - u8 antidx_antd: 3; - u8 antidx_antc: 3; -#endif -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 antidx_anta: 3; /*antidx_anta[2:0]*/ - u8 antidx_antb: 3; /*antidx_antb[2:0]*/ - u8 hw_antsw_occur: 2; /*1'b0*/ -#else /*_BIG_ENDIAN_*/ - u8 hw_antsw_occur: 2; - u8 antidx_antb: 3; - u8 antidx_anta: 3; -#endif -}; - -void -phydm_reset_avg_rssi_for_ss( - struct PHY_DM_STRUCT *p_dm_odm -); - -void -phydm_reset_rssi_for_dm( - struct PHY_DM_STRUCT *p_dm_odm, - u8 station_id -); - -u8 -phydm_rate_to_num_ss( - struct PHY_DM_STRUCT *p_dm_odm, - u8 data_rate -); - -void -odm_init_rssi_for_dm( - struct PHY_DM_STRUCT *p_dm_odm -); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -phydm_normal_driver_rx_sniffer( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_desc, - PRT_RFD_STATUS p_rt_rfd_status, - u8 *p_drv_info, - u8 phy_status -); -#endif - -void -odm_phy_status_query( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -); - -void -odm_mac_status_query( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_mac_status, - u8 mac_id, - boolean is_packet_match_bssid, - boolean is_packet_to_self, - boolean is_packet_beacon -); - enum hal_status odm_config_rf_with_tx_pwr_track_header_file( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); enum hal_status odm_config_rf_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum odm_rf_config_type config_type, - enum odm_rf_radio_path_e e_rf_path + u8 e_rf_path ); enum hal_status odm_config_bb_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum odm_bb_config_type config_type ); enum hal_status odm_config_mac_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm -); - -enum hal_status -odm_config_fw_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_fw_config_type config_type, - u8 *p_firmware, - u32 *p_size + struct dm_struct *dm ); u32 odm_get_hw_img_version( - struct PHY_DM_STRUCT *p_dm_odm -); - -s32 -odm_signal_scale_mapping( - struct PHY_DM_STRUCT *p_dm_odm, - s32 curr_sig -); - -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) -/*For 8822B only!! need to move to FW finally */ -/*==============================================*/ -void -phydm_rx_phy_status_new_type( - struct PHY_DM_STRUCT *p_phydm, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo, - struct _odm_phy_status_info_ *p_phy_info + struct dm_struct *dm ); -boolean -phydm_query_is_mu_api( - struct PHY_DM_STRUCT *p_phydm, - u8 ppdu_idx, - u8 *p_data_rate, - u8 *p_gid -); - -struct _phy_status_rpt_jaguar2_type0 { - /* DW0 */ - u8 page_num; - u8 pwdb; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 gain: 6; - u8 rsvd_0: 1; - u8 trsw: 1; -#else - u8 trsw: 1; - u8 rsvd_0: 1; - u8 gain: 6; -#endif - u8 rsvd_1; - - /* DW1 */ - u8 rsvd_2; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 rxsc: 4; - u8 agc_table: 4; -#else - u8 agc_table: 4; - u8 rxsc: 4; -#endif - u8 channel; - u8 band; - - /* DW2 */ - u16 length; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 antidx_a: 3; - u8 antidx_b: 3; - u8 rsvd_3: 2; - u8 antidx_c: 3; - u8 antidx_d: 3; - u8 rsvd_4:2; -#else - u8 rsvd_3: 2; - u8 antidx_b: 3; - u8 antidx_a: 3; - u8 rsvd_4:2; - u8 antidx_d: 3; - u8 antidx_c: 3; -#endif - - /* DW3 */ - u8 signal_quality; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 vga:5; - u8 lna_l:3; - u8 bb_power:6; - u8 rsvd_9:1; - u8 lna_h:1; -#else - u8 lna_l:3; - u8 vga:5; - u8 lna_h:1; - u8 rsvd_9:1; - u8 bb_power:6; -#endif - u8 rsvd_5; - - /* DW4 */ - u32 rsvd_6; - - /* DW5 */ - u32 rsvd_7; - - /* DW6 */ - u32 rsvd_8; -}; - -struct _phy_status_rpt_jaguar2_type1 { - /* DW0 and DW1 */ - u8 page_num; - u8 pwdb[4]; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 l_rxsc: 4; - u8 ht_rxsc: 4; -#else - u8 ht_rxsc: 4; - u8 l_rxsc: 4; -#endif - u8 channel; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 band: 2; - u8 rsvd_0: 1; - u8 hw_antsw_occu: 1; - u8 gnt_bt: 1; - u8 ldpc: 1; - u8 stbc: 1; - u8 beamformed: 1; -#else - u8 beamformed: 1; - u8 stbc: 1; - u8 ldpc: 1; - u8 gnt_bt: 1; - u8 hw_antsw_occu: 1; - u8 rsvd_0: 1; - u8 band: 2; -#endif - - /* DW2 */ - u16 lsig_length; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 antidx_a: 3; - u8 antidx_b: 3; - u8 rsvd_1: 2; - u8 antidx_c: 3; - u8 antidx_d: 3; - u8 rsvd_2: 2; -#else - u8 rsvd_1: 2; - u8 antidx_b: 3; - u8 antidx_a: 3; - u8 rsvd_2: 2; - u8 antidx_d: 3; - u8 antidx_c: 3; -#endif - - /* DW3 */ - u8 paid; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 paid_msb: 1; - u8 gid: 6; - u8 rsvd_3: 1; -#else - u8 rsvd_3: 1; - u8 gid: 6; - u8 paid_msb: 1; -#endif - u8 intf_pos; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 intf_pos_msb: 1; - u8 rsvd_4: 2; - u8 nb_intf_flag: 1; - u8 rf_mode: 2; - u8 rsvd_5: 2; -#else - u8 rsvd_5: 2; - u8 rf_mode: 2; - u8 nb_intf_flag: 1; - u8 rsvd_4: 2; - u8 intf_pos_msb: 1; -#endif - - /* DW4 */ - s8 rxevm[4]; /* s(8,1) */ - - /* DW5 */ - s8 cfo_tail[4]; /* s(8,7) */ - - /* DW6 */ - s8 rxsnr[4]; /* s(8,1) */ -}; - -struct _phy_status_rpt_jaguar2_type2 { - /* DW0 ane DW1 */ - u8 page_num; - u8 pwdb[4]; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 l_rxsc: 4; - u8 ht_rxsc: 4; -#else - u8 ht_rxsc: 4; - u8 l_rxsc: 4; -#endif - u8 channel; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 band: 2; - u8 rsvd_0: 1; - u8 hw_antsw_occu: 1; - u8 gnt_bt: 1; - u8 ldpc: 1; - u8 stbc: 1; - u8 beamformed: 1; -#else - u8 beamformed: 1; - u8 stbc: 1; - u8 ldpc: 1; - u8 gnt_bt: 1; - u8 hw_antsw_occu: 1; - u8 rsvd_0: 1; - u8 band: 2; -#endif - - /* DW2 */ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 shift_l_map: 6; - u8 rsvd_1: 2; -#else - u8 rsvd_1: 2; - u8 shift_l_map: 6; -#endif - u8 cnt_pw2cca; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 agc_table_a: 4; - u8 agc_table_b: 4; - u8 agc_table_c: 4; - u8 agc_table_d: 4; -#else - u8 agc_table_b: 4; - u8 agc_table_a: 4; - u8 agc_table_d: 4; - u8 agc_table_c: 4; -#endif - - /* DW3 ~ DW6*/ - u8 cnt_cca2agc_rdy; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 gain_a: 6; - u8 rsvd_2: 1; - u8 trsw_a: 1; - u8 gain_b: 6; - u8 rsvd_3: 1; - u8 trsw_b: 1; - u8 gain_c: 6; - u8 rsvd_4: 1; - u8 trsw_c: 1; - u8 gain_d: 6; - u8 rsvd_5: 1; - u8 trsw_d: 1; - u8 aagc_step_a: 2; - u8 aagc_step_b: 2; - u8 aagc_step_c: 2; - u8 aagc_step_d: 2; -#else - u8 trsw_a: 1; - u8 rsvd_2: 1; - u8 gain_a: 6; - u8 trsw_b: 1; - u8 rsvd_3: 1; - u8 gain_b: 6; - u8 trsw_c: 1; - u8 rsvd_4: 1; - u8 gain_c: 6; - u8 trsw_d: 1; - u8 rsvd_5: 1; - u8 gain_d: 6; - u8 aagc_step_d: 2; - u8 aagc_step_c: 2; - u8 aagc_step_b: 2; - u8 aagc_step_a: 2; -#endif - u8 ht_aagc_gain[4]; - u8 dagc_gain[4]; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 counter: 6; - u8 rsvd_6: 2; - u8 syn_count: 5; - u8 rsvd_7:3; -#else - u8 rsvd_6: 2; - u8 counter: 6; - u8 rsvd_7:3; - u8 syn_count: 5; -#endif -}; -/*==============================================*/ -#endif /*#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)*/ u32 query_phydm_trx_capability( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 query_phydm_stbc_capability( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 query_phydm_ldpc_capability( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 query_phydm_txbf_parameters( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 query_phydm_txbf_capability( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); #endif /*#ifndef __HALHWOUTSRC_H__*/ diff --git a/hal/phydm/phydm_interface.c b/hal/phydm/phydm_interface.c index 1392300..e12bac9 100644 --- a/hal/phydm/phydm_interface.c +++ b/hal/phydm/phydm_interface.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -26,22 +36,22 @@ u8 odm_read_1byte( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; return RTL_R8(reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; return rtl_read_byte(rtlpriv, reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; return rtw_read8(adapter, reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; return PlatformEFIORead1Byte(adapter, reg_addr); #endif @@ -50,22 +60,22 @@ odm_read_1byte( u16 odm_read_2byte( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; return RTL_R16(reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; return rtl_read_word(rtlpriv, reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; return rtw_read16(adapter, reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; return PlatformEFIORead2Byte(adapter, reg_addr); #endif @@ -74,22 +84,22 @@ odm_read_2byte( u32 odm_read_4byte( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; return RTL_R32(reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; return rtl_read_dword(rtlpriv, reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; return rtw_read32(adapter, reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; return PlatformEFIORead4Byte(adapter, reg_addr); #endif @@ -98,23 +108,23 @@ odm_read_4byte( void odm_write_1byte( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u8 data ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; RTL_W8(reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; rtl_write_byte(rtlpriv, reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; rtw_write8(adapter, reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PlatformEFIOWrite1Byte(adapter, reg_addr, data); #endif @@ -123,23 +133,23 @@ odm_write_1byte( void odm_write_2byte( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u16 data ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; RTL_W16(reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; rtl_write_word(rtlpriv, reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; rtw_write16(adapter, reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PlatformEFIOWrite2Byte(adapter, reg_addr, data); #endif @@ -148,23 +158,23 @@ odm_write_2byte( void odm_write_4byte( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u32 data ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; RTL_W32(reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; rtl_write_dword(rtlpriv, reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; rtw_write32(adapter, reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PlatformEFIOWrite4Byte(adapter, reg_addr, data); #endif @@ -173,162 +183,159 @@ odm_write_4byte( void odm_set_mac_reg( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - phy_set_bb_reg(p_dm_odm->priv, reg_addr, bit_mask, data); + phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PHY_SetBBReg(adapter, reg_addr, bit_mask, data); + PHY_SetBBReg((PADAPTER)dm->adapter, reg_addr, bit_mask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data); #else - phy_set_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask, data); + phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data); #endif } u32 odm_get_mac_reg( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u32 bit_mask ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return phy_query_bb_reg(p_dm_odm->priv, reg_addr, bit_mask); + return phy_query_bb_reg(dm->priv, reg_addr, bit_mask); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - return PHY_QueryMacReg(p_dm_odm->adapter, reg_addr, bit_mask); + return PHY_QueryMacReg((PADAPTER)dm->adapter, reg_addr, bit_mask); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask); #else - return phy_query_mac_reg(p_dm_odm->adapter, reg_addr, bit_mask); + return phy_query_mac_reg(dm->adapter, reg_addr, bit_mask); #endif } void odm_set_bb_reg( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - phy_set_bb_reg(p_dm_odm->priv, reg_addr, bit_mask, data); + phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PHY_SetBBReg(adapter, reg_addr, bit_mask, data); + PHY_SetBBReg((PADAPTER)dm->adapter, reg_addr, bit_mask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data); #else - phy_set_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask, data); + phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data); #endif } u32 odm_get_bb_reg( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u32 bit_mask ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return phy_query_bb_reg(p_dm_odm->priv, reg_addr, bit_mask); + return phy_query_bb_reg(dm->priv, reg_addr, bit_mask); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - return PHY_QueryBBReg(adapter, reg_addr, bit_mask); + return PHY_QueryBBReg((PADAPTER)dm->adapter, reg_addr, bit_mask); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask); #else - return phy_query_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask); + return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask); #endif } void odm_set_rf_reg( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e e_rf_path, + struct dm_struct *dm, + u8 e_rf_path, u32 reg_addr, u32 bit_mask, u32 data ) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_set_rf_reg(p_dm_odm->priv, e_rf_path, reg_addr, bit_mask, data); + phy_set_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PHY_SetRFReg(adapter, e_rf_path, reg_addr, bit_mask, data); + PHY_SetRFReg((PADAPTER)dm->adapter, e_rf_path, reg_addr, bit_mask, data); ODM_delay_us(2); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; rtl_set_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - phy_set_rf_reg(p_dm_odm->adapter, e_rf_path, reg_addr, bit_mask, data); + phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data); #endif } u32 odm_get_rf_reg( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e e_rf_path, + struct dm_struct *dm, + u8 e_rf_path, u32 reg_addr, u32 bit_mask ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return phy_query_rf_reg(p_dm_odm->priv, e_rf_path, reg_addr, bit_mask, 1); + return phy_query_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, 1); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - return PHY_QueryRFReg(adapter, e_rf_path, reg_addr, bit_mask); + return PHY_QueryRFReg((PADAPTER)dm->adapter, e_rf_path, reg_addr, bit_mask); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; return rtl_get_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask); #else - return phy_query_rf_reg(p_dm_odm->adapter, e_rf_path, reg_addr, bit_mask); + return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask); #endif } enum hal_status phydm_set_reg_by_fw( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum phydm_halmac_param config_type, u32 offset, u32 data, u32 mask, - enum odm_rf_radio_path_e e_rf_path, + enum rf_path e_rf_path, u32 delay_time ) { - enum hal_status stat = HAL_STATUS_SUCCESS; #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - stat = HAL_MAC_Config_PHY_WriteNByte(p_dm_odm, + return HAL_MAC_Config_PHY_WriteNByte(dm, config_type, offset, data, mask, e_rf_path, delay_time); -#elif (0)/*(DM_ODM_SUPPORT_TYPE & ODM_CE)*/ - return rtw_phydm_cfg_phy_para(p_dm_odm, +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + PHYDM_DBG(dm, ODM_COMP_COMMON, "Not support for CE MAC80211 driver!\n"); +#else + return rtw_phydm_cfg_phy_para(dm, config_type, offset, data, @@ -336,7 +343,7 @@ phydm_set_reg_by_fw( e_rf_path, delay_time); #endif - return stat; +#endif } @@ -346,64 +353,64 @@ phydm_set_reg_by_fw( * */ void odm_allocate_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void **p_ptr, + struct dm_struct *dm, + void **ptr, u32 length ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - *p_ptr = kmalloc(length, GFP_ATOMIC); + *ptr = kmalloc(length, GFP_ATOMIC); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - *p_ptr = kmalloc(length, GFP_ATOMIC); + *ptr = kmalloc(length, GFP_ATOMIC); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - *p_ptr = rtw_zvmalloc(length); + *ptr = rtw_zvmalloc(length); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PlatformAllocateMemory(adapter, p_ptr, length); + void *adapter = dm->adapter; + PlatformAllocateMemory(adapter, ptr, length); #endif } /* length could be ignored, used to detect memory leakage. */ void odm_free_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void *p_ptr, + struct dm_struct *dm, + void *ptr, u32 length ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - kfree(p_ptr); + kfree(ptr); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - kfree(p_ptr); + kfree(ptr); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_vmfree(p_ptr, length); + rtw_vmfree(ptr, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - /* struct _ADAPTER* adapter = p_dm_odm->adapter; */ - PlatformFreeMemory(p_ptr, length); + /* struct void* adapter = dm->adapter; */ + PlatformFreeMemory(ptr, length); #endif } void odm_move_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void *p_dest, - void *p_src, + struct dm_struct *dm, + void *dest, + void *src, u32 length ) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - memcpy(p_dest, p_src, length); + memcpy(dest, src, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - memcpy(p_dest, p_src, length); + memcpy(dest, src, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - _rtw_memcpy(p_dest, p_src, length); + _rtw_memcpy(dest, src, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformMoveMemory(p_dest, p_src, length); + PlatformMoveMemory(dest, src, length); #endif } void odm_memory_set( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, void *pbuf, s8 value, u32 length @@ -420,20 +427,20 @@ void odm_memory_set( #endif } s32 odm_compare_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void *p_buf1, - void *p_buf2, + struct dm_struct *dm, + void *buf1, + void *buf2, u32 length ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return memcmp(p_buf1, p_buf2, length); + return memcmp(buf1, buf2, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - return memcmp(p_buf1, p_buf2, length); + return memcmp(buf1, buf2, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - return _rtw_memcmp(p_buf1, p_buf2, length); + return _rtw_memcmp(buf1, buf2, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - return PlatformCompareMemory(p_buf1, p_buf2, length); + return PlatformCompareMemory(buf1, buf2, length); #endif } @@ -444,35 +451,39 @@ s32 odm_compare_memory( * */ void odm_acquire_spin_lock( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum rt_spinlock_type type ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + rtl_odm_acquirespinlock(rtlpriv, type); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; rtw_odm_acquirespinlock(adapter, type); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PlatformAcquireSpinLock(adapter, type); #endif } void odm_release_spin_lock( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum rt_spinlock_type type ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + rtl_odm_releasespinlock(rtlpriv, type); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; rtw_odm_releasespinlock(adapter, type); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PlatformReleaseSpinLock(adapter, type); #endif } @@ -483,10 +494,10 @@ odm_release_spin_lock( * */ void odm_initialize_work_item( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, PRT_WORK_ITEM p_rt_work_item, RT_WORKITEM_CALL_BACK rt_work_item_callback, - void *p_context, + void *context, const char *sz_id ) { @@ -495,8 +506,8 @@ odm_initialize_work_item( #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PlatformInitializeWorkItem(adapter, p_rt_work_item, rt_work_item_callback, p_context, sz_id); + void *adapter = dm->adapter; + PlatformInitializeWorkItem(adapter, p_rt_work_item, rt_work_item_callback, context, sz_id); #endif } @@ -580,21 +591,6 @@ odm_is_work_item_scheduled( /* * ODM Timer relative API. * */ -void -odm_stall_execution( - u32 us_delay -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - udelay(us_delay); -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_udelay_os(us_delay); -#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformStallExecution(us_delay); -#endif -} void ODM_delay_ms(u32 ms) @@ -628,12 +624,13 @@ void ODM_sleep_ms(u32 ms) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - + delay_ms(ms); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) msleep(ms); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) rtw_msleep_os(ms); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + delay_ms(ms); #endif } @@ -641,103 +638,90 @@ void ODM_sleep_us(u32 us) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - + delay_us(us); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) usleep_range(us, us + 1); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) rtw_usleep_os(us); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStallExecution(us); #endif } void odm_set_timer( - struct PHY_DM_STRUCT *p_dm_odm, - #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) - struct legacy_timer_emu *p_timer, - #else - struct timer_list *p_timer, - #endif + struct dm_struct *dm, + struct phydm_timer_list *timer, u32 ms_delay ) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - mod_timer(p_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay)); + mod_timer(timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay)); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - mod_timer(p_timer, jiffies + msecs_to_jiffies(ms_delay)); + mod_timer(timer, jiffies + msecs_to_jiffies(ms_delay)); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - _set_timer(p_timer, ms_delay); /* ms */ + _set_timer(timer, ms_delay); /* ms */ #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PlatformSetTimer(adapter, p_timer, ms_delay); + void *adapter = dm->adapter; + PlatformSetTimer(adapter, timer, ms_delay); #endif } void odm_initialize_timer( - struct PHY_DM_STRUCT *p_dm_odm, - #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) - struct legacy_timer_emu *p_timer, - #else - struct timer_list *p_timer, - #endif + struct dm_struct *dm, + struct phydm_timer_list *timer, void *call_back_func, - void *p_context, + void *context, const char *sz_id ) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - init_timer(p_timer); - p_timer->function = call_back_func; - p_timer->data = (unsigned long)p_dm_odm; - /*mod_timer(p_timer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */ + init_timer(timer); + timer->function = call_back_func; + timer->data = (unsigned long)dm; + /*mod_timer(timer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */ #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - init_timer(p_timer); - p_timer->function = call_back_func; - p_timer->data = (unsigned long)p_dm_odm; - /*mod_timer(p_timer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */ + init_timer(timer); + timer->function = call_back_func; + timer->data = (unsigned long)dm; + /*mod_timer(timer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */ #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; - _init_timer(p_timer, adapter->pnetdev, call_back_func, p_dm_odm); + struct _ADAPTER *adapter = dm->adapter; + + _init_timer(timer, adapter->pnetdev, call_back_func, dm); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PlatformInitializeTimer(adapter, p_timer, call_back_func, p_context, sz_id); + void *adapter = dm->adapter; + + PlatformInitializeTimer(adapter, timer, (RT_TIMER_CALL_BACK)call_back_func, context, sz_id); #endif } void odm_cancel_timer( - struct PHY_DM_STRUCT *p_dm_odm, - #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) - struct legacy_timer_emu *p_timer - #else - struct timer_list *p_timer - #endif + struct dm_struct *dm, + struct phydm_timer_list *timer ) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - del_timer(p_timer); + del_timer(timer); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - del_timer(p_timer); + del_timer(timer); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - _cancel_timer_ex(p_timer); + _cancel_timer_ex(timer); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PlatformCancelTimer(adapter, p_timer); + void *adapter = dm->adapter; + PlatformCancelTimer(adapter, timer); #endif } void odm_release_timer( - struct PHY_DM_STRUCT *p_dm_odm, - #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) - struct legacy_timer_emu *p_timer - #else - struct timer_list *p_timer - #endif + struct dm_struct *dm, + struct phydm_timer_list *timer ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) @@ -746,23 +730,23 @@ odm_release_timer( #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; /* <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm. * Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail. */ - if (p_timer == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>odm_release_timer(), The timer is NULL! Please check it!\n")); + if (timer == 0) { + PHYDM_DBG(dm, ODM_COMP_INIT, "=====>odm_release_timer(), The timer is NULL! Please check it!\n"); return; } - PlatformReleaseTimer(adapter, p_timer); + PlatformReleaseTimer(adapter, timer); #endif } u8 phydm_trans_h2c_id( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 phydm_h2c_id ) { @@ -773,9 +757,9 @@ phydm_trans_h2c_id( case ODM_H2C_RSSI_REPORT: #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) + if (dm->support_ic_type == ODM_RTL8188E) platform_h2c_id = H2C_88E_RSSI_REPORT; - else if (p_dm_odm->support_ic_type == ODM_RTL8814A) + else if (dm->support_ic_type == ODM_RTL8814A) platform_h2c_id = H2C_8814A_RSSI_REPORT; else platform_h2c_id = H2C_RSSI_REPORT; @@ -786,12 +770,12 @@ phydm_trans_h2c_id( #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) + if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES) platform_h2c_id = H2C_88XX_RSSI_REPORT; else #endif #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) + if (dm->support_ic_type == ODM_RTL8812) platform_h2c_id = H2C_8812_RSSI_REPORT; else #endif @@ -832,7 +816,7 @@ phydm_trans_h2c_id( case ODM_H2C_RA_PARA_ADJUST: #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) + if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) platform_h2c_id = H2C_8814A_RA_PARA_ADJUST; else platform_h2c_id = H2C_RA_PARA_ADJUST; @@ -850,12 +834,12 @@ phydm_trans_h2c_id( #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) + if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES) platform_h2c_id = H2C_88XX_RA_PARA_ADJUST; else #endif #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) + if (dm->support_ic_type == ODM_RTL8812) platform_h2c_id = H2C_8812_RA_PARA_ADJUST; else #endif @@ -869,16 +853,16 @@ phydm_trans_h2c_id( case PHYDM_H2C_DYNAMIC_TX_PATH: #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) + if (dm->support_ic_type == ODM_RTL8814A) platform_h2c_id = H2C_8814A_DYNAMIC_TX_PATH; #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) + if (dm->support_ic_type == ODM_RTL8814A) platform_h2c_id = H2C_DYNAMIC_TX_PATH; #endif #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) + if (dm->support_ic_type == ODM_RTL8814A) platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH; #endif @@ -890,7 +874,7 @@ phydm_trans_h2c_id( case PHYDM_H2C_FW_TRACE_EN: #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) + if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) platform_h2c_id = H2C_8814A_FW_TRACE_EN; else platform_h2c_id = H2C_FW_TRACE_EN; @@ -901,12 +885,12 @@ phydm_trans_h2c_id( #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) + if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES) platform_h2c_id = H2C_88XX_FW_TRACE_EN; else #endif #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) + if (dm->support_ic_type == ODM_RTL8812) platform_h2c_id = H2C_8812_FW_TRACE_EN; else #endif @@ -941,118 +925,120 @@ phydm_trans_h2c_id( void odm_fill_h2c_cmd( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 phydm_h2c_id, u32 cmd_len, - u8 *p_cmd_buffer + u8 *cmd_buffer ) { #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; #else - struct _ADAPTER *adapter = p_dm_odm->adapter; + PADAPTER adapter = (PADAPTER)dm->adapter; #endif - u8 platform_h2c_id; + u8 h2c_id = phydm_trans_h2c_id(dm, phydm_h2c_id); - platform_h2c_id = phydm_trans_h2c_id(p_dm_odm, phydm_h2c_id); - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] platform_h2c_id = ((0x%x))\n", platform_h2c_id)); + PHYDM_DBG(dm, DBG_RA, "[H2C] h2c_id=((0x%x))\n", h2c_id); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - if (!p_dm_odm->ra_support88e) - FillH2CCmd88E(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); - } else if (p_dm_odm->support_ic_type == ODM_RTL8814A) - FillH2CCmd8814A(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) -#if (RTL8822B_SUPPORT == 1) - FillH2CCmd8822B(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); -#endif + if (dm->support_ic_type == ODM_RTL8188E) { + if (!dm->ra_support88e) + FillH2CCmd88E(adapter, h2c_id, cmd_len, cmd_buffer); + } else if (dm->support_ic_type == ODM_RTL8814A) + FillH2CCmd8814A(adapter, h2c_id, cmd_len, cmd_buffer); + else if (dm->support_ic_type == ODM_RTL8822B) + FillH2CCmd8822B(adapter, h2c_id, cmd_len, cmd_buffer); else - FillH2CCmd(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); + FillH2CCmd(adapter, h2c_id, cmd_len, cmd_buffer); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) -#ifdef DM_ODM_CE_MAC80211 - rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, platform_h2c_id, - cmd_len, p_cmd_buffer); -#else - - rtw_hal_fill_h2c_cmd(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); -#endif + #ifdef DM_ODM_CE_MAC80211 + rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, h2c_id,cmd_len, cmd_buffer); + #else + rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buffer); + #endif #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) -#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) - GET_HAL_INTERFACE(p_dm_odm->priv)->fill_h2c_cmd_handler(p_dm_odm->priv, platform_h2c_id, cmd_len, p_cmd_buffer); - else -#endif -#if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - fill_h2c_cmd8812(p_dm_odm->priv, platform_h2c_id, cmd_len, p_cmd_buffer); - else -#endif - {} + + #if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8812) { + fill_h2c_cmd8812(dm->priv, h2c_id, cmd_len, cmd_buffer); + } else + #endif + { + GET_HAL_INTERFACE(dm->priv)->fill_h2c_cmd_handler(dm->priv, h2c_id, cmd_len, cmd_buffer); + } #endif } u8 phydm_c2H_content_parsing( - void *p_dm_void, + void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len, u8 *tmp_buf ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; #endif u8 extend_c2h_sub_id = 0; u8 find_c2h_cmd = true; - + + if ((c2h_cmd_len > 12) || (c2h_cmd_len == 0)) { + pr_debug("[Warning] Error C2H ID=%d, len=%d\n", c2h_cmd_id, c2h_cmd_len); + + find_c2h_cmd = false; + return find_c2h_cmd; + } + switch (c2h_cmd_id) { case PHYDM_C2H_DBG: - phydm_fw_trace_handler(p_dm_odm, tmp_buf, c2h_cmd_len); + phydm_fw_trace_handler(dm, tmp_buf, c2h_cmd_len); break; case PHYDM_C2H_RA_RPT: - phydm_c2h_ra_report_handler(p_dm_odm, tmp_buf, c2h_cmd_len); + phydm_c2h_ra_report_handler(dm, tmp_buf, c2h_cmd_len); break; case PHYDM_C2H_RA_PARA_RPT: - odm_c2h_ra_para_report_handler(p_dm_odm, tmp_buf, c2h_cmd_len); + odm_c2h_ra_para_report_handler(dm, tmp_buf, c2h_cmd_len); break; case PHYDM_C2H_DYNAMIC_TX_PATH_RPT: - if (p_dm_odm->support_ic_type & (ODM_RTL8814A)) - phydm_c2h_dtp_handler(p_dm_odm, tmp_buf, c2h_cmd_len); + if (dm->support_ic_type & (ODM_RTL8814A)) + phydm_c2h_dtp_handler(dm, tmp_buf, c2h_cmd_len); break; case PHYDM_C2H_IQK_FINISH: #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) { - + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) { RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n")); - odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); - p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false; - odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); - p_dm_odm->rf_calibrate_info.iqk_progressing_time = 0; - p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.iqk_progressing_time = 0; + dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time); } #endif break; + case PHYDM_C2H_CLM_MONITOR: + phydm_clm_c2h_report_handler(dm, tmp_buf, c2h_cmd_len); + break; + case PHYDM_C2H_DBG_CODE: - phydm_fw_trace_handler_code(p_dm_odm, tmp_buf, c2h_cmd_len); + phydm_fw_trace_handler_code(dm, tmp_buf, c2h_cmd_len); break; case PHYDM_C2H_EXTEND: extend_c2h_sub_id = tmp_buf[0]; if (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT) - phydm_fw_trace_handler_8051(p_dm_odm, tmp_buf, c2h_cmd_len); + phydm_fw_trace_handler_8051(dm, tmp_buf, c2h_cmd_len); break; @@ -1067,15 +1053,15 @@ phydm_c2H_content_parsing( u64 odm_get_current_time( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return 0; + return (u64)rtw_get_current_time(); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) return jiffies; #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - return (u64)rtw_get_current_time(); + return rtw_get_current_time(); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) return PlatformGetCurrentTime(); #endif @@ -1083,16 +1069,16 @@ odm_get_current_time( u64 odm_get_progressing_time( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u64 start_time ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return 0; + return rtw_get_passing_time_ms((u32)start_time); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - return jiffies_to_msecs(jiffies - (u32)start_time); + return jiffies_to_msecs(jiffies - start_time); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - return rtw_get_passing_time_ms((u32)start_time); + return rtw_get_passing_time_ms((systime)start_time); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) return ((PlatformGetCurrentTime() - start_time) >> 10); #endif @@ -1102,16 +1088,16 @@ odm_get_progressing_time( void phydm_set_hw_reg_handler_interface ( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 RegName, u8 *val ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _ADAPTER *adapter = (PADAPTER)dm->adapter; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - adapter->HalFunc.SetHwRegHandler(adapter, RegName, val); + ((PADAPTER)adapter)->HalFunc.SetHwRegHandler(adapter, RegName, val); #else adapter->hal_func.set_hw_reg_handler(adapter, RegName, val); #endif @@ -1122,18 +1108,18 @@ phydm_set_hw_reg_handler_interface ( void phydm_get_hal_def_var_handler_interface ( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum _HAL_DEF_VARIABLE e_variable, - void *p_value + void *value ) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _ADAPTER *adapter = (PADAPTER)dm->adapter; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - adapter->HalFunc.GetHalDefVarHandler(adapter, e_variable, p_value); + adapter->HalFunc.GetHalDefVarHandler(adapter, e_variable, value); #else - adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, p_value); + adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, value); #endif #endif @@ -1143,42 +1129,39 @@ phydm_get_hal_def_var_handler_interface ( void odm_set_tx_power_index_by_rate_section ( - struct PHY_DM_STRUCT *p_dm_odm, - u8 RFPath, - u8 Channel, - u8 RateSection + struct dm_struct *dm, + enum rf_path path, + u8 channel, + u8 rate_section ) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PHY_SetTxPowerIndexByRateSection(adapter, RFPath, Channel, RateSection); + PHY_SetTxPowerIndexByRateSection((PADAPTER)dm->adapter, path, channel, rate_section); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - void *adapter = p_dm_odm->adapter; - - phy_set_tx_power_index_by_rs(adapter, Channel, RFPath, RateSection); + phy_set_tx_power_index_by_rs((PADAPTER)dm->adapter, channel, path, rate_section); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - phy_set_tx_power_index_by_rate_section(p_dm_odm->adapter, RFPath, Channel, RateSection); + phy_set_tx_power_index_by_rate_section(dm->adapter, path, channel, rate_section); #endif } u8 odm_get_tx_power_index ( - struct PHY_DM_STRUCT *p_dm_odm, - u8 RFPath, + struct dm_struct *dm, + enum rf_path path, u8 tx_rate, u8 band_width, - u8 Channel + u8 channel ) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - return PHY_GetTxPowerIndex(p_dm_odm->adapter, RFPath, tx_rate, band_width, Channel); + return PHY_GetTxPowerIndex((PADAPTER)dm->adapter, path, tx_rate, (CHANNEL_WIDTH)band_width, channel); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - void *adapter = p_dm_odm->adapter; - return phy_get_tx_power_index(adapter, (enum odm_rf_radio_path_e)RFPath, tx_rate, band_width, Channel); + void *adapter = dm->adapter; + + return phy_get_tx_power_index(adapter, (enum rf_path)path, tx_rate, band_width, channel); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - return phy_get_tx_power_index(p_dm_odm->adapter, RFPath, tx_rate, band_width, Channel); + return phy_get_tx_power_index(dm->adapter, path, tx_rate, band_width, channel); #endif } @@ -1186,24 +1169,22 @@ odm_get_tx_power_index ( u8 odm_efuse_one_byte_read( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u16 addr, u8 *data, boolean b_pseu_do_test ) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - - return (u8)EFUSE_OneByteRead(adapter, addr, data, b_pseu_do_test); + return (u8)EFUSE_OneByteRead((PADAPTER)dm->adapter, addr, data, b_pseu_do_test); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) - void *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; - return efuse_onebyte_read(adapter, addr, data, b_pseu_do_test); + return rtl_efuse_onebyte_read(adapter, addr, data, b_pseu_do_test); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - return efuse_onebyte_read(p_dm_odm->adapter, addr, data, b_pseu_do_test); + return efuse_onebyte_read(dm->adapter, addr, data, b_pseu_do_test); #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) - /*ReadEFuseByte(p_dm_odm->priv, addr, data);*/ + /*ReadEFuseByte(dm->priv, addr, data);*/ /*return true;*/ #endif } @@ -1212,24 +1193,26 @@ odm_efuse_one_byte_read( void odm_efuse_logical_map_read( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 type, u16 offset, u32 *data ) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + EFUSE_ShadowRead((PADAPTER)dm->adapter, type, offset, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = dm->adapter; - EFUSE_ShadowRead(adapter, type, offset, data); + rtl_efuse_logical_map_read(adapter, type, offset, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - efuse_logical_map_read(p_dm_odm->adapter, type, offset, data); + efuse_logical_map_read(dm->adapter, type, offset, data); #endif } enum hal_status odm_iq_calibrate_by_fw( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 clear, u8 segment ) @@ -1237,45 +1220,33 @@ odm_iq_calibrate_by_fw( enum hal_status iqk_result = HAL_STATUS_FAILURE; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - + struct _ADAPTER *adapter = (PADAPTER)dm->adapter; + if (HAL_MAC_FWIQK_Trigger(&GET_HAL_MAC_INFO(adapter), clear, segment) == 0) iqk_result = HAL_STATUS_SUCCESS; #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - #ifdef RTW_HALMAC - #include "../hal_halmac.h" - struct _ADAPTER *adapter = p_dm_odm->adapter; - - if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0) - iqk_result = HAL_STATUS_SUCCESS; - #endif +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = dm->adapter; + iqk_result = rtl_phydm_fw_iqk(adapter, clear, segment); +#else + iqk_result = rtw_phydm_fw_iqk(dm, clear, segment); +#endif #endif return iqk_result; } void odm_cmn_info_ptr_array_hook( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_cmninfo_e cmn_info, + struct dm_struct *dm, + enum odm_cmninfo cmn_info, u16 index, - void *p_value + void *value ) { switch (cmn_info) { /*Dynamic call by reference pointer. */ case ODM_CMNINFO_STA_STATUS: - p_dm_odm->p_odm_sta_info[index] = (struct sta_info *)p_value; - - if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[index])) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->AssociatedMacId] = index; /*associated_mac_id are unique bttween different adapter*/ -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->aid] = index; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - p_dm_odm->platform2phydm_macid_table[index] = index; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->mac_id] = index; -#endif + dm->odm_sta_info[index] = (struct sta_info *)value; break; /* To remove the compiler warning, must add an empty default statement to handle the other values. */ default: @@ -1287,12 +1258,155 @@ odm_cmn_info_ptr_array_hook( void phydm_cmn_sta_info_hook( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 mac_id, struct cmn_sta_info *pcmn_sta_info ) { - p_dm_odm->p_phydm_sta_info[mac_id] = pcmn_sta_info; + dm->phydm_sta_info[mac_id] = pcmn_sta_info; + + if (is_sta_active(pcmn_sta_info)) + dm->phydm_macid_table[pcmn_sta_info->mac_id] = mac_id; +} + +void +phydm_macid2sta_idx_table( + struct dm_struct *dm, + u8 entry_idx, + struct cmn_sta_info *pcmn_sta_info +) +{ + if (is_sta_active(pcmn_sta_info)) + dm->phydm_macid_table[pcmn_sta_info->mac_id] = entry_idx; +} + +void +phydm_add_interrupt_mask_handler( + struct dm_struct *dm, + u8 interrupt_type +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + struct rtl8192cd_priv *priv = dm->priv; + + #if IS_EXIST_PCI || IS_EXIST_EMBEDDED + GET_HAL_INTERFACE(priv)->AddInterruptMaskHandler(priv, interrupt_type); + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#endif +} + +void +phydm_enable_rx_related_interrupt_handler( + struct dm_struct *dm +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + struct rtl8192cd_priv *priv = dm->priv; + + #if IS_EXIST_PCI || IS_EXIST_EMBEDDED + GET_HAL_INTERFACE(priv)->EnableRxRelatedInterruptHandler(priv); + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#endif +} + +#if 0 +boolean +phydm_get_txbf_en( + struct dm_struct *dm, + u16 mac_id, + u8 i +) +{ + boolean txbf_en = false; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && !defined(DM_ODM_CE_MAC80211) + + #ifdef CONFIG_BEAMFORMING + enum beamforming_cap beamform_cap; + void *adapter = dm->adapter; + #if (BEAMFORMING_SUPPORT == 1) + beamform_cap = + phydm_beamforming_get_entry_beam_cap_by_mac_id(dm, mac_id); + #else/*for drv beamforming*/ + beamform_cap = + beamforming_get_entry_beam_cap_by_mac_id(&adapter->mlmepriv, mac_id); + #endif + if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + txbf_en = true; + else + txbf_en = false; + #endif /*#ifdef CONFIG_BEAMFORMING*/ + +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) + + #if (BEAMFORMING_SUPPORT == 1) + u8 idx = 0xff; + boolean act_bfer = false; + BEAMFORMING_CAP beamform_cap = BEAMFORMING_CAP_NONE; + PRT_BEAMFORMING_ENTRY entry = NULL; + struct rtl8192cd_priv *priv = dm->priv; + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + + dm_bdc_table->num_txbfee_client = 0; + dm_bdc_table->num_txbfer_client = 0; + #endif + #endif + + #if (BEAMFORMING_SUPPORT == 1) + beamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, mac_id); + entry = Beamforming_GetEntryByMacId(priv, mac_id, &idx); + if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { + if (entry->Sounding_En) + txbf_en = true; + else + txbf_en = false; + act_bfer = true; + } + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*BDC*/ + if (act_bfer == true) { + dm_bdc_table->w_bfee_client[i] = true; /* AP act as BFer */ + dm_bdc_table->num_txbfee_client++; + } else + dm_bdc_table->w_bfee_client[i] = false; /* AP act as BFer */ + + if (beamform_cap & (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP_VHT_SU)) { + dm_bdc_table->w_bfer_client[i] = true; /* AP act as BFee */ + dm_bdc_table->num_txbfer_client++; + } else + dm_bdc_table->w_bfer_client[i] = false; /* AP act as BFer */ + + #endif + #endif + +#endif + return txbf_en; } +#endif +void +phydm_iqk_wait( + struct dm_struct *dm, + u32 timeout +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + PHYDM_DBG(dm, ODM_COMP_COMMON, "Not support for CE MAC80211 driver!\n"); +#else + void *adapter = dm->adapter; + + rtl8812_iqk_wait(adapter, timeout); +#endif +#endif +} diff --git a/hal/phydm/phydm_interface.h b/hal/phydm/phydm_interface.h index 05101ce..04ff7d4 100644 --- a/hal/phydm/phydm_interface.h +++ b/hal/phydm/phydm_interface.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,26 +8,82 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __ODM_INTERFACE_H__ #define __ODM_INTERFACE_H__ -#define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/ +#define INTERFACE_VERSION "1.2" /*2017.05.03 YuChen add phy param offload HAL MAC API*/ -/* - * =========== Constant/Structure/Enum/... Define - * */ +#define pdm_set_reg odm_set_bb_reg +/*=========== Constant/Structure/Enum/... Define*/ +enum phydm_h2c_cmd { + PHYDM_H2C_RA_MASK = 0x40, + PHYDM_H2C_TXBF = 0x41, + ODM_H2C_RSSI_REPORT = 0x42, + ODM_H2C_IQ_CALIBRATION = 0x45, + PHYDM_RA_MASK_ABOVE_3SS = 0x46, + ODM_H2C_RA_PARA_ADJUST = 0x47, + PHYDM_H2C_DYNAMIC_TX_PATH = 0x48, + PHYDM_H2C_FW_TRACE_EN = 0x49, + ODM_H2C_WIFI_CALIBRATION = 0x6d, + PHYDM_H2C_MU = 0x4a, + PHYDM_H2C_FW_GENERAL_INIT = 0x4c, + PHYDM_H2C_FW_CLM_MNTR = 0x4d, + ODM_MAX_H2CCMD +}; -/* - * =========== Macro Define - * */ +enum phydm_c2h_evt { + PHYDM_C2H_DBG = 0, + PHYDM_C2H_LB = 1, + PHYDM_C2H_XBF = 2, + PHYDM_C2H_TX_REPORT = 3, + PHYDM_C2H_INFO = 9, + PHYDM_C2H_BT_MP = 11, + PHYDM_C2H_RA_RPT = 12, + PHYDM_C2H_RA_PARA_RPT = 14, + PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, + PHYDM_C2H_IQK_FINISH = 17, /*0x11*/ + PHYDM_C2H_CLM_MONITOR = 0x2a, + PHYDM_C2H_DBG_CODE = 0xFE, + PHYDM_C2H_EXTEND = 0xFF, +}; + +enum phydm_extend_c2h_evt { + PHYDM_EXTEND_C2H_DBG_PRINT = 0 + +}; + +enum phydm_halmac_param { + PHYDM_HALMAC_CMD_MAC_W8 = 0, + PHYDM_HALMAC_CMD_MAC_W16 = 1, + PHYDM_HALMAC_CMD_MAC_W32 = 2, + PHYDM_HALMAC_CMD_BB_W8, + PHYDM_HALMAC_CMD_BB_W16, + PHYDM_HALMAC_CMD_BB_W32, + PHYDM_HALMAC_CMD_RF_W, + PHYDM_HALMAC_CMD_DELAY_US, + PHYDM_HALMAC_CMD_DELAY_MS, + PHYDM_HALMAC_CMD_END = 0XFF, +}; + +/*=========== Macro Define*/ #define _reg_all(_name) ODM_##_name #define _reg_ic(_name, _ic) ODM_##_name##_ic @@ -79,7 +135,7 @@ ODM_REG(DIG,_pdm_odm) */ /* _name: name of register or bit. - * Example: "ODM_REG(R_A_AGC_CORE1, p_dm_odm)" + * Example: "ODM_REG(R_A_AGC_CORE1, dm)" * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on support_ic_type. */ #ifdef __ECOS #define ODM_REG(_name, _pdm_odm) _rtk_cat(_name, _pdm_odm->support_ic_type, _reg) @@ -88,51 +144,6 @@ ODM_REG(DIG,_pdm_odm) #define ODM_REG(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _reg) #define ODM_BIT(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _bit) #endif -enum phydm_h2c_cmd { - PHYDM_H2C_TXBF = 0x41, - ODM_H2C_RSSI_REPORT = 0x42, - ODM_H2C_IQ_CALIBRATION = 0x45, - ODM_H2C_RA_PARA_ADJUST = 0x47, - PHYDM_H2C_DYNAMIC_TX_PATH = 0x48, - PHYDM_H2C_FW_TRACE_EN = 0x49, - ODM_H2C_WIFI_CALIBRATION = 0x6d, - PHYDM_H2C_MU = 0x4a, - PHYDM_H2C_FW_GENERAL_INIT = 0x4c, - ODM_MAX_H2CCMD -}; - -enum phydm_c2h_evt { - PHYDM_C2H_DBG = 0, - PHYDM_C2H_LB = 1, - PHYDM_C2H_XBF = 2, - PHYDM_C2H_TX_REPORT = 3, - PHYDM_C2H_INFO = 9, - PHYDM_C2H_BT_MP = 11, - PHYDM_C2H_RA_RPT = 12, - PHYDM_C2H_RA_PARA_RPT = 14, - PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, - PHYDM_C2H_IQK_FINISH = 17, /*0x11*/ - PHYDM_C2H_DBG_CODE = 0xFE, - PHYDM_C2H_EXTEND = 0xFF, -}; - -enum phydm_extend_c2h_evt { - PHYDM_EXTEND_C2H_DBG_PRINT = 0 - -}; - -enum phydm_halmac_param { - PHYDM_HALMAC_CMD_MAC_W8 = 0, - PHYDM_HALMAC_CMD_MAC_W16 = 1, - PHYDM_HALMAC_CMD_MAC_W32 = 2, - PHYDM_HALMAC_CMD_BB_W8, - PHYDM_HALMAC_CMD_BB_W16, - PHYDM_HALMAC_CMD_BB_W32, - PHYDM_HALMAC_CMD_RF_W, - PHYDM_HALMAC_CMD_DELAY_US, - PHYDM_HALMAC_CMD_DELAY_MS, - PHYDM_HALMAC_CMD_END = 0XFF, -}; /* * =========== Extern Variable ??? It should be forbidden. @@ -146,46 +157,46 @@ enum phydm_halmac_param { u8 odm_read_1byte( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr ); u16 odm_read_2byte( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr ); u32 odm_read_4byte( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr ); void odm_write_1byte( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u8 data ); void odm_write_2byte( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u16 data ); void odm_write_4byte( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u32 data ); void odm_set_mac_reg( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data @@ -193,14 +204,14 @@ odm_set_mac_reg( u32 odm_get_mac_reg( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u32 bit_mask ); void odm_set_bb_reg( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data @@ -208,15 +219,15 @@ odm_set_bb_reg( u32 odm_get_bb_reg( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 reg_addr, u32 bit_mask ); void odm_set_rf_reg( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e e_rf_path, + struct dm_struct *dm, + u8 e_rf_path, u32 reg_addr, u32 bit_mask, u32 data @@ -224,73 +235,63 @@ odm_set_rf_reg( u32 odm_get_rf_reg( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e e_rf_path, + struct dm_struct *dm, + u8 e_rf_path, u32 reg_addr, u32 bit_mask ); -enum hal_status -phydm_set_reg_by_fw( - struct PHY_DM_STRUCT *p_dm_odm, - enum phydm_halmac_param config_type, - u32 offset, - u32 data, - u32 mask, - enum odm_rf_radio_path_e e_rf_path, - u32 delay_time -); - /* * Memory Relative Function. * */ void odm_allocate_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void **p_ptr, + struct dm_struct *dm, + void **ptr, u32 length ); void odm_free_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void *p_ptr, + struct dm_struct *dm, + void *ptr, u32 length ); void odm_move_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void *p_dest, - void *p_src, + struct dm_struct *dm, + void *dest, + void *src, u32 length ); s32 odm_compare_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void *p_buf1, - void *p_buf2, + struct dm_struct *dm, + void *buf1, + void *buf2, u32 length ); -void odm_memory_set -(struct PHY_DM_STRUCT *p_dm_odm, - void *pbuf, - s8 value, - u32 length); +void odm_memory_set( + struct dm_struct *dm, + void *pbuf, + s8 value, + u32 length +); /* * ODM MISC-spin lock relative API. * */ void odm_acquire_spin_lock( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum rt_spinlock_type type ); void odm_release_spin_lock( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum rt_spinlock_type type ); @@ -300,10 +301,10 @@ odm_release_spin_lock( * */ void odm_initialize_work_item( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, PRT_WORK_ITEM p_rt_work_item, RT_WORKITEM_CALL_BACK rt_work_item_callback, - void *p_context, + void *context, const char *sz_id ); @@ -336,16 +337,9 @@ odm_is_work_item_scheduled( /* * ODM Timer relative API. * */ -void -odm_stall_execution( - u32 us_delay -); - void ODM_delay_ms(u32 ms); - - void ODM_delay_us(u32 us); @@ -357,62 +351,57 @@ ODM_sleep_us(u32 us); void odm_set_timer( - struct PHY_DM_STRUCT *p_dm_odm, - #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) - struct legacy_timer_emu *p_timer, - #else - struct timer_list *p_timer, - #endif + struct dm_struct *dm, + struct phydm_timer_list *timer, u32 ms_delay ); void odm_initialize_timer( - struct PHY_DM_STRUCT *p_dm_odm, - #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) - struct legacy_timer_emu *p_timer, - #else - struct timer_list *p_timer, - #endif + struct dm_struct *dm, + struct phydm_timer_list *timer, void *call_back_func, - void *p_context, + void *context, const char *sz_id ); void odm_cancel_timer( - struct PHY_DM_STRUCT *p_dm_odm, - #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) - struct legacy_timer_emu *p_timer - #else - struct timer_list *p_timer - #endif + struct dm_struct *dm, + struct phydm_timer_list *timer ); void odm_release_timer( - struct PHY_DM_STRUCT *p_dm_odm, - #if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) - struct legacy_timer_emu *p_timer - #else - struct timer_list *p_timer - #endif + struct dm_struct *dm, + struct phydm_timer_list *timer +); + +/*ODM FW relative API.*/ + + +enum hal_status +phydm_set_reg_by_fw( + struct dm_struct *dm, + enum phydm_halmac_param config_type, + u32 offset, + u32 data, + u32 mask, + enum rf_path e_rf_path, + u32 delay_time ); -/* - * ODM FW relative API. - * */ void odm_fill_h2c_cmd( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 element_id, u32 cmd_len, - u8 *p_cmd_buffer + u8 *cmd_buffer ); u8 phydm_c2H_content_parsing( - void *p_dm_void, + void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len, u8 *tmp_buf @@ -420,11 +409,11 @@ phydm_c2H_content_parsing( u64 odm_get_current_time( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u64 odm_get_progressing_time( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u64 start_time ); @@ -432,40 +421,40 @@ odm_get_progressing_time( void phydm_set_hw_reg_handler_interface ( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 reg_Name, u8 *val ); void phydm_get_hal_def_var_handler_interface ( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, enum _HAL_DEF_VARIABLE e_variable, - void *p_value + void *value ); #endif void odm_set_tx_power_index_by_rate_section ( - struct PHY_DM_STRUCT *p_dm_odm, - u8 RFPath, - u8 Channel, - u8 RateSection + struct dm_struct *dm, + enum rf_path path, + u8 channel, + u8 rate_section ); u8 odm_get_tx_power_index ( - struct PHY_DM_STRUCT *p_dm_odm, - u8 RFPath, + struct dm_struct *dm, + enum rf_path path, u8 tx_rate, u8 band_width, - u8 Channel + u8 channel ); u8 odm_efuse_one_byte_read( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u16 addr, u8 *data, boolean b_pseu_do_test @@ -473,7 +462,7 @@ odm_efuse_one_byte_read( void odm_efuse_logical_map_read( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 type, u16 offset, u32 *data @@ -481,25 +470,57 @@ odm_efuse_logical_map_read( enum hal_status odm_iq_calibrate_by_fw( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 clear, u8 segment ); void odm_cmn_info_ptr_array_hook( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_cmninfo_e cmn_info, + struct dm_struct *dm, + enum odm_cmninfo cmn_info, u16 index, - void *p_value + void *value ); void phydm_cmn_sta_info_hook( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 index, struct cmn_sta_info *pcmn_sta_info ); +void +phydm_macid2sta_idx_table( + struct dm_struct *dm, + u8 entry_idx, + struct cmn_sta_info *pcmn_sta_info +); + +void +phydm_add_interrupt_mask_handler( + struct dm_struct *dm, + u8 interrupt_type +); + +void +phydm_enable_rx_related_interrupt_handler( + struct dm_struct *dm +); + +#if 0 +boolean +phydm_get_txbf_en( + struct dm_struct *dm, + u16 mac_id, + u8 i +); +#endif + +void +phydm_iqk_wait( + struct dm_struct *dm, + u32 timeout +); #endif /* __ODM_INTERFACE_H__ */ diff --git a/hal/phydm/phydm_iqk.h b/hal/phydm/phydm_iqk.h deleted file mode 100644 index 3b668bc..0000000 --- a/hal/phydm/phydm_iqk.h +++ /dev/null @@ -1,50 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMIQK_H__ -#define __PHYDMIQK_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define LOK_delay 1 -#define WBIQK_delay 10 -#define TX_IQK 0 -#define RX_IQK 1 -#define NUM 4 -/*---------------------------End Define Parameters-------------------------------*/ - -typedef struct _IQK_INFORMATION { - BOOLEAN LOK_fail[NUM]; - BOOLEAN IQK_fail[2][NUM]; - u4Byte IQC_Matrix[2][NUM]; - u1Byte IQKtimes; - u4Byte RFReg18; - - u4Byte IQK_Channel[2]; - BOOLEAN IQK_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */ - u4Byte IQK_CFIR_real[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ - u4Byte IQK_CFIR_imag[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ - u1Byte retry_count[2][4][2]; /* channel / path / TRX(TX:0, RX:1) */ - u4Byte LOK_IDAC[2][4]; /*channel / path*/ - u4Byte RXIQK_AGC[2][4]; /*channel / path*/ - - -} IQK_INFO, *PIQK_INFO; - -#endif diff --git a/hal/phydm/phydm_kfree.c b/hal/phydm/phydm_kfree.c deleted file mode 100644 index 071064a..0000000 --- a/hal/phydm/phydm_kfree.c +++ /dev/null @@ -1,191 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -/*============================================================*/ -/*include files*/ -/*============================================================*/ -#include "mp_precomp.h" -#include "phydm_precomp.h" - - -/* Add for KFree Feature Requested by RF David.*/ -/*This is a phydm API*/ - -VOID -phydm_SetKfreeToRF_8814A( - IN PVOID pDM_VOID, - IN u1Byte eRFPath, - IN u1Byte Data - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - BOOLEAN bOdd; - - if ((Data%2) != 0) { /*odd -> positive*/ - Data = Data - 1; - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT19, 1); - bOdd = TRUE; - } else { /*even -> negative*/ - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT19, 0); - bOdd = FALSE; - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", bOdd)); - switch (Data) { - case 0: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 0); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 0; - break; - case 2: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 0); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 0; - break; - case 4: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 1); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 1; - break; - case 6: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 1); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 1; - break; - case 8: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 2); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 2; - break; - case 10: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 2); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 2; - break; - case 12: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 3); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 3; - break; - case 14: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 3); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 3; - break; - case 16: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 4); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 4; - break; - case 18: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 4); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 4; - break; - case 20: - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0); - ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 5); - pRFCalibrateInfo->KfreeOffset[eRFPath] = 5; - break; - - default: - break; - } - - if (bOdd == FALSE) { - /*that means Kfree offset is negative, we need to record it.*/ - pRFCalibrateInfo->KfreeOffset[eRFPath] = (-1)*pRFCalibrateInfo->KfreeOffset[eRFPath]; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): KfreeOffset = %d\n", pRFCalibrateInfo->KfreeOffset[eRFPath])); - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): KfreeOffset = %d\n", pRFCalibrateInfo->KfreeOffset[eRFPath])); - -} - - -VOID -phydm_SetKfreeToRF( - IN PVOID pDM_VOID, - IN u1Byte eRFPath, - IN u1Byte Data - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - if (pDM_Odm->SupportICType & ODM_RTL8814A) - phydm_SetKfreeToRF_8814A(pDM_Odm, eRFPath, Data); -} - -VOID -phydm_ConfigKFree( - IN PVOID pDM_VOID, - IN u1Byte channelToSW, - IN pu1Byte kfreeTable - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u1Byte rfpath = 0, maxRFpath = 0; - u1Byte channelIdx = 0; - - if (pDM_Odm->SupportICType & ODM_RTL8814A) - maxRFpath = 4; /*0~3*/ - else if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B)) - maxRFpath = 2; /*0~1*/ - else - maxRFpath = 1; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("===>phy_ConfigKFree8814A()\n")); - - if (pRFCalibrateInfo->RegRfKFreeEnable == 2) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RegRfKFreeEnable == 2, Disable\n")); - return; - } else if (pRFCalibrateInfo->RegRfKFreeEnable == 1 || pRFCalibrateInfo->RegRfKFreeEnable == 0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RegRfKFreeEnable == TRUE\n")); - /*Make sure the targetval is defined*/ - if (((pRFCalibrateInfo->RegRfKFreeEnable == 1) && (kfreeTable[0] != 0xFF)) || (pRFCalibrateInfo->RfKFreeEnable == TRUE)) { - /*if kfreeTable[0] == 0xff, means no Kfree*/ - if (*pDM_Odm->pBandType == ODM_BAND_2_4G) { - if (channelToSW <= 14 && channelToSW >= 1) - channelIdx = PHYDM_2G; - } else if (*pDM_Odm->pBandType == ODM_BAND_5G) { - if (channelToSW >= 36 && channelToSW <= 48) - channelIdx = PHYDM_5GLB1; - if (channelToSW >= 52 && channelToSW <= 64) - channelIdx = PHYDM_5GLB2; - if (channelToSW >= 100 && channelToSW <= 120) - channelIdx = PHYDM_5GMB1; - if (channelToSW >= 124 && channelToSW <= 144) - channelIdx = PHYDM_5GMB2; - if (channelToSW >= 149 && channelToSW <= 177) - channelIdx = PHYDM_5GHB; - } - - for (rfpath = ODM_RF_PATH_A; rfpath < maxRFpath; rfpath++) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phydm_kfree(): PATH_%d: %#x\n", rfpath, kfreeTable[channelIdx*maxRFpath + rfpath])); - phydm_SetKfreeToRF(pDM_Odm, rfpath, kfreeTable[channelIdx*maxRFpath + rfpath]); - } - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): targetval not defined, Don't execute KFree Process.\n")); - return; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("<===phy_ConfigKFree8814A()\n")); -} - diff --git a/hal/phydm/phydm_kfree.h b/hal/phydm/phydm_kfree.h deleted file mode 100644 index d2c75ad..0000000 --- a/hal/phydm/phydm_kfree.h +++ /dev/null @@ -1,45 +0,0 @@ - -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMKFREE_H__ -#define __PHYDKFREE_H__ - -#define KFREE_VERSION "1.0" - -typedef enum tag_phydm_kfree_channeltosw { - PHYDM_2G = 0, - PHYDM_5GLB1 = 1, - PHYDM_5GLB2 = 2, - PHYDM_5GMB1 = 3, - PHYDM_5GMB2 = 4, - PHYDM_5GHB = 5, -} PHYDM_KFREE_CHANNELTOSW; - - -VOID -phydm_ConfigKFree( - IN PVOID pDM_VOID, - IN u1Byte channelToSW, - IN pu1Byte kfreeTable -); - - -#endif diff --git a/hal/phydm/phydm_noisemonitor.c b/hal/phydm/phydm_noisemonitor.c index 8a34ba1..1034167 100644 --- a/hal/phydm/phydm_noisemonitor.c +++ b/hal/phydm/phydm_noisemonitor.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -18,7 +28,6 @@ * ************************************************************ */ #include "mp_precomp.h" #include "phydm_precomp.h" -#include "phydm_noisemonitor.h" /* ************************************************* * This function is for inband noise test utility only @@ -30,18 +39,13 @@ * * ************************************************* */ -#define VALID_MIN -35 -#define VALID_MAX 10 #define VALID_CNT 5 -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) - void phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path) { u8 rf_path; - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { - /* printk("%s PATH_%d - sum = %d, VALID_CNT = %d\n",__FUNCTION__,rf_path,noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]); */ + for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) { if (noise_data->valid_cnt[rf_path]) noise_data->sum[rf_path] /= noise_data->valid_cnt[rf_path]; else @@ -49,7 +53,7 @@ void phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path) } } -s16 odm_inband_noise_monitor_n_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_dig, u8 igi_value, u32 max_time) +s16 odm_inband_noise_monitor_n_series(struct dm_struct *dm, u8 is_pause_dig, u8 igi_value, u32 max_time) { u32 tmp4b; u8 max_rf_path = 0, rf_path; @@ -57,161 +61,228 @@ s16 odm_inband_noise_monitor_n_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_paus struct noise_level noise_data; u64 start = 0, func_start = 0, func_end = 0; - func_start = odm_get_current_time(p_dm_odm); - p_dm_odm->noise_level.noise_all = 0; + func_start = odm_get_current_time(dm); + dm->noise_level.noise_all = 0; - if ((p_dm_odm->rf_type == ODM_1T2R) || (p_dm_odm->rf_type == ODM_2T2R)) + if ((dm->rf_type == RF_1T2R) || (dm->rf_type == RF_2T2R)) max_rf_path = 2; else max_rf_path = 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() ==>\n")); - - odm_memory_set(p_dm_odm, &noise_data, 0, sizeof(struct noise_level)); + PHYDM_DBG(dm, DBG_ENV_MNTR, "odm_DebugControlInbandNoise_Nseries() ==>\n"); - /* */ + odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level)); /* step 1. Disable DIG && Set initial gain. */ - /* */ if (is_pause_dig) - odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value); - /* */ - /* step 2. Disable all power save for read registers */ - /* */ - /* dcmd_DebugControlPowerSave(p_adapter, PSDisable); */ + odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value); - /* */ /* step 3. Get noise power level */ - /* */ - start = odm_get_current_time(p_dm_odm); + start = odm_get_current_time(dm); while (1) { - /* Stop updating idle time pwer report (for driver read) */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1); + odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1); /* Read Noise Floor Report */ - tmp4b = odm_get_bb_reg(p_dm_odm, 0x8f8, MASKDWORD); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b)); - - /* odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0, TestInitialGain); */ - /* if(max_rf_path == 2) */ - /* odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0, TestInitialGain); */ + tmp4b = odm_get_bb_reg(dm, 0x8f8, MASKDWORD); /* update idle time pwer report per 5us */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0); + odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0); - noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b & 0xff); - noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8); + ODM_delay_us(5); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n", - noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B])); + noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff); + noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8); - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { + for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) { noise_data.sval[rf_path] = (s8)noise_data.value[rf_path]; noise_data.sval[rf_path] /= 2; } + for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) { + if (noise_data.valid_cnt[rf_path] >= VALID_CNT) + continue; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("sval_a = %d, sval_b = %d\n", - noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B])); - /* ODM_delay_ms(10); */ - /* ODM_sleep_ms(10); */ + noise_data.valid_cnt[rf_path]++; + noise_data.sum[rf_path] += noise_data.sval[rf_path]; + PHYDM_DBG(dm, DBG_ENV_MNTR, "rf_path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path]); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", noise_data.sum[rf_path]); + if (noise_data.valid_cnt[rf_path] == VALID_CNT) + valid_done++; + } + if ((valid_done == max_rf_path) || (odm_get_progressing_time(dm, start) > max_time)) { + phydm_set_noise_data_sum(&noise_data, max_rf_path); + break; + } + } + reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0); + reg_c50 &= ~BIT(7); + dm->noise_level.noise[RF_PATH_A] = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]); + dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A]; - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { - if (!(noise_data.valid_cnt[rf_path] < VALID_CNT) || !(noise_data.sval[rf_path] < VALID_MAX && noise_data.sval[rf_path] >= VALID_MIN)) { + if (max_rf_path == 2) { + reg_c58 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0); + reg_c58 &= ~BIT(7); + dm->noise_level.noise[RF_PATH_B] = (s8)(-110 + reg_c58 + noise_data.sum[RF_PATH_B]); + dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B]; + } + dm->noise_level.noise_all /= max_rf_path; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "noise_a = %d, noise_b = %d, noise_all = %d\n", + dm->noise_level.noise[RF_PATH_A], dm->noise_level.noise[RF_PATH_B], + dm->noise_level.noise_all); + + /* step 4. Recover the Dig */ + if (is_pause_dig) + odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value); + func_end = odm_get_progressing_time(dm, func_start); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n"); + return dm->noise_level.noise_all; + +} + + +s16 +phydm_idle_noise_measurement_ac( + struct dm_struct *dm, + u8 is_pause_dig, + u8 igi_value, + u32 max_time + ) +{ + u32 tmp4b; + u8 max_rf_path = 0, rf_path; + u8 reg_c50, reg_e50, valid_done = 0; + u64 start = 0, func_start = 0, func_end = 0; + struct noise_level noise_data; + + func_start = odm_get_current_time(dm); + dm->noise_level.noise_all = 0; + + if ((dm->rf_type == RF_1T2R) || (dm->rf_type == RF_2T2R)) + max_rf_path = 2; + else + max_rf_path = 1; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "phydm_idle_noise_measurement_ac==>\n"); + + odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level)); + + /*Step 1. Disable DIG && Set initial gain.*/ + + if (is_pause_dig) + odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value); + + /*Step 2. Get noise power level*/ + start = odm_get_current_time(dm); + + while (1) { + /*Stop updating idle time pwer report (for driver read)*/ + odm_set_bb_reg(dm, 0x9e4, BIT(30), 0x1); + + /*Read Noise Floor Report*/ + tmp4b = odm_get_bb_reg(dm, 0xff0, MASKDWORD); + + /*update idle time pwer report per 5us*/ + odm_set_bb_reg(dm, 0x9e4, BIT(30), 0x0); + + ODM_delay_us(5); + + noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff); + noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8); + + for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) { + noise_data.sval[rf_path] = (s8)noise_data.value[rf_path]; + noise_data.sval[rf_path] = noise_data.sval[rf_path] >> 1; + } + + for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) { + if (noise_data.valid_cnt[rf_path] >= VALID_CNT) continue; - } noise_data.valid_cnt[rf_path]++; noise_data.sum[rf_path] += noise_data.sval[rf_path]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("rf_path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", noise_data.sum[rf_path])); - if (noise_data.valid_cnt[rf_path] == VALID_CNT) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path]); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d\n", noise_data.sum[rf_path]); + if (noise_data.valid_cnt[rf_path] == VALID_CNT) valid_done++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, rf_path:%d,sum = %d\n", rf_path, noise_data.sum[rf_path])); - } - } - /* printk("####### valid_done:%d #############\n",valid_done); */ - if ((valid_done == max_rf_path) || (odm_get_progressing_time(p_dm_odm, start) > max_time)) { + if ((valid_done == max_rf_path) || (odm_get_progressing_time(dm, start) > max_time)) { phydm_set_noise_data_sum(&noise_data, max_rf_path); break; } } - reg_c50 = (u8)odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0); + reg_c50 = (u8)odm_get_bb_reg(dm, 0xc50, MASKBYTE0); reg_c50 &= ~BIT(7); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", REG_OFDM_0_XA_AGC_CORE1, reg_c50, reg_c50)); - p_dm_odm->noise_level.noise[ODM_RF_PATH_A] = (s8)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]); - p_dm_odm->noise_level.noise_all += p_dm_odm->noise_level.noise[ODM_RF_PATH_A]; + dm->noise_level.noise[RF_PATH_A] = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]); + dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A]; if (max_rf_path == 2) { - reg_c58 = (u8)odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0); - reg_c58 &= ~BIT(7); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", REG_OFDM_0_XB_AGC_CORE1, reg_c58, reg_c58)); - p_dm_odm->noise_level.noise[ODM_RF_PATH_B] = (s8)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]); - p_dm_odm->noise_level.noise_all += p_dm_odm->noise_level.noise[ODM_RF_PATH_B]; + reg_e50 = (u8)odm_get_bb_reg(dm, 0xe50, MASKBYTE0); + reg_e50 &= ~BIT(7); + dm->noise_level.noise[RF_PATH_B] = (s8)(-110 + reg_e50 + noise_data.sum[RF_PATH_B]); + dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B]; } - p_dm_odm->noise_level.noise_all /= max_rf_path; + dm->noise_level.noise_all /= max_rf_path; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise_a = %d, noise_b = %d\n", - p_dm_odm->noise_level.noise[ODM_RF_PATH_A], - p_dm_odm->noise_level.noise[ODM_RF_PATH_B])); + PHYDM_DBG(dm, DBG_ENV_MNTR, "noise_a = %d, noise_b = %d, noise_all = %d\n", + dm->noise_level.noise[RF_PATH_A], dm->noise_level.noise[RF_PATH_B], + dm->noise_level.noise_all); - /* */ - /* step 4. Recover the Dig */ - /* */ + /*Step 3. Recover the Dig*/ if (is_pause_dig) - odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value); - func_end = odm_get_progressing_time(p_dm_odm, func_start) ; + odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value); + func_end = odm_get_progressing_time(dm, func_start); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n")); - return p_dm_odm->noise_level.noise_all; + PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n"); + return dm->noise_level.noise_all; } + s16 -odm_inband_noise_monitor_ac_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_dig, u8 igi_value, u32 max_time - ) +odm_inband_noise_monitor_ac_series( + struct dm_struct *dm, + u8 is_pause_dig, + u8 igi_value, + u32 max_time + ) { s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/ - s32 value32, pwdb_A = 0, sval, noise, sum; + s32 value32, pwdb_A = 0, sval, noise, sum = 0; boolean pd_flag; - u8 valid_cnt; + u8 valid_cnt = 0; u64 start = 0, func_start = 0, func_end = 0; + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) + return phydm_idle_noise_measurement_ac(dm, is_pause_dig, igi_value, max_time); - if (!(p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A))) + if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A))) return 0; - func_start = odm_get_current_time(p_dm_odm); - p_dm_odm->noise_level.noise_all = 0; + func_start = odm_get_current_time(dm); + dm->noise_level.noise_all = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_inband_noise_monitor_ac_series() ==>\n")); + PHYDM_DBG(dm, DBG_ENV_MNTR, "odm_inband_noise_monitor_ac_series() ==>\n"); /* step 1. Disable DIG && Set initial gain. */ if (is_pause_dig) - odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value); - - /* step 2. Disable all power save for read registers */ - /*dcmd_DebugControlPowerSave(p_adapter, PSDisable); */ + odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value); /* step 3. Get noise power level */ - start = odm_get_current_time(p_dm_odm); - - /* reset counters */ - sum = 0; - valid_cnt = 0; + start = odm_get_current_time(dm); /* step 3. Get noise power level */ while (1) { /*Set IGI=0x1C */ - odm_write_dig(p_dm_odm, 0x1C); + odm_write_dig(dm, 0x1C); /*stop CK320&CK88 */ - odm_set_bb_reg(p_dm_odm, 0x8B4, BIT(6), 1); + odm_set_bb_reg(dm, 0x8B4, BIT(6), 1); /*Read path-A */ - odm_set_bb_reg(p_dm_odm, 0x8FC, MASKDWORD, 0x200); /*set debug port*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xFA0, MASKDWORD); /*read debug port*/ + odm_set_bb_reg(dm, 0x8FC, MASKDWORD, 0x200); /*set debug port*/ + value32 = odm_get_bb_reg(dm, 0xFA0, MASKDWORD); /*read debug port*/ rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/ rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/ @@ -226,20 +297,20 @@ odm_inband_noise_monitor_ac_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_d pwdb_A = odm_pwdb_conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF)); + PHYDM_DBG(dm, DBG_ENV_MNTR, "pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF); } /*Start CK320&CK88*/ - odm_set_bb_reg(p_dm_odm, 0x8B4, BIT(6), 0); + odm_set_bb_reg(dm, 0x8B4, BIT(6), 0); /*BB Reset*/ - odm_write_1byte(p_dm_odm, 0x02, odm_read_1byte(p_dm_odm, 0x02) & (~BIT(0))); - odm_write_1byte(p_dm_odm, 0x02, odm_read_1byte(p_dm_odm, 0x02) | BIT(0)); + odm_write_1byte(dm, 0x02, odm_read_1byte(dm, 0x02) & (~BIT(0))); + odm_write_1byte(dm, 0x02, odm_read_1byte(dm, 0x02) | BIT(0)); /*PMAC Reset*/ - odm_write_1byte(p_dm_odm, 0xB03, odm_read_1byte(p_dm_odm, 0xB03) & (~BIT(0))); - odm_write_1byte(p_dm_odm, 0xB03, odm_read_1byte(p_dm_odm, 0xB03) | BIT(0)); + odm_write_1byte(dm, 0xB03, odm_read_1byte(dm, 0xB03) & (~BIT(0))); + odm_write_1byte(dm, 0xB03, odm_read_1byte(dm, 0xB03) | BIT(0)); /*CCK Reset*/ - if (odm_read_1byte(p_dm_odm, 0x80B) & BIT(4)) { - odm_write_1byte(p_dm_odm, 0x80B, odm_read_1byte(p_dm_odm, 0x80B) & (~BIT(4))); - odm_write_1byte(p_dm_odm, 0x80B, odm_read_1byte(p_dm_odm, 0x80B) | BIT(4)); + if (odm_read_1byte(dm, 0x80B) & BIT(4)) { + odm_write_1byte(dm, 0x80B, odm_read_1byte(dm, 0x80B) & (~BIT(4))); + odm_write_1byte(dm, 0x80B, odm_read_1byte(dm, 0x80B) | BIT(4)); } sval = pwdb_A; @@ -247,11 +318,11 @@ odm_inband_noise_monitor_ac_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_d if ((sval < 0 && sval >= -27) && (valid_cnt < VALID_CNT)){ valid_cnt++; sum += sval; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Valid sval = %d\n", sval)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", sum)); - if ((valid_cnt >= VALID_CNT) || (odm_get_progressing_time(p_dm_odm, start) > max_time)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Valid sval = %d\n", sval); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", sum); + if ((valid_cnt >= VALID_CNT) || (odm_get_progressing_time(dm, start) > max_time)) { sum /= VALID_CNT; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, sum = %d\n", sum)); + PHYDM_DBG(dm, DBG_ENV_MNTR, "After divided, sum = %d\n", sum); break; } } @@ -263,31 +334,94 @@ odm_inband_noise_monitor_ac_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_d /*Offset*/ noise = noise - 3; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise = %d\n", noise)); - p_dm_odm->noise_level.noise_all = (s16)noise; + PHYDM_DBG(dm, DBG_ENV_MNTR, "noise = %d\n", noise); + dm->noise_level.noise_all = (s16)noise; /* step 4. Recover the Dig*/ if (is_pause_dig) - odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value); + odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value); - func_end = odm_get_progressing_time(p_dm_odm, func_start); + func_end = odm_get_progressing_time(dm, func_start); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_inband_noise_monitor_ac_series() <==\n")); + PHYDM_DBG(dm, DBG_ENV_MNTR, "odm_inband_noise_monitor_ac_series() <==\n"); - return p_dm_odm->noise_level.noise_all; + return dm->noise_level.noise_all; } s16 -odm_inband_noise_monitor(void *p_dm_void, u8 is_pause_dig, u8 igi_value, u32 max_time) +odm_inband_noise_monitor( + void *dm_void, + u8 is_pause_dig, + u8 igi_value, + u32 max_time + ) { + struct dm_struct *dm = (struct dm_struct *)dm_void; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - return odm_inband_noise_monitor_ac_series(p_dm_odm, is_pause_dig, igi_value, max_time); + igi_value = 0x32; /*since HW ability is about +15~-35, we fix IGI = -60 for maximum coverage*/ + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + return odm_inband_noise_monitor_ac_series(dm, is_pause_dig, igi_value, max_time); else - return odm_inband_noise_monitor_n_series(p_dm_odm, is_pause_dig, igi_value, max_time); + return odm_inband_noise_monitor_n_series(dm, is_pause_dig, igi_value, max_time); } +void +phydm_noisy_detection( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 total_fa_cnt, total_cca_cnt; + u32 score = 0, i, score_smooth; + + total_cca_cnt = dm->false_alm_cnt.cnt_cca_all; + total_fa_cnt = dm->false_alm_cnt.cnt_all; + +#if 0 + if (total_fa_cnt * 16 >= total_cca_cnt * 14) /* 87.5 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /* 75 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /* 56.25 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /* 50 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /* 43.75 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /* 37.5 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /* 31.25% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /* 25% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /* 18.75% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /* 12.5% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /* 6.25% */ + ; #endif + for (i = 0; i <= 16; i++) { + if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) { + score = 16 - i; + break; + } + } + + /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */ + dm->noisy_decision_smooth = (dm->noisy_decision_smooth >> 1) + (score << 2); + + /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */ + score_smooth = (total_cca_cnt >= 300) ? ((dm->noisy_decision_smooth + 3) >> 3) : 0; + + dm->noisy_decision = (score_smooth >= 3) ? 1 : 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[NoisyDetection] CCA_cnt=%d,FA_cnt=%d, noisy_dec_smooth=%d, score=%d, score_smooth=%d, noisy_dec=%d\n", + total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score, score_smooth, dm->noisy_decision); + +} + diff --git a/hal/phydm/phydm_noisemonitor.h b/hal/phydm/phydm_noisemonitor.h index 05b2e50..d7101ad 100644 --- a/hal/phydm/phydm_noisemonitor.h +++ b/hal/phydm/phydm_noisemonitor.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,35 +8,48 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __ODMNOISEMONITOR_H__ #define __ODMNOISEMONITOR_H__ #define ODM_MAX_CHANNEL_NUM 38/* 14+24 */ struct noise_level { - /* u8 value_a, value_b; */ - u8 value[MAX_RF_PATH]; - /* s8 sval_a, sval_b; */ - s8 sval[MAX_RF_PATH]; - - /* s32 noise_a=0, noise_b=0,sum_a=0, sum_b=0; */ - /* s32 noise[ODM_RF_PATH_MAX]; */ - s32 sum[MAX_RF_PATH]; - /* u8 valid_cnt_a=0, valid_cnt_b=0, */ - u8 valid[MAX_RF_PATH]; - u8 valid_cnt[MAX_RF_PATH]; - + u8 value[PHYDM_MAX_RF_PATH]; + s8 sval[PHYDM_MAX_RF_PATH]; + s32 sum[PHYDM_MAX_RF_PATH]; + u8 valid[PHYDM_MAX_RF_PATH]; + u8 valid_cnt[PHYDM_MAX_RF_PATH]; }; -struct _ODM_NOISE_MONITOR_ { - s8 noise[MAX_RF_PATH]; +struct odm_noise_monitor { + s8 noise[PHYDM_MAX_RF_PATH]; s16 noise_all; }; -s16 odm_inband_noise_monitor(void *p_dm_void, u8 is_pause_dig, u8 igi_value, u32 max_time); +s16 odm_inband_noise_monitor( + void *dm_void, + u8 is_pause_dig, + u8 igi_value, + u32 max_time +); + +void +phydm_noisy_detection( + void *dm_void +); #endif diff --git a/hal/phydm/phydm_pathdiv.c b/hal/phydm/phydm_pathdiv.c index 9a2ada6..5550ab4 100644 --- a/hal/phydm/phydm_pathdiv.c +++ b/hal/phydm/phydm_pathdiv.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -24,211 +34,211 @@ void phydm_dtp_fix_tx_path( - void *p_dm_void, + void *dm_void, u8 path ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; u8 i, num_enable_path = 0; - if (path == p_dm_path_div->pre_tx_path) + if (path == dm_path_div->pre_tx_path) return; else - p_dm_path_div->pre_tx_path = path; + dm_path_div->pre_tx_path = path; - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(18) | BIT(19), 3); + odm_set_bb_reg(dm, 0x93c, BIT(18) | BIT(19), 3); for (i = 0; i < 4; i++) { if (path & BIT(i)) num_enable_path++; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" number of trun-on path : (( %d ))\n", num_enable_path)); + PHYDM_DBG(dm, DBG_PATH_DIV, " number of turn-on path : (( %d ))\n", num_enable_path); if (num_enable_path == 1) { - odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path); - - if (path == PHYDM_A) { /* 1-1 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A ))\n")); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - } else if (path == PHYDM_B) { /* 1-2 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B ))\n")); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0); - } else if (path == PHYDM_C) { /* 1-3 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C ))\n")); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 0); - - } else if (path == PHYDM_D) { /* 1-4 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( D ))\n")); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 0); + odm_set_bb_reg(dm, 0x93c, 0xf00000, path); + + if (path == BB_PATH_A) { /* 1-1 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A ))\n"); + odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0); + } else if (path == BB_PATH_B) { /* 1-2 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B ))\n"); + odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 0); + } else if (path == BB_PATH_C) { /* 1-3 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( C ))\n"); + odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 0); + + } else if (path == BB_PATH_D) { /* 1-4 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( D ))\n"); + odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 0); } } else if (num_enable_path == 2) { - odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path); - odm_set_bb_reg(p_dm_odm, 0x940, 0xf0, path); + odm_set_bb_reg(dm, 0x93c, 0xf00000, path); + odm_set_bb_reg(dm, 0x940, 0xf0, path); - if (path == PHYDM_AB) { /* 2-1 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B ))\n")); + if (path == (BB_PATH_AB)) { /* 2-1 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A B ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1); + odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 1); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1); - } else if (path == PHYDM_AC) { /* 2-2 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C ))\n")); + odm_set_bb_reg(dm, 0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, 0x940, BIT(11) | BIT(10), 1); + } else if (path == BB_PATH_AC) { /* 2-2 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A C ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1); + odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 1); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1); - } else if (path == PHYDM_AD) { /* 2-3 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A D ))\n")); + odm_set_bb_reg(dm, 0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, 0x940, BIT(13) | BIT(12), 1); + } else if (path == BB_PATH_AD) { /* 2-3 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A D ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1); + odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 1); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1); - } else if (path == PHYDM_BC) { /* 2-4 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C ))\n")); + odm_set_bb_reg(dm, 0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, 0x940, BIT(15) | BIT(14), 1); + } else if (path == BB_PATH_BC) { /* 2-4 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B C ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1); + odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 0); + odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 1); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1); - } else if (path == PHYDM_BD) { /* 2-5 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B D ))\n")); + odm_set_bb_reg(dm, 0x940, BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, 0x940, BIT(13) | BIT(12), 1); + } else if (path == BB_PATH_BD) { /* 2-5 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B D ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1); + odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 0); + odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 1); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1); - } else if (path == PHYDM_CD) { /* 2-6 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C D ))\n")); + odm_set_bb_reg(dm, 0x940, BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, 0x940, BIT(15) | BIT(14), 1); + } else if (path == BB_PATH_CD) { /* 2-6 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( C D ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1); + odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 0); + odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 1); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1); + odm_set_bb_reg(dm, 0x940, BIT(13) | BIT(12), 0); + odm_set_bb_reg(dm, 0x940, BIT(15) | BIT(14), 1); } } else if (num_enable_path == 3) { - odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path); - odm_set_bb_reg(p_dm_odm, 0x940, 0xf0, path); - odm_set_bb_reg(p_dm_odm, 0x940, 0xf0000, path); + odm_set_bb_reg(dm, 0x93c, 0xf00000, path); + odm_set_bb_reg(dm, 0x940, 0xf0, path); + odm_set_bb_reg(dm, 0x940, 0xf0000, path); - if (path == PHYDM_ABC) { /* 3-1 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B C))\n")); + if (path == BB_PATH_ABC) { /* 3-1 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A B C))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 2); + odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 1); + odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 2); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 2); + odm_set_bb_reg(dm, 0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, 0x940, BIT(11) | BIT(10), 1); + odm_set_bb_reg(dm, 0x940, BIT(13) | BIT(12), 2); /* set for 3ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 2); - } else if (path == PHYDM_ABD) { /* 3-2 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B D ))\n")); + odm_set_bb_reg(dm, 0x940, BIT(21) | BIT(20), 0); + odm_set_bb_reg(dm, 0x940, BIT(23) | BIT(22), 1); + odm_set_bb_reg(dm, 0x940, BIT(25) | BIT(24), 2); + } else if (path == BB_PATH_ABD) { /* 3-2 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A B D ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2); + odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 1); + odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 2); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2); + odm_set_bb_reg(dm, 0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, 0x940, BIT(11) | BIT(10), 1); + odm_set_bb_reg(dm, 0x940, BIT(15) | BIT(14), 2); /* set for 3ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2); + odm_set_bb_reg(dm, 0x940, BIT(21) | BIT(20), 0); + odm_set_bb_reg(dm, 0x940, BIT(23) | BIT(22), 1); + odm_set_bb_reg(dm, 0x940, BIT(27) | BIT(26), 2); - } else if (path == PHYDM_ACD) { /* 3-3 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C D ))\n")); + } else if (path == BB_PATH_ACD) { /* 3-3 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A C D ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2); + odm_set_bb_reg(dm, 0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 1); + odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 2); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2); + odm_set_bb_reg(dm, 0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, 0x940, BIT(13) | BIT(12), 1); + odm_set_bb_reg(dm, 0x940, BIT(15) | BIT(14), 2); /* set for 3ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2); - } else if (path == PHYDM_BCD) { /* 3-4 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C D))\n")); + odm_set_bb_reg(dm, 0x940, BIT(21) | BIT(20), 0); + odm_set_bb_reg(dm, 0x940, BIT(25) | BIT(24), 1); + odm_set_bb_reg(dm, 0x940, BIT(27) | BIT(26), 2); + } else if (path == BB_PATH_BCD) { /* 3-4 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B C D))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2); + odm_set_bb_reg(dm, 0x93c, BIT(27) | BIT(26), 0); + odm_set_bb_reg(dm, 0x93c, BIT(29) | BIT(28), 1); + odm_set_bb_reg(dm, 0x93c, BIT(31) | BIT(30), 2); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2); + odm_set_bb_reg(dm, 0x940, BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, 0x940, BIT(13) | BIT(12), 1); + odm_set_bb_reg(dm, 0x940, BIT(15) | BIT(14), 2); /* set for 3ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2); + odm_set_bb_reg(dm, 0x940, BIT(23) | BIT(22), 0); + odm_set_bb_reg(dm, 0x940, BIT(25) | BIT(24), 1); + odm_set_bb_reg(dm, 0x940, BIT(27) | BIT(26), 2); } } else if (num_enable_path == 4) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path ((A B C D))\n")); + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path ((A B C D))\n"); } void phydm_find_default_path( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; u32 rssi_avg_a = 0, rssi_avg_b = 0, rssi_avg_c = 0, rssi_avg_d = 0, rssi_avg_bcd = 0; u32 rssi_total_a = 0, rssi_total_b = 0, rssi_total_c = 0, rssi_total_d = 0; /* 2 Default path Selection By RSSI */ - rssi_avg_a = (p_dm_path_div->path_a_cnt_all > 0) ? (p_dm_path_div->path_a_sum_all / p_dm_path_div->path_a_cnt_all) : 0 ; - rssi_avg_b = (p_dm_path_div->path_b_cnt_all > 0) ? (p_dm_path_div->path_b_sum_all / p_dm_path_div->path_b_cnt_all) : 0 ; - rssi_avg_c = (p_dm_path_div->path_c_cnt_all > 0) ? (p_dm_path_div->path_c_sum_all / p_dm_path_div->path_c_cnt_all) : 0 ; - rssi_avg_d = (p_dm_path_div->path_d_cnt_all > 0) ? (p_dm_path_div->path_d_sum_all / p_dm_path_div->path_d_cnt_all) : 0 ; + rssi_avg_a = (dm_path_div->path_a_cnt_all > 0) ? (dm_path_div->path_a_sum_all / dm_path_div->path_a_cnt_all) : 0 ; + rssi_avg_b = (dm_path_div->path_b_cnt_all > 0) ? (dm_path_div->path_b_sum_all / dm_path_div->path_b_cnt_all) : 0 ; + rssi_avg_c = (dm_path_div->path_c_cnt_all > 0) ? (dm_path_div->path_c_sum_all / dm_path_div->path_c_cnt_all) : 0 ; + rssi_avg_d = (dm_path_div->path_d_cnt_all > 0) ? (dm_path_div->path_d_sum_all / dm_path_div->path_d_cnt_all) : 0 ; - p_dm_path_div->path_a_sum_all = 0; - p_dm_path_div->path_a_cnt_all = 0; - p_dm_path_div->path_b_sum_all = 0; - p_dm_path_div->path_b_cnt_all = 0; - p_dm_path_div->path_c_sum_all = 0; - p_dm_path_div->path_c_cnt_all = 0; - p_dm_path_div->path_d_sum_all = 0; - p_dm_path_div->path_d_cnt_all = 0; + dm_path_div->path_a_sum_all = 0; + dm_path_div->path_a_cnt_all = 0; + dm_path_div->path_b_sum_all = 0; + dm_path_div->path_b_cnt_all = 0; + dm_path_div->path_c_sum_all = 0; + dm_path_div->path_c_cnt_all = 0; + dm_path_div->path_d_sum_all = 0; + dm_path_div->path_d_cnt_all = 0; - if (p_dm_path_div->use_path_a_as_default_ant == 1) { + if (dm_path_div->use_path_a_as_default_ant == 1) { rssi_avg_bcd = (rssi_avg_b + rssi_avg_c + rssi_avg_d) / 3; if ((rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd) { - p_dm_path_div->is_path_a_exist = true; - p_dm_path_div->default_path = PATH_A; + dm_path_div->is_path_a_exist = true; + dm_path_div->default_path = PATH_A; } else - p_dm_path_div->is_path_a_exist = false; + dm_path_div->is_path_a_exist = false; } else { if ((rssi_avg_a >= rssi_avg_b) && (rssi_avg_a >= rssi_avg_c) && (rssi_avg_a >= rssi_avg_d)) - p_dm_path_div->default_path = PATH_A; + dm_path_div->default_path = PATH_A; else if ((rssi_avg_b >= rssi_avg_c) && (rssi_avg_b >= rssi_avg_d)) - p_dm_path_div->default_path = PATH_B; + dm_path_div->default_path = PATH_B; else if (rssi_avg_c >= rssi_avg_d) - p_dm_path_div->default_path = PATH_C; + dm_path_div->default_path = PATH_C; else - p_dm_path_div->default_path = PATH_D; + dm_path_div->default_path = PATH_D; } @@ -237,76 +247,76 @@ phydm_find_default_path( void phydm_candidate_dtp_update( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; - p_dm_path_div->num_candidate = 3; + dm_path_div->num_candidate = 3; - if (p_dm_path_div->use_path_a_as_default_ant == 1) { - if (p_dm_path_div->num_tx_path == 3) { - if (p_dm_path_div->is_path_a_exist) { - p_dm_path_div->ant_candidate_1 = PHYDM_ABC; - p_dm_path_div->ant_candidate_2 = PHYDM_ABD; - p_dm_path_div->ant_candidate_3 = PHYDM_ACD; + if (dm_path_div->use_path_a_as_default_ant == 1) { + if (dm_path_div->num_tx_path == 3) { + if (dm_path_div->is_path_a_exist) { + dm_path_div->ant_candidate_1 = BB_PATH_ABC; + dm_path_div->ant_candidate_2 = BB_PATH_ABD; + dm_path_div->ant_candidate_3 = BB_PATH_ACD; } else { /* use path BCD */ - p_dm_path_div->num_candidate = 1; - phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BCD); + dm_path_div->num_candidate = 1; + phydm_dtp_fix_tx_path(dm, BB_PATH_BCD); return; } - } else if (p_dm_path_div->num_tx_path == 2) { - if (p_dm_path_div->is_path_a_exist) { - p_dm_path_div->ant_candidate_1 = PHYDM_AB; - p_dm_path_div->ant_candidate_2 = PHYDM_AC; - p_dm_path_div->ant_candidate_3 = PHYDM_AD; + } else if (dm_path_div->num_tx_path == 2) { + if (dm_path_div->is_path_a_exist) { + dm_path_div->ant_candidate_1 = BB_PATH_AB; + dm_path_div->ant_candidate_2 = BB_PATH_AC; + dm_path_div->ant_candidate_3 = BB_PATH_AD; } else { - p_dm_path_div->ant_candidate_1 = PHYDM_BC; - p_dm_path_div->ant_candidate_2 = PHYDM_BD; - p_dm_path_div->ant_candidate_3 = PHYDM_CD; + dm_path_div->ant_candidate_1 = BB_PATH_BC; + dm_path_div->ant_candidate_2 = BB_PATH_BD; + dm_path_div->ant_candidate_3 = BB_PATH_CD; } } } else { /* 2 3 TX mode */ - if (p_dm_path_div->num_tx_path == 3) { /* choose 3 ant form 4 */ - if (p_dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */ - p_dm_path_div->ant_candidate_1 = PHYDM_ABC; - p_dm_path_div->ant_candidate_2 = PHYDM_ABD; - p_dm_path_div->ant_candidate_3 = PHYDM_ACD; - } else if (p_dm_path_div->default_path == PATH_B) { - p_dm_path_div->ant_candidate_1 = PHYDM_ABC; - p_dm_path_div->ant_candidate_2 = PHYDM_ABD; - p_dm_path_div->ant_candidate_3 = PHYDM_BCD; - } else if (p_dm_path_div->default_path == PATH_C) { - p_dm_path_div->ant_candidate_1 = PHYDM_ABC; - p_dm_path_div->ant_candidate_2 = PHYDM_ACD; - p_dm_path_div->ant_candidate_3 = PHYDM_BCD; - } else if (p_dm_path_div->default_path == PATH_D) { - p_dm_path_div->ant_candidate_1 = PHYDM_ABD; - p_dm_path_div->ant_candidate_2 = PHYDM_ACD; - p_dm_path_div->ant_candidate_3 = PHYDM_BCD; + if (dm_path_div->num_tx_path == 3) { /* choose 3 ant form 4 */ + if (dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */ + dm_path_div->ant_candidate_1 = BB_PATH_ABC; + dm_path_div->ant_candidate_2 = BB_PATH_ABD; + dm_path_div->ant_candidate_3 = BB_PATH_ACD; + } else if (dm_path_div->default_path == PATH_B) { + dm_path_div->ant_candidate_1 = BB_PATH_ABC; + dm_path_div->ant_candidate_2 = BB_PATH_ABD; + dm_path_div->ant_candidate_3 = BB_PATH_BCD; + } else if (dm_path_div->default_path == PATH_C) { + dm_path_div->ant_candidate_1 = BB_PATH_ABC; + dm_path_div->ant_candidate_2 = BB_PATH_ACD; + dm_path_div->ant_candidate_3 = BB_PATH_BCD; + } else if (dm_path_div->default_path == PATH_D) { + dm_path_div->ant_candidate_1 = BB_PATH_ABD; + dm_path_div->ant_candidate_2 = BB_PATH_ACD; + dm_path_div->ant_candidate_3 = BB_PATH_BCD; } } /* 2 2 TX mode */ - else if (p_dm_path_div->num_tx_path == 2) { /* choose 2 ant form 4 */ - if (p_dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */ - p_dm_path_div->ant_candidate_1 = PHYDM_AB; - p_dm_path_div->ant_candidate_2 = PHYDM_AC; - p_dm_path_div->ant_candidate_3 = PHYDM_AD; - } else if (p_dm_path_div->default_path == PATH_B) { - p_dm_path_div->ant_candidate_1 = PHYDM_AB; - p_dm_path_div->ant_candidate_2 = PHYDM_BC; - p_dm_path_div->ant_candidate_3 = PHYDM_BD; - } else if (p_dm_path_div->default_path == PATH_C) { - p_dm_path_div->ant_candidate_1 = PHYDM_AC; - p_dm_path_div->ant_candidate_2 = PHYDM_BC; - p_dm_path_div->ant_candidate_3 = PHYDM_CD; - } else if (p_dm_path_div->default_path == PATH_D) { - p_dm_path_div->ant_candidate_1 = PHYDM_AD; - p_dm_path_div->ant_candidate_2 = PHYDM_BD; - p_dm_path_div->ant_candidate_3 = PHYDM_CD; + else if (dm_path_div->num_tx_path == 2) { /* choose 2 ant form 4 */ + if (dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */ + dm_path_div->ant_candidate_1 = BB_PATH_AB; + dm_path_div->ant_candidate_2 = BB_PATH_AC; + dm_path_div->ant_candidate_3 = BB_PATH_AD; + } else if (dm_path_div->default_path == PATH_B) { + dm_path_div->ant_candidate_1 = BB_PATH_AB; + dm_path_div->ant_candidate_2 = BB_PATH_BC; + dm_path_div->ant_candidate_3 = BB_PATH_BD; + } else if (dm_path_div->default_path == PATH_C) { + dm_path_div->ant_candidate_1 = BB_PATH_AC; + dm_path_div->ant_candidate_2 = BB_PATH_BC; + dm_path_div->ant_candidate_3 = BB_PATH_CD; + } else if (dm_path_div->default_path == PATH_D) { + dm_path_div->ant_candidate_1 = BB_PATH_AD; + dm_path_div->ant_candidate_2 = BB_PATH_BD; + dm_path_div->ant_candidate_3 = BB_PATH_CD; } } } @@ -315,86 +325,87 @@ phydm_candidate_dtp_update( void phydm_dynamic_tx_path( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; - struct sta_info *p_entry; + struct sta_info *entry; u32 i; u8 num_client = 0; u8 h2c_parameter[6] = {0}; - if (!p_dm_odm->is_linked) { /* is_linked==False */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("DTP_8814 [No Link!!!]\n")); + if (!dm->is_linked) { /* is_linked==False */ + PHYDM_DBG(dm, DBG_PATH_DIV, "DTP_8814 [No Link!!!]\n"); - if (p_dm_path_div->is_become_linked == true) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be disconnected]----->\n")); - p_dm_path_div->is_become_linked = p_dm_odm->is_linked; + if (dm_path_div->is_become_linked == true) { + PHYDM_DBG(dm, DBG_PATH_DIV, " [Be disconnected]----->\n"); + dm_path_div->is_become_linked = dm->is_linked; } return; } else { - if (p_dm_path_div->is_become_linked == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be Linked !!!]----->\n")); - p_dm_path_div->is_become_linked = p_dm_odm->is_linked; + if (dm_path_div->is_become_linked == false) { + PHYDM_DBG(dm, DBG_PATH_DIV, " [Be Linked !!!]----->\n"); + dm_path_div->is_become_linked = dm->is_linked; } } /* 2 [period CTRL] */ - if (p_dm_path_div->dtp_period >= 2) - p_dm_path_div->dtp_period = 0; + if (dm_path_div->dtp_period >= 2) + dm_path_div->dtp_period = 0; else { - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",p_dm_path_div->dtp_period)); */ - p_dm_path_div->dtp_period++; + /* PHYDM_DBG(dm,DBG_PATH_DIV, "Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",dm_path_div->dtp_period); */ + dm_path_div->dtp_period++; return; } /* 2 [Fix path] */ - if (p_dm_odm->path_select != PHYDM_AUTO_PATH) + if (dm->path_select != PHYDM_AUTO_PATH) return; /* 2 [Check Bfer] */ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #if (BEAMFORMING_SUPPORT == 1) { - enum beamforming_cap beamform_cap = (p_dm_odm->beamforming_info.beamform_cap); + enum beamforming_cap beamform_cap = (dm->beamforming_info.beamform_cap); if (beamform_cap & BEAMFORMER_CAP) { /* BFmer On && Div On->Div Off */ - if (p_dm_path_div->fix_path_bfer == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[ PathDiv : OFF ] BFmer ==1\n")); - p_dm_path_div->fix_path_bfer = 1 ; + if (dm_path_div->fix_path_bfer == 0) { + PHYDM_DBG(dm, DBG_PATH_DIV, "[ PathDiv : OFF ] BFmer ==1\n"); + dm_path_div->fix_path_bfer = 1 ; } return; } else { /* BFmer Off && Div Off->Div On */ - if (p_dm_path_div->fix_path_bfer == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[ PathDiv : ON ] BFmer ==0\n")); - p_dm_path_div->fix_path_bfer = 0; + if (dm_path_div->fix_path_bfer == 1) { + PHYDM_DBG(dm, DBG_PATH_DIV, "[ PathDiv : ON ] BFmer ==0\n"); + dm_path_div->fix_path_bfer = 0; } } } #endif #endif - if (p_dm_path_div->use_path_a_as_default_ant == 1) { - phydm_find_default_path(p_dm_odm); - phydm_candidate_dtp_update(p_dm_odm); + if (dm_path_div->use_path_a_as_default_ant == 1) { + phydm_find_default_path(dm); + phydm_candidate_dtp_update(dm); } else { - if (p_dm_path_div->phydm_dtp_state == PHYDM_DTP_INIT) { - phydm_find_default_path(p_dm_odm); - phydm_candidate_dtp_update(p_dm_odm); - p_dm_path_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1; + if (dm_path_div->phydm_dtp_state == PHYDM_DTP_INIT) { + phydm_find_default_path(dm); + phydm_candidate_dtp_update(dm); + dm_path_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1; } - else if (p_dm_path_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) { - p_dm_path_div->dtp_check_patha_counter++; + else if (dm_path_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) { + dm_path_div->dtp_check_patha_counter++; - if (p_dm_path_div->dtp_check_patha_counter >= NUM_RESET_DTP_PERIOD) { - p_dm_path_div->dtp_check_patha_counter = 0; - p_dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT; + if (dm_path_div->dtp_check_patha_counter >= NUM_RESET_DTP_PERIOD) { + dm_path_div->dtp_check_patha_counter = 0; + dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT; } +#if 0 /* 2 Search space update */ else { /* 1. find the worst candidate */ @@ -402,21 +413,22 @@ phydm_dynamic_tx_path( /* 2. repalce the worst candidate */ } +#endif } } /* 2 Dynamic path Selection H2C */ - if (p_dm_path_div->num_candidate == 1) + if (dm_path_div->num_candidate == 1) return; else { - h2c_parameter[0] = p_dm_path_div->num_candidate; - h2c_parameter[1] = p_dm_path_div->num_tx_path; - h2c_parameter[2] = p_dm_path_div->ant_candidate_1; - h2c_parameter[3] = p_dm_path_div->ant_candidate_2; - h2c_parameter[4] = p_dm_path_div->ant_candidate_3; + h2c_parameter[0] = dm_path_div->num_candidate; + h2c_parameter[1] = dm_path_div->num_tx_path; + h2c_parameter[2] = dm_path_div->ant_candidate_1; + h2c_parameter[3] = dm_path_div->ant_candidate_2; + h2c_parameter[4] = dm_path_div->ant_candidate_3; - odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter); + odm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter); } } @@ -425,39 +437,41 @@ phydm_dynamic_tx_path( void phydm_dynamic_tx_path_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div); - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - u8 search_space_2[NUM_CHOOSE2_FROM4] = {PHYDM_AB, PHYDM_AC, PHYDM_AD, PHYDM_BC, PHYDM_BD, PHYDM_CD }; - u8 search_space_3[NUM_CHOOSE3_FROM4] = {PHYDM_BCD, PHYDM_ACD, PHYDM_ABD, PHYDM_ABC}; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; + void *adapter = dm->adapter; + u8 search_space_2[NUM_CHOOSE2_FROM4] = {BB_PATH_AB, BB_PATH_AC, BB_PATH_AD, BB_PATH_BC, BB_PATH_BD, BB_PATH_CD }; + u8 search_space_3[NUM_CHOOSE3_FROM4] = {BB_PATH_BCD, BB_PATH_ACD, BB_PATH_ABD, BB_PATH_ABC}; #if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT) - p_dm_path_div->is_u3_mode = (*p_dm_odm->hub_usb_mode == 2) ? 1 : 0 ; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[WIN USB] is_u3_mode = (( %d ))\n", p_dm_path_div->is_u3_mode)); + dm_path_div->is_u3_mode = (*dm->hub_usb_mode == 2) ? 1 : 0; + PHYDM_DBG(dm, DBG_PATH_DIV, "[WIN USB] is_u3_mode = (( %d ))\n", dm_path_div->is_u3_mode); #else - p_dm_path_div->is_u3_mode = 1; + dm_path_div->is_u3_mode = 1; #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Dynamic TX path Init 8814\n")); + PHYDM_DBG(dm, DBG_PATH_DIV, "Dynamic TX path Init 8814\n"); - memcpy(&(p_dm_path_div->search_space_2[0]), &(search_space_2[0]), NUM_CHOOSE2_FROM4); - memcpy(&(p_dm_path_div->search_space_3[0]), &(search_space_3[0]), NUM_CHOOSE3_FROM4); + memcpy(&dm_path_div->search_space_2[0], &search_space_2[0], + NUM_CHOOSE2_FROM4); + memcpy(&dm_path_div->search_space_3[0], &search_space_3[0], + NUM_CHOOSE3_FROM4); - p_dm_path_div->use_path_a_as_default_ant = 1; - p_dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT; - p_dm_odm->path_select = PHYDM_AUTO_PATH; - p_dm_path_div->phydm_path_div_type = PHYDM_4R_PATH_DIV; + dm_path_div->use_path_a_as_default_ant = 1; + dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT; + dm->path_select = PHYDM_AUTO_PATH; + dm_path_div->phydm_path_div_type = PHYDM_4R_PATH_DIV; - if (p_dm_path_div->is_u3_mode) { - p_dm_path_div->num_tx_path = 3; - phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BCD);/* 3TX Set Init TX path*/ + if (dm_path_div->is_u3_mode) { + dm_path_div->num_tx_path = 3; + phydm_dtp_fix_tx_path(dm, BB_PATH_BCD);/* 3TX Set Init TX path*/ } else { - p_dm_path_div->num_tx_path = 2; - phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BC);/* 2TX // Set Init TX path*/ + dm_path_div->num_tx_path = 2; + phydm_dtp_fix_tx_path(dm, BB_PATH_BC);/* 2TX // Set Init TX path*/ } } @@ -465,91 +479,97 @@ phydm_dynamic_tx_path_init( void phydm_process_rssi_for_path_div( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void + void *dm_void, + void *phy_info_void, + void *pkt_info_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; - struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div); - - if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_match_bssid) { - if (p_pktinfo->data_rate > ODM_RATE11M) { - if (p_dm_path_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; + + if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid)) + return; + + if (pktinfo->data_rate <= ODM_RATE11M) + return; + + if (dm_path_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) { #if RTL8814A_SUPPORT - if (p_dm_odm->support_ic_type & ODM_RTL8814A) { - p_dm_path_div->path_a_sum_all += p_phy_info->rx_mimo_signal_strength[0]; - p_dm_path_div->path_a_cnt_all++; + if (dm->support_ic_type & ODM_RTL8814A) { + dm_path_div->path_a_sum_all += phy_info->rx_mimo_signal_strength[0]; + dm_path_div->path_a_cnt_all++; - p_dm_path_div->path_b_sum_all += p_phy_info->rx_mimo_signal_strength[1]; - p_dm_path_div->path_b_cnt_all++; + dm_path_div->path_b_sum_all += phy_info->rx_mimo_signal_strength[1]; + dm_path_div->path_b_cnt_all++; - p_dm_path_div->path_c_sum_all += p_phy_info->rx_mimo_signal_strength[2]; - p_dm_path_div->path_c_cnt_all++; + dm_path_div->path_c_sum_all += phy_info->rx_mimo_signal_strength[2]; + dm_path_div->path_c_cnt_all++; - p_dm_path_div->path_d_sum_all += p_phy_info->rx_mimo_signal_strength[3]; - p_dm_path_div->path_d_cnt_all++; - } + dm_path_div->path_d_sum_all += phy_info->rx_mimo_signal_strength[3]; + dm_path_div->path_d_cnt_all++; + } #endif - } else { - p_dm_path_div->path_a_sum[p_pktinfo->station_id] += p_phy_info->rx_mimo_signal_strength[0]; - p_dm_path_div->path_a_cnt[p_pktinfo->station_id]++; + } else { + dm_path_div->path_a_sum[pktinfo->station_id] += phy_info->rx_mimo_signal_strength[0]; + dm_path_div->path_a_cnt[pktinfo->station_id]++; - p_dm_path_div->path_b_sum[p_pktinfo->station_id] += p_phy_info->rx_mimo_signal_strength[1]; - p_dm_path_div->path_b_cnt[p_pktinfo->station_id]++; - } - } + dm_path_div->path_b_sum[pktinfo->station_id] += phy_info->rx_mimo_signal_strength[1]; + dm_path_div->path_b_cnt[pktinfo->station_id]++; } - - } #endif /* #if RTL8814A_SUPPORT */ void odm_pathdiv_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, - char *output, + char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; u32 used = *_used; u32 out_len = *_out_len; - p_dm_odm->path_select = (dm_value[0] & 0xf); - PHYDM_SNPRINTF((output + used, out_len - used, "Path_select = (( 0x%x ))\n", p_dm_odm->path_select)); + dm->path_select = (dm_value[0] & 0xf); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Path_select = (( 0x%x ))\n", dm->path_select); /* 2 [Fix path] */ - if (p_dm_odm->path_select != PHYDM_AUTO_PATH) { - PHYDM_SNPRINTF((output + used, out_len - used, "Trun on path [%s%s%s%s]\n", - ((p_dm_odm->path_select) & 0x1) ? "A" : "", - ((p_dm_odm->path_select) & 0x2) ? "B" : "", - ((p_dm_odm->path_select) & 0x4) ? "C" : "", - ((p_dm_odm->path_select) & 0x8) ? "D" : "")); - - phydm_dtp_fix_tx_path(p_dm_odm, p_dm_odm->path_select); + if (dm->path_select != PHYDM_AUTO_PATH) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Trun on path [%s%s%s%s]\n", + ((dm->path_select) & 0x1) ? "A" : "", + ((dm->path_select) & 0x2) ? "B" : "", + ((dm->path_select) & 0x4) ? "C" : "", + ((dm->path_select) & 0x8) ? "D" : ""); + + phydm_dtp_fix_tx_path(dm, dm->path_select); } else - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Auto path")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s\n", "Auto path"); + + *_used = used; + *_out_len = out_len; } #endif /* #if(defined(CONFIG_PATH_DIVERSITY)) */ void phydm_c2h_dtp_handler( - void *p_dm_void, + void *dm_void, u8 *cmd_buf, u8 cmd_len ) { #if (defined(CONFIG_PATH_DIVERSITY)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; u8 macid = cmd_buf[0]; u8 target = cmd_buf[1]; @@ -557,19 +577,19 @@ phydm_c2h_dtp_handler( u8 nsc_2 = cmd_buf[3]; u8 nsc_3 = cmd_buf[4]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Target_candidate = (( %d ))\n", target)); + PHYDM_DBG(dm, DBG_PATH_DIV, "Target_candidate = (( %d ))\n", target); /* if( (nsc_1 >= nsc_2) && (nsc_1 >= nsc_3)) { - phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_1); + phydm_dtp_fix_tx_path(dm, dm_path_div->ant_candidate_1); } else if( nsc_2 >= nsc_3) { - phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_2); + phydm_dtp_fix_tx_path(dm, dm_path_div->ant_candidate_2); } else { - phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_3); + phydm_dtp_fix_tx_path(dm, dm_path_div->ant_candidate_3); } */ #endif @@ -577,26 +597,27 @@ phydm_c2h_dtp_handler( void odm_path_diversity( - void *p_dm_void + void *dm_void ) { #if (defined(CONFIG_PATH_DIVERSITY)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (!(p_dm_odm->support_ability & ODM_BB_PATH_DIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Return: Not Support PathDiv\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_PATH_DIV)) { + PHYDM_DBG(dm, DBG_PATH_DIV, "Return: Not Support PathDiv\n"); return; } #if RTL8812A_SUPPORT - if (p_dm_odm->support_ic_type & ODM_RTL8812) - odm_path_diversity_8812a(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8812) + odm_path_diversity_8812a(dm); else #endif #if RTL8814A_SUPPORT - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - phydm_dynamic_tx_path(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8814A) + phydm_dynamic_tx_path(dm); else #endif {} @@ -604,32 +625,32 @@ odm_path_diversity( } void -odm_path_diversity_init( - void *p_dm_void +phydm_path_diversity_init( + void *dm_void ) { #if (defined(CONFIG_PATH_DIVERSITY)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - /*p_dm_odm->support_ability |= ODM_BB_PATH_DIV;*/ + /*dm->support_ability |= ODM_BB_PATH_DIV;*/ - if (*(p_dm_odm->p_mp_mode) == true) + if (*dm->mp_mode == true) return; - if (!(p_dm_odm->support_ability & ODM_BB_PATH_DIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Return: Not Support PathDiv\n")); + if (!(dm->support_ability & ODM_BB_PATH_DIV)) { + PHYDM_DBG(dm, DBG_PATH_DIV, "Return: Not Support PathDiv\n"); return; } #if RTL8812A_SUPPORT - if (p_dm_odm->support_ic_type & ODM_RTL8812) - odm_path_diversity_init_8812a(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8812) + odm_path_diversity_init_8812a(dm); else #endif #if RTL8814A_SUPPORT - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - phydm_dynamic_tx_path_init(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8814A) + phydm_dynamic_tx_path_init(dm); else #endif {} @@ -645,41 +666,41 @@ odm_path_diversity_init( void odm_path_div_chk_ant_switch_callback( - struct timer_list *p_timer + struct phydm_timer_list *timer ) { } void odm_path_div_chk_ant_switch_workitem_callback( - void *p_context + void *context ) { } void odm_cck_tx_path_diversity_callback( - struct timer_list *p_timer + struct phydm_timer_list *timer ) { } void odm_cck_tx_path_diversity_work_item_callback( - void *p_context + void *context ) { } u8 odm_sw_ant_div_select_scan_chnl( - struct _ADAPTER *adapter + void *adapter ) { return 0; } void odm_sw_ant_div_construct_scan_chnl( - struct _ADAPTER *adapter, + void *adapter, u8 scan_chnl ) { diff --git a/hal/phydm/phydm_pathdiv.h b/hal/phydm/phydm_pathdiv.h index e12b56f..29e2078 100644 --- a/hal/phydm/phydm_pathdiv.h +++ b/hal/phydm/phydm_pathdiv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __PHYDMPATHDIV_H__ @@ -35,26 +45,6 @@ #define NUM_CHOOSE2_FROM4 6 #define NUM_CHOOSE3_FROM4 4 - -#define PHYDM_A BIT(0) -#define PHYDM_B BIT(1) -#define PHYDM_C BIT(2) -#define PHYDM_D BIT(3) -#define PHYDM_AB (BIT(0) | BIT1) /* 0 */ -#define PHYDM_AC (BIT(0) | BIT2) /* 1 */ -#define PHYDM_AD (BIT(0) | BIT3) /* 2 */ -#define PHYDM_BC (BIT(1) | BIT2) /* 3 */ -#define PHYDM_BD (BIT(1) | BIT3) /* 4 */ -#define PHYDM_CD (BIT(2) | BIT3) /* 5 */ - -#define PHYDM_ABC (BIT(0) | BIT1 | BIT2) /* 0*/ -#define PHYDM_ABD (BIT(0) | BIT1 | BIT3) /* 1*/ -#define PHYDM_ACD (BIT(0) | BIT2 | BIT3) /* 2*/ -#define PHYDM_BCD (BIT(1) | BIT2 | BIT3) /* 3*/ - -#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3)) - - enum phydm_dtp_state { PHYDM_DTP_INIT = 1, PHYDM_DTP_RUNNING_1 @@ -68,9 +58,9 @@ enum phydm_path_div_type { void phydm_process_rssi_for_path_div( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void + void *dm_void, + void *phy_info_void, + void *pkt_info_void ); struct _ODM_PATH_DIVERSITY_ { @@ -120,24 +110,24 @@ struct _ODM_PATH_DIVERSITY_ { void phydm_c2h_dtp_handler( - void *p_dm_void, + void *dm_void, u8 *cmd_buf, u8 cmd_len ); void -odm_path_diversity_init( - void *p_dm_void +phydm_path_diversity_init( + void *dm_void ); void odm_path_diversity( - void *p_dm_void + void *dm_void ); void odm_pathdiv_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, char *output, @@ -185,126 +175,126 @@ struct _path_div_parameter_define_ { void odm_path_diversity_init_92c( - struct _ADAPTER *adapter + void *adapter ); void odm_2t_path_diversity_init_92c( - struct _ADAPTER *adapter + void *adapter ); void odm_1t_path_diversity_init_92c( - struct _ADAPTER *adapter + void *adapter ); boolean odm_is_connected_92c( - struct _ADAPTER *adapter + void *adapter ); boolean odm_path_diversity_before_link92c( - /* struct _ADAPTER* adapter */ - struct PHY_DM_STRUCT *p_dm_odm + /* struct void* adapter */ + struct dm_struct *dm ); void odm_path_diversity_after_link_92c( - struct _ADAPTER *adapter + void *adapter ); void odm_set_resp_path_92c( - struct _ADAPTER *adapter, + void *adapter, u8 default_resp_path ); void odm_ofdm_tx_path_diversity_92c( - struct _ADAPTER *adapter + void *adapter ); void odm_cck_tx_path_diversity_92c( - struct _ADAPTER *adapter + void *adapter ); void odm_reset_path_diversity_92c( - struct _ADAPTER *adapter + void *adapter ); void odm_cck_tx_path_diversity_callback( - struct timer_list *p_timer + struct phydm_timer_list *timer ); void odm_cck_tx_path_diversity_work_item_callback( - void *p_context + void *context ); void odm_path_div_chk_ant_switch_callback( - struct timer_list *p_timer + struct phydm_timer_list *timer ); void odm_path_div_chk_ant_switch_workitem_callback( - void *p_context + void *context ); void odm_path_div_chk_ant_switch( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); void odm_cck_path_diversity_chk_per_pkt_rssi( - struct _ADAPTER *adapter, + void *adapter, boolean is_def_port, boolean is_match_bssid, - struct _WLAN_STA *p_entry, - PRT_RFD p_rfd, - u8 *p_desc + struct _WLAN_STA *entry, + PRT_RFD rfd, + u8 *desc ); void odm_path_div_chk_per_pkt_rssi( - struct _ADAPTER *adapter, + void *adapter, boolean is_def_port, boolean is_match_bssid, - struct _WLAN_STA *p_entry, - PRT_RFD p_rfd + struct _WLAN_STA *entry, + PRT_RFD rfd ); void odm_path_div_rest_after_link( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); void odm_fill_tx_path_in_txdesc( - struct _ADAPTER *adapter, - PRT_TCB p_tcb, - u8 *p_desc + void *adapter, + PRT_TCB tcb, + u8 *desc ); void odm_path_div_init_92d( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u8 odm_sw_ant_div_select_scan_chnl( - struct _ADAPTER *adapter + void *adapter ); void odm_sw_ant_div_construct_scan_chnl( - struct _ADAPTER *adapter, + void *adapter, u8 scan_chnl ); diff --git a/hal/phydm/phydm_powertracking_ap.c b/hal/phydm/phydm_powertracking_ap.c deleted file mode 100644 index ea1e531..0000000 --- a/hal/phydm/phydm_powertracking_ap.c +++ /dev/null @@ -1,1216 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#if !defined(_OUTSRC_COEXIST) -//============================================================ -// Global var -//============================================================ - - -u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE_92D] = { - 0x0b40002d, // 0, -15.0dB - 0x0c000030, // 1, -14.5dB - 0x0cc00033, // 2, -14.0dB - 0x0d800036, // 3, -13.5dB - 0x0e400039, // 4, -13.0dB - 0x0f00003c, // 5, -12.5dB - 0x10000040, // 6, -12.0dB - 0x11000044, // 7, -11.5dB - 0x12000048, // 8, -11.0dB - 0x1300004c, // 9, -10.5dB - 0x14400051, // 10, -10.0dB - 0x15800056, // 11, -9.5dB - 0x16c0005b, // 12, -9.0dB - 0x18000060, // 13, -8.5dB - 0x19800066, // 14, -8.0dB - 0x1b00006c, // 15, -7.5dB - 0x1c800072, // 16, -7.0dB - 0x1e400079, // 17, -6.5dB - 0x20000080, // 18, -6.0dB - 0x22000088, // 19, -5.5dB - 0x24000090, // 20, -5.0dB - 0x26000098, // 21, -4.5dB - 0x288000a2, // 22, -4.0dB - 0x2ac000ab, // 23, -3.5dB - 0x2d4000b5, // 24, -3.0dB - 0x300000c0, // 25, -2.5dB - 0x32c000cb, // 26, -2.0dB - 0x35c000d7, // 27, -1.5dB - 0x390000e4, // 28, -1.0dB - 0x3c8000f2, // 29, -0.5dB - 0x40000100, // 30, +0dB - 0x43c0010f, // 31, +0.5dB - 0x47c0011f, // 32, +1.0dB - 0x4c000130, // 33, +1.5dB - 0x50800142, // 34, +2.0dB - 0x55400155, // 35, +2.5dB - 0x5a400169, // 36, +3.0dB - 0x5fc0017f, // 37, +3.5dB - 0x65400195, // 38, +4.0dB - 0x6b8001ae, // 39, +4.5dB - 0x71c001c7, // 40, +5.0dB - 0x788001e2, // 41, +5.5dB - 0x7f8001fe // 42, +6.0dB -}; - -u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = { - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB - {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, // 20, -6.0dB - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB -}; - - -u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= { - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB - {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB -}; - -u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { - 0x0b40002d, // 0, -15.0dB - 0x0c000030, // 1, -14.5dB - 0x0cc00033, // 2, -14.0dB - 0x0d800036, // 3, -13.5dB - 0x0e400039, // 4, -13.0dB - 0x0f00003c, // 5, -12.5dB - 0x10000040, // 6, -12.0dB - 0x11000044, // 7, -11.5dB - 0x12000048, // 8, -11.0dB - 0x1300004c, // 9, -10.5dB - 0x14400051, // 10, -10.0dB - 0x15800056, // 11, -9.5dB - 0x16c0005b, // 12, -9.0dB - 0x18000060, // 13, -8.5dB - 0x19800066, // 14, -8.0dB - 0x1b00006c, // 15, -7.5dB - 0x1c800072, // 16, -7.0dB - 0x1e400079, // 17, -6.5dB - 0x20000080, // 18, -6.0dB - 0x22000088, // 19, -5.5dB - 0x24000090, // 20, -5.0dB - 0x26000098, // 21, -4.5dB - 0x288000a2, // 22, -4.0dB - 0x2ac000ab, // 23, -3.5dB - 0x2d4000b5, // 24, -3.0dB - 0x300000c0, // 25, -2.5dB - 0x32c000cb, // 26, -2.0dB - 0x35c000d7, // 27, -1.5dB - 0x390000e4, // 28, -1.0dB - 0x3c8000f2, // 29, -0.5dB - 0x40000100, // 30, +0dB - 0x43c0010f, // 31, +0.5dB - 0x47c0011f, // 32, +1.0dB - 0x4c000130, // 33, +1.5dB - 0x50800142, // 34, +2.0dB - 0x55400155, // 35, +2.5dB - 0x5a400169, // 36, +3.0dB - 0x5fc0017f, // 37, +3.5dB - 0x65400195, // 38, +4.0dB - 0x6b8001ae, // 39, +4.5dB - 0x71c001c7, // 40, +5.0dB - 0x788001e2, // 41, +5.5dB - 0x7f8001fe // 42, +6.0dB -}; - - -u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB - {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, // 20, -6.0dB - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB -}; - - -u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= { - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB - {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB -}; - -u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { -{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */ -{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */ -{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */ -{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */ -{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */ -{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */ -{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */ -{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */ -{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */ -{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */ -{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */ -{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */ -{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */ -{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */ -{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */ -{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */ -{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */ -{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */ -{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */ -{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */ -{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */ -}; - - -u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16] = { -{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */ -{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */ -{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */ -{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */ -{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */ -{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */ -{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */ -{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */ -{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */ -{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */ -{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */ -{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */ -{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */ -{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */ -{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */ -{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */ -{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */ -{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */ -{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */ -{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */ -{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */ -}; - - -u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - - -#if 0 -u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E] = { - /* Index0 6 dB */ 0x7fc001ff, - /* Index1 5.7dB */ 0x7b4001ed, - /* Index2 5.4dB */ 0x774001dd, - /* Index3 5.1dB */ 0x734001cd, - /* Index4 4.8dB */ 0x6f4001bd, - /* Index5 4.5dB */ 0x6b8001ae, - /* Index6 4.2dB */ 0x67c0019f, - /* Index7 3.9dB */ 0x64400191, - /* Index8 3.6dB */ 0x60c00183, - /* Index9 3.3dB */ 0x5d800176, - /* Index10 3 dB */ 0x5a80016a, - /* Index11 2.7dB */ 0x5740015d, - /* Index12 2.4dB */ 0x54400151, - /* Index13 2.1dB */ 0x51800146, - /* Index14 1.8dB */ 0x4ec0013b, - /* Index15 1.5dB */ 0x4c000130, - /* Index16 1.2dB */ 0x49800126, - /* Index17 0.9dB */ 0x4700011c, - /* Index18 0.6dB */ 0x44800112, - /* Index19 0.3dB */ 0x42000108, - /* Index20 0 dB */ 0x40000100, // 20 This is OFDM base index - /* Index21 -0.3dB */ 0x3dc000f7, - /* Index22 -0.6dB */ 0x3bc000ef, - /* Index23 -0.9dB */ 0x39c000e7, - /* Index24 -1.2dB */ 0x37c000df, - /* Index25 -1.5dB */ 0x35c000d7, - /* Index26 -1.8dB */ 0x340000d0, - /* Index27 -2.1dB */ 0x324000c9, - /* Index28 -2.4dB */ 0x308000c2, - /* Index29 -2.7dB */ 0x2f0000bc, - /* Index30 -3 dB */ 0x2d4000b5, - /* Index31 -3.3dB */ 0x2bc000af, - /* Index32 -3.6dB */ 0x2a4000a9, - /* Index33 -3.9dB */ 0x28c000a3, - /* Index34 -4.2dB */ 0x2780009e, - /* Index35 -4.5dB */ 0x26000098, - /* Index36 -4.8dB */ 0x24c00093, - /* Index37 -5.1dB */ 0x2380008e, - /* Index38 -5.4dB */ 0x22400089, - /* Index39 -5.7dB */ 0x21400085, - /* Index40 -6 dB */ 0x20000080, - /* Index41 -6.3dB */ 0x1f00007c, - /* Index42 -6.6dB */ 0x1e000078, - /* Index43 -6.9dB */ 0x1d000074, - /* Index44 -7.2dB */ 0x1c000070, - /* Index45 -7.5dB */ 0x1b00006c, - /* Index46 -7.8dB */ 0x1a000068, - /* Index47 -8.1dB */ 0x19400065, - /* Index48 -8.4dB */ 0x18400061, - /* Index49 -8.7dB */ 0x1780005e, - /* Index50 -9 dB */ 0x16c0005b, - /* Index51 -9.3dB */ 0x16000058, - /* Index52 -9.6dB */ 0x15400055, - /* Index53 -9.9dB */ 0x14800052 -}; -u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8] = { - /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x1C , 0x12 , 0x08 , 0x04}, - /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x1B , 0x11 , 0x08 , 0x04}, - /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x1A , 0x11 , 0x07 , 0x04}, - /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x19 , 0x10 , 0x07 , 0x04}, - /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x18 , 0x10 , 0x07 , 0x03}, - /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x18 , 0x0F , 0x07 , 0x03}, - /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x17 , 0x0F , 0x06 , 0x03}, - /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x16 , 0x0E , 0x06 , 0x03}, - /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x15 , 0x0E , 0x06 , 0x03}, - /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x14 , 0x0D , 0x06 , 0x03}, - /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x14 , 0x0D , 0x06 , 0x03}, - /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x13 , 0x0C , 0x05 , 0x03}, - /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x12 , 0x0C , 0x05 , 0x03}, - /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x12 , 0x0B , 0x05 , 0x03}, - /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, - /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, - /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x10 , 0x0A , 0x05 , 0x02}, - /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x10 , 0x0A , 0x04 , 0x02}, - /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x0F , 0x0A , 0x04 , 0x02}, - /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x0E , 0x09 , 0x04 , 0x02}, - /* Index20 -6.0dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x0E , 0x09 , 0x04 , 0x02}, // 20 This is CCK base index - /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x0E , 0x09 , 0x04 , 0x02}, - /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x0D , 0x08 , 0x04 , 0x02}, - /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x0D , 0x08 , 0x04 , 0x02}, - /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x0C , 0x08 , 0x03 , 0x02}, - /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x0C , 0x08 , 0x03 , 0x02}, - /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, - /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, - /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x0B , 0x07 , 0x03 , 0x02}, - /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x0A , 0x07 , 0x03 , 0x01}, - /* Index30 -9.0dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, // 30 This is hp CCK base index - /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, - /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x09 , 0x06 , 0x03 , 0x01}, - /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x09 , 0x06 , 0x03 , 0x01}, - /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x09 , 0x06 , 0x02 , 0x01}, - /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, - /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, - /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x08 , 0x05 , 0x02 , 0x01}, - /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, - /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, - /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, - /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, - /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, - /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x05 , 0x03 , 0x02 , 0x01}, - /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x04 , 0x03 , 0x01 , 0x01} -}; -u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8] = { - /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index20 -6 dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index30 -9 dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00} -}; -#endif - -#ifdef AP_BUILD_WORKAROUND - -unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { - /* +6.0dB */ 0x7f8001fe, - /* +5.5dB */ 0x788001e2, - /* +5.0dB */ 0x71c001c7, - /* +4.5dB */ 0x6b8001ae, - /* +4.0dB */ 0x65400195, - /* +3.5dB */ 0x5fc0017f, - /* +3.0dB */ 0x5a400169, - /* +2.5dB */ 0x55400155, - /* +2.0dB */ 0x50800142, - /* +1.5dB */ 0x4c000130, - /* +1.0dB */ 0x47c0011f, - /* +0.5dB */ 0x43c0010f, - /* 0.0dB */ 0x40000100, - /* -0.5dB */ 0x3c8000f2, - /* -1.0dB */ 0x390000e4, - /* -1.5dB */ 0x35c000d7, - /* -2.0dB */ 0x32c000cb, - /* -2.5dB */ 0x300000c0, - /* -3.0dB */ 0x2d4000b5, - /* -3.5dB */ 0x2ac000ab, - /* -4.0dB */ 0x288000a2, - /* -4.5dB */ 0x26000098, - /* -5.0dB */ 0x24000090, - /* -5.5dB */ 0x22000088, - /* -6.0dB */ 0x20000080, - /* -6.5dB */ 0x1a00006c, - /* -7.0dB */ 0x1c800072, - /* -7.5dB */ 0x18000060, - /* -8.0dB */ 0x19800066, - /* -8.5dB */ 0x15800056, - /* -9.0dB */ 0x26c0005b, - /* -9.5dB */ 0x14400051, - /* -10.0dB */ 0x24400051, - /* -10.5dB */ 0x1300004c, - /* -11.0dB */ 0x12000048, - /* -11.5dB */ 0x11000044, - /* -12.0dB */ 0x10000040 -}; -#endif - -#endif - - -u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3 -, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; -u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4 -, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; - - -#ifdef CONFIG_WLAN_HAL_8192EE -u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E] = { - /* Index0 6 dB */ 0x7fc001ff, - /* Index1 5.7dB */ 0x7b4001ed, - /* Index2 5.4dB */ 0x774001dd, - /* Index3 5.1dB */ 0x734001cd, - /* Index4 4.8dB */ 0x6f4001bd, - /* Index5 4.5dB */ 0x6b8001ae, - /* Index6 4.2dB */ 0x67c0019f, - /* Index7 3.9dB */ 0x64400191, - /* Index8 3.6dB */ 0x60c00183, - /* Index9 3.3dB */ 0x5d800176, - /* Index10 3 dB */ 0x5a80016a, - /* Index11 2.7dB */ 0x5740015d, - /* Index12 2.4dB */ 0x54400151, - /* Index13 2.1dB */ 0x51800146, - /* Index14 1.8dB */ 0x4ec0013b, - /* Index15 1.5dB */ 0x4c000130, - /* Index16 1.2dB */ 0x49800126, - /* Index17 0.9dB */ 0x4700011c, - /* Index18 0.6dB */ 0x44800112, - /* Index19 0.3dB */ 0x42000108, - /* Index20 0 dB */ 0x40000100, // 20 This is OFDM base index - /* Index21 -0.3dB */ 0x3dc000f7, - /* Index22 -0.6dB */ 0x3bc000ef, - /* Index23 -0.9dB */ 0x39c000e7, - /* Index24 -1.2dB */ 0x37c000df, - /* Index25 -1.5dB */ 0x35c000d7, - /* Index26 -1.8dB */ 0x340000d0, - /* Index27 -2.1dB */ 0x324000c9, - /* Index28 -2.4dB */ 0x308000c2, - /* Index29 -2.7dB */ 0x2f0000bc, - /* Index30 -3 dB */ 0x2d4000b5, - /* Index31 -3.3dB */ 0x2bc000af, - /* Index32 -3.6dB */ 0x2a4000a9, - /* Index33 -3.9dB */ 0x28c000a3, - /* Index34 -4.2dB */ 0x2780009e, - /* Index35 -4.5dB */ 0x26000098, - /* Index36 -4.8dB */ 0x24c00093, - /* Index37 -5.1dB */ 0x2380008e, - /* Index38 -5.4dB */ 0x22400089, - /* Index39 -5.7dB */ 0x21400085, - /* Index40 -6 dB */ 0x20000080, - /* Index41 -6.3dB */ 0x1f00007c, - /* Index42 -6.6dB */ 0x1e000078, - /* Index43 -6.9dB */ 0x1d000074, - /* Index44 -7.2dB */ 0x1c000070, - /* Index45 -7.5dB */ 0x1b00006c, - /* Index46 -7.8dB */ 0x1a000068, - /* Index47 -8.1dB */ 0x19400065, - /* Index48 -8.4dB */ 0x18400061, - /* Index49 -8.7dB */ 0x1780005e, - /* Index50 -9 dB */ 0x16c0005b, - /* Index51 -9.3dB */ 0x16000058, - /* Index52 -9.6dB */ 0x15400055, - /* Index53 -9.9dB */ 0x14800052 -}; -u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8] = { - /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x1C , 0x12 , 0x08 , 0x04}, - /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x1B , 0x11 , 0x08 , 0x04}, - /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x1A , 0x11 , 0x07 , 0x04}, - /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x19 , 0x10 , 0x07 , 0x04}, - /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x18 , 0x10 , 0x07 , 0x03}, - /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x18 , 0x0F , 0x07 , 0x03}, - /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x17 , 0x0F , 0x06 , 0x03}, - /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x16 , 0x0E , 0x06 , 0x03}, - /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x15 , 0x0E , 0x06 , 0x03}, - /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x14 , 0x0D , 0x06 , 0x03}, - /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x14 , 0x0D , 0x06 , 0x03}, - /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x13 , 0x0C , 0x05 , 0x03}, - /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x12 , 0x0C , 0x05 , 0x03}, - /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x12 , 0x0B , 0x05 , 0x03}, - /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, - /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, - /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x10 , 0x0A , 0x05 , 0x02}, - /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x10 , 0x0A , 0x04 , 0x02}, - /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x0F , 0x0A , 0x04 , 0x02}, - /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x0E , 0x09 , 0x04 , 0x02}, - /* Index20 -6.0dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x0E , 0x09 , 0x04 , 0x02}, // 20 This is CCK base index - /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x0E , 0x09 , 0x04 , 0x02}, - /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x0D , 0x08 , 0x04 , 0x02}, - /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x0D , 0x08 , 0x04 , 0x02}, - /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x0C , 0x08 , 0x03 , 0x02}, - /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x0C , 0x08 , 0x03 , 0x02}, - /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, - /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, - /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x0B , 0x07 , 0x03 , 0x02}, - /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x0A , 0x07 , 0x03 , 0x01}, - /* Index30 -9.0dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, // 30 This is hp CCK base index - /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, - /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x09 , 0x06 , 0x03 , 0x01}, - /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x09 , 0x06 , 0x03 , 0x01}, - /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x09 , 0x06 , 0x02 , 0x01}, - /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, - /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, - /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x08 , 0x05 , 0x02 , 0x01}, - /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, - /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, - /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, - /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, - /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, - /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x06 , 0x04 , 0x02 , 0x01}, - /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x05 , 0x03 , 0x02 , 0x01}, - /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, - /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x04 , 0x03 , 0x01 , 0x01} -}; -u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8] = { - /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index20 -6 dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index30 -9 dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, - /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00} -}; -#endif - -#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1) -u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] = -{ - 0x081, // 0, -12.0dB - 0x088, // 1, -11.5dB - 0x090, // 2, -11.0dB - 0x099, // 3, -10.5dB - 0x0A2, // 4, -10.0dB - 0x0AC, // 5, -9.5dB - 0x0B6, // 6, -9.0dB - 0x0C0, // 7, -8.5dB - 0x0CC, // 8, -8.0dB - 0x0D8, // 9, -7.5dB - 0x0E5, // 10, -7.0dB - 0x0F2, // 11, -6.5dB - 0x101, // 12, -6.0dB - 0x110, // 13, -5.5dB - 0x120, // 14, -5.0dB - 0x131, // 15, -4.5dB - 0x143, // 16, -4.0dB - 0x156, // 17, -3.5dB - 0x16A, // 18, -3.0dB - 0x180, // 19, -2.5dB - 0x197, // 20, -2.0dB - 0x1AF, // 21, -1.5dB - 0x1C8, // 22, -1.0dB - 0x1E3, // 23, -0.5dB - 0x200, // 24, +0 dB - 0x21E, // 25, +0.5dB - 0x23E, // 26, +1.0dB - 0x261, // 27, +1.5dB - 0x285, // 28, +2.0dB - 0x2AB, // 29, +2.5dB - 0x2D3, // 30, +3.0dB - 0x2FE, // 31, +3.5dB - 0x32B, // 32, +4.0dB - 0x35C, // 33, +4.5dB - 0x38E, // 34, +5.0dB - 0x3C4, // 35, +5.5dB - 0x3FE // 36, +6.0dB -}; -#elif(ODM_IC_11AC_SERIES_SUPPORT) -u4Byte OFDMSwingTable_8812[OFDM_TABLE_SIZE_8812] = { - 0x3FE, // 0, (6dB) - 0x3C4, // 1, (5.5dB) - 0x38E, // 2, (5dB) - 0x35C, // 3, (4.5dB) - 0x32B, // 4, (4dB) - 0x2FE, // 5, (3.5dB) - 0x2D3, // 6, (3dB) - 0x2AB, // 7, (2.5dB) - 0x285, // 8, (2dB) - 0x261, // 9, (1.5dB - 0x23E, // 10, (1dB) - 0x21E, // 11, (0.5dB) - 0x200, // 12, (0dB) 8814 int PA 2G default - 0x1E3, // 13, (-0.5dB) - 0x1C8, // 14, (-1dB) - 0x1AF, // 15, (-1.5dB) - 0x197, // 16, (-2dB) - 0x180, // 17, (-2.5dB) - 0x16A, // 18, (-3dB) 8812 / 8814 int PA 5G / 8814 ext PA 2G5G default - 0x156, // 19, (-3.5dB) - 0x143, // 20, (-4dB) 8812 HP default - 0x131, // 21, (-4.5dB) - 0x120, // 22, (-5dB) - 0x110, // 23, (-5.5dB) - 0x101, // 24, (-6dB) - 0x0F2, // 25, (-6.5dB) - 0x0E5, // 26, (-7dB) - 0x0D8, // 27, (-7.5dB) - 0x0CC, // 28, (-8dB) - 0x0C0, // 29, (-8.5dB) - 0x0B6, // 30, (-9dB) - 0x0AC, // 31, (-9.5dB) - 0x0A2, // 32, (-10dB) - 0x099, // 33, (-10.5dB) - 0x090, // 34, (-11dB) - 0x088, // 35, (-11.5dB) - 0x081, // 36, (-12dB) - 0x079, // 37, (-12.5dB) - 0x072, // 38, (-13dB) - 0x06c, // 39, (-13.5dB) - 0x066, // 40, (-14dB) - 0x060, // 41, (-14.5dB) - 0x05B // 42, (-15dB) -}; -#endif - -u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D] = { - 0x0CD, - 0x0D9, - 0x0E6, - 0x0F3, - 0x102, - 0x111, - 0x121, - 0x132, - 0x144, - 0x158, - 0x16C, - 0x182, - 0x198, - 0x1B1, - 0x1CA, - 0x1E5, - 0x202, - 0x221, - 0x241, - 0x263, - 0x287, - 0x2AE, - 0x2D6, - 0x301, - 0x32F, - 0x35F, - 0x392, - 0x3C9, - 0x402, - 0x43F, - 0x47F, - 0x4C3, - 0x50C, - 0x558, - 0x5A9, - 0x5FF, - 0x65A, - 0x6BA, - 0x720, - 0x78C, - 0x7FF, -}; - - -//#endif -//3============================================================ -//3 Tx Power Tracking -//3============================================================ - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - if (!(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES))) - return; -#endif - - odm_TXPowerTrackingThermalMeterInit(pDM_Odm); -} - - -u1Byte -getSwingIndex( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte i = 0, BBswingMask = 0; - u4Byte bbSwing = 0; - u4Byte swingTableSize = 0; - pu4Byte pSwingTable = 0; - prtl8192cd_priv priv = pDM_Odm->priv; - -#if (RTL8197F_SUPPORT == 1) - if (GET_CHIP_VER(priv) == VERSION_8197F) { - bbSwing = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskOFDM_D); - pSwingTable = OFDMSwingTable_New; - swingTableSize = OFDM_TABLE_SIZE_92D; - BBswingMask = 22; - } -#endif - -#if (RTL8822B_SUPPORT == 1) - if (GET_CHIP_VER(priv) == VERSION_8822B) { - bbSwing = PHY_QueryBBReg(priv, rA_TxScale_Jaguar, 0xFFE00000); - pSwingTable = TxScalingTable_Jaguar; - swingTableSize = TXSCALE_TABLE_SIZE; - BBswingMask = 0; - } -#endif - - for (i = 0; i < swingTableSize-1; i++) { - u4Byte tableValue = pSwingTable[i] >> BBswingMask; - - if (bbSwing == tableValue) - break; - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("bbSwing=0x%x bbswing_index=%d\n", bbSwing, i)); - - - return i; -} - - -VOID -odm_TXPowerTrackingThermalMeterInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - prtl8192cd_priv priv = pDM_Odm->priv; - u1Byte p; - u1Byte defaultSwingIndex; -#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) - if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B)) - defaultSwingIndex = getSwingIndex(pDM_Odm); -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - pMgntInfo->bTXPowerTracking = TRUE; - pHalData->TXPowercount = 0; - pHalData->bTXPowerTrackingInit = FALSE; - - if(pDM_Odm->mp_mode == FALSE) - pHalData->TxPowerTrackControl = TRUE; - ODM_RT_TRACE(pDM_Odm,COMP_POWER_TRACKING, DBG_LOUD, ("pMgntInfo->bTXPowerTracking = %d\n", pMgntInfo->bTXPowerTracking)); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #ifdef CONFIG_RTL8188E - { - pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; - pDM_Odm->RFCalibrateInfo.TXPowercount = 0; - pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE; - - if(pDM_Odm->mp_mode == FALSE) - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; - - MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); - } - #else - { - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - - //if(IS_HARDWARE_TYPE_8192C(pHalData)) - { - pdmpriv->bTXPowerTracking = _TRUE; - pdmpriv->TXPowercount = 0; - pdmpriv->bTXPowerTrackingInit = _FALSE; - - if(pDM_Odm->mp_mode == FALSE) //for mp driver, turn off txpwrtracking as default - pdmpriv->TxPowerTrackControl = _TRUE; - - } - MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl); - - } - #endif//endif (CONFIG_RTL8188E==1) -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - - #ifdef RTL8188E_SUPPORT - { - pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; - pDM_Odm->RFCalibrateInfo.TXPowercount = 0; - pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE; - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; - pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; - } - #endif -#endif - - pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE; - pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = 0; - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = 0; - pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; - pDM_Odm->RFCalibrateInfo.ThermalValue = 0; - pRFCalibrateInfo->DefaultOfdmIndex = 28; - -#if (RTL8197F_SUPPORT == 1) - if (GET_CHIP_VER(priv) == VERSION_8197F) { - pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : defaultSwingIndex; - pRFCalibrateInfo->DefaultCckIndex = 28; - } -#endif - -#if (RTL8822B_SUPPORT == 1) - if (GET_CHIP_VER(priv) == VERSION_8822B) { - pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : defaultSwingIndex; - pRFCalibrateInfo->DefaultCckIndex = 20; - } -#endif - - -#if RTL8188E_SUPPORT - pRFCalibrateInfo->DefaultCckIndex = 20; // -6 dB -#elif RTL8192E_SUPPORT - pRFCalibrateInfo->DefaultCckIndex = 8; // -12 dB -#endif - pRFCalibrateInfo->BbSwingIdxOfdmBase = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; - pDM_Odm->RFCalibrateInfo.CCK_index = pRFCalibrateInfo->DefaultCckIndex; - - for (p = 0; p < MAX_RF_PATH; p++) { - pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->KfreeOffset[p] = 0; /* for 8814 kfree*/ - } - pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d pRFCalibrateInfo->DefaultCckIndex=%d\n", pRFCalibrateInfo->DefaultOfdmIndex , pRFCalibrateInfo->DefaultCckIndex)); - - -} - - -VOID -ODM_TXPowerTrackingCheck( - IN PVOID pDM_VOID - ) -{ - // - // For AP/ADSL use prtl8192cd_priv - // For CE/NIC use PADAPTER - // - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - - - if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) - return; - - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // - switch (pDM_Odm->SupportPlatform) - { - case ODM_WIN: - odm_TXPowerTrackingCheckMP(pDM_Odm); - break; - - case ODM_CE: - odm_TXPowerTrackingCheckCE(pDM_Odm); - break; - - case ODM_AP: - odm_TXPowerTrackingCheckAP(pDM_Odm); - break; - - case ODM_ADSL: - /*odm_DIGAP(pDM_Odm);*/ - break; - } - -} - -VOID -odm_TXPowerTrackingCheckCE( - IN PVOID pDM_VOID - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - - #if(RTL8188E_SUPPORT==1) - - //if(!pMgntInfo->bTXPowerTracking /*|| (!pdmpriv->TxPowerTrackControl && pdmpriv->bAPKdone)*/) - if(!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) - { - return; - } - - if(!pDM_Odm->RFCalibrateInfo.TM_Trigger) //at least delay 1 sec - { - //pHalData->TxPowerCheckCnt++; //cosa add for debug - ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); - //DBG_8192C("Trigger 92C Thermal Meter!!\n"); - - pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; - return; - - } - else - { - //DBG_8192C("Schedule TxPowerTracking direct call!!\n"); - odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); - pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; - } - #endif - -#endif -} - -VOID -odm_TXPowerTrackingCheckMP( - IN PVOID pDM_VOID - ) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - - if (ODM_CheckPowerStatus(Adapter) == FALSE) - return; - - if(!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE) - odm_TXPowerTrackingThermalMeterCheck(Adapter); -#endif - -} - - -VOID -odm_TXPowerTrackingCheckAP( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - prtl8192cd_priv priv = pDM_Odm->priv; - -#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B)) - ODM_TXPowerTrackingCallback_ThermalMeter(pDM_Odm); - else -#endif - { - } -#endif - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -VOID -odm_TXPowerTrackingThermalMeterCheck( - IN PADAPTER Adapter - ) -{ -#ifndef AP_BUILD_WORKAROUND -#if (HAL_CODE_BASE==RTL8192_C) - PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - static u1Byte TM_Trigger = 0; - //u1Byte TxPowerCheckCnt = 5; //10 sec - - if(!pMgntInfo->bTXPowerTracking /*|| (!pHalData->TxPowerTrackControl && pHalData->bAPKdone)*/) - { - return; - } - - if(!TM_Trigger) //at least delay 1 sec - { - if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_8812(Adapter)) - PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); - else - PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger 92C Thermal Meter!!\n")); - - TM_Trigger = 1; - return; - } - else - { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); - odm_TXPowerTrackingDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18. - TM_Trigger = 0; - } -#endif -#endif -} - -#endif - diff --git a/hal/phydm/phydm_powertracking_ap.h b/hal/phydm/phydm_powertracking_ap.h deleted file mode 100644 index de97d63..0000000 --- a/hal/phydm/phydm_powertracking_ap.h +++ /dev/null @@ -1,351 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMPOWERTRACKING_H__ -#define __PHYDMPOWERTRACKING_H__ - -#define POWRTRACKING_VERSION "1.1" - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#ifdef RTK_AC_SUPPORT -#define ODM_IC_11AC_SERIES_SUPPORT 1 -#else -#define ODM_IC_11AC_SERIES_SUPPORT 0 -#endif -#else -#define ODM_IC_11AC_SERIES_SUPPORT 1 -#endif - -#define DPK_DELTA_MAPPING_NUM 13 -#define index_mapping_HP_NUM 15 -#define DELTA_SWINGIDX_SIZE 30 -#define DELTA_SWINTSSI_SIZE 61 -#define BAND_NUM 3 -#define MAX_RF_PATH 4 -#define TXSCALE_TABLE_SIZE 37 -#define CCK_TABLE_SIZE_8723D 41 - -#define IQK_MAC_REG_NUM 4 -#define IQK_ADDA_REG_NUM 16 -#define IQK_BB_REG_NUM_MAX 10 - -#define IQK_BB_REG_NUM 9 - -#define HP_THERMAL_NUM 8 - -#define AVG_THERMAL_NUM 8 -#define IQK_Matrix_REG_NUM 8 -//#define IQK_Matrix_Settings_NUM 1+24+21 -#define IQK_Matrix_Settings_NUM (14+24+21) // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G - -#if !defined(_OUTSRC_COEXIST) -#define OFDM_TABLE_SIZE_92D 43 -#define OFDM_TABLE_SIZE 37 -#define CCK_TABLE_SIZE 33 -#define CCK_TABLE_SIZE_88F 21 - - - -//#define OFDM_TABLE_SIZE_92E 54 -//#define CCK_TABLE_SIZE_92E 54 -extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D]; -extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; - - -extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE_92D]; -extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; -extern u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16]; -extern u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16]; - -#endif - -#define ODM_OFDM_TABLE_SIZE 37 -#define ODM_CCK_TABLE_SIZE 33 -// <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. -extern u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE]; -extern u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE]; - -static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; -static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; - -//extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E]; -//extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8]; -//extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8]; - -#ifdef CONFIG_WLAN_HAL_8192EE -#define OFDM_TABLE_SIZE_92E 54 -#define CCK_TABLE_SIZE_92E 54 -extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E]; -extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8]; -extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8]; -#endif - -#define OFDM_TABLE_SIZE_8812 43 -#define AVG_THERMAL_NUM_8812 4 - -#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1) -extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; -#elif(ODM_IC_11AC_SERIES_SUPPORT) -extern unsigned int OFDMSwingTable_8812[OFDM_TABLE_SIZE_8812]; -#endif - -extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D]; - -#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck - -typedef struct _IQK_MATRIX_REGS_SETTING{ - BOOLEAN bIQKDone; - s4Byte Value[1][IQK_Matrix_REG_NUM]; -}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; - -typedef struct ODM_RF_Calibration_Structure -{ - //for tx power tracking - - u4Byte RegA24; // for TempCCK - s4Byte RegE94; - s4Byte RegE9C; - s4Byte RegEB4; - s4Byte RegEBC; - - //u1Byte bTXPowerTracking; - u1Byte TXPowercount; - BOOLEAN bTXPowerTrackingInit; - BOOLEAN bTXPowerTracking; - u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default - u1Byte TM_Trigger; - u1Byte InternalPA5G[2]; //pathA / pathB - - u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 - u1Byte ThermalValue; - u1Byte ThermalValue_LCK; - u1Byte ThermalValue_IQK; - u1Byte ThermalValue_DPK; - u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; - u1Byte ThermalValue_AVG_index; - u1Byte ThermalValue_RxGain; - u1Byte ThermalValue_Crystal; - u1Byte ThermalValue_DPKstore; - u1Byte ThermalValue_DPKtrack; - BOOLEAN TxPowerTrackingInProgress; - BOOLEAN bDPKenable; - - BOOLEAN bReloadtxpowerindex; - u1Byte bRfPiEnable; - u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug - - u1Byte bCCKinCH14; - u1Byte CCK_index; - u1Byte OFDM_index[MAX_RF_PATH]; - s1Byte PowerIndexOffset; - s1Byte DeltaPowerIndex; - s1Byte DeltaPowerIndexLast; - BOOLEAN bTxPowerChanged; - - u1Byte ThermalValue_HP[HP_THERMAL_NUM]; - u1Byte ThermalValue_HP_index; - IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; - u1Byte Delta_LCK; - u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKA[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKB[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKC[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKD[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GA[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GB[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GC[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GD[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GA[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GB[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GC[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GD[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; - - u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; - u1Byte BbSwingIdxOfdmCurrent; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; -#else - u1Byte BbSwingIdxOfdmBase; -#endif - BOOLEAN BbSwingFlagOfdm; - u1Byte BbSwingIdxCck; - u1Byte BbSwingIdxCckCurrent; - u1Byte BbSwingIdxCckBase; - u1Byte DefaultOfdmIndex; - u1Byte DefaultCckIndex; - BOOLEAN BbSwingFlagCck; - - s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; - s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; - s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH]; - s1Byte Remnant_CCKSwingIdx; - s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ - BOOLEAN Modify_TxAGC_Flag_PathA; - BOOLEAN Modify_TxAGC_Flag_PathB; - BOOLEAN Modify_TxAGC_Flag_PathC; - BOOLEAN Modify_TxAGC_Flag_PathD; - BOOLEAN Modify_TxAGC_Flag_PathA_CCK; - - s1Byte KfreeOffset[MAX_RF_PATH]; - - //--------------------------------------------------------------------// - - //for IQK - u4Byte RegC04; - u4Byte Reg874; - u4Byte RegC08; - u4Byte RegB68; - u4Byte RegB6C; - u4Byte Reg870; - u4Byte Reg860; - u4Byte Reg864; - - BOOLEAN bIQKInitialized; - BOOLEAN bLCKInProgress; - BOOLEAN bAntennaDetected; - BOOLEAN bNeedIQK; - BOOLEAN bIQKInProgress; - BOOLEAN bIQKPAoff; - u1Byte Delta_IQK; - u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; - u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; - u4Byte IQK_BB_backup_recover[9]; - u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; - u4Byte TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ - u4Byte RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ - u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ - u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ - - u8Byte IQK_StartTime; - u8Byte IQK_TotalProgressingTime; - u8Byte IQK_ProgressingTime; - u4Byte LOK_Result; - u1Byte IQKstep; - u1Byte Kcount; - u1Byte retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ - BOOLEAN isMPmode; - - //for APK - u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a - u1Byte bAPKdone; - u1Byte bAPKThermalMeterIgnore; - u1Byte bDPdone; - u1Byte bDPPathAOK; - u1Byte bDPPathBOK; - - /*Add by Yuchen for Kfree Phydm*/ - u1Byte RegRfKFreeEnable; /*for registry*/ - u1Byte RfKFreeEnable; /*for efuse enable check*/ - u4Byte TxLOK[2]; -}ODM_RF_CAL_T,*PODM_RF_CAL_T; - -VOID -odm_TXPowerTrackingCheckAP( - IN PVOID pDM_VOID - ); - -VOID -ODM_TXPowerTrackingCheck( - IN PVOID pDM_VOID - ); - - -VOID -odm_TXPowerTrackingThermalMeterInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingCheckMP( - IN PVOID pDM_VOID - ); - - -VOID -odm_TXPowerTrackingCheckCE( - IN PVOID pDM_VOID - ); - - -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - -VOID -odm_TXPowerTrackingCallbackThermalMeter92C( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingCallbackRXGainThermalMeter92D( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingCallbackThermalMeter92D( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingDirectCall92C( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingThermalMeterCheck( - IN PADAPTER Adapter - ); - -#endif - - - -#endif diff --git a/hal/phydm/phydm_powertracking_ce.c b/hal/phydm/phydm_powertracking_ce.c deleted file mode 100644 index e3bc4a9..0000000 --- a/hal/phydm/phydm_powertracking_ce.c +++ /dev/null @@ -1,756 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -/*============================================================ */ -/* include files */ -/*============================================================ */ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -//============================================================ -// Global var -//============================================================ - -u4Byte OFDMSwingTable[OFDM_TABLE_SIZE] = { - 0x7f8001fe, /* 0, +6.0dB */ - 0x788001e2, /* 1, +5.5dB */ - 0x71c001c7, /* 2, +5.0dB*/ - 0x6b8001ae, /* 3, +4.5dB*/ - 0x65400195, /* 4, +4.0dB*/ - 0x5fc0017f, /* 5, +3.5dB*/ - 0x5a400169, /* 6, +3.0dB*/ - 0x55400155, /* 7, +2.5dB*/ - 0x50800142, /* 8, +2.0dB*/ - 0x4c000130, /* 9, +1.5dB*/ - 0x47c0011f, /* 10, +1.0dB*/ - 0x43c0010f, /* 11, +0.5dB*/ - 0x40000100, /* 12, +0dB*/ - 0x3c8000f2, /* 13, -0.5dB*/ - 0x390000e4, /* 14, -1.0dB*/ - 0x35c000d7, /* 15, -1.5dB*/ - 0x32c000cb, /* 16, -2.0dB*/ - 0x300000c0, /* 17, -2.5dB*/ - 0x2d4000b5, /* 18, -3.0dB*/ - 0x2ac000ab, /* 19, -3.5dB*/ - 0x288000a2, /* 20, -4.0dB*/ - 0x26000098, /* 21, -4.5dB*/ - 0x24000090, /* 22, -5.0dB*/ - 0x22000088, /* 23, -5.5dB*/ - 0x20000080, /* 24, -6.0dB*/ - 0x1e400079, /* 25, -6.5dB*/ - 0x1c800072, /* 26, -7.0dB*/ - 0x1b00006c, /* 27. -7.5dB*/ - 0x19800066, /* 28, -8.0dB*/ - 0x18000060, /* 29, -8.5dB*/ - 0x16c0005b, /* 30, -9.0dB*/ - 0x15800056, /* 31, -9.5dB*/ - 0x14400051, /* 32, -10.0dB*/ - 0x1300004c, /* 33, -10.5dB*/ - 0x12000048, /* 34, -11.0dB*/ - 0x11000044, /* 35, -11.5dB*/ - 0x10000040, /* 36, -12.0dB*/ -}; - -u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/ - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/ - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/ - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/ - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/ - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/ - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/ - {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */ - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/ - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/ - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/ - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/ - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/ - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/ - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/ - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/ - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/ - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/ - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/ - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/ - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/ - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/ - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/ - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/ - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/ -}; - - -u1Byte CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/ - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/ - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/ - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/ - {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default*/ - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/ - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/ - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/ - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/ - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/ - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/ - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/ - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/ - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/ - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/ - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/ - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/ - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/ - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/ - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/ - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/ -}; - - -u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = { - 0x0b40002d, /* 0, -15.0dB */ - 0x0c000030, /* 1, -14.5dB*/ - 0x0cc00033, /* 2, -14.0dB*/ - 0x0d800036, /* 3, -13.5dB*/ - 0x0e400039, /* 4, -13.0dB */ - 0x0f00003c, /* 5, -12.5dB*/ - 0x10000040, /* 6, -12.0dB*/ - 0x11000044, /* 7, -11.5dB*/ - 0x12000048, /* 8, -11.0dB*/ - 0x1300004c, /* 9, -10.5dB*/ - 0x14400051, /* 10, -10.0dB*/ - 0x15800056, /* 11, -9.5dB*/ - 0x16c0005b, /* 12, -9.0dB*/ - 0x18000060, /* 13, -8.5dB*/ - 0x19800066, /* 14, -8.0dB*/ - 0x1b00006c, /* 15, -7.5dB*/ - 0x1c800072, /* 16, -7.0dB*/ - 0x1e400079, /* 17, -6.5dB*/ - 0x20000080, /* 18, -6.0dB*/ - 0x22000088, /* 19, -5.5dB*/ - 0x24000090, /* 20, -5.0dB*/ - 0x26000098, /* 21, -4.5dB*/ - 0x288000a2, /* 22, -4.0dB*/ - 0x2ac000ab, /* 23, -3.5dB*/ - 0x2d4000b5, /* 24, -3.0dB*/ - 0x300000c0, /* 25, -2.5dB*/ - 0x32c000cb, /* 26, -2.0dB*/ - 0x35c000d7, /* 27, -1.5dB*/ - 0x390000e4, /* 28, -1.0dB*/ - 0x3c8000f2, /* 29, -0.5dB*/ - 0x40000100, /* 30, +0dB*/ - 0x43c0010f, /* 31, +0.5dB*/ - 0x47c0011f, /* 32, +1.0dB*/ - 0x4c000130, /* 33, +1.5dB*/ - 0x50800142, /* 34, +2.0dB*/ - 0x55400155, /* 35, +2.5dB*/ - 0x5a400169, /* 36, +3.0dB*/ - 0x5fc0017f, /* 37, +3.5dB*/ - 0x65400195, /* 38, +4.0dB*/ - 0x6b8001ae, /* 39, +4.5dB*/ - 0x71c001c7, /* 40, +5.0dB*/ - 0x788001e2, /* 41, +5.5dB*/ - 0x7f8001fe /* 42, +6.0dB*/ -}; - - -u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - -u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - -u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - -u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = { - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/ - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/ - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/ - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/ - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/ - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/ - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/ - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/ - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/ - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/ - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/ - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/ - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/ - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/ - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/ - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/ - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/ - {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */ - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/ - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/ - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/ - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/ - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/ - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/ - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/ - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/ - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/ -}; - - -u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= { - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/ - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/ - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/ - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/ - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/ - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/ - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/ - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/ - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/ - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/ - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/ - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/ - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/ - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/ - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */ - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/ - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/ - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ - {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/ - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/ - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/ - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/ - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ -}; -u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D] = { - 0x0CD, /*0 , -20dB*/ - 0x0D9, - 0x0E6, - 0x0F3, - 0x102, - 0x111, - 0x121, - 0x132, - 0x144, - 0x158, - 0x16C, - 0x182, - 0x198, - 0x1B1, - 0x1CA, - 0x1E5, - 0x202, - 0x221, - 0x241, - 0x263, - 0x287, - 0x2AE, - 0x2D6, - 0x301, - 0x32F, - 0x35F, - 0x392, - 0x3C9, - 0x402, - 0x43F, - 0x47F, - 0x4C3, - 0x50C, - 0x558, - 0x5A9, - 0x5FF, - 0x65A, - 0x6BA, - 0x720, - 0x78C, - 0x7FF, -}; - - -u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] = -{ - 0x081, /* 0, -12.0dB*/ - 0x088, /* 1, -11.5dB*/ - 0x090, /* 2, -11.0dB*/ - 0x099, /* 3, -10.5dB*/ - 0x0A2, /* 4, -10.0dB*/ - 0x0AC, /* 5, -9.5dB*/ - 0x0B6, /* 6, -9.0dB*/ - 0x0C0, /*7, -8.5dB*/ - 0x0CC, /* 8, -8.0dB*/ - 0x0D8, /* 9, -7.5dB*/ - 0x0E5, /* 10, -7.0dB*/ - 0x0F2, /* 11, -6.5dB*/ - 0x101, /* 12, -6.0dB*/ - 0x110, /* 13, -5.5dB*/ - 0x120, /* 14, -5.0dB*/ - 0x131, /* 15, -4.5dB*/ - 0x143, /* 16, -4.0dB*/ - 0x156, /* 17, -3.5dB*/ - 0x16A, /* 18, -3.0dB*/ - 0x180, /* 19, -2.5dB*/ - 0x197, /* 20, -2.0dB*/ - 0x1AF, /* 21, -1.5dB*/ - 0x1C8, /* 22, -1.0dB*/ - 0x1E3, /* 23, -0.5dB*/ - 0x200, /* 24, +0 dB*/ - 0x21E, /* 25, +0.5dB*/ - 0x23E, /* 26, +1.0dB*/ - 0x261, /* 27, +1.5dB*/ - 0x285,/* 28, +2.0dB*/ - 0x2AB, /* 29, +2.5dB*/ - 0x2D3, /*30, +3.0dB*/ - 0x2FE, /* 31, +3.5dB*/ - 0x32B, /* 32, +4.0dB*/ - 0x35C, /* 33, +4.5dB*/ - 0x38E, /* 34, +5.0dB*/ - 0x3C4, /* 35, +5.5dB*/ - 0x3FE /* 36, +6.0dB */ -}; - -#ifdef AP_BUILD_WORKAROUND - -unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { - /* +6.0dB */ 0x7f8001fe, - /* +5.5dB */ 0x788001e2, - /* +5.0dB */ 0x71c001c7, - /* +4.5dB */ 0x6b8001ae, - /* +4.0dB */ 0x65400195, - /* +3.5dB */ 0x5fc0017f, - /* +3.0dB */ 0x5a400169, - /* +2.5dB */ 0x55400155, - /* +2.0dB */ 0x50800142, - /* +1.5dB */ 0x4c000130, - /* +1.0dB */ 0x47c0011f, - /* +0.5dB */ 0x43c0010f, - /* 0.0dB */ 0x40000100, - /* -0.5dB */ 0x3c8000f2, - /* -1.0dB */ 0x390000e4, - /* -1.5dB */ 0x35c000d7, - /* -2.0dB */ 0x32c000cb, - /* -2.5dB */ 0x300000c0, - /* -3.0dB */ 0x2d4000b5, - /* -3.5dB */ 0x2ac000ab, - /* -4.0dB */ 0x288000a2, - /* -4.5dB */ 0x26000098, - /* -5.0dB */ 0x24000090, - /* -5.5dB */ 0x22000088, - /* -6.0dB */ 0x20000080, - /* -6.5dB */ 0x1a00006c, - /* -7.0dB */ 0x1c800072, - /* -7.5dB */ 0x18000060, - /* -8.0dB */ 0x19800066, - /* -8.5dB */ 0x15800056, - /* -9.0dB */ 0x26c0005b, - /* -9.5dB */ 0x14400051, - /* -10.0dB */ 0x24400051, - /* -10.5dB */ 0x1300004c, - /* -11.0dB */ 0x12000048, - /* -11.5dB */ 0x11000044, - /* -12.0dB */ 0x10000040 -}; -#endif - - - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - if (!(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_IC_11N_SERIES))) - return; -#endif - - odm_TXPowerTrackingThermalMeterInit(pDM_Odm); -} - -u1Byte -getSwingIndex( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte i = 0; - u4Byte bbSwing; - u4Byte swingTableSize; - pu4Byte pSwingTable; - - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B - || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8703B - ) { - bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000); - - pSwingTable = OFDMSwingTable_New; - swingTableSize = OFDM_TABLE_SIZE; - } else { -#if ((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1)) - if (pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8821) - { - bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A); - pSwingTable = TxScalingTable_Jaguar; - swingTableSize = TXSCALE_TABLE_SIZE; - } - else -#endif - { - bbSwing = 0; - pSwingTable = OFDMSwingTable; - swingTableSize = OFDM_TABLE_SIZE; - } - } - - for (i = 0; i < swingTableSize; ++i) { - u4Byte tableValue = pSwingTable[i]; - - if (tableValue >= 0x100000 ) - tableValue >>= 22; - if (bbSwing == tableValue) - break; - } - return i; -} - -VOID -odm_TXPowerTrackingThermalMeterInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm); - u1Byte p = 0; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - if(pDM_Odm->mp_mode == FALSE) - pHalData->TxPowerTrackControl = TRUE; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - pRFCalibrateInfo->bTXPowerTracking = _TRUE; - pRFCalibrateInfo->TXPowercount = 0; - pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; - - if(pDM_Odm->mp_mode == FALSE) - pRFCalibrateInfo->TxPowerTrackControl = _TRUE; - else - pRFCalibrateInfo->TxPowerTrackControl = _FALSE; - - if(pDM_Odm->mp_mode == FALSE) - pRFCalibrateInfo->TxPowerTrackControl = _TRUE; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pDM_Odm TxPowerTrackControl = %d\n", pRFCalibrateInfo->TxPowerTrackControl)); - -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #ifdef RTL8188E_SUPPORT - { - pRFCalibrateInfo->bTXPowerTracking = _TRUE; - pRFCalibrateInfo->TXPowercount = 0; - pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; - pRFCalibrateInfo->TxPowerTrackControl = _TRUE; - } - #endif -#endif - - //pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE; - pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; - pRFCalibrateInfo->ThermalValue_IQK = pHalData->EEPROMThermalMeter; - pRFCalibrateInfo->ThermalValue_LCK = pHalData->EEPROMThermalMeter; - - if (pRFCalibrateInfo->DefaultBbSwingIndexFlag != TRUE) { - /*The index of "0 dB" in SwingTable.*/ - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B || - pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8703B) { - pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex; - pRFCalibrateInfo->DefaultCckIndex = 20; - } else if (pDM_Odm->SupportICType == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ - pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/ - pRFCalibrateInfo->DefaultCckIndex = 20; /*CCK:-6dB*/ - } else if (pDM_Odm->SupportICType == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ - pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/ - pRFCalibrateInfo->DefaultCckIndex = 28; /*CCK: -6dB*/ - } else { - pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex; - pRFCalibrateInfo->DefaultCckIndex = 24; - } - pRFCalibrateInfo->DefaultBbSwingIndexFlag = TRUE; - } - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; - pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->DefaultCckIndex; - - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) - { - pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->DeltaPowerIndex[p] = 0; - pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - } - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM = 0; - pRFCalibrateInfo->Modify_TxAGC_Value_CCK = 0; - -} - - -VOID -ODM_TXPowerTrackingCheck( - IN PVOID pDM_VOID - ) -{ - /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - at the same time. In the stage2/3, we need to prive universal interface and merge all - HW dynamic mechanism. */ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - switch (pDM_Odm->SupportPlatform) - { - case ODM_WIN: - odm_TXPowerTrackingCheckMP(pDM_Odm); - break; - - case ODM_CE: - odm_TXPowerTrackingCheckCE(pDM_Odm); - break; - - case ODM_AP: - odm_TXPowerTrackingCheckAP(pDM_Odm); - break; - - default: - break; - } - -} - -VOID -odm_TXPowerTrackingCheckCE( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - - if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) - return; - - if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { - - if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) - || IS_HARDWARE_TYPE_8723B(Adapter) - || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) - || IS_HARDWARE_TYPE_8703B(Adapter) - ) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16), 0x03); - } else { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_OLD, bRFRegOffsetMask, 0x60); - } - - - - pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; - return; - } - else - { - - ODM_TXPowerTrackingCallback_ThermalMeter(Adapter); - pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; - } - -#endif -} - -VOID -odm_TXPowerTrackingCheckMP( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - - if (ODM_CheckPowerStatus(Adapter) == FALSE) - { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n")); - return; - } - - odm_TXPowerTrackingThermalMeterCheck(Adapter); -#endif - -} - - -VOID -odm_TXPowerTrackingCheckAP( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - prtl8192cd_priv priv = pDM_Odm->priv; - - return; - -#endif -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -VOID -odm_TXPowerTrackingThermalMeterCheck( - IN PADAPTER Adapter - ) -{ -#ifndef AP_BUILD_WORKAROUND - static u1Byte TM_Trigger = 0; - - if (!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK)) { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, - ("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n")); - return; - } - - if (!TM_Trigger) { - if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) || - IS_HARDWARE_TYPE_8723B(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) - || IS_HARDWARE_TYPE_8703B(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter)) - PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); - else - PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); - - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n")); - - TM_Trigger = 1; - return; - } else { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); - odm_TXPowerTrackingDirectCall(Adapter); - TM_Trigger = 0; - } -#endif -} -#endif - - diff --git a/hal/phydm/phydm_powertracking_ce.h b/hal/phydm/phydm_powertracking_ce.h deleted file mode 100644 index 015b048..0000000 --- a/hal/phydm/phydm_powertracking_ce.h +++ /dev/null @@ -1,334 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMPOWERTRACKING_H__ -#define __PHYDMPOWERTRACKING_H__ - -#define POWRTRACKING_VERSION "1.1" - -#define DPK_DELTA_MAPPING_NUM 13 -#define index_mapping_HP_NUM 15 -#define OFDM_TABLE_SIZE 43 -#define CCK_TABLE_SIZE 33 -#define CCK_TABLE_SIZE_88F 21 -#define TXSCALE_TABLE_SIZE 37 -#define CCK_TABLE_SIZE_8723D 41 - -#define TXPWR_TRACK_TABLE_SIZE 30 -#define DELTA_SWINGIDX_SIZE 30 -#define DELTA_SWINTSSI_SIZE 61 -#define BAND_NUM 4 - -#define AVG_THERMAL_NUM 8 -#define HP_THERMAL_NUM 8 -#define IQK_MAC_REG_NUM 4 -#define IQK_ADDA_REG_NUM 16 -#define IQK_BB_REG_NUM_MAX 10 - -#define IQK_BB_REG_NUM 9 - - - -#define IQK_Matrix_REG_NUM 8 -#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G - -extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE]; -extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; - -extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE]; -extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; -extern u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16]; -extern u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16]; -extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D]; - -extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; - -// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. -static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; -static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; - -#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck - -typedef struct _IQK_MATRIX_REGS_SETTING{ - BOOLEAN bIQKDone; - s4Byte Value[3][IQK_Matrix_REG_NUM]; - BOOLEAN bBWIqkResultSaved[3]; -}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; - -typedef struct ODM_RF_Calibration_Structure -{ - //for tx power tracking - - u4Byte RegA24; // for TempCCK - s4Byte RegE94; - s4Byte RegE9C; - s4Byte RegEB4; - s4Byte RegEBC; - - u1Byte TXPowercount; - BOOLEAN bTXPowerTrackingInit; - BOOLEAN bTXPowerTracking; - u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default - u1Byte TM_Trigger; - u1Byte InternalPA5G[2]; //pathA / pathB - - u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 - u1Byte ThermalValue; - u1Byte ThermalValue_LCK; - u1Byte ThermalValue_IQK; - u1Byte ThermalValue_DPK; - u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; - u1Byte ThermalValue_AVG_index; - u1Byte ThermalValue_RxGain; - u1Byte ThermalValue_Crystal; - u1Byte ThermalValue_DPKstore; - u1Byte ThermalValue_DPKtrack; - BOOLEAN TxPowerTrackingInProgress; - - BOOLEAN bReloadtxpowerindex; - u1Byte bRfPiEnable; - u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug - - - //------------------------- Tx power Tracking -------------------------// - u1Byte bCCKinCH14; - u1Byte CCK_index; - u1Byte OFDM_index[MAX_RF_PATH]; - s1Byte PowerIndexOffset[MAX_RF_PATH]; - s1Byte DeltaPowerIndex[MAX_RF_PATH]; - s1Byte DeltaPowerIndexLast[MAX_RF_PATH]; - BOOLEAN bTxPowerChanged; - s1Byte XtalOffset; - s1Byte XtalOffsetLast; - - u1Byte ThermalValue_HP[HP_THERMAL_NUM]; - u1Byte ThermalValue_HP_index; - IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; - u1Byte Delta_LCK; - s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB - u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKA[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKB[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKC[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKD[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GA[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GB[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GC[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GD[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GA[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GB[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GC[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GD[BAND_NUM][DELTA_SWINTSSI_SIZE]; - s1Byte DeltaSwingTableXtal_P[DELTA_SWINGIDX_SIZE]; - s1Byte DeltaSwingTableXtal_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; - - u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; - u1Byte BbSwingIdxOfdmCurrent; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; -#else - u1Byte BbSwingIdxOfdmBase; -#endif - BOOLEAN DefaultBbSwingIndexFlag; - BOOLEAN BbSwingFlagOfdm; - u1Byte BbSwingIdxCck; - u1Byte BbSwingIdxCckCurrent; - u1Byte BbSwingIdxCckBase; - u1Byte DefaultOfdmIndex; - u1Byte DefaultCckIndex; - BOOLEAN BbSwingFlagCck; - - s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; - s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; - s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH]; - s1Byte Remnant_CCKSwingIdx; - s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ - BOOLEAN Modify_TxAGC_Flag_PathA; - BOOLEAN Modify_TxAGC_Flag_PathB; - BOOLEAN Modify_TxAGC_Flag_PathC; - BOOLEAN Modify_TxAGC_Flag_PathD; - BOOLEAN Modify_TxAGC_Flag_PathA_CCK; - - s1Byte KfreeOffset[MAX_RF_PATH]; - - //--------------------------------------------------------------------// - - //for IQK - u4Byte RegC04; - u4Byte Reg874; - u4Byte RegC08; - u4Byte RegB68; - u4Byte RegB6C; - u4Byte Reg870; - u4Byte Reg860; - u4Byte Reg864; - - BOOLEAN bIQKInitialized; - BOOLEAN bLCKInProgress; - BOOLEAN bAntennaDetected; - BOOLEAN bNeedIQK; - BOOLEAN bIQKInProgress; - BOOLEAN bIQKPAoff; - u1Byte Delta_IQK; - u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; - u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; - u4Byte IQK_BB_backup_recover[9]; - u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; - u4Byte TxIQC_8723B[2][3][2]; // { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} - u4Byte RxIQC_8723B[2][2][2]; // { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} - u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ - u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ - u4Byte TxIQC_8723D[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ - u4Byte RxIQC_8723D[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ - - u1Byte IQKstep; - u1Byte Kcount; - u1Byte retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ - BOOLEAN isMPmode; - - - - // IQK time measurement - u8Byte IQK_StartTime; - u8Byte IQK_ProgressingTime; - u8Byte IQK_TotalProgressingTime; - - u4Byte LOK_Result; - - //for APK - u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a - u1Byte bAPKdone; - u1Byte bAPKThermalMeterIgnore; - - // DPK - BOOLEAN bDPKFail; - u1Byte bDPdone; - u1Byte bDPPathAOK; - u1Byte bDPPathBOK; - - u4Byte TxLOK[2]; - u4Byte DpkTxAGC; - s4Byte DpkGain; - u4Byte DpkThermal[4]; - s1Byte Modify_TxAGC_Value_OFDM; - s1Byte Modify_TxAGC_Value_CCK; - - /*Add by Yuchen for Kfree Phydm*/ - u1Byte RegRfKFreeEnable; /*for registry*/ - u1Byte RfKFreeEnable; /*for efuse enable check*/ - -}ODM_RF_CAL_T,*PODM_RF_CAL_T; - - -VOID -ODM_TXPowerTrackingCheck( - IN PVOID pDM_VOID - ); - - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingCheckAP( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingThermalMeterInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingCheckMP( - IN PVOID pDM_VOID - ); - - -VOID -odm_TXPowerTrackingCheckCE( - IN PVOID pDM_VOID - ); - -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - -VOID -odm_TXPowerTrackingCallbackThermalMeter92C( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingCallbackRXGainThermalMeter92D( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingCallbackThermalMeter92D( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingDirectCall92C( - IN PADAPTER Adapter - ); - -VOID -odm_TXPowerTrackingThermalMeterCheck( - IN PADAPTER Adapter - ); - -#endif - -#endif diff --git a/hal/phydm/phydm_powertracking_win.c b/hal/phydm/phydm_powertracking_win.c deleted file mode 100644 index 15a243b..0000000 --- a/hal/phydm/phydm_powertracking_win.c +++ /dev/null @@ -1,788 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" - -//============================================================ -// Global var -//============================================================ - -u4Byte OFDMSwingTable[OFDM_TABLE_SIZE] = { - 0x7f8001fe, // 0, +6.0dB - 0x788001e2, // 1, +5.5dB - 0x71c001c7, // 2, +5.0dB - 0x6b8001ae, // 3, +4.5dB - 0x65400195, // 4, +4.0dB - 0x5fc0017f, // 5, +3.5dB - 0x5a400169, // 6, +3.0dB - 0x55400155, // 7, +2.5dB - 0x50800142, // 8, +2.0dB - 0x4c000130, // 9, +1.5dB - 0x47c0011f, // 10, +1.0dB - 0x43c0010f, // 11, +0.5dB - 0x40000100, // 12, +0dB - 0x3c8000f2, // 13, -0.5dB - 0x390000e4, // 14, -1.0dB - 0x35c000d7, // 15, -1.5dB - 0x32c000cb, // 16, -2.0dB - 0x300000c0, // 17, -2.5dB - 0x2d4000b5, // 18, -3.0dB - 0x2ac000ab, // 19, -3.5dB - 0x288000a2, // 20, -4.0dB - 0x26000098, // 21, -4.5dB - 0x24000090, // 22, -5.0dB - 0x22000088, // 23, -5.5dB - 0x20000080, // 24, -6.0dB - 0x1e400079, // 25, -6.5dB - 0x1c800072, // 26, -7.0dB - 0x1b00006c, // 27. -7.5dB - 0x19800066, // 28, -8.0dB - 0x18000060, // 29, -8.5dB - 0x16c0005b, // 30, -9.0dB - 0x15800056, // 31, -9.5dB - 0x14400051, // 32, -10.0dB - 0x1300004c, // 33, -10.5dB - 0x12000048, // 34, -11.0dB - 0x11000044, // 35, -11.5dB - 0x10000040, // 36, -12.0dB -}; - -u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB - {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB <== default - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB -}; - - -u1Byte CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB - {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB <== default - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB -}; - - -u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = { - 0x0b40002d, // 0, -15.0dB - 0x0c000030, // 1, -14.5dB - 0x0cc00033, // 2, -14.0dB - 0x0d800036, // 3, -13.5dB - 0x0e400039, // 4, -13.0dB - 0x0f00003c, // 5, -12.5dB - 0x10000040, // 6, -12.0dB - 0x11000044, // 7, -11.5dB - 0x12000048, // 8, -11.0dB - 0x1300004c, // 9, -10.5dB - 0x14400051, // 10, -10.0dB - 0x15800056, // 11, -9.5dB - 0x16c0005b, // 12, -9.0dB - 0x18000060, // 13, -8.5dB - 0x19800066, // 14, -8.0dB - 0x1b00006c, // 15, -7.5dB - 0x1c800072, // 16, -7.0dB - 0x1e400079, // 17, -6.5dB - 0x20000080, // 18, -6.0dB - 0x22000088, // 19, -5.5dB - 0x24000090, // 20, -5.0dB - 0x26000098, // 21, -4.5dB - 0x288000a2, // 22, -4.0dB - 0x2ac000ab, // 23, -3.5dB - 0x2d4000b5, // 24, -3.0dB - 0x300000c0, // 25, -2.5dB - 0x32c000cb, // 26, -2.0dB - 0x35c000d7, // 27, -1.5dB - 0x390000e4, // 28, -1.0dB - 0x3c8000f2, // 29, -0.5dB - 0x40000100, // 30, +0dB - 0x43c0010f, // 31, +0.5dB - 0x47c0011f, // 32, +1.0dB - 0x4c000130, // 33, +1.5dB - 0x50800142, // 34, +2.0dB - 0x55400155, // 35, +2.5dB - 0x5a400169, // 36, +3.0dB - 0x5fc0017f, // 37, +3.5dB - 0x65400195, // 38, +4.0dB - 0x6b8001ae, // 39, +4.5dB - 0x71c001c7, // 40, +5.0dB - 0x788001e2, // 41, +5.5dB - 0x7f8001fe // 42, +6.0dB -}; - - -u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - -u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - -u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { -{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -}; - - - - -u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = { - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB - {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 20, -6.0dB - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB -}; - - -u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= { - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB - {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB -}; -u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D] = { - 0x0CD, - 0x0D9, - 0x0E6, - 0x0F3, - 0x102, - 0x111, - 0x121, - 0x132, - 0x144, - 0x158, - 0x16C, - 0x182, - 0x198, - 0x1B1, - 0x1CA, - 0x1E5, - 0x202, - 0x221, - 0x241, - 0x263, - 0x287, - 0x2AE, - 0x2D6, - 0x301, - 0x32F, - 0x35F, - 0x392, - 0x3C9, - 0x402, - 0x43F, - 0x47F, - 0x4C3, - 0x50C, - 0x558, - 0x5A9, - 0x5FF, - 0x65A, - 0x6BA, - 0x720, - 0x78C, - 0x7FF, -}; - - -u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] = -{ - 0x081, // 0, -12.0dB - 0x088, // 1, -11.5dB - 0x090, // 2, -11.0dB - 0x099, // 3, -10.5dB - 0x0A2, // 4, -10.0dB - 0x0AC, // 5, -9.5dB - 0x0B6, // 6, -9.0dB - 0x0C0, // 7, -8.5dB - 0x0CC, // 8, -8.0dB - 0x0D8, // 9, -7.5dB - 0x0E5, // 10, -7.0dB - 0x0F2, // 11, -6.5dB - 0x101, // 12, -6.0dB - 0x110, // 13, -5.5dB - 0x120, // 14, -5.0dB - 0x131, // 15, -4.5dB - 0x143, // 16, -4.0dB - 0x156, // 17, -3.5dB - 0x16A, // 18, -3.0dB - 0x180, // 19, -2.5dB - 0x197, // 20, -2.0dB - 0x1AF, // 21, -1.5dB - 0x1C8, // 22, -1.0dB - 0x1E3, // 23, -0.5dB - 0x200, // 24, +0 dB - 0x21E, // 25, +0.5dB - 0x23E, // 26, +1.0dB - 0x261, // 27, +1.5dB - 0x285, // 28, +2.0dB - 0x2AB, // 29, +2.5dB - 0x2D3, // 30, +3.0dB - 0x2FE, // 31, +3.5dB - 0x32B, // 32, +4.0dB - 0x35C, // 33, +4.5dB - 0x38E, // 34, +5.0dB - 0x3C4, // 35, +5.5dB - 0x3FE // 36, +6.0dB -}; -u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3 -, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; -u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4 -, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; - - -#ifdef AP_BUILD_WORKAROUND - -unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { - /* +6.0dB */ 0x7f8001fe, - /* +5.5dB */ 0x788001e2, - /* +5.0dB */ 0x71c001c7, - /* +4.5dB */ 0x6b8001ae, - /* +4.0dB */ 0x65400195, - /* +3.5dB */ 0x5fc0017f, - /* +3.0dB */ 0x5a400169, - /* +2.5dB */ 0x55400155, - /* +2.0dB */ 0x50800142, - /* +1.5dB */ 0x4c000130, - /* +1.0dB */ 0x47c0011f, - /* +0.5dB */ 0x43c0010f, - /* 0.0dB */ 0x40000100, - /* -0.5dB */ 0x3c8000f2, - /* -1.0dB */ 0x390000e4, - /* -1.5dB */ 0x35c000d7, - /* -2.0dB */ 0x32c000cb, - /* -2.5dB */ 0x300000c0, - /* -3.0dB */ 0x2d4000b5, - /* -3.5dB */ 0x2ac000ab, - /* -4.0dB */ 0x288000a2, - /* -4.5dB */ 0x26000098, - /* -5.0dB */ 0x24000090, - /* -5.5dB */ 0x22000088, - /* -6.0dB */ 0x20000080, - /* -6.5dB */ 0x1a00006c, - /* -7.0dB */ 0x1c800072, - /* -7.5dB */ 0x18000060, - /* -8.0dB */ 0x19800066, - /* -8.5dB */ 0x15800056, - /* -9.0dB */ 0x26c0005b, - /* -9.5dB */ 0x14400051, - /* -10.0dB */ 0x24400051, - /* -10.5dB */ 0x1300004c, - /* -11.0dB */ 0x12000048, - /* -11.5dB */ 0x11000044, - /* -12.0dB */ 0x10000040 -}; - -#endif - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - if(!(pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_IC_11N_SERIES|ODM_RTL8822B))) - return; -#endif - - odm_TXPowerTrackingThermalMeterInit(pDM_Odm); -} - -u1Byte -getSwingIndex( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte i = 0; - u4Byte bbSwing; - u4Byte swingTableSize; - pu4Byte pSwingTable; - - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B || - pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8703B) - { - bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000); - - pSwingTable = OFDMSwingTable_New; - swingTableSize = OFDM_TABLE_SIZE; - } else { - bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A); - pSwingTable = TxScalingTable_Jaguar; - swingTableSize = TXSCALE_TABLE_SIZE; - } - - for (i = 0; i < swingTableSize; ++i) { - u4Byte tableValue = pSwingTable[i]; - - if (tableValue >= 0x100000 ) - tableValue >>= 22; - if (bbSwing == tableValue) - break; - } - return i; -} - -VOID -odm_TXPowerTrackingThermalMeterInit( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm); - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte p = 0; - - if(pDM_Odm->mp_mode == FALSE) - pRFCalibrateInfo->TxPowerTrackControl = TRUE; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #ifdef CONFIG_RTL8188E - { - pRFCalibrateInfo->bTXPowerTracking = _TRUE; - pRFCalibrateInfo->TXPowercount = 0; - pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; - - if(pDM_Odm->mp_mode == FALSE) - pRFCalibrateInfo->TxPowerTrackControl = _TRUE; - - MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pRFCalibrateInfo->TxPowerTrackControl); - } - #else - { - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - - pdmpriv->bTXPowerTracking = _TRUE; - pdmpriv->TXPowercount = 0; - pdmpriv->bTXPowerTrackingInit = _FALSE; - - if(pDM_Odm->mp_mode == FALSE) - pdmpriv->TxPowerTrackControl = _TRUE; - - MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl); - - } - #endif -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #ifdef RTL8188E_SUPPORT - { - pRFCalibrateInfo->bTXPowerTracking = _TRUE; - pRFCalibrateInfo->TXPowercount = 0; - pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; - pRFCalibrateInfo->TxPowerTrackControl = _TRUE; - } - #endif -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #if (MP_DRIVER == 1) - pRFCalibrateInfo->TxPowerTrackControl = FALSE; - #else - pRFCalibrateInfo->TxPowerTrackControl = TRUE; - #endif -#else - pRFCalibrateInfo->TxPowerTrackControl = TRUE; -#endif - - pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; - pRFCalibrateInfo->ThermalValue_IQK = pHalData->EEPROMThermalMeter; - pRFCalibrateInfo->ThermalValue_LCK = pHalData->EEPROMThermalMeter; - - if (pRFCalibrateInfo->DefaultBbSwingIndexFlag != TRUE) { - /*The index of "0 dB" in SwingTable.*/ - if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B || - pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8703B) { - pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex; - pRFCalibrateInfo->DefaultCckIndex = 20; - } else if (pDM_Odm->SupportICType == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ - pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/ - pRFCalibrateInfo->DefaultCckIndex = 20; /*CCK:-6dB*/ - } else if (pDM_Odm->SupportICType == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ - pRFCalibrateInfo->DefaultOfdmIndex = 28; /*OFDM: -1dB*/ - pRFCalibrateInfo->DefaultCckIndex = 28; /*CCK: -6dB*/ - } else { - pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex; - pRFCalibrateInfo->DefaultCckIndex = 24; - } - pRFCalibrateInfo->DefaultBbSwingIndexFlag = TRUE; - } - - pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; - pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->DefaultCckIndex; - - for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) - { - pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; - pRFCalibrateInfo->DeltaPowerIndex[p] = 0; - pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; - pRFCalibrateInfo->PowerIndexOffset[p] = 0; - pRFCalibrateInfo->KfreeOffset[p] = 0; - } - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM = 0; - pRFCalibrateInfo->Modify_TxAGC_Value_CCK = 0; - -} - - -VOID -ODM_TXPowerTrackingCheck( - IN PVOID pDM_VOID - ) -{ - - /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism.*/ - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - switch (pDM_Odm->SupportPlatform) - { - case ODM_WIN: - odm_TXPowerTrackingCheckMP(pDM_Odm); - break; - - case ODM_CE: - odm_TXPowerTrackingCheckCE(pDM_Odm); - break; - - case ODM_AP: - odm_TXPowerTrackingCheckAP(pDM_Odm); - break; - - default: - break; - } - -} - -VOID -odm_TXPowerTrackingCheckCE( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PADAPTER Adapter = pDM_Odm->Adapter; - #if ((RTL8188F_SUPPORT == 1)) - rtl8192c_odm_CheckTXPowerTracking(Adapter); - #endif - - #if(RTL8188E_SUPPORT==1) - - if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) { - return; - } - - if (!pRFCalibrateInfo->TM_Trigger) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); - /*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/ - - pRFCalibrateInfo->TM_Trigger = 1; - return; - - } else { - /*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/ - odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); - pRFCalibrateInfo->TM_Trigger = 0; - } - #endif -#endif -} - -VOID -odm_TXPowerTrackingCheckMP( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PADAPTER Adapter = pDM_Odm->Adapter; - - if (*pDM_Odm->pIsFcsModeEnable) - return; - - if (ODM_CheckPowerStatus(Adapter) == FALSE) - { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n")); - return; - } - - if (IS_HARDWARE_TYPE_8821B(Adapter)) /* TODO: Don't Do PowerTracking*/ - return; - - odm_TXPowerTrackingThermalMeterCheck(Adapter); - - -#endif - -} - - -VOID -odm_TXPowerTrackingCheckAP( - IN PVOID pDM_VOID - ) -{ -return; - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -VOID -odm_TXPowerTrackingDirectCall( - IN PADAPTER Adapter - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - - ODM_TXPowerTrackingCallback_ThermalMeter(Adapter); -} - -VOID -odm_TXPowerTrackingThermalMeterCheck( - IN PADAPTER Adapter - ) -{ -#ifndef AP_BUILD_WORKAROUND - static u1Byte TM_Trigger = 0; - - if (!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK)) - { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, - ("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n")); - return; - } - - if (!TM_Trigger) - { - if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) || - IS_HARDWARE_TYPE_8723B(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8703B(Adapter) - || IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter)) - PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); - else - PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); - - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n")); - - TM_Trigger = 1; - return; - } else { - RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); - odm_TXPowerTrackingDirectCall(Adapter); - TM_Trigger = 0; - } -#endif -} - -#endif - - diff --git a/hal/phydm/phydm_powertracking_win.h b/hal/phydm/phydm_powertracking_win.h deleted file mode 100644 index 3ee9dc1..0000000 --- a/hal/phydm/phydm_powertracking_win.h +++ /dev/null @@ -1,299 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMPOWERTRACKING_H__ -#define __PHYDMPOWERTRACKING_H__ - -#define POWRTRACKING_VERSION "1.1" - -#define DPK_DELTA_MAPPING_NUM 13 -#define index_mapping_HP_NUM 15 -#define TXSCALE_TABLE_SIZE 37 -#define CCK_TABLE_SIZE_8723D 41 -#define TXPWR_TRACK_TABLE_SIZE 30 -#define DELTA_SWINGIDX_SIZE 30 -#define DELTA_SWINTSSI_SIZE 61 -#define BAND_NUM 3 -#define MAX_RF_PATH 4 -#define CCK_TABLE_SIZE_88F 21 - - -#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck - -#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G -#define AVG_THERMAL_NUM 8 -#define HP_THERMAL_NUM 8 -#define IQK_Matrix_REG_NUM 8 -#define IQK_MAC_REG_NUM 4 -#define IQK_ADDA_REG_NUM 16 - -#define IQK_BB_REG_NUM 9 - - -extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE]; -extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; - -extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE]; -extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; -extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; -extern u1Byte CCKSwingTable_Ch1_Ch13_88F[CCK_TABLE_SIZE_88F][16]; -extern u1Byte CCKSwingTable_Ch14_88F[CCK_TABLE_SIZE_88F][16]; -extern u4Byte CCKSwingTable_Ch1_Ch14_8723D[CCK_TABLE_SIZE_8723D]; - -extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; - -// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. -static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; -static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; - -VOID -ODM_TXPowerTrackingCheck( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingCheckAP( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingThermalMeterInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingInit( - IN PVOID pDM_VOID - ); - -VOID -odm_TXPowerTrackingCheckMP( - IN PVOID pDM_VOID - ); - - -VOID -odm_TXPowerTrackingCheckCE( - IN PVOID pDM_VOID - ); - -#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - - -VOID -odm_TXPowerTrackingThermalMeterCheck( - IN PADAPTER Adapter - ); - -#endif - -typedef struct _IQK_MATRIX_REGS_SETTING{ - BOOLEAN bIQKDone; - s4Byte Value[3][IQK_Matrix_REG_NUM]; - BOOLEAN bBWIqkResultSaved[3]; -}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; - -typedef struct ODM_RF_Calibration_Structure -{ - //for tx power tracking - - u4Byte RegA24; // for TempCCK - s4Byte RegE94; - s4Byte RegE9C; - s4Byte RegEB4; - s4Byte RegEBC; - //u1Byte bTXPowerTracking; - u1Byte TXPowercount; - BOOLEAN bTXPowerTrackingInit; - BOOLEAN bTXPowerTracking; - u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default - u1Byte TM_Trigger; - u1Byte InternalPA5G[2]; //pathA / pathB - - u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 - u1Byte ThermalValue; - u1Byte ThermalValue_LCK; - u1Byte ThermalValue_IQK; - u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; - u1Byte ThermalValue_AVG_index; - u1Byte ThermalValue_RxGain; - - BOOLEAN bReloadtxpowerindex; - u1Byte bRfPiEnable; - u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug - - - //------------------------- Tx power Tracking -------------------------// - u1Byte bCCKinCH14; - u1Byte CCK_index; - u1Byte OFDM_index[MAX_RF_PATH]; - s1Byte PowerIndexOffset[MAX_RF_PATH]; - s1Byte DeltaPowerIndex[MAX_RF_PATH]; - s1Byte DeltaPowerIndexLast[MAX_RF_PATH]; - BOOLEAN bTxPowerChanged; - s1Byte XtalOffset; - s1Byte XtalOffsetLast; - - u1Byte ThermalValue_HP[HP_THERMAL_NUM]; - u1Byte ThermalValue_HP_index; - IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; - u1Byte Delta_LCK; - s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB - u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKA[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKB[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKC[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GCCKD[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GA[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GB[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GC[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_2GD[DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GA[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GB[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GC[BAND_NUM][DELTA_SWINTSSI_SIZE]; - u1Byte DeltaSwingTSSITable_5GD[BAND_NUM][DELTA_SWINTSSI_SIZE]; - s1Byte DeltaSwingTableXtal_P[DELTA_SWINGIDX_SIZE]; - s1Byte DeltaSwingTableXtal_N[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; - u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; - - u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; - u1Byte BbSwingIdxOfdmCurrent; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; -#else - u1Byte BbSwingIdxOfdmBase; -#endif - BOOLEAN DefaultBbSwingIndexFlag; - BOOLEAN BbSwingFlagOfdm; - u1Byte BbSwingIdxCck; - u1Byte BbSwingIdxCckCurrent; - u1Byte BbSwingIdxCckBase; - u1Byte DefaultOfdmIndex; - u1Byte DefaultCckIndex; - BOOLEAN BbSwingFlagCck; - - s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; - s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; - s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH]; - s1Byte Remnant_CCKSwingIdx; - s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ - BOOLEAN Modify_TxAGC_Flag_PathA; - BOOLEAN Modify_TxAGC_Flag_PathB; - BOOLEAN Modify_TxAGC_Flag_PathC; - BOOLEAN Modify_TxAGC_Flag_PathD; - BOOLEAN Modify_TxAGC_Flag_PathA_CCK; - - s1Byte KfreeOffset[MAX_RF_PATH]; - - //--------------------------------------------------------------------// - - //for IQK - u4Byte RegC04; - u4Byte Reg874; - u4Byte RegC08; - u4Byte RegB68; - u4Byte RegB6C; - u4Byte Reg870; - u4Byte Reg860; - u4Byte Reg864; - - BOOLEAN bIQKInitialized; - BOOLEAN bLCKInProgress; - BOOLEAN bAntennaDetected; - BOOLEAN bNeedIQK; - BOOLEAN bIQKInProgress; - BOOLEAN bIQKPAoff; - u1Byte Delta_IQK; - u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; - u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; - u4Byte IQK_BB_backup_recover[9]; - u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; - u4Byte TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ - u4Byte RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ - u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ - u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ - u4Byte TxIQC_8723D[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ - u4Byte RxIQC_8723D[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ - - u8Byte IQK_StartTime; - u8Byte IQK_TotalProgressingTime; - u8Byte IQK_ProgressingTime; - u4Byte LOK_Result; - u1Byte IQKstep; - u1Byte Kcount; - u1Byte retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ - BOOLEAN isMPmode; - - //for APK - u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a - u1Byte bAPKdone; - u1Byte bAPKThermalMeterIgnore; - - // DPK - BOOLEAN bDPKFail; - u1Byte bDPdone; - u1Byte bDPPathAOK; - u1Byte bDPPathBOK; - - u4Byte TxLOK[2]; - u4Byte DpkTxAGC; - s4Byte DpkGain; - u4Byte DpkThermal[4]; - - s1Byte Modify_TxAGC_Value_OFDM; - s1Byte Modify_TxAGC_Value_CCK; - - /*Add by Yuchen for Kfree Phydm*/ - u1Byte RegRfKFreeEnable; /*for registry*/ - u1Byte RfKFreeEnable; /*for efuse enable check*/ - - HALMAC_PWR_TRACKING_OPTION HALMAC_PWR_TRACKING_INFO; -}ODM_RF_CAL_T,*PODM_RF_CAL_T; - - - - -#endif diff --git a/hal/phydm/phydm_pre_define.h b/hal/phydm/phydm_pre_define.h index 95a8708..91dc0c1 100644 --- a/hal/phydm/phydm_pre_define.h +++ b/hal/phydm/phydm_pre_define.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ @@ -21,46 +31,45 @@ * 1 Definition * 1 ============================================================ */ -#define PHYDM_CODE_BASE "PHYDM_v017" -#define PHYDM_RELEASE_DATE "20170306" +#define PHYDM_CODE_BASE "PHYDM_V024" +#define PHYDM_RELEASE_DATE "20171213" + +/*PHYDM API status*/ +#define PHYDM_SET_FAIL 0 +#define PHYDM_SET_SUCCESS 1 +#define PHYDM_SET_NO_NEED 3 + +/*PHYDM Set/Revert*/ +#define PHYDM_SET 1 +#define PHYDM_REVERT 2 /* Max path of IC */ +/*N-IC*/ #define MAX_PATH_NUM_8188E 1 -#define MAX_PATH_NUM_8192E 2 -#define MAX_PATH_NUM_8723B 1 -#define MAX_PATH_NUM_8812A 2 -#define MAX_PATH_NUM_8821A 1 -#define MAX_PATH_NUM_8814A 4 -#define MAX_PATH_NUM_8822B 2 -#define MAX_PATH_NUM_8821B 2 -#define MAX_PATH_NUM_8703B 1 #define MAX_PATH_NUM_8188F 1 +#define MAX_PATH_NUM_8710B 1 +#define MAX_PATH_NUM_8723B 1 #define MAX_PATH_NUM_8723D 1 +#define MAX_PATH_NUM_8703B 1 +#define MAX_PATH_NUM_8192E 2 +#define MAX_PATH_NUM_8192F 2 #define MAX_PATH_NUM_8197F 2 +#define MAX_PATH_NUM_8198F 4 +/*AC-IC*/ +#define MAX_PATH_NUM_8821A 1 +#define MAX_PATH_NUM_8881A 1 #define MAX_PATH_NUM_8821C 1 -/* JJ ADD 20161014 */ -#define MAX_PATH_NUM_8710B 1 +#define MAX_PATH_NUM_8195B 1 +#define MAX_PATH_NUM_8812A 2 +#define MAX_PATH_NUM_8822B 2 +#define MAX_PATH_NUM_8822C 2 +#define MAX_PATH_NUM_8814A 4 +#define MAX_PATH_NUM_8814B 4 +#define MAX_PATH_NUM_8814C 4 /* Max RF path */ -#define ODM_RF_PATH_MAX 2 -#define ODM_RF_PATH_MAX_JAGUAR 4 - -/*Bit define path*/ -#define PHYDM_A BIT(0) -#define PHYDM_B BIT(1) -#define PHYDM_C BIT(2) -#define PHYDM_D BIT(3) -#define PHYDM_AB (BIT(0) | BIT(1)) -#define PHYDM_AC (BIT(0) | BIT(2)) -#define PHYDM_AD (BIT(0) | BIT(3)) -#define PHYDM_BC (BIT(1) | BIT(2)) -#define PHYDM_BD (BIT(1) | BIT(3)) -#define PHYDM_CD (BIT(2) | BIT(3)) -#define PHYDM_ABC (BIT(0) | BIT(1) | BIT(2)) -#define PHYDM_ABD (BIT(0) | BIT(1) | BIT(3)) -#define PHYDM_ACD (BIT(0) | BIT(2) | BIT(3)) -#define PHYDM_BCD (BIT(1) | BIT(2) | BIT(3)) -#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define PHYDM_MAX_RF_PATH_N 2 /*For old N-series IC*/ +#define PHYDM_MAX_RF_PATH 4 /* number of entry */ #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) @@ -77,34 +86,30 @@ #define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1) #endif -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - #define RX_SMOOTH_FACTOR 20 -#endif - /* -----MGN rate--------------------------------- */ enum ODM_MGN_RATE { ODM_MGN_1M = 0x02, ODM_MGN_2M = 0x04, - ODM_MGN_5_5M = 0x0B, + ODM_MGN_5_5M = 0x0B, ODM_MGN_6M = 0x0C, ODM_MGN_9M = 0x12, - ODM_MGN_11M = 0x16, - ODM_MGN_12M = 0x18, - ODM_MGN_18M = 0x24, - ODM_MGN_24M = 0x30, - ODM_MGN_36M = 0x48, - ODM_MGN_48M = 0x60, - ODM_MGN_54M = 0x6C, + ODM_MGN_11M = 0x16, + ODM_MGN_12M = 0x18, + ODM_MGN_18M = 0x24, + ODM_MGN_24M = 0x30, + ODM_MGN_36M = 0x48, + ODM_MGN_48M = 0x60, + ODM_MGN_54M = 0x6C, ODM_MGN_MCS32 = 0x7F, - ODM_MGN_MCS0, + ODM_MGN_MCS0 = 0x80, ODM_MGN_MCS1, ODM_MGN_MCS2, ODM_MGN_MCS3, ODM_MGN_MCS4, ODM_MGN_MCS5, ODM_MGN_MCS6, - ODM_MGN_MCS7, + ODM_MGN_MCS7 = 0x87, ODM_MGN_MCS8, ODM_MGN_MCS9, ODM_MGN_MCS10, @@ -113,7 +118,7 @@ enum ODM_MGN_RATE { ODM_MGN_MCS13, ODM_MGN_MCS14, ODM_MGN_MCS15, - ODM_MGN_MCS16, + ODM_MGN_MCS16 = 0x90, ODM_MGN_MCS17, ODM_MGN_MCS18, ODM_MGN_MCS19, @@ -121,7 +126,7 @@ enum ODM_MGN_RATE { ODM_MGN_MCS21, ODM_MGN_MCS22, ODM_MGN_MCS23, - ODM_MGN_MCS24, + ODM_MGN_MCS24 = 0x98, ODM_MGN_MCS25, ODM_MGN_MCS26, ODM_MGN_MCS27, @@ -129,7 +134,7 @@ enum ODM_MGN_RATE { ODM_MGN_MCS29, ODM_MGN_MCS30, ODM_MGN_MCS31, - ODM_MGN_VHT1SS_MCS0, + ODM_MGN_VHT1SS_MCS0 = 0xa0, ODM_MGN_VHT1SS_MCS1, ODM_MGN_VHT1SS_MCS2, ODM_MGN_VHT1SS_MCS3, @@ -139,27 +144,27 @@ enum ODM_MGN_RATE { ODM_MGN_VHT1SS_MCS7, ODM_MGN_VHT1SS_MCS8, ODM_MGN_VHT1SS_MCS9, - ODM_MGN_VHT2SS_MCS0, - ODM_MGN_VHT2SS_MCS1, + ODM_MGN_VHT2SS_MCS0 = 0xaa, + ODM_MGN_VHT2SS_MCS1 = 0xab, ODM_MGN_VHT2SS_MCS2, ODM_MGN_VHT2SS_MCS3, ODM_MGN_VHT2SS_MCS4, - ODM_MGN_VHT2SS_MCS5, - ODM_MGN_VHT2SS_MCS6, + ODM_MGN_VHT2SS_MCS5 = 0xaf, + ODM_MGN_VHT2SS_MCS6 = 0xb0, ODM_MGN_VHT2SS_MCS7, ODM_MGN_VHT2SS_MCS8, - ODM_MGN_VHT2SS_MCS9, - ODM_MGN_VHT3SS_MCS0, + ODM_MGN_VHT2SS_MCS9 = 0xb3, + ODM_MGN_VHT3SS_MCS0 = 0xb4, ODM_MGN_VHT3SS_MCS1, ODM_MGN_VHT3SS_MCS2, ODM_MGN_VHT3SS_MCS3, ODM_MGN_VHT3SS_MCS4, ODM_MGN_VHT3SS_MCS5, ODM_MGN_VHT3SS_MCS6, - ODM_MGN_VHT3SS_MCS7, - ODM_MGN_VHT3SS_MCS8, - ODM_MGN_VHT3SS_MCS9, - ODM_MGN_VHT4SS_MCS0, + ODM_MGN_VHT3SS_MCS7 = 0xbb, + ODM_MGN_VHT3SS_MCS8 = 0xbc, + ODM_MGN_VHT3SS_MCS9 = 0xbd, + ODM_MGN_VHT4SS_MCS0 = 0xbe, ODM_MGN_VHT4SS_MCS1, ODM_MGN_VHT4SS_MCS2, ODM_MGN_VHT4SS_MCS3, @@ -168,7 +173,7 @@ enum ODM_MGN_RATE { ODM_MGN_VHT4SS_MCS6, ODM_MGN_VHT4SS_MCS7, ODM_MGN_VHT4SS_MCS8, - ODM_MGN_VHT4SS_MCS9, + ODM_MGN_VHT4SS_MCS9 = 0xc7, ODM_MGN_UNKNOWN }; @@ -195,93 +200,94 @@ enum ODM_MGN_RATE { #define ODM_RATEMCS32 0x20 -/* CCK Rates, TxHT = 0 */ -#define ODM_RATE1M 0x00 -#define ODM_RATE2M 0x01 -#define ODM_RATE5_5M 0x02 -#define ODM_RATE11M 0x03 +enum phydm_ctrl_info_rate { + ODM_RATE1M = 0x00, + ODM_RATE2M = 0x01, + ODM_RATE5_5M = 0x02, + ODM_RATE11M = 0x03, /* OFDM Rates, TxHT = 0 */ -#define ODM_RATE6M 0x04 -#define ODM_RATE9M 0x05 -#define ODM_RATE12M 0x06 -#define ODM_RATE18M 0x07 -#define ODM_RATE24M 0x08 -#define ODM_RATE36M 0x09 -#define ODM_RATE48M 0x0A -#define ODM_RATE54M 0x0B + ODM_RATE6M = 0x04, + ODM_RATE9M = 0x05, + ODM_RATE12M = 0x06, + ODM_RATE18M = 0x07, + ODM_RATE24M = 0x08, + ODM_RATE36M = 0x09, + ODM_RATE48M = 0x0A, + ODM_RATE54M = 0x0B, /* MCS Rates, TxHT = 1 */ -#define ODM_RATEMCS0 0x0C -#define ODM_RATEMCS1 0x0D -#define ODM_RATEMCS2 0x0E -#define ODM_RATEMCS3 0x0F -#define ODM_RATEMCS4 0x10 -#define ODM_RATEMCS5 0x11 -#define ODM_RATEMCS6 0x12 -#define ODM_RATEMCS7 0x13 -#define ODM_RATEMCS8 0x14 -#define ODM_RATEMCS9 0x15 -#define ODM_RATEMCS10 0x16 -#define ODM_RATEMCS11 0x17 -#define ODM_RATEMCS12 0x18 -#define ODM_RATEMCS13 0x19 -#define ODM_RATEMCS14 0x1A -#define ODM_RATEMCS15 0x1B -#define ODM_RATEMCS16 0x1C -#define ODM_RATEMCS17 0x1D -#define ODM_RATEMCS18 0x1E -#define ODM_RATEMCS19 0x1F -#define ODM_RATEMCS20 0x20 -#define ODM_RATEMCS21 0x21 -#define ODM_RATEMCS22 0x22 -#define ODM_RATEMCS23 0x23 -#define ODM_RATEMCS24 0x24 -#define ODM_RATEMCS25 0x25 -#define ODM_RATEMCS26 0x26 -#define ODM_RATEMCS27 0x27 -#define ODM_RATEMCS28 0x28 -#define ODM_RATEMCS29 0x29 -#define ODM_RATEMCS30 0x2A -#define ODM_RATEMCS31 0x2B -#define ODM_RATEVHTSS1MCS0 0x2C -#define ODM_RATEVHTSS1MCS1 0x2D -#define ODM_RATEVHTSS1MCS2 0x2E -#define ODM_RATEVHTSS1MCS3 0x2F -#define ODM_RATEVHTSS1MCS4 0x30 -#define ODM_RATEVHTSS1MCS5 0x31 -#define ODM_RATEVHTSS1MCS6 0x32 -#define ODM_RATEVHTSS1MCS7 0x33 -#define ODM_RATEVHTSS1MCS8 0x34 -#define ODM_RATEVHTSS1MCS9 0x35 -#define ODM_RATEVHTSS2MCS0 0x36 -#define ODM_RATEVHTSS2MCS1 0x37 -#define ODM_RATEVHTSS2MCS2 0x38 -#define ODM_RATEVHTSS2MCS3 0x39 -#define ODM_RATEVHTSS2MCS4 0x3A -#define ODM_RATEVHTSS2MCS5 0x3B -#define ODM_RATEVHTSS2MCS6 0x3C -#define ODM_RATEVHTSS2MCS7 0x3D -#define ODM_RATEVHTSS2MCS8 0x3E -#define ODM_RATEVHTSS2MCS9 0x3F -#define ODM_RATEVHTSS3MCS0 0x40 -#define ODM_RATEVHTSS3MCS1 0x41 -#define ODM_RATEVHTSS3MCS2 0x42 -#define ODM_RATEVHTSS3MCS3 0x43 -#define ODM_RATEVHTSS3MCS4 0x44 -#define ODM_RATEVHTSS3MCS5 0x45 -#define ODM_RATEVHTSS3MCS6 0x46 -#define ODM_RATEVHTSS3MCS7 0x47 -#define ODM_RATEVHTSS3MCS8 0x48 -#define ODM_RATEVHTSS3MCS9 0x49 -#define ODM_RATEVHTSS4MCS0 0x4A -#define ODM_RATEVHTSS4MCS1 0x4B -#define ODM_RATEVHTSS4MCS2 0x4C -#define ODM_RATEVHTSS4MCS3 0x4D -#define ODM_RATEVHTSS4MCS4 0x4E -#define ODM_RATEVHTSS4MCS5 0x4F -#define ODM_RATEVHTSS4MCS6 0x50 -#define ODM_RATEVHTSS4MCS7 0x51 -#define ODM_RATEVHTSS4MCS8 0x52 -#define ODM_RATEVHTSS4MCS9 0x53 + ODM_RATEMCS0 = 0x0C, + ODM_RATEMCS1 = 0x0D, + ODM_RATEMCS2 = 0x0E, + ODM_RATEMCS3 = 0x0F, + ODM_RATEMCS4 = 0x10, + ODM_RATEMCS5 = 0x11, + ODM_RATEMCS6 = 0x12, + ODM_RATEMCS7 = 0x13, + ODM_RATEMCS8 = 0x14, + ODM_RATEMCS9 = 0x15, + ODM_RATEMCS10 = 0x16, + ODM_RATEMCS11 = 0x17, + ODM_RATEMCS12 = 0x18, + ODM_RATEMCS13 = 0x19, + ODM_RATEMCS14 = 0x1A, + ODM_RATEMCS15 = 0x1B, + ODM_RATEMCS16 = 0x1C, + ODM_RATEMCS17 = 0x1D, + ODM_RATEMCS18 = 0x1E, + ODM_RATEMCS19 = 0x1F, + ODM_RATEMCS20 = 0x20, + ODM_RATEMCS21 = 0x21, + ODM_RATEMCS22 = 0x22, + ODM_RATEMCS23 = 0x23, + ODM_RATEMCS24 = 0x24, + ODM_RATEMCS25 = 0x25, + ODM_RATEMCS26 = 0x26, + ODM_RATEMCS27 = 0x27, + ODM_RATEMCS28 = 0x28, + ODM_RATEMCS29 = 0x29, + ODM_RATEMCS30 = 0x2A, + ODM_RATEMCS31 = 0x2B, + ODM_RATEVHTSS1MCS0 = 0x2C, + ODM_RATEVHTSS1MCS1 = 0x2D, + ODM_RATEVHTSS1MCS2 = 0x2E, + ODM_RATEVHTSS1MCS3 = 0x2F, + ODM_RATEVHTSS1MCS4 = 0x30, + ODM_RATEVHTSS1MCS5 = 0x31, + ODM_RATEVHTSS1MCS6 = 0x32, + ODM_RATEVHTSS1MCS7 = 0x33, + ODM_RATEVHTSS1MCS8 = 0x34, + ODM_RATEVHTSS1MCS9 = 0x35, + ODM_RATEVHTSS2MCS0 = 0x36, + ODM_RATEVHTSS2MCS1 = 0x37, + ODM_RATEVHTSS2MCS2 = 0x38, + ODM_RATEVHTSS2MCS3 = 0x39, + ODM_RATEVHTSS2MCS4 = 0x3A, + ODM_RATEVHTSS2MCS5 = 0x3B, + ODM_RATEVHTSS2MCS6 = 0x3C, + ODM_RATEVHTSS2MCS7 = 0x3D, + ODM_RATEVHTSS2MCS8 = 0x3E, + ODM_RATEVHTSS2MCS9 = 0x3F, + ODM_RATEVHTSS3MCS0 = 0x40, + ODM_RATEVHTSS3MCS1 = 0x41, + ODM_RATEVHTSS3MCS2 = 0x42, + ODM_RATEVHTSS3MCS3 = 0x43, + ODM_RATEVHTSS3MCS4 = 0x44, + ODM_RATEVHTSS3MCS5 = 0x45, + ODM_RATEVHTSS3MCS6 = 0x46, + ODM_RATEVHTSS3MCS7 = 0x47, + ODM_RATEVHTSS3MCS8 = 0x48, + ODM_RATEVHTSS3MCS9 = 0x49, + ODM_RATEVHTSS4MCS0 = 0x4A, + ODM_RATEVHTSS4MCS1 = 0x4B, + ODM_RATEVHTSS4MCS2 = 0x4C, + ODM_RATEVHTSS4MCS3 = 0x4D, + ODM_RATEVHTSS4MCS4 = 0x4E, + ODM_RATEVHTSS4MCS5 = 0x4F, + ODM_RATEVHTSS4MCS6 = 0x50, + ODM_RATEVHTSS4MCS7 = 0x51, + ODM_RATEVHTSS4MCS8 = 0x52, + ODM_RATEVHTSS4MCS9 = 0x53, +}; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) @@ -311,15 +317,17 @@ enum ODM_MGN_RATE { /* ODM_CMNINFO_INTERFACE */ -enum odm_interface_e { +enum odm_interface { ODM_ITRF_PCIE = 0x1, ODM_ITRF_USB = 0x2, ODM_ITRF_SDIO = 0x4, ODM_ITRF_ALL = 0x7, }; -/* ODM_CMNINFO_IC_TYPE */ -enum odm_ic_type_e { + +/*========[Run time IC flag] ===============================================================================]*/ + +enum phydm_ic { ODM_RTL8188E = BIT(0), ODM_RTL8812 = BIT(1), ODM_RTL8821 = BIT(2), @@ -338,39 +346,57 @@ enum odm_ic_type_e { ODM_RTL8198F = BIT(15), ODM_RTL8710B = BIT(16), ODM_RTL8192F = BIT(17), - ODM_RTL8822C = BIT(18) + ODM_RTL8822C = BIT(18), + ODM_RTL8195B = BIT(19) }; -/*========[Run time ic flag] ===============================================================================]*/ - +#define ODM_IC_N_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A | ODM_RTL8710B) #define ODM_IC_N_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F) +#define ODM_IC_N_3SS 0 +#define ODM_IC_N_4SS (ODM_RTL8198F) + +#define ODM_IC_AC_1SS (ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | ODM_RTL8195B) #define ODM_IC_AC_2SS (ODM_RTL8812 | ODM_RTL8822B | ODM_RTL8822C) +#define ODM_IC_AC_3SS 0 +#define ODM_IC_AC_4SS (ODM_RTL8814A | ODM_RTL8814B) -#define ODM_IC_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | ODM_RTL8195A | ODM_RTL8710B) +/*====the following macro DO NOT need to update when adding a new IC======= */ +#define ODM_IC_1SS (ODM_IC_N_1SS | ODM_IC_AC_1SS) #define ODM_IC_2SS (ODM_IC_N_2SS | ODM_IC_AC_2SS) -#define ODM_IC_3SS (ODM_RTL8814A) -#define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F) - -#define ODM_IC_11N_SERIES (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B) -#define ODM_IC_11AC_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8821C) - -#define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A) -#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C) - -#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) -#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B) -#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C) -#define ODM_IC_PHY_STATUE_NEW_TYPE (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B) - -#define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F) -#define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) - -#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) -#define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B) -#define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B) - - -/*========[AC/N Support] ===============================================================================]*/ +#define ODM_IC_3SS (ODM_IC_N_3SS | ODM_IC_AC_3SS) +#define ODM_IC_4SS (ODM_IC_N_4SS | ODM_IC_AC_4SS) + +#define PHYDM_IC_ABOVE_1SS (ODM_IC_1SS | ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS) +#define PHYDM_IC_ABOVE_2SS (ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS) +#define PHYDM_IC_ABOVE_3SS (ODM_IC_3SS | ODM_IC_4SS) +#define PHYDM_IC_ABOVE_4SS ODM_IC_4SS + +#define ODM_IC_11N_SERIES (ODM_IC_N_1SS | ODM_IC_N_2SS | ODM_IC_N_3SS | ODM_IC_N_4SS) +#define ODM_IC_11AC_SERIES (ODM_IC_AC_1SS | ODM_IC_AC_2SS | ODM_IC_AC_3SS | ODM_IC_AC_4SS) +/*====================================================*/ + +#define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A) +#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B) +/*[EDCCA]*/ +#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B) +#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C) +#define ODM_IC_GAIN_IDX_EDCCA (ODM_IC_11N_GAIN_IDX_EDCCA | ODM_IC_11AC_GAIN_IDX_EDCCA) +/*[Phy status type]*/ +#define PHYSTS_2ND_TYPE_IC (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B) +#define PHYSTS_3RD_TYPE_IC (ODM_RTL8198F | ODM_RTL8814B) +/*[FW Type]*/ +#define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F) +#define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F) +/*[LA mode]*/ +#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F) +/*[BF]*/ +#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F) +#define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B | ODM_RTL8195B | ODM_RTL8198F) +#define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B | ODM_RTL8198F) + + +/*========[Compile time IC flag] ===============================================================================]*/ +/*========[AC/N Support] ===========================*/ #if (DM_ODM_SUPPORT_TYPE == ODM_AP) #ifdef RTK_AC_SUPPORT @@ -380,21 +406,18 @@ enum odm_ic_type_e { #endif #define ODM_IC_11N_SERIES_SUPPORT 1 - #define ODM_CONFIG_BT_COEXIST 0 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) #define ODM_IC_11AC_SERIES_SUPPORT 1 #define ODM_IC_11N_SERIES_SUPPORT 1 - #define ODM_CONFIG_BT_COEXIST 1 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) #define ODM_IC_11AC_SERIES_SUPPORT 1 #define ODM_IC_11N_SERIES_SUPPORT 1 - #define ODM_CONFIG_BT_COEXIST 1 -#else +#else /*ODM_CE*/ #if ((RTL8188E_SUPPORT == 1) || \ (RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \ @@ -405,18 +428,50 @@ enum odm_ic_type_e { #define ODM_IC_11N_SERIES_SUPPORT 0 #define ODM_IC_11AC_SERIES_SUPPORT 1 #endif +#endif - #ifdef CONFIG_BT_COEXIST - #define ODM_CONFIG_BT_COEXIST 1 - #else - #define ODM_CONFIG_BT_COEXIST 0 - #endif +/*===IC SS Compile Flag, prepare for code size reduction==============*/ +#if ((RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) ||\ + (RTL8723D_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) ||\ + (RTL8195A_SUPPORT == 1) || (RTL8710B_SUPPORT == 1) || (RTL8195B_SUPPORT == 1)) + + #define PHYDM_COMPILE_IC_1SS +#endif +#if ((RTL8192E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) + #define PHYDM_COMPILE_IC_2SS #endif +/*#define PHYDM_COMPILE_IC_3SS*/ -/*========[New Phy-Status Support] =========================================================================]*/ +#if ((RTL8814B_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8198F_SUPPORT == 1)) + #define PHYDM_COMPILE_IC_4SS +#endif + +/*==[ABOVE N-SS COMPILE FLAG]=============================*/ +#if (defined(PHYDM_COMPILE_IC_1SS) || defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) + #define PHYDM_COMPILE_ABOVE_1SS +#endif + +#if (defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) + #define PHYDM_COMPILE_ABOVE_2SS +#endif +#if (defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) + #define PHYDM_COMPILE_ABOVE_3SS +#endif + +#if (defined(PHYDM_COMPILE_IC_4SS)) + #define PHYDM_COMPILE_ABOVE_4SS +#endif + +/*========[New Phy-Status Support] =========================================================================]*/ +#if (RTL8824B_SUPPORT == 1) + #define CONFIG_PHYSTS_3RD_TYPE 1 +#else + #define CONFIG_PHYSTS_3RD_TYPE 0 +#endif + #if ((RTL8197F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8710B_SUPPORT == 1) ) #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1 #else @@ -425,16 +480,55 @@ enum odm_ic_type_e { /*==================================================================================================]*/ +#if ((RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) +#define PHYDM_COMMON_API_SUPPORT +#endif + + +#define CCK_RATE_NUM 4 +#define OFDM_RATE_NUM 8 + +#define LEGACY_RATE_NUM 12 + +#define HT_RATE_NUM_4SS 32 +#define VHT_RATE_NUM_4SS 40 + +#define HT_RATE_NUM_3SS 24 +#define VHT_RATE_NUM_3SS 30 + +#define HT_RATE_NUM_2SS 16 +#define VHT_RATE_NUM_2SS 20 + +#define HT_RATE_NUM_1SS 8 +#define VHT_RATE_NUM_1SS 10 + +#if (defined(PHYDM_COMPILE_ABOVE_4SS)) + #define HT_RATE_NUM HT_RATE_NUM_4SS + #define VHT_RATE_NUM VHT_RATE_NUM_4SS +#elif (defined(PHYDM_COMPILE_ABOVE_3SS)) + #define HT_RATE_NUM HT_RATE_NUM_3SS + #define VHT_RATE_NUM VHT_RATE_NUM_3SS +#elif (defined(PHYDM_COMPILE_ABOVE_2SS)) + #define HT_RATE_NUM HT_RATE_NUM_2SS + #define VHT_RATE_NUM VHT_RATE_NUM_2SS +#else + #define HT_RATE_NUM HT_RATE_NUM_1SS + #define VHT_RATE_NUM VHT_RATE_NUM_1SS +#endif + +#define LOW_BW_RATE_NUM VHT_RATE_NUM + /* ODM_CMNINFO_CUT_VER */ -enum odm_cut_version_e { +enum odm_cut_version { ODM_CUT_A = 0, ODM_CUT_B = 1, ODM_CUT_C = 2, ODM_CUT_D = 3, ODM_CUT_E = 4, ODM_CUT_F = 5, - + ODM_CUT_G = 6, + ODM_CUT_H = 7, ODM_CUT_I = 8, ODM_CUT_J = 9, ODM_CUT_K = 10, @@ -442,59 +536,13 @@ enum odm_cut_version_e { }; /* ODM_CMNINFO_FAB_VER */ -enum odm_fab_e { +enum odm_fab { ODM_TSMC = 0, ODM_UMC = 1, }; -/* ODM_CMNINFO_RF_TYPE - * - * For example 1T2R (A+AB = BIT(0)|BIT(4)|BIT(5)) - * */ -enum odm_rf_path_e { - ODM_RF_A = BIT(0), - ODM_RF_B = BIT(1), - ODM_RF_C = BIT(2), - ODM_RF_D = BIT(3), -}; - -enum odm_rf_tx_num_e { - ODM_1T = 1, - ODM_2T = 2, - ODM_3T = 3, - ODM_4T = 4, -}; - -enum odm_rf_type_e { - ODM_1T1R, - ODM_1T2R, - ODM_2T2R, - ODM_2T2R_GREEN, - ODM_2T3R, - ODM_2T4R, - ODM_3T3R, - ODM_3T4R, - ODM_4T4R, - ODM_XTXR -}; - - -enum odm_mac_phy_mode_e { - ODM_SMSP = 0, - ODM_DMSP = 1, - ODM_DMDP = 2, -}; - - -enum odm_bt_coexist_e { - ODM_BT_BUSY = 1, - ODM_BT_ON = 2, - ODM_BT_OFF = 3, - ODM_BT_NONE = 4, -}; - /* ODM_CMNINFO_OP_MODE */ -enum odm_operation_mode_e { +enum odm_operation_mode { ODM_NO_LINK = BIT(0), ODM_LINK = BIT(1), ODM_SCAN = BIT(2), @@ -508,7 +556,7 @@ enum odm_operation_mode_e { /* ODM_CMNINFO_WM_MODE */ #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -enum odm_wireless_mode_e { +enum odm_wireless_mode { ODM_WM_UNKNOW = 0x0, ODM_WM_B = BIT(0), ODM_WM_G = BIT(1), @@ -519,7 +567,7 @@ enum odm_wireless_mode_e { ODM_WM_AC = BIT(6), }; #else -enum odm_wireless_mode_e { +enum odm_wireless_mode { ODM_WM_UNKNOWN = 0x00,/*0x0*/ ODM_WM_A = BIT(0), /* 0x1*/ ODM_WM_B = BIT(1), /* 0x2*/ @@ -536,7 +584,7 @@ enum odm_wireless_mode_e { #endif /* ODM_CMNINFO_BAND */ -enum odm_band_type_e { +enum odm_band_type { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) ODM_BAND_2_4G = BIT(0), ODM_BAND_5G = BIT(1), @@ -550,15 +598,14 @@ enum odm_band_type_e { /* ODM_CMNINFO_SEC_CHNL_OFFSET */ -enum phydm_sec_chnl_offset_e { - +enum phydm_sec_chnl_offset { PHYDM_DONT_CARE = 0, PHYDM_BELOW = 1, PHYDM_ABOVE = 2 }; /* ODM_CMNINFO_SEC_MODE */ -enum odm_security_e { +enum odm_security { ODM_SEC_OPEN = 0, ODM_SEC_WEP40 = 1, ODM_SEC_TKIP = 2, @@ -569,21 +616,10 @@ enum odm_security_e { ODM_SEC_SMS4 = 7, }; -/* ODM_CMNINFO_BW */ -enum odm_bw_e { - ODM_BW20M = 0, - ODM_BW40M = 1, - ODM_BW80M = 2, - ODM_BW160M = 3, - ODM_BW5M = 4, - ODM_BW10M = 5, - ODM_BW_MAX = 6 -}; - /* ODM_CMNINFO_CHNL */ /* ODM_CMNINFO_BOARD_TYPE */ -enum odm_board_type_e { +enum odm_board_type { ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */ ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */ @@ -595,14 +631,14 @@ enum odm_board_type_e { ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ }; -enum odm_package_type_e { +enum odm_package_type { ODM_PACKAGE_DEFAULT = 0, ODM_PACKAGE_QFN68 = BIT(0), ODM_PACKAGE_TFBGA90 = BIT(1), ODM_PACKAGE_TFBGA79 = BIT(2), }; -enum odm_type_gpa_e { +enum odm_type_gpa { TYPE_GPA0 = 0x0000, TYPE_GPA1 = 0x0055, TYPE_GPA2 = 0x00AA, @@ -621,7 +657,7 @@ enum odm_type_gpa_e { TYPE_GPA15 = 0xFFFF, }; -enum odm_type_apa_e { +enum odm_type_apa { TYPE_APA0 = 0x0000, TYPE_APA1 = 0x0055, TYPE_APA2 = 0x00AA, @@ -640,7 +676,7 @@ enum odm_type_apa_e { TYPE_APA15 = 0xFFFF, }; -enum odm_type_glna_e { +enum odm_type_glna { TYPE_GLNA0 = 0x0000, TYPE_GLNA1 = 0x0055, TYPE_GLNA2 = 0x00AA, @@ -659,7 +695,7 @@ enum odm_type_glna_e { TYPE_GLNA15 = 0xFFFF, }; -enum odm_type_alna_e { +enum odm_type_alna { TYPE_ALNA0 = 0x0000, TYPE_ALNA1 = 0x0055, TYPE_ALNA2 = 0x00AA, @@ -678,29 +714,34 @@ enum odm_type_alna_e { TYPE_ALNA15 = 0xFFFF, }; +#define PAUSE_FAIL 0 +#define PAUSE_SUCCESS 1 -enum odm_rf_radio_path_e { - ODM_RF_PATH_A = 0, /* Radio path A */ - ODM_RF_PATH_B = 1, /* Radio path B */ - ODM_RF_PATH_C = 2, /* Radio path C */ - ODM_RF_PATH_D = 3, /* Radio path D */ - ODM_RF_PATH_AB, - ODM_RF_PATH_AC, - ODM_RF_PATH_AD, - ODM_RF_PATH_BC, - ODM_RF_PATH_BD, - ODM_RF_PATH_CD, - ODM_RF_PATH_ABC, - ODM_RF_PATH_ACD, - ODM_RF_PATH_BCD, - ODM_RF_PATH_ABCD, - /* ODM_RF_PATH_MAX, */ /* Max RF number 90 support */ -}; - -enum odm_parameter_init_e { +enum odm_parameter_init { ODM_PRE_SETTING = 0, ODM_POST_SETTING = 1, ODM_INIT_FW_SETTING }; + +enum phydm_pause_type { + PHYDM_PAUSE = 1, /*Pause & Set new value*/ + PHYDM_PAUSE_NO_SET = 2, /*Pause & Stay in current value*/ + PHYDM_RESUME = 3 +}; + +enum phydm_pause_level { + PHYDM_PAUSE_RELEASE = -1, + PHYDM_PAUSE_LEVEL_0 = 0, /* Low Priority function */ + PHYDM_PAUSE_LEVEL_1 = 1, /* Middle Priority function */ + PHYDM_PAUSE_LEVEL_2 = 2, /* High priority function (ex: Check hang function) */ + PHYDM_PAUSE_LEVEL_3 = 3, /* Debug function (the highest priority) */ + PHYDM_PAUSE_MAX_NUM = 4 +}; + +enum phydm_dis_hw_fun { + HW_FUN_DIS = 0, /*Disable a cetain HW function & backup the original value*/ + HW_FUN_RESUME = 1 /*Revert */ +}; + #endif diff --git a/hal/phydm/phydm_precomp.h b/hal/phydm/phydm_precomp.h index a2b8a90..69f8a7a 100644 --- a/hal/phydm/phydm_precomp.h +++ b/hal/phydm/phydm_precomp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __ODM_PRECOMP_H__ @@ -61,19 +71,18 @@ #include "phydm.h" #include "phydm_hwconfig.h" +#include "phydm_phystatus.h" #include "phydm_debug.h" #include "phydm_regdefine11ac.h" #include "phydm_regdefine11n.h" #include "phydm_interface.h" #include "phydm_reg.h" -#include "phydm_adc_sampling.h" - #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && !defined(DM_ODM_CE_MAC80211) void phy_set_tx_power_limit( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 *regulation, u8 *band, u8 *bandwidth, @@ -82,6 +91,25 @@ phy_set_tx_power_limit( u8 *channel, u8 *power_limit ); + +enum hal_status +rtw_phydm_fw_iqk( + struct dm_struct *dm, + u8 clear, + u8 segment +); + +enum hal_status +rtw_phydm_cfg_phy_para( + struct dm_struct *dm, + enum phydm_halmac_param config_type, + u32 offset, + u32 data, + u32 mask, + enum rf_path e_rf_path, + u32 delay_time +); + #endif #if (DM_ODM_SUPPORT_TYPE & ODM_AP) @@ -104,13 +132,16 @@ phy_set_tx_power_limit( #endif #endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#define RTL8195B_SUPPORT 0 /*Just for PHYDM API development*/ +#define RTL8198F_SUPPORT 0 /*Just for PHYDM API development*/ +#endif + #if (RTL8188E_SUPPORT == 1) #include "rtl8188e/hal8188erateadaptive.h" /* for RA,Power training */ #include "rtl8188e/halhwimg8188e_mac.h" #include "rtl8188e/halhwimg8188e_rf.h" #include "rtl8188e/halhwimg8188e_bb.h" - #include "rtl8188e/halhwimg8188e_t_fw.h" - #include "rtl8188e/halhwimg8188e_s_fw.h" #include "rtl8188e/phydm_regconfig8188e.h" #include "rtl8188e/phydm_rtl8188e.h" #include "rtl8188e/hal8188ereg.h" @@ -144,7 +175,6 @@ phy_set_tx_power_limit( #include "rtl8192e/halhwimg8192e_mac.h" #include "rtl8192e/halhwimg8192e_rf.h" #include "rtl8192e/phydm_regconfig8192e.h" - #include "rtl8192e/halhwimg8192e_fw.h" #include "rtl8192e/hal8192ereg.h" #endif #if (DM_ODM_SUPPORT_TYPE == ODM_CE) @@ -168,7 +198,6 @@ phy_set_tx_power_limit( #include "rtl8812a/halhwimg8812a_mac.h" #include "rtl8812a/halhwimg8812a_rf.h" #include "rtl8812a/phydm_regconfig8812a.h" - #include "rtl8812a/halhwimg8812a_fw.h" #include "rtl8812a/phydm_rtl8812a.h" #endif @@ -186,9 +215,6 @@ phy_set_tx_power_limit( #include "rtl8814a/halhwimg8814a_bb.h" #include "rtl8814a/version_rtl8814a.h" #include "rtl8814a/phydm_rtl8814a.h" - #if (DM_ODM_SUPPORT_TYPE != ODM_AP) - #include "rtl8814a/halhwimg8814a_fw.h" - #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #include "halrf/rtl8814a/halrf_8814a_win.h" #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) @@ -221,7 +247,6 @@ phy_set_tx_power_limit( #include "rtl8723b/halhwimg8723b_mac.h" #include "rtl8723b/halhwimg8723b_rf.h" #include "rtl8723b/halhwimg8723b_bb.h" - #include "rtl8723b/halhwimg8723b_fw.h" #include "rtl8723b/phydm_regconfig8723b.h" #include "rtl8723b/phydm_rtl8723b.h" #include "rtl8723b/hal8723breg.h" @@ -241,7 +266,6 @@ phy_set_tx_power_limit( #include "rtl8821a/halhwimg8821a_mac.h" #include "rtl8821a/halhwimg8821a_rf.h" #include "rtl8821a/halhwimg8821a_bb.h" - #include "rtl8821a/halhwimg8821a_fw.h" #include "rtl8821a/phydm_regconfig8821a.h" #include "rtl8821a/phydm_rtl8821a.h" #include "rtl8821a/version_rtl8821a.h" @@ -258,27 +282,6 @@ phy_set_tx_power_limit( #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) #include "../halmac/halmac_reg2.h" - -#define LDPC_HT_ENABLE_RX BIT(0) -#define LDPC_HT_ENABLE_TX BIT(1) -#define LDPC_HT_TEST_TX_ENABLE BIT(2) -#define LDPC_HT_CAP_TX BIT(3) - -#define STBC_HT_ENABLE_RX BIT(0) -#define STBC_HT_ENABLE_TX BIT(1) -#define STBC_HT_TEST_TX_ENABLE BIT(2) -#define STBC_HT_CAP_TX BIT(3) - - -#define LDPC_VHT_ENABLE_RX BIT(0) -#define LDPC_VHT_ENABLE_TX BIT(1) -#define LDPC_VHT_TEST_TX_ENABLE BIT(2) -#define LDPC_VHT_CAP_TX BIT(3) - -#define STBC_VHT_ENABLE_RX BIT(0) -#define STBC_VHT_ENABLE_TX BIT(1) -#define STBC_VHT_TEST_TX_ENABLE BIT(2) -#define STBC_VHT_CAP_TX BIT(3) #endif @@ -286,7 +289,6 @@ phy_set_tx_power_limit( #include "rtl8822b/halhwimg8822b_mac.h" #include "rtl8822b/halhwimg8822b_rf.h" #include "rtl8822b/halhwimg8822b_bb.h" - #include "rtl8822b/halhwimg8822b_fw.h" #include "rtl8822b/phydm_regconfig8822b.h" #include "halrf/rtl8822b/halrf_8822b.h" #include "rtl8822b/phydm_rtl8822b.h" @@ -311,7 +313,6 @@ phy_set_tx_power_limit( #include "rtl8703b/halhwimg8703b_mac.h" #include "rtl8703b/halhwimg8703b_rf.h" #include "rtl8703b/halhwimg8703b_bb.h" - #include "rtl8703b/halhwimg8703b_fw.h" #include "halrf/rtl8703b/halrf_8703b.h" #include "rtl8703b/version_rtl8703b.h" #if (DM_ODM_SUPPORT_TYPE == ODM_CE) @@ -323,7 +324,6 @@ phy_set_tx_power_limit( #include "rtl8188f/halhwimg8188f_mac.h" #include "rtl8188f/halhwimg8188f_rf.h" #include "rtl8188f/halhwimg8188f_bb.h" - #include "rtl8188f/halhwimg8188f_fw.h" #include "rtl8188f/hal8188freg.h" #include "rtl8188f/phydm_rtl8188f.h" #include "rtl8188f/phydm_regconfig8188f.h" @@ -341,7 +341,6 @@ phy_set_tx_power_limit( #include "rtl8723d/halhwimg8723d_mac.h" #include "rtl8723d/halhwimg8723d_rf.h" #include "rtl8723d/phydm_regconfig8723d.h" - #include "rtl8723d/halhwimg8723d_fw.h" #include "rtl8723d/hal8723dreg.h" #include "rtl8723d/phydm_rtl8723d.h" #include "halrf/rtl8723d/halrf_8723d.h" @@ -360,7 +359,6 @@ phy_set_tx_power_limit( #include "rtl8710b/halhwimg8710b_mac.h" #include "rtl8710b/halhwimg8710b_rf.h" #include "rtl8710b/phydm_regconfig8710b.h" - #include "rtl8710b/halhwimg8710b_fw.h" #include "rtl8710b/hal8710breg.h" #include "rtl8710b/phydm_rtl8710b.h" #include "halrf/rtl8710b/halrf_8710b.h" @@ -385,13 +383,9 @@ phy_set_tx_power_limit( #if (RTL8821C_SUPPORT == 1) #include "rtl8821c/phydm_hal_api8821c.h" - #include "rtl8821c/halhwimg8821c_testchip_mac.h" - #include "rtl8821c/halhwimg8821c_testchip_rf.h" - #include "rtl8821c/halhwimg8821c_testchip_bb.h" #include "rtl8821c/halhwimg8821c_mac.h" #include "rtl8821c/halhwimg8821c_rf.h" #include "rtl8821c/halhwimg8821c_bb.h" - #include "rtl8821c/halhwimg8821c_fw.h" #include "rtl8821c/phydm_regconfig8821c.h" #include "halrf/rtl8821c/halrf_8821c.h" #include "rtl8821c/version_rtl8821c.h" @@ -400,4 +394,12 @@ phy_set_tx_power_limit( #endif #endif +#if (RTL8195B_SUPPORT == 1) + #include "rtl8195b/phydm_hal_api8195b.h" +#endif + +#if (RTL8198F_SUPPORT == 1) + #include "rtl8198f/phydm_hal_api8198F.h" +#endif + #endif /* __ODM_PRECOMP_H__ */ diff --git a/hal/phydm/phydm_psd.c b/hal/phydm/phydm_psd.c index f870621..8717aca 100644 --- a/hal/phydm/phydm_psd.c +++ b/hal/phydm/phydm_psd.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,432 +8,395 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ - -//============================================================ -// include files -//============================================================ + +//============================================================ +// include files +//============================================================ #include "mp_precomp.h" -#include "phydm_precomp.h" - -#if (CONFIG_PSD_TOOL == 1) - -u32 -phydm_get_psd_data( - void *p_dm_void, - u32 psd_tone_idx, - u32 igi - ) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); - u32 psd_report = 0; - - odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, 0x3ff, psd_tone_idx); - - odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, BIT(22), 1); /*PSD trigger start*/ - ODM_delay_us(10); - odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, BIT(22), 0); /*PSD trigger stop*/ - - psd_report = odm_get_bb_reg(p_dm_odm, p_dm_psd_table->psd_report_reg, 0xffff); - psd_report = odm_convert_to_db(psd_report) + igi; - - return psd_report; -} - -u8 -phydm_psd_stop_trx( - void *p_dm_void - ) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 i; - u8 trx_idle_success = false; - u32 dbg_port_value = 0; - - /*[Stop TRX]---------------------------------------------------------------------*/ - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_3, 0x0) == false) /*set debug port to 0x0*/ - return STOP_TRX_FAIL; - - for (i = 0; i<10000; i++) { - dbg_port_value = phydm_get_bb_dbg_port_value(p_dm_odm); - if ((dbg_port_value & (BIT(17) | BIT(3))) == 0) /* PHYTXON && CCA_all */ { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD wait for ((%d)) times\n", i)); - - trx_idle_success = true; - break; - } - } - - if (trx_idle_success) { - - odm_set_bb_reg(p_dm_odm, 0x520, 0xff0000, 0xff); /*pause all TX queue*/ - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0); /*disable CCK block*/ - odm_set_bb_reg(p_dm_odm, 0x838, BIT(1), 1); /*disable OFDM RX CCA*/ - } else { - /*TBD*/ - odm_set_bb_reg(p_dm_odm, 0x800, BIT(24), 0); /* disable whole CCK block */ - odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */ - } - - } else { - return STOP_TRX_FAIL; - } - - phydm_release_bb_dbg_port(p_dm_odm); - - return STOP_TRX_SUCCESS; - -} - -u8 psd_result_cali_tone_8821[7]= {21, 28, 33, 93, 98, 105, 127}; -u8 psd_result_cali_val_8821[7] = {67,69,71,72,71,69,67}; - -void -phydm_psd( - void *p_dm_void, - u32 igi, - u16 start_point, - u16 stop_point - ) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); - u32 i = 0, mod_tone_idx; - u32 t = 0; - u16 fft_max_half_bw; - u32 psd_igi_a_reg; - u32 psd_igi_b_reg; - u16 psd_fc_channel = p_dm_psd_table->psd_fc_channel; - u8 ag_rf_mode_reg = 0; - u8 rf_reg18_9_8 = 0; - u32 psd_result_tmp = 0; - u8 psd_result = 0; - u8 psd_result_cali_tone[7] = {0}; - u8 psd_result_cali_val[7] = {0}; - u8 noise_table_idx = 0; - - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - odm_move_memory(p_dm_odm, psd_result_cali_tone, psd_result_cali_tone_8821, 7); - odm_move_memory(p_dm_odm, psd_result_cali_val, psd_result_cali_val_8821, 7); - } - - p_dm_psd_table->psd_in_progress = 1; - - /*[Stop DIG]*/ - p_dm_odm->support_ability &= ~(ODM_BB_DIG); - p_dm_odm->support_ability &= ~(ODM_BB_FA_CNT); - - - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD Start =>\n")); - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - psd_igi_a_reg = 0xc50; - psd_igi_b_reg = 0xe50; - } else { - psd_igi_a_reg = 0xc50; - psd_igi_b_reg = 0xc58; - } - - /*[back up IGI]*/ - p_dm_psd_table->initial_gain_backup = odm_get_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff); - odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/ - odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/ - ODM_delay_us(10); - - if (phydm_psd_stop_trx(p_dm_odm) == STOP_TRX_FAIL) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("STOP_TRX_FAIL\n")); - return; - } - - /*[Set IGI]*/ - odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, igi); - odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, igi); - - /*[Backup RF Reg]*/ - p_dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); - - if (psd_fc_channel > 14) { - - rf_reg18_9_8 = 1; - - if (36 <= psd_fc_channel && psd_fc_channel <= 64) - ag_rf_mode_reg = 0x1; - else if (100 <= psd_fc_channel && psd_fc_channel <= 140) - ag_rf_mode_reg = 0x3; - else if (140 < psd_fc_channel) - ag_rf_mode_reg = 0x5; - } - - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xff, psd_fc_channel); /* Set RF fc*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0x300, rf_reg18_9_8); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xc00, p_dm_psd_table->psd_bw_rf_reg); /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xf0000, ag_rf_mode_reg); /* Set RF ag fc mode*/ - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("0xc50=((0x%x))\n", odm_get_bb_reg(p_dm_odm, 0xc50, MASKDWORD))); - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("RF0x0=((0x%x))\n", odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, RFREGOFFSETMASK)));*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("RF0x18=((0x%x))\n", odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK))); - - /*[Stop 3-wires]*/ - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, 0xc00, 0xf, 0x4);/* hardware 3-wire off */ - odm_set_bb_reg(p_dm_odm, 0xe00, 0xf, 0x4);/* hardware 3-wire off */ - } else { - odm_set_bb_reg(p_dm_odm, 0x88c, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ - } - ODM_delay_us(10); - - if (stop_point > (p_dm_psd_table->fft_smp_point-1)) - stop_point = (p_dm_psd_table->fft_smp_point-1); - - if (start_point > (p_dm_psd_table->fft_smp_point-1)) - start_point = (p_dm_psd_table->fft_smp_point-1); - - if (start_point > stop_point) - stop_point = start_point; - - - for (i = start_point; i <= stop_point; i++ ) { - - fft_max_half_bw = (p_dm_psd_table->fft_smp_point)>>1; - - if (i < fft_max_half_bw) { - mod_tone_idx = i + fft_max_half_bw; - } else { - mod_tone_idx = i - fft_max_half_bw; - } - - psd_result_tmp = 0; - for (t = 0; t < p_dm_psd_table->sw_avg_time; t++) { - psd_result_tmp += phydm_get_psd_data(p_dm_odm, mod_tone_idx, igi); - /**/ - } - psd_result = (u8)((psd_result_tmp/p_dm_psd_table->sw_avg_time)) - p_dm_psd_table->psd_pwr_common_offset; - - if( p_dm_psd_table->fft_smp_point == 128 && (p_dm_psd_table->noise_k_en)) { - - if (i > psd_result_cali_tone[noise_table_idx]) { - noise_table_idx ++; - } - - if (noise_table_idx > 6) - noise_table_idx = 6; - - if (psd_result >= psd_result_cali_val[noise_table_idx]) - psd_result = psd_result - psd_result_cali_val[noise_table_idx]; - else - psd_result = 0; - - - p_dm_psd_table->psd_result[i] = psd_result; - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[%d] N_cali = %d, PSD = %d\n", mod_tone_idx, psd_result_cali_val[noise_table_idx], psd_result)); - - } - - /*[Start 3-wires]*/ - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, 0xc00, 0xf, 0x7);/* hardware 3-wire on */ - odm_set_bb_reg(p_dm_odm, 0xe00, 0xf, 0x7);/* hardware 3-wire on */ - } else { - odm_set_bb_reg(p_dm_odm, 0x88c, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ - } - ODM_delay_us(10); - - /*[Revert Reg]*/ - odm_set_bb_reg(p_dm_odm, 0x520, 0xff0000, 0x0); /*start all TX queue*/ - odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 1); /*enable CCK block*/ - odm_set_bb_reg(p_dm_odm, 0x838, BIT(1), 0); /*enable OFDM RX CCA*/ - - odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, p_dm_psd_table->initial_gain_backup); - odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, p_dm_psd_table->initial_gain_backup); - - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, p_dm_psd_table->rf_0x18_bkp); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD finished\n\n")); - - p_dm_odm->support_ability |= ODM_BB_DIG; - p_dm_odm->support_ability |= ODM_BB_FA_CNT; - p_dm_psd_table->psd_in_progress = 0; - - -} - -void -phydm_psd_para_setting( - void *p_dm_void, - u8 sw_avg_time, - u8 hw_avg_time, - u8 i_q_setting, - u16 fft_smp_point, - u8 ant_sel, - u8 psd_input, - u8 channel, - u8 noise_k_en - ) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); - u8 fft_smp_point_idx = 0; - - p_dm_psd_table->fft_smp_point = fft_smp_point; - - if (sw_avg_time == 0) - sw_avg_time = 1; - - p_dm_psd_table->sw_avg_time = sw_avg_time; - p_dm_psd_table->psd_fc_channel = channel; - p_dm_psd_table->noise_k_en = noise_k_en; - - if (fft_smp_point == 128) - fft_smp_point_idx = 0; - else if (fft_smp_point == 256) - fft_smp_point_idx = 1; - else if (fft_smp_point == 512) - fft_smp_point_idx = 2; - else if (fft_smp_point == 1024) - fft_smp_point_idx = 3; - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0x910, BIT(11) | BIT(10), i_q_setting); - odm_set_bb_reg(p_dm_odm, 0x910, BIT(13) | BIT(12), hw_avg_time); - odm_set_bb_reg(p_dm_odm, 0x910, BIT(15) | BIT(14), fft_smp_point_idx); - odm_set_bb_reg(p_dm_odm, 0x910, BIT(17) | BIT(16), ant_sel); - odm_set_bb_reg(p_dm_odm, 0x910, BIT(23), psd_input); - - } else { - - } - - /*bw = (*p_dm_odm->p_band_width); //ODM_BW20M */ - /*channel = *(p_dm_odm->p_channel);*/ - - - - -} - -void -phydm_psd_init( - void *p_dm_void - ) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD para init\n")); - - p_dm_psd_table->psd_in_progress = false; - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - p_dm_psd_table->psd_reg = 0x910; - p_dm_psd_table->psd_report_reg = 0xF44; - - if (ODM_IC_11AC_2_SERIES) - p_dm_psd_table->psd_bw_rf_reg = 1; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ - else - p_dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ - - } else { - - p_dm_psd_table->psd_reg = 0x808; - p_dm_psd_table->psd_report_reg = 0x8B4; - p_dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ - } - - if (p_dm_odm->support_ic_type == ODM_RTL8812) - p_dm_psd_table->psd_pwr_common_offset = 0; - else if (p_dm_odm->support_ic_type == ODM_RTL8821) - p_dm_psd_table->psd_pwr_common_offset = 0; - else - p_dm_psd_table->psd_pwr_common_offset = 0; - - phydm_psd_para_setting(p_dm_odm, 1, 2, 3, 128, 0, 0, 7, 0); - /*phydm_psd(p_dm_odm, 0x3c, 0, 127);*/ /* target at -50dBm */ - - -} - +#include "phydm_precomp.h" + +#ifdef CONFIG_PSD_TOOL + +u32 +phydm_get_psd_data( + void *dm_void, + u32 psd_tone_idx, + u32 igi + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + u32 psd_report = 0; + + odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx); + + odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1); /*PSD trigger start*/ + ODM_delay_us(10); + odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0); /*PSD trigger stop*/ + + psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg, 0xffff); + psd_report = odm_convert_to_db(psd_report) + igi; + + return psd_report; +} + +u8 psd_result_cali_tone_8821[7]= {21, 28, 33, 93, 98, 105, 127}; +u8 psd_result_cali_val_8821[7] = {67,69,71,72,71,69,67}; + +void +phydm_psd( + void *dm_void, + u32 igi, + u16 start_point, + u16 stop_point + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + u32 i = 0, mod_tone_idx; + u32 t = 0; + u16 fft_max_half_bw; + u32 psd_igi_a_reg; + u32 psd_igi_b_reg; + u16 psd_fc_channel = dm_psd_table->psd_fc_channel; + u8 ag_rf_mode_reg = 0; + u8 rf_reg18_9_8 = 0; + u32 psd_result_tmp = 0; + u8 psd_result = 0; + u8 psd_result_cali_tone[7] = {0}; + u8 psd_result_cali_val[7] = {0}; + u8 noise_table_idx = 0; + u8 set_result; + + if (dm->support_ic_type == ODM_RTL8821) { + odm_move_memory(dm, psd_result_cali_tone, psd_result_cali_tone_8821, 7); + odm_move_memory(dm, psd_result_cali_val, psd_result_cali_val_8821, 7); + } + + dm_psd_table->psd_in_progress = 1; + + /*[Stop DIG]*/ + dm->support_ability &= ~(ODM_BB_DIG); + dm->support_ability &= ~(ODM_BB_FA_CNT); + + + + PHYDM_DBG(dm, ODM_COMP_API, "PSD Start =>\n"); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + psd_igi_a_reg = 0xc50; + psd_igi_b_reg = 0xe50; + } else { + psd_igi_a_reg = 0xc50; + psd_igi_b_reg = 0xc58; + } + + /*[back up IGI]*/ + dm_psd_table->initial_gain_backup = odm_get_bb_reg(dm, psd_igi_a_reg, 0xff); + odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/ + odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/ + ODM_delay_us(10); + + if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) { + PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n"); + return; + } + + /*[Set IGI]*/ + odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, igi); + odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, igi); + + /*[Backup RF Reg]*/ + dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK); + dm_psd_table->rf_0x18_bkp_b = odm_get_rf_reg(dm, RF_PATH_B, 0x18, RFREGOFFSETMASK); + + if (psd_fc_channel > 14) { + + rf_reg18_9_8 = 1; + + if (36 <= psd_fc_channel && psd_fc_channel <= 64) + ag_rf_mode_reg = 0x1; + else if (100 <= psd_fc_channel && psd_fc_channel <= 140) + ag_rf_mode_reg = 0x3; + else if (140 < psd_fc_channel) + ag_rf_mode_reg = 0x5; + } + + /* RF path-a */ + odm_set_rf_reg(dm, RF_PATH_A, 0x18, 0xff, psd_fc_channel); /* Set RF fc*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x18, 0x300, rf_reg18_9_8); + odm_set_rf_reg(dm, RF_PATH_A, 0x18, 0xc00, dm_psd_table->psd_bw_rf_reg); /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + odm_set_rf_reg(dm, RF_PATH_A, 0x18, 0xf0000, ag_rf_mode_reg); /* Set RF ag fc mode*/ + + /* RF path-b */ + odm_set_rf_reg(dm, RF_PATH_B, 0x18, 0xff, psd_fc_channel); /* Set RF fc*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x18, 0x300, rf_reg18_9_8); + odm_set_rf_reg(dm, RF_PATH_B, 0x18, 0xc00, dm_psd_table->psd_bw_rf_reg); /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + odm_set_rf_reg(dm, RF_PATH_B, 0x18, 0xf0000, ag_rf_mode_reg); /* Set RF ag fc mode*/ + + PHYDM_DBG(dm, ODM_COMP_API, "0xc50=((0x%x))\n", odm_get_bb_reg(dm, 0xc50, MASKDWORD)); + /*PHYDM_DBG(dm, ODM_COMP_API, "RF0x0=((0x%x))\n", odm_get_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK));*/ + PHYDM_DBG(dm, ODM_COMP_API, "RF0x18=((0x%x))\n", odm_get_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK)); + + /*[Stop 3-wires]*/ + phydm_stop_3_wire(dm, PHYDM_SET); + + ODM_delay_us(10); + + if (stop_point > (dm_psd_table->fft_smp_point-1)) + stop_point = (dm_psd_table->fft_smp_point-1); + + if (start_point > (dm_psd_table->fft_smp_point-1)) + start_point = (dm_psd_table->fft_smp_point-1); + + if (start_point > stop_point) + stop_point = start_point; + + + for (i = start_point; i <= stop_point; i++ ) { + fft_max_half_bw = (dm_psd_table->fft_smp_point)>>1; + + if (i < fft_max_half_bw) { + mod_tone_idx = i + fft_max_half_bw; + } else { + mod_tone_idx = i - fft_max_half_bw; + } + + psd_result_tmp = 0; + for (t = 0; t < dm_psd_table->sw_avg_time; t++) { + psd_result_tmp += phydm_get_psd_data(dm, mod_tone_idx, igi); + /**/ + } + psd_result = (u8)((psd_result_tmp/dm_psd_table->sw_avg_time)) - dm_psd_table->psd_pwr_common_offset; + + if( dm_psd_table->fft_smp_point == 128 && (dm_psd_table->noise_k_en)) { + if (i > psd_result_cali_tone[noise_table_idx]) { + noise_table_idx ++; + } + + if (noise_table_idx > 6) + noise_table_idx = 6; + + if (psd_result >= psd_result_cali_val[noise_table_idx]) + psd_result = psd_result - psd_result_cali_val[noise_table_idx]; + else + psd_result = 0; + + + dm_psd_table->psd_result[i] = psd_result; + } + + PHYDM_DBG(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n", mod_tone_idx, psd_result_cali_val[noise_table_idx], psd_result); + + } + + /*[Start 3-wires]*/ + phydm_stop_3_wire(dm, PHYDM_REVERT); + + ODM_delay_us(10); + + /*[Revert Reg]*/ + set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT); + + odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, dm_psd_table->initial_gain_backup); + odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, dm_psd_table->initial_gain_backup); + + odm_set_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK, dm_psd_table->rf_0x18_bkp); + odm_set_rf_reg(dm, RF_PATH_B, 0x18, RFREGOFFSETMASK, dm_psd_table->rf_0x18_bkp_b); + + PHYDM_DBG(dm, ODM_COMP_API, "PSD finished\n\n"); + + dm->support_ability |= ODM_BB_DIG; + dm->support_ability |= ODM_BB_FA_CNT; + dm_psd_table->psd_in_progress = 0; + + +} + void -phydm_psd_debug( - void *p_dm_void, - char input[][16], +phydm_psd_para_setting( + void *dm_void, + u8 sw_avg_time, + u8 hw_avg_time, + u8 i_q_setting, + u16 fft_smp_point, + u8 ant_sel, + u8 psd_input, + u8 channel, + u8 noise_k_en + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + u8 fft_smp_point_idx = 0; + + dm_psd_table->fft_smp_point = fft_smp_point; + + if (sw_avg_time == 0) + sw_avg_time = 1; + + dm_psd_table->sw_avg_time = sw_avg_time; + dm_psd_table->psd_fc_channel = channel; + dm_psd_table->noise_k_en = noise_k_en; + + if (fft_smp_point == 128) + fft_smp_point_idx = 0; + else if (fft_smp_point == 256) + fft_smp_point_idx = 1; + else if (fft_smp_point == 512) + fft_smp_point_idx = 2; + else if (fft_smp_point == 1024) + fft_smp_point_idx = 3; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + + odm_set_bb_reg(dm, 0x910, BIT(11) | BIT(10), i_q_setting); + odm_set_bb_reg(dm, 0x910, BIT(13) | BIT(12), hw_avg_time); + odm_set_bb_reg(dm, 0x910, BIT(15) | BIT(14), fft_smp_point_idx); + odm_set_bb_reg(dm, 0x910, BIT(17) | BIT(16), ant_sel); + odm_set_bb_reg(dm, 0x910, BIT(23), psd_input); +#if 0 + } else { /*ODM_IC_11N_SERIES*/ +#endif + } + + /*bw = (*dm->band_width); //ODM_BW20M */ + /*channel = *(dm->channel);*/ + + + + +} + +void +phydm_psd_init( + void *dm_void + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + + PHYDM_DBG(dm, ODM_COMP_API, "PSD para init\n"); + + dm_psd_table->psd_in_progress = false; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + + dm_psd_table->psd_reg = 0x910; + dm_psd_table->psd_report_reg = 0xF44; + + if (ODM_IC_11AC_2_SERIES) + dm_psd_table->psd_bw_rf_reg = 1; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + else + dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + + } else { + dm_psd_table->psd_reg = 0x808; + dm_psd_table->psd_report_reg = 0x8B4; + dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + } + + if (dm->support_ic_type == ODM_RTL8812) + dm_psd_table->psd_pwr_common_offset = 0; + else if (dm->support_ic_type == ODM_RTL8821) + dm_psd_table->psd_pwr_common_offset = 0; + else + dm_psd_table->psd_pwr_common_offset = 0; + + phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0); + /*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */ + + +} + +void +phydm_psd_debug( + void *dm_void, + char input[][16], u32 *_used, - char *output, + char *output, u32 *_out_len, u32 input_num ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - char help[] = "-h"; - u32 var1[10] = {0}; - u32 used = *_used; - u32 out_len = *_out_len; - u8 i; - - if ((strcmp(input[1], help) == 0)) { - PHYDM_SNPRINTF((output + used, out_len - used, "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "{1} {IGI(hex)} {start_point} {stop_point}\n")); - - } else { - - - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - - if (var1[0] == 0) { - - for (i = 1; i < 10; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - } - } - - PHYDM_SNPRINTF((output + used, out_len - used, "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n", - var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], (u8)var1[7], (u8)var1[8])); - phydm_psd_para_setting(p_dm_odm, (u8)var1[1], (u8)var1[2], (u8)var1[3], (u16)var1[4], (u8)var1[5], (u8)var1[6], (u8)var1[7], (u8)var1[8]); - - } else if (var1[0] == 1) { - - PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]); - PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); - PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]); - PHYDM_SNPRINTF((output + used, out_len - used, "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n", var1[1], var1[2], var1[3])); - p_dm_odm->debug_components |= ODM_COMP_API; - phydm_psd(p_dm_odm, var1[1], (u16)var1[2], (u16)var1[3]); - p_dm_odm->debug_components &= (~ODM_COMP_API); - } - - } - - - -} - -u8 -phydm_get_psd_result_table( - void *p_dm_void, - int index - ) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); - u8 temp_result = 0; - - if(index<128) - temp_result = p_dm_psd_table->psd_result[index]; - - return temp_result; - -} - -#endif - + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {IGI(hex)} {start_point} {stop_point}\n"); + goto out; + } + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 0) { + for (i = 1; i < 10; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n", + + var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], (u8)var1[7], (u8)var1[8]); + phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2], (u8)var1[3], (u16)var1[4], (u8)var1[5], (u8)var1[6], (u8)var1[7], (u8)var1[8]); + + } else if (var1[0] == 1) { + PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n", + var1[1], var1[2], var1[3]); + dm->debug_components |= ODM_COMP_API; + phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]); + dm->debug_components &= (~ODM_COMP_API); + } + +out: + *_used = used; + *_out_len = out_len; + +} + +u8 +phydm_get_psd_result_table( + void *dm_void, + int index + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + u8 temp_result = 0; + + if(index<128) + temp_result = dm_psd_table->psd_result[index]; + + return temp_result; + +} + +#endif + diff --git a/hal/phydm/phydm_psd.h b/hal/phydm/phydm_psd.h index 80d3617..df23278 100644 --- a/hal/phydm/phydm_psd.h +++ b/hal/phydm/phydm_psd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,89 +8,95 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ - -#ifndef __PHYDMPSD_H__ -#define __PHYDMPSD_H__ - -/*#define PSD_VERSION "1.0"*/ /*2016.09.22 Dino*/ -#define PSD_VERSION "1.1" /*2016.10.07 Dino, Add Option for PSD Tone index Selection */ - -#if (CONFIG_PSD_TOOL == 1) - - -#define STOP_TRX_SUCCESS 1 -#define STOP_TRX_FAIL 0 - - -struct _PHYDM_PSD_ { - - u8 psd_in_progress; - u32 psd_reg; - u32 psd_report_reg; - u8 psd_pwr_common_offset; - u16 sw_avg_time; - u16 fft_smp_point; - u32 initial_gain_backup; - u32 rf_0x18_bkp; - u16 psd_fc_channel; - u32 psd_bw_rf_reg; - u8 psd_result[128]; - u8 noise_k_en; -}; - -u32 -phydm_get_psd_data( - void *p_dm_void, - u32 psd_tone_idx, - u32 igi -); - + +#ifndef __PHYDMPSD_H__ +#define __PHYDMPSD_H__ + +/*#define PSD_VERSION "1.0"*/ /*2016.09.22 Dino*/ +#define PSD_VERSION "1.1" /*2016.10.07 Dino, Add Option for PSD Tone index Selection */ + +#ifdef CONFIG_PSD_TOOL + + +struct psd_info { + u8 psd_in_progress; + u32 psd_reg; + u32 psd_report_reg; + u8 psd_pwr_common_offset; + u16 sw_avg_time; + u16 fft_smp_point; + u32 initial_gain_backup; + u32 rf_0x18_bkp; + u32 rf_0x18_bkp_b; + u16 psd_fc_channel; + u32 psd_bw_rf_reg; + u8 psd_result[128]; + u8 noise_k_en; +}; + +u32 +phydm_get_psd_data( + void *dm_void, + u32 psd_tone_idx, + u32 igi +); + void -phydm_psd_debug( - void *p_dm_void, - char input[][16], +phydm_psd_debug( + void *dm_void, + char input[][16], u32 *_used, - char *output, + char *output, u32 *_out_len, u32 input_num -); - -void -phydm_psd( - void *p_dm_void, - u32 igi, - u16 start_point, - u16 stop_point -); - -void -phydm_psd_para_setting( - void *p_dm_void, - u8 sw_avg_time, - u8 hw_avg_time, - u8 i_q_setting, - u16 fft_smp_point, - u8 ant_sel, - u8 psd_input, - u8 channel, - u8 noise_k_en -); - -void -phydm_psd_init( - void *p_dm_void -); - -u8 -phydm_get_psd_result_table( - void *p_dm_void, - int index -); - -#endif -#endif - +); + +void +phydm_psd( + void *dm_void, + u32 igi, + u16 start_point, + u16 stop_point +); + +void +phydm_psd_para_setting( + void *dm_void, + u8 sw_avg_time, + u8 hw_avg_time, + u8 i_q_setting, + u16 fft_smp_point, + u8 ant_sel, + u8 psd_input, + u8 channel, + u8 noise_k_en +); + +void +phydm_psd_init( + void *dm_void +); + +u8 +phydm_get_psd_result_table( + void *dm_void, + int index +); + +#endif +#endif + diff --git a/hal/phydm/phydm_rainfo.c b/hal/phydm/phydm_rainfo.c index 991cecf..73af1a2 100644 --- a/hal/phydm/phydm_rainfo.c +++ b/hal/phydm/phydm_rainfo.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ @@ -21,286 +31,155 @@ void phydm_h2C_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, - char *output, + char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 h2c_parameter[H2C_MAX_LENGTH] = {0}; u8 phydm_h2c_id = (u8)dm_value[0]; u8 i; u32 used = *_used; u32 out_len = *_out_len; - PHYDM_SNPRINTF((output + used, out_len - used, "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id); for (i = 0; i < H2C_MAX_LENGTH; i++) { - h2c_parameter[i] = (u8)dm_value[i + 1]; - PHYDM_SNPRINTF((output + used, out_len - used, "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i])); + PDM_SNPF(out_len, used, output + used, out_len - used, + "H2C: Byte[%d] = ((0x%x))\n", i, + h2c_parameter[i]); } - odm_fill_h2c_cmd(p_dm_odm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter); - + odm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter); + + *_used = used; + *_out_len = out_len; } -#if (defined(CONFIG_RA_DBG_CMD)) void -odm_ra_para_adjust_send_h2c( - void *p_dm_void +phydm_fw_fix_rate( + void *dm_void, + u8 en, + u8 macid, + u8 bw, + u8 rate + ) { - - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = RA_FIRST_MACID; - - if (p_ra_table->ra_para_feedback_req) { /*h2c_parameter[5]=1 ; ask FW for all RA parameters*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Ask FW for RA parameter\n")); - h2c_parameter[5] |= BIT(1); /*ask FW to report RA parameters*/ - h2c_parameter[1] = p_ra_table->para_idx; /*p_ra_table->para_idx;*/ - p_ra_table->ra_para_feedback_req = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_u32_tmp; + + if (dm->support_ic_type & PHYDM_IC_8051_SERIES) { + + reg_u32_tmp = (bw << 24) | (rate << 16) | (macid << 8) | en; + odm_set_bb_reg(dm, 0x4a0, MASKDWORD, reg_u32_tmp); + } else { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Send H2C to FW for modifying RA parameter\n")); - - h2c_parameter[1] = p_ra_table->para_idx; - h2c_parameter[2] = p_ra_table->rate_idx; - /* [8 bit]*/ - if (p_ra_table->para_idx == RADBG_RTY_PENALTY || p_ra_table->para_idx == RADBG_RATE_UP_RTY_RATIO || p_ra_table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { - h2c_parameter[3] = p_ra_table->value; - h2c_parameter[4] = 0; - } - /* [16 bit]*/ - else { - h2c_parameter[3] = (u8)(((p_ra_table->value_16) & 0xf0) >> 4); /*byte1*/ - h2c_parameter[4] = (u8)((p_ra_table->value_16) & 0x0f); /*byte0*/ - } - } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[1] = 0x%x\n", h2c_parameter[1])); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[2] = 0x%x\n", h2c_parameter[2])); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[3] = 0x%x\n", h2c_parameter[3])); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[4] = 0x%x\n", h2c_parameter[4])); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[5] = 0x%x\n", h2c_parameter[5])); - - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RA_PARA_ADJUST, 6, h2c_parameter); - -} - - -void -odm_ra_para_adjust( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 rate_idx = p_ra_table->rate_idx; - u8 value = p_ra_table->value; - u8 pre_value = 0xff; - - if (p_ra_table->para_idx == RADBG_RTY_PENALTY) { - pre_value = p_ra_table->RTY_P[rate_idx]; - p_ra_table->RTY_P[rate_idx] = value; - p_ra_table->RTY_P_modify_note[rate_idx] = 1; - } else if (p_ra_table->para_idx == RADBG_N_HIGH) { - - } else if (p_ra_table->para_idx == RADBG_N_LOW) { - - } else if (p_ra_table->para_idx == RADBG_RATE_UP_RTY_RATIO) { - pre_value = p_ra_table->RATE_UP_RTY_RATIO[rate_idx]; - p_ra_table->RATE_UP_RTY_RATIO[rate_idx] = value; - p_ra_table->RATE_UP_RTY_RATIO_modify_note[rate_idx] = 1; - } else if (p_ra_table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { - pre_value = p_ra_table->RATE_DOWN_RTY_RATIO[rate_idx]; - p_ra_table->RATE_DOWN_RTY_RATIO[rate_idx] = value; - p_ra_table->RATE_DOWN_RTY_RATIO_modify_note[rate_idx] = 1; - } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("Change RA Papa[%d], rate[ %d ], ((%d)) -> ((%d))\n", p_ra_table->para_idx, rate_idx, pre_value, value)); - odm_ra_para_adjust_send_h2c(p_dm_odm); -} - -void -phydm_ra_print_msg( - void *p_dm_void, - u8 *value, - u8 *value_default, - u8 *modify_note -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u32 i; - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |Current-value| |Default-value| |Modify?|\n")); - for (i = 0 ; i <= (p_ra_table->rate_length); i++) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %20d %25d %20s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); -#else - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %10d %14d %14s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); -#endif + + if (en == 1) + reg_u32_tmp = (0x60 << 24) | (macid << 16) | (bw << 8) | rate; + else + reg_u32_tmp = 0x40000000; + + odm_set_bb_reg(dm, 0x450, MASKDWORD, reg_u32_tmp); } - -} - -void -odm_RA_debug( - void *p_dm_void, - u32 *const dm_value -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - - p_ra_table->is_ra_dbg_init = false; - - if (dm_value[0] == 100) { /*1 Print RA Parameters*/ - u8 default_pointer_value; - u8 *pvalue; - u8 *pvalue_default; - u8 *pmodify_note; - - pvalue = pvalue_default = pmodify_note = &default_pointer_value; - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n")); - - if (dm_value[1] == RADBG_RTY_PENALTY) { /* [1]*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [1] RTY_PENALTY\n")); - pvalue = &(p_ra_table->RTY_P[0]); - pvalue_default = &(p_ra_table->RTY_P_default[0]); - pmodify_note = (u8 *)&(p_ra_table->RTY_P_modify_note[0]); - } else if (dm_value[1] == RADBG_N_HIGH) /* [2]*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [2] N_HIGH\n")); - - else if (dm_value[1] == RADBG_N_LOW) /*[3]*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [3] N_LOW\n")); - - else if (dm_value[1] == RADBG_RATE_UP_RTY_RATIO) { /* [8]*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [8] RATE_UP_RTY_RATIO\n")); - pvalue = &(p_ra_table->RATE_UP_RTY_RATIO[0]); - pvalue_default = &(p_ra_table->RATE_UP_RTY_RATIO_default[0]); - pmodify_note = (u8 *)&(p_ra_table->RATE_UP_RTY_RATIO_modify_note[0]); - } else if (dm_value[1] == RADBG_RATE_DOWN_RTY_RATIO) { /* [9]*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [9] RATE_DOWN_RTY_RATIO\n")); - pvalue = &(p_ra_table->RATE_DOWN_RTY_RATIO[0]); - pvalue_default = &(p_ra_table->RATE_DOWN_RTY_RATIO_default[0]); - pmodify_note = (u8 *)&(p_ra_table->RATE_DOWN_RTY_RATIO_modify_note[0]); - } - - phydm_ra_print_msg(p_dm_odm, pvalue, pvalue_default, pmodify_note); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n\n")); - - } else if (dm_value[0] == 101) { - p_ra_table->para_idx = (u8)dm_value[1]; - - p_ra_table->ra_para_feedback_req = 1; - odm_ra_para_adjust_send_h2c(p_dm_odm); + if (en == 1) { + PHYDM_DBG(dm, ODM_COMP_API, "FW fix TX rate[id =%d], %dM, Rate(%d)=", macid, (20 << bw), rate); + phydm_print_rate(dm, rate, ODM_COMP_API); } else { - p_ra_table->para_idx = (u8)dm_value[0]; - p_ra_table->rate_idx = (u8)dm_value[1]; - p_ra_table->value = (u8)dm_value[2]; - - odm_ra_para_adjust(p_dm_odm); - } -} - -void -odm_ra_para_adjust_init( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 i; - u8 ra_para_pool_u8[3] = { RADBG_RTY_PENALTY, RADBG_RATE_UP_RTY_RATIO, RADBG_RATE_DOWN_RTY_RATIO}; - u8 rate_size_ht_1ss = 20, rate_size_ht_2ss = 28, rate_size_ht_3ss = 36; /*4+8+8+8+8 =36*/ - u8 rate_size_vht_1ss = 10, rate_size_vht_2ss = 20, rate_size_vht_3ss = 30; /*10 + 10 +10 =30*/ -#if 0 - /* RTY_PENALTY = 1, u8 */ - /* N_HIGH = 2, */ - /* N_LOW = 3, */ - /* RATE_UP_TABLE = 4, */ - /* RATE_DOWN_TABLE = 5, */ - /* TRYING_NECESSARY = 6, */ - /* DROPING_NECESSARY = 7, */ - /* RATE_UP_RTY_RATIO = 8, u8 */ - /* RATE_DOWN_RTY_RATIO= 9, u8 */ - /* ALL_PARA = 0xff */ - -#endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("odm_ra_para_adjust_init\n")); - -/* JJ ADD 20161014 */ - if (p_dm_odm->support_ic_type & (ODM_RTL8188F | ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8723D | ODM_RTL8710B)) - p_ra_table->rate_length = rate_size_ht_1ss; - else if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) - p_ra_table->rate_length = rate_size_ht_2ss; - else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8821C)) - p_ra_table->rate_length = rate_size_ht_1ss + rate_size_vht_1ss; - else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) - p_ra_table->rate_length = rate_size_ht_2ss + rate_size_vht_2ss; - else if (p_dm_odm->support_ic_type == ODM_RTL8814A) - p_ra_table->rate_length = rate_size_ht_3ss + rate_size_vht_3ss; - else - p_ra_table->rate_length = rate_size_ht_1ss; - - p_ra_table->is_ra_dbg_init = true; - for (i = 0; i < 3; i++) { - p_ra_table->ra_para_feedback_req = 1; - p_ra_table->para_idx = ra_para_pool_u8[i]; - odm_ra_para_adjust_send_h2c(p_dm_odm); + PHYDM_DBG(dm, ODM_COMP_API, "Auto Rate\n"); } } -#else - void -phydm_RA_debug_PCR( - void *p_dm_void, - u32 *const dm_value, +phydm_ra_debug( + void *dm_void, + char input[][16], u32 *_used, - char *output, + char *output, u32 *_out_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; u32 used = *_used; u32 out_len = *_out_len; + char help[] = "-h"; + u32 var1[5] = {0}; + u8 i = 0; + u32 reg_u32_tmp; - if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output + used, out_len - used, "[Get] PCR RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); - /**/ - } else if (dm_value[0] == 0) { - p_ra_table->RA_offset_direction = 0; - p_ra_table->RA_threshold_offset = (u8)dm_value[1]; - PHYDM_SNPRINTF((output + used, out_len - used, "[Set] PCR RA_threshold_offset = (( -%d ))\n", p_ra_table->RA_threshold_offset)); - } else if (dm_value[0] == 1) { - p_ra_table->RA_offset_direction = 1; - p_ra_table->RA_threshold_offset = (u8)dm_value[1]; - PHYDM_SNPRINTF((output + used, out_len - used, "[Set] PCR RA_threshold_offset = (( +%d ))\n", p_ra_table->RA_threshold_offset)); + for (i = 0; i < 5; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {0:-,1:+} {ofst}: set offset\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {100}: show offset\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2} {en} {macid} {bw} {rate}: fw fix rate\n"); + + } else if (var1[0] == 1) { /*Adjust PCR offset*/ + + if (var1[1] == 100) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[Get] RA_ofst=((%s%d))\n", + ((ra_tab->RA_threshold_offset == 0) ? " " : ((ra_tab->RA_offset_direction) ? "+" : "-")), + ra_tab->RA_threshold_offset); + + } else if (var1[1] == 0) { + ra_tab->RA_offset_direction = 0; + ra_tab->RA_threshold_offset = (u8)var1[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[Set] RA_ofst=((-%d))\n", + ra_tab->RA_threshold_offset); + } else if (var1[1] == 1) { + ra_tab->RA_offset_direction = 1; + ra_tab->RA_threshold_offset = (u8)var1[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[Set] RA_ofst=((+%d))\n", + ra_tab->RA_threshold_offset); + } + + } else if (var1[0] == 2) { /*FW fix rate*/ + + PDM_SNPF(out_len, used, output + used, out_len - used, + "[FW fix TX Rate] {en, macid,bw,rate}={%d, %d, %d, 0x%x}", + var1[1], var1[2], var1[3], var1[4]); + + phydm_fw_fix_rate(dm, (u8)var1[1], (u8)var1[2], (u8)var1[3], (u8)var1[4]); + } else { - PHYDM_SNPRINTF((output + used, out_len - used, "[Set] Error\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Set] Error\n"); /**/ } - + *_used = used; + *_out_len = out_len; } -#endif /*#if (defined(CONFIG_RA_DBG_CMD))*/ + void odm_c2h_ra_para_report_handler( - void *p_dm_void, + void *dm_void, u8 *cmd_buf, u8 cmd_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (defined(CONFIG_RA_DBG_CMD)) - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct ra_table *ra_tab = &dm->dm_ra_table; #endif u8 para_idx = cmd_buf[0]; /*Retry Penalty, NH, NL*/ @@ -311,1585 +190,1128 @@ odm_c2h_ra_para_report_handler( u8 i; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[ From FW C2H RA Para ] cmd_buf[0]= (( %d ))\n", cmd_buf[0])); + PHYDM_DBG(dm, DBG_RA, "[ From FW C2H RA Para ] cmd_buf[0]= (( %d ))\n", cmd_buf[0]); #if (defined(CONFIG_RA_DBG_CMD)) if (para_idx == RADBG_RTY_PENALTY) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |RTY Penality index|\n")); + PHYDM_DBG(dm, DBG_RA, " |rate index| |RTY Penality index|\n"); for (i = 0 ; i < (rate_type_length) ; i++) { - if (p_ra_table->is_ra_dbg_init) - p_ra_table->RTY_P_default[rate_type_start + i] = cmd_buf[2 + i]; + if (ra_tab->is_ra_dbg_init) + ra_tab->RTY_P_default[rate_type_start + i] = cmd_buf[2 + i]; - p_ra_table->RTY_P[rate_type_start + i] = cmd_buf[2 + i]; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (rate_type_start + i), p_ra_table->RTY_P[rate_type_start + i])); + ra_tab->RTY_P[rate_type_start + i] = cmd_buf[2 + i]; + PHYDM_DBG(dm, DBG_RA, "%8d %15d\n", (rate_type_start + i), ra_tab->RTY_P[rate_type_start + i]); } } else if (para_idx == RADBG_N_HIGH) { /**/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |N-High|\n")); + PHYDM_DBG(dm, DBG_RA, " |rate index| |N-High|\n"); } else if (para_idx == RADBG_N_LOW) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |N-Low|\n")); + PHYDM_DBG(dm, DBG_RA, " |rate index| |N-Low|\n"); /**/ } else if (para_idx == RADBG_RATE_UP_RTY_RATIO) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |rate Up RTY Ratio|\n")); + PHYDM_DBG(dm, DBG_RA, " |rate index| |rate Up RTY Ratio|\n"); for (i = 0; i < (rate_type_length); i++) { - if (p_ra_table->is_ra_dbg_init) - p_ra_table->RATE_UP_RTY_RATIO_default[rate_type_start + i] = cmd_buf[2 + i]; + if (ra_tab->is_ra_dbg_init) + ra_tab->RATE_UP_RTY_RATIO_default[rate_type_start + i] = cmd_buf[2 + i]; - p_ra_table->RATE_UP_RTY_RATIO[rate_type_start + i] = cmd_buf[2 + i]; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (rate_type_start + i), p_ra_table->RATE_UP_RTY_RATIO[rate_type_start + i])); + ra_tab->RATE_UP_RTY_RATIO[rate_type_start + i] = cmd_buf[2 + i]; + PHYDM_DBG(dm, DBG_RA, "%8d %15d\n", (rate_type_start + i), ra_tab->RATE_UP_RTY_RATIO[rate_type_start + i]); } } else if (para_idx == RADBG_RATE_DOWN_RTY_RATIO) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |rate Down RTY Ratio|\n")); + PHYDM_DBG(dm, DBG_RA, " |rate index| |rate Down RTY Ratio|\n"); for (i = 0; i < (rate_type_length); i++) { - if (p_ra_table->is_ra_dbg_init) - p_ra_table->RATE_DOWN_RTY_RATIO_default[rate_type_start + i] = cmd_buf[2 + i]; + if (ra_tab->is_ra_dbg_init) + ra_tab->RATE_DOWN_RTY_RATIO_default[rate_type_start + i] = cmd_buf[2 + i]; - p_ra_table->RATE_DOWN_RTY_RATIO[rate_type_start + i] = cmd_buf[2 + i]; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (rate_type_start + i), p_ra_table->RATE_DOWN_RTY_RATIO[rate_type_start + i])); + ra_tab->RATE_DOWN_RTY_RATIO[rate_type_start + i] = cmd_buf[2 + i]; + PHYDM_DBG(dm, DBG_RA, "%8d %15d\n", (rate_type_start + i), ra_tab->RATE_DOWN_RTY_RATIO[rate_type_start + i]); } } else #endif if (para_idx == RADBG_DEBUG_MONITOR1) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { - - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", cmd_buf[1])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "rate =", cmd_buf[2] & 0x7f)); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI =", (cmd_buf[2] & 0x80) >> 7)); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW =", cmd_buf[3])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW_max =", cmd_buf[4])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate0 =", cmd_buf[5])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate1 =", cmd_buf[6])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", cmd_buf[7])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", cmd_buf[8])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI_support =", cmd_buf[9])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "try_ness =", cmd_buf[10])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "pre_rate =", cmd_buf[11])); + PHYDM_DBG(dm, DBG_FW_TRACE, "-------------------------------\n"); + if (dm->support_ic_type & PHYDM_IC_3081_SERIES) { + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "RSSI =", cmd_buf[1]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "rate =", cmd_buf[2] & 0x7f); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "SGI =", (cmd_buf[2] & 0x80) >> 7); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "BW =", cmd_buf[3]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "BW_max =", cmd_buf[4]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "multi_rate0 =", cmd_buf[5]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "multi_rate1 =", cmd_buf[6]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "DISRA =", cmd_buf[7]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "VHT_EN =", cmd_buf[8]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "SGI_support =", cmd_buf[9]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "try_ness =", cmd_buf[10]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "pre_rate =", cmd_buf[11]); } else { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", cmd_buf[1])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x\n", "BW =", cmd_buf[2])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", cmd_buf[3])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", cmd_buf[4])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Hightest rate =", cmd_buf[5])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Lowest rate =", cmd_buf[6])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "SGI_support =", cmd_buf[7])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Rate_ID =", cmd_buf[8]));; + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "RSSI =", cmd_buf[1]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %x\n", "BW =", cmd_buf[2]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "DISRA =", cmd_buf[3]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "VHT_EN =", cmd_buf[4]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Hightest rate =", cmd_buf[5]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "Lowest rate =", cmd_buf[6]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "SGI_support =", cmd_buf[7]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Rate_ID =", cmd_buf[8]); } - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + PHYDM_DBG(dm, DBG_FW_TRACE, "-------------------------------\n"); } else if (para_idx == RADBG_DEBUG_MONITOR2) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "rate_id =", cmd_buf[1])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest_rate =", cmd_buf[2])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "lowest_rate =", cmd_buf[3])); + PHYDM_DBG(dm, DBG_FW_TRACE, "-------------------------------\n"); + if (dm->support_ic_type & PHYDM_IC_3081_SERIES) { + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "rate_id =", cmd_buf[1]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "highest_rate =", cmd_buf[2]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "lowest_rate =", cmd_buf[3]); for (i = 4; i <= 11; i++) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("RAMASK = 0x%x\n", cmd_buf[i])); + PHYDM_DBG(dm, DBG_FW_TRACE, "RAMASK = 0x%x\n", cmd_buf[i]); } else { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x%x %x%x %x%x %x%x\n", "RA Mask:", - cmd_buf[8], cmd_buf[7], cmd_buf[6], cmd_buf[5], cmd_buf[4], cmd_buf[3], cmd_buf[2], cmd_buf[1])); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %x%x %x%x %x%x %x%x\n", "RA Mask:", + cmd_buf[8], cmd_buf[7], cmd_buf[6], cmd_buf[5], cmd_buf[4], cmd_buf[3], cmd_buf[2], cmd_buf[1]); } - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + PHYDM_DBG(dm, DBG_FW_TRACE, "-------------------------------\n"); } else if (para_idx == RADBG_DEBUG_MONITOR3) { - for (i = 0; i < (cmd_len - 1); i++) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("content[%d] = %d\n", i, cmd_buf[1 + i])); + PHYDM_DBG(dm, DBG_FW_TRACE, "content[%d] = %d\n", i, cmd_buf[1 + i]); } else if (para_idx == RADBG_DEBUG_MONITOR4) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {%d.%d}\n", "RA version =", cmd_buf[1], cmd_buf[2])); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s {%d.%d}\n", "RA version =", cmd_buf[1], cmd_buf[2]); else if (para_idx == RADBG_DEBUG_MONITOR5) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Current rate =", cmd_buf[1])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Retry ratio =", cmd_buf[2])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "rate down ratio =", cmd_buf[3])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest rate =", cmd_buf[4])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {0x%x 0x%x}\n", "Muti-try =", cmd_buf[5], cmd_buf[6])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x%x%x%x%x\n", "RA mask =", cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8], cmd_buf[7])); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "Current rate =", cmd_buf[1]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Retry ratio =", cmd_buf[2]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "rate down ratio =", cmd_buf[3]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "highest rate =", cmd_buf[4]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s {0x%x 0x%x}\n", "Muti-try =", cmd_buf[5], cmd_buf[6]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x%x%x%x%x\n", "RA mask =", cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8], cmd_buf[7]); } } void phydm_ra_dynamic_retry_count( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_ARFR)) + if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR)) return; - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("p_dm_odm->pre_b_noisy = %d\n", p_dm_odm->pre_b_noisy ));*/ - if (p_dm_odm->pre_b_noisy != p_dm_odm->noisy_decision) { - - if (p_dm_odm->noisy_decision) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Noisy Env. RA fallback value\n")); - odm_set_mac_reg(p_dm_odm, 0x430, MASKDWORD, 0x0); - odm_set_mac_reg(p_dm_odm, 0x434, MASKDWORD, 0x04030201); + /*PHYDM_DBG(dm, DBG_RA, "dm->pre_b_noisy = %d\n", dm->pre_b_noisy );*/ + if (dm->pre_b_noisy != dm->noisy_decision) { + if (dm->noisy_decision) { + PHYDM_DBG(dm, DBG_DYN_ARFR, "Noisy Env. RA fallback\n"); + odm_set_mac_reg(dm, 0x430, MASKDWORD, 0x0); + odm_set_mac_reg(dm, 0x434, MASKDWORD, 0x04030201); } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Clean Env. RA fallback value\n")); - odm_set_mac_reg(p_dm_odm, 0x430, MASKDWORD, 0x01000000); - odm_set_mac_reg(p_dm_odm, 0x434, MASKDWORD, 0x06050402); + PHYDM_DBG(dm, DBG_DYN_ARFR, "Clean Env. RA fallback\n"); + odm_set_mac_reg(dm, 0x430, MASKDWORD, 0x01000000); + odm_set_mac_reg(dm, 0x434, MASKDWORD, 0x06050402); } - p_dm_odm->pre_b_noisy = p_dm_odm->noisy_decision; + dm->pre_b_noisy = dm->noisy_decision; } } -#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - void -phydm_retry_limit_table_bound( - void *p_dm_void, - u8 *retry_limit, - u8 offset +phydm_print_rate( + void *dm_void, + u8 rate, + u32 dbg_component ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - - if (*retry_limit > offset) { - - *retry_limit -= offset; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0; + u8 b_sgi = (rate & 0x80) >> 7; - if (*retry_limit < p_ra_table->retrylimit_low) - *retry_limit = p_ra_table->retrylimit_low; - else if (*retry_limit > p_ra_table->retrylimit_high) - *retry_limit = p_ra_table->retrylimit_high; - } else - *retry_limit = p_ra_table->retrylimit_low; + PHYDM_DBG_F(dm, dbg_component, "( %s%s%s%s%d%s%s)\n", + ((rate_idx >= ODM_RATEVHTSS1MCS0) && (rate_idx <= ODM_RATEVHTSS1MCS9)) ? "VHT 1ss " : "", + ((rate_idx >= ODM_RATEVHTSS2MCS0) && (rate_idx <= ODM_RATEVHTSS2MCS9)) ? "VHT 2ss " : "", + ((rate_idx >= ODM_RATEVHTSS3MCS0) && (rate_idx <= ODM_RATEVHTSS3MCS9)) ? "VHT 3ss " : "", + (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", + (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0) % 10) : ((rate_idx >= ODM_RATEMCS0) ? (rate_idx - ODM_RATEMCS0) : ((rate_idx <= ODM_RATE54M) ? legacy_table[rate_idx] : 0)), + (b_sgi) ? "-S" : " ", + (rate_idx >= ODM_RATEMCS0) ? "" : "M"); } void -phydm_reset_retry_limit_table( - void *p_dm_void +phydm_c2h_ra_report_handler( + void *dm_void, + u8 *cmd_buf, + u8 cmd_len ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 i; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*support all IC platform*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 macid = cmd_buf[1]; + u8 rate = cmd_buf[0]; + u8 curr_ra_ratio = 0xff; + u8 curr_bw = 0xff; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 rate_order; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; -#else -#if ((RTL8192E_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1)) - u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = { - 1, 1, 2, 4, /*CCK*/ - 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ - 2, 4, 6, 8, 12, 18, 20, 22, /*20M HT-1SS*/ - 2, 4, 6, 8, 12, 18, 20, 22 /*20M HT-2SS*/ - }; - u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = { - 1, 1, 2, 4, /*CCK*/ - 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ - 4, 8, 12, 16, 24, 32, 32, 32, /*40M HT-1SS*/ - 4, 8, 12, 16, 24, 32, 32, 32 /*40M HT-2SS*/ - }; + if (cmd_len >= 7) { + curr_ra_ratio = cmd_buf[5]; + curr_bw = cmd_buf[6]; + PHYDM_DBG(dm, DBG_RA, "RA retry ratio: [%d]:", curr_ra_ratio); + /**/ + } + + if (cmd_buf[3] != 0) { + if (cmd_buf[3] == 0xff) { + PHYDM_DBG(dm, DBG_RA, "FW Level: Fix rate[%d]:", macid); + /**/ + } else if (cmd_buf[3] == 1) { + PHYDM_DBG(dm, DBG_RA, "Try Success[%d]:", macid); + /**/ + } else if (cmd_buf[3] == 2) { + PHYDM_DBG(dm, DBG_RA, "Try Fail & Try Again[%d]:", macid); + /**/ + } else if (cmd_buf[3] == 3) { + PHYDM_DBG(dm, DBG_RA, "rate Back[%d]:", macid); + /**/ + } else if (cmd_buf[3] == 4) { + PHYDM_DBG(dm, DBG_RA, "start rate by RSSI[%d]:", macid); + /**/ + } else if (cmd_buf[3] == 5) { + PHYDM_DBG(dm, DBG_RA, "Try rate[%d]:", macid); + /**/ + } + } + + PHYDM_DBG(dm, DBG_RA, "Tx rate Update[%d]:", macid); + phydm_print_rate(dm, rate, DBG_RA); + + if (macid >= 128) { + u8 gid_index = macid - 128; + ra_tab->mu1_rate[gid_index] = rate; + } + + /*ra_tab->link_tx_rate[macid] = rate;*/ + + if (is_sta_active(sta)) { + sta->ra_info.curr_tx_rate = rate; + sta->ra_info.curr_tx_bw = (enum channel_width)curr_bw; + sta->ra_info.curr_retry_ratio= curr_ra_ratio; -#elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) + /*if (sta->ra_info.curr_tx_bw < sta->ra_info.ra_bw_mode)*/ + } -#elif (RTL8812A_SUPPORT == 1) + /*trigger power training*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#elif (RTL8814A_SUPPORT == 1) + rate_order = phydm_rate_order_compute(dm, rate_idx); -#else + if ((dm->is_one_entry_only) || + ((rate_order > ra_tab->highest_client_tx_order) && (ra_tab->power_tracking_flag == 1)) + ) { + halrf_update_pwr_track(dm, rate_idx); + ra_tab->power_tracking_flag = 0; + } -#endif #endif - memcpy(&(p_ra_table->per_rate_retrylimit_20M[0]), &(per_rate_retrylimit_table_20M[0]), ODM_NUM_RATE_IDX); - memcpy(&(p_ra_table->per_rate_retrylimit_40M[0]), &(per_rate_retrylimit_table_40M[0]), ODM_NUM_RATE_IDX); + /*trigger dynamic rate ID*/ +/*#if (defined(CONFIG_RA_DYNAMIC_RATE_ID))*/ /*dino will refine here later*/ +#if 0 + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) + phydm_update_rate_id(dm, rate, macid); +#endif - for (i = 0; i < ODM_NUM_RATE_IDX; i++) { - phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_20M[i]), 0); - phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_40M[i]), 0); - } } void -phydm_ra_dynamic_retry_limit_init( - void *p_dm_void +odm_ra_post_action_on_assoc( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; +#if 0 + struct dm_struct *dm = (struct dm_struct *)dm_void; - p_ra_table->retry_descend_num = RA_RETRY_DESCEND_NUM; - p_ra_table->retrylimit_low = RA_RETRY_LIMIT_LOW; - p_ra_table->retrylimit_high = RA_RETRY_LIMIT_HIGH; + dm->h2c_rarpt_connect = 1; + phydm_rssi_monitor_check(dm); + dm->h2c_rarpt_connect = 0; +#endif +} + +void +phydm_modify_RA_PCR_threshold( + void *dm_void, + u8 RA_offset_direction, + u8 RA_threshold_offset - phydm_reset_retry_limit_table(p_dm_odm); +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + ra_tab->RA_offset_direction = RA_offset_direction; + ra_tab->RA_threshold_offset = RA_threshold_offset; + PHYDM_DBG(dm, DBG_RA_MASK, "Set RA_threshold_offset = (( %s%d ))\n", ((RA_threshold_offset == 0) ? " " : ((RA_offset_direction) ? "+" : "-")), RA_threshold_offset); } -#endif +#if 0 /*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ void -phydm_ra_dynamic_retry_limit( - void *p_dm_void +odm_refresh_rate_adaptive_mask_mp( + void *dm_void ) { -#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 i, retry_offset; - u32 ma_rx_tp; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + void *adapter = dm->adapter; + void *target_adapter = NULL; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + PMGNT_INFO mgnt_info = GetDefaultMgntInfo(adapter); + void *loop_adapter = GetDefaultAdapter(adapter); + PMGNT_INFO p_loop_mgnt_info = &loop_adapter->MgntInfo; + HAL_DATA_TYPE *loop_hal_data = GET_HAL_DATA(loop_adapter); + + u32 i; + struct sta_info *entry; + u8 ratr_state_new; + PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__); - if (p_dm_odm->pre_number_active_client == p_dm_odm->number_active_client) { + if (adapter->bDriverStopped) { + PHYDM_DBG(dm, DBG_RA_MASK, "driver is going to unload\n"); + return; + } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" pre_number_active_client == number_active_client\n")); + if (!hal_data->bUseRAMask) { + PHYDM_DBG(dm, DBG_RA_MASK, "driver does not control rate adaptive mask\n"); return; + } - } else { - if (p_dm_odm->number_active_client == 1) { - phydm_reset_retry_limit_table(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("one client only->reset to default value\n")); - } else { + /* if default port is connected, update RA table for default port (infrastructure mode only) */ + /* Need to consider other ports for P2P cases*/ + + while(loop_adapter){ + p_loop_mgnt_info = &loop_adapter->MgntInfo; + loop_hal_data = GET_HAL_DATA(loop_adapter); + + if (p_loop_mgnt_info->mAssoc && (!ACTING_AS_AP(loop_adapter))) { + odm_refresh_ldpc_rts_mp(loop_adapter, dm, p_loop_mgnt_info->mMacId, p_loop_mgnt_info->IOTPeer, loop_hal_data->UndecoratedSmoothedPWDB); + /*PHYDM_DBG(dm, DBG_RA_MASK, "Infrasture mode\n");*/ - retry_offset = p_dm_odm->number_active_client * p_ra_table->retry_descend_num; + ratr_state_new = phydm_rssi_lv_dec(dm, loop_hal_data->UndecoratedSmoothedPWDB, p_loop_mgnt_info->Ratr_State); - for (i = 0; i < ODM_NUM_RATE_IDX; i++) { + if ((p_loop_mgnt_info->Ratr_State != ratr_state_new) || (ra_tab->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD)) { + ra_tab->up_ramask_cnt = 0; + PHYDM_PRINT_ADDR(dm, DBG_RA_MASK, ("Target AP addr :"), p_loop_mgnt_info->Bssid); + PHYDM_DBG(dm, DBG_RA_MASK, "Update RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n\n", + mgnt_info->Ratr_State, ratr_state_new, loop_hal_data->UndecoratedSmoothedPWDB); - phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_20M[i]), retry_offset); - phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_40M[i]), retry_offset); + p_loop_mgnt_info->Ratr_State = ratr_state_new; + adapter->HalFunc.UpdateHalRAMaskHandler(loop_adapter, p_loop_mgnt_info->mMacId, NULL); + } else { + PHYDM_DBG(dm, DBG_RA_MASK, "Stay in RA level = (( %d ))\n\n", ratr_state_new); + /**/ } } + + loop_adapter = GetNextExtAdapter(loop_adapter); } -#endif -} -#if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) -void -phydm_ra_dynamic_rate_id_on_assoc( - void *p_dm_void, - u8 wireless_mode, - u8 init_rate_id -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + /* */ + /* The following part configure AP/VWifi/IBSS rate adaptive mask. */ + /* */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n", p_dm_odm->rf_type, wireless_mode, init_rate_id)); + if (mgnt_info->mIbss) /* Target: AP/IBSS peer. */ + target_adapter = GetDefaultAdapter(adapter); + else + target_adapter = GetFirstAPAdapter(adapter); - if ((p_dm_odm->rf_type == ODM_2T2R) | (p_dm_odm->rf_type == ODM_2T2R_GREEN) | (p_dm_odm->rf_type == ODM_2T3R) | (p_dm_odm->rf_type == ODM_2T4R)) { + /* if extension port (softap) is started, updaet RA table for more than one clients associate */ + if (target_adapter != NULL) { + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + entry = AsocEntry_EnumStation(target_adapter, i); - if ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) && - (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) - ) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set N-2SS ARFR5 table\n")); - odm_set_mac_reg(p_dm_odm, 0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ - odm_set_mac_reg(p_dm_odm, 0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ - } else if ((p_dm_odm->support_ic_type & (ODM_RTL8812)) && - (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) - ) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set AC-2SS ARFR0 table\n")); - odm_set_mac_reg(p_dm_odm, 0x444, MASKDWORD, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ - odm_set_mac_reg(p_dm_odm, 0x448, MASKDWORD, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ - } - } - -} + if (is_sta_active((&GET_STA_INFO(entry)))) { + odm_refresh_ldpc_rts_mp(target_adapter, dm, GET_STA_INFO(entry).mac_id, entry->IOTPeer, GET_STA_INFO(entry).rssi_stat.rssi); -void -phydm_ra_dynamic_rate_id_init( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + ratr_state_new = phydm_rssi_lv_dec(dm, GET_STA_INFO(entry).rssi_stat.rssi, GET_STA_INFO(entry).ra_info.rssi_level); - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) { + if ((GET_STA_INFO(entry).ra_info.rssi_level != ratr_state_new) || (ra_tab->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD)) { + ra_tab->up_ramask_cnt = 0; + PHYDM_PRINT_ADDR(dm, DBG_RA_MASK, ("Target AP addr :"), GET_STA_INFO(entry).mac_addr); + PHYDM_DBG(dm, DBG_RA_MASK, "Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", + GET_STA_INFO(entry).ra_info.rssi_level, ratr_state_new, GET_STA_INFO(entry).rssi_stat.rssi); - odm_set_mac_reg(p_dm_odm, 0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ - odm_set_mac_reg(p_dm_odm, 0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ + GET_STA_INFO(entry).ra_info.rssi_level = ratr_state_new; + adapter->HalFunc.UpdateHalRAMaskHandler(target_adapter, GET_STA_INFO(entry).mac_id, entry); + } else { + PHYDM_DBG(dm, DBG_RA_MASK, "Stay in RA level = (( %d ))\n\n", ratr_state_new); + /**/ + } - odm_set_mac_reg(p_dm_odm, 0x444, MASKDWORD, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ - odm_set_mac_reg(p_dm_odm, 0x448, MASKDWORD, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ + } + } } } +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + void -phydm_update_rate_id( - void *p_dm_void, - u8 rate, - u8 platform_macid +odm_refresh_rate_adaptive_mask_ap( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 current_tx_ss; - u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ - u8 wireless_mode; - u8 phydm_macid; - struct sta_info *p_entry; - + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + struct rtl8192cd_priv *priv = dm->priv; + struct aid_obj *aidarray; + u32 i; + struct sta_info *entry; + struct cmn_sta_info *sta; + u8 ratr_state_new; -#if 0 - if (rate_idx >= ODM_RATEVHTSS2MCS0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( VHT2SS-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0))); - /*dummy for SD4 check patch*/ - } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( VHT1SS-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0))); - /*dummy for SD4 check patch*/ - } else if (rate_idx >= ODM_RATEMCS0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( HT-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEMCS0))); - /*dummy for SD4 check patch*/ - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( HT-MCS%d ))\n", platform_macid, rate_idx)); - /*dummy for SD4 check patch*/ - } -#endif + if (priv->up_time % 2) + return; - phydm_macid = p_dm_odm->platform2phydm_macid_table[platform_macid]; - p_entry = p_dm_odm->p_odm_sta_info[phydm_macid]; + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + entry = dm->odm_sta_info[i]; + sta = dm->phydm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { - wireless_mode = p_entry->wireless_mode; + if (is_sta_active(sta)) { + #if defined(UNIVERSAL_REPEATER) || defined(MBSSID) + aidarray = container_of(entry, struct aid_obj, station); + priv = aidarray->priv; + #endif - if ((p_dm_odm->rf_type == ODM_2T2R) | (p_dm_odm->rf_type == ODM_2T2R_GREEN) | (p_dm_odm->rf_type == ODM_2T3R) | (p_dm_odm->rf_type == ODM_2T4R)) { + if (!priv->pmib->dot11StationConfigEntry.autoRate) + continue; - p_entry->ratr_idx = p_entry->ratr_idx_init; - if (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) { /*N mode*/ - if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*2SS mode*/ + ratr_state_new = phydm_rssi_lv_dec(dm, (u32)sta->rssi_stat.rssi, sta->ra_info.rssi_level); - p_entry->ratr_idx = ARFR_5_RATE_ID; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_5\n")); - } - } else if (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) {/*AC mode*/ - if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*2SS mode*/ + if ((sta->ra_info.rssi_level != ratr_state_new) || (ra_tab->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD)) { + ra_tab->up_ramask_cnt = 0; + PHYDM_PRINT_ADDR(dm, DBG_RA_MASK, "Target AP addr :", sta->mac_addr); + PHYDM_DBG(dm, DBG_RA_MASK, "Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", sta->ra_info.rssi_level, ratr_state_new, sta->rssi_stat.rssi); - p_entry->ratr_idx = ARFR_0_RATE_ID; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_0\n")); - } + sta->ra_info.rssi_level = ratr_state_new; + phydm_gen_ramask_h2c_AP(dm, priv, entry, sta->ra_info.rssi_level); + } else { + PHYDM_DBG(dm, DBG_RA_MASK, "Stay in RA level = (( %d ))\n\n", ratr_state_new); + /**/ } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("UPdate_RateID[%d]: (( 0x%x ))\n", platform_macid, p_entry->ratr_idx)); } } - } #endif void -phydm_print_rate( - void *p_dm_void, - u8 rate, - u32 dbg_component +phydm_rate_adaptive_mask_init( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; - u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ - u8 vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0; - u8 b_sgi = (rate & 0x80) >> 7; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER adapter = (PADAPTER)dm->adapter; + PMGNT_INFO mgnt_info = &(adapter->MgntInfo); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + + if (mgnt_info->DM_Type == dm_type_by_driver) + hal_data->bUseRAMask = true; + else + hal_data->bUseRAMask = false; + +#endif + + ra_t->ldpc_thres = 35; + ra_t->up_ramask_cnt = 0; + ra_t->up_ramask_cnt_tmp = 0; - ODM_RT_TRACE_F(p_dm_odm, dbg_component, ODM_DBG_LOUD, ("( %s%s%s%s%d%s%s)\n", - ((rate_idx >= ODM_RATEVHTSS1MCS0) && (rate_idx <= ODM_RATEVHTSS1MCS9)) ? "VHT 1ss " : "", - ((rate_idx >= ODM_RATEVHTSS2MCS0) && (rate_idx <= ODM_RATEVHTSS2MCS9)) ? "VHT 2ss " : "", - ((rate_idx >= ODM_RATEVHTSS3MCS0) && (rate_idx <= ODM_RATEVHTSS3MCS9)) ? "VHT 3ss " : "", - (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", - (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0) % 10) : ((rate_idx >= ODM_RATEMCS0) ? (rate_idx - ODM_RATEMCS0) : ((rate_idx <= ODM_RATE54M) ? legacy_table[rate_idx] : 0)), - (b_sgi) ? "-S" : " ", - (rate_idx >= ODM_RATEMCS0) ? "" : "M")); } void -phydm_c2h_ra_report_handler( - void *p_dm_void, - u8 *cmd_buf, - u8 cmd_len +phydm_refresh_rate_adaptive_mask( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 macid = cmd_buf[1]; - u8 rate = cmd_buf[0]; - u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ - u8 rate_order; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - - GET_HAL_DATA(adapter)->CurrentRARate = HwRateToMRate(rate_idx); -#endif + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__); - if (cmd_len >= 4) { - if (cmd_buf[3] == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("TX Init-rate Update[%d]:", macid)); - /**/ - } else if (cmd_buf[3] == 0xff) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("FW Level: Fix rate[%d]:", macid)); - /**/ - } else if (cmd_buf[3] == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Success[%d]:", macid)); - /**/ - } else if (cmd_buf[3] == 2) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Fail & Try Again[%d]:", macid)); - /**/ - } else if (cmd_buf[3] == 3) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate Back[%d]:", macid)); - /**/ - } else if (cmd_buf[3] == 4) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("start rate by RSSI[%d]:", macid)); - /**/ - } else if (cmd_buf[3] == 5) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try rate[%d]:", macid)); - /**/ - } - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Tx rate Update[%d]:", macid)); - /**/ + if (!(dm->support_ability & ODM_BB_RA_MASK)) { + PHYDM_DBG(dm, DBG_RA_MASK, "Return: Not support\n"); + return; } - /*phydm_print_rate(p_dm_odm, pre_rate_idx, ODM_COMP_RATE_ADAPTIVE);*/ - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (">\n",macid );*/ - phydm_print_rate(p_dm_odm, rate, ODM_COMP_RATE_ADAPTIVE); + if (!dm->is_linked) + return; - p_ra_table->link_tx_rate[macid] = rate; + ra_t->up_ramask_cnt++; + /*ra_t->up_ramask_cnt_tmp++;*/ + - /*trigger power training*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - rate_order = phydm_rate_order_compute(p_dm_odm, rate_idx); + odm_refresh_rate_adaptive_mask_ap(dm); - if ((p_dm_odm->is_one_entry_only) || - ((rate_order > p_ra_table->highest_client_tx_order) && (p_ra_table->power_tracking_flag == 1)) - ) { - phydm_update_pwr_track(p_dm_odm, rate_idx); - p_ra_table->power_tracking_flag = 0; - } +#else -#endif + phydm_ra_mask_watchdog(dm); - /*trigger dynamic rate ID*/ -#if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) - phydm_update_rate_id(p_dm_odm, rate, macid); #endif - + } void -odm_rssi_monitor_init( - void *p_dm_void +phydm_show_sta_info( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num ) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + struct ra_sta_info *ra = NULL; + #ifdef CONFIG_BEAMFORMING + struct bf_cmn_info *bf = NULL; + #endif + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 i, macid_start, macid_end; + u8 tatal_sta_num = 0; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "All STA: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "STA[macid]: {2} {macid}\n"); + return; + } else if (var1[0] == 1) { + macid_start = 0; + macid_end = ODM_ASSOCIATE_ENTRY_NUM; + } else if (var1[0] == 2) { + macid_start = var1[1]; + macid_end = var1[1]; + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Warning input value!\n"); + return; + } + + for (i = macid_start; i < macid_end; i++) { + + sta = dm->phydm_sta_info[i]; - p_ra_table->PT_collision_pre = true; /*used in odm_dynamic_arfb_select(WIN only)*/ - p_hal_data->UndecoratedSmoothedPWDB = -1; - p_hal_data->ra_rpt_linked = false; -#endif + if (!is_sta_active(sta)) + continue; - p_ra_table->firstconnect = false; + ra = &sta->ra_info; + #ifdef CONFIG_BEAMFORMING + bf = &sta->bf_info; + #endif + + tatal_sta_num++; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "==[MACID: %d]============>\n", sta->mac_id); + PDM_SNPF(out_len, used, output + used, out_len - used, + "AID:%d\n", sta->aid); + PDM_SNPF(out_len, used, output + used, out_len - used, + "ADDR:%x-%x-%x-%x-%x-%x\n", + sta->mac_addr[5], sta->mac_addr[4], + sta->mac_addr[3], sta->mac_addr[2], + sta->mac_addr[1], sta->mac_addr[0]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "DM_ctrl:0x%x\n", sta->dm_ctrl); + PDM_SNPF(out_len, used, output + used, out_len - used, + "BW:%d, MIMO_Type:0x%x\n", sta->bw_mode, + sta->mimo_type); + PDM_SNPF(out_len, used, output + used, out_len - used, + "STBC_en:%d, LDPC_en=%d\n", sta->stbc_en, + sta->ldpc_en); + + /*[RSSI Info]*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "RSSI{All, OFDM, CCK}={%d, %d, %d}\n", + sta->rssi_stat.rssi, sta->rssi_stat.rssi_ofdm, + sta->rssi_stat.rssi_cck); + + /*[RA Info]*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "Rate_ID:%d, RSSI_LV:%d, ra_bw:%d, SGI_en:%d\n", + + ra->rate_id, ra->rssi_level, ra->ra_bw_mode, + ra->is_support_sgi); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "VHT_en:%d, Wireless_set=0x%x, sm_ps=%d\n", + ra->is_vht_enable, sta->support_wireless_set, + sta->sm_ps); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Dis{RA, PT}={%d, %d}, TxRx:%d, Noisy:%d\n", + ra->disable_ra, ra->disable_pt, ra->txrx_state, + ra->is_noisy); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "TX{Rate, BW}={0x%x, %d}, RTY:%d\n", + ra->curr_tx_rate, ra->curr_tx_bw, + ra->curr_retry_ratio); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "RA_Mask:0x%llx\n", ra->ramask); + + /*[TP]*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "TP{TX,RX}={%d, %d}\n", + sta->tx_moving_average_tp, + sta->rx_moving_average_tp); + + #ifdef CONFIG_BEAMFORMING + /*[Beamforming]*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "BF CAP{HT,VHT}={0x%x, 0x%x}\n", + bf->ht_beamform_cap, bf->vht_beamform_cap); + PDM_SNPF(out_len, used, output + used, out_len - used, + "BF {p_aid,g_id}={0x%x, 0x%x}\n\n", + bf->p_aid, bf->g_id); + #endif + } + + if (tatal_sta_num == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "No Linked STA\n"); + } + + *_used = used; + *_out_len = out_len; +} +#ifdef PHYDM_3RD_REFORM_RA_MASK -#endif +u8 +phydm_get_tx_stream_num( + void *dm_void, + enum rf_type mimo_type + +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 tx_num = 1; + + if (mimo_type == RF_1T1R || mimo_type == RF_1T2R) + tx_num = 1; + else if (mimo_type == RF_2T2R || mimo_type == RF_2T3R || mimo_type == RF_2T4R) + tx_num = 2; + else if (mimo_type == RF_3T3R || mimo_type == RF_3T4R) + tx_num = 3; + else if (mimo_type == RF_4T4R) + tx_num = 4; + else { + PHYDM_DBG(dm, DBG_RA, "[Warrning] no mimo_type is found\n"); + } + return tx_num; } -void -odm_ra_post_action_on_assoc( - void *p_dm_void +u64 +phydm_get_bb_mod_ra_mask( + void *dm_void, + u8 macid ) { -#if 0 - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct ra_sta_info *ra = NULL; + enum channel_width bw = (enum channel_width)0; + enum wireless_set wireless_mode = (enum wireless_set)0; + u8 tx_stream_num = 1; + u8 rssi_lv = 0; + u64 ra_mask_bitmap = 0; + + if (is_sta_active(sta)) { + + ra = &sta->ra_info; + bw = ra->ra_bw_mode; + wireless_mode = sta->support_wireless_set; + tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type); + rssi_lv = ra->rssi_level; + ra_mask_bitmap = ra->ramask; + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid sta_info\n", __func__); + return 0; + } - p_dm_odm->h2c_rarpt_connect = 1; - odm_rssi_monitor_check(p_dm_odm); - p_dm_odm->h2c_rarpt_connect = 0; -#endif + PHYDM_DBG(dm, DBG_RA, "macid=%d ori_RA_Mask= 0x%llx\n", sta->mac_id, ra_mask_bitmap); + PHYDM_DBG(dm, DBG_RA, "wireless_mode=0x%x, tx_stream_num=%d, BW=%d, MimoPs=%d, rssi_lv=%d\n", + wireless_mode, tx_stream_num, bw, sta->sm_ps, rssi_lv); + + if (sta->sm_ps == SM_PS_STATIC) /*mimo_ps_enable*/ + tx_stream_num = 1; + + + /*[Modify RA Mask by Wireless Mode]*/ + + if (wireless_mode == WIRELESS_CCK) /*B mode*/ + ra_mask_bitmap &= 0x0000000f; + else if (wireless_mode == WIRELESS_OFDM) /*G mode*/ + ra_mask_bitmap &= 0x00000ff0; + else if (wireless_mode == (WIRELESS_CCK | WIRELESS_OFDM)) /*BG mode*/ + ra_mask_bitmap &= 0x00000ff5; + else if (wireless_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) { + /*N_2G*/ + if (tx_stream_num == 1) { + if (bw == CHANNEL_WIDTH_40) + ra_mask_bitmap &= 0x000ff015; + else + ra_mask_bitmap &= 0x000ff005; + } else if (tx_stream_num == 2) { + if (bw == CHANNEL_WIDTH_40) + ra_mask_bitmap &= 0x0ffff015; + else + ra_mask_bitmap &= 0x0ffff005; + } else if (tx_stream_num == 3) + ra_mask_bitmap &= 0xffffff015; + } else if (wireless_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*N_5G*/ + + if (tx_stream_num == 1) { + if (bw == CHANNEL_WIDTH_40) + ra_mask_bitmap &= 0x000ff030; + else + ra_mask_bitmap &= 0x000ff010; + } else if (tx_stream_num == 2) { + if (bw == CHANNEL_WIDTH_40) + ra_mask_bitmap &= 0x0ffff030; + else + ra_mask_bitmap &= 0x0ffff010; + } else if (tx_stream_num == 3) + ra_mask_bitmap &= 0xffffff010; + } else if (wireless_mode == (WIRELESS_CCK |WIRELESS_OFDM | WIRELESS_VHT)) { + /*AC_2G*/ + if (tx_stream_num == 1) + ra_mask_bitmap &= 0x003ff015; + else if (tx_stream_num == 2) + ra_mask_bitmap &= 0xfffff015; + else if (tx_stream_num == 3) + ra_mask_bitmap &= 0x3fffffff010; + + + if (bw == CHANNEL_WIDTH_20) {/* AC 20MHz doesn't support MCS9 */ + ra_mask_bitmap &= 0x1ff7fdfffff; + } + } else if (wireless_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*AC_5G*/ + + if (tx_stream_num == 1) + ra_mask_bitmap &= 0x003ff010; + else if (tx_stream_num == 2) + ra_mask_bitmap &= 0xfffff010; + else if (tx_stream_num == 3) + ra_mask_bitmap &= 0x3fffffff010; + + if (bw == CHANNEL_WIDTH_20) /* AC 20MHz doesn't support MCS9 */ + ra_mask_bitmap &= 0x1ff7fdfffff; + } else { + PHYDM_DBG(dm, DBG_RA, "[Warrning] No RA mask is found\n"); + /**/ + } + + PHYDM_DBG(dm, DBG_RA, "Mod by mode=0x%llx\n", ra_mask_bitmap); + + + /*[Modify RA Mask by RSSI level]*/ + if (wireless_mode != WIRELESS_CCK) { + if (rssi_lv == 0) + ra_mask_bitmap &= 0xffffffffffffffff; + else if (rssi_lv == 1) + ra_mask_bitmap &= 0xfffffffffffffff0; + else if (rssi_lv == 2) + ra_mask_bitmap &= 0xffffffffffffefe0; + else if (rssi_lv == 3) + ra_mask_bitmap &= 0xffffffffffffcfc0; + else if (rssi_lv == 4) + ra_mask_bitmap &= 0xffffffffffff8f80; + else if (rssi_lv >= 5) + ra_mask_bitmap &= 0xffffffffffff0f00; + + } + PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap); + + return ra_mask_bitmap; } -void -phydm_init_ra_info( - void *p_dm_void +u8 +phydm_get_rate_id( + void *dm_void, + u8 macid ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct ra_sta_info *ra =NULL; + enum channel_width bw = (enum channel_width)0; + enum wireless_set wireless_mode = (enum wireless_set)0; + u8 tx_stream_num = 1; + u8 rate_id_idx = PHYDM_BGN_20M_1SS; + + if (is_sta_active(sta)) { + + ra = &sta->ra_info; + bw = ra->ra_bw_mode; + wireless_mode = sta->support_wireless_set; + tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type); -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - u32 ret_value; + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s: invalid sta_info\n", __func__); + return 0; + } + + PHYDM_DBG(dm, DBG_RA, "macid=%d, wireless_set=0x%x, tx_stream_num=%d, BW=0x%x\n", + sta->mac_id, wireless_mode, tx_stream_num, bw); + + if (wireless_mode == WIRELESS_CCK) /*B mode*/ + rate_id_idx = PHYDM_B_20M; + else if (wireless_mode == WIRELESS_OFDM) /*G mode*/ + rate_id_idx = PHYDM_G; + else if (wireless_mode == (WIRELESS_CCK | WIRELESS_OFDM)) /*BG mode*/ + rate_id_idx = PHYDM_BG; + else if (wireless_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*GN mode*/ + + if (tx_stream_num == 1) + rate_id_idx = PHYDM_GN_N1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_GN_N2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR5_N_3SS; + } else if (wireless_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) { /*BGN mode*/ + + + if (bw == CHANNEL_WIDTH_40) { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_BGN_40M_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_BGN_40M_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR5_N_3SS; - ret_value = odm_get_bb_reg(p_dm_odm, 0x4c8, MASKBYTE2); - odm_set_bb_reg(p_dm_odm, 0x4cc, MASKBYTE3, (ret_value - 1)); + } else { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_BGN_20M_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_BGN_20M_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR5_N_3SS; + } + } else if (wireless_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*AC mode*/ + + if (tx_stream_num == 1) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR4_AC_3SS; + } else if (wireless_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) { /*AC 2.4G mode*/ + + if (bw >= CHANNEL_WIDTH_80) { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR4_AC_3SS; + } else { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR4_AC_3SS; + } + } else { + PHYDM_DBG(dm, DBG_RA, "[Warrning] No rate_id is found\n"); + rate_id_idx = 0; } -#endif + + PHYDM_DBG(dm, DBG_RA, "Rate_ID=((0x%x))\n", rate_id_idx); + + return rate_id_idx; } void -phydm_modify_RA_PCR_threshold( - void *p_dm_void, - u8 RA_offset_direction, - u8 RA_threshold_offset - +phydm_ra_h2c( + void *dm_void, + u8 macid, + u8 dis_ra, + u8 dis_pt, + u8 no_update_bw, + u8 init_ra_lv, + u64 ra_mask ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct ra_sta_info *ra = NULL; + u8 h2c_val[H2C_MAX_LENGTH] = {0}; - p_ra_table->RA_offset_direction = RA_offset_direction; - p_ra_table->RA_threshold_offset = RA_threshold_offset; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Set RA_threshold_offset = (( %s%d ))\n", ((RA_threshold_offset == 0) ? " " : ((RA_offset_direction) ? "+" : "-")), RA_threshold_offset)); + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid sta_info\n", __func__); + return; + } + + PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id); + + if (dm->is_disable_power_training == true) + dis_pt = true; + else if (dm->is_disable_power_training == false) + dis_pt = false; + + h2c_val[0] = sta->mac_id; + h2c_val[1] = (ra->rate_id & 0x1f) | ((init_ra_lv & 0x3) << 5) | (ra->is_support_sgi << 7); + h2c_val[2] = (u8)((ra->ra_bw_mode) | (((sta->ldpc_en) ? 1 : 0) << 2) | + ((no_update_bw & 0x1) << 3) | (ra->is_vht_enable << 4) | + ((dis_pt & 0x1) << 6) | ((dis_ra & 0x1) << 7)); + + h2c_val[3] = (u8)(ra_mask & 0xff); + h2c_val[4] = (u8)((ra_mask & 0xff00) >> 8); + h2c_val[5] = (u8)((ra_mask & 0xff0000) >> 16); + h2c_val[6] = (u8)((ra_mask & 0xff000000) >> 24); + + PHYDM_DBG(dm, DBG_RA, "PHYDM h2c[0x40]=0x%x %x %x %x %x %x %x\n", + h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2], h2c_val[1], h2c_val[0]); + + odm_fill_h2c_cmd(dm, PHYDM_H2C_RA_MASK, H2C_MAX_LENGTH, h2c_val); + + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) { + + h2c_val[3] = (u8)((ra_mask >> 32) & 0x000000ff); + h2c_val[4] = (u8)(((ra_mask >> 32) & 0x0000ff00) >> 8); + h2c_val[5] = (u8)(((ra_mask >> 32) & 0x00ff0000) >> 16); + h2c_val[6] = (u8)(((ra_mask >> 32) & 0xff000000) >> 24); + + PHYDM_DBG(dm, DBG_RA, "PHYDM h2c[0x46]=0x%x %x %x %x %x %x %x\n", + h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2], h2c_val[1], h2c_val[0]); + + odm_fill_h2c_cmd(dm, PHYDM_RA_MASK_ABOVE_3SS, 5, h2c_val); + } + #endif } void -odm_rssi_monitor_check_mp( - void *p_dm_void +phydm_ra_registed( + void *dm_void, + u8 macid, + u8 rssi_from_assoc ) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; - u32 i; - boolean is_ext_ra_info = true; - u8 cmdlen = H2C_0X42_LENGTH; - u8 tx_bf_en = 0, stbc_en = 0; - - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct sta_info *p_entry = NULL; - s32 tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff; - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; - PMGNT_INFO p_default_mgnt_info = &adapter->MgntInfo; - u64 cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0; -#if (BEAMFORMING_SUPPORT == 1) -#ifndef BEAMFORMING_VERSION_1 - enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; -#endif -#endif - struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(adapter); - - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - is_ext_ra_info = false; - cmdlen = 3; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct ra_sta_info *ra = NULL; + u8 init_ra_lv; + u64 ra_mask; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n", __func__); + PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", macid); + return; } - while (p_loop_adapter) { + PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d, rssi_from_assoc=%d\n", + sta->mac_id, rssi_from_assoc); - if (p_loop_adapter != NULL) { - p_mgnt_info = &p_loop_adapter->MgntInfo; - cur_tx_ok_cnt = p_loop_adapter->TxStats.NumTxBytesUnicast - p_mgnt_info->lastTxOkCnt; - cur_rx_ok_cnt = p_loop_adapter->RxStats.NumRxBytesUnicast - p_mgnt_info->lastRxOkCnt; - p_mgnt_info->lastTxOkCnt = cur_tx_ok_cnt; - p_mgnt_info->lastRxOkCnt = cur_rx_ok_cnt; - } + #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) + ra->rate_id = phydm_get_rate_id_88e(dm, macid); + else + #endif + { + ra->rate_id = phydm_get_rate_id(dm, macid); + } + + /*ra->is_vht_enable = (sta->support_wireless_set | WIRELESS_VHT) ? 1 : 0;*/ + /*ra->disable_ra = 0;*/ + /*ra->disable_pt = 0;*/ + ra_mask = phydm_get_bb_mod_ra_mask(dm, macid); - for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) { - if (IsAPModeExist(p_loop_adapter)) { - if (GetFirstExtAdapter(p_loop_adapter) != NULL && - GetFirstExtAdapter(p_loop_adapter) == p_loop_adapter) - p_entry = AsocEntry_EnumStation(p_loop_adapter, i); - else if (GetFirstGOPort(p_loop_adapter) != NULL && - IsFirstGoAdapter(p_loop_adapter)) - p_entry = AsocEntry_EnumStation(p_loop_adapter, i); - } else { - if (GetDefaultAdapter(p_loop_adapter) == p_loop_adapter) - p_entry = AsocEntry_EnumStation(p_loop_adapter, i); - } + if (rssi_from_assoc > 40) + init_ra_lv = 3; + else if (rssi_from_assoc > 20) + init_ra_lv = 2; + else + init_ra_lv = 1; - if (p_entry != NULL) { - if (p_entry->bAssociated) { + if (ra_t->record_ra_info) + ra_t->record_ra_info(dm, macid, sta, ra_mask); - RT_DISP_ADDR(FDM, DM_PWDB, ("p_entry->mac_addr ="), p_entry->MacAddr); - RT_DISP(FDM, DM_PWDB, ("p_entry->rssi = 0x%x(%d)\n", - p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_stat.undecorated_smoothed_pwdb)); + #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) + /*Driver RA*/ + odm_ra_update_rate_info_8188e(dm, macid, ra->rate_id, (u32)ra_mask, ra->is_support_sgi); + else + #endif + { + /*FW RA*/ + phydm_ra_h2c(dm, macid, ra->disable_ra, ra->disable_pt, 0, init_ra_lv, ra_mask); + } - /* 2 BF_en */ -#if (BEAMFORMING_SUPPORT == 1) -#ifndef BEAMFORMING_VERSION_1 - beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(p_dm_odm, p_entry->AssociatedMacId); - if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) - tx_bf_en = 1; -#else - if (Beamform_GetSupportBeamformerCap(GetDefaultAdapter(adapter), p_entry)) - tx_bf_en = 1; -#endif -#endif - /* 2 STBC_en */ - if ((IS_WIRELESS_MODE_AC(adapter) && TEST_FLAG(p_entry->VHTInfo.STBC, STBC_VHT_ENABLE_TX)) || - TEST_FLAG(p_entry->HTInfo.STBC, STBC_HT_ENABLE_TX)) - stbc_en = 1; - - if (p_entry->rssi_stat.undecorated_smoothed_pwdb < tmp_entry_min_pwdb) - tmp_entry_min_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - if (p_entry->rssi_stat.undecorated_smoothed_pwdb > tmp_entry_max_pwdb) - tmp_entry_max_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - - h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); - - if (is_ext_ra_info) { - if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6)) - h2c_parameter[3] |= RAINFO_BE_RX_STATE; - - if (tx_bf_en) - h2c_parameter[3] |= RAINFO_BF_STATE; - else { - if (stbc_en) - h2c_parameter[3] |= RAINFO_STBC_STATE; - } - - if (p_dm_odm->noisy_decision) - h2c_parameter[3] |= RAINFO_NOISY_STATE; - else - h2c_parameter[3] &= (~RAINFO_NOISY_STATE); -#if 1 - if (p_dm_odm->h2c_rarpt_connect) { - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("h2c_rarpt_connect = (( %d ))\n", p_dm_odm->h2c_rarpt_connect)); - } -#else + - if (p_entry->rssi_stat.ra_rpt_linked == false) { - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - p_entry->rssi_stat.ra_rpt_linked = true; +} - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("RA First Link, RSSI[%d] = ((%d))\n", - p_entry->associated_mac_id, p_entry->rssi_stat.undecorated_smoothed_pwdb)); - } -#endif - } +void +phydm_ra_offline( + void *dm_void, + u8 macid +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct ra_sta_info *ra = NULL; - h2c_parameter[2] = (u8)(p_entry->rssi_stat.undecorated_smoothed_pwdb & 0xFF); - /* h2c_parameter[1] = 0x20; */ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 */ - h2c_parameter[0] = (p_entry->AssociatedMacId); + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid sta_info\n", __func__); + return; + } - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); - } - } else - break; - } + PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id); - p_loop_adapter = GetNextExtAdapter(p_loop_adapter); - } + odm_memory_set(dm, &ra->rate_id, 0, sizeof(struct ra_sta_info)); + ra->disable_ra = 1; + ra->disable_pt = 1; + if (ra_t->record_ra_info) + ra_t->record_ra_info(dm, macid, sta, 0); - /*Default port*/ - if (tmp_entry_max_pwdb != 0) { /* If associated entry is found */ - p_hal_data->EntryMaxUndecoratedSmoothedPWDB = tmp_entry_max_pwdb; - RT_DISP(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n", tmp_entry_max_pwdb, tmp_entry_max_pwdb)); - } else - p_hal_data->EntryMaxUndecoratedSmoothedPWDB = 0; + if (dm->support_ic_type != ODM_RTL8188E) + phydm_ra_h2c(dm, macid, ra->disable_ra, ra->disable_pt, 0, 0, 0); +} - if (tmp_entry_min_pwdb != 0xff) { /* If associated entry is found */ - p_hal_data->EntryMinUndecoratedSmoothedPWDB = tmp_entry_min_pwdb; - RT_DISP(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", tmp_entry_min_pwdb, tmp_entry_min_pwdb)); +void +phydm_ra_mask_watchdog( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + struct cmn_sta_info *sta = NULL; + struct ra_sta_info *ra = NULL; + u8 macid; + u64 ra_mask; + u8 rssi_lv_new; + + if (!(dm->support_ability & ODM_BB_RA_MASK)) + return; + + if (((!dm->is_linked)) || (dm->phydm_sys_up_time % 2) == 1) + return; - } else - p_hal_data->EntryMinUndecoratedSmoothedPWDB = 0; + PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__); + + ra_t->up_ramask_cnt++; - /* Default porti sent RSSI to FW */ - if (p_hal_data->bUseRAMask) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("1 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", - WIN_DEFAULT_PORT_MACID, p_hal_data->UndecoratedSmoothedPWDB, p_hal_data->ra_rpt_linked)); - if (p_hal_data->UndecoratedSmoothedPWDB > 0) { + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + + sta = dm->phydm_sta_info[macid]; + + if (!is_sta_active(sta)) + continue; - PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_default_mgnt_info); - PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_default_mgnt_info); + ra = &sta->ra_info; - /* BF_en*/ -#if (BEAMFORMING_SUPPORT == 1) -#ifndef BEAMFORMING_VERSION_1 - beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(p_dm_odm, p_default_mgnt_info->m_mac_id); + if (ra->disable_ra) + continue; - if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) - tx_bf_en = 1; -#else - if (Beamform_GetSupportBeamformerCap(GetDefaultAdapter(adapter), NULL)) - tx_bf_en = 1; -#endif -#endif - - /* STBC_en*/ - if ((IS_WIRELESS_MODE_AC(adapter) && TEST_FLAG(p_vht_info->VhtCurStbc, STBC_VHT_ENABLE_TX)) || - TEST_FLAG(p_ht_info->HtCurStbc, STBC_HT_ENABLE_TX)) - stbc_en = 1; - - h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); - - if (is_ext_ra_info) { - if (tx_bf_en) - h2c_parameter[3] |= RAINFO_BF_STATE; - else { - if (stbc_en) - h2c_parameter[3] |= RAINFO_STBC_STATE; - } - -#if 1 - if (p_dm_odm->h2c_rarpt_connect) { - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("h2c_rarpt_connect = (( %d ))\n", p_dm_odm->h2c_rarpt_connect)); - } -#else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("2 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", - WIN_DEFAULT_PORT_MACID, p_hal_data->undecorated_smoothed_pwdb, p_hal_data->ra_rpt_linked)); - - if (p_hal_data->ra_rpt_linked == false) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("3 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", - WIN_DEFAULT_PORT_MACID, p_hal_data->undecorated_smoothed_pwdb, p_hal_data->ra_rpt_linked)); - - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - p_hal_data->ra_rpt_linked = true; - - - } -#endif - - if (p_dm_odm->noisy_decision == 1) { - h2c_parameter[3] |= RAINFO_NOISY_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] Send H2C to FW\n")); - } else - h2c_parameter[3] &= (~RAINFO_NOISY_STATE); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] h2c_parameter=%x\n", h2c_parameter[3])); - } - - h2c_parameter[2] = (u8)(p_hal_data->UndecoratedSmoothedPWDB & 0xFF); - /*h2c_parameter[1] = 0x20;*/ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ - h2c_parameter[0] = WIN_DEFAULT_PORT_MACID; /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ - - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); - } - - /* BT 3.0 HS mode rssi */ - if (p_dm_odm->is_bt_hs_operation) { - h2c_parameter[2] = p_dm_odm->bt_hs_rssi; - /* h2c_parameter[1] = 0x0; */ - h2c_parameter[0] = WIN_BT_PORT_MACID; - - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); - } - } else - PlatformEFIOWrite1Byte(adapter, 0x4fe, (u8)p_hal_data->UndecoratedSmoothedPWDB); - - if ((p_dm_odm->support_ic_type == ODM_RTL8812) || (p_dm_odm->support_ic_type == ODM_RTL8192E)) - odm_rssi_dump_to_register(p_dm_odm); - - - { - struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(adapter); - boolean default_pointer_value, *p_is_link_temp = &default_pointer_value; - s32 global_rssi_min = 0xFF, local_rssi_min; - boolean is_link = false; - - while (p_loop_adapter) { - local_rssi_min = phydm_find_minimum_rssi(p_dm_odm, p_loop_adapter, p_is_link_temp); - /* dbg_print("p_hal_data->is_linked=%d, local_rssi_min=%d\n", p_hal_data->is_linked, local_rssi_min); */ - - if (*p_is_link_temp) - is_link = true; - - if ((local_rssi_min < global_rssi_min) && (*p_is_link_temp)) - global_rssi_min = local_rssi_min; - - p_loop_adapter = GetNextExtAdapter(p_loop_adapter); - } - - p_hal_data->bLinked = is_link; - odm_cmn_info_update(&p_hal_data->DM_OutSrc, ODM_CMNINFO_LINK, (u64)is_link); - - if (is_link) - odm_cmn_info_update(&p_hal_data->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, (u64)global_rssi_min); - else - odm_cmn_info_update(&p_hal_data->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, 0); - - } - -#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && !defined(DM_ODM_CE_MAC80211) -/*H2C_RSSI_REPORT*/ -s8 phydm_rssi_report(struct PHY_DM_STRUCT *p_dm_odm, u8 mac_id) -{ - struct _ADAPTER *adapter = p_dm_odm->adapter; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter); - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; - u8 UL_DL_STATE = 0, STBC_TX = 0, tx_bf_en = 0; - u8 cmdlen = H2C_0X42_LENGTH, first_connect = _FALSE; - u64 cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0; - struct sta_info *p_entry = p_dm_odm->p_odm_sta_info[mac_id]; - - if (!IS_STA_VALID(p_entry)) - return _FAIL; - - if (mac_id != p_entry->mac_id) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u:%u invalid\n", __func__, mac_id, p_entry->mac_id)); - rtw_warn_on(1); - return _FAIL; - } - - if (IS_MCAST(p_entry->hwaddr)) /*if(psta->mac_id ==1)*/ - return _FAIL; - - if (p_dm_odm->is_in_lps_pg) - return _FAIL; - - if (p_entry->rssi_stat.undecorated_smoothed_pwdb == (-1)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi == -1\n", __func__, p_entry->mac_id, MAC_ARG(p_entry->hwaddr))); - return _FAIL; - } - - cur_tx_ok_cnt = pdvobjpriv->traffic_stat.cur_tx_bytes; - cur_rx_ok_cnt = pdvobjpriv->traffic_stat.cur_rx_bytes; - if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6)) - UL_DL_STATE = 1; - else - UL_DL_STATE = 0; - -#ifdef CONFIG_BEAMFORMING - { -#if (BEAMFORMING_SUPPORT == 1) - enum beamforming_cap beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(p_dm_odm, p_entry->mac_id); -#else/*for drv beamforming*/ - enum beamforming_cap beamform_cap = beamforming_get_entry_beam_cap_by_mac_id(&adapter->mlmepriv, p_entry->mac_id); -#endif - - if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) - tx_bf_en = 1; - else - tx_bf_en = 0; - } -#endif /*#ifdef CONFIG_BEAMFORMING*/ - - if (tx_bf_en) - STBC_TX = 0; - else { -#ifdef CONFIG_80211AC_VHT - if (is_supported_vht(p_entry->wireless_mode)) - STBC_TX = TEST_FLAG(p_entry->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX); - else -#endif -#ifdef CONFIG_80211N_HT - STBC_TX = TEST_FLAG(p_entry->htpriv.stbc_cap, STBC_HT_ENABLE_TX); -#endif - } - - h2c_parameter[0] = (u8)(p_entry->mac_id & 0xFF); - h2c_parameter[2] = p_entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F; - - if (UL_DL_STATE) - h2c_parameter[3] |= RAINFO_BE_RX_STATE; - - if (tx_bf_en) - h2c_parameter[3] |= RAINFO_BF_STATE; - if (STBC_TX) - h2c_parameter[3] |= RAINFO_STBC_STATE; - if (p_dm_odm->noisy_decision) - h2c_parameter[3] |= RAINFO_NOISY_STATE; - - if ((p_entry->ra_rpt_linked == _FALSE) && (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_SEND)) { - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - p_entry->ra_rpt_linked = _TRUE; - p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_HOLD; - first_connect = _TRUE; - } - - h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); - -#if 1 - if (first_connect) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__, - p_entry->mac_id, MAC_ARG(p_entry->hwaddr), p_entry->rssi_stat.undecorated_smoothed_pwdb)); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s RAINFO - TP:%s, TxBF:%s, STBC:%s, Noisy:%s, Firstcont:%s\n", __func__, - (UL_DL_STATE) ? "DL" : "UL", (tx_bf_en) ? "EN" : "DIS", (STBC_TX) ? "EN" : "DIS", - (p_dm_odm->noisy_decision) ? "True" : "False", (first_connect) ? "True" : "False")); - } -#endif - - if (p_hal_data->fw_ractrl == _TRUE) { -#if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - cmdlen = 3; -#endif - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); - } else { -#if ((RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - odm_ra_set_rssi_8188e(p_dm_odm, (u8)(p_entry->mac_id & 0xFF), p_entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F); -#endif - } - return _SUCCESS; -} - -void phydm_ra_rssi_rpt_wk_hdl(void *p_context) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_context; - int i; - u8 mac_id = 0xFF; - struct sta_info *p_entry = NULL; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { - if (IS_MCAST(p_entry->hwaddr)) /*if(psta->mac_id ==1)*/ - continue; - if (p_entry->ra_rpt_linked == _FALSE) { - mac_id = i; - break; - } - } - } - if (mac_id != 0xFF) - phydm_rssi_report(p_dm_odm, mac_id); -} -void phydm_ra_rssi_rpt_wk(void *p_context) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_context; - - rtw_run_in_thread_cmd(p_dm_odm->adapter, phydm_ra_rssi_rpt_wk_hdl, p_dm_odm); -} -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) -void -odm_rssi_monitor_check_ce( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - struct rtl_priv *rtlpriv = (struct rtl_priv *)p_dm_odm->adapter; - struct rtl_mac *mac = rtl_mac(rtlpriv); - struct rtl_sta_info *p_entry; - int i; - int tmp_entry_min_pwdb = 0xff; - unsigned long cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0; - u8 UL_DL_STATE = 0, STBC_TX = 0, tx_bf_en = 0; - u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; - u8 cmdlen = H2C_0X42_LENGTH; - u8 macid = 0; - - if (p_dm_odm->is_linked != _TRUE) - return; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = (struct rtl_sta_info *)p_dm_odm->p_odm_sta_info[i]; - if (!IS_STA_VALID(p_entry)) - continue; - - if (is_multicast_ether_addr(p_entry->mac_addr) || - is_broadcast_ether_addr(p_entry->mac_addr)) - continue; - - if (p_entry->rssi_stat.undecorated_smoothed_pwdb == (-1)) - continue; - - /* calculate min_pwdb */ - if (p_entry->rssi_stat.undecorated_smoothed_pwdb < tmp_entry_min_pwdb) - tmp_entry_min_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - - /* report RSSI */ - cur_tx_ok_cnt = rtlpriv->stats.txbytesunicast_inperiod; - cur_rx_ok_cnt = rtlpriv->stats.rxbytesunicast_inperiod; - - if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6)) - UL_DL_STATE = 1; - else - UL_DL_STATE = 0; - - if (mac->opmode == NL80211_IFTYPE_AP || - mac->opmode == NL80211_IFTYPE_ADHOC) { - struct ieee80211_sta *sta = - container_of((void *)p_entry, struct ieee80211_sta, drv_priv); - macid = sta->aid + 1; - } - - h2c_parameter[0] = macid; - h2c_parameter[2] = p_entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F; - - if (UL_DL_STATE) - h2c_parameter[3] |= RAINFO_BE_RX_STATE; - - if (tx_bf_en) - h2c_parameter[3] |= RAINFO_BF_STATE; - if (STBC_TX) - h2c_parameter[3] |= RAINFO_STBC_STATE; - if (p_dm_odm->noisy_decision) - h2c_parameter[3] |= RAINFO_NOISY_STATE; - - if (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_SEND) { - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_HOLD; - } - - h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); - - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); - } - - if (tmp_entry_min_pwdb != 0xff) - p_dm_odm->rssi_min = tmp_entry_min_pwdb; -} -#else -void -odm_rssi_monitor_check_ce( - void *p_dm_void -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct sta_info *p_entry; - int i; - int tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff; - u8 sta_cnt = 0; - - if (p_dm_odm->is_linked != _TRUE) - return; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { - if (IS_MCAST(p_entry->hwaddr)) /*if(psta->mac_id ==1)*/ - continue; - - if (p_entry->rssi_stat.undecorated_smoothed_pwdb == (-1)) - continue; - if (p_entry->rssi_stat.undecorated_smoothed_pwdb < tmp_entry_min_pwdb) - tmp_entry_min_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - - if (p_entry->rssi_stat.undecorated_smoothed_pwdb > tmp_entry_max_pwdb) - tmp_entry_max_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - - if (phydm_rssi_report(p_dm_odm, i)) - sta_cnt++; + /*to be modified*/ + #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + if ((dm->support_ic_type == ODM_RTL8812) || + ((dm->support_ic_type == ODM_RTL8821) && (dm->cut_version == ODM_CUT_A)) + ) { + + if (sta->rssi_stat.rssi < ra_t->ldpc_thres) { + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + set_ra_ldpc_8812(sta, true); /*LDPC TX enable*/ + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + { + MgntSet_TX_LDPC(macid, true); + } + #endif + PHYDM_DBG(dm, DBG_RA_MASK, "RSSI=%d, ldpc_en =TRUE\n", sta->rssi_stat.rssi); + + } else if (sta->rssi_stat.rssi > (ra_t->ldpc_thres + 3)) { + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + set_ra_ldpc_8812(sta, false); /*LDPC TX disable*/ + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + { + MgntSet_TX_LDPC(macid, false); + } + #endif + PHYDM_DBG(dm, DBG_RA_MASK, "RSSI=%d, ldpc_en =FALSE\n", sta->rssi_stat.rssi); + } } - } - - if (tmp_entry_max_pwdb != 0) /* If associated entry is found */ - p_hal_data->entry_max_undecorated_smoothed_pwdb = tmp_entry_max_pwdb; - else - p_hal_data->entry_max_undecorated_smoothed_pwdb = 0; - - if (tmp_entry_min_pwdb != 0xff) /* If associated entry is found */ - p_hal_data->entry_min_undecorated_smoothed_pwdb = tmp_entry_min_pwdb; - else - p_hal_data->entry_min_undecorated_smoothed_pwdb = 0; - - find_minimum_rssi(adapter);/* get pdmpriv->min_undecorated_pwdb_for_dm */ - - p_dm_odm->rssi_min = p_hal_data->min_undecorated_pwdb_for_dm; - /* odm_cmn_info_update(&p_hal_data->odmpriv,ODM_CMNINFO_RSSI_MIN, pdmpriv->min_undecorated_pwdb_for_dm); */ -#endif/* if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ -} -#endif - - -void -odm_rssi_monitor_check_ap( - void *p_dm_void -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#if (RTL8812A_SUPPORT || RTL8881A_SUPPORT || RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8197F_SUPPORT) - - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; - u32 i; - boolean is_ext_ra_info = true; - u8 cmdlen = H2C_0X42_LENGTH; - u8 tx_bf_en = 0, stbc_en = 0; - - struct rtl8192cd_priv *priv = p_dm_odm->priv; - struct sta_info *pstat; - boolean act_bfer = false; - -#if (BEAMFORMING_SUPPORT == 1) - u8 idx = 0xff; -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; - p_dm_bdc_table->num_txbfee_client = 0; - p_dm_bdc_table->num_txbfer_client = 0; -#endif -#endif - if (!p_dm_odm->h2c_rarpt_connect && (priv->up_time % 2)) - return; - - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - is_ext_ra_info = false; - cmdlen = 3; - } - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - pstat = p_dm_odm->p_odm_sta_info[i]; - - if (IS_STA_VALID(pstat)) { - if (pstat->sta_in_firmware != 1) - continue; - - /* 2 BF_en */ -#if (BEAMFORMING_SUPPORT == 1) - BEAMFORMING_CAP beamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, pstat->aid); - PRT_BEAMFORMING_ENTRY p_entry = Beamforming_GetEntryByMacId(priv, pstat->aid, &idx); - - if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { - - if (p_entry->Sounding_En) - tx_bf_en = 1; - else - tx_bf_en = 0; - - act_bfer = true; - } - -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*BDC*/ - if (act_bfer == true) { - p_dm_bdc_table->w_bfee_client[i] = 1; /* AP act as BFer */ - p_dm_bdc_table->num_txbfee_client++; - } else { - p_dm_bdc_table->w_bfee_client[i] = 0; /* AP act as BFer */ - } - - if ((beamform_cap & BEAMFORMEE_CAP_HT_EXPLICIT) || (beamform_cap & BEAMFORMEE_CAP_VHT_SU)) { - p_dm_bdc_table->w_bfer_client[i] = 1; /* AP act as BFee */ - p_dm_bdc_table->num_txbfer_client++; - } else { - p_dm_bdc_table->w_bfer_client[i] = 0; /* AP act as BFer */ - } -#endif -#endif - - /* 2 STBC_en */ - if ((priv->pmib->dot11nConfigEntry.dot11nSTBC) && - ((pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_RX_STBC_CAP_)) -#ifdef RTK_AC_SUPPORT - || (pstat->vht_cap_buf.vht_cap_info & cpu_to_le32(_VHTCAP_RX_STBC_CAP_)) -#endif - )) - stbc_en = 1; - - /* 2 RAINFO */ - - h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); - - if (is_ext_ra_info) { - if ((pstat->rx_avarage) > ((pstat->tx_avarage) * 6)) - h2c_parameter[3] |= RAINFO_BE_RX_STATE; - - if (tx_bf_en) - h2c_parameter[3] |= RAINFO_BF_STATE; - else { - if (stbc_en) - h2c_parameter[3] |= RAINFO_STBC_STATE; - } - - if (p_dm_odm->noisy_decision) - h2c_parameter[3] |= RAINFO_NOISY_STATE; - else - h2c_parameter[3] &= (~RAINFO_NOISY_STATE); - - if (pstat->H2C_rssi_rpt) { - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[RA Init] set Init rate by RSSI, STA %d\n", pstat->aid)); - } - - /*ODM_RT_TRACE(p_dm_odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RAINFO] H2C_Para[3] = %x\n",h2c_parameter[3]));*/ + #endif + + rssi_lv_new = phydm_rssi_lv_dec(dm, (u32)sta->rssi_stat.rssi, ra->rssi_level); + + if ((ra->rssi_level != rssi_lv_new) || + (ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD)) { + PHYDM_DBG(dm, DBG_RA_MASK, "RSSI LV:((%d))->((%d))\n", ra->rssi_level, rssi_lv_new); + + ra->rssi_level = rssi_lv_new; + ra_t->up_ramask_cnt = 0; + + ra_mask = phydm_get_bb_mod_ra_mask(dm, macid); + + if (ra_t->record_ra_info) + ra_t->record_ra_info(dm, macid, sta, ra_mask); + + #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) + /*Driver RA*/ + odm_ra_update_rate_info_8188e(dm, macid, ra->rate_id, (u32)ra_mask, ra->is_support_sgi); + else + #endif + { + /*FW RA*/ + phydm_ra_h2c(dm, macid, ra->disable_ra, ra->disable_pt, 1, 0, ra_mask); } - - h2c_parameter[2] = (u8)(pstat->rssi & 0xFF); - h2c_parameter[0] = REMAP_AID(pstat); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("h2c_parameter[3]=%d\n", h2c_parameter[3])); - - /* ODM_RT_TRACE(p_dm_odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RSSI] H2C_Para[2] = %x,\n",h2c_parameter[2])); */ - /* ODM_RT_TRACE(p_dm_odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[MACID] H2C_Para[0] = %x,\n",h2c_parameter[0])); */ - - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); - } } -#endif -#endif - } - -void -odm_rssi_monitor_check( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (!(p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR)) - return; - - switch (p_dm_odm->support_platform) { - case ODM_WIN: - odm_rssi_monitor_check_mp(p_dm_odm); - break; - - case ODM_CE: - odm_rssi_monitor_check_ce(p_dm_odm); - break; - - case ODM_AP: - odm_rssi_monitor_check_ap(p_dm_odm); - break; - - default: - break; - } - -} - -void -odm_rate_adaptive_mask_init( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_RATE_ADAPTIVE *p_odm_ra = &p_dm_odm->rate_adaptive; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMGNT_INFO p_mgnt_info = &p_dm_odm->adapter->MgntInfo; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); - - p_mgnt_info->Ratr_State = DM_RATR_STA_INIT; - - if (p_mgnt_info->DM_Type == dm_type_by_driver) - p_hal_data->bUseRAMask = true; - else - p_hal_data->bUseRAMask = false; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - p_odm_ra->type = dm_type_by_driver; - if (p_odm_ra->type == dm_type_by_driver) - p_dm_odm->is_use_ra_mask = _TRUE; - else - p_dm_odm->is_use_ra_mask = _FALSE; -#endif - - p_odm_ra->ratr_state = DM_RATR_STA_INIT; - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - p_odm_ra->ldpc_thres = 50; - else - p_odm_ra->ldpc_thres = 35; - - p_odm_ra->rts_thres = 35; - -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - p_odm_ra->ldpc_thres = 35; - p_odm_ra->is_use_ldpc = false; - -#else - p_odm_ra->ultra_low_rssi_thresh = 9; - -#endif - - p_odm_ra->high_rssi_thresh = 50; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - p_odm_ra->low_rssi_thresh = 23; -#else - p_odm_ra->low_rssi_thresh = 20; #endif -} -/*----------------------------------------------------------------------------- - * Function: odm_refresh_rate_adaptive_mask() - * - * Overview: Update rate table mask according to rssi - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 05/27/2009 hpfan Create version 0. - * - *---------------------------------------------------------------------------*/ -void -odm_refresh_rate_adaptive_mask( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - - if (!p_dm_odm->is_linked) - return; - - if (!(p_dm_odm->support_ability & ODM_BB_RA_MASK)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_refresh_rate_adaptive_mask(): Return cos not supported\n")); - return; - } - - p_ra_table->force_update_ra_mask_count++; - /* */ - /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ - /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ - /* HW dynamic mechanism. */ - /* */ - switch (p_dm_odm->support_platform) { - case ODM_WIN: - odm_refresh_rate_adaptive_mask_mp(p_dm_odm); - break; - - case ODM_CE: - odm_refresh_rate_adaptive_mask_ce(p_dm_odm); - break; - - case ODM_AP: - odm_refresh_rate_adaptive_mask_apadsl(p_dm_odm); - break; - } - -} - -u8 -phydm_trans_platform_bw( - void *p_dm_void, - u8 BW -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (BW == CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == CHANNEL_WIDTH_40) - BW = PHYDM_BW_40; - - else if (BW == CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - - else if (BW == CHANNEL_WIDTH_160) - BW = PHYDM_BW_160; - - else if (BW == CHANNEL_WIDTH_80_80) - BW = PHYDM_BW_80_80; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - if (BW == HT_CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == HT_CHANNEL_WIDTH_20_40) - BW = PHYDM_BW_40; - - else if (BW == HT_CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - - else if (BW == HT_CHANNEL_WIDTH_160) - BW = PHYDM_BW_160; - - else if (BW == HT_CHANNEL_WIDTH_10) - BW = PHYDM_BW_10; - - else if (BW == HT_CHANNEL_WIDTH_5) - BW = PHYDM_BW_5; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - - if (BW == HT_CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == HT_CHANNEL_WIDTH_20_40) - BW = PHYDM_BW_40; - - else if (BW == HT_CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - if (BW == CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == CHANNEL_WIDTH_40) - BW = PHYDM_BW_40; - - else if (BW == CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - - else if (BW == CHANNEL_WIDTH_160) - BW = PHYDM_BW_160; - - else if (BW == CHANNEL_WIDTH_80_80) - BW = PHYDM_BW_80_80; -#endif - - return BW; - -} - -u8 -phydm_trans_platform_rf_type( - void *p_dm_void, - u8 rf_type -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (rf_type == RF_1T2R) - rf_type = PHYDM_RF_1T2R; - - else if (rf_type == RF_2T4R) - rf_type = PHYDM_RF_2T4R; - - else if (rf_type == RF_2T2R) - rf_type = PHYDM_RF_2T2R; - - else if (rf_type == RF_1T1R) - rf_type = PHYDM_RF_1T1R; - - else if (rf_type == RF_2T2R_GREEN) - rf_type = PHYDM_RF_2T2R_GREEN; - - else if (rf_type == RF_3T3R) - rf_type = PHYDM_RF_3T3R; - - else if (rf_type == RF_4T4R) - rf_type = PHYDM_RF_4T4R; - - else if (rf_type == RF_2T3R) - rf_type = PHYDM_RF_1T2R; - - else if (rf_type == RF_3T4R) - rf_type = PHYDM_RF_3T4R; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - if (rf_type == MIMO_1T2R) - rf_type = PHYDM_RF_1T2R; - - else if (rf_type == MIMO_2T4R) - rf_type = PHYDM_RF_2T4R; - - else if (rf_type == MIMO_2T2R) - rf_type = PHYDM_RF_2T2R; - - else if (rf_type == MIMO_1T1R) - rf_type = PHYDM_RF_1T1R; - - else if (rf_type == MIMO_3T3R) - rf_type = PHYDM_RF_3T3R; - - else if (rf_type == MIMO_4T4R) - rf_type = PHYDM_RF_4T4R; - - else if (rf_type == MIMO_2T3R) - rf_type = PHYDM_RF_1T2R; - - else if (rf_type == MIMO_3T4R) - rf_type = PHYDM_RF_3T4R; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - if (rf_type == RF_1T2R) - rf_type = PHYDM_RF_1T2R; - - else if (rf_type == RF_2T4R) - rf_type = PHYDM_RF_2T4R; - - else if (rf_type == RF_2T2R) - rf_type = PHYDM_RF_2T2R; - - else if (rf_type == RF_1T1R) - rf_type = PHYDM_RF_1T1R; - - else if (rf_type == RF_2T2R_GREEN) - rf_type = PHYDM_RF_2T2R_GREEN; - - else if (rf_type == RF_3T3R) - rf_type = PHYDM_RF_3T3R; - - else if (rf_type == RF_4T4R) - rf_type = PHYDM_RF_4T4R; - - else if (rf_type == RF_2T3R) - rf_type = PHYDM_RF_1T2R; - - else if (rf_type == RF_3T4R) - rf_type = PHYDM_RF_3T4R; - -#endif - - return rf_type; - -} - -u32 -phydm_trans_platform_wireless_mode( - void *p_dm_void, - u32 wireless_mode -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - if (wireless_mode == WIRELESS_11A) - wireless_mode = PHYDM_WIRELESS_MODE_A; - - else if (wireless_mode == WIRELESS_11B) - wireless_mode = PHYDM_WIRELESS_MODE_B; - - else if ((wireless_mode == WIRELESS_11G) || (wireless_mode == WIRELESS_11BG)) - wireless_mode = PHYDM_WIRELESS_MODE_G; - - else if (wireless_mode == WIRELESS_AUTO) - wireless_mode = PHYDM_WIRELESS_MODE_AUTO; - - else if ((wireless_mode == WIRELESS_11_24N) || (wireless_mode == WIRELESS_11G_24N) || (wireless_mode == WIRELESS_11B_24N) || - (wireless_mode == WIRELESS_11BG_24N) || (wireless_mode == WIRELESS_MODE_24G) || (wireless_mode == WIRELESS_11ABGN) || (wireless_mode == WIRELESS_11AGN)) - wireless_mode = PHYDM_WIRELESS_MODE_N_24G; - - else if ((wireless_mode == WIRELESS_11_5N) || (wireless_mode == WIRELESS_11A_5N)) - wireless_mode = PHYDM_WIRELESS_MODE_N_5G; - - else if ((wireless_mode == WIRELESS_11AC) || (wireless_mode == WIRELESS_11_5AC) || (wireless_mode == WIRELESS_MODE_5G)) - wireless_mode = PHYDM_WIRELESS_MODE_AC_5G; - - else if (wireless_mode == WIRELESS_11_24AC) - wireless_mode = PHYDM_WIRELESS_MODE_AC_24G; - - else if (wireless_mode == WIRELESS_11AC) - wireless_mode = PHYDM_WIRELESS_MODE_AC_ONLY; - - else if (wireless_mode == WIRELESS_MODE_MAX) - wireless_mode = PHYDM_WIRELESS_MODE_MAX; - else - wireless_mode = PHYDM_WIRELESS_MODE_UNKNOWN; -#endif - - return wireless_mode; - -} u8 phydm_vht_en_mapping( - void *p_dm_void, + void *dm_void, u32 wireless_mode ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 vht_en_out = 0; if ((wireless_mode == PHYDM_WIRELESS_MODE_AC_5G) || @@ -1900,52 +1322,40 @@ phydm_vht_en_mapping( /**/ } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n", wireless_mode, vht_en_out)); + PHYDM_DBG(dm, DBG_RA, "wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n", wireless_mode, vht_en_out); return vht_en_out; } u8 phydm_rate_id_mapping( - void *p_dm_void, + void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 rate_id_idx = 0; - u8 phydm_BW; - u8 phydm_rf_type; - phydm_BW = phydm_trans_platform_bw(p_dm_odm, bw); - phydm_rf_type = phydm_trans_platform_rf_type(p_dm_odm, rf_type); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - wireless_mode = phydm_trans_platform_wireless_mode(p_dm_odm, wireless_mode); -#endif - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n", - wireless_mode, phydm_rf_type, phydm_BW)); + PHYDM_DBG(dm, DBG_RA, "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n", + wireless_mode, rf_type, bw); switch (wireless_mode) { - case PHYDM_WIRELESS_MODE_N_24G: { - - if (phydm_BW == PHYDM_BW_40) { - - if (phydm_rf_type == PHYDM_RF_1T1R) + if (bw == CHANNEL_WIDTH_40) { + if (rf_type == RF_1T1R) rate_id_idx = PHYDM_BGN_40M_1SS; - else if (phydm_rf_type == PHYDM_RF_2T2R) + else if (rf_type == RF_2T2R) rate_id_idx = PHYDM_BGN_40M_2SS; else rate_id_idx = PHYDM_ARFR5_N_3SS; } else { - - if (phydm_rf_type == PHYDM_RF_1T1R) + if (rf_type == RF_1T1R) rate_id_idx = PHYDM_BGN_20M_1SS; - else if (phydm_rf_type == PHYDM_RF_2T2R) + else if (rf_type == RF_2T2R) rate_id_idx = PHYDM_BGN_20M_2SS; else rate_id_idx = PHYDM_ARFR5_N_3SS; @@ -1955,9 +1365,9 @@ phydm_rate_id_mapping( case PHYDM_WIRELESS_MODE_N_5G: { - if (phydm_rf_type == PHYDM_RF_1T1R) + if (rf_type == RF_1T1R) rate_id_idx = PHYDM_GN_N1SS; - else if (phydm_rf_type == PHYDM_RF_2T2R) + else if (rf_type == RF_2T2R) rate_id_idx = PHYDM_GN_N2SS; else rate_id_idx = PHYDM_ARFR5_N_3SS; @@ -1981,9 +1391,9 @@ phydm_rate_id_mapping( case PHYDM_WIRELESS_MODE_AC_5G: case PHYDM_WIRELESS_MODE_AC_ONLY: { - if (phydm_rf_type == PHYDM_RF_1T1R) + if (rf_type == RF_1T1R) rate_id_idx = PHYDM_ARFR1_AC_1SS; - else if (phydm_rf_type == PHYDM_RF_2T2R) + else if (rf_type == RF_2T2R) rate_id_idx = PHYDM_ARFR0_AC_2SS; else rate_id_idx = PHYDM_ARFR4_AC_3SS; @@ -1993,18 +1403,17 @@ phydm_rate_id_mapping( case PHYDM_WIRELESS_MODE_AC_24G: { /*Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/ - if (phydm_BW >= PHYDM_BW_80) { - if (phydm_rf_type == PHYDM_RF_1T1R) + if (bw >= CHANNEL_WIDTH_80) { + if (rf_type == RF_1T1R) rate_id_idx = PHYDM_ARFR1_AC_1SS; - else if (phydm_rf_type == PHYDM_RF_2T2R) + else if (rf_type == RF_2T2R) rate_id_idx = PHYDM_ARFR0_AC_2SS; else rate_id_idx = PHYDM_ARFR4_AC_3SS; } else { - - if (phydm_rf_type == PHYDM_RF_1T1R) + if (rf_type == RF_1T1R) rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; - else if (phydm_rf_type == PHYDM_RF_2T2R) + else if (rf_type == RF_2T2R) rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; else rate_id_idx = PHYDM_ARFR4_AC_3SS; @@ -2017,17 +1426,17 @@ phydm_rate_id_mapping( break; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA rate ID = (( 0x%x ))\n", rate_id_idx)); + PHYDM_DBG(dm, DBG_RA, "RA rate ID = (( 0x%x ))\n", rate_id_idx); return rate_id_idx; } void phydm_update_hal_ra_mask( - void *p_dm_void, + void *dm_void, u32 wireless_mode, u8 rf_type, - u8 BW, + u8 bw, u8 mimo_ps_enable, u8 disable_cck_rate, u32 *ratr_bitmap_msb_in, @@ -2035,24 +1444,13 @@ phydm_update_hal_ra_mask( u8 tx_rate_level ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 phydm_rf_type; - u8 phydm_BW; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 ratr_bitmap = *ratr_bitmap_lsb_in, ratr_bitmap_msb = *ratr_bitmap_msb_in; - /*struct _ODM_RATE_ADAPTIVE* p_ra = &(p_dm_odm->rate_adaptive);*/ -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - wireless_mode = phydm_trans_platform_wireless_mode(p_dm_odm, wireless_mode); -#endif - - phydm_rf_type = phydm_trans_platform_rf_type(p_dm_odm, rf_type); - phydm_BW = phydm_trans_platform_bw(p_dm_odm, BW); - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type));*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Platfoem original RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap)); + /*PHYDM_DBG(dm, DBG_RA_MASK, "phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type);*/ + PHYDM_DBG(dm, DBG_RA_MASK, "Platfoem original RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap); switch (wireless_mode) { - case PHYDM_WIRELESS_MODE_B: { ratr_bitmap &= 0x0000000f; @@ -2075,572 +1473,157 @@ phydm_update_hal_ra_mask( case PHYDM_WIRELESS_MODE_N_5G: { if (mimo_ps_enable) - phydm_rf_type = PHYDM_RF_1T1R; + rf_type = RF_1T1R; - if (phydm_rf_type == PHYDM_RF_1T1R) { - - if (phydm_BW == PHYDM_BW_40) + if (rf_type == RF_1T1R) { + if (bw == CHANNEL_WIDTH_40) ratr_bitmap &= 0x000ff015; else ratr_bitmap &= 0x000ff005; - } else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) { - - if (phydm_BW == PHYDM_BW_40) + } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) { + if (bw == CHANNEL_WIDTH_40) ratr_bitmap &= 0x0ffff015; else ratr_bitmap &= 0x0ffff005; } else { /*3T*/ - ratr_bitmap &= 0xfffff015; - ratr_bitmap_msb &= 0xf; - } - } - break; - - case PHYDM_WIRELESS_MODE_AC_24G: - { - if (phydm_rf_type == PHYDM_RF_1T1R) - ratr_bitmap &= 0x003ff015; - else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) - ratr_bitmap &= 0xfffff015; - else {/*3T*/ - - ratr_bitmap &= 0xfffff010; - ratr_bitmap_msb &= 0x3ff; - } - - if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ - ratr_bitmap &= 0x7fdfffff; - ratr_bitmap_msb &= 0x1ff; - } - } - break; - - case PHYDM_WIRELESS_MODE_AC_5G: - { - if (phydm_rf_type == PHYDM_RF_1T1R) - ratr_bitmap &= 0x003ff010; - else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) - ratr_bitmap &= 0xfffff010; - else {/*3T*/ - - ratr_bitmap &= 0xfffff010; - ratr_bitmap_msb &= 0x3ff; - } - - if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ - ratr_bitmap &= 0x7fdfffff; - ratr_bitmap_msb &= 0x1ff; - } - } - break; - - default: - break; - } - - if (wireless_mode != PHYDM_WIRELESS_MODE_B) { - - if (tx_rate_level == 0) - ratr_bitmap &= 0xffffffff; - else if (tx_rate_level == 1) - ratr_bitmap &= 0xfffffff0; - else if (tx_rate_level == 2) - ratr_bitmap &= 0xffffefe0; - else if (tx_rate_level == 3) - ratr_bitmap &= 0xffffcfc0; - else if (tx_rate_level == 4) - ratr_bitmap &= 0xffff8f80; - else if (tx_rate_level >= 5) - ratr_bitmap &= 0xffff0f00; - - } - - if (disable_cck_rate) - ratr_bitmap &= 0xfffffff0; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n", - wireless_mode, phydm_rf_type, phydm_BW, mimo_ps_enable, tx_rate_level)); - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap));*/ - - *ratr_bitmap_lsb_in = ratr_bitmap; - *ratr_bitmap_msb_in = ratr_bitmap_msb; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Phydm modified RA Mask = (( 0x %x | %x ))\n", *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in)); - -} - -u8 -phydm_RA_level_decision( - void *p_dm_void, - u32 rssi, - u8 ratr_state -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 ra_rate_floor_table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/ - u8 new_ratr_state = 0; - u8 i; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("curr RA level = ((%d)), Rate_floor_table ori [ %d , %d, %d , %d, %d, %d]\n", ratr_state, - ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5])); - - for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { - - if (i >= (ratr_state)) - ra_rate_floor_table[i] += RA_FLOOR_UP_GAP; - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI = ((%d)), Rate_floor_table_mod [ %d , %d, %d , %d, %d, %d]\n", - rssi, ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5])); - - for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { - - if (rssi < ra_rate_floor_table[i]) { - new_ratr_state = i; - break; - } - } - - - - return new_ratr_state; - -} - -void -odm_refresh_rate_adaptive_mask_mp( - void *p_dm_void -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - struct _ADAPTER *p_target_adapter = NULL; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(p_adapter); - struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(p_adapter); - PMGNT_INFO p_loop_mgnt_info = &(p_loop_adapter->MgntInfo); - HAL_DATA_TYPE *p_loop_hal_data = GET_HAL_DATA(p_loop_adapter); - - u32 i; - struct sta_info *p_entry; - u8 ratr_state_new; - - if (p_adapter->bDriverStopped) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_refresh_rate_adaptive_mask(): driver is going to unload\n")); - return; - } - - if (!p_hal_data->bUseRAMask) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_refresh_rate_adaptive_mask(): driver does not control rate adaptive mask\n")); - return; - } - - /* if default port is connected, update RA table for default port (infrastructure mode only) */ - /* Need to consider other ports for P2P cases*/ - - while(p_loop_adapter){ - - p_loop_mgnt_info = &(p_loop_adapter->MgntInfo); - p_loop_hal_data = GET_HAL_DATA(p_loop_adapter); - - if (p_loop_mgnt_info->mAssoc && (!ACTING_AS_AP(p_loop_adapter))) { - odm_refresh_ldpc_rts_mp(p_loop_adapter, p_dm_odm, p_loop_mgnt_info->mMacId, p_loop_mgnt_info->IOTPeer, p_loop_hal_data->UndecoratedSmoothedPWDB); - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Infrasture mode\n"));*/ - -#if RA_MASK_PHYDMLIZE_WIN - ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_loop_hal_data->UndecoratedSmoothedPWDB, p_loop_mgnt_info->Ratr_State); - - if ((p_loop_mgnt_info->Ratr_State != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { - - p_ra_table->force_update_ra_mask_count = 0; - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), p_loop_mgnt_info->Bssid); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n\n", - p_mgnt_info->Ratr_State, ratr_state_new, p_loop_hal_data->UndecoratedSmoothedPWDB)); - - p_loop_mgnt_info->Ratr_State = ratr_state_new; - p_adapter->HalFunc.UpdateHalRAMaskHandler(p_loop_adapter, p_loop_mgnt_info->mMacId, NULL, ratr_state_new); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); - /**/ - } - -#else - if (odm_ra_state_check(p_dm_odm, p_hal_data->UndecoratedSmoothedPWDB, p_mgnt_info->bSetTXPowerTrainingByOid, &p_mgnt_info->Ratr_State)) { - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), p_mgnt_info->Bssid); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_hal_data->UndecoratedSmoothedPWDB, p_mgnt_info->Ratr_State)); - p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, p_mgnt_info->Ratr_State); - } else if (p_dm_odm->is_change_state) { - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), p_mgnt_info->Bssid); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training state, is_disable_power_training = %d\n", p_dm_odm->is_disable_power_training)); - p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, p_mgnt_info->Ratr_State); - } -#endif - - } - - p_loop_adapter = GetNextExtAdapter(p_loop_adapter); - } - - /* */ - /* The following part configure AP/VWifi/IBSS rate adaptive mask. */ - /* */ - - if (p_mgnt_info->mIbss) /* Target: AP/IBSS peer. */ - p_target_adapter = GetDefaultAdapter(p_adapter); - else - p_target_adapter = GetFirstAPAdapter(p_adapter); - - /* if extension port (softap) is started, updaet RA table for more than one clients associate */ - if (p_target_adapter != NULL) { - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - - p_entry = AsocEntry_EnumStation(p_target_adapter, i); - - if (IS_STA_VALID(p_entry)) { - - odm_refresh_ldpc_rts_mp(p_target_adapter, p_dm_odm, p_entry->AssociatedMacId, p_entry->IOTPeer, p_entry->rssi_stat.undecorated_smoothed_pwdb); - -#if RA_MASK_PHYDMLIZE_WIN - ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->Ratr_State); - - if ((p_entry->Ratr_State != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { - - p_ra_table->force_update_ra_mask_count = 0; - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), p_entry->MacAddr); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", - p_entry->Ratr_State, ratr_state_new, p_entry->rssi_stat.undecorated_smoothed_pwdb)); - - p_entry->Ratr_State = ratr_state_new; - p_adapter->HalFunc.UpdateHalRAMaskHandler(p_target_adapter, p_entry->AssociatedMacId, p_entry, ratr_state_new); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); - /**/ - } - - -#else - - if (odm_ra_state_check(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_mgnt_info->bSetTXPowerTrainingByOid, &p_entry->Ratr_State)) { - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), p_entry->mac_addr); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->Ratr_State)); - p_adapter->hal_func.update_hal_ra_mask_handler(p_target_adapter, p_entry->AssociatedMacId, p_entry, p_entry->Ratr_State); - } else if (p_dm_odm->is_change_state) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training state, is_disable_power_training = %d\n", p_dm_odm->is_disable_power_training)); - p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, p_mgnt_info->Ratr_State); - } -#endif - - } - } - } - -#if RA_MASK_PHYDMLIZE_WIN - -#else - if (p_mgnt_info->bSetTXPowerTrainingByOid) - p_mgnt_info->bSetTXPowerTrainingByOid = false; -#endif -#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ -} - - -void -odm_refresh_rate_adaptive_mask_ce( - void *p_dm_void -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; -#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) - struct _ODM_RATE_ADAPTIVE *p_ra = &p_dm_odm->rate_adaptive; -#endif - u32 i; - struct sta_info *p_entry; - u8 ratr_state_new; - -#ifndef DM_ODM_CE_MAC80211 - if (RTW_CANNOT_RUN(p_adapter)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_refresh_rate_adaptive_mask(): driver is going to unload\n")); - return; - } -#endif - - if (!p_dm_odm->is_use_ra_mask) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_refresh_rate_adaptive_mask(): driver does not control rate adaptive mask\n")); - return; - } - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - - p_entry = p_dm_odm->p_odm_sta_info[i]; - - if (!IS_STA_VALID(p_entry)) { - continue; - } - -#ifdef DM_ODM_CE_MAC80211 - if (is_multicast_ether_addr(p_entry->mac_addr)) - continue; - else if (is_broadcast_ether_addr(p_entry->mac_addr)) - continue; -#else - if (IS_MCAST(p_entry->hwaddr)) - continue; -#endif - -#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) - if ((p_dm_odm->support_ic_type == ODM_RTL8812) || (p_dm_odm->support_ic_type == ODM_RTL8821)) { - if (p_entry->rssi_stat.undecorated_smoothed_pwdb < p_ra->ldpc_thres) { - p_ra->is_use_ldpc = true; - p_ra->is_lower_rts_rate = true; - if ((p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->cut_version == ODM_CUT_A)) - set_ra_ldpc_8812(p_entry, true); - /* dbg_print("RSSI=%d, is_use_ldpc = true\n", p_hal_data->undecorated_smoothed_pwdb); */ - } else if (p_entry->rssi_stat.undecorated_smoothed_pwdb > (p_ra->ldpc_thres - 5)) { - p_ra->is_use_ldpc = false; - p_ra->is_lower_rts_rate = false; - if ((p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->cut_version == ODM_CUT_A)) - set_ra_ldpc_8812(p_entry, false); - /* dbg_print("RSSI=%d, is_use_ldpc = false\n", p_hal_data->undecorated_smoothed_pwdb); */ - } - } -#endif - -#if RA_MASK_PHYDMLIZE_CE - ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_level); - - if ((p_entry->rssi_level != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { - - p_ra_table->force_update_ra_mask_count = 0; - /*ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pstat->hwaddr);*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", - p_entry->rssi_level, ratr_state_new, p_entry->rssi_stat.undecorated_smoothed_pwdb)); - - p_entry->rssi_level = ratr_state_new; -#ifdef DM_ODM_CE_MAC80211 - rtl_hal_update_ra_mask(p_adapter, p_entry, p_entry->rssi_level); -#else - rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE); -#endif - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); - /**/ - } -#else - if (true == odm_ra_state_check(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, false, &p_entry->rssi_level)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_level)); - /* printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.undecorated_smoothed_pwdb, pstat->rssi_level); */ - rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE); - } else if (p_dm_odm->is_change_state) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training state, is_disable_power_training = %d\n", p_dm_odm->is_disable_power_training)); - rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE); - } -#endif - - - } - -#endif -} - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -void -phydm_gen_ramask_h2c_AP( - void *p_dm_void, - struct rtl8192cd_priv *priv, - struct sta_info *p_entry, - u8 rssi_level -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (p_dm_odm->support_ic_type == ODM_RTL8812) { - -#if (RTL8812A_SUPPORT == 1) - UpdateHalRAMask8812(priv, p_entry, rssi_level); - /**/ -#endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - -#if (RTL8188E_SUPPORT == 1) -#ifdef TXREPORT - add_RATid(priv, p_entry); - /**/ -#endif -#endif - } else { - -#ifdef CONFIG_WLAN_HAL - GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, p_entry, rssi_level); -#endif - - } -} - -#endif - -void -odm_refresh_rate_adaptive_mask_apadsl( - void *p_dm_void -) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - struct rtl8192cd_priv *priv = p_dm_odm->priv; - struct aid_obj *aidarray; - u32 i; - struct sta_info *p_entry; - u8 ratr_state_new; - - if (priv->up_time % 2) - return; + ratr_bitmap &= 0xfffff015; + ratr_bitmap_msb &= 0xf; + } + } + break; - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; + case PHYDM_WIRELESS_MODE_AC_24G: + { + if (rf_type == RF_1T1R) + ratr_bitmap &= 0x003ff015; + else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) + ratr_bitmap &= 0xfffff015; + else {/*3T*/ - if (IS_STA_VALID(p_entry)) { + ratr_bitmap &= 0xfffff010; + ratr_bitmap_msb &= 0x3ff; + } -#if defined(UNIVERSAL_REPEATER) || defined(MBSSID) - aidarray = container_of(p_entry, struct aid_obj, station); - priv = aidarray->priv; -#endif + if (bw == CHANNEL_WIDTH_20) {/* AC 20MHz doesn't support MCS9 */ + ratr_bitmap &= 0x7fdfffff; + ratr_bitmap_msb &= 0x1ff; + } + } + break; - if (!priv->pmib->dot11StationConfigEntry.autoRate) - continue; + case PHYDM_WIRELESS_MODE_AC_5G: + { + if (rf_type == RF_1T1R) + ratr_bitmap &= 0x003ff010; + else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) + ratr_bitmap &= 0xfffff010; + else {/*3T*/ -#if RA_MASK_PHYDMLIZE_AP - ratr_state_new = phydm_RA_level_decision(p_dm_odm, (u32)p_entry->rssi, p_entry->rssi_level); + ratr_bitmap &= 0xfffff010; + ratr_bitmap_msb &= 0x3ff; + } - if ((p_entry->rssi_level != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { + if (bw == CHANNEL_WIDTH_20) {/* AC 20MHz doesn't support MCS9 */ + ratr_bitmap &= 0x7fdfffff; + ratr_bitmap_msb &= 0x1ff; + } + } + break; - p_ra_table->force_update_ra_mask_count = 0; - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), p_entry->hwaddr); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", p_entry->rssi_level, ratr_state_new, p_entry->rssi)); + default: + break; + } - p_entry->rssi_level = ratr_state_new; - phydm_gen_ramask_h2c_AP(p_dm_odm, priv, p_entry, p_entry->rssi_level); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); - /**/ - } + if (wireless_mode != PHYDM_WIRELESS_MODE_B) { + if (tx_rate_level == 0) + ratr_bitmap &= 0xffffffff; + else if (tx_rate_level == 1) + ratr_bitmap &= 0xfffffff0; + else if (tx_rate_level == 2) + ratr_bitmap &= 0xffffefe0; + else if (tx_rate_level == 3) + ratr_bitmap &= 0xffffcfc0; + else if (tx_rate_level == 4) + ratr_bitmap &= 0xffff8f80; + else if (tx_rate_level >= 5) + ratr_bitmap &= 0xffff0f00; -#else - if (odm_ra_state_check(p_dm_odm, (s32)p_entry->rssi, false, &p_entry->rssi_level)) { - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), p_entry->hwaddr); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_entry->rssi, p_entry->rssi_level)); - -#ifdef CONFIG_WLAN_HAL - if (IS_HAL_CHIP(priv)) { -#ifdef WDS - /*if(!(pstat->state & WIFI_WDS))*/ /*if WDS donot setting*/ -#endif - GET_HAL_INTERFACE(priv)->update_hal_ra_mask_handler(priv, p_entry, p_entry->rssi_level); - } else -#endif + } -#ifdef CONFIG_RTL_8812_SUPPORT - if (GET_CHIP_VER(priv) == VERSION_8812E) - update_hal_ra_mask8812(priv, p_entry, 3); - else -#endif - { -#ifdef CONFIG_RTL_88E_SUPPORT - if (GET_CHIP_VER(priv) == VERSION_8188E) { -#ifdef TXREPORT - add_ra_tid(priv, p_entry); -#endif - } -#endif + if (disable_cck_rate) + ratr_bitmap &= 0xfffffff0; + PHYDM_DBG(dm, DBG_RA_MASK, "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n", + wireless_mode, rf_type, bw, mimo_ps_enable, tx_rate_level); - } - } -#endif /*#ifdef RA_MASK_PHYDMLIZE*/ + /*PHYDM_DBG(dm, DBG_RA_MASK, "111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap);*/ + + *ratr_bitmap_lsb_in = ratr_bitmap; + *ratr_bitmap_msb_in = ratr_bitmap_msb; + PHYDM_DBG(dm, DBG_RA_MASK, "Phydm modified RA Mask = (( 0x %x | %x ))\n", *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in); - } - } -#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_AP)*/ } -void -odm_refresh_basic_rate_mask( - void *p_dm_void +u8 +phydm_rssi_lv_dec( + void *dm_void, + u32 rssi, + u8 ratr_state ) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - static u8 stage = 0; - u8 cur_stage = 0; - OCTET_STRING os_rate_set; - PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(adapter); - u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M}; - - if (p_dm_odm->support_ic_type != ODM_RTL8812 && p_dm_odm->support_ic_type != ODM_RTL8821) - return; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rssi_lv_table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/ + u8 new_rssi_lv = 0; + u8 i; - if (p_dm_odm->is_linked == false) /* unlink Default port information */ - cur_stage = 0; - else if (p_dm_odm->rssi_min < 40) /* link RSSI < 40% */ - cur_stage = 1; - else if (p_dm_odm->rssi_min > 45) /* link RSSI > 45% */ - cur_stage = 3; - else - cur_stage = 2; /* link 25% <= RSSI <= 30% */ + PHYDM_DBG(dm, DBG_RA_MASK, "curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\n", + ratr_state, rssi_lv_table[0], rssi_lv_table[1], rssi_lv_table[2], rssi_lv_table[3], rssi_lv_table[4], rssi_lv_table[5]); - if (cur_stage != stage) { - if (cur_stage == 1) { - FillOctetString(os_rate_set, rate_set, 5); - FilterSupportRate(p_mgnt_info->mBrates, &os_rate_set, false); - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set); - } else if (cur_stage == 3 && (stage == 1 || stage == 2)) - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_BASIC_RATE, (u8 *)(&p_mgnt_info->mBrates)); + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { + if (i >= (ratr_state)) + rssi_lv_table[i] += RA_FLOOR_UP_GAP; } - stage = cur_stage; -#endif + PHYDM_DBG(dm, DBG_RA_MASK, "RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\n", + rssi, rssi_lv_table[0], rssi_lv_table[1], rssi_lv_table[2], rssi_lv_table[3], rssi_lv_table[4], rssi_lv_table[5]); + + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { + if (rssi < rssi_lv_table[i]) { + new_rssi_lv = i; + break; + } + } + return new_rssi_lv; } u8 phydm_rate_order_compute( - void *p_dm_void, + void *dm_void, u8 rate_idx ) { u8 rate_order = 0; if (rate_idx >= ODM_RATEVHTSS4MCS0) { - rate_idx -= ODM_RATEVHTSS4MCS0; /**/ } else if (rate_idx >= ODM_RATEVHTSS3MCS0) { - rate_idx -= ODM_RATEVHTSS3MCS0; /**/ } else if (rate_idx >= ODM_RATEVHTSS2MCS0) { - rate_idx -= ODM_RATEVHTSS2MCS0; /**/ } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { - rate_idx -= ODM_RATEVHTSS1MCS0; /**/ } else if (rate_idx >= ODM_RATEMCS24) { - rate_idx -= ODM_RATEMCS24; /**/ } else if (rate_idx >= ODM_RATEMCS16) { - rate_idx -= ODM_RATEMCS16; /**/ } else if (rate_idx >= ODM_RATEMCS8) { - rate_idx -= ODM_RATEMCS8; /**/ } @@ -2650,89 +1633,191 @@ phydm_rate_order_compute( } +u8 +phydm_rate2ss( + void *dm_void, + u8 rate_idx +) +{ + u8 ret = 0xff; + u8 i,j; + u8 search_idx; + u32 ss_mapping_tab[4][3] = {{0x00000000, 0x003ff000, 0x000ff000}, + {0x00000000, 0xffc00000, 0x0ff00000}, + {0x000003ff, 0x0000000f, 0xf0000000}, + {0x000ffc00, 0x00000ff0, 0x00000000}}; + if (rate_idx < 32) { + search_idx = rate_idx; + j = 0; + } else if (rate_idx < 64) { + search_idx = rate_idx - 32; + j = 1; + } else { + search_idx = rate_idx -64; + j = 2; + } + for (i = 0; i<4; i++) + if (ss_mapping_tab[i][j] & BIT(search_idx)) + ret = i; + return ret; +} + +u8 +phydm_rate2plcp( + void *dm_void, + u8 rate_idx +) +{ + u8 rate2ss = 0; + u8 vht_en = 0; + u8 ltftime = 0; + u8 plcptime = 0xff; + + if (rate_idx < ODM_RATE6M) { + plcptime = 192; + /* CCK PLCP = 192us (long preamble) */ + } else if (rate_idx < ODM_RATEMCS0) { + plcptime = 20; + /* LegOFDM PLCP = 20us */ + } else { + if (rate_idx < ODM_RATEVHTSS1MCS0) + plcptime = 32; + /* HT mode PLCP = 20us + 12us + 4us x Nss */ + else + plcptime = 36; + /* VHT mode PLCP = 20us + 16us + 4us x Nss */ + rate2ss = phydm_rate2ss(dm_void, rate_idx); + if (rate2ss == 0xff) + return 0xff; + else + ltftime = (rate2ss + 1) * 4; + plcptime += ltftime; + /**/ + } + return plcptime; + +} + +u8 +phydm_get_plcp( + void *dm_void, + u16 macid +) +{ + u8 plcp_time = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + struct ra_sta_info *ra = NULL; + sta = dm->phydm_sta_info[macid]; + ra = &sta->ra_info; + plcp_time = phydm_rate2plcp(dm, ra->curr_tx_rate); + return plcp_time; +} + + void phydm_ra_common_info_update( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + struct cmn_sta_info *sta = NULL; u16 macid; u8 rate_order_tmp; u8 cnt = 0; - p_ra_table->highest_client_tx_order = 0; - p_ra_table->power_tracking_flag = 1; + ra_tab->highest_client_tx_order = 0; + ra_tab->power_tracking_flag = 1; + + if (!dm->number_linked_client) + return; - if (p_dm_odm->number_linked_client != 0) { - for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + sta = dm->phydm_sta_info[macid]; - rate_order_tmp = phydm_rate_order_compute(p_dm_odm, ((p_ra_table->link_tx_rate[macid]) & 0x7f)); + if (is_sta_active(sta)) { + rate_order_tmp = phydm_rate_order_compute(dm, (sta->ra_info.curr_tx_rate & 0x7f)); - if (rate_order_tmp >= (p_ra_table->highest_client_tx_order)) { - p_ra_table->highest_client_tx_order = rate_order_tmp; - p_ra_table->highest_client_tx_rate_order = macid; + if (rate_order_tmp >= (ra_tab->highest_client_tx_order)) { + ra_tab->highest_client_tx_order = rate_order_tmp; + ra_tab->highest_client_tx_rate_order = macid; } cnt++; - if (cnt == p_dm_odm->number_linked_client) + if (cnt == dm->number_linked_client) break; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("MACID[%d], Highest Tx order Update for power traking: %d\n", (p_ra_table->highest_client_tx_rate_order), (p_ra_table->highest_client_tx_order))); } + PHYDM_DBG(dm, DBG_RA, "MACID[%d], Highest Tx order Update for power traking: %d\n", (ra_tab->highest_client_tx_rate_order), (ra_tab->highest_client_tx_order)); } void phydm_ra_info_watchdog( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - phydm_ra_common_info_update(p_dm_odm); - phydm_ra_dynamic_retry_limit(p_dm_odm); - phydm_ra_dynamic_retry_count(p_dm_odm); - odm_refresh_rate_adaptive_mask(p_dm_odm); - odm_refresh_basic_rate_mask(p_dm_odm); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + phydm_ra_common_info_update(dm); + #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) + phydm_ra_dynamic_retry_limit(dm); + #endif + phydm_ra_dynamic_retry_count(dm); + phydm_refresh_rate_adaptive_mask(dm); + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + odm_refresh_basic_rate_mask(dm); + #endif } void phydm_ra_info_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; - p_ra_table->highest_client_tx_rate_order = 0; - p_ra_table->highest_client_tx_order = 0; - p_ra_table->RA_threshold_offset = 0; - p_ra_table->RA_offset_direction = 0; + ra_tab->highest_client_tx_rate_order = 0; + ra_tab->highest_client_tx_order = 0; + ra_tab->RA_threshold_offset = 0; + ra_tab->RA_offset_direction = 0; + +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + u32 ret_value; -#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - phydm_ra_dynamic_retry_limit_init(p_dm_odm); + ret_value = odm_get_bb_reg(dm, 0x4c8, MASKBYTE2); + odm_set_bb_reg(dm, 0x4cc, MASKBYTE3, (ret_value - 1)); + } #endif + + #ifdef CONFIG_RA_DYNAMIC_RTY_LIMIT + phydm_ra_dynamic_retry_limit_init(dm); + #endif -#if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) - phydm_ra_dynamic_rate_id_init(p_dm_odm); -#endif -#if (defined(CONFIG_RA_DBG_CMD)) - odm_ra_para_adjust_init(p_dm_odm); -#endif + #ifdef CONFIG_RA_DYNAMIC_RATE_ID + phydm_ra_dynamic_rate_id_init(dm); + #endif -} + #ifdef CONFIG_RA_DBG_CMD + odm_ra_para_adjust_init(dm); + #endif + phydm_rate_adaptive_mask_init(dm); + +} -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) u8 odm_find_rts_rate( - void *p_dm_void, + void *dm_void, u8 tx_rate, - boolean is_erp_protect + boolean is_erp_protect ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 rts_ini_rate = ODM_RATE6M; if (is_erp_protect) /* use CCK rate as RTS*/ @@ -2811,7 +1896,7 @@ odm_find_rts_rate( } } - if (*p_dm_odm->p_band_type == 1) { + if (*dm->band_type == ODM_BAND_5G) { if (rts_ini_rate < ODM_RATE6M) rts_ini_rate = ODM_RATE6M; } @@ -2819,739 +1904,538 @@ odm_find_rts_rate( } +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void -odm_set_ra_dm_arfb_by_noisy( - struct PHY_DM_STRUCT *p_dm_odm +odm_refresh_basic_rate_mask( + void *dm_void ) { -#if 0 + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + static u8 stage = 0; + u8 cur_stage = 0; + OCTET_STRING os_rate_set; + PMGNT_INFO mgnt_info = GetDefaultMgntInfo(((PADAPTER)adapter)); + u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M}; - /*dbg_print("DM_ARFB ====>\n");*/ - if (p_dm_odm->is_noisy_state) { - odm_write_4byte(p_dm_odm, 0x430, 0x00000000); - odm_write_4byte(p_dm_odm, 0x434, 0x05040200); - /*dbg_print("DM_ARFB ====> Noisy state\n");*/ - } else { - odm_write_4byte(p_dm_odm, 0x430, 0x02010000); - odm_write_4byte(p_dm_odm, 0x434, 0x07050403); - /*dbg_print("DM_ARFB ====> Clean state\n");*/ - } -#endif -} + if (dm->support_ic_type != ODM_RTL8812 && dm->support_ic_type != ODM_RTL8821) + return; -void -odm_update_noisy_state( - void *p_dm_void, - boolean is_noisy_state_from_c2h -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + if (dm->is_linked == false) /* unlink Default port information */ + cur_stage = 0; + else if (dm->rssi_min < 40) /* link RSSI < 40% */ + cur_stage = 1; + else if (dm->rssi_min > 45) /* link RSSI > 45% */ + cur_stage = 3; + else + cur_stage = 2; /* link 25% <= RSSI <= 30% */ -/* JJ ADD 20161014 */ - /*dbg_print("Get C2H Command! NoisyState=0x%x\n ", is_noisy_state_from_c2h);*/ - if (p_dm_odm->support_ic_type == ODM_RTL8821 || p_dm_odm->support_ic_type == ODM_RTL8812 || - p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B) - p_dm_odm->is_noisy_state = is_noisy_state_from_c2h; - odm_set_ra_dm_arfb_by_noisy(p_dm_odm); -}; + if (cur_stage != stage) { + if (cur_stage == 1) { + FillOctetString(os_rate_set, rate_set, 5); + FilterSupportRate(mgnt_info->mBrates, &os_rate_set, false); + phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set); + } else if (cur_stage == 3 && (stage == 1 || stage == 2)) + phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)(&mgnt_info->mBrates)); + } + + stage = cur_stage; +} +#if 0 void -phydm_update_pwr_track( - void *p_dm_void, - u8 rate +odm_refresh_ldpc_rts_mp( + void *adapter, + struct dm_struct *dm, + u8 m_mac_id, + u8 iot_peer, + s32 undecorated_smoothed_pwdb ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - u8 path_idx = 0; -#endif + boolean is_ctl_ldpc = false; + struct ra_table *ra_t = &dm->dm_ra_table; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Pwr Track Get rate=0x%x\n", rate)); + if (dm->support_ic_type != ODM_RTL8821 && dm->support_ic_type != ODM_RTL8812) + return; - p_dm_odm->tx_rate = rate; + if ((dm->support_ic_type == ODM_RTL8821) && (dm->cut_version == ODM_CUT_A)) + is_ctl_ldpc = true; + else if (dm->support_ic_type == ODM_RTL8812 && + iot_peer == HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP) + is_ctl_ldpc = true; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#if DEV_BUS_TYPE == RT_PCI_INTERFACE -#if USE_WORKITEM - odm_schedule_work_item(&p_dm_odm->ra_rpt_workitem); -#else - if (p_dm_odm->support_ic_type == ODM_RTL8821) { -#if (RTL8821A_SUPPORT == 1) - odm_tx_pwr_track_set_pwr8821a(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); -#endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { - for (path_idx = ODM_RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) { -#if (RTL8812A_SUPPORT == 1) - odm_tx_pwr_track_set_pwr8812a(p_dm_odm, MIX_MODE, path_idx, 0); -#endif - } - } else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { -#if (RTL8723B_SUPPORT == 1) - odm_tx_pwr_track_set_pwr_8723b(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); -#endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - for (path_idx = ODM_RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) { -#if (RTL8192E_SUPPORT == 1) - odm_tx_pwr_track_set_pwr92_e(p_dm_odm, MIX_MODE, path_idx, 0); -#endif - } - } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { -#if (RTL8188E_SUPPORT == 1) - odm_tx_pwr_track_set_pwr88_e(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); -#endif + if (is_ctl_ldpc) { + if (undecorated_smoothed_pwdb < (ra_t->ldpc_thres - 5)) + MgntSet_TX_LDPC(m_mac_id, true); + else if (undecorated_smoothed_pwdb > ra_t->ldpc_thres) + MgntSet_TX_LDPC(m_mac_id, false); } -#endif -#else - odm_schedule_work_item(&p_dm_odm->ra_rpt_workitem); -#endif -#endif - } +#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -s32 -phydm_find_minimum_rssi( - struct PHY_DM_STRUCT *p_dm_odm, - struct _ADAPTER *p_adapter, - OUT boolean *p_is_link_temp +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +void +phydm_gen_ramask_h2c_AP( + void *dm_void, + struct rtl8192cd_priv *priv, + struct sta_info *entry, + u8 rssi_level ) { - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - PMGNT_INFO p_mgnt_info = &(p_adapter->MgntInfo); - boolean act_as_ap = ACTING_AS_AP(p_adapter); + struct dm_struct *dm = (struct dm_struct *)dm_void; - /* 1.Determine the minimum RSSI */ - if ((!p_mgnt_info->bMediaConnect) || - (act_as_ap && (p_hal_data->EntryMinUndecoratedSmoothedPWDB == 0))) {/* We should check AP mode and Entry info.into consideration, revised by Roger, 2013.10.18*/ - - p_hal_data->MinUndecoratedPWDBForDM = 0; - *p_is_link_temp = false; + if (dm->support_ic_type == ODM_RTL8812) { + #if (RTL8812A_SUPPORT == 1) + UpdateHalRAMask8812(priv, entry, rssi_level); + /**/ + #endif + } else if (dm->support_ic_type == ODM_RTL8188E) { + #if (RTL8188E_SUPPORT == 1) + #ifdef TXREPORT + add_RATid(priv, entry); + /**/ + #endif + #endif + } else { + #ifdef CONFIG_WLAN_HAL + GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, entry, rssi_level); + #endif + } +} - } else - *p_is_link_temp = true; +#endif +#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - if (p_mgnt_info->bMediaConnect) { /* Default port*/ +void +phydm_retry_limit_table_bound( + void *dm_void, + u8 *retry_limit, + u8 offset +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; - if (act_as_ap || p_mgnt_info->mIbss) { - p_hal_data->MinUndecoratedPWDBForDM = p_hal_data->EntryMinUndecoratedSmoothedPWDB; - /**/ - } else { - p_hal_data->MinUndecoratedPWDBForDM = p_hal_data->UndecoratedSmoothedPWDB; - /**/ - } - } else { /* associated entry pwdb*/ - p_hal_data->MinUndecoratedPWDBForDM = p_hal_data->EntryMinUndecoratedSmoothedPWDB; - /**/ - } + if (*retry_limit > offset) { + *retry_limit -= offset; - return p_hal_data->MinUndecoratedPWDBForDM; + if (*retry_limit < ra_tab->retrylimit_low) + *retry_limit = ra_tab->retrylimit_low; + else if (*retry_limit > ra_tab->retrylimit_high) + *retry_limit = ra_tab->retrylimit_high; + } else + *retry_limit = ra_tab->retrylimit_low; } void -odm_update_init_rate_work_item_callback( - void *p_context +phydm_reset_retry_limit_table( + void *dm_void ) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - u8 p = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 i; - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - odm_tx_pwr_track_set_pwr8821a(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); - /**/ - } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { - for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) { /*DOn't know how to include &c*/ + u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = { + 1, 1, 2, 4, /*CCK*/ + 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ + 2, 4, 6, 8, 12, 18, 20, 22, /*20M HT-1SS*/ + 2, 4, 6, 8, 12, 18, 20, 22 /*20M HT-2SS*/ + }; + u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = { + 1, 1, 2, 4, /*CCK*/ + 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ + 4, 8, 12, 16, 24, 32, 32, 32, /*40M HT-1SS*/ + 4, 8, 12, 16, 24, 32, 32, 32 /*40M HT-2SS*/ + }; - odm_tx_pwr_track_set_pwr8812a(p_dm_odm, MIX_MODE, p, 0); - /**/ - } - } else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - odm_tx_pwr_track_set_pwr_8723b(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); - /**/ - } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) { /*DOn't know how to include &c*/ - odm_tx_pwr_track_set_pwr92_e(p_dm_odm, MIX_MODE, p, 0); - /**/ - } - } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - odm_tx_pwr_track_set_pwr88_e(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); - /**/ - } -} + memcpy(&ra_tab->per_rate_retrylimit_20M[0], + &per_rate_retrylimit_table_20M[0], ODM_NUM_RATE_IDX); + memcpy(&ra_tab->per_rate_retrylimit_40M[0], + &per_rate_retrylimit_table_40M[0], ODM_NUM_RATE_IDX); -void -odm_rssi_dump_to_register( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - - if (p_dm_odm->support_ic_type == ODM_RTL8812) { - PlatformEFIOWrite1Byte(adapter, REG_A_RSSI_DUMP_JAGUAR, adapter->RxStats.RxRSSIPercentage[0]); - PlatformEFIOWrite1Byte(adapter, REG_B_RSSI_DUMP_JAGUAR, adapter->RxStats.RxRSSIPercentage[1]); - - /* Rx EVM*/ - PlatformEFIOWrite1Byte(adapter, REG_S1_RXEVM_DUMP_JAGUAR, adapter->RxStats.RxEVMdbm[0]); - PlatformEFIOWrite1Byte(adapter, REG_S2_RXEVM_DUMP_JAGUAR, adapter->RxStats.RxEVMdbm[1]); - - /* Rx SNR*/ - PlatformEFIOWrite1Byte(adapter, REG_A_RX_SNR_DUMP_JAGUAR, (u8)(adapter->RxStats.RxSNRdB[0])); - PlatformEFIOWrite1Byte(adapter, REG_B_RX_SNR_DUMP_JAGUAR, (u8)(adapter->RxStats.RxSNRdB[1])); - - /* Rx Cfo_Short*/ - PlatformEFIOWrite2Byte(adapter, REG_A_CFO_SHORT_DUMP_JAGUAR, adapter->RxStats.RxCfoShort[0]); - PlatformEFIOWrite2Byte(adapter, REG_B_CFO_SHORT_DUMP_JAGUAR, adapter->RxStats.RxCfoShort[1]); - - /* Rx Cfo_Tail*/ - PlatformEFIOWrite2Byte(adapter, REG_A_CFO_LONG_DUMP_JAGUAR, adapter->RxStats.RxCfoTail[0]); - PlatformEFIOWrite2Byte(adapter, REG_B_CFO_LONG_DUMP_JAGUAR, adapter->RxStats.RxCfoTail[1]); - } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - PlatformEFIOWrite1Byte(adapter, REG_A_RSSI_DUMP_92E, adapter->RxStats.RxRSSIPercentage[0]); - PlatformEFIOWrite1Byte(adapter, REG_B_RSSI_DUMP_92E, adapter->RxStats.RxRSSIPercentage[1]); - /* Rx EVM*/ - PlatformEFIOWrite1Byte(adapter, REG_S1_RXEVM_DUMP_92E, adapter->RxStats.RxEVMdbm[0]); - PlatformEFIOWrite1Byte(adapter, REG_S2_RXEVM_DUMP_92E, adapter->RxStats.RxEVMdbm[1]); - /* Rx SNR*/ - PlatformEFIOWrite1Byte(adapter, REG_A_RX_SNR_DUMP_92E, (u8)(adapter->RxStats.RxSNRdB[0])); - PlatformEFIOWrite1Byte(adapter, REG_B_RX_SNR_DUMP_92E, (u8)(adapter->RxStats.RxSNRdB[1])); - /* Rx Cfo_Short*/ - PlatformEFIOWrite2Byte(adapter, REG_A_CFO_SHORT_DUMP_92E, adapter->RxStats.RxCfoShort[0]); - PlatformEFIOWrite2Byte(adapter, REG_B_CFO_SHORT_DUMP_92E, adapter->RxStats.RxCfoShort[1]); - /* Rx Cfo_Tail*/ - PlatformEFIOWrite2Byte(adapter, REG_A_CFO_LONG_DUMP_92E, adapter->RxStats.RxCfoTail[0]); - PlatformEFIOWrite2Byte(adapter, REG_B_CFO_LONG_DUMP_92E, adapter->RxStats.RxCfoTail[1]); + for (i = 0; i < ODM_NUM_RATE_IDX; i++) { + phydm_retry_limit_table_bound(dm, + &ra_tab->per_rate_retrylimit_20M[i], + 0); + phydm_retry_limit_table_bound(dm, + &ra_tab->per_rate_retrylimit_40M[i], + 0); } } void -odm_refresh_ldpc_rts_mp( - struct _ADAPTER *p_adapter, - struct PHY_DM_STRUCT *p_dm_odm, - u8 m_mac_id, - u8 iot_peer, - s32 undecorated_smoothed_pwdb +phydm_ra_dynamic_retry_limit_init( + void *dm_void ) { - boolean is_ctl_ldpc = false; - struct _ODM_RATE_ADAPTIVE *p_ra = &p_dm_odm->rate_adaptive; - - if (p_dm_odm->support_ic_type != ODM_RTL8821 && p_dm_odm->support_ic_type != ODM_RTL8812) - return; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; - if ((p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->cut_version == ODM_CUT_A)) - is_ctl_ldpc = true; - else if (p_dm_odm->support_ic_type == ODM_RTL8812 && - iot_peer == HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP) - is_ctl_ldpc = true; + ra_tab->retry_descend_num = RA_RETRY_DESCEND_NUM; + ra_tab->retrylimit_low = RA_RETRY_LIMIT_LOW; + ra_tab->retrylimit_high = RA_RETRY_LIMIT_HIGH; - if (is_ctl_ldpc) { - if (undecorated_smoothed_pwdb < (p_ra->ldpc_thres - 5)) - MgntSet_TX_LDPC(p_adapter, m_mac_id, true); - else if (undecorated_smoothed_pwdb > p_ra->ldpc_thres) - MgntSet_TX_LDPC(p_adapter, m_mac_id, false); - } + phydm_reset_retry_limit_table(dm); - if (undecorated_smoothed_pwdb < (p_ra->rts_thres - 5)) - p_ra->is_lower_rts_rate = true; - else if (undecorated_smoothed_pwdb > p_ra->rts_thres) - p_ra->is_lower_rts_rate = false; } -#if 0 void -odm_dynamic_arfb_select( - void *p_dm_void, - u8 rate, - boolean collision_state +phydm_ra_dynamic_retry_limit( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 i, retry_offset; + u32 ma_rx_tp; - if (p_dm_odm->support_ic_type != ODM_RTL8192E) - return; - if (collision_state == p_ra_table->PT_collision_pre) + if (dm->pre_number_active_client == dm->number_active_client) { + PHYDM_DBG(dm, DBG_RA, " pre_number_active_client == number_active_client\n"); return; - if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS12) { - if (collision_state == 1) { - if (rate == DESC_RATEMCS12) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07060501); - } else if (rate == DESC_RATEMCS11) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07070605); - } else if (rate == DESC_RATEMCS10) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08080706); - } else if (rate == DESC_RATEMCS9) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08080707); - } else { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09090808); - } - } else { /* collision_state == 0*/ - if (rate == DESC_RATEMCS12) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x05010000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09080706); - } else if (rate == DESC_RATEMCS11) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x06050000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09080807); - } else if (rate == DESC_RATEMCS10) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x07060000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x0a090908); - } else if (rate == DESC_RATEMCS9) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x07070000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x0a090808); - } else { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x08080000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x0b0a0909); - } - } - } else { /* MCS13~MCS15, 1SS, G-mode*/ - if (collision_state == 1) { - if (rate == DESC_RATEMCS15) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x05040302); - } else if (rate == DESC_RATEMCS14) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x06050302); - } else if (rate == DESC_RATEMCS13) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07060502); - } else { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x06050402); - } - } else { /* collision_state == 0 */ - if (rate == DESC_RATEMCS15) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x03020000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07060504); - } else if (rate == DESC_RATEMCS14) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x03020000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08070605); - } else if (rate == DESC_RATEMCS13) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x05020000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09080706); - } else { + } else { + if (dm->number_active_client == 1) { + phydm_reset_retry_limit_table(dm); + PHYDM_DBG(dm, DBG_RA, "one client only->reset to default value\n"); + } else { + retry_offset = dm->number_active_client * ra_tab->retry_descend_num; - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x04020000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08070605); + for (i = 0; i < ODM_NUM_RATE_IDX; i++) { + phydm_retry_limit_table_bound(dm, + &ra_tab->per_rate_retrylimit_20M[i], + retry_offset); + phydm_retry_limit_table_bound(dm, + &ra_tab->per_rate_retrylimit_40M[i], + retry_offset); } } } - p_ra_table->PT_collision_pre = collision_state; } #endif +#if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) void -odm_rate_adaptive_state_ap_init( - void *PADAPTER_VOID, - struct sta_info *p_entry +phydm_ra_dynamic_rate_id_on_assoc( + void *dm_void, + u8 wireless_mode, + u8 init_rate_id ) { - struct _ADAPTER *adapter = (struct _ADAPTER *)PADAPTER_VOID; - p_entry->Ratr_State = DM_RATR_STA_INIT; -} + struct dm_struct *dm = (struct dm_struct *)dm_void; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + PHYDM_DBG(dm, DBG_RA, "[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n", dm->rf_type, wireless_mode, init_rate_id); + + if ((dm->rf_type == RF_2T2R) || (dm->rf_type == RF_2T3R) || (dm->rf_type == RF_2T4R)) { + if ((dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) && + (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) + ) { + PHYDM_DBG(dm, DBG_RA, "[ON ASSOC] set N-2SS ARFR5 table\n"); + odm_set_mac_reg(dm, 0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ + odm_set_mac_reg(dm, 0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ + } else if ((dm->support_ic_type & (ODM_RTL8812)) && + (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) + ) { + PHYDM_DBG(dm, DBG_RA, "[ON ASSOC] set AC-2SS ARFR0 table\n"); + odm_set_mac_reg(dm, 0x444, MASKDWORD, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ + odm_set_mac_reg(dm, 0x448, MASKDWORD, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ + } + } -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ +} -static void -find_minimum_rssi( - struct _ADAPTER *p_adapter +void +phydm_ra_dynamic_rate_id_init( + void *dm_void ) { - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &(p_hal_data->odmpriv); + struct dm_struct *dm = (struct dm_struct *)dm_void; - /*Determine the minimum RSSI*/ + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) { + odm_set_mac_reg(dm, 0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ + odm_set_mac_reg(dm, 0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ - if ((p_dm_odm->is_linked != _TRUE) && - (p_hal_data->entry_min_undecorated_smoothed_pwdb == 0)) { - p_hal_data->min_undecorated_pwdb_for_dm = 0; - /*ODM_RT_TRACE(p_dm_odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any\n"));*/ - } else - p_hal_data->min_undecorated_pwdb_for_dm = p_hal_data->entry_min_undecorated_smoothed_pwdb; - - /*DBG_8192C("%s=>min_undecorated_pwdb_for_dm(%d)\n",__FUNCTION__,pdmpriv->min_undecorated_pwdb_for_dm);*/ - /*ODM_RT_TRACE(p_dm_odm,COMP_DIG, DBG_LOUD, ("min_undecorated_pwdb_for_dm =%d\n",p_hal_data->min_undecorated_pwdb_for_dm));*/ + odm_set_mac_reg(dm, 0x444, MASKDWORD, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ + odm_set_mac_reg(dm, 0x448, MASKDWORD, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ + } } -u64 -phydm_get_rate_bitmap_ex( - void *p_dm_void, - u32 macid, - u64 ra_mask, - u8 rssi_level, - u64 *dm_ra_mask, - u8 *dm_rte_id +void +phydm_update_rate_id( + void *dm_void, + u8 rate, + u8 platform_macid ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct sta_info *p_entry; - u64 rate_bitmap = 0; - u8 wireless_mode; - - p_entry = p_dm_odm->p_odm_sta_info[macid]; - if (!IS_STA_VALID(p_entry)) - return ra_mask; - wireless_mode = p_entry->wireless_mode; - switch (wireless_mode) { - case ODM_WM_B: - if (ra_mask & 0x000000000000000c) /* 11M or 5.5M enable */ - rate_bitmap = 0x000000000000000d; - else - rate_bitmap = 0x000000000000000f; - break; +#if 0 - case (ODM_WM_G): - case (ODM_WM_A): - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x0000000000000f00; - else - rate_bitmap = 0x0000000000000ff0; - break; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 current_tx_ss; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 wireless_mode; + u8 phydm_macid; + struct sta_info *entry; + struct cmn_sta_info *sta; - case (ODM_WM_B|ODM_WM_G): - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x0000000000000f00; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x0000000000000ff0; - else - rate_bitmap = 0x0000000000000ff5; - break; - case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): - case (ODM_WM_B|ODM_WM_N24G): - case (ODM_WM_G|ODM_WM_N24G): - case (ODM_WM_A|ODM_WM_N5G): - { - if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x00000000000f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x00000000000ff000; - else { - if (*(p_dm_odm->p_band_width) == ODM_BW40M) - rate_bitmap = 0x00000000000ff015; - else - rate_bitmap = 0x00000000000ff005; - } - } else if (p_dm_odm->rf_type == ODM_2T2R || p_dm_odm->rf_type == ODM_2T3R || p_dm_odm->rf_type == ODM_2T4R) { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x000000000f8f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x000000000f8ff000; - else { - if (*(p_dm_odm->p_band_width) == ODM_BW40M) - rate_bitmap = 0x000000000f8ff015; - else - rate_bitmap = 0x000000000f8ff005; - } - } else { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x0000000f0f0f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x0000000fcfcfe000; - else { - if (*(p_dm_odm->p_band_width) == ODM_BW40M) - rate_bitmap = 0x0000000ffffff015; - else - rate_bitmap = 0x0000000ffffff005; - } - } +#if 0 + if (rate_idx >= ODM_RATEVHTSS2MCS0) { + PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT2SS-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0)); + /*dummy for SD4 check patch*/ + } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { + PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT1SS-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0)); + /*dummy for SD4 check patch*/ + } else if (rate_idx >= ODM_RATEMCS0) { + PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEMCS0)); + /*dummy for SD4 check patch*/ + } else { + PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n", platform_macid, rate_idx); + /*dummy for SD4 check patch*/ } - break; +#endif - case (ODM_WM_AC|ODM_WM_G): - if (rssi_level == 1) - rate_bitmap = 0x00000000fc3f0000; - else if (rssi_level == 2) - rate_bitmap = 0x00000000fffff000; - else - rate_bitmap = 0x00000000ffffffff; - break; + phydm_macid = dm->phydm_macid_table[platform_macid]; + entry = dm->odm_sta_info[phydm_macid]; + sta = dm->phydm_sta_info[phydm_macid]; - case (ODM_WM_AC|ODM_WM_A): + if (is_sta_active(sta)) { + wireless_mode = entry->wireless_mode; - if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0x00000000003f8000; - else if (rssi_level == 2) - rate_bitmap = 0x00000000003fe000; - else - rate_bitmap = 0x00000000003ff010; - } else if (p_dm_odm->rf_type == ODM_2T2R || p_dm_odm->rf_type == ODM_2T3R || p_dm_odm->rf_type == ODM_2T4R) { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0x00000000fe3f8000; /* VHT 2SS MCS3~9 */ - else if (rssi_level == 2) - rate_bitmap = 0x00000000fffff000; /* VHT 2SS MCS0~9 */ - else - rate_bitmap = 0x00000000fffff010; /* All */ - } else { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0x000003f8fe3f8000ULL; /* VHT 3SS MCS3~9 */ - else if (rssi_level == 2) - rate_bitmap = 0x000003fffffff000ULL; /* VHT3SS MCS0~9 */ - else - rate_bitmap = 0x000003fffffff010ULL; /* All */ - } - break; + if ((dm->rf_type == RF_2T2R) || (dm->rf_type == RF_2T3R) || (dm->rf_type == RF_2T4R)) { + if (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) { /*N mode*/ + if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*2SS mode*/ - default: - if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) - rate_bitmap = 0x00000000000fffff; - else if (p_dm_odm->rf_type == ODM_2T2R || p_dm_odm->rf_type == ODM_2T3R || p_dm_odm->rf_type == ODM_2T4R) - rate_bitmap = 0x000000000fffffff; - else - rate_bitmap = 0x0000003fffffffffULL; - break; + sta->ra_info.rate_id = ARFR_5_RATE_ID; + PHYDM_DBG(dm, DBG_RA, "ARFR_5\n"); + } + } else if (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) {/*AC mode*/ + if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*2SS mode*/ - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%016llx\n", rssi_level, wireless_mode, rate_bitmap)); + sta->ra_info.rate_id = ARFR_0_RATE_ID; + PHYDM_DBG(dm, DBG_RA, "ARFR_0\n"); + } + } else + sta->ra_info.rate_id = ARFR_0_RATE_ID; - return ra_mask & rate_bitmap; + PHYDM_DBG(dm, DBG_RA, "UPdate_RateID[%d]: (( 0x%x ))\n", platform_macid, sta->ra_info.rate_id); + } + } +#endif } +#endif -u32 -odm_get_rate_bitmap( - void *p_dm_void, - u32 macid, - u32 ra_mask, - u8 rssi_level +#if (defined(CONFIG_RA_DBG_CMD)) +void +odm_ra_para_adjust_send_h2c( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct sta_info *p_entry; - u32 rate_bitmap = 0; - u8 wireless_mode; - /* u8 wireless_mode =*(p_dm_odm->p_wireless_mode); */ - - - p_entry = p_dm_odm->p_odm_sta_info[macid]; - if (!IS_STA_VALID(p_entry)) - return ra_mask; - - wireless_mode = p_entry->wireless_mode; - - switch (wireless_mode) { - case ODM_WM_B: - if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ - rate_bitmap = 0x0000000d; - else - rate_bitmap = 0x0000000f; - break; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 h2c_parameter[6] = {0}; - case (ODM_WM_G): - case (ODM_WM_A): - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x00000f00; - else - rate_bitmap = 0x00000ff0; - break; + h2c_parameter[0] = RA_FIRST_MACID; - case (ODM_WM_B|ODM_WM_G): - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x00000f00; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x00000ff0; - else - rate_bitmap = 0x00000ff5; - break; + if (ra_tab->ra_para_feedback_req) { /*h2c_parameter[5]=1 ; ask FW for all RA parameters*/ + PHYDM_DBG(dm, DBG_RA, "[H2C] Ask FW for RA parameter\n"); + h2c_parameter[5] |= BIT(1); /*ask FW to report RA parameters*/ + h2c_parameter[1] = ra_tab->para_idx; /*ra_tab->para_idx;*/ + ra_tab->ra_para_feedback_req = 0; + } else { + PHYDM_DBG(dm, DBG_RA, "[H2C] Send H2C to FW for modifying RA parameter\n"); - case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): - case (ODM_WM_B|ODM_WM_N24G): - case (ODM_WM_G|ODM_WM_N24G): - case (ODM_WM_A|ODM_WM_N5G): - { - if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x000f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x000ff000; - else { - if (*(p_dm_odm->p_band_width) == ODM_BW40M) - rate_bitmap = 0x000ff015; - else - rate_bitmap = 0x000ff005; - } - } else { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x0f8f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x0f8ff000; - else { - if (*(p_dm_odm->p_band_width) == ODM_BW40M) - rate_bitmap = 0x0f8ff015; - else - rate_bitmap = 0x0f8ff005; - } + h2c_parameter[1] = ra_tab->para_idx; + h2c_parameter[2] = ra_tab->rate_idx; + /* [8 bit]*/ + if (ra_tab->para_idx == RADBG_RTY_PENALTY || ra_tab->para_idx == RADBG_RATE_UP_RTY_RATIO || ra_tab->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { + h2c_parameter[3] = ra_tab->value; + h2c_parameter[4] = 0; + } + /* [16 bit]*/ + else { + h2c_parameter[3] = (u8)(((ra_tab->value_16) & 0xf0) >> 4); /*byte1*/ + h2c_parameter[4] = (u8)((ra_tab->value_16) & 0x0f); /*byte0*/ } } - break; + PHYDM_DBG(dm, DBG_RA, " h2c_parameter[1] = 0x%x\n", h2c_parameter[1]); + PHYDM_DBG(dm, DBG_RA, " h2c_parameter[2] = 0x%x\n", h2c_parameter[2]); + PHYDM_DBG(dm, DBG_RA, " h2c_parameter[3] = 0x%x\n", h2c_parameter[3]); + PHYDM_DBG(dm, DBG_RA, " h2c_parameter[4] = 0x%x\n", h2c_parameter[4]); + PHYDM_DBG(dm, DBG_RA, " h2c_parameter[5] = 0x%x\n", h2c_parameter[5]); - case (ODM_WM_AC|ODM_WM_G): - if (rssi_level == 1) - rate_bitmap = 0xfc3f0000; - else if (rssi_level == 2) - rate_bitmap = 0xfffff000; - else - rate_bitmap = 0xffffffff; - break; + odm_fill_h2c_cmd(dm, ODM_H2C_RA_PARA_ADJUST, 6, h2c_parameter); - case (ODM_WM_AC|ODM_WM_A): +} - if (p_dm_odm->rf_type == RF_1T1R) { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0x003f8000; - else if (rssi_level == 2) - rate_bitmap = 0x003ff000; - else - rate_bitmap = 0x003ff010; - } else { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0xfe3f8000; /* VHT 2SS MCS3~9 */ - else if (rssi_level == 2) - rate_bitmap = 0xfffff000; /* VHT 2SS MCS0~9 */ - else - rate_bitmap = 0xfffff010; /* All */ - } - break; - default: - if (p_dm_odm->rf_type == RF_1T2R) - rate_bitmap = 0x000fffff; - else - rate_bitmap = 0x0fffffff; - break; +void +odm_ra_para_adjust( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 rate_idx = ra_tab->rate_idx; + u8 value = ra_tab->value; + u8 pre_value = 0xff; - } + if (ra_tab->para_idx == RADBG_RTY_PENALTY) { + pre_value = ra_tab->RTY_P[rate_idx]; + ra_tab->RTY_P[rate_idx] = value; + ra_tab->RTY_P_modify_note[rate_idx] = 1; + } else if (ra_tab->para_idx == RADBG_N_HIGH) { + } else if (ra_tab->para_idx == RADBG_N_LOW) { + } else if (ra_tab->para_idx == RADBG_RATE_UP_RTY_RATIO) { + pre_value = ra_tab->RATE_UP_RTY_RATIO[rate_idx]; + ra_tab->RATE_UP_RTY_RATIO[rate_idx] = value; + ra_tab->RATE_UP_RTY_RATIO_modify_note[rate_idx] = 1; + } else if (ra_tab->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { + pre_value = ra_tab->RATE_DOWN_RTY_RATIO[rate_idx]; + ra_tab->RATE_DOWN_RTY_RATIO[rate_idx] = value; + ra_tab->RATE_DOWN_RTY_RATIO_modify_note[rate_idx] = 1; + } + PHYDM_DBG(dm, DBG_RA, "Change RA Papa[%d], rate[ %d ], ((%d)) -> ((%d))\n", ra_tab->para_idx, rate_idx, pre_value, value); + odm_ra_para_adjust_send_h2c(dm); +} - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%08x\n", __func__, rssi_level, wireless_mode, rate_bitmap)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%08x\n", rssi_level, wireless_mode, rate_bitmap)); +void +phydm_ra_print_msg( + void *dm_void, + u8 *value, + u8 *value_default, + u8 *modify_note +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u32 i; - return ra_mask & rate_bitmap; + PHYDM_DBG(dm, DBG_RA, " |rate index| |Current-value| |Default-value| |Modify?|\n"); + for (i = 0 ; i <= (ra_tab->rate_length); i++) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + PHYDM_DBG(dm, DBG_RA, " [ %d ] %20d %25d %20s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . ")); +#else + PHYDM_DBG(dm, DBG_RA, " [ %d ] %10d %14d %14s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . ")); +#endif + } } -#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ - -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +void +odm_RA_debug( + void *dm_void, + u32 *const dm_value +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + ra_tab->is_ra_dbg_init = false; -#endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ + if (dm_value[0] == 100) { /*1 Print RA Parameters*/ + u8 default_pointer_value; + u8 *pvalue; + u8 *pvalue_default; + u8 *pmodify_note; + pvalue = pvalue_default = pmodify_note = &default_pointer_value; -/* RA_MASK_PHYDMLIZE, will delete it later*/ + PHYDM_DBG(dm, DBG_RA, "\n------------------------------------------------------------------------------------\n"); -#if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN) + if (dm_value[1] == RADBG_RTY_PENALTY) { /* [1]*/ + PHYDM_DBG(dm, DBG_RA, " [1] RTY_PENALTY\n"); + pvalue = &ra_tab->RTY_P[0]; + pvalue_default = &ra_tab->RTY_P_default[0]; + pmodify_note = (u8 *)&ra_tab->RTY_P_modify_note[0]; + } else if (dm_value[1] == RADBG_N_HIGH) /* [2]*/ + PHYDM_DBG(dm, DBG_RA, " [2] N_HIGH\n"); -boolean -odm_ra_state_check( - void *p_dm_void, - s32 RSSI, - boolean is_force_update, - u8 *p_ra_tr_state -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_RATE_ADAPTIVE *p_ra = &p_dm_odm->rate_adaptive; - const u8 go_up_gap = 5; - u8 high_rssi_thresh_for_ra = p_ra->high_rssi_thresh; - u8 low_rssi_thresh_for_ra = p_ra->low_rssi_thresh; - u8 ratr_state; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI= (( %d )), Current_RSSI_level = (( %d ))\n", RSSI, *p_ra_tr_state)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Ori RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", high_rssi_thresh_for_ra, low_rssi_thresh_for_ra)); - /* threshold Adjustment:*/ - /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough.*/ - /* Here go_up_gap is added to solve the boundary's level alternation issue.*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u8 ultra_low_rssi_thresh_for_ra = p_ra->ultra_low_rssi_thresh; - - if (p_dm_odm->support_ic_type == ODM_RTL8881A) - low_rssi_thresh_for_ra = 30; /* for LDPC / BCC switch*/ -#endif + else if (dm_value[1] == RADBG_N_LOW) /*[3]*/ + PHYDM_DBG(dm, DBG_RA, " [3] N_LOW\n"); - switch (*p_ra_tr_state) { - case DM_RATR_STA_INIT: - case DM_RATR_STA_HIGH: - break; + else if (dm_value[1] == RADBG_RATE_UP_RTY_RATIO) { /* [8]*/ + PHYDM_DBG(dm, DBG_RA, " [8] RATE_UP_RTY_RATIO\n"); + pvalue = &ra_tab->RATE_UP_RTY_RATIO[0]; + pvalue_default = &ra_tab->RATE_UP_RTY_RATIO_default[0]; + pmodify_note = (u8 *)&ra_tab->RATE_UP_RTY_RATIO_modify_note[0]; + } else if (dm_value[1] == RADBG_RATE_DOWN_RTY_RATIO) { /* [9]*/ + PHYDM_DBG(dm, DBG_RA, " [9] RATE_DOWN_RTY_RATIO\n"); + pvalue = &ra_tab->RATE_DOWN_RTY_RATIO[0]; + pvalue_default = &ra_tab->RATE_DOWN_RTY_RATIO_default[0]; + pmodify_note = (u8 *)&ra_tab->RATE_DOWN_RTY_RATIO_modify_note[0]; + } - case DM_RATR_STA_MIDDLE: - high_rssi_thresh_for_ra += go_up_gap; - break; + phydm_ra_print_msg(dm, pvalue, pvalue_default, pmodify_note); + PHYDM_DBG(dm, DBG_RA, "\n------------------------------------------------------------------------------------\n\n"); - case DM_RATR_STA_LOW: - high_rssi_thresh_for_ra += go_up_gap; - low_rssi_thresh_for_ra += go_up_gap; - break; + } else if (dm_value[0] == 101) { + ra_tab->para_idx = (u8)dm_value[1]; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - case DM_RATR_STA_ULTRA_LOW: - high_rssi_thresh_for_ra += go_up_gap; - low_rssi_thresh_for_ra += go_up_gap; - ultra_low_rssi_thresh_for_ra += go_up_gap; - break; -#endif + ra_tab->ra_para_feedback_req = 1; + odm_ra_para_adjust_send_h2c(dm); + } else { + ra_tab->para_idx = (u8)dm_value[0]; + ra_tab->rate_idx = (u8)dm_value[1]; + ra_tab->value = (u8)dm_value[2]; - default: - ODM_RT_ASSERT(p_dm_odm, false, ("wrong rssi level setting %d !", *p_ra_tr_state)); - break; + odm_ra_para_adjust(dm); } +} + +void +odm_ra_para_adjust_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 i; + u8 ra_para_pool_u8[3] = { RADBG_RTY_PENALTY, RADBG_RATE_UP_RTY_RATIO, RADBG_RATE_DOWN_RTY_RATIO}; + u8 rate_size_ht_1ss = 20, rate_size_ht_2ss = 28, rate_size_ht_3ss = 36; /*4+8+8+8+8 =36*/ + u8 rate_size_vht_1ss = 10, rate_size_vht_2ss = 20, rate_size_vht_3ss = 30; /*10 + 10 +10 =30*/ +#if 0 + /* RTY_PENALTY = 1, u8 */ + /* N_HIGH = 2, */ + /* N_LOW = 3, */ + /* RATE_UP_TABLE = 4, */ + /* RATE_DOWN_TABLE = 5, */ + /* TRYING_NECESSARY = 6, */ + /* DROPING_NECESSARY = 7, */ + /* RATE_UP_RTY_RATIO = 8, u8 */ + /* RATE_DOWN_RTY_RATIO= 9, u8 */ + /* ALL_PARA = 0xff */ - /* Decide ratr_state by RSSI.*/ - if (RSSI > high_rssi_thresh_for_ra) - ratr_state = DM_RATR_STA_HIGH; - else if (RSSI > low_rssi_thresh_for_ra) - ratr_state = DM_RATR_STA_MIDDLE; +#endif + PHYDM_DBG(dm, DBG_RA, "odm_ra_para_adjust_init\n"); -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - else if (RSSI > ultra_low_rssi_thresh_for_ra) - ratr_state = DM_RATR_STA_LOW; - else - ratr_state = DM_RATR_STA_ULTRA_LOW; -#else +/* JJ ADD 20161014 */ + if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8723D | ODM_RTL8710B)) + ra_tab->rate_length = rate_size_ht_1ss; + else if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) + ra_tab->rate_length = rate_size_ht_2ss; + else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8821C)) + ra_tab->rate_length = rate_size_ht_1ss + rate_size_vht_1ss; + else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) + ra_tab->rate_length = rate_size_ht_2ss + rate_size_vht_2ss; + else if (dm->support_ic_type == ODM_RTL8814A) + ra_tab->rate_length = rate_size_ht_3ss + rate_size_vht_3ss; else - ratr_state = DM_RATR_STA_LOW; -#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Mod RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", high_rssi_thresh_for_ra, low_rssi_thresh_for_ra)); - /*printk("==>%s,ratr_state:0x%02x,RSSI:%d\n",__FUNCTION__,ratr_state,RSSI);*/ + ra_tab->rate_length = rate_size_ht_1ss; - if (*p_ra_tr_state != ratr_state || is_force_update) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[RSSI Level Update] %d->%d\n", *p_ra_tr_state, ratr_state)); - *p_ra_tr_state = ratr_state; - return true; + ra_tab->is_ra_dbg_init = true; + for (i = 0; i < 3; i++) { + ra_tab->ra_para_feedback_req = 1; + ra_tab->para_idx = ra_para_pool_u8[i]; + odm_ra_para_adjust_send_h2c(dm); } - - return false; } -#endif +#endif /*#if (defined(CONFIG_RA_DBG_CMD))*/ + + diff --git a/hal/phydm/phydm_rainfo.h b/hal/phydm/phydm_rainfo.h index 82d58cb..8c26012 100644 --- a/hal/phydm/phydm_rainfo.h +++ b/hal/phydm/phydm_rainfo.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,27 +8,37 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __PHYDMRAINFO_H__ #define __PHYDMRAINFO_H__ -/*#define RAINFO_VERSION "2.0" //2014.11.04*/ -/*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/ -/*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/ -/*#define RAINFO_VERSION "3.3" 2015.07.29 YuChen*/ +/*#define RAINFO_VERSION "2.0"*/ /*2014.11.04*/ +/*#define RAINFO_VERSION "3.0"*/ /*2015.01.13 Dino*/ +/*#define RAINFO_VERSION "3.1"*/ /*2015.01.14 Dino*/ +/*#define RAINFO_VERSION "3.3"*/ /*2015.07.29 YuChen*/ /*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/ /*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */ /*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */ /*#define RAINFO_VERSION "4.2"*/ /*2016.05.17 Dino, Add H2C debug cmd */ -#define RAINFO_VERSION "4.3" /*2016.07.11 Dino, Fix RA hang in CCK 1M problem */ +/*#define RAINFO_VERSION "4.3"*/ /*2016.07.11 Dino, Fix RA hang in CCK 1M problem */ +#define RAINFO_VERSION "5.0" /*2017.04.20 Dino, the 3rd PHYDM reform*/ #define FORCED_UPDATE_RAMASK_PERIOD 5 -#define H2C_0X42_LENGTH 5 #define H2C_MAX_LENGTH 7 #define RA_FLOOR_UP_GAP 3 @@ -39,25 +49,6 @@ #define RA_RETRY_LIMIT_LOW 4 #define RA_RETRY_LIMIT_HIGH 32 -#define RAINFO_BE_RX_STATE BIT(0) /* 1:RX */ /* ULDL */ -#define RAINFO_STBC_STATE BIT(1) -/* #define RAINFO_LDPC_STATE BIT2 */ -#define RAINFO_NOISY_STATE BIT(2) /* set by Noisy_Detection */ -#define RAINFO_SHURTCUT_STATE BIT(3) -#define RAINFO_SHURTCUT_FLAG BIT(4) -#define RAINFO_INIT_RSSI_RATE_STATE BIT(5) -#define RAINFO_BF_STATE BIT(6) -#define RAINFO_BE_TX_STATE BIT(7) /* 1:TX */ - -#define RA_MASK_CCK 0xf -#define RA_MASK_OFDM 0xff0 -#define RA_MASK_HT1SS 0xff000 -#define RA_MASK_HT2SS 0xff00000 -/*#define RA_MASK_MCS3SS */ -#define RA_MASK_HT4SS 0xff0 -#define RA_MASK_VHT1SS 0x3ff000 -#define RA_MASK_VHT2SS 0xffc00000 - #if (DM_ODM_SUPPORT_TYPE == ODM_AP) #define RA_FIRST_MACID 1 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) @@ -68,30 +59,8 @@ #define RA_FIRST_MACID 0 #endif -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#define AP_InitRateAdaptiveState odm_rate_adaptive_state_ap_init -#else -#define ap_init_rate_adaptive_state odm_rate_adaptive_state_ap_init -#endif - -#if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN) - #define DM_RATR_STA_INIT 0 - #define DM_RATR_STA_HIGH 1 - #define DM_RATR_STA_MIDDLE 2 - #define DM_RATR_STA_LOW 3 - #define DM_RATR_STA_ULTRA_LOW 4 -#endif - -enum phydm_ra_arfr_num_e { - ARFR_0_RATE_ID = 0x9, - ARFR_1_RATE_ID = 0xa, - ARFR_2_RATE_ID = 0xb, - ARFR_3_RATE_ID = 0xc, - ARFR_4_RATE_ID = 0xd, - ARFR_5_RATE_ID = 0xe -}; -enum phydm_ra_dbg_para_e { +enum phydm_ra_dbg_para { RADBG_PCR_TH_OFFSET = 0, RADBG_RTY_PENALTY = 1, RADBG_N_HIGH = 2, @@ -111,8 +80,7 @@ enum phydm_ra_dbg_para_e { NUM_RA_PARA }; -enum phydm_wireless_mode_e { - +enum phydm_wireless_mode { PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, PHYDM_WIRELESS_MODE_A = 0x01, PHYDM_WIRELESS_MODE_B = 0x02, @@ -127,8 +95,7 @@ enum phydm_wireless_mode_e { PHYDM_WIRELESS_MODE_ALL = 0xFFFF }; -enum phydm_rateid_idx_e { - +enum phydm_rateid_idx { PHYDM_BGN_40M_2SS = 0, PHYDM_BGN_40M_1SS = 1, PHYDM_BGN_20M_2SS = 2, @@ -146,30 +113,6 @@ enum phydm_rateid_idx_e { PHYDM_ARFR5_N_3SS = 14 }; -enum phydm_rf_type_def_e { - PHYDM_RF_1T1R = 0, - PHYDM_RF_1T2R, - PHYDM_RF_2T2R, - PHYDM_RF_2T2R_GREEN, - PHYDM_RF_2T3R, - PHYDM_RF_2T4R, - PHYDM_RF_3T3R, - PHYDM_RF_3T4R, - PHYDM_RF_4T4R, - PHYDM_RF_MAX_TYPE -}; - -enum phydm_bw_e { - PHYDM_BW_20 = 0, - PHYDM_BW_40, - PHYDM_BW_80, - PHYDM_BW_80_80, - PHYDM_BW_160, - PHYDM_BW_10, - PHYDM_BW_5 -}; - - #if (RATE_ADAPTIVE_SUPPORT == 1)/* 88E RA */ struct _odm_ra_info_ { u8 rate_id; @@ -217,7 +160,7 @@ struct _odm_ra_info_ { #endif -struct _rate_adaptive_table_ { +struct ra_table { u8 firstconnect; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) boolean PT_collision_pre; @@ -246,50 +189,31 @@ struct _rate_adaptive_table_ { u16 value_16; u8 rate_length; #endif - u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM]; + /*u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];*/ + u8 mu1_rate[30]; u8 highest_client_tx_order; u16 highest_client_tx_rate_order; u8 power_tracking_flag; u8 RA_threshold_offset; u8 RA_offset_direction; - u8 force_update_ra_mask_count; + u8 up_ramask_cnt; /*force update_ra_mask counter*/ + u8 up_ramask_cnt_tmp; /*Just for debug, should be removed latter*/ #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - u8 per_rate_retrylimit_20M[ODM_NUM_RATE_IDX]; - u8 per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; - u8 retry_descend_num; - u8 retrylimit_low; - u8 retrylimit_high; -#endif - - -}; - -struct _ODM_RATE_ADAPTIVE { - u8 type; /* dm_type_by_fw/dm_type_by_driver */ - u8 high_rssi_thresh; /* if RSSI > high_rssi_thresh => ratr_state is DM_RATR_STA_HIGH */ - u8 low_rssi_thresh; /* if RSSI <= low_rssi_thresh => ratr_state is DM_RATR_STA_LOW */ - u8 ratr_state; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - u8 ldpc_thres; /* if RSSI > ldpc_thres => switch from LPDC to BCC */ - boolean is_lower_rts_rate; -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - u8 rts_thres; -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - boolean is_use_ldpc; -#else - u8 ultra_low_rssi_thresh; - u32 last_ratr; /* RATR Register Content */ + u8 per_rate_retrylimit_20M[ODM_NUM_RATE_IDX]; + u8 per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; + u8 retry_descend_num; + u8 retrylimit_low; + u8 retrylimit_high; #endif + u8 ldpc_thres; /* if RSSI > ldpc_thres => switch from LPDC to BCC */ + void (*record_ra_info)(void *dm_void, u8 macid, struct cmn_sta_info *sta, u64 ra_mask); }; void phydm_h2C_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value, u32 *_used, char *output, @@ -300,118 +224,94 @@ phydm_h2C_debug( void odm_RA_debug( - void *p_dm_void, + void *dm_void, u32 *const dm_value ); void odm_ra_para_adjust_init( - void *p_dm_void + void *dm_void ); -#else +#endif void -phydm_RA_debug_PCR( - void *p_dm_void, - u32 *const dm_value, +phydm_ra_debug( + void *dm_void, + char input[][16], u32 *_used, - char *output, + char *output, u32 *_out_len ); -#endif - void odm_c2h_ra_para_report_handler( - void *p_dm_void, + void *dm_void, u8 *cmd_buf, u8 cmd_len ); void odm_ra_para_adjust( - void *p_dm_void + void *dm_void ); void phydm_ra_dynamic_retry_count( - void *p_dm_void + void *dm_void ); void phydm_ra_dynamic_retry_limit( - void *p_dm_void -); - -void -phydm_ra_dynamic_rate_id_on_assoc( - void *p_dm_void, - u8 wireless_mode, - u8 init_rate_id + void *dm_void ); void phydm_print_rate( - void *p_dm_void, + void *dm_void, u8 rate, u32 dbg_component ); void phydm_c2h_ra_report_handler( - void *p_dm_void, + void *dm_void, u8 *cmd_buf, u8 cmd_len ); u8 phydm_rate_order_compute( - void *p_dm_void, + void *dm_void, u8 rate_idx ); void phydm_ra_info_watchdog( - void *p_dm_void + void *dm_void ); void phydm_ra_info_init( - void *p_dm_void -); - -void -odm_rssi_monitor_init( - void *p_dm_void + void *dm_void ); void phydm_modify_RA_PCR_threshold( - void *p_dm_void, + void *dm_void, u8 RA_offset_direction, u8 RA_threshold_offset ); -void -odm_rssi_monitor_check( - void *p_dm_void -); - -void -phydm_init_ra_info( - void *p_dm_void -); - u8 phydm_vht_en_mapping( - void *p_dm_void, + void *dm_void, u32 wireless_mode ); u8 phydm_rate_id_mapping( - void *p_dm_void, + void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw @@ -419,7 +319,7 @@ phydm_rate_id_mapping( void phydm_update_hal_ra_mask( - void *p_dm_void, + void *dm_void, u32 wireless_mode, u8 rf_type, u8 BW, @@ -431,156 +331,123 @@ phydm_update_hal_ra_mask( ); void -odm_rate_adaptive_mask_init( - void *p_dm_void +phydm_refresh_rate_adaptive_mask( + void *dm_void ); -void -odm_refresh_rate_adaptive_mask( - void *p_dm_void +u8 +phydm_rssi_lv_dec( + void *dm_void, + u32 rssi, + u8 ratr_state ); void -odm_refresh_rate_adaptive_mask_mp( - void *p_dm_void +odm_ra_post_action_on_assoc( + void *dm ); -void -odm_refresh_rate_adaptive_mask_ce( - void *p_dm_void +u8 +odm_find_rts_rate( + void *dm_void, + u8 tx_rate, + boolean is_erp_protect ); void -odm_refresh_rate_adaptive_mask_apadsl( - void *p_dm_void +phydm_show_sta_info( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num ); u8 -phydm_RA_level_decision( - void *p_dm_void, - u32 rssi, - u8 ratr_state +phydm_get_plcp( + void *dm_void, + u16 macid ); -boolean -odm_ra_state_check( - void *p_dm_void, - s32 RSSI, - boolean is_force_update, - u8 *p_ra_tr_state -); +#ifdef PHYDM_3RD_REFORM_RA_MASK void -odm_refresh_basic_rate_mask( - void *p_dm_void +phydm_ra_registed( + void *dm_void, + u8 macid, + u8 rssi_from_assoc ); + void -odm_ra_post_action_on_assoc( - void *p_dm_odm +phydm_ra_offline( + void *dm_void, + u8 macid ); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - -u8 -odm_find_rts_rate( - void *p_dm_void, - u8 tx_rate, - boolean is_erp_protect -); void -odm_update_noisy_state( - void *p_dm_void, - boolean is_noisy_state_from_c2h +phydm_ra_mask_watchdog( + void *dm_void ); -void -phydm_update_pwr_track( - void *p_dm_void, - u8 rate -); +#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -s32 -phydm_find_minimum_rssi( - struct PHY_DM_STRUCT *p_dm_odm, - struct _ADAPTER *p_adapter, - OUT boolean *p_is_link_temp -); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void -odm_update_init_rate_work_item_callback( - void *p_context +odm_refresh_basic_rate_mask( + void *dm_void ); void -odm_rssi_dump_to_register( - void *p_dm_void +odm_update_init_rate_work_item_callback( + void *context ); void odm_refresh_ldpc_rts_mp( - struct _ADAPTER *p_adapter, - struct PHY_DM_STRUCT *p_dm_odm, + void *adapter, + struct dm_struct *dm, u8 m_mac_id, u8 iot_peer, s32 undecorated_smoothed_pwdb ); -#if 0 -void -odm_dynamic_arfb_select( - void *p_dm_void, - u8 rate, - boolean collision_state -); -#endif +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) void -odm_rate_adaptive_state_ap_init( - void *PADAPTER_VOID, - struct sta_info *p_entry +phydm_gen_ramask_h2c_AP( + void *dm_void, + struct rtl8192cd_priv *priv, + struct sta_info *entry, + u8 rssi_level ); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))*/ -static void -find_minimum_rssi( - struct _ADAPTER *p_adapter -); -u64 -phydm_get_rate_bitmap_ex( - void *p_dm_void, - u32 macid, - u64 ra_mask, - u8 rssi_level, - u64 *dm_ra_mask, - u8 *dm_rte_id -); -u32 -odm_get_rate_bitmap( - void *p_dm_void, - u32 macid, - u32 ra_mask, - u8 rssi_level +#if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) +void +phydm_ra_dynamic_rate_id_on_assoc( + void *dm_void, + u8 wireless_mode, + u8 init_rate_id ); -void phydm_ra_rssi_rpt_wk(void *p_context); -#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ +void +phydm_ra_dynamic_rate_id_init( + void *dm_void +); -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -/* void -phydm_gen_ramask_h2c_AP( - void *p_dm_void, - struct rtl8192cd_priv *priv, - struct sta_info *p_entry, - u8 rssi_level +phydm_update_rate_id( + void *dm_void, + u8 rate, + u8 platform_macid ); -*/ -#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ + +#endif #endif /*#ifndef __ODMRAINFO_H__*/ diff --git a/hal/phydm/phydm_reg.h b/hal/phydm/phydm_reg.h index 9bb5dde..e6302eb 100644 --- a/hal/phydm/phydm_reg.h +++ b/hal/phydm/phydm_reg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ /* ************************************************************ * File Name: odm_reg.h @@ -204,21 +214,4 @@ #define BIT_FA_RESET BIT(0) -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - #define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0xC80 - #define REG_OFDM_0_ECCA_THRESHOLD 0xC4C - #define REG_FPGA0_XB_LSSI_READ_BACK 0x8A4 - #define REG_FPGA0_TX_GAIN_STAGE 0x80C - #define REG_OFDM_0_XA_AGC_CORE1 0xC50 - #define REG_OFDM_0_XB_AGC_CORE1 0xC58 - #define REG_A_TX_SCALE_JAGUAR 0xC1C - #define REG_B_TX_SCALE_JAGUAR 0xE1C - - #define REG_AFE_XTAL_CTRL 0x0024 - #define REG_AFE_PLL_CTRL 0x0028 - #define REG_MAC_PHY_CTRL 0x002C - - #define RF_CHNLBW 0x18 -#endif - #endif diff --git a/hal/phydm/phydm_regdefine11ac.h b/hal/phydm/phydm_regdefine11ac.h index 7bcd4d8..6a213e2 100644 --- a/hal/phydm/phydm_regdefine11ac.h +++ b/hal/phydm/phydm_regdefine11ac.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __ODM_REGDEFINE11AC_H__ @@ -60,6 +70,12 @@ #define ODM_REG_HT_CRC32_CNT_11AC 0xF10 #define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14 #define ODM_REG_OFDM_FA_11AC 0xF48 +#define ODM_REG_OFDM_FA_TYPE1_11AC 0xFCC +#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 +#define ODM_REG_OFDM_FA_TYPE3_11AC 0xFBC +#define ODM_REG_OFDM_FA_TYPE4_11AC 0xFC0 +#define ODM_REG_OFDM_FA_TYPE5_11AC 0xFC4 +#define ODM_REG_OFDM_FA_TYPE6_11AC 0xFC8 #define ODM_REG_RPT_11AC 0xfa0 #define ODM_REG_CLM_RESULT_11AC 0xfa4 #define ODM_REG_NHM_CNT_11AC 0xfa8 @@ -67,7 +83,6 @@ #define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac #define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0 -#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 /* PAGE 18 */ #define ODM_REG_IGI_C_11AC 0x1850 /* PAGE 1A */ @@ -79,7 +94,7 @@ /* DIG Related */ -#define ODM_BIT_IGI_11AC 0xFFFFFFFF +#define ODM_BIT_IGI_11AC 0x0000007F #define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16) #define ODM_BIT_BB_RX_PATH_11AC 0xF #define ODM_BIT_BB_TX_PATH_11AC 0xF diff --git a/hal/phydm/phydm_regdefine11n.h b/hal/phydm/phydm_regdefine11n.h index 7d85b94..1d8326d 100644 --- a/hal/phydm/phydm_regdefine11n.h +++ b/hal/phydm/phydm_regdefine11n.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __ODM_REGDEFINE11N_H__ @@ -42,8 +52,8 @@ #define ODM_REG_BB_PWR_SAV5_11N 0x818 #define ODM_REG_CCK_RPT_FORMAT_11N 0x824 #define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C -#define ODM_REG_RX_DEFUALT_A_11N 0x858 -#define ODM_REG_RX_DEFUALT_B_11N 0x85A +#define ODM_REG_RX_DEFAULT_A_11N 0x858 +#define ODM_REG_RX_DEFAULT_B_11N 0x85A #define ODM_REG_BB_PWR_SAV3_11N 0x85C #define ODM_REG_ANTSEL_CTRL_11N 0x860 #define ODM_REG_RX_ANT_CTRL_11N 0x864 @@ -63,7 +73,7 @@ #define ODM_REG_CLM_RESULT_11N 0x8d0 #define ODM_REG_NHM_CNT_11N 0x8d8 -/* For struct _ACS_, Jeffery, 2014-12-26 */ +/* For struct acs_info, Jeffery, 2014-12-26 */ #define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc #define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0 #define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4 @@ -76,6 +86,7 @@ #define ODM_REG_ANT_MAPPING2_11N 0x918 #define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 #define ODM_REG_RX_DFIR_MOD_97F 0x948 +#define ODM_REG_SOML_97F 0x998 /* PAGE A */ #define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 diff --git a/hal/phydm/phydm_types.h b/hal/phydm/phydm_types.h index 2d4417c..d1248e4 100644 --- a/hal/phydm/phydm_types.h +++ b/hal/phydm/phydm_types.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,20 +8,30 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __ODM_TYPES_H__ #define __ODM_TYPES_H__ /*Define Different SW team support*/ -#define ODM_AP 0x01 /*BIT0*/ -#define ODM_CE 0x04 /*BIT2*/ -#define ODM_WIN 0x08 /*BIT3*/ -#define ODM_ADSL 0x10 /*BIT4*/ /*already combine with ODM_AP, and is nouse now*/ -#define ODM_IOT 0x20 /*BIT5*/ +#define ODM_AP 0x01 /*BIT(0)*/ +#define ODM_CE 0x04 /*BIT(2)*/ +#define ODM_WIN 0x08 /*BIT(3)*/ +#define ODM_ADSL 0x10 /*BIT(4)*/ /*already combine with ODM_AP, and is nouse now*/ +#define ODM_IOT 0x20 /*BIT(5)*/ /*For FW API*/ #define __iram_odm_func__ @@ -31,11 +41,11 @@ #define ODM_ENDIAN_LITTLE 1 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->DM_OutSrc))) + #define GET_PDM_ODM(__padapter) ((struct dm_struct*)(&(GET_HAL_DATA(__padapter))->DM_OutSrc)) #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->odmpriv))) + #define GET_PDM_ODM(__padapter) ((struct dm_struct*)(&(GET_HAL_DATA(__padapter))->odmpriv)) #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - #define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&(__padapter->pshare->_dmODM))) + #define GET_PDM_ODM(__padapter) ((struct dm_struct*)(&__padapter->pshare->_dmODM)) #endif #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) @@ -113,7 +123,6 @@ enum rt_spinlock_type { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #define sta_info _RT_WLAN_STA - #define cmn_sta_info _RT_WLAN_STA /*tmp add for compile*/ #define __func__ __FUNCTION__ #define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT #define MASKH3BYTES 0xffffff00 @@ -132,7 +141,7 @@ enum rt_spinlock_type { #define u64 u8Byte #define s64 s8Byte - #define timer_list _RT_TIMER + #define phydm_timer_list _RT_TIMER #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) @@ -142,9 +151,6 @@ enum rt_spinlock_type { #define DEV_BUS_TYPE RT_PCI_INTERFACE #endif - #define _TRUE 1 - #define _FALSE 0 - #if (defined(TESTCHIP_SUPPORT)) #define PHYDM_TESTCHIP_SUPPORT 1 #else @@ -152,9 +158,10 @@ enum rt_spinlock_type { #endif #define sta_info stat_info - #define cmn_sta_info stat_info /*tmp add for compile*/ #define boolean bool + #define phydm_timer_list timer_list + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) #include @@ -176,29 +183,13 @@ enum rt_spinlock_type { #define RTL8881A_SUPPORT 0 #define PHYDM_TESTCHIP_SUPPORT 0 - /* support list */ - #define RTL8188E_SUPPORT 0 - #define RTL8812A_SUPPORT 0 - #define RTL8821A_SUPPORT 0 - #define RTL8723B_SUPPORT 0 - #define RTL8723D_SUPPORT 0 - #define RTL8192E_SUPPORT 0 - #define RTL8814A_SUPPORT 0 - #define RTL8195A_SUPPORT 0 - #define RTL8197F_SUPPORT 0 - #define RTL8703B_SUPPORT 0 - #define RTL8188F_SUPPORT 0 - #define RTL8822B_SUPPORT 1 - #define RTL8821B_SUPPORT 0 - #define RTL8821C_SUPPORT 0 #define RATE_ADAPTIVE_SUPPORT 0 #define POWER_TRAINING_ACTIVE 0 #define sta_info rtl_sta_info - #define cmn_sta_info rtl_sta_info /*tmp add for compile*/ - #define _FALSE false #define boolean bool + #define phydm_timer_list rtw_timer_list #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) #include @@ -222,10 +213,6 @@ enum rt_spinlock_type { #define boolean bool - #define true _TRUE - #define false _FALSE - - #define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+8, 24, 1, __value) #define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+8, 25, 1, __value) #define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+28, 29, 1, __value) @@ -241,6 +228,8 @@ enum rt_spinlock_type { #else #define PHYDM_TESTCHIP_SUPPORT 0 #endif + + #define phydm_timer_list rtw_timer_list #endif #define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i+1]; } while (0) diff --git a/hal/phydm/rtchnlplan.c b/hal/phydm/rtchnlplan.c deleted file mode 100644 index 9c29145..0000000 --- a/hal/phydm/rtchnlplan.c +++ /dev/null @@ -1,481 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -/****************************************************************************** - - History: - Data Who Remark (Internal History) - - 05/14/2012 MH Collect RTK inernal infromation and generate channel plan draft. - -******************************************************************************/ - -//============================================================ -// include files -//============================================================ -#include "mp_precomp.h" -#include "phydm_precomp.h" -#include "rtchnlplan.h" - - - -// -// Channel Plan Domain Code -// - -/* - Channel Plan Contents - Domain Code EEPROM Countries in Specific Domain - 2G RD 5G RD Bit[6:0] 2G 5G - Case Old Define 00h~1Fh Old Define Old Define - 1 2G_WORLD 5G_NULL 20h Worldwird 13 NA - 2 2G_ETSI1 5G_NULL 21h Europe 2G NA - 3 2G_FCC1 5G_NULL 22h US 2G NA - 4 2G_MKK1 5G_NULL 23h Japan 2G NA - 5 2G_ETSI2 5G_NULL 24h France 2G NA - 6 2G_FCC1 5G_FCC1 25h US 2G US 5G ¤K¤j°ê»{ÃÒ - 7 2G_WORLD 5G_ETSI1 26h Worldwird 13 Europe ¤K¤j°ê»{ÃÒ - 8 2G_MKK1 5G_MKK1 27h Japan 2G Japan 5G ¤K¤j°ê»{ÃÒ - 9 2G_WORLD 5G_KCC1 28h Worldwird 13 Korea ¤K¤j°ê»{ÃÒ - 10 2G_WORLD 5G_FCC2 29h Worldwird 13 US o/w DFS Channels - 11 2G_WORLD 5G_FCC3 30h Worldwird 13 India, Mexico - 12 2G_WORLD 5G_FCC4 31h Worldwird 13 Venezuela - 13 2G_WORLD 5G_FCC5 32h Worldwird 13 China - 14 2G_WORLD 5G_FCC6 33h Worldwird 13 Israel - 15 2G_FCC1 5G_FCC7 34h US 2G US/Canada ¤K¤j°ê»{ÃÒ - 16 2G_WORLD 5G_ETSI2 35h Worldwird 13 Australia, New Zealand ¤K¤j°ê»{ÃÒ - 17 2G_WORLD 5G_ETSI3 36h Worldwird 13 Russia - 18 2G_MKK1 5G_MKK2 37h Japan 2G Japan (W52, W53) - 19 2G_MKK1 5G_MKK3 38h Japan 2G Japan (W56) - 20 2G_FCC1 5G_NCC1 39h US 2G Taiwan ¤K¤j°ê»{ÃÒ - - NA 2G_WORLD 5G_FCC1 7F FCC FCC DFS Channels Realtek Define - - - - - - 2.4G Regulatory Domains - Case 2G RD Regulation Channels Frequencyes Note Countries in Specific Domain - 1 2G_WORLD ETSI 1~13 2412~2472 Passive scan CH 12, 13 Worldwird 13 - 2 2G_ETSI1 ETSI 1~13 2412~2472 Europe - 3 2G_FCC1 FCC 1~11 2412~2462 US - 4 2G_MKK1 MKK 1~13, 14 2412~2472, 2484 Japan - 5 2G_ETSI2 ETSI 10~13 2457~2472 France - - - - - 5G Regulatory Domains - Case 5G RD Regulation Channels Frequencyes Note Countries in Specific Domain - 1 5G_NULL NA NA NA Do not support 5GHz - 2 5G_ETSI1 ETSI "36~48, 52~64, - 100~140" "5180~5240, 5260~5230 - 5500~5700" Band1, Ban2, Band3 Europe - 3 5G_ETSI2 ETSI "36~48, 52~64, - 100~140, 149~165" "5180~5240, 5260~5230 - 5500~5700, 5745~5825" Band1, Ban2, Band3, Band4 Australia, New Zealand - 4 5G_ETSI3 ETSI "36~48, 52~64, - 100~132, 149~165" - "5180~5240, 5260~5230 - 5500~5660, 5745~5825" Band1, Ban2, Band3(except CH 136, 140), Band4" Russia - 5 5G_FCC1 FCC "36~48, 52~64, - 100~140, 149~165" - "5180~5240, 5260~5230 - 5500~5700, 5745~5825" Band1(5150~5250MHz), - Band2(5250~5350MHz), - Band3(5470~5725MHz), - Band4(5725~5850MHz)" US - 6 5G_FCC2 FCC 36~48, 149~165 5180~5240, 5745~5825 Band1, Band4 FCC o/w DFS Channels - 7 5G_FCC3 FCC "36~48, 52~64, - 149~165" "5180~5240, 5260~5230 - 5745~5825" Band1, Ban2, Band4 India, Mexico - 8 5G_FCC4 FCC "36~48, 52~64, - 149~161" "5180~5240, 5260~5230 - 5745~5805" Band1, Ban2, - Band4(except CH 165)" Venezuela - 9 5G_FCC5 FCC 149~165 5745~5825 Band4 China - 10 5G_FCC6 FCC 36~48, 52~64 5180~5240, 5260~5230 Band1, Band2 Israel - 11 5G_FCC7 - 5G_IC1 FCC - IC" "36~48, 52~64, - 100~116, 136, 140, - 149~165" "5180~5240, 5260~5230 - 5500~5580, 5680, 5700, - 5745~5825" "Band1, Band2, - Band3(except 5600~5650MHz), - Band4" "US - Canada" - 12 5G_KCC1 KCC "36~48, 52~64, - 100~124, 149~165" "5180~5240, 5260~5230 - 5500~5620, 5745~5825" "Band1, Ban2, - Band3(5470~5650MHz), - Band4" Korea - 13 5G_MKK1 MKK "36~48, 52~64, - 100~140" "5180~5240, 5260~5230 - 5500~5700" W52, W53, W56 Japan - 14 5G_MKK2 MKK 36~48, 52~64 5180~5240, 5260~5230 W52, W53 Japan (W52, W53) - 15 5G_MKK3 MKK 100~140 5500~5700 W56 Japan (W56) - 16 5G_NCC1 NCC "56~64, - 100~116, 136, 140, - 149~165" "5260~5320 - 5500~5580, 5680, 5700, - 5745~5825" "Band2(except CH 52), - Band3(except 5600~5650MHz), - Band4" Taiwan - - -*/ - -// -// 2.4G CHannel -// -/* - - 2.4G Band Regulatory Domains RTL8192D - Channel Number Channel Frequency US Canada Europe Spain France Japan Japan 20M 40M - (MHz) (FCC) (IC) (ETSI) (MPHPT) - 1 2412 v v v v v - 2 2417 v v v v v - 3 2422 v v v v v v - 4 2427 v v v v v v - 5 2432 v v v v v v - 6 2437 v v v v v v - 7 2442 v v v v v v - 8 2447 v v v v v v - 9 2452 v v v v v v - 10 2457 v v v v v v v v - 11 2462 v v v v v v v v - 12 2467 v v v v v - 13 2472 v v v v - 14 2484 v v - - -*/ - - -// -// 5G Operating Channel -// -/* - - 5G Band RTL8192D RTL8195 (Jaguar) Jaguar 2 Regulatory Domains - Channel Number Channel Frequency Global Global Global "US -(FCC 15.407)" "Canada -(FCC, except 5.6~5.65GHz)" Argentina, Australia, New Zealand, Brazil, S. Africa (FCC/ETSI) "Europe -(CE 301 893)" China India, Mexico, Singapore Israel, Turkey "Japan -(MIC Item 19-3, 19-3-2)" Korea Russia, Ukraine "Taiwan -(NCC)" Venezuela - (MHz) (20MHz) (20MHz) (40MHz) (80MHz) (160MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) -"Band 1 -5.15GHz -~ -5.25GHz" 36 5180 v v v v v Indoor Indoor v Indoor v Indoor Indoor v v v - 40 5200 v v v Indoor Indoor v Indoor v Indoor Indoor v v v - 44 5220 v v v v Indoor Indoor v Indoor v Indoor Indoor v v v - 48 5240 v v v Indoor Indoor v Indoor v Indoor Indoor v v v -"Band 2 -5.25GHz -~ -5.35GHz -(DFS)" 52 5260 v v v v v v v v Indoor v Indoor Indoor v v v - 56 5280 v v v v v v Indoor v Indoor Indoor v v Indoor v - 60 5300 v v v v v v v Indoor v Indoor Indoor v v Indoor v - 64 5320 v v v v v v Indoor v Indoor Indoor v v Indoor v - -"Band 3 -5.47GHz -~ -5.725GHz -(DFS)" 100 5500 v v v v v v v v v v v v v - 104 5520 v v v v v v v v v v v - 108 5540 v v v v v v v v v v v v - 112 5560 v v v v v v v v v v v - 116 5580 v v v v v v v v v v v v v - 120 5600 v v v Indoor v Indoor v v v - 124 5620 v v v v Indoor v Indoor v v v - 128 5640 v v v Indoor v Indoor v v - 132 5660 v v v E v Indoor v Indoor v v - 136 5680 v v v v v v v v v - 140 5700 v v E v v v v v v v - 144 5720 E E E -"Band 4 -5.725GHz -~ -5.85GHz -(~5.9GHz)" 149 5745 v v v v v v v v v v v v v v - 153 5765 v v v v v v v v v v v v - 157 5785 v v v v v v v v v v v v v - 161 5805 v v v v v v v v v v v v - 165 5825 v v P P v v v v v v v v v - 169 5845 P P P - 173 5865 P P P P - 177 5885 P P P -Channel Count 28 28 14 7 0 28 24 20 24 19 5 13 8 19 20 22 15 12 - E: FCC accepted the ask for CH144 from Accord. PS: 160MHz ¥Î 80MHz+80MHz¹ê²{¡H Argentina Belgium (¤ñ§Q®É) India Israel Russia - P: Customer's requirement from James. Australia The Netherlands (²üÄõ) Mexico Turkey Ukraine - New Zealand UK (­^°ê) Singapore - Brazil Switzerland (·ç¤h) - - -*/ - -/*---------------------------Define Local Constant---------------------------*/ - - -// define Maximum Power v.s each band for each region -// ISRAEL -// Format: -// RT_CHANNEL_DOMAIN_Region ={{{Chnl_Start, Chnl_end, Pwr_dB_Max}, {Chn2_Start, Chn2_end, Pwr_dB_Max}, {Chn3_Start, Chn3_end, Pwr_dB_Max}, {Chn4_Start, Chn4_end, Pwr_dB_Max}, {Chn5_Start, Chn5_end, Pwr_dB_Max}}, Limit_Num} */ -// RT_CHANNEL_DOMAIN_FCC ={{{01,11,30}, {36,48,17}, {52,64,24}, {100,140,24}, {149,165,30}}, 5} -// "NR" is non-release channle. -// Issue--- Israel--Russia--New Zealand -// DOMAIN_01= (2G_WORLD, 5G_NULL) -// DOMAIN_02= (2G_ETSI1, 5G_NULL) -// DOMAIN_03= (2G_FCC1, 5G_NULL) -// DOMAIN_04= (2G_MKK1, 5G_NULL) -// DOMAIN_05= (2G_ETSI2, 5G_NULL) -// DOMAIN_06= (2G_FCC1, 5G_FCC1) -// DOMAIN_07= (2G_WORLD, 5G_ETSI1) -// DOMAIN_08= (2G_MKK1, 5G_MKK1) -// DOMAIN_09= (2G_WORLD, 5G_KCC1) -// DOMAIN_10= (2G_WORLD, 5G_FCC2) -// DOMAIN_11= (2G_WORLD, 5G_FCC3)----india -// DOMAIN_12= (2G_WORLD, 5G_FCC4)----Venezuela -// DOMAIN_13= (2G_WORLD, 5G_FCC5)----China -// DOMAIN_14= (2G_WORLD, 5G_FCC6)----Israel -// DOMAIN_15= (2G_FCC1, 5G_FCC7)-----Canada -// DOMAIN_16= (2G_WORLD, 5G_ETSI2)---Australia -// DOMAIN_17= (2G_WORLD, 5G_ETSI3)---Russia -// DOMAIN_18= (2G_MKK1, 5G_MKK2)-----Japan -// DOMAIN_19= (2G_MKK1, 5G_MKK3)-----Japan -// DOMAIN_20= (2G_FCC1, 5G_NCC1)-----Taiwan -// DOMAIN_21= (2G_FCC1, 5G_NCC1)-----Taiwan - - -static RT_CHANNEL_PLAN_MAXPWR ChnlPlanPwrMax_2G[] = { - - // 2G_WORLD, - {{1, 13, 20}, 1}, - - // 2G_ETSI1 - {{1, 13, 20}, 1}, - - /* RT_CHANNEL_DOMAIN_ETSI */ - {{{1, 11, 17}, {40, 56, 17}, {60, 128, 17}, {0, 0, 0}, {149, 165, 17}}, 4}, - - // RT_CHANNEL_DOMAIN_MKK - {{{1, 11, 17}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}}, 1}, - - // Add new channel plan mex power table. - // ...... - }; - - -/* -//===========================================1:(2G_WORLD, 5G_NULL) - -RT_CHANNEL_PLAN_MAXPWR RT_DOMAIN_01 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} - -//===========================================2:(2G_ETSI1, 5G_NULL) - -RT_DOMAIN_02 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} - -//===========================================3:(2G_FCC1, 5G_NULL) - -RT_DOMAIN_03 ={{{01,11,30}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} - -//===========================================4:(2G_MKK1, 5G_NULL) - -RT_DOMAIN_04 ={{{01,14,23}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} - -//===========================================5:(2G_ETSI2, 5G_NULL) - -RT_DOMAIN_05 ={{{10,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} - -//===========================================6:(2G_FCC1, 5G_FCC1) - -RT_DOMAIN_06 ={{{01,13,30}, {36,48,17}, {52,64,24}, {100,140,24}, {149,165,30}}, 5} - -//===========================================7:(2G_WORLD, 5G_ETSI1) - -RT_DOMAIN_07 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {NR,NR,0}}, 4} - -//===========================================8:(2G_MKK1, 5G_MKK1) - -RT_DOMAIN_08 ={{{01,14,23}, {36,48,23}, {52,64,23}, {100,140,23}, {NR,NR,0}}, 4} - -//===========================================9:(2G_WORLD, 5G_KCC1) - -RT_DOMAIN_09 ={{{01,13,20}, {36,48,17}, {52,64,23}, {100,124,23}, {149,165,23}}, 5} - -//===========================================10:(2G_WORLD, 5G_FCC2) - -RT_DOMAIN_10 ={{{01,13,20}, {36,48,17}, {NR,NR,0}, {NR,NR,0}, {149,165,30}}, 3} - -//===========================================11:(2G_WORLD, 5G_FCC3) -RT_DOMAIN_11 ={{{01,13,20}, {36,48,23}, {52,64,23}, {NR,NR,0}, {149,165,23}}, 4} - -//===========================================12:(2G_WORLD, 5G_FCC4) -RT_DOMAIN_12 ={{{01,13,20}, {36,48,24}, {52,64,24}, {NR,NR,0}, {149,161,27}}, 4} - -//===========================================13:(2G_WORLD, 5G_FCC5) -RT_DOMAIN_13 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {149,165,27}}, 2} - -//===========================================14:(2G_WORLD, 5G_FCC6) -RT_DOMAIN_14 ={{{01,13,20}, {36,48,17}, {52,64,17}, {NR,NR,0}, {NR,NR,0}}, 3} - -//===========================================15:(2G_FCC1, 5G_FCC7) -RT_DOMAIN_15 ={{{01,11,30}, {36,48,23}, {52,64,24}, {100,140,24}, {149,165,30}}, 5} - -//===========================================16:(2G_WORLD, 5G_ETSI2) -RT_DOMAIN_16 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {149,165,30}}, 5} - -//===========================================17:(2G_WORLD, 5G_ETSI3) -RT_DOMAIN_17 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,132,30}, {149,165,20}}, 5} - -//===========================================18:(2G_MKK1, 5G_MKK2) -RT_DOMAIN_18 ={{{01,14,23}, {36,48,23}, {52,64,23}, {NR,NR,0}, {NR,NR,0}}, 3} - -//===========================================19:(2G_MKK1, 5G_MKK3) -RT_DOMAIN_19 ={{{01,14,23}, {NR,NR,0}, {NR,NR,0}, {100,140,23}, {NR,NR,0}}, 2} - -//===========================================20:(2G_FCC1, 5G_NCC1) -RT_DOMAIN_20 ={{{01,11,30}, {NR,NR,0}, {56,64,23}, {100,140,24}, {149,165,30}}, 4} - -//===========================================21:(2G_FCC1, 5G_NCC2) -RT_DOMAIN_21 ={{{01,11,30}, {NR,NR,0}, {56,64,23}, {NR,NR,0}, {149,165,30}}, 3} - -//===========================================22:(2G_WORLD, 5G_FCC3) -RT_DOMAIN_22 ={{{01,13,24}, {36,48,20}, {52,64,24}, {NR,NR,0}, {149,165,30}}, 4} - -//===========================================23:(2G_WORLD, 5G_ETSI2) -RT_DOMAIN_23 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {149,165,30}}, 5} - -*/ - -// -// Counter & Realtek Channel plan transfer table. -// -RT_CHNL_CTRY_TBL RtCtryChnlTbl[] = -{ - - { - RT_CTRY_AL, // "Albaniaªüº¸¤Ú¥§¨È" - "AL", - RT_2G_WORLD, - RT_5G_WORLD, - RT_CHANNEL_DOMAIN_UNDEFINED // 2G/5G world. - }, -#if 0 - { - RT_CTRY_BB, // "Barbados¤Ú¤Ú¦h´µ" - "BB", - RT_2G_WORLD, - RT_5G_NULL, - RT_CHANNEL_DOMAIN_EFUSE_0x20 // 2G world. 5G_NULL - }, - - { - RT_CTRY_DE, // "Germany¼w°ê" - "DE", - RT_2G_WORLD, - RT_5G_ETSI1, - RT_CHANNEL_DOMAIN_EFUSE_0x26 - }, - - { - RT_CTRY_US, // "Germany¼w°ê" - "US", - RT_2G_FCC1, - RT_5G_FCC7, - RT_CHANNEL_DOMAIN_EFUSE_0x34 - }, - - { - RT_CTRY_JP, // "Germany¼w°ê" - "JP", - RT_2G_MKK1, - RT_5G_MKK1, - RT_CHANNEL_DOMAIN_EFUSE_0x34 - }, - - { - RT_CTRY_TW, // "Germany¼w°ê" - "TW", - RT_2G_FCC1, - RT_5G_NCC1, - RT_CHANNEL_DOMAIN_EFUSE_0x39 - }, -#endif - -}; // RtCtryChnlTbl - -// -// Realtek Defined Channel plan. -// -#if 0 - -static RT_CHANNEL_PLAN_NEW RtChnlPlan[] = -{ - // Channel Plan 0x20. - { - &RtCtryChnlTbl[1], // RT_CHNL_CTRY_TBL Country & channel plan transfer table. - RT_CHANNEL_DOMAIN_EFUSE_0x20, // RT_CHANNEL_DOMAIN RT Channel Plan Define - RT_2G_WORLD, // RT_REGULATION_2G - RT_5G_NULL, // RT_REGULATION_5G - RT_WORLD, // RT_REGULATION_CMN RT Regulatory domain definition. - RT_SREQ_NA, // RT Channel plan special & customerize requirement. - - CHNL_RT_2G_WORLD, - CHNL_RT_2G_WORLD_SCAN_TYPE, - &ChnlPlanPwrMax_2G[0], - - CHNL_RT_5G_NULL, - CHNL_RT_5G_NULL_SCAN_TYPE, - - - }, - - // Channel Plan 0x26. - { - &RtCtryChnlTbl[1], // RT_CHNL_CTRY_TBL Country & channel plan transfer table. - RT_CHANNEL_DOMAIN_EFUSE_0x26, // RT_CHANNEL_DOMAIN RT Channel Plan Define - RT_2G_WORLD, // RT_REGULATION_2G - RT_5G_ETSI1, // RT_REGULATION_5G - RT_WORLD, // RT_REGULATION_CMN RT Regulatory domain definition. - RT_SREQ_NA, // RT Channel plan special & customerize requirement. - - CHNL_RT_2G_WORLD, // 2G workd cannel - CHNL_RT_2G_WORLD_SCAN_TYPE, - &ChnlPlanPwrMax_2G[1], - - CHNL_RT_5G_ETSI1, - CHNL_RT_5G_ETSI1_SCAN_TYPE, - - } - - -}; -#endif - - - - diff --git a/hal/phydm/rtchnlplan.h b/hal/phydm/rtchnlplan.h deleted file mode 100644 index 78a31dc..0000000 --- a/hal/phydm/rtchnlplan.h +++ /dev/null @@ -1,699 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - - -#ifndef __RT_CHANNELPLAN_H__ -#define __RT_CHANNELPLAN_H__ - -typedef enum _RT_CHANNEL_DOMAIN_NEW -{ - - //===== Add new channel plan above this line ===============// - - // For new architecture we define different 2G/5G CH area for all country. - // 2.4 G only - RT_CHANNEL_DOMAIN_2G_WORLD_5G_NULL = 0x20, - RT_CHANNEL_DOMAIN_2G_ETSI1_5G_NULL = 0x21, - RT_CHANNEL_DOMAIN_2G_FCC1_5G_NULL = 0x22, - RT_CHANNEL_DOMAIN_2G_MKK1_5G_NULL = 0x23, - RT_CHANNEL_DOMAIN_2G_ETSI2_5G_NULL = 0x24, - // 2.4 G + 5G type 1 - RT_CHANNEL_DOMAIN_2G_FCC1_5G_FCC1 = 0x25, - RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x26, - //RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x27, - // ..... - - RT_CHANNEL_DOMAIN_MAX_NEW, - -}RT_CHANNEL_DOMAIN_NEW, *PRT_CHANNEL_DOMAIN_NEW; - - -#if 0 -#define DOMAIN_CODE_2G_WORLD \ - {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 -#define DOMAIN_CODE_2G_ETSI1 \ - {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 -#define DOMAIN_CODE_2G_ETSI2 \ - {1,2,3,4,5,6,7,8,9,10,11}, 11 -#define DOMAIN_CODE_2G_FCC1 \ - {1,2,3,4,5,6,7,8,9,10,11,12,13,14}, 14 -#define DOMAIN_CODE_2G_MKK1 \ - {10,11,12,13}, 4 - -#define DOMAIN_CODE_5G_ETSI1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 -#define DOMAIN_CODE_5G_ETSI2 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 -#define DOMAIN_CODE_5G_ETSI3 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 -#define DOMAIN_CODE_5G_FCC1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 -#define DOMAIN_CODE_5G_FCC2 \ - {36,40,44,48,149,153,157,161,165}, 9 -#define DOMAIN_CODE_5G_FCC3 \ - {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 -#define DOMAIN_CODE_5G_FCC4 \ - {36,40,44,48,52,56,60,64,149,153,157,161}, 12 -#define DOMAIN_CODE_5G_FCC5 \ - {149,153,157,161,165}, 5 -#define DOMAIN_CODE_5G_FCC6 \ - {36,40,44,48,52,56,60,64}, 8 -#define DOMAIN_CODE_5G_FCC7 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 -#define DOMAIN_CODE_5G_IC1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 -#define DOMAIN_CODE_5G_KCC1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 -#define DOMAIN_CODE_5G_MKK1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 -#define DOMAIN_CODE_5G_MKK2 \ - {36,40,44,48,52,56,60,64}, 8 -#define DOMAIN_CODE_5G_MKK3 \ - {100,104,108,112,116,120,124,128,132,136,140}, 11 -#define DOMAIN_CODE_5G_NCC1 \ - {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 -#define DOMAIN_CODE_5G_NCC2 \ - {56,60,64,149,153,157,161,165}, 8 -#define UNDEFINED \ - {0}, 0 -#endif - -// -// -// -/* - -Countries "Country Abbreviation" Domain Code SKU's Ch# of 20MHz - 2G 5G Ch# of 40MHz -"Albaniaªüº¸¤Ú¥§¨È" AL Local Test - -"Algeriaªüº¸¤Î§Q¨È" DZ CE TCF - -"Antigua & Barbuda¦w´£¥Ê®q&¤Ú¥¬¹F" AG 2G_WORLD FCC TCF - -"Argentinaªü®Ú§Ê" AR 2G_WORLD Local Test - -"Armenia¨È¬ü¥§¨È" AM 2G_WORLD ETSI - -"Arubaªü¾|¤Ú®q" AW 2G_WORLD FCC TCF - -"Australia¿D¬w" AU 2G_WORLD 5G_ETSI2 - -"Austria¶ø¦a§Q" AT 2G_WORLD 5G_ETSI1 CE - -"Azerbaijanªü¶ë«ô¾Ê" AZ 2G_WORLD CE TCF - -"Bahamas¤Ú«¢°¨" BS 2G_WORLD - -"Barbados¤Ú¤Ú¦h´µ" BB 2G_WORLD FCC TCF - -"Belgium¤ñ§Q®É" BE 2G_WORLD 5G_ETSI1 CE - -"Bermuda¦Ê¼}¹F" BM 2G_WORLD FCC TCF - -"Brazil¤Ú¦è" BR 2G_WORLD Local Test - -"Bulgaria«O¥[§Q¨È" BG 2G_WORLD 5G_ETSI1 CE - -"Canada¥[®³¤j" CA 2G_FCC1 5G_FCC7 IC / FCC IC / FCC - -"Cayman Islands¶}°Ò¸s®q" KY 2G_WORLD 5G_ETSI1 CE - -"Chile´¼§Q" CL 2G_WORLD FCC TCF - -"China¤¤°ê" CN 2G_WORLD 5G_FCC5 «H³¡?¡i2002¡j353? - -"Columbia­ô­Û¤ñ¨È" CO 2G_WORLD Voluntary - -"Costa Rica­ô´µ¹F¾¤¥[" CR 2G_WORLD FCC TCF - -"Cyprus¶ë®ú¸ô´µ" CY 2G_WORLD 5G_ETSI1 CE - -"Czech ±¶§J" CZ 2G_WORLD 5G_ETSI1 CE - -"Denmark¤¦³Á" DK 2G_WORLD 5G_ETSI1 CE - -"Dominican Republic¦h©ú¥§¥[¦@©M°ê" DO 2G_WORLD FCC TCF - -"Egypt®J¤Î" EG 2G_WORLD CE T CF - -"El SalvadorÂĺ¸¥Ë¦h" SV 2G_WORLD Voluntary - -"Estonia·R¨F¥§¨È" EE 2G_WORLD 5G_ETSI1 CE - -"FinlandªâÄõ" FI 2G_WORLD 5G_ETSI1 CE - -"Franceªk°ê" FR 5G_E TSI1 CE - -"Germany¼w°ê" DE 2G_WORLD 5G_ETSI1 CE - -"Greece §Æþ" GR 2G_WORLD 5G_ETSI1 CE - -"GuamÃö®q" GU 2G_WORLD - -"Guatemala¥Ê¦a°¨©Ô" GT 2G_WORLD - -"Haiti®ü¦a" HT 2G_WORLD FCC TCF - -"Honduras§»³£©Ô´µ" HN 2G_WORLD FCC TCF - -"Hungary¦I¤ú§Q" HU 2G_WORLD 5G_ETSI1 CE - -"Iceland¦B®q" IS 2G_WORLD 5G_ETSI1 CE - -"India¦L«×" IN 2G_WORLD 5G_FCC3 FCC/CE TCF - -"Ireland·Rº¸Äõ" IE 2G_WORLD 5G_ETSI1 CE - -"Israel¥H¦â¦C" IL 5G_F CC6 CE TCF - -"Italy¸q¤j§Q" IT 2G_WORLD 5G_ETSI1 CE - -"Japan¤é¥»" JP 2G_MKK1 5G_MKK1 MKK MKK - -"KoreaÁú°ê" KR 2G_WORLD 5G_KCC1 KCC KCC - -"Latvia©Ô²æºû¨È" LV 2G_WORLD 5G_ETSI1 CE - -"Lithuania¥ß³³©{" LT 2G_WORLD 5G_ETSI1 CE - -"Luxembourg¿c´Ë³ù" LU 2G_WORLD 5G_ETSI1 CE - -"Malaysia°¨¨Ó¦è¨È" MY 2G_WORLD Local Test - -"Malta°¨º¸¥L" MT 2G_WORLD 5G_ETSI1 CE - -"Mexico¾¥¦è­ô" MX 2G_WORLD 5G_FCC3 Local Test - -"Morocco¼¯¬¥­ô" MA CE TCF - -"Netherlands²üÄõ" NL 2G_WORLD 5G_ETSI1 CE - -"New Zealand¯Ã¦èÄõ" NZ 2G_WORLD 5G_ETSI2 - -"Norway®¿«Â" NO 2G_WORLD 5G_ETSI1 CE - -"Panama¤Ú®³°¨ " PA 2G_FCC1 Voluntary - -"Philippinesµá«ß»«" PH 2G_WORLD FCC TCF - -"PolandªiÄõ" PL 2G_WORLD 5G_ETSI1 CE - -"Portugal¸²µå¤ú" PT 2G_WORLD 5G_ETSI1 CE - -"Romaniaù°¨¥§¨È" RO 2G_WORLD 5G_ETSI1 CE - -"Russia«Xù´µ" RU 2G_WORLD 5G_ETSI3 CE TCF - -"Saudi Arabia¨F¦aªü©Ô§B" SA 2G_WORLD CE TCF - -"Singapore·s¥[©Y" SG 2G_WORLD - -"Slovakia´µ¬¥¥ï§J" SK 2G_WORLD 5G_ETSI1 CE - -"Slovenia´µ¬¥ºû¥§¨È" SI 2G_WORLD 5G_ETSI1 CE - -"South Africa«n«D" ZA 2G_WORLD CE TCF - -"Spain¦è¯Z¤ú" ES 5G_ETSI1 CE - -"Sweden·ç¨å" SE 2G_WORLD 5G_ETSI1 CE - -"Switzerland·ç¤h" CH 2G_WORLD 5G_ETSI1 CE - -"Taiwan»OÆW" TW 2G_FCC1 5G_NCC1 NCC - -"Thailand®õ°ê" TH 2G_WORLD FCC/CE TCF - -"Turkey¤g¦Õ¨ä" TR 2G_WORLD - -"Ukraine¯Q§JÄõ" UA 2G_WORLD Local Test - -"United Kingdom­^°ê" GB 2G_WORLD 5G_ETSI1 CE ETSI - -"United States¬ü°ê" US 2G_FCC1 5G_FCC7 FCC FCC - -"Venezuela©e¤º·ç©Ô" VE 2G_WORLD 5G_FCC4 FCC TCF - -"Vietnam¶V«n" VN 2G_WORLD FCC/CE TCF - - - -*/ - -// Counter abbervation. -typedef enum _RT_COUNTRY_DEFINE_NUM -{ - RT_CTRY_AL, // "Albaniaªüº¸¤Ú¥§¨È" - RT_CTRY_DZ, // "Algeriaªüº¸¤Î§Q¨È" - RT_CTRY_AG, // "Antigua & Barbuda¦w´£¥Ê®q&¤Ú¥¬¹F" - RT_CTRY_AR, // "Argentinaªü®Ú§Ê" - RT_CTRY_AM, // "Armenia¨È¬ü¥§¨È" - RT_CTRY_AW, // "Arubaªü¾|¤Ú®q" - RT_CTRY_AU, // "Australia¿D¬w" - RT_CTRY_AT, // "Austria¶ø¦a§Q" - RT_CTRY_AZ, // "Azerbaijanªü¶ë«ô¾Ê" - RT_CTRY_BS, // "Bahamas¤Ú«¢°¨" - RT_CTRY_BB, // "Barbados¤Ú¤Ú¦h´µ" - RT_CTRY_BE, // "Belgium¤ñ§Q®É" - RT_CTRY_BM, // "Bermuda¦Ê¼}¹F" - RT_CTRY_BR, // "Brazil¤Ú¦è" - RT_CTRY_BG, // "Bulgaria«O¥[§Q¨È" - RT_CTRY_CA, // "Canada¥[®³¤j" - RT_CTRY_KY, // "Cayman Islands¶}°Ò¸s®q" - RT_CTRY_CL, // "Chile´¼§Q" - RT_CTRY_CN, // "China¤¤°ê" - RT_CTRY_CO, // "Columbia­ô­Û¤ñ¨È" - RT_CTRY_CR, // "Costa Rica­ô´µ¹F¾¤¥[" - RT_CTRY_CY, // "Cyprus¶ë®ú¸ô´µ" - RT_CTRY_CZ, // "Czech ±¶§J" - RT_CTRY_DK, // "Denmark¤¦³Á" - RT_CTRY_DO, // "Dominican Republic¦h©ú¥§¥[¦@©M°ê" - RT_CTRY_CE, // "Egypt®J¤Î" EG 2G_WORLD - RT_CTRY_SV, // "El SalvadorÂĺ¸¥Ë¦h" - RT_CTRY_EE, // "Estonia·R¨F¥§¨È" - RT_CTRY_FI, // "FinlandªâÄõ" - RT_CTRY_FR, // "Franceªk°ê" - RT_CTRY_DE, // "Germany¼w°ê" - RT_CTRY_GR, // "Greece §Æþ" - RT_CTRY_GU, // "GuamÃö®q" - RT_CTRY_GT, // "Guatemala¥Ê¦a°¨©Ô" - RT_CTRY_HT, // "Haiti®ü¦a" - RT_CTRY_HN, // "Honduras§»³£©Ô´µ" - RT_CTRY_HU, // "Hungary¦I¤ú§Q" - RT_CTRY_IS, // "Iceland¦B®q" - RT_CTRY_IN, // "India¦L«×" - RT_CTRY_IE, // "Ireland·Rº¸Äõ" - RT_CTRY_IL, // "Israel¥H¦â¦C" - RT_CTRY_IT, // "Italy¸q¤j§Q" - RT_CTRY_JP, // "Japan¤é¥»" - RT_CTRY_KR, // "KoreaÁú°ê" - RT_CTRY_LV, // "Latvia©Ô²æºû¨È" - RT_CTRY_LT, // "Lithuania¥ß³³©{" - RT_CTRY_LU, // "Luxembourg¿c´Ë³ù" - RT_CTRY_MY, // "Malaysia°¨¨Ó¦è¨È" - RT_CTRY_MT, // "Malta°¨º¸¥L" - RT_CTRY_MX, // "Mexico¾¥¦è­ô" - RT_CTRY_MA, // "Morocco¼¯¬¥­ô" - RT_CTRY_NL, // "Netherlands²üÄõ" - RT_CTRY_NZ, // "New Zealand¯Ã¦èÄõ" - RT_CTRY_NO, // "Norway®¿«Â" - RT_CTRY_PA, // "Panama¤Ú®³°¨ " - RT_CTRY_PH, // "Philippinesµá«ß»«" - RT_CTRY_PL, // "PolandªiÄõ" - RT_CTRY_PT, // "Portugal¸²µå¤ú" - RT_CTRY_RO, // "Romaniaù°¨¥§¨È" - RT_CTRY_RU, // "Russia«Xù´µ" - RT_CTRY_SA, // "Saudi Arabia¨F¦aªü©Ô§B" - RT_CTRY_SG, // "Singapore·s¥[©Y" - RT_CTRY_SK, // "Slovakia´µ¬¥¥ï§J" - RT_CTRY_SI, // "Slovenia´µ¬¥ºû¥§¨È" - RT_CTRY_ZA, // "South Africa«n«D" - RT_CTRY_ES, // "Spain¦è¯Z¤ú" - RT_CTRY_SE, // "Sweden·ç¨å" - RT_CTRY_CH, // "Switzerland·ç¤h" - RT_CTRY_TW, // "Taiwan»OÆW" - RT_CTRY_TH, // "Thailand®õ°ê" - RT_CTRY_TR, // "Turkey¤g¦Õ¨ä" - RT_CTRY_UA, // "Ukraine¯Q§JÄõ" - RT_CTRY_GB, // "United Kingdom­^°ê" - RT_CTRY_US, // "United States¬ü°ê" - RT_CTRY_VE, // "Venezuela©e¤º·ç©Ô" - RT_CTRY_VN, // "Vietnam¶V«n" - RT_CTRY_MAX, // - -}RT_COUNTRY_NAME, *PRT_COUNTRY_NAME; - -// Scan type including active and passive scan. -typedef enum _RT_SCAN_TYPE_NEW -{ - SCAN_NULL, - SCAN_ACT, - SCAN_PAS, - SCAN_BOTH, -}RT_SCAN_TYPE_NEW, *PRT_SCAN_TYPE_NEW; - - -// Power table sample. - -typedef struct _RT_CHNL_PLAN_LIMIT -{ - u2Byte Chnl_Start; - u2Byte Chnl_end; - - u2Byte Freq_Start; - u2Byte Freq_end; -}RT_CHNL_PLAN_LIMIT, *PRT_CHNL_PLAN_LIMIT; - - -// -// 2.4G Regulatory Domains -// -typedef enum _RT_REGULATION_DOMAIN_2G -{ - RT_2G_NULL, - RT_2G_WORLD, - RT_2G_ETSI1, - RT_2G_FCC1, - RT_2G_MKK1, - RT_2G_ETSI2 - -}RT_REGULATION_2G, *PRT_REGULATION_2G; - - -//typedef struct _RT_CHANNEL_BEHAVIOR -//{ -// u1Byte Chnl; -// RT_SCAN_TYPE_NEW -// -//}RT_CHANNEL_BEHAVIOR, *PRT_CHANNEL_BEHAVIOR; - -//typedef struct _RT_CHANNEL_PLAN_TYPE -//{ -// RT_CHANNEL_BEHAVIOR -// u1Byte Chnl_num; -//}RT_CHNL_PLAN_TYPE, *PRT_CHNL_PLAN_TYPE; - -// -// 2.4G Channel Number -// Channel definition & number -// -#define CHNL_RT_2G_NULL \ - {0}, 0 -#define CHNL_RT_2G_WORLD \ - {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 -#define CHNL_RT_2G_WORLD_TEST \ - {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 - -#define CHNL_RT_2G_EFSI1 \ - {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 -#define CHNL_RT_2G_FCC1 \ - {1,2,3,4,5,6,7,8,9,10,11}, 11 -#define CHNL_RT_2G_MKK1 \ - {1,2,3,4,5,6,7,8,9,10,11,12,13,14}, 14 -#define CHNL_RT_2G_ETSI2 \ - {10,11,12,13}, 4 - -// -// 2.4G Channel Active or passive scan. -// -#define CHNL_RT_2G_NULL_SCAN_TYPE \ - {SCAN_NULL} -#define CHNL_RT_2G_WORLD_SCAN_TYPE \ - {1,1,1,1,1,1,1,1,1,1,1,0,0} -#define CHNL_RT_2G_EFSI1_SCAN_TYPE \ - {1,1,1,1,1,1,1,1,1,1,1,1,1} -#define CHNL_RT_2G_FCC1_SCAN_TYPE \ - {1,1,1,1,1,1,1,1,1,1,1} -#define CHNL_RT_2G_MKK1_SCAN_TYPE \ - {1,1,1,1,1,1,1,1,1,1,1,1,1,1} -#define CHNL_RT_2G_ETSI2_SCAN_TYPE \ - {1,1,1,1} - - -// -// 2.4G Band & Frequency Section -// Freqency start & end / band number -// -#define FREQ_RT_2G_NULL \ - {0}, 0 - // Passive scan CH 12, 13 -#define FREQ_RT_2G_WORLD \ - {2412, 2472}, 1 -#define FREQ_RT_2G_EFSI1 \ - {2412, 2472}, 1 -#define FREQ_RT_2G_FCC1 \ - {2412, 2462}, 1 -#define FREQ_RT_2G_MKK1 \ - {2412, 2484}, 1 -#define FREQ_RT_2G_ETSI2 \ - {2457, 2472}, 1 - - -// -// 5G Regulatory Domains -// -typedef enum _RT_REGULATION_DOMAIN_5G -{ - RT_5G_NULL, - RT_5G_WORLD, - RT_5G_ETSI1, - RT_5G_ETSI2, - RT_5G_ETSI3, - RT_5G_FCC1, - RT_5G_FCC2, - RT_5G_FCC3, - RT_5G_FCC4, - RT_5G_FCC5, - RT_5G_FCC6, - RT_5G_FCC7, - RT_5G_IC1, - RT_5G_KCC1, - RT_5G_MKK1, - RT_5G_MKK2, - RT_5G_MKK3, - RT_5G_NCC1, - -}RT_REGULATION_5G, *PRT_REGULATION_5G; - -// -// 5G Channel Number -// -#define CHNL_RT_5G_NULL \ - {0}, 0 -#define CHNL_RT_5G_WORLD \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 -#define CHNL_RT_5G_ETSI1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 -#define CHNL_RT_5G_ETSI2 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 -#define CHNL_RT_5G_ETSI3 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 -#define CHNL_RT_5G_FCC1 \ - {36,40,44,48,149,153,157,161,165}, 9 -#define CHNL_RT_5G_FCC2 \ - {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 -#define CHNL_RT_5G_FCC3 \ - {36,40,44,48,52,56,60,64,149,153,157,161}, 12 -#define CHNL_RT_5G_FCC4 \ - {149,153,157,161,165}, 5 -#define CHNL_RT_5G_FCC5 \ - {36,40,44,48,52,56,60,64}, 8 -#define CHNL_RT_5G_FCC6 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 -#define CHNL_RT_5G_FCC7 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 -#define CHNL_RT_5G_IC1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 -#define CHNL_RT_5G_KCC1 \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 -#define CHNL_RT_5G_MKK1 \ - {36,40,44,48,52,56,60,64}, 8 -#define CHNL_RT_5G_MKK2 \ - {100,104,108,112,116,120,124,128,132,136,140}, 11 -#define CHNL_RT_5G_MKK3 \ - {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 -#define CHNL_RT_5G_NCC1 \ - {56,60,64,149,153,157,161,165}, 8 - -// -// 5G Channel Active or passive scan. -// -#define CHNL_RT_5G_NULL_SCAN_TYPE \ - {SCAN_NULL} -#define CHNL_RT_5G_WORLD_SCAN_TYPE \ - {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1} -#define CHNL_RT_5G_ETSI1_SCAN_TYPE \ - {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1} -#define CHNL_RT_5G_ETSI2_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 -#define CHNL_RT_5G_ETSI3_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 -#define CHNL_RT_5G_FCC1_SCAN_TYPE \ - {36,40,44,48,149,153,157,161,165}, 9 -#define CHNL_RT_5G_FCC2_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 -#define CHNL_RT_5G_FCC3_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,149,153,157,161}, 12 -#define CHNL_RT_5G_FCC4_SCAN_TYPE \ - {149,153,157,161,165}, 5 -#define CHNL_RT_5G_FCC5_SCAN_TYPE \ - {36,40,44,48,52,56,60,64}, 8 -#define CHNL_RT_5G_FCC6_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 -#define CHNL_RT_5G_FCC7_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 -#define CHNL_RT_5G_IC1_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 -#define CHNL_RT_5G_KCC1_SCAN_TYPE \ - {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 -#define CHNL_RT_5G_MKK1_SCAN_TYPE \ - {36,40,44,48,52,56,60,64}, 8 -#define CHNL_RT_5G_MKK2_SCAN_TYPE \ - {100,104,108,112,116,120,124,128,132,136,140}, 11 -#define CHNL_RT_5G_MKK3_SCAN_TYPE \ - {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 -#define CHNL_RT_5G_NCC1_SCAN_TYPE \ - {56,60,64,149,153,157,161,165}, 8 - -// -// Global Regulation -// -typedef enum _RT_REGULATION_COMMON -{ - RT_WORLD, - RT_FCC, - RT_MKK, - RT_ETSI, - RT_IC, - RT_CE, - RT_NCC, - -}RT_REGULATION_CMN, *PRT_REGULATION_CMN; - - - -// -// Special requirement for different regulation domain. -// For internal test or customerize special request. -// -typedef enum _RT_CHNLPLAN_SREQ -{ - RT_SREQ_NA = 0x0, - RT_SREQ_2G_ADHOC_11N = 0x00000001, - RT_SREQ_2G_ADHOC_11B = 0x00000002, - RT_SREQ_2G_ALL_PASS = 0x00000004, - RT_SREQ_2G_ALL_ACT = 0x00000008, - RT_SREQ_5G_ADHOC_11N = 0x00000010, - RT_SREQ_5G_ADHOC_11AC = 0x00000020, - RT_SREQ_5G_ALL_PASS = 0x00000040, - RT_SREQ_5G_ALL_ACT = 0x00000080, - RT_SREQ_C1_PLAN = 0x00000100, - RT_SREQ_C2_PLAN = 0x00000200, - RT_SREQ_C3_PLAN = 0x00000400, - RT_SREQ_C4_PLAN = 0x00000800, - RT_SREQ_NFC_ON = 0x00001000, - RT_SREQ_MASK = 0x0000FFFF, /* Requirements bit mask */ - -}RT_CHNLPLAN_SREQ, *PRT_CHNLPLAN_SREQ; - - -// -// RT_COUNTRY_NAME & RT_REGULATION_2G & RT_REGULATION_5G transfer table -// -// -typedef struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE -{ - // - // Define countery domain and corresponding - // - RT_COUNTRY_NAME Country_Enum; - char Country_Name[3]; - - //char Domain_Name[12]; - RT_REGULATION_2G Domain_2G; - - RT_REGULATION_5G Domain_5G; - - RT_CHANNEL_DOMAIN RtChDomain; - //u1Byte Country_Area; - -}RT_CHNL_CTRY_TBL, *PRT_CHNL_CTRY_TBL; - - -#define RT_MAX_CHNL_NUM_2G 13 -#define RT_MAX_CHNL_NUM_5G 44 - -// Power table sample. - -typedef struct _RT_CHNL_PLAN_PWR_LIMIT -{ - u2Byte Chnl_Start; - u2Byte Chnl_end; - u1Byte dB_Max; - u2Byte mW_Max; -}RT_CHNL_PWR_LIMIT, *PRT_CHNL_PWR_LIMIT; - - -#define RT_MAX_BAND_NUM 5 - -typedef struct _RT_CHANNEL_PLAN_MAXPWR -{ -// STRING_T - RT_CHNL_PWR_LIMIT Chnl[RT_MAX_BAND_NUM]; - u1Byte Band_Useful_Num; - - -}RT_CHANNEL_PLAN_MAXPWR, *PRT_CHANNEL_PLAN_MAXPWR; - - -// -// Power By Rate Table. -// - - - -typedef struct _RT_CHANNEL_PLAN_NEW -{ - // - // Define countery domain and corresponding - // - //char Country_Name[36]; - //u1Byte Country_Enum; - - //char Domain_Name[12]; - - - PRT_CHNL_CTRY_TBL pCtryTransfer; - - RT_CHANNEL_DOMAIN RtChDomain; - - RT_REGULATION_2G Domain_2G; - - RT_REGULATION_5G Domain_5G; - - RT_REGULATION_CMN Regulator; - - RT_CHNLPLAN_SREQ ChnlSreq; - - //RT_CHNL_PLAN_LIMIT RtChnl; - - u1Byte Chnl2G[MAX_CHANNEL_NUM]; // CHNL_RT_2G_WORLD - u1Byte Len2G; - u1Byte Chnl2GScanTp[MAX_CHANNEL_NUM]; // CHNL_RT_2G_WORLD_SCAN_TYPE - //u1Byte Freq2G[2]; // FREQ_RT_2G_WORLD - - u1Byte Chnl5G[MAX_CHANNEL_NUM]; - u1Byte Len5G; - u1Byte Chnl5GScanTp[MAX_CHANNEL_NUM]; - //u1Byte Freq2G[2]; // FREQ_RT_2G_WORLD - - RT_CHANNEL_PLAN_MAXPWR ChnlMaxPwr; - - -}RT_CHANNEL_PLAN_NEW, *PRT_CHANNEL_PLAN_NEW; - - -#endif // __RT_CHANNELPLAN_H__ - - - - - diff --git a/hal/phydm/rtl8822b/halhwimg8822b_bb.c b/hal/phydm/rtl8822b/halhwimg8822b_bb.c index a23b07e..9c73696 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_bb.c +++ b/hal/phydm/rtl8822b/halhwimg8822b_bb.c @@ -1,26 +1,36 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ -/*Image2HeaderVersion: R2 1.2.1*/ +/*Image2HeaderVersion: R3 1.0*/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (RTL8822B_SUPPORT == 1) static boolean check_positive( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, const u32 condition1, const u32 condition2, const u32 condition3, @@ -29,50 +39,51 @@ check_positive( { u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; - u8 cut_version_for_para = (p_dm_odm->cut_version == ODM_CUT_A) ? 15 : p_dm_odm->cut_version; - u8 pkg_type_for_para = (p_dm_odm->package_type == 0) ? 15 : p_dm_odm->package_type; + u8 cut_version_for_para = (dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version; + u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; u32 driver1 = cut_version_for_para << 24 | - (p_dm_odm->support_interface & 0xF0) << 16 | - p_dm_odm->support_platform << 16 | + (dm->support_interface & 0xF0) << 16 | + dm->support_platform << 16 | pkg_type_for_para << 12 | - (p_dm_odm->support_interface & 0x0F) << 8 | - p_dm_odm->rfe_type; + (dm->support_interface & 0x0F) << 8 | + dm->rfe_type; - u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 | - (p_dm_odm->type_gpa & 0xFF) << 8 | - (p_dm_odm->type_alna & 0xFF) << 16 | - (p_dm_odm->type_apa & 0xFF) << 24; + u32 driver2 = (dm->type_glna & 0xFF) << 0 | + (dm->type_gpa & 0xFF) << 8 | + (dm->type_alna & 0xFF) << 16 | + (dm->type_apa & 0xFF) << 24; u32 driver3 = 0; - u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 | - (p_dm_odm->type_gpa & 0xFF00) | - (p_dm_odm->type_alna & 0xFF00) << 8 | - (p_dm_odm->type_apa & 0xFF00) << 16; + u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | + (dm->type_gpa & 0xFF00) | + (dm->type_alna & 0xFF00) << 8 | + (dm->type_apa & 0xFF00) << 16; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (RFE, Package) = (0x%X, 0x%X)\n", p_dm_odm->rfe_type, p_dm_odm->package_type)); + PHYDM_DBG(dm, ODM_COMP_INIT, + " (Platform, Interface) = (0x%X, 0x%X)\n", dm->support_platform, dm->support_interface); + PHYDM_DBG(dm, ODM_COMP_INIT, + " (RFE, Package) = (0x%X, 0x%X)\n", dm->rfe_type, dm->package_type); /*============== value Defined Check ===============*/ /*cut version [27:24] need to do value check*/ - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) return false; /*pkg type [15:12] need to do value check*/ - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) return false; + /*interface [11:8] need to do value check*/ + if (((cond1 & 0x00000F00) != 0) && ((cond1 & 0x00000F00) != (driver1 & 0x00000F00))) + return false; /*=============== Bit Defined Check ================*/ /* We don't care [31:28] */ @@ -86,7 +97,7 @@ check_positive( } static boolean check_negative( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, const u32 condition1, const u32 condition2 ) @@ -893,63 +904,63 @@ u32 array_mp_8822b_agc_tab[] = { 0x81C, 0x007E0003, 0x9000000c, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003, - 0x81C, 0xFE000003, - 0x81C, 0xFD020003, - 0x81C, 0xFC040003, - 0x81C, 0xFB060003, - 0x81C, 0xFA080003, - 0x81C, 0xF90A0003, - 0x81C, 0xF80C0003, - 0x81C, 0xF70E0003, - 0x81C, 0xF6100003, - 0x81C, 0xF5120003, - 0x81C, 0xF4140003, - 0x81C, 0xF3160003, - 0x81C, 0xF2180003, - 0x81C, 0xF11A0003, - 0x81C, 0xF01C0003, - 0x81C, 0xEF1E0003, - 0x81C, 0xEE200003, - 0x81C, 0xED220003, - 0x81C, 0xEC240003, - 0x81C, 0xEB260003, - 0x81C, 0xEA280003, - 0x81C, 0xE92A0003, - 0x81C, 0xE82C0003, - 0x81C, 0xE72E0003, - 0x81C, 0xE6300003, - 0x81C, 0xE5320003, - 0x81C, 0xC8340003, - 0x81C, 0xC7360003, - 0x81C, 0xC6380003, - 0x81C, 0xC53A0003, - 0x81C, 0xC43C0003, - 0x81C, 0xC33E0003, - 0x81C, 0xC2400003, - 0x81C, 0xC1420003, - 0x81C, 0xC0440003, - 0x81C, 0xA3460003, - 0x81C, 0xA2480003, - 0x81C, 0xA14A0003, - 0x81C, 0xA04C0003, - 0x81C, 0x824E0003, - 0x81C, 0x81500003, - 0x81C, 0x80520003, - 0x81C, 0x64540003, - 0x81C, 0x63560003, - 0x81C, 0x62580003, - 0x81C, 0x445A0003, - 0x81C, 0x435C0003, - 0x81C, 0x425E0003, - 0x81C, 0x41600003, - 0x81C, 0x40620003, - 0x81C, 0x05640003, - 0x81C, 0x04660003, - 0x81C, 0x03680003, - 0x81C, 0x026A0003, - 0x81C, 0x016C0003, - 0x81C, 0x006E0003, - 0x81C, 0x00700003, + 0x81C, 0xFD000003, + 0x81C, 0xFC020003, + 0x81C, 0xFB040003, + 0x81C, 0xFA060003, + 0x81C, 0xF9080003, + 0x81C, 0xF80A0003, + 0x81C, 0xF70C0003, + 0x81C, 0xF60E0003, + 0x81C, 0xF5100003, + 0x81C, 0xF4120003, + 0x81C, 0xF3140003, + 0x81C, 0xF2160003, + 0x81C, 0xF1180003, + 0x81C, 0xF01A0003, + 0x81C, 0xEF1C0003, + 0x81C, 0xEE1E0003, + 0x81C, 0xED200003, + 0x81C, 0xEC220003, + 0x81C, 0xEB240003, + 0x81C, 0xEA260003, + 0x81C, 0xE9280003, + 0x81C, 0xE82A0003, + 0x81C, 0xE72C0003, + 0x81C, 0xE62E0003, + 0x81C, 0xE5300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xC43A0003, + 0x81C, 0xC33C0003, + 0x81C, 0xC23E0003, + 0x81C, 0xC1400003, + 0x81C, 0xC0420003, + 0x81C, 0xA5440003, + 0x81C, 0xA4460003, + 0x81C, 0xA3480003, + 0x81C, 0xA24A0003, + 0x81C, 0xA14C0003, + 0x81C, 0x834E0003, + 0x81C, 0x82500003, + 0x81C, 0x81520003, + 0x81C, 0x80540003, + 0x81C, 0x65560003, + 0x81C, 0x64580003, + 0x81C, 0x635A0003, + 0x81C, 0x625C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x40640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, 0x81C, 0x00720003, 0x81C, 0x00740003, 0x81C, 0x00760003, @@ -1089,6 +1100,138 @@ u32 array_mp_8822b_agc_tab[] = { 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003, + 0x9000000f, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFC000003, + 0x81C, 0xFB020003, + 0x81C, 0xFA040003, + 0x81C, 0xF9060003, + 0x81C, 0xF8080003, + 0x81C, 0xF70A0003, + 0x81C, 0xF60C0003, + 0x81C, 0xF50E0003, + 0x81C, 0xF4100003, + 0x81C, 0xF3120003, + 0x81C, 0xF2140003, + 0x81C, 0xF1160003, + 0x81C, 0xF0180003, + 0x81C, 0xEF1A0003, + 0x81C, 0xEE1C0003, + 0x81C, 0xED1E0003, + 0x81C, 0xEC200003, + 0x81C, 0xEB220003, + 0x81C, 0xEA240003, + 0x81C, 0xE9260003, + 0x81C, 0xE8280003, + 0x81C, 0xE72A0003, + 0x81C, 0xE62C0003, + 0x81C, 0xE52E0003, + 0x81C, 0xC8300003, + 0x81C, 0xC7320003, + 0x81C, 0xC6340003, + 0x81C, 0xC5360003, + 0x81C, 0xC4380003, + 0x81C, 0xC33A0003, + 0x81C, 0xC23C0003, + 0x81C, 0xC13E0003, + 0x81C, 0xA4400003, + 0x81C, 0xA3420003, + 0x81C, 0xA2440003, + 0x81C, 0xA1460003, + 0x81C, 0xA0480003, + 0x81C, 0x684A0003, + 0x81C, 0x674C0003, + 0x81C, 0x664E0003, + 0x81C, 0x65500003, + 0x81C, 0x64520003, + 0x81C, 0x63540003, + 0x81C, 0x44560003, + 0x81C, 0x43580003, + 0x81C, 0x425A0003, + 0x81C, 0x415C0003, + 0x81C, 0x405E0003, + 0x81C, 0x23600003, + 0x81C, 0x22620003, + 0x81C, 0x21640003, + 0x81C, 0x03660003, + 0x81C, 0x02680003, + 0x81C, 0x016A0003, + 0x81C, 0x006C0003, + 0x81C, 0x006E0003, + 0x81C, 0x00700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000003, + 0x81C, 0xFD000003, + 0x81C, 0xFC020003, + 0x81C, 0xFB040003, + 0x81C, 0xFA060003, + 0x81C, 0xF9080003, + 0x81C, 0xF80A0003, + 0x81C, 0xF70C0003, + 0x81C, 0xF60E0003, + 0x81C, 0xF5100003, + 0x81C, 0xF4120003, + 0x81C, 0xF3140003, + 0x81C, 0xF2160003, + 0x81C, 0xF1180003, + 0x81C, 0xF01A0003, + 0x81C, 0xEF1C0003, + 0x81C, 0xEE1E0003, + 0x81C, 0xED200003, + 0x81C, 0xEC220003, + 0x81C, 0xEB240003, + 0x81C, 0xEA260003, + 0x81C, 0xE9280003, + 0x81C, 0xE82A0003, + 0x81C, 0xE72C0003, + 0x81C, 0xE62E0003, + 0x81C, 0xE5300003, + 0x81C, 0xC8320003, + 0x81C, 0xC7340003, + 0x81C, 0xC6360003, + 0x81C, 0xC5380003, + 0x81C, 0xC43A0003, + 0x81C, 0xC33C0003, + 0x81C, 0xC23E0003, + 0x81C, 0xC1400003, + 0x81C, 0xC0420003, + 0x81C, 0xA5440003, + 0x81C, 0xA4460003, + 0x81C, 0xA3480003, + 0x81C, 0xA24A0003, + 0x81C, 0xA14C0003, + 0x81C, 0x834E0003, + 0x81C, 0x82500003, + 0x81C, 0x81520003, + 0x81C, 0x80540003, + 0x81C, 0x65560003, + 0x81C, 0x64580003, + 0x81C, 0x635A0003, + 0x81C, 0x625C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x40640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, + 0x81C, 0x00720003, + 0x81C, 0x00740003, + 0x81C, 0x00760003, + 0x81C, 0x00780003, + 0x81C, 0x007A0003, + 0x81C, 0x007C0003, + 0x81C, 0x007E0003, 0xA0000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xFE000003, @@ -1937,68 +2080,68 @@ u32 array_mp_8822b_agc_tab[] = { 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x9000000c, 0x00000000, 0x40000000, 0x00000000, - 0x81C, 0xFD000103, - 0x81C, 0xFC020103, - 0x81C, 0xFB040103, - 0x81C, 0xFA060103, - 0x81C, 0xF9080103, - 0x81C, 0xF80A0103, - 0x81C, 0xF70C0103, - 0x81C, 0xF60E0103, - 0x81C, 0xF5100103, - 0x81C, 0xF4120103, - 0x81C, 0xF3140103, - 0x81C, 0xF2160103, - 0x81C, 0xF1180103, - 0x81C, 0xF01A0103, - 0x81C, 0xEE1C0103, - 0x81C, 0xED1E0103, - 0x81C, 0xEC200103, - 0x81C, 0xEB220103, - 0x81C, 0xEA240103, - 0x81C, 0xE9260103, - 0x81C, 0xE8280103, - 0x81C, 0xE72A0103, - 0x81C, 0xE62C0103, - 0x81C, 0xE52E0103, - 0x81C, 0xE4300103, - 0x81C, 0xE3320103, - 0x81C, 0xE2340103, - 0x81C, 0xC5360103, - 0x81C, 0xC4380103, - 0x81C, 0xC33A0103, - 0x81C, 0xC23C0103, - 0x81C, 0xA53E0103, - 0x81C, 0xA4400103, - 0x81C, 0xA3420103, - 0x81C, 0xA2440103, - 0x81C, 0xA1460103, - 0x81C, 0x83480103, - 0x81C, 0x824A0103, - 0x81C, 0x814C0103, - 0x81C, 0x804E0103, - 0x81C, 0x63500103, - 0x81C, 0x62520103, - 0x81C, 0x61540103, - 0x81C, 0x43560103, - 0x81C, 0x42580103, - 0x81C, 0x415A0103, - 0x81C, 0x405C0103, - 0x81C, 0x225E0103, - 0x81C, 0x21600103, - 0x81C, 0x20620103, - 0x81C, 0x03640103, - 0x81C, 0x02660103, - 0x81C, 0x01680103, - 0x81C, 0x006A0103, - 0x81C, 0x006C0103, - 0x81C, 0x006E0103, - 0x81C, 0x00700103, - 0x81C, 0x00720103, - 0x81C, 0x00740103, - 0x81C, 0x00760103, - 0x81C, 0x00780103, - 0x81C, 0x007A0103, + 0x81C, 0xFE000103, + 0x81C, 0xFD020103, + 0x81C, 0xFC040103, + 0x81C, 0xFB060103, + 0x81C, 0xFA080103, + 0x81C, 0xF90A0103, + 0x81C, 0xF80C0103, + 0x81C, 0xF70E0103, + 0x81C, 0xF6100103, + 0x81C, 0xF5120103, + 0x81C, 0xF4140103, + 0x81C, 0xF3160103, + 0x81C, 0xF2180103, + 0x81C, 0xF11A0103, + 0x81C, 0xF01C0103, + 0x81C, 0xEF1E0103, + 0x81C, 0xEE200103, + 0x81C, 0xED220103, + 0x81C, 0xEC240103, + 0x81C, 0xEB260103, + 0x81C, 0xEA280103, + 0x81C, 0xE92A0103, + 0x81C, 0xE82C0103, + 0x81C, 0xE72E0103, + 0x81C, 0xE6300103, + 0x81C, 0xE5320103, + 0x81C, 0xE4340103, + 0x81C, 0xE3360103, + 0x81C, 0xC6380103, + 0x81C, 0xC53A0103, + 0x81C, 0xC43C0103, + 0x81C, 0xC33E0103, + 0x81C, 0xA5400103, + 0x81C, 0xA4420103, + 0x81C, 0xA3440103, + 0x81C, 0xA2460103, + 0x81C, 0xA1480103, + 0x81C, 0xA04A0103, + 0x81C, 0x824C0103, + 0x81C, 0x814E0103, + 0x81C, 0x80500103, + 0x81C, 0x64520103, + 0x81C, 0x63540103, + 0x81C, 0x62560103, + 0x81C, 0x61580103, + 0x81C, 0x605A0103, + 0x81C, 0x235C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x9000000d, 0x00000000, 0x40000000, 0x00000000, @@ -2131,6 +2274,136 @@ u32 array_mp_8822b_agc_tab[] = { 0x81C, 0x007A0103, 0x81C, 0x007C0103, 0x81C, 0x007E0103, + 0x9000000f, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000103, + 0x81C, 0xFB020103, + 0x81C, 0xFA040103, + 0x81C, 0xF9060103, + 0x81C, 0xF8080103, + 0x81C, 0xF70A0103, + 0x81C, 0xF60C0103, + 0x81C, 0xF50E0103, + 0x81C, 0xF4100103, + 0x81C, 0xF3120103, + 0x81C, 0xF2140103, + 0x81C, 0xF1160103, + 0x81C, 0xF0180103, + 0x81C, 0xEF1A0103, + 0x81C, 0xEE1C0103, + 0x81C, 0xED1E0103, + 0x81C, 0xEC200103, + 0x81C, 0xEB220103, + 0x81C, 0xEA240103, + 0x81C, 0xE9260103, + 0x81C, 0xE8280103, + 0x81C, 0xE72A0103, + 0x81C, 0xE62C0103, + 0x81C, 0xE52E0103, + 0x81C, 0xE4300103, + 0x81C, 0xE3320103, + 0x81C, 0xE2340103, + 0x81C, 0xE1360103, + 0x81C, 0xC3380103, + 0x81C, 0xC23A0103, + 0x81C, 0xC13C0103, + 0x81C, 0xC03E0103, + 0x81C, 0xA4400103, + 0x81C, 0xA3420103, + 0x81C, 0xA2440103, + 0x81C, 0xA1460103, + 0x81C, 0x82480103, + 0x81C, 0x814A0103, + 0x81C, 0x804C0103, + 0x81C, 0x634E0103, + 0x81C, 0x62500103, + 0x81C, 0x61520103, + 0x81C, 0x42540103, + 0x81C, 0x41560103, + 0x81C, 0x24580103, + 0x81C, 0x235A0103, + 0x81C, 0x225C0103, + 0x81C, 0x215E0103, + 0x81C, 0x20600103, + 0x81C, 0x03620103, + 0x81C, 0x02640103, + 0x81C, 0x01660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000103, + 0x81C, 0xFD020103, + 0x81C, 0xFC040103, + 0x81C, 0xFB060103, + 0x81C, 0xFA080103, + 0x81C, 0xF90A0103, + 0x81C, 0xF80C0103, + 0x81C, 0xF70E0103, + 0x81C, 0xF6100103, + 0x81C, 0xF5120103, + 0x81C, 0xF4140103, + 0x81C, 0xF3160103, + 0x81C, 0xF2180103, + 0x81C, 0xF11A0103, + 0x81C, 0xF01C0103, + 0x81C, 0xEF1E0103, + 0x81C, 0xEE200103, + 0x81C, 0xED220103, + 0x81C, 0xEC240103, + 0x81C, 0xEB260103, + 0x81C, 0xEA280103, + 0x81C, 0xE92A0103, + 0x81C, 0xE82C0103, + 0x81C, 0xE72E0103, + 0x81C, 0xE6300103, + 0x81C, 0xE5320103, + 0x81C, 0xE4340103, + 0x81C, 0xE3360103, + 0x81C, 0xC6380103, + 0x81C, 0xC53A0103, + 0x81C, 0xC43C0103, + 0x81C, 0xC33E0103, + 0x81C, 0xA5400103, + 0x81C, 0xA4420103, + 0x81C, 0xA3440103, + 0x81C, 0xA2460103, + 0x81C, 0xA1480103, + 0x81C, 0xA04A0103, + 0x81C, 0x824C0103, + 0x81C, 0x814E0103, + 0x81C, 0x80500103, + 0x81C, 0x64520103, + 0x81C, 0x63540103, + 0x81C, 0x62560103, + 0x81C, 0x61580103, + 0x81C, 0x605A0103, + 0x81C, 0x235C0103, + 0x81C, 0x225E0103, + 0x81C, 0x21600103, + 0x81C, 0x20620103, + 0x81C, 0x03640103, + 0x81C, 0x02660103, + 0x81C, 0x01680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, 0xA0000000, 0x00000000, 0x81C, 0xFE000103, 0x81C, 0xFD020103, @@ -2991,46 +3264,46 @@ u32 array_mp_8822b_agc_tab[] = { 0x81C, 0xF2140203, 0x81C, 0xF1160203, 0x81C, 0xF0180203, - 0x81C, 0xEE1A0203, - 0x81C, 0xED1C0203, - 0x81C, 0xEC1E0203, - 0x81C, 0xEB200203, - 0x81C, 0xEA220203, - 0x81C, 0xE9240203, - 0x81C, 0xE8260203, - 0x81C, 0xE7280203, - 0x81C, 0xE62A0203, - 0x81C, 0xE52C0203, - 0x81C, 0xE42E0203, - 0x81C, 0xE3300203, - 0x81C, 0xE2320203, - 0x81C, 0xC6340203, - 0x81C, 0xC5360203, - 0x81C, 0xC4380203, - 0x81C, 0xC33A0203, - 0x81C, 0xA63C0203, - 0x81C, 0xA53E0203, - 0x81C, 0xA4400203, - 0x81C, 0xA3420203, - 0x81C, 0xA2440203, - 0x81C, 0xA1460203, - 0x81C, 0x83480203, - 0x81C, 0x824A0203, - 0x81C, 0x814C0203, - 0x81C, 0x804E0203, - 0x81C, 0x63500203, - 0x81C, 0x62520203, - 0x81C, 0x61540203, - 0x81C, 0x42560203, - 0x81C, 0x41580203, + 0x81C, 0xEF1A0203, + 0x81C, 0xEE1C0203, + 0x81C, 0xED1E0203, + 0x81C, 0xEC200203, + 0x81C, 0xEB220203, + 0x81C, 0xEA240203, + 0x81C, 0xE9260203, + 0x81C, 0xE8280203, + 0x81C, 0xE72A0203, + 0x81C, 0xE62C0203, + 0x81C, 0xE52E0203, + 0x81C, 0xE4300203, + 0x81C, 0xE3320203, + 0x81C, 0xE2340203, + 0x81C, 0xC6360203, + 0x81C, 0xC5380203, + 0x81C, 0xC43A0203, + 0x81C, 0xC33C0203, + 0x81C, 0xA63E0203, + 0x81C, 0xA5400203, + 0x81C, 0xA4420203, + 0x81C, 0xA3440203, + 0x81C, 0xA2460203, + 0x81C, 0xA1480203, + 0x81C, 0x834A0203, + 0x81C, 0x824C0203, + 0x81C, 0x814E0203, + 0x81C, 0x64500203, + 0x81C, 0x63520203, + 0x81C, 0x62540203, + 0x81C, 0x61560203, + 0x81C, 0x60580203, 0x81C, 0x405A0203, - 0x81C, 0x225C0203, - 0x81C, 0x215E0203, - 0x81C, 0x20600203, - 0x81C, 0x04620203, - 0x81C, 0x03640203, - 0x81C, 0x02660203, - 0x81C, 0x01680203, + 0x81C, 0x215C0203, + 0x81C, 0x205E0203, + 0x81C, 0x03600203, + 0x81C, 0x02620203, + 0x81C, 0x01640203, + 0x81C, 0x00660203, + 0x81C, 0x00680203, 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203, @@ -3172,29 +3445,159 @@ u32 array_mp_8822b_agc_tab[] = { 0x81C, 0x007A0203, 0x81C, 0x007C0203, 0x81C, 0x007E0203, - 0xA0000000, 0x00000000, - 0x81C, 0xFD000203, - 0x81C, 0xFC020203, - 0x81C, 0xFB040203, - 0x81C, 0xFA060203, - 0x81C, 0xF9080203, - 0x81C, 0xF80A0203, - 0x81C, 0xF70C0203, - 0x81C, 0xF60E0203, - 0x81C, 0xF5100203, - 0x81C, 0xF4120203, - 0x81C, 0xF3140203, - 0x81C, 0xF2160203, - 0x81C, 0xF1180203, - 0x81C, 0xF01A0203, - 0x81C, 0xEF1C0203, - 0x81C, 0xEE1E0203, - 0x81C, 0xED200203, - 0x81C, 0xEC220203, - 0x81C, 0xEB240203, - 0x81C, 0xEA260203, - 0x81C, 0xE9280203, - 0x81C, 0xE82A0203, + 0x9000000f, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000203, + 0x81C, 0xFB020203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEF1A0203, + 0x81C, 0xEE1C0203, + 0x81C, 0xED1E0203, + 0x81C, 0xEC200203, + 0x81C, 0xEB220203, + 0x81C, 0xEA240203, + 0x81C, 0xE9260203, + 0x81C, 0xE8280203, + 0x81C, 0xE72A0203, + 0x81C, 0xE62C0203, + 0x81C, 0xE52E0203, + 0x81C, 0xE4300203, + 0x81C, 0xE3320203, + 0x81C, 0xE2340203, + 0x81C, 0xE1360203, + 0x81C, 0xE0380203, + 0x81C, 0xC33A0203, + 0x81C, 0xC23C0203, + 0x81C, 0xC13E0203, + 0x81C, 0xA3400203, + 0x81C, 0xA2420203, + 0x81C, 0xA1440203, + 0x81C, 0xA0460203, + 0x81C, 0x83480203, + 0x81C, 0x824A0203, + 0x81C, 0x814C0203, + 0x81C, 0x644E0203, + 0x81C, 0x63500203, + 0x81C, 0x62520203, + 0x81C, 0x61540203, + 0x81C, 0x42560203, + 0x81C, 0x41580203, + 0x81C, 0x235A0203, + 0x81C, 0x225C0203, + 0x81C, 0x215E0203, + 0x81C, 0x04600203, + 0x81C, 0x03620203, + 0x81C, 0x02640203, + 0x81C, 0x01660203, + 0x81C, 0x00680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000203, + 0x81C, 0xFB020203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEF1A0203, + 0x81C, 0xEE1C0203, + 0x81C, 0xED1E0203, + 0x81C, 0xEC200203, + 0x81C, 0xEB220203, + 0x81C, 0xEA240203, + 0x81C, 0xE9260203, + 0x81C, 0xE8280203, + 0x81C, 0xE72A0203, + 0x81C, 0xE62C0203, + 0x81C, 0xE52E0203, + 0x81C, 0xE4300203, + 0x81C, 0xE3320203, + 0x81C, 0xE2340203, + 0x81C, 0xC6360203, + 0x81C, 0xC5380203, + 0x81C, 0xC43A0203, + 0x81C, 0xC33C0203, + 0x81C, 0xA63E0203, + 0x81C, 0xA5400203, + 0x81C, 0xA4420203, + 0x81C, 0xA3440203, + 0x81C, 0xA2460203, + 0x81C, 0xA1480203, + 0x81C, 0x834A0203, + 0x81C, 0x824C0203, + 0x81C, 0x814E0203, + 0x81C, 0x64500203, + 0x81C, 0x63520203, + 0x81C, 0x62540203, + 0x81C, 0x61560203, + 0x81C, 0x60580203, + 0x81C, 0x405A0203, + 0x81C, 0x215C0203, + 0x81C, 0x205E0203, + 0x81C, 0x03600203, + 0x81C, 0x02620203, + 0x81C, 0x01640203, + 0x81C, 0x00660203, + 0x81C, 0x00680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, + 0xA0000000, 0x00000000, + 0x81C, 0xFD000203, + 0x81C, 0xFC020203, + 0x81C, 0xFB040203, + 0x81C, 0xFA060203, + 0x81C, 0xF9080203, + 0x81C, 0xF80A0203, + 0x81C, 0xF70C0203, + 0x81C, 0xF60E0203, + 0x81C, 0xF5100203, + 0x81C, 0xF4120203, + 0x81C, 0xF3140203, + 0x81C, 0xF2160203, + 0x81C, 0xF1180203, + 0x81C, 0xF01A0203, + 0x81C, 0xEF1C0203, + 0x81C, 0xEE1E0203, + 0x81C, 0xED200203, + 0x81C, 0xEC220203, + 0x81C, 0xEB240203, + 0x81C, 0xEA260203, + 0x81C, 0xE9280203, + 0x81C, 0xE82A0203, 0x81C, 0xE72C0203, 0x81C, 0xE62E0203, 0x81C, 0xE5300203, @@ -4031,47 +4434,47 @@ u32 array_mp_8822b_agc_tab[] = { 0x81C, 0xF3120303, 0x81C, 0xF2140303, 0x81C, 0xF1160303, - 0x81C, 0xEF180303, - 0x81C, 0xEE1A0303, - 0x81C, 0xED1C0303, - 0x81C, 0xEC1E0303, - 0x81C, 0xEB200303, - 0x81C, 0xEA220303, - 0x81C, 0xE9240303, - 0x81C, 0xE8260303, - 0x81C, 0xE7280303, - 0x81C, 0xE62A0303, - 0x81C, 0xE52C0303, - 0x81C, 0xE42E0303, - 0x81C, 0xE3300303, - 0x81C, 0xE2320303, - 0x81C, 0xC6340303, - 0x81C, 0xC5360303, - 0x81C, 0xC4380303, - 0x81C, 0xC33A0303, - 0x81C, 0xA63C0303, - 0x81C, 0xA53E0303, - 0x81C, 0xA4400303, - 0x81C, 0xA3420303, - 0x81C, 0xA2440303, - 0x81C, 0xA1460303, - 0x81C, 0x83480303, - 0x81C, 0x824A0303, - 0x81C, 0x814C0303, - 0x81C, 0x804E0303, - 0x81C, 0x63500303, - 0x81C, 0x62520303, - 0x81C, 0x61540303, - 0x81C, 0x42560303, - 0x81C, 0x41580303, - 0x81C, 0x405A0303, - 0x81C, 0x225C0303, - 0x81C, 0x215E0303, - 0x81C, 0x20600303, - 0x81C, 0x04620303, - 0x81C, 0x03640303, - 0x81C, 0x02660303, - 0x81C, 0x01680303, + 0x81C, 0xF0180303, + 0x81C, 0xEF1A0303, + 0x81C, 0xEE1C0303, + 0x81C, 0xED1E0303, + 0x81C, 0xEC200303, + 0x81C, 0xEB220303, + 0x81C, 0xEA240303, + 0x81C, 0xE9260303, + 0x81C, 0xE8280303, + 0x81C, 0xE72A0303, + 0x81C, 0xE62C0303, + 0x81C, 0xE52E0303, + 0x81C, 0xE4300303, + 0x81C, 0xE3320303, + 0x81C, 0xE2340303, + 0x81C, 0xC6360303, + 0x81C, 0xC5380303, + 0x81C, 0xC43A0303, + 0x81C, 0xC33C0303, + 0x81C, 0xA63E0303, + 0x81C, 0xA5400303, + 0x81C, 0xA4420303, + 0x81C, 0xA3440303, + 0x81C, 0xA2460303, + 0x81C, 0x84480303, + 0x81C, 0x834A0303, + 0x81C, 0x824C0303, + 0x81C, 0x814E0303, + 0x81C, 0x80500303, + 0x81C, 0x63520303, + 0x81C, 0x62540303, + 0x81C, 0x61560303, + 0x81C, 0x60580303, + 0x81C, 0x225A0303, + 0x81C, 0x055C0303, + 0x81C, 0x045E0303, + 0x81C, 0x03600303, + 0x81C, 0x02620303, + 0x81C, 0x01640303, + 0x81C, 0x00660303, + 0x81C, 0x00680303, 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303, @@ -4213,36 +4616,166 @@ u32 array_mp_8822b_agc_tab[] = { 0x81C, 0x007A0303, 0x81C, 0x007C0303, 0x81C, 0x007E0303, - 0xA0000000, 0x00000000, - 0x81C, 0xFC000303, - 0x81C, 0xFB020303, - 0x81C, 0xFA040303, - 0x81C, 0xF9060303, - 0x81C, 0xF8080303, - 0x81C, 0xF70A0303, - 0x81C, 0xF60C0303, - 0x81C, 0xF50E0303, - 0x81C, 0xF4100303, - 0x81C, 0xF3120303, - 0x81C, 0xF2140303, - 0x81C, 0xF1160303, - 0x81C, 0xF0180303, - 0x81C, 0xEF1A0303, - 0x81C, 0xEE1C0303, - 0x81C, 0xED1E0303, - 0x81C, 0xEC200303, - 0x81C, 0xEB220303, - 0x81C, 0xEA240303, - 0x81C, 0xE9260303, - 0x81C, 0xE8280303, - 0x81C, 0xE72A0303, - 0x81C, 0xE62C0303, - 0x81C, 0xE52E0303, - 0x81C, 0xE4300303, - 0x81C, 0xE3320303, - 0x81C, 0xE2340303, - 0x81C, 0xC6360303, - 0x81C, 0xC5380303, + 0x9000000f, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000303, + 0x81C, 0xFA020303, + 0x81C, 0xF9040303, + 0x81C, 0xF8060303, + 0x81C, 0xF7080303, + 0x81C, 0xF60A0303, + 0x81C, 0xF50C0303, + 0x81C, 0xF40E0303, + 0x81C, 0xF3100303, + 0x81C, 0xF2120303, + 0x81C, 0xF1140303, + 0x81C, 0xF0160303, + 0x81C, 0xEF180303, + 0x81C, 0xEE1A0303, + 0x81C, 0xED1C0303, + 0x81C, 0xEC1E0303, + 0x81C, 0xEB200303, + 0x81C, 0xEA220303, + 0x81C, 0xE9240303, + 0x81C, 0xE8260303, + 0x81C, 0xE7280303, + 0x81C, 0xE62A0303, + 0x81C, 0xE52C0303, + 0x81C, 0xE42E0303, + 0x81C, 0xE3300303, + 0x81C, 0xE2320303, + 0x81C, 0xE1340303, + 0x81C, 0xE0360303, + 0x81C, 0xC3380303, + 0x81C, 0xC23A0303, + 0x81C, 0xC13C0303, + 0x81C, 0xC03E0303, + 0x81C, 0xA3400303, + 0x81C, 0xA2420303, + 0x81C, 0xA1440303, + 0x81C, 0xA0460303, + 0x81C, 0x83480303, + 0x81C, 0x824A0303, + 0x81C, 0x814C0303, + 0x81C, 0x644E0303, + 0x81C, 0x63500303, + 0x81C, 0x62520303, + 0x81C, 0x61540303, + 0x81C, 0x24560303, + 0x81C, 0x23580303, + 0x81C, 0x225A0303, + 0x81C, 0x215C0303, + 0x81C, 0x055E0303, + 0x81C, 0x04600303, + 0x81C, 0x03620303, + 0x81C, 0x02640303, + 0x81C, 0x01660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000303, + 0x81C, 0xFB020303, + 0x81C, 0xFA040303, + 0x81C, 0xF9060303, + 0x81C, 0xF8080303, + 0x81C, 0xF70A0303, + 0x81C, 0xF60C0303, + 0x81C, 0xF50E0303, + 0x81C, 0xF4100303, + 0x81C, 0xF3120303, + 0x81C, 0xF2140303, + 0x81C, 0xF1160303, + 0x81C, 0xF0180303, + 0x81C, 0xEF1A0303, + 0x81C, 0xEE1C0303, + 0x81C, 0xED1E0303, + 0x81C, 0xEC200303, + 0x81C, 0xEB220303, + 0x81C, 0xEA240303, + 0x81C, 0xE9260303, + 0x81C, 0xE8280303, + 0x81C, 0xE72A0303, + 0x81C, 0xE62C0303, + 0x81C, 0xE52E0303, + 0x81C, 0xE4300303, + 0x81C, 0xE3320303, + 0x81C, 0xE2340303, + 0x81C, 0xC6360303, + 0x81C, 0xC5380303, + 0x81C, 0xC43A0303, + 0x81C, 0xC33C0303, + 0x81C, 0xA63E0303, + 0x81C, 0xA5400303, + 0x81C, 0xA4420303, + 0x81C, 0xA3440303, + 0x81C, 0xA2460303, + 0x81C, 0x84480303, + 0x81C, 0x834A0303, + 0x81C, 0x824C0303, + 0x81C, 0x814E0303, + 0x81C, 0x80500303, + 0x81C, 0x63520303, + 0x81C, 0x62540303, + 0x81C, 0x61560303, + 0x81C, 0x60580303, + 0x81C, 0x225A0303, + 0x81C, 0x055C0303, + 0x81C, 0x045E0303, + 0x81C, 0x03600303, + 0x81C, 0x02620303, + 0x81C, 0x01640303, + 0x81C, 0x00660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, + 0xA0000000, 0x00000000, + 0x81C, 0xFC000303, + 0x81C, 0xFB020303, + 0x81C, 0xFA040303, + 0x81C, 0xF9060303, + 0x81C, 0xF8080303, + 0x81C, 0xF70A0303, + 0x81C, 0xF60C0303, + 0x81C, 0xF50E0303, + 0x81C, 0xF4100303, + 0x81C, 0xF3120303, + 0x81C, 0xF2140303, + 0x81C, 0xF1160303, + 0x81C, 0xF0180303, + 0x81C, 0xEF1A0303, + 0x81C, 0xEE1C0303, + 0x81C, 0xED1E0303, + 0x81C, 0xEC200303, + 0x81C, 0xEB220303, + 0x81C, 0xEA240303, + 0x81C, 0xE9260303, + 0x81C, 0xE8280303, + 0x81C, 0xE72A0303, + 0x81C, 0xE62C0303, + 0x81C, 0xE52E0303, + 0x81C, 0xE4300303, + 0x81C, 0xE3320303, + 0x81C, 0xE2340303, + 0x81C, 0xC6360303, + 0x81C, 0xC5380303, 0x81C, 0xC43A0303, 0x81C, 0xC33C0303, 0x81C, 0xA63E0303, @@ -5269,7 +5802,73 @@ u32 array_mp_8822b_agc_tab[] = { 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403, - 0xA0000000, 0x00000000, + 0x9000000f, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xFF000403, 0x81C, 0xFF020403, @@ -5335,68 +5934,3701 @@ u32 array_mp_8822b_agc_tab[] = { 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403, - 0xB0000000, 0x00000000, - 0x80000000, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00000022, - 0xC50, 0x00000020, - 0xE50, 0x00000022, - 0xE50, 0x00000020, - 0x9000000d, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00000022, - 0xC50, 0x00000020, - 0xE50, 0x00000022, - 0xE50, 0x00000020, - 0x9000000e, 0x00000000, 0x40000000, 0x00000000, - 0xC50, 0x00000022, - 0xC50, 0x00000020, - 0xE50, 0x00000022, - 0xE50, 0x00000020, 0xA0000000, 0x00000000, - 0xC50, 0x00000022, - 0xC50, 0x00000020, - 0xE50, 0x00000022, - 0xE50, 0x00000020, - 0xB0000000, 0x00000000, - -}; - -void -odm_read_and_config_mp_8822b_agc_tab( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - u32 i = 0; - u8 c_cond; - boolean is_matched = true, is_skipped = false; - u32 array_len = sizeof(array_mp_8822b_agc_tab)/sizeof(u32); - u32 *array = array_mp_8822b_agc_tab; - - u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_agc_tab\n")); - - while ((i + 1) < array_len) { - v1 = array[i]; - v2 = array[i + 1]; - - if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ - if (v1 & BIT(31)) {/* positive condition*/ - c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); - if (c_cond == COND_ENDIF) {/*end*/ - is_matched = true; - is_skipped = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + 0x81C, 0xFF000403, + 0x81C, 0xFF000403, + 0x81C, 0xFF020403, + 0x81C, 0xFE040403, + 0x81C, 0xFD060403, + 0x81C, 0xFC080403, + 0x81C, 0xFB0A0403, + 0x81C, 0xFA0C0403, + 0x81C, 0xF90E0403, + 0x81C, 0xF8100403, + 0x81C, 0xF7120403, + 0x81C, 0xF6140403, + 0x81C, 0xF5160403, + 0x81C, 0xF4180403, + 0x81C, 0xF31A0403, + 0x81C, 0xF21C0403, + 0x81C, 0xD51E0403, + 0x81C, 0xD4200403, + 0x81C, 0xD3220403, + 0x81C, 0xD2240403, + 0x81C, 0xB6260403, + 0x81C, 0xB5280403, + 0x81C, 0xB42A0403, + 0x81C, 0xB32C0403, + 0x81C, 0xB22E0403, + 0x81C, 0xB1300403, + 0x81C, 0xB0320403, + 0x81C, 0xAF340403, + 0x81C, 0xAE360403, + 0x81C, 0xAD380403, + 0x81C, 0xAC3A0403, + 0x81C, 0xAB3C0403, + 0x81C, 0xAA3E0403, + 0x81C, 0xA9400403, + 0x81C, 0xA8420403, + 0x81C, 0xA7440403, + 0x81C, 0xA6460403, + 0x81C, 0xA5480403, + 0x81C, 0xA44A0403, + 0x81C, 0xA34C0403, + 0x81C, 0x854E0403, + 0x81C, 0x84500403, + 0x81C, 0x83520403, + 0x81C, 0x82540403, + 0x81C, 0x81560403, + 0x81C, 0x80580403, + 0x81C, 0x485A0403, + 0x81C, 0x475C0403, + 0x81C, 0x465E0403, + 0x81C, 0x45600403, + 0x81C, 0x44620403, + 0x81C, 0x0A640403, + 0x81C, 0x09660403, + 0x81C, 0x08680403, + 0x81C, 0x076A0403, + 0x81C, 0x066C0403, + 0x81C, 0x056E0403, + 0x81C, 0x04700403, + 0x81C, 0x03720403, + 0x81C, 0x02740403, + 0x81C, 0x01760403, + 0x81C, 0x00780403, + 0x81C, 0x007A0403, + 0x81C, 0x007C0403, + 0x81C, 0x007E0403, + 0xB0000000, 0x00000000, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000503, + 0x81C, 0xFC020503, + 0x81C, 0xFB040503, + 0x81C, 0xFA060503, + 0x81C, 0xF9080503, + 0x81C, 0xF80A0503, + 0x81C, 0xF70C0503, + 0x81C, 0xF60E0503, + 0x81C, 0xF5100503, + 0x81C, 0xF4120503, + 0x81C, 0xF3140503, + 0x81C, 0xF2160503, + 0x81C, 0xF1180503, + 0x81C, 0xF01A0503, + 0x81C, 0xEE1C0503, + 0x81C, 0xED1E0503, + 0x81C, 0xEC200503, + 0x81C, 0xEB220503, + 0x81C, 0xEA240503, + 0x81C, 0xE9260503, + 0x81C, 0xE8280503, + 0x81C, 0xE72A0503, + 0x81C, 0xE62C0503, + 0x81C, 0xE52E0503, + 0x81C, 0xE4300503, + 0x81C, 0xE3320503, + 0x81C, 0xE2340503, + 0x81C, 0xC5360503, + 0x81C, 0xC4380503, + 0x81C, 0xC33A0503, + 0x81C, 0xC23C0503, + 0x81C, 0xA53E0503, + 0x81C, 0xA4400503, + 0x81C, 0xA3420503, + 0x81C, 0xA2440503, + 0x81C, 0xA1460503, + 0x81C, 0x83480503, + 0x81C, 0x824A0503, + 0x81C, 0x814C0503, + 0x81C, 0x804E0503, + 0x81C, 0x63500503, + 0x81C, 0x62520503, + 0x81C, 0x61540503, + 0x81C, 0x43560503, + 0x81C, 0x42580503, + 0x81C, 0x415A0503, + 0x81C, 0x405C0503, + 0x81C, 0x225E0503, + 0x81C, 0x21600503, + 0x81C, 0x20620503, + 0x81C, 0x03640503, + 0x81C, 0x02660503, + 0x81C, 0x01680503, + 0x81C, 0x006A0503, + 0x81C, 0x006C0503, + 0x81C, 0x006E0503, + 0x81C, 0x00700503, + 0x81C, 0x00720503, + 0x81C, 0x00740503, + 0x81C, 0x00760503, + 0x81C, 0x00780503, + 0x81C, 0x007A0503, + 0x81C, 0x007C0503, + 0x81C, 0x007E0503, + 0x81C, 0x007E0503, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xBE000503, + 0x81C, 0xBD020503, + 0x81C, 0xBC040503, + 0x81C, 0xBB060503, + 0x81C, 0xBA080503, + 0x81C, 0xB90A0503, + 0x81C, 0xB80C0503, + 0x81C, 0xB70E0503, + 0x81C, 0xB6100503, + 0x81C, 0xB5120503, + 0x81C, 0xB4140503, + 0x81C, 0xB3160503, + 0x81C, 0xB2180503, + 0x81C, 0xB11A0503, + 0x81C, 0xB01C0503, + 0x81C, 0xAF1E0503, + 0x81C, 0xAE200503, + 0x81C, 0xAD220503, + 0x81C, 0xAC240503, + 0x81C, 0xAB260503, + 0x81C, 0x8D280503, + 0x81C, 0x8C2A0503, + 0x81C, 0x8B2C0503, + 0x81C, 0x8A2E0503, + 0x81C, 0x89300503, + 0x81C, 0x88320503, + 0x81C, 0x6A340503, + 0x81C, 0x69360503, + 0x81C, 0x68380503, + 0x81C, 0x673A0503, + 0x81C, 0x663C0503, + 0x81C, 0x653E0503, + 0x81C, 0x64400503, + 0x81C, 0x63420503, + 0x81C, 0x62440503, + 0x81C, 0x61460503, + 0x81C, 0x60480503, + 0x81C, 0x424A0503, + 0x81C, 0x414C0503, + 0x81C, 0x404E0503, + 0x81C, 0x06500503, + 0x81C, 0x05520503, + 0x81C, 0x04540503, + 0x81C, 0x03560503, + 0x81C, 0x02580503, + 0x81C, 0x015A0503, + 0x81C, 0x005C0503, + 0x81C, 0x005E0503, + 0x81C, 0x00600503, + 0x81C, 0x00620503, + 0x81C, 0x00640503, + 0x81C, 0x00660503, + 0x81C, 0x00680503, + 0x81C, 0x006A0503, + 0x81C, 0x006C0503, + 0x81C, 0x006E0503, + 0x81C, 0x00700503, + 0x81C, 0x00720503, + 0x81C, 0x00740503, + 0x81C, 0x00760503, + 0x81C, 0x00780503, + 0x81C, 0x007A0503, + 0x81C, 0x007C0503, + 0x81C, 0x007E0503, + 0x81C, 0x007C0503, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000503, + 0x81C, 0xF7020503, + 0x81C, 0xF6040503, + 0x81C, 0xF5060503, + 0x81C, 0xF4080503, + 0x81C, 0xF30A0503, + 0x81C, 0xF20C0503, + 0x81C, 0xF10E0503, + 0x81C, 0xF0100503, + 0x81C, 0xEF120503, + 0x81C, 0xEE140503, + 0x81C, 0xED160503, + 0x81C, 0xEC180503, + 0x81C, 0xEB1A0503, + 0x81C, 0xEA1C0503, + 0x81C, 0xE91E0503, + 0x81C, 0xE8200503, + 0x81C, 0xE7220503, + 0x81C, 0xE6240503, + 0x81C, 0xE5260503, + 0x81C, 0xE4280503, + 0x81C, 0xE32A0503, + 0x81C, 0xC32C0503, + 0x81C, 0xC22E0503, + 0x81C, 0xC1300503, + 0x81C, 0xC0320503, + 0x81C, 0xA3340503, + 0x81C, 0xA2360503, + 0x81C, 0xA1380503, + 0x81C, 0xA03A0503, + 0x81C, 0x823C0503, + 0x81C, 0x813E0503, + 0x81C, 0x80400503, + 0x81C, 0x63420503, + 0x81C, 0x62440503, + 0x81C, 0x61460503, + 0x81C, 0x60480503, + 0x81C, 0x424A0503, + 0x81C, 0x414C0503, + 0x81C, 0x404E0503, + 0x81C, 0x22500503, + 0x81C, 0x21520503, + 0x81C, 0x20540503, + 0x81C, 0x03560503, + 0x81C, 0x02580503, + 0x81C, 0x015A0503, + 0x81C, 0x005C0503, + 0x81C, 0x005E0503, + 0x81C, 0x00600503, + 0x81C, 0x00620503, + 0x81C, 0x00640503, + 0x81C, 0x00660503, + 0x81C, 0x00680503, + 0x81C, 0x006A0503, + 0x81C, 0x006C0503, + 0x81C, 0x006E0503, + 0x81C, 0x00700503, + 0x81C, 0x00720503, + 0x81C, 0x00740503, + 0x81C, 0x00760503, + 0x81C, 0x00780503, + 0x81C, 0x007A0503, + 0x81C, 0x007C0503, + 0x81C, 0x007E0503, + 0x81C, 0x007E0503, + 0x90000003, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFE000503, + 0x81C, 0xFD020503, + 0x81C, 0xFC040503, + 0x81C, 0xFB060503, + 0x81C, 0xFA080503, + 0x81C, 0xF90A0503, + 0x81C, 0xF80C0503, + 0x81C, 0xF70E0503, + 0x81C, 0xF6100503, + 0x81C, 0xF5120503, + 0x81C, 0xF4140503, + 0x81C, 0xF3160503, + 0x81C, 0xF2180503, + 0x81C, 0xF11A0503, + 0x81C, 0xF01C0503, + 0x81C, 0xEF1E0503, + 0x81C, 0xEE200503, + 0x81C, 0xED220503, + 0x81C, 0xEC240503, + 0x81C, 0xEB260503, + 0x81C, 0xEA280503, + 0x81C, 0xE92A0503, + 0x81C, 0xE82C0503, + 0x81C, 0xE72E0503, + 0x81C, 0xE6300503, + 0x81C, 0xE5320503, + 0x81C, 0xE4340503, + 0x81C, 0xE3360503, + 0x81C, 0xC6380503, + 0x81C, 0xC53A0503, + 0x81C, 0xC43C0503, + 0x81C, 0xC33E0503, + 0x81C, 0xA5400503, + 0x81C, 0xA4420503, + 0x81C, 0xA3440503, + 0x81C, 0xA2460503, + 0x81C, 0xA1480503, + 0x81C, 0xA04A0503, + 0x81C, 0x824C0503, + 0x81C, 0x814E0503, + 0x81C, 0x80500503, + 0x81C, 0x64520503, + 0x81C, 0x63540503, + 0x81C, 0x62560503, + 0x81C, 0x61580503, + 0x81C, 0x605A0503, + 0x81C, 0x235C0503, + 0x81C, 0x225E0503, + 0x81C, 0x21600503, + 0x81C, 0x20620503, + 0x81C, 0x03640503, + 0x81C, 0x02660503, + 0x81C, 0x01680503, + 0x81C, 0x006A0503, + 0x81C, 0x006C0503, + 0x81C, 0x006E0503, + 0x81C, 0x00700503, + 0x81C, 0x00720503, + 0x81C, 0x00740503, + 0x81C, 0x00760503, + 0x81C, 0x00780503, + 0x81C, 0x007A0503, + 0x81C, 0x007C0503, + 0x81C, 0x007E0503, + 0x81C, 0x007E0503, + 0x90000004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF8000503, + 0x81C, 0xF7020503, + 0x81C, 0xF6040503, + 0x81C, 0xF5060503, + 0x81C, 0xF4080503, + 0x81C, 0xF30A0503, + 0x81C, 0xF20C0503, + 0x81C, 0xF10E0503, + 0x81C, 0xF0100503, + 0x81C, 0xEF120503, + 0x81C, 0xEE140503, + 0x81C, 0xED160503, + 0x81C, 0xEC180503, + 0x81C, 0xEB1A0503, + 0x81C, 0xEA1C0503, + 0x81C, 0xE91E0503, + 0x81C, 0xE8200503, + 0x81C, 0xE7220503, + 0x81C, 0xE6240503, + 0x81C, 0xE5260503, + 0x81C, 0xE4280503, + 0x81C, 0xE32A0503, + 0x81C, 0xC32C0503, + 0x81C, 0xC22E0503, + 0x81C, 0xC1300503, + 0x81C, 0xC0320503, + 0x81C, 0xA3340503, + 0x81C, 0xA2360503, + 0x81C, 0xA1380503, + 0x81C, 0xA03A0503, + 0x81C, 0x823C0503, + 0x81C, 0x813E0503, + 0x81C, 0x80400503, + 0x81C, 0x63420503, + 0x81C, 0x62440503, + 0x81C, 0x61460503, + 0x81C, 0x60480503, + 0x81C, 0x424A0503, + 0x81C, 0x414C0503, + 0x81C, 0x404E0503, + 0x81C, 0x22500503, + 0x81C, 0x21520503, + 0x81C, 0x20540503, + 0x81C, 0x03560503, + 0x81C, 0x02580503, + 0x81C, 0x015A0503, + 0x81C, 0x005C0503, + 0x81C, 0x005E0503, + 0x81C, 0x00600503, + 0x81C, 0x00620503, + 0x81C, 0x00640503, + 0x81C, 0x00660503, + 0x81C, 0x00680503, + 0x81C, 0x006A0503, + 0x81C, 0x006C0503, + 0x81C, 0x006E0503, + 0x81C, 0x00700503, + 0x81C, 0x00720503, + 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0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x9000000b, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF9000603, + 0x81C, 0xF8020603, + 0x81C, 0xF7040603, + 0x81C, 0xF6060603, + 0x81C, 0xF5080603, + 0x81C, 0xF40A0603, + 0x81C, 0xF30C0603, + 0x81C, 0xF20E0603, + 0x81C, 0xF1100603, + 0x81C, 0xF0120603, + 0x81C, 0xEF140603, + 0x81C, 0xEE160603, + 0x81C, 0xED180603, + 0x81C, 0xEC1A0603, + 0x81C, 0xEB1C0603, + 0x81C, 0xEA1E0603, + 0x81C, 0xE9200603, + 0x81C, 0xE8220603, + 0x81C, 0xE7240603, + 0x81C, 0xE6260603, + 0x81C, 0xE5280603, + 0x81C, 0xE42A0603, + 0x81C, 0xC42C0603, + 0x81C, 0xC32E0603, + 0x81C, 0xC2300603, + 0x81C, 0xC1320603, + 0x81C, 0xA3340603, + 0x81C, 0xA2360603, + 0x81C, 0xA1380603, + 0x81C, 0xA03A0603, + 0x81C, 0x823C0603, + 0x81C, 0x813E0603, + 0x81C, 0x80400603, + 0x81C, 0x64420603, + 0x81C, 0x63440603, + 0x81C, 0x62460603, + 0x81C, 0x61480603, + 0x81C, 0x604A0603, + 0x81C, 0x244C0603, + 0x81C, 0x234E0603, + 0x81C, 0x22500603, + 0x81C, 0x21520603, + 0x81C, 0x20540603, + 0x81C, 0x05560603, + 0x81C, 0x04580603, + 0x81C, 0x035A0603, + 0x81C, 0x025C0603, + 0x81C, 0x015E0603, + 0x81C, 0x00600603, + 0x81C, 0x00620603, + 0x81C, 0x00640603, + 0x81C, 0x00660603, + 0x81C, 0x00680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x9000000c, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000603, + 0x81C, 0xFB020603, + 0x81C, 0xFA040603, + 0x81C, 0xF9060603, + 0x81C, 0xF8080603, + 0x81C, 0xF70A0603, + 0x81C, 0xF60C0603, + 0x81C, 0xF50E0603, + 0x81C, 0xF4100603, + 0x81C, 0xF3120603, + 0x81C, 0xF2140603, + 0x81C, 0xF1160603, + 0x81C, 0xF0180603, + 0x81C, 0xEF1A0603, + 0x81C, 0xEE1C0603, + 0x81C, 0xED1E0603, + 0x81C, 0xEC200603, + 0x81C, 0xEB220603, + 0x81C, 0xEA240603, + 0x81C, 0xE9260603, + 0x81C, 0xE8280603, + 0x81C, 0xE72A0603, + 0x81C, 0xE62C0603, + 0x81C, 0xE52E0603, + 0x81C, 0xE4300603, + 0x81C, 0xE3320603, + 0x81C, 0xE2340603, + 0x81C, 0xC6360603, + 0x81C, 0xC5380603, + 0x81C, 0xC43A0603, + 0x81C, 0xC33C0603, + 0x81C, 0xA63E0603, + 0x81C, 0xA5400603, + 0x81C, 0xA4420603, + 0x81C, 0xA3440603, + 0x81C, 0xA2460603, + 0x81C, 0xA1480603, + 0x81C, 0x834A0603, + 0x81C, 0x824C0603, + 0x81C, 0x814E0603, + 0x81C, 0x64500603, + 0x81C, 0x63520603, + 0x81C, 0x62540603, + 0x81C, 0x61560603, + 0x81C, 0x60580603, + 0x81C, 0x405A0603, + 0x81C, 0x215C0603, + 0x81C, 0x205E0603, + 0x81C, 0x03600603, + 0x81C, 0x02620603, + 0x81C, 0x01640603, + 0x81C, 0x00660603, + 0x81C, 0x00680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000603, + 0x81C, 0xFB020603, + 0x81C, 0xFA040603, + 0x81C, 0xF9060603, + 0x81C, 0xF8080603, + 0x81C, 0xF70A0603, + 0x81C, 0xF60C0603, + 0x81C, 0xF50E0603, + 0x81C, 0xF4100603, + 0x81C, 0xF3120603, + 0x81C, 0xF2140603, + 0x81C, 0xF1160603, + 0x81C, 0xF0180603, + 0x81C, 0xEE1A0603, + 0x81C, 0xED1C0603, + 0x81C, 0xEC1E0603, + 0x81C, 0xEB200603, + 0x81C, 0xEA220603, + 0x81C, 0xE9240603, + 0x81C, 0xE8260603, + 0x81C, 0xE7280603, + 0x81C, 0xE62A0603, + 0x81C, 0xE52C0603, + 0x81C, 0xE42E0603, + 0x81C, 0xE3300603, + 0x81C, 0xE2320603, + 0x81C, 0xC6340603, + 0x81C, 0xC5360603, + 0x81C, 0xC4380603, + 0x81C, 0xC33A0603, + 0x81C, 0xA63C0603, + 0x81C, 0xA53E0603, + 0x81C, 0xA4400603, + 0x81C, 0xA3420603, + 0x81C, 0xA2440603, + 0x81C, 0xA1460603, + 0x81C, 0x83480603, + 0x81C, 0x824A0603, + 0x81C, 0x814C0603, + 0x81C, 0x804E0603, + 0x81C, 0x63500603, + 0x81C, 0x62520603, + 0x81C, 0x61540603, + 0x81C, 0x42560603, + 0x81C, 0x41580603, + 0x81C, 0x405A0603, + 0x81C, 0x225C0603, + 0x81C, 0x215E0603, + 0x81C, 0x20600603, + 0x81C, 0x04620603, + 0x81C, 0x03640603, + 0x81C, 0x02660603, + 0x81C, 0x01680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000603, + 0x81C, 0xFB020603, + 0x81C, 0xFA040603, + 0x81C, 0xF9060603, + 0x81C, 0xF8080603, + 0x81C, 0xF70A0603, + 0x81C, 0xF60C0603, + 0x81C, 0xF50E0603, + 0x81C, 0xF4100603, + 0x81C, 0xF3120603, + 0x81C, 0xF2140603, + 0x81C, 0xF1160603, + 0x81C, 0xF0180603, + 0x81C, 0xEE1A0603, + 0x81C, 0xED1C0603, + 0x81C, 0xEC1E0603, + 0x81C, 0xEB200603, + 0x81C, 0xEA220603, + 0x81C, 0xE9240603, + 0x81C, 0xE8260603, + 0x81C, 0xE7280603, + 0x81C, 0xE62A0603, + 0x81C, 0xE52C0603, + 0x81C, 0xE42E0603, + 0x81C, 0xE3300603, + 0x81C, 0xE2320603, + 0x81C, 0xC6340603, + 0x81C, 0xC5360603, + 0x81C, 0xC4380603, + 0x81C, 0xC33A0603, + 0x81C, 0xA63C0603, + 0x81C, 0xA53E0603, + 0x81C, 0xA4400603, + 0x81C, 0xA3420603, + 0x81C, 0xA2440603, + 0x81C, 0xA1460603, + 0x81C, 0x83480603, + 0x81C, 0x824A0603, + 0x81C, 0x814C0603, + 0x81C, 0x804E0603, + 0x81C, 0x63500603, + 0x81C, 0x62520603, + 0x81C, 0x61540603, + 0x81C, 0x42560603, + 0x81C, 0x41580603, + 0x81C, 0x405A0603, + 0x81C, 0x225C0603, + 0x81C, 0x215E0603, + 0x81C, 0x20600603, + 0x81C, 0x04620603, + 0x81C, 0x03640603, + 0x81C, 0x02660603, + 0x81C, 0x01680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x9000000f, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xBF000603, + 0x81C, 0xBF020603, + 0x81C, 0xBF040603, + 0x81C, 0xBF060603, + 0x81C, 0xBF080603, + 0x81C, 0xBE0A0603, + 0x81C, 0xBD0C0603, + 0x81C, 0xBC0E0603, + 0x81C, 0xBB100603, + 0x81C, 0xBA120603, + 0x81C, 0xB9140603, + 0x81C, 0xB8160603, + 0x81C, 0xB7180603, + 0x81C, 0xB61A0603, + 0x81C, 0xB51C0603, + 0x81C, 0xB41E0603, + 0x81C, 0xB1200603, + 0x81C, 0xB2220603, + 0x81C, 0xB1240603, + 0x81C, 0xB0260603, + 0x81C, 0xAF280603, + 0x81C, 0xAE2A0603, + 0x81C, 0xAD2C0603, + 0x81C, 0xAC2E0603, + 0x81C, 0xAB300603, + 0x81C, 0xAA320603, + 0x81C, 0xC6340603, + 0x81C, 0xC5360603, + 0x81C, 0xC4380603, + 0x81C, 0xC33A0603, + 0x81C, 0x883C0603, + 0x81C, 0x873E0603, + 0x81C, 0x86400603, + 0x81C, 0x85420603, + 0x81C, 0x84440603, + 0x81C, 0x83460603, + 0x81C, 0x67480603, + 0x81C, 0x664A0603, + 0x81C, 0x654C0603, + 0x81C, 0x644E0603, + 0x81C, 0x27500603, + 0x81C, 0x26520603, + 0x81C, 0x25540603, + 0x81C, 0x24560603, + 0x81C, 0x23580603, + 0x81C, 0x225A0603, + 0x81C, 0x215C0603, + 0x81C, 0x205E0603, + 0x81C, 0x03600603, + 0x81C, 0x02620603, + 0x81C, 0x01640603, + 0x81C, 0x00660603, + 0x81C, 0x00680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0x81C, 0x007E0603, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000403, + 0x81C, 0xFB000603, + 0x81C, 0xFA020603, + 0x81C, 0xF9040603, + 0x81C, 0xF8060603, + 0x81C, 0xF7080603, + 0x81C, 0xF60A0603, + 0x81C, 0xF50C0603, + 0x81C, 0xF40E0603, + 0x81C, 0xF3100603, + 0x81C, 0xF2120603, + 0x81C, 0xF1140603, + 0x81C, 0xF0160603, + 0x81C, 0xEF180603, + 0x81C, 0xEE1A0603, + 0x81C, 0xED1C0603, + 0x81C, 0xEC1E0603, + 0x81C, 0xEB200603, + 0x81C, 0xEA220603, + 0x81C, 0xE9240603, + 0x81C, 0xE8260603, + 0x81C, 0xE7280603, + 0x81C, 0xE62A0603, + 0x81C, 0xE52C0603, + 0x81C, 0xE42E0603, + 0x81C, 0xE3300603, + 0x81C, 0xE2320603, + 0x81C, 0xC6340603, + 0x81C, 0xC5360603, + 0x81C, 0xC4380603, + 0x81C, 0xC33A0603, + 0x81C, 0xA63C0603, + 0x81C, 0xA53E0603, + 0x81C, 0xA4400603, + 0x81C, 0xA3420603, + 0x81C, 0xA2440603, + 0x81C, 0xA1460603, + 0x81C, 0x83480603, + 0x81C, 0x824A0603, + 0x81C, 0x814C0603, + 0x81C, 0x644E0603, + 0x81C, 0x63500603, + 0x81C, 0x62520603, + 0x81C, 0x61540603, + 0x81C, 0x60560603, + 0x81C, 0x40580603, + 0x81C, 0x215A0603, + 0x81C, 0x205C0603, + 0x81C, 0x035E0603, + 0x81C, 0x02600603, + 0x81C, 0x01620603, + 0x81C, 0x00640603, + 0x81C, 0x00660603, + 0x81C, 0x00680603, + 0x81C, 0x006A0603, + 0x81C, 0x006C0603, + 0x81C, 0x006E0603, + 0x81C, 0x00700603, + 0x81C, 0x00720603, + 0x81C, 0x00740603, + 0x81C, 0x00760603, + 0x81C, 0x00780603, + 0x81C, 0x007A0603, + 0x81C, 0x007C0603, + 0x81C, 0x007E0603, + 0xA0000000, 0x00000000, + 0x81C, 0xFD000603, + 0x81C, 0xFC020603, + 0x81C, 0xFB040603, + 0x81C, 0xFA060603, + 0x81C, 0xF9080603, + 0x81C, 0xF80A0603, + 0x81C, 0xF70C0603, + 0x81C, 0xF60E0603, + 0x81C, 0xF5100603, + 0x81C, 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0x63500703, + 0x81C, 0x62520703, + 0x81C, 0x61540703, + 0x81C, 0x42560703, + 0x81C, 0x41580703, + 0x81C, 0x405A0703, + 0x81C, 0x225C0703, + 0x81C, 0x215E0703, + 0x81C, 0x20600703, + 0x81C, 0x04620703, + 0x81C, 0x03640703, + 0x81C, 0x02660703, + 0x81C, 0x01680703, + 0x81C, 0x006A0703, + 0x81C, 0x006C0703, + 0x81C, 0x006E0703, + 0x81C, 0x00700703, + 0x81C, 0x00720703, + 0x81C, 0x00740703, + 0x81C, 0x00760703, + 0x81C, 0x00780703, + 0x81C, 0x007A0703, + 0x81C, 0x007C0703, + 0x81C, 0x007E0703, + 0x81C, 0x007E0703, + 0x9000000f, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xBF000703, + 0x81C, 0xBF020703, + 0x81C, 0xBF040703, + 0x81C, 0xBF060703, + 0x81C, 0xBF080703, + 0x81C, 0xBE0A0703, + 0x81C, 0xBD0C0703, + 0x81C, 0xBC0E0703, + 0x81C, 0xBB100703, + 0x81C, 0xBA120703, + 0x81C, 0xB9140703, + 0x81C, 0xB8160703, + 0x81C, 0xB7180703, + 0x81C, 0xB61A0703, + 0x81C, 0xB51C0703, + 0x81C, 0xB41E0703, + 0x81C, 0xB1200703, + 0x81C, 0xB2220703, + 0x81C, 0xB1240703, + 0x81C, 0xB0260703, + 0x81C, 0xAF280703, + 0x81C, 0xAE2A0703, + 0x81C, 0xAD2C0703, + 0x81C, 0xAC2E0703, + 0x81C, 0xAB300703, + 0x81C, 0xAA320703, + 0x81C, 0xC6340703, + 0x81C, 0xC5360703, + 0x81C, 0xC4380703, + 0x81C, 0xC33A0703, + 0x81C, 0x883C0703, + 0x81C, 0x873E0703, + 0x81C, 0x86400703, + 0x81C, 0x85420703, + 0x81C, 0x84440703, + 0x81C, 0x83460703, + 0x81C, 0x67480703, + 0x81C, 0x664A0703, + 0x81C, 0x654C0703, + 0x81C, 0x644E0703, + 0x81C, 0x27500703, + 0x81C, 0x26520703, + 0x81C, 0x25540703, + 0x81C, 0x24560703, + 0x81C, 0x23580703, + 0x81C, 0x225A0703, + 0x81C, 0x215C0703, + 0x81C, 0x205E0703, + 0x81C, 0x03600703, + 0x81C, 0x02620703, + 0x81C, 0x01640703, + 0x81C, 0x00660703, + 0x81C, 0x00680703, + 0x81C, 0x006A0703, + 0x81C, 0x006C0703, + 0x81C, 0x006E0703, + 0x81C, 0x00700703, + 0x81C, 0x00720703, + 0x81C, 0x00740703, + 0x81C, 0x00760703, + 0x81C, 0x00780703, + 0x81C, 0x007A0703, + 0x81C, 0x007C0703, + 0x81C, 0x007E0703, + 0x81C, 0x007E0703, + 0x90000010, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000403, + 0x81C, 0xFB000703, + 0x81C, 0xFA020703, + 0x81C, 0xF9040703, + 0x81C, 0xF8060703, + 0x81C, 0xF7080703, + 0x81C, 0xF60A0703, + 0x81C, 0xF50C0703, + 0x81C, 0xF40E0703, + 0x81C, 0xF3100703, + 0x81C, 0xF2120703, + 0x81C, 0xF1140703, + 0x81C, 0xF0160703, + 0x81C, 0xEF180703, + 0x81C, 0xEE1A0703, + 0x81C, 0xED1C0703, + 0x81C, 0xEC1E0703, + 0x81C, 0xEB200703, + 0x81C, 0xEA220703, + 0x81C, 0xE9240703, + 0x81C, 0xE8260703, + 0x81C, 0xE7280703, + 0x81C, 0xE62A0703, + 0x81C, 0xE52C0703, + 0x81C, 0xE42E0703, + 0x81C, 0xE3300703, + 0x81C, 0xE2320703, + 0x81C, 0xC6340703, + 0x81C, 0xC5360703, + 0x81C, 0xC4380703, + 0x81C, 0xC33A0703, + 0x81C, 0xA63C0703, + 0x81C, 0xA53E0703, + 0x81C, 0xA4400703, + 0x81C, 0xA3420703, + 0x81C, 0xA2440703, + 0x81C, 0x84460703, + 0x81C, 0x83480703, + 0x81C, 0x824A0703, + 0x81C, 0x814C0703, + 0x81C, 0x804E0703, + 0x81C, 0x63500703, + 0x81C, 0x62520703, + 0x81C, 0x61540703, + 0x81C, 0x60560703, + 0x81C, 0x22580703, + 0x81C, 0x055A0703, + 0x81C, 0x045C0703, + 0x81C, 0x035E0703, + 0x81C, 0x02600703, + 0x81C, 0x01620703, + 0x81C, 0x00640703, + 0x81C, 0x00660703, + 0x81C, 0x00680703, + 0x81C, 0x006A0703, + 0x81C, 0x006C0703, + 0x81C, 0x006E0703, + 0x81C, 0x00700703, + 0x81C, 0x00720703, + 0x81C, 0x00740703, + 0x81C, 0x00760703, + 0x81C, 0x00780703, + 0x81C, 0x007A0703, + 0x81C, 0x007C0703, + 0x81C, 0x007E0703, + 0xA0000000, 0x00000000, + 0x81C, 0xFC000703, + 0x81C, 0xFB020703, + 0x81C, 0xFA040703, + 0x81C, 0xF9060703, + 0x81C, 0xF8080703, + 0x81C, 0xF70A0703, + 0x81C, 0xF60C0703, + 0x81C, 0xF50E0703, + 0x81C, 0xF4100703, + 0x81C, 0xF3120703, + 0x81C, 0xF2140703, + 0x81C, 0xF1160703, + 0x81C, 0xF0180703, + 0x81C, 0xEF1A0703, + 0x81C, 0xEE1C0703, + 0x81C, 0xED1E0703, + 0x81C, 0xEC200703, + 0x81C, 0xEB220703, + 0x81C, 0xEA240703, + 0x81C, 0xE9260703, + 0x81C, 0xE8280703, + 0x81C, 0xE72A0703, + 0x81C, 0xE62C0703, + 0x81C, 0xE52E0703, + 0x81C, 0xE4300703, + 0x81C, 0xE3320703, + 0x81C, 0xE2340703, + 0x81C, 0xC6360703, + 0x81C, 0xC5380703, + 0x81C, 0xC43A0703, + 0x81C, 0xC33C0703, + 0x81C, 0xA63E0703, + 0x81C, 0xA5400703, + 0x81C, 0xA4420703, + 0x81C, 0xA3440703, + 0x81C, 0xA2460703, + 0x81C, 0x84480703, + 0x81C, 0x834A0703, + 0x81C, 0x824C0703, + 0x81C, 0x814E0703, + 0x81C, 0x80500703, + 0x81C, 0x63520703, + 0x81C, 0x62540703, + 0x81C, 0x61560703, + 0x81C, 0x60580703, + 0x81C, 0x235A0703, + 0x81C, 0x225C0703, + 0x81C, 0x215E0703, + 0x81C, 0x20600703, + 0x81C, 0x03620703, + 0x81C, 0x02640703, + 0x81C, 0x01660703, + 0x81C, 0x00680703, + 0x81C, 0x006A0703, + 0x81C, 0x006C0703, + 0x81C, 0x006E0703, + 0x81C, 0x00700703, + 0x81C, 0x00720703, + 0x81C, 0x00740703, + 0x81C, 0x00760703, + 0x81C, 0x00780703, + 0x81C, 0x007A0703, + 0x81C, 0x007C0703, + 0x81C, 0x007E0703, + 0x81C, 0x007E0703, + 0xB0000000, 0x00000000, + 0x80000000, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + 0x9000000d, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + 0x9000000e, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + 0xA0000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xE50, 0x00000022, + 0xE50, 0x00000020, + 0xB0000000, 0x00000000, + +}; + +void +odm_read_and_config_mp_8822b_agc_tab( + struct dm_struct *dm +) +{ + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8822b_agc_tab)/sizeof(u32); + u32 *array = array_mp_8822b_agc_tab; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_agc_tab\n"); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); } else if (c_cond == COND_ELSE) { /*else*/ is_matched = is_skipped?false:true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); } } else if (v1 & BIT(30)) { /*negative condition*/ if (is_skipped == false) { - if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { is_matched = true; is_skipped = true; } else { @@ -5408,7 +9640,7 @@ odm_read_and_config_mp_8822b_agc_tab( } } else { if (is_matched) - odm_config_bb_agc_8822b(p_dm_odm, v1, MASKDWORD, v2); + odm_config_bb_agc_8822b(dm, v1, MASKDWORD, v2); } i = i + 2; } @@ -5417,7 +9649,7 @@ odm_read_and_config_mp_8822b_agc_tab( u32 odm_get_version_mp_8822b_agc_tab(void) { - return 85; + return 104; } /****************************************************************************** @@ -5429,20 +9661,20 @@ u32 array_mp_8822b_phy_reg[] = { 0x804, 0x800181A0, 0x808, 0x0E028233, 0x80C, 0x10000013, - 0x810, 0x21101243, - 0x814, 0x020C3D10, + 0x810, 0x22101243, + 0x814, 0x020C3D11, 0x818, 0x84A10385, 0x81C, 0x1E1E081F, 0x820, 0x0001AAAA, 0x824, 0x00030FE0, 0x828, 0x0000CCCC, 0x82C, 0x75CB7010, - 0x830, 0x79A0EA2A, + 0x830, 0x79A0EAAA, 0x834, 0x072E6986, 0x838, 0x87766441, 0x83C, 0x9194B2B7, 0x840, 0x171750E0, - 0x844, 0x4C3D7CDB, + 0x844, 0x4D3D7CDB, 0x848, 0x4AD0408B, 0x84C, 0x6AFBF7A5, 0x850, 0x28A74706, @@ -5617,7 +9849,7 @@ u32 array_mp_8822b_phy_reg[] = { 0xB88, 0x00000000, 0xB8C, 0x00000000, 0xC00, 0x00000007, - 0xC04, 0x00240020, + 0xC04, 0x00000020, 0xC08, 0x60403231, 0xC0C, 0x00012345, 0xC10, 0x00000100, @@ -5674,7 +9906,7 @@ u32 array_mp_8822b_phy_reg[] = { 0xCE8, 0x00000000, 0xCEC, 0x00000000, 0xE00, 0x00000007, - 0xE04, 0x00240020, + 0xE04, 0x00000020, 0xE08, 0x60403231, 0xE0C, 0x00012345, 0xE10, 0x00000100, @@ -5695,7 +9927,7 @@ u32 array_mp_8822b_phy_reg[] = { 0xE4C, 0x00000000, 0xE50, 0x00000020, 0xE54, 0x00000000, - 0xE58, 0xD8020402, + 0xE58, 0xD8120402, 0xE5C, 0xDE000120, 0xE68, 0x5979993F, 0xE6C, 0x0000122A, @@ -6922,7 +11154,7 @@ u32 array_mp_8822b_phy_reg[] = { void odm_read_and_config_mp_8822b_phy_reg( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 i = 0; @@ -6933,7 +11165,7 @@ odm_read_and_config_mp_8822b_phy_reg( u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_phy_reg\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_phy_reg\n"); while ((i + 1) < array_len) { v1 = array[i]; @@ -6945,18 +11177,18 @@ odm_read_and_config_mp_8822b_phy_reg( if (c_cond == COND_ENDIF) {/*end*/ is_matched = true; is_skipped = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); } else if (c_cond == COND_ELSE) { /*else*/ is_matched = is_skipped?false:true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); } } else if (v1 & BIT(30)) { /*negative condition*/ if (is_skipped == false) { - if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { is_matched = true; is_skipped = true; } else { @@ -6968,7 +11200,7 @@ odm_read_and_config_mp_8822b_phy_reg( } } else { if (is_matched) - odm_config_bb_phy_8822b(p_dm_odm, v1, MASKDWORD, v2); + odm_config_bb_phy_8822b(dm, v1, MASKDWORD, v2); } i = i + 2; } @@ -6977,7 +11209,7 @@ odm_read_and_config_mp_8822b_phy_reg( u32 odm_get_version_mp_8822b_phy_reg(void) { - return 85; + return 104; } /****************************************************************************** @@ -6985,6 +11217,100 @@ odm_get_version_mp_8822b_phy_reg(void) ******************************************************************************/ u32 array_mp_8822b_phy_reg_pg[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x38404244, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323436, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x38404244, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x38404244, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x30323436, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x38404244, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x30323436, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x42442628, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x38404244, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323436, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x38404244, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x38404244, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x30323436, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x38404244, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x30323436, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x42442628, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628 +}; + +void +odm_read_and_config_mp_8822b_phy_reg_pg( + struct dm_struct *dm +) +{ + u32 i = 0; + u32 array_len = sizeof(array_mp_8822b_phy_reg_pg)/sizeof(u32); + u32 *array = array_mp_8822b_phy_reg_pg; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrByRate = array_len/6; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_phy_reg_pg\n"); + + dm->phy_reg_pg_version = 1; + dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < array_len; i += 6) { + u32 v1 = array[i]; + u32 v2 = array[i+1]; + u32 v3 = array[i+2]; + u32 v4 = array[i+3]; + u32 v5 = array[i+4]; + u32 v6 = array[i+5]; + + odm_config_bb_phy_reg_pg_8822b(dm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* phy_reg_pg_type12.TXT +******************************************************************************/ + +u32 array_mp_8822b_phy_reg_pg_type12[] = { 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, @@ -7009,51 +11335,709 @@ u32 array_mp_8822b_phy_reg_pg[] = { 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, - 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, - 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, - 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, - 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, - 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, - 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, - 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, - 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, - 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, - 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, - 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, - 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, - 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, - 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, - 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, - 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, - 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, - 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 + 1, 0, 0, 0x00000c24, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x22242628, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x30323436, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x34361820, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x26283032, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x18202224, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x22242628, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x30323436, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x22242628, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x22242628, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x34361820, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x26283032, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x18202224 }; void -odm_read_and_config_mp_8822b_phy_reg_pg( - struct PHY_DM_STRUCT *p_dm_odm +odm_read_and_config_mp_8822b_phy_reg_pg_type12( + struct dm_struct *dm ) { u32 i = 0; - u32 array_len = sizeof(array_mp_8822b_phy_reg_pg)/sizeof(u32); - u32 *array = array_mp_8822b_phy_reg_pg; + u32 array_len = sizeof(array_mp_8822b_phy_reg_pg_type12)/sizeof(u32); + u32 *array = array_mp_8822b_phy_reg_pg_type12; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrByRate = array_len/6; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_phy_reg_pg_type12\n"); + + dm->phy_reg_pg_version = 1; + dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < array_len; i += 6) { + u32 v1 = array[i]; + u32 v2 = array[i+1]; + u32 v3 = array[i+2]; + u32 v4 = array[i+3]; + u32 v5 = array[i+4]; + u32 v6 = array[i+5]; + + odm_config_bb_phy_reg_pg_8822b(dm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* phy_reg_pg_type15.TXT +******************************************************************************/ + +u32 array_mp_8822b_phy_reg_pg_type15[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 +}; + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type15( + struct dm_struct *dm +) +{ + u32 i = 0; + u32 array_len = sizeof(array_mp_8822b_phy_reg_pg_type15)/sizeof(u32); + u32 *array = array_mp_8822b_phy_reg_pg_type15; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrByRate = array_len/6; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_phy_reg_pg_type15\n"); + + dm->phy_reg_pg_version = 1; + dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < array_len; i += 6) { + u32 v1 = array[i]; + u32 v2 = array[i+1]; + u32 v3 = array[i+2]; + u32 v4 = array[i+3]; + u32 v5 = array[i+4]; + u32 v6 = array[i+5]; + + odm_config_bb_phy_reg_pg_8822b(dm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* phy_reg_pg_type16.TXT +******************************************************************************/ + +u32 array_mp_8822b_phy_reg_pg_type16[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 +}; + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type16( + struct dm_struct *dm +) +{ + u32 i = 0; + u32 array_len = sizeof(array_mp_8822b_phy_reg_pg_type16)/sizeof(u32); + u32 *array = array_mp_8822b_phy_reg_pg_type16; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrByRate = array_len/6; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_phy_reg_pg_type16\n"); + + dm->phy_reg_pg_version = 1; + dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < array_len; i += 6) { + u32 v1 = array[i]; + u32 v2 = array[i+1]; + u32 v3 = array[i+2]; + u32 v4 = array[i+3]; + u32 v5 = array[i+4]; + u32 v6 = array[i+5]; + + odm_config_bb_phy_reg_pg_8822b(dm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* phy_reg_pg_type17.TXT +******************************************************************************/ + +u32 array_mp_8822b_phy_reg_pg_type17[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 +}; + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type17( + struct dm_struct *dm +) +{ + u32 i = 0; + u32 array_len = sizeof(array_mp_8822b_phy_reg_pg_type17)/sizeof(u32); + u32 *array = array_mp_8822b_phy_reg_pg_type17; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrByRate = array_len/6; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_phy_reg_pg_type17\n"); + + dm->phy_reg_pg_version = 1; + dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < array_len; i += 6) { + u32 v1 = array[i]; + u32 v2 = array[i+1]; + u32 v3 = array[i+2]; + u32 v4 = array[i+3]; + u32 v5 = array[i+4]; + u32 v6 = array[i+5]; + + odm_config_bb_phy_reg_pg_8822b(dm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* phy_reg_pg_type2.TXT +******************************************************************************/ + +u32 array_mp_8822b_phy_reg_pg_type2[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x40424446, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x38404244, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x30323436, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x38404244, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x38404244, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x42442628, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x34363840, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x40424446, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x38404244, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x30323436, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x38404244, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x38404244, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x42442628, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x34363840, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x26283032 +}; + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type2( + struct dm_struct *dm +) +{ + u32 i = 0; + u32 array_len = sizeof(array_mp_8822b_phy_reg_pg_type2)/sizeof(u32); + u32 *array = array_mp_8822b_phy_reg_pg_type2; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrByRate = array_len/6; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_phy_reg_pg_type2\n"); + + dm->phy_reg_pg_version = 1; + dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < array_len; i += 6) { + u32 v1 = array[i]; + u32 v2 = array[i+1]; + u32 v3 = array[i+2]; + u32 v4 = array[i+3]; + u32 v5 = array[i+4]; + u32 v6 = array[i+5]; + + odm_config_bb_phy_reg_pg_8822b(dm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* phy_reg_pg_type3.TXT +******************************************************************************/ + +u32 array_mp_8822b_phy_reg_pg_type3[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 +}; + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type3( + struct dm_struct *dm +) +{ + u32 i = 0; + u32 array_len = sizeof(array_mp_8822b_phy_reg_pg_type3)/sizeof(u32); + u32 *array = array_mp_8822b_phy_reg_pg_type3; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrByRate = array_len/6; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_phy_reg_pg_type3\n"); + + dm->phy_reg_pg_version = 1; + dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < array_len; i += 6) { + u32 v1 = array[i]; + u32 v2 = array[i+1]; + u32 v3 = array[i+2]; + u32 v4 = array[i+3]; + u32 v5 = array[i+4]; + u32 v6 = array[i+5]; + + odm_config_bb_phy_reg_pg_8822b(dm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* phy_reg_pg_type4.TXT +******************************************************************************/ + +u32 array_mp_8822b_phy_reg_pg_type4[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x38404244, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x42444648, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x40424446, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x32343638, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x40424446, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x40424446, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x44462830, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x36384042, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x38404244, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x42444648, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x40424446, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x32343638, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x40424446, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x40424446, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x44462830, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x36384042, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x28303234, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x40424446, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x38404244, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x30323436, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x38404244, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x38404244, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x42442628, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x34363840, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x40424446, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x38404244, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x30323436, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x38404244, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x38404244, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x30323436, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x42442628, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x34363840, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x26283032 +}; + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type4( + struct dm_struct *dm +) +{ + u32 i = 0; + u32 array_len = sizeof(array_mp_8822b_phy_reg_pg_type4)/sizeof(u32); + u32 *array = array_mp_8822b_phy_reg_pg_type4; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrByRate = array_len/6; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_phy_reg_pg_type4\n"); + + dm->phy_reg_pg_version = 1; + dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < array_len; i += 6) { + u32 v1 = array[i]; + u32 v2 = array[i+1]; + u32 v3 = array[i+2]; + u32 v4 = array[i+3]; + u32 v5 = array[i+4]; + u32 v6 = array[i+5]; + + odm_config_bb_phy_reg_pg_8822b(dm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* phy_reg_pg_type5.TXT +******************************************************************************/ + +u32 array_mp_8822b_phy_reg_pg_type5[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840, + 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224, + 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436, + 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628, + 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638, + 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042, + 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234, + 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032, + 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840, + 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840, + 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032, + 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224, + 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436, + 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638, + 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022, + 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234, + 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426, + 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840, + 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032, + 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830, + 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638, + 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638, + 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830, + 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022, + 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234, + 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426 +}; + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type5( + struct dm_struct *dm +) +{ + u32 i = 0; + u32 array_len = sizeof(array_mp_8822b_phy_reg_pg_type5)/sizeof(u32); + u32 *array = array_mp_8822b_phy_reg_pg_type5; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - PlatformZeroMemory(p_hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - p_hal_data->nLinesReadPwrByRate = array_len/6; + PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrByRate = array_len/6; #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_phy_reg_pg\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_phy_reg_pg_type5\n"); - p_dm_odm->phy_reg_pg_version = 1; - p_dm_odm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + dm->phy_reg_pg_version = 1; + dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; for (i = 0; i < array_len; i += 6) { u32 v1 = array[i]; @@ -7063,10 +12047,10 @@ odm_read_and_config_mp_8822b_phy_reg_pg( u32 v5 = array[i+4]; u32 v6 = array[i+5]; - odm_config_bb_phy_reg_pg_8822b(p_dm_odm, v1, v2, v3, v4, v5, v6); + odm_config_bb_phy_reg_pg_8822b(dm, v1, v2, v3, v4, v5, v6); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)p_hal_data->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + rsprintf((char *)hal_data->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); #endif } diff --git a/hal/phydm/rtl8822b/halhwimg8822b_bb.h b/hal/phydm/rtl8822b/halhwimg8822b_bb.h index cd0ba96..f5e2f48 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_bb.h +++ b/hal/phydm/rtl8822b/halhwimg8822b_bb.h @@ -1,19 +1,29 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1*/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*Image2HeaderVersion: R3 1.0*/ #if (RTL8822B_SUPPORT == 1) #ifndef __INC_MP_BB_HW_IMG_8822B_H #define __INC_MP_BB_HW_IMG_8822B_H @@ -25,7 +35,7 @@ void odm_read_and_config_mp_8822b_agc_tab(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_agc_tab(void); @@ -35,7 +45,7 @@ u32 odm_get_version_mp_8822b_agc_tab(void); void odm_read_and_config_mp_8822b_phy_reg(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_phy_reg(void); @@ -45,10 +55,90 @@ u32 odm_get_version_mp_8822b_phy_reg(void); void odm_read_and_config_mp_8822b_phy_reg_pg(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_phy_reg_pg(void); +/****************************************************************************** +* phy_reg_pg_type12.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type12(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_phy_reg_pg_type12(void); + +/****************************************************************************** +* phy_reg_pg_type15.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type15(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_phy_reg_pg_type15(void); + +/****************************************************************************** +* phy_reg_pg_type16.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type16(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_phy_reg_pg_type16(void); + +/****************************************************************************** +* phy_reg_pg_type17.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type17(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_phy_reg_pg_type17(void); + +/****************************************************************************** +* phy_reg_pg_type2.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type2(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_phy_reg_pg_type2(void); + +/****************************************************************************** +* phy_reg_pg_type3.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type3(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_phy_reg_pg_type3(void); + +/****************************************************************************** +* phy_reg_pg_type4.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type4(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_phy_reg_pg_type4(void); + +/****************************************************************************** +* phy_reg_pg_type5.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_phy_reg_pg_type5(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_phy_reg_pg_type5(void); + #endif #endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8822b/halhwimg8822b_fw.c b/hal/phydm/rtl8822b/halhwimg8822b_fw.c deleted file mode 100644 index 6b5ed8e..0000000 --- a/hal/phydm/rtl8822b/halhwimg8822b_fw.c +++ /dev/null @@ -1,13433 +0,0 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#ifdef LOAD_FW_HEADER_FROM_DRIVER - #include "../../rtl8822b/hal8822b_fw.h" -#endif - - -#if (RTL8822B_SUPPORT == 1) -#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) - - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u8 array_mp_8822b_fw_ap[] = { - 0x22, 0x88, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, 0xC9, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x03, 0x1B, 0x10, 0x33, 0xE0, 0x07, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x20, 0x80, 0x88, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xB0, 0xDD, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x12, 0x80, 0x00, 0x00, 0x00, 0x80, - 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0xB0, 0x67, 0x00, 0x18, 0xEA, 0x34, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7, 0x62, 0x32, 0x01, 0x10, - 0x00, 0x6A, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0x91, 0x23, 0x00, 0x00, - 0x90, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; -u32 array_length_mp_8822b_fw_ap = 65928; - -#endif - -void -odm_read_firmware_mp_8822b_fw_ap( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_firmware, - u32 *p_firmware_size -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)p_firmware) = (SIZE_PTR)array_mp_8822b_fw_ap; -#else - odm_move_memory(p_dm_odm, p_firmware, array_mp_8822b_fw_ap, array_length_mp_8822b_fw_ap); -#endif - *p_firmware_size = array_length_mp_8822b_fw_ap; -} - - -#endif /* #if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)) */ - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u8 array_mp_8822b_fw_nic[] = { - 0x22, 0x88, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, 0xC9, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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u8 *p_firmware, - u32 *p_firmware_size -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)p_firmware) = (SIZE_PTR)array_mp_8822b_fw_nic; -#else - odm_move_memory(p_dm_odm, p_firmware, array_mp_8822b_fw_nic, array_length_mp_8822b_fw_nic); -#endif - *p_firmware_size = array_length_mp_8822b_fw_nic; -} - -#ifndef LOAD_FW_HEADER_FROM_DRIVER -u8 array_mp_8822b_fw_wowlan[] = { - 0x22, 0x88, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, 0xC9, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x03, 0x1B, 0x10, 0x33, 0xE0, 0x07, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x20, 0x80, 0xE8, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x60, 0xDB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x12, 0x80, 0x00, 0x00, 0x00, 0x80, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x4C, 0xE9, 0x6C, 0xE9, 0x0C, 0x93, 0x4A, 0xA3, 0x0D, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0x81, 0xF0, - 0xF0, 0x9A, 0x83, 0x67, 0x01, 0x6D, 0x18, 0x6E, 0x04, 0xD0, 0x00, 0x18, 0xCB, 0x33, 0x4C, 0xE9, - 0xFF, 0x6A, 0x4C, 0xE9, 0x0C, 0x94, 0x06, 0x95, 0x00, 0x18, 0xDE, 0x32, 0x01, 0x2A, 0x00, 0x69, - 0x51, 0x67, 0x0B, 0x97, 0x0A, 0x91, 0x09, 0x90, 0x06, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62, - 0x08, 0xD1, 0x07, 0xD0, 0xFF, 0x68, 0x0C, 0xED, 0x24, 0x67, 0x0D, 0xD7, 0x04, 0xD5, 0xCC, 0xE8, - 0x00, 0x18, 0x7C, 0x36, 0x0F, 0x22, 0x04, 0x95, 0x91, 0x67, 0x00, 0x18, 0xCC, 0x35, 0x0A, 0x22, - 0x0D, 0x96, 0x91, 0x67, 0xB0, 0x67, 0x00, 0x18, 0xFB, 0x34, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7, - 0x62, 0x32, 0x01, 0x10, 0x00, 0x6A, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, - 0xE9, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; -u32 array_length_mp_8822b_fw_wowlan = 59032; - -#endif - -void -odm_read_firmware_mp_8822b_fw_wowlan( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_firmware, - u32 *p_firmware_size -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - *((SIZE_PTR *)p_firmware) = (SIZE_PTR)array_mp_8822b_fw_wowlan; -#else - odm_move_memory(p_dm_odm, p_firmware, array_mp_8822b_fw_wowlan, array_length_mp_8822b_fw_wowlan); -#endif - *p_firmware_size = array_length_mp_8822b_fw_wowlan; -} - - - -#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ - -#endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8822b/halhwimg8822b_fw.h b/hal/phydm/rtl8822b/halhwimg8822b_fw.h deleted file mode 100644 index 9c52383..0000000 --- a/hal/phydm/rtl8822b/halhwimg8822b_fw.h +++ /dev/null @@ -1,61 +0,0 @@ -/****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ - -/*Image2HeaderVersion: 2.16*/ -#if (RTL8822B_SUPPORT == 1) -#ifndef __INC_MP_FW_HW_IMG_8822B_H -#define __INC_MP_FW_HW_IMG_8822B_H - - -/******************************************************************************/ -/* FW_AP.TXT*/ -/******************************************************************************/ - -void -odm_read_firmware_mp_8822b_fw_ap( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_firmware, - u32 *p_firmware_size -); - -/******************************************************************************/ -/* FW_NIC.TXT*/ -/******************************************************************************/ - -void -odm_read_firmware_mp_8822b_fw_nic( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_firmware, - u32 *p_firmware_size -); - -/******************************************************************************/ -/* FW_WoWLAN.TXT*/ -/******************************************************************************/ - -void -odm_read_firmware_mp_8822b_fw_wowlan( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_firmware, - u32 *p_firmware_size -); - -#endif -#endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8822b/halhwimg8822b_mac.c b/hal/phydm/rtl8822b/halhwimg8822b_mac.c index f3212bb..6dde986 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_mac.c +++ b/hal/phydm/rtl8822b/halhwimg8822b_mac.c @@ -1,26 +1,36 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ -/*Image2HeaderVersion: R2 1.2.1*/ +/*Image2HeaderVersion: R3 1.0*/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (RTL8822B_SUPPORT == 1) static boolean check_positive( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, const u32 condition1, const u32 condition2, const u32 condition3, @@ -29,50 +39,51 @@ check_positive( { u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; - u8 cut_version_for_para = (p_dm_odm->cut_version == ODM_CUT_A) ? 15 : p_dm_odm->cut_version; - u8 pkg_type_for_para = (p_dm_odm->package_type == 0) ? 15 : p_dm_odm->package_type; + u8 cut_version_for_para = (dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version; + u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; u32 driver1 = cut_version_for_para << 24 | - (p_dm_odm->support_interface & 0xF0) << 16 | - p_dm_odm->support_platform << 16 | + (dm->support_interface & 0xF0) << 16 | + dm->support_platform << 16 | pkg_type_for_para << 12 | - (p_dm_odm->support_interface & 0x0F) << 8 | - p_dm_odm->rfe_type; + (dm->support_interface & 0x0F) << 8 | + dm->rfe_type; - u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 | - (p_dm_odm->type_gpa & 0xFF) << 8 | - (p_dm_odm->type_alna & 0xFF) << 16 | - (p_dm_odm->type_apa & 0xFF) << 24; + u32 driver2 = (dm->type_glna & 0xFF) << 0 | + (dm->type_gpa & 0xFF) << 8 | + (dm->type_alna & 0xFF) << 16 | + (dm->type_apa & 0xFF) << 24; u32 driver3 = 0; - u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 | - (p_dm_odm->type_gpa & 0xFF00) | - (p_dm_odm->type_alna & 0xFF00) << 8 | - (p_dm_odm->type_apa & 0xFF00) << 16; + u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | + (dm->type_gpa & 0xFF00) | + (dm->type_alna & 0xFF00) << 8 | + (dm->type_apa & 0xFF00) << 16; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (RFE, Package) = (0x%X, 0x%X)\n", p_dm_odm->rfe_type, p_dm_odm->package_type)); + PHYDM_DBG(dm, ODM_COMP_INIT, + " (Platform, Interface) = (0x%X, 0x%X)\n", dm->support_platform, dm->support_interface); + PHYDM_DBG(dm, ODM_COMP_INIT, + " (RFE, Package) = (0x%X, 0x%X)\n", dm->rfe_type, dm->package_type); /*============== value Defined Check ===============*/ /*cut version [27:24] need to do value check*/ - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) return false; /*pkg type [15:12] need to do value check*/ - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) return false; + /*interface [11:8] need to do value check*/ + if (((cond1 & 0x00000F00) != 0) && ((cond1 & 0x00000F00) != (driver1 & 0x00000F00))) + return false; /*=============== Bit Defined Check ================*/ /* We don't care [31:28] */ @@ -86,7 +97,7 @@ check_positive( } static boolean check_negative( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, const u32 condition1, const u32 condition2 ) @@ -101,7 +112,7 @@ check_negative( u32 array_mp_8822b_mac_reg[] = { 0x029, 0x000000F9, 0x420, 0x00000080, - 0x421, 0x0000000F, + 0x421, 0x0000001F, 0x428, 0x0000000A, 0x429, 0x00000010, 0x430, 0x00000000, @@ -229,7 +240,7 @@ u32 array_mp_8822b_mac_reg[] = { void odm_read_and_config_mp_8822b_mac_reg( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 i = 0; @@ -240,7 +251,7 @@ odm_read_and_config_mp_8822b_mac_reg( u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_mac_reg\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_mac_reg\n"); while ((i + 1) < array_len) { v1 = array[i]; @@ -252,18 +263,18 @@ odm_read_and_config_mp_8822b_mac_reg( if (c_cond == COND_ENDIF) {/*end*/ is_matched = true; is_skipped = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); } else if (c_cond == COND_ELSE) { /*else*/ is_matched = is_skipped?false:true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); } } else if (v1 & BIT(30)) { /*negative condition*/ if (is_skipped == false) { - if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { is_matched = true; is_skipped = true; } else { @@ -275,7 +286,7 @@ odm_read_and_config_mp_8822b_mac_reg( } } else { if (is_matched) - odm_config_mac_8822b(p_dm_odm, v1, (u8)v2); + odm_config_mac_8822b(dm, v1, (u8)v2); } i = i + 2; } @@ -284,7 +295,7 @@ odm_read_and_config_mp_8822b_mac_reg( u32 odm_get_version_mp_8822b_mac_reg(void) { - return 85; + return 104; } #endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8822b/halhwimg8822b_mac.h b/hal/phydm/rtl8822b/halhwimg8822b_mac.h index 17c9c57..9b5b1b0 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_mac.h +++ b/hal/phydm/rtl8822b/halhwimg8822b_mac.h @@ -1,19 +1,29 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ -/*Image2HeaderVersion: R2 1.2.1*/ +/*Image2HeaderVersion: R3 1.0*/ #if (RTL8822B_SUPPORT == 1) #ifndef __INC_MP_MAC_HW_IMG_8822B_H #define __INC_MP_MAC_HW_IMG_8822B_H @@ -25,7 +35,7 @@ void odm_read_and_config_mp_8822b_mac_reg(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_mac_reg(void); diff --git a/hal/phydm/rtl8822b/halhwimg8822b_rf.c b/hal/phydm/rtl8822b/halhwimg8822b_rf.c index 0228bde..e0b63b6 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_rf.c +++ b/hal/phydm/rtl8822b/halhwimg8822b_rf.c @@ -1,26 +1,36 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1*/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*Image2HeaderVersion: R3 1.0*/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (RTL8822B_SUPPORT == 1) static boolean check_positive( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, const u32 condition1, const u32 condition2, const u32 condition3, @@ -29,50 +39,51 @@ check_positive( { u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; - u8 cut_version_for_para = (p_dm_odm->cut_version == ODM_CUT_A) ? 15 : p_dm_odm->cut_version; - u8 pkg_type_for_para = (p_dm_odm->package_type == 0) ? 15 : p_dm_odm->package_type; + u8 cut_version_for_para = (dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version; + u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; u32 driver1 = cut_version_for_para << 24 | - (p_dm_odm->support_interface & 0xF0) << 16 | - p_dm_odm->support_platform << 16 | + (dm->support_interface & 0xF0) << 16 | + dm->support_platform << 16 | pkg_type_for_para << 12 | - (p_dm_odm->support_interface & 0x0F) << 8 | - p_dm_odm->rfe_type; + (dm->support_interface & 0x0F) << 8 | + dm->rfe_type; - u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 | - (p_dm_odm->type_gpa & 0xFF) << 8 | - (p_dm_odm->type_alna & 0xFF) << 16 | - (p_dm_odm->type_apa & 0xFF) << 24; + u32 driver2 = (dm->type_glna & 0xFF) << 0 | + (dm->type_gpa & 0xFF) << 8 | + (dm->type_alna & 0xFF) << 16 | + (dm->type_apa & 0xFF) << 24; u32 driver3 = 0; - u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 | - (p_dm_odm->type_gpa & 0xFF00) | - (p_dm_odm->type_alna & 0xFF00) << 8 | - (p_dm_odm->type_apa & 0xFF00) << 16; + u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | + (dm->type_gpa & 0xFF00) | + (dm->type_alna & 0xFF00) << 8 | + (dm->type_apa & 0xFF00) << 16; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (RFE, Package) = (0x%X, 0x%X)\n", p_dm_odm->rfe_type, p_dm_odm->package_type)); + PHYDM_DBG(dm, ODM_COMP_INIT, + " (Platform, Interface) = (0x%X, 0x%X)\n", dm->support_platform, dm->support_interface); + PHYDM_DBG(dm, ODM_COMP_INIT, + " (RFE, Package) = (0x%X, 0x%X)\n", dm->rfe_type, dm->package_type); /*============== value Defined Check ===============*/ /*cut version [27:24] need to do value check*/ - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) return false; /*pkg type [15:12] need to do value check*/ - if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) return false; + /*interface [11:8] need to do value check*/ + if (((cond1 & 0x00000F00) != 0) && ((cond1 & 0x00000F00) != (driver1 & 0x00000F00))) + return false; /*=============== Bit Defined Check ================*/ /* We don't care [31:28] */ @@ -86,7 +97,7 @@ check_positive( } static boolean check_negative( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, const u32 condition1, const u32 condition2 ) @@ -124,6 +135,12 @@ u32 array_mp_8822b_radioa[] = { 0x001, 0x00040029, 0x9300000c, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x00040029, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x0004002D, 0x90000002, 0x00000000, 0x40000000, 0x00000000, @@ -200,6 +217,12 @@ u32 array_mp_8822b_radioa[] = { 0x0B0, 0x000FF0F8, 0x9300000e, 0x00000000, 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FB0F8, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x90000002, 0x00000000, 0x40000000, 0x00000000, @@ -376,9 +399,15 @@ u32 array_mp_8822b_radioa[] = { 0x9300000c, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C0006, 0x9300000d, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000DFF86, - 0x9300000e, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000DFF86, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x90000002, 0x00000000, 0x40000000, 0x00000000, @@ -595,6 +624,12 @@ u32 array_mp_8822b_radioa[] = { 0x03F, 0x000C3186, 0x9300000e, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x90000002, 0x00000000, 0x40000000, 0x00000000, @@ -696,9 +731,15 @@ u32 array_mp_8822b_radioa[] = { 0x9300000c, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C0006, 0x9300000d, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000C3186, + 0x03F, 0x000DFF86, 0x9300000e, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0006, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x90000002, 0x00000000, 0x40000000, 0x00000000, @@ -768,6 +809,12 @@ u32 array_mp_8822b_radioa[] = { 0x03F, 0x00000005, 0x9300000e, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00000005, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x90000002, 0x00000000, 0x40000000, 0x00000000, @@ -944,6 +991,18 @@ u32 array_mp_8822b_radioa[] = { 0x061, 0x0005D3D1, 0x062, 0x0000D3A2, 0x063, 0x00000002, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D301, + 0x062, 0x0000D303, + 0x063, 0x00000002, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D301, + 0x062, 0x0000D303, + 0x063, 0x00000002, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D301, + 0x062, 0x0000D303, + 0x063, 0x00000002, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203, @@ -1062,10 +1121,10 @@ u32 array_mp_8822b_radioa[] = { 0x030, 0x00005355, 0x030, 0x00006355, 0x030, 0x00007355, - 0x030, 0x00008314, - 0x030, 0x00009314, - 0x030, 0x0000A314, - 0x030, 0x0000B314, + 0x030, 0x00008315, + 0x030, 0x00009315, + 0x030, 0x0000A315, + 0x030, 0x0000B315, 0x0EF, 0x00000000, 0x93000006, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200, @@ -1178,10 +1237,10 @@ u32 array_mp_8822b_radioa[] = { 0x030, 0x00001443, 0x030, 0x00002443, 0x030, 0x00003443, - 0x030, 0x00004383, - 0x030, 0x00005383, - 0x030, 0x00006383, - 0x030, 0x00007383, + 0x030, 0x00004483, + 0x030, 0x00005483, + 0x030, 0x00006483, + 0x030, 0x00007483, 0x030, 0x000084A4, 0x030, 0x000094A4, 0x030, 0x0000A4A4, @@ -1189,18 +1248,63 @@ u32 array_mp_8822b_radioa[] = { 0x0EF, 0x00000000, 0x9300000e, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200, - 0x030, 0x00000363, - 0x030, 0x00001363, - 0x030, 0x00002363, - 0x030, 0x00003363, - 0x030, 0x000043A3, - 0x030, 0x000053A3, - 0x030, 0x000063A3, - 0x030, 0x000073A3, - 0x030, 0x000084A4, - 0x030, 0x000094A4, - 0x030, 0x0000A4A4, - 0x030, 0x0000B4A4, + 0x030, 0x00000361, + 0x030, 0x00001361, + 0x030, 0x00002361, + 0x030, 0x00003361, + 0x030, 0x00004443, + 0x030, 0x00005443, + 0x030, 0x00006443, + 0x030, 0x00007443, + 0x030, 0x00008424, + 0x030, 0x00009424, + 0x030, 0x0000A424, + 0x030, 0x0000B424, + 0x0EF, 0x00000000, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x00000334, + 0x030, 0x00001334, + 0x030, 0x00002334, + 0x030, 0x00003334, + 0x030, 0x000043A4, + 0x030, 0x000053A4, + 0x030, 0x000063A4, + 0x030, 0x000073A4, + 0x030, 0x00008365, + 0x030, 0x00009365, + 0x030, 0x0000A365, + 0x030, 0x0000B365, + 0x0EF, 0x00000000, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x00000403, + 0x030, 0x00001403, + 0x030, 0x00002403, + 0x030, 0x00003403, + 0x030, 0x000044A2, + 0x030, 0x000054A2, + 0x030, 0x000064A2, + 0x030, 0x000074A2, + 0x030, 0x000083A3, + 0x030, 0x000093A3, + 0x030, 0x0000A3A3, + 0x030, 0x0000B3A3, + 0x0EF, 0x00000000, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x000003A3, + 0x030, 0x000013A3, + 0x030, 0x000023A3, + 0x030, 0x000033A3, + 0x030, 0x000043A4, + 0x030, 0x000053A4, + 0x030, 0x000063A4, + 0x030, 0x000073A4, + 0x030, 0x00008365, + 0x030, 0x00009365, + 0x030, 0x0000A365, + 0x030, 0x0000B365, 0x0EF, 0x00000000, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200, @@ -1533,6 +1637,48 @@ u32 array_mp_8822b_radioa[] = { 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000080, 0x030, 0x00000203, @@ -1691,7 +1837,7 @@ u32 array_mp_8822b_radioa[] = { 0x0EF, 0x00000040, 0x030, 0x00000776, 0x030, 0x00001455, - 0x030, 0x00002325, + 0x030, 0x00002335, 0x030, 0x00004777, 0x030, 0x00005777, 0x030, 0x00006777, @@ -1753,7 +1899,7 @@ u32 array_mp_8822b_radioa[] = { 0x030, 0x00006777, 0x9300000d, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000040, - 0x030, 0x00000767, + 0x030, 0x00000765, 0x030, 0x00001632, 0x030, 0x00002451, 0x030, 0x00004000, @@ -1767,6 +1913,30 @@ u32 array_mp_8822b_radioa[] = { 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000777, + 0x030, 0x00001454, + 0x030, 0x00002224, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000777, + 0x030, 0x00001442, + 0x030, 0x00002222, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000777, + 0x030, 0x00001442, + 0x030, 0x00002222, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645, @@ -1892,7 +2062,7 @@ u32 array_mp_8822b_radioa[] = { 0x033, 0x00000024, 0x03F, 0x0000002B, 0x033, 0x00000025, - 0x03F, 0x00000068, + 0x03F, 0x0000002E, 0x033, 0x00000026, 0x03F, 0x0000006B, 0x033, 0x00000027, @@ -1915,13 +2085,13 @@ u32 array_mp_8822b_radioa[] = { 0x033, 0x00000024, 0x03F, 0x00000C4B, 0x033, 0x00000025, - 0x03F, 0x00000C8A, + 0x03F, 0x00000C6C, 0x033, 0x00000026, - 0x03F, 0x00000CEA, + 0x03F, 0x00000C8D, 0x033, 0x00000027, - 0x03F, 0x00000CED, + 0x03F, 0x00000CAF, 0x033, 0x00000028, - 0x03F, 0x00000CF0, + 0x03F, 0x00000CD1, 0x033, 0x00000029, 0x03F, 0x00000CF3, 0x033, 0x0000002A, @@ -1938,7 +2108,7 @@ u32 array_mp_8822b_radioa[] = { 0x033, 0x00000024, 0x03F, 0x0000002B, 0x033, 0x00000025, - 0x03F, 0x00000068, + 0x03F, 0x0000002E, 0x033, 0x00000026, 0x03F, 0x0000006B, 0x033, 0x00000027, @@ -1961,9 +2131,9 @@ u32 array_mp_8822b_radioa[] = { 0x033, 0x00000024, 0x03F, 0x00000C4C, 0x033, 0x00000025, - 0x03F, 0x00000CA9, + 0x03F, 0x00000C6C, 0x033, 0x00000026, - 0x03F, 0x00000CEA, + 0x03F, 0x00000CAC, 0x033, 0x00000027, 0x03F, 0x00000CED, 0x033, 0x00000028, @@ -2135,21 +2305,21 @@ u32 array_mp_8822b_radioa[] = { 0x03F, 0x00000CF4, 0x9300000d, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, - 0x03F, 0x00000C0A, + 0x03F, 0x00000C0B, 0x033, 0x00000021, - 0x03F, 0x00000C0D, + 0x03F, 0x00000C0E, 0x033, 0x00000022, - 0x03F, 0x00000C2A, + 0x03F, 0x00000C2B, 0x033, 0x00000023, - 0x03F, 0x00000C2D, + 0x03F, 0x00000C2E, 0x033, 0x00000024, - 0x03F, 0x00000C6A, + 0x03F, 0x00000C89, 0x033, 0x00000025, - 0x03F, 0x00000CAA, + 0x03F, 0x00000CE8, 0x033, 0x00000026, - 0x03F, 0x00000CAD, + 0x03F, 0x00000CEB, 0x033, 0x00000027, - 0x03F, 0x00000CB0, + 0x03F, 0x00000CEE, 0x033, 0x00000028, 0x03F, 0x00000CF1, 0x033, 0x00000029, @@ -2179,6 +2349,75 @@ u32 array_mp_8822b_radioa[] = { 0x03F, 0x00000CF2, 0x033, 0x0000002A, 0x03F, 0x00000CF5, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000429, + 0x033, 0x00000021, + 0x03F, 0x00000828, + 0x033, 0x00000022, + 0x03F, 0x00000847, + 0x033, 0x00000023, + 0x03F, 0x0000084A, + 0x033, 0x00000024, + 0x03F, 0x0000086A, + 0x033, 0x00000025, + 0x03F, 0x0000086D, + 0x033, 0x00000026, + 0x03F, 0x00000870, + 0x033, 0x00000027, + 0x03F, 0x00000891, + 0x033, 0x00000028, + 0x03F, 0x00000894, + 0x033, 0x00000029, + 0x03F, 0x000008B5, + 0x033, 0x0000002A, + 0x03F, 0x000008F5, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000429, + 0x033, 0x00000021, + 0x03F, 0x00000828, + 0x033, 0x00000022, + 0x03F, 0x00000847, + 0x033, 0x00000023, + 0x03F, 0x0000084A, + 0x033, 0x00000024, + 0x03F, 0x00000C4B, + 0x033, 0x00000025, + 0x03F, 0x00000C6C, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000CAF, + 0x033, 0x00000028, + 0x03F, 0x00000CD1, + 0x033, 0x00000029, + 0x03F, 0x00000CF3, + 0x033, 0x0000002A, + 0x03F, 0x00000CF6, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000429, + 0x033, 0x00000021, + 0x03F, 0x00000828, + 0x033, 0x00000022, + 0x03F, 0x00000847, + 0x033, 0x00000023, + 0x03F, 0x0000084A, + 0x033, 0x00000024, + 0x03F, 0x00000C4B, + 0x033, 0x00000025, + 0x03F, 0x00000C6C, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000CAF, + 0x033, 0x00000028, + 0x03F, 0x00000CD1, + 0x033, 0x00000029, + 0x03F, 0x00000CF3, + 0x033, 0x0000002A, + 0x03F, 0x00000CF6, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, 0x03F, 0x00000007, @@ -2422,7 +2661,7 @@ u32 array_mp_8822b_radioa[] = { 0x033, 0x00000064, 0x03F, 0x0000002B, 0x033, 0x00000065, - 0x03F, 0x00000068, + 0x03F, 0x0000002E, 0x033, 0x00000066, 0x03F, 0x0000006B, 0x033, 0x00000067, @@ -2445,13 +2684,13 @@ u32 array_mp_8822b_radioa[] = { 0x033, 0x00000064, 0x03F, 0x00000C4B, 0x033, 0x00000065, - 0x03F, 0x00000C8A, + 0x03F, 0x00000C6C, 0x033, 0x00000066, - 0x03F, 0x00000CEA, + 0x03F, 0x00000C8D, 0x033, 0x00000067, - 0x03F, 0x00000CED, + 0x03F, 0x00000CAF, 0x033, 0x00000068, - 0x03F, 0x00000CF0, + 0x03F, 0x00000CD1, 0x033, 0x00000069, 0x03F, 0x00000CF3, 0x033, 0x0000006A, @@ -2468,7 +2707,7 @@ u32 array_mp_8822b_radioa[] = { 0x033, 0x00000064, 0x03F, 0x0000002B, 0x033, 0x00000065, - 0x03F, 0x00000068, + 0x03F, 0x0000002E, 0x033, 0x00000066, 0x03F, 0x0000006B, 0x033, 0x00000067, @@ -2481,19 +2720,19 @@ u32 array_mp_8822b_radioa[] = { 0x03F, 0x00000077, 0x93000005, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060, - 0x03F, 0x0000042B, + 0x03F, 0x0000042A, 0x033, 0x00000061, - 0x03F, 0x0000082A, + 0x03F, 0x00000829, 0x033, 0x00000062, - 0x03F, 0x00000849, + 0x03F, 0x00000848, 0x033, 0x00000063, - 0x03F, 0x0000084C, + 0x03F, 0x0000084B, 0x033, 0x00000064, - 0x03F, 0x00000C4C, + 0x03F, 0x00000C4B, 0x033, 0x00000065, - 0x03F, 0x00000CA9, + 0x03F, 0x00000C6C, 0x033, 0x00000066, - 0x03F, 0x00000CEA, + 0x03F, 0x00000CAC, 0x033, 0x00000067, 0x03F, 0x00000CED, 0x033, 0x00000068, @@ -2669,17 +2908,17 @@ u32 array_mp_8822b_radioa[] = { 0x033, 0x00000061, 0x03F, 0x00000C0D, 0x033, 0x00000062, - 0x03F, 0x00000C2A, + 0x03F, 0x00000C10, 0x033, 0x00000063, - 0x03F, 0x00000C2D, + 0x03F, 0x00000C4A, 0x033, 0x00000064, - 0x03F, 0x00000C6A, + 0x03F, 0x00000C4D, 0x033, 0x00000065, - 0x03F, 0x00000CAA, + 0x03F, 0x00000CC9, 0x033, 0x00000066, - 0x03F, 0x00000CAD, + 0x03F, 0x00000CEB, 0x033, 0x00000067, - 0x03F, 0x00000CB0, + 0x03F, 0x00000CEE, 0x033, 0x00000068, 0x03F, 0x00000CF1, 0x033, 0x00000069, @@ -2709,32 +2948,101 @@ u32 array_mp_8822b_radioa[] = { 0x03F, 0x00000CF4, 0x033, 0x0000006A, 0x03F, 0x00000CF7, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060, - 0x03F, 0x00000007, + 0x03F, 0x00000429, 0x033, 0x00000061, - 0x03F, 0x0000000A, + 0x03F, 0x00000828, 0x033, 0x00000062, - 0x03F, 0x0000000D, + 0x03F, 0x00000847, 0x033, 0x00000063, - 0x03F, 0x0000002A, + 0x03F, 0x0000084A, 0x033, 0x00000064, - 0x03F, 0x0000002D, + 0x03F, 0x0000086A, 0x033, 0x00000065, - 0x03F, 0x00000030, + 0x03F, 0x0000086D, 0x033, 0x00000066, - 0x03F, 0x0000006D, + 0x03F, 0x00000870, 0x033, 0x00000067, - 0x03F, 0x00000070, + 0x03F, 0x00000891, 0x033, 0x00000068, - 0x03F, 0x000000ED, + 0x03F, 0x00000894, 0x033, 0x00000069, - 0x03F, 0x000000F0, + 0x03F, 0x000008B5, 0x033, 0x0000006A, - 0x03F, 0x000000F3, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000008F5, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060, - 0x03F, 0x00000005, + 0x03F, 0x00000429, + 0x033, 0x00000061, + 0x03F, 0x00000828, + 0x033, 0x00000062, + 0x03F, 0x00000847, + 0x033, 0x00000063, + 0x03F, 0x0000084A, + 0x033, 0x00000064, + 0x03F, 0x00000C4B, + 0x033, 0x00000065, + 0x03F, 0x00000C6C, + 0x033, 0x00000066, + 0x03F, 0x00000C8D, + 0x033, 0x00000067, + 0x03F, 0x00000CAF, + 0x033, 0x00000068, + 0x03F, 0x00000CD1, + 0x033, 0x00000069, + 0x03F, 0x00000CF3, + 0x033, 0x0000006A, + 0x03F, 0x00000CF6, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000429, + 0x033, 0x00000061, + 0x03F, 0x00000828, + 0x033, 0x00000062, + 0x03F, 0x00000847, + 0x033, 0x00000063, + 0x03F, 0x0000084A, + 0x033, 0x00000064, + 0x03F, 0x00000C4B, + 0x033, 0x00000065, + 0x03F, 0x00000C6C, + 0x033, 0x00000066, + 0x03F, 0x00000C8D, + 0x033, 0x00000067, + 0x03F, 0x00000CAF, + 0x033, 0x00000068, + 0x03F, 0x00000CD1, + 0x033, 0x00000069, + 0x03F, 0x00000CF3, + 0x033, 0x0000006A, + 0x03F, 0x00000CF6, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000007, + 0x033, 0x00000061, + 0x03F, 0x0000000A, + 0x033, 0x00000062, + 0x03F, 0x0000000D, + 0x033, 0x00000063, + 0x03F, 0x0000002A, + 0x033, 0x00000064, + 0x03F, 0x0000002D, + 0x033, 0x00000065, + 0x03F, 0x00000030, + 0x033, 0x00000066, + 0x03F, 0x0000006D, + 0x033, 0x00000067, + 0x03F, 0x00000070, + 0x033, 0x00000068, + 0x03F, 0x000000ED, + 0x033, 0x00000069, + 0x03F, 0x000000F0, + 0x033, 0x0000006A, + 0x03F, 0x000000F3, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000005, 0x033, 0x00000061, 0x03F, 0x00000008, 0x033, 0x00000062, @@ -2950,19 +3258,19 @@ u32 array_mp_8822b_radioa[] = { 0x033, 0x000000A3, 0x03F, 0x0000000E, 0x033, 0x000000A4, - 0x03F, 0x00000047, + 0x03F, 0x0000002B, 0x033, 0x000000A5, - 0x03F, 0x0000004A, + 0x03F, 0x0000002E, 0x033, 0x000000A6, - 0x03F, 0x0000004D, + 0x03F, 0x00000031, 0x033, 0x000000A7, - 0x03F, 0x00000050, + 0x03F, 0x00000034, 0x033, 0x000000A8, 0x03F, 0x00000053, 0x033, 0x000000A9, 0x03F, 0x00000056, 0x033, 0x000000AA, - 0x03F, 0x00000094, + 0x03F, 0x000000D1, 0x93000003, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x00000429, @@ -2975,13 +3283,13 @@ u32 array_mp_8822b_radioa[] = { 0x033, 0x000000A4, 0x03F, 0x00000C4B, 0x033, 0x000000A5, - 0x03F, 0x00000C8A, + 0x03F, 0x00000C6C, 0x033, 0x000000A6, - 0x03F, 0x00000CEA, + 0x03F, 0x00000C8D, 0x033, 0x000000A7, - 0x03F, 0x00000CED, + 0x03F, 0x00000CAF, 0x033, 0x000000A8, - 0x03F, 0x00000CF0, + 0x03F, 0x00000CD1, 0x033, 0x000000A9, 0x03F, 0x00000CF3, 0x033, 0x000000AA, @@ -2996,34 +3304,34 @@ u32 array_mp_8822b_radioa[] = { 0x033, 0x000000A3, 0x03F, 0x0000000E, 0x033, 0x000000A4, - 0x03F, 0x00000047, + 0x03F, 0x0000002B, 0x033, 0x000000A5, - 0x03F, 0x0000004A, + 0x03F, 0x0000002E, 0x033, 0x000000A6, - 0x03F, 0x0000004D, + 0x03F, 0x00000031, 0x033, 0x000000A7, - 0x03F, 0x00000050, + 0x03F, 0x00000034, 0x033, 0x000000A8, 0x03F, 0x00000053, 0x033, 0x000000A9, 0x03F, 0x00000056, 0x033, 0x000000AA, - 0x03F, 0x00000094, + 0x03F, 0x000000D1, 0x93000005, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x0000042A, + 0x03F, 0x00000429, 0x033, 0x000000A1, - 0x03F, 0x00000829, + 0x03F, 0x00000828, 0x033, 0x000000A2, - 0x03F, 0x00000848, + 0x03F, 0x00000847, 0x033, 0x000000A3, - 0x03F, 0x0000084B, + 0x03F, 0x0000084A, 0x033, 0x000000A4, - 0x03F, 0x00000C4C, + 0x03F, 0x00000C4B, 0x033, 0x000000A5, - 0x03F, 0x00000CA9, + 0x03F, 0x00000C6C, 0x033, 0x000000A6, - 0x03F, 0x00000CEA, + 0x03F, 0x00000CAC, 0x033, 0x000000A7, 0x03F, 0x00000CED, 0x033, 0x000000A8, @@ -3195,21 +3503,21 @@ u32 array_mp_8822b_radioa[] = { 0x03F, 0x00000CF4, 0x9300000d, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x00000C09, + 0x03F, 0x00000824, 0x033, 0x000000A1, - 0x03F, 0x00000C0C, + 0x03F, 0x00000827, 0x033, 0x000000A2, - 0x03F, 0x00000C0F, + 0x03F, 0x0000082A, 0x033, 0x000000A3, - 0x03F, 0x00000C2C, + 0x03F, 0x0000082D, 0x033, 0x000000A4, - 0x03F, 0x00000C2F, + 0x03F, 0x00000C68, 0x033, 0x000000A5, - 0x03F, 0x00000C8A, + 0x03F, 0x00000C6B, 0x033, 0x000000A6, - 0x03F, 0x00000C8D, + 0x03F, 0x00000CCA, 0x033, 0x000000A7, - 0x03F, 0x00000C90, + 0x03F, 0x00000CCD, 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9, @@ -3218,27 +3526,96 @@ u32 array_mp_8822b_radioa[] = { 0x03F, 0x00000CF5, 0x9300000e, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x00000C09, + 0x03F, 0x00000C08, 0x033, 0x000000A1, - 0x03F, 0x00000C0C, + 0x03F, 0x00000C0B, 0x033, 0x000000A2, - 0x03F, 0x00000C0F, + 0x03F, 0x00000C0E, 0x033, 0x000000A3, - 0x03F, 0x00000C2C, + 0x03F, 0x00000C2B, 0x033, 0x000000A4, - 0x03F, 0x00000C2F, + 0x03F, 0x00000C2E, 0x033, 0x000000A5, - 0x03F, 0x00000C8A, + 0x03F, 0x00000C31, 0x033, 0x000000A6, - 0x03F, 0x00000C8D, + 0x03F, 0x00000CCA, 0x033, 0x000000A7, - 0x03F, 0x00000C90, + 0x03F, 0x00000CCD, 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9, 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000429, + 0x033, 0x000000A1, + 0x03F, 0x00000828, + 0x033, 0x000000A2, + 0x03F, 0x00000847, + 0x033, 0x000000A3, + 0x03F, 0x0000084A, + 0x033, 0x000000A4, + 0x03F, 0x0000086A, + 0x033, 0x000000A5, + 0x03F, 0x0000086D, + 0x033, 0x000000A6, + 0x03F, 0x00000870, + 0x033, 0x000000A7, + 0x03F, 0x00000891, + 0x033, 0x000000A8, + 0x03F, 0x00000894, + 0x033, 0x000000A9, + 0x03F, 0x000008B5, + 0x033, 0x000000AA, + 0x03F, 0x000008F5, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000429, + 0x033, 0x000000A1, + 0x03F, 0x00000828, + 0x033, 0x000000A2, + 0x03F, 0x00000847, + 0x033, 0x000000A3, + 0x03F, 0x0000084A, + 0x033, 0x000000A4, + 0x03F, 0x00000C4B, + 0x033, 0x000000A5, + 0x03F, 0x00000C6C, + 0x033, 0x000000A6, + 0x03F, 0x00000C8D, + 0x033, 0x000000A7, + 0x03F, 0x00000CAF, + 0x033, 0x000000A8, + 0x03F, 0x00000CD1, + 0x033, 0x000000A9, + 0x03F, 0x00000CF3, + 0x033, 0x000000AA, + 0x03F, 0x00000CF6, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000429, + 0x033, 0x000000A1, + 0x03F, 0x00000828, + 0x033, 0x000000A2, + 0x03F, 0x00000847, + 0x033, 0x000000A3, + 0x03F, 0x0000084A, + 0x033, 0x000000A4, + 0x03F, 0x00000C4B, + 0x033, 0x000000A5, + 0x03F, 0x00000C6C, + 0x033, 0x000000A6, + 0x03F, 0x00000C8D, + 0x033, 0x000000A7, + 0x03F, 0x00000CAF, + 0x033, 0x000000A8, + 0x03F, 0x00000CD1, + 0x033, 0x000000A9, + 0x03F, 0x00000CF3, + 0x033, 0x000000AA, + 0x03F, 0x00000CF6, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x00000007, @@ -3973,18 +4350,87 @@ u32 array_mp_8822b_radioa[] = { 0x03E, 0x00005934, 0x03F, 0x0005AFCF, 0x0EF, 0x00000000, - 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x83000002, 0x00000000, 0x40000000, 0x00000000, + 0x0CE, 0x00094400, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x0CE, 0x00094400, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x0CE, 0x00094400, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x0CE, 0x00094400, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x0CE, 0x00094400, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x0CE, 0x00094400, + 0xA0000000, 0x00000000, + 0x0CE, 0x00094C00, + 0xB0000000, 0x00000000, + 0x83000002, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00072F00, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00072F00, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00072F00, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00072F00, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, 0x0CF, 0x00064700, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00072F00, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x0CF, 0x00072F00, 0xA0000000, 0x00000000, 0x0CF, 0x00064700, 0xB0000000, 0x00000000, - 0x8300000c, 0x00000000, 0x40000000, 0x00000000, + 0x83000002, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000056, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0x93000003, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000056, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0x93000004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000056, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0x93000005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000056, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, + 0x9300000c, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000004, 0x033, 0x00000000, 0x03F, 0x00000096, 0x033, 0x00000001, 0x03F, 0x000000D6, 0x0EF, 0x00000000, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000056, + 0x033, 0x00000001, + 0x03F, 0x00000056, + 0x0EF, 0x00000000, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000004, + 0x033, 0x00000000, + 0x03F, 0x00000056, + 0x033, 0x00000001, + 0x03F, 0x000000D6, + 0x0EF, 0x00000000, 0xA0000000, 0x00000000, 0x0EF, 0x00000000, 0x033, 0x00000000, @@ -3995,13 +4441,13 @@ u32 array_mp_8822b_radioa[] = { 0xB0000000, 0x00000000, 0x0B0, 0x000FF0FC, 0x0C4, 0x00081402, - 0x0CC, 0x00080000, + 0x0CC, 0x00082000, }; void odm_read_and_config_mp_8822b_radioa( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 i = 0; @@ -4012,7 +4458,7 @@ odm_read_and_config_mp_8822b_radioa( u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_radioa\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_radioa\n"); while ((i + 1) < array_len) { v1 = array[i]; @@ -4024,18 +4470,18 @@ odm_read_and_config_mp_8822b_radioa( if (c_cond == COND_ENDIF) {/*end*/ is_matched = true; is_skipped = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); } else if (c_cond == COND_ELSE) { /*else*/ is_matched = is_skipped?false:true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); } } else if (v1 & BIT(30)) { /*negative condition*/ if (is_skipped == false) { - if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { is_matched = true; is_skipped = true; } else { @@ -4047,7 +4493,7 @@ odm_read_and_config_mp_8822b_radioa( } } else { if (is_matched) - odm_config_rf_radio_a_8822b(p_dm_odm, v1, v2); + odm_config_rf_radio_a_8822b(dm, v1, v2); } i = i + 2; } @@ -4056,7 +4502,7 @@ odm_read_and_config_mp_8822b_radioa( u32 odm_get_version_mp_8822b_radioa(void) { - return 85; + return 104; } /****************************************************************************** @@ -4089,6 +4535,12 @@ u32 array_mp_8822b_radiob[] = { 0x001, 0x0004002D, 0x9300000c, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x00040029, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x001, 0x00040029, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x001, 0x0004002D, 0x90000002, 0x00000000, 0x40000000, 0x00000000, @@ -4186,7 +4638,7 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x000C3186, 0x93000008, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000, - 0x03F, 0x000C3186, + 0x03F, 0x000C0006, 0x93000009, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x03F, 0x000C3186, @@ -4201,10 +4653,19 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x000C0006, 0x9300000d, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000, - 0x03F, 0x000DFF86, + 0x03F, 0x000C3186, 0x9300000e, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x03F, 0x000C3186, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x03F, 0x000C3186, @@ -4272,7 +4733,7 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x000C3186, 0x93000008, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000, - 0x03F, 0x000C3186, + 0x03F, 0x000C0006, 0x93000009, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x03F, 0x000C3186, @@ -4291,6 +4752,15 @@ u32 array_mp_8822b_radiob[] = { 0x9300000e, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x03F, 0x000C3186, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x03F, 0x000C3186, @@ -4314,7 +4784,11 @@ u32 array_mp_8822b_radiob[] = { 0x03E, 0x00004080, 0x03F, 0x000C3186, 0x033, 0x0000000D, + 0x8300000f, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000040D0, + 0xA0000000, 0x00000000, 0x03E, 0x000040C8, + 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x0000000C, 0x03E, 0x00004190, @@ -4373,10 +4847,19 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x000C0006, 0x9300000d, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000, - 0x03F, 0x000C3186, + 0x03F, 0x000DFF86, 0x9300000e, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x03F, 0x000C3186, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00004000, + 0x03F, 0x000C0006, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x03F, 0x000C3186, @@ -4400,7 +4883,11 @@ u32 array_mp_8822b_radiob[] = { 0x03E, 0x00004080, 0x03F, 0x000C3186, 0x033, 0x00000015, + 0x8300000f, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000040D0, + 0xA0000000, 0x00000000, 0x03E, 0x000040C8, + 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000014, 0x03E, 0x00004190, @@ -4452,6 +4939,12 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x00000005, 0x9300000e, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00000005, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x90000002, 0x00000000, 0x40000000, 0x00000000, @@ -4617,10 +5110,22 @@ u32 array_mp_8822b_radiob[] = { 0x061, 0x0005D3D1, 0x062, 0x0000D3A2, 0x063, 0x00000002, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, - 0x061, 0x0005D4A0, - 0x062, 0x0000D203, - 0x063, 0x00000062, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D2A1, + 0x062, 0x0000D3A2, + 0x063, 0x00000002, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0005D4A0, + 0x062, 0x0000D203, + 0x063, 0x00000062, 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, @@ -4821,31 +5326,70 @@ u32 array_mp_8822b_radiob[] = { 0x030, 0x0000A365, 0x030, 0x0000B365, 0x9300000d, 0x00000000, 0x40000000, 0x00000000, - 0x030, 0x00000443, - 0x030, 0x00001443, - 0x030, 0x00002443, - 0x030, 0x00003443, - 0x030, 0x00004383, - 0x030, 0x00005383, - 0x030, 0x00006383, - 0x030, 0x00007383, - 0x030, 0x000084A4, - 0x030, 0x000094A4, - 0x030, 0x0000A4A4, - 0x030, 0x0000B4A4, - 0x9300000e, 0x00000000, 0x40000000, 0x00000000, - 0x030, 0x00000363, - 0x030, 0x00001363, - 0x030, 0x00002363, - 0x030, 0x00003363, - 0x030, 0x000043A3, - 0x030, 0x000053A3, - 0x030, 0x000063A3, - 0x030, 0x000073A3, + 0x030, 0x00000343, + 0x030, 0x00001343, + 0x030, 0x00002343, + 0x030, 0x00003343, + 0x030, 0x00004483, + 0x030, 0x00005483, + 0x030, 0x00006483, + 0x030, 0x00007483, 0x030, 0x000083A4, 0x030, 0x000093A4, 0x030, 0x0000A3A4, 0x030, 0x0000B3A4, + 0x9300000e, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x00004423, + 0x030, 0x00005423, + 0x030, 0x00006423, + 0x030, 0x00007423, + 0x030, 0x00008324, + 0x030, 0x00009324, + 0x030, 0x0000A324, + 0x030, 0x0000B324, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000303, + 0x030, 0x00001303, + 0x030, 0x00002303, + 0x030, 0x00003303, + 0x030, 0x000043A4, + 0x030, 0x000053A4, + 0x030, 0x000063A4, + 0x030, 0x000073A4, + 0x030, 0x00008365, + 0x030, 0x00009365, + 0x030, 0x0000A365, + 0x030, 0x0000B365, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000403, + 0x030, 0x00001403, + 0x030, 0x00002403, + 0x030, 0x00003403, + 0x030, 0x000043A4, + 0x030, 0x000053A4, + 0x030, 0x000063A4, + 0x030, 0x000073A4, + 0x030, 0x000083A3, + 0x030, 0x000093A3, + 0x030, 0x0000A3A3, + 0x030, 0x0000B3A3, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A3, + 0x030, 0x000013A3, + 0x030, 0x000023A3, + 0x030, 0x000033A3, + 0x030, 0x000043A4, + 0x030, 0x000053A4, + 0x030, 0x000063A4, + 0x030, 0x000073A4, + 0x030, 0x00008365, + 0x030, 0x00009365, + 0x030, 0x0000A365, + 0x030, 0x0000B365, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000004A0, 0x030, 0x000014A0, @@ -5148,6 +5692,45 @@ u32 array_mp_8822b_radiob[] = { 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x000003A2, + 0x030, 0x000013A2, + 0x030, 0x000023A2, + 0x030, 0x000033A2, + 0x030, 0x000043A2, + 0x030, 0x000053A2, + 0x030, 0x000063A2, + 0x030, 0x000073A2, + 0x030, 0x000083A2, + 0x030, 0x000093A2, + 0x030, 0x0000A3A2, + 0x030, 0x0000B3A2, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000203, 0x030, 0x00001203, @@ -5347,7 +5930,7 @@ u32 array_mp_8822b_radiob[] = { 0x030, 0x00005777, 0x030, 0x00006777, 0x9300000d, 0x00000000, 0x40000000, 0x00000000, - 0x030, 0x00000767, + 0x030, 0x00000765, 0x030, 0x00001632, 0x030, 0x00002451, 0x030, 0x00004000, @@ -5360,6 +5943,27 @@ u32 array_mp_8822b_radiob[] = { 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000777, + 0x030, 0x00001442, + 0x030, 0x00002222, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000776, + 0x030, 0x00001442, + 0x030, 0x00002222, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000777, + 0x030, 0x00001442, + 0x030, 0x00002222, + 0x030, 0x00004777, + 0x030, 0x00005777, + 0x030, 0x00006777, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333, @@ -5477,7 +6081,7 @@ u32 array_mp_8822b_radiob[] = { 0x033, 0x00000024, 0x03F, 0x0000002B, 0x033, 0x00000025, - 0x03F, 0x00000068, + 0x03F, 0x0000002E, 0x033, 0x00000026, 0x03F, 0x0000006B, 0x033, 0x00000027, @@ -5500,13 +6104,13 @@ u32 array_mp_8822b_radiob[] = { 0x033, 0x00000024, 0x03F, 0x00000C4B, 0x033, 0x00000025, - 0x03F, 0x00000C8A, + 0x03F, 0x00000C6C, 0x033, 0x00000026, - 0x03F, 0x00000CEA, + 0x03F, 0x00000C8D, 0x033, 0x00000027, - 0x03F, 0x00000CED, + 0x03F, 0x00000CAF, 0x033, 0x00000028, - 0x03F, 0x00000CF0, + 0x03F, 0x00000CD1, 0x033, 0x00000029, 0x03F, 0x00000CF3, 0x033, 0x0000002A, @@ -5523,7 +6127,7 @@ u32 array_mp_8822b_radiob[] = { 0x033, 0x00000024, 0x03F, 0x0000002B, 0x033, 0x00000025, - 0x03F, 0x00000068, + 0x03F, 0x0000002E, 0x033, 0x00000026, 0x03F, 0x0000006B, 0x033, 0x00000027, @@ -5536,19 +6140,19 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x00000077, 0x93000005, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, - 0x03F, 0x0000042A, + 0x03F, 0x0000042C, 0x033, 0x00000021, - 0x03F, 0x00000829, + 0x03F, 0x0000082B, 0x033, 0x00000022, - 0x03F, 0x00000848, + 0x03F, 0x0000084A, 0x033, 0x00000023, - 0x03F, 0x0000084B, + 0x03F, 0x0000084D, 0x033, 0x00000024, - 0x03F, 0x00000C4C, + 0x03F, 0x00000C4E, 0x033, 0x00000025, - 0x03F, 0x00000C8B, + 0x03F, 0x00000C6E, 0x033, 0x00000026, - 0x03F, 0x00000CEA, + 0x03F, 0x00000CAD, 0x033, 0x00000027, 0x03F, 0x00000CED, 0x033, 0x00000028, @@ -5720,21 +6324,21 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x00000CF4, 0x9300000d, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, - 0x03F, 0x00000C0A, + 0x03F, 0x00000C25, 0x033, 0x00000021, - 0x03F, 0x00000C0D, + 0x03F, 0x00000C28, 0x033, 0x00000022, - 0x03F, 0x00000C2A, + 0x03F, 0x00000C2B, 0x033, 0x00000023, - 0x03F, 0x00000C2D, + 0x03F, 0x00000C68, 0x033, 0x00000024, - 0x03F, 0x00000C6A, + 0x03F, 0x00000C6B, 0x033, 0x00000025, - 0x03F, 0x00000CAA, + 0x03F, 0x00000C6E, 0x033, 0x00000026, - 0x03F, 0x00000CAD, + 0x03F, 0x00000CEB, 0x033, 0x00000027, - 0x03F, 0x00000CB0, + 0x03F, 0x00000CEE, 0x033, 0x00000028, 0x03F, 0x00000CF1, 0x033, 0x00000029, @@ -5764,6 +6368,75 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x00000CF2, 0x033, 0x0000002A, 0x03F, 0x00000CF5, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000429, + 0x033, 0x00000021, + 0x03F, 0x00000828, + 0x033, 0x00000022, + 0x03F, 0x00000847, + 0x033, 0x00000023, + 0x03F, 0x0000084A, + 0x033, 0x00000024, + 0x03F, 0x00000C4B, + 0x033, 0x00000025, + 0x03F, 0x00000C8A, + 0x033, 0x00000026, + 0x03F, 0x00000CEA, + 0x033, 0x00000027, + 0x03F, 0x00000CED, + 0x033, 0x00000028, + 0x03F, 0x00000CF0, + 0x033, 0x00000029, + 0x03F, 0x00000CF3, + 0x033, 0x0000002A, + 0x03F, 0x00000CF6, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000429, + 0x033, 0x00000021, + 0x03F, 0x00000828, + 0x033, 0x00000022, + 0x03F, 0x00000847, + 0x033, 0x00000023, + 0x03F, 0x0000084A, + 0x033, 0x00000024, + 0x03F, 0x00000C4B, + 0x033, 0x00000025, + 0x03F, 0x00000C6C, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000CAF, + 0x033, 0x00000028, + 0x03F, 0x00000CD1, + 0x033, 0x00000029, + 0x03F, 0x00000CF3, + 0x033, 0x0000002A, + 0x03F, 0x00000CF6, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000429, + 0x033, 0x00000021, + 0x03F, 0x00000828, + 0x033, 0x00000022, + 0x03F, 0x00000847, + 0x033, 0x00000023, + 0x03F, 0x0000084A, + 0x033, 0x00000024, + 0x03F, 0x00000C4B, + 0x033, 0x00000025, + 0x03F, 0x00000C6C, + 0x033, 0x00000026, + 0x03F, 0x00000C8D, + 0x033, 0x00000027, + 0x03F, 0x00000CAF, + 0x033, 0x00000028, + 0x03F, 0x00000CD1, + 0x033, 0x00000029, + 0x03F, 0x00000CF3, + 0x033, 0x0000002A, + 0x03F, 0x00000CF6, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020, 0x03F, 0x00000007, @@ -6007,7 +6680,7 @@ u32 array_mp_8822b_radiob[] = { 0x033, 0x00000064, 0x03F, 0x0000002B, 0x033, 0x00000065, - 0x03F, 0x00000068, + 0x03F, 0x0000002E, 0x033, 0x00000066, 0x03F, 0x0000006B, 0x033, 0x00000067, @@ -6030,13 +6703,13 @@ u32 array_mp_8822b_radiob[] = { 0x033, 0x00000064, 0x03F, 0x00000C4B, 0x033, 0x00000065, - 0x03F, 0x00000C8A, + 0x03F, 0x00000C6C, 0x033, 0x00000066, - 0x03F, 0x00000CEA, + 0x03F, 0x00000C8D, 0x033, 0x00000067, - 0x03F, 0x00000CED, + 0x03F, 0x00000CAF, 0x033, 0x00000068, - 0x03F, 0x00000CF0, + 0x03F, 0x00000CD1, 0x033, 0x00000069, 0x03F, 0x00000CF3, 0x033, 0x0000006A, @@ -6053,7 +6726,7 @@ u32 array_mp_8822b_radiob[] = { 0x033, 0x00000064, 0x03F, 0x0000002B, 0x033, 0x00000065, - 0x03F, 0x00000068, + 0x03F, 0x0000002E, 0x033, 0x00000066, 0x03F, 0x0000006B, 0x033, 0x00000067, @@ -6074,11 +6747,11 @@ u32 array_mp_8822b_radiob[] = { 0x033, 0x00000063, 0x03F, 0x0000084B, 0x033, 0x00000064, - 0x03F, 0x00000C69, + 0x03F, 0x00000C4B, 0x033, 0x00000065, - 0x03F, 0x00000CA9, + 0x03F, 0x00000C6C, 0x033, 0x00000066, - 0x03F, 0x00000CEA, + 0x03F, 0x00000CAC, 0x033, 0x00000067, 0x03F, 0x00000CED, 0x033, 0x00000068, @@ -6254,17 +6927,17 @@ u32 array_mp_8822b_radiob[] = { 0x033, 0x00000061, 0x03F, 0x00000C0D, 0x033, 0x00000062, - 0x03F, 0x00000C2A, + 0x03F, 0x00000C10, 0x033, 0x00000063, - 0x03F, 0x00000C2D, + 0x03F, 0x00000C4A, 0x033, 0x00000064, - 0x03F, 0x00000C6A, + 0x03F, 0x00000C4D, 0x033, 0x00000065, - 0x03F, 0x00000CAA, + 0x03F, 0x00000CC9, 0x033, 0x00000066, - 0x03F, 0x00000CAD, + 0x03F, 0x00000CEB, 0x033, 0x00000067, - 0x03F, 0x00000CB0, + 0x03F, 0x00000CEE, 0x033, 0x00000068, 0x03F, 0x00000CF1, 0x033, 0x00000069, @@ -6294,30 +6967,99 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x00000CF4, 0x033, 0x0000006A, 0x03F, 0x00000CF7, - 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060, - 0x03F, 0x00000007, + 0x03F, 0x00000429, 0x033, 0x00000061, - 0x03F, 0x0000000A, + 0x03F, 0x00000828, 0x033, 0x00000062, - 0x03F, 0x0000000D, + 0x03F, 0x00000847, 0x033, 0x00000063, - 0x03F, 0x0000002A, + 0x03F, 0x0000084A, 0x033, 0x00000064, - 0x03F, 0x0000002D, + 0x03F, 0x00000C4B, 0x033, 0x00000065, - 0x03F, 0x00000030, + 0x03F, 0x00000C8A, 0x033, 0x00000066, - 0x03F, 0x0000006D, + 0x03F, 0x00000CEA, 0x033, 0x00000067, - 0x03F, 0x00000070, + 0x03F, 0x00000CED, 0x033, 0x00000068, - 0x03F, 0x000000ED, + 0x03F, 0x00000CF0, 0x033, 0x00000069, - 0x03F, 0x000000F0, + 0x03F, 0x00000CF3, 0x033, 0x0000006A, - 0x03F, 0x000000F3, - 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000CF6, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000429, + 0x033, 0x00000061, + 0x03F, 0x00000828, + 0x033, 0x00000062, + 0x03F, 0x00000847, + 0x033, 0x00000063, + 0x03F, 0x0000084A, + 0x033, 0x00000064, + 0x03F, 0x00000C4B, + 0x033, 0x00000065, + 0x03F, 0x00000C6C, + 0x033, 0x00000066, + 0x03F, 0x00000C8D, + 0x033, 0x00000067, + 0x03F, 0x00000CAF, + 0x033, 0x00000068, + 0x03F, 0x00000CD1, + 0x033, 0x00000069, + 0x03F, 0x00000CF3, + 0x033, 0x0000006A, + 0x03F, 0x00000CF6, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000429, + 0x033, 0x00000061, + 0x03F, 0x00000828, + 0x033, 0x00000062, + 0x03F, 0x00000847, + 0x033, 0x00000063, + 0x03F, 0x0000084A, + 0x033, 0x00000064, + 0x03F, 0x00000C4B, + 0x033, 0x00000065, + 0x03F, 0x00000C6C, + 0x033, 0x00000066, + 0x03F, 0x00000C8D, + 0x033, 0x00000067, + 0x03F, 0x00000CAF, + 0x033, 0x00000068, + 0x03F, 0x00000CD1, + 0x033, 0x00000069, + 0x03F, 0x00000CF3, + 0x033, 0x0000006A, + 0x03F, 0x00000CF6, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000007, + 0x033, 0x00000061, + 0x03F, 0x0000000A, + 0x033, 0x00000062, + 0x03F, 0x0000000D, + 0x033, 0x00000063, + 0x03F, 0x0000002A, + 0x033, 0x00000064, + 0x03F, 0x0000002D, + 0x033, 0x00000065, + 0x03F, 0x00000030, + 0x033, 0x00000066, + 0x03F, 0x0000006D, + 0x033, 0x00000067, + 0x03F, 0x00000070, + 0x033, 0x00000068, + 0x03F, 0x000000ED, + 0x033, 0x00000069, + 0x03F, 0x000000F0, + 0x033, 0x0000006A, + 0x03F, 0x000000F3, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060, 0x03F, 0x00000005, 0x033, 0x00000061, @@ -6535,19 +7277,19 @@ u32 array_mp_8822b_radiob[] = { 0x033, 0x000000A3, 0x03F, 0x0000000E, 0x033, 0x000000A4, - 0x03F, 0x00000047, + 0x03F, 0x0000002B, 0x033, 0x000000A5, - 0x03F, 0x0000004A, + 0x03F, 0x0000002E, 0x033, 0x000000A6, - 0x03F, 0x0000004D, + 0x03F, 0x00000031, 0x033, 0x000000A7, - 0x03F, 0x00000050, + 0x03F, 0x00000034, 0x033, 0x000000A8, 0x03F, 0x00000053, 0x033, 0x000000A9, 0x03F, 0x00000056, 0x033, 0x000000AA, - 0x03F, 0x00000094, + 0x03F, 0x000000D1, 0x93000003, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x00000429, @@ -6560,13 +7302,13 @@ u32 array_mp_8822b_radiob[] = { 0x033, 0x000000A4, 0x03F, 0x00000C4B, 0x033, 0x000000A5, - 0x03F, 0x00000C8A, + 0x03F, 0x00000C6C, 0x033, 0x000000A6, - 0x03F, 0x00000CEA, + 0x03F, 0x00000C8D, 0x033, 0x000000A7, - 0x03F, 0x00000CED, + 0x03F, 0x00000CAF, 0x033, 0x000000A8, - 0x03F, 0x00000CF0, + 0x03F, 0x00000CD1, 0x033, 0x000000A9, 0x03F, 0x00000CF3, 0x033, 0x000000AA, @@ -6581,19 +7323,19 @@ u32 array_mp_8822b_radiob[] = { 0x033, 0x000000A3, 0x03F, 0x0000000E, 0x033, 0x000000A4, - 0x03F, 0x00000047, + 0x03F, 0x0000002B, 0x033, 0x000000A5, - 0x03F, 0x0000004A, + 0x03F, 0x0000002E, 0x033, 0x000000A6, - 0x03F, 0x0000004D, + 0x03F, 0x00000031, 0x033, 0x000000A7, - 0x03F, 0x00000050, + 0x03F, 0x00000034, 0x033, 0x000000A8, 0x03F, 0x00000053, 0x033, 0x000000A9, 0x03F, 0x00000056, 0x033, 0x000000AA, - 0x03F, 0x00000094, + 0x03F, 0x000000D1, 0x93000005, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x0000042A, @@ -6606,9 +7348,9 @@ u32 array_mp_8822b_radiob[] = { 0x033, 0x000000A4, 0x03F, 0x00000C4C, 0x033, 0x000000A5, - 0x03F, 0x00000CA9, + 0x03F, 0x00000C6C, 0x033, 0x000000A6, - 0x03F, 0x00000CEA, + 0x03F, 0x00000CAC, 0x033, 0x000000A7, 0x03F, 0x00000CED, 0x033, 0x000000A8, @@ -6780,21 +7522,21 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x00000CF4, 0x9300000d, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x00000C09, + 0x03F, 0x0000080A, 0x033, 0x000000A1, - 0x03F, 0x00000C0C, + 0x03F, 0x0000080D, 0x033, 0x000000A2, - 0x03F, 0x00000C0F, + 0x03F, 0x00000810, 0x033, 0x000000A3, - 0x03F, 0x00000C2C, + 0x03F, 0x00000868, 0x033, 0x000000A4, - 0x03F, 0x00000C2F, + 0x03F, 0x00000C68, 0x033, 0x000000A5, - 0x03F, 0x00000C8A, + 0x03F, 0x00000C6B, 0x033, 0x000000A6, - 0x03F, 0x00000C8D, + 0x03F, 0x00000CAB, 0x033, 0x000000A7, - 0x03F, 0x00000C90, + 0x03F, 0x00000CAE, 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9, @@ -6803,27 +7545,96 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x00000CF5, 0x9300000e, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x03F, 0x00000C09, + 0x03F, 0x00000C08, 0x033, 0x000000A1, - 0x03F, 0x00000C0C, + 0x03F, 0x00000C0B, 0x033, 0x000000A2, - 0x03F, 0x00000C0F, + 0x03F, 0x00000C0E, 0x033, 0x000000A3, - 0x03F, 0x00000C2C, + 0x03F, 0x00000C2B, 0x033, 0x000000A4, - 0x03F, 0x00000C2F, + 0x03F, 0x00000C2E, 0x033, 0x000000A5, - 0x03F, 0x00000C8A, + 0x03F, 0x00000C31, 0x033, 0x000000A6, - 0x03F, 0x00000C8D, + 0x03F, 0x00000CAB, 0x033, 0x000000A7, - 0x03F, 0x00000C90, + 0x03F, 0x00000CAE, 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9, 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000429, + 0x033, 0x000000A1, + 0x03F, 0x00000828, + 0x033, 0x000000A2, + 0x03F, 0x00000847, + 0x033, 0x000000A3, + 0x03F, 0x0000084A, + 0x033, 0x000000A4, + 0x03F, 0x00000C4B, + 0x033, 0x000000A5, + 0x03F, 0x00000C8A, + 0x033, 0x000000A6, + 0x03F, 0x00000CEA, + 0x033, 0x000000A7, + 0x03F, 0x00000CED, + 0x033, 0x000000A8, + 0x03F, 0x00000CF0, + 0x033, 0x000000A9, + 0x03F, 0x00000CF3, + 0x033, 0x000000AA, + 0x03F, 0x00000CF6, + 0x93000010, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000429, + 0x033, 0x000000A1, + 0x03F, 0x00000828, + 0x033, 0x000000A2, + 0x03F, 0x00000847, + 0x033, 0x000000A3, + 0x03F, 0x0000084A, + 0x033, 0x000000A4, + 0x03F, 0x00000C4B, + 0x033, 0x000000A5, + 0x03F, 0x00000C6C, + 0x033, 0x000000A6, + 0x03F, 0x00000C8D, + 0x033, 0x000000A7, + 0x03F, 0x00000CAF, + 0x033, 0x000000A8, + 0x03F, 0x00000CD1, + 0x033, 0x000000A9, + 0x03F, 0x00000CF3, + 0x033, 0x000000AA, + 0x03F, 0x00000CF6, + 0x93000011, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000429, + 0x033, 0x000000A1, + 0x03F, 0x00000828, + 0x033, 0x000000A2, + 0x03F, 0x00000847, + 0x033, 0x000000A3, + 0x03F, 0x0000084A, + 0x033, 0x000000A4, + 0x03F, 0x00000C4B, + 0x033, 0x000000A5, + 0x03F, 0x00000C6C, + 0x033, 0x000000A6, + 0x03F, 0x00000C8D, + 0x033, 0x000000A7, + 0x03F, 0x00000CAF, + 0x033, 0x000000A8, + 0x03F, 0x00000CD1, + 0x033, 0x000000A9, + 0x03F, 0x00000CF3, + 0x033, 0x000000AA, + 0x03F, 0x00000CF6, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x00000007, @@ -7056,6 +7867,15 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x0000265A, 0x033, 0x00000003, 0x03F, 0x0000265A, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x000004FB, + 0x033, 0x00000001, + 0x03F, 0x000004FB, + 0x033, 0x00000002, + 0x03F, 0x000004FB, + 0x033, 0x00000003, + 0x03F, 0x000004FB, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000265A, @@ -7435,6 +8255,29 @@ u32 array_mp_8822b_radiob[] = { 0x03F, 0x00051CF4, 0x033, 0x0000000A, 0x03F, 0x00051CF7, + 0x9300000f, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000000, + 0x03F, 0x0005142C, + 0x033, 0x00000001, + 0x03F, 0x0005144B, + 0x033, 0x00000002, + 0x03F, 0x00051868, + 0x033, 0x00000003, + 0x03F, 0x0005186B, + 0x033, 0x00000004, + 0x03F, 0x0005186E, + 0x033, 0x00000005, + 0x03F, 0x00051871, + 0x033, 0x00000006, + 0x03F, 0x00051874, + 0x033, 0x00000007, + 0x03F, 0x00051895, + 0x033, 0x00000008, + 0x03F, 0x000518B6, + 0x033, 0x00000009, + 0x03F, 0x000518F6, + 0x033, 0x0000000A, + 0x03F, 0x00051CF7, 0x90000001, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003, @@ -7581,7 +8424,7 @@ u32 array_mp_8822b_radiob[] = { void odm_read_and_config_mp_8822b_radiob( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 i = 0; @@ -7592,7 +8435,7 @@ odm_read_and_config_mp_8822b_radiob( u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_radiob\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_radiob\n"); while ((i + 1) < array_len) { v1 = array[i]; @@ -7604,18 +8447,18 @@ odm_read_and_config_mp_8822b_radiob( if (c_cond == COND_ENDIF) {/*end*/ is_matched = true; is_skipped = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); } else if (c_cond == COND_ELSE) { /*else*/ is_matched = is_skipped?false:true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); } } else if (v1 & BIT(30)) { /*negative condition*/ if (is_skipped == false) { - if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { is_matched = true; is_skipped = true; } else { @@ -7627,7 +8470,7 @@ odm_read_and_config_mp_8822b_radiob( } } else { if (is_matched) - odm_config_rf_radio_b_8822b(p_dm_odm, v1, v2); + odm_config_rf_radio_b_8822b(dm, v1, v2); } i = i + 2; } @@ -7636,892 +8479,1069 @@ odm_read_and_config_mp_8822b_radiob( u32 odm_get_version_mp_8822b_radiob(void) { - return 85; + return 104; } /****************************************************************************** * txpowertrack.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20}, {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18}, {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void odm_read_and_config_mp_8822b_txpowertrack( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** * txpowertrack_type0.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type0_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type0_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type0_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type0_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type0_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type0_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type0_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type0_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type0_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type0_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type0_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type0_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type0_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type0_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type0_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type0_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type0_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type0_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type0_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type0_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type0_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type0_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type0_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type0_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void odm_read_and_config_mp_8822b_txpowertrack_type0( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type0_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type0_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type0_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type0_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type0_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type0_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type0_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type0_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** * txpowertrack_type1.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type1_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type1_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type1_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type1_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type1_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type1_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type1_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type1_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20}, {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18}, {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type1_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type1_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type1_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type1_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type1_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type1_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type1_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type1_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type1_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type1_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type1_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type1_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type1_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type1_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type1_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type1_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void odm_read_and_config_mp_8822b_txpowertrack_type1( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type1_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type1_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type1_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type1_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type1_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type1_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type1_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type1_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** * txpowertrack_type10.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type10_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type10_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type10_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type10_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type10_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type10_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type10_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type10_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type10_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type10_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type10_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type10_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type10_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type10_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type10_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type10_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type10_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type10_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type10_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type10_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type10_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type10_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type10_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type10_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void odm_read_and_config_mp_8822b_txpowertrack_type10( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type10_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type10_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type10_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type10_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type10_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type10_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type10_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type10_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** * txpowertrack_type11.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type11_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type11_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type11_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type11_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type11_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type11_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type11_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type11_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type11_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type11_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type11_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type11_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type11_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type11_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type11_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type11_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type11_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type11_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type11_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type11_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type11_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type11_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type11_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type11_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void odm_read_and_config_mp_8822b_txpowertrack_type11( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type11_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type11_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type11_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type11_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type11_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type11_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type11_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type11_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** * txpowertrack_type12.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type12_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type12_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type12_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type12_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type12_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type12_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type12_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type12_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type12_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type12_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type12_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type12_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type12_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type12_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type12_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type12_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type12_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type12_8822b[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type12_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type12_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type12_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type12_8822b[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type12_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type12_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; void odm_read_and_config_mp_8822b_txpowertrack_type12( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type12_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type12_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type12_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type12_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type12_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type12_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type12_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type12_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** * txpowertrack_type13.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type13_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type13_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type13_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type13_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type13_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type13_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type13_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type13_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type13_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type13_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type13_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type13_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type13_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type13_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type13_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type13_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type13_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type13_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type13_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type13_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type13_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type13_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type13_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type13_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void odm_read_and_config_mp_8822b_txpowertrack_type13( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type13_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type13_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type13_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type13_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type13_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type13_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type13_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type13_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** * txpowertrack_type14.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type14_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type14_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type14_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type14_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type14_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type14_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type14_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type14_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type14_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type14_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type14_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type14_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type14_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type14_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type14_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type14_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type14_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type14_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type14_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type14_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type14_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type14_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type14_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type14_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void odm_read_and_config_mp_8822b_txpowertrack_type14( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type14_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type14_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type14_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type14_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type14_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type14_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type14_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type14_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** -* txpowertrack_type2.TXT +* txpowertrack_type15.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type2_8822b[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type15_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type2_8822b[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type15_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type2_8822b[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type15_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type2_8822b[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, - {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type15_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type2_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type2_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type2_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type2_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type2_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type2_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type2_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type2_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type15_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type15_8822b[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type15_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type15_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type15_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type15_8822b[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type15_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type15_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; void -odm_read_and_config_mp_8822b_txpowertrack_type2( - struct PHY_DM_STRUCT *p_dm_odm +odm_read_and_config_mp_8822b_txpowertrack_type15( + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type15_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type15_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type15_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type15_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type15_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type15_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type15_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type15_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type2_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type15_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type15_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type15_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type15_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** -* txpowertrack_type3_type5.TXT +* txpowertrack_type16.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type3_type5_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type16_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type3_type5_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type16_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type3_type5_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type16_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type3_type5_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type16_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type3_type5_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type16_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type16_8822b[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type16_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type16_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type16_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type16_8822b[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type16_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type16_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; void -odm_read_and_config_mp_8822b_txpowertrack_type3_type5( - struct PHY_DM_STRUCT *p_dm_odm +odm_read_and_config_mp_8822b_txpowertrack_type16( + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type16_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type16_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type16_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type16_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type16_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type16_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type16_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type16_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type3_type5_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type16_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type16_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type16_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type16_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** -* txpowertrack_type4.TXT +* txpowertrack_type17.TXT +******************************************************************************/ + +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type17_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type17_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type17_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type17_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type17_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type17_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type17_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type17_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type17_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type17_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type17_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type17_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; + +void +odm_read_and_config_mp_8822b_txpowertrack_type17( + struct dm_struct *dm +) +{ + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type17_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type17_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type17_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type17_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type17_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type17_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type17_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type17_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type17_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type17_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type17_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type17_8822b, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpowertrack_type2.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type4_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type2_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type4_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type2_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type4_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type2_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type4_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type2_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type4_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type4_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type4_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type4_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type4_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type4_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type4_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type4_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type2_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type2_8822b[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type2_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type2_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type2_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type2_8822b[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type2_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type2_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; void -odm_read_and_config_mp_8822b_txpowertrack_type4( - struct PHY_DM_STRUCT *p_dm_odm +odm_read_and_config_mp_8822b_txpowertrack_type2( + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type2_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type2_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type2_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type4_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type2_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type2_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type2_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type2_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** -* txpowertrack_type6.TXT +* txpowertrack_type3_type5.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type6_8822b[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, - {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, - {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17}, +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type3_type5_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type6_8822b[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, - {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21}, - {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21}, +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type3_type5_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type6_8822b[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17}, +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type3_type5_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, +}; +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type3_type5_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, + {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, +}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type3_type5_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type3_type5_8822b[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type3_type5_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type3_type5_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type3_type5_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type3_type5_8822b[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type3_type5_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type3_type5_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; + +void +odm_read_and_config_mp_8822b_txpowertrack_type3_type5( + struct dm_struct *dm +) +{ + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type3_type5_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type3_type5_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type3_type5_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type3_type5_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type3_type5_8822b, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpowertrack_type4.TXT +******************************************************************************/ + +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type4_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, +}; +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type4_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, +}; +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type4_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22}, +}; +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type4_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, + {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, +}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type4_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type4_8822b[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type4_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type4_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type4_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type4_8822b[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type4_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type4_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15}; + +void +odm_read_and_config_mp_8822b_txpowertrack_type4( + struct dm_struct *dm +) +{ + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type4_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type4_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type4_8822b, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type4_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type4_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type4_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type4_8822b, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpowertrack_type6.TXT +******************************************************************************/ + +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type6_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, + {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17}, +}; +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type6_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, + {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21}, + {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21}, +}; +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type6_8822b[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15}, {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type6_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type6_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21}, {0, 1, 2, 2, 3, 4, 4, 5, 7, 7, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21}, {0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 20, 20, 20, 20}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type6_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type6_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type6_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type6_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type6_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type6_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type6_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type6_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type6_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type6_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type6_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type6_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type6_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type6_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type6_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type6_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void odm_read_and_config_mp_8822b_txpowertrack_type6( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type6_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type6_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type6_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type6_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type6_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type6_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type6_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type6_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** * txpowertrack_type7.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type7_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type7_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15}, {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type7_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type7_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19}, {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21}, {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type7_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type7_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17}, {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15}, {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type7_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type7_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21}, {0, 1, 2, 2, 3, 4, 4, 5, 7, 7, 8, 9, 10, 11, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21}, {0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 20, 20, 20, 20}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type7_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type7_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type7_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type7_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type7_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type7_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type7_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type7_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type7_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type7_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type7_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type7_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type7_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type7_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type7_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type7_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void odm_read_and_config_mp_8822b_txpowertrack_type7( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type7_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type7_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type7_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type7_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type7_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type7_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type7_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type7_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** * txpowertrack_type8.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type8_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type8_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type8_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type8_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type8_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type8_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type8_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type8_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type8_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type8_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type8_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type8_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type8_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type8_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type8_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type8_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type8_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type8_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type8_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type8_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type8_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type8_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type8_8822b[] = {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type8_8822b[] = {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}; void odm_read_and_config_mp_8822b_txpowertrack_type8( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type8_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type8_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type8_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type8_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type8_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type8_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type8_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type8_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** * txpowertrack_type9.TXT ******************************************************************************/ -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type9_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type9_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type9_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type9_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16}, }; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type9_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type9_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14}, }; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type9_8822b[][DELTA_SWINGIDX_SIZE] = { +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type9_8822b[][DELTA_SWINGIDX_SIZE] = { {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15}, {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15}, }; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type9_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type9_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type9_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type9_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type9_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type9_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type9_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type9_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type9_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type9_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type9_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type9_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type9_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type9_8822b[] = {0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type9_8822b[] = {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type9_8822b[] = {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22}; void odm_read_and_config_mp_8822b_txpowertrack_type9( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8822b\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n"); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type9_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type9_8822b, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type9_8822b, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_type9_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type9_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type9_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type9_8822b, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type9_8822b, DELTA_SWINGIDX_SIZE*3); } /****************************************************************************** @@ -9118,7 +10138,7 @@ const char *array_mp_8822b_txpwr_lmt[] = { void odm_read_and_config_mp_8822b_txpwr_lmt( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 i = 0; @@ -9131,14 +10151,14 @@ odm_read_and_config_mp_8822b_txpwr_lmt( #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - PlatformZeroMemory(p_hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - p_hal_data->nLinesReadPwrLmt = array_len/7; + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len/7; #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_txpwr_lmt\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_txpwr_lmt\n"); for (i = 0; i < array_len; i += 7) { #if (DM_ODM_SUPPORT_TYPE == ODM_IOT) @@ -9159,9 +10179,9 @@ odm_read_and_config_mp_8822b_txpwr_lmt( u8 *val = array[i+6]; #endif - odm_config_bb_txpwr_lmt_8822b(p_dm_odm, regulation, band, bandwidth, rate, rf_path, chnl, val); + odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)p_hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", regulation, band, bandwidth, rate, rf_path, chnl, val); #endif } @@ -9169,10 +10189,10 @@ odm_read_and_config_mp_8822b_txpwr_lmt( } /****************************************************************************** -* txpwr_lmt_type5.TXT +* txpwr_lmt_type12.TXT ******************************************************************************/ -const char *array_mp_8822b_txpwr_lmt_type5[] = { +const char *array_mp_8822b_txpwr_lmt_type12[] = { "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", @@ -9760,9 +10780,5492 @@ const char *array_mp_8822b_txpwr_lmt_type5[] = { "MKK", "5G", "80M", "VHT", "2T", "155", "63" }; +void +odm_read_and_config_mp_8822b_txpwr_lmt_type12( + struct dm_struct *dm +) +{ + u32 i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type12)/sizeof(u8); + u8 *array = (u8 *)array_mp_8822b_txpwr_lmt_type12; +#else + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type12)/sizeof(u8 *); + u8 **array = (u8 **)array_mp_8822b_txpwr_lmt_type12; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len/7; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_txpwr_lmt_type12\n"); + + for (i = 0; i < array_len; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u8 regulation = array[i]; + u8 band = array[i+1]; + u8 bandwidth = array[i+2]; + u8 rate = array[i+3]; + u8 rf_path = array[i+4]; + u8 chnl = array[i+5]; + u8 val = array[i+6]; +#else + u8 *regulation = array[i]; + u8 *band = array[i+1]; + u8 *bandwidth = array[i+2]; + u8 *rate = array[i+3]; + u8 *rf_path = array[i+4]; + u8 *chnl = array[i+5]; + u8 *val = array[i+6]; +#endif + + odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rf_path, chnl, val); +#endif + } + +} + +/****************************************************************************** +* txpwr_lmt_type15.TXT +******************************************************************************/ + +const char *array_mp_8822b_txpwr_lmt_type15[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type15( + struct dm_struct *dm +) +{ + u32 i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type15)/sizeof(u8); + u8 *array = (u8 *)array_mp_8822b_txpwr_lmt_type15; +#else + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type15)/sizeof(u8 *); + u8 **array = (u8 **)array_mp_8822b_txpwr_lmt_type15; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len/7; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_txpwr_lmt_type15\n"); + + for (i = 0; i < array_len; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u8 regulation = array[i]; + u8 band = array[i+1]; + u8 bandwidth = array[i+2]; + u8 rate = array[i+3]; + u8 rf_path = array[i+4]; + u8 chnl = array[i+5]; + u8 val = array[i+6]; +#else + u8 *regulation = array[i]; + u8 *band = array[i+1]; + u8 *bandwidth = array[i+2]; + u8 *rate = array[i+3]; + u8 *rf_path = array[i+4]; + u8 *chnl = array[i+5]; + u8 *val = array[i+6]; +#endif + + odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rf_path, chnl, val); +#endif + } + +} + +/****************************************************************************** +* txpwr_lmt_type16.TXT +******************************************************************************/ + +const char *array_mp_8822b_txpwr_lmt_type16[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type16( + struct dm_struct *dm +) +{ + u32 i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type16)/sizeof(u8); + u8 *array = (u8 *)array_mp_8822b_txpwr_lmt_type16; +#else + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type16)/sizeof(u8 *); + u8 **array = (u8 **)array_mp_8822b_txpwr_lmt_type16; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len/7; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_txpwr_lmt_type16\n"); + + for (i = 0; i < array_len; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u8 regulation = array[i]; + u8 band = array[i+1]; + u8 bandwidth = array[i+2]; + u8 rate = array[i+3]; + u8 rf_path = array[i+4]; + u8 chnl = array[i+5]; + u8 val = array[i+6]; +#else + u8 *regulation = array[i]; + u8 *band = array[i+1]; + u8 *bandwidth = array[i+2]; + u8 *rate = array[i+3]; + u8 *rf_path = array[i+4]; + u8 *chnl = array[i+5]; + u8 *val = array[i+6]; +#endif + + odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rf_path, chnl, val); +#endif + } + +} + +/****************************************************************************** +* txpwr_lmt_type17.TXT +******************************************************************************/ + +const char *array_mp_8822b_txpwr_lmt_type17[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "31", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "01", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "31", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "02", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "31", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "03", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "31", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "04", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "05", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "06", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "07", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "08", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "37", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "09", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "37", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "10", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "37", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "11", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "29", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "12", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "24", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "KCC", "2.4G", "20M", "CCK", "1T", "13", "35", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "01", "35", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "02", "35", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "03", "35", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "31", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "27", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "27", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "27", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "20", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "-1", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "KCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "25", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "31", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "KCC", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "25", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "31", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "KCC", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "25", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "31", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "KCC", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "25", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "31", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "KCC", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "25", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "KCC", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "25", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "KCC", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "25", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "KCC", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "25", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "KCC", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "KCC", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "KCC", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "KCC", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "KCC", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "-5", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "KCC", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "KCC", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "25", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "26", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "KCC", "2.4G", "20M", "HT", "2T", "01", "32", + "FCC", "2.4G", "20M", "HT", "2T", "02", "25", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "26", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "KCC", "2.4G", "20M", "HT", "2T", "02", "32", + "FCC", "2.4G", "20M", "HT", "2T", "03", "25", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "26", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "KCC", "2.4G", "20M", "HT", "2T", "03", "32", + "FCC", "2.4G", "20M", "HT", "2T", "04", "25", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "26", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "KCC", "2.4G", "20M", "HT", "2T", "04", "32", + "FCC", "2.4G", "20M", "HT", "2T", "05", "25", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "26", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "KCC", "2.4G", "20M", "HT", "2T", "05", "32", + "FCC", "2.4G", "20M", "HT", "2T", "06", "25", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "26", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "KCC", "2.4G", "20M", "HT", "2T", "06", "32", + "FCC", "2.4G", "20M", "HT", "2T", "07", "25", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "26", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "KCC", "2.4G", "20M", "HT", "2T", "07", "32", + "FCC", "2.4G", "20M", "HT", "2T", "08", "25", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "26", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "KCC", "2.4G", "20M", "HT", "2T", "08", "32", + "FCC", "2.4G", "20M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "26", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "KCC", "2.4G", "20M", "HT", "2T", "09", "32", + "FCC", "2.4G", "20M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "25", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "KCC", "2.4G", "20M", "HT", "2T", "10", "32", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "25", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "KCC", "2.4G", "20M", "HT", "2T", "11", "32", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "25", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "KCC", "2.4G", "20M", "HT", "2T", "12", "32", + "FCC", "2.4G", "20M", "HT", "2T", "13", "-5", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "25", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "KCC", "2.4G", "20M", "HT", "2T", "13", "32", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "KCC", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "KCC", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "KCC", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "21", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "KCC", "2.4G", "40M", "HT", "1T", "03", "30", + "FCC", "2.4G", "40M", "HT", "1T", "04", "21", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "KCC", "2.4G", "40M", "HT", "1T", "04", "30", + "FCC", "2.4G", "40M", "HT", "1T", "05", "21", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "KCC", "2.4G", "40M", "HT", "1T", "05", "30", + "FCC", "2.4G", "40M", "HT", "1T", "06", "21", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "KCC", "2.4G", "40M", "HT", "1T", "06", "30", + "FCC", "2.4G", "40M", "HT", "1T", "07", "21", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "KCC", "2.4G", "40M", "HT", "1T", "07", "30", + "FCC", "2.4G", "40M", "HT", "1T", "08", "21", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "KCC", "2.4G", "40M", "HT", "1T", "08", "30", + "FCC", "2.4G", "40M", "HT", "1T", "09", "21", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "KCC", "2.4G", "40M", "HT", "1T", "09", "30", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "KCC", "2.4G", "40M", "HT", "1T", "10", "30", + "FCC", "2.4G", "40M", "HT", "1T", "11", "-2", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "29", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "KCC", "2.4G", "40M", "HT", "1T", "11", "30", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "KCC", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "KCC", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "KCC", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "KCC", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "KCC", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "21", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "KCC", "2.4G", "40M", "HT", "2T", "03", "28", + "FCC", "2.4G", "40M", "HT", "2T", "04", "21", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "KCC", "2.4G", "40M", "HT", "2T", "04", "28", + "FCC", "2.4G", "40M", "HT", "2T", "05", "21", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "KCC", "2.4G", "40M", "HT", "2T", "05", "28", + "FCC", "2.4G", "40M", "HT", "2T", "06", "21", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "KCC", "2.4G", "40M", "HT", "2T", "06", "28", + "FCC", "2.4G", "40M", "HT", "2T", "07", "21", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "KCC", "2.4G", "40M", "HT", "2T", "07", "28", + "FCC", "2.4G", "40M", "HT", "2T", "08", "21", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "KCC", "2.4G", "40M", "HT", "2T", "08", "28", + "FCC", "2.4G", "40M", "HT", "2T", "09", "21", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "KCC", "2.4G", "40M", "HT", "2T", "09", "28", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "KCC", "2.4G", "40M", "HT", "2T", "10", "28", + "FCC", "2.4G", "40M", "HT", "2T", "11", "-2", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "KCC", "2.4G", "40M", "HT", "2T", "11", "28", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "KCC", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "KCC", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "KCC", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "20", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "26", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "KCC", "5G", "20M", "OFDM", "1T", "36", "29", + "FCC", "5G", "20M", "OFDM", "1T", "40", "21", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "27", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "KCC", "5G", "20M", "OFDM", "1T", "40", "29", + "FCC", "5G", "20M", "OFDM", "1T", "44", "20", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "27", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "KCC", "5G", "20M", "OFDM", "1T", "44", "29", + "FCC", "5G", "20M", "OFDM", "1T", "48", "20", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "27", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "KCC", "5G", "20M", "OFDM", "1T", "48", "29", + "FCC", "5G", "20M", "OFDM", "1T", "52", "21", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "20", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "KCC", "5G", "20M", "OFDM", "1T", "52", "31", + "FCC", "5G", "20M", "OFDM", "1T", "56", "21", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "20", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "KCC", "5G", "20M", "OFDM", "1T", "56", "31", + "FCC", "5G", "20M", "OFDM", "1T", "60", "24", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "20", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "KCC", "5G", "20M", "OFDM", "1T", "60", "31", + "FCC", "5G", "20M", "OFDM", "1T", "64", "24", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "20", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "KCC", "5G", "20M", "OFDM", "1T", "64", "30", + "FCC", "5G", "20M", "OFDM", "1T", "100", "25", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "19", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "KCC", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "25", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "19", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "KCC", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "25", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "19", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "KCC", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "25", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "19", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "KCC", "5G", "20M", "OFDM", "1T", "112", "31", + "FCC", "5G", "20M", "OFDM", "1T", "116", "25", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "19", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "KCC", "5G", "20M", "OFDM", "1T", "116", "31", + "FCC", "5G", "20M", "OFDM", "1T", "120", "25", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "19", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "KCC", "5G", "20M", "OFDM", "1T", "120", "31", + "FCC", "5G", "20M", "OFDM", "1T", "124", "25", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "19", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "KCC", "5G", "20M", "OFDM", "1T", "124", "31", + "FCC", "5G", "20M", "OFDM", "1T", "128", "25", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "19", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "KCC", "5G", "20M", "OFDM", "1T", "128", "31", + "FCC", "5G", "20M", "OFDM", "1T", "132", "21", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "19", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "KCC", "5G", "20M", "OFDM", "1T", "132", "29", + "FCC", "5G", "20M", "OFDM", "1T", "136", "21", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "19", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "KCC", "5G", "20M", "OFDM", "1T", "136", "29", + "FCC", "5G", "20M", "OFDM", "1T", "140", "21", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "19", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "KCC", "5G", "20M", "OFDM", "1T", "140", "29", + "FCC", "5G", "20M", "OFDM", "1T", "144", "21", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "10", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "KCC", "5G", "20M", "OFDM", "1T", "144", "31", + "FCC", "5G", "20M", "OFDM", "1T", "149", "24", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "10", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "KCC", "5G", "20M", "OFDM", "1T", "149", "31", + "FCC", "5G", "20M", "OFDM", "1T", "153", "23", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "10", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "KCC", "5G", "20M", "OFDM", "1T", "153", "31", + "FCC", "5G", "20M", "OFDM", "1T", "157", "23", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "11", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "KCC", "5G", "20M", "OFDM", "1T", "157", "31", + "FCC", "5G", "20M", "OFDM", "1T", "161", "22", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "11", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "KCC", "5G", "20M", "OFDM", "1T", "161", "31", + "FCC", "5G", "20M", "OFDM", "1T", "165", "22", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "11", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "KCC", "5G", "20M", "OFDM", "1T", "165", "31", + "FCC", "5G", "20M", "HT", "1T", "36", "20", + "ETSI", "5G", "20M", "HT", "1T", "36", "24", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "KCC", "5G", "20M", "HT", "1T", "36", "27", + "FCC", "5G", "20M", "HT", "1T", "40", "21", + "ETSI", "5G", "20M", "HT", "1T", "40", "24", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "KCC", "5G", "20M", "HT", "1T", "40", "27", + "FCC", "5G", "20M", "HT", "1T", "44", "21", + "ETSI", "5G", "20M", "HT", "1T", "44", "24", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "KCC", "5G", "20M", "HT", "1T", "44", "27", + "FCC", "5G", "20M", "HT", "1T", "48", "21", + "ETSI", "5G", "20M", "HT", "1T", "48", "24", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "KCC", "5G", "20M", "HT", "1T", "48", "27", + "FCC", "5G", "20M", "HT", "1T", "52", "21", + "ETSI", "5G", "20M", "HT", "1T", "52", "17", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "KCC", "5G", "20M", "HT", "1T", "52", "27", + "FCC", "5G", "20M", "HT", "1T", "56", "21", + "ETSI", "5G", "20M", "HT", "1T", "56", "17", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "KCC", "5G", "20M", "HT", "1T", "56", "27", + "FCC", "5G", "20M", "HT", "1T", "60", "24", + "ETSI", "5G", "20M", "HT", "1T", "60", "17", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "KCC", "5G", "20M", "HT", "1T", "60", "27", + "FCC", "5G", "20M", "HT", "1T", "64", "24", + "ETSI", "5G", "20M", "HT", "1T", "64", "17", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "KCC", "5G", "20M", "HT", "1T", "64", "26", + "FCC", "5G", "20M", "HT", "1T", "100", "28", + "ETSI", "5G", "20M", "HT", "1T", "100", "19", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "KCC", "5G", "20M", "HT", "1T", "100", "28", + "FCC", "5G", "20M", "HT", "1T", "104", "28", + "ETSI", "5G", "20M", "HT", "1T", "104", "19", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "KCC", "5G", "20M", "HT", "1T", "104", "28", + "FCC", "5G", "20M", "HT", "1T", "108", "27", + "ETSI", "5G", "20M", "HT", "1T", "108", "19", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "KCC", "5G", "20M", "HT", "1T", "108", "28", + "FCC", "5G", "20M", "HT", "1T", "112", "27", + "ETSI", "5G", "20M", "HT", "1T", "112", "19", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "KCC", "5G", "20M", "HT", "1T", "112", "27", + "FCC", "5G", "20M", "HT", "1T", "116", "27", + "ETSI", "5G", "20M", "HT", "1T", "116", "19", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "KCC", "5G", "20M", "HT", "1T", "116", "27", + "FCC", "5G", "20M", "HT", "1T", "120", "27", + "ETSI", "5G", "20M", "HT", "1T", "120", "19", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "KCC", "5G", "20M", "HT", "1T", "120", "27", + "FCC", "5G", "20M", "HT", "1T", "124", "27", + "ETSI", "5G", "20M", "HT", "1T", "124", "19", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "KCC", "5G", "20M", "HT", "1T", "124", "27", + "FCC", "5G", "20M", "HT", "1T", "128", "27", + "ETSI", "5G", "20M", "HT", "1T", "128", "19", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "KCC", "5G", "20M", "HT", "1T", "128", "27", + "FCC", "5G", "20M", "HT", "1T", "132", "21", + "ETSI", "5G", "20M", "HT", "1T", "132", "19", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "KCC", "5G", "20M", "HT", "1T", "132", "25", + "FCC", "5G", "20M", "HT", "1T", "136", "21", + "ETSI", "5G", "20M", "HT", "1T", "136", "18", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "KCC", "5G", "20M", "HT", "1T", "136", "25", + "FCC", "5G", "20M", "HT", "1T", "140", "21", + "ETSI", "5G", "20M", "HT", "1T", "140", "17", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "KCC", "5G", "20M", "HT", "1T", "140", "25", + "FCC", "5G", "20M", "HT", "1T", "144", "21", + "ETSI", "5G", "20M", "HT", "1T", "144", "8", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "KCC", "5G", "20M", "HT", "1T", "144", "28", + "FCC", "5G", "20M", "HT", "1T", "149", "25", + "ETSI", "5G", "20M", "HT", "1T", "149", "8", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "KCC", "5G", "20M", "HT", "1T", "149", "28", + "FCC", "5G", "20M", "HT", "1T", "153", "25", + "ETSI", "5G", "20M", "HT", "1T", "153", "8", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "KCC", "5G", "20M", "HT", "1T", "153", "28", + "FCC", "5G", "20M", "HT", "1T", "157", "25", + "ETSI", "5G", "20M", "HT", "1T", "157", "10", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "KCC", "5G", "20M", "HT", "1T", "157", "28", + "FCC", "5G", "20M", "HT", "1T", "161", "24", + "ETSI", "5G", "20M", "HT", "1T", "161", "10", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "KCC", "5G", "20M", "HT", "1T", "161", "27", + "FCC", "5G", "20M", "HT", "1T", "165", "24", + "ETSI", "5G", "20M", "HT", "1T", "165", "10", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "KCC", "5G", "20M", "HT", "1T", "165", "27", + "FCC", "5G", "20M", "HT", "2T", "36", "18", + "ETSI", "5G", "20M", "HT", "2T", "36", "21", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "KCC", "5G", "20M", "HT", "2T", "36", "25", + "FCC", "5G", "20M", "HT", "2T", "40", "21", + "ETSI", "5G", "20M", "HT", "2T", "40", "24", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "KCC", "5G", "20M", "HT", "2T", "40", "24", + "FCC", "5G", "20M", "HT", "2T", "44", "21", + "ETSI", "5G", "20M", "HT", "2T", "44", "24", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "KCC", "5G", "20M", "HT", "2T", "44", "24", + "FCC", "5G", "20M", "HT", "2T", "48", "21", + "ETSI", "5G", "20M", "HT", "2T", "48", "24", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "KCC", "5G", "20M", "HT", "2T", "48", "24", + "FCC", "5G", "20M", "HT", "2T", "52", "21", + "ETSI", "5G", "20M", "HT", "2T", "52", "17", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "KCC", "5G", "20M", "HT", "2T", "52", "28", + "FCC", "5G", "20M", "HT", "2T", "56", "21", + "ETSI", "5G", "20M", "HT", "2T", "56", "17", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "KCC", "5G", "20M", "HT", "2T", "56", "27", + "FCC", "5G", "20M", "HT", "2T", "60", "24", + "ETSI", "5G", "20M", "HT", "2T", "60", "17", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "KCC", "5G", "20M", "HT", "2T", "60", "27", + "FCC", "5G", "20M", "HT", "2T", "64", "24", + "ETSI", "5G", "20M", "HT", "2T", "64", "17", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "KCC", "5G", "20M", "HT", "2T", "64", "27", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "19", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "KCC", "5G", "20M", "HT", "2T", "100", "27", + "FCC", "5G", "20M", "HT", "2T", "104", "28", + "ETSI", "5G", "20M", "HT", "2T", "104", "19", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "KCC", "5G", "20M", "HT", "2T", "104", "27", + "FCC", "5G", "20M", "HT", "2T", "108", "27", + "ETSI", "5G", "20M", "HT", "2T", "108", "19", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "KCC", "5G", "20M", "HT", "2T", "108", "27", + "FCC", "5G", "20M", "HT", "2T", "112", "27", + "ETSI", "5G", "20M", "HT", "2T", "112", "19", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "KCC", "5G", "20M", "HT", "2T", "112", "26", + "FCC", "5G", "20M", "HT", "2T", "116", "27", + "ETSI", "5G", "20M", "HT", "2T", "116", "19", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "KCC", "5G", "20M", "HT", "2T", "116", "26", + "FCC", "5G", "20M", "HT", "2T", "120", "27", + "ETSI", "5G", "20M", "HT", "2T", "120", "19", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "KCC", "5G", "20M", "HT", "2T", "120", "26", + "FCC", "5G", "20M", "HT", "2T", "124", "27", + "ETSI", "5G", "20M", "HT", "2T", "124", "19", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "KCC", "5G", "20M", "HT", "2T", "124", "26", + "FCC", "5G", "20M", "HT", "2T", "128", "27", + "ETSI", "5G", "20M", "HT", "2T", "128", "19", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "KCC", "5G", "20M", "HT", "2T", "128", "26", + "FCC", "5G", "20M", "HT", "2T", "132", "21", + "ETSI", "5G", "20M", "HT", "2T", "132", "19", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "KCC", "5G", "20M", "HT", "2T", "132", "26", + "FCC", "5G", "20M", "HT", "2T", "136", "21", + "ETSI", "5G", "20M", "HT", "2T", "136", "18", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "KCC", "5G", "20M", "HT", "2T", "136", "26", + "FCC", "5G", "20M", "HT", "2T", "140", "21", + "ETSI", "5G", "20M", "HT", "2T", "140", "17", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "KCC", "5G", "20M", "HT", "2T", "140", "26", + "FCC", "5G", "20M", "HT", "2T", "144", "21", + "ETSI", "5G", "20M", "HT", "2T", "144", "8", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "KCC", "5G", "20M", "HT", "2T", "144", "26", + "FCC", "5G", "20M", "HT", "2T", "149", "25", + "ETSI", "5G", "20M", "HT", "2T", "149", "8", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "KCC", "5G", "20M", "HT", "2T", "149", "26", + "FCC", "5G", "20M", "HT", "2T", "153", "25", + "ETSI", "5G", "20M", "HT", "2T", "153", "8", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "KCC", "5G", "20M", "HT", "2T", "153", "26", + "FCC", "5G", "20M", "HT", "2T", "157", "25", + "ETSI", "5G", "20M", "HT", "2T", "157", "10", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "KCC", "5G", "20M", "HT", "2T", "157", "26", + "FCC", "5G", "20M", "HT", "2T", "161", "24", + "ETSI", "5G", "20M", "HT", "2T", "161", "10", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "KCC", "5G", "20M", "HT", "2T", "161", "26", + "FCC", "5G", "20M", "HT", "2T", "165", "24", + "ETSI", "5G", "20M", "HT", "2T", "165", "10", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "KCC", "5G", "20M", "HT", "2T", "165", "26", + "FCC", "5G", "40M", "HT", "1T", "38", "19", + "ETSI", "5G", "40M", "HT", "1T", "38", "26", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "KCC", "5G", "40M", "HT", "1T", "38", "27", + "FCC", "5G", "40M", "HT", "1T", "46", "22", + "ETSI", "5G", "40M", "HT", "1T", "46", "26", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "KCC", "5G", "40M", "HT", "1T", "46", "27", + "FCC", "5G", "40M", "HT", "1T", "54", "22", + "ETSI", "5G", "40M", "HT", "1T", "54", "18", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "KCC", "5G", "40M", "HT", "1T", "54", "28", + "FCC", "5G", "40M", "HT", "1T", "62", "20", + "ETSI", "5G", "40M", "HT", "1T", "62", "18", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "KCC", "5G", "40M", "HT", "1T", "62", "28", + "FCC", "5G", "40M", "HT", "1T", "102", "15", + "ETSI", "5G", "40M", "HT", "1T", "102", "20", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "KCC", "5G", "40M", "HT", "1T", "102", "28", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "20", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "KCC", "5G", "40M", "HT", "1T", "110", "26", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "20", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "KCC", "5G", "40M", "HT", "1T", "118", "26", + "FCC", "5G", "40M", "HT", "1T", "126", "28", + "ETSI", "5G", "40M", "HT", "1T", "126", "20", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "KCC", "5G", "40M", "HT", "1T", "126", "25", + "FCC", "5G", "40M", "HT", "1T", "134", "28", + "ETSI", "5G", "40M", "HT", "1T", "134", "19", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "KCC", "5G", "40M", "HT", "1T", "134", "25", + "FCC", "5G", "40M", "HT", "1T", "142", "28", + "ETSI", "5G", "40M", "HT", "1T", "142", "9", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "KCC", "5G", "40M", "HT", "1T", "142", "25", + "FCC", "5G", "40M", "HT", "1T", "151", "29", + "ETSI", "5G", "40M", "HT", "1T", "151", "9", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "KCC", "5G", "40M", "HT", "1T", "151", "27", + "FCC", "5G", "40M", "HT", "1T", "159", "29", + "ETSI", "5G", "40M", "HT", "1T", "159", "10", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "KCC", "5G", "40M", "HT", "1T", "159", "26", + "FCC", "5G", "40M", "HT", "2T", "38", "19", + "ETSI", "5G", "40M", "HT", "2T", "38", "24", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "KCC", "5G", "40M", "HT", "2T", "38", "25", + "FCC", "5G", "40M", "HT", "2T", "46", "22", + "ETSI", "5G", "40M", "HT", "2T", "46", "26", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "KCC", "5G", "40M", "HT", "2T", "46", "25", + "FCC", "5G", "40M", "HT", "2T", "54", "22", + "ETSI", "5G", "40M", "HT", "2T", "54", "18", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "KCC", "5G", "40M", "HT", "2T", "54", "26", + "FCC", "5G", "40M", "HT", "2T", "62", "20", + "ETSI", "5G", "40M", "HT", "2T", "62", "18", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "KCC", "5G", "40M", "HT", "2T", "62", "26", + "FCC", "5G", "40M", "HT", "2T", "102", "15", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "KCC", "5G", "40M", "HT", "2T", "102", "27", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "KCC", "5G", "40M", "HT", "2T", "110", "25", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "KCC", "5G", "40M", "HT", "2T", "118", "25", + "FCC", "5G", "40M", "HT", "2T", "126", "28", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "KCC", "5G", "40M", "HT", "2T", "126", "24", + "FCC", "5G", "40M", "HT", "2T", "134", "28", + "ETSI", "5G", "40M", "HT", "2T", "134", "19", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "KCC", "5G", "40M", "HT", "2T", "134", "24", + "FCC", "5G", "40M", "HT", "2T", "142", "28", + "ETSI", "5G", "40M", "HT", "2T", "142", "9", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "KCC", "5G", "40M", "HT", "2T", "142", "24", + "FCC", "5G", "40M", "HT", "2T", "151", "29", + "ETSI", "5G", "40M", "HT", "2T", "151", "9", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "KCC", "5G", "40M", "HT", "2T", "151", "25", + "FCC", "5G", "40M", "HT", "2T", "159", "29", + "ETSI", "5G", "40M", "HT", "2T", "159", "10", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "KCC", "5G", "40M", "HT", "2T", "159", "24", + "FCC", "5G", "80M", "VHT", "1T", "42", "17", + "ETSI", "5G", "80M", "VHT", "1T", "42", "26", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "KCC", "5G", "80M", "VHT", "1T", "42", "26", + "FCC", "5G", "80M", "VHT", "1T", "58", "18", + "ETSI", "5G", "80M", "VHT", "1T", "58", "20", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "KCC", "5G", "80M", "VHT", "1T", "58", "25", + "FCC", "5G", "80M", "VHT", "1T", "106", "16", + "ETSI", "5G", "80M", "VHT", "1T", "106", "21", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "KCC", "5G", "80M", "VHT", "1T", "106", "26", + "FCC", "5G", "80M", "VHT", "1T", "122", "16", + "ETSI", "5G", "80M", "VHT", "1T", "122", "17", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "KCC", "5G", "80M", "VHT", "1T", "122", "24", + "FCC", "5G", "80M", "VHT", "1T", "138", "29", + "ETSI", "5G", "80M", "VHT", "1T", "138", "17", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "KCC", "5G", "80M", "VHT", "1T", "138", "25", + "FCC", "5G", "80M", "VHT", "1T", "155", "28", + "ETSI", "5G", "80M", "VHT", "1T", "155", "9", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "KCC", "5G", "80M", "VHT", "1T", "155", "25", + "FCC", "5G", "80M", "VHT", "2T", "42", "17", + "ETSI", "5G", "80M", "VHT", "2T", "42", "23", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "KCC", "5G", "80M", "VHT", "2T", "42", "23", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "KCC", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "16", + "ETSI", "5G", "80M", "VHT", "2T", "106", "21", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "KCC", "5G", "80M", "VHT", "2T", "106", "26", + "FCC", "5G", "80M", "VHT", "2T", "122", "16", + "ETSI", "5G", "80M", "VHT", "2T", "122", "17", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "KCC", "5G", "80M", "VHT", "2T", "122", "24", + "FCC", "5G", "80M", "VHT", "2T", "138", "29", + "ETSI", "5G", "80M", "VHT", "2T", "138", "17", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "KCC", "5G", "80M", "VHT", "2T", "138", "24", + "FCC", "5G", "80M", "VHT", "2T", "155", "28", + "ETSI", "5G", "80M", "VHT", "2T", "155", "9", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "KCC", "5G", "80M", "VHT", "2T", "155", "24" +}; + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type17( + struct dm_struct *dm +) +{ + u32 i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type17)/sizeof(u8); + u8 *array = (u8 *)array_mp_8822b_txpwr_lmt_type17; +#else + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type17)/sizeof(u8 *); + u8 **array = (u8 **)array_mp_8822b_txpwr_lmt_type17; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len/7; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_txpwr_lmt_type17\n"); + + for (i = 0; i < array_len; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u8 regulation = array[i]; + u8 band = array[i+1]; + u8 bandwidth = array[i+2]; + u8 rate = array[i+3]; + u8 rf_path = array[i+4]; + u8 chnl = array[i+5]; + u8 val = array[i+6]; +#else + u8 *regulation = array[i]; + u8 *band = array[i+1]; + u8 *bandwidth = array[i+2]; + u8 *rate = array[i+3]; + u8 *rf_path = array[i+4]; + u8 *chnl = array[i+5]; + u8 *val = array[i+6]; +#endif + + odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rf_path, chnl, val); +#endif + } + +} + +/****************************************************************************** +* txpwr_lmt_type2.TXT +******************************************************************************/ + +const char *array_mp_8822b_txpwr_lmt_type2[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "36", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "38", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "38", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "38", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "38", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "38", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "38", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "34", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "32", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "38", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "38", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "38", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "38", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "38", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "38", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "38", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "38", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "38", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "32", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "38", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "38", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "38", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "38", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "38", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "34", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "36", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "36", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "36", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "36", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "36", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "36", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "34", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "32", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "36", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "38", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "38", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "38", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "38", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "38", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "38", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "38", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "36", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "32", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "38", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "38", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "38", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "38", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "38", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "28", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "36", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "36", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "30", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "30", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "36", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "36", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "36", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "36", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "36", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "36", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "26", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "36", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "36", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "28", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "28", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "36", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "36", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "36", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "36", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "36", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "36", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "26", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "26", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "26", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "36", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "36", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "36", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "24", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "24", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "26", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "36", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "36", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "36", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type2( + struct dm_struct *dm +) +{ + u32 i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type2)/sizeof(u8); + u8 *array = (u8 *)array_mp_8822b_txpwr_lmt_type2; +#else + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type2)/sizeof(u8 *); + u8 **array = (u8 **)array_mp_8822b_txpwr_lmt_type2; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len/7; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_txpwr_lmt_type2\n"); + + for (i = 0; i < array_len; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u8 regulation = array[i]; + u8 band = array[i+1]; + u8 bandwidth = array[i+2]; + u8 rate = array[i+3]; + u8 rf_path = array[i+4]; + u8 chnl = array[i+5]; + u8 val = array[i+6]; +#else + u8 *regulation = array[i]; + u8 *band = array[i+1]; + u8 *bandwidth = array[i+2]; + u8 *rate = array[i+3]; + u8 *rf_path = array[i+4]; + u8 *chnl = array[i+5]; + u8 *val = array[i+6]; +#endif + + odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rf_path, chnl, val); +#endif + } + +} + +/****************************************************************************** +* txpwr_lmt_type3.TXT +******************************************************************************/ + +const char *array_mp_8822b_txpwr_lmt_type3[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type3( + struct dm_struct *dm +) +{ + u32 i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type3)/sizeof(u8); + u8 *array = (u8 *)array_mp_8822b_txpwr_lmt_type3; +#else + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type3)/sizeof(u8 *); + u8 **array = (u8 **)array_mp_8822b_txpwr_lmt_type3; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len/7; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_txpwr_lmt_type3\n"); + + for (i = 0; i < array_len; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u8 regulation = array[i]; + u8 band = array[i+1]; + u8 bandwidth = array[i+2]; + u8 rate = array[i+3]; + u8 rf_path = array[i+4]; + u8 chnl = array[i+5]; + u8 val = array[i+6]; +#else + u8 *regulation = array[i]; + u8 *band = array[i+1]; + u8 *bandwidth = array[i+2]; + u8 *rate = array[i+3]; + u8 *rf_path = array[i+4]; + u8 *chnl = array[i+5]; + u8 *val = array[i+6]; +#endif + + odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rf_path, chnl, val); +#endif + } + +} + +/****************************************************************************** +* txpwr_lmt_type4.TXT +******************************************************************************/ + +const char *array_mp_8822b_txpwr_lmt_type4[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "38", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "38", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "40", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "38", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "36", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "20", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "38", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "40", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "38", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "36", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "38", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "38", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "38", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "36", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "34", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "FCC", "2.4G", "40M", "HT", "1T", "04", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "FCC", "2.4G", "40M", "HT", "1T", "05", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "FCC", "2.4G", "40M", "HT", "1T", "06", "38", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "FCC", "2.4G", "40M", "HT", "1T", "07", "36", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "FCC", "2.4G", "40M", "HT", "1T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "FCC", "2.4G", "40M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "FCC", "2.4G", "40M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "FCC", "2.4G", "40M", "HT", "1T", "11", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "FCC", "2.4G", "40M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "FCC", "2.4G", "40M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "FCC", "2.4G", "40M", "HT", "2T", "06", "34", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "FCC", "2.4G", "40M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "FCC", "2.4G", "40M", "HT", "2T", "08", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "FCC", "2.4G", "40M", "HT", "2T", "09", "32", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "FCC", "2.4G", "40M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "FCC", "2.4G", "40M", "HT", "2T", "11", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "36", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "FCC", "5G", "20M", "OFDM", "1T", "56", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "FCC", "5G", "20M", "OFDM", "1T", "60", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "FCC", "5G", "20M", "OFDM", "1T", "64", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "FCC", "5G", "20M", "OFDM", "1T", "100", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "104", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "144", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "38", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "36", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "FCC", "5G", "20M", "HT", "1T", "40", "38", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "FCC", "5G", "20M", "HT", "1T", "44", "38", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "FCC", "5G", "20M", "HT", "1T", "48", "38", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "FCC", "5G", "20M", "HT", "1T", "52", "38", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "FCC", "5G", "20M", "HT", "1T", "56", "38", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "FCC", "5G", "20M", "HT", "1T", "60", "38", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "FCC", "5G", "20M", "HT", "1T", "64", "34", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "FCC", "5G", "20M", "HT", "1T", "100", "32", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "104", "38", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "38", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "38", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "38", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "38", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "38", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "38", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "38", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "38", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "32", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "38", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "38", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "38", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "38", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "38", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "34", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "FCC", "5G", "20M", "HT", "2T", "40", "36", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "FCC", "5G", "20M", "HT", "2T", "44", "36", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "FCC", "5G", "20M", "HT", "2T", "48", "36", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "FCC", "5G", "20M", "HT", "2T", "52", "36", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "FCC", "5G", "20M", "HT", "2T", "56", "36", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "FCC", "5G", "20M", "HT", "2T", "60", "36", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "FCC", "5G", "20M", "HT", "2T", "64", "34", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "FCC", "5G", "20M", "HT", "2T", "100", "32", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "104", "36", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "38", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "38", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "38", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "38", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "38", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "38", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "38", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "36", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "32", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "FCC", "5G", "20M", "HT", "2T", "149", "38", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "38", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "38", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "38", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "38", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "28", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "FCC", "5G", "40M", "HT", "1T", "46", "36", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "36", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "30", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "FCC", "5G", "40M", "HT", "1T", "102", "30", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "36", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "36", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "36", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "36", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "36", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "36", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "26", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "FCC", "5G", "40M", "HT", "2T", "46", "36", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "FCC", "5G", "40M", "HT", "2T", "54", "36", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "FCC", "5G", "40M", "HT", "2T", "62", "28", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "FCC", "5G", "40M", "HT", "2T", "102", "28", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "36", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "36", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "36", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "36", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "FCC", "5G", "40M", "HT", "2T", "151", "36", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "36", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "26", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "26", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "26", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "36", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "36", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "36", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "24", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "FCC", "5G", "80M", "VHT", "2T", "58", "24", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "FCC", "5G", "80M", "VHT", "2T", "106", "26", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "36", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "138", "36", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "FCC", "5G", "80M", "VHT", "2T", "155", "36", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type4( + struct dm_struct *dm +) +{ + u32 i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type4)/sizeof(u8); + u8 *array = (u8 *)array_mp_8822b_txpwr_lmt_type4; +#else + u32 array_len = sizeof(array_mp_8822b_txpwr_lmt_type4)/sizeof(u8 *); + u8 **array = (u8 **)array_mp_8822b_txpwr_lmt_type4; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len/7; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_txpwr_lmt_type4\n"); + + for (i = 0; i < array_len; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u8 regulation = array[i]; + u8 band = array[i+1]; + u8 bandwidth = array[i+2]; + u8 rate = array[i+3]; + u8 rf_path = array[i+4]; + u8 chnl = array[i+5]; + u8 val = array[i+6]; +#else + u8 *regulation = array[i]; + u8 *band = array[i+1]; + u8 *bandwidth = array[i+2]; + u8 *rate = array[i+3]; + u8 *rf_path = array[i+4]; + u8 *chnl = array[i+5]; + u8 *val = array[i+6]; +#endif + + odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rf_path, chnl, val); +#endif + } + +} + +/****************************************************************************** +* txpwr_lmt_type5.TXT +******************************************************************************/ + +const char *array_mp_8822b_txpwr_lmt_type5[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "30", + "IC", "2.4G", "20M", "CCK", "1T", "01", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "01", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "01", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "30", + "IC", "2.4G", "20M", "CCK", "1T", "02", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "02", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "02", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "30", + "IC", "2.4G", "20M", "CCK", "1T", "03", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "03", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "03", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "30", + "IC", "2.4G", "20M", "CCK", "1T", "04", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "04", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "04", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "30", + "IC", "2.4G", "20M", "CCK", "1T", "05", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "05", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "05", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "30", + "IC", "2.4G", "20M", "CCK", "1T", "06", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "06", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "06", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "30", + "IC", "2.4G", "20M", "CCK", "1T", "07", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "07", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "07", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "30", + "IC", "2.4G", "20M", "CCK", "1T", "08", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "08", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "08", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "30", + "IC", "2.4G", "20M", "CCK", "1T", "09", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "09", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "09", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "30", + "IC", "2.4G", "20M", "CCK", "1T", "10", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "10", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "10", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "30", + "IC", "2.4G", "20M", "CCK", "1T", "11", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "11", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "11", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "30", + "IC", "2.4G", "20M", "CCK", "1T", "12", "26", + "KCC", "2.4G", "20M", "CCK", "1T", "12", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "12", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "12", "26", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "28", + "IC", "2.4G", "20M", "CCK", "1T", "13", "20", + "KCC", "2.4G", "20M", "CCK", "1T", "13", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "13", "28", + "CHILE", "2.4G", "20M", "CCK", "1T", "13", "20", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "IC", "2.4G", "20M", "CCK", "1T", "14", "63", + "KCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ACMA", "2.4G", "20M", "CCK", "1T", "14", "63", + "CHILE", "2.4G", "20M", "CCK", "1T", "14", "63", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "01", "26", + "KCC", "2.4G", "20M", "OFDM", "1T", "01", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "01", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "01", "26", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "02", "30", + "KCC", "2.4G", "20M", "OFDM", "1T", "02", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "02", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "02", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "03", "32", + "KCC", "2.4G", "20M", "OFDM", "1T", "03", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "03", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "03", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "04", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "05", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "06", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "07", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "08", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "09", "32", + "KCC", "2.4G", "20M", "OFDM", "1T", "09", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "09", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "09", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "10", "30", + "KCC", "2.4G", "20M", "OFDM", "1T", "10", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "10", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "10", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "KCC", "2.4G", "20M", "OFDM", "1T", "11", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "11", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "11", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "12", "22", + "KCC", "2.4G", "20M", "OFDM", "1T", "12", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "12", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "12", "22", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "13", "14", + "KCC", "2.4G", "20M", "OFDM", "1T", "13", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "13", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "13", "14", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "IC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "KCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ACMA", "2.4G", "20M", "OFDM", "1T", "14", "63", + "CHILE", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "IC", "2.4G", "20M", "HT", "1T", "01", "26", + "KCC", "2.4G", "20M", "HT", "1T", "01", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "01", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "01", "26", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "IC", "2.4G", "20M", "HT", "1T", "02", "30", + "KCC", "2.4G", "20M", "HT", "1T", "02", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "02", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "02", "30", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "IC", "2.4G", "20M", "HT", "1T", "03", "32", + "KCC", "2.4G", "20M", "HT", "1T", "03", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "03", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "IC", "2.4G", "20M", "HT", "1T", "04", "34", + "KCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "04", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "IC", "2.4G", "20M", "HT", "1T", "05", "34", + "KCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "05", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "IC", "2.4G", "20M", "HT", "1T", "06", "34", + "KCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "06", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "IC", "2.4G", "20M", "HT", "1T", "07", "34", + "KCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "07", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "IC", "2.4G", "20M", "HT", "1T", "08", "34", + "KCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "08", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "IC", "2.4G", "20M", "HT", "1T", "09", "32", + "KCC", "2.4G", "20M", "HT", "1T", "09", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "09", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "IC", "2.4G", "20M", "HT", "1T", "10", "30", + "KCC", "2.4G", "20M", "HT", "1T", "10", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "10", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "10", "30", + "FCC", "2.4G", "20M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "IC", "2.4G", "20M", "HT", "1T", "11", "26", + "KCC", "2.4G", "20M", "HT", "1T", "11", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "11", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "11", "26", + "FCC", "2.4G", "20M", "HT", "1T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "IC", "2.4G", "20M", "HT", "1T", "12", "20", + "KCC", "2.4G", "20M", "HT", "1T", "12", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "12", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "12", "20", + "FCC", "2.4G", "20M", "HT", "1T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "IC", "2.4G", "20M", "HT", "1T", "13", "14", + "KCC", "2.4G", "20M", "HT", "1T", "13", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "13", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "13", "14", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "IC", "2.4G", "20M", "HT", "1T", "14", "63", + "KCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ACMA", "2.4G", "20M", "HT", "1T", "14", "63", + "CHILE", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "18", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "IC", "2.4G", "20M", "HT", "2T", "01", "26", + "KCC", "2.4G", "20M", "HT", "2T", "01", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "01", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "01", "26", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "IC", "2.4G", "20M", "HT", "2T", "02", "28", + "KCC", "2.4G", "20M", "HT", "2T", "02", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "02", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "02", "28", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "18", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "IC", "2.4G", "20M", "HT", "2T", "03", "30", + "KCC", "2.4G", "20M", "HT", "2T", "03", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "03", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "18", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "IC", "2.4G", "20M", "HT", "2T", "04", "30", + "KCC", "2.4G", "20M", "HT", "2T", "04", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "04", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "IC", "2.4G", "20M", "HT", "2T", "05", "32", + "KCC", "2.4G", "20M", "HT", "2T", "05", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "05", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "05", "32", + "FCC", "2.4G", "20M", "HT", "2T", "06", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "18", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "IC", "2.4G", "20M", "HT", "2T", "06", "32", + "KCC", "2.4G", "20M", "HT", "2T", "06", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "06", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "06", "32", + "FCC", "2.4G", "20M", "HT", "2T", "07", "32", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "18", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "IC", "2.4G", "20M", "HT", "2T", "07", "32", + "KCC", "2.4G", "20M", "HT", "2T", "07", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "07", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "07", "32", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "IC", "2.4G", "20M", "HT", "2T", "08", "30", + "KCC", "2.4G", "20M", "HT", "2T", "08", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "08", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "18", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "IC", "2.4G", "20M", "HT", "2T", "09", "30", + "KCC", "2.4G", "20M", "HT", "2T", "09", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "09", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "18", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "IC", "2.4G", "20M", "HT", "2T", "10", "28", + "KCC", "2.4G", "20M", "HT", "2T", "10", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "10", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "10", "28", + "FCC", "2.4G", "20M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "IC", "2.4G", "20M", "HT", "2T", "11", "26", + "KCC", "2.4G", "20M", "HT", "2T", "11", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "11", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "11", "26", + "FCC", "2.4G", "20M", "HT", "2T", "12", "20", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "18", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "IC", "2.4G", "20M", "HT", "2T", "12", "20", + "KCC", "2.4G", "20M", "HT", "2T", "12", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "12", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "12", "20", + "FCC", "2.4G", "20M", "HT", "2T", "13", "14", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "18", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "IC", "2.4G", "20M", "HT", "2T", "13", "14", + "KCC", "2.4G", "20M", "HT", "2T", "13", "34", + "ACMA", "2.4G", "20M", "HT", "2T", "13", "18", + "CHILE", "2.4G", "20M", "HT", "2T", "13", "14", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "IC", "2.4G", "20M", "HT", "2T", "14", "63", + "KCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ACMA", "2.4G", "20M", "HT", "2T", "14", "63", + "CHILE", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "IC", "2.4G", "40M", "HT", "1T", "01", "63", + "KCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "01", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "IC", "2.4G", "40M", "HT", "1T", "02", "63", + "KCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "02", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "34", + "IC", "2.4G", "40M", "HT", "1T", "03", "26", + "KCC", "2.4G", "40M", "HT", "1T", "03", "34", + "ACMA", "2.4G", "40M", "HT", "1T", "03", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "03", "26", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "34", + "IC", "2.4G", "40M", "HT", "1T", "04", "26", + "KCC", "2.4G", "40M", "HT", "1T", "04", "34", + "ACMA", "2.4G", "40M", "HT", "1T", "04", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "04", "26", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "34", + "IC", "2.4G", "40M", "HT", "1T", "05", "30", + "KCC", "2.4G", "40M", "HT", "1T", "05", "34", + "ACMA", "2.4G", "40M", "HT", "1T", "05", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "05", "30", + "FCC", "2.4G", "40M", "HT", "1T", "06", "32", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "34", + "IC", "2.4G", "40M", "HT", "1T", "06", "32", + "KCC", "2.4G", "40M", "HT", "1T", "06", "34", + "ACMA", "2.4G", "40M", "HT", "1T", "06", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "06", "32", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "34", + "IC", "2.4G", "40M", "HT", "1T", "07", "30", + "KCC", "2.4G", "40M", "HT", "1T", "07", "34", + "ACMA", "2.4G", "40M", "HT", "1T", "07", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "07", "30", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "34", + "IC", "2.4G", "40M", "HT", "1T", "08", "26", + "KCC", "2.4G", "40M", "HT", "1T", "08", "34", + "ACMA", "2.4G", "40M", "HT", "1T", "08", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "08", "26", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "34", + "IC", "2.4G", "40M", "HT", "1T", "09", "26", + "KCC", "2.4G", "40M", "HT", "1T", "09", "34", + "ACMA", "2.4G", "40M", "HT", "1T", "09", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "09", "26", + "FCC", "2.4G", "40M", "HT", "1T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "34", + "IC", "2.4G", "40M", "HT", "1T", "10", "20", + "KCC", "2.4G", "40M", "HT", "1T", "10", "34", + "ACMA", "2.4G", "40M", "HT", "1T", "10", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "10", "20", + "FCC", "2.4G", "40M", "HT", "1T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "34", + "IC", "2.4G", "40M", "HT", "1T", "11", "14", + "KCC", "2.4G", "40M", "HT", "1T", "11", "34", + "ACMA", "2.4G", "40M", "HT", "1T", "11", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "11", "14", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "IC", "2.4G", "40M", "HT", "1T", "12", "63", + "KCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "12", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "IC", "2.4G", "40M", "HT", "1T", "13", "63", + "KCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "13", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "IC", "2.4G", "40M", "HT", "1T", "14", "63", + "KCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "14", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "IC", "2.4G", "40M", "HT", "2T", "01", "63", + "KCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ACMA", "2.4G", "40M", "HT", "2T", "01", "63", + "CHILE", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "IC", "2.4G", "40M", "HT", "2T", "02", "63", + "KCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ACMA", "2.4G", "40M", "HT", "2T", "02", "63", + "CHILE", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "18", + "MKK", "2.4G", "40M", "HT", "2T", "03", "30", + "IC", "2.4G", "40M", "HT", "2T", "03", "24", + "KCC", "2.4G", "40M", "HT", "2T", "03", "34", + "ACMA", "2.4G", "40M", "HT", "2T", "03", "18", + "CHILE", "2.4G", "40M", "HT", "2T", "03", "24", + "FCC", "2.4G", "40M", "HT", "2T", "04", "24", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", + "MKK", "2.4G", "40M", "HT", "2T", "04", "30", + "IC", "2.4G", "40M", "HT", "2T", "04", "24", + "KCC", "2.4G", "40M", "HT", "2T", "04", "34", + "ACMA", "2.4G", "40M", "HT", "2T", "04", "18", + "CHILE", "2.4G", "40M", "HT", "2T", "04", "24", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "18", + "MKK", "2.4G", "40M", "HT", "2T", "05", "30", + "IC", "2.4G", "40M", "HT", "2T", "05", "26", + "KCC", "2.4G", "40M", "HT", "2T", "05", "34", + "ACMA", "2.4G", "40M", "HT", "2T", "05", "18", + "CHILE", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "28", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "18", + "MKK", "2.4G", "40M", "HT", "2T", "06", "30", + "IC", "2.4G", "40M", "HT", "2T", "06", "28", + "KCC", "2.4G", "40M", "HT", "2T", "06", "34", + "ACMA", "2.4G", "40M", "HT", "2T", "06", "18", + "CHILE", "2.4G", "40M", "HT", "2T", "06", "28", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", + "MKK", "2.4G", "40M", "HT", "2T", "07", "30", + "IC", "2.4G", "40M", "HT", "2T", "07", "26", + "KCC", "2.4G", "40M", "HT", "2T", "07", "34", + "ACMA", "2.4G", "40M", "HT", "2T", "07", "18", + "CHILE", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "18", + "MKK", "2.4G", "40M", "HT", "2T", "08", "30", + "IC", "2.4G", "40M", "HT", "2T", "08", "26", + "KCC", "2.4G", "40M", "HT", "2T", "08", "34", + "ACMA", "2.4G", "40M", "HT", "2T", "08", "18", + "CHILE", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "18", + "MKK", "2.4G", "40M", "HT", "2T", "09", "30", + "IC", "2.4G", "40M", "HT", "2T", "09", "26", + "KCC", "2.4G", "40M", "HT", "2T", "09", "34", + "ACMA", "2.4G", "40M", "HT", "2T", "09", "18", + "CHILE", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "20", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", + "MKK", "2.4G", "40M", "HT", "2T", "10", "30", + "IC", "2.4G", "40M", "HT", "2T", "10", "20", + "KCC", "2.4G", "40M", "HT", "2T", "10", "34", + "ACMA", "2.4G", "40M", "HT", "2T", "10", "18", + "CHILE", "2.4G", "40M", "HT", "2T", "10", "20", + "FCC", "2.4G", "40M", "HT", "2T", "11", "14", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "18", + "MKK", "2.4G", "40M", "HT", "2T", "11", "30", + "IC", "2.4G", "40M", "HT", "2T", "11", "14", + "KCC", "2.4G", "40M", "HT", "2T", "11", "34", + "ACMA", "2.4G", "40M", "HT", "2T", "11", "18", + "CHILE", "2.4G", "40M", "HT", "2T", "11", "14", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "63", + "MKK", "2.4G", "40M", "HT", "2T", "12", "63", + "IC", "2.4G", "40M", "HT", "2T", "12", "63", + "KCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ACMA", "2.4G", "40M", "HT", "2T", "12", "63", + "CHILE", "2.4G", "40M", "HT", "2T", "12", "63", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", + "MKK", "2.4G", "40M", "HT", "2T", "13", "63", + "IC", "2.4G", "40M", "HT", "2T", "13", "63", + "KCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ACMA", "2.4G", "40M", "HT", "2T", "13", "63", + "CHILE", "2.4G", "40M", "HT", "2T", "13", "63", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "IC", "2.4G", "40M", "HT", "2T", "14", "63", + "KCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ACMA", "2.4G", "40M", "HT", "2T", "14", "63", + "CHILE", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "30", + "IC", "5G", "20M", "OFDM", "1T", "36", "30", + "KCC", "5G", "20M", "OFDM", "1T", "36", "18", + "ACMA", "5G", "20M", "OFDM", "1T", "36", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "36", "30", + "FCC", "5G", "20M", "OFDM", "1T", "40", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "30", + "IC", "5G", "20M", "OFDM", "1T", "40", "30", + "KCC", "5G", "20M", "OFDM", "1T", "40", "24", + "ACMA", "5G", "20M", "OFDM", "1T", "40", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "40", "30", + "FCC", "5G", "20M", "OFDM", "1T", "44", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "30", + "IC", "5G", "20M", "OFDM", "1T", "44", "30", + "KCC", "5G", "20M", "OFDM", "1T", "44", "24", + "ACMA", "5G", "20M", "OFDM", "1T", "44", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "30", + "IC", "5G", "20M", "OFDM", "1T", "48", "30", + "KCC", "5G", "20M", "OFDM", "1T", "48", "18", + "ACMA", "5G", "20M", "OFDM", "1T", "48", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "28", + "IC", "5G", "20M", "OFDM", "1T", "52", "32", + "KCC", "5G", "20M", "OFDM", "1T", "52", "10", + "ACMA", "5G", "20M", "OFDM", "1T", "52", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "52", "30", + "FCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "28", + "IC", "5G", "20M", "OFDM", "1T", "56", "32", + "KCC", "5G", "20M", "OFDM", "1T", "56", "32", + "ACMA", "5G", "20M", "OFDM", "1T", "56", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "56", "30", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "28", + "IC", "5G", "20M", "OFDM", "1T", "60", "32", + "KCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ACMA", "5G", "20M", "OFDM", "1T", "60", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "60", "30", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "28", + "IC", "5G", "20M", "OFDM", "1T", "64", "28", + "KCC", "5G", "20M", "OFDM", "1T", "64", "32", + "ACMA", "5G", "20M", "OFDM", "1T", "64", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "64", "30", + "FCC", "5G", "20M", "OFDM", "1T", "100", "26", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "IC", "5G", "20M", "OFDM", "1T", "100", "26", + "KCC", "5G", "20M", "OFDM", "1T", "100", "32", + "ACMA", "5G", "20M", "OFDM", "1T", "100", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "100", "30", + "FCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "32", + "IC", "5G", "20M", "OFDM", "1T", "104", "32", + "KCC", "5G", "20M", "OFDM", "1T", "104", "32", + "ACMA", "5G", "20M", "OFDM", "1T", "104", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "104", "30", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "IC", "5G", "20M", "OFDM", "1T", "108", "32", + "KCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ACMA", "5G", "20M", "OFDM", "1T", "108", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "108", "30", + "FCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "IC", "5G", "20M", "OFDM", "1T", "112", "32", + "KCC", "5G", "20M", "OFDM", "1T", "112", "32", + "ACMA", "5G", "20M", "OFDM", "1T", "112", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "112", "30", + "FCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "IC", "5G", "20M", "OFDM", "1T", "116", "32", + "KCC", "5G", "20M", "OFDM", "1T", "116", "32", + "ACMA", "5G", "20M", "OFDM", "1T", "116", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "116", "30", + "FCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "IC", "5G", "20M", "OFDM", "1T", "120", "-63", + "KCC", "5G", "20M", "OFDM", "1T", "120", "32", + "ACMA", "5G", "20M", "OFDM", "1T", "120", "-63", + "CHILE", "5G", "20M", "OFDM", "1T", "120", "30", + "FCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "IC", "5G", "20M", "OFDM", "1T", "124", "-63", + "KCC", "5G", "20M", "OFDM", "1T", "124", "32", + "ACMA", "5G", "20M", "OFDM", "1T", "124", "-63", + "CHILE", "5G", "20M", "OFDM", "1T", "124", "30", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "IC", "5G", "20M", "OFDM", "1T", "128", "-63", + "KCC", "5G", "20M", "OFDM", "1T", "128", "-63", + "ACMA", "5G", "20M", "OFDM", "1T", "128", "-63", + "CHILE", "5G", "20M", "OFDM", "1T", "128", "30", + "FCC", "5G", "20M", "OFDM", "1T", "132", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "IC", "5G", "20M", "OFDM", "1T", "132", "32", + "KCC", "5G", "20M", "OFDM", "1T", "132", "-63", + "ACMA", "5G", "20M", "OFDM", "1T", "132", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "132", "30", + "FCC", "5G", "20M", "OFDM", "1T", "136", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "IC", "5G", "20M", "OFDM", "1T", "136", "32", + "KCC", "5G", "20M", "OFDM", "1T", "136", "-63", + "ACMA", "5G", "20M", "OFDM", "1T", "136", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "136", "30", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "IC", "5G", "20M", "OFDM", "1T", "140", "28", + "KCC", "5G", "20M", "OFDM", "1T", "140", "-63", + "ACMA", "5G", "20M", "OFDM", "1T", "140", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "140", "30", + "FCC", "5G", "20M", "OFDM", "1T", "144", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "63", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "IC", "5G", "20M", "OFDM", "1T", "144", "28", + "KCC", "5G", "20M", "OFDM", "1T", "144", "-63", + "ACMA", "5G", "20M", "OFDM", "1T", "144", "-63", + "CHILE", "5G", "20M", "OFDM", "1T", "144", "30", + "FCC", "5G", "20M", "OFDM", "1T", "149", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "IC", "5G", "20M", "OFDM", "1T", "149", "32", + "KCC", "5G", "20M", "OFDM", "1T", "149", "26", + "ACMA", "5G", "20M", "OFDM", "1T", "149", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "149", "30", + "FCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "IC", "5G", "20M", "OFDM", "1T", "153", "32", + "KCC", "5G", "20M", "OFDM", "1T", "153", "32", + "ACMA", "5G", "20M", "OFDM", "1T", "153", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "153", "30", + "FCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "IC", "5G", "20M", "OFDM", "1T", "157", "32", + "KCC", "5G", "20M", "OFDM", "1T", "157", "32", + "ACMA", "5G", "20M", "OFDM", "1T", "157", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "157", "30", + "FCC", "5G", "20M", "OFDM", "1T", "161", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "IC", "5G", "20M", "OFDM", "1T", "161", "32", + "KCC", "5G", "20M", "OFDM", "1T", "161", "30", + "ACMA", "5G", "20M", "OFDM", "1T", "161", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "161", "30", + "FCC", "5G", "20M", "OFDM", "1T", "165", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "IC", "5G", "20M", "OFDM", "1T", "165", "32", + "KCC", "5G", "20M", "OFDM", "1T", "165", "-63", + "ACMA", "5G", "20M", "OFDM", "1T", "165", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "165", "30", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "28", + "IC", "5G", "20M", "HT", "1T", "36", "30", + "KCC", "5G", "20M", "HT", "1T", "36", "18", + "ACMA", "5G", "20M", "HT", "1T", "36", "32", + "CHILE", "5G", "20M", "HT", "1T", "36", "30", + "FCC", "5G", "20M", "HT", "1T", "40", "32", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "28", + "IC", "5G", "20M", "HT", "1T", "40", "30", + "KCC", "5G", "20M", "HT", "1T", "40", "24", + "ACMA", "5G", "20M", "HT", "1T", "40", "32", + "CHILE", "5G", "20M", "HT", "1T", "40", "30", + "FCC", "5G", "20M", "HT", "1T", "44", "32", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "28", + "IC", "5G", "20M", "HT", "1T", "44", "30", + "KCC", "5G", "20M", "HT", "1T", "44", "24", + "ACMA", "5G", "20M", "HT", "1T", "44", "32", + "CHILE", "5G", "20M", "HT", "1T", "44", "30", + "FCC", "5G", "20M", "HT", "1T", "48", "32", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "28", + "IC", "5G", "20M", "HT", "1T", "48", "30", + "KCC", "5G", "20M", "HT", "1T", "48", "18", + "ACMA", "5G", "20M", "HT", "1T", "48", "32", + "CHILE", "5G", "20M", "HT", "1T", "48", "30", + "FCC", "5G", "20M", "HT", "1T", "52", "32", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "28", + "IC", "5G", "20M", "HT", "1T", "52", "32", + "KCC", "5G", "20M", "HT", "1T", "52", "4", + "ACMA", "5G", "20M", "HT", "1T", "52", "32", + "CHILE", "5G", "20M", "HT", "1T", "52", "30", + "FCC", "5G", "20M", "HT", "1T", "56", "32", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "28", + "IC", "5G", "20M", "HT", "1T", "56", "32", + "KCC", "5G", "20M", "HT", "1T", "56", "32", + "ACMA", "5G", "20M", "HT", "1T", "56", "32", + "CHILE", "5G", "20M", "HT", "1T", "56", "30", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "28", + "IC", "5G", "20M", "HT", "1T", "60", "32", + "KCC", "5G", "20M", "HT", "1T", "60", "32", + "ACMA", "5G", "20M", "HT", "1T", "60", "32", + "CHILE", "5G", "20M", "HT", "1T", "60", "30", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "28", + "IC", "5G", "20M", "HT", "1T", "64", "28", + "KCC", "5G", "20M", "HT", "1T", "64", "32", + "ACMA", "5G", "20M", "HT", "1T", "64", "32", + "CHILE", "5G", "20M", "HT", "1T", "64", "30", + "FCC", "5G", "20M", "HT", "1T", "100", "26", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "IC", "5G", "20M", "HT", "1T", "100", "26", + "KCC", "5G", "20M", "HT", "1T", "100", "32", + "ACMA", "5G", "20M", "HT", "1T", "100", "32", + "CHILE", "5G", "20M", "HT", "1T", "100", "30", + "FCC", "5G", "20M", "HT", "1T", "104", "32", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "32", + "IC", "5G", "20M", "HT", "1T", "104", "32", + "KCC", "5G", "20M", "HT", "1T", "104", "32", + "ACMA", "5G", "20M", "HT", "1T", "104", "32", + "CHILE", "5G", "20M", "HT", "1T", "104", "30", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "IC", "5G", "20M", "HT", "1T", "108", "32", + "KCC", "5G", "20M", "HT", "1T", "108", "32", + "ACMA", "5G", "20M", "HT", "1T", "108", "32", + "CHILE", "5G", "20M", "HT", "1T", "108", "30", + "FCC", "5G", "20M", "HT", "1T", "112", "32", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "IC", "5G", "20M", "HT", "1T", "112", "32", + "KCC", "5G", "20M", "HT", "1T", "112", "32", + "ACMA", "5G", "20M", "HT", "1T", "112", "32", + "CHILE", "5G", "20M", "HT", "1T", "112", "30", + "FCC", "5G", "20M", "HT", "1T", "116", "32", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "IC", "5G", "20M", "HT", "1T", "116", "32", + "KCC", "5G", "20M", "HT", "1T", "116", "32", + "ACMA", "5G", "20M", "HT", "1T", "116", "32", + "CHILE", "5G", "20M", "HT", "1T", "116", "30", + "FCC", "5G", "20M", "HT", "1T", "120", "32", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "IC", "5G", "20M", "HT", "1T", "120", "-63", + "KCC", "5G", "20M", "HT", "1T", "120", "32", + "ACMA", "5G", "20M", "HT", "1T", "120", "-63", + "CHILE", "5G", "20M", "HT", "1T", "120", "30", + "FCC", "5G", "20M", "HT", "1T", "124", "32", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "IC", "5G", "20M", "HT", "1T", "124", "-63", + "KCC", "5G", "20M", "HT", "1T", "124", "32", + "ACMA", "5G", "20M", "HT", "1T", "124", "-63", + "CHILE", "5G", "20M", "HT", "1T", "124", "30", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "IC", "5G", "20M", "HT", "1T", "128", "-63", + "KCC", "5G", "20M", "HT", "1T", "128", "-63", + "ACMA", "5G", "20M", "HT", "1T", "128", "-63", + "CHILE", "5G", "20M", "HT", "1T", "128", "30", + "FCC", "5G", "20M", "HT", "1T", "132", "32", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "IC", "5G", "20M", "HT", "1T", "132", "32", + "KCC", "5G", "20M", "HT", "1T", "132", "-63", + "ACMA", "5G", "20M", "HT", "1T", "132", "32", + "CHILE", "5G", "20M", "HT", "1T", "132", "30", + "FCC", "5G", "20M", "HT", "1T", "136", "32", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "IC", "5G", "20M", "HT", "1T", "136", "32", + "KCC", "5G", "20M", "HT", "1T", "136", "-63", + "ACMA", "5G", "20M", "HT", "1T", "136", "32", + "CHILE", "5G", "20M", "HT", "1T", "136", "30", + "FCC", "5G", "20M", "HT", "1T", "140", "26", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "IC", "5G", "20M", "HT", "1T", "140", "26", + "KCC", "5G", "20M", "HT", "1T", "140", "-63", + "ACMA", "5G", "20M", "HT", "1T", "140", "32", + "CHILE", "5G", "20M", "HT", "1T", "140", "30", + "FCC", "5G", "20M", "HT", "1T", "144", "26", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "IC", "5G", "20M", "HT", "1T", "144", "26", + "KCC", "5G", "20M", "HT", "1T", "144", "-63", + "ACMA", "5G", "20M", "HT", "1T", "144", "-63", + "CHILE", "5G", "20M", "HT", "1T", "144", "30", + "FCC", "5G", "20M", "HT", "1T", "149", "32", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "IC", "5G", "20M", "HT", "1T", "149", "32", + "KCC", "5G", "20M", "HT", "1T", "149", "24", + "ACMA", "5G", "20M", "HT", "1T", "149", "32", + "CHILE", "5G", "20M", "HT", "1T", "149", "30", + "FCC", "5G", "20M", "HT", "1T", "153", "32", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "IC", "5G", "20M", "HT", "1T", "153", "32", + "KCC", "5G", "20M", "HT", "1T", "153", "32", + "ACMA", "5G", "20M", "HT", "1T", "153", "32", + "CHILE", "5G", "20M", "HT", "1T", "153", "30", + "FCC", "5G", "20M", "HT", "1T", "157", "32", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "IC", "5G", "20M", "HT", "1T", "157", "32", + "KCC", "5G", "20M", "HT", "1T", "157", "32", + "ACMA", "5G", "20M", "HT", "1T", "157", "32", + "CHILE", "5G", "20M", "HT", "1T", "157", "30", + "FCC", "5G", "20M", "HT", "1T", "161", "32", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "IC", "5G", "20M", "HT", "1T", "161", "32", + "KCC", "5G", "20M", "HT", "1T", "161", "30", + "ACMA", "5G", "20M", "HT", "1T", "161", "32", + "CHILE", "5G", "20M", "HT", "1T", "161", "30", + "FCC", "5G", "20M", "HT", "1T", "165", "32", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "IC", "5G", "20M", "HT", "1T", "165", "32", + "KCC", "5G", "20M", "HT", "1T", "165", "-63", + "ACMA", "5G", "20M", "HT", "1T", "165", "32", + "CHILE", "5G", "20M", "HT", "1T", "165", "30", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "20", + "MKK", "5G", "20M", "HT", "2T", "36", "22", + "IC", "5G", "20M", "HT", "2T", "36", "18", + "KCC", "5G", "20M", "HT", "2T", "36", "18", + "ACMA", "5G", "20M", "HT", "2T", "36", "20", + "CHILE", "5G", "20M", "HT", "2T", "36", "18", + "FCC", "5G", "20M", "HT", "2T", "40", "30", + "ETSI", "5G", "20M", "HT", "2T", "40", "20", + "MKK", "5G", "20M", "HT", "2T", "40", "22", + "IC", "5G", "20M", "HT", "2T", "40", "18", + "KCC", "5G", "20M", "HT", "2T", "40", "18", + "ACMA", "5G", "20M", "HT", "2T", "40", "20", + "CHILE", "5G", "20M", "HT", "2T", "40", "18", + "FCC", "5G", "20M", "HT", "2T", "44", "30", + "ETSI", "5G", "20M", "HT", "2T", "44", "20", + "MKK", "5G", "20M", "HT", "2T", "44", "22", + "IC", "5G", "20M", "HT", "2T", "44", "18", + "KCC", "5G", "20M", "HT", "2T", "44", "18", + "ACMA", "5G", "20M", "HT", "2T", "44", "20", + "CHILE", "5G", "20M", "HT", "2T", "44", "18", + "FCC", "5G", "20M", "HT", "2T", "48", "30", + "ETSI", "5G", "20M", "HT", "2T", "48", "20", + "MKK", "5G", "20M", "HT", "2T", "48", "22", + "IC", "5G", "20M", "HT", "2T", "48", "18", + "KCC", "5G", "20M", "HT", "2T", "48", "18", + "ACMA", "5G", "20M", "HT", "2T", "48", "20", + "CHILE", "5G", "20M", "HT", "2T", "48", "18", + "FCC", "5G", "20M", "HT", "2T", "52", "30", + "ETSI", "5G", "20M", "HT", "2T", "52", "20", + "MKK", "5G", "20M", "HT", "2T", "52", "22", + "IC", "5G", "20M", "HT", "2T", "52", "20", + "KCC", "5G", "20M", "HT", "2T", "52", "4", + "ACMA", "5G", "20M", "HT", "2T", "52", "20", + "CHILE", "5G", "20M", "HT", "2T", "52", "18", + "FCC", "5G", "20M", "HT", "2T", "56", "30", + "ETSI", "5G", "20M", "HT", "2T", "56", "20", + "MKK", "5G", "20M", "HT", "2T", "56", "22", + "IC", "5G", "20M", "HT", "2T", "56", "20", + "KCC", "5G", "20M", "HT", "2T", "56", "32", + "ACMA", "5G", "20M", "HT", "2T", "56", "20", + "CHILE", "5G", "20M", "HT", "2T", "56", "18", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "20", + "MKK", "5G", "20M", "HT", "2T", "60", "22", + "IC", "5G", "20M", "HT", "2T", "60", "20", + "KCC", "5G", "20M", "HT", "2T", "60", "32", + "ACMA", "5G", "20M", "HT", "2T", "60", "20", + "CHILE", "5G", "20M", "HT", "2T", "60", "18", + "FCC", "5G", "20M", "HT", "2T", "64", "28", + "ETSI", "5G", "20M", "HT", "2T", "64", "20", + "MKK", "5G", "20M", "HT", "2T", "64", "22", + "IC", "5G", "20M", "HT", "2T", "64", "20", + "KCC", "5G", "20M", "HT", "2T", "64", "32", + "ACMA", "5G", "20M", "HT", "2T", "64", "20", + "CHILE", "5G", "20M", "HT", "2T", "64", "18", + "FCC", "5G", "20M", "HT", "2T", "100", "26", + "ETSI", "5G", "20M", "HT", "2T", "100", "20", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "IC", "5G", "20M", "HT", "2T", "100", "26", + "KCC", "5G", "20M", "HT", "2T", "100", "32", + "ACMA", "5G", "20M", "HT", "2T", "100", "20", + "CHILE", "5G", "20M", "HT", "2T", "100", "18", + "FCC", "5G", "20M", "HT", "2T", "104", "30", + "ETSI", "5G", "20M", "HT", "2T", "104", "20", + "MKK", "5G", "20M", "HT", "2T", "104", "30", + "IC", "5G", "20M", "HT", "2T", "104", "30", + "KCC", "5G", "20M", "HT", "2T", "104", "32", + "ACMA", "5G", "20M", "HT", "2T", "104", "20", + "CHILE", "5G", "20M", "HT", "2T", "104", "18", + "FCC", "5G", "20M", "HT", "2T", "108", "32", + "ETSI", "5G", "20M", "HT", "2T", "108", "20", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "IC", "5G", "20M", "HT", "2T", "108", "32", + "KCC", "5G", "20M", "HT", "2T", "108", "32", + "ACMA", "5G", "20M", "HT", "2T", "108", "20", + "CHILE", "5G", "20M", "HT", "2T", "108", "18", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "20", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "IC", "5G", "20M", "HT", "2T", "112", "32", + "KCC", "5G", "20M", "HT", "2T", "112", "32", + "ACMA", "5G", "20M", "HT", "2T", "112", "20", + "CHILE", "5G", "20M", "HT", "2T", "112", "18", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "20", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "IC", "5G", "20M", "HT", "2T", "116", "32", + "KCC", "5G", "20M", "HT", "2T", "116", "32", + "ACMA", "5G", "20M", "HT", "2T", "116", "20", + "CHILE", "5G", "20M", "HT", "2T", "116", "18", + "FCC", "5G", "20M", "HT", "2T", "120", "32", + "ETSI", "5G", "20M", "HT", "2T", "120", "20", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "IC", "5G", "20M", "HT", "2T", "120", "-63", + "KCC", "5G", "20M", "HT", "2T", "120", "32", + "ACMA", "5G", "20M", "HT", "2T", "120", "-63", + "CHILE", "5G", "20M", "HT", "2T", "120", "18", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "20", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "IC", "5G", "20M", "HT", "2T", "124", "-63", + "KCC", "5G", "20M", "HT", "2T", "124", "32", + "ACMA", "5G", "20M", "HT", "2T", "124", "-63", + "CHILE", "5G", "20M", "HT", "2T", "124", "18", + "FCC", "5G", "20M", "HT", "2T", "128", "32", + "ETSI", "5G", "20M", "HT", "2T", "128", "20", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "IC", "5G", "20M", "HT", "2T", "128", "-63", + "KCC", "5G", "20M", "HT", "2T", "128", "-63", + "ACMA", "5G", "20M", "HT", "2T", "128", "-63", + "CHILE", "5G", "20M", "HT", "2T", "128", "18", + "FCC", "5G", "20M", "HT", "2T", "132", "32", + "ETSI", "5G", "20M", "HT", "2T", "132", "20", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "IC", "5G", "20M", "HT", "2T", "132", "32", + "KCC", "5G", "20M", "HT", "2T", "132", "-63", + "ACMA", "5G", "20M", "HT", "2T", "132", "20", + "CHILE", "5G", "20M", "HT", "2T", "132", "18", + "FCC", "5G", "20M", "HT", "2T", "136", "30", + "ETSI", "5G", "20M", "HT", "2T", "136", "20", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "IC", "5G", "20M", "HT", "2T", "136", "30", + "KCC", "5G", "20M", "HT", "2T", "136", "-63", + "ACMA", "5G", "20M", "HT", "2T", "136", "20", + "CHILE", "5G", "20M", "HT", "2T", "136", "18", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "20", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "IC", "5G", "20M", "HT", "2T", "140", "26", + "KCC", "5G", "20M", "HT", "2T", "140", "-63", + "ACMA", "5G", "20M", "HT", "2T", "140", "20", + "CHILE", "5G", "20M", "HT", "2T", "140", "18", + "FCC", "5G", "20M", "HT", "2T", "144", "26", + "ETSI", "5G", "20M", "HT", "2T", "144", "63", + "MKK", "5G", "20M", "HT", "2T", "144", "63", + "IC", "5G", "20M", "HT", "2T", "144", "26", + "KCC", "5G", "20M", "HT", "2T", "144", "-63", + "ACMA", "5G", "20M", "HT", "2T", "144", "-63", + "CHILE", "5G", "20M", "HT", "2T", "144", "18", + "FCC", "5G", "20M", "HT", "2T", "149", "32", + "ETSI", "5G", "20M", "HT", "2T", "149", "63", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "IC", "5G", "20M", "HT", "2T", "149", "32", + "KCC", "5G", "20M", "HT", "2T", "149", "24", + "ACMA", "5G", "20M", "HT", "2T", "149", "32", + "CHILE", "5G", "20M", "HT", "2T", "149", "18", + "FCC", "5G", "20M", "HT", "2T", "153", "32", + "ETSI", "5G", "20M", "HT", "2T", "153", "63", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "IC", "5G", "20M", "HT", "2T", "153", "32", + "KCC", "5G", "20M", "HT", "2T", "153", "30", + "ACMA", "5G", "20M", "HT", "2T", "153", "32", + "CHILE", "5G", "20M", "HT", "2T", "153", "18", + "FCC", "5G", "20M", "HT", "2T", "157", "32", + "ETSI", "5G", "20M", "HT", "2T", "157", "63", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "IC", "5G", "20M", "HT", "2T", "157", "32", + "KCC", "5G", "20M", "HT", "2T", "157", "30", + "ACMA", "5G", "20M", "HT", "2T", "157", "32", + "CHILE", "5G", "20M", "HT", "2T", "157", "18", + "FCC", "5G", "20M", "HT", "2T", "161", "32", + "ETSI", "5G", "20M", "HT", "2T", "161", "63", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "IC", "5G", "20M", "HT", "2T", "161", "32", + "KCC", "5G", "20M", "HT", "2T", "161", "30", + "ACMA", "5G", "20M", "HT", "2T", "161", "32", + "CHILE", "5G", "20M", "HT", "2T", "161", "18", + "FCC", "5G", "20M", "HT", "2T", "165", "32", + "ETSI", "5G", "20M", "HT", "2T", "165", "63", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "IC", "5G", "20M", "HT", "2T", "165", "32", + "KCC", "5G", "20M", "HT", "2T", "165", "-63", + "ACMA", "5G", "20M", "HT", "2T", "165", "32", + "CHILE", "5G", "20M", "HT", "2T", "165", "18", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "30", + "MKK", "5G", "40M", "HT", "1T", "38", "30", + "IC", "5G", "40M", "HT", "1T", "38", "22", + "KCC", "5G", "40M", "HT", "1T", "38", "18", + "ACMA", "5G", "40M", "HT", "1T", "38", "30", + "CHILE", "5G", "40M", "HT", "1T", "38", "22", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "30", + "MKK", "5G", "40M", "HT", "1T", "46", "30", + "IC", "5G", "40M", "HT", "1T", "46", "30", + "KCC", "5G", "40M", "HT", "1T", "46", "18", + "ACMA", "5G", "40M", "HT", "1T", "46", "30", + "CHILE", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "30", + "ETSI", "5G", "40M", "HT", "1T", "54", "30", + "MKK", "5G", "40M", "HT", "1T", "54", "30", + "IC", "5G", "40M", "HT", "1T", "54", "30", + "KCC", "5G", "40M", "HT", "1T", "54", "16", + "ACMA", "5G", "40M", "HT", "1T", "54", "30", + "CHILE", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "24", + "ETSI", "5G", "40M", "HT", "1T", "62", "30", + "MKK", "5G", "40M", "HT", "1T", "62", "30", + "IC", "5G", "40M", "HT", "1T", "62", "24", + "KCC", "5G", "40M", "HT", "1T", "62", "30", + "ACMA", "5G", "40M", "HT", "1T", "62", "30", + "CHILE", "5G", "40M", "HT", "1T", "62", "22", + "FCC", "5G", "40M", "HT", "1T", "102", "24", + "ETSI", "5G", "40M", "HT", "1T", "102", "30", + "MKK", "5G", "40M", "HT", "1T", "102", "30", + "IC", "5G", "40M", "HT", "1T", "102", "24", + "KCC", "5G", "40M", "HT", "1T", "102", "26", + "ACMA", "5G", "40M", "HT", "1T", "102", "30", + "CHILE", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "30", + "ETSI", "5G", "40M", "HT", "1T", "110", "30", + "MKK", "5G", "40M", "HT", "1T", "110", "30", + "IC", "5G", "40M", "HT", "1T", "110", "30", + "KCC", "5G", "40M", "HT", "1T", "110", "30", + "ACMA", "5G", "40M", "HT", "1T", "110", "30", + "CHILE", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "30", + "ETSI", "5G", "40M", "HT", "1T", "118", "30", + "MKK", "5G", "40M", "HT", "1T", "118", "30", + "IC", "5G", "40M", "HT", "1T", "118", "-63", + "KCC", "5G", "40M", "HT", "1T", "118", "30", + "ACMA", "5G", "40M", "HT", "1T", "118", "-63", + "CHILE", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "30", + "ETSI", "5G", "40M", "HT", "1T", "126", "30", + "MKK", "5G", "40M", "HT", "1T", "126", "30", + "IC", "5G", "40M", "HT", "1T", "126", "-63", + "KCC", "5G", "40M", "HT", "1T", "126", "-63", + "ACMA", "5G", "40M", "HT", "1T", "126", "-63", + "CHILE", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "30", + "ETSI", "5G", "40M", "HT", "1T", "134", "30", + "MKK", "5G", "40M", "HT", "1T", "134", "30", + "IC", "5G", "40M", "HT", "1T", "134", "30", + "KCC", "5G", "40M", "HT", "1T", "134", "-63", + "ACMA", "5G", "40M", "HT", "1T", "134", "30", + "CHILE", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "30", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "IC", "5G", "40M", "HT", "1T", "142", "30", + "KCC", "5G", "40M", "HT", "1T", "142", "-63", + "ACMA", "5G", "40M", "HT", "1T", "142", "-63", + "CHILE", "5G", "40M", "HT", "1T", "142", "30", + "FCC", "5G", "40M", "HT", "1T", "151", "30", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "IC", "5G", "40M", "HT", "1T", "151", "30", + "KCC", "5G", "40M", "HT", "1T", "151", "20", + "ACMA", "5G", "40M", "HT", "1T", "151", "30", + "CHILE", "5G", "40M", "HT", "1T", "151", "30", + "FCC", "5G", "40M", "HT", "1T", "159", "30", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "IC", "5G", "40M", "HT", "1T", "159", "30", + "KCC", "5G", "40M", "HT", "1T", "159", "24", + "ACMA", "5G", "40M", "HT", "1T", "159", "30", + "CHILE", "5G", "40M", "HT", "1T", "159", "30", + "FCC", "5G", "40M", "HT", "2T", "38", "20", + "ETSI", "5G", "40M", "HT", "2T", "38", "20", + "MKK", "5G", "40M", "HT", "2T", "38", "22", + "IC", "5G", "40M", "HT", "2T", "38", "20", + "KCC", "5G", "40M", "HT", "2T", "38", "18", + "ACMA", "5G", "40M", "HT", "2T", "38", "20", + "CHILE", "5G", "40M", "HT", "2T", "38", "18", + "FCC", "5G", "40M", "HT", "2T", "46", "30", + "ETSI", "5G", "40M", "HT", "2T", "46", "20", + "MKK", "5G", "40M", "HT", "2T", "46", "22", + "IC", "5G", "40M", "HT", "2T", "46", "18", + "KCC", "5G", "40M", "HT", "2T", "46", "18", + "ACMA", "5G", "40M", "HT", "2T", "46", "20", + "CHILE", "5G", "40M", "HT", "2T", "46", "18", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "20", + "MKK", "5G", "40M", "HT", "2T", "54", "22", + "IC", "5G", "40M", "HT", "2T", "54", "20", + "KCC", "5G", "40M", "HT", "2T", "54", "16", + "ACMA", "5G", "40M", "HT", "2T", "54", "20", + "CHILE", "5G", "40M", "HT", "2T", "54", "18", + "FCC", "5G", "40M", "HT", "2T", "62", "22", + "ETSI", "5G", "40M", "HT", "2T", "62", "20", + "MKK", "5G", "40M", "HT", "2T", "62", "22", + "IC", "5G", "40M", "HT", "2T", "62", "20", + "KCC", "5G", "40M", "HT", "2T", "62", "30", + "ACMA", "5G", "40M", "HT", "2T", "62", "20", + "CHILE", "5G", "40M", "HT", "2T", "62", "18", + "FCC", "5G", "40M", "HT", "2T", "102", "22", + "ETSI", "5G", "40M", "HT", "2T", "102", "20", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "IC", "5G", "40M", "HT", "2T", "102", "22", + "KCC", "5G", "40M", "HT", "2T", "102", "26", + "ACMA", "5G", "40M", "HT", "2T", "102", "20", + "CHILE", "5G", "40M", "HT", "2T", "102", "18", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "20", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "IC", "5G", "40M", "HT", "2T", "110", "30", + "KCC", "5G", "40M", "HT", "2T", "110", "30", + "ACMA", "5G", "40M", "HT", "2T", "110", "20", + "CHILE", "5G", "40M", "HT", "2T", "110", "18", + "FCC", "5G", "40M", "HT", "2T", "118", "30", + "ETSI", "5G", "40M", "HT", "2T", "118", "20", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "IC", "5G", "40M", "HT", "2T", "118", "-63", + "KCC", "5G", "40M", "HT", "2T", "118", "30", + "ACMA", "5G", "40M", "HT", "2T", "118", "-63", + "CHILE", "5G", "40M", "HT", "2T", "118", "18", + "FCC", "5G", "40M", "HT", "2T", "126", "30", + "ETSI", "5G", "40M", "HT", "2T", "126", "20", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "IC", "5G", "40M", "HT", "2T", "126", "-63", + "KCC", "5G", "40M", "HT", "2T", "126", "-63", + "ACMA", "5G", "40M", "HT", "2T", "126", "-63", + "CHILE", "5G", "40M", "HT", "2T", "126", "18", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "20", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "IC", "5G", "40M", "HT", "2T", "134", "30", + "KCC", "5G", "40M", "HT", "2T", "134", "-63", + "ACMA", "5G", "40M", "HT", "2T", "134", "20", + "CHILE", "5G", "40M", "HT", "2T", "134", "18", + "FCC", "5G", "40M", "HT", "2T", "142", "30", + "ETSI", "5G", "40M", "HT", "2T", "142", "63", + "MKK", "5G", "40M", "HT", "2T", "142", "63", + "IC", "5G", "40M", "HT", "2T", "142", "30", + "KCC", "5G", "40M", "HT", "2T", "142", "-63", + "ACMA", "5G", "40M", "HT", "2T", "142", "-63", + "CHILE", "5G", "40M", "HT", "2T", "142", "18", + "FCC", "5G", "40M", "HT", "2T", "151", "30", + "ETSI", "5G", "40M", "HT", "2T", "151", "63", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "IC", "5G", "40M", "HT", "2T", "151", "30", + "KCC", "5G", "40M", "HT", "2T", "151", "20", + "ACMA", "5G", "40M", "HT", "2T", "151", "30", + "CHILE", "5G", "40M", "HT", "2T", "151", "18", + "FCC", "5G", "40M", "HT", "2T", "159", "30", + "ETSI", "5G", "40M", "HT", "2T", "159", "63", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "IC", "5G", "40M", "HT", "2T", "159", "30", + "KCC", "5G", "40M", "HT", "2T", "159", "24", + "ACMA", "5G", "40M", "HT", "2T", "159", "30", + "CHILE", "5G", "40M", "HT", "2T", "159", "18", + "FCC", "5G", "80M", "VHT", "1T", "42", "20", + "ETSI", "5G", "80M", "VHT", "1T", "42", "30", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "IC", "5G", "80M", "VHT", "1T", "42", "20", + "KCC", "5G", "80M", "VHT", "1T", "42", "14", + "ACMA", "5G", "80M", "VHT", "1T", "42", "30", + "CHILE", "5G", "80M", "VHT", "1T", "42", "20", + "FCC", "5G", "80M", "VHT", "1T", "58", "20", + "ETSI", "5G", "80M", "VHT", "1T", "58", "30", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "IC", "5G", "80M", "VHT", "1T", "58", "20", + "KCC", "5G", "80M", "VHT", "1T", "58", "28", + "ACMA", "5G", "80M", "VHT", "1T", "58", "30", + "CHILE", "5G", "80M", "VHT", "1T", "58", "20", + "FCC", "5G", "80M", "VHT", "1T", "106", "20", + "ETSI", "5G", "80M", "VHT", "1T", "106", "30", + "MKK", "5G", "80M", "VHT", "1T", "106", "30", + "IC", "5G", "80M", "VHT", "1T", "106", "20", + "KCC", "5G", "80M", "VHT", "1T", "106", "28", + "ACMA", "5G", "80M", "VHT", "1T", "106", "30", + "CHILE", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "30", + "ETSI", "5G", "80M", "VHT", "1T", "122", "30", + "MKK", "5G", "80M", "VHT", "1T", "122", "30", + "IC", "5G", "80M", "VHT", "1T", "122", "-63", + "KCC", "5G", "80M", "VHT", "1T", "122", "28", + "ACMA", "5G", "80M", "VHT", "1T", "122", "-63", + "CHILE", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "30", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "IC", "5G", "80M", "VHT", "1T", "138", "30", + "KCC", "5G", "80M", "VHT", "1T", "138", "-63", + "ACMA", "5G", "80M", "VHT", "1T", "138", "-63", + "CHILE", "5G", "80M", "VHT", "1T", "138", "30", + "FCC", "5G", "80M", "VHT", "1T", "155", "30", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "IC", "5G", "80M", "VHT", "1T", "155", "30", + "KCC", "5G", "80M", "VHT", "1T", "155", "22", + "ACMA", "5G", "80M", "VHT", "1T", "155", "30", + "CHILE", "5G", "80M", "VHT", "1T", "155", "30", + "FCC", "5G", "80M", "VHT", "2T", "42", "18", + "ETSI", "5G", "80M", "VHT", "2T", "42", "20", + "MKK", "5G", "80M", "VHT", "2T", "42", "22", + "IC", "5G", "80M", "VHT", "2T", "42", "18", + "KCC", "5G", "80M", "VHT", "2T", "42", "14", + "ACMA", "5G", "80M", "VHT", "2T", "42", "20", + "CHILE", "5G", "80M", "VHT", "2T", "42", "18", + "FCC", "5G", "80M", "VHT", "2T", "58", "18", + "ETSI", "5G", "80M", "VHT", "2T", "58", "20", + "MKK", "5G", "80M", "VHT", "2T", "58", "22", + "IC", "5G", "80M", "VHT", "2T", "58", "18", + "KCC", "5G", "80M", "VHT", "2T", "58", "28", + "ACMA", "5G", "80M", "VHT", "2T", "58", "20", + "CHILE", "5G", "80M", "VHT", "2T", "58", "18", + "FCC", "5G", "80M", "VHT", "2T", "106", "20", + "ETSI", "5G", "80M", "VHT", "2T", "106", "20", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "IC", "5G", "80M", "VHT", "2T", "106", "20", + "KCC", "5G", "80M", "VHT", "2T", "106", "28", + "ACMA", "5G", "80M", "VHT", "2T", "106", "20", + "CHILE", "5G", "80M", "VHT", "2T", "106", "18", + "FCC", "5G", "80M", "VHT", "2T", "122", "30", + "ETSI", "5G", "80M", "VHT", "2T", "122", "20", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "IC", "5G", "80M", "VHT", "2T", "122", "-63", + "KCC", "5G", "80M", "VHT", "2T", "122", "28", + "ACMA", "5G", "80M", "VHT", "2T", "122", "-63", + "CHILE", "5G", "80M", "VHT", "2T", "122", "18", + "FCC", "5G", "80M", "VHT", "2T", "138", "30", + "ETSI", "5G", "80M", "VHT", "2T", "138", "63", + "MKK", "5G", "80M", "VHT", "2T", "138", "63", + "IC", "5G", "80M", "VHT", "2T", "138", "30", + "KCC", "5G", "80M", "VHT", "2T", "138", "-63", + "ACMA", "5G", "80M", "VHT", "2T", "138", "-63", + "CHILE", "5G", "80M", "VHT", "2T", "138", "18", + "FCC", "5G", "80M", "VHT", "2T", "155", "30", + "ETSI", "5G", "80M", "VHT", "2T", "155", "63", + "MKK", "5G", "80M", "VHT", "2T", "155", "63", + "IC", "5G", "80M", "VHT", "2T", "155", "30", + "KCC", "5G", "80M", "VHT", "2T", "155", "22", + "ACMA", "5G", "80M", "VHT", "2T", "155", "30", + "CHILE", "5G", "80M", "VHT", "2T", "155", "18" +}; + void odm_read_and_config_mp_8822b_txpwr_lmt_type5( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 i = 0; @@ -9775,14 +16278,14 @@ odm_read_and_config_mp_8822b_txpwr_lmt_type5( #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - PlatformZeroMemory(p_hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - p_hal_data->nLinesReadPwrLmt = array_len/7; + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len/7; #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8822b_txpwr_lmt_type5\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_txpwr_lmt_type5\n"); for (i = 0; i < array_len; i += 7) { #if (DM_ODM_SUPPORT_TYPE == ODM_IOT) @@ -9803,9 +16306,9 @@ odm_read_and_config_mp_8822b_txpwr_lmt_type5( u8 *val = array[i+6]; #endif - odm_config_bb_txpwr_lmt_8822b(p_dm_odm, regulation, band, bandwidth, rate, rf_path, chnl, val); + odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)p_hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", regulation, band, bandwidth, rate, rf_path, chnl, val); #endif } diff --git a/hal/phydm/rtl8822b/halhwimg8822b_rf.h b/hal/phydm/rtl8822b/halhwimg8822b_rf.h index 203aec1..332d723 100644 --- a/hal/phydm/rtl8822b/halhwimg8822b_rf.h +++ b/hal/phydm/rtl8822b/halhwimg8822b_rf.h @@ -1,19 +1,29 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2017 Realtek Corporation. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -******************************************************************************/ - -/*Image2HeaderVersion: R2 1.2.1*/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*Image2HeaderVersion: R3 1.0*/ #if (RTL8822B_SUPPORT == 1) #ifndef __INC_MP_RF_HW_IMG_8822B_H #define __INC_MP_RF_HW_IMG_8822B_H @@ -25,7 +35,7 @@ void odm_read_and_config_mp_8822b_radioa(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_radioa(void); @@ -35,7 +45,7 @@ u32 odm_get_version_mp_8822b_radioa(void); void odm_read_and_config_mp_8822b_radiob(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_radiob(void); @@ -45,7 +55,7 @@ u32 odm_get_version_mp_8822b_radiob(void); void odm_read_and_config_mp_8822b_txpowertrack(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack(void); @@ -55,7 +65,7 @@ u32 odm_get_version_mp_8822b_txpowertrack(void); void odm_read_and_config_mp_8822b_txpowertrack_type0(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type0(void); @@ -65,7 +75,7 @@ u32 odm_get_version_mp_8822b_txpowertrack_type0(void); void odm_read_and_config_mp_8822b_txpowertrack_type1(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type1(void); @@ -75,7 +85,7 @@ u32 odm_get_version_mp_8822b_txpowertrack_type1(void); void odm_read_and_config_mp_8822b_txpowertrack_type10(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type10(void); @@ -85,7 +95,7 @@ u32 odm_get_version_mp_8822b_txpowertrack_type10(void); void odm_read_and_config_mp_8822b_txpowertrack_type11(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type11(void); @@ -95,7 +105,7 @@ u32 odm_get_version_mp_8822b_txpowertrack_type11(void); void odm_read_and_config_mp_8822b_txpowertrack_type12(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type12(void); @@ -105,7 +115,7 @@ u32 odm_get_version_mp_8822b_txpowertrack_type12(void); void odm_read_and_config_mp_8822b_txpowertrack_type13(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type13(void); @@ -115,17 +125,47 @@ u32 odm_get_version_mp_8822b_txpowertrack_type13(void); void odm_read_and_config_mp_8822b_txpowertrack_type14(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type14(void); +/****************************************************************************** +* txpowertrack_type15.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpowertrack_type15(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_txpowertrack_type15(void); + +/****************************************************************************** +* txpowertrack_type16.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpowertrack_type16(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_txpowertrack_type16(void); + +/****************************************************************************** +* txpowertrack_type17.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpowertrack_type17(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_txpowertrack_type17(void); + /****************************************************************************** * txpowertrack_type2.TXT ******************************************************************************/ void odm_read_and_config_mp_8822b_txpowertrack_type2(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type2(void); @@ -135,7 +175,7 @@ u32 odm_get_version_mp_8822b_txpowertrack_type2(void); void odm_read_and_config_mp_8822b_txpowertrack_type3_type5(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type3_type5(void); @@ -145,7 +185,7 @@ u32 odm_get_version_mp_8822b_txpowertrack_type3_type5(void); void odm_read_and_config_mp_8822b_txpowertrack_type4(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type4(void); @@ -155,7 +195,7 @@ u32 odm_get_version_mp_8822b_txpowertrack_type4(void); void odm_read_and_config_mp_8822b_txpowertrack_type6(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type6(void); @@ -165,7 +205,7 @@ u32 odm_get_version_mp_8822b_txpowertrack_type6(void); void odm_read_and_config_mp_8822b_txpowertrack_type7(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type7(void); @@ -175,7 +215,7 @@ u32 odm_get_version_mp_8822b_txpowertrack_type7(void); void odm_read_and_config_mp_8822b_txpowertrack_type8(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type8(void); @@ -185,7 +225,7 @@ u32 odm_get_version_mp_8822b_txpowertrack_type8(void); void odm_read_and_config_mp_8822b_txpowertrack_type9(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpowertrack_type9(void); @@ -195,17 +235,87 @@ u32 odm_get_version_mp_8822b_txpowertrack_type9(void); void odm_read_and_config_mp_8822b_txpwr_lmt(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpwr_lmt(void); +/****************************************************************************** +* txpwr_lmt_type12.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type12(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_txpwr_lmt_type12(void); + +/****************************************************************************** +* txpwr_lmt_type15.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type15(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_txpwr_lmt_type15(void); + +/****************************************************************************** +* txpwr_lmt_type16.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type16(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_txpwr_lmt_type16(void); + +/****************************************************************************** +* txpwr_lmt_type17.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type17(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_txpwr_lmt_type17(void); + +/****************************************************************************** +* txpwr_lmt_type2.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type2(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_txpwr_lmt_type2(void); + +/****************************************************************************** +* txpwr_lmt_type3.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type3(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_txpwr_lmt_type3(void); + +/****************************************************************************** +* txpwr_lmt_type4.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8822b_txpwr_lmt_type4(/* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm +); +u32 odm_get_version_mp_8822b_txpwr_lmt_type4(void); + /****************************************************************************** * txpwr_lmt_type5.TXT ******************************************************************************/ void odm_read_and_config_mp_8822b_txpwr_lmt_type5(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); u32 odm_get_version_mp_8822b_txpwr_lmt_type5(void); diff --git a/hal/phydm/rtl8822b/halphyrf_8822b.c b/hal/phydm/rtl8822b/halphyrf_8822b.c deleted file mode 100644 index 16cf374..0000000 --- a/hal/phydm/rtl8822b/halphyrf_8822b.c +++ /dev/null @@ -1,481 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8822B_SUPPORT == 1) - -BOOLEAN -GetMixModeTXAGCBBSWingOffset_8822b( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte TxPowerIndexOffest - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - - u1Byte BBSwingUpperBound = pRFCalibrateInfo->DefaultOfdmIndex + 10; - u1Byte BBSwingLowerBound = 0; - - s1Byte TX_AGC_Index = 0; - u1Byte TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, TxPowerIndexOffest=%d\n", - RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], TxPowerIndexOffest)); - - if (TxPowerIndexOffest > 0XF) - TxPowerIndexOffest = 0XF; - - if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0 && pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] <= TxPowerIndexOffest) { - TX_AGC_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex; - } else if (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] > TxPowerIndexOffest) { - TX_AGC_Index = TxPowerIndexOffest; - pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - TxPowerIndexOffest; - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]; - - if (TX_BBSwing_Index > BBSwingUpperBound) - TX_BBSwing_Index = BBSwingUpperBound; - } else { - TX_AGC_Index = 0; - - if (pRFCalibrateInfo->DefaultOfdmIndex > (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] * (-1))) - TX_BBSwing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - else - TX_BBSwing_Index = BBSwingLowerBound; - - if (TX_BBSwing_Index < BBSwingLowerBound) - TX_BBSwing_Index = BBSwingLowerBound; - } - - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] = TX_AGC_Index; - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] = TX_BBSwing_Index; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("MixMode Offset Path_%d pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]=%d TxPowerIndexOffest=%d\n", - RFPath, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] , TxPowerIndexOffest)); - - return TRUE; -} - - -VOID -ODM_TxPwrTrackSetPwr8822B( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u1Byte Channel = pHalData->CurrentChannel; - u1Byte BandWidth = pHalData->CurrentChannelBW; - u1Byte TxPowerIndex = 0; - u1Byte TxRate = 0xFF; - RT_STATUS status = RT_STATUS_SUCCESS; - - PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt = &(pRFCalibrateInfo->HALMAC_PWR_TRACKING_INFO); - - if (pDM_Odm->mp_mode == TRUE) { - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #if (MP_DRIVER == 1) - PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); - - TxRate = MptToMgntRate(pMptCtx->MptRateIndex); - #endif - #endif - } else { - u2Byte rate = *(pDM_Odm->pForcedDataRate); - - if (!rate) { /*auto rate*/ - #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (pDM_Odm->number_linked_client != 0) - TxRate = HwRateToMRate(pDM_Odm->TxRate); - #endif - } else { /*force rate*/ - TxRate = (u1Byte) rate; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s TxRate=0x%X\n", __func__, TxRate)); - - TxPowerIndex = PHY_GetTxPowerIndex(Adapter, (ODM_RF_RADIO_PATH_E) RFPath, TxRate, BandWidth, Channel); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("type=%d TxPowerIndex=%d pRFCalibrateInfo->Absolute_OFDMSwingIdx=%d pRFCalibrateInfo->DefaultOfdmIndex=%d RFPath=%d\n", Method, TxPowerIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->DefaultOfdmIndex, RFPath)); - - pPwr_tracking_opt->type = Method; - pPwr_tracking_opt->bbswing_index = pRFCalibrateInfo->DefaultOfdmIndex; - pPwr_tracking_opt->pwr_tracking_para[RFPath].enable = 1; - pPwr_tracking_opt->pwr_tracking_para[RFPath].tx_pwr_index = TxPowerIndex; - pPwr_tracking_opt->pwr_tracking_para[RFPath].pwr_tracking_offset_value = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; - pPwr_tracking_opt->pwr_tracking_para[RFPath].tssi_value = 0; - - - if (RFPath == (MAX_PATH_NUM_8822B - 1)) { - status = HAL_MAC_Send_PowerTracking_Info(&GET_HAL_MAC_INFO(Adapter), pPwr_tracking_opt); - - if (status == RT_STATUS_SUCCESS) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Path A 0xC94=0x%X 0xC1C=0x%X\n", - ODM_GetBBReg(pDM_Odm, 0xC94, BIT29 | BIT28 | BIT27 | BIT26 | BIT25), - ODM_GetBBReg(pDM_Odm, 0xC1C, 0xFFE00000) - )); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Path B 0xE94=0x%X 0xE1C=0x%X\n", - ODM_GetBBReg(pDM_Odm, 0xE94, BIT29 | BIT28 | BIT27 | BIT26 | BIT25), - ODM_GetBBReg(pDM_Odm, 0xE1C, 0xFFE00000) - )); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("Power Tracking to FW Fail ret code = %d\n", status)); - } - } - -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - u1Byte TxPowerIndexOffest = 0; - u1Byte TxPowerIndex = 0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRF->DefaultOfdmIndex=%d pRF->DefaultCckIndex=%d\n", pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("pRF->Absolute_OFDMSwingIdx=%d pRF->Remnant_OFDMSwingIdx=%d pRF->Absolute_CCKSwingIdx=%d pRF->Remnant_CCKSwingIdx=%d RFPath=%d\n", - pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath], pRFCalibrateInfo->Absolute_CCKSwingIdx[RFPath], pRFCalibrateInfo->Remnant_CCKSwingIdx, RFPath)); - - TxPowerIndex = config_phydm_read_txagc_8822b(pDM_Odm, RFPath, 0x04); /*0x04(TX_AGC_OFDM_6M)*/ - - if (TxPowerIndex >= 63) - TxPowerIndex = 63; - - TxPowerIndexOffest = 63 - TxPowerIndex; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TxPowerIndex=%d TxPowerIndexOffest=%d RFPath=%d\n", TxPowerIndex, TxPowerIndexOffest, RFPath)); - - - if (Method == MIX_MODE) { - switch (RFPath) { - case ODM_RF_PATH_A: - GetMixModeTXAGCBBSWingOffset_8822b(pDM_Odm, Method, RFPath, TxPowerIndexOffest); - ODM_SetBBReg(pDM_Odm, 0xC94, (BIT29 | BIT28 | BIT27 | BIT26 | BIT25), pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d RFPath=%d\n", - ODM_GetBBReg(pDM_Odm, 0xC94, (BIT29 | BIT28 | BIT27 | BIT26 | BIT25)), - ODM_GetBBReg(pDM_Odm, 0xc1c, 0xFFE00000), - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], RFPath)); - break; - - case ODM_RF_PATH_B: - GetMixModeTXAGCBBSWingOffset_8822b(pDM_Odm, Method, RFPath, TxPowerIndexOffest); - ODM_SetBBReg(pDM_Odm, 0xE94, (BIT29 | BIT28 | BIT27 | BIT26 | BIT25), pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]); - ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[pRFCalibrateInfo->BbSwingIdxOfdm[RFPath]]); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, - ("TXAGC(0xE94)=0x%x BBSwing(0xe1c)=0x%x BBSwingIndex=%d RFPath=%d\n", - ODM_GetBBReg(pDM_Odm, 0xE94, (BIT29 | BIT28 | BIT27 | BIT26 | BIT25)), - ODM_GetBBReg(pDM_Odm, 0xe1c, 0xFFE00000), - pRFCalibrateInfo->BbSwingIdxOfdm[RFPath], RFPath)); - break; - - default: - break; - } - } - -#endif - -} - - -VOID -GetDeltaSwingTable_8822B( - PVOID pDM_VOID, -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B, - pu1Byte *TemperatureUP_CCK_A, - pu1Byte *TemperatureDOWN_CCK_A, - pu1Byte *TemperatureUP_CCK_B, - pu1Byte *TemperatureDOWN_CCK_B -#else - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B -#endif - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - u1Byte channel = *(pDM_Odm->pChannel); -#else - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u1Byte channel = pHalData->CurrentChannel; -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - *TemperatureUP_CCK_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; - *TemperatureDOWN_CCK_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; - *TemperatureUP_CCK_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; - *TemperatureDOWN_CCK_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; -#endif - - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; - - if (36 <= channel && channel <= 64) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; - } else if (100 <= channel && channel <= 144) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; - } else if (149 <= channel && channel <= 177) { - *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; - *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; - *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; - *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; - } -} - - -VOID -phy_LCCalibrate_8822B( - PDM_ODM_T pDM_Odm - ) -{ - u4Byte LC_Cal = 0, cnt = 0; - - /*backup RF0x18*/ - LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); - - /*Start LCK*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal | 0x08000); - - ODM_delay_ms(100); - - for (cnt = 0; cnt < 100; cnt++) { - if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) - break; - ODM_delay_ms(10); - } - - /*Recover channel number*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); -} - - - -VOID -PHY_LCCalibrate_8822B( - PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; - u8Byte StartTime; - u8Byte ProgressingTime; - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - -#if (MP_DRIVER == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); -#else - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); -#endif - bStartContTx = pMptCtx->bStartContTx; - bSingleTone = pMptCtx->bSingleTone; - bCarrierSuppression = pMptCtx->bCarrierSuppression; -#endif -#endif - - if (bStartContTx || bSingleTone || bCarrierSuppression) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]continues TX ing !!! LCK return\n")); - return; - } - - StartTime = ODM_GetCurrentTime(pDM_Odm); - phy_LCCalibrate_8822B(pDM_Odm); - ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK ProgressingTime = %lld\n", ProgressingTime)); -} - - - -void ConfigureTxpowerTrack_8822B( - PTXPWRTRACK_CFG pConfig - ) -{ - pConfig->SwingTableSize_CCK = TXSCALE_TABLE_SIZE; - pConfig->SwingTableSize_OFDM = TXSCALE_TABLE_SIZE; - pConfig->Threshold_IQK = IQK_THRESHOLD; - pConfig->Threshold_DPK = DPK_THRESHOLD; - pConfig->AverageThermalNum = AVG_THERMAL_NUM_8822B; - pConfig->RfPathCount = MAX_PATH_NUM_8822B; - pConfig->ThermalRegAddr = RF_T_METER_8822B; - - pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8822B; - pConfig->DoIQK = DoIQK_8822B; - pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8822B; - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - pConfig->GetDeltaAllSwingTable = GetDeltaSwingTable_8822B; -#else - pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8822B; -#endif -} - - -VOID PHY_SetRFPathSwitch_8822B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - -#if 0 - ODM_SetBBReg(pDM_Odm, 0xCB4, bMaskDWord, 0x00004577); - ODM_SetBBReg(pDM_Odm, 0x1900, bMaskDWord, 0x00001000); - ODM_SetBBReg(pDM_Odm, 0x4C, bMaskDWord, 0x01628202); - - if (bMain) - ODM_SetBBReg(pDM_Odm, 0xCBC, bMaskDWord, 0x00000200); /*WiFi */ - else - ODM_SetBBReg(pDM_Odm, 0xCBC, bMaskDWord, 0x00000100); /* BT*/ -#else - /*BY SY Request */ - ODM_SetBBReg(pDM_Odm, 0x4C, (BIT24 | BIT23), 0x2); - ODM_SetBBReg(pDM_Odm, 0x974, 0xff, 0xff); - - /*ODM_SetBBReg(pDM_Odm, 0x1991, 0x3, 0x0);*/ - ODM_SetBBReg(pDM_Odm, 0x1990, (BIT9 | BIT8), 0x0); - - /*ODM_SetBBReg(pDM_Odm, 0xCBE, 0x8, 0x0);*/ - ODM_SetBBReg(pDM_Odm, 0xCBC, BIT19, 0x0); - - ODM_SetBBReg(pDM_Odm, 0xCB4, 0xff, 0x77); - - if (bMain) { - /*ODM_SetBBReg(pDM_Odm, 0xCBD, 0x3, 0x2); WiFi */ - ODM_SetBBReg(pDM_Odm, 0xCBC, (BIT9 | BIT8), 0x2); /*WiFi */ - } else { - /*ODM_SetBBReg(pDM_Odm, 0xCBD, 0x3, 0x1); BT*/ - ODM_SetBBReg(pDM_Odm, 0xCBC, (BIT9 | BIT8), 0x1); /*BT*/ - } - -#endif -} - -BOOLEAN -phy_QueryRFPathSwitch_8822B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PDM_ODM_T pDM_Odm -#else - PADAPTER pAdapter -#endif - ) -{ -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; - #endif -#endif - - if (ODM_GetBBReg(pDM_Odm, 0xCBC, (BIT9 | BIT8)) == 0x2) /*WiFi */ - return TRUE; - else - return FALSE; -} - - -BOOLEAN PHY_QueryRFPathSwitch_8822B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - PDM_ODM_T pDM_Odm -#else - PADAPTER pAdapter -#endif - ) -{ - -#if DISABLE_BB_RF - return TRUE; -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - return phy_QueryRFPathSwitch_8822B(pDM_Odm); -#else - return phy_QueryRFPathSwitch_8822B(pAdapter); -#endif -} - - -#endif /* (RTL8822B_SUPPORT == 0)*/ diff --git a/hal/phydm/rtl8822b/halphyrf_8822b.h b/hal/phydm/rtl8822b/halphyrf_8822b.h deleted file mode 100644 index 97162dd..0000000 --- a/hal/phydm/rtl8822b/halphyrf_8822b.h +++ /dev/null @@ -1,76 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL_PHY_RF_8822B_H__ -#define __HAL_PHY_RF_8822B_H__ - -#define AVG_THERMAL_NUM_8822B 4 -#define RF_T_METER_8822B 0x42 - -void ConfigureTxpowerTrack_8822B( - PTXPWRTRACK_CFG pConfig - ); - -VOID -ODM_TxPwrTrackSetPwr8822B( - PVOID pDM_VOID, - PWRTRACK_METHOD Method, - u1Byte RFPath, - u1Byte ChannelMappedIndex - ); - -VOID -GetDeltaSwingTable_8822B( - PVOID pDM_VOID, -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B, - pu1Byte *TemperatureUP_CCK_A, - pu1Byte *TemperatureDOWN_CCK_A, - pu1Byte *TemperatureUP_CCK_B, - pu1Byte *TemperatureDOWN_CCK_B -#else - pu1Byte *TemperatureUP_A, - pu1Byte *TemperatureDOWN_A, - pu1Byte *TemperatureUP_B, - pu1Byte *TemperatureDOWN_B -#endif - ); - -VOID -PHY_LCCalibrate_8822B( - PVOID pDM_VOID - ); - - - -VOID PHY_SetRFPathSwitch_8822B( -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - IN PDM_ODM_T pDM_Odm, -#else - IN PADAPTER pAdapter, -#endif - IN BOOLEAN bMain - ); - -#endif /* #ifndef __HAL_PHY_RF_8822B_H__ */ - diff --git a/hal/phydm/rtl8822b/mp_precomp.h b/hal/phydm/rtl8822b/mp_precomp.h index fa483c6..9c7ab63 100644 --- a/hal/phydm/rtl8822b/mp_precomp.h +++ b/hal/phydm/rtl8822b/mp_precomp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,9 +11,4 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ diff --git a/hal/phydm/rtl8822b/phydm_hal_api8822b.c b/hal/phydm/rtl8822b/phydm_hal_api8822b.c index c0f33ad..148fd53 100644 --- a/hal/phydm/rtl8822b/phydm_hal_api8822b.c +++ b/hal/phydm/rtl8822b/phydm_hal_api8822b.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #include "mp_precomp.h" #include "../phydm_precomp.h" @@ -26,8 +31,9 @@ /* ======================================================================== */ /* These following functions can be used for PHY DM only*/ -enum odm_bw_e bw_8822b; +enum channel_width bw_8822b; u8 central_ch_8822b; +u8 central_ch_8822b_drp; #if !(DM_ODM_SUPPORT_TYPE == ODM_CE) u32 cca_ifem_bcut[3][4] = { @@ -44,33 +50,147 @@ u8 central_ch_8822b; u32 cca_ifem_ccut[3][4] = { {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ - {0x79a0ea2a, 0x79A0EA2C, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ + {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ {0x87765541, 0x87746341, 0x87765541, 0x87746341} /*Reg838*/ }; u32 cca_efem_ccut[3][4] = { {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/ - {0x79A0EA28, 0x79A0EA2C, 0x79A0EA28, 0x79a0ea2a}, /*Reg830*/ + {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/ {0x87766451, 0x87766431, 0x87766451, 0x87766431} /*Reg838*/ }; u32 cca_ifem_ccut_rfetype[3][4] = { {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/ - {0x79a0ea2a, 0x97A0EA2C, 0x79a0ea2a, 0x79a0ea2a}, /*Reg830*/ + {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ {0x87765541, 0x86666341, 0x87765561, 0x86666361} /*Reg838*/ }; +__iram_odm_func__ +void +phydm_rxagc_switch_8822b( + struct dm_struct *dm, + boolean enable_rxagc_switch +) +{ + if ((dm->rfe_type == 15) || (dm->rfe_type == 16)) { + PHYDM_DBG(dm, ODM_COMP_API, "Microsoft case!\n"); + + } else { + PHYDM_DBG(dm, ODM_COMP_API, "Not Microsoft case\n"); + return; + } + + if (enable_rxagc_switch == true) { + if ((*dm->channel >= 36) && (*dm->channel <= 64)) { + odm_set_bb_reg(dm, 0x958, BIT(4), 0x1); + odm_set_bb_reg(dm, 0xc1c, (BIT(11)|BIT(10)|BIT(9)|BIT(8)), 0x1); + odm_set_bb_reg(dm, 0xe1c, (BIT(11)|BIT(10)|BIT(9)|BIT(8)), 0x5); + } else if ((*dm->channel >= 100) && (*dm->channel <= 144)) { + odm_set_bb_reg(dm, 0x958, BIT(4), 0x1); + odm_set_bb_reg(dm, 0xc1c, (BIT(11)|BIT(10)|BIT(9)|BIT(8)), 0x2); + odm_set_bb_reg(dm, 0xe1c, (BIT(11)|BIT(10)|BIT(9)|BIT(8)), 0x6); + } else if (*dm->channel >= 149) { + odm_set_bb_reg(dm, 0x958, BIT(4), 0x1); + odm_set_bb_reg(dm, 0xc1c, (BIT(11)|BIT(10)|BIT(9)|BIT(8)), 0x3); + odm_set_bb_reg(dm, 0xe1c, (BIT(11)|BIT(10)|BIT(9)|BIT(8)), 0x7); + } + dm->brxagcswitch = true; + PHYDM_DBG(dm, ODM_COMP_API, "Microsoft case! AGC table (path-b) is switched!\n"); + + } else { + if ((*dm->channel >= 36) && (*dm->channel <= 64)) { + odm_set_bb_reg(dm, 0x958, BIT(4), 0x1); + odm_set_bb_reg(dm, 0xc1c, (BIT(11)|BIT(10)|BIT(9)|BIT(8)), 0x1); + odm_set_bb_reg(dm, 0xe1c, (BIT(11)|BIT(10)|BIT(9)|BIT(8)), 0x1); + } else if ((*dm->channel >= 100) && (*dm->channel <= 144)) { + odm_set_bb_reg(dm, 0x958, BIT(4), 0x1); + odm_set_bb_reg(dm, 0xc1c, (BIT(11)|BIT(10)|BIT(9)|BIT(8)), 0x2); + odm_set_bb_reg(dm, 0xe1c, (BIT(11)|BIT(10)|BIT(9)|BIT(8)), 0x2); + } else if (*dm->channel >= 149) { + odm_set_bb_reg(dm, 0x958, BIT(4), 0x1); + odm_set_bb_reg(dm, 0xc1c, (BIT(11)|BIT(10)|BIT(9)|BIT(8)), 0x3); + odm_set_bb_reg(dm, 0xe1c, (BIT(11)|BIT(10)|BIT(9)|BIT(8)), 0x3); + } + dm->brxagcswitch = false; + PHYDM_DBG(dm, ODM_COMP_API, "AGC table are the same on path-a and b\n"); + + } + +} + __iram_odm_func__ void phydm_igi_toggle_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 igi = 0x20; - igi = odm_get_bb_reg(p_dm_odm, 0xc50, 0x7f); - odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, (igi - 2)); - odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, igi); - odm_set_bb_reg(p_dm_odm, 0xe50, 0x7f, (igi - 2)); - odm_set_bb_reg(p_dm_odm, 0xe50, 0x7f, igi); + igi = odm_get_bb_reg(dm, 0xc50, 0x7f); + odm_set_bb_reg(dm, 0xc50, 0x7f, (igi - 2)); + odm_set_bb_reg(dm, 0xc50, 0x7f, igi); + odm_set_bb_reg(dm, 0xe50, 0x7f, (igi - 2)); + odm_set_bb_reg(dm, 0xe50, 0x7f, igi); +} + + +__iram_odm_func__ +void +phydm_8822b_type15_rfe( + struct dm_struct *dm, + u8 channel +) +{ + if (channel <= 14) { + /* signal source */ + odm_set_bb_reg(dm, 0xcb0, 0xffffff, 0x777777); + odm_set_bb_reg(dm, 0xeb0, 0xffffff, 0x777777); + odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x77); + odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x77); + + } else if ((channel > 35) && (channel <= 64)) { + /* signal source */ + odm_set_bb_reg(dm, 0xcb0, 0xffffff, 0x777747); + odm_set_bb_reg(dm, 0xeb0, 0xffffff, 0x777747); + odm_set_bb_reg(dm, 0xcb4, MASKBYTE0, 0x57); + odm_set_bb_reg(dm, 0xeb4, MASKBYTE0, 0x57); + + } else if (channel > 64) { + /* signal source */ + odm_set_bb_reg(dm, 0xcb0, 0xffffff, 0x777747); + odm_set_bb_reg(dm, 0xeb0, 0xffffff, 0x777747); + odm_set_bb_reg(dm, 0xcb4, MASKBYTE0, 0x75); + odm_set_bb_reg(dm, 0xeb4, MASKBYTE0, 0x75); + + } else + return; + + /* inverse or not */ + odm_set_bb_reg(dm, 0xcbc, 0x3f, 0x0); + odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10) | BIT(9) | BIT(8)), 0x0); + odm_set_bb_reg(dm, 0xebc, 0x3f, 0x0); + odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10) | BIT(9) | BIT(8)), 0x0); + + + /* antenna switch table */ + if (channel <= 14) { + if ((dm->rx_ant_status == BB_PATH_AB) || (dm->tx_ant_status == BB_PATH_AB)) { + /* 2TX or 2RX */ + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501); + } else if (dm->rx_ant_status == dm->tx_ant_status) { + /* TXA+RXA or TXB+RXB */ + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500); + } else { + /* TXB+RXA or TXA+RXB */ + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005); + } + } else if (channel > 35) { + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa5a5); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa5a5); + } + } __iram_odm_func__ @@ -89,223 +209,342 @@ phydm_check_bit_mask(u32 bit_mask, u32 data_original, u32 data) return data; } +__iram_odm_func__ +void +phydm_rfe_8822b_setting( + void *dm_void, + u8 rfe_num, + u8 path_mux_sel, + u8 inv_en, + u8 source_sel +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 debug_level = dm->debug_level;/*no use, just prevent FW 3081 compile warning*/ + + debug_level = 5; /*no use, just prevent FW 3081 compile warning*/ + + PHYDM_DBG(dm, ODM_PHY_CONFIG, "8822B RFE[%d]:{Path=0x%x}{inv_en=%d}{source=0x%x}\n", + rfe_num, path_mux_sel, inv_en, source_sel); + + if(rfe_num > 11) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[Warning] Wrong RFE num=%d}\n", rfe_num); + return; + } + + /*[Path_mux_sel]*/ + odm_set_bb_reg(dm, 0x1990, BIT(rfe_num), ((path_mux_sel == BB_PATH_A) ? 0 : 1)); + + /*[Inv_en]*/ + odm_set_bb_reg(dm, 0xcbc, BIT(rfe_num), (u32)inv_en); + odm_set_bb_reg(dm, 0xebc, BIT(rfe_num), (u32)inv_en); + + /*[Output Source Signal Selection]*/ + if (rfe_num <= 7) { + odm_set_bb_reg(dm, 0xcb0, ((0xf)<<(rfe_num * 4)), (u32)source_sel); + odm_set_bb_reg(dm, 0xeb0, ((0xf)<<(rfe_num * 4)), (u32)source_sel); + } else { + odm_set_bb_reg(dm, 0xcb4, ((0xf)<<((rfe_num - 8) * 4)), (u32)source_sel); + odm_set_bb_reg(dm, 0xeb4, ((0xf)<<((rfe_num - 8) * 4)), (u32)source_sel); + } +} + +__iram_odm_func__ +void +phydm_rfe_8822b_init( + struct dm_struct *dm +) +{ + PHYDM_DBG(dm, ODM_PHY_CONFIG, "8822B RFE_Init, RFE_type=((%d))\n", dm->rfe_type); + + /* chip top mux */ + odm_set_bb_reg(dm, 0x64, BIT(29) | BIT(28), 0x3); + odm_set_bb_reg(dm, 0x4c, BIT(26) | BIT(25), 0x0); + odm_set_bb_reg(dm, 0x40, BIT(2), 0x1); + + /* from s0 or s1 */ + odm_set_bb_reg(dm, 0x1990, 0x3f, 0x30); + odm_set_bb_reg(dm, 0x1990, (BIT(11) | BIT(10)), 0x3); + + /* input or output */ + odm_set_bb_reg(dm, 0x974, 0x3f, 0x3f); + odm_set_bb_reg(dm, 0x974, (BIT(11) | BIT(10)), 0x3); +} + __iram_odm_func__ boolean phydm_rfe_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - u8 channel + struct dm_struct *dm, + u8 channel ) { + boolean is_channel_2g = (channel <= 14) ? true : false; + u8 rfe_type = dm->rfe_type; + + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[8822B] Update RFE PINs: CH:%d, T/RX_path:{ 0x%x, 0x%x}, cut_ver:%d, rfe_type:%d\n", + channel, dm->tx_ant_status, dm->rx_ant_status, dm->cut_version, rfe_type); + + if (((channel > 14) && (channel < 36)) || ((channel == 0))) + return false; /* Distinguish the setting band */ - if (channel <= 14) - p_dm_odm->rfe_hwsetting_band = 1; - else - p_dm_odm->rfe_hwsetting_band = 2; + dm->rfe_hwsetting_band = (is_channel_2g) ? 1 : 2; /* HW Setting for each RFE type */ - if ((p_dm_odm->rfe_type == 4) || (p_dm_odm->rfe_type == 11)) { - + if ((rfe_type == 4) || (rfe_type == 11)) { /*TRSW = trsw_forced_BT ? 0x804[0] : (0xCB8[2] ? 0xCB8[0] : trsw_lut); trsw_lut = TXON*/ /*TRSWB = trsw_forced_BT ? (~0x804[0]) : (0xCB8[2] ? 0xCB8[1] : trswb_lut); trswb_lut = TXON*/ /*trsw_forced_BT = 0x804[1] ? 0 : (~GNT_WL); */ - /*odm_set_bb_reg(p_dm_odm, 0x804, (BIT1|BIT0), 0x0);*/ + /*odm_set_bb_reg(dm, 0x804, (BIT(1)|BIT(0)), 0x0);*/ /* Default setting is in PHY parameters */ - if (channel <= 14) { + if (is_channel_2g) { /* signal source */ - odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x745774); - odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x745774); - odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x57); - odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x57); + odm_set_bb_reg(dm, 0xcb0, 0xffffff, 0x745774); + odm_set_bb_reg(dm, 0xeb0, 0xffffff, 0x745774); + odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57); + odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57); /* inverse or not */ - odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x8); - odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(11) | BIT(10)), 0x2); - odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x8); - odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(11) | BIT(10)), 0x2); + odm_set_bb_reg(dm, 0xcbc, 0x3f, 0x8); + odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x2); + odm_set_bb_reg(dm, 0xebc, 0x3f, 0x8); + odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x2); /* antenna switch table */ - if ((p_dm_odm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) || (p_dm_odm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) { + if ((dm->rx_ant_status == BB_PATH_AB) || (dm->tx_ant_status == BB_PATH_AB)) { /* 2TX or 2RX */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xf050); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xf050); - } else if (p_dm_odm->rx_ant_status == p_dm_odm->tx_ant_status) { + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf050); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf050); + } else if (dm->rx_ant_status == dm->tx_ant_status) { /* TXA+RXA or TXB+RXB */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xf055); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xf055); + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf055); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf055); } else { /* TXB+RXA or TXA+RXB */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xf550); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xf550); + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf550); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf550); } - } else if (channel > 35) { + } else { /* signal source */ - odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x477547); - odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x477547); - odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x75); - odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x75); + odm_set_bb_reg(dm, 0xcb0, 0xffffff, 0x477547); + odm_set_bb_reg(dm, 0xeb0, 0xffffff, 0x477547); + odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75); + odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75); /* inverse or not */ - odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(11) | BIT(10)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(dm, 0xcbc, 0x3f, 0x0); + odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(dm, 0xebc, 0x3f, 0x0); + odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0); /* antenna switch table */ - if ((p_dm_odm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) || (p_dm_odm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) { + if ((dm->rx_ant_status == BB_PATH_AB) || (dm->tx_ant_status == BB_PATH_AB)) { /* 2TX or 2RX */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa501); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa501); - } else if (p_dm_odm->rx_ant_status == p_dm_odm->tx_ant_status) { + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501); + } else if (dm->rx_ant_status == dm->tx_ant_status) { /* TXA+RXA or TXB+RXB */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa500); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa500); + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500); } else { /* TXB+RXA or TXA+RXB */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa005); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa005); + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005); } - } else - return false; - - - } else if ((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 2) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7) || (p_dm_odm->rfe_type == 9)) { + } + } else if ((rfe_type == 1) || (rfe_type == 2) || (rfe_type == 6) || (rfe_type == 7) || (rfe_type == 9)) { /* eFem */ - if ((p_dm_odm->cut_version == ODM_CUT_B) && (p_dm_odm->rfe_type < 2)) { - if (channel <= 14) { + if ((dm->cut_version == ODM_CUT_B) && (rfe_type < 2)) { + if (is_channel_2g) { /* signal source */ - odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x704570); - odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x704570); - odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x45); - odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x45); - } else if (channel > 35) { - odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x174517); - odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x174517); - odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x45); - odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x45); - } else - return false; + odm_set_bb_reg(dm, 0xcb0, 0xffffff, 0x704570); + odm_set_bb_reg(dm, 0xeb0, 0xffffff, 0x704570); + odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x45); + odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x45); + } else { + odm_set_bb_reg(dm, 0xcb0, 0xffffff, 0x174517); + odm_set_bb_reg(dm, 0xeb0, 0xffffff, 0x174517); + odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x45); + odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x45); + } /* delay 400ns for PAPE */ - odm_set_bb_reg(p_dm_odm, 0x810, MASKBYTE3 | BIT(20) | BIT(21) | BIT(22) | BIT(23), 0x211); + odm_set_bb_reg(dm, 0x810, 0xfff00000, 0x211); /* antenna switch table */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa555); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa555); + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa555); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa555); /* inverse or not */ - odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(11) | BIT(10)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(11) | BIT(10)), 0x0); - - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Using old RFE control pin setting for A-cut and B-cut\n", __func__)); + odm_set_bb_reg(dm, 0xcbc, 0x3f, 0x0); + odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(dm, 0xebc, 0x3f, 0x0); + odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0); } else { - if (channel <= 14) { + if (is_channel_2g) { /* signal source */ - odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x705770); - odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x705770); - odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x57); - odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x57); - odm_set_bb_reg(p_dm_odm, 0xcb8, BIT(4), 0); - odm_set_bb_reg(p_dm_odm, 0xeb8, BIT(4), 0); - } else if (channel > 35) { + odm_set_bb_reg(dm, 0xcb0, 0xffffff, 0x705770); + odm_set_bb_reg(dm, 0xeb0, 0xffffff, 0x705770); + odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57); + odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57); + odm_set_bb_reg(dm, 0xcb8, BIT(4), 0); + odm_set_bb_reg(dm, 0xeb8, BIT(4), 0); + } else { /* signal source */ - odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x177517); - odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x177517); - odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x75); - odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x75); - odm_set_bb_reg(p_dm_odm, 0xcb8, BIT(5), 0); - odm_set_bb_reg(p_dm_odm, 0xeb8, BIT(5), 0); - } else - return false; - + odm_set_bb_reg(dm, 0xcb0, 0xffffff, 0x177517); + odm_set_bb_reg(dm, 0xeb0, 0xffffff, 0x177517); + odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75); + odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75); + odm_set_bb_reg(dm, 0xcb8, BIT(5), 0); + odm_set_bb_reg(dm, 0xeb8, BIT(5), 0); + } + /* inverse or not */ - odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(11) | BIT(10)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(dm, 0xcbc, 0x3f, 0x0); + odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(dm, 0xebc, 0x3f, 0x0); + odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0); /* delay 400ns for PAPE */ - /* odm_set_bb_reg(p_dm_odm, 0x810, MASKBYTE3|BIT20|BIT21|BIT22|BIT23, 0x211); */ + /* odm_set_bb_reg(dm, 0x810, MASKBYTE3|BIT20|BIT21|BIT22|BIT23, 0x211); */ /* antenna switch table */ - if ((p_dm_odm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) || (p_dm_odm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) { + if ((dm->rx_ant_status == BB_PATH_AB) || (dm->tx_ant_status == BB_PATH_AB)) { /* 2TX or 2RX */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa501); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa501); - } else if (p_dm_odm->rx_ant_status == p_dm_odm->tx_ant_status) { + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501); + } else if (dm->rx_ant_status == dm->tx_ant_status) { /* TXA+RXA or TXB+RXB */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa500); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa500); + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500); } else { /* TXB+RXA or TXA+RXB */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa005); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa005); + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005); } } - } else if ((p_dm_odm->rfe_type == 0) || (p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5) || (p_dm_odm->rfe_type == 8) || (p_dm_odm->rfe_type == 10) || (p_dm_odm->rfe_type == 12)) { + } else if ((rfe_type == 0) || (rfe_type == 3) || (rfe_type == 5) || (rfe_type == 8) || (rfe_type == 10) || (rfe_type == 12) || (rfe_type == 13) || (rfe_type == 14) || (rfe_type == 16) || (rfe_type == 17)) { /* iFEM */ - if (channel <= 14) { + if (is_channel_2g) { /* signal source */ - odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x745774); - odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x745774); - odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x57); - odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x57); + odm_set_bb_reg(dm, 0xcb0, 0xffffff, 0x745774); + odm_set_bb_reg(dm, 0xeb0, 0xffffff, 0x745774); + odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57); + odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57); - } else if (channel > 35) { + } else { /* signal source */ - odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x477547); - odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x477547); - odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x75); - odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x75); - - } else - return false; + odm_set_bb_reg(dm, 0xcb0, 0xffffff, 0x477547); + odm_set_bb_reg(dm, 0xeb0, 0xffffff, 0x477547); + odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75); + odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75); + } /* inverse or not */ - odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(11) | BIT(10)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(dm, 0xcbc, 0x3f, 0x0); + odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(dm, 0xebc, 0x3f, 0x0); + odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0); /* antenna switch table */ - if (channel <= 14) { - if ((p_dm_odm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) || (p_dm_odm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) { + if (is_channel_2g) { + if ((dm->rx_ant_status == BB_PATH_AB) || (dm->tx_ant_status == BB_PATH_AB)) { /* 2TX or 2RX */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa501); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa501); - } else if (p_dm_odm->rx_ant_status == p_dm_odm->tx_ant_status) { + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501); + } else if (dm->rx_ant_status == dm->tx_ant_status) { /* TXA+RXA or TXB+RXB */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa500); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa500); + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500); } else { /* TXB+RXA or TXA+RXB */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa005); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa005); + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005); } - } else if (channel > 35) { - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa5a5); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa5a5); + } else { + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa5a5); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa5a5); } + } else if (rfe_type == 15) { + /* iFEM for Microsoft, 5G low/high band */ + phydm_8822b_type15_rfe(dm, channel); } + #if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) + else if (rfe_type == SMTANT_TMP_RFE_TYPE) { + /*modify from RFE_TYPE = 1*/ + + if (is_channel_2g) { + #if 0 + /* signal source */ + odm_set_bb_reg(dm, 0xcb0, 0xffffff, 0x705770); + odm_set_bb_reg(dm, 0xeb0, 0xffffff, 0x705770); + odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57); + odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57); + odm_set_bb_reg(dm, 0xcb8, BIT(4), 0); + odm_set_bb_reg(dm, 0xeb8, BIT(4), 0); + + /* inverse or not */ + odm_set_bb_reg(dm, 0xcbc, 0x3f, 0x0); + odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(dm, 0xebc, 0x3f, 0x0); + odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0); + + #endif + } else { + /* signal source */ + #if 1 + /*path A*/ + odm_set_bb_reg(dm, 0x1990, BIT(3), 0); /*RFE_CTRL_3*/ /*A_0*/ + odm_set_bb_reg(dm, 0x1990, BIT(0), 0); /*RFE_CTRL_0*/ /*A_1*/ + odm_set_bb_reg(dm, 0x1990, BIT(8), 0); /*RFE_CTRL_8*/ /*A_2*/ + + /*path B*/ + odm_set_bb_reg(dm, 0x1990, BIT(4), 1); /*RFE_CTRL_4*/ /*B_0*/ + odm_set_bb_reg(dm, 0x1990, BIT(11), 1); /*RFE_CTRL_11*/ /*B_1*/ + odm_set_bb_reg(dm, 0x1990, BIT(9), 1); /*RFE_CTRL_9*/ /*B_2*/ + + odm_set_bb_reg(dm, 0xcb0, MASKDWORD, 0x77178519); + //odm_set_bb_reg(dm, 0xeb0, MASKDWORD, 0x77177517); + odm_set_bb_reg(dm, 0xeb0, MASKDWORD, 0x771c7517); + odm_set_bb_reg(dm, 0xcb4, MASKDWORD, 0x757a); + //odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x7577); + odm_set_bb_reg(dm, 0xeb4, MASKDWORD, 0xd5e7); - /* chip top mux */ - odm_set_bb_reg(p_dm_odm, 0x64, BIT(29) | BIT(28), 0x3); - odm_set_bb_reg(p_dm_odm, 0x4c, BIT(26) | BIT(25), 0x0); - odm_set_bb_reg(p_dm_odm, 0x40, BIT(2), 0x1); - - /* from s0 or s1 */ - odm_set_bb_reg(p_dm_odm, 0x1990, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x30); - odm_set_bb_reg(p_dm_odm, 0x1990, (BIT(11) | BIT(10)), 0x3); - - /* input or output */ - odm_set_bb_reg(p_dm_odm, 0x974, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x3f); - odm_set_bb_reg(p_dm_odm, 0x974, (BIT(11) | BIT(10)), 0x3); + /* inverse or not */ + odm_set_bb_reg(dm, 0xcbc, 0xfff, 0x0); + odm_set_bb_reg(dm, 0xebc, 0xfff, 0x0); + #else + phydm_rfe_8822b_setting(dm, 1, BB_PATH_A, 0, PAPE_5G); + phydm_rfe_8822b_setting(dm, 2, BB_PATH_A, 0, TRSW_B); + phydm_rfe_8822b_setting(dm, 5, BB_PATH_B, 0, PAPE_5G); + phydm_rfe_8822b_setting(dm, 10, BB_PATH_B, 0, TRSW_B); + #endif + + odm_set_bb_reg(dm, 0xcb8, BIT(5), 0); + odm_set_bb_reg(dm, 0xeb8, BIT(5), 0); + } + + /* delay 400ns for PAPE */ + /* odm_set_bb_reg(dm, 0x810, MASKBYTE3|BIT20|BIT21|BIT22|BIT23, 0x211); */ - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update RFE control pin setting (ch%d, tx_path 0x%x, rx_path 0x%x)\n", __func__, channel, p_dm_odm->tx_ant_status, p_dm_odm->rx_ant_status)); + /* antenna switch table */ + if ((dm->rx_ant_status == BB_PATH_AB) || (dm->tx_ant_status == BB_PATH_AB)) { + /* 2TX or 2RX */ + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501); + } else if (dm->rx_ant_status == dm->tx_ant_status) { + /* TXA+RXA or TXB+RXB */ + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500); + } else { + /* TXB+RXA or TXA+RXB */ + odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005); + odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005); + } + } + #endif return true; } @@ -323,7 +562,7 @@ phydm_is_dfs_channel(u8 channel_num) __iram_odm_func__ void phydm_ccapar_by_rfe_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u32 cca_ifem[3][4], cca_efem[3][4]; @@ -332,42 +571,42 @@ phydm_ccapar_by_rfe_8822b( boolean is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false; #if !(DM_ODM_SUPPORT_TYPE == ODM_CE) - if (p_dm_odm->cut_version == ODM_CUT_B) { - odm_move_memory(p_dm_odm, cca_efem, cca_efem_bcut, 12 * 4); - odm_move_memory(p_dm_odm, cca_ifem, cca_ifem_bcut, 12 * 4); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Bcut\n", __func__)); + if (dm->cut_version == ODM_CUT_B) { + odm_move_memory(dm, cca_efem, cca_efem_bcut, 12 * 4); + odm_move_memory(dm, cca_ifem, cca_ifem_bcut, 12 * 4); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: Update CCA parameters for Bcut\n", __func__); } else #endif { - odm_move_memory(p_dm_odm, cca_efem, cca_efem_ccut, 12 * 4); - if ((p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5)) { - odm_move_memory(p_dm_odm, cca_ifem, cca_ifem_ccut_rfetype, 12 * 4); + odm_move_memory(dm, cca_efem, cca_efem_ccut, 12 * 4); + if ((dm->rfe_type == 3) || (dm->rfe_type == 5) || (dm->rfe_type == 12) || (dm->rfe_type == 15) || (dm->rfe_type == 16) || (dm->rfe_type == 17)) { + odm_move_memory(dm, cca_ifem, cca_ifem_ccut_rfetype, 12 * 4); is_rfe_type = true; } else - odm_move_memory(p_dm_odm, cca_ifem, cca_ifem_ccut, 12 * 4); + odm_move_memory(dm, cca_ifem, cca_ifem_ccut, 12 * 4); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Ccut\n", __func__)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: Update CCA parameters for Ccut\n", __func__); } if (central_ch_8822b <= 14) { - if ((p_dm_odm->rx_ant_status == ODM_RF_A) || (p_dm_odm->rx_ant_status == ODM_RF_B)) + if ((dm->rx_ant_status == BB_PATH_A) || (dm->rx_ant_status == BB_PATH_B)) col = 0; /*1R 2G*/ else col = 1; /*2R 2G*/ } else { - if ((p_dm_odm->rx_ant_status == ODM_RF_A) || (p_dm_odm->rx_ant_status == ODM_RF_B)) + if ((dm->rx_ant_status == BB_PATH_A) || (dm->rx_ant_status == BB_PATH_B)) col = 2; /*1R 5G*/ else col = 3; /*2R 5G*/ } - if ((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 4) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7) || (p_dm_odm->rfe_type == 11)) { + if ((dm->rfe_type == 1) || (dm->rfe_type == 4) || (dm->rfe_type == 6) || (dm->rfe_type == 7) || (dm->rfe_type == 11)) { /*eFEM => RFE type 1 & RFE type 4 & RFE type 6 & RFE type 7 & RFE type 11*/ reg82c = cca_efem[0][col]; reg830 = cca_efem[1][col]; reg838 = cca_efem[2][col]; is_efem_cca = true; - } else if ((p_dm_odm->rfe_type == 2) || (p_dm_odm->rfe_type == 9)) { + } else if ((dm->rfe_type == 2) || (dm->rfe_type == 9)) { /*5G eFEM, 2G iFEM => RFE type 2, 5G eFEM => RFE type 9 */ if (central_ch_8822b <= 14) { reg82c = cca_ifem[0][col]; @@ -381,71 +620,73 @@ phydm_ccapar_by_rfe_8822b( is_efem_cca = true; } } else { - /* iFEM =>RFEtype 3 & RFE type 5 & RFE type 0 & RFE type 8 & RFE type 10 & RFE type 12*/ + /* iFEM =>RFEtype 3 & RFE type 5 & RFE type 0 & RFE type 8 & RFE type 10 & RFE type 12 & RFE type 13 & RFE type 15~17 */ reg82c = cca_ifem[0][col]; reg830 = cca_ifem[1][col]; reg838 = cca_ifem[2][col]; is_ifem_cca = true; } - odm_set_bb_reg(p_dm_odm, 0x82c, MASKDWORD, reg82c); + odm_set_bb_reg(dm, 0x82c, MASKDWORD, reg82c); if (is_ifem_cca == true) - if (((p_dm_odm->cut_version == ODM_CUT_B) && (col == 1 || col == 3) && (bw_8822b == ODM_BW40M)) || - ((is_rfe_type == false) && (col == 3) && (bw_8822b == ODM_BW40M)) || - ((p_dm_odm->rfe_type == 5) && (col == 3))) - odm_set_bb_reg(p_dm_odm, 0x830, MASKDWORD, 0x79a0ea28); + if (((dm->cut_version == ODM_CUT_B) && (col == 1 || col == 3) && (bw_8822b == CHANNEL_WIDTH_40)) || + ((is_rfe_type == false) && (col == 3) && (bw_8822b == CHANNEL_WIDTH_40)) || + ((dm->rfe_type == 5) && (col == 3))) + odm_set_bb_reg(dm, 0x830, MASKDWORD, 0x79a0ea28); else - odm_set_bb_reg(p_dm_odm, 0x830, MASKDWORD, reg830); + odm_set_bb_reg(dm, 0x830, MASKDWORD, reg830); else - odm_set_bb_reg(p_dm_odm, 0x830, MASKDWORD, reg830); + odm_set_bb_reg(dm, 0x830, MASKDWORD, reg830); - odm_set_bb_reg(p_dm_odm, 0x838, MASKDWORD, reg838); + odm_set_bb_reg(dm, 0x838, MASKDWORD, reg838); - if ((is_efem_cca == true) && !(p_dm_odm->cut_version == ODM_CUT_B)) - odm_set_bb_reg(p_dm_odm, 0x83c, MASKDWORD, 0x9194b2b9); + if ((is_efem_cca == true) && !(dm->cut_version == ODM_CUT_B)) + odm_set_bb_reg(dm, 0x83c, MASKDWORD, 0x9194b2b9); - if (phydm_is_dfs_channel(central_ch_8822b) && (bw_8822b == ODM_BW80M)) - odm_set_bb_reg(p_dm_odm, 0x838, 0x1, 0); + /* enlarge big jump size in type 16 for MS case */ + if ((dm->rfe_type == 16) && (central_ch_8822b <= 14)) + odm_set_bb_reg(dm, 0x8c8, BIT(3) | BIT (2) | BIT(1), 0x3); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: (Pkt%d, Intf%d, RFE%d), col = %d\n", - __func__, p_dm_odm->package_type, p_dm_odm->support_interface, p_dm_odm->rfe_type, col)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: (Pkt%d, Intf%d, RFE%d), col = %d\n", + __func__, dm->package_type, dm->support_interface, dm->rfe_type, col); } __iram_odm_func__ void phydm_rxdfirpar_by_bw_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_bw_e bandwidth + struct dm_struct *dm, + enum channel_width bandwidth ) { - if (bandwidth == ODM_BW40M) { + if (bandwidth == CHANNEL_WIDTH_40) { /* RX DFIR for BW40 */ - odm_set_bb_reg(p_dm_odm, 0x948, BIT(29) | BIT(28), 0x1); - odm_set_bb_reg(p_dm_odm, 0x94c, BIT(29) | BIT(28), 0x0); - odm_set_bb_reg(p_dm_odm, 0xc20, BIT(31), 0x0); - odm_set_bb_reg(p_dm_odm, 0xe20, BIT(31), 0x0); - } else if (bandwidth == ODM_BW80M) { + odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x1); + odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x0); + odm_set_bb_reg(dm, 0xc20, BIT(31), 0x0); + odm_set_bb_reg(dm, 0xe20, BIT(31), 0x0); + } else if (bandwidth == CHANNEL_WIDTH_80) { /* RX DFIR for BW80 */ - odm_set_bb_reg(p_dm_odm, 0x948, BIT(29) | BIT(28), 0x2); - odm_set_bb_reg(p_dm_odm, 0x94c, BIT(29) | BIT(28), 0x1); - odm_set_bb_reg(p_dm_odm, 0xc20, BIT(31), 0x0); - odm_set_bb_reg(p_dm_odm, 0xe20, BIT(31), 0x0); + odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x1); + odm_set_bb_reg(dm, 0xc20, BIT(31), 0x0); + odm_set_bb_reg(dm, 0xe20, BIT(31), 0x0); } else { /* RX DFIR for BW20, BW10 and BW5*/ - odm_set_bb_reg(p_dm_odm, 0x948, BIT(29) | BIT(28), 0x2); - odm_set_bb_reg(p_dm_odm, 0x94c, BIT(29) | BIT(28), 0x2); - odm_set_bb_reg(p_dm_odm, 0xc20, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0xe20, BIT(31), 0x1); + odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(dm, 0xc20, BIT(31), 0x1); + odm_set_bb_reg(dm, 0xe20, BIT(31), 0x1); } + /* PHYDM_DBG(dm, ODM_PHY_CONFIG, "phydm_rxdfirpar_by_bw_8822b\n");*/ } __iram_odm_func__ boolean phydm_write_txagc_1byte_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 power_index, - enum odm_rf_radio_path_e path, + enum rf_path path, u8 hw_rate ) { @@ -459,22 +700,22 @@ phydm_write_txagc_1byte_8822b( /* For debug command only!!!! */ /* Error handling */ - if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): unsupported path (%d)\n", path)); + if ((path > RF_PATH_B) || (hw_rate > 0x53)) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "phydm_write_txagc_1byte_8822b(): unsupported path (%d)\n", path); return false; } /* For HW limitation, We can't write TXAGC once a byte. */ for (i = 0; i < 4; i++) { if (i != rate_offset) - txagc_content = txagc_content | (config_phydm_read_txagc_8822b(p_dm_odm, path, rate_idx + i) << (i << 3)); + txagc_content = txagc_content | (config_phydm_read_txagc_8822b(dm, path, rate_idx + i) << (i << 3)); else txagc_content = txagc_content | ((power_index & 0x3f) << (i << 3)); } - odm_set_bb_reg(p_dm_odm, (offset_txagc[path] + rate_idx), MASKDWORD, txagc_content); + odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD, txagc_content); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): path-%d rate index 0x%x (0x%x) = 0x%x\n", - path, hw_rate, (offset_txagc[path] + hw_rate), power_index)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "phydm_write_txagc_1byte_8822b(): path-%d rate index 0x%x (0x%x) = 0x%x\n", + path, hw_rate, (offset_txagc[path] + hw_rate), power_index); return true; #else return false; @@ -484,7 +725,7 @@ phydm_write_txagc_1byte_8822b( __iram_odm_func__ void phydm_init_hw_info_by_rfe_type_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { #if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1) @@ -493,152 +734,152 @@ phydm_init_hw_info_by_rfe_type_8822b( /*u16 mask_path_c = 0x3030;*/ /*u16 mask_path_d = 0xc0c0;*/ - p_dm_odm->is_init_hw_info_by_rfe = false; - - if ((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7)) { - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G)); - - if (p_dm_odm->rfe_type == 6) { - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a | mask_path_b))); - } else if (p_dm_odm->rfe_type == 7) { - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GPA, (TYPE_GPA2 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_APA, (TYPE_APA2 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GLNA, (TYPE_GLNA2 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA2 & (mask_path_a | mask_path_b))); + dm->is_init_hw_info_by_rfe = false; + + if ((dm->rfe_type == 1) || (dm->rfe_type == 6) || (dm->rfe_type == 7)) { + odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G)); + + if (dm->rfe_type == 6) { + odm_cmn_info_init(dm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a | mask_path_b))); + } else if (dm->rfe_type == 7) { + odm_cmn_info_init(dm, ODM_CMNINFO_GPA, (TYPE_GPA2 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_APA, (TYPE_APA2 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_GLNA, (TYPE_GLNA2 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_ALNA, (TYPE_ALNA2 & (mask_path_a | mask_path_b))); } else { - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a | mask_path_b))); } - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); - - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, true); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, true); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, true); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, true); - } else if (p_dm_odm->rfe_type == 2) { - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA_5G)); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a | mask_path_b))); - - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 2); - - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, true); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, true); - } else if (p_dm_odm->rfe_type == 9) { - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G)); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a | mask_path_b))); - - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); - - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, true); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); - } else if (p_dm_odm->rfe_type == 3) { + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1); + + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, true); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, true); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true); + } else if (dm->rfe_type == 2) { + odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA_5G)); + odm_cmn_info_init(dm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a | mask_path_b))); + + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true); + } else if (dm->rfe_type == 9) { + odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G)); + odm_cmn_info_init(dm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a | mask_path_b))); + + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1); + + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false); + } else if (dm->rfe_type == 3) { /* RFE type 3: 8822BS\8822BU TFBGA iFEM */ - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, 0); + odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); - } else if (p_dm_odm->rfe_type == 5) { + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false); + } else if (dm->rfe_type == 5) { /* RFE type 5: 8822BE TFBGA iFEM */ - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_SLIM); + odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_SLIM); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); - } else if (p_dm_odm->rfe_type == 12) { + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false); + } else if (dm->rfe_type == 12) { /* RFE type 12: QFN iFEM */ - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, 0); + odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); - } else if (p_dm_odm->rfe_type == 4) { - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G)); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a | mask_path_b))); - - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 2); - - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, true); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, true); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, true); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, true); - } else if (p_dm_odm->rfe_type == 11) { - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G)); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false); + } else if (dm->rfe_type == 4) { + odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G)); + odm_cmn_info_init(dm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a | mask_path_b))); + + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2); + + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, true); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, true); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true); + } else if (dm->rfe_type == 11) { + odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G)); + odm_cmn_info_init(dm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a | mask_path_b))); + odm_cmn_info_init(dm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a | mask_path_b))); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, true); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, true); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, true); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, true); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, true); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, true); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true); - } else if (p_dm_odm->rfe_type == 8) { + } else if (dm->rfe_type == 8) { /* RFE type 8: TFBGA iFEM AP */ - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, 0); + odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 2); + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); - } else if (p_dm_odm->rfe_type == 10) { + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false); + } else if (dm->rfe_type == 10) { /* RFE type 10: QFN iFEM AP PCIE TRSW */ - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_TRSW); + odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, ODM_BOARD_EXT_TRSW); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false); } else { /* RFE Type 0: QFN iFEM */ - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_BOARD_TYPE, 0); + odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_LNA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_EXT_PA, false); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_5G_EXT_PA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false); + odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false); } - p_dm_odm->is_init_hw_info_by_rfe = true; + dm->is_init_hw_info_by_rfe = true; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, - ("%s: RFE type (%d), Board type (0x%x), Package type (%d)\n", __func__, p_dm_odm->rfe_type, p_dm_odm->board_type, p_dm_odm->package_type)); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, - ("%s: 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n", __func__, p_dm_odm->ext_pa_5g, p_dm_odm->ext_lna_5g, p_dm_odm->ext_pa, p_dm_odm->ext_lna)); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, - ("%s: 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n", __func__, p_dm_odm->type_apa, p_dm_odm->type_alna, p_dm_odm->type_gpa, p_dm_odm->type_glna)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: RFE type (%d), Board type (0x%x), Package type (%d)\n", __func__, dm->rfe_type, dm->board_type, dm->package_type); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n", __func__, dm->ext_pa_5g, dm->ext_lna_5g, dm->ext_pa, dm->ext_lna); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n", __func__, dm->type_apa, dm->type_alna, dm->type_gpa, dm->type_glna); #endif /*PHYDM_FW_API_FUNC_ENABLE_8822B == 1*/ } @@ -646,13 +887,13 @@ phydm_init_hw_info_by_rfe_type_8822b( __iram_odm_func__ s32 phydm_get_condition_number_8822B( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { s32 ret_val; - odm_set_bb_reg(p_dm_odm, 0x1988, BIT(22), 0x1); - ret_val = (s32)odm_get_bb_reg(p_dm_odm, 0xf84, (BIT(17) | BIT(16) | MASKLWORD)); + odm_set_bb_reg(dm, 0x1988, BIT(22), 0x1); + ret_val = (s32)odm_get_bb_reg(dm, 0xf84, (BIT(17) | BIT(16) | MASKLWORD)); if (bw_8822b == 0) { ret_val = ret_val << (8 - 4); @@ -676,8 +917,8 @@ phydm_get_condition_number_8822B( __iram_odm_func__ u32 config_phydm_read_rf_reg_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e rf_path, + struct dm_struct *dm, + enum rf_path path, u32 reg_addr, u32 bit_mask ) @@ -686,30 +927,30 @@ config_phydm_read_rf_reg_8822b( u32 offset_read_rf[2] = {0x2800, 0x2c00}; /* Error handling.*/ - if (rf_path > ODM_RF_PATH_B) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): unsupported path (%d)\n", rf_path)); + if (path > RF_PATH_B) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_read_rf_reg_8822b(): unsupported path (%d)\n", path); return INVALID_RF_DATA; } /* Calculate offset */ reg_addr &= 0xff; - direct_addr = offset_read_rf[rf_path] + (reg_addr << 2); + direct_addr = offset_read_rf[path] + (reg_addr << 2); /* RF register only has 20bits */ bit_mask &= RFREGOFFSETMASK; /* Read RF register directly */ - readback_value = odm_get_bb_reg(p_dm_odm, direct_addr, bit_mask); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", - rf_path, reg_addr, readback_value, bit_mask)); + readback_value = odm_get_bb_reg(dm, direct_addr, bit_mask); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_read_rf_reg_8822b(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", + path, reg_addr, readback_value, bit_mask); return readback_value; } __iram_odm_func__ boolean config_phydm_write_rf_reg_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e rf_path, + struct dm_struct *dm, + enum rf_path path, u32 reg_addr, u32 bit_mask, u32 data @@ -719,8 +960,8 @@ config_phydm_write_rf_reg_8822b( u32 offset_write_rf[2] = {0xc90, 0xe90}; /* Error handling.*/ - if (rf_path > ODM_RF_PATH_B) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): unsupported path (%d)\n", rf_path)); + if (path > RF_PATH_B) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_write_rf_reg_8822b(): unsupported path (%d)\n", path); return false; } @@ -729,11 +970,11 @@ config_phydm_write_rf_reg_8822b( bit_mask = bit_mask & RFREGOFFSETMASK; if (bit_mask != RFREGOFFSETMASK) { - data_original = config_phydm_read_rf_reg_8822b(p_dm_odm, rf_path, reg_addr, RFREGOFFSETMASK); + data_original = config_phydm_read_rf_reg_8822b(dm, path, reg_addr, RFREGOFFSETMASK); /* Error handling. RF is disabled */ if (config_phydm_read_rf_check_8822b(data_original) == false) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): Write fail, RF is disable\n")); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_write_rf_reg_8822b(): Write fail, RF is disable\n"); return false; } @@ -745,56 +986,51 @@ config_phydm_write_rf_reg_8822b( data_and_addr = ((reg_addr << 20) | (data & 0x000fffff)) & 0x0fffffff; /* Write operation */ - odm_set_bb_reg(p_dm_odm, offset_write_rf[rf_path], MASKDWORD, data_and_addr); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", - rf_path, reg_addr, data, data_original, bit_mask)); + odm_set_bb_reg(dm, offset_write_rf[path], MASKDWORD, data_and_addr); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_write_rf_reg_8822b(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", + path, reg_addr, data, data_original, bit_mask); return true; } __iram_odm_func__ boolean config_phydm_write_txagc_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 power_index, - enum odm_rf_radio_path_e path, + enum rf_path path, u8 hw_rate ) { -#if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1) - u32 offset_txagc[2] = {0x1d00, 0x1d80}; u8 rate_idx = (hw_rate & 0xfc); /* Input need to be HW rate index, not driver rate index!!!! */ - if (p_dm_odm->is_disable_phy_api) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): disable PHY API for debug!!\n")); + if (dm->is_disable_phy_api) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_write_txagc_8822b(): disable PHY API for debug!!\n"); return true; } /* Error handling */ - if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): unsupported path (%d)\n", path)); + if ((path > RF_PATH_B) || (hw_rate > 0x53)) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_write_txagc_8822b(): unsupported path (%d)\n", path); return false; } /* driver need to construct a 4-byte power index */ - odm_set_bb_reg(p_dm_odm, (offset_txagc[path] + rate_idx), MASKDWORD, power_index); + odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD, power_index); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): path-%d rate index 0x%x (0x%x) = 0x%x\n", - path, hw_rate, (offset_txagc[path] + hw_rate), power_index)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_write_txagc_8822b(): path-%d rate index 0x%x (0x%x) = 0x%x\n", + path, hw_rate, (offset_txagc[path] + hw_rate), power_index); return true; -#else - return false; -#endif } __iram_odm_func__ u8 config_phydm_read_txagc_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e path, + struct dm_struct *dm, + enum rf_path path, u8 hw_rate ) { @@ -804,27 +1040,27 @@ config_phydm_read_txagc_8822b( /* Input need to be HW rate index, not driver rate index!!!! */ /* Error handling */ - if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): unsupported path (%d)\n", path)); + if ((path > RF_PATH_B) || (hw_rate > 0x53)) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_read_txagc_8822b(): unsupported path (%d)\n", path); return INVALID_TXAGC_DATA; } /* Disable TX AGC report */ - odm_set_bb_reg(p_dm_odm, 0x1998, BIT(16), 0x0); /* need to check */ + odm_set_bb_reg(dm, 0x1998, BIT(16), 0x0); /* need to check */ /* Set data rate index (bit0~6) and path index (bit7) */ - odm_set_bb_reg(p_dm_odm, 0x1998, MASKBYTE0, (hw_rate | (path << 7))); + odm_set_bb_reg(dm, 0x1998, MASKBYTE0, (hw_rate | (path << 7))); /* Enable TXAGC report */ - odm_set_bb_reg(p_dm_odm, 0x1998, BIT(16), 0x1); + odm_set_bb_reg(dm, 0x1998, BIT(16), 0x1); /* Read TX AGC report */ - read_back_data = (u8)odm_get_bb_reg(p_dm_odm, 0xd30, 0x7f0000); + read_back_data = (u8)odm_get_bb_reg(dm, 0xd30, 0x7f0000); /* Driver have to disable TXAGC report after reading TXAGC (ref. user guide v11) */ - odm_set_bb_reg(p_dm_odm, 0x1998, BIT(16), 0x0); + odm_set_bb_reg(dm, 0x1998, BIT(16), 0x0); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): path-%d rate index 0x%x = 0x%x\n", path, hw_rate, read_back_data)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_read_txagc_8822b(): path-%d rate index 0x%x = 0x%x\n", path, hw_rate, read_back_data); return read_back_data; #else return 0; @@ -833,54 +1069,60 @@ config_phydm_read_txagc_8822b( __iram_odm_func__ void -phydm_dynamic_spur_det_elimitor( - struct PHY_DM_STRUCT *p_dm_odm +phydm_dynamic_spur_det_eliminate( + struct dm_struct *dm ) { #if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1) - u32 freq_2g[number_of_2g_freq_pt] = {0xFC67, 0xFC27, 0xFFE6, 0xFFA6, 0xFC67, 0xFCE7, 0xFCA7, 0xFC67, 0xFC27, 0xFFE6, 0xFFA6, 0xFF66, 0xFF26, 0xFCE7}; - u32 freq_5g[number_of_5g_freq_pt] = {0xFFC0, 0xFFC0, 0xFC81, 0xFC81, 0xFC41, 0xFC40, 0xFF80, 0xFF80, 0xFF40, 0xFD42}; - u32 freq_2g_n1[number_of_2g_freq_pt] = {0}, freq_2g_p1[number_of_2g_freq_pt] = {0}; - u32 freq_5g_n1[number_of_5g_freq_pt] = {0}, freq_5g_p1[number_of_5g_freq_pt] = {0}; + u32 freq_2g[FREQ_PT_2G_NUM] = {0xFC67, 0xFC27, 0xFFE6, 0xFFA6, 0xFC67, 0xFCE7, 0xFCA7, 0xFC67, 0xFC27, 0xFFE6, 0xFFA6, 0xFF66, 0xFF26, 0xFCE7}; + u32 freq_5g[FREQ_PT_5G_NUM] = {0xFFC0, 0xFFC0, 0xFC81, 0xFC81, 0xFC41, 0xFC40, 0xFF80, 0xFF80, 0xFF40, 0xFD42}; + u32 freq_2g_n1[FREQ_PT_2G_NUM] = {0}, freq_2g_p1[FREQ_PT_2G_NUM] = {0}; + u32 freq_5g_n1[FREQ_PT_5G_NUM] = {0}, freq_5g_p1[FREQ_PT_5G_NUM] = {0}; u32 freq_pt_2g_final = 0, freq_pt_5g_final = 0, freq_pt_2g_b_final = 0, freq_pt_5g_b_final = 0; u32 max_ret_psd_final = 0, max_ret_psd_b_final = 0; - u32 max_ret_psd_2nd[number_of_sample] = {0}, max_ret_psd_b_2nd[number_of_sample] = {0}; - u32 psd_set[number_of_psd_value] = {0}, psd_set_B[number_of_psd_value] = {0}; - u32 rank_psd_index_in[number_of_psd_value] = {0}, rank_sample_index_in[number_of_sample] = {0}; - u32 rank_psd_index_out[number_of_psd_value] = {0}; - u32 rank_sample_index_out[number_of_sample] = {0}; + u32 max_ret_psd_2nd[PSD_SMP_NUM] = {0}, max_ret_psd_b_2nd[PSD_SMP_NUM] = {0}; + u32 psd_set[PSD_VAL_NUM] = {0}, psd_set_B[PSD_VAL_NUM] = {0}; + u32 rank_psd_index_in[PSD_VAL_NUM] = {0}, rank_sample_index_in[PSD_SMP_NUM] = {0}; + u32 rank_psd_index_out[PSD_VAL_NUM] = {0}; + u32 rank_sample_index_out[PSD_SMP_NUM] = {0}; u32 reg_910_15_12 = 0; u8 j = 0, k = 0, threshold_nbi = 0x8D, threshold_csi = 0x8D; - u8 idx = 0, set_result_nbi = SET_NO_NEED, set_result_csi = SET_NO_NEED; + u8 idx = 0, set_result_nbi = PHYDM_SET_NO_NEED, set_result_csi = PHYDM_SET_NO_NEED; boolean s_dopsd = false, s_donbi_a = false, s_docsi = false, s_donbi_b = false; - if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_PSDTOOL)) { - ODM_RT_TRACE(p_dm_odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[Return Init] Not Support Dynamic Spur Detection and Eliminator\n")); - return; - } - - ODM_RT_TRACE(p_dm_odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("Dynamic Spur Detection and Eliminator is ON\n")); + /* Reset NBI/CSI everytime after changing channel/BW/band */ + odm_set_bb_reg(dm, 0x880, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x884, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x888, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x88c, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x890, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x894, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x898, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x89c, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x874, BIT(0), 0x0); + + odm_set_bb_reg(dm, 0x87c, BIT(13), 0x0); + odm_set_bb_reg(dm, 0xc20, BIT(28), 0x0); + odm_set_bb_reg(dm, 0xe20, BIT(28), 0x0); /* 2G Channel Setting > 20M: 5, 6, 7, 8, 13; 40M: 3~11 */ - if ((*p_dm_odm->p_channel >= 1) && (*p_dm_odm->p_channel <= 14)) { - if (*p_dm_odm->p_band_width == ODM_BW20M) { - - if (*p_dm_odm->p_channel >= 5 && *p_dm_odm->p_channel <= 8) - idx = *p_dm_odm->p_channel - 5; - else if (*p_dm_odm->p_channel == 13) + if ((*dm->channel >= 1) && (*dm->channel <= 14)) { + if (*dm->band_width == CHANNEL_WIDTH_20) { + if (*dm->channel >= 5 && *dm->channel <= 8) + idx = *dm->channel - 5; + else if (*dm->channel == 13) idx = 4; else idx = 16; } else { - - if (*p_dm_odm->p_channel >= 3 && *p_dm_odm->p_channel <= 11) - idx = *p_dm_odm->p_channel + 2; + if (*dm->channel >= 3 && *dm->channel <= 11) + idx = *dm->channel + 2; else idx = 16; } } else { /* 5G Channel Setting > 20M: 153, 161; 40M: 54, 118, 151, 159; 80M: 58, 122, 155, 155 */ - switch (*p_dm_odm->p_channel) { + switch (*dm->channel) { case 153: idx = 0; break; @@ -914,210 +1156,214 @@ phydm_dynamic_spur_det_elimitor( } } - if (idx == 16) - s_dopsd = false; - else + if (idx <= 16) { s_dopsd = true; + } else { + PHYDM_DBG(dm, ODM_COMP_API, "[Return Point] Idx Is Exceed, Not Support Dynamic Spur Detection and Eliminator\n"); + return; + } + + PHYDM_DBG(dm, ODM_COMP_API, "[%s] idx = %d, BW = %d, Channel = %d\n", __func__, idx, *dm->band_width, *dm->channel); - ODM_RT_TRACE(p_dm_odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[%s] idx = %d, BW = %d, Channel = %d\n", __func__, idx, *p_dm_odm->p_band_width, *p_dm_odm->p_channel)); - - for (k = 0; k < number_of_2g_freq_pt; k++) { + for (k = 0; k < FREQ_PT_2G_NUM; k++) { freq_2g_n1[k] = freq_2g[k] - 1; freq_2g_p1[k] = freq_2g[k] + 1; } - for (k = 0; k < number_of_5g_freq_pt; k++) { + for (k = 0; k < FREQ_PT_5G_NUM; k++) { freq_5g_n1[k] = freq_5g[k] - 1; freq_5g_p1[k] = freq_5g[k] + 1; } - if ((s_dopsd == TRUE) && (idx <= 13)) { - for (k = 0; k < number_of_sample; k++) { - if (k == 0) { - freq_pt_2g_final = freq_2g_n1[idx]; + if (!s_dopsd || idx > 13) { + PHYDM_DBG(dm, ODM_COMP_API, "[Return Point] s_dopsd is flase, Not Support Dynamic Spur Detection and Eliminator\n"); + return; + } + + for (k = 0; k < PSD_SMP_NUM; k++) { + if (k == 0) { + freq_pt_2g_final = freq_2g_n1[idx]; + freq_pt_2g_b_final = freq_2g_n1[idx] | BIT(16); + if (idx <= 10) { freq_pt_5g_final = freq_5g_n1[idx]; - freq_pt_2g_b_final = freq_2g_n1[idx] | BIT(16); freq_pt_5g_b_final = freq_5g_n1[idx] | BIT(16); - } else if (k == 1) { - freq_pt_2g_final = freq_2g[idx]; + } + } else if (k == 1) { + freq_pt_2g_final = freq_2g[idx]; + freq_pt_2g_b_final = freq_2g[idx] | BIT(16); + if (idx <= 10) { freq_pt_5g_final = freq_5g[idx]; - freq_pt_2g_b_final = freq_2g[idx] | BIT(16); freq_pt_5g_b_final = freq_5g[idx] | BIT(16); - } else if (k == 2) { - freq_pt_2g_final = freq_2g_p1[idx]; + } + } else if (k == 2) { + freq_pt_2g_final = freq_2g_p1[idx]; + freq_pt_2g_b_final = freq_2g_p1[idx] | BIT(16); + if (idx <= 10) { freq_pt_5g_final = freq_5g_p1[idx]; - freq_pt_2g_b_final = freq_2g_p1[idx] | BIT(16); freq_pt_5g_b_final = freq_5g_p1[idx] | BIT(16); } + } - for (j = 0; j < number_of_psd_value; j++) { - odm_set_bb_reg(p_dm_odm, 0xc00, MASKBYTE0, 0x4);/* disable 3-wire, path-A */ - odm_set_bb_reg(p_dm_odm, 0xe00, MASKBYTE0, 0x4);/* disable 3-wire, path-B */ - reg_910_15_12 = odm_get_bb_reg(p_dm_odm, 0x910, (BIT15 | BIT14 | BIT13 | BIT12)); + for (j = 0; j < PSD_VAL_NUM; j++) { + odm_set_bb_reg(dm, 0xc00, MASKBYTE0, 0x4);/* disable 3-wire, path-A */ + odm_set_bb_reg(dm, 0xe00, MASKBYTE0, 0x4);/* disable 3-wire, path-B */ + reg_910_15_12 = odm_get_bb_reg(dm, 0x910, (BIT(15) | BIT(14) | BIT(13) | BIT(12))); - if (p_dm_odm->rx_ant_status & ODM_RF_A) { - odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, (((ODM_RF_A)<<4) | ODM_RF_A));/*path-A*/ + if (dm->rx_ant_status & BB_PATH_A) { + odm_set_bb_reg(dm, 0x808, MASKBYTE0, (((BB_PATH_A)<<4) | BB_PATH_A));/*path-A*/ - if ((*p_dm_odm->p_channel >= 1) && (*p_dm_odm->p_channel <= 14)) - odm_set_bb_reg(p_dm_odm, 0x910, MASKDWORD, BIT(22) | freq_pt_2g_final);/* Start PSD */ - else - odm_set_bb_reg(p_dm_odm, 0x910, MASKDWORD, BIT(22) | freq_pt_5g_final);/* Start PSD */ + if ((*dm->channel >= 1) && (*dm->channel <= 14)) + odm_set_bb_reg(dm, 0x910, MASKDWORD, BIT(22) | freq_pt_2g_final);/* Start PSD */ + else + odm_set_bb_reg(dm, 0x910, MASKDWORD, BIT(22) | freq_pt_5g_final);/* Start PSD */ - ODM_delay_us(500); + ODM_delay_us(500); - psd_set[j] = odm_get_bb_reg(p_dm_odm, 0xf44, MASKLWORD); + psd_set[j] = odm_get_bb_reg(dm, 0xf44, MASKLWORD); - odm_set_bb_reg(p_dm_odm, 0x910, BIT22, 0x0);/* turn off PSD */ - } + odm_set_bb_reg(dm, 0x910, BIT(22), 0x0);/* turn off PSD */ + } - if (p_dm_odm->rx_ant_status & ODM_RF_B) { - odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, (((ODM_RF_B)<<4) | ODM_RF_B));/*path-B*/ + if (dm->rx_ant_status & BB_PATH_B) { + odm_set_bb_reg(dm, 0x808, MASKBYTE0, (((BB_PATH_B)<<4) | BB_PATH_B));/*path-B*/ - if ((*p_dm_odm->p_channel > 0) && (*p_dm_odm->p_channel <= 14)) - odm_set_bb_reg(p_dm_odm, 0x910, MASKDWORD, BIT(22) | freq_pt_2g_b_final);/* Start PSD */ - else - odm_set_bb_reg(p_dm_odm, 0x910, MASKDWORD, BIT(22) | freq_pt_5g_b_final);/* Start PSD */ + if ((*dm->channel > 0) && (*dm->channel <= 14)) + odm_set_bb_reg(dm, 0x910, MASKDWORD, BIT(22) | freq_pt_2g_b_final);/* Start PSD */ + else + odm_set_bb_reg(dm, 0x910, MASKDWORD, BIT(22) | freq_pt_5g_b_final);/* Start PSD */ - ODM_delay_us(500); + ODM_delay_us(500); - psd_set_B[j] = odm_get_bb_reg(p_dm_odm, 0xf44, MASKLWORD); + psd_set_B[j] = odm_get_bb_reg(dm, 0xf44, MASKLWORD); - odm_set_bb_reg(p_dm_odm, 0x910, BIT22, 0x0);/* turn off PSD */ - } + odm_set_bb_reg(dm, 0x910, BIT(22), 0x0);/* turn off PSD */ + } - odm_set_bb_reg(p_dm_odm, 0xc00, MASKBYTE0, 0x7);/*eanble 3-wire*/ - odm_set_bb_reg(p_dm_odm, 0xe00, MASKBYTE0, 0x7); - odm_set_bb_reg(p_dm_odm, 0x910, (BIT15 | BIT14 | BIT13 | BIT12), reg_910_15_12); + odm_set_bb_reg(dm, 0xc00, MASKBYTE0, 0x7);/*eanble 3-wire*/ + odm_set_bb_reg(dm, 0xe00, MASKBYTE0, 0x7); + odm_set_bb_reg(dm, 0x910, (BIT(15) | BIT(14) | BIT(13) | BIT(12)), reg_910_15_12); - odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, (((p_dm_odm->rx_ant_status)<<4) | p_dm_odm->rx_ant_status)); + odm_set_bb_reg(dm, 0x808, MASKBYTE0, (((dm->rx_ant_status)<<4) | dm->rx_ant_status)); - /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */ - phydm_igi_toggle_8822b(p_dm_odm); + /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */ + phydm_igi_toggle_8822b(dm); - } - if (p_dm_odm->rx_ant_status & ODM_RF_A) { - phydm_seq_sorting(p_dm_odm, psd_set, rank_psd_index_in, rank_psd_index_out, number_of_psd_value); - max_ret_psd_2nd[k] = psd_set[0]; - } - if (p_dm_odm->rx_ant_status & ODM_RF_B) { - phydm_seq_sorting(p_dm_odm, psd_set_B, rank_psd_index_in, rank_psd_index_out, number_of_psd_value); - max_ret_psd_b_2nd[k] = psd_set_B[0]; - } } - - if (p_dm_odm->rx_ant_status & ODM_RF_A) { - phydm_seq_sorting(p_dm_odm, max_ret_psd_2nd, rank_sample_index_in, rank_sample_index_out, number_of_sample); - max_ret_psd_final = max_ret_psd_2nd[0]; - - if (max_ret_psd_final >= threshold_nbi) - s_donbi_a = true; - else - s_donbi_a = false; + if (dm->rx_ant_status & BB_PATH_A) { + phydm_seq_sorting(dm, psd_set, rank_psd_index_in, rank_psd_index_out, PSD_VAL_NUM); + max_ret_psd_2nd[k] = psd_set[0]; } - if (p_dm_odm->rx_ant_status & ODM_RF_B) { - phydm_seq_sorting(p_dm_odm, max_ret_psd_b_2nd, rank_sample_index_in, rank_sample_index_out, number_of_sample); - max_ret_psd_b_final = max_ret_psd_b_2nd[0]; - - if (max_ret_psd_b_final >= threshold_nbi) - s_donbi_b = true; - else - s_donbi_b = false; + if (dm->rx_ant_status & BB_PATH_B) { + phydm_seq_sorting(dm, psd_set_B, rank_psd_index_in, rank_psd_index_out, PSD_VAL_NUM); + max_ret_psd_b_2nd[k] = psd_set_B[0]; } + } - ODM_RT_TRACE(p_dm_odm, ODM_BB_DYNAMIC_PSDTOOL, ODM_DBG_LOUD, ("[%s] max_ret_psd_final = %d, max_ret_psd_b_final = %d\n", __func__, max_ret_psd_final, max_ret_psd_b_final)); + if (dm->rx_ant_status & BB_PATH_A) { + phydm_seq_sorting(dm, max_ret_psd_2nd, rank_sample_index_in, rank_sample_index_out, PSD_SMP_NUM); + max_ret_psd_final = max_ret_psd_2nd[0]; - if ((max_ret_psd_final >= threshold_csi) || (max_ret_psd_b_final >= threshold_csi)) - s_docsi = true; + if (max_ret_psd_final >= threshold_nbi) + s_donbi_a = true; else - s_docsi = false; + s_donbi_a = false; + } + if (dm->rx_ant_status & BB_PATH_B) { + phydm_seq_sorting(dm, max_ret_psd_b_2nd, rank_sample_index_in, rank_sample_index_out, PSD_SMP_NUM); + max_ret_psd_b_final = max_ret_psd_b_2nd[0]; + if (max_ret_psd_b_final >= threshold_nbi) + s_donbi_b = true; + else + s_donbi_b = false; } - /* Reset NBI/CSI everytime after changing channel/BW/band */ - odm_set_bb_reg(p_dm_odm, 0x880, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x884, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x888, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x88c, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x890, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x894, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x898, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x89c, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x874, BIT(0), 0x0); - - odm_set_bb_reg(p_dm_odm, 0x87c, BIT(13), 0x0); - odm_set_bb_reg(p_dm_odm, 0xc20, BIT(28), 0x0); - odm_set_bb_reg(p_dm_odm, 0xe20, BIT(28), 0x0); + PHYDM_DBG(dm, ODM_COMP_API, "[%s] max_ret_psd_final = %d, max_ret_psd_b_final = %d\n", __func__, max_ret_psd_final, max_ret_psd_b_final); + + if ((max_ret_psd_final >= threshold_csi) || (max_ret_psd_b_final >= threshold_csi)) + s_docsi = true; + else + s_docsi = false; if (s_donbi_a == true || s_donbi_b == true) { - if (*p_dm_odm->p_band_width == ODM_BW20M) { - if (*p_dm_odm->p_channel == 153) - set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 20, 5760, PHYDM_DONT_CARE); - else if (*p_dm_odm->p_channel == 161) - set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 20, 5800, PHYDM_DONT_CARE); - else if (*p_dm_odm->p_channel >= 5 && *p_dm_odm->p_channel <= 8) - set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 20, 2440, PHYDM_DONT_CARE); - else if (*p_dm_odm->p_channel == 13) - set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 20, 2480, PHYDM_DONT_CARE); + if (*dm->band_width == CHANNEL_WIDTH_20) { + if (*dm->channel == 153) + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 20, 5760, PHYDM_DONT_CARE); + else if (*dm->channel == 161) + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 20, 5800, PHYDM_DONT_CARE); + else if (*dm->channel >= 5 && *dm->channel <= 8) + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 20, 2440, PHYDM_DONT_CARE); + else if (*dm->channel == 13) + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 20, 2480, PHYDM_DONT_CARE); else - set_result_nbi = SET_NO_NEED; - } else if (*p_dm_odm->p_band_width == ODM_BW40M) { - if (*p_dm_odm->p_channel == 54) { - set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 40, 5280, PHYDM_DONT_CARE); - } else if (*p_dm_odm->p_channel == 118) { - set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 40, 5600, PHYDM_DONT_CARE); - } else if (*p_dm_odm->p_channel == 151) { - set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 40, 5760, PHYDM_DONT_CARE); - } else if (*p_dm_odm->p_channel == 159) { - set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 40, 5800, PHYDM_DONT_CARE); + set_result_nbi = PHYDM_SET_NO_NEED; + } else if (*dm->band_width == CHANNEL_WIDTH_40) { + if (*dm->channel == 54) { + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 40, 5280, PHYDM_DONT_CARE); + } else if (*dm->channel == 118) { + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 40, 5600, PHYDM_DONT_CARE); + } else if (*dm->channel == 151) { + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 40, 5760, PHYDM_DONT_CARE); + } else if (*dm->channel == 159) { + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 40, 5800, PHYDM_DONT_CARE); /* 2.4G */ - } else if ((*p_dm_odm->p_channel >= 4) && (*p_dm_odm->p_channel <= 6)) { - set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 40, 2440, PHYDM_DONT_CARE); - } else if (*p_dm_odm->p_channel == 11) { - set_result_nbi = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, *p_dm_odm->p_channel, 40, 2480, PHYDM_DONT_CARE); + } else if ((*dm->channel >= 4) && (*dm->channel <= 6)) { + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 40, 2440, PHYDM_DONT_CARE); + } else if (*dm->channel == 11) { + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 40, 2480, PHYDM_DONT_CARE); + } else + set_result_nbi = PHYDM_SET_NO_NEED; + } else if (*dm->band_width == CHANNEL_WIDTH_80) { + if (*dm->channel == 58) { + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 80, 5280, PHYDM_DONT_CARE); + } else if (*dm->channel == 122) { + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 80, 5600, PHYDM_DONT_CARE); + } else if (*dm->channel == 155) { + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 80, 5760, PHYDM_DONT_CARE); } else - set_result_nbi = SET_NO_NEED; + set_result_nbi = PHYDM_SET_NO_NEED; } else - set_result_nbi = SET_NO_NEED; + set_result_nbi = PHYDM_SET_NO_NEED; } if (s_docsi == true) { - if (*p_dm_odm->p_band_width == ODM_BW20M) { - if (*p_dm_odm->p_channel == 153) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 20, 5760, PHYDM_DONT_CARE); - else if (*p_dm_odm->p_channel == 161) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 20, 5800, PHYDM_DONT_CARE); - else if (*p_dm_odm->p_channel >= 5 && *p_dm_odm->p_channel <= 8) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 20, 2440, PHYDM_DONT_CARE); - else if (*p_dm_odm->p_channel == 13) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 20, 2480, PHYDM_DONT_CARE); + if (*dm->band_width == CHANNEL_WIDTH_20) { + if (*dm->channel == 153) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 20, 5760, PHYDM_DONT_CARE); + else if (*dm->channel == 161) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 20, 5800, PHYDM_DONT_CARE); + else if (*dm->channel >= 5 && *dm->channel <= 8) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 20, 2440, PHYDM_DONT_CARE); + else if (*dm->channel == 13) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 20, 2480, PHYDM_DONT_CARE); else - set_result_csi = SET_NO_NEED; - } else if (*p_dm_odm->p_band_width == ODM_BW40M) { - if (*p_dm_odm->p_channel == 54) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 40, 5280, PHYDM_DONT_CARE); - else if (*p_dm_odm->p_channel == 118) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 40, 5600, PHYDM_DONT_CARE); - else if (*p_dm_odm->p_channel == 151) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 40, 5760, PHYDM_DONT_CARE); - else if (*p_dm_odm->p_channel == 159) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 40, 5800, PHYDM_DONT_CARE); - else if ((*p_dm_odm->p_channel >= 3) && (*p_dm_odm->p_channel <= 10)) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 40, 2440, PHYDM_DONT_CARE); - else if (*p_dm_odm->p_channel == 11) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 40, 2480, PHYDM_DONT_CARE); + set_result_csi = PHYDM_SET_NO_NEED; + } else if (*dm->band_width == CHANNEL_WIDTH_40) { + if (*dm->channel == 54) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 40, 5280, PHYDM_DONT_CARE); + else if (*dm->channel == 118) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 40, 5600, PHYDM_DONT_CARE); + else if (*dm->channel == 151) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 40, 5760, PHYDM_DONT_CARE); + else if (*dm->channel == 159) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 40, 5800, PHYDM_DONT_CARE); + else if ((*dm->channel >= 3) && (*dm->channel <= 10)) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 40, 2440, PHYDM_DONT_CARE); + else if (*dm->channel == 11) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 40, 2480, PHYDM_DONT_CARE); else - set_result_csi = SET_NO_NEED; - } else if (*p_dm_odm->p_band_width == ODM_BW80M) { - if (*p_dm_odm->p_channel == 58) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 80, 5280, PHYDM_DONT_CARE); - else if (*p_dm_odm->p_channel == 122) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 80, 5600, PHYDM_DONT_CARE); - else if (*p_dm_odm->p_channel == 155) - set_result_csi = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, *p_dm_odm->p_channel, 80, 5760, PHYDM_DONT_CARE); + set_result_csi = PHYDM_SET_NO_NEED; + } else if (*dm->band_width == CHANNEL_WIDTH_80) { + if (*dm->channel == 58) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 80, 5280, PHYDM_DONT_CARE); + else if (*dm->channel == 122) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 80, 5600, PHYDM_DONT_CARE); + else if (*dm->channel == 155) + set_result_csi = phydm_csi_mask_setting(dm, FUNC_ENABLE, *dm->channel, 80, 5760, PHYDM_DONT_CARE); else - set_result_csi = SET_NO_NEED; + set_result_csi = PHYDM_SET_NO_NEED; } else - set_result_csi = SET_NO_NEED; + set_result_csi = PHYDM_SET_NO_NEED; } #endif /*PHYDM_SPUR_CANCELL_ENABLE_8822B == 1*/ @@ -1126,7 +1372,7 @@ phydm_dynamic_spur_det_elimitor( __iram_odm_func__ boolean config_phydm_switch_band_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 central_ch ) { @@ -1134,129 +1380,153 @@ config_phydm_switch_band_8822b( boolean rf_reg_status = true; u32 reg_8; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b()======================>\n")); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_band_8822b()======================>\n"); - if (p_dm_odm->is_disable_phy_api) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): disable PHY API for debug!!\n")); + if (dm->is_disable_phy_api) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_band_8822b(): disable PHY API for debug!!\n"); return true; } - rf_reg18 = config_phydm_read_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + rf_reg18 = config_phydm_read_rf_reg_8822b(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK); rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); if (central_ch <= 14) { /* 2.4G */ /* Enable CCK block */ - odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0x1); + odm_set_bb_reg(dm, 0x808, BIT(28), 0x1); /* Disable MAC CCK check */ - odm_set_bb_reg(p_dm_odm, 0x454, BIT(7), 0x0); + odm_set_bb_reg(dm, 0x454, BIT(7), 0x0); /* Disable BB CCK check */ - odm_set_bb_reg(p_dm_odm, 0xa80, BIT(18), 0x0); + odm_set_bb_reg(dm, 0xa80, BIT(18), 0x0); /*CCA Mask*/ - odm_set_bb_reg(p_dm_odm, 0x814, 0x0000FC00, 15); /*default value*/ + odm_set_bb_reg(dm, 0x814, 0x0000FC00, 15); /*default value*/ /* RF band */ rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8)))); /* RxHP dynamic control */ /* QFN eFEM RxHP are always low at 2G */ - reg_8 = odm_get_bb_reg(p_dm_odm, 0x19a8, BIT(31)); + reg_8 = odm_get_bb_reg(dm, 0x19a8, BIT(31)); - if (!((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7) || (p_dm_odm->rfe_type == 9))) { - /* SoML on */ - if ((reg_8 == 0x1) && (!((p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5)))) { - odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08100000); - odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x0); - odm_set_bb_reg(p_dm_odm, 0xc04, (BIT(18)|BIT(21)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xe04, (BIT(18)|BIT(21)), 0x0); - /* SoML off */ + /* SoML on */ + if (reg_8 == 0x1) { + odm_set_bb_reg(dm, 0xc04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(dm, 0xe04, (BIT(18)|BIT(21)), 0x0); + if ((dm->rfe_type == 3) || (dm->rfe_type == 5) || (dm->rfe_type == 8) || (dm->rfe_type == 17)) { + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492); + odm_set_bb_reg(dm, 0x8d8, BIT(19), 0x0); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x1); } else { - odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08108492); - odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x1); - odm_set_bb_reg(p_dm_odm, 0xc04, BIT(18), 0x1); - odm_set_bb_reg(p_dm_odm, 0xe04, BIT(18), 0x1); - odm_set_bb_reg(p_dm_odm, 0xc04, BIT(21), 0x1); - odm_set_bb_reg(p_dm_odm, 0xe04, BIT(21), 0x1); + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000); + odm_set_bb_reg(dm, 0x8d8, BIT(19), 0x0); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0); } } - + + /* SoML off */ + if (reg_8 == 0x0) { + odm_set_bb_reg(dm, 0xc04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(dm, 0xe04, (BIT(18)|BIT(21)), 0x0); + if ((dm->rfe_type == 1) || (dm->rfe_type == 6) || (dm->rfe_type == 7) || (dm->rfe_type == 9)) { + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000); + odm_set_bb_reg(dm, 0x8d8, BIT(19), 0x0); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0); + } else { + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492); + odm_set_bb_reg(dm, 0x8d8, BIT(19), 0x0); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x1); + } + } + } else if (central_ch > 35) { /* 5G */ /* Enable BB CCK check */ - odm_set_bb_reg(p_dm_odm, 0xa80, BIT(18), 0x1); + odm_set_bb_reg(dm, 0xa80, BIT(18), 0x1); /* Enable CCK check */ - odm_set_bb_reg(p_dm_odm, 0x454, BIT(7), 0x1); + odm_set_bb_reg(dm, 0x454, BIT(7), 0x1); /* Disable CCK block */ - odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0x0); + odm_set_bb_reg(dm, 0x808, BIT(28), 0x0); /*CCA Mask*/ - if (!p_dm_odm->wifi_test) - odm_set_bb_reg(p_dm_odm, 0x814, 0x0000FC00, 34); /*CCA mask = 13.6us*/ + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + odm_set_bb_reg(dm, 0x814, 0x0000FC00, 34); /*CCA mask = 13.6us*/ + #else + if ((!dm->wifi_test)) + odm_set_bb_reg(dm, 0x814, 0x0000FC00, 34); /*CCA mask = 13.6us*/ else - odm_set_bb_reg(p_dm_odm, 0x814, 0x0000FC00, 15); /*default value*/ + odm_set_bb_reg(dm, 0x814, 0x0000FC00, 15); /*default value*/ + #endif /* RF band */ rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8)))); rf_reg18 = (rf_reg18 | BIT(8) | BIT(16)); /* RxHP dynamic control */ - reg_8 = odm_get_bb_reg(p_dm_odm, 0x19a8, BIT(31)); - - if ((reg_8 == 0x1) && (!((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7) || (p_dm_odm->rfe_type == 9)))) { - odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08100000); - odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x0); - odm_set_bb_reg(p_dm_odm, 0xc04, (BIT(18)|BIT(21)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xe04, (BIT(18)|BIT(21)), 0x0); - } else { - odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08108492); - odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x1); - odm_set_bb_reg(p_dm_odm, 0xc04, BIT(18), 0x1); - odm_set_bb_reg(p_dm_odm, 0xe04, BIT(18), 0x1); - odm_set_bb_reg(p_dm_odm, 0xc04, BIT(21), 0x1); - odm_set_bb_reg(p_dm_odm, 0xe04, BIT(21), 0x1); + reg_8 = odm_get_bb_reg(dm, 0x19a8, BIT(31)); + + /* SoML on */ + if (reg_8 == 0x1) { + odm_set_bb_reg(dm, 0xc04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(dm, 0xe04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0); } + /* SoML off */ + if (reg_8 == 0x0) { + odm_set_bb_reg(dm, 0xc04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(dm, 0xe04, (BIT(18)|BIT(21)), 0x0); + if ((dm->rfe_type == 1) || (dm->rfe_type == 6) || (dm->rfe_type == 7) || (dm->rfe_type == 9)) { + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000); + odm_set_bb_reg(dm, 0x8d8, BIT(19), 0x0); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0); + } else { + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492); + odm_set_bb_reg(dm, 0x8d8, BIT(19), 0x0); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x1); + } + } } else { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d)\n", central_ch)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_band_8822b(): Fail to switch band (ch: %d)\n", central_ch); return false; } - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); + odm_set_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); - if (p_dm_odm->rf_type > ODM_1T1R) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_B, 0x18, RFREGOFFSETMASK, rf_reg18); + if (dm->rf_type > RF_1T1R) + odm_set_rf_reg(dm, RF_PATH_B, 0x18, RFREGOFFSETMASK, rf_reg18); - if (phydm_rfe_8822b(p_dm_odm, central_ch) == false) + if (phydm_rfe_8822b(dm, central_ch) == false) return false; if (rf_reg_status == false) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d), because writing RF register is fail\n", central_ch)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_band_8822b(): Fail to switch band (ch: %d), because writing RF register is fail\n", central_ch); return false; } /* Dynamic spur detection by PSD and NBI/CSI mask */ - if (*(p_dm_odm->p_mp_mode)) - phydm_dynamic_spur_det_elimitor(p_dm_odm); + if (*dm->mp_mode) + phydm_dynamic_spur_det_eliminate(dm); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Success to switch band (ch: %d)\n", central_ch)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_band_8822b(): Success to switch band (ch: %d)\n", central_ch); return true; } __iram_odm_func__ boolean config_phydm_switch_channel_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 central_ch ) { - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct phydm_dig_struct *dig_tab = &dm->dm_dig_table; u32 rf_reg18 = 0, rf_reg_be = 0xff; boolean rf_reg_status = true; u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6}; @@ -1264,26 +1534,29 @@ config_phydm_switch_channel_8822b( u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 0x7, 0x7, 0x6, 0x5, 0x5, 0x0}; u8 band_index = 0; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b()====================>\n")); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_channel_8822b()====================>\n"); - if (p_dm_odm->is_disable_phy_api) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): disable PHY API for debug!!\n")); + if (dm->is_disable_phy_api) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_channel_8822b(): disable PHY API for debug!!\n"); return true; } central_ch_8822b = central_ch; - + /* Errir handling for wrong HW setting due to wrong channel setting */ if (central_ch_8822b <= 14) band_index = 1; else band_index = 2; - if (p_dm_odm->rfe_hwsetting_band != band_index) - phydm_rfe_8822b(p_dm_odm, central_ch_8822b); + if (dm->rfe_hwsetting_band != band_index) + phydm_rfe_8822b(dm, central_ch_8822b); + + if (dm->rfe_type == 15) + phydm_rfe_8822b(dm, central_ch_8822b); /* RF register setting */ - rf_reg18 = config_phydm_read_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + rf_reg18 = config_phydm_read_rf_reg_8822b(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK); rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0))); @@ -1295,20 +1568,20 @@ config_phydm_switch_channel_8822b( rf_reg18 = (rf_reg18 | central_ch); /* 2. AGC table selection */ - odm_set_bb_reg(p_dm_odm, 0x958, 0x1f, 0x0); - p_dm_dig_table->agc_table_idx = 0x0; + odm_set_bb_reg(dm, 0x958, 0x1f, 0x0); + dig_tab->agc_table_idx = 0x0; /* 3. Set central frequency for clock offset tracking */ - odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x96a); + odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x96a); /* CCK TX filter parameters */ if (central_ch == 14) { - odm_set_bb_reg(p_dm_odm, 0xa24, MASKDWORD, 0x00006577); - odm_set_bb_reg(p_dm_odm, 0xa28, MASKLWORD, 0x0000); + odm_set_bb_reg(dm, 0xa24, MASKDWORD, 0x00006577); + odm_set_bb_reg(dm, 0xa28, MASKLWORD, 0x0000); } else { - odm_set_bb_reg(p_dm_odm, 0xa24, MASKDWORD, 0x384f6577); - odm_set_bb_reg(p_dm_odm, 0xa28, MASKLWORD, 0x1525); + odm_set_bb_reg(dm, 0xa24, MASKDWORD, 0x384f6577); + odm_set_bb_reg(dm, 0xa28, MASKLWORD, 0x1525); } } else if (central_ch > 35) { @@ -1318,45 +1591,52 @@ config_phydm_switch_channel_8822b( rf_reg18 = (rf_reg18 | central_ch); /* 2. AGC table selection */ - if ((central_ch >= 36) && (central_ch <= 64)) { - odm_set_bb_reg(p_dm_odm, 0x958, 0x1f, 0x1); - p_dm_dig_table->agc_table_idx = 0x1; - } else if ((central_ch >= 100) && (central_ch <= 144)) { - odm_set_bb_reg(p_dm_odm, 0x958, 0x1f, 0x2); - p_dm_dig_table->agc_table_idx = 0x2; - } else if (central_ch >= 149) { - odm_set_bb_reg(p_dm_odm, 0x958, 0x1f, 0x3); - p_dm_dig_table->agc_table_idx = 0x3; - } else { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (AGC) (ch: %d)\n", central_ch)); - return false; + if (!((dm->rfe_type == 15) || (dm->rfe_type == 16))) { + if ((central_ch >= 36) && (central_ch <= 64)) { + odm_set_bb_reg(dm, 0x958, 0x1f, 0x1); + dig_tab->agc_table_idx = 0x1; + } else if ((central_ch >= 100) && (central_ch <= 144)) { + odm_set_bb_reg(dm, 0x958, 0x1f, 0x2); + dig_tab->agc_table_idx = 0x2; + } else if (central_ch >= 149) { + odm_set_bb_reg(dm, 0x958, 0x1f, 0x3); + dig_tab->agc_table_idx = 0x3; + } else { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_channel_8822b(): Fail to switch channel (AGC) (ch: %d)\n", central_ch); + return false; + } + } else if ((dm->rfe_type == 15) || (dm->rfe_type == 16)) { + if (dm->brxagcswitch) + phydm_rxagc_switch_8822b(dm, true); + else + phydm_rxagc_switch_8822b(dm, false); } /* 3. Set central frequency for clock offset tracking */ if ((central_ch >= 36) && (central_ch <= 48)) - odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x494); + odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x494); else if ((central_ch >= 52) && (central_ch <= 64)) - odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x453); + odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x453); else if ((central_ch >= 100) && (central_ch <= 116)) - odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x452); + odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x452); else if ((central_ch >= 118) && (central_ch <= 177)) - odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x412); + odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x412); else { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (fc_area) (ch: %d)\n", central_ch)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_channel_8822b(): Fail to switch channel (fc_area) (ch: %d)\n", central_ch); return false; } } else { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d)\n", central_ch)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d)\n", central_ch); return false; } /* Modify IGI for MP driver to aviod PCIE interference */ - if ((*(p_dm_odm->p_mp_mode) == true) && ((p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5))) { + if (*dm->mp_mode && ((dm->rfe_type == 3) || (dm->rfe_type == 5))) { if (central_ch == 14) - odm_write_dig(p_dm_odm, 0x26); + odm_write_dig(dm, 0x26); else - odm_write_dig(p_dm_odm, 0x20); + odm_write_dig(dm, 0x20); } /* Modify the setting of register 0xBE to reduce phase noise */ @@ -1368,13 +1648,11 @@ config_phydm_switch_channel_8822b( rf_reg_be = middle_band[(central_ch - 100) >> 1]; else if ((central_ch >= 149) && (central_ch <= 177)) rf_reg_be = high_band[(central_ch - 149) >> 1]; - else - rf_reg_be = 0xff; if (rf_reg_be != 0xff) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xbe, (BIT(17) | BIT(16) | BIT(15)), rf_reg_be); + odm_set_rf_reg(dm, RF_PATH_A, 0xbe, (BIT(17) | BIT(16) | BIT(15)), rf_reg_be); else { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d, Phase noise)\n", central_ch)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d, Phase noise)\n", central_ch); return false; } @@ -1382,10 +1660,10 @@ config_phydm_switch_channel_8822b( /* 00 when freq < 5400; 01 when 5400<=freq<=5720; 10 when freq > 5720; 2G don't care*/ /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ if (central_ch == 144) { - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xdf, BIT(18), 0x1); + odm_set_rf_reg(dm, RF_PATH_A, 0xdf, BIT(18), 0x1); rf_reg18 = (rf_reg18 | BIT(17)); } else { - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xdf, BIT(18), 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xdf, BIT(18), 0x0); if (central_ch > 144) rf_reg18 = (rf_reg18 | BIT(18)); @@ -1393,102 +1671,113 @@ config_phydm_switch_channel_8822b( rf_reg18 = (rf_reg18 | BIT(17)); } - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); + odm_set_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); - if (p_dm_odm->rf_type > ODM_1T1R) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_B, 0x18, RFREGOFFSETMASK, rf_reg18); + if (dm->rf_type > RF_1T1R) + odm_set_rf_reg(dm, RF_PATH_B, 0x18, RFREGOFFSETMASK, rf_reg18); if (rf_reg_status == false) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d), because writing RF register is fail\n", central_ch)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d), because writing RF register is fail\n", central_ch); return false; } /* Debug for RF resister reading error during synthesizer parameters parsing */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xb8, BIT(19), 0); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xb8, BIT(19), 1); + odm_set_rf_reg(dm, RF_PATH_A, 0xb8, BIT(19), 0); + odm_set_rf_reg(dm, RF_PATH_A, 0xb8, BIT(19), 1); - phydm_igi_toggle_8822b(p_dm_odm); + phydm_igi_toggle_8822b(dm); /* Dynamic spur detection by PSD and NBI/CSI mask */ - if (*(p_dm_odm->p_mp_mode)) - phydm_dynamic_spur_det_elimitor(p_dm_odm); + if (*dm->mp_mode) + phydm_dynamic_spur_det_eliminate(dm); - phydm_ccapar_by_rfe_8822b(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Success to switch channel (ch: %d)\n", central_ch)); + phydm_ccapar_by_rfe_8822b(dm); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_channel_8822b(): Success to switch channel (ch: %d)\n", central_ch); return true; } __iram_odm_func__ boolean config_phydm_switch_bandwidth_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 primary_ch_idx, - enum odm_bw_e bandwidth + enum channel_width bandwidth ) { - u32 rf_reg18; + u32 rf_reg18, val32; boolean rf_reg_status = true; + u8 rfe_type = dm->rfe_type; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b()===================>\n")); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_bandwidth_8822b()===================>\n"); - if (p_dm_odm->is_disable_phy_api) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): disable PHY API for debug!!\n")); + if (dm->is_disable_phy_api) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_bandwidth_8822b(): disable PHY API for debug!!\n"); return true; } /* Error handling */ - if ((bandwidth >= ODM_BW_MAX) || ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) || ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); + if ((bandwidth >= CHANNEL_WIDTH_MAX) || ((bandwidth == CHANNEL_WIDTH_40) && (primary_ch_idx > 2)) || ((bandwidth == CHANNEL_WIDTH_80) && (primary_ch_idx > 4))) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx); return false; } bw_8822b = bandwidth; - rf_reg18 = config_phydm_read_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + rf_reg18 = config_phydm_read_rf_reg_8822b(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK); rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18); /* Switch bandwidth */ switch (bandwidth) { - case ODM_BW20M: + case CHANNEL_WIDTH_20: { /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, ODM_BW20M); + /* odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, CHANNEL_WIDTH_20);*/ /* ADC clock = 160M clock for BW20 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(9) | BIT(8)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(16), 0x1); + /* odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x0);*/ + /* odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x1);*/ /* DAC clock = 160M clock for BW20 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(21) | BIT(20)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(28), 0x1); + /* odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x0);*/ + /* odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x1);*/ + + val32 = odm_get_bb_reg(dm, 0x8ac, MASKDWORD); + val32 &= 0xFFCFFC00; + val32 |= (CHANNEL_WIDTH_20); + odm_set_bb_reg(dm, 0x8ac, MASKDWORD, val32); /* ADC buffer clock */ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x1); + odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1); /* RF bandwidth */ rf_reg18 = (rf_reg18 | BIT(11) | BIT(10)); break; } - case ODM_BW40M: + case CHANNEL_WIDTH_40: { /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 40M */ - odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | ODM_BW40M)); + /* odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_40));*/ /* CCK primary channel */ if (primary_ch_idx == 1) - odm_set_bb_reg(p_dm_odm, 0xa00, BIT(4), primary_ch_idx); + odm_set_bb_reg(dm, 0xa00, BIT(4), primary_ch_idx); else - odm_set_bb_reg(p_dm_odm, 0xa00, BIT(4), 0); + odm_set_bb_reg(dm, 0xa00, BIT(4), 0); /* ADC clock = 160M clock for BW40 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(11) | BIT(10)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(17), 0x1); + /*odm_set_bb_reg(dm, 0x8ac, (BIT(11) | BIT(10)), 0x0);*/ + /*odm_set_bb_reg(dm, 0x8ac, BIT(17), 0x1);*/ /* DAC clock = 160M clock for BW20 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(23) | BIT(22)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(29), 0x1); + /*odm_set_bb_reg(dm, 0x8ac, (BIT(23) | BIT(22)), 0x0);*/ + /*odm_set_bb_reg(dm, 0x8ac, BIT(29), 0x1);*/ + + val32 = odm_get_bb_reg(dm, 0x8ac, MASKDWORD); + val32 &= 0xFF3FF300; + val32 |= (((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_40); + odm_set_bb_reg(dm, 0x8ac, MASKDWORD, val32); /* ADC buffer clock */ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x1); + odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1); /* RF bandwidth */ rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10)))); @@ -1496,66 +1785,87 @@ config_phydm_switch_bandwidth_8822b( break; } - case ODM_BW80M: + case CHANNEL_WIDTH_80: { /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */ - odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | ODM_BW80M)); + /*odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_80));*/ /* ADC clock = 160M clock for BW80 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(13) | BIT(12)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(18), 0x1); + /*odm_set_bb_reg(dm, 0x8ac, (BIT(13) | BIT(12)), 0x0);*/ + /*odm_set_bb_reg(dm, 0x8ac, BIT(18), 0x1);*/ /* DAC clock = 160M clock for BW20 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(25) | BIT(24)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(30), 0x1); + /*odm_set_bb_reg(dm, 0x8ac, (BIT(25) | BIT(24)), 0x0);*/ + /*odm_set_bb_reg(dm, 0x8ac, BIT(30), 0x1);*/ + + val32 = odm_get_bb_reg(dm, 0x8ac, MASKDWORD); + val32 &= 0xFCEFCF00; + val32 |= (((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_80); + odm_set_bb_reg(dm, 0x8ac, MASKDWORD, val32); /* ADC buffer clock */ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x1); + odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1); /* RF bandwidth */ rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10)))); rf_reg18 = (rf_reg18 | BIT(10)); + /* Parameters for SD4 TP requirement */ + if ((rfe_type == 2) || (rfe_type == 3) || (rfe_type == 17) ) { + odm_set_bb_reg(dm, 0x840, 0x0000f000, 0x6); + odm_set_bb_reg(dm, 0x8c8, BIT(10), 0x1); + } + break; } - case ODM_BW5M: + case CHANNEL_WIDTH_5: { /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (BIT(6) | ODM_BW20M)); + /*dm_set_bb_reg(dm, 0x8ac, MASKBYTE0, (BIT(6) | CHANNEL_WIDTH_20));*/ /* ADC clock = 40M clock */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(9) | BIT(8)), 0x2); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(16), 0x0); + /*odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x2);*/ + /*odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x0);*/ /* DAC clock = 160M clock for BW20 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(21) | BIT(20)), 0x2); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(28), 0x0); + /*odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x2);*/ + /*odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x0);*/ + + val32 = odm_get_bb_reg(dm, 0x8ac, MASKDWORD); + val32 &= 0xEFEEFE00; + val32 |= ((BIT(6) | CHANNEL_WIDTH_20)); + odm_set_bb_reg(dm, 0x8ac, MASKDWORD, val32); /* ADC buffer clock */ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8c8, BIT(31), 0x1); + odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x0); + odm_set_bb_reg(dm, 0x8c8, BIT(31), 0x1); /* RF bandwidth */ rf_reg18 = (rf_reg18 | BIT(11) | BIT(10)); break; } - case ODM_BW10M: + case CHANNEL_WIDTH_10: { /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (BIT(7) | ODM_BW20M)); + /*odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, (BIT(7) | CHANNEL_WIDTH_20));*/ /* ADC clock = 80M clock */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(9) | BIT(8)), 0x3); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(16), 0x0); + /*odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x3);*/ + /*odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x0);*/ /* DAC clock = 160M clock for BW20 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(21) | BIT(20)), 0x3); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(28), 0x0); + /*odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x3);*/ + /*odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x0);*/ + + val32 = odm_get_bb_reg(dm, 0x8ac, MASKDWORD); + val32 &= 0xEFFEFF00; + val32 |= ((BIT(7) | CHANNEL_WIDTH_20)); + odm_set_bb_reg(dm, 0x8ac, MASKDWORD, val32); /* ADC buffer clock */ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8c8, BIT(31), 0x1); + odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x0); + odm_set_bb_reg(dm, 0x8c8, BIT(31), 0x1); /* RF bandwidth */ rf_reg18 = (rf_reg18 | BIT(11) | BIT(10)); @@ -1563,61 +1873,60 @@ config_phydm_switch_bandwidth_8822b( break; } default: - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx); } /* Write RF register */ - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); + odm_set_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); - if (p_dm_odm->rf_type > ODM_1T1R) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_B, 0x18, RFREGOFFSETMASK, rf_reg18); + if (dm->rf_type > RF_1T1R) + odm_set_rf_reg(dm, RF_PATH_B, 0x18, RFREGOFFSETMASK, rf_reg18); if (rf_reg_status == false) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", bandwidth, primary_ch_idx)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", bandwidth, primary_ch_idx); return false; } /* Modify RX DFIR parameters */ - phydm_rxdfirpar_by_bw_8822b(p_dm_odm, bandwidth); + phydm_rxdfirpar_by_bw_8822b(dm, bandwidth); /* Toggle IGI to let RF enter RX mode */ - phydm_igi_toggle_8822b(p_dm_odm); + phydm_igi_toggle_8822b(dm); /* Dynamic spur detection by PSD and NBI/CSI mask */ - if (*(p_dm_odm->p_mp_mode)) - phydm_dynamic_spur_det_elimitor(p_dm_odm); + if (*dm->mp_mode) + phydm_dynamic_spur_det_eliminate(dm); /* Modify CCA parameters */ - phydm_ccapar_by_rfe_8822b(p_dm_odm); + phydm_ccapar_by_rfe_8822b(dm); /* Toggle RX path to avoid RX dead zone issue */ - odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, 0x0); - odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, (p_dm_odm->rx_ant_status | (p_dm_odm->rx_ant_status << 4))); + odm_set_bb_reg(dm, 0x808, MASKBYTE0, 0x0); + odm_set_bb_reg(dm, 0x808, MASKBYTE0, (dm->rx_ant_status | (dm->rx_ant_status << 4))); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Success to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "config_phydm_switch_bandwidth_8822b(): Success to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx); return true; } __iram_odm_func__ boolean config_phydm_switch_channel_bw_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 central_ch, u8 primary_ch_idx, - enum odm_bw_e bandwidth + enum channel_width bandwidth ) { - /* Switch band */ - if (config_phydm_switch_band_8822b(p_dm_odm, central_ch) == false) + if (config_phydm_switch_band_8822b(dm, central_ch) == false) return false; /* Switch channel */ - if (config_phydm_switch_channel_8822b(p_dm_odm, central_ch) == false) + if (config_phydm_switch_channel_8822b(dm, central_ch) == false) return false; /* Switch bandwidth */ - if (config_phydm_switch_bandwidth_8822b(p_dm_odm, primary_ch_idx, bandwidth) == false) + if (config_phydm_switch_bandwidth_8822b(dm, primary_ch_idx, bandwidth) == false) return false; return true; @@ -1626,221 +1935,207 @@ config_phydm_switch_channel_bw_8822b( __iram_odm_func__ boolean config_phydm_trx_mode_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_path_e tx_path, - enum odm_rf_path_e rx_path, + struct dm_struct *dm, + enum bb_path tx_path, + enum bb_path rx_path, boolean is_tx2_path ) { - boolean rf_reg_status = true; u32 rf_reg33 = 0; u16 counter = 0; - /* struct PHY_DM_STRUCT* p_dm_odm = (struct PHY_DM_STRUCT*)p_dm_void; */ - /* struct _ADAPTER* p_adapter = p_dm_odm->adapter; */ - /* PMGNT_INFO p_mgnt_info = &(p_adapter->mgnt_info); */ - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b()=====================>\n")); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======>\n", __func__); - if (p_dm_odm->is_disable_phy_api) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): disable PHY API for debug!!\n")); + if (dm->is_disable_phy_api) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "disable PHY API\n"); return true; } - if ((tx_path & (~(ODM_RF_A | ODM_RF_B))) != 0) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong TX setting (TX: 0x%x)\n", tx_path)); - return false; - } - - if ((rx_path & (~(ODM_RF_A | ODM_RF_B))) != 0) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong RX setting (RX: 0x%x)\n", rx_path)); + if (((tx_path & (~BB_PATH_AB)) != 0) || ((rx_path & (~BB_PATH_AB)) != 0)) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Wrong setting: TX:0x%x, RX:0x%x\n", tx_path, rx_path); return false; } - /* RF mode of path-A and path-B */ + /* [mode table] RF mode of path-A and path-B ===========================*/ /* Cannot shut down path-A, beacause synthesizer will be shut down when path-A is in shut down mode */ - if ((tx_path | rx_path) & ODM_RF_A) - odm_set_bb_reg(p_dm_odm, 0xc08, MASKLWORD, 0x3231); + /* 3-wire setting */ + /*0: shutdown, 1: standby, 2: TX, 3: RX */ + + if ((tx_path | rx_path) & BB_PATH_A) + odm_set_bb_reg(dm, 0xc08, MASKLWORD, 0x3231); else - odm_set_bb_reg(p_dm_odm, 0xc08, MASKLWORD, 0x1111); + odm_set_bb_reg(dm, 0xc08, MASKLWORD, 0x1111); - if ((tx_path | rx_path) & ODM_RF_B) - odm_set_bb_reg(p_dm_odm, 0xe08, MASKLWORD, 0x3231); + if ((tx_path | rx_path) & BB_PATH_B) + odm_set_bb_reg(dm, 0xe08, MASKLWORD, 0x3231); else - odm_set_bb_reg(p_dm_odm, 0xe08, MASKLWORD, 0x1111); + odm_set_bb_reg(dm, 0xe08, MASKLWORD, 0x1111); + /*[TX Antenna Setting] ==========================================*/ + /* Set TX antenna by Nsts */ - odm_set_bb_reg(p_dm_odm, 0x93c, (BIT(19) | BIT(18)), 0x3); - odm_set_bb_reg(p_dm_odm, 0x80c, (BIT(29) | BIT(28)), 0x1); + odm_set_bb_reg(dm, 0x93c, (BIT(19) | BIT(18)), 0x3); + odm_set_bb_reg(dm, 0x80c, (BIT(29) | BIT(28)), 0x1); /* Control CCK TX path by 0xa07[7] */ - odm_set_bb_reg(p_dm_odm, 0x80c, BIT(30), 0x1); + odm_set_bb_reg(dm, 0x80c, BIT(30), 0x1); /* TX logic map and TX path en for Nsts = 1, and CCK TX path*/ - if (tx_path & ODM_RF_A) { - odm_set_bb_reg(p_dm_odm, 0x93c, 0xfff00000, 0x001); - odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x8); - } else if (tx_path & ODM_RF_B) { - odm_set_bb_reg(p_dm_odm, 0x93c, 0xfff00000, 0x002); - odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x4); + if (tx_path & BB_PATH_A) { + odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x001); + odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x8); + } else if (tx_path & BB_PATH_B) { + odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x002); + odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x4); } /* TX logic map and TX path en for Nsts = 2*/ - if ((tx_path == ODM_RF_A) || (tx_path == ODM_RF_B)) - odm_set_bb_reg(p_dm_odm, 0x940, 0xfff0, 0x01); + /* Due to LO is stand-by while 1T at path-b in normal driver, so 0x940 is the same setting btw path-A/B*/ + if ((tx_path == BB_PATH_A) || (tx_path == BB_PATH_B)) + odm_set_bb_reg(dm, 0x940, 0xfff0, 0x01); else - odm_set_bb_reg(p_dm_odm, 0x940, 0xfff0, 0x43); + odm_set_bb_reg(dm, 0x940, 0xfff0, 0x43); - /* TX path enable */ - odm_set_bb_reg(p_dm_odm, 0x80c, MASKBYTE0, ((tx_path << 4) | tx_path)); + odm_set_bb_reg(dm, 0x80c, MASKBYTE0, ((tx_path << 4) | tx_path));/* TX path HW block enable */ /* Tx2path for 1ss */ - if (!((tx_path == ODM_RF_A) || (tx_path == ODM_RF_B))) { - if (is_tx2_path || *(p_dm_odm->p_mp_mode)) { - /* 2Tx for OFDM */ - odm_set_bb_reg(p_dm_odm, 0x93c, 0xfff00000, 0x043); - - /* 2Tx for CCK */ - odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0xc); + if (!((tx_path == BB_PATH_A) || (tx_path == BB_PATH_B))) { + if (is_tx2_path || *dm->mp_mode) { + + odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x043); /* 2Tx for OFDM */ + odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0xc); /* 2Tx for CCK */ } } + + /*[RX Antenna Setting] ==========================================*/ - /* Always disable MRC for CCK CCA */ - odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(22), 0x0); - - /* Always disable MRC for CCK barker */ - odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(18), 0x0); + odm_set_bb_reg(dm, 0xa2c, BIT(22), 0x0); /*Disable MRC for CCK CCA */ + odm_set_bb_reg(dm, 0xa2c, BIT(18), 0x0); /*Disable MRC for CCK barker */ /* CCK RX 1st and 2nd path setting*/ - if (rx_path & ODM_RF_A) - odm_set_bb_reg(p_dm_odm, 0xa04, 0x0f000000, 0x0); - else if (rx_path & ODM_RF_B) - odm_set_bb_reg(p_dm_odm, 0xa04, 0x0f000000, 0x5); + if (rx_path & BB_PATH_A) + odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x0); /*00,00*/ + else if (rx_path & BB_PATH_B) + odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x5);/*01,01*/ /* RX path enable */ - odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, ((rx_path << 4) | rx_path)); + odm_set_bb_reg(dm, 0x808, MASKBYTE0, ((rx_path << 4) | rx_path)); - if ((rx_path == ODM_RF_A) || (rx_path == ODM_RF_B)) { + if ((rx_path == BB_PATH_A) || (rx_path == BB_PATH_B)) { /* 1R */ /* Disable MRC for CCA */ - /* odm_set_bb_reg(p_dm_odm, 0xa2c, BIT22, 0x0); */ + /* odm_set_bb_reg(dm, 0xa2c, BIT22, 0x0); */ /* Disable MRC for barker */ - /* odm_set_bb_reg(p_dm_odm, 0xa2c, BIT18, 0x0); */ + /* odm_set_bb_reg(dm, 0xa2c, BIT18, 0x0); */ /* Disable CCK antenna diversity */ - /* odm_set_bb_reg(p_dm_odm, 0xa00, BIT15, 0x0); */ + /* odm_set_bb_reg(dm, 0xa00, BIT15, 0x0); */ /* Disable Antenna weighting */ - odm_set_bb_reg(p_dm_odm, 0x1904, BIT(16), 0x0); - odm_set_bb_reg(p_dm_odm, 0x800, BIT(28), 0x0); - odm_set_bb_reg(p_dm_odm, 0x850, BIT(23), 0x0); + odm_set_bb_reg(dm, 0x1904, BIT(16), 0x0); /*AntWgt_en*/ + odm_set_bb_reg(dm, 0x800, BIT(28), 0x0); /*htstf ant-wgt enable = 0*/ + odm_set_bb_reg(dm, 0x850, BIT(23), 0x0); /*MRC_mode = 'original ZF eqz'*/ } else { /* 2R */ /* Enable MRC for CCA */ - /* odm_set_bb_reg(p_dm_odm, 0xa2c, BIT22, 0x1); */ + /* odm_set_bb_reg(dm, 0xa2c, BIT22, 0x1); */ /* Enable MRC for barker */ - /* odm_set_bb_reg(p_dm_odm, 0xa2c, BIT18, 0x1); */ + /* odm_set_bb_reg(dm, 0xa2c, BIT18, 0x1); */ /* Disable CCK antenna diversity */ - /* odm_set_bb_reg(p_dm_odm, 0xa00, BIT15, 0x0); */ + /* odm_set_bb_reg(dm, 0xa00, BIT15, 0x0); */ /* Enable Antenna weighting */ - odm_set_bb_reg(p_dm_odm, 0x1904, BIT(16), 0x1); - odm_set_bb_reg(p_dm_odm, 0x800, BIT(28), 0x1); - odm_set_bb_reg(p_dm_odm, 0x850, BIT(23), 0x1); + odm_set_bb_reg(dm, 0x1904, BIT(16), 0x1); /*AntWgt_en*/ + odm_set_bb_reg(dm, 0x800, BIT(28), 0x1); /*htstf ant-wgt enable = 1*/ + odm_set_bb_reg(dm, 0x850, BIT(23), 0x1); /*MRC_mode = 'modified ZF eqz'*/ } /* Update TXRX antenna status for PHYDM */ - p_dm_odm->tx_ant_status = (tx_path & 0x3); - p_dm_odm->rx_ant_status = (rx_path & 0x3); + dm->tx_ant_status = (tx_path & 0x3); + dm->rx_ant_status = (rx_path & 0x3); /* MP driver need to support path-B TX\RX */ while (1) { counter++; - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x80000); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK, 0x00001); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x80000); + odm_set_rf_reg(dm, RF_PATH_A, 0x33, RFREGOFFSETMASK, 0x00001); ODM_delay_us(2); - rf_reg33 = config_phydm_read_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK); + rf_reg33 = config_phydm_read_rf_reg_8822b(dm, RF_PATH_A, 0x33, RFREGOFFSETMASK); if ((rf_reg33 == 0x00001) && (config_phydm_read_rf_check_8822b(rf_reg33))) break; else if (counter == 100) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting, because writing RF mode table is fail\n")); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Fail to set TRx mode setting, because writing RF mode table is fail\n"); return false; } } - if (*(p_dm_odm->p_mp_mode) || (*p_dm_odm->p_antenna_test) || (p_dm_odm->normal_rx_path)) { + if (*dm->mp_mode || (*dm->antenna_test) || (dm->normal_rx_path)) { /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080e 0xef 0x00000 suggested by Lucas*/ - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x80000); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK, 0x00001); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x3e, RFREGOFFSETMASK, 0x00034); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x3f, RFREGOFFSETMASK, 0x4080e); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x00000); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): MP mode or Antenna test mode!! support path-B TX and RX\n")); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x80000); + odm_set_rf_reg(dm, RF_PATH_A, 0x33, RFREGOFFSETMASK, 0x00001); + odm_set_rf_reg(dm, RF_PATH_A, 0x3e, RFREGOFFSETMASK, 0x00034); + odm_set_rf_reg(dm, RF_PATH_A, 0x3f, RFREGOFFSETMASK, 0x4080e); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x00000); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "MP mode or Antenna test mode!! support path-B TX and RX\n"); } else { /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080c 0xef 0x00000 */ - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x80000); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK, 0x00001); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x3e, RFREGOFFSETMASK, 0x00034); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0x3f, RFREGOFFSETMASK, 0x4080c); - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x00000); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Normal mode!! Do not support path-B TX and RX\n")); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x80000); + odm_set_rf_reg(dm, RF_PATH_A, 0x33, RFREGOFFSETMASK, 0x00001); + odm_set_rf_reg(dm, RF_PATH_A, 0x3e, RFREGOFFSETMASK, 0x00034); + odm_set_rf_reg(dm, RF_PATH_A, 0x3f, RFREGOFFSETMASK, 0x4080c); + odm_set_rf_reg(dm, RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x00000); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Normal mode!! Do not support path-B TX and RX\n"); } - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x00000); - - if (rf_reg_status == false) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting (TX: 0x%x, RX: 0x%x), because writing RF register is fail\n", tx_path, rx_path)); - return false; - } + odm_set_rf_reg(dm, RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x00000); /* Toggle igi to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */ - phydm_igi_toggle_8822b(p_dm_odm); + phydm_igi_toggle_8822b(dm); /* Modify CCA parameters */ - phydm_ccapar_by_rfe_8822b(p_dm_odm); - phydm_rfe_8822b(p_dm_odm, central_ch_8822b); + phydm_ccapar_by_rfe_8822b(dm); - /* Dynamic spur detection by PSD and NBI/CSI mask */ - if (*(p_dm_odm->p_mp_mode)) - phydm_dynamic_spur_det_elimitor(p_dm_odm); + /* HW Setting depending on RFE type & band */ + phydm_rfe_8822b(dm, central_ch_8822b); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n", tx_path, rx_path)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n", tx_path, rx_path); return true; } __iram_odm_func__ boolean config_phydm_parameter_init_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_parameter_init_e type + struct dm_struct *dm, + enum odm_parameter_init type ) { if (type == ODM_PRE_SETTING) { - odm_set_bb_reg(p_dm_odm, 0x808, (BIT(28) | BIT(29)), 0x0); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Pre setting: disable OFDM and CCK block\n", __func__)); + odm_set_bb_reg(dm, 0x808, (BIT(28) | BIT(29)), 0x0); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: Pre setting: disable OFDM and CCK block\n", __func__); } else if (type == ODM_POST_SETTING) { - odm_set_bb_reg(p_dm_odm, 0x808, (BIT(28) | BIT(29)), 0x3); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Post setting: enable OFDM and CCK block\n", __func__)); + odm_set_bb_reg(dm, 0x808, (BIT(28) | BIT(29)), 0x3); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: Post setting: enable OFDM and CCK block\n", __func__); #if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1) } else if (type == ODM_INIT_FW_SETTING) { u8 h2c_content[4] = {0}; - h2c_content[0] = p_dm_odm->rfe_type; - h2c_content[1] = p_dm_odm->rf_type; - h2c_content[2] = p_dm_odm->cut_version; - h2c_content[3] = (p_dm_odm->tx_ant_status << 4) | p_dm_odm->rx_ant_status; + h2c_content[0] = dm->rfe_type; + h2c_content[1] = dm->rf_type; + h2c_content[2] = dm->cut_version; + h2c_content[3] = (dm->tx_ant_status << 4) | dm->rx_ant_status; - odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_FW_GENERAL_INIT, 4, h2c_content); + odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_GENERAL_INIT, 4, h2c_content); #endif } else { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Wrong type!!\n", __func__)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: Wrong type!!\n", __func__); return false; } diff --git a/hal/phydm/rtl8822b/phydm_hal_api8822b.h b/hal/phydm/rtl8822b/phydm_hal_api8822b.h index 1f74a1c..bb70224 100644 --- a/hal/phydm/rtl8822b/phydm_hal_api8822b.h +++ b/hal/phydm/rtl8822b/phydm_hal_api8822b.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #ifndef __INC_PHYDM_API_H_8822B__ #define __INC_PHYDM_API_H_8822B__ @@ -24,29 +29,50 @@ #define PHY_CONFIG_VERSION_8822B "28.5.34" /*2017.01.18 (HW user guide version: R28, SW user guide version: R05, Modification: R34), remove A cut setting, refine CCK txfilter and OFDM CCA setting by YuChen*/ +#define SMTANT_TMP_RFE_TYPE 100 + #define INVALID_RF_DATA 0xffffffff #define INVALID_TXAGC_DATA 0xff -#define number_of_psd_value 5 -#define number_of_sample 3 -#define number_of_2g_freq_pt 14 -#define number_of_5g_freq_pt 10 +#define PSD_VAL_NUM 5 +#define PSD_SMP_NUM 3 +#define FREQ_PT_2G_NUM 14 +#define FREQ_PT_5G_NUM 10 + +#define number_channel_interferecne 4 #define config_phydm_read_rf_check_8822b(data) (data != INVALID_RF_DATA) #define config_phydm_read_txagc_check_8822b(data) (data != INVALID_TXAGC_DATA) +void +phydm_rxagc_switch_8822b( + struct dm_struct *dm, + boolean enable_rxagc_swich +); + +void +phydm_rfe_8822b_init( + struct dm_struct *dm +); + +boolean +phydm_rfe_8822b( + struct dm_struct *dm, + u8 channel +); + u32 config_phydm_read_rf_reg_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e rf_path, + struct dm_struct *dm, + enum rf_path path, u32 reg_addr, u32 bit_mask ); boolean config_phydm_write_rf_reg_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e rf_path, + struct dm_struct *dm, + enum rf_path path, u32 reg_addr, u32 bit_mask, u32 data @@ -54,63 +80,63 @@ config_phydm_write_rf_reg_8822b( boolean config_phydm_write_txagc_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 power_index, - enum odm_rf_radio_path_e path, + enum rf_path path, u8 hw_rate ); u8 config_phydm_read_txagc_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e path, + struct dm_struct *dm, + enum rf_path path, u8 hw_rate ); void -phydm_dynamic_spur_det_elimitor( - struct PHY_DM_STRUCT *p_dm_odm +phydm_dynamic_spur_det_eliminate( + struct dm_struct *dm ); boolean config_phydm_switch_band_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 central_ch ); boolean config_phydm_switch_channel_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 central_ch ); boolean config_phydm_switch_bandwidth_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 primary_ch_idx, - enum odm_bw_e bandwidth + enum channel_width bandwidth ); boolean config_phydm_switch_channel_bw_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 central_ch, u8 primary_ch_idx, - enum odm_bw_e bandwidth + enum channel_width bandwidth ); boolean config_phydm_trx_mode_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_path_e tx_path, - enum odm_rf_path_e rx_path, + struct dm_struct *dm, + enum bb_path tx_path, + enum bb_path rx_path, boolean is_tx2_path ); boolean config_phydm_parameter_init_8822b( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_parameter_init_e type + struct dm_struct *dm, + enum odm_parameter_init type ); @@ -119,20 +145,20 @@ config_phydm_parameter_init_8822b( boolean phydm_write_txagc_1byte_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 power_index, - enum odm_rf_radio_path_e path, + enum rf_path path, u8 hw_rate ); void phydm_init_hw_info_by_rfe_type_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); s32 phydm_get_condition_number_8822B( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ); /* ======================================================================== */ diff --git a/hal/phydm/rtl8822b/phydm_iqk_8822b.c b/hal/phydm/rtl8822b/phydm_iqk_8822b.c deleted file mode 100644 index 0f33c4a..0000000 --- a/hal/phydm/rtl8822b/phydm_iqk_8822b.c +++ /dev/null @@ -1,1244 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#include "mp_precomp.h" -#include "../phydm_precomp.h" - -#if (RTL8822B_SUPPORT == 1) - - -/*---------------------------Define Local Constant---------------------------*/ - - -/*---------------------------Define Local Constant---------------------------*/ - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -void DoIQK_8822B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - PADAPTER Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - ODM_ResetIQKResult(pDM_Odm); - - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue; - - PHY_IQCalibrate_8822B(pDM_Odm, TRUE); - -} -#else -/*Originally pConfig->DoIQK is hooked PHY_IQCalibrate_8822B, but DoIQK_8822B and PHY_IQCalibrate_8822B have different arguments*/ -void DoIQK_8822B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - BOOLEAN bReCovery = (BOOLEAN) DeltaThermalIndex; - - PHY_IQCalibrate_8822B(pDM_Odm, TRUE); -} -#endif - -VOID -_IQK_Fill_IQK_Report_8822B( - IN PVOID pDM_VOID, - u1Byte channel -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; - u4Byte tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0, tmp4 = 0x0; - u1Byte i; - - for (i = 0; i < SS_8822B; i++) { - tmp1 = tmp1 + ((pIQK_info->IQK_fail_report[channel][i][TX_IQK] & 0x1) << i); - tmp2 = tmp2 + ((pIQK_info->retry_count[channel][i][TX_IQK] & 0x3) << (4+i*2)); - tmp3 = tmp3 + ((pIQK_info->IQK_fail_report[channel][i][RX_IQK] & 0x1) << (i+12)); - tmp4 = tmp4 + ((pIQK_info->retry_count[channel][i][RX_IQK] & 0x3) << (16+i*2)); - } - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008); - ODM_SetBBReg(pDM_Odm, 0x1bf0, 0x00ffffff, tmp1 | tmp2 | tmp3 | tmp4); - - for (i = 0; i < 2; i++) - ODM_Write4Byte(pDM_Odm, 0x1be8+(i*4), (pIQK_info->RXIQK_AGC[channel][(i*2)+1] << 16) | pIQK_info->RXIQK_AGC[channel][i*2]); -} - - -VOID -_IQK_IQK_failReport_8822B( - IN PDM_ODM_T pDM_Odm -) -{ - u4Byte tmp1bf0 = 0x0; - u1Byte i; - - tmp1bf0 = ODM_Read4Byte(pDM_Odm, 0x1bf0); - - for (i = 0; i < 4; i++) { - if (tmp1bf0 & (0x1 << i)) -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] please check S%d TXIQK\n", i)); -#else - panic_printk("[IQK] please check S%d TXIQK\n", i); -#endif - if (tmp1bf0 & (0x1 << (i + 12))) -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] please check S%d RXIQK\n", i)); -#else - panic_printk("[IQK] please check S%d RXIQK\n", i); -#endif - - } -} - - -VOID -_IQK_BackupMacBB_8822B( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MAC_backup, - IN pu4Byte BB_backup, - IN pu4Byte Backup_MAC_REG, - IN pu4Byte Backup_BB_REG - ) -{ - u4Byte i; - for (i = 0; i < MAC_REG_NUM_8822B; i++) - MAC_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_MAC_REG[i]); - - for (i = 0; i < BB_REG_NUM_8822B; i++) - BB_backup[i] = ODM_Read4Byte(pDM_Odm, Backup_BB_REG[i]); - -/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BackupMacBB Success!!!!\n")); */ -} - - -VOID -_IQK_BackupRF_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte RF_backup[][2], - IN pu4Byte Backup_RF_REG - ) -{ - u4Byte i; - - for (i = 0; i < RF_REG_NUM_8822B; i++) { - RF_backup[i][ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bRFRegOffsetMask); - RF_backup[i][ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG[i], bRFRegOffsetMask); - } -/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BackupRF Success!!!!\n")); */ -} - - -VOID -_IQK_AGCbnd_int_8822B( - IN PDM_ODM_T pDM_Odm - ) -{ - /*initialize RX AGC bnd, it must do after bbreset*/ - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008); - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf80a7008); - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8015008); - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008); - /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]init. rx agc bnd\n"));*/ -} - - -VOID -_IQK_BB_Reset_8822B( - IN PDM_ODM_T pDM_Odm - ) -{ - BOOLEAN CCAing = FALSE; - u4Byte count = 0; - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, bRFRegOffsetMask, 0x10000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0, bRFRegOffsetMask, 0x10000); - - while (1) { - ODM_Write4Byte(pDM_Odm, 0x8fc, 0x0); - ODM_SetBBReg(pDM_Odm, 0x198c, 0x7, 0x7); - CCAing = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0xfa0, BIT3); - - if (count > 30) - CCAing = FALSE; - - if (CCAing) { - ODM_delay_ms(1); - count++; - } - else { - ODM_Write1Byte(pDM_Odm, 0x808, 0x0); /*RX ant off*/ - ODM_SetBBReg(pDM_Odm, 0xa04, BIT27|BIT26|BIT25|BIT24, 0x0); /*CCK RX Path off*/ - - /*BBreset*/ - ODM_SetBBReg(pDM_Odm, 0x0, BIT16, 0x0); - ODM_SetBBReg(pDM_Odm, 0x0, BIT16, 0x1); - - if (ODM_GetBBReg(pDM_Odm, 0x660, BIT16)) - ODM_Write4Byte(pDM_Odm, 0x6b4, 0x89000006); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BBreset!!!!\n")); - break; - } - } -} - -VOID -_IQK_AFESetting_8822B( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN Do_IQK - ) -{ - if (Do_IQK) { - ODM_Write4Byte(pDM_Odm, 0xc60, 0x50000000); - ODM_Write4Byte(pDM_Odm, 0xc60, 0x70070040); - ODM_Write4Byte(pDM_Odm, 0xe60, 0x50000000); - ODM_Write4Byte(pDM_Odm, 0xe60, 0x70070040); - - ODM_Write4Byte(pDM_Odm, 0xc58, 0xd8000402); - ODM_Write4Byte(pDM_Odm, 0xc5c, 0xd1000120); - ODM_Write4Byte(pDM_Odm, 0xc6c, 0x00000a15); - ODM_Write4Byte(pDM_Odm, 0xe58, 0xd8000402); - ODM_Write4Byte(pDM_Odm, 0xe5c, 0xd1000120); - ODM_Write4Byte(pDM_Odm, 0xe6c, 0x00000a15); - _IQK_BB_Reset_8822B(pDM_Odm); -/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]AFE setting for IQK mode!!!!\n")); */ - } else { - ODM_Write4Byte(pDM_Odm, 0xc60, 0x50000000); - ODM_Write4Byte(pDM_Odm, 0xc60, 0x70038040); - ODM_Write4Byte(pDM_Odm, 0xe60, 0x50000000); - ODM_Write4Byte(pDM_Odm, 0xe60, 0x70038040); - - ODM_Write4Byte(pDM_Odm, 0xc58, 0xd8020402); - ODM_Write4Byte(pDM_Odm, 0xc5c, 0xde000120); - ODM_Write4Byte(pDM_Odm, 0xc6c, 0x0000122a); - ODM_Write4Byte(pDM_Odm, 0xe58, 0xd8020402); - ODM_Write4Byte(pDM_Odm, 0xe5c, 0xde000120); - ODM_Write4Byte(pDM_Odm, 0xe6c, 0x0000122a); -/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]AFE setting for Normal mode!!!!\n")); */ - } -} - -VOID -_IQK_RestoreMacBB_8822B( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte MAC_backup, - IN pu4Byte BB_backup, - IN pu4Byte Backup_MAC_REG, - IN pu4Byte Backup_BB_REG - ) -{ - u4Byte i; - - for (i = 0; i < MAC_REG_NUM_8822B; i++) - ODM_Write4Byte(pDM_Odm, Backup_MAC_REG[i], MAC_backup[i]); - for (i = 0; i < BB_REG_NUM_8822B; i++) - ODM_Write4Byte(pDM_Odm, Backup_BB_REG[i], BB_backup[i]); -/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RestoreMacBB Success!!!!\n")); */ -} - -VOID -_IQK_RestoreRF_8822B( - IN PDM_ODM_T pDM_Odm, - IN pu4Byte Backup_RF_REG, - IN u4Byte RF_backup[][2] - ) -{ - u4Byte i; - - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, bRFRegOffsetMask, 0x0); - /*0xdf[4]=0*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, RF_backup[0][ODM_RF_PATH_A]&(~BIT4)); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, RF_backup[0][ODM_RF_PATH_B]&(~BIT4)); - - for (i = 1; i < RF_REG_NUM_8822B; i++) { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][ODM_RF_PATH_A]); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][ODM_RF_PATH_B]); - } -/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RestoreRF Success!!!!\n")); */ - -} - - -void -_IQK_backupIQK_8822B( - IN PDM_ODM_T pDM_Odm, - IN u1Byte step - ) -{ - PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; - u1Byte i, j, k, path, idx; - u4Byte tmp; - - if (step == 0x0) { - pIQK_info->IQK_Channel[1] = pIQK_info->IQK_Channel[0]; - for (i = 0; i < 2; i++) { - pIQK_info->LOK_IDAC[1][i] = pIQK_info->LOK_IDAC[0][i]; - pIQK_info->RXIQK_AGC[1][i] = pIQK_info->RXIQK_AGC[0][i]; - for (j = 0; j < 2; j++) { - pIQK_info->IQK_fail_report[1][i][j] = pIQK_info->IQK_fail_report[0][i][j]; - pIQK_info->retry_count[1][i][j] = pIQK_info->retry_count[0][i][j]; - for (k = 0; k < 8; k++) { - pIQK_info->IQK_CFIR_real[1][i][j][k] = pIQK_info->IQK_CFIR_real[0][i][j][k]; - pIQK_info->IQK_CFIR_imag[1][i][j][k] = pIQK_info->IQK_CFIR_imag[0][i][j][k]; - } - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("RXAGC[0][0]=0x%x, RXAGC[0][1]=0x%x\n", pIQK_info->RXIQK_AGC[0][0], pIQK_info->RXIQK_AGC[0][1])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("RXAGC[0][2]=0x%x, RXAGC[0][3]=0x%x\n", pIQK_info->RXIQK_AGC[0][2], pIQK_info->RXIQK_AGC[0][3])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("RXAGC[1][0]=0x%x, RXAGC[1][1]=0x%x\n", pIQK_info->RXIQK_AGC[1][0], pIQK_info->RXIQK_AGC[1][1])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("RXAGC[1][2]=0x%x, RXAGC[1][3]=0x%x\n", pIQK_info->RXIQK_AGC[1][2], pIQK_info->RXIQK_AGC[1][3])); - - - } else { - pIQK_info->IQK_Channel[0] = pIQK_info->RFReg18; - for (path = 0; path < 2; path++) - pIQK_info->LOK_IDAC[0][path] = ODM_GetRFReg(pDM_Odm, path, 0x58, bRFRegOffsetMask); - - for (path = 0; path < 2; path++) { - for (idx = 0; idx < 2; idx++) { - ODM_SetBBReg(pDM_Odm, 0x1b00, bMaskDWord, 0xf8000008 | path << 1); - - if (idx == 0) - ODM_SetBBReg(pDM_Odm, 0x1b0c, BIT13|BIT12, 0x3); - else - ODM_SetBBReg(pDM_Odm, 0x1b0c, BIT13|BIT12, 0x1); - - ODM_SetBBReg(pDM_Odm, 0x1bd4, BIT20|BIT19|BIT18|BIT17|BIT16, 0x10); - - for (i = 0; i < 8; i++) { - ODM_SetBBReg(pDM_Odm, 0x1bd8, bMaskDWord, 0xe0000001+(i*4)); - tmp = ODM_GetBBReg(pDM_Odm, 0x1bfc, bMaskDWord); - pIQK_info->IQK_CFIR_real[0][path][idx][i] = (tmp & 0x0fff0000)>>16; - pIQK_info->IQK_CFIR_imag[0][path][idx][i] = tmp & 0xfff; - } - } - ODM_SetBBReg(pDM_Odm, 0x1bd8, bMaskDWord, 0x0); - ODM_SetBBReg(pDM_Odm, 0x1b0c, BIT13|BIT12, 0x0); - } - } -} - -VOID -_IQK_ReloadIQKsetting_8822B( - IN PDM_ODM_T pDM_Odm, - IN u1Byte channel, - IN u1Byte reload_idx /*1: reload TX, 2: reload LO, TX, RX*/ - ) -{ - PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; - u1Byte i, path, idx; - - for (path = 0; path < 2; path++) { - if (reload_idx == 2) { - ODM_SetRFReg(pDM_Odm, path, 0xdf, BIT4, 0x1); - ODM_SetRFReg(pDM_Odm, path, 0x58, bRFRegOffsetMask, pIQK_info->LOK_IDAC[channel][path]); - } - - for (idx = 0; idx < reload_idx; idx++) { - ODM_SetBBReg(pDM_Odm, 0x1b00, bMaskDWord, 0xf8000008 | path << 1); - - if (idx == 0) - ODM_SetBBReg(pDM_Odm, 0x1b0c, BIT13|BIT12, 0x3); - else - ODM_SetBBReg(pDM_Odm, 0x1b0c, BIT13|BIT12, 0x1); - - ODM_SetBBReg(pDM_Odm, 0x1bd4, BIT20|BIT19|BIT18|BIT17|BIT16, 0x10); - - for (i = 0; i < 8; i++) { - ODM_Write4Byte(pDM_Odm, 0x1bd8, ((0xc0000000 >> idx) + 0x3)+(i*4)+(pIQK_info->IQK_CFIR_real[channel][path][idx][i]<<9)); - ODM_Write4Byte(pDM_Odm, 0x1bd8, ((0xc0000000 >> idx) + 0x1)+(i*4)+(pIQK_info->IQK_CFIR_imag[channel][path][idx][i]<<9)); - } - } - ODM_SetBBReg(pDM_Odm, 0x1bd8, bMaskDWord, 0x0); - ODM_SetBBReg(pDM_Odm, 0x1b0c, BIT13|BIT12, 0x0); - } -} - - -BOOLEAN -_IQK_ReloadIQK_8822B( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN reset - ) -{ - PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; - u1Byte i; - BOOLEAN reload = FALSE; - - if (reset) { - for (i = 0; i < 2; i++) - pIQK_info->IQK_Channel[i] = 0x0; - } else { - pIQK_info->RFReg18 = ODM_GetRFReg(pDM_Odm, 0, 0x18, bRFRegOffsetMask); - - for (i = 0; i < 2; i++) { - if (pIQK_info->RFReg18 == pIQK_info->IQK_Channel[i]) { - _IQK_ReloadIQKsetting_8822B(pDM_Odm, i, 2); - _IQK_Fill_IQK_Report_8822B(pDM_Odm, i); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]reload IQK result before!!!!\n")); - reload = TRUE; - } - } - } - return reload; -} - - -VOID -_IQK_RFESetting_8822B( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN extPAon - ) -{ - if (extPAon) { - /*RFE setting*/ - ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xcb4, 0x00007777); - ODM_Write4Byte(pDM_Odm, 0xcbc, 0x0000083B); - ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77777777); - ODM_Write4Byte(pDM_Odm, 0xeb4, 0x00007777); - ODM_Write4Byte(pDM_Odm, 0xebc, 0x0000083B); - /*ODM_Write4Byte(pDM_Odm, 0x1990, 0x00000c30);*/ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]external PA on!!!!\n")); - } else { - /*RFE setting*/ - ODM_Write4Byte(pDM_Odm, 0xcb0, 0x77171117); - ODM_Write4Byte(pDM_Odm, 0xcb4, 0x00001177); - ODM_Write4Byte(pDM_Odm, 0xcbc, 0x00000404); - ODM_Write4Byte(pDM_Odm, 0xeb0, 0x77171117); - ODM_Write4Byte(pDM_Odm, 0xeb4, 0x00001177); - ODM_Write4Byte(pDM_Odm, 0xebc, 0x00000404); - /*ODM_Write4Byte(pDM_Odm, 0x1990, 0x00000c30);*/ -/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]external PA off!!!!\n"));*/ - } -} - - -VOID -_IQK_ConfigureMACBB_8822B( - IN PDM_ODM_T pDM_Odm - ) -{ - /*MACBB register setting*/ - ODM_Write1Byte(pDM_Odm, 0x522, 0x7f); - ODM_SetBBReg(pDM_Odm, 0x550, BIT11|BIT3, 0x0); - ODM_SetBBReg(pDM_Odm, 0x90c, BIT15, 0x1); /*0x90c[15]=1: dac_buf reset selection*/ - ODM_SetBBReg(pDM_Odm, 0x9a4, BIT31, 0x0); /*0x9a4[31]=0: Select da clock*/ - /*0xc94[0]=1, 0xe94[0]=1: Åýtx±qiqk¥´¥X¨Ó*/ - ODM_SetBBReg(pDM_Odm, 0xc94, BIT0, 0x1); - ODM_SetBBReg(pDM_Odm, 0xe94, BIT0, 0x1); - /* 3-wire off*/ - ODM_Write4Byte(pDM_Odm, 0xc00, 0x00000004); - ODM_Write4Byte(pDM_Odm, 0xe00, 0x00000004); -/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set MACBB setting for IQK!!!!\n"));*/ - -} - -VOID -_IQK_LOKSetting_8822B( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Path - ) -{ - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008 | Path << 1); - ODM_Write4Byte(pDM_Odm, 0x1bcc, 0x9); - ODM_Write1Byte(pDM_Odm, 0x1b23, 0x00); - - switch (*pDM_Odm->pBandType) { - case ODM_BAND_2_4G: - ODM_Write1Byte(pDM_Odm, 0x1b2b, 0x00); - ODM_SetRFReg(pDM_Odm, Path, 0x56, bRFRegOffsetMask, 0x50df2); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0xadc00); - break; - case ODM_BAND_5G: - ODM_Write1Byte(pDM_Odm, 0x1b2b, 0x80); - ODM_SetRFReg(pDM_Odm, Path, 0x56, bRFRegOffsetMask, 0x5086c); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0xa9c00); - break; -} -/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set LOK setting!!!!\n"));*/ -} - - -VOID -_IQK_TXKSetting_8822B( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Path - ) -{ - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008 | Path << 1); - ODM_Write4Byte(pDM_Odm, 0x1bcc, 0x9); - ODM_Write4Byte(pDM_Odm, 0x1b20, 0x01440008); - - if (Path == 0x0) - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf800000a); - else - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008); - ODM_Write4Byte(pDM_Odm, 0x1bcc, 0x3f); - - switch (*pDM_Odm->pBandType) { - case ODM_BAND_2_4G: - ODM_SetRFReg(pDM_Odm, Path, 0x56, bRFRegOffsetMask, 0x50df2); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0xadc00); - ODM_Write1Byte(pDM_Odm, 0x1b2b, 0x00); - break; - case ODM_BAND_5G: - ODM_SetRFReg(pDM_Odm, Path, 0x56, bRFRegOffsetMask, 0x500ef); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0xa9c00); - ODM_Write1Byte(pDM_Odm, 0x1b2b, 0x80); - break; - } -/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set TXK setting!!!!\n"));*/ - -} - -VOID -_IQK_RXKSetting_8822B( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Path - ) -{ - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008 | Path << 1); - - switch (*pDM_Odm->pBandType) { - case ODM_BAND_2_4G: - ODM_Write1Byte(pDM_Odm, 0x1bcc, 0x1b); - ODM_Write1Byte(pDM_Odm, 0x1b2b, 0x00); - ODM_Write4Byte(pDM_Odm, 0x1b20, 0x01450008); - ODM_Write4Byte(pDM_Odm, 0x1b24, 0x01460c88); - ODM_SetRFReg(pDM_Odm, Path, 0x56, bRFRegOffsetMask, 0x510e0); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0xacc00); - break; - case ODM_BAND_5G: - ODM_Write1Byte(pDM_Odm, 0x1bcc, 0x09); - ODM_Write1Byte(pDM_Odm, 0x1b2b, 0x80); - ODM_Write4Byte(pDM_Odm, 0x1b20, 0x00850008); - ODM_Write4Byte(pDM_Odm, 0x1b24, 0x00461448); - ODM_SetRFReg(pDM_Odm, Path, 0x56, bRFRegOffsetMask, 0x510e0); - ODM_SetRFReg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0xacc00); - break; - } -/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set RXK setting!!!!\n"));*/ - -} - - -BOOLEAN -_IQK_CheckCal_8822B( - IN PDM_ODM_T pDM_Odm, - IN u4Byte IQK_CMD - ) -{ - BOOLEAN notready = TRUE, fail = TRUE; - u4Byte delay_count = 0x0; - - while (notready) { - if (ODM_Read4Byte(pDM_Odm, 0x1b00) == (IQK_CMD & 0xffffff0f)) { - fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x1b08, BIT26); - notready = FALSE; - } else { - ODM_delay_ms(1); - delay_count++; - } - - if (delay_count >= 50) { - fail = TRUE; - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]IQK timeout!!!\n")); - break; - } - } - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]delay count = 0x%x!!!\n", delay_count)); - return fail; -} - - -BOOLEAN -_IQK_RXIQK_GainSearchFail_8822B( - IN PDM_ODM_T pDM_Odm, - IN u1Byte Path - ) -{ - u1Byte count = 0x0; - BOOLEAN fail = TRUE; - u4Byte IQK_CMD = 0x0, RFReg0, Reg1bcc, tmp, bb_idx, lna_idx; - - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008 | Path << 1); - Reg1bcc = ODM_GetBBReg(pDM_Odm, 0x1bcc, bMaskDWord); - - while (1) { - IQK_CMD = 0xf8000208 | (1 << (Path + 4)); - - ODM_Write4Byte(pDM_Odm, 0x1b00, IQK_CMD); - ODM_Write4Byte(pDM_Odm, 0x1b00, IQK_CMD+0x1); - - fail = _IQK_CheckCal_8822B(pDM_Odm, IQK_CMD); - - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008 | Path << 1); - ODM_Write4Byte(pDM_Odm, 0x1bcc, Reg1bcc); - - RFReg0 = ODM_GetRFReg(pDM_Odm, Path, 0x0, bRFRegOffsetMask); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]S%d ==> RF0x0 = 0x%x\n", Path, RFReg0)); - - if (((RFReg0 >> 16) == 0x6) && (count < 3)) { - tmp = (RFReg0 & 0x1fe0) >> 5; - lna_idx = tmp >> 5; - bb_idx = tmp & 0x1f; - - if (bb_idx == 0x1) - lna_idx--; - else if (bb_idx == 0xa) - lna_idx++; - else { - fail = FALSE; - break; - } - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008 | Path << 1); - ODM_Write4Byte(pDM_Odm, 0x1b24, (ODM_Read4Byte(pDM_Odm, 0x1b24) & 0xffffe3ff) | (lna_idx << 10)); - } else { - if (count >= 3) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]S%d RXIQK gain search count out!!!\n", Path)); - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]S%d RXIQK gain search fail!!!\n", Path)); - fail = TRUE; - break; - } - count++; - } - return fail; -} - -BOOLEAN -_LOK_One_Shot_8822B( - IN PVOID pDM_VOID, - u1Byte Path -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; - u1Byte delay_count = 0, ii; - BOOLEAN LOK_notready = FALSE; - u4Byte LOK_temp = 0; - u4Byte IQK_CMD = 0x0; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]==========S%d LOK ==========\n", Path)); - - IQK_CMD = 0xf8000008|(1<<(4+Path)); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,("[IQK]LOK_Trigger = 0x%x\n", IQK_CMD)); - - ODM_Write4Byte(pDM_Odm, 0x1b00, IQK_CMD); - ODM_Write4Byte(pDM_Odm, 0x1b00, IQK_CMD+1); - /*LOK: CMD ID = 0 {0xf8000018, 0xf8000028}*/ - /*LOK: CMD ID = 0 {0xf8000019, 0xf8000029}*/ - ODM_delay_ms(LOK_delay_8822B); - - delay_count = 0; - LOK_notready = TRUE; - - while (LOK_notready) { - if (ODM_Read4Byte(pDM_Odm, 0x1b00) == (IQK_CMD & 0xffffff0f)) - LOK_notready = FALSE; - else - LOK_notready = TRUE; - - if (LOK_notready) { - ODM_delay_ms(1); - delay_count++; - } - - if (delay_count >= 50) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]S%d LOK timeout!!!\n", Path)); - break; - } - } - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]S%d ==> delay_count = 0x%d\n", Path, delay_count)); - if (ODM_COMP_CALIBRATION) { - if (!LOK_notready) { - LOK_temp = ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)Path, 0x58, bRFRegOffsetMask); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]0x58 = 0x%x\n", LOK_temp)); - } else { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]==>S%d LOK Fail!!!\n", Path)); - } - } - pIQK_info->LOK_fail[Path] = LOK_notready; - return LOK_notready; -} - -BOOLEAN -_IQK_One_Shot_8822B( - IN PVOID pDM_VOID, - u1Byte Path, - u1Byte idx -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; - u1Byte delay_count = 0; - BOOLEAN notready = TRUE, fail = TRUE, search_fail = TRUE; - u4Byte IQK_CMD = 0x0, tmp; - u2Byte IQK_Apply[2] = {0xc94, 0xe94}; - - if (idx == TX_IQK) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBTXIQK ============\n", Path)); - else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBRXIQK ============\n", Path)); - - if (idx == TX_IQK) { - IQK_CMD = 0xf8000008 | ((*pDM_Odm->pBandWidth + 3) << 8) | (1 << (Path + 4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]TXK_Trigger = 0x%x\n", IQK_CMD)); - /*{0xf8000318, 0xf800032a} ==> 20 WBTXK (CMD = 3)*/ - /*{0xf8000418, 0xf800042a} ==> 40 WBTXK (CMD = 4)*/ - /*{0xf8000518, 0xf800052a} ==> 80 WBTXK (CMD = 5)*/ - } else if (idx == RX_IQK) { -#if 1 - if (!_IQK_RXIQK_GainSearchFail_8822B(pDM_Odm, Path)) { -#endif - search_fail = FALSE; - IQK_CMD = 0xf8000008 | ((*pDM_Odm->pBandWidth + 6) << 8) | (1 << (Path+4)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]RXK_Trigger = 0x%x\n", IQK_CMD)); - /*{0xf8000618, 0xf800062a} ==> 20 WBRXK (CMD = 6)*/ - /*{0xf8000718, 0xf800072a} ==> 40 WBRXK (CMD = 7)*/ - /*{0xf8000818, 0xf800082a} ==> 80 WBRXK (CMD = 8)*/ - } - } - - if ((idx == TX_IQK) || ((idx == RX_IQK) && (!search_fail))) { - ODM_Write4Byte(pDM_Odm, 0x1b00, IQK_CMD); - ODM_Write4Byte(pDM_Odm, 0x1b00, IQK_CMD+0x1); - ODM_delay_ms(WBIQK_delay_8822B); - - while (notready) { - if (ODM_Read4Byte(pDM_Odm, 0x1b00) == (IQK_CMD & 0xffffff0f)) - notready = FALSE; - else - notready = TRUE; - - if (notready) { - ODM_delay_ms(1); - delay_count++; - } else { - fail = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x1b08, BIT26); - break; - } - - if (delay_count >= 50) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]S%d IQK timeout!!!\n", Path)); - break; - } - } - - if (pDM_Odm->DebugComponents && ODM_COMP_CALIBRATION) { - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008 | Path << 1); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]S%d ==> 0x1b00 = 0x%x, 0x1b08 = 0x%x\n", Path, ODM_Read4Byte(pDM_Odm, 0x1b00), ODM_Read4Byte(pDM_Odm, 0x1b08))); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]S%d ==> delay_count = 0x%d\n", Path, delay_count)); - if (idx == RX_IQK) - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]S%d ==> RF0x0 = 0x%x, RF0x56 = 0x%x\n", Path, ODM_GetRFReg(pDM_Odm, Path, 0x0, bRFRegOffsetMask), ODM_GetRFReg(pDM_Odm, Path, 0x56, bRFRegOffsetMask))); - } - - } - - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008 | Path << 1); - - if (!fail) { - if(idx == TX_IQK) - pIQK_info->IQC_Matrix[idx][Path] = ODM_Read4Byte(pDM_Odm, 0x1b38); - else if(idx == RX_IQK) - pIQK_info->IQC_Matrix[idx][Path] = ODM_Read4Byte(pDM_Odm, 0x1b3c); - } - - if (idx == RX_IQK) { - pIQK_info->RXIQK_AGC[0][Path] = ODM_GetRFReg(pDM_Odm, Path, 0x0, bRFRegOffsetMask) >> 4; - - if (pIQK_info->IQK_fail_report[0][Path][TX_IQK] == FALSE) /*TXIQK success in RXIQK*/ - ODM_Write4Byte(pDM_Odm, 0x1b38, pIQK_info->IQC_Matrix[TX_IQK][Path]); - else - ODM_Write4Byte(pDM_Odm, 0x1b38, 0x20000000); - - if (!fail) /*RXIQK success*/ - ODM_SetBBReg(pDM_Odm, IQK_Apply[Path], (BIT11|BIT10), 0x1); - else - ODM_SetBBReg(pDM_Odm, IQK_Apply[Path], (BIT11|BIT10), 0x0); - - } - pIQK_info->IQK_fail_report[0][Path][idx] = fail; - return fail; -} - - -VOID -_IQK_IQKbyPath_8822B( - IN PVOID pDM_VOID -) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; - BOOLEAN KFAIL = TRUE; - u1Byte i; - -/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]IQKstep = 0x%x\n", pDM_Odm->RFCalibrateInfo.IQKstep)); */ -#if 1 - switch (pDM_Odm->RFCalibrateInfo.IQKstep) { - case 1: /*S0 LOK*/ -#if 1 - _IQK_LOKSetting_8822B(pDM_Odm, ODM_RF_PATH_A); - _LOK_One_Shot_8822B(pDM_Odm, ODM_RF_PATH_A); -#endif - pDM_Odm->RFCalibrateInfo.IQKstep++; - break; - case 2: /*S1 LOK*/ -#if 1 - _IQK_LOKSetting_8822B(pDM_Odm, ODM_RF_PATH_B); - _LOK_One_Shot_8822B(pDM_Odm, ODM_RF_PATH_B); -#endif - pDM_Odm->RFCalibrateInfo.IQKstep++; - break; - case 3: /*S0 TXIQK*/ -#if 1 - _IQK_TXKSetting_8822B(pDM_Odm, ODM_RF_PATH_A); - KFAIL = _IQK_One_Shot_8822B(pDM_Odm, ODM_RF_PATH_A, TXIQK); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]KFail = 0x%x\n", KFAIL)); - - if (KFAIL && (pIQK_info->retry_count[0][ODM_RF_PATH_A][TXIQK] < 3)) - pIQK_info->retry_count[0][ODM_RF_PATH_A][TXIQK]++; - else -#endif - pDM_Odm->RFCalibrateInfo.IQKstep++; - break; - case 4: /*S1 TXIQK*/ -#if 1 - _IQK_TXKSetting_8822B(pDM_Odm, ODM_RF_PATH_B); - - KFAIL = _IQK_One_Shot_8822B(pDM_Odm, ODM_RF_PATH_B, TXIQK); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]KFail = 0x%x\n", KFAIL)); - - if (KFAIL && pIQK_info->retry_count[0][ODM_RF_PATH_B][TXIQK] < 3) - pIQK_info->retry_count[0][ODM_RF_PATH_B][TXIQK]++; - else -#endif - pDM_Odm->RFCalibrateInfo.IQKstep++; - break; - case 5: /*S0 RXIQK*/ -#if 1 - _IQK_RXKSetting_8822B(pDM_Odm, ODM_RF_PATH_A); - - KFAIL = _IQK_One_Shot_8822B(pDM_Odm, ODM_RF_PATH_A, RXIQK); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]KFail = 0x%x\n", KFAIL)); - - if (KFAIL && pIQK_info->retry_count[0][ODM_RF_PATH_A][RXIQK] < 3) - pIQK_info->retry_count[0][ODM_RF_PATH_A][RXIQK]++; - else -#endif - pDM_Odm->RFCalibrateInfo.IQKstep++; - break; - case 6: /*S1 RXIQK*/ -#if 1 - _IQK_RXKSetting_8822B(pDM_Odm, ODM_RF_PATH_B); - - KFAIL = _IQK_One_Shot_8822B(pDM_Odm, ODM_RF_PATH_B, RXIQK); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]KFail = 0x%x\n", KFAIL)); - - if (KFAIL && pIQK_info->retry_count[0][ODM_RF_PATH_B][RXIQK] < 3) - pIQK_info->retry_count[0][ODM_RF_PATH_B][RXIQK]++; - else -#endif - pDM_Odm->RFCalibrateInfo.IQKstep++; - - break; - case 7: - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]==========LOK summary ==========\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]LOK0_notready = %d, LOK1_notready = %d\n", - pIQK_info->LOK_fail[ODM_RF_PATH_A], pIQK_info->LOK_fail[ODM_RF_PATH_B])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]==========IQK summary ==========\n")); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]TXIQK0_fail = %d, TXIQK1_fail = %d\n", - pIQK_info->IQK_fail_report[0][ODM_RF_PATH_A][TXIQK], pIQK_info->IQK_fail_report[0][ODM_RF_PATH_B][TXIQK])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]TXIQK0_retry = %d, TXIQK1_retry = %d\n", - pIQK_info->retry_count[0][ODM_RF_PATH_A][TXIQK], pIQK_info->retry_count[0][ODM_RF_PATH_B][TXIQK])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]RXIQK0_fail = %d, RXIQK1_fail = %d\n", - pIQK_info->IQK_fail_report[0][ODM_RF_PATH_A][RXIQK], pIQK_info->IQK_fail_report[0][ODM_RF_PATH_B][RXIQK])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]RXIQK0_retry = %d, RXIQK1_retry = %d\n", - pIQK_info->retry_count[0][ODM_RF_PATH_A][RXIQK], pIQK_info->retry_count[0][ODM_RF_PATH_B][RXIQK])); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]================================\n")); - - for (i = 0; i < 2; i++) { - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008 | i << 1); - ODM_Write4Byte(pDM_Odm, 0x1b2c, 0x7); - } - - pDM_Odm->RFCalibrateInfo.IQKstep++; - break; - } - -#endif - - -} - -VOID -_IQK_StartIQK_8822B( - IN PDM_ODM_T pDM_Odm - ) -{ - u4Byte tmp; - - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008); - ODM_Write4Byte(pDM_Odm, 0x1bb8, 0x00000000); - - /*0xdf:B11 = 1,B4 = 0, B1 = 1*/ -#if 1 - tmp = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask); - tmp = (tmp&(~BIT4))|BIT1|BIT11; - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, tmp); - - tmp = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask); - tmp = (tmp&(~BIT4))|BIT1|BIT11; - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, tmp); -#endif - - /*release 0x56 TXBB*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x65, bRFRegOffsetMask, 0x09000); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x65, bRFRegOffsetMask, 0x09000); - - /* WE_LUT_TX_LOK*/ - if (*pDM_Odm->pBandType == ODM_BAND_5G) { - /*[1:0]: AMODE=1; GMODE=0*/ - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, BIT4, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, BIT1|BIT0, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, BIT4, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x33, BIT1|BIT0, 0x1); - } else { - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, BIT4, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x33, BIT1|BIT0, 0x0); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, BIT4, 0x1); - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x33, BIT1|BIT0, 0x0); - } - - /*GNT_WL = 1*/ - tmp = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask); - tmp = tmp|BIT5|BIT0; - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x1, bRFRegOffsetMask, tmp); - - tmp = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x1, bRFRegOffsetMask); - tmp = tmp|BIT5|BIT0; - ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x1, bRFRegOffsetMask, tmp); - - _IQK_IQKbyPath_8822B(pDM_Odm); - - -} - -VOID -_IQCalibrate_8822B_Init( - IN PVOID pDM_VOID - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; - u1Byte i, j, k, m; - - if (pIQK_info->IQKtimes == 0x0) { - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]=====>PHY_IQCalibrate_8822B_Init\n")); - - for (i = 0; i < SS_8822B; i++) { - for (j = 0; j < 2; j++) { - pIQK_info->LOK_fail[i] = TRUE; - pIQK_info->IQK_fail[j][i] = TRUE; - pIQK_info->IQC_Matrix[j][i] = 0x20000000; - } - } - - for (i = 0; i < 2; i++) { - pIQK_info->IQK_Channel[i] = 0x0; - - for (j = 0; j < SS_8822B; j++) { - pIQK_info->LOK_IDAC[i][j] = 0x0; - pIQK_info->RXIQK_AGC[i][j] = 0x0; - - for (k = 0; k < 2; k++) { - pIQK_info->IQK_fail_report[i][j][k] = TRUE; - pIQK_info->retry_count[i][j][k] = 0x0; - - for (m = 0; m < 8; m++) { - pIQK_info->IQK_CFIR_real[i][j][k][m] = 0x0; - pIQK_info->IQK_CFIR_imag[i][j][k][m] = 0x0; - } - } - } - } - } - pIQK_info->IQKtimes++; -} - - -VOID -phy_IQCalibrate_8822B( - IN PDM_ODM_T pDM_Odm, - IN BOOLEAN reset - ) -{ - - u4Byte MAC_backup[MAC_REG_NUM_8822B], BB_backup[BB_REG_NUM_8822B], RF_backup[RF_REG_NUM_8822B][SS_8822B]; - u4Byte Backup_MAC_REG[MAC_REG_NUM_8822B] = {0x520, 0x550}; - u4Byte Backup_BB_REG[BB_REG_NUM_8822B] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00, 0xeb0, 0xeb4, 0xebc, 0x1990, 0x9a4, 0xa04}; - u4Byte Backup_RF_REG[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1}; - u1Byte i, j; - - PIQK_INFO pIQK_info = &pDM_Odm->IQK_info; - - if (_IQK_ReloadIQK_8822B(pDM_Odm, reset)) - return; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]==========IQK strat!!!!!==========\n")); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]pBandType = %s, BandWidth = %d, ExtPA2G = %d, ExtPA5G = %d\n", (*pDM_Odm->pBandType == ODM_BAND_5G) ? "5G" : "2G", *pDM_Odm->pBandWidth, pDM_Odm->ExtPA, pDM_Odm->ExtPA5G)); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]Interface = %d, CutVersion = %x\n", pDM_Odm->SupportInterface, pDM_Odm->CutVersion)); - - pDM_Odm->RFCalibrateInfo.Kcount = 0; - pDM_Odm->RFCalibrateInfo.IQK_TotalProgressingTime = 0; - pDM_Odm->RFCalibrateInfo.IQKstep = 1; - - for (i = 0; i < 4; i++) { - for (j = 0; j < 2; j++) { - pIQK_info->IQK_fail_report[0][i][j] = TRUE; - pIQK_info->retry_count[0][i][j] = 0x0; - } - } - -#if 1 - _IQK_backupIQK_8822B(pDM_Odm, 0); - _IQK_BackupMacBB_8822B(pDM_Odm, MAC_backup, BB_backup, Backup_MAC_REG, Backup_BB_REG); - _IQK_BackupRF_8822B(pDM_Odm, RF_backup, Backup_RF_REG); - - _IQK_ConfigureMACBB_8822B(pDM_Odm); - _IQK_AFESetting_8822B(pDM_Odm,TRUE); - _IQK_RFESetting_8822B(pDM_Odm, FALSE); - _IQK_AGCbnd_int_8822B(pDM_Odm); - - - - while (1) { - pDM_Odm->RFCalibrateInfo.Kcount++; - - if (!pDM_Odm->mp_mode) - pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime(pDM_Odm); - - _IQK_StartIQK_8822B(pDM_Odm); - - if (!pDM_Odm->mp_mode) { - pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime(pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); - pDM_Odm->RFCalibrateInfo.IQK_TotalProgressingTime += ODM_GetProgressingTime(pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]IQK ProgressingTime = %lld ms\n", pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime)); - } - - if (pDM_Odm->RFCalibrateInfo.IQKstep == 8) - break; - - }; - - _IQK_backupIQK_8822B(pDM_Odm, 1); - _IQK_AFESetting_8822B(pDM_Odm,FALSE); - _IQK_RestoreMacBB_8822B(pDM_Odm, MAC_backup, BB_backup, Backup_MAC_REG, Backup_BB_REG); - _IQK_RestoreRF_8822B(pDM_Odm, Backup_RF_REG, RF_backup); - _IQK_Fill_IQK_Report_8822B(pDM_Odm, 0); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]Total LOK/TXK/RXK count = %d\n", pDM_Odm->RFCalibrateInfo.Kcount - 1)); - - pDM_Odm->RFCalibrateInfo.IQK_TotalProgressingTime += ODM_GetProgressingTime(pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, - ("[IQK]Total IQK ProgressingTime = %lld ms\n", pDM_Odm->RFCalibrateInfo.IQK_TotalProgressingTime)); -#endif - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]==========IQK end!!!!!==========\n")); -} - - -VOID -phy_IQCalibrate_By_FW_8822B( - IN PVOID pDM_VOID, - IN u1Byte clear - ) -{ -} - - -/*IQK version:v2.8 , NCTL v0.5*/ -/*1. backup last two channel IQK result*/ -/*2. IQK report at 0x1bf0, 0x1be8, 0x1bec*/ -/*3. IQK fail report for AP*/ -/*4. modify BB reset procedure*/ -/*5. RXIQK auto gain search*/ -VOID -PHY_IQCalibrate_8822B( - IN PVOID pDM_VOID, - IN BOOLEAN clear - ) -{ - PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; - - u4Byte counter = 0x0; - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) - PADAPTER pAdapter = pDM_Odm->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - #if (MP_DRIVER == 1) - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); - #else - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif - #endif - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - if (ODM_CheckPowerStatus(pAdapter) == FALSE) - return; - #endif - - #if MP_DRIVER == 1 - if( pMptCtx->bSingleTone || pMptCtx->bCarrierSuppression ) - return; - #endif - -#endif - - pDM_Odm->IQKFWOffload = 0; - -/*FW IQK*/ - if (pDM_Odm->IQKFWOffload) { - if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress) { - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - - pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime(pDM_Odm); - - ODM_Write4Byte(pDM_Odm, 0x1b00, 0xf8000008); - ODM_SetBBReg(pDM_Odm, 0x1bf0, 0xff000000, 0xff); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]0x1bf0 = 0x%x\n", ODM_Read4Byte(pDM_Odm, 0x1bf0))); - - phy_IQCalibrate_By_FW_8822B(pDM_Odm, clear); - - while (1) { - if (((ODM_Read4Byte(pDM_Odm, 0x1bf0) >> 24) == 0x7f) || (counter > 300)) - break; - - counter++; - ODM_delay_ms(1); - }; - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, - ("[IQK]counter = %d\n", counter)); - - pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime(pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); - - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK ProgressingTime = %lld ms\n", pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime)); - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - } else - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); - - } - else { - - _IQCalibrate_8822B_Init(pDM_VOID); - - if (!pDM_Odm->RFCalibrateInfo.bIQKInProgress) { - - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - if (pDM_Odm->mp_mode) - pDM_Odm->RFCalibrateInfo.IQK_StartTime = ODM_GetCurrentTime(pDM_Odm); - - #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - phy_IQCalibrate_8822B(pDM_Odm, clear); - /*DBG_871X("%s,%d, do IQK %u ms\n", __func__, __LINE__, rtw_get_passing_time_ms(time_iqk));*/ - #else - phy_IQCalibrate_8822B(pDM_Odm, clear); - #endif - if (pDM_Odm->mp_mode) { - pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime(pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK ProgressingTime = %lld ms\n", pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime)); - } - ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; - ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK); - } - else{ - ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]== Return the IQK CMD, because the IQK in Progress ==\n")); - } - -} - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - _IQK_IQK_failReport_8822B(pDM_Odm); -#endif - -} - -#endif - - diff --git a/hal/phydm/rtl8822b/phydm_iqk_8822b.h b/hal/phydm/rtl8822b/phydm_iqk_8822b.h deleted file mode 100644 index df955db..0000000 --- a/hal/phydm/rtl8822b/phydm_iqk_8822b.h +++ /dev/null @@ -1,74 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __PHYDM_IQK_8822B_H__ -#define __PHYDM_IQK_8822B_H__ - -#if (RTL8822B_SUPPORT == 1) - - -/*--------------------------Define Parameters-------------------------------*/ -#define MAC_REG_NUM_8822B 2 -#define BB_REG_NUM_8822B 13 -#define RF_REG_NUM_8822B 5 - - -#define LOK_delay_8822B 1 -#define IQK_delay_8822B 1 -#define WBIQK_delay_8822B 1 - -#define TXIQK 0 -#define RXIQK 1 -#define SS_8822B 2 - -/*---------------------------End Define Parameters-------------------------------*/ - - -#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) -VOID -DoIQK_8822B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -#else -VOID -DoIQK_8822B( - PVOID pDM_VOID, - u1Byte DeltaThermalIndex, - u1Byte ThermalValue, - u1Byte Threshold - ); -#endif - -VOID -PHY_IQCalibrate_8822B( - IN PVOID pDM_VOID, - IN BOOLEAN clear - ); - -#else /* (RTL8822B_SUPPORT == 0)*/ - -#define PHY_IQCalibrate_8822B(_pDM_VOID, clear) - -#endif /* RTL8822B_SUPPORT */ - - #endif /* #ifndef __PHYDM_IQK_8822B_H__*/ - diff --git a/hal/phydm/rtl8822b/phydm_regconfig8822b.c b/hal/phydm/rtl8822b/phydm_regconfig8822b.c index 7a06ebf..e530fe7 100644 --- a/hal/phydm/rtl8822b/phydm_regconfig8822b.c +++ b/hal/phydm/rtl8822b/phydm_regconfig8822b.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #include "mp_precomp.h" #include "../phydm_precomp.h" @@ -25,44 +30,44 @@ void odm_config_rf_reg_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u32 data, - enum odm_rf_radio_path_e RF_PATH, + enum rf_path rf_path, u32 reg_addr ) { - if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { if (addr == 0xffe) - phydm_set_reg_by_fw(p_dm_odm, + phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_MS, reg_addr, data, RFREGOFFSETMASK, - RF_PATH, + rf_path, 50); else if (addr == 0xfe) - phydm_set_reg_by_fw(p_dm_odm, + phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_US, reg_addr, data, RFREGOFFSETMASK, - RF_PATH, + rf_path, 100); else { - phydm_set_reg_by_fw(p_dm_odm, + phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_RF_W, reg_addr, data, RFREGOFFSETMASK, - RF_PATH, + rf_path, 0); - phydm_set_reg_by_fw(p_dm_odm, + phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_US, reg_addr, data, RFREGOFFSETMASK, - RF_PATH, + rf_path, 1); } } else { @@ -79,7 +84,7 @@ odm_config_rf_reg_8822b( ODM_delay_us(100); #endif } else { - odm_set_rf_reg(p_dm_odm, RF_PATH, reg_addr, RFREGOFFSETMASK, data); + odm_set_rf_reg(dm, rf_path, reg_addr, RFREGOFFSETMASK, data); /* Add 1us delay between BB/RF register setting. */ ODM_delay_us(1); @@ -89,7 +94,7 @@ odm_config_rf_reg_8822b( void odm_config_rf_radio_a_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u32 data ) @@ -97,14 +102,14 @@ odm_config_rf_radio_a_8822b( u32 content = 0x1000; /* RF_Content: radioa_txt */ u32 maskfor_phy_set = (u32)(content & 0xE000); - odm_config_rf_reg_8822b(p_dm_odm, addr, data, ODM_RF_PATH_A, addr | maskfor_phy_set); + odm_config_rf_reg_8822b(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", addr, data)); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_rf: [RadioA] %08X %08X\n", addr, data); } void odm_config_rf_radio_b_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u32 data ) @@ -112,39 +117,39 @@ odm_config_rf_radio_b_8822b( u32 content = 0x1001; /* RF_Content: radiob_txt */ u32 maskfor_phy_set = (u32)(content & 0xE000); - odm_config_rf_reg_8822b(p_dm_odm, addr, data, ODM_RF_PATH_B, addr | maskfor_phy_set); + odm_config_rf_reg_8822b(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n", addr, data)); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_rf: [RadioB] %08X %08X\n", addr, data); } void odm_config_mac_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u8 data ) { - if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) - phydm_set_reg_by_fw(p_dm_odm, + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) + phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_MAC_W8, addr, data, 0, - 0, + (enum rf_path)0, 0); else - odm_write_1byte(p_dm_odm, addr, data); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> config_mac: [MAC_REG] %08X %08X\n", addr, data)); + odm_write_1byte(dm, addr, data); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_mac: [MAC_REG] %08X %08X\n", addr, data); } void odm_update_agc_big_jump_lmt_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u32 data ) { - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct phydm_dig_struct *dig_tab = &dm->dm_dig_table; u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24); u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16); u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8); @@ -154,48 +159,48 @@ odm_update_agc_big_jump_lmt_8822b( return; /*dbg_print("data = 0x%x, rf_gain_idx = 0x%x, bb_gain_idx = 0x%x, agc_table_idx = 0x%x\n", data, rf_gain_idx, bb_gain_idx, agc_table_idx);*/ - /*dbg_print("rf_gain_idx = 0x%x, p_dm_dig_table->rf_gain_idx = 0x%x\n", rf_gain_idx, p_dm_dig_table->rf_gain_idx);*/ + /*dbg_print("rf_gain_idx = 0x%x, dig_tab->rf_gain_idx = 0x%x\n", rf_gain_idx, dig_tab->rf_gain_idx);*/ if (bb_gain_idx > 0x3c) { - if ((rf_gain_idx == p_dm_dig_table->rf_gain_idx) && (is_limit == false)) { + if ((rf_gain_idx == dig_tab->rf_gain_idx) && !is_limit) { is_limit = true; - p_dm_dig_table->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n", agc_table_idx, p_dm_dig_table->big_jump_lmt[agc_table_idx])); + dig_tab->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2; + PHYDM_DBG(dm, DBG_DIG, "===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n", agc_table_idx, dig_tab->big_jump_lmt[agc_table_idx]); } } else is_limit = false; - p_dm_dig_table->rf_gain_idx = rf_gain_idx; + dig_tab->rf_gain_idx = rf_gain_idx; } void odm_config_bb_agc_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u32 bitmask, u32 data ) { - odm_update_agc_big_jump_lmt_8822b(p_dm_odm, addr, data); + odm_update_agc_big_jump_lmt_8822b(dm, addr, data); - if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) - phydm_set_reg_by_fw(p_dm_odm, + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) + phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_BB_W32, addr, data, bitmask, - 0, + (enum rf_path)0, 0); else - odm_set_bb_reg(p_dm_odm, addr, bitmask, data); + odm_set_bb_reg(dm, addr, bitmask, data); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data)); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [AGC_TAB] %08X %08X\n", addr, data); } void odm_config_bb_phy_reg_pg_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 band, u32 rf_path, u32 tx_num, @@ -212,24 +217,24 @@ odm_config_bb_phy_reg_pg_8822b( #endif } else { #if (DM_ODM_SUPPORT_TYPE & ODM_CE) - phy_store_tx_power_by_rate(p_dm_odm->adapter, band, rf_path, tx_num, addr, bitmask, data); + phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PHY_StoreTxPowerByRate(p_dm_odm->adapter, band, rf_path, tx_num, addr, bitmask, data); + PHY_StoreTxPowerByRate((PADAPTER)dm->adapter, band, rf_path, tx_num, addr, bitmask, data); #endif } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data)); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data); } void odm_config_bb_phy_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u32 bitmask, u32 data ) { - if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { u32 delay_time = 0; if (addr >= 0xf9 && addr <= 0xfe) { @@ -241,28 +246,28 @@ odm_config_bb_phy_8822b( delay_time = 1; if (addr >= 0xfc && addr <=0xfe) - phydm_set_reg_by_fw(p_dm_odm, + phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_MS, addr, data, bitmask, - 0, + (enum rf_path)0, delay_time); else - phydm_set_reg_by_fw(p_dm_odm, + phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_US, addr, data, bitmask, - 0, + (enum rf_path)0, delay_time); } else - phydm_set_reg_by_fw(p_dm_odm, + phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_BB_W32, addr, data, bitmask, - 0, + (enum rf_path)0, 0); } else { if (addr == 0xfe) @@ -282,15 +287,15 @@ odm_config_bb_phy_8822b( else if (addr == 0xf9) ODM_delay_us(1); else - odm_set_bb_reg(p_dm_odm, addr, bitmask, data); + odm_set_bb_reg(dm, addr, bitmask, data); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> config_bb: [PHY_REG] %08X %08X\n", addr, data)); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [PHY_REG] %08X %08X\n", addr, data); } void odm_config_bb_txpwr_lmt_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 *regulation, u8 *band, u8 *bandwidth, @@ -301,10 +306,10 @@ odm_config_bb_txpwr_lmt_8822b( ) { #if (DM_ODM_SUPPORT_TYPE & ODM_CE) - phy_set_tx_power_limit(p_dm_odm, regulation, band, + phy_set_tx_power_limit(dm, regulation, band, bandwidth, rate_section, rf_path, channel, power_limit); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PHY_SetTxPowerLimit(p_dm_odm, regulation, band, + PHY_SetTxPowerLimit(dm, regulation, band, bandwidth, rate_section, rf_path, channel, power_limit); #endif } diff --git a/hal/phydm/rtl8822b/phydm_regconfig8822b.h b/hal/phydm/rtl8822b/phydm_regconfig8822b.h index 0b9ef68..3d8c648 100644 --- a/hal/phydm/rtl8822b/phydm_regconfig8822b.h +++ b/hal/phydm/rtl8822b/phydm_regconfig8822b.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #ifndef __INC_ODM_REGCONFIG_H_8822B #define __INC_ODM_REGCONFIG_H_8822B @@ -24,44 +29,44 @@ void odm_config_rf_reg_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u32 data, - enum odm_rf_radio_path_e RF_PATH, + enum rf_path rf_path, u32 reg_addr ); void odm_config_rf_radio_a_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u32 data ); void odm_config_rf_radio_b_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u32 data ); void odm_config_mac_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u8 data ); void odm_update_agc_big_jump_lmt_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u32 data ); void odm_config_bb_agc_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u32 bitmask, u32 data @@ -69,7 +74,7 @@ odm_config_bb_agc_8822b( void odm_config_bb_phy_reg_pg_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 band, u32 rf_path, u32 tx_num, @@ -80,7 +85,7 @@ odm_config_bb_phy_reg_pg_8822b( void odm_config_bb_phy_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u32 addr, u32 bitmask, u32 data @@ -88,7 +93,7 @@ odm_config_bb_phy_8822b( void odm_config_bb_txpwr_lmt_8822b( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 *regulation, u8 *band, u8 *bandwidth, diff --git a/hal/phydm/rtl8822b/phydm_rtl8822b.c b/hal/phydm/rtl8822b/phydm_rtl8822b.c index 85c3c25..084286f 100644 --- a/hal/phydm/rtl8822b/phydm_rtl8822b.c +++ b/hal/phydm/rtl8822b/phydm_rtl8822b.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,22 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ - -#if 0 - /* ============================================================ - * include files - * ============================================================ */ -#endif - + * Larry Finger + * + *****************************************************************************/ #include "mp_precomp.h" #include "../phydm_precomp.h" @@ -32,234 +30,218 @@ void phydm_dynamic_switch_htstf_mumimo_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - s32 sig_power; - u32 value32; - u8 pwdb; - - value32 = odm_get_bb_reg(p_dm_odm, 0xF90, MASKDWORD); - pwdb = (u8)((value32 & MASKBYTE1) >> 8); - pwdb = pwdb >> 1; - sig_power = -110 + pwdb; + u8 rssi_l2h = 40, rssi_h2l = 35; /*if Pin > -60dBm, enable HT-STF gain controller, otherwise, if rssi < -65dBm, disable the controller*/ - if (sig_power >= -60) - odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(17), 0x1); - else if (sig_power < -65) - odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(17), 0x0); + if (dm->rssi_min >= rssi_l2h) + odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x1); + else if (dm->rssi_min < rssi_h2l) + odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x0); } void phydm_dynamic_parameters_ota( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - s32 sig_power; - u32 value32, bktreg, bktreg1, bktreg2, bktreg3; - u8 pwdb; - - value32 = odm_get_bb_reg(p_dm_odm, 0xF90, MASKDWORD); - pwdb = (u8)((value32 & MASKBYTE1) >> 8); - pwdb = pwdb >> 1; - sig_power = -110 + pwdb; - - bktreg = odm_get_bb_reg(p_dm_odm, 0x98c, MASKDWORD); - bktreg1 = odm_get_bb_reg(p_dm_odm, 0x818, MASKDWORD); - bktreg2 = odm_get_bb_reg(p_dm_odm, 0x98c, MASKDWORD); - bktreg3 = odm_get_bb_reg(p_dm_odm, 0x818, MASKDWORD); - - if ((*p_dm_odm->p_channel <= 14) && (*p_dm_odm->p_band_width == ODM_BW20M)) { - if (sig_power >= -60) { - odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(17), 0x1); - odm_set_bb_reg(p_dm_odm, 0x98c, 0x7fc0000, 0x0); - odm_set_bb_reg(p_dm_odm, 0x818, 0x7000000, 0x1); - odm_set_bb_reg(p_dm_odm, 0xc04, BIT(18), 0x1); - odm_set_bb_reg(p_dm_odm, 0xe04, BIT(18), 0x1); - if (p_dm_odm->p_advance_ota & BIT(1)) { - odm_set_bb_reg(p_dm_odm, 0x19d8, MASKDWORD, 0x444); - odm_set_bb_reg(p_dm_odm, 0x19d4, MASKDWORD, 0x4444aaaa); - } else if (p_dm_odm->p_advance_ota & BIT(2)) { - odm_set_bb_reg(p_dm_odm, 0x19d8, MASKDWORD, 0x444); - odm_set_bb_reg(p_dm_odm, 0x19d4, MASKDWORD, 0x444444aa); + u8 rssi_l2h = 40, rssi_h2l = 35; + + if ((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_20)) { + if (dm->rssi_min >= rssi_l2h) { + /*if (dm->bhtstfdisabled == false)*/ + odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x1); + + odm_set_bb_reg(dm, 0x98c, 0x7fc0000, 0x0); + odm_set_bb_reg(dm, 0x818, 0x7000000, 0x1); + odm_set_bb_reg(dm, 0xc04, BIT(18), 0x0); + odm_set_bb_reg(dm, 0xe04, BIT(18), 0x0); + if (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_A) { + odm_set_bb_reg(dm, 0x19d8, MASKDWORD, 0x444); + odm_set_bb_reg(dm, 0x19d4, MASKDWORD, 0x4444aaaa); + } else if (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_B) { + odm_set_bb_reg(dm, 0x19d8, MASKDWORD, 0x444); + odm_set_bb_reg(dm, 0x19d4, MASKDWORD, 0x444444aa); } - } else if (sig_power < -65) { - odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(17), 0x0); - odm_set_bb_reg(p_dm_odm, 0x98c, MASKDWORD, 0x43440000); - odm_set_bb_reg(p_dm_odm, 0x818, 0x7000000, 0x4); - odm_set_bb_reg(p_dm_odm, 0xc04, (BIT(18)|BIT(21)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xe04, (BIT(18)|BIT(21)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x19d8, MASKDWORD, 0xaaa); - odm_set_bb_reg(p_dm_odm, 0x19d4, MASKDWORD, 0xaaaaaaaa); + } else if (dm->rssi_min < rssi_h2l) { + /*if (dm->bhtstfdisabled == true)*/ + odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x0); + + odm_set_bb_reg(dm, 0x98c, MASKDWORD, 0x43440000); + odm_set_bb_reg(dm, 0x818, 0x7000000, 0x4); + odm_set_bb_reg(dm, 0xc04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(dm, 0xe04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(dm, 0x19d8, MASKDWORD, 0xaaa); + odm_set_bb_reg(dm, 0x19d4, MASKDWORD, 0xaaaaaaaa); } } else { - //odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(17), 0x0); - odm_set_bb_reg(p_dm_odm, 0x98c, MASKDWORD, 0x43440000); - odm_set_bb_reg(p_dm_odm, 0x818, 0x7000000, 0x4); - odm_set_bb_reg(p_dm_odm, 0xc04, (BIT(18)|BIT(21)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xe04, (BIT(18)|BIT(21)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x19d8, MASKDWORD, 0xaaa); - odm_set_bb_reg(p_dm_odm, 0x19d4, MASKDWORD, 0xaaaaaaaa); + //odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x0); + odm_set_bb_reg(dm, 0x98c, MASKDWORD, 0x43440000); + odm_set_bb_reg(dm, 0x818, 0x7000000, 0x4); + odm_set_bb_reg(dm, 0xc04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(dm, 0xe04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(dm, 0x19d8, MASKDWORD, 0xaaa); + odm_set_bb_reg(dm, 0x19d4, MASKDWORD, 0xaaaaaaaa); } } - static void -_setTxACaliValue( - struct PHY_DM_STRUCT *p_dm_odm, - u8 eRFPath, +_set_tx_a_cali_value( + struct dm_struct *dm, + enum rf_path rf_path, u8 offset, - u8 TxABiaOffset + u8 tx_a_bias_offset ) { - u32 modiTxAValue = 0; - u8 tmp1Byte = 0; - boolean bMinus = false; - u8 compValue = 0; + u32 modi_tx_a_value = 0; + u8 tmp1_byte = 0; + boolean is_minus = false; + u8 comp_value = 0; switch (offset) { case 0x0: - odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X10124); + odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10124); break; case 0x1: - odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X10524); + odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10524); break; case 0x2: - odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X10924); + odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10924); break; case 0x3: - odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X10D24); + odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10D24); break; case 0x4: - odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X30164); + odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30164); break; case 0x5: - odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X30564); + odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30564); break; case 0x6: - odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X30964); + odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30964); break; case 0x7: - odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X30D64); + odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30D64); break; case 0x8: - odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X50195); + odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50195); break; case 0x9: - odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X50595); + odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50595); break; case 0xa: - odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X50995); + odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50995); break; case 0xb: - odm_set_rf_reg(p_dm_odm, eRFPath, 0x18, 0xFFFFF, 0X50D95); + odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50D95); break; default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Invalid TxA band offset...\n")); + PHYDM_DBG(dm, ODM_COMP_API, "Invalid TxA band offset...\n"); return; break; } /* Get TxA value */ - modiTxAValue = odm_get_rf_reg(p_dm_odm, eRFPath, 0x61, 0xFFFFF); - tmp1Byte = (u8)modiTxAValue&(BIT(3)|BIT(2)|BIT(1)|BIT(0)); + modi_tx_a_value = odm_get_rf_reg(dm, rf_path, 0x61, 0xFFFFF); + tmp1_byte = (u8)modi_tx_a_value&(BIT(3)|BIT(2)|BIT(1)|BIT(0)); /* check how much need to calibration */ - switch (TxABiaOffset) { + switch (tx_a_bias_offset) { case 0xF6: - bMinus = true; - compValue = 3; + is_minus = true; + comp_value = 3; break; case 0xF4: - bMinus = true; - compValue = 2; + is_minus = true; + comp_value = 2; break; case 0xF2: - bMinus = true; - compValue = 1; + is_minus = true; + comp_value = 1; break; case 0xF3: - bMinus = false; - compValue = 1; + is_minus = false; + comp_value = 1; break; case 0xF5: - bMinus = false; - compValue = 2; + is_minus = false; + comp_value = 2; break; case 0xF7: - bMinus = false; - compValue = 3; + is_minus = false; + comp_value = 3; break; case 0xF9: - bMinus = false; - compValue = 4; + is_minus = false; + comp_value = 4; break; /* do nothing case */ case 0xF0: default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("No need to do TxA bias current calibration\n")); + PHYDM_DBG(dm, ODM_COMP_API, "No need to do TxA bias current calibration\n"); return; break; } /* calc correct value to calibrate */ - if (bMinus) { - if (tmp1Byte >= compValue) { - tmp1Byte -= compValue; - //modiTxAValue += tmp1Byte; + if (is_minus) { + if (tmp1_byte >= comp_value) { + tmp1_byte -= comp_value; + //modi_tx_a_value += tmp1_byte; } else { - tmp1Byte = 0; + tmp1_byte = 0; } } else { - tmp1Byte += compValue; - if (tmp1Byte >= 7) { - tmp1Byte = 7; + tmp1_byte += comp_value; + if (tmp1_byte >= 7) { + tmp1_byte = 7; } } /* Write back to RF reg */ - odm_set_rf_reg(p_dm_odm, eRFPath, 0x30, 0xFFFF, (offset<<12|(modiTxAValue&0xFF0)|tmp1Byte)); + odm_set_rf_reg(dm, rf_path, 0x30, 0xFFFF, (offset<<12|(modi_tx_a_value&0xFF0)|tmp1_byte)); } static void -_txaBiasCali4eachPath( - struct PHY_DM_STRUCT *p_dm_odm, - u8 eRFPath, - u8 efuseValue +_txa_bias_cali_4_each_path( + struct dm_struct *dm, + u8 rf_path, + u8 efuse_value ) { /* switch on set TxA bias */ - odm_set_rf_reg(p_dm_odm, eRFPath, 0xEF, 0xFFFFF, 0x200); + odm_set_rf_reg(dm, rf_path, 0xEF, 0xFFFFF, 0x200); /* Set 12 sets of TxA value */ - _setTxACaliValue(p_dm_odm, eRFPath, 0x0, efuseValue); - _setTxACaliValue(p_dm_odm, eRFPath, 0x1, efuseValue); - _setTxACaliValue(p_dm_odm, eRFPath, 0x2, efuseValue); - _setTxACaliValue(p_dm_odm, eRFPath, 0x3, efuseValue); - _setTxACaliValue(p_dm_odm, eRFPath, 0x4, efuseValue); - _setTxACaliValue(p_dm_odm, eRFPath, 0x5, efuseValue); - _setTxACaliValue(p_dm_odm, eRFPath, 0x6, efuseValue); - _setTxACaliValue(p_dm_odm, eRFPath, 0x7, efuseValue); - _setTxACaliValue(p_dm_odm, eRFPath, 0x8, efuseValue); - _setTxACaliValue(p_dm_odm, eRFPath, 0x9, efuseValue); - _setTxACaliValue(p_dm_odm, eRFPath, 0xa, efuseValue); - _setTxACaliValue(p_dm_odm, eRFPath, 0xb, efuseValue); + _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x0, efuse_value); + _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x1, efuse_value); + _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x2, efuse_value); + _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x3, efuse_value); + _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x4, efuse_value); + _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x5, efuse_value); + _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x6, efuse_value); + _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x7, efuse_value); + _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x8, efuse_value); + _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x9, efuse_value); + _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0xa, efuse_value); + _set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0xb, efuse_value); // switch off set TxA bias - odm_set_rf_reg(p_dm_odm, eRFPath, 0xEF, 0xFFFFF, 0x0); + odm_set_rf_reg(dm, rf_path, 0xEF, 0xFFFFF, 0x0); } /* for 8822B PCIE D-cut patch only */ @@ -267,156 +249,267 @@ _txaBiasCali4eachPath( void phydm_txcurrentcalibration( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u8 efuse0x3D8, efuse0x3D7; - u32 origRF0x18PathA = 0, origRF0x18PathB = 0; + u32 orig_rf0x18_path_a = 0, orig_rf0x18_path_b = 0; - if (!(p_dm_odm->support_ic_type & ODM_RTL8822B)) + if (!(dm->support_ic_type & ODM_RTL8822B)) return; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("8822b 5g tx current calibration 0x3d7=0x%X 0x3d8=0x%X\n", p_dm_odm->efuse0x3d7, p_dm_odm->efuse0x3d8)); + PHYDM_DBG(dm, ODM_COMP_MP, "8822b 5g tx current calibration 0x3d7=0x%X 0x3d8=0x%X\n", dm->efuse0x3d7, dm->efuse0x3d8); /* save original 0x18 value */ - origRF0x18PathA = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xFFFFF); - origRF0x18PathB = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x18, 0xFFFFF); + orig_rf0x18_path_a = odm_get_rf_reg(dm, RF_PATH_A, 0x18, 0xFFFFF); + orig_rf0x18_path_b = odm_get_rf_reg(dm, RF_PATH_B, 0x18, 0xFFFFF); /* define efuse content */ - efuse0x3D8 = p_dm_odm->efuse0x3d8; - efuse0x3D7 = p_dm_odm->efuse0x3d7; + efuse0x3D8 = dm->efuse0x3d8; + efuse0x3D7 = dm->efuse0x3d7; /* check efuse content to judge whether need to calibration or not */ if (0xFF == efuse0x3D7) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("efuse content 0x3D7 == 0xFF, No need to do TxA cali\n")); + PHYDM_DBG(dm, ODM_COMP_MP, "efuse content 0x3D7 == 0xFF, No need to do TxA cali\n"); return; } /* write RF register for calibration */ - _txaBiasCali4eachPath(p_dm_odm, ODM_RF_PATH_A, efuse0x3D7); - _txaBiasCali4eachPath(p_dm_odm, ODM_RF_PATH_B, efuse0x3D8); + _txa_bias_cali_4_each_path(dm, RF_PATH_A, efuse0x3D7); + _txa_bias_cali_4_each_path(dm, RF_PATH_B, efuse0x3D8); /* restore original 0x18 value */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xFFFFF, origRF0x18PathA); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x18, 0xFFFFF, origRF0x18PathB); + odm_set_rf_reg(dm, RF_PATH_A, 0x18, 0xFFFFF, orig_rf0x18_path_a); + odm_set_rf_reg(dm, RF_PATH_B, 0x18, 0xFFFFF, orig_rf0x18_path_b); +} + +void +phydm_1rcca_setting( + struct dm_struct *dm, + boolean enable_1rcca +) +{ + u32 reg_32; + + reg_32 = odm_get_bb_reg(dm, 0xa04, 0x0f000000); + + /* Enable or disable 1RCCA setting accrodding to the control from driver */ + if (enable_1rcca == true) { + if (reg_32 == 0x0) { + odm_set_bb_reg(dm, 0x808, MASKBYTE0, 0x13); /* CCK path-a */ + } else if (reg_32 == 0x5) { + odm_set_bb_reg(dm, 0x808, MASKBYTE0, 0x23); /* CCK path-b */ + } + } else { + odm_set_bb_reg(dm, 0x808, MASKBYTE0, 0x33); /* disable 1RCCA */ + odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x0); /* CCK default is at path-a */ + } } void phydm_dynamic_select_cck_path_8822b( - struct PHY_DM_STRUCT *p_dm + struct dm_struct *dm ) { - struct _FALSE_ALARM_STATISTICS *p_fa_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm, PHYDM_FALSEALMCNT); - struct phydm_rtl8822b_struct *p_8822b = &p_dm->phydm_rtl8822b; + struct phydm_fa_struct *fa_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT); + struct drp_rtl8822b_struct *drp_8822b = &dm->phydm_rtl8822b; - if (p_dm->ap_total_num > 10) { - if (p_8822b->path_judge & BIT(2)) - odm_set_bb_reg(p_dm, 0xa04, 0x0f000000, 0x0); /*fix CCK Path A if AP nums > 10*/ + if (dm->ap_total_num > 10) { + if (drp_8822b->path_judge & BIT(2)) + odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x0); /*fix CCK Path A if AP nums > 10*/ return; } - if (p_8822b->path_judge & BIT(2)) + if (drp_8822b->path_judge & BIT(2)) return; - ODM_RT_TRACE(p_dm, ODM_PHY_CONFIG, ODM_DBG_LOUD, - ("phydm 8822b cck rx path selection start\n")); + PHYDM_DBG(dm, ODM_PHY_CONFIG,"phydm 8822b cck rx path selection start\n"); - if (p_8822b->path_judge & ODM_RF_A) { - p_8822b->path_a_cck_fa = (u16)p_fa_cnt->cnt_cck_fail; - p_8822b->path_judge &= ~ODM_RF_A; - odm_set_bb_reg(p_dm, 0xa04, 0x0f000000, 0x5); /*change to path B collect CCKFA*/ - } else if (p_8822b->path_judge & ODM_RF_B) { - p_8822b->path_b_cck_fa = (u16)p_fa_cnt->cnt_cck_fail; - p_8822b->path_judge &= ~ODM_RF_B; + if (drp_8822b->path_judge & BB_PATH_A) { + drp_8822b->path_a_cck_fa = (u16)fa_cnt->cnt_cck_fail; + drp_8822b->path_judge = (enum bb_path)(drp_8822b->path_judge & ~BB_PATH_A); + odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x5); /*change to path B collect CCKFA*/ + } else if (drp_8822b->path_judge & BB_PATH_B) { + drp_8822b->path_b_cck_fa = (u16)fa_cnt->cnt_cck_fail; + drp_8822b->path_judge =(enum bb_path)(drp_8822b->path_judge & ~BB_PATH_B); - if (p_8822b->path_a_cck_fa <= p_8822b->path_b_cck_fa) - odm_set_bb_reg(p_dm, 0xa04, 0x0f000000, 0x0); /*FA A<=B choose A*/ + if (drp_8822b->path_a_cck_fa <= drp_8822b->path_b_cck_fa) + odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x0); /*FA A<=B choose A*/ else - odm_set_bb_reg(p_dm, 0xa04, 0x0f000000, 0x5); /*FA B>A choose B*/ + odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x5); /*FA B>A choose B*/ - p_8822b->path_judge |= BIT(2); /*it means we have already choosed cck rx path*/ + drp_8822b->path_judge = (enum bb_path)(drp_8822b->path_judge | BIT(2)); /*it means we have already choosed cck rx path*/ } - ODM_RT_TRACE(p_dm, ODM_PHY_CONFIG, ODM_DBG_LOUD, - ("path_a_fa = %d, path_b_fa = %d\n", p_8822b->path_a_cck_fa, p_8822b->path_b_cck_fa)); + PHYDM_DBG(dm, ODM_PHY_CONFIG,"path_a_fa = %d, path_b_fa = %d\n", drp_8822b->path_a_cck_fa, drp_8822b->path_b_cck_fa); } + void phydm_somlrxhp_setting( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, boolean switch_soml ) { - if (switch_soml == true) - odm_set_bb_reg(p_dm_odm, 0x19a8, MASKDWORD, 0xd10a0000); - else - odm_set_bb_reg(p_dm_odm, 0x19a8, MASKDWORD, 0x010a0000); - - /* Dynamic RxHP setting with SoML on/off apply on all RFE type, except of QFN eFEM (1,6,7,9) */ - /* SoML on -> 2.4G: high-to-low; 5G: always low */ - /* SoML off-> 2.4G, 5G: high-to-low */ - if (!((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7) || (p_dm_odm->rfe_type == 9))) { - if (*p_dm_odm->p_channel <= 14) { + if (switch_soml == true) { + odm_set_bb_reg(dm, 0x19a8, MASKDWORD, 0xd10a0000); + /* Following are RxHP settings for T2R as always low, workaround for OTA test, required to classify */ + odm_set_bb_reg(dm, 0xc04, (BIT(21)|BIT(18)), 0x0); + odm_set_bb_reg(dm, 0xe04, (BIT(21)|BIT(18)), 0x0); + } else { + odm_set_bb_reg(dm, 0x19a8, MASKDWORD, 0x010a0000); + odm_set_bb_reg(dm, 0xc04, (BIT(21)|BIT(18)), 0x0); + odm_set_bb_reg(dm, 0xe04, (BIT(21)|BIT(18)), 0x0); + } + + /* Dynamic RxHP setting with SoML on/off apply on all RFE type */ + if (!switch_soml && ((dm->rfe_type == 1) || (dm->rfe_type == 6) || (dm->rfe_type == 7) || (dm->rfe_type == 9))) { + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0); + } + + if (*dm->channel <= 14) { + if (switch_soml && (!((dm->rfe_type == 3) || (dm->rfe_type == 5) || (dm->rfe_type == 8) || (dm->rfe_type == 17)))) { + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0); + } + } else if (*dm->channel > 35) { + if (switch_soml == true) { + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0); + } + } + +#if 0 + if (!((dm->rfe_type == 1) || (dm->rfe_type == 6) || (dm->rfe_type == 7) || (dm->rfe_type == 9))) { + if (*dm->channel <= 14) { /* TFBGA iFEM SoML on/off with RxHP always high-to-low */ - if (!((p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5))) { + if ((switch_soml == true) && (!((dm->rfe_type == 3) || (dm->rfe_type == 5)))) { if (switch_soml == true) { - odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08100000); - odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x0); - odm_set_bb_reg(p_dm_odm, 0xc04, (BIT(18)|BIT(21)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xe04, (BIT(18)|BIT(21)), 0x0); + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0); + odm_set_bb_reg(dm, 0xc04, (BIT(21)|(BIT(18))), 0x0); + odm_set_bb_reg(dm, 0xe04, (BIT(21)|(BIT(18))), 0x0); } else { - odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08108492); - odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x1); + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x1); } } - } else if (*p_dm_odm->p_channel > 35) { - if ((switch_soml == true) && (!((p_dm_odm->rfe_type == 1) || (p_dm_odm->rfe_type == 6) || (p_dm_odm->rfe_type == 7) || (p_dm_odm->rfe_type == 9)))) { - odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08100000); - odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x0); - odm_set_bb_reg(p_dm_odm, 0xc04, (BIT(18)|BIT(21)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xe04, (BIT(18)|BIT(21)), 0x0); + } else if (*dm->channel > 35) { + if (switch_soml == true) { + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0); + odm_set_bb_reg(dm, 0xc04, (BIT(21)|(BIT(18))), 0x0); + odm_set_bb_reg(dm, 0xe04, (BIT(21)|(BIT(18))), 0x0); } else { - odm_set_bb_reg(p_dm_odm, 0x8cc, MASKDWORD, 0x08108492); - odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(27), 0x1); + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492); + odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x1); } } - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Dynamic RxHP control with SoML is enable !!\n")); */ + PHYDM_DBG(dm, ODM_COMP_API, "Dynamic RxHP control with SoML is enable !!\n"); } +#endif + } +void +phydm_config_tx2path_8822b( + struct dm_struct *dm, + enum wireless_set wireless_mode, + boolean is_tx2_path +) +{ + if (wireless_mode == WIRELESS_CCK) { + if (is_tx2_path == true) + odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0xc); + else + odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x8); + } else { + if (is_tx2_path == true) + odm_set_bb_reg(dm, 0x93c, 0xf00000, 0x3); + else + odm_set_bb_reg(dm, 0x93c, 0xf00000, 0x1); + } +} + +#ifdef DYN_ANT_WEIGHTING_SUPPORT +void +phydm_dynamic_ant_weighting_8822b( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rssi_l2h = 43, rssi_h2l = 37; + u8 reg_8; + + if (dm->is_disable_dym_ant_weighting) + return; + + if (*dm->channel <= 14) { + if (dm->rssi_min >= rssi_l2h) { + odm_set_bb_reg(dm, 0x98c, 0x7fc0000, 0x0); + + /*equal weighting*/ + reg_8 = (u8)odm_get_bb_reg(dm, 0xf94, BIT(0)|BIT(1)|BIT(2)); + PHYDM_DBG(dm, ODM_COMP_API, "Equal weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n", dm->rssi_min, reg_8); + } else if (dm->rssi_min <= rssi_h2l) { + odm_set_bb_reg(dm, 0x98c, MASKDWORD, 0x43440000); + + /*fix sec_min_wgt = 1/2*/ + reg_8 = (u8)odm_get_bb_reg(dm, 0xf94, BIT(0)|BIT(1)|BIT(2)); + PHYDM_DBG(dm, ODM_COMP_API, "AGC weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n", dm->rssi_min, reg_8); + } + } else { + odm_set_bb_reg(dm, 0x98c, MASKDWORD, 0x43440000); + + reg_8 = (u8)odm_get_bb_reg(dm, 0xf94, BIT(0)|BIT(1)|BIT(2)); + PHYDM_DBG(dm, ODM_COMP_API, "AGC weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n", dm->rssi_min, reg_8); + /*fix sec_min_wgt = 1/2*/ + } + +} +#endif void phydm_hwsetting_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { - struct phydm_rtl8822b_struct *p_8822b = &p_dm_odm->phydm_rtl8822b; + struct drp_rtl8822b_struct *drp_8822b = &dm->phydm_rtl8822b; + u8 set_result_nbi = PHYDM_SET_NO_NEED; - if((p_dm_odm->p_advance_ota & PHYDM_HP_OTA_SETTING_A) || (p_dm_odm->p_advance_ota & PHYDM_HP_OTA_SETTING_B)) { - phydm_dynamic_parameters_ota(p_dm_odm); + if ((dm->p_advance_ota & PHYDM_HP_OTA_SETTING_A) || (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_B)) { + phydm_dynamic_parameters_ota(dm); } else { - if (p_dm_odm->bhtstfenabled == TRUE) - phydm_dynamic_switch_htstf_mumimo_8822b(p_dm_odm); + if (dm->bhtstfdisabled == false) + phydm_dynamic_switch_htstf_mumimo_8822b(dm); else - /* odm_set_bb_reg(p_dm_odm, 0x8d8, BIT(17), 0x1);*/ - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_LOUD, ("Default HT-STF gain control setting\n")); - } - - if (p_dm_odm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) { - if (p_dm_odm->rssi_min <= 20) - phydm_somlrxhp_setting(p_dm_odm, false); - else if (p_dm_odm->rssi_min >= 25) - phydm_somlrxhp_setting(p_dm_odm, true); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Default HT-STF gain control setting\n"); } - if (p_dm_odm->p_advance_ota & PHYDM_ASUS_OTA_SETTING_CCK_PATH) { - if (p_dm_odm->is_linked) - phydm_dynamic_select_cck_path_8822b(p_dm_odm); + phydm_dynamic_ant_weighting(dm); + + if (dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) { + if (dm->rssi_min <= 20) + phydm_somlrxhp_setting(dm, false); + else if (dm->rssi_min >= 25) + phydm_somlrxhp_setting(dm, true); + } + + if ((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING_CCK_PATH) || (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_CCK_PATH)) { + if (dm->is_linked) + phydm_dynamic_select_cck_path_8822b(dm); else - p_8822b->path_judge |= ((~ BIT(2)) | ODM_RF_A | ODM_RF_B); + drp_8822b->path_judge =(enum bb_path)(drp_8822b->path_judge | ((~ BIT(2)) | BB_PATH_A | BB_PATH_B)); + } + + if (dm->p_advance_ota & PHYDM_LENOVO_OTA_SETTING_NBI_CSI) { + if ((*dm->band_width == CHANNEL_WIDTH_80) && (*dm->channel == 157)) { + set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 80, 5760, PHYDM_DONT_CARE); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Enable NBI\n"); + } } - } #endif /* RTL8822B_SUPPORT == 1 */ diff --git a/hal/phydm/rtl8822b/phydm_rtl8822b.h b/hal/phydm/rtl8822b/phydm_rtl8822b.h index 3b23b13..72cd54e 100644 --- a/hal/phydm/rtl8822b/phydm_rtl8822b.h +++ b/hal/phydm/rtl8822b/phydm_rtl8822b.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,28 +8,53 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #if (RTL8822B_SUPPORT == 1) #ifndef __ODM_RTL8822B_H__ #define __ODM_RTL8822B_H__ +#ifdef DYN_ANT_WEIGHTING_SUPPORT +void +phydm_dynamic_ant_weighting_8822b( + void *dm_void +); +#endif + +void +phydm_1rcca_setting( + struct dm_struct *dm, + boolean enable_1rcca +); + void phydm_somlrxhp_setting( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, boolean switch_soml ); void phydm_hwsetting_8822b( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm +); + +void +phydm_config_tx2path_8822b( + struct dm_struct *dm, + enum wireless_set wireless_mode, + boolean is_tx2_path ); #endif /* #define __ODM_RTL8822B_H__ */ diff --git a/hal/phydm/rtl8822b/phydm_rtl8822b_ram.c b/hal/phydm/rtl8822b/phydm_rtl8822b_ram.c deleted file mode 100644 index 55c568f..0000000 --- a/hal/phydm/rtl8822b/phydm_rtl8822b_ram.c +++ /dev/null @@ -1,7 +0,0 @@ -//alex temp disable for merge, 20160328 -//#include "phydm_precomp.h" - -//__iram_odm_func__ void phydm_InitFuncPtrTableRAM8822B(void){ - - -//} \ No newline at end of file diff --git a/hal/phydm/rtl8822b/phydm_rtl8822b_ram.h b/hal/phydm/rtl8822b/phydm_rtl8822b_ram.h deleted file mode 100644 index 908a549..0000000 --- a/hal/phydm/rtl8822b/phydm_rtl8822b_ram.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef __PHYDM_RTL8822B_RAM_H__ -#define __PHYDM_RTL8822B_RAM_H__ - -//============================================================ -//3 -//3 This file defines 8822B RAM code function pointer -//3 -//============================================================ - -//#define phydm_InitFuncPtrTableRAM phydm_InitFuncPtrTableRAM8822B - -//void phydm_InitFuncPtrTableRAM8822B(void); - -#if IS_CUT_TEST(CONFIG_CHIP_SEL) -#define FW_FIFO_Parsing_pu1Byte FW_FIFO_Parsing_pu1Byte_RAM -#define odm_ConvertTo_dB odm_ConvertTo_dB_RAM -#define odm_ConvertTo_linear odm_ConvertTo_linear_RAM -#define odm_QueryRxPwrPercentage odm_QueryRxPwrPercentage_RAM -#define odm_EVMdbToPercentage odm_EVMdbToPercentage_RAM -#define phydm_ResetPhyInfo phydm_ResetPhyInfo_RAM -#define phydm_SetPerPathPhyInfo phydm_SetPerPathPhyInfo_RAM -#define phydm_SetCommonPhyInfo phydm_SetCommonPhyInfo_RAM -#define phydm_GetRxPhyStatusType0 phydm_GetRxPhyStatusType0_RAM -#define phydm_GetRxPhyStatusType1 phydm_GetRxPhyStatusType1_RAM -#define phydm_GetRxPhyStatusType2 phydm_GetRxPhyStatusType2_RAM -#define phydm_GetRxPhyStatusType5 phydm_GetRxPhyStatusType5_RAM -#define phydm_Process_RSSIForDM_Jaguar2 phydm_Process_RSSIForDM_Jaguar2_RAM -#define phydm_RxPhyStatusJaguarSeries2 phydm_RxPhyStatusJaguarSeries2_RAM -#define phystatus_parsing phystatus_parsing_RAM -#elif IS_CUT_B(CONFIG_CHIP_SEL) - -#endif - -#endif //__PHYDM_RTL8821C_RAM_H__ \ No newline at end of file diff --git a/hal/phydm/rtl8822b/version_rtl8822b.h b/hal/phydm/rtl8822b/version_rtl8822b.h index 85de71d..c3be6dc 100644 --- a/hal/phydm/rtl8822b/version_rtl8822b.h +++ b/hal/phydm/rtl8822b/version_rtl8822b.h @@ -1,9 +1,33 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ /*RTL8822B PHY Parameters*/ /* [Caution] Since 01/Aug/2015, the commit rules will be simplified. You do not need to fill up the version.h anymore, only the maintenance supervisor fills it before formal release. */ -#define RELEASE_DATE_8822B 20170526 +#define RELEASE_DATE_8822B 20171201 #define COMMIT_BY_8822B "BB_JOE" -#define RELEASE_VERSION_8822B 85 +#define RELEASE_VERSION_8822B 104 diff --git a/hal/phydm/txbf/halcomtxbf.c b/hal/phydm/txbf/halcomtxbf.c index 090b239..8de20bb 100644 --- a/hal/phydm/txbf/halcomtxbf.c +++ b/hal/phydm/txbf/halcomtxbf.c @@ -26,276 +26,276 @@ void hal_com_txbf_beamform_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; boolean is_iqgen_setting_ok = false; - if (p_dm_odm->support_ic_type & ODM_RTL8814A) { - is_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] is_iqgen_setting_ok = %d\n", __func__, is_iqgen_setting_ok)); + if (dm->support_ic_type & ODM_RTL8814A) { + is_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(dm); + PHYDM_DBG(dm, DBG_TXBF, "[%s] is_iqgen_setting_ok = %d\n", __func__, is_iqgen_setting_ok); } } /*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ void hal_com_txbf_config_gtab( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - hal_txbf_8822b_config_gtab(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_config_gtab(dm); } void phydm_beamform_set_sounding_enter( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_enter_work_item)) == false) odm_schedule_work_item(&(p_txbf_info->txbf_enter_work_item)); #else - hal_com_txbf_enter_work_item_callback(p_dm_odm); + hal_com_txbf_enter_work_item_callback(dm); #endif } void phydm_beamform_set_sounding_leave( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_leave_work_item)) == false) odm_schedule_work_item(&(p_txbf_info->txbf_leave_work_item)); #else - hal_com_txbf_leave_work_item_callback(p_dm_odm); + hal_com_txbf_leave_work_item_callback(dm); #endif } void phydm_beamform_set_sounding_rate( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_rate_work_item)) == false) odm_schedule_work_item(&(p_txbf_info->txbf_rate_work_item)); #else - hal_com_txbf_rate_work_item_callback(p_dm_odm); + hal_com_txbf_rate_work_item_callback(dm); #endif } void phydm_beamform_set_sounding_status( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_status_work_item)) == false) odm_schedule_work_item(&(p_txbf_info->txbf_status_work_item)); #else - hal_com_txbf_status_work_item_callback(p_dm_odm); + hal_com_txbf_status_work_item_callback(dm); #endif } void phydm_beamform_set_sounding_fw_ndpa( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - if (*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress) - odm_set_timer(p_dm_odm, &(p_txbf_info->txbf_fw_ndpa_timer), 5); + if (*dm->is_fw_dw_rsvd_page_in_progress) + odm_set_timer(dm, &(p_txbf_info->txbf_fw_ndpa_timer), 5); else odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item)); #else - hal_com_txbf_fw_ndpa_work_item_callback(p_dm_odm); + hal_com_txbf_fw_ndpa_work_item_callback(dm); #endif } void phydm_beamform_set_sounding_clk( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_clk_work_item)) == false) odm_schedule_work_item(&(p_txbf_info->txbf_clk_work_item)); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct _ADAPTER *padapter = p_dm_odm->adapter; + void *padapter = dm->adapter; - rtw_run_in_thread_cmd(padapter, hal_com_txbf_clk_work_item_callback, padapter); + rtw_run_in_thread_cmd(padapter, hal_com_txbf_clk_work_item_callback, dm); #else - hal_com_txbf_clk_work_item_callback(p_dm_odm); + hal_com_txbf_clk_work_item_callback(dm); #endif } void phydm_beamform_set_reset_tx_path( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_reset_tx_path_work_item)) == false) odm_schedule_work_item(&(p_txbf_info->txbf_reset_tx_path_work_item)); #else - hal_com_txbf_reset_tx_path_work_item_callback(p_dm_odm); + hal_com_txbf_reset_tx_path_work_item_callback(dm); #endif } void phydm_beamform_set_get_tx_rate( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_get_tx_rate_work_item)) == false) odm_schedule_work_item(&(p_txbf_info->txbf_get_tx_rate_work_item)); #else - hal_com_txbf_get_tx_rate_work_item_callback(p_dm_odm); + hal_com_txbf_get_tx_rate_work_item_callback(dm); #endif } void hal_com_txbf_enter_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; u8 idx = p_txbf_info->txbf_idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) - hal_txbf_jaguar_enter(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8192E) - hal_txbf_8192e_enter(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_enter(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8822B) - hal_txbf_8822b_enter(p_dm_odm, idx); + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_enter(dm, idx); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_enter(dm, idx); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_enter(dm, idx); + else if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_enter(dm, idx); } void hal_com_txbf_leave_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; u8 idx = p_txbf_info->txbf_idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) - hal_txbf_jaguar_leave(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8192E) - hal_txbf_8192e_leave(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_leave(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8822B) - hal_txbf_8822b_leave(p_dm_odm, idx); + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_leave(dm, idx); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_leave(dm, idx); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_leave(dm, idx); + else if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_leave(dm, idx); } void hal_com_txbf_fw_ndpa_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; u8 idx = p_txbf_info->ndpa_idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) - hal_txbf_jaguar_fw_txbf(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8192E) - hal_txbf_8192e_fw_tx_bf(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_fw_txbf(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8822B) - hal_txbf_8822b_fw_txbf(p_dm_odm, idx); + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_fw_txbf(dm, idx); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_fw_tx_bf(dm, idx); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_fw_txbf(dm, idx); + else if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_fw_txbf(dm, idx); } void hal_com_txbf_clk_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_dm_odm->support_ic_type & ODM_RTL8812) - hal_txbf_jaguar_clk_8812a(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8812) + hal_txbf_jaguar_clk_8812a(dm); } @@ -303,30 +303,30 @@ hal_com_txbf_clk_work_item_callback( void hal_com_txbf_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; u8 BW = p_txbf_info->BW; u8 rate = p_txbf_info->rate; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_dm_odm->support_ic_type & ODM_RTL8812) - hal_txbf_8812a_set_ndpa_rate(p_dm_odm, BW, rate); - else if (p_dm_odm->support_ic_type & ODM_RTL8192E) - hal_txbf_8192e_set_ndpa_rate(p_dm_odm, BW, rate); - else if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_set_ndpa_rate(p_dm_odm, BW, rate); + if (dm->support_ic_type & ODM_RTL8812) + hal_txbf_8812a_set_ndpa_rate(dm, BW, rate); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_set_ndpa_rate(dm, BW, rate); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_set_ndpa_rate(dm, BW, rate); } @@ -334,21 +334,21 @@ hal_com_txbf_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void hal_com_txbf_fw_ndpa_timer_callback( - struct timer_list *p_timer + struct phydm_timer_list *timer ) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + void *adapter = (void *)timer->Adapter; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress) - odm_set_timer(p_dm_odm, &(p_txbf_info->txbf_fw_ndpa_timer), 5); + if (*dm->is_fw_dw_rsvd_page_in_progress) + odm_set_timer(dm, &(p_txbf_info->txbf_fw_ndpa_timer), 5); else odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item)); } @@ -358,130 +358,130 @@ hal_com_txbf_fw_ndpa_timer_callback( void hal_com_txbf_status_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; u8 idx = p_txbf_info->txbf_idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) - hal_txbf_jaguar_status(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8192E) - hal_txbf_8192e_status(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_status(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8822B) - hal_txbf_8822b_status(p_dm_odm, idx); + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_status(dm, idx); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_status(dm, idx); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_status(dm, idx); + else if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_status(dm, idx); } void hal_com_txbf_reset_tx_path_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; u8 idx = p_txbf_info->txbf_idx; - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_reset_tx_path(p_dm_odm, idx); + if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_reset_tx_path(dm, idx); } void hal_com_txbf_get_tx_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_get_tx_rate(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_get_tx_rate(dm); } boolean hal_com_txbf_set( - void *p_dm_void, + void *dm_void, u8 set_type, void *p_in_buf ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 *p_u1_tmp = (u8 *)p_in_buf; - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set_type = 0x%X\n", __func__, set_type)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] set_type = 0x%X\n", __func__, set_type); switch (set_type) { case TXBF_SET_SOUNDING_ENTER: p_txbf_info->txbf_idx = *p_u1_tmp; - phydm_beamform_set_sounding_enter(p_dm_odm); + phydm_beamform_set_sounding_enter(dm); break; case TXBF_SET_SOUNDING_LEAVE: p_txbf_info->txbf_idx = *p_u1_tmp; - phydm_beamform_set_sounding_leave(p_dm_odm); + phydm_beamform_set_sounding_leave(dm); break; case TXBF_SET_SOUNDING_RATE: p_txbf_info->BW = p_u1_tmp[0]; p_txbf_info->rate = p_u1_tmp[1]; - phydm_beamform_set_sounding_rate(p_dm_odm); + phydm_beamform_set_sounding_rate(dm); break; case TXBF_SET_SOUNDING_STATUS: p_txbf_info->txbf_idx = *p_u1_tmp; - phydm_beamform_set_sounding_status(p_dm_odm); + phydm_beamform_set_sounding_status(dm); break; case TXBF_SET_SOUNDING_FW_NDPA: p_txbf_info->ndpa_idx = *p_u1_tmp; - phydm_beamform_set_sounding_fw_ndpa(p_dm_odm); + phydm_beamform_set_sounding_fw_ndpa(dm); break; case TXBF_SET_SOUNDING_CLK: - phydm_beamform_set_sounding_clk(p_dm_odm); + phydm_beamform_set_sounding_clk(dm); break; case TXBF_SET_TX_PATH_RESET: p_txbf_info->txbf_idx = *p_u1_tmp; - phydm_beamform_set_reset_tx_path(p_dm_odm); + phydm_beamform_set_reset_tx_path(dm); break; case TXBF_SET_GET_TX_RATE: - phydm_beamform_set_get_tx_rate(p_dm_odm); + phydm_beamform_set_get_tx_rate(dm); break; } @@ -492,16 +492,16 @@ hal_com_txbf_set( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) boolean hal_com_txbf_get( - struct _ADAPTER *adapter, + void *adapter, u8 get_type, void *p_out_buf ) { - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; boolean *p_boolean = (boolean *)p_out_buf; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); if (get_type == TXBF_GET_EXPLICIT_BEAMFORMEE) { if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter)) @@ -520,7 +520,7 @@ hal_com_txbf_get( IS_HARDWARE_TYPE_8821B(adapter) || IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) { - if (p_hal_data->RF_Type == RF_2T2R || p_hal_data->RF_Type == RF_3T3R) + if (hal_data->RF_Type == RF_2T2R || hal_data->RF_Type == RF_3T3R) *p_boolean = true; else *p_boolean = false; diff --git a/hal/phydm/txbf/halcomtxbf.h b/hal/phydm/txbf/halcomtxbf.h index 0d95b69..2e9e5a0 100644 --- a/hal/phydm/txbf/halcomtxbf.h +++ b/hal/phydm/txbf/halcomtxbf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __HAL_COM_TXBF_H__ #define __HAL_COM_TXBF_H__ @@ -18,14 +28,14 @@ /* typedef bool (*TXBF_GET)( - void* p_adapter, + void* adapter, u8 get_type, void* p_out_buf ); typedef bool (*TXBF_SET)( - void* p_adapter, + void* adapter, u8 set_type, void* p_in_buf ); @@ -59,7 +69,7 @@ struct _HAL_TXBF_INFO { u8 BW; u8 rate; - struct timer_list txbf_fw_ndpa_timer; + struct phydm_timer_list txbf_fw_ndpa_timer; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) RT_WORK_ITEM txbf_enter_work_item; RT_WORK_ITEM txbf_leave_work_item; @@ -77,108 +87,108 @@ struct _HAL_TXBF_INFO { void hal_com_txbf_beamform_init( - void *p_dm_void + void *dm_void ); void hal_com_txbf_config_gtab( - void *p_dm_void + void *dm_void ); void hal_com_txbf_enter_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ); void hal_com_txbf_leave_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ); void hal_com_txbf_fw_ndpa_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ); void hal_com_txbf_clk_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ); void hal_com_txbf_reset_tx_path_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ); void hal_com_txbf_get_tx_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ); void hal_com_txbf_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ); void hal_com_txbf_fw_ndpa_timer_callback( - struct timer_list *p_timer + struct phydm_timer_list *timer ); void hal_com_txbf_status_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif ); boolean hal_com_txbf_set( - void *p_dm_void, + void *dm_void, u8 set_type, void *p_in_buf ); boolean hal_com_txbf_get( - struct _ADAPTER *adapter, + void *adapter, u8 get_type, void *p_out_buf ); #else -#define hal_com_txbf_beamform_init(p_dm_void) NULL -#define hal_com_txbf_config_gtab(p_dm_void) NULL +#define hal_com_txbf_beamform_init(dm_void) NULL +#define hal_com_txbf_config_gtab(dm_void) NULL #define hal_com_txbf_enter_work_item_callback(_adapter) NULL #define hal_com_txbf_leave_work_item_callback(_adapter) NULL #define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL diff --git a/hal/phydm/txbf/haltxbf8192e.c b/hal/phydm/txbf/haltxbf8192e.c index 8b1df1e..cec2559 100644 --- a/hal/phydm/txbf/haltxbf8192e.c +++ b/hal/phydm/txbf/haltxbf8192e.c @@ -26,93 +26,90 @@ void hal_txbf_8192e_set_ndpa_rate( - void *p_dm_void, + void *dm_void, u8 BW, u8 rate ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW)); + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW)); } void hal_txbf_8192e_rf_mode( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - boolean is_self_beamformer = false; - boolean is_self_beamformee = false; - enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_dm_odm->rf_type == ODM_1T1R) + if (dm->rf_type == RF_1T1R) return; - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ - if (p_beam_info->beamformee_su_cnt > 0) { + if (beam_info->beamformee_su_cnt > 0) { /*Path_A*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ /*Path_B*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0xfffff, 0x18000); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ } else { /*Path_A*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ /*Path_B*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0xfffff, 0x18000); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ } - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ - if (p_beam_info->beamformee_su_cnt > 0) { - odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x83321333); - odm_set_bb_reg(p_dm_odm, 0xa04, MASKBYTE3, 0xc1); + if (beam_info->beamformee_su_cnt > 0) { + odm_set_bb_reg(dm, 0x90c, MASKDWORD, 0x83321333); + odm_set_bb_reg(dm, 0xa04, MASKBYTE3, 0xc1); } else - odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x81121313); + odm_set_bb_reg(dm, 0x90c, MASKDWORD, 0x81121313); } void hal_txbf_8192e_fw_txbf_cmd( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 idx, period0 = 0, period1 = 0; u8 PageNum0 = 0xFF, PageNum1 = 0xFF; u8 u1_tx_bf_parm[3] = {0}; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - if (p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { if (idx == 0) { - if (p_beam_info->beamformee_entry[idx].is_sound) + if (beam_info->beamformee_entry[idx].is_sound) PageNum0 = 0xFE; else PageNum0 = 0xFF; /* stop sounding */ - period0 = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + period0 = (u8)(beam_info->beamformee_entry[idx].sound_period); } else if (idx == 1) { - if (p_beam_info->beamformee_entry[idx].is_sound) + if (beam_info->beamformee_entry[idx].is_sound) PageNum1 = 0xFE; else PageNum1 = 0xFF; /* stop sounding */ - period1 = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + period1 = (u8)(beam_info->beamformee_entry[idx].sound_period); } } } @@ -120,91 +117,90 @@ hal_txbf_8192e_fw_txbf_cmd( u1_tx_bf_parm[0] = PageNum0; u1_tx_bf_parm[1] = PageNum1; u1_tx_bf_parm[2] = (period1 << 4) | period0; - odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); + odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, - ("[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", __func__, PageNum0, period0, PageNum1, period1)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", __func__, PageNum0, period0, PageNum1, period1); } void hal_txbf_8192e_download_ndpa( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 u1b_tmp = 0, tmp_reg422 = 0, head_page; u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; boolean is_send_beacon = false; - struct _ADAPTER *adapter = p_dm_odm->adapter; u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/ - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true; + *dm->is_fw_dw_rsvd_page_in_progress = true; #endif if (idx == 0) head_page = 0xFE; else head_page = 0xFE; - phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy); + phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy); /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8192E+1); - odm_write_1byte(p_dm_odm, REG_CR_8192E+1, (u1b_tmp | BIT(0))); + u1b_tmp = odm_read_1byte(dm, REG_CR_8192E+1); + odm_write_1byte(dm, REG_CR_8192E+1, (u1b_tmp | BIT(0))); /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2); - odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422 & (~BIT(6))); + tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8192E+2); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422 & (~BIT(6))); if (tmp_reg422 & BIT(6)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an adapter is sending beacon.\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s There is an adapter is sending beacon.\n", __func__); is_send_beacon = true; } /*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/ - odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+1, head_page); + odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E+1, head_page); do { /*Clear beacon valid check bit.*/ - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2); - odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2, (bcn_valid_reg | BIT(0))); + bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E+2); + odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E+2, (bcn_valid_reg | BIT(0))); /* download NDPA rsvd page. */ - beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - u1b_tmp = odm_read_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3); + u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E+3); count = 0; while ((count < 20) && (u1b_tmp & BIT(4))) { count++; ODM_delay_us(10); - u1b_tmp = odm_read_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3); + u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E+3); } - odm_write_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3, u1b_tmp | BIT(4)); + odm_write_1byte(dm, REG_MGQ_TXBD_NUM_8192E+3, u1b_tmp | BIT(4)); #endif /*check rsvd page download OK.*/ - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2); + bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E+2); count = 0; while (!(bcn_valid_reg & BIT(0)) && count < 20) { count++; ODM_delay_us(10); - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2); + bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E+2); } dl_bcn_count++; } while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5); if (!(bcn_valid_reg & BIT(0))) - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n", __func__); /*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/ - odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+1, tx_page_bndy); + odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E+1, tx_page_bndy); /*To make sure that if there exists an adapter which would like to send beacon.*/ /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ @@ -212,99 +208,99 @@ hal_txbf_8192e_download_ndpa( /*the beacon cannot be sent by HW.*/ /*2010.06.23. Added by tynli.*/ if (is_send_beacon) - odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422); /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8192E+1); - odm_write_1byte(p_dm_odm, REG_CR_8192E+1, (u1b_tmp & (~BIT(0)))); + u1b_tmp = odm_read_1byte(dm, REG_CR_8192E+1); + odm_write_1byte(dm, REG_CR_8192E+1, (u1b_tmp & (~BIT(0)))); p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false; + *dm->is_fw_dw_rsvd_page_in_progress = false; #endif } void hal_txbf_8192e_enter( - void *p_dm_void, + void *dm_void, u8 bfer_bfee_idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; u8 bfee_idx = (bfer_bfee_idx & 0xF); u32 csi_param; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; struct _RT_BEAMFORMEE_ENTRY beamformee_entry; struct _RT_BEAMFORMER_ENTRY beamformer_entry; u16 sta_id = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - hal_txbf_8192e_rf_mode(p_dm_odm, p_beamforming_info); + hal_txbf_8192e_rf_mode(dm, beamforming_info); - if (p_dm_odm->rf_type == ODM_2T2R) - odm_write_4byte(p_dm_odm, 0xd80, 0x00000000); /*nc =2*/ + if (dm->rf_type == RF_2T2R) + odm_write_4byte(dm, 0xd80, 0x00000000); /*nc =2*/ - if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { - beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx]; + if ((beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { + beamformer_entry = beamforming_info->beamformer_entry[bfer_idx]; /*Sounding protocol control*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E, 0xCB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xCB); /*MAC address/Partial AID of Beamformer*/ if (bfer_idx == 0) { for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), beamformer_entry.mac_addr[i]); + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), beamformer_entry.mac_addr[i]); } else { for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), beamformer_entry.mac_addr[i]); + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), beamformer_entry.mac_addr[i]); } /*CSI report parameters of Beamformer Default use nc = 2*/ csi_param = 0x03090309; - odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param); - odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param); - odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param); /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E+3, 0x50); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E+3, 0x50); } - if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { - beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx]; + if ((beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { + beamformee_entry = beamforming_info->beamformee_entry[bfee_idx]; - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) sta_id = beamformee_entry.mac_id; else sta_id = beamformee_entry.p_aid; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], sta_id=0x%X\n", __func__, sta_id)); + PHYDM_DBG(dm, DBG_TXBF, "[%s], sta_id=0x%X\n", __func__, sta_id); /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ if (bfee_idx == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E, sta_id); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_TXBF_CTRL_8192E, sta_id); + odm_write_1byte(dm, REG_TXBF_CTRL_8192E+3, odm_read_1byte(dm, REG_TXBF_CTRL_8192E+3) | BIT(4) | BIT(6) | BIT(7)); } else - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E+2, sta_id | BIT(12) | BIT(14) | BIT(15)); + odm_write_2byte(dm, REG_TXBF_CTRL_8192E+2, sta_id | BIT(12) | BIT(14) | BIT(15)); /*CSI report parameters of Beamformee*/ if (bfee_idx == 0) { /*Get BIT24 & BIT25*/ - u8 tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3; + u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3; - odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9)); + odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9)); } else { /*Set BIT25*/ - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, sta_id | 0xE200); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, sta_id | 0xE200); } - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); } } @@ -312,51 +308,51 @@ hal_txbf_8192e_enter( void hal_txbf_8192e_leave( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; - hal_txbf_8192e_rf_mode(p_dm_odm, p_beam_info); + hal_txbf_8192e_rf_mode(dm, beam_info); /* Clear P_AID of Beamformee * Clear MAC addresss of Beamformer * Clear Associated Bfmee Sel */ - if (p_beam_info->beamform_cap == BEAMFORMING_CAP_NONE) - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E, 0xC8); + if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE) + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xC8); if (idx == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E, 0); - odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0); + odm_write_2byte(dm, REG_TXBF_CTRL_8192E, 0); + odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0); } else { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E+2, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+2) & 0xF000); - odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60); + odm_write_2byte(dm, REG_TXBF_CTRL_8192E+2, odm_read_1byte(dm, REG_TXBF_CTRL_8192E+2) & 0xF000); + odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60); } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx %d\n", __func__, idx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] idx %d\n", __func__, idx); } void hal_txbf_8192e_status( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u16 beam_ctrl_val; u32 beam_ctrl_reg; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY beamform_entry = p_beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx]; - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) beam_ctrl_val = beamform_entry.mac_id; else beam_ctrl_val = beamform_entry.p_aid; @@ -368,7 +364,7 @@ hal_txbf_8192e_status( beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); } - if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beam_info->apply_v_matrix == true)) { + if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (beam_info->apply_v_matrix == true)) { if (beamform_entry.sound_bw == CHANNEL_WIDTH_20) beam_ctrl_val |= BIT(9); else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40) @@ -376,28 +372,28 @@ hal_txbf_8192e_status( } else beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); - odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val); + odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__, idx, beam_ctrl_reg, beam_ctrl_val)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__, idx, beam_ctrl_reg, beam_ctrl_val); } void hal_txbf_8192e_fw_tx_bf( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) - hal_txbf_8192e_download_ndpa(p_dm_odm, idx); + hal_txbf_8192e_download_ndpa(dm, idx); - hal_txbf_8192e_fw_txbf_cmd(p_dm_odm); + hal_txbf_8192e_fw_txbf_cmd(dm); } #endif /* #if (RTL8192E_SUPPORT == 1)*/ diff --git a/hal/phydm/txbf/haltxbf8192e.h b/hal/phydm/txbf/haltxbf8192e.h index 636e0d5..360cbf7 100644 --- a/hal/phydm/txbf/haltxbf8192e.h +++ b/hal/phydm/txbf/haltxbf8192e.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __HAL_TXBF_8192E_H__ #define __HAL_TXBF_8192E_H__ @@ -20,54 +30,54 @@ void hal_txbf_8192e_set_ndpa_rate( - void *p_dm_void, + void *dm_void, u8 BW, u8 rate ); void hal_txbf_8192e_enter( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_8192e_leave( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_8192e_status( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_8192e_fw_tx_bf( - void *p_dm_void, + void *dm_void, u8 idx ); #else -#define hal_txbf_8192e_set_ndpa_rate(p_dm_void, BW, rate) -#define hal_txbf_8192e_enter(p_dm_void, idx) -#define hal_txbf_8192e_leave(p_dm_void, idx) -#define hal_txbf_8192e_status(p_dm_void, idx) -#define hal_txbf_8192e_fw_tx_bf(p_dm_void, idx) +#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_8192e_enter(dm_void, idx) +#define hal_txbf_8192e_leave(dm_void, idx) +#define hal_txbf_8192e_status(dm_void, idx) +#define hal_txbf_8192e_fw_tx_bf(dm_void, idx) #endif #else -#define hal_txbf_8192e_set_ndpa_rate(p_dm_void, BW, rate) -#define hal_txbf_8192e_enter(p_dm_void, idx) -#define hal_txbf_8192e_leave(p_dm_void, idx) -#define hal_txbf_8192e_status(p_dm_void, idx) -#define hal_txbf_8192e_fw_tx_bf(p_dm_void, idx) +#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_8192e_enter(dm_void, idx) +#define hal_txbf_8192e_leave(dm_void, idx) +#define hal_txbf_8192e_status(dm_void, idx) +#define hal_txbf_8192e_fw_tx_bf(dm_void, idx) #endif diff --git a/hal/phydm/txbf/haltxbf8814a.c b/hal/phydm/txbf/haltxbf8814a.c index 0c700c3..7a4eafb 100644 --- a/hal/phydm/txbf/haltxbf8814a.c +++ b/hal/phydm/txbf/haltxbf8814a.c @@ -27,43 +27,43 @@ boolean phydm_beamforming_set_iqgen_8814A( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; u16 counter = 0; u32 rf_mode[4]; - for (i = ODM_RF_PATH_A ; i < MAX_RF_PATH ; i++) - odm_set_rf_reg(p_dm_odm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ + for (i = RF_PATH_A ; i < MAX_RF_PATH ; i++) + odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ while (1) { counter++; - for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) - odm_set_rf_reg(p_dm_odm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/ + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) + odm_set_rf_reg(dm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/ ODM_delay_us(2); - for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) - rf_mode[i] = odm_get_rf_reg(p_dm_odm, i, RF_RCK_OS, 0xfffff); + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) + rf_mode[i] = odm_get_rf_reg(dm, i, RF_RCK_OS, 0xfffff); if ((rf_mode[0] == 0x18000) && (rf_mode[1] == 0x18000) && (rf_mode[2] == 0x18000) && (rf_mode[3] == 0x18000)) break; else if (counter == 100) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("iqgen setting fail:8814A\n")); + PHYDM_DBG(dm, DBG_TXBF, "iqgen setting fail:8814A\n"); return false; } } - for (i = ODM_RF_PATH_A ; i < MAX_RF_PATH ; i++) { - odm_set_rf_reg(p_dm_odm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*Enable TXIQGEN in Rx mode*/ + for (i = RF_PATH_A ; i < MAX_RF_PATH ; i++) { + odm_set_rf_reg(dm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/ + odm_set_rf_reg(dm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*Enable TXIQGEN in Rx mode*/ } - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*Enable TXIQGEN in Rx mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*Enable TXIQGEN in Rx mode*/ - for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) - odm_set_rf_reg(p_dm_odm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) + odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ return true; @@ -73,15 +73,15 @@ phydm_beamforming_set_iqgen_8814A( void hal_txbf_8814a_set_ndpa_rate( - void *p_dm_void, + void *dm_void, u8 BW, u8 rate ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8814A, BW); - odm_write_1byte(p_dm_odm, REG_NDPA_RATE_8814A, (u8) rate); + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8814A, BW); + odm_write_1byte(dm, REG_NDPA_RATE_8814A, (u8) rate); } #if 0 @@ -90,7 +90,7 @@ hal_txbf_8814a_set_ndpa_rate( void phydm_data_rate_8814a( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 mac_id, u32 *data, u8 data_len @@ -99,84 +99,89 @@ phydm_data_rate_8814a( u8 i = 0; u16 x_read_data_addr = 0; - odm_write_2byte(p_dm_odm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE); + odm_write_2byte(dm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE); x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*Ctrl Info: 32Bytes for each macid(n)*/ if ((x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ) || (x_read_data_addr > 0x8FFF)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("x_read_data_addr(0x%x) is not correct!\n", x_read_data_addr)); + PHYDM_DBG(dm, DBG_TXBF, "x_read_data_addr(0x%x) is not correct!\n", x_read_data_addr); return; } /* Read data */ for (i = 0; i < data_len; i++) - *(data + i) = odm_read_2byte(p_dm_odm, x_read_data_addr + i); + *(data + i) = odm_read_2byte(dm, x_read_data_addr + i); } #endif void hal_txbf_8814a_get_tx_rate( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_entry; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u32 tx_rpt_data = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *entry; + struct ra_table *ra_tab = &dm->dm_ra_table; + struct cmn_sta_info *sta = NULL; u8 data_rate = 0xFF; + u8 macid = 0; - p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); + entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]); + macid = (u8)entry->mac_id; - data_rate = p_ra_table->link_tx_rate[(u8)p_entry->mac_id]; - data_rate &= 0x7f; /*Bit7 indicates SGI*/ - - p_beam_info->tx_bf_data_rate = data_rate; + sta = dm->phydm_sta_info[macid]; + + if (is_sta_active(sta)) { + + data_rate = (sta->ra_info.curr_tx_rate) & 0x7f; /*Bit7 indicates SGI*/ + beam_info->tx_bf_data_rate = data_rate; + } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] p_dm_odm->tx_bf_data_rate = 0x%x\n", __func__, p_beam_info->tx_bf_data_rate)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] dm->tx_bf_data_rate = 0x%x\n", __func__, beam_info->tx_bf_data_rate); } void hal_txbf_8814a_reset_tx_path( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if DEV_BUS_TYPE == RT_USB_INTERFACE - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; struct _RT_BEAMFORMEE_ENTRY beamformee_entry; u8 nr_index = 0, tx_ss = 0; if (idx < BEAMFORMEE_ENTRY_NUM) - beamformee_entry = p_beamforming_info->beamformee_entry[idx]; + beamformee_entry = beamforming_info->beamformee_entry[idx]; else return; - if ((p_beamforming_info->last_usb_hub) != (*p_dm_odm->hub_usb_mode)) { - nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), beamformee_entry.comp_steering_num_of_bfer); + if ((beamforming_info->last_usb_hub) != (*dm->hub_usb_mode)) { + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer); - if (*p_dm_odm->hub_usb_mode == 2) { - if (p_dm_odm->rf_type == ODM_4T4R) + if (*dm->hub_usb_mode == 2) { + if (dm->rf_type == RF_4T4R) tx_ss = 0xf; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) tx_ss = 0xe; else tx_ss = 0x6; - } else if (*p_dm_odm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/ + } else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/ tx_ss = 0x6; else tx_ss = 0x6; if (tx_ss == 0xf) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0); } else if (tx_ss == 0xe) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0); } else if (tx_ss == 0x6) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360); } if (idx == 0) { @@ -185,15 +190,15 @@ hal_txbf_8814a_reset_tx_path( break; case 1: /*Nsts = 2 BC*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ break; case 2: /*Nsts = 3 BCD*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ break; default: /*nr>3, same as Case 3*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ break; } } else { @@ -202,20 +207,20 @@ hal_txbf_8814a_reset_tx_path( break; case 1: /*Nsts = 2 BC*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ break; case 2: /*Nsts = 3 BCD*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ break; default: /*nr>3, same as Case 3*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ break; } } - p_beamforming_info->last_usb_hub = *p_dm_odm->hub_usb_mode; + beamforming_info->last_usb_hub = *dm->hub_usb_mode; } else return; #endif @@ -224,19 +229,19 @@ hal_txbf_8814a_reset_tx_path( u8 hal_txbf_8814a_get_ntx( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 ntx = 0, tx_ss = 3; #if DEV_BUS_TYPE == RT_USB_INTERFACE - tx_ss = *p_dm_odm->hub_usb_mode; + tx_ss = *dm->hub_usb_mode; #endif if (tx_ss == 3 || tx_ss == 2) { - if (p_dm_odm->rf_type == ODM_4T4R) + if (dm->rf_type == RF_4T4R) ntx = 3; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) ntx = 2; else ntx = 1; @@ -245,70 +250,70 @@ hal_txbf_8814a_get_ntx( else ntx = 1; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ntx = %d\n", __func__, ntx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ntx = %d\n", __func__, ntx); return ntx; } u8 hal_txbf_8814a_get_nrx( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 nrx = 0; - if (p_dm_odm->rf_type == ODM_4T4R) + if (dm->rf_type == RF_4T4R) nrx = 3; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) nrx = 2; - else if (p_dm_odm->rf_type == ODM_2T2R) + else if (dm->rf_type == RF_2T2R) nrx = 1; - else if (p_dm_odm->rf_type == ODM_2T3R) + else if (dm->rf_type == RF_2T3R) nrx = 2; - else if (p_dm_odm->rf_type == ODM_2T4R) + else if (dm->rf_type == RF_2T4R) nrx = 3; - else if (p_dm_odm->rf_type == ODM_1T1R) + else if (dm->rf_type == RF_1T1R) nrx = 0; - else if (p_dm_odm->rf_type == ODM_1T2R) + else if (dm->rf_type == RF_1T2R) nrx = 1; else nrx = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] nrx = %d\n", __func__, nrx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] nrx = %d\n", __func__, nrx); return nrx; } void hal_txbf_8814a_rf_mode( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beamforming_info, + void *dm_void, + struct _RT_BEAMFORMING_INFO *beamforming_info, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i, nr_index = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 nr_index = 0; u8 tx_ss = 3; /*default use 3 Tx*/ struct _RT_BEAMFORMEE_ENTRY beamformee_entry; if (idx < BEAMFORMEE_ENTRY_NUM) - beamformee_entry = p_beamforming_info->beamformee_entry[idx]; + beamformee_entry = beamforming_info->beamformee_entry[idx]; else return; - nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), beamformee_entry.comp_steering_num_of_bfer); + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer); - if (p_dm_odm->rf_type == ODM_1T1R) + if (dm->rf_type == RF_1T1R) return; - if (p_beamforming_info->beamformee_su_cnt > 0) { + if (beamforming_info->beamformee_su_cnt > 0) { #if DEV_BUS_TYPE == RT_USB_INTERFACE - p_beamforming_info->last_usb_hub = *p_dm_odm->hub_usb_mode; - tx_ss = *p_dm_odm->hub_usb_mode; + beamforming_info->last_usb_hub = *dm->hub_usb_mode; + tx_ss = *dm->hub_usb_mode; #endif if (tx_ss == 3 || tx_ss == 2) { - if (p_dm_odm->rf_type == ODM_4T4R) + if (dm->rf_type == RF_4T4R) tx_ss = 0xf; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) tx_ss = 0xe; else tx_ss = 0x6; @@ -318,19 +323,19 @@ hal_txbf_8814a_rf_mode( tx_ss = 0x6; if (tx_ss == 0xf) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0); } else if (tx_ss == 0xe) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0); } else if (tx_ss == 0x6) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360); } /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*if Nsts > Nc don't apply V matrix*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*if Nsts > Nc don't apply V matrix*/ if (idx == 0) { switch (nr_index) { @@ -338,15 +343,15 @@ hal_txbf_8814a_rf_mode( break; case 1: /*Nsts = 2 BC*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ break; case 2: /*Nsts = 3 BCD*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ break; default: /*nr>3, same as Case 3*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ break; } @@ -356,93 +361,93 @@ hal_txbf_8814a_rf_mode( break; case 1: /*Nsts = 2 BC*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ break; case 2: /*Nsts = 3 BCD*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ break; default: /*nr>3, same as Case 3*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ break; } } } - if ((p_beamforming_info->beamformee_su_cnt == 0) && (p_beamforming_info->beamformer_su_cnt == 0)) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360); + if ((beamforming_info->beamformee_su_cnt == 0) && (beamforming_info->beamformer_su_cnt == 0)) { + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360); } } #if 0 void hal_txbf_8814a_download_ndpa( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 u1b_tmp = 0, tmp_reg422 = 0; u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; u16 head_page = 0x7FE; boolean is_send_beacon = false; u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + void *adapter = dm->adapter; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true; + *dm->is_fw_dw_rsvd_page_in_progress = true; #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy); + phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy); /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8814A + 1); - odm_write_1byte(p_dm_odm, REG_CR_8814A + 1, (u1b_tmp | BIT(0))); + u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1); + odm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp | BIT(0))); /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2); - odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422 & (~BIT(6))); + tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422 & (~BIT(6))); if (tmp_reg422 & BIT(6)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: There is an adapter is sending beacon.\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s: There is an adapter is sending beacon.\n", __func__); is_send_beacon = true; } /*0x204[11:0] Beacon Head for TXDMA*/ - odm_write_2byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A, head_page); + odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, head_page); do { /*Clear beacon valid check bit.*/ - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1); - odm_write_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7))); + bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1); + odm_write_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7))); /*download NDPA rsvd page.*/ if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) - beamforming_send_vht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE); else - beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); /*check rsvd page download OK.*/ - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1); + bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1); count = 0; while (!(bcn_valid_reg & BIT(7)) && count < 20) { count++; ODM_delay_ms(10); - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 2); + bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 2); } dl_bcn_count++; } while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5); if (!(bcn_valid_reg & BIT(7))) - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n", __func__); /*0x204[11:0] Beacon Head for TXDMA*/ - odm_write_2byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy); + odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy); /*To make sure that if there exists an adapter which would like to send beacon.*/ /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ @@ -450,37 +455,37 @@ hal_txbf_8814a_download_ndpa( /*the beacon cannot be sent by HW.*/ /*2010.06.23. Added by tynli.*/ if (is_send_beacon) - odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422); /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8814A + 1); - odm_write_1byte(p_dm_odm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0)))); + u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1); + odm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0)))); p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false; + *dm->is_fw_dw_rsvd_page_in_progress = false; #endif } void hal_txbf_8814a_fw_txbf_cmd( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 idx, period = 0; u8 PageNum0 = 0xFF, PageNum1 = 0xFF; u8 u1_tx_bf_parm[3] = {0}; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (p_beam_info->beamformee_entry[idx].is_sound) { + if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (beam_info->beamformee_entry[idx].is_sound) { PageNum0 = 0xFE; PageNum1 = 0x07; - period = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + period = (u8)(beam_info->beamformee_entry[idx].sound_period); } else if (PageNum0 == 0xFF) { PageNum0 = 0xFF; /*stop sounding*/ PageNum1 = 0x0F; @@ -491,47 +496,47 @@ hal_txbf_8814a_fw_txbf_cmd( u1_tx_bf_parm[0] = PageNum0; u1_tx_bf_parm[1] = PageNum1; u1_tx_bf_parm[2] = period; - odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); + odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, - ("[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__, PageNum0, PageNum1, period)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__, PageNum0, PageNum1, period); } #endif void hal_txbf_8814a_enter( - void *p_dm_void, + void *dm_void, u8 bfer_bfee_idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; u8 bfee_idx = (bfer_bfee_idx & 0xF); - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; struct _RT_BEAMFORMEE_ENTRY beamformee_entry; struct _RT_BEAMFORMER_ENTRY beamformer_entry; u16 sta_id = 0, csi_param = 0; u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_idx, bfee_idx)); - odm_set_mac_reg(p_dm_odm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202); + PHYDM_DBG(dm, DBG_TXBF, "[%s] bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_idx, bfee_idx); + odm_set_mac_reg(dm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202); - if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { - beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx]; + if ((beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { + beamformer_entry = beamforming_info->beamformer_entry[bfer_idx]; /*Sounding protocol control*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A, 0xDB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xDB); /*MAC address/Partial AID of Beamformer*/ if (bfer_idx == 0) { for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]); + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]); } else { for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]); + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]); } /*CSI report parameters of Beamformer*/ - nc_index = hal_txbf_8814a_get_nrx(p_dm_odm); /*for 8814A nrx = 3(4 ant), min=0(1 ant)*/ + nc_index = hal_txbf_8814a_get_nrx(dm); /*for 8814A nrx = 3(4 ant), min=0(1 ant)*/ nr_index = beamformer_entry.num_of_sounding_dim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ grouping = 0; @@ -547,42 +552,42 @@ hal_txbf_8814a_enter( csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index)); if (bfer_idx == 0) - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param); else - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param); /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A + 3, 0x40); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A + 3, 0x40); } - if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { - beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx]; + if ((beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { + beamformee_entry = beamforming_info->beamformee_entry[bfee_idx]; - hal_txbf_8814a_rf_mode(p_dm_odm, p_beamforming_info, bfee_idx); + hal_txbf_8814a_rf_mode(dm, beamforming_info, bfee_idx); - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) sta_id = beamformee_entry.mac_id; else sta_id = beamformee_entry.p_aid; /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ if (bfee_idx == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, sta_id); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_TXBF_CTRL_8814A, sta_id); + odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7)); } else - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12)); + odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12)); /*CSI report parameters of Beamformee*/ if (bfee_idx == 0) { /*Get BIT24 & BIT25*/ - u8 tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3; + u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3; - odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9)); + odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9)); } else - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/ + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/ - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); } } @@ -590,18 +595,18 @@ hal_txbf_8814a_enter( void hal_txbf_8814a_leave( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; struct _RT_BEAMFORMER_ENTRY beamformer_entry; struct _RT_BEAMFORMEE_ENTRY beamformee_entry; if (idx < BEAMFORMER_ENTRY_NUM) { - beamformer_entry = p_beamforming_info->beamformer_entry[idx]; - beamformee_entry = p_beamforming_info->beamformee_entry[idx]; + beamformer_entry = beamforming_info->beamformer_entry[idx]; + beamformee_entry = beamforming_info->beamformee_entry[idx]; } else return; @@ -610,55 +615,55 @@ hal_txbf_8814a_leave( /*Clear Associated Bfmee Sel*/ if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A, 0xD8); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xD8); if (idx == 0) { - odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A, 0); + odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, 0); } else { - odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0); + odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0); } } if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { - hal_txbf_8814a_rf_mode(p_dm_odm, p_beamforming_info, idx); + hal_txbf_8814a_rf_mode(dm, beamforming_info, idx); if (idx == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, 0x0); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7)); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0); + odm_write_2byte(dm, REG_TXBF_CTRL_8814A, 0x0); + odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0); } else { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12)); + odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12)); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60); } } } void hal_txbf_8814a_status( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u16 beam_ctrl_val, tmp_val; u32 beam_ctrl_reg; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; struct _RT_BEAMFORMEE_ENTRY beamform_entry; if (idx < BEAMFORMEE_ENTRY_NUM) - beamform_entry = p_beamforming_info->beamformee_entry[idx]; + beamform_entry = beamforming_info->beamformee_entry[idx]; else return; - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) beam_ctrl_val = beamform_entry.mac_id; else beam_ctrl_val = beamform_entry.p_aid; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, beamform_entry.beamform_entry_state = %d", __func__, beamform_entry.beamform_entry_state)); + PHYDM_DBG(dm, DBG_TXBF, "@%s, beamform_entry.beamform_entry_state = %d", __func__, beamform_entry.beamform_entry_state); if (idx == 0) beam_ctrl_reg = REG_TXBF_CTRL_8814A; @@ -667,7 +672,7 @@ hal_txbf_8814a_status( beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); } - if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beamforming_info->apply_v_matrix == true)) { + if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (beamforming_info->apply_v_matrix == true)) { if (beamform_entry.sound_bw == CHANNEL_WIDTH_20) beam_ctrl_val |= BIT(9); else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40) @@ -675,14 +680,14 @@ hal_txbf_8814a_status( else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80) beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11)); } else { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", __func__); beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); } - odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val); + odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val); /*disable NDP packet use beamforming */ - tmp_val = odm_read_2byte(p_dm_odm, REG_TXBF_CTRL_8814A); - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15)); + tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8814A); + odm_write_2byte(dm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15)); } @@ -692,21 +697,21 @@ hal_txbf_8814a_status( void hal_txbf_8814a_fw_txbf( - void *p_dm_void, + void *dm_void, u8 idx ) { #if 0 - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) - hal_txbf_8814a_download_ndpa(p_dm_odm, idx); + hal_txbf_8814a_download_ndpa(dm, idx); - hal_txbf_8814a_fw_txbf_cmd(p_dm_odm); + hal_txbf_8814a_fw_txbf_cmd(dm); #endif } diff --git a/hal/phydm/txbf/haltxbf8814a.h b/hal/phydm/txbf/haltxbf8814a.h index b070564..2612ad2 100644 --- a/hal/phydm/txbf/haltxbf8814a.h +++ b/hal/phydm/txbf/haltxbf8814a.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __HAL_TXBF_8814A_H__ #define __HAL_TXBF_8814A_H__ @@ -20,84 +30,84 @@ boolean phydm_beamforming_set_iqgen_8814A( - void *p_dm_void + void *dm_void ); void hal_txbf_8814a_set_ndpa_rate( - void *p_dm_void, + void *dm_void, u8 BW, u8 rate ); u8 hal_txbf_8814a_get_ntx( - void *p_dm_void + void *dm_void ); void hal_txbf_8814a_enter( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_8814a_leave( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_8814a_status( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_8814a_reset_tx_path( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_8814a_get_tx_rate( - void *p_dm_void + void *dm_void ); void hal_txbf_8814a_fw_txbf( - void *p_dm_void, + void *dm_void, u8 idx ); #else -#define hal_txbf_8814a_set_ndpa_rate(p_dm_void, BW, rate) -#define hal_txbf_8814a_get_ntx(p_dm_void) 0 -#define hal_txbf_8814a_enter(p_dm_void, idx) -#define hal_txbf_8814a_leave(p_dm_void, idx) -#define hal_txbf_8814a_status(p_dm_void, idx) -#define hal_txbf_8814a_reset_tx_path(p_dm_void, idx) -#define hal_txbf_8814a_get_tx_rate(p_dm_void) -#define hal_txbf_8814a_fw_txbf(p_dm_void, idx) -#define phydm_beamforming_set_iqgen_8814A(p_dm_void) 0 +#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_8814a_get_ntx(dm_void) 0 +#define hal_txbf_8814a_enter(dm_void, idx) +#define hal_txbf_8814a_leave(dm_void, idx) +#define hal_txbf_8814a_status(dm_void, idx) +#define hal_txbf_8814a_reset_tx_path(dm_void, idx) +#define hal_txbf_8814a_get_tx_rate(dm_void) +#define hal_txbf_8814a_fw_txbf(dm_void, idx) +#define phydm_beamforming_set_iqgen_8814A(dm_void) 0 #endif #else -#define hal_txbf_8814a_set_ndpa_rate(p_dm_void, BW, rate) -#define hal_txbf_8814a_get_ntx(p_dm_void) 0 -#define hal_txbf_8814a_enter(p_dm_void, idx) -#define hal_txbf_8814a_leave(p_dm_void, idx) -#define hal_txbf_8814a_status(p_dm_void, idx) -#define hal_txbf_8814a_reset_tx_path(p_dm_void, idx) -#define hal_txbf_8814a_get_tx_rate(p_dm_void) -#define hal_txbf_8814a_fw_txbf(p_dm_void, idx) -#define phydm_beamforming_set_iqgen_8814A(p_dm_void) 0 +#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_8814a_get_ntx(dm_void) 0 +#define hal_txbf_8814a_enter(dm_void, idx) +#define hal_txbf_8814a_leave(dm_void, idx) +#define hal_txbf_8814a_status(dm_void, idx) +#define hal_txbf_8814a_reset_tx_path(dm_void, idx) +#define hal_txbf_8814a_get_tx_rate(dm_void) +#define hal_txbf_8814a_fw_txbf(dm_void, idx) +#define phydm_beamforming_set_iqgen_8814A(dm_void) 0 #endif #endif diff --git a/hal/phydm/txbf/haltxbf8822b.c b/hal/phydm/txbf/haltxbf8822b.c index 56ad3e7..75e08b5 100644 --- a/hal/phydm/txbf/haltxbf8822b.c +++ b/hal/phydm/txbf/haltxbf8822b.c @@ -27,31 +27,31 @@ u8 hal_txbf_8822b_get_ntx( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 ntx = 0; #if DEV_BUS_TYPE == RT_USB_INTERFACE - if (p_dm_odm->support_interface == ODM_ITRF_USB) { - if (*p_dm_odm->hub_usb_mode == 2) {/*USB3.0*/ - if (p_dm_odm->rf_type == ODM_4T4R) + if (dm->support_interface == ODM_ITRF_USB) { + if (*dm->hub_usb_mode == 2) {/*USB3.0*/ + if (dm->rf_type == RF_4T4R) ntx = 3; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) ntx = 2; else ntx = 1; - } else if (*p_dm_odm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/ + } else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/ ntx = 1; else ntx = 1; } else #endif { - if (p_dm_odm->rf_type == ODM_4T4R) + if (dm->rf_type == RF_4T4R) ntx = 3; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) ntx = 2; else ntx = 1; @@ -63,25 +63,25 @@ hal_txbf_8822b_get_ntx( u8 hal_txbf_8822b_get_nrx( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 nrx = 0; - if (p_dm_odm->rf_type == ODM_4T4R) + if (dm->rf_type == RF_4T4R) nrx = 3; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) nrx = 2; - else if (p_dm_odm->rf_type == ODM_2T2R) + else if (dm->rf_type == RF_2T2R) nrx = 1; - else if (p_dm_odm->rf_type == ODM_2T3R) + else if (dm->rf_type == RF_2T3R) nrx = 2; - else if (p_dm_odm->rf_type == ODM_2T4R) + else if (dm->rf_type == RF_2T4R) nrx = 3; - else if (p_dm_odm->rf_type == ODM_1T1R) + else if (dm->rf_type == RF_1T1R) nrx = 0; - else if (p_dm_odm->rf_type == ODM_1T2R) + else if (dm->rf_type == RF_1T2R) nrx = 1; else nrx = 0; @@ -93,82 +93,82 @@ hal_txbf_8822b_get_nrx( /***************SU & MU BFee Entry********************/ void hal_txbf_8822b_rf_mode( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beamforming_info, + void *dm_void, + struct _RT_BEAMFORMING_INFO *beamforming_info, u8 idx ) { #if 0 - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i, nr_index = 0; boolean is_self_beamformer = false; boolean is_self_beamformee = false; struct _RT_BEAMFORMEE_ENTRY beamformee_entry; if (idx < BEAMFORMEE_ENTRY_NUM) - beamformee_entry = p_beamforming_info->beamformee_entry[idx]; + beamformee_entry = beamforming_info->beamformee_entry[idx]; else return; - if (p_dm_odm->rf_type == ODM_1T1R) + if (dm->rf_type == RF_1T1R) return; - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_welut_jaguar, 0x80000, 0x1); + for (i = RF_PATH_A; i < RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x1); /*RF mode table write enable*/ } - if ((p_beamforming_info->beamformee_su_cnt > 0) || (p_beamforming_info->beamformee_mu_cnt > 0)) { - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_mode_table_addr, 0xfffff, 0x18000); + if ((beamforming_info->beamformee_su_cnt > 0) || (beamforming_info->beamformee_mu_cnt > 0)) { + for (i = RF_PATH_A; i < RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_addr, 0xfffff, 0x18000); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_mode_table_data0, 0xfffff, 0xBE77F); + odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data0, 0xfffff, 0xBE77F); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_mode_table_data1, 0xfffff, 0x226BF); + odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data1, 0xfffff, 0x226BF); /*Enable TXIQGEN in RX mode*/ } - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, rf_mode_table_data1, 0xfffff, 0xE26BF); + odm_set_rf_reg(dm, RF_PATH_A, rf_mode_table_data1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ } - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_welut_jaguar, 0x80000, 0x0); + for (i = RF_PATH_A; i < RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x0); /*RF mode table write disable*/ } - if (p_beamforming_info->beamformee_su_cnt > 0) { + if (beamforming_info->beamformee_su_cnt > 0) { /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ if (idx == 0) { /*Nsts = 2 AB*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); - /*odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430);*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + /*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430);*/ } else {/*IDX =1*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); - /*odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430;*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + /*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430;*/ } } else { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*2SS by path-A,B*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*2SS by path-A,B*/ } - if (p_beamforming_info->beamformee_mu_cnt > 0) { + if (beamforming_info->beamformee_mu_cnt > 0) { /*MU STAs share the common setting*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); } #endif } #if 0 void hal_txbf_8822b_download_ndpa( - struct _ADAPTER *adapter, + void *adapter, u8 idx ) { @@ -176,13 +176,13 @@ hal_txbf_8822b_download_ndpa( u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; u16 head_page = 0x7FE; boolean is_send_beacon = false; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ - struct _RT_BEAMFORMING_INFO *p_beam_info = GET_BEAMFORM_INFO(adapter); - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + struct _RT_BEAMFORMING_INFO *beam_info = GET_BEAMFORM_INFO(adapter); + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; - p_hal_data->is_fw_dw_rsvd_page_in_progress = true; - phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy); + hal_data->is_fw_dw_rsvd_page_in_progress = true; + phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy); /*Set REG_CR bit 8. DMA beacon by SW.*/ u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1); @@ -208,9 +208,9 @@ hal_txbf_8822b_download_ndpa( /*download NDPA rsvd page.*/ if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) - beamforming_send_vht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE); else - beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); /*check rsvd page download OK.*/ bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); @@ -244,27 +244,27 @@ hal_txbf_8822b_download_ndpa( p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; - p_hal_data->is_fw_dw_rsvd_page_in_progress = false; + hal_data->is_fw_dw_rsvd_page_in_progress = false; } void hal_txbf_8822b_fw_txbf_cmd( - struct _ADAPTER *adapter + void *adapter ) { u8 idx, period = 0; u8 PageNum0 = 0xFF, PageNum1 = 0xFF; u8 u1_tx_bf_parm[3] = {0}; - PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); - struct _RT_BEAMFORMING_INFO *p_beam_info = GET_BEAMFORM_INFO(adapter); + PMGNT_INFO mgnt_info = &(adapter->MgntInfo); + struct _RT_BEAMFORMING_INFO *beam_info = GET_BEAMFORM_INFO(adapter); for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (p_beam_info->beamformee_entry[idx].is_sound) { + if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (beam_info->beamformee_entry[idx].is_sound) { PageNum0 = 0xFE; PageNum1 = 0x07; - period = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + period = (u8)(beam_info->beamformee_entry[idx].sound_period); } else if (PageNum0 == 0xFF) { PageNum0 = 0xFF; /*stop sounding*/ PageNum1 = 0x0F; @@ -284,64 +284,64 @@ hal_txbf_8822b_fw_txbf_cmd( #if 0 void hal_txbf_8822b_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 u1b_tmp; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + void *adapter = dm->adapter; - odm_set_bb_reg(p_dm_odm, 0x14c0, BIT(16), 1); /*Enable P1 aggr new packet according to P0 transfer time*/ - odm_set_bb_reg(p_dm_odm, 0x14c0, BIT(15) | BIT14 | BIT13 | BIT12, 10); /*MU Retry Limit*/ - odm_set_bb_reg(p_dm_odm, 0x14c0, BIT(7), 0); /*Disable Tx MU-MIMO until sounding done*/ - odm_set_bb_reg(p_dm_odm, 0x14c0, 0x3F, 0); /* Clear validity of MU STAs */ - odm_write_1byte(p_dm_odm, 0x167c, 0x70); /*MU-MIMO Option as default value*/ - odm_write_2byte(p_dm_odm, 0x1680, 0); /*MU-MIMO Control as default value*/ + odm_set_bb_reg(dm, 0x14c0, BIT(16), 1); /*Enable P1 aggr new packet according to P0 transfer time*/ + odm_set_bb_reg(dm, 0x14c0, BIT(15) | BIT14 | BIT13 | BIT12, 10); /*MU Retry Limit*/ + odm_set_bb_reg(dm, 0x14c0, BIT(7), 0); /*Disable Tx MU-MIMO until sounding done*/ + odm_set_bb_reg(dm, 0x14c0, 0x3F, 0); /* Clear validity of MU STAs */ + odm_write_1byte(dm, 0x167c, 0x70); /*MU-MIMO Option as default value*/ + odm_write_2byte(dm, 0x1680, 0); /*MU-MIMO Control as default value*/ /* Set MU NDPA rate & BW source */ /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ - u1b_tmp = odm_read_1byte(p_dm_odm, 0x42C); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8822B, (u1b_tmp | BIT(6))); + u1b_tmp = odm_read_1byte(dm, 0x42C); + odm_write_1byte(dm, REG_TXBF_CTRL_8822B, (u1b_tmp | BIT(6))); /* 0x45F[7:0] = 0x10 (rate=OFDM_6M, BW20) */ - odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8822B, 0x10); + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, 0x10); /*Temp Settings*/ - odm_set_bb_reg(p_dm_odm, 0x6DC, 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/ - odm_set_bb_reg(p_dm_odm, 0x1C94, MASKDWORD, 0xAFFFAFFF); /*Grouping bitmap parameters*/ + odm_set_bb_reg(dm, 0x6DC, 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/ + odm_set_bb_reg(dm, 0x1C94, MASKDWORD, 0xAFFFAFFF); /*Grouping bitmap parameters*/ /* Init HW variable */ - p_beamforming_info->reg_mu_tx_ctrl = odm_read_4byte(p_dm_odm, 0x14c0); + beamforming_info->reg_mu_tx_ctrl = odm_read_4byte(dm, 0x14c0); - if (p_dm_odm->rf_type == ODM_2T2R) { /*2T2R*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: rf_type is 2T2R\n", __func__)); - config_phydm_trx_mode_8822b(p_dm_odm, (enum odm_rf_path_e)3, (enum odm_rf_path_e)3, true);/*Tx2path*/ + if (dm->rf_type == RF_2T2R) { /*2T2R*/ + PHYDM_DBG(dm, DBG_TXBF, "%s: rf_type is 2T2R\n", __func__); + config_phydm_trx_mode_8822b(dm, (enum bb_path)3, (enum bb_path)3, true);/*Tx2path*/ } #if (OMNIPEEK_SNIFFER_ENABLED == 1) /* Config HW to receive packet on the user position from registry for sniffer mode. */ - /* odm_set_bb_reg(p_dm_odm, 0xB00, BIT(9), 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */ - odm_set_bb_reg(p_dm_odm, 0xB54, BIT(30), 1); /* RegB54[30] = 1 (force user position) */ - odm_set_bb_reg(p_dm_odm, 0xB54, (BIT(29) | BIT28), adapter->MgntInfo.sniff_user_position); /* RegB54[29:28] = user position (0~3) */ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Set adapter->MgntInfo.sniff_user_position=%#X\n", adapter->MgntInfo.sniff_user_position)); + /* odm_set_bb_reg(dm, 0xB00, BIT(9), 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */ + odm_set_bb_reg(dm, 0xB54, BIT(30), 1); /* RegB54[30] = 1 (force user position) */ + odm_set_bb_reg(dm, 0xB54, (BIT(29) | BIT28), adapter->MgntInfo.sniff_user_position); /* RegB54[29:28] = user position (0~3) */ + PHYDM_DBG(dm, DBG_TXBF, "Set adapter->MgntInfo.sniff_user_position=%#X\n", adapter->MgntInfo.sniff_user_position); #endif } #endif void hal_txbf_8822b_enter( - void *p_dm_void, + void *dm_void, u8 bfer_bfee_idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; u8 bfee_idx = (bfer_bfee_idx & 0xF); u16 csi_param = 0; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry; - struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry; + struct _RT_BEAMFORMER_ENTRY *beamformer_entry; u16 value16, sta_id = 0; u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; u32 gid_valid, user_position_l, user_position_h; @@ -352,40 +352,40 @@ hal_txbf_8822b_enter( RT_DISP(FBEAM, FBEAM_FUN, ("%s: bfer_bfee_idx=%d, bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_bfee_idx, bfer_idx, bfee_idx)); /*************SU BFer Entry Init*************/ - if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { - p_beamformer_entry = &p_beamforming_info->beamformer_entry[bfer_idx]; - p_beamformer_entry->is_mu_ap = false; + if ((beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { + beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx]; + beamformer_entry->is_mu_ap = false; /*Sounding protocol control*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB); for (i = 0; i < MAX_BEAMFORMER_SU; i++) { - if ((p_beamforming_info->beamformer_su_reg_maping & BIT(i)) == 0) { - p_beamforming_info->beamformer_su_reg_maping |= BIT(i); - p_beamformer_entry->su_reg_index = i; + if ((beamforming_info->beamformer_su_reg_maping & BIT(i)) == 0) { + beamforming_info->beamformer_su_reg_maping |= BIT(i); + beamformer_entry->su_reg_index = i; break; } } /*MAC address/Partial AID of Beamformer*/ - if (p_beamformer_entry->su_reg_index == 0) { + if (beamformer_entry->su_reg_index == 0) { for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), p_beamformer_entry->mac_addr[i]); + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]); } else { for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8822B + i), p_beamformer_entry->mac_addr[i]); + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8822B + i), beamformer_entry->mac_addr[i]); } /*CSI report parameters of Beamformer*/ - nc_index = hal_txbf_8822b_get_nrx(p_dm_odm); /*for 8814A nrx = 3(4 ant), min=0(1 ant)*/ - nr_index = p_beamformer_entry->num_of_sounding_dim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ + nc_index = hal_txbf_8822b_get_nrx(dm); /*for 8814A nrx = 3(4 ant), min=0(1 ant)*/ + nr_index = beamformer_entry->num_of_sounding_dim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ grouping = 0; /*for ac = 1, for n = 3*/ - if (p_beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) + if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) codebookinfo = 1; - else if (p_beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT) + else if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT) codebookinfo = 3; coefficientsize = 3; @@ -393,28 +393,28 @@ hal_txbf_8822b_enter( csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index)); if (bfer_idx == 0) - odm_write_2byte(p_dm_odm, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param); + odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param); else - odm_write_2byte(p_dm_odm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, csi_param); + odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, csi_param); /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B + 3, 0x70); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B + 3, 0x70); } /*************SU BFee Entry Init*************/ - if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { - p_beamformee_entry = &p_beamforming_info->beamformee_entry[bfee_idx]; + if ((beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { + p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx]; p_beamformee_entry->is_mu_sta = false; - hal_txbf_8822b_rf_mode(p_dm_odm, p_beamforming_info, bfee_idx); + hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx); - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) sta_id = p_beamformee_entry->mac_id; else sta_id = p_beamformee_entry->p_aid; for (i = 0; i < MAX_BEAMFORMEE_SU; i++) { - if ((p_beamforming_info->beamformee_su_reg_maping & BIT(i)) == 0) { - p_beamforming_info->beamformee_su_reg_maping |= BIT(i); + if ((beamforming_info->beamformee_su_reg_maping & BIT(i)) == 0) { + beamforming_info->beamformee_su_reg_maping |= BIT(i); p_beamformee_entry->su_reg_index = i; break; } @@ -422,83 +422,83 @@ hal_txbf_8822b_enter( /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ if (p_beamformee_entry->su_reg_index == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B, sta_id); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_TXBF_CTRL_8822B, sta_id); + odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7)); } else - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B + 2, sta_id | BIT(14) | BIT(15) | BIT(12)); + odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, sta_id | BIT(14) | BIT(15) | BIT(12)); /*CSI report parameters of Beamformee*/ if (p_beamformee_entry->su_reg_index == 0) { /*Get BIT24 & BIT25*/ - u8 tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3) & 0x3; + u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3) & 0x3; - odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B, sta_id | BIT(9)); + odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, sta_id | BIT(9)); } else - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, sta_id | 0xE200); /*Set BIT25*/ + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, sta_id | 0xE200); /*Set BIT25*/ - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); } /*************MU BFer Entry Init*************/ - if ((p_beamforming_info->beamformer_mu_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { - p_beamformer_entry = &p_beamforming_info->beamformer_entry[bfer_idx]; - p_beamforming_info->mu_ap_index = bfer_idx; - p_beamformer_entry->is_mu_ap = true; + if ((beamforming_info->beamformer_mu_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { + beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx]; + beamforming_info->mu_ap_index = bfer_idx; + beamformer_entry->is_mu_ap = true; for (i = 0; i < 8; i++) - p_beamformer_entry->gid_valid[i] = 0; + beamformer_entry->gid_valid[i] = 0; for (i = 0; i < 16; i++) - p_beamformer_entry->user_position[i] = 0; + beamformer_entry->user_position[i] = 0; /*Sounding protocol control*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB); /* MAC address */ for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), p_beamformer_entry->mac_addr[i]); + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]); /* Set partial AID */ - odm_write_2byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8822B + 6), p_beamformer_entry->p_aid); + odm_write_2byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + 6), beamformer_entry->p_aid); /* Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/ - u1b_tmp = odm_read_1byte(p_dm_odm, 0x1680); - u1b_tmp = (p_beamformer_entry->p_aid) & 0xFFF; - odm_write_1byte(p_dm_odm, 0x1680, u1b_tmp); + u1b_tmp = odm_read_1byte(dm, 0x1680); + u1b_tmp = (beamformer_entry->p_aid) & 0xFFF; + odm_write_1byte(dm, 0x1680, u1b_tmp); /* Set 80us for leaving ndp_rx_standby_state */ - odm_write_1byte(p_dm_odm, 0x71B, 0x50); + odm_write_1byte(dm, 0x71B, 0x50); /* Set 0x6A0[14] = 1 to accept action_no_ack */ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_RXFLTMAP0_8822B + 1); + u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1); u1b_tmp |= 0x40; - odm_write_1byte(p_dm_odm, REG_RXFLTMAP0_8822B + 1, u1b_tmp); + odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp); /* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_RXFLTMAP1_8822B); + u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP1_8822B); u1b_tmp |= 0x30; - odm_write_1byte(p_dm_odm, REG_RXFLTMAP1_8822B, u1b_tmp); + odm_write_1byte(dm, REG_RXFLTMAP1_8822B, u1b_tmp); /*CSI report parameters of Beamformer*/ - nc_index = hal_txbf_8822b_get_nrx(p_dm_odm); /* Depend on RF type */ + nc_index = hal_txbf_8822b_get_nrx(dm); /* Depend on RF type */ nr_index = 1; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ grouping = 0; /*no grouping*/ codebookinfo = 1; /*7 bit for psi, 9 bit for phi*/ coefficientsize = 0; /*This is nothing really matter*/ csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index)); - odm_write_2byte(p_dm_odm, 0x6F4, csi_param); + odm_write_2byte(dm, 0x6F4, csi_param); /*for B-cut*/ - odm_set_bb_reg(p_dm_odm, 0x6A0, BIT(20), 0); - odm_set_bb_reg(p_dm_odm, 0x688, BIT(20), 0); + odm_set_bb_reg(dm, 0x6A0, BIT(20), 0); + odm_set_bb_reg(dm, 0x688, BIT(20), 0); } /*************MU BFee Entry Init*************/ - if ((p_beamforming_info->beamformee_mu_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { - p_beamformee_entry = &p_beamforming_info->beamformee_entry[bfee_idx]; + if ((beamforming_info->beamformee_mu_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { + p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx]; p_beamformee_entry->is_mu_sta = true; for (i = 0; i < MAX_BEAMFORMEE_MU; i++) { - if ((p_beamforming_info->beamformee_mu_reg_maping & BIT(i)) == 0) { - p_beamforming_info->beamformee_mu_reg_maping |= BIT(i); + if ((beamforming_info->beamformee_mu_reg_maping & BIT(i)) == 0) { + beamforming_info->beamformee_mu_reg_maping |= BIT(i); p_beamformee_entry->mu_reg_index = i; break; } @@ -561,75 +561,75 @@ hal_txbf_8822b_enter( } /*Sounding protocol control*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB); /*select MU STA table*/ - p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); - p_beamforming_info->reg_mu_tx_ctrl |= (p_beamformee_entry->mu_reg_index << 8) & (BIT(8) | BIT(9) | BIT(10)); - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + beamforming_info->reg_mu_tx_ctrl |= (p_beamformee_entry->mu_reg_index << 8) & (BIT(8) | BIT(9) | BIT(10)); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); - odm_set_bb_reg(p_dm_odm, 0x14c4, MASKDWORD, 0); /*Reset gid_valid table*/ - odm_set_bb_reg(p_dm_odm, 0x14c8, MASKDWORD, user_position_l); - odm_set_bb_reg(p_dm_odm, 0x14cc, MASKDWORD, user_position_h); + odm_set_bb_reg(dm, 0x14c4, MASKDWORD, 0); /*Reset gid_valid table*/ + odm_set_bb_reg(dm, 0x14c8, MASKDWORD, user_position_l); + odm_set_bb_reg(dm, 0x14cc, MASKDWORD, user_position_h); /*set validity of MU STAs*/ - p_beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; - p_beamforming_info->reg_mu_tx_ctrl |= p_beamforming_info->beamformee_mu_reg_maping & 0x3F; - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; + beamforming_info->reg_mu_tx_ctrl |= beamforming_info->beamformee_mu_reg_maping & 0x3F; + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, reg_mu_tx_ctrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", - __func__, p_beamforming_info->reg_mu_tx_ctrl, user_position_l, user_position_h)); + PHYDM_DBG(dm, DBG_TXBF, "@%s, reg_mu_tx_ctrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, beamforming_info->reg_mu_tx_ctrl, user_position_l, user_position_h); - value16 = odm_read_2byte(p_dm_odm, mu_reg[p_beamformee_entry->mu_reg_index]); + value16 = odm_read_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index]); value16 &= 0xFE00; /*Clear PAID*/ value16 |= BIT(9); /*Enable MU BFee*/ value16 |= p_beamformee_entry->p_aid; - odm_write_2byte(p_dm_odm, mu_reg[p_beamformee_entry->mu_reg_index], value16); + odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], value16); /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3); + u1b_tmp = odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3); u1b_tmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/ - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3, u1b_tmp); + odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, u1b_tmp); /* Set NDPA to 6M*/ - odm_write_1byte(p_dm_odm, REG_NDPA_RATE_8822B, 0x4); + odm_write_1byte(dm, REG_NDPA_RATE_8822B, 0x4); - u1b_tmp = odm_read_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8822B); + u1b_tmp = odm_read_1byte(dm, REG_NDPA_OPT_CTRL_8822B); u1b_tmp &= 0xFC; /* Clear bit 0, 1*/ - odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8822B, u1b_tmp); + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, u1b_tmp); - u4b_tmp = odm_read_4byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B); + u4b_tmp = odm_read_4byte(dm, REG_SND_PTCL_CTRL_8822B); u4b_tmp = ((u4b_tmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202*/ - odm_write_4byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, u4b_tmp); + odm_write_4byte(dm, REG_SND_PTCL_CTRL_8822B, u4b_tmp); /* Set 0x6A0[14] = 1 to accept action_no_ack */ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_RXFLTMAP0_8822B + 1); + u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1); u1b_tmp |= 0x40; - odm_write_1byte(p_dm_odm, REG_RXFLTMAP0_8822B + 1, u1b_tmp); + odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp); /* End of MAC registers setting */ - hal_txbf_8822b_rf_mode(p_dm_odm, p_beamforming_info, bfee_idx); + hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx); #if (SUPPORT_MU_BF == 1) /*Special for plugfest*/ delay_ms(50); /* wait for 4-way handshake ending*/ - send_sw_vht_gid_mgnt_frame(p_dm_odm, p_beamformee_entry->mac_addr, bfee_idx); + send_sw_vht_gid_mgnt_frame(dm, p_beamformee_entry->mac_addr, bfee_idx); #endif - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); #if 1 { u32 ctrl_info_offset, index; /*Set Ctrl Info*/ - odm_write_2byte(p_dm_odm, 0x140, 0x660); + odm_write_2byte(dm, 0x140, 0x660); ctrl_info_offset = 0x8000 + 32 * p_beamformee_entry->mac_id; /*Reset Ctrl Info*/ for (index = 0; index < 8; index++) - odm_write_4byte(p_dm_odm, ctrl_info_offset + index * 4, 0); + odm_write_4byte(dm, ctrl_info_offset + index * 4, 0); - odm_write_4byte(p_dm_odm, ctrl_info_offset, (p_beamformee_entry->mu_reg_index + 1) << 16); - odm_write_1byte(p_dm_odm, 0x81, 0x80); /*RPTBUF ready*/ + odm_write_4byte(dm, ctrl_info_offset, (p_beamformee_entry->mu_reg_index + 1) << 16); + odm_write_1byte(dm, 0x81, 0x80); /*RPTBUF ready*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, mac_id = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n", - __func__, p_beamformee_entry->mac_id, ctrl_info_offset, p_beamformee_entry->mu_reg_index)); + PHYDM_DBG(dm, DBG_TXBF, "@%s, mac_id = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n", + __func__, p_beamformee_entry->mac_id, ctrl_info_offset, p_beamformee_entry->mu_reg_index); } #endif } @@ -639,19 +639,19 @@ hal_txbf_8822b_enter( void hal_txbf_8822b_leave( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY *beamformer_entry; struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry; u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; if (idx < BEAMFORMER_ENTRY_NUM) { - p_beamformer_entry = &p_beamforming_info->beamformer_entry[idx]; - p_beamformee_entry = &p_beamforming_info->beamformee_entry[idx]; + beamformer_entry = &beamforming_info->beamformer_entry[idx]; + p_beamformee_entry = &beamforming_info->beamformee_entry[idx]; } else return; @@ -659,56 +659,56 @@ hal_txbf_8822b_leave( /*Clear MAC address of Beamformer*/ /*Clear Associated Bfmee Sel*/ - if (p_beamformer_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) { - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, 0xD8); - if (p_beamformer_entry->is_mu_ap == 0) { /*SU BFer */ - if (p_beamformer_entry->su_reg_index == 0) { - odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8822B + 4, 0); - odm_write_2byte(p_dm_odm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0); + if (beamformer_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) { + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xD8); + if (beamformer_entry->is_mu_ap == 0) { /*SU BFer */ + if (beamformer_entry->su_reg_index == 0) { + odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B + 4, 0); + odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0); } else { - odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8822B + 4, 0); - odm_write_2byte(p_dm_odm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, 0); + odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B + 4, 0); + odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, 0); } - p_beamforming_info->beamformer_su_reg_maping &= ~(BIT(p_beamformer_entry->su_reg_index)); - p_beamformer_entry->su_reg_index = 0xFF; + beamforming_info->beamformer_su_reg_maping &= ~(BIT(beamformer_entry->su_reg_index)); + beamformer_entry->su_reg_index = 0xFF; } else { /*MU BFer */ /*set validity of MU STA0 and MU STA1*/ - p_beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); - odm_memory_set(p_dm_odm, p_beamformer_entry->gid_valid, 0, 8); - odm_memory_set(p_dm_odm, p_beamformer_entry->user_position, 0, 16); - p_beamformer_entry->is_mu_ap = false; + odm_memory_set(dm, beamformer_entry->gid_valid, 0, 8); + odm_memory_set(dm, beamformer_entry->user_position, 0, 16); + beamformer_entry->is_mu_ap = false; } } if (p_beamformee_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) { - hal_txbf_8822b_rf_mode(p_dm_odm, p_beamforming_info, idx); + hal_txbf_8822b_rf_mode(dm, beamforming_info, idx); if (p_beamformee_entry->is_mu_sta == 0) { /*SU BFee*/ if (p_beamformee_entry->su_reg_index == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B, 0x0); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7)); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0); + odm_write_2byte(dm, REG_TXBF_CTRL_8822B, 0x0); + odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0); } else { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B + 2, 0x0 | BIT(14) | BIT(15) | BIT(12)); + odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, 0x0 | BIT(14) | BIT(15) | BIT(12)); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, - odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2) & 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, + odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2) & 0x60); } - p_beamforming_info->beamformee_su_reg_maping &= ~(BIT(p_beamformee_entry->su_reg_index)); + beamforming_info->beamformee_su_reg_maping &= ~(BIT(p_beamformee_entry->su_reg_index)); p_beamformee_entry->su_reg_index = 0xFF; } else { /*MU BFee */ /*Disable sending NDPA & BF-rpt-poll to this BFee*/ - odm_write_2byte(p_dm_odm, mu_reg[p_beamformee_entry->mu_reg_index], 0); + odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], 0); /*set validity of MU STA*/ - p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(p_beamformee_entry->mu_reg_index)); - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(p_beamformee_entry->mu_reg_index)); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); p_beamformee_entry->is_mu_sta = false; - p_beamforming_info->beamformee_mu_reg_maping &= ~(BIT(p_beamformee_entry->mu_reg_index)); + beamforming_info->beamformee_mu_reg_maping &= ~(BIT(p_beamformee_entry->mu_reg_index)); p_beamformee_entry->mu_reg_index = 0xFF; } } @@ -718,84 +718,82 @@ hal_txbf_8822b_leave( /***********SU & MU BFee Entry Only when souding done****************/ void hal_txbf_8822b_status( - void *p_dm_void, + void *dm_void, u8 beamform_idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u16 beam_ctrl_val, tmp_val; u32 beam_ctrl_reg; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry; - boolean is_mu_sounding = p_beamforming_info->is_mu_sounding, is_bitmap_ready = false; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry; + boolean is_mu_sounding = beamforming_info->is_mu_sounding, is_bitmap_ready = false; u16 bitmap; u8 idx, gid, i; u8 id1, id0; u32 gid_valid[6] = {0}; - u32 user_position_lsb[6] = {0}; - u32 user_position_msb[6] = {0}; u32 value32; boolean is_sounding_success[6] = {false}; if (beamform_idx < BEAMFORMEE_ENTRY_NUM) - p_beamform_entry = &p_beamforming_info->beamformee_entry[beamform_idx]; + beamform_entry = &beamforming_info->beamformee_entry[beamform_idx]; else return; /*SU sounding done */ if (is_mu_sounding == false) { - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) - beam_ctrl_val = p_beamform_entry->mac_id; + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) + beam_ctrl_val = beamform_entry->mac_id; else - beam_ctrl_val = p_beamform_entry->p_aid; + beam_ctrl_val = beamform_entry->p_aid; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, beamform_entry.beamform_entry_state = %d", __func__, p_beamform_entry->beamform_entry_state)); + PHYDM_DBG(dm, DBG_TXBF, "@%s, beamform_entry.beamform_entry_state = %d", __func__, beamform_entry->beamform_entry_state); - if (p_beamform_entry->su_reg_index == 0) + if (beamform_entry->su_reg_index == 0) beam_ctrl_reg = REG_TXBF_CTRL_8822B; else { beam_ctrl_reg = REG_TXBF_CTRL_8822B + 2; beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); } - if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (p_beamform_entry->sound_bw == CHANNEL_WIDTH_20) + if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (beamform_entry->sound_bw == CHANNEL_WIDTH_20) beam_ctrl_val |= BIT(9); - else if (p_beamform_entry->sound_bw == CHANNEL_WIDTH_40) + else if (beamform_entry->sound_bw == CHANNEL_WIDTH_40) beam_ctrl_val |= (BIT(9) | BIT(10)); - else if (p_beamform_entry->sound_bw == CHANNEL_WIDTH_80) + else if (beamform_entry->sound_bw == CHANNEL_WIDTH_80) beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11)); } else { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", __func__); beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); } - odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val); + odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val); /*disable NDP packet use beamforming */ - tmp_val = odm_read_2byte(p_dm_odm, REG_TXBF_CTRL_8822B); - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B, tmp_val | BIT(15)); + tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8822B); + odm_write_2byte(dm, REG_TXBF_CTRL_8822B, tmp_val | BIT(15)); } else { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, MU Sounding Done\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "@%s, MU Sounding Done\n", __func__); /*MU sounding done */ - if (1) { /* (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { */ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n", __func__)); + if (1) { /* (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { */ + PHYDM_DBG(dm, DBG_TXBF, "@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n", __func__); - value32 = odm_get_bb_reg(p_dm_odm, 0x1684, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0x1684, MASKDWORD); is_sounding_success[0] = (value32 & BIT(10)) ? 1 : 0; is_sounding_success[1] = (value32 & BIT(26)) ? 1 : 0; - value32 = odm_get_bb_reg(p_dm_odm, 0x1688, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0x1688, MASKDWORD); is_sounding_success[2] = (value32 & BIT(10)) ? 1 : 0; is_sounding_success[3] = (value32 & BIT(26)) ? 1 : 0; - value32 = odm_get_bb_reg(p_dm_odm, 0x168C, MASKDWORD); + value32 = odm_get_bb_reg(dm, 0x168C, MASKDWORD); is_sounding_success[4] = (value32 & BIT(10)) ? 1 : 0; is_sounding_success[5] = (value32 & BIT(26)) ? 1 : 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n", - __func__, is_sounding_success[0], is_sounding_success[1], is_sounding_success[2], is_sounding_success[3], is_sounding_success[4], is_sounding_success[5])); + PHYDM_DBG(dm, DBG_TXBF, "@%s, is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n", + __func__, is_sounding_success[0], is_sounding_success[1], is_sounding_success[2], is_sounding_success[3], is_sounding_success[4], is_sounding_success[5]); - value32 = odm_get_bb_reg(p_dm_odm, 0xF4C, 0xFFFF0000); - /* odm_set_bb_reg(p_dm_odm, 0x19E0, MASKHWORD, 0xFFFF);Let MAC ignore bitmap */ + value32 = odm_get_bb_reg(dm, 0xF4C, 0xFFFF0000); + /* odm_set_bb_reg(dm, 0x19E0, MASKHWORD, 0xFFFF);Let MAC ignore bitmap */ is_bitmap_ready = (boolean)((value32 & BIT(15)) >> 15); bitmap = (u16)(value32 & 0x3FFF); @@ -839,29 +837,29 @@ hal_txbf_8822b_status( } for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - p_beamform_entry = &p_beamforming_info->beamformee_entry[i]; - if ((p_beamform_entry->is_mu_sta) && (p_beamform_entry->mu_reg_index < 6)) { - value32 = gid_valid[p_beamform_entry->mu_reg_index]; + beamform_entry = &beamforming_info->beamformee_entry[i]; + if ((beamform_entry->is_mu_sta) && (beamform_entry->mu_reg_index < 6)) { + value32 = gid_valid[beamform_entry->mu_reg_index]; for (idx = 0; idx < 4; idx++) { - p_beamform_entry->gid_valid[idx] = (u8)(value32 & 0xFF); + beamform_entry->gid_valid[idx] = (u8)(value32 & 0xFF); value32 = (value32 >> 8); } } } for (idx = 0; idx < 6; idx++) { - p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); - p_beamforming_info->reg_mu_tx_ctrl |= ((idx << 8) & (BIT(8) | BIT(9) | BIT(10))); - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); - odm_set_mac_reg(p_dm_odm, 0x14C4, MASKDWORD, gid_valid[idx]); /*set MU STA gid valid table*/ + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + beamforming_info->reg_mu_tx_ctrl |= ((idx << 8) & (BIT(8) | BIT(9) | BIT(10))); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + odm_set_mac_reg(dm, 0x14C4, MASKDWORD, gid_valid[idx]); /*set MU STA gid valid table*/ } /*Enable TxMU PPDU*/ - if (p_beamforming_info->dbg_disable_mu_tx == false) - p_beamforming_info->reg_mu_tx_ctrl |= BIT(7); + if (beamforming_info->dbg_disable_mu_tx == false) + beamforming_info->reg_mu_tx_ctrl |= BIT(7); else - p_beamforming_info->reg_mu_tx_ctrl &= ~BIT(7); - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + beamforming_info->reg_mu_tx_ctrl &= ~BIT(7); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); } } } @@ -869,39 +867,39 @@ hal_txbf_8822b_status( /*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ void hal_txbf_8822b_config_gtab( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry = NULL; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; u32 gid_valid = 0, user_position_l = 0, user_position_h = 0, i; - if (p_beamforming_info->mu_ap_index < BEAMFORMER_ENTRY_NUM) - p_beamformer_entry = &p_beamforming_info->beamformer_entry[p_beamforming_info->mu_ap_index]; + if (beamforming_info->mu_ap_index < BEAMFORMER_ENTRY_NUM) + beamformer_entry = &beamforming_info->beamformer_entry[beamforming_info->mu_ap_index]; else return; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s==>\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s==>\n", __func__); /*For GID 0~31*/ for (i = 0; i < 4; i++) - gid_valid |= (p_beamformer_entry->gid_valid[i] << (i << 3)); + gid_valid |= (beamformer_entry->gid_valid[i] << (i << 3)); for (i = 0; i < 8; i++) { if (i < 4) - user_position_l |= (p_beamformer_entry->user_position[i] << (i << 3)); + user_position_l |= (beamformer_entry->user_position[i] << (i << 3)); else - user_position_h |= (p_beamformer_entry->user_position[i] << ((i - 4) << 3)); + user_position_h |= (beamformer_entry->user_position[i] << ((i - 4) << 3)); } /*select MU STA0 table*/ - p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); - odm_set_bb_reg(p_dm_odm, 0x14c4, MASKDWORD, gid_valid); - odm_set_bb_reg(p_dm_odm, 0x14c8, MASKDWORD, user_position_l); - odm_set_bb_reg(p_dm_odm, 0x14cc, MASKDWORD, user_position_h); + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + odm_set_bb_reg(dm, 0x14c4, MASKDWORD, gid_valid); + odm_set_bb_reg(dm, 0x14c8, MASKDWORD, user_position_l); + odm_set_bb_reg(dm, 0x14cc, MASKDWORD, user_position_h); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", - __func__, gid_valid, user_position_l, user_position_h)); + PHYDM_DBG(dm, DBG_TXBF, "%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, gid_valid, user_position_l, user_position_h); gid_valid = 0; user_position_l = 0; @@ -909,28 +907,28 @@ hal_txbf_8822b_config_gtab( /*For GID 32~64*/ for (i = 4; i < 8; i++) - gid_valid |= (p_beamformer_entry->gid_valid[i] << ((i - 4) << 3)); + gid_valid |= (beamformer_entry->gid_valid[i] << ((i - 4) << 3)); for (i = 8; i < 16; i++) { if (i < 4) - user_position_l |= (p_beamformer_entry->user_position[i] << ((i - 8) << 3)); + user_position_l |= (beamformer_entry->user_position[i] << ((i - 8) << 3)); else - user_position_h |= (p_beamformer_entry->user_position[i] << ((i - 12) << 3)); + user_position_h |= (beamformer_entry->user_position[i] << ((i - 12) << 3)); } /*select MU STA1 table*/ - p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); - p_beamforming_info->reg_mu_tx_ctrl |= BIT(8); - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); - odm_set_bb_reg(p_dm_odm, 0x14c4, MASKDWORD, gid_valid); - odm_set_bb_reg(p_dm_odm, 0x14c8, MASKDWORD, user_position_l); - odm_set_bb_reg(p_dm_odm, 0x14cc, MASKDWORD, user_position_h); + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + beamforming_info->reg_mu_tx_ctrl |= BIT(8); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + odm_set_bb_reg(dm, 0x14c4, MASKDWORD, gid_valid); + odm_set_bb_reg(dm, 0x14c8, MASKDWORD, user_position_l); + odm_set_bb_reg(dm, 0x14cc, MASKDWORD, user_position_h); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", - __func__, gid_valid, user_position_l, user_position_h)); + PHYDM_DBG(dm, DBG_TXBF, "%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, gid_valid, user_position_l, user_position_h); /* Set validity of MU STA0 and MU STA1*/ - p_beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; - p_beamforming_info->reg_mu_tx_ctrl |= 0x3; /* STA0, STA1*/ - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; + beamforming_info->reg_mu_tx_ctrl |= 0x3; /* STA0, STA1*/ + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); } @@ -940,7 +938,7 @@ hal_txbf_8822b_config_gtab( /*This function translate the bitmap to GTAB*/ void haltxbf8822b_gtab_translation( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u8 idx, gid; @@ -1003,13 +1001,13 @@ haltxbf8822b_gtab_translation( void hal_txbf_8822b_fw_txbf( - void *p_dm_void, + void *dm_void, u8 idx ) { #if 0 - struct _RT_BEAMFORMING_INFO *p_beam_info = GET_BEAMFORM_INFO(adapter); - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + struct _RT_BEAMFORMING_INFO *beam_info = GET_BEAMFORM_INFO(adapter); + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) hal_txbf_8822b_download_ndpa(adapter, idx); @@ -1024,45 +1022,45 @@ hal_txbf_8822b_fw_txbf( /*this function is only used for BFer*/ void phydm_8822btxbf_rfmode( - void *p_dm_void, + void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i, nr_index = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i; - if (p_dm_odm->rf_type == ODM_1T1R) + if (dm->rf_type == RF_1T1R) return; if ((su_bfee_cnt > 0) || (mu_bfee_cnt > 0)) { - for (i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++) { - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0xEF, BIT(19), 0x1); /*RF mode table write enable*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0x33, 0xF, 3); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0x3E, 0xfffff, 0x00036); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0x3F, 0xfffff, 0x5AFCE); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0xEF, BIT(19), 0x0); /*RF mode table write disable*/ + for (i = RF_PATH_A; i <= RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, 0xEF, BIT(19), 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, (enum rf_path)i, 0x33, 0xF, 3); /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, 0x3E, 0xfffff, 0x00036); /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, 0x3F, 0xfffff, 0x5AFCE); /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, 0xEF, BIT(19), 0x0); /*RF mode table write disable*/ } } - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(30), 1); /*if Nsts > Nc, don't apply V matrix*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(30), 1); /*if Nsts > Nc, don't apply V matrix*/ if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); /*ignore user since 8822B only 2Tx*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); /*ignore user since 8822B only 2Tx*/ /*Nsts = 2 AB*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); } else { - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x0); /*enable BB TxBF ant mapping register*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 0); /*ignore user since 8822B only 2Tx*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x0); /*enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 0); /*ignore user since 8822B only 2Tx*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*2SS by path-A,B*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*2SS by path-A,B*/ } } @@ -1071,7 +1069,7 @@ phydm_8822btxbf_rfmode( /*this function is for BFer bug workaround*/ void phydm_8822b_sutxbfer_workaroud( - void *p_dm_void, + void *dm_void, boolean enable_su_bfer, u8 nc, u8 nr, @@ -1081,32 +1079,32 @@ phydm_8822b_sutxbfer_workaroud( boolean is_vht ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (enable_su_bfer) { - odm_set_bb_reg(p_dm_odm, 0x19f8, BIT(22) | BIT(21) | BIT(20), 0x1); - odm_set_bb_reg(p_dm_odm, 0x19f8, BIT(25) | BIT(24) | BIT(23), 0x0); - odm_set_bb_reg(p_dm_odm, 0x19f8, BIT(16), 0x1); + odm_set_bb_reg(dm, 0x19f8, BIT(22) | BIT(21) | BIT(20), 0x1); + odm_set_bb_reg(dm, 0x19f8, BIT(25) | BIT(24) | BIT(23), 0x0); + odm_set_bb_reg(dm, 0x19f8, BIT(16), 0x1); if (is_vht) - odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x1f); + odm_set_bb_reg(dm, 0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x1f); else - odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x22); + odm_set_bb_reg(dm, 0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x22); - odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(7) | BIT(6), nc); - odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(9) | BIT(8), nr); - odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(11) | BIT(10), ng); - odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(13) | BIT(12), CB); + odm_set_bb_reg(dm, 0x19f0, BIT(7) | BIT(6), nc); + odm_set_bb_reg(dm, 0x19f0, BIT(9) | BIT(8), nr); + odm_set_bb_reg(dm, 0x19f0, BIT(11) | BIT(10), ng); + odm_set_bb_reg(dm, 0x19f0, BIT(13) | BIT(12), CB); - odm_set_bb_reg(p_dm_odm, 0xb58, BIT(3) | BIT(2), BW); - odm_set_bb_reg(p_dm_odm, 0xb58, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x0); - odm_set_bb_reg(p_dm_odm, 0xb58, BIT(9) | BIT(8), BW); - odm_set_bb_reg(p_dm_odm, 0xb58, BIT(13) | BIT(12) | BIT(11) | BIT(10), 0x0); + odm_set_bb_reg(dm, 0xb58, BIT(3) | BIT(2), BW); + odm_set_bb_reg(dm, 0xb58, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x0); + odm_set_bb_reg(dm, 0xb58, BIT(9) | BIT(8), BW); + odm_set_bb_reg(dm, 0xb58, BIT(13) | BIT(12) | BIT(11) | BIT(10), 0x0); } else - odm_set_bb_reg(p_dm_odm, 0x19f8, BIT(16), 0x0); + odm_set_bb_reg(dm, 0x19f8, BIT(16), 0x0); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] enable_su_bfer = %d, is_vht = %d\n", __func__, enable_su_bfer, is_vht)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] nc = %d, nr = %d, ng = %d, CB = %d, BW = %d\n", __func__, nc, nr, ng, CB, BW)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] enable_su_bfer = %d, is_vht = %d\n", __func__, enable_su_bfer, is_vht); + PHYDM_DBG(dm, DBG_TXBF, "[%s] nc = %d, nr = %d, ng = %d, CB = %d, BW = %d\n", __func__, nc, nr, ng, CB, BW); } diff --git a/hal/phydm/txbf/haltxbf8822b.h b/hal/phydm/txbf/haltxbf8822b.h index 2ff19bd..ba33162 100644 --- a/hal/phydm/txbf/haltxbf8822b.h +++ b/hal/phydm/txbf/haltxbf8822b.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __HAL_TXBF_8822B_H__ #define __HAL_TXBF_8822B_H__ @@ -20,54 +30,54 @@ void hal_txbf_8822b_enter( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_8822b_leave( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_8822b_status( - void *p_dm_void, + void *dm_void, u8 beamform_idx ); void hal_txbf_8822b_config_gtab( - void *p_dm_void + void *dm_void ); void hal_txbf_8822b_fw_txbf( - void *p_dm_void, + void *dm_void, u8 idx ); #else -#define hal_txbf_8822b_enter(p_dm_void, idx) -#define hal_txbf_8822b_leave(p_dm_void, idx) -#define hal_txbf_8822b_status(p_dm_void, idx) -#define hal_txbf_8822b_fw_txbf(p_dm_void, idx) -#define hal_txbf_8822b_config_gtab(p_dm_void) +#define hal_txbf_8822b_enter(dm_void, idx) +#define hal_txbf_8822b_leave(dm_void, idx) +#define hal_txbf_8822b_status(dm_void, idx) +#define hal_txbf_8822b_fw_txbf(dm_void, idx) +#define hal_txbf_8822b_config_gtab(dm_void) #endif #if (defined(CONFIG_BB_TXBF_API)) void phydm_8822btxbf_rfmode( - void *p_dm_void, + void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt ); void phydm_8822b_sutxbfer_workaroud( - void *p_dm_void, + void *dm_void, boolean enable_su_bfer, u8 nc, u8 nr, @@ -78,16 +88,16 @@ phydm_8822b_sutxbfer_workaroud( ); #else -#define phydm_8822btxbf_rfmode(p_dm_void, su_bfee_cnt, mu_bfee_cnt) -#define phydm_8822b_sutxbfer_workaroud(p_dm_void, enable_su_bfer, nc, nr, ng, CB, BW, is_vht) +#define phydm_8822btxbf_rfmode(dm_void, su_bfee_cnt, mu_bfee_cnt) +#define phydm_8822b_sutxbfer_workaroud(dm_void, enable_su_bfer, nc, nr, ng, CB, BW, is_vht) #endif #else -#define hal_txbf_8822b_enter(p_dm_void, idx) -#define hal_txbf_8822b_leave(p_dm_void, idx) -#define hal_txbf_8822b_status(p_dm_void, idx) -#define hal_txbf_8822b_fw_txbf(p_dm_void, idx) -#define hal_txbf_8822b_config_gtab(p_dm_void) +#define hal_txbf_8822b_enter(dm_void, idx) +#define hal_txbf_8822b_leave(dm_void, idx) +#define hal_txbf_8822b_status(dm_void, idx) +#define hal_txbf_8822b_fw_txbf(dm_void, idx) +#define hal_txbf_8822b_config_gtab(dm_void) #endif #endif diff --git a/hal/phydm/txbf/haltxbfinterface.c b/hal/phydm/txbf/haltxbfinterface.c index 5be3016..dbaeb04 100644 --- a/hal/phydm/txbf/haltxbfinterface.c +++ b/hal/phydm/txbf/haltxbfinterface.c @@ -25,94 +25,93 @@ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) void beamforming_gid_paid( - struct _ADAPTER *adapter, - PRT_TCB p_tcb + void *adapter, + PRT_TCB tcb ) { - u8 idx = 0; u8 RA[6] = {0}; - u8 *p_header = GET_FRAME_OF_FIRST_FRAG(adapter, p_tcb); - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + u8 *p_header = GET_FRAME_OF_FIRST_FRAG((PADAPTER)adapter, tcb); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); - if (adapter->HardwareType < HARDWARE_TYPE_RTL8192EE) + if (((PADAPTER)adapter)->HardwareType < HARDWARE_TYPE_RTL8192EE) return; - else if (IS_WIRELESS_MODE_N(adapter) == false) + else if (IS_WIRELESS_MODE_N((PADAPTER)adapter) == false) return; #if (SUPPORT_MU_BF == 1) - if (p_tcb->tx_bf_pkt_type == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* MU NDPA */ + if (tcb->tx_bf_pkt_type == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* MU NDPA */ #else if (0) { #endif /* Fill G_ID and P_AID */ - p_tcb->G_ID = 63; - if (p_beam_info->first_mu_bfee_index < BEAMFORMEE_ENTRY_NUM) { - p_tcb->P_AID = p_beam_info->beamformee_entry[p_beam_info->first_mu_bfee_index].p_aid; - RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, p_tcb->G_ID, p_tcb->P_AID)); + tcb->G_ID = 63; + if (beam_info->first_mu_bfee_index < BEAMFORMEE_ENTRY_NUM) { + tcb->P_AID = beam_info->beamformee_entry[beam_info->first_mu_bfee_index].p_aid; + RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, tcb->G_ID, tcb->P_AID)); } } else { GET_80211_HDR_ADDRESS1(p_header, &RA); /* VHT SU PPDU carrying one or more group addressed MPDUs or */ /* Transmitting a VHT NDP intended for multiple recipients */ - if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || p_tcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) { - p_tcb->G_ID = 63; - p_tcb->P_AID = 0; - } else if (ACTING_AS_AP(adapter)) { - u16 AID = (u16)(MacIdGetOwnerAssociatedClientAID(adapter, p_tcb->macId) & 0x1ff); /*AID[0:8]*/ + if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || tcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) { + tcb->G_ID = 63; + tcb->P_AID = 0; + } else if (ACTING_AS_AP((PADAPTER)adapter)) { + u16 AID = (u16)(MacIdGetOwnerAssociatedClientAID((PADAPTER)adapter, tcb->macId) & 0x1ff); /*AID[0:8]*/ - /*RT_DISP(FBEAM, FBEAM_FUN, ("@%s p_tcb->mac_id=0x%X, AID=0x%X\n", __func__, p_tcb->mac_id, AID));*/ - p_tcb->G_ID = 63; + /*RT_DISP(FBEAM, FBEAM_FUN, ("@%s tcb->mac_id=0x%X, AID=0x%X\n", __func__, tcb->mac_id, AID));*/ + tcb->G_ID = 63; if (AID == 0) /*A PPDU sent by an AP to a non associated STA*/ - p_tcb->P_AID = 0; + tcb->P_AID = 0; else { /*Sent by an AP and addressed to a STA associated with that AP*/ u16 BSSID = 0; GET_80211_HDR_ADDRESS2(p_header, &RA); BSSID = ((RA[5] & 0xf0) >> 4) ^ (RA[5] & 0xf); /*BSSID[44:47] xor BSSID[40:43]*/ - p_tcb->P_AID = (AID + BSSID * 32) & 0x1ff; /*(dec(A) + dec(B)*32) mod 512*/ + tcb->P_AID = (AID + BSSID * 32) & 0x1ff; /*(dec(A) + dec(B)*32) mod 512*/ } - } else if (ACTING_AS_IBSS(adapter)) { - p_tcb->G_ID = 63; + } else if (ACTING_AS_IBSS(((PADAPTER)adapter))) { + tcb->G_ID = 63; /*P_AID for infrasturcture mode; MACID for ad-hoc mode. */ - p_tcb->P_AID = p_tcb->macId; - } else if (MgntLinkStatusQuery(adapter)) { /*Addressed to AP*/ - p_tcb->G_ID = 0; + tcb->P_AID = tcb->macId; + } else if (MgntLinkStatusQuery((PADAPTER)adapter)) { /*Addressed to AP*/ + tcb->G_ID = 0; GET_80211_HDR_ADDRESS1(p_header, &RA); - p_tcb->P_AID = RA[5]; /*RA[39:47]*/ - p_tcb->P_AID = (p_tcb->P_AID << 1) | (RA[4] >> 7); + tcb->P_AID = RA[5]; /*RA[39:47]*/ + tcb->P_AID = (tcb->P_AID << 1) | (RA[4] >> 7); } else { - p_tcb->G_ID = 63; - p_tcb->P_AID = 0; + tcb->G_ID = 63; + tcb->P_AID = 0; } - /*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, p_tcb->G_ID, p_tcb->P_AID));*/ + /*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, tcb->G_ID, tcb->P_AID));*/ } } enum rt_status beamforming_get_report_frame( - struct _ADAPTER *adapter, - PRT_RFD p_rfd, + void *adapter, + PRT_RFD rfd, POCTET_STRING p_pdu_os ) { - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; - u8 *p_mimo_ctrl_field, p_csi_report, p_csi_matrix; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + u8 *p_mimo_ctrl_field, p_csi_matrix; u8 idx, nc, nr, CH_W; u16 csi_matrix_len = 0; ACT_PKT_TYPE pkt_type = ACT_PKT_TYPE_UNKNOWN; /* Memory comparison to see if CSI report is the same with previous one */ - p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, Frame_Addr2(*p_pdu_os), &idx); + beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, Frame_Addr2(*p_pdu_os), &idx); - if (p_beamform_entry == NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("beamforming_get_report_frame: Cannot find entry by addr\n")); + if (beamform_entry == NULL) { + PHYDM_DBG(dm, DBG_TXBF, "beamforming_get_report_frame: Cannot find entry by addr\n"); return RT_STATUS_FAILURE; } @@ -136,7 +135,7 @@ beamforming_get_report_frame( } else return RT_STATUS_SUCCESS; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d, pkt type=%d, nc=%d, nr=%d, CH_W=%d\n", __func__, idx, pkt_type, nc, nr, CH_W)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] idx=%d, pkt type=%d, nc=%d, nr=%d, CH_W=%d\n", __func__, idx, pkt_type, nc, nr, CH_W); return RT_STATUS_SUCCESS; } @@ -144,15 +143,20 @@ beamforming_get_report_frame( void construct_ht_ndpa_packet( - struct _ADAPTER *adapter, + // 2017/11 MH PHYDM compile. But why need to use windows maco? + // For all linux code, it should be useless? + //void *adapter = dm->adapter; + ADAPTER *adapter, + //void *adapter, u8 *RA, u8 *buffer, u32 *p_length, - CHANNEL_WIDTH BW + enum channel_width BW ) { u16 duration = 0; - PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); + PMGNT_INFO mgnt_info = &(((PADAPTER)adapter)->MgntInfo); + //PMGNT_INFO mgnt_info = &((MGNT_INFO)(((PADAPTER)adapter)->MgntInfo)); OCTET_STRING p_ndpa_frame, action_content; u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; @@ -164,8 +168,8 @@ construct_ht_ndpa_packet( SET_80211_HDR_TYPE_AND_SUBTYPE(buffer, Type_Action_No_Ack); SET_80211_HDR_ADDRESS1(buffer, RA); - SET_80211_HDR_ADDRESS2(buffer, adapter->CurrentAddress); - SET_80211_HDR_ADDRESS3(buffer, p_mgnt_info->Bssid); + SET_80211_HDR_ADDRESS2(buffer, ((PADAPTER)adapter)->CurrentAddress); + SET_80211_HDR_ADDRESS3(buffer, ((PMGNT_INFO)mgnt_info)->Bssid); duration = 2 * a_SifsTime + 40; @@ -193,36 +197,35 @@ construct_ht_ndpa_packet( boolean send_fw_ht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, - CHANNEL_WIDTH BW + enum channel_width BW ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - PRT_TCB p_tcb; + struct dm_struct *dm = (struct dm_struct *)dm_void; + PADAPTER adapter = (PADAPTER)dm->adapter; + PRT_TCB tcb; PRT_TX_LOCAL_BUFFER p_buf; boolean ret = true; u32 buf_len; u8 *buf_addr; u8 desc_len = 0, idx = 0, ndp_tx_rate; - struct _ADAPTER *p_def_adapter = GetDefaultAdapter(adapter); - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + void *p_def_adapter = GetDefaultAdapter((adapter)); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((adapter)); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_beamform_entry == NULL) + if (beamform_entry == NULL) return false; - ndp_tx_rate = beamforming_get_htndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetFWBuffer(p_def_adapter, &p_tcb, &p_buf)) { + if (MgntGetFWBuffer((PADAPTER)p_def_adapter, &tcb, &p_buf)) { #if (DEV_BUS_TYPE != RT_PCI_INTERFACE) - desc_len = adapter->HWDescHeadLength - p_hal_data->USBALLDummyLength; + desc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength; #endif buf_addr = p_buf->Buffer.VirtualAddress + desc_len; @@ -234,26 +237,26 @@ send_fw_ht_ndpa_packet( BW ); - p_tcb->PacketLength = buf_len + desc_len; + tcb->PacketLength = buf_len + desc_len; - p_tcb->bTxEnableSwCalcDur = true; + tcb->bTxEnableSwCalcDur = true; - p_tcb->BWOfPacket = BW; + tcb->BWOfPacket = BW; - if (ACTING_AS_IBSS(adapter) || ACTING_AS_AP(adapter)) - p_tcb->G_ID = 63; + if (ACTING_AS_IBSS((adapter)) || ACTING_AS_AP((adapter))) + tcb->G_ID = 63; - p_tcb->P_AID = p_beamform_entry->p_aid; - p_tcb->DataRate = ndp_tx_rate; /*rate of NDP decide by nr*/ + tcb->P_AID = beamform_entry->p_aid; + tcb->DataRate = ndp_tx_rate; /*rate of NDP decide by nr*/ - adapter->HalFunc.CmdSendPacketHandler(adapter, p_tcb, p_buf, p_tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false); + adapter->HalFunc.CmdSendPacketHandler(adapter, tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } @@ -261,48 +264,47 @@ send_fw_ht_ndpa_packet( boolean send_sw_ht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, - CHANNEL_WIDTH BW + enum channel_width BW ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - PRT_TCB p_tcb; + struct dm_struct *dm = (struct dm_struct *)dm_void; + PADAPTER adapter = (PADAPTER)dm->adapter; + PRT_TCB tcb; PRT_TX_LOCAL_BUFFER p_buf; boolean ret = true; u8 idx = 0, ndp_tx_rate = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - ndp_tx_rate = beamforming_get_htndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { construct_ht_ndpa_packet( adapter, RA, p_buf->Buffer.VirtualAddress, - &p_tcb->PacketLength, + &tcb->PacketLength, BW ); - p_tcb->bTxEnableSwCalcDur = true; + tcb->bTxEnableSwCalcDur = true; - p_tcb->BWOfPacket = BW; + tcb->BWOfPacket = BW; - MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } @@ -311,28 +313,33 @@ send_sw_ht_ndpa_packet( void construct_vht_ndpa_packet( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 *RA, u16 AID, u8 *buffer, u32 *p_length, - CHANNEL_WIDTH BW + enum channel_width BW ) { u16 duration = 0; u8 sequence = 0; u8 *p_ndpa_frame = buffer; struct _RT_NDPA_STA_INFO sta_info; - struct _ADAPTER *adapter = p_dm_odm->adapter; + // 2017/11 MH PHYDM compile. But why need to use windows maco? + // For all linux code, it should be useless? + //void *adapter = dm->adapter; + ADAPTER *adapter = (PADAPTER)(dm->adapter); u8 idx = 0; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); /* Frame control. */ SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0); SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA); SET_80211_HDR_ADDRESS1(p_ndpa_frame, RA); - SET_80211_HDR_ADDRESS2(p_ndpa_frame, p_beamform_entry->my_mac_addr); + SET_80211_HDR_ADDRESS2(p_ndpa_frame, beamform_entry->my_mac_addr); + // 2017/11 MH PHYDM compile. But why need to use windows maco? + // For all linux code, it should be useless? duration = 2 * a_SifsTime + 44; if (BW == CHANNEL_WIDTH_80) @@ -344,17 +351,17 @@ construct_vht_ndpa_packet( SET_80211_HDR_DURATION(p_ndpa_frame, duration); - sequence = *(p_dm_odm->p_sounding_seq) << 2; - odm_move_memory(p_dm_odm, p_ndpa_frame + 16, &sequence, 1); + sequence = *(dm->sounding_seq) << 2; + odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1); - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss) || phydm_acting_determine(p_dm_odm, phydm_acting_as_ap) == false) + if (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap) == false) AID = 0; sta_info.aid = AID; sta_info.feedback_type = 0; sta_info.nc_index = 0; - odm_move_memory(p_dm_odm, p_ndpa_frame + 17, (u8 *)&sta_info, 2); + odm_move_memory(dm, p_ndpa_frame + 17, (u8 *)&sta_info, 2); *p_length = 19; } @@ -362,43 +369,42 @@ construct_vht_ndpa_packet( boolean send_fw_vht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, u16 AID, - CHANNEL_WIDTH BW + enum channel_width BW ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - PRT_TCB p_tcb; + struct dm_struct *dm = (struct dm_struct *)dm_void; + PADAPTER adapter = (PADAPTER)dm->adapter; + PRT_TCB tcb; PRT_TX_LOCAL_BUFFER p_buf; boolean ret = true; u32 buf_len; u8 *buf_addr; u8 desc_len = 0, idx = 0, ndp_tx_rate = 0; - struct _ADAPTER *p_def_adapter = GetDefaultAdapter(adapter); - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + void *p_def_adapter = GetDefaultAdapter((adapter)); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((adapter)); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_beamform_entry == NULL) + if (beamform_entry == NULL) return false; - ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetFWBuffer(p_def_adapter, &p_tcb, &p_buf)) { + if (MgntGetFWBuffer((PADAPTER)p_def_adapter, &tcb, &p_buf)) { #if (DEV_BUS_TYPE != RT_PCI_INTERFACE) - desc_len = adapter->HWDescHeadLength - p_hal_data->USBALLDummyLength; + desc_len = adapter->HWDescHeadLength - hal_data->USBALLDummyLength; #endif buf_addr = p_buf->Buffer.VirtualAddress + desc_len; construct_vht_ndpa_packet( - p_dm_odm, + dm, RA, AID, buf_addr, @@ -406,28 +412,28 @@ send_fw_vht_ndpa_packet( BW ); - p_tcb->PacketLength = buf_len + desc_len; + tcb->PacketLength = buf_len + desc_len; - p_tcb->bTxEnableSwCalcDur = true; + tcb->bTxEnableSwCalcDur = true; - p_tcb->BWOfPacket = BW; + tcb->BWOfPacket = BW; - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss) || phydm_acting_determine(p_dm_odm, phydm_acting_as_ap)) - p_tcb->G_ID = 63; + if (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap)) + tcb->G_ID = 63; - p_tcb->P_AID = p_beamform_entry->p_aid; - p_tcb->DataRate = ndp_tx_rate; /*decide by nr*/ + tcb->P_AID = beamform_entry->p_aid; + tcb->DataRate = ndp_tx_rate; /*decide by nr*/ - adapter->HalFunc.CmdSendPacketHandler(adapter, p_tcb, p_buf, p_tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false); + adapter->HalFunc.CmdSendPacketHandler(adapter, tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, ret=%d\n", __func__, ret)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] End, ret=%d\n", __func__, ret); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } @@ -436,48 +442,47 @@ send_fw_vht_ndpa_packet( boolean send_sw_vht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, u16 AID, - CHANNEL_WIDTH BW + enum channel_width BW ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - PRT_TCB p_tcb; + struct dm_struct *dm = (struct dm_struct *)dm_void; + PADAPTER adapter = (PADAPTER)dm->adapter; + PRT_TCB tcb; PRT_TX_LOCAL_BUFFER p_buf; boolean ret = true; u8 idx = 0, ndp_tx_rate = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); - ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { construct_vht_ndpa_packet( - p_dm_odm, + dm, RA, AID, p_buf->Buffer.VirtualAddress, - &p_tcb->PacketLength, + &tcb->PacketLength, BW ); - p_tcb->bTxEnableSwCalcDur = true; - p_tcb->BWOfPacket = BW; + tcb->bTxEnableSwCalcDur = true; + tcb->BWOfPacket = BW; /*rate of NDP decide by nr*/ - MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } @@ -491,33 +496,33 @@ send_sw_vht_ndpa_packet( */ enum rt_status beamforming_get_vht_gid_mgnt_frame( - struct _ADAPTER *adapter, - PRT_RFD p_rfd, + void *adapter, + PRT_RFD rfd, POCTET_STRING p_pdu_os ) { - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; enum rt_status rt_status = RT_STATUS_SUCCESS; u8 *p_buffer = NULL; u8 *p_raddr = NULL; u8 mem_status[8] = {0}, user_pos[16] = {0}; u8 idx; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMER_ENTRY *p_beamform_entry = &p_beam_info->beamformer_entry[p_beam_info->mu_ap_index]; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMER_ENTRY *beamform_entry = &beam_info->beamformer_entry[beam_info->mu_ap_index]; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] On VHT GID mgnt frame!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] On VHT GID mgnt frame!\n", __func__); /* Check length*/ if (p_pdu_os->length < (FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY + 16)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("beamforming_get_vht_gid_mgnt_frame(): Invalid length (%d)\n", p_pdu_os->length)); + PHYDM_DBG(dm, DBG_TXBF, "beamforming_get_vht_gid_mgnt_frame(): Invalid length (%d)\n", p_pdu_os->length); return RT_STATUS_INVALID_LENGTH; } /* Check RA*/ p_raddr = (u8 *)(p_pdu_os->Octet) + 4; if (!eq_mac_addr(p_raddr, adapter->CurrentAddress)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("beamforming_get_vht_gid_mgnt_frame(): Drop because of RA error.\n")); + PHYDM_DBG(dm, DBG_TXBF, "beamforming_get_vht_gid_mgnt_frame(): Drop because of RA error.\n"); return RT_STATUS_PKT_DROP; } @@ -527,7 +532,7 @@ beamforming_get_vht_gid_mgnt_frame( p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY; for (idx = 0; idx < 8; idx++) { mem_status[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx); - p_beamform_entry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx); + beamform_entry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx); } RT_DISP_DATA(FBEAM, FBEAM_DATA, "mem_status: ", mem_status, 8); @@ -536,7 +541,7 @@ beamforming_get_vht_gid_mgnt_frame( p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY; for (idx = 0; idx < 16; idx++) { user_pos[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx); - p_beamform_entry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx); + beamform_entry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx); } RT_DISP_DATA(FBEAM, FBEAM_DATA, "user_pos: ", user_pos, 16); @@ -552,8 +557,8 @@ beamforming_get_vht_gid_mgnt_frame( tmp_val2 = ((user_pos[i * 2 + 1] << 8) & 0xFF00) + (user_pos[i * 2] & 0xFF); for (j = 0; j < 8; j++) { if ((tmp_val >> j) & BIT(0)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Use Group ID (%d), User Position (%d)\n", - (i * 8 + j), (tmp_val2 >> 2 * j) & 0x3)); + PHYDM_DBG(dm, DBG_TXBF, "Use Group ID (%d), User Position (%d)\n", + (i * 8 + j), (tmp_val2 >> 2 * j) & 0x3); } } } @@ -564,9 +569,9 @@ beamforming_get_vht_gid_mgnt_frame( u8 indibuffer[24] = {0}; u8 indioffset = 0; - PlatformMoveMemory(indibuffer + indioffset, p_beamform_entry->gid_valid, 8); + PlatformMoveMemory(indibuffer + indioffset, beamform_entry->gid_valid, 8); indioffset += 8; - PlatformMoveMemory(indibuffer + indioffset, p_beamform_entry->user_position, 16); + PlatformMoveMemory(indibuffer + indioffset, beamform_entry->user_position, 16); indioffset += 16; PlatformIndicateCustomStatus( @@ -578,7 +583,7 @@ beamforming_get_vht_gid_mgnt_frame( } /* Config HW GID table */ - hal_com_txbf_config_gtab(p_dm_odm); + hal_com_txbf_config_gtab(dm); return rt_status; } @@ -590,16 +595,16 @@ beamforming_get_vht_gid_mgnt_frame( */ void construct_vht_gid_mgnt_frame( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 *RA, - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry, + struct _RT_BEAMFORMEE_ENTRY *beamform_entry, u8 *buffer, u32 *p_length ) { - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _ADAPTER *adapter = p_beam_info->source_adapter; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; OCTET_STRING os_ftm_frame, tmp; FillOctetString(os_ftm_frame, buffer, 0); @@ -613,11 +618,11 @@ construct_vht_gid_mgnt_frame( &os_ftm_frame); /* Membership status array*/ - FillOctetString(tmp, p_beamform_entry->gid_valid, 8); + FillOctetString(tmp, beamform_entry->gid_valid, 8); PacketAppendData(&os_ftm_frame, tmp); /* User Position array*/ - FillOctetString(tmp, p_beamform_entry->user_position, 16); + FillOctetString(tmp, beamform_entry->user_position, 16); PacketAppendData(&os_ftm_frame, tmp); *p_length = os_ftm_frame.length; @@ -627,43 +632,43 @@ construct_vht_gid_mgnt_frame( boolean send_sw_vht_gid_mgnt_frame( - void *p_dm_void, + void *dm_void, u8 *RA, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - PRT_TCB p_tcb; + struct dm_struct *dm = (struct dm_struct *)dm_void; + PRT_TCB tcb; PRT_TX_LOCAL_BUFFER p_buf; boolean ret = true; u8 data_rate = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = &p_beam_info->beamformee_entry[idx]; - struct _ADAPTER *adapter = p_beam_info->source_adapter; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = &beam_info->beamformee_entry[idx]; + void *adapter = beam_info->source_adapter; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { construct_vht_gid_mgnt_frame( - p_dm_odm, + dm, RA, - p_beamform_entry, + beamform_entry, p_buf->Buffer.VirtualAddress, - &p_tcb->PacketLength + &tcb->PacketLength ); - p_tcb->bw_of_packet = CHANNEL_WIDTH_20; + tcb->bw_of_packet = CHANNEL_WIDTH_20; data_rate = MGN_6M; - MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, data_rate); + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } @@ -676,14 +681,14 @@ send_sw_vht_gid_mgnt_frame( */ void construct_vht_bf_report_poll( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 *RA, u8 *buffer, u32 *p_length ) { - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _ADAPTER *adapter = p_beam_info->source_adapter; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; u8 *p_bf_rpt_poll = buffer; /* Frame control*/ @@ -710,49 +715,49 @@ construct_vht_bf_report_poll( boolean send_sw_vht_bf_report_poll( - void *p_dm_void, + void *dm_void, u8 *RA, boolean is_final_poll ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - PRT_TCB p_tcb; + struct dm_struct *dm = (struct dm_struct *)dm_void; + PRT_TCB tcb; PRT_TX_LOCAL_BUFFER p_buf; boolean ret = true; u8 idx = 0, data_rate = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); - struct _ADAPTER *adapter = p_beam_info->source_adapter; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + void *adapter = beam_info->source_adapter; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { construct_vht_bf_report_poll( - p_dm_odm, + dm, RA, p_buf->Buffer.VirtualAddress, - &p_tcb->PacketLength + &tcb->PacketLength ); - p_tcb->bTxEnableSwCalcDur = true; /* need?*/ - p_tcb->BWOfPacket = CHANNEL_WIDTH_20; + tcb->bTxEnableSwCalcDur = true; /* need?*/ + tcb->BWOfPacket = CHANNEL_WIDTH_20; if (is_final_poll) - p_tcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL; + tcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL; else - p_tcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL; + tcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL; data_rate = MGN_6M; /* Legacy OFDM rate*/ - MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, data_rate); + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "send_sw_vht_bf_report_poll():\n", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "send_sw_vht_bf_report_poll():\n", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; @@ -767,32 +772,32 @@ send_sw_vht_bf_report_poll( */ void construct_vht_mu_ndpa_packet( - struct PHY_DM_STRUCT *p_dm_odm, - CHANNEL_WIDTH BW, + struct dm_struct *dm, + enum channel_width BW, u8 *buffer, u32 *p_length ) { - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _ADAPTER *adapter = p_beam_info->source_adapter; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; u16 duration = 0; u8 sequence = 0; u8 *p_ndpa_frame = buffer; struct _RT_NDPA_STA_INFO sta_info; u8 idx; u8 dest_addr[6] = {0}; - struct _RT_BEAMFORMEE_ENTRY *p_entry = NULL; + struct _RT_BEAMFORMEE_ENTRY *entry = NULL; /* Fill the first MU BFee entry (STA1) MAC addr to destination address then HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_entry = &(p_beam_info->beamformee_entry[idx]); - if (p_entry->is_mu_sta) { - cp_mac_addr(dest_addr, p_entry->mac_addr); + entry = &(beam_info->beamformee_entry[idx]); + if (entry->is_mu_sta) { + cp_mac_addr(dest_addr, entry->mac_addr); break; } } - if (p_entry == NULL) + if (entry == NULL) return; /* Frame control.*/ @@ -800,7 +805,7 @@ construct_vht_mu_ndpa_packet( SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA); SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr); - SET_80211_HDR_ADDRESS2(p_ndpa_frame, p_entry->my_mac_addr); + SET_80211_HDR_ADDRESS2(p_ndpa_frame, entry->my_mac_addr); /*--------------------------------------------*/ /* Need to modify "duration" to MU consideration. */ @@ -816,22 +821,22 @@ construct_vht_mu_ndpa_packet( SET_80211_HDR_DURATION(p_ndpa_frame, duration); - sequence = *(p_dm_odm->p_sounding_seq) << 2; - odm_move_memory(p_dm_odm, p_ndpa_frame + 16, &sequence, 1); + sequence = *(dm->sounding_seq) << 2; + odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1); *p_length = 17; /* Construct STA info. for multiple STAs*/ for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_entry = &(p_beam_info->beamformee_entry[idx]); - if (p_entry->is_mu_sta) { - sta_info.aid = p_entry->AID; + entry = &(beam_info->beamformee_entry[idx]); + if (entry->is_mu_sta) { + sta_info.aid = entry->AID; sta_info.feedback_type = 1; /* 1'b1: MU*/ sta_info.nc_index = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get beamformee_entry idx(%d), AID =%d\n", __func__, idx, p_entry->AID)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Get beamformee_entry idx(%d), AID =%d\n", __func__, idx, entry->AID); - odm_move_memory(p_dm_odm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2); + odm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2); *p_length += 2; } } @@ -840,44 +845,44 @@ construct_vht_mu_ndpa_packet( boolean send_sw_vht_mu_ndpa_packet( - void *p_dm_void, - CHANNEL_WIDTH BW + void *dm_void, + enum channel_width BW ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - PRT_TCB p_tcb; + struct dm_struct *dm = (struct dm_struct *)dm_void; + PRT_TCB tcb; PRT_TX_LOCAL_BUFFER p_buf; boolean ret = true; u8 ndp_tx_rate = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _ADAPTER *adapter = p_beam_info->source_adapter; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; ndp_tx_rate = MGN_VHT2SS_MCS0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { construct_vht_mu_ndpa_packet( - p_dm_odm, + dm, BW, p_buf->Buffer.VirtualAddress, - &p_tcb->PacketLength + &tcb->PacketLength ); - p_tcb->bTxEnableSwCalcDur = true; - p_tcb->BWOfPacket = BW; - p_tcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA; + tcb->bTxEnableSwCalcDur = true; + tcb->BWOfPacket = BW; + tcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA; /*rate of NDP decide by nr*/ - MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } @@ -885,21 +890,21 @@ send_sw_vht_mu_ndpa_packet( void dbg_construct_vht_mundpa_packet( - struct PHY_DM_STRUCT *p_dm_odm, - CHANNEL_WIDTH BW, + struct dm_struct *dm, + enum channel_width BW, u8 *buffer, u32 *p_length ) { - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _ADAPTER *adapter = p_beam_info->source_adapter; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; u16 duration = 0; u8 sequence = 0; u8 *p_ndpa_frame = buffer; struct _RT_NDPA_STA_INFO sta_info; u8 idx; u8 dest_addr[6] = {0}; - struct _RT_BEAMFORMEE_ENTRY *p_entry = NULL; + struct _RT_BEAMFORMEE_ENTRY *entry = NULL; boolean is_STA1 = false; @@ -907,13 +912,13 @@ dbg_construct_vht_mundpa_packet( /* Fill the first MU BFee entry (STA1) MAC addr to destination address then HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_entry = &(p_beam_info->beamformee_entry[idx]); - if (p_entry->is_mu_sta) { + entry = &(beam_info->beamformee_entry[idx]); + if (entry->is_mu_sta) { if (is_STA1 == false) { is_STA1 = true; continue; } else { - cp_mac_addr(dest_addr, p_entry->mac_addr); + cp_mac_addr(dest_addr, entry->mac_addr); break; } } @@ -924,7 +929,7 @@ dbg_construct_vht_mundpa_packet( SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA); SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr); - SET_80211_HDR_ADDRESS2(p_ndpa_frame, p_dm_odm->CurrentAddress); + SET_80211_HDR_ADDRESS2(p_ndpa_frame, dm->CurrentAddress); /*--------------------------------------------*/ /* Need to modify "duration" to MU consideration. */ @@ -940,63 +945,63 @@ dbg_construct_vht_mundpa_packet( SET_80211_HDR_DURATION(p_ndpa_frame, duration); - sequence = *(p_dm_odm->p_sounding_seq) << 2; - odm_move_memory(p_dm_odm, p_ndpa_frame + 16, &sequence, 1); + sequence = *(dm->sounding_seq) << 2; + odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1); *p_length = 17; /*STA2's STA Info*/ - sta_info.aid = p_entry->aid; + sta_info.aid = entry->aid; sta_info.feedback_type = 1; /* 1'b1: MU */ sta_info.nc_index = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get beamformee_entry idx(%d), AID =%d\n", __func__, idx, p_entry->aid)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Get beamformee_entry idx(%d), AID =%d\n", __func__, idx, entry->aid); - odm_move_memory(p_dm_odm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2); + odm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2); *p_length += 2; } boolean dbg_send_sw_vht_mundpa_packet( - void *p_dm_void, - CHANNEL_WIDTH BW + void *dm_void, + enum channel_width BW ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - PRT_TCB p_tcb; + struct dm_struct *dm = (struct dm_struct *)dm_void; + PRT_TCB tcb; PRT_TX_LOCAL_BUFFER p_buf; boolean ret = true; u8 ndp_tx_rate = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _ADAPTER *adapter = p_beam_info->source_adapter; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; ndp_tx_rate = MGN_VHT2SS_MCS0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { dbg_construct_vht_mundpa_packet( - p_dm_odm, + dm, BW, p_buf->Buffer.VirtualAddress, - &p_tcb->PacketLength + &tcb->PacketLength ); - p_tcb->bTxEnableSwCalcDur = true; - p_tcb->BWOfPacket = BW; - p_tcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA; + tcb->bTxEnableSwCalcDur = true; + tcb->BWOfPacket = BW; + tcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA; /*rate of NDP decide by nr*/ - MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } @@ -1010,13 +1015,13 @@ dbg_send_sw_vht_mundpa_packet( u32 beamforming_get_report_frame( - void *p_dm_void, + void *dm_void, union recv_frame *precv_frame ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 ret = _SUCCESS; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; u8 *pframe = precv_frame->u.hdr.rx_data; u32 frame_len = precv_frame->u.hdr.len; u8 *TA; @@ -1025,10 +1030,10 @@ beamforming_get_report_frame( /*Memory comparison to see if CSI report is the same with previous one*/ TA = get_addr2_ptr(pframe); - p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, TA, &idx); - if (p_beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) + beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, TA, &idx); + if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) offset = 31; /*24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/ - else if (p_beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) + else if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) offset = 34; /*24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/ else return ret; @@ -1040,13 +1045,13 @@ beamforming_get_report_frame( boolean send_fw_ht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, - CHANNEL_WIDTH BW + enum channel_width BW ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ADAPTER *adapter = dm->adapter; struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; struct rtw_ieee80211_hdr *pwlanhdr; @@ -1058,14 +1063,14 @@ send_fw_ht_ndpa_packet( u16 *fctrl; u16 duration = 0; u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); - return _FALSE; + PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n", __func__); + return false; } /* update attribute */ @@ -1073,8 +1078,8 @@ send_fw_ht_ndpa_packet( update_mgntframe_attrib(adapter, pattrib); pattrib->qsel = QSLT_BEACON; - ndp_tx_rate = beamforming_get_htndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate); pattrib->rate = ndp_tx_rate; pattrib->bwmode = BW; pattrib->order = 1; @@ -1093,7 +1098,7 @@ send_fw_ht_ndpa_packet( set_frame_sub_type(pframe, WIFI_ACTION_NOACK); _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, p_beamform_entry->my_mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); if (pmlmeext->cur_wireless_mode == WIRELESS_11B) @@ -1122,19 +1127,19 @@ send_fw_ht_ndpa_packet( dump_mgntframe(adapter, pmgntframe); - return _TRUE; + return true; } boolean send_sw_ht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, - CHANNEL_WIDTH BW + enum channel_width BW ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ADAPTER *adapter = dm->adapter; struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; struct rtw_ieee80211_hdr *pwlanhdr; @@ -1146,16 +1151,16 @@ send_sw_ht_ndpa_packet( u16 *fctrl; u16 duration = 0; u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); - ndp_tx_rate = beamforming_get_htndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); + ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); - return _FALSE; + PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n", __func__); + return false; } /*update attribute*/ @@ -1180,7 +1185,7 @@ send_sw_ht_ndpa_packet( set_frame_sub_type(pframe, WIFI_ACTION_NOACK); _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, p_beamform_entry->my_mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); if (pmlmeext->cur_wireless_mode == WIRELESS_11B) @@ -1209,20 +1214,20 @@ send_sw_ht_ndpa_packet( dump_mgntframe(adapter, pmgntframe); - return _TRUE; + return true; } boolean send_fw_vht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, u16 AID, - CHANNEL_WIDTH BW + enum channel_width BW ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ADAPTER *adapter = dm->adapter; struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; struct rtw_ieee80211_hdr *pwlanhdr; @@ -1234,15 +1239,15 @@ send_fw_vht_ndpa_packet( u16 *fctrl; u16 duration = 0; u8 sequence = 0, a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); struct _RT_NDPA_STA_INFO sta_info; pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); - return _FALSE; + PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n", __func__); + return false; } /* update attribute */ @@ -1251,8 +1256,8 @@ send_fw_vht_ndpa_packet( update_mgntframe_attrib(adapter, pattrib); pattrib->qsel = QSLT_BEACON; - ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate); pattrib->rate = ndp_tx_rate; pattrib->bwmode = BW; pattrib->subtype = WIFI_NDPA; @@ -1269,7 +1274,7 @@ send_fw_vht_ndpa_packet( set_frame_sub_type(pframe, WIFI_NDPA); _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, p_beamform_entry->my_mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN); if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) a_sifs_time = 16; @@ -1287,11 +1292,11 @@ send_fw_vht_ndpa_packet( set_duration(pframe, duration); - sequence = p_beam_info->sounding_sequence << 2; - if (p_beam_info->sounding_sequence >= 0x3f) - p_beam_info->sounding_sequence = 0; + sequence = beam_info->sounding_sequence << 2; + if (beam_info->sounding_sequence >= 0x3f) + beam_info->sounding_sequence = 0; else - p_beam_info->sounding_sequence++; + beam_info->sounding_sequence++; _rtw_memcpy(pframe + 16, &sequence, 1); @@ -1310,21 +1315,21 @@ send_fw_vht_ndpa_packet( dump_mgntframe(adapter, pmgntframe); - return _TRUE; + return true; } boolean send_sw_vht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, u16 AID, - CHANNEL_WIDTH BW + enum channel_width BW ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ADAPTER *adapter = dm->adapter; struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; struct rtw_ieee80211_hdr *pwlanhdr; @@ -1337,17 +1342,17 @@ send_sw_vht_ndpa_packet( u8 *pframe; u16 *fctrl; u16 duration = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); - ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate); pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); - return _FALSE; + PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n", __func__); + return false; } /*update attribute*/ @@ -1371,7 +1376,7 @@ send_sw_vht_ndpa_packet( set_frame_sub_type(pframe, WIFI_NDPA); _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, p_beamform_entry->my_mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN); if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) a_sifs_time = 16; @@ -1389,11 +1394,11 @@ send_sw_vht_ndpa_packet( set_duration(pframe, duration); - sequence = p_beam_info->sounding_sequence << 2; - if (p_beam_info->sounding_sequence >= 0x3f) - p_beam_info->sounding_sequence = 0; + sequence = beam_info->sounding_sequence << 2; + if (beam_info->sounding_sequence >= 0x3f) + beam_info->sounding_sequence = 0; else - p_beam_info->sounding_sequence++; + beam_info->sounding_sequence++; _rtw_memcpy(pframe + 16, &sequence, 1); if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) @@ -1410,9 +1415,9 @@ send_sw_vht_ndpa_packet( pattrib->last_txcmdsz = pattrib->pktlen; dump_mgntframe(adapter, pmgntframe); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] [%d]\n", __func__, __LINE__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] [%d]\n", __func__, __LINE__); - return _TRUE; + return true; } @@ -1421,7 +1426,7 @@ send_sw_vht_ndpa_packet( void beamforming_get_ndpa_frame( - void *p_dm_void, + void *dm_void, #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) OCTET_STRING pdu_os #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) @@ -1429,8 +1434,7 @@ beamforming_get_ndpa_frame( #endif ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 *TA ; u8 idx, sequence; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) @@ -1438,7 +1442,7 @@ beamforming_get_ndpa_frame( #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) u8 *p_ndpa_frame = precv_frame->u.hdr.rx_data; #endif - struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry = NULL; /*Modified By Jeffery @2014-10-29*/ + struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; /*Modified By Jeffery @2014-10-29*/ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) @@ -1448,8 +1452,8 @@ beamforming_get_ndpa_frame( if (get_frame_sub_type(p_ndpa_frame) != WIFI_NDPA) #endif return; - else if (!(p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] not 8812 or 8821A, return\n", __func__)); + else if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] not 8812 or 8821A, return\n", __func__); return; } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) @@ -1460,54 +1464,54 @@ beamforming_get_ndpa_frame( /*Remove signaling TA. */ TA[0] = TA[0] & 0xFE; - p_beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(p_dm_odm, TA, &idx); /* Modified By Jeffery @2014-10-29 */ + beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, TA, &idx); /* Modified By Jeffery @2014-10-29 */ /*Break options for Clock Reset*/ - if (p_beamformer_entry == NULL) + if (beamformer_entry == NULL) return; - else if (!(p_beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)) + else if (!(beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)) return; /*log_success: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/ /*clock_reset_times: While BFer entry always doesn't receive our CSI, clock will reset again and again.So clock_reset_times is limited to 5 times.2015-04-13, Jeffery*/ - else if ((p_beamformer_entry->log_success == 1) || (p_beamformer_entry->clock_reset_times == 5)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, log_success=%d, clock_reset_times=%d, clock reset is no longer needed.\n", - __func__, p_beamformer_entry->log_seq, p_beamformer_entry->pre_log_seq, p_beamformer_entry->log_retry_cnt, p_beamformer_entry->log_success, p_beamformer_entry->clock_reset_times)); + else if ((beamformer_entry->log_success == 1) || (beamformer_entry->clock_reset_times == 5)) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, log_success=%d, clock_reset_times=%d, clock reset is no longer needed.\n", + __func__, beamformer_entry->log_seq, beamformer_entry->pre_log_seq, beamformer_entry->log_retry_cnt, beamformer_entry->log_success, beamformer_entry->clock_reset_times); return; } sequence = (p_ndpa_frame[16]) >> 2; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start, sequence=%d, log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, clock_reset_times=%d, log_success=%d\n", - __func__, sequence, p_beamformer_entry->log_seq, p_beamformer_entry->pre_log_seq, p_beamformer_entry->log_retry_cnt, p_beamformer_entry->clock_reset_times, p_beamformer_entry->log_success)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start, sequence=%d, log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, clock_reset_times=%d, log_success=%d\n", + __func__, sequence, beamformer_entry->log_seq, beamformer_entry->pre_log_seq, beamformer_entry->log_retry_cnt, beamformer_entry->clock_reset_times, beamformer_entry->log_success); - if ((p_beamformer_entry->log_seq != 0) && (p_beamformer_entry->pre_log_seq != 0)) { + if ((beamformer_entry->log_seq != 0) && (beamformer_entry->pre_log_seq != 0)) { /*Success condition*/ - if ((p_beamformer_entry->log_seq != sequence) && (p_beamformer_entry->pre_log_seq != p_beamformer_entry->log_seq)) { + if ((beamformer_entry->log_seq != sequence) && (beamformer_entry->pre_log_seq != beamformer_entry->log_seq)) { /* break option for clcok reset, 2015-03-30, Jeffery */ - p_beamformer_entry->log_retry_cnt = 0; + beamformer_entry->log_retry_cnt = 0; /*As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/ /*That is, log_success is NOT needed to be reset to zero, 2015-04-13, Jeffery*/ - p_beamformer_entry->log_success = 1; + beamformer_entry->log_success = 1; } else {/*Fail condition*/ - if (p_beamformer_entry->log_retry_cnt == 5) { - p_beamformer_entry->clock_reset_times++; - p_beamformer_entry->log_retry_cnt = 0; + if (beamformer_entry->log_retry_cnt == 5) { + beamformer_entry->clock_reset_times++; + beamformer_entry->log_retry_cnt = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Clock Reset!!! clock_reset_times=%d\n", - __func__, p_beamformer_entry->clock_reset_times)); - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_CLK, NULL); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Clock Reset!!! clock_reset_times=%d\n", + __func__, beamformer_entry->clock_reset_times); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_CLK, NULL); } else - p_beamformer_entry->log_retry_cnt++; + beamformer_entry->log_retry_cnt++; } } /*Update log_seq & pre_log_seq*/ - p_beamformer_entry->pre_log_seq = p_beamformer_entry->log_seq; - p_beamformer_entry->log_seq = sequence; + beamformer_entry->pre_log_seq = beamformer_entry->log_seq; + beamformer_entry->log_seq = sequence; } diff --git a/hal/phydm/txbf/haltxbfinterface.h b/hal/phydm/txbf/haltxbfinterface.h index fcaae54..7482ae4 100644 --- a/hal/phydm/txbf/haltxbfinterface.h +++ b/hal/phydm/txbf/haltxbfinterface.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __HAL_TXBF_INTERFACE_H__ #define __HAL_TXBF_INTERFACE_H__ @@ -22,85 +32,85 @@ void beamforming_gid_paid( - struct _ADAPTER *adapter, - PRT_TCB p_tcb + void *adapter, + PRT_TCB tcb ); enum rt_status beamforming_get_report_frame( - struct _ADAPTER *adapter, - PRT_RFD p_rfd, + void *adapter, + PRT_RFD rfd, POCTET_STRING p_pdu_os ); void beamforming_get_ndpa_frame( - void *p_dm_void, + void *dm_void, OCTET_STRING pdu_os ); boolean send_fw_ht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, - CHANNEL_WIDTH BW + enum channel_width BW ); boolean send_fw_vht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, u16 AID, - CHANNEL_WIDTH BW + enum channel_width BW ); boolean send_sw_vht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, u16 AID, - CHANNEL_WIDTH BW + enum channel_width BW ); boolean send_sw_ht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, - CHANNEL_WIDTH BW + enum channel_width BW ); #if (SUPPORT_MU_BF == 1) enum rt_status beamforming_get_vht_gid_mgnt_frame( - struct _ADAPTER *adapter, - PRT_RFD p_rfd, + void *adapter, + PRT_RFD rfd, POCTET_STRING p_pdu_os ); boolean send_sw_vht_gid_mgnt_frame( - void *p_dm_void, + void *dm_void, u8 *RA, u8 idx ); boolean send_sw_vht_bf_report_poll( - void *p_dm_void, + void *dm_void, u8 *RA, boolean is_final_poll ); boolean send_sw_vht_mu_ndpa_packet( - void *p_dm_void, - CHANNEL_WIDTH BW + void *dm_void, + enum channel_width BW ); #else -#define beamforming_get_vht_gid_mgnt_frame(adapter, p_rfd, p_pdu_os) RT_STATUS_FAILURE -#define send_sw_vht_gid_mgnt_frame(p_dm_void, RA) -#define send_sw_vht_bf_report_poll(p_dm_void, RA, is_final_poll) -#define send_sw_vht_mu_ndpa_packet(p_dm_void, BW) +#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE +#define send_sw_vht_gid_mgnt_frame(dm_void, RA) +#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll) +#define send_sw_vht_mu_ndpa_packet(dm_void, BW) #endif @@ -108,44 +118,44 @@ send_sw_vht_mu_ndpa_packet( u32 beamforming_get_report_frame( - void *p_dm_void, + void *dm_void, union recv_frame *precv_frame ); boolean send_fw_ht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, - CHANNEL_WIDTH BW + enum channel_width BW ); boolean send_sw_ht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, - CHANNEL_WIDTH BW + enum channel_width BW ); boolean send_fw_vht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, u16 AID, - CHANNEL_WIDTH BW + enum channel_width BW ); boolean send_sw_vht_ndpa_packet( - void *p_dm_void, + void *dm_void, u8 *RA, u16 AID, - CHANNEL_WIDTH BW + enum channel_width BW ); #endif void beamforming_get_ndpa_frame( - void *p_dm_void, + void *dm_void, #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) OCTET_STRING pdu_os #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) @@ -155,25 +165,25 @@ beamforming_get_ndpa_frame( boolean dbg_send_sw_vht_mundpa_packet( - void *p_dm_void, - CHANNEL_WIDTH BW + void *dm_void, + enum channel_width BW ); #else -#define beamforming_get_ndpa_frame(p_dm_odm, _pdu_os) +#define beamforming_get_ndpa_frame(dm, _pdu_os) #if (DM_ODM_SUPPORT_TYPE == ODM_CE) #define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define beamforming_get_report_frame(adapter, p_rfd, p_pdu_os) RT_STATUS_FAILURE - #define beamforming_get_vht_gid_mgnt_frame(adapter, p_rfd, p_pdu_os) RT_STATUS_FAILURE + #define beamforming_get_report_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE + #define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE #endif -#define send_fw_ht_ndpa_packet(p_dm_void, RA, BW) -#define send_sw_ht_ndpa_packet(p_dm_void, RA, BW) -#define send_fw_vht_ndpa_packet(p_dm_void, RA, AID, BW) -#define send_sw_vht_ndpa_packet(p_dm_void, RA, AID, BW) -#define send_sw_vht_gid_mgnt_frame(p_dm_void, RA, idx) -#define send_sw_vht_bf_report_poll(p_dm_void, RA, is_final_poll) -#define send_sw_vht_mu_ndpa_packet(p_dm_void, BW) +#define send_fw_ht_ndpa_packet(dm_void, RA, BW) +#define send_sw_ht_ndpa_packet(dm_void, RA, BW) +#define send_fw_vht_ndpa_packet(dm_void, RA, AID, BW) +#define send_sw_vht_ndpa_packet(dm_void, RA, AID, BW) +#define send_sw_vht_gid_mgnt_frame(dm_void, RA, idx) +#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll) +#define send_sw_vht_mu_ndpa_packet(dm_void, BW) #endif #endif diff --git a/hal/phydm/txbf/haltxbfjaguar.c b/hal/phydm/txbf/haltxbfjaguar.c index 4525771..85eac44 100644 --- a/hal/phydm/txbf/haltxbfjaguar.c +++ b/hal/phydm/txbf/haltxbfjaguar.c @@ -25,133 +25,133 @@ #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) void hal_txbf_8812a_set_ndpa_rate( - void *p_dm_void, + void *dm_void, u8 BW, u8 rate ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8812A, (rate << 2 | BW)); + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8812A, (rate << 2 | BW)); } void hal_txbf_jaguar_rf_mode( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->rf_type == ODM_1T1R) + if (dm->rf_type == RF_1T1R) return; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set TxIQGen\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] set TxIQGen\n", __func__); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); /*RF mode table write enable*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x1); /*RF mode table write enable*/ - if (p_beam_info->beamformee_su_cnt > 0) { + if (beam_info->beamformee_su_cnt > 0) { /* Paath_A */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0x78000, 0x3); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ /* Path_B */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0x78000, 0x3); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ } else { /* Paath_A */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0x78000, 0x3); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ /* Path_B */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0x78000, 0x3); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ } - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); /*RF mode table write disable*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0); /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x0); /*RF mode table write disable*/ - if (p_beam_info->beamformee_su_cnt > 0) - odm_set_bb_reg(p_dm_odm, 0x80c, MASKBYTE1, 0x33); + if (beam_info->beamformee_su_cnt > 0) + odm_set_bb_reg(dm, 0x80c, MASKBYTE1, 0x33); else - odm_set_bb_reg(p_dm_odm, 0x80c, MASKBYTE1, 0x11); + odm_set_bb_reg(dm, 0x80c, MASKBYTE1, 0x11); } void hal_txbf_jaguar_download_ndpa( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 u1b_tmp = 0, tmp_reg422 = 0, head_page; u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; boolean is_send_beacon = false; u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/ - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + void *adapter = dm->adapter; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true; + *dm->is_fw_dw_rsvd_page_in_progress = true; #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); if (idx == 0) head_page = 0xFE; else head_page = 0xFE; - phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy); + phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy); /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8812A + 1); - odm_write_1byte(p_dm_odm, REG_CR_8812A + 1, (u1b_tmp | BIT(0))); + u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1); + odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp | BIT(0))); /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8812A + 2); - odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6))); + tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6))); if (tmp_reg422 & BIT(6)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\n")); + PHYDM_DBG(dm, DBG_TXBF, "SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\n"); is_send_beacon = true; } /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ - odm_write_1byte(p_dm_odm, REG_TDECTRL_8812A + 1, head_page); + odm_write_1byte(dm, REG_TDECTRL_8812A + 1, head_page); do { /*Clear beacon valid check bit.*/ - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_TDECTRL_8812A + 2); - odm_write_1byte(p_dm_odm, REG_TDECTRL_8812A + 2, (bcn_valid_reg | BIT(0))); + bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2); + odm_write_1byte(dm, REG_TDECTRL_8812A + 2, (bcn_valid_reg | BIT(0))); /*download NDPA rsvd page.*/ if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) - beamforming_send_vht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->aid, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->aid, p_beam_entry->sound_bw, BEACON_QUEUE); else - beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); /*check rsvd page download OK.*/ - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_TDECTRL_8812A + 2); + bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2); count = 0; while (!(bcn_valid_reg & BIT(0)) && count < 20) { count++; ODM_delay_ms(10); - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_TDECTRL_8812A + 2); + bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2); } dl_bcn_count++; } while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5); if (!(bcn_valid_reg & BIT(0))) - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n", __func__); /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ - odm_write_1byte(p_dm_odm, REG_TDECTRL_8812A + 1, tx_page_bndy); + odm_write_1byte(dm, REG_TDECTRL_8812A + 1, tx_page_bndy); /*To make sure that if there exists an adapter which would like to send beacon.*/ /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ @@ -159,46 +159,46 @@ hal_txbf_jaguar_download_ndpa( /*the beacon cannot be sent by HW.*/ /*2010.06.23. Added by tynli.*/ if (is_send_beacon) - odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422); /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8812A + 1); - odm_write_1byte(p_dm_odm, REG_CR_8812A + 1, (u1b_tmp & (~BIT(0)))); + u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1); + odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp & (~BIT(0)))); p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false; + *dm->is_fw_dw_rsvd_page_in_progress = false; #endif } void hal_txbf_jaguar_fw_txbf_cmd( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 idx, period0 = 0, period1 = 0; u8 PageNum0 = 0xFF, PageNum1 = 0xFF; u8 u1_tx_bf_parm[3] = {0}; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { /*Modified by David*/ - if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { if (idx == 0) { - if (p_beam_info->beamformee_entry[idx].is_sound) + if (beam_info->beamformee_entry[idx].is_sound) PageNum0 = 0xFE; else PageNum0 = 0xFF; /*stop sounding*/ - period0 = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + period0 = (u8)(beam_info->beamformee_entry[idx].sound_period); } else if (idx == 1) { - if (p_beam_info->beamformee_entry[idx].is_sound) + if (beam_info->beamformee_entry[idx].is_sound) PageNum1 = 0xFE; else PageNum1 = 0xFF; /*stop sounding*/ - period1 = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + period1 = (u8)(beam_info->beamformee_entry[idx].sound_period); } } } @@ -206,158 +206,158 @@ hal_txbf_jaguar_fw_txbf_cmd( u1_tx_bf_parm[0] = PageNum0; u1_tx_bf_parm[1] = PageNum1; u1_tx_bf_parm[2] = (period1 << 4) | period0; - odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); + odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, - ("[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", __func__, PageNum0, period0, PageNum1, period1)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", __func__, PageNum0, period0, PageNum1, period1); } void hal_txbf_jaguar_enter( - void *p_dm_void, + void *dm_void, u8 bfer_bfee_idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; u8 bfee_idx = (bfer_bfee_idx & 0xF); u32 csi_param; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; struct _RT_BEAMFORMEE_ENTRY beamformee_entry; struct _RT_BEAMFORMER_ENTRY beamformer_entry; u16 sta_id = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!\n", __func__); - hal_txbf_jaguar_rf_mode(p_dm_odm, p_beamforming_info); + hal_txbf_jaguar_rf_mode(dm, beamforming_info); - if (p_dm_odm->rf_type == ODM_2T2R) - odm_set_bb_reg(p_dm_odm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/ + if (dm->rf_type == RF_2T2R) + odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/ else - odm_set_bb_reg(p_dm_odm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/ + odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/ - if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { - beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx]; + if ((beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { + beamformer_entry = beamforming_info->beamformer_entry[bfer_idx]; /*Sounding protocol control*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A, 0xCB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB); /*MAC address/Partial AID of Beamformer*/ if (bfer_idx == 0) { for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_BFMER0_INFO_8812A + i), beamformer_entry.mac_addr[i]); + odm_write_1byte(dm, (REG_BFMER0_INFO_8812A + i), beamformer_entry.mac_addr[i]); /*CSI report use legacy ofdm so don't need to fill P_AID. */ /*platform_efio_write_2byte(adapter, REG_BFMER0_INFO_8812A+6, beamform_entry.P_AID); */ } else { for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_BFMER1_INFO_8812A + i), beamformer_entry.mac_addr[i]); + odm_write_1byte(dm, (REG_BFMER1_INFO_8812A + i), beamformer_entry.mac_addr[i]); /*CSI report use legacy ofdm so don't need to fill P_AID.*/ /*platform_efio_write_2byte(adapter, REG_BFMER1_INFO_8812A+6, beamform_entry.P_AID);*/ } /*CSI report parameters of Beamformee*/ if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) { - if (p_dm_odm->rf_type == ODM_2T2R) + if (dm->rf_type == RF_2T2R) csi_param = 0x01090109; else csi_param = 0x01080108; } else { - if (p_dm_odm->rf_type == ODM_2T2R) + if (dm->rf_type == RF_2T2R) csi_param = 0x03090309; else csi_param = 0x03080308; } - odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8812A, csi_param); - odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8812A, csi_param); - odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8812A, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, csi_param); /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A + 3, 0x50); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A + 3, 0x50); } - if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { - beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx]; + if ((beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { + beamformee_entry = beamforming_info->beamformee_entry[bfee_idx]; - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) sta_id = beamformee_entry.mac_id; else sta_id = beamformee_entry.p_aid; /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ if (bfee_idx == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8812A, sta_id); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8812A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8812A + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_TXBF_CTRL_8812A, sta_id); + odm_write_1byte(dm, REG_TXBF_CTRL_8812A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8812A + 3) | BIT(4) | BIT(6) | BIT(7)); } else - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8812A + 2, sta_id | BIT(12) | BIT(14) | BIT(15)); + odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, sta_id | BIT(12) | BIT(14) | BIT(15)); /*CSI report parameters of Beamformee*/ if (bfee_idx == 0) { /*Get BIT24 & BIT25*/ - u8 tmp = odm_read_1byte(p_dm_odm, REG_BFMEE_SEL_8812A + 3) & 0x3; + u8 tmp = odm_read_1byte(dm, REG_BFMEE_SEL_8812A + 3) & 0x3; - odm_write_1byte(p_dm_odm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60); - odm_write_2byte(p_dm_odm, REG_BFMEE_SEL_8812A, sta_id | BIT(9)); + odm_write_1byte(dm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60); + odm_write_2byte(dm, REG_BFMEE_SEL_8812A, sta_id | BIT(9)); } else { /*Set BIT25*/ - odm_write_2byte(p_dm_odm, REG_BFMEE_SEL_8812A + 2, sta_id | 0xE200); + odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, sta_id | 0xE200); } - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); } } void hal_txbf_jaguar_leave( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; struct _RT_BEAMFORMER_ENTRY beamformer_entry; struct _RT_BEAMFORMEE_ENTRY beamformee_entry; if (idx < BEAMFORMER_ENTRY_NUM) { - beamformer_entry = p_beamforming_info->beamformer_entry[idx]; - beamformee_entry = p_beamforming_info->beamformee_entry[idx]; + beamformer_entry = beamforming_info->beamformer_entry[idx]; + beamformee_entry = beamforming_info->beamformee_entry[idx]; } else return; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!, IDx = %d\n", __func__, idx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!, IDx = %d\n", __func__, idx); /*Clear P_AID of Beamformee*/ /*Clear MAC address of Beamformer*/ /*Clear Associated Bfmee Sel*/ if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A, 0xC8); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8); if (idx == 0) { - odm_write_4byte(p_dm_odm, REG_BFMER0_INFO_8812A, 0); - odm_write_2byte(p_dm_odm, REG_BFMER0_INFO_8812A + 4, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); + odm_write_4byte(dm, REG_BFMER0_INFO_8812A, 0); + odm_write_2byte(dm, REG_BFMER0_INFO_8812A + 4, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0); } else { - odm_write_4byte(p_dm_odm, REG_BFMER1_INFO_8812A, 0); - odm_write_2byte(p_dm_odm, REG_BFMER1_INFO_8812A + 4, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); + odm_write_4byte(dm, REG_BFMER1_INFO_8812A, 0); + odm_write_2byte(dm, REG_BFMER1_INFO_8812A + 4, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0); } } if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { - hal_txbf_jaguar_rf_mode(p_dm_odm, p_beamforming_info); + hal_txbf_jaguar_rf_mode(dm, beamforming_info); if (idx == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8812A, 0x0); - odm_write_2byte(p_dm_odm, REG_BFMEE_SEL_8812A, 0); + odm_write_2byte(dm, REG_TXBF_CTRL_8812A, 0x0); + odm_write_2byte(dm, REG_BFMEE_SEL_8812A, 0); } else { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8812A + 2, odm_read_2byte(p_dm_odm, REG_TXBF_CTRL_8812A + 2) & 0xF000); - odm_write_2byte(p_dm_odm, REG_BFMEE_SEL_8812A + 2, odm_read_2byte(p_dm_odm, REG_BFMEE_SEL_8812A + 2) & 0x60); + odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, odm_read_2byte(dm, REG_TXBF_CTRL_8812A + 2) & 0xF000); + odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, odm_read_2byte(dm, REG_BFMEE_SEL_8812A + 2) & 0x60); } } @@ -366,17 +366,17 @@ hal_txbf_jaguar_leave( void hal_txbf_jaguar_status( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u16 beam_ctrl_val; u32 beam_ctrl_reg; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY beamform_entry = p_beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx]; - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) beam_ctrl_val = beamform_entry.mac_id; else beam_ctrl_val = beamform_entry.p_aid; @@ -388,7 +388,7 @@ hal_txbf_jaguar_status( beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); } - if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beam_info->apply_v_matrix == true)) { + if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (beam_info->apply_v_matrix == true)) { if (beamform_entry.sound_bw == CHANNEL_WIDTH_20) beam_ctrl_val |= BIT(9); else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40) @@ -398,85 +398,85 @@ hal_txbf_jaguar_status( } else beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] beam_ctrl_val = 0x%x!\n", __func__, beam_ctrl_val)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] beam_ctrl_val = 0x%x!\n", __func__, beam_ctrl_val); - odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val); + odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val); } void hal_txbf_jaguar_fw_txbf( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) - hal_txbf_jaguar_download_ndpa(p_dm_odm, idx); + hal_txbf_jaguar_download_ndpa(dm, idx); - hal_txbf_jaguar_fw_txbf_cmd(p_dm_odm); + hal_txbf_jaguar_fw_txbf_cmd(dm); } void hal_txbf_jaguar_patch( - void *p_dm_void, + void *dm_void, u8 operation ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_beam_info->beamform_cap == BEAMFORMING_CAP_NONE) + if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE) return; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) if (operation == SCAN_OPT_BACKUP_BAND0) - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A, 0xC8); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8); else if (operation == SCAN_OPT_RESTORE) - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A, 0xCB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB); #endif } void hal_txbf_jaguar_clk_8812a( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u16 u2btmp; u8 count = 0, u1btmp; - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (*(p_dm_odm->p_is_scan_in_process)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] return by Scan\n", __func__)); + if (*(dm->is_scan_in_process)) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] return by Scan\n", __func__); return; } #if DEV_BUS_TYPE == RT_PCI_INTERFACE /*Stop PCIe TxDMA*/ - odm_write_1byte(p_dm_odm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE); + odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE); #endif /*Stop Usb TxDMA*/ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_DISABLE_FUNC(adapter, DF_TX_BIT); - PlatformReturnAllPendingTxPackets(adapter); + RT_DISABLE_FUNC((PADAPTER)adapter, DF_TX_BIT); + PlatformReturnAllPendingTxPackets((PADAPTER)adapter); #else rtw_write_port_cancel(adapter); #endif /*Wait TXFF empty*/ for (count = 0; count < 100; count++) { - u2btmp = odm_read_2byte(p_dm_odm, REG_TXPKT_EMPTY_8812A); + u2btmp = odm_read_2byte(dm, REG_TXPKT_EMPTY_8812A); u2btmp = u2btmp & 0xfff; if (u2btmp != 0xfff) { ODM_delay_ms(10); @@ -486,11 +486,11 @@ hal_txbf_jaguar_clk_8812a( } /*TX pause*/ - odm_write_1byte(p_dm_odm, REG_TXPAUSE_8812A, 0xFF); + odm_write_1byte(dm, REG_TXPAUSE_8812A, 0xFF); /*Wait TX state Machine OK*/ for (count = 0; count < 100; count++) { - if (odm_read_4byte(p_dm_odm, REG_SCH_TXCMD_8812A) != 0) + if (odm_read_4byte(dm, REG_SCH_TXCMD_8812A) != 0) continue; else break; @@ -498,11 +498,11 @@ hal_txbf_jaguar_clk_8812a( /*Stop RX DMA path*/ - u1btmp = odm_read_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A); - odm_write_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT(2)); + u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A); + odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT(2)); for (count = 0; count < 100; count++) { - u1btmp = odm_read_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A); + u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A); if (u1btmp & BIT(1)) break; else @@ -510,27 +510,27 @@ hal_txbf_jaguar_clk_8812a( } /*Disable clock*/ - odm_write_1byte(p_dm_odm, REG_SYS_CLKR_8812A + 1, 0xf0); + odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xf0); /*Disable 320M*/ - odm_write_1byte(p_dm_odm, REG_AFE_PLL_CTRL_8812A + 3, 0x8); + odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0x8); /*Enable 320M*/ - odm_write_1byte(p_dm_odm, REG_AFE_PLL_CTRL_8812A + 3, 0xa); + odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0xa); /*Enable clock*/ - odm_write_1byte(p_dm_odm, REG_SYS_CLKR_8812A + 1, 0xfc); + odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xfc); /*Release Tx pause*/ - odm_write_1byte(p_dm_odm, REG_TXPAUSE_8812A, 0); + odm_write_1byte(dm, REG_TXPAUSE_8812A, 0); /*Enable RX DMA path*/ - u1btmp = odm_read_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A); - odm_write_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT(2))); + u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A); + odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT(2))); #if DEV_BUS_TYPE == RT_PCI_INTERFACE /*Enable PCIe TxDMA*/ - odm_write_1byte(p_dm_odm, REG_PCIE_CTRL_REG_8812A + 1, 0); + odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0); #endif /*Start Usb TxDMA*/ - RT_ENABLE_FUNC(adapter, DF_TX_BIT); + RT_ENABLE_FUNC((PADAPTER)adapter, DF_TX_BIT); } #endif diff --git a/hal/phydm/txbf/haltxbfjaguar.h b/hal/phydm/txbf/haltxbfjaguar.h index 4b1b320..1b89675 100644 --- a/hal/phydm/txbf/haltxbfjaguar.h +++ b/hal/phydm/txbf/haltxbfjaguar.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,9 +8,19 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ #ifndef __HAL_TXBF_JAGUAR_H__ #define __HAL_TXBF_JAGUAR_H__ @@ -19,7 +29,7 @@ void hal_txbf_8812a_set_ndpa_rate( - void *p_dm_void, + void *dm_void, u8 BW, u8 rate ); @@ -27,62 +37,62 @@ hal_txbf_8812a_set_ndpa_rate( void hal_txbf_jaguar_enter( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_jaguar_leave( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_jaguar_status( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_jaguar_fw_txbf( - void *p_dm_void, + void *dm_void, u8 idx ); void hal_txbf_jaguar_patch( - void *p_dm_void, + void *dm_void, u8 operation ); void hal_txbf_jaguar_clk_8812a( - void *p_dm_void + void *dm_void ); #else -#define hal_txbf_8812a_set_ndpa_rate(p_dm_void, BW, rate) -#define hal_txbf_jaguar_enter(p_dm_void, idx) -#define hal_txbf_jaguar_leave(p_dm_void, idx) -#define hal_txbf_jaguar_status(p_dm_void, idx) -#define hal_txbf_jaguar_fw_txbf(p_dm_void, idx) -#define hal_txbf_jaguar_patch(p_dm_void, operation) -#define hal_txbf_jaguar_clk_8812a(p_dm_void) +#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_jaguar_enter(dm_void, idx) +#define hal_txbf_jaguar_leave(dm_void, idx) +#define hal_txbf_jaguar_status(dm_void, idx) +#define hal_txbf_jaguar_fw_txbf(dm_void, idx) +#define hal_txbf_jaguar_patch(dm_void, operation) +#define hal_txbf_jaguar_clk_8812a(dm_void) #endif #else -#define hal_txbf_8812a_set_ndpa_rate(p_dm_void, BW, rate) -#define hal_txbf_jaguar_enter(p_dm_void, idx) -#define hal_txbf_jaguar_leave(p_dm_void, idx) -#define hal_txbf_jaguar_status(p_dm_void, idx) -#define hal_txbf_jaguar_fw_txbf(p_dm_void, idx) -#define hal_txbf_jaguar_patch(p_dm_void, operation) -#define hal_txbf_jaguar_clk_8812a(p_dm_void) +#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_jaguar_enter(dm_void, idx) +#define hal_txbf_jaguar_leave(dm_void, idx) +#define hal_txbf_jaguar_status(dm_void, idx) +#define hal_txbf_jaguar_fw_txbf(dm_void, idx) +#define hal_txbf_jaguar_patch(dm_void, operation) +#define hal_txbf_jaguar_clk_8812a(dm_void) #endif #endif /* #ifndef __HAL_TXBF_JAGUAR_H__ */ diff --git a/hal/phydm/txbf/phydm_hal_txbf_api.c b/hal/phydm/txbf/phydm_hal_txbf_api.c index eed3487..6e9be14 100644 --- a/hal/phydm/txbf/phydm_hal_txbf_api.c +++ b/hal/phydm/txbf/phydm_hal_txbf_api.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,6 +12,7 @@ * more details. * *****************************************************************************/ + #include "mp_precomp.h" #include "phydm_precomp.h" @@ -22,18 +23,18 @@ /*this function is only used for BFer*/ u8 phydm_get_ndpa_rate( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 ndpa_rate = ODM_RATE6M; - if (p_dm_odm->rssi_min >= 30) /*link RSSI > 30%*/ + if (dm->rssi_min >= 30) /*link RSSI > 30%*/ ndpa_rate = ODM_RATE24M; - else if (p_dm_odm->rssi_min <= 25) + else if (dm->rssi_min <= 25) ndpa_rate = ODM_RATE6M; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] ndpa_rate = 0x%x\n", __func__, ndpa_rate)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndpa_rate = 0x%x\n", __func__, ndpa_rate); return ndpa_rate; @@ -42,7 +43,7 @@ phydm_get_ndpa_rate( /*this function is only used for BFer*/ u8 phydm_get_beamforming_sounding_info( - void *p_dm_void, + void *dm_void, u16 *troughput, u8 total_bfee_num, u8 *tx_rate @@ -50,11 +51,19 @@ phydm_get_beamforming_sounding_info( { u8 idx = 0; u8 soundingdecision = 0xff; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; for (idx = 0; idx < total_bfee_num; idx++) { - if (((tx_rate[idx] >= ODM_RATEVHTSS3MCS7) && (tx_rate[idx] <= ODM_RATEVHTSS3MCS9))) - soundingdecision = soundingdecision & ~(1 << idx); + if (dm->support_ic_type & (ODM_RTL8814A)) { + if (((tx_rate[idx] >= ODM_RATEVHTSS3MCS7) && (tx_rate[idx] <= ODM_RATEVHTSS3MCS9))) + soundingdecision = soundingdecision & ~(1 << idx); + } else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C | ODM_RTL8812)) { + if (((tx_rate[idx] >= ODM_RATEVHTSS2MCS7) && (tx_rate[idx] <= ODM_RATEVHTSS2MCS9))) + soundingdecision = soundingdecision & ~(1 << idx); + } else if (dm->support_ic_type & (ODM_RTL8814B)) { + if (((tx_rate[idx] >= ODM_RATEVHTSS4MCS7) && (tx_rate[idx] <= ODM_RATEVHTSS4MCS9))) + soundingdecision = soundingdecision & ~(1 << idx); + } } for (idx = 0; idx < total_bfee_num; idx++) { @@ -62,7 +71,7 @@ phydm_get_beamforming_sounding_info( soundingdecision = soundingdecision & ~(1 << idx); } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] soundingdecision = 0x%x\n", __func__, soundingdecision)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] soundingdecision = 0x%x\n", __func__, soundingdecision); return soundingdecision; @@ -71,12 +80,12 @@ phydm_get_beamforming_sounding_info( /*this function is only used for BFer*/ u8 phydm_get_mu_bfee_snding_decision( - void *p_dm_void, + void *dm_void, u16 throughput ) { u8 snding_score = 0; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; /*throughput unit is Mbps*/ if (throughput >= 500) @@ -102,7 +111,7 @@ phydm_get_mu_bfee_snding_decision( else snding_score = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] snding_score = 0x%x\n", __func__, snding_score)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] snding_score = 0x%x\n", __func__, snding_score); return snding_score; @@ -113,17 +122,17 @@ phydm_get_mu_bfee_snding_decision( #if (DM_ODM_SUPPORT_TYPE != ODM_AP) u8 beamforming_get_htndp_tx_rate( - void *p_dm_void, + void *dm_void, u8 comp_steering_num_of_bfer ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 nr_index = 0; u8 ndp_tx_rate; /*Find nr*/ #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), comp_steering_num_of_bfer); + if (dm->support_ic_type & ODM_RTL8814A) + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), comp_steering_num_of_bfer); else #endif nr_index = tx_bf_nr(1, comp_steering_num_of_bfer); @@ -152,17 +161,17 @@ beamforming_get_htndp_tx_rate( u8 beamforming_get_vht_ndp_tx_rate( - void *p_dm_void, + void *dm_void, u8 comp_steering_num_of_bfer ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 nr_index = 0; u8 ndp_tx_rate; /*Find nr*/ #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), comp_steering_num_of_bfer); + if (dm->support_ic_type & ODM_RTL8814A) + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), comp_steering_num_of_bfer); else #endif nr_index = tx_bf_nr(1, comp_steering_num_of_bfer); diff --git a/hal/phydm/txbf/phydm_hal_txbf_api.h b/hal/phydm/txbf/phydm_hal_txbf_api.h index 3dd0bb3..e31dab6 100644 --- a/hal/phydm/txbf/phydm_hal_txbf_api.h +++ b/hal/phydm/txbf/phydm_hal_txbf_api.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2011 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,11 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * *****************************************************************************/ - #ifndef __PHYDM_HAL_TXBF_API_H__ #define __PHYDM_HAL_TXBF_API_H__ @@ -23,13 +32,13 @@ u8 beamforming_get_htndp_tx_rate( - void *p_dm_void, + void *dm_void, u8 comp_steering_num_of_bfer ); u8 beamforming_get_vht_ndp_tx_rate( - void *p_dm_void, + void *dm_void, u8 comp_steering_num_of_bfer ); @@ -38,7 +47,7 @@ beamforming_get_vht_ndp_tx_rate( #if (RTL8822B_SUPPORT == 1) u8 phydm_get_beamforming_sounding_info( - void *p_dm_void, + void *dm_void, u16 *troughput, u8 total_bfee_num, u8 *tx_rate @@ -46,19 +55,19 @@ phydm_get_beamforming_sounding_info( u8 phydm_get_ndpa_rate( - void *p_dm_void + void *dm_void ); u8 phydm_get_mu_bfee_snding_decision( - void *p_dm_void, + void *dm_void, u16 throughput ); #else -#define phydm_get_beamforming_sounding_info(p_dm_void, troughput, total_bfee_num, tx_rate) -#define phydm_get_ndpa_rate(p_dm_void) -#define phydm_get_mu_bfee_snding_decision(p_dm_void, troughput) +#define phydm_get_beamforming_sounding_info(dm_void, troughput, total_bfee_num, tx_rate) 0 +#define phydm_get_ndpa_rate(dm_void) +#define phydm_get_mu_bfee_snding_decision(dm_void, troughput) #endif diff --git a/hal/rtl8822b/hal8822b_fw.c b/hal/rtl8822b/hal8822b_fw.c index f935d13..780755e 100644 --- a/hal/rtl8822b/hal8822b_fw.c +++ b/hal/rtl8822b/hal8822b_fw.c @@ -1,17 +1,17 @@ /****************************************************************************** - * - * Copyright(c) 2015 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ +* +* Copyright(c) 2012 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ #ifdef CONFIG_RTL8822B @@ -22,13 +22,13 @@ #if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) u8 array_mp_8822b_fw_ap[] = { -0x22, 0x88, 0x00, 0x00, 0x0D, 0x00, 0x01, 0x00, -0x67, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x03, 0x0D, 0x0F, 0x28, 0xE1, 0x07, 0x00, 0x00, -0x08, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, -0x00, 0x00, 0x20, 0x80, 0xC8, 0x28, 0x00, 0x00, +0x22, 0x88, 0x00, 0x00, 0x16, 0x00, 0x06, 0x00, +0x42, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x04, 0x19, 0x0E, 0x27, 0xE2, 0x07, 0x00, 0x00, +0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, +0x00, 0x00, 0x20, 0x80, 0x28, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x48, 0x15, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, +0x40, 0x6A, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x12, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -39,11 +39,11 @@ u8 array_mp_8822b_fw_ap[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x9D, 0x29, 0x00, 0x80, 0xE9, 0x06, 0x00, 0x80, +0xA1, 0x31, 0x00, 0x80, 0xE9, 0x06, 0x00, 0x80, 0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE, 0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE, 0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE, -0x61, 0x50, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, +0xCD, 0x73, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -51,7 +51,7 @@ u8 array_mp_8822b_fw_ap[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x75, 0x51, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, +0xA9, 0x75, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -59,7 +59,7 @@ u8 array_mp_8822b_fw_ap[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0xC8, 0x28, 0x20, 0x80, 0x41, 0x4E, 0x59, 0x00, +0x28, 0x2E, 0x20, 0x80, 0x41, 0x4E, 0x59, 0x00, 0x61, 0x6E, 0x79, 0x00, 0x81, 0x00, 0x88, 0x00, 0x90, 0x00, 0x99, 0x00, 0xA2, 0x00, 0xAC, 0x00, 0xB6, 0x00, 0xC0, 0x00, 0xCC, 0x00, 0xD8, 0x00, @@ -74,96 +74,124 @@ u8 array_mp_8822b_fw_ap[] = { 0x08, 0x08, 0x0C, 0x09, 0x00, 0x0C, 0xB0, 0x0C, 0xB4, 0x0C, 0xBC, 0x0C, 0x00, 0x0E, 0xB0, 0x0E, 0xB4, 0x0E, 0xBC, 0x0E, 0x90, 0x19, 0xA4, 0x09, -0x04, 0x0A, 0x00, 0x0B, 0xDF, 0x8F, 0x65, 0x00, -0x01, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x04, 0x00, -0x2D, 0x00, 0x2C, 0x01, 0x2D, 0x01, 0x2C, 0x02, -0x2E, 0x01, 0xFF, 0x00, 0x2D, 0x02, 0xFF, 0x00, -0x03, 0x00, 0x00, 0x00, 0x10, 0x70, 0xC9, 0x75, +0x04, 0x0A, 0x00, 0x0B, 0x38, 0x08, 0x00, 0x00, +0xDF, 0x8F, 0x65, 0x00, 0x01, 0x00, 0x00, 0x00, +0x2C, 0x00, 0x04, 0x00, 0x2D, 0x00, 0x2C, 0x01, +0x2D, 0x01, 0x2C, 0x02, 0x2E, 0x01, 0xFF, 0x00, +0x2D, 0x02, 0xFF, 0x00, 0x03, 0x02, 0x00, 0x00, 0x10, 0x70, 0xC9, 0x75, 0x10, 0x70, 0xC9, 0x75, -0x10, 0x70, 0xC9, 0x75, 0x2A, 0xEA, 0xA0, 0x79, -0x2C, 0xEA, 0xA0, 0x79, 0x2A, 0xEA, 0xA0, 0x79, -0x2A, 0xEA, 0xA0, 0x79, 0x41, 0x55, 0x76, 0x87, -0x41, 0x63, 0x74, 0x87, 0x41, 0x55, 0x76, 0x87, -0x41, 0x63, 0x74, 0x87, 0x10, 0x60, 0xB8, 0x75, -0x10, 0x60, 0xB7, 0x75, 0x10, 0x60, 0xB8, 0x75, -0x10, 0x60, 0xB7, 0x75, 0x28, 0xEA, 0xA0, 0x79, -0x2C, 0xEA, 0xA0, 0x79, 0x28, 0xEA, 0xA0, 0x79, -0x2A, 0xEA, 0xA0, 0x79, 0x51, 0x64, 0x76, 0x87, -0x31, 0x64, 0x76, 0x87, 0x51, 0x64, 0x76, 0x87, -0x31, 0x64, 0x76, 0x87, 0x10, 0x70, 0xC9, 0x75, 0x10, 0x70, 0xC9, 0x75, 0x10, 0x70, 0xC9, 0x75, -0x10, 0x70, 0xC9, 0x75, 0x2A, 0xEA, 0xA0, 0x79, -0x2C, 0xEA, 0xA0, 0x97, 0x2A, 0xEA, 0xA0, 0x79, -0x2A, 0xEA, 0xA0, 0x79, 0x41, 0x55, 0x76, 0x87, -0x41, 0x63, 0x66, 0x86, 0x61, 0x55, 0x76, 0x87, -0x61, 0x63, 0x66, 0x86, 0x06, 0x00, 0x00, 0x00, -0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, -0x67, 0x3E, 0x00, 0x80, 0xC3, 0x3E, 0x00, 0x80, -0x57, 0x3F, 0x00, 0x80, 0xEB, 0x3F, 0x00, 0x80, -0x83, 0x40, 0x00, 0x80, 0x61, 0x4F, 0x00, 0x80, -0x5B, 0x4F, 0x00, 0x80, 0x67, 0x4F, 0x00, 0x80, -0x6D, 0x4F, 0x00, 0x80, 0x73, 0x4F, 0x00, 0x80, -0x79, 0x4F, 0x00, 0x80, 0x57, 0x9E, 0x00, 0x80, -0x61, 0x9E, 0x00, 0x80, 0x6F, 0x9E, 0x00, 0x80, -0xA1, 0x9E, 0x00, 0x80, 0xE7, 0x9E, 0x00, 0x80, -0xFF, 0x9E, 0x00, 0x80, 0x94, 0x0C, 0x94, 0x0E, -0x94, 0x18, 0x94, 0x1A, 0x09, 0x12, 0x1B, 0x24, -0x39, 0xB1, 0x00, 0x80, 0x85, 0xB1, 0x00, 0x80, -0x41, 0xB1, 0x00, 0x80, 0x77, 0xB1, 0x00, 0x80, -0x85, 0xB1, 0x00, 0x80, 0x85, 0xB1, 0x00, 0x80, -0x49, 0xB1, 0x00, 0x80, 0x51, 0xB1, 0x00, 0x80, -0x59, 0xB1, 0x00, 0x80, 0x61, 0xB1, 0x00, 0x80, -0x69, 0xB1, 0x00, 0x80, 0x71, 0xB1, 0x00, 0x80, -0x7F, 0xB1, 0x00, 0x80, 0x02, 0x04, 0x06, 0x08, -0x0A, 0x01, 0x0C, 0x0E, 0x10, 0x12, 0x03, 0x0B, -0x14, 0x16, 0x18, 0x05, 0x0D, 0x13, 0x1A, 0x1C, -0x07, 0x0F, 0x15, 0x19, 0x1E, 0x09, 0x11, 0x17, -0x1B, 0x1D, 0x00, 0x00, 0x01, 0x03, 0x05, 0x07, -0x09, 0x02, 0x0B, 0x0D, 0x0F, 0x11, 0x04, 0x0C, -0x13, 0x15, 0x17, 0x06, 0x0E, 0x14, 0x19, 0x1B, -0x08, 0x10, 0x16, 0x1A, 0x1D, 0x0A, 0x12, 0x18, -0x1C, 0x1E, 0x00, 0x00, 0x04, 0x08, 0x08, 0x08, -0x08, 0x08, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, -0x00, 0x04, 0x0C, 0x14, 0x1C, 0x24, 0x2C, 0x36, -0x40, 0x00, 0x00, 0x00, 0xB5, 0xD5, 0x00, 0x80, -0xCB, 0xD5, 0x00, 0x80, 0xB5, 0xD5, 0x00, 0x80, -0xCB, 0xD5, 0x00, 0x80, 0xB5, 0xD5, 0x00, 0x80, -0xCB, 0xD5, 0x00, 0x80, 0xF5, 0xD5, 0x00, 0x80, -0xF5, 0xD5, 0x00, 0x80, 0xF5, 0xD5, 0x00, 0x80, -0xB9, 0xD5, 0x00, 0x80, 0xDD, 0xD5, 0x00, 0x80, -0xDD, 0xD5, 0x00, 0x80, 0xB9, 0xD5, 0x00, 0x80, -0x09, 0xD6, 0x00, 0x80, 0x1F, 0xD6, 0x00, 0x80, +0x2A, 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0x00, 0x60, 0xB8, 0xFF, 0xFF, 0xFF, 0xFD, 0xE3, 0x00, 0x60, 0xB8, -0x00, 0x00, 0x00, 0x40, 0xE1, 0x00, 0x60, 0xB8, -0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, -0xCC, 0x00, 0x60, 0xB8, 0x02, 0x00, 0x60, 0xB8, -0xE8, 0x12, 0x64, 0xB8, 0xF8, 0x10, 0x60, 0xB8, +0x00, 0x00, 0x00, 0x01, 0xE1, 0x00, 0x60, 0xB8, +0x00, 0x00, 0x00, 0x60, 0xCC, 0x00, 0x60, 0xB8, +0x02, 0x00, 0x60, 0xB8, 0xE8, 0x12, 0x64, 0xB8, 0x00, 0x00, 0x00, 0x04, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xFF, 0x1F, 0x04, 0x00, 0x60, 0xB8, 0x04, 0x00, 0x64, 0xB8, 0x08, 0x00, 0x60, 0xB8, 0x08, 0x00, 0x64, 0xB8, 0x24, 0x00, 0x60, 0xB8, 0x80, 0x00, 0x60, 0xB8, -0x00, 0x00, 0x03, 0x00, 0xCC, 0x07, 0x64, 0xB8, -0x00, 0x00, 0x78, 0xB8, 0x00, 0x00, 0x70, 0xB8, -0x00, 0x0C, 0x01, 0x00, 0x77, 0x77, 0x77, 0x77, -0x50, 0x05, 0x64, 0xB8, 0x51, 0x05, 0x64, 0xB8, -0x08, 0x00, 0x00, 0xF8, 0x08, 0x70, 0x0A, 0xF8, -0x08, 0x50, 0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0x00, -0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0xE0, 0xFF, -0x00, 0x1C, 0x01, 0x88, 0x00, 0x00, 0x00, 0xFF, -0x08, 0x00, 0x45, 0x01, 0x48, 0x08, 0x46, 0x01, -0xFF, 0xFF, 0x0F, 0x00, 0xE0, 0x10, 0x05, 0x00, -0x00, 0x9C, 0x0A, 0x00, 0x08, 0x00, 0x85, 0x00, -0x48, 0x08, 0x46, 0x00, 0x60, 0x10, 0x05, 0x00, -0x88, 0x0C, 0x46, 0x01, 0x00, 0xCC, 0x0A, 0x00, -0x48, 0x00, 0x46, 0x00, 0x00, 0xDC, 0x0A, 0x00, -0x08, 0x00, 0x44, 0x01, 0xF2, 0x0D, 0x05, 0x00, -0xEF, 0x00, 0x05, 0x00, 0x6C, 0x08, 0x05, 0x00, -0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xC0, -0x00, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, +0x00, 0x00, 0x03, 0x00, 0xFF, 0xFF, 0xFF, 0xEF, +0xCC, 0x07, 0x64, 0xB8, 0x00, 0x00, 0x78, 0xB8, +0x00, 0x00, 0x70, 0xB8, 0x87, 0x02, 0x64, 0xB8, +0x00, 0x0C, 0x01, 0x00, 0xA8, 0x9F, 0x7B, 0x18, +0xA8, 0x87, 0x7B, 0x18, 0x77, 0x77, 0x77, 0x77, +0x08, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x3E, +0x00, 0x00, 0xE0, 0xFF, 0x00, 0x1C, 0x01, 0x88, +0x00, 0x00, 0x00, 0xFF, 0x08, 0x00, 0x45, 0x01, +0x48, 0x08, 0x46, 0x01, 0xFF, 0xFF, 0x0F, 0x00, +0xE0, 0x10, 0x05, 0x00, 0x00, 0x9C, 0x0A, 0x00, +0x08, 0x00, 0x85, 0x00, 0x48, 0x08, 0x46, 0x00, +0x60, 0x10, 0x05, 0x00, 0x88, 0x0C, 0x46, 0x01, +0x00, 0xCC, 0x0A, 0x00, 0x48, 0x00, 0x46, 0x00, +0x00, 0xDC, 0x0A, 0x00, 0x08, 0x00, 0x44, 0x01, +0xF2, 0x0D, 0x05, 0x00, 0xEF, 0x00, 0x05, 0x00, +0x6C, 0x08, 0x05, 0x00, 0x00, 0x00, 0x1F, 0x00, +0x00, 0x00, 0x00, 0xC0, 0x00, 0x0A, 0x08, 0x00, 0xCE, 0xEF, 0x0D, 0x00, 0xCE, 0xEF, 0x05, 0x00, 0x01, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xFF, 0x0F, 0x21, 0x00, 0x00, 0xE0, 0x45, 0x23, 0x01, 0x00, 0x08, 0x08, 0x00, 0xF8, 0x08, 0x07, 0x00, 0xF8, 0x08, 0x02, 0x00, 0xF8, 0x08, 0x03, 0x00, 0xF8, -0x00, 0x00, 0x00, 0x0F, 0x62, 0x06, 0x64, 0xB8, -0xB4, 0x06, 0x64, 0xB8, 0x06, 0x00, 0x00, 0x89, -0x00, 0x00, 0x00, 0x50, 0x40, 0x00, 0x07, 0x70, -0x02, 0x04, 0x00, 0xD8, 0x20, 0x01, 0x00, 0xD1, -0x40, 0x80, 0x03, 0x70, 0x02, 0x04, 0x02, 0xD8, -0x20, 0x01, 0x00, 0xDE, 0xDE, 0xBC, 0x0A, 0x00, -0x01, 0x00, 0x66, 0xB8, 0x00, 0x00, 0x02, 0x00, +0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x0F, +0x62, 0x06, 0x64, 0xB8, 0xB4, 0x06, 0x64, 0xB8, +0x06, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x50, +0x40, 0x00, 0x07, 0x70, 0x02, 0x04, 0x00, 0xD8, +0x20, 0x01, 0x00, 0xD1, 0x40, 0x80, 0x03, 0x70, +0x02, 0x04, 0x02, 0xD8, 0x20, 0x01, 0x00, 0xDE, +0x08, 0x70, 0x0A, 0xF8, 0x08, 0x50, 0x01, 0xF8, +0xDE, 0xBC, 0x0A, 0x00, 0x01, 0x00, 0x66, 0xB8, 0x00, 0x00, 0x66, 0xB8, 0x00, 0xFF, 0xFF, 0x00, 0xCD, 0x9B, 0x78, 0x56, 0x04, 0x1C, 0x66, 0xB8, 0xFF, 0xFF, 0xFF, 0x3F, 0x1F, 0x00, 0x60, 0xB8, @@ -290,30 +332,28 @@ u8 array_mp_8822b_fw_ap[] = { 0x04, 0xEA, 0xEF, 0xFD, 0x07, 0xEA, 0xEF, 0xFD, 0x08, 0xEA, 0xEF, 0xFD, 0x09, 0xEA, 0xEF, 0xFD, 0x0A, 0xEA, 0xEF, 0xFD, 0x00, 0xF0, 0x0F, 0x00, -0x00, 0xF0, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x0F, -0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0xF0, -0x00, 0xFC, 0x0F, 0x00, 0x80, 0x81, 0x81, 0x81, -0x81, 0x81, 0x01, 0x06, 0x00, 0x0E, 0x0E, 0x0E, -0x0E, 0x0E, 0x0E, 0x38, 0xE0, 0x80, 0x03, 0x00, -0x00, 0x00, 0x30, 0xC0, 0x00, 0x03, 0x0C, 0x00, -0x4A, 0x04, 0x64, 0xB8, 0x49, 0x04, 0x64, 0xB8, -0x01, 0x00, 0x60, 0xB8, 0x01, 0x00, 0x64, 0xB8, -0x02, 0x00, 0x64, 0xB8, 0x03, 0x00, 0x60, 0xB8, -0x03, 0x00, 0x64, 0xB8, 0x23, 0x04, 0x64, 0xB8, -0x30, 0x04, 0x64, 0xB8, 0x00, 0x00, 0x00, 0x02, -0x34, 0x04, 0x64, 0xB8, 0x04, 0x05, 0x07, 0x08, -0x00, 0x01, 0x01, 0x02, 0x81, 0x18, 0x66, 0xB8, +0x00, 0xF0, 0x3F, 0x00, 0x00, 0x00, 0xC0, 0xFF, +0x00, 0x00, 0x00, 0xF0, 0x00, 0xFC, 0x0F, 0x00, +0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x01, 0x06, +0x00, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x38, +0xE0, 0x80, 0x03, 0x00, 0x00, 0x00, 0x30, 0xC0, +0x00, 0x03, 0x0C, 0x00, 0x4A, 0x04, 0x64, 0xB8, +0x49, 0x04, 0x64, 0xB8, 0x02, 0x00, 0x64, 0xB8, +0x03, 0x00, 0x60, 0xB8, 0x03, 0x00, 0x64, 0xB8, +0x23, 0x04, 0x64, 0xB8, 0x30, 0x04, 0x64, 0xB8, +0x34, 0x04, 0x64, 0xB8, 0x01, 0x02, 0x02, 0x03, +0x00, 0x01, 0x01, 0x01, 0x81, 0x18, 0x66, 0xB8, 0x53, 0x04, 0x64, 0xB8, 0x80, 0x18, 0x66, 0xB8, 0x82, 0x18, 0x66, 0xB8, 0x83, 0x18, 0x66, 0xB8, 0x84, 0x18, 0x66, 0xB8, 0x85, 0x18, 0x66, 0xB8, -0x2D, 0x04, 0x64, 0xB8, 0xF0, 0x10, 0x60, 0xB8, -0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x0C, -0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0F, 0x00, +0x2D, 0x04, 0x64, 0xB8, 0xCF, 0x04, 0x64, 0xB8, +0xF0, 0x10, 0x60, 0xB8, 0x00, 0x00, 0xF0, 0x00, +0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0xC0, 0x00, -0x06, 0x00, 0x66, 0xB8, 0x08, 0x1C, 0x66, 0xB8, -0xFF, 0xFF, 0xCF, 0x3F, 0xFF, 0xFC, 0x3F, 0xFF, -0x50, 0x04, 0x64, 0xB8, 0x51, 0x04, 0x64, 0xB8, -0x52, 0x04, 0x64, 0xB8, 0x01, 0x1C, 0x66, 0xB8, +0x06, 0x00, 0x66, 0xB8, 0x50, 0x04, 0x64, 0xB8, +0x51, 0x04, 0x64, 0xB8, 0x52, 0x04, 0x64, 0xB8, +0x08, 0x1C, 0x66, 0xB8, 0xFF, 0xFF, 0xCF, 0x3F, +0xFF, 0xFC, 0x3F, 0xFF, 0x01, 0x1C, 0x66, 0xB8, 0x02, 0x1C, 0x66, 0xB8, 0x03, 0x1C, 0x66, 0xB8, 0x05, 0x1C, 0x66, 0xB8, 0x06, 0x1C, 0x66, 0xB8, 0x07, 0x1C, 0x66, 0xB8, 0x00, 0x10, 0x66, 0xB8, @@ -322,25 +362,25 @@ u8 array_mp_8822b_fw_ap[] = { 0x05, 0x10, 0x66, 0xB8, 0x0C, 0x10, 0x66, 0xB8, 0x02, 0x10, 0x66, 0xB8, 0x01, 0x10, 0x66, 0xB8, 0x0D, 0x10, 0x66, 0xB8, 0x06, 0x10, 0x66, 0xB8, -0x00, 0x00, 0x40, 0x00, 0x74, 0x57, 0x74, 0x00, +0xFF, 0xFF, 0xFF, 0x00, 0x74, 0x57, 0x74, 0x00, 0x47, 0x75, 0x47, 0x00, 0x70, 0x45, 0x70, 0x00, 0x17, 0x45, 0x17, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x70, 0x57, 0x70, 0x00, 0x17, 0x75, 0x17, 0x00, 0x00, 0x00, 0x00, 0x06, 0xFF, 0xFF, 0xFF, 0x0F, -0x00, 0x00, 0x00, 0x10, 0xFF, 0xFC, 0xFE, 0xFF, -0x92, 0x84, 0x10, 0x08, 0x12, 0x56, 0x09, 0x29, -0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x10, 0x08, -0x12, 0x56, 0x09, 0x21, 0x28, 0xEA, 0xA0, 0x79, -0xB9, 0xB2, 0x94, 0x91, 0x00, 0x00, 0x0C, 0x00, -0x00, 0x00, 0x80, 0x00, 0x0E, 0x08, 0x04, 0x00, -0x0C, 0x08, 0x04, 0x00, 0x00, 0xFF, 0xF9, 0xFF, -0x00, 0x00, 0xFE, 0x1F, 0x77, 0x65, 0x4F, 0x38, -0x00, 0x80, 0x03, 0x00, 0x18, 0x00, 0x70, 0xB8, -0x18, 0x00, 0x78, 0xB8, 0x0B, 0x00, 0x78, 0xB8, -0x0B, 0x00, 0x70, 0xB8, 0x02, 0x00, 0x78, 0xB8, -0x02, 0x00, 0x70, 0xB8, 0x96, 0x02, 0x64, 0xB8, +0xFF, 0xFC, 0xFE, 0xFF, 0x92, 0x84, 0x10, 0x08, +0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x01, 0x00, +0x00, 0x00, 0x10, 0x08, 0x00, 0x00, 0x40, 0x00, +0x28, 0xEA, 0xA0, 0x79, 0xB9, 0xB2, 0x94, 0x91, +0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x80, 0x00, +0x0E, 0x08, 0x04, 0x00, 0x0C, 0x08, 0x04, 0x00, +0x00, 0xFF, 0xF9, 0xFF, 0x00, 0x00, 0xFE, 0x1F, +0x77, 0x65, 0x4F, 0x38, 0x00, 0x80, 0x03, 0x00, +0x18, 0x00, 0x70, 0xB8, 0x18, 0x00, 0x78, 0xB8, +0x0B, 0x00, 0x78, 0xB8, 0x0B, 0x00, 0x70, 0xB8, +0x02, 0x00, 0x78, 0xB8, 0x02, 0x00, 0x70, 0xB8, 0x01, 0xA0, 0x02, 0x00, 0x94, 0x02, 0x64, 0xB8, 0x97, 0x02, 0x64, 0xB8, 0xCC, 0x01, 0x64, 0xB8, +0xCF, 0x01, 0x64, 0xB8, 0x34, 0x01, 0x64, 0xB8, 0x54, 0x02, 0x64, 0xB8, 0x50, 0x02, 0x64, 0xB8, 0x4C, 0x02, 0x64, 0xB8, 0x04, 0x00, 0x78, 0xB8, 0x48, 0x02, 0x64, 0xB8, 0x44, 0x02, 0x64, 0xB8, @@ -348,62 +388,81 @@ u8 array_mp_8822b_fw_ap[] = { 0x84, 0x04, 0x60, 0xB8, 0x84, 0x04, 0x64, 0xB8, 0xC8, 0x04, 0x60, 0xB8, 0xC8, 0x04, 0x64, 0xB8, 0x78, 0x04, 0x60, 0xB8, 0x78, 0x04, 0x64, 0xB8, -0x01, 0xEA, 0xEF, 0xFD, 0x02, 0xEA, 0xEF, 0xFD, -0xC8, 0x01, 0x64, 0xB8, 0xC9, 0x01, 0x64, 0xB8, -0xA0, 0x01, 0x64, 0xB8, 0x44, 0x00, 0x60, 0xB8, -0x60, 0x00, 0x60, 0xB8, 0x4C, 0x00, 0x60, 0xB8, -0xFF, 0xFF, 0xBF, 0xFF, 0x00, 0x00, 0x00, 0x05, -0x53, 0x05, 0x64, 0xB8, 0x77, 0x05, 0x64, 0xB8, -0x68, 0x05, 0x64, 0xB8, 0x80, 0x34, 0x00, 0xB8, -0x94, 0x01, 0x64, 0xB8, 0x34, 0x01, 0x64, 0xB8, -0x30, 0x01, 0x64, 0xB8, 0x24, 0x01, 0x64, 0xB8, -0x20, 0x01, 0x64, 0xB8, 0x24, 0x11, 0x64, 0xB8, -0x20, 0x11, 0x64, 0xB8, 0x2C, 0x11, 0x64, 0xB8, -0x28, 0x11, 0x64, 0xB8, 0x34, 0x11, 0x64, 0xB8, -0x30, 0x11, 0x64, 0xB8, 0x38, 0x01, 0x64, 0xB8, -0x3C, 0x11, 0x64, 0xB8, 0x38, 0x11, 0x64, 0xB8, -0xE4, 0x11, 0x64, 0xB8, 0xE0, 0x11, 0x64, 0xB8, -0x50, 0x00, 0x60, 0xB8, 0x54, 0x00, 0x60, 0xB8, -0x9A, 0x01, 0x64, 0xB8, 0x99, 0x01, 0x64, 0xB8, -0xC6, 0x01, 0x64, 0xB8, 0xE0, 0x12, 0x64, 0xB8, -0x02, 0x01, 0x64, 0xB8, 0x21, 0x05, 0x64, 0xB8, +0xBE, 0x05, 0x64, 0xB8, 0x01, 0xEA, 0xEF, 0xFD, +0x02, 0xEA, 0xEF, 0xFD, 0xC8, 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0x32, 0x5D, 0x3D, 0x30, 0x78, 0x25, 0x62, 0x58, 0x20, 0x00, 0x44, 0x65, 0x6C, 0x4D, 0x55, 0x3A, 0x25, 0x62, 0x78, 0x00, 0x00, 0x00, +0x50, 0x45, 0x52, 0x20, 0x52, 0x50, 0x54, 0x3A, +0x20, 0x6D, 0x69, 0x64, 0x25, 0x62, 0x58, 0x2C, +0x52, 0x3A, 0x25, 0x62, 0x78, 0x2C, 0x72, 0x74, +0x3A, 0x25, 0x62, 0x78, 0x2C, 0x62, 0x77, 0x3A, +0x25, 0x62, 0x78, 0x00, 0x50, 0x45, 0x52, 0x20, +0x52, 0x50, 0x54, 0x3A, 0x20, 0x6D, 0x69, 0x64, +0x25, 0x62, 0x58, 0x2C, 0x54, 0x54, 0x3A, 0x25, +0x77, 0x78, 0x00, 0x00, 0x50, 0x45, 0x52, 0x20, +0x52, 0x50, 0x54, 0x3A, 0x20, 0x25, 0x62, 0x58, +0x2C, 0x25, 0x62, 0x78, 0x2C, 0x25, 0x62, 0x78, +0x2C, 0x25, 0x62, 0x78, 0x2C, 0x25, 0x62, 0x58, +0x2C, 0x25, 0x62, 0x78, 0x2C, 0x25, 0x62, 0x78, +0x2C, 0x25, 0x62, 0x78, 0x2C, 0x25, 0x62, 0x58, +0x2C, 0x25, 0x62, 0x78, 0x2C, 0x25, 0x62, 0x78, +0x2C, 0x25, 0x62, 0x78, 0x00, 0x00, 0x00, 0x00, +0x52, 0x65, 0x71, 0x20, 0x50, 0x45, 0x52, 0x20, +0x43, 0x4D, 0x44, 0x3A, 0x20, 0x47, 0x72, 0x3A, +0x25, 0x62, 0x58, 0x2C, 0x20, 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0x1F, 0x20, 0x20, 0x20, +0x36, 0x36, 0x37, 0x37, 0x38, 0x39, 0x39, 0x3A, +0x3A, 0x3A, 0x00, 0x00, 0x40, 0x40, 0x40, 0x40, +0x41, 0x41, 0x42, 0x42, 0x43, 0x43, 0x00, 0x00, +0x40, 0x40, 0x41, 0x42, 0x43, 0x44, 0x44, 0x44, +0x45, 0x46, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, +0x00, 0x00, 0x30, 0xC0, 0xE0, 0x00, 0x00, 0x00, +0x00, 0x0C, 0x0E, 0x38, 0x18, 0x00, 0x00, 0x00, +0x00, 0x83, 0x01, 0x06, 0x80, 0x03, 0x00, 0x00, +0x00, 0x00, 0x70, 0xE0, 0x00, 0x00, 0x00, 0x00, +0x61, 0x8F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1410,63 +1582,63 @@ u8 array_mp_8822b_fw_ap[] = { 0x00, 0x6E, 0x30, 0xF0, 0x20, 0x6F, 0x00, 0xF0, 0x00, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, 0xE3, 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-0x04, 0x4A, 0x00, 0xF0, 0x20, 0x6B, 0x60, 0xDA, -0x30, 0xF0, 0x20, 0x6A, 0xEF, 0xF7, 0x1C, 0x4A, +0x00, 0x65, 0x30, 0xF0, 0x21, 0x6A, 0xB1, 0xF6, +0x10, 0x4A, 0x00, 0xF0, 0x20, 0x6B, 0x60, 0xDA, +0x30, 0xF0, 0x21, 0x6A, 0x11, 0xF7, 0x08, 0x4A, 0x60, 0x9A, 0x41, 0x9A, 0x6A, 0xEA, 0x0D, 0x61, 0x6E, 0xB8, 0x00, 0x65, 0x62, 0x43, 0xCB, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x5A, 0xB8, @@ -1479,13 +1651,13 @@ u8 array_mp_8822b_fw_ap[] = { 0x84, 0xDB, 0x9B, 0xB8, 0x00, 0x65, 0x85, 0xDB, 0x8E, 0xB8, 0x00, 0x65, 0x82, 0x44, 0x81, 0xDB, 0x8C, 0xB8, 0x00, 0x65, 0x80, 0xDB, 0x30, 0xF0, -0x20, 0x6B, 0xEF, 0xF7, 0x1C, 0x4B, 0x60, 0x9B, +0x21, 0x6B, 0x11, 0xF7, 0x08, 0x4B, 0x60, 0x9B, 0x9D, 0x67, 0x89, 0xDB, 0x6A, 0x9B, 0xCF, 0xF7, 0x80, 0x44, 0x62, 0xEC, 0x0D, 0x60, 0x77, 0xF0, 0x24, 0x6C, 0xA0, 0xF1, 0x1C, 0x4C, 0x1D, 0xF4, 0x01, 0x6B, 0x60, 0xDC, 0x10, 0xF0, 0x20, 0x6C, -0x85, 0xF1, 0x1D, 0x4C, 0x00, 0xEC, 0x00, 0x65, -0x30, 0xF0, 0x20, 0x6B, 0xEF, 0xF7, 0x1C, 0x4B, +0xA6, 0xF1, 0x01, 0x4C, 0x00, 0xEC, 0x00, 0x65, +0x30, 0xF0, 0x21, 0x6B, 0x11, 0xF7, 0x08, 0x4B, 0x41, 0x9B, 0x40, 0xDB, 0x89, 0x9A, 0xBC, 0x65, 0x7D, 0x67, 0xDF, 0xF7, 0x00, 0x03, 0x4C, 0xB8, 0x00, 0x65, 0x00, 0xF0, 0x20, 0x6D, 0x05, 0x4D, @@ -1507,7 +1679,7 @@ u8 array_mp_8822b_fw_ap[] = { 0x9A, 0xB8, 0x00, 0x65, 0x84, 0xDB, 0x9B, 0xB8, 0x00, 0x65, 0x85, 0xDB, 0x7D, 0x67, 0x5B, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x40, 0x9A, -0x30, 0xF0, 0x21, 0x6C, 0x30, 0xF3, 0x18, 0x4C, +0x30, 0xF0, 0x21, 0x6C, 0x52, 0xF2, 0x04, 0x4C, 0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65, 0x82, 0x67, 0x40, 0xEA, 0x00, 0x65, 0x7A, 0xB8, 0x00, 0x65, 0xBB, 0x65, 0xDF, 0xF7, 0x00, 0x03, 0x82, 0x9B, @@ -1518,8 +1690,8 @@ u8 array_mp_8822b_fw_ap[] = { 0x00, 0x65, 0x2B, 0x9B, 0x0A, 0x9B, 0xE9, 0x9B, 0xC8, 0x9B, 0xA7, 0x9B, 0x86, 0x9B, 0x5A, 0xB8, 0x00, 0x65, 0x7B, 0xB8, 0x00, 0x65, 0x00, 0xBA, -0x00, 0x65, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6B, -0xAF, 0xF7, 0x04, 0x4B, 0x40, 0xDB, 0xDF, 0xF7, +0x00, 0x65, 0x00, 0x65, 0x30, 0xF0, 0x21, 0x6B, +0xB1, 0xF6, 0x10, 0x4B, 0x40, 0xDB, 0xDF, 0xF7, 0x00, 0x03, 0x86, 0xDB, 0xA7, 0xDB, 0xC8, 0xDB, 0xE9, 0xDB, 0x0A, 0xDB, 0x2B, 0xDB, 0x98, 0x67, 0x8C, 0xDB, 0x9F, 0x67, 0x8E, 0xDB, 0x12, 0xEC, @@ -1527,18 +1699,18 @@ u8 array_mp_8822b_fw_ap[] = { 0x00, 0x65, 0x84, 0xDB, 0x9B, 0xB8, 0x00, 0x65, 0x85, 0xDB, 0x8E, 0xB8, 0x00, 0x65, 0x81, 0xDB, 0x8C, 0xB8, 0x00, 0x65, 0x80, 0xDB, 0x30, 0xF0, -0x20, 0x6B, 0xEF, 0xF7, 0x1C, 0x4B, 0x60, 0x9B, +0x21, 0x6B, 0x11, 0xF7, 0x08, 0x4B, 0x60, 0x9B, 0x9D, 0x67, 0x89, 0xDB, 0x6A, 0x9B, 0xCF, 0xF7, 0x80, 0x44, 0x62, 0xEC, 0x0D, 0x60, 0x77, 0xF0, 0x24, 0x6C, 0xA0, 0xF1, 0x1C, 0x4C, 0x1D, 0xF4, 0x01, 0x6B, 0x60, 0xDC, 0x10, 0xF0, 0x20, 0x6C, -0x85, 0xF1, 0x1D, 0x4C, 0x00, 0xEC, 0x00, 0x65, -0x40, 0x9A, 0x30, 0xF0, 0x21, 0x6C, 0x30, 0xF3, -0x18, 0x4C, 0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65, -0x82, 0x67, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6C, -0xAF, 0xF7, 0x04, 0x4C, 0x00, 0xF0, 0x20, 0x6D, -0xA0, 0xDC, 0x30, 0xF0, 0x20, 0x6A, 0xEF, 0xF7, -0x1C, 0x4A, 0x10, 0xF0, 0x20, 0x6B, 0x40, 0xF6, +0xA6, 0xF1, 0x01, 0x4C, 0x00, 0xEC, 0x00, 0x65, +0x40, 0x9A, 0x30, 0xF0, 0x21, 0x6C, 0x52, 0xF2, +0x04, 0x4C, 0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65, +0x82, 0x67, 0x40, 0xEA, 0x30, 0xF0, 0x21, 0x6C, +0xB1, 0xF6, 0x10, 0x4C, 0x00, 0xF0, 0x20, 0x6D, +0xA0, 0xDC, 0x30, 0xF0, 0x21, 0x6A, 0x11, 0xF7, +0x08, 0x4A, 0x10, 0xF0, 0x20, 0x6B, 0x40, 0xF6, 0x1D, 0x4B, 0x00, 0xEB, 0x61, 0x9A, 0x60, 0xDA, 0x49, 0x9B, 0xBA, 0x65, 0xDF, 0xF7, 0x00, 0x03, 0x4C, 0xB8, 0x00, 0x65, 0x00, 0xF0, 0x20, 0x6D, @@ -1556,234 +1728,403 @@ u8 array_mp_8822b_fw_ap[] = { 0x5A, 0xB8, 0x00, 0x65, 0x00, 0xBA, 0x00, 0x65, 0x5F, 0x67, 0x5A, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x00, 0x18, 0xCA, 0x00, 0x00, 0x18, -0x2E, 0x09, 0x5A, 0xB8, 0x00, 0x65, 0x00, 0xEA, +0x2F, 0x0B, 0x5A, 0xB8, 0x00, 0x65, 0x00, 0xEA, 0x6D, 0xB8, 0x00, 0xF0, 0x20, 0x6A, 0x00, 0xF2, 0x00, 0x4A, 0x4F, 0xEA, 0x4C, 0xEB, 0xAB, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x5F, 0x67, 0x5A, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 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0xF1, 0x55, 0xC3, 0x20, 0xE8, +0x30, 0xF0, 0x20, 0x6B, 0x45, 0xF6, 0x18, 0x4B, +0x43, 0xF3, 0xBD, 0xA3, 0x8C, 0xEA, 0x8F, 0xEC, +0xAC, 0xEC, 0x8D, 0xEA, 0x43, 0xF3, 0x5D, 0xC3, 0x20, 0xE8, 0x00, 0x65, 0xF7, 0x63, 0x11, 0x62, 0x10, 0xD1, 0x0F, 0xD0, 0x40, 0xA4, 0x08, 0xD2, 0x08, 0x93, 0x1F, 0x6A, 0x4C, 0xEB, 0x08, 0xD3, @@ -1792,110 +2133,185 @@ u8 array_mp_8822b_fw_ap[] = { 0x80, 0xF0, 0x0C, 0x60, 0x84, 0x31, 0x09, 0x94, 0x01, 0x2C, 0x23, 0x22, 0xFF, 0x68, 0x0C, 0xEA, 0x0C, 0xEB, 0xA2, 0x67, 0xC3, 0x67, 0x91, 0x67, -0x0B, 0xD2, 0x0C, 0xD3, 0x00, 0x18, 0x68, 0x03, +0x0B, 0xD2, 0x0C, 0xD3, 0x00, 0x18, 0xBA, 0x04, 0x09, 0x93, 0x0D, 0x94, 0x41, 0x41, 0x0C, 0xEA, 0x0C, 0xEB, 0x8C, 0xE8, 0xA3, 0x67, 0x82, 0x67, 0xD0, 0x67, 0x0A, 0xD2, 0x09, 0xD3, 0x00, 0x18, -0x68, 0x03, 0x0B, 0x95, 0x0C, 0x96, 0x91, 0x67, -0x01, 0x6F, 0x00, 0x18, 0x27, 0x04, 0x0A, 0x94, +0xBA, 0x04, 0x0B, 0x95, 0x0C, 0x96, 0x91, 0x67, +0x01, 0x6F, 0x00, 0x18, 0x0C, 0x06, 0x0A, 0x94, 0x09, 0x95, 0xD0, 0x67, 0x02, 0x6F, 0x00, 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0x80, 0xA8, 0xC1, 0x98, 0x01, 0x6D, 0xAB, 0xED, 0x00, 0x18, -0xF8, 0x1B, 0x02, 0x49, 0x08, 0x48, 0x04, 0x92, +0x0E, 0x29, 0x02, 0x49, 0x08, 0x48, 0x04, 0x92, 0x43, 0xE9, 0xF5, 0x61, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0, @@ -2370,7 +2798,7 @@ u8 array_mp_8822b_fw_ap[] = { 0x48, 0x34, 0x91, 0xE1, 0xE1, 0xF7, 0x1E, 0x73, 0xE0, 0x9C, 0x02, 0x61, 0x02, 0x67, 0x09, 0x10, 0xFF, 0xF7, 0x1F, 0x6D, 0x01, 0x6E, 0x01, 0x6C, -0x6C, 0xED, 0xCB, 0xEE, 0x00, 0x18, 0x1E, 0x1C, +0x6C, 0xED, 0xCB, 0xEE, 0x00, 0x18, 0x34, 0x29, 0x02, 0x48, 0x04, 0x93, 0x41, 0x40, 0x63, 0xEA, 0xE8, 0x61, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62, @@ -2380,1632 +2808,2550 @@ u8 array_mp_8822b_fw_ap[] = { 0xE1, 0xF7, 0x1E, 0x73, 0xE0, 0x9C, 0x02, 0x61, 0x02, 0x67, 0x09, 0x10, 0xFF, 0xF7, 0x1F, 0x6D, 0x01, 0x6E, 0x00, 0x6C, 0x6C, 0xED, 0xCB, 0xEE, -0x00, 0x18, 0x1E, 0x1C, 0x02, 0x48, 0x04, 0x93, +0x00, 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0x03, 0x6A, 0x0A, 0x60, 0x10, 0x24, @@ -4892,9 +6739,9 @@ u8 array_mp_8822b_fw_ap[] = { 0x06, 0xD1, 0x05, 0xD0, 0xFF, 0x6B, 0x8C, 0xEB, 0xFF, 0xF7, 0x1F, 0x6A, 0x81, 0x46, 0x26, 0x67, 0xAC, 0xEA, 0x06, 0x2C, 0x83, 0x67, 0xA2, 0x67, -0x00, 0x18, 0x89, 0x1B, 0x02, 0x67, 0x0A, 0x10, -0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0x89, 0x1B, -0x02, 0x67, 0x91, 0x67, 0x00, 0x18, 0x7B, 0x14, +0x00, 0x18, 0x9F, 0x28, 0x02, 0x67, 0x0A, 0x10, +0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0x9F, 0x28, +0x02, 0x67, 0x91, 0x67, 0x00, 0x18, 0x88, 0x1D, 0x2C, 0xE8, 0x06, 0xEA, 0x50, 0x67, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0, @@ -4902,697 +6749,1381 @@ u8 array_mp_8822b_fw_ap[] = { 0xFF, 0xF7, 0x1F, 0x6A, 0x4C, 0xED, 0x4C, 0xE9, 0x0C, 0xD6, 0x0D, 0xD7, 0x0F, 0x90, 0x05, 0xD5, 0x00, 0x6A, 0x05, 0x10, 0x0A, 0x6C, 0x00, 0x18, -0x51, 0x15, 0x40, 0xA8, 0x01, 0x4A, 0x40, 0xC8, +0x7D, 0x1E, 0x40, 0xA8, 0x01, 0x4A, 0x40, 0xC8, 0x30, 0xF0, 0x20, 0x6A, 0x04, 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0xF3, 0x00, 0x4C, 0x00, 0x18, +0x76, 0x40, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFB, 0x63, 0x09, 0xD1, 0x08, 0xD0, 0x0A, 0xD4, 0x44, 0x67, 0x82, 0x10, 0x25, 0x73, 0x04, 0x60, 0x60, 0xA5, 0x60, 0xC2, @@ -6606,8 +9178,8 @@ u8 array_mp_8822b_fw_ap[] = { 0x7D, 0x67, 0x20, 0x61, 0x62, 0x85, 0x78, 0x73, 0x03, 0x60, 0x58, 0x73, 0x7D, 0x67, 0x1A, 0x61, 0x82, 0x85, 0x60, 0xA6, 0x78, 0x6F, 0xEE, 0xEC, -0x30, 0xF0, 0x20, 0x6F, 0x72, 0x30, 0x41, 0xF6, -0x14, 0x4F, 0xE1, 0xE0, 0x00, 0xA0, 0x01, 0x5C, +0x30, 0xF0, 0x20, 0x6F, 0x72, 0x30, 0x02, 0xF0, +0x1C, 0x4F, 0xE1, 0xE0, 0x00, 0xA0, 0x01, 0x5C, 0x98, 0x67, 0x94, 0x34, 0x8D, 0xE8, 0x3D, 0x67, 0x00, 0xC1, 0x0F, 0x68, 0x6C, 0xE8, 0xFD, 0xE0, 0x60, 0xA7, 0x02, 0x4D, 0x8D, 0xEB, 0x61, 0xC1, @@ -6617,8 +9189,8 @@ u8 array_mp_8822b_fw_ap[] = { 0x07, 0xD4, 0x82, 0x85, 0x78, 0x74, 0xF8, 0x67, 0x01, 0x5F, 0x18, 0x67, 0x14, 0x30, 0x18, 0x65, 0x0C, 0x6C, 0x07, 0x97, 0x0F, 0x68, 0x30, 0xF0, -0x20, 0x69, 0xE7, 0xEC, 0x0C, 0xEF, 0x41, 0xF6, -0x14, 0x49, 0x3D, 0xE7, 0xE0, 0xA7, 0x06, 0x90, +0x20, 0x69, 0xE7, 0xEC, 0x0C, 0xEF, 0x02, 0xF0, +0x1C, 0x49, 0x3D, 0xE7, 0xE0, 0xA7, 0x06, 0x90, 0x38, 0x67, 0x2D, 0xEF, 0xFC, 0x4C, 0xE0, 0xC0, 0x01, 0x48, 0xE4, 0x44, 0x06, 0xD0, 0xED, 0x2F, 0x04, 0x4B, 0x02, 0x4D, 0x25, 0x10, 0x81, 0x85, @@ -6627,7 +9199,7 @@ u8 array_mp_8822b_fw_ap[] = { 0x98, 0x67, 0x01, 0x5C, 0xF8, 0x67, 0xF4, 0x37, 0x07, 0xD1, 0x1F, 0x65, 0x1C, 0x6C, 0x07, 0x97, 0x0F, 0x68, 0x30, 0xF0, 0x20, 0x69, 0xE6, 0xEC, -0x0C, 0xEF, 0x41, 0xF6, 0x14, 0x49, 0x3D, 0xE7, +0x0C, 0xEF, 0x02, 0xF0, 0x1C, 0x49, 0x3D, 0xE7, 0xE0, 0xA7, 0x06, 0x91, 0x18, 0x67, 0x0D, 0xEF, 0xFC, 0x4C, 0xE0, 0xC1, 0x01, 0x49, 0xE4, 0x44, 0x06, 0xD1, 0xED, 0x2F, 0x08, 0x4B, 0x01, 0x4D, @@ -6636,706 +9208,945 @@ u8 array_mp_8822b_fw_ap[] = { 0x04, 0x4E, 0x01, 0x4D, 0x60, 0x85, 0x7F, 0xF7, 0x1B, 0x2B, 0x0A, 0x94, 0x01, 0x24, 0x60, 0xC2, 0x0A, 0x97, 0x09, 0x91, 0x08, 0x90, 0xEB, 0xE2, -0x05, 0x63, 0x20, 0xE8, 0xFD, 0x63, 0x05, 0x62, -0xFF, 0x6A, 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0x9D, 0x20, 0x9D, 0xE4, 0x35, 0xC1, 0xE0, +0xB5, 0xE0, 0x79, 0xE6, 0x55, 0xE5, 0x49, 0xE6, +0x44, 0x32, 0x55, 0xE5, 0x00, 0x6A, 0x0A, 0x25, +0x6B, 0xEB, 0xFF, 0xE3, 0x27, 0xE7, 0x93, 0xE1, +0xB1, 0xE4, 0x83, 0xED, 0x64, 0x6A, 0x02, 0x61, +0x00, 0x18, 0x3F, 0x43, 0x07, 0x97, 0x06, 0x91, +0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFF, 0x6A, 0x4C, 0xEC, 0x20, 0x5C, 0x01, 0x6B, 0x03, 0x60, 0xE0, 0x4C, 0x4C, 0xEC, 0x00, 0x6B, 0x68, 0x33, 0x75, 0xE5, 0x01, 0x6B, 0x64, 0xEC, @@ -7344,24 +10155,24 @@ u8 array_mp_8822b_fw_ap[] = { 0xFF, 0x6B, 0x44, 0x67, 0x6C, 0xEA, 0x6C, 0xEE, 0x6C, 0xED, 0x82, 0x67, 0x03, 0x26, 0x88, 0x42, 0xE8, 0x4C, 0x6C, 0xEC, 0x20, 0x5C, 0x0B, 0x61, -0x30, 0xF0, 0x20, 0x6B, 0xE0, 0xF7, 0x6C, 0x9B, +0x30, 0xF0, 0x20, 0x6B, 0x21, 0xF1, 0x7C, 0x9B, 0xAC, 0x35, 0xE0, 0x4C, 0x75, 0xE5, 0xFF, 0x6B, 0xA0, 0x9D, 0x6C, 0xEC, 0x07, 0x10, 0x30, 0xF0, -0x20, 0x6B, 0x01, 0xF0, 0x60, 0x9B, 0xAC, 0x35, +0x20, 0x6B, 0x41, 0xF1, 0x70, 0x9B, 0xAC, 0x35, 0x75, 0xE5, 0xA0, 0x9D, 0x01, 0x6B, 0x64, 0xEC, 0xAC, 0xEB, 0x01, 0x2B, 0xFF, 0x6A, 0x20, 0xE8, -0xFF, 0x6A, 0x8C, 0xEA, 0x2A, 0x6B, 0x78, 0xEA, -0x30, 0xF0, 0x20, 0x6B, 0x68, 0xF4, 0x1C, 0x4B, +0xFF, 0x6A, 0x8C, 0xEA, 0x2E, 0x6B, 0x78, 0xEA, +0x30, 0xF0, 0x20, 0x6B, 0x89, 0xF7, 0x18, 0x4B, 0x12, 0xEA, 0x49, 0xE3, 0x93, 0xA2, 0x7F, 0x6B, 0x6C, 0xEC, 0x93, 0xC2, 0x92, 0xA2, 0x8C, 0xEB, 0x72, 0xC2, 0x20, 0xE8, 0xFF, 0x6A, 0xAC, 0xEA, 0x20, 0xE8, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0x7F, 0x68, 0x8C, 0xE8, 0x90, 0x67, -0x00, 0x18, 0x82, 0x2C, 0x01, 0x6B, 0x12, 0x2A, -0x90, 0x67, 0x00, 0x18, 0x92, 0x2C, 0x02, 0x6B, -0x0D, 0x2A, 0x90, 0x67, 0x00, 0x18, 0xA2, 0x2C, +0x00, 0x18, 0x1F, 0x41, 0x01, 0x6B, 0x12, 0x2A, +0x90, 0x67, 0x00, 0x18, 0x2F, 0x41, 0x02, 0x6B, +0x0D, 0x2A, 0x90, 0x67, 0x00, 0x18, 0x3F, 0x41, 0x03, 0x6B, 0x08, 0x2A, 0x90, 0x67, 0x00, 0x18, -0xB3, 0x2C, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7, +0x50, 0x41, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7, 0x62, 0x33, 0x68, 0x33, 0x05, 0x97, 0x04, 0x90, 0x43, 0x67, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFF, 0x63, 0xFF, 0x6B, 0xBD, 0x67, 0x20, 0xF4, @@ -7369,16 +10180,16 @@ u8 array_mp_8822b_fw_ap[] = { 0x20, 0xF4, 0x0F, 0x6A, 0x41, 0xCD, 0x91, 0xE5, 0x80, 0xAC, 0x1F, 0xF7, 0x00, 0x6A, 0x8C, 0xEA, 0x02, 0xF0, 0x00, 0x72, 0x01, 0x60, 0x0A, 0x2A, -0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF6, 0x4C, 0x9A, +0x30, 0xF0, 0x20, 0x6A, 0x00, 0xF7, 0x5C, 0x9A, 0x51, 0xE4, 0x60, 0xA4, 0x0E, 0x6A, 0x6C, 0xEA, 0x46, 0x32, 0x0A, 0x10, 0x30, 0xF0, 0x20, 0x6A, -0x80, 0xF6, 0x50, 0x9A, 0x51, 0xE4, 0x80, 0xA4, +0x20, 0xF7, 0x40, 0x9A, 0x51, 0xE4, 0x80, 0xA4, 0x0E, 0x6A, 0x8C, 0xEA, 0x47, 0x32, 0x6C, 0xEA, 0x01, 0x63, 0x20, 0xE8, 0xFF, 0x63, 0x01, 0xD1, -0x00, 0xD0, 0xFF, 0x68, 0x0C, 0xEC, 0x2A, 0x6A, -0x58, 0xEC, 0x30, 0xF0, 0x20, 0x6A, 0x68, 0xF4, -0x1C, 0x4A, 0xCC, 0xE8, 0x60, 0xA5, 0x12, 0xEC, -0x91, 0xE2, 0x30, 0xF0, 0x20, 0x6A, 0x81, 0xF0, +0x00, 0xD0, 0xFF, 0x68, 0x0C, 0xEC, 0x2E, 0x6A, +0x58, 0xEC, 0x30, 0xF0, 0x20, 0x6A, 0x89, 0xF7, +0x18, 0x4A, 0xCC, 0xE8, 0x60, 0xA5, 0x12, 0xEC, +0x91, 0xE2, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF1, 0x48, 0x9A, 0xE0, 0xA4, 0xC1, 0xA4, 0x40, 0xA2, 0x1A, 0x65, 0x38, 0x67, 0x20, 0x6A, 0x2C, 0xEA, 0x25, 0x2A, 0xFF, 0x73, 0x01, 0x6A, 0x23, 0x60, @@ -7392,8 +10203,8 @@ u8 array_mp_8822b_fw_ap[] = { 0x80, 0xA5, 0x80, 0x6A, 0x4B, 0xEA, 0x8C, 0xEA, 0x6D, 0xEA, 0x40, 0xC5, 0x00, 0x6A, 0x01, 0x91, 0x00, 0x90, 0x01, 0x63, 0x20, 0xE8, 0x00, 0x65, -0xFF, 0x6A, 0x4C, 0xEC, 0x2A, 0x6B, 0x78, 0xEC, -0x30, 0xF0, 0x20, 0x6B, 0x68, 0xF4, 0x1C, 0x4B, +0xFF, 0x6A, 0x4C, 0xEC, 0x2E, 0x6B, 0x78, 0xEC, +0x30, 0xF0, 0x20, 0x6B, 0x89, 0xF7, 0x18, 0x4B, 0x19, 0x6E, 0xCB, 0xEE, 0x4C, 0xED, 0x12, 0xEC, 0x91, 0xE3, 0x72, 0xA4, 0x6C, 0xEE, 0x04, 0x6B, 0xCC, 0xEB, 0x4C, 0xEB, 0xD2, 0xC4, 0x53, 0x23, @@ -7421,58 +10232,59 @@ u8 array_mp_8822b_fw_ap[] = { 0x20, 0xE8, 0x45, 0x6A, 0x20, 0xE8, 0x3D, 0x6A, 0x20, 0xE8, 0x33, 0x6A, 0x20, 0xE8, 0x00, 0x65, 0xFF, 0x63, 0x01, 0xD0, 0xFF, 0x6A, 0x4C, 0xEC, -0x2A, 0x6B, 0x78, 0xEC, 0x30, 0xF0, 0x20, 0x6B, -0x68, 0xF4, 0x1C, 0x4B, 0x19, 0x6E, 0xCB, 0xEE, +0x2E, 0x6B, 0x78, 0xEC, 0x30, 0xF0, 0x20, 0x6B, +0x89, 0xF7, 0x18, 0x4B, 0x19, 0x6E, 0xCB, 0xEE, 0x4C, 0xED, 0x12, 0xEC, 0x91, 0xE3, 0x72, 0xA4, 0x6C, 0xEE, 0x04, 0x6B, 0xCC, 0xEB, 0x4C, 0xEB, -0xD2, 0xC4, 0x51, 0x23, 0xD0, 0xA4, 0x80, 0x6B, -0x6B, 0xEB, 0xCC, 0xEB, 0x4C, 0xEB, 0x4B, 0x23, +0xD2, 0xC4, 0x56, 0x23, 0xD0, 0xA4, 0x80, 0x6B, +0x6B, 0xEB, 0xCC, 0xEB, 0x4C, 0xEB, 0x50, 0x23, 0x0E, 0xA4, 0x07, 0x6F, 0x7F, 0x6B, 0x0C, 0xEF, 0x4C, 0xEF, 0x80, 0x6E, 0x03, 0x77, 0xAC, 0xEB, 0xAC, 0xEE, 0x14, 0x61, 0x45, 0x73, 0x09, 0x61, 0xF1, 0xA4, 0x0C, 0x6A, 0xEC, 0xEA, 0x08, 0x72, -0x04, 0x61, 0x47, 0x6A, 0x39, 0x2E, 0xC5, 0x6A, -0x37, 0x10, 0x48, 0x43, 0xC3, 0x4A, 0xFF, 0x6F, -0xEC, 0xEA, 0x04, 0x5A, 0x30, 0x60, 0x00, 0x6A, +0x04, 0x61, 0x47, 0x6A, 0x3E, 0x2E, 0xC5, 0x6A, +0x3C, 0x10, 0x48, 0x43, 0xC3, 0x4A, 0xFF, 0x6F, +0xEC, 0xEA, 0x04, 0x5A, 0x35, 0x60, 0x00, 0x6A, 0xC8, 0x75, 0x13, 0x10, 0x02, 0x77, 0x08, 0x61, 0xE8, 0x43, 0xCB, 0x4F, 0x4C, 0xEF, 0x02, 0x5F, -0x26, 0x60, 0x00, 0x6A, 0xBE, 0x75, 0x09, 0x10, -0x01, 0x77, 0x21, 0x61, 0xE8, 0x43, 0xD5, 0x4F, -0x4C, 0xEF, 0x02, 0x5F, 0x1C, 0x60, 0x00, 0x6A, -0xB4, 0x75, 0x01, 0x60, 0x01, 0x6A, 0x10, 0x22, -0x03, 0x26, 0x01, 0x4B, 0xFF, 0x6A, 0x4C, 0xEB, -0xB2, 0xA4, 0x41, 0x43, 0x45, 0xC4, 0x19, 0x6A, -0x4B, 0xEA, 0xAC, 0xEA, 0x08, 0x6D, 0xAD, 0xEA, -0x52, 0xC4, 0x80, 0x6A, 0x4B, 0xEA, 0x03, 0x10, -0x41, 0x43, 0x80, 0x6B, 0x6B, 0xEB, 0x6D, 0xEA, -0xFF, 0x6B, 0x6C, 0xEA, 0x01, 0x10, 0xFF, 0x6A, -0x01, 0x90, 0x01, 0x63, 0x20, 0xE8, 0x00, 0x65, +0x2B, 0x60, 0x00, 0x6A, 0xBE, 0x75, 0x09, 0x10, +0x01, 0x77, 0x26, 0x61, 0xE8, 0x43, 0xD5, 0x4F, +0x4C, 0xEF, 0x02, 0x5F, 0x21, 0x60, 0x00, 0x6A, +0xB4, 0x75, 0x01, 0x60, 0x01, 0x6A, 0x15, 0x22, +0x05, 0x26, 0x80, 0x6D, 0x41, 0x43, 0xAB, 0xED, +0xAD, 0xEA, 0x03, 0x10, 0x80, 0x6A, 0x4B, 0xEA, +0x6D, 0xEA, 0xFF, 0x6D, 0x01, 0x4B, 0xAC, 0xEA, +0xB2, 0xA4, 0x65, 0xC4, 0x19, 0x6B, 0x6B, 0xEB, +0xAC, 0xEB, 0x08, 0x6D, 0xAD, 0xEB, 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0x6B, 0x45, 0xF6, +0x18, 0x4B, 0x44, 0x32, 0x69, 0xE2, 0x63, 0xAA, 0xFF, 0xF7, 0x1F, 0x6C, 0x13, 0xE4, 0x63, 0xEC, -0x03, 0x61, 0x61, 0xE0, 0x05, 0xCA, 0x03, 0x10, -0x01, 0x6B, 0x6B, 0xEB, 0x65, 0xCA, 0x01, 0x91, +0x03, 0x61, 0x61, 0xE0, 0x03, 0xCA, 0x03, 0x10, +0x01, 0x6B, 0x6B, 0xEB, 0x63, 0xCA, 0x01, 0x91, 0x00, 0x90, 0x01, 0x63, 0x20, 0xE8, 0x00, 0x65, 0xFF, 0x6B, 0x6C, 0xED, 0x6C, 0xEC, 0x0F, 0x2D, 0x48, 0x44, 0xFC, 0x4A, 0x6C, 0xEA, 0x08, 0x5A, @@ -7484,70 +10296,76 @@ u8 array_mp_8822b_fw_ap[] = { 0x07, 0x61, 0x48, 0x44, 0xC8, 0x4A, 0x6C, 0xEA, 0x0A, 0x5A, 0x03, 0x6A, 0x06, 0x61, 0x04, 0x10, 0x02, 0x6A, 0x03, 0x10, 0x01, 0x6A, 0x01, 0x10, -0x00, 0x6A, 0x30, 0xF0, 0x20, 0x6B, 0x4F, 0xF4, -0x70, 0xA3, 0x03, 0x73, 0x22, 0x61, 0x03, 0x72, +0x00, 0x6A, 0x30, 0xF0, 0x21, 0x6B, 0x51, 0xF3, +0x74, 0xA3, 0x03, 0x73, 0x22, 0x61, 0x03, 0x72, 0x35, 0x60, 0x02, 0x72, 0x11, 0x61, 0x08, 0x2D, -0x30, 0xF0, 0x20, 0x6A, 0x45, 0xF0, 0x1C, 0x4A, +0x30, 0xF0, 0x20, 0x6A, 0xA5, 0xF5, 0x18, 0x4A, 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0x09, 0x61, -0x30, 0xF0, 0x20, 0x6C, 0x42, 0xF0, 0x08, 0x4C, -0xB0, 0x67, 0x00, 0x18, 0x38, 0x2A, 0x01, 0x10, +0x63, 0xF5, 0x5C, 0x9A, 0x05, 0x5A, 0x09, 0x61, +0x30, 0xF0, 0x20, 0x6C, 0xE2, 0xF3, 0x04, 0x4C, +0xB0, 0x67, 0x00, 0x18, 0x39, 0x3D, 0x01, 0x10, 0x00, 0x68, 0x50, 0x67, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0x00, 0x68, 0xF0, 0x67, 0xD0, 0x67, 0xE0, 0x17, 0x00, 0x65, @@ -7603,694 +10421,1399 @@ u8 array_mp_8822b_fw_ap[] = { 0x65, 0x67, 0x01, 0x74, 0x4C, 0xEB, 0x4C, 0xEE, 0xC0, 0xF0, 0x08, 0x61, 0xC0, 0xF0, 0x06, 0x2E, 0x8C, 0x43, 0x4C, 0xEC, 0x08, 0x5C, 0x1B, 0x60, -0x30, 0xF0, 0x20, 0x6A, 0xE5, 0xF0, 0x10, 0x4A, -0xC2, 0xF7, 0x98, 0x9A, 0x01, 0x6D, 0xAC, 0xEC, -0xA0, 0xF0, 0x18, 0x24, 0xC2, 0xF7, 0x5C, 0x9A, +0x30, 0xF0, 0x20, 0x6A, 0x45, 0xF6, 0x18, 0x4A, +0x63, 0xF5, 0x98, 0x9A, 0x01, 0x6D, 0xAC, 0xEC, +0xA0, 0xF0, 0x18, 0x24, 0x63, 0xF5, 0x5C, 0x9A, 0x05, 0x5A, 0xA0, 0xF0, 0x13, 0x61, 0x30, 0xF0, -0x20, 0x6A, 0x64, 0xF2, 0x14, 0x4A, 0x4D, 0xE3, -0x30, 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array_length_mp_8822b_fw_ap = 104632; #endif /*defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))*/ #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) u8 array_mp_8822b_fw_nic[] = { -0x22, 0x88, 0x00, 0x00, 0x0D, 0x00, 0x01, 0x00, -0x67, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x03, 0x0D, 0x0F, 0x27, 0xE1, 0x07, 0x00, 0x00, -0x08, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, -0x00, 0x00, 0x20, 0x80, 0x70, 0x2D, 0x00, 0x00, +0x22, 0x88, 0x00, 0x00, 0x16, 0x00, 0x06, 0x00, +0x42, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x04, 0x19, 0x0E, 0x26, 0xE2, 0x07, 0x00, 0x00, +0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, +0x00, 0x00, 0x20, 0x80, 0x50, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x48, 0xC4, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, +0x30, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x12, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -10236,11 +13127,11 @@ u8 array_mp_8822b_fw_nic[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x15, 0x36, 0x00, 0x80, 0xE9, 0x06, 0x00, 0x80, +0x01, 0x38, 0x00, 0x80, 0xE9, 0x06, 0x00, 0x80, 0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE, 0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE, 0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE, -0xAD, 0x77, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, +0x19, 0x7C, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -10248,7 +13139,7 @@ u8 array_mp_8822b_fw_nic[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0xB1, 0x79, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, +0x79, 0x7E, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -10256,7 +13147,7 @@ u8 array_mp_8822b_fw_nic[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x70, 0x2D, 0x20, 0x80, 0x81, 0x00, 0x88, 0x00, +0x50, 0x32, 0x20, 0x80, 0x81, 0x00, 0x88, 0x00, 0x90, 0x00, 0x99, 0x00, 0xA2, 0x00, 0xAC, 0x00, 0xB6, 0x00, 0xC0, 0x00, 0xCC, 0x00, 0xD8, 0x00, 0xE5, 0x00, 0xF2, 0x00, 0x01, 0x01, 0x10, 0x01, @@ -10270,127 +13161,130 @@ u8 array_mp_8822b_fw_nic[] = { 0x08, 0x08, 0x0C, 0x09, 0x00, 0x0C, 0xB0, 0x0C, 0xB4, 0x0C, 0xBC, 0x0C, 0x00, 0x0E, 0xB0, 0x0E, 0xB4, 0x0E, 0xBC, 0x0E, 0x90, 0x19, 0xA4, 0x09, -0x04, 0x0A, 0x00, 0x0B, 0xDF, 0x8F, 0x65, 0x00, -0x01, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x04, 0x00, -0x2D, 0x00, 0x2C, 0x01, 0x2D, 0x01, 0x2C, 0x02, -0x2E, 0x01, 0xFF, 0x00, 0x2D, 0x02, 0xFF, 0x00, -0x03, 0x00, 0x00, 0x00, 0x10, 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+0xE3, 0x00, 0x60, 0xB8, 0x00, 0x00, 0x00, 0x01, +0xE1, 0x00, 0x60, 0xB8, 0x00, 0x00, 0x00, 0x60, +0xCC, 0x00, 0x60, 0xB8, 0x02, 0x00, 0x60, 0xB8, +0xE8, 0x12, 0x64, 0xB8, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x04, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xFF, 0x1F, 0x04, 0x00, 0x60, 0xB8, 0x04, 0x00, 0x64, 0xB8, 0x08, 0x00, 0x60, 0xB8, 0x08, 0x00, 0x64, 0xB8, 0x24, 0x00, 0x60, 0xB8, 0x80, 0x00, 0x60, 0xB8, -0xCC, 0x07, 0x64, 0xB8, 0x00, 0x0C, 0x01, 0x00, -0x77, 0x77, 0x77, 0x77, 0x08, 0x00, 0x00, 0xF8, -0x08, 0x70, 0x0A, 0xF8, 0x08, 0x50, 0x01, 0xF8, -0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x3E, +0xFF, 0xFF, 0xFF, 0xEF, 0xCC, 0x07, 0x64, 0xB8, +0x24, 0x04, 0x64, 0xB8, 0x87, 0x02, 0x64, 0xB8, +0x1C, 0x04, 0x64, 0xB8, 0x1C, 0x01, 0x64, 0xB8, +0x00, 0x0C, 0x01, 0x00, 0x10, 0xA9, 0x7B, 0x18, +0x10, 0x91, 0x7B, 0x18, 0x77, 0x77, 0x77, 0x77, +0x08, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0xE0, 0xFF, 0x00, 0x1C, 0x01, 0x88, 0x00, 0x00, 0x00, 0xFF, 0x08, 0x00, 0x45, 0x01, 0x48, 0x08, 0x46, 0x01, 0xFF, 0xFF, 0x0F, 0x00, @@ -10546,13 +13431,15 @@ u8 array_mp_8822b_fw_nic[] = { 0x21, 0x00, 0x00, 0xE0, 0x45, 0x23, 0x01, 0x00, 0x08, 0x08, 0x00, 0xF8, 0x08, 0x07, 0x00, 0xF8, 0x08, 0x02, 0x00, 0xF8, 0x08, 0x03, 0x00, 0xF8, -0x00, 0x00, 0x00, 0x0F, 0x62, 0x06, 0x64, 0xB8, -0xB4, 0x06, 0x64, 0xB8, 0x06, 0x00, 0x00, 0x89, -0x00, 0x00, 0x00, 0x50, 0x40, 0x00, 0x07, 0x70, -0x02, 0x04, 0x00, 0xD8, 0x20, 0x01, 0x00, 0xD1, -0x40, 0x80, 0x03, 0x70, 0x02, 0x04, 0x02, 0xD8, -0x20, 0x01, 0x00, 0xDE, 0xDE, 0xBC, 0x0A, 0x00, -0x01, 0x00, 0x66, 0xB8, 0x00, 0x00, 0x66, 0xB8, +0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x0F, +0x62, 0x06, 0x64, 0xB8, 0xB4, 0x06, 0x64, 0xB8, +0x06, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x50, +0x40, 0x00, 0x07, 0x70, 0x02, 0x04, 0x00, 0xD8, +0x20, 0x01, 0x00, 0xD1, 0x40, 0x80, 0x03, 0x70, +0x02, 0x04, 0x02, 0xD8, 0x20, 0x01, 0x00, 0xDE, +0x08, 0x70, 0x0A, 0xF8, 0x08, 0x50, 0x01, 0xF8, +0xDE, 0xBC, 0x0A, 0x00, 0x01, 0x00, 0x66, 0xB8, +0x20, 0x04, 0x64, 0xB8, 0x00, 0x00, 0x66, 0xB8, 0x00, 0xFF, 0xFF, 0x00, 0xCD, 0x9B, 0x78, 0x56, 0x04, 0x1C, 0x66, 0xB8, 0xFF, 0xFF, 0xFF, 0x3F, 0x1F, 0x00, 0x60, 0xB8, 0x05, 0xEA, 0xEF, 0xFD, @@ -10561,29 +13448,27 @@ u8 array_mp_8822b_fw_nic[] = { 0x07, 0xEA, 0xEF, 0xFD, 0x08, 0xEA, 0xEF, 0xFD, 0x09, 0xEA, 0xEF, 0xFD, 0x0A, 0xEA, 0xEF, 0xFD, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0xF0, 0x3F, 0x00, -0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0xC0, 0xFF, -0x00, 0x00, 0x00, 0xF0, 0x00, 0xFC, 0x0F, 0x00, -0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x01, 0x06, -0x00, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x38, -0xE0, 0x80, 0x03, 0x00, 0x00, 0x00, 0x30, 0xC0, -0x00, 0x03, 0x0C, 0x00, 0x4A, 0x04, 0x64, 0xB8, -0x49, 0x04, 0x64, 0xB8, 0x01, 0x00, 0x60, 0xB8, -0x01, 0x00, 0x64, 0xB8, 0x02, 0x00, 0x64, 0xB8, -0x03, 0x00, 0x60, 0xB8, 0x03, 0x00, 0x64, 0xB8, -0x23, 0x04, 0x64, 0xB8, 0x30, 0x04, 0x64, 0xB8, -0x00, 0x00, 0x00, 0x02, 0x34, 0x04, 0x64, 0xB8, -0x04, 0x05, 0x07, 0x08, 0x00, 0x01, 0x01, 0x02, +0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0xF0, +0x00, 0xFC, 0x0F, 0x00, 0x80, 0x81, 0x81, 0x81, +0x81, 0x81, 0x01, 0x06, 0x00, 0x0E, 0x0E, 0x0E, +0x0E, 0x0E, 0x0E, 0x38, 0xE0, 0x80, 0x03, 0x00, +0x00, 0x00, 0x30, 0xC0, 0x00, 0x03, 0x0C, 0x00, +0x4A, 0x04, 0x64, 0xB8, 0x49, 0x04, 0x64, 0xB8, +0x02, 0x00, 0x64, 0xB8, 0x03, 0x00, 0x60, 0xB8, +0x03, 0x00, 0x64, 0xB8, 0x23, 0x04, 0x64, 0xB8, +0x30, 0x04, 0x64, 0xB8, 0x34, 0x04, 0x64, 0xB8, +0x01, 0x02, 0x02, 0x03, 0x00, 0x01, 0x01, 0x01, 0x81, 0x18, 0x66, 0xB8, 0x53, 0x04, 0x64, 0xB8, 0x80, 0x18, 0x66, 0xB8, 0x82, 0x18, 0x66, 0xB8, 0x83, 0x18, 0x66, 0xB8, 0x84, 0x18, 0x66, 0xB8, 0x85, 0x18, 0x66, 0xB8, 0x2D, 0x04, 0x64, 0xB8, -0xF0, 0x10, 0x60, 0xB8, 0x00, 0x00, 0xF0, 0x00, -0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x0F, 0x00, -0x00, 0x00, 0xC0, 0x00, 0x06, 0x00, 0x66, 0xB8, -0x08, 0x1C, 0x66, 0xB8, 0xFF, 0xFF, 0xCF, 0x3F, -0xFF, 0xFC, 0x3F, 0xFF, 0x50, 0x04, 0x64, 0xB8, +0xCF, 0x04, 0x64, 0xB8, 0xF0, 0x10, 0x60, 0xB8, +0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x0C, +0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x00, +0x06, 0x00, 0x66, 0xB8, 0x50, 0x04, 0x64, 0xB8, 0x51, 0x04, 0x64, 0xB8, 0x52, 0x04, 0x64, 0xB8, -0x20, 0x04, 0x64, 0xB8, 0x01, 0x1C, 0x66, 0xB8, +0x08, 0x1C, 0x66, 0xB8, 0xFF, 0xFF, 0xCF, 0x3F, +0xFF, 0xFC, 0x3F, 0xFF, 0x01, 0x1C, 0x66, 0xB8, 0x02, 0x1C, 0x66, 0xB8, 0x03, 0x1C, 0x66, 0xB8, 0x05, 0x1C, 0x66, 0xB8, 0x06, 0x1C, 0x66, 0xB8, 0x07, 0x1C, 0x66, 0xB8, 0x00, 0x10, 0x66, 0xB8, @@ -10592,145 +13477,156 @@ u8 array_mp_8822b_fw_nic[] = { 0x05, 0x10, 0x66, 0xB8, 0x0C, 0x10, 0x66, 0xB8, 0x02, 0x10, 0x66, 0xB8, 0x01, 0x10, 0x66, 0xB8, 0x0D, 0x10, 0x66, 0xB8, 0x06, 0x10, 0x66, 0xB8, -0x00, 0x00, 0x40, 0x00, 0x74, 0x57, 0x74, 0x00, -0x47, 0x75, 0x47, 0x00, 0x70, 0x45, 0x70, 0x00, -0x17, 0x45, 0x17, 0x00, 0x00, 0x00, 0xF0, 0xFF, -0x70, 0x57, 0x70, 0x00, 0x17, 0x75, 0x17, 0x00, -0x00, 0x00, 0x00, 0x06, 0xFF, 0xFF, 0xFF, 0x0F, -0xFF, 0xFC, 0xFE, 0xFF, 0x92, 0x84, 0x10, 0x08, -0x12, 0x56, 0x09, 0x29, 0x00, 0x01, 0x01, 0x00, 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0xB8, 0x38, 0x06, 0x64, 0xB8, +0xA0, 0x06, 0x64, 0xB8, 0x84, 0x02, 0x64, 0xB8, +0xFF, 0xFF, 0xFB, 0xFF, 0xA0, 0x02, 0x64, 0xB8, 0x57, 0x05, 0x64, 0xB8, 0x04, 0x15, 0x64, 0xB8, 0x10, 0x15, 0x64, 0xB8, 0x08, 0x15, 0x64, 0xB8, 0x0C, 0x15, 0x64, 0xB8, 0xFF, 0xFF, 0xF8, 0xFF, @@ -10747,9 +13643,11 @@ u8 array_mp_8822b_fw_nic[] = { 0xCF, 0x05, 0x64, 0xB8, 0xE0, 0x05, 0x64, 0xB8, 0xE4, 0x05, 0x64, 0xB8, 0xE8, 0x05, 0x64, 0xB8, 0xEC, 0x05, 0x64, 0xB8, 0xF0, 0x05, 0x64, 0xB8, -0xB6, 0x05, 0x64, 0xB8, 0x20, 0x00, 0x78, 0xB8, -0x03, 0x00, 0x78, 0xB8, 0xFF, 0xFF, 0x01, 0xFF, -0x05, 0x00, 0x78, 0xB8, 0x12, 0x05, 0x64, 0xB8, +0xB6, 0x05, 0x64, 0xB8, 0x04, 0x06, 0x64, 0xB8, +0x60, 0x16, 0x64, 0xB8, 0x20, 0x00, 0x78, 0xB8, +0x10, 0x00, 0x78, 0xB8, 0x03, 0x00, 0x78, 0xB8, +0xFF, 0xFF, 0x01, 0xFF, 0x05, 0x00, 0x78, 0xB8, +0x12, 0x05, 0x64, 0xB8, 0x10, 0x05, 0x64, 0xB8, 0x43, 0x6C, 0x65, 0x61, 0x72, 0x50, 0x57, 0x54, 0x00, 0x00, 0x00, 0x00, 0x41, 0x20, 0x4D, 0x69, 0x78, 0x4D, 0x6F, 0x64, 0x65, 0x20, 0x41, 0x47, @@ -10768,16 +13666,14 @@ u8 array_mp_8822b_fw_nic[] = { 0x51, 0x4B, 0x20, 0x72, 0x65, 0x73, 0x75, 0x6C, 0x74, 0x20, 0x62, 0x65, 0x66, 0x6F, 0x72, 0x65, 0x2C, 0x20, 0x30, 0x78, 0x25, 0x62, 0x78, 0x0A, -0x00, 0x00, 0x00, 0x00, 0x4C, 0x4F, 0x4B, 0x20, +0x00, 0x00, 0x00, 0x00, 0x49, 0x51, 0x4B, 0x20, 0x74, 0x69, 0x6D, 0x65, 0x6F, 0x75, 0x74, 0x21, 0x21, 0x21, 0x0A, 0x00, 0x64, 0x65, 0x6C, 0x61, +0x79, 0x20, 0x63, 0x6F, 0x75, 0x6E, 0x74, 0x20, +0x3D, 0x20, 0x30, 0x78, 0x25, 0x78, 0x21, 0x21, +0x21, 0x0A, 0x00, 0x00, 0x64, 0x65, 0x6C, 0x61, 0x79, 0x5F, 0x63, 0x6F, 0x75, 0x6E, 0x74, 0x20, 0x3D, 0x20, 0x30, 0x78, 0x25, 0x78, 0x0A, 0x00, -0x49, 0x51, 0x4B, 0x20, 0x74, 0x69, 0x6D, 0x65, -0x6F, 0x75, 0x74, 0x21, 0x21, 0x21, 0x0A, 0x00, -0x64, 0x65, 0x6C, 0x61, 0x79, 0x20, 0x63, 0x6F, -0x75, 0x6E, 0x74, 0x20, 0x3D, 0x20, 0x30, 0x78, -0x25, 0x78, 0x21, 0x21, 0x21, 0x0A, 0x00, 0x00, 0x49, 0x51, 0x4B, 0x73, 0x74, 0x65, 0x70, 0x20, 0x3D, 0x20, 0x30, 0x78, 0x25, 0x62, 0x78, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x5B, 0x49, 0x51, 0x4B, @@ -10834,65 +13730,154 @@ u8 array_mp_8822b_fw_nic[] = { 0x20, 0x25, 0x64, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x46, 0x57, 0x49, 0x51, 0x4B, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x21, 0x21, 0x21, 0x00, 0x00, -0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, -0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, -0x00, 0x00, 0x00, 0x00, 0x53, 0x65, 0x74, 0x5F, -0x43, 0x61, 0x6E, 0x64, 0x69, 0x5F, 0x33, 0x3A, -0x20, 0x5B, 0x31, 0x5D, 0x3D, 0x30, 0x78, 0x25, -0x62, 0x58, 0x2C, 0x20, 0x20, 0x5B, 0x32, 0x5D, +0x72, 0x73, 0x73, 0x69, 0x56, 0x61, 0x72, 0x3A, +0x25, 0x62, 0x78, 0x2C, 0x25, 0x62, 0x78, 0x00, +0x53, 0x5F, 0x52, 0x41, 0x3D, 0x25, 0x62, 0x78, +0x00, 0x00, 0x00, 0x00, 0x50, 0x57, 0x52, 0x53, +0x54, 0x53, 0x20, 0x25, 0x62, 0x78, 0x2C, 0x72, +0x61, 0x74, 0x65, 0x20, 0x25, 0x62, 0x78, 0x2C, +0x25, 0x62, 0x78, 0x00, 0x52, 0x53, 0x53, 0x49, +0x20, 0x30, 0x78, 0x25, 0x62, 0x78, 0x2C, 0x44, +0x49, 0x53, 0x50, 0x54, 0x20, 0x25, 0x62, 0x78, +0x00, 0x00, 0x00, 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+14091,11 @@ u8 array_mp_8822b_fw_nic[] = { 0x78, 0x20, 0x54, 0x74, 0x25, 0x62, 0x78, 0x20, 0x4D, 0x32, 0x53, 0x25, 0x62, 0x78, 0x00, 0x00, 0x54, 0x52, 0x59, 0x25, 0x62, 0x78, 0x2C, 0x25, -0x62, 0x78, 0x00, 0x00, 0x4D, 0x20, 0x4D, 0x25, +0x62, 0x78, 0x00, 0x00, 0x54, 0x52, 0x5F, 0x53, +0x3A, 0x25, 0x62, 0x78, 0x2C, 0x25, 0x62, 0x78, +0x00, 0x00, 0x00, 0x00, 0x54, 0x52, 0x5F, 0x46, +0x3A, 0x25, 0x62, 0x78, 0x2C, 0x25, 0x62, 0x78, +0x00, 0x00, 0x00, 0x00, 0x4D, 0x20, 0x4D, 0x25, 0x62, 0x78, 0x20, 0x72, 0x74, 0x25, 0x62, 0x78, 0x20, 0x4F, 0x25, 0x62, 0x78, 0x20, 0x54, 0x25, 0x62, 0x78, 0x20, 0x44, 0x25, 0x62, 0x78, 0x00, @@ -11085,207 +14108,198 @@ u8 array_mp_8822b_fw_nic[] = { 0x78, 0x20, 0x44, 0x25, 0x62, 0x78, 0x00, 0x00, 0x52, 0x72, 0x20, 0x25, 0x77, 0x78, 0x20, 0x54, 0x54, 0x20, 0x25, 0x77, 0x78, 0x00, 0x00, 0x00, -0x63, 0x6F, 0x6E, 0x66, 0x69, 0x67, 0x5F, 0x70, -0x68, 0x79, 0x64, 0x6D, 0x5F, 0x70, 0x61, 0x72, -0x61, 0x6D, 0x65, 0x74, 0x65, 0x72, 0x5F, 0x69, -0x6E, 0x69, 0x74, 0x28, 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0x70, 0xE0, +0xB5, 0xA5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -11756,63 +14803,63 @@ u8 array_mp_8822b_fw_nic[] = { 0x00, 0x6E, 0x30, 0xF0, 0x20, 0x6F, 0x00, 0xF0, 0x00, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, 0xE3, 0xEC, 0xB8, 0x67, 0xFB, 0x2D, 0x30, 0xF0, 0x20, 0x6C, -0x65, 0xF5, 0x10, 0x4C, 0x00, 0x6E, 0x30, 0xF0, -0x21, 0x6F, 0x70, 0xF4, 0x00, 0x4F, 0xC0, 0xDC, +0x46, 0xF2, 0x10, 0x4C, 0x00, 0x6E, 0x30, 0xF0, +0x21, 0x6F, 0x72, 0xF2, 0x10, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, 0xE3, 0xEC, 0xB8, 0x67, 0xFB, 0x2D, 0x10, 0xF0, 0x20, 0x6C, 0x60, 0xF2, 0x15, 0x4C, 0x00, 0xEC, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, -0x30, 0xF0, 0x20, 0x6B, 0x60, 0xF7, 0x7C, 0x9B, +0x30, 0xF0, 0x20, 0x6B, 0x60, 0xF7, 0x6C, 0x9B, 0x10, 0xF0, 0x20, 0x6A, 0x60, 0xF2, 0x15, 0x4A, -0x40, 0xDB, 0x00, 0x18, 0x7C, 0x07, 0x00, 0x18, -0x93, 0x07, 0x00, 0x18, 0xFB, 0x09, 0x00, 0x18, -0xAA, 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0x6A, 0x32, 0xF1, +0x04, 0x4A, 0x60, 0xDA, 0x30, 0xF0, 0x21, 0x6A, +0x71, 0xF1, 0x10, 0x4A, 0x60, 0xDA, 0x10, 0xF0, 0x20, 0x6B, 0xE0, 0xF3, 0x09, 0x4B, 0x00, 0xEB, 0x5A, 0xB8, 0x00, 0x65, 0x7B, 0xB8, 0x00, 0x65, 0x40, 0xE8, 0x5A, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x7B, 0xB9, 0x00, 0x65, 0x00, 0x65, -0x00, 0x65, 0x30, 0xF0, 0x20, 0x6A, 0xAF, 0xF3, -0x04, 0x4A, 0x00, 0xF0, 0x20, 0x6B, 0x60, 0xDA, -0x30, 0xF0, 0x20, 0x6A, 0xEF, 0xF3, 0x1C, 0x4A, +0x00, 0x65, 0x30, 0xF0, 0x21, 0x6A, 0x71, 0xF1, +0x10, 0x4A, 0x00, 0xF0, 0x20, 0x6B, 0x60, 0xDA, +0x30, 0xF0, 0x21, 0x6A, 0xD1, 0xF1, 0x08, 0x4A, 0x60, 0x9A, 0x41, 0x9A, 0x6A, 0xEA, 0x0D, 0x61, 0x6E, 0xB8, 0x00, 0x65, 0x62, 0x43, 0xCB, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x5A, 0xB8, @@ -11825,13 +14872,13 @@ u8 array_mp_8822b_fw_nic[] = { 0x84, 0xDB, 0x9B, 0xB8, 0x00, 0x65, 0x85, 0xDB, 0x8E, 0xB8, 0x00, 0x65, 0x82, 0x44, 0x81, 0xDB, 0x8C, 0xB8, 0x00, 0x65, 0x80, 0xDB, 0x30, 0xF0, -0x20, 0x6B, 0xEF, 0xF3, 0x1C, 0x4B, 0x60, 0x9B, +0x21, 0x6B, 0xD1, 0xF1, 0x08, 0x4B, 0x60, 0x9B, 0x9D, 0x67, 0x89, 0xDB, 0x6A, 0x9B, 0xCF, 0xF7, 0x80, 0x44, 0x62, 0xEC, 0x0D, 0x60, 0x77, 0xF0, 0x24, 0x6C, 0xA0, 0xF1, 0x1C, 0x4C, 0x1D, 0xF4, 0x01, 0x6B, 0x60, 0xDC, 0x10, 0xF0, 0x20, 0x6C, -0x06, 0xF6, 0x15, 0x4C, 0x00, 0xEC, 0x00, 0x65, -0x30, 0xF0, 0x20, 0x6B, 0xEF, 0xF3, 0x1C, 0x4B, +0x07, 0xF0, 0x01, 0x4C, 0x00, 0xEC, 0x00, 0x65, +0x30, 0xF0, 0x21, 0x6B, 0xD1, 0xF1, 0x08, 0x4B, 0x41, 0x9B, 0x40, 0xDB, 0x89, 0x9A, 0xBC, 0x65, 0x7D, 0x67, 0xDF, 0xF7, 0x00, 0x03, 0x4C, 0xB8, 0x00, 0x65, 0x00, 0xF0, 0x20, 0x6D, 0x05, 0x4D, @@ -11853,7 +14900,7 @@ u8 array_mp_8822b_fw_nic[] = { 0x9A, 0xB8, 0x00, 0x65, 0x84, 0xDB, 0x9B, 0xB8, 0x00, 0x65, 0x85, 0xDB, 0x7D, 0x67, 0x5B, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x40, 0x9A, -0x30, 0xF0, 0x20, 0x6C, 0x2F, 0xF7, 0x18, 0x4C, +0x30, 0xF0, 0x21, 0x6C, 0x11, 0xF5, 0x04, 0x4C, 0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65, 0x82, 0x67, 0x40, 0xEA, 0x00, 0x65, 0x7A, 0xB8, 0x00, 0x65, 0xBB, 0x65, 0xDF, 0xF7, 0x00, 0x03, 0x82, 0x9B, @@ -11864,8 +14911,8 @@ u8 array_mp_8822b_fw_nic[] = { 0x00, 0x65, 0x2B, 0x9B, 0x0A, 0x9B, 0xE9, 0x9B, 0xC8, 0x9B, 0xA7, 0x9B, 0x86, 0x9B, 0x5A, 0xB8, 0x00, 0x65, 0x7B, 0xB8, 0x00, 0x65, 0x00, 0xBA, -0x00, 0x65, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6B, -0xAF, 0xF3, 0x04, 0x4B, 0x40, 0xDB, 0xDF, 0xF7, +0x00, 0x65, 0x00, 0x65, 0x30, 0xF0, 0x21, 0x6B, +0x71, 0xF1, 0x10, 0x4B, 0x40, 0xDB, 0xDF, 0xF7, 0x00, 0x03, 0x86, 0xDB, 0xA7, 0xDB, 0xC8, 0xDB, 0xE9, 0xDB, 0x0A, 0xDB, 0x2B, 0xDB, 0x98, 0x67, 0x8C, 0xDB, 0x9F, 0x67, 0x8E, 0xDB, 0x12, 0xEC, @@ -11873,18 +14920,18 @@ u8 array_mp_8822b_fw_nic[] = { 0x00, 0x65, 0x84, 0xDB, 0x9B, 0xB8, 0x00, 0x65, 0x85, 0xDB, 0x8E, 0xB8, 0x00, 0x65, 0x81, 0xDB, 0x8C, 0xB8, 0x00, 0x65, 0x80, 0xDB, 0x30, 0xF0, -0x20, 0x6B, 0xEF, 0xF3, 0x1C, 0x4B, 0x60, 0x9B, +0x21, 0x6B, 0xD1, 0xF1, 0x08, 0x4B, 0x60, 0x9B, 0x9D, 0x67, 0x89, 0xDB, 0x6A, 0x9B, 0xCF, 0xF7, 0x80, 0x44, 0x62, 0xEC, 0x0D, 0x60, 0x77, 0xF0, 0x24, 0x6C, 0xA0, 0xF1, 0x1C, 0x4C, 0x1D, 0xF4, 0x01, 0x6B, 0x60, 0xDC, 0x10, 0xF0, 0x20, 0x6C, -0x06, 0xF6, 0x15, 0x4C, 0x00, 0xEC, 0x00, 0x65, -0x40, 0x9A, 0x30, 0xF0, 0x20, 0x6C, 0x2F, 0xF7, -0x18, 0x4C, 0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65, -0x82, 0x67, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6C, -0xAF, 0xF3, 0x04, 0x4C, 0x00, 0xF0, 0x20, 0x6D, -0xA0, 0xDC, 0x30, 0xF0, 0x20, 0x6A, 0xEF, 0xF3, -0x1C, 0x4A, 0x10, 0xF0, 0x20, 0x6B, 0x40, 0xF6, +0x07, 0xF0, 0x01, 0x4C, 0x00, 0xEC, 0x00, 0x65, +0x40, 0x9A, 0x30, 0xF0, 0x21, 0x6C, 0x11, 0xF5, +0x04, 0x4C, 0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65, +0x82, 0x67, 0x40, 0xEA, 0x30, 0xF0, 0x21, 0x6C, +0x71, 0xF1, 0x10, 0x4C, 0x00, 0xF0, 0x20, 0x6D, +0xA0, 0xDC, 0x30, 0xF0, 0x21, 0x6A, 0xD1, 0xF1, +0x08, 0x4A, 0x10, 0xF0, 0x20, 0x6B, 0x40, 0xF6, 0x1D, 0x4B, 0x00, 0xEB, 0x61, 0x9A, 0x60, 0xDA, 0x49, 0x9B, 0xBA, 0x65, 0xDF, 0xF7, 0x00, 0x03, 0x4C, 0xB8, 0x00, 0x65, 0x00, 0xF0, 0x20, 0x6D, @@ -11902,492 +14949,541 @@ u8 array_mp_8822b_fw_nic[] = { 0x5A, 0xB8, 0x00, 0x65, 0x00, 0xBA, 0x00, 0x65, 0x5F, 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0x41, 0xF0, 0x58, 0x9A, 0x04, 0x10, +0x30, 0xF0, 0x20, 0x6A, 0x41, 0xF0, 0x5C, 0x9A, 0x41, 0xE0, 0x20, 0xD8, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x06, 0xD4, 0x06, 0x04, 0x09, 0xD7, 0x07, 0xD5, 0x08, 0xD6, 0x00, 0x18, -0x6D, 0x21, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, +0xBC, 0x27, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0xFF, 0x63, 0x01, 0xD0, 0xFF, 0x6B, 0x3F, 0x68, 0x6C, 0xED, 0xB7, 0xE0, 0x6C, 0xED, 0x00, 0x68, 0x06, 0x92, 0x00, 0xC7, 0x05, 0x67, 0x6C, 0xED, @@ -21537,1117 +25980,1443 @@ u8 array_mp_8822b_fw_nic[] = { 0x60, 0xC2, 0x01, 0x90, 0x01, 0x6A, 0x01, 0x63, 0x20, 0xE8, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0xFF, 0x6A, 0x8C, 0xEA, -0x2D, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0x61, 0xF1, -0x20, 0x9A, 0x01, 0x68, 0x0B, 0xE8, 0xA1, 0xF4, +0x2D, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0x21, 0xF1, +0x3C, 0x9A, 0x01, 0x68, 0x0B, 0xE8, 0xA1, 0xF4, 0x10, 0x6C, 0xB0, 0x67, 0xD1, 0x67, 0x00, 0x18, -0x6B, 0x2C, 0xA1, 0xF4, 0x14, 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0xF2, +0x00, 0x4A, 0x4D, 0xE0, 0xE9, 0xF0, 0x21, 0xC3, +0xC6, 0xF3, 0x98, 0x9A, 0xFF, 0x6B, 0x01, 0x48, +0x6C, 0xE8, 0x07, 0xF7, 0x01, 0x4B, 0x8C, 0xEB, +0x0C, 0x23, 0xC6, 0xF3, 0x5C, 0x9A, 0x05, 0x5A, +0x08, 0x61, 0x30, 0xF0, 0x20, 0x6C, 0x22, 0xF5, +0x08, 0x4C, 0xB0, 0x67, 0xD1, 0x67, 0x00, 0x18, +0x4D, 0x63, 0x07, 0x92, 0x4A, 0xE8, 0x04, 0x60, +0x06, 0x92, 0x1F, 0x4A, 0x2E, 0xEA, 0x23, 0x2A, +0x30, 0xF0, 0x20, 0x6A, 0x86, 0xF2, 0x00, 0x4A, +0xC6, 0xF3, 0x98, 0x9A, 0x08, 0xF0, 0x00, 0x6B, +0x8C, 0xEB, 0x12, 0x23, 0xC6, 0xF3, 0x7C, 0x9A, +0x05, 0x5B, 0x0E, 0x61, 0xE9, 0xF0, 0xC1, 0xA2, +0xE9, 0xF0, 0xE2, 0xA2, 0xE9, 0xF0, 0x43, 0xA2, +0x30, 0xF0, 0x20, 0x6C, 0x42, 0xF5, 0x08, 0x4C, +0xB0, 0x67, 0x04, 0xD2, 0x00, 0x18, 0x4D, 0x63, +0x0D, 0x20, 0x07, 0x94, 0x00, 0x68, 0x00, 0x18, +0x8C, 0x63, 0x00, 0x18, 0x3D, 0x62, 0x01, 0x49, +0xFF, 0x6A, 0x4C, 0xE9, 0x06, 0x92, 0x20, 0x4A, +0x42, 0xE9, 0xAE, 0x61, 0x0D, 0x97, 0x0C, 0x91, +0x0B, 0x90, 0x07, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xF6, 0x63, 0x13, 0x62, 0x12, 0xD1, 0x11, 0xD0, 0x30, 0xF0, 0x20, 0x6B, 0xFF, 0x6A, 0x8C, 0xEA, -0xE0, 0xF3, 0x8C, 0x9B, 0xE0, 0xF3, 0x0C, 0x4B, +0xC0, 0xF3, 0x98, 0x9B, 0xC0, 0xF3, 0x18, 0x4B, 0x01, 0x72, 0x04, 0xD4, 0x81, 0x9B, 0x68, 0xA3, 0x05, 0xD4, 0x9D, 0x67, 0x78, 0xC4, 0x30, 0xF0, -0x20, 0x6B, 0xE0, 0xF3, 0x80, 0x9B, 0xE0, 0xF3, -0x00, 0x4B, 0x07, 0xD4, 0x81, 0x9B, 0x68, 0xA3, +0x20, 0x6B, 0xC0, 0xF3, 0x8C, 0x9B, 0xC0, 0xF3, +0x0C, 0x4B, 0x07, 0xD4, 0x81, 0x9B, 0x68, 0xA3, 0x08, 0xD4, 0x9D, 0x67, 0x20, 0xF0, 0x64, 0xC4, 0x20, 0x61, 0x00, 0x68, 0x5D, 0x67, 0x0D, 0xE2, 0x5C, 0xA3, 0x0B, 0x5A, 0x01, 0x61, 0x0A, 0x6A, @@ -22717,7 +27575,7 @@ u8 array_mp_8822b_fw_nic[] = { 0x01, 0x6A, 0x20, 0xF0, 0x4A, 0xC3, 0x09, 0xE3, 0x50, 0xA2, 0x0B, 0x95, 0x0C, 0x96, 0x20, 0xF0, 0x4B, 0xC3, 0x0A, 0x94, 0x0D, 0x97, 0x01, 0x48, -0x00, 0x18, 0xD8, 0x4C, 0x09, 0x70, 0xE2, 0x61, +0x00, 0x18, 0xC0, 0x57, 0x09, 0x70, 0xE2, 0x61, 0x71, 0x10, 0x08, 0x72, 0x37, 0x61, 0x20, 0xF0, 0x05, 0x04, 0x07, 0x00, 0x04, 0x01, 0x0E, 0xD4, 0x40, 0xA0, 0x0B, 0x5A, 0x01, 0x61, 0x0A, 0x6A, @@ -22726,12 +27584,12 @@ u8 array_mp_8822b_fw_nic[] = { 0x08, 0x6A, 0x20, 0xF0, 0x4A, 0xC4, 0x40, 0xA1, 0x20, 0xF0, 0x4B, 0xC4, 0x00, 0x6A, 0x0E, 0x10, 0x9D, 0x67, 0x55, 0xE4, 0xC0, 0xA1, 0x30, 0xF0, -0x20, 0x6C, 0x85, 0xF5, 0x18, 0x4C, 0x91, 0xE2, -0xD1, 0xE4, 0x67, 0xF7, 0x86, 0xA4, 0x01, 0x4A, +0x20, 0x6C, 0x86, 0xF2, 0x00, 0x4C, 0x91, 0xE2, +0xD1, 0xE4, 0xC8, 0xF6, 0x96, 0xA4, 0x01, 0x4A, 0x20, 0xF0, 0x8C, 0xC5, 0xFF, 0x6C, 0x4C, 0xEC, 0x63, 0xEC, 0xEE, 0x61, 0x0A, 0x94, 0x0B, 0x95, 0x0C, 0x96, 0x0D, 0x97, 0x01, 0x48, 0x01, 0x49, -0x00, 0x18, 0xD8, 0x4C, 0x0E, 0x92, 0x4A, 0xE8, +0x00, 0x18, 0xC0, 0x57, 0x0E, 0x92, 0x4A, 0xE8, 0xCF, 0x61, 0x38, 0x10, 0x09, 0x72, 0x36, 0x61, 0x20, 0xF0, 0x05, 0x03, 0x07, 0x00, 0x04, 0x01, 0x0F, 0xD3, 0x40, 0xA0, 0x0B, 0x5A, 0x01, 0x61, @@ -22740,43 +27598,43 @@ u8 array_mp_8822b_fw_nic[] = { 0x48, 0xC4, 0x09, 0x6A, 0x20, 0xF0, 0x4A, 0xC4, 0x40, 0xA1, 0x20, 0xF0, 0x4B, 0xC4, 0x00, 0x6A, 0x0E, 0x10, 0x9D, 0x67, 0x55, 0xE4, 0xC0, 0xA1, -0x30, 0xF0, 0x20, 0x6C, 0x85, 0xF5, 0x18, 0x4C, -0x91, 0xE2, 0xD1, 0xE4, 0xA7, 0xF7, 0x9A, 0xA4, +0x30, 0xF0, 0x20, 0x6C, 0x86, 0xF2, 0x00, 0x4C, +0x91, 0xE2, 0xD1, 0xE4, 0x28, 0xF7, 0x8A, 0xA4, 0x01, 0x4A, 0x20, 0xF0, 0x8C, 0xC5, 0xFF, 0x6C, 0x4C, 0xEC, 0x63, 0xEC, 0xEE, 0x61, 0x0A, 0x94, 0x0B, 0x95, 0x0C, 0x96, 0x0D, 0x97, 0x01, 0x48, -0x01, 0x49, 0x00, 0x18, 0xD8, 0x4C, 0x0F, 0x92, +0x01, 0x49, 0x00, 0x18, 0xC0, 0x57, 0x0F, 0x92, 0x4A, 0xE8, 0xCF, 0x61, 0x13, 0x97, 0x12, 0x91, 0x11, 0x90, 0x0A, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0x44, 0x67, 0x65, 0xA2, 0x02, 0x6D, 0x81, 0xA4, -0xAC, 0xEB, 0x03, 0x23, 0x00, 0x18, 0x18, 0x56, +0xAC, 0xEB, 0x03, 0x23, 0x00, 0x18, 0x3E, 0x64, 0x3D, 0x10, 0x01, 0x74, 0x22, 0xA2, 0x04, 0xA2, 0x43, 0xA2, 0x07, 0x61, 0x30, 0xF0, 0x20, 0x6C, -0x62, 0xF3, 0x0C, 0x4C, 0x00, 0x18, 0x97, 0x55, +0x62, 0xF5, 0x10, 0x4C, 0x00, 0x18, 0x0B, 0x63, 0x31, 0x10, 0x10, 0x30, 0x08, 0x74, 0x4D, 0xE8, -0x0E, 0x61, 0x30, 0xF0, 0x20, 0x6C, 0x62, 0xF3, -0x18, 0x4C, 0x00, 0x18, 0x97, 0x55, 0x30, 0xF0, -0x20, 0x6A, 0x85, 0xF5, 0x18, 0x4A, 0x45, 0xE1, -0x67, 0xF7, 0x06, 0xC1, 0x1F, 0x10, 0x09, 0x74, -0x0E, 0x61, 0x30, 0xF0, 0x20, 0x6C, 0x82, 0xF3, -0x18, 0x4C, 0x00, 0x18, 0x97, 0x55, 0x30, 0xF0, -0x20, 0x6A, 0x85, 0xF5, 0x18, 0x4A, 0x45, 0xE1, -0xA7, 0xF7, 0x1A, 0xC1, 0x0F, 0x10, 0x0A, 0x74, -0x0D, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x21, 0xF2, -0xF4, 0x9A, 0x30, 0xF0, 0x20, 0x6C, 0xA2, 0xF3, -0x08, 0x4C, 0xF9, 0x6D, 0x28, 0xF3, 0x01, 0x6E, -0x00, 0x18, 0xD9, 0x55, 0x07, 0x97, 0x06, 0x91, +0x0E, 0x61, 0x30, 0xF0, 0x20, 0x6C, 0x62, 0xF5, +0x1C, 0x4C, 0x00, 0x18, 0x0B, 0x63, 0x30, 0xF0, +0x20, 0x6A, 0x86, 0xF2, 0x00, 0x4A, 0x45, 0xE1, +0xC8, 0xF6, 0x16, 0xC1, 0x1F, 0x10, 0x09, 0x74, +0x0E, 0x61, 0x30, 0xF0, 0x20, 0x6C, 0x82, 0xF5, +0x1C, 0x4C, 0x00, 0x18, 0x0B, 0x63, 0x30, 0xF0, +0x20, 0x6A, 0x86, 0xF2, 0x00, 0x4A, 0x45, 0xE1, +0x28, 0xF7, 0x0A, 0xC1, 0x0F, 0x10, 0x0A, 0x74, +0x0D, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x01, 0xF2, +0xF4, 0x9A, 0x30, 0xF0, 0x20, 0x6C, 0xA2, 0xF5, +0x0C, 0x4C, 0xF9, 0x6D, 0x28, 0xF3, 0x01, 0x6E, +0x00, 0x18, 0x4D, 0x63, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFB, 0x63, 0x09, 0x62, 0xFF, 0x6A, 0x4C, 0xEC, -0x2A, 0x6B, 0x78, 0xEC, 0x30, 0xF0, 0x20, 0x6E, -0xAB, 0xF5, 0x1C, 0x4E, 0xAC, 0xEA, 0x05, 0x6D, +0x2E, 0x6B, 0x78, 0xEC, 0x30, 0xF0, 0x20, 0x6E, +0xAD, 0xF0, 0x00, 0x4E, 0xAC, 0xEA, 0x05, 0x6D, 0x12, 0xEB, 0x6D, 0xE6, 0xDD, 0x67, 0xAF, 0xCE, 0x0F, 0x6D, 0xB0, 0xC6, 0x92, 0xC6, 0x53, 0xC6, 0x20, 0xF0, 0x44, 0xA3, 0x07, 0x97, 0x04, 0x94, 0x54, 0xC6, 0x20, 0xF0, 0x45, 0xA3, 0x55, 0xC6, 0x20, 0xF0, 0x46, 0xA3, 0x56, 0xC6, 0x05, 0x95, -0x06, 0x96, 0x00, 0x18, 0xD8, 0x4C, 0x09, 0x97, +0x06, 0x96, 0x00, 0x18, 0xC0, 0x57, 0x09, 0x97, 0x05, 0x63, 0x00, 0xEF, 0xF8, 0x63, 0x0F, 0x62, 0x0E, 0xD1, 0x0D, 0xD0, 0x14, 0x92, 0x15, 0x93, 0x16, 0x90, 0x0A, 0xD2, 0xFF, 0x6A, 0x1A, 0x65, @@ -22784,11 +27642,11 @@ u8 array_mp_8822b_fw_nic[] = { 0x17, 0x91, 0x1A, 0x65, 0x0A, 0x92, 0xFF, 0xF7, 0x1F, 0x6D, 0xAC, 0xEF, 0xAC, 0xEA, 0xAC, 0xEB, 0xAC, 0xE8, 0xAC, 0xE9, 0x30, 0xF0, 0x20, 0x6D, -0x85, 0xF5, 0x18, 0x4D, 0xE5, 0xF5, 0xD0, 0x9D, -0x0A, 0xD2, 0x8C, 0xEE, 0x36, 0x26, 0xE5, 0xF5, -0x94, 0x9D, 0x05, 0x6A, 0x4E, 0xEC, 0x31, 0x2C, -0x30, 0xF0, 0x20, 0x6C, 0x21, 0xF2, 0x90, 0x9C, -0xC8, 0xF1, 0xA0, 0x9D, 0x7F, 0x4A, 0x7C, 0x4A, +0x86, 0xF2, 0x00, 0x4D, 0xC6, 0xF3, 0xD8, 0x9D, +0x0A, 0xD2, 0x8C, 0xEE, 0x36, 0x26, 0xC6, 0xF3, +0x9C, 0x9D, 0x05, 0x6A, 0x4E, 0xEC, 0x31, 0x2C, +0x30, 0xF0, 0x20, 0x6C, 0x01, 0xF2, 0x90, 0x9C, +0xE9, 0xF0, 0xA4, 0x9D, 0x7F, 0x4A, 0x7C, 0x4A, 0xAC, 0xEC, 0x4E, 0xEC, 0x26, 0x2C, 0x9D, 0x67, 0x47, 0x44, 0x19, 0x4A, 0x40, 0xA2, 0xF4, 0xC4, 0xE2, 0x37, 0x52, 0xC4, 0x58, 0x67, 0x53, 0xC4, @@ -22799,155 +27657,272 @@ u8 array_mp_8822b_fw_nic[] = { 0x02, 0x30, 0x22, 0x31, 0x0C, 0x6A, 0x79, 0xC4, 0x1B, 0xC4, 0x3D, 0xC4, 0x4F, 0xCC, 0x05, 0x95, 0x04, 0x94, 0x06, 0x96, 0x07, 0x97, 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0x14, 0x61, 0x40, 0xF2, 0xB2, 0xA8, +0x64, 0x6A, 0x90, 0x67, 0x58, 0xED, 0x8F, 0xF7, +0x1C, 0x4A, 0x12, 0xED, 0x55, 0xE5, 0x40, 0xF2, +0x50, 0xA0, 0xA2, 0x35, 0xA2, 0x35, 0x01, 0x4A, +0x40, 0xF2, 0x50, 0xC0, 0x40, 0xF2, 0xD0, 0xA0, +0x00, 0x18, 0xDF, 0x66, 0x40, 0xF2, 0x50, 0xA0, +0x01, 0x72, 0x03, 0x61, 0x90, 0x67, 0x00, 0x18, +0xCB, 0x66, 0x90, 0x67, 0x00, 0x18, 0xD5, 0x66, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63, 0x00, 0xEF, 0xFF, 0x6B, 0x8C, 0xEB, 0x20, 0x5B, 0x00, 0x6A, 0x02, 0x60, 0x01, 0x6A, 0x44, 0xEB, 0x20, 0xE8, @@ -22958,106 +27933,106 @@ u8 array_mp_8822b_fw_nic[] = { 0x00, 0x6A, 0x02, 0x60, 0x01, 0x6A, 0x44, 0xEC, 0x20, 0xE8, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0xFF, 0x68, 0x0C, 0xEC, 0x00, 0x18, -0x06, 0x58, 0x0F, 0x6B, 0x4C, 0xEB, 0x43, 0x67, +0x16, 0x67, 0x0F, 0x6B, 0x4C, 0xEB, 0x43, 0x67, 0x0C, 0xEA, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0xFF, 0x68, 0x0C, 0xEC, 0x00, 0x18, -0x06, 0x58, 0x10, 0x6B, 0x6B, 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0x08, 0x60, 0xDD, 0x67, 0xB0, 0xC6, 0x72, 0xA0, 0x19, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, @@ -24448,12 +29274,12 @@ u8 array_mp_8822b_fw_nic[] = { 0x15, 0x4C, 0x80, 0xA4, 0x90, 0xC3, 0x0A, 0x95, 0xFF, 0x6A, 0x06, 0x91, 0x01, 0x4D, 0x4C, 0xED, 0x0A, 0xD5, 0x0A, 0x96, 0x09, 0x92, 0x43, 0xEE, -0x90, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x85, 0xF5, -0x18, 0x4A, 0xE5, 0xF5, 0x70, 0x9A, 0x01, 0x6C, -0x8C, 0xEB, 0x0F, 0x23, 0xE5, 0xF5, 0x54, 0x9A, +0x90, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x86, 0xF2, +0x00, 0x4A, 0xC6, 0xF3, 0x78, 0x9A, 0x01, 0x6C, +0x8C, 0xEB, 0x0F, 0x23, 0xC6, 0xF3, 0x5C, 0x9A, 0x05, 0x5A, 0x0B, 0x61, 0x7D, 0x67, 0xB0, 0xA3, -0x30, 0xF0, 0x20, 0x6C, 0xC2, 0xF7, 0x18, 0x4C, -0x00, 0x18, 0xD9, 0x55, 0x01, 0x6C, 0x06, 0xD4, +0x30, 0xF0, 0x20, 0x6C, 0x63, 0xF2, 0x08, 0x4C, +0x00, 0x18, 0x4D, 0x63, 0x01, 0x6C, 0x06, 0xD4, 0x02, 0x10, 0x01, 0x6D, 0x06, 0xD5, 0x0D, 0x96, 0x01, 0x76, 0x04, 0x60, 0x72, 0xA0, 0x18, 0x6A, 0x6C, 0xEA, 0x07, 0x2A, 0x72, 0xA0, 0x19, 0x6A, @@ -24462,372 +29288,410 @@ u8 array_mp_8822b_fw_nic[] = { 0x02, 0x6D, 0x48, 0xC0, 0x71, 0xA3, 0x03, 0x6A, 0x00, 0x6E, 0x6C, 0xEA, 0x48, 0x33, 0x0D, 0x6A, 0x4B, 0xEA, 0x8C, 0xEA, 0x6D, 0xEA, 0x51, 0xC0, -0x08, 0x94, 0x00, 0x18, 0x9C, 0x58, 0x6F, 0xA0, +0x08, 0x94, 0x00, 0x18, 0xAC, 0x67, 0x6F, 0xA0, 0x0F, 0x6A, 0xDD, 0x67, 0x6C, 0xEA, 0x20, 0x6B, 0x6D, 0xEA, 0x4F, 0xC0, 0x5D, 0x67, 0xB0, 0xA6, 0xF1, 0xA2, 0x08, 0x94, 0x06, 0x96, 0x00, 0x18, -0x72, 0x60, 0x11, 0x97, 0x10, 0x91, 0x0F, 0x90, -0x09, 0x63, 0x00, 0xEF, 0xF0, 0x63, 0x1F, 0x62, -0x1E, 0xD1, 0x1D, 0xD0, 0x00, 0x18, 0xF4, 0x5B, -0x30, 0xF0, 0x20, 0x6A, 0x6D, 0xF7, 0x00, 0x4A, -0x30, 0xF0, 0x20, 0x6B, 0x30, 0xF0, 0x20, 0x6C, -0x30, 0xF0, 0x20, 0x6D, 0x00, 0x6E, 0x17, 0xD2, -0x4E, 0xF0, 0x1C, 0x4B, 0xCB, 0xF5, 0x05, 0x4C, -0xCB, 0xF5, 0x15, 0x4D, 0x01, 0x6A, 0x16, 0xD3, -0x13, 0xD4, 0x10, 0xD5, 0x11, 0xD6, 0x19, 0xD6, -0x1A, 0xD2, 0x17, 0x93, 0x11, 0x94, 0x10, 0x91, -0x00, 0x9B, 0x00, 0x18, 0x31, 0x4C, 0x10, 0x94, -0x0E, 0xD2, 0xE7, 0x49, 0xFF, 0xF7, 0x87, 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0xA3, 0x01, 0x4A, 0xFF, 0xF7, 0x50, 0xC3, +0x17, 0x10, 0x44, 0x99, 0x01, 0x6B, 0x6C, 0xEA, +0x09, 0x22, 0x45, 0x99, 0x05, 0x5A, 0x06, 0x61, +0x30, 0xF0, 0x20, 0x6C, 0x83, 0xF4, 0x04, 0x4C, +0x00, 0x18, 0x4D, 0x63, 0x13, 0x94, 0x04, 0x6D, +0x00, 0x6E, 0x00, 0x18, 0xAC, 0x67, 0x11, 0x94, +0x0F, 0x6A, 0x6F, 0xA4, 0x6C, 0xEA, 0x4F, 0xC4, +0x00, 0x18, 0xE8, 0x67, 0x44, 0x99, 0x01, 0x6B, +0x6C, 0xEA, 0x09, 0x22, 0x45, 0x99, 0x05, 0x5A, +0x06, 0x61, 0x30, 0xF0, 0x20, 0x6C, 0x83, 0xF4, +0x08, 0x4C, 0x00, 0x18, 0x4D, 0x63, 0x13, 0x94, +0x00, 0x18, 0xBE, 0x77, 0x13, 0x95, 0x18, 0x96, +0x17, 0x97, 0x0F, 0x92, 0x01, 0x4D, 0x04, 0x4E, +0x14, 0x4F, 0x2E, 0x4A, 0x3F, 0x75, 0x13, 0xD5, +0x18, 0xD6, 0x17, 0xD7, 0x0F, 0xD2, 0x3F, 0xF2, +0x1E, 0x61, 0x21, 0x97, 0x20, 0x91, 0x1F, 0x90, +0x11, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, +0x04, 0xD0, 0x30, 0xF0, 0x20, 0x6A, 0x66, 0xF2, +0x6D, 0xA2, 0x01, 0x4B, 0x66, 0xF2, 0x6D, 0xC2, +0x66, 0xF2, 0x6D, 0xA2, 0x02, 0x5B, 0x03, 0x61, +0x00, 0x6B, 0x66, 0xF2, 0x6D, 0xC2, 0x30, 0xF0, +0x20, 0x68, 0x4C, 0xF6, 0x08, 0x48, 0x90, 0x67, +0x00, 0x18, 0xC9, 0x71, 0x00, 0x18, 0x5E, 0x60, +0x90, 0x67, 0x00, 0x18, 0xF3, 0x66, 0x05, 0x97, +0x04, 0x90, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0, -0xFF, 0x69, 0x2C, 0xEC, 0x2A, 0x6A, 0x58, 0xEC, -0x30, 0xF0, 0x20, 0x6B, 0xAB, 0xF5, 0x1C, 0x4B, +0xFF, 0x69, 0x2C, 0xEC, 0x2E, 0x6A, 0x58, 0xEC, +0x30, 0xF0, 0x20, 0x6B, 0xAD, 0xF0, 0x00, 0x4B, 0x04, 0xD4, 0x03, 0x6D, 0x12, 0xEA, 0x49, 0xE3, 0xD2, 0xA2, 0xF1, 0xA2, 0x68, 0xA2, 0xCC, 0xED, 0xA8, 0x36, 0xAC, 0xE9, 0x0D, 0x6D, 0xAB, 0xED, @@ -24836,36 +29700,36 @@ u8 array_mp_8822b_fw_nic[] = { 0x64, 0x67, 0x48, 0xA2, 0x80, 0x68, 0x0B, 0xE8, 0x4C, 0xE8, 0x6D, 0xE8, 0x00, 0xF6, 0x00, 0x30, 0xFF, 0x6A, 0x00, 0xF6, 0x03, 0x30, 0x4C, 0xE8, -0x30, 0xF0, 0x20, 0x6A, 0x85, 0xF5, 0x18, 0x4A, -0xE5, 0xF5, 0x70, 0x9A, 0x01, 0x6C, 0x8C, 0xEB, -0x0C, 0x23, 0xE5, 0xF5, 0x54, 0x9A, 0x05, 0x5A, -0x08, 0x61, 0x30, 0xF0, 0x20, 0x6C, 0x03, 0xF1, -0x08, 0x4C, 0xB0, 0x67, 0xD1, 0x67, 0x00, 0x18, -0xD9, 0x55, 0x04, 0x94, 0xB0, 0x67, 0xF1, 0x67, -0x00, 0x6E, 0x00, 0x18, 0x72, 0x60, 0x09, 0x97, +0x30, 0xF0, 0x20, 0x6A, 0x86, 0xF2, 0x00, 0x4A, +0xC6, 0xF3, 0x78, 0x9A, 0x01, 0x6C, 0x8C, 0xEB, +0x0C, 0x23, 0xC6, 0xF3, 0x5C, 0x9A, 0x05, 0x5A, +0x08, 0x61, 0x30, 0xF0, 0x20, 0x6C, 0x83, 0xF4, +0x14, 0x4C, 0xB0, 0x67, 0xD1, 0x67, 0x00, 0x18, +0x4D, 0x63, 0x04, 0x94, 0xB0, 0x67, 0xF1, 0x67, +0x00, 0x6E, 0x00, 0x18, 0x9B, 0x6F, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0xFA, 0x63, 0x0B, 0x62, 0x0A, 0xD1, 0x09, 0xD0, -0xFF, 0x69, 0x8C, 0xE9, 0x2A, 0x68, 0x18, 0xE9, +0xFF, 0x69, 0x8C, 0xE9, 0x2E, 0x68, 0x18, 0xE9, 0xFF, 0x6A, 0xAC, 0xEA, 0x06, 0xD2, 0x30, 0xF0, -0x20, 0x6A, 0xAB, 0xF5, 0x1C, 0x4A, 0x91, 0x67, -0x12, 0xE8, 0x01, 0xE2, 0x00, 0x18, 0x31, 0x4C, -0x04, 0xD2, 0x30, 0xF0, 0x20, 0x6A, 0x21, 0xF2, -0x48, 0x9A, 0x34, 0x33, 0x91, 0x67, 0x49, 0xE3, +0x20, 0x6A, 0xAD, 0xF0, 0x00, 0x4A, 0x91, 0x67, +0x12, 0xE8, 0x01, 0xE2, 0x00, 0x18, 0x14, 0x57, +0x04, 0xD2, 0x30, 0xF0, 0x20, 0x6A, 0x01, 0xF2, +0x44, 0x9A, 0x34, 0x33, 0x91, 0x67, 0x49, 0xE3, 0x40, 0xA2, 0xFF, 0x6B, 0x4C, 0xEB, 0x05, 0xD3, -0x00, 0x18, 0x7B, 0x12, 0x52, 0xA0, 0x01, 0x6B, +0x00, 0x18, 0xAA, 0x13, 0x52, 0xA0, 0x01, 0x6B, 0xFF, 0x6C, 0x5A, 0x32, 0x6C, 0xEA, 0x8C, 0xEA, 0x00, 0xF1, 0x06, 0x22, 0x06, 0x92, 0x63, 0x22, 0x8F, 0xA0, 0x10, 0x6A, 0x4B, 0xEA, 0x8C, 0xEA, -0x4F, 0xC0, 0x30, 0xF0, 0x20, 0x6A, 0x85, 0xF5, -0x18, 0x4A, 0xE5, 0xF5, 0x90, 0x9A, 0x6C, 0xEC, -0x0B, 0x24, 0xE5, 0xF5, 0x54, 0x9A, 0x05, 0x5A, +0x4F, 0xC0, 0x30, 0xF0, 0x20, 0x6A, 0x86, 0xF2, +0x00, 0x4A, 0xC6, 0xF3, 0x98, 0x9A, 0x6C, 0xEC, +0x0B, 0x24, 0xC6, 0xF3, 0x5C, 0x9A, 0x05, 0x5A, 0x07, 0x61, 0x04, 0x95, 0x30, 0xF0, 0x20, 0x6C, -0x03, 0xF1, 0x18, 0x4C, 0x00, 0x18, 0xD9, 0x55, +0xA3, 0xF4, 0x04, 0x4C, 0x00, 0x18, 0x4D, 0x63, 0x91, 0x67, 0x06, 0x6D, 0x00, 0x6E, 0x00, 0x18, -0x9C, 0x58, 0x54, 0xA0, 0x10, 0x6B, 0x6B, 0xEB, +0xAC, 0x67, 0x54, 0xA0, 0x10, 0x6B, 0x6B, 0xEB, 0x6C, 0xEA, 0x54, 0xC0, 0x05, 0x94, 0x18, 0x6F, 0x04, 0x95, 0x8C, 0xEF, 0x00, 0x6E, 0x91, 0x67, -0xEE, 0x37, 0x00, 0x18, 0x72, 0x60, 0x72, 0xA0, +0xEE, 0x37, 0x00, 0x18, 0x9B, 0x6F, 0x72, 0xA0, 0x19, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0x52, 0xC0, 0x4F, 0xA0, 0x10, 0x6B, 0x6B, 0xEB, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x10, 0x6C, 0x8E, 0xEA, @@ -24876,17 +29740,17 @@ u8 array_mp_8822b_fw_nic[] = { 0x08, 0x6B, 0x4C, 0xEB, 0x4E, 0xC0, 0xA0, 0xF0, 0x0B, 0x23, 0x6F, 0xA0, 0x10, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x10, 0x72, -0x05, 0x61, 0x30, 0xF0, 0x20, 0x6C, 0x23, 0xF1, -0x04, 0x4C, 0x04, 0x10, 0x30, 0xF0, 0x20, 0x6C, -0x23, 0xF1, 0x14, 0x4C, 0x04, 0x96, 0xB1, 0x67, -0x00, 0x18, 0xD9, 0x55, 0x95, 0x10, 0x6E, 0xA0, +0x05, 0x61, 0x30, 0xF0, 0x20, 0x6C, 0xA3, 0xF4, +0x10, 0x4C, 0x04, 0x10, 0x30, 0xF0, 0x20, 0x6C, +0xC3, 0xF4, 0x00, 0x4C, 0x04, 0x96, 0xB1, 0x67, +0x00, 0x18, 0x4D, 0x63, 0x95, 0x10, 0x6E, 0xA0, 0x08, 0x6A, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x15, 0x22, 0x6F, 0xA0, 0x10, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0xFF, 0x6C, 0x8C, 0xEA, 0x10, 0x72, -0x05, 0x61, 0x30, 0xF0, 0x20, 0x6C, 0x43, 0xF1, -0x04, 0x4C, 0x04, 0x10, 0x30, 0xF0, 0x20, 0x6C, -0x43, 0xF1, 0x14, 0x4C, 0x04, 0x96, 0xB1, 0x67, -0x00, 0x18, 0xD9, 0x55, 0x72, 0xA0, 0x18, 0x6A, +0x05, 0x61, 0x30, 0xF0, 0x20, 0x6C, 0xC3, 0xF4, +0x10, 0x4C, 0x04, 0x10, 0x30, 0xF0, 0x20, 0x6C, +0xE3, 0xF4, 0x00, 0x4C, 0x04, 0x96, 0xB1, 0x67, +0x00, 0x18, 0x4D, 0x63, 0x72, 0xA0, 0x18, 0x6A, 0x6C, 0xEA, 0x4C, 0x2A, 0x4F, 0xA0, 0x10, 0x6B, 0x6B, 0xEB, 0x6C, 0xEA, 0xFF, 0x6C, 0x8C, 0xEA, 0x10, 0x72, 0x3F, 0x61, 0x54, 0xA0, 0x0F, 0x6C, @@ -24894,28 +29758,28 @@ u8 array_mp_8822b_fw_nic[] = { 0x6C, 0xEA, 0xAD, 0xEA, 0x4C, 0xEC, 0x03, 0x54, 0x54, 0xC0, 0x0E, 0x61, 0x6C, 0xEA, 0x54, 0xC0, 0x04, 0x94, 0x30, 0xF0, 0x20, 0x6A, 0x7F, 0x6B, -0x8C, 0xEB, 0x05, 0xF1, 0x08, 0x4A, 0x49, 0xE3, +0x8C, 0xEB, 0xE5, 0xF5, 0x0C, 0x4A, 0x49, 0xE3, 0x40, 0xA2, 0x44, 0x32, 0x0A, 0x4A, 0x55, 0xC0, 0x6E, 0xA0, 0x08, 0x6A, 0x6C, 0xEA, 0x0C, 0x22, 0x74, 0xA0, 0x0F, 0x6A, 0xD5, 0xA0, 0x6C, 0xEA, -0x30, 0xF0, 0x20, 0x6C, 0xFF, 0x6D, 0x63, 0xF1, -0x04, 0x4C, 0x4C, 0xED, 0x00, 0x18, 0xD9, 0x55, -0x30, 0xF0, 0x20, 0x6A, 0x85, 0xF5, 0x18, 0x4A, -0xE5, 0xF5, 0x70, 0x9A, 0x01, 0x6C, 0x8C, 0xEB, -0x11, 0x23, 0xE5, 0xF5, 0x54, 0x9A, 0x05, 0x5A, +0x30, 0xF0, 0x20, 0x6C, 0xFF, 0x6D, 0xE3, 0xF4, +0x10, 0x4C, 0x4C, 0xED, 0x00, 0x18, 0x4D, 0x63, +0x30, 0xF0, 0x20, 0x6A, 0x86, 0xF2, 0x00, 0x4A, +0xC6, 0xF3, 0x78, 0x9A, 0x01, 0x6C, 0x8C, 0xEB, +0x11, 0x23, 0xC6, 0xF3, 0x5C, 0x9A, 0x05, 0x5A, 0x0D, 0x61, 0xB5, 0xA0, 0x30, 0xF0, 0x20, 0x6C, -0x63, 0xF1, 0x14, 0x4C, 0x00, 0x18, 0xD9, 0x55, +0x03, 0xF5, 0x00, 0x4C, 0x00, 0x18, 0x4D, 0x63, 0x05, 0x10, 0x54, 0xA0, 0x4C, 0xEB, 0x03, 0x6A, 0x74, 0xC0, 0x55, 0xC0, 0x30, 0xF0, 0x20, 0x6A, -0x85, 0xF5, 0x18, 0x4A, 0xE5, 0xF5, 0x70, 0x9A, -0x01, 0x6C, 0x8C, 0xEB, 0x0D, 0x23, 0xE5, 0xF5, -0x54, 0x9A, 0x05, 0x5A, 0x09, 0x61, 0x54, 0xA0, -0x30, 0xF0, 0x20, 0x6C, 0x0F, 0x6D, 0x83, 0xF1, -0x00, 0x4C, 0x4C, 0xED, 0x00, 0x18, 0xD9, 0x55, +0x86, 0xF2, 0x00, 0x4A, 0xC6, 0xF3, 0x78, 0x9A, +0x01, 0x6C, 0x8C, 0xEB, 0x0D, 0x23, 0xC6, 0xF3, +0x5C, 0x9A, 0x05, 0x5A, 0x09, 0x61, 0x54, 0xA0, +0x30, 0xF0, 0x20, 0x6C, 0x0F, 0x6D, 0x03, 0xF5, +0x0C, 0x4C, 0x4C, 0xED, 0x00, 0x18, 0x4D, 0x63, 0x6E, 0xA0, 0x11, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0x4E, 0xC0, 0x91, 0x67, 0x07, 0x6D, 0x00, 0x6E, -0x00, 0x18, 0x9C, 0x58, 0x91, 0x67, 0x00, 0x18, -0xAE, 0x66, 0x73, 0xA0, 0x7F, 0x6A, 0x4C, 0xEB, +0x00, 0x18, 0xAC, 0x67, 0x91, 0x67, 0x00, 0x18, +0xE0, 0x74, 0x73, 0xA0, 0x7F, 0x6A, 0x4C, 0xEB, 0x73, 0xC0, 0x72, 0xA0, 0x6C, 0xEA, 0x52, 0xC0, 0x72, 0xA0, 0x41, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0x73, 0xA0, 0x52, 0xC0, 0x08, 0x6A, 0x4B, 0xEA, @@ -24923,8 +29787,8 @@ u8 array_mp_8822b_fw_nic[] = { 0x0B, 0x97, 0x0A, 0x91, 0x09, 0x90, 0x06, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0, 0xFF, 0x6A, 0x4C, 0xEC, -0xE6, 0x67, 0x2A, 0x6E, 0xD8, 0xEC, 0x30, 0xF0, -0x20, 0x6B, 0xAB, 0xF5, 0x1C, 0x4B, 0x04, 0xD4, +0xE6, 0x67, 0x2E, 0x6E, 0xD8, 0xEC, 0x30, 0xF0, +0x20, 0x6B, 0xAD, 0xF0, 0x00, 0x4B, 0x04, 0xD4, 0x25, 0x67, 0x4C, 0xE9, 0x4C, 0xEF, 0x12, 0xEE, 0xD9, 0xE3, 0x16, 0xA6, 0x60, 0xA6, 0x82, 0xA6, 0xA1, 0xA6, 0x01, 0x6E, 0x0C, 0xEE, 0x4C, 0xEE, @@ -24932,1242 +29796,1472 @@ u8 array_mp_8822b_fw_nic[] = { 0x08, 0x60, 0x24, 0x59, 0x83, 0xE3, 0x04, 0x60, 0x15, 0x59, 0x05, 0x67, 0x02, 0x61, 0xA1, 0xE4, 0x4C, 0xE8, 0x04, 0x94, 0xB0, 0x67, 0x00, 0x6E, -0x00, 0x18, 0x72, 0x60, 0x30, 0xF0, 0x20, 0x6A, -0x85, 0xF5, 0x18, 0x4A, 0xE5, 0xF5, 0x70, 0x9A, -0x01, 0x6C, 0x8C, 0xEB, 0x0D, 0x23, 0xE5, 0xF5, -0x54, 0x9A, 0x05, 0x5A, 0x09, 0x61, 0x04, 0x96, -0x30, 0xF0, 0x20, 0x6C, 0x83, 0xF1, 0x0C, 0x4C, -0xB1, 0x67, 0xF0, 0x67, 0x00, 0x18, 0xD9, 0x55, +0x00, 0x18, 0x9B, 0x6F, 0x30, 0xF0, 0x20, 0x6A, +0x86, 0xF2, 0x00, 0x4A, 0xC6, 0xF3, 0x78, 0x9A, +0x01, 0x6C, 0x8C, 0xEB, 0x0D, 0x23, 0xC6, 0xF3, +0x5C, 0x9A, 0x05, 0x5A, 0x09, 0x61, 0x04, 0x96, +0x30, 0xF0, 0x20, 0x6C, 0x03, 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0x67, 0x0D, 0xD7, 0x04, 0xD5, 0xCC, 0xE8, +0x00, 0x18, 0x53, 0x7C, 0x0F, 0x22, 0x04, 0x95, +0x91, 0x67, 0x00, 0x18, 0xEB, 0x7F, 0x0A, 0x22, +0x0D, 0x96, 0x91, 0x67, 0xB0, 0x67, 0x00, 0x18, +0xEC, 0x7E, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7, +0x62, 0x32, 0x01, 0x10, 0x00, 0x6A, 0x09, 0x97, +0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, +0x42, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -u32 array_length_mp_8822b_fw_nic = 127496; +u32 array_length_mp_8822b_fw_nic = 145104; + +#ifdef CONFIG_WOWLAN u8 array_mp_8822b_fw_wowlan[] = { -0x22, 0x88, 0x00, 0x00, 0x0D, 0x00, 0x01, 0x00, -0x67, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x03, 0x0D, 0x0F, 0x28, 0xE1, 0x07, 0x00, 0x00, -0x08, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, -0x00, 0x00, 0x20, 0x80, 0xB8, 0x0B, 0x00, 0x00, +0x22, 0x88, 0x00, 0x00, 0x16, 0x00, 0x06, 0x00, +0x42, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x04, 0x19, 0x0E, 0x27, 0xE2, 0x07, 0x00, 0x00, +0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, +0x00, 0x00, 0x20, 0x80, 0x48, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x38, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, +0xA0, 0x3C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x12, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -26178,11 +31272,11 @@ u8 array_mp_8822b_fw_wowlan[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x3D, 0x2D, 0x00, 0x80, 0xE5, 0x06, 0x00, 0x80, +0x71, 0x2F, 0x00, 0x80, 0xE5, 0x06, 0x00, 0x80, 0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE, 0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE, 0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE, -0xE9, 0x9B, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, +0xD5, 0xAA, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -26190,7 +31284,7 @@ u8 array_mp_8822b_fw_wowlan[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x49, 0x9D, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, +0xB9, 0xAC, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -26198,7 +31292,7 @@ u8 array_mp_8822b_fw_wowlan[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0xB8, 0x0B, 0x20, 0x80, 0x10, 0x70, 0xC9, 0x75, +0x48, 0x0B, 0x20, 0x80, 0x10, 0x70, 0xC9, 0x75, 0x10, 0x70, 0xC9, 0x75, 0x10, 0x70, 0xC9, 0x75, 0x10, 0x70, 0xC9, 0x75, 0x2A, 0xEA, 0xA0, 0x79, 0x2C, 0xEA, 0xA0, 0x79, 0x2A, 0xEA, 0xA0, 0x79, @@ -26219,247 +31313,228 @@ u8 array_mp_8822b_fw_wowlan[] = { 0x61, 0x63, 0x66, 0x86, 0x06, 0x00, 0x00, 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0x02, 0x64, 0xB8, 0x18, 0x11, 0x64, 0xB8, +0xFF, 0xFF, 0xFB, 0xFF, 0x00, 0x00, 0x78, 0x18, +0x04, 0x06, 0x64, 0xB8, 0x60, 0x16, 0x64, 0xB8, +0xFF, 0xFF, 0x01, 0xFF, 0x12, 0x05, 0x64, 0xB8, +0x10, 0x05, 0x64, 0xB8, 0x00, 0x00, 0x04, 0x04, +0x08, 0x08, 0x08, 0x08, 0x0C, 0x0C, 0x0C, 0x0C, +0x0C, 0x0C, 0x0C, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, +0x10, 0x10, 0x10, 0x10, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, -0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, -0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, +0x14, 0x14, 0x14, 0x14, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, @@ -26527,6 +31606,7 @@ u8 array_mp_8822b_fw_wowlan[] = { 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, +0x18, 0x18, 0x18, 0x18, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, @@ -26542,9 +31622,9 @@ u8 array_mp_8822b_fw_wowlan[] = { 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, -0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, -0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0xF2, 0x01, -0xDC, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x1C, 0x1C, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x00, +0x00, 0x50, 0xF2, 0x01, 0x00, 0x00, 0x00, 0x00, +0x53, 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -26619,63 +31699,63 @@ u8 array_mp_8822b_fw_wowlan[] = { 0x00, 0x6E, 0x30, 0xF0, 0x20, 0x6F, 0x00, 0xF0, 0x00, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, 0xE3, 0xEC, 0xB8, 0x67, 0xFB, 0x2D, 0x30, 0xF0, 0x20, 0x6C, -0xA1, 0xF3, 0x18, 0x4C, 0x00, 0x6E, 0x30, 0xF0, -0x20, 0x6F, 0x68, 0xF6, 0x10, 0x4F, 0xC0, 0xDC, +0x41, 0xF3, 0x08, 0x4C, 0x00, 0x6E, 0x30, 0xF0, +0x20, 0x6F, 0xE9, 0xF4, 0x08, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, 0xE3, 0xEC, 0xB8, 0x67, 0xFB, 0x2D, 0x10, 0xF0, 0x20, 0x6C, 0x60, 0xF2, 0x15, 0x4C, 0x00, 0xEC, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, -0x30, 0xF0, 0x20, 0x6B, 0x80, 0xF4, 0x68, 0x9B, +0x30, 0xF0, 0x20, 0x6B, 0x40, 0xF4, 0x7C, 0x9B, 0x10, 0xF0, 0x20, 0x6A, 0x60, 0xF2, 0x15, 0x4A, -0x40, 0xDB, 0x00, 0x18, 0x5E, 0x05, 0x00, 0x18, -0x75, 0x05, 0x00, 0x18, 0xD4, 0x07, 0x00, 0x18, -0x8C, 0x05, 0x00, 0x18, 0x7F, 0x07, 0x00, 0x18, -0xB5, 0x0E, 0x30, 0xF0, 0x20, 0x6C, 0x30, 0xF0, +0x40, 0xDB, 0x00, 0x18, 0xD6, 0x05, 0x00, 0x18, +0xF5, 0x05, 0x00, 0x18, 0x2F, 0x08, 0x00, 0x18, +0x10, 0x06, 0x00, 0x18, 0x0F, 0x08, 0x00, 0x18, +0xF6, 0x0F, 0x30, 0xF0, 0x20, 0x6C, 0x30, 0xF0, 0x21, 0x6A, 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0x20, 0x6B, 0x21, 0xF2, 0x1C, 0x4B, 0x49, 0xE3, 0x40, 0xA2, 0x30, 0xF0, 0x20, 0x6B, 0x40, 0xF0, 0x08, 0x4B, 0x69, 0xE2, 0x30, 0xF0, -0x20, 0x6B, 0x68, 0xF6, 0x08, 0x4B, 0x60, 0x9B, +0x20, 0x6B, 0x49, 0xF3, 0x10, 0x4B, 0x60, 0x9B, 0x05, 0x2B, 0x10, 0xF0, 0x20, 0x6B, 0x00, 0xF5, 0x1D, 0x4B, 0x00, 0xEB, 0x10, 0xF0, 0x20, 0x6B, 0xA0, 0xF5, 0x11, 0x4B, 0x00, 0xEB, 0x00, 0x65, 0x00, 0xF0, 0x20, 0x6B, 0x01, 0x6B, 0x30, 0xF0, -0x20, 0x6A, 0x68, 0xF6, 0x0C, 0x4A, 0x60, 0xDA, -0x30, 0xF0, 0x20, 0x6A, 0xA7, 0xF6, 0x18, 0x4A, +0x20, 0x6A, 0x49, 0xF3, 0x14, 0x4A, 0x60, 0xDA, +0x30, 0xF0, 0x20, 0x6A, 0xA8, 0xF3, 0x00, 0x4A, 0x60, 0xDA, 0x10, 0xF0, 0x20, 0x6B, 0xE0, 0xF3, 0x05, 0x4B, 0x00, 0xEB, 0x5A, 0xB8, 0x00, 0x65, 0x7B, 0xB8, 0x00, 0x65, 0x40, 0xE8, 0x5A, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x7B, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x30, 0xF0, -0x20, 0x6A, 0xA7, 0xF6, 0x18, 0x4A, 0x00, 0xF0, +0x20, 0x6A, 0xA8, 0xF3, 0x00, 0x4A, 0x00, 0xF0, 0x20, 0x6B, 0x60, 0xDA, 0x30, 0xF0, 0x20, 0x6A, -0x07, 0xF7, 0x10, 0x4A, 0x60, 0x9A, 0x41, 0x9A, +0xE8, 0xF3, 0x18, 0x4A, 0x60, 0x9A, 0x41, 0x9A, 0x6A, 0xEA, 0x0D, 0x61, 0x6E, 0xB8, 0x00, 0x65, 0x62, 0x43, 0xCB, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x5A, 0xB8, 0x00, 0x65, 0x7B, 0xB8, @@ -26687,14 +31767,14 @@ u8 array_mp_8822b_fw_wowlan[] = { 0x9A, 0xB8, 0x00, 0x65, 0x84, 0xDB, 0x9B, 0xB8, 0x00, 0x65, 0x85, 0xDB, 0x8E, 0xB8, 0x00, 0x65, 0x82, 0x44, 0x81, 0xDB, 0x8C, 0xB8, 0x00, 0x65, -0x80, 0xDB, 0x30, 0xF0, 0x20, 0x6B, 0x07, 0xF7, -0x10, 0x4B, 0x60, 0x9B, 0x9D, 0x67, 0x89, 0xDB, +0x80, 0xDB, 0x30, 0xF0, 0x20, 0x6B, 0xE8, 0xF3, +0x18, 0x4B, 0x60, 0x9B, 0x9D, 0x67, 0x89, 0xDB, 0x6A, 0x9B, 0xCF, 0xF7, 0x80, 0x44, 0x62, 0xEC, 0x0D, 0x60, 0x77, 0xF0, 0x24, 0x6C, 0xA0, 0xF1, 0x1C, 0x4C, 0x1D, 0xF4, 0x01, 0x6B, 0x60, 0xDC, -0x10, 0xF0, 0x20, 0x6C, 0x25, 0xF5, 0x1D, 0x4C, +0x10, 0xF0, 0x20, 0x6C, 0x65, 0xF7, 0x11, 0x4C, 0x00, 0xEC, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6B, -0x07, 0xF7, 0x10, 0x4B, 0x41, 0x9B, 0x40, 0xDB, +0xE8, 0xF3, 0x18, 0x4B, 0x41, 0x9B, 0x40, 0xDB, 0x89, 0x9A, 0xBC, 0x65, 0x7D, 0x67, 0xDF, 0xF7, 0x00, 0x03, 0x4C, 0xB8, 0x00, 0x65, 0x00, 0xF0, 0x20, 0x6D, 0x05, 0x4D, 0xAF, 0xED, 0xAC, 0xEA, @@ -26716,7 +31796,7 @@ u8 array_mp_8822b_fw_wowlan[] = { 0x84, 0xDB, 0x9B, 0xB8, 0x00, 0x65, 0x85, 0xDB, 0x7D, 0x67, 0x5B, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x40, 0x9A, 0x30, 0xF0, 0x20, 0x6C, -0x48, 0xF2, 0x0C, 0x4C, 0x00, 0xF4, 0x00, 0x4C, +0x28, 0xF7, 0x14, 0x4C, 0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65, 0x82, 0x67, 0x40, 0xEA, 0x00, 0x65, 0x7A, 0xB8, 0x00, 0x65, 0xBB, 0x65, 0xDF, 0xF7, 0x00, 0x03, 0x82, 0x9B, 0xA3, 0x9B, 0x32, 0xEC, @@ -26727,7 +31807,7 @@ u8 array_mp_8822b_fw_wowlan[] = { 0x0A, 0x9B, 0xE9, 0x9B, 0xC8, 0x9B, 0xA7, 0x9B, 0x86, 0x9B, 0x5A, 0xB8, 0x00, 0x65, 0x7B, 0xB8, 0x00, 0x65, 0x00, 0xBA, 0x00, 0x65, 0x00, 0x65, -0x30, 0xF0, 0x20, 0x6B, 0xA7, 0xF6, 0x18, 0x4B, +0x30, 0xF0, 0x20, 0x6B, 0xA8, 0xF3, 0x00, 0x4B, 0x40, 0xDB, 0xDF, 0xF7, 0x00, 0x03, 0x86, 0xDB, 0xA7, 0xDB, 0xC8, 0xDB, 0xE9, 0xDB, 0x0A, 0xDB, 0x2B, 0xDB, 0x98, 0x67, 0x8C, 0xDB, 0x9F, 0x67, @@ -26735,18 +31815,18 @@ u8 array_mp_8822b_fw_wowlan[] = { 0xA3, 0xDB, 0x9A, 0xB8, 0x00, 0x65, 0x84, 0xDB, 0x9B, 0xB8, 0x00, 0x65, 0x85, 0xDB, 0x8E, 0xB8, 0x00, 0x65, 0x81, 0xDB, 0x8C, 0xB8, 0x00, 0x65, -0x80, 0xDB, 0x30, 0xF0, 0x20, 0x6B, 0x07, 0xF7, -0x10, 0x4B, 0x60, 0x9B, 0x9D, 0x67, 0x89, 0xDB, +0x80, 0xDB, 0x30, 0xF0, 0x20, 0x6B, 0xE8, 0xF3, +0x18, 0x4B, 0x60, 0x9B, 0x9D, 0x67, 0x89, 0xDB, 0x6A, 0x9B, 0xCF, 0xF7, 0x80, 0x44, 0x62, 0xEC, 0x0D, 0x60, 0x77, 0xF0, 0x24, 0x6C, 0xA0, 0xF1, 0x1C, 0x4C, 0x1D, 0xF4, 0x01, 0x6B, 0x60, 0xDC, -0x10, 0xF0, 0x20, 0x6C, 0x25, 0xF5, 0x1D, 0x4C, +0x10, 0xF0, 0x20, 0x6C, 0x65, 0xF7, 0x11, 0x4C, 0x00, 0xEC, 0x00, 0x65, 0x40, 0x9A, 0x30, 0xF0, -0x20, 0x6C, 0x48, 0xF2, 0x0C, 0x4C, 0x00, 0xF4, +0x20, 0x6C, 0x28, 0xF7, 0x14, 0x4C, 0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65, 0x82, 0x67, 0x40, 0xEA, -0x30, 0xF0, 0x20, 0x6C, 0xA7, 0xF6, 0x18, 0x4C, +0x30, 0xF0, 0x20, 0x6C, 0xA8, 0xF3, 0x00, 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0x63, 0xF3, +0x98, 0xA0, 0x83, 0xF3, 0x48, 0xA0, 0x8D, 0xEA, +0xFF, 0x6C, 0x8C, 0xEA, 0x40, 0xC3, 0x30, 0xF0, +0x20, 0x6A, 0xE4, 0xF6, 0x25, 0xC2, 0x07, 0x97, +0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -27222,2563 +32362,2613 @@ u8 array_mp_8822b_fw_wowlan[] = { 0x10, 0xF0, 0x20, 0x6B, 0x20, 0xF7, 0x01, 0x4B, 0x66, 0xDA, 0x10, 0xF0, 0x20, 0x6B, 0x00, 0xF7, 0x11, 0x4B, 0x67, 0xDA, 0x20, 0xE8, 0x00, 0x65, -0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x1C, 0x4A, -0x00, 0x6B, 0xE2, 0xF6, 0x64, 0xC2, 0xE2, 0xF6, -0x65, 0xC2, 0xE2, 0xF6, 0x66, 0xC2, 0xE2, 0xF6, -0x67, 0xC2, 0x42, 0xF4, 0x10, 0x6A, 0x1F, 0xF7, +0x30, 0xF0, 0x20, 0x6A, 0x61, 0xF3, 0x10, 0x4A, +0x00, 0x6B, 0x63, 0xF3, 0x70, 0xC2, 0x63, 0xF3, +0x71, 0xC2, 0x63, 0xF3, 0x72, 0xC2, 0x63, 0xF3, +0x73, 0xC2, 0x42, 0xF4, 0x10, 0x6A, 0x1F, 0xF7, 0x00, 0x6B, 0x4C, 0xEB, 0x02, 0xF0, 0x00, 0x73, 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+0x00, 0xF2, 0x00, 0x4B, 0x43, 0xF2, 0x70, 0xDA, +0x01, 0xF2, 0x00, 0x4B, 0x43, 0xF2, 0x74, 0xDA, +0x00, 0xF2, 0x00, 0x4B, 0x43, 0xF2, 0x78, 0xDA, 0x20, 0xE8, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6A, -0x21, 0xF1, 0x44, 0x9A, 0xFF, 0x6B, 0x40, 0xA2, +0x81, 0xF0, 0x4C, 0x9A, 0xFF, 0x6B, 0x40, 0xA2, 0x6C, 0xEA, 0x5E, 0x32, 0x6C, 0xEA, 0x20, 0xE8, 0xFF, 0x6B, 0x6C, 0xEC, 0x1F, 0x6D, 0x8C, 0xED, 0x96, 0x34, 0x6C, 0xEC, 0x01, 0x74, 0x03, 0x6A, @@ -32960,178 +38797,178 @@ u8 array_mp_8822b_fw_wowlan[] = { 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0xFF, 0x6B, 0x8C, 0xEB, 0xFF, 0xF7, 0x1F, 0x6A, 0x81, 0x46, 0x26, 0x67, 0xAC, 0xEA, 0x06, 0x2C, -0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0xDB, 0x31, +0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0xC5, 0x37, 0x02, 0x67, 0x0A, 0x10, 0x83, 0x67, 0xA2, 0x67, -0x00, 0x18, 0xDB, 0x31, 0x02, 0x67, 0x91, 0x67, -0x00, 0x18, 0x7B, 0x27, 0x2C, 0xE8, 0x06, 0xEA, +0x00, 0x18, 0xC5, 0x37, 0x02, 0x67, 0x91, 0x67, +0x00, 0x18, 0x57, 0x2B, 0x2C, 0xE8, 0x06, 0xEA, 0x50, 0x67, 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0xD0, 0x67, 0x00, 0x18, +0x11, 0x39, 0xB8, 0x6D, 0xD0, 0x67, 0x01, 0x6F, +0x00, 0x6C, 0x00, 0x18, 0x11, 0x39, 0x91, 0x67, +0x00, 0x18, 0xD3, 0x4B, 0x91, 0x67, 0x00, 0x18, +0xE7, 0x4B, 0x01, 0x6A, 0x01, 0x10, 0x00, 0x6A, +0x19, 0x97, 0x18, 0x91, 0x17, 0x90, 0x0D, 0x63, +0x00, 0xEF, 0x00, 0x6A, 0x77, 0x17, 0x00, 0x65, +0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0, +0xFF, 0x68, 0x0C, 0xED, 0x24, 0x67, 0x0D, 0xD7, +0x04, 0xD5, 0xCC, 0xE8, 0x00, 0x18, 0x51, 0x4B, +0x0F, 0x22, 0x04, 0x95, 0x91, 0x67, 0x00, 0x18, +0x3F, 0x4E, 0x0A, 0x22, 0x0D, 0x96, 0x91, 0x67, +0xB0, 0x67, 0x00, 0x18, 0x6D, 0x4D, 0x4B, 0xEB, +0x4D, 0xEB, 0xC0, 0xF7, 0x62, 0x32, 0x01, 0x10, +0x00, 0x6A, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, +0x05, 0x63, 0x00, 0xEF, 0x51, 0x0B, 0x00, 0x00, +0xA9, 0xA6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -u32 array_length_mp_8822b_fw_wowlan = 73536; +u32 array_length_mp_8822b_fw_wowlan = 84024; + +#endif /*CONFIG_WOWLAN*/ #endif diff --git a/hal/rtl8822b/hal8822b_fw.h b/hal/rtl8822b/hal8822b_fw.h index 31e4c09..5968ac8 100644 --- a/hal/rtl8822b/hal8822b_fw.h +++ b/hal/rtl8822b/hal8822b_fw.h @@ -1,17 +1,17 @@ /****************************************************************************** - * - * Copyright(c) 2015 - 2017 Realtek Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - *****************************************************************************/ +* +* Copyright(c) 2012 - 2017 Realtek Corporation. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +******************************************************************************/ #ifdef CONFIG_RTL8822B @@ -20,15 +20,17 @@ #ifdef LOAD_FW_HEADER_FROM_DRIVER #if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) -extern u8 array_mp_8822b_fw_ap[81504]; +extern u8 array_mp_8822b_fw_ap[104632]; extern u32 array_length_mp_8822b_fw_ap; #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -extern u8 array_mp_8822b_fw_nic[127496]; +extern u8 array_mp_8822b_fw_nic[145104]; extern u32 array_length_mp_8822b_fw_nic; -extern u8 array_mp_8822b_fw_wowlan[73536]; +#ifdef CONFIG_WOWLAN +extern u8 array_mp_8822b_fw_wowlan[84024]; extern u32 array_length_mp_8822b_fw_wowlan; +#endif /*CONFIG_WOWLAN*/ #endif #endif /* end of LOAD_FW_HEADER_FROM_DRIVER */ diff --git a/hal/rtl8822b/rtl8822b.h b/hal/rtl8822b/rtl8822b.h index 978be7f..79545c4 100644 --- a/hal/rtl8822b/rtl8822b.h +++ b/hal/rtl8822b/rtl8822b.h @@ -54,21 +54,20 @@ void rtl8822b_init_default_value(PADAPTER); /* rtl8822b_mac.c */ u8 rtl8822b_rcr_config(PADAPTER, u32 rcr); -u8 rtl8822b_rcr_get(PADAPTER, u32 *rcr); -u8 rtl8822b_rcr_check(PADAPTER, u32 check_bit); -u8 rtl8822b_rcr_add(PADAPTER, u32 add); -u8 rtl8822b_rcr_clear(PADAPTER, u32 clear); u8 rtl8822b_rx_ba_ssn_appended(PADAPTER); u8 rtl8822b_rx_fcs_append_switch(PADAPTER, u8 enable); u8 rtl8822b_rx_fcs_appended(PADAPTER); u8 rtl8822b_rx_tsf_addr_filter_config(PADAPTER, u8 config); s32 rtl8822b_fw_dl(PADAPTER, u8 wowlan); +u8 rtl8822b_get_rx_drv_info_size(struct _ADAPTER *a); +u32 rtl8822b_get_tx_desc_size(struct _ADAPTER *a); +u32 rtl8822b_get_rx_desc_size(struct _ADAPTER *a); /* rtl8822b_ops.c */ u8 rtl8822b_read_efuse(PADAPTER); void rtl8822b_run_thread(PADAPTER); void rtl8822b_cancel_thread(PADAPTER); -void rtl8822b_sethwreg(PADAPTER, u8 variable, u8 *pval); +u8 rtl8822b_sethwreg(PADAPTER, u8 variable, u8 *pval); void rtl8822b_gethwreg(PADAPTER, u8 variable, u8 *pval); u8 rtl8822b_sethaldefvar(PADAPTER, HAL_DEF_VARIABLE, void *pval); u8 rtl8822b_gethaldefvar(PADAPTER, HAL_DEF_VARIABLE, void *pval); @@ -79,6 +78,7 @@ void rtl8822b_fill_txdesc_sectype(struct pkt_attrib *, u8 *ptxdesc); void rtl8822b_fill_txdesc_vcs(PADAPTER, struct pkt_attrib *, u8 *ptxdesc); void rtl8822b_fill_txdesc_phy(PADAPTER, struct pkt_attrib *, u8 *ptxdesc); void rtl8822b_fill_txdesc_force_bmc_camid(struct pkt_attrib *, u8 *ptxdesc); +void rtl8822b_fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); u8 rtl8822b_bw_mapping(PADAPTER, struct pkt_attrib *); u8 rtl8822b_sc_mapping(PADAPTER, struct pkt_attrib *); void rtl8822b_fill_txdesc_bf(struct xmit_frame *, u8 *desc); @@ -94,9 +94,15 @@ void rtl8822b_query_rx_desc(union recv_frame *, u8 *pdesc); /* rtl8822b_cmd.c */ s32 rtl8822b_fillh2ccmd(PADAPTER, u8 id, u32 buf_len, u8 *pbuf); void rtl8822b_set_FwMediaStatusRpt_cmd(PADAPTER, u8 mstatus, u8 macid); -void rtl8822b_set_FwMacIdConfig_cmd(PADAPTER , u64 bitmap, u8 *arg, u8 bw); void rtl8822b_set_FwRssiSetting_cmd(PADAPTER, u8 *param); void rtl8822b_set_FwPwrMode_cmd(PADAPTER, u8 psmode); + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW +void rtl8822b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); +#endif +#endif + void rtl8822b_set_FwPwrModeInIPS_cmd(PADAPTER adapter, u8 cmd_param); void rtl8822b_req_txrpt_cmd(PADAPTER, u8 macid); void rtl8822b_fw_update_beacon_cmd(PADAPTER); @@ -114,17 +120,15 @@ void rtl8822b_phy_init_dm_priv(PADAPTER); void rtl8822b_phy_deinit_dm_priv(PADAPTER); void rtl8822b_phy_init_haldm(PADAPTER); void rtl8822b_phy_haldm_watchdog(PADAPTER); -void rtl8822b_phy_haldm_in_lps(PADAPTER); -void rtl8822b_phy_haldm_watchdog_in_lps(PADAPTER); u32 rtl8822b_read_bb_reg(PADAPTER, u32 addr, u32 mask); void rtl8822b_write_bb_reg(PADAPTER, u32 addr, u32 mask, u32 val); -u32 rtl8822b_read_rf_reg(PADAPTER, u8 path, u32 addr, u32 mask); -void rtl8822b_write_rf_reg(PADAPTER, u8 path, u32 addr, u32 mask, u32 val); -void rtl8822b_set_channel_bw(PADAPTER, u8 center_ch, CHANNEL_WIDTH, u8 offset40, u8 offset80); +u32 rtl8822b_read_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask); +void rtl8822b_write_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask, u32 val); +void rtl8822b_set_channel_bw(PADAPTER adapter, u8 center_ch, enum channel_width, u8 offset40, u8 offset80); void rtl8822b_set_tx_power_level(PADAPTER, u8 channel); void rtl8822b_get_tx_power_level(PADAPTER, s32 *power); -void rtl8822b_set_tx_power_index(PADAPTER, u32 powerindex, u8 rfpath, u8 rate); -u8 rtl8822b_get_tx_power_index(PADAPTER, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); +void rtl8822b_set_tx_power_index(PADAPTER adapter, u32 powerindex, enum rf_path rfpath, u8 rate); +u8 rtl8822b_get_tx_power_index(PADAPTER adapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); void rtl8822b_notch_filter_switch(PADAPTER, bool enable); #ifdef CONFIG_BEAMFORMING void rtl8822b_phy_bf_init(PADAPTER); diff --git a/hal/rtl8822b/rtl8822b_cmd.c b/hal/rtl8822b/rtl8822b_cmd.c index 4f59767..2d2ec0b 100644 --- a/hal/rtl8822b/rtl8822b_cmd.c +++ b/hal/rtl8822b/rtl8822b_cmd.c @@ -221,120 +221,6 @@ static u8 get_ra_vht_en(u32 wirelessMode, u32 bitmap) return ret; } -static u8 get_ra_ldpc(struct sta_info *psta) -{ - u8 en_ldpc = 0; - - if (psta != NULL) { - if (psta->mac_id == 1) - en_ldpc = 0; - else { -#ifdef CONFIG_80211AC_VHT - if (is_supported_vht(psta->wireless_mode)) { - if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_CAP_TX)) - en_ldpc = 1; - else - en_ldpc = 0; - } else if (is_supported_ht(psta->wireless_mode)) { - if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_CAP_TX)) - en_ldpc = 1; - else - en_ldpc = 0; - } else -#endif - en_ldpc = 0; - } - } - - return en_ldpc; -} - - -/* - * arg[0] = macid - * arg[1] = raid - * arg[2] = shortGIrate - * arg[3] = init_rate - */ -void rtl8822b_set_FwMacIdConfig_cmd(PADAPTER adapter, u64 mask, u8 *arg, u8 bw) -{ - HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); - struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; - struct sta_info *psta = NULL; - u8 mac_id, init_rate, raid, sgi = _FALSE; - u8 ignore_bw = _FALSE; - u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; - - - if (hal->fw_ractrl == _FALSE) { - RTW_INFO(FUNC_ADPT_FMT" fw ractrl = _FALSE\n", - FUNC_ADPT_ARG(adapter)); - return; - } - - mac_id = arg[0]; - raid = arg[1]; - sgi = arg[2] & 0x0F; - ignore_bw = arg[2] >> 4; - init_rate = arg[3]; - - if (mac_id < macid_ctl->num) - psta = macid_ctl->sta[mac_id]; - - if (!psta) { - RTW_INFO(FUNC_ADPT_FMT" macid:%u, sta is NULL\n", - FUNC_ADPT_ARG(adapter), mac_id); - return; - } - - RTW_INFO(FUNC_ADPT_FMT ": mac_id=%d raid=0x%x bw=%d mask=0x%016llx\n", - FUNC_ADPT_ARG(adapter), mac_id, raid, bw, mask); - - - MACID_CFG_SET_CMD_ID(h2c, CMD_ID_MACID_CFG); - MACID_CFG_SET_CLASS(h2c, CLASS_MACID_CFG); - - /* common for h2c cmd 0x40 & 0x46 */ - MACID_CFG_SET_MAC_ID(h2c, mac_id); - MACID_CFG_SET_RATE_ID(h2c, raid); - MACID_CFG_SET_SGI(h2c, (sgi) ? 1 : 0); - MACID_CFG_SET_NO_UPDATE(h2c, (ignore_bw) ? 1 : 0); - MACID_CFG_SET_BW(h2c, bw); - MACID_CFG_SET_LDPC_CAP(h2c, get_ra_ldpc(psta)); - MACID_CFG_SET_WHT_EN(h2c, get_ra_vht_en(psta->wireless_mode, mask)); - - - /* DisableTXPowerTraining */ - if (hal->bDisableTXPowerTraining) { - MACID_CFG_SET_DISPT(h2c, 1); - RTW_INFO("%s: Disable PWT by driver\n", __FUNCTION__); - } else { - struct PHY_DM_STRUCT *p_dm_out_src = &hal->odmpriv; - - if (p_dm_out_src->is_disable_power_training) { - MACID_CFG_SET_DISPT(h2c, 1); - RTW_INFO("%s: Disable PWT by DM\n", __FUNCTION__); - } - } - - MACID_CFG_SET_RATE_MASK7_0(h2c, (u8)(mask & 0x000000ff)); - MACID_CFG_SET_RATE_MASK15_8(h2c, (u8)((mask & 0x0000ff00) >> 8)); - MACID_CFG_SET_RATE_MASK23_16(h2c, (u8)((mask & 0x00ff0000) >> 16)); - MACID_CFG_SET_RATE_MASK31_24(h2c, (u8)((mask & 0xff000000) >> 24)); - - RTW_INFO("%s, mask=0x%016llx, mac_id=0x%x, raid=0x%x, shortGIrate=%x, power training=%02x\n" - , __FUNCTION__, mask, mac_id, raid, sgi, h2c[2] & BIT(6)); - - RTW_DBG_DUMP("H2C-MACIDConfig Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); - rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); - - /* update initial rate */ - if (sgi) - init_rate |= BIT(7); - - hal->INIDATA_RATE[mac_id] = init_rate; -} - void rtl8822b_set_FwRssiSetting_cmd(PADAPTER adapter, u8 *param) { u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; @@ -392,38 +278,119 @@ void rtl8822b_req_txrpt_cmd(PADAPTER adapter, u8 macid) rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); } +/* + * lps_wait_bb_rf_ready() - Wait BB/RF ready after leaving LPS + * @adapter struct _ADAPTER* + * @timeout time to wait complete, unit is millisecond + * + * This function is used to wait BB and RF ready after leaving LPS. Besdies + * checking registers, it will wait 1 ms to let everything has time to finish + * their jobs, so this function will cost more than 1ms to return. Please call + * this function carefully, or you will waste time to wait. + * + * Return 0 for BB/RF ready, otherwise NOT ready. + * The error codes are as following: + * -1 unclassified error + * -2 RF ready check timeout + * -3 BB ready check timeout + */ +static int lps_wait_bb_rf_ready(struct _ADAPTER *adapter, u32 timeout) +{ + systime s_time; /* start time */ + u8 ready = 0; +#define RF_READY BIT(0) /* BB ready */ +#define BB_READY BIT(1) /* RF ready */ + u8 awake = _FALSE; + u8 sys_func_en; + + + s_time = rtw_get_current_time(); + + do { + if (!(ready & RF_READY)) { + rtw_hal_get_hwreg(adapter, HW_VAR_FWLPS_RF_ON, &awake); + if (awake == _TRUE) + ready |= RF_READY; + } + + if ((ready & RF_READY) && (!(ready & BB_READY))) { + sys_func_en = rtw_read8(adapter, REG_SYS_FUNC_EN_8822B); + if (sys_func_en & BIT_FEN_BBRSTB_8822B) + break; + } + + if (rtw_is_surprise_removed(adapter)) + return -1; + + if (rtw_get_passing_time_ms(s_time) > timeout) { + if (!(ready & RF_READY)) + return -2; + return -3; + } + + rtw_usleep_os(100); /* 100us interval between each check */ + } while (1); + + rtw_usleep_os(1000); /* Wait 1ms */ + + return 0; +} + void rtl8822b_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) { int i; u8 smart_ps = 0, mode = 0; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; +#ifdef CONFIG_WMMPS_STA + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct qos_priv *pqospriv = &pmlmepriv->qospriv; +#endif /* CONFIG_WMMPS_STA */ u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; u8 PowerState = 0, awake_intvl = 1, byte5 = 0, rlbm = 0; + u8 allQueueUAPSD = 0; + char *fw_psmode_str = ""; #ifdef CONFIG_P2P struct wifidirect_info *wdinfo = &adapter->wdinfo; #endif /* CONFIG_P2P */ if (pwrpriv->dtim > 0) - RTW_INFO(FUNC_ADPT_FMT ": FW LPS mode = %d, SmartPS=%d, dtim=%d, HW port id=%d\n", - FUNC_ADPT_ARG(adapter), psmode, pwrpriv->smart_ps, pwrpriv->dtim, - psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id:get_hw_port(adapter)); + RTW_INFO(FUNC_ADPT_FMT ": dtim=%d, HW port id=%d\n", FUNC_ADPT_ARG(adapter), + pwrpriv->dtim, psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id:get_hw_port(adapter)); else - RTW_INFO(FUNC_ADPT_FMT ": FW LPS mode = %d, SmartPS=%d, HW port id=%d\n", - FUNC_ADPT_ARG(adapter), psmode, pwrpriv->smart_ps, - psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id:get_hw_port(adapter)); + RTW_INFO(FUNC_ADPT_FMT ": HW port id=%d\n", FUNC_ADPT_ARG(adapter), + psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id:get_hw_port(adapter)); - if (psmode == PS_MODE_MIN) { - mode = 1; - rlbm = 0; - awake_intvl = 2; - smart_ps = pwrpriv->smart_ps; - } else if (psmode == PS_MODE_MAX) { - mode = 1; - rlbm = 1; - awake_intvl = 2; - smart_ps = pwrpriv->smart_ps; + if (psmode == PS_MODE_MIN || psmode == PS_MODE_MAX) { +#ifdef CONFIG_WMMPS_STA + if (rtw_is_wmmps_mode(adapter)) { + mode = 2; + + smart_ps = pwrpriv->wmm_smart_ps; + + /* (WMMPS) allQueueUAPSD: 0: PSPoll, 1: QosNullData (if wmm_smart_ps=1) or do nothing (if wmm_smart_ps=2) */ + if ((pqospriv->uapsd_tid & BIT_MASK_TID_TC) == ALL_TID_TC_SUPPORTED_UAPSD) + allQueueUAPSD = 1; + } else +#endif /* CONFIG_WMMPS_STA */ + { + mode = 1; +#ifdef CONFIG_WMMPS_STA + /* For WMMPS test case, the station must retain sleep mode to capture buffered data on LPS mechanism */ + if ((pqospriv->uapsd_tid & BIT_MASK_TID_TC) != 0) + smart_ps = 0; + else +#endif /* CONFIG_WMMPS_STA */ + { + smart_ps = pwrpriv->smart_ps; + } + } + + if (psmode == PS_MODE_MIN) + rlbm = 0; + else + rlbm = 1; } else if (psmode == PS_MODE_DTIM) { mode = 1; /* For WOWLAN LPS, DTIM = (awake_intvl - 1) */ @@ -436,11 +403,6 @@ void rtl8822b_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) rlbm = 2; smart_ps = pwrpriv->smart_ps; - } else if (psmode == PS_MODE_UAPSD_WMM) { - mode = 2; - rlbm = 0; /*1*/ - /*(WMM)smart_ps: 0:PS_Poll, 1:NullData*/ - smart_ps = (pwrpriv->smart_ps) ? 1 : 0; } else if (psmode == PS_MODE_ACTIVE) { mode = 0; } else { @@ -486,13 +448,25 @@ void rtl8822b_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) byte5 = 0x40; } + if (mode == 0) + fw_psmode_str = "ACTIVE"; + else if (mode == 1) + fw_psmode_str = "LPS"; + else if (mode == 2) + fw_psmode_str = "WMMPS"; + else + fw_psmode_str = "UNSPECIFIED"; + + RTW_INFO(FUNC_ADPT_FMT": fw ps mode = %s, drv ps mode = %d, rlbm = %d , smart_ps = %d, allQueueUAPSD = %d\n", + FUNC_ADPT_ARG(adapter), fw_psmode_str, psmode, rlbm, smart_ps, allQueueUAPSD); + SET_PWR_MODE_SET_CMD_ID(h2c, CMD_ID_SET_PWR_MODE); SET_PWR_MODE_SET_CLASS(h2c, CLASS_SET_PWR_MODE); SET_PWR_MODE_SET_MODE(h2c, mode); SET_PWR_MODE_SET_SMART_PS(h2c, smart_ps); SET_PWR_MODE_SET_RLBM(h2c, rlbm); SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c, awake_intvl); - SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c, adapter->registrypriv.uapsd_enable); + SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c, allQueueUAPSD); SET_PWR_MODE_SET_PWR_STATE(h2c, PowerState); if (psmode == PS_MODE_ACTIVE) { /* Leave LPS, set the same HW port ID */ @@ -563,8 +537,33 @@ void rtl8822b_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) RTW_DBG_DUMP("H2C-PwrMode Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); + + if (psmode == PS_MODE_ACTIVE) { + i = lps_wait_bb_rf_ready(adapter, 1000); + if (i) + RTW_WARN("%s: BB/RF status is unknown!(%d)\n", + __FUNCTION__, i); + } } +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW +void rtl8822b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable) +{ + u8 u1H2CSetPwrMode[RTW_HALMAC_H2C_MAX_SIZE] = {0}; + + SET_PWR_MODE_SET_CMD_ID(u1H2CSetPwrMode, CMD_ID_SET_PWR_MODE); + SET_PWR_MODE_SET_CLASS(u1H2CSetPwrMode, CLASS_SET_PWR_MODE); + SET_PWR_MODE_SET_MODE(u1H2CSetPwrMode, 1); + SET_PWR_MODE_SET_RLBM(u1H2CSetPwrMode, 1); + SET_PWR_MODE_SET_BCN_EARLY_RPT(u1H2CSetPwrMode, enable); + SET_PWR_MODE_SET_PWR_STATE(u1H2CSetPwrMode, 0x0C); + + rtw_halmac_send_h2c(adapter_to_dvobj(padapter), u1H2CSetPwrMode); +} +#endif +#endif + void rtl8822b_set_FwPwrModeInIPS_cmd(PADAPTER adapter, u8 cmd_param) { @@ -589,407 +588,6 @@ static s32 rtl8822b_set_FwLowPwrLps_cmd(PADAPTER adapter, u8 enable) } #ifdef CONFIG_BT_COEXIST -static void ConstructBeacon(PADAPTER adapter, u8 *pframe, u32 *pLength) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u32 rate_len, pktlen; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; - WLAN_BSSID_EX *cur_network = &pmlmeinfo->network; - u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); - - SetSeqNum(pwlanhdr, 0); - set_frame_sub_type(pframe, WIFI_BEACON); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - /* timestamp will be inserted by hardware */ - pframe += 8; - pktlen += 8; - - /* beacon interval: 2 bytes */ - _rtw_memcpy(pframe, (u8 *)rtw_get_beacon_interval_from_ie(cur_network->IEs), 2); - - pframe += 2; - pktlen += 2; - - /* capability info: 2 bytes */ - _rtw_memcpy(pframe, (u8 *)rtw_get_capability_from_ie(cur_network->IEs), 2); - - pframe += 2; - pktlen += 2; - - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { - pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs); - _rtw_memcpy(pframe, cur_network->IEs + sizeof(NDIS_802_11_FIXED_IEs), pktlen); - - goto _ConstructBeacon; - } - - /* below for ad-hoc mode */ - - /* SSID */ - pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen); - - /* supported rates... */ - rate_len = rtw_get_rateset_len(cur_network->SupportedRates); - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen); - - /* DS parameter set */ - pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen); - - if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { - u32 ATIMWindow; - /* IBSS Parameter Set... */ - ATIMWindow = 0; - pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen); - } - - /* todo: ERP IE */ - - /* EXTERNDED SUPPORTED RATE */ - if (rate_len > 8) - pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); - - - /* todo:HT for adhoc */ - -_ConstructBeacon: - - if ((pktlen + TXDESC_SIZE) > 512) { - RTW_INFO("beacon frame too large\n"); - return; - } - - *pLength = pktlen; -} - -static void ConstructPSPoll(PADAPTER adapter, u8 *pframe, u32 *pLength) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u32 pktlen; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; - - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - /* Frame control. */ - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - SetPwrMgt(fctrl); - set_frame_sub_type(pframe, WIFI_PSPOLL); - - /* AID. */ - set_duration(pframe, (pmlmeinfo->aid | 0xc000)); - - /* BSSID. */ - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - - /* TA. */ - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); - - *pLength = 16; -} - -static void ConstructNullFunctionData( - PADAPTER adapter, - u8 *pframe, - u32 *pLength, - u8 *StaAddr, - u8 bQoS, - u8 AC, - u8 bEosp, - u8 bForcePowerSave) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u32 pktlen; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct wlan_network *cur_network = &pmlmepriv->cur_network; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; - - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &pwlanhdr->frame_ctl; - *(fctrl) = 0; - if (bForcePowerSave) - SetPwrMgt(fctrl); - - switch (cur_network->network.InfrastructureMode) { - case Ndis802_11Infrastructure: - SetToDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN); - break; - case Ndis802_11APMode: - SetFrDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN); - break; - case Ndis802_11IBSS: - default: - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - break; - } - - SetSeqNum(pwlanhdr, 0); - - if (bQoS == _TRUE) { - struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; - - set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); - - pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe; - SetPriority(&pwlanqoshdr->qc, AC); - SetEOSP(&pwlanqoshdr->qc, bEosp); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); - } else { - set_frame_sub_type(pframe, WIFI_DATA_NULL); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - } - - *pLength = pktlen; -} - -static void ConstructProbeRsp(PADAPTER adapter, u8 *pframe, u32 *pLength, u8 *StaAddr, BOOLEAN bHideSSID) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u8 *mac, *bssid; - u32 pktlen; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; - WLAN_BSSID_EX *cur_network = &pmlmeinfo->network; -#if defined(CONFIG_AP_MODE) && defined(CONFIG_NATIVEAP_MLME) - u8 *pwps_ie; - uint wps_ielen; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; -#endif /* CONFIG_AP_MODE && CONFIG_NATIVEAP_MLME */ -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &adapter->wdinfo; -#ifdef CONFIG_WFD - u32 wfdielen = 0; -#endif /* CONFIG_WFD */ -#endif /* CONFIG_P2P */ - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - mac = adapter_mac_addr(adapter); - bssid = cur_network->MacAddress; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); - - RTW_INFO("%s FW Mac Addr:" MAC_FMT "\n", __FUNCTION__, MAC_ARG(mac)); - RTW_INFO("%s FW IP Addr" IP_FMT "\n", __FUNCTION__, IP_ARG(StaAddr)); - - SetSeqNum(pwlanhdr, 0); - set_frame_sub_type(fctrl, WIFI_PROBERSP); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - pframe += pktlen; - - if (cur_network->IELength > MAX_IE_SZ) - return; - - pwps_ie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, - cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen); - - /* inerset & update wps_probe_resp_ie */ - if ((pmlmepriv->wps_probe_resp_ie != NULL) && pwps_ie && (wps_ielen > 0)) { - uint wps_offset, remainder_ielen; - u8 *premainder_ie; - - wps_offset = (uint)(pwps_ie - cur_network->IEs); - - premainder_ie = pwps_ie + wps_ielen; - - remainder_ielen = cur_network->IELength - wps_offset - wps_ielen; - - _rtw_memcpy(pframe, cur_network->IEs, wps_offset); - pframe += wps_offset; - pktlen += wps_offset; - - wps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];/* to get ie data len */ - if ((wps_offset + wps_ielen + 2) <= MAX_IE_SZ) { - _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen + 2); - pframe += wps_ielen + 2; - pktlen += wps_ielen + 2; - } - - if ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) { - _rtw_memcpy(pframe, premainder_ie, remainder_ielen); - pframe += remainder_ielen; - pktlen += remainder_ielen; - } - } else { - _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); - pframe += cur_network->IELength; - pktlen += cur_network->IELength; - } - - /* retrieve SSID IE from cur_network->Ssid */ - { - u8 *ssid_ie; - sint ssid_ielen = 0; - sint ssid_ielen_diff; - u8 buf[MAX_IE_SZ]; - u8 *ies = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - - ssid_ie = rtw_get_ie(ies + _FIXED_IE_LENGTH_, _SSID_IE_, &ssid_ielen, - (pframe - ies) - _FIXED_IE_LENGTH_); - - ssid_ielen_diff = cur_network->Ssid.SsidLength - ssid_ielen; - - if (ssid_ie && cur_network->Ssid.SsidLength) { - uint remainder_ielen; - u8 *remainder_ie; - - remainder_ie = ssid_ie + 2; - remainder_ielen = pframe - remainder_ie; - - if (remainder_ielen > MAX_IE_SZ) { - RTW_WARN(FUNC_ADPT_FMT" remainder_ielen > MAX_IE_SZ\n", FUNC_ADPT_ARG(adapter)); - remainder_ielen = MAX_IE_SZ; - } - - _rtw_memcpy(buf, remainder_ie, remainder_ielen); - _rtw_memcpy(remainder_ie + ssid_ielen_diff, buf, remainder_ielen); - *(ssid_ie + 1) = cur_network->Ssid.SsidLength; - _rtw_memcpy(ssid_ie + 2, cur_network->Ssid.Ssid, cur_network->Ssid.SsidLength); - pframe += ssid_ielen_diff; - pktlen += ssid_ielen_diff; - } - } - -#ifdef CONFIG_P2P - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - u32 len; -#ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(adapter)->p2p_enabled && (pwdinfo->driver_interface == DRIVER_CFG80211)) { - /* if pwdinfo->role == P2P_ROLE_DEVICE will call issue_probersp_p2p() */ - len = pmlmepriv->p2p_go_probe_resp_ie_len; - if (pmlmepriv->p2p_go_probe_resp_ie && (len > 0)) - _rtw_memcpy(pframe, pmlmepriv->p2p_go_probe_resp_ie, len); - } else -#endif /* CONFIG_IOCTL_CFG80211 */ - { - len = build_probe_resp_p2p_ie(pwdinfo, pframe); - } - - pframe += len; - pktlen += len; - -#ifdef CONFIG_WFD -#ifdef CONFIG_IOCTL_CFG80211 - if (_FALSE == pwdinfo->wfd_info->wfd_enable) { - len = 0; - if (pmlmepriv->wfd_probe_resp_ie && (pmlmepriv->wfd_probe_resp_ie_len > 0)) { - len = pmlmepriv->wfd_probe_resp_ie_len; - _rtw_memcpy(pframe, pmlmepriv->wfd_probe_resp_ie, len); - } - } else -#endif /* CONFIG_IOCTL_CFG80211 */ - { - len = build_probe_resp_wfd_ie(pwdinfo, pframe, 0); - } - - pframe += len; - pktlen += len; -#endif /* CONFIG_WFD */ - } -#endif /* CONFIG_P2P */ - - *pLength = pktlen; -} - -static void ConstructBtNullFunctionData( - PADAPTER adapter, - u8 *pframe, - u32 *pLength, - u8 *StaAddr, - u8 bQoS, - u8 AC, - u8 bEosp, - u8 bForcePowerSave) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u32 pktlen; - struct mlme_ext_priv *pmlmeext; - struct mlme_ext_info *pmlmeinfo; - u8 bssid[ETH_ALEN]; - - - RTW_INFO("+" FUNC_ADPT_FMT ": qos=%d eosp=%d ps=%d\n", - FUNC_ADPT_ARG(adapter), bQoS, bEosp, bForcePowerSave); - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - pmlmeext = &adapter->mlmeextpriv; - pmlmeinfo = &pmlmeext->mlmext_info; - - if (NULL == StaAddr) { - _rtw_memcpy(bssid, adapter_mac_addr(adapter), ETH_ALEN); - StaAddr = bssid; - } - - fctrl = &pwlanhdr->frame_ctl; - *fctrl = 0; - if (bForcePowerSave) - SetPwrMgt(fctrl); - - SetFrDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN); - - set_duration(pwlanhdr, 0); - SetSeqNum(pwlanhdr, 0); - - if (bQoS == _TRUE) { - struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; - - set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); - - pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe; - SetPriority(&pwlanqoshdr->qc, AC); - SetEOSP(&pwlanqoshdr->qc, bEosp); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); - } else { - set_frame_sub_type(pframe, WIFI_DATA_NULL); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - } - - *pLength = pktlen; -} - static void SetFwRsvdPagePkt_BTCoex(PADAPTER adapter) { PHAL_DATA_TYPE hal; @@ -1001,9 +599,10 @@ static void SetFwRsvdPagePkt_BTCoex(PADAPTER adapter) u32 BeaconLength = 0; u32 BTQosNullLength = 0; u8 *ReservedPagePacket; - u8 TxDescLen, TxDescOffset; + u32 page_size, desc_size; + u8 TxDescOffset; u8 TotalPageNum = 0, CurtPktPageNum = 0, RsvdPageNum = 0; - u16 BufIndex, PageSize; + u16 BufIndex; u32 TotalPacketLen, MaxRsvdPageBufSize = 0; RSVDPAGE_LOC RsvdPageLoc; @@ -1012,12 +611,12 @@ static void SetFwRsvdPagePkt_BTCoex(PADAPTER adapter) pxmitpriv = &adapter->xmitpriv; pmlmeext = &adapter->mlmeextpriv; pmlmeinfo = &pmlmeext->mlmext_info; - TxDescLen = TXDESC_SIZE; + rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); + desc_size = rtl8822b_get_tx_desc_size(adapter); TxDescOffset = TXDESC_OFFSET; - rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize); RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE); - MaxRsvdPageBufSize = RsvdPageNum * PageSize; + MaxRsvdPageBufSize = RsvdPageNum * page_size; pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv); if (pcmdframe == NULL) { @@ -1030,13 +629,14 @@ static void SetFwRsvdPagePkt_BTCoex(PADAPTER adapter) /* (1) beacon */ BufIndex = TxDescOffset; - ConstructBeacon(adapter, &ReservedPagePacket[BufIndex], &BeaconLength); + rtw_hal_construct_beacon(adapter, + &ReservedPagePacket[BufIndex], &BeaconLength); /* * When we count the first page size, we need to reserve description size for the RSVD * packet, it will be filled in front of the packet in TXPKTBUF. */ - CurtPktPageNum = (u8)PageNum(TxDescLen + BeaconLength, PageSize); + CurtPktPageNum = (u8)PageNum(desc_size + BeaconLength, page_size); /* * If we don't add 1 more page, the WOWLAN function has a problem. * Maybe it's a bug of firmware? @@ -1045,25 +645,25 @@ static void SetFwRsvdPagePkt_BTCoex(PADAPTER adapter) CurtPktPageNum += 1; TotalPageNum += CurtPktPageNum; - BufIndex += (CurtPktPageNum * PageSize); + BufIndex += (CurtPktPageNum * page_size); /* Jump to lastest page */ - if (BufIndex < (MaxRsvdPageBufSize - PageSize)) { - BufIndex = TxDescOffset + (MaxRsvdPageBufSize - PageSize); + if (BufIndex < (MaxRsvdPageBufSize - page_size)) { + BufIndex = TxDescOffset + (MaxRsvdPageBufSize - page_size); TotalPageNum = RsvdPageNum - 1; } /* (6) BT Qos null data */ RsvdPageLoc.LocBTQosNull = TotalPageNum; - ConstructBtNullFunctionData( + rtw_hal_construct_NullFunctionData( adapter, &ReservedPagePacket[BufIndex], &BTQosNullLength, - NULL, + get_my_bssid(&pmlmeinfo->network), _TRUE, 0, 0, _FALSE); - rtw_hal_fill_fake_txdesc(adapter, &ReservedPagePacket[BufIndex - TxDescLen], BTQosNullLength, _FALSE, _TRUE, _FALSE); + rtw_hal_fill_fake_txdesc(adapter, &ReservedPagePacket[BufIndex - desc_size], BTQosNullLength, _FALSE, _TRUE, _FALSE); - CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength, PageSize); + CurtPktPageNum = (u8)PageNum(desc_size + BTQosNullLength, page_size); TotalPageNum += CurtPktPageNum; @@ -1205,32 +805,6 @@ void rtl8822b_download_BTCoex_AP_mode_rsvd_page(PADAPTER adapter) } #endif /* CONFIG_BT_COEXIST */ - -#ifdef CONFIG_TSF_RESET_OFFLOAD -/* - * ask FW to Reset sync register at Beacon early interrupt - */ -u8 rtl8822b_reset_tsf(PADAPTER adapter, u8 reset_port) -{ - u8 buf[2]; - u8 res = _SUCCESS; - - - if (HW_PORT0 == reset_port) { - buf[0] = 0x1; - buf[1] = 0; - } else { - buf[0] = 0x0; - buf[1] = 0x1; - } - - rtl8822b_fillh2ccmd(adapter, H2C_RESET_TSF, 2, buf); - - return res; -} -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - - void rtl8822b_fw_update_beacon_cmd(PADAPTER adapter) { } @@ -1241,10 +815,10 @@ void rtl8822b_fw_update_beacon_cmd(PADAPTER adapter) static void c2h_ccx_rpt(PADAPTER adapter, u8 *pdata) { #ifdef CONFIG_XMIT_ACK -#define C2H_CCX_RPT_GET_TX_STATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 30, 2) - u8 tx_state = _FALSE; + u8 tx_state; - tx_state = C2H_CCX_RPT_GET_TX_STATE(pdata); + + tx_state = CCX_RPT_GET_TX_STATE(pdata); /* 0 means success, 1 means retry drop */ if (tx_state == 0) @@ -1264,17 +838,29 @@ C2HTxRPTHandler_8822b( _irqL irqL; u8 macid = 0, IniRate = 0; u16 TxOK = 0, TxFail = 0; + struct sta_priv *pstapriv = &(GET_PRIMARY_ADAPTER(Adapter))->stapriv, *pstapriv_original = NULL; u8 TxOK0 = 0, TxOK1 = 0; u8 TxFail0 = 0, TxFail1 = 0; - struct sta_priv *pstapriv = &(Adapter->stapriv); struct sta_info *psta = NULL; - struct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(Adapter); + PADAPTER adapter_ognl = NULL; - if (!pstapriv->c2h_sta) { + if(!pstapriv->gotc2h) { + RTW_WARN("%s,%d: No gotc2h!\n", __FUNCTION__, __LINE__); + return; + } + + adapter_ognl = rtw_get_iface_by_id(GET_PRIMARY_ADAPTER(Adapter), pstapriv->c2h_adapter_id); + if(!adapter_ognl) { + RTW_WARN("%s: No adapter!\n", __FUNCTION__); + return; + } + + psta = rtw_get_stainfo(&adapter_ognl->stapriv, pstapriv->c2h_sta_mac); + if (!psta) { RTW_WARN("%s: No corresponding sta_info!\n", __FUNCTION__); return; } - psta = pstapriv->c2h_sta; + macid = C2H_AP_REQ_TXRPT_GET_STA1_MACID(CmdBuf); TxOK0 = C2H_AP_REQ_TXRPT_GET_TX_OK1_0(CmdBuf); TxOK1 = C2H_AP_REQ_TXRPT_GET_TX_OK1_1(CmdBuf); @@ -1297,19 +883,30 @@ C2HSPC_STAT_8822b( ) { _irqL irqL; - struct sta_priv *pstapriv = &(Adapter->stapriv); + struct sta_priv *pstapriv = &(GET_PRIMARY_ADAPTER(Adapter))->stapriv; struct sta_info *psta = NULL; struct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(Adapter); _list *plist, *phead; u8 idx = C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(CmdBuf); + PADAPTER adapter_ognl = NULL; + + if(!pstapriv->gotc2h) { + RTW_WARN("%s, %d: No gotc2h!\n", __FUNCTION__, __LINE__); + return; + } + + adapter_ognl = rtw_get_iface_by_id(GET_PRIMARY_ADAPTER(Adapter), pstapriv->c2h_adapter_id); + if(!adapter_ognl) { + RTW_WARN("%s: No adapter!\n", __FUNCTION__); + return; + } - if (!pstapriv->c2h_sta) { + psta = rtw_get_stainfo(&adapter_ognl->stapriv, pstapriv->c2h_sta_mac); + if (!psta) { RTW_WARN("%s: No corresponding sta_info!\n", __FUNCTION__); return; } - psta = pstapriv->c2h_sta; psta->sta_stats.tx_retry_cnt = (C2H_SPECIAL_STATISTICS_GET_DATA3(CmdBuf) << 8) | C2H_SPECIAL_STATISTICS_GET_DATA2(CmdBuf); - pstapriv->c2h_sta = NULL; rtw_sctx_done(&pstapriv->gotc2h); } @@ -1320,10 +917,9 @@ C2HSPC_STAT_8822b( */ static void process_c2h_event(PADAPTER adapter, u8 *c2h, u32 size) { - PHAL_DATA_TYPE hal; struct mlme_ext_priv *pmlmeext; struct mlme_ext_info *pmlmeinfo; - struct PHY_DM_STRUCT *p_dm_odm; + u32 desc_size; u8 id, seq; u8 c2h_len, c2h_payload_len; u8 *pc2h_data, *pc2h_payload; @@ -1334,20 +930,20 @@ static void process_c2h_event(PADAPTER adapter, u8 *c2h, u32 size) return; } - if (size < HALMAC_RX_DESC_SIZE_8822B) { + desc_size = rtl8822b_get_rx_desc_size(adapter); + + if (size < desc_size) { RTW_INFO("%s: c2h length(%d) is smaller than RXDESC_SIZE(%d)!!\n", - __FUNCTION__, size, HALMAC_RX_DESC_SIZE_8822B); + __FUNCTION__, size, desc_size); return; } - hal = GET_HAL_DATA(adapter); - p_dm_odm = &hal->odmpriv; pmlmeext = &adapter->mlmeextpriv; pmlmeinfo = &pmlmeext->mlmext_info; /* shift rx desc len */ - pc2h_data = c2h + HALMAC_RX_DESC_SIZE_8822B; - c2h_len = size - HALMAC_RX_DESC_SIZE_8822B; + pc2h_data = c2h + desc_size; + c2h_len = size - desc_size; id = C2H_GET_CMD_ID(pc2h_data); seq = C2H_GET_SEQ(pc2h_data); @@ -1364,10 +960,6 @@ static void process_c2h_event(PADAPTER adapter, u8 *c2h, u32 size) break; #endif /* CONFIG_BEAMFORMING */ - case CMD_ID_C2H_CCX_RPT: - c2h_ccx_rpt(adapter, pc2h_data); - break; - case CMD_ID_C2H_AP_REQ_TXRPT: /*RTW_INFO("[C2H], C2H_AP_REQ_TXRPT!!\n");*/ C2HTxRPTHandler_8822b(adapter, pc2h_data, c2h_len); @@ -1378,10 +970,20 @@ static void process_c2h_event(PADAPTER adapter, u8 *c2h, u32 size) C2HSPC_STAT_8822b(adapter, pc2h_data, c2h_len); break; + case CMD_ID_C2H_CUR_CHANNEL: + { + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct submit_ctx *chsw_sctx = &hal->chsw_sctx; + + /* RTW_INFO("[C2H], CMD_ID_C2H_CUR_CHANNEL!!\n"); */ + rtw_sctx_done(&chsw_sctx); + break; + } + case C2H_EXTEND: if (C2H_HDR_GET_C2H_SUB_CMD_ID(pc2h_data) == C2H_SUB_CMD_ID_CCX_RPT) { /* Shift C2H HDR 4 bytes */ - c2h_ccx_rpt(adapter, pc2h_data + 4); + c2h_ccx_rpt(adapter, pc2h_data); break; } @@ -1401,9 +1003,15 @@ void rtl8822b_c2h_handler(PADAPTER adapter, u8 *pbuf, u16 length) #ifdef CONFIG_WOWLAN struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + if (pwrpriv->wowlan_mode == _TRUE) { +#ifdef CONFIG_RTW_DEBUG + u32 desc_size; + + desc_size = rtl8822b_get_rx_desc_size(adapter); RTW_INFO("%s: return because wowolan_mode==TRUE! CMDID=%d\n", - __FUNCTION__, C2H_GET_CMD_ID(pbuf + RXDESC_SIZE)); + __FUNCTION__, C2H_GET_CMD_ID(pbuf + desc_size)); +#endif /* CONFIG_RTW_DEBUG */ return; } #endif /* CONFIG_WOWLAN*/ @@ -1417,6 +1025,7 @@ void rtl8822b_c2h_handler(PADAPTER adapter, u8 *pbuf, u16 length) */ void rtl8822b_c2h_handler_no_io(PADAPTER adapter, u8 *pbuf, u16 length) { + u32 desc_size; u8 id, seq; u8 *pc2h_content; u8 res; @@ -1425,12 +1034,14 @@ void rtl8822b_c2h_handler_no_io(PADAPTER adapter, u8 *pbuf, u16 length) if ((length == 0) || (!pbuf)) return; + desc_size = rtl8822b_get_rx_desc_size(adapter); + /* shift rx desc len to get c2h packet content */ - pc2h_content = pbuf + HALMAC_RX_DESC_SIZE_8822B; + pc2h_content = pbuf + desc_size; id = C2H_GET_CMD_ID(pc2h_content); seq = C2H_GET_SEQ(pc2h_content); - RTW_INFO("%s: C2H, ID=%d seq=%d len=%d\n", + RTW_DBG("%s: C2H, ID=%d seq=%d len=%d\n", __FUNCTION__, id, seq, length); switch (id) { diff --git a/hal/rtl8822b/rtl8822b_halinit.c b/hal/rtl8822b/rtl8822b_halinit.c index a58bf55..b1aeb08 100644 --- a/hal/rtl8822b/rtl8822b_halinit.c +++ b/hal/rtl8822b/rtl8822b_halinit.c @@ -48,7 +48,15 @@ void rtl8822b_init_hal_spec(PADAPTER adapter) | WL_FUNC_TDLS ; + hal_spec->pg_txpwr_saddr = 0x10; + hal_spec->hci_type = 0; + + rtw_macid_ctl_init_sleep_reg(adapter_to_macidctl(adapter) + , REG_MACID_SLEEP_8822B + , REG_MACID_SLEEP1_8822B + , REG_MACID_SLEEP2_8822B + , REG_MACID_SLEEP3_8822B); } u32 rtl8822b_power_on(PADAPTER adapter) @@ -154,7 +162,7 @@ u8 rtl8822b_hal_init(PADAPTER adapter) hal->firmware_version, hal->firmware_sub_version, hal->firmware_size); /* Sync driver status with hardware setting */ - rtl8822b_rcr_get(adapter, NULL); + rtw_hal_get_hwreg(adapter, HW_VAR_RCR, NULL); hal->bFWReady = _TRUE; hal->fw_ractrl = _TRUE; @@ -223,7 +231,7 @@ void rtl8822b_init_misc(PADAPTER adapter) invalidate_cam_all(adapter); /* check RCR/ICV bit */ - rtl8822b_rcr_clear(adapter, BIT_ACRC32_8822B | BIT_AICV_8822B); + rtw_hal_rcr_clear(adapter, BIT_ACRC32_8822B | BIT_AICV_8822B); /* clear rx ctrl frame */ rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0); @@ -237,6 +245,7 @@ void rtl8822b_init_misc(PADAPTER adapter) rtw_read32(adapter, REG_FWHW_TXQ_CTRL_8822B) | BIT_EN_QUEUE_RPT_8822B(BIT(4))); #endif /* CONFIG_XMIT_ACK */ + rtw_write8(adapter, REG_TIMER0_SRC_SEL_8822B, rtw_read8(adapter, REG_TIMER0_SRC_SEL_8822B) & ~BIT(6)); } u32 rtl8822b_init(PADAPTER adapter) @@ -309,10 +318,6 @@ void rtl8822b_init_default_value(PADAPTER adapter) /* init phydm default value */ hal->bIQKInitialized = _FALSE; - hal->odmpriv.rf_calibrate_info.tm_trigger = 0; /* for IQK */ - hal->odmpriv.rf_calibrate_info.thermal_value_hp_index = 0; - for (i = 0; i < HP_THERMAL_NUM; i++) - hal->odmpriv.rf_calibrate_info.thermal_value_hp[i] = 0; /* init Efuse variables */ hal->EfuseUsedBytes = 0; diff --git a/hal/rtl8822b/rtl8822b_mac.c b/hal/rtl8822b/rtl8822b_mac.c index 4ceac65..4397576 100644 --- a/hal/rtl8822b/rtl8822b_mac.c +++ b/hal/rtl8822b/rtl8822b_mac.c @@ -56,65 +56,9 @@ inline u8 rtl8822b_rcr_config(PADAPTER p, u32 rcr) return _TRUE; } -inline u8 rtl8822b_rcr_get(PADAPTER p, u32 *rcr) -{ - u32 v32; - - v32 = rtw_read32(p, REG_RCR_8822B); - if (rcr) - *rcr = v32; - GET_HAL_DATA(p)->ReceiveConfig = v32; - return _TRUE; -} - -inline u8 rtl8822b_rcr_check(PADAPTER p, u32 check_bit) -{ - PHAL_DATA_TYPE hal; - u32 rcr; - - hal = GET_HAL_DATA(p); - rcr = hal->ReceiveConfig; - if ((rcr & check_bit) == check_bit) - return _TRUE; - - return _FALSE; -} - -inline u8 rtl8822b_rcr_add(PADAPTER p, u32 add) -{ - PHAL_DATA_TYPE hal; - u32 rcr; - u8 ret = _TRUE; - - hal = GET_HAL_DATA(p); - - rcr = hal->ReceiveConfig; - rcr |= add; - if (rcr != hal->ReceiveConfig) - ret = rtl8822b_rcr_config(p, rcr); - - return ret; -} - -inline u8 rtl8822b_rcr_clear(PADAPTER p, u32 clear) -{ - PHAL_DATA_TYPE hal; - u32 rcr; - u8 ret = _TRUE; - - hal = GET_HAL_DATA(p); - - rcr = hal->ReceiveConfig; - rcr &= ~clear; - if (rcr != hal->ReceiveConfig) - ret = rtl8822b_rcr_config(p, rcr); - - return ret; -} - inline u8 rtl8822b_rx_ba_ssn_appended(PADAPTER p) { - return rtl8822b_rcr_check(p, BIT_APP_BASSN_8822B); + return rtw_hal_rcr_check(p, BIT_APP_BASSN_8822B); } inline u8 rtl8822b_rx_fcs_append_switch(PADAPTER p, u8 enable) @@ -124,16 +68,16 @@ inline u8 rtl8822b_rx_fcs_append_switch(PADAPTER p, u8 enable) rcr_bit = BIT_APP_FCS_8822B; if (_TRUE == enable) - ret = rtl8822b_rcr_add(p, rcr_bit); + ret = rtw_hal_rcr_add(p, rcr_bit); else - ret = rtl8822b_rcr_clear(p, rcr_bit); + ret = rtw_hal_rcr_clear(p, rcr_bit); return ret; } inline u8 rtl8822b_rx_fcs_appended(PADAPTER p) { - return rtl8822b_rcr_check(p, BIT_APP_FCS_8822B); + return rtw_hal_rcr_check(p, BIT_APP_FCS_8822B); } inline u8 rtl8822b_rx_tsf_addr_filter_config(PADAPTER p, u8 config) @@ -213,3 +157,60 @@ s32 rtl8822b_fw_dl(PADAPTER adapter, u8 wowlan) return _FAIL; } } + +u8 rtl8822b_get_rx_drv_info_size(struct _ADAPTER *a) +{ + struct dvobj_priv *d; + u8 size = 80; /* HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX */ + int err = 0; + + + d = adapter_to_dvobj(a); + + err = rtw_halmac_get_rx_drv_info_sz(d, &size); + if (err) { + RTW_WARN(FUNC_ADPT_FMT ": Fail to get DRV INFO size!!(err=%d)\n", + FUNC_ADPT_ARG(a), err); + size = 80; + } + + return size; +} + +u32 rtl8822b_get_tx_desc_size(struct _ADAPTER *a) +{ + struct dvobj_priv *d; + u32 size = 48; /* HALMAC_TX_DESC_SIZE_8822B */ + int err = 0; + + + d = adapter_to_dvobj(a); + + err = rtw_halmac_get_tx_desc_size(d, &size); + if (err) { + RTW_WARN(FUNC_ADPT_FMT ": Fail to get TX Descriptor size!!(err=%d)\n", + FUNC_ADPT_ARG(a), err); + size = 48; + } + + return size; +} + +u32 rtl8822b_get_rx_desc_size(struct _ADAPTER *a) +{ + struct dvobj_priv *d; + u32 size = 24; /* HALMAC_RX_DESC_SIZE_8822B */ + int err = 0; + + + d = adapter_to_dvobj(a); + + err = rtw_halmac_get_rx_desc_size(d, &size); + if (err) { + RTW_WARN(FUNC_ADPT_FMT ": Fail to get RX Descriptor size!!(err=%d)\n", + FUNC_ADPT_ARG(a), err); + size = 24; + } + + return size; +} diff --git a/hal/rtl8822b/rtl8822b_ops.c b/hal/rtl8822b/rtl8822b_ops.c index 96b1183..e0dbf72 100644 --- a/hal/rtl8822b/rtl8822b_ops.c +++ b/hal/rtl8822b/rtl8822b_ops.c @@ -98,6 +98,20 @@ static const struct hw_port_reg port_cfg[] = { .ps_aid = REG_BCN_PSR_RPT4_8822B, }, }; +static void hw_bcn_ctrl_set(_adapter *adapter, u8 bcn_ctl_val) +{ + u8 hw_port = get_hw_port(adapter); + u32 bcn_ctl_addr = 0; + + if (hw_port >= MAX_HW_PORT) { + RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port); + rtw_warn_on(1); + return; + } + + bcn_ctl_addr = port_cfg[hw_port].bcn_ctl; + rtw_write8(adapter, bcn_ctl_addr, bcn_ctl_val); +} static void hw_bcn_ctrl_add(_adapter *adapter, u8 bcn_ctl_val) { @@ -197,7 +211,7 @@ static u8 Hal_EfuseParseIDCode(PADAPTER adapter, u8 *map) if (EEPROMId == RTL_EEPROM_ID) return _TRUE; - RTW_INFO(" EEPROM ID is invalid!!\n"); + RTW_WARN("EEPROM ID is invalid!!\n"); return _FALSE; } @@ -245,17 +259,9 @@ static void Hal_EfuseParseBoardType(PADAPTER adapter, u8 *map, u8 mapvalid) static void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); u8 setting; u32 tmpu4; -#ifdef CONFIG_RTW_MAC_HIDDEN_RPT - if (hal_spec->hci_type <= 3 && hal_spec->hci_type >= 1) { - hal->EEPROMBluetoothCoexist = _FALSE; - goto exit; - } -#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */ - if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8822B] != 0xFF)) { /* 0xc1[7:5] = 0x01 */ if (((map[EEPROM_RF_BOARD_OPTION_8822B] & 0xe0) >> 5) == 0x01) @@ -271,13 +277,13 @@ static void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid) if ((_TRUE == mapvalid) && (setting != 0xFF)) { hal->EEPROMBluetoothAntNum = setting & BIT(0); /* - * EFUSE_0xC3[6] == 0, S1(Main)-ODM_RF_PATH_A; - * EFUSE_0xC3[6] == 1, S0(Aux)-ODM_RF_PATH_B + * EFUSE_0xC3[6] == 0, S1(Main)-RF_PATH_A; + * EFUSE_0xC3[6] == 1, S0(Aux)-RF_PATH_B */ - hal->ant_path = (setting & BIT(6)) ? ODM_RF_PATH_B : ODM_RF_PATH_A; + hal->ant_path = (setting & BIT(6)) ? RF_PATH_B : RF_PATH_A; } else { hal->EEPROMBluetoothAntNum = Ant_x2; - hal->ant_path = ODM_RF_PATH_A; + hal->ant_path = RF_PATH_A; } exit: @@ -370,7 +376,7 @@ static void Hal_EfuseParseCustomerID(PADAPTER adapter, u8 *map, u8 mapvalid) if (_TRUE == mapvalid) - hal->EEPROMCustomerID = map[EEPROM_CustomID_8723B]; + hal->EEPROMCustomerID = map[EEPROM_CustomID_8822B]; else hal->EEPROMCustomerID = 0; RTW_INFO("EEPROM Customer ID=0x%02x\n", hal->EEPROMCustomerID); @@ -565,6 +571,23 @@ static void Hal_ReadUsbModeSwitch(PADAPTER adapter, u8 *map, u8 mapvalid) RTW_INFO("EEPROM USB Switch=%d\n", hal->EEPROMUsbSwitch); } + +static void hal_read_usb_pid_vid(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + if (_TRUE == mapvalid) { + /* VID, PID */ + hal->EEPROMVID = ReadLE2Byte(&map[EEPROM_VID_8822BU]); + hal->EEPROMPID = ReadLE2Byte(&map[EEPROM_PID_8822BU]); + } else { + hal->EEPROMVID = EEPROM_Default_VID; + hal->EEPROMPID = EEPROM_Default_PID; + } + + RTW_INFO("EEPROM VID = 0x%04X, PID = 0x%04X\n", hal->EEPROMVID, hal->EEPROMPID); +} + #endif /* CONFIG_USB_HCI */ /* @@ -587,11 +610,6 @@ u8 rtl8822b_read_efuse(PADAPTER adapter) hal = GET_HAL_DATA(adapter); efuse_map = hal->efuse_eeprom_data; -#ifdef CONFIG_RTW_MAC_HIDDEN_RPT - if (hal_read_mac_hidden_rpt(adapter) != _SUCCESS) - goto exit; -#endif - /* 1. Read registers to check hardware eFuse available or not */ val8 = rtw_read8(adapter, REG_SYS_EEPROM_CTRL_8822B); hal->EepromOrEfuse = (val8 & BIT_EERPOMSEL_8822B) ? _TRUE : _FALSE; @@ -608,7 +626,7 @@ u8 rtl8822b_read_efuse(PADAPTER adapter) #ifdef CONFIG_EFUSE_CONFIG_FILE if (check_phy_efuse_tx_power_info_valid(adapter) == _FALSE) { if (Hal_readPGDataFromConfigFile(adapter) != _SUCCESS) - RTW_INFO("%s: invalid phy efuse and read from file fail, will use driver default!!\n", __FUNCTION__); + RTW_WARN("%s: invalid phy efuse and read from file fail, will use driver default!!\n", __FUNCTION__); } #endif /* CONFIG_EFUSE_CONFIG_FILE */ @@ -640,8 +658,25 @@ u8 rtl8822b_read_efuse(PADAPTER adapter) #ifdef CONFIG_USB_HCI Hal_ReadUsbModeSwitch(adapter, efuse_map, valid); + hal_read_usb_pid_vid(adapter, efuse_map, valid); #endif /* CONFIG_USB_HCI */ + /* set coex. ant info once efuse parsing is done */ + rtw_btcoex_set_ant_info(adapter); + +#ifdef CONFIG_RTW_MAC_HIDDEN_RPT + hal_read_mac_hidden_rpt(adapter); + { + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + + if (hal_spec->hci_type <= 3 && hal_spec->hci_type >= 1) { + hal->EEPROMBluetoothCoexist = _FALSE; + RTW_INFO("EEPROM Disable BT-coex by hal_spec\n"); + rtw_btcoex_wifionly_AntInfoSetting(adapter); + } + } +#endif + ret = _SUCCESS; exit: @@ -676,19 +711,6 @@ static u8 check_ips_status(PADAPTER adapter) return _FALSE; } -static void update_ra_mask_8822b(_adapter *adapter, struct sta_info *psta, struct macid_cfg *h2c_macid_cfg) -{ - u8 arg[4] = {0}; - - arg[0] = h2c_macid_cfg->mac_id; - arg[1] = h2c_macid_cfg->rate_id; - arg[2] = (h2c_macid_cfg->ignore_bw << 4) | h2c_macid_cfg->short_gi; - arg[3] = psta->init_rate; - - rtl8822b_set_FwMacIdConfig_cmd(adapter, h2c_macid_cfg->ra_mask, arg, h2c_macid_cfg->bandwidth); - -} - static void InitBeaconParameters(PADAPTER adapter) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); @@ -705,14 +727,13 @@ static void InitBeaconParameters(PADAPTER adapter) #endif rtw_write16(adapter, REG_BCN_CTRL_8822B, val16); - /* setup time:128 us */ - rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B, 0x04); + /* TBTT setup time */ + rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B, TBTT_PROHIBIT_SETUP_TIME); - /*TBTT hold time :4ms 0x540[19:8]*/ - rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 1, - TBTT_PROBIHIT_HOLD_TIME & 0xFF); + /* TBTT hold time: 0x540[19:8] */ + rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF); rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 2, - (rtw_read8(adapter, REG_TBTT_PROHIBIT_8822B + 2) & 0xF0) | (TBTT_PROBIHIT_HOLD_TIME >> 8)); + (rtw_read8(adapter, REG_TBTT_PROHIBIT_8822B + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8)); rtw_write8(adapter, REG_DRVERLYINT_8822B, DRIVER_EARLY_INT_TIME_8822B); /* 5ms */ rtw_write8(adapter, REG_BCNDMATIM_8822B, BCN_DMA_ATIME_INT_TIME_8822B); /* 2ms */ @@ -816,18 +837,21 @@ static void set_beacon_related_registers(PADAPTER adapter) ResumeTxBeacon(adapter); } +#ifdef DBG_CONFIG_ERROR_DETECT static void xmit_status_check(PADAPTER p) { PHAL_DATA_TYPE hal = GET_HAL_DATA(p); struct sreset_priv *psrtpriv = &hal->srestpriv; struct xmit_priv *pxmitpriv = &p->xmitpriv; - unsigned long current_time = 0; + systime current_time = 0; unsigned int diff_time = 0; u32 txdma_status = 0; txdma_status = rtw_read32(p, REG_TXDMA_STATUS_8822B); if (txdma_status != 0x00) { RTW_INFO("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status); + psrtpriv->tx_dma_status_cnt++; + psrtpriv->self_dect_case = 4; rtw_hal_sreset_reset(p); } #ifdef CONFIG_USB_HCI @@ -849,12 +873,15 @@ static void xmit_status_check(PADAPTER p) RTW_INFO("%s tx hang %s\n", __FUNCTION__, (ability & ODM_BB_ADAPTIVITY) ? "ODM_BB_ADAPTIVITY" : ""); - if (!(ability & ODM_BB_ADAPTIVITY)) + if (!(ability & ODM_BB_ADAPTIVITY)) { + psrtpriv->self_dect_tx_cnt++; + psrtpriv->self_dect_case = 1; rtw_hal_sreset_reset(p); } } } } + } #endif /* CONFIG_USB_HCI */ if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) { @@ -864,15 +891,66 @@ static void xmit_status_check(PADAPTER p) } } +static void check_rx_count(PADAPTER p) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(p); + struct sreset_priv *psrtpriv = &hal->srestpriv; + u16 cur_mac_rxff_ptr; + + cur_mac_rxff_ptr = rtw_read16(p, REG_RXFF_PTR_V1_8822B); + +#if 0 + RTW_INFO("%s,psrtpriv->last_mac_rxff_ptr = %d , cur_mac_rxff_ptr = %d\n", __func__, psrtpriv->last_mac_rxff_ptr, cur_mac_rxff_ptr); +#endif + + if (psrtpriv->last_mac_rxff_ptr == cur_mac_rxff_ptr) { + psrtpriv->rx_cnt++; +#if 0 + RTW_INFO("%s,MAC case rx_cnt=%d\n", __func__, psrtpriv->rx_cnt); +#endif + goto exit; + } + + psrtpriv->rx_cnt = 0; + +exit: + + psrtpriv->last_mac_rxff_ptr = cur_mac_rxff_ptr; + + if (psrtpriv->rx_cnt > 3) { + psrtpriv->self_dect_case = 2; + psrtpriv->self_dect_rx_cnt++; + rtw_hal_sreset_reset(p); + } +} + static void linked_status_check(PADAPTER p) { PHAL_DATA_TYPE hal = GET_HAL_DATA(p); struct sreset_priv *psrtpriv = &hal->srestpriv; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(p); u32 rx_dma_status = 0; rx_dma_status = rtw_read32(p, REG_RXDMA_STATUS_8822B); - if (rx_dma_status != 0x00) + if (rx_dma_status != 0x00) { RTW_INFO("%s REG_RXDMA_STATUS:0x%08x\n", __FUNCTION__, rx_dma_status); + psrtpriv->rx_dma_status_cnt++; + psrtpriv->self_dect_case = 5; +#ifdef CONFIG_USB_HCI + rtw_hal_sreset_reset(p); +#endif /* CONFIG_USB_HCI */ + } + + if (psrtpriv->self_dect_fw) { + psrtpriv->self_dect_case = 3; +#ifdef CONFIG_USB_HCI + rtw_hal_sreset_reset(p); +#endif /* CONFIG_USB_HCI */ + } + +#ifdef CONFIG_USB_HCI + check_rx_count(p); +#endif /* CONFIG_USB_HCI */ if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) { psrtpriv->dbg_trigger_point = SRESET_TGP_NULL; @@ -880,6 +958,7 @@ static void linked_status_check(PADAPTER p) return; } } +#endif /* DBG_CONFIG_ERROR_DETECT */ static void set_opmode_monitor(PADAPTER adapter) { @@ -896,12 +975,12 @@ static void set_opmode_monitor(PADAPTER adapter) /* Append FCS */ rcr_bits |= BIT_APP_FCS_8822B; + rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&GET_HAL_DATA(adapter)->rcr_backup); + rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_bits); + /* Receive all data frames */ value_rxfltmap2 = 0xFFFF; - - rtl8822b_rcr_config(adapter, rcr_bits); - - rtw_write16(adapter, REG_RXFLTMAP_8822B, value_rxfltmap2); + rtw_write16(adapter, REG_RXFLTMAP2_8822B, value_rxfltmap2); } static void hw_port0_tsf_sync_sel(_adapter *adapter, u8 hw_port, u8 benable, u16 tr_offset) @@ -909,9 +988,19 @@ static void hw_port0_tsf_sync_sel(_adapter *adapter, u8 hw_port, u8 benable, u16 u8 val8, client_port_num = 0; /* check if port0 is already synced */ - if (adapter->tsf.sync_port != MAX_HW_PORT) + if (benable && adapter->tsf.sync_port != MAX_HW_PORT) { + RTW_WARN(FUNC_ADPT_FMT ": port0 already enable TSF sync(%d)\n", + FUNC_ADPT_ARG(adapter), adapter->tsf.sync_port); return; + } + /* check if port0 already disable sync */ + if (!benable && adapter->tsf.sync_port == MAX_HW_PORT) { + RTW_WARN(FUNC_ADPT_FMT ": port0 already disable TSF sync\n", FUNC_ADPT_ARG(adapter)); + return; + } + + /* check if port0 sync from port0 */ if (benable && hw_port == HW_PORT0) { RTW_ERR(FUNC_ADPT_FMT ": hw_port is port0 under enable\n", FUNC_ADPT_ARG(adapter)); rtw_warn_on(1); @@ -943,9 +1032,9 @@ static void hw_port0_tsf_sync_sel(_adapter *adapter, u8 hw_port, u8 benable, u16 rtw_write16(adapter, REG_TSFTR_SYN_OFFSET_8822B, tr_offset); - /* auto sycn for every TBTT */ + /* auto sync for every TBTT */ val8 = rtw_read8(adapter, REG_MISC_CTRL_8822B); - val8 |= BIT6; + val8 |= BIT_AUTO_SYNC_BY_TBTT_8822B; rtw_write8(adapter, REG_MISC_CTRL_8822B, val8); /*0x5B4 [6:4] :SYNC_CLI_SEL - The selector for the CLINT port of sync tsft source for port 0*/ @@ -955,9 +1044,16 @@ static void hw_port0_tsf_sync_sel(_adapter *adapter, u8 hw_port, u8 benable, u16 if (benable) { val8 &= 0x8F; val8 |= (BIT(6) | (client_port_num << 4)); - } else + + adapter->tsf.sync_port = hw_port; + adapter->tsf.offset = tr_offset; + } else { val8 &= ~BIT(6); + adapter->tsf.sync_port = MAX_HW_PORT; + adapter->tsf.offset = 0; + } + rtw_write8(adapter, REG_TIMER0_SRC_SEL_8822B, val8); /* restart port0 bcn funtion */ @@ -966,15 +1062,16 @@ static void hw_port0_tsf_sync_sel(_adapter *adapter, u8 hw_port, u8 benable, u16 static void set_opmode_port0(PADAPTER adapter, u8 mode) { - u8 is_ap_exist; + u8 is_tx_bcn; u8 val8; + u16 val16; u32 val32; #ifdef CONFIG_CONCURRENT_MODE - is_ap_exist = rtw_mi_check_status(adapter, MI_AP_MODE); + is_tx_bcn = rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter); #else /* !CONFIG_CONCURRENT_MODE */ - is_ap_exist = _FALSE; + is_tx_bcn = 0; #endif /* !CONFIG_CONCURRENT_MODE */ /* disable Port0 TSF update */ @@ -990,7 +1087,7 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) switch (mode) { case _HW_STATE_NOLINK_: case _HW_STATE_STATION_: - if (_FALSE == is_ap_exist) { + if (!is_tx_bcn) { StopTxBeacon(adapter); #ifdef CONFIG_PCI_HCI UpdateInterruptMask8822BE(adapter, 0, 0, RT_BCN_INT_MASKS, 0); @@ -1005,18 +1102,12 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) val8 = rtw_read8(adapter, REG_DIS_ATIM_8822B); val8 |= BIT_DIS_ATIM_ROOT_8822B; rtw_write8(adapter, REG_DIS_ATIM_8822B, val8); - - /* clear rx ctrl frame */ - rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0); break; case _HW_STATE_ADHOC_: ResumeTxBeacon(adapter); val8 = BIT_DIS_TSF_UDT_8822B | BIT_EN_BCN_FUNCTION_8822B; rtw_write8(adapter, REG_BCN_CTRL_8822B, val8); - - /* clear rx ctrl frame */ - rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0); break; case _HW_STATE_AP_: @@ -1059,18 +1150,13 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) */ rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01); - /* Set RCR */ - /* CBSSID_DATA must set to 0, reject ICV_ERR packet */ - if (adapter->registrypriv.wifi_spec) - /* for 11n Logo 4.2.31/4.2.32, disable BSSID BCN check for AP mode */ - rtl8822b_rcr_clear(adapter, BIT_CBSSID_DATA_8822B | BIT_CBSSID_BCN_8822B); - else - rtl8822b_rcr_clear(adapter, BIT_CBSSID_DATA_8822B); - /* enable to rx data frame */ - rtw_write16(adapter, REG_RXFLTMAP_8822B, 0xFFFF); + rtw_write16(adapter, REG_RXFLTMAP2_8822B, 0xFFFF); + /* enable to rx ps-poll */ - rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0x0400); + val16 = rtw_read16(adapter, REG_RXFLTMAP1_8822B); + val16 |= BIT_CTRLFLT10EN_8822B; + rtw_write16(adapter, REG_RXFLTMAP1_8822B, val16); /* Beacon Control related register for first time */ rtw_write8(adapter, REG_BCNDMATIM_8822B, 0x02); /* 2ms */ @@ -1079,15 +1165,6 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) rtw_write16(adapter, REG_BCNTCFG_8822B, 0x00); - /* setup time:128 us */ - rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B, 0x04); - - /*TBTT hold time :4ms 0x540[19:8]*/ - rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 1, - TBTT_PROBIHIT_HOLD_TIME & 0xFF); - rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 2, - (rtw_read8(adapter, REG_TBTT_PROHIBIT_8822B + 2) & 0xF0) | (TBTT_PROBIHIT_HOLD_TIME >> 8)); - rtw_write16(adapter, REG_TSFTR_SYN_OFFSET_8822B, 0x7fff); /* +32767 (~32ms) */ /* reset TSF */ @@ -1130,11 +1207,10 @@ static void set_opmode_port0(PADAPTER adapter, u8 mode) static void set_opmode_port1(PADAPTER adapter, u8 mode) { #ifdef CONFIG_CONCURRENT_MODE - u8 is_ap_exist; + u8 is_tx_bcn; u8 val8; - - is_ap_exist = rtw_mi_check_status(adapter, MI_AP_MODE); + is_tx_bcn = rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter); /* disable Port1 TSF update */ val8 = rtw_read8(adapter, REG_BCN_CTRL_CLINT0_8822B); @@ -1149,7 +1225,7 @@ static void set_opmode_port1(PADAPTER adapter, u8 mode) switch (mode) { case _HW_STATE_NOLINK_: case _HW_STATE_STATION_: - if (_FALSE == is_ap_exist) { + if (!is_tx_bcn) { StopTxBeacon(adapter); #ifdef CONFIG_PCI_HCI UpdateInterruptMask8822BE(adapter, 0, 0, RT_BCN_INT_MASKS, 0); @@ -1159,18 +1235,12 @@ static void set_opmode_port1(PADAPTER adapter, u8 mode) /* disable beacon function */ val8 = BIT_CLI0_DIS_TSF_UDT_8822B | BIT_CLI0_EN_BCN_FUNCTION_8822B; rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822B, val8); - - /* clear rx ctrl frame */ - rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0); break; case _HW_STATE_ADHOC_: ResumeTxBeacon(adapter); val8 = BIT_CLI0_DIS_TSF_UDT_8822B | BIT_CLI0_EN_BCN_FUNCTION_8822B; rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822B, val8); - - /* clear rx ctrl frame */ - rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0); break; case _HW_STATE_AP_: @@ -1191,20 +1261,9 @@ static void hw_var_set_opmode(PADAPTER adapter, u8 mode) if (isMonitor == _TRUE) { - u32 rcr; - /* reset RCR */ - rcr = BIT_APM_8822B - | BIT_AM_8822B - | BIT_AB_8822B - | BIT_CBSSID_DATA_8822B - | BIT_CBSSID_BCN_8822B - | BIT_HTC_LOC_CTRL_8822B - | BIT_VHT_DACK_8822B - | BIT_APP_PHYSTS_8822B - | BIT_APP_ICV_8822B - | BIT_APP_MIC_8822B - ; - rtl8822b_rcr_config(adapter, rcr); + /* reset RCR from backup */ + rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&GET_HAL_DATA(adapter)->rcr_backup); + rtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE); isMonitor = _FALSE; } @@ -1217,8 +1276,8 @@ static void hw_var_set_opmode(PADAPTER adapter, u8 mode) } /* clear crc bit */ - if (rtl8822b_rcr_check(adapter, BIT_ACRC32_8822B)) - rtl8822b_rcr_clear(adapter, BIT_ACRC32_8822B); + if (rtw_hal_rcr_check(adapter, BIT_ACRC32_8822B)) + rtw_hal_rcr_clear(adapter, BIT_ACRC32_8822B); switch (adapter->hw_port) { case HW_PORT0: @@ -1234,24 +1293,6 @@ static void hw_var_set_opmode(PADAPTER adapter, u8 mode) } } -static void hw_var_set_macaddr(PADAPTER adapter, u8 *val) -{ - u8 port; - - - port = adapter->hw_port; - rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), port, val); -} - -static void hw_var_set_bssid(PADAPTER adapter, u8 *val) -{ - u8 port; - - - port = adapter->hw_port; - rtw_halmac_set_bssid(adapter_to_dvobj(adapter), port, val); -} - static void hw_var_set_basic_rate(PADAPTER adapter, u8 *ratetbl) { #define RATE_1M BIT(0) @@ -1321,6 +1362,14 @@ static void hw_var_set_basic_rate(PADAPTER adapter, u8 *ratetbl) val32 = rtw_write32(adapter, REG_RRSR_8822B, val32); } +static void hw_var_hw_port_cfg(_adapter *adapter, u8 enable) +{ + if (enable) + hw_bcn_ctrl_set(adapter, (BIT_P0_EN_RXBCN_RPT | BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION)); + else + hw_bcn_ctrl_clr(adapter, BIT_EN_BCN_FUNCTION_8822B); +} + static void hw_var_set_bcn_func(PADAPTER adapter, u8 enable) { u8 val8 = 0; @@ -1424,7 +1473,8 @@ static void hw_var_set_correct_tsf(PADAPTER adapter) #ifdef CONFIG_CONCURRENT_MODE /* Update buddy port's TSF if it is SoftAP for beacon TX issue!*/ if (((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) - && (rtw_mi_check_status(adapter, MI_AP_MODE) == _TRUE)) { + && (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) + ) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); u32 i; PADAPTER iface; @@ -1436,8 +1486,8 @@ static void hw_var_set_correct_tsf(PADAPTER adapter) if (iface == adapter) continue; - if ((check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE) - && (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE)) + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) + && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) hw_port0_tsf_sync_sel(iface, adapter->hw_port, _TRUE, 50);/* the offset = 50ms.*/ } } else if (((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) @@ -1452,20 +1502,6 @@ static void hw_var_set_correct_tsf(PADAPTER adapter) #endif /* !CONFIG_MI_WITH_MBSSID_CAM */ } -static void hw_var_set_check_bssid(PADAPTER adapter, u8 enable) -{ - u32 rcr; - - rcr = BIT_CBSSID_DATA_8822B | BIT_CBSSID_BCN_8822B; - if (enable) - rtl8822b_rcr_add(adapter, rcr); - else - rtl8822b_rcr_clear(adapter, rcr); - - RTW_INFO("%s: [HW_VAR_CHECK_BSSID] 0x%x=0x%x\n", __FUNCTION__, - REG_RCR_8822B, rtw_read32(adapter, REG_RCR_8822B)); -} - static void hw_var_set_mlme_disconnect(PADAPTER adapter) { u8 val8; @@ -1475,7 +1511,7 @@ static void hw_var_set_mlme_disconnect(PADAPTER adapter) if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE) #endif /* reject all data frames under not link state */ - rtw_write16(adapter, REG_RXFLTMAP_8822B, 0); + rtw_write16(adapter, REG_RXFLTMAP2_8822B, 0); #ifdef CONFIG_CONCURRENT_MODE if (adapter->hw_port == HW_PORT1) { @@ -1516,7 +1552,7 @@ static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable) PHAL_DATA_TYPE hal; struct mlme_priv *pmlmepriv; PADAPTER iface; - u32 rcr_bit, reg_bcn_ctl; + u32 reg_bcn_ctl; u16 value_rxfltmap2; u8 val8, i; @@ -1526,24 +1562,12 @@ static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable) pmlmepriv = &adapter->mlmepriv; #ifdef CONFIG_FIND_BEST_CHANNEL - rcr_bit = BIT_CBSSID_BCN_8822B | BIT_CBSSID_DATA_8822B; - /* Receive all data frames */ value_rxfltmap2 = 0xFFFF; -#else /* CONFIG_FIND_BEST_CHANNEL */ - rcr_bit = BIT_CBSSID_BCN_8822B; - - /* config RCR to receive different BSSID & not to receive data frame */ +#else + /* not to receive data frame */ value_rxfltmap2 = 0; -#endif /* CONFIG_FIND_BEST_CHANNEL */ - - if (rtw_mi_check_fwstate(adapter, WIFI_AP_STATE)) - rcr_bit = BIT_CBSSID_BCN_8822B; -#ifdef CONFIG_TDLS - /* TDLS will clear RCR_CBSSID_DATA bit for connection. */ - else if (adapter->tdlsinfo.link_established == _TRUE) - rcr_bit = BIT_CBSSID_BCN_8822B; -#endif /* CONFIG_TDLS */ +#endif if (enable) { /* @@ -1551,14 +1575,14 @@ static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable) * 2. config RCR to receive different BSSID BCN or probe rsp */ - rtw_write16(adapter, REG_RXFLTMAP_8822B, value_rxfltmap2); + rtw_write16(adapter, REG_RXFLTMAP2_8822B, value_rxfltmap2); - rtl8822b_rcr_clear(adapter, rcr_bit); + rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_ENTER); /* Save orignal RRSR setting. */ hal->RegRRSR = rtw_read16(adapter, REG_RRSR_8822B); - if (rtw_mi_check_status(adapter, MI_AP_MODE)) + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) StopTxBeacon(adapter); } else { /* sitesurvey done @@ -1566,25 +1590,16 @@ static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable) * 2. config RCR not to receive different BSSID BCN or probe rsp */ - if (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE)) + if (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE)) /* enable to rx data frame */ - rtw_write16(adapter, REG_RXFLTMAP_8822B, 0xFFFF); - -#ifdef CONFIG_MI_WITH_MBSSID_CAM - rtl8822b_rcr_clear(adapter, BIT_CBSSID_BCN_8822B | BIT_CBSSID_DATA_8822B); -#else /* CONFIG_MI_WITH_MBSSID_CAM */ + rtw_write16(adapter, REG_RXFLTMAP2_8822B, 0xFFFF); - /* for 11n Logo 4.2.31/4.2.32, disable BSSID BCN check for AP mode */ - if (adapter->registrypriv.wifi_spec && MLME_IS_AP(adapter)) - rcr_bit &= ~(BIT_CBSSID_BCN_8822B); - - rtl8822b_rcr_add(adapter, rcr_bit); -#endif /* CONFIG_MI_WITH_MBSSID_CAM */ + rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_DONE); /* Restore orignal RRSR setting. */ rtw_write16(adapter, REG_RRSR_8822B, hal->RegRRSR); - if (rtw_mi_check_status(adapter, MI_AP_MODE)) { + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) { ResumeTxBeacon(adapter); rtw_mi_tx_beacon_hdl(adapter); } @@ -1600,7 +1615,7 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) PHAL_DATA_TYPE hal; struct mlme_priv *pmlmepriv; - RetryLimit = 0x30; + RetryLimit = RL_VAL_STA; hal = GET_HAL_DATA(adapter); pmlmepriv = &adapter->mlmepriv; @@ -1608,27 +1623,16 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) #ifdef CONFIG_CONCURRENT_MODE if (type == 0) { /* prepare to join */ - if (rtw_mi_check_status(adapter, MI_AP_MODE)) + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) StopTxBeacon(adapter); /* enable to rx data frame.Accept all data frame */ - rtw_write16(adapter, REG_RXFLTMAP_8822B, 0xFFFF); - -#ifdef CONFIG_MI_WITH_MBSSID_CAM - val32 = BIT_CBSSID_DATA_8822B | BIT_CBSSID_BCN_8822B; - rtl8822b_rcr_clear(adapter, val32); -#else /* !CONFIG_MI_WITH_MBSSID_CAM */ - if (rtw_mi_check_status(adapter, MI_AP_MODE)) - val32 = BIT_CBSSID_BCN_8822B; - else - val32 = BIT_CBSSID_DATA_8822B | BIT_CBSSID_BCN_8822B; - rtl8822b_rcr_add(adapter, val32); -#endif /* !CONFIG_MI_WITH_MBSSID_CAM */ + rtw_write16(adapter, REG_RXFLTMAP2_8822B, 0xFFFF); if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) - RetryLimit = (hal->CustomerID == RT_CID_CCX) ? 7 : 48; + RetryLimit = (hal->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA; else /* Ad-hoc Mode */ - RetryLimit = 0x7; + RetryLimit = RL_VAL_AP; /* * for 8822B, must enable BCN function if BIT_CBSSID_BCN_8822B(bit 7) of REG_RCR(0x608) is enable to recv BSSID bcn @@ -1640,9 +1644,9 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) } else if (type == 1) { /* joinbss_event call back when join res < 0 */ if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE) - rtw_write16(adapter, REG_RXFLTMAP_8822B, 0x00); + rtw_write16(adapter, REG_RXFLTMAP2_8822B, 0x00); - if (rtw_mi_check_status(adapter, MI_AP_MODE)) { + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) { ResumeTxBeacon(adapter); /* reset TSF 1/2 after resume_tx_beacon */ @@ -1668,10 +1672,10 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { rtw_write8(adapter, 0x542, 0x02); - RetryLimit = 0x7; + RetryLimit = RL_VAL_AP; } - if (rtw_mi_check_status(adapter, MI_AP_MODE)) { + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) { ResumeTxBeacon(adapter); /* reset TSF 1/2 after resume_tx_beacon */ @@ -1686,9 +1690,7 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) /* prepare to join */ /* enable to rx data frame. Accept all data frame */ - rtw_write16(adapter, REG_RXFLTMAP_8822B, 0xFFFF); - - hw_var_set_check_bssid(adapter, !adapter->in_cta_test); + rtw_write16(adapter, REG_RXFLTMAP2_8822B, 0xFFFF); /* * for 8822B, must enable BCN function if BIT_CBSSID_BCN_8822B(bit 7) of REG_RCR(0x608) is enabled to recv BSSID bcn @@ -1699,12 +1701,12 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) rtl8822b_rx_tsf_addr_filter_config(adapter, BIT_CHK_TSF_EN_8822B | BIT_CHK_TSF_CBSSID_8822B); if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) - RetryLimit = (hal->CustomerID == RT_CID_CCX) ? 7 : 48; + RetryLimit = (hal->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA; else /* Ad-hoc Mode */ - RetryLimit = 0x7; + RetryLimit = RL_VAL_AP; } else if (type == 1) { /* joinbss_event call back when join res < 0 */ - rtw_write16(adapter, REG_RXFLTMAP_8822B, 0x00); + rtw_write16(adapter, REG_RXFLTMAP2_8822B, 0x00); } else if (type == 2) { /* sta add event callback */ @@ -1714,7 +1716,7 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) rtw_write8(adapter, REG_BCN_CTRL_8822B, val8); if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) - RetryLimit = 0x7; + RetryLimit = RL_VAL_AP; } val16 = BIT_LRL_8822B(RetryLimit) | BIT_SRL_8822B(RetryLimit); @@ -1749,42 +1751,6 @@ static void hw_var_set_acm_ctrl(PADAPTER adapter, u8 ctrl) rtw_write8(adapter, REG_ACMHWCTRL_8822B, hwctrl); } -static void hw_var_set_rcr_am(PADAPTER adapter, u8 enable) -{ - u32 rcr; - - rcr = BIT_AM_8822B; - if (enable) - rtl8822b_rcr_add(adapter, rcr); - else - rtl8822b_rcr_clear(adapter, rcr); - - RTW_INFO("%s: [HW_VAR_ON_RCR_AM] RCR(0x%x)=0x%x\n", - __FUNCTION__, REG_RCR_8822B, rtw_read32(adapter, REG_RCR_8822B)); -} - -static void hw_var_set_bcn_interval(PADAPTER adapter, u16 bcn_interval) -{ - u16 val16 = 0; - -#ifdef CONFIG_CONCURRENT_MODE - if (adapter->hw_port == HW_PORT1) { - /* Port 1(clint 0) */ - val16 = rtw_read16(adapter, (REG_MBSSID_BCN_SPACE_8822B + 2)); - val16 &= (~BIT_MASK_BCN_SPACE_CLINT0_8822B); - val16 |= (bcn_interval & BIT_MASK_BCN_SPACE_CLINT0_8822B); - rtw_write16(adapter, REG_MBSSID_BCN_SPACE_8822B + 2, val16); - } else -#endif - { - /* Port 0 */ - rtw_write16(adapter, REG_MBSSID_BCN_SPACE_8822B, bcn_interval); - } - - RTW_INFO("%s: [HW_VAR_BEACON_INTERVAL] 0x%x=0x%x\n", __FUNCTION__, - REG_MBSSID_BCN_SPACE_8822B, rtw_read32(adapter, REG_MBSSID_BCN_SPACE_8822B)); -} - static void hw_var_set_sec_dk_cfg(PADAPTER adapter, u8 enable) { struct security_priv *sec = &adapter->securitypriv; @@ -1970,18 +1936,6 @@ static void hw_var_set_h2c_fw_joinbssrpt(PADAPTER adapter, u8 mstatus) hw_var_set_dl_rsvd_page(adapter, RT_MEDIA_CONNECT); } -/* - * Description: Get the reserved page number in Tx packet buffer. - * Retrun value: the page number. - */ -u8 get_txbuffer_rsvdpagenum(PADAPTER adapter, bool wowlan) -{ - u8 RsvdPageNum = HALMAC_RSVD_DRV_PGNUM_8822B; - - - return RsvdPageNum; -} - /* * Parameters: * adapter @@ -2041,17 +1995,16 @@ static void hw_port_reconfig(_adapter * if_ap, _adapter *if_port0) /*reconfigure*/ if_port0->hw_port = port; /* adapter mac addr switch to port mac addr */ - hw_var_set_macaddr(if_port0, adapter_mac_addr(if_port0)); + rtw_hal_set_hwreg(if_port0, HW_VAR_MAC_ADDR, adapter_mac_addr(if_port0)); Set_MSR(if_port0, vnet_type); rtw_write8(if_port0, port_cfg[if_port0->hw_port].bcn_ctl, vbcn_ctrl); if (is_client_associated_to_ap(if_port0)) - hw_var_set_bssid(if_port0, bssid); + rtw_hal_set_hwreg(if_port0, HW_VAR_BSSID, bssid); if_ap->hw_port =HW_PORT0; /* port mac addr switch to adapter mac addr */ - hw_var_set_macaddr(if_ap, adapter_mac_addr(if_ap)); - + rtw_hal_set_hwreg(if_ap, HW_VAR_MAC_ADDR, adapter_mac_addr(if_ap)); } static void hw_var_ap_port_switch(_adapter *adapter, u8 mode) @@ -2106,9 +2059,10 @@ static void hw_var_ap_port_switch(_adapter *adapter, u8 mode) } #endif -void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) +u8 rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + u8 ret = _SUCCESS; u8 val8; u16 val16; u32 val32; @@ -2122,14 +2076,6 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_SET_OPMODE: hw_var_set_opmode(adapter, *val); break; - - case HW_VAR_MAC_ADDR: - hw_var_set_macaddr(adapter, val); - break; - - case HW_VAR_BSSID: - hw_var_set_bssid(adapter, val); - break; /* case HW_VAR_INIT_RTS_RATE: break; @@ -2146,12 +2092,12 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) hw_var_set_bcn_func(adapter, *val); break; - case HW_VAR_CORRECT_TSF: - hw_var_set_correct_tsf(adapter); + case HW_VAR_PORT_CFG: + hw_var_hw_port_cfg(adapter, *val); break; - case HW_VAR_CHECK_BSSID: - hw_var_set_check_bssid(adapter, *val); + case HW_VAR_CORRECT_TSF: + hw_var_set_correct_tsf(adapter); break; case HW_VAR_MLME_DISCONNECT: @@ -2190,16 +2136,31 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) #endif /* CONFIG_BT_COEXIST */ break; - case HW_VAR_ON_RCR_AM: - hw_var_set_rcr_am(adapter, 1); - break; - - case HW_VAR_OFF_RCR_AM: - hw_var_set_rcr_am(adapter, 0); + case HW_VAR_RCR: + ret = rtl8822b_rcr_config(adapter, *((u32 *)val)); break; case HW_VAR_BEACON_INTERVAL: - hw_var_set_bcn_interval(adapter, *(u16 *)val); + { + u16 bcn_interval = *((u16 *)val); + + #ifdef CONFIG_SWTIMER_BASED_TXBCN + bcn_interval = rtw_hal_bcn_interval_adjust(adapter, bcn_interval); + #endif + + SetHwReg(adapter, HW_VAR_BEACON_INTERVAL, (u8 *)&bcn_interval); + #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + { + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + RTW_INFO("%s==> bcn_interval:%d, eraly_int:%d\n", __func__, bcn_interval, bcn_interval >> 1); + rtw_write8(adapter, REG_DRVERLYINT, bcn_interval >> 1); + } + } + #endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ + } break; case HW_VAR_SLOT_TIME: @@ -2370,11 +2331,10 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_CHECK_TXBUF: { u16 rtylmtorg; u8 RetryLimit = 0x01; - u32 start, passtime; + systime start; + u32 passtime; u32 timelmt = 2000; /* ms */ - u32 waittime = 10; /* ms */ - u32 high, low, normal, extra, publc; - u16 rsvd, available; + int err; u8 empty; @@ -2385,85 +2345,32 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) /* Check TX FIFO empty or not */ empty = _FALSE; - high = 0; - low = 0; - normal = 0; - extra = 0; - publc = 0; start = rtw_get_current_time(); - while ((rtw_get_passing_time_ms(start) < timelmt) - && !RTW_CANNOT_RUN(adapter)) { - high = rtw_read32(adapter, REG_FIFOPAGE_INFO_1_8822B); - low = rtw_read32(adapter, REG_FIFOPAGE_INFO_2_8822B); - normal = rtw_read32(adapter, REG_FIFOPAGE_INFO_3_8822B); - extra = rtw_read32(adapter, REG_FIFOPAGE_INFO_4_8822B); - publc = rtw_read32(adapter, REG_FIFOPAGE_INFO_5_8822B); - - rsvd = BIT_GET_HPQ_V1_8822B(high); - available = BIT_GET_HPQ_AVAL_PG_V1_8822B(high); - if (rsvd != available) { - rtw_msleep_os(waittime); - continue; - } - - rsvd = BIT_GET_LPQ_V1_8822B(low); - available = BIT_GET_LPQ_AVAL_PG_V1_8822B(low); - if (rsvd != available) { - rtw_msleep_os(waittime); - continue; - } - - rsvd = BIT_GET_NPQ_V1_8822B(normal); - available = BIT_GET_NPQ_AVAL_PG_V1_8822B(normal); - if (rsvd != available) { - rtw_msleep_os(waittime); - continue; - } - - rsvd = BIT_GET_EXQ_V1_8822B(extra); - available = BIT_GET_EXQ_AVAL_PG_V1_8822B(extra); - if (rsvd != available) { - rtw_msleep_os(waittime); - continue; - } - - rsvd = BIT_GET_PUBQ_V1_8822B(publc); - available = BIT_GET_PUBQ_AVAL_PG_V1_8822B(publc); - if (rsvd != available) { - rtw_msleep_os(waittime); - continue; - } - + err = rtw_halmac_txfifo_wait_empty(adapter_to_dvobj(adapter), timelmt); + if (!err) empty = _TRUE; - break; - } - passtime = rtw_get_passing_time_ms(start); + if (_TRUE == empty) RTW_INFO("[HW_VAR_CHECK_TXBUF] Empty in %d ms\n", passtime); else if (RTW_CANNOT_RUN(adapter)) - RTW_INFO("[HW_VAR_CHECK_TXBUF] bDriverStopped or bSurpriseRemoved\n"); + RTW_WARN("[HW_VAR_CHECK_TXBUF] bDriverStopped or bSurpriseRemoved\n"); else { - RTW_PRINT("[HW_VAR_CHECK_TXBUF] NOT empty in %d ms\n", passtime); - RTW_PRINT("[HW_VAR_CHECK_TXBUF] 0x230=0x%08x 0x234=0x%08x 0x238=0x%08x 0x23c=0x%08x 0x240=0x%08x\n", - high, low, normal, extra, publc); - } + RTW_ERR("[HW_VAR_CHECK_TXBUF] NOT empty in %d ms\n", passtime); + } rtw_write16(adapter, REG_RETRY_LIMIT_8822B, rtylmtorg); } break; /* case HW_VAR_PCIE_STOP_TX_DMA: - break; -*/ - -/* + case HW_VAR_APFM_ON_MAC case HW_VAR_HCI_SUS_STATE: #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) case HW_VAR_WOWLAN: case HW_VAR_WAKEUP_REASON: - case HW_VAR_RPWM_TOG: #endif + case HW_VAR_RPWM_TOG: break; */ #ifdef CONFIG_GPIO_WAKEUP @@ -2545,9 +2452,6 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) hal->bNeedIQK = _FALSE; break; - case HW_VAR_DM_IN_LPS: - rtl8822b_phy_haldm_in_lps(adapter); - break; /* case HW_VAR_SET_REQ_FW_PS: case HW_VAR_FW_PS_STATE: @@ -2597,76 +2501,6 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) /* case HW_VAR_MACID_LINK: case HW_VAR_MACID_NOLINK: - break; -*/ - case HW_VAR_MACID_SLEEP: { - u32 reg_macid_sleep; - u8 bit_shift; - u8 id = *(u8 *)val; - - if (id < 32) { - reg_macid_sleep = REG_MACID_SLEEP_8822B; - bit_shift = id; - } else if (id < 64) { - reg_macid_sleep = REG_MACID_SLEEP1_8822B; - bit_shift = id - 32; - } else if (id < 96) { - reg_macid_sleep = REG_MACID_SLEEP2_8822B; - bit_shift = id - 64; - } else if (id < 128) { - reg_macid_sleep = REG_MACID_SLEEP3_8822B; - bit_shift = id - 96; - } else { - rtw_warn_on(1); - break; - } - - val32 = rtw_read32(adapter, reg_macid_sleep); - RTW_INFO(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] macid=%d, org reg_0x%03x=0x%08X\n", - FUNC_ADPT_ARG(adapter), id, reg_macid_sleep, val32); - - if (val32 & BIT(bit_shift)) - break; - - val32 |= BIT(bit_shift); - rtw_write32(adapter, reg_macid_sleep, val32); - } - break; - - case HW_VAR_MACID_WAKEUP: { - u32 reg_macid_sleep; - u8 bit_shift; - u8 id = *(u8 *)val; - - if (id < 32) { - reg_macid_sleep = REG_MACID_SLEEP_8822B; - bit_shift = id; - } else if (id < 64) { - reg_macid_sleep = REG_MACID_SLEEP1_8822B; - bit_shift = id - 32; - } else if (id < 96) { - reg_macid_sleep = REG_MACID_SLEEP2_8822B; - bit_shift = id - 64; - } else if (id < 128) { - reg_macid_sleep = REG_MACID_SLEEP3_8822B; - bit_shift = id - 96; - } else { - rtw_warn_on(1); - break; - } - - val32 = rtw_read32(adapter, reg_macid_sleep); - RTW_INFO(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] macid=%d, org reg_0x%03x=0x%08X\n", - FUNC_ADPT_ARG(adapter), id, reg_macid_sleep, val32); - - if (!(val32 & BIT(bit_shift))) - break; - - val32 &= ~BIT(bit_shift); - rtw_write32(adapter, reg_macid_sleep, val32); - } - break; -/* case HW_VAR_DUMP_MAC_QUEUE_INFO: case HW_VAR_ASIX_IOT: #ifdef CONFIG_MBSSID_CAM @@ -2681,50 +2515,90 @@ void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val) break; */ #ifdef CONFIG_TDLS - case HW_VAR_TDLS_WRCR: - rtl8822b_rcr_clear(adapter, BIT_CBSSID_DATA_8822B); - break; - - case HW_VAR_TDLS_RS_RCR: - rtl8822b_rcr_add(adapter, BIT_CBSSID_DATA_8822B); - break; -/* #ifdef CONFIG_TDLS_CH_SW case HW_VAR_TDLS_BCN_EARLY_C2H_RPT: + rtl8822b_set_BcnEarly_C2H_Rpt_cmd(adapter, *val); break; #endif -*/ #endif + case HW_VAR_FREECNT: + + val8 = (u8)*val; + + if (val8==0) { + /* disable free run counter set 0x577[3]=0 */ + rtw_write8(adapter, REG_MISC_CTRL, + rtw_read8(adapter, REG_MISC_CTRL)&(~BIT_EN_FREECNT)); + + /* reset FREE_RUN_COUNTER set 0x553[5]=1 */ + val8 = rtw_read8(adapter, REG_DUAL_TSF_RST); + val8 |= BIT_FREECNT_RST; + rtw_write8(adapter, REG_DUAL_TSF_RST, val8); + + } else if (val8==1){ + + /* enable free run counter */ + + /* disable first set 0x577[3]=0 */ + rtw_write8(adapter, REG_MISC_CTRL, + rtw_read8(adapter, REG_MISC_CTRL)&(~BIT_EN_FREECNT)); + + /* reset FREE_RUN_COUNTER set 0x553[5]=1 */ + val8 = rtw_read8(adapter, REG_DUAL_TSF_RST); + val8 |= BIT_FREECNT_RST; + rtw_write8(adapter, REG_DUAL_TSF_RST, val8); + + /* enable free run counter 0x577[3]=1 */ + rtw_write8(adapter, REG_MISC_CTRL, + rtw_read8(adapter, REG_MISC_CTRL)|BIT_EN_FREECNT); + } + break; + + case HW_VAR_TSF_AUTO_SYNC: + if (*val == _TRUE) + hw_port0_tsf_sync_sel(adapter, adapter->hw_port, _TRUE, 50); + else + hw_port0_tsf_sync_sel(adapter, adapter->hw_port, _FALSE, 50); + break; + + case HW_VAR_SET_SOML_PARAM: +#ifdef CONFIG_DYNAMIC_SOML + rtw_dyn_soml_para_set(adapter, 4, 20, 1, 0); +#endif + break; + default: - SetHwReg(adapter, variable, val); + ret = SetHwReg(adapter, variable, val); break; } + + return ret; } struct qinfo { - u32 head:8; - u32 pkt_num:7; - u32 tail:8; + u32 head:11; + u32 tail:11; + u32 empty:1; u32 ac:2; u32 macid:7; }; struct bcn_qinfo { - u16 head:8; - u16 pkt_num:8; + u16 head:12; + u16 rsvd:4; }; -static void dump_qinfo(void *sel, struct qinfo *info, const char *tag) +static void dump_qinfo(void *sel, struct qinfo *info, u32 pkt_num, const char *tag) { RTW_PRINT_SEL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n", - tag ? tag : "", info->head, info->tail, info->pkt_num, info->macid, info->ac); + tag ? tag : "", info->head, info->tail, pkt_num, info->macid, info->ac); } -static void dump_bcn_qinfo(void *sel, struct bcn_qinfo *info, const char *tag) +static void dump_bcn_qinfo(void *sel, struct bcn_qinfo *info, u32 pkt_num, const char *tag) { RTW_PRINT_SEL(sel, "%shead:0x%02x, pkt_num:%u\n", - tag ? tag : "", info->head, info->pkt_num); + tag ? tag : "", info->head, pkt_num); } static void dump_mac_qinfo(void *sel, _adapter *adapter) @@ -2740,6 +2614,12 @@ static void dump_mac_qinfo(void *sel, _adapter *adapter) u32 mg_q_info; u32 hi_q_info; u16 bcn_q_info; + u32 q0_q1_info; + u32 q2_q3_info; + u32 q4_q5_info; + u32 q6_q7_info; + u32 mg_hi_q_info; + u32 cmd_bcn_q_info; q0_info = rtw_read32(adapter, REG_Q0_INFO_8822B); q1_info = rtw_read32(adapter, REG_Q1_INFO_8822B); @@ -2753,17 +2633,49 @@ static void dump_mac_qinfo(void *sel, _adapter *adapter) hi_q_info = rtw_read32(adapter, REG_HIQ_INFO_8822B); bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO_8822B); - dump_qinfo(sel, (struct qinfo *)&q0_info, "Q0 "); - dump_qinfo(sel, (struct qinfo *)&q1_info, "Q1 "); - dump_qinfo(sel, (struct qinfo *)&q2_info, "Q2 "); - dump_qinfo(sel, (struct qinfo *)&q3_info, "Q3 "); - dump_qinfo(sel, (struct qinfo *)&q4_info, "Q4 "); - dump_qinfo(sel, (struct qinfo *)&q5_info, "Q5 "); - dump_qinfo(sel, (struct qinfo *)&q6_info, "Q6 "); - dump_qinfo(sel, (struct qinfo *)&q7_info, "Q7 "); - dump_qinfo(sel, (struct qinfo *)&mg_q_info, "MG "); - dump_qinfo(sel, (struct qinfo *)&hi_q_info, "HI "); - dump_bcn_qinfo(sel, (struct bcn_qinfo *)&bcn_q_info, "BCN "); + q0_q1_info = rtw_read32(adapter, REG_Q0_Q1_INFO_8822B); + q2_q3_info = rtw_read32(adapter, REG_Q2_Q3_INFO_8822B); + q4_q5_info = rtw_read32(adapter, REG_Q4_Q5_INFO_8822B); + q6_q7_info = rtw_read32(adapter, REG_Q6_Q7_INFO_8822B); + mg_hi_q_info = rtw_read32(adapter, REG_MGQ_HIQ_INFO_8822B); + cmd_bcn_q_info = rtw_read32(adapter, REG_CMDQ_BCNQ_INFO_8822B); + + dump_qinfo(sel, (struct qinfo *)&q0_info, q0_q1_info&0xFFF, "Q0 "); + dump_qinfo(sel, (struct qinfo *)&q1_info, (q0_q1_info>>15)&0xFFF, "Q1 "); + dump_qinfo(sel, (struct qinfo *)&q2_info, q2_q3_info&0xFFF, "Q2 "); + dump_qinfo(sel, (struct qinfo *)&q3_info, (q2_q3_info>>15)&0xFFF, "Q3 "); + dump_qinfo(sel, (struct qinfo *)&q4_info, q4_q5_info&0xFFF, "Q4 "); + dump_qinfo(sel, (struct qinfo *)&q5_info, (q4_q5_info>>15)&0xFFF, "Q5 "); + dump_qinfo(sel, (struct qinfo *)&q6_info, q6_q7_info&0xFFF, "Q6 "); + dump_qinfo(sel, (struct qinfo *)&q7_info, (q6_q7_info>>15)&0xFFF, "Q7 "); + dump_qinfo(sel, (struct qinfo *)&mg_q_info, mg_hi_q_info&0xFFF, "MG "); + dump_qinfo(sel, (struct qinfo *)&hi_q_info, (mg_hi_q_info>>15)&0xFFF, "HI "); + dump_bcn_qinfo(sel, (struct bcn_qinfo *)&bcn_q_info, cmd_bcn_q_info&0xFFF, "BCN "); + +} + +static void dump_mac_txfifo(void *sel, _adapter *adapter) +{ + u32 hpq, lpq, npq, epq, pubq; + + hpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_1_8822B); + lpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_2_8822B); + npq = rtw_read32(adapter, REG_FIFOPAGE_INFO_3_8822B); + epq = rtw_read32(adapter, REG_FIFOPAGE_INFO_4_8822B); + pubq = rtw_read32(adapter, REG_FIFOPAGE_INFO_5_8822B); + + hpq = (hpq & 0xFFF0000)>>16; + lpq = (lpq & 0xFFF0000)>>16; + npq = (npq & 0xFFF0000)>>16; + epq = (epq & 0xFFF0000)>>16; + pubq = (pubq & 0xFFF0000)>>16; + + RTW_PRINT_SEL(sel, "Tx: available page num: "); + if ((hpq == 0xAEA) && (hpq == lpq) && (hpq == pubq)) + RTW_PRINT_SEL(sel, "N/A (reg val = 0xea)\n"); + else + RTW_PRINT_SEL(sel, "HPQ: %d, LPQ: %d, NPQ: %d, EPQ: %d, PUBQ: %d\n" + , hpq, lpq, npq, epq, pubq); } static u8 hw_var_get_bcn_valid(PADAPTER adapter) @@ -2778,12 +2690,55 @@ static u8 hw_var_get_bcn_valid(PADAPTER adapter) return ret; } +void rtl8822b_read_wmmedca_reg(PADAPTER adapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params) +{ + u8 vo_reg_params[4]; + u8 vi_reg_params[4]; + u8 be_reg_params[4]; + u8 bk_reg_params[4]; + + rtl8822b_gethwreg(adapter, HW_VAR_AC_PARAM_VO, vo_reg_params); + rtl8822b_gethwreg(adapter, HW_VAR_AC_PARAM_VI, vi_reg_params); + rtl8822b_gethwreg(adapter, HW_VAR_AC_PARAM_BE, be_reg_params); + rtl8822b_gethwreg(adapter, HW_VAR_AC_PARAM_BK, bk_reg_params); + + vo_params[0] = vo_reg_params[0]; + vo_params[1] = vo_reg_params[1] & 0x0F; + vo_params[2] = (vo_reg_params[1] & 0xF0) >> 4; + vo_params[3] = ((vo_reg_params[3] << 8) | (vo_reg_params[2])) * 32; + + vi_params[0] = vi_reg_params[0]; + vi_params[1] = vi_reg_params[1] & 0x0F; + vi_params[2] = (vi_reg_params[1] & 0xF0) >> 4; + vi_params[3] = ((vi_reg_params[3] << 8) | (vi_reg_params[2])) * 32; + + be_params[0] = be_reg_params[0]; + be_params[1] = be_reg_params[1] & 0x0F; + be_params[2] = (be_reg_params[1] & 0xF0) >> 4; + be_params[3] = ((be_reg_params[3] << 8) | (be_reg_params[2])) * 32; + + bk_params[0] = bk_reg_params[0]; + bk_params[1] = bk_reg_params[1] & 0x0F; + bk_params[2] = (bk_reg_params[1] & 0xF0) >> 4; + bk_params[3] = ((bk_reg_params[3] << 8) | (bk_reg_params[2])) * 32; + + vo_params[1] = (1 << vo_params[1]) - 1; + vo_params[2] = (1 << vo_params[2]) - 1; + vi_params[1] = (1 << vi_params[1]) - 1; + vi_params[2] = (1 << vi_params[2]) - 1; + be_params[1] = (1 << be_params[1]) - 1; + be_params[2] = (1 << be_params[2]) - 1; + bk_params[1] = (1 << bk_params[1]) - 1; + bk_params[2] = (1 << bk_params[2]) - 1; +} + void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) { PHAL_DATA_TYPE hal; u8 val8; u16 val16; u32 val32; + u64 val64; hal = GET_HAL_DATA(adapter); @@ -2792,8 +2747,6 @@ void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) /* case HW_VAR_MEDIA_STATUS: case HW_VAR_SET_OPMODE: - case HW_VAR_MAC_ADDR: - case HW_VAR_BSSID: case HW_VAR_INIT_RTS_RATE: case HW_VAR_BASIC_RATE: break; @@ -2804,12 +2757,9 @@ void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) /* case HW_VAR_BCN_FUNC: case HW_VAR_CORRECT_TSF: - case HW_VAR_CHECK_BSSID: case HW_VAR_MLME_DISCONNECT: case HW_VAR_MLME_SITESURVEY: case HW_VAR_MLME_JOIN: - case HW_VAR_ON_RCR_AM: - case HW_VAR_OFF_RCR_AM: case HW_VAR_BEACON_INTERVAL: case HW_VAR_SLOT_TIME: case HW_VAR_RESP_SIFS: @@ -2823,12 +2773,42 @@ void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) break; /* case HW_VAR_RF_TYPE: + case HW_VAR_FREECNT: case HW_VAR_CAM_EMPTY_ENTRY: case HW_VAR_CAM_INVALID_ALL: +*/ case HW_VAR_AC_PARAM_VO: + val32 = rtw_read32(adapter, REG_EDCA_VO_PARAM); + val[0] = val32 & 0xFF; + val[1] = (val32 >> 8) & 0xFF; + val[2] = (val32 >> 16) & 0xFF; + val[3] = (val32 >> 24) & 0x07; + break; + case HW_VAR_AC_PARAM_VI: + val32 = rtw_read32(adapter, REG_EDCA_VI_PARAM); + val[0] = val32 & 0xFF; + val[1] = (val32 >> 8) & 0xFF; + val[2] = (val32 >> 16) & 0xFF; + val[3] = (val32 >> 24) & 0x07; + break; + case HW_VAR_AC_PARAM_BE: + val32 = rtw_read32(adapter, REG_EDCA_BE_PARAM); + val[0] = val32 & 0xFF; + val[1] = (val32 >> 8) & 0xFF; + val[2] = (val32 >> 16) & 0xFF; + val[3] = (val32 >> 24) & 0x07; + break; + case HW_VAR_AC_PARAM_BK: + val32 = rtw_read32(adapter, REG_EDCA_BK_PARAM); + val[0] = val32 & 0xFF; + val[1] = (val32 >> 8) & 0xFF; + val[2] = (val32 >> 16) & 0xFF; + val[3] = (val32 >> 24) & 0x07; + break; +/* case HW_VAR_ACM_CTRL: case HW_VAR_AMPDU_MIN_SPACE: case HW_VAR_AMPDU_FACTOR: @@ -2851,8 +2831,13 @@ void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) */ *val = _TRUE; } else { - rtl8822b_rcr_get(adapter, &val32); - val32 &= (BIT_UC_MD_EN_8822B | BIT_BC_MD_EN_8822B | BIT_TIM_PARSER_EN_8822B); + rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&val32); + + if (adapter_to_pwrctl(adapter)->wowlan_mode == _TRUE) + val32 &= (BIT_UC_MD_EN_8822B | BIT_BC_MD_EN_8822B); + else + val32 &= (BIT_UC_MD_EN_8822B | BIT_BC_MD_EN_8822B | BIT_TIM_PARSER_EN_8822B); + if (val32) *val = _FALSE; else @@ -2912,6 +2897,10 @@ void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) val16 = rtw_read16(adapter, REG_TXPKT_EMPTY_8822B); *val = (val16 & BIT_HQQ_EMPTY_8822B) ? _TRUE : _FALSE; break; + case HW_VAR_CHK_MGQ_CPU_EMPTY: + val16 = rtw_read16(adapter, REG_TXPKT_EMPTY_8822B); + *val = (val16 & BIT_MGQ_CPU_EMPTY_8822B) ? _TRUE : _FALSE; + break; /* case HW_VAR_DL_BCN_SEL: case HW_VAR_AMPDU_MAX_TIME: @@ -2919,7 +2908,6 @@ void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_USB_MODE: case HW_VAR_PORT_SWITCH: case HW_VAR_DO_IQK: - case HW_VAR_DM_IN_LPS: case HW_VAR_SET_REQ_FW_PS: case HW_VAR_FW_PS_STATE: case HW_VAR_SOUNDING_ENTER: @@ -2935,13 +2923,15 @@ void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_DL_RSVD_PAGE: case HW_VAR_MACID_LINK: case HW_VAR_MACID_NOLINK: - case HW_VAR_MACID_SLEEP: - case HW_VAR_MACID_WAKEUP: break; */ case HW_VAR_DUMP_MAC_QUEUE_INFO: dump_mac_qinfo(val, adapter); break; + + case HW_VAR_DUMP_MAC_TXFIFO: + dump_mac_txfifo(val, adapter); + break; /* case HW_VAR_ASIX_IOT: #ifdef CONFIG_MBSSID_CAM @@ -2954,14 +2944,28 @@ void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_CH_SW_IQK_INFO_BACKUP: case HW_VAR_CH_SW_IQK_INFO_RESTORE: #ifdef CONFIG_TDLS - case HW_VAR_TDLS_WRCR: - case HW_VAR_TDLS_RS_RCR: #ifdef CONFIG_TDLS_CH_SW case HW_VAR_TDLS_BCN_EARLY_C2H_RPT: #endif #endif break; */ + case HW_VAR_TSF: + /* select TSF by port 0x554[30:28]=port */ + val32 = rtw_read32(adapter, REG_MBSSID_BCN_SPACE); + val32 &= ~BIT_BCN_TIMER_SEL_FWRD(BIT_MASK_BCN_TIMER_SEL_FWRD); + val32 |= BIT_BCN_TIMER_SEL_FWRD(adapter->hw_port); + rtw_write32(adapter, REG_MBSSID_BCN_SPACE, val32); + + /* read and save HIGH 32bits TSF value */ + val64 = rtw_read32(adapter, REG_TSFTR+4); + val64 = val64 << 32; + + /* read and save LOW 32bits TSF value */ + val64 |= rtw_read32(adapter, REG_TSFTR); + *((u64*)val) = val64; + break; + default: GetHwReg(adapter, variable, val); break; @@ -3006,7 +3010,6 @@ u8 rtl8822b_sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval case HAL_DEF_BEAMFORMER_CAP: case HAL_DEF_BEAMFORMEE_CAP: case HW_VAR_MAX_RX_AMPDU_FACTOR: - case HW_DEF_RA_INFO_DUMP: case HAL_DEF_DBG_DUMP_TXPKT: case HAL_DEF_TX_PAGE_SIZE: case HAL_DEF_TX_PAGE_BOUNDARY: @@ -3015,8 +3018,6 @@ u8 rtl8822b_sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval case HAL_DEF_PCI_SUUPORT_L1_BACKDOOR: case HAL_DEF_PCI_AMD_L1_SUPPORT: case HAL_DEF_PCI_ASPM_OSC: - case HAL_DEF_MACID_SLEEP: - case HAL_DEF_DBG_DIS_PWT: case HAL_DEF_EFUSE_USAGE: case HAL_DEF_EFUSE_BYTES: case HW_VAR_BEST_AMPDU_DENSITY: @@ -3029,7 +3030,27 @@ u8 rtl8822b_sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval return bResult; } +void rtl8822b_ra_info_dump(_adapter *padapter, void *sel) +{ + u8 mac_id; + struct sta_info *psta; + u32 rate_mask1, rate_mask2; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + + for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) { + if (rtw_macid_is_used(macid_ctl, mac_id) && !rtw_macid_is_bmc(macid_ctl, mac_id)) { + psta = macid_ctl->sta[mac_id]; + if (!psta) + continue; + dump_sta_info(sel, psta); + rate_mask1 = macid_ctl->rate_bmp0[mac_id]; + rate_mask2 = macid_ctl->rate_bmp1[mac_id]; + _RTW_PRINT_SEL(sel, "rate_mask2:0x%08x, rate_mask1:0x%08x\n", rate_mask2, rate_mask1); + } + } +} /* * Description: * Query setting of specified variable. @@ -3039,7 +3060,8 @@ u8 rtl8822b_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval PHAL_DATA_TYPE hal; struct dvobj_priv *d; u8 bResult; - u8 val8; + u8 val8 = 0; + u32 val32 = 0; d = adapter_to_dvobj(adapter); @@ -3059,16 +3081,20 @@ u8 rtl8822b_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval #endif break; +/* + case HAL_DEF_DRVINFO_SZ: + break; +*/ case HAL_DEF_MAX_RECVBUF_SZ: *((u32 *)pval) = MAX_RECVBUF_SZ; break; case HAL_DEF_RX_PACKET_OFFSET: - rtw_halmac_get_drv_info_sz(d, &val8); - *((u32 *)pval) = HALMAC_RX_DESC_SIZE_8822B + val8; + val32 = rtl8822b_get_rx_desc_size(adapter); + val8 = rtl8822b_get_rx_drv_info_size(adapter); + *((u32 *)pval) = val32 + val8; break; /* - case HAL_DEF_DRVINFO_SZ: case HAL_DEF_RX_DMA_SZ_WOW: case HAL_DEF_RX_DMA_SZ: case HAL_DEF_RX_PAGE_SIZE: @@ -3131,77 +3157,18 @@ u8 rtl8822b_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval *(HT_CAP_AMPDU_FACTOR *)pval = MAX_AMPDU_FACTOR_16K; break; - case HW_DEF_RA_INFO_DUMP: { -#if 0 - u8 mac_id = *(u8 *)pval; - u32 cmd; - u32 ra_info1, ra_info2; - u32 rate_mask1, rate_mask2; - u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate; - - RTW_INFO("============ RA status check Mac_id:%d ===================\n", mac_id); - - cmd = 0x40000100 | mac_id; - rtw_write32(adapter, REG_HMEBOX_DBG_2_8723B, cmd); - rtw_msleep_os(10); - ra_info1 = rtw_read32(adapter, 0x2F0); - curr_tx_rate = ra_info1 & 0x7F; - curr_tx_sgi = (ra_info1 >> 7) & 0x01; - RTW_INFO("[ ra_info1:0x%08x ] =>cur_tx_rate=%s, cur_sgi:%d, PWRSTS=0x%02x\n", - ra_info1, - HDATA_RATE(curr_tx_rate), - curr_tx_sgi, - (ra_info1 >> 8) & 0x07); - - cmd = 0x40000400 | mac_id; - rtw_write32(adapter, REG_HMEBOX_DBG_2_8723B, cmd); - rtw_msleep_os(10); - ra_info1 = rtw_read32(adapter, 0x2F0); - ra_info2 = rtw_read32(adapter, 0x2F4); - rate_mask1 = rtw_read32(adapter, 0x2F8); - rate_mask2 = rtw_read32(adapter, 0x2FC); - hight_rate = ra_info2 & 0xFF; - lowest_rate = (ra_info2 >> 8) & 0xFF; - - RTW_INFO("[ ra_info1:0x%08x ] =>RSSI=%d, BW_setting=0x%02x, DISRA=0x%02x, VHT_EN=0x%02x\n", - ra_info1, - ra_info1 & 0xFF, - (ra_info1 >> 8) & 0xFF, - (ra_info1 >> 16) & 0xFF, - (ra_info1 >> 24) & 0xFF); - - RTW_INFO("[ ra_info2:0x%08x ] =>hight_rate=%s, lowest_rate=%s, SGI=0x%02x, RateID=%d\n", - ra_info2, - HDATA_RATE(hight_rate), - HDATA_RATE(lowest_rate), - (ra_info2 >> 16) & 0xFF, - (ra_info2 >> 24) & 0xFF); - - RTW_INFO("rate_mask2=0x%08x, rate_mask1=0x%08x\n", rate_mask2, rate_mask1); -#endif - } - break; + case HW_DEF_RA_INFO_DUMP: + rtl8822b_ra_info_dump(adapter, pval); + break; /* case HAL_DEF_DBG_DUMP_TXPKT: - break; -*/ case HAL_DEF_TX_PAGE_SIZE: - *(u32 *)pval = HALMAC_TX_PAGE_SIZE_8822B; - break; -/* case HAL_DEF_TX_PAGE_BOUNDARY: case HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN: case HAL_DEF_ANT_DETECT: case HAL_DEF_PCI_SUUPORT_L1_BACKDOOR: case HAL_DEF_PCI_AMD_L1_SUPPORT: case HAL_DEF_PCI_ASPM_OSC: - break; -*/ - case HAL_DEF_MACID_SLEEP: - *(u8 *)pval = _TRUE; /* support macid sleep */ - break; -/* - case HAL_DEF_DBG_DIS_PWT: case HAL_DEF_EFUSE_USAGE: case HAL_DEF_EFUSE_BYTES: break; @@ -3358,6 +3325,51 @@ void rtl8822b_fill_txdesc_phy(PADAPTER adapter, struct pkt_attrib *pattrib, u8 * } } +/** + * rtl8822b_fill_txdesc_tx_rate() - Set rate in tx description + * @adapter struct _ADAPTER* + * @attrib packet attribute + * @rate DESC_RATE* + * @shrt 1/0 means short/long PLCP for CCK, short/long GI for HT/VHT + * @fallback enable rate fallback or not + * @desc buffer of tx description + * + * Fill rate related fields of tx description when driver want to use specific + * data rate to send this packet. + */ +static void rtl8822b_fill_txdesc_tx_rate(struct _ADAPTER *adapter, + struct pkt_attrib *attrib, + u8 rate, u8 shrt, u8 fallback, u8 *desc) +{ + u8 disfb; + u8 bw; + + + rate = rate & 0x7F; + shrt = shrt ? 1 : 0; + disfb = fallback ? 0 : 1; + + SET_TX_DESC_USE_RATE_8822B(desc, 1); + SET_TX_DESC_DATARATE_8822B(desc, rate); + SET_TX_DESC_DATA_SHORT_8822B(desc, shrt); + SET_TX_DESC_DISDATAFB_8822B(desc, disfb); + + /* HT MCS rate can't support bandwidth higher than 40MHz */ + bw = GET_TX_DESC_DATA_BW_8822B(desc); + if (((rate >= DESC_RATEMCS0) && (rate <= DESC_RATEMCS31)) && (bw > 1)) { + RTW_WARN(FUNC_ADPT_FMT ": Use HT rate(%s) on bandwidth " + "higher than 40MHz(%u>%u) is illegal, " + "switch bandwidth to 40MHz!\n", + FUNC_ADPT_ARG(adapter), + HDATA_RATE(rate), attrib->bwmode, + CHANNEL_WIDTH_40); + + if (attrib->bwmode > CHANNEL_WIDTH_40) + attrib->bwmode = CHANNEL_WIDTH_40; + rtl8822b_fill_txdesc_phy(adapter, attrib, desc); + } +} + #ifdef CONFIG_CONCURRENT_MODE void rtl8822b_fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc) { @@ -3369,6 +3381,13 @@ void rtl8822b_fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdes } #endif +void rtl8822b_fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc) +{ + SET_TX_DESC_USE_RATE_8822B(ptxdesc, 1); + SET_TX_DESC_DATARATE_8822B(ptxdesc, MRateToHwRate(pattrib->rate)); + SET_TX_DESC_DISDATAFB_8822B(ptxdesc, 1); +} + /* * Description: * Fill tx description for beamforming packets @@ -3434,7 +3453,8 @@ void rtl8822b_fill_txdesc_mgnt_bf(struct xmit_frame *frame, u8 *desc) SET_TX_DESC_DISDATAFB(desc, 1); /*SET_TX_DESC_SW_SEQ_8822B(desc, pattrib->seqnum);*/ SET_TX_DESC_DATA_BW_8822B(desc, rtl8822b_bw_mapping(adapter, attrib)); - SET_TX_DESC_RTS_SC_8822B(desc, rtl8822b_sc_mapping(adapter, attrib)); + SET_TX_DESC_SIGNALING_TA_PKT_SC_8822B(desc, + rtl8822b_sc_mapping(adapter, attrib)); /*SET_TX_DESC_RTY_LMT_EN_8822B(ptxdesc, 1);*/ SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(desc, 5); SET_TX_DESC_NDPA_8822B(desc, 1); @@ -3462,8 +3482,8 @@ void rtl8822b_fill_txdesc_mgnt_bf(struct xmit_frame *frame, u8 *desc) void rtl8822b_cal_txdesc_chksum(PADAPTER adapter, u8 *ptxdesc) { - PHALMAC_ADAPTER halmac; - PHALMAC_API api; + struct halmac_adapter *halmac; + struct halmac_api *api; halmac = adapter_to_halmac(adapter); @@ -3480,6 +3500,7 @@ void rtl8822b_prepare_mp_txdesc(PADAPTER adapter, struct mp_priv *pmp_priv) struct pkt_attrib *attrib; u32 pkt_size; s32 bmcast; + u32 desc_size; u8 data_rate, pwr_status, offset; @@ -3487,11 +3508,12 @@ void rtl8822b_prepare_mp_txdesc(PADAPTER adapter, struct mp_priv *pmp_priv) attrib = &pmp_priv->tx.attrib; pkt_size = attrib->last_txcmdsz; bmcast = IS_MCAST(attrib->ra); + desc_size = rtl8822b_get_tx_desc_size(adapter); SET_TX_DESC_LS_8822B(desc, 1); SET_TX_DESC_TXPKTSIZE_8822B(desc, pkt_size); - offset = HALMAC_TX_DESC_SIZE_8822B; + offset = desc_size; SET_TX_DESC_OFFSET_8822B(desc, offset); #if defined(CONFIG_PCI_HCI) SET_TX_DESC_PKT_OFFSET_8822B(desc, 0); /* 8822BE pkt_offset is 0 */ @@ -3517,7 +3539,7 @@ void rtl8822b_prepare_mp_txdesc(PADAPTER adapter, struct mp_priv *pmp_priv) if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160) SET_TX_DESC_DATA_BW_8822B(desc, pmp_priv->bandwidth); else { - RTW_INFO("%s: unknown bandwidth %d, use 20M\n", + RTW_ERR("%s: unknown bandwidth %d, use 20M\n", __FUNCTION__, pmp_priv->bandwidth); SET_TX_DESC_DATA_BW_8822B(desc, CHANNEL_WIDTH_20); } @@ -3536,10 +3558,9 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) struct mlme_ext_info *pmlmeinfo; struct pkt_attrib *pattrib; s32 bmcst; + u32 desc_size; - _rtw_memset(pbuf, 0, HALMAC_TX_DESC_SIZE_8822B); - adapter = pxmitframe->padapter; hal = GET_HAL_DATA(adapter); pmlmeext = &adapter->mlmeextpriv; @@ -3548,6 +3569,9 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) pattrib = &pxmitframe->attrib; bmcst = IS_MCAST(pattrib->ra); + desc_size = rtl8822b_get_tx_desc_size(adapter); + _rtw_memset(pbuf, 0, desc_size); + if (pxmitframe->frame_tag == DATA_FRAMETAG) { u8 drv_userate = 0; @@ -3592,31 +3616,32 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) rtl8822b_fill_txdesc_phy(adapter, pattrib, pbuf); /* compatibility for MCC consideration, use pmlmeext->cur_channel */ - if (pmlmeext->cur_channel > 14) - /* for 5G, OFDM 6M */ - SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(pbuf, 4); - else - /* for 2.4G, CCK 1M */ - SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(pbuf, 0); - - if (hal->fw_ractrl == _FALSE) { - SET_TX_DESC_USE_RATE_8822B(pbuf, 1); + if (!bmcst) { + if (pmlmeext->cur_channel > 14) + /* for 5G, OFDM 6M */ + SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(pbuf, 4); + else + /* for 2.4G, CCK 1M */ + SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(pbuf, 0); + } - if (hal->INIDATA_RATE[pattrib->mac_id] & BIT(7)) - SET_TX_DESC_DATA_SHORT_8822B(pbuf, 1); + if (hal->fw_ractrl == _FALSE) + rtl8822b_fill_txdesc_tx_rate(adapter, pattrib, + hal->INIDATA_RATE[pattrib->mac_id] & 0x7F, + hal->INIDATA_RATE[pattrib->mac_id] & BIT(7) ? 1 : 0, + 1, pbuf); - SET_TX_DESC_DATARATE_8822B(pbuf, hal->INIDATA_RATE[pattrib->mac_id] & 0x7F); + if (bmcst) { + SET_TX_DESC_SW_DEFINE_8822B(pbuf, 0x01); + rtl8822b_fill_txdesc_bmc_tx_rate(pattrib, pbuf); } /* modify data rate by iwpriv */ - if (adapter->fix_rate != 0xFF) { - SET_TX_DESC_USE_RATE_8822B(pbuf, 1); - if (adapter->fix_rate & BIT(7)) - SET_TX_DESC_DATA_SHORT_8822B(pbuf, 1); - SET_TX_DESC_DATARATE_8822B(pbuf, adapter->fix_rate & 0x7F); - if (!adapter->data_fb) - SET_TX_DESC_DISDATAFB_8822B(pbuf, 1); - } + if (adapter->fix_rate != 0xFF) + rtl8822b_fill_txdesc_tx_rate(adapter, pattrib, + adapter->fix_rate & 0x7F, + adapter->fix_rate & BIT(7) ? 1 : 0, + adapter->data_fb, pbuf); if (pattrib->ldpc) SET_TX_DESC_DATA_LDPC_8822B(pbuf, 1); @@ -3626,6 +3651,12 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) #ifdef CONFIG_CMCC_TEST SET_TX_DESC_DATA_SHORT_8822B(pbuf, 1); /* use cck short premble */ #endif + +#ifdef CONFIG_WMMPS_STA + if (pattrib->trigger_frame) + SET_TX_DESC_TRI_FRAME_8822B (pbuf, 1); +#endif /* CONFIG_WMMPS_STA */ + } else { /* * EAP data packet and ARP packet. @@ -3686,7 +3717,7 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) RTW_INFO("%s: TXAGG_FRAMETAG\n", __FUNCTION__); #ifdef CONFIG_MP_INCLUDED else if (pxmitframe->frame_tag == MP_FRAMETAG) { - RTW_INFO("%s: MP_FRAMETAG\n", __FUNCTION__); + RTW_DBG("%s: MP_FRAMETAG\n", __FUNCTION__); fill_txdesc_for_mp(adapter, pbuf); } #endif @@ -3707,7 +3738,7 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) u8 pkt_offset, offset; pkt_offset = 0; - offset = HALMAC_TX_DESC_SIZE_8822B; + offset = desc_size; #ifdef CONFIG_USB_HCI pkt_offset = pxmitframe->pkt_offset; offset += (pxmitframe->pkt_offset >> 3); @@ -3743,6 +3774,11 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) SET_TX_DESC_PORT_ID_8822B(pbuf, get_hw_port(adapter)); SET_TX_DESC_MULTIPLE_PORT_8822B(pbuf, get_hw_port(adapter)); +#ifdef CONFIG_ANTENNA_DIVERSITY + if (!bmcst && pattrib->psta) + odm_set_tx_ant_by_tx_info(adapter_to_phydm(adapter), pbuf, pattrib->psta->cmn.mac_id); +#endif + rtl8822b_fill_txdesc_bf(pxmitframe, pbuf); } @@ -3756,11 +3792,6 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) void rtl8822b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) { fill_default_txdesc(pxmitframe, pbuf); - -#ifdef CONFIG_ANTENNA_DIVERSITY - odm_set_tx_ant_by_tx_info(&GET_HAL_DATA(pxmitframe->padapter)->odmpriv, pbuf, pxmitframe->attrib.mac_id); -#endif /* CONFIG_ANTENNA_DIVERSITY */ - rtl8822b_cal_txdesc_chksum(pxmitframe->padapter, pbuf); } @@ -3776,12 +3807,15 @@ static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen, { /* Clear all status */ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + u32 desc_size; + - _rtw_memset(pDesc, 0, HALMAC_TX_DESC_SIZE_8822B); + desc_size = rtl8822b_get_tx_desc_size(adapter); + _rtw_memset(pDesc, 0, desc_size); SET_TX_DESC_LS_8822B(pDesc, 1); - SET_TX_DESC_OFFSET_8822B(pDesc, HALMAC_TX_DESC_SIZE_8822B); + SET_TX_DESC_OFFSET_8822B(pDesc, desc_size); SET_TX_DESC_TXPKTSIZE_8822B(pDesc, BufferLen); SET_TX_DESC_QSEL_8822B(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */ @@ -3807,6 +3841,20 @@ static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen, SET_TX_DESC_USE_RATE_8822B(pDesc, 1); SET_TX_DESC_DATARATE_8822B(pDesc, MRateToHwRate(pmlmeext->tx_rate)); +#ifdef CONFIG_MCC_MODE + /* config Null data retry number */ + if (IsPsPoll == _FALSE && IsBTQosNull == _FALSE && bDataFrame == _FALSE) { + if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) { + u8 rty_num = adapter->mcc_adapterpriv.null_rty_num; + if (rty_num != 0) { + SET_TX_DESC_RTY_LMT_EN_8822B(pDesc, 1); + SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(pDesc, rty_num); + } + } + } +#endif + + /* * Encrypt the data frame if under security mode excepct null data. */ @@ -3886,8 +3934,11 @@ void rtl8822b_dbg_dump_tx_desc(PADAPTER adapter, int frame_tag, u8 *ptxdesc) void rtl8822b_rxdesc2attribute(struct rx_pkt_attrib *a, u8 *desc) { + /* initial value */ _rtw_memset(a, 0, sizeof(struct rx_pkt_attrib)); + a->bw = CHANNEL_WIDTH_MAX; + /* Get from RX DESC */ a->pkt_len = (u16)GET_RX_DESC_PKT_LEN_8822B(desc); a->pkt_rpt_type = GET_RX_DESC_C2H_8822B(desc) ? C2H_PACKET : NORMAL_RX; @@ -3910,6 +3961,8 @@ void rtl8822b_rxdesc2attribute(struct rx_pkt_attrib *a, u8 *desc) a->frag_num = (u8)GET_RX_DESC_FRAG_8822B(desc); a->data_rate = (u8)GET_RX_DESC_RX_RATE_8822B(desc); + a->ppdu_cnt = (u8)GET_RX_DESC_PPDU_CNT_8822B(desc); + a->free_cnt = (u32)GET_RX_DESC_TSFL_8822B(desc); } } @@ -3992,10 +4045,6 @@ void rtl8822b_set_hal_ops(PADAPTER adapter) */ /*** DM section ***/ -/* - ops->InitSwLeds = NULL; - ops->DeInitSwLeds = NULL; -*/ ops->set_chnl_bw_handler = rtl8822b_set_channel_bw; ops->set_tx_power_level_handler = rtl8822b_set_tx_power_level; @@ -4005,9 +4054,6 @@ void rtl8822b_set_hal_ops(PADAPTER adapter) ops->get_tx_power_index_handler = rtl8822b_get_tx_power_index; ops->hal_dm_watchdog = rtl8822b_phy_haldm_watchdog; -#ifdef CONFIG_LPS_LCLK_WD_TIMER - ops->hal_dm_watchdog_in_lps = rtl8822b_phy_haldm_watchdog_in_lps; -#endif ops->set_hw_reg_handler = rtl8822b_sethwreg; ops->GetHwRegHandler = rtl8822b_gethwreg; @@ -4017,7 +4063,6 @@ void rtl8822b_set_hal_ops(PADAPTER adapter) ops->GetHalODMVarHandler = GetHalODMVar; ops->SetHalODMVarHandler = SetHalODMVar; - ops->update_ra_mask_handler = update_ra_mask_8822b; ops->SetBeaconRelatedRegistersHandler = set_beacon_related_registers; /* @@ -4027,6 +4072,7 @@ void rtl8822b_set_hal_ops(PADAPTER adapter) ops->write_bbreg = rtl8822b_write_bb_reg; ops->read_rfreg = rtl8822b_read_rf_reg; ops->write_rfreg = rtl8822b_write_rf_reg; + ops->read_wmmedca_reg = rtl8822b_read_wmmedca_reg; #ifdef CONFIG_HOSTAPD_MLME /* @@ -4071,9 +4117,9 @@ void rtl8822b_set_hal_ops(PADAPTER adapter) ops->clear_interrupt = NULL; */ #endif - - ops->hal_get_tx_buff_rsvd_page_num = get_txbuffer_rsvdpagenum; - +/* + ops->hal_get_tx_buff_rsvd_page_num = NULL; +*/ #ifdef CONFIG_GPIO_API /* ops->update_hisr_hsisr_ind = NULL; diff --git a/hal/rtl8822b/rtl8822b_phy.c b/hal/rtl8822b/rtl8822b_phy.c index e606317..b83d129 100644 --- a/hal/rtl8822b/rtl8822b_phy.c +++ b/hal/rtl8822b/rtl8822b_phy.c @@ -30,28 +30,28 @@ static void bb_rf_register_definition(PADAPTER adapter) /* RF Interface Sowrtware Control */ - hal->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; - hal->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; + hal->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; + hal->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* RF Interface Output (and Enable) */ - hal->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; - hal->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; + hal->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; + hal->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* RF Interface (Output and) Enable */ - hal->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; - hal->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; + hal->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; + hal->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; - hal->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rA_LSSIWrite_Jaguar; - hal->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rB_LSSIWrite_Jaguar; + hal->PHYRegDef[RF_PATH_A].rf3wireOffset = rA_LSSIWrite_Jaguar; + hal->PHYRegDef[RF_PATH_B].rf3wireOffset = rB_LSSIWrite_Jaguar; - hal->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rHSSIRead_Jaguar; - hal->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rHSSIRead_Jaguar; + hal->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rHSSIRead_Jaguar; + hal->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rHSSIRead_Jaguar; /* Tranceiver Readback LSSI/HSPI mode */ - hal->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rA_SIRead_Jaguar; - hal->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rB_SIRead_Jaguar; - hal->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = rA_PIRead_Jaguar; - hal->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = rB_PIRead_Jaguar; + hal->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rA_SIRead_Jaguar; + hal->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rB_SIRead_Jaguar; + hal->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = rA_PIRead_Jaguar; + hal->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = rB_PIRead_Jaguar; } /* @@ -180,7 +180,8 @@ static u8 init_bb_reg(PADAPTER adapter) static u8 _init_rf_reg(PADAPTER adapter) { - u8 path, phydm_path; + u8 path; + enum rf_path phydm_path; PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE u8 *regfile; @@ -196,15 +197,15 @@ static u8 _init_rf_reg(PADAPTER adapter) for (path = 0; path < hal->NumTotalRFPath; path++) { /* Initialize RF from configuration file */ switch (path) { - case RF_PATH_A: - phydm_path = ODM_RF_PATH_A; + case 0: + phydm_path = RF_PATH_A; #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE regfile = PHY_FILE_RADIO_A; #endif break; - case RF_PATH_B: - phydm_path = ODM_RF_PATH_B; + case 1: + phydm_path = RF_PATH_B; #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE regfile = PHY_FILE_RADIO_B; #endif @@ -222,7 +223,7 @@ static u8 _init_rf_reg(PADAPTER adapter) ret = _TRUE; #endif if (_FALSE == ret) { - status = odm_config_rf_with_header_file(&hal->odmpriv, CONFIG_RF_RADIO, (enum odm_rf_radio_path_e)phydm_path); + status = odm_config_rf_with_header_file(&hal->odmpriv, CONFIG_RF_RADIO, phydm_path); if (HAL_STATUS_SUCCESS != status) goto exit; ret = _TRUE; @@ -271,21 +272,24 @@ static u8 init_rf_reg(PADAPTER adapter) */ u8 rtl8822b_phy_init(PADAPTER adapter) { - PHAL_DATA_TYPE hal; - struct PHY_DM_STRUCT *phydm; - u8 rf_type; - enum odm_rf_path_e txpath, rxpath; + struct dvobj_priv *d; + struct dm_struct *phydm; + enum bb_path txpath = BB_PATH_A | BB_PATH_B; + enum bb_path rxpath = BB_PATH_A | BB_PATH_B; BOOLEAN tx2path; + int err; u8 ok = _TRUE; BOOLEAN ret; - hal = GET_HAL_DATA(adapter); - phydm = &hal->odmpriv; + d = adapter_to_dvobj(adapter); + phydm = adapter_to_phydm(adapter); bb_rf_register_definition(adapter); - rtw_halmac_phy_power_switch(adapter_to_dvobj(adapter), _TRUE); + err = rtw_halmac_phy_power_switch(d, _TRUE); + if (err) + return _FALSE; ret = config_phydm_parameter_init_8822b(phydm, ODM_PRE_SETTING); if (FALSE == ret) @@ -302,23 +306,7 @@ u8 rtl8822b_phy_init(PADAPTER adapter) if (FALSE == ret) return _FALSE; - rf_type = RF_2T2R; - rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)&rf_type); - switch (rf_type) { - case RF_1T1R: - txpath = ODM_RF_A; - rxpath = ODM_RF_A; - break; - case RF_1T2R: - txpath = ODM_RF_A; - rxpath = ODM_RF_A | ODM_RF_B; - break; - default: - case RF_2T2R: - txpath = ODM_RF_A | ODM_RF_B; - rxpath = ODM_RF_A | ODM_RF_B; - break; - } + rtw_hal_get_rf_path(d, NULL, &txpath, &rxpath); tx2path = FALSE; ret = config_phydm_trx_mode_8822b(phydm, txpath, rxpath, tx2path); if (FALSE == ret) @@ -331,10 +319,6 @@ static void dm_CheckProtection(PADAPTER adapter) { } -static void dm_CheckStatistics(PADAPTER adapter) -{ -} - #ifdef CONFIG_SUPPORT_HW_WPS_PBC static void dm_CheckPbcGPIO(PADAPTER adapter) { @@ -439,38 +423,6 @@ void dm_InterruptMigration(PADAPTER adapter) } #endif /* CONFIG_PCI_HCI */ -#ifdef CONFIG_BEAMFORMING -#ifdef RTW_BEAMFORMING_VERSION_2 -void dm_HalBeamformingConfigCSIRate(PADAPTER adapter) -{ - struct PHY_DM_STRUCT *p_dm_odm; - struct beamforming_info *bf_info; - u8 fix_rate_enable = 0; - u8 new_csi_rate_idx; - - /* Acting as BFee */ - if (IS_BEAMFORMEE(adapter)) { - #if 0 - /* Do not enable now because it will affect MU performance and CTS/BA rate. 2016.07.19. by tynli. [PCIE-1660] */ - if (IS_HARDWARE_TYPE_8821C(Adapter)) - FixRateEnable = 1; /* Support after 8821C */ - #endif - - p_dm_odm = GET_ODM(adapter); - bf_info = GET_BEAMFORM_INFO(adapter); - - rtw_halmac_bf_cfg_csi_rate(adapter_to_dvobj(adapter), - p_dm_odm->rssi_min, - bf_info->cur_csi_rpt_rate, - fix_rate_enable, &new_csi_rate_idx); - - if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) - bf_info->cur_csi_rpt_rate = new_csi_rate_idx; - } -} -#endif /* RTW_BEAMFORMING_VERSION_2 */ -#endif /* CONFIG_BEAMFORMING */ - /* * ============================================================ * functions @@ -479,7 +431,7 @@ void dm_HalBeamformingConfigCSIRate(PADAPTER adapter) static void init_phydm_cominfo(PADAPTER adapter) { PHAL_DATA_TYPE hal; - struct PHY_DM_STRUCT *p_dm_odm; + struct dm_struct *p_dm_odm; u32 support_ability = 0; u8 cut_ver = ODM_CUT_A, fab_ver = ODM_TSMC; @@ -532,43 +484,28 @@ static void init_phydm_cominfo(PADAPTER adapter) void rtl8822b_phy_init_dm_priv(PADAPTER adapter) { - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *podmpriv = &hal->odmpriv; + struct dm_struct *podmpriv = adapter_to_phydm(adapter); init_phydm_cominfo(adapter); odm_init_all_timers(podmpriv); - /*PHYDM API - thermal trim*/ - phydm_get_thermal_trim_offset(podmpriv); - /*PHYDM API - power trim*/ - phydm_get_power_trim_offset(podmpriv); - } void rtl8822b_phy_deinit_dm_priv(PADAPTER adapter) { - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *podmpriv = &hal->odmpriv; + struct dm_struct *podmpriv = adapter_to_phydm(adapter); odm_cancel_all_timers(podmpriv); } void rtl8822b_phy_init_haldm(PADAPTER adapter) { - PHAL_DATA_TYPE hal; - struct PHY_DM_STRUCT *p_dm_odm; - - - hal = GET_HAL_DATA(adapter); - p_dm_odm = &hal->odmpriv; - - odm_dm_init(p_dm_odm); + rtw_phydm_init(adapter); } static void check_rxfifo_full(PADAPTER adapter) { struct dvobj_priv *psdpriv = adapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); struct registry_priv *regsty = &adapter->registrypriv; u8 val8 = 0; @@ -587,9 +524,7 @@ static void check_rxfifo_full(PADAPTER adapter) void rtl8822b_phy_haldm_watchdog(PADAPTER adapter) { BOOLEAN bFwCurrentInPSMode = _FALSE; - BOOLEAN bFwPSAwake = _TRUE; - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - + u8 bFwPSAwake = _TRUE; #ifdef CONFIG_MP_INCLUDED /* for MP power tracking */ @@ -603,7 +538,7 @@ void rtl8822b_phy_haldm_watchdog(PADAPTER adapter) #ifdef CONFIG_LPS bFwCurrentInPSMode = adapter_to_pwrctl(adapter)->bFwCurrentInPSMode; - rtw_hal_get_hwreg(adapter, HW_VAR_FWLPS_RF_ON, (u8 *)&bFwPSAwake); + rtw_hal_get_hwreg(adapter, HW_VAR_FWLPS_RF_ON, &bFwPSAwake); #endif /* CONFIG_LPS */ #ifdef CONFIG_P2P_PS @@ -625,34 +560,16 @@ void rtl8822b_phy_haldm_watchdog(PADAPTER adapter) dm_CheckProtection(adapter); } - /* PHYDM */ - if (rtw_is_hw_init_completed(adapter)) { - u8 is_linked = _FALSE; - u8 bsta_state = _FALSE; - u8 bBtDisabled = _TRUE; - - if (rtw_mi_check_status(adapter, MI_ASSOC)) { - is_linked = _TRUE; - if (rtw_mi_check_status(adapter, MI_STA_LINKED)) - bsta_state = _TRUE; - } - - odm_cmn_info_update(&hal->odmpriv, ODM_CMNINFO_LINK, is_linked); - odm_cmn_info_update(&hal->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state); - -#ifdef CONFIG_BT_COEXIST - bBtDisabled = rtw_btcoex_IsBtDisabled(adapter); -#endif /* CONFIG_BT_COEXIST */ - odm_cmn_info_update(&hal->odmpriv, ODM_CMNINFO_BT_ENABLED, ((bBtDisabled == _TRUE) ? _FALSE : _TRUE)); - - odm_dm_watchdog(&hal->odmpriv); - } +#ifdef CONFIG_DISABLE_ODM + goto skip_dm; +#endif + rtw_phydm_watchdog(adapter); #ifdef CONFIG_BEAMFORMING #ifdef RTW_BEAMFORMING_VERSION_2 if (check_fwstate(&adapter->mlmepriv, WIFI_STATION_STATE) && check_fwstate(&adapter->mlmepriv, _FW_LINKED)) - dm_HalBeamformingConfigCSIRate(adapter); + rtw_hal_beamforming_config_csirate(adapter); #endif #endif @@ -668,83 +585,6 @@ void rtl8822b_phy_haldm_watchdog(PADAPTER adapter) #endif /* !CONFIG_SUPPORT_HW_WPS_PBC */ } -void rtl8822b_phy_haldm_in_lps(PADAPTER adapter) -{ - u32 PWDB_rssi = 0; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &hal->odmpriv; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct sta_priv *pstapriv = &adapter->stapriv; - struct sta_info *psta = NULL; - - - RTW_INFO("%s: rssi_min=%d\n", __FUNCTION__, p_dm_odm->rssi_min); - - /* update IGI */ - odm_write_dig(p_dm_odm, p_dm_odm->rssi_min); - - /* set rssi to fw */ - psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); - if (psta && (psta->rssi_stat.undecorated_smoothed_pwdb > 0)) { - PWDB_rssi = (psta->mac_id | (psta->rssi_stat.undecorated_smoothed_pwdb << 16)); - rtl8822b_set_FwRssiSetting_cmd(adapter, (u8 *)&PWDB_rssi); - } -} - -void rtl8822b_phy_haldm_watchdog_in_lps(PADAPTER adapter) -{ - u8 is_linked = _FALSE; - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct PHY_DM_STRUCT *p_dm_odm = &hal->odmpriv; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct sta_priv *pstapriv = &adapter->stapriv; - struct sta_info *psta = NULL; - - if (!rtw_is_hw_init_completed(adapter)) - goto skip_lps_dm; - - if (rtw_mi_check_status(adapter, MI_ASSOC)) - is_linked = _TRUE; - - odm_cmn_info_update(&hal->odmpriv, ODM_CMNINFO_LINK, is_linked); - - if (is_linked == _FALSE) - goto skip_lps_dm; - - if (!(p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR)) - goto skip_lps_dm; - - /* Do DIG by RSSI In LPS-32K */ - - /* 1. Find MIN-RSSI */ - psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); - if (psta == NULL) - goto skip_lps_dm; - - hal->entry_min_undecorated_smoothed_pwdb = psta->rssi_stat.undecorated_smoothed_pwdb; - - RTW_INFO("CurIGValue=%d, entry_min_undecorated_smoothed_pwdb=%d\n", - p_dm_dig_table->cur_ig_value, hal->entry_min_undecorated_smoothed_pwdb); - - if (hal->entry_min_undecorated_smoothed_pwdb <= 0) - goto skip_lps_dm; - - hal->min_undecorated_pwdb_for_dm = hal->entry_min_undecorated_smoothed_pwdb; - - p_dm_odm->rssi_min = hal->min_undecorated_pwdb_for_dm; - -#ifdef CONFIG_LPS - if ((p_dm_dig_table->cur_ig_value > p_dm_odm->rssi_min + 5) - || (p_dm_dig_table->cur_ig_value < p_dm_odm->rssi_min - 5)) - rtw_dm_in_lps_wk_cmd(adapter); -#endif - -skip_lps_dm: - return; -} - static u32 phy_calculatebitshift(u32 mask) { u32 i; @@ -792,16 +632,11 @@ void rtl8822b_write_bb_reg(PADAPTER adapter, u32 addr, u32 mask, u32 val) rtw_write32(adapter, addr, val); } -u32 rtl8822b_read_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask) +u32 rtl8822b_read_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask) { - PHAL_DATA_TYPE hal; - struct PHY_DM_STRUCT *phydm; + struct dm_struct *phydm = adapter_to_phydm(adapter); u32 val; - - hal = GET_HAL_DATA(adapter); - phydm = &hal->odmpriv; - val = config_phydm_read_rf_reg_8822b(phydm, path, addr, mask); if (!config_phydm_read_rf_check_8822b(val)) RTW_INFO(FUNC_ADPT_FMT ": read RF reg path=%d addr=0x%x mask=0x%x FAIL!\n", @@ -810,16 +645,11 @@ u32 rtl8822b_read_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask) return val; } -void rtl8822b_write_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask, u32 val) +void rtl8822b_write_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask, u32 val) { - PHAL_DATA_TYPE hal; - struct PHY_DM_STRUCT *phydm; + struct dm_struct *phydm = adapter_to_phydm(adapter); u8 ret; - - hal = GET_HAL_DATA(adapter); - phydm = &hal->odmpriv; - ret = config_phydm_write_rf_reg_8822b(phydm, path, addr, mask, val); if (_FALSE == ret) RTW_INFO(FUNC_ADPT_FMT ": write RF reg path=%d addr=0x%x mask=0x%x val=0x%x FAIL!\n", @@ -839,9 +669,9 @@ static void set_tx_power_level_by_path(PADAPTER adapter, u8 channel, u8 path) void rtl8822b_set_tx_power_level(PADAPTER adapter, u8 channel) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *phydm; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table; - u8 path = ODM_RF_PATH_A; + struct dm_struct *phydm; + struct phydm_fat_struct *p_dm_fat_table; + u8 path = RF_PATH_A; hal = GET_HAL_DATA(adapter); @@ -850,11 +680,11 @@ void rtl8822b_set_tx_power_level(PADAPTER adapter, u8 channel) if (hal->AntDivCfg) { /* antenna diversity Enable */ - path = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B; + path = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? RF_PATH_A : RF_PATH_B; set_tx_power_level_by_path(adapter, channel, path); } else { /* antenna diversity disable */ - for (path = ODM_RF_PATH_A; path < hal->NumTotalRFPath; ++path) + for (path = RF_PATH_A; path < hal->NumTotalRFPath; ++path) set_tx_power_level_by_path(adapter, channel, path); } } @@ -867,13 +697,12 @@ void rtl8822b_get_tx_power_level(PADAPTER adapter, s32 *power) * Parameters: * padatper * powerindex power index for rate - * rfpath Antenna(RF) path, type "enum odm_rf_radio_path_e" + * rfpath Antenna(RF) path, type "enum rf_path" * rate data rate, type "enum MGN_RATE" */ -void rtl8822b_set_tx_power_index(PADAPTER adapter, u32 powerindex, u8 rfpath, u8 rate) +void rtl8822b_set_tx_power_index(PADAPTER adapter, u32 powerindex, enum rf_path rfpath, u8 rate) { - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *phydm = &hal->odmpriv; + struct dm_struct *phydm = adapter_to_phydm(adapter); u8 shift = 0; static u32 index = 0; @@ -916,7 +745,7 @@ static u8 rtl8822b_phy_get_current_tx_num(PADAPTER adapter, u8 rate) /* * Parameters: * padatper - * rfpath Antenna(RF) path, type "enum odm_rf_radio_path_e" + * rfpath Antenna(RF) path, type "enum rf_path" * rate data rate, type "enum MGN_RATE" * bandwidth Bandwidth, type "enum _CHANNEL_WIDTH" * channel Channel number @@ -924,10 +753,11 @@ static u8 rtl8822b_phy_get_current_tx_num(PADAPTER adapter, u8 rate) * Rteurn: * tx_power power index for rate */ -u8 rtl8822b_get_tx_power_index(PADAPTER adapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic) +u8 rtl8822b_get_tx_power_index(PADAPTER adapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - u8 base_idx = 0, power_idx = 0; + s16 power_idx; + u8 base_idx = 0; s8 by_rate_diff = 0, limit = 0, tpt_offset = 0, extra_bias = 0; u8 ntx_idx = rtl8822b_phy_get_current_tx_num(adapter, rate); u8 bIn24G = _FALSE; @@ -958,7 +788,9 @@ u8 rtl8822b_get_tx_power_index(PADAPTER adapter, u8 rfpath, u8 rate, u8 bandwidt #endif #endif - if (power_idx > MAX_POWER_INDEX) + if (power_idx < 0) + power_idx = 0; + else if (power_idx > MAX_POWER_INDEX) power_idx = MAX_POWER_INDEX; return power_idx; @@ -1053,49 +885,15 @@ static void mac_switch_bandwidth(PADAPTER adapter, u8 pri_ch_idx) } } -/* - * Description: - * Set channel & bandwidth & offset - */ -void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) +static void switch_chnl_and_set_bw_by_drv(PADAPTER adapter, u8 switch_band) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &hal->odmpriv; + struct dm_struct *p_dm_odm = &hal->odmpriv; u8 center_ch = 0, ret = 0; - if (adapter->bNotifyChannelChange) { - RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n", - __FUNCTION__, - hal->bSwChnl, - hal->current_channel, - hal->bSetChnlBW, - hal->current_channel_bw); - } - - if (RTW_CANNOT_RUN(adapter)) { - hal->bSwChnlAndSetBWInProgress = _FALSE; - return; - } - /* set channel & Bandwidth register */ /* 1. set switch band register if need to switch band */ - if (need_switch_band(adapter, hal->current_channel) == _TRUE) { -#ifdef CONFIG_BT_COEXIST - if (hal->EEPROMBluetoothCoexist) { - struct mlme_ext_priv *mlmeext; - - /* switch band under site survey or not, must notify to BT COEX */ - mlmeext = &adapter->mlmeextpriv; - if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE) - rtw_btcoex_switchband_notify(_TRUE, hal->current_band_type); - else - rtw_btcoex_switchband_notify(_FALSE, hal->current_band_type); - } else - rtw_btcoex_wifionly_switchband_notify(adapter); -#else /* !CONFIG_BT_COEXIST */ - rtw_btcoex_wifionly_switchband_notify(adapter); -#endif /* CONFIG_BT_COEXIST */ - + if (switch_band) { /* hal->current_channel is center channel of pmlmeext->cur_channel(primary channel) */ ret = config_phydm_switch_band_8822b(p_dm_odm, hal->current_channel); @@ -1104,19 +902,6 @@ void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) rtw_warn_on(1); return; } - - /* <2016/03/09> ** This Setting is for MP Driver Only*/ -#ifdef CONFIG_MP_INCLUDED - if (adapter->registrypriv.mp_mode == _TRUE) { - /* <2016/02/25, VincentL> Add for 8822B Antenna Binding between "2.4G-WiFi" - And between "5G-BT", Suggested by RF SzuyiTsai*/ - if (hal->current_channel <= 14) /* 2.4G*/ - phy_set_rf_path_switch_8822b(adapter, 1); /*To WiFi-2.4G*/ - else /* 5G */ - phy_set_rf_path_switch_8822b(adapter, 0); /*To BT-5G*/ - } -#endif - } /* 2. set channel register */ @@ -1130,7 +915,7 @@ void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) return; } } - phydm_config_kfree(p_dm_odm, hal->current_channel); + /* 3. set Bandwidth register */ if (hal->bSetChnlBW) { /* get primary channel index */ @@ -1149,6 +934,93 @@ void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) return; } } +} + +#ifdef RTW_CHANNEL_SWITCH_OFFLOAD +static void switch_chnl_and_set_bw_by_fw(PADAPTER adapter, u8 switch_band) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + if (switch_band ||hal->bSwChnl || hal->bSetChnlBW) { + rtw_hal_switch_chnl_and_set_bw_offload(adapter, + hal->current_channel, get_pri_ch_id(adapter), hal->current_channel_bw); + + hal->bSwChnl = _FALSE; + hal->bSetChnlBW = _FALSE; + } +} +#endif + +/* + * Description: + * Set channel & bandwidth & offset + */ +void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct dm_struct *p_dm_odm = &hal->odmpriv; + u8 center_ch = 0, ret = 0, switch_band = _FALSE; + + if (adapter->bNotifyChannelChange) { + RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n", + __FUNCTION__, + hal->bSwChnl, + hal->current_channel, + hal->bSetChnlBW, + hal->current_channel_bw); + } + + if (RTW_CANNOT_RUN(adapter)) { + hal->bSwChnlAndSetBWInProgress = _FALSE; + return; + } + + switch_band = need_switch_band(adapter, hal->current_channel); + + /* config channel, bw, offset setting */ +#ifdef RTW_CHANNEL_SWITCH_OFFLOAD + if (hal->ch_switch_offload) + switch_chnl_and_set_bw_by_fw(adapter, switch_band); + + else + switch_chnl_and_set_bw_by_drv(adapter, switch_band); +#else + switch_chnl_and_set_bw_by_drv(adapter, switch_band); +#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ + + + /* config coex setting */ + if (switch_band) { +#ifdef CONFIG_BT_COEXIST + if (hal->EEPROMBluetoothCoexist) { + struct mlme_ext_priv *mlmeext; + + /* switch band under site survey or not, must notify to BT COEX */ + mlmeext = &adapter->mlmeextpriv; + if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE) + rtw_btcoex_switchband_notify(_TRUE, hal->current_band_type); + else + rtw_btcoex_switchband_notify(_FALSE, hal->current_band_type); + } else + rtw_btcoex_wifionly_switchband_notify(adapter); +#else /* !CONFIG_BT_COEXIST */ + rtw_btcoex_wifionly_switchband_notify(adapter); +#endif /* CONFIG_BT_COEXIST */ + } + + /* <2016/03/09> ** This Setting is for MP Driver Only*/ +#ifdef CONFIG_MP_INCLUDED + if (adapter->registrypriv.mp_mode == _TRUE) { + /* <2016/02/25, VincentL> Add for 8822B Antenna Binding between "2.4G-WiFi" + And between "5G-BT", Suggested by RF SzuyiTsai*/ + if (hal->current_channel <= 14) /* 2.4G*/ + phy_set_rf_path_switch_8822b(p_dm_odm, 1); /*To WiFi-2.4G*/ + else /* 5G */ + phy_set_rf_path_switch_8822b(p_dm_odm, 0); /*To BT-5G*/ + } +#endif + + phydm_config_kfree(p_dm_odm, hal->current_channel); /* TX Power Setting */ odm_clear_txpowertracking_state(p_dm_odm); @@ -1157,7 +1029,8 @@ void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) /* IQK */ if ((hal->bNeedIQK == _TRUE) || (adapter->registrypriv.mp_mode == 1)) { - phy_iq_calibrate_8822b(p_dm_odm, _FALSE); + /*phy_iq_calibrate_8822b(p_dm_odm, _FALSE);*/ + rtw_phydm_iqk_trigger(adapter); hal->bNeedIQK = _FALSE; } } @@ -1177,13 +1050,13 @@ void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter) void rtl8822b_handle_sw_chnl_and_set_bw( PADAPTER Adapter, u8 bSwitchChannel, u8 bSetBandWidth, - u8 ChannelNum, CHANNEL_WIDTH ChnlWidth, u8 ChnlOffsetOf40MHz, + u8 ChannelNum, enum channel_width ChnlWidth, u8 ChnlOffsetOf40MHz, u8 ChnlOffsetOf80MHz, u8 CenterFrequencyIndex1) { PADAPTER pDefAdapter = GetDefaultAdapter(Adapter); PHAL_DATA_TYPE hal = GET_HAL_DATA(pDefAdapter); u8 tmpChannel = hal->current_channel; - CHANNEL_WIDTH tmpBW = hal->current_channel_bw; + enum channel_width tmpBW = hal->current_channel_bw; u8 tmpnCur40MhzPrimeSC = hal->nCur40MhzPrimeSC; u8 tmpnCur80MhzPrimeSC = hal->nCur80MhzPrimeSC; u8 tmpCenterFrequencyIndex1 = hal->CurrentCenterFrequencyIndex1; @@ -1264,7 +1137,7 @@ void rtl8822b_handle_sw_chnl_and_set_bw( * offset40 channel offset for 40MHz Bandwidth * offset80 channel offset for 80MHz Bandwidth */ -void rtl8822b_set_channel_bw(PADAPTER adapter, u8 center_ch, CHANNEL_WIDTH bw, u8 offset40, u8 offset80) +void rtl8822b_set_channel_bw(PADAPTER adapter, u8 center_ch, enum channel_width bw, u8 offset40, u8 offset80) { rtl8822b_handle_sw_chnl_and_set_bw(adapter, _TRUE, _TRUE, center_ch, bw, offset40, offset80, center_ch); } @@ -1290,7 +1163,7 @@ void rtl8822b_mp_config_rfpath(PADAPTER adapter) PHAL_DATA_TYPE hal; PMPT_CONTEXT mpt; ANTENNA_PATH anttx, antrx; - enum odm_rf_path_e rxant; + enum bb_path bb_tx, bb_rx; hal = GET_HAL_DATA(adapter); @@ -1302,31 +1175,34 @@ void rtl8822b_mp_config_rfpath(PADAPTER adapter) switch (anttx) { case ANTENNA_A: - mpt->mpt_rf_path = ODM_RF_A; + mpt->mpt_rf_path = RF_PATH_A; + bb_tx = BB_PATH_A; break; case ANTENNA_B: - mpt->mpt_rf_path = ODM_RF_B; + mpt->mpt_rf_path = RF_PATH_B; + bb_tx = BB_PATH_B; break; case ANTENNA_AB: default: - mpt->mpt_rf_path = ODM_RF_A | ODM_RF_B; + mpt->mpt_rf_path = RF_PATH_AB; + bb_tx = BB_PATH_A | BB_PATH_B; break; } switch (antrx) { case ANTENNA_A: - rxant = ODM_RF_A; + bb_rx = BB_PATH_A; break; case ANTENNA_B: - rxant = ODM_RF_B; + bb_rx = BB_PATH_B; break; case ANTENNA_AB: default: - rxant = ODM_RF_A | ODM_RF_B; + bb_rx = BB_PATH_A | BB_PATH_B; break; } - config_phydm_trx_mode_8822b(GET_PDM_ODM(adapter), mpt->mpt_rf_path, rxant, FALSE); + config_phydm_trx_mode_8822b(GET_PDM_ODM(adapter), bb_tx, bb_rx, FALSE); RTW_INFO("-Config RF Path Finish\n"); } @@ -1747,7 +1623,7 @@ static void _config_beamformer_mu(PADAPTER adapter, struct beamformer_entry *bfe csi_param, bfer->aid & 0xfff, HAL_CSI_SEG_4K, bfer->mac_addr); - bf_info->cur_csi_rpt_rate = HALMAC_OFDM54; + bf_info->cur_csi_rpt_rate = HALMAC_OFDM6; rtw_halmac_bf_cfg_sounding(adapter_to_dvobj(adapter), HAL_BFEE, bf_info->cur_csi_rpt_rate); @@ -2195,11 +2071,11 @@ void rtl8822b_phy_bf_enter(PADAPTER adapter, struct sta_info *sta) struct beamformee_entry *bfee; - RTW_INFO("+%s: " MAC_FMT "\n", __FUNCTION__, MAC_ARG(sta->hwaddr)); + RTW_INFO("+%s: " MAC_FMT "\n", __FUNCTION__, MAC_ARG(sta->cmn.mac_addr)); info = GET_BEAMFORM_INFO(adapter); - bfer = rtw_bf_bfer_get_entry_by_addr(adapter, sta->hwaddr); - bfee = rtw_bf_bfee_get_entry_by_addr(adapter, sta->hwaddr); + bfer = rtw_bf_bfer_get_entry_by_addr(adapter, sta->cmn.mac_addr); + bfee = rtw_bf_bfee_get_entry_by_addr(adapter, sta->cmn.mac_addr); info->bSetBFHwConfigInProgess = _TRUE; diff --git a/hal/rtl8822b/usb/rtl8822bu.h b/hal/rtl8822b/usb/rtl8822bu.h index f8d0858..075e275 100644 --- a/hal/rtl8822b/usb/rtl8822bu.h +++ b/hal/rtl8822b/usb/rtl8822bu.h @@ -36,11 +36,11 @@ void rtl8822bu_interface_configure(PADAPTER); int rtl8822bu_halmac_init_adapter(PADAPTER); /* rtl8822bu_io.c */ - +#ifdef CONFIG_RTW_SW_LED /* rtl8822bu_led.c */ void rtl8822bu_initswleds(PADAPTER); void rtl8822bu_deinitswleds(PADAPTER); - +#endif /* rtl8822bu_xmit.c */ #define OFFSET_SZ 0 #define MAX_TX_AGG_PACKET_NUMBER_8822B 0xff diff --git a/hal/rtl8822b/usb/rtl8822bu_halinit.c b/hal/rtl8822b/usb/rtl8822bu_halinit.c index 5711127..dd1d3ac 100644 --- a/hal/rtl8822b/usb/rtl8822bu_halinit.c +++ b/hal/rtl8822b/usb/rtl8822bu_halinit.c @@ -48,7 +48,7 @@ u8 rtl8822bu_fw_ips_init(_adapter *padapter) if (pwrctl->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE && GET_HAL_DATA(padapter)->bFWReady == _TRUE && pwrctl->pre_ips_type == 0) { - u32 start_time; + systime start_time; u8 cpwm_orig, cpwm_now, rpwm; u8 bMacPwrCtrlOn = _TRUE; @@ -177,37 +177,50 @@ u8 rtl8822bu_fw_ips_deinit(_adapter *padapter) #endif -static void hal_init_misc(PADAPTER padapter) +static void init_hwled(PADAPTER adapter, u8 enable) { - if (padapter->registrypriv.wifi_spec) { - padapter->registrypriv.adaptivity_en = 1; - padapter->registrypriv.adaptivity_mode = 0; - } + u8 mode = 0; + struct led_priv *ledpriv = adapter_to_led(adapter); + + if (ledpriv->LedStrategy != HW_LED) + return; + + rtw_halmac_led_cfg(adapter_to_dvobj(adapter), enable, mode); +} + +static void hal_init_misc(PADAPTER adapter) +{ +#ifdef CONFIG_RTW_LED + init_hwled(adapter, 1); +#endif /* CONFIG_RTW_LED */ + } u32 rtl8822bu_init(PADAPTER padapter) { u8 status = _SUCCESS; - u32 init_start_time = rtw_get_current_time(); + systime init_start_time = rtw_get_current_time(); #ifdef CONFIG_FWLPS_IN_IPS if (_SUCCESS == rtl8822bu_fw_ips_init(padapter)) goto exit; #endif - hal_init_misc(padapter); - rtl8822b_init(padapter); + hal_init_misc(padapter); + exit: RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(init_start_time)); return status; } -static void hal_deinit_misc(PADAPTER padapter) +static void hal_deinit_misc(PADAPTER adapter) { - +#ifdef CONFIG_RTW_LED + init_hwled(adapter, 0); +#endif /* CONFIG_RTW_LED */ } u32 rtl8822bu_deinit(PADAPTER padapter) @@ -402,7 +415,7 @@ void rtl8822bu_interface_configure(PADAPTER padapter) #ifdef CONFIG_USB_TX_AGGREGATION /* according to value defined by halmac */ pHalData->UsbTxAggMode = 1; - pHalData->UsbTxAggDescNum = HALMAC_BLK_DESC_NUM_8822B; + rtw_halmac_usb_get_txagg_desc_num(pdvobjpriv, &pHalData->UsbTxAggDescNum); #endif /* CONFIG_USB_TX_AGGREGATION */ #ifdef CONFIG_USB_RX_AGGREGATION diff --git a/hal/rtl8822b/usb/rtl8822bu_halmac.c b/hal/rtl8822b/usb/rtl8822bu_halmac.c index 2941487..48f1a90 100644 --- a/hal/rtl8822b/usb/rtl8822bu_halmac.c +++ b/hal/rtl8822b/usb/rtl8822bu_halmac.c @@ -16,7 +16,7 @@ #include /* struct dvobj_priv and etc. */ #include "../../hal_halmac.h" -#include "../rtl8822b.h" /* rtl8822b_cal_txdesc_chksum() */ +#include "../rtl8822b.h" /* rtl8822b_cal_txdesc_chksum() and etc. */ #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) #define usb_write_port_complete_not_xmitframe(purb, regs) usb_write_port_complete_not_xmitframe(purb) @@ -129,8 +129,6 @@ static u8 usb_write_data_not_xmitframe(void *d, u8 *pBuf, u32 size, u8 qsel) struct dvobj_priv *pobj = (struct dvobj_priv *)d; PADAPTER padapter = dvobj_get_primary_adapter(pobj); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - PHALMAC_ADAPTER halmac; - PHALMAC_API api; u32 desclen, len; u8 *buf; u8 ret; @@ -138,34 +136,48 @@ static u8 usb_write_data_not_xmitframe(void *d, u8 *pBuf, u32 size, u8 qsel) u8 add_pkt_offset = 0; + desclen = rtl8822b_get_tx_desc_size(padapter); + len = desclen + size; - halmac = dvobj_to_halmac((struct dvobj_priv *)d); - api = HALMAC_GET_API(halmac); + if (qsel == HALMAC_TXDESC_QSEL_BEACON) { - desclen = HALMAC_TX_DESC_SIZE_8822B; - len = desclen + size; + if (len % pHalData->UsbBulkOutSize == 0) + add_pkt_offset = 1; - if (len % pHalData->UsbBulkOutSize == 0) - add_pkt_offset = 1; + if (add_pkt_offset == 1) + len = len + PACKET_OFFSET_SZ; - if (add_pkt_offset == 1) - len = len + PACKET_OFFSET_SZ; + buf = rtw_zmalloc(len); + if (!buf) + return _FALSE; - buf = rtw_zmalloc(len); - if (!buf) - return _FALSE; + if (add_pkt_offset == 1) + _rtw_memcpy(buf + desclen + PACKET_OFFSET_SZ , pBuf, size); + else + _rtw_memcpy(buf + desclen, pBuf, size); + + SET_TX_DESC_TXPKTSIZE_8822B(buf, size); + if (add_pkt_offset == 1) { + SET_TX_DESC_OFFSET_8822B(buf, desclen + PACKET_OFFSET_SZ); + SET_TX_DESC_PKT_OFFSET_8822B(buf, 1); + } else + SET_TX_DESC_OFFSET_8822B(buf, desclen); + + } else if (qsel == HALMAC_TXDESC_QSEL_H2C_CMD){ + + buf = rtw_zmalloc(len); + if (!buf) + return _FALSE; - if (add_pkt_offset == 1) - _rtw_memcpy(buf + desclen + PACKET_OFFSET_SZ , pBuf, size); - else _rtw_memcpy(buf + desclen, pBuf, size); - SET_TX_DESC_TXPKTSIZE_8822B(buf, size); - if (add_pkt_offset == 1) { - SET_TX_DESC_OFFSET_8822B(buf, desclen + PACKET_OFFSET_SZ); - SET_TX_DESC_PKT_OFFSET_8822B(buf, 1); - } else - SET_TX_DESC_OFFSET_8822B(buf, desclen); + SET_TX_DESC_TXPKTSIZE_8822B(buf, size); + } else { + + RTW_ERR("%s: qsel may be error(%d)\n", __func__, qsel); + + return _FALSE; + } SET_TX_DESC_QSEL_8822B(buf, qsel); rtl8822b_cal_txdesc_chksum(padapter, buf); @@ -188,11 +200,9 @@ static u8 usb_write_data_rsvd_page_normal(void *d, u8 *pBuf, u32 size) { struct dvobj_priv *pobj = (struct dvobj_priv *)d; PADAPTER padapter = dvobj_get_primary_adapter(pobj); - PHALMAC_ADAPTER halmac = dvobj_to_halmac((struct dvobj_priv *)d); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct xmit_frame *pcmdframe = NULL; struct pkt_attrib *pattrib = NULL; - PHALMAC_API api = HALMAC_GET_API(halmac); u8 txdesoffset = 0; u8 *buf = NULL; @@ -230,11 +240,9 @@ static u8 usb_write_data_h2c_normal(void *d, u8 *pBuf, u32 size) { struct dvobj_priv *pobj = (struct dvobj_priv *)d; PADAPTER padapter = dvobj_get_primary_adapter(pobj); - PHALMAC_ADAPTER halmac = dvobj_to_halmac((struct dvobj_priv *)d); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct xmit_frame *pcmdframe = NULL; struct pkt_attrib *pattrib = NULL; - PHALMAC_API api = HALMAC_GET_API(halmac); u8 txdesoffset = 0; u8 *buf = NULL; @@ -297,7 +305,7 @@ static u8 usb_write_data_h2c(void *d, u8 *pBuf, u32 size) int rtl8822bu_halmac_init_adapter(PADAPTER padapter) { struct dvobj_priv *d; - PHALMAC_PLATFORM_API api; + struct halmac_platform_api *api; int err; diff --git a/hal/rtl8822b/usb/rtl8822bu_led.c b/hal/rtl8822b/usb/rtl8822bu_led.c index 188f1d0..d684eeb 100644 --- a/hal/rtl8822b/usb/rtl8822bu_led.c +++ b/hal/rtl8822b/usb/rtl8822bu_led.c @@ -17,6 +17,8 @@ #include /* PADAPTER */ #include /* PHAL_DATA_TYPE */ #include /* PLED_USB */ +#include "../../hal_halmac.h" /* HALMAC API */ +#ifdef CONFIG_RTW_SW_LED /* * ============================================================================= @@ -41,15 +43,25 @@ * Description: * Turn on LED according to LedPin specified. */ -void swledon(PADAPTER padapter, PLED_USB pLed) +static void swledon(PADAPTER padapter, PLED_USB led) { - u8 LedCfg; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); if (RTW_CANNOT_RUN(padapter)) return; - pLed->bLedOn = _TRUE; + switch (led->LedPin) { + case LED_PIN_GPIO0: + break; + case LED_PIN_LED0: + case LED_PIN_LED1: + case LED_PIN_LED2: + default: + rtw_halmac_led_switch(adapter_to_dvobj(padapter), 1); + break; + } + + led->bLedOn = _TRUE; } @@ -57,16 +69,25 @@ void swledon(PADAPTER padapter, PLED_USB pLed) * Description: * Turn off LED according to LedPin specified. */ -void swledoff(PADAPTER padapter, PLED_USB pLed) +static void swledoff(PADAPTER padapter, PLED_USB led) { - u8 LedCfg; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); if (RTW_CANNOT_RUN(padapter)) - goto exit; + return; -exit: - pLed->bLedOn = _FALSE; + switch (led->LedPin) { + case LED_PIN_GPIO0: + break; + case LED_PIN_LED0: + case LED_PIN_LED1: + case LED_PIN_LED2: + default: + rtw_halmac_led_switch(adapter_to_dvobj(padapter), 0); + break; + } + + led->bLedOn = _FALSE; } /* @@ -87,6 +108,19 @@ void swledoff(PADAPTER padapter, PLED_USB pLed) */ void rtl8822bu_initswleds(PADAPTER padapter) { + struct led_priv *ledpriv = adapter_to_led(padapter); + u8 enable = 1; + u8 mode = 3; + + ledpriv->LedControlHandler = LedControlUSB; + ledpriv->SwLedOn = swledon; + ledpriv->SwLedOff = swledoff; + + InitLed(padapter, &(ledpriv->SwLed0), LED_PIN_LED0); + InitLed(padapter, &(ledpriv->SwLed1), LED_PIN_LED1); + InitLed(padapter, &(ledpriv->SwLed2), LED_PIN_LED2); + + rtw_halmac_led_cfg(adapter_to_dvobj(padapter), enable, mode); } /* @@ -95,4 +129,14 @@ void rtl8822bu_initswleds(PADAPTER padapter) */ void rtl8822bu_deinitswleds(PADAPTER padapter) { + struct led_priv *ledpriv = adapter_to_led(padapter); + u8 enable = 0; + u8 mode = 3; + + DeInitLed(&(ledpriv->SwLed0)); + DeInitLed(&(ledpriv->SwLed1)); + DeInitLed(&(ledpriv->SwLed2)); + + rtw_halmac_led_cfg(adapter_to_dvobj(padapter), enable, mode); } +#endif diff --git a/hal/rtl8822b/usb/rtl8822bu_ops.c b/hal/rtl8822b/usb/rtl8822bu_ops.c index 8310ac4..0986583 100644 --- a/hal/rtl8822b/usb/rtl8822bu_ops.c +++ b/hal/rtl8822b/usb/rtl8822bu_ops.c @@ -33,13 +33,14 @@ void rtl8822bu_set_hw_type(struct dvobj_priv *pdvobj) RTW_INFO("CHIP TYPE: RTL8822B\n"); } -static void sethwreg(PADAPTER padapter, u8 variable, u8 *val) +static u8 sethwreg(PADAPTER padapter, u8 variable, u8 *val) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); struct registry_priv *registry_par = &padapter->registrypriv; int status = 0; + u8 ret = _SUCCESS; switch (variable) { case HW_VAR_RXDMA_AGG_PG_TH: @@ -47,7 +48,7 @@ static void sethwreg(PADAPTER padapter, u8 variable, u8 *val) if (pdvobjpriv->traffic_stat.cur_tx_tp < 1 && pdvobjpriv->traffic_stat.cur_rx_tp < 1) { /* for low traffic, do not usb AGGREGATION */ pHalData->rxagg_usb_timeout = 0x01; - pHalData->rxagg_usb_size = 0; + pHalData->rxagg_usb_size = 0x01; } else { #ifdef CONFIG_PLATFORM_NOVATEK_NT72668 @@ -128,9 +129,11 @@ static void sethwreg(PADAPTER padapter, u8 variable, u8 *val) } break; default: - rtl8822b_sethwreg(padapter, variable, val); + ret = rtl8822b_sethwreg(padapter, variable, val); break; } + + return ret; } static void gethwreg(PADAPTER padapter, u8 variable, u8 *val) @@ -147,7 +150,7 @@ static void gethwreg(PADAPTER padapter, u8 variable, u8 *val) case HW_VAR_RPWM_TOG: #ifdef CONFIG_LPS_LCLK *val = rtw_read8(padapter, REG_USB_HRPWM_8822B); - *val &= BIT_TOGGLING_8822B; + *val &= BIT_TOGGLE_8822B; #endif /* CONFIG_LPS_LCLK */ break; @@ -223,6 +226,36 @@ static u8 rtl8822bu_ps_func(PADAPTER padapter, HAL_INTF_PS_FUNC efunc_id, u8 *va return bResult; } +#ifdef CONFIG_RTW_LED +static void read_ledsetting(PADAPTER adapter) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + +#ifdef CONFIG_RTW_SW_LED + PHAL_DATA_TYPE hal; + + hal = GET_HAL_DATA(adapter); + ledpriv->bRegUseLed = _TRUE; + + switch (hal->EEPROMCustomerID) { + default: + hal->CustomerID = RT_CID_DEFAULT; + break; + } + + switch (hal->CustomerID) { + case RT_CID_DEFAULT: + default: + ledpriv->LedStrategy = SW_LED_MODE9; + break; + } +#else /* HW LED */ + ledpriv->LedStrategy = HW_LED; +#endif /* CONFIG_RTW_SW_LED */ +} +#endif /* CONFIG_RTW_LED */ + + /* * Description: * Collect all hardware information, fill "HAL_DATA_TYPE". @@ -250,6 +283,10 @@ static u8 read_adapter_info(PADAPTER padapter) * 3. Other Initialization */ +#ifdef CONFIG_RTW_LED + read_ledsetting(padapter); +#endif /* CONFIG_RTW_LED */ + ret = _SUCCESS; exit: @@ -284,12 +321,9 @@ void rtl8822bu_set_hal_ops(PADAPTER padapter) ops->init_recv_priv = rtl8822bu_init_recv_priv; ops->free_recv_priv = rtl8822bu_free_recv_priv; -#ifdef CONFIG_SW_LED +#ifdef CONFIG_RTW_SW_LED ops->InitSwLeds = rtl8822bu_initswleds; ops->DeInitSwLeds = rtl8822bu_deinitswleds; -#else - ops->InitSwLeds = NULL; - ops->DeInitSwLeds = NULL; #endif ops->init_default_value = rtl8822bu_init_default_value; diff --git a/hal/rtl8822b/usb/rtl8822bu_recv.c b/hal/rtl8822b/usb/rtl8822bu_recv.c index 983ff99..e889b96 100644 --- a/hal/rtl8822b/usb/rtl8822bu_recv.c +++ b/hal/rtl8822b/usb/rtl8822bu_recv.c @@ -44,12 +44,14 @@ static u8 recvbuf2recvframe_proccess_normal_rx (PADAPTER padapter, u8 *pbuf, struct rx_pkt_attrib *pattrib, union recv_frame *precvframe, _pkt *pskb) { u8 ret = _SUCCESS; - u8 *pphy_status = NULL; struct recv_priv *precvpriv = &padapter->recvpriv; _queue *pfree_recv_queue = &precvpriv->free_recv_queue; #ifdef CONFIG_RX_PACKET_APPEND_FCS - pattrib->pkt_len -= IEEE80211_FCS_LEN; + if (check_fwstate(&padapter->mlmepriv, WIFI_MONITOR_STATE) == _FALSE) { + if (rtl8822b_rx_fcs_appended(padapter)) + pattrib->pkt_len -= IEEE80211_FCS_LEN; + } #endif if (rtw_os_alloc_recvframe(padapter, precvframe, @@ -62,17 +64,7 @@ static u8 recvbuf2recvframe_proccess_normal_rx recvframe_put(precvframe, pattrib->pkt_len); - if (pattrib->physt) - pphy_status = (pbuf + RXDESC_OFFSET); - -#ifdef CONFIG_CONCURRENT_MODE - pre_recv_entry(precvframe, pphy_status); -#endif /* CONFIG_CONCURRENT_MODE */ - - if (pattrib->physt && pphy_status) - rx_query_phy_status(precvframe, pphy_status); - - rtw_recv_entry(precvframe); + pre_recv_entry(precvframe, pattrib->physt ? (pbuf + RXDESC_OFFSET) : NULL); exit: return ret; diff --git a/hal/rtl8822b/usb/rtl8822bu_xmit.c b/hal/rtl8822b/usb/rtl8822bu_xmit.c index 5e13abb..d2a9c9f 100644 --- a/hal/rtl8822b/usb/rtl8822bu_xmit.c +++ b/hal/rtl8822b/usb/rtl8822bu_xmit.c @@ -27,7 +27,7 @@ static void update_txdesc_h2c_pkt(struct xmit_frame *pxmitframe, u8 *pmem, s32 s _rtw_memset(ptxdesc, 0, TXDESC_SIZE); SET_TX_DESC_TXPKTSIZE_8822B(ptxdesc, sz); - SET_TX_DESC_QSEL_8822B(ptxdesc, HALMAC_QUEUE_SELECT_CMD); + SET_TX_DESC_QSEL_8822B(ptxdesc, HALMAC_TXDESC_QSEL_H2C_CMD); rtl8822b_cal_txdesc_chksum(padapter, ptxdesc); rtl8822b_dbg_dump_tx_desc(padapter, pxmitframe->frame_tag, ptxdesc); } @@ -147,12 +147,14 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bag rtl8822b_fill_txdesc_phy(padapter, pattrib, ptxdesc); /* compatibility for MCC consideration, use pmlmeext->cur_channel */ - if (pmlmeext->cur_channel > 14) - /* for 5G. OFDM 6M */ - SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(ptxdesc, 4); - else - /* for 2.4G. CCK 1M */ - SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(ptxdesc, 0); + if (!bmcst) { + if (pmlmeext->cur_channel > 14) + /* for 5G. OFDM 6M */ + SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(ptxdesc, 4); + else + /* for 2.4G. CCK 1M */ + SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(ptxdesc, 0); + } if (pHalData->fw_ractrl == _FALSE) { SET_TX_DESC_USE_RATE_8822B(ptxdesc, 1); @@ -163,6 +165,10 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bag SET_TX_DESC_DATARATE_8822B(ptxdesc, (pHalData->INIDATA_RATE[pattrib->mac_id] & 0x7F)); } + if (bmcst) { + DriverFixedRate = 0x01; + rtl8822b_fill_txdesc_bmc_tx_rate(pattrib, ptxdesc); + } /* modify data rate by iwpriv or proc */ if (padapter->fix_rate != 0xFF) { @@ -184,6 +190,11 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bag if (pattrib->stbc) SET_TX_DESC_DATA_STBC_8822B(ptxdesc, 1); +#ifdef CONFIG_WMMPS_STA + if (pattrib->trigger_frame) + SET_TX_DESC_TRI_FRAME_8822B (ptxdesc, 1); +#endif /* CONFIG_WMMPS_STA */ + } else { /* EAP data packet and ARP packet and DHCP. @@ -202,6 +213,17 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bag SET_TX_DESC_DATARATE_8822B(ptxdesc, MRateToHwRate(pmlmeext->tx_rate)); } +#ifdef CONFIG_TDLS +#ifdef CONFIG_XMIT_ACK + /* CCX-TXRPT ack for xmit data frames */ + if (pxmitframe->ack_report) { + SET_TX_DESC_SPE_RPT_8822B(ptxdesc, 1); +#ifdef DBG_CCX + RTW_INFO("%s set tx report\n", __func__); +#endif + } +#endif /* CONFIG_XMIT_ACK */ +#endif } else if ((pxmitframe->frame_tag & 0x0f) == MGNT_FRAMETAG) { /* RTW_INFO("pxmitframe->frame_tag == MGNT_FRAMETAG\n"); */ @@ -387,7 +409,7 @@ static s32 rtw_dump_xframe(PADAPTER padapter, struct xmit_frame *pxmitframe) pxmitbuf->len = w_sz; pxmitbuf->ff_hwaddr = ff_hwaddr; - if (pxmitbuf->buf_tag == XMITBUF_CMD) + if ((pattrib->qsel == QSLT_BEACON) || (pattrib->qsel == QSLT_CMD)) /* download rsvd page or fw */ inner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz, (unsigned char *)pxmitbuf); else @@ -414,24 +436,6 @@ static s32 rtw_dump_xframe(PADAPTER padapter, struct xmit_frame *pxmitframe) } #ifdef CONFIG_USB_TX_AGGREGATION -static u32 xmitframe_need_length(struct xmit_frame *pxmitframe) -{ - struct pkt_attrib *pattrib = &pxmitframe->attrib; - - u32 len = 0; - - /* no consider fragement */ - len = pattrib->hdrlen + pattrib->iv_len + - SNAP_SIZE + sizeof(u16) + - pattrib->pktlen + - ((pattrib->bswenc) ? pattrib->icv_len : 0); - - if (pattrib->encrypt == _TKIP_) - len += 8; - - return len; -} - #define IDEA_CONDITION 1 /* check all packets before enqueue */ static s32 rtl8822bu_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) { @@ -526,7 +530,7 @@ static s32 rtl8822bu_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxm /* 2. aggregate same priority and same DA(AP or STA) frames */ pfirstframe = pxmitframe; - len = xmitframe_need_length(pfirstframe) + TXDESC_SIZE + (pfirstframe->pkt_offset * PACKET_OFFSET_SZ); + len = rtw_wlan_pkt_size(pfirstframe) + TXDESC_SIZE + (pfirstframe->pkt_offset * PACKET_OFFSET_SZ); pbuf_tail = len; pbuf = _RND8(pbuf_tail); @@ -598,7 +602,7 @@ static s32 rtl8822bu_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxm pxmitframe->pkt_offset = 0; /* not first frame of aggregation, no need to reserve offset */ #endif - len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ); + len = rtw_wlan_pkt_size(pxmitframe) + TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ); if (_RND8(pbuf + len) > MAX_XMITBUF_SZ) { /* RTW_INFO("%s: len> MAX_XMITBUF_SZ\n", __func__); */ diff --git a/include/.osdep_service_linux.h.swp b/include/.osdep_service_linux.h.swp deleted file mode 100644 index 47dcb930ebdb6e18b89712fb4b0f5b80f243ca7c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 16384 zcmeI2TWlj&8ONuvKm!!2QV>ucP7`*OxJjINx4T=i4RRbivDUGz@i-T0tE2JEaeS2V z%rKXvfdyW;2?;7LF9jjdA_1yES`d{$NOYx@03q>0d0}6uc%XteUMkp!!vD-Aj_onK zi1LDtm7naK%Xhx-f6n=4=GdL3?dle}ytt&`^`N5MdG+Sr`=?E1|H4T9>q-6fr2K4RAhq-6r2OIJ{kf6)q*%U51*8H}0jYpg zKq?>=kP1izqyka_sen{KD)2v0KsOcTG1xW40RX=LPoMv9yjxLz2(E);un7M0E=Bn{ z_$lCkfZso$D7U~(;DQEN1PkCH@Y*{S);yL1}oqKI1e5He}0>y{0h7TUI5<#&x0?5KIj4lRImsZz~A4B*ul%-ci=_v z6>tbzKm|+S1K>Vz=Pioz4{#g&4167Y4fx<1Xafzbf^*<+XP`g$Ew}-`51s?x2G;=t z4R8q%a0cAQLChb(E%0670u5XMkAWHRA@B%z1#9Au;6?BgU;?pDI^aKf%`l61$!x7! zZ|~CWvf8RP>a^5YFOw_eYFVw9Yia3hVgBNL;fXnN?i?{$m)p#oEj8+u>IPM{9a=9o zt8;Uhz!~Owjz^};w%)NA5#^-Ax{k*Pi;FhY#x;8y@nGZ(OQ?r=~EUle`A3ab&Q~QWcR$UXy$-bz@C~=;hsNOQWqu>1tV{nz~DJ zdErz1`x|m4`pHe+W&u7NEcRB%>$sg+9GdP(IgI23BdgSRjL7z|7@znA)5%mNpRG zhn*NUpN>Bs*l8wWAgy{sqdIf_?zrS zxHOzLcB*Q*R&HT(ceRnA>e!xYalP6&)%j%M>wZ7aok*=gZaS%rr_0s%naBFEPm{Aw zcG6iENheWR)vnU@ttM^Oidvr@56yyq3-hhSgQ#;aeNNW&y!2@ zWGR}0G%1h78+>?En|D&=uCEux@YxOEY|+`v(>aXp-=wML%rPWR`xM<%SoW%HLx{ zcB$@-I3w1wZknFq*xg}+(JDWpJ>51f<_*`yAslg!S1>vBLfVDl%(udlXETcc>DJYv6xkx9?IcaB(G$a_R)N z4?LC(o_z~9zF7Hi%dbvsCTiRAx-L96(bd!plX^We&i492Z zjeO-5lEWV^G`RCMS)g;vUlawEs#eE^g&<**B54*?ty*f=iYmb^W3$mJFOn8x1pAY0 z)Z1i(+04@|(hNHmH%JW|*7li5N5WRIzDIV7s#>gTdn@FK2R$bY2s>nUWPtZwi!+lP z>7J+C!7*{VWUH)}HqpMgR;^XFJrWzzdfX?j=j?lWpWvg3JnHdI7@#+gjrAN?xTOb# z2N=q-a9dA8pLIiPo}eY!scM^zwwA>03Wt595z;x1oT+#StL1b9c*97=32jpk#O#Sc z@DKB%W=OkzUpRUgPcA8lf9@iO?h7NML3G84elp?;Id(!~=r-}#AUY8XGH5=&BjDX* z6eIzZ9QWAc`@LY+m?MRyrAuT1Z_Ag6%5*DW2c+b9uH&7=pyc1k<&(=P;`#rBcuxNu z5YPYV_w#?n^Zu{Fj{yS}@Lup5p83B4o&|?MoCE9t4ZIE;FM(fxXTX=imw>SSSs-6h z0jYpgKq?>=kP1izqyka_sen{KDv+Gw;uJDDAZ}@DyQI-(5#Q6S<1|4Jk|$+K$?UAF z8wbo3rdMzxRLn$F1*sg48WcsW>d)A+u9version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE) -#endif #define IS_VENDOR_8812A_TEST_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE) #define IS_VENDOR_8812A_MP_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE) #define IS_VENDOR_8812A_C_CUT(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE) diff --git a/include/autoconf.h b/include/autoconf.h index f0f42df..6eca5ac 100644 --- a/include/autoconf.h +++ b/include/autoconf.h @@ -38,7 +38,7 @@ #ifdef CONFIG_80211N_HT #define CONFIG_80211AC_VHT 1 - /* #define CONFIG_BEAMFORMING */ + #define CONFIG_BEAMFORMING #endif /* set CONFIG_IOCTL_CFG80211 from Makefile */ @@ -76,17 +76,12 @@ #define CONFIG_RECV_REORDERING_CTRL 1 -/* #define CONFIG_TCP_CSUM_OFFLOAD_RX 1 */ - -/* #define CONFIG_DRVEXT_MODULE 1 */ - - /* #define CONFIG_SUPPORT_USB_INT */ #ifdef CONFIG_SUPPORT_USB_INT /* #define CONFIG_USB_INTERRUPT_IN_PIPE 1 */ #endif /* CONFIG_SUPPORT_USB_INT */ -/* #ifndef CONFIG_MP_INCLUDED */ +#ifdef CONFIG_POWER_SAVING /* #define CONFIG_IPS 1 */ #ifdef CONFIG_IPS /* #define CONFIG_IPS_LEVEL_2 1*/ /*enable this to set default IPS mode to IPS_LEVEL_2*/ @@ -111,6 +106,10 @@ /* #define DBG_CHECK_FW_PS_STATE */ #endif /* CONFIG_LPS_LCLK */ + #ifdef CONFIG_LPS + #define CONFIG_WMMPS_STA 1 + #endif /* CONFIG_LPS */ +#endif /*CONFIG_POWER_SAVING*/ /* before link */ /* #define CONFIG_ANTENNA_DIVERSITY */ @@ -120,19 +119,6 @@ #endif - /*#define CONFIG_CONCURRENT_MODE 1 */ - #ifdef CONFIG_CONCURRENT_MODE - /* #define CONFIG_HWPORT_SWAP */ /* Port0->Sec , Port1->Pri */ - /*#define CONFIG_RUNTIME_PORT_SWITCH*/ - /* #define DBG_RUNTIME_PORT_SWITCH */ - #define CONFIG_SCAN_BACKOP - #if 0 - #ifdef CONFIG_RTL8812A - #define CONFIG_TSF_RESET_OFFLOAD 1 /* For 2 PORT TSF SYNC. */ - #endif - #endif - #endif - /*#else*/ /* CONFIG_MP_INCLUDED */ /*#endif*/ /* CONFIG_MP_INCLUDED */ @@ -168,7 +154,7 @@ /* #define CONFIG_P2P_IPS */ #define CONFIG_P2P_OP_CHK_SOCIAL_CH #define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT /* replace CONFIG_P2P_CHK_INVITE_CH_LIST flag */ - #define CONFIG_P2P_INVITE_IOT + /*#define CONFIG_P2P_INVITE_IOT*/ #endif /* Added by Kurt 20110511 */ @@ -187,17 +173,19 @@ #define CONFIG_SKB_COPY 1 /* amsdu */ -#define CONFIG_LED -#ifdef CONFIG_LED - #define CONFIG_SW_LED - #ifdef CONFIG_SW_LED - /* #define CONFIG_LED_HANDLED_BY_CMD_THREAD */ +#define CONFIG_RTW_LED +#ifdef CONFIG_RTW_LED + #define CONFIG_RTW_SW_LED + #ifdef CONFIG_RTW_SW_LED + /* #define CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD */ #endif -#endif /* CONFIG_LED */ +#endif /* CONFIG_RTW_LED */ #define USB_INTERFERENCE_ISSUE /* this should be checked in all usb interface */ #define CONFIG_GLOBAL_UI_PID +/*#define CONFIG_RTW_80211K*/ + #define CONFIG_LAYER2_ROAMING #define CONFIG_LAYER2_ROAMING_RESUME /*#define CONFIG_ADAPTOR_INFO_CACHING_FILE */ /* now just applied on 8192cu only, should make it general... */ @@ -286,22 +274,6 @@ /* * Platform Related Config */ -#ifdef CONFIG_PLATFORM_MN10300 - #define CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - #define CONFIG_USE_USB_BUFFER_ALLOC_RX - - #if defined(CONFIG_SW_ANTENNA_DIVERSITY) - #undef CONFIG_SW_ANTENNA_DIVERSITY - #define CONFIG_HW_ANTENNA_DIVERSITY - #endif - - #if defined(CONFIG_POWER_SAVING) - #undef CONFIG_POWER_SAVING - #endif - -#endif /* CONFIG_PLATFORM_MN10300 */ - - #if defined(CONFIG_PLATFORM_ACTIONS_ATM702X) #ifdef CONFIG_USB_TX_AGGREGATION #undef CONFIG_USB_TX_AGGREGATION @@ -329,8 +301,6 @@ #define RTL8188E_EARLY_MODE_PKT_NUM_10 0 -#define CONFIG_80211D - #define CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR /* @@ -370,3 +340,5 @@ #define DBG_MEMORY_LEAK 1 */ + +/*#define DBG_FW_DEBUG_MSG_PKT*/ /* FW use this feature to tx debug broadcast pkt. This pkt include FW debug message*/ diff --git a/include/basic_types.h b/include/basic_types.h index 1c65aa7..c0737f5 100644 --- a/include/basic_types.h +++ b/include/basic_types.h @@ -95,9 +95,14 @@ #define UINT u32 #define ULONG u32 - #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) - typedef _Bool bool; - #endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) +typedef _Bool bool; + +enum { + false = 0, + true = 1 +}; +#endif typedef void (*proc_t)(void *); @@ -105,6 +110,36 @@ typedef __kernel_ssize_t SSIZE_T; #define FIELD_OFFSET(s, field) ((SSIZE_T)&((s *)(0))->field) +#define u1Byte u8 +#define pu1Byte u8* + +#define u2Byte u16 +#define pu2Byte u16* + +#define u4Byte u32 +#define pu4Byte u32* + +#define u8Byte u64 +#define pu8Byte u64* + +#define s1Byte s8 +#define ps1Byte s8* + +#define s2Byte s16 +#define ps2Byte s16* + +#define s4Byte s32 +#define ps4Byte s32* + +#define s8Byte s64 +#define ps8Byte s64* + +#define UCHAR u8 +#define USHORT u16 +#define UINT u32 +#define ULONG u32 +#define PULONG u32* + #endif diff --git a/include/drv_conf.h b/include/drv_conf.h index cf43fab..cc00167 100644 --- a/include/drv_conf.h +++ b/include/drv_conf.h @@ -23,6 +23,26 @@ #endif +#ifdef CONFIG_RTW_REPEATER_SON + #ifndef CONFIG_AP + #define CONFIG_AP + #endif + #ifndef CONFIG_CONCURRENT_MODE + #define CONFIG_CONCURRENT_MODE + #endif + #ifndef CONFIG_BR_EXT + #define CONFIG_BR_EXT + #endif + #ifndef CONFIG_RTW_REPEATER_SON_ID + #define CONFIG_RTW_REPEATER_SON_ID 0x02040608 + #endif + //#define CONFIG_RTW_REPEATER_SON_ROOT + #ifndef CONFIG_RTW_REPEATER_SON_ROOT + #define CONFIG_LAYER2_ROAMING_ACTIVE + #endif + #undef CONFIG_POWER_SAVING +#endif + #if defined(CONFIG_MCC_MODE) && (!defined(CONFIG_CONCURRENT_MODE)) #error "Enable CONCURRENT_MODE before enable MCC MODE\n" @@ -100,6 +120,37 @@ #undef CONFIG_DFS_MASTER #endif +#ifdef CONFIG_RTW_MESH + #ifndef CONFIG_RTW_MESH_OFFCH_CAND + #define CONFIG_RTW_MESH_OFFCH_CAND 1 + #endif + + #ifndef CONFIG_RTW_MESH_PEER_BLACKLIST + #define CONFIG_RTW_MESH_PEER_BLACKLIST 1 + #endif + + #ifndef CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + #define CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST 1 + #endif + + #ifndef CONFIG_RTW_MPM_TX_IES_SYNC_BSS + #define CONFIG_RTW_MPM_TX_IES_SYNC_BSS 1 + #endif + #if CONFIG_RTW_MPM_TX_IES_SYNC_BSS + #ifndef CONFIG_RTW_MESH_AEK + #define CONFIG_RTW_MESH_AEK + #endif + #endif + + #ifndef CONFIG_RTW_MESH_DATA_BMC_TO_UC + #define CONFIG_RTW_MESH_DATA_BMC_TO_UC 1 + #endif +#endif + +#if !defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) +#define CONFIG_SCAN_BACKOP +#endif + #define RTW_SCAN_SPARSE_MIRACAST 1 #define RTW_SCAN_SPARSE_BG 0 #define RTW_SCAN_SPARSE_ROAMING_ACTIVE 1 @@ -108,10 +159,6 @@ #define CONFIG_RTW_HIQ_FILTER 1 #endif -#ifndef CONFIG_RTW_FORCE_IGI_LB - #define CONFIG_RTW_FORCE_IGI_LB 0 -#endif - #ifndef CONFIG_RTW_ADAPTIVITY_EN #define CONFIG_RTW_ADAPTIVITY_EN 0 #endif @@ -151,6 +198,10 @@ #define CONFIG_TXPWR_LIMIT_EN 2 /* by efuse */ #endif +#ifndef CONFIG_RTW_CHPLAN +#define CONFIG_RTW_CHPLAN 0xFF /* RTW_CHPLAN_UNSPECIFIED */ +#endif + /* compatible with old fashion configuration */ #if defined(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY) #undef CONFIG_TXPWR_BY_RATE_EN @@ -180,6 +231,15 @@ #define CONFIG_TXPWR_LIMIT #endif +#ifdef CONFIG_RTW_IPCAM_APPLICATION + #undef CONFIG_TXPWR_BY_RATE_EN + #define CONFIG_TXPWR_BY_RATE_EN 1 + #define CONFIG_RTW_CUSTOMIZE_BEEDCA 0x0000431C + #define CONFIG_RTW_CUSTOMIZE_BWMODE 0x00 + #define CONFIG_RTW_CUSTOMIZE_RLSTA 0x7 +#endif + + #ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS #define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS {0xFF, 0xFF, 0xFF, 0xFF} #endif @@ -322,4 +382,33 @@ #define RTW_RX_AGGREGATION #endif /* CONFIG_SDIO_HCI || CONFIG_USB_RX_AGGREGATION */ +#ifdef CONFIG_RTW_HOSTAPD_ACS + #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) + #ifndef CONFIG_FIND_BEST_CHANNEL + #define CONFIG_FIND_BEST_CHANNEL + #endif + #else + #ifdef CONFIG_FIND_BEST_CHANNEL + #undef CONFIG_FIND_BEST_CHANNEL + #endif + #ifndef CONFIG_RTW_ACS + #define CONFIG_RTW_ACS + #endif + #ifndef CONFIG_BACKGROUND_NOISE_MONITOR + #define CONFIG_BACKGROUND_NOISE_MONITOR + #endif + #endif +#endif + +#ifdef CONFIG_RTW_80211K + #ifndef CONFIG_RTW_ACS + #define CONFIG_RTW_ACS + #endif +#endif /*CONFIG_RTW_80211K*/ + +#ifdef DBG_CONFIG_ERROR_RESET +#ifndef CONFIG_IPS +#define CONFIG_IPS +#endif +#endif #endif /* __DRV_CONF_H__ */ diff --git a/include/drv_types.h b/include/drv_types.h index b6d71e3..37f8fc7 100644 --- a/include/drv_types.h +++ b/include/drv_types.h @@ -58,6 +58,7 @@ enum _NIC_VERSION { typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include +#include #include #ifdef CONFIG_80211N_HT @@ -78,6 +79,7 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include #include #include +#include #ifdef CONFIG_BEAMFORMING #include @@ -107,6 +109,9 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include #include #include +#ifdef CONFIG_RTW_MESH +#include "../core/mesh/rtw_mesh.h" +#endif #include #include #include @@ -125,10 +130,6 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include #endif /* CONFIG_WAPI_SUPPORT */ -#ifdef CONFIG_DRVEXT_MODULE - #include -#endif /* CONFIG_DRVEXT_MODULE */ - #ifdef CONFIG_MP_INCLUDED #include #endif /* CONFIG_MP_INCLUDED */ @@ -149,14 +150,16 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include #include -#ifdef CONFIG_BT_COEXIST - #include -#endif /* CONFIG_BT_COEXIST */ +#include #ifdef CONFIG_MCC_MODE #include #endif /*CONFIG_MCC_MODE */ +#ifdef CONFIG_RTW_REPEATER_SON + #include +#endif /*CONFIG_RTW_REPEATER_SON */ + #define SPEC_DEV_ID_NONE BIT(0) #define SPEC_DEV_ID_DISABLE_HT BIT(1) #define SPEC_DEV_ID_ENABLE_PS BIT(2) @@ -195,6 +198,9 @@ struct registry_priv { u8 ips_mode; u8 lps_level; u8 smart_ps; +#ifdef CONFIG_WMMPS_STA + u8 wmm_smart_ps; +#endif /* CONFIG_WMMPS_STA */ u8 usb_rxagg_mode; u8 dynamic_agg_enable; u8 long_retry_lmt; @@ -212,19 +218,21 @@ struct registry_priv { u8 early_mode; #endif u8 acm_method; - /* UAPSD */ + /* WMM */ u8 wmm_enable; - u8 uapsd_enable; - u8 uapsd_max_sp; - u8 uapsd_acbk_en; - u8 uapsd_acbe_en; - u8 uapsd_acvi_en; - u8 uapsd_acvo_en; +#ifdef CONFIG_WMMPS_STA + /* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */ + u8 uapsd_max_sp_len; + /* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */ + u8 uapsd_ac_enable; +#endif /* CONFIG_WMMPS_STA */ WLAN_BSSID_EX dev_network; u8 tx_bw_mode; - +#ifdef CONFIG_AP_MODE + u8 bmc_tx_rate; +#endif #ifdef CONFIG_80211N_HT u8 ht_enable; /* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz */ @@ -233,7 +241,8 @@ struct registry_priv { u8 bw_mode; u8 ampdu_enable;/* for tx */ u8 rx_stbc; - u8 ampdu_amsdu;/* A-MPDU Supports A-MSDU is permitted */ + u8 rx_ampdu_amsdu;/* Rx A-MPDU Supports A-MSDU is permitted */ + u8 tx_ampdu_amsdu;/* Tx A-MPDU Supports A-MSDU is permitted */ u8 rx_ampdu_sz_limit_by_nss_bw[4][4]; /* 1~4SS, BW20~BW160 */ /* Short GI support Bit Map */ /* BIT0 - 20MHz, 1: support, 0: non-support */ @@ -282,6 +291,7 @@ struct registry_priv { u8 bt_sco; u8 bt_ampdu; u8 ant_num; + u8 single_ant_path; #endif BOOLEAN bAcceptAddbaReq; @@ -318,13 +328,6 @@ struct registry_priv { u8 notch_filter; -#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - u8 force_ant;/* 0 normal,1 main,2 aux */ - u8 force_igi;/* 0 normal */ -#endif - - u8 force_igi_lb; - /* for pll reference clock selction */ u8 pll_ref_clk_sel; @@ -370,9 +373,13 @@ struct registry_priv { u8 boffefusemask; BOOLEAN bFileMaskEfuse; -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - u8 acs_mode; +#ifdef CONFIG_RTW_ACS u8 acs_auto_scan; + u8 acs_mode; +#endif + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + u8 nm_mode; #endif u32 reg_rxgain_offset_2g; u32 reg_rxgain_offset_5gl; @@ -394,21 +401,23 @@ struct registry_priv { u32 rtw_mcc_sta_bw80_target_tx_tp; s8 rtw_mcc_policy_table_idx; u8 rtw_mcc_duration; - u8 rtw_mcc_tsf_sync_offset; - u8 rtw_mcc_start_time_offset; - u8 rtw_mcc_interval; - s8 rtw_mcc_guard_offset0; - s8 rtw_mcc_guard_offset1; + u8 rtw_mcc_enable_runtime_duration; #endif /* CONFIG_MCC_MODE */ #ifdef CONFIG_RTW_NAPI u8 en_napi; +#ifdef CONFIG_RTW_NAPI_DYNAMIC + u32 napi_threshold; /* unit: Mbps */ +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ #ifdef CONFIG_RTW_GRO u8 en_gro; #endif /* CONFIG_RTW_GRO */ #endif /* CONFIG_RTW_NAPI */ - bool default_patterns_en; +#ifdef CONFIG_WOWLAN + u8 wakeup_event; +#endif + #ifdef CONFIG_SUPPORT_TRX_SHARED u8 trx_share_mode; #endif @@ -417,6 +426,26 @@ struct registry_priv { u32 pci_aspm_config; u8 iqk_fw_offload; + u8 ch_switch_offload; + +#ifdef CONFIG_TDLS + u8 en_tdls; +#endif + +#ifdef CONFIG_ADVANCE_OTA + u8 adv_ota; +#endif + +#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT + u8 fw_param_init; +#endif +#ifdef CONFIG_DYNAMIC_SOML + u8 dyn_soml_en; + u8 dyn_soml_train_num; + u8 dyn_soml_interval; + u8 dyn_soml_period; + u8 dyn_soml_delay; +#endif }; /* For registry parameters */ @@ -649,15 +678,10 @@ struct debug_priv { u32 dbg_rpwm_toogle_cnt; u32 dbg_rpwm_timeout_fail_cnt; u32 dbg_sreset_cnt; + u32 dbg_fw_mem_dl_error_cnt; u64 dbg_rx_fifo_last_overflow; u64 dbg_rx_fifo_curr_overflow; u64 dbg_rx_fifo_diff_overflow; - u64 dbg_rx_ampdu_drop_count; - u64 dbg_rx_ampdu_forced_indicate_count; - u64 dbg_rx_ampdu_loss_count; - u64 dbg_rx_dup_mgt_frame_drop_count; - u64 dbg_rx_ampdu_window_shift_cnt; - u64 dbg_rx_conflic_mac_addr_cnt; }; struct rtw_traffic_statistics { @@ -718,6 +742,8 @@ struct sec_cam_ent { ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \ ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] +#define RTW_DEFAULT_MGMT_MACID 1 + struct macid_bmp { u32 m0; #if (MACID_NUM_SW_LIMIT > 32) @@ -737,14 +763,29 @@ struct macid_ctl_t { struct macid_bmp used; struct macid_bmp bmc; struct macid_bmp if_g[CONFIG_IFACE_NUMBER]; - u8 iface_bmc[CONFIG_IFACE_NUMBER];/*for bc-sta of AP or Adhoc mode*/ struct macid_bmp ch_g[2]; /* 2 ch concurrency */ + + u8 iface_bmc[CONFIG_IFACE_NUMBER]; /* bmc TX macid for each iface*/ + u8 h2c_msr[MACID_NUM_SW_LIMIT]; u8 bw[MACID_NUM_SW_LIMIT]; u8 vht_en[MACID_NUM_SW_LIMIT]; u32 rate_bmp0[MACID_NUM_SW_LIMIT]; u32 rate_bmp1[MACID_NUM_SW_LIMIT]; - struct sta_info *sta[MACID_NUM_SW_LIMIT]; + + struct sta_info *sta[MACID_NUM_SW_LIMIT]; /* corresponding stainfo when macid is not shared */ + + /* macid sleep registers */ + u16 reg_sleep_m0; +#if (MACID_NUM_SW_LIMIT > 32) + u16 reg_sleep_m1; +#endif +#if (MACID_NUM_SW_LIMIT > 64) + u16 reg_sleep_m2; +#endif +#if (MACID_NUM_SW_LIMIT > 96) + u16 reg_sleep_m3; +#endif }; /* used for rf_ctl_t.rate_bmp_cck_ofdm */ @@ -792,6 +833,11 @@ struct macid_ctl_t { #define TXPWR_LMT_HAS_OFDM_3T BIT6 #define TXPWR_LMT_HAS_OFDM_4T BIT7 +#define OFFCHS_NONE 0 +#define OFFCHS_LEAVING_OP 1 +#define OFFCHS_LEAVE_OP 2 +#define OFFCHS_BACKING_OP 3 + struct rf_ctl_t { const struct country_chplan *country_ent; u8 ChannelPlan; @@ -799,6 +845,9 @@ struct rf_ctl_t { RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM]; struct p2p_channels channel_list; + _mutex offch_mutex; + u8 offch_state; + /* used for debug or by tx power limit */ u16 rate_bmp_cck_ofdm; /* 20MHz */ u32 rate_bmp_ht_by_bw[2]; /* 20MHz, 40MHz. 4SS supported */ @@ -823,6 +872,8 @@ struct rf_ctl_t { #endif #endif + u8 ch_sel_same_band_prefer; + #ifdef CONFIG_DFS_MASTER bool radar_detect_by_others; u8 dfs_master_enabled; @@ -832,8 +883,9 @@ struct rf_ctl_t { u8 radar_detect_bw; u8 radar_detect_offset; - u32 cac_start_time; - u32 cac_end_time; + systime cac_start_time; + systime cac_end_time; + u8 cac_force_stop; u8 dfs_ch_sel_d_flags; @@ -844,9 +896,15 @@ struct rf_ctl_t { }; #define RTW_CAC_STOPPED 0 +#ifdef CONFIG_DFS_MASTER #define IS_CAC_STOPPED(rfctl) ((rfctl)->cac_end_time == RTW_CAC_STOPPED) -#define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && time_after((unsigned long)(rfctl)->cac_end_time, (unsigned long)rtw_get_current_time())) -#define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && time_after((unsigned long)rtw_get_current_time(), (unsigned long)(rfctl)->cac_start_time)) +#define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && rtw_time_after((rfctl)->cac_end_time, rtw_get_current_time())) +#define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && rtw_time_after(rtw_get_current_time(), (rfctl)->cac_start_time)) +#else +#define IS_CAC_STOPPED(rfctl) 1 +#define IS_CH_WAITING(rfctl) 0 +#define IS_UNDER_CAC(rfctl) 0 +#endif /* CONFIG_DFS_MASTER */ #ifdef CONFIG_MBSSID_CAM #define TOTAL_MBID_CAM_NUM 8 @@ -918,7 +976,7 @@ struct dvobj_priv { unsigned char oper_channel; /* saved channel info when call set_channel_bw */ unsigned char oper_bwmode; unsigned char oper_ch_offset;/* PRIME_CHNL_OFFSET */ - u32 on_oper_ch_time; + systime on_oper_ch_time; _adapter *padapters[CONFIG_IFACE_NUMBER];/*IFACE_ID_MAX*/ u8 iface_nums; /* total number of ifaces used runtime */ @@ -926,8 +984,12 @@ struct dvobj_priv { #ifdef CONFIG_AP_MODE u8 nr_ap_if; /* total interface s number of ap/go mode. */ - u32 inter_bcn_space; /* unit:ms */ + u16 inter_bcn_space; /* unit:ms */ _queue ap_if_q; +#ifdef CONFIG_RTW_REPEATER_SON + struct rtw_rson_struct rson_data; +#endif + #endif struct macid_ctl_t macid_ctl; @@ -975,6 +1037,10 @@ struct dvobj_priv { _timer txbcn_timer; #endif _timer dynamic_chk_timer; /* dynamic/periodic check timer */ + +#ifdef CONFIG_RTW_NAPI_DYNAMIC + u8 en_napi_dynamic; +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ #ifdef RTW_HALMAC void *halmac; @@ -1111,10 +1177,15 @@ struct dvobj_priv { #define DEV_STA_NUM(_dvobj) MSTATE_STA_NUM(&((_dvobj)->iface_state)) #define DEV_STA_LD_NUM(_dvobj) MSTATE_STA_LD_NUM(&((_dvobj)->iface_state)) #define DEV_STA_LG_NUM(_dvobj) MSTATE_STA_LG_NUM(&((_dvobj)->iface_state)) +#define DEV_TDLS_LD_NUM(_dvobj) MSTATE_TDLS_LD_NUM(&((_dvobj)->iface_state)) #define DEV_AP_NUM(_dvobj) MSTATE_AP_NUM(&((_dvobj)->iface_state)) +#define DEV_AP_STARTING_NUM(_dvobj) MSTATE_AP_STARTING_NUM(&((_dvobj)->iface_state)) #define DEV_AP_LD_NUM(_dvobj) MSTATE_AP_LD_NUM(&((_dvobj)->iface_state)) #define DEV_ADHOC_NUM(_dvobj) MSTATE_ADHOC_NUM(&((_dvobj)->iface_state)) #define DEV_ADHOC_LD_NUM(_dvobj) MSTATE_ADHOC_LD_NUM(&((_dvobj)->iface_state)) +#define DEV_MESH_NUM(_dvobj) MSTATE_MESH_NUM(&((_dvobj)->iface_state)) +#define DEV_MESH_LD_NUM(_dvobj) MSTATE_MESH_LD_NUM(&((_dvobj)->iface_state)) +#define DEV_SCAN_NUM(_dvobj) MSTATE_SCAN_NUM(&((_dvobj)->iface_state)) #define DEV_WPS_NUM(_dvobj) MSTATE_WPS_NUM(&((_dvobj)->iface_state)) #define DEV_ROCH_NUM(_dvobj) MSTATE_ROCH_NUM(&((_dvobj)->iface_state)) #define DEV_MGMT_TX_NUM(_dvobj) MSTATE_MGMT_TX_NUM(&((_dvobj)->iface_state)) @@ -1255,6 +1326,10 @@ struct _ADAPTER { struct mlme_ext_priv mlmeextpriv; struct cmd_priv cmdpriv; struct evt_priv evtpriv; + +#ifdef CONFIG_RTW_80211K + struct rm_priv rmpriv; +#endif /* struct io_queue *pio_queue; */ struct io_priv iopriv; struct xmit_priv xmitpriv; @@ -1264,11 +1339,6 @@ struct _ADAPTER { _lock security_key_mutex; /* add for CONFIG_IEEE80211W, none 11w also can use */ struct registry_priv registrypriv; - struct led_priv ledpriv; -#ifdef CONFIG_CHNL_LOAD_MAGT - BOOLEAN clm_flag; -#endif - #ifdef CONFIG_RTW_NAPI struct napi_struct napi; u8 napi_state; @@ -1278,10 +1348,6 @@ struct _ADAPTER { struct mp_priv mppriv; #endif -#ifdef CONFIG_DRVEXT_MODULE - struct drvext_priv drvextpriv; -#endif - #ifdef CONFIG_AP_MODE struct hostapd_priv *phostapdpriv; #endif @@ -1307,6 +1373,9 @@ struct _ADAPTER { RT_WAPI_T wapiInfo; #endif +#ifdef CONFIG_RTW_REPEATER_SON + u8 rtw_rson_scanstage; +#endif #ifdef CONFIG_WFD struct wifi_display_info wfd_info; @@ -1338,22 +1407,21 @@ struct _ADAPTER { } gpiointpriv; #endif _thread_hdl_ cmdThread; +#ifdef CONFIG_EVENT_THREAD_MODE _thread_hdl_ evtThread; +#endif +#ifdef CONFIG_XMIT_THREAD_MODE _thread_hdl_ xmitThread; +#endif +#ifdef CONFIG_RECV_THREAD_MODE _thread_hdl_ recvThread; - +#endif u8 registered; #ifndef PLATFORM_LINUX NDIS_STATUS(*dvobj_init)(struct dvobj_priv *dvobj); void (*dvobj_deinit)(struct dvobj_priv *dvobj); #endif - u32(*intf_init)(struct dvobj_priv *dvobj); - void (*intf_deinit)(struct dvobj_priv *dvobj); - int (*intf_alloc_irq)(struct dvobj_priv *dvobj); - void (*intf_free_irq)(struct dvobj_priv *dvobj); - - void (*intf_start)(_adapter *adapter); void (*intf_stop)(_adapter *adapter); @@ -1413,12 +1481,11 @@ struct _ADAPTER { u8 netif_up; - u8 bBTFWReady; u8 bLinkInfoDump; - u8 bRxRSSIDisplay; /* Added by Albert 2012/10/26 */ /* The driver will show up the desired channel number when this flag is 1. */ u8 bNotifyChannelChange; + u8 bsta_tp_dump; #ifdef CONFIG_P2P /* Added by Albert 2012/12/06 */ /* The driver will show the current P2P status when the upper application reads it. */ @@ -1468,6 +1535,9 @@ struct _ADAPTER { #ifdef CONFIG_MAC_LOOPBACK_DRIVER PLOOPBACKDATA ploopback; #endif +#ifdef CONFIG_AP_MODE + u8 bmc_tx_rate; +#endif /* for debug purpose */ u8 fix_rate; @@ -1477,7 +1547,6 @@ struct _ADAPTER { u8 driver_tx_bw_mode; u8 rsvd_page_offset; u8 rsvd_page_num; - #ifdef CONFIG_SUPPORT_FIFO_DUMP u8 fifo_sel; u32 fifo_addr; @@ -1496,7 +1565,6 @@ struct _ADAPTER { u16 tx_amsdu_rate; #endif u8 driver_tx_max_agg_num; /*fix tx desc max agg num , 0xff: disable drv ctrl*/ - unsigned char in_cta_test; #ifdef DBG_RX_COUNTER_DUMP u8 dump_rx_cnt_mode;/*BIT0:drv,BIT1:mac,BIT2:phy*/ u32 drv_rx_cnt_ok; @@ -1513,6 +1581,16 @@ struct _ADAPTER { #ifdef CONFIG_MCC_MODE struct mcc_adapter_priv mcc_adapterpriv; #endif /* CONFIG_MCC_MODE */ + +#ifdef CONFIG_RTW_MESH + struct rtw_mesh_cfg mesh_cfg; + struct rtw_mesh_info mesh_info; + _timer mesh_path_timer; + _timer mesh_path_root_timer; + _timer mesh_atlm_param_req_timer; /* airtime link metrics param request timer */ + _workitem mesh_work; + unsigned long wrkq_flags; +#endif /* CONFIG_RTW_MESH */ }; #define adapter_to_dvobj(adapter) ((adapter)->dvobj) @@ -1526,6 +1604,7 @@ struct _ADAPTER { #endif #define adapter_to_rfctl(adapter) dvobj_to_rfctl(adapter_to_dvobj((adapter))) +#define adapter_to_macidctl(adapter) dvobj_to_macidctl(adapter_to_dvobj((adapter))) #define adapter_mac_addr(adapter) (adapter->mac_addr) #define adapter_to_chset(adapter) (adapter_to_rfctl((adapter))->channel_set) diff --git a/include/drv_types_pci.h b/include/drv_types_pci.h index 682688d..a3a4927 100644 --- a/include/drv_types_pci.h +++ b/include/drv_types_pci.h @@ -24,10 +24,8 @@ #define INTEL_VENDOR_ID 0x8086 #define SIS_VENDOR_ID 0x1039 #define ATI_VENDOR_ID 0x1002 -#define AMD_VENDOR_ID 0x1022 -#define NVI_VENDOR_ID 0x10de - #define ATI_DEVICE_ID 0x7914 +#define AMD_VENDOR_ID 0x1022 #define PCI_MAX_BRIDGE_NUMBER 255 #define PCI_MAX_DEVICES 32 @@ -83,10 +81,9 @@ enum pci_bridge_vendor { PCI_BRIDGE_VENDOR_INTEL = 0x0,/* 0b'0000,0001 */ PCI_BRIDGE_VENDOR_ATI, /* = 0x02, */ /* 0b'0000,0010 */ PCI_BRIDGE_VENDOR_AMD, /* = 0x04, */ /* 0b'0000,0100 */ - PCI_BRIDGE_VENDOR_SIS, /* = 0x08, */ /* 0b'0000,1000 */ - PCI_BRIDGE_VENDOR_NVI, /* = 0x10, */ /* 0b'0001,0000 */ + PCI_BRIDGE_VENDOR_SIS ,/* = 0x08, */ /* 0b'0000,1000 */ PCI_BRIDGE_VENDOR_UNKNOWN, /* = 0x40, */ /* 0b'0100,0000 */ - PCI_BRIDGE_VENDOR_MAX, /* = 0x80 */ + PCI_BRIDGE_VENDOR_MAX ,/* = 0x80 */ } ; /* copy this data structor defination from MSDN SDK */ diff --git a/include/hal_btcoex.h b/include/hal_btcoex.h index 0e01607..03021fe 100644 --- a/include/hal_btcoex.h +++ b/include/hal_btcoex.h @@ -37,6 +37,7 @@ void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum); u8 hal_btcoex_Initialize(PADAPTER padapter); void hal_btcoex_PowerOnSetting(PADAPTER padapter); +void hal_btcoex_AntInfoSetting(PADAPTER padapter); void hal_btcoex_PowerOffSetting(PADAPTER padapter); void hal_btcoex_PreLoadFirmware(PADAPTER padapter); void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly); @@ -86,6 +87,8 @@ u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data); u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val); void hal_btcoex_set_rfe_type(u8 type); void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type); +void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length); +void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id); #ifdef CONFIG_RF4CE_COEXIST void hal_btcoex_set_rf4ce_link_state(u8 state); diff --git a/include/hal_btcoex_wifionly.h b/include/hal_btcoex_wifionly.h index 8a726c0..b41bc36 100644 --- a/include/hal_btcoex_wifionly.h +++ b/include/hal_btcoex_wifionly.h @@ -18,6 +18,15 @@ #include #include +/* Define the ICs that support wifi only cfg in coex. codes */ +#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) +#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 1 +#else +#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 0 +#endif + +#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1) + typedef enum _WIFIONLY_CHIP_INTERFACE { WIFIONLY_INTF_UNKNOWN = 0, WIFIONLY_INTF_PCI = 1, @@ -52,10 +61,19 @@ u8 halwifionly_read1byte(PVOID pwifionlyContext, u32 RegAddr); u16 halwifionly_read2byte(PVOID pwifionlyContext, u32 RegAddr); u32 halwifionly_read4byte(PVOID pwifionlyContext, u32 RegAddr); void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMask, u8 data); -void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); +void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data); void halwifionly_phy_set_bb_reg(PVOID pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data); void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter); void hal_btcoex_wifionly_scan_notify(PADAPTER padapter); void hal_btcoex_wifionly_hw_config(PADAPTER padapter); void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter); +void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter); +#else +#define hal_btcoex_wifionly_switchband_notify(padapter) +#define hal_btcoex_wifionly_scan_notify(padapter) +#define hal_btcoex_wifionly_hw_config(padapter) +#define hal_btcoex_wifionly_initlizevariables(padapter) +#define hal_btcoex_wifionly_AntInfoSetting(padapter) +#endif + #endif diff --git a/include/hal_com.h b/include/hal_com.h index 5a10a27..bdfeb6e 100644 --- a/include/hal_com.h +++ b/include/hal_com.h @@ -281,6 +281,9 @@ struct dbg_rx_counter { #ifdef CONFIG_MI_WITH_MBSSID_CAM void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr); void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr); + #ifdef CONFIG_SWTIMER_BASED_TXBCN + u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval); + #endif #endif void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter); @@ -327,7 +330,9 @@ void rtw_hal_config_rftype(PADAPTER padapter); #define WL_FUNC_FTM BIT3 #define WL_FUNC_BIT_NUM 4 -#define TBTT_PROBIHIT_HOLD_TIME 0x80 +#define TBTT_PROHIBIT_SETUP_TIME 0x04 /* 128us, unit is 32us */ +#define TBTT_PROHIBIT_HOLD_TIME 0x80 /* 4ms, unit is 32us*/ +#define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 /* 3.2ms unit is 32us*/ int hal_spec_init(_adapter *adapter); void dump_hal_spec(void *sel, _adapter *adapter); @@ -376,6 +381,7 @@ Hal_MappingOutPipe( ); void rtw_dump_fw_info(void *sel, _adapter *adapter); +void rtw_restore_hw_port_cfg(_adapter *adapter); void rtw_restore_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/ void rtw_hal_dump_macaddr(void *sel, _adapter *adapter); @@ -391,9 +397,12 @@ void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len); void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len); #endif -u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta); u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type); -void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta); + +void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta); +s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta); +s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta); +void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta); /* access HW only */ u32 rtw_sec_read_cam(_adapter *adapter, u8 addr); @@ -403,15 +412,15 @@ void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id); bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id); -void rtw_hal_set_msr(_adapter *adapter, u8 net_type); -void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val); -void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr); +u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit); -void rtw_hal_set_bssid(_adapter *adapter, u8 *val); +u8 rtw_hal_rcr_add(_adapter *adapter, u32 add); +u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear); +void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action); void hw_var_port_switch(_adapter *adapter); -void SetHwReg(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHwReg(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg(PADAPTER padapter, u8 variable, u8 *val); void rtw_hal_check_rxfifo_full(_adapter *adapter); void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid); @@ -483,13 +492,12 @@ void linked_info_dump(_adapter *padapter, u8 benable); #endif void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe); #define HWSET_MAX_SIZE 1024 + #ifdef CONFIG_EFUSE_CONFIG_FILE - #define EFUSE_FILE_COLUMN_NUM 16 - u32 Hal_readPGDataFromConfigFile(PADAPTER padapter); - u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr); +u32 Hal_readPGDataFromConfigFile(PADAPTER padapter); +u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr); #endif /* CONFIG_EFUSE_CONFIG_FILE */ -int check_phy_efuse_tx_power_info_valid(PADAPTER padapter); int hal_efuse_macaddr_offset(_adapter *adapter); int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr); void rtw_dump_cur_efuse(PADAPTER padapter); @@ -500,32 +508,16 @@ void rtw_dump_cur_efuse(PADAPTER padapter); void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer); u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel); -void GetHalODMVar( - PADAPTER Adapter, - HAL_ODM_VARIABLE eVariable, - PVOID pValue1, - PVOID pValue2); -void SetHalODMVar( - PADAPTER Adapter, - HAL_ODM_VARIABLE eVariable, - PVOID pValue1, - BOOLEAN bSet); - -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR -struct noise_info { - u8 bPauseDIG; - u8 IGIValue; - u32 max_time;/* ms */ - u8 chan; -}; -#endif -void rtw_get_noise(_adapter *padapter); -u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid); -u8 rtw_get_current_tx_sgi(_adapter *padapter, u8 macid); -void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength, u8 *StaAddr, u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave); +u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta); +u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta); void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished); +u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter); + +#ifdef CONFIG_TSF_RESET_OFFLOAD +int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port); +#endif #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW @@ -551,6 +543,7 @@ void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case); #ifdef CONFIG_GPIO_WAKEUP void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable); void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval); + void rtw_hal_set_input_gpio(_adapter *padapter, u8 index); #endif #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE @@ -561,10 +554,6 @@ void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case); void update_IOT_info(_adapter *padapter); -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - void rtw_acs_start(_adapter *padapter, bool bStart); -#endif - void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap); void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf); @@ -610,6 +599,9 @@ enum lps_pg_hdl_id { #endif int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size); +void rtw_hal_construct_beacon(_adapter *padapter, u8 *pframe, u32 *pLength); +void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength, + u8 *StaAddr, u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave); #ifdef CONFIG_WOWLAN struct rtl_wow_pattern { @@ -633,7 +625,16 @@ struct rtw_ndp_info { u8 remote_ipv6_addr[16]; /* Just respond IP */ u8 target_ipv6_addr[16]; /* target IP */ }; -#endif +#define REMOTE_INFO_CTRL_SET_VALD_EN(target, _value) \ + SET_BITS_TO_LE_4BYTE(target + 0, 0, 8, _value) +#define REMOTE_INFO_CTRL_SET_PTK_EN(target, _value) \ + SET_BITS_TO_LE_4BYTE(target + 1, 0, 1, _value) +#define REMOTE_INFO_CTRL_SET_GTK_EN(target, _value) \ + SET_BITS_TO_LE_4BYTE(target + 1, 1, 1, _value) +#define REMOTE_INFO_CTRL_SET_GTK_IDX(target, _value) \ + SET_BITS_TO_LE_4BYTE(target + 2, 0, 8, _value) +#endif /*CONFIG_WOWLAN*/ + void rtw_dump_phy_cap(void *sel, _adapter *adapter); void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num); #ifdef CONFIG_SUPPORT_FIFO_DUMP @@ -652,6 +653,26 @@ void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state); #endif #endif -void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter); +#ifdef RTW_CHANNEL_SWITCH_OFFLOAD +void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw); +#endif +s16 translate_dbm_to_percentage(s16 signal); + +#ifdef CONFIG_SWTIMER_BASED_TXBCN +#ifdef CONFIG_BCN_RECOVERY +u8 rtw_ap_bcn_recovery(_adapter *padapter); +#endif +#ifdef CONFIG_BCN_XMIT_PROTECT +u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms); +#endif +#endif /*CONFIG_SWTIMER_BASED_TXBCN*/ + +void rtw_hal_get_rf_path(struct dvobj_priv *d, enum rf_type *type, + enum bb_path *tx, enum bb_path *rx); +#ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 +void rtw_hal_beamforming_config_csirate(PADAPTER adapter); +#endif +#endif #endif /* __HAL_COMMON_H__ */ diff --git a/include/hal_com_h2c.h b/include/hal_com_h2c.h index 9e63909..06cd273 100644 --- a/include/hal_com_h2c.h +++ b/include/hal_com_h2c.h @@ -35,14 +35,16 @@ enum h2c_cmd { H2C_FCS_INFO = 0x11, H2C_AP_WOW_GPIO_CTRL = 0x13, #ifdef CONFIG_MCC_MODE - H2C_MCC_UPDATE_PARAM = 0x15, + H2C_MCC_RQT_TSF = 0x15, H2C_MCC_MACID_BITMAP = 0x16, H2C_MCC_LOCATION = 0x10, + H2C_MCC_CTRL_V2 = 0x17, H2C_MCC_CTRL = 0x18, - H2C_MCC_NOA_PARAM = 0x19, + H2C_MCC_TIME_SETTING = 0x19, H2C_MCC_IQK_PARAM = 0x1A, #endif /* CONFIG_MCC_MODE */ H2C_CHNL_SWITCH_OPER_OFFLOAD = 0x1C, + H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D, /* PoweSave Class: 001 */ H2C_SET_PWR_MODE = 0x20, @@ -78,7 +80,9 @@ enum h2c_cmd { H2C_DYNAMIC_TX_PATH = 0x48,/* for 8814A */ H2C_FW_TRACE_EN = 0x49, - +#ifdef RTW_PER_CMD_SUPPORT_FW + H2C_REQ_PER_RPT = 0x4e, +#endif /* BT Class: 011 */ H2C_B_TYPE_TDMA = 0x60, H2C_BT_INFO = 0x61, @@ -112,6 +116,9 @@ enum h2c_cmd { H2C_CUSTOMER_STR_W1 = 0xC6, H2C_CUSTOMER_STR_W2 = 0xC7, H2C_CUSTOMER_STR_W3 = 0xC8, +#ifdef DBG_FW_DEBUG_MSG_PKT + H2C_FW_DBG_MSG_PKT = 0xE1, +#endif /*DBG_FW_DEBUG_MSG_PKT*/ H2C_MAXID, }; @@ -132,7 +139,7 @@ enum h2c_cmd { #define H2C_PSTUNEPARAM_LEN 4 #define H2C_MACID_CFG_LEN 7 #define H2C_BTMP_OPER_LEN 5 -#define H2C_WOWLAN_LEN 5 +#define H2C_WOWLAN_LEN 6 #define H2C_REMOTE_WAKE_CTRL_LEN 3 #define H2C_AOAC_GLOBAL_INFO_LEN 2 #define H2C_AOAC_RSVDPAGE_LOC_LEN 7 @@ -147,10 +154,14 @@ enum h2c_cmd { #define H2C_P2P_OFFLOAD_LEN 3 #ifdef CONFIG_MCC_MODE #define H2C_MCC_CTRL_LEN 7 +#ifdef CONFIG_MCC_MODE_V2 + #define H2C_MCC_LOCATION_LEN 7 +#else #define H2C_MCC_LOCATION_LEN 3 +#endif #define H2C_MCC_MACID_BITMAP_LEN 6 - #define H2C_MCC_UPDATE_INFO_LEN 4 - #define H2C_MCC_NOA_PARAM_LEN 4 + #define H2C_MCC_RQT_TSF_LEN 1 + #define H2C_MCC_TIME_SETTING_LEN 6 #define H2C_MCC_IQK_PARAM_LEN 7 #endif /* CONFIG_MCC_MODE */ #ifdef CONFIG_LPS_PG @@ -165,6 +176,13 @@ enum h2c_cmd { #if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) #define H2C_BTC_WL_PORT_ID_LEN 1 #endif + +#ifdef DBG_FW_DEBUG_MSG_PKT + #define H2C_FW_DBG_MSG_PKT_LEN 2 +#endif /*DBG_FW_DEBUG_MSG_PKT*/ + +#define H2C_SINGLE_CHANNELSWITCH_V2_LEN 2 + #define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0) #define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5]) #define cpIpAddr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3]) @@ -249,7 +267,8 @@ enum h2c_cmd { #define H2C_MSR_ROLE_GO 4 #define H2C_MSR_ROLE_TDLS 5 #define H2C_MSR_ROLE_ADHOC 6 -#define H2C_MSR_ROLE_MAX 7 +#define H2C_MSR_ROLE_MESH 7 +#define H2C_MSR_ROLE_MAX 8 extern const char *const _h2c_msr_role_str[]; #define h2c_msr_role_str(role) (((role) >= H2C_MSR_ROLE_MAX) ? _h2c_msr_role_str[H2C_MSR_ROLE_MAX] : _h2c_msr_role_str[(role)]) @@ -357,12 +376,36 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); #ifdef CONFIG_MCC_MODE /* MCC LOC CMD 0x10 */ #define SET_H2CCMD_MCC_RSVDPAGE_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 0, 1, __Value) +#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 4, 4, __Value) +#define SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 4, 0, 8, __Value) + +/* MCC RQT TSF 0x15 */ +#define SET_H2CCMD_MCC_RQT_TSFX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_H2CCMD_MCC_RQT_TSFY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) /* MCC MAC ID CMD 0x16 */ #define SET_H2CCMD_MCC_MACID_BITMAP_L(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) #define SET_H2CCMD_MCC_MACID_BITMAP_H(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -/* MCC INFO CMD 0x18 */ +/* NEW MCC CTRL CMD 0x17 */ +#define SET_H2CCMD_MCC_CTRL_V2_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_INCURCH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_C2HRPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 6, 2, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_TSFX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 4, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value) + + +/* MCC CTRL CMD 0x18 */ #define SET_H2CCMD_MCC_CTRL_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) #define SET_H2CCMD_MCC_CTRL_TOTALNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) #define SET_H2CCMD_MCC_CTRL_CHIDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) @@ -379,12 +422,16 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); #define SET_H2CCMD_MCC_CTRL_C2HRPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 5, 2, __Value) #define SET_H2CCMD_MCC_CTRL_CHSCAN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value) -/* MCC NoA CMD 0x19 */ -#define SET_H2CCMD_MCC_NOA_FW_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_H2CCMD_MCC_NOA_TSF_SYNC_OFFSET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value) -#define SET_H2CCMD_MCC_NOA_START_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_H2CCMD_MCC_NOA_INTERVAL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_H2CCMD_MCC_EARLY_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +/* MCC Time CMD 0x19 */ +#define SET_H2CCMD_MCC_TIME_SETTING_FW_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_START_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 4, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 1, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 1, 7, __Value) /* MCC IQK CMD 0x1A */ #define SET_H2CCMD_MCC_IQK_READY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) @@ -407,6 +454,12 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); #define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 5, 3, __Value) #define SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 0, 4, __Value) +/* H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D */ +#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 4, __Value) +#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 4, 4, __Value) + + #if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) #define SET_H2CCMD_BTC_WL_PORT_ID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) #endif @@ -425,8 +478,14 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); #define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) #define SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 1, __Value) #define SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 1, 7, __Value) -#define SET_H2CCMD_WOWLAN_LOWPR_RX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 1, __Value) +#define SET_H2CCMD_WOWLAN_DISABLE_UPHY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 1, __Value) +#define SET_H2CCMD_WOWLAN_HST2DEV_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 1, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_DURATION_MS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value) #define SET_H2CCMD_WOWLAN_CHANGE_UNIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value) +#define SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value) +#define SET_H2CCMD_WOWLAN_TAKE_PDN_UPHY_DIS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value) + /* _REMOTE_WAKEUP_CMD_0x81 */ #define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) #define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) @@ -495,6 +554,11 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); #define SET_H2CCMD_LPSPG_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)/*Loc_LPS_PG*/ #endif +#ifdef DBG_FW_DEBUG_MSG_PKT +#define SET_H2CCMD_FW_DBG_MSG_PKT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*sniffer_dbg_en*/ +#define SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) /*loc_debug_packet*/ +#endif /*DBG_FW_DEBUG_MSG_PKT*/ + /* --------------------------------------------------------------------------------------------------------- * ------------------------------------------- Structure -------------------------------------------------- * --------------------------------------------------------------------------------------------------------- */ @@ -532,6 +596,9 @@ typedef struct _RSVDPAGE_LOC { u8 LocInviteRsp; u8 LocPDRsp; #endif /* CONFIG_P2P_WOWLAN */ +#ifdef DBG_FW_DEBUG_MSG_PKT + u8 loc_fw_dbg_msg_pkt; +#endif /*DBG_FW_DEBUG_MSG_PKT*/ } RSVDPAGE_LOC, *PRSVDPAGE_LOC; #endif @@ -547,3 +614,8 @@ u8 rtw_hal_set_fw_media_status_cmd(_adapter *adapter, u8 mstatus, u8 macid); u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter); #endif /* CONFIG_P2P_WOWLAN */ #endif + +#ifdef RTW_PER_CMD_SUPPORT_FW +u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid, + u8 rpt_type, u32 macid_bitmap); +#endif diff --git a/include/hal_com_led.h b/include/hal_com_led.h index 38ac683..d88556d 100644 --- a/include/hal_com_led.h +++ b/include/hal_com_led.h @@ -15,7 +15,10 @@ #ifndef __HAL_COMMON_LED_H_ #define __HAL_COMMON_LED_H_ +#define NO_LED 0 +#define HW_LED 1 +#ifdef CONFIG_RTW_LED #define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) /* ******************************************************************************** @@ -98,17 +101,21 @@ typedef enum _LED_CTL_MODE { LED_CTL_POWER_ON = 1, LED_CTL_LINK = 2, LED_CTL_NO_LINK = 3, - LED_CTL_TX = 4, - LED_CTL_RX = 5, - LED_CTL_SITE_SURVEY = 6, - LED_CTL_POWER_OFF = 7, - LED_CTL_START_TO_LINK = 8, - LED_CTL_START_WPS = 9, - LED_CTL_STOP_WPS = 10, - LED_CTL_START_WPS_BOTTON = 11, /* added for runtop */ - LED_CTL_STOP_WPS_FAIL = 12, /* added for ALPHA */ - LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, /* added for BELKIN */ - LED_CTL_CONNECTION_NO_TRANSFER = 14, + LED_CTL_TX = 4, /* unspecific data TX, including single & group addressed */ + LED_CTL_RX = 5, /* unspecific data RX, including single & group addressed */ + LED_CTL_UC_TX = 6, /* single addressed data TX */ + LED_CTL_UC_RX = 7, /* single addressed data RX */ + LED_CTL_BMC_TX = 8, /* group addressed data TX */ + LED_CTL_BMC_RX = 9, /* group addressed data RX */ + LED_CTL_SITE_SURVEY = 10, + LED_CTL_POWER_OFF = 11, + LED_CTL_START_TO_LINK = 12, + LED_CTL_START_WPS = 13, + LED_CTL_STOP_WPS = 14, + LED_CTL_START_WPS_BOTTON = 15, /* added for runtop */ + LED_CTL_STOP_WPS_FAIL = 16, /* added for ALPHA */ + LED_CTL_STOP_WPS_FAIL_OVERLAP = 17, /* added for BELKIN */ + LED_CTL_CONNECTION_NO_TRANSFER = 18, } LED_CTL_MODE; typedef enum _LED_STATE { @@ -154,6 +161,8 @@ typedef enum _LED_PIN { * ******************************************************************************** */ #ifdef CONFIG_PCI_HCI typedef enum _LED_STRATEGY_PCIE { + /* start from 2 */ + SW_LED_MODE_UC_TRX_ONLY = 2, SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */ SW_LED_MODE1, /* SW control for PCI Express */ SW_LED_MODE2, /* SW control for Cameo. */ @@ -167,7 +176,6 @@ typedef enum _LED_STRATEGY_PCIE { SW_LED_MODE10, /* added by chiyokolin, for Edimax-ASUS */ SW_LED_MODE11, /* added by hpfan, for Xavi */ SW_LED_MODE12, /* added by chiyokolin, for Azurewave */ - HW_LED, /* HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes) */ } LED_STRATEGY_PCIE, *PLED_STRATEGY_PCIE; typedef struct _LED_PCIE { @@ -215,6 +223,8 @@ gen_RefreshLedState( typedef enum _LED_STRATEGY_USB { + /* start from 2 */ + SW_LED_MODE_UC_TRX_ONLY = 2, SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */ SW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */ SW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */ @@ -231,7 +241,6 @@ typedef enum _LED_STRATEGY_USB { SW_LED_MODE13, /* for Netgear A6100, 8811Au */ SW_LED_MODE14, /* for Buffalo, DNI, 8811Au */ SW_LED_MODE15, /* for DLINK, 8811Au/8812AU */ - HW_LED, /* HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) */ } LED_STRATEGY_USB, *PLED_STRATEGY_USB; @@ -264,12 +273,13 @@ typedef struct _LED_USB { typedef struct _LED_USB LED_DATA, *PLED_DATA; typedef enum _LED_STRATEGY_USB LED_STRATEGY, *PLED_STRATEGY; - +#ifdef CONFIG_RTW_SW_LED VOID LedControlUSB( IN PADAPTER Adapter, IN LED_CTL_MODE LedAction ); +#endif /* ******************************************************************************** @@ -286,6 +296,8 @@ LedControlUSB( typedef enum _LED_STRATEGY_SDIO { + /* start from 2 */ + SW_LED_MODE_UC_TRX_ONLY = 2, SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */ SW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */ SW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */ @@ -293,7 +305,6 @@ typedef enum _LED_STRATEGY_SDIO { SW_LED_MODE4, /* for Edimax / Belkin */ SW_LED_MODE5, /* for Sercomm / Belkin */ SW_LED_MODE6, /* for 88CU minicard, porting from ce SW_LED_MODE7 */ - HW_LED, /* HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) */ } LED_STRATEGY_SDIO, *PLED_STRATEGY_SDIO; typedef struct _LED_SDIO { @@ -334,38 +345,30 @@ LedControlSDIO( #endif struct led_priv { - /* add for led controll */ + LED_STRATEGY LedStrategy; +#ifdef CONFIG_RTW_SW_LED LED_DATA SwLed0; LED_DATA SwLed1; LED_DATA SwLed2; - LED_STRATEGY LedStrategy; u8 bRegUseLed; + u8 iface_en_mask; + u32 ctl_en_mask[CONFIG_IFACE_NUMBER]; void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction); void (*SwLedOn)(_adapter *padapter, PLED_DATA pLed); void (*SwLedOff)(_adapter *padapter, PLED_DATA pLed); - /* add for led controll */ +#endif }; -#ifdef CONFIG_SW_LED -#define rtw_led_control(adapter, LedAction) \ - do { \ - if ((adapter)->ledpriv.LedControlHandler) \ - (adapter)->ledpriv.LedControlHandler((adapter), (LedAction)); \ - } while (0) -#else /* CONFIG_SW_LED */ -#define rtw_led_control(adapter, LedAction) -#endif /* CONFIG_SW_LED */ - #define SwLedOn(adapter, pLed) \ do { \ - if ((adapter)->ledpriv.SwLedOn) \ - (adapter)->ledpriv.SwLedOn((adapter), (pLed)); \ + if (adapter_to_led(adapter)->SwLedOn) \ + adapter_to_led(adapter)->SwLedOn((adapter), (pLed)); \ } while (0) #define SwLedOff(adapter, pLed) \ do { \ - if ((adapter)->ledpriv.SwLedOff) \ - (adapter)->ledpriv.SwLedOff((adapter), (pLed)); \ + if (adapter_to_led(adapter)->SwLedOff) \ + adapter_to_led(adapter)->SwLedOff((adapter), (pLed)); \ } while (0) void BlinkTimerCallback(void *data); @@ -387,5 +390,48 @@ DeInitLed( /* hal... */ extern void BlinkHandler(PLED_DATA pLed); +void dump_led_config(void *sel, _adapter *adapter); +void rtw_led_set_strategy(_adapter *adapter, u8 strategy); +#endif /* CONFIG_RTW_LED */ + +#if defined(CONFIG_RTW_LED) +#define rtw_led_get_strategy(adapter) (adapter_to_led(adapter)->LedStrategy) +#else +#define rtw_led_get_strategy(adapter) NO_LED +#endif + +#define IS_NO_LED_STRATEGY(s) ((s) == NO_LED) +#define IS_HW_LED_STRATEGY(s) ((s) == HW_LED) +#define IS_SW_LED_STRATEGY(s) ((s) != NO_LED && (s) != HW_LED) + +#if defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) + +#ifndef CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY +#define CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY 0 +#endif + +#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY +void rtw_sw_led_blink_uc_trx_only(LED_DATA *led); +void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl); +#endif +void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl); +void rtw_led_tx_control(_adapter *adapter, const u8 *da); +void rtw_led_rx_control(_adapter *adapter, const u8 *da); +void rtw_led_set_iface_en(_adapter *adapter, u8 en); +void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask); +void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask); +void rtw_led_set_ctl_en_mask_primary(_adapter *adapter); +void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter); +#else +#define rtw_led_control(adapter, ctl) do {} while (0) +#define rtw_led_tx_control(adapter, da) do {} while (0) +#define rtw_led_rx_control(adapter, da) do {} while (0) +#define rtw_led_set_iface_en(adapter, en) do {} while (0) +#define rtw_led_set_iface_en_mask(adapter, mask) do {} while (0) +#define rtw_led_set_ctl_en_mask(adapter, ctl_mask) do {} while (0) +#define rtw_led_set_ctl_en_mask_primary(adapter) do {} while (0) +#define rtw_led_set_ctl_en_mask_virtual(adapter) do {} while (0) +#endif /* defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) */ + +#endif /*__HAL_COMMON_LED_H_*/ -#endif /* __RTW_LED_H_ */ diff --git a/include/hal_com_phycfg.h b/include/hal_com_phycfg.h index 67eec83..581bca4 100644 --- a/include/hal_com_phycfg.h +++ b/include/hal_com_phycfg.h @@ -84,7 +84,7 @@ PHY_GetRateIndexOfTxPowerByRate( VOID phy_set_tx_power_index_by_rate_section( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Channel, IN u8 RateSection ); @@ -93,7 +93,7 @@ s8 _PHY_GetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 RateIndex ); @@ -101,7 +101,7 @@ s8 PHY_GetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 RateIndex ); @@ -109,7 +109,7 @@ VOID PHY_SetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, IN s8 Value ); @@ -124,8 +124,8 @@ phy_set_tx_power_level_by_path( VOID PHY_SetTxPowerIndexByRateArray( IN PADAPTER pAdapter, - IN u8 RFPath, - IN CHANNEL_WIDTH BandWidth, + IN enum rf_path RFPath, + IN enum channel_width BandWidth, IN u8 Channel, IN u8 *Rates, IN u8 RateArraySize @@ -155,10 +155,10 @@ PHY_TxPowerByRateConfiguration( u8 PHY_GetTxPowerIndexBase( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, u8 ntx_idx, - IN CHANNEL_WIDTH BandWidth, + IN enum channel_width BandWidth, IN u8 Channel, OUT PBOOLEAN bIn24G ); @@ -166,19 +166,19 @@ PHY_GetTxPowerIndexBase( #ifdef CONFIG_TXPWR_LIMIT s8 phy_get_txpwr_lmt_abs(_adapter *adapter , const char *regd_name - , BAND_TYPE band, CHANNEL_WIDTH bw + , BAND_TYPE band, enum channel_width bw , u8 tlrs, u8 ntx_idx, u8 cch, u8 lock ); s8 phy_get_txpwr_lmt(_adapter *adapter , const char *regd_name - , BAND_TYPE band, CHANNEL_WIDTH bw + , BAND_TYPE band, enum channel_width bw , u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock ); s8 PHY_GetTxPowerLimit(_adapter *adapter , const char *regd_name - , BAND_TYPE band, CHANNEL_WIDTH bw + , BAND_TYPE band, enum channel_width bw , u8 rfpath, u8 rate, u8 ntx_idx, u8 cch ); #else @@ -190,7 +190,7 @@ s8 PHY_GetTxPowerLimit(_adapter *adapter s8 PHY_GetTxPowerTrackingOffset( PADAPTER pAdapter, - u8 RFPath, + enum rf_path RFPath, u8 Rate ); @@ -206,9 +206,9 @@ struct txpwr_idx_comp { u8 phy_get_tx_power_index( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, + IN enum channel_width BandWidth, IN u8 Channel ); @@ -216,7 +216,7 @@ VOID PHY_SetTxPowerIndex( IN PADAPTER pAdapter, IN u32 PowerIndex, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ); @@ -236,6 +236,10 @@ void phy_reload_default_tx_power_ext_info(_adapter *adapter); const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter); +#ifdef CONFIG_EFUSE_CONFIG_FILE +int check_phy_efuse_tx_power_info_valid(_adapter *adapter); +#endif + void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt); void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt); @@ -285,7 +289,7 @@ int phy_ConfigMACWithParaFile(IN PADAPTER Adapter, IN char *pFileName); int phy_ConfigBBWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN u32 ConfigType); int phy_ConfigBBWithPgParaFile(IN PADAPTER Adapter, IN const char *pFileName); int phy_ConfigBBWithMpParaFile(IN PADAPTER Adapter, IN char *pFileName); -int PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN u8 eRFPath); +int PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN enum rf_path eRFPath); int PHY_ConfigRFWithTxPwrTrackParaFile(IN PADAPTER Adapter, IN char *pFileName); #ifdef CONFIG_TXPWR_LIMIT int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER Adapter, IN const char *pFileName); diff --git a/include/hal_com_reg.h b/include/hal_com_reg.h index 71990e7..862164f 100644 --- a/include/hal_com_reg.h +++ b/include/hal_com_reg.h @@ -209,8 +209,6 @@ #define REG_DBI_FLAG 0x0352 /* Backdoor REG for Access Configuration */ #define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ #define REG_DBG_SEL 0x0360 /* Debug Selection Register */ -#define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ -#define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ #define REG_WATCH_DOG 0x0368 #define REG_RX_RXBD_NUM 0x0382 @@ -315,6 +313,11 @@ #define REG_MACID_SLEEP 0x04D4 #define REG_NQOS_SEQ 0x04DC +#define REG_HW_SEQ0 0x04D8 +#define REG_HW_SEQ1 0x04DA +#define REG_HW_SEQ2 0x04DC +#define REG_HW_SEQ3 0x04DE + #define REG_QOS_SEQ 0x04DE #define REG_NEED_CPU_HANDLE 0x04E0 #define REG_PKT_LOSE_RPT 0x04E1 @@ -381,6 +384,7 @@ #define REG_PSTIMER 0x0580 #define REG_TIMER0 0x0584 #define REG_TIMER1 0x0588 +#define REG_HIQ_NO_LMT_EN 0x05A7 #define REG_ACMHWCTRL 0x05C0 #define REG_NOA_DESC_SEL 0x05CF #define REG_NOA_DESC_DURATION 0x05E0 @@ -706,6 +710,7 @@ Default: 00b. ** REG_CCK_CHECK (offset 0x454) ------------------------------------------------------------------------------*/ #define BIT_BCN_PORT_SEL BIT(5) +#define BIT_EN_BCN_PKT_REL BIT(6) #endif /* RTW_HALMAC */ @@ -1479,6 +1484,12 @@ Current IOREG MAP #define RETRY_LIMIT_SHORT_SHIFT 8 #define RETRY_LIMIT_LONG_SHIFT 0 +#define RL_VAL_AP 7 +#ifdef CONFIG_RTW_CUSTOMIZE_RLSTA +#define RL_VAL_STA CONFIG_RTW_CUSTOMIZE_RLSTA +#else +#define RL_VAL_STA 0x30 +#endif /* ----------------------------------------------------- * * 0x0500h ~ 0x05FFh EDCA Configuration @@ -1513,12 +1524,12 @@ Current IOREG MAP /* 2 ACMHWCTRL */ #define AcmHw_HwEn BIT(0) -#define AcmHw_BeqEn BIT(1) +#define AcmHw_VoqEn BIT(1) #define AcmHw_ViqEn BIT(2) -#define AcmHw_VoqEn BIT(3) -#define AcmHw_BeqStatus BIT(4) -#define AcmHw_ViqStatus BIT(5) -#define AcmHw_VoqStatus BIT(6) +#define AcmHw_BeqEn BIT(3) +#define AcmHw_VoqStatus BIT(5) +#define AcmHw_ViqStatus BIT(6) +#define AcmHw_BeqStatus BIT(7) /* 2 */ /* REG_DUAL_TSF_RST (0x553) */ #define DUAL_TSF_RST_P2P BIT(4) @@ -1800,7 +1811,11 @@ Current IOREG MAP * General definitions * ******************************************************** */ -#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter) (IS_VENDOR_8188E_I_CUT_SERIES(__Adapter) ? 255 : 175) +#ifdef CONFIG_USB_HCI + #define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter) (175) +#else + #define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter) (IS_VENDOR_8188E_I_CUT_SERIES(__Adapter) ? 255 : 175) +#endif #define LAST_ENTRY_OF_TX_PKT_BUFFER_8812 255 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B 255 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C 255 diff --git a/include/hal_data.h b/include/hal_data.h index a036ec8..7af31d2 100644 --- a/include/hal_data.h +++ b/include/hal_data.h @@ -28,6 +28,11 @@ #ifdef CONFIG_GSPI_HCI #include #endif + +#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR) +#include "../hal/hal_dm_acs.h" +#endif + /* * For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. * */ @@ -91,21 +96,6 @@ typedef enum _RT_AMPDU_BRUST_MODE { #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 /* OFDM:1, HT:4, VHT:4 */ - -/* ###### duplicate code,will move to ODM ######### */ -/* #define IQK_MAC_REG_NUM 4 */ -/* #define IQK_ADDA_REG_NUM 16 */ - -/* #define IQK_BB_REG_NUM 10 */ -#define IQK_BB_REG_NUM_92C 9 -#define IQK_BB_REG_NUM_92D 10 -#define IQK_BB_REG_NUM_test 6 - -#define IQK_Matrix_Settings_NUM_92D (1+24+21) - -/* #define HP_THERMAL_NUM 8 */ -/* ###### duplicate code,will move to ODM ######### */ - #ifdef RTW_RX_AGGREGATION typedef enum _RX_AGG_MODE { RX_AGG_DISABLE, @@ -194,24 +184,6 @@ typedef struct _BB_INIT_REGISTER { #define HCI_SUS_ENTERING 3 #define HCI_SUS_ERR 4 -#ifdef CONFIG_AUTO_CHNL_SEL_NHM -typedef enum _ACS_OP { - ACS_INIT, /*ACS - Variable init*/ - ACS_RESET, /*ACS - NHM Counter reset*/ - ACS_SELECT, /*ACS - NHM Counter Statistics */ -} ACS_OP; - -typedef enum _ACS_STATE { - ACS_DISABLE, - ACS_ENABLE, -} ACS_STATE; - -struct auto_chan_sel { - ATOMIC_T state; - u8 ch; /* previous channel*/ -}; -#endif /*CONFIG_AUTO_CHNL_SEL_NHM*/ - #define EFUSE_FILE_UNUSED 0 #define EFUSE_FILE_FAILED 1 #define EFUSE_FILE_LOADED 2 @@ -220,9 +192,6 @@ struct auto_chan_sel { #define MACADDR_FILE_FAILED 1 #define MACADDR_FILE_LOADED 2 -#define KFREE_FLAG_ON BIT(0) -#define KFREE_FLAG_THERMAL_K_ON BIT(1) - #define MAX_IQK_INFO_BACKUP_CHNL_NUM 5 #define MAX_IQK_INFO_BACKUP_REG_NUM 10 @@ -257,6 +226,9 @@ struct hal_spec_t { u8 port_num; u8 proto_cap; /* value of PROTO_CAP_XXX */ u8 wl_func; /* value of WL_FUNC_XXX */ + + u8 pg_txpwr_saddr; /* starting address of PG tx power info */ + u8 hci_type; /* value of HCI Type */ }; @@ -363,13 +335,13 @@ typedef struct hal_com_data { u16 FirmwareSignature; u8 RegFWOffload; u8 bFWReady; + u8 bBTFWReady; u8 fw_ractrl; - u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/ u8 LastHMEBoxNum; /* H2C - for host message to fw */ /****** current WIFI_PHY values ******/ WIRELESS_MODE CurrentWirelessMode; - CHANNEL_WIDTH current_channel_bw; + enum channel_width current_channel_bw; BAND_TYPE current_band_type; /* 0:2.4G, 1:5G */ BAND_TYPE BandSet; u8 current_channel; @@ -383,6 +355,7 @@ typedef struct hal_com_data { u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ u16 BasicRateSet; u32 ReceiveConfig; + u32 rcr_backup; /* used for switching back from monitor mode */ u8 rx_tsf_addr_filter_config; /* for 8822B/8821C USE */ BOOLEAN bSwChnl; BOOLEAN bSetChnlBW; @@ -391,26 +364,24 @@ typedef struct hal_com_data { BOOLEAN bChnlBWInitialized; u32 BackUp_BB_REG_4_2nd_CCA[3]; -#ifdef CONFIG_CHNL_LOAD_MAGT - u16 clm_result[MAX_CHANNEL_NUM]; - u16 clm_period; -#endif -#ifdef CONFIG_AUTO_CHNL_SEL_NHM +#ifdef CONFIG_RTW_ACS struct auto_chan_sel acs; #endif +#ifdef CONFIG_BCN_RECOVERY + u8 issue_bcn_fail; +#endif /*CONFIG_BCN_RECOVERY*/ + /****** rf_ctrl *****/ u8 rf_chip; - u8 rf_type; + u8 rf_type; /*enum rf_type*/ u8 PackageType; u8 NumTotalRFPath; u8 antenna_test; /****** Debug ******/ u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ - u8 u1ForcedIgiLb; /* forced IGI lower bound */ u8 bDumpRxPkt; u8 bDumpTxPkt; - u8 bDisableTXPowerTraining; u8 dis_turboedca; @@ -548,15 +519,13 @@ typedef struct hal_com_data { /******** PHY DM & DM Section **********/ _lock IQKSpinLock; u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; - /* Upper and Lower Signal threshold for Rate Adaptive*/ - int entry_min_undecorated_smoothed_pwdb; - int entry_max_undecorated_smoothed_pwdb; - int min_undecorated_pwdb_for_dm; - struct PHY_DM_STRUCT odmpriv; + + struct dm_struct odmpriv; u64 bk_rf_ability; u8 bIQKInitialized; u8 bNeedIQK; - u8 IQK_MP_Switch; + u8 IQK_MP_Switch; + u8 bScanInProcess; /******** PHY DM & DM Section **********/ @@ -576,6 +545,8 @@ typedef struct hal_com_data { u8 RegIQKFWOffload; struct submit_ctx iqk_sctx; + u8 ch_switch_offload; + struct submit_ctx chsw_sctx; RT_AMPDU_BRUST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */ @@ -620,7 +591,7 @@ typedef struct hal_com_data { /* SDIO Rx FIFO related. */ /* */ u8 SdioRxFIFOCnt; - u32 SdioRxFIFOSize; + u16 SdioRxFIFOSize; #ifndef RTW_HALMAC u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */ @@ -631,7 +602,7 @@ typedef struct hal_com_data { u16 tx_normal_page; u16 tx_extra_page; u16 tx_pub_page; - u16 max_oqt_page; + u8 max_oqt_size; #ifdef XMIT_BUF_SIZE u32 max_xmit_size_vovi; u32 max_xmit_size_bebk; @@ -696,6 +667,9 @@ typedef struct hal_com_data { u8 bDisableTxInt; u16 RxTag; +#ifdef CONFIG_PCI_DYNAMIC_ASPM + BOOLEAN bAspmL1LastIdle; +#endif #endif /* CONFIG_PCI_HCI */ @@ -740,7 +714,7 @@ typedef struct hal_com_data { #endif #ifdef CONFIG_BACKGROUND_NOISE_MONITOR - s16 noise[ODM_MAX_CHANNEL_NUM]; + struct noise_monitor nm; #endif struct hal_spec_t hal_spec; @@ -772,14 +746,19 @@ typedef struct hal_com_data { #endif /* CONFIG_BEAMFORMING */ u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/ -} HAL_DATA_COMMON, *PHAL_DATA_COMMON; + u8 phydm_op_mode; + u8 in_cta_test; +#ifdef CONFIG_RTW_LED + struct led_priv led; +#endif +} HAL_DATA_COMMON, *PHAL_DATA_COMMON; typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; -#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) +#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData)) #define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec)) -#define GET_ODM(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->odmpriv)) +#define adapter_to_led(adapter) (&(GET_HAL_DATA(adapter)->led)) #define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath) #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) @@ -793,16 +772,10 @@ typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; #define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr) #define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse) #define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed) +#define rtw_set_hw_init_completed(adapter, cmp) (GET_HAL_DATA(adapter)->hw_init_completed = cmp) #define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE) #endif -#ifdef CONFIG_AUTO_CHNL_SEL_NHM -#define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state)) -#define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state)) -#define rtw_get_acs_channel(padapter) (GET_HAL_DATA(padapter)->acs.ch) -#define rtw_set_acs_channel(padapter, survey_ch) (GET_HAL_DATA(padapter)->acs.ch = survey_ch) -#endif /*CONFIG_AUTO_CHNL_SEL_NHM*/ - #ifdef RTW_HALMAC int rtw_halmac_deinit_adapter(struct dvobj_priv *); #endif /* RTW_HALMAC */ diff --git a/include/hal_ic_cfg.h b/include/hal_ic_cfg.h index 5432b16..50764f8 100644 --- a/include/hal_ic_cfg.h +++ b/include/hal_ic_cfg.h @@ -31,7 +31,10 @@ #define RTL8821C_SUPPORT 0 #define RTL8710B_SUPPORT 0 #define RTL8814B_SUPPORT 0 - +#define RTL8824B_SUPPORT 0 +#define RTL8192F_SUPPORT 0 +#define RTL8198F_SUPPORT 0 +#define RTL8195B_SUPPORT 0 /*#if (RTL8188E_SUPPORT==1)*/ #define RATE_ADAPTIVE_SUPPORT 0 #define POWER_TRAINING_ACTIVE 0 @@ -47,7 +50,6 @@ #define RTL8188E_SUPPORT 1 #define RATE_ADAPTIVE_SUPPORT 1 #define POWER_TRAINING_ACTIVE 1 - #define CONFIG_GET_RAID_BY_DRV #endif #ifdef CONFIG_RTL8812A @@ -140,19 +142,15 @@ #ifdef CONFIG_WOWLAN #define CONFIG_GTK_OL - #define CONFIG_ARP_KEEP_ALIVE - #ifndef CONFIG_DEFAULT_PATTERNS_EN - #warning "Force to enable CONFIG_DEFAULT_PATTERNS_EN under WOW" - #define CONFIG_DEFAULT_PATTERNS_EN - #endif /* !CONFIG_DEFAULT_PATTERNS_EN */ + /*#define CONFIG_ARP_KEEP_ALIVE*/ #ifdef CONFIG_GPIO_WAKEUP #ifndef WAKEUP_GPIO_IDX #define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */ #endif /* !WAKEUP_GPIO_IDX */ #endif /* CONFIG_GPIO_WAKEUP */ - #endif /* CONFIG_WOWLAN */ + #ifdef CONFIG_CONCURRENT_MODE #define CONFIG_AP_PORT_SWAP #define CONFIG_FW_MULTI_PORT_SUPPORT @@ -179,6 +177,30 @@ #ifndef RTW_IQK_FW_OFFLOAD #define RTW_IQK_FW_OFFLOAD #endif /* RTW_IQK_FW_OFFLOAD */ + #define CONFIG_ADVANCE_OTA + + #ifdef CONFIG_MCC_MODE + #define CONFIG_MCC_MODE_V2 + #endif /* CONFIG_MCC_MODE */ + + #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) + #define CONFIG_TDLS_CH_SW_V2 + #endif + + #ifndef RTW_CHANNEL_SWITCH_OFFLOAD + #ifdef CONFIG_TDLS_CH_SW_V2 + #define RTW_CHANNEL_SWITCH_OFFLOAD + #endif + #endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ + + #if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW) + /* Supported since fw v22.1 */ + #define RTW_PER_CMD_SUPPORT_FW + #endif /* RTW_PER_CMD_SUPPORT_FW */ + + #ifndef CONFIG_DYNAMIC_SOML + #define CONFIG_DYNAMIC_SOML + #endif /* CONFIG_DYNAMIC_SOML */ #endif /* CONFIG_RTL8822B */ #ifdef CONFIG_RTL8821C @@ -203,6 +225,20 @@ #define CONFIG_FW_MULTI_PORT_SUPPORT #endif #define CONFIG_SUPPORT_FIFO_DUMP + #ifndef RTW_IQK_FW_OFFLOAD + #define RTW_IQK_FW_OFFLOAD + #endif /* RTW_IQK_FW_OFFLOAD */ + /*#define CONFIG_AMPDU_PRETX_CD*/ + /*#define DBG_PRE_TX_HANG*/ + /* + * Beamforming related definition + */ + /* Beamforming mechanism is on driver not phydm, always disable it */ + #define BEAMFORMING_SUPPORT 0 + /* Only support new beamforming mechanism */ + #ifdef CONFIG_BEAMFORMING + #define RTW_BEAMFORMING_VERSION_2 + #endif /* CONFIG_BEAMFORMING */ #endif #endif /*__HAL_IC_CFG_H__*/ diff --git a/include/hal_intf.h b/include/hal_intf.h index 2ca849d..bf6ce00 100644 --- a/include/hal_intf.h +++ b/include/hal_intf.h @@ -68,7 +68,7 @@ typedef enum _HW_VARIABLES { HW_VAR_TXPAUSE, HW_VAR_BCN_FUNC, HW_VAR_CORRECT_TSF, - HW_VAR_CHECK_BSSID, + HW_VAR_RCR, HW_VAR_MLME_DISCONNECT, HW_VAR_MLME_SITESURVEY, HW_VAR_MLME_JOIN, @@ -82,6 +82,9 @@ typedef enum _HW_VARIABLES { HW_VAR_SEC_DK_CFG, HW_VAR_BCN_VALID, HW_VAR_RF_TYPE, + HW_VAR_TSF, + HW_VAR_FREECNT, + /* PHYDM odm->SupportAbility */ HW_VAR_CAM_EMPTY_ENTRY, HW_VAR_CAM_INVALID_ALL, @@ -90,9 +93,9 @@ typedef enum _HW_VARIABLES { HW_VAR_AC_PARAM_BE, HW_VAR_AC_PARAM_BK, HW_VAR_ACM_CTRL, -#ifdef CONFIG_WMMPS +#ifdef CONFIG_WMMPS_STA HW_VAR_UAPSD_TID, -#endif +#endif /* CONFIG_WMMPS_STA */ HW_VAR_AMPDU_MIN_SPACE, HW_VAR_AMPDU_FACTOR, HW_VAR_RXDMA_AGG_PG_TH, @@ -141,13 +144,15 @@ typedef enum _HW_VARIABLES { HW_VAR_RPT_TIMER_SETTING, HW_VAR_TX_RPT_MAX_MACID, HW_VAR_CHK_HI_QUEUE_EMPTY, + HW_VAR_CHK_MGQ_CPU_EMPTY, HW_VAR_DL_BCN_SEL, HW_VAR_AMPDU_MAX_TIME, HW_VAR_WIRELESS_MODE, HW_VAR_USB_MODE, HW_VAR_PORT_SWITCH, + HW_VAR_PORT_CFG, HW_VAR_DO_IQK, - HW_VAR_DM_IN_LPS, + HW_VAR_DM_IN_LPS_LCLK,/*flag CONFIG_LPS_LCLK_WD_TIMER*/ HW_VAR_SET_REQ_FW_PS, HW_VAR_FW_PS_STATE, HW_VAR_SOUNDING_ENTER, @@ -167,8 +172,6 @@ typedef enum _HW_VARIABLES { HW_VAR_DL_RSVD_PAGE, HW_VAR_MACID_LINK, HW_VAR_MACID_NOLINK, - HW_VAR_MACID_SLEEP, - HW_VAR_MACID_WAKEUP, HW_VAR_DUMP_MAC_QUEUE_INFO, HW_VAR_ASIX_IOT, #ifdef CONFIG_MBSSID_CAM @@ -186,12 +189,15 @@ typedef enum _HW_VARIABLES { HW_VAR_L1OFF_CAPABILITY, HW_VAR_L1OFF_NIC_SUPPORT, #ifdef CONFIG_TDLS - HW_VAR_TDLS_WRCR, - HW_VAR_TDLS_RS_RCR, #ifdef CONFIG_TDLS_CH_SW - HW_VAR_TDLS_BCN_EARLY_C2H_RPT + HW_VAR_TDLS_BCN_EARLY_C2H_RPT, #endif #endif + HW_VAR_DUMP_MAC_TXFIFO, + HW_VAR_PWR_CMD, + HW_VAR_SET_SOML_PARAM, + HW_VAR_ENABLE_RX_BAR, + HW_VAR_TSF_AUTO_SYNC, } HW_VARIABLES; typedef enum _HAL_DEF_VARIABLE { @@ -228,8 +234,6 @@ typedef enum _HAL_DEF_VARIABLE { HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, /* Determine if the L1 Backdoor setting is turned on. */ HAL_DEF_PCI_AMD_L1_SUPPORT, HAL_DEF_PCI_ASPM_OSC, /* Support for ASPM OSC, added by Roger, 2013.03.27. */ - HAL_DEF_MACID_SLEEP, /* Support for MACID sleep */ - HAL_DEF_DBG_DIS_PWT, /* disable Tx power training or not. */ HAL_DEF_EFUSE_USAGE, /* Get current EFUSE utilization. 2008.12.19. Added by Roger. */ HAL_DEF_EFUSE_BYTES, HW_VAR_BEST_AMPDU_DENSITY, @@ -239,17 +243,10 @@ typedef enum _HAL_ODM_VARIABLE { HAL_ODM_STA_INFO, HAL_ODM_P2P_STATE, HAL_ODM_WIFI_DISPLAY_STATE, - HAL_ODM_NOISE_MONITOR, HAL_ODM_REGULATION, HAL_ODM_INITIAL_GAIN, - HAL_ODM_FA_CNT_DUMP, - HAL_ODM_DBG_FLAG, - HAL_ODM_DBG_LEVEL, HAL_ODM_RX_INFO_DUMP, HAL_ODM_RX_Dframe_INFO, -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - HAL_ODM_AUTO_CHNL_SEL, -#endif #ifdef CONFIG_ANTENNA_DIVERSITY HAL_ODM_ANTDIV_SELECT #endif @@ -264,17 +261,6 @@ typedef s32(*c2h_id_filter)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *paylo struct txpwr_idx_comp; -struct macid_cfg { - u8 mac_id; - u8 rate_id; - u8 bandwidth; - u8 short_gi; - u8 ignore_bw; - u8 rsvd; - u16 rsvd1; - u64 ra_mask; -}; - struct hal_ops { /*** initialize section ***/ void (*read_chip_version)(_adapter *padapter); @@ -330,25 +316,21 @@ struct hal_ops { #endif /*** DM section ***/ - +#ifdef CONFIG_RTW_SW_LED void (*InitSwLeds)(_adapter *padapter); void (*DeInitSwLeds)(_adapter *padapter); - - void (*set_chnl_bw_handler)(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); +#endif + void (*set_chnl_bw_handler)(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80); void (*set_tx_power_level_handler)(_adapter *padapter, u8 channel); void (*get_tx_power_level_handler)(_adapter *padapter, s32 *powerlevel); - void (*set_tx_power_index_handler)(_adapter *padapter, u32 powerindex, u8 rfpath, u8 rate); - u8(*get_tx_power_index_handler)(_adapter *padapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); + void (*set_tx_power_index_handler)(_adapter *padapter, u32 powerindex, enum rf_path rfpath, u8 rate); + u8 (*get_tx_power_index_handler)(_adapter *padapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); void (*hal_dm_watchdog)(_adapter *padapter); -#ifdef CONFIG_LPS_LCLK_WD_TIMER - void (*hal_dm_watchdog_in_lps)(_adapter *padapter); -#endif - - void (*set_hw_reg_handler)(_adapter *padapter, u8 variable, u8 *val); + u8 (*set_hw_reg_handler)(_adapter *padapter, u8 variable, u8 *val); void (*GetHwRegHandler)(_adapter *padapter, u8 variable, u8 *val); @@ -361,16 +343,17 @@ struct hal_ops { void (*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2); void (*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet); - void (*update_ra_mask_handler)(_adapter *padapter, struct sta_info *psta, struct macid_cfg *h2c_macid_cfg); void (*SetBeaconRelatedRegistersHandler)(_adapter *padapter); u8(*interface_ps_func)(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val); u32(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask); void (*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); - u32(*read_rfreg)(_adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask); - void (*write_rfreg)(_adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); + u32 (*read_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask); + void (*write_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data); + void (*read_wmmedca_reg)(_adapter *padapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params); + #ifdef CONFIG_HOSTAPD_MLME s32(*hostap_mgnt_xmit_entry)(_adapter *padapter, _pkt *pkt); #endif @@ -434,6 +417,10 @@ struct hal_ops { void (*hal_set_l1ssbackdoor_handler)(_adapter *padapter, u8 enable); #endif +#ifdef CONFIG_RFKILL_POLL + bool (*hal_radio_onoff_check)(_adapter *adapter, u8 *valid); +#endif + }; typedef enum _RT_EEPROM_TYPE { @@ -618,16 +605,17 @@ void rtw_hal_free_data(_adapter *padapter); void rtw_hal_dm_init(_adapter *padapter); void rtw_hal_dm_deinit(_adapter *padapter); +#ifdef CONFIG_RTW_SW_LED void rtw_hal_sw_led_init(_adapter *padapter); void rtw_hal_sw_led_deinit(_adapter *padapter); - +#endif u32 rtw_hal_power_on(_adapter *padapter); void rtw_hal_power_off(_adapter *padapter); uint rtw_hal_init(_adapter *padapter); uint rtw_hal_deinit(_adapter *padapter); void rtw_hal_stop(_adapter *padapter); -void rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val); +u8 rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val); void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val); void rtw_hal_chip_configure(_adapter *padapter); @@ -672,8 +660,7 @@ void rtw_hal_free_xmit_priv(_adapter *padapter); s32 rtw_hal_init_recv_priv(_adapter *padapter); void rtw_hal_free_recv_priv(_adapter *padapter); -void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level, u8 is_update_bw); -void rtw_update_ramask(_adapter *padapter, struct sta_info *psta, u32 mac_id, u8 rssi_level, u8 is_update_bw); +void rtw_hal_update_ra_mask(struct sta_info *psta); void rtw_hal_start_thread(_adapter *padapter); void rtw_hal_stop_thread(_adapter *padapter); @@ -682,8 +669,8 @@ void rtw_hal_bcn_related_reg_setting(_adapter *padapter); u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask); void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); -u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask); -void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); +u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask); +void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data); #define phy_query_bb_reg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask)) @@ -702,7 +689,7 @@ void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMa void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf); #endif -void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); +void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80); void rtw_hal_dm_watchdog(_adapter *padapter); void rtw_hal_dm_watchdog_in_lps(_adapter *padapter); @@ -755,8 +742,10 @@ s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter); -s32 rtw_hal_macid_sleep(PADAPTER padapter, u8 macid); -s32 rtw_hal_macid_wakeup(PADAPTER padapter, u8 macid); +s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid); +s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid); +s32 rtw_hal_macid_sleep_all_used(_adapter *adapter); +s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter); s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen, @@ -776,8 +765,9 @@ s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan); void rtw_hal_clear_interrupt(_adapter *padapter); #endif -void rtw_hal_set_tx_power_index(PADAPTER, u32 powerindex, u8 rfpath, u8 rate); -u8 rtw_hal_get_tx_power_index(PADAPTER, u8 rfpath, u8 rate, u8 bandwidth, u8 channel,struct txpwr_idx_comp *tic); +void rtw_hal_set_tx_power_index(PADAPTER adapter, u32 powerindex, enum rf_path rfpath, u8 rate); +u8 rtw_hal_get_tx_power_index(PADAPTER adapter, enum rf_path + rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); u8 rtw_hal_ops_check(_adapter *padapter); @@ -787,4 +777,8 @@ u8 rtw_hal_ops_check(_adapter *padapter); s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem); #endif /* RTW_HALMAC */ +#ifdef CONFIG_RFKILL_POLL +bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid); +#endif + #endif /* __HAL_INTF_H__ */ diff --git a/include/hal_pg.h b/include/hal_pg.h index c60f7fc..ad6a557 100644 --- a/include/hal_pg.h +++ b/include/hal_pg.h @@ -29,8 +29,6 @@ /* **************************************************** * EEPROM/Efuse PG Offset for 88EE/88EU/88ES * **************************************************** */ -#define EEPROM_TX_PWR_INX_88E 0x10 - #define EEPROM_ChannelPlan_88E 0xB8 #define EEPROM_XTAL_88E 0xB9 #define EEPROM_THERMAL_METER_88E 0xBA @@ -69,9 +67,6 @@ #define PPG_BB_GAIN_2G_TXA_OFFSET_8192E 0x1F6 #define PPG_THERMAL_OFFSET_8192E 0x1F5 -/* 0x10 ~ 0x63 = TX power area. */ -#define EEPROM_TX_PWR_INX_8192E 0x10 - #define EEPROM_ChannelPlan_8192E 0xB8 #define EEPROM_XTAL_8192E 0xB9 #define EEPROM_THERMAL_METER_8192E 0xBA @@ -112,10 +107,8 @@ #define EEPROM_MAC_ADDR_8192ES 0x11A /* **************************************************** * EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS - * **************************************************** - * 0x10 ~ 0x63 = TX power area. */ + * *****************************************************/ #define EEPROM_USB_MODE_8812 0x08 -#define EEPROM_TX_PWR_INX_8812 0x10 #define EEPROM_ChannelPlan_8812 0xB8 #define EEPROM_XTAL_8812 0xB9 @@ -180,7 +173,6 @@ #define PPG_THERMAL_OFFSET_8814A 0x3EF -#define EEPROM_TX_PWR_INX_8814 0x10 #define EEPROM_USB_MODE_8814A 0x0E #define EEPROM_ChannelPlan_8814 0xB8 #define EEPROM_XTAL_8814 0xB9 @@ -228,8 +220,6 @@ #define PPG_BB_GAIN_5GMB2_TXA_OFFSET_8821A 0x1F1 #define PPG_BB_GAIN_5GHB_TXA_OFFSET_8821A 0x1F0 -#define EEPROM_TX_PWR_INX_8821 0x10 - #define EEPROM_ChannelPlan_8821 0xB8 #define EEPROM_XTAL_8821 0xB9 #define EEPROM_THERMAL_METER_8821 0xBA @@ -297,9 +287,6 @@ #define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xEE #define PPG_THERMAL_OFFSET_8188F 0xEF -/* 0x10 ~ 0x63 = TX power area. */ -#define EEPROM_TX_PWR_INX_8188F 0x10 - #define EEPROM_ChannelPlan_8188F 0xB8 #define EEPROM_XTAL_8188F 0xB9 #define EEPROM_THERMAL_METER_8188F 0xBA @@ -335,10 +322,7 @@ /* **************************************************** * EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS - * **************************************************** - * 0x10 ~ 0x63 = TX power area. */ -#define EEPROM_TX_PWR_INX_8723B 0x10 - + * *****************************************************/ #define EEPROM_ChannelPlan_8723B 0xB8 #define EEPROM_XTAL_8723B 0xB9 #define EEPROM_THERMAL_METER_8723B 0xBA @@ -386,8 +370,6 @@ #define PPG_BB_GAIN_2G_TXA_OFFSET_8703B 0xEE #define PPG_THERMAL_OFFSET_8703B 0xEF -#define EEPROM_TX_PWR_INX_8703B 0x10 - #define EEPROM_ChannelPlan_8703B 0xB8 #define EEPROM_XTAL_8703B 0xB9 #define EEPROM_THERMAL_METER_8703B 0xBA @@ -424,8 +406,6 @@ * EEPROM/Efuse PG Offset for 8822B * ==================================================== */ -#define EEPROM_TX_PWR_INX_8822B 0x10 - #define EEPROM_ChannelPlan_8822B 0xB8 #define EEPROM_XTAL_8822B 0xB9 #define EEPROM_THERMAL_METER_8822B 0xBA @@ -468,8 +448,6 @@ * EEPROM/Efuse PG Offset for 8821C * ==================================================== */ -#define EEPROM_TX_PWR_INX_8821C 0x10 - #define EEPROM_CHANNEL_PLAN_8821C 0xB8 #define EEPROM_XTAL_8821C 0xB9 #define EEPROM_THERMAL_METER_8821C 0xBA @@ -523,8 +501,6 @@ #define PPG_BB_GAIN_2G_TX_OFFSET_8723D 0x1EE #define PPG_THERMAL_OFFSET_8723D 0xEF -#define EEPROM_TX_PWR_INX_8723D 0x10 - #define EEPROM_ChannelPlan_8723D 0xB8 #define EEPROM_XTAL_8723D 0xB9 #define EEPROM_THERMAL_METER_8723D 0xBA diff --git a/include/hal_phy.h b/include/hal_phy.h index 2c3c321..342613b 100644 --- a/include/hal_phy.h +++ b/include/hal_phy.h @@ -51,15 +51,15 @@ /*--------------------------Define Parameters-------------------------------*/ -typedef enum _RF_TYPE { - RF_TYPE_MIN = 0, /* 0 */ +typedef enum _RF_CHIP { + RF_CHIP_MIN = 0, /* 0 */ RF_8225 = 1, /* 1 11b/g RF for verification only */ RF_8256 = 2, /* 2 11b/g/n */ RF_8258 = 3, /* 3 11a/b/g/n RF */ RF_6052 = 4, /* 4 11b/g/n RF */ RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */ - RF_TYPE_MAX -} RF_TYPE_E, *PRF_TYPE_E; + RF_CHIP_MAX +} RF_CHIP_E, *PRF_CHIP_E; typedef enum _ANTENNA_PATH { ANTENNA_NONE = 0, @@ -151,6 +151,14 @@ typedef struct _R_ANTENNA_SELECT_CCK { u8 r_ccktx_enable:4; } R_ANTENNA_SELECT_CCK; + +/*--------------------------Exported Function prototype---------------------*/ +u32 +PHY_CalculateBitShift( + u32 BitMask +); + +#ifdef CONFIG_RF_SHADOW_RW typedef struct RF_Shadow_Compare_Map { /* Shadow register value */ u32 Value; @@ -164,36 +172,29 @@ typedef struct RF_Shadow_Compare_Map { u8 Driver_Write; } RF_SHADOW_T; -/*--------------------------Exported Function prototype---------------------*/ - -u32 -PHY_CalculateBitShift( - u32 BitMask -); - u32 PHY_RFShadowRead( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset); VOID PHY_RFShadowWrite( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset, IN u32 Data); BOOLEAN PHY_RFShadowCompare( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset); VOID PHY_RFShadowRecorver( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset); VOID @@ -207,14 +208,14 @@ PHY_RFShadowRecorverAll( VOID PHY_RFShadowCompareFlagSet( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset, IN u8 Type); VOID PHY_RFShadowRecorverFlagSet( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset, IN u8 Type); @@ -229,5 +230,5 @@ PHY_RFShadowRecorverFlagSetAll( VOID PHY_RFShadowRefresh( IN PADAPTER Adapter); - +#endif /*#CONFIG_RF_SHADOW_RW*/ #endif /* __HAL_COMMON_H__ */ diff --git a/include/ieee80211.h b/include/ieee80211.h index 05a4c51..5ba92b5 100644 --- a/include/ieee80211.h +++ b/include/ieee80211.h @@ -201,7 +201,7 @@ enum NETWORK_TYPE { WIRELESS_11A_5N = (WIRELESS_11A | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ WIRELESS_11B_24N = (WIRELESS_11B | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ WIRELESS_11BG_24N = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ - WIRELESS_11_24AC = (WIRELESS_11G | WIRELESS_11AC), + WIRELESS_11_24AC = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11AC), WIRELESS_11_5AC = (WIRELESS_11A | WIRELESS_11AC), @@ -391,6 +391,28 @@ struct eapol { u16 length; } __attribute__((packed)); +struct rtw_ieee80211s_hdr { + u8 flags; + u8 ttl; + u32 seqnum; + u8 eaddr1[ETH_ALEN]; + u8 eaddr2[ETH_ALEN]; +} __attribute__((packed)); + +/** + * struct rtw_ieee80211_rann_ie + * + * This structure refers to "Root Announcement information element" + */ + struct rtw_ieee80211_rann_ie { + u8 rann_flags; + u8 rann_hopcount; + u8 rann_ttl; + u8 rann_addr[ETH_ALEN]; + u32 rann_seq; + u32 rann_interval; + u32 rann_metric; +} __attribute__((packed)); #endif @@ -631,10 +653,33 @@ struct ieee80211_snap_hdr { #define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 #define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 #define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 +#define WLAN_REASON_MESH_PEER_CANCELED 52 +#define WLAN_REASON_MESH_MAX_PEERS 53 +#define WLAN_REASON_MESH_CONFIG 54 +#define WLAN_REASON_MESH_CLOSE 55 +#define WLAN_REASON_MESH_MAX_RETRIES 56 +#define WLAN_REASON_MESH_CONFIRM_TIMEOUT 57 +#define WLAN_REASON_MESH_INVALID_GTK 58 +#define WLAN_REASON_MESH_INCONSISTENT_PARAM 59 +#define WLAN_REASON_MESH_INVALID_SECURITY 60 +#define WLAN_REASON_MESH_PATH_NOPROXY 61 +#define WLAN_REASON_MESH_PATH_NOFORWARD 62 +#define WLAN_REASON_MESH_PATH_DEST_UNREACHABLE 63 +#define WLAN_REASON_MAC_EXISTS_IN_MBSS 64 +#define WLAN_REASON_MESH_CHAN_REGULATORY 65 +#define WLAN_REASON_MESH_CHAN 66 +#define WLAN_REASON_SA_QUERY_TIMEOUT 65532 #define WLAN_REASON_ACTIVE_ROAM 65533 #define WLAN_REASON_JOIN_WRONG_CHANNEL 65534 #define WLAN_REASON_EXPIRATION_CHK 65535 +#define WLAN_REASON_IS_PRIVATE(reason) ( \ + reason == WLAN_REASON_EXPIRATION_CHK \ + || reason == WLAN_REASON_JOIN_WRONG_CHANNEL \ + || reason == WLAN_REASON_ACTIVE_ROAM \ + || reason == WLAN_REASON_SA_QUERY_TIMEOUT \ + ) + /* Information Element IDs */ #define WLAN_EID_SSID 0 #define WLAN_EID_SUPP_RATES 1 @@ -670,6 +715,15 @@ struct ieee80211_snap_hdr { #define WLAN_EID_20_40_BSS_INTOLERANT 73 #define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74 #define WLAN_EID_MMIE 76 +#define WLAN_EID_MESH_CONFIG 113 +#define WLAN_EID_MESH_ID 114 +#define WLAN_EID_MPM 117 +#define WLAN_EID_RANN 126 +#define WLAN_EID_PREQ 130 +#define WLAN_EID_PREP 131 +#define WLAN_EID_PERR 132 +#define WLAN_EID_AMPE 139 +#define WLAN_EID_MIC 140 #define WLAN_EID_VENDOR_SPECIFIC 221 #define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC) #define WLAN_EID_VHT_CAPABILITY 191 @@ -1099,11 +1153,8 @@ struct ieee80211_softmac_stats { #define WEP_KEYS 4 #define WEP_KEY_LEN 13 - -#ifdef CONFIG_IEEE80211W - #define BIP_MAX_KEYID 5 - #define BIP_AAD_SIZE 20 -#endif /* CONFIG_IEEE80211W */ +#define BIP_MAX_KEYID 5 +#define BIP_AAD_SIZE 20 #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) @@ -1537,19 +1588,34 @@ enum rtw_ieee80211_category { RTW_WLAN_CATEGORY_DLS = 2, RTW_WLAN_CATEGORY_BACK = 3, RTW_WLAN_CATEGORY_PUBLIC = 4, /* IEEE 802.11 public action frames */ - RTW_WLAN_CATEGORY_RADIO_MEASUREMENT = 5, + RTW_WLAN_CATEGORY_RADIO_MEAS = 5, RTW_WLAN_CATEGORY_FT = 6, RTW_WLAN_CATEGORY_HT = 7, RTW_WLAN_CATEGORY_SA_QUERY = 8, RTW_WLAN_CATEGORY_WNM = 10, RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, /* add for CONFIG_IEEE80211W, none 11w also can use */ RTW_WLAN_CATEGORY_TDLS = 12, - RTW_WLAN_CATEGORY_SELF_PROTECTED = 15, /* add for CONFIG_IEEE80211W, none 11w also can use */ + RTW_WLAN_CATEGORY_MESH = 13, + RTW_WLAN_CATEGORY_MULTIHOP = 14, + RTW_WLAN_CATEGORY_SELF_PROTECTED = 15, RTW_WLAN_CATEGORY_WMM = 17, RTW_WLAN_CATEGORY_VHT = 21, RTW_WLAN_CATEGORY_P2P = 0x7f,/* P2P action frames */ }; +#define CATEGORY_IS_GROUP_PRIVACY(cat) \ + (cat == RTW_WLAN_CATEGORY_MESH || cat == RTW_WLAN_CATEGORY_MULTIHOP) + +#define CATEGORY_IS_NON_ROBUST(cat) \ + (cat == RTW_WLAN_CATEGORY_PUBLIC \ + || cat == RTW_WLAN_CATEGORY_HT \ + || cat == RTW_WLAN_CATEGORY_UNPROTECTED_WNM \ + || cat == RTW_WLAN_CATEGORY_SELF_PROTECTED \ + || cat == RTW_WLAN_CATEGORY_VHT \ + || cat == RTW_WLAN_CATEGORY_P2P) + +#define CATEGORY_IS_ROBUST(cat) !CATEGORY_IS_NON_ROBUST(cat) + /* SPECTRUM_MGMT action code */ enum rtw_ieee80211_spectrum_mgmt_actioncode { RTW_WLAN_ACTION_SPCT_MSR_REQ = 0, @@ -1560,6 +1626,32 @@ enum rtw_ieee80211_spectrum_mgmt_actioncode { RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, }; +/* SELF_PROTECTED action code */ +enum rtw_ieee80211_self_protected_actioncode { + RTW_ACT_SELF_PROTECTED_RSVD = 0, + RTW_ACT_SELF_PROTECTED_MESH_OPEN = 1, + RTW_ACT_SELF_PROTECTED_MESH_CONF = 2, + RTW_ACT_SELF_PROTECTED_MESH_CLOSE = 3, + RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM = 4, + RTW_ACT_SELF_PROTECTED_MESH_GK_ACK = 5, + RTW_ACT_SELF_PROTECTED_NUM, +}; + +/* MESH action code */ +enum rtw_ieee80211_mesh_actioncode { + RTW_ACT_MESH_LINK_METRIC_REPORT, + RTW_ACT_MESH_HWMP_PATH_SELECTION, + RTW_ACT_MESH_GATE_ANNOUNCEMENT, + RTW_ACT_MESH_CONGESTION_CONTROL_NOTIFICATION, + RTW_ACT_MESH_MCCA_SETUP_REQUEST, + RTW_ACT_MESH_MCCA_SETUP_REPLY, + RTW_ACT_MESH_MCCA_ADVERTISEMENT_REQUEST, + RTW_ACT_MESH_MCCA_ADVERTISEMENT, + RTW_ACT_MESH_MCCA_TEARDOWN, + RTW_ACT_MESH_TBTT_ADJUSTMENT_REQUEST, + RTW_ACT_MESH_TBTT_ADJUSTMENT_RESPONSE, +}; + enum _PUBLIC_ACTION { ACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */ ACT_PUBLIC_DSE_ENABLE = 1, @@ -1644,14 +1736,22 @@ enum rtw_ieee80211_vht_actioncode { #ifdef CONFIG_RTW_80211R enum rtw_ieee80211_ft_actioncode { RTW_WLAN_ACTION_FT_RESV, - RTW_WLAN_ACTION_FT_REQUEST, - RTW_WLAN_ACTION_FT_RESPONSE, - RTW_WLAN_ACTION_FT_CONFIRM, + RTW_WLAN_ACTION_FT_REQ, + RTW_WLAN_ACTION_FT_RSP, + RTW_WLAN_ACTION_FT_CONF, RTW_WLAN_ACTION_FT_ACK, RTW_WLAN_ACTION_FT_MAX, }; #endif +#ifdef CONFIG_RTW_WNM +enum rtw_ieee80211_wnm_actioncode { + RTW_WLAN_ACTION_WNM_BTM_QUERY = 6, + RTW_WLAN_ACTION_WNM_BTM_REQ = 7, + RTW_WLAN_ACTION_WNM_BTM_RSP = 8, +}; +#endif + #define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs) * 00:50:F2 */ #ifndef PLATFORM_FREEBSD /* Baron BSD has defined */ @@ -1679,6 +1779,55 @@ enum rtw_ieee80211_ft_actioncode { #define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */ +enum rtw_ieee80211_rann_flags { + RTW_RANN_FLAG_IS_GATE = 1 << 0, +}; + +/** + * enum rtw_ieee80211_preq_flags - mesh PREQ element flags + * + * @RTW_IEEE80211_PREQ_IS_GATE_FLAG: Gate Announcement subfield + * @RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG: proactive PREP subfield + */ +enum rtw_ieee80211_preq_flags { + RTW_IEEE80211_PREQ_IS_GATE_FLAG = 1 << 0, + RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG = 1 << 2, +}; + +/** + * enum rtw_ieee80211_preq_target_flags - mesh PREQ element per target flags + * + * @RTW_IEEE80211_PREQ_TO_FLAG: target only subfield + * @RTW_IEEE80211_PREQ_USN_FLAG: unknown target HWMP sequence number subfield + */ +enum rtw_ieee80211_preq_target_flags { + RTW_IEEE80211_PREQ_TO_FLAG = 1<<0, + RTW_IEEE80211_PREQ_USN_FLAG = 1<<2, +}; + +/** + * enum rtw_ieee80211_root_mode_identifier - root mesh STA mode identifier + * + * These attribute are used by dot11MeshHWMPRootMode to set root mesh STA mode + * + * @RTW_IEEE80211_ROOTMODE_NO_ROOT: the mesh STA is not a root mesh STA (default) + * @RTW_IEEE80211_ROOTMODE_ROOT: the mesh STA is a root mesh STA if greater than + * this value + * @RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP: the mesh STA is a root mesh STA supports + * the proactive PREQ with proactive PREP subfield set to 0 + * @RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP: the mesh STA is a root mesh STA + * supports the proactive PREQ with proactive PREP subfield set to 1 + * @RTW_IEEE80211_PROACTIVE_RANN: the mesh STA is a root mesh STA supports + * the proactive RANN + */ +enum rtw_ieee80211_root_mode_identifier { + RTW_IEEE80211_ROOTMODE_NO_ROOT = 0, + RTW_IEEE80211_ROOTMODE_ROOT = 1, + RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP = 2, + RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP = 3, + RTW_IEEE80211_PROACTIVE_RANN = 4, +}; + /** * enum rtw_ieee80211_channel_flags - channel flags * @@ -1801,6 +1950,18 @@ struct rtw_ieee802_11_elems { u8 vht_operation_len; u8 *vht_op_mode_notify; u8 vht_op_mode_notify_len; + u8 *rm_en_cap; + u8 rm_en_cap_len; +#ifdef CONFIG_RTW_MESH + u8 *preq; + u8 preq_len; + u8 *prep; + u8 prep_len; + u8 *perr; + u8 perr_len; + u8 *rann; + u8 rann_len; +#endif }; typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes; @@ -1810,7 +1971,7 @@ ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, int show_errors); u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen); -u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen); +u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, const u8 *source, uint *frlen); enum secondary_ch_offset { SCN = 0, /* no secondary channel */ @@ -1823,25 +1984,47 @@ u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, u8 new_ch, u8 u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset); u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence); -u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit); -u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen); +u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit); +u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen); int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len); void rtw_set_supported_rate(u8 *SupportedRates, uint mode) ; +#define GET_RSN_CAP_MFP_OPTION(cap) LE_BITS_TO_2BYTE(((u8 *)(cap)), 6, 2) + +#define MFP_NO 0 +#define MFP_INVALID 1 +#define MFP_OPTIONAL 2 +#define MFP_REQUIRED 3 + +struct rsne_info { + u8 *gcs; + u16 pcs_cnt; + u8 *pcs_list; + u16 akm_cnt; + u8 *akm_list; + u8 *cap; + u16 pmkid_cnt; + u8 *pmkid_list; + u8 *gmcs; + + u8 err; +}; +int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info); + unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit); unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit); int rtw_get_wpa_cipher_suite(u8 *s); int rtw_get_wpa2_cipher_suite(u8 *s); int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len); int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); -int rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); +int rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x, u8 *mfp_opt); int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len); u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen); -u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, u8 frame_type); -u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen); +u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type); +u8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen); u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_attr, u32 *len_attr); u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_content, uint *len_content); @@ -1854,17 +2037,21 @@ u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 #define for_each_ie(ie, buf, buf_len) \ for (ie = (void *)buf; (((u8 *)ie) - ((u8 *)buf) + 1) < buf_len; ie = (void *)(((u8 *)ie) + *(((u8 *)ie)+1) + 2)) -void dump_ies(void *sel, u8 *buf, u32 buf_len); +void dump_ies(void *sel, const u8 *buf, u32 buf_len); #ifdef CONFIG_80211N_HT -void dump_ht_cap_ie_content(void *sel, u8 *buf, u32 buf_len); +#define HT_SC_OFFSET_MAX 4 +extern const char *const _ht_sc_offset_str[]; +#define ht_sc_offset_str(sc) (((sc) >= HT_SC_OFFSET_MAX) ? _ht_sc_offset_str[2] : _ht_sc_offset_str[(sc)]) + +void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len); #endif -void dump_wps_ie(void *sel, u8 *ie, u32 ie_len); +void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len); -void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset); +void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht); -void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset); +void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht); bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a , u8 ch_b, u8 bw_b, u8 offset_b); @@ -1873,8 +2060,8 @@ void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len); int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie); -void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len); -u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen); +void dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len); +u8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen); u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr); u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content); u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr); @@ -1884,8 +2071,8 @@ u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen); void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex); void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id); -void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len); -u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen); +void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len); +u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen); u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr); u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content); uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg); diff --git a/include/mlme_osdep.h b/include/mlme_osdep.h index 291ecd2..131eb09 100644 --- a/include/mlme_osdep.h +++ b/include/mlme_osdep.h @@ -15,11 +15,6 @@ #ifndef __MLME_OSDEP_H_ #define __MLME_OSDEP_H_ - -#if defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) - extern int time_after(u32 now, u32 old); -#endif - extern void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated); extern void rtw_os_indicate_connect(_adapter *adapter); void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted); diff --git a/include/osdep_service.h b/include/osdep_service.h index 7756685..442f0a7 100644 --- a/include/osdep_service.h +++ b/include/osdep_service.h @@ -15,11 +15,6 @@ #ifndef __OSDEP_SERVICE_H_ #define __OSDEP_SERVICE_H_ -//EDX_S -#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) -#include -#endif -//EDX_E #define _FAIL 0 #define _SUCCESS 1 @@ -29,6 +24,9 @@ #define RTW_RBUF_UNAVAIL 5 #define RTW_RBUF_PKT_UNAVAIL 6 #define RTW_SDIO_READ_PORT_FAIL 7 +#define RTW_ALREADY 8 +#define RTW_RA_RESOLVING 9 +#define RTW_BMC_NO_NEED 10 /* #define RTW_STATUS_TIMEDOUT -110 */ @@ -44,6 +42,11 @@ #endif #ifdef PLATFORM_LINUX + #include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) + #include + #include +#endif #include #endif @@ -137,12 +140,13 @@ typedef enum mstat_status { #ifdef DBG_MEM_ALLOC void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz); void rtw_mstat_dump(void *sel); -u8 *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); -u8 *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); -void dbg_rtw_vmfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); -u8 *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line); -u8 *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); -void dbg_rtw_mfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); +bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size); +void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_vmfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); +void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_mfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line); void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); @@ -209,12 +213,13 @@ void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dm #else /* DBG_MEM_ALLOC */ #define rtw_mstat_update(flag, status, sz) do {} while (0) #define rtw_mstat_dump(sel) do {} while (0) -u8 *_rtw_vmalloc(u32 sz); -u8 *_rtw_zvmalloc(u32 sz); -void _rtw_vmfree(u8 *pbuf, u32 sz); -u8 *_rtw_zmalloc(u32 sz); -u8 *_rtw_malloc(u32 sz); -void _rtw_mfree(u8 *pbuf, u32 sz); +#define match_mstat_sniff_rules(flags, size) _FALSE +void *_rtw_vmalloc(u32 sz); +void *_rtw_zvmalloc(u32 sz); +void _rtw_vmfree(void *pbuf, u32 sz); +void *_rtw_zmalloc(u32 sz); +void *_rtw_malloc(u32 sz); +void _rtw_mfree(void *pbuf, u32 sz); struct sk_buff *_rtw_skb_alloc(u32 sz); void _rtw_skb_free(struct sk_buff *skb); @@ -283,6 +288,11 @@ void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_a extern void *rtw_malloc2d(int h, int w, size_t size); extern void rtw_mfree2d(void *pbuf, int h, int w, int size); +void rtw_os_pkt_free(_pkt *pkt); +_pkt *rtw_os_pkt_copy(_pkt *pkt); +void *rtw_os_pkt_data(_pkt *pkt); +u32 rtw_os_pkt_len(_pkt *pkt); + extern void _rtw_memcpy(void *dec, const void *sour, u32 sz); extern void _rtw_memmove(void *dst, const void *src, u32 sz); extern int _rtw_memcmp(const void *dst, const void *src, u32 sz); @@ -292,10 +302,20 @@ extern void _rtw_init_listhead(_list *list); extern u32 rtw_is_list_empty(_list *phead); extern void rtw_list_insert_head(_list *plist, _list *phead); extern void rtw_list_insert_tail(_list *plist, _list *phead); +void rtw_list_splice(_list *list, _list *head); +void rtw_list_splice_init(_list *list, _list *head); +void rtw_list_splice_tail(_list *list, _list *head); + #ifndef PLATFORM_FREEBSD extern void rtw_list_delete(_list *plist); #endif /* PLATFORM_FREEBSD */ +void rtw_hlist_head_init(rtw_hlist_head *h); +void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h); +void rtw_hlist_del(rtw_hlist_node *n); +void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h); +void rtw_hlist_del_rcu(rtw_hlist_node *n); + extern void _rtw_init_sema(_sema *sema, int init_val); extern void _rtw_free_sema(_sema *sema); extern void _rtw_up_sema(_sema *sema); @@ -316,11 +336,36 @@ extern void _rtw_deinit_queue(_queue *pqueue); extern u32 _rtw_queue_empty(_queue *pqueue); extern u32 rtw_end_of_queue_search(_list *queue, _list *pelement); -extern u32 rtw_get_current_time(void); -extern u32 rtw_systime_to_ms(u32 systime); -extern u32 rtw_ms_to_systime(u32 ms); -extern s32 rtw_get_passing_time_ms(u32 start); -extern s32 rtw_get_time_interval_ms(u32 start, u32 end); +extern systime _rtw_get_current_time(void); +extern u32 _rtw_systime_to_ms(systime stime); +extern systime _rtw_ms_to_systime(u32 ms); +extern systime _rtw_us_to_systime(u32 us); +extern s32 _rtw_get_passing_time_ms(systime start); +extern s32 _rtw_get_remaining_time_ms(systime end); +extern s32 _rtw_get_time_interval_ms(systime start, systime end); +extern bool _rtw_time_after(systime a, systime b); + +#ifdef DBG_SYSTIME +#define rtw_get_current_time() ({systime __stime = _rtw_get_current_time(); __stime;}) +#define rtw_systime_to_ms(stime) ({u32 __ms = _rtw_systime_to_ms(stime); typecheck(systime, stime); __ms;}) +#define rtw_ms_to_systime(ms) ({systime __stime = _rtw_ms_to_systime(ms); __stime;}) +#define rtw_us_to_systime(us) ({systime __stime = _rtw_us_to_systime(us); __stime;}) +#define rtw_get_passing_time_ms(start) ({u32 __ms = _rtw_get_passing_time_ms(start); typecheck(systime, start); __ms;}) +#define rtw_get_remaining_time_ms(end) ({u32 __ms = _rtw_get_remaining_time_ms(end); typecheck(systime, end); __ms;}) +#define rtw_get_time_interval_ms(start, end) ({u32 __ms = _rtw_get_time_interval_ms(start, end); typecheck(systime, start); typecheck(systime, end); __ms;}) +#define rtw_time_after(a,b) ({bool __r = _rtw_time_after(a,b); typecheck(systime, a); typecheck(systime, b); __r;}) +#define rtw_time_before(a,b) ({bool __r = _rtw_time_after(b, a); typecheck(systime, a); typecheck(systime, b); __r;}) +#else +#define rtw_get_current_time() _rtw_get_current_time() +#define rtw_systime_to_ms(stime) _rtw_systime_to_ms(stime) +#define rtw_ms_to_systime(ms) _rtw_ms_to_systime(ms) +#define rtw_us_to_systime(us) _rtw_us_to_systime(us) +#define rtw_get_passing_time_ms(start) _rtw_get_passing_time_ms(start) +#define rtw_get_remaining_time_ms(end) _rtw_get_remaining_time_ms(end) +#define rtw_get_time_interval_ms(start, end) _rtw_get_time_interval_ms(start, end) +#define rtw_time_after(a,b) _rtw_time_after(a,b) +#define rtw_time_before(a,b) _rtw_time_after(b,a) +#endif extern void rtw_sleep_schedulable(int ms); @@ -550,10 +595,7 @@ extern void rtw_suspend_lock_uninit(void); extern void rtw_lock_suspend(void); extern void rtw_unlock_suspend(void); extern void rtw_lock_suspend_timeout(u32 timeout_ms); -extern void rtw_lock_ext_suspend_timeout(u32 timeout_ms); -extern void rtw_lock_rx_suspend_timeout(u32 timeout_ms); extern void rtw_lock_traffic_suspend_timeout(u32 timeout_ms); -extern void rtw_lock_resume_scan_timeout(u32 timeout_ms); extern void rtw_resume_lock_suspend(void); extern void rtw_resume_unlock_suspend(void); #ifdef CONFIG_AP_WOWLAN @@ -561,6 +603,10 @@ extern void rtw_softap_lock_suspend(void); extern void rtw_softap_unlock_suspend(void); #endif +extern void rtw_set_bit(int nr, unsigned long *addr); +extern void rtw_clear_bit(int nr, unsigned long *addr); +extern int rtw_test_and_clear_bit(int nr, unsigned long *addr); + extern void ATOMIC_SET(ATOMIC_T *v, int i); extern int ATOMIC_READ(ATOMIC_T *v); extern void ATOMIC_ADD(ATOMIC_T *v, int i); @@ -571,6 +617,7 @@ extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i); extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i); extern int ATOMIC_INC_RETURN(ATOMIC_T *v); extern int ATOMIC_DEC_RETURN(ATOMIC_T *v); +extern bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u); /* File operation APIs, just for linux now */ extern int rtw_is_file_readable(const char *path); @@ -653,6 +700,17 @@ extern u32 rtw_random32(void); (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \ (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \ (((u64) (a)[1]) << 8) | ((u64) (a)[0])) +#define RTW_PUT_LE64(a, val) \ + do { \ + (a)[7] = (u8) ((((u64) (val)) >> 56) & 0xff); \ + (a)[6] = (u8) ((((u64) (val)) >> 48) & 0xff); \ + (a)[5] = (u8) ((((u64) (val)) >> 40) & 0xff); \ + (a)[4] = (u8) ((((u64) (val)) >> 32) & 0xff); \ + (a)[3] = (u8) ((((u64) (val)) >> 24) & 0xff); \ + (a)[2] = (u8) ((((u64) (val)) >> 16) & 0xff); \ + (a)[1] = (u8) ((((u64) (val)) >> 8) & 0xff); \ + (a)[0] = (u8) (((u64) (val)) & 0xff); \ + } while (0) void rtw_buf_free(u8 **buf, u32 *buf_len); void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len); @@ -696,6 +754,18 @@ struct map_t { int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf); u8 map_read8(const struct map_t *map, u16 offset); +struct blacklist_ent { + _list list; + u8 addr[ETH_ALEN]; + systime exp_time; +}; + +int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms); +int rtw_blacklist_del(_queue *blist, const u8 *addr); +int rtw_blacklist_search(_queue *blist, const u8 *addr); +void rtw_blacklist_flush(_queue *blist); +void dump_blacklist(void *sel, _queue *blist, const char *title); + /* String handler */ BOOLEAN is_null(char c); @@ -706,6 +776,10 @@ BOOLEAN IsHexDigit(char chTmp); BOOLEAN is_alpha(char chTmp); char alpha_to_upper(char c); +int hex2num_i(char c); +int hex2byte_i(const char *hex); +int hexstr2bin(const char *hex, u8 *buf, size_t len); + /* * Write formatted output to sized buffer */ diff --git a/include/osdep_service_bsd.h b/include/osdep_service_bsd.h index f4ce7f8..4412963 100644 --- a/include/osdep_service_bsd.h +++ b/include/osdep_service_bsd.h @@ -12,654 +12,653 @@ * more details. * *****************************************************************************/ -#ifndef __OSDEP_BSD_SERVICE_H_ -#define __OSDEP_BSD_SERVICE_H_ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include "usbdevs.h" - -#define USB_DEBUG_VAR rum_debug -#include - -#if 1 //Baron porting from linux, it's all temp solution, needs to check again -#include -#include /* XXX for PCPU_GET */ -// typedef struct semaphore _sema; - typedef struct sema _sema; -// typedef spinlock_t _lock; - typedef struct mtx _lock; - typedef struct mtx _mutex; - typedef struct timer_list _timer; - struct list_head { - struct list_head *next, *prev; - }; - struct __queue { - struct list_head queue; - _lock lock; - }; - - //typedef struct sk_buff _pkt; - typedef struct mbuf _pkt; - typedef struct mbuf _buffer; - - typedef struct __queue _queue; - typedef struct list_head _list; - typedef int _OS_STATUS; - //typedef u32 _irqL; - typedef unsigned long _irqL; - typedef struct ifnet * _nic_hdl; - - typedef pid_t _thread_hdl_; -// typedef struct thread _thread_hdl_; - typedef void thread_return; - typedef void* thread_context; - - typedef void timer_hdl_return; - typedef void* timer_hdl_context; - typedef struct work_struct _workitem; - -#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) -/* emulate a modern version */ -#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35) - -#define WIRELESS_EXT -1 -#define HZ hz -#define spin_lock_irqsave mtx_lock_irqsave -#define spin_lock_bh mtx_lock_irqsave -#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));} -//#define IFT_RTW 0xf9 //ifnet allocate type for RTW -#define free_netdev if_free -#define LIST_CONTAINOR(ptr, type, member) \ - ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) -#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n)) -/* - * Linux timers are emulated using FreeBSD callout functions - * (and taskqueue functionality). - * - * Currently no timer stats functionality. - * - * See (linux_compat) processes.c - * - */ -struct timer_list { +#ifndef __OSDEP_BSD_SERVICE_H_ +#define __OSDEP_BSD_SERVICE_H_ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include "usbdevs.h" + +#define USB_DEBUG_VAR rum_debug +#include + +#if 1 //Baron porting from linux, it's all temp solution, needs to check again +#include +#include /* XXX for PCPU_GET */ +// typedef struct semaphore _sema; + typedef struct sema _sema; +// typedef spinlock_t _lock; + typedef struct mtx _lock; + typedef struct mtx _mutex; + typedef struct rtw_timer_list _timer; + struct list_head { + struct list_head *next, *prev; + }; + struct __queue { + struct list_head queue; + _lock lock; + }; + + typedef struct mbuf _pkt; + typedef struct mbuf _buffer; + + typedef struct __queue _queue; + typedef struct list_head _list; + typedef int _OS_STATUS; + //typedef u32 _irqL; + typedef unsigned long _irqL; + typedef struct ifnet * _nic_hdl; + + typedef pid_t _thread_hdl_; +// typedef struct thread _thread_hdl_; + typedef void thread_return; + typedef void* thread_context; + + typedef void timer_hdl_return; + typedef void* timer_hdl_context; + typedef struct work_struct _workitem; + +#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) +/* emulate a modern version */ +#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35) + +#define WIRELESS_EXT -1 +#define HZ hz +#define spin_lock_irqsave mtx_lock_irqsave +#define spin_lock_bh mtx_lock_irqsave +#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));} +//#define IFT_RTW 0xf9 //ifnet allocate type for RTW +#define free_netdev if_free +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) +#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n)) +/* + * Linux timers are emulated using FreeBSD callout functions + * (and taskqueue functionality). + * + * Currently no timer stats functionality. + * + * See (linux_compat) processes.c + * + */ +struct rtw_timer_list { struct callout callout; void (*function)(void *); void *arg; }; - -struct workqueue_struct; -struct work_struct; -typedef void (*work_func_t)(struct work_struct *work); -/* Values for the state of an item of work (work_struct) */ -typedef enum work_state { - WORK_STATE_UNSET = 0, - WORK_STATE_CALLOUT_PENDING = 1, - WORK_STATE_TASK_PENDING = 2, - WORK_STATE_WORK_CANCELLED = 3 -} work_state_t; - -struct work_struct { - struct task task; /* FreeBSD task */ - work_state_t state; /* the pending or otherwise state of work. */ - work_func_t func; -}; -#define spin_unlock_irqrestore mtx_unlock_irqrestore -#define spin_unlock_bh mtx_unlock_irqrestore -#define mtx_unlock_irqrestore(lock,x) mtx_unlock(lock); -extern void _rtw_spinlock_init(_lock *plock); - -//modify private structure to match freebsd -#define BITS_PER_LONG 32 -union ktime { - s64 tv64; -#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR) - struct { -#ifdef __BIG_ENDIAN - s32 sec, nsec; -#else - s32 nsec, sec; -#endif - } tv; -#endif -}; -#define kmemcheck_bitfield_begin(name) -#define kmemcheck_bitfield_end(name) -#define CHECKSUM_NONE 0 -typedef unsigned char *sk_buff_data_t; -typedef union ktime ktime_t; /* Kill this */ - -void rtw_mtx_lock(_lock *plock); - -void rtw_mtx_unlock(_lock *plock); - -/** - * struct sk_buff - socket buffer - * @next: Next buffer in list - * @prev: Previous buffer in list - * @sk: Socket we are owned by - * @tstamp: Time we arrived - * @dev: Device we arrived on/are leaving by - * @transport_header: Transport layer header - * @network_header: Network layer header - * @mac_header: Link layer header - * @_skb_refdst: destination entry (with norefcount bit) - * @sp: the security path, used for xfrm - * @cb: Control buffer. Free for use by every layer. Put private vars here - * @len: Length of actual data - * @data_len: Data length - * @mac_len: Length of link layer header - * @hdr_len: writable header length of cloned skb - * @csum: Checksum (must include start/offset pair) - * @csum_start: Offset from skb->head where checksumming should start - * @csum_offset: Offset from csum_start where checksum should be stored - * @local_df: allow local fragmentation - * @cloned: Head may be cloned (check refcnt to be sure) - * @nohdr: Payload reference only, must not modify header - * @pkt_type: Packet class - * @fclone: skbuff clone status - * @ip_summed: Driver fed us an IP checksum - * @priority: Packet queueing priority - * @users: User count - see {datagram,tcp}.c - * @protocol: Packet protocol from driver - * @truesize: Buffer size - * @head: Head of buffer - * @data: Data head pointer - * @tail: Tail pointer - * @end: End pointer - * @destructor: Destruct function - * @mark: Generic packet mark - * @nfct: Associated connection, if any - * @ipvs_property: skbuff is owned by ipvs - * @peeked: this packet has been seen already, so stats have been - * done for it, don't do them again - * @nf_trace: netfilter packet trace flag - * @nfctinfo: Relationship of this skb to the connection - * @nfct_reasm: netfilter conntrack re-assembly pointer - * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c - * @skb_iif: ifindex of device we arrived on - * @rxhash: the packet hash computed on receive - * @queue_mapping: Queue mapping for multiqueue devices - * @tc_index: Traffic control index - * @tc_verd: traffic control verdict - * @ndisc_nodetype: router type (from link layer) - * @dma_cookie: a cookie to one of several possible DMA operations - * done by skb DMA functions - * @secmark: security marking - * @vlan_tci: vlan tag control information - */ - -struct sk_buff { - /* These two members must be first. */ - struct sk_buff *next; - struct sk_buff *prev; - - ktime_t tstamp; - - struct sock *sk; - //struct net_device *dev; - struct ifnet *dev; - - /* - * This is the control buffer. It is free to use for every - * layer. Please put your private variables there. If you - * want to keep them across layers you have to do a skb_clone() - * first. This is owned by whoever has the skb queued ATM. - */ - char cb[48] __aligned(8); - - unsigned long _skb_refdst; -#ifdef CONFIG_XFRM - struct sec_path *sp; -#endif - unsigned int len, - data_len; - u16 mac_len, - hdr_len; - union { - u32 csum; - struct { - u16 csum_start; - u16 csum_offset; - }smbol2; - }smbol1; - u32 priority; - kmemcheck_bitfield_begin(flags1); - u8 local_df:1, - cloned:1, - ip_summed:2, - nohdr:1, - nfctinfo:3; - u8 pkt_type:3, - fclone:2, - ipvs_property:1, - peeked:1, - nf_trace:1; - kmemcheck_bitfield_end(flags1); - u16 protocol; - - void (*destructor)(struct sk_buff *skb); -#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) - struct nf_conntrack *nfct; - struct sk_buff *nfct_reasm; -#endif -#ifdef CONFIG_BRIDGE_NETFILTER - struct nf_bridge_info *nf_bridge; -#endif - - int skb_iif; -#ifdef CONFIG_NET_SCHED - u16 tc_index; /* traffic control index */ -#ifdef CONFIG_NET_CLS_ACT - u16 tc_verd; /* traffic control verdict */ -#endif -#endif - - u32 rxhash; - - kmemcheck_bitfield_begin(flags2); - u16 queue_mapping:16; -#ifdef CONFIG_IPV6_NDISC_NODETYPE - u8 ndisc_nodetype:2, - deliver_no_wcard:1; -#else - u8 deliver_no_wcard:1; -#endif - kmemcheck_bitfield_end(flags2); - - /* 0/14 bit hole */ - -#ifdef CONFIG_NET_DMA - dma_cookie_t dma_cookie; -#endif -#ifdef CONFIG_NETWORK_SECMARK - u32 secmark; -#endif - union { - u32 mark; - u32 dropcount; - }symbol3; - - u16 vlan_tci; - - sk_buff_data_t transport_header; - sk_buff_data_t network_header; - sk_buff_data_t mac_header; - /* These elements must be at the end, see alloc_skb() for details. */ - sk_buff_data_t tail; - sk_buff_data_t end; - unsigned char *head, - *data; - unsigned int truesize; - atomic_t users; -}; -struct sk_buff_head { - /* These two members must be first. */ - struct sk_buff *next; - struct sk_buff *prev; - - u32 qlen; - _lock lock; -}; -#define skb_tail_pointer(skb) skb->tail -static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len) -{ - unsigned char *tmp = skb_tail_pointer(skb); - //SKB_LINEAR_ASSERT(skb); - skb->tail += len; - skb->len += len; - return tmp; -} - -static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len) -{ - skb->len -= len; - if(skb->len < skb->data_len) - printf("%s(),%d,error!\n",__FUNCTION__,__LINE__); - return skb->data += len; -} -static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len) -{ - #ifdef PLATFORM_FREEBSD - return __skb_pull(skb, len); - #else - return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len); - #endif //PLATFORM_FREEBSD -} -static inline u32 skb_queue_len(const struct sk_buff_head *list_) -{ - return list_->qlen; -} -static inline void __skb_insert(struct sk_buff *newsk, - struct sk_buff *prev, struct sk_buff *next, - struct sk_buff_head *list) -{ - newsk->next = next; - newsk->prev = prev; - next->prev = prev->next = newsk; - list->qlen++; -} -static inline void __skb_queue_before(struct sk_buff_head *list, - struct sk_buff *next, - struct sk_buff *newsk) -{ - __skb_insert(newsk, next->prev, next, list); -} -static inline void skb_queue_tail(struct sk_buff_head *list, - struct sk_buff *newsk) -{ - mtx_lock(&list->lock); - __skb_queue_before(list, (struct sk_buff *)list, newsk); - mtx_unlock(&list->lock); -} -static inline struct sk_buff *skb_peek(struct sk_buff_head *list_) -{ - struct sk_buff *list = ((struct sk_buff *)list_)->next; - if (list == (struct sk_buff *)list_) - list = NULL; - return list; -} -static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list) -{ - struct sk_buff *next, *prev; - - list->qlen--; - next = skb->next; - prev = skb->prev; - skb->next = skb->prev = NULL; - next->prev = prev; - prev->next = next; -} - -static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list) -{ - mtx_lock(&list->lock); - - struct sk_buff *skb = skb_peek(list); - if (skb) - __skb_unlink(skb, list); - - mtx_unlock(&list->lock); - - return skb; -} -static inline void skb_reserve(struct sk_buff *skb, int len) -{ - skb->data += len; - skb->tail += len; -} -static inline void __skb_queue_head_init(struct sk_buff_head *list) -{ - list->prev = list->next = (struct sk_buff *)list; - list->qlen = 0; -} -/* - * This function creates a split out lock class for each invocation; - * this is needed for now since a whole lot of users of the skb-queue - * infrastructure in drivers have different locking usage (in hardirq) - * than the networking core (in softirq only). In the long run either the - * network layer or drivers should need annotation to consolidate the - * main types of usage into 3 classes. - */ -static inline void skb_queue_head_init(struct sk_buff_head *list) -{ - _rtw_spinlock_init(&list->lock); - __skb_queue_head_init(list); -} -unsigned long copy_from_user(void *to, const void *from, unsigned long n); -unsigned long copy_to_user(void *to, const void *from, unsigned long n); -struct sk_buff * dev_alloc_skb(unsigned int size); -struct sk_buff *skb_clone(const struct sk_buff *skb); -void dev_kfree_skb_any(struct sk_buff *skb); -#endif //Baron porting from linux, it's all temp solution, needs to check again - - -#if 1 // kenny add Linux compatibility code for Linux USB driver -#include - -#define __init // __attribute ((constructor)) -#define __exit // __attribute ((destructor)) - -/* - * Definitions for module_init and module_exit macros. - * - * These macros will use the SYSINIT framework to call a specified - * function (with no arguments) on module loading or unloading. - * - */ - -void module_init_exit_wrapper(void *arg); - -#define module_init(initfn) \ - SYSINIT(mod_init_ ## initfn, \ - SI_SUB_KLD, SI_ORDER_FIRST, \ - module_init_exit_wrapper, initfn) - -#define module_exit(exitfn) \ - SYSUNINIT(mod_exit_ ## exitfn, \ - SI_SUB_KLD, SI_ORDER_ANY, \ - module_init_exit_wrapper, exitfn) - -/* - * The usb_register and usb_deregister functions are used to register - * usb drivers with the usb subsystem. - */ -int usb_register(struct usb_driver *driver); -int usb_deregister(struct usb_driver *driver); - -/* - * usb_get_dev and usb_put_dev - increment/decrement the reference count - * of the usb device structure. - * - * Original body of usb_get_dev: - * - * if (dev) - * get_device(&dev->dev); - * return dev; - * - * Reference counts are not currently used in this compatibility - * layer. So these functions will do nothing. - */ -static inline struct usb_device * -usb_get_dev(struct usb_device *dev) -{ - return dev; -} - -static inline void -usb_put_dev(struct usb_device *dev) -{ - return; -} - - -// rtw_usb_compat_linux -int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags); -int rtw_usb_unlink_urb(struct urb *urb); -int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe); -int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe, - uint8_t request, uint8_t requesttype, - uint16_t value, uint16_t index, void *data, - uint16_t size, usb_timeout_t timeout); -int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index); -int rtw_usb_setup_endpoint(struct usb_device *dev, - struct usb_host_endpoint *uhe, usb_size_t bufsize); -struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags); -struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep); -struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index); -struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no); -void *rtw_usbd_get_intfdata(struct usb_interface *intf); -void rtw_usb_linux_register(void *arg); -void rtw_usb_linux_deregister(void *arg); -void rtw_usb_linux_free_device(struct usb_device *dev); -void rtw_usb_free_urb(struct urb *urb); -void rtw_usb_init_urb(struct urb *urb); -void rtw_usb_kill_urb(struct urb *urb); -void rtw_usb_set_intfdata(struct usb_interface *intf, void *data); -void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev, - struct usb_host_endpoint *uhe, void *buf, - int length, usb_complete_t callback, void *arg); -int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe, - void *data, int len, uint16_t *pactlen, usb_timeout_t timeout); -void *usb_get_intfdata(struct usb_interface *intf); -int usb_linux_init_endpoints(struct usb_device *udev); - - - -typedef struct urb * PURB; - -typedef unsigned gfp_t; -#define __GFP_WAIT ((gfp_t)0x10u) /* Can wait and reschedule? */ -#define __GFP_HIGH ((gfp_t)0x20u) /* Should access emergency pools? */ -#define __GFP_IO ((gfp_t)0x40u) /* Can start physical IO? */ -#define __GFP_FS ((gfp_t)0x80u) /* Can call down to low-level FS? */ -#define __GFP_COLD ((gfp_t)0x100u) /* Cache-cold page required */ -#define __GFP_NOWARN ((gfp_t)0x200u) /* Suppress page allocation failure warning */ -#define __GFP_REPEAT ((gfp_t)0x400u) /* Retry the allocation. Might fail */ -#define __GFP_NOFAIL ((gfp_t)0x800u) /* Retry for ever. Cannot fail */ -#define __GFP_NORETRY ((gfp_t)0x1000u)/* Do not retry. Might fail */ -#define __GFP_NO_GROW ((gfp_t)0x2000u)/* Slab internal usage */ -#define __GFP_COMP ((gfp_t)0x4000u)/* Add compound page metadata */ -#define __GFP_ZERO ((gfp_t)0x8000u)/* Return zeroed page on success */ -#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */ -#define __GFP_HARDWALL ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */ - -/* This equals 0, but use constants in case they ever change */ -#define GFP_NOWAIT (GFP_ATOMIC & ~__GFP_HIGH) -/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */ -#define GFP_ATOMIC (__GFP_HIGH) -#define GFP_NOIO (__GFP_WAIT) -#define GFP_NOFS (__GFP_WAIT | __GFP_IO) -#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS) -#define GFP_USER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL) -#define GFP_HIGHUSER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \ - __GFP_HIGHMEM) - - -#endif // kenny add Linux compatibility code for Linux USB - -__inline static _list *get_next(_list *list) -{ - return list->next; -} - -__inline static _list *get_list_head(_queue *queue) -{ - return (&(queue->queue)); -} - - -#define LIST_CONTAINOR(ptr, type, member) \ - ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) - - -__inline static void _enter_critical(_lock *plock, _irqL *pirqL) -{ - spin_lock_irqsave(plock, *pirqL); -} - -__inline static void _exit_critical(_lock *plock, _irqL *pirqL) -{ - spin_unlock_irqrestore(plock, *pirqL); -} - -__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) -{ - spin_lock_irqsave(plock, *pirqL); -} - -__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) -{ - spin_unlock_irqrestore(plock, *pirqL); -} - -__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) -{ - spin_lock_bh(plock, *pirqL); -} - -__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) -{ - spin_unlock_bh(plock, *pirqL); -} - -__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - - mtx_lock(pmutex); - -} - - -__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - - mtx_unlock(pmutex); - -} -static inline void __list_del(struct list_head * prev, struct list_head * next) -{ - next->prev = prev; - prev->next = next; -} -static inline void INIT_LIST_HEAD(struct list_head *list) -{ - list->next = list; - list->prev = list; -} -__inline static void rtw_list_delete(_list *plist) -{ - __list_del(plist->prev, plist->next); - INIT_LIST_HEAD(plist); -} - + +struct workqueue_struct; +struct work_struct; +typedef void (*work_func_t)(struct work_struct *work); +/* Values for the state of an item of work (work_struct) */ +typedef enum work_state { + WORK_STATE_UNSET = 0, + WORK_STATE_CALLOUT_PENDING = 1, + WORK_STATE_TASK_PENDING = 2, + WORK_STATE_WORK_CANCELLED = 3 +} work_state_t; + +struct work_struct { + struct task task; /* FreeBSD task */ + work_state_t state; /* the pending or otherwise state of work. */ + work_func_t func; +}; +#define spin_unlock_irqrestore mtx_unlock_irqrestore +#define spin_unlock_bh mtx_unlock_irqrestore +#define mtx_unlock_irqrestore(lock,x) mtx_unlock(lock); +extern void _rtw_spinlock_init(_lock *plock); + +//modify private structure to match freebsd +#define BITS_PER_LONG 32 +union ktime { + s64 tv64; +#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR) + struct { +#ifdef __BIG_ENDIAN + s32 sec, nsec; +#else + s32 nsec, sec; +#endif + } tv; +#endif +}; +#define kmemcheck_bitfield_begin(name) +#define kmemcheck_bitfield_end(name) +#define CHECKSUM_NONE 0 +typedef unsigned char *sk_buff_data_t; +typedef union ktime ktime_t; /* Kill this */ + +void rtw_mtx_lock(_lock *plock); + +void rtw_mtx_unlock(_lock *plock); + +/** + * struct sk_buff - socket buffer + * @next: Next buffer in list + * @prev: Previous buffer in list + * @sk: Socket we are owned by + * @tstamp: Time we arrived + * @dev: Device we arrived on/are leaving by + * @transport_header: Transport layer header + * @network_header: Network layer header + * @mac_header: Link layer header + * @_skb_refdst: destination entry (with norefcount bit) + * @sp: the security path, used for xfrm + * @cb: Control buffer. Free for use by every layer. Put private vars here + * @len: Length of actual data + * @data_len: Data length + * @mac_len: Length of link layer header + * @hdr_len: writable header length of cloned skb + * @csum: Checksum (must include start/offset pair) + * @csum_start: Offset from skb->head where checksumming should start + * @csum_offset: Offset from csum_start where checksum should be stored + * @local_df: allow local fragmentation + * @cloned: Head may be cloned (check refcnt to be sure) + * @nohdr: Payload reference only, must not modify header + * @pkt_type: Packet class + * @fclone: skbuff clone status + * @ip_summed: Driver fed us an IP checksum + * @priority: Packet queueing priority + * @users: User count - see {datagram,tcp}.c + * @protocol: Packet protocol from driver + * @truesize: Buffer size + * @head: Head of buffer + * @data: Data head pointer + * @tail: Tail pointer + * @end: End pointer + * @destructor: Destruct function + * @mark: Generic packet mark + * @nfct: Associated connection, if any + * @ipvs_property: skbuff is owned by ipvs + * @peeked: this packet has been seen already, so stats have been + * done for it, don't do them again + * @nf_trace: netfilter packet trace flag + * @nfctinfo: Relationship of this skb to the connection + * @nfct_reasm: netfilter conntrack re-assembly pointer + * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c + * @skb_iif: ifindex of device we arrived on + * @rxhash: the packet hash computed on receive + * @queue_mapping: Queue mapping for multiqueue devices + * @tc_index: Traffic control index + * @tc_verd: traffic control verdict + * @ndisc_nodetype: router type (from link layer) + * @dma_cookie: a cookie to one of several possible DMA operations + * done by skb DMA functions + * @secmark: security marking + * @vlan_tci: vlan tag control information + */ + +struct sk_buff { + /* These two members must be first. */ + struct sk_buff *next; + struct sk_buff *prev; + + ktime_t tstamp; + + struct sock *sk; + //struct net_device *dev; + struct ifnet *dev; + + /* + * This is the control buffer. It is free to use for every + * layer. Please put your private variables there. If you + * want to keep them across layers you have to do a skb_clone() + * first. This is owned by whoever has the skb queued ATM. + */ + char cb[48] __aligned(8); + + unsigned long _skb_refdst; +#ifdef CONFIG_XFRM + struct sec_path *sp; +#endif + unsigned int len, + data_len; + u16 mac_len, + hdr_len; + union { + u32 csum; + struct { + u16 csum_start; + u16 csum_offset; + }smbol2; + }smbol1; + u32 priority; + kmemcheck_bitfield_begin(flags1); + u8 local_df:1, + cloned:1, + ip_summed:2, + nohdr:1, + nfctinfo:3; + u8 pkt_type:3, + fclone:2, + ipvs_property:1, + peeked:1, + nf_trace:1; + kmemcheck_bitfield_end(flags1); + u16 protocol; + + void (*destructor)(struct sk_buff *skb); +#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) + struct nf_conntrack *nfct; + struct sk_buff *nfct_reasm; +#endif +#ifdef CONFIG_BRIDGE_NETFILTER + struct nf_bridge_info *nf_bridge; +#endif + + int skb_iif; +#ifdef CONFIG_NET_SCHED + u16 tc_index; /* traffic control index */ +#ifdef CONFIG_NET_CLS_ACT + u16 tc_verd; /* traffic control verdict */ +#endif +#endif + + u32 rxhash; + + kmemcheck_bitfield_begin(flags2); + u16 queue_mapping:16; +#ifdef CONFIG_IPV6_NDISC_NODETYPE + u8 ndisc_nodetype:2, + deliver_no_wcard:1; +#else + u8 deliver_no_wcard:1; +#endif + kmemcheck_bitfield_end(flags2); + + /* 0/14 bit hole */ + +#ifdef CONFIG_NET_DMA + dma_cookie_t dma_cookie; +#endif +#ifdef CONFIG_NETWORK_SECMARK + u32 secmark; +#endif + union { + u32 mark; + u32 dropcount; + }symbol3; + + u16 vlan_tci; + + sk_buff_data_t transport_header; + sk_buff_data_t network_header; + sk_buff_data_t mac_header; + /* These elements must be at the end, see alloc_skb() for details. */ + sk_buff_data_t tail; + sk_buff_data_t end; + unsigned char *head, + *data; + unsigned int truesize; + atomic_t users; +}; +struct sk_buff_head { + /* These two members must be first. */ + struct sk_buff *next; + struct sk_buff *prev; + + u32 qlen; + _lock lock; +}; +#define skb_tail_pointer(skb) skb->tail +static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len) +{ + unsigned char *tmp = skb_tail_pointer(skb); + //SKB_LINEAR_ASSERT(skb); + skb->tail += len; + skb->len += len; + return tmp; +} + +static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len) +{ + skb->len -= len; + if(skb->len < skb->data_len) + printf("%s(),%d,error!\n",__FUNCTION__,__LINE__); + return skb->data += len; +} +static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len) +{ + #ifdef PLATFORM_FREEBSD + return __skb_pull(skb, len); + #else + return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len); + #endif //PLATFORM_FREEBSD +} +static inline u32 skb_queue_len(const struct sk_buff_head *list_) +{ + return list_->qlen; +} +static inline void __skb_insert(struct sk_buff *newsk, + struct sk_buff *prev, struct sk_buff *next, + struct sk_buff_head *list) +{ + newsk->next = next; + newsk->prev = prev; + next->prev = prev->next = newsk; + list->qlen++; +} +static inline void __skb_queue_before(struct sk_buff_head *list, + struct sk_buff *next, + struct sk_buff *newsk) +{ + __skb_insert(newsk, next->prev, next, list); +} +static inline void skb_queue_tail(struct sk_buff_head *list, + struct sk_buff *newsk) +{ + mtx_lock(&list->lock); + __skb_queue_before(list, (struct sk_buff *)list, newsk); + mtx_unlock(&list->lock); +} +static inline struct sk_buff *skb_peek(struct sk_buff_head *list_) +{ + struct sk_buff *list = ((struct sk_buff *)list_)->next; + if (list == (struct sk_buff *)list_) + list = NULL; + return list; +} +static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list) +{ + struct sk_buff *next, *prev; + + list->qlen--; + next = skb->next; + prev = skb->prev; + skb->next = skb->prev = NULL; + next->prev = prev; + prev->next = next; +} + +static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list) +{ + mtx_lock(&list->lock); + + struct sk_buff *skb = skb_peek(list); + if (skb) + __skb_unlink(skb, list); + + mtx_unlock(&list->lock); + + return skb; +} +static inline void skb_reserve(struct sk_buff *skb, int len) +{ + skb->data += len; + skb->tail += len; +} +static inline void __skb_queue_head_init(struct sk_buff_head *list) +{ + list->prev = list->next = (struct sk_buff *)list; + list->qlen = 0; +} +/* + * This function creates a split out lock class for each invocation; + * this is needed for now since a whole lot of users of the skb-queue + * infrastructure in drivers have different locking usage (in hardirq) + * than the networking core (in softirq only). In the long run either the + * network layer or drivers should need annotation to consolidate the + * main types of usage into 3 classes. + */ +static inline void skb_queue_head_init(struct sk_buff_head *list) +{ + _rtw_spinlock_init(&list->lock); + __skb_queue_head_init(list); +} +unsigned long copy_from_user(void *to, const void *from, unsigned long n); +unsigned long copy_to_user(void *to, const void *from, unsigned long n); +struct sk_buff * dev_alloc_skb(unsigned int size); +struct sk_buff *skb_clone(const struct sk_buff *skb); +void dev_kfree_skb_any(struct sk_buff *skb); +#endif //Baron porting from linux, it's all temp solution, needs to check again + + +#if 1 // kenny add Linux compatibility code for Linux USB driver +#include + +#define __init // __attribute ((constructor)) +#define __exit // __attribute ((destructor)) + +/* + * Definitions for module_init and module_exit macros. + * + * These macros will use the SYSINIT framework to call a specified + * function (with no arguments) on module loading or unloading. + * + */ + +void module_init_exit_wrapper(void *arg); + +#define module_init(initfn) \ + SYSINIT(mod_init_ ## initfn, \ + SI_SUB_KLD, SI_ORDER_FIRST, \ + module_init_exit_wrapper, initfn) + +#define module_exit(exitfn) \ + SYSUNINIT(mod_exit_ ## exitfn, \ + SI_SUB_KLD, SI_ORDER_ANY, \ + module_init_exit_wrapper, exitfn) + +/* + * The usb_register and usb_deregister functions are used to register + * usb drivers with the usb subsystem. + */ +int usb_register(struct usb_driver *driver); +int usb_deregister(struct usb_driver *driver); + +/* + * usb_get_dev and usb_put_dev - increment/decrement the reference count + * of the usb device structure. + * + * Original body of usb_get_dev: + * + * if (dev) + * get_device(&dev->dev); + * return dev; + * + * Reference counts are not currently used in this compatibility + * layer. So these functions will do nothing. + */ +static inline struct usb_device * +usb_get_dev(struct usb_device *dev) +{ + return dev; +} + +static inline void +usb_put_dev(struct usb_device *dev) +{ + return; +} + + +// rtw_usb_compat_linux +int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags); +int rtw_usb_unlink_urb(struct urb *urb); +int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe); +int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe, + uint8_t request, uint8_t requesttype, + uint16_t value, uint16_t index, void *data, + uint16_t size, usb_timeout_t timeout); +int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index); +int rtw_usb_setup_endpoint(struct usb_device *dev, + struct usb_host_endpoint *uhe, usb_size_t bufsize); +struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags); +struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep); +struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index); +struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no); +void *rtw_usbd_get_intfdata(struct usb_interface *intf); +void rtw_usb_linux_register(void *arg); +void rtw_usb_linux_deregister(void *arg); +void rtw_usb_linux_free_device(struct usb_device *dev); +void rtw_usb_free_urb(struct urb *urb); +void rtw_usb_init_urb(struct urb *urb); +void rtw_usb_kill_urb(struct urb *urb); +void rtw_usb_set_intfdata(struct usb_interface *intf, void *data); +void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev, + struct usb_host_endpoint *uhe, void *buf, + int length, usb_complete_t callback, void *arg); +int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe, + void *data, int len, uint16_t *pactlen, usb_timeout_t timeout); +void *usb_get_intfdata(struct usb_interface *intf); +int usb_linux_init_endpoints(struct usb_device *udev); + + + +typedef struct urb * PURB; + +typedef unsigned gfp_t; +#define __GFP_WAIT ((gfp_t)0x10u) /* Can wait and reschedule? */ +#define __GFP_HIGH ((gfp_t)0x20u) /* Should access emergency pools? */ +#define __GFP_IO ((gfp_t)0x40u) /* Can start physical IO? */ +#define __GFP_FS ((gfp_t)0x80u) /* Can call down to low-level FS? */ +#define __GFP_COLD ((gfp_t)0x100u) /* Cache-cold page required */ +#define __GFP_NOWARN ((gfp_t)0x200u) /* Suppress page allocation failure warning */ +#define __GFP_REPEAT ((gfp_t)0x400u) /* Retry the allocation. Might fail */ +#define __GFP_NOFAIL ((gfp_t)0x800u) /* Retry for ever. Cannot fail */ +#define __GFP_NORETRY ((gfp_t)0x1000u)/* Do not retry. Might fail */ +#define __GFP_NO_GROW ((gfp_t)0x2000u)/* Slab internal usage */ +#define __GFP_COMP ((gfp_t)0x4000u)/* Add compound page metadata */ +#define __GFP_ZERO ((gfp_t)0x8000u)/* Return zeroed page on success */ +#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */ +#define __GFP_HARDWALL ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */ + +/* This equals 0, but use constants in case they ever change */ +#define GFP_NOWAIT (GFP_ATOMIC & ~__GFP_HIGH) +/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */ +#define GFP_ATOMIC (__GFP_HIGH) +#define GFP_NOIO (__GFP_WAIT) +#define GFP_NOFS (__GFP_WAIT | __GFP_IO) +#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS) +#define GFP_USER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL) +#define GFP_HIGHUSER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \ + __GFP_HIGHMEM) + + +#endif // kenny add Linux compatibility code for Linux USB + +__inline static _list *get_next(_list *list) +{ + return list->next; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + + +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) + + +__inline static void _enter_critical(_lock *plock, _irqL *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +__inline static void _exit_critical(_lock *plock, _irqL *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +{ + spin_lock_bh(plock, *pirqL); +} + +__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +{ + spin_unlock_bh(plock, *pirqL); +} + +__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + + mtx_lock(pmutex); + +} + + +__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + + mtx_unlock(pmutex); + +} +static inline void __list_del(struct list_head * prev, struct list_head * next) +{ + next->prev = prev; + prev->next = next; +} +static inline void INIT_LIST_HEAD(struct list_head *list) +{ + list->next = list; + list->prev = list; +} +__inline static void rtw_list_delete(_list *plist) +{ + __list_del(plist->prev, plist->next); + INIT_LIST_HEAD(plist); +} + static inline void timer_hdl(void *ctx) { _timer *timer = (_timer *)ctx; @@ -691,67 +690,67 @@ static inline void _init_timer(_timer *ptimer, _nic_hdl padapter, void *pfunc, v callout_init(&ptimer->callout, CALLOUT_MPSAFE); } -__inline static void _set_timer(_timer *ptimer,u32 delay_time) -{ +__inline static void _set_timer(_timer *ptimer,u32 delay_time) +{ if (ptimer->function && ptimer->arg) { - rtw_mtx_lock(NULL); + rtw_mtx_lock(NULL); callout_reset(&ptimer->callout, delay_time, timer_hdl, ptimer); - rtw_mtx_unlock(NULL); - } -} - -__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) -{ - rtw_mtx_lock(NULL); - callout_drain(&ptimer->callout); - rtw_mtx_unlock(NULL); + rtw_mtx_unlock(NULL); + } +} + +__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) +{ + rtw_mtx_lock(NULL); + callout_drain(&ptimer->callout); + rtw_mtx_unlock(NULL); *bcancelled = 1; /* assume an pending timer to be canceled */ -} - -__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) -{ - printf("%s Not implement yet! \n",__FUNCTION__); -} - -__inline static void _set_workitem(_workitem *pwork) -{ - printf("%s Not implement yet! \n",__FUNCTION__); -// schedule_work(pwork); -} - -// -// Global Mutex: can only be used at PASSIVE level. -// - -#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ -} - -#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ -} - -#define ATOMIC_INIT(i) { (i) } - -static __inline void thread_enter(char *name); - -//Atomic integer operations -typedef uint32_t ATOMIC_T ; - -#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc) - -#define rtw_free_netdev(netdev) if_free((netdev)) - -#define NDEV_FMT "%s" -#define NDEV_ARG(ndev) "" -#define ADPT_FMT "%s" -#define ADPT_ARG(adapter) "" -#define FUNC_NDEV_FMT "%s" -#define FUNC_NDEV_ARG(ndev) __func__ -#define FUNC_ADPT_FMT "%s" -#define FUNC_ADPT_ARG(adapter) __func__ - -#define STRUCT_PACKED - -#endif - +} + +__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +{ + printf("%s Not implement yet! \n",__FUNCTION__); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + printf("%s Not implement yet! \n",__FUNCTION__); +// schedule_work(pwork); +} + +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ +} + +#define ATOMIC_INIT(i) { (i) } + +static __inline void thread_enter(char *name); + +//Atomic integer operations +typedef uint32_t ATOMIC_T ; + +#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc) + +#define rtw_free_netdev(netdev) if_free((netdev)) + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) "" +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) "" +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s" +#define FUNC_ADPT_ARG(adapter) __func__ + +#define STRUCT_PACKED + +#endif + diff --git a/include/osdep_service_ce.h b/include/osdep_service_ce.h index bc920c0..2bf65ef 100644 --- a/include/osdep_service_ce.h +++ b/include/osdep_service_ce.h @@ -12,113 +12,113 @@ * more details. * *****************************************************************************/ - -#ifndef __OSDEP_CE_SERVICE_H_ -#define __OSDEP_CE_SERVICE_H_ - - -#include -#include - -#ifdef CONFIG_SDIO_HCI -#include "SDCardDDK.h" -#endif - -#ifdef CONFIG_USB_HCI -#include -#endif - -typedef HANDLE _sema; -typedef LIST_ENTRY _list; -typedef NDIS_STATUS _OS_STATUS; - -typedef NDIS_SPIN_LOCK _lock; - -typedef HANDLE _rwlock; //Mutex - -typedef u32 _irqL; - -typedef NDIS_HANDLE _nic_hdl; - -struct timer_list { + +#ifndef __OSDEP_CE_SERVICE_H_ +#define __OSDEP_CE_SERVICE_H_ + + +#include +#include + +#ifdef CONFIG_SDIO_HCI +#include "SDCardDDK.h" +#endif + +#ifdef CONFIG_USB_HCI +#include +#endif + +typedef HANDLE _sema; +typedef LIST_ENTRY _list; +typedef NDIS_STATUS _OS_STATUS; + +typedef NDIS_SPIN_LOCK _lock; + +typedef HANDLE _rwlock; //Mutex + +typedef u32 _irqL; + +typedef NDIS_HANDLE _nic_hdl; + +struct rtw_timer_list { NDIS_MINIPORT_TIMER ndis_timer; void (*function)(void *); void *arg; }; - -struct __queue { - LIST_ENTRY queue; - _lock lock; -}; - -typedef NDIS_PACKET _pkt; -typedef NDIS_BUFFER _buffer; -typedef struct __queue _queue; - -typedef HANDLE _thread_hdl_; -typedef DWORD thread_return; -typedef void* thread_context; -typedef NDIS_WORK_ITEM _workitem; - - - -#define SEMA_UPBND (0x7FFFFFFF) //8192 - -__inline static _list *get_prev(_list *list) -{ - return list->Blink; -} - -__inline static _list *get_next(_list *list) -{ - return list->Flink; -} - -__inline static _list *get_list_head(_queue *queue) -{ - return (&(queue->queue)); -} - -#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) - -__inline static void _enter_critical(_lock *plock, _irqL *pirqL) -{ - NdisAcquireSpinLock(plock); -} - -__inline static void _exit_critical(_lock *plock, _irqL *pirqL) -{ - NdisReleaseSpinLock(plock); -} - -__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) -{ - NdisDprAcquireSpinLock(plock); -} - -__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) -{ - NdisDprReleaseSpinLock(plock); -} - - -__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL) -{ - WaitForSingleObject(*prwlock, INFINITE ); - -} - -__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL) -{ - ReleaseMutex(*prwlock); -} - -__inline static void rtw_list_delete(_list *plist) -{ - RemoveEntryList(plist); - InitializeListHead(plist); -} - + +struct __queue { + LIST_ENTRY queue; + _lock lock; +}; + +typedef NDIS_PACKET _pkt; +typedef NDIS_BUFFER _buffer; +typedef struct __queue _queue; + +typedef HANDLE _thread_hdl_; +typedef DWORD thread_return; +typedef void* thread_context; +typedef NDIS_WORK_ITEM _workitem; + + + +#define SEMA_UPBND (0x7FFFFFFF) //8192 + +__inline static _list *get_prev(_list *list) +{ + return list->Blink; +} + +__inline static _list *get_next(_list *list) +{ + return list->Flink; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + +#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) + +__inline static void _enter_critical(_lock *plock, _irqL *pirqL) +{ + NdisAcquireSpinLock(plock); +} + +__inline static void _exit_critical(_lock *plock, _irqL *pirqL) +{ + NdisReleaseSpinLock(plock); +} + +__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprAcquireSpinLock(plock); +} + +__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprReleaseSpinLock(plock); +} + + +__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL) +{ + WaitForSingleObject(*prwlock, INFINITE ); + +} + +__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL) +{ + ReleaseMutex(*prwlock); +} + +__inline static void rtw_list_delete(_list *plist) +{ + RemoveEntryList(plist); + InitializeListHead(plist); +} + static inline void timer_hdl( IN PVOID SystemSpecific1, IN PVOID FunctionContext, @@ -146,55 +146,55 @@ static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled) { NdisMCancelTimer(ptimer, bcancelled); } - -__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) -{ - - NdisInitializeWorkItem(pwork, pfunc, cntx); -} - -__inline static void _set_workitem(_workitem *pwork) -{ - NdisScheduleWorkItem(pwork); -} - -#define ATOMIC_INIT(i) { (i) } - -// -// Global Mutex: can only be used at PASSIVE level. -// - -#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ - { \ - NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ - NdisMSleep(10000); \ - } \ -} - -#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ -} - -// limitation of path length -#define PATH_LENGTH_MAX MAX_PATH - -//Atomic integer operations -#define ATOMIC_T LONG - -#define NDEV_FMT "%s" -#define NDEV_ARG(ndev) "" -#define ADPT_FMT "%s" -#define ADPT_ARG(adapter) "" -#define FUNC_NDEV_FMT "%s" -#define FUNC_NDEV_ARG(ndev) __func__ -#define FUNC_ADPT_FMT "%s" -#define FUNC_ADPT_ARG(adapter) __func__ - -#define STRUCT_PACKED - - -#endif - + +__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +{ + + NdisInitializeWorkItem(pwork, pfunc, cntx); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + NdisScheduleWorkItem(pwork); +} + +#define ATOMIC_INIT(i) { (i) } + +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ + { \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ + NdisMSleep(10000); \ + } \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ +} + +// limitation of path length +#define PATH_LENGTH_MAX MAX_PATH + +//Atomic integer operations +#define ATOMIC_T LONG + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) "" +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) "" +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s" +#define FUNC_ADPT_ARG(adapter) __func__ + +#define STRUCT_PACKED + + +#endif + diff --git a/include/osdep_service_linux.h b/include/osdep_service_linux.h index 3b79bfb..769d6e4 100644 --- a/include/osdep_service_linux.h +++ b/include/osdep_service_linux.h @@ -42,9 +42,6 @@ #endif #include #include -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) - #include -#endif #include #include #include @@ -86,6 +83,11 @@ #include #endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)) + #define CONFIG_IEEE80211_HT_ADDT_INFO +#endif + #ifdef CONFIG_IOCTL_CFG80211 /* #include */ #include @@ -134,12 +136,22 @@ #error "Enable NAPI before enable GRO\n" -#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) && defined(CONFIG_RTW_NAPI)) +#endif + - #error "Linux Kernel version too old (should newer than 2.6.29)\n" +#if (KERNEL_VERSION(2, 6, 29) > LINUX_VERSION_CODE && defined(CONFIG_RTW_NAPI)) + + #undef CONFIG_RTW_NAPI + /*#warning "Linux Kernel version too old to support NAPI (should newer than 2.6.29)\n"*/ #endif +#if (KERNEL_VERSION(2, 6, 33) > LINUX_VERSION_CODE && defined(CONFIG_RTW_GRO)) + + #undef CONFIG_RTW_GRO + /*#warning "Linux Kernel version too old to support GRO(should newer than 2.6.33)\n"*/ + +#endif typedef struct semaphore _sema; typedef spinlock_t _lock; @@ -148,15 +160,13 @@ typedef spinlock_t _lock; #else typedef struct semaphore _mutex; #endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) -typedef struct legacy_timer_emu { - struct timer_list t; - void (*function)(unsigned long); - unsigned long data; -} _timer; -#else -typedef struct timer_list _timer; -#endif +struct rtw_timer_list { + struct timer_list timer; + void (*function)(void *); + void *arg; +}; + +typedef struct rtw_timer_list _timer; typedef struct completion _completion; struct __queue { @@ -169,6 +179,25 @@ typedef unsigned char _buffer; typedef struct __queue _queue; typedef struct list_head _list; + +/* hlist */ +typedef struct hlist_head rtw_hlist_head; +typedef struct hlist_node rtw_hlist_node; + +/* RCU */ +typedef struct rcu_head rtw_rcu_head; +#define rtw_rcu_dereference(p) rcu_dereference((p)) +#define rtw_rcu_dereference_protected(p, c) rcu_dereference_protected(p, c) +#define rtw_rcu_assign_pointer(p, v) rcu_assign_pointer((p), (v)) +#define rtw_rcu_read_lock() rcu_read_lock() +#define rtw_rcu_read_unlock() rcu_read_unlock() +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) +#define rtw_rcu_access_pointer(p) rcu_access_pointer(p) +#endif + +/* rhashtable */ +#include "../os_dep/linux/rtw_rhashtable.h" + typedef int _OS_STATUS; /* typedef u32 _irqL; */ typedef unsigned long _irqL; @@ -191,6 +220,8 @@ typedef void *timer_hdl_context; #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) #endif +typedef unsigned long systime; + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22)) /* Porting from linux kernel, for compatible with old kernel. */ static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb) @@ -214,20 +245,31 @@ static inline unsigned char *skb_end_pointer(const struct sk_buff *skb) } #endif -__inline static _list *get_next(_list *list) +__inline static void rtw_list_delete(_list *plist) { - return list->next; + list_del_init(plist); } -__inline static _list *get_list_head(_queue *queue) +__inline static _list *get_next(_list *list) { - return &(queue->queue); + return list->next; } - #define LIST_CONTAINOR(ptr, type, member) \ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) +#define rtw_list_first_entry(ptr, type, member) list_first_entry(ptr, type, member) + +#define rtw_hlist_for_each_entry(pos, head, member) hlist_for_each_entry(pos, head, member) +#define rtw_hlist_for_each_safe(pos, n, head) hlist_for_each_safe(pos, n, head) +#define rtw_hlist_entry(ptr, type, member) hlist_entry(ptr, type, member) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) +#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, n, head, member) +#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, head, member) +#else +#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, np, n, head, member) +#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, node, head, member) +#endif __inline static void _enter_critical(_lock *plock, _irqL *pirqL) { @@ -259,6 +301,16 @@ __inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) spin_unlock_bh(plock); } +__inline static void enter_critical_bh(_lock *plock) +{ + spin_lock_bh(plock); +} + +__inline static void exit_critical_bh(_lock *plock) +{ + spin_unlock_bh(plock); +} + __inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) { int ret = 0; @@ -272,6 +324,17 @@ __inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) } +__inline static int _enter_critical_mutex_lock(_mutex *pmutex, _irqL *pirqL) +{ + int ret = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + mutex_lock(pmutex); +#else + down(pmutex); +#endif + return ret; +} + __inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) @@ -281,47 +344,48 @@ __inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) #endif } -__inline static void rtw_list_delete(_list *plist) +__inline static _list *get_list_head(_queue *queue) { - list_del_init(plist); + return &(queue->queue); } -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) -static void legacy_timer_emu_func(struct timer_list *t) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) +static inline void timer_hdl(struct timer_list *in_timer) +#else +static inline void timer_hdl(unsigned long cntx) +#endif { - struct legacy_timer_emu *lt = from_timer(lt, t, t); - lt->function(lt->data); -} +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + _timer *ptimer = from_timer(ptimer, in_timer, timer); +#else + _timer *ptimer = (_timer *)cntx; #endif + ptimer->function(ptimer->arg); +} __inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx) { - /* setup_timer(ptimer, pfunc,(u32)cntx); */ ptimer->function = pfunc; - ptimer->data = (unsigned long)cntx; - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) - timer_setup(&ptimer->t, legacy_timer_emu_func, 0); - #else - init_timer(ptimer); - #endif + ptimer->arg = cntx; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + timer_setup(&ptimer->timer, timer_hdl, 0); +#else + /* setup_timer(ptimer, pfunc,(u32)cntx); */ + ptimer->timer.function = timer_hdl; + ptimer->timer.data = (unsigned long)ptimer; + init_timer(&ptimer->timer); +#endif } __inline static void _set_timer(_timer *ptimer, u32 delay_time) { - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) - mod_timer(&ptimer->t, (jiffies + (delay_time * HZ / 1000))); - #else - mod_timer(ptimer , (jiffies + (delay_time * HZ / 1000))); - #endif + mod_timer(&ptimer->timer , (jiffies + (delay_time * HZ / 1000))); } __inline static void _cancel_timer(_timer *ptimer, u8 *bcancelled) { - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) - *bcancelled = del_timer_sync(&ptimer->t) == 1 ? 1 : 0; - #else - *bcancelled = del_timer_sync(ptimer) == 1 ? 1 : 0; - #endif + *bcancelled = del_timer_sync(&ptimer->timer) == 1 ? 1 : 0; } static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx) @@ -409,11 +473,23 @@ static inline void rtw_netif_stop_queue(struct net_device *pnetdev) netif_stop_queue(pnetdev); #endif } -static inline void rtw_netif_carrier_on(struct net_device *pnetdev) +static inline void rtw_netif_device_attach(struct net_device *pnetdev) { netif_device_attach(pnetdev); +} +static inline void rtw_netif_device_detach(struct net_device *pnetdev) +{ + netif_device_detach(pnetdev); +} +static inline void rtw_netif_carrier_on(struct net_device *pnetdev) +{ netif_carrier_on(pnetdev); } +static inline void rtw_netif_carrier_off(struct net_device *pnetdev) +{ + netif_carrier_off(pnetdev); +} + static inline int rtw_merge_string(char *dst, int dst_len, const char *src1, const char *src2) { int len = 0; diff --git a/include/osdep_service_xp.h b/include/osdep_service_xp.h index fdbdb50..57e6f31 100644 --- a/include/osdep_service_xp.h +++ b/include/osdep_service_xp.h @@ -12,122 +12,122 @@ * more details. * *****************************************************************************/ -#ifndef __OSDEP_LINUX_SERVICE_H_ -#define __OSDEP_LINUX_SERVICE_H_ - - #include - #include - #include - #include - -#ifdef CONFIG_USB_HCI - #include - #include - #include -#endif - - typedef KSEMAPHORE _sema; - typedef LIST_ENTRY _list; - typedef NDIS_STATUS _OS_STATUS; - - - typedef NDIS_SPIN_LOCK _lock; - - typedef KMUTEX _mutex; - - typedef KIRQL _irqL; - - // USB_PIPE for WINCE , but handle can be use just integer under windows - typedef NDIS_HANDLE _nic_hdl; - - struct timer_list { +#ifndef __OSDEP_LINUX_SERVICE_H_ +#define __OSDEP_LINUX_SERVICE_H_ + + #include + #include + #include + #include + +#ifdef CONFIG_USB_HCI + #include + #include + #include +#endif + + typedef KSEMAPHORE _sema; + typedef LIST_ENTRY _list; + typedef NDIS_STATUS _OS_STATUS; + + + typedef NDIS_SPIN_LOCK _lock; + + typedef KMUTEX _mutex; + + typedef KIRQL _irqL; + + // USB_PIPE for WINCE , but handle can be use just integer under windows + typedef NDIS_HANDLE _nic_hdl; + + struct rtw_timer_list { NDIS_MINIPORT_TIMER ndis_timer; void (*function)(void *); void *arg; }; - - struct __queue { - LIST_ENTRY queue; - _lock lock; - }; - - typedef NDIS_PACKET _pkt; - typedef NDIS_BUFFER _buffer; - typedef struct __queue _queue; - - typedef PKTHREAD _thread_hdl_; - typedef void thread_return; - typedef void* thread_context; - - typedef NDIS_WORK_ITEM _workitem; - - - #define HZ 10000000 - #define SEMA_UPBND (0x7FFFFFFF) //8192 - -__inline static _list *get_next(_list *list) -{ - return list->Flink; -} - -__inline static _list *get_list_head(_queue *queue) -{ - return (&(queue->queue)); -} - - -#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) - - -__inline static _enter_critical(_lock *plock, _irqL *pirqL) -{ - NdisAcquireSpinLock(plock); -} - -__inline static _exit_critical(_lock *plock, _irqL *pirqL) -{ - NdisReleaseSpinLock(plock); -} - - -__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) -{ - NdisDprAcquireSpinLock(plock); -} - -__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) -{ - NdisDprReleaseSpinLock(plock); -} - -__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) -{ - NdisDprAcquireSpinLock(plock); -} - -__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) -{ - NdisDprReleaseSpinLock(plock); -} - -__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL); -} - - -__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - KeReleaseMutex(pmutex, FALSE); -} - - -__inline static void rtw_list_delete(_list *plist) -{ - RemoveEntryList(plist); - InitializeListHead(plist); -} - + + struct __queue { + LIST_ENTRY queue; + _lock lock; + }; + + typedef NDIS_PACKET _pkt; + typedef NDIS_BUFFER _buffer; + typedef struct __queue _queue; + + typedef PKTHREAD _thread_hdl_; + typedef void thread_return; + typedef void* thread_context; + + typedef NDIS_WORK_ITEM _workitem; + + + #define HZ 10000000 + #define SEMA_UPBND (0x7FFFFFFF) //8192 + +__inline static _list *get_next(_list *list) +{ + return list->Flink; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + + +#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) + + +__inline static _enter_critical(_lock *plock, _irqL *pirqL) +{ + NdisAcquireSpinLock(plock); +} + +__inline static _exit_critical(_lock *plock, _irqL *pirqL) +{ + NdisReleaseSpinLock(plock); +} + + +__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprAcquireSpinLock(plock); +} + +__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprReleaseSpinLock(plock); +} + +__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +{ + NdisDprAcquireSpinLock(plock); +} + +__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +{ + NdisDprReleaseSpinLock(plock); +} + +__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL); +} + + +__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + KeReleaseMutex(pmutex, FALSE); +} + + +__inline static void rtw_list_delete(_list *plist) +{ + RemoveEntryList(plist); + InitializeListHead(plist); +} + static inline void timer_hdl( IN PVOID SystemSpecific1, IN PVOID FunctionContext, @@ -155,56 +155,56 @@ static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled) { NdisMCancelTimer(ptimer, bcancelled); } - -__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) -{ - - NdisInitializeWorkItem(pwork, pfunc, cntx); -} - -__inline static void _set_workitem(_workitem *pwork) -{ - NdisScheduleWorkItem(pwork); -} - - -#define ATOMIC_INIT(i) { (i) } - -// -// Global Mutex: can only be used at PASSIVE level. -// - -#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ - { \ - NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ - NdisMSleep(10000); \ - } \ -} - -#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ -} - -// limitation of path length -#define PATH_LENGTH_MAX MAX_PATH - -//Atomic integer operations -#define ATOMIC_T LONG - - -#define NDEV_FMT "%s" -#define NDEV_ARG(ndev) "" -#define ADPT_FMT "%s" -#define ADPT_ARG(adapter) "" -#define FUNC_NDEV_FMT "%s" -#define FUNC_NDEV_ARG(ndev) __func__ -#define FUNC_ADPT_FMT "%s" -#define FUNC_ADPT_ARG(adapter) __func__ - -#define STRUCT_PACKED - -#endif - + +__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +{ + + NdisInitializeWorkItem(pwork, pfunc, cntx); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + NdisScheduleWorkItem(pwork); +} + + +#define ATOMIC_INIT(i) { (i) } + +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ + { \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ + NdisMSleep(10000); \ + } \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ +} + +// limitation of path length +#define PATH_LENGTH_MAX MAX_PATH + +//Atomic integer operations +#define ATOMIC_T LONG + + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) "" +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) "" +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s" +#define FUNC_ADPT_ARG(adapter) __func__ + +#define STRUCT_PACKED + +#endif + diff --git a/include/pci_osintf.h b/include/pci_osintf.h index 29143ca..c6a0fdd 100644 --- a/include/pci_osintf.h +++ b/include/pci_osintf.h @@ -40,6 +40,9 @@ void rtw_pci_enable_aspm(_adapter *padapter); void PlatformClearPciPMEStatus(PADAPTER Adapter); void rtw_pci_aspm_config(_adapter *padapter); void rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 eanble); +#ifdef CONFIG_PCI_DYNAMIC_ASPM +void rtw_pci_aspm_config_dynamic_l1_ilde_time(_adapter *padapter); +#endif #ifdef CONFIG_64BIT_DMA u8 PlatformEnableDMA64(PADAPTER Adapter); #endif diff --git a/include/recv_osdep.h b/include/recv_osdep.h index 7715442..8c569b6 100644 --- a/include/recv_osdep.h +++ b/include/recv_osdep.h @@ -21,12 +21,15 @@ extern void _rtw_free_recv_priv(struct recv_priv *precvpriv); extern s32 rtw_recv_entry(union recv_frame *precv_frame); +void rtw_rframe_set_os_pkt(union recv_frame *rframe); extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame); extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt); extern int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame); +#ifdef CONFIG_HOSTAPD_MLME extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame); +#endif struct sta_info; extern void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup); @@ -45,8 +48,8 @@ void rtw_os_free_recvframe(union recv_frame *precvframe); int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf); int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf); -_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 *pdata); -void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attrib *pattrib); +_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa, u8 *msdu ,u16 msdu_len); +void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe); void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf); @@ -55,6 +58,9 @@ void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf); #include /* struct napi_struct */ int rtw_recv_napi_poll(struct napi_struct *, int budget); +#ifdef CONFIG_RTW_NAPI_DYNAMIC +void dynamic_napi_th_chk (_adapter *adapter); +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ #endif /* CONFIG_RTW_NAPI */ #endif /* PLATFORM_LINUX */ diff --git a/include/rtl8188e_cmd.h b/include/rtl8188e_cmd.h index e9f252b..99a9cba 100644 --- a/include/rtl8188e_cmd.h +++ b/include/rtl8188e_cmd.h @@ -136,7 +136,6 @@ typedef struct _RSVDPAGE_LOC_88E { void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); u8 rtl8188e_set_rssi_cmd(PADAPTER padapter, u8 *param); -u8 rtl8188e_set_raid_cmd(_adapter *padapter, u32 bitmap, u8 *arg, u8 bw); s32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); /* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */ u8 GetTxBufferRsvdPageNum8188E(_adapter *padapter, bool wowlan); @@ -146,13 +145,6 @@ u8 GetTxBufferRsvdPageNum8188E(_adapter *padapter, bool wowlan); void rtl8188e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(PADAPTER padapter); - -#ifdef CONFIG_TSF_RESET_OFFLOAD - /* u8 rtl8188e_reset_tsf(_adapter *padapter, u8 reset_port); */ - int reset_tsf(PADAPTER Adapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - /* #define H2C_8188E_RSVDPAGE_LOC_LEN 5 */ /* #define H2C_8188E_AOAC_RSVDPAGE_LOC_LEN 7 */ diff --git a/include/rtl8188e_hal.h b/include/rtl8188e_hal.h index 4c8ef93..23c435e 100644 --- a/include/rtl8188e_hal.h +++ b/include/rtl8188e_hal.h @@ -110,7 +110,11 @@ typedef struct _RT_8188E_FIRMWARE_HDR { /* #define MAX_RX_DMA_BUFFER_SIZE_88E 0x2400 */ /* 9k for 88E nornal chip , */ /* MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */ -#define RX_DMA_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter))?0x2800:0x4000) +#ifdef CONFIG_USB_HCI + #define RX_DMA_SIZE_88E(__Adapter) 0x2800 +#else + #define RX_DMA_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter))?0x2800:0x4000) +#endif #ifdef CONFIG_WOWLAN #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ @@ -143,7 +147,11 @@ Tx FIFO Size : previous CUT:22K /I_CUT after:32KB Tx page Size : 128B Total page numbers : 176(0xB0) / 256(0x100) */ -#define TOTAL_PAGE_NUMBER_88E(_Adapter) ((IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)?0x100:0xB0) - 1)/* must reserved 1 page for dma issue */ +#ifdef CONFIG_USB_HCI + #define TOTAL_PAGE_NUMBER_88E(_Adapter) (0xB0 - 1) +#else + #define TOTAL_PAGE_NUMBER_88E(_Adapter) ((IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)?0x100:0xB0) - 1)/* must reserved 1 page for dma issue */ +#endif #define TX_TOTAL_PAGE_NUMBER_88E(_Adapter) (TOTAL_PAGE_NUMBER_88E(_Adapter) - BCNQ_PAGE_NUM_88E - WOWLAN_PAGE_NUM_88E) #define TX_PAGE_BOUNDARY_88E(_Adapter) (TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1) /* beacon header start address */ @@ -277,6 +285,9 @@ BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter); void rtl8188e_init_default_value(_adapter *adapter); +void InitBeaconParameters_8188e(_adapter *adapter); +void SetBeaconRelatedRegisters8188E(PADAPTER padapter); + void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8188e(_adapter *adapter); @@ -292,7 +303,7 @@ void rtw_IOL_cmd_tx_pkt_buf_dump(ADAPTER *Adapter, int data_len); #endif/* CONFIG_IOL_EFUSE_PATCH */ void _InitTransferPageSize(PADAPTER padapter); -void SetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val); u8 diff --git a/include/rtl8188e_led.h b/include/rtl8188e_led.h index d3e7f0b..ef05467 100644 --- a/include/rtl8188e_led.h +++ b/include/rtl8188e_led.h @@ -15,6 +15,7 @@ #ifndef __RTL8188E_LED_H__ #define __RTL8188E_LED_H__ +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. @@ -33,3 +34,4 @@ #endif #endif +#endif /*CONFIG_RTW_SW_LED*/ diff --git a/include/rtl8188e_recv.h b/include/rtl8188e_recv.h index dc79cbc..92425a8 100644 --- a/include/rtl8188e_recv.h +++ b/include/rtl8188e_recv.h @@ -29,11 +29,7 @@ /* #define MAX_RECVBUF_SZ (32768) */ /* 32k */ /* #define MAX_RECVBUF_SZ (16384) */ /* 16K */ /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ - #ifdef CONFIG_PLATFORM_MSTAR - #define MAX_RECVBUF_SZ (8192) /* 8K */ - #else - #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ - #endif + #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ /* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */ #else #define MAX_RECVBUF_SZ (4000) /* about 4K */ diff --git a/include/rtl8188e_rf.h b/include/rtl8188e_rf.h index e7f9750..f5c5fbd 100644 --- a/include/rtl8188e_rf.h +++ b/include/rtl8188e_rf.h @@ -22,6 +22,6 @@ void rtl8188e_RF_ChangeTxPath(IN PADAPTER Adapter, IN u16 DataRate); void rtl8188e_PHY_RF6052SetBandwidth( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); #endif/* __RTL8188E_RF_H__ */ diff --git a/include/rtl8188e_spec.h b/include/rtl8188e_spec.h index 9691f51..802659a 100644 --- a/include/rtl8188e_spec.h +++ b/include/rtl8188e_spec.h @@ -84,6 +84,8 @@ * 0x0300h ~ 0x03FFh PCIe * * ----------------------------------------------------- */ +#define REG_PCIE_HRPWM_8188E 0x0361 /* PCIe RPWM */ +#define REG_PCIE_HCPWM_8188E 0x0363 /* PCIe CPWM */ /* ----------------------------------------------------- * diff --git a/include/rtl8188f_cmd.h b/include/rtl8188f_cmd.h index 16e0a96..a198e33 100644 --- a/include/rtl8188f_cmd.h +++ b/include/rtl8188f_cmd.h @@ -182,7 +182,6 @@ void rtl8188f_set_rssi_cmd(PADAPTER padapter, u8 *param); void rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); /* s32 rtl8188f_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ void rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8188f_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); void rtl8188f_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus); #ifdef CONFIG_BT_COEXIST @@ -192,8 +191,6 @@ void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus); void rtl8188f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(PADAPTER padapter); - #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW void rtl8188f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); @@ -206,9 +203,6 @@ void rtl8188f_set_p2p_wowlan_offload_cmd(PADAPTER padapter); void rtl8188f_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); -#ifdef CONFIG_TSF_RESET_OFFLOAD -u8 rtl8188f_reset_tsf(_adapter *padapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ s32 FillH2CCmd8188F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8188F(_adapter *padapter, bool wowlan); #endif diff --git a/include/rtl8188f_dm.h b/include/rtl8188f_dm.h index 4af0338..342ade9 100644 --- a/include/rtl8188f_dm.h +++ b/include/rtl8188f_dm.h @@ -35,8 +35,5 @@ void rtl8188f_deinit_dm_priv(PADAPTER padapter); void rtl8188f_InitHalDm(PADAPTER padapter); void rtl8188f_HalDmWatchDog(PADAPTER padapter); -void rtl8188f_HalDmWatchDog_in_LPS(PADAPTER padapter); -void rtl8188f_hal_dm_in_lps(PADAPTER padapter); - #endif diff --git a/include/rtl8188f_hal.h b/include/rtl8188f_hal.h index 9f36709..7aaead7 100644 --- a/include/rtl8188f_hal.h +++ b/include/rtl8188f_hal.h @@ -223,7 +223,7 @@ void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel); void rtl8188f_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8188f(_adapter *adapter); -void SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val); u8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); diff --git a/include/rtl8188f_led.h b/include/rtl8188f_led.h index ffd1971..ef5d1a7 100644 --- a/include/rtl8188f_led.h +++ b/include/rtl8188f_led.h @@ -14,6 +14,7 @@ *****************************************************************************/ #ifndef __RTL8188F_LED_H__ #define __RTL8188F_LED_H__ +#ifdef CONFIG_RTW_SW_LED #include #include @@ -41,3 +42,4 @@ void rtl8188fe_DeInitSwLeds(PADAPTER padapter); #endif #endif +#endif/*CONFIG_RTW_SW_LED*/ diff --git a/include/rtl8188f_rf.h b/include/rtl8188f_rf.h index eef9337..bf4f591 100644 --- a/include/rtl8188f_rf.h +++ b/include/rtl8188f_rf.h @@ -20,6 +20,6 @@ int PHY_RF6052_Config8188F(IN PADAPTER Adapter); VOID PHY_RF6052SetBandwidth8188F( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); #endif diff --git a/include/rtl8188f_xmit.h b/include/rtl8188f_xmit.h index 069183d..cf75fce 100644 --- a/include/rtl8188f_xmit.h +++ b/include/rtl8188f_xmit.h @@ -301,9 +301,10 @@ thread_return rtl8188fs_xmit_thread(thread_context context); #endif #ifdef CONFIG_USB_HCI +#ifdef CONFIG_XMIT_THREAD_MODE s32 rtl8188fu_xmit_buf_handler(PADAPTER padapter); #define hal_xmit_handler rtl8188fu_xmit_buf_handler - +#endif s32 rtl8188fu_init_xmit_priv(PADAPTER padapter); void rtl8188fu_free_xmit_priv(PADAPTER padapter); diff --git a/include/rtl8192e_cmd.h b/include/rtl8192e_cmd.h index 976bc29..6aff7ea 100644 --- a/include/rtl8192e_cmd.h +++ b/include/rtl8192e_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -117,7 +117,6 @@ typedef struct _RSVDPAGE_LOC_92E { void rtl8192e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8192e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); u8 rtl8192e_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8192e_set_raid_cmd(PADAPTER padapter, u32 bitmap, u8 *arg, u8 bw); s32 FillH2CCmd_8192E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8192E(_adapter *padapter, bool wowlan); /* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */ @@ -129,18 +128,12 @@ s32 c2h_handler_8192e(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); void rtl8192e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(PADAPTER padapter); - #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW void rtl8192e_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); #endif #endif -#ifdef CONFIG_TSF_RESET_OFFLOAD - int reset_tsf(PADAPTER Adapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - /* / TX Feedback Content */ #define USEC_UNIT_FOR_8192E_C2H_TX_RPT_QUEUE_TIME 256 diff --git a/include/rtl8192e_dm.h b/include/rtl8192e_dm.h index 0f3d96d..5f6ee4b 100644 --- a/include/rtl8192e_dm.h +++ b/include/rtl8192e_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/rtl8192e_hal.h b/include/rtl8192e_hal.h index 6799210..edd4040 100644 --- a/include/rtl8192e_hal.h +++ b/include/rtl8192e_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -273,7 +273,6 @@ void _InitID_8192E(IN PADAPTER Adapter); VOID _InitNetworkType_8192E(IN PADAPTER Adapter); VOID _InitWMACSetting_8192E(IN PADAPTER Adapter); VOID _InitAdaptiveCtrl_8192E(IN PADAPTER Adapter); -VOID _InitRateFallback_8192E(IN PADAPTER Adapter); VOID _InitEDCA_8192E(IN PADAPTER Adapter); VOID _InitRetryFunction_8192E(IN PADAPTER Adapter); VOID _BBTurnOnBlock_8192E(IN PADAPTER Adapter); @@ -287,7 +286,7 @@ VOID hal_ReadRFType_8192E(PADAPTER Adapter); /* RTL8192E-MAC Setting ***********************************************************/ -void SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val); +u8 SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val); void GetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val); u8 SetHalDefVar8192E( @@ -313,7 +312,7 @@ void rtl8192e_stop_thread(_adapter *padapter); #ifdef CONFIG_PCI_HCI BOOLEAN InterruptRecognized8192EE(PADAPTER Adapter); - u16 get_txdesc_buf_addr(u16 ff_hwaddr); + u16 get_txbd_rw_reg(u16 ff_hwaddr); #endif #ifdef CONFIG_SDIO_HCI diff --git a/include/rtl8192e_led.h b/include/rtl8192e_led.h index ad8fd4d..3d795c4 100644 --- a/include/rtl8192e_led.h +++ b/include/rtl8192e_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,7 +15,7 @@ #ifndef __RTL8192E_LED_H__ #define __RTL8192E_LED_H__ - +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. * ******************************************************************************** */ @@ -33,3 +33,4 @@ #endif #endif +#endif/*CONFIG_RTW_SW_LED*/ diff --git a/include/rtl8192e_recv.h b/include/rtl8192e_recv.h index 7d17b86..6ccb8e9 100644 --- a/include/rtl8192e_recv.h +++ b/include/rtl8192e_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -35,6 +35,10 @@ /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ /* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */ /* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */ + #ifdef CONFIG_PLATFORM_NOVATEK_NT72668 + #undef MAX_RECVBUF_SZ + #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ + #endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */ #endif #endif #endif /* !MAX_RECVBUF_SZ */ @@ -139,6 +143,12 @@ #define GET_RX_STATUS_DESC_UNICAST_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) #define GET_RX_STATUS_DESC_MAGIC_WAKE_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) +/* DWORD 6 */ +#define GET_RX_STATUS_DESC_SPLCP_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1) +#define GET_RX_STATUS_DESC_LDPC_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1) +#define GET_RX_STATUS_DESC_STBC_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1) +#define GET_RX_STATUS_DESC_BW_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2) + /* DWORD 5 */ #define GET_RX_STATUS_DESC_TSFL_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) @@ -150,6 +160,7 @@ #ifdef CONFIG_SDIO_HCI s32 rtl8192es_init_recv_priv(PADAPTER padapter); void rtl8192es_free_recv_priv(PADAPTER padapter); + s32 rtl8192es_recv_hdl(_adapter *padapter); #endif #ifdef CONFIG_USB_HCI diff --git a/include/rtl8192e_rf.h b/include/rtl8192e_rf.h index 6a4b9f6..f15e070 100644 --- a/include/rtl8192e_rf.h +++ b/include/rtl8192e_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -18,7 +18,7 @@ VOID PHY_RF6052SetBandwidth8192E( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); int diff --git a/include/rtl8192e_spec.h b/include/rtl8192e_spec.h index 8af37a7..c9b2b41 100644 --- a/include/rtl8192e_spec.h +++ b/include/rtl8192e_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/rtl8192e_sreset.h b/include/rtl8192e_sreset.h index 4273824..78109ae 100644 --- a/include/rtl8192e_sreset.h +++ b/include/rtl8192e_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/rtl8192e_xmit.h b/include/rtl8192e_xmit.h index a621fd9..0202302 100644 --- a/include/rtl8192e_xmit.h +++ b/include/rtl8192e_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -440,6 +440,8 @@ void fill_txdesc_vcs(struct pkt_attrib *pattrib, u8 *ptxdesc); #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); + void fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc); void rtl8192e_fixed_rate(_adapter *padapter, u8 *ptxdesc); diff --git a/include/rtl8703b_cmd.h b/include/rtl8703b_cmd.h index 8e97ec8..43f7a88 100644 --- a/include/rtl8703b_cmd.h +++ b/include/rtl8703b_cmd.h @@ -181,7 +181,6 @@ void rtl8703b_set_rssi_cmd(PADAPTER padapter, u8 *param); void rtl8703b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); /* s32 rtl8703b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ void rtl8703b_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8703b_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); void rtl8703b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); void rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus); #ifdef CONFIG_BT_COEXIST @@ -191,8 +190,6 @@ void rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus); void rtl8703b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(PADAPTER padapter); - #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW void rtl8703b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); @@ -205,9 +202,6 @@ void CheckFwRsvdPageContent(PADAPTER padapter); void rtl8703b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); -#ifdef CONFIG_TSF_RESET_OFFLOAD - u8 rtl8703b_reset_tsf(_adapter *padapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ s32 FillH2CCmd8703B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8703B(_adapter *padapter, bool wowlan); #endif diff --git a/include/rtl8703b_dm.h b/include/rtl8703b_dm.h index 7ca7995..912c7da 100644 --- a/include/rtl8703b_dm.h +++ b/include/rtl8703b_dm.h @@ -35,8 +35,5 @@ void rtl8703b_deinit_dm_priv(PADAPTER padapter); void rtl8703b_InitHalDm(PADAPTER padapter); void rtl8703b_HalDmWatchDog(PADAPTER padapter); -void rtl8703b_HalDmWatchDog_in_LPS(PADAPTER padapter); -void rtl8703b_hal_dm_in_lps(PADAPTER padapter); - #endif diff --git a/include/rtl8703b_hal.h b/include/rtl8703b_hal.h index 149320e..dfc9b6d 100644 --- a/include/rtl8703b_hal.h +++ b/include/rtl8703b_hal.h @@ -227,7 +227,7 @@ VOID Hal_EfuseParseBoardType_8703B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN Au void rtl8703b_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8703b(_adapter *adapter); -void SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val); u8 SetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); diff --git a/include/rtl8703b_led.h b/include/rtl8703b_led.h index 2baaa96..99e590d 100644 --- a/include/rtl8703b_led.h +++ b/include/rtl8703b_led.h @@ -19,7 +19,7 @@ #include #include - +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. * ******************************************************************************** */ @@ -40,4 +40,5 @@ void rtl8703be_DeInitSwLeds(PADAPTER padapter); #endif -#endif +#endif/*CONFIG_RTW_SW_LED*/ +#endif /*__RTL8703B_LED_H__*/ diff --git a/include/rtl8703b_rf.h b/include/rtl8703b_rf.h index 14dde98..8d980a8 100644 --- a/include/rtl8703b_rf.h +++ b/include/rtl8703b_rf.h @@ -20,6 +20,6 @@ int PHY_RF6052_Config8703B(IN PADAPTER Adapter); VOID PHY_RF6052SetBandwidth8703B( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); #endif diff --git a/include/rtl8703b_xmit.h b/include/rtl8703b_xmit.h index 4aad2cb..2bcd5a7 100644 --- a/include/rtl8703b_xmit.h +++ b/include/rtl8703b_xmit.h @@ -288,6 +288,7 @@ void rtl8703b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 I #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) s32 rtl8703bs_init_xmit_priv(PADAPTER padapter); diff --git a/include/rtl8723b_cmd.h b/include/rtl8723b_cmd.h index 995d016..f284a05 100644 --- a/include/rtl8723b_cmd.h +++ b/include/rtl8723b_cmd.h @@ -181,7 +181,6 @@ void rtl8723b_set_rssi_cmd(PADAPTER padapter, u8 *param); void rtl8723b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); /* s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ void rtl8723b_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8723b_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); void rtl8723b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); void rtl8723b_download_rsvd_page(PADAPTER padapter, u8 mstatus); #ifdef CONFIG_BT_COEXIST @@ -191,8 +190,6 @@ void rtl8723b_download_rsvd_page(PADAPTER padapter, u8 mstatus); void rtl8723b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(PADAPTER padapter); - #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW void rtl8723b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); @@ -205,9 +202,6 @@ void CheckFwRsvdPageContent(PADAPTER padapter); void rtl8723b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); -#ifdef CONFIG_TSF_RESET_OFFLOAD - u8 rtl8723b_reset_tsf(_adapter *padapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ s32 FillH2CCmd8723B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8723B(_adapter *padapter, bool wowlan); #endif diff --git a/include/rtl8723b_dm.h b/include/rtl8723b_dm.h index a7ab603..ea51717 100644 --- a/include/rtl8723b_dm.h +++ b/include/rtl8723b_dm.h @@ -35,8 +35,4 @@ void rtl8723b_deinit_dm_priv(PADAPTER padapter); void rtl8723b_InitHalDm(PADAPTER padapter); void rtl8723b_HalDmWatchDog(PADAPTER padapter); -void rtl8723b_HalDmWatchDog_in_LPS(PADAPTER padapter); -void rtl8723b_hal_dm_in_lps(PADAPTER padapter); - - #endif diff --git a/include/rtl8723b_hal.h b/include/rtl8723b_hal.h index ecb6f25..6e9ac57 100644 --- a/include/rtl8723b_hal.h +++ b/include/rtl8723b_hal.h @@ -149,11 +149,13 @@ typedef struct _RT_8723B_FIRMWARE_HDR { #define NORMAL_PAGE_NUM_HPQ_8723B 0x0C #define NORMAL_PAGE_NUM_LPQ_8723B 0x02 #define NORMAL_PAGE_NUM_NPQ_8723B 0x02 +#define NORMAL_PAGE_NUM_EPQ_8723B 0x04 /* Note: For Normal Chip Setting, modify later */ #define WMM_NORMAL_PAGE_NUM_HPQ_8723B 0x30 #define WMM_NORMAL_PAGE_NUM_LPQ_8723B 0x20 #define WMM_NORMAL_PAGE_NUM_NPQ_8723B 0x20 +#define WMM_NORMAL_PAGE_NUM_EPQ_8723B 0x00 #include "HalVerDef.h" @@ -228,7 +230,7 @@ VOID Hal_EfuseParseBoardType_8723B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN Au void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8723b(_adapter *adapter); -void SetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val); u8 SetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); diff --git a/include/rtl8723b_led.h b/include/rtl8723b_led.h index 24c5124..6b772cc 100644 --- a/include/rtl8723b_led.h +++ b/include/rtl8723b_led.h @@ -19,7 +19,7 @@ #include #include - +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. * ******************************************************************************** */ @@ -41,3 +41,4 @@ #endif #endif +#endif/*CONFIG_RTW_SW_LED*/ diff --git a/include/rtl8723b_rf.h b/include/rtl8723b_rf.h index 3494e8c..6325ad5 100644 --- a/include/rtl8723b_rf.h +++ b/include/rtl8723b_rf.h @@ -20,6 +20,6 @@ int PHY_RF6052_Config8723B(IN PADAPTER Adapter); VOID PHY_RF6052SetBandwidth8723B( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); #endif diff --git a/include/rtl8723b_xmit.h b/include/rtl8723b_xmit.h index 199e7ef..1364951 100644 --- a/include/rtl8723b_xmit.h +++ b/include/rtl8723b_xmit.h @@ -288,6 +288,7 @@ void rtl8723b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 I #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) s32 rtl8723bs_init_xmit_priv(PADAPTER padapter); diff --git a/include/rtl8723d_cmd.h b/include/rtl8723d_cmd.h index 5cabd19..c90b8ea 100644 --- a/include/rtl8723d_cmd.h +++ b/include/rtl8723d_cmd.h @@ -93,24 +93,13 @@ enum h2c_cmd_8723D { #define SET_8723D_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) #define SET_8723D_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -/* _KEEP_ALIVE_CMD_0x03 */ -#define SET_8723D_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8723D_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8723D_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) -#define SET_8723D_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) - -/* _DISCONNECT_DECISION_CMD_0x04 */ -#define SET_8723D_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8723D_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8723D_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8723D_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) - /* _PWR_MOD_CMD_0x20 */ #define SET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) #define SET_8723D_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) #define SET_8723D_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) #define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) #define SET_8723D_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) #define SET_8723D_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) #define SET_8723D_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) @@ -176,12 +165,8 @@ enum h2c_cmd_8723D { /* host message to firmware cmd */ void rtl8723d_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8723d_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); -void rtl8723d_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8723d_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); /* s32 rtl8723d_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ void rtl8723d_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8723d_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); -void rtl8723d_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); void rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus); #ifdef CONFIG_BT_COEXIST void rtl8723d_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); @@ -190,17 +175,16 @@ void rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus); void rtl8723d_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(PADAPTER padapter); +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW +void rtl8723d_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); +#endif +#endif #ifdef CONFIG_P2P_WOWLAN void rtl8723d_set_p2p_wowlan_offload_cmd(PADAPTER padapter); #endif -void rtl8723d_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); - -#ifdef CONFIG_TSF_RESET_OFFLOAD - u8 rtl8723d_reset_tsf(_adapter *padapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ s32 FillH2CCmd8723D(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8723D(_adapter *padapter, bool wowlan); #endif diff --git a/include/rtl8723d_dm.h b/include/rtl8723d_dm.h index c2bdac3..0612f06 100644 --- a/include/rtl8723d_dm.h +++ b/include/rtl8723d_dm.h @@ -35,8 +35,5 @@ void rtl8723d_deinit_dm_priv(PADAPTER padapter); void rtl8723d_InitHalDm(PADAPTER padapter); void rtl8723d_HalDmWatchDog(PADAPTER padapter); -void rtl8723d_HalDmWatchDog_in_LPS(PADAPTER padapter); -void rtl8723d_hal_dm_in_lps(PADAPTER padapter); - #endif diff --git a/include/rtl8723d_hal.h b/include/rtl8723d_hal.h index 139c60c..7ebf666 100644 --- a/include/rtl8723d_hal.h +++ b/include/rtl8723d_hal.h @@ -156,11 +156,13 @@ typedef struct _RT_8723D_FIRMWARE_HDR { #define NORMAL_PAGE_NUM_HPQ_8723D 0x0C #define NORMAL_PAGE_NUM_LPQ_8723D 0x02 #define NORMAL_PAGE_NUM_NPQ_8723D 0x02 +#define NORMAL_PAGE_NUM_EPQ_8723D 0x04 /* Note: For Normal Chip Setting, modify later */ #define WMM_NORMAL_PAGE_NUM_HPQ_8723D 0x30 #define WMM_NORMAL_PAGE_NUM_LPQ_8723D 0x20 #define WMM_NORMAL_PAGE_NUM_NPQ_8723D 0x20 +#define WMM_NORMAL_PAGE_NUM_EPQ_8723D 0x00 #include "HalVerDef.h" @@ -257,7 +259,7 @@ VOID Hal_EfuseParseBoardType_8723D(PADAPTER Adapter, void rtl8723d_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8723d(_adapter *adapter); -void SetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val); u8 SetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); @@ -265,8 +267,6 @@ u8 GetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); /* register */ void rtl8723d_InitBeaconParameters(PADAPTER padapter); void rtl8723d_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); -void _InitBurstPktLen_8723DS(PADAPTER Adapter); -void _InitLTECoex_8723DS(PADAPTER Adapter); void _InitMacAPLLSetting_8723D(PADAPTER Adapter); void _8051Reset8723(PADAPTER padapter); #ifdef CONFIG_WOWLAN @@ -307,7 +307,7 @@ void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); #ifdef CONFIG_PCI_HCI BOOLEAN InterruptRecognized8723DE(PADAPTER Adapter); VOID UpdateInterruptMask8723DE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); - u16 get_txbufdesc_idx_hwaddr(u16 ff_hwaddr); + u16 get_txbd_rw_reg(u16 ff_hwaddr); #endif #endif diff --git a/include/rtl8723d_led.h b/include/rtl8723d_led.h index 7111dfc..1905e8b 100644 --- a/include/rtl8723d_led.h +++ b/include/rtl8723d_led.h @@ -19,7 +19,7 @@ #include #include - +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. * ******************************************************************************** */ @@ -40,4 +40,5 @@ void rtl8723de_DeInitSwLeds(PADAPTER padapter); #endif +#endif /*#ifdef CONFIG_RTW_SW_LED*/ #endif diff --git a/include/rtl8723d_recv.h b/include/rtl8723d_recv.h index 0be4309..03539a8 100644 --- a/include/rtl8723d_recv.h +++ b/include/rtl8723d_recv.h @@ -97,6 +97,7 @@ #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) s32 rtl8723ds_init_recv_priv(PADAPTER padapter); void rtl8723ds_free_recv_priv(PADAPTER padapter); + s32 rtl8723ds_recv_hdl(_adapter *padapter); #endif #ifdef CONFIG_USB_HCI diff --git a/include/rtl8723d_rf.h b/include/rtl8723d_rf.h index 5101eaf..733eb0a 100644 --- a/include/rtl8723d_rf.h +++ b/include/rtl8723d_rf.h @@ -17,5 +17,5 @@ int PHY_RF6052_Config8723D(IN PADAPTER pdapter); -void PHY_RF6052SetBandwidth8723D(IN PADAPTER Adapter, IN CHANNEL_WIDTH Bandwidth); +void PHY_RF6052SetBandwidth8723D(IN PADAPTER Adapter, IN enum channel_width Bandwidth); #endif diff --git a/include/rtl8723d_spec.h b/include/rtl8723d_spec.h index 950242e..5106b23 100644 --- a/include/rtl8723d_spec.h +++ b/include/rtl8723d_spec.h @@ -79,6 +79,7 @@ #define REG_PMC_DBG_CTRL2_8723D 0x00CC #define REG_EFUSE_BURN_GNT_8723D 0x00CF #define REG_HPON_FSM_8723D 0x00EC +#define REG_SYS_CFG1_8723D 0x00F0 #define REG_SYS_CFG_8723D 0x00FC #define REG_ROM_VERSION 0x00FD @@ -376,6 +377,11 @@ #define REG_BFMEE_SEL_8723D 0x0714 #define REG_SND_PTCL_CTRL_8723D 0x0718 +/* LTR */ +#define REG_LTR_CTRL_BASIC_8723D 0x07A4 +#define REG_LTR_IDLE_LATENCY_V1_8723D 0x0798 +#define REG_LTR_ACTIVE_LATENCY_V1_8723D 0x079C + /* LTE_COEX */ #define REG_LTECOEX_CTRL 0x07C0 #define REG_LTECOEX_WRITE_DATA 0x07C4 diff --git a/include/rtl8723d_xmit.h b/include/rtl8723d_xmit.h index 054bf32..b825c83 100644 --- a/include/rtl8723d_xmit.h +++ b/include/rtl8723d_xmit.h @@ -212,9 +212,8 @@ SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value) /* Dword 3 */ -#define SET_TX_DESC_NAV_USE_HDR_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) -#define SET_TX_DESC_HWSEQ_SEL_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) +#define SET_TX_DESC_HWSEQ_SEL_8723D(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) #define SET_TX_DESC_USE_RATE_8723D(__pTxDesc, __Value) \ SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) #define SET_TX_DESC_DISABLE_RTS_FB_8723D(__pTxDesc, __Value) \ @@ -229,6 +228,8 @@ SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) #define SET_TX_DESC_PORT_ID_8723D(__pTxDesc, __Value) \ SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value) +#define SET_TX_DESC_NAV_USE_HDR_8723D(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) #define SET_TX_DESC_USE_MAX_LEN_8723D(__pTxDesc, __Value) \ SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) #define SET_TX_DESC_MAX_AGG_NUM_8723D(__pTxDesc, __Value) \ @@ -475,6 +476,7 @@ void rtl8723d_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 I #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) s32 rtl8723ds_init_xmit_priv(PADAPTER padapter); diff --git a/include/rtl8812a_cmd.h b/include/rtl8812a_cmd.h index 8979470..17dd2dd 100644 --- a/include/rtl8812a_cmd.h +++ b/include/rtl8812a_cmd.h @@ -98,14 +98,13 @@ struct H2C_SS_RFOFF_PARAM { #define SET_8812_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) -void set_ra_ldpc_8812(struct sta_info *psta, BOOLEAN bLDPC); +void set_ra_ldpc_8812(struct cmn_sta_info *cmn_sta_info, BOOLEAN bLDPC); /* host message to firmware cmd */ s32 fill_h2c_cmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); void rtl8812_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode); void rtl8812_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); u8 rtl8812_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8812_set_raid_cmd(PADAPTER padapter, u32 bitmap, u8 *arg, u8 bw); void rtl8812_set_wowlan_cmd(_adapter *padapter, u8 enable); u8 GetTxBufferRsvdPageNum8812(_adapter *padapter, bool wowlan); @@ -120,18 +119,12 @@ void rtl8812_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); void rtl8812_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); #endif -void CheckFwRsvdPageContent(PADAPTER padapter); - #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW void rtl8812_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); #endif #endif -#ifdef CONFIG_TSF_RESET_OFFLOAD -int reset_tsf(PADAPTER Adapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - /* ------------------------------------ * C2H format * ------------------------------------ */ diff --git a/include/rtl8812a_hal.h b/include/rtl8812a_hal.h index e79a866..77ffe4b 100644 --- a/include/rtl8812a_hal.h +++ b/include/rtl8812a_hal.h @@ -154,7 +154,13 @@ typedef struct _RT_FIRMWARE_8812 { #define FW_NDPA_PAGE_NUM 0x00 #endif -#define TX_TOTAL_PAGE_NUMBER_8812 (0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812-FW_NDPA_PAGE_NUM) +#ifdef DBG_FW_DEBUG_MSG_PKT + #define FW_DBG_MSG_PKT_PAGE_NUM_8812 0x01 +#else + #define FW_DBG_MSG_PKT_PAGE_NUM_8812 0x00 +#endif /*DBG_FW_DEBUG_MSG_PKT*/ + +#define TX_TOTAL_PAGE_NUMBER_8812 (0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 - FW_NDPA_PAGE_NUM - FW_DBG_MSG_PKT_PAGE_NUM_8812) #define TX_PAGE_BOUNDARY_8812 (TX_TOTAL_PAGE_NUMBER_8812 + 1) #define TX_PAGE_BOUNDARY_WOWLAN_8812 (0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 + 1) @@ -214,10 +220,12 @@ typedef struct _RT_FIRMWARE_8812 { #define NORMAL_PAGE_NUM_LPQ_8821 0x08/* 0x10 */ #define NORMAL_PAGE_NUM_HPQ_8821 0x08/* 0x10 */ #define NORMAL_PAGE_NUM_NPQ_8821 0x00 +#define NORMAL_PAGE_NUM_EPQ_8821 0x04 #define WMM_NORMAL_PAGE_NUM_HPQ_8821 0x30 #define WMM_NORMAL_PAGE_NUM_LPQ_8821 0x20 #define WMM_NORMAL_PAGE_NUM_NPQ_8821 0x20 +#define WMM_NORMAL_PAGE_NUM_EPQ_8821 0x00 #define MCC_NORMAL_PAGE_NUM_HPQ_8821 0x10 #define MCC_NORMAL_PAGE_NUM_LPQ_8821 0x10 @@ -326,7 +334,7 @@ void SetBeaconRelatedRegisters8812A(PADAPTER padapter); void ReadRFType8812A(PADAPTER padapter); void InitDefaultValue8821A(PADAPTER padapter); -void SetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval); +u8 SetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval); void GetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval); u8 SetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); @@ -334,6 +342,8 @@ void rtl8812_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8812a(_adapter *adapter); void init_hal_spec_8821a(_adapter *adapter); +u32 upload_txpktbuf_8812au(_adapter *adapter, u8 *buf, u32 buflen); + /* register */ void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits); diff --git a/include/rtl8812a_led.h b/include/rtl8812a_led.h index c28b391..30c676e 100644 --- a/include/rtl8812a_led.h +++ b/include/rtl8812a_led.h @@ -14,8 +14,8 @@ *****************************************************************************/ #ifndef __RTL8812A_LED_H__ #define __RTL8812A_LED_H__ - - +#ifdef CONFIG_RTW_LED +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. * ******************************************************************************** */ @@ -28,9 +28,14 @@ void rtl8812ae_InitSwLeds(PADAPTER padapter); void rtl8812ae_DeInitSwLeds(PADAPTER padapter); #endif #ifdef CONFIG_SDIO_HCI -void rtl8821as_hw_led_config(PADAPTER adapter); void rtl8821as_InitSwLeds(PADAPTER padapter); void rtl8821as_DeInitSwLeds(PADAPTER padapter); #endif +#endif/*CONFIG_RTW_SW_LED*/ +#endif/*#ifdef CONFIG_RTW_LED*/ +#ifdef CONFIG_SDIO_HCI +void rtl8821as_init_led_circuit(PADAPTER adapter); #endif + +#endif /*__RTL8812A_LED_H__*/ diff --git a/include/rtl8812a_rf.h b/include/rtl8812a_rf.h index 1e2c1a0..9a7b60e 100644 --- a/include/rtl8812a_rf.h +++ b/include/rtl8812a_rf.h @@ -18,7 +18,7 @@ VOID PHY_RF6052SetBandwidth8812( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); int diff --git a/include/rtl8812a_spec.h b/include/rtl8812a_spec.h index 3e3927b..37ba247 100644 --- a/include/rtl8812a_spec.h +++ b/include/rtl8812a_spec.h @@ -98,14 +98,17 @@ * 0x0300h ~ 0x03FFh PCIe * * ----------------------------------------------------- */ -#define REG_PCIE_CTRL_REG_8812A 0x0300 +#define REG_PCIE_CTRL_REG_8812A 0x0300 #define REG_DBI_WDATA_8812 0x0348 /* DBI Write Data */ #define REG_DBI_RDATA_8812 0x034C /* DBI Read Data */ -#define REG_DBI_ADDR_8812 0x0350 /* DBI Address */ -#define REG_DBI_FLAG_8812 0x0352 /* DBI Read/Write Flag */ +#define REG_DBI_ADDR_8812 0x0350 /* DBI Address */ +#define REG_DBI_FLAG_8812 0x0352 /* DBI Read/Write Flag */ #define REG_MDIO_WDATA_8812 0x0354 /* MDIO for Write PCIE PHY */ #define REG_MDIO_RDATA_8812 0x0356 /* MDIO for Reads PCIE PHY */ -#define REG_MDIO_CTL_8812 0x0358 /* MDIO for Control */ +#define REG_MDIO_CTL_8812 0x0358 /* MDIO for Control */ +#define REG_PCIE_HRPWM_8812A 0x0361 /* PCIe RPWM */ +#define REG_PCIE_HCPWM_8812A 0x0363 /* PCIe CPWM */ + #define REG_PCIE_MULTIFET_CTRL_8812 0x036A /* PCIE Multi-Fethc Control */ /* ----------------------------------------------------- diff --git a/include/rtl8812a_xmit.h b/include/rtl8812a_xmit.h index 0daa43e..6105a8e 100644 --- a/include/rtl8812a_xmit.h +++ b/include/rtl8812a_xmit.h @@ -321,6 +321,7 @@ void rtl8812a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); #ifdef CONFIG_USB_HCI s32 rtl8812au_init_xmit_priv(PADAPTER padapter); diff --git a/include/rtl8814a_cmd.h b/include/rtl8814a_cmd.h index d17951b..53c2828 100644 --- a/include/rtl8814a_cmd.h +++ b/include/rtl8814a_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -136,7 +136,6 @@ void rtl8814_fw_update_beacon_cmd(_adapter *padapter); #define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) s32 FillH2CCmd_8814(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); -void rtl8814_set_raid_cmd(PADAPTER padapter, u64 bitmap, u8 *arg, u8 bw); void rtl8814_set_wowlan_cmd(_adapter *padapter, u8 enable); void rtl8814_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); void rtl8814_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode); diff --git a/include/rtl8814a_dm.h b/include/rtl8814a_dm.h index f615117..afbc8be 100644 --- a/include/rtl8814a_dm.h +++ b/include/rtl8814a_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/rtl8814a_hal.h b/include/rtl8814a_hal.h index 319ad21..e8b0876 100644 --- a/include/rtl8814a_hal.h +++ b/include/rtl8814a_hal.h @@ -143,7 +143,7 @@ typedef struct _RT_FIRMWARE_8814 { #endif /* #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8814 0x00 + #define WOWLAN_PAGE_NUM_8814 0x06 #else #define WOWLAN_PAGE_NUM_8814 0x00 #endif @@ -196,12 +196,12 @@ Chip specific /* pic buffer descriptor */ #if 1 /* according to the define in the rtw_xmit.h, rtw_recv.h */ #define RTL8814AE_SEG_NUM TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */ - #define TX_DESC_NUM_8814A TXDESC_NUM /* 128 */ + #define TX_DESC_NUM_8814A TX_BD_NUM /* 128 */ #define RX_DESC_NUM_8814A PCI_MAX_RX_COUNT /* 128 */ #ifdef CONFIG_CONCURRENT_MODE - #define BE_QUEUE_TX_DESC_NUM_8814A (TXDESC_NUM<<1) /* 256 */ + #define BE_QUEUE_TX_DESC_NUM_8814A (TX_BD_NUM<<1) /* 256 */ #else - #define BE_QUEUE_TX_DESC_NUM_8814A (TXDESC_NUM+(TXDESC_NUM>>1)) /* 192 */ + #define BE_QUEUE_TX_DESC_NUM_8814A (TX_BD_NUM+(TX_BD_NUM>>1)) /* 192 */ #endif #else #define RTL8814AE_SEG_NUM TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */ @@ -217,6 +217,16 @@ Chip specific * */ #define EFUSE_OOB_PROTECT_BYTES 15 /* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */ +#ifdef CONFIG_FILE_FWIMG +extern char *rtw_fw_file_path; +#ifdef CONFIG_WOWLAN +extern char *rtw_fw_wow_file_path; +#endif +#ifdef CONFIG_MP_INCLUDED +extern char *rtw_fw_mp_bt_file_path; +#endif /* CONFIG_MP_INCLUDED */ +#endif /* CONFIG_FILE_FWIMG */ + /* rtl8814_hal_init.c */ s32 FirmwareDownload8814A(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw); void InitializeFirmwareVars8814(PADAPTER padapter); @@ -292,7 +302,7 @@ void SetBeaconRelatedRegisters8814A(PADAPTER padapter); void ReadRFType8814A(PADAPTER padapter); void InitDefaultValue8814A(PADAPTER padapter); -void SetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval); +u8 SetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval); void GetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval); u8 SetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); @@ -309,7 +319,8 @@ void rtl8814_stop_thread(PADAPTER padapter); #ifdef CONFIG_PCI_HCI BOOLEAN InterruptRecognized8814AE(PADAPTER Adapter); VOID UpdateInterruptMask8814AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); - u16 get_txbd_idx_addr(u16 ff_hwaddr); + VOID InitMAC_TRXBD_8814AE(PADAPTER Adapter); + u16 get_txbd_rw_reg(u16 ff_hwaddr); #endif #ifdef CONFIG_BT_COEXIST diff --git a/include/rtl8814a_led.h b/include/rtl8814a_led.h index 799ae87..cc45792 100644 --- a/include/rtl8814a_led.h +++ b/include/rtl8814a_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -15,7 +15,7 @@ #ifndef __RTL8814A_LED_H__ #define __RTL8814A_LED_H__ - +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. * ******************************************************************************** */ @@ -33,3 +33,4 @@ #endif /* CONFIG_SDIO_HCI */ #endif /* __RTL8814A_LED_H__ */ +#endif /*CONFIG_RTW_SW_LED*/ diff --git a/include/rtl8814a_recv.h b/include/rtl8814a_recv.h index 0963ea8..c6792d8 100644 --- a/include/rtl8814a_recv.h +++ b/include/rtl8814a_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/rtl8814a_rf.h b/include/rtl8814a_rf.h index 17fe1c0..e374439 100644 --- a/include/rtl8814a_rf.h +++ b/include/rtl8814a_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -18,7 +18,7 @@ VOID PHY_RF6052SetBandwidth8814A( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); int diff --git a/include/rtl8814a_spec.h b/include/rtl8814a_spec.h index 3d94e8e..917b961 100644 --- a/include/rtl8814a_spec.h +++ b/include/rtl8814a_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -446,6 +446,8 @@ #define REG_SND_PTCL_CTRL_8814A 0x0718 #define REG_IQ_DUMP_8814A 0x07C0 +#define REG_CPU_DMEM_CON_8814A 0x1080 + /**** page 19 ****/ /* TX BeamForming */ #define REG_BB_TXBF_ANT_SET_BF1 0x19ac @@ -477,6 +479,13 @@ #define REG_DDMA_CHKSUM 0x12F0 #define REG_DDMA_MONITER 0x12FC +#define REG_Q0_Q1_INFO_8814A 0x1400 +#define REG_Q2_Q3_INFO_8814A 0x1404 +#define REG_Q4_Q5_INFO_8814A 0x1408 +#define REG_Q6_Q7_INFO_8814A 0x140C +#define REG_MGQ_HIQ_INFO_8814A 0x1410 +#define REG_CMDQ_BCNQ_INFO_8814A 0x1414 + #define DDMA_LEN_MASK 0x0001FFFF #define FW_CHKSUM_DUMMY_SZ 8 #define DDMA_CH_CHKSUM_CNT BIT(24) diff --git a/include/rtl8814a_sreset.h b/include/rtl8814a_sreset.h index 939b151..d65cb98 100644 --- a/include/rtl8814a_sreset.h +++ b/include/rtl8814a_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/rtl8814a_xmit.h b/include/rtl8814a_xmit.h index bc9310b..5b1e966 100644 --- a/include/rtl8814a_xmit.h +++ b/include/rtl8814a_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 - 2017 Realtek Corporation. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -265,6 +265,7 @@ void rtl8814a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); #ifdef CONFIG_USB_HCI s32 rtl8814au_init_xmit_priv(PADAPTER padapter); @@ -286,6 +287,9 @@ void rtl8814a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 s32 rtl8814ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); s32 rtl8814ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); void rtl8814ae_xmit_tasklet(void *priv); +#ifdef CONFIG_XMIT_THREAD_MODE + s32 rtl8814ae_xmit_buf_handler(_adapter *padapter); +#endif #endif void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, u8 *ptxdesc); diff --git a/include/rtl8821a_spec.h b/include/rtl8821a_spec.h index 44afdff..1379ffc 100644 --- a/include/rtl8821a_spec.h +++ b/include/rtl8821a_spec.h @@ -80,10 +80,8 @@ /* ----------------------------------------------------- * SDIO register * ----------------------------------------------------- */ -#undef SDIO_REG_HCPWM1 #define SDIO_REG_FREE_TXPG2 0x024 -#define SDIO_REG_HCPWM1 0x025 - +#define SDIO_REG_HCPWM1_8821A 0x025 /* ************************************************************ * Regsiter Bit and Content definition diff --git a/include/rtl8821c_dm.h b/include/rtl8821c_dm.h index 7d10941..b1e4fe6 100644 --- a/include/rtl8821c_dm.h +++ b/include/rtl8821c_dm.h @@ -19,7 +19,5 @@ void rtl8821c_phy_init_dm_priv(PADAPTER); void rtl8821c_phy_deinit_dm_priv(PADAPTER); void rtl8821c_phy_init_haldm(PADAPTER); void rtl8821c_phy_haldm_watchdog(PADAPTER); -void rtl8821c_phy_haldm_in_lps(PADAPTER); -void rtl8821c_phy_haldm_watchdog_in_lps(PADAPTER); #endif diff --git a/include/rtl8821c_hal.h b/include/rtl8821c_hal.h index 083af0c..75d8750 100644 --- a/include/rtl8821c_hal.h +++ b/include/rtl8821c_hal.h @@ -43,12 +43,11 @@ #ifndef MAX_RECVBUF_SZ #ifndef CONFIG_MINIMAL_MEMORY_USAGE - #ifdef CONFIG_PLATFORM_MSTAR - #define MAX_RECVBUF_SZ (8192 + RX_FIFO_EXPANDING) /* 8K */ - #else - /* 8821C - RX FIFO :16K ,for RX agg DMA mode = 16K, Rx agg USB mode could large than 16k*/ - #define MAX_RECVBUF_SZ (HALMAC_RX_FIFO_SIZE_8821C + RX_FIFO_EXPANDING) - #endif + /* 8821C - RX FIFO :16K ,for RX agg DMA mode = 16K, Rx agg USB mode could large than 16k*/ + /* #define MAX_RECVBUF_SZ (16384 + RX_FIFO_EXPANDING)*/ + /* For Max throughput issue , need to use USB AGG mode to replace DMA AGG mode*/ + #define MAX_RECVBUF_SZ (32768) + /*#define MAX_RECVBUF_SZ_8821C (24576)*/ /* 24k*/ /*#define MAX_RECVBUF_SZ_8821C (20480)*/ /*20K*/ /*#define MAX_RECVBUF_SZ_8821C (10240) */ /*10K*/ @@ -67,15 +66,18 @@ /*#endif*/ #elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - #define MAX_RECVBUF_SZ (HALMAC_RX_FIFO_SIZE_8821C + RX_FIFO_EXPANDING) + #define MAX_RECVBUF_SZ (16384 + RX_FIFO_EXPANDING) #endif void init_hal_spec_rtl8821c(PADAPTER); /* MP Functions */ #ifdef CONFIG_MP_INCLUDED -void rtl8821c_phy_init_haldm(PADAPTER); /* rtw_mp.c */ void rtl8821c_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ void rtl8821c_mp_config_rfpath(PADAPTER); /* hal_mp.c */ #endif +#ifdef CONFIG_PCI_HCI +u16 get_txbd_rw_reg(u16 q_idx); +#endif + #endif /* _RTL8821C_HAL_H_ */ diff --git a/include/rtl8821c_spec.h b/include/rtl8821c_spec.h index 44865bf..26218df 100644 --- a/include/rtl8821c_spec.h +++ b/include/rtl8821c_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2017 Realtek Corporation. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -30,7 +30,6 @@ #define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ #define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */ #define REG_TSFTR1 REG_FREERUN_CNT_8821C /* hal_com.c */ -#define REG_RXFLTMAP2 REG_RXFLTMAP_8821C /* rtw_mp.c */ #define REG_WOWLAN_WAKE_REASON 0x01C7 #define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8821C @@ -113,7 +112,18 @@ #define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ #define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ #define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ -#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ +/* RFE */ +#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ +#define rB_RFE_Pinmux_Jaguar 0xEB0 /* Path_B RFE control pinmux */ +#define rA_RFE_Inv_Jaguar 0xCB4 /* Path_A RFE cotrol */ +#define rB_RFE_Inv_Jaguar 0xEB4 /* Path_B RFE control */ +#define rA_RFE_Jaguar 0xCB8 /* Path_A RFE cotrol */ +#define rB_RFE_Jaguar 0xEB8 /* Path_B RFE control */ +#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ +#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ +#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ +#define bMask_RFEInv_Jaguar 0x3FF00000 +#define bMask_AntselPathFollow_Jaguar 0x00030000 #define rOFDM1_LSTF 0xD00 #define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ @@ -132,7 +142,6 @@ #define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ #define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ #define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ -#define rB_RFE_Pinmux_Jaguar 0xEB0 /* hal_mp.c */ /* Page1(0x100) */ #define bBBResetB 0x100 diff --git a/include/rtl8822b_hal.h b/include/rtl8822b_hal.h index 307dd61..3cf482e 100644 --- a/include/rtl8822b_hal.h +++ b/include/rtl8822b_hal.h @@ -21,9 +21,9 @@ #ifdef CONFIG_SUPPORT_TRX_SHARED -#define MAX_RECVBUF_SZ HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8822B +#define MAX_RECVBUF_SZ 46080 /* 45KB, TX: (256-64)KB */ #else /* !CONFIG_SUPPORT_TRX_SHARED */ -#define MAX_RECVBUF_SZ HALMAC_RX_FIFO_SIZE_8822B +#define MAX_RECVBUF_SZ 24576 /* 24KB, TX: 256KB */ #endif /* !CONFIG_SUPPORT_TRX_SHARED */ /* @@ -39,7 +39,6 @@ #define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ #define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8822B /* hal_com.c */ #define REG_TSFTR1 REG_FREERUN_CNT_8822B /* hal_com.c */ -#define REG_RXFLTMAP2 REG_RXFLTMAP_8822B /* rtw_mp.c */ #define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c */ #define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8822B /* hal_com.c */ @@ -129,7 +128,6 @@ #define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ #define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ #define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ -#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ #define rOFDM1_LSTF 0xD00 #define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ @@ -148,7 +146,22 @@ #define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ #define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ #define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ -#define rB_RFE_Pinmux_Jaguar 0xEB0 /* hal_mp.c */ +/* RFE */ +#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ +#define rB_RFE_Pinmux_Jaguar 0xEB0 /* Path_B RFE control pinmux */ +#define rA_RFE_Inv_Jaguar 0xCB4 /* Path_A RFE cotrol */ +#define rB_RFE_Inv_Jaguar 0xEB4 /* Path_B RFE control */ +#define rA_RFE_Jaguar 0xCB8 /* Path_A RFE cotrol */ +#define rB_RFE_Jaguar 0xEB8 /* Path_B RFE control */ +#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ +#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ +#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ +#define bMask_RFEInv_Jaguar 0x3FF00000 +#define bMask_AntselPathFollow_Jaguar 0x00030000 + +#define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux*/ +#define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux*/ +#define rA_RFE_Sel_Jaguar2 0x1990 /* Page1(0x100) */ #define bBBResetB 0x100 @@ -201,7 +214,6 @@ void rtl8822b_init_hal_spec(PADAPTER); /* hal/hal_com.c */ #ifdef CONFIG_MP_INCLUDED /* MP Functions */ #include /* struct mp_priv */ -void rtl8822b_phy_init_haldm(PADAPTER); /* rtw_mp.c */ void rtl8822b_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ void rtl8822b_mp_config_rfpath(PADAPTER); /* hal_mp.c */ #endif diff --git a/include/rtl8822be_hal.h b/include/rtl8822be_hal.h index 1755869..a81445f 100644 --- a/include/rtl8822be_hal.h +++ b/include/rtl8822be_hal.h @@ -21,5 +21,7 @@ /* rtl8822be_ops.c */ void UpdateInterruptMask8822BE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); +u16 get_txbd_rw_reg(u16 q_idx); + #endif /* _RTL8822BE_HAL_H_ */ diff --git a/include/rtw_android.h b/include/rtw_android.h index 424a64e..253ee9a 100644 --- a/include/rtw_android.h +++ b/include/rtw_android.h @@ -69,6 +69,7 @@ enum ANDROID_WIFI_CMD { ANDROID_WIFI_CMD_GTK_REKEY_OFFLOAD, #endif /* CONFIG_GTK_OL */ ANDROID_WIFI_CMD_P2P_DISABLE, + ANDROID_WIFI_CMD_SET_AEK, ANDROID_WIFI_CMD_DRIVERVERSION, ANDROID_WIFI_CMD_MAX }; diff --git a/include/rtw_ap.h b/include/rtw_ap.h index 44e2239..8822015 100644 --- a/include/rtw_ap.h +++ b/include/rtw_ap.h @@ -25,12 +25,16 @@ extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info void init_mlme_ap_info(_adapter *padapter); void free_mlme_ap_info(_adapter *padapter); +u8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period + , const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie); /* void update_BCNTIM(_adapter *padapter); */ void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len); void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index); void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *tag); #define update_beacon(adapter, ie_id, oui, tx) _update_beacon((adapter), (ie_id), (oui), (tx), __func__) -void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level, u8 is_update_bw); + +void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta); + void expire_timeout_chk(_adapter *padapter); void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta); void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter); @@ -39,11 +43,15 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len); void rtw_ap_restore_network(_adapter *padapter); #if CONFIG_RTW_MACADDR_ACL -void rtw_set_macaddr_acl(_adapter *adapter, int mode); -int rtw_acl_add_sta(_adapter *adapter, const u8 *addr); -int rtw_acl_remove_sta(_adapter *adapter, const u8 *addr); +void rtw_macaddr_acl_init(_adapter *adapter, u8 period); +void rtw_macaddr_acl_deinit(_adapter *adapter, u8 period); +void rtw_macaddr_acl_clear(_adapter *adapter, u8 period); +void rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode); +int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr); +int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr); #endif /* CONFIG_RTW_MACADDR_ACL */ +u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk); u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta); int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid); int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx); @@ -65,19 +73,32 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow); #ifdef CONFIG_AUTO_AP_MODE +void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos); extern void rtw_start_auto_ap(_adapter *adapter); #endif /* CONFIG_AUTO_AP_MODE */ -void rtw_ap_acdata_control(_adapter *padapter, u8 power_mode); -#endif /* end of CONFIG_AP_MODE */ -#endif +void rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap); +u16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len); +u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems); +void rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len); +void rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems); +void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems); + void update_bmc_sta(_adapter *padapter); +#ifdef CONFIG_BMC_TX_RATE_SELECT +void rtw_update_bmc_sta_tx_rate(_adapter *adapter); +#endif + void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field); void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len); int rtw_ht_operation_update(_adapter *padapter); +u8 rtw_ap_sta_linking_state_check(_adapter *adapter); #ifdef CONFIG_SWTIMER_BASED_TXBCN void tx_beacon_handlder(struct dvobj_priv *pdvobj); void tx_beacon_timer_handlder(void *ctx); -#endif +#endif /*CONFIG_SWTIMER_BASED_TXBCN*/ + +#endif /* end of CONFIG_AP_MODE */ +#endif /*__RTW_AP_H_*/ diff --git a/include/rtw_beamforming.h b/include/rtw_beamforming.h index f589c74..b5875d4 100644 --- a/include/rtw_beamforming.h +++ b/include/rtw_beamforming.h @@ -101,7 +101,7 @@ struct beamformee_entry { /* Used to fill Reg6E4 to fill Mac address of CSI report frame */ u8 mac_addr[ETH_ALEN]; /* Sounding BandWidth */ - CHANNEL_WIDTH sound_bw; + enum channel_width sound_bw; u16 sound_period; enum beamforming_cap cap; @@ -116,7 +116,7 @@ struct beamformee_entry { u8 bApplySounding; /* information for sounding judgement */ - u32 tx_timestamp; + systime tx_timestamp; u64 tx_bytes; u16 LogStatusFailCnt:5; /* 0~21 */ @@ -328,7 +328,7 @@ struct beamforming_entry { u16 p_aid; /* Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ u16 g_id; u8 mac_addr[6];/* Used to fill Reg6E4 to fill Mac address of CSI report frame. */ - CHANNEL_WIDTH sound_bw; /* Sounding BandWidth */ + enum channel_width sound_bw; /* Sounding BandWidth */ u16 sound_period; BEAMFORMING_CAP beamforming_entry_cap; BEAMFORMING_ENTRY_STATE beamforming_entry_state; @@ -346,7 +346,7 @@ struct beamforming_entry { struct sounding_info { u8 sound_idx; - CHANNEL_WIDTH sound_bw; + enum channel_width sound_bw; SOUNDING_MODE sound_mode; u16 sound_period; }; @@ -371,8 +371,8 @@ BEAMFORMING_CAP beamforming_get_entry_beam_cap_by_mac_id(PVOID pmlmepriv , u8 ma void beamforming_notify(PADAPTER adapter); BEAMFORMING_CAP beamforming_get_beamform_cap(struct beamforming_info *pBeamInfo); -BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx); -BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx); +BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx); +BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx); void beamforming_check_sounding_success(PADAPTER Adapter, BOOLEAN status); diff --git a/include/rtw_btcoex.h b/include/rtw_btcoex.h index 847c426..fd42248 100644 --- a/include/rtw_btcoex.h +++ b/include/rtw_btcoex.h @@ -12,6 +12,8 @@ * more details. * *****************************************************************************/ +#ifdef CONFIG_BT_COEXIST + #ifndef __RTW_BTCOEX_H__ #define __RTW_BTCOEX_H__ @@ -364,6 +366,7 @@ struct bt_coex_info { void rtw_btcoex_Initialize(PADAPTER); void rtw_btcoex_PowerOnSetting(PADAPTER padapter); +void rtw_btcoex_AntInfoSetting(PADAPTER padapter); void rtw_btcoex_PowerOffSetting(PADAPTER padapter); void rtw_btcoex_PreLoadFirmware(PADAPTER padapter); void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly); @@ -379,6 +382,8 @@ void rtw_btcoex_BtMpRptNotify(PADAPTER, u8 length, u8 *tmpBuf); void rtw_btcoex_SuspendNotify(PADAPTER, u8 state); void rtw_btcoex_HaltNotify(PADAPTER); void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type); +void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length); +void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id); void rtw_btcoex_SwitchBtTRxMask(PADAPTER); void rtw_btcoex_Switch(PADAPTER, u8 enable); u8 rtw_btcoex_IsBtDisabled(PADAPTER); @@ -444,3 +449,7 @@ void rtw_btcoex_LPS_Enter(PADAPTER padapter); u8 rtw_btcoex_LPS_Leave(PADAPTER padapter); #endif /* __RTW_BTCOEX_H__ */ +#endif /* CONFIG_BT_COEXIST */ + +void rtw_btcoex_set_ant_info(PADAPTER padapter); + diff --git a/include/rtw_btcoex_wifionly.h b/include/rtw_btcoex_wifionly.h index 5410481..c5a0740 100644 --- a/include/rtw_btcoex_wifionly.h +++ b/include/rtw_btcoex_wifionly.h @@ -19,4 +19,5 @@ void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter); void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter); void rtw_btcoex_wifionly_hw_config(PADAPTER padapter); void rtw_btcoex_wifionly_initialize(PADAPTER padapter); +void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter); #endif diff --git a/include/rtw_cmd.h b/include/rtw_cmd.h index 8ae7c9a..914dbb0 100644 --- a/include/rtw_cmd.h +++ b/include/rtw_cmd.h @@ -205,9 +205,21 @@ u8 p2p_roch_cmd(_adapter *adapter , u8 flags ); u8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags); + #endif /* CONFIG_IOCTL_CFG80211 */ #endif /* CONFIG_P2P */ +#ifdef CONFIG_IOCTL_CFG80211 +u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags); +struct mgnt_tx_parm { + u8 tx_ch; + u8 no_cck; + const u8 *buf; + size_t len; + int wait_ack; +}; +#endif + #else /* #include */ #endif /* CONFIG_RTL8711FW */ @@ -240,6 +252,14 @@ enum rtw_drvextra_cmd_id { TEST_H2C_CID, MP_CMD_WK_CID, CUSTOMER_STR_WK_CID, +#ifdef CONFIG_RTW_REPEATER_SON + RSON_SCAN_WK_CID, +#endif + MGNT_TX_WK_CID, +#ifdef CONFIG_MCC_MODE + MCC_SET_DURATION_WK_CID, +#endif /* CONFIG_MCC_MODE */ + REQ_PER_CMD_WK_CID, MAX_WK_CID }; @@ -368,6 +388,11 @@ struct sitesurvey_parm { u8 ch_num; NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; + + u32 token; /* 80211k use it to identify caller */ + u16 duration; /* 0: use default, otherwise: channel scan time */ + u8 igi; /* 0: use defalut */ + u8 bw; /* 0: use default */ }; /* @@ -399,7 +424,6 @@ when 802.1x ==> keyid > 2 ==> unicast key struct setkey_parm { u8 algorithm; /* encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 */ u8 keyid; - u8 grpkey; /* 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x */ u8 set_tx; /* 1: main tx key for wep. 0: other key. */ u8 key[16]; /* this could be 40 or 104 */ }; @@ -414,10 +438,11 @@ when shared key ==> algorithm/keyid */ struct set_stakey_parm { - u8 addr[ETH_ALEN]; - u8 algorithm; - u8 keyid; - u8 key[16]; + u8 addr[ETH_ALEN]; + u8 algorithm; + u8 keyid; + u8 key[16]; + u8 gk; }; struct set_stakey_rsp { @@ -980,13 +1005,19 @@ struct RunInThread_param { #define H2C_RESERVED 0x07 #define H2C_ENQ_HEAD 0x08 #define H2C_ENQ_HEAD_FAIL 0x09 +#define H2C_CMD_FAIL 0x0A extern u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr); extern u8 rtw_setstandby_cmd(_adapter *padapter, uint action); -u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, struct rtw_ieee80211_channel *ch, int ch_num); - +void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm); +u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm); u8 rtw_create_ibss_cmd(_adapter *adapter, int flags); u8 rtw_startbss_cmd(_adapter *adapter, int flags); + +#define REQ_CH_NONE -1 +#define REQ_BW_NONE -1 +#define REQ_OFFSET_NONE -1 + u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags, s16 req_ch, s8 req_bw, s8 req_offset); extern u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch); @@ -997,7 +1028,7 @@ extern u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enque extern u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork); u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags); -extern u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, bool enqueue); +extern u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags); extern u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset); extern u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset); extern u8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr); @@ -1044,13 +1075,6 @@ u8 rtw_dfs_master_cmd(_adapter *adapter, bool enqueue); void rtw_dfs_master_timer_hdl(void *ctx); void rtw_dfs_master_enable(_adapter *adapter, u8 ch, u8 bw, u8 offset); void rtw_dfs_master_disable(_adapter *adapter, u8 ch, u8 bw, u8 offset, bool by_others); -enum { - MLME_STA_CONNECTING, - MLME_STA_CONNECTED, - MLME_STA_DISCONNECTED, - MLME_AP_STARTED, - MLME_AP_STOPPED, -}; void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action); #endif /* CONFIG_DFS_MASTER */ #endif /* CONFIG_AP_MODE */ @@ -1063,7 +1087,7 @@ u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len); u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter); -u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue); +u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags); u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig); u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig); @@ -1086,12 +1110,22 @@ u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt); u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length); #endif +#ifdef CONFIG_RTW_REPEATER_SON +#define RSON_SCAN_PROCESS 10 +#define RSON_SCAN_DISABLE 11 +u8 rtw_rson_scan_wk_cmd(_adapter *adapter, int op); +#endif + u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context); u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta); u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); +#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW) +u8 rtw_req_per_cmd(_adapter * adapter); +#endif + u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf); extern void rtw_survey_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); @@ -1188,6 +1222,7 @@ enum rtw_h2c_cmd { GEN_CMD_CODE(_RunInThreadCMD), /*64*/ GEN_CMD_CODE(_AddBARsp) , /*65*/ + GEN_CMD_CODE(_RM_POST_EVENT), /*66*/ MAX_H2CCMD }; @@ -1275,6 +1310,7 @@ struct _cmd_callback rtw_cmd_callback[] = { {GEN_CMD_CODE(_RunInThreadCMD), NULL},/*64*/ {GEN_CMD_CODE(_AddBARsp), NULL}, /*65*/ + {GEN_CMD_CODE(_RM_POST_EVENT), NULL}, /*66*/ }; #endif diff --git a/include/rtw_debug.h b/include/rtw_debug.h index 74a26de..66f8c5c 100644 --- a/include/rtw_debug.h +++ b/include/rtw_debug.h @@ -63,15 +63,11 @@ extern void rtl871x_cedbg(const char *fmt, ...); #define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) #define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) #define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) -#define _RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) -#define _RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) #define RTW_DBG_EXPR(EXPR) do {} while (0) #define RTW_DBGDUMP 0 /* 'stream' for _dbgdump */ -/* don't use these 3 APIs anymore, will be removed later */ -#define RT_TRACE(_Comp, _Level, Fmt) do {} while (0) #undef _dbgdump @@ -79,18 +75,29 @@ extern void rtl871x_cedbg(const char *fmt, ...); #if defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_XP) #define _dbgdump DbgPrint + #define KERN_CONT #define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg) #elif defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_CE) #define _dbgdump rtl871x_cedbg + #define KERN_CONT #define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg) #elif defined PLATFORM_LINUX #define _dbgdump printk + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) + #define KERN_CONT + #endif #define _seqdump seq_printf #elif defined PLATFORM_FREEBSD #define _dbgdump printf + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) + #define KERN_CONT + #endif #define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg) #endif +void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring, + bool _idx_show, const u8 *_hexdata, int _hexdatalen); + #ifdef CONFIG_RTW_DEBUG #ifndef _OS_INTFS_C_ @@ -142,65 +149,25 @@ extern uint rtw_drv_log_level; } \ } while (0) - #undef RTW_INFO_DUMP -#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) \ - do {\ - if (_DRV_INFO_ <= rtw_drv_log_level) { \ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - _dbgdump("%s", DRIVER_PREFIX); \ - _dbgdump(_TitleString); \ - for (__i = 0; __i < (int)_HexDataLen; __i++) { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) \ - _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } \ - } while (0) +#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) \ + RTW_BUF_DUMP_SEL(_DRV_INFO_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen) #undef RTW_DBG_DUMP -#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) \ - do {\ - if (_DRV_DEBUG_ <= rtw_drv_log_level) { \ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - _dbgdump("%s", DRIVER_PREFIX); \ - _dbgdump(_TitleString); \ - for (__i = 0; __i < (int)_HexDataLen; __i++) { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) \ - _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } \ - } while (0) +#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) \ + RTW_BUF_DUMP_SEL(_DRV_DEBUG_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen) #undef RTW_PRINT_DUMP -#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) \ - do {\ - if (_DRV_ALWAYS_ <= rtw_drv_log_level) { \ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - _dbgdump("%s", DRIVER_PREFIX); \ - _dbgdump(_TitleString); \ - for (__i = 0; __i < (int)_HexDataLen; __i++) { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) \ - _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } \ - } while (0) +#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) \ + RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen) /* without driver-defined prefix */ #undef _RTW_PRINT #define _RTW_PRINT(fmt, arg...) \ do {\ if (_DRV_ALWAYS_ <= rtw_drv_log_level) {\ - _dbgdump(fmt, ##arg);\ + _dbgdump(KERN_CONT fmt, ##arg);\ } \ } while (0) @@ -208,7 +175,7 @@ extern uint rtw_drv_log_level; #define _RTW_ERR(fmt, arg...) \ do {\ if (_DRV_ERR_ <= rtw_drv_log_level) {\ - _dbgdump(fmt, ##arg);\ + _dbgdump(KERN_CONT fmt, ##arg);\ } \ } while (0) @@ -217,7 +184,7 @@ extern uint rtw_drv_log_level; #define _RTW_WARN(fmt, arg...) \ do {\ if (_DRV_WARNING_ <= rtw_drv_log_level) {\ - _dbgdump(fmt, ##arg);\ + _dbgdump(KERN_CONT fmt, ##arg);\ } \ } while (0) @@ -225,7 +192,7 @@ extern uint rtw_drv_log_level; #define _RTW_INFO(fmt, arg...) \ do {\ if (_DRV_INFO_ <= rtw_drv_log_level) {\ - _dbgdump(fmt, ##arg);\ + _dbgdump(KERN_CONT fmt, ##arg);\ } \ } while (0) @@ -233,39 +200,11 @@ extern uint rtw_drv_log_level; #define _RTW_DBG(fmt, arg...) \ do {\ if (_DRV_DEBUG_ <= rtw_drv_log_level) {\ - _dbgdump(fmt, ##arg);\ + _dbgdump(KERN_CONT fmt, ##arg);\ } \ } while (0) -#undef _RTW_INFO_DUMP -#define _RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) \ - if (_DRV_INFO_ <= rtw_drv_log_level) { \ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - _dbgdump(_TitleString); \ - for (__i = 0; __i<(int)_HexDataLen; __i++) \ - { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } - -#undef _RTW_DBG_DUMP -#define _RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) \ - if (_DRV_DEBUG_ <= rtw_drv_log_level) { \ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - _dbgdump(_TitleString); \ - for (__i = 0; __i<(int)_HexDataLen; __i++) \ - { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } - /* other debug APIs */ #undef RTW_DBG_EXPR #define RTW_DBG_EXPR(EXPR) do { if (_DRV_DEBUG_ <= rtw_drv_log_level) EXPR; } while (0) @@ -298,31 +237,12 @@ extern uint rtw_drv_log_level; } while (0) /* dump message to selected 'stream' */ -#undef _RTW_DUMP_SEL -#define _RTW_DUMP_SEL(sel, _HexData, _HexDataLen) \ - do {\ - if (sel == RTW_DBGDUMP) {\ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - for (__i = 0; __i < (int)_HexDataLen; __i++) { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) \ - _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } \ - else {\ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - for (__i = 0; __i < (int)_HexDataLen; __i++) { \ - _seqdump(sel, "%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) \ - _seqdump(sel, "\n"); \ - } \ - _seqdump(sel, "\n"); \ - } \ - } while (0) +#undef RTW_DUMP_SEL +#define RTW_DUMP_SEL(sel, _HexData, _HexDataLen) \ + RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, NULL, _FALSE, _HexData, _HexDataLen) +#define RTW_MAP_DUMP_SEL(sel, _TitleString, _HexData, _HexDataLen) \ + RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, _TitleString, _TRUE, _HexData, _HexDataLen) #endif /* defined(_seqdump) */ @@ -346,7 +266,7 @@ void bb_reg_dump(void *sel, _adapter *adapter); void bb_reg_dump_ex(void *sel, _adapter *adapter); void rf_reg_dump(void *sel, _adapter *adapter); -void rtw_sink_rtp_seq_dbg(_adapter *adapter, _pkt *pkt); +void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos); struct sta_info; void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta); @@ -392,6 +312,10 @@ ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, int proc_get_backop_flags_ap(struct seq_file *m, void *v); ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif /* CONFIG_SCAN_BACKOP */ +#ifdef CONFIG_RTW_REPEATER_SON +int proc_get_rson_data(struct seq_file *m, void *v); +ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif int proc_get_survey_info(struct seq_file *m, void *v); ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_ap_info(struct seq_file *m, void *v); @@ -408,20 +332,20 @@ ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t cou int proc_get_rx_cnt_dump(struct seq_file *m, void *v); ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif -int proc_get_dis_pwt(struct seq_file *m, void *v); -ssize_t proc_set_dis_pwt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_suspend_resume_info(struct seq_file *m, void *v); +#ifdef CONFIG_AP_MODE +int proc_get_bmc_tx_rate(struct seq_file *m, void *v); +ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /*CONFIG_AP_MODE*/ + +int proc_get_ps_dbg_info(struct seq_file *m, void *v); +ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); bool rtw_fwdl_test_trigger_chksum_fail(void); bool rtw_fwdl_test_trigger_wintint_rdy_fail(void); ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void); ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#ifdef CONFIG_DFS_MASTER -int proc_get_dfs_master_test_case(struct seq_file *m, void *v); -ssize_t proc_set_dfs_master_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#endif /* CONFIG_DFS_MASTER */ u32 rtw_get_wait_hiq_empty_ms(void); ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); void rtw_sta_linking_test_set_start(void); @@ -538,12 +462,19 @@ int proc_get_int_logs(struct seq_file *m, void *v); int proc_get_rx_ring(struct seq_file *m, void *v); int proc_get_tx_ring(struct seq_file *m, void *v); int proc_get_pci_aspm(struct seq_file *m, void *v); +#ifdef DBG_TXBD_DESC_DUMP +int proc_get_tx_ring_ext(struct seq_file *m, void *v); +ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif #endif #ifdef CONFIG_WOWLAN int proc_get_pattern_info(struct seq_file *m, void *v); ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_wakeup_event(struct seq_file *m, void *v); +ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data); int proc_get_wakeup_reason(struct seq_file *m, void *v); #endif @@ -562,9 +493,15 @@ ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_ #ifdef CONFIG_POWER_SAVING int proc_get_ps_info(struct seq_file *m, void *v); +#ifdef CONFIG_WMMPS_STA +int proc_get_wmmps_info(struct seq_file *m, void *v); +ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /* CONFIG_WMMPS_STA */ #endif /* CONFIG_POWER_SAVING */ #ifdef CONFIG_TDLS +int proc_get_tdls_enable(struct seq_file *m, void *v); +ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_tdls_info(struct seq_file *m, void *v); #endif @@ -597,6 +534,7 @@ ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t #ifdef CONFIG_MCC_MODE int proc_get_mcc_info(struct seq_file *m, void *v); ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); ssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); ssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); @@ -605,14 +543,20 @@ ssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *bu ssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_mcc_policy_table(struct seq_file *m, void *v); -ssize_t proc_set_mcc_policy_table(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif /* CONFIG_MCC_MODE */ int proc_get_ack_timeout(struct seq_file *m, void *v); ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_iqk_fw_offload(struct seq_file *m, void *v); -ssize_t proc_set_iqk_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_fw_offload(struct seq_file *m, void *v); +ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +#ifdef CONFIG_DBG_RF_CAL +int proc_get_iqk_info(struct seq_file *m, void *v); +ssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_lck_info(struct seq_file *m, void *v); +ssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /*CONFIG_DBG_RF_CAL*/ #define _drv_always_ 1 #define _drv_emerg_ 2 diff --git a/include/rtw_ht.h b/include/rtw_ht.h index 028f2c8..2c7aa2f 100644 --- a/include/rtw_ht.h +++ b/include/rtw_ht.h @@ -15,6 +15,8 @@ #ifndef _RTW_HT_H_ #define _RTW_HT_H_ +#define HT_CAP_IE_LEN 26 +#define HT_OP_IE_LEN 22 struct ht_priv { u8 ht_option; @@ -42,7 +44,10 @@ struct ht_priv { u8 beamform_cap; u8 smps_cap; /*spatial multiplexing power save mode. 0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/ + u8 op_present:1; /* ht_op is present */ + struct rtw_ieee80211_ht_cap ht_cap; + u8 ht_op[HT_OP_IE_LEN]; }; @@ -84,12 +89,6 @@ typedef enum _RT_HT_INF1_CAP { #define STBC_HT_TEST_TX_ENABLE BIT2 #define STBC_HT_CAP_TX BIT3 -#define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */ -#define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */ -#define BEAMFORMING_HT_BEAMFORMER_TEST BIT2 /* Transmiting Beamforming no matter the target supports it or not */ -#define BEAMFORMING_HT_BEAMFORMER_STEER_NUM (BIT4 | BIT5) -#define BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP (BIT6 | BIT7) - /* ------------------------------------------------------------ * The HT Control field * ------------------------------------------------------------ */ @@ -144,6 +143,9 @@ typedef enum _RT_HT_INF1_CAP { , (1 << (13+GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(((u8 *)x)-2)))-1 \ , GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(((u8 *)x)-2) +#define SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val) +#define SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 3, _val) + /* Supported MCS Set field */ #define HT_CAP_ELE_SUP_MCS_SET(_pEleStart) (((u8 *)(_pEleStart))+3) #define HT_CAP_ELE_RX_MCS_MAP(_pEleStart) HT_CAP_ELE_SUP_MCS_SET(_pEleStart) @@ -153,11 +155,14 @@ typedef enum _RT_HT_INF1_CAP { #define GET_HT_CAP_ELE_TX_MAX_SS(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 2, 2) #define GET_HT_CAP_ELE_TX_UEQM(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 4, 1) -#define HT_SUP_MCS_SET_FMT "%02x %02x %02x %02x %02x%02x%02x%02x%02x%02x" \ +#define HT_RX_MCS_BMP_FMT "%02x %02x %02x %02x %02x%02x%02x%02x%02x%02x" +#define HT_RX_MCS_BMP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \ + ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9] + +#define HT_SUP_MCS_SET_FMT HT_RX_MCS_BMP_FMT \ /* "\n%02x%02x%02x%02x%02x%02x" */\ " %uMbps %s%s%s" -#define HT_SUP_MCS_SET_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \ - ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9] \ +#define HT_SUP_MCS_SET_ARG(x) HT_RX_MCS_BMP_ARG(x) \ /*,((u8 *)(x))[10], ((u8 *)(x))[11], ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] */\ , GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(((u8 *)x)-3) \ , GET_HT_CAP_ELE_TX_MCS_DEF(((u8 *)x)-3) ? "TX_MCS_DEF " : "" \ diff --git a/include/rtw_ioctl_set.h b/include/rtw_ioctl_set.h index 1d252ca..2bfe570 100644 --- a/include/rtw_ioctl_set.h +++ b/include/rtw_ioctl_set.h @@ -46,17 +46,14 @@ void rtw_pnp_sleep_wk(void *context); #endif -u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key); u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode); u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid); u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep); u8 rtw_set_802_11_disassociate(_adapter *padapter); -u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num, struct rtw_ieee80211_channel *ch, int ch_num); +u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm); u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype); -u8 rtw_set_802_11_remove_wep(_adapter *padapter, u32 keyindex); u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid); u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid); -u8 rtw_set_802_11_remove_key(_adapter *padapter, NDIS_802_11_REMOVE_KEY *key); u8 rtw_validate_bssid(u8 *bssid); u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid); diff --git a/include/rtw_mcc.h b/include/rtw_mcc.h index e73e9cf..62e880e 100644 --- a/include/rtw_mcc.h +++ b/include/rtw_mcc.h @@ -28,6 +28,7 @@ #define MCC_SWCH_FW_EARLY_TIME 10 /* ms */ #define MCC_EXPIRE_TIME 50 /* ms */ #define MCC_TOLERANCE_TIME 2 /* 2*2 = 4s */ +#define MCC_UPDATE_PARAMETER_THRESHOLD 5 /* ms */ #define MCC_ROLE_STA_GC_MGMT_QUEUE_MACID 0 #define MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID 1 @@ -55,8 +56,19 @@ #define MAX_MCC_NUM 2 #define MCC_STOP(adapter) (adapter->mcc_adapterpriv.mcc_tx_stop) -#define MCC_EN(adapter) (adapter->registrypriv.en_mcc) - +#define MCC_EN(adapter) (adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc) +#define SET_MCC_EN_FLAG(adapter, flag)\ + do { \ + adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc = (flag); \ + } while (0) +#define SET_MCC_DURATION(adapter, val)\ + do { \ + adapter_to_dvobj(adapter)->mcc_objpriv.duration = (val); \ + } while (0) +#define SET_MCC_RUNTIME_DURATION(adapter, flag)\ + do { \ + adapter_to_dvobj(adapter)->mcc_objpriv.enable_runtime_duration = (flag); \ + } while (0) /* Represent Channel Tx Null setting */ enum mcc_channel_tx_null { MCC_ENABLE_TX_NULL = 0, @@ -84,6 +96,7 @@ enum mcc_status_rpt { MCC_RPT_READY = 3, MCC_RPT_SWICH_CHANNEL_NOTIFY = 7, MCC_RPT_UPDATE_NOA_START_TIME = 8, + MCC_RPT_TSF = 9, MCC_RPT_MAX, }; @@ -102,6 +115,17 @@ struct mcc_iqk_backup { u16 RX_Y; }; +enum MCC_DURATION_SETTING { + MCC_DURATION_MAPPING = 0, + MCC_DURATION_DIRECET = 1, +}; + +enum MCC_SCHED_MODE { + MCC_FAIR_SCHEDULE = 0, + MCC_FAVOE_STA = 1, + MCC_FAVOE_P2P = 2, +}; + /* mcc data for adapter */ struct mcc_adapter_priv { u8 order; /* FW document, softap/AP must be 0 */ @@ -134,10 +158,20 @@ struct mcc_adapter_priv { u8 p2p_go_noa_ie[MAX_P2P_IE_LEN]; u32 p2p_go_noa_ie_len; + u64 tsf; +#ifdef CONFIG_TDLS + u8 backup_tdls_en; +#endif /* CONFIG_TDLS */ + + u8 null_early; + u8 null_rty_num; }; struct mcc_obj_priv { - u8 duration; /* channel stay period, UNIT:1TU */ + u8 en_mcc; /* enable MCC or not */ + u8 duration; /* store duration(%) from registry, for primary adapter */ + u8 interval; + u8 start_time; u8 mcc_c2h_status; u8 cur_mcc_success_cnt; /* used for check mcc switch channel success */ u8 prev_mcc_success_cnt; /* used for check mcc switch channel success */ @@ -145,11 +179,23 @@ struct mcc_obj_priv { u8 mcc_loc_rsvd_paga[MAX_MCC_NUM]; /* mcc rsvd page */ u8 mcc_status; /* mcc status stop or start .... */ u8 policy_index; + u8 mcc_stop_threshold; + u8 current_order; + u8 last_tsfdiff; u32 mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */ _mutex mcc_mutex; _lock mcc_lock; PADAPTER iface[MAX_MCC_NUM]; /* by order, use for mcc parameter cmd */ struct submit_ctx mcc_sctx; + struct submit_ctx mcc_tsf_req_sctx; +#ifdef CONFIG_MCC_MODE_V2 + u8 mcc_iqk_value_rsvd_page[3]; +#endif /* CONFIG_MCC_MODE_V2 */ + u8 mcc_pwr_idx_rsvd_page[MAX_MCC_NUM]; + u8 enable_runtime_duration; + u32 backup_phydm_ability; + /* for LG */ + u8 mchan_sched_mode; }; /* backup IQK val */ @@ -166,7 +212,7 @@ void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status); /* dl mcc rsvd page */ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index - , u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len, RSVDPAGE_LOC *rsvd_page_loc); + , u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num); /* handle C2H */ void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf); @@ -208,9 +254,16 @@ void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode); u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len); -void rtw_hal_mcc_update_switch_channel_policy_table(PADAPTER padapter); - void rtw_hal_dump_mcc_policy_table(void *sel); +void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add); + +void rtw_hal_mcc_process_noa(PADAPTER padapter); + +void rtw_hal_mcc_parameter_init(PADAPTER padapter); + +u8 rtw_set_mcc_duration_hdl(PADAPTER adapter, u8 type, const u8 *val); + +u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val); #endif /* _RTW_MCC_H_ */ #endif /* CONFIG_MCC_MODE */ diff --git a/include/rtw_mi.h b/include/rtw_mi.h index 153aa39..dfbac2d 100644 --- a/include/rtw_mi.h +++ b/include/rtw_mi.h @@ -16,19 +16,32 @@ #define __RTW_MI_H_ void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw); +u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter); +u8 rtw_mi_stayin_union_band_chk(_adapter *adapter); int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset); int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset); struct mi_state { - u8 sta_num; /*WIFI_FW_STATION_STATE*/ - u8 ld_sta_num; /*WIFI_FW_STATION_STATE |_FW_LINKED*/ - u8 lg_sta_num; /*WIFI_FW_STATION_STATE |_FW_UNDER_LINKING*/ - u8 ap_num; /*WIFI_FW_AP_STATE|_FW_LINKED*/ - u8 ld_ap_num; /*WIFI_FW_AP_STATE|_FW_LINKED && asoc_sta_count > 2*/ - u8 adhoc_num; /* WIFI_FW_ADHOC_STATE */ - u8 ld_adhoc_num; /* WIFI_FW_ADHOC_STATE && asoc_sta_count > 2 */ - u8 uwps_num; /*WIFI_UNDER_WPS*/ - + u8 sta_num; /* WIFI_STATION_STATE */ + u8 ld_sta_num; /* WIFI_STATION_STATE && _FW_LINKED */ + u8 lg_sta_num; /* WIFI_STATION_STATE && _FW_UNDER_LINKING */ +#ifdef CONFIG_TDLS + u8 ld_tdls_num; /* adapter.tdlsinfo.link_established */ +#endif +#ifdef CONFIG_AP_MODE + u8 ap_num; /* WIFI_AP_STATE && _FW_LINKED */ + u8 starting_ap_num; /*WIFI_FW_AP_STATE*/ + u8 ld_ap_num; /* WIFI_AP_STATE && _FW_LINKED && asoc_sta_count > 2 */ +#endif + u8 adhoc_num; /* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && _FW_LINKED */ + u8 ld_adhoc_num; /* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && _FW_LINKED && asoc_sta_count > 2 */ +#ifdef CONFIG_RTW_MESH + u8 mesh_num; /* WIFI_MESH_STATE && _FW_LINKED */ + u8 ld_mesh_num; /* WIFI_MESH_STATE && _FW_LINKED && asoc_sta_count > 2 */ +#endif + u8 scan_num; /* WIFI_SITE_MONITOR */ + u8 scan_enter_num; /* WIFI_SITE_MONITOR && !SCAN_DISABLE && !SCAN_BACK_OP */ + u8 uwps_num; /* WIFI_UNDER_WPS */ #ifdef CONFIG_IOCTL_CFG80211 #ifdef CONFIG_P2P u8 roch_num; @@ -44,10 +57,36 @@ struct mi_state { #define MSTATE_STA_NUM(_mstate) ((_mstate)->sta_num) #define MSTATE_STA_LD_NUM(_mstate) ((_mstate)->ld_sta_num) #define MSTATE_STA_LG_NUM(_mstate) ((_mstate)->lg_sta_num) + +#ifdef CONFIG_TDLS +#define MSTATE_TDLS_LD_NUM(_mstate) ((_mstate)->ld_tdls_num) +#else +#define MSTATE_TDLS_LD_NUM(_mstate) 0 +#endif + +#ifdef CONFIG_AP_MODE #define MSTATE_AP_NUM(_mstate) ((_mstate)->ap_num) +#define MSTATE_AP_STARTING_NUM(_mstate) ((_mstate)->starting_ap_num) #define MSTATE_AP_LD_NUM(_mstate) ((_mstate)->ld_ap_num) +#else +#define MSTATE_AP_NUM(_mstate) 0 +#define MSTATE_AP_STARTING_NUM(_mstate) 0 +#define MSTATE_AP_LD_NUM(_mstate) 0 +#endif + #define MSTATE_ADHOC_NUM(_mstate) ((_mstate)->adhoc_num) #define MSTATE_ADHOC_LD_NUM(_mstate) ((_mstate)->ld_adhoc_num) + +#ifdef CONFIG_RTW_MESH +#define MSTATE_MESH_NUM(_mstate) ((_mstate)->mesh_num) +#define MSTATE_MESH_LD_NUM(_mstate) ((_mstate)->ld_mesh_num) +#else +#define MSTATE_MESH_NUM(_mstate) 0 +#define MSTATE_MESH_LD_NUM(_mstate) 0 +#endif + +#define MSTATE_SCAN_NUM(_mstate) ((_mstate)->scan_num) +#define MSTATE_SCAN_ENTER_NUM(_mstate) ((_mstate)->scan_enter_num) #define MSTATE_WPS_NUM(_mstate) ((_mstate)->uwps_num) #if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P) @@ -72,26 +111,38 @@ struct mi_state { #define rtw_mi_get_assoced_sta_num(adapter) DEV_STA_LD_NUM(adapter_to_dvobj(adapter)) #define rtw_mi_get_ap_num(adapter) DEV_AP_NUM(adapter_to_dvobj(adapter)) +#define rtw_mi_get_mesh_num(adapter) DEV_MESH_NUM(adapter_to_dvobj(adapter)) /* For now, not return union_ch/bw/offset */ void rtw_mi_status(_adapter *adapter, struct mi_state *mstate); void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate); +void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate); + +/* For now, not handle union_ch/bw/offset */ +void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a); void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state); -u8 rtw_mi_netif_stop_queue(_adapter *padapter, bool carrier_off); -u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter, bool carrier_off); +u8 rtw_mi_netif_stop_queue(_adapter *padapter); +u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter); u8 rtw_mi_netif_wake_queue(_adapter *padapter); u8 rtw_mi_buddy_netif_wake_queue(_adapter *padapter); u8 rtw_mi_netif_carrier_on(_adapter *padapter); u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter); +u8 rtw_mi_netif_carrier_off(_adapter *padapter); +u8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter); + +u8 rtw_mi_netif_caroff_qstop(_adapter *padapter); +u8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter); +u8 rtw_mi_netif_caron_qstart(_adapter *padapter); +u8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter); void rtw_mi_scan_abort(_adapter *adapter, bool bwait); void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait); -void rtw_mi_start_drv_threads(_adapter *adapter); -void rtw_mi_buddy_start_drv_threads(_adapter *adapter); +u32 rtw_mi_start_drv_threads(_adapter *adapter); +u32 rtw_mi_buddy_start_drv_threads(_adapter *adapter); void rtw_mi_stop_drv_threads(_adapter *adapter); void rtw_mi_buddy_stop_drv_threads(_adapter *adapter); void rtw_mi_cancel_all_timer(_adapter *adapter); @@ -120,9 +171,6 @@ void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms); u8 rtw_mi_is_scan_deny(_adapter *adapter); u8 rtw_mi_buddy_is_scan_deny(_adapter *adapter); -u8 rtw_mi_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); -u8 rtw_mi_buddy_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); - void rtw_mi_beacon_update(_adapter *padapter); void rtw_mi_buddy_beacon_update(_adapter *padapter); @@ -150,6 +198,8 @@ enum { MI_AP_ASSOC, MI_ADHOC, MI_ADHOC_ASSOC, + MI_MESH, + MI_MESH_ASSOC, MI_STA_NOLINK, /* this is misleading, but not used now */ MI_STA_LINKED, MI_STA_LINKING, @@ -230,9 +280,4 @@ _adapter *rtw_mi_get_ap_adapter(_adapter *padapter); void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b); -#ifdef CONFIG_AP_MODE -void rtw_mi_ap_acdata_control(_adapter *padapter, u8 power_mode); -void rtw_mi_buddy_ap_acdata_control(_adapter *padapter, u8 power_mode); -#endif /*CONFIG_AP_MODE*/ - #endif /*__RTW_MI_H_*/ diff --git a/include/rtw_mlme.h b/include/rtw_mlme.h index 9880aaf..114a3ec 100644 --- a/include/rtw_mlme.h +++ b/include/rtw_mlme.h @@ -24,14 +24,6 @@ /* Commented by Albert 20101105 * Increase the scanning timeout because of increasing the SURVEY_TO value. */ -#define SCANNING_TIMEOUT 8000 -#ifdef CONFIG_CHNL_LOAD_MAGT -#define CLM_SCANNING_TIMEOUT 9000 -#endif -#ifdef CONFIG_SCAN_BACKOP -#define CONC_SCANNING_TIMEOUT_SINGLE_BAND 10000 -#define CONC_SCANNING_TIMEOUT_DUAL_BAND 15000 -#endif #ifdef PALTFORM_OS_WINCE #define SCANQUEUE_LIFETIME 12000000 /* unit:us */ @@ -49,7 +41,7 @@ #define WIFI_ADHOC_MASTER_STATE 0x00000040 #define WIFI_UNDER_LINKING 0x00000080 #define WIFI_UNDER_WPS 0x00000100 -/*#define WIFI_UNDEFINED_STATE 0x00000200*/ +#define WIFI_MESH_STATE 0x00000200 #define WIFI_STA_ALIVE_CHK_STATE 0x00000400 #define WIFI_SITE_MONITOR 0x00000800 /* under site surveying */ #define WIFI_WDS 0x00001000 @@ -86,13 +78,16 @@ const char *get_miracast_mode_str(int mode); void rtw_wfd_st_switch(struct sta_info *sta, bool on); #define MLME_STATE(adapter) get_fwstate(&((adapter)->mlmepriv)) - -#define MLME_IS_STA(adapter) (MLME_STATE((adapter)) & WIFI_STATION_STATE) -#define MLME_IS_AP(adapter) (MLME_STATE((adapter)) & WIFI_AP_STATE) -#define MLME_IS_ADHOC(adapter) (MLME_STATE((adapter)) & WIFI_ADHOC_STATE) -#define MLME_IS_ADHOC_MASTER(adapter) (MLME_STATE((adapter)) & WIFI_ADHOC_MASTER_STATE) -#define MLME_IS_MONITOR(adapter) (MLME_STATE((adapter)) & WIFI_MONITOR_STATE) -#define MLME_IS_MP(adapter) (MLME_STATE((adapter)) & WIFI_MP_STATE) +#define CHK_MLME_STATE(adapter, state) check_fwstate(&((adapter)->mlmepriv), (state)) + +#define MLME_IS_NULL(adapter) CHK_MLME_STATE(adapter, WIFI_NULL_STATE) +#define MLME_IS_STA(adapter) CHK_MLME_STATE(adapter, WIFI_STATION_STATE) +#define MLME_IS_AP(adapter) CHK_MLME_STATE(adapter, WIFI_AP_STATE) +#define MLME_IS_ADHOC(adapter) CHK_MLME_STATE(adapter, WIFI_ADHOC_STATE) +#define MLME_IS_ADHOC_MASTER(adapter) CHK_MLME_STATE(adapter, WIFI_ADHOC_MASTER_STATE) +#define MLME_IS_MESH(adapter) CHK_MLME_STATE(adapter, WIFI_MESH_STATE) +#define MLME_IS_MONITOR(adapter) CHK_MLME_STATE(adapter, WIFI_MONITOR_STATE) +#define MLME_IS_MP(adapter) CHK_MLME_STATE(adapter, WIFI_MP_STATE) #ifdef CONFIG_P2P #define MLME_IS_PD(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_DEVICE) #define MLME_IS_GC(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_CLIENT) @@ -103,15 +98,21 @@ void rtw_wfd_st_switch(struct sta_info *sta, bool on); #define MLME_IS_GO(adapter) 0 #endif /* !CONFIG_P2P */ +#define MLME_IS_MSRC(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SOURCE) +#define MLME_IS_MSINK(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SINK) + +#define MLME_IS_SCAN(adapter) CHK_MLME_STATE(adapter, WIFI_SITE_MONITOR) +#define MLME_IS_LINKING(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_LINKING) +#define MLME_IS_ASOC(adapter) CHK_MLME_STATE(adapter, WIFI_ASOC_STATE) +#define MLME_IS_OPCH_SW(adapter) CHK_MLME_STATE(adapter, WIFI_OP_CH_SWITCHING) +#define MLME_IS_WPS(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_WPS) + #if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P) #define MLME_IS_ROCH(adapter) (rtw_cfg80211_get_is_roch(adapter) == _TRUE) #else #define MLME_IS_ROCH(adapter) 0 #endif -#define MLME_IS_MSRC(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SOURCE) -#define MLME_IS_MSINK(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SINK) - #ifdef CONFIG_IOCTL_CFG80211 #define MLME_IS_MGMT_TX(adapter) rtw_cfg80211_get_is_mgmt_tx(adapter) #else @@ -124,20 +125,41 @@ void rtw_wfd_st_switch(struct sta_info *sta, bool on); MLME_IS_AP((adapter)) ? (MLME_IS_GO((adapter)) ? " GO" : " AP") : \ MLME_IS_ADHOC((adapter)) ? " ADHOC" : \ MLME_IS_ADHOC_MASTER((adapter)) ? " ADHOC_M" : \ + MLME_IS_MESH((adapter)) ? " MESH" : \ MLME_IS_MONITOR((adapter)) ? " MONITOR" : \ MLME_IS_MP((adapter)) ? " MP" : "", \ MLME_IS_PD((adapter)) ? " PD" : "", \ MLME_IS_MSRC((adapter)) ? " MSRC" : "", \ MLME_IS_MSINK((adapter)) ? " MSINK" : "", \ - (MLME_STATE((adapter)) & WIFI_SITE_MONITOR) ? " SCAN" : "", \ - (MLME_STATE((adapter)) & WIFI_UNDER_LINKING) ? " LINKING" : "", \ - (MLME_STATE((adapter)) & WIFI_ASOC_STATE) ? " ASOC" : "", \ - (MLME_STATE((adapter)) & WIFI_OP_CH_SWITCHING) ? " OP_CH_SW" : "", \ - (MLME_STATE((adapter)) & WIFI_UNDER_WPS) ? " WPS" : "", \ + MLME_IS_SCAN((adapter)) ? " SCAN" : "", \ + MLME_IS_LINKING((adapter)) ? " LINKING" : "", \ + MLME_IS_ASOC((adapter)) ? " ASOC" : "", \ + MLME_IS_OPCH_SW((adapter)) ? " OPCH_SW" : "", \ + MLME_IS_WPS((adapter)) ? " WPS" : "", \ MLME_IS_ROCH((adapter)) ? " ROCH" : "", \ MLME_IS_MGMT_TX((adapter)) ? " MGMT_TX" : "", \ (MLME_STATE((adapter)) & WIFI_SLEEP_STATE) ? " SLEEP" : "" +enum { + MLME_ACTION_UNKNOWN, + MLME_ACTION_NONE, + MLME_SCAN_ENABLE, /* WIFI_SITE_MONITOR */ + MLME_SCAN_ENTER, /* WIFI_SITE_MONITOR && !SCAN_DISABLE && !SCAN_BACK_OP */ + MLME_SCAN_DONE, /* WIFI_SITE_MONITOR && (SCAN_DISABLE || SCAN_BACK_OP) */ + MLME_SCAN_DISABLE, /* WIFI_SITE_MONITOR is going to be cleared */ + MLME_STA_CONNECTING, + MLME_STA_CONNECTED, + MLME_STA_DISCONNECTED, + MLME_TDLS_LINKED, + MLME_TDLS_NOLINK, + MLME_AP_STARTED, + MLME_AP_STOPPED, + MLME_ADHOC_STARTED, + MLME_ADHOC_STOPPED, + MLME_MESH_STARTED, + MLME_MESH_STOPPED, +}; + #define _FW_UNDER_LINKING WIFI_UNDER_LINKING #define _FW_LINKED WIFI_ASOC_STATE #define _FW_UNDER_SURVEY WIFI_SITE_MONITOR @@ -307,7 +329,7 @@ struct cfg80211_wifidirect_info { u64 remain_on_ch_cookie; bool is_ro_ch; struct wireless_dev *ro_ch_wdev; - u32 last_ro_ch_time; /* this will be updated at the beginning and end of ro_ch */ + systime last_ro_ch_time; /* this will be updated at the beginning and end of ro_ch */ }; #endif /* CONFIG_IOCTL_CFG80211 */ @@ -377,7 +399,7 @@ struct wifidirect_info { u8 p2p_peer_device_addr[ETH_ALEN]; u8 peer_intent; /* Included the intent value and tie breaker value. */ u8 device_name[WPS_MAX_DEVICE_NAME_LEN]; /* Device name for displaying on searching device screen */ - u8 device_name_len; + u16 device_name_len; u8 profileindex; /* Used to point to the index of profileinfo array */ u8 peer_operating_ch; u8 find_phase_state_exchange_cnt; @@ -477,13 +499,14 @@ struct tdls_info { _lock hdl_lock; u8 watchdog_count; u8 dev_discovered; /* WFD_TDLS: for sigma test */ - u8 tdls_enable; /* Let wpa_supplicant to setup*/ u8 driver_setup; #ifdef CONFIG_WFD struct wifi_display_info *wfd_info; #endif + + struct submit_ctx *tdls_sctx; }; struct tdls_txmgmt { @@ -514,9 +537,10 @@ struct beacon_keys { int is_8021x; }; #ifdef CONFIG_RTW_80211R -#define FT_ACTION_REQ_LIMIT 4 +#define RTW_FT_ACTION_REQ_LMT 4 +#define RTW_FT_MAX_IE_SZ 256 -typedef enum _RTW_WIFI_FT_STA_STATUS { +enum _rtw_ft_sta_status { RTW_FT_UNASSOCIATED_STA = 0, RTW_FT_AUTHENTICATING_STA, RTW_FT_AUTHENTICATED_STA, @@ -526,58 +550,204 @@ typedef enum _RTW_WIFI_FT_STA_STATUS { RTW_FT_REQUESTED_STA, RTW_FT_CONFIRMED_STA, RTW_FT_UNSPECIFIED_STA -} RTW_WIFI_FT_STA_STATUS; +}; + +#define rtw_ft_chk_status(a, s) \ + ((a)->mlmepriv.ft_roam.ft_status == (s)) -#define rtw_chk_ft_status(adapter, status) ((adapter)->mlmepriv.ftpriv.ft_status == status) -#define rtw_set_ft_status(adapter, status) \ +#define rtw_ft_roam_status(a, s) \ + ((rtw_to_roam(a) > 0) && rtw_ft_chk_status(a, s)) + +#define rtw_ft_authed_sta(a) \ + ((rtw_ft_chk_status(a, RTW_FT_AUTHENTICATED_STA)) || \ + (rtw_ft_chk_status(a, RTW_FT_ASSOCIATING_STA)) || \ + (rtw_ft_chk_status(a, RTW_FT_ASSOCIATED_STA))) + +#define rtw_ft_set_status(a, s) \ + do { \ + ((a)->mlmepriv.ft_roam.ft_status = (s)); \ + } while (0) + +#define rtw_ft_lock_set_status(a, s, irq) \ do { \ - ((adapter)->mlmepriv.ftpriv.ft_status = status); \ + _enter_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq))); \ + ((a)->mlmepriv.ft_roam.ft_status = (s)); \ + _exit_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq))); \ } while (0) -#define rtw_reset_ft_status(adapter) \ +#define rtw_ft_reset_status(a) \ do { \ - ((adapter)->mlmepriv.ftpriv.ft_status = RTW_FT_UNASSOCIATED_STA); \ + ((a)->mlmepriv.ft_roam.ft_status = RTW_FT_UNASSOCIATED_STA); \ } while (0) -typedef enum _RTW_WIFI_FT_CAPABILITY { - RTW_FT_STA_SUPPORTED = BIT0, - RTW_FT_STA_OVER_DS_SUPPORTED = BIT1, - RTW_FT_SUPPORTED = BIT2, - RTW_FT_OVER_DS_SUPPORTED = BIT3, -} RTW_WIFI_FT_CAPABILITY; +enum rtw_ft_capability { + RTW_FT_EN = BIT0, + RTW_FT_OTD_EN = BIT1, + RTW_FT_PEER_EN = BIT2, + RTW_FT_PEER_OTD_EN = BIT3, + RTW_FT_BTM_ROAM = BIT4, +}; + +#define rtw_ft_chk_flags(a, f) \ + ((a)->mlmepriv.ft_roam.ft_flags & (f)) -#define rtw_chk_ft_flags(adapter, flags) ((adapter)->mlmepriv.ftpriv.ft_flags & (flags)) -#define rtw_set_ft_flags(adapter, flags) \ +#define rtw_ft_set_flags(a, f) \ do { \ - ((adapter)->mlmepriv.ftpriv.ft_flags |= (flags)); \ + ((a)->mlmepriv.ft_roam.ft_flags |= (f)); \ } while (0) -#define rtw_clr_ft_flags(adapter, flags) \ +#define rtw_ft_clr_flags(a, f) \ do { \ - ((adapter)->mlmepriv.ftpriv.ft_flags &= ~(flags)); \ + ((a)->mlmepriv.ft_roam.ft_flags &= ~(f)); \ } while (0) -#define RTW_MAX_FTIE_SZ 256 -typedef struct _ft_priv { +#define rtw_ft_roam(a) \ + ((rtw_to_roam(a) > 0) && rtw_ft_chk_flags(a, RTW_FT_PEER_EN)) + +#define rtw_ft_valid_akm(a, t) \ + ((rtw_ft_chk_flags(a, RTW_FT_EN)) && \ + (((t) == 3) || ((t) == 4))) + +#define rtw_ft_roam_expired(a, r) \ + ((rtw_chk_roam_flags(a, RTW_ROAM_ON_EXPIRED)) \ + && (r == WLAN_REASON_ACTIVE_ROAM)) + +#define rtw_ft_otd_roam_en(a) \ + ((rtw_ft_chk_flags(a, RTW_FT_OTD_EN)) \ + && ((a)->mlmepriv.ft_roam.ft_roam_on_expired == _FALSE) \ + && ((a)->mlmepriv.ft_roam.ft_cap & 0x01)) + +#define rtw_ft_otd_roam(a) \ + rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN) + +#define rtw_ft_valid_otd_candidate(a, p) \ + ((rtw_ft_chk_flags(a, RTW_FT_OTD_EN)) \ + && ((rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN) \ + && ((*((p)+4) & 0x01) == 0)) \ + || ((rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN) == 0) \ + && (*((p)+4) & 0x01)))) + +struct ft_roam_info { u16 mdid; - u8 ft_cap; /*b0: FT over DS, b1: Resource Req Protocol Cap, b2~b7: Reserved*/ - u8 updated_ft_ies[RTW_MAX_FTIE_SZ]; + u8 ft_cap; + /*b0: FT over DS, b1: Resource Req Protocol Cap, b2~b7: Reserved*/ + u8 updated_ft_ies[RTW_FT_MAX_IE_SZ]; u16 updated_ft_ies_len; - u8 ft_action[RTW_MAX_FTIE_SZ]; + u8 ft_action[RTW_FT_MAX_IE_SZ]; u16 ft_action_len; struct cfg80211_ft_event_params ft_event; u8 ft_roam_on_expired; u8 ft_flags; u32 ft_status; u32 ft_req_retry_cnt; -} ft_priv; + bool ft_updated_bcn; +}; +#endif + +#ifdef CONFIG_LAYER2_ROAMING +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) +#define RTW_RRM_NB_RPT_EN BIT(1) +#define RTW_MAX_NB_RPT_NUM 8 + +#define rtw_roam_busy_scan(a, nb) \ + (((a)->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE) && \ + (((a)->mlmepriv.ch_cnt) < ((nb)->nb_rpt_ch_list_num))) + +#define rtw_wnm_btm_preference_cap(a) \ + ((a)->mlmepriv.nb_info.preference_en == _TRUE) + +#define rtw_wnm_btm_diff_bss(a) \ + ((rtw_wnm_btm_preference_cap(a)) && \ + (is_zero_mac_addr((a)->mlmepriv.nb_info.roam_target_addr) == _FALSE) && \ + (_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\ + (a)->mlmepriv.cur_network.network.MacAddress, ETH_ALEN) == _FALSE)) + +#define rtw_wnm_btm_roam_candidate(a, c) \ + ((rtw_wnm_btm_preference_cap(a)) && \ + (is_zero_mac_addr((a)->mlmepriv.nb_info.roam_target_addr) == _FALSE) && \ + (_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\ + (c)->network.MacAddress, ETH_ALEN))) + +#define rtw_wnm_set_ext_cap_btm(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 3, 1, _val) + +#define wnm_btm_bss_term_inc(p) (*((u8 *)((p)+3)) & BSS_TERMINATION_INCLUDED) + +#define wnm_btm_ess_disassoc_im(p) (*((u8 *)((p)+3)) & ESS_DISASSOC_IMMINENT) + +#define wnm_btm_req_mode(p) (*((u8 *)((p)+3))) + +#define wnm_btm_disassoc_timer(p) (*((u16 *)((p)+4))) + +#define wnm_btm_valid_interval(p) (*((u8 *)((p)+6))) + +#define wnm_btm_term_duration_offset(p) ((p)+7) + +/*IEEE Std 80211k Figure 7-95b Neighbor Report element format*/ +struct nb_rpt_hdr { + u8 id; /*0x34: Neighbor Report Element ID*/ + u8 len; + u8 bssid[ETH_ALEN]; + u32 bss_info; + u8 reg_class; + u8 ch_num; + u8 phy_type; +}; + +/*IEEE Std 80211v, Figure 7-95e2¡XBSS Termination Duration subelement field format */ +struct btm_term_duration { + u8 id; + u8 len; + u64 tsf; + u16 duration; +}; + +/*IEEE Std 80211v, Figure 7-101n8¡XBSS Transition Management Request frame body format */ +struct btm_req_hdr { + u8 req_mode; + u16 disassoc_timer; + u8 validity_interval; + struct btm_term_duration term_duration; +}; + +/*IEEE Std 80211v, Table 7-43b Optional Subelement IDs for Neighbor Report*/ +/* BSS Transition Candidate Preference */ +#define WNM_BTM_CAND_PREF_SUBEID 0x03 + +/* BSS Termination Duration */ +#define WNM_BTM_TERM_DUR_SUBEID 0x04 + +struct wnm_btm_cant { + struct nb_rpt_hdr nb_rpt; + u8 preference; /* BSS Transition Candidate Preference */ +}; + +enum rtw_btm_req_mod { + PREFERRED_CANDIDATE_LIST_INCLUDED = BIT0, + ABRIDGED = BIT1, + DISASSOC_IMMINENT = BIT2, + BSS_TERMINATION_INCLUDED = BIT3, + ESS_DISASSOC_IMMINENT = BIT4, +}; + +struct roam_nb_info { + struct nb_rpt_hdr nb_rpt[RTW_MAX_NB_RPT_NUM]; + struct rtw_ieee80211_channel nb_rpt_ch_list[RTW_MAX_NB_RPT_NUM]; + bool nb_rpt_valid; + u8 nb_rpt_ch_list_num; + u8 preference_en; + u8 roam_target_addr[ETH_ALEN]; + u32 last_nb_rpt_entries; + bool nb_rpt_is_same; + _timer roam_scan_timer; +}; +#endif /* defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) */ #endif struct mlme_priv { _lock lock; sint fw_state; /* shall we protect this variable? maybe not necessarily... */ - u8 bScanInProcess; u8 to_join; /* flag */ #ifdef CONFIG_LAYER2_ROAMING u8 to_roam; /* roaming trying times */ @@ -628,7 +798,7 @@ struct mlme_priv { uint assoc_by_rssi; _timer scan_to_timer; /* driver itself handles scan_timeout status. */ - u32 scan_start_time; /* used to evaluate the time spent in scanning */ + systime scan_start_time; /* used to evaluate the time spent in scanning */ #ifdef CONFIG_SET_SCAN_DENY_TIMER _timer set_scan_deny_timer; @@ -671,7 +841,11 @@ struct mlme_priv { _timer dfs_master_timer; #endif #ifdef CONFIG_RTW_80211R - ft_priv ftpriv; + struct ft_roam_info ft_roam; +#endif +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) + struct roam_nb_info nb_info; + u8 ch_cnt; #endif RT_LINK_DETECT_T LinkDetectInfo; @@ -766,6 +940,9 @@ struct mlme_priv { u8 ori_ch; u8 ori_bw; u8 ori_offset; + #ifdef CONFIG_80211AC_VHT + u8 ori_vht_en; + #endif #endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ #if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) @@ -820,7 +997,7 @@ struct mlme_priv { u8 p2p_reject_disable; /* When starting NL80211 wpa_supplicant/hostapd, it will call netdev_close */ /* such that it will cause p2p disabled. Use this flag to reject. */ #endif /* CONFIG_INTEL_WIDI */ - u32 lastscantime; + systime lastscantime; #ifdef CONFIG_CONCURRENT_MODE u8 scanning_via_buddy_intf; #endif @@ -848,10 +1025,11 @@ struct mlme_priv { adapter->mlmepriv.auto_scan_int_ms = ms; \ } while (0) -#define RTW_AUTO_SCAN_REASON_UNSPECIFIED 0 -#define RTW_AUTO_SCAN_REASON_2040_BSS BIT0 -#define RTW_AUTO_SCAN_REASON_ACS BIT1 -#define RTW_AUTO_SCAN_REASON_ROAM BIT2 +#define RTW_AUTO_SCAN_REASON_UNSPECIFIED 0 +#define RTW_AUTO_SCAN_REASON_2040_BSS BIT0 +#define RTW_AUTO_SCAN_REASON_ACS BIT1 +#define RTW_AUTO_SCAN_REASON_ROAM BIT2 +#define RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND BIT3 void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason); @@ -878,6 +1056,7 @@ extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf); +void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id); void rtw_sta_mstatus_report(_adapter *adapter); extern void rtw_atimdone_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf); @@ -886,9 +1065,15 @@ extern void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf); void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf); #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_RTW_80211R -void rtw_update_ft_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork); +void rtw_ft_info_init(struct ft_roam_info *pft); +u8 rtw_ft_chk_roaming_candidate(_adapter *padapter, + struct wlan_network *competitor); +void rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork); void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf); #endif +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) +void rtw_roam_nb_info_init(_adapter *padapter); +#endif thread_return event_thread(thread_context context); @@ -938,32 +1123,17 @@ extern void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state); static inline void set_fwstate(struct mlme_priv *pmlmepriv, sint state) { pmlmepriv->fw_state |= state; - - /*bScanInProcess hook in phydm*/ - if (_FW_UNDER_SURVEY == state) - pmlmepriv->bScanInProcess = _TRUE; - rtw_mi_update_iface_status(pmlmepriv, state); } static inline void init_fwstate(struct mlme_priv *pmlmepriv, sint state) { pmlmepriv->fw_state = state; - - /*bScanInProcess hook in phydm*/ - if (_FW_UNDER_SURVEY == state) - pmlmepriv->bScanInProcess = _TRUE; - rtw_mi_update_iface_status(pmlmepriv, state); } static inline void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state) { pmlmepriv->fw_state &= ~state; - - /*bScanInProcess hook in phydm*/ - if (_FW_UNDER_SURVEY == state) - pmlmepriv->bScanInProcess = _FALSE; - rtw_mi_update_iface_status(pmlmepriv, state); } @@ -1009,10 +1179,11 @@ __inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint v } extern u16 rtw_get_capability(WLAN_BSSID_EX *bss); -extern void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target); +extern bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target); extern void rtw_disconnect_hdl_under_linked(_adapter *adapter, struct sta_info *psta, u8 free_assoc); extern void rtw_generate_random_ibss(u8 *pibss); -extern struct wlan_network *rtw_find_network(_queue *scanned_queue, u8 *addr); +struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr); +struct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr); extern struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue); struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network); struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network); @@ -1027,8 +1198,13 @@ void rtw_scan_wait_completed(_adapter *adapter); u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms); void rtw_scan_abort_no_wait(_adapter *adapter); void rtw_scan_abort(_adapter *adapter); +u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms); -extern int rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len); +extern int rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie); +#ifdef CONFIG_WMMPS_STA +void rtw_uapsd_use_default_setting(_adapter *padapter); +bool rtw_is_wmmps_mode(_adapter *padapter); +#endif /* CONFIG_WMMPS_STA */ extern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len); extern void rtw_init_registrypriv_dev_network(_adapter *adapter); @@ -1075,9 +1251,6 @@ extern struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv); extern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall); extern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork); - -extern struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr); - extern void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall); extern sint rtw_if_up(_adapter *padapter); @@ -1151,6 +1324,7 @@ struct sta_media_status_rpt_cmd_parm { void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected); u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected); void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm); +void rtw_sta_traffic_info(void *sel, _adapter *adapter); #ifdef CONFIG_INTEL_PROXIM void rtw_proxim_enable(_adapter *padapter); diff --git a/include/rtw_mlme_ext.h b/include/rtw_mlme_ext.h index 2871f97..6a784a9 100644 --- a/include/rtw_mlme_ext.h +++ b/include/rtw_mlme_ext.h @@ -21,11 +21,8 @@ * The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. * So, this driver tried to extend the dwell time for each scanning channel. * This will increase the chance to receive the probe response from SoftAP. */ -#ifdef CONFIG_CHNL_LOAD_MAGT - #define SURVEY_TO (200) -#else - #define SURVEY_TO (100) -#endif +#define SURVEY_TO (100) + #define REAUTH_TO (300) /* (50) */ #define REASSOC_TO (300) /* (50) */ /* #define DISCONNECT_TO (3000) */ @@ -128,6 +125,10 @@ typedef enum _RT_CHANNEL_DOMAIN { RTW_CHPLAN_WORLD_FCC2 = 0x29, RTW_CHPLAN_FCC2_NULL = 0x2A, RTW_CHPLAN_IC1_IC2 = 0x2B, + RTW_CHPLAN_MKK2_NULL = 0x2C, + RTW_CHPLAN_WORLD_CHILE1= 0x2D, + RTW_CHPLAN_WORLD1_WORLD1 = 0x2E, + RTW_CHPLAN_WORLD_CHILE2 = 0x2F, RTW_CHPLAN_WORLD_FCC3 = 0x30, RTW_CHPLAN_WORLD_FCC4 = 0x31, RTW_CHPLAN_WORLD_FCC5 = 0x32, @@ -138,12 +139,16 @@ typedef enum _RT_CHANNEL_DOMAIN { RTW_CHPLAN_MKK1_MKK2 = 0x37, RTW_CHPLAN_MKK1_MKK3 = 0x38, RTW_CHPLAN_FCC1_NCC1 = 0x39, + RTW_CHPLAN_ETSI1_ETSI1 = 0x3A, + RTW_CHPLAN_ETSI1_ACMA1 = 0x3B, + RTW_CHPLAN_ETSI1_ETSI6 = 0x3C, + RTW_CHPLAN_ETSI1_ETSI12 = 0x3D, RTW_CHPLAN_FCC1_NCC2 = 0x40, RTW_CHPLAN_GLOBAL_NULL = 0x41, RTW_CHPLAN_ETSI1_ETSI4 = 0x42, RTW_CHPLAN_FCC1_FCC2 = 0x43, RTW_CHPLAN_FCC1_NCC3 = 0x44, - RTW_CHPLAN_WORLD_ETSI5 = 0x45, + RTW_CHPLAN_WORLD_ACMA1 = 0x45, RTW_CHPLAN_FCC1_FCC8 = 0x46, RTW_CHPLAN_WORLD_ETSI6 = 0x47, RTW_CHPLAN_WORLD_ETSI7 = 0x48, @@ -183,89 +188,13 @@ typedef enum _RT_CHANNEL_DOMAIN { RTW_CHPLAN_FCC2_FCC11 = 0x76, RTW_CHPLAN_WORLD_ETSI21 = 0x77, RTW_CHPLAN_FCC1_FCC18 = 0x78, + RTW_CHPLAN_MKK2_MKK1 = 0x79, RTW_CHPLAN_MAX, RTW_CHPLAN_REALTEK_DEFINE = 0x7F, + RTW_CHPLAN_UNSPECIFIED = 0xFF, } RT_CHANNEL_DOMAIN, *PRT_CHANNEL_DOMAIN; -typedef enum _RT_CHANNEL_DOMAIN_2G { - RTW_RD_2G_NULL = 0, - RTW_RD_2G_WORLD = 1, /* Worldwird 13 */ - RTW_RD_2G_ETSI1 = 2, /* Europe */ - RTW_RD_2G_FCC1 = 3, /* US */ - RTW_RD_2G_MKK1 = 4, /* Japan */ - RTW_RD_2G_ETSI2 = 5, /* France */ - RTW_RD_2G_GLOBAL = 6, /* Global domain */ - RTW_RD_2G_MKK2 = 7, /* Japan */ - RTW_RD_2G_FCC2 = 8, /* US */ - RTW_RD_2G_IC1 = 9, /* Canada */ - - RTW_RD_2G_MAX, -} RT_CHANNEL_DOMAIN_2G, *PRT_CHANNEL_DOMAIN_2G; - -typedef enum _RT_CHANNEL_DOMAIN_5G { - RTW_RD_5G_NULL = 0, /* */ - RTW_RD_5G_ETSI1 = 1, /* Europe */ - RTW_RD_5G_ETSI2 = 2, /* Australia, New Zealand */ - RTW_RD_5G_ETSI3 = 3, /* Russia */ - RTW_RD_5G_FCC1 = 4, /* US */ - RTW_RD_5G_FCC2 = 5, /* FCC w/o DFS Channels */ - RTW_RD_5G_FCC3 = 6, /* Bolivia, Chile, El Salvador, Venezuela */ - RTW_RD_5G_FCC4 = 7, /* Venezuela */ - RTW_RD_5G_FCC5 = 8, /* China */ - RTW_RD_5G_FCC6 = 9, /* */ - RTW_RD_5G_FCC7 = 10, /* US(w/o Weather radar) */ - RTW_RD_5G_IC1 = 11, /* Canada(w/o Weather radar) */ - RTW_RD_5G_KCC1 = 12, /* Korea */ - RTW_RD_5G_MKK1 = 13, /* Japan */ - RTW_RD_5G_MKK2 = 14, /* Japan (W52, W53) */ - RTW_RD_5G_MKK3 = 15, /* Japan (W56) */ - RTW_RD_5G_NCC1 = 16, /* Taiwan, (w/o Weather radar) */ - RTW_RD_5G_NCC2 = 17, /* Taiwan, Band2, Band4 */ - RTW_RD_5G_NCC3 = 18, /* Taiwan w/o DFS, Band4 only */ - RTW_RD_5G_ETSI4 = 19, /* Europe w/o DFS, Band1 only */ - RTW_RD_5G_ETSI5 = 20, /* Australia, New Zealand(w/o Weather radar) */ - RTW_RD_5G_FCC8 = 21, /* Latin America */ - RTW_RD_5G_ETSI6 = 22, /* Israel, Bahrain, Egypt, India, China, Malaysia */ - RTW_RD_5G_ETSI7 = 23, /* China */ - RTW_RD_5G_ETSI8 = 24, /* Jordan */ - RTW_RD_5G_ETSI9 = 25, /* Lebanon */ - RTW_RD_5G_ETSI10 = 26, /* Qatar */ - RTW_RD_5G_ETSI11 = 27, /* Russia */ - RTW_RD_5G_NCC4 = 28, /* Taiwan, (w/o Weather radar) */ - RTW_RD_5G_ETSI12 = 29, /* Indonesia */ - RTW_RD_5G_FCC9 = 30, /* (w/o Weather radar) */ - RTW_RD_5G_ETSI13 = 31, /* (w/o Weather radar) */ - RTW_RD_5G_FCC10 = 32, /* Argentina(w/o Weather radar) */ - RTW_RD_5G_MKK4 = 33, /* Japan (W52) */ - RTW_RD_5G_ETSI14 = 34, /* Russia */ - RTW_RD_5G_FCC11 = 35, /* US(include CH144) */ - RTW_RD_5G_ETSI15 = 36, /* Malaysia */ - RTW_RD_5G_MKK5 = 37, /* Japan */ - RTW_RD_5G_ETSI16 = 38, /* Europe */ - RTW_RD_5G_ETSI17 = 39, /* Europe */ - RTW_RD_5G_FCC12 = 40, /* FCC */ - RTW_RD_5G_FCC13 = 41, /* FCC */ - RTW_RD_5G_FCC14 = 42, /* FCC w/o Weather radar(w/o 5600~5650MHz) */ - RTW_RD_5G_FCC15 = 43, /* FCC w/o Band3 */ - RTW_RD_5G_FCC16 = 44, /* FCC w/o Band3 */ - RTW_RD_5G_ETSI18 = 45, /* ETSI w/o DFS Band2&3 */ - RTW_RD_5G_ETSI19 = 46, /* Europe */ - RTW_RD_5G_FCC17 = 47, /* FCC w/o Weather radar(w/o 5600~5650MHz) */ - RTW_RD_5G_ETSI20 = 48, /* Europe */ - RTW_RD_5G_IC2 = 49, /* Canada(w/o Weather radar), include ch144 */ - RTW_RD_5G_ETSI21 = 50, /* Australia, New Zealand(w/o Weather radar) */ - RTW_RD_5G_FCC18 = 51, /* */ - RTW_RD_5G_WORLD = 52, /* Worldwide */ - - /* === Below are driver defined for legacy channel plan compatible, DON'T assign index ==== */ - RTW_RD_5G_OLD_FCC1, - RTW_RD_5G_OLD_NCC1, - RTW_RD_5G_OLD_KCC1, - - RTW_RD_5G_MAX, -} RT_CHANNEL_DOMAIN_5G, *PRT_CHANNEL_DOMAIN_5G; - bool rtw_chplan_is_empty(u8 id); #define rtw_is_channel_plan_valid(chplan) (((chplan) < RTW_CHPLAN_MAX || (chplan) == RTW_CHPLAN_REALTEK_DEFINE) && !rtw_chplan_is_empty(chplan)) #define rtw_is_legacy_channel_plan(chplan) ((chplan) < 0x20) @@ -389,6 +318,7 @@ struct ss_res { #endif int scan_mode; u16 scan_ch_ms; + u32 scan_timeout_ms; u8 rx_ampdu_accept; u8 rx_ampdu_size; u8 igi_scan; @@ -399,7 +329,7 @@ struct ss_res { u8 backop_flags; /* per backop runtime decision */ u8 scan_cnt; u8 scan_cnt_max; - u32 backop_time; /* the start time of backop */ + systime backop_time; /* the start time of backop */ u16 backop_ms; #endif #if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) @@ -409,6 +339,11 @@ struct ss_res { u8 ch_num; NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; + + u32 token; /* 0: use to identify caller */ + u16 duration; /* 0: use default */ + u8 igi; /* 0: use defalut */ + u8 bw; /* 0: use default */ }; /* #define AP_MODE 0x0C */ @@ -445,7 +380,9 @@ enum TDLS_option { TDLS_CH_SW_END, TDLS_RS_RCR, TDLS_TEARDOWN_STA, + TDLS_TEARDOWN_STA_NO_WAIT, TDLS_TEARDOWN_STA_LOCALLY, + TDLS_TEARDOWN_STA_LOCALLY_POST, maxTDLS, }; @@ -543,10 +480,16 @@ typedef struct _RT_CHANNEL_INFO { #endif #ifdef CONFIG_DFS #ifdef CONFIG_DFS_MASTER - u32 non_ocp_end_time; + systime non_ocp_end_time; #endif u8 hidden_bss_cnt; /* per scan count */ #endif + +#ifdef CONFIG_RTW_MESH + #if CONFIG_RTW_MESH_OFFCH_CAND + u8 mesh_candidate_cnt; /* update at scan done for specific mesh iface */ + #endif +#endif /* CONFIG_RTW_MESH */ } RT_CHANNEL_INFO, *PRT_CHANNEL_INFO; #define DFS_MASTER_TIMER_MS 100 @@ -562,7 +505,7 @@ void rtw_rfctl_deinit(_adapter *adapter); #ifdef CONFIG_DFS_MASTER struct rf_ctl_t; -#define CH_IS_NON_OCP(rt_ch_info) (time_after((unsigned long)(rt_ch_info)->non_ocp_end_time, (unsigned long)rtw_get_current_time())) +#define CH_IS_NON_OCP(rt_ch_info) (rtw_time_after((rt_ch_info)->non_ocp_end_time, rtw_get_current_time())) bool rtw_is_cac_reset_needed(_adapter *adapter, u8 ch, u8 bw, u8 offset); bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset); bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl); @@ -572,6 +515,7 @@ void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms); u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms); void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset); +u32 rtw_force_stop_cac(_adapter *adapter, u32 timeout_ms); #else #define CH_IS_NON_OCP(rt_ch_info) 0 #define rtw_chset_is_ch_non_ocp(ch_set, ch, bw, offset) _FALSE @@ -588,7 +532,9 @@ enum { RTW_CHF_NON_OCP = BIT6, }; -bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset, u8 d_flags); +bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 sel_ch, u8 max_bw + , u8 *dec_ch, u8 *dec_bw, u8 *dec_offset + , u8 d_flags, u8 cur_ch, u8 same_band_prefer); void dump_country_chplan(void *sel, const struct country_chplan *ent); void dump_country_chplan_map(void *sel); @@ -599,6 +545,8 @@ void dump_cur_chset(void *sel, _adapter *adapter); int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch); u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); +void rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset + , u8 *g_ch, u8 *g_bw, u8 *g_offset); bool rtw_mlme_band_check(_adapter *adapter, const u32 ch); @@ -653,9 +601,7 @@ struct mlme_ext_priv { u16 mgnt_seq; #ifdef CONFIG_IEEE80211W u16 sa_query_seq; - u64 mgnt_80211w_IPN; - u64 mgnt_80211w_IPN_rx; -#endif /* CONFIG_IEEE80211W */ +#endif /* struct fw_priv fwpriv; */ unsigned char cur_channel; @@ -674,13 +620,18 @@ struct mlme_ext_priv { * for ap mode, network includes ap's cap_info */ _timer survey_timer; _timer link_timer; + +#ifdef CONFIG_RTW_REPEATER_SON + _timer rson_scan_timer; +#endif #ifdef CONFIG_RTW_80211R _timer ft_link_timer; _timer ft_roam_timer; #endif - u32 last_scan_time; + systime last_scan_time; u8 scan_abort; + u8 join_abort; u8 tx_rate; /* TXRATE when USERATE is set. */ u32 retry; /* retry for issue probereq */ @@ -724,6 +675,8 @@ static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state) return _FALSE; } +void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state); + #define mlmeext_msr(mlmeext) ((mlmeext)->mlmext_info.state & 0x03) #define mlmeext_scan_state(mlmeext) ((mlmeext)->sitesurvey_res.state) #define mlmeext_scan_state_str(mlmeext) scan_state_str((mlmeext)->sitesurvey_res.state) @@ -732,7 +685,9 @@ static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state) do { \ ((mlmeext)->sitesurvey_res.state = (_state)); \ ((mlmeext)->sitesurvey_res.next_state = (_state)); \ + rtw_mi_update_iface_status(&((container_of(mlmeext, _adapter, mlmeextpriv)->mlmepriv)), 0); \ /* RTW_INFO("set_scan_state:%s\n", scan_state_str(_state)); */ \ + sitesurvey_set_offch_state(container_of(mlmeext, _adapter, mlmeextpriv), _state); \ } while (0) #define mlmeext_scan_next_state(mlmeext) ((mlmeext)->sitesurvey_res.next_state) @@ -777,6 +732,7 @@ static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state) #define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) (0) #define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) do {} while (0) #endif +u32 rtw_scan_timeout_decision(_adapter *padapter); void init_mlme_default_rate_set(_adapter *padapter); int init_mlme_ext_priv(_adapter *padapter); @@ -786,10 +742,6 @@ extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv); struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv); /* void fill_fwpriv(_adapter * padapter, struct fw_priv *pfwpriv); */ -#ifdef CONFIG_GET_RAID_BY_DRV -unsigned char networktype_to_raid(_adapter *adapter, struct sta_info *psta); -unsigned char networktype_to_raid_ex(_adapter *adapter, struct sta_info *psta); -#endif u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen); void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len); void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask); @@ -806,11 +758,10 @@ void rtw_set_oper_bw(_adapter *adapter, u8 bw); u8 rtw_get_oper_choffset(_adapter *adapter); void rtw_set_oper_choffset(_adapter *adapter, u8 offset); u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset); -u32 rtw_get_on_oper_ch_time(_adapter *adapter); -u32 rtw_get_on_cur_ch_time(_adapter *adapter); +systime rtw_get_on_oper_ch_time(_adapter *adapter); +systime rtw_get_on_cur_ch_time(_adapter *adapter); u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset); -u8 rtw_get_offset_by_ch(u8 channel); void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode); @@ -841,7 +792,6 @@ void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType); u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid); void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter *padapter, bool update_ie); -int get_bsstype(unsigned short capability); u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork); u16 get_beacon_interval(WLAN_BSSID_EX *bss); @@ -873,7 +823,7 @@ void rtw_dump_bcn_keys(struct beacon_keys *recv_beacon); int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len); void update_beacon_info(_adapter *padapter, u8 *pframe, uint len, struct sta_info *psta); #ifdef CONFIG_DFS -void process_csa_ie(_adapter *padapter, u8 *pframe, uint len); +void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len); #endif /* CONFIG_DFS */ void update_capinfo(PADAPTER Adapter, u16 updateCap); void update_wireless_mode(_adapter *padapter); @@ -890,7 +840,10 @@ void set_sta_rate(_adapter *padapter, struct sta_info *psta); unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated); -unsigned char get_highest_rate_idx(u32 mask); +unsigned char get_highest_rate_idx(u64 mask); +unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit); +#define get_lowest_rate_idx(mask) get_lowest_rate_idx_ex(mask, 0) + int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode); unsigned int is_ap_in_tkip(_adapter *padapter); unsigned int is_ap_in_wep(_adapter *padapter); @@ -910,7 +863,7 @@ void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map); bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id); bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id); s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk); -s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used); +s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool *used); void rtw_camid_free(_adapter *adapter, u8 cam_id); u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id); @@ -918,9 +871,12 @@ struct macid_bmp; struct macid_ctl_t; void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num); bool rtw_macid_is_set(struct macid_bmp *map, u8 id); +void rtw_macid_map_clr(struct macid_bmp *map, u8 id); bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id); bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id); -s8 rtw_macid_get_if_g(struct macid_ctl_t *macid_ctl, u8 id); +u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id); +bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id); +bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter); s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id); void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta); void rtw_release_macid(_adapter *padapter, struct sta_info *psta); @@ -930,9 +886,25 @@ void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw); void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en); void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp); void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp); +void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3); void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl); void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl); u8 rtw_iface_bcmc_id_get(_adapter *padapter); +void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id); + +bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id); +void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id); +void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id); +bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len); +bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len); + +#ifdef CONFIG_AP_MODE +bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id); +void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id); +void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id); +bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map); +bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map); +#endif /* CONFIG_AP_MODE */ u32 report_join_res(_adapter *padapter, int res); void report_survey_event(_adapter *padapter, union recv_frame *precv_frame); @@ -972,11 +944,10 @@ void issue_assocreq(_adapter *padapter); void issue_reassocreq(_adapter *padapter); void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type); void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status); -void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da); -s32 issue_probereq_ex(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps, int try_cnt, int wait_ms); +void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da); +s32 issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int try_cnt, int wait_ms); int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); -s32 issue_nulldata_in_interrupt(PADAPTER padapter, u8 *da, unsigned int power_mode); -int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_cnt, int wait_ms); +int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms); int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason); int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, int wait_ms); void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset); @@ -985,6 +956,7 @@ void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms); void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator); int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator, int try_cnt, int wait_ms); +void issue_action_BSSCoexistPacket(_adapter *padapter); #ifdef CONFIG_IEEE80211W void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type); @@ -1048,17 +1020,38 @@ unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame); #ifdef CONFIG_IEEE80211W unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame); #endif /* CONFIG_IEEE80211W */ +unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame); #ifdef CONFIG_RTW_80211R -void start_clnt_ft_action(_adapter *padapter, u8 *pTargetAddr); -void issue_action_ft_request(_adapter *padapter, u8 *pTargetAddr); -void report_ft_event(_adapter *padapter); -void report_ft_reassoc_event(_adapter *padapter, u8 *pMacAddr); -void ft_link_timer_hdl(void *ctx); -void ft_roam_timer_hdl(void *ctx); +void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame); +void rtw_ft_start_clnt_join(_adapter *padapter); +u8 rtw_ft_update_rsnie(_adapter *padapter, u8 bwrite, + struct pkt_attrib *pattrib, u8 **pframe); +void rtw_ft_build_auth_req_ies(_adapter *padapter, + struct pkt_attrib *pattrib, u8 **pframe); +void rtw_ft_build_assoc_req_ies(_adapter *padapter, + u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe); +u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len); +void rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr); +void rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr); +void rtw_ft_report_evt(_adapter *padapter); +void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr); +void rtw_ft_link_timer_hdl(void *ctx); +void rtw_ft_roam_timer_hdl(void *ctx); +void rtw_ft_roam_status_reset(_adapter *padapter); +#endif +#ifdef CONFIG_RTW_WNM +void rtw_wnm_roam_scan_hdl(void *ctx); +void rtw_wnm_process_btm_req(_adapter *padapter, u8* pframe, u32 frame_len); +void rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb); +void rtw_wnm_reset_btm_state(_adapter *padapter); +void rtw_wnm_issue_action(_adapter *padapter, u8 action, u8 reason); +#endif +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) +u32 rtw_wnm_btm_candidates_survey(_adapter *padapter, u8* pframe, u32 elem_len, u8 is_preference); #endif void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res); void mlmeext_sta_del_event_callback(_adapter *padapter); @@ -1069,6 +1062,9 @@ void linked_status_chk(_adapter *padapter, u8 from_timer); void _linked_info_dump(_adapter *padapter); void survey_timer_hdl(void *ctx); +#ifdef CONFIG_RTW_REPEATER_SON +void rson_timer_hdl(void *ctx); +#endif void link_timer_hdl(void *ctx); void addba_timer_hdl(void *ctx); #ifdef CONFIG_IEEE80211W @@ -1091,6 +1087,10 @@ void reassoc_timer_hdl(_adapter *padapter); _set_timer(&(mlmeext)->link_timer, (ms)); \ } while (0) +bool rtw_is_basic_rate_cck(u8 rate); +bool rtw_is_basic_rate_ofdm(u8 rate); +bool rtw_is_basic_rate_mix(u8 rate); + extern int cckrates_included(unsigned char *rate, int ratelen); extern int cckratesonly_included(unsigned char *rate, int ratelen); @@ -1101,7 +1101,7 @@ extern void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext); extern void adaptive_early_32k(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); extern u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer); - +void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame); void rtw_join_done_chk_ch(_adapter *padapter, int join_res); int rtw_chk_start_clnt_join(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset); @@ -1117,6 +1117,8 @@ struct cmd_hdl { u8(*h2cfuns)(struct _ADAPTER *padapter, u8 *pbuf); }; +void rtw_leave_opch(_adapter *adapter); +void rtw_back_opch(_adapter *adapter); u8 read_macreg_hdl(_adapter *padapter, u8 *pbuf); u8 write_macreg_hdl(_adapter *padapter, u8 *pbuf); @@ -1146,7 +1148,7 @@ u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf); u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf); u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf); u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf); -u8 set_ch_hdl(_adapter *padapter, u8 *pbuf); +u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf); u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf); u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf); u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf); /* Kurt: Handling DFS channel switch announcement ie. */ @@ -1206,7 +1208,7 @@ struct cmd_hdl wlancmds[] = { GEN_MLME_EXT_HANDLER(0, NULL) GEN_MLME_EXT_HANDLER(0, NULL) GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl) - GEN_MLME_EXT_HANDLER(sizeof(struct set_ch_parm), set_ch_hdl) /* 46 */ + GEN_MLME_EXT_HANDLER(sizeof(struct set_ch_parm), rtw_set_chbw_hdl) /* 46 */ GEN_MLME_EXT_HANDLER(0, NULL) GEN_MLME_EXT_HANDLER(0, NULL) GEN_MLME_EXT_HANDLER(0, NULL) @@ -1229,6 +1231,7 @@ struct cmd_hdl wlancmds[] = { GEN_MLME_EXT_HANDLER(0, chk_bmc_sleepq_hdl) /*63*/ GEN_MLME_EXT_HANDLER(sizeof(struct RunInThread_param), run_in_thread_hdl) /*64*/ GEN_MLME_EXT_HANDLER(sizeof(struct addBaRsp_parm), add_ba_rsp_hdl) /* 65 */ + GEN_MLME_EXT_HANDLER(sizeof(struct rm_event), rm_post_event_hdl) /* 66 */ }; #endif diff --git a/include/rtw_mp.h b/include/rtw_mp.h index c645f37..2fbf74e 100644 --- a/include/rtw_mp.h +++ b/include/rtw_mp.h @@ -97,39 +97,7 @@ struct mp_tx { #define MP_MAX_LINES 1000 #define MP_MAX_LINES_BYTES 256 -#define u1Byte u8 -#define s1Byte s8 -#define u4Byte u32 -#define s4Byte s32 -#define u1Byte u8 -#define pu1Byte u8* -#define u2Byte u16 -#define pu2Byte u16* - -#define u4Byte u32 -#define pu4Byte u32* - -#define u8Byte u64 -#define pu8Byte u64* - -#define s1Byte s8 -#define ps1Byte s8* - -#define s2Byte s16 -#define ps2Byte s16* - -#define s4Byte s32 -#define ps4Byte s32* - -#define s8Byte s64 -#define ps8Byte s64* - -#define UCHAR u8 -#define USHORT u16 -#define UINT u32 -#define ULONG u32 -#define PULONG u32* typedef struct _RT_PMAC_PKT_INFO { UCHAR MCS; @@ -303,6 +271,7 @@ enum { MP_STOP, MP_RATE, MP_CHANNEL, + MP_CHL_OFFSET, MP_BANDWIDTH, MP_TXPOWER, MP_ANT_TX, @@ -337,8 +306,10 @@ enum { MP_CUSTOMER_STR, MP_PWRLMT, MP_PWRBYRATE, - MP_NULL, + BT_EFUSE_FILE, MP_SetBT, + MP_SWRFPath, + MP_NULL, #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE VENDOR_IE_SET , VENDOR_IE_GET , @@ -405,6 +376,9 @@ struct mp_priv { u8 mac_filter[ETH_ALEN]; u8 bmac_filter; + /* RF PATH Setting for WLG WLA BTG BT */ + u8 rf_path_cfg; + struct wlan_network mp_network; NDIS_802_11_MAC_ADDRESS network_macaddr; @@ -442,6 +416,7 @@ struct mp_priv { BOOLEAN bRTWSmbCfg; BOOLEAN bloopback; BOOLEAN bloadefusemap; + BOOLEAN bloadBTefusemap; MPT_CONTEXT mpt_ctx; @@ -729,7 +704,9 @@ extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask); extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val); extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr); extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val); - +#ifdef CONFIG_ANTENNA_DIVERSITY +u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain); +#endif void SetChannel(PADAPTER pAdapter); void SetBandwidth(PADAPTER pAdapter); int SetTxPower(PADAPTER pAdapter); @@ -776,6 +753,7 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart); void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); void mpt_ProSetPMacTx(PADAPTER Adapter); void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain); +void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate); u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter); ULONG mpt_ProQueryCalTxPower(PADAPTER pAdapter, u8 RfPath); void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart); @@ -845,6 +823,9 @@ int rtw_mp_rate(struct net_device *dev, int rtw_mp_channel(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); +int rtw_mp_ch_offset(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_bandwidth(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); @@ -902,6 +883,9 @@ int rtw_mp_phypara(struct net_device *dev, int rtw_mp_SetRFPath(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); +int rtw_mp_switch_rf_path(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_QueryDrv(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); @@ -926,6 +910,9 @@ int rtw_efuse_mask_file(struct net_device *dev, int rtw_efuse_file_map(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); +int rtw_bt_efuse_file_map(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_mp_SetBT(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); @@ -943,7 +930,7 @@ u8 HwRateToMPTRate(u8 rate); int rtw_mp_iqk(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); -int rtw_mp_lck(struct net_device *dev, - struct iw_request_info *info, +int rtw_mp_lck(struct net_device *dev, + struct iw_request_info *info, struct iw_point *wrqu, char *extra); #endif /* _RTW_MP_H_ */ diff --git a/include/rtw_odm.h b/include/rtw_odm.h index bcb4ea9..4ce6fe1 100644 --- a/include/rtw_odm.h +++ b/include/rtw_odm.h @@ -37,12 +37,23 @@ typedef enum _HAL_PHYDM_OPS { #define rtw_phydm_func_disable_all(adapter) \ rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0) +#ifdef CONFIG_RTW_ACS #define rtw_phydm_func_for_offchannel(adapter) \ do { \ rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \ if (rtw_odm_adaptivity_needed(adapter)) \ rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \ + if (IS_ACS_ENABLE(adapter))\ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ENV_MONITOR); \ } while (0) +#else +#define rtw_phydm_func_for_offchannel(adapter) \ + do { \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \ + if (rtw_odm_adaptivity_needed(adapter)) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \ + } while (0) +#endif #define rtw_phydm_func_clr(adapter, ability) \ rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability) @@ -62,9 +73,6 @@ static inline u32 rtw_phydm_ability_get(_adapter *adapter) void rtw_odm_init_ic_type(_adapter *adapter); -void rtw_odm_set_force_igi_lb(_adapter *adapter, u8 lb); -u8 rtw_odm_get_force_igi_lb(_adapter *adapter); - void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter); bool rtw_odm_adaptivity_needed(_adapter *adapter); diff --git a/include/rtw_p2p.h b/include/rtw_p2p.h index f5fe3c1..203886b 100644 --- a/include/rtw_p2p.h +++ b/include/rtw_p2p.h @@ -70,6 +70,7 @@ u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue); #endif /* CONFIG_P2P_PS */ #ifdef CONFIG_IOCTL_CFG80211 +u8 roch_stay_in_cur_chan(_adapter *padapter); void rtw_init_cfg80211_wifidirect_info(_adapter *padapter); int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx); #endif /* CONFIG_IOCTL_CFG80211 */ diff --git a/include/rtw_pwrctrl.h b/include/rtw_pwrctrl.h index 1d5dfe9..696ff70 100644 --- a/include/rtw_pwrctrl.h +++ b/include/rtw_pwrctrl.h @@ -40,7 +40,6 @@ #endif /* CONFIG_BT_COEXIST */ #ifdef CONFIG_WOWLAN -#ifdef CONFIG_DEFAULT_PATTERNS_EN #ifdef CONFIG_PLATFORM_ANDROID_INTEL_X86 /* TCP/ICMP/UDP multicast with specific IP addr */ #define DEFAULT_PATTERN_NUM 4 @@ -48,9 +47,6 @@ /* TCP/ICMP */ #define DEFAULT_PATTERN_NUM 3 #endif -#else - #define DEFAULT_PATTERN_NUM 0 -#endif /*CONFIG_DEFAULT_PATTERNS_EN*/ #ifdef CONFIG_WOW_PATTERN_HW_CAM /* Frame Mask Cam number for pattern match */ #define MAX_WKFM_CAM_NUM 12 @@ -175,7 +171,7 @@ __inline static void _exit_pwrlock(_pwrlock *plock) _rtw_up_sema(plock); } -#define LPS_DELAY_TIME 1*HZ /* 1 sec */ +#define LPS_DELAY_MS 1000 /* 1 sec */ #define EXE_PWR_NONE 0x01 #define EXE_PWR_IPS 0x02 @@ -307,6 +303,11 @@ struct aoac_report { u8 group_key[32]; u8 key_index; u8 security_type; + u8 wow_pattern_idx; + u8 version_info; + u8 reserved[4]; + u8 rxptk_iv[8]; + u8 rxgtk_iv[4][8]; }; struct pwrctrl_priv { @@ -322,6 +323,10 @@ struct pwrctrl_priv { u8 bcn_ant_mode; u8 dtim; +#ifdef CONFIG_WMMPS_STA + u8 wmm_smart_ps; +#endif /* CONFIG_WMMPS_STA */ + u32 alives; _workitem cpwm_event; _workitem dma_event; /*for handle un-synchronized tx dma*/ @@ -350,7 +355,7 @@ struct pwrctrl_priv { u8 ips_org_mode; u8 ips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */ uint bips_processing; - u32 ips_deny_time; /* will deny IPS when system time is smaller than this */ + systime ips_deny_time; /* will deny IPS when system time is smaller than this */ u8 pre_ips_type;/* 0: default flow, 1: carddisbale flow */ /* ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. */ @@ -367,12 +372,14 @@ struct pwrctrl_priv { u8 power_mgnt; u8 org_power_mgnt; u8 bFwCurrentInPSMode; - u32 DelayLPSLastTimeStamp; + systime DelayLPSLastTimeStamp; s32 pnp_current_pwr_state; u8 pnp_bstop_trx; - + #ifdef CONFIG_AUTOSUSPEND + int ps_flag; /* used by autosuspend */ u8 bInternalAutoSuspend; + #endif u8 bInSuspend; #ifdef CONFIG_BT_COEXIST u8 bAutoResume; @@ -386,11 +393,15 @@ struct pwrctrl_priv { u8 wowlan_p2p_mode; u8 wowlan_pno_enable; u8 wowlan_in_resume; + #ifdef CONFIG_GPIO_WAKEUP u8 is_high_active; #endif /* CONFIG_GPIO_WAKEUP */ #ifdef CONFIG_WOWLAN + bool default_patterns_en; +#ifdef CONFIG_IPV6 u8 wowlan_ns_offload_en; +#endif /*CONFIG_IPV6*/ u8 wowlan_txpause_status; u8 wowlan_pattern_idx; u64 wowlan_fw_iv; @@ -412,7 +423,6 @@ struct pwrctrl_priv { int pwr_state_check_interval; u8 pwr_state_check_cnts; - int ps_flag; /* used by autosuspend */ rt_rf_power_state rf_pwrstate;/* cur power state, only for IPS */ /* rt_rf_power_state current_rfpwrstate; */ @@ -453,6 +463,16 @@ struct pwrctrl_priv { u8 blpspg_info_up; #endif u8 current_lps_hw_port_id; + +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + systime radio_on_start_time; + systime pwr_saving_start_time; + u32 pwr_saving_time; + u32 on_time; + u32 tx_time; + u32 rx_time; +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + }; #define rtw_get_ips_mode_req(pwrctl) \ diff --git a/include/rtw_qos.h b/include/rtw_qos.h index 380120f..8e1d013 100644 --- a/include/rtw_qos.h +++ b/include/rtw_qos.h @@ -17,13 +17,50 @@ #ifndef _RTW_QOS_H_ #define _RTW_QOS_H_ +#define DRV_CFG_UAPSD_VO BIT0 +#define DRV_CFG_UAPSD_VI BIT1 +#define DRV_CFG_UAPSD_BK BIT2 +#define DRV_CFG_UAPSD_BE BIT3 +#define WMM_IE_UAPSD_VO BIT0 +#define WMM_IE_UAPSD_VI BIT1 +#define WMM_IE_UAPSD_BK BIT2 +#define WMM_IE_UAPSD_BE BIT3 + +#define WMM_TID0 BIT0 +#define WMM_TID1 BIT1 +#define WMM_TID2 BIT2 +#define WMM_TID3 BIT3 +#define WMM_TID4 BIT4 +#define WMM_TID5 BIT5 +#define WMM_TID6 BIT6 +#define WMM_TID7 BIT7 + +#define AP_SUPPORTED_UAPSD BIT7 +/* TC = Traffic Category, TID0~7 represents TC */ +#define BIT_MASK_TID_TC 0xff +/* TS = Traffic Stream, TID8~15 represents TS */ +#define BIT_MASK_TID_TS 0xff00 +#define ALL_TID_TC_SUPPORTED_UAPSD 0xff struct qos_priv { unsigned int qos_option; /* bit mask option: u-apsd, s-apsd, ts, block ack... */ +#ifdef CONFIG_WMMPS_STA + /* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */ + u8 uapsd_max_sp_len; + /* declare uapsd_tid as a bitmap for the uapsd setting of TID 0~15 */ + u16 uapsd_tid; + /* declare uapsd_tid_delivery_enabled as a bitmap for the delivery-enabled setting of TID 0~7 */ + u8 uapsd_tid_delivery_enabled; + /* declare uapsd_tid_trigger_enabled as a bitmap for the trigger-enabled setting of TID 0~7 */ + u8 uapsd_tid_trigger_enabled; + /* declare uapsd_ap_supported to record whether the connected ap supports uapsd or not */ + u8 uapsd_ap_supported; +#endif /* CONFIG_WMMPS_STA */ + }; -#endif /* _RTL871X_QOS_H_ */ +#endif /* _RTL871X_QOS_H_ */ \ No newline at end of file diff --git a/include/rtw_recv.h b/include/rtw_recv.h index 750dff1..d77557d 100644 --- a/include/rtw_recv.h +++ b/include/rtw_recv.h @@ -15,6 +15,10 @@ #ifndef _RTW_RECV_H_ #define _RTW_RECV_H_ +#define RTW_RX_MSDU_ACT_NONE 0 +#define RTW_RX_MSDU_ACT_INDICATE BIT0 +#define RTW_RX_MSDU_ACT_FORWARD BIT1 + #ifdef PLATFORM_OS_XP #ifdef CONFIG_SDIO_HCI #define NR_RECVBUFF 1024/* 512 */ /* 128 */ @@ -51,6 +55,13 @@ #endif #endif +#if defined(CONFIG_RTL8821C) && defined(CONFIG_SDIO_HCI) && defined(CONFIG_RECV_THREAD_MODE) + #ifdef NR_RECVBUFF + #undef NR_RECVBUFF + #define NR_RECVBUFF (32) + #endif +#endif + #define NR_RECVFRAME 256 #define RXFRAME_ALIGN 8 @@ -91,6 +102,7 @@ static u8 rtw_bridge_tunnel_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 }; /* for Rx reordering buffer control */ struct recv_reorder_ctrl { _adapter *padapter; + u8 tid; u8 enable; u16 indicate_seq;/* =wstart_b, init_value=0xffff */ u16 wend_b; @@ -103,6 +115,8 @@ struct recv_reorder_ctrl { struct stainfo_rxcache { u16 tid_rxseq[16]; + u8 iv[16][8]; + u8 last_tid; #if 0 unsigned short tid0_rxseq; unsigned short tid1_rxseq; @@ -137,69 +151,6 @@ struct signal_stat { u32 total_num; /* num of valid elements */ u32 total_val; /* sum of valid elements */ }; -#if 0 -typedef struct _ODM_Phy_Status_Info_ { - /* */ - /* Be care, if you want to add any element please insert between */ - /* RxPWDBAll & SignalStrength. */ - /* */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - u4Byte RxPWDBAll; -#else - u1Byte RxPWDBAll; -#endif - - u1Byte SignalQuality; /* in 0-100 index. */ - s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */ - u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ - - u1Byte RxMIMOSignalStrength[4];/* in 0~100 index */ - - u2Byte Cfo_short[4]; /* per-path's Cfo_short */ - u2Byte Cfo_tail[4]; /* per-path's Cfo_tail */ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - s1Byte RxPower; /* in dBm Translate from PWdB */ - s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ - u1Byte BTRxRSSIPercentage; - u1Byte SignalStrength; /* in 0-100 index. */ - - u1Byte RxPwr[4]; /* per-path's pwdb */ -#endif - u1Byte RxSNR[4]; /* per-path's SNR */ - u1Byte BandWidth; - u1Byte btCoexPwrAdjust; -} ODM_PHY_INFO_T, *PODM_PHY_INFO_T; -#endif - -struct phy_info { - u8 RxPWDBAll; - u8 SignalQuality; /* in 0-100 index. */ - s8 RxMIMOSignalQuality[4]; /* per-path's EVM */ - u8 RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ - u8 RxMIMOSignalStrength[4]; /* in 0~100 index */ - s16 Cfo_short[4]; /* per-path's Cfo_short */ - s16 Cfo_tail[4]; /* per-path's Cfo_tail */ - s8 RxPower; /* in dBm Translate from PWdB */ - s8 RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ - u8 BTRxRSSIPercentage; - u8 SignalStrength; /* in 0-100 index. */ - s8 RxPwr[4]; /* per-path's pwdb */ - s8 RxSNR[4]; -#if ((RTL8822B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - u8 RxCount:2; - u8 BandWidth:2; - u8 rxsc:4; -#else - u8 BandWidth; -#endif - u8 btCoexPwrAdjust; -#if ((RTL8822B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - u8 channel; /* channel number---*/ - BOOLEAN bMuPacket; /* is MU packet or not---*/ - BOOLEAN bBeamformed; -#endif -}; struct rx_raw_rssi { u8 data_rate; @@ -214,6 +165,8 @@ struct rx_raw_rssi { }; +#include "cmn_info/rtw_sta_info.h" + struct rx_pkt_attrib { u16 pkt_len; u8 physt; @@ -245,14 +198,15 @@ struct rx_pkt_attrib { u8 ta[ETH_ALEN]; u8 ra[ETH_ALEN]; u8 bssid[ETH_ALEN]; +#ifdef CONFIG_RTW_MESH + u8 msa[ETH_ALEN]; /* mesh sa */ + u8 mda[ETH_ALEN]; /* mesh da */ + u8 mesh_ctrl_present; + u8 mesh_ctrl_len; /* length of mesh control field */ +#endif u8 ack_policy; -/* #ifdef CONFIG_TCP_CSUM_OFFLOAD_RX */ - u8 tcpchk_valid; /* 0: invalid, 1: valid */ - u8 ip_chkrpt; /* 0: incorrect, 1: correct */ - u8 tcp_chkrpt; /* 0: incorrect, 1: correct */ -/* #endif */ u8 key_index; u8 data_rate; @@ -264,17 +218,16 @@ struct rx_pkt_attrib { u8 pkt_rpt_type; u32 tsfl; u32 MacIDValidEntry[2]; /* 64 bits present 64 entry. */ - -#if 0 - u8 signal_qual; - s8 rx_mimo_signal_qual[2]; - u8 signal_strength; - u32 RxPWDBAll; - s32 RecvSignalPower; -#endif - struct phy_info phy_info; + u8 ppdu_cnt; + u32 free_cnt; /* free run counter */ + struct phydm_phyinfo_struct phy_info; }; +#ifdef CONFIG_RTW_MESH +#define RATTRIB_GET_MCTRL_LEN(rattrib) ((rattrib)->mesh_ctrl_len) +#else +#define RATTRIB_GET_MCTRL_LEN(rattrib) 0 +#endif /* These definition is used for Rx packet reordering. */ #define SN_LESS(a, b) (((a-b) & 0x800) != 0) @@ -362,6 +315,11 @@ accesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(pas using enter_critical section to protect */ + +#ifndef DBG_RX_BH_TRACKING +#define DBG_RX_BH_TRACKING 0 +#endif + struct recv_priv { _lock lock; @@ -381,6 +339,17 @@ struct recv_priv { uint free_recvframe_cnt; + #if DBG_RX_BH_TRACKING + u32 rx_bh_stage; + u32 rx_bh_buf_dq_cnt; + void *rx_bh_lbuf; + void *rx_bh_cbuf; + void *rx_bh_cbuf_data; + u32 rx_bh_cbuf_dlen; + u32 rx_bh_cbuf_pos; + void *rx_bh_cframe; + #endif + _adapter *adapter; #ifdef PLATFORM_WINDOWS @@ -401,6 +370,14 @@ struct recv_priv { u64 rx_pkts; u64 rx_drop; + u64 dbg_rx_drop_count; + u64 dbg_rx_ampdu_drop_count; + u64 dbg_rx_ampdu_forced_indicate_count; + u64 dbg_rx_ampdu_loss_count; + u64 dbg_rx_dup_mgt_frame_drop_count; + u64 dbg_rx_ampdu_window_shift_cnt; + u64 dbg_rx_conflic_mac_addr_cnt; + uint rx_icv_err; uint rx_largepacket_crcerr; uint rx_smallpacket_crcerr; @@ -466,7 +443,6 @@ struct recv_priv { s8 rssi; /* translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); */ struct rx_raw_rssi raw_rssi_info; /* s8 rxpwdb; */ - s16 noise; /* int RxSNRdB[2]; */ /* s8 RxRssi[2]; */ /* int FalseAlmCnt_all; */ @@ -487,6 +463,30 @@ struct recv_priv { BOOLEAN store_law_data_flag; }; +#define RX_BH_STG_UNKNOWN 0 +#define RX_BH_STG_HDL_ENTER 1 +#define RX_BH_STG_HDL_EXIT 2 +#define RX_BH_STG_NEW_BUF 3 +#define RX_BH_STG_NEW_FRAME 4 +#define RX_BH_STG_NORMAL_RX 5 +#define RX_BH_STG_NORMAL_RX_END 6 +#define RX_BH_STG_C2H 7 +#define RX_BH_STG_C2H_END 8 + +#if DBG_RX_BH_TRACKING +void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s); +void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen); +void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos); +void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame); +void dump_rx_bh_tk(void *sel, struct recv_priv *recv); +#else +#define rx_bh_tk_set_stage(recv, s) do {} while (0) +#define rx_bh_tk_set_buf(recv, buf, data, dlen) do {} while (0) +#define rx_bh_tk_set_buf_pos(recv, pos) do {} while (0) +#define rx_bh_tk_set_frame(recv, frame) do {} while (0) +#define dump_rx_bh_tk(sel, recv) do {} while (0) +#endif + #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS #define rtw_set_signal_stat_timer(recvpriv) _set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval) #endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ @@ -500,6 +500,7 @@ struct sta_recv_priv { _queue defrag_q; /* keeping the fragment frame until defrag */ struct stainfo_rxcache rxcache; + u16 bmc_tid_rxseq[16]; /* uint sta_rx_bytes; */ /* uint sta_rx_pkts; */ @@ -547,12 +548,11 @@ struct recv_buf { #endif -#ifdef PLATFORM_LINUX - _pkt *pskb; -#endif -#ifdef PLATFORM_FREEBSD /* skb solution */ +#if defined(PLATFORM_LINUX) + _pkt *pskb; +#elif defined(PLATFORM_FREEBSD) /* skb solution */ struct sk_buff *pskb; -#endif /* PLATFORM_FREEBSD */ /* skb solution */ +#endif }; @@ -573,13 +573,7 @@ struct recv_buf { */ struct recv_frame_hdr { _list list; -#ifndef CONFIG_BSD_RX_USE_MBUF - struct sk_buff *pkt; - struct sk_buff *pkt_newalloc; -#else /* CONFIG_BSD_RX_USE_MBUF */ - _pkt *pkt; - _pkt *pkt_newalloc; -#endif /* CONFIG_BSD_RX_USE_MBUF */ + _pkt *pkt; _adapter *adapter; @@ -653,7 +647,9 @@ sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue); sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue); struct recv_buf *rtw_dequeue_recvbuf(_queue *queue); +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) void rtw_reordering_ctrl_timeout_handler(void *pcontext); +#endif void rx_query_phy_status(union recv_frame *rframe, u8 *phy_stat); int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index); @@ -880,13 +876,14 @@ __inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex) return SignalPower; } - struct sta_info; extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv); extern void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame); +u8 adapter_allow_bmc_data_rx(_adapter *adapter); s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status); +void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta); #endif diff --git a/include/rtw_rf.h b/include/rtw_rf.h index 113adf3..e4c80b9 100644 --- a/include/rtw_rf.h +++ b/include/rtw_rf.h @@ -79,13 +79,6 @@ enum _REG_PREAMBLE_MODE { PREAMBLE_SHORT = 3, }; -typedef enum _RF_PATH { - RF_PATH_A = 0, - RF_PATH_B = 1, - RF_PATH_C = 2, - RF_PATH_D = 3, -} RF_PATH, *PRF_PATH; - #define rf_path_char(path) (((path) >= RF_PATH_MAX) ? 'X' : 'A' + (path)) /* Bandwidth Offset */ @@ -106,22 +99,12 @@ extern const char *const _band_str[]; extern const u8 _band_to_band_cap[]; #define band_to_band_cap(band) (((band) >= BAND_MAX) ? _band_to_band_cap[BAND_MAX] : _band_to_band_cap[(band)]) -/* Represent Channel Width in HT Capabilities - * */ -typedef enum _CHANNEL_WIDTH { - CHANNEL_WIDTH_20 = 0, - CHANNEL_WIDTH_40 = 1, - CHANNEL_WIDTH_80 = 2, - CHANNEL_WIDTH_160 = 3, - CHANNEL_WIDTH_80_80 = 4, - CHANNEL_WIDTH_MAX = 5, -} CHANNEL_WIDTH, *PCHANNEL_WIDTH; extern const char *const _ch_width_str[]; -#define ch_width_str(bw) (((bw) >= CHANNEL_WIDTH_MAX) ? _ch_width_str[CHANNEL_WIDTH_MAX] : _ch_width_str[(bw)]) +#define ch_width_str(bw) (((bw) < CHANNEL_WIDTH_MAX) ? _ch_width_str[(bw)] : "CHANNEL_WIDTH_MAX") extern const u8 _ch_width_to_bw_cap[]; -#define ch_width_to_bw_cap(bw) (((bw) >= CHANNEL_WIDTH_MAX) ? _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] : _ch_width_to_bw_cap[(bw)]) +#define ch_width_to_bw_cap(bw) (((bw) < CHANNEL_WIDTH_MAX) ? _ch_width_to_bw_cap[(bw)] : 0) /* * Represent Extention Channel Offset in HT Capabilities @@ -154,21 +137,7 @@ typedef enum _PROTECTION_MODE { PROTECTION_MODE_FORCE_DISABLE = 2, } PROTECTION_MODE, *PPROTECTION_MODE; -typedef enum _RT_RF_TYPE_DEFINITION { - RF_1T2R = 0, - RF_2T4R = 1, - RF_2T2R = 2, - RF_1T1R = 3, - RF_2T2R_GREEN = 4, - RF_2T3R = 5, - RF_3T3R = 6, - RF_3T4R = 7, - RF_4T4R = 8, - - RF_TYPE_AUTO, -} RT_RF_TYPE_DEF_E; - -#define RF_TYPE_VALID(rf_type) (rf_type < RF_TYPE_AUTO) +#define RF_TYPE_VALID(rf_type) (rf_type < RF_TYPE_MAX) extern const u8 _rf_type_to_rf_tx_cnt[]; #define rf_type_to_rf_tx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_tx_cnt[rf_type] : 0) @@ -180,16 +149,17 @@ int rtw_ch2freq(int chan); int rtw_freq2ch(int freq); bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo); -#define RTW_MODULE_RTL8821AE_HMC_M2 BIT0 /* RTL8821AE(HMC + M.2) */ -#define RTW_MODULE_RTL8821AU BIT1 /* RTL8821AU */ -#define RTW_MODULE_RTL8812AENF_NGFF BIT2 /* RTL8812AENF(8812AE+8761)_NGFF */ -#define RTW_MODULE_RTL8812AEBT_HMC BIT3 /* RTL8812AEBT(8812AE+8761)_HMC */ -#define RTW_MODULE_RTL8188EE_HMC_M2 BIT4 /* RTL8188EE(HMC + M.2) */ -#define RTW_MODULE_RTL8723BE_HMC_M2 BIT5 /* RTL8723BE(HMC + M.2) */ -#define RTW_MODULE_RTL8723BS_NGFF1216 BIT6 /* RTL8723BS(NGFF1216) */ -#define RTW_MODULE_RTL8192EEBT_HMC_M2 BIT7 /* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */ -#define RTW_MODULE_RTL8723DE_NGFF1630 BIT8 /* RTL8723DE(NGFF1630) */ -#define RTW_MODULE_RTL8822BE BIT9 /* RTL8822BE */ +#define RTW_MODULE_RTL8821AE_HMC_M2 BIT0 /* RTL8821AE(HMC + M.2) */ +#define RTW_MODULE_RTL8821AU BIT1 /* RTL8821AU */ +#define RTW_MODULE_RTL8812AENF_NGFF BIT2 /* RTL8812AENF(8812AE+8761)_NGFF */ +#define RTW_MODULE_RTL8812AEBT_HMC BIT3 /* RTL8812AEBT(8812AE+8761)_HMC */ +#define RTW_MODULE_RTL8188EE_HMC_M2 BIT4 /* RTL8188EE(HMC + M.2) */ +#define RTW_MODULE_RTL8723BE_HMC_M2 BIT5 /* RTL8723BE(HMC + M.2) */ +#define RTW_MODULE_RTL8723BS_NGFF1216 BIT6 /* RTL8723BS(NGFF1216) */ +#define RTW_MODULE_RTL8192EEBT_HMC_M2 BIT7 /* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */ +#define RTW_MODULE_RTL8723DE_NGFF1630 BIT8 /* RTL8723DE(NGFF1630) */ +#define RTW_MODULE_RTL8822BE BIT9 /* RTL8822BE */ +#define RTW_MODULE_RTL8821CE BIT10 /* RTL8821CE */ #define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF) @@ -227,7 +197,9 @@ typedef enum _REGULATION_TXPWR_LMT { TXPWR_LMT_ETSI = 3, TXPWR_LMT_IC = 4, TXPWR_LMT_KCC = 5, - TXPWR_LMT_WW = 6, /* smallest of all available limit, keep last */ + TXPWR_LMT_ACMA = 6, + TXPWR_LMT_CHILE = 7, + TXPWR_LMT_WW = 8, /* smallest of all available limit, keep last */ } REGULATION_TXPWR_LMT; extern const char *const _regd_str[]; @@ -277,10 +249,22 @@ int rtw_ch_to_bb_gain_sel(int ch); void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset); void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch); -u8 rtw_is_5g_band1(u8 ch); -u8 rtw_is_5g_band2(u8 ch); -u8 rtw_is_5g_band3(u8 ch); -u8 rtw_is_5g_band4(u8 ch); +/* only check channel ranges */ +#define rtw_is_2g_ch(ch) (ch >= 1 && ch <= 14) +#define rtw_is_5g_ch(ch) ((ch) >= 36 && (ch) <= 177) +#define rtw_is_same_band(a, b) \ + ((rtw_is_2g_ch(a) && rtw_is_2g_ch(b)) \ + || (rtw_is_5g_ch(a) && rtw_is_5g_ch(b))) + +#define rtw_is_5g_band1(ch) ((ch) >= 36 && (ch) <= 48) +#define rtw_is_5g_band2(ch) ((ch) >= 52 && (ch) <= 64) +#define rtw_is_5g_band3(ch) ((ch) >= 100 && (ch) <= 144) +#define rtw_is_5g_band4(ch) ((ch) >= 149 && (ch) <= 177) +#define rtw_is_same_5g_band(a, b) \ + ((rtw_is_5g_band1(a) && rtw_is_5g_band1(b)) \ + || (rtw_is_5g_band2(a) && rtw_is_5g_band2(b)) \ + || (rtw_is_5g_band3(a) && rtw_is_5g_band3(b)) \ + || (rtw_is_5g_band4(a) && rtw_is_5g_band4(b))) u8 rtw_is_dfs_range(u32 hi, u32 lo); u8 rtw_is_dfs_ch(u8 ch); diff --git a/include/rtw_security.h b/include/rtw_security.h index ca7c526..ac8432e 100644 --- a/include/rtw_security.h +++ b/include/rtw_security.h @@ -22,16 +22,18 @@ #define _TKIP_WTMIC_ 0x3 #define _AES_ 0x4 #define _WEP104_ 0x5 -#define _WEP_WPA_MIXED_ 0x07 /* WEP + WPA */ #define _SMS4_ 0x06 -#ifdef CONFIG_IEEE80211W +#define _WEP_WPA_MIXED_ 0x07 /* WEP + WPA */ #define _BIP_ 0x8 -#endif /* CONFIG_IEEE80211W */ + /* 802.11W use wrong key */ #define IEEE80211W_RIGHT_KEY 0x0 #define IEEE80211W_WRONG_KEY 0x1 #define IEEE80211W_NO_KEY 0x2 +#define CCMPH_2_PN(ch) ((ch) & 0x000000000000ffff) \ + | (((ch) & 0xffffffff00000000) >> 16) + #define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_)) const char *security_type_str(u8 value); @@ -124,23 +126,24 @@ struct security_priv { /* WEP */ u32 dot11PrivacyKeyIndex; /* this is only valid for legendary wep, 0~3 for key id. (tx key index) */ - union Keytype dot11DefKey[4]; /* this is only valid for def. key */ - u32 dot11DefKeylen[4]; - u8 dot11Def_camid[4]; + union Keytype dot11DefKey[6]; /* this is only valid for def. key */ + u32 dot11DefKeylen[6]; + u8 dot11Def_camid[6]; u8 key_mask; /* use to restore wep key after hal_init */ u32 dot118021XGrpPrivacy; /* This specify the privacy algthm. used for Grp key */ u32 dot118021XGrpKeyid; /* key id used for Grp Key ( tx key index) */ - union Keytype dot118021XGrpKey[4]; /* 802.1x Group Key, for inx0 and inx1 */ - union Keytype dot118021XGrptxmickey[4]; - union Keytype dot118021XGrprxmickey[4]; + union Keytype dot118021XGrpKey[6]; /* 802.1x Group Key, for inx0 and inx1 */ + union Keytype dot118021XGrptxmickey[6]; + union Keytype dot118021XGrprxmickey[6]; union pn48 dot11Grptxpn; /* PN48 used for Grp Key xmit. */ union pn48 dot11Grprxpn; /* PN48 used for Grp Key recv. */ + u8 iv_seq[4][8]; #ifdef CONFIG_IEEE80211W u32 dot11wBIPKeyid; /* key id used for BIP Key ( tx key index) */ union Keytype dot11wBIPKey[6]; /* BIP Key, for index4 and index5 */ - union pn48 dot11wBIPtxpn; /* PN48 used for Grp Key xmit. */ - union pn48 dot11wBIPrxpn; /* PN48 used for Grp Key recv. */ + union pn48 dot11wBIPtxpn; /* PN48 used for BIP xmit. */ + union pn48 dot11wBIPrxpn; /* PN48 used for BIP recv. */ #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_AP_MODE /* extend security capabilities for AP_MODE */ @@ -150,6 +153,7 @@ struct security_priv { unsigned int wpa2_group_cipher; unsigned int wpa_pairwise_cipher; unsigned int wpa2_pairwise_cipher; + u8 mfp_opt; #endif #ifdef CONFIG_CONCURRENT_MODE u8 dot118021x_bmc_cam_id; @@ -197,10 +201,10 @@ struct security_priv { /* for tkip countermeasure */ - u32 last_mic_err_time; + systime last_mic_err_time; u8 btkip_countermeasure; u8 btkip_wait_report; - u32 btkip_countermeasure_time; + systime btkip_countermeasure_time; /* --------------------------------------------------------------------------- */ /* For WPA2 Pre-Authentication. */ @@ -239,6 +243,12 @@ struct security_priv { #endif /* DBG_SW_SEC_CNT */ }; +#ifdef CONFIG_IEEE80211W +#define SEC_IS_BIP_KEY_INSTALLED(sec) ((sec)->binstallBIPkey) +#else +#define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE +#endif + struct sha256_state { u64 length; u32 state[8], curlen; @@ -400,11 +410,6 @@ static inline u32 rotr(u32 val, int bits) (a)[7] = (u8) (((u64) (val)) & 0xff); \ } while (0) -/* ===== start - public domain SHA256 implementation ===== */ - -/* This is based on SHA256 implementation in LibTomCrypt that was released into - * public domain by Tom St Denis. */ - /* the K array */ static const unsigned long K[64] = { 0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL, @@ -439,8 +444,14 @@ static const unsigned long K[64] = { #define MIN(x, y) (((x) < (y)) ? (x) : (y)) #endif #ifdef CONFIG_IEEE80211W -int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac); +int omac1_aes_128(const u8 *key, const u8 *data, size_t data_len, u8 *mac); #endif /* CONFIG_IEEE80211W */ +#ifdef CONFIG_RTW_MESH_AEK +int aes_siv_encrypt(const u8 *key, const u8 *pw, size_t pwlen + , size_t num_elem, const u8 *addr[], const size_t *len, u8 *out); +int aes_siv_decrypt(const u8 *key, const u8 *iv_crypt, size_t iv_c_len + , size_t num_elem, const u8 *addr[], const size_t *len, u8 *out); +#endif void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key); void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b); void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nBytes); @@ -462,8 +473,9 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe); u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe); void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe); #ifdef CONFIG_IEEE80211W -u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe); -#endif /* CONFIG_IEEE80211W */ +u32 rtw_BIP_verify(_adapter *padapter, u8 *whdr_pos, sint flen + , const u8 *key, u16 id, u64* ipn); +#endif #ifdef CONFIG_TDLS void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta); int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq, diff --git a/include/rtw_sreset.h b/include/rtw_sreset.h index edf3763..1fd999a 100644 --- a/include/rtw_sreset.h +++ b/include/rtw_sreset.h @@ -21,16 +21,27 @@ enum { SRESET_TGP_NULL = 0, SRESET_TGP_XMIT_STATUS = 1, SRESET_TGP_LINK_STATUS = 2, + SRESET_TGP_INFO = 99, }; struct sreset_priv { _mutex silentreset_mutex; u8 silent_reset_inprogress; u8 Wifi_Error_Status; - unsigned long last_tx_time; - unsigned long last_tx_complete_time; + systime last_tx_time; + systime last_tx_complete_time; s32 dbg_trigger_point; + u64 self_dect_tx_cnt; + u64 self_dect_rx_cnt; + u64 self_dect_fw_cnt; + u64 tx_dma_status_cnt; + u64 rx_dma_status_cnt; + u8 rx_cnt; + u8 self_dect_fw; + u8 self_dect_case; + u16 last_mac_rxff_ptr; + u8 dbg_sreset_ctrl; }; diff --git a/include/rtw_tdls.h b/include/rtw_tdls.h index 841fd58..5c23e4e 100644 --- a/include/rtw_tdls.h +++ b/include/rtw_tdls.h @@ -58,13 +58,23 @@ enum TDLS_CH_SW_CHNL { TDLS_CH_SW_OFF_CHNL }; +#define TDLS_MIC_CTRL_LEN 2 +#define TDLS_FTIE_DATA_LEN (TDLS_MIC_CTRL_LEN + TDLS_MIC_LEN + \ + WPA_NONCE_LEN + WPA_NONCE_LEN) struct wpa_tdls_ftie { u8 ie_type; /* FTIE */ u8 ie_len; - u8 mic_ctrl[2]; - u8 mic[TDLS_MIC_LEN]; - u8 Anonce[WPA_NONCE_LEN]; /* Responder Nonce in TDLS */ - u8 Snonce[WPA_NONCE_LEN]; /* Initiator Nonce in TDLS */ + union { + struct { + u8 mic_ctrl[TDLS_MIC_CTRL_LEN]; + u8 mic[TDLS_MIC_LEN]; + u8 Anonce[WPA_NONCE_LEN]; /* Responder Nonce in TDLS */ + u8 Snonce[WPA_NONCE_LEN]; /* Initiator Nonce in TDLS */ + }; + struct { + u8 data[TDLS_FTIE_DATA_LEN]; + }; + }; /* followed by optional elements */ } ; @@ -98,18 +108,26 @@ static u8 TDLS_SRC[] = { 0x01, 0x01, 0x02, 0x03, 0x04, 0x0c, 0x16, 0x17, 0x18, 0 int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len); int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len); +void rtw_set_tdls_enable(_adapter *padapter, u8 enable); +u8 rtw_is_tdls_enabled(_adapter *padapter); +u8 rtw_is_tdls_sta_existed(_adapter *padapter); u8 rtw_tdls_is_setup_allowed(_adapter *padapter); #ifdef CONFIG_TDLS_CH_SW u8 rtw_tdls_is_chsw_allowed(_adapter *padapter); #endif +void rtw_tdls_set_link_established(_adapter *adapter, bool en); void rtw_reset_tdls_info(_adapter *padapter); int rtw_init_tdls_info(_adapter *padapter); void rtw_free_tdls_info(struct tdls_info *ptdlsinfo); +void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd); +void rtw_enable_tdls_func(_adapter *padapter); +void rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd); int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta); -void rtw_free_tdls_timer(struct sta_info *psta); -void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta); +void rtw_cancel_tdls_timer(struct sta_info *psta); +void rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta); +void rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd); #ifdef CONFIG_TDLS_CH_SW void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable); @@ -135,31 +153,30 @@ int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta); int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack); #endif sint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame); -sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame); -int On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame); -int On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame); +sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); +int On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); +int On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); int On_TDLS_Dis_Req(_adapter *adapter, union recv_frame *precv_frame); -int On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame); -int On_TDLS_Peer_Traffic_Indication(_adapter *adapter, union recv_frame *precv_frame); -int On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame); +int On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); +int On_TDLS_Peer_Traffic_Indication(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); +int On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); #ifdef CONFIG_TDLS_CH_SW -sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame); -sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame); -void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); -void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); +sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); +void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); +void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); #endif -void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); -void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); -void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); -void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); +void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); +void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); +void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); void rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, u8 privacy); -void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); -void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); +void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); void rtw_build_tunneled_probe_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe); void rtw_build_tunneled_probe_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe); -u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta); int rtw_tdls_is_driver_setup(_adapter *padapter); void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta); const char *rtw_tdls_action_txt(enum TDLS_ACTION_FIELD action); diff --git a/include/rtw_version.h b/include/rtw_version.h index ab5dcbd..7f11717 100644 --- a/include/rtw_version.h +++ b/include/rtw_version.h @@ -1,2 +1,2 @@ -#define DRIVERVERSION "v5.2.4_22552.20170531_COEX20170518-4444" -#define BTCOEXVERSION "COEX20170518-4444" +#define DRIVERVERSION "v5.3.1_27678.20180430_COEX20180427-5959" +#define BTCOEXVERSION "COEX20180427-5959" diff --git a/include/rtw_vht.h b/include/rtw_vht.h index f316c85..bad14fe 100644 --- a/include/rtw_vht.h +++ b/include/rtw_vht.h @@ -15,6 +15,9 @@ #ifndef _RTW_VHT_H_ #define _RTW_VHT_H_ +#define VHT_CAP_IE_LEN 12 +#define VHT_OP_IE_LEN 5 + #define LDPC_VHT_ENABLE_RX BIT0 #define LDPC_VHT_ENABLE_TX BIT1 #define LDPC_VHT_TEST_TX_ENABLE BIT2 @@ -25,15 +28,6 @@ #define STBC_VHT_TEST_TX_ENABLE BIT2 #define STBC_VHT_CAP_TX BIT3 -#define BEAMFORMING_VHT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */ -#define BEAMFORMING_VHT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */ -#define BEAMFORMING_VHT_MU_MIMO_AP_ENABLE BIT2 /*Declare our NIC support MU-MIMO AP mode*/ -#define BEAMFORMING_VHT_MU_MIMO_STA_ENABLE BIT3 /*Declare our NIC support MU-MIMO STA mode*/ -#define BEAMFORMING_VHT_BEAMFORMER_TEST BIT4 /*Transmiting Beamforming no matter the target supports it or not*/ -#define BEAMFORMING_VHT_BEAMFORMER_STS_CAP (BIT8 | BIT9 | BIT10) /*Asoc rsp cap*/ -#define BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM (BIT12 | BIT13 | BIT14) /*Asoc rsp cap*/ - - /* VHT capability info */ #define SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) #define SET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val) @@ -102,6 +96,25 @@ #define SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+7, 6, 1, _val) #define GET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+7, 6, 1) +#define VHT_MAX_MPDU_LEN_MAX 3 +extern const u16 _vht_max_mpdu_len[]; +#define vht_max_mpdu_len(val) (((val) >= VHT_MAX_MPDU_LEN_MAX) ? _vht_max_mpdu_len[VHT_MAX_MPDU_LEN_MAX] : _vht_max_mpdu_len[(val)]) + +#define VHT_SUP_CH_WIDTH_SET_MAX 3 +extern const u8 _vht_sup_ch_width_set_to_bw_cap[]; +#define vht_sup_ch_width_set_to_bw_cap(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_to_bw_cap[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_to_bw_cap[(set)]) +extern const char *const _vht_sup_ch_width_set_str[]; +#define vht_sup_ch_width_set_str(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_str[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_str[(set)]) + +#define VHT_MAX_AMPDU_LEN(f) ((1 << (13 + f)) - 1) +void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len); + +#define VHT_OP_CH_WIDTH_MAX 4 +extern const char *const _vht_op_ch_width_str[]; +#define vht_op_ch_width_str(ch_width) (((ch_width) >= VHT_OP_CH_WIDTH_MAX) ? _vht_op_ch_width_str[VHT_OP_CH_WIDTH_MAX] : _vht_op_ch_width_str[(ch_width)]) + +void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len); + struct vht_priv { u8 vht_option; @@ -112,11 +125,15 @@ struct vht_priv { u8 sgi_80m;/* short GI */ u8 ampdu_len; - u8 vht_op_mode_notify; u8 vht_highest_rate; u8 vht_mcs_map[2]; - u8 vht_cap[32]; + u8 op_present:1; /* vht_op is present */ + u8 notify_present:1; /* vht_op_mode_notify is present */ + + u8 vht_cap[32]; + u8 vht_op[VHT_OP_IE_LEN]; + u8 vht_op_mode_notify; }; u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map); @@ -135,5 +152,7 @@ u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_le void VHTOnAssocRsp(_adapter *padapter); u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map); void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map); - +void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pcur_network); +void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pcur_network); +void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len); #endif /* _RTW_VHT_H_ */ diff --git a/include/rtw_wapi.h b/include/rtw_wapi.h index 92d68d6..512bb7f 100644 --- a/include/rtw_wapi.h +++ b/include/rtw_wapi.h @@ -193,7 +193,7 @@ u8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data); void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame); -u8 rtw_wapi_check_for_drop(_adapter *padapter, union recv_frame *precv_frame); +u8 rtw_wapi_check_for_drop(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_ops); void rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib); @@ -225,4 +225,6 @@ u8 WapiIncreasePN(u8 *PN, u8 AddCount); bool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA); +void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param); + #endif diff --git a/include/rtw_xmit.h b/include/rtw_xmit.h index b89d5aa..f612888 100644 --- a/include/rtw_xmit.h +++ b/include/rtw_xmit.h @@ -84,7 +84,7 @@ #endif #ifdef CONFIG_RTL8812A - #define MAX_CMDBUF_SZ (512 * 17) + #define MAX_CMDBUF_SZ (512 * 18) #elif defined(CONFIG_RTL8723D) && defined(CONFIG_LPS_POFF) #define MAX_CMDBUF_SZ (128*70) /*(8960)*/ #else @@ -119,16 +119,17 @@ #define WEP_IV(pattrib_iv, dot11txpn, keyidx)\ do {\ + dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val + 1);\ pattrib_iv[0] = dot11txpn._byte_.TSC0;\ pattrib_iv[1] = dot11txpn._byte_.TSC1;\ pattrib_iv[2] = dot11txpn._byte_.TSC2;\ pattrib_iv[3] = ((keyidx & 0x3)<<6);\ - dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val+1);\ } while (0) #define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\ do {\ + dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\ pattrib_iv[0] = dot11txpn._byte_.TSC1;\ pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\ pattrib_iv[2] = dot11txpn._byte_.TSC0;\ @@ -137,11 +138,11 @@ pattrib_iv[5] = dot11txpn._byte_.TSC3;\ pattrib_iv[6] = dot11txpn._byte_.TSC4;\ pattrib_iv[7] = dot11txpn._byte_.TSC5;\ - dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\ } while (0) #define AES_IV(pattrib_iv, dot11txpn, keyidx)\ do {\ + dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\ pattrib_iv[0] = dot11txpn._byte_.TSC0;\ pattrib_iv[1] = dot11txpn._byte_.TSC1;\ pattrib_iv[2] = 0;\ @@ -150,7 +151,6 @@ pattrib_iv[5] = dot11txpn._byte_.TSC3;\ pattrib_iv[6] = dot11txpn._byte_.TSC4;\ pattrib_iv[7] = dot11txpn._byte_.TSC5;\ - dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\ } while (0) /* Check if AMPDU Tx is supported or not. If it is supported, @@ -319,6 +319,21 @@ struct rtw_tx_ring { u16 hw_rp_cache; #endif }; + +#ifdef DBG_TXBD_DESC_DUMP + +#define TX_BAK_FRMAE_CNT 10 +#define TX_BAK_DESC_LEN 48 /* byte */ +#define TX_BAK_DATA_LEN 30 /* byte */ + +struct rtw_tx_desc_backup { + int tx_bak_rp; + int tx_bak_wp; + u8 tx_bak_desc[TX_BAK_DESC_LEN]; + u8 tx_bak_data_hdr[TX_BAK_DATA_LEN]; + u8 tx_desc_size; +}; +#endif #endif struct hw_xmit { @@ -410,6 +425,17 @@ struct pkt_attrib { u8 src[ETH_ALEN]; u8 ta[ETH_ALEN]; u8 ra[ETH_ALEN]; +#ifdef CONFIG_RTW_MESH + u8 mda[ETH_ALEN]; /* mesh da */ + u8 msa[ETH_ALEN]; /* mesh sa */ + u8 meshctrl_len; /* Length of Mesh Control field */ + u8 mesh_frame_mode; + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + u8 mb2u; + #endif + u8 mfwd_ttl; + u32 mseq; +#endif u8 key_idx; u8 qos_en; u8 ht_en; @@ -433,6 +459,10 @@ struct pkt_attrib { u8 mbssid; u8 ldpc; u8 stbc; +#ifdef CONFIG_WMMPS_STA + u8 trigger_frame; +#endif /* CONFIG_WMMPS_STA */ + struct sta_info *psta; #ifdef CONFIG_TCP_CSUM_OFFLOAD_TX u8 hw_tcp_csum; @@ -468,6 +498,12 @@ struct pkt_attrib { }; #endif +#ifdef CONFIG_RTW_MESH +#define XATTRIB_GET_MCTRL_LEN(xattrib) ((xattrib)->meshctrl_len) +#else +#define XATTRIB_GET_MCTRL_LEN(xattrib) 0 +#endif + #ifdef CONFIG_TX_AMSDU enum { RTW_AMSDU_TIMER_UNSET = 0, @@ -500,7 +536,7 @@ enum { bool rtw_xmit_ac_blocked(_adapter *adapter); struct submit_ctx { - u32 submit_time; /* */ + systime submit_time; /* */ u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */ int status; /* status for operation */ #ifdef PLATFORM_LINUX @@ -846,6 +882,9 @@ struct xmit_priv { u32 amsdu_debug_coalesce_one; u32 amsdu_debug_coalesce_two; +#endif +#ifdef DBG_TXBD_DESC_DUMP + BOOLEAN dump_txbd_desc; #endif _lock lock_sctx; @@ -880,6 +919,11 @@ void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int s extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len); static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta); static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta); + +#ifdef CONFIG_WMMPS_STA +static void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib); +#endif /* CONFIG_WMMPS_STA */ + extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib); extern s32 rtw_put_snap(u8 *data, u16 h_proto); @@ -896,9 +940,9 @@ extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib); #define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib) extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); -#ifdef CONFIG_IEEE80211W +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); -#endif /* CONFIG_IEEE80211W */ +#endif #ifdef CONFIG_TDLS extern struct tdls_txmgmt *ptxmgmt; s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt); @@ -922,6 +966,7 @@ void rtw_free_hwxmits(_adapter *padapter); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev); #endif +s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt); s32 rtw_xmit(_adapter *padapter, _pkt **pkt); bool xmitframe_hiq_filter(struct xmit_frame *xmitframe); #if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) @@ -971,6 +1016,12 @@ extern s32 check_amsdu_tx_support(_adapter *padapter); extern struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame); #endif +#ifdef DBG_TXBD_DESC_DUMP +void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq); +void rtw_tx_desc_backup_reset(void); +u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak); +#endif + static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib); u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe); diff --git a/include/sdio_ops.h b/include/sdio_ops.h index 73eeae4..9fc20da 100644 --- a/include/sdio_ops.h +++ b/include/sdio_ops.h @@ -47,6 +47,11 @@ struct async_context { extern void sdio_set_intf_ops(_adapter *padapter, struct _io_ops *pops); void dump_sdio_card_info(void *sel, struct dvobj_priv *dvobj); +u32 sdio_init(struct dvobj_priv *dvobj); +void sdio_deinit(struct dvobj_priv *dvobj); +int sdio_alloc_irq(struct dvobj_priv *dvobj); +void sdio_free_irq(struct dvobj_priv *dvobj); + #if 0 extern void sdio_func1cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); extern void sdio_func1cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); @@ -154,4 +159,39 @@ extern void ClearInterrupt8188FSdio(PADAPTER padapter); #endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */ #endif +/** + * rtw_sdio_get_block_size() - Get block size of SDIO transfer + * @d struct dvobj_priv* + * + * The unit of return value is byte. + */ +static inline u32 rtw_sdio_get_block_size(struct dvobj_priv *d) +{ + return d->intf_data.block_transfer_len; +} + +/** + * rtw_sdio_cmd53_align_size() - Align size to one CMD53 could complete + * @d struct dvobj_priv* + * @len length to align + * + * Adjust len to align block size, and the new size could be transfered by one + * CMD53. + * If len < block size, it would keep original value, otherwise the value + * would be rounded up by block size. + * + * Return adjusted length. + */ +static inline size_t rtw_sdio_cmd53_align_size(struct dvobj_priv *d, size_t len) +{ + u32 blk_sz; + + + blk_sz = rtw_sdio_get_block_size(d); + if (len <= blk_sz) + return len; + + return _RND(len, blk_sz); +} + #endif /* !__SDIO_OPS_H__ */ diff --git a/include/sdio_ops_linux.h b/include/sdio_ops_linux.h index a4c948a..4bbd8fe 100644 --- a/include/sdio_ops_linux.h +++ b/include/sdio_ops_linux.h @@ -35,6 +35,7 @@ void _sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err); void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err); #endif /* RTW_HALMAC */ +bool rtw_is_sdio30(_adapter *adapter); /* The unit of return value is Hz */ static inline u32 rtw_sdio_get_clock(struct dvobj_priv *d) @@ -42,7 +43,6 @@ static inline u32 rtw_sdio_get_clock(struct dvobj_priv *d) return d->intf_data.clock; } -bool rtw_is_sdio30(_adapter *adapter); s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); s32 sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); s32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); diff --git a/include/sta_info.h b/include/sta_info.h index b7fb7ee..56733a1 100644 --- a/include/sta_info.h +++ b/include/sta_info.h @@ -15,6 +15,7 @@ #ifndef __STA_INFO_H_ #define __STA_INFO_H_ +#include #define IBSS_START_MAC_ID 2 #define NUM_STA MACID_NUM_SW_LIMIT @@ -28,14 +29,21 @@ #endif #define NUM_ACL 16 + +#define RTW_ACL_PERIOD_DEV 0 +#define RTW_ACL_PERIOD_BSS 1 +#define RTW_ACL_PERIOD_NUM 2 + #define RTW_ACL_MODE_DISABLED 0 #define RTW_ACL_MODE_ACCEPT_UNLESS_LISTED 1 #define RTW_ACL_MODE_DENY_UNLESS_LISTED 2 #define RTW_ACL_MODE_MAX 3 #if CONFIG_RTW_MACADDR_ACL -extern const char *const _acl_mode_str[]; -#define acl_mode_str(mode) (((mode) >= RTW_ACL_MODE_MAX) ? _acl_mode_str[RTW_ACL_MODE_DISABLED] : _acl_mode_str[(mode)]) +extern const char *const _acl_period_str[RTW_ACL_PERIOD_NUM]; +#define acl_period_str(mode) (((mode) >= RTW_ACL_PERIOD_NUM) ? "INVALID" : _acl_period_str[(mode)]) +extern const char *const _acl_mode_str[RTW_ACL_MODE_MAX]; +#define acl_mode_str(mode) (((mode) >= RTW_ACL_MODE_MAX) ? "INVALID" : _acl_mode_str[(mode)]) #endif #ifndef RTW_PRE_LINK_STA_NUM @@ -87,51 +95,57 @@ struct wlan_acl_pool { _queue acl_node_q; }; -typedef struct _RSSI_STA { - - s32 undecorated_smoothed_pwdb; - s32 undecorated_smoothed_cck; - s32 undecorated_smoothed_ofdm; - u8 ofdm_pkt; - u8 cck_pkt; - u16 cck_sum_power; - u8 is_send_rssi; - u64 packet_map; - u8 valid_bit; -} RSSI_STA, *PRSSI_STA; - struct stainfo_stats { + systime last_rx_time; u64 rx_mgnt_pkts; u64 rx_beacon_pkts; u64 rx_probereq_pkts; - u64 rx_probersp_pkts; + u64 rx_probersp_pkts; /* unicast to self */ u64 rx_probersp_bm_pkts; - u64 rx_probersp_uo_pkts; + u64 rx_probersp_uo_pkts; /* unicast to others */ u64 rx_ctrl_pkts; u64 rx_data_pkts; - u64 rx_data_last_pkts; /* For Read & Clear requirement in proc_get_rx_stat() */ - u64 rx_data_qos_pkts[TID_NUM]; + u64 rx_data_bc_pkts; + u64 rx_data_mc_pkts; + u64 rx_data_qos_pkts[TID_NUM]; /* unicast only */ + u64 last_rx_mgnt_pkts; u64 last_rx_beacon_pkts; u64 last_rx_probereq_pkts; - u64 last_rx_probersp_pkts; + u64 last_rx_probersp_pkts; /* unicast to self */ u64 last_rx_probersp_bm_pkts; - u64 last_rx_probersp_uo_pkts; + u64 last_rx_probersp_uo_pkts; /* unicast to others */ u64 last_rx_ctrl_pkts; u64 last_rx_data_pkts; - u64 last_rx_data_qos_pkts[TID_NUM]; + u64 last_rx_data_bc_pkts; + u64 last_rx_data_mc_pkts; + u64 last_rx_data_qos_pkts[TID_NUM]; /* unicast only */ + #ifdef CONFIG_TDLS u64 rx_tdls_disc_rsp_pkts; u64 last_rx_tdls_disc_rsp_pkts; #endif + u64 rx_bytes; - u64 rx_drops; + u64 rx_bc_bytes; + u64 rx_mc_bytes; + u64 last_rx_bytes; + u64 last_rx_bc_bytes; + u64 last_rx_mc_bytes; + u64 rx_drops; /* TBD */ + u16 rx_tp_mbytes; u64 tx_pkts; + u64 last_tx_pkts; + u64 tx_bytes; - u64 tx_drops; + u64 last_tx_bytes; + u64 tx_drops; /* TBD */ + u16 tx_tp_mbytes; + /* unicast only */ + u64 last_rx_data_uc_pkts; /* For Read & Clear requirement in proc_get_rx_stat() */ u32 duplicate_cnt; /* Read & Clear, in proc_get_rx_stat() */ u32 rxratecnt[128]; /* Read & Clear, in proc_get_rx_stat() */ u32 tx_ok_cnt; /* Read & Clear, in proc_get_tx_stat() */ @@ -157,7 +171,7 @@ struct session_tracker { u16 local_port; u32 remote_naddr; u16 remote_port; - u32 set_time; + systime set_time; u8 status; }; @@ -196,6 +210,7 @@ void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_regist void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id); bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto); bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); +void rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos); void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl); #ifdef CONFIG_TDLS @@ -217,6 +232,21 @@ struct sta_recv_dframe_info { }; #endif +#ifdef CONFIG_RTW_MESH +struct mesh_plink_ent; +struct rtw_ewma_err_rate { + unsigned long internal; +}; + +/* Mesh airtime link metrics parameters */ +struct rtw_atlm_param { + struct rtw_ewma_err_rate err_rate; /* Now is PACKET error rate */ + u16 data_rate; /* The unit is 100Kbps */ + u16 total_pkt; + u16 overhead; /* Channel access overhead */ +}; +#endif + struct sta_info { _lock lock; @@ -226,23 +256,26 @@ struct sta_info { /* _list sleep_list; */ /* sleep_q */ /* _list wakeup_list; */ /* wakeup_q */ _adapter *padapter; + struct cmn_sta_info cmn; struct sta_xmit_priv sta_xmitpriv; struct sta_recv_priv sta_recvpriv; #ifdef DBG_RX_DFRAME_RAW_DATA struct sta_recv_dframe_info sta_dframe_info; + struct sta_recv_dframe_info sta_dframe_info_bmc; #endif _queue sleep_q; unsigned int sleepq_len; uint state; - uint aid; - uint mac_id; uint qos_option; - u8 hwaddr[ETH_ALEN]; u16 hwseq; - u8 ra_rpt_linked; + +#ifdef CONFIG_RTW_80211K + u8 rm_en_cap[5]; + u8 rm_diag_token; +#endif /* CONFIG_RTW_80211K */ uint ieee8021x_blocked; /* 0: allowed, 1:blocked */ uint dot118021XPrivacy; /* aes, tkip... */ @@ -250,39 +283,38 @@ struct sta_info { union Keytype dot11tkiprxmickey; union Keytype dot118021x_UncstKey; union pn48 dot11txpn; /* PN48 used for Unicast xmit */ + union pn48 dot11rxpn; /* PN48 used for Unicast recv. */ +#ifdef CONFIG_RTW_MESH + /* peer's GTK, RX only */ + u8 group_privacy; + u8 gtk_bmp; + union Keytype gtk; + union pn48 gtk_pn; + #ifdef CONFIG_IEEE80211W + /* peer's IGTK, RX only */ + u8 igtk_bmp; + u8 igtk_id; + union Keytype igtk; + union pn48 igtk_pn; + #endif /* CONFIG_IEEE80211W */ +#endif /* CONFIG_RTW_MESH */ #ifdef CONFIG_GTK_OL u8 kek[RTW_KEK_LEN]; u8 kck[RTW_KCK_LEN]; u8 replay_ctr[RTW_REPLAY_CTR_LEN]; #endif /* CONFIG_GTK_OL */ #ifdef CONFIG_IEEE80211W - union pn48 dot11wtxpn; /* PN48 used for Unicast mgmt xmit. */ _timer dot11w_expire_timer; #endif /* CONFIG_IEEE80211W */ - union pn48 dot11rxpn; /* PN48 used for Unicast recv. */ - u8 bssrateset[16]; u32 bssratelen; - s32 rssi; - s32 signal_quality; u8 cts2self; u8 rtsen; - u8 raid; u8 init_rate; - u64 ra_mask; u8 wireless_mode; /* NETWORK_TYPE */ - u8 bw_mode; - - u8 ldpc; - u8 stbc; - -#ifdef CONFIG_BEAMFORMING - u16 txbf_paid; - u16 txbf_gid; -#endif struct stainfo_stats sta_stats; @@ -424,47 +456,47 @@ struct sta_info { #endif /* CONFIG_AP_MODE */ +#ifdef CONFIG_RTW_MESH + struct mesh_plink_ent *plink; + + u8 local_mps; + u8 peer_mps; + u8 nonpeer_mps; + + struct rtw_atlm_param metrics; +#endif + #ifdef CONFIG_IOCTL_CFG80211 u8 *passoc_req; u32 assoc_req_len; #endif - /* for DM */ - RSSI_STA rssi_stat; - - /* ODM_STA_INFO_T */ - /* ================ODM Relative Info======================= */ - /* Please be care, dont declare too much structure here. It will cost memory * STA support num. */ - /* */ - /* */ - /* 2011/10/20 MH Add for ODM STA info. */ - /* */ - /* Driver Write */ - u8 bValid; /* record the sta status link or not? */ - /* u8 WirelessMode; */ /* */ u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ - /* ODM Write */ - /* 1 PHY_STATUS_INFO */ - u8 RSSI_Path[4]; /* */ - u8 RSSI_Ave; - u8 RXEVM[4]; - u8 RXSNR[4]; - - u8 rssi_level; /* for Refresh RA mask */ - /* ODM Write */ - /* 1 TX_INFO (may changed by IC) */ - /* TX_INFO_T pTxInfo; */ /* Define in IC folder. Move lower layer. */ - /* */ - /* ================ODM Relative Info======================= */ - /* */ +#ifdef CONFIG_LPS_PG + u8 lps_pg_rssi_lv; +#endif /* To store the sequence number of received management frame */ u16 RxMgmtFrameSeqNum; struct st_ctl_t st_ctl; u8 max_agg_num_minimal_record; /*keep minimal tx desc max_agg_num setting*/ + u8 curr_rx_rate; + u8 curr_rx_rate_bmc; }; +#ifdef CONFIG_RTW_MESH +#define STA_SET_MESH_PLINK(sta, link) (sta)->plink = link +#else +#define STA_SET_MESH_PLINK(sta, link) do {} while (0) +#endif + +#define sta_tx_pkts(sta) \ + (sta->sta_stats.tx_pkts) + +#define sta_last_tx_pkts(sta) \ + (sta->sta_stats.last_tx_pkts) + #define sta_rx_pkts(sta) \ (sta->sta_stats.rx_mgnt_pkts \ + sta->sta_stats.rx_ctrl_pkts \ @@ -475,15 +507,15 @@ struct sta_info { + sta->sta_stats.last_rx_ctrl_pkts \ + sta->sta_stats.last_rx_data_pkts) -#define sta_rx_data_pkts(sta) \ - (sta->sta_stats.rx_data_pkts) +#define sta_rx_data_pkts(sta) (sta->sta_stats.rx_data_pkts) +#define sta_last_rx_data_pkts(sta) (sta->sta_stats.last_rx_data_pkts) + +#define sta_rx_data_uc_pkts(sta) (sta->sta_stats.rx_data_pkts - sta->sta_stats.rx_data_bc_pkts - sta->sta_stats.rx_data_mc_pkts) +#define sta_last_rx_data_uc_pkts(sta) (sta->sta_stats.last_rx_data_pkts - sta->sta_stats.last_rx_data_bc_pkts - sta->sta_stats.last_rx_data_mc_pkts) #define sta_rx_data_qos_pkts(sta, i) \ (sta->sta_stats.rx_data_qos_pkts[i]) -#define sta_last_rx_data_pkts(sta) \ - (sta->sta_stats.last_rx_data_pkts) - #define sta_last_rx_data_qos_pkts(sta, i) \ (sta->sta_stats.last_rx_data_qos_pkts[i]) @@ -525,6 +557,8 @@ struct sta_info { #define sta_update_last_rx_pkts(sta) \ do { \ + int __i; \ + \ sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \ sta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \ sta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \ @@ -532,7 +566,12 @@ struct sta_info { sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \ sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \ sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \ + \ sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \ + sta->sta_stats.last_rx_data_bc_pkts = sta->sta_stats.rx_data_bc_pkts; \ + sta->sta_stats.last_rx_data_mc_pkts = sta->sta_stats.rx_data_mc_pkts; \ + for (__i = 0; __i < TID_NUM; __i++) \ + sta->sta_stats.last_rx_data_qos_pkts[__i] = sta->sta_stats.rx_data_qos_pkts[__i]; \ } while (0) #define STA_RX_PKTS_ARG(sta) \ @@ -552,6 +591,9 @@ struct sta_info { #define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)" +#define sta_rx_uc_bytes(sta) (sta->sta_stats.rx_bytes - sta->sta_stats.rx_bc_bytes - sta->sta_stats.rx_mc_bytes) +#define sta_last_rx_uc_bytes(sta) (sta->sta_stats.last_rx_bytes - sta->sta_stats.last_rx_bc_bytes - sta->sta_stats.last_rx_mc_bytes) + #ifdef CONFIG_WFD #define STA_OP_WFD_MODE(sta) (sta)->op_wfd_mode #define STA_SET_OP_WFD_MODE(sta, mode) (sta)->op_wfd_mode = (mode) @@ -560,6 +602,8 @@ struct sta_info { #define STA_SET_OP_WFD_MODE(sta, mode) do {} while (0) #endif +#define AID_BMP_LEN(max_aid) ((max_aid + 1) / 8 + (((max_aid + 1) % 8) ? 1 : 0)) + struct sta_priv { u8 *pallocated_stainfo_buf; @@ -588,19 +632,22 @@ struct sta_priv { unsigned int assoc_to; /* sec, time to expire before associating. */ unsigned int expire_to; /* sec , time to expire after associated. */ - /* pointers to STA info; based on allocated AID or NULL if AID free - * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1 - * and so on - */ - struct sta_info *sta_aid[NUM_STA]; - - u16 sta_dz_bitmap;/* only support 15 stations, staion aid bitmap for sleeping sta. */ - u16 tim_bitmap;/* only support 15 stations, aid=0~15 mapping bit0~bit15 */ + /* + * pointers to STA info; based on allocated AID or NULL if AID free + * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1 + */ + struct sta_info **sta_aid; + u16 max_aid; + u16 started_aid; /* started AID for allocation search */ + bool rr_aid; /* round robin AID allocation, will modify started_aid */ + u8 aid_bmp_len; /* in byte */ + u8 *sta_dz_bitmap; + u8 *tim_bitmap; u16 max_num_sta; #if CONFIG_RTW_MACADDR_ACL - struct wlan_acl_pool acl_list; + struct wlan_acl_pool acl_list[RTW_ACL_PERIOD_NUM]; #endif #if CONFIG_RTW_PRE_LINK_STA @@ -612,12 +659,13 @@ struct sta_priv { #ifdef CONFIG_ATMEL_RC_PATCH u8 atmel_rc_pattern[6]; #endif - struct sta_info *c2h_sta; + u8 c2h_sta_mac[ETH_ALEN]; + u8 c2h_adapter_id; struct submit_ctx *gotc2h; }; -__inline static u32 wifi_mac_hash(u8 *mac) +__inline static u32 wifi_mac_hash(const u8 *mac) { u32 x; @@ -642,15 +690,20 @@ extern u32 _rtw_free_sta_priv(struct sta_priv *pstapriv); int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta); struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset); -extern struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr); +extern struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr); extern u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta); extern void rtw_free_all_stainfo(_adapter *padapter); -extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr); +extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr); extern u32 rtw_init_bcmc_stainfo(_adapter *padapter); extern struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter); +#ifdef CONFIG_AP_MODE +u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta); +void dump_aid_status(void *sel, _adapter *adapter); +#endif + #if CONFIG_RTW_MACADDR_ACL -extern u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr); +extern u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr); void dump_macaddr_acl(void *sel, _adapter *adapter); #endif diff --git a/include/usb_ops.h b/include/usb_ops.h index 06b0f42..a0238f1 100644 --- a/include/usb_ops.h +++ b/include/usb_ops.h @@ -117,7 +117,7 @@ static inline u8 rtw_usb_bulk_size_boundary(_adapter *padapter, int buf_len) if (IS_SUPER_SPEED_USB(padapter)) rst = (0 == (buf_len) % USB_SUPER_SPEED_BULK_SIZE) ? _TRUE : _FALSE; - if (IS_HIGH_SPEED_USB(padapter)) + else if (IS_HIGH_SPEED_USB(padapter)) rst = (0 == (buf_len) % USB_HIGH_SPEED_BULK_SIZE) ? _TRUE : _FALSE; else rst = (0 == (buf_len) % USB_FULL_SPEED_BULK_SIZE) ? _TRUE : _FALSE; diff --git a/include/wifi.h b/include/wifi.h index 8540bf5..62d55fb 100644 --- a/include/wifi.h +++ b/include/wifi.h @@ -92,6 +92,7 @@ enum WIFI_FRAME_SUBTYPE { /* below is for control frame */ WIFI_BF_REPORT_POLL = (BIT(6) | WIFI_CTRL_TYPE), WIFI_NDPA = (BIT(6) | BIT(4) | WIFI_CTRL_TYPE), + WIFI_BAR = (BIT(7) | WIFI_CTRL_TYPE), WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE), @@ -400,31 +401,26 @@ enum WIFI_REG_DOMAIN { } while (0) -#define SetPriority(pbuf, tid) \ - do { \ - *(unsigned short *)(pbuf) |= cpu_to_le16(tid & 0xf); \ - } while (0) +/* QoS control field */ +#define SetPriority(qc, tid) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 0, 4, tid) +#define SetEOSP(qc, eosp) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 4, 1, eosp) +#define SetAckpolicy(qc, ack) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 5, 2, ack) +#define SetAMsdu(qc, amsdu) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 7, 1, amsdu) -#define GetPriority(pbuf) ((le16_to_cpu(*(unsigned short *)(pbuf))) & 0xf) - -#define SetEOSP(pbuf, eosp) \ - do { \ - *(unsigned short *)(pbuf) |= cpu_to_le16((eosp & 1) << 4); \ - } while (0) - -#define SetAckpolicy(pbuf, ack) \ - do { \ - *(unsigned short *)(pbuf) |= cpu_to_le16((ack & 3) << 5); \ - } while (0) +#define GetPriority(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 0, 4) +#define GetEOSP(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 4, 1) +#define GetAckpolicy(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 5, 2) +#define GetAMsdu(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 7, 1) -#define GetAckpolicy(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 5) & 0x3) +/* QoS control field (MSTA only) */ +#define set_mctrl_present(qc, p) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 8, 1, p) +#define set_mps_lv(qc, lv) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 9, 1, lv) +#define set_rspi(qc, rspi) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 10, 1, rspi) -#define GetAMsdu(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 7) & 0x1) +#define get_mctrl_present(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 8, 1) +#define get_mps_lv(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 9, 1) +#define get_rspi(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 10, 1) -#define SetAMsdu(pbuf, amsdu) \ - do { \ - *(unsigned short *)(pbuf) |= cpu_to_le16((amsdu & 1) << 7); \ - } while (0) #define GetAid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 2)) & 0x3fff) @@ -446,7 +442,7 @@ enum WIFI_REG_DOMAIN { (addr[4] == 0xff) && (addr[5] == 0xff)) ? _TRUE : _FALSE \ ) -__inline static int IS_MCAST(unsigned char *da) +__inline static int IS_MCAST(const u8 *da) { if ((*da) & 0x01) return _TRUE; @@ -467,6 +463,7 @@ __inline static unsigned char *get_ta(unsigned char *pframe) return ta; } +/* can't apply to mesh mode */ __inline static unsigned char *get_da(unsigned char *pframe) { unsigned char *da; @@ -490,7 +487,7 @@ __inline static unsigned char *get_da(unsigned char *pframe) return da; } - +/* can't apply to mesh mode */ __inline static unsigned char *get_sa(unsigned char *pframe) { unsigned char *sa; @@ -514,6 +511,7 @@ __inline static unsigned char *get_sa(unsigned char *pframe) return sa; } +/* can't apply to mesh mode */ __inline static unsigned char *get_hdr_bssid(unsigned char *pframe) { unsigned char *sa = NULL; @@ -545,6 +543,22 @@ __inline static int IsFrameTypeCtrl(unsigned char *pframe) else return _FALSE; } +static inline int IsFrameTypeMgnt(unsigned char *pframe) +{ + if (GetFrameType(pframe) == WIFI_MGT_TYPE) + return _TRUE; + else + return _FALSE; +} +static inline int IsFrameTypeData(unsigned char *pframe) +{ + if (GetFrameType(pframe) == WIFI_DATA_TYPE) + return _TRUE; + else + return _FALSE; +} + + /*----------------------------------------------------------------------------- Below is for the security related definition ------------------------------------------------------------------------------*/ @@ -582,19 +596,22 @@ __inline static int IsFrameTypeCtrl(unsigned char *pframe) #define _CHLGETXT_IE_ 16 #define _SUPPORTED_CH_IE_ 36 #define _CH_SWTICH_ANNOUNCE_ 37 /* Secondary Channel Offset */ +#define _MEAS_REQ_IE_ 38 +#define _MEAS_RSP_IE_ 39 #define _RSN_IE_2_ 48 #define _SSN_IE_1_ 221 #define _ERPINFO_IE_ 42 #define _EXT_SUPPORTEDRATES_IE_ 50 #define _HT_CAPABILITY_IE_ 45 -#define _MDIE_ 54 -#define _FTIE_ 55 +#define _MDIE_ 54 +#define _FTIE_ 55 #define _TIMEOUT_ITVL_IE_ 56 #define _SRC_IE_ 59 #define _HT_EXTRA_INFO_IE_ 61 #define _HT_ADD_INFO_IE_ 61 /* _HT_EXTRA_INFO_IE_ */ -#define _WAPI_IE_ 68 +#define _WAPI_IE_ 68 +#define _EID_RRM_EN_CAP_IE_ 70 /* #define EID_BSSCoexistence 72 */ /* 20/40 BSS Coexistence @@ -737,9 +754,8 @@ typedef enum _ELEMENT_ID { #define _WEP_WPA_MIXED_PRIVACY_ 6 /* WEP + WPA */ #endif -#ifdef CONFIG_IEEE80211W #define _MME_IE_LENGTH_ 18 -#endif /* CONFIG_IEEE80211W */ + /*----------------------------------------------------------------------------- Below is the definition for WMM ------------------------------------------------------------------------------*/ @@ -812,6 +828,7 @@ struct rtw_ieee80211_ht_cap { * This structure refers to "HT information element" as * described in 802.11n draft section 7.3.2.53 */ +#ifndef CONFIG_IEEE80211_HT_ADDT_INFO struct ieee80211_ht_addt_info { unsigned char control_chan; unsigned char ht_param; @@ -819,7 +836,7 @@ struct ieee80211_ht_addt_info { unsigned short stbc_param; unsigned char basic_set[16]; } __attribute__((packed)); - +#endif struct HT_caps_element { union { @@ -1356,10 +1373,8 @@ enum P2P_PS_MODE { #define WFD_DEVINFO_PC_TDLS 0x0080 #define WFD_DEVINFO_HDCP_SUPPORT 0x0100 -#ifdef CONFIG_TX_MCAST2UNI #define IP_MCAST_MAC(mac) ((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e)) #define ICMPV6_MCAST_MAC(mac) ((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff)) -#endif /* CONFIG_TX_MCAST2UNI */ #ifdef CONFIG_IOCTL_CFG80211 /* Regulatroy Domain */ diff --git a/include/wlan_bssdef.h b/include/wlan_bssdef.h index 84cb2d4..e7ae359 100644 --- a/include/wlan_bssdef.h +++ b/include/wlan_bssdef.h @@ -77,6 +77,7 @@ typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE { Ndis802_11InfrastructureMax, /* Not a real value, defined as upper bound */ Ndis802_11APMode, Ndis802_11Monitor, + Ndis802_11_mesh, } NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE; @@ -521,7 +522,12 @@ typedef struct _WLAN_PHY_INFO { u8 SignalStrength;/* (in percentage) */ u8 SignalQuality;/* (in percentage) */ u8 Optimum_antenna; /* for Antenna diversity */ - u8 Reserved_0; + u8 is_cck_rate; /* 1:cck_rate */ + s8 rx_snr[4]; +#ifdef CONFIG_RTW_80211K + u32 free_cnt; /* freerun counter */ + u8 rm_en_cap[5]; +#endif } WLAN_PHY_INFO, *PWLAN_PHY_INFO; typedef struct _WLAN_BCN_INFO { @@ -537,6 +543,13 @@ typedef struct _WLAN_BCN_INFO { unsigned char ht_info_infos_0; } WLAN_BCN_INFO, *PWLAN_BCN_INFO; +enum bss_type { + BSS_TYPE_UNDEF, + BSS_TYPE_BCN = 1, + BSS_TYPE_PROB_REQ = 2, + BSS_TYPE_PROB_RSP = 3, +}; + /* temporally add #pragma pack for structure alignment issue of * WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz() */ @@ -547,8 +560,9 @@ typedef struct _WLAN_BCN_INFO { typedef struct _WLAN_BSSID_EX { ULONG Length; NDIS_802_11_MAC_ADDRESS MacAddress; - UCHAR Reserved[2];/* [0]: IS beacon frame */ + UCHAR Reserved[2];/* [0]: IS beacon frame , bss_type*/ NDIS_802_11_SSID Ssid; + NDIS_802_11_SSID mesh_id; ULONG Privacy; NDIS_802_11_RSSI Rssi;/* (in dBM,raw data ,get from PHY) */ NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; @@ -569,7 +583,7 @@ WLAN_BSSID_EX, *PWLAN_BSSID_EX; #define BSS_EX_IES(bss_ex) ((bss_ex)->IEs) #define BSS_EX_IES_LEN(bss_ex) ((bss_ex)->IELength) -#define BSS_EX_FIXED_IE_OFFSET(bss_ex) ((bss_ex)->Reserved[0] == 2 ? 0 : 12) +#define BSS_EX_FIXED_IE_OFFSET(bss_ex) ((bss_ex)->Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12) #define BSS_EX_TLV_IES(bss_ex) (BSS_EX_IES((bss_ex)) + BSS_EX_FIXED_IE_OFFSET((bss_ex))) #define BSS_EX_TLV_IES_LEN(bss_ex) (BSS_EX_IES_LEN((bss_ex)) - BSS_EX_FIXED_IE_OFFSET((bss_ex))) @@ -603,7 +617,7 @@ struct wlan_network { _list list; int network_type; /* refer to ieee80211.h for WIRELESS_11A/B/G */ int fixed; /* set to fixed when not to be removed as site-surveying */ - unsigned long last_scanned; /* timestamp for the network */ + systime last_scanned; /* timestamp for the network */ int aid; /* will only be valid when a BSS is joinned. */ int join_res; WLAN_BSSID_EX network; /* must be the last item */ diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index 7a18ad0..e7e8930 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -19,28 +19,29 @@ #ifdef CONFIG_IOCTL_CFG80211 -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) - #if !defined(WIPHY_FLAG_SUPPORTS_SCHED_SCAN) - #define WIPHY_FLAG_SUPPORTS_SCHED_SCAN BIT(12) - #endif -#endif - - -#ifdef CONFIG_CENTOS_7 - #define STATION_INFO_SIGNAL BIT(NL80211_STA_INFO_SIGNAL) - #define STATION_INFO_TX_BITRATE BIT(NL80211_STA_INFO_TX_BITRATE) - #define STATION_INFO_RX_PACKETS BIT(NL80211_STA_INFO_RX_PACKETS) - #define STATION_INFO_TX_PACKETS BIT(NL80211_STA_INFO_TX_PACKETS) - #define STATION_INFO_ASSOC_REQ_IES 0 -#else - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) - #define STATION_INFO_SIGNAL BIT(NL80211_STA_INFO_SIGNAL) - #define STATION_INFO_TX_BITRATE BIT(NL80211_STA_INFO_TX_BITRATE) - #define STATION_INFO_RX_PACKETS BIT(NL80211_STA_INFO_RX_PACKETS) - #define STATION_INFO_TX_PACKETS BIT(NL80211_STA_INFO_TX_PACKETS) - #define STATION_INFO_ASSOC_REQ_IES 0 - #endif /* Linux kernel >= 4.0.0 */ -#endif +#ifndef DBG_RTW_CFG80211_STA_PARAM +#define DBG_RTW_CFG80211_STA_PARAM 0 +#endif + +#ifndef DBG_RTW_CFG80211_MESH_CONF +#define DBG_RTW_CFG80211_MESH_CONF 0 +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) +#define STATION_INFO_INACTIVE_TIME BIT(NL80211_STA_INFO_INACTIVE_TIME) +#define STATION_INFO_LLID BIT(NL80211_STA_INFO_LLID) +#define STATION_INFO_PLID BIT(NL80211_STA_INFO_PLID) +#define STATION_INFO_PLINK_STATE BIT(NL80211_STA_INFO_PLINK_STATE) +#define STATION_INFO_SIGNAL BIT(NL80211_STA_INFO_SIGNAL) +#define STATION_INFO_TX_BITRATE BIT(NL80211_STA_INFO_TX_BITRATE) +#define STATION_INFO_RX_PACKETS BIT(NL80211_STA_INFO_RX_PACKETS) +#define STATION_INFO_TX_PACKETS BIT(NL80211_STA_INFO_TX_PACKETS) +#define STATION_INFO_TX_FAILED BIT(NL80211_STA_INFO_TX_FAILED) +#define STATION_INFO_LOCAL_PM BIT(NL80211_STA_INFO_LOCAL_PM) +#define STATION_INFO_PEER_PM BIT(NL80211_STA_INFO_PEER_PM) +#define STATION_INFO_NONPEER_PM BIT(NL80211_STA_INFO_NONPEER_PM) +#define STATION_INFO_ASSOC_REQ_IES 0 +#endif /* Linux kernel >= 4.0.0 */ #include @@ -78,6 +79,15 @@ #define WLAN_AKM_SUITE_FT_PSK 0x000FAC04 #endif +/* + * In the current design of Wi-Fi driver, it will return success to the system (e.g. supplicant) + * when Wi-Fi driver decides to abort the scan request in the scan flow by default. + * Defining this flag makes Wi-Fi driver to return -EBUSY to the system if Wi-Fi driver is too busy to do the scan. + */ +#ifndef CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY + #define CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY 0 +#endif + static const u32 rtw_cipher_suites[] = { WLAN_CIPHER_SUITE_WEP40, WLAN_CIPHER_SUITE_WEP104, @@ -129,9 +139,6 @@ static const struct wiphy_wowlan_support wowlan_stub = { .pattern_min_len = 0, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) .max_pkt_offset = 0, - #ifdef CONFIG_CENTOS_7 - .max_nd_match_sets = 0, - #endif #endif }; #endif @@ -188,6 +195,247 @@ static struct ieee80211_channel rtw_5ghz_a_channels[MAX_CHANNEL_NUM_5G] = { CHAN5G(165, 0), CHAN5G(169, 0), CHAN5G(173, 0), CHAN5G(177, 0), }; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) +static const char *nl80211_channel_type_str(enum nl80211_channel_type ctype) +{ + switch (ctype) { + case NL80211_CHAN_NO_HT: + return "NO_HT"; + case NL80211_CHAN_HT20: + return "HT20"; + case NL80211_CHAN_HT40MINUS: + return "HT40-"; + case NL80211_CHAN_HT40PLUS: + return "HT40+"; + default: + return "INVALID"; + }; +} + +static enum nl80211_channel_type rtw_chbw_to_nl80211_channel_type(u8 ch, u8 bw, u8 offset, u8 ht) +{ + rtw_warn_on(!ht && (bw >= CHANNEL_WIDTH_40 || offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE)); + + if (!ht) + return NL80211_CHAN_NO_HT; + if (bw >= CHANNEL_WIDTH_40) { + if (offset == HAL_PRIME_CHNL_OFFSET_UPPER) + return NL80211_CHAN_HT40MINUS; + else if (offset == HAL_PRIME_CHNL_OFFSET_LOWER) + return NL80211_CHAN_HT40PLUS; + else + rtw_warn_on(1); + } + return NL80211_CHAN_HT20; +} + +static void rtw_get_chbw_from_nl80211_channel_type(struct ieee80211_channel *chan, enum nl80211_channel_type ctype, u8 *ht, u8 *ch, u8 *bw, u8 *offset) +{ + int pri_freq; + + pri_freq = rtw_ch2freq(chan->hw_value); + if (!pri_freq) { + RTW_INFO("invalid channel:%d\n", chan->hw_value); + rtw_warn_on(1); + *ch = 0; + return; + } + *ch = chan->hw_value; + + switch (ctype) { + case NL80211_CHAN_NO_HT: + *ht = 0; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + case NL80211_CHAN_HT20: + *ht = 1; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + case NL80211_CHAN_HT40MINUS: + *ht = 1; + *bw = CHANNEL_WIDTH_40; + *offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + case NL80211_CHAN_HT40PLUS: + *ht = 1; + *bw = CHANNEL_WIDTH_40; + *offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + default: + *ht = 0; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + RTW_INFO("unsupported ctype:%s\n", nl80211_channel_type_str(ctype)); + rtw_warn_on(1); + }; +} +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) */ + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) +static const char *nl80211_chan_width_str(enum nl80211_chan_width cwidth) +{ + switch (cwidth) { + case NL80211_CHAN_WIDTH_20_NOHT: + return "20_NOHT"; + case NL80211_CHAN_WIDTH_20: + return "20"; + case NL80211_CHAN_WIDTH_40: + return "40"; + case NL80211_CHAN_WIDTH_80: + return "80"; + case NL80211_CHAN_WIDTH_80P80: + return "80+80"; + case NL80211_CHAN_WIDTH_160: + return "160"; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + case NL80211_CHAN_WIDTH_5: + return "5"; + case NL80211_CHAN_WIDTH_10: + return "10"; +#endif + default: + return "INVALID"; + }; +} + +static u8 rtw_chbw_to_cfg80211_chan_def(struct wiphy *wiphy, struct cfg80211_chan_def *chdef, u8 ch, u8 bw, u8 offset, u8 ht) +{ + int freq, cfreq; + struct ieee80211_channel *chan; + u8 ret = _FAIL; + + freq = rtw_ch2freq(ch); + if (!freq) + goto exit; + + cfreq = rtw_get_center_ch(ch, bw, offset); + if (!cfreq) + goto exit; + cfreq = rtw_ch2freq(cfreq); + if (!cfreq) + goto exit; + + chan = ieee80211_get_channel(wiphy, freq); + if (!chan) + goto exit; + + if (bw == CHANNEL_WIDTH_20) + chdef->width = ht ? NL80211_CHAN_WIDTH_20 : NL80211_CHAN_WIDTH_20_NOHT; + else if (bw == CHANNEL_WIDTH_40) + chdef->width = NL80211_CHAN_WIDTH_40; + else if (bw == CHANNEL_WIDTH_80) + chdef->width = NL80211_CHAN_WIDTH_80; + else if (bw == CHANNEL_WIDTH_160) + chdef->width = NL80211_CHAN_WIDTH_160; + else { + rtw_warn_on(1); + goto exit; + } + + chdef->chan = chan; + chdef->center_freq1 = cfreq; + chdef->center_freq2 = 0; + + ret = _SUCCESS; + +exit: + return ret; +} + +static void rtw_get_chbw_from_cfg80211_chan_def(struct cfg80211_chan_def *chdef, u8 *ht, u8 *ch, u8 *bw, u8 *offset) +{ + int pri_freq; + struct ieee80211_channel *chan = chdef->chan; + + pri_freq = rtw_ch2freq(chan->hw_value); + if (!pri_freq) { + RTW_INFO("invalid channel:%d\n", chan->hw_value); + rtw_warn_on(1); + *ch = 0; + return; + } + + switch (chdef->width) { + case NL80211_CHAN_WIDTH_20_NOHT: + *ht = 0; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *ch = chan->hw_value; + break; + case NL80211_CHAN_WIDTH_20: + *ht = 1; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *ch = chan->hw_value; + break; + case NL80211_CHAN_WIDTH_40: + *ht = 1; + *bw = CHANNEL_WIDTH_40; + *offset = pri_freq > chdef->center_freq1 ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER; + if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset)) + *ch = chan->hw_value; + break; + case NL80211_CHAN_WIDTH_80: + *ht = 1; + *bw = CHANNEL_WIDTH_80; + if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset)) + *ch = chan->hw_value; + break; + case NL80211_CHAN_WIDTH_160: + *ht = 1; + *bw = CHANNEL_WIDTH_160; + if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset)) + *ch = chan->hw_value; + break; + case NL80211_CHAN_WIDTH_80P80: + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + case NL80211_CHAN_WIDTH_5: + case NL80211_CHAN_WIDTH_10: + #endif + default: + *ht = 0; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + RTW_INFO("unsupported cwidth:%s\n", nl80211_chan_width_str(chdef->width)); + rtw_warn_on(1); + }; +} +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) */ + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) +u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, u8 ht) +{ + struct wiphy *wiphy = adapter_to_wiphy(adapter); + u8 ret = _SUCCESS; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + struct cfg80211_chan_def chdef; + + ret = rtw_chbw_to_cfg80211_chan_def(wiphy, &chdef, ch, bw, offset, ht); + if (ret != _SUCCESS) + goto exit; + + cfg80211_ch_switch_notify(adapter->pnetdev, &chdef); + +#else + int freq = rtw_ch2freq(ch); + enum nl80211_channel_type ctype; + + if (!freq) { + ret = _FAIL; + goto exit; + } + + ctype = rtw_chbw_to_nl80211_channel_type(ch, bw, offset, ht); + cfg80211_ch_switch_notify(adapter->pnetdev, freq, ctype); +#endif + +exit: + return ret; +} +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */ void rtw_2g_channels_init(struct ieee80211_channel *channels) { @@ -213,17 +461,15 @@ void rtw_5g_rates_init(struct ieee80211_rate *rates) ); } -struct ieee80211_supported_band *rtw_spt_band_alloc( - enum nl80211_band band -) +struct ieee80211_supported_band *rtw_spt_band_alloc(BAND_TYPE band) { struct ieee80211_supported_band *spt_band = NULL; int n_channels, n_bitrates; - if (band == NL80211_BAND_2GHZ) { + if (band == BAND_ON_2_4G) { n_channels = MAX_CHANNEL_NUM_2G; n_bitrates = RTW_G_RATES_NUM; - } else if (band == NL80211_BAND_5GHZ) { + } else if (band == BAND_ON_5G) { n_channels = MAX_CHANNEL_NUM_5G; n_bitrates = RTW_A_RATES_NUM; } else @@ -239,14 +485,14 @@ struct ieee80211_supported_band *rtw_spt_band_alloc( spt_band->channels = (struct ieee80211_channel *)(((u8 *)spt_band) + sizeof(struct ieee80211_supported_band)); spt_band->bitrates = (struct ieee80211_rate *)(((u8 *)spt_band->channels) + sizeof(struct ieee80211_channel) * n_channels); - spt_band->band = band; + spt_band->band = rtw_band_to_nl80211_band(band); spt_band->n_channels = n_channels; spt_band->n_bitrates = n_bitrates; - if (band == NL80211_BAND_2GHZ) { + if (band == BAND_ON_2_4G) { rtw_2g_channels_init(spt_band->channels); rtw_2g_rates_init(spt_band->bitrates); - } else if (band == NL80211_BAND_5GHZ) { + } else if (band == BAND_ON_5G) { rtw_5g_channels_init(spt_band->channels); rtw_5g_rates_init(spt_band->bitrates); } @@ -265,27 +511,11 @@ void rtw_spt_band_free(struct ieee80211_supported_band *spt_band) if (!spt_band) return; -#ifdef CONFIG_CENTOS_7 if (spt_band->band == NL80211_BAND_2GHZ) { -#else - #if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE) - if (spt_band->band == NL80211_BAND_2GHZ) { - #else - if (spt_band->band == IEEE80211_BAND_2GHZ) { - #endif -#endif size = sizeof(struct ieee80211_supported_band) + sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_2G + sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM; -#ifdef CONFIG_CENTOS_7 } else if (spt_band->band == NL80211_BAND_5GHZ) { -#else - #if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE) - } else if (spt_band->band == NL80211_BAND_5GHZ) { - #else - } else if (spt_band->band == IEEE80211_BAND_5GHZ) { - #endif -#endif size = sizeof(struct ieee80211_supported_band) + sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_5G + sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM; @@ -350,9 +580,110 @@ static const struct ieee80211_txrx_stypes BIT(IEEE80211_STYPE_PROBE_REQ >> 4) }, #endif +#if defined(CONFIG_RTW_MESH) + [NL80211_IFTYPE_MESH_POINT] = { + .tx = 0xffff, + .rx = BIT(IEEE80211_STYPE_ACTION >> 4) + | BIT(IEEE80211_STYPE_AUTH >> 4) + }, +#endif + }; #endif +NDIS_802_11_NETWORK_INFRASTRUCTURE nl80211_iftype_to_rtw_network_type(enum nl80211_iftype type) +{ + switch (type) { + case NL80211_IFTYPE_ADHOC: + return Ndis802_11IBSS; + + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + case NL80211_IFTYPE_P2P_CLIENT: + #endif + case NL80211_IFTYPE_STATION: + return Ndis802_11Infrastructure; + +#ifdef CONFIG_AP_MODE + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + case NL80211_IFTYPE_P2P_GO: + #endif + case NL80211_IFTYPE_AP: + return Ndis802_11APMode; +#endif + +#ifdef CONFIG_RTW_MESH + case NL80211_IFTYPE_MESH_POINT: + return Ndis802_11_mesh; +#endif + + case NL80211_IFTYPE_MONITOR: + return Ndis802_11Monitor; + + default: + return Ndis802_11InfrastructureMax; + } +} + +u32 nl80211_iftype_to_rtw_mlme_state(enum nl80211_iftype type) +{ + switch (type) { + case NL80211_IFTYPE_ADHOC: + return WIFI_ADHOC_STATE; + + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + case NL80211_IFTYPE_P2P_CLIENT: + #endif + case NL80211_IFTYPE_STATION: + return WIFI_STATION_STATE; + +#ifdef CONFIG_AP_MODE + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + case NL80211_IFTYPE_P2P_GO: + #endif + case NL80211_IFTYPE_AP: + return WIFI_AP_STATE; +#endif + +#ifdef CONFIG_RTW_MESH + case NL80211_IFTYPE_MESH_POINT: + return WIFI_MESH_STATE; +#endif + + case NL80211_IFTYPE_MONITOR: + return WIFI_MONITOR_STATE; + + default: + return WIFI_NULL_STATE; + } +} + +static int rtw_cfg80211_sync_iftype(_adapter *adapter) +{ + struct wireless_dev *rtw_wdev = adapter->rtw_wdev; + + if (!(nl80211_iftype_to_rtw_mlme_state(rtw_wdev->iftype) & MLME_STATE(adapter))) { + /* iftype and mlme state is not syc */ + NDIS_802_11_NETWORK_INFRASTRUCTURE network_type; + + network_type = nl80211_iftype_to_rtw_network_type(rtw_wdev->iftype); + if (network_type != Ndis802_11InfrastructureMax) { + if (rtw_pwr_wakeup(adapter) == _FAIL) { + RTW_WARN(FUNC_ADPT_FMT" call rtw_pwr_wakeup fail\n", FUNC_ADPT_ARG(adapter)); + return _FAIL; + } + + rtw_set_802_11_infrastructure_mode(adapter, network_type); + rtw_setopmode_cmd(adapter, network_type, RTW_CMDF_WAIT_ACK); + } else { + rtw_warn_on(1); + RTW_WARN(FUNC_ADPT_FMT" iftype:%u is not support\n", FUNC_ADPT_ARG(adapter), rtw_wdev->iftype); + return _FAIL; + } + } + + return _SUCCESS; +} + static u64 rtw_get_systime_us(void) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) @@ -492,7 +823,7 @@ struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_net SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); /* pmlmeext->mgnt_seq++; */ - if (pnetwork->network.Reserved[0] == 1) { /* WIFI_BEACON */ + if (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) { /* WIFI_BEACON */ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); set_frame_sub_type(pbuf, WIFI_BEACON); } else { @@ -534,7 +865,7 @@ struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_net #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 38)) #ifndef COMPAT_KERNEL_RELEASE /* patch for cfg80211, update beacon ies to information_elements */ - if (pnetwork->network.Reserved[0] == 1) { /* WIFI_BEACON */ + if (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) { /* WIFI_BEACON */ if (bss->len_information_elements != bss->len_beacon_ies) { bss->information_elements = bss->beacon_ies; @@ -611,16 +942,10 @@ void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter) struct wlan_network *cur_network = &(pmlmepriv->cur_network); struct wireless_dev *pwdev = padapter->rtw_wdev; struct cfg80211_bss *bss = NULL; -#ifdef CONFIG_CENTOS_7 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) struct wiphy *wiphy = pwdev->wiphy; int freq = 2412; struct ieee80211_channel *notify_channel; -#else - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) - struct wiphy *wiphy = pwdev->wiphy; - int freq = 2412; - struct ieee80211_channel *notify_channel; - #endif #endif RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); @@ -673,16 +998,11 @@ void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter) RTW_PRINT(FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter)); } /* notify cfg80211 that device joined an IBSS */ -#ifdef CONFIG_CENTOS_7 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) notify_channel = ieee80211_get_channel(wiphy, freq); cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, notify_channel, GFP_ATOMIC); #else - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) - notify_channel = ieee80211_get_channel(wiphy, freq); - cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, notify_channel, GFP_ATOMIC); - #else - cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, GFP_ATOMIC); - #endif + cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, GFP_ATOMIC); #endif } @@ -698,6 +1018,10 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) #endif struct cfg80211_bss *bss = NULL; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) + struct cfg80211_roam_info roam_info ={}; +#endif + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); if (pwdev->iftype != NL80211_IFTYPE_STATION #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) @@ -706,7 +1030,7 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) ) return; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (!MLME_IS_STA(padapter)) return; #ifdef CONFIG_P2P @@ -767,21 +1091,18 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) notify_channel = ieee80211_get_channel(wiphy, freq); #endif - RTW_INFO(FUNC_ADPT_FMT" call cfg80211_roamed\n", FUNC_ADPT_ARG(padapter)); - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)) - struct cfg80211_roam_info roam_info = { - .channel = notify_channel, - .bssid = cur_network->network.MacAddress, - .req_ie = pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2, - .req_ie_len = pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2, - .resp_ie = pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6, - .resp_ie_len = pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 - }; - cfg80211_roamed(padapter->pnetdev,&roam_info, GFP_ATOMIC); + #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) + roam_info.bssid = cur_network->network.MacAddress; + roam_info.req_ie = pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2; + roam_info.req_ie_len = pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2; + roam_info.resp_ie = pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6; + roam_info.resp_ie_len = pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6; + + cfg80211_roamed(padapter->pnetdev, &roam_info, GFP_ATOMIC); #else - cfg80211_roamed(padapter->pnetdev + cfg80211_roamed(padapter->pnetdev #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) - , notify_channel + , notify_channel #endif , cur_network->network.MacAddress , pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2 @@ -789,29 +1110,28 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) , pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 , GFP_ATOMIC); - #endif + #endif /*LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)*/ + + RTW_INFO(FUNC_ADPT_FMT" call cfg80211_roamed\n", FUNC_ADPT_ARG(padapter)); + #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) - rtw_set_ft_status(padapter, RTW_FT_ASSOCIATED_STA); + if (rtw_ft_roam(padapter)) + rtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA); #endif } else { - #ifdef CONFIG_CENTOS_7 - #else - #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) - RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state); - #endif + #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) + RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state); #endif - rtw_cfg80211_connect_result(pwdev, cur_network->network.MacAddress - , pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2 - , pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2 - , pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 - , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 - , WLAN_STATUS_SUCCESS, GFP_ATOMIC); - #ifdef CONFIG_CENTOS_7 - #else - #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) - RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state); - #endif + + if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) + rtw_cfg80211_connect_result(pwdev, cur_network->network.MacAddress + , pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2 + , pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2 + , pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 + , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 + , WLAN_STATUS_SUCCESS, GFP_ATOMIC); + #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) + RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state); #endif } @@ -833,7 +1153,7 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); /*always replace privated definitions with wifi reserved value 0*/ - if ((reason == WLAN_REASON_ACTIVE_ROAM) || (reason == WLAN_REASON_JOIN_WRONG_CHANNEL) || (reason == WLAN_REASON_EXPIRATION_CHK)) + if (WLAN_REASON_IS_PRIVATE(reason)) reason = 0; if (pwdev->iftype != NL80211_IFTYPE_STATION @@ -843,7 +1163,7 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally ) return; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (!MLME_IS_STA(padapter)) return; #ifdef CONFIG_P2P @@ -866,31 +1186,28 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally _enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL); if (padapter->ndev_unregistering || !rtw_wdev_not_indic_disco(pwdev_priv)) { - #ifdef CONFIG_CENTOS_7 - #else - #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) - RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state); - - if (pwdev->sme_state == CFG80211_SME_CONNECTING) { - RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result\n", FUNC_ADPT_ARG(padapter)); - rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0, - WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC); - } else if (pwdev->sme_state == CFG80211_SME_CONNECTED) { - RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter)); - rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC); - } + #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) + RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state); + + if (pwdev->sme_state == CFG80211_SME_CONNECTING) { + RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result\n", FUNC_ADPT_ARG(padapter)); + rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0, + WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC); + } else if (pwdev->sme_state == CFG80211_SME_CONNECTED) { + RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter)); + rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC); + } - RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state); - #else - if (pwdev_priv->connect_req) { - RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result\n", FUNC_ADPT_ARG(padapter)); - rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0, - WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC); - } else { - RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter)); - rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC); - } - #endif + RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state); + #else + if (pwdev_priv->connect_req) { + RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result\n", FUNC_ADPT_ARG(padapter)); + rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0, + WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC); + } else { + RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter)); + rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC); + } #endif } @@ -901,7 +1218,7 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally #ifdef CONFIG_AP_MODE -static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param) { int ret = 0; u32 wep_key_idx, wep_key_len, wep_total_len; @@ -916,20 +1233,11 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa param->u.crypt.err = 0; param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; - /* sizeof(struct ieee_param) = 64 bytes; */ - /* if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) */ - if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len) { - ret = -EINVAL; - goto exit; - } - - if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { + if (is_broadcast_mac_addr(param->sta_addr)) { if (param->u.crypt.idx >= WEP_KEYS -#ifdef CONFIG_IEEE80211W + #ifdef CONFIG_IEEE80211W && param->u.crypt.idx > BIP_MAX_KEYID -#endif /* CONFIG_IEEE80211W */ + #endif ) { ret = -EINVAL; goto exit; @@ -937,8 +1245,9 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } else { psta = rtw_get_stainfo(pstapriv, param->sta_addr); if (!psta) { - /* ret = -EINVAL; */ - RTW_INFO("rtw_set_encryption(), sta has already been removed or never been added\n"); + ret = -EINVAL; + RTW_INFO(FUNC_ADPT_FMT", sta "MAC_FMT" not found\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(param->sta_addr)); goto exit; } } @@ -994,76 +1303,64 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } - - if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) { /* group key */ - if (param->u.crypt.set_tx == 0) { /* group key */ + if (!psta) { /* group key */ + if (param->u.crypt.set_tx == 0) { /* group key, TX only */ if (strcmp(param->u.crypt.alg, "WEP") == 0) { - RTW_INFO("%s, set group_key, WEP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set WEP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - psecuritypriv->dot118021XGrpPrivacy = _WEP40_; if (param->u.crypt.key_len == 13) psecuritypriv->dot118021XGrpPrivacy = _WEP104_; } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - RTW_INFO("%s, set group_key, TKIP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set TKIP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); psecuritypriv->dot118021XGrpPrivacy = _TKIP_; - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ /* set mic key */ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); - psecuritypriv->busetkipkey = _TRUE; } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - RTW_INFO("%s, set group_key, CCMP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set CCMP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); psecuritypriv->dot118021XGrpPrivacy = _AES_; - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - } -#ifdef CONFIG_IEEE80211W - else if (strcmp(param->u.crypt.alg, "BIP") == 0) { - int no; - RTW_INFO("BIP key_len=%d , index=%d\n", param->u.crypt.key_len, param->u.crypt.idx); - /* save the IGTK key, length 16 bytes */ + #ifdef CONFIG_IEEE80211W + } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set TX IGTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - /* RTW_INFO("IGTK key below:\n"); - for(no=0;no<16;no++) - printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); - RTW_INFO("\n"); */ padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; + psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq); padapter->securitypriv.binstallBIPkey = _TRUE; - RTW_INFO(" ~~~~set sta key:IGKT\n"); goto exit; - } -#endif /* CONFIG_IEEE80211W */ - else { - RTW_INFO("%s, set group_key, none\n", __FUNCTION__); + #endif /* CONFIG_IEEE80211W */ + } else if (strcmp(param->u.crypt.alg, "none") == 0) { + RTW_INFO(FUNC_ADPT_FMT" clear group key, idx:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx); psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + } else { + RTW_WARN(FUNC_ADPT_FMT" set group key, not support\n" + , FUNC_ADPT_ARG(padapter)); + goto exit; } psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; - - psecuritypriv->binstallGrpkey = _TRUE; - - psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ - - rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); if (pbcmc_sta) { + pbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); pbcmc_sta->ieee8021x_blocked = _FALSE; pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy */ } + psecuritypriv->binstallGrpkey = _TRUE; + psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ + rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); } goto exit; @@ -1071,99 +1368,103 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */ - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - if (param->u.crypt.set_tx == 1) { /* pairwise key */ - _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - if (strcmp(param->u.crypt.alg, "WEP") == 0) { - RTW_INFO("%s, set pairwise key, WEP\n", __FUNCTION__); - - psta->dot118021XPrivacy = _WEP40_; - if (param->u.crypt.key_len == 13) - psta->dot118021XPrivacy = _WEP104_; - } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - RTW_INFO("%s, set pairwise key, TKIP\n", __FUNCTION__); - - psta->dot118021XPrivacy = _TKIP_; - - /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ - /* set mic key */ - _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); - _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); - - psecuritypriv->busetkipkey = _TRUE; - - } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - - RTW_INFO("%s, set pairwise key, CCMP\n", __FUNCTION__); - - psta->dot118021XPrivacy = _AES_; - } else { - RTW_INFO("%s, set pairwise key, none\n", __FUNCTION__); - - psta->dot118021XPrivacy = _NO_PRIVACY_; - } - - rtw_ap_set_pairwise_key(padapter, psta); - - psta->ieee8021x_blocked = _FALSE; - - psta->bpairwise_key_installed = _TRUE; - - } else { /* group key??? */ - if (strcmp(param->u.crypt.alg, "WEP") == 0) { - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - psecuritypriv->dot118021XGrpPrivacy = _WEP40_; - if (param->u.crypt.key_len == 13) - psecuritypriv->dot118021XGrpPrivacy = _WEP104_; - } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - psecuritypriv->dot118021XGrpPrivacy = _TKIP_; - - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ - /* set mic key */ - _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); - _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); - - psecuritypriv->busetkipkey = _TRUE; - - } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - psecuritypriv->dot118021XGrpPrivacy = _AES_; - - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - } else - psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; - - psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; + if (param->u.crypt.set_tx == 1) { + /* pairwise key */ + _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - psecuritypriv->binstallGrpkey = _TRUE; + if (strcmp(param->u.crypt.alg, "WEP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + psta->dot118021XPrivacy = _WEP40_; + if (param->u.crypt.key_len == 13) + psta->dot118021XPrivacy = _WEP104_; - psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ + } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + psta->dot118021XPrivacy = _TKIP_; + /* set mic key */ + _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); + psecuritypriv->busetkipkey = _TRUE; - rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); + } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + psta->dot118021XPrivacy = _AES_; + + } else if (strcmp(param->u.crypt.alg, "none") == 0) { + RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx); + psta->dot118021XPrivacy = _NO_PRIVACY_; + } else { + RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + goto exit; + } - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); - if (pbcmc_sta) { - pbcmc_sta->ieee8021x_blocked = _FALSE; - pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy */ - } + psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); + psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq); + psta->ieee8021x_blocked = _FALSE; + psta->bpairwise_key_installed = _TRUE; + rtw_ap_set_pairwise_key(padapter, psta); + } else { + /* peer's group key, RX only */ + #ifdef CONFIG_RTW_MESH + if (strcmp(param->u.crypt.alg, "CCMP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set CCMP GTK of "MAC_FMT", idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + psta->group_privacy = _AES_; + _rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + psta->gtk_bmp |= BIT(param->u.crypt.idx); + psta->gtk_pn.val = RTW_GET_LE64(param->u.crypt.seq); + + #ifdef CONFIG_IEEE80211W + } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set IGTK of "MAC_FMT", idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + _rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + psta->igtk_bmp |= BIT(param->u.crypt.idx); + psta->igtk_id = param->u.crypt.idx; + psta->igtk_pn.val = RTW_GET_LE64(param->u.crypt.seq); + goto exit; + #endif /* CONFIG_IEEE80211W */ + + } else if (strcmp(param->u.crypt.alg, "none") == 0) { + RTW_INFO(FUNC_ADPT_FMT" clear group key of "MAC_FMT", idx:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx); + psta->group_privacy = _NO_PRIVACY_; + psta->gtk_bmp &= ~BIT(param->u.crypt.idx); + } else + #endif /* CONFIG_RTW_MESH */ + { + RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + goto exit; } + #ifdef CONFIG_RTW_MESH + rtw_ap_set_sta_key(padapter, psta->cmn.mac_addr, psta->group_privacy + , param->u.crypt.key, param->u.crypt.idx, 1); + #endif } } exit: - return ret; - } -#endif +#endif /* CONFIG_AP_MODE */ -static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param) { int ret = 0; u32 wep_key_idx, wep_key_len, wep_total_len; @@ -1174,24 +1475,16 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param struct wifidirect_info *pwdinfo = &padapter->wdinfo; #endif /* CONFIG_P2P */ - RTW_INFO("%s\n", __func__); param->u.crypt.err = 0; param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; - if (param_len < (u32)((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) { - ret = -EINVAL; - goto exit; - } - - if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { + if (is_broadcast_mac_addr(param->sta_addr)) { if (param->u.crypt.idx >= WEP_KEYS -#ifdef CONFIG_IEEE80211W + #ifdef CONFIG_IEEE80211W && param->u.crypt.idx > BIP_MAX_KEYID -#endif /* CONFIG_IEEE80211W */ + #endif ) { ret = -EINVAL; goto exit; @@ -1212,7 +1505,7 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param wep_key_idx = param->u.crypt.idx; wep_key_len = param->u.crypt.key_len; - if ((wep_key_idx > WEP_KEYS) || (wep_key_len <= 0)) { + if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) { ret = -EINVAL; goto exit; } @@ -1251,7 +1544,7 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */ #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) + if (rtw_ft_roam(padapter)) psta = rtw_get_stainfo(pstapriv, pmlmepriv->assoc_bssid); else #endif @@ -1264,61 +1557,53 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param if (strcmp(param->u.crypt.alg, "none") != 0) psta->ieee8021x_blocked = _FALSE; - if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) || (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; if (param->u.crypt.set_tx == 1) { /* pairwise key */ - - RTW_INFO("%s, : param->u.crypt.set_tx ==1\n", __func__); - + RTW_INFO(FUNC_ADPT_FMT" set %s PTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - if (strcmp(param->u.crypt.alg, "TKIP") == 0) { /* set mic key */ - /* DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); */ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); - padapter->securitypriv.busetkipkey = _FALSE; } + psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); + psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq); psta->bpairwise_key_installed = _TRUE; -#ifdef CONFIG_RTW_80211R + #ifdef CONFIG_RTW_80211R psta->ft_pairwise_key_installed = _TRUE; -#endif - /* DEBUG_ERR((" param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); */ - RTW_INFO(" ~~~~set sta key:unicastkey\n"); - + #endif rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE); + } else { /* group key */ if (strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set %s GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); padapter->securitypriv.binstallGrpkey = _TRUE; - /* DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); */ - RTW_INFO(" ~~~~set sta key:groupkey\n"); - + if (param->u.crypt.idx < 4) + _rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8); padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx; rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE); - } -#ifdef CONFIG_IEEE80211W - else if (strcmp(param->u.crypt.alg, "BIP") == 0) { - int no; - /* RTW_INFO("BIP key_len=%d , index=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.key_len, param->u.crypt.idx); */ - /* save the IGTK key, length 16 bytes */ + + #ifdef CONFIG_IEEE80211W + } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set IGTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - /*RTW_INFO("IGTK key below:\n"); - for(no=0;no<16;no++) - printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); - RTW_INFO("\n");*/ - padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; - padapter->securitypriv.binstallBIPkey = _TRUE; - RTW_INFO(" ~~~~set sta key:IGKT\n"); + psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx; + psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq); + psecuritypriv->binstallBIPkey = _TRUE; + #endif /* CONFIG_IEEE80211W */ + } -#endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_P2P if (pwdinfo->driver_interface == DRIVER_CFG80211) { @@ -1346,64 +1631,10 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param } } -#ifdef CONFIG_WAPI_SUPPORT - if (strcmp(param->u.crypt.alg, "SMS4") == 0) { - PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; - PRT_WAPI_STA_INFO pWapiSta; - u8 WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - - if (param->u.crypt.set_tx == 1) { - list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { - if (_rtw_memcmp(pWapiSta->PeerMacAddr, param->sta_addr, 6)) { - _rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16); - - pWapiSta->wapiUsk.bSet = true; - _rtw_memcpy(pWapiSta->wapiUsk.dataKey, param->u.crypt.key, 16); - _rtw_memcpy(pWapiSta->wapiUsk.micKey, param->u.crypt.key + 16, 16); - pWapiSta->wapiUsk.keyId = param->u.crypt.idx ; - pWapiSta->wapiUsk.bTxEnable = true; - - _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16); - pWapiSta->wapiUskUpdate.bTxEnable = false; - pWapiSta->wapiUskUpdate.bSet = false; - - if (psecuritypriv->sw_encrypt == false || psecuritypriv->sw_decrypt == false) { - /* set unicast key for ASUE */ - rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false); - } - } - } - } else { - list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { - if (_rtw_memcmp(pWapiSta->PeerMacAddr, get_bssid(pmlmepriv), 6)) { - pWapiSta->wapiMsk.bSet = true; - _rtw_memcpy(pWapiSta->wapiMsk.dataKey, param->u.crypt.key, 16); - _rtw_memcpy(pWapiSta->wapiMsk.micKey, param->u.crypt.key + 16, 16); - pWapiSta->wapiMsk.keyId = param->u.crypt.idx ; - pWapiSta->wapiMsk.bTxEnable = false; - if (!pWapiSta->bSetkeyOk) - pWapiSta->bSetkeyOk = true; - pWapiSta->bAuthenticateInProgress = false; - - _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); - - if (psecuritypriv->sw_decrypt == false) { - /* set rx broadcast key for ASUE */ - rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false); - } - } - - } - } - } -#endif - + #ifdef CONFIG_WAPI_SUPPORT + if (strcmp(param->u.crypt.alg, "SMS4") == 0) + rtw_wapi_set_set_encryption(padapter, param); + #endif exit: @@ -1413,13 +1644,12 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param return ret; } -static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, +static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev + , u8 key_index #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - u8 key_index, bool pairwise, const u8 *mac_addr, -#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - u8 key_index, const u8 *mac_addr, -#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - struct key_params *params) + , bool pairwise +#endif + , const u8 *mac_addr, struct key_params *params) { char *alg_name; u32 param_len; @@ -1432,17 +1662,21 @@ static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, struct sta_info *ptdls_sta; #endif /* CONFIG_TDLS */ - RTW_INFO(FUNC_NDEV_FMT" adding key for %pM\n", FUNC_NDEV_ARG(ndev), mac_addr); - RTW_INFO("cipher=0x%x\n", params->cipher); - RTW_INFO("key_len=0x%x\n", params->key_len); - RTW_INFO("seq_len=0x%x\n", params->seq_len); - RTW_INFO("key_index=%d\n", key_index); + if (mac_addr) + RTW_INFO(FUNC_NDEV_FMT" adding key for %pM\n", FUNC_NDEV_ARG(ndev), mac_addr); + RTW_INFO(FUNC_NDEV_FMT" cipher=0x%x\n", FUNC_NDEV_ARG(ndev), params->cipher); + RTW_INFO(FUNC_NDEV_FMT" key_len=%d, key_index=%d\n", FUNC_NDEV_ARG(ndev), params->key_len, key_index); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - RTW_INFO("pairwise=%d\n", pairwise); -#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ + RTW_INFO(FUNC_NDEV_FMT" pairwise=%d\n", FUNC_NDEV_ARG(ndev), pairwise); +#endif + + if (rtw_cfg80211_sync_iftype(padapter) != _SUCCESS) { + ret = -ENOTSUPP; + goto addkey_end; + } param_len = sizeof(struct ieee_param) + params->key_len; - param = (struct ieee_param *)rtw_malloc(param_len); + param = rtw_malloc(param_len); if (param == NULL) return -1; @@ -1495,18 +1729,23 @@ static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN); - if (!mac_addr || is_broadcast_ether_addr(mac_addr)) { + if (!mac_addr || is_broadcast_ether_addr(mac_addr) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + || !pairwise + #endif + ) { param->u.crypt.set_tx = 0; /* for wpa/wpa2 group key */ } else { param->u.crypt.set_tx = 1; /* for wpa/wpa2 pairwise key */ } - - /* param->u.crypt.idx = key_index - 1; */ param->u.crypt.idx = key_index; - if (params->seq_len && params->seq) + if (params->seq_len && params->seq) { _rtw_memcpy(param->u.crypt.seq, (u8 *)params->seq, params->seq_len); + RTW_INFO(FUNC_NDEV_FMT" seq_len:%u, seq:0x%llx\n", FUNC_NDEV_ARG(ndev) + , params->seq_len, RTW_GET_LE64(param->u.crypt.seq)); + } if (params->key_len && params->key) { param->u.crypt.key_len = params->key_len; @@ -1524,62 +1763,194 @@ static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, } } #endif /* CONFIG_TDLS */ - - ret = rtw_cfg80211_set_encryption(ndev, param, param_len); - } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + ret = rtw_cfg80211_set_encryption(ndev, param); + } else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { #ifdef CONFIG_AP_MODE if (mac_addr) _rtw_memcpy(param->sta_addr, (void *)mac_addr, ETH_ALEN); - ret = rtw_cfg80211_ap_set_encryption(ndev, param, param_len); + ret = rtw_cfg80211_ap_set_encryption(ndev, param); #endif } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE ) { /* RTW_INFO("@@@@@@@@@@ fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype); */ - ret = rtw_cfg80211_set_encryption(ndev, param, param_len); + ret = rtw_cfg80211_set_encryption(ndev, param); } else RTW_INFO("error! fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype); addkey_end: if (param) - rtw_mfree((u8 *)param, param_len); + rtw_mfree(param, param_len); return ret; } -static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev, +static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev + , u8 keyid #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - u8 key_index, bool pairwise, const u8 *mac_addr, -#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - u8 key_index, const u8 *mac_addr, -#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - void *cookie, - void (*callback)(void *cookie, struct key_params *)) + , bool pairwise +#endif + , const u8 *mac_addr, void *cookie + , void (*callback)(void *cookie, struct key_params *)) { -#if 0 - struct iwm_priv *iwm = ndev_to_iwm(ndev); - struct iwm_key *key = &iwm->keys[key_index]; +#define GET_KEY_PARAM_FMT_S " keyid=%d" +#define GET_KEY_PARAM_ARG_S , keyid +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + #define GET_KEY_PARAM_FMT_2_6_37 ", pairwise=%d" + #define GET_KEY_PARAM_ARG_2_6_37 , pairwise +#else + #define GET_KEY_PARAM_FMT_2_6_37 "" + #define GET_KEY_PARAM_ARG_2_6_37 +#endif +#define GET_KEY_PARAM_FMT_E ", addr=%pM" +#define GET_KEY_PARAM_ARG_E , mac_addr + + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + struct security_priv *sec = &adapter->securitypriv; + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sta = NULL; + u32 cipher = _NO_PRIVACY_; + union Keytype *key = NULL; + u8 key_len = 0; + u64 *pn = NULL; + u8 pn_len = 0; + u8 pn_val[8] = {0}; + struct key_params params; + int ret = -ENOENT; + + if (keyid >= WEP_KEYS + #ifdef CONFIG_IEEE80211W + && keyid > BIP_MAX_KEYID + #endif + ) + goto exit; + + if (!mac_addr || is_broadcast_ether_addr(mac_addr) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + || (MLME_IS_STA(adapter) && !pairwise) + #endif + ) { + /* WEP key, TX GTK/IGTK, RX GTK/IGTK(for STA mode) */ + if (is_wep_enc(sec->dot118021XGrpPrivacy)) { + if (keyid >= WEP_KEYS) + goto exit; + if (!(sec->key_mask & BIT(keyid))) + goto exit; + cipher = sec->dot118021XGrpPrivacy; + key = &sec->dot11DefKey[keyid]; + } else { + if (keyid < WEP_KEYS) { + if (sec->binstallGrpkey != _TRUE) + goto exit; + cipher = sec->dot118021XGrpPrivacy; + key = &sec->dot118021XGrpKey[keyid]; + sta = rtw_get_bcmc_stainfo(adapter); + if (sta) + pn = &sta->dot11txpn.val; + #ifdef CONFIG_IEEE80211W + } else if (keyid < BIP_MAX_KEYID) { + if (SEC_IS_BIP_KEY_INSTALLED(sec) != _TRUE) + goto exit; + cipher = _BIP_; + key = &sec->dot11wBIPKey[keyid]; + pn = &sec->dot11wBIPtxpn.val; + #endif + } + } + } else { + /* Pairwise key, RX GTK/IGTK for specific peer */ + sta = rtw_get_stainfo(stapriv, mac_addr); + if (!sta) + goto exit; + + if (keyid < WEP_KEYS && pairwise) { + if (sta->bpairwise_key_installed != _TRUE) + goto exit; + cipher = sta->dot118021XPrivacy; + key = &sta->dot118021x_UncstKey; + #ifdef CONFIG_RTW_MESH + } else if (keyid < WEP_KEYS && !pairwise) { + if (!(sta->gtk_bmp & BIT(keyid))) + goto exit; + cipher = sta->group_privacy; + key = &sta->gtk; + #ifdef CONFIG_IEEE80211W + } else if (keyid < BIP_MAX_KEYID && !pairwise) { + if (!(sta->igtk_bmp & BIT(keyid))) + goto exit; + cipher = _BIP_; + key = &sta->igtk; + pn = &sta->igtk_pn.val; + #endif + #endif /* CONFIG_RTW_MESH */ + } + } + + if (!key) + goto exit; - IWM_DBG_WEXT(iwm, DBG, "Getting key %d\n", key_index); + if (cipher == _WEP40_) { + cipher = WLAN_CIPHER_SUITE_WEP40; + key_len = sec->dot11DefKeylen[keyid]; + } else if (cipher == _WEP104_) { + cipher = WLAN_CIPHER_SUITE_WEP104; + key_len = sec->dot11DefKeylen[keyid]; + } else if (cipher == _TKIP_) { + cipher = WLAN_CIPHER_SUITE_TKIP; + key_len = 16; + } else if (cipher == _AES_) { + cipher = WLAN_CIPHER_SUITE_CCMP; + key_len = 16; + #ifdef CONFIG_IEEE80211W + } else if (cipher == _BIP_) { + cipher = WLAN_CIPHER_SUITE_AES_CMAC; + key_len = 16; + #endif + } else { + RTW_WARN(FUNC_NDEV_FMT" unknown cipher:%u\n", FUNC_NDEV_ARG(ndev), cipher); + rtw_warn_on(1); + goto exit; + } - memset(¶ms, 0, sizeof(params)); + if (pn) { + *((u64 *)pn_val) = cpu_to_le64(*pn); + pn_len = 6; + } - params.cipher = key->cipher; - params.key_len = key->key_len; - params.seq_len = key->seq_len; - params.seq = key->seq; - params.key = key->key; + ret = 0; + +exit: + RTW_INFO(FUNC_NDEV_FMT + GET_KEY_PARAM_FMT_S + GET_KEY_PARAM_FMT_2_6_37 + GET_KEY_PARAM_FMT_E + " ret %d\n", FUNC_NDEV_ARG(ndev) + GET_KEY_PARAM_ARG_S + GET_KEY_PARAM_ARG_2_6_37 + GET_KEY_PARAM_ARG_E + , ret); + if (pn) + RTW_INFO(FUNC_NDEV_FMT " seq:0x%llx\n", FUNC_NDEV_ARG(ndev), *pn); + + if (ret == 0) { + _rtw_memset(¶ms, 0, sizeof(params)); + + params.cipher = cipher; + params.key = key->skey; + params.key_len = key_len; + if (pn) { + params.seq = pn_val; + params.seq_len = pn_len; + } - callback(cookie, ¶ms); + callback(cookie, ¶ms); + } - return key->key_len ? 0 : -ENOENT; -#endif - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); - return 0; + return ret; } static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev, @@ -1592,7 +1963,7 @@ static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev, _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct security_priv *psecuritypriv = &padapter->securitypriv; - RTW_INFO(FUNC_NDEV_FMT" key_index=%d\n", FUNC_NDEV_ARG(ndev), key_index); + RTW_INFO(FUNC_NDEV_FMT" key_index=%d, addr=%pM\n", FUNC_NDEV_ARG(ndev), key_index, mac_addr); if (key_index == psecuritypriv->dot11PrivacyKeyIndex) { /* clear the flag of wep default key set. */ @@ -1648,6 +2019,24 @@ static int cfg80211_rtw_set_default_key(struct wiphy *wiphy, return 0; } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)) +int cfg80211_rtw_set_default_mgmt_key(struct wiphy *wiphy, + struct net_device *ndev, u8 key_index) +{ +#define SET_DEF_KEY_PARAM_FMT " key_index=%d" +#define SET_DEF_KEY_PARAM_ARG , key_index + + RTW_INFO(FUNC_NDEV_FMT + SET_DEF_KEY_PARAM_FMT + "\n", FUNC_NDEV_ARG(ndev) + SET_DEF_KEY_PARAM_ARG + ); + + return 0; +} +#endif + #if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) static int cfg80211_rtw_set_rekey_data(struct wiphy *wiphy, struct net_device *ndev, @@ -1683,6 +2072,101 @@ static int cfg80211_rtw_set_rekey_data(struct wiphy *wiphy, return 0; } #endif /*CONFIG_GTK_OL*/ + +#ifdef CONFIG_RTW_MESH +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) +static enum nl80211_mesh_power_mode rtw_mesh_ps_to_nl80211_mesh_power_mode(u8 ps) +{ + if (ps == RTW_MESH_PS_UNKNOWN) + return NL80211_MESH_POWER_UNKNOWN; + if (ps == RTW_MESH_PS_ACTIVE) + return NL80211_MESH_POWER_ACTIVE; + if (ps == RTW_MESH_PS_LSLEEP) + return NL80211_MESH_POWER_LIGHT_SLEEP; + if (ps == RTW_MESH_PS_DSLEEP) + return NL80211_MESH_POWER_DEEP_SLEEP; + + rtw_warn_on(1); + return NL80211_MESH_POWER_UNKNOWN; +} +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +enum nl80211_plink_state rtw_plink_state_to_nl80211_plink_state(u8 plink_state) +{ + if (plink_state == RTW_MESH_PLINK_UNKNOWN) + return NUM_NL80211_PLINK_STATES; + if (plink_state == RTW_MESH_PLINK_LISTEN) + return NL80211_PLINK_LISTEN; + if (plink_state == RTW_MESH_PLINK_OPN_SNT) + return NL80211_PLINK_OPN_SNT; + if (plink_state == RTW_MESH_PLINK_OPN_RCVD) + return NL80211_PLINK_OPN_RCVD; + if (plink_state == RTW_MESH_PLINK_CNF_RCVD) + return NL80211_PLINK_CNF_RCVD; + if (plink_state == RTW_MESH_PLINK_ESTAB) + return NL80211_PLINK_ESTAB; + if (plink_state == RTW_MESH_PLINK_HOLDING) + return NL80211_PLINK_HOLDING; + if (plink_state == RTW_MESH_PLINK_BLOCKED) + return NL80211_PLINK_BLOCKED; + + rtw_warn_on(1); + return NUM_NL80211_PLINK_STATES; +} + +u8 nl80211_plink_state_to_rtw_plink_state(enum nl80211_plink_state plink_state) +{ + if (plink_state == NL80211_PLINK_LISTEN) + return RTW_MESH_PLINK_LISTEN; + if (plink_state == NL80211_PLINK_OPN_SNT) + return RTW_MESH_PLINK_OPN_SNT; + if (plink_state == NL80211_PLINK_OPN_RCVD) + return RTW_MESH_PLINK_OPN_RCVD; + if (plink_state == NL80211_PLINK_CNF_RCVD) + return RTW_MESH_PLINK_CNF_RCVD; + if (plink_state == NL80211_PLINK_ESTAB) + return RTW_MESH_PLINK_ESTAB; + if (plink_state == NL80211_PLINK_HOLDING) + return RTW_MESH_PLINK_HOLDING; + if (plink_state == NL80211_PLINK_BLOCKED) + return RTW_MESH_PLINK_BLOCKED; + + rtw_warn_on(1); + return RTW_MESH_PLINK_UNKNOWN; +} +#endif + +static void rtw_cfg80211_fill_mesh_only_sta_info(struct mesh_plink_ent *plink, struct sta_info *sta, struct station_info *sinfo) +{ + sinfo->filled |= STATION_INFO_LLID; + sinfo->llid = plink->llid; + sinfo->filled |= STATION_INFO_PLID; + sinfo->plid = plink->plid; + sinfo->filled |= STATION_INFO_PLINK_STATE; + sinfo->plink_state = rtw_plink_state_to_nl80211_plink_state(plink->plink_state); + if (!sta && plink->scanned) { + sinfo->filled |= STATION_INFO_SIGNAL; + sinfo->signal = translate_percentage_to_dbm(plink->scanned->network.PhyInfo.SignalStrength); + sinfo->filled |= STATION_INFO_INACTIVE_TIME; + if (plink->plink_state == RTW_MESH_PLINK_UNKNOWN) + sinfo->inactive_time = 0 - 1; + else + sinfo->inactive_time = rtw_get_passing_time_ms(plink->scanned->last_scanned); + } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + if (sta) { + sinfo->filled |= STATION_INFO_LOCAL_PM; + sinfo->local_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->local_mps); + sinfo->filled |= STATION_INFO_PEER_PM; + sinfo->peer_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->peer_mps); + sinfo->filled |= STATION_INFO_NONPEER_PM; + sinfo->nonpeer_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->nonpeer_mps); + } +#endif +} +#endif /* CONFIG_RTW_MESH */ + static int cfg80211_rtw_get_station(struct wiphy *wiphy, struct net_device *ndev, #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)) @@ -1697,6 +2181,9 @@ static int cfg80211_rtw_get_station(struct wiphy *wiphy, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; +#ifdef CONFIG_RTW_MESH + struct mesh_plink_ent *plink = NULL; +#endif sinfo->filled = 0; @@ -1706,9 +2193,23 @@ static int cfg80211_rtw_get_station(struct wiphy *wiphy, goto exit; } - psta = rtw_get_stainfo(pstapriv, (u8 *)mac); - if (psta == NULL) { - RTW_INFO("%s, sta_info is null\n", __func__); + psta = rtw_get_stainfo(pstapriv, mac); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + if (!psta) + plink = rtw_mesh_plink_get(padapter, mac); + else + plink = psta->plink; + } +#endif /* CONFIG_RTW_MESH */ + + if (!psta + #ifdef CONFIG_RTW_MESH + && !plink + #endif + ) { + RTW_INFO(FUNC_NDEV_FMT" no sta info for mac="MAC_FMT"\n" + , FUNC_NDEV_ARG(ndev), MAC_ARG(mac)); ret = -ENOENT; goto exit; } @@ -1734,23 +2235,29 @@ static int cfg80211_rtw_get_station(struct wiphy *wiphy, sinfo->filled |= STATION_INFO_TX_BITRATE; sinfo->txrate.legacy = rtw_get_cur_max_rate(padapter); + } + if (psta) { + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE + || check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE + ) { + sinfo->filled |= STATION_INFO_SIGNAL; + sinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi); + } + sinfo->filled |= STATION_INFO_INACTIVE_TIME; + sinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time); sinfo->filled |= STATION_INFO_RX_PACKETS; sinfo->rx_packets = sta_rx_data_pkts(psta); - sinfo->filled |= STATION_INFO_TX_PACKETS; sinfo->tx_packets = psta->sta_stats.tx_pkts; - + sinfo->filled |= STATION_INFO_TX_FAILED; + sinfo->tx_failed = psta->sta_stats.tx_fail_cnt; } - /* for Ad-Hoc/AP mode */ - if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) - || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) - || check_fwstate(pmlmepriv, WIFI_AP_STATE)) - && check_fwstate(pmlmepriv, _FW_LINKED) - ) { - /* TODO: should acquire station info... */ - } +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_cfg80211_fill_mesh_only_sta_info(plink, psta, sinfo); +#endif exit: return ret; @@ -1777,11 +2284,10 @@ enum nl80211_iftype { #endif static int cfg80211_rtw_change_iface(struct wiphy *wiphy, struct net_device *ndev, - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)) - enum nl80211_iftype type, - #else - enum nl80211_iftype type, u32 *flags, - #endif + enum nl80211_iftype type, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) + u32 *flags, +#endif struct vif_params *params) { enum nl80211_iftype old_type; @@ -1894,6 +2400,12 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, break; +#ifdef CONFIG_RTW_MESH + case NL80211_IFTYPE_MESH_POINT: + networkType = Ndis802_11_mesh; + break; +#endif + case NL80211_IFTYPE_MONITOR: networkType = Ndis802_11Monitor; #if 0 @@ -1914,7 +2426,7 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, goto exit; } - rtw_setopmode_cmd(padapter, networkType, _TRUE); + rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK); exit: @@ -1963,7 +2475,7 @@ u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms) { struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter); u8 empty = _FALSE; - u32 start; + systime start; u32 pass_ms; start = rtw_get_current_time(); @@ -2307,9 +2819,7 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy int i, chan_num = 0; u8 _status = _FALSE; int ret = 0; - NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; - struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; - struct rtw_ieee80211_channel *pch; + struct sitesurvey_parm parm; _irqL irqL; u8 *wps_ie = NULL; uint wps_ielen = 0; @@ -2369,6 +2879,14 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy } #endif +#ifdef CONFIG_RTW_REPEATER_SON + if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) { + RTW_INFO(FUNC_ADPT_FMT" blocking scan for under rson scanning process\n", FUNC_ADPT_ARG(padapter)); + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } +#endif + if (adapter_wdev_data(padapter)->block_scan == _TRUE) { RTW_INFO(FUNC_ADPT_FMT" wdev_priv.block_scan is set\n", FUNC_ADPT_ARG(padapter)); need_indicate_scan_done = _TRUE; @@ -2413,8 +2931,13 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy if (rtw_is_scan_deny(padapter)) { RTW_INFO(FUNC_ADPT_FMT ": scan deny\n", FUNC_ADPT_ARG(padapter)); +#if CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY + ret = -EBUSY; + goto exit; +#else need_indicate_scan_done = _TRUE; goto check_need_indicate_scan_done; +#endif } /* check fw state*/ @@ -2470,7 +2993,6 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy #ifdef CONFIG_P2P if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) { rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); - rtw_free_network_queue(padapter, _TRUE); if (social_channel == 0) rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); @@ -2479,46 +3001,42 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy } #endif /* CONFIG_P2P */ + rtw_init_sitesurvey_parm(padapter, &parm); - _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID) * RTW_SSID_SCAN_AMOUNT); /* parsing request ssids, n_ssids */ for (i = 0; i < request->n_ssids && i < RTW_SSID_SCAN_AMOUNT; i++) { #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("ssid=%s, len=%d\n", ssids[i].ssid, ssids[i].ssid_len); #endif - _rtw_memcpy(ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len); - ssid[i].SsidLength = ssids[i].ssid_len; + _rtw_memcpy(&parm.ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len); + parm.ssid[i].SsidLength = ssids[i].ssid_len; } + parm.ssid_num = i; /* parsing channels, n_channels */ - _rtw_memset(ch, 0, sizeof(struct rtw_ieee80211_channel) * RTW_CHANNEL_SCAN_AMOUNT); for (i = 0; i < request->n_channels && i < RTW_CHANNEL_SCAN_AMOUNT; i++) { #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO(FUNC_ADPT_FMT CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(request->channels[i])); #endif - ch[i].hw_value = request->channels[i]->hw_value; - ch[i].flags = request->channels[i]->flags; + parm.ch[i].hw_value = request->channels[i]->hw_value; + parm.ch[i].flags = request->channels[i]->flags; } + parm.ch_num = i; if (request->n_channels == 1) { for (i = 1; i < survey_times_for_one_ch; i++) - _rtw_memcpy(&ch[i], &ch[0], sizeof(struct rtw_ieee80211_channel)); - pch = ch; - chan_num = survey_times_for_one_ch; + _rtw_memcpy(&parm.ch[i], &parm.ch[0], sizeof(struct rtw_ieee80211_channel)); + parm.ch_num = survey_times_for_one_ch; } else if (request->n_channels <= 4) { for (j = request->n_channels - 1; j >= 0; j--) for (i = 0; i < survey_times; i++) - _rtw_memcpy(&ch[j * survey_times + i], &ch[j], sizeof(struct rtw_ieee80211_channel)); - pch = ch; - chan_num = survey_times * request->n_channels; - } else { - pch = ch; - chan_num = request->n_channels; + _rtw_memcpy(&parm.ch[j * survey_times + i], &parm.ch[j], sizeof(struct rtw_ieee80211_channel)); + parm.ch_num = survey_times * request->n_channels; } _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); _enter_critical_bh(&pmlmepriv->lock, &irqL); - _status = rtw_sitesurvey_cmd(padapter, ssid, RTW_SSID_SCAN_AMOUNT, pch, chan_num); + _status = rtw_sitesurvey_cmd(padapter, &parm); if (_status == _SUCCESS) pwdev_priv->scan_request = request; else @@ -2760,6 +3278,7 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) u8 *buf = NULL, *pos = NULL; u32 left; int group_cipher = 0, pairwise_cipher = 0; + u8 mfp_opt = MFP_NO; int ret = 0; int wpa_ielen = 0; int wpa2_ielen = 0; @@ -2785,13 +3304,8 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) _rtw_memcpy(buf, pie , ielen); - /* dump */ - { - int i; - RTW_INFO("set wpa_ie(length:%zu):\n", ielen); - for (i = 0; i < ielen; i = i + 8) - RTW_INFO("0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x\n", buf[i], buf[i + 1], buf[i + 2], buf[i + 3], buf[i + 4], buf[i + 5], buf[i + 6], buf[i + 7]); - } + RTW_INFO("set wpa_ie(length:%zu):\n", ielen); + RTW_INFO_DUMP(NULL, buf, ielen); pos = buf; if (ielen < RSN_HEADER_LEN) { @@ -2812,7 +3326,7 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) pwpa2 = rtw_get_wpa2_ie(buf, &wpa2_ielen, ielen); if (pwpa2 && wpa2_ielen > 0) { - if (rtw_parse_wpa2_ie(pwpa2, wpa2_ielen + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + if (rtw_parse_wpa2_ie(pwpa2, wpa2_ielen + 2, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) { padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; _rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa2[0], wpa2_ielen + 2); @@ -2872,6 +3386,13 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) break; } + if (mfp_opt == MFP_INVALID) { + RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter)); + ret = -EINVAL; + goto exit; + } + padapter->securitypriv.mfp_opt = mfp_opt; + {/* handle wps_ie */ uint wps_ielen; u8 *wps_ie; @@ -2985,11 +3506,6 @@ static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev, goto exit; } - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - ret = -EPERM; - goto exit; - } - rtw_ps_deny(padapter, PS_DENY_JOIN); if (_FAIL == rtw_pwr_wakeup(padapter)) { ret = -EPERM; @@ -3062,7 +3578,7 @@ static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev) ret = -EPERM; goto leave_ibss; } - rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, _TRUE); + rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK); } leave_ibss: @@ -3071,6 +3587,19 @@ static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev) return 0; } +bool rtw_cfg80211_is_connect_requested(_adapter *adapter) +{ + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); + _irqL irqL; + bool requested; + + _enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + requested = pwdev_priv->connect_req ? 1 : 0; + _exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + + return requested; +} + static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, struct cfg80211_connect_params *sme) { @@ -3135,17 +3664,9 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, goto cancel_ps_deny; } - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - ret = -EPERM; - goto cancel_ps_deny; - } - - if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { - ret = -EBUSY; - RTW_INFO("%s, fw_state=0x%x, goto exit\n", __func__, pmlmepriv->fw_state); - goto cancel_ps_deny; - } + rtw_mi_scan_abort(padapter, _TRUE); + rtw_join_abort_timeout(padapter, 300); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING)) { ret = -EINVAL; @@ -3153,8 +3674,6 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, } #endif - rtw_mi_scan_abort(padapter, _TRUE); - _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); ndis_ssid.SsidLength = sme->ssid_len; _rtw_memcpy(ndis_ssid.Ssid, (u8 *)sme->ssid, sme->ssid_len); @@ -3345,9 +3864,12 @@ static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev, /* if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) */ { rtw_scan_abort(padapter); + rtw_join_abort_timeout(padapter, 300); LeaveAllPowerSaveMode(padapter); rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK); - +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_do_disconnect(padapter); +#endif RTW_INFO("%s...call rtw_indicate_disconnect\n", __func__); rtw_free_assoc_resources(padapter, 1); @@ -3592,7 +4114,7 @@ void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint f } -void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason) +void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason) { s32 freq; int channel; @@ -3677,13 +4199,21 @@ static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_de struct rtw_ieee80211_hdr *dot11_hdr; struct ieee80211_radiotap_header *rtap_hdr; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); if (skb) rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize); - if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) + if (IS_CH_WAITING(rfctl)) { + #ifdef CONFIG_DFS_MASTER + if (rtw_rfctl_overlap_radar_detect_ch(rfctl)) + goto fail; + #endif + } + + if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) goto fail; rtap_hdr = (struct ieee80211_radiotap_header *)skb->data; @@ -3870,12 +4400,11 @@ static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct ne mon_ndev->type = ARPHRD_IEEE80211_RADIOTAP; strncpy(mon_ndev->name, name, IFNAMSIZ); mon_ndev->name[IFNAMSIZ - 1] = 0; - #if (LINUX_VERSION_CODE>=KERNEL_VERSION(4,11,9)) - mon_ndev->needs_free_netdev = true; - mon_ndev->priv_destructor = rtw_ndev_destructor; - #else - mon_ndev->destructor = rtw_ndev_destructor; - #endif +#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 11, 8)) + mon_ndev->priv_destructor = rtw_ndev_destructor; +#else + mon_ndev->destructor = rtw_ndev_destructor; +#endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) mon_ndev->netdev_ops = &rtw_cfg80211_monitor_if_ops; @@ -3941,11 +4470,11 @@ static int #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) unsigned char name_assign_type, #endif - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)) - enum nl80211_iftype type, struct vif_params *params) - #else - enum nl80211_iftype type, u32 *flags, struct vif_params *params) + enum nl80211_iftype type, + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) + u32 *flags, #endif + struct vif_params *params) { int ret = 0; struct wireless_dev *wdev = NULL; @@ -3971,6 +4500,9 @@ static int #endif case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_AP: +#ifdef CONFIG_RTW_MESH + case NL80211_IFTYPE_MESH_POINT: +#endif padapter = dvobj_get_unregisterd_adapter(dvobj); if (!padapter) { RTW_WARN("adapter pool empty!\n"); @@ -3999,7 +4531,6 @@ static int case NL80211_IFTYPE_ADHOC: case NL80211_IFTYPE_AP_VLAN: case NL80211_IFTYPE_WDS: - case NL80211_IFTYPE_MESH_POINT: default: ret = -ENODEV; RTW_INFO("Unsupported interface type\n"); @@ -4174,8 +4705,15 @@ static int cfg80211_rtw_add_beacon(struct wiphy *wiphy, struct net_device *ndev, _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) { + ret = -ENOTSUPP; + goto exit; + } + ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len); +exit: return ret; } @@ -4196,8 +4734,13 @@ static int cfg80211_rtw_set_beacon(struct wiphy *wiphy, struct net_device *ndev, static int cfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *ndev) { + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure); + rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK); + return 0; } #else @@ -4210,6 +4753,11 @@ static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, RTW_INFO(FUNC_NDEV_FMT" hidden_ssid:%d, auth_type:%d\n", FUNC_NDEV_ARG(ndev), settings->hidden_ssid, settings->auth_type); + if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) { + ret = -ENOTSUPP; + goto exit; + } + ret = rtw_add_beacon(adapter, settings->beacon.head, settings->beacon.head_len, settings->beacon.tail, settings->beacon.tail_len); @@ -4235,6 +4783,7 @@ static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); } +exit: return ret; } @@ -4253,10 +4802,15 @@ static int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *nd static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev) { + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure); + rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK); + return 0; } - #endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) */ #if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) @@ -4270,6 +4824,7 @@ static int cfg80211_rtw_set_mac_acl(struct wiphy *wiphy, struct net_device *ndev if (!params) { RTW_WARN(FUNC_ADPT_FMT" params NULL\n", FUNC_ADPT_ARG(adapter)); + rtw_macaddr_acl_clear(adapter, RTW_ACL_PERIOD_BSS); goto exit; } @@ -4281,25 +4836,197 @@ static int cfg80211_rtw_set_mac_acl(struct wiphy *wiphy, struct net_device *ndev else if (params->acl_policy == NL80211_ACL_POLICY_DENY_UNLESS_LISTED) acl_mode = RTW_ACL_MODE_DENY_UNLESS_LISTED; - if (!params->n_acl_entries) { - if (acl_mode != RTW_ACL_MODE_DISABLED) - RTW_WARN(FUNC_ADPT_FMT" acl_policy:%d with no entry\n" - , FUNC_ADPT_ARG(adapter), params->acl_policy); - acl_mode = RTW_ACL_MODE_DISABLED; - goto exit; - } + rtw_macaddr_acl_clear(adapter, RTW_ACL_PERIOD_BSS); + + rtw_set_macaddr_acl(adapter, RTW_ACL_PERIOD_BSS, acl_mode); for (i = 0; i < params->n_acl_entries; i++) - rtw_acl_add_sta(adapter, params->mac_addrs[i].addr); + rtw_acl_add_sta(adapter, RTW_ACL_PERIOD_BSS, params->mac_addrs[i].addr); ret = 0; exit: - rtw_set_macaddr_acl(adapter, acl_mode); return ret; } #endif /* CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) */ +const char *_nl80211_sta_flags_str[] = { + "INVALID", + "AUTHORIZED", + "SHORT_PREAMBLE", + "WME", + "MFP", + "AUTHENTICATED", + "TDLS_PEER", + "ASSOCIATED", +}; + +#define nl80211_sta_flags_str(_f) ((_f <= NL80211_STA_FLAG_MAX) ? _nl80211_sta_flags_str[_f] : _nl80211_sta_flags_str[0]) + +const char *_nl80211_plink_state_str[] = { + "LISTEN", + "OPN_SNT", + "OPN_RCVD", + "CNF_RCVD", + "ESTAB", + "HOLDING", + "BLOCKED", + "UNKNOWN", +}; + +#define nl80211_plink_state_str(_s) ((_s < NUM_NL80211_PLINK_STATES) ? _nl80211_plink_state_str[_s] : _nl80211_plink_state_str[NUM_NL80211_PLINK_STATES]) + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)) +#define NL80211_PLINK_ACTION_NO_ACTION PLINK_ACTION_INVALID +#define NL80211_PLINK_ACTION_OPEN PLINK_ACTION_OPEN +#define NL80211_PLINK_ACTION_BLOCK PLINK_ACTION_BLOCK +#define NUM_NL80211_PLINK_ACTIONS 3 +#endif + +const char *_nl80211_plink_actions_str[] = { + "NO_ACTION", + "OPEN", + "BLOCK", + "UNKNOWN", +}; + +#define nl80211_plink_actions_str(_a) ((_a < NUM_NL80211_PLINK_ACTIONS) ? _nl80211_plink_actions_str[_a] : _nl80211_plink_actions_str[NUM_NL80211_PLINK_ACTIONS]) + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) +const char *_nl80211_mesh_power_mode_str[] = { + "UNKNOWN", + "ACTIVE", + "LIGHT_SLEEP", + "DEEP_SLEEP", +}; + +#define nl80211_mesh_power_mode_str(_p) ((_p <= NL80211_MESH_POWER_MAX) ? _nl80211_mesh_power_mode_str[_p] : _nl80211_mesh_power_mode_str[0]) +#endif + +void dump_station_parameters(void *sel, struct wiphy *wiphy, const struct station_parameters *params) +{ +#if DBG_RTW_CFG80211_STA_PARAM + if (params->supported_rates_len) { + #define SUPP_RATES_BUF_LEN (3 * RTW_G_RATES_NUM + 1) + int i; + char supp_rates_buf[SUPP_RATES_BUF_LEN] = {0}; + u8 cnt = 0; + + rtw_warn_on(params->supported_rates_len > RTW_G_RATES_NUM); + + for (i = 0; i < params->supported_rates_len; i++) { + if (i >= RTW_G_RATES_NUM) + break; + cnt += snprintf(supp_rates_buf + cnt, SUPP_RATES_BUF_LEN - cnt -1 + , "%02X ", params->supported_rates[i]); + if (cnt >= SUPP_RATES_BUF_LEN - 1) + break; + } + + RTW_PRINT_SEL(sel, "supported_rates:%s\n", supp_rates_buf); + } + + if (params->vlan) + RTW_PRINT_SEL(sel, "vlan:"NDEV_FMT"\n", NDEV_ARG(params->vlan)); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) + if (params->sta_flags_mask) { + #define STA_FLAGS_BUF_LEN 128 + int i = 0; + char sta_flags_buf[STA_FLAGS_BUF_LEN] = {0}; + u8 cnt = 0; + + for (i = 1; i <= NL80211_STA_FLAG_MAX; i++) { + if (params->sta_flags_mask & BIT(i)) { + cnt += snprintf(sta_flags_buf + cnt, STA_FLAGS_BUF_LEN - cnt -1, "%s=%u " + , nl80211_sta_flags_str(i), (params->sta_flags_set & BIT(i)) >> i); + if (cnt >= STA_FLAGS_BUF_LEN - 1) + break; + } + } + + RTW_PRINT_SEL(sel, "sta_flags:%s\n", sta_flags_buf); + } +#else + u32 station_flags; + #error "TBD\n" +#endif + + if (params->listen_interval != -1) + RTW_PRINT_SEL(sel, "listen_interval:%d\n", params->listen_interval); + + if (params->aid) + RTW_PRINT_SEL(sel, "aid:%u\n", params->aid); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)) + if (params->peer_aid) + RTW_PRINT_SEL(sel, "peer_aid:%u\n", params->peer_aid); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) + if (params->plink_action != NL80211_PLINK_ACTION_NO_ACTION) + RTW_PRINT_SEL(sel, "plink_action:%s\n", nl80211_plink_actions_str(params->plink_action)); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + if (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE) + #endif + RTW_PRINT_SEL(sel, "plink_state:%s\n" + , nl80211_plink_state_str(params->plink_state)); +#endif + +#if 0 /* TODO */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) + const struct ieee80211_ht_cap *ht_capa; +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + const struct ieee80211_vht_cap *vht_capa; +#endif +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + if (params->sta_modify_mask & STATION_PARAM_APPLY_UAPSD) + RTW_PRINT_SEL(sel, "uapsd_queues:0x%02x\n", params->uapsd_queues); + if (params->max_sp) + RTW_PRINT_SEL(sel, "max_sp:%u\n", params->max_sp); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + if (params->local_pm != NL80211_MESH_POWER_UNKNOWN) { + RTW_PRINT_SEL(sel, "local_pm:%s\n" + , nl80211_mesh_power_mode_str(params->local_pm)); + } + + if (params->sta_modify_mask & STATION_PARAM_APPLY_CAPABILITY) + RTW_PRINT_SEL(sel, "capability:0x%04x\n", params->capability); + +#if 0 /* TODO */ + const u8 *ext_capab; + u8 ext_capab_len; +#endif +#endif + +#if 0 /* TODO */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)) + const u8 *supported_channels; + u8 supported_channels_len; + const u8 *supported_oper_classes; + u8 supported_oper_classes_len; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) + u8 opmode_notif; + bool opmode_notif_used; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) + int support_p2p_ps; +#endif +#endif +#endif /* DBG_RTW_CFG80211_STA_PARAM */ +} + static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev, #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)) u8 *mac, @@ -4309,12 +5036,133 @@ static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev struct station_parameters *params) { int ret = 0; -#ifdef CONFIG_TDLS _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct sta_priv *pstapriv = &padapter->stapriv; +#ifdef CONFIG_TDLS struct sta_info *psta; #endif /* CONFIG_TDLS */ - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + RTW_INFO(FUNC_NDEV_FMT" mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac)); + +#if CONFIG_RTW_MACADDR_ACL + if (rtw_access_ctrl(padapter, mac) == _FALSE) { + RTW_INFO(FUNC_NDEV_FMT" deny by macaddr ACL\n", FUNC_NDEV_ARG(ndev)); + ret = -EINVAL; + goto exit; + } +#endif + + dump_station_parameters(RTW_DBGDUMP, wiphy, params); + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + struct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg; + struct rtw_mesh_info *minfo = &padapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *plink = NULL; + struct wlan_network *scanned = NULL; + u8 add_new_sta = 0, probe_req = 0; + _irqL irqL; + + if (params->plink_state != NL80211_PLINK_LISTEN) { + RTW_WARN(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(ndev), nl80211_plink_state_str(params->plink_state)); + rtw_warn_on(1); + } + if (!params->aid || params->aid > pstapriv->max_aid) { + RTW_WARN(FUNC_NDEV_FMT" invalid aid:%u\n", FUNC_NDEV_ARG(ndev), params->aid); + rtw_warn_on(1); + ret = -EINVAL; + goto exit; + } + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + + plink = _rtw_mesh_plink_get(padapter, mac); + if (plink) + goto release_plink_ctl; + + #if CONFIG_RTW_MESH_PEER_BLACKLIST + if (rtw_mesh_peer_blacklist_search(padapter, mac)) { + RTW_INFO(FUNC_NDEV_FMT" deny by peer blacklist\n" + , FUNC_NDEV_ARG(ndev)); + ret = -EINVAL; + goto release_plink_ctl; + } + #endif + + /* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */ + if (plink_ctl->num >= mcfg->max_peer_links) { + RTW_INFO(FUNC_NDEV_FMT" exceed max_peer_links:%u\n" + , FUNC_NDEV_ARG(ndev), mcfg->max_peer_links); + ret = -EINVAL; + goto release_plink_ctl; + } + + scanned = rtw_find_network(&padapter->mlmepriv.scanned_queue, mac); + if (!scanned + || rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms + ) { + if (!scanned) + RTW_INFO(FUNC_NDEV_FMT" corresponding network not found\n", FUNC_NDEV_ARG(ndev)); + else + RTW_INFO(FUNC_NDEV_FMT" corresponding network too old\n", FUNC_NDEV_ARG(ndev)); + + if (adapter_to_rfctl(padapter)->offch_state == OFFCHS_NONE) + probe_req = 1; + + ret = -EINVAL; + goto release_plink_ctl; + } + + if (!rtw_bss_is_candidate_mesh_peer(&padapter->mlmepriv.cur_network.network, &scanned->network, 1, 1)){ + RTW_WARN(FUNC_NDEV_FMT" corresponding network is not candidate with same ch\n" + , FUNC_NDEV_ARG(ndev)); + ret = -EINVAL; + goto release_plink_ctl; + } + + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + if (!rtw_mesh_cto_mgate_network_filter(padapter, scanned)) { + RTW_INFO(FUNC_NDEV_FMT" peer filtered out by cto_mgate check\n" + , FUNC_NDEV_ARG(ndev)); + ret = -EINVAL; + goto release_plink_ctl; + } + #endif + + if (_rtw_mesh_plink_add(padapter, mac) == _SUCCESS) { + /* hook corresponding network in scan queue */ + plink = _rtw_mesh_plink_get(padapter, mac); + plink->aid = params->aid; + plink->scanned = scanned; + + add_new_sta = 1; + } else { + RTW_WARN(FUNC_NDEV_FMT" rtw_mesh_plink_add not success\n" + , FUNC_NDEV_ARG(ndev)); + ret = -EINVAL; + } +release_plink_ctl: + _exit_critical_bh(&(plink_ctl->lock), &irqL); + + if (probe_req) + issue_probereq(padapter, &padapter->mlmepriv.cur_network.network.mesh_id, mac); + + if (add_new_sta) { + struct station_info sinfo; + + #ifdef CONFIG_DFS_MASTER + if (IS_UNDER_CAC(adapter_to_rfctl(padapter))) + rtw_force_stop_cac(padapter, 300); + #endif + + /* indicate new sta */ + _rtw_memset(&sinfo, 0, sizeof(sinfo)); + cfg80211_new_sta(ndev, mac, &sinfo, GFP_ATOMIC); + } + goto exit; + } +#endif /* CONFIG_RTW_MESH */ #ifdef CONFIG_TDLS psta = rtw_get_stainfo(pstapriv, (u8 *)mac); @@ -4352,17 +5200,16 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct sta_priv *pstapriv = &padapter->stapriv; - RTW_INFO("+"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); - - #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)) target_mac = mac; #else target_mac = params->mac; #endif - if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE) { - RTW_INFO("%s, fw_state != FW_LINKED|WIFI_AP_STATE\n", __func__); + RTW_INFO("+"FUNC_NDEV_FMT" mac=%pM\n", FUNC_NDEV_ARG(ndev), target_mac); + + if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE)) != _TRUE) { + RTW_INFO("%s, fw_state != FW_LINKED|WIFI_AP_STATE|WIFI_MESH_STATE\n", __func__); return -EINVAL; } @@ -4372,8 +5219,9 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev flush_all_cam_entry(padapter); /* clear CAM */ +#ifdef CONFIG_AP_MODE ret = rtw_sta_flush(padapter, _TRUE); - +#endif return ret; } @@ -4397,17 +5245,18 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev plist = get_next(plist); - if (_rtw_memcmp((u8 *)target_mac, psta->hwaddr, ETH_ALEN)) { + if (_rtw_memcmp((u8 *)target_mac, psta->cmn.mac_addr, ETH_ALEN)) { if (psta->dot8021xalg == 1 && psta->bpairwise_key_installed == _FALSE) RTW_INFO("%s, sta's dot8021xalg = 1 and key_installed = _FALSE\n", __func__); else { - RTW_INFO("free psta=%p, aid=%d\n", psta, psta->aid); + RTW_INFO("free psta=%p, aid=%d\n", psta, psta->cmn.aid); rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; + STA_SET_MESH_PLINK(psta, NULL); /* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */ - if (check_fwstate(pmlmepriv, (WIFI_AP_STATE)) == _TRUE) + if (MLME_IS_AP(padapter)) updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE); else updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); @@ -4426,6 +5275,11 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_mesh_plink_del(padapter, target_mac); +#endif + RTW_INFO("-"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); return ret; @@ -4440,15 +5294,95 @@ static int cfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *n #endif struct station_parameters *params) { - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sta = NULL; + _irqL irqL; + int ret = 0; - return 0; -} + RTW_INFO(FUNC_NDEV_FMT" mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac)); -struct sta_info *rtw_sta_info_get_by_idx(const int idx, struct sta_priv *pstapriv) + dump_station_parameters(RTW_DBGDUMP, wiphy, params); -{ +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + enum cfg80211_station_type sta_type = CFG80211_STA_MESH_PEER_USER; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *plink = NULL; + _irqL irqL2; + + ret = cfg80211_check_station_change(wiphy, params, sta_type); + if (ret) { + RTW_INFO("cfg80211_check_station_change return %d\n", ret); + goto exit; + } + + _enter_critical_bh(&(plink_ctl->lock), &irqL2); + + plink = _rtw_mesh_plink_get(adapter, mac); + if (!plink) { + ret = -ENOENT; + goto release_plink_ctl; + } + + plink->plink_state = nl80211_plink_state_to_rtw_plink_state(params->plink_state); + + if ((params->plink_state == NL80211_PLINK_OPN_RCVD + || params->plink_state == NL80211_PLINK_CNF_RCVD + || params->plink_state == NL80211_PLINK_ESTAB) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + && (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE) + #endif + ) { + sta = rtw_get_stainfo(stapriv, mac); + if (!sta) { + sta = rtw_alloc_stainfo(stapriv, mac); + if (!sta) + goto release_plink_ctl; + } + + if (params->plink_state == NL80211_PLINK_ESTAB) { + if (rtw_mesh_peer_establish(adapter, plink, sta) != _SUCCESS) { + rtw_free_stainfo(adapter, sta); + ret = -ENOENT; + goto release_plink_ctl; + } + } + } + else if (params->plink_state == NL80211_PLINK_HOLDING + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + && (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE) + #endif + ) { + u8 updated = _FALSE; + + sta = rtw_get_stainfo(stapriv, mac); + if (!sta) + goto release_plink_ctl; + + _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + if (!rtw_is_list_empty(&sta->asoc_list)) { + rtw_list_delete(&sta->asoc_list); + stapriv->asoc_list_cnt--; + STA_SET_MESH_PLINK(sta, NULL); + } + _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + updated = ap_free_sta(adapter, sta, 0, 0, 1); + associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL); + } + +release_plink_ctl: + _exit_critical_bh(&(plink_ctl->lock), &irqL2); + } +#endif /* CONFIG_RTW_MESH */ + +exit: + return ret; +} +struct sta_info *rtw_sta_info_get_by_idx(struct sta_priv *pstapriv, const int idx, u8 *asoc_list_num) +{ _list *phead, *plist; struct sta_info *psta = NULL; int i = 0; @@ -4463,32 +5397,75 @@ struct sta_info *rtw_sta_info_get_by_idx(const int idx, struct sta_priv *pstapri plist = get_next(plist); i++; } + + if (asoc_list_num) + *asoc_list_num = i; + return psta; } static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *ndev, int idx, u8 *mac, struct station_info *sinfo) { +#define DBG_DUMP_STATION 0 int ret = 0; _irqL irqL; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); - struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + struct sta_info *psta = NULL; +#ifdef CONFIG_RTW_MESH + struct mesh_plink_ent *plink = NULL; +#endif + u8 asoc_list_num; + + if (DBG_DUMP_STATION) + RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); - psta = rtw_sta_info_get_by_idx(idx, pstapriv); + psta = rtw_sta_info_get_by_idx(pstapriv, idx, &asoc_list_num); _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - if (NULL == psta) { - RTW_INFO("Station is not found\n"); + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + if (!psta) + plink = rtw_mesh_plink_get_no_estab_by_idx(padapter, idx - asoc_list_num); + else + plink = psta->plink; + } +#endif /* CONFIG_RTW_MESH */ + + if (!psta + #ifdef CONFIG_RTW_MESH + && !plink + #endif + ) { + if (DBG_DUMP_STATION) + RTW_INFO(FUNC_NDEV_FMT" end with idx:%d\n", FUNC_NDEV_ARG(ndev), idx); ret = -ENOENT; goto exit; } - _rtw_memcpy(mac, psta->hwaddr, ETH_ALEN); + + if (psta) + _rtw_memcpy(mac, psta->cmn.mac_addr, ETH_ALEN); + #ifdef CONFIG_RTW_MESH + else + _rtw_memcpy(mac, plink->addr, ETH_ALEN); + #endif + sinfo->filled = 0; - sinfo->filled |= STATION_INFO_SIGNAL; - sinfo->signal = psta->rssi; + + if (psta) { + sinfo->filled |= STATION_INFO_SIGNAL; + sinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi); + sinfo->filled |= STATION_INFO_INACTIVE_TIME; + sinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time); + } + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_cfg80211_fill_mesh_only_sta_info(plink, psta, sinfo); +#endif exit: return ret; @@ -4553,7 +5530,10 @@ static int cfg80211_rtw_set_channel(struct wiphy *wiphy break; } - set_channel_bwmode(padapter, chan_target, chan_offset, chan_width); + RTW_INFO(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d\n" + , FUNC_ADPT_ARG(padapter), chan_target, chan_width, chan_offset); + + rtw_set_chbw_cmd(padapter, chan_target, chan_width, chan_offset, RTW_CMDF_WAIT_ACK); return 0; } @@ -4649,8 +5629,10 @@ static int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy break; } #endif + RTW_INFO(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d\n" + , FUNC_ADPT_ARG(padapter), target_channal, target_width, target_offset); - set_channel_bwmode(padapter, target_channal, target_offset, target_width); + rtw_set_chbw_cmd(padapter, target_channal, target_width, target_offset, RTW_CMDF_WAIT_ACK); return 0; } @@ -4685,7 +5667,8 @@ void rtw_cfg80211_rx_probe_request(_adapter *adapter, union recv_frame *rframe) freq = rtw_ch2freq(ch); #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("RTW_Rx: probe request, ch=%d(%d)\n", ch, sch); + RTW_INFO("RTW_Rx: probe request, ch=%d(%d), ta="MAC_FMT"\n" + , ch, sch, MAC_ARG(get_addr2_ptr(frame))); #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) @@ -4708,7 +5691,8 @@ void rtw_cfg80211_rx_action_p2p(_adapter *adapter, union recv_frame *rframe) ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; freq = rtw_ch2freq(ch); - RTW_INFO("RTW_Rx:ch=%d(%d)\n", ch, sch); + RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n" + , ch, sch, MAC_ARG(get_addr2_ptr(frame))); #ifdef CONFIG_P2P type = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE); if (type >= 0) @@ -4741,7 +5725,8 @@ void rtw_cfg80211_rx_p2p_action_public(_adapter *adapter, union recv_frame *rfra ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; freq = rtw_ch2freq(ch); - RTW_INFO("RTW_Rx:ch=%d(%d)\n", ch, sch); + RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n" + , ch, sch, MAC_ARG(get_addr2_ptr(frame))); #ifdef CONFIG_P2P type = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE); if (type >= 0) { @@ -4803,52 +5788,118 @@ void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const c s32 freq; u8 ch, sch = rtw_get_oper_ch(adapter); u8 category, action; + int type = -1; ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; freq = rtw_ch2freq(ch); - rtw_action_frame_parse(frame, frame_len, &category, &action); + RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n" + , ch, sch, MAC_ARG(get_addr2_ptr(frame))); - if (action == ACT_PUBLIC_GAS_INITIAL_REQ) { - rtw_mi_set_scan_deny(adapter, 200); - rtw_mi_scan_abort(adapter, _FALSE); /*rtw_scan_abort_no_wait*/ +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + type = rtw_mesh_check_frames_rx(adapter, frame, frame_len); + if (type >= 0) + goto indicate; + } +#endif + rtw_action_frame_parse(frame, frame_len, &category, &action); + if (category == RTW_WLAN_CATEGORY_PUBLIC) { + if (action == ACT_PUBLIC_GAS_INITIAL_REQ) { + rtw_mi_set_scan_deny(adapter, 200); + rtw_mi_scan_abort(adapter, _FALSE); /*rtw_scan_abort_no_wait*/ + } } +indicate: #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); #else cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); #endif - RTW_INFO("RTW_Rx:ch=%d(%d)\n", ch, sch); - if (msg) - RTW_INFO("RTW_Rx:%s\n", msg); - else - RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action); + if (type == -1) { + if (msg) + RTW_INFO("RTW_Rx:%s\n", msg); + else + RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action); + } } -#ifdef CONFIG_P2P -void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len) +#ifdef CONFIG_RTW_80211K +void rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe) { - u16 wps_devicepassword_id = 0x0000; - uint wps_devicepassword_id_len = 0; - u8 wpsie[255] = { 0x00 }, p2p_ie[255] = { 0x00 }; - uint p2p_ielen = 0; - uint wpsielen = 0; - u32 devinfo_contentlen = 0; - u8 devinfo_content[64] = { 0x00 }; - u16 capability = 0; - uint capability_len = 0; - - unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; - u8 action = P2P_PUB_ACTION_ACTION; - u8 dialogToken = 1; - u32 p2poui = cpu_to_be32(P2POUI); - u8 oui_subtype = P2P_PROVISION_DISC_REQ; - u32 p2pielen = 0; -#ifdef CONFIG_WFD - u32 wfdielen = 0; -#endif + struct wireless_dev *wdev = adapter->rtw_wdev; + u8 *frame = get_recvframe_data(rframe); + uint frame_len = rframe->u.hdr.len; + s32 freq; + u8 ch, sch = rtw_get_oper_ch(adapter); + + ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; + freq = rtw_ch2freq(ch); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); +#else + cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); +#endif + RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n" + , ch, sch, MAC_ARG(get_addr2_ptr(frame))); +} +#endif /* CONFIG_RTW_80211K */ + +void rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const char *msg) +{ + struct wireless_dev *wdev = adapter->rtw_wdev; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); + u8 *frame = get_recvframe_data(rframe); + uint frame_len = rframe->u.hdr.len; + s32 freq; + u8 ch, sch = rtw_get_oper_ch(adapter); + + ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; + freq = rtw_ch2freq(ch); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); +#else + cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); +#endif + + RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n", ch, sch, MAC_ARG(get_addr2_ptr(frame))); + #ifdef CONFIG_RTW_MESH + if (!rtw_sae_check_frames(adapter, frame, frame_len, _FALSE)) + #endif + { + if (msg) + RTW_INFO("RTW_Rx:%s\n", msg); + else + RTW_INFO("RTW_Rx:frame_control:0x%02x\n", le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)rframe)->frame_ctl)); + } +} + +#ifdef CONFIG_P2P +void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len) +{ + u16 wps_devicepassword_id = 0x0000; + uint wps_devicepassword_id_len = 0; + u8 wpsie[255] = { 0x00 }, p2p_ie[255] = { 0x00 }; + uint p2p_ielen = 0; + uint wpsielen = 0; + u32 devinfo_contentlen = 0; + u8 devinfo_content[64] = { 0x00 }; + u16 capability = 0; + uint capability_len = 0; + + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u8 dialogToken = 1; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_PROVISION_DISC_REQ; + u32 p2pielen = 0; +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; @@ -5058,7 +6109,7 @@ static s32 cfg80211_rtw_update_ft_ies(struct wiphy *wiphy, { _adapter *padapter = NULL; struct mlme_priv *pmlmepriv = NULL; - ft_priv *pftpriv = NULL; + struct ft_roam_info *pft_roam = NULL; _irqL irqL; u8 *p; u8 *pie = NULL; @@ -5069,24 +6120,22 @@ static s32 cfg80211_rtw_update_ft_ies(struct wiphy *wiphy, padapter = (_adapter *)rtw_netdev_priv(ndev); pmlmepriv = &(padapter->mlmepriv); - pftpriv = &pmlmepriv->ftpriv; + pft_roam = &(pmlmepriv->ft_roam); p = (u8 *)ftie->ie; - if (ftie->ie_len <= sizeof(pftpriv->updated_ft_ies)) { + if (ftie->ie_len <= sizeof(pft_roam->updated_ft_ies)) { _enter_critical_bh(&pmlmepriv->lock, &irqL); - _rtw_memcpy(pftpriv->updated_ft_ies, ftie->ie, ftie->ie_len); - pftpriv->updated_ft_ies_len = ftie->ie_len; + _rtw_memcpy(pft_roam->updated_ft_ies, ftie->ie, ftie->ie_len); + pft_roam->updated_ft_ies_len = ftie->ie_len; _exit_critical_bh(&pmlmepriv->lock, &irqL); } else { RTW_ERR("FTIEs parsing fail!\n"); return -EINVAL; } - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_status(padapter, RTW_FT_AUTHENTICATED_STA)) { + if (rtw_ft_roam_status(padapter, RTW_FT_AUTHENTICATED_STA)) { RTW_PRINT("auth success, start reassoc\n"); - _enter_critical_bh(&pmlmepriv->lock, &irqL); - rtw_set_ft_status(padapter, RTW_FT_ASSOCIATING_STA); - _exit_critical_bh(&pmlmepriv->lock, &irqL); + rtw_ft_lock_set_status(padapter, RTW_FT_ASSOCIATING_STA, &irqL); start_clnt_assoc(padapter); } @@ -5105,6 +6154,24 @@ inline bool rtw_cfg80211_get_is_roch(_adapter *adapter) return adapter->cfg80211_wdinfo.is_ro_ch; } +inline bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter) +{ + return adapter->cfg80211_wdinfo.last_ro_ch_time ? 1 : 0; +} + +inline void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter) +{ + adapter->cfg80211_wdinfo.last_ro_ch_time = rtw_get_current_time(); + + if (!adapter->cfg80211_wdinfo.last_ro_ch_time) + adapter->cfg80211_wdinfo.last_ro_ch_time++; +} + +inline s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter) +{ + return rtw_get_passing_time_ms(adapter->cfg80211_wdinfo.last_ro_ch_time); +} + static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) struct wireless_dev *wdev, @@ -5121,21 +6188,12 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, u8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq); u8 union_ch = 0, union_bw = 0, union_offset = 0; u8 i; - u8 ready_on_channel = _FALSE; _adapter *padapter = NULL; - _adapter *iface; - struct dvobj_priv *dvobj; struct rtw_wdev_priv *pwdev_priv; - struct mlme_ext_priv *pmlmeext; struct wifidirect_info *pwdinfo; struct cfg80211_wifidirect_info *pcfg80211_wdinfo; u8 is_p2p_find = _FALSE; -#ifndef CONFIG_RADIO_WORK -#define RTW_ROCH_DURATION_ENLARGE -#define RTW_ROCH_BACK_OP -#endif - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) #if defined(RTW_DEDICATED_P2P_DEVICE) if (wdev == wiphy_to_pd_wdev(wiphy)) @@ -5159,9 +6217,7 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, wdev = ndev_to_wdev(ndev); #endif - dvobj = adapter_to_dvobj(padapter); pwdev_priv = adapter_wdev_data(padapter); - pmlmeext = &padapter->mlmeextpriv; pwdinfo = &padapter->wdinfo; pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; #ifdef CONFIG_CONCURRENT_MODE @@ -5212,7 +6268,7 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, RTW_INFO(FUNC_ADPT_FMT" init listen_channel %u\n" , FUNC_ADPT_ARG(padapter), padapter->wdinfo.listen_channel); } else if (rtw_p2p_chk_state(pwdinfo , P2P_STATE_LISTEN) - && (time_after_eq((unsigned long)rtw_get_current_time(), (unsigned long)pwdev_priv->probe_resp_ie_update_time) + && (time_after_eq(rtw_get_current_time(), pwdev_priv->probe_resp_ie_update_time) && rtw_get_passing_time_ms(pwdev_priv->probe_resp_ie_update_time) < 50) ) { if (padapter->wdinfo.listen_channel != remain_ch) { @@ -5222,17 +6278,9 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, } } else { rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); - #ifdef CONFIG_DEBUG_CFG80211 +#ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); - #endif - } - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS) == _TRUE) { - RTW_INFO(ADPT_FMT"- _FW_UNDER_LINKING |WIFI_UNDER_WPS (mlme state:0x%x)\n", ADPT_ARG(iface), get_fwstate(&iface->mlmepriv)); - remain_ch = iface->mlmeextpriv.cur_channel; - } +#endif } rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); @@ -5254,65 +6302,17 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, rtw_cfg80211_set_is_roch(padapter, _TRUE); pcfg80211_wdinfo->ro_ch_wdev = wdev; pcfg80211_wdinfo->remain_on_ch_cookie = *cookie; - pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); + rtw_cfg80211_set_last_ro_ch_time(padapter); _rtw_memcpy(&pcfg80211_wdinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel)); #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) pcfg80211_wdinfo->remain_on_ch_type = channel_type; #endif pcfg80211_wdinfo->restore_channel = rtw_get_oper_ch(padapter); -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) && (0 != rtw_mi_get_union_chan(padapter))) { - if ((remain_ch != rtw_mi_get_union_chan(padapter)) && !check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { - if ( -#ifdef RTW_ROCH_BACK_OP - ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1 || -#endif - (remain_ch != pmlmeext->cur_channel)) { - #ifdef CONFIG_AP_MODE - /*mac-id sleep or wake-up for AP mode*/ - rtw_mi_buddy_ap_acdata_control(padapter, 1); - #endif/*CONFIG_AP_MODE*/ - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); - #ifdef RTW_ROCH_BACK_OP - RTW_INFO("%s, set switch ch timer, duration=%d\n", __func__, duration - pwdinfo->ext_listen_interval); - ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); - _set_timer(&pwdinfo->ap_p2p_switch_timer, duration - pwdinfo->ext_listen_interval); - #endif - } - } - ready_on_channel = _TRUE; - } else -#endif /* CONFIG_CONCURRENT_MODE */ - { - if (remain_ch != rtw_get_oper_ch(padapter)) - ready_on_channel = _TRUE; - } - - if (ready_on_channel == _TRUE) { - #ifndef RTW_SINGLE_WIPHY - if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) - #endif - { - #ifdef CONFIG_CONCURRENT_MODE - if (rtw_get_oper_ch(padapter) != remain_ch) - #endif - { - /* if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic) */ - set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - } - } - } - -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_ScanNotify(padapter, _TRUE); -#endif - - RTW_INFO("%s, set ro ch timer, duration=%d\n", __func__, duration); - _set_timer(&pcfg80211_wdinfo->remain_on_ch_timer, duration); + p2p_roch_cmd(padapter, *cookie, wdev, channel, pcfg80211_wdinfo->remain_on_ch_type, + duration, RTW_CMDF_WAIT_ACK); rtw_cfg80211_ready_on_channel(wdev, *cookie, channel, channel_type, duration, GFP_KERNEL); - exit: return err; } @@ -5576,14 +6576,12 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - + u8 u_ch = rtw_mi_get_union_chan(padapter); + u8 leave_op = 0; #ifdef CONFIG_P2P + struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; struct wifidirect_info *pwdinfo = &padapter->wdinfo; -#endif /* CONFIG_P2P */ - /* struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; */ - - rtw_mi_set_scan_deny(padapter, 1000); - rtw_mi_scan_abort(padapter, _TRUE); +#endif rtw_cfg80211_set_is_mgmt_tx(padapter, 1); @@ -5610,50 +6608,31 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const } #endif /* CONFIG_MCC_MODE */ -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) { - u8 union_ch = rtw_mi_get_union_chan(padapter); - u8 co_channel = 0xff; - co_channel = rtw_get_oper_ch(padapter); + if (rtw_mi_check_status(padapter, MI_LINKED) + && tx_ch != u_ch + ) { + rtw_leave_opch(padapter); + leave_op = 1; - if (tx_ch != union_ch) { + #if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE) + if (rtw_cfg80211_get_is_roch(padapter) + && ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1 + ) { u16 ext_listen_period; - if (ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1) { - #ifdef CONFIG_AP_MODE - /*mac-id sleep or wake-up for AP mode*/ - rtw_mi_buddy_ap_acdata_control(padapter, 1); - #endif/*CONFIG_AP_MODE*/ - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); - ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); - /* RTW_INFO("%s, set switch ch timer, period=%d\n", __func__, pwdinfo->ext_listen_period); */ - /* _set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period); */ - } - if (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) - ext_listen_period = 500;/*500ms*/ -#ifdef CONFIG_P2P + ext_listen_period = 500; else ext_listen_period = pwdinfo->ext_listen_period; - + ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); _set_timer(&pwdinfo->ap_p2p_switch_timer, ext_listen_period); -#endif RTW_INFO("%s, set switch ch timer, period=%d\n", __func__, ext_listen_period); } + #endif /* RTW_ROCH_BACK_OP && CONFIG_P2P && CONFIG_CONCURRENT_MODE */ + } - if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) - pmlmeext->cur_channel = tx_ch; - - if (tx_ch != co_channel) - set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - } else -#endif /* CONFIG_CONCURRENT_MODE */ - /* if (tx_ch != pmlmeext->cur_channel) { */ - if (tx_ch != rtw_get_oper_ch(padapter)) { - if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) - pmlmeext->cur_channel = tx_ch; + if (tx_ch != rtw_get_oper_ch(padapter)) set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - } issue_mgmt_frame: /* starting alloc mgmt frame to dump it */ @@ -5706,7 +6685,8 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const } else { #ifdef CONFIG_XMIT_ACK - rtw_msleep_os(50); + if (!MLME_IS_MESH(padapter)) /* TODO: remove this sleep for all mode */ + rtw_msleep_os(50); #endif #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s, ack=%d, ok!\n", __func__, ack); @@ -5717,7 +6697,29 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const dump_mgntframe(padapter, pmgntframe); ret = _SUCCESS; } + exit: + #ifdef CONFIG_P2P + if (rtw_cfg80211_get_is_roch(padapter) + && !roch_stay_in_cur_chan(padapter) + && pcfg80211_wdinfo->remain_on_ch_channel.hw_value != u_ch + ) { + /* roch is ongoing, switch back to rch */ + if (pcfg80211_wdinfo->remain_on_ch_channel.hw_value != tx_ch) + set_channel_bwmode(padapter, pcfg80211_wdinfo->remain_on_ch_channel.hw_value + , HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } else + #endif + if (leave_op) { + if (rtw_mi_check_status(padapter, MI_LINKED)) { + u8 u_bw = rtw_mi_get_union_bw(padapter); + u8 u_offset = rtw_mi_get_union_offset(padapter); + + set_channel_bwmode(padapter, u_ch, u_offset, u_bw); + } + rtw_back_opch(padapter); + } + rtw_cfg80211_set_is_mgmt_tx(padapter, 0); #ifdef CONFIG_BT_COEXIST @@ -5732,6 +6734,18 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const } +u8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf) +{ + u8 rst = H2C_CMD_FAIL; + struct mgnt_tx_parm *mgnt_parm = (struct mgnt_tx_parm *)buf; + + if (_cfg80211_rtw_mgmt_tx(adapter, mgnt_parm->tx_ch, mgnt_parm->no_cck, + mgnt_parm->buf, mgnt_parm->len, mgnt_parm->wait_ack) == _SUCCESS) + rst = H2C_SUCCESS; + + return rst; +} + static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) struct wireless_dev *wdev, @@ -5777,19 +6791,27 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, bool no_cck = 0; #endif int ret = 0; - int tx_ret; + u8 tx_ret; int wait_ack = 1; + const u8 *dump_buf = buf; + size_t dump_len = len; u32 dump_limit = RTW_MAX_MGMT_TX_CNT; u32 dump_cnt = 0; + u32 sleep_ms = 0; + u32 retry_guarantee_ms = 0; bool ack = _TRUE; u8 tx_ch; u8 category, action; u8 frame_styp; +#ifdef CONFIG_P2P + u8 is_p2p = 0; +#endif int type = (-1); - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); _adapter *padapter; struct dvobj_priv *dvobj; struct rtw_wdev_priv *pwdev_priv; + struct rf_ctl_t *rfctl; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) #if defined(RTW_DEDICATED_P2P_DEVICE) @@ -5819,13 +6841,22 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, goto exit; } + rfctl = adapter_to_rfctl(padapter); tx_ch = (u8)ieee80211_frequency_to_channel(chan->center_freq); + if (IS_CH_WAITING(rfctl)) { + #ifdef CONFIG_DFS_MASTER + if (_rtw_rfctl_overlap_radar_detect_ch(rfctl, tx_ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE)) { + ret = -EINVAL; + goto exit; + } + #endif + } dvobj = adapter_to_dvobj(padapter); pwdev_priv = adapter_wdev_data(padapter); /* cookie generation */ - *cookie = (unsigned long) buf; + *cookie = pwdev_priv->mgmt_tx_cookie++; #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO(FUNC_ADPT_FMT"%s len=%zu, ch=%d" @@ -5861,9 +6892,18 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, wait_ack = 0; goto dump; } +#ifdef CONFIG_RTW_MESH + else if (frame_styp == RTW_IEEE80211_STYPE_AUTH) { + RTW_INFO("RTW_Tx:tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf))); + if (!rtw_sae_check_frames(padapter, buf, len, _TRUE)) + RTW_INFO("RTW_Tx:AUTH\n"); + dump_limit = 1; + goto dump; + } +#endif if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) { - RTW_INFO(FUNC_ADPT_FMT" frame_control:0x%x\n", FUNC_ADPT_ARG(padapter), + RTW_INFO(FUNC_ADPT_FMT" frame_control:0x%02x\n", FUNC_ADPT_ARG(padapter), le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl)); goto exit; } @@ -5872,12 +6912,34 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, #ifdef CONFIG_P2P type = rtw_p2p_check_frames(padapter, buf, len, _TRUE); if (type >= 0) { + is_p2p = 1; no_cck = 1; /* force no CCK for P2P frames */ goto dump; } #endif - if (category == RTW_WLAN_CATEGORY_PUBLIC) +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + type = rtw_mesh_check_frames_tx(padapter, &dump_buf, &dump_len); + if (type >= 0) { + dump_limit = 1; + goto dump; + } + } +#endif + if (category == RTW_WLAN_CATEGORY_PUBLIC) { RTW_INFO("RTW_Tx:%s\n", action_public_str(action)); + switch (action) { + case ACT_PUBLIC_GAS_INITIAL_REQ: + case ACT_PUBLIC_GAS_INITIAL_RSP: + sleep_ms = 50; + retry_guarantee_ms = RTW_MAX_MGMT_TX_MS_GAS; + break; + } + } +#ifdef CONFIG_RTW_80211K + else if (category == RTW_WLAN_CATEGORY_RADIO_MEAS) + RTW_INFO("RTW_Tx: RRM Action\n"); +#endif else RTW_INFO("RTW_Tx:category(%u), action(%u)\n", category, action); @@ -5890,19 +6952,11 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, } while (1) { - u32 sleep_ms = 0; - u32 retry_guarantee_ms = 0; - dump_cnt++; - tx_ret = _cfg80211_rtw_mgmt_tx(padapter, tx_ch, no_cck, buf, len, wait_ack); - - switch (action) { - case ACT_PUBLIC_GAS_INITIAL_REQ: - case ACT_PUBLIC_GAS_INITIAL_RSP: - sleep_ms = 50; - retry_guarantee_ms = RTW_MAX_MGMT_TX_MS_GAS; - } + rtw_mi_set_scan_deny(padapter, 1000); + rtw_mi_scan_abort(padapter, _TRUE); + tx_ret = rtw_mgnt_tx_cmd(padapter, tx_ch, no_cck, dump_buf, dump_len, wait_ack, RTW_CMDF_WAIT_ACK); if (tx_ret == _SUCCESS || (dump_cnt >= dump_limit && rtw_get_passing_time_ms(start) >= retry_guarantee_ms)) break; @@ -5916,44 +6970,51 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, tx_ret == _SUCCESS ? "OK" : "FAIL", dump_cnt, dump_limit, rtw_get_passing_time_ms(start)); } - switch (type) { - case P2P_GO_NEGO_CONF: - if (0) { - RTW_INFO(FUNC_ADPT_FMT" Nego confirm. state=%u, status=%u, iaddr="MAC_FMT"\n" - , FUNC_ADPT_ARG(padapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status - , MAC_ARG(pwdev_priv->nego_info.iface_addr)); - } - if (pwdev_priv->nego_info.state == 2 - && pwdev_priv->nego_info.status == 0 - && rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE - ) { - _adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr); - - if (intended_iface) { - RTW_INFO(FUNC_ADPT_FMT" Nego confirm. Allow only "ADPT_FMT" to scan for 2000 ms\n" - , FUNC_ADPT_ARG(padapter), ADPT_ARG(intended_iface)); - /* allow only intended_iface to do scan for 2000 ms */ - rtw_mi_set_scan_deny(padapter, 2000); - rtw_clear_scan_deny(intended_iface); +#ifdef CONFIG_P2P + if (is_p2p) { + switch (type) { + case P2P_GO_NEGO_CONF: + if (0) { + RTW_INFO(FUNC_ADPT_FMT" Nego confirm. state=%u, status=%u, iaddr="MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status + , MAC_ARG(pwdev_priv->nego_info.iface_addr)); } + if (pwdev_priv->nego_info.state == 2 + && pwdev_priv->nego_info.status == 0 + && rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE + ) { + _adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr); + + if (intended_iface) { + RTW_INFO(FUNC_ADPT_FMT" Nego confirm. Allow only "ADPT_FMT" to scan for 2000 ms\n" + , FUNC_ADPT_ARG(padapter), ADPT_ARG(intended_iface)); + /* allow only intended_iface to do scan for 2000 ms */ + rtw_mi_set_scan_deny(padapter, 2000); + rtw_clear_scan_deny(intended_iface); + } + } + break; + case P2P_INVIT_RESP: + if (pwdev_priv->invit_info.flags & BIT(0) + && pwdev_priv->invit_info.status == 0 + ) { + RTW_INFO(FUNC_ADPT_FMT" agree with invitation of persistent group\n", + FUNC_ADPT_ARG(padapter)); + #if !RTW_P2P_GROUP_INTERFACE + rtw_mi_buddy_set_scan_deny(padapter, 5000); + #endif + rtw_pwr_wakeup_ex(padapter, 5000); + } + break; } - break; - case P2P_INVIT_RESP: - if (pwdev_priv->invit_info.flags & BIT(0) - && pwdev_priv->invit_info.status == 0 - ) { - RTW_INFO(FUNC_ADPT_FMT" agree with invitation of persistent group\n", - FUNC_ADPT_ARG(padapter)); - #if !RTW_P2P_GROUP_INTERFACE - rtw_mi_buddy_set_scan_deny(padapter, 5000); - #endif - rtw_pwr_wakeup_ex(padapter, 5000); - } - break; } +#endif /* CONFIG_P2P */ cancel_ps_deny: rtw_ps_deny_cancel(padapter, PS_DENY_MGNT_TX); + + if (dump_buf != buf) + rtw_mfree((u8 *)dump_buf, dump_len); exit: return ret; } @@ -6033,6 +7094,11 @@ static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy, goto discard; } + if (rtw_is_tdls_enabled(padapter) == _FALSE) { + RTW_INFO("TDLS is not enabled\n"); + goto discard; + } + if (rtw_tdls_is_driver_setup(padapter)) { RTW_INFO("Discard tdls action:%d, let driver to set up direct link\n", action_code); goto discard; @@ -6086,94 +7152,1076 @@ static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy, break; } -bad: - if (txmgmt.buf) - rtw_mfree(txmgmt.buf, txmgmt.len); +bad: + if (txmgmt.buf) + rtw_mfree(txmgmt.buf, txmgmt.len); + +discard: + return ret; +} + +static int cfg80211_rtw_tdls_oper(struct wiphy *wiphy, + struct net_device *ndev, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + const u8 *peer, +#else + u8 *peer, +#endif + enum nl80211_tdls_operation oper) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct tdls_txmgmt txmgmt; + struct sta_info *ptdls_sta = NULL; + + RTW_INFO(FUNC_NDEV_FMT", nl80211_tdls_operation:%d\n", FUNC_NDEV_ARG(ndev), oper); + + if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) { + RTW_INFO("Discard tdls oper:%d, since hal doesn't support tdls\n", oper); + return 0; + } + + if (rtw_is_tdls_enabled(padapter) == _FALSE) { + RTW_INFO("TDLS is not enabled\n"); + return 0; + } + +#ifdef CONFIG_LPS + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); +#endif /* CONFIG_LPS */ + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + if (peer) + _rtw_memcpy(txmgmt.peer, peer, ETH_ALEN); + + if (rtw_tdls_is_driver_setup(padapter)) { + /* these two cases are done by driver itself */ + if (oper == NL80211_TDLS_ENABLE_LINK || oper == NL80211_TDLS_DISABLE_LINK) + return 0; + } + + switch (oper) { + case NL80211_TDLS_DISCOVERY_REQ: + issue_tdls_dis_req(padapter, &txmgmt); + break; + case NL80211_TDLS_SETUP: +#ifdef CONFIG_WFD + if (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) { + if (padapter->wdinfo.wfd_tdls_weaksec == _TRUE) + issue_tdls_setup_req(padapter, &txmgmt, _TRUE); + else + RTW_INFO("[%s] Current link is not AES, SKIP sending the tdls setup request!!\n", __FUNCTION__); + } else +#endif /* CONFIG_WFD */ + { + issue_tdls_setup_req(padapter, &txmgmt, _TRUE); + } + break; + case NL80211_TDLS_TEARDOWN: + ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), txmgmt.peer); + if (ptdls_sta != NULL) { + txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; + issue_tdls_teardown(padapter, &txmgmt, _TRUE); + } else + RTW_INFO("TDLS peer not found\n"); + break; + case NL80211_TDLS_ENABLE_LINK: + RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_ENABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer)); + ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer); + if (ptdls_sta != NULL) { + rtw_tdls_set_link_established(padapter, _TRUE); + ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE; + ptdls_sta->state |= _FW_LINKED; + rtw_tdls_cmd(padapter, txmgmt.peer, TDLS_ESTABLISHED); + } + break; + case NL80211_TDLS_DISABLE_LINK: + RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_DISABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer)); + ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer); + if (ptdls_sta != NULL) { + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, (u8 *)peer, TDLS_TEARDOWN_STA_LOCALLY_POST); + } + break; + } + return 0; +} +#endif /* CONFIG_TDLS */ + +#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) + +#if DBG_RTW_CFG80211_MESH_CONF +#define LEGACY_RATES_STR_LEN (RTW_G_RATES_NUM * 5 + 1) +int get_legacy_rates_str(struct wiphy *wiphy, enum nl80211_band band, u32 mask, char *buf) +{ + int i; + int cnt = 0; + + for (i = 0; i < wiphy->bands[band]->n_bitrates; i++) { + if (mask & BIT(i)) { + cnt += snprintf(buf + cnt, LEGACY_RATES_STR_LEN - cnt -1, "%d.%d " + , wiphy->bands[band]->bitrates[i].bitrate / 10 + , wiphy->bands[band]->bitrates[i].bitrate % 10); + if (cnt >= LEGACY_RATES_STR_LEN - 1) + break; + } + } + + return cnt; +} + +void dump_mesh_setup(void *sel, struct wiphy *wiphy, const struct mesh_setup *setup) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef); +#endif + struct ieee80211_channel *chan; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + chan = (struct ieee80211_channel *)chdef->chan; +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + chan = (struct ieee80211_channel *)setup->channel; +#endif + + RTW_PRINT_SEL(sel, "mesh_id:\"%s\", len:%u\n", setup->mesh_id, setup->mesh_id_len); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + RTW_PRINT_SEL(sel, "sync_method:%u\n", setup->sync_method); +#endif + RTW_PRINT_SEL(sel, "path_sel_proto:%u, path_metric:%u\n", setup->path_sel_proto, setup->path_metric); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + RTW_PRINT_SEL(sel, "auth_id:%u\n", setup->auth_id); +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) + if (setup->ie && setup->ie_len) { + RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->ie, setup->ie_len); + dump_ies(RTW_DBGDUMP, setup->ie, setup->ie_len); + } +#else + if (setup->vendor_ie && setup->vendor_ie_len) { + RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->vendor_ie, setup->vendor_ie_len); + dump_ies(RTW_DBGDUMP, setup->vendor_ie, setup->vendor_ie_len); + } +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) + RTW_PRINT_SEL(sel, "is_authenticated:%d, is_secure:%d\n", setup->is_authenticated, setup->is_secure); +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + RTW_PRINT_SEL(sel, "user_mpm:%d\n", setup->user_mpm); +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + RTW_PRINT_SEL(sel, "dtim_period:%u, beacon_interval:%u\n", setup->dtim_period, setup->beacon_interval); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, width:%s, cfreq1:%u, cfreq2:%u\n" + , chan->center_freq, chan->hw_value, nl80211_chan_width_str(chdef->width), chdef->center_freq1, chdef->center_freq2); +#else + RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, channel_type:%s\n" + , chan->center_freq, chan->hw_value, nl80211_channel_type_str(setup->channel_type)); +#endif +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + if (setup->mcast_rate[chan->band]) { + RTW_PRINT_SEL(sel, "mcast_rate:%d.%d\n" + , wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate / 10 + , wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate % 10 + ); + } +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + if (setup->basic_rates) { + char buf[LEGACY_RATES_STR_LEN] = {0}; + + get_legacy_rates_str(wiphy, chan->band, setup->basic_rates, buf); + RTW_PRINT_SEL(sel, "basic_rates:%s\n", buf); + } +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)) + if (setup->beacon_rate.control[chan->band].legacy) { + char buf[LEGACY_RATES_STR_LEN] = {0}; + + get_legacy_rates_str(wiphy, chan->band, setup->beacon_rate.control[chan->band].legacy, buf); + RTW_PRINT_SEL(sel, "beacon_rate.legacy:%s\n", buf); + } + if (*((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[0])) + || *((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[4])) + || *((u16 *)&(setup->beacon_rate.control[chan->band].ht_mcs[8])) + ) { + RTW_PRINT_SEL(sel, "beacon_rate.ht_mcs:"HT_RX_MCS_BMP_FMT"\n" + , HT_RX_MCS_BMP_ARG(setup->beacon_rate.control[chan->band].ht_mcs)); + } + + if (setup->beacon_rate.control[chan->band].vht_mcs[0] + || setup->beacon_rate.control[chan->band].vht_mcs[1] + || setup->beacon_rate.control[chan->band].vht_mcs[2] + || setup->beacon_rate.control[chan->band].vht_mcs[3] + ) { + int i; + + for (i = 0; i < 4; i++) {/* parsing up to 4SS */ + u16 mcs_mask = setup->beacon_rate.control[chan->band].vht_mcs[i]; + + RTW_PRINT_SEL(sel, "beacon_rate.vht_mcs[%d]:%s\n", i + , mcs_mask == 0x00FF ? "0~7" : mcs_mask == 0x01FF ? "0~8" : mcs_mask == 0x03FF ? "0~9" : "invalid"); + } + } + + if (setup->beacon_rate.control[chan->band].gi) { + RTW_PRINT_SEL(sel, "beacon_rate.gi:%s\n" + , setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_SGI ? "SGI" : + setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_LGI ? "LGI" : "invalid" + ); + } +#endif +} + +void dump_mesh_config(void *sel, const struct mesh_config *conf) +{ + RTW_PRINT_SEL(sel, "dot11MeshRetryTimeout:%u\n", conf->dot11MeshRetryTimeout); + RTW_PRINT_SEL(sel, "dot11MeshConfirmTimeout:%u\n", conf->dot11MeshConfirmTimeout); + RTW_PRINT_SEL(sel, "dot11MeshHoldingTimeout:%u\n", conf->dot11MeshHoldingTimeout); + RTW_PRINT_SEL(sel, "dot11MeshMaxPeerLinks:%u\n", conf->dot11MeshMaxPeerLinks); + RTW_PRINT_SEL(sel, "dot11MeshMaxRetries:%u\n", conf->dot11MeshMaxRetries); + RTW_PRINT_SEL(sel, "dot11MeshTTL:%u\n", conf->dot11MeshTTL); + RTW_PRINT_SEL(sel, "element_ttl:%u\n", conf->element_ttl); + RTW_PRINT_SEL(sel, "auto_open_plinks:%d\n", conf->auto_open_plinks); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + RTW_PRINT_SEL(sel, "dot11MeshNbrOffsetMaxNeighbor:%u\n", conf->dot11MeshNbrOffsetMaxNeighbor); +#endif + + RTW_PRINT_SEL(sel, "dot11MeshHWMPmaxPREQretries:%u\n", conf->dot11MeshHWMPmaxPREQretries); + RTW_PRINT_SEL(sel, "path_refresh_time:%u\n", conf->path_refresh_time); + RTW_PRINT_SEL(sel, "min_discovery_timeout:%u\n", conf->min_discovery_timeout); + RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathTimeout:%u\n", conf->dot11MeshHWMPactivePathTimeout); + RTW_PRINT_SEL(sel, "dot11MeshHWMPpreqMinInterval:%u\n", conf->dot11MeshHWMPpreqMinInterval); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + RTW_PRINT_SEL(sel, "dot11MeshHWMPperrMinInterval:%u\n", conf->dot11MeshHWMPperrMinInterval); +#endif + RTW_PRINT_SEL(sel, "dot11MeshHWMPnetDiameterTraversalTime:%u\n", conf->dot11MeshHWMPnetDiameterTraversalTime); + RTW_PRINT_SEL(sel, "dot11MeshHWMPRootMode:%u\n", conf->dot11MeshHWMPRootMode); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + RTW_PRINT_SEL(sel, "dot11MeshHWMPRannInterval:%u\n", conf->dot11MeshHWMPRannInterval); + RTW_PRINT_SEL(sel, "dot11MeshGateAnnouncementProtocol:%d\n", conf->dot11MeshGateAnnouncementProtocol); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) + RTW_PRINT_SEL(sel, "dot11MeshForwarding:%d\n", conf->dot11MeshForwarding); + RTW_PRINT_SEL(sel, "rssi_threshold:%d\n", conf->rssi_threshold); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + RTW_PRINT_SEL(sel, "ht_opmode:0x%04x\n", conf->ht_opmode); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathToRootTimeout:%u\n", conf->dot11MeshHWMPactivePathToRootTimeout); + RTW_PRINT_SEL(sel, "dot11MeshHWMProotInterval:%u\n", conf->dot11MeshHWMProotInterval); + RTW_PRINT_SEL(sel, "dot11MeshHWMPconfirmationInterval:%u\n", conf->dot11MeshHWMPconfirmationInterval); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + RTW_PRINT_SEL(sel, "power_mode:%s\n", nl80211_mesh_power_mode_str(conf->power_mode)); + RTW_PRINT_SEL(sel, "dot11MeshAwakeWindowDuration:%u\n", conf->dot11MeshAwakeWindowDuration); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + RTW_PRINT_SEL(sel, "plink_timeout:%u\n", conf->plink_timeout); +#endif +} +#endif /* DBG_RTW_CFG80211_MESH_CONF */ + +static void rtw_cfg80211_mesh_info_set_profile(struct rtw_mesh_info *minfo, const struct mesh_setup *setup) +{ + _rtw_memcpy(minfo->mesh_id, setup->mesh_id, setup->mesh_id_len); + minfo->mesh_id_len = setup->mesh_id_len; + minfo->mesh_pp_id = setup->path_sel_proto; + minfo->mesh_pm_id = setup->path_metric; + minfo->mesh_cc_id = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + minfo->mesh_sp_id = setup->sync_method; +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + minfo->mesh_auth_id = setup->auth_id; +#else + if (setup->is_authenticated) { + u8 *rsn_ie; + sint rsn_ie_len; + struct rsne_info info; + u8 *akm; + u8 AKM_SUITE_SAE[4] = {0x00, 0x0F, 0xAC, 0x08}; + + rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len); + if (!rsn_ie || !rsn_ie_len) { + rtw_warn_on(1); + return; + } + + if (rtw_rsne_info_parse(rsn_ie, rsn_ie_len + 2, &info) != _SUCCESS) { + rtw_warn_on(1); + return; + } + + if (!info.akm_list || !info.akm_cnt) { + rtw_warn_on(1); + return; + } + + akm = info.akm_list; + while (akm < info.akm_list + info.akm_cnt * 4) { + if (_rtw_memcmp(akm, AKM_SUITE_SAE, 4) == _TRUE) { + minfo->mesh_auth_id = 0x01; + break; + } + } + + if (!minfo->mesh_auth_id) { + rtw_warn_on(1); + return; + } + } +#endif +} + +static inline bool chk_mesh_attr(enum nl80211_meshconf_params parm, u32 mask) +{ + return (mask >> (parm - 1)) & 0x1; +} + +static void rtw_cfg80211_mesh_cfg_set(_adapter *adapter, const struct mesh_config *conf, u32 mask) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + +#if 0 /* driver MPM */ + if (chk_mesh_attr(NL80211_MESHCONF_RETRY_TIMEOUT, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_CONFIRM_TIMEOUT, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_HOLDING_TIMEOUT, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_MAX_PEER_LINKS, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_MAX_RETRIES, mask)); +#endif + + if (chk_mesh_attr(NL80211_MESHCONF_TTL, mask)) + mcfg->dot11MeshTTL = conf->dot11MeshTTL; + if (chk_mesh_attr(NL80211_MESHCONF_ELEMENT_TTL, mask)) + mcfg->element_ttl = conf->element_ttl; + +#if 0 /* driver MPM */ + if (chk_mesh_attr(NL80211_MESHCONF_AUTO_OPEN_PLINKS, mask)); +#endif + +#if 0 /* TBD: synchronization */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR, mask)); +#endif +#endif + + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES, mask)) + mcfg->dot11MeshHWMPmaxPREQretries = conf->dot11MeshHWMPmaxPREQretries; + if (chk_mesh_attr(NL80211_MESHCONF_PATH_REFRESH_TIME, mask)) + mcfg->path_refresh_time = conf->path_refresh_time; + if (chk_mesh_attr(NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT, mask)) + mcfg->min_discovery_timeout = conf->min_discovery_timeout; + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT, mask)) + mcfg->dot11MeshHWMPactivePathTimeout = conf->dot11MeshHWMPactivePathTimeout; + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL, mask)) + mcfg->dot11MeshHWMPpreqMinInterval = conf->dot11MeshHWMPpreqMinInterval; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL, mask)) + mcfg->dot11MeshHWMPperrMinInterval = conf->dot11MeshHWMPperrMinInterval; +#endif + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME, mask)) + mcfg->dot11MeshHWMPnetDiameterTraversalTime = conf->dot11MeshHWMPnetDiameterTraversalTime; + + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOTMODE, mask)) + mcfg->dot11MeshHWMPRootMode = conf->dot11MeshHWMPRootMode; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_GATE_ANNOUNCEMENTS, mask)) + mcfg->dot11MeshGateAnnouncementProtocol = conf->dot11MeshGateAnnouncementProtocol; + /* our current gate annc implementation rides on root annc with gate annc bit in PREQ flags */ + if (mcfg->dot11MeshGateAnnouncementProtocol + && mcfg->dot11MeshHWMPRootMode <= RTW_IEEE80211_ROOTMODE_ROOT + ) { + mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_PROACTIVE_RANN; + RTW_INFO(ADPT_FMT" enable PROACTIVE_RANN becaue gate annc is needed\n", ADPT_ARG(adapter)); + } + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_RANN_INTERVAL, mask)) + mcfg->dot11MeshHWMPRannInterval = conf->dot11MeshHWMPRannInterval; +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_FORWARDING, mask)) + mcfg->dot11MeshForwarding = conf->dot11MeshForwarding; + + if (chk_mesh_attr(NL80211_MESHCONF_RSSI_THRESHOLD, mask)) + mcfg->rssi_threshold = conf->rssi_threshold; +#endif + +#if 0 /* controlled by driver */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_HT_OPMODE, mask)); +#endif +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT, mask)) + mcfg->dot11MeshHWMPactivePathToRootTimeout = conf->dot11MeshHWMPactivePathToRootTimeout; + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOT_INTERVAL, mask)) + mcfg->dot11MeshHWMProotInterval = conf->dot11MeshHWMProotInterval; + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL, mask)) + mcfg->dot11MeshHWMPconfirmationInterval = conf->dot11MeshHWMPconfirmationInterval; +#endif + +#if 0 /* TBD */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_POWER_MODE, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_AWAKE_WINDOW, mask)); +#endif +#endif + +#if 0 /* driver MPM */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_PLINK_TIMEOUT, mask)); +#endif +#endif +} + +u8 *rtw_cfg80211_construct_mesh_beacon_ies(struct wiphy *wiphy, _adapter *adapter + , const struct mesh_config *conf, const struct mesh_setup *setup + , uint *ies_len) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef); +#endif + struct ieee80211_channel *chan; + u8 ch, bw, offset; +#endif + uint len; + u8 n_bitrates; + u8 ht = 0; + u8 vht = 0; + u8 *rsn_ie = NULL; + sint rsn_ie_len = 0; + u8 *ies = NULL, *c; + u8 supported_rates[RTW_G_RATES_NUM] = {0}; + int i; + + *ies_len = 0; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + chan = (struct ieee80211_channel *)chdef->chan; +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + chan = (struct ieee80211_channel *)setup->channel; +#endif + + n_bitrates = wiphy->bands[chan->band]->n_bitrates; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + rtw_get_chbw_from_cfg80211_chan_def(chdef, &ht, &ch, &bw, &offset); +#else + rtw_get_chbw_from_nl80211_channel_type(chan, setup->channel_type, &ht, &ch, &bw, &offset); +#endif + if (!ch) + goto exit; + +#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + vht = ht && ch > 14 && bw >= CHANNEL_WIDTH_80; /* VHT40/VHT20? */ +#endif + + RTW_INFO(FUNC_ADPT_FMT" => ch:%u,%u,%u, ht:%u, vht:%u\n" + , FUNC_ADPT_ARG(adapter), ch, bw, offset, ht, vht); +#endif + + rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len); + if (rsn_ie && !rsn_ie_len) { + rtw_warn_on(1); + rsn_ie = NULL; + } + + len = _BEACON_IE_OFFSET_ + + 2 /* 0-length SSID */ + + (n_bitrates >= 8 ? 8 : n_bitrates) + 2 /* Supported Rates */ + + 3 /* DS parameter set */ + + 6 /* TIM */ + + (n_bitrates > 8 ? n_bitrates - 8 + 2 : 0) /* Extended Supported Rates */ + + (rsn_ie ? rsn_ie_len + 2 : 0) /* RSN */ + #if defined(CONFIG_80211N_HT) + + (ht ? HT_CAP_IE_LEN + 2 + HT_OP_IE_LEN + 2 : 0) /* HT */ + #endif + #if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + + (vht ? VHT_CAP_IE_LEN + 2 + VHT_OP_IE_LEN + 2 : 0) /* VHT */ + #endif + + minfo->mesh_id_len + 2 /* Mesh ID */ + + 9 /* Mesh configuration */ + ; + + ies = rtw_zmalloc(len); + if (!ies) + goto exit; + + /* timestamp */ + c = ies + 8; + + /* beacon interval */ + RTW_PUT_LE16(c , setup->beacon_interval); + c += 2; + + /* capability */ + if (rsn_ie) + *((u16 *)c) |= cpu_to_le16(cap_Privacy); + c += 2; + + /* SSID */ + c = rtw_set_ie(c, WLAN_EID_SSID, 0, NULL, NULL); + + /* Supported Rates */ + for (i = 0; i < n_bitrates; i++) { + supported_rates[i] = wiphy->bands[chan->band]->bitrates[i].bitrate / 5; + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + if (setup->basic_rates & BIT(i)) + #else + if (rtw_is_basic_rate_mix(supported_rates[i])) + #endif + supported_rates[i] |= IEEE80211_BASIC_RATE_MASK; + } + c = rtw_set_ie(c, WLAN_EID_SUPP_RATES, (n_bitrates >= 8 ? 8 : n_bitrates), supported_rates, NULL); + + /* DS parameter set */ + c = rtw_set_ie(c, WLAN_EID_DS_PARAMS, 1, &ch, NULL); + + /* TIM */ + *c = WLAN_EID_TIM; + *(c + 1) = 4; + c += 6; + //c = rtw_set_ie(c, _TIM_IE_, 4, NULL, NULL); + + /* Extended Supported Rates */ + if (n_bitrates > 8) + c = rtw_set_ie(c, WLAN_EID_EXT_SUPP_RATES, n_bitrates - 8, supported_rates + 8, NULL); + + /* RSN */ + if (rsn_ie) + c = rtw_set_ie(c, WLAN_EID_RSN, rsn_ie_len, rsn_ie + 2, NULL); + +#if defined(CONFIG_80211N_HT) + if (ht) { + struct ieee80211_sta_ht_cap *sta_ht_cap = &wiphy->bands[chan->band]->ht_cap; + u8 ht_cap[HT_CAP_IE_LEN]; + u8 ht_op[HT_OP_IE_LEN]; + + _rtw_memset(ht_cap, 0, HT_CAP_IE_LEN); + _rtw_memset(ht_op, 0, HT_OP_IE_LEN); + + /* WLAN_EID_HT_CAP */ + RTW_PUT_LE16(HT_CAP_ELE_CAP_INFO(ht_cap), sta_ht_cap->cap); + SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(ht_cap, sta_ht_cap->ampdu_factor); + SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(ht_cap, sta_ht_cap->ampdu_density); + _rtw_memcpy(HT_CAP_ELE_SUP_MCS_SET(ht_cap), &sta_ht_cap->mcs, 16); + c = rtw_set_ie(c, WLAN_EID_HT_CAP, HT_CAP_IE_LEN, ht_cap, NULL); + + /* WLAN_EID_HT_OPERATION */ + SET_HT_OP_ELE_PRI_CHL(ht_op, ch); + switch (offset) { + case HAL_PRIME_CHNL_OFFSET_LOWER: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCA); + break; + case HAL_PRIME_CHNL_OFFSET_UPPER: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCB); + break; + case HAL_PRIME_CHNL_OFFSET_DONT_CARE: + default: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCN); + break; + } + if (bw >= CHANNEL_WIDTH_40) + SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 1); + else + SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 0); + c = rtw_set_ie(c, WLAN_EID_HT_OPERATION, HT_OP_IE_LEN, ht_op, NULL); + } +#endif /* defined(CONFIG_80211N_HT) */ + +#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + if (vht) { + struct ieee80211_sta_vht_cap *sta_vht_cap = &wiphy->bands[chan->band]->vht_cap; + u8 vht_cap[VHT_CAP_IE_LEN]; + u8 vht_op[VHT_OP_IE_LEN]; + u8 cch = rtw_get_center_ch(ch, bw, offset); + + _rtw_memset(vht_op, 0, VHT_OP_IE_LEN); + + /* WLAN_EID_VHT_CAPABILITY */ + _rtw_memcpy(vht_cap, &sta_vht_cap->cap, 4); + _rtw_memcpy(vht_cap + 4, &sta_vht_cap->vht_mcs, 8); + c = rtw_set_ie(c, WLAN_EID_VHT_CAPABILITY, VHT_CAP_IE_LEN, vht_cap, NULL); + + /* WLAN_EID_VHT_OPERATION */ + if (bw < CHANNEL_WIDTH_80) { + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0); + } else if (bw == CHANNEL_WIDTH_80) { + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 1); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, cch); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0); + } else { + RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(adapter), bw); + rtw_warn_on(1); + rtw_mfree(ies, len); + goto exit; + } + + /* Hard code 1 stream, MCS0-7 is a min Basic VHT MCS rates */ + vht_op[3] = 0xfc; + vht_op[4] = 0xff; + c = rtw_set_ie(c, WLAN_EID_VHT_OPERATION, VHT_OP_IE_LEN, vht_op, NULL); + } +#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */ + + /* Mesh ID */ + c = rtw_set_ie_mesh_id(c, NULL, minfo->mesh_id, minfo->mesh_id_len); + + /* Mesh configuration */ + c = rtw_set_ie_mesh_config(c, NULL + , minfo->mesh_pp_id + , minfo->mesh_pm_id + , minfo->mesh_cc_id + , minfo->mesh_sp_id + , minfo->mesh_auth_id + , 0, 0, 0 + , 1 + , 0, 0 + , mcfg->dot11MeshForwarding + , 0, 0, 0 + ); + +#if DBG_RTW_CFG80211_MESH_CONF + RTW_INFO(FUNC_ADPT_FMT" ies_len:%u\n", FUNC_ADPT_ARG(adapter), len); + dump_ies(RTW_DBGDUMP, ies + _BEACON_IE_OFFSET_, len - _BEACON_IE_OFFSET_); +#endif + +exit: + if (ies) + *ies_len = len; + return ies; +} + +static int cfg80211_rtw_get_mesh_config(struct wiphy *wiphy, struct net_device *dev + , struct mesh_config *conf) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_cfg *mesh_cfg = &adapter->mesh_cfg; + int ret = 0; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + + /* driver MPM */ + conf->dot11MeshRetryTimeout = 0; + conf->dot11MeshConfirmTimeout = 0; + conf->dot11MeshHoldingTimeout = 0; + conf->dot11MeshMaxPeerLinks = mesh_cfg->max_peer_links; + conf->dot11MeshMaxRetries = 0; + + conf->dot11MeshTTL = mesh_cfg->dot11MeshTTL; + conf->element_ttl = mesh_cfg->element_ttl; + + /* driver MPM */ + conf->auto_open_plinks = 0; + + /* TBD: synchronization */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + conf->dot11MeshNbrOffsetMaxNeighbor = 0; +#endif + + conf->dot11MeshHWMPmaxPREQretries = mesh_cfg->dot11MeshHWMPmaxPREQretries; + conf->path_refresh_time = mesh_cfg->path_refresh_time; + conf->min_discovery_timeout = mesh_cfg->min_discovery_timeout; + conf->dot11MeshHWMPactivePathTimeout = mesh_cfg->dot11MeshHWMPactivePathTimeout; + conf->dot11MeshHWMPpreqMinInterval = mesh_cfg->dot11MeshHWMPpreqMinInterval; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + conf->dot11MeshHWMPperrMinInterval = mesh_cfg->dot11MeshHWMPperrMinInterval; +#endif + conf->dot11MeshHWMPnetDiameterTraversalTime = mesh_cfg->dot11MeshHWMPnetDiameterTraversalTime; + conf->dot11MeshHWMPRootMode = mesh_cfg->dot11MeshHWMPRootMode; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + conf->dot11MeshHWMPRannInterval = mesh_cfg->dot11MeshHWMPRannInterval; +#endif + conf->dot11MeshGateAnnouncementProtocol = mesh_cfg->dot11MeshGateAnnouncementProtocol; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) + conf->dot11MeshForwarding = mesh_cfg->dot11MeshForwarding; + conf->rssi_threshold = mesh_cfg->rssi_threshold; +#endif + + /* TBD */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + conf->ht_opmode = 0xffff; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + conf->dot11MeshHWMPactivePathToRootTimeout = mesh_cfg->dot11MeshHWMPactivePathToRootTimeout; + conf->dot11MeshHWMProotInterval = mesh_cfg->dot11MeshHWMProotInterval; + conf->dot11MeshHWMPconfirmationInterval = mesh_cfg->dot11MeshHWMPconfirmationInterval; +#endif + + /* TBD: power save */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + conf->power_mode = NL80211_MESH_POWER_ACTIVE; + conf->dot11MeshAwakeWindowDuration = 0; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + conf->plink_timeout = mesh_cfg->plink_timeout; +#endif + + return ret; +} + +static void rtw_mbss_info_change_notify(_adapter *adapter, bool minfo_changed, bool need_work) +{ + if (need_work) + rtw_mesh_work(&adapter->mesh_work); +} + +static int cfg80211_rtw_update_mesh_config(struct wiphy *wiphy, struct net_device *dev + , u32 mask, const struct mesh_config *nconf) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + int ret = 0; + bool minfo_changed = _FALSE, need_work = _FALSE; + + RTW_INFO(FUNC_ADPT_FMT" mask:0x%08x\n", FUNC_ADPT_ARG(adapter), mask); + + rtw_cfg80211_mesh_cfg_set(adapter, nconf, mask); + update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE); + need_work = rtw_ieee80211_mesh_root_setup(adapter); + + rtw_mbss_info_change_notify(adapter, minfo_changed, need_work); + + return ret; +} + +static int cfg80211_rtw_join_mesh(struct wiphy *wiphy, struct net_device *dev, + const struct mesh_config *conf, const struct mesh_setup *setup) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u8 *ies = NULL; + uint ies_len; + int ret = 0; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + +#if DBG_RTW_CFG80211_MESH_CONF + RTW_INFO(FUNC_ADPT_FMT" mesh_setup:\n", FUNC_ADPT_ARG(adapter)); + dump_mesh_setup(RTW_DBGDUMP, wiphy, setup); + RTW_INFO(FUNC_ADPT_FMT" mesh_config:\n", FUNC_ADPT_ARG(adapter)); + dump_mesh_config(RTW_DBGDUMP, conf); +#endif + + if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) { + ret = -ENOTSUPP; + goto exit; + } + + /* initialization */ + rtw_mesh_init_mesh_info(adapter); + + /* apply cfg80211 settings*/ + rtw_cfg80211_mesh_info_set_profile(&adapter->mesh_info, setup); + rtw_cfg80211_mesh_cfg_set(adapter, conf, 0xFFFFFFFF); + + /* apply cfg80211 settings (join only) */ + rtw_mesh_cfg_init_max_peer_links(adapter, conf->dot11MeshMaxPeerLinks); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + rtw_mesh_cfg_init_plink_timeout(adapter, conf->plink_timeout); + #endif + + rtw_ieee80211_mesh_root_setup(adapter); + + ies = rtw_cfg80211_construct_mesh_beacon_ies(wiphy, adapter, conf, setup, &ies_len); + if (!ies) { + ret = -EINVAL; + goto exit; + } + + /* start mbss */ + if (rtw_check_beacon_data(adapter, ies, ies_len) != _SUCCESS) { + ret = -EINVAL; + goto exit; + } + + rtw_mesh_work(&adapter->mesh_work); + +exit: + if (ies) + rtw_mfree(ies, ies_len); + if (ret) + rtw_mesh_deinit_mesh_info(adapter); + + return ret; +} + +static int cfg80211_rtw_leave_mesh(struct wiphy *wiphy, struct net_device *dev) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + int ret = 0; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + + rtw_mesh_deinit_mesh_info(adapter); + + rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure); + rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK); + + return ret; +} + +static int cfg80211_rtw_add_mpath(struct wiphy *wiphy, struct net_device *dev + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + , const u8 *dst, const u8 *next_hop + #else + , u8 *dst, u8 *next_hop + #endif +) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sta; + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + sta = rtw_get_stainfo(stapriv, next_hop); + if (!sta) { + ret = -ENOENT; + goto exit; + } + + mpath = rtw_mesh_path_add(adapter, dst); + if (!mpath) { + ret = -ENOENT; + goto exit; + } + + rtw_mesh_path_fix_nexthop(mpath, sta); + +exit: + rtw_rcu_read_unlock(); + + return ret; +} + +static int cfg80211_rtw_del_mpath(struct wiphy *wiphy, struct net_device *dev + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + , const u8 *dst + #else + , u8 *dst + #endif +) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + int ret = 0; + + if (dst) { + if (rtw_mesh_path_del(adapter, dst)) { + ret = -ENOENT; + goto exit; + } + } else { + rtw_mesh_path_flush_by_iface(adapter); + } + +exit: + return ret; +} + +static int cfg80211_rtw_change_mpath(struct wiphy *wiphy, struct net_device *dev + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + , const u8 *dst, const u8 *next_hop + #else + , u8 *dst, u8 *next_hop + #endif +) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sta; + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + sta = rtw_get_stainfo(stapriv, next_hop); + if (!sta) { + ret = -ENOENT; + goto exit; + } + + mpath = rtw_mesh_path_lookup(adapter, dst); + if (!mpath) { + ret = -ENOENT; + goto exit; + } + + rtw_mesh_path_fix_nexthop(mpath, sta); + +exit: + rtw_rcu_read_unlock(); + + return ret; +} + +static void rtw_cfg80211_mpath_set_pinfo(struct rtw_mesh_path *mpath, u8 *next_hop, struct mpath_info *pinfo) +{ + struct sta_info *next_hop_sta = rtw_rcu_dereference(mpath->next_hop); + + if (next_hop_sta) + _rtw_memcpy(next_hop, next_hop_sta->cmn.mac_addr, ETH_ALEN); + else + _rtw_memset(next_hop, 0, ETH_ALEN); + + _rtw_memset(pinfo, 0, sizeof(*pinfo)); + + pinfo->generation = mpath->adapter->mesh_info.mesh_paths_generation; + + pinfo->filled = 0 + | MPATH_INFO_FRAME_QLEN + | MPATH_INFO_SN + | MPATH_INFO_METRIC + | MPATH_INFO_EXPTIME + | MPATH_INFO_DISCOVERY_TIMEOUT + | MPATH_INFO_DISCOVERY_RETRIES + | MPATH_INFO_FLAGS + ; + + pinfo->frame_qlen = mpath->frame_queue_len; + pinfo->sn = mpath->sn; + pinfo->metric = mpath->metric; + if (rtw_time_after(mpath->exp_time, rtw_get_current_time())) + pinfo->exptime = rtw_get_remaining_time_ms(mpath->exp_time); + pinfo->discovery_timeout = rtw_systime_to_ms(mpath->discovery_timeout); + pinfo->discovery_retries = mpath->discovery_retries; + if (mpath->flags & RTW_MESH_PATH_ACTIVE) + pinfo->flags |= NL80211_MPATH_FLAG_ACTIVE; + if (mpath->flags & RTW_MESH_PATH_RESOLVING) + pinfo->flags |= NL80211_MPATH_FLAG_RESOLVING; + if (mpath->flags & RTW_MESH_PATH_SN_VALID) + pinfo->flags |= NL80211_MPATH_FLAG_SN_VALID; + if (mpath->flags & RTW_MESH_PATH_FIXED) + pinfo->flags |= NL80211_MPATH_FLAG_FIXED; + if (mpath->flags & RTW_MESH_PATH_RESOLVED) + pinfo->flags |= NL80211_MPATH_FLAG_RESOLVED; +} + +static int cfg80211_rtw_get_mpath(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *next_hop, struct mpath_info *pinfo) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + mpath = rtw_mesh_path_lookup(adapter, dst); + if (!mpath) { + ret = -ENOENT; + goto exit; + } + + rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo); + +exit: + rtw_rcu_read_unlock(); + + return ret; +} + +static int cfg80211_rtw_dump_mpath(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *next_hop, struct mpath_info *pinfo) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + mpath = rtw_mesh_path_lookup_by_idx(adapter, idx); + if (!mpath) { + ret = -ENOENT; + goto exit; + } + + _rtw_memcpy(dst, mpath->dst, ETH_ALEN); + rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo); + +exit: + rtw_rcu_read_unlock(); -discard: return ret; } -static int cfg80211_rtw_tdls_oper(struct wiphy *wiphy, - struct net_device *ndev, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) - const u8 *peer, -#else - u8 *peer, -#endif - enum nl80211_tdls_operation oper) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) +static void rtw_cfg80211_mpp_set_pinfo(struct rtw_mesh_path *mpath, u8 *mpp, struct mpath_info *pinfo) { - _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); - struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - struct tdls_txmgmt txmgmt; - struct sta_info *ptdls_sta = NULL; + _rtw_memcpy(mpp, mpath->mpp, ETH_ALEN); - RTW_INFO(FUNC_NDEV_FMT", nl80211_tdls_operation:%d\n", FUNC_NDEV_ARG(ndev), oper); + _rtw_memset(pinfo, 0, sizeof(*pinfo)); + pinfo->generation = mpath->adapter->mesh_info.mpp_paths_generation; +} - if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) { - RTW_INFO("Discard tdls oper:%d, since hal doesn't support tdls\n", oper); - return 0; +static int cfg80211_rtw_get_mpp(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *mpp, struct mpath_info *pinfo) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + mpath = rtw_mpp_path_lookup(adapter, dst); + if (!mpath) { + ret = -ENOENT; + goto exit; } -#ifdef CONFIG_LPS - rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); -#endif /* CONFIG_LPS */ + rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo); - _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - if (peer) - _rtw_memcpy(txmgmt.peer, peer, ETH_ALEN); +exit: + rtw_rcu_read_unlock(); - if (rtw_tdls_is_driver_setup(padapter)) { - /* these two cases are done by driver itself */ - if (oper == NL80211_TDLS_ENABLE_LINK || oper == NL80211_TDLS_DISABLE_LINK) - return 0; - } + return ret; +} - switch (oper) { - case NL80211_TDLS_DISCOVERY_REQ: - issue_tdls_dis_req(padapter, &txmgmt); - break; - case NL80211_TDLS_SETUP: -#ifdef CONFIG_WFD - if (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) { - if (padapter->wdinfo.wfd_tdls_weaksec == _TRUE) - issue_tdls_setup_req(padapter, &txmgmt, _TRUE); - else - RTW_INFO("[%s] Current link is not AES, SKIP sending the tdls setup request!!\n", __FUNCTION__); - } else -#endif /* CONFIG_WFD */ - { - issue_tdls_setup_req(padapter, &txmgmt, _TRUE); - } - break; - case NL80211_TDLS_TEARDOWN: - ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), txmgmt.peer); - if (ptdls_sta != NULL) { - txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; - issue_tdls_teardown(padapter, &txmgmt, _TRUE); - } else - RTW_INFO("TDLS peer not found\n"); - break; - case NL80211_TDLS_ENABLE_LINK: - RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_ENABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer)); - ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer); - if (ptdls_sta != NULL) { - ptdlsinfo->link_established = _TRUE; - ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE; - ptdls_sta->state |= _FW_LINKED; - rtw_tdls_cmd(padapter, txmgmt.peer, TDLS_ESTABLISHED); - } - break; - case NL80211_TDLS_DISABLE_LINK: - RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_DISABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer)); - ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer); - if (ptdls_sta != NULL) - rtw_tdls_cmd(padapter, (u8 *)peer, TDLS_TEARDOWN_STA_LOCALLY); - break; +static int cfg80211_rtw_dump_mpp(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *mpp, struct mpath_info *pinfo) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + mpath = rtw_mpp_path_lookup_by_idx(adapter, idx); + if (!mpath) { + ret = -ENOENT; + goto exit; } - return 0; + + _rtw_memcpy(dst, mpath->dst, ETH_ALEN); + rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo); + +exit: + rtw_rcu_read_unlock(); + + return ret; } -#endif /* CONFIG_TDLS */ +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */ + +#endif /* defined(CONFIG_RTW_MESH) */ #if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, @@ -6183,6 +8231,10 @@ static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct cfg80211_ssid *ssids; + int n_ssids = 0; + int interval = 0; + int i = 0; u8 ret; if (padapter->bup == _FALSE) { @@ -6201,10 +8253,26 @@ static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, RTW_INFO("%s: invalid cfg80211_requests parameters.\n", __func__); return -EINVAL; } - - ret = rtw_android_cfg80211_pno_setup(dev, request->ssids, - request->n_ssids, request->interval); - +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0) + interval = request->interval; + n_ssids = request->n_match_sets; + ssids = (struct cfg80211_ssid *)rtw_zmalloc(n_ssids * sizeof(struct cfg80211_ssid)); + if(ssids == NULL) { + RTW_ERR("Fail to allocate ssids for PNO\n"); + return -ENOMEM; + } + for (i=0;in_match_sets;i++) { + ssids[i].ssid_len = request->match_sets[i].ssid.ssid_len; + memcpy(ssids[i].ssid, request->match_sets[i].ssid.ssid, + request->match_sets[i].ssid.ssid_len); + } +#else + interval = request->interval; + n_ssids = request->n_ssids; + ssids = request->ssids; +#endif +ret = rtw_android_cfg80211_pno_setup(dev, ssids, + n_ssids, interval); if (ret < 0) { RTW_INFO("%s ret: %d\n", __func__, ret); goto exit; @@ -6224,6 +8292,63 @@ static int cfg80211_rtw_sched_scan_stop(struct wiphy *wiphy, { return rtw_android_pno_enable(dev, _FALSE); } + +int cfg80211_rtw_suspend(struct wiphy *wiphy, struct cfg80211_wowlan *wow) { + RTW_DBG("==> %s\n",__func__); + RTW_DBG("<== %s\n",__func__); + return 0; +} + +int cfg80211_rtw_resume(struct wiphy *wiphy) { + + _adapter *padapter; + struct pwrctrl_priv *pwrpriv; + struct mlme_priv *pmlmepriv; + padapter = wiphy_to_adapter(wiphy); + pwrpriv = adapter_to_pwrctl(padapter); + pmlmepriv = &padapter->mlmepriv; + struct sitesurvey_parm parm; + int i, len; + + + RTW_DBG("==> %s\n",__func__); + if (pwrpriv->wowlan_last_wake_reason == RX_PNO) { + + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + _irqL irqL; + int PNOWakeupScanWaitCnt = 0; + + rtw_cfg80211_disconnected(padapter->rtw_wdev, 0, NULL, 0, 1, GFP_ATOMIC); + + rtw_init_sitesurvey_parm(padapter, &parm); + for (i=0;ipnlo_info->ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) { + len = pwrpriv->pno_ssid_list->node[i].SSID_len; + _rtw_memcpy(&parm.ssid[i].Ssid, pwrpriv->pno_ssid_list->node[i].SSID, len); + parm->ssid[i].SsidLength = len; + } + prm->ssid_num = pwrpriv->pnlo_info->ssid_num; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + //This modification fix PNO wakeup reconnect issue with hidden SSID AP. + //rtw_sitesurvey_cmd(padapter, NULL); + rtw_sitesurvey_cmd(padapter, &parm); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + for (PNOWakeupScanWaitCnt = 0; PNOWakeupScanWaitCnt < 10; PNOWakeupScanWaitCnt++) { + if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _FALSE) + break; + rtw_msleep_os(1000); + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + cfg80211_sched_scan_results(padapter->rtw_wdev->wiphy); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + } + RTW_DBG("<== %s\n",__func__); + return 0; + +} #endif /* CONFIG_PNO_SUPPORT */ static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len) @@ -6583,7 +8708,9 @@ int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, } -static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter, struct ieee80211_sta_ht_cap *ht_cap, enum nl80211_band band, u8 rf_type) +#ifdef CONFIG_80211N_HT +static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter + , struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type) { struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -6603,9 +8730,9 @@ static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter, struct ieee80211_s /* RX STBC */ if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) { /*rtw_rx_stbc 0: disable, bit(0):enable 2.4g, bit(1):enable 5g*/ - if (band == NL80211_BAND_2GHZ) + if (band == BAND_ON_2_4G) stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(0)) ? _TRUE : _FALSE; - if (band == NL80211_BAND_5GHZ) + if (band == BAND_ON_5G) stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(1)) ? _TRUE : _FALSE; if (stbc_rx_enable) { @@ -6631,7 +8758,8 @@ static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter, struct ieee80211_s } } -static void rtw_cfg80211_init_ht_capab(_adapter *padapter, struct ieee80211_sta_ht_cap *ht_cap, enum nl80211_band band, u8 rf_type) +static void rtw_cfg80211_init_ht_capab(_adapter *padapter + , struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type) { struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); u8 rx_nss = 0; @@ -6679,12 +8807,41 @@ static void rtw_cfg80211_init_ht_capab(_adapter *padapter, struct ieee80211_sta_ RTW_INFO("%s, error rf_type=%d\n", __func__, rf_type); }; - ht_cap->mcs.rx_highest = rtw_mcs_rate(rf_type - , hal_is_bw_support(padapter, CHANNEL_WIDTH_40) - , hal_is_bw_support(padapter, CHANNEL_WIDTH_40) ? ht_cap->cap & IEEE80211_HT_CAP_SGI_40 : ht_cap->cap & IEEE80211_HT_CAP_SGI_20 - , ht_cap->mcs.rx_mask - ); + ht_cap->mcs.rx_highest = cpu_to_le16( + rtw_mcs_rate(rf_type + , hal_is_bw_support(padapter, CHANNEL_WIDTH_40) + , hal_is_bw_support(padapter, CHANNEL_WIDTH_40) ? ht_cap->cap & IEEE80211_HT_CAP_SGI_40 : ht_cap->cap & IEEE80211_HT_CAP_SGI_20 + , ht_cap->mcs.rx_mask) / 10); +} +#endif /* CONFIG_80211N_HT */ + +#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +static void rtw_cfg80211_init_vht_capab(_adapter *padapter + , struct ieee80211_sta_vht_cap *sta_vht_cap, BAND_TYPE band, u8 rf_type) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + struct registry_priv *regsty = &padapter->registrypriv; + struct vht_priv *vhtpriv = &padapter->mlmepriv.vhtpriv; + u8 vht_cap_ie[2 + 12] = {0}; + u8 bw; + + if (!REGSTY_IS_11AC_ENABLE(regsty) + || !hal_chk_proto_cap(padapter, PROTO_CAP_11AC) + ) { + sta_vht_cap->vht_supported = 0; + return; + } + + rtw_vht_use_default_setting(padapter); + rtw_build_vht_cap_ie(padapter, vht_cap_ie); + + sta_vht_cap->vht_supported = 1; + + _rtw_memcpy(&sta_vht_cap->cap, vht_cap_ie + 2, 4); + _rtw_memcpy(&sta_vht_cap->vht_mcs, vht_cap_ie + 2 + 4, 8); } +#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */ + void rtw_cfg80211_init_wdev_data(_adapter *padapter) { #ifdef CONFIG_CONCURRENT_MODE @@ -6697,7 +8854,7 @@ void rtw_cfg80211_init_wdev_data(_adapter *padapter) void rtw_cfg80211_init_wiphy(_adapter *padapter) { u8 rf_type; - struct ieee80211_supported_band *bands; + struct ieee80211_supported_band *band; struct wireless_dev *pwdev = padapter->rtw_wdev; struct wiphy *wiphy = pwdev->wiphy; @@ -6706,15 +8863,24 @@ void rtw_cfg80211_init_wiphy(_adapter *padapter) RTW_INFO("%s:rf_type=%d\n", __func__, rf_type); if (IsSupported24G(padapter->registrypriv.wireless_mode)) { - bands = wiphy->bands[NL80211_BAND_2GHZ]; - if (bands) - rtw_cfg80211_init_ht_capab(padapter, &bands->ht_cap, NL80211_BAND_2GHZ, rf_type); + band = wiphy->bands[NL80211_BAND_2GHZ]; + if (band) { + #if defined(CONFIG_80211N_HT) + rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_2_4G, rf_type); + #endif + } } #ifdef CONFIG_IEEE80211_BAND_5GHZ if (is_supported_5g(padapter->registrypriv.wireless_mode)) { - bands = wiphy->bands[NL80211_BAND_5GHZ]; - if (bands) - rtw_cfg80211_init_ht_capab(padapter, &bands->ht_cap, NL80211_BAND_5GHZ, rf_type); + band = wiphy->bands[NL80211_BAND_5GHZ]; + if (band) { + #if defined(CONFIG_80211N_HT) + rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_5G, rf_type); + #endif + #if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + rtw_cfg80211_init_vht_capab(padapter, &band->vht_cap, BAND_ON_5G, rf_type); + #endif + } } #endif /* init regulary domain */ @@ -6747,7 +8913,13 @@ struct ieee80211_iface_limit rtw_limits[] = { { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) - } + }, + #endif + #if defined(CONFIG_RTW_MESH) + { + .max = 1, + .types = BIT(NL80211_IFTYPE_MESH_POINT) + }, #endif }; @@ -6798,6 +8970,9 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) #if defined(RTW_DEDICATED_P2P_DEVICE) | BIT(NL80211_IFTYPE_P2P_DEVICE) #endif +#endif +#ifdef CONFIG_RTW_MESH + | BIT(NL80211_IFTYPE_MESH_POINT) /* 2.6.26 */ #endif ; @@ -6822,11 +8997,11 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites); if (IsSupported24G(adapter->registrypriv.wireless_mode)) - wiphy->bands[NL80211_BAND_2GHZ] = rtw_spt_band_alloc(NL80211_BAND_2GHZ); + wiphy->bands[NL80211_BAND_2GHZ] = rtw_spt_band_alloc(BAND_ON_2_4G); #ifdef CONFIG_IEEE80211_BAND_5GHZ if (is_supported_5g(adapter->registrypriv.wireless_mode)) - wiphy->bands[NL80211_BAND_5GHZ] = rtw_spt_band_alloc(NL80211_BAND_5GHZ); + wiphy->bands[NL80211_BAND_5GHZ] = rtw_spt_band_alloc(BAND_ON_5G); #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38) && LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0)) @@ -6840,23 +9015,23 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) /* wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX | WIPHY_FLAG_HAVE_AP_SME; */ #endif -#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN; #ifdef CONFIG_PNO_SUPPORT wiphy->max_sched_scan_ssids = MAX_PNO_LIST_COUNT; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0) + wiphy->max_match_sets = MAX_PNO_LIST_COUNT; +#endif #endif #endif -#ifdef CONFIG_CENTOS_7 - wiphy->wowlan = &wowlan_stub; +#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)) + wiphy->wowlan = wowlan_stub; #else - #if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) - #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)) - wiphy->wowlan = wowlan_stub; - #else - wiphy->wowlan = &wowlan_stub; - #endif - #endif + wiphy->wowlan = &wowlan_stub; +#endif #endif #if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) @@ -6875,7 +9050,197 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) /* wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM; */ #endif + +#ifdef CONFIG_RTW_MESH + wiphy->flags |= 0 + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + | WIPHY_FLAG_IBSS_RSN + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) + | WIPHY_FLAG_MESH_AUTH + #endif + ; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + wiphy->features |= 0 + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + | NL80211_FEATURE_USERSPACE_MPM + #endif + ; +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) */ +#endif /* CONFIG_RTW_MESH */ +} + +#ifdef CONFIG_RFKILL_POLL +void rtw_cfg80211_init_rfkill(struct wiphy *wiphy) +{ + wiphy_rfkill_set_hw_state(wiphy, 0); + wiphy_rfkill_start_polling(wiphy); +} + +void rtw_cfg80211_deinit_rfkill(struct wiphy *wiphy) +{ + wiphy_rfkill_stop_polling(wiphy); +} + +static void cfg80211_rtw_rfkill_poll(struct wiphy *wiphy) +{ + _adapter *padapter = NULL; + bool blocked = _FALSE; + u8 valid = 0; + + padapter = wiphy_to_adapter(wiphy); + + if (adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) { + /*RTW_INFO("cfg80211_rtw_rfkill_poll: device is removed!\n");*/ + return; + } + + blocked = rtw_hal_rfkill_poll(padapter, &valid); + /*RTW_INFO("cfg80211_rtw_rfkill_poll: valid=%d, blocked=%d\n", + valid, blocked);*/ + + if (valid) + wiphy_rfkill_set_hw_state(wiphy, blocked); +} +#endif + +#if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)) +#define SURVEY_INFO_TIME SURVEY_INFO_CHANNEL_TIME +#define SURVEY_INFO_TIME_BUSY SURVEY_INFO_CHANNEL_TIME_BUSY +#define SURVEY_INFO_TIME_EXT_BUSY SURVEY_INFO_CHANNEL_TIME_EXT_BUSY +#define SURVEY_INFO_TIME_RX SURVEY_INFO_CHANNEL_TIME_RX +#define SURVEY_INFO_TIME_TX SURVEY_INFO_CHANNEL_TIME_TX +#endif + +#ifdef CONFIG_FIND_BEST_CHANNEL +static void rtw_cfg80211_set_survey_info_with_find_best_channel(struct wiphy *wiphy + , struct net_device *netdev, int idx, struct survey_info *info) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + RT_CHANNEL_INFO *ch_set = rfctl->channel_set; + u8 ch_num = rfctl->max_chan_nums; + u32 total_rx_cnt = 0; + int i; + + s8 noise = -50; /*channel noise in dBm. This and all following fields are optional */ + u64 time = 100; /*amount of time in ms the radio was turn on (on the channel)*/ + u64 time_busy = 0; /*amount of time the primary channel was sensed busy*/ + + info->filled = SURVEY_INFO_NOISE_DBM + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + | SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY + #endif + ; + + for (i = 0; i < ch_num; i++) + total_rx_cnt += ch_set[i].rx_count; + + time_busy = ch_set[idx].rx_count * time / total_rx_cnt; + noise += ch_set[idx].rx_count * 50 / total_rx_cnt; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)) + info->channel_time = time; + info->channel_time_busy = time_busy; + #else + info->time = time; + info->time_busy = time_busy; + #endif +#endif + info->noise = noise; + + /* reset if final channel is got */ + if (idx == ch_num - 1) { + for (i = 0; i < ch_num; i++) + ch_set[i].rx_count = 0; + } +} +#endif /* CONFIG_FIND_BEST_CHANNEL */ + +#if defined(CONFIG_RTW_ACS) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) +static void rtw_cfg80211_set_survey_info_with_clm(PADAPTER padapter, int idx, struct survey_info *pinfo) +{ + s8 noise = -50; /*channel noise in dBm. This and all following fields are optional */ + u64 time = SURVEY_TO; /*amount of time in ms the radio was turn on (on the channel)*/ + u64 time_busy = 0; /*amount of time the primary channel was sensed busy*/ + u8 chan = (u8)idx; + + if ((idx < 0) || (pinfo == NULL)) + return; + + pinfo->filled = SURVEY_INFO_NOISE_DBM + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + | SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY + #endif + ; + + time_busy = rtw_acs_get_clm_ratio_by_ch_idx(padapter, chan); + noise = rtw_noise_query_by_chan_idx(padapter, chan); + /* RTW_INFO("%s: ch-idx:%d time=%llu(ms), time_busy=%llu(ms), noise=%d(dbm)\n", __func__, idx, time, time_busy, noise); */ + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)) + pinfo->channel_time = time; + pinfo->channel_time_busy = time_busy; + #else + pinfo->time = time; + pinfo->time_busy = time_busy; + #endif +#endif + pinfo->noise = noise; +} +#endif + +int rtw_hostapd_acs_dump_survey(struct wiphy *wiphy, struct net_device *netdev, int idx, struct survey_info *info) +{ + PADAPTER padapter = (_adapter *)rtw_netdev_priv(netdev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + RT_CHANNEL_INFO *pch_set = rfctl->channel_set; + u8 max_chan_nums = rfctl->max_chan_nums; + u32 freq = 0; + u8 ret = 0; + u16 channel = 0; + + if (!netdev || !info) { + RTW_INFO("%s: invial parameters.\n", __func__); + return -EINVAL; + } + + _rtw_memset(info, 0, sizeof(struct survey_info)); + if (padapter->bup == _FALSE) { + RTW_INFO("%s: net device is down.\n", __func__); + return -EIO; + } + + if (idx >= max_chan_nums) + return -ENOENT; + + channel = pch_set[idx].ChannelNum; + freq = rtw_ch2freq(channel); + info->channel = ieee80211_get_channel(wiphy, freq); + /* RTW_INFO("%s: channel %d, freq %d\n", __func__, channel, freq); */ + + if (!info->channel) + return -EINVAL; + + if (info->channel->flags == IEEE80211_CHAN_DISABLED) + return ret; + +#ifdef CONFIG_FIND_BEST_CHANNEL + rtw_cfg80211_set_survey_info_with_find_best_channel(wiphy, netdev, idx, info); +#elif defined(CONFIG_RTW_ACS) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) + rtw_cfg80211_set_survey_info_with_clm(padapter, idx, info); +#else + RTW_ERR("%s: unknown acs operation!\n", __func__); +#endif + + return ret; } +#endif /* defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) */ static struct cfg80211_ops rtw_cfg80211_ops = { .change_virtual_intf = cfg80211_rtw_change_iface, @@ -6883,6 +9248,9 @@ static struct cfg80211_ops rtw_cfg80211_ops = { .get_key = cfg80211_rtw_get_key, .del_key = cfg80211_rtw_del_key, .set_default_key = cfg80211_rtw_set_default_key, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)) + .set_default_mgmt_key = cfg80211_rtw_set_default_mgmt_key, +#endif #if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) .set_rekey_data = cfg80211_rtw_set_rekey_data, #endif /*CONFIG_GTK_OL*/ @@ -6930,6 +9298,22 @@ static struct cfg80211_ops rtw_cfg80211_ops = { /* .assoc = cfg80211_rtw_assoc, */ #endif /* CONFIG_AP_MODE */ +#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) + .get_mesh_config = cfg80211_rtw_get_mesh_config, + .update_mesh_config = cfg80211_rtw_update_mesh_config, + .join_mesh = cfg80211_rtw_join_mesh, + .leave_mesh = cfg80211_rtw_leave_mesh, + .add_mpath = cfg80211_rtw_add_mpath, + .del_mpath = cfg80211_rtw_del_mpath, + .change_mpath = cfg80211_rtw_change_mpath, + .get_mpath = cfg80211_rtw_get_mpath, + .dump_mpath = cfg80211_rtw_dump_mpath, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) + .get_mpp = cfg80211_rtw_get_mpp, + .dump_mpp = cfg80211_rtw_dump_mpp, + #endif +#endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) .set_monitor_channel = cfg80211_rtw_set_monitor_channel, #endif @@ -6962,7 +9346,15 @@ static struct cfg80211_ops rtw_cfg80211_ops = { #if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) .sched_scan_start = cfg80211_rtw_sched_scan_start, .sched_scan_stop = cfg80211_rtw_sched_scan_stop, + .suspend = cfg80211_rtw_suspend, + .resume = cfg80211_rtw_resume, #endif /* CONFIG_PNO_SUPPORT */ +#ifdef CONFIG_RFKILL_POLL + .rfkill_poll = cfg80211_rtw_rfkill_poll, +#endif +#if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) + .dump_survey = rtw_hostapd_acs_dump_survey, +#endif }; struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev) @@ -7204,6 +9596,10 @@ int rtw_cfg80211_ndev_res_register(_adapter *adapter) RTW_INFO("%s rtw_wiphy_register fail for if%d\n", __func__, (adapter->iface_id + 1)); goto exit; } + +#ifdef CONFIG_RFKILL_POLL + rtw_cfg80211_init_rfkill(adapter_to_wiphy(adapter)); +#endif #endif ret = _SUCCESS; @@ -7253,6 +9649,10 @@ int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj) #if defined(RTW_SINGLE_WIPHY) if (rtw_wiphy_register(dvobj_to_wiphy(dvobj)) != 0) goto exit; + +#ifdef CONFIG_RFKILL_POLL + rtw_cfg80211_init_rfkill(dvobj_to_wiphy(dvobj)); +#endif #endif ret = _SUCCESS; @@ -7264,6 +9664,9 @@ int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj) void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj) { #if defined(RTW_SINGLE_WIPHY) +#ifdef CONFIG_RFKILL_POLL + rtw_cfg80211_deinit_rfkill(dvobj_to_wiphy(dvobj)); +#endif rtw_wiphy_unregister(dvobj_to_wiphy(dvobj)); #endif } diff --git a/os_dep/linux/ioctl_cfg80211.h b/os_dep/linux/ioctl_cfg80211.h index 2e5e06f..54a319f 100644 --- a/os_dep/linux/ioctl_cfg80211.h +++ b/os_dep/linux/ioctl_cfg80211.h @@ -15,9 +15,12 @@ #ifndef __IOCTL_CFG80211_H__ #define __IOCTL_CFG80211_H__ - #ifndef RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT - #define RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT 0 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) +#define RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT 1 +#else +#define RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT 0 +#endif #endif #if defined(RTW_USE_CFG80211_STA_EVENT) @@ -50,6 +53,11 @@ #endif #endif +#ifndef CONFIG_RADIO_WORK +#define RTW_ROCH_DURATION_ENLARGE +#define RTW_ROCH_BACK_OP +#endif + #if !defined(CONFIG_P2P) && RTW_P2P_GROUP_INTERFACE #error "RTW_P2P_GROUP_INTERFACE can't be enabled when CONFIG_P2P is disabled\n" #endif @@ -62,6 +70,12 @@ #error "RTW_DEDICATED_P2P_DEVICE can't be enabled when kernel < 3.7.0\n" #endif +#ifdef CONFIG_RTW_MESH + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)) + #error "CONFIG_RTW_MESH can't be enabled when kernel < 3.10.0\n" + #endif +#endif + struct rtw_wdev_invit_info { u8 state; /* 0: req, 1:rep */ u8 peer_mac[ETH_ALEN]; @@ -139,7 +153,7 @@ struct rtw_wdev_priv { char ifname_mon[IFNAMSIZ + 1]; /* interface name for monitor interface */ u8 p2p_enabled; - u32 probe_resp_ie_update_time; + systime probe_resp_ie_update_time; u8 provdisc_req_issued; @@ -155,6 +169,7 @@ struct rtw_wdev_priv { u16 report_mgmt; u8 is_mgmt_tx; + u16 mgmt_tx_cookie; _mutex roch_mutex; @@ -164,6 +179,8 @@ struct rtw_wdev_priv { }; +bool rtw_cfg80211_is_connect_requested(_adapter *adapter); + #if RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT #define rtw_wdev_not_indic_disco(rtw_wdev_data) 0 #define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do {} while (0) @@ -257,12 +274,15 @@ void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_ab #ifdef CONFIG_AP_MODE void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); -void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason); +void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason); #endif /* CONFIG_AP_MODE */ #ifdef CONFIG_P2P void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val); bool rtw_cfg80211_get_is_roch(_adapter *adapter); +bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter); +void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter); +s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter); int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter); int rtw_cfg80211_is_p2p_scan(_adapter *adapter); @@ -276,17 +296,27 @@ void rtw_pd_iface_free(struct wiphy *wiphy); void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val); u8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter); +u8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf); void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len); void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, union recv_frame *rframe); void rtw_cfg80211_rx_action_p2p(_adapter *padapter, union recv_frame *rframe); void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg); +void rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const char *msg); void rtw_cfg80211_rx_probe_request(_adapter *padapter, union recv_frame *rframe); int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type); bool rtw_cfg80211_pwr_mgmt(_adapter *adapter); +#ifdef CONFIG_RTW_80211K +void rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe); +#endif + +#ifdef CONFIG_RFKILL_POLL +void rtw_cfg80211_init_rfkill(struct wiphy *wiphy); +void rtw_cfg80211_deinit_rfkill(struct wiphy *wiphy); +#endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE) #define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, buf, len, gfp) @@ -325,15 +355,11 @@ bool rtw_cfg80211_pwr_mgmt(_adapter *adapter); #define rtw_cfg80211_connect_result(wdev, bssid, req_ie, req_ie_len, resp_ie, resp_ie_len, status, gfp) cfg80211_connect_result(wdev_to_ndev(wdev), bssid, req_ie, req_ie_len, resp_ie, resp_ie_len, status, gfp) -#ifdef CONFIG_CENTOS_7 -#define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, locally_generated, gfp) -#else #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0)) #define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, gfp) #else #define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, locally_generated, gfp) #endif -#endif #ifdef CONFIG_RTW_80211R #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) @@ -343,13 +369,27 @@ bool rtw_cfg80211_pwr_mgmt(_adapter *adapter); #endif #endif -#ifdef CONFIG_CENTOS_7 -#else -#if (KERNEL_VERSION(4, 7, 0) >= LINUX_VERSION_CODE) -#define NUM_NL80211_BANDS IEEE80211_NUM_BANDS +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +#define rtw_cfg80211_notify_new_peer_candidate(wdev, addr, ie, ie_len, gfp) cfg80211_notify_new_peer_candidate(wdev_to_ndev(wdev), addr, ie, ie_len, gfp) #endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) +u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, u8 ht); #endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0)) +#define NL80211_BAND_2GHZ IEEE80211_BAND_2GHZ +#define NL80211_BAND_5GHZ IEEE80211_BAND_5GHZ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#define NL80211_BAND_60GHZ IEEE80211_BAND_60GHZ +#endif +#define NUM_NL80211_BANDS IEEE80211_NUM_BANDS +#endif + +#define rtw_band_to_nl80211_band(band) \ + (band == BAND_ON_2_4G) ? NL80211_BAND_2GHZ : \ + (band == BAND_ON_5G) ? NL80211_BAND_5GHZ : NUM_NL80211_BANDS + #include "rtw_cfgvendor.h" #endif /* __IOCTL_CFG80211_H__ */ diff --git a/os_dep/linux/ioctl_linux.c b/os_dep/linux/ioctl_linux.c index 3609a77..3ff1564 100644 --- a/os_dep/linux/ioctl_linux.c +++ b/os_dep/linux/ioctl_linux.c @@ -68,29 +68,6 @@ static const char *const iw_operation_mode[] = { "Auto", "Ad-Hoc", "Managed", "Master", "Repeater", "Secondary", "Monitor" }; -static int hex2num_i(char c) -{ - if (c >= '0' && c <= '9') - return c - '0'; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - if (c >= 'A' && c <= 'F') - return c - 'A' + 10; - return -1; -} - -static int hex2byte_i(const char *hex) -{ - int a, b; - a = hex2num_i(*hex++); - if (a < 0) - return -1; - b = hex2num_i(*hex++); - if (b < 0) - return -1; - return (a << 4) | b; -} - /** * hwaddr_aton - Convert ASCII string to MAC address * @txt: MAC address as a string (e.g., "00:11:22:33:44:55") @@ -441,7 +418,7 @@ static inline char *iwe_stream_protocol_process(_adapter *padapter, u16 ht_cap = _FALSE, vht_cap = _FALSE; u32 ht_ielen = 0, vht_ielen = 0; char *p; - u8 ie_offset = (pnetwork->network.Reserved[0] == 2 ? 0 : 12); /* Probe Request */ + u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); /* Probe Request */ /* parsing HT_CAP_IE */ p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset); @@ -501,7 +478,7 @@ static inline char *iwe_stream_rate_process(_adapter *padapter, u8 bw_40MHz = 0, short_GI = 0, bw_160MHz = 0, vht_highest_rate = 0; u16 mcs_rate = 0, vht_data_rate = 0; char custom[MAX_CUSTOM_LEN] = {0}; - u8 ie_offset = (pnetwork->network.Reserved[0] == 2 ? 0 : 12); /* Probe Request */ + u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); /* Probe Request */ /* parsing HT_CAP_IE */ p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset); @@ -589,7 +566,7 @@ static inline char *iwe_stream_wpa_wpa2_process(_adapter *padapter, p = pbuf; /* parsing WPA/WPA2 IE */ - if (pnetwork->network.Reserved[0] != 2) { /* Probe Request */ + if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ) { /* Probe Request */ out_len = rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, rsn_ie, &rsn_len, wpa_ie, &wpa_len); if (wpa_len > 0) { @@ -648,12 +625,12 @@ static inline char *iwe_stream_wps_process(_adapter *padapter, uint cnt = 0, total_ielen; u8 *wpsie_ptr = NULL; uint wps_ielen = 0; - u8 ie_offset = (pnetwork->network.Reserved[0] == 2 ? 0 : 12); + u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); u8 *ie_ptr = pnetwork->network.IEs + ie_offset; total_ielen = pnetwork->network.IELength - ie_offset; - if (pnetwork->network.Reserved[0] == 2) { /* Probe Request */ + if (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ) { /* Probe Request */ ie_ptr = pnetwork->network.IEs; total_ielen = pnetwork->network.IELength; } else { /* Beacon or Probe Respones */ @@ -679,7 +656,7 @@ static inline char *iwe_stream_wapi_process(_adapter *padapter, #ifdef CONFIG_WAPI_SUPPORT char *p; - if (pnetwork->network.Reserved[0] != 2) { /* Probe Request */ + if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ) { /* Probe Request */ sint out_len_wapi = 0; /* here use static for stack size */ static u8 buf_wapi[MAX_WAPI_IE_LEN * 2] = {0}; @@ -720,12 +697,13 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, char *start, char *stop, struct iw_event *iwe) { u8 ss, sq; + s16 noise = 0; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); /* Add quality statistics */ iwe->cmd = IWEVQUAL; iwe->u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR | IW_QUAL_NOISE_UPDATED #else | IW_QUAL_NOISE_INVALID @@ -756,7 +734,7 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); - iwe->u.qual.level = (u8)odm_signal_scale_mapping(&pHal->odmpriv, ss); + iwe->u.qual.level = (u8)phydm_signal_scale_mapping(&pHal->odmpriv, ss); } #endif #endif @@ -766,11 +744,13 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, #ifdef CONFIG_PLATFORM_ROCKCHIPS iwe->u.qual.noise = -100; /* noise level suggest by zhf@rockchips */ #else -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - { - s16 tmp_noise = 0; - rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &(pnetwork->network.Configuration.DSConfig), &(tmp_noise)); - iwe->u.qual.noise = tmp_noise ; +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + if (IS_NM_ENABLE(padapter)) { + noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig); + #ifndef CONFIG_SIGNAL_DISPLAY_DBM + noise = translate_dbm_to_percentage(noise);/*percentage*/ + #endif + iwe->u.qual.noise = noise; } #else iwe->u.qual.noise = 0; /* noise level */ @@ -801,7 +781,6 @@ static inline char *iwe_stream_net_rsv_process(_adapter *padapter, return start; } -#if 1 static char *translate_scan(_adapter *padapter, struct iw_request_info *info, struct wlan_network *pnetwork, char *start, char *stop) @@ -816,7 +795,7 @@ static char *translate_scan(_adapter *padapter, start = iwe_stream_mac_addr_proess(padapter, info, pnetwork, start, stop, &iwe); start = iwe_stream_essid_proess(padapter, info, pnetwork, start, stop, &iwe); start = iwe_stream_protocol_process(padapter, info, pnetwork, start, stop, &iwe); - if (pnetwork->network.Reserved[0] == 2) /* Probe Request */ + if (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ) /* Probe Request */ cap = 0; else { _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2); @@ -835,374 +814,6 @@ static char *translate_scan(_adapter *padapter, return start; } -#else -static char *translate_scan(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop) -{ - struct iw_event iwe; - u16 cap; - u32 ht_ielen = 0, vht_ielen = 0; - char custom[MAX_CUSTOM_LEN]; - char *p; - u16 max_rate = 0, rate, ht_cap = _FALSE, vht_cap = _FALSE; - u32 i = 0; - char *current_val; - long rssi; - u8 bw_40MHz = 0, short_GI = 0, bw_160MHz = 0, vht_highest_rate = 0; - u16 mcs_rate = 0, vht_data_rate = 0; - u8 ie_offset = (pnetwork->network.Reserved[0] == 2 ? 0 : 12); - struct registry_priv *pregpriv = &padapter->registrypriv; - - if (_FALSE == search_p2p_wfd_ie(padapter, info, pnetwork, start, stop)) - return start; - - /* AP MAC address */ - iwe.cmd = SIOCGIWAP; - iwe.u.ap_addr.sa_family = ARPHRD_ETHER; - - _rtw_memcpy(iwe.u.ap_addr.sa_data, pnetwork->network.MacAddress, ETH_ALEN); - start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_ADDR_LEN); - - /* Add the ESSID */ - iwe.cmd = SIOCGIWESSID; - iwe.u.data.flags = 1; - iwe.u.data.length = min((u16)pnetwork->network.Ssid.SsidLength, (u16)32); - start = iwe_stream_add_point(info, start, stop, &iwe, pnetwork->network.Ssid.Ssid); - - /* parsing HT_CAP_IE */ - if (pnetwork->network.Reserved[0] == 2) /* Probe Request */ - p = rtw_get_ie(&pnetwork->network.IEs[0], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength); - else - p = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - 12); - if (p && ht_ielen > 0) { - struct rtw_ieee80211_ht_cap *pht_capie; - ht_cap = _TRUE; - pht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2); - _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2); - bw_40MHz = (pht_capie->cap_info & IEEE80211_HT_CAP_SUP_WIDTH) ? 1 : 0; - short_GI = (pht_capie->cap_info & (IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40)) ? 1 : 0; - } - -#ifdef CONFIG_80211AC_VHT - /* parsing VHT_CAP_IE */ - p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset); - if (p && vht_ielen > 0) { - u8 mcs_map[2]; - - vht_cap = _TRUE; - bw_160MHz = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2); - if (bw_160MHz) - short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI160M(p + 2); - else - short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI80M(p + 2); - - _rtw_memcpy(mcs_map, GET_VHT_CAPABILITY_ELE_TX_MCS(p + 2), 2); - - vht_highest_rate = rtw_get_vht_highest_rate(mcs_map); - vht_data_rate = rtw_vht_mcs_to_data_rate(CHANNEL_WIDTH_80, short_GI, vht_highest_rate); - } -#endif - - /* Add the protocol name */ - iwe.cmd = SIOCGIWNAME; - if ((rtw_is_cckratesonly_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) { - if (ht_cap == _TRUE) - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bn"); - else - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b"); - } else if ((rtw_is_cckrates_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) { - if (ht_cap == _TRUE) - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bgn"); - else - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bg"); - } else { - if (pnetwork->network.Configuration.DSConfig > 14) { - if (vht_cap == _TRUE) - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11AC"); - else if (ht_cap == _TRUE) - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11an"); - else - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a"); - } else { - if (ht_cap == _TRUE) - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11gn"); - else - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g"); - } - } - - start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_CHAR_LEN); - - /* Add mode */ - if (pnetwork->network.Reserved[0] == 2) /* Probe Request */ - cap = 0; - else { - iwe.cmd = SIOCGIWMODE; - _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2); - cap = le16_to_cpu(cap); - } - - if (cap & (WLAN_CAPABILITY_IBSS | WLAN_CAPABILITY_BSS)) { - if (cap & WLAN_CAPABILITY_BSS) - iwe.u.mode = IW_MODE_MASTER; - else - iwe.u.mode = IW_MODE_ADHOC; - - start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_UINT_LEN); - } - - if (pnetwork->network.Configuration.DSConfig < 1 /*|| pnetwork->network.Configuration.DSConfig>14*/) - pnetwork->network.Configuration.DSConfig = 1; - - /* Add frequency/channel */ - iwe.cmd = SIOCGIWFREQ; - iwe.u.freq.m = rtw_ch2freq(pnetwork->network.Configuration.DSConfig) * 100000; - iwe.u.freq.e = 1; - iwe.u.freq.i = pnetwork->network.Configuration.DSConfig; - start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_FREQ_LEN); - - /* Add encryption capability */ - iwe.cmd = SIOCGIWENCODE; - if (cap & WLAN_CAPABILITY_PRIVACY) - iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; - else - iwe.u.data.flags = IW_ENCODE_DISABLED; - iwe.u.data.length = 0; - start = iwe_stream_add_point(info, start, stop, &iwe, pnetwork->network.Ssid.Ssid); - - /*Add basic and extended rates */ - max_rate = 0; - p = custom; - p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): "); - while (pnetwork->network.SupportedRates[i] != 0) { - rate = pnetwork->network.SupportedRates[i] & 0x7F; - if (rate > max_rate) - max_rate = rate; - p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), - "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); - i++; - } - - if (vht_cap == _TRUE) - max_rate = vht_data_rate; - else if (ht_cap == _TRUE) { - if (mcs_rate & 0x8000) /* MCS15 */ - max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130); - - else if (mcs_rate & 0x0080) /* MCS7 */ - max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65); - else { /* default MCS7 */ - /* RTW_INFO("wx_get_scan, mcs_rate_bitmap=0x%x\n", mcs_rate); */ - max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65); - } - - max_rate = max_rate * 2; /* Mbps/2; */ - } - - iwe.cmd = SIOCGIWRATE; - iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0; - iwe.u.bitrate.value = max_rate * 500000; - start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_PARAM_LEN); - - /* parsing WPA/WPA2 IE */ - if (pnetwork->network.Reserved[0] != 2) { /* Probe Request */ - u8 buf[MAX_WPA_IE_LEN * 2]; - u8 wpa_ie[255], rsn_ie[255]; - u16 wpa_len = 0, rsn_len = 0; - u8 *p; - sint out_len = 0; - out_len = rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, rsn_ie, &rsn_len, wpa_ie, &wpa_len); - - if (wpa_len > 0) { - p = buf; - _rtw_memset(buf, 0, MAX_WPA_IE_LEN * 2); - p += sprintf(p, "wpa_ie="); - for (i = 0; i < wpa_len; i++) - p += sprintf(p, "%02x", wpa_ie[i]); - - if (wpa_len > 100) { - printk("-----------------Len %d----------------\n", wpa_len); - for (i = 0; i < wpa_len; i++) - printk("%02x ", wpa_ie[i]); - printk("\n"); - printk("-----------------Len %d----------------\n", wpa_len); - } - - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVCUSTOM; - iwe.u.data.length = strlen(buf); - start = iwe_stream_add_point(info, start, stop, &iwe, buf); - - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVGENIE; - iwe.u.data.length = wpa_len; - start = iwe_stream_add_point(info, start, stop, &iwe, wpa_ie); - } - if (rsn_len > 0) { - p = buf; - _rtw_memset(buf, 0, MAX_WPA_IE_LEN * 2); - p += sprintf(p, "rsn_ie="); - for (i = 0; i < rsn_len; i++) - p += sprintf(p, "%02x", rsn_ie[i]); - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVCUSTOM; - iwe.u.data.length = strlen(buf); - start = iwe_stream_add_point(info, start, stop, &iwe, buf); - - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVGENIE; - iwe.u.data.length = rsn_len; - start = iwe_stream_add_point(info, start, stop, &iwe, rsn_ie); - } - } - - { /* parsing WPS IE */ - uint cnt = 0, total_ielen; - u8 *wpsie_ptr = NULL; - uint wps_ielen = 0; - - u8 *ie_ptr = pnetwork->network.IEs + ie_offset; - total_ielen = pnetwork->network.IELength - ie_offset; - - if (pnetwork->network.Reserved[0] == 2) { /* Probe Request */ - ie_ptr = pnetwork->network.IEs; - total_ielen = pnetwork->network.IELength; - } else { /* Beacon or Probe Respones */ - ie_ptr = pnetwork->network.IEs + _FIXED_IE_LENGTH_; - total_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_; - } - - while (cnt < total_ielen) { - if (rtw_is_wps_ie(&ie_ptr[cnt], &wps_ielen) && (wps_ielen > 2)) { - wpsie_ptr = &ie_ptr[cnt]; - iwe.cmd = IWEVGENIE; - iwe.u.data.length = (u16)wps_ielen; - start = iwe_stream_add_point(info, start, stop, &iwe, wpsie_ptr); - } - cnt += ie_ptr[cnt + 1] + 2; /* goto next */ - } - } - -#ifdef CONFIG_WAPI_SUPPORT - if (pnetwork->network.Reserved[0] != 2) { /* Probe Request */ - sint out_len_wapi = 0; - /* here use static for stack size */ - static u8 buf_wapi[MAX_WAPI_IE_LEN * 2]; - static u8 wapi_ie[MAX_WAPI_IE_LEN]; - u16 wapi_len = 0; - u16 i; - - _rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN); - _rtw_memset(wapi_ie, 0, MAX_WAPI_IE_LEN); - - out_len_wapi = rtw_get_wapi_ie(pnetwork->network.IEs , pnetwork->network.IELength, wapi_ie, &wapi_len); - - RTW_INFO("rtw_wx_get_scan: %s ", pnetwork->network.Ssid.Ssid); - RTW_INFO("rtw_wx_get_scan: ssid = %d ", wapi_len); - - - if (wapi_len > 0) { - p = buf_wapi; - _rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN * 2); - p += sprintf(p, "wapi_ie="); - for (i = 0; i < wapi_len; i++) - p += sprintf(p, "%02x", wapi_ie[i]); - - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVCUSTOM; - iwe.u.data.length = strlen(buf_wapi); - start = iwe_stream_add_point(info, start, stop, &iwe, buf_wapi); - - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVGENIE; - iwe.u.data.length = wapi_len; - start = iwe_stream_add_point(info, start, stop, &iwe, wapi_ie); - } - } -#endif - - { - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - u8 ss, sq; - - /* Add quality statistics */ - iwe.cmd = IWEVQUAL; - iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - | IW_QUAL_NOISE_UPDATED -#else - | IW_QUAL_NOISE_INVALID -#endif -#ifdef CONFIG_SIGNAL_DISPLAY_DBM - | IW_QUAL_DBM -#endif - ; - - if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && - is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { - ss = padapter->recvpriv.signal_strength; - sq = padapter->recvpriv.signal_qual; - } else { - ss = pnetwork->network.PhyInfo.SignalStrength; - sq = pnetwork->network.PhyInfo.SignalQuality; - } - - -#ifdef CONFIG_SIGNAL_DISPLAY_DBM - iwe.u.qual.level = (u8) translate_percentage_to_dbm(ss); /* dbm */ -#else -#ifdef CONFIG_SIGNAL_SCALE_MAPPING - iwe.u.qual.level = (u8)ss; /* % */ -#else - { - /* Do signal scale mapping when using percentage as the unit of signal strength, since the scale mapping is skipped in odm */ - - HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); - - iwe.u.qual.level = (u8)odm_signal_scale_mapping(&pHal->odmpriv, ss); - } -#endif -#endif - - iwe.u.qual.qual = (u8)sq; /* signal quality */ - -#ifdef CONFIG_PLATFORM_ROCKCHIPS - iwe.u.qual.noise = -100; /* noise level suggest by zhf@rockchips */ -#else -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - { - s16 tmp_noise = 0; - rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &(pnetwork->network.Configuration.DSConfig), &(tmp_noise)); - iwe.u.qual.noise = tmp_noise ; - } -#else - iwe.u.qual.noise = 0; /* noise level */ -#endif -#endif /* CONFIG_PLATFORM_ROCKCHIPS */ - - /* RTW_INFO("iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\n", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated); */ - - start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_QUAL_LEN); - } - - { - u8 buf[MAX_WPA_IE_LEN]; - u8 *p, *pos; - int len; - p = buf; - pos = pnetwork->network.Reserved; - _rtw_memset(buf, 0, MAX_WPA_IE_LEN); - p += sprintf(p, "fm=%02X%02X", pos[1], pos[0]); - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVCUSTOM; - iwe.u.data.length = strlen(buf); - start = iwe_stream_add_point(info, start, stop, &iwe, buf); - } - - return start; -} -#endif static int wpa_set_auth_algs(struct net_device *dev, u32 value) { @@ -1297,7 +908,7 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, wep_key_idx = param->u.crypt.idx; wep_key_len = param->u.crypt.key_len; - if ((wep_key_idx > WEP_KEYS) || (wep_key_len <= 0)) { + if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) { ret = -EINVAL; goto exit; } @@ -1325,6 +936,7 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, psecuritypriv->key_mask |= BIT(wep_key_idx); + padapter->mlmeextpriv.mlmext_info.key_index = wep_key_idx; goto exit; } @@ -1346,25 +958,23 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; if (param->u.crypt.set_tx == 1) { /* pairwise key */ + RTW_INFO(FUNC_ADPT_FMT" set %s PTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - if (strcmp(param->u.crypt.alg, "TKIP") == 0) { /* set mic key */ - /* DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); */ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); - padapter->securitypriv.busetkipkey = _FALSE; } - - /* DEBUG_ERR((" param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); */ - RTW_INFO(" ~~~~set sta key:unicastkey\n"); - - rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE); - + psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); + psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq); psta->bpairwise_key_installed = _TRUE; + rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE); } else { /* group key */ if (strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set %s GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); /* only TKIP group key need to install this */ @@ -1373,29 +983,23 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); } padapter->securitypriv.binstallGrpkey = _TRUE; - /* DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); */ - RTW_INFO(" ~~~~set sta key:groupkey\n"); - + if (param->u.crypt.idx < 4) + _rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8); padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx; - rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE); - } -#ifdef CONFIG_IEEE80211W - else if (strcmp(param->u.crypt.alg, "BIP") == 0) { - int no; - /* printk("BIP key_len=%d , index=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.key_len, param->u.crypt.idx); */ - /* save the IGTK key, length 16 bytes */ + + #ifdef CONFIG_IEEE80211W + } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set IGTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - /*printk("IGTK key below:\n"); - for(no=0;no<16;no++) - printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); - printk("\n");*/ - padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; - padapter->securitypriv.binstallBIPkey = _TRUE; - RTW_INFO(" ~~~~set sta key:IGKT\n"); + psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx; + psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq); + psecuritypriv->binstallBIPkey = _TRUE; + #endif /* CONFIG_IEEE80211W */ + } -#endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_P2P if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) @@ -1422,61 +1026,8 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, } #ifdef CONFIG_WAPI_SUPPORT - if (strcmp(param->u.crypt.alg, "SMS4") == 0) { - PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; - PRT_WAPI_STA_INFO pWapiSta; - u8 WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - - if (param->u.crypt.set_tx == 1) { - list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { - if (_rtw_memcmp(pWapiSta->PeerMacAddr, param->sta_addr, 6)) { - _rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16); - - pWapiSta->wapiUsk.bSet = true; - _rtw_memcpy(pWapiSta->wapiUsk.dataKey, param->u.crypt.key, 16); - _rtw_memcpy(pWapiSta->wapiUsk.micKey, param->u.crypt.key + 16, 16); - pWapiSta->wapiUsk.keyId = param->u.crypt.idx ; - pWapiSta->wapiUsk.bTxEnable = true; - - _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16); - pWapiSta->wapiUskUpdate.bTxEnable = false; - pWapiSta->wapiUskUpdate.bSet = false; - - if (psecuritypriv->sw_encrypt == false || psecuritypriv->sw_decrypt == false) { - /* set unicast key for ASUE */ - rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false); - } - } - } - } else { - list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { - if (_rtw_memcmp(pWapiSta->PeerMacAddr, get_bssid(pmlmepriv), 6)) { - pWapiSta->wapiMsk.bSet = true; - _rtw_memcpy(pWapiSta->wapiMsk.dataKey, param->u.crypt.key, 16); - _rtw_memcpy(pWapiSta->wapiMsk.micKey, param->u.crypt.key + 16, 16); - pWapiSta->wapiMsk.keyId = param->u.crypt.idx ; - pWapiSta->wapiMsk.bTxEnable = false; - if (!pWapiSta->bSetkeyOk) - pWapiSta->bSetkeyOk = true; - pWapiSta->bAuthenticateInProgress = false; - - _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); - - if (psecuritypriv->sw_decrypt == false) { - /* set rx broadcast key for ASUE */ - rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false); - } - } - - } - } - } + if (strcmp(param->u.crypt.alg, "SMS4") == 0) + rtw_wapi_set_set_encryption(padapter, param); #endif exit: @@ -1490,6 +1041,7 @@ static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) u8 *buf = NULL, *pos = NULL; u32 left; int group_cipher = 0, pairwise_cipher = 0; + u8 mfp_opt = MFP_NO; int ret = 0; u8 null_addr[] = {0, 0, 0, 0, 0, 0}; #ifdef CONFIG_P2P @@ -1527,26 +1079,13 @@ static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) goto exit; } -#if 0 - pos += RSN_HEADER_LEN; - left = ielen - RSN_HEADER_LEN; - - if (left >= RSN_SELECTOR_LEN) { - pos += RSN_SELECTOR_LEN; - left -= RSN_SELECTOR_LEN; - } else if (left > 0) { - ret = -1; - goto exit; - } -#endif - if (rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen); } - if (rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + if (rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) { padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen); @@ -1603,6 +1142,13 @@ static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) break; } + if (mfp_opt == MFP_INVALID) { + RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter)); + ret = -EINVAL; + goto exit; + } + padapter->securitypriv.mfp_opt = mfp_opt; + _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); {/* set wps_ie */ u16 cnt = 0; @@ -1731,7 +1277,9 @@ static int rtw_wx_set_freq(struct net_device *dev, int exp = 1, freq = 0, div = 0; - + rtw_ps_deny(padapter, PS_DENY_IOCTL); + if (rtw_pwr_wakeup(padapter) == _FALSE) + goto exit; if (wrqu->freq.m <= 1000) { if (wrqu->freq.flags == IW_FREQ_AUTO) { if (rtw_chset_search_ch(adapter_to_chset(padapter), wrqu->freq.m) > 0) { @@ -1772,9 +1320,8 @@ static int rtw_wx_set_freq(struct net_device *dev, padapter->mlmeextpriv.cur_channel = rtw_freq2ch(freq); RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel); } - rtw_ps_deny(padapter, PS_DENY_IOCTL); - LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */ set_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); +exit: rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); return 0; @@ -1858,7 +1405,6 @@ static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, case IW_MODE_MASTER: networkType = Ndis802_11APMode; RTW_INFO("set_mode = IW_MODE_MASTER\n"); - /* rtw_setopmode_cmd(padapter, networkType,_TRUE); */ break; case IW_MODE_INFRA: networkType = Ndis802_11Infrastructure; @@ -1870,17 +1416,6 @@ static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, goto exit; } - /* - if(Ndis802_11APMode == networkType) - { - rtw_setopmode_cmd(padapter, networkType,_TRUE); - } - else - { - rtw_setopmode_cmd(padapter, Ndis802_11AutoUnknown,_TRUE); - } - */ - if (rtw_set_802_11_infrastructure_mode(padapter, networkType) == _FALSE) { ret = -EPERM; @@ -1888,7 +1423,7 @@ static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, } - rtw_setopmode_cmd(padapter, networkType, _TRUE); + rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK); if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) rtw_indicate_connect(padapter); @@ -2383,7 +1918,9 @@ static int rtw_wx_set_mlme(struct net_device *dev, default: return -EOPNOTSUPP; } - +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_do_disconnect(padapter); +#endif return ret; } @@ -2394,7 +1931,7 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; + struct sitesurvey_parm parm; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); @@ -2437,7 +1974,13 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, goto cancel_ps_deny; } #endif - +#ifdef CONFIG_RTW_REPEATER_SON + if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) { + RTW_INFO(FUNC_ADPT_FMT" blocking scan for under rson scanning process\n", FUNC_ADPT_ARG(padapter)); + indicate_wx_scan_complete_event(padapter); + goto cancel_ps_deny; + } +#endif if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { RTW_INFO("AP mode process WPS\n"); indicate_wx_scan_complete_event(padapter); @@ -2467,8 +2010,6 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, } #endif /* CONFIG_P2P */ - _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID) * RTW_SSID_SCAN_AMOUNT); - #if WIRELESS_EXT >= 17 if (wrqu->data.length == sizeof(struct iw_scan_req)) { struct iw_scan_req *req = (struct iw_scan_req *)extra; @@ -2476,12 +2017,14 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, if (wrqu->data.flags & IW_SCAN_THIS_ESSID) { int len = min((int)req->essid_len, IW_ESSID_MAX_SIZE); - _rtw_memcpy(ssid[0].Ssid, req->essid, len); - ssid[0].SsidLength = len; + rtw_init_sitesurvey_parm(padapter, &parm); + _rtw_memcpy(&parm.ssid[0].Ssid, &req->essid, len); + parm.ssid[0].SsidLength = len; + parm.ssid_num = 1; RTW_INFO("IW_SCAN_THIS_ESSID, ssid=%s, len=%d\n", req->essid, req->essid_len); - _status = rtw_set_802_11_bssid_list_scan(padapter, ssid, 1, NULL, 0); + _status = rtw_set_802_11_bssid_list_scan(padapter, &parm); } else if (req->scan_type == IW_SCAN_TYPE_PASSIVE) RTW_INFO("rtw_wx_set_scan, req->scan_type == IW_SCAN_TYPE_PASSIVE\n"); @@ -2499,6 +2042,7 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, int ssid_index = 0; /* RTW_INFO("%s COMBO_SCAN header is recognized\n", __FUNCTION__); */ + rtw_init_sitesurvey_parm(padapter, &parm); while (len >= 1) { section = *(pos++); @@ -2516,10 +2060,12 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, len -= 1; if (sec_len > 0 && sec_len <= len) { - ssid[ssid_index].SsidLength = sec_len; - _rtw_memcpy(ssid[ssid_index].Ssid, pos, ssid[ssid_index].SsidLength); - /* RTW_INFO("%s COMBO_SCAN with specific ssid:%s, %d\n", __FUNCTION__ */ - /* , ssid[ssid_index].Ssid, ssid[ssid_index].SsidLength); */ + + parm.ssid[ssid_index].SsidLength = sec_len; + _rtw_memcpy(&parm.ssid[ssid_index].Ssid, pos, sec_len); + + /* RTW_INFO("%s COMBO_SCAN with specific parm.ssid:%s, %d\n", __FUNCTION__ */ + /* , parm.ssid[ssid_index].Ssid, parm.ssid[ssid_index].SsidLength); */ ssid_index++; } @@ -2566,13 +2112,14 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, /* RTW_INFO("len:%d\n", len); */ } + parm.ssid_num = ssid_index; /* jeff: it has still some scan paramater to parse, we only do this now... */ - _status = rtw_set_802_11_bssid_list_scan(padapter, ssid, RTW_SSID_SCAN_AMOUNT, NULL, 0); + _status = rtw_set_802_11_bssid_list_scan(padapter, &parm); } else - _status = rtw_set_802_11_bssid_list_scan(padapter, NULL, 0, NULL, 0); + _status = rtw_set_802_11_bssid_list_scan(padapter, NULL); if (_status == _FALSE) ret = -1; @@ -3821,6 +3368,22 @@ static int rtw_wx_priv_null(struct net_device *dev, struct iw_request_info *a, return -1; } +#ifdef CONFIG_RTW_80211K +extern void rm_dbg_cmd(_adapter *padapter, char *s); +static int rtw_wx_priv_rrm(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u32 path, addr, data32; + + + rm_dbg_cmd(padapter, b); + wrqu->data.length = strlen(b); + + return 0; +} +#endif + static int dummy(struct net_device *dev, struct iw_request_info *a, union iwreq_data *wrqu, char *b) { @@ -3887,111 +3450,6 @@ static int rtw_wx_set_mtk_wps_ie(struct net_device *dev, #endif } -/* -typedef int (*iw_handler)(struct net_device *dev, struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); -*/ -/* - * For all data larger than 16 octets, we need to use a - * pointer to memory allocated in user space. - */ -static int rtw_drvext_hdl(struct net_device *dev, struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - -#if 0 - struct iw_point { - void __user *pointer; /* Pointer to the data (in user space) */ - __u16 length; /* number of fields or size in bytes */ - __u16 flags; /* Optional params */ - }; -#endif - -#ifdef CONFIG_DRVEXT_MODULE - u8 res; - struct drvext_handler *phandler; - struct drvext_oidparam *poidparam; - int ret; - u16 len; - u8 *pparmbuf, bset; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *p = &wrqu->data; - - if ((!p->length) || (!p->pointer)) { - ret = -EINVAL; - goto _rtw_drvext_hdl_exit; - } - - - bset = (u8)(p->flags & 0xFFFF); - len = p->length; - pparmbuf = (u8 *)rtw_malloc(len); - if (pparmbuf == NULL) { - ret = -ENOMEM; - goto _rtw_drvext_hdl_exit; - } - - if (bset) { /* set info */ - if (copy_from_user(pparmbuf, p->pointer, len)) { - rtw_mfree(pparmbuf, len); - ret = -EFAULT; - goto _rtw_drvext_hdl_exit; - } - } else { /* query info */ - - } - - - /* */ - poidparam = (struct drvext_oidparam *)pparmbuf; - - - - /* check subcode */ - if (poidparam->subcode >= MAX_DRVEXT_HANDLERS) { - ret = -EINVAL; - goto _rtw_drvext_hdl_exit; - } - - - if (poidparam->subcode >= MAX_DRVEXT_OID_SUBCODES) { - ret = -EINVAL; - goto _rtw_drvext_hdl_exit; - } - - - phandler = drvextoidhandlers + poidparam->subcode; - - if (poidparam->len != phandler->parmsize) { - ret = -EINVAL; - goto _rtw_drvext_hdl_exit; - } - - - res = phandler->handler(&padapter->drvextpriv, bset, poidparam->data); - - if (res == 0) { - ret = 0; - - if (bset == 0x00) {/* query info */ - /* _rtw_memcpy(p->pointer, pparmbuf, len); */ - if (copy_to_user(p->pointer, pparmbuf, len)) - ret = -EFAULT; - } - } else - ret = -EFAULT; - - -_rtw_drvext_hdl_exit: - - return ret; - -#endif - - return 0; - -} - static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len) { pRW_Reg RegRWStruct; @@ -5328,13 +4786,9 @@ static int rtw_p2p_connect(struct net_device *dev, u8 union_ch = rtw_mi_get_union_chan(padapter); u8 union_bw = rtw_mi_get_union_bw(padapter); u8 union_offset = rtw_mi_get_union_offset(padapter); - /* Have to enter the power saving with the AP */ + set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - #ifdef CONFIG_AP_MODE - /*mac-id sleep or wake-up for AP mode*/ - rtw_mi_buddy_ap_acdata_control(padapter, 1); - #endif - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); + rtw_leave_opch(padapter); } #endif /* CONFIG_CONCURRENT_MODE */ @@ -5361,7 +4815,7 @@ static int rtw_p2p_connect(struct net_device *dev, * driver will do scanning itself */ _enter_critical_bh(&pmlmepriv->lock, &irqL); - rtw_sitesurvey_cmd(padapter, NULL, 0, NULL, 0); + rtw_sitesurvey_cmd(padapter, NULL); _exit_critical_bh(&pmlmepriv->lock, &irqL); #endif /* CONFIG_INTEL_WIDI */ ret = -1; @@ -5523,13 +4977,10 @@ static int rtw_p2p_invite_req(struct net_device *dev, u8 union_ch = rtw_mi_get_union_chan(padapter); u8 union_bw = rtw_mi_get_union_bw(padapter); u8 union_offset = rtw_mi_get_union_offset(padapter); - /* Have to enter the power saving with the AP */ + set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - #ifdef CONFIG_AP_MODE - /*mac-id sleep or wake-up for AP mode*/ - rtw_mi_buddy_ap_acdata_control(padapter, 1); - #endif/*CONFIG_AP_MODE*/ - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); + rtw_leave_opch(padapter); + } else set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); #else @@ -5604,23 +5055,6 @@ static int rtw_p2p_set_persistent(struct net_device *dev, } -static int hexstr2bin(const char *hex, u8 *buf, size_t len) -{ - size_t i; - int a; - const char *ipos = hex; - u8 *opos = buf; - - for (i = 0; i < len; i++) { - a = hex2byte_i(ipos); - if (a < 0) - return -1; - *opos++ = a; - ipos += 2; - } - return 0; -} - static int uuid_str2bin(const char *str, u8 *bin) { const char *pos; @@ -6089,13 +5523,9 @@ static int rtw_p2p_prov_disc(struct net_device *dev, u8 union_bw = rtw_mi_get_union_bw(padapter); u8 union_offset = rtw_mi_get_union_offset(padapter); - /* Have to enter the power saving with the AP */ set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - #ifdef CONFIG_AP_MODE - /*mac-id sleep or wake-up for AP mode*/ - rtw_mi_buddy_ap_acdata_control(padapter, 1); - #endif/*CONFIG_AP_MODE*/ - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); + rtw_leave_opch(padapter); + } else set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); #else @@ -6121,7 +5551,7 @@ static int rtw_p2p_prov_disc(struct net_device *dev, rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); rtw_free_network_queue(padapter, _TRUE); _enter_critical_bh(&pmlmepriv->lock, &irqL); - rtw_sitesurvey_cmd(padapter, NULL, 0, NULL, 0); + rtw_sitesurvey_cmd(padapter, NULL); _exit_critical_bh(&pmlmepriv->lock, &irqL); #endif /* CONFIG_INTEL_WIDI */ } @@ -6372,27 +5802,19 @@ static int rtw_cta_test_start(struct net_device *dev, { int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + RTW_INFO("%s %s\n", __func__, extra); if (!strcmp(extra, "1")) - padapter->in_cta_test = 1; + hal_data->in_cta_test = 1; else - padapter->in_cta_test = 0; + hal_data->in_cta_test = 0; + + rtw_hal_rcr_set_chk_bssid(padapter, MLME_ACTION_NONE); - if (padapter->in_cta_test) { - u32 v = rtw_read32(padapter, REG_RCR); - v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); /* | RCR_ADF */ - rtw_write32(padapter, REG_RCR, v); - RTW_INFO("enable RCR_ADF\n"); - } else { - u32 v = rtw_read32(padapter, REG_RCR); - v |= RCR_CBSSID_DATA | RCR_CBSSID_BCN ;/* | RCR_ADF */ - rtw_write32(padapter, REG_RCR, v); - RTW_INFO("disable RCR_ADF\n"); - } return ret; } - extern int rtw_change_ifname(_adapter *padapter, const char *ifname); static int rtw_rereg_nd_name(struct net_device *dev, struct iw_request_info *info, @@ -6435,8 +5857,6 @@ static int rtw_rereg_nd_name(struct net_device *dev, goto exit; if (_rtw_memcmp(rereg_priv->old_ifname, "disable%d", 9) == _TRUE) { - padapter->ledpriv.bRegUseLed = rereg_priv->old_bRegUseLed; - rtw_hal_sw_led_init(padapter); /* rtw_ips_mode_req(&padapter->pwrctrlpriv, rereg_priv->old_ips_mode); */ } @@ -6449,12 +5869,6 @@ static int rtw_rereg_nd_name(struct net_device *dev, /* free network queue for Android's timming issue */ rtw_free_network_queue(padapter, _TRUE); - /* close led */ - rtw_led_control(padapter, LED_CTL_POWER_OFF); - rereg_priv->old_bRegUseLed = padapter->ledpriv.bRegUseLed; - padapter->ledpriv.bRegUseLed = _FALSE; - rtw_hal_sw_led_deinit(padapter); - /* the interface is being "disabled", we can do deeper IPS */ /* rereg_priv->old_ips_mode = rtw_get_ips_mode_req(&padapter->pwrctrlpriv); */ /* rtw_ips_mode_req(&padapter->pwrctrlpriv, IPS_NORMAL); */ @@ -6467,7 +5881,9 @@ static int rtw_rereg_nd_name(struct net_device *dev, #ifdef CONFIG_IOL #include #endif - +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR +#include "../../hal/hal_dm_acs.h" +#endif #ifdef DBG_CMD_QUEUE u8 dump_cmd_id = 0; #endif @@ -6784,13 +6200,15 @@ static int rtw_dbg_port(struct net_device *dev, psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); if (psta) { RTW_INFO("SSID=%s\n", cur_network->network.Ssid.Ssid); - RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); RTW_INFO("cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); - RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); + RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", + psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id); #ifdef CONFIG_80211N_HT RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); - RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n" + , psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); #endif /* CONFIG_80211N_HT */ @@ -6833,7 +6251,8 @@ static int rtw_dbg_port(struct net_device *dev, _list *plist, *phead; #ifdef CONFIG_AP_MODE - RTW_INFO("sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap); + RTW_INFO_DUMP("sta_dz_bitmap:", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); + RTW_INFO_DUMP("tim_bitmap:", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); #endif _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); @@ -6846,13 +6265,15 @@ static int rtw_dbg_port(struct net_device *dev, plist = get_next(plist); - if (extra_arg == psta->aid) { - RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + if (extra_arg == psta->cmn.aid) { + RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); - RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); + RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", + psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id); #ifdef CONFIG_80211N_HT RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); - RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, + RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", + psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); @@ -7092,17 +6513,9 @@ static int rtw_dbg_port(struct net_device *dev, break; #ifdef CONFIG_BACKGROUND_NOISE_MONITOR case 0x1e: { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - u8 chan = rtw_get_oper_ch(padapter); RTW_INFO("===========================================\n"); - odm_inband_noise_monitor(pDM_Odm, _TRUE, 0x1e, 100); - RTW_INFO("channel(%d),noise_a = %d, noise_b = %d , noise_all:%d\n", - chan, pDM_Odm->noise_level.noise[ODM_RF_PATH_A], - pDM_Odm->noise_level.noise[ODM_RF_PATH_B], - pDM_Odm->noise_level.noise_all); + rtw_noise_measure_curchan(padapter); RTW_INFO("===========================================\n"); - } break; #endif @@ -7455,7 +6868,9 @@ static int wpa_mlme(struct net_device *dev, u32 command, u32 reason) ret = -EOPNOTSUPP; break; } - +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_do_disconnect(padapter); +#endif return ret; } @@ -7657,72 +7072,61 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) /* */ { /* group key */ if (param->u.crypt.set_tx == 1) { if (strcmp(param->u.crypt.alg, "WEP") == 0) { - RTW_INFO("%s, set group_key, WEP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set WEP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - psecuritypriv->dot118021XGrpPrivacy = _WEP40_; if (param->u.crypt.key_len == 13) psecuritypriv->dot118021XGrpPrivacy = _WEP104_; } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - RTW_INFO("%s, set group_key, TKIP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set TKIP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); psecuritypriv->dot118021XGrpPrivacy = _TKIP_; - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ /* set mic key */ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); - psecuritypriv->busetkipkey = _TRUE; } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - RTW_INFO("%s, set group_key, CCMP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set CCMP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); psecuritypriv->dot118021XGrpPrivacy = _AES_; - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - } -#ifdef CONFIG_IEEE80211W - else if (strcmp(param->u.crypt.alg, "BIP") == 0) { - int no; - RTW_INFO("BIP key_len=%d , index=%d\n", param->u.crypt.key_len, param->u.crypt.idx); - /* save the IGTK key, length 16 bytes */ + #ifdef CONFIG_IEEE80211W + } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set TX IGTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - /* RTW_INFO("IGTK key below:\n"); - for(no=0;no<16;no++) - printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); - RTW_INFO("\n"); */ - padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; - padapter->securitypriv.binstallBIPkey = _TRUE; - RTW_INFO(" ~~~~set sta key:IGKT\n"); + psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx; + psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq); + psecuritypriv->binstallBIPkey = _TRUE; goto exit; - } -#endif /* CONFIG_IEEE80211W */ - else { - RTW_INFO("%s, set group_key, none\n", __FUNCTION__); + #endif /* CONFIG_IEEE80211W */ + } else if (strcmp(param->u.crypt.alg, "none") == 0) { + RTW_INFO(FUNC_ADPT_FMT" clear group key, idx:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx); psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + } else { + RTW_WARN(FUNC_ADPT_FMT" set group key, not support\n" + , FUNC_ADPT_ARG(padapter)); + goto exit; } psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; - - psecuritypriv->binstallGrpkey = _TRUE; - - psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ - - rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); if (pbcmc_sta) { + pbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); pbcmc_sta->ieee8021x_blocked = _FALSE; pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy */ } + psecuritypriv->binstallGrpkey = _TRUE; + psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ + rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); } goto exit; @@ -7735,80 +7139,51 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); if (strcmp(param->u.crypt.alg, "WEP") == 0) { - RTW_INFO("%s, set pairwise key, WEP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); psta->dot118021XPrivacy = _WEP40_; if (param->u.crypt.key_len == 13) psta->dot118021XPrivacy = _WEP104_; - } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - RTW_INFO("%s, set pairwise key, TKIP\n", __FUNCTION__); + } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); psta->dot118021XPrivacy = _TKIP_; - - /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ /* set mic key */ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); - psecuritypriv->busetkipkey = _TRUE; } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - - RTW_INFO("%s, set pairwise key, CCMP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); psta->dot118021XPrivacy = _AES_; - } else { - RTW_INFO("%s, set pairwise key, none\n", __FUNCTION__); + } else if (strcmp(param->u.crypt.alg, "none") == 0) { + RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx); psta->dot118021XPrivacy = _NO_PRIVACY_; - } - rtw_ap_set_pairwise_key(padapter, psta); + } else { + RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + goto exit; + } + psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); + psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq); psta->ieee8021x_blocked = _FALSE; - psta->bpairwise_key_installed = _TRUE; + rtw_ap_set_pairwise_key(padapter, psta); - } else { /* group key??? */ - if (strcmp(param->u.crypt.alg, "WEP") == 0) { - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - psecuritypriv->dot118021XGrpPrivacy = _WEP40_; - if (param->u.crypt.key_len == 13) - psecuritypriv->dot118021XGrpPrivacy = _WEP104_; - } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - psecuritypriv->dot118021XGrpPrivacy = _TKIP_; - - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ - /* set mic key */ - _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); - _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); - - psecuritypriv->busetkipkey = _TRUE; - - } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - psecuritypriv->dot118021XGrpPrivacy = _AES_; - - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - } else - psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; - - psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; - - psecuritypriv->binstallGrpkey = _TRUE; - - psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ - - rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); - - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); - if (pbcmc_sta) { - pbcmc_sta->ieee8021x_blocked = _FALSE; - pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy */ - } - + } else { + RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + goto exit; } } @@ -7866,9 +7241,9 @@ static int rtw_hostapd_sta_flush(struct net_device *dev) RTW_INFO("%s\n", __FUNCTION__); flush_all_cam_entry(padapter); /* clear CAM */ - +#ifdef CONFIG_AP_MODE ret = rtw_sta_flush(padapter, _TRUE); - +#endif return ret; } @@ -7910,7 +7285,7 @@ static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) /* RTW_INFO("rtw_add_sta(), init sta's variables, psta=%p\n", psta); */ - psta->aid = param->u.add_sta.aid;/* aid=1~2007 */ + psta->cmn.aid = param->u.add_sta.aid;/* aid=1~2007 */ _rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16); @@ -7972,7 +7347,7 @@ static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) if (psta) { u8 updated = _FALSE; - /* RTW_INFO("free psta=%p, aid=%d\n", psta, psta->aid); */ + /* RTW_INFO("free psta=%p, aid=%d\n", psta, psta->cmn.aid); */ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { @@ -8037,7 +7412,7 @@ static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *par u64 tx_drops; } get_sta; #endif - psta_data->aid = (u16)psta->aid; + psta_data->aid = (u16)psta->cmn.aid; psta_data->capability = psta->capability; psta_data->flags = psta->flags; @@ -8304,7 +7679,7 @@ static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *p param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) return -EINVAL; - ret = rtw_acl_remove_sta(padapter, param->sta_addr); + ret = rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr); return ret; @@ -8324,7 +7699,7 @@ static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *para param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) return -EINVAL; - ret = rtw_acl_add_sta(padapter, param->sta_addr); + ret = rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr); return ret; @@ -8339,7 +7714,7 @@ static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param * if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) return -EINVAL; - rtw_set_macaddr_acl(padapter, param->u.mlme.command); + rtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, param->u.mlme.command); return ret; } @@ -8661,7 +8036,7 @@ static int rtw_wowlan_ctrl(struct net_device *dev, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct sta_info *psta = NULL; int ret = 0; - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); poidparam.subcode = 0; RTW_INFO("+rtw_wowlan_ctrl: %s\n", extra); @@ -8732,7 +8107,7 @@ static int rtw_wowlan_set_pattern(struct net_device *dev, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wowlan_ioctl_param poidparam; int ret = 0, len = 0, i = 0; - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); u8 input[wrqu->data.length]; u8 index = 0; @@ -8803,7 +8178,7 @@ static int rtw_ap_wowlan_ctrl(struct net_device *dev, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct sta_info *psta = NULL; int ret = 0; - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); poidparam.subcode = 0; RTW_INFO("+rtw_ap_wowlan_ctrl: %s\n", extra); @@ -9102,6 +8477,9 @@ static int rtw_mp_efuse_get(struct net_device *dev, err = -EFAULT; goto exit; } + + *(extra + wrqu->length) = '\0'; + #ifdef CONFIG_LPS lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */ rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); @@ -9732,6 +9110,8 @@ static int rtw_mp_efuse_get(struct net_device *dev, return err; } + +#ifdef CONFIG_MP_INCLUDED static int rtw_mp_efuse_set(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wdata, char *extra) @@ -9769,6 +9149,8 @@ static int rtw_mp_efuse_set(struct net_device *dev, if (copy_from_user(extra, wrqu->pointer, wrqu->length)) return -EFAULT; + *(extra + wrqu->length) = '\0'; + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&wifimaplen, _FALSE); setdata = rtw_zmalloc(1024); @@ -10139,21 +9521,6 @@ static int rtw_mp_efuse_set(struct net_device *dev, for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); -#ifdef CONFIG_RTL8703B - if (cnts == 1 && addr == 0x189) { - setdata[1] = setdata[0]; - setdata[0] = 0x00; - cnts += 1; - addr = 0x188; - RTW_INFO("addr 0x%x ,setdata=0x%X 0x%X\n", addr, setdata[0], setdata[1]); - } else if (cnts == 1 && addr == 0x161) { - setdata[1] = setdata[0]; - setdata[0] = 0xFE; - cnts += 1; - addr = 0x160; - RTW_INFO("addr 0x%x ,setdata=0x%X 0x%X\n", addr, setdata[0], setdata[1]); - } -#endif #ifndef RTW_HALMAC EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE); if ((addr + cnts) > max_available_len) { @@ -10294,7 +9661,8 @@ static int rtw_mp_efuse_set(struct net_device *dev, if (padapter->registrypriv.bFileMaskEfuse != _TRUE && pmp_priv->bloadefusemap == _TRUE) { RTW_INFO("%s: File eFuse mask file not to be loaded\n", __FUNCTION__); - sprintf(extra, "Not load eFuse mask file yet, Please use the efuse_mask CMD.\n"); + sprintf(extra, "Not load eFuse mask file yet, Please use the efuse_mask CMD, now remove the interface !!!!\n"); + rtw_set_surprise_removed(padapter); err = 0; goto exit; } @@ -10443,8 +9811,6 @@ static int rtw_mp_efuse_set(struct net_device *dev, return err; } -#ifdef CONFIG_MP_INCLUDED - #ifdef CONFIG_RTW_CUSTOMER_STR static int rtw_mp_customer_str( struct net_device *dev, @@ -10632,6 +9998,10 @@ static int rtw_priv_mp_get(struct net_device *dev, RTW_INFO("set case mp_channel\n"); rtw_mp_channel(dev , info, wrqu, extra); break; + case MP_CHL_OFFSET: + RTW_INFO("set case mp_ch_offset\n"); + rtw_mp_ch_offset(dev , info, wrqu, extra); + break; case READ_REG: RTW_INFO("mp_get READ_REG\n"); rtw_mp_read_reg(dev, info, wrqu, extra); @@ -10691,10 +10061,12 @@ static int rtw_priv_mp_get(struct net_device *dev, RTW_INFO("set case MP_PWRTRK\n"); rtw_mp_pwrtrk(dev, info, wrqu, extra); break; +#ifdef CONFIG_MP_INCLUDED case EFUSE_SET: RTW_INFO("set case efuse set\n"); rtw_mp_efuse_set(dev, info, wdata, extra); break; +#endif case EFUSE_GET: RTW_INFO("efuse get EFUSE_GET\n"); rtw_mp_efuse_get(dev, info, wdata, extra); @@ -10745,6 +10117,14 @@ static int rtw_priv_mp_get(struct net_device *dev, RTW_INFO("mp_get MP_SETPWRBYRATE\n"); rtw_mp_pwrbyrate(dev, info, wdata, extra); break; + case BT_EFUSE_FILE: + RTW_INFO("mp_get BT EFUSE_FILE\n"); + rtw_bt_efuse_file_map(dev, info, wdata, extra); + break; + case MP_SWRFPath: + RTW_INFO("mp_get MP_SWRFPath\n"); + rtw_mp_switch_rf_path(dev, info, wrqu, extra); + break; default: return -EIO; } @@ -10983,7 +10363,7 @@ static int rtw_priv_get(struct net_device *dev, if (subcmd < MP_NULL) { #ifdef CONFIG_MP_INCLUDED rtw_priv_mp_get(dev, info, wdata, extra); -#endif +#endif return 0; } @@ -11073,57 +10453,14 @@ static int rtw_tdls_enable(struct net_device *dev, int ret = 0; #ifdef CONFIG_TDLS - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - _irqL irqL; - _list *plist, *phead; - s32 index; - struct sta_info *psta = NULL; - struct sta_priv *pstapriv = &padapter->stapriv; - u8 tdls_sta[NUM_STA][ETH_ALEN]; - u8 empty_hwaddr[ETH_ALEN] = { 0x00 }; - struct tdls_txmgmt txmgmt; RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1); - _rtw_memset(tdls_sta, 0x00, sizeof(tdls_sta)); - _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - - if (extra[0] == '0') { - ptdlsinfo->tdls_enable = 0; - - if (pstapriv->asoc_sta_count == 1) - return ret; - - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); - for (index = 0; index < NUM_STA; index++) { - phead = &(pstapriv->sta_hash[index]); - plist = get_next(phead); - - while (rtw_end_of_queue_search(phead, plist) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info , hash_list); - - plist = get_next(plist); - - if (psta->tdls_sta_state != TDLS_STATE_NONE) - _rtw_memcpy(tdls_sta[index], psta->hwaddr, ETH_ALEN); - } - } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); - - for (index = 0; index < NUM_STA; index++) { - if (!_rtw_memcmp(tdls_sta[index], empty_hwaddr, ETH_ALEN)) { - RTW_INFO("issue tear down to "MAC_FMT"\n", MAC_ARG(tdls_sta[index])); - txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; - _rtw_memcpy(txmgmt.peer, tdls_sta[index], ETH_ALEN); - issue_tdls_teardown(padapter, &txmgmt, _TRUE); - } - } - rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR); - rtw_reset_tdls_info(padapter); - } else if (extra[0] == '1') - ptdlsinfo->tdls_enable = 1; + if (extra[0] == '0') + rtw_disable_tdls_func(padapter, _TRUE); + else if (extra[0] == '1') + rtw_enable_tdls_func(padapter); #endif /* CONFIG_TDLS */ return ret; @@ -11283,11 +10620,11 @@ static int rtw_tdls_ch_switch(struct net_device *dev, bw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20; central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset); if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) >= 0) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START); else - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_PREPARE); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE); } else - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START); /* issue_tdls_ch_switch_req(padapter, ptdls_sta); */ /* RTW_INFO("issue tdls ch switch req\n"); */ @@ -11331,7 +10668,7 @@ static int rtw_tdls_ch_switch_off(struct net_device *dev, if (ptdls_sta == NULL) return ret; - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL); pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE | TDLS_CH_SWITCH_ON_STATE | @@ -11455,7 +10792,7 @@ static int rtw_tdls_pson(struct net_device *dev, ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); - issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 1, 3, 500); + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 3, 500); #endif /* CONFIG_TDLS */ @@ -11482,7 +10819,7 @@ static int rtw_tdls_psoff(struct net_device *dev, ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); if (ptdls_sta) - issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 0, 3, 500); + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 3, 500); #endif /* CONFIG_TDLS */ @@ -11655,7 +10992,7 @@ static int rtw_wfd_tdls_status(struct net_device *dev, , ptdlsinfo->link_established, ptdlsinfo->sta_cnt, ptdlsinfo->sta_maximum, ptdlsinfo->cur_channel, - ptdlsinfo->tdls_enable + rtw_is_tdls_enabled(padapter) #ifdef CONFIG_TDLS_CH_SW , ptdlsinfo->chsw_info.ch_sw_state, @@ -11804,8 +11141,8 @@ static int rtw_tdls(struct net_device *dev, return 0; } - if (padapter->tdlsinfo.tdls_enable == 0) { - RTW_INFO("tdls haven't enabled\n"); + if (rtw_is_tdls_enabled(padapter) == _FALSE) { + RTW_INFO("TDLS is not enabled\n"); return 0; } @@ -12030,7 +11367,7 @@ static s32 initpseudoadhoc(PADAPTER padapter) if (err == _FALSE) return _FAIL; - err = rtw_setopmode_cmd(padapter, networkType, _TRUE); + err = rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK); if (err == _FAIL) return _FAIL; @@ -12097,7 +11434,7 @@ static s32 createpseudoadhoc(PADAPTER padapter) /* 3 join psudo AdHoc */ pcur_network->join_res = 1; - pcur_network->aid = psta->aid = 1; + pcur_network->aid = psta->cmn.aid = 1; _rtw_memcpy(&pcur_network->network, pdev_network, get_WLAN_BSSID_EX_sz(pdev_network)); /* set msr to WIFI_FW_ADHOC_STATE */ @@ -12175,14 +11512,12 @@ static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size) pattrib->qos_en = _FALSE; bmcast = IS_MCAST(pattrib->ra); - if (bmcast) { - pattrib->mac_id = 1; + if (bmcast) pattrib->psta = rtw_get_bcmc_stainfo(padapter); - } else { - pattrib->mac_id = 0; + else pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); - } + pattrib->mac_id = pattrib->psta->cmn.mac_id; pattrib->pktlen = size; pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen; @@ -12315,7 +11650,7 @@ static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) rxpktsize = prxreport->pktlen; phal = GET_HAL_DATA(padapter); - if (phal->ReceiveConfig & RCR_APPFCS) + if (rtw_hal_rcr_check(padapter, RCR_APPFCS)) fcssize = IEEE80211_FCS_LEN; else fcssize = 0; @@ -12521,17 +11856,20 @@ static int rtw_test( RTW_INFO("+%s\n", __func__); len = wrqu->data.length; - pbuf = (u8 *)rtw_zmalloc(len); + pbuf = (u8 *)rtw_zmalloc(len + 1); if (pbuf == NULL) { RTW_INFO("%s: no memory!\n", __func__); return -ENOMEM; } if (copy_from_user(pbuf, wrqu->data.pointer, len)) { - rtw_mfree(pbuf, len); + rtw_mfree(pbuf, len + 1); RTW_INFO("%s: copy from user fail!\n", __func__); return -EFAULT; } + + pbuf[len] = '\0'; + RTW_INFO("%s: string=\"%s\"\n", __func__, pbuf); ptmp = (char *)pbuf; @@ -12779,13 +12117,18 @@ static const struct iw_priv_args rtw_private_args[] = { SIOCIWFIRSTPRIV + 0x16, IW_PRIV_TYPE_CHAR | 64, 0, "pm_set" }, - +#ifdef CONFIG_RTW_80211K + { + SIOCIWFIRSTPRIV + 0x17, + IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | 1024 , "rrm" + }, +#endif {SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | IFNAMSIZ , 0 , "rereg_nd_name"}, #ifdef CONFIG_MP_INCLUDED {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0, "NULL"}, {SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "NULL"}, #else - {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0, "efuse_set"}, + {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0, "NULL"}, {SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get"}, #endif { @@ -12837,6 +12180,7 @@ static const struct iw_priv_args rtw_mp_private_args[] = { { MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" }, { MP_STOP , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_stop" }, { MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" }, + { MP_CHL_OFFSET , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ch_offset" }, { MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_bandwidth"}, { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, { MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_reset_stats"}, @@ -12874,6 +12218,8 @@ static const struct iw_priv_args rtw_mp_private_args[] = { { CTA_TEST, IW_PRIV_TYPE_CHAR | 1024, 0, "cta_test"}, { MP_IQK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_iqk"}, { MP_LCK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_lck"}, + { BT_EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "bt_efuse_file" }, + { MP_SWRFPath, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_swrfpath" }, #ifdef CONFIG_RTW_CUSTOMER_STR { MP_CUSTOMER_STR, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "customer_str" }, #endif @@ -12884,7 +12230,7 @@ static const struct iw_priv_args rtw_mp_private_args[] = { static iw_handler rtw_private_handler[] = { rtw_wx_write32, /* 0x00 */ rtw_wx_read32, /* 0x01 */ - rtw_drvext_hdl, /* 0x02 */ + NULL, /* 0x02 */ #ifdef MP_IOCTL_HDL rtw_mp_ioctl_hdl, /* 0x03 */ #else @@ -12921,14 +12267,18 @@ static iw_handler rtw_private_handler[] = { rtw_tdls_get, /* 0x15 */ rtw_pm_set, /* 0x16 */ +#ifdef CONFIG_RTW_80211K + rtw_wx_priv_rrm, /* 0x17 */ +#else rtw_wx_priv_null, /* 0x17 */ +#endif rtw_rereg_nd_name, /* 0x18 */ rtw_wx_priv_null, /* 0x19 */ #ifdef CONFIG_MP_INCLUDED rtw_wx_priv_null, /* 0x1A */ rtw_wx_priv_null, /* 0x1B */ #else - rtw_mp_efuse_set, /* 0x1A */ + rtw_wx_priv_null, /* 0x1A */ rtw_mp_efuse_get, /* 0x1B */ #endif NULL, /* 0x1C is reserved for hostapd */ @@ -12965,14 +12315,20 @@ static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev) HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); - tmp_level = (u8)odm_signal_scale_mapping(&pHal->odmpriv, padapter->recvpriv.signal_strength); + tmp_level = (u8)phydm_signal_scale_mapping(&pHal->odmpriv, padapter->recvpriv.signal_strength); } #endif #endif tmp_qual = padapter->recvpriv.signal_qual; - rtw_get_noise(padapter); - tmp_noise = padapter->recvpriv.noise; + #ifdef CONFIG_BACKGROUND_NOISE_MONITOR + if (IS_NM_ENABLE(padapter)) { + tmp_noise = rtw_noise_measure_curchan(padapter); + #ifndef CONFIG_SIGNAL_DISPLAY_DBM + tmp_noise = translate_dbm_to_percentage(tmp_noise);/*percentage*/ + #endif + } + #endif /* RTW_INFO("level:%d, qual:%d, noise:%d, rssi (%d)\n", tmp_level, tmp_qual, tmp_noise,padapter->recvpriv.rssi); */ piwstats->qual.level = tmp_level; @@ -13172,6 +12528,11 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq goto exit; } + if (k >= num_priv_args) { + err = -EINVAL; + goto exit; + } + /* If we have to set some data */ if ((priv_args[k].set_args & IW_PRIV_TYPE_MASK) && (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) { diff --git a/os_dep/linux/ioctl_mp.c b/os_dep/linux/ioctl_mp.c index f2a9418..e82c39f 100644 --- a/os_dep/linux/ioctl_mp.c +++ b/os_dep/linux/ioctl_mp.c @@ -43,11 +43,15 @@ int rtw_mp_write_reg(struct net_device *dev, u32 addr, data; int ret; PADAPTER padapter = rtw_netdev_priv(dev); - char input[wrqu->length]; + char input[wrqu->length + 1]; + + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; + _rtw_memset(extra, 0, wrqu->length); pch = input; @@ -482,6 +486,33 @@ int rtw_mp_channel(struct net_device *dev, } +int rtw_mp_ch_offset(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 input[wrqu->length + 1]; + u32 ch_offset = 0; + + _rtw_memset(input, 0, sizeof(input)); + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + input[wrqu->length] = '\0'; + ch_offset = rtw_atoi(input); + /*RTW_INFO("%s: channel=%d\n", __func__, channel);*/ + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "Change prime channel offset %d to %d", padapter->mppriv.prime_channel_offset , ch_offset); + padapter->mppriv.prime_channel_offset = ch_offset; + SetChannel(padapter); + + wrqu->length = strlen(extra); + return 0; +} + + int rtw_mp_bandwidth(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) @@ -510,8 +541,7 @@ int rtw_mp_bandwidth(struct net_device *dev, SetBandwidth(padapter); pHalData->current_channel_bw = bandwidth; - /*cur_ch_offset = rtw_get_offset_by_ch(padapter->mppriv.channel);*/ - /*set_channel_bwmode(padapter, padapter->mppriv.channel, cur_ch_offset, bandwidth);*/ + wrqu->length = strlen(extra); return 0; @@ -523,16 +553,20 @@ int rtw_mp_txpower_index(struct net_device *dev, struct iw_point *wrqu, char *extra) { PADAPTER padapter = rtw_netdev_priv(dev); - char input[wrqu->length]; + char input[wrqu->length + 1]; u32 rfpath; u32 txpower_inx; if (wrqu->length > 128) return -EFAULT; + _rtw_memset(input, 0, sizeof(input)); + if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; + rfpath = rtw_atoi(input); txpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath); sprintf(extra, " %d", txpower_inx); @@ -567,10 +601,10 @@ int rtw_mp_txpower(struct net_device *dev, sprintf(extra, "Set power level path_A:%d path_B:%d path_C:%d path_D:%d", idx_a , idx_b , idx_c , idx_d); padapter->mppriv.txpoweridx = (u8)idx_a; - pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)idx_a; - pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)idx_b; - pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)idx_c; - pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)idx_d; + pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)idx_a; + pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)idx_b; + pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)idx_c; + pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)idx_d; padapter->mppriv.bSetTxPower = 1; SetTxPower(padapter); @@ -814,12 +848,16 @@ int rtw_mp_disable_bt_coexist(struct net_device *dev, HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct hal_ops *pHalFunc = &padapter->hal_func; - u8 input[wrqu->data.length]; + u8 input[wrqu->data.length + 1]; u32 bt_coexist; + _rtw_memset(input, 0, sizeof(input)); + if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; + input[wrqu->data.length] = '\0'; + bt_coexist = rtw_atoi(input); if (bt_coexist == 0) { @@ -1234,6 +1272,7 @@ int rtw_mp_SetRFPath(struct net_device *dev, PADAPTER padapter = rtw_netdev_priv(dev); char input[wrqu->length]; int bMain = 1, bTurnoff = 1; + u8 ret = _TRUE; RTW_INFO("%s:iwpriv in=%s\n", __func__, input); @@ -1244,6 +1283,14 @@ int rtw_mp_SetRFPath(struct net_device *dev, bTurnoff = strncmp(input, "0", 3); /* strncmp TRUE is 0*/ _rtw_memset(extra, 0, wrqu->length); +#ifdef CONFIG_ANTENNA_DIVERSITY + if (bMain == 0) + ret = rtw_mp_set_antdiv(padapter, _TRUE); + else + ret = rtw_mp_set_antdiv(padapter, _FALSE); + if (ret == _FALSE) + RTW_INFO("%s:ANTENNA_DIVERSITY FAIL\n", __func__); +#endif if (bMain == 0) { MP_PHY_SetRFPathSwitch(padapter, _TRUE); @@ -1266,6 +1313,56 @@ int rtw_mp_SetRFPath(struct net_device *dev, } +int rtw_mp_switch_rf_path(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv; + char input[wrqu->length]; + int bwlg = 1, bwla = 1, btg = 1, bbt=1; + u8 ret = 0; + + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + pmp_priv = &padapter->mppriv; + + RTW_INFO("%s: in=%s\n", __func__, input); + + bwlg = strncmp(input, "WLG", 3); /* strncmp TRUE is 0*/ + bwla = strncmp(input, "WLA", 3); /* strncmp TRUE is 0*/ + btg = strncmp(input, "BTG", 3); /* strncmp TRUE is 0*/ + bbt = strncmp(input, "BT", 3); /* strncmp TRUE is 0*/ + + _rtw_memset(extra, 0, wrqu->length); +#ifdef CONFIG_RTL8821C /* only support for 8821c wlg/wla/btg/bt RF switch path */ + if (bwlg == 0) { + pmp_priv->rf_path_cfg = SWITCH_TO_WLG; + sprintf(extra, "switch rf path WLG\n"); + } else if (bwla == 0) { + pmp_priv->rf_path_cfg = SWITCH_TO_WLA; + sprintf(extra, "switch rf path WLA\n"); + } else if (btg == 0) { + pmp_priv->rf_path_cfg = SWITCH_TO_BTG; + sprintf(extra, "switch rf path BTG\n"); + } else if (bbt == 0) { + pmp_priv->rf_path_cfg = SWITCH_TO_BT; + sprintf(extra, "switch rf path BG\n"); + } else { + sprintf(extra, "Error set %s\n", __func__); + return -EFAULT; + } + + mp_phy_switch_rf_path_set(padapter, &pmp_priv->rf_path_cfg); +#endif + + wrqu->length = strlen(extra); + + return ret; + +} int rtw_mp_QueryDrv(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) @@ -1716,10 +1813,10 @@ int rtw_mp_tx(struct net_device *dev, pextra += sprintf(pextra, "\nSet power level :%d", txpower); padapter->mppriv.txpoweridx = (u8)txpower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)txpower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)txpower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)txpower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)txpower; + pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)txpower; + pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)txpower; + pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)txpower; + pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)txpower; SetTxPower(padapter); RTW_INFO("%s: bw=%d sg=%d\n", __func__, bandwidth, sg); @@ -1957,10 +2054,16 @@ int rtw_mp_hwtx(struct net_device *dev, _rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(RT_PMAC_TX_INFO)); _rtw_memcpy((void *)&pMptCtx->PMacTxInfo, (void *)input, sizeof(RT_PMAC_TX_INFO)); + _rtw_memset(wrqu->data.pointer, 0, wrqu->data.length); - mpt_ProSetPMacTx(padapter); - sprintf(extra, "Set PMac Tx Mode start\n"); - + if (pMptCtx->PMacTxInfo.bEnPMacTx == 1 && pmp_priv->mode != MP_ON) { + sprintf(extra, "MP Tx Running, Please Set PMac Tx Mode Stop\n"); + RTW_INFO("Error !!! MP Tx Running, Please Set PMac Tx Mode Stop\n"); + } else { + RTW_INFO("To set MAC Tx mode\n"); + mpt_ProSetPMacTx(padapter); + sprintf(extra, "Set PMac Tx Mode OK\n"); + } wrqu->data.length = strlen(extra); #endif return 0; @@ -1977,6 +2080,8 @@ int rtw_mp_pwrlmt(struct net_device *dev, if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; + + *(extra + wrqu->data.length) = '\0'; #ifdef CONFIG_TXPWR_LIMIT pwrlimtstat = registry_par->RegEnableTxPowerLimit; if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { @@ -2005,6 +2110,7 @@ int rtw_mp_pwrbyrate(struct net_device *dev, if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; + *(extra + wrqu->data.length) = '\0'; if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { padapter->registrypriv.RegEnableTxPowerByRate = 0; sprintf(extra, "Turn off Tx Power by Rate\n"); @@ -2092,9 +2198,14 @@ int rtw_efuse_mask_file(struct net_device *dev, if (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) { RTW_INFO("%s do rtw_efuse_mask_file_read = %s! ,sizeof maskfileBuffer %zu\n", __func__, rtw_efuse_mask_file_path, sizeof(maskfileBuffer)); Status = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, maskfileBuffer, sizeof(maskfileBuffer)); - if (Status == _TRUE) + if (Status == _TRUE) { padapter->registrypriv.bFileMaskEfuse = _TRUE; - sprintf(extra, "efuse mask file read OK\n"); + sprintf(extra, "efuse mask file read OK\n"); + } else { + padapter->registrypriv.bFileMaskEfuse = _FALSE; + sprintf(extra, "read efuse mask file FAIL\n"); + RTW_INFO("%s rtw_efuse_file_read mask fail!\n", __func__); + } } else { padapter->registrypriv.bFileMaskEfuse = _FALSE; sprintf(extra, "efuse mask file readable FAIL\n"); @@ -2142,6 +2253,43 @@ int rtw_efuse_file_map(struct net_device *dev, return 0; } +int rtw_bt_efuse_file_map(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + char *rtw_efuse_file_map_path; + u8 Status; + PEFUSE_HAL pEfuseHal; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mp_priv *pmp_priv = &padapter->mppriv; + + pEfuseHal = &pHalData->EfuseHal; + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + rtw_efuse_file_map_path = extra; + + _rtw_memset(pEfuseHal->fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); + + if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) { + RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path); + Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeBTEfuseModifiedMap, sizeof(pEfuseHal->fakeBTEfuseModifiedMap)); + if (Status == _TRUE) { + pmp_priv->bloadBTefusemap = _TRUE; + sprintf(extra, "BT efuse file file_read OK\n"); + } else { + pmp_priv->bloadBTefusemap = _FALSE; + sprintf(extra, "BT efuse file file_read FAIL\n"); + } + } else { + sprintf(extra, "BT efuse file readable FAIL\n"); + RTW_INFO("%s rtw_is_file_readable fail!\n", __func__); + } + wrqu->data.length = strlen(extra); + return 0; +} + #if defined(CONFIG_RTL8723B) int rtw_mp_SetBT(struct net_device *dev, struct iw_request_info *info, @@ -2167,6 +2315,9 @@ int rtw_mp_SetBT(struct net_device *dev, if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; + + *(extra + wrqu->data.length) = '\0'; + if (strlen(extra) < 1) return -EFAULT; @@ -2183,7 +2334,7 @@ int rtw_mp_SetBT(struct net_device *dev, if (strncmp(extra, "dlbt", 4) == 0) { pHalData->LastHMEBoxNum = 0; - padapter->bBTFWReady = _FALSE; + pHalData->bBTFWReady = _FALSE; rtw_write8(padapter, 0xa3, 0x05); BTStatus = rtw_read8(padapter, 0xa0); RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus); @@ -2215,7 +2366,7 @@ int rtw_mp_SetBT(struct net_device *dev, pBTFirmware = (PRT_MP_FIRMWARE)rtw_zmalloc(sizeof(RT_MP_FIRMWARE)); if (pBTFirmware == NULL) goto exit; - padapter->bBTFWReady = _FALSE; + pHalData->bBTFWReady = _FALSE; FirmwareDownloadBT(padapter, pBTFirmware); if (pBTFirmware) rtw_mfree((u8 *)pBTFirmware, sizeof(RT_MP_FIRMWARE)); @@ -2244,7 +2395,7 @@ int rtw_mp_SetBT(struct net_device *dev, } if (strncmp(extra, "dlfw", 4) == 0) { pHalData->LastHMEBoxNum = 0; - padapter->bBTFWReady = _FALSE; + pHalData->bBTFWReady = _FALSE; rtw_write8(padapter, 0xa3, 0x05); BTStatus = rtw_read8(padapter, 0xa0); RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus); @@ -2352,7 +2503,7 @@ int rtw_mp_SetBT(struct net_device *dev, } if (strncmp(extra, "h2c", 3) == 0) { RTW_INFO("SetBT h2c !\n"); - padapter->bBTFWReady = _TRUE; + pHalData->bBTFWReady = _TRUE; rtw_hal_fill_h2c_cmd(padapter, 0x63, 1, u1H2CBtMpOperParm); goto exit; } @@ -2453,7 +2604,7 @@ int rtw_mp_SetBT(struct net_device *dev, todo: _rtw_memset(extra, '\0', wrqu->data.length); - if (padapter->bBTFWReady == _FALSE) { + if (pHalData->bBTFWReady == _FALSE) { sprintf(extra, "BTFWReady = FALSE.\n"); goto exit; } diff --git a/os_dep/linux/mlme_linux.c b/os_dep/linux/mlme_linux.c index 4da606e..418fd69 100644 --- a/os_dep/linux/mlme_linux.c +++ b/os_dep/linux/mlme_linux.c @@ -67,7 +67,7 @@ void rtw_os_indicate_connect(_adapter *adapter) #endif /* CONFIG_IOCTL_CFG80211 */ rtw_indicate_wx_assoc_event(adapter); - netif_carrier_on(adapter->pnetdev); + rtw_netif_carrier_on(adapter->pnetdev); if (adapter->pid[2] != 0) rtw_signal_process(adapter->pid[2], SIGALRM); @@ -113,10 +113,6 @@ void rtw_reset_securitypriv(_adapter *adapter) backupPMKIDIndex = adapter->securitypriv.PMKIDIndex; backupTKIPCountermeasure = adapter->securitypriv.btkip_countermeasure; backupTKIPcountermeasure_time = adapter->securitypriv.btkip_countermeasure_time; -#ifdef CONFIG_IEEE80211W - /* reset RX BIP packet number */ - pmlmeext->mgnt_80211w_IPN_rx = 0; -#endif /* CONFIG_IEEE80211W */ _rtw_memset((unsigned char *)&adapter->securitypriv, 0, sizeof(struct security_priv)); /* Added by Albert 2009/02/18 */ @@ -156,7 +152,7 @@ void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_gener /* RT_PMKID_LIST backupPMKIDList[NUM_PMKID_CACHE]; */ - netif_carrier_off(adapter->pnetdev); /* Do it first for tx broadcast pkt after disconnection issue! */ + rtw_netif_carrier_off(adapter->pnetdev); /* Do it first for tx broadcast pkt after disconnection issue! */ #ifdef CONFIG_IOCTL_CFG80211 rtw_cfg80211_indicate_disconnect(adapter, reason, locally_generated); @@ -228,16 +224,16 @@ void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta) if (psta == NULL) return; - if (psta->aid > NUM_STA) + if (psta->cmn.aid > pstapriv->max_aid) return; - if (pstapriv->sta_aid[psta->aid - 1] != psta) + if (pstapriv->sta_aid[psta->cmn.aid - 1] != psta) return; wrqu.addr.sa_family = ARPHRD_ETHER; - _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN); RTW_INFO("+rtw_indicate_sta_assoc_event\n"); @@ -255,16 +251,16 @@ void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta) if (psta == NULL) return; - if (psta->aid > NUM_STA) + if (psta->cmn.aid > pstapriv->max_aid) return; - if (pstapriv->sta_aid[psta->aid - 1] != psta) + if (pstapriv->sta_aid[psta->cmn.aid - 1] != psta) return; wrqu.addr.sa_family = ARPHRD_ETHER; - _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN); RTW_INFO("+rtw_indicate_sta_disassoc_event\n"); @@ -298,7 +294,7 @@ static int mgnt_netdev_open(struct net_device *pnetdev) rtw_netif_wake_queue(pnetdev); - netif_carrier_on(pnetdev); + rtw_netif_carrier_on(pnetdev); /* rtw_write16(phostapdpriv->padapter, 0x0116, 0x0100); */ /* only excluding beacon */ @@ -312,7 +308,7 @@ static int mgnt_netdev_close(struct net_device *pnetdev) usb_kill_anchored_urbs(&phostapdpriv->anchored); - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); @@ -405,7 +401,7 @@ int hostapd_mode_init(_adapter *padapter) _rtw_memcpy(pnetdev->dev_addr, mac, ETH_ALEN); - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); /* Tell the network stack we exist */ diff --git a/os_dep/linux/os_intfs.c b/os_dep/linux/os_intfs.c index d58b71e..21497ee 100644 --- a/os_dep/linux/os_intfs.c +++ b/os_dep/linux/os_intfs.c @@ -81,8 +81,22 @@ MODULE_PARM_DESC(rtw_ips_mode, "The default IPS mode"); module_param(rtw_lps_level, int, 0644); MODULE_PARM_DESC(rtw_lps_level, "The default LPS level"); +/* LPS: + * rtw_smart_ps = 0 => TX: pwr bit = 1, RX: PS_Poll + * rtw_smart_ps = 1 => TX: pwr bit = 0, RX: PS_Poll + * rtw_smart_ps = 2 => TX: pwr bit = 0, RX: NullData with pwr bit = 0 +*/ int rtw_smart_ps = 2; +#ifdef CONFIG_WMMPS_STA +/* WMMPS: + * rtw_smart_ps = 0 => Only for fw test + * rtw_smart_ps = 1 => Refer to Beacon's TIM Bitmap + * rtw_smart_ps = 2 => Don't refer to Beacon's TIM Bitmap +*/ +int rtw_wmm_smart_ps = 2; +#endif /* CONFIG_WMMPS_STA */ + int rtw_check_fw_ps = 1; #ifdef CONFIG_TX_EARLY_MODE @@ -127,12 +141,15 @@ int rtw_software_decrypt = 0; int rtw_acm_method = 0;/* 0:By SW 1:By HW. */ int rtw_wmm_enable = 1;/* default is set to enable the wmm. */ -int rtw_uapsd_enable = 0; + +#ifdef CONFIG_WMMPS_STA +/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */ +/* 0: NO_LIMIT, 1: TWO_MSDU, 2: FOUR_MSDU, 3: SIX_MSDU */ int rtw_uapsd_max_sp = NO_LIMIT; -int rtw_uapsd_acbk_en = 0; -int rtw_uapsd_acbe_en = 0; -int rtw_uapsd_acvi_en = 0; -int rtw_uapsd_acvo_en = 0; +/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */ +int rtw_uapsd_ac_enable = 0x0; +#endif /* CONFIG_WMMPS_STA */ + #if defined(CONFIG_RTL8814A) int rtw_pwrtrim_enable = 2; /* disable kfree , rename to power trim disable */ #elif defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) @@ -151,14 +168,24 @@ int rtw_ht_enable = 1; /* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz, 4: 80+80MHz * 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 * 0x21 means enable 2.4G 40MHz & 5G 80MHz */ +#ifdef CONFIG_RTW_CUSTOMIZE_BWMODE +int rtw_bw_mode = CONFIG_RTW_CUSTOMIZE_BWMODE; +#else int rtw_bw_mode = 0x21; +#endif int rtw_ampdu_enable = 1;/* for enable tx_ampdu , */ /* 0: disable, 0x1:enable */ int rtw_rx_stbc = 1;/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */ #if (defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)) && defined(CONFIG_PCI_HCI) -int rtw_ampdu_amsdu = 2;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */ +int rtw_rx_ampdu_amsdu = 2;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */ #else -int rtw_ampdu_amsdu = 0;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */ +int rtw_rx_ampdu_amsdu;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */ #endif +/* +* 2: Follow the AMSDU filed in ADDBA Resp. (Deault) +* 0: Force the AMSDU filed in ADDBA Resp. to be disabled. +* 1: Force the AMSDU filed in ADDBA Resp. to be enabled. +*/ +int rtw_tx_ampdu_amsdu = 2; static uint rtw_rx_ampdu_sz_limit_1ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS; static uint rtw_rx_ampdu_sz_limit_1ss_num = 0; @@ -217,7 +244,7 @@ MODULE_PARM_DESC(rtw_vht_rx_mcs_map, "VHT RX MCS map"); int rtw_lowrate_two_xmit = 1;/* Use 2 path Tx to transmit MCS0~7 and legacy mode */ -int rtw_rf_config = RF_TYPE_AUTO; +int rtw_rf_config = RF_TYPE_MAX; module_param(rtw_rf_config, int, 0644); /* 0: not check in watch dog, 1: check in watch dog */ @@ -230,12 +257,6 @@ int rtw_low_power = 0; int rtw_wifi_spec = 0; #endif -#ifdef CONFIG_DEFAULT_PATTERNS_EN - bool rtw_support_default_patterns = _TRUE; -#else - bool rtw_support_default_patterns = _FALSE; -#endif - int rtw_special_rf_path = 0; /* 0: 2T2R ,1: only turn on path A 1T1R */ char rtw_country_unspecified[] = {0xFF, 0xFF, 0x00}; @@ -243,7 +264,7 @@ char *rtw_country_code = rtw_country_unspecified; module_param(rtw_country_code, charp, 0644); MODULE_PARM_DESC(rtw_country_code, "The default country code (in alpha2)"); -int rtw_channel_plan = RTW_CHPLAN_MAX; +int rtw_channel_plan = CONFIG_RTW_CHPLAN; module_param(rtw_channel_plan, int, 0644); MODULE_PARM_DESC(rtw_channel_plan, "The default chplan ID when rtw_alpha2 is not specified or valid"); @@ -282,6 +303,8 @@ int rtw_antdiv_type = 0 int rtw_drv_ant_band_switch = 1; /* 0:OFF , 1:ON, Driver control antenna band switch*/ +int rtw_single_ant_path; /*0:main ant , 1:aux ant , Fixed single antenna path, default main ant*/ + /* 0: doesn't switch, 1: switch from usb2.0 to usb 3.0 2: switch from usb3.0 to usb 2.0 */ int rtw_switch_usb_mode = 0; @@ -315,22 +338,11 @@ int rtw_80211d = 0; #ifdef CONFIG_PCI_ASPM /* CLK_REQ:BIT0 L0s:BIT1 ASPM_L1:BIT2 L1Off:BIT3*/ -int rtw_pci_aspm_enable = 0xF; +int rtw_pci_aspm_enable = 0x5; #else int rtw_pci_aspm_enable; #endif -#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV -int rtw_force_ant = 2;/* 0 :normal, 1:Main ant, 2:Aux ant */ -int rtw_force_igi = 0; /* 0 :normal */ -module_param(rtw_force_ant, int, 0644); -module_param(rtw_force_igi, int, 0644); -#endif - -int rtw_force_igi_lb = CONFIG_RTW_FORCE_IGI_LB; -module_param(rtw_force_igi_lb, int, 0644); -MODULE_PARM_DESC(rtw_force_igi_lb, "force IGI low-bound, 0:no specified"); - #ifdef CONFIG_QOS_OPTIMIZATION int rtw_qos_opt_enable = 1; /* 0: disable,1:enable */ #else @@ -338,13 +350,17 @@ int rtw_qos_opt_enable = 0; /* 0: disable,1:enable */ #endif module_param(rtw_qos_opt_enable, int, 0644); -#ifdef CONFIG_AUTO_CHNL_SEL_NHM -int rtw_acs_mode = 1; /*0:disable, 1:enable*/ -module_param(rtw_acs_mode, int, 0644); - +#ifdef CONFIG_RTW_ACS int rtw_acs_auto_scan = 0; /*0:disable, 1:enable*/ module_param(rtw_acs_auto_scan, int, 0644); +int rtw_acs = 1; +module_param(rtw_acs, int, 0644); +#endif + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR +int rtw_nm = 1;/*noise monitor*/ +module_param(rtw_nm, int, 0644); #endif char *ifname = "wlan%d"; @@ -371,7 +387,9 @@ char *rtw_initmac = 0; /* temp mac address if users want to use instead of the #endif #endif - +#ifdef CONFIG_AP_MODE +u8 rtw_bmc_tx_rate = MGN_UNKNOWN; +#endif module_param(rtw_pwrtrim_enable, int, 0644); module_param(rtw_initmac, charp, 0644); module_param(rtw_special_rf_path, int, 0644); @@ -382,6 +400,11 @@ module_param(rtw_network_mode, int, 0644); module_param(rtw_channel, int, 0644); module_param(rtw_mp_mode, int, 0644); module_param(rtw_wmm_enable, int, 0644); +#ifdef CONFIG_WMMPS_STA +module_param(rtw_uapsd_max_sp, int, 0644); +module_param(rtw_uapsd_ac_enable, int, 0644); +module_param(rtw_wmm_smart_ps, int, 0644); +#endif /* CONFIG_WMMPS_STA */ module_param(rtw_vrtl_carrier_sense, int, 0644); module_param(rtw_vcs_type, int, 0644); module_param(rtw_busy_thresh, int, 0644); @@ -391,7 +414,8 @@ module_param(rtw_ht_enable, int, 0644); module_param(rtw_bw_mode, int, 0644); module_param(rtw_ampdu_enable, int, 0644); module_param(rtw_rx_stbc, int, 0644); -module_param(rtw_ampdu_amsdu, int, 0644); +module_param(rtw_rx_ampdu_amsdu, int, 0644); +module_param(rtw_tx_ampdu_amsdu, int, 0644); #endif /* CONFIG_80211N_HT */ #ifdef CONFIG_BEAMFORMING @@ -409,6 +433,7 @@ module_param(rtw_antdiv_cfg, int, 0644); module_param(rtw_antdiv_type, int, 0644); module_param(rtw_drv_ant_band_switch, int, 0644); +module_param(rtw_single_ant_path, int, 0644); module_param(rtw_switch_usb_mode, int, 0644); @@ -469,6 +494,14 @@ module_param(rtw_80211d, int, 0644); MODULE_PARM_DESC(rtw_80211d, "Enable 802.11d mechanism"); #endif +#ifdef CONFIG_ADVANCE_OTA +/* BIT(0): OTA continuous rotated test within low RSSI,1R CCA in path B + BIT(1) & BIT(2): OTA continuous rotated test with low high RSSI */ +/* Experimental environment: shielding room with half of absorber and 2~3 rotation per minute */ +int rtw_advnace_ota; +module_param(rtw_advnace_ota, int, 0644); +#endif + uint rtw_notch_filter = RTW_NOTCH_FILTER; module_param(rtw_notch_filter, uint, 0644); MODULE_PARM_DESC(rtw_notch_filter, "0:Disable, 1:Enable, 2:Enable only for P2P"); @@ -645,6 +678,29 @@ module_param(rtw_trx_share_mode, int, 0644); MODULE_PARM_DESC(rtw_trx_share_mode, "TRx FIFO Shared"); #endif +#ifdef CONFIG_DYNAMIC_SOML +uint rtw_dynamic_soml_en = 1; +module_param(rtw_dynamic_soml_en, int, 0644); +MODULE_PARM_DESC(rtw_dynamic_soml_en, "0: disable, 1: enable with default param, 2: enable with specified param."); + +uint rtw_dynamic_soml_train_num = 0; +module_param(rtw_dynamic_soml_train_num, int, 0644); +MODULE_PARM_DESC(rtw_dynamic_soml_train_num, "SOML training number"); + +uint rtw_dynamic_soml_interval = 0; +module_param(rtw_dynamic_soml_interval, int, 0644); +MODULE_PARM_DESC(rtw_dynamic_soml_interval, "SOML training interval"); + +uint rtw_dynamic_soml_period = 0; +module_param(rtw_dynamic_soml_period, int, 0644); +MODULE_PARM_DESC(rtw_dynamic_soml_period, "SOML training period"); + +uint rtw_dynamic_soml_delay = 0; +module_param(rtw_dynamic_soml_delay, int, 0644); +MODULE_PARM_DESC(rtw_dynamic_soml_delay, "SOML training delay"); +#endif + + int _netdev_open(struct net_device *pnetdev); int netdev_open(struct net_device *pnetdev); static int netdev_close(struct net_device *pnetdev); @@ -665,11 +721,7 @@ int rtw_mcc_sta_bw80_target_tx_tp = MCC_STA_BW80_TARGET_TX_TP; int rtw_mcc_single_tx_cri = MCC_SINGLE_TX_CRITERIA; int rtw_mcc_policy_table_idx = 0; int rtw_mcc_duration = 0; -int rtw_mcc_tsf_sync_offset = 0; -int rtw_mcc_start_time_offset = 0; -int rtw_mcc_interval = 0; -int rtw_mcc_guard_offset0 = -1; -int rtw_mcc_guard_offset1 = -1; +int rtw_mcc_enable_runtime_duration = 1; module_param(rtw_en_mcc, int, 0644); module_param(rtw_mcc_single_tx_cri, int, 0644); module_param(rtw_mcc_ap_bw20_target_tx_tp, int, 0644); @@ -680,11 +732,6 @@ module_param(rtw_mcc_sta_bw40_target_tx_tp, int, 0644); module_param(rtw_mcc_sta_bw80_target_tx_tp, int, 0644); module_param(rtw_mcc_policy_table_idx, int, 0644); module_param(rtw_mcc_duration, int, 0644); -module_param(rtw_mcc_tsf_sync_offset, int, 0644); -module_param(rtw_mcc_start_time_offset, int, 0644); -module_param(rtw_mcc_interval, int, 0644); -module_param(rtw_mcc_guard_offset0, int, 0644); -module_param(rtw_mcc_guard_offset1, int, 0644); #endif /*CONFIG_MCC_MODE */ #ifdef CONFIG_RTW_NAPI @@ -692,6 +739,10 @@ module_param(rtw_mcc_guard_offset1, int, 0644); enable napi only = 1, disable napi = 0*/ int rtw_en_napi = 1; module_param(rtw_en_napi, int, 0644); +#ifdef CONFIG_RTW_NAPI_DYNAMIC +int rtw_napi_threshold = 100; /* unit: Mbps */ +module_param(rtw_napi_threshold, int, 0644); +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ #ifdef CONFIG_RTW_GRO /*following setting should define GRO in Makefile enable gro = 1, disable gro = 0*/ @@ -707,6 +758,33 @@ int rtw_iqk_fw_offload; #endif /* RTW_IQK_FW_OFFLOAD */ module_param(rtw_iqk_fw_offload, int, 0644); +#ifdef RTW_CHANNEL_SWITCH_OFFLOAD +int rtw_ch_switch_offload = 0; +#else +int rtw_ch_switch_offload; +#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ +module_param(rtw_ch_switch_offload, int, 0644); + +#ifdef CONFIG_TDLS +int rtw_en_tdls = 1; +module_param(rtw_en_tdls, int, 0644); +#endif + +#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT +int rtw_fw_param_init = 1; +module_param(rtw_fw_param_init, int, 0644); +#endif + +#ifdef CONFIG_WOWLAN +/* + * bit[0]: magic packet wake up + * bit[1]: unucast packet(HW/FW unuicast) + * bit[2]: deauth wake up + */ +uint rtw_wakeup_event = RTW_WAKEUP_EVENT; +module_param(rtw_wakeup_event, uint, 0644); +#endif + void rtw_regsty_load_target_tx_power(struct registry_priv *regsty) { int path, rs; @@ -838,14 +916,15 @@ uint loadparam(_adapter *padapter) registry_par->usb_rxagg_mode = (u8)rtw_usb_rxagg_mode; registry_par->dynamic_agg_enable = (u8)rtw_dynamic_agg_enable; - /* UAPSD */ + /* WMM */ registry_par->wmm_enable = (u8)rtw_wmm_enable; - registry_par->uapsd_enable = (u8)rtw_uapsd_enable; - registry_par->uapsd_max_sp = (u8)rtw_uapsd_max_sp; - registry_par->uapsd_acbk_en = (u8)rtw_uapsd_acbk_en; - registry_par->uapsd_acbe_en = (u8)rtw_uapsd_acbe_en; - registry_par->uapsd_acvi_en = (u8)rtw_uapsd_acvi_en; - registry_par->uapsd_acvo_en = (u8)rtw_uapsd_acvo_en; + +#ifdef CONFIG_WMMPS_STA + /* UAPSD */ + registry_par->uapsd_max_sp_len= (u8)rtw_uapsd_max_sp; + registry_par->uapsd_ac_enable = (u8)rtw_uapsd_ac_enable; + registry_par->wmm_smart_ps = (u8)rtw_wmm_smart_ps; +#endif /* CONFIG_WMMPS_STA */ registry_par->RegPwrTrimEnable = (u8)rtw_pwrtrim_enable; @@ -856,7 +935,8 @@ uint loadparam(_adapter *padapter) registry_par->bw_mode = (u8)rtw_bw_mode; registry_par->ampdu_enable = (u8)rtw_ampdu_enable; registry_par->rx_stbc = (u8)rtw_rx_stbc; - registry_par->ampdu_amsdu = (u8)rtw_ampdu_amsdu; + registry_par->rx_ampdu_amsdu = (u8)rtw_rx_ampdu_amsdu; + registry_par->tx_ampdu_amsdu = (u8)rtw_tx_ampdu_amsdu; registry_par->short_gi = (u8)rtw_short_gi; registry_par->ldpc_cap = (u8)rtw_ldpc_cap; registry_par->stbc_cap = (u8)rtw_stbc_cap; @@ -906,6 +986,7 @@ uint loadparam(_adapter *padapter) registry_par->bt_sco = (u8)rtw_bt_sco; registry_par->bt_ampdu = (u8)rtw_bt_ampdu; registry_par->ant_num = (u8)rtw_ant_num; + registry_par->single_ant_path = (u8) rtw_single_ant_path; #endif registry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq; @@ -952,17 +1033,9 @@ uint loadparam(_adapter *padapter) registry_par->notch_filter = (u8)rtw_notch_filter; -#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - registry_par->force_ant = (u8)rtw_force_ant; - registry_par->force_igi = (u8)rtw_force_igi; -#endif - #ifdef CONFIG_CONCURRENT_MODE registry_par->virtual_iface_num = (u8)rtw_virtual_iface_num; #endif - - registry_par->force_igi_lb = (u8)rtw_force_igi_lb; - registry_par->pll_ref_clk_sel = (u8)rtw_pll_ref_clk_sel; #ifdef CONFIG_TXPWR_LIMIT @@ -995,11 +1068,23 @@ uint loadparam(_adapter *padapter) registry_par->adaptivity_th_l2h_ini = (s8)rtw_adaptivity_th_l2h_ini; registry_par->adaptivity_th_edcca_hl_diff = (s8)rtw_adaptivity_th_edcca_hl_diff; +#ifdef CONFIG_DYNAMIC_SOML + registry_par->dyn_soml_en = (u8)rtw_dynamic_soml_en; + registry_par->dyn_soml_train_num = (u8)rtw_dynamic_soml_train_num; + registry_par->dyn_soml_interval = (u8)rtw_dynamic_soml_interval; + registry_par->dyn_soml_period = (u8)rtw_dynamic_soml_period; + registry_par->dyn_soml_delay = (u8)rtw_dynamic_soml_delay; +#endif + registry_par->boffefusemask = (u8)rtw_OffEfuseMask; registry_par->bFileMaskEfuse = (u8)rtw_FileMaskEfuse; -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - registry_par->acs_mode = (u8)rtw_acs_mode; + +#ifdef CONFIG_RTW_ACS + registry_par->acs_mode = (u8)rtw_acs; registry_par->acs_auto_scan = (u8)rtw_acs_auto_scan; +#endif +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + registry_par->nm_mode = (u8)rtw_nm; #endif registry_par->reg_rxgain_offset_2g = (u32) rtw_rxgain_offset_2g; registry_par->reg_rxgain_offset_5gl = (u32) rtw_rxgain_offset_5gl; @@ -1021,14 +1106,11 @@ uint loadparam(_adapter *padapter) registry_par->rtw_mcc_single_tx_cri = (u32)rtw_mcc_single_tx_cri; registry_par->rtw_mcc_policy_table_idx = rtw_mcc_policy_table_idx; registry_par->rtw_mcc_duration = (u8)rtw_mcc_duration; - registry_par->rtw_mcc_tsf_sync_offset = (u8)rtw_mcc_tsf_sync_offset; - registry_par->rtw_mcc_start_time_offset = (u8)rtw_mcc_start_time_offset; - registry_par->rtw_mcc_interval = (u8)rtw_mcc_interval; - registry_par->rtw_mcc_guard_offset0 = rtw_mcc_guard_offset0; - registry_par->rtw_mcc_guard_offset1 = rtw_mcc_guard_offset1; + registry_par->rtw_mcc_enable_runtime_duration = rtw_mcc_enable_runtime_duration; #endif /*CONFIG_MCC_MODE */ -#ifdef CONFIG_DEFAULT_PATTERNS_EN - registry_par->default_patterns_en = rtw_support_default_patterns; + +#ifdef CONFIG_WOWLAN + registry_par->wakeup_event = rtw_wakeup_event; #endif #ifdef CONFIG_SUPPORT_TRX_SHARED @@ -1041,6 +1123,9 @@ uint loadparam(_adapter *padapter) #ifdef CONFIG_RTW_NAPI registry_par->en_napi = (u8)rtw_en_napi; +#ifdef CONFIG_RTW_NAPI_DYNAMIC + registry_par->napi_threshold = (u32)rtw_napi_threshold; +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ #ifdef CONFIG_RTW_GRO registry_par->en_gro = (u8)rtw_en_gro; if (!registry_par->en_napi && registry_par->en_gro) { @@ -1051,7 +1136,21 @@ uint loadparam(_adapter *padapter) #endif /* CONFIG_RTW_NAPI */ registry_par->iqk_fw_offload = (u8)rtw_iqk_fw_offload; + registry_par->ch_switch_offload = (u8)rtw_ch_switch_offload; + +#ifdef CONFIG_TDLS + registry_par->en_tdls = rtw_en_tdls; +#endif +#ifdef CONFIG_ADVANCE_OTA + registry_par->adv_ota = rtw_advnace_ota; +#endif +#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT + registry_par->fw_param_init = rtw_fw_param_init; +#endif +#ifdef CONFIG_AP_MODE + registry_par->bmc_tx_rate = rtw_bmc_tx_rate; +#endif return status; } @@ -1375,7 +1474,7 @@ int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname) if (dev_alloc_name(pnetdev, ifname) < 0) RTW_ERR("dev_alloc_name, fail!\n"); - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); /* rtw_netif_stop_queue(pnetdev); */ return 0; @@ -1431,6 +1530,13 @@ struct net_device *rtw_init_netdev(_adapter *old_padapter) pnetdev->features |= NETIF_F_IP_CSUM; #endif +#ifdef CONFIG_RTW_NETIF_SG + pnetdev->features |= NETIF_F_SG; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39) + pnetdev->hw_features |= NETIF_F_SG; +#endif +#endif + /* pnetdev->tx_timeout = NULL; */ pnetdev->watchdog_timeo = HZ * 3; /* 3 second timeout */ @@ -1513,10 +1619,6 @@ int rtw_os_ndev_register(_adapter *adapter, const char *name) } #endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) - ndev->gro_flush_timeout = 100000; -#endif - /* alloc netdev name */ rtw_init_netdev_name(ndev, name); @@ -1578,6 +1680,9 @@ void rtw_os_ndev_unregister(_adapter *adapter) } #if defined(CONFIG_IOCTL_CFG80211) && !defined(RTW_SINGLE_WIPHY) +#ifdef CONFIG_RFKILL_POLL + rtw_cfg80211_deinit_rfkill(adapter_to_wiphy(adapter)); +#endif rtw_wiphy_unregister(adapter_to_wiphy(adapter)); #endif @@ -1719,40 +1824,52 @@ u32 rtw_start_drv_threads(_adapter *padapter) if (is_primary_adapter(padapter)) #endif { - padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD"); - if (IS_ERR(padapter->xmitThread)) { - padapter->xmitThread = NULL; - _status = _FAIL; + if (padapter->xmitThread == NULL) { + RTW_INFO(FUNC_ADPT_FMT " start RTW_XMIT_THREAD\n", FUNC_ADPT_ARG(padapter)); + padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD"); + if (IS_ERR(padapter->xmitThread)) { + padapter->xmitThread = NULL; + _status = _FAIL; + } } } #endif /* #ifdef CONFIG_XMIT_THREAD_MODE */ #ifdef CONFIG_RECV_THREAD_MODE if (is_primary_adapter(padapter)) { - padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD"); - if (IS_ERR(padapter->recvThread)) { - padapter->recvThread = NULL; - _status = _FAIL; + if (padapter->recvThread == NULL) { + RTW_INFO(FUNC_ADPT_FMT " start RTW_RECV_THREAD\n", FUNC_ADPT_ARG(padapter)); + padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD"); + if (IS_ERR(padapter->recvThread)) { + padapter->recvThread = NULL; + _status = _FAIL; + } } } #endif if (is_primary_adapter(padapter)) { - padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD"); - if (IS_ERR(padapter->cmdThread)) { - padapter->cmdThread = NULL; - _status = _FAIL; + if (padapter->cmdThread == NULL) { + RTW_INFO(FUNC_ADPT_FMT " start RTW_CMD_THREAD\n", FUNC_ADPT_ARG(padapter)); + padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD"); + if (IS_ERR(padapter->cmdThread)) { + padapter->cmdThread = NULL; + _status = _FAIL; + } + else + _rtw_down_sema(&padapter->cmdpriv.start_cmdthread_sema); /* wait for cmd_thread to run */ } - else - _rtw_down_sema(&padapter->cmdpriv.start_cmdthread_sema); /* wait for cmd_thread to run */ } #ifdef CONFIG_EVENT_THREAD_MODE - padapter->evtThread = kthread_run(event_thread, padapter, "RTW_EVENT_THREAD"); - if (IS_ERR(padapter->evtThread)) { - padapter->evtThread = NULL; - _status = _FAIL; + if (padapter->evtThread == NULL) { + RTW_INFO(FUNC_ADPT_FMT " start RTW_EVENT_THREAD\n", FUNC_ADPT_ARG(padapter)); + padapter->evtThread = kthread_run(event_thread, padapter, "RTW_EVENT_THREAD"); + if (IS_ERR(padapter->evtThread)) { + padapter->evtThread = NULL; + _status = _FAIL; + } } #endif @@ -1853,6 +1970,11 @@ u8 rtw_init_default_value(_adapter *padapter) /* hal_priv */ rtw_hal_def_value_init(padapter); +#ifdef CONFIG_MCC_MODE + /* MCC parameter */ + rtw_hal_mcc_parameter_init(padapter); +#endif /* CONFIG_MCC_MODE */ + /* misc. */ RTW_ENABLE_FUNC(padapter, DF_RX_BIT); RTW_ENABLE_FUNC(padapter, DF_TX_BIT); @@ -1869,7 +1991,9 @@ u8 rtw_init_default_value(_adapter *padapter) padapter->power_offset = 0; padapter->rsvd_page_offset = 0; padapter->rsvd_page_num = 0; - +#ifdef CONFIG_AP_MODE + padapter->bmc_tx_rate = pregistrypriv->bmc_tx_rate; +#endif padapter->driver_tx_bw_mode = pregistrypriv->tx_bw_mode; padapter->driver_ampdu_spacing = 0xFF; @@ -1894,10 +2018,18 @@ u8 rtw_init_default_value(_adapter *padapter) padapter->tsf.sync_port = MAX_HW_PORT; padapter->tsf.offset = 0; -#ifdef CONFIG_CHNL_LOAD_MAGT - padapter->clm_flag = FALSE; +#ifdef CONFIG_RTW_ACS + if (pregistrypriv->acs_mode) + rtw_acs_start(padapter); + else + rtw_acs_stop(padapter); +#endif +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + if (pregistrypriv->nm_mode) + rtw_nm_enable(padapter); + else + rtw_nm_disable(padapter); #endif - return ret; } @@ -1953,6 +2085,11 @@ struct dvobj_priv *devobj_init(void) _rtw_spinlock_init(&pdvobj->mcc_objpriv.mcc_lock); #endif /* CONFIG_MCC_MODE */ +#ifdef CONFIG_RTW_NAPI_DYNAMIC + pdvobj->en_napi_dynamic = 0; +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ + + return pdvobj; } @@ -2145,6 +2282,10 @@ u8 rtw_init_drv_sw(_adapter *padapter) } #endif /* CONFIG_TDLS */ +#ifdef CONFIG_RTW_MESH + rtw_mesh_cfg_init(padapter); +#endif + if (_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL) { RTW_INFO("Can't _rtw_init_xmit_priv\n"); ret8 = _FAIL; @@ -2168,7 +2309,6 @@ u8 rtw_init_drv_sw(_adapter *padapter) goto exit; } - padapter->stapriv.padapter = padapter; padapter->setband = WIFI_FREQUENCY_BAND_AUTO; padapter->fix_rate = 0xFF; padapter->power_offset = 0; @@ -2196,7 +2336,7 @@ u8 rtw_init_drv_sw(_adapter *padapter) #endif rtw_hal_dm_init(padapter); -#ifdef CONFIG_SW_LED +#ifdef CONFIG_RTW_SW_LED rtw_hal_sw_led_init(padapter); #endif #ifdef DBG_CONFIG_ERROR_DETECT @@ -2226,6 +2366,14 @@ u8 rtw_init_drv_sw(_adapter *padapter) #endif /* RTW_BEAMFORMING_VERSION_2 */ #endif /* CONFIG_BEAMFORMING */ +#ifdef CONFIG_RTW_REPEATER_SON + init_rtw_rson_data(adapter_to_dvobj(padapter)); +#endif + +#ifdef CONFIG_RTW_80211K + rtw_init_rm(padapter); +#endif + exit: @@ -2253,10 +2401,10 @@ void rtw_cancel_all_timer(_adapter *padapter) #endif _cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer); - +#ifdef CONFIG_RTW_SW_LED /* cancel sw led timer */ rtw_hal_sw_led_deinit(padapter); - +#endif _cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_state_check_timer)); #ifdef CONFIG_TX_AMSDU @@ -2334,6 +2482,10 @@ u8 rtw_free_drv_sw(_adapter *padapter) /* rtw_free_tdls_info(&padapter->tdlsinfo); */ #endif /* CONFIG_TDLS */ +#ifdef CONFIG_RTW_80211K + rtw_free_rm_priv(padapter); +#endif + rtw_free_cmd_priv(&padapter->cmdpriv); rtw_free_evt_priv(&padapter->evtpriv); @@ -2355,10 +2507,6 @@ u8 rtw_free_drv_sw(_adapter *padapter) /* rtw_mfree((void *)padapter, sizeof (padapter)); */ -#ifdef CONFIG_DRVEXT_MODULE - free_drvext(&padapter->drvextpriv); -#endif - rtw_hal_free_data(padapter); @@ -2468,7 +2616,7 @@ int _netdev_vir_if_open(struct net_device *pnetdev) } #endif - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); return -1; @@ -2619,6 +2767,10 @@ _adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, #ifdef CONFIG_P2P rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); #endif + + rtw_led_set_ctl_en_mask_virtual(padapter); + rtw_led_set_iface_en(padapter, 1); + res = _SUCCESS; free_drv_sw: @@ -2647,7 +2799,7 @@ void rtw_drv_stop_vir_if(_adapter *padapter) rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); #ifdef CONFIG_AP_MODE - if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { free_mlme_ap_info(padapter); #ifdef CONFIG_HOSTAPD_MLME hostapd_mode_unload(padapter); @@ -2765,6 +2917,7 @@ static int rtw_inetaddr_notifier_call(struct notifier_block *nb, return NOTIFY_DONE; } +#ifdef CONFIG_IPV6 static int rtw_inet6addr_notifier_call(struct notifier_block *nb, unsigned long action, void *data) { @@ -2820,27 +2973,34 @@ static int rtw_inet6addr_notifier_call(struct notifier_block *nb, } return NOTIFY_DONE; } +#endif static struct notifier_block rtw_inetaddr_notifier = { .notifier_call = rtw_inetaddr_notifier_call }; +#ifdef CONFIG_IPV6 static struct notifier_block rtw_inet6addr_notifier = { .notifier_call = rtw_inet6addr_notifier_call }; +#endif void rtw_inetaddr_notifier_register(void) { RTW_INFO("%s\n", __func__); register_inetaddr_notifier(&rtw_inetaddr_notifier); +#ifdef CONFIG_IPV6 register_inet6addr_notifier(&rtw_inet6addr_notifier); +#endif } void rtw_inetaddr_notifier_unregister(void) { RTW_INFO("%s\n", __func__); unregister_inetaddr_notifier(&rtw_inetaddr_notifier); +#ifdef CONFIG_IPV6 unregister_inet6addr_notifier(&rtw_inet6addr_notifier); +#endif } int rtw_os_ndevs_register(struct dvobj_priv *dvobj) @@ -3028,10 +3188,12 @@ int _netdev_open(struct net_device *pnetdev) rtw_sdio_set_power(1); #endif /* CONFIG_PLATFORM_INTEL_BYT */ + #ifdef CONFIG_AUTOSUSPEND if (pwrctrlpriv->ps_flag == _TRUE) { padapter->net_closed = _FALSE; goto netdev_open_normal_process; } + #endif if (padapter->bup == _FALSE) { #ifdef CONFIG_PLATFORM_INTEL_BYT @@ -3056,11 +3218,13 @@ int _netdev_open(struct net_device *pnetdev) RTW_INFO("MAC Address = "MAC_FMT"\n", MAC_ARG(pnetdev->dev_addr)); +#ifndef RTW_HALMAC status = rtw_start_drv_threads(padapter); if (status == _FAIL) { RTW_INFO("Initialize driver software resource Failed!\n"); goto netdev_open_error; } +#endif /* !RTW_HALMAC */ #ifdef CONFIG_RTW_NAPI if(padapter->napi_state == NAPI_DISABLE) { @@ -3069,10 +3233,9 @@ int _netdev_open(struct net_device *pnetdev) } #endif -#ifdef CONFIG_DRVEXT_MODULE - init_drvext(padapter); -#endif +#ifndef RTW_HALMAC rtw_intf_start(padapter); +#endif /* !RTW_HALMAC */ #ifdef CONFIG_IOCTL_CFG80211 rtw_cfg80211_init_wiphy(padapter); @@ -3098,7 +3261,7 @@ int _netdev_open(struct net_device *pnetdev) rtw_set_pwr_state_check_timer(pwrctrlpriv); #endif - /* netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */ + /* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */ rtw_netif_wake_queue(pnetdev); #ifdef CONFIG_BR_EXT @@ -3128,6 +3291,15 @@ int _netdev_open(struct net_device *pnetdev) } #endif +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + pwrctrlpriv->radio_on_start_time = rtw_get_current_time(); + pwrctrlpriv->pwr_saving_start_time = rtw_get_current_time(); + pwrctrlpriv->pwr_saving_time = 0; + pwrctrlpriv->on_time = 0; + pwrctrlpriv->tx_time = 0; + pwrctrlpriv->rx_time = 0; +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + RTW_INFO("-871x_drv - drv_open, bup=%d\n", padapter->bup); return 0; @@ -3143,7 +3315,7 @@ int _netdev_open(struct net_device *pnetdev) } #endif - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); RTW_INFO("-871x_drv - drv_open fail, bup=%d\n", padapter->bup); @@ -3202,7 +3374,9 @@ int ips_netdrv_open(_adapter *padapter) #if 0 rtw_restore_mac_addr(padapter); #endif +#ifndef RTW_HALMAC rtw_intf_start(padapter); +#endif /* !RTW_HALMAC */ #ifndef CONFIG_IPS_CHECK_IN_WD rtw_set_pwr_state_check_timer(adapter_to_pwrctl(padapter)); @@ -3225,7 +3399,7 @@ int rtw_ips_pwr_up(_adapter *padapter) #ifdef DBG_CONFIG_ERROR_DETECT struct sreset_priv *psrtpriv = &pHalData->srestpriv; #endif/* #ifdef DBG_CONFIG_ERROR_DETECT */ - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); RTW_INFO("===> rtw_ips_pwr_up..............\n"); #if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) @@ -3246,7 +3420,7 @@ int rtw_ips_pwr_up(_adapter *padapter) void rtw_ips_pwr_down(_adapter *padapter) { - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); RTW_INFO("===> rtw_ips_pwr_down...................\n"); padapter->net_closed = _TRUE; @@ -3314,11 +3488,13 @@ static int netdev_close(struct net_device *pnetdev) RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); #ifndef CONFIG_PLATFORM_INTEL_BYT + #ifdef CONFIG_AUTOSUSPEND if (pwrctl->bInternalAutoSuspend == _TRUE) { /* rtw_pwr_wakeup(padapter); */ if (pwrctl->rf_pwrstate == rf_off) pwrctl->ps_flag = _TRUE; } + #endif padapter->net_closed = _TRUE; padapter->netif_up = _FALSE; pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; @@ -3349,8 +3525,6 @@ static int netdev_close(struct net_device *pnetdev) /* s2-4. */ rtw_free_network_queue(padapter, _TRUE); #endif - /* Close LED */ - rtw_led_control(padapter, LED_CTL_POWER_OFF); } #ifdef CONFIG_BR_EXT @@ -3552,7 +3726,11 @@ static int route_dump(u32 *gw_addr , int *gw_index) oldfs = get_fs(); set_fs(KERNEL_DS); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) + err = sock_recvmsg(sock, &msg, MSG_DONTWAIT); +#else err = sock_recvmsg(sock, &msg, PAGE_SIZE, MSG_DONTWAIT); +#endif set_fs(oldfs); if (err < 0) @@ -3749,8 +3927,10 @@ void rtw_dev_unload(PADAPTER padapter) rtw_intf_stop(padapter); - - if (!pwrctl->bInternalAutoSuspend) { + #ifdef CONFIG_AUTOSUSPEND + if (!pwrctl->bInternalAutoSuspend) + #endif + { rtw_stop_drv_threads(padapter); if (ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE) { @@ -3827,7 +4007,7 @@ int rtw_suspend_free_assoc_resource(_adapter *padapter) rtw_indicate_disconnect(padapter, 0, _FALSE); } #ifdef CONFIG_AP_MODE - else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) + else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) rtw_sta_flush(padapter, _TRUE); #endif @@ -3860,14 +4040,8 @@ int rtw_suspend_wow(_adapter *padapter) { u8 ch, bw, offset; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct net_device *pnetdev = padapter->pnetdev; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct wowlan_ioctl_param poidparam; - int i; - _adapter *iface = NULL; u8 ps_mode; int ret = _SUCCESS; @@ -3881,9 +4055,10 @@ int rtw_suspend_wow(_adapter *padapter) #endif if (pwrpriv->wowlan_mode == _TRUE) { - if (pnetdev) - rtw_netif_stop_queue(pnetdev); - rtw_mi_buddy_netif_stop_queue(padapter, _TRUE); + rtw_mi_netif_stop_queue(padapter); + #ifdef CONFIG_CONCURRENT_MODE + rtw_mi_buddy_netif_carrier_off(padapter); + #endif /* 0. Power off LED */ rtw_led_control(padapter, LED_CTL_POWER_OFF); @@ -3898,23 +4073,20 @@ int rtw_suspend_wow(_adapter *padapter) /* 1. stop thread */ rtw_set_drv_stopped(padapter); /*for stop thread*/ - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if ((iface) && (iface->bup == _TRUE)) - rtw_stop_drv_threads(iface); - } + rtw_mi_stop_drv_threads(padapter); + rtw_clr_drv_stopped(padapter); /*for 32k command*/ /* #ifdef CONFIG_LPS */ /* rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN"); */ /* #endif */ + #ifdef CONFIG_SDIO_HCI /* 2.2 free irq */ - /* sdio_free_irq(adapter_to_dvobj(padapter)); */ -#if !(CONFIG_RTW_SDIO_KEEP_IRQ) - if (padapter->intf_free_irq) - padapter->intf_free_irq(adapter_to_dvobj(padapter)); -#endif + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + sdio_free_irq(adapter_to_dvobj(padapter)); + #endif + #endif/*CONFIG_SDIO_HCI*/ #ifdef CONFIG_RUNTIME_PORT_SWITCH if (rtw_port_switch_chk(padapter)) { @@ -3963,15 +4135,14 @@ int rtw_suspend_wow(_adapter *padapter) rtw_mi_update_union_chan_inf(padapter, ch, offset, bw); } #endif +#ifdef CONFIG_CONCURRENT_MODE + rtw_mi_buddy_suspend_free_assoc_resource(padapter); +#endif #ifdef CONFIG_BT_COEXIST rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT); #endif -#ifdef CONFIG_CONCURRENT_MODE - rtw_mi_buddy_suspend_free_assoc_resource(padapter); -#endif - if (pwrpriv->wowlan_pno_enable) { RTW_PRINT("%s: pno: %d\n", __func__, pwrpriv->wowlan_pno_enable); @@ -4000,13 +4171,8 @@ int rtw_suspend_ap_wow(_adapter *padapter) { u8 ch, bw, offset; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct wowlan_ioctl_param poidparam; - int i; - _adapter *iface = NULL; u8 ps_mode; int ret = _SUCCESS; @@ -4016,7 +4182,7 @@ int rtw_suspend_ap_wow(_adapter *padapter) RTW_INFO("wowlan_ap_mode: %d\n", pwrpriv->wowlan_ap_mode); - rtw_mi_netif_stop_queue(padapter, _FALSE); + rtw_mi_netif_stop_queue(padapter); /* 0. Power off LED */ rtw_led_control(padapter, LED_CTL_POWER_OFF); @@ -4030,16 +4196,15 @@ int rtw_suspend_ap_wow(_adapter *padapter) /* 1. stop thread */ rtw_set_drv_stopped(padapter); /*for stop thread*/ - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if ((iface) && (iface->bup == _TRUE)) - rtw_stop_drv_threads(iface); - } + rtw_mi_stop_drv_threads(padapter); rtw_clr_drv_stopped(padapter); /*for 32k command*/ + #ifdef CONFIG_SDIO_HCI /* 2.2 free irq */ - if (padapter->intf_free_irq) - padapter->intf_free_irq(adapter_to_dvobj(padapter)); + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + sdio_free_irq(adapter_to_dvobj(padapter)); + #endif + #endif/*CONFIG_SDIO_HCI*/ #ifdef CONFIG_RUNTIME_PORT_SWITCH if (rtw_port_switch_chk(padapter)) { @@ -4068,10 +4233,6 @@ int rtw_suspend_ap_wow(_adapter *padapter) } #endif -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT); -#endif - /*FOR ONE AP - TODO :Multi-AP*/ { int i; @@ -4081,13 +4242,17 @@ int rtw_suspend_ap_wow(_adapter *padapter) for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if ((iface) && rtw_is_adapter_up(iface)) { - if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | _FW_LINKED)) - rtw_mi_buddy_suspend_free_assoc_resource(iface); + if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE) + rtw_suspend_free_assoc_resource(iface); } } } +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT); +#endif + #ifdef CONFIG_LPS if (!(pwrpriv->wowlan_dis_lps)) { rtw_wow_lps_level_decide(padapter, _TRUE); @@ -4112,8 +4277,7 @@ int rtw_suspend_normal(_adapter *padapter) #ifdef CONFIG_BT_COEXIST rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND); #endif - - rtw_mi_netif_stop_queue(padapter, _TRUE); + rtw_mi_netif_caroff_qstop(padapter); rtw_mi_suspend_free_assoc_resource(padapter); @@ -4131,14 +4295,13 @@ int rtw_suspend_normal(_adapter *padapter) #endif rtw_dev_unload(padapter); - /* sdio_deinit(adapter_to_dvobj(padapter)); */ - if (padapter->intf_deinit) - padapter->intf_deinit(adapter_to_dvobj(padapter)); + #ifdef CONFIG_SDIO_HCI + sdio_deinit(adapter_to_dvobj(padapter)); -#if !(CONFIG_RTW_SDIO_KEEP_IRQ) - if(padapter->intf_free_irq) - padapter->intf_free_irq(adapter_to_dvobj(padapter)); -#endif + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + sdio_free_irq(adapter_to_dvobj(padapter)); + #endif + #endif /*CONFIG_SDIO_HCI*/ RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); return ret; @@ -4146,13 +4309,13 @@ int rtw_suspend_normal(_adapter *padapter) int rtw_suspend_common(_adapter *padapter) { - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(psdpriv); + struct dvobj_priv *dvobj = padapter->dvobj; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; int ret = 0; - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); RTW_PRINT(" suspend start\n"); RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid); @@ -4232,7 +4395,6 @@ int rtw_resume_process_wow(_adapter *padapter) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct net_device *pnetdev = padapter->pnetdev; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; @@ -4243,7 +4405,6 @@ int rtw_resume_process_wow(_adapter *padapter) RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); if (padapter) { - pnetdev = padapter->pnetdev; pwrpriv = adapter_to_pwrctl(padapter); } else { pdbgpriv->dbg_resume_error_cnt++; @@ -4282,13 +4443,14 @@ int rtw_resume_process_wow(_adapter *padapter) rtw_hal_clear_interrupt(padapter); #endif -#if !(CONFIG_RTW_SDIO_KEEP_IRQ) - /* if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { */ - if ((padapter->intf_alloc_irq) && (padapter->intf_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS)) { + #ifdef CONFIG_SDIO_HCI + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { ret = -1; goto exit; } -#endif + #endif + #endif/*CONFIG_SDIO_HCI*/ /* Disable WOW, set H2C command */ poidparam.subcode = WOWLAN_DISABLE; @@ -4315,8 +4477,8 @@ int rtw_resume_process_wow(_adapter *padapter) #endif /* start netif queue */ - if (pnetdev) - rtw_netif_wake_queue(pnetdev); + rtw_mi_netif_wake_queue(padapter); + } else RTW_PRINT("%s: ### ERROR ### wowlan_mode=%d\n", __FUNCTION__, pwrpriv->wowlan_mode); @@ -4348,21 +4510,6 @@ int rtw_resume_process_wow(_adapter *padapter) } } - if (pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT) - rtw_lock_ext_suspend_timeout(2000); - - if (pwrpriv->wowlan_wake_reason == RX_GTK || - pwrpriv->wowlan_wake_reason == RX_DISASSOC|| - pwrpriv->wowlan_wake_reason == RX_DEAUTH) - rtw_lock_ext_suspend_timeout(8000); - - if (pwrpriv->wowlan_wake_reason == RX_PNO) { - #ifdef CONFIG_IOCTL_CFG80211 - rtw_cfg80211_disconnected(padapter->rtw_wdev, 0, NULL, 0, 1, GFP_ATOMIC); - #endif - rtw_lock_ext_suspend_timeout(10000); - } - if (pwrpriv->wowlan_mode == _TRUE) { pwrpriv->bips_processing = _FALSE; _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); @@ -4375,7 +4522,7 @@ int rtw_resume_process_wow(_adapter *padapter) pwrpriv->wowlan_mode = _FALSE; /* Power On LED */ -#ifdef CONFIG_SW_LED +#ifdef CONFIG_RTW_SW_LED if (pwrpriv->wowlan_wake_reason == RX_DISASSOC|| pwrpriv->wowlan_wake_reason == RX_DEAUTH|| @@ -4402,7 +4549,6 @@ int rtw_resume_process_wow(_adapter *padapter) int rtw_resume_process_ap_wow(_adapter *padapter) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct net_device *pnetdev = padapter->pnetdev; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; @@ -4414,7 +4560,6 @@ int rtw_resume_process_ap_wow(_adapter *padapter) RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); if (padapter) { - pnetdev = padapter->pnetdev; pwrpriv = adapter_to_pwrctl(padapter); } else { pdbgpriv->dbg_resume_error_cnt++; @@ -4436,12 +4581,14 @@ int rtw_resume_process_ap_wow(_adapter *padapter) rtw_hal_clear_interrupt(padapter); - /* if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { */ - if ((padapter->intf_alloc_irq) && (padapter->intf_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS)) { + #ifdef CONFIG_SDIO_HCI + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { ret = -1; goto exit; } - + #endif + #endif/*CONFIG_SDIO_HCI*/ /* Disable WOW, set H2C command */ poidparam.subcode = WOWLAN_AP_DISABLE; rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam); @@ -4477,13 +4624,15 @@ int rtw_resume_process_ap_wow(_adapter *padapter) for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if ((iface) && rtw_is_adapter_up(iface)) { - if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | _FW_LINKED)) + if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE | _FW_LINKED)) rtw_reset_drv_sw(iface); } } } rtw_mi_intf_start(padapter); + + /* start netif queue */ rtw_mi_netif_wake_queue(padapter); if (padapter->pid[1] != 0) { @@ -4495,9 +4644,6 @@ int rtw_resume_process_ap_wow(_adapter *padapter) /* rtw_unlock_suspend(); */ #endif /* CONFIG_RESUME_IN_WORKQUEUE */ - if (pwrpriv->wowlan_wake_reason == AP_OFFLOAD_WAKEUP) - rtw_lock_ext_suspend_timeout(8000); - pwrpriv->bips_processing = _FALSE; _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); #ifndef CONFIG_IPS_CHECK_IN_WD @@ -4511,7 +4657,7 @@ int rtw_resume_process_ap_wow(_adapter *padapter) #endif /* CONFIG_BT_COEXIST */ /* Power On LED */ -#ifdef CONFIG_SW_LED +#ifdef CONFIG_RTW_SW_LED rtw_led_control(padapter, LED_CTL_LINK); #endif @@ -4534,18 +4680,18 @@ void rtw_mi_resume_process_normal(_adapter *padapter) pmlmepriv = &iface->mlmepriv; if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv)); - if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) - rtw_roaming(padapter, NULL); + if (rtw_chk_roam_flags(iface, RTW_ROAM_ON_RESUME)) + rtw_roaming(iface, NULL); - } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); - rtw_ap_restore_network(padapter); + } else if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) { + RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(iface), MLME_IS_AP(iface) ? "AP" : "MESH"); + rtw_ap_restore_network(iface); } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) - RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv)); else - RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv)); } } } @@ -4570,21 +4716,26 @@ int rtw_resume_process_normal(_adapter *padapter) pdbgpriv = &psdpriv->drv_dbg; RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); + + #ifdef CONFIG_SDIO_HCI /* interface init */ - /* if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) */ - if ((padapter->intf_init) && (padapter->intf_init(adapter_to_dvobj(padapter)) != _SUCCESS)) { + if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) { ret = -1; goto exit; } + #endif/*CONFIG_SDIO_HCI*/ + rtw_clr_surprise_removed(padapter); rtw_hal_disable_interrupt(padapter); -#if !(CONFIG_RTW_SDIO_KEEP_IRQ) - /* if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) */ - if ((padapter->intf_alloc_irq) && (padapter->intf_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS)) { + + #ifdef CONFIG_SDIO_HCI + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { ret = -1; goto exit; } -#endif + #endif + #endif/*CONFIG_SDIO_HCI*/ rtw_mi_reset_drv_sw(padapter); @@ -4597,7 +4748,7 @@ int rtw_resume_process_normal(_adapter *padapter) goto exit; } - rtw_mi_netif_carrier_on(padapter); + rtw_mi_netif_caron_qstart(padapter); if (padapter->pid[1] != 0) { RTW_INFO("pid[1]:%d\n", padapter->pid[1]); @@ -4622,7 +4773,7 @@ int rtw_resume_process_normal(_adapter *padapter) int rtw_resume_common(_adapter *padapter) { int ret = 0; - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; diff --git a/os_dep/linux/recv_linux.c b/os_dep/linux/recv_linux.c index 2541885..d099f69 100644 --- a/os_dep/linux/recv_linux.c +++ b/os_dep/linux/recv_linux.c @@ -161,8 +161,7 @@ int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 void rtw_os_free_recvframe(union recv_frame *precvframe) { if (precvframe->u.hdr.pkt) { - rtw_skb_free(precvframe->u.hdr.pkt);/* free skb by driver */ - + rtw_os_pkt_free(precvframe->u.hdr.pkt); precvframe->u.hdr.pkt = NULL; } } @@ -185,7 +184,7 @@ int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe) { int res = _SUCCESS; - precvframe->u.hdr.pkt_newalloc = precvframe->u.hdr.pkt = NULL; + precvframe->u.hdr.pkt = NULL; return res; } @@ -205,10 +204,7 @@ void rtw_os_recv_resource_free(struct recv_priv *precvpriv) #endif /* CONFIG_RTW_NAPI */ for (i = 0; i < NR_RECVFRAME; i++) { - if (precvframe->u.hdr.pkt) { - rtw_skb_free(precvframe->u.hdr.pkt);/* free skb by driver */ - precvframe->u.hdr.pkt = NULL; - } + rtw_os_free_recvframe(precvframe); precvframe++; } } @@ -285,7 +281,7 @@ int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf) } -_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 *pdata) +_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa, u8 *msdu ,u16 msdu_len) { u16 eth_type; u8 *data_ptr; @@ -295,19 +291,19 @@ _pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 pattrib = &prframe->u.hdr.attrib; #ifdef CONFIG_SKB_COPY - sub_skb = rtw_skb_alloc(nSubframe_Length + 12); + sub_skb = rtw_skb_alloc(msdu_len + 14); if (sub_skb) { - skb_reserve(sub_skb, 12); - data_ptr = (u8 *)skb_put(sub_skb, nSubframe_Length); - _rtw_memcpy(data_ptr, (pdata + ETH_HLEN), nSubframe_Length); + skb_reserve(sub_skb, 14); + data_ptr = (u8 *)skb_put(sub_skb, msdu_len); + _rtw_memcpy(data_ptr, msdu, msdu_len); } else #endif /* CONFIG_SKB_COPY */ { sub_skb = rtw_skb_clone(prframe->u.hdr.pkt); if (sub_skb) { - sub_skb->data = pdata + ETH_HLEN; - sub_skb->len = nSubframe_Length; - skb_set_tail_pointer(sub_skb, nSubframe_Length); + sub_skb->data = msdu; + sub_skb->len = msdu_len; + skb_set_tail_pointer(sub_skb, msdu_len); } else { RTW_INFO("%s(): rtw_skb_clone() Fail!!!\n", __FUNCTION__); return NULL; @@ -316,21 +312,23 @@ _pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 eth_type = RTW_GET_BE16(&sub_skb->data[6]); - if (sub_skb->len >= 8 && - ((_rtw_memcmp(sub_skb->data, rtw_rfc1042_header, SNAP_SIZE) && - eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || - _rtw_memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE))) { + if (sub_skb->len >= 8 + && ((_rtw_memcmp(sub_skb->data, rtw_rfc1042_header, SNAP_SIZE) + && eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) + || _rtw_memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE)) + ) { /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ skb_pull(sub_skb, SNAP_SIZE); - _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pdata+6, ETH_ALEN); - _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pdata, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), sa, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), da, ETH_ALEN); } else { - u16 len; /* Leave Ethernet header part of hdr and full payload */ + u16 len; + len = htons(sub_skb->len); _rtw_memcpy(skb_push(sub_skb, 2), &len, 2); - _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN); - _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), sa, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), da, ETH_ALEN); } return sub_skb; @@ -386,24 +384,35 @@ int rtw_recv_napi_poll(struct napi_struct *napi, int budget) work_done = napi_recv(padapter, budget); if (work_done < budget) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) - napi_complete_done(napi, work_done); -#else napi_complete(napi); -#endif if (!skb_queue_empty(&precvpriv->rx_napi_skb_queue)) napi_schedule(napi); } return work_done; } -#endif /* CONFIG_RTW_NAPI */ -#ifdef DBG_UDP_PKT_LOSE_11AC - #define PAYLOAD_LEN_LOC_OF_IP_HDR 0x10 /*ethernet payload length location of ip header (DA + SA+eth_type+(version&hdr_len)) */ -#endif +#ifdef CONFIG_RTW_NAPI_DYNAMIC +void dynamic_napi_th_chk (_adapter *adapter) +{ -void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attrib *pattrib) + if (adapter->registrypriv.en_napi) { + struct dvobj_priv *dvobj; + struct registry_priv *registry; + + dvobj = adapter_to_dvobj(adapter); + registry = &adapter->registrypriv; + if (dvobj->traffic_stat.cur_rx_tp > registry->napi_threshold) + dvobj->en_napi_dynamic = 1; + else + dvobj->en_napi_dynamic = 0; + } + +} +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ +#endif /* CONFIG_RTW_NAPI */ + +void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct recv_priv *precvpriv = &(padapter->recvpriv); @@ -415,22 +424,26 @@ void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attri /* Indicat the packets to upper layer */ if (pkt) { - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + struct ethhdr *ehdr = (struct ethhdr *)pkt->data; + + DBG_COUNTER(padapter->rx_logs.os_indicate); + + if (MLME_IS_AP(padapter)) { _pkt *pskb2 = NULL; struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; - int bmcast = IS_MCAST(pattrib->dst); + int bmcast = IS_MCAST(ehdr->h_dest); /* RTW_INFO("bmcast=%d\n", bmcast); */ - if (_rtw_memcmp(pattrib->dst, adapter_mac_addr(padapter), ETH_ALEN) == _FALSE) { - /* RTW_INFO("not ap psta=%p, addr=%pM\n", psta, pattrib->dst); */ + if (_rtw_memcmp(ehdr->h_dest, adapter_mac_addr(padapter), ETH_ALEN) == _FALSE) { + /* RTW_INFO("not ap psta=%p, addr=%pM\n", psta, ehdr->h_dest); */ if (bmcast) { psta = rtw_get_bcmc_stainfo(padapter); pskb2 = rtw_skb_clone(pkt); } else - psta = rtw_get_stainfo(pstapriv, pattrib->dst); + psta = rtw_get_stainfo(pstapriv, ehdr->h_dest); if (psta) { struct net_device *pnetdev = (struct net_device *)padapter->pnetdev; @@ -439,9 +452,9 @@ void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attri /* skb->ip_summed = CHECKSUM_NONE; */ pkt->dev = pnetdev; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) skb_set_queue_mapping(pkt, rtw_recv_select_queue(pkt)); -#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) */ + #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) */ _rtw_xmit_entry(pkt, pnetdev); @@ -460,69 +473,57 @@ void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attri } #ifdef CONFIG_BR_EXT - /* Insert NAT2.5 RX here! */ -#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) - br_port = padapter->pnetdev->br_port; -#else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ - rcu_read_lock(); - br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); - rcu_read_unlock(); -#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ - - - if (br_port && (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) { - int nat25_handle_frame(_adapter *priv, struct sk_buff *skb); - if (nat25_handle_frame(padapter, pkt) == -1) { - /* priv->ext_stats.rx_data_drops++; */ - /* DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n"); */ - /* return FAIL; */ - -#if 1 - /* bypass this frame to upper layer!! */ -#else - rtw_skb_free(sub_skb); - continue; -#endif + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) { + /* Insert NAT2.5 RX here! */ + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + br_port = padapter->pnetdev->br_port; + #else + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); + #endif + + if (br_port) { + int nat25_handle_frame(_adapter *priv, struct sk_buff *skb); + + if (nat25_handle_frame(padapter, pkt) == -1) { + /* priv->ext_stats.rx_data_drops++; */ + /* DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n"); */ + /* return FAIL; */ + + #if 1 + /* bypass this frame to upper layer!! */ + #else + rtw_skb_free(sub_skb); + continue; + #endif + } } } #endif /* CONFIG_BR_EXT */ - if (precvpriv->sink_udpport > 0) - rtw_sink_rtp_seq_dbg(padapter, pkt); -#ifdef DBG_UDP_PKT_LOSE_11AC - /* After eth_type_trans process , pkt->data pointer will move from ethrnet header to ip header , - * we have to check ethernet type , so this debug must be print before eth_type_trans - */ - if (*((unsigned short *)(pkt->data + ETH_ALEN * 2)) == htons(ETH_P_ARP)) { - /* ARP Payload length will be 42bytes or 42+18(tailer)=60bytes*/ - if (pkt->len != 42 && pkt->len != 60) - RTW_INFO("Error !!%s,ARP Payload length %u not correct\n" , __func__ , pkt->len); - } else if (*((unsigned short *)(pkt->data + ETH_ALEN * 2)) == htons(ETH_P_IP)) { - if (be16_to_cpu(*((u16 *)(pkt->data + PAYLOAD_LEN_LOC_OF_IP_HDR))) != (pkt->len) - ETH_HLEN) { - RTW_INFO("Error !!%s,Payload length not correct\n" , __func__); - RTW_INFO("%s, IP header describe Total length=%u\n" , __func__ , be16_to_cpu(*((u16 *)(pkt->data + PAYLOAD_LEN_LOC_OF_IP_HDR)))); - RTW_INFO("%s, Pkt real length=%u\n" , __func__ , (pkt->len) - ETH_HLEN); - } - } -#endif + /* After eth_type_trans process , pkt->data pointer will move from ethrnet header to ip header */ pkt->protocol = eth_type_trans(pkt, padapter->pnetdev); pkt->dev = padapter->pnetdev; - -#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX - if ((pattrib->tcpchk_valid == 1) && (pattrib->tcp_chkrpt == 1)) - pkt->ip_summed = CHECKSUM_UNNECESSARY; - else - pkt->ip_summed = CHECKSUM_NONE; -#else /* !CONFIG_TCP_CSUM_OFFLOAD_RX */ - pkt->ip_summed = CHECKSUM_NONE; -#endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */ + pkt->ip_summed = CHECKSUM_NONE; /* CONFIG_TCP_CSUM_OFFLOAD_RX */ #ifdef CONFIG_RTW_NAPI - if (pregistrypriv->en_napi) { +#ifdef CONFIG_RTW_NAPI_DYNAMIC + if (!skb_queue_empty(&precvpriv->rx_napi_skb_queue) + && !adapter_to_dvobj(padapter)->en_napi_dynamic + ) + napi_recv(padapter, RTL_NAPI_WEIGHT); +#endif + + if (pregistrypriv->en_napi + #ifdef CONFIG_RTW_NAPI_DYNAMIC + && adapter_to_dvobj(padapter)->en_napi_dynamic + #endif + ) { skb_queue_tail(&precvpriv->rx_napi_skb_queue, pkt); -#ifndef CONFIG_RTW_NAPI_V2 + #ifndef CONFIG_RTW_NAPI_V2 napi_schedule(&padapter->napi); -#endif /* !CONFIG_RTW_NAPI_V2 */ + #endif return; } #endif /* CONFIG_RTW_NAPI */ @@ -544,7 +545,7 @@ void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup struct iw_michaelmicfailure ev; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct security_priv *psecuritypriv = &padapter->securitypriv; - u32 cur_time = 0; + systime cur_time = 0; if (psecuritypriv->last_mic_err_time == 0) psecuritypriv->last_mic_err_time = rtw_get_current_time(); @@ -565,7 +566,7 @@ void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup else key_type |= NL80211_KEYTYPE_PAIRWISE; - cfg80211_michael_mic_failure(padapter->pnetdev, sta->hwaddr, key_type, -1, NULL, GFP_ATOMIC); + cfg80211_michael_mic_failure(padapter->pnetdev, sta->cmn.mac_addr, key_type, -1, NULL, GFP_ATOMIC); #endif _rtw_memset(&ev, 0x00, sizeof(ev)); @@ -575,7 +576,7 @@ void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup ev.flags |= IW_MICFAILURE_PAIRWISE; ev.src_addr.sa_family = ARPHRD_ETHER; - _rtw_memcpy(ev.src_addr.sa_data, sta->hwaddr, ETH_ALEN); + _rtw_memcpy(ev.src_addr.sa_data, sta->cmn.mac_addr, ETH_ALEN); _rtw_memset(&wrqu, 0x00, sizeof(wrqu)); wrqu.data.length = sizeof(ev); @@ -585,9 +586,9 @@ void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup #endif } +#ifdef CONFIG_HOSTAPD_MLME void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame) { -#ifdef CONFIG_HOSTAPD_MLME _pkt *skb; struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; struct net_device *pmgnt_netdev = phostapdpriv->pmgnt_netdev; @@ -622,52 +623,8 @@ void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame) rtw_netif_rx(pmgnt_netdev, skb); precv_frame->u.hdr.pkt = NULL; /* set pointer to NULL before rtw_free_recvframe() if call rtw_netif_rx() */ -#endif } - -#ifdef CONFIG_AUTO_AP_MODE -static void rtw_os_ksocket_send(_adapter *padapter, union recv_frame *precv_frame) -{ - _pkt *skb = precv_frame->u.hdr.pkt; - struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct sta_info *psta = precv_frame->u.hdr.psta; - - RTW_INFO("eth rx: got eth_type=0x%x\n", pattrib->eth_type); - - if (psta && psta->isrc && psta->pid > 0) { - u16 rx_pid; - - rx_pid = *(u16 *)(skb->data + ETH_HLEN); - - RTW_INFO("eth rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n", - rx_pid, MAC_ARG(psta->hwaddr), psta->pid); - - if (rx_pid == psta->pid) { - int i; - u16 len = *(u16 *)(skb->data + ETH_HLEN + 2); - /* u16 ctrl_type = *(u16*)(skb->data+ETH_HLEN+4); */ - - /* RTW_INFO("eth, RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type); */ - RTW_INFO("eth, RC: len=0x%x\n", len); - - for (i = 0; i < len; i++) - RTW_INFO("0x%x\n", *(skb->data + ETH_HLEN + 4 + i)); - /* RTW_INFO("0x%x\n", *(skb->data+ETH_HLEN+6+i)); */ - - RTW_INFO("eth, RC-end\n"); - -#if 0 - /* send_sz = ksocket_send(padapter->ksock_send, &padapter->kaddr_send, (skb->data+ETH_HLEN+2), len); */ - rtw_recv_ksocket_send_cmd(padapter, (skb->data + ETH_HLEN + 2), len); - - /* RTW_INFO("ksocket_send size=%d\n", send_sz); */ -#endif - } - - } - -} -#endif /* CONFIG_AUTO_AP_MODE */ +#endif /* CONFIG_HOSTAPD_MLME */ int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame) { @@ -715,136 +672,38 @@ int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame) } +inline void rtw_rframe_set_os_pkt(union recv_frame *rframe) +{ + _pkt *skb = rframe->u.hdr.pkt; + + skb->data = rframe->u.hdr.rx_data; + skb_set_tail_pointer(skb, rframe->u.hdr.len); + skb->len = rframe->u.hdr.len; +} + int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame) { struct recv_priv *precvpriv; _queue *pfree_recv_queue; - _pkt *skb; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct rx_pkt_attrib *pattrib; - - if (NULL == precv_frame) - goto _recv_indicatepkt_drop; - DBG_COUNTER(padapter->rx_logs.os_indicate); - pattrib = &precv_frame->u.hdr.attrib; precvpriv = &(padapter->recvpriv); pfree_recv_queue = &(precvpriv->free_recv_queue); -#ifdef CONFIG_DRVEXT_MODULE - if (drvext_rx_handler(padapter, precv_frame->u.hdr.rx_data, precv_frame->u.hdr.len) == _SUCCESS) + if (precv_frame->u.hdr.pkt == NULL) goto _recv_indicatepkt_drop; -#endif -#ifdef CONFIG_WAPI_SUPPORT - if (rtw_wapi_check_for_drop(padapter, precv_frame)) { - WAPI_TRACE(WAPI_ERR, "%s(): Rx Reorder Drop case!!\n", __FUNCTION__); - goto _recv_indicatepkt_drop; - } -#endif - - skb = precv_frame->u.hdr.pkt; - if (skb == NULL) { - goto _recv_indicatepkt_drop; - } - - - skb->data = precv_frame->u.hdr.rx_data; - - skb_set_tail_pointer(skb, precv_frame->u.hdr.len); - - skb->len = precv_frame->u.hdr.len; - - - if (pattrib->eth_type == 0x888e) - RTW_PRINT("recv eapol packet\n"); - -#ifdef CONFIG_AUTO_AP_MODE -#if 1 /* for testing */ -#if 1 - if (0x8899 == pattrib->eth_type) { - rtw_os_ksocket_send(padapter, precv_frame); - - /* goto _recv_indicatepkt_drop; */ - } -#else - if (0x8899 == pattrib->eth_type) { - rtw_auto_ap_mode_rx(padapter, precv_frame); - - goto _recv_indicatepkt_end; - } -#endif -#endif -#endif /* CONFIG_AUTO_AP_MODE */ - - /* TODO: move to core */ - { - _pkt *pkt = skb; - struct ethhdr *etherhdr = (struct ethhdr *)pkt->data; - struct sta_info *sta = precv_frame->u.hdr.psta; - - if (!sta) - goto bypass_session_tracker; - - if (ntohs(etherhdr->h_proto) == ETH_P_IP) { - u8 *ip = pkt->data + 14; - - if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */ - && rtw_st_ctl_chk_reg_s_proto(&sta->st_ctl, 0x06) == _TRUE - ) { - u8 *tcp = ip + GET_IPV4_IHL(ip) * 4; - - if (rtw_st_ctl_chk_reg_rule(&sta->st_ctl, padapter, IPV4_DST(ip), TCP_DST(tcp), IPV4_SRC(ip), TCP_SRC(tcp)) == _TRUE) { - if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) { - session_tracker_add_cmd(padapter, sta - , IPV4_DST(ip), TCP_DST(tcp) - , IPV4_SRC(ip), TCP_SRC(tcp)); - if (DBG_SESSION_TRACKER) - RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n" - , FUNC_ADPT_ARG(padapter) - , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)) - , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))); - } - if (GET_TCP_FIN(tcp)) { - session_tracker_del_cmd(padapter, sta - , IPV4_DST(ip), TCP_DST(tcp) - , IPV4_SRC(ip), TCP_SRC(tcp)); - if (DBG_SESSION_TRACKER) - RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n" - , FUNC_ADPT_ARG(padapter) - , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)) - , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))); - } - } - - } - } -bypass_session_tracker: - ; - } - - rtw_os_recv_indicate_pkt(padapter, skb, pattrib); + rtw_os_recv_indicate_pkt(padapter, precv_frame->u.hdr.pkt, precv_frame); _recv_indicatepkt_end: - - precv_frame->u.hdr.pkt = NULL; /* pointers to NULL before rtw_free_recvframe() */ - + precv_frame->u.hdr.pkt = NULL; rtw_free_recvframe(precv_frame, pfree_recv_queue); - - - return _SUCCESS; _recv_indicatepkt_drop: - - /* enqueue back to free_recv_queue */ - if (precv_frame) - rtw_free_recvframe(precv_frame, pfree_recv_queue); - + rtw_free_recvframe(precv_frame, pfree_recv_queue); DBG_COUNTER(padapter->rx_logs.os_indicate_err); - return _FAIL; - } void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf) diff --git a/os_dep/linux/rtw_android.c b/os_dep/linux/rtw_android.c index c8eeca3..b8b4377 100644 --- a/os_dep/linux/rtw_android.c +++ b/os_dep/linux/rtw_android.c @@ -93,6 +93,7 @@ const char *android_wifi_cmd_str[ANDROID_WIFI_CMD_MAX] = { #endif /* CONFIG_GTK_OL */ /* Private command for P2P disable*/ "P2P_DISABLE", + "SET_AEK", "DRIVER_VERSION" }; @@ -305,7 +306,10 @@ int rtw_android_cfg80211_pno_setup(struct net_device *net, memcpy(pno_ssids_local[index].SSID, ssids[index].ssid, ssids[index].ssid_len); } - +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0) + if(ssids) + rtw_mfree((u8 *)ssids, (n_ssids * sizeof(struct cfg80211_ssid))); +#endif pno_time = (interval / 1000); RTW_INFO("%s: nssids: %d, pno_time=%d\n", __func__, nssid, pno_time); @@ -561,6 +565,38 @@ int rtw_gtk_offload(struct net_device *net, u8 *cmd_ptr) } #endif /* CONFIG_GTK_OL */ +#ifdef CONFIG_RTW_MESH_AEK +static int rtw_android_set_aek(struct net_device *ndev, char *command, int total_len) +{ +#define SET_AEK_DATA_LEN (ETH_ALEN + 32) + + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + u8 *addr; + u8 *aek; + int err = 0; + + if (total_len - strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AEK]) - 1 != SET_AEK_DATA_LEN) { + err = -EINVAL; + goto exit; + } + + addr = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AEK]) + 1; + aek = addr + ETH_ALEN; + + RTW_PRINT(FUNC_NDEV_FMT" addr="MAC_FMT"\n" + , FUNC_NDEV_ARG(ndev), MAC_ARG(addr)); + if (0) + RTW_PRINT(FUNC_NDEV_FMT" aek="KEY_FMT KEY_FMT"\n" + , FUNC_NDEV_ARG(ndev), KEY_ARG(aek), KEY_ARG(aek + 16)); + + if (rtw_mesh_plink_set_aek(adapter, addr, aek) != _SUCCESS) + err = -ENOENT; + +exit: + return err; +} +#endif /* CONFIG_RTW_MESH_AEK */ + int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) { int ret = 0; @@ -853,19 +889,19 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) #if CONFIG_RTW_MACADDR_ACL case ANDROID_WIFI_CMD_HOSTAPD_SET_MACADDR_ACL: { - rtw_set_macaddr_acl(padapter, get_int_from_command(command)); + rtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, get_int_from_command(command)); break; } case ANDROID_WIFI_CMD_HOSTAPD_ACL_ADD_STA: { u8 addr[ETH_ALEN] = {0x00}; macstr2num(addr, command + strlen("HOSTAPD_ACL_ADD_STA") + 3); /* 3 is space bar + "=" + space bar these 3 chars */ - rtw_acl_add_sta(padapter, addr); + rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, addr); break; } case ANDROID_WIFI_CMD_HOSTAPD_ACL_REMOVE_STA: { u8 addr[ETH_ALEN] = {0x00}; macstr2num(addr, command + strlen("HOSTAPD_ACL_REMOVE_STA") + 3); /* 3 is space bar + "=" + space bar these 3 chars */ - rtw_acl_remove_sta(padapter, addr); + rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, addr); break; } #endif /* CONFIG_RTW_MACADDR_ACL */ @@ -884,6 +920,13 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) #endif /* CONFIG_P2P */ break; } + +#ifdef CONFIG_RTW_MESH_AEK + case ANDROID_WIFI_CMD_SET_AEK: + bytes_written = rtw_android_set_aek(net, command, priv_cmd.total_len); + break; +#endif + case ANDROID_WIFI_CMD_DRIVERVERSION: { bytes_written = strlen(DRIVERVERSION); snprintf(command, bytes_written + 1, DRIVERVERSION); diff --git a/os_dep/linux/rtw_cfgvendor.c b/os_dep/linux/rtw_cfgvendor.c index 79e3f98..0f0f24f 100644 --- a/os_dep/linux/rtw_cfgvendor.c +++ b/os_dep/linux/rtw_cfgvendor.c @@ -209,22 +209,34 @@ static int rtw_cfgvendor_send_cmd_reply(struct wiphy *wiphy, return rtw_cfg80211_vendor_cmd_reply(skb); } -#define WIFI_FEATURE_INFRA 0x0001 /* Basic infrastructure mode */ -#define WIFI_FEATURE_INFRA_5G 0x0002 /* Support for 5 GHz Band */ -#define WIFI_FEATURE_HOTSPOT 0x0004 /* Support for GAS/ANQP */ -#define WIFI_FEATURE_P2P 0x0008 /* Wifi-Direct */ -#define WIFI_FEATURE_SOFT_AP 0x0010 /* Soft AP */ -#define WIFI_FEATURE_GSCAN 0x0020 /* Google-Scan APIs */ -#define WIFI_FEATURE_NAN 0x0040 /* Neighbor Awareness Networking */ -#define WIFI_FEATURE_D2D_RTT 0x0080 /* Device-to-device RTT */ -#define WIFI_FEATURE_D2AP_RTT 0x0100 /* Device-to-AP RTT */ -#define WIFI_FEATURE_BATCH_SCAN 0x0200 /* Batched Scan (legacy) */ -#define WIFI_FEATURE_PNO 0x0400 /* Preferred network offload */ -#define WIFI_FEATURE_ADDITIONAL_STA 0x0800 /* Support for two STAs */ -#define WIFI_FEATURE_TDLS 0x1000 /* Tunnel directed link setup */ -#define WIFI_FEATURE_TDLS_OFFCHANNEL 0x2000 /* Support for TDLS off channel */ -#define WIFI_FEATURE_EPR 0x4000 /* Enhanced power reporting */ -#define WIFI_FEATURE_AP_STA 0x8000 /* Support for AP STA Concurrency */ +/* Feature enums */ +#define WIFI_FEATURE_INFRA 0x0001 // Basic infrastructure mode +#define WIFI_FEATURE_INFRA_5G 0x0002 // Support for 5 GHz Band +#define WIFI_FEATURE_HOTSPOT 0x0004 // Support for GAS/ANQP +#define WIFI_FEATURE_P2P 0x0008 // Wifi-Direct +#define WIFI_FEATURE_SOFT_AP 0x0010 // Soft AP +#define WIFI_FEATURE_GSCAN 0x0020 // Google-Scan APIs +#define WIFI_FEATURE_NAN 0x0040 // Neighbor Awareness Networking +#define WIFI_FEATURE_D2D_RTT 0x0080 // Device-to-device RTT +#define WIFI_FEATURE_D2AP_RTT 0x0100 // Device-to-AP RTT +#define WIFI_FEATURE_BATCH_SCAN 0x0200 // Batched Scan (legacy) +#define WIFI_FEATURE_PNO 0x0400 // Preferred network offload +#define WIFI_FEATURE_ADDITIONAL_STA 0x0800 // Support for two STAs +#define WIFI_FEATURE_TDLS 0x1000 // Tunnel directed link setup +#define WIFI_FEATURE_TDLS_OFFCHANNEL 0x2000 // Support for TDLS off channel +#define WIFI_FEATURE_EPR 0x4000 // Enhanced power reporting +#define WIFI_FEATURE_AP_STA 0x8000 // Support for AP STA Concurrency +#define WIFI_FEATURE_LINK_LAYER_STATS 0x10000 // Link layer stats collection +#define WIFI_FEATURE_LOGGER 0x20000 // WiFi Logger +#define WIFI_FEATURE_HAL_EPNO 0x40000 // WiFi PNO enhanced +#define WIFI_FEATURE_RSSI_MONITOR 0x80000 // RSSI Monitor +#define WIFI_FEATURE_MKEEP_ALIVE 0x100000 // WiFi mkeep_alive +#define WIFI_FEATURE_CONFIG_NDO 0x200000 // ND offload configure +#define WIFI_FEATURE_TX_TRANSMIT_POWER 0x400000 // Capture Tx transmit power levels +#define WIFI_FEATURE_CONTROL_ROAMING 0x800000 // Enable/Disable firmware roaming +#define WIFI_FEATURE_IE_WHITELIST 0x1000000 // Support Probe IE white listing +#define WIFI_FEATURE_SCAN_RAND 0x2000000 // Support MAC & Probe Sequence Number randomization +// Add more features here #define MAX_FEATURE_SET_CONCURRRENT_GROUPS 3 @@ -239,14 +251,19 @@ int rtw_dev_get_feature_set(struct net_device *dev) feature_set |= WIFI_FEATURE_INFRA; - if (IS_8814A_SERIES(*hal_ver) || IS_8812_SERIES(*hal_ver) || - IS_8821_SERIES(*hal_ver)) +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (is_supported_5g(adapter_to_regsty(adapter)->wireless_mode) + && hal_chk_band_cap(adapter, BAND_CAP_5G)) /* v5.3 has no rtw_init_wireless_mode(), need checking hal spec here */ feature_set |= WIFI_FEATURE_INFRA_5G; +#endif feature_set |= WIFI_FEATURE_P2P; feature_set |= WIFI_FEATURE_SOFT_AP; feature_set |= WIFI_FEATURE_ADDITIONAL_STA; +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + feature_set |= WIFI_FEATURE_LINK_LAYER_STATS; +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ return feature_set; } @@ -362,8 +379,8 @@ static int rtw_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy, } #if defined(GSCAN_SUPPORT) && 0 -int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy, - struct net_device *dev, void *data, int len, wl_vendor_event_t event) +int rtw_cfgvendor_send_hotlist_event(struct wiphy *wiphy, + struct net_device *dev, void *data, int len, rtw_vendor_event_t event) { u16 kflags; const void *ptr; @@ -413,7 +430,7 @@ int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy, } -static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy, +static int rtw_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -440,7 +457,7 @@ static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy, return err; } -static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy, +static int rtw_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0, type, band; @@ -487,7 +504,7 @@ static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy, return err; } -static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, +static int rtw_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -571,7 +588,7 @@ static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, return rtw_cfg80211_vendor_cmd_reply(skb); } -static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy, +static int rtw_cfgvendor_initiate_gscan(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -601,7 +618,7 @@ static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy, } -static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy, +static int rtw_cfgvendor_enable_full_scan_result(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -625,7 +642,7 @@ static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy, return err; } -static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy, +static int rtw_cfgvendor_set_scan_cfg(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -717,7 +734,7 @@ static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy, } -static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy, +static int rtw_cfgvendor_hotlist_cfg(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -783,7 +800,7 @@ static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy, kfree(hotlist_params); return err; } -static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy, +static int rtw_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0, tmp, type; @@ -820,7 +837,7 @@ static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy, return err; } -static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy, +static int rtw_cfgvendor_significant_change_cfg(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -894,7 +911,7 @@ static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy, #endif /* GSCAN_SUPPORT */ #if defined(RTT_SUPPORT) && 0 -void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data) +void rtw_cfgvendor_rtt_evt(void *ctx, void *rtt_data) { struct wireless_dev *wdev = (struct wireless_dev *)ctx; struct wiphy *wiphy; @@ -958,7 +975,7 @@ void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data) return; } -static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev *wdev, +static int rtw_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0, rem, rem1, rem2, type; @@ -1045,7 +1062,7 @@ static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev return err; } -static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_dev *wdev, +static int rtw_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0, rem, type, target_cnt = 0; @@ -1085,7 +1102,7 @@ static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_d kfree(mac_list); return err; } -static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_dev *wdev, +static int rtw_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -1107,57 +1124,174 @@ static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_ } #endif /* RTT_SUPPORT */ -static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) + +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS +enum { + LSTATS_SUBCMD_GET_INFO = ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START, + LSTATS_SUBCMD_SET_INFO, + LSTATS_SUBCMD_CLEAR_INFO, +}; +static void LinkLayerStats(_adapter *padapter) { - int err = 0; - u8 resp[1] = {'\0'}; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct recv_priv *precvpriv = &(padapter->recvpriv); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + u32 ps_time, trx_total_time; + u64 tx_bytes, rx_bytes, trx_total_bytes = 0; + u64 tmp = 0; + + RTW_DBG("%s adapter type : %u\n", __func__, padapter->adapter_type); + + tx_bytes = 0; + rx_bytes = 0; + ps_time = 0; + trx_total_time = 0; + + if ( padapter->netif_up == _TRUE ) { + + pwrpriv->on_time = rtw_get_passing_time_ms(pwrpriv->radio_on_start_time); + + if (rtw_mi_check_fwstate(padapter, _FW_LINKED)) { + if ( pwrpriv->bpower_saving == _TRUE ) { + pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time); + pwrpriv->pwr_saving_start_time = rtw_get_current_time(); + } + } else { +#ifdef CONFIG_IPS + if ( pwrpriv->bpower_saving == _TRUE ) { + pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time); + pwrpriv->pwr_saving_start_time = rtw_get_current_time(); + } +#else + pwrpriv->pwr_saving_time = pwrpriv->on_time; +#endif + } - RTW_PRINT(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char *)data); - err = rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), resp, 1); - if (unlikely(err)) - RTW_ERR(FUNC_NDEV_FMT"Vendor Command reply failed ret:%d\n" - , FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err); + ps_time = pwrpriv->pwr_saving_time; - return err; -#if 0 - struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); - int err = 0; - int data_len = 0; + /* Deviation caused by caculation start time */ + if ( ps_time > pwrpriv->on_time ) + ps_time = pwrpriv->on_time; + + tx_bytes = pdvobjpriv->traffic_stat.last_tx_bytes; + rx_bytes = pdvobjpriv->traffic_stat.last_rx_bytes; + trx_total_bytes = tx_bytes + rx_bytes; - bzero(cfg->ioctl_buf, WLC_IOCTL_MAXLEN); + trx_total_time = pwrpriv->on_time - ps_time; + + if ( trx_total_bytes == 0) { + pwrpriv->tx_time = 0; + pwrpriv->rx_time = 0; + } else { + + /* tx_time = (trx_total_time * tx_total_bytes) / trx_total_bytes; */ + /* rx_time = (trx_total_time * rx_total_bytes) / trx_total_bytes; */ + + tmp = (tx_bytes * trx_total_time); + tmp = rtw_division64(tmp, trx_total_bytes); + pwrpriv->tx_time = tmp; + + tmp = (rx_bytes * trx_total_time); + tmp = rtw_division64(tmp, trx_total_bytes); + pwrpriv->rx_time = tmp; - if (strncmp((char *)data, BRCM_VENDOR_SCMD_CAPA, strlen(BRCM_VENDOR_SCMD_CAPA)) == 0) { - err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "cap", NULL, 0, - cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync); - if (unlikely(err)) { - WL_ERR(("error (%d)\n", err)); - return err; } - data_len = strlen(cfg->ioctl_buf); - cfg->ioctl_buf[data_len] = '\0'; + + } + else { + pwrpriv->on_time = 0; + pwrpriv->tx_time = 0; + pwrpriv->rx_time = 0; } - err = rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg), - cfg->ioctl_buf, data_len + 1); - if (unlikely(err)) - WL_ERR(("Vendor Command reply failed ret:%d\n", err)); - else - WL_INFORM(("Vendor Command reply sent successfully!\n")); +#ifdef CONFIG_RTW_WIFI_HAL_DEBUG + RTW_INFO("- tx_bytes : %llu rx_bytes : %llu total bytes : %llu\n", tx_bytes, rx_bytes, trx_total_bytes); + RTW_INFO("- netif_up=%s, on_time : %u ms\n", padapter->netif_up ? "1":"0", pwrpriv->on_time); + RTW_INFO("- pwr_saving_time : %u (%u) ms\n", pwrpriv->pwr_saving_time, ps_time); + RTW_INFO("- trx_total_time : %u ms\n", trx_total_time); + RTW_INFO("- tx_time : %u ms\n", pwrpriv->tx_time); + RTW_INFO("- rx_time : %u ms\n", pwrpriv->rx_time); +#endif /* CONFIG_RTW_WIFI_HAL_DEBUG */ + +} + +#define DUMMY_TIME_STATICS 99 +static int rtw_cfgvendor_lstats_get_info(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int err = 0; + _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy)); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + wifi_radio_stat *radio; + wifi_iface_stat *iface; + char *output; + + output = rtw_malloc(sizeof(wifi_radio_stat) + sizeof(wifi_iface_stat)+1); + if (output == NULL) { + RTW_DBG("Allocate lstats info buffer fail!\n"); +} + radio = (wifi_radio_stat *)output; + + radio->num_channels = 0; + radio->radio = 1; + + /* to get on_time, tx_time, rx_time */ + LinkLayerStats(padapter); + + radio->on_time = pwrpriv->on_time; + radio->tx_time = pwrpriv->tx_time; + radio->rx_time = pwrpriv->rx_time; + + radio->num_tx_levels = 1; + radio->tx_time_per_levels = NULL; + radio->tx_time_per_levels = (u32*)(output+sizeof(wifi_radio_stat) + sizeof(wifi_iface_stat)); + *(radio->tx_time_per_levels) = DUMMY_TIME_STATICS; + + radio->on_time_scan = 0; + radio->on_time_nbd = 0; + radio->on_time_gscan = 0; + radio->on_time_pno_scan = 0; + radio->on_time_hs20 = 0; + #ifdef CONFIG_RTW_WIFI_HAL_DEBUG + RTW_INFO("==== %s ====\n", __func__); + RTW_INFO("radio->radio : %d\n", (radio->radio)); + RTW_INFO("pwrpriv->on_time : %u ms\n", (pwrpriv->on_time)); + RTW_INFO("pwrpriv->tx_time : %u ms\n", (pwrpriv->tx_time)); + RTW_INFO("pwrpriv->rx_time : %u ms\n", (pwrpriv->rx_time)); + RTW_INFO("radio->on_time : %u ms\n", (radio->on_time)); + RTW_INFO("radio->tx_time : %u ms\n", (radio->tx_time)); + RTW_INFO("radio->rx_time : %u ms\n", (radio->rx_time)); + RTW_INFO("radio->tx_time_per_levels value : %u ms\n", *(radio->tx_time_per_levels)); + #endif /* CONFIG_RTW_WIFI_HAL_DEBUG */ + + RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data); + err = rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), + output, sizeof(wifi_iface_stat) + sizeof(wifi_radio_stat)+1); + if (unlikely(err)) + RTW_ERR(FUNC_NDEV_FMT"Vendor Command reply failed ret:%d \n" + , FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err); + rtw_mfree(output, sizeof(wifi_iface_stat) + sizeof(wifi_radio_stat)+1); return err; -#endif } +static int rtw_cfgvendor_lstats_set_info(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int err = 0; + RTW_INFO("%s\n", __func__); + return err; +} +static int rtw_cfgvendor_lstats_clear_info(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int err = 0; + RTW_INFO("%s\n", __func__); + return err; +} +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { - { - { - .vendor_id = OUI_BRCM, - .subcmd = BRCM_VENDOR_SCMD_PRIV_STR - }, - .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_priv_string_handler - }, #if defined(GSCAN_SUPPORT) && 0 { { @@ -1165,7 +1299,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_gscan_get_capabilities + .doit = rtw_cfgvendor_gscan_get_capabilities }, { { @@ -1173,7 +1307,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_SET_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_set_scan_cfg + .doit = rtw_cfgvendor_set_scan_cfg }, { { @@ -1181,7 +1315,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_set_batch_scan_cfg + .doit = rtw_cfgvendor_set_batch_scan_cfg }, { { @@ -1189,7 +1323,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_initiate_gscan + .doit = rtw_cfgvendor_initiate_gscan }, { { @@ -1197,7 +1331,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_enable_full_scan_result + .doit = rtw_cfgvendor_enable_full_scan_result }, { { @@ -1205,7 +1339,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_SET_HOTLIST }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_hotlist_cfg + .doit = rtw_cfgvendor_hotlist_cfg }, { { @@ -1213,7 +1347,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_significant_change_cfg + .doit = rtw_cfgvendor_significant_change_cfg }, { { @@ -1221,7 +1355,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_gscan_get_batch_results + .doit = rtw_cfgvendor_gscan_get_batch_results }, { { @@ -1229,7 +1363,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_gscan_get_channel_list + .doit = rtw_cfgvendor_gscan_get_channel_list }, #endif /* GSCAN_SUPPORT */ #if defined(RTT_SUPPORT) && 0 @@ -1239,7 +1373,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = RTT_SUBCMD_SET_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_rtt_set_config + .doit = rtw_cfgvendor_rtt_set_config }, { { @@ -1247,7 +1381,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = RTT_SUBCMD_CANCEL_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_rtt_cancel_config + .doit = rtw_cfgvendor_rtt_cancel_config }, { { @@ -1255,13 +1389,39 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = RTT_SUBCMD_GETCAPABILITY }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_rtt_get_capability + .doit = rtw_cfgvendor_rtt_get_capability }, #endif /* RTT_SUPPORT */ +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LSTATS_SUBCMD_GET_INFO + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_lstats_get_info + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LSTATS_SUBCMD_SET_INFO + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_lstats_set_info + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LSTATS_SUBCMD_CLEAR_INFO + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_lstats_clear_info + }, +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ { { .vendor_id = OUI_GOOGLE, - .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET + .subcmd = WIFI_SUBCMD_GET_FEATURE_SET }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, .doit = rtw_cfgvendor_get_feature_set @@ -1269,7 +1429,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { { { .vendor_id = OUI_GOOGLE, - .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX + .subcmd = WIFI_SUBCMD_GET_FEATURE_SET_MATRIX }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, .doit = rtw_cfgvendor_get_feature_set_matrix @@ -1277,20 +1437,18 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { }; static const struct nl80211_vendor_cmd_info rtw_vendor_events[] = { - { OUI_BRCM, BRCM_VENDOR_EVENT_UNSPEC }, - { OUI_BRCM, BRCM_VENDOR_EVENT_PRIV_STR }, #if defined(GSCAN_SUPPORT) && 0 - { OUI_GOOGLE, GOOGLE_GSCAN_SIGNIFICANT_EVENT }, - { OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT }, - { OUI_GOOGLE, GOOGLE_GSCAN_BATCH_SCAN_EVENT }, - { OUI_GOOGLE, GOOGLE_SCAN_FULL_RESULTS_EVENT }, + { OUI_GOOGLE, GSCAN_EVENT_SIGNIFICANT_CHANGE_RESULTS }, + { OUI_GOOGLE, GSCAN_EVENT_HOTLIST_RESULTS_FOUND }, + { OUI_GOOGLE, GSCAN_EVENT_SCAN_RESULTS_AVAILABLE }, + { OUI_GOOGLE, GSCAN_EVENT_FULL_SCAN_RESULTS }, #endif /* GSCAN_SUPPORT */ #if defined(RTT_SUPPORT) && 0 - { OUI_GOOGLE, GOOGLE_RTT_COMPLETE_EVENT }, + { OUI_GOOGLE, RTT_EVENT_COMPLETE }, #endif /* RTT_SUPPORT */ #if defined(GSCAN_SUPPORT) && 0 - { OUI_GOOGLE, GOOGLE_SCAN_COMPLETE_EVENT }, - { OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT } + { OUI_GOOGLE, GSCAN_EVENT_COMPLETE_SCAN }, + { OUI_GOOGLE, GSCAN_EVENT_HOTLIST_RESULTS_LOST } #endif /* GSCAN_SUPPORT */ }; diff --git a/os_dep/linux/rtw_cfgvendor.h b/os_dep/linux/rtw_cfgvendor.h index 9f36e9f..d5157b3 100644 --- a/os_dep/linux/rtw_cfgvendor.h +++ b/os_dep/linux/rtw_cfgvendor.h @@ -16,9 +16,7 @@ #ifndef _RTW_CFGVENDOR_H_ #define _RTW_CFGVENDOR_H_ -#define OUI_BRCM 0x001018 #define OUI_GOOGLE 0x001A11 -#define BRCM_VENDOR_SUBCMD_PRIV_STR 1 #define ATTRIBUTE_U32_LEN (NLA_HDRLEN + 4) #define VENDOR_ID_OVERHEAD ATTRIBUTE_U32_LEN #define VENDOR_SUBCMD_OVERHEAD ATTRIBUTE_U32_LEN @@ -39,54 +37,91 @@ VENDOR_SUBCMD_OVERHEAD + \ VENDOR_DATA_OVERHEAD) typedef enum { - /* don't use 0 as a valid subcommand */ - VENDOR_NL80211_SUBCMD_UNSPECIFIED, + /* don't use 0 as a valid subcommand */ + VENDOR_NL80211_SUBCMD_UNSPECIFIED, - /* define all vendor startup commands between 0x0 and 0x0FFF */ - VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001, - VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF, + /* define all vendor startup commands between 0x0 and 0x0FFF */ + VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001, + VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF, - /* define all GScan related commands between 0x1000 and 0x10FF */ - ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000, - ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF, + /* define all GScan related commands between 0x1000 and 0x10FF */ + ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000, + ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF, - /* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */ - ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100, - ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF, + /* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */ + ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100, + ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF, - /* define all RTT related commands between 0x1100 and 0x11FF */ - ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100, - ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF, + /* define all RTT related commands between 0x1100 and 0x11FF */ + ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100, + ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF, - ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200, - ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF, + ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200, + ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF, - ANDROID_NL80211_SUBCMD_TDLS_RANGE_START = 0x1300, - ANDROID_NL80211_SUBCMD_TDLS_RANGE_END = 0x13FF, - /* This is reserved for future usage */ + /* define all Logger related commands between 0x1400 and 0x14FF */ + ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START = 0x1400, + ANDROID_NL80211_SUBCMD_DEBUG_RANGE_END = 0x14FF, + + /* define all wifi offload related commands between 0x1600 and 0x16FF */ + ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START = 0x1600, + ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_END = 0x16FF, + + /* define all NAN related commands between 0x1700 and 0x17FF */ + ANDROID_NL80211_SUBCMD_NAN_RANGE_START = 0x1700, + ANDROID_NL80211_SUBCMD_NAN_RANGE_END = 0x17FF, + + /* define all Android Packet Filter related commands between 0x1800 and 0x18FF */ + ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START = 0x1800, + ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_END = 0x18FF, + + /* This is reserved for future usage */ } ANDROID_VENDOR_SUB_COMMAND; -enum wl_vendor_subcmd { - BRCM_VENDOR_SCMD_UNSPEC, - BRCM_VENDOR_SCMD_PRIV_STR, - GSCAN_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START, - GSCAN_SUBCMD_SET_CONFIG, - GSCAN_SUBCMD_SET_SCAN_CONFIG, - GSCAN_SUBCMD_ENABLE_GSCAN, - GSCAN_SUBCMD_GET_SCAN_RESULTS, - GSCAN_SUBCMD_SCAN_RESULTS, - GSCAN_SUBCMD_SET_HOTLIST, - GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG, - GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS, - GSCAN_SUBCMD_GET_CHANNEL_LIST, - ANDR_WIFI_SUBCMD_GET_FEATURE_SET, - ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX, +enum rtw_vendor_subcmd { + GSCAN_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START, + + GSCAN_SUBCMD_SET_CONFIG, /* 0x1001 */ + + GSCAN_SUBCMD_SET_SCAN_CONFIG, /* 0x1002 */ + GSCAN_SUBCMD_ENABLE_GSCAN, /* 0x1003 */ + GSCAN_SUBCMD_GET_SCAN_RESULTS, /* 0x1004 */ + GSCAN_SUBCMD_SCAN_RESULTS, /* 0x1005 */ + + GSCAN_SUBCMD_SET_HOTLIST, /* 0x1006 */ + + GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG, /* 0x1007 */ + GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS, /* 0x1008 */ + GSCAN_SUBCMD_GET_CHANNEL_LIST, /* 0x1009 */ + + WIFI_SUBCMD_GET_FEATURE_SET, /* 0x100A */ + WIFI_SUBCMD_GET_FEATURE_SET_MATRIX, /* 0x100B */ + WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI, /* 0x100C */ + WIFI_SUBCMD_NODFS_SET, /* 0x100D */ + WIFI_SUBCMD_SET_COUNTRY_CODE, /* 0x100E */ + /* Add more sub commands here */ + GSCAN_SUBCMD_SET_EPNO_SSID, /* 0x100F */ + + WIFI_SUBCMD_SET_SSID_WHITE_LIST, /* 0x1010 */ + WIFI_SUBCMD_SET_ROAM_PARAMS, /* 0x1011 */ + WIFI_SUBCMD_ENABLE_LAZY_ROAM, /* 0x1012 */ + WIFI_SUBCMD_SET_BSSID_PREF, /* 0x1013 */ + WIFI_SUBCMD_SET_BSSID_BLACKLIST, /* 0x1014 */ + + GSCAN_SUBCMD_ANQPO_CONFIG, /* 0x1015 */ + WIFI_SUBCMD_SET_RSSI_MONITOR, /* 0x1016 */ + WIFI_SUBCMD_CONFIG_ND_OFFLOAD, /* 0x1017 */ + /* Add more sub commands here */ + + GSCAN_SUBCMD_MAX, + RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START, RTT_SUBCMD_CANCEL_CONFIG, RTT_SUBCMD_GETCAPABILITY, - /* Add more sub commands here */ - VENDOR_SUBCMD_MAX + + APF_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START, + APF_SUBCMD_SET_FILTER, }; enum gscan_attributes { @@ -178,24 +213,29 @@ enum rtt_attributes { RTT_ATTRIBUTE_TARGET_NUM_RETRY }; -typedef enum wl_vendor_event { - BRCM_VENDOR_EVENT_UNSPEC, - BRCM_VENDOR_EVENT_PRIV_STR, - GOOGLE_GSCAN_SIGNIFICANT_EVENT, - GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT, - GOOGLE_GSCAN_BATCH_SCAN_EVENT, - GOOGLE_SCAN_FULL_RESULTS_EVENT, - GOOGLE_RTT_COMPLETE_EVENT, - GOOGLE_SCAN_COMPLETE_EVENT, - GOOGLE_GSCAN_GEOFENCE_LOST_EVENT -} wl_vendor_event_t; +typedef enum rtw_vendor_event { + RTK_RESERVED1, + RTK_RESERVED2, + GSCAN_EVENT_SIGNIFICANT_CHANGE_RESULTS , + GSCAN_EVENT_HOTLIST_RESULTS_FOUND, + GSCAN_EVENT_SCAN_RESULTS_AVAILABLE, + GSCAN_EVENT_FULL_SCAN_RESULTS, + RTT_EVENT_COMPLETE, + GSCAN_EVENT_COMPLETE_SCAN, + GSCAN_EVENT_HOTLIST_RESULTS_LOST, + GSCAN_EVENT_EPNO_EVENT, + GOOGLE_DEBUG_RING_EVENT, + GOOGLE_DEBUG_MEM_DUMP_EVENT, + GSCAN_EVENT_ANQPO_HOTSPOT_MATCH, + GOOGLE_RSSI_MONITOR_EVENT +} rtw_vendor_event_t; enum andr_wifi_feature_set_attr { ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, ANDR_WIFI_ATTRIBUTE_FEATURE_SET }; -typedef enum wl_vendor_gscan_attribute { +typedef enum rtw_vendor_gscan_attribute { ATTR_START_GSCAN, ATTR_STOP_GSCAN, ATTR_SET_SCAN_BATCH_CFG_ID, /* set batch scan params */ @@ -205,7 +245,7 @@ typedef enum wl_vendor_gscan_attribute { ATTR_GET_GSCAN_CAPABILITIES_ID, /* Add more sub commands here */ ATTR_GSCAN_MAX -} wl_vendor_gscan_attribute_t; +} rtw_vendor_gscan_attribute_t; typedef enum gscan_batch_attribute { ATTR_GSCAN_BATCH_BESTN, @@ -222,9 +262,288 @@ typedef enum gscan_complete_event { WIFI_SCAN_BUFFER_FULL, WIFI_SCAN_COMPLETE } gscan_complete_event_t; +/* wifi_hal.h */ +/* WiFi Common definitions */ +typedef unsigned char byte; +typedef int wifi_request_id; +typedef int wifi_channel; // indicates channel frequency in MHz +typedef int wifi_rssi; +typedef byte mac_addr[6]; +typedef byte oui[3]; +typedef int64_t wifi_timestamp; // In microseconds (us) +typedef int64_t wifi_timespan; // In picoseconds (ps) + +struct wifi_info; +struct wifi_interface_info; +typedef struct wifi_info *wifi_handle; +typedef struct wifi_interface_info *wifi_interface_handle; + +/* channel operating width */ +typedef enum { + WIFI_CHAN_WIDTH_20 = 0, + WIFI_CHAN_WIDTH_40 = 1, + WIFI_CHAN_WIDTH_80 = 2, + WIFI_CHAN_WIDTH_160 = 3, + WIFI_CHAN_WIDTH_80P80 = 4, + WIFI_CHAN_WIDTH_5 = 5, + WIFI_CHAN_WIDTH_10 = 6, + WIFI_CHAN_WIDTH_INVALID = -1 +} wifi_channel_width; + +typedef int wifi_radio; + +typedef struct { + wifi_channel_width width; + int center_frequency0; + int center_frequency1; + int primary_frequency; +} wifi_channel_spec; + +typedef enum { + WIFI_SUCCESS = 0, + WIFI_ERROR_NONE = 0, + WIFI_ERROR_UNKNOWN = -1, + WIFI_ERROR_UNINITIALIZED = -2, + WIFI_ERROR_NOT_SUPPORTED = -3, + WIFI_ERROR_NOT_AVAILABLE = -4, // Not available right now, but try later + WIFI_ERROR_INVALID_ARGS = -5, + WIFI_ERROR_INVALID_REQUEST_ID = -6, + WIFI_ERROR_TIMED_OUT = -7, + WIFI_ERROR_TOO_MANY_REQUESTS = -8, // Too many instances of this request + WIFI_ERROR_OUT_OF_MEMORY = -9, + WIFI_ERROR_BUSY = -10, +} wifi_error; + +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS +#define STATS_MAJOR_VERSION 1 +#define STATS_MINOR_VERSION 0 +#define STATS_MICRO_VERSION 0 + +typedef enum { + WIFI_DISCONNECTED = 0, + WIFI_AUTHENTICATING = 1, + WIFI_ASSOCIATING = 2, + WIFI_ASSOCIATED = 3, + WIFI_EAPOL_STARTED = 4, // if done by firmware/driver + WIFI_EAPOL_COMPLETED = 5, // if done by firmware/driver +} wifi_connection_state; + +typedef enum { + WIFI_ROAMING_IDLE = 0, + WIFI_ROAMING_ACTIVE = 1, +} wifi_roam_state; + +typedef enum { + WIFI_INTERFACE_STA = 0, + WIFI_INTERFACE_SOFTAP = 1, + WIFI_INTERFACE_IBSS = 2, + WIFI_INTERFACE_P2P_CLIENT = 3, + WIFI_INTERFACE_P2P_GO = 4, + WIFI_INTERFACE_NAN = 5, + WIFI_INTERFACE_MESH = 6, + WIFI_INTERFACE_UNKNOWN = -1 + } wifi_interface_mode; + +#define WIFI_CAPABILITY_QOS 0x00000001 // set for QOS association +#define WIFI_CAPABILITY_PROTECTED 0x00000002 // set for protected association (802.11 beacon frame control protected bit set) +#define WIFI_CAPABILITY_INTERWORKING 0x00000004 // set if 802.11 Extended Capabilities element interworking bit is set +#define WIFI_CAPABILITY_HS20 0x00000008 // set for HS20 association +#define WIFI_CAPABILITY_SSID_UTF8 0x00000010 // set is 802.11 Extended Capabilities element UTF-8 SSID bit is set +#define WIFI_CAPABILITY_COUNTRY 0x00000020 // set is 802.11 Country Element is present + +typedef struct { + wifi_interface_mode mode; // interface mode + u8 mac_addr[6]; // interface mac address (self) + wifi_connection_state state; // connection state (valid for STA, CLI only) + wifi_roam_state roaming; // roaming state + u32 capabilities; // WIFI_CAPABILITY_XXX (self) + u8 ssid[33]; // null terminated SSID + u8 bssid[6]; // bssid + u8 ap_country_str[3]; // country string advertised by AP + u8 country_str[3]; // country string for this association +} wifi_interface_link_layer_info; + +/* channel information */ +typedef struct { + wifi_channel_width width; // channel width (20, 40, 80, 80+80, 160) + wifi_channel center_freq; // primary 20 MHz channel + wifi_channel center_freq0; // center frequency (MHz) first segment + wifi_channel center_freq1; // center frequency (MHz) second segment +} wifi_channel_info; + +/* wifi rate */ +typedef struct { + u32 preamble :3; // 0: OFDM, 1:CCK, 2:HT 3:VHT 4..7 reserved + u32 nss :2; // 0:1x1, 1:2x2, 3:3x3, 4:4x4 + u32 bw :3; // 0:20MHz, 1:40Mhz, 2:80Mhz, 3:160Mhz + u32 rateMcsIdx :8; // OFDM/CCK rate code would be as per ieee std in the units of 0.5mbps + // HT/VHT it would be mcs index + u32 reserved :16; // reserved + u32 bitrate; // units of 100 Kbps +} wifi_rate; + +/* channel statistics */ +typedef struct { + wifi_channel_info channel; // channel + u32 on_time; // msecs the radio is awake (32 bits number accruing over time) + u32 cca_busy_time; // msecs the CCA register is busy (32 bits number accruing over time) +} wifi_channel_stat; + +// Max number of tx power levels. The actual number vary per device and is specified by |num_tx_levels| +#define RADIO_STAT_MAX_TX_LEVELS 256 + +/* radio statistics */ +typedef struct { + wifi_radio radio; // wifi radio (if multiple radio supported) + u32 on_time; // msecs the radio is awake (32 bits number accruing over time) + u32 tx_time; // msecs the radio is transmitting (32 bits number accruing over time) + u32 num_tx_levels; // number of radio transmit power levels + u32* tx_time_per_levels; // pointer to an array of radio transmit per power levels in + // msecs accured over time + u32 rx_time; // msecs the radio is in active receive (32 bits number accruing over time) + u32 on_time_scan; // msecs the radio is awake due to all scan (32 bits number accruing over time) + u32 on_time_nbd; // msecs the radio is awake due to NAN (32 bits number accruing over time) + u32 on_time_gscan; // msecs the radio is awake due to G?scan (32 bits number accruing over time) + u32 on_time_roam_scan; // msecs the radio is awake due to roam?scan (32 bits number accruing over time) + u32 on_time_pno_scan; // msecs the radio is awake due to PNO scan (32 bits number accruing over time) + u32 on_time_hs20; // msecs the radio is awake due to HS2.0 scans and GAS exchange (32 bits number accruing over time) + u32 num_channels; // number of channels + wifi_channel_stat channels[]; // channel statistics +} wifi_radio_stat; + +/** + * Packet statistics reporting by firmware is performed on MPDU basi (i.e. counters increase by 1 for each MPDU) + * As well, "data packet" in associated comments, shall be interpreted as 802.11 data packet, + * that is, 802.11 frame control subtype == 2 and excluding management and control frames. + * + * As an example, in the case of transmission of an MSDU fragmented in 16 MPDUs which are transmitted + * OTA in a 16 units long a-mpdu, for which a block ack is received with 5 bits set: + * tx_mpdu : shall increase by 5 + * retries : shall increase by 16 + * tx_ampdu : shall increase by 1 + * data packet counters shall not increase regardless of the number of BAR potentially sent by device for this a-mpdu + * data packet counters shall not increase regardless of the number of BA received by device for this a-mpdu + * + * For each subsequent retransmission of the 11 remaining non ACK'ed mpdus + * (regardless of the fact that they are transmitted in a-mpdu or not) + * retries : shall increase by 1 + * + * If no subsequent BA or ACK are received from AP, until packet lifetime expires for those 11 packet that were not ACK'ed + * mpdu_lost : shall increase by 11 + */ + +/* per rate statistics */ +typedef struct { + wifi_rate rate; // rate information + u32 tx_mpdu; // number of successfully transmitted data pkts (ACK rcvd) + u32 rx_mpdu; // number of received data pkts + u32 mpdu_lost; // number of data packet losses (no ACK) + u32 retries; // total number of data pkt retries + u32 retries_short; // number of short data pkt retries + u32 retries_long; // number of long data pkt retries +} wifi_rate_stat; + +/* access categories */ +typedef enum { + WIFI_AC_VO = 0, + WIFI_AC_VI = 1, + WIFI_AC_BE = 2, + WIFI_AC_BK = 3, + WIFI_AC_MAX = 4, +} wifi_traffic_ac; + +/* wifi peer type */ +typedef enum +{ + WIFI_PEER_STA, + WIFI_PEER_AP, + WIFI_PEER_P2P_GO, + WIFI_PEER_P2P_CLIENT, + WIFI_PEER_NAN, + WIFI_PEER_TDLS, + WIFI_PEER_INVALID, +} wifi_peer_type; + +/* per peer statistics */ +typedef struct { + wifi_peer_type type; // peer type (AP, TDLS, GO etc.) + u8 peer_mac_address[6]; // mac address + u32 capabilities; // peer WIFI_CAPABILITY_XXX + u32 num_rate; // number of rates + wifi_rate_stat rate_stats[]; // per rate statistics, number of entries = num_rate +} wifi_peer_info; + +/* Per access category statistics */ +typedef struct { + wifi_traffic_ac ac; // access category (VI, VO, BE, BK) + u32 tx_mpdu; // number of successfully transmitted unicast data pkts (ACK rcvd) + u32 rx_mpdu; // number of received unicast data packets + u32 tx_mcast; // number of succesfully transmitted multicast data packets + // STA case: implies ACK received from AP for the unicast packet in which mcast pkt was sent + u32 rx_mcast; // number of received multicast data packets + u32 rx_ampdu; // number of received unicast a-mpdus; support of this counter is optional + u32 tx_ampdu; // number of transmitted unicast a-mpdus; support of this counter is optional + u32 mpdu_lost; // number of data pkt losses (no ACK) + u32 retries; // total number of data pkt retries + u32 retries_short; // number of short data pkt retries + u32 retries_long; // number of long data pkt retries + u32 contention_time_min; // data pkt min contention time (usecs) + u32 contention_time_max; // data pkt max contention time (usecs) + u32 contention_time_avg; // data pkt avg contention time (usecs) + u32 contention_num_samples; // num of data pkts used for contention statistics +} wifi_wmm_ac_stat; + +/* interface statistics */ +typedef struct { + wifi_interface_handle iface; // wifi interface + wifi_interface_link_layer_info info; // current state of the interface + u32 beacon_rx; // access point beacon received count from connected AP + u64 average_tsf_offset; // average beacon offset encountered (beacon_TSF - TBTT) + // The average_tsf_offset field is used so as to calculate the + // typical beacon contention time on the channel as well may be + // used to debug beacon synchronization and related power consumption issue + u32 leaky_ap_detected; // indicate that this AP typically leaks packets beyond the driver guard time. + u32 leaky_ap_avg_num_frames_leaked; // average number of frame leaked by AP after frame with PM bit set was ACK'ed by AP + u32 leaky_ap_guard_time; // guard time currently in force (when implementing IEEE power management based on + // frame control PM bit), How long driver waits before shutting down the radio and + // after receiving an ACK for a data frame with PM bit set) + u32 mgmt_rx; // access point mgmt frames received count from connected AP (including Beacon) + u32 mgmt_action_rx; // action frames received count + u32 mgmt_action_tx; // action frames transmit count + wifi_rssi rssi_mgmt; // access Point Beacon and Management frames RSSI (averaged) + wifi_rssi rssi_data; // access Point Data Frames RSSI (averaged) from connected AP + wifi_rssi rssi_ack; // access Point ACK RSSI (averaged) from connected AP + wifi_wmm_ac_stat ac[WIFI_AC_MAX]; // per ac data packet statistics + u32 num_peers; // number of peers + wifi_peer_info peer_info[]; // per peer statistics +} wifi_iface_stat; + +/* configuration params */ +typedef struct { + u32 mpdu_size_threshold; // threshold to classify the pkts as short or long + // packet size < mpdu_size_threshold => short + u32 aggressive_statistics_gathering; // set for field debug mode. Driver should collect all statistics regardless of performance impact. +} wifi_link_layer_params; + +/* callback for reporting link layer stats */ +typedef struct { + void (*on_link_stats_results) (wifi_request_id id, wifi_iface_stat *iface_stat, + int num_radios, wifi_radio_stat *radio_stat); +} wifi_stats_result_handler; + + +/* wifi statistics bitmap */ +#define WIFI_STATS_RADIO 0x00000001 // all radio statistics +#define WIFI_STATS_RADIO_CCA 0x00000002 // cca_busy_time (within radio statistics) +#define WIFI_STATS_RADIO_CHANNELS 0x00000004 // all channel statistics (within radio statistics) +#define WIFI_STATS_RADIO_SCAN 0x00000008 // all scan statistics (within radio statistics) +#define WIFI_STATS_IFACE 0x00000010 // all interface statistics +#define WIFI_STATS_IFACE_TXRATE 0x00000020 // all tx rate statistics (within interface statistics) +#define WIFI_STATS_IFACE_AC 0x00000040 // all ac statistics (within interface statistics) +#define WIFI_STATS_IFACE_CONTENTION 0x00000080 // all contention (min, max, avg) statistics (within ac statisctics) + +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ -/* Capture the BRCM_VENDOR_SUBCMD_PRIV_STRINGS* here */ -#define BRCM_VENDOR_SCMD_CAPA "cap" #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) extern int rtw_cfgvendor_attach(struct wiphy *wiphy); @@ -232,8 +551,8 @@ extern int rtw_cfgvendor_detach(struct wiphy *wiphy); extern int rtw_cfgvendor_send_async_event(struct wiphy *wiphy, struct net_device *dev, int event_id, const void *data, int len); #if defined(GSCAN_SUPPORT) && 0 -extern int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy, - struct net_device *dev, void *data, int len, wl_vendor_event_t event); +extern int rtw_cfgvendor_send_hotlist_event(struct wiphy *wiphy, + struct net_device *dev, void *data, int len, rtw_vendor_event_t event); #endif #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */ diff --git a/os_dep/linux/rtw_proc.c b/os_dep/linux/rtw_proc.c index 38ae3b2..e5577de 100644 --- a/os_dep/linux/rtw_proc.c +++ b/os_dep/linux/rtw_proc.c @@ -17,9 +17,7 @@ #include #include #include "rtw_proc.h" -#ifdef CONFIG_BT_COEXIST #include -#endif #ifdef CONFIG_PROC_DEBUG @@ -161,6 +159,21 @@ static int proc_get_chplan_test(struct seq_file *m, void *v) return 0; } +#ifdef RTW_HALMAC +extern void rtw_halmac_get_version(char *str, u32 len); + +static int proc_get_halmac_info(struct seq_file *m, void *v) +{ + char ver[30] = {0}; + + + rtw_halmac_get_version(ver, 30); + RTW_PRINT_SEL(m, "version: %s\n", ver); + + return 0; +} +#endif + /* * rtw_drv_proc: * init/deinit when register/unregister driver @@ -175,6 +188,9 @@ const struct rtw_proc_hdl drv_proc_hdls[] = { RTW_PROC_HDL_SSEQ("country_chplan_map", proc_get_country_chplan_map, NULL), RTW_PROC_HDL_SSEQ("chplan_id_list", proc_get_chplan_id_list, NULL), RTW_PROC_HDL_SSEQ("chplan_test", proc_get_chplan_test, NULL), +#ifdef RTW_HALMAC + RTW_PROC_HDL_SSEQ("halmac_info", proc_get_halmac_info, NULL), +#endif /* RTW_HALMAC */ }; const int drv_proc_hdls_num = sizeof(drv_proc_hdls) / sizeof(struct rtw_proc_hdl); @@ -377,17 +393,6 @@ static int proc_get_sdio_card_info(struct seq_file *m, void *v) } #endif /* CONFIG_SDIO_HCI */ -#ifdef RTW_HALMAC -#include "../../hal/hal_halmac.h" -static int proc_get_halmac_info(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - rtw_dump_halmac_info(m); - return 0; -} -#endif static int proc_get_fw_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -436,6 +441,93 @@ static int proc_get_rf_reg_dump(struct seq_file *m, void *v) return 0; } +#ifdef CONFIG_RTW_LED +int proc_get_led_config(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_led_config(m, adapter); + + return 0; +} + +ssize_t proc_set_led_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + char tmp[32]; + u8 strategy; + u8 iface_en_mask; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hhx", &strategy, &iface_en_mask); + + if (num >= 1) + rtw_led_set_strategy(adapter, strategy); + if (num >= 2) + rtw_led_set_iface_en_mask(adapter, iface_en_mask); + } + + return count; +} +#endif /* CONFIG_RTW_LED */ + +#ifdef CONFIG_AP_MODE +int proc_get_aid_status(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_aid_status(m, adapter); + + return 0; +} + +ssize_t proc_set_aid_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_priv *stapriv = &adapter->stapriv; + + char tmp[32]; + u8 rr; + u16 started_aid; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hu", &rr, &started_aid); + + if (num >= 1) + stapriv->rr_aid = rr ? 1 : 0; + if (num >= 2) { + started_aid = started_aid % (stapriv->max_aid + 1); + stapriv->started_aid = started_aid ? started_aid : 1; + } + } + + return count; +} +#endif /* CONFIG_AP_MODE */ + static int proc_get_dump_tx_rate_bmp(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -463,12 +555,17 @@ static int proc_get_customer_str(struct seq_file *m, void *v) _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); u8 cstr[RTW_CUSTOMER_STR_LEN]; + rtw_ps_deny(adapter, PS_DENY_IOCTL); + if (rtw_pwr_wakeup(adapter) == _FAIL) + goto exit; + if (rtw_hal_customer_str_read(adapter, cstr) != _SUCCESS) goto exit; RTW_PRINT_SEL(m, RTW_CUSTOMER_STR_FMT"\n", RTW_CUSTOMER_STR_ARG(cstr)); exit: + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); return 0; } #endif /* CONFIG_RTW_CUSTOMER_STR */ @@ -565,77 +662,6 @@ static ssize_t proc_set_gpio(struct file *file, const char __user *buffer, size_ } #endif -#ifdef CONFIG_CHNL_LOAD_MAGT -static ssize_t proc_set_clm_result(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - - char tmp[32] = {0}; - int clm_flag = 0; - int clm_scan_ms = SURVEY_TO; - u16 *clm_period = &pHalData->clm_period; - - RTW_INFO("DBG_RX_SEQ %s\n", __FUNCTION__); - - if (count < 1) { - RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter)); - return -EFAULT; - } - if (count > sizeof(tmp)) { - RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter)); - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%d %d", &clm_flag, &clm_scan_ms); - - if (num < 2) { - RTW_INFO("argument size is less than 2\n"); - goto exit; - } - RTW_INFO(" clm_flag = %d clm_scan_ms =%d\n", clm_flag, clm_scan_ms); - - padapter->clm_flag = (BOOLEAN)clm_flag; - RTW_INFO("clm feature on or off = %d\n", (int)padapter->clm_flag); - if (clm_flag == TRUE) { - if (clm_scan_ms > 200 || clm_scan_ms < 6) { - RTW_INFO("clm scan time need between 6 ~ 200ms\n"); - goto exit; - } - if (clm_scan_ms > 5 && clm_scan_ms <= 200) - *clm_period = (u16)((clm_scan_ms - 5)*1000/4); - pmlmeext->sitesurvey_res.scan_ch_ms = (u16)clm_scan_ms; - - RTW_INFO("clm_period = %u\n", pHalData->clm_period); - - } - } -exit: - return count; -} -static int proc_get_clm_result(struct seq_file *m, void *v) -{ - - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - u32 i; - - for (i = 0; i < rfctl->max_chan_nums ; i++) { - if (hal_data->clm_period != 0) - RTW_PRINT_SEL(m, "clm_period = %6u;clm_result =%6d ;channel %3d = %3d %%\n", hal_data->clm_period, hal_data->clm_result[i], rfctl->channel_set[i].ChannelNum, (hal_data->clm_result[i]*100/hal_data->clm_period)); - /* "x*100" to show by percentage*/ - } - return 0; -} -#endif - static ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { @@ -695,10 +721,12 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); - if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE)) + if (MLME_IS_STA(padapter)) status = "station mode"; - else if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE)) + else if (MLME_IS_AP(padapter)) status = "AP mode"; + else if (MLME_IS_MESH(padapter)) + status = "mesh mode"; else status = " "; _RTW_PRINT_SEL(m, "status=%s\n", status); @@ -712,11 +740,11 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) plist = get_next(plist); - if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), 6) != _TRUE)) { + if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, 6) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), 6) != _TRUE)) { - switch (psta->bw_mode) { + switch (psta->cmn.bw_mode) { case CHANNEL_WIDTH_20: BW = "20M"; @@ -738,11 +766,11 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) BW = ""; break; } - current_rate_id = rtw_get_current_tx_rate(adapter, psta->mac_id); - current_sgi = rtw_get_current_tx_sgi(adapter, psta->mac_id); + current_rate_id = rtw_get_current_tx_rate(adapter, psta); + current_sgi = rtw_get_current_tx_sgi(adapter, psta); RTW_PRINT_SEL(m, "==============================\n"); - _RTW_PRINT_SEL(m, "macaddr=" MAC_FMT"\n", MAC_ARG(psta->hwaddr)); + _RTW_PRINT_SEL(m, "macaddr=" MAC_FMT"\n", MAC_ARG(psta->cmn.mac_addr)); _RTW_PRINT_SEL(m, "Tx_Data_Rate=%s\n", HDATA_RATE(current_rate_id)); _RTW_PRINT_SEL(m, "BW=%s,sgi=%u\n", BW, current_sgi); @@ -809,6 +837,60 @@ static ssize_t proc_set_linked_info_dump(struct file *file, const char __user *b return count; } + +static int proc_get_sta_tp_dump(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + if (padapter) + RTW_PRINT_SEL(m, "sta_tp_dump :%s\n", (padapter->bsta_tp_dump) ? "enable" : "disable"); + + return 0; +} + +static ssize_t proc_set_sta_tp_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + char tmp[32] = {0}; + int mode = 0; + int num = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + num = sscanf(tmp, "%d ", &mode); + + if (num != 1) { + RTW_INFO("argument number is wrong\n"); + return -EFAULT; + } + if (padapter) + padapter->bsta_tp_dump = mode; + } + return count; +} + +static int proc_get_sta_tp_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + if (padapter) + rtw_sta_traffic_info(m, padapter); + + return 0; +} + static int proc_get_turboedca_ctrl(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -926,7 +1008,7 @@ static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; - u8 chan_plan = RTW_CHPLAN_MAX; + u8 chan_plan = RTW_CHPLAN_UNSPECIFIED; if (!padapter) return -EFAULT; @@ -1012,9 +1094,25 @@ ssize_t proc_set_macaddr_acl(struct file *file, const char __user *buffer, size_ struct mlme_priv *mlme = &adapter->mlmepriv; struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; char tmp[17 * NUM_ACL + 32] = {0}; + u8 period; + char cmd[32]; u8 mode; u8 addr[ETH_ALEN]; +#define MAC_ACL_CMD_MODE 0 +#define MAC_ACL_CMD_ADD 1 +#define MAC_ACL_CMD_DEL 2 +#define MAC_ACL_CMD_CLR 3 +#define MAC_ACL_CMD_NUM 4 + + static const char * const mac_acl_cmd_str[] = { + "mode", + "add", + "del", + "clr", + }; + u8 cmd_id = MAC_ACL_CMD_NUM; + if (count < 1) return -EFAULT; @@ -1024,36 +1122,93 @@ ssize_t proc_set_macaddr_acl(struct file *file, const char __user *buffer, size_ } if (buffer && !copy_from_user(tmp, buffer, count)) { - /* mode [] */ + /* + * mode [] + * mode + * add [] + * del [] + * clr + */ char *c, *next; + int i; + u8 is_bcast; next = tmp; c = strsep(&next, " \t"); + if (!c || sscanf(c, "%hhu", &period) != 1) + goto exit; - if (sscanf(c, "%hhu", &mode) != 1) - return count; + if (period >= RTW_ACL_PERIOD_NUM) { + RTW_WARN(FUNC_ADPT_FMT" invalid period:%u", FUNC_ADPT_ARG(adapter), period); + goto exit; + } - if (mode >= RTW_ACL_MODE_MAX) - mode = RTW_ACL_MODE_DISABLED; + c = strsep(&next, " \t"); + if (!c || sscanf(c, "%s", cmd) != 1) + goto exit; - rtw_set_macaddr_acl(adapter, RTW_ACL_MODE_DISABLED); /* deinit first */ - if (mode == RTW_ACL_MODE_DISABLED) - return count; + for (i = 0; i < MAC_ACL_CMD_NUM; i++) + if (strcmp(mac_acl_cmd_str[i], cmd) == 0) + cmd_id = i; + + switch (cmd_id) { + case MAC_ACL_CMD_MODE: + c = strsep(&next, " \t"); + if (!c || sscanf(c, "%hhu", &mode) != 1) + goto exit; + + if (mode >= RTW_ACL_MODE_MAX) { + RTW_WARN(FUNC_ADPT_FMT" invalid mode:%u", FUNC_ADPT_ARG(adapter), mode); + goto exit; + } + break; - rtw_set_macaddr_acl(adapter, mode); + case MAC_ACL_CMD_ADD: + case MAC_ACL_CMD_DEL: + break; - /* macaddr list */ + case MAC_ACL_CMD_CLR: + /* clear settings */ + rtw_macaddr_acl_clear(adapter, period); + goto exit; + + default: + RTW_WARN(FUNC_ADPT_FMT" invalid cmd:\"%s\"", FUNC_ADPT_ARG(adapter), cmd); + goto exit; + } + + /* check for macaddr list */ c = strsep(&next, " \t"); + if (!c && cmd_id == MAC_ACL_CMD_MODE) { + /* set mode only */ + rtw_set_macaddr_acl(adapter, period, mode); + goto exit; + } + + if (cmd_id == MAC_ACL_CMD_MODE) { + /* set mode and entire macaddr list */ + rtw_macaddr_acl_clear(adapter, period); + rtw_set_macaddr_acl(adapter, period, mode); + } + while (c != NULL) { if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6) break; - if (rtw_check_invalid_mac_address(addr, 0) == _FALSE) - rtw_acl_add_sta(adapter, addr); - + is_bcast = is_broadcast_mac_addr(addr); + if (is_bcast + || rtw_check_invalid_mac_address(addr, 0) == _FALSE + ) { + if (cmd_id == MAC_ACL_CMD_DEL) { + rtw_acl_remove_sta(adapter, period, addr); + if (is_bcast) + break; + } else if (!is_bcast) + rtw_acl_add_sta(adapter, period, addr); + } + c = strsep(&next, " \t"); } - } exit: @@ -1149,15 +1304,27 @@ ssize_t proc_set_pre_link_sta(struct file *file, const char __user *buffer, size } #endif /* CONFIG_RTW_PRE_LINK_STA */ -#ifdef CONFIG_DFS_MASTER -ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +static int proc_get_ch_sel_policy(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + RTW_PRINT_SEL(m, "%-16s\n", "same_band_prefer"); + + RTW_PRINT_SEL(m, "%16u\n", rfctl->ch_sel_same_band_prefer); + + return 0; +} + +static ssize_t proc_set_ch_sel_policy(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); char tmp[32]; - u8 ch, bw = CHANNEL_WIDTH_20, offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - int ms = -1; + u8 sb_prefer; + int num; if (count < 1) return -EFAULT; @@ -1167,32 +1334,41 @@ ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, si return -EFAULT; } - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhu %hhu %hhu %d", &ch, &bw, &offset, &ms); - - if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3)) - goto exit; + if (!buffer || copy_from_user(tmp, buffer, count)) + goto exit; - if (bw == CHANNEL_WIDTH_20) - rtw_chset_update_non_ocp_ms(rfctl->channel_set - , ch, bw, HAL_PRIME_CHNL_OFFSET_DONT_CARE, ms); - else - rtw_chset_update_non_ocp_ms(rfctl->channel_set - , ch, bw, offset, ms); - } + num = sscanf(tmp, "%hhu", &sb_prefer); + if (num >= 1) + rfctl->ch_sel_same_band_prefer = sb_prefer; exit: return count; } -ssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +#ifdef CONFIG_DFS_MASTER +int proc_get_dfs_master_test_case(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + RTW_PRINT_SEL(m, "%-24s %-19s\n", "radar_detect_trigger_non", "choose_dfs_ch_first"); + RTW_PRINT_SEL(m, "%24hhu %19hhu\n" + , rfctl->dbg_dfs_master_radar_detect_trigger_non + , rfctl->dbg_dfs_master_choose_dfs_ch_first + ); + + return 0; +} + +ssize_t proc_set_dfs_master_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); char tmp[32]; - u8 fake_radar_detect_cnt = 0; + u8 radar_detect_trigger_non; + u8 choose_dfs_ch_first; if (count < 1) return -EFAULT; @@ -1203,8 +1379,72 @@ ssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size } if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%hhu %hhu", &radar_detect_trigger_non, &choose_dfs_ch_first); - int num = sscanf(tmp, "%hhu", &fake_radar_detect_cnt); + if (num >= 1) + rfctl->dbg_dfs_master_radar_detect_trigger_non = radar_detect_trigger_non; + if (num >= 2) + rfctl->dbg_dfs_master_choose_dfs_ch_first = choose_dfs_ch_first; + } + + return count; +} + +ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + char tmp[32]; + u8 ch, bw = CHANNEL_WIDTH_20, offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + int ms = -1; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hhu %hhu %d", &ch, &bw, &offset, &ms); + + if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3)) + goto exit; + + if (bw == CHANNEL_WIDTH_20) + rtw_chset_update_non_ocp_ms(rfctl->channel_set + , ch, bw, HAL_PRIME_CHNL_OFFSET_DONT_CARE, ms); + else + rtw_chset_update_non_ocp_ms(rfctl->channel_set + , ch, bw, offset, ms); + } + +exit: + return count; +} + +ssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + char tmp[32]; + u8 fake_radar_detect_cnt = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu", &fake_radar_detect_cnt); if (num < 1) goto exit; @@ -1373,7 +1613,7 @@ static int proc_get_macid_info(struct seq_file *m, void *v) _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - u8 chip_type = rtw_get_chip_type(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); u8 i; u8 null_addr[ETH_ALEN] = {0}; u8 *macaddr; @@ -1385,10 +1625,10 @@ static int proc_get_macid_info(struct seq_file *m, void *v) dump_macid_map(m, &macid_ctl->used, macid_ctl->num); RTW_PRINT_SEL(m, "\n"); - RTW_PRINT_SEL(m, "%-3s %-3s %-4s %-4s %-17s %-6s %-3s" - , "id", "bmc", "if_g", "ch_g", "macaddr", "bw", "vht"); + RTW_PRINT_SEL(m, "%-3s %-3s %-5s %-4s %-17s %-6s %-3s" + , "id", "bmc", "ifbmp", "ch_g", "macaddr", "bw", "vht"); - if (chip_type == RTL8814A) + if (hal_spec->tx_nss_num > 2) _RTW_PRINT_SEL(m, " %-10s", "rate_bmp1"); _RTW_PRINT_SEL(m, " %-10s %s\n", "rate_bmp0", "status"); @@ -1398,21 +1638,21 @@ static int proc_get_macid_info(struct seq_file *m, void *v) || macid_ctl->h2c_msr[i] ) { if (macid_ctl->sta[i]) - macaddr = macid_ctl->sta[i]->hwaddr; + macaddr = macid_ctl->sta[i]->cmn.mac_addr; else macaddr = null_addr; - RTW_PRINT_SEL(m, "%3u %3u %4d %4d "MAC_FMT" %6s %3u" + RTW_PRINT_SEL(m, "%3u %3u 0x%02x %4d "MAC_FMT" %6s %3u" , i , rtw_macid_is_bmc(macid_ctl, i) - , rtw_macid_get_if_g(macid_ctl, i) + , rtw_macid_get_iface_bmp(macid_ctl, i) , rtw_macid_get_ch_g(macid_ctl, i) , MAC_ARG(macaddr) , ch_width_str(macid_ctl->bw[i]) , macid_ctl->vht_en[i] ); - if (chip_type == RTL8814A) + if (hal_spec->tx_nss_num > 2) _RTW_PRINT_SEL(m, " 0x%08X", macid_ctl->rate_bmp1[i]); _RTW_PRINT_SEL(m, " 0x%08X "H2C_MSR_FMT" %s\n" @@ -1535,7 +1775,8 @@ static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *bu if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3)) goto exit; - if (check_fwstate(mlme, WIFI_AP_STATE) && check_fwstate(mlme, WIFI_ASOC_STATE)) + if ((MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) + && check_fwstate(mlme, WIFI_ASOC_STATE)) rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_WAIT_ACK, ch, bw, offset); } @@ -1596,7 +1837,7 @@ static ssize_t proc_set_tx_bw_mode(struct file *file, const char __user *buffer, for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { sta = macid_ctl->sta[i]; - if (sta && !is_broadcast_mac_addr(sta->hwaddr)) + if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) rtw_dm_ra_mask_wk_cmd(adapter, (u8 *)sta); } } @@ -1690,13 +1931,15 @@ static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user * #endif rtw_ps_deny(adapter, PS_DENY_IOCTL); - LeaveAllPowerSaveModeDirect(adapter); + if (rtw_pwr_wakeup(adapter) == _FALSE) + goto clear_ps_deny; if (strcmp("default", cmd) == 0) rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_default_tx_power_ext_info)), adapter); else rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_tx_power_ext_info)), adapter); +clear_ps_deny: rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); } @@ -2319,26 +2562,93 @@ static ssize_t proc_set_skip_band(struct file *file, const char __user *buffer, } -#ifdef CONFIG_AUTO_CHNL_SEL_NHM -static int proc_get_best_chan(struct seq_file *m, void *v) +#ifdef CONFIG_RTW_ACS +static int proc_get_chan_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - u8 best_24g_ch = 0, best_5g_ch = 0; - rtw_hal_get_odm_var(adapter, HAL_ODM_AUTO_CHNL_SEL, &(best_24g_ch), &(best_5g_ch)); + rtw_acs_chan_info_dump(m, adapter); + return 0; +} + +static int proc_get_best_chan(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - RTW_PRINT_SEL(m, "Best 2.4G CH:%u\n", best_24g_ch); - RTW_PRINT_SEL(m, "Best 5G CH:%u\n", best_5g_ch); + if (IS_ACS_ENABLE(adapter)) + rtw_acs_info_dump(m, adapter); + else + _RTW_PRINT_SEL(m,"ACS disabled\n"); return 0; } static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ +#ifdef CONFIG_RTW_ACS_DBG + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 acs_state = 0; + u16 scan_ch_ms= 0, acs_scan_ch_ms = 0; + u8 scan_type = SCAN_ACTIVE, igi= 0, bw = 0; + u8 acs_scan_type = SCAN_ACTIVE, acs_igi= 0, acs_bw = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hhu %hu %hhx %hhu", + &acs_state, &scan_type, &scan_ch_ms, &igi, &bw); + + if (num < 1) + return -EINVAL; + + if (acs_state) + rtw_acs_start(padapter); + else + rtw_acs_stop(padapter); + num = num -1; + + if(num) { + if (num-- > 0) + acs_scan_type = scan_type; + if (num-- > 0) + acs_scan_ch_ms = scan_ch_ms; + if (num-- > 0) + acs_igi = igi; + if (num-- > 0) + acs_bw = bw; + rtw_acs_adv_setting(padapter, acs_scan_type, acs_scan_ch_ms, acs_igi, acs_bw); + } + } +#endif /*CONFIG_RTW_ACS_DBG*/ + return count; +} +#endif /*CONFIG_RTW_ACS*/ + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR +static int proc_get_nm(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_noise_info_dump(m, adapter); + return 0; +} + +static ssize_t proc_set_nm(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; - u8 acs_satae = 0; + u8 nm_state = 0; if (count < 1) return -EFAULT; @@ -2349,20 +2659,20 @@ static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t } if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hhu", &acs_satae); + int num = sscanf(tmp, "%hhu", &nm_state); if (num < 1) return -EINVAL; - if (1 == acs_satae) - rtw_acs_start(padapter, _TRUE); + if (nm_state) + rtw_nm_enable(padapter); else - rtw_acs_start(padapter, _FALSE); + rtw_nm_disable(padapter); } return count; } -#endif +#endif /*CONFIG_RTW_ACS*/ static int proc_get_hal_spec(struct seq_file *m, void *v) { @@ -2495,6 +2805,8 @@ static int proc_get_napi_info(struct seq_file *m, void *v) struct registry_priv *pregistrypriv = &adapter->registrypriv; u8 napi = 0, gro = 0; u32 weight = 0; + struct dvobj_priv *d; + d = adapter_to_dvobj(adapter); #ifdef CONFIG_RTW_NAPI @@ -2509,14 +2821,71 @@ static int proc_get_napi_info(struct seq_file *m, void *v) #endif /* CONFIG_RTW_GRO */ #endif /* CONFIG_RTW_NAPI */ - if (napi) + if (napi) { RTW_PRINT_SEL(m, "NAPI enable, weight=%d\n", weight); - else +#ifdef CONFIG_RTW_NAPI_DYNAMIC + RTW_PRINT_SEL(m, "Dynamaic NAPI mechanism is on, current NAPI %s\n", + d->en_napi_dynamic ? "enable" : "disable"); + RTW_PRINT_SEL(m, "Dynamaic NAPI info:\n" + "\ttcp_rx_threshold = %d Mbps\n" + "\tcur_rx_tp = %d Mbps\n", + pregistrypriv->napi_threshold, + d->traffic_stat.cur_rx_tp); +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ + } else { RTW_PRINT_SEL(m, "NAPI disable\n"); + } RTW_PRINT_SEL(m, "GRO %s\n", gro?"enable":"disable"); return 0; + +} + +#ifdef CONFIG_RTW_NAPI_DYNAMIC +static ssize_t proc_set_napi_th(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + struct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev); + struct registry_priv *registry = &adapter->registrypriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + PADAPTER iface = NULL; + char tmp[32] = {0}; + int thrshld = 0; + int num = 0, i = 0; + + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + RTW_INFO("%s: Last threshold = %d Mbps\n", __FUNCTION__, registry->napi_threshold); + + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + if (buffer && !copy_from_user(tmp, buffer, count)) { + registry = &iface->registrypriv; + num = sscanf(tmp, "%d", &thrshld); + if (num > 0) { + if (thrshld > 0) + registry->napi_threshold = thrshld; + } + } + } + } + RTW_INFO("%s: New threshold = %d Mbps\n", __FUNCTION__, registry->napi_threshold); + RTW_INFO("%s: Current RX throughput = %d Mbps\n", + __FUNCTION__, adapter_to_dvobj(adapter)->traffic_stat.cur_rx_tp); + + return count; } +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ + ssize_t proc_set_dynamic_agg_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { @@ -2566,6 +2935,228 @@ static int proc_get_dynamic_agg_enable(struct seq_file *m, void *v) return 0; } +#ifdef CONFIG_RTW_MESH +static int proc_get_mesh_peer_sel_policy(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_mesh_peer_sel_policy(m, adapter); + + return 0; +} + +#if CONFIG_RTW_MESH_PEER_BLACKLIST +static int proc_get_mesh_peer_blacklist(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) { + dump_mesh_peer_blacklist_settings(m, adapter); + if (MLME_IS_ASOC(adapter)) + dump_mesh_peer_blacklist(m, adapter); + } + + return 0; +} + +static ssize_t proc_set_mesh_peer_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + u32 conf_timeout_ms; + u32 blacklist_timeout_ms; + int num = sscanf(tmp, "%u %u", &conf_timeout_ms, &blacklist_timeout_ms); + + if (num >= 1) + peer_sel_policy->peer_conf_timeout_ms = conf_timeout_ms; + if (num >= 2) + peer_sel_policy->peer_blacklist_timeout_ms = blacklist_timeout_ms; + } + +exit: + return count; +} +#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */ + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST +static int proc_get_mesh_cto_mgate_blacklist(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) { + dump_mesh_cto_mgate_blacklist_settings(m, adapter); + if (MLME_IS_ASOC(adapter)) + dump_mesh_cto_mgate_blacklist(m, adapter); + } + + return 0; +} + +static ssize_t proc_set_mesh_cto_mgate_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + u8 require; + u32 conf_timeout_ms; + u32 blacklist_timeout_ms; + int num = sscanf(tmp, "%hhx %u %u", &require, &conf_timeout_ms, &blacklist_timeout_ms); + + if (num >= 1) + peer_sel_policy->cto_mgate_require = require; + if (num >= 2) + peer_sel_policy->cto_mgate_conf_timeout_ms = conf_timeout_ms; + if (num >= 3) + peer_sel_policy->cto_mgate_blacklist_timeout_ms = blacklist_timeout_ms; + } + +exit: + return count; +} +#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */ + +static int proc_get_mesh_networks(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_mesh_networks(m, adapter); + + return 0; +} + +static int proc_get_mesh_plink_ctl(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) + dump_mesh_plink_ctl(m, adapter); + + return 0; +} + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC +static int proc_get_mesh_b2u_flags(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) + dump_mesh_b2u_flags(m, adapter); + + return 0; +} + +static ssize_t proc_set_mesh_b2u_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + u8 msrc, mfwd; + int num = sscanf(tmp, "%hhx %hhx", &msrc, &mfwd); + + if (num >= 1) + mcfg->b2u_flags_msrc = msrc; + if (num >= 2) + mcfg->b2u_flags_mfwd = mfwd; + } + +exit: + return count; +} +#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */ + +static int proc_get_mesh_stats(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) + dump_mesh_stats(m, adapter); + + return 0; +} + +static int proc_get_mesh_gate_timeout(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) + RTW_PRINT_SEL(m, "%u factor\n", + adapter->mesh_cfg.path_gate_timeout_factor); + + return 0; +} + +static ssize_t proc_set_mesh_gate_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + u32 timeout; + int num = sscanf(tmp, "%u", &timeout); + + if (num < 1) + goto exit; + + mcfg->path_gate_timeout_factor = timeout; + } + +exit: + return count; +} +#endif /* CONFIG_RTW_MESH */ + /* * rtw_adapter_proc: * init/deinit when register/unregister net_device @@ -2592,6 +3183,9 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #ifdef CONFIG_SCAN_BACKOP RTW_PROC_HDL_SSEQ("backop_flags_sta", proc_get_backop_flags_sta, proc_set_backop_flags_sta), RTW_PROC_HDL_SSEQ("backop_flags_ap", proc_get_backop_flags_ap, proc_set_backop_flags_ap), +#endif +#ifdef CONFIG_RTW_REPEATER_SON + RTW_PROC_HDL_SSEQ("rson_data", proc_get_rson_data, proc_set_rson_data), #endif RTW_PROC_HDL_SSEQ("survey_info", proc_get_survey_info, proc_set_survey_info), RTW_PROC_HDL_SSEQ("ap_info", proc_get_ap_info, NULL), @@ -2599,13 +3193,12 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("tx_power_offset", proc_get_tx_power_offset, proc_set_tx_power_offset), RTW_PROC_HDL_SSEQ("rate_ctl", proc_get_rate_ctl, proc_set_rate_ctl), RTW_PROC_HDL_SSEQ("bw_ctl", proc_get_bw_ctl, proc_set_bw_ctl), - RTW_PROC_HDL_SSEQ("dis_pwt_ctl", proc_get_dis_pwt, proc_set_dis_pwt), RTW_PROC_HDL_SSEQ("mac_qinfo", proc_get_mac_qinfo, NULL), RTW_PROC_HDL_SSEQ("macid_info", proc_get_macid_info, NULL), RTW_PROC_HDL_SSEQ("bcmc_info", proc_get_mi_ap_bc_info, NULL), RTW_PROC_HDL_SSEQ("sec_cam", proc_get_sec_cam, proc_set_sec_cam), RTW_PROC_HDL_SSEQ("sec_cam_cache", proc_get_sec_cam_cache, NULL), - RTW_PROC_HDL_SSEQ("suspend_info", proc_get_suspend_resume_info, NULL), + RTW_PROC_HDL_SSEQ("ps_dbg_info", proc_get_ps_dbg_info, proc_set_ps_dbg_info), RTW_PROC_HDL_SSEQ("wifi_spec", proc_get_wifi_spec, NULL), #ifdef CONFIG_LAYER2_ROAMING RTW_PROC_HDL_SSEQ("roam_flags", proc_get_roam_flags, proc_set_roam_flags), @@ -2633,8 +3226,14 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("bb_reg_dump_ex", proc_get_bb_reg_dump_ex, NULL), RTW_PROC_HDL_SSEQ("rf_reg_dump", proc_get_rf_reg_dump, NULL), +#ifdef CONFIG_RTW_LED + RTW_PROC_HDL_SSEQ("led_config", proc_get_led_config, proc_set_led_config), +#endif + #ifdef CONFIG_AP_MODE + RTW_PROC_HDL_SSEQ("aid_status", proc_get_aid_status, proc_set_aid_status), RTW_PROC_HDL_SSEQ("all_sta_info", proc_get_all_sta_info, NULL), + RTW_PROC_HDL_SSEQ("bmc_tx_rate", proc_get_bmc_tx_rate, proc_set_bmc_tx_rate), #endif /* CONFIG_AP_MODE */ #ifdef DBG_MEMORY_LEAK @@ -2686,12 +3285,12 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #endif /* DBG_CONFIG_ERROR_DETECT */ RTW_PROC_HDL_SSEQ("trx_info_debug", proc_get_trx_info_debug, NULL), RTW_PROC_HDL_SSEQ("linked_info_dump", proc_get_linked_info_dump, proc_set_linked_info_dump), + RTW_PROC_HDL_SSEQ("sta_tp_dump", proc_get_sta_tp_dump, proc_set_sta_tp_dump), + RTW_PROC_HDL_SSEQ("sta_tp_info", proc_get_sta_tp_info, NULL), RTW_PROC_HDL_SSEQ("dis_turboedca", proc_get_turboedca_ctrl, proc_set_turboedca_ctrl), RTW_PROC_HDL_SSEQ("tx_info_msg", proc_get_tx_info_msg, NULL), RTW_PROC_HDL_SSEQ("rx_info_msg", proc_get_rx_info_msg, proc_set_rx_info_msg), -#ifdef CONFIG_CHNL_LOAD_MAGT - RTW_PROC_HDL_SSEQ("clm_result", proc_get_clm_result, proc_set_clm_result), -#endif + #ifdef CONFIG_GPIO_API RTW_PROC_HDL_SSEQ("gpio_info", proc_get_gpio, proc_set_gpio), RTW_PROC_HDL_SSEQ("gpio_set_output_value", NULL, proc_set_gpio_output_value), @@ -2704,14 +3303,24 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("int_logs", proc_get_int_logs, NULL), #endif +#ifdef CONFIG_DBG_RF_CAL + RTW_PROC_HDL_SSEQ("iqk", proc_get_iqk_info, proc_set_iqk), + RTW_PROC_HDL_SSEQ("lck", proc_get_lck_info, proc_set_lck), +#endif + #ifdef CONFIG_PCI_HCI RTW_PROC_HDL_SSEQ("rx_ring", proc_get_rx_ring, NULL), RTW_PROC_HDL_SSEQ("tx_ring", proc_get_tx_ring, NULL), +#ifdef DBG_TXBD_DESC_DUMP + RTW_PROC_HDL_SSEQ("tx_ring_ext", proc_get_tx_ring_ext, proc_set_tx_ring_ext), +#endif RTW_PROC_HDL_SSEQ("pci_aspm", proc_get_pci_aspm, NULL), #endif #ifdef CONFIG_WOWLAN RTW_PROC_HDL_SSEQ("wow_pattern_info", proc_get_pattern_info, proc_set_pattern_info), + RTW_PROC_HDL_SSEQ("wow_wakeup_event", proc_get_wakeup_event, + proc_set_wakeup_event), RTW_PROC_HDL_SSEQ("wowlan_last_wake_reason", proc_get_wakeup_reason, NULL), #ifdef CONFIG_WOW_PATTERN_HW_CAM RTW_PROC_HDL_SSEQ("wow_pattern_cam", proc_dump_pattern_cam, NULL), @@ -2733,6 +3342,7 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #if CONFIG_RTW_PRE_LINK_STA RTW_PROC_HDL_SSEQ("pre_link_sta", proc_get_pre_link_sta, proc_set_pre_link_sta), #endif + RTW_PROC_HDL_SSEQ("ch_sel_policy", proc_get_ch_sel_policy, proc_set_ch_sel_policy), #ifdef CONFIG_DFS_MASTER RTW_PROC_HDL_SSEQ("dfs_master_test_case", proc_get_dfs_master_test_case, proc_set_dfs_master_test_case), RTW_PROC_HDL_SSEQ("update_non_ocp", NULL, proc_set_update_non_ocp), @@ -2762,15 +3372,25 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #endif #ifdef CONFIG_POWER_SAVING RTW_PROC_HDL_SSEQ("ps_info", proc_get_ps_info, NULL), +#ifdef CONFIG_WMMPS_STA + RTW_PROC_HDL_SSEQ("wmmps_info", proc_get_wmmps_info, proc_set_wmmps_info), +#endif /* CONFIG_WMMPS_STA */ #endif #ifdef CONFIG_TDLS RTW_PROC_HDL_SSEQ("tdls_info", proc_get_tdls_info, NULL), + RTW_PROC_HDL_SSEQ("tdls_enable", proc_get_tdls_enable, proc_set_tdls_enable), #endif RTW_PROC_HDL_SSEQ("monitor", proc_get_monitor, proc_set_monitor), -#ifdef CONFIG_AUTO_CHNL_SEL_NHM +#ifdef CONFIG_RTW_ACS RTW_PROC_HDL_SSEQ("acs", proc_get_best_chan, proc_set_acs), + RTW_PROC_HDL_SSEQ("chan_info", proc_get_chan_info, NULL), +#endif + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + RTW_PROC_HDL_SSEQ("noise_monitor", proc_get_nm, proc_set_nm), #endif + #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER RTW_PROC_HDL_SSEQ("rtkm_info", proc_get_rtkm_info, NULL), #endif @@ -2805,15 +3425,16 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("trx_share_mode", proc_get_trx_share_mode, NULL), #endif RTW_PROC_HDL_SSEQ("napi_info", proc_get_napi_info, NULL), +#ifdef CONFIG_RTW_NAPI_DYNAMIC + RTW_PROC_HDL_SSEQ("napi_th", proc_get_napi_info, proc_set_napi_th), +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ + RTW_PROC_HDL_SSEQ("rsvd_page", proc_dump_rsvd_page, proc_set_rsvd_page_info), #ifdef CONFIG_SUPPORT_FIFO_DUMP RTW_PROC_HDL_SSEQ("fifo_dump", proc_dump_fifo, proc_set_fifo_info), #endif RTW_PROC_HDL_SSEQ("fw_info", proc_get_fw_info, NULL), -#ifdef RTW_HALMAC - RTW_PROC_HDL_SSEQ("halmac_info", proc_get_halmac_info, NULL), -#endif #ifdef DBG_XMIT_BLOCK RTW_PROC_HDL_SSEQ("xmit_block", proc_get_xmit_block, proc_set_xmit_block), @@ -2822,8 +3443,24 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("ack_timeout", proc_get_ack_timeout, proc_set_ack_timeout), RTW_PROC_HDL_SSEQ("dynamic_agg_enable", proc_get_dynamic_agg_enable, proc_set_dynamic_agg_enable), - RTW_PROC_HDL_SSEQ("iqk_fw_offload", proc_get_iqk_fw_offload, proc_set_iqk_fw_offload), - + RTW_PROC_HDL_SSEQ("fw_offload", proc_get_fw_offload, proc_set_fw_offload), + +#ifdef CONFIG_RTW_MESH + #if CONFIG_RTW_MESH_PEER_BLACKLIST + RTW_PROC_HDL_SSEQ("mesh_peer_blacklist", proc_get_mesh_peer_blacklist, proc_set_mesh_peer_blacklist), + #endif + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + RTW_PROC_HDL_SSEQ("mesh_cto_mgate_blacklist", proc_get_mesh_cto_mgate_blacklist, proc_set_mesh_cto_mgate_blacklist), + #endif + RTW_PROC_HDL_SSEQ("mesh_peer_sel_policy", proc_get_mesh_peer_sel_policy, NULL), + RTW_PROC_HDL_SSEQ("mesh_networks", proc_get_mesh_networks, NULL), + RTW_PROC_HDL_SSEQ("mesh_plink_ctl", proc_get_mesh_plink_ctl, NULL), + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + RTW_PROC_HDL_SSEQ("mesh_b2u_flags", proc_get_mesh_b2u_flags, proc_set_mesh_b2u_flags), + #endif + RTW_PROC_HDL_SSEQ("mesh_stats", proc_get_mesh_stats, NULL), + RTW_PROC_HDL_SSEQ("mesh_gate_timeout_factor", proc_get_mesh_gate_timeout, proc_set_mesh_gate_timeout), +#endif }; const int adapter_proc_hdls_num = sizeof(adapter_proc_hdls) / sizeof(struct rtw_proc_hdl); @@ -2880,45 +3517,6 @@ static const struct file_operations rtw_adapter_proc_sseq_fops = { .write = rtw_adapter_proc_write, }; - -int proc_get_odm_force_igi_lb(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - - RTW_PRINT_SEL(m, "force_igi_lb:0x%02x\n", rtw_odm_get_force_igi_lb(padapter)); - - return 0; -} - -ssize_t proc_set_odm_force_igi_lb(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 force_igi_lb; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx", &force_igi_lb); - - if (num != 1) - return count; - - rtw_odm_set_force_igi_lb(padapter, force_igi_lb); - } - - return count; -} - int proc_get_odm_adaptivity(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -2968,14 +3566,12 @@ int proc_get_phydm_cmd(struct seq_file *m, void *v) { struct net_device *netdev; PADAPTER padapter; - PHAL_DATA_TYPE pHalData; - struct PHY_DM_STRUCT *phydm; + struct dm_struct *phydm; netdev = m->private; padapter = (PADAPTER)rtw_netdev_priv(netdev); - pHalData = GET_HAL_DATA(padapter); - phydm = &pHalData->odmpriv; + phydm = adapter_to_phydm(padapter); if (NULL == phydm_msg) { phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN); @@ -2997,15 +3593,13 @@ ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t { struct net_device *netdev; PADAPTER padapter; - PHAL_DATA_TYPE pHalData; - struct PHY_DM_STRUCT *phydm; + struct dm_struct *phydm; char tmp[64] = {0}; netdev = (struct net_device *)data; padapter = (PADAPTER)rtw_netdev_priv(netdev); - pHalData = GET_HAL_DATA(padapter); - phydm = &pHalData->odmpriv; + phydm = adapter_to_phydm(padapter); if (count < 1) return -EFAULT; @@ -3032,97 +3626,13 @@ ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t return count; } -#ifdef CONFIG_LAMODE -static void *proc_start_lamode_dump(struct seq_file *m, loff_t *pos) -{ - _adapter *adapter = (_adapter *)rtw_netdev_priv(m->private); - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - static unsigned long index; - static unsigned long max; - - - if (*pos == 0) { - rtw_pm_set_ips(adapter, IPS_NONE); - rtw_pm_set_lps(adapter, PS_MODE_ACTIVE); - ADCSmp_Start(pDM_Odm, AdcSmp); - index = 0; - *pos = max = ADCSmp_Get_SampleCounts(pDM_Odm); - if (max == 0) - return NULL; - } else if (index >= max) { - return NULL; - } - - return &index; -} - -static void proc_stop_lamode_dump(struct seq_file *m, void *v) -{ - /* v is a NULL in kernel 3.19.0-25 */ -} - -static void *proc_next_lamode_dump(struct seq_file *m, void *v, loff_t *pos) -{ - _adapter *adapter = (_adapter *)rtw_netdev_priv(m->private); - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - unsigned long *index = v; - - - *index += 2; - if (*index >= *pos) { - ADCSmp_DeInit(pDM_Odm); - if (phydm_msg) { - _RTW_PRINT_SEL(m, "%s", phydm_msg); - rtw_mfree(phydm_msg, PHYDM_MSG_LEN); - phydm_msg = NULL; - } - return NULL; - } - return index; -} - -static int proc_show_lamode_data(struct seq_file *m, void *v) -{ - _adapter *adapter = (_adapter *)rtw_netdev_priv(m->private); - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - unsigned long *index = v; - char line[32]; - int rtn; - - - memset(line, 0, sizeof(line)); - rtn = ADCSmp_Query_SingleData(pDM_Odm, line, sizeof(line), *index); - _RTW_PRINT_SEL(m, "%s", line); - - if (rtn<0) - return -1; - - return 0; -} - -static struct seq_operations seq_ops_lamode = { - .start = proc_start_lamode_dump, - .stop = proc_stop_lamode_dump, - .next = proc_next_lamode_dump, - .show = proc_show_lamode_data, -}; -#endif /* CONFIG_LAMODE */ - /* * rtw_odm_proc: * init/deinit when register/unregister net_device, along with rtw_adapter_proc */ const struct rtw_proc_hdl odm_proc_hdls[] = { RTW_PROC_HDL_SSEQ("adaptivity", proc_get_odm_adaptivity, proc_set_odm_adaptivity), - RTW_PROC_HDL_SSEQ("force_igi_lb", proc_get_odm_force_igi_lb, proc_set_odm_force_igi_lb), RTW_PROC_HDL_SSEQ("cmd", proc_get_phydm_cmd, proc_set_phydm_cmd), -#ifdef CONFIG_LAMODE - RTW_PROC_HDL_SEQ("lamode", &seq_ops_lamode, proc_set_phydm_cmd) -#endif /* CONFIG_LAMODE */ }; const int odm_proc_hdls_num = sizeof(odm_proc_hdls) / sizeof(struct rtw_proc_hdl); @@ -3255,6 +3765,7 @@ void rtw_odm_proc_deinit(_adapter *adapter) const struct rtw_proc_hdl mcc_proc_hdls[] = { RTW_PROC_HDL_SSEQ("mcc_info", proc_get_mcc_info, NULL), RTW_PROC_HDL_SSEQ("mcc_enable", proc_get_mcc_info, proc_set_mcc_enable), + RTW_PROC_HDL_SSEQ("mcc_duration", proc_get_mcc_info, proc_set_mcc_duration), RTW_PROC_HDL_SSEQ("mcc_single_tx_criteria", proc_get_mcc_info, proc_set_mcc_single_tx_criteria), RTW_PROC_HDL_SSEQ("mcc_ap_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw20_target_tp), RTW_PROC_HDL_SSEQ("mcc_ap_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw40_target_tp), @@ -3262,7 +3773,7 @@ const struct rtw_proc_hdl mcc_proc_hdls[] = { RTW_PROC_HDL_SSEQ("mcc_sta_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw20_target_tp), RTW_PROC_HDL_SSEQ("mcc_sta_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw40_target_tp), RTW_PROC_HDL_SSEQ("mcc_sta_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw80_target_tp), - RTW_PROC_HDL_SSEQ("mcc_policy_table", proc_get_mcc_policy_table, proc_set_mcc_policy_table), + RTW_PROC_HDL_SSEQ("mcc_policy_table", proc_get_mcc_policy_table, NULL), }; const int mcc_proc_hdls_num = sizeof(mcc_proc_hdls) / sizeof(struct rtw_proc_hdl); diff --git a/os_dep/linux/usb_intf.c b/os_dep/linux/usb_intf.c index b490d27..34a36d5 100644 --- a/os_dep/linux/usb_intf.c +++ b/os_dep/linux/usb_intf.c @@ -233,14 +233,12 @@ static struct usb_device_id rtw_usb_id_tbl[] = { #ifdef CONFIG_RTL8822B /*=== Realtek demoboard ===*/ - /*=== Realtek demoboard ===*/ - {USB_DEVICE(0x0BDA, 0xB812), .driver_info = RTL8822B}, - {USB_DEVICE(0x0B05, 0x1812), .driver_info = RTL8812}, /* ASUS - Edimax */ - {USB_DEVICE(0x7392, 0xB822), .driver_info = RTL8822B}, /* Edimax - EW-7822ULC */ - {USB_DEVICE(0x0b05, 0x184c), .driver_info = RTL8822B}, /* ASUS USB AC53 */ - {USB_DEVICE(0x7392, 0xC822), .driver_info = RTL8822B}, /* Edimax - EW-7822UTC */ - {USB_DEVICE(0x2001, 0x331c), .driver_info = RTL8822B}, /* D-Link - DWA-182 Rev D */ - {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB82C, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Default ID */ + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB82C, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Default ID for USB multi-function */ + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB812, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Default ID for USB Single-function, WiFi only */ + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_EDIMAX, 0xB822, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, //EDX + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_EDIMAX, 0xC822, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, //EDX + /*=== Customer ID ===*/ + {USB_DEVICE_AND_INTERFACE_INFO(0x13b1, 0x0043, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Alpha - Alpha*/ #endif /* CONFIG_RTL8822B */ #ifdef CONFIG_RTL8723D @@ -256,6 +254,8 @@ static struct usb_device_id rtw_usb_id_tbl[] = { {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC820, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC82A, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC82B, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8821CU */ + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xC811, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8811CU */ + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0x8811, 0xff, 0xff, 0xff), .driver_info = RTL8821C}, /* 8811CU */ /*=== Customer ID ===*/ #endif @@ -833,7 +833,7 @@ int rtw_hw_suspend(_adapter *padapter) /* padapter->net_closed = _TRUE; */ /* s1. */ if (pnetdev) { - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); } @@ -891,7 +891,7 @@ int rtw_hw_resume(_adapter *padapter) _exit_pwrlock(&pwrpriv->lock); goto error_exit; } - + rtw_netif_device_attach(pnetdev); rtw_netif_carrier_on(pnetdev); rtw_netif_wake_queue(pnetdev); @@ -1042,9 +1042,12 @@ static int rtw_resume(struct usb_interface *pusb_intf) RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid); pdbgpriv->dbg_resume_cnt++; + #ifdef CONFIG_AUTOSUSPEND if (pwrpriv->bInternalAutoSuspend) ret = rtw_resume_process(padapter); - else { + else + #endif + { if (pwrpriv->wowlan_mode || pwrpriv->wowlan_ap_mode) { rtw_resume_lock_suspend(); ret = rtw_resume_process(padapter); @@ -1251,6 +1254,11 @@ _adapter *rtw_usb_primary_adapter_init(struct dvobj_priv *dvobj, /* step usb endpoint mapping */ rtw_hal_chip_configure(padapter); +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_Initialize(padapter); +#endif + rtw_btcoex_wifionly_initialize(padapter); + /* step read efuse/eeprom data and get mac_addr */ if (rtw_hal_read_chip_info(padapter) == _FAIL) goto free_hal_data; @@ -1260,15 +1268,6 @@ _adapter *rtw_usb_primary_adapter_init(struct dvobj_priv *dvobj, goto free_hal_data; } -#ifdef CONFIG_BT_COEXIST - if (GET_HAL_DATA(padapter)->EEPROMBluetoothCoexist) - rtw_btcoex_Initialize(padapter); - else - rtw_btcoex_wifionly_initialize(padapter); -#else /* !CONFIG_BT_COEXIST */ - rtw_btcoex_wifionly_initialize(padapter); -#endif /* CONFIG_BT_COEXIST */ - #ifdef CONFIG_PM #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) if (dvobj_to_pwrctl(dvobj)->bSupportRemoteWakeup) { @@ -1357,7 +1356,7 @@ static void rtw_usb_primary_adapter_deinit(_adapter *padapter) rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); #ifdef CONFIG_AP_MODE - if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { free_mlme_ap_info(padapter); #ifdef CONFIG_HOSTAPD_MLME hostapd_mode_unload(padapter); @@ -1525,7 +1524,7 @@ static void rtw_dev_remove(struct usb_interface *pusb_intf) /*else { - padapter->HalData->hw_init_completed = _FALSE; + rtw_set_hw_init_completed(padapter, _FALSE); }*/ diff --git a/os_dep/linux/usb_ops_linux.c b/os_dep/linux/usb_ops_linux.c index f3d64e5..20af2be 100644 --- a/os_dep/linux/usb_ops_linux.c +++ b/os_dep/linux/usb_ops_linux.c @@ -37,6 +37,13 @@ int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 inde u8 *pIo_buf; int vendorreq_times = 0; +#if (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)) +#define REG_ON_SEC 0x00 +#define REG_OFF_SEC 0x01 +#define REG_LOCAL_SEC 0x02 + u8 current_reg_sec = REG_LOCAL_SEC; +#endif + #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE u8 *tmp_buf; #else /* use stack memory */ @@ -57,7 +64,7 @@ int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 inde } #ifdef CONFIG_USB_VENDOR_REQ_MUTEX - _enter_critical_mutex(&pdvobjpriv->usb_vendor_req_mutex, NULL); + _enter_critical_mutex_lock(&pdvobjpriv->usb_vendor_req_mutex, NULL); #endif @@ -141,6 +148,38 @@ int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 inde } +#if (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)) + if (value < 0xFE00) { + if (0x00 <= value && value <= 0xff) + current_reg_sec = REG_ON_SEC; + else if (0x1000 <= value && value <= 0x10ff) + current_reg_sec = REG_ON_SEC; + else + current_reg_sec = REG_OFF_SEC; + } else { + current_reg_sec = REG_LOCAL_SEC; + } + + if (current_reg_sec == REG_ON_SEC) { + unsigned int t_pipe = usb_sndctrlpipe(udev, 0);/* write_out */ + u8 t_reqtype = REALTEK_USB_VENQT_WRITE; + u8 t_len = 1; + u8 t_req = 0x05; + u16 t_reg = 0; + u16 t_index = 0; + + t_reg = 0x4e0; + + status = rtw_usb_control_msg(udev, t_pipe, t_req, t_reqtype, t_reg, t_index, pIo_buf, t_len, RTW_USB_CONTROL_MSG_TIMEOUT); + + if (status == t_len) + rtw_reset_continual_io_error(pdvobjpriv); + else + RTW_INFO("reg 0x%x, usb %s %u fail, status:%d\n", t_reg, "write" , t_len, status); + + } +#endif + /* release IO memory used by vendorreq */ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE rtw_mfree(tmp_buf, tmp_buflen); diff --git a/os_dep/linux/wifi_regd.c b/os_dep/linux/wifi_regd.c index 745a9fe..c710b25 100644 --- a/os_dep/linux/wifi_regd.c +++ b/os_dep/linux/wifi_regd.c @@ -155,7 +155,7 @@ static void _rtw_reg_apply_beaconing_flags(struct wiphy *wiphy, u32 bandwidth = 0; int r; - for (band = 0; band < IEEE80211_NUM_BANDS; band++) { + for (band = 0; band < NUM_NL80211_BANDS; band++) { if (!wiphy->bands[band]) continue; @@ -278,14 +278,10 @@ static void _rtw_reg_apply_radar_flags(struct wiphy *wiphy) #endif ) { ch->flags |= IEEE80211_CHAN_RADAR; - #ifdef CONFIG_CENTOS_7 - ch->flags |= IEEE80211_CHAN_NO_IR; + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + ch->flags |= (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN); #else - #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) - ch->flags |= (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN); - #else - ch->flags |= IEEE80211_CHAN_NO_IR; - #endif + ch->flags |= IEEE80211_CHAN_NO_IR; #endif } #endif /* CONFIG_DFS */ @@ -351,14 +347,10 @@ static void _rtw_reg_apply_flags(struct wiphy *wiphy) && rtw_odm_dfs_domain_unknown(wiphy_to_adapter(wiphy)) #endif ) { - #ifdef CONFIG_CENTOS_7 - ch->flags = IEEE80211_CHAN_NO_IR; + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + ch->flags = (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN); #else - #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) - ch->flags = (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN); - #else - ch->flags = IEEE80211_CHAN_NO_IR; - #endif + ch->flags = IEEE80211_CHAN_NO_IR; #endif } else ch->flags = 0; @@ -505,20 +497,14 @@ static void _rtw_regd_init_wiphy(struct rtw_regulatory *reg, struct wiphy *wiphy wiphy->reg_notifier = rtw_reg_notifier; -#ifdef CONFIG_CENTOS_7 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY; + wiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY; + wiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS; +#else wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG; wiphy->regulatory_flags &= ~REGULATORY_STRICT_REG; wiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS; -#else - #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) - wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY; - wiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY; - wiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS; - #else - wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG; - wiphy->regulatory_flags &= ~REGULATORY_STRICT_REG; - wiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS; - #endif #endif regd = _rtw_regdomain_select(reg); diff --git a/os_dep/linux/xmit_linux.c b/os_dep/linux/xmit_linux.c index aeef418..6ddb0fe 100644 --- a/os_dep/linux/xmit_linux.c +++ b/os_dep/linux/xmit_linux.c @@ -195,6 +195,12 @@ static inline bool rtw_os_need_wake_queue(_adapter *padapter, u16 qidx) if (padapter->registrypriv.wifi_spec) { if (pxmitpriv->hwxmits[qidx].accnt < WMM_XMIT_THRESHOLD) return _TRUE; +#ifdef DBG_CONFIG_ERROR_DETECT +#ifdef DBG_CONFIG_ERROR_RESET + } else if (rtw_hal_sreset_inprogress(padapter) == _TRUE) { + return _FALSE; +#endif/* #ifdef DBG_CONFIG_ERROR_RESET */ +#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */ } else { #ifdef CONFIG_MCC_MODE if (MCC_EN(padapter)) { @@ -398,9 +404,9 @@ int rtw_mlcst2unicst(_adapter *padapter, struct sk_buff *skb) } /* avoid come from STA1 and send back STA1 */ - if (_rtw_memcmp(psta->hwaddr, &skb->data[6], 6) == _TRUE - || _rtw_memcmp(psta->hwaddr, null_addr, 6) == _TRUE - || _rtw_memcmp(psta->hwaddr, bc_addr, 6) == _TRUE + if (_rtw_memcmp(psta->cmn.mac_addr, &skb->data[6], 6) == _TRUE + || _rtw_memcmp(psta->cmn.mac_addr, null_addr, 6) == _TRUE + || _rtw_memcmp(psta->cmn.mac_addr, bc_addr, 6) == _TRUE ) { DBG_COUNTER(padapter->tx_logs.os_tx_m2u_ignore_self); continue; @@ -411,7 +417,7 @@ int rtw_mlcst2unicst(_adapter *padapter, struct sk_buff *skb) newskb = rtw_skb_copy(skb); if (newskb) { - _rtw_memcpy(newskb->data, psta->hwaddr, 6); + _rtw_memcpy(newskb->data, psta->cmn.mac_addr, 6); res = rtw_xmit(padapter, &newskb); if (res < 0) { DBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry_err_xmit); @@ -466,7 +472,7 @@ int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) #ifdef CONFIG_TX_MCAST2UNI if (!rtw_mc2u_disable - && check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE + && MLME_IS_AP(padapter) && (IP_MCAST_MAC(pkt->data) || ICMPV6_MCAST_MAC(pkt->data) #ifdef CONFIG_TX_BCAST2UNI diff --git a/os_dep/osdep_service.c b/os_dep/osdep_service.c index 86c38ee..2dca007 100644 --- a/os_dep/osdep_service.c +++ b/os_dep/osdep_service.c @@ -73,9 +73,9 @@ u32 rtw_atoi(u8 *s) } -inline u8 *_rtw_vmalloc(u32 sz) +inline void *_rtw_vmalloc(u32 sz) { - u8 *pbuf; + void *pbuf; #ifdef PLATFORM_LINUX pbuf = vmalloc(sz); #endif @@ -99,9 +99,9 @@ inline u8 *_rtw_vmalloc(u32 sz) return pbuf; } -inline u8 *_rtw_zvmalloc(u32 sz) +inline void *_rtw_zvmalloc(u32 sz) { - u8 *pbuf; + void *pbuf; #ifdef PLATFORM_LINUX pbuf = _rtw_vmalloc(sz); if (pbuf != NULL) @@ -119,7 +119,7 @@ inline u8 *_rtw_zvmalloc(u32 sz) return pbuf; } -inline void _rtw_vmfree(u8 *pbuf, u32 sz) +inline void _rtw_vmfree(void *pbuf, u32 sz) { #ifdef PLATFORM_LINUX vfree(pbuf); @@ -139,15 +139,14 @@ inline void _rtw_vmfree(u8 *pbuf, u32 sz) #endif /* DBG_MEMORY_LEAK */ } -u8 *_rtw_malloc(u32 sz) +void *_rtw_malloc(u32 sz) { - - u8 *pbuf = NULL; + void *pbuf = NULL; #ifdef PLATFORM_LINUX #ifdef RTK_DMP_PLATFORM if (sz > 0x4000) - pbuf = (u8 *)dvr_malloc(sz); + pbuf = dvr_malloc(sz); else #endif pbuf = kmalloc(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); @@ -176,12 +175,12 @@ u8 *_rtw_malloc(u32 sz) } -u8 *_rtw_zmalloc(u32 sz) +void *_rtw_zmalloc(u32 sz) { #ifdef PLATFORM_FREEBSD return malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT); #else /* PLATFORM_FREEBSD */ - u8 *pbuf = _rtw_malloc(sz); + void *pbuf = _rtw_malloc(sz); if (pbuf != NULL) { @@ -199,7 +198,7 @@ u8 *_rtw_zmalloc(u32 sz) #endif /* PLATFORM_FREEBSD */ } -void _rtw_mfree(u8 *pbuf, u32 sz) +void _rtw_mfree(void *pbuf, u32 sz) { #ifdef PLATFORM_LINUX @@ -236,8 +235,8 @@ struct sk_buff *dev_alloc_skb(unsigned int size) struct sk_buff *skb = NULL; u8 *data = NULL; - /* skb = (struct sk_buff *)_rtw_zmalloc(sizeof(struct sk_buff)); */ /* for skb->len, etc. */ - skb = (struct sk_buff *)_rtw_malloc(sizeof(struct sk_buff)); + /* skb = _rtw_zmalloc(sizeof(struct sk_buff)); */ /* for skb->len, etc. */ + skb = _rtw_malloc(sizeof(struct sk_buff)); if (!skb) goto out; data = _rtw_malloc(size); @@ -254,7 +253,7 @@ struct sk_buff *dev_alloc_skb(unsigned int size) out: return skb; nodata: - _rtw_mfree((u8 *)skb, sizeof(struct sk_buff)); + _rtw_mfree(skb, sizeof(struct sk_buff)); skb = NULL; goto out; @@ -267,7 +266,7 @@ void dev_kfree_skb_any(struct sk_buff *skb) _rtw_mfree(skb->head, 0); /* printf("%s()-%d: skb = %p\n", __FUNCTION__, __LINE__, skb); */ if (skb) - _rtw_mfree((u8 *)skb, 0); + _rtw_mfree(skb, 0); } struct sk_buff *skb_clone(const struct sk_buff *skb) { @@ -478,7 +477,7 @@ void rtw_mstat_dump(void *sel) void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz) { - static u32 update_time = 0; + static systime update_time = 0; int peak, alloc; int i; @@ -569,9 +568,9 @@ bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size) return _FALSE; } -inline u8 *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) +inline void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) { - u8 *p; + void *p; if (match_mstat_sniff_rules(flags, sz)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); @@ -587,9 +586,9 @@ inline u8 *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, c return p; } -inline u8 *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) +inline void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) { - u8 *p; + void *p; if (match_mstat_sniff_rules(flags, sz)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); @@ -605,7 +604,7 @@ inline u8 *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, return p; } -inline void dbg_rtw_vmfree(u8 *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line) +inline void dbg_rtw_vmfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line) { if (match_mstat_sniff_rules(flags, sz)) @@ -620,9 +619,9 @@ inline void dbg_rtw_vmfree(u8 *pbuf, u32 sz, const enum mstat_f flags, const cha ); } -inline u8 *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line) +inline void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line) { - u8 *p; + void *p; if (match_mstat_sniff_rules(flags, sz)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); @@ -638,9 +637,9 @@ inline u8 *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, co return p; } -inline u8 *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) +inline void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) { - u8 *p; + void *p; if (match_mstat_sniff_rules(flags, sz)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); @@ -656,7 +655,7 @@ inline u8 *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, c return p; } -inline void dbg_rtw_mfree(u8 *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line) +inline void dbg_rtw_mfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line) { if (match_mstat_sniff_rules(flags, sz)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); @@ -724,7 +723,7 @@ inline struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum ms rtw_mstat_update( flags , skb_cp ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL - , truesize + , cp_truesize ); return skb_cp; @@ -746,7 +745,7 @@ inline struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f rtw_mstat_update( flags , skb_cl ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL - , truesize + , cl_truesize ); return skb_cl; @@ -879,6 +878,50 @@ void rtw_mfree2d(void *pbuf, int h, int w, int size) rtw_mfree((u8 *)pbuf, h * sizeof(void *) + w * h * size); } +inline void rtw_os_pkt_free(_pkt *pkt) +{ +#if defined(PLATFORM_LINUX) + rtw_skb_free(pkt); +#elif defined(PLATFORM_FREEBSD) + m_freem(pkt); +#else + #error "TBD\n" +#endif +} + +inline _pkt *rtw_os_pkt_copy(_pkt *pkt) +{ +#if defined(PLATFORM_LINUX) + return rtw_skb_copy(pkt); +#elif defined(PLATFORM_FREEBSD) + return m_dup(pkt, M_NOWAIT); +#else + #error "TBD\n" +#endif +} + +inline void *rtw_os_pkt_data(_pkt *pkt) +{ +#if defined(PLATFORM_LINUX) + return pkt->data; +#elif defined(PLATFORM_FREEBSD) + return pkt->m_data; +#else + #error "TBD\n" +#endif +} + +inline u32 rtw_os_pkt_len(_pkt *pkt) +{ +#if defined(PLATFORM_LINUX) + return pkt->len; +#elif defined(PLATFORM_FREEBSD) + return pkt->m_pkthdr.len; +#else + #error "TBD\n" +#endif +} + void _rtw_memcpy(void *dst, const void *src, u32 sz) { @@ -901,7 +944,7 @@ inline void _rtw_memmove(void *dst, const void *src, u32 sz) #if defined(PLATFORM_LINUX) memmove(dst, src, sz); #else - #warning "no implementation\n" + #error "TBD\n" #endif } @@ -1061,6 +1104,83 @@ void rtw_list_insert_tail(_list *plist, _list *phead) } +inline void rtw_list_splice(_list *list, _list *head) +{ +#ifdef PLATFORM_LINUX + list_splice(list, head); +#else + #error "TBD\n" +#endif +} + +inline void rtw_list_splice_init(_list *list, _list *head) +{ +#ifdef PLATFORM_LINUX + list_splice_init(list, head); +#else + #error "TBD\n" +#endif +} + +inline void rtw_list_splice_tail(_list *list, _list *head) +{ +#ifdef PLATFORM_LINUX + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)) + if (!list_empty(list)) + __list_splice(list, head); + #else + list_splice_tail(list, head); + #endif +#else + #error "TBD\n" +#endif +} + +inline void rtw_hlist_head_init(rtw_hlist_head *h) +{ +#ifdef PLATFORM_LINUX + INIT_HLIST_HEAD(h); +#else + #error "TBD\n" +#endif +} + +inline void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h) +{ +#ifdef PLATFORM_LINUX + hlist_add_head(n, h); +#else + #error "TBD\n" +#endif +} + +inline void rtw_hlist_del(rtw_hlist_node *n) +{ +#ifdef PLATFORM_LINUX + hlist_del(n); +#else + #error "TBD\n" +#endif +} + +inline void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h) +{ +#ifdef PLATFORM_LINUX + hlist_add_head_rcu(n, h); +#else + #error "TBD\n" +#endif +} + +inline void rtw_hlist_del_rcu(rtw_hlist_node *n) +{ +#ifdef PLATFORM_LINUX + hlist_del_rcu(n); +#else + #error "TBD\n" +#endif +} + void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx) { _adapter *adapter = (_adapter *)padapter; @@ -1415,7 +1535,7 @@ u32 rtw_end_of_queue_search(_list *head, _list *plist) } -u32 rtw_get_current_time(void) +systime _rtw_get_current_time(void) { #ifdef PLATFORM_LINUX @@ -1429,27 +1549,27 @@ u32 rtw_get_current_time(void) #ifdef PLATFORM_WINDOWS LARGE_INTEGER SystemTime; NdisGetCurrentSystemTime(&SystemTime); - return (u32)(SystemTime.LowPart);/* count of 100-nanosecond intervals */ + return SystemTime.LowPart;/* count of 100-nanosecond intervals */ #endif } -inline u32 rtw_systime_to_ms(u32 systime) +inline u32 _rtw_systime_to_ms(systime stime) { #ifdef PLATFORM_LINUX - return systime * 1000 / HZ; + return jiffies_to_msecs(stime); #endif #ifdef PLATFORM_FREEBSD - return systime * 1000; + return stime * 1000; #endif #ifdef PLATFORM_WINDOWS - return systime / 10000 ; + return stime / 10000 ; #endif } -inline u32 rtw_ms_to_systime(u32 ms) +inline systime _rtw_ms_to_systime(u32 ms) { #ifdef PLATFORM_LINUX - return ms * HZ / 1000; + return msecs_to_jiffies(ms); #endif #ifdef PLATFORM_FREEBSD return ms / 1000; @@ -1459,36 +1579,40 @@ inline u32 rtw_ms_to_systime(u32 ms) #endif } -/* the input parameter start use the same unit as returned by rtw_get_current_time */ -inline s32 rtw_get_passing_time_ms(u32 start) +inline systime _rtw_us_to_systime(u32 us) { #ifdef PLATFORM_LINUX - return rtw_systime_to_ms(jiffies - start); -#endif -#ifdef PLATFORM_FREEBSD - return rtw_systime_to_ms(rtw_get_current_time()); -#endif -#ifdef PLATFORM_WINDOWS - LARGE_INTEGER SystemTime; - NdisGetCurrentSystemTime(&SystemTime); - return rtw_systime_to_ms((u32)(SystemTime.LowPart) - start) ; + return usecs_to_jiffies(us); +#else + #error "TBD\n" #endif } -inline s32 rtw_get_time_interval_ms(u32 start, u32 end) +/* the input parameter start use the same unit as returned by rtw_get_current_time */ +inline s32 _rtw_get_passing_time_ms(systime start) +{ + return _rtw_systime_to_ms(_rtw_get_current_time() - start); +} + +inline s32 _rtw_get_remaining_time_ms(systime end) +{ + return _rtw_systime_to_ms(end - _rtw_get_current_time()); +} + +inline s32 _rtw_get_time_interval_ms(systime start, systime end) +{ + return _rtw_systime_to_ms(end - start); +} + +inline bool _rtw_time_after(systime a, systime b) { #ifdef PLATFORM_LINUX - return rtw_systime_to_ms(end - start); -#endif -#ifdef PLATFORM_FREEBSD - return rtw_systime_to_ms(rtw_get_current_time()); -#endif -#ifdef PLATFORM_WINDOWS - return rtw_systime_to_ms(end - start); + return time_after(a, b); +#else + #error "TBD\n" #endif } - void rtw_sleep_schedulable(int ms) { @@ -1685,55 +1809,34 @@ void rtw_yield_os(void) } #define RTW_SUSPEND_LOCK_NAME "rtw_wifi" -#define RTW_SUSPEND_EXT_LOCK_NAME "rtw_wifi_ext" -#define RTW_SUSPEND_RX_LOCK_NAME "rtw_wifi_rx" #define RTW_SUSPEND_TRAFFIC_LOCK_NAME "rtw_wifi_traffic" #define RTW_SUSPEND_RESUME_LOCK_NAME "rtw_wifi_resume" -#define RTW_RESUME_SCAN_LOCK_NAME "rtw_wifi_scan" #ifdef CONFIG_WAKELOCK static struct wake_lock rtw_suspend_lock; -static struct wake_lock rtw_suspend_ext_lock; -static struct wake_lock rtw_suspend_rx_lock; static struct wake_lock rtw_suspend_traffic_lock; static struct wake_lock rtw_suspend_resume_lock; -static struct wake_lock rtw_resume_scan_lock; #elif defined(CONFIG_ANDROID_POWER) static android_suspend_lock_t rtw_suspend_lock = { .name = RTW_SUSPEND_LOCK_NAME }; -static android_suspend_lock_t rtw_suspend_ext_lock = { - .name = RTW_SUSPEND_EXT_LOCK_NAME -}; -static android_suspend_lock_t rtw_suspend_rx_lock = { - .name = RTW_SUSPEND_RX_LOCK_NAME -}; static android_suspend_lock_t rtw_suspend_traffic_lock = { .name = RTW_SUSPEND_TRAFFIC_LOCK_NAME }; static android_suspend_lock_t rtw_suspend_resume_lock = { .name = RTW_SUSPEND_RESUME_LOCK_NAME }; -static android_suspend_lock_t rtw_resume_scan_lock = { - .name = RTW_RESUME_SCAN_LOCK_NAME -}; #endif inline void rtw_suspend_lock_init(void) { #ifdef CONFIG_WAKELOCK wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME); - wake_lock_init(&rtw_suspend_ext_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_EXT_LOCK_NAME); - wake_lock_init(&rtw_suspend_rx_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RX_LOCK_NAME); wake_lock_init(&rtw_suspend_traffic_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_TRAFFIC_LOCK_NAME); wake_lock_init(&rtw_suspend_resume_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RESUME_LOCK_NAME); - wake_lock_init(&rtw_resume_scan_lock, WAKE_LOCK_SUSPEND, RTW_RESUME_SCAN_LOCK_NAME); #elif defined(CONFIG_ANDROID_POWER) android_init_suspend_lock(&rtw_suspend_lock); - android_init_suspend_lock(&rtw_suspend_ext_lock); - android_init_suspend_lock(&rtw_suspend_rx_lock); android_init_suspend_lock(&rtw_suspend_traffic_lock); android_init_suspend_lock(&rtw_suspend_resume_lock); - android_init_suspend_lock(&rtw_resume_scan_lock); #endif } @@ -1741,18 +1844,12 @@ inline void rtw_suspend_lock_uninit(void) { #ifdef CONFIG_WAKELOCK wake_lock_destroy(&rtw_suspend_lock); - wake_lock_destroy(&rtw_suspend_ext_lock); - wake_lock_destroy(&rtw_suspend_rx_lock); wake_lock_destroy(&rtw_suspend_traffic_lock); wake_lock_destroy(&rtw_suspend_resume_lock); - wake_lock_destroy(&rtw_resume_scan_lock); #elif defined(CONFIG_ANDROID_POWER) android_uninit_suspend_lock(&rtw_suspend_lock); - android_uninit_suspend_lock(&rtw_suspend_ext_lock); - android_uninit_suspend_lock(&rtw_suspend_rx_lock); android_uninit_suspend_lock(&rtw_suspend_traffic_lock); android_uninit_suspend_lock(&rtw_suspend_resume_lock); - android_uninit_suspend_lock(&rtw_resume_scan_lock); #endif } @@ -1817,45 +1914,42 @@ inline void rtw_lock_suspend_timeout(u32 timeout_ms) #endif } -inline void rtw_lock_ext_suspend_timeout(u32 timeout_ms) + +inline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms) { #ifdef CONFIG_WAKELOCK - wake_lock_timeout(&rtw_suspend_ext_lock, rtw_ms_to_systime(timeout_ms)); + wake_lock_timeout(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); #elif defined(CONFIG_ANDROID_POWER) - android_lock_suspend_auto_expire(&rtw_suspend_ext_lock, rtw_ms_to_systime(timeout_ms)); + android_lock_suspend_auto_expire(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); #endif - /* RTW_INFO("EXT lock timeout:%d\n", timeout_ms); */ + /* RTW_INFO("traffic lock timeout:%d\n", timeout_ms); */ } -inline void rtw_lock_rx_suspend_timeout(u32 timeout_ms) +inline void rtw_set_bit(int nr, unsigned long *addr) { -#ifdef CONFIG_WAKELOCK - wake_lock_timeout(&rtw_suspend_rx_lock, rtw_ms_to_systime(timeout_ms)); -#elif defined(CONFIG_ANDROID_POWER) - android_lock_suspend_auto_expire(&rtw_suspend_rx_lock, rtw_ms_to_systime(timeout_ms)); +#ifdef PLATFORM_LINUX + set_bit(nr, addr); +#else + #error "TBD\n"; #endif - /* RTW_INFO("RX lock timeout:%d\n", timeout_ms); */ } - -inline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms) +inline void rtw_clear_bit(int nr, unsigned long *addr) { -#ifdef CONFIG_WAKELOCK - wake_lock_timeout(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); -#elif defined(CONFIG_ANDROID_POWER) - android_lock_suspend_auto_expire(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); +#ifdef PLATFORM_LINUX + clear_bit(nr, addr); +#else + #error "TBD\n"; #endif - /* RTW_INFO("traffic lock timeout:%d\n", timeout_ms); */ } -inline void rtw_lock_resume_scan_timeout(u32 timeout_ms) +inline int rtw_test_and_clear_bit(int nr, unsigned long *addr) { -#ifdef CONFIG_WAKELOCK - wake_lock_timeout(&rtw_resume_scan_lock, rtw_ms_to_systime(timeout_ms)); -#elif defined(CONFIG_ANDROID_POWER) - android_lock_suspend_auto_expire(&rtw_resume_scan_lock, rtw_ms_to_systime(timeout_ms)); +#ifdef PLATFORM_LINUX + return test_and_clear_bit(nr, addr); +#else + #error "TBD\n"; #endif - /* RTW_INFO("resume scan lock:%d\n", timeout_ms); */ } inline void ATOMIC_SET(ATOMIC_T *v, int i) @@ -1971,6 +2065,23 @@ inline int ATOMIC_DEC_RETURN(ATOMIC_T *v) #endif } +inline bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u) +{ +#ifdef PLATFORM_LINUX +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15)) + return atomic_add_unless(v, 1, u); +#else + /* only make sure not exceed after this function */ + if (ATOMIC_INC_RETURN(v) > u) { + ATOMIC_DEC(v); + return 0; + } + return 1; +#endif +#else + #error "TBD\n" +#endif +} #ifdef PLATFORM_LINUX /* @@ -2018,12 +2129,10 @@ static int readFile(struct file *fp, char *buf, int len) return -EPERM; while (sum < len) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) && LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)) - rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) rlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos); -#endif +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos); #else rlen = fp->f_op->read(fp, buf + sum, len - sum, &fp->f_pos); #endif @@ -2721,6 +2830,167 @@ u8 map_read8(const struct map_t *map, u16 offset) return val; } +int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms) +{ + struct blacklist_ent *ent; + _list *list, *head; + u8 exist = _FALSE, timeout = _FALSE; + + enter_critical_bh(&blist->lock); + + head = &blist->queue; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + ent = LIST_CONTAINOR(list, struct blacklist_ent, list); + list = get_next(list); + + if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) { + exist = _TRUE; + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) + timeout = _TRUE; + ent->exp_time = rtw_get_current_time() + + rtw_ms_to_systime(timeout_ms); + break; + } + + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + } + } + + if (exist == _FALSE) { + ent = rtw_malloc(sizeof(struct blacklist_ent)); + if (ent) { + _rtw_memcpy(ent->addr, addr, ETH_ALEN); + ent->exp_time = rtw_get_current_time() + + rtw_ms_to_systime(timeout_ms); + rtw_list_insert_tail(&ent->list, head); + } + } + + exit_critical_bh(&blist->lock); + +exit: + return (exist == _TRUE && timeout == _FALSE) ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL); +} + +int rtw_blacklist_del(_queue *blist, const u8 *addr) +{ + struct blacklist_ent *ent = NULL; + _list *list, *head; + u8 exist = _FALSE; + + enter_critical_bh(&blist->lock); + head = &blist->queue; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + ent = LIST_CONTAINOR(list, struct blacklist_ent, list); + list = get_next(list); + + if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + exist = _TRUE; + break; + } + + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + } + } + + exit_critical_bh(&blist->lock); + +exit: + return exist == _TRUE ? _SUCCESS : RTW_ALREADY; +} + +int rtw_blacklist_search(_queue *blist, const u8 *addr) +{ + struct blacklist_ent *ent = NULL; + _list *list, *head; + u8 exist = _FALSE; + + enter_critical_bh(&blist->lock); + head = &blist->queue; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + ent = LIST_CONTAINOR(list, struct blacklist_ent, list); + list = get_next(list); + + if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) { + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + } else + exist = _TRUE; + break; + } + + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + } + } + + exit_critical_bh(&blist->lock); + +exit: + return exist; +} + +void rtw_blacklist_flush(_queue *blist) +{ + struct blacklist_ent *ent; + _list *list, *head; + _list tmp; + + _rtw_init_listhead(&tmp); + + enter_critical_bh(&blist->lock); + rtw_list_splice_init(&blist->queue, &tmp); + exit_critical_bh(&blist->lock); + + head = &tmp; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + ent = LIST_CONTAINOR(list, struct blacklist_ent, list); + list = get_next(list); + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + } +} + +void dump_blacklist(void *sel, _queue *blist, const char *title) +{ + struct blacklist_ent *ent = NULL; + _list *list, *head; + + enter_critical_bh(&blist->lock); + head = &blist->queue; + list = get_next(head); + + if (rtw_end_of_queue_search(head, list) == _FALSE) { + if (title) + RTW_PRINT_SEL(sel, "%s:\n", title); + + while (rtw_end_of_queue_search(head, list) == _FALSE) { + ent = LIST_CONTAINOR(list, struct blacklist_ent, list); + list = get_next(list); + + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) + RTW_PRINT_SEL(sel, MAC_FMT" expired\n", MAC_ARG(ent->addr)); + else + RTW_PRINT_SEL(sel, MAC_FMT" %u\n", MAC_ARG(ent->addr) + , rtw_get_remaining_time_ms(ent->exp_time)); + } + + } + exit_critical_bh(&blist->lock); +} + /** * is_null - * @@ -2809,3 +3079,44 @@ inline char alpha_to_upper(char c) c = 'A' + (c - 'a'); return c; } + +int hex2num_i(char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + return -1; +} + +int hex2byte_i(const char *hex) +{ + int a, b; + a = hex2num_i(*hex++); + if (a < 0) + return -1; + b = hex2num_i(*hex++); + if (b < 0) + return -1; + return (a << 4) | b; +} + +int hexstr2bin(const char *hex, u8 *buf, size_t len) +{ + size_t i; + int a; + const char *ipos = hex; + u8 *opos = buf; + + for (i = 0; i < len; i++) { + a = hex2byte_i(ipos); + if (a < 0) + return -1; + *opos++ = a; + ipos += 2; + } + return 0; +} + diff --git a/rtl8822b.mk b/rtl8822b.mk index f935b6c..e9f556c 100644 --- a/rtl8822b.mk +++ b/rtl8822b.mk @@ -1,20 +1,5 @@ -RTL871X := rtl8822b EXTRA_CFLAGS += -DCONFIG_RTL8822B -ifeq ($(CONFIG_USB_HCI), y) -ifeq ($(CONFIG_BT_COEXIST), n) -MODULE_NAME = 8812bu -else -MODULE_NAME = 88x2bu -endif -endif -ifeq ($(CONFIG_PCI_HCI), y) -MODULE_NAME = 88x2be -endif -ifeq ($(CONFIG_SDIO_HCI), y) -MODULE_NAME = 88x2bs -endif - ifeq ($(CONFIG_MP_INCLUDED), y) ### 8822B Default Enable VHT MP HW TX MODE ### #EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE @@ -23,21 +8,28 @@ endif _HAL_HALMAC_FILES += hal/halmac/halmac_api.o -_HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_api_88xx.o \ - hal/halmac/halmac_88xx/halmac_api_88xx_usb.o \ - hal/halmac/halmac_88xx/halmac_api_88xx_sdio.o \ - hal/halmac/halmac_88xx/halmac_api_88xx_pcie.o \ - hal/halmac/halmac_88xx/halmac_func_88xx.o \ - hal/halmac/halmac_88xx/halmac_gpio_88xx.o +_HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_bb_rf_88xx.o \ + hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.o \ + hal/halmac/halmac_88xx/halmac_common_88xx.o \ + hal/halmac/halmac_88xx/halmac_efuse_88xx.o \ + hal/halmac/halmac_88xx/halmac_flash_88xx.o \ + hal/halmac/halmac_88xx/halmac_fw_88xx.o \ + hal/halmac/halmac_88xx/halmac_gpio_88xx.o \ + hal/halmac/halmac_88xx/halmac_init_88xx.o \ + hal/halmac/halmac_88xx/halmac_mimo_88xx.o \ + hal/halmac/halmac_88xx/halmac_pcie_88xx.o \ + hal/halmac/halmac_88xx/halmac_sdio_88xx.o \ + hal/halmac/halmac_88xx/halmac_usb_88xx.o -_HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.o \ - hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.o +_HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.o \ + hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.o \ + hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.o \ + hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.o \ + hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.o \ + hal/halmac/halmac_88xx/halmac_8822b/halmac_phy_8822b.o \ + hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.o \ + hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.o \ + hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.o _HAL_INTFS_FILES += hal/hal_halmac.o @@ -82,4 +74,10 @@ _HAL_INTFS_FILES += hal/rtl8822b/$(HCI_NAME)/rtl8822bs_halinit.o \ _HAL_INTFS_FILES +=hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.o endif -_HAL_INTFS_FILES += $(_HAL_HALMAC_FILES) \ No newline at end of file +_HAL_INTFS_FILES += $(_HAL_HALMAC_FILES) + +_BTC_FILES += hal/btc/halbtc8822bwifionly.o +ifeq ($(CONFIG_BT_COEXIST), y) +_BTC_FILES += hal/btc/halbtc8822b1ant.o \ + hal/btc/halbtc8822b2ant.o +endif \ No newline at end of file From 6b52ad73008a01b4c174bae5d0ed8945b0872c4e Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Sat, 6 Oct 2018 13:14:29 +0200 Subject: [PATCH 10/48] won't compile with debug disabled, reduced default logging level --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index f1bbc8d..a6bc303 100644 --- a/Makefile +++ b/Makefile @@ -77,10 +77,10 @@ CONFIG_RTW_IPCAM_APPLICATION = n CONFIG_RTW_REPEATER_SON = n CONFIG_RTW_WIFI_HAL = y ########################## Debug ########################### -CONFIG_RTW_DEBUG = n +CONFIG_RTW_DEBUG = y # default log level is _DRV_INFO_ = 4, # please refer to "How_to_set_driver_debug_log_level.doc" to set the available level. -CONFIG_RTW_LOG_LEVEL = 4 +CONFIG_RTW_LOG_LEVEL = 1 ######################## Wake On Lan ########################## CONFIG_WOWLAN = n CONFIG_WAKEUP_TYPE = 0x7 #bit2: deauth, bit1: unicast, bit0: magic pkt. From baabab8adfcaeec04044de5e04369d014ef6deaf Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Sat, 6 Oct 2018 13:30:55 +0200 Subject: [PATCH 11/48] added devices + reduced log level to 0 --- Makefile | 2 +- include/wifi.h | 4 ++-- os_dep/linux/os_intfs.c | 6 +++++- os_dep/linux/usb_intf.c | 6 ++++++ 4 files changed, 14 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index a6bc303..60370cc 100644 --- a/Makefile +++ b/Makefile @@ -80,7 +80,7 @@ CONFIG_RTW_WIFI_HAL = y CONFIG_RTW_DEBUG = y # default log level is _DRV_INFO_ = 4, # please refer to "How_to_set_driver_debug_log_level.doc" to set the available level. -CONFIG_RTW_LOG_LEVEL = 1 +CONFIG_RTW_LOG_LEVEL = 0 ######################## Wake On Lan ########################## CONFIG_WOWLAN = n CONFIG_WAKEUP_TYPE = 0x7 #bit2: deauth, bit1: unicast, bit0: magic pkt. diff --git a/include/wifi.h b/include/wifi.h index 62d55fb..979860d 100644 --- a/include/wifi.h +++ b/include/wifi.h @@ -1027,8 +1027,8 @@ typedef enum _HT_CAP_AMPDU_DENSITY { * A-PMDU buffer sizes * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2) */ -#define IEEE80211_MIN_AMPDU_BUF 0x8 -#define IEEE80211_MAX_AMPDU_BUF 0x40 +//#define IEEE80211_MIN_AMPDU_BUF 0x8 +//#define IEEE80211_MAX_AMPDU_BUF 0x40 /* Spatial Multiplexing Power Save Modes */ diff --git a/os_dep/linux/os_intfs.c b/os_dep/linux/os_intfs.c index 21497ee..f1a93f4 100644 --- a/os_dep/linux/os_intfs.c +++ b/os_dep/linux/os_intfs.c @@ -1292,7 +1292,11 @@ unsigned int rtw_classify8021d(struct sk_buff *skb) static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) - , void *accel_priv + #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0) + , void *accel_priv + #else + , struct net_device *sb_dev + #endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) , select_queue_fallback_t fallback #endif diff --git a/os_dep/linux/usb_intf.c b/os_dep/linux/usb_intf.c index 34a36d5..7e764f3 100644 --- a/os_dep/linux/usb_intf.c +++ b/os_dep/linux/usb_intf.c @@ -237,6 +237,12 @@ static struct usb_device_id rtw_usb_id_tbl[] = { {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xB812, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Default ID for USB Single-function, WiFi only */ {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_EDIMAX, 0xB822, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, //EDX {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_EDIMAX, 0xC822, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, //EDX + {USB_DEVICE(0x0BDA, 0xB812), .driver_info = RTL8822B}, + {USB_DEVICE(0x0B05, 0x1812), .driver_info = RTL8812}, /* ASUS - Edimax */ + {USB_DEVICE(0x7392, 0xB822), .driver_info = RTL8822B}, /* Edimax - EW-7822ULC */ + {USB_DEVICE(0x0b05, 0x184c), .driver_info = RTL8822B}, /* ASUS USB AC53 */ + {USB_DEVICE(0x7392, 0xC822), .driver_info = RTL8822B}, /* Edimax - EW-7822UTC */ + {USB_DEVICE(0x2001, 0x331c), .driver_info = RTL8822B}, /* D-Link - DWA-182 Rev D */ /*=== Customer ID ===*/ {USB_DEVICE_AND_INTERFACE_INFO(0x13b1, 0x0043, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Alpha - Alpha*/ #endif /* CONFIG_RTL8822B */ From 14b4cc877fe6c7fa6f75a11ed55be9c6b2d359d0 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Sat, 6 Oct 2018 13:33:42 +0200 Subject: [PATCH 12/48] restore README --- README.md | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 README.md diff --git a/README.md b/README.md new file mode 100644 index 0000000..1a92175 --- /dev/null +++ b/README.md @@ -0,0 +1,46 @@ +**8822BU for Linux** + +Driver for 802.11ac USB Adapter with +RTL8822BU chipset +Only STA/Monitor Mode is supported, no AP. + +A few known wireless cards that use this driver include +* [Edimax EW-7822ULC](http://us.edimax.com/edimax/merchandise/merchandise_detail/data/edimax/us/wireless_adapters_ac1200_dual-band/ew-7822ulc/) +* [ASUS AC-53 NANO](https://www.asus.com/Networking/USB-AC53-Nano/) +* [D-Link DWA-182 (Revision D1 only)](http://ca.dlink.com/products/connect/wireless-ac1200-dual-band-usb-adapter/) + + +> NOTE: At least v4.7 is needed to compile this module +> sorry people with older kernels, the code is removed. +> Upon request I can work towards making it backwards compatible. + +Currently tested on X86_64 and ARM platform(s) **only**, +cross compile possible. + +For compiling type +`make` +in source dir + +To install the firmware files +`sudo make install` + + +To Unload driver you may need to disconnect the device + +If the driver fails building consult your distro how to +install the kernel sources and build an external module. + + +**NOTES** +This driver allows use of wpa_supplicant by using the nl80211 driver +`wpa_supplicant -Dnl80211` + +If installing on Rasberry Pi or other "armv71" devices, edit the Makefile and set `CONFIG_PLATFORM_ARM_RPI = y` and `CONFIG_PLATFORM_I386_PC = n` + +**STATUS** +Driver works fine (some sort of) +Most of the work is done is cleaning the driver and make this mess **readable** for conversion. +Updates for wireless-ext/cfg80211 are not accepted. + + +**BUGS** From 2bc4859e5e776f14dfc6038de839330c954650b6 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Sat, 6 Oct 2018 13:36:56 +0200 Subject: [PATCH 13/48] track new files in new driver version - ignore .o files --- .cache.mk | 70 + core/mesh/rtw_mesh.c | 3630 +++ core/mesh/rtw_mesh.h | 506 + core/mesh/rtw_mesh_hwmp.c | 1570 ++ core/mesh/rtw_mesh_hwmp.h | 60 + core/mesh/rtw_mesh_pathtbl.c | 1082 + core/mesh/rtw_mesh_pathtbl.h | 193 + core/rtw_rm.c | 2493 ++ core/rtw_rm_fsm.c | 998 + core/rtw_rson.c | 595 + hal/hal_dm_acs.c | 554 + hal/hal_dm_acs.h | 167 + .../halmac_8822b/halmac_cfg_wmac_8822b.c | 168 + .../halmac_8822b/halmac_cfg_wmac_8822b.h | 40 + .../halmac_8822b/halmac_common_8822b.c | 168 + .../halmac_8822b/halmac_common_8822b.h | 36 + .../halmac_8822b/halmac_init_8822b.c | 724 + .../halmac_8822b/halmac_init_8822b.h | 37 + .../halmac_8822b/halmac_pcie_8822b.c | 214 + .../halmac_8822b/halmac_pcie_8822b.h | 42 + .../halmac_8822b/halmac_phy_8822b.c | 150 + .../halmac_8822b/halmac_pwr_seq_8822b.c | 914 + .../halmac_8822b/halmac_pwr_seq_8822b.h | 40 + .../halmac_8822b/halmac_sdio_8822b.c | 868 + .../halmac_8822b/halmac_sdio_8822b.h | 66 + .../halmac_8822b/halmac_usb_8822b.c | 159 + .../halmac_8822b/halmac_usb_8822b.h | 42 + hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c | 392 + hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h | 57 + hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c | 1168 + hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h | 123 + hal/halmac/halmac_88xx/halmac_common_88xx.c | 2858 ++ hal/halmac/halmac_88xx/halmac_common_88xx.h | 155 + hal/halmac/halmac_88xx/halmac_efuse_88xx.c | 1902 ++ hal/halmac/halmac_88xx/halmac_efuse_88xx.h | 105 + hal/halmac/halmac_88xx/halmac_flash_88xx.c | 316 + hal/halmac/halmac_88xx/halmac_flash_88xx.h | 39 + hal/halmac/halmac_88xx/halmac_fw_88xx.c | 1134 + hal/halmac/halmac_88xx/halmac_fw_88xx.h | 61 + hal/halmac/halmac_88xx/halmac_init_88xx.c | 1081 + hal/halmac/halmac_88xx/halmac_init_88xx.h | 74 + hal/halmac/halmac_88xx/halmac_mimo_88xx.c | 876 + hal/halmac/halmac_88xx/halmac_mimo_88xx.h | 83 + hal/halmac/halmac_88xx/halmac_pcie_88xx.c | 543 + hal/halmac/halmac_88xx/halmac_pcie_88xx.h | 102 + hal/halmac/halmac_88xx/halmac_sdio_88xx.c | 892 + hal/halmac/halmac_88xx/halmac_sdio_88xx.h | 79 + hal/halmac/halmac_88xx/halmac_usb_88xx.c | 533 + hal/halmac/halmac_88xx/halmac_usb_88xx.h | 87 + hal/halmac/halmac_bit_8822c.h | 21816 ++++++++++++++++ hal/halmac/halmac_reg_8822c.h | 875 + hal/halmac/halmac_state_machine.h | 157 + hal/halmac/halmac_tx_desc_buffer_ap.h | 1078 + hal/halmac/halmac_tx_desc_buffer_chip.h | 509 + hal/halmac/halmac_tx_desc_buffer_nic.h | 491 + hal/halmac/halmac_tx_desc_ie_ap.h | 1005 + hal/halmac/halmac_tx_desc_ie_chip.h | 438 + hal/halmac/halmac_tx_desc_ie_nic.h | 450 + hal/led/hal_led.c | 254 + hal/phydm/halrf/halrf_powertracking.c | 159 + hal/phydm/halrf/halrf_powertracking.h | 50 + hal/phydm/halrf/halrf_psd.c | 321 + hal/phydm/halrf/halrf_psd.h | 60 + hal/phydm/halrf/halrf_txgapcal.c | 303 + hal/phydm/halrf/halrf_txgapcal.h | 29 + hal/phydm/phydm_api.c | 1424 + hal/phydm/phydm_api.h | 250 + hal/phydm/phydm_auto_dbg.c | 682 + hal/phydm/phydm_auto_dbg.h | 124 + hal/phydm/phydm_cck_pd.c | 471 + hal/phydm/phydm_cck_pd.h | 94 + hal/phydm/phydm_features_ap.h | 131 + hal/phydm/phydm_features_ce.h | 132 + hal/phydm/phydm_features_win.h | 120 + hal/phydm/phydm_math_lib.c | 179 + hal/phydm/phydm_math_lib.h | 87 + hal/phydm/phydm_phystatus.c | 2554 ++ hal/phydm/phydm_phystatus.h | 1083 + hal/phydm/phydm_pow_train.c | 228 + hal/phydm/phydm_pow_train.h | 86 + hal/phydm/phydm_primary_cca.c | 730 + hal/phydm/phydm_primary_cca.h | 126 + hal/phydm/phydm_regtable.h | 563 + hal/phydm/phydm_rssi_monitor.c | 450 + hal/phydm/phydm_rssi_monitor.h | 75 + hal/phydm/phydm_smt_ant.c | 2228 ++ hal/phydm/phydm_smt_ant.h | 249 + hal/phydm/phydm_soml.c | 862 + hal/phydm/phydm_soml.h | 254 + include/cmn_info/rtw_sta_info.h | 253 + include/rtw_rm.h | 88 + include/rtw_rm_fsm.h | 389 + include/rtw_rson.h | 61 + os_dep/linux/rhashtable.c | 844 + os_dep/linux/rhashtable.h | 827 + os_dep/linux/rtw_rhashtable.c | 74 + os_dep/linux/rtw_rhashtable.h | 55 + platform/platform_aml_s905_sdio.c | 54 + platform/platform_aml_s905_sdio.h | 28 + platform/platform_hisilicon_hi3798_sdio.c | 110 + platform/platform_hisilicon_hi3798_sdio.h | 28 + platform/platform_zte_zx296716_sdio.c | 53 + platform/platform_zte_zx296716_sdio.h | 25 + 103 files changed, 72312 insertions(+) create mode 100644 .cache.mk create mode 100644 core/mesh/rtw_mesh.c create mode 100644 core/mesh/rtw_mesh.h create mode 100644 core/mesh/rtw_mesh_hwmp.c create mode 100644 core/mesh/rtw_mesh_hwmp.h create mode 100644 core/mesh/rtw_mesh_pathtbl.c create mode 100644 core/mesh/rtw_mesh_pathtbl.h create mode 100644 core/rtw_rm.c create mode 100644 core/rtw_rm_fsm.c create mode 100644 core/rtw_rson.c create mode 100644 hal/hal_dm_acs.c create mode 100644 hal/hal_dm_acs.h create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.c create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.h create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.c create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.h create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.c create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.h create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.c create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.h create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_phy_8822b.c create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.c create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.h create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.c create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.h create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.c create mode 100644 hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.h create mode 100644 hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_common_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_common_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_efuse_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_efuse_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_flash_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_flash_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_fw_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_fw_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_init_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_init_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_mimo_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_mimo_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_pcie_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_pcie_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_sdio_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_sdio_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_usb_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_usb_88xx.h create mode 100644 hal/halmac/halmac_bit_8822c.h create mode 100644 hal/halmac/halmac_reg_8822c.h create mode 100644 hal/halmac/halmac_state_machine.h create mode 100644 hal/halmac/halmac_tx_desc_buffer_ap.h create mode 100644 hal/halmac/halmac_tx_desc_buffer_chip.h create mode 100644 hal/halmac/halmac_tx_desc_buffer_nic.h create mode 100644 hal/halmac/halmac_tx_desc_ie_ap.h create mode 100644 hal/halmac/halmac_tx_desc_ie_chip.h create mode 100644 hal/halmac/halmac_tx_desc_ie_nic.h create mode 100644 hal/led/hal_led.c create mode 100644 hal/phydm/halrf/halrf_powertracking.c create mode 100644 hal/phydm/halrf/halrf_powertracking.h create mode 100644 hal/phydm/halrf/halrf_psd.c create mode 100644 hal/phydm/halrf/halrf_psd.h create mode 100644 hal/phydm/halrf/halrf_txgapcal.c create mode 100644 hal/phydm/halrf/halrf_txgapcal.h create mode 100644 hal/phydm/phydm_api.c create mode 100644 hal/phydm/phydm_api.h create mode 100644 hal/phydm/phydm_auto_dbg.c create mode 100644 hal/phydm/phydm_auto_dbg.h create mode 100644 hal/phydm/phydm_cck_pd.c create mode 100644 hal/phydm/phydm_cck_pd.h create mode 100644 hal/phydm/phydm_features_ap.h create mode 100644 hal/phydm/phydm_features_ce.h create mode 100644 hal/phydm/phydm_features_win.h create mode 100644 hal/phydm/phydm_math_lib.c create mode 100644 hal/phydm/phydm_math_lib.h create mode 100644 hal/phydm/phydm_phystatus.c create mode 100644 hal/phydm/phydm_phystatus.h create mode 100644 hal/phydm/phydm_pow_train.c create mode 100644 hal/phydm/phydm_pow_train.h create mode 100644 hal/phydm/phydm_primary_cca.c create mode 100644 hal/phydm/phydm_primary_cca.h create mode 100644 hal/phydm/phydm_regtable.h create mode 100644 hal/phydm/phydm_rssi_monitor.c create mode 100644 hal/phydm/phydm_rssi_monitor.h create mode 100644 hal/phydm/phydm_smt_ant.c create mode 100644 hal/phydm/phydm_smt_ant.h create mode 100644 hal/phydm/phydm_soml.c create mode 100644 hal/phydm/phydm_soml.h create mode 100644 include/cmn_info/rtw_sta_info.h create mode 100644 include/rtw_rm.h create mode 100644 include/rtw_rm_fsm.h create mode 100644 include/rtw_rson.h create mode 100644 os_dep/linux/rhashtable.c create mode 100644 os_dep/linux/rhashtable.h create mode 100644 os_dep/linux/rtw_rhashtable.c create mode 100644 os_dep/linux/rtw_rhashtable.h create mode 100644 platform/platform_aml_s905_sdio.c create mode 100644 platform/platform_aml_s905_sdio.h create mode 100644 platform/platform_hisilicon_hi3798_sdio.c create mode 100644 platform/platform_hisilicon_hi3798_sdio.h create mode 100644 platform/platform_zte_zx296716_sdio.c create mode 100644 platform/platform_zte_zx296716_sdio.h diff --git a/.cache.mk b/.cache.mk new file mode 100644 index 0000000..18907ce --- /dev/null +++ b/.cache.mk @@ -0,0 +1,70 @@ +__cached_gcc_-v_2>&1_|_grep_-q_"clang_version"_&&_echo_clang_||_echo_gcc := gcc +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-mretpoline-external-thunk_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mretpoline-external-thunk";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-mindirect-branch_thunk-extern_-mindirect-branch-register_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mindirect-branch_thunk-extern_-mindirect-branch-register";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mindirect-branch=thunk-extern -mindirect-branch-register +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-PIE";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-PIE +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-fno-PIE_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-PIE";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-PIE +__cached_/bin/sh_./scripts/gcc-goto.sh_gcc_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE := y +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-fno-tree-loop-im_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-tree-loop-im";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-tree-loop-im +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-Wmaybe-uninitialized_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-maybe-uninitialized";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-maybe-uninitialized +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO__-mpreferred-stack-boundary_4_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-mpreferred-stack-boundary_4";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mpreferred-stack-boundary=4 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO__-m16_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-m16";_else_echo_"_-m32_-Wa_./arch/x86/boot/code16gcc.h";_fi;_rm_-f_"_TMP"_"_TMPO" := -m16 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-m16_-g_-Os_-DDISABLE_BRANCH_PROFILING_-Wall_-Wstrict-prototypes_-march_i386_-mregparm_3_-fno-strict-aliasing_-fomit-frame-pointer_-fno-pic_-mno-mmx_-mno-sse__-ffreestanding_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-ffreestanding";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -ffreestanding +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-m16_-g_-Os_-DDISABLE_BRANCH_PROFILING_-Wall_-Wstrict-prototypes_-march_i386_-mregparm_3_-fno-strict-aliasing_-fomit-frame-pointer_-fno-pic_-mno-mmx_-mno-sse_-ffreestanding__-fno-stack-protector_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-fno-stack-protector";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-stack-protector +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-m16_-g_-Os_-DDISABLE_BRANCH_PROFILING_-Wall_-Wstrict-prototypes_-march_i386_-mregparm_3_-fno-strict-aliasing_-fomit-frame-pointer_-fno-pic_-mno-mmx_-mno-sse_-ffreestanding_-fno-stack-protector__-mpreferred-stack-boundary_2_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-mpreferred-stack-boundary_2";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mpreferred-stack-boundary=2 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mno-avx";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mno-avx +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-falign-jumps_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -falign-jumps=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-falign-loops_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -falign-loops=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mno-80387";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mno-80387 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mno-fp-ret-in-387";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mno-fp-ret-in-387 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mpreferred-stack-boundary_3";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mpreferred-stack-boundary=3 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mskip-rax-setup";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mskip-rax-setup +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-mtune_skylake_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mtune_skylake";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mtune=skylake +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-march_skylake";_else_echo_"-mtune_skylake";_fi;_rm_-f_"_TMP"_"_TMPO" := -march=skylake +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-funit-at-a-time";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -funit-at-a-time +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time__-mfentry_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"y";_else_echo_"n";_fi;_rm_-f_"_TMP"_"_TMPO" := y +__cached_/bin/sh_./scripts/gcc-version.sh_-p_gcc := 080101 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_".cfi_startproc_n.cfi_rel_offset_rsp_0_n.cfi_endproc"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_CFI_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_CFI=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_".cfi_startproc_n.cfi_signal_frame_n.cfi_endproc"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_CFI_SIGNAL_FRAME_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_CFI_SIGNAL_FRAME=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_".cfi_sections_.debug_frame"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_CFI_SECTIONS_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_CFI_SECTIONS=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"fxsaveq__%rax_"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_FXSAVEQ_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_FXSAVEQ=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"pshufb_%xmm0_%xmm0"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_SSSE3_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_SSSE3=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"crc32l_%eax_%eax"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_CRC32_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_CRC32=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"vxorps_%ymm0_%ymm1_%ymm2"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_AVX_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_AVX=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"vpbroadcastb_%xmm0_%ymm1"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_AVX2_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_AVX2=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"vpmovm2b_%k1_%zmm5"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_AVX512_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_AVX512=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"sha1msg1_%xmm0_%xmm1"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_SHA1_NI_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_SHA1_NI=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"sha256msg1_%xmm0_%xmm1"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_SHA256_NI_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_SHA256_NI=1 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___ld_-m_elf_x86_64__-z_max-page-size_0x200000_-v__>/dev/null_2>&1;_then_echo_"_-z_max-page-size_0x200000";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -z max-page-size=0x200000 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-delete-null-pointer-checks";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-delete-null-pointer-checks +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wframe-address_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-frame-address";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-frame-address +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wformat-truncation_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-format-truncation";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-format-truncation +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wformat-overflow_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-format-overflow";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-format-overflow +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wint-in-bool-context_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-int-in-bool-context";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-int-in-bool-context +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_-Wmaybe-uninitialized_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-maybe-uninitialized";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-maybe-uninitialized +__cached_/bin/sh_./scripts/gcc-version.sh_gcc := 0801 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"--param_allow-store-data-races_0";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := --param=allow-store-data-races=0 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wframe-larger-than_2048";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wframe-larger-than=2048 +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fstack-protector";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fstack-protector +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fstack-protector-strong";_else_echo_"-fstack-protector";_fi;_rm_-f_"_TMP"_"_TMPO" := -fstack-protector-strong +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wunused-but-set-variable_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-unused-but-set-variable";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-unused-but-set-variable +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wunused-const-variable_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-unused-const-variable";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-unused-const-variable +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable__-fno-var-tracking-assignments_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-fno-var-tracking-assignments";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-var-tracking-assignments +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments__-mfentry_-DCC_USING_FENTRY_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-mfentry_-DCC_USING_FENTRY";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mfentry -DCC_USING_FENTRY +__cached_gcc_-print-file-name_include := /usr/lib/gcc/x86_64-pc-linux-gnu/8.1.1/include +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wdeclaration-after-statement";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wdeclaration-after-statement +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wpointer-sign_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-pointer-sign";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-pointer-sign +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-strict-overflow";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-strict-overflow +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-merge-all-constants";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-merge-all-constants +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fmerge-constants";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fmerge-constants +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-stack-check";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-stack-check +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fconserve-stack";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fconserve-stack +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Werror_implicit-int";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Werror=implicit-int +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-Werror_strict-prototypes_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Werror_strict-prototypes";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Werror=strict-prototypes +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-Werror_strict-prototypes_-Werror_date-time_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Werror_date-time";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Werror=date-time +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-Werror_strict-prototypes_-Werror_date-time_-Werror_incompatible-pointer-types_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Werror_incompatible-pointer-types";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Werror=incompatible-pointer-types +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-Werror_strict-prototypes_-Werror_date-time_-Werror_incompatible-pointer-types_-Werror_designated-init_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Werror_designated-init";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Werror=designated-init +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-Werror_strict-prototypes_-Werror_date-time_-Werror_incompatible-pointer-types_-Werror_designated-init_-fmacro-prefix-map_./__-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fmacro-prefix-map_./_";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fmacro-prefix-map=./= +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___ar_rcD_"_TMP"__>/dev/null_2>&1;_then_echo_"D";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := D +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-Werror_strict-prototypes_-Werror_date-time_-Werror_incompatible-pointer-types_-Werror_designated-init_-fmacro-prefix-map_./__-Wpacked-not-aligned_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-packed-not-aligned";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-packed-not-aligned +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___ld_-m_elf_x86_64_-z_max-page-size_0x200000__--build-id_-v__>/dev/null_2>&1;_then_echo_"_--build-id";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := --build-id +__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___ld_-m_elf_x86_64_-z_max-page-size_0x200000__-X_-v__>/dev/null_2>&1;_then_echo_"_-X";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -X diff --git a/core/mesh/rtw_mesh.c b/core/mesh/rtw_mesh.c new file mode 100644 index 0000000..1c33616 --- /dev/null +++ b/core/mesh/rtw_mesh.c @@ -0,0 +1,3630 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_MESH_C_ + +#ifdef CONFIG_RTW_MESH +#include + +const char *_rtw_mesh_plink_str[] = { + "UNKNOWN", + "LISTEN", + "OPN_SNT", + "OPN_RCVD", + "CNF_RCVD", + "ESTAB", + "HOLDING", + "BLOCKED", +}; + +const char *_rtw_mesh_ps_str[] = { + "UNKNOWN", + "ACTIVE", + "LSLEEP", + "DSLEEP", +}; + +const char *_action_self_protected_str[] = { + "ACT_SELF_PROTECTED_RSVD", + "MESH_OPEN", + "MESH_CONF", + "MESH_CLOSE", + "MESH_GK_INFORM", + "MESH_GK_ACK", +}; + +inline u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len) +{ + return rtw_set_ie(buf, WLAN_EID_MESH_ID, id_len, mesh_id, buf_len); +} + +inline u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len + , u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto + , u8 num_of_peerings, bool cto_mgate, bool cto_as + , bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding + , bool mbca_en, bool tbtt_adj, bool ps_level) +{ + + u8 conf[7] = {0}; + + SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(conf, path_sel_proto); + SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(conf, path_sel_metric); + SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(conf, congest_ctl_mode); + SET_MESH_CONF_ELE_SYNC_METHOD_ID(conf, sync_method); + SET_MESH_CONF_ELE_AUTH_PROTO_ID(conf, auth_proto); + + SET_MESH_CONF_ELE_CTO_MGATE(conf, cto_mgate); + SET_MESH_CONF_ELE_NUM_OF_PEERINGS(conf, num_of_peerings); + SET_MESH_CONF_ELE_CTO_AS(conf, cto_as); + + SET_MESH_CONF_ELE_ACCEPT_PEERINGS(conf, accept_peerings); + SET_MESH_CONF_ELE_MCCA_SUP(conf, mcca_sup); + SET_MESH_CONF_ELE_MCCA_EN(conf, mcca_en); + SET_MESH_CONF_ELE_FORWARDING(conf, forwarding); + SET_MESH_CONF_ELE_MBCA_EN(conf, mbca_en); + SET_MESH_CONF_ELE_TBTT_ADJ(conf, tbtt_adj); + SET_MESH_CONF_ELE_PS_LEVEL(conf, ps_level); + + return rtw_set_ie(buf, WLAN_EID_MESH_CONFIG, 7, conf, buf_len); +} + +inline u8 *rtw_set_ie_mpm(u8 *buf, u32 *buf_len + , u8 proto_id, u16 llid, u16 *plid, u16 *reason, u8 *chosen_pmk) +{ + u8 data[24] = {0}; + u8 *pos = data; + + RTW_PUT_LE16(pos, proto_id); + pos += 2; + + RTW_PUT_LE16(pos, llid); + pos += 2; + + if (plid) { + RTW_PUT_LE16(pos, *plid); + pos += 2; + } + + if (reason) { + RTW_PUT_LE16(pos, *reason); + pos += 2; + } + + if (chosen_pmk) { + _rtw_memcpy(pos, chosen_pmk, 16); + pos += 16; + } + + return rtw_set_ie(buf, WLAN_EID_MPM, pos - data, data, buf_len); +} + +bool rtw_bss_is_forwarding(WLAN_BSSID_EX *bss) +{ + u8 *ie; + int ie_len; + bool ret = 0; + + ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, + BSS_EX_TLV_IES_LEN(bss)); + if (!ie || ie_len != 7) + goto exit; + + ret = GET_MESH_CONF_ELE_FORWARDING(ie + 2); + +exit: + return ret; +} + +bool rtw_bss_is_cto_mgate(WLAN_BSSID_EX *bss) +{ + u8 *ie; + int ie_len; + bool ret = 0; + + ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, + BSS_EX_TLV_IES_LEN(bss)); + if (!ie || ie_len != 7) + goto exit; + + ret = GET_MESH_CONF_ELE_CTO_MGATE(ie + 2); + +exit: + return ret; +} + +int rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b) +{ + int ret = 0; + u8 *a_mconf_ie, *b_mconf_ie; + sint a_mconf_ie_len, b_mconf_ie_len; + + if (a->InfrastructureMode != Ndis802_11_mesh) + goto exit; + a_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(a), WLAN_EID_MESH_CONFIG, &a_mconf_ie_len, BSS_EX_TLV_IES_LEN(a)); + if (!a_mconf_ie || a_mconf_ie_len != 7) + goto exit; + if (b->InfrastructureMode != Ndis802_11_mesh) + goto exit; + b_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(b), WLAN_EID_MESH_CONFIG, &b_mconf_ie_len, BSS_EX_TLV_IES_LEN(b)); + if (!b_mconf_ie || b_mconf_ie_len != 7) + goto exit; + + if (a->mesh_id.SsidLength != b->mesh_id.SsidLength + || _rtw_memcmp(a->mesh_id.Ssid, b->mesh_id.Ssid, a->mesh_id.SsidLength) == _FALSE) + goto exit; + + if (_rtw_memcmp(a_mconf_ie + 2, b_mconf_ie + 2, 5) == _FALSE) + goto exit; + + ret = 1; + +exit: + return ret; +} + +int rtw_bss_is_candidate_mesh_peer(WLAN_BSSID_EX *self, WLAN_BSSID_EX *target, u8 ch, u8 add_peer) +{ + int ret = 0; + u8 *mconf_ie; + sint mconf_ie_len; + int i, j; + + if (!rtw_bss_is_same_mbss(self, target)) + goto exit; + + if (ch && self->Configuration.DSConfig != target->Configuration.DSConfig) + goto exit; + + if (add_peer) { + /* Accept additional mesh peerings */ + mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(target), WLAN_EID_MESH_CONFIG, &mconf_ie_len, BSS_EX_TLV_IES_LEN(target)); + if (!mconf_ie || mconf_ie_len != 7) + goto exit; + if (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mconf_ie + 2) == 0) + goto exit; + } + + /* BSSBasicRateSet */ + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + if (target->SupportedRates[i] == 0) + break; + if (target->SupportedRates[i] & 0x80) { + u8 match = 0; + + if (!ch) { + /* off-channel, check target with our hardcode capability */ + if (target->Configuration.DSConfig > 14) + match = rtw_is_basic_rate_ofdm(target->SupportedRates[i]); + else + match = rtw_is_basic_rate_mix(target->SupportedRates[i]); + } else { + for (j = 0; j < NDIS_802_11_LENGTH_RATES_EX; j++) { + if (self->SupportedRates[j] == 0) + break; + if (self->SupportedRates[j] == target->SupportedRates[i]) { + match = 1; + break; + } + } + } + if (!match) + goto exit; + } + } + + + /* BSSBasicMCSSet */ + + /* 802.1X connected to AS ? */ + + ret = 1; + +exit: + return ret; +} + +#if CONFIG_RTW_MESH_PEER_BLACKLIST +int rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + return rtw_blacklist_add(&plink_ctl->peer_blacklist, addr + , mcfg->peer_sel_policy.peer_blacklist_timeout_ms); +} + +int rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + return rtw_blacklist_del(&plink_ctl->peer_blacklist, addr); +} + +int rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + return rtw_blacklist_search(&plink_ctl->peer_blacklist, addr); +} + +void rtw_mesh_peer_blacklist_flush(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + rtw_blacklist_flush(&plink_ctl->peer_blacklist); +} + +void dump_mesh_peer_blacklist(void *sel, _adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + dump_blacklist(sel, &plink_ctl->peer_blacklist, "blacklist"); +} + +void dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter) +{ + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + + RTW_PRINT_SEL(sel, "%-12s %-17s\n" + , "conf_timeout", "blacklist_timeout"); + RTW_PRINT_SEL(sel, "%12u %17u\n" + , peer_sel_policy->peer_conf_timeout_ms + , peer_sel_policy->peer_blacklist_timeout_ms); +} +#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */ + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST +u8 rtw_mesh_cto_mgate_required(_adapter *adapter) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + return mcfg->peer_sel_policy.cto_mgate_require + && !rtw_bss_is_cto_mgate(&(mlmeext->mlmext_info.network)); +} + +u8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + return !rtw_mesh_cto_mgate_required(adapter) + || (rtw_bss_is_cto_mgate(&scanned->network) + && !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress)); +} + +int rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + return rtw_blacklist_add(&plink_ctl->cto_mgate_blacklist, addr + , mcfg->peer_sel_policy.cto_mgate_blacklist_timeout_ms); +} + +int rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + return rtw_blacklist_del(&plink_ctl->cto_mgate_blacklist, addr); +} + +int rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + return rtw_blacklist_search(&plink_ctl->cto_mgate_blacklist, addr); +} + +void rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + rtw_blacklist_flush(&plink_ctl->cto_mgate_blacklist); +} + +void dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + dump_blacklist(sel, &plink_ctl->cto_mgate_blacklist, "blacklist"); +} + +void dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter) +{ + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + + RTW_PRINT_SEL(sel, "%-7s %-12s %-17s\n" + , "require", "conf_timeout", "blacklist_timeout"); + RTW_PRINT_SEL(sel, "%7u %12u %17u\n" + , peer_sel_policy->cto_mgate_require + , peer_sel_policy->cto_mgate_conf_timeout_ms + , peer_sel_policy->cto_mgate_blacklist_timeout_ms); +} + +static void rtw_mesh_cto_mgate_blacklist_chk(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + _queue *blist = &plink_ctl->cto_mgate_blacklist; + _list *list, *head; + struct blacklist_ent *ent = NULL; + struct wlan_network *scanned = NULL; + + enter_critical_bh(&blist->lock); + head = &blist->queue; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + ent = LIST_CONTAINOR(list, struct blacklist_ent, list); + list = get_next(list); + + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + continue; + } + + scanned = rtw_find_network(&adapter->mlmepriv.scanned_queue, ent->addr); + if (!scanned) + continue; + + if (rtw_bss_is_forwarding(&scanned->network)) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + } + } + + exit_critical_bh(&blist->lock); +} +#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */ + +void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct mlme_priv *mlme = &adapter->mlmepriv; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + if (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl)) + goto exit; + + if (plink_ctl->num >= RTW_MESH_MAX_PEER_CANDIDATES) + goto exit; + + /* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */ + if (plink_ctl->num >= mcfg->max_peer_links) + goto exit; + + if (rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms + || (mcfg->rssi_threshold && mcfg->rssi_threshold > scanned->network.Rssi) + || !rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1) + #if CONFIG_RTW_MACADDR_ACL + || rtw_access_ctrl(adapter, scanned->network.MacAddress) == _FALSE + #endif + || rtw_mesh_plink_get(adapter, scanned->network.MacAddress) + #if CONFIG_RTW_MESH_PEER_BLACKLIST + || rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress) + #endif + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + || !rtw_mesh_cto_mgate_network_filter(adapter, scanned) + #endif + ) + goto exit; + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev + , scanned->network.MacAddress + , BSS_EX_TLV_IES(&scanned->network) + , BSS_EX_TLV_IES_LEN(&scanned->network) + , GFP_ATOMIC + ); +#endif + +exit: + return; +} + +void rtw_mesh_peer_status_chk(_adapter *adapter) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *plink; + _list *head, *list; + struct sta_info *sta = NULL; + struct sta_priv *stapriv = &adapter->stapriv; + int stainfo_offset; +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + u8 cto_mgate, forwarding, mgate; +#endif + u8 flush; + char flush_list[NUM_STA]; + u8 flush_num = 0; + int i; + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + if (rtw_mesh_cto_mgate_required(adapter)) { + /* active scan on operating channel */ + issue_probereq_ex(adapter, &adapter->mlmepriv.cur_network.network.mesh_id, NULL, 0, 0, 0, 0); + } +#endif + + enter_critical_bh(&(plink_ctl->lock)); + + /* check established peers */ + enter_critical_bh(&stapriv->asoc_list_lock); + + head = &stapriv->asoc_list; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + sta = LIST_CONTAINOR(list, struct sta_info, asoc_list); + list = get_next(list); + + if (!sta->plink || !sta->plink->scanned) { + rtw_warn_on(1); + continue; + } + plink = sta->plink; + flush = 0; + + /* remove unsuitable peer */ + if (!rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &plink->scanned->network, 1, 0) + #if CONFIG_RTW_MACADDR_ACL + || rtw_access_ctrl(adapter, plink->addr) == _FALSE + #endif + ) { + flush = 1; + goto flush_add; + } + + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + cto_mgate = rtw_bss_is_cto_mgate(&(plink->scanned->network)); + forwarding = rtw_bss_is_forwarding(&(plink->scanned->network)); + mgate = rtw_mesh_gate_search(minfo->mesh_paths, sta->cmn.mac_addr); + + /* CTO_MGATE required, remove peer without CTO_MGATE */ + if (rtw_mesh_cto_mgate_required(adapter) && !cto_mgate) { + flush = 1; + goto flush_add; + } + + /* cto_mgate_conf status update */ + if (IS_CTO_MGATE_CONF_DISABLED(plink)) { + if (cto_mgate && !forwarding && !mgate) + SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms); + else + rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr); + } else { + /* cto_mgate_conf ongoing */ + if (cto_mgate && !forwarding && !mgate) { + if (IS_CTO_MGATE_CONF_TIMEOUT(plink)) { + rtw_mesh_cto_mgate_blacklist_add(adapter, sta->cmn.mac_addr); + + /* CTO_MGATE required, remove peering can't achieve CTO_MGATE */ + if (rtw_mesh_cto_mgate_required(adapter)) { + flush = 1; + goto flush_add; + } + } + } else { + SET_CTO_MGATE_CONF_DISABLED(plink); + rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr); + } + } + #endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */ + +flush_add: + if (flush) { + rtw_list_delete(&sta->asoc_list); + stapriv->asoc_list_cnt--; + STA_SET_MESH_PLINK(sta, NULL); + + stainfo_offset = rtw_stainfo_offset(stapriv, sta); + if (stainfo_offset_valid(stainfo_offset)) + flush_list[flush_num++] = stainfo_offset; + else + rtw_warn_on(1); + } + } + + exit_critical_bh(&stapriv->asoc_list_lock); + + /* check non-established peers */ + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + plink = &plink_ctl->ent[i]; + if (plink->valid != _TRUE || plink->plink_state == RTW_MESH_PLINK_ESTAB) + continue; + + /* remove unsuitable peer */ + if (!rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &plink->scanned->network, 1, 1) + #if CONFIG_RTW_MACADDR_ACL + || rtw_access_ctrl(adapter, plink->addr) == _FALSE + #endif + ) { + _rtw_mesh_expire_peer_ent(adapter, plink); + continue; + } + + #if CONFIG_RTW_MESH_PEER_BLACKLIST + /* peer confirm check timeout, add to black list */ + if (IS_PEER_CONF_TIMEOUT(plink)) { + rtw_mesh_peer_blacklist_add(adapter, plink->addr); + _rtw_mesh_expire_peer_ent(adapter, plink); + } + #endif + } + + exit_critical_bh(&(plink_ctl->lock)); + + for (i = 0; i < flush_num; i++) { + u8 sta_addr[ETH_ALEN]; + + sta = rtw_get_stainfo_by_offset(stapriv, flush_list[i]); + _rtw_memcpy(sta_addr, sta->cmn.mac_addr, ETH_ALEN); + + ap_free_sta(adapter, sta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _FALSE); + rtw_mesh_expire_peer(adapter, sta_addr); + } + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + /* loop cto_mgate_blacklist to remove ent according to scan_r */ + rtw_mesh_cto_mgate_blacklist_chk(adapter); +#endif + + return; +} + +#if CONFIG_RTW_MESH_OFFCH_CAND +static u8 rtw_mesh_offch_cto_mgate_required(_adapter *adapter) +{ +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct mlme_priv *mlme = &adapter->mlmepriv; + _queue *queue = &(mlme->scanned_queue); + _list *head, *pos; + struct wlan_network *scanned = NULL; + u8 ret = 0; + + if (!rtw_mesh_cto_mgate_required(adapter)) + goto exit; + + enter_critical_bh(&(mlme->scanned_queue.lock)); + + head = get_list_head(queue); + pos = get_next(head); + while (!rtw_end_of_queue_search(head, pos)) { + scanned = LIST_CONTAINOR(pos, struct wlan_network, list); + + if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms + && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi) + #if CONFIG_RTW_MACADDR_ACL + && rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE + #endif + && rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1) + && rtw_bss_is_cto_mgate(&scanned->network) + #if CONFIG_RTW_MESH_PEER_BLACKLIST + && !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress) + #endif + && !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress) + ) + break; + + pos = get_next(pos); + } + + if (rtw_end_of_queue_search(head, pos)) + ret = 1; + + exit_critical_bh(&(mlme->scanned_queue.lock)); + +exit: + return ret; +#else + return 0; +#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */ +} + +u8 rtw_mesh_offch_candidate_accepted(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + u8 ret; + + ret = MLME_IS_MESH(adapter) + && check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE + && (!plink_ctl->num || rtw_mesh_offch_cto_mgate_required(adapter)) + ; + +#ifdef CONFIG_CONCURRENT_MODE + if (ret) { + struct mi_state mstate_no_self; + + rtw_mi_status_no_self(adapter, &mstate_no_self); + if (MSTATE_STA_LD_NUM(&mstate_no_self) || MSTATE_AP_LD_NUM(&mstate_no_self) + || MSTATE_ADHOC_LD_NUM(&mstate_no_self) || MSTATE_MESH_LD_NUM(&mstate_no_self)) + ret = 0; + } +#endif + + return ret; +} + +/* + * this function is called under off channel candidate is required + * the channel with maximum candidate count is selected +*/ +u8 rtw_mesh_select_operating_ch(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct mlme_priv *mlme = &adapter->mlmepriv; + _queue *queue = &(mlme->scanned_queue); + _list *head, *pos; + _irqL irqL; + struct wlan_network *scanned = NULL; + int i; + u8 max_cand_ch = 0; + u8 max_cand_cnt = 0; + + for (i = 0; i < rfctl->max_chan_nums; i++) + rfctl->channel_set[i].mesh_candidate_cnt = 0; + + _enter_critical_bh(&(mlme->scanned_queue.lock), &irqL); + + head = get_list_head(queue); + pos = get_next(head); + while (!rtw_end_of_queue_search(head, pos)) { + scanned = LIST_CONTAINOR(pos, struct wlan_network, list); + pos = get_next(pos); + + if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms + && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi) + #if CONFIG_RTW_MACADDR_ACL + && rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE + #endif + && rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 0, 1) + #if CONFIG_RTW_MESH_PEER_BLACKLIST + && !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress) + #endif + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + && rtw_mesh_cto_mgate_network_filter(adapter, scanned) + #endif + ) { + int ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scanned->network.Configuration.DSConfig); + + if (ch_set_idx >= 0 + && !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx]) + ) { + rfctl->channel_set[ch_set_idx].mesh_candidate_cnt++; + if (max_cand_cnt < rfctl->channel_set[ch_set_idx].mesh_candidate_cnt) { + max_cand_cnt = rfctl->channel_set[ch_set_idx].mesh_candidate_cnt; + max_cand_ch = rfctl->channel_set[ch_set_idx].ChannelNum; + } + } + } + } + + _exit_critical_bh(&(mlme->scanned_queue.lock), &irqL); + + return max_cand_ch; +} +#endif /* CONFIG_RTW_MESH_OFFCH_CAND */ + +void dump_mesh_peer_sel_policy(void *sel, _adapter *adapter) +{ + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + +#if CONFIG_RTW_MESH_OFFCH_CAND +#define OFFCH_CAND_TITLE_FMT " %-17s" +#define OFFCH_CAND_VALUE_FMT " %17u" +#define OFFCH_CAND_TITLE_ARG , "offch_find_int_ms" +#define OFFCH_CAND_VALUE_ARG , peer_sel_policy->offch_find_int_ms +#else +#define OFFCH_CAND_TITLE_FMT "" +#define OFFCH_CAND_VALUE_FMT "" +#define OFFCH_CAND_TITLE_ARG +#define OFFCH_CAND_VALUE_ARG +#endif + + RTW_PRINT_SEL(sel, + "%-12s" + OFFCH_CAND_TITLE_FMT + "\n" + , "scanr_exp_ms" + OFFCH_CAND_TITLE_ARG + ); + RTW_PRINT_SEL(sel, + "%12u" + OFFCH_CAND_VALUE_FMT + "\n" + , peer_sel_policy->scanr_exp_ms + OFFCH_CAND_VALUE_ARG + ); +} + +void dump_mesh_networks(void *sel, _adapter *adapter) +{ + struct mlme_priv *mlme = &(adapter->mlmepriv); + _queue *queue = &(mlme->scanned_queue); + struct wlan_network *network; + _list *list, *head; + u8 same_mbss; + u8 candidate; + struct mesh_plink_ent *plink; + u8 blocked; + u8 established; + s32 age_ms; + u8 *mesh_conf_ie; + sint mesh_conf_ie_len; + struct wlan_network **mesh_networks; + u8 mesh_network_cnt = 0; + int i; + + mesh_networks = rtw_zvmalloc(MAX_BSS_CNT * sizeof(struct wlan_network *)); + if (!mesh_networks) + return; + + enter_critical_bh(&queue->lock); + head = get_list_head(queue); + list = get_next(head); + + while (rtw_end_of_queue_search(head, list) == _FALSE) { + network = LIST_CONTAINOR(list, struct wlan_network, list); + list = get_next(list); + + if (network->network.InfrastructureMode != Ndis802_11_mesh) + continue; + + mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG + , &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network)); + if (!mesh_conf_ie || mesh_conf_ie_len != 7) + continue; + + mesh_networks[mesh_network_cnt++] = network; + } + + exit_critical_bh(&queue->lock); + + RTW_PRINT_SEL(sel, " %-17s %-3s %-4s %-5s %-32s %-3s %-3s %-3s\n" + , "bssid", "ch", "rssi", "age", "mesh_id", "nop", "fwd", "cto"); + + + for (i = 0; i < mesh_network_cnt; i++) { + network = mesh_networks[i]; + + if (network->network.InfrastructureMode != Ndis802_11_mesh) + continue; + + mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG + , &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network)); + if (!mesh_conf_ie || mesh_conf_ie_len != 7) + continue; + + age_ms = rtw_get_passing_time_ms(network->last_scanned); + same_mbss = 0; + candidate = 0; + plink = NULL; + blocked = 0; + established = 0; + + if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) { + plink = rtw_mesh_plink_get(adapter, network->network.MacAddress); + if (plink && plink->plink_state == RTW_MESH_PLINK_ESTAB) + established = 1; + else if (plink && plink->plink_state == RTW_MESH_PLINK_BLOCKED) + blocked = 1; + else if (plink) + ; + else if (rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &network->network, 0, 1)) + candidate = 1; + else if (rtw_bss_is_same_mbss(&mlme->cur_network.network, &network->network)) + same_mbss = 1; + } + + RTW_PRINT_SEL(sel, "%c "MAC_FMT" %3d %4ld %5d %-32s %c%2u %3u %c%c \n" + , established ? 'E' : (blocked ? 'B' : (plink ? 'N' : (candidate ? 'C' : (same_mbss ? 'S' : ' ')))) + , MAC_ARG(network->network.MacAddress) + , network->network.Configuration.DSConfig + , network->network.Rssi + , age_ms < 99999 ? age_ms : 99999 + , network->network.mesh_id.Ssid + , GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mesh_conf_ie + 2) ? '+' : ' ' + , GET_MESH_CONF_ELE_NUM_OF_PEERINGS(mesh_conf_ie + 2) + , GET_MESH_CONF_ELE_FORWARDING(mesh_conf_ie + 2) + , GET_MESH_CONF_ELE_CTO_MGATE(mesh_conf_ie + 2) ? 'G' : ' ' + , GET_MESH_CONF_ELE_CTO_AS(mesh_conf_ie + 2) ? 'A' : ' ' + ); + } + + rtw_vmfree(mesh_networks, MAX_BSS_CNT * sizeof(struct wlan_network *)); +} + +int rtw_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx) +{ + const u8 *frame_body = buf + sizeof(struct rtw_ieee80211_hdr_3addr); + u16 alg; + u16 seq; + u16 status; + int ret = 0; + + alg = RTW_GET_LE16(frame_body); + if (alg != 3) + goto exit; + + seq = RTW_GET_LE16(frame_body + 2); + status = RTW_GET_LE16(frame_body + 4); + + RTW_INFO("RTW_%s:AUTH alg:0x%04x, seq:0x%04x, status:0x%04x\n" + , (tx == _TRUE) ? "Tx" : "Rx", alg, seq, status); + + ret = 1; + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + if (tx && seq == 1) + rtw_mesh_plink_set_peer_conf_timeout(adapter, GetAddr1Ptr(buf)); +#endif + +exit: + return ret; +} + +#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS +#ifdef CONFIG_RTW_MESH_AEK +static int rtw_mpm_ampe_dec(_adapter *adapter, struct mesh_plink_ent *plink + , u8 *fhead, size_t flen, u8* fbody, u8 *mic_ie, u8 *ampe_buf) +{ + int ret = _FAIL, verify_ret; + const u8 *aad[] = {adapter_mac_addr(adapter), plink->addr, fbody}; + const size_t aad_len[] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody}; + u8 *iv_crypt; + size_t iv_crypt_len = flen - (mic_ie + 2 - fhead); + + iv_crypt = rtw_malloc(iv_crypt_len); + if (!iv_crypt) + goto exit; + + _rtw_memcpy(iv_crypt, mic_ie + 2, iv_crypt_len); + + verify_ret = aes_siv_decrypt(plink->aek, iv_crypt, iv_crypt_len + , 3, aad, aad_len, ampe_buf); + + rtw_mfree(iv_crypt, iv_crypt_len); + + if (verify_ret) { + RTW_WARN("verify error, aek_valid=%u\n", plink->aek_valid); + goto exit; + } else if (*ampe_buf != WLAN_EID_AMPE) { + RTW_WARN("plaintext is not AMPE IE\n"); + goto exit; + } else if (AES_BLOCK_SIZE + 2 + *(ampe_buf + 1) > iv_crypt_len) { + RTW_WARN("plaintext AMPE IE length is not valid\n"); + goto exit; + } + + ret = _SUCCESS; + +exit: + return ret; +} + +static int rtw_mpm_ampe_enc(_adapter *adapter, struct mesh_plink_ent *plink + , u8* fbody, u8 *mic_ie, u8 *ampe_buf, bool inverse) +{ + int ret = _FAIL, protect_ret; + const u8 *aad[3]; + const size_t aad_len[3] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody}; + u8 *ampe_ie; + size_t ampe_ie_len = *(ampe_buf + 1) + 2; /* including id & len */ + + if (inverse) { + aad[0] = plink->addr; + aad[1] = adapter_mac_addr(adapter); + } else { + aad[0] = adapter_mac_addr(adapter); + aad[1] = plink->addr; + } + aad[2] = fbody; + + ampe_ie = rtw_malloc(ampe_ie_len); + if (!ampe_ie) + goto exit; + + _rtw_memcpy(ampe_ie, ampe_buf, ampe_ie_len); + + protect_ret = aes_siv_encrypt(plink->aek, ampe_ie, ampe_ie_len + , 3, aad, aad_len, mic_ie + 2); + + rtw_mfree(ampe_ie, ampe_ie_len); + + if (protect_ret) { + RTW_WARN("protect error, aek_valid=%u\n", plink->aek_valid); + goto exit; + } + + ret = _SUCCESS; + +exit: + return ret; +} +#endif /* CONFIG_RTW_MESH_AEK */ + +static int rtw_mpm_tx_ies_sync_bss(_adapter *adapter, struct mesh_plink_ent *plink + , u8 *fhead, size_t flen, u8* fbody, u8 tlv_ies_offset, u8 *mpm_ie, u8 *mic_ie + , u8 **nbuf, size_t *nlen) +{ + int ret = _FAIL; + struct mlme_priv *mlme = &(adapter->mlmepriv); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); + WLAN_BSSID_EX *network = &(mlmeinfo->network); + uint left; + u8 *pos; + + uint mpm_ielen = *(mpm_ie + 1); + u8 *fpos; + u8 *new_buf = NULL; + size_t new_len = 0; + + u8 *new_fhead; + size_t new_flen; + u8 *new_fbody; + u8 *new_mic_ie; + +#ifdef CONFIG_RTW_MESH_AEK + u8 *ampe_buf = NULL; + size_t ampe_buf_len = 0; + + /* decode */ + if (mic_ie) { + ampe_buf_len = flen - (mic_ie + 2 + AES_BLOCK_SIZE - fhead); + ampe_buf = rtw_malloc(ampe_buf_len); + if (!ampe_buf) + goto exit; + + if (rtw_mpm_ampe_dec(adapter, plink, fhead, flen, fbody, mic_ie, ampe_buf) != _SUCCESS) + goto exit; + + if (*(ampe_buf + 1) >= 68) { + _rtw_memcpy(plink->sel_pcs, ampe_buf + 2, 4); + _rtw_memcpy(plink->l_nonce, ampe_buf + 6, 32); + _rtw_memcpy(plink->p_nonce, ampe_buf + 38, 32); + } + } +#endif + + /* count for new frame length */ + new_len = sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset; + left = BSS_EX_TLV_IES_LEN(network); + pos = BSS_EX_TLV_IES(network); + while (left >= 2) { + u8 id, elen; + + id = *pos++; + elen = *pos++; + left -= 2; + + if (elen > left) + break; + + switch (id) { + case WLAN_EID_SSID: + case WLAN_EID_DS_PARAMS: + case WLAN_EID_TIM: + break; + default: + new_len += 2 + elen; + } + + left -= elen; + pos += elen; + } + new_len += mpm_ielen + 2; + if (mic_ie) + new_len += AES_BLOCK_SIZE + 2 + ampe_buf_len; + + /* alloc new frame */ + new_buf = rtw_malloc(new_len); + if (!new_buf) { + rtw_warn_on(1); + goto exit; + } + + /* build new frame */ + _rtw_memcpy(new_buf, fhead, sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset); + new_fhead = new_buf; + new_flen = new_len; + new_fbody = new_fhead + sizeof(struct rtw_ieee80211_hdr_3addr); + + fpos = new_fbody + tlv_ies_offset; + left = BSS_EX_TLV_IES_LEN(network); + pos = BSS_EX_TLV_IES(network); + while (left >= 2) { + u8 id, elen; + + id = *pos++; + elen = *pos++; + left -= 2; + + if (elen > left) + break; + + switch (id) { + case WLAN_EID_SSID: + case WLAN_EID_DS_PARAMS: + case WLAN_EID_TIM: + break; + default: + fpos = rtw_set_ie(fpos, id, elen, pos, NULL); + if (id == WLAN_EID_MESH_CONFIG) + fpos = rtw_set_ie(fpos, WLAN_EID_MPM, mpm_ielen, mpm_ie + 2, NULL); + } + + left -= elen; + pos += elen; + } + if (mic_ie) { + new_mic_ie = fpos; + *fpos++ = WLAN_EID_MIC; + *fpos++ = AES_BLOCK_SIZE; + } + +#ifdef CONFIG_RTW_MESH_AEK + /* encode */ + if (mic_ie) { + int enc_ret = rtw_mpm_ampe_enc(adapter, plink, new_fbody, new_mic_ie, ampe_buf, 0); + if (enc_ret != _SUCCESS) + goto exit; + } +#endif + + *nlen = new_len; + *nbuf = new_buf; + + ret = _SUCCESS; + +exit: + if (ret != _SUCCESS && new_buf) + rtw_mfree(new_buf, new_len); + +#ifdef CONFIG_RTW_MESH_AEK + if (ampe_buf) + rtw_mfree(ampe_buf, ampe_buf_len); +#endif + + return ret; +} +#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */ + +struct mpm_frame_info { + u8 *aid; + u16 aid_v; + u8 *pid; + u16 pid_v; + u8 *llid; + u16 llid_v; + u8 *plid; + u16 plid_v; + u8 *reason; + u16 reason_v; + u8 *chosen_pmk; +}; + +/* +* pid:0x0000 llid:0x0000 chosen_pmk:0x00000000000000000000000000000000 +* aid:0x0000 pid:0x0000 llid:0x0000 plid:0x0000 chosen_pmk:0x00000000000000000000000000000000 +* pid:0x0000 llid:0x0000 plid:0x0000 reason:0x0000 chosen_pmk:0x00000000000000000000000000000000 +*/ +#define MPM_LOG_BUF_LEN 96 /* this length is limited for legal combination */ +static void rtw_mpm_info_msg(struct mpm_frame_info *mpm_info, u8 *mpm_log_buf) +{ + int cnt = 0; + + if (mpm_info->aid) { + cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "aid:0x%04x ", mpm_info->aid_v); + if (cnt >= MPM_LOG_BUF_LEN - 1) + goto exit; + } + if (mpm_info->pid) { + cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "pid:0x%04x ", mpm_info->pid_v); + if (cnt >= MPM_LOG_BUF_LEN - 1) + goto exit; + } + if (mpm_info->llid) { + cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "llid:0x%04x ", mpm_info->llid_v); + if (cnt >= MPM_LOG_BUF_LEN - 1) + goto exit; + } + if (mpm_info->plid) { + cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "plid:0x%04x ", mpm_info->plid_v); + if (cnt >= MPM_LOG_BUF_LEN - 1) + goto exit; + } + if (mpm_info->reason) { + cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "reason:0x%04x ", mpm_info->reason_v); + if (cnt >= MPM_LOG_BUF_LEN - 1) + goto exit; + } + if (mpm_info->chosen_pmk) { + cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "chosen_pmk:0x"KEY_FMT, KEY_ARG(mpm_info->chosen_pmk)); + if (cnt >= MPM_LOG_BUF_LEN - 1) + goto exit; + } + +exit: + return; +} + +static int rtw_mpm_check_frames(_adapter *adapter, u8 action, const u8 **buf, size_t *len, u8 tx) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *plink = NULL; + u8 *nbuf = NULL; + size_t nlen = 0; + u8 *fhead = (u8 *)*buf; + size_t flen = *len; + u8 *peer_addr = tx ? GetAddr1Ptr(fhead) : get_addr2_ptr(fhead); + u8 *frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr); + struct mpm_frame_info mpm_info; + u8 tlv_ies_offset; + u8 *mpm_ie = NULL; + uint mpm_ielen = 0; + u8 *mic_ie = NULL; + uint mic_ielen = 0; + int ret = 0; + u8 mpm_log_buf[MPM_LOG_BUF_LEN] = {0}; + + if (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN) + tlv_ies_offset = 4; + else if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) + tlv_ies_offset = 6; + else if (action == RTW_ACT_SELF_PROTECTED_MESH_CLOSE) + tlv_ies_offset = 2; + else { + rtw_warn_on(1); + goto exit; + } + + plink = rtw_mesh_plink_get(adapter, peer_addr); + if (!plink && (tx == _TRUE || action == RTW_ACT_SELF_PROTECTED_MESH_CONF)) { + /* warning message if no plink when: 1.TX all MPM or 2.RX CONF */ + RTW_WARN("RTW_%s:%s without plink of "MAC_FMT"\n" + , (tx == _TRUE) ? "Tx" : "Rx", action_self_protected_str(action), MAC_ARG(peer_addr)); + goto exit; + } + + _rtw_memset(&mpm_info, 0, sizeof(struct mpm_frame_info)); + + if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) { + mpm_info.aid = (u8 *)frame_body + 4; + mpm_info.aid_v = RTW_GET_LE16(mpm_info.aid); + } + + mpm_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset + , WLAN_EID_MPM, &mpm_ielen + , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset); + if (!mpm_ie || mpm_ielen < 2 + 2) + goto exit; + + mpm_info.pid = mpm_ie + 2; + mpm_info.pid_v = RTW_GET_LE16(mpm_info.pid); + mpm_info.llid = mpm_info.pid + 2; + mpm_info.llid_v = RTW_GET_LE16(mpm_info.llid); + + switch (action) { + case RTW_ACT_SELF_PROTECTED_MESH_OPEN: + /* pid:2, llid:2, (chosen_pmk:16) */ + if (mpm_info.pid_v == 0 && mpm_ielen == 4) + ; + else if (mpm_info.pid_v == 1 && mpm_ielen == 20) + mpm_info.chosen_pmk = mpm_info.llid + 2; + else + goto exit; + break; + case RTW_ACT_SELF_PROTECTED_MESH_CONF: + /* pid:2, llid:2, plid:2, (chosen_pmk:16) */ + mpm_info.plid = mpm_info.llid + 2; + mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid); + if (mpm_info.pid_v == 0 && mpm_ielen == 6) + ; + else if (mpm_info.pid_v == 1 && mpm_ielen == 22) + mpm_info.chosen_pmk = mpm_info.plid + 2; + else + goto exit; + break; + case RTW_ACT_SELF_PROTECTED_MESH_CLOSE: + /* pid:2, llid:2, (plid:2), reason:2, (chosen_pmk:16) */ + if (mpm_info.pid_v == 0 && mpm_ielen == 6) { + /* MPM, without plid */ + mpm_info.reason = mpm_info.llid + 2; + mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason); + } else if (mpm_info.pid_v == 0 && mpm_ielen == 8) { + /* MPM, with plid */ + mpm_info.plid = mpm_info.llid + 2; + mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid); + mpm_info.reason = mpm_info.plid + 2; + mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason); + } else if (mpm_info.pid_v == 1 && mpm_ielen == 22) { + /* AMPE, without plid */ + mpm_info.reason = mpm_info.llid + 2; + mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason); + mpm_info.chosen_pmk = mpm_info.reason + 2; + } else if (mpm_info.pid_v == 1 && mpm_ielen == 24) { + /* AMPE, with plid */ + mpm_info.plid = mpm_info.llid + 2; + mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid); + mpm_info.reason = mpm_info.plid + 2; + mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason); + mpm_info.chosen_pmk = mpm_info.reason + 2; + } else + goto exit; + break; + }; + + if (mpm_info.pid_v == 1) { + mic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset + , WLAN_EID_MIC, &mic_ielen + , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset); + if (!mic_ie || mic_ielen != AES_BLOCK_SIZE) + goto exit; + } + +#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS + if ((action == RTW_ACT_SELF_PROTECTED_MESH_OPEN || action == RTW_ACT_SELF_PROTECTED_MESH_CONF) + && tx == _TRUE + ) { +#define DBG_RTW_MPM_TX_IES_SYNC_BSS 0 + + if (mpm_info.pid_v == 1 && (!plink || !MESH_PLINK_AEK_VALID(plink))) { + RTW_WARN("AEK not ready, IEs can't sync with BSS\n"); + goto bypass_sync_bss; + } + + if (DBG_RTW_MPM_TX_IES_SYNC_BSS) { + RTW_INFO(FUNC_ADPT_FMT" before:\n", FUNC_ADPT_ARG(adapter)); + dump_ies(RTW_DBGDUMP + , fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset + , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset); + } + + rtw_mpm_tx_ies_sync_bss(adapter, plink + , fhead, flen, frame_body, tlv_ies_offset, mpm_ie, mic_ie + , &nbuf, &nlen); + if (!nbuf) + goto exit; + + /* update pointer & len for new frame */ + fhead = nbuf; + flen = nlen; + frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr); + if (mpm_info.pid_v == 1) { + mic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset + , WLAN_EID_MIC, &mic_ielen + , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset); + } + + if (DBG_RTW_MPM_TX_IES_SYNC_BSS) { + RTW_INFO(FUNC_ADPT_FMT" after:\n", FUNC_ADPT_ARG(adapter)); + dump_ies(RTW_DBGDUMP + , fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset + , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset); + } + } +bypass_sync_bss: +#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */ + + if (!plink) + goto mpm_log; + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + if (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN) { + if (tx) + rtw_mesh_plink_set_peer_conf_timeout(adapter, peer_addr); + + } else +#endif + if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) { + _irqL irqL; + u8 *ies = NULL; + u16 ies_len = 0; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + + plink = _rtw_mesh_plink_get(adapter, peer_addr); + if (!plink) + goto release_plink_ctl; + + if (tx == _FALSE) { + ies = plink->rx_conf_ies; + ies_len = plink->rx_conf_ies_len; + plink->rx_conf_ies = NULL; + plink->rx_conf_ies_len = 0; + + plink->llid = mpm_info.plid_v; + plink->plid = mpm_info.llid_v; + plink->peer_aid = mpm_info.aid_v; + if (mpm_info.pid_v == 1) + _rtw_memcpy(plink->chosen_pmk, mpm_info.chosen_pmk, 16); + } + #ifdef CONFIG_RTW_MESH_DRIVER_AID + else { + ies = plink->tx_conf_ies; + ies_len = plink->tx_conf_ies_len; + plink->tx_conf_ies = NULL; + plink->tx_conf_ies_len = 0; + } + #endif + + if (ies && ies_len) + rtw_mfree(ies, ies_len); + + #ifndef CONFIG_RTW_MESH_DRIVER_AID + if (tx == _TRUE) + goto release_plink_ctl; /* no need to copy tx conf ies */ + #endif + + /* copy mesh confirm IEs */ + if (mpm_info.pid_v == 1) /* not include MIC & encrypted AMPE */ + ies_len = (mic_ie - fhead) - sizeof(struct rtw_ieee80211_hdr_3addr) - 2; + else + ies_len = flen - sizeof(struct rtw_ieee80211_hdr_3addr) - 2; + + ies = rtw_zmalloc(ies_len); + if (ies) { + _rtw_memcpy(ies, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + 2, ies_len); + if (tx == _FALSE) { + plink->rx_conf_ies = ies; + plink->rx_conf_ies_len = ies_len; + } + #ifdef CONFIG_RTW_MESH_DRIVER_AID + else { + plink->tx_conf_ies = ies; + plink->tx_conf_ies_len = ies_len; + } + #endif + } + +release_plink_ctl: + _exit_critical_bh(&(plink_ctl->lock), &irqL); + } + +mpm_log: + rtw_mpm_info_msg(&mpm_info, mpm_log_buf); + RTW_INFO("RTW_%s:%s %s\n" + , (tx == _TRUE) ? "Tx" : "Rx" + , action_self_protected_str(action) + , mpm_log_buf + ); + + ret = 1; + +exit: + if (nbuf) { + if (ret == 1) { + *buf = nbuf; + *len = nlen; + } else + rtw_mfree(nbuf, nlen); + } + + return ret; +} + +static int rtw_mesh_check_frames(_adapter *adapter, const u8 **buf, size_t *len, u8 tx) +{ + int is_mesh_frame = -1; + const u8 *frame_body; + u8 category, action; + + frame_body = *buf + sizeof(struct rtw_ieee80211_hdr_3addr); + category = frame_body[0]; + + if (category == RTW_WLAN_CATEGORY_SELF_PROTECTED) { + action = frame_body[1]; + switch (action) { + case RTW_ACT_SELF_PROTECTED_MESH_OPEN: + case RTW_ACT_SELF_PROTECTED_MESH_CONF: + case RTW_ACT_SELF_PROTECTED_MESH_CLOSE: + rtw_mpm_check_frames(adapter, action, buf, len, tx); + is_mesh_frame = action; + break; + case RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM: + case RTW_ACT_SELF_PROTECTED_MESH_GK_ACK: + RTW_INFO("RTW_%s:%s\n", (tx == _TRUE) ? "Tx" : "Rx", action_self_protected_str(action)); + is_mesh_frame = action; + break; + default: + break; + }; + } + +exit: + return is_mesh_frame; +} + +int rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len) +{ + return rtw_mesh_check_frames(adapter, buf, len, _TRUE); +} + +int rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len) +{ + return rtw_mesh_check_frames(adapter, &buf, &len, _FALSE); +} + +unsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe) +{ + unsigned int ret = _FAIL; + struct sta_info *sta = NULL; + u8 *pframe = rframe->u.hdr.rx_data; + uint frame_len = rframe->u.hdr.len; + u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 category; + u8 action; + + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(adapter), GetAddr1Ptr(pframe), ETH_ALEN)) + goto exit; + + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_SELF_PROTECTED) + goto exit; + + action = frame_body[1]; + switch (action) { + case RTW_ACT_SELF_PROTECTED_MESH_OPEN: + case RTW_ACT_SELF_PROTECTED_MESH_CONF: + case RTW_ACT_SELF_PROTECTED_MESH_CLOSE: + case RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM: + case RTW_ACT_SELF_PROTECTED_MESH_GK_ACK: + if (!(MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))) + goto exit; +#ifdef CONFIG_IOCTL_CFG80211 + #if CONFIG_RTW_MACADDR_ACL + if (rtw_access_ctrl(adapter, get_addr2_ptr(pframe)) == _FALSE) + goto exit; + #endif + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + if (rtw_mesh_cto_mgate_required(adapter) + /* only peer being added (checked by notify conditions) is allowed */ + && !rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe))) + goto exit; + #endif + rtw_cfg80211_rx_action(adapter, rframe, NULL); + ret = _SUCCESS; +#endif /* CONFIG_IOCTL_CFG80211 */ + break; + default: + break; + } + +exit: + return ret; +} + +const u8 ae_to_mesh_ctrl_len[] = { + 6, + 12, /* MESH_FLAGS_AE_A4 */ + 18, /* MESH_FLAGS_AE_A5_A6 */ + 0, +}; + +unsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe) +{ + unsigned int ret = _FAIL; + struct sta_info *sta = NULL; + struct sta_priv *stapriv = &adapter->stapriv; + u8 *pframe = rframe->u.hdr.rx_data; + uint frame_len = rframe->u.hdr.len; + u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 category; + u8 action; + + if (!MLME_IS_MESH(adapter)) + goto exit; + + /* check stainfo exist? */ + + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_MESH) + goto exit; + + action = frame_body[1]; + switch (action) { + case RTW_ACT_MESH_HWMP_PATH_SELECTION: + rtw_mesh_rx_path_sel_frame(adapter, rframe); + ret = _SUCCESS; + break; + default: + break; + } + +exit: + return ret; +} + +bool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + u8 num_of_peerings = stapriv->asoc_list_cnt; + bool accept_peerings = stapriv->asoc_list_cnt < mcfg->max_peer_links; + u8 *ie; + int ie_len; + bool updated = 0; + + ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, BSS_EX_TLV_IES_LEN(bss)); + if (!ie || ie_len != 7) { + rtw_warn_on(1); + goto exit; + } + + if (GET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2) != num_of_peerings) { + SET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2, num_of_peerings); + updated = 1; + } + + if (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2) != accept_peerings) { + SET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2, accept_peerings); + updated = 1; + } + +exit: + return updated; +} + +bool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + u8 cto_mgate = (minfo->num_gates || mcfg->dot11MeshGateAnnouncementProtocol); + u8 cto_as = 0; + u8 *ie; + int ie_len; + bool updated = 0; + + ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, + BSS_EX_TLV_IES_LEN(bss)); + if (!ie || ie_len != 7) { + rtw_warn_on(1); + goto exit; + } + + if (GET_MESH_CONF_ELE_CTO_MGATE(ie + 2) != cto_mgate) { + SET_MESH_CONF_ELE_CTO_MGATE(ie + 2, cto_mgate); + updated = 1; + } + + if (GET_MESH_CONF_ELE_CTO_AS(ie + 2) != cto_as) { + SET_MESH_CONF_ELE_CTO_AS(ie + 2, cto_as); + updated = 1; + } + +exit: + return updated; +} + +bool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + u8 forward = mcfg->dot11MeshForwarding; + u8 *ie; + int ie_len; + bool updated = 0; + + ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, + BSS_EX_TLV_IES_LEN(bss)); + if (!ie || ie_len != 7) { + rtw_warn_on(1); + goto exit; + } + + if (GET_MESH_CONF_ELE_FORWARDING(ie + 2) != forward) { + SET_MESH_CONF_ELE_FORWARDING(ie + 2, forward); + updated = 1; + } + +exit: + return updated; +} + +struct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + int i; + + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + if (plink_ctl->ent[i].valid == _TRUE + && _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE + ) { + ent = &plink_ctl->ent[i]; + break; + } + } + +exit: + return ent; +} + +struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + ent = _rtw_mesh_plink_get(adapter, hwaddr); + _exit_critical_bh(&(plink_ctl->lock), &irqL); + +exit: + return ent; +} + +struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + int i, j = 0; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + if (plink_ctl->ent[i].valid == _TRUE + && plink_ctl->ent[i].plink_state != RTW_MESH_PLINK_ESTAB + ) { + if (j == idx) { + ent = &plink_ctl->ent[i]; + break; + } + j++; + } + } + _exit_critical_bh(&(plink_ctl->lock), &irqL); + + return ent; +} + +int _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + u8 exist = _FALSE; + int i; + + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + if (plink_ctl->ent[i].valid == _TRUE + && _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE + ) { + ent = &plink_ctl->ent[i]; + exist = _TRUE; + break; + } + + if (ent == NULL && plink_ctl->ent[i].valid == _FALSE) + ent = &plink_ctl->ent[i]; + } + + if (exist == _FALSE && ent) { + _rtw_memcpy(ent->addr, hwaddr, ETH_ALEN); + ent->valid = _TRUE; + #ifdef CONFIG_RTW_MESH_AEK + ent->aek_valid = 0; + #endif + ent->llid = 0; + ent->plid = 0; + _rtw_memset(ent->chosen_pmk, 0, 16); + #ifdef CONFIG_RTW_MESH_AEK + _rtw_memset(ent->sel_pcs, 0, 4); + _rtw_memset(ent->l_nonce, 0, 32); + _rtw_memset(ent->p_nonce, 0, 32); + #endif + ent->plink_state = RTW_MESH_PLINK_LISTEN; + #ifndef CONFIG_RTW_MESH_DRIVER_AID + ent->aid = 0; + #endif + ent->peer_aid = 0; + SET_PEER_CONF_DISABLED(ent); + SET_CTO_MGATE_CONF_DISABLED(ent); + plink_ctl->num++; + } + +exit: + return exist == _TRUE ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL); +} + +int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + _irqL irqL; + int ret; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + ret = _rtw_mesh_plink_add(adapter, hwaddr); + _exit_critical_bh(&(plink_ctl->lock), &irqL); + + return ret; +} + +int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + ent = _rtw_mesh_plink_get(adapter, hwaddr); + if (ent) + ent->plink_state = state; + _exit_critical_bh(&(plink_ctl->lock), &irqL); + +exit: + return ent ? _SUCCESS : _FAIL; +} + +#ifdef CONFIG_RTW_MESH_AEK +int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + ent = _rtw_mesh_plink_get(adapter, hwaddr); + if (ent) { + _rtw_memcpy(ent->aek, aek, 32); + ent->aek_valid = 1; + } + _exit_critical_bh(&(plink_ctl->lock), &irqL); + +exit: + return ent ? _SUCCESS : _FAIL; +} +#endif + +#if CONFIG_RTW_MESH_PEER_BLACKLIST +int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + ent = _rtw_mesh_plink_get(adapter, hwaddr); + if (ent) { + if (IS_PEER_CONF_DISABLED(ent)) + SET_PEER_CONF_END_TIME(ent, mcfg->peer_sel_policy.peer_conf_timeout_ms); + } + _exit_critical_bh(&(plink_ctl->lock), &irqL); + +exit: + return ent ? _SUCCESS : _FAIL; +} +#endif + +void _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + ent->valid = _FALSE; + #ifdef CONFIG_RTW_MESH_DRIVER_AID + if (ent->tx_conf_ies && ent->tx_conf_ies_len) + rtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len); + ent->tx_conf_ies = NULL; + ent->tx_conf_ies_len = 0; + #endif + if (ent->rx_conf_ies && ent->rx_conf_ies_len) + rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len); + ent->rx_conf_ies = NULL; + ent->rx_conf_ies_len = 0; + if (ent->scanned) + ent->scanned = NULL; + plink_ctl->num--; +} + +int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + u8 exist = _FALSE; + int i; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + if (plink_ctl->ent[i].valid == _TRUE + && _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE + ) { + ent = &plink_ctl->ent[i]; + exist = _TRUE; + break; + } + } + + if (exist == _TRUE) + _rtw_mesh_plink_del_ent(adapter, ent); + + _exit_critical_bh(&(plink_ctl->lock), &irqL); + +exit: + return exist == _TRUE ? _SUCCESS : RTW_ALREADY; +} + +void rtw_mesh_plink_ctl_init(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + int i; + + _rtw_spinlock_init(&plink_ctl->lock); + plink_ctl->num = 0; + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) + plink_ctl->ent[i].valid = _FALSE; + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + _rtw_init_queue(&plink_ctl->peer_blacklist); +#endif +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + _rtw_init_queue(&plink_ctl->cto_mgate_blacklist); +#endif +} + +void rtw_mesh_plink_ctl_deinit(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent; + int i; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + ent = &plink_ctl->ent[i]; + #ifdef CONFIG_RTW_MESH_DRIVER_AID + if (ent->tx_conf_ies && ent->tx_conf_ies_len) + rtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len); + #endif + if (ent->rx_conf_ies && ent->rx_conf_ies_len) + rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len); + } + _exit_critical_bh(&(plink_ctl->lock), &irqL); + + _rtw_spinlock_free(&plink_ctl->lock); + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + rtw_mesh_peer_blacklist_flush(adapter); + _rtw_deinit_queue(&plink_ctl->peer_blacklist); +#endif +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + rtw_mesh_cto_mgate_blacklist_flush(adapter); + _rtw_deinit_queue(&plink_ctl->cto_mgate_blacklist); +#endif +} + +void dump_mesh_plink_ctl(void *sel, _adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent; + int i; + + RTW_PRINT_SEL(sel, "num:%u\n", plink_ctl->num); + + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + ent = &plink_ctl->ent[i]; + if (!ent->valid) + continue; + + RTW_PRINT_SEL(sel, "\n"); + RTW_PRINT_SEL(sel, "peer:"MAC_FMT"\n", MAC_ARG(ent->addr)); + RTW_PRINT_SEL(sel, "plink_state:%s\n", rtw_mesh_plink_str(ent->plink_state)); + + #ifdef CONFIG_RTW_MESH_AEK + if (ent->aek_valid) + RTW_PRINT_SEL(sel, "aek:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->aek), KEY_ARG(ent->aek + 16)); + #endif + + RTW_PRINT_SEL(sel, "llid:%u, plid:%u\n", ent->llid, ent->plid); + #ifndef CONFIG_RTW_MESH_DRIVER_AID + RTW_PRINT_SEL(sel, "aid:%u\n", ent->aid); + #endif + RTW_PRINT_SEL(sel, "peer_aid:%u\n", ent->peer_aid); + + RTW_PRINT_SEL(sel, "chosen_pmk:"KEY_FMT"\n", KEY_ARG(ent->chosen_pmk)); + + #ifdef CONFIG_RTW_MESH_AEK + RTW_PRINT_SEL(sel, "sel_pcs:%02x%02x%02x%02x\n" + , ent->sel_pcs[0], ent->sel_pcs[1], ent->sel_pcs[2], ent->sel_pcs[3]); + RTW_PRINT_SEL(sel, "l_nonce:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->l_nonce), KEY_ARG(ent->l_nonce + 16)); + RTW_PRINT_SEL(sel, "p_nonce:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->p_nonce), KEY_ARG(ent->p_nonce + 16)); + #endif + + #ifdef CONFIG_RTW_MESH_DRIVER_AID + RTW_PRINT_SEL(sel, "tx_conf_ies:%p, len:%u\n", ent->tx_conf_ies, ent->tx_conf_ies_len); + #endif + RTW_PRINT_SEL(sel, "rx_conf_ies:%p, len:%u\n", ent->rx_conf_ies, ent->rx_conf_ies_len); + RTW_PRINT_SEL(sel, "scanned:%p\n", ent->scanned); + + #if CONFIG_RTW_MESH_PEER_BLACKLIST + if (!IS_PEER_CONF_DISABLED(ent)) { + if (!IS_PEER_CONF_TIMEOUT(ent)) + RTW_PRINT_SEL(sel, "peer_conf:%d\n", rtw_systime_to_ms(ent->peer_conf_end_time - rtw_get_current_time())); + else + RTW_PRINT_SEL(sel, "peer_conf:TIMEOUT\n"); + } + #endif + + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + if (!IS_CTO_MGATE_CONF_DISABLED(ent)) { + if (!IS_CTO_MGATE_CONF_TIMEOUT(ent)) + RTW_PRINT_SEL(sel, "cto_mgate_conf:%d\n", rtw_systime_to_ms(ent->cto_mgate_conf_end_time - rtw_get_current_time())); + else + RTW_PRINT_SEL(sel, "cto_mgate_conf:TIMEOUT\n"); + } + #endif + } +} + +/* this function is called with plink_ctl being locked */ +int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *plink, struct sta_info *sta) +{ +#ifndef DBG_RTW_MESH_PEER_ESTABLISH +#define DBG_RTW_MESH_PEER_ESTABLISH 0 +#endif + + struct sta_priv *stapriv = &adapter->stapriv; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + u8 *tlv_ies; + u16 tlv_ieslen; + struct rtw_ieee802_11_elems elems; + _irqL irqL; + int i; + int ret = _FAIL; + + if (!plink->rx_conf_ies || !plink->rx_conf_ies_len) { + RTW_INFO(FUNC_ADPT_FMT" no rx confirm from sta "MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + goto exit; + } + + if (plink->rx_conf_ies_len < 4) { + RTW_INFO(FUNC_ADPT_FMT" confirm from sta "MAC_FMT" too short\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + goto exit; + } + +#ifdef CONFIG_RTW_MESH_DRIVER_AID + if (!plink->tx_conf_ies || !plink->tx_conf_ies_len) { + RTW_INFO(FUNC_ADPT_FMT" no tx confirm to sta "MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + goto exit; + } + + if (plink->tx_conf_ies_len < 4) { + RTW_INFO(FUNC_ADPT_FMT" confirm to sta "MAC_FMT" too short\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + goto exit; + } +#endif + + tlv_ies = plink->rx_conf_ies + 4; + tlv_ieslen = plink->rx_conf_ies_len - 4; + + if (DBG_RTW_MESH_PEER_ESTABLISH) + dump_ies(RTW_DBGDUMP, tlv_ies, tlv_ieslen); + + if (rtw_ieee802_11_parse_elems(tlv_ies, tlv_ieslen, &elems, 1) == ParseFailed) { + RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" sent invalid confirm\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + goto exit; + } + + SET_PEER_CONF_DISABLED(plink); + if (rtw_bss_is_cto_mgate(&plink->scanned->network) + && !rtw_bss_is_forwarding(&plink->scanned->network)) + SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms); + else + SET_CTO_MGATE_CONF_DISABLED(plink); + + sta->state &= (~WIFI_FW_AUTH_SUCCESS); + sta->state |= WIFI_FW_ASSOC_STATE; + + rtw_ap_parse_sta_capability(adapter, sta, plink->rx_conf_ies); + + if (rtw_ap_parse_sta_supported_rates(adapter, sta, tlv_ies, tlv_ieslen) != _STATS_SUCCESSFUL_) + goto exit; + + if (rtw_ap_parse_sta_security_ie(adapter, sta, &elems) != _STATS_SUCCESSFUL_) + goto exit; + + rtw_ap_parse_sta_wmm_ie(adapter, sta, tlv_ies, tlv_ieslen); + + rtw_ap_parse_sta_ht_ie(adapter, sta, &elems); + rtw_ap_parse_sta_vht_ie(adapter, sta, &elems); + + /* AID */ +#ifdef CONFIG_RTW_MESH_DRIVER_AID + sta->cmn.aid = RTW_GET_LE16(plink->tx_conf_ies + 2); +#else + sta->cmn.aid = plink->aid; +#endif + stapriv->sta_aid[sta->cmn.aid - 1] = sta; + RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" aid:%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr), sta->cmn.aid); + + sta->state &= (~WIFI_FW_ASSOC_STATE); + sta->state |= WIFI_FW_ASSOC_SUCCESS; + + sta->local_mps = RTW_MESH_PS_ACTIVE; + + rtw_ewma_err_rate_init(&sta->metrics.err_rate); + rtw_ewma_err_rate_add(&sta->metrics.err_rate, 1); + /* init data_rate to 1M */ + sta->metrics.data_rate = 10; + + _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&sta->asoc_list)) { + STA_SET_MESH_PLINK(sta, plink); + sta->expire_to = mcfg->plink_timeout / 2; + rtw_list_insert_tail(&sta->asoc_list, &stapriv->asoc_list); + stapriv->asoc_list_cnt++; + } + _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + + bss_cap_update_on_sta_join(adapter, sta); + sta_info_update(adapter, sta); + report_add_sta_event(adapter, sta->cmn.mac_addr); + + ret = _SUCCESS; + +exit: + return ret; +} + +void rtw_mesh_expire_peer_notify(_adapter *adapter, const u8 *peer_addr) +{ + u8 null_ssid[2] = {0, 0}; + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev + , peer_addr + , null_ssid + , 2 + , GFP_ATOMIC + ); +#endif + +exit: + return; +} + +static u8 *rtw_mesh_construct_peer_mesh_close(_adapter *adapter, struct mesh_plink_ent *plink, u16 reason, u32 *len) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + u8 *frame = NULL, *pos; + u32 flen; + struct rtw_ieee80211_hdr *whdr; + + if (minfo->mesh_auth_id && !MESH_PLINK_AEK_VALID(plink)) + goto exit; + + flen = sizeof(struct rtw_ieee80211_hdr_3addr) + + 2 /* category, action */ + + 2 + minfo->mesh_id_len /* mesh id */ + + 2 + 8 + (minfo->mesh_auth_id ? 16 : 0) /* mpm */ + + (minfo->mesh_auth_id ? 2 + AES_BLOCK_SIZE : 0) /* mic */ + + (minfo->mesh_auth_id ? 70 : 0) /* ampe */ + ; + + pos = frame = rtw_zmalloc(flen); + if (!frame) + goto exit; + + whdr = (struct rtw_ieee80211_hdr *)frame; + _rtw_memcpy(whdr->addr1, adapter_mac_addr(adapter), ETH_ALEN); + _rtw_memcpy(whdr->addr2, plink->addr, ETH_ALEN); + _rtw_memcpy(whdr->addr3, adapter_mac_addr(adapter), ETH_ALEN); + + set_frame_sub_type(frame, WIFI_ACTION); + + pos += sizeof(struct rtw_ieee80211_hdr_3addr); + *(pos++) = RTW_WLAN_CATEGORY_SELF_PROTECTED; + *(pos++) = RTW_ACT_SELF_PROTECTED_MESH_CLOSE; + + pos = rtw_set_ie_mesh_id(pos, NULL, minfo->mesh_id, minfo->mesh_id_len); + + pos = rtw_set_ie_mpm(pos, NULL + , minfo->mesh_auth_id ? 1 : 0 + , plink->plid + , &plink->llid + , &reason + , minfo->mesh_auth_id ? plink->chosen_pmk : NULL); + +#ifdef CONFIG_RTW_MESH_AEK + if (minfo->mesh_auth_id) { + u8 ampe_buf[70]; + int enc_ret; + + *pos = WLAN_EID_MIC; + *(pos + 1) = AES_BLOCK_SIZE; + + ampe_buf[0] = WLAN_EID_AMPE; + ampe_buf[1] = 68; + _rtw_memcpy(ampe_buf + 2, plink->sel_pcs, 4); + _rtw_memcpy(ampe_buf + 6, plink->p_nonce, 32); + _rtw_memcpy(ampe_buf + 38, plink->l_nonce, 32); + + enc_ret = rtw_mpm_ampe_enc(adapter, plink + , frame + sizeof(struct rtw_ieee80211_hdr_3addr) + , pos, ampe_buf, 1); + if (enc_ret != _SUCCESS) { + rtw_mfree(frame, flen); + frame = NULL; + goto exit; + } + } +#endif + + *len = flen; + +exit: + return frame; +} + +void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink) +{ +#if defined(CONFIG_RTW_MESH_STA_DEL_DISASOC) + _rtw_mesh_plink_del_ent(adapter, plink); + rtw_cfg80211_indicate_sta_disassoc(adapter, plink->addr, 0); +#else + u8 *frame = NULL; + u32 flen; + + if (plink->plink_state == RTW_MESH_PLINK_ESTAB) + frame = rtw_mesh_construct_peer_mesh_close(adapter, plink, WLAN_REASON_MESH_CLOSE, &flen); + + if (frame) { + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct wireless_dev *wdev = adapter->rtw_wdev; + s32 freq = rtw_ch2freq(mlmeext->cur_channel); + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, flen, GFP_ATOMIC); + #else + cfg80211_rx_action(adapter->pnetdev, freq, frame, flen, GFP_ATOMIC); + #endif + + rtw_mfree(frame, flen); + } else { + rtw_mesh_expire_peer_notify(adapter, plink->addr); + RTW_INFO(FUNC_ADPT_FMT" set "MAC_FMT" plink unknown\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(plink->addr)); + plink->plink_state = RTW_MESH_PLINK_UNKNOWN; + } +#endif +} + +void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *plink; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + + plink = _rtw_mesh_plink_get(adapter, peer_addr); + if (!plink) + goto exit; + + _rtw_mesh_expire_peer_ent(adapter, plink); + +exit: + _exit_critical_bh(&(plink_ctl->lock), &irqL); +} + +u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps) +{ + _irqL irqL; + _list *head, *list; + struct sta_info *sta; + struct sta_priv *stapriv = &adapter->stapriv; + u8 sta_alive_num = 0, i; + char sta_alive_list[NUM_STA]; + u8 annc_cnt = 0; + + if (rtw_linked_check(adapter) == _FALSE) + goto exit; + + _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + + head = &stapriv->asoc_list; + list = get_next(head); + while ((rtw_end_of_queue_search(head, list)) == _FALSE) { + int stainfo_offset; + + sta = LIST_CONTAINOR(list, struct sta_info, asoc_list); + list = get_next(list); + + stainfo_offset = rtw_stainfo_offset(stapriv, sta); + if (stainfo_offset_valid(stainfo_offset)) + sta_alive_list[sta_alive_num++] = stainfo_offset; + } + _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + + for (i = 0; i < sta_alive_num; i++) { + sta = rtw_get_stainfo_by_offset(stapriv, sta_alive_list[i]); + if (!sta) + continue; + + issue_qos_nulldata(adapter, sta->cmn.mac_addr, 7, ps, 3, 500); + annc_cnt++; + } + +exit: + return annc_cnt; +} + +static void mpath_tx_tasklet_hdl(void *priv) +{ + _adapter *adapter = (_adapter *)priv; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct xmit_frame *xframe; + _list *list, *head; + _list tmp; + u32 tmp_len; + s32 res; + + _rtw_init_listhead(&tmp); + + while (1) { + tmp_len = 0; + enter_critical_bh(&minfo->mpath_tx_queue.lock); + if (minfo->mpath_tx_queue_len) { + rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp); + tmp_len = minfo->mpath_tx_queue_len; + minfo->mpath_tx_queue_len = 0; + } + exit_critical_bh(&minfo->mpath_tx_queue.lock); + + if (!tmp_len) + break; + + head = &tmp; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + xframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&xframe->list); + res = rtw_xmit_posthandle(adapter, xframe, xframe->pkt); + if (res < 0) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__); + #endif + adapter->xmitpriv.tx_drop++; + } + } + } +} + +static void rtw_mpath_tx_queue_flush(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct xmit_frame *xframe; + _list *list, *head; + _list tmp; + + _rtw_init_listhead(&tmp); + + enter_critical_bh(&minfo->mpath_tx_queue.lock); + rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp); + minfo->mpath_tx_queue_len = 0; + exit_critical_bh(&minfo->mpath_tx_queue.lock); + + head = &tmp; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + xframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&xframe->list); + rtw_free_xmitframe(&adapter->xmitpriv, xframe); + } +} + +#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */ +#if defined(CONFIG_SLUB) +#include +#elif defined(CONFIG_SLAB) +#include +#endif +typedef struct kmem_cache rtw_mcache; +#endif + +rtw_mcache *rtw_mcache_create(const char *name, size_t size) +{ +#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */ + return kmem_cache_create(name, size, 0, 0, NULL); +#else + #error "TBD\n"; +#endif +} + +void rtw_mcache_destroy(rtw_mcache *s) +{ +#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */ + kmem_cache_destroy(s); +#else + #error "TBD\n"; +#endif +} + +void *_rtw_mcache_alloc(rtw_mcache *cachep) +{ +#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */ + return kmem_cache_alloc(cachep, GFP_ATOMIC); +#else + #error "TBD\n"; +#endif +} + +void _rtw_mcache_free(rtw_mcache *cachep, void *objp) +{ +#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */ + kmem_cache_free(cachep, objp); +#else + #error "TBD\n"; +#endif +} + +#ifdef DBG_MEM_ALLOC +inline void *dbg_rtw_mcache_alloc(rtw_mcache *cachep, const enum mstat_f flags, const char *func, const int line) +{ + void *p; + u32 sz = cachep->size; + + if (match_mstat_sniff_rules(flags, sz)) + RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u)\n", func, line, __func__, sz); + + p = _rtw_mcache_alloc(cachep); + + rtw_mstat_update( + flags + , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , sz + ); + + return p; +} + +inline void dbg_rtw_mcache_free(rtw_mcache *cachep, void *pbuf, const enum mstat_f flags, const char *func, const int line) +{ + u32 sz = cachep->size; + + if (match_mstat_sniff_rules(flags, sz)) + RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u)\n", func, line, __func__, sz); + + _rtw_mcache_free(cachep, pbuf); + + rtw_mstat_update( + flags + , MSTAT_FREE + , sz + ); +} + +#define rtw_mcache_alloc(cachep) dbg_rtw_mcache_alloc(cachep, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_mcache_free(cachep, objp) dbg_rtw_mcache_free(cachep, objp, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#else +#define rtw_mcache_alloc(cachep) _rtw_mcache_alloc(cachep) +#define rtw_mcache_free(cachep, objp) _rtw_mcache_free(cachep, objp) +#endif /* DBG_MEM_ALLOC */ + +/* Mesh Received Cache */ +#define RTW_MRC_BUCKETS 256 /* must be a power of 2 */ +#define RTW_MRC_QUEUE_MAX_LEN 4 +#define RTW_MRC_TIMEOUT_MS (3 * 1000) + +/** + * struct rtw_mrc_entry - entry in the Mesh Received Cache + * + * @seqnum: mesh sequence number of the frame + * @exp_time: expiration time of the entry + * @msa: mesh source address of the frame + * @list: hashtable list pointer + * + * The Mesh Received Cache keeps track of the latest received frames that + * have been received by a mesh interface and discards received frames + * that are found in the cache. + */ +struct rtw_mrc_entry { + rtw_hlist_node list; + systime exp_time; + u32 seqnum; + u8 msa[ETH_ALEN]; +}; + +struct rtw_mrc { + rtw_hlist_head bucket[RTW_MRC_BUCKETS]; + u32 idx_mask; + rtw_mcache *cache; +}; + +static int rtw_mrc_init(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + char cache_name[IFNAMSIZ + 8 + 1]; + int i; + + minfo->mrc = rtw_malloc(sizeof(struct rtw_mrc)); + if (!minfo->mrc) + return -ENOMEM; + minfo->mrc->idx_mask = RTW_MRC_BUCKETS - 1; + for (i = 0; i < RTW_MRC_BUCKETS; i++) + rtw_hlist_head_init(&minfo->mrc->bucket[i]); + + sprintf(cache_name, "rtw_mrc_%s", ADPT_ARG(adapter)); + minfo->mrc->cache = rtw_mcache_create(cache_name, sizeof(struct rtw_mrc_entry)); + + return 0; +} + +static void rtw_mrc_free(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mrc *mrc = minfo->mrc; + struct rtw_mrc_entry *p; + rtw_hlist_node *np, *n; + int i; + + if (!mrc) + return; + + for (i = 0; i < RTW_MRC_BUCKETS; i++) { + rtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[i], list) { + rtw_hlist_del(&p->list); + rtw_mcache_free(mrc->cache, p); + } + } + + rtw_mcache_destroy(mrc->cache); + + rtw_mfree(mrc, sizeof(struct rtw_mrc)); + minfo->mrc = NULL; +} + +/** + * rtw_mrc_check - Check frame in mesh received cache and add if absent. + * + * @adapter: interface + * @msa: mesh source address + * @seq: mesh seq number + * + * Returns: 0 if the frame is not in the cache, nonzero otherwise. + * + * Checks using the mesh source address and the mesh sequence number if we have + * received this frame lately. If the frame is not in the cache, it is added to + * it. + */ +static int rtw_mrc_check(_adapter *adapter, const u8 *msa, u32 seq) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mrc *mrc = minfo->mrc; + int entries = 0; + u8 idx; + struct rtw_mrc_entry *p; + rtw_hlist_node *np, *n; + u8 timeout; + + if (!mrc) + return -1; + + idx = seq & mrc->idx_mask; + rtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[idx], list) { + ++entries; + timeout = rtw_time_after(rtw_get_current_time(), p->exp_time); + if (timeout || entries == RTW_MRC_QUEUE_MAX_LEN) { + if (!timeout) + minfo->mshstats.mrc_del_qlen++; + + rtw_hlist_del(&p->list); + rtw_mcache_free(mrc->cache, p); + --entries; + } else if ((seq == p->seqnum) && _rtw_memcmp(msa, p->msa, ETH_ALEN) == _TRUE) + return -1; + } + + p = rtw_mcache_alloc(mrc->cache); + if (!p) + return 0; + + p->seqnum = seq; + p->exp_time = rtw_get_current_time() + rtw_ms_to_systime(RTW_MRC_TIMEOUT_MS); + _rtw_memcpy(p->msa, msa, ETH_ALEN); + rtw_hlist_add_head(&p->list, &mrc->bucket[idx]); + return 0; +} + +static int rtw_mesh_decache(_adapter *adapter, const u8 *msa, u32 seq) +{ + return rtw_mrc_check(adapter, msa, seq); +} + +void rtw_mesh_cfg_init_peer_sel_policy(struct rtw_mesh_cfg *mcfg) +{ + struct mesh_peer_sel_policy *sel_policy = &mcfg->peer_sel_policy; + + sel_policy->scanr_exp_ms = RTW_MESH_SCAN_RESULT_EXP_MS; + +#if CONFIG_RTW_MESH_OFFCH_CAND + sel_policy->offch_find_int_ms = RTW_MESH_OFFCH_CAND_FIND_INT_MS; +#endif + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + sel_policy->peer_conf_timeout_ms = RTW_MESH_PEER_CONF_TIMEOUT_MS; + sel_policy->peer_blacklist_timeout_ms = RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS; +#endif + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + sel_policy->cto_mgate_require = 0; + sel_policy->cto_mgate_conf_timeout_ms = RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS; + sel_policy->cto_mgate_blacklist_timeout_ms = RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS; +#endif +} + +void rtw_mesh_cfg_init(_adapter *adapter) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + + mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS; + mcfg->plink_timeout = RTW_MESH_PEER_LINK_TIMEOUT; + + mcfg->dot11MeshTTL = RTW_MESH_TTL; + mcfg->element_ttl = RTW_MESH_DEFAULT_ELEMENT_TTL; + mcfg->dot11MeshHWMPmaxPREQretries = RTW_MESH_MAX_PREQ_RETRIES; + mcfg->path_refresh_time = RTW_MESH_PATH_REFRESH_TIME; + mcfg->min_discovery_timeout = RTW_MESH_MIN_DISCOVERY_TIMEOUT; + mcfg->dot11MeshHWMPactivePathTimeout = RTW_MESH_PATH_TIMEOUT; + mcfg->dot11MeshHWMPpreqMinInterval = RTW_MESH_PREQ_MIN_INT; + mcfg->dot11MeshHWMPperrMinInterval = RTW_MESH_PERR_MIN_INT; + mcfg->dot11MeshHWMPnetDiameterTraversalTime = RTW_MESH_DIAM_TRAVERSAL_TIME; + mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_ROOTMODE_NO_ROOT; + mcfg->dot11MeshHWMPRannInterval = RTW_MESH_RANN_INTERVAL; + mcfg->dot11MeshGateAnnouncementProtocol = _FALSE; + mcfg->dot11MeshForwarding = _TRUE; + mcfg->rssi_threshold = 0; + mcfg->dot11MeshHWMPactivePathToRootTimeout = RTW_MESH_PATH_TO_ROOT_TIMEOUT; + mcfg->dot11MeshHWMProotInterval = RTW_MESH_ROOT_INTERVAL; + mcfg->dot11MeshHWMPconfirmationInterval = RTW_MESH_ROOT_CONFIRMATION_INTERVAL; + mcfg->path_gate_timeout_factor = 3; + rtw_mesh_cfg_init_peer_sel_policy(mcfg); + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + mcfg->b2u_flags_msrc = 0; + mcfg->b2u_flags_mfwd = RTW_MESH_B2U_GA_UCAST; +#endif +} + +void rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + + mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS; + + if (mcfg->max_peer_links > stack_conf) + mcfg->max_peer_links = stack_conf; +} + +void rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + + mcfg->plink_timeout = stack_conf; +} + +void rtw_mesh_init_mesh_info(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + + _rtw_memset(minfo, 0, sizeof(struct rtw_mesh_info)); + + rtw_mesh_plink_ctl_init(adapter); + + minfo->last_preq = rtw_get_current_time(); + /* minfo->last_sn_update = rtw_get_current_time(); */ + minfo->next_perr = rtw_get_current_time(); + + ATOMIC_SET(&minfo->mpaths, 0); + rtw_mesh_pathtbl_init(adapter); + + _rtw_init_queue(&minfo->mpath_tx_queue); + tasklet_init(&minfo->mpath_tx_tasklet + , (void(*)(unsigned long))mpath_tx_tasklet_hdl + , (unsigned long)adapter); + + rtw_mrc_init(adapter); + + _rtw_init_listhead(&minfo->preq_queue.list); + _rtw_spinlock_init(&minfo->mesh_preq_queue_lock); + + rtw_init_timer(&adapter->mesh_path_timer, adapter, rtw_ieee80211_mesh_path_timer, adapter); + rtw_init_timer(&adapter->mesh_path_root_timer, adapter, rtw_ieee80211_mesh_path_root_timer, adapter); + rtw_init_timer(&adapter->mesh_atlm_param_req_timer, adapter, rtw_mesh_atlm_param_req_timer, adapter); + _init_workitem(&adapter->mesh_work, rtw_mesh_work_hdl, NULL); +} + +void rtw_mesh_deinit_mesh_info(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + + tasklet_kill(&minfo->mpath_tx_tasklet); + rtw_mpath_tx_queue_flush(adapter); + _rtw_deinit_queue(&adapter->mesh_info.mpath_tx_queue); + + rtw_mrc_free(adapter); + + rtw_mesh_pathtbl_unregister(adapter); + + rtw_mesh_plink_ctl_deinit(adapter); + + _cancel_workitem_sync(&adapter->mesh_work); + _cancel_timer_ex(&adapter->mesh_path_timer); + _cancel_timer_ex(&adapter->mesh_path_root_timer); + _cancel_timer_ex(&adapter->mesh_atlm_param_req_timer); +} + +/** + * rtw_mesh_nexthop_resolve - lookup next hop; conditionally start path discovery + * + * @skb: 802.11 frame to be sent + * @sdata: network subif the frame will be sent through + * + * Lookup next hop for given skb and start path discovery if no + * forwarding information is found. + * + * Returns: 0 if the next hop was found and -ENOENT if the frame was queued. + * skb is freeed here if no mpath could be allocated. + */ +int rtw_mesh_nexthop_resolve(_adapter *adapter, + struct xmit_frame *xframe) +{ + struct pkt_attrib *attrib = &xframe->attrib; + struct rtw_mesh_path *mpath; + struct xmit_frame *xframe_to_free = NULL; + u8 *target_addr = attrib->mda; + int err = 0; + int ret = _SUCCESS; + + rtw_rcu_read_lock(); + err = rtw_mesh_nexthop_lookup(adapter, target_addr, attrib->msa, attrib->ra); + if (!err) + goto endlookup; + + /* no nexthop found, start resolving */ + mpath = rtw_mesh_path_lookup(adapter, target_addr); + if (!mpath) { + mpath = rtw_mesh_path_add(adapter, target_addr); + if (IS_ERR(mpath)) { + xframe->pkt = NULL; /* free pkt outside */ + rtw_mesh_path_discard_frame(adapter, xframe); + err = PTR_ERR(mpath); + ret = _FAIL; + goto endlookup; + } + } + + if (!(mpath->flags & RTW_MESH_PATH_RESOLVING)) + rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START); + + enter_critical_bh(&mpath->frame_queue.lock); + + if (mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) { + xframe_to_free = LIST_CONTAINOR(get_next(get_list_head(&mpath->frame_queue)), struct xmit_frame, list); + rtw_list_delete(&(xframe_to_free->list)); + mpath->frame_queue_len--; + } + + rtw_list_insert_tail(&xframe->list, get_list_head(&mpath->frame_queue)); + mpath->frame_queue_len++; + + exit_critical_bh(&mpath->frame_queue.lock); + + ret = RTW_RA_RESOLVING; + if (xframe_to_free) + rtw_mesh_path_discard_frame(adapter, xframe_to_free); + +endlookup: + rtw_rcu_read_unlock(); + return ret; +} + +/** + * rtw_mesh_nexthop_lookup - put the appropriate next hop on a mesh frame. Calling + * this function is considered "using" the associated mpath, so preempt a path + * refresh if this mpath expires soon. + * + * @skb: 802.11 frame to be sent + * @sdata: network subif the frame will be sent through + * + * Returns: 0 if the next hop was found. Nonzero otherwise. + */ +int rtw_mesh_nexthop_lookup(_adapter *adapter, + const u8 *mda, const u8 *msa, u8 *ra) +{ + struct rtw_mesh_path *mpath; + struct sta_info *next_hop; + const u8 *target_addr = mda; + int err = -ENOENT; + + rtw_rcu_read_lock(); + mpath = rtw_mesh_path_lookup(adapter, target_addr); + + if (!mpath || !(mpath->flags & RTW_MESH_PATH_ACTIVE)) + goto endlookup; + + if (rtw_time_after(rtw_get_current_time(), + mpath->exp_time - + rtw_ms_to_systime(adapter->mesh_cfg.path_refresh_time)) && + _rtw_memcmp(adapter_mac_addr(adapter), msa, ETH_ALEN) == _TRUE && + !(mpath->flags & RTW_MESH_PATH_RESOLVING) && + !(mpath->flags & RTW_MESH_PATH_FIXED)) { + rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH); + } + + next_hop = rtw_rcu_dereference(mpath->next_hop); + if (next_hop) { + _rtw_memcpy(ra, next_hop->cmn.mac_addr, ETH_ALEN); + err = 0; + } + +endlookup: + rtw_rcu_read_unlock(); + return err; +} + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC +static bool rtw_mesh_data_bmc_to_uc(_adapter *adapter + , const u8 *da, const u8 *sa, const u8 *mda, const u8 *msa + , u8 ae_need, const u8 *ori_ta, u8 mfwd_ttl + , _list *b2u_list, u8 *b2u_num, u32 *b2u_mseq) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct xmit_priv *xmitpriv = &adapter->xmitpriv; + _irqL irqL; + _list *head, *list; + struct sta_info *sta; + char b2u_sta_id[NUM_STA]; + u8 b2u_sta_num = 0; + bool bmc_need = _FALSE; + int i; + + _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + head = &stapriv->asoc_list; + list = get_next(head); + + while ((rtw_end_of_queue_search(head, list)) == _FALSE) { + int stainfo_offset; + + sta = LIST_CONTAINOR(list, struct sta_info, asoc_list); + list = get_next(list); + + stainfo_offset = rtw_stainfo_offset(stapriv, sta); + if (stainfo_offset_valid(stainfo_offset)) + b2u_sta_id[b2u_sta_num++] = stainfo_offset; + } + _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + + if (!b2u_sta_num) + goto exit; + + for (i = 0; i < b2u_sta_num; i++) { + struct xmit_frame *b2uframe; + struct pkt_attrib *attrib; + + sta = rtw_get_stainfo_by_offset(stapriv, b2u_sta_id[i]); + if (!(sta->state & _FW_LINKED) + || _rtw_memcmp(sta->cmn.mac_addr, msa, ETH_ALEN) == _TRUE + || (ori_ta && _rtw_memcmp(sta->cmn.mac_addr, ori_ta, ETH_ALEN) == _TRUE) + || is_broadcast_mac_addr(sta->cmn.mac_addr) + || is_zero_mac_addr(sta->cmn.mac_addr)) + continue; + + b2uframe = rtw_alloc_xmitframe(xmitpriv); + if (!b2uframe) { + bmc_need = _TRUE; + break; + } + + if ((*b2u_num)++ == 0 && !ori_ta) { + *b2u_mseq = (cpu_to_le32(adapter->mesh_info.mesh_seqnum)); + adapter->mesh_info.mesh_seqnum++; + } + + attrib = &b2uframe->attrib; + + attrib->mb2u = 1; + attrib->mseq = *b2u_mseq; + attrib->mfwd_ttl = ori_ta ? mfwd_ttl : 0; + _rtw_memcpy(attrib->ra, sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN); + _rtw_memcpy(attrib->mda, mda, ETH_ALEN); + _rtw_memcpy(attrib->msa, msa, ETH_ALEN); + _rtw_memcpy(attrib->dst, da, ETH_ALEN); + _rtw_memcpy(attrib->src, sa, ETH_ALEN); + attrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA; + + rtw_list_insert_tail(&b2uframe->list, b2u_list); + } + +exit: + return bmc_need; +} + +void dump_mesh_b2u_flags(void *sel, _adapter *adapter) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + + RTW_PRINT_SEL(sel, "%4s %4s\n", "msrc", "mfwd"); + RTW_PRINT_SEL(sel, "0x%02x 0x%02x\n", mcfg->b2u_flags_msrc, mcfg->b2u_flags_mfwd); +} +#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */ + +int rtw_mesh_addr_resolve(_adapter *adapter, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list) +{ + struct pkt_file pktfile; + struct ethhdr etherhdr; + struct pkt_attrib *attrib; + struct rtw_mesh_path *mpath = NULL, *mppath = NULL; + u8 is_da_mcast; + u8 ae_need; +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + bool bmc_need = _TRUE; + u8 b2u_num = 0; + u32 b2u_mseq = 0; +#endif + int res = _SUCCESS; + + _rtw_open_pktfile(pkt, &pktfile); + if (_rtw_pktfile_read(&pktfile, (u8 *)ðerhdr, ETH_HLEN) != ETH_HLEN) { + res = _FAIL; + goto exit; + } + + xframe->pkt = pkt; +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + _rtw_init_listhead(b2u_list); +#endif + + is_da_mcast = IS_MCAST(etherhdr.h_dest); + if (!is_da_mcast) { + struct sta_info *next_hop; + bool mpp_lookup = 1; + + mpath = rtw_mesh_path_lookup(adapter, etherhdr.h_dest); + if (mpath) { + mpp_lookup = 0; + next_hop = rtw_rcu_dereference(mpath->next_hop); + if (!next_hop + || !(mpath->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING)) + ) { + /* mpath is not valid, search mppath */ + mpp_lookup = 1; + } + } + + if (mpp_lookup) { + mppath = rtw_mpp_path_lookup(adapter, etherhdr.h_dest); + if (mppath) + mppath->exp_time = rtw_get_current_time(); + } + + if (mppath && mpath) + rtw_mesh_path_del(adapter, mpath->dst); + + ae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE + || (mppath && _rtw_memcmp(mppath->mpp, etherhdr.h_dest, ETH_ALEN) == _FALSE); + } else { + ae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE; + + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (rtw_msrc_b2u_policy_chk(adapter->mesh_cfg.b2u_flags_msrc, etherhdr.h_dest)) { + bmc_need = rtw_mesh_data_bmc_to_uc(adapter + , etherhdr.h_dest, etherhdr.h_source + , etherhdr.h_dest, adapter_mac_addr(adapter), ae_need, NULL, 0 + , b2u_list, &b2u_num, &b2u_mseq); + if (bmc_need == _FALSE) { + res = RTW_BMC_NO_NEED; + goto exit; + } + } + #endif + } + + attrib = &xframe->attrib; + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (b2u_num) { + attrib->mb2u = 1; + attrib->mseq = b2u_mseq; + } else + attrib->mb2u = 0; +#endif + + attrib->mfwd_ttl = 0; + _rtw_memcpy(attrib->dst, etherhdr.h_dest, ETH_ALEN); + _rtw_memcpy(attrib->src, etherhdr.h_source, ETH_ALEN); + _rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN); + + if (is_da_mcast) { + attrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA; + _rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN); + _rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN); + } else { + attrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA; + _rtw_memcpy(attrib->mda, (mppath && ae_need) ? mppath->mpp : attrib->dst, ETH_ALEN); + _rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN); + /* RA needs to be resolved */ + res = rtw_mesh_nexthop_resolve(adapter, xframe); + } + +exit: + return res; +} + +s8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib) +{ + u8 ret = 0; + switch (mesh_frame_mode) { + case MESH_UCAST_DATA: + attrib->hdrlen = WLAN_HDR_A4_QOS_LEN; + /* mesh flag + mesh TTL + Mesh SN. no ext addr. */ + attrib->meshctrl_len = 6; + break; + case MESH_BMCAST_DATA: + attrib->hdrlen = WLAN_HDR_A3_QOS_LEN; + /* mesh flag + mesh TTL + Mesh SN. no ext addr. */ + attrib->meshctrl_len = 6; + break; + case MESH_UCAST_PX_DATA: + attrib->hdrlen = WLAN_HDR_A4_QOS_LEN; + /* mesh flag + mesh TTL + Mesh SN + extaddr1 + extaddr2. */ + attrib->meshctrl_len = 18; + break; + case MESH_BMCAST_PX_DATA: + attrib->hdrlen = WLAN_HDR_A3_QOS_LEN; + /* mesh flag + mesh TTL + Mesh SN + extaddr1 */ + attrib->meshctrl_len = 12; + break; + default: + RTW_WARN("Invalid mesh frame mode:%u\n", mesh_frame_mode); + ret = -1; + break; + } + + return ret; +} + +void rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf) +{ + struct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)buf; + + _rtw_memset(mctrl, 0, XATTRIB_GET_MCTRL_LEN(attrib)); + + if (attrib->mfwd_ttl + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + || attrib->mb2u + #endif + ) { + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (!attrib->mfwd_ttl) + mctrl->ttl = adapter->mesh_cfg.dot11MeshTTL; + else + #endif + mctrl->ttl = attrib->mfwd_ttl; + + mctrl->seqnum = (cpu_to_le32(attrib->mseq)); + } else { + mctrl->ttl = adapter->mesh_cfg.dot11MeshTTL; + mctrl->seqnum = (cpu_to_le32(adapter->mesh_info.mesh_seqnum)); + adapter->mesh_info.mesh_seqnum++; + } + + switch (attrib->mesh_frame_mode){ + case MESH_UCAST_DATA: + case MESH_BMCAST_DATA: + break; + case MESH_UCAST_PX_DATA: + mctrl->flags |= MESH_FLAGS_AE_A5_A6; + _rtw_memcpy(mctrl->eaddr1, attrib->dst, ETH_ALEN); + _rtw_memcpy(mctrl->eaddr2, attrib->src, ETH_ALEN); + break; + case MESH_BMCAST_PX_DATA: + mctrl->flags |= MESH_FLAGS_AE_A4; + _rtw_memcpy(mctrl->eaddr1, attrib->src, ETH_ALEN); + break; + case MESH_MHOP_UCAST_ACT: + /* TBD */ + break; + case MESH_MHOP_BMCAST_ACT: + /* TBD */ + break; + default: + break; + } +} + +u8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib + , u16 *fctrl, struct rtw_ieee80211_hdr *whdr) +{ + switch (attrib->mesh_frame_mode) { + case MESH_UCAST_DATA: /* 1, 1, RA, TA, mDA(=DA), mSA(=SA) */ + case MESH_UCAST_PX_DATA: /* 1, 1, RA, TA, mDA, mSA, [DA, SA] */ + SetToDs(fctrl); + SetFrDs(fctrl); + _rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN); + _rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN); + _rtw_memcpy(whdr->addr3, attrib->mda, ETH_ALEN); + _rtw_memcpy(whdr->addr4, attrib->msa, ETH_ALEN); + break; + case MESH_BMCAST_DATA: /* 0, 1, RA(DA), TA, mSA(SA) */ + case MESH_BMCAST_PX_DATA: /* 0, 1, RA(DA), TA, mSA, [SA] */ + SetFrDs(fctrl); + _rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN); + _rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN); + _rtw_memcpy(whdr->addr3, attrib->msa, ETH_ALEN); + break; + case MESH_MHOP_UCAST_ACT: + /* TBD */ + RTW_INFO("MESH_MHOP_UCAST_ACT\n"); + break; + case MESH_MHOP_BMCAST_ACT: + /* TBD */ + RTW_INFO("MESH_MHOP_BMCAST_ACT\n"); + break; + default: + RTW_WARN("Invalid mesh frame mode\n"); + break; + } + + return 0; +} + +int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib; + u8 *whdr = get_recvframe_data(rframe); + u8 is_ra_bmc = 0; + u8 a4_shift = 0; + u8 ps; + u8 *qc; + u8 mps_mode = RTW_MESH_PS_UNKNOWN; + sint ret = _FAIL; + + if (!(MLME_STATE(adapter) & WIFI_ASOC_STATE)) + goto exit; + + if (!rattrib->qos) + goto exit; + + switch (rattrib->to_fr_ds) { + case 1: + if (!IS_MCAST(GetAddr1Ptr(whdr))) + goto exit; + *sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr)); + if (*sta == NULL) { + ret = _SUCCESS; /* return _SUCCESS to drop at sta checking */ + goto exit; + } + _rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->mda, GetAddr1Ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->msa, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */ + _rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->src, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */ + _rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN); + is_ra_bmc = 1; + break; + case 3: + if (IS_MCAST(GetAddr1Ptr(whdr))) + goto exit; + *sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr)); + if (*sta == NULL) { + ret = _SUCCESS; /* return _SUCCESS to drop at sta checking */ + goto exit; + } + _rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->mda, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */ + _rtw_memcpy(rattrib->msa, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */ + _rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */ + _rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */ + _rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN); + a4_shift = ETH_ALEN; + break; + default: + goto exit; + } + + qc = whdr + WLAN_HDR_A3_LEN + a4_shift; + ps = GetPwrMgt(whdr); + mps_mode = ps ? (is_ra_bmc || (get_mps_lv(qc)) ? RTW_MESH_PS_DSLEEP : RTW_MESH_PS_LSLEEP) : RTW_MESH_PS_ACTIVE; + + if (ps) { + if (!((*sta)->state & WIFI_SLEEP_STATE)) + stop_sta_xmit(adapter, *sta); + } else { + if ((*sta)->state & WIFI_SLEEP_STATE) + wakeup_sta_to_xmit(adapter, *sta); + } + + if (is_ra_bmc) + (*sta)->nonpeer_mps = mps_mode; + else { + (*sta)->peer_mps = mps_mode; + if (mps_mode != RTW_MESH_PS_ACTIVE && (*sta)->nonpeer_mps == RTW_MESH_PS_ACTIVE) + (*sta)->nonpeer_mps = RTW_MESH_PS_DSLEEP; + } + + if (get_frame_sub_type(whdr) & BIT(6)) { + /* No data, will not indicate to upper layer, temporily count it here */ + count_rx_stats(adapter, rframe, *sta); + ret = RTW_RX_HANDLED; + goto exit; + } + + rattrib->mesh_ctrl_present = get_mctrl_present(qc) ? 1 : 0; + if (!rattrib->mesh_ctrl_present) + goto exit; + + ret = _SUCCESS; + +exit: + return ret; +} + +int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe + , const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa + , u8 *mctrl_len + , const u8 **da, const u8 **sa) +{ + struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib; + u8 mlen; + u8 ae; + int ret = _SUCCESS; + + ae = mctrl->flags & MESH_FLAGS_AE; + mlen = ae_to_mesh_ctrl_len[ae]; + switch (rattrib->to_fr_ds) { + case 1: + *da = mda; + if (ae == MESH_FLAGS_AE_A4) + *sa = mctrl->eaddr1; + else if (ae == 0) + *sa = msa; + else + ret = _FAIL; + break; + case 3: + if (ae == MESH_FLAGS_AE_A5_A6) { + *da = mctrl->eaddr1; + *sa = mctrl->eaddr2; + } else if (ae == 0) { + *da = mda; + *sa = msa; + } else + ret = _FAIL; + break; + default: + ret = _FAIL; + } + + if (ret == _FAIL) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" invalid tfDS:%u AE:%u combination ra="MAC_FMT" ta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), rattrib->to_fr_ds, ae, MAC_ARG(rattrib->ra), MAC_ARG(rattrib->ta)); + #endif + *mctrl_len = 0; + } else + *mctrl_len = mlen; + + return ret; +} + +inline int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe) +{ + struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib; + const u8 *da, *sa; + int ret; + + ret = rtw_mesh_rx_data_validate_mctrl(adapter, rframe + , (struct rtw_ieee80211s_hdr *)(get_recvframe_data(rframe) + rattrib->hdrlen + rattrib->iv_len) + , rattrib->mda, rattrib->msa + , &rattrib->mesh_ctrl_len + , &da, &sa); + + if (ret == _SUCCESS) { + _rtw_memcpy(rattrib->dst, da, ETH_ALEN); + _rtw_memcpy(rattrib->src, sa, ETH_ALEN); + } + + return ret; +} + +/** + * rtw_mesh_rx_nexthop_resolve - lookup next hop; conditionally start path discovery + * + * @skb: 802.11 frame to be sent + * @sdata: network subif the frame will be sent through + * + * Lookup next hop for given skb and start path discovery if no + * forwarding information is found. + * + * Returns: 0 if the next hop was found and -ENOENT if the frame was queued. + * skb is freeed here if no mpath could be allocated. + */ +static int rtw_mesh_rx_nexthop_resolve(_adapter *adapter, + const u8 *mda, const u8 *msa, u8 *ra) +{ + struct rtw_mesh_path *mpath; + struct xmit_frame *xframe_to_free = NULL; + int err = 0; + int ret = _SUCCESS; + + rtw_rcu_read_lock(); + err = rtw_mesh_nexthop_lookup(adapter, mda, msa, ra); + if (!err) + goto endlookup; + + /* no nexthop found, start resolving */ + mpath = rtw_mesh_path_lookup(adapter, mda); + if (!mpath) { + mpath = rtw_mesh_path_add(adapter, mda); + if (IS_ERR(mpath)) { + err = PTR_ERR(mpath); + ret = _FAIL; + goto endlookup; + } + } + + if (!(mpath->flags & RTW_MESH_PATH_RESOLVING)) + rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START); + + ret = _FAIL; + +endlookup: + rtw_rcu_read_unlock(); + return ret; +} + +#define RTW_MESH_DECACHE_BMC 1 +#define RTW_MESH_DECACHE_UC 0 + +#define RTW_MESH_FORWARD_MDA_SELF_COND 1 +int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe + , const u8 *mda, const u8 *msa + , const u8 *da, const u8 *sa + , struct rtw_ieee80211s_hdr *mctrl + , struct xmit_frame **fwd_frame, _list *b2u_list) +{ + _adapter *adapter = rframe->u.hdr.adapter; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib; + struct rtw_mesh_path *mppath; + u8 is_mda_bmc = IS_MCAST(mda); + u8 is_mda_self = !is_mda_bmc && _rtw_memcmp(mda, adapter_mac_addr(adapter), ETH_ALEN); + struct xmit_frame *xframe; + struct pkt_attrib *xattrib; + u8 fwd_ra[ETH_ALEN] = {0}; + u8 fwd_mpp[ETH_ALEN] = {0}; /* forward to other gate */ + u32 fwd_mseq; + int act = 0; + u8 ae_need; +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + bool bmc_need = _TRUE; + u8 b2u_num = 0; +#endif + + /* fwd info lifetime update */ + #if 0 + if (!is_mda_self) + mDA(A3) fwinfo.lifetime + mSA(A4) fwinfo.lifetime + Precursor-to-mDA(A2) fwinfo.lifetime + #endif + + /* update/create pxoxy info for SA, mSA */ + if ((mctrl->flags & MESH_FLAGS_AE) + && sa != msa && _rtw_memcmp(sa, msa, ETH_ALEN) == _FALSE + ) { + const u8 *proxied_addr = sa; + const u8 *mpp_addr = msa; + + rtw_rcu_read_lock(); + mppath = rtw_mpp_path_lookup(adapter, proxied_addr); + if (!mppath) + rtw_mpp_path_add(adapter, proxied_addr, mpp_addr); + else { + enter_critical_bh(&mppath->state_lock); + if (_rtw_memcmp(mppath->mpp, mpp_addr, ETH_ALEN) == _FALSE) + _rtw_memcpy(mppath->mpp, mpp_addr, ETH_ALEN); + mppath->exp_time = rtw_get_current_time(); + exit_critical_bh(&mppath->state_lock); + } + rtw_rcu_read_unlock(); + } + + /* mSA is self, need no further process */ + if (_rtw_memcmp(msa, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE) + goto exit; + + fwd_mseq = le32_to_cpu(mctrl->seqnum); + + /* check duplicate MSDU from mSA */ + if (((RTW_MESH_DECACHE_BMC && is_mda_bmc) + || (RTW_MESH_DECACHE_UC && !is_mda_bmc)) + && rtw_mesh_decache(adapter, msa, fwd_mseq) + ) { + minfo->mshstats.dropped_frames_duplicate++; + goto exit; + } + + if (is_mda_bmc) { + /* mDA is bmc addr */ + act |= RTW_RX_MSDU_ACT_INDICATE; + if (!mcfg->dot11MeshForwarding) + goto exit; + goto fwd_chk; + + } else if (!is_mda_self) { + /* mDA is unicast but not self */ + if (!mcfg->dot11MeshForwarding) { + rtw_mesh_path_error_tx(adapter + , adapter->mesh_cfg.element_ttl + , mda, 0 + , WLAN_REASON_MESH_PATH_NOFORWARD + , rattrib->ta + ); + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" mDA("MAC_FMT") not self, !dot11MeshForwarding\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(mda)); + #endif + goto exit; + } + + if (rtw_mesh_rx_nexthop_resolve(adapter, mda, msa, fwd_ra) != _SUCCESS) { + /* mDA is unknown */ + rtw_mesh_path_error_tx(adapter + , adapter->mesh_cfg.element_ttl + , mda, 0 + , WLAN_REASON_MESH_PATH_NOFORWARD + , rattrib->ta + ); + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" mDA("MAC_FMT") unknown\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(mda)); + #endif + minfo->mshstats.dropped_frames_no_route++; + goto exit; + + } else { + /* mDA is known in fwd info */ + #if 0 + if (TA is not in precursors) + goto exit; + #endif + goto fwd_chk; + } + + } else { + /* mDA is self */ + #if RTW_MESH_FORWARD_MDA_SELF_COND + u8 is_da_self = da == mda || _rtw_memcmp(da, adapter_mac_addr(adapter), ETH_ALEN); + + if (is_da_self) { + /* DA is self, indicate */ + act |= RTW_RX_MSDU_ACT_INDICATE; + goto exit; + } + + /* DA is not self */ + if (rtw_mesh_nexthop_lookup(adapter, da, msa, fwd_ra) == _SUCCESS) { + /* DA is known in fwd info */ + if (!mcfg->dot11MeshForwarding) { + /* path error to? */ + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") not self, !dot11MeshForwarding\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(da)); + #endif + goto exit; + } + mda = da; + goto fwd_chk; + } + + rtw_rcu_read_lock(); + mppath = rtw_mpp_path_lookup(adapter, da); + if (mppath && _rtw_memcmp(mppath->mpp, adapter_mac_addr(adapter), ETH_ALEN) == _FALSE) { + /* DA is reached by the other gate */ + if (!mcfg->dot11MeshForwarding) { + /* path error to? */ + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") is reached by proxy("MAC_FMT"), !dot11MeshForwarding\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp)); + #endif + rtw_rcu_read_unlock(); + goto exit; + } + _rtw_memcpy(fwd_mpp, mppath->mpp, ETH_ALEN); + mda = fwd_mpp; + msa = adapter_mac_addr(adapter); + rtw_rcu_read_unlock(); + + /* resolve RA */ + if (rtw_mesh_nexthop_lookup(adapter, mda, msa, fwd_ra) != _SUCCESS) { + minfo->mshstats.dropped_frames_no_route++; + goto exit; + } + goto fwd_chk; /* forward to other gate */ + } + rtw_rcu_read_unlock(); + + if (!mppath) { + /* DA is unknown */ + #if 0 /* TODO: flags with AE bit */ + rtw_mesh_path_error_tx(adapter + , adapter->mesh_cfg.element_ttl + , mda, adapter->mesh_info.last_sn_update + , WLAN_REASON_MESH_PATH_NOPROXY + , msa + ); + #endif + } + + /* + * indicate to DS for both cases: + * 1.) DA is reached by self + * 2.) DA is unknown + */ + #endif /* RTW_MESH_FORWARD_MDA_SELF_COND */ + act |= RTW_RX_MSDU_ACT_INDICATE; + goto exit; + } + +fwd_chk: + + if (adapter->stapriv.asoc_list_cnt <= 1) + goto exit; + + if (mctrl->ttl == 1) { + minfo->mshstats.dropped_frames_ttl++; + if (!act) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" ttl reaches 0, not forwarding\n" + , FUNC_ADPT_ARG(adapter)); + #endif + } + goto exit; + } + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + _rtw_init_listhead(b2u_list); +#endif + + ae_need = _rtw_memcmp(da , mda, ETH_ALEN) == _FALSE + || _rtw_memcmp(sa , msa, ETH_ALEN) == _FALSE; + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (is_mda_bmc + && rtw_mfwd_b2u_policy_chk(mcfg->b2u_flags_mfwd, mda, rattrib->to_fr_ds == 3) + ) { + bmc_need = rtw_mesh_data_bmc_to_uc(adapter + , da, sa, mda, msa, ae_need, rframe->u.hdr.psta->cmn.mac_addr, mctrl->ttl - 1 + , b2u_list, &b2u_num, &fwd_mseq); + } + + if (bmc_need == _TRUE) +#endif + { + xframe = rtw_alloc_xmitframe(&adapter->xmitpriv); + if (!xframe) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME "FUNC_ADPT_FMT" rtw_alloc_xmitframe fail\n" + , FUNC_ADPT_ARG(adapter)); + #endif + goto exit; + } + + xattrib = &xframe->attrib; + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (b2u_num) + xattrib->mb2u = 1; + else + xattrib->mb2u = 0; +#endif + xattrib->mfwd_ttl = mctrl->ttl - 1; + xattrib->mseq = fwd_mseq; + _rtw_memcpy(xattrib->dst, da, ETH_ALEN); + _rtw_memcpy(xattrib->src, sa, ETH_ALEN); + _rtw_memcpy(xattrib->mda, mda, ETH_ALEN); + _rtw_memcpy(xattrib->msa, msa, ETH_ALEN); + _rtw_memcpy(xattrib->ta, adapter_mac_addr(adapter), ETH_ALEN); + + if (is_mda_bmc) { + xattrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA; + _rtw_memcpy(xattrib->ra, mda, ETH_ALEN); + } else { + xattrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA; + _rtw_memcpy(xattrib->ra, fwd_ra, ETH_ALEN); + } + + *fwd_frame = xframe; + } + + act |= RTW_RX_MSDU_ACT_FORWARD; + if (is_mda_bmc) + minfo->mshstats.fwded_mcast++; + else + minfo->mshstats.fwded_unicast++; + minfo->mshstats.fwded_frames++; + +exit: + return act; +} + +void dump_mesh_stats(void *sel, _adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_stats *stats = &minfo->mshstats; + + RTW_PRINT_SEL(sel, "fwd_bmc:%u\n", stats->fwded_mcast); + RTW_PRINT_SEL(sel, "fwd_uc:%u\n", stats->fwded_unicast); + + RTW_PRINT_SEL(sel, "drop_ttl:%u\n", stats->dropped_frames_ttl); + RTW_PRINT_SEL(sel, "drop_no_route:%u\n", stats->dropped_frames_no_route); + RTW_PRINT_SEL(sel, "drop_congestion:%u\n", stats->dropped_frames_congestion); + RTW_PRINT_SEL(sel, "drop_dup:%u\n", stats->dropped_frames_duplicate); + + RTW_PRINT_SEL(sel, "mrc_del_qlen:%u\n", stats->mrc_del_qlen); +} +#endif /* CONFIG_RTW_MESH */ + diff --git a/core/mesh/rtw_mesh.h b/core/mesh/rtw_mesh.h new file mode 100644 index 0000000..3a8a6d7 --- /dev/null +++ b/core/mesh/rtw_mesh.h @@ -0,0 +1,506 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_MESH_H_ +#define __RTW_MESH_H_ + +#ifndef CONFIG_AP_MODE + #error "CONFIG_RTW_MESH can't be enabled when CONFIG_AP_MODE is not defined\n" +#endif + +#ifndef RTW_MESH_SCAN_RESULT_EXP_MS +#define RTW_MESH_SCAN_RESULT_EXP_MS (10 * 1000) +#endif +#ifndef RTW_MESH_OFFCH_CAND_FIND_INT_MS +#define RTW_MESH_OFFCH_CAND_FIND_INT_MS (10 * 1000) +#endif +#define RTW_MESH_TTL 31 +#define RTW_MESH_PERR_MIN_INT 100 +#define RTW_MESH_DEFAULT_ELEMENT_TTL 31 +#define RTW_MESH_RANN_INTERVAL 5000 +#define RTW_MESH_PATH_TO_ROOT_TIMEOUT 6000 +#define RTW_MESH_DIAM_TRAVERSAL_TIME 50 +#define RTW_MESH_PATH_TIMEOUT 5000 +#define RTW_MESH_PREQ_MIN_INT 10 +#define RTW_MESH_MAX_PREQ_RETRIES 4 +#define RTW_MESH_MIN_DISCOVERY_TIMEOUT (2 * RTW_MESH_DIAM_TRAVERSAL_TIME) +#define RTW_MESH_ROOT_CONFIRMATION_INTERVAL 2000 +#define RTW_MESH_PATH_REFRESH_TIME 1000 +#define RTW_MESH_ROOT_INTERVAL 5000 + +#define RTW_MESH_PLINK_UNKNOWN 0 +#define RTW_MESH_PLINK_LISTEN 1 +#define RTW_MESH_PLINK_OPN_SNT 2 +#define RTW_MESH_PLINK_OPN_RCVD 3 +#define RTW_MESH_PLINK_CNF_RCVD 4 +#define RTW_MESH_PLINK_ESTAB 5 +#define RTW_MESH_PLINK_HOLDING 6 +#define RTW_MESH_PLINK_BLOCKED 7 + +extern const char *_rtw_mesh_plink_str[]; +#define rtw_mesh_plink_str(s) ((s <= RTW_MESH_PLINK_BLOCKED) ? _rtw_mesh_plink_str[s] : _rtw_mesh_plink_str[RTW_MESH_PLINK_UNKNOWN]) + +#define RTW_MESH_PS_UNKNOWN 0 +#define RTW_MESH_PS_ACTIVE 1 +#define RTW_MESH_PS_LSLEEP 2 +#define RTW_MESH_PS_DSLEEP 3 + +extern const char *_rtw_mesh_ps_str[]; +#define rtw_mesh_ps_str(mps) ((mps <= RTW_MESH_PS_DSLEEP) ? _rtw_mesh_ps_str[mps] : _rtw_mesh_ps_str[RTW_MESH_PS_UNKNOWN]) + +#define GET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 0, 0, 8) +#define GET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 1, 0, 8) +#define GET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 2, 0, 8) +#define GET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 3, 0, 8) +#define GET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 4, 0, 8) + +#define GET_MESH_CONF_ELE_MESH_FORMATION(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 8) +#define GET_MESH_CONF_ELE_CTO_MGATE(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 1) +#define GET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 1, 6) +#define GET_MESH_CONF_ELE_CTO_AS(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 7, 1) + +#define GET_MESH_CONF_ELE_MESH_CAP(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 8) +#define GET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 1) +#define GET_MESH_CONF_ELE_MCCA_SUP(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 1, 1) +#define GET_MESH_CONF_ELE_MCCA_EN(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 2, 1) +#define GET_MESH_CONF_ELE_FORWARDING(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 3, 1) +#define GET_MESH_CONF_ELE_MBCA_EN(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 4, 1) +#define GET_MESH_CONF_ELE_TBTT_ADJ(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 5, 1) +#define GET_MESH_CONF_ELE_PS_LEVEL(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 6, 1) + +#define SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 0, 0, 8, _val) +#define SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 1, 0, 8, _val) +#define SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 2, 0, 8, _val) +#define SET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 3, 0, 8, _val) +#define SET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 4, 0, 8, _val) + +#define SET_MESH_CONF_ELE_CTO_MGATE(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 0, 1, _val) +#define SET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 1, 6, _val) +#define SET_MESH_CONF_ELE_CTO_AS(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 7, 1, _val) + +#define SET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 0, 1, _val) +#define SET_MESH_CONF_ELE_MCCA_SUP(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 1, 1, _val) +#define SET_MESH_CONF_ELE_MCCA_EN(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 2, 1, _val) +#define SET_MESH_CONF_ELE_FORWARDING(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 3, 1, _val) +#define SET_MESH_CONF_ELE_MBCA_EN(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 4, 1, _val) +#define SET_MESH_CONF_ELE_TBTT_ADJ(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 5, 1, _val) +#define SET_MESH_CONF_ELE_PS_LEVEL(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 6, 1, _val) + +/* Mesh flags */ +#define MESH_FLAGS_AE 0x3 /* mask */ +#define MESH_FLAGS_AE_A4 0x1 +#define MESH_FLAGS_AE_A5_A6 0x2 + +/* Max number of paths */ +#define RTW_MESH_MAX_PATHS 1024 + +#define RTW_PREQ_Q_F_START 0x1 +#define RTW_PREQ_Q_F_REFRESH 0x2 +struct rtw_mesh_preq_queue { + _list list; + u8 dst[ETH_ALEN]; + u8 flags; +}; + +extern const u8 ae_to_mesh_ctrl_len[]; + +enum mesh_frame_type { + MESH_UCAST_DATA = 0x0, + MESH_BMCAST_DATA = 0x1, + MESH_UCAST_PX_DATA = 0x2, + MESH_BMCAST_PX_DATA = 0x3, + MESH_MHOP_UCAST_ACT = 0x4, + MESH_MHOP_BMCAST_ACT = 0x5, +}; + +enum mpath_sel_frame_type { + MPATH_PREQ = 0, + MPATH_PREP, + MPATH_PERR, + MPATH_RANN +}; + +/** + * enum rtw_mesh_deferred_task_flags - mesh deferred tasks + * + * + * + * @RTW_MESH_WORK_HOUSEKEEPING: run the periodic mesh housekeeping tasks + * @RTW_MESH_WORK_ROOT: the mesh root station needs to send a frame + * @RTW_MESH_WORK_DRIFT_ADJUST: time to compensate for clock drift relative to other + * mesh nodes + * @RTW_MESH_WORK_MBSS_CHANGED: rebuild beacon and notify driver of BSS changes + */ +enum rtw_mesh_deferred_task_flags { + RTW_MESH_WORK_HOUSEKEEPING, + RTW_MESH_WORK_ROOT, + RTW_MESH_WORK_DRIFT_ADJUST, + RTW_MESH_WORK_MBSS_CHANGED, +}; + +#define RTW_MESH_MAX_PEER_CANDIDATES 15 /* aid consideration */ +#define RTW_MESH_MAX_PEER_LINKS 8 +#define RTW_MESH_PEER_LINK_TIMEOUT 20 + +#define RTW_MESH_PEER_CONF_DISABLED 0 /* special time value means no confirmation ongoing */ +#if CONFIG_RTW_MESH_PEER_BLACKLIST +#define IS_PEER_CONF_DISABLED(plink) ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED) +#define IS_PEER_CONF_TIMEOUT(plink)(!IS_PEER_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->peer_conf_end_time)) +#define SET_PEER_CONF_DISABLED(plink) (plink)->peer_conf_end_time = RTW_MESH_PEER_CONF_DISABLED +#define SET_PEER_CONF_END_TIME(plink, timeout_ms) \ + do { \ + (plink)->peer_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \ + if ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED) \ + (plink)->peer_conf_end_time++; \ + } while (0) +#else +#define IS_PEER_CONF_DISABLED(plink) 1 +#define IS_PEER_CONF_TIMEOUT(plink) 0 +#define SET_PEER_CONF_DISABLED(plink) do {} while (0) +#define SET_PEER_CONF_END_TIME(plink, timeout_ms) do {} while (0) +#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */ + +#define RTW_MESH_CTO_MGATE_CONF_DISABLED 0 /* special time value means no confirmation ongoing */ +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST +#define IS_CTO_MGATE_CONF_DISABLED(plink) ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED) +#define IS_CTO_MGATE_CONF_TIMEOUT(plink)(!IS_CTO_MGATE_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->cto_mgate_conf_end_time)) +#define SET_CTO_MGATE_CONF_DISABLED(plink) (plink)->cto_mgate_conf_end_time = RTW_MESH_CTO_MGATE_CONF_DISABLED +#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) \ + do { \ + (plink)->cto_mgate_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \ + if ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED) \ + (plink)->cto_mgate_conf_end_time++; \ + } while (0) +#else +#define IS_CTO_MGATE_CONF_DISABLED(plink) 1 +#define IS_CTO_MGATE_CONF_TIMEOUT(plink) 0 +#define SET_CTO_MGATE_CONF_DISABLED(plink) do {} while (0) +#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) do {} while (0) +#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */ + +struct mesh_plink_ent { + u8 valid; + u8 addr[ETH_ALEN]; + u8 plink_state; + +#ifdef CONFIG_RTW_MESH_AEK + u8 aek_valid; + u8 aek[32]; +#endif + + u16 llid; + u16 plid; +#ifndef CONFIG_RTW_MESH_DRIVER_AID + u16 aid; /* aid assigned from upper layer */ +#endif + u16 peer_aid; /* aid assigned from peer */ + + u8 chosen_pmk[16]; + +#ifdef CONFIG_RTW_MESH_AEK + u8 sel_pcs[4]; + u8 l_nonce[32]; + u8 p_nonce[32]; +#endif + +#ifdef CONFIG_RTW_MESH_DRIVER_AID + u8 *tx_conf_ies; + u16 tx_conf_ies_len; +#endif + u8 *rx_conf_ies; + u16 rx_conf_ies_len; + + struct wlan_network *scanned; + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + systime peer_conf_end_time; +#endif +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + systime cto_mgate_conf_end_time; +#endif +}; + +#ifdef CONFIG_RTW_MESH_AEK +#define MESH_PLINK_AEK_VALID(ent) ent->aek_valid +#else +#define MESH_PLINK_AEK_VALID(ent) 0 +#endif + +struct mesh_plink_pool { + _lock lock; + u8 num; /* current ent being used */ + struct mesh_plink_ent ent[RTW_MESH_MAX_PEER_CANDIDATES]; + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + _queue peer_blacklist; +#endif +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + _queue cto_mgate_blacklist; +#endif +}; + +#define RTW_MESH_PEER_CONF_TIMEOUT_MS (20 * 1000) +#define RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS (20 * 1000) +#define RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS (20 * 1000) +#define RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS (20 * 1000) + +struct mesh_peer_sel_policy { + u32 scanr_exp_ms; + +#if CONFIG_RTW_MESH_OFFCH_CAND + u32 offch_find_int_ms; /* 0 means no offch find by driver */ +#endif + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + u32 peer_conf_timeout_ms; + u32 peer_blacklist_timeout_ms; +#endif + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + u8 cto_mgate_require; + u32 cto_mgate_conf_timeout_ms; + u32 cto_mgate_blacklist_timeout_ms; +#endif +}; + +/* b2u flags */ +#define RTW_MESH_B2U_ALL BIT0 +#define RTW_MESH_B2U_GA_UCAST BIT1 /* Group addressed unicast frame, forward only */ +#define RTW_MESH_B2U_BCAST BIT2 +#define RTW_MESH_B2U_IP_MCAST BIT3 + +#define rtw_msrc_b2u_policy_chk(flags, mda) ( \ + (flags & RTW_MESH_B2U_ALL) \ + || ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \ + || ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \ + ) + +#define rtw_mfwd_b2u_policy_chk(flags, mda, ucst) ( \ + (flags & RTW_MESH_B2U_ALL) \ + || ((flags & RTW_MESH_B2U_GA_UCAST) && ucst) \ + || ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \ + || ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \ + ) + +struct rtw_mesh_cfg { + u8 max_peer_links; /* peering limit */ + u32 plink_timeout; /* seconds */ + + u8 dot11MeshTTL; + u8 element_ttl; + u32 path_refresh_time; + u16 dot11MeshHWMPpreqMinInterval; + u16 dot11MeshHWMPnetDiameterTraversalTime; + u32 dot11MeshHWMPactivePathTimeout; + u8 dot11MeshHWMPmaxPREQretries; + u16 min_discovery_timeout; + u16 dot11MeshHWMPconfirmationInterval; + u16 dot11MeshHWMPperrMinInterval; + u8 dot11MeshHWMPRootMode; + BOOLEAN dot11MeshForwarding; + s32 rssi_threshold; /* in dBm, 0: no specified */ + u16 dot11MeshHWMPRannInterval; + BOOLEAN dot11MeshGateAnnouncementProtocol; + u32 dot11MeshHWMPactivePathToRootTimeout; + u16 dot11MeshHWMProotInterval; + u8 path_gate_timeout_factor; + + struct mesh_peer_sel_policy peer_sel_policy; + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + u8 b2u_flags_msrc; + u8 b2u_flags_mfwd; +#endif +}; + +struct rtw_mesh_stats { + u32 fwded_mcast; /* Mesh forwarded multicast frames */ + u32 fwded_unicast; /* Mesh forwarded unicast frames */ + u32 fwded_frames; /* Mesh total forwarded frames */ + u32 dropped_frames_ttl; /* Not transmitted since mesh_ttl == 0*/ + u32 dropped_frames_no_route; /* Not transmitted, no route found */ + u32 dropped_frames_congestion;/* Not forwarded due to congestion */ + u32 dropped_frames_duplicate; + + u32 mrc_del_qlen; /* MRC entry deleted cause by queue length limit */ +}; + +struct rtw_mrc; + +struct rtw_mesh_info { + u8 mesh_id[NDIS_802_11_LENGTH_SSID]; + size_t mesh_id_len; + /* Active Path Selection Protocol Identifier */ + u8 mesh_pp_id; + /* Active Path Selection Metric Identifier */ + u8 mesh_pm_id; + /* Congestion Control Mode Identifier */ + u8 mesh_cc_id; + /* Synchronization Protocol Identifier */ + u8 mesh_sp_id; + /* Authentication Protocol Identifier */ + u8 mesh_auth_id; + + struct mesh_plink_pool plink_ctl; + + u32 mesh_seqnum; + /* MSTA's own hwmp sequence number */ + u32 sn; + systime last_preq; + systime last_sn_update; + systime next_perr; + /* Last used Path Discovery ID */ + u32 preq_id; + + ATOMIC_T mpaths; + struct rtw_mesh_table *mesh_paths; + struct rtw_mesh_table *mpp_paths; + int mesh_paths_generation; + int mpp_paths_generation; + + int num_gates; + + struct rtw_mesh_stats mshstats; + + _queue mpath_tx_queue; + u32 mpath_tx_queue_len; + struct tasklet_struct mpath_tx_tasklet; + + struct rtw_mrc *mrc; + + _lock mesh_preq_queue_lock; + struct rtw_mesh_preq_queue preq_queue; + int preq_queue_len; +}; + +extern const char *_action_self_protected_str[]; +#define action_self_protected_str(action) ((action < RTW_ACT_SELF_PROTECTED_NUM) ? _action_self_protected_str[action] : _action_self_protected_str[0]) + +u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len); +u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len + , u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto + , u8 num_of_peerings, bool cto_mgate, bool cto_as + , bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding + , bool mbca_en, bool tbtt_adj, bool ps_level); + +int rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b); +int rtw_bss_is_candidate_mesh_peer(WLAN_BSSID_EX *self, WLAN_BSSID_EX *target, u8 ch, u8 add_peer); + +void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned); + +void rtw_mesh_peer_status_chk(_adapter *adapter); + +#if CONFIG_RTW_MESH_OFFCH_CAND +u8 rtw_mesh_offch_candidate_accepted(_adapter *adapter); +u8 rtw_mesh_select_operating_ch(_adapter *adapter); +#endif + +#if CONFIG_RTW_MESH_PEER_BLACKLIST +int rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr); +int rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr); +int rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr); +void rtw_mesh_peer_blacklist_flush(_adapter *adapter); +void dump_mesh_peer_blacklist(void *sel, _adapter *adapter); +void dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter); +#endif +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST +u8 rtw_mesh_cto_mgate_required(_adapter *adapter); +u8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned); +int rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr); +int rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr); +int rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr); +void rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter); +void dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter); +void dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter); +#endif +void dump_mesh_peer_sel_policy(void *sel, _adapter *adapter); +void dump_mesh_networks(void *sel, _adapter *adapter); + +int rtw_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx); +int rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len); +int rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len); + +unsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe); + +bool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss); +bool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss); +bool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss); + +struct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr); +struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr); +struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx); +int _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr); +int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr); +int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state); +#ifdef CONFIG_RTW_MESH_AEK +int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek); +#endif +#if CONFIG_RTW_MESH_PEER_BLACKLIST +int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr); +#endif +void _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent); +int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr); +void rtw_mesh_plink_ctl_init(_adapter *adapter); +void rtw_mesh_plink_ctl_deinit(_adapter *adapter); +void dump_mesh_plink_ctl(void *sel, _adapter *adapter); + +int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *plink, struct sta_info *sta); +void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink); +void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr); +u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps); + +unsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe); + +void rtw_mesh_cfg_init(_adapter *adapter); +void rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf); +void rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf); +void rtw_mesh_init_mesh_info(_adapter *adapter); +void rtw_mesh_deinit_mesh_info(_adapter *adapter); + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC +void dump_mesh_b2u_flags(void *sel, _adapter *adapter); +#endif + +int rtw_mesh_addr_resolve(_adapter *adapter, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list); + +s8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib); +void rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf); +u8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib + , u16 *fctrl, struct rtw_ieee80211_hdr *whdr); + +int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta); +int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe + , const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa + , u8 *mctrl_len, const u8 **da, const u8 **sa); +int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe); + +int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe + , const u8 *mda, const u8 *msa + , const u8 *da, const u8 *sa + , struct rtw_ieee80211s_hdr *mctrl + , struct xmit_frame **fwd_frame, _list *b2u_list); + +void dump_mesh_stats(void *sel, _adapter *adapter); + +#if defined(PLATFORM_LINUX) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)) +#define rtw_lockdep_assert_held(l) lockdep_assert_held(l) +#define rtw_lockdep_is_held(l) lockdep_is_held(l) +#else +#error "TBD\n" +#endif + +#include "rtw_mesh_pathtbl.h" +#include "rtw_mesh_hwmp.h" +#endif /* __RTW_MESH_H_ */ + diff --git a/core/mesh/rtw_mesh_hwmp.c b/core/mesh/rtw_mesh_hwmp.c new file mode 100644 index 0000000..bfde360 --- /dev/null +++ b/core/mesh/rtw_mesh_hwmp.c @@ -0,0 +1,1570 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_HWMP_C_ + +#ifdef CONFIG_RTW_MESH +#include +#include + +#define RTW_TEST_FRAME_LEN 8192 +#define RTW_MAX_METRIC 0xffffffff +#define RTW_ARITH_SHIFT 8 +#define RTW_LINK_FAIL_THRESH 95 +#define RTW_MAX_PREQ_QUEUE_LEN 64 +#define RTW_ATLM_REQ_CYCLE 1000 + +#define rtw_ilog2(n) \ +( \ + (n) < 2 ? 0 : \ + (n) & (1ULL << 63) ? 63 : \ + (n) & (1ULL << 62) ? 62 : \ + (n) & (1ULL << 61) ? 61 : \ + (n) & (1ULL << 60) ? 60 : \ + (n) & (1ULL << 59) ? 59 : \ + (n) & (1ULL << 58) ? 58 : \ + (n) & (1ULL << 57) ? 57 : \ + (n) & (1ULL << 56) ? 56 : \ + (n) & (1ULL << 55) ? 55 : \ + (n) & (1ULL << 54) ? 54 : \ + (n) & (1ULL << 53) ? 53 : \ + (n) & (1ULL << 52) ? 52 : \ + (n) & (1ULL << 51) ? 51 : \ + (n) & (1ULL << 50) ? 50 : \ + (n) & (1ULL << 49) ? 49 : \ + (n) & (1ULL << 48) ? 48 : \ + (n) & (1ULL << 47) ? 47 : \ + (n) & (1ULL << 46) ? 46 : \ + (n) & (1ULL << 45) ? 45 : \ + (n) & (1ULL << 44) ? 44 : \ + (n) & (1ULL << 43) ? 43 : \ + (n) & (1ULL << 42) ? 42 : \ + (n) & (1ULL << 41) ? 41 : \ + (n) & (1ULL << 40) ? 40 : \ + (n) & (1ULL << 39) ? 39 : \ + (n) & (1ULL << 38) ? 38 : \ + (n) & (1ULL << 37) ? 37 : \ + (n) & (1ULL << 36) ? 36 : \ + (n) & (1ULL << 35) ? 35 : \ + (n) & (1ULL << 34) ? 34 : \ + (n) & (1ULL << 33) ? 33 : \ + (n) & (1ULL << 32) ? 32 : \ + (n) & (1ULL << 31) ? 31 : \ + (n) & (1ULL << 30) ? 30 : \ + (n) & (1ULL << 29) ? 29 : \ + (n) & (1ULL << 28) ? 28 : \ + (n) & (1ULL << 27) ? 27 : \ + (n) & (1ULL << 26) ? 26 : \ + (n) & (1ULL << 25) ? 25 : \ + (n) & (1ULL << 24) ? 24 : \ + (n) & (1ULL << 23) ? 23 : \ + (n) & (1ULL << 22) ? 22 : \ + (n) & (1ULL << 21) ? 21 : \ + (n) & (1ULL << 20) ? 20 : \ + (n) & (1ULL << 19) ? 19 : \ + (n) & (1ULL << 18) ? 18 : \ + (n) & (1ULL << 17) ? 17 : \ + (n) & (1ULL << 16) ? 16 : \ + (n) & (1ULL << 15) ? 15 : \ + (n) & (1ULL << 14) ? 14 : \ + (n) & (1ULL << 13) ? 13 : \ + (n) & (1ULL << 12) ? 12 : \ + (n) & (1ULL << 11) ? 11 : \ + (n) & (1ULL << 10) ? 10 : \ + (n) & (1ULL << 9) ? 9 : \ + (n) & (1ULL << 8) ? 8 : \ + (n) & (1ULL << 7) ? 7 : \ + (n) & (1ULL << 6) ? 6 : \ + (n) & (1ULL << 5) ? 5 : \ + (n) & (1ULL << 4) ? 4 : \ + (n) & (1ULL << 3) ? 3 : \ + (n) & (1ULL << 2) ? 2 : \ + 1 \ +) + +enum rtw_mpath_frame_type { + RTW_MPATH_PREQ = 0, + RTW_MPATH_PREP, + RTW_MPATH_PERR, + RTW_MPATH_RANN +}; + +static inline u32 rtw_u32_field_get(const u8 *preq_elem, int shift, BOOLEAN ae) +{ + if (ae) + shift += 6; + return LE_BITS_TO_4BYTE(preq_elem + shift, 0, 32); +} + +static inline u16 rtw_u16_field_get(const u8 *preq_elem, int shift, BOOLEAN ae) +{ + if (ae) + shift += 6; + return LE_BITS_TO_2BYTE(preq_elem + shift, 0, 16); +} + +/* HWMP IE processing macros */ +#define RTW_AE_F (1<<6) +#define RTW_AE_F_SET(x) (*x & RTW_AE_F) +#define RTW_PREQ_IE_FLAGS(x) (*(x)) +#define RTW_PREQ_IE_HOPCOUNT(x) (*(x + 1)) +#define RTW_PREQ_IE_TTL(x) (*(x + 2)) +#define RTW_PREQ_IE_PREQ_ID(x) rtw_u32_field_get(x, 3, 0) +#define RTW_PREQ_IE_ORIG_ADDR(x) (x + 7) +#define RTW_PREQ_IE_ORIG_SN(x) rtw_u32_field_get(x, 13, 0) +#define RTW_PREQ_IE_LIFETIME(x) rtw_u32_field_get(x, 17, RTW_AE_F_SET(x)) +#define RTW_PREQ_IE_METRIC(x) rtw_u32_field_get(x, 21, RTW_AE_F_SET(x)) +#define RTW_PREQ_IE_TARGET_F(x) (*(RTW_AE_F_SET(x) ? x + 32 : x + 26)) +#define RTW_PREQ_IE_TARGET_ADDR(x) (RTW_AE_F_SET(x) ? x + 33 : x + 27) +#define RTW_PREQ_IE_TARGET_SN(x) rtw_u32_field_get(x, 33, RTW_AE_F_SET(x)) + +#define RTW_PREP_IE_FLAGS(x) RTW_PREQ_IE_FLAGS(x) +#define RTW_PREP_IE_HOPCOUNT(x) RTW_PREQ_IE_HOPCOUNT(x) +#define RTW_PREP_IE_TTL(x) RTW_PREQ_IE_TTL(x) +#define RTW_PREP_IE_ORIG_ADDR(x) (RTW_AE_F_SET(x) ? x + 27 : x + 21) +#define RTW_PREP_IE_ORIG_SN(x) rtw_u32_field_get(x, 27, RTW_AE_F_SET(x)) +#define RTW_PREP_IE_LIFETIME(x) rtw_u32_field_get(x, 13, RTW_AE_F_SET(x)) +#define RTW_PREP_IE_METRIC(x) rtw_u32_field_get(x, 17, RTW_AE_F_SET(x)) +#define RTW_PREP_IE_TARGET_ADDR(x) (x + 3) +#define RTW_PREP_IE_TARGET_SN(x) rtw_u32_field_get(x, 9, 0) + +#define RTW_PERR_IE_TTL(x) (*(x)) +#define RTW_PERR_IE_TARGET_FLAGS(x) (*(x + 2)) +#define RTW_PERR_IE_TARGET_ADDR(x) (x + 3) +#define RTW_PERR_IE_TARGET_SN(x) rtw_u32_field_get(x, 9, 0) +#define RTW_PERR_IE_TARGET_RCODE(x) rtw_u16_field_get(x, 13, 0) + +#define RTW_TU_TO_SYSTIME(x) (rtw_us_to_systime((x) * 1024)) +#define RTW_TU_TO_EXP_TIME(x) (rtw_get_current_time() + RTW_TU_TO_SYSTIME(x)) +#define RTW_MSEC_TO_TU(x) (x*1000/1024) +#define RTW_SN_GT(x, y) ((s32)(y - x) < 0) +#define RTW_SN_LT(x, y) ((s32)(x - y) < 0) +#define RTW_MAX_SANE_SN_DELTA 32 + +static inline u32 RTW_SN_DELTA(u32 x, u32 y) +{ + return x >= y ? x - y : y - x; +} + +#define rtw_net_traversal_jiffies(adapter) \ + rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPnetDiameterTraversalTime) +#define rtw_default_lifetime(adapter) \ + RTW_MSEC_TO_TU(adapter->mesh_cfg.dot11MeshHWMPactivePathTimeout) +#define rtw_min_preq_int_jiff(adapter) \ + (rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPpreqMinInterval)) +#define rtw_max_preq_retries(adapter) (adapter->mesh_cfg.dot11MeshHWMPmaxPREQretries) +#define rtw_disc_timeout_jiff(adapter) \ + rtw_ms_to_systime(adapter->mesh_cfg.min_discovery_timeout) +#define rtw_root_path_confirmation_jiffies(adapter) \ + rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPconfirmationInterval) + +static inline BOOLEAN rtw_ether_addr_equal(const u8 *addr1, const u8 *addr2) +{ + return _rtw_memcmp(addr1, addr2, ETH_ALEN); +} + +#ifdef PLATFORM_LINUX +#define rtw_print_ratelimit() printk_ratelimit() +#define rtw_mod_timer(ptimer, expires) mod_timer(&(ptimer)->timer, expires) +#else + +#endif + +#define RTW_MESH_EWMA_PRECISION 20 +#define RTW_MESH_EWMA_WEIGHT_RCP 8 +#define RTW_TOTAL_PKT_MIN_THRESHOLD 1 +inline void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e) +{ + e->internal = 0; +} +inline unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e) +{ + return e->internal >> (RTW_MESH_EWMA_PRECISION); +} +inline void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e, + unsigned long val) +{ + unsigned long internal = e->internal; + unsigned long weight_rcp = rtw_ilog2(RTW_MESH_EWMA_WEIGHT_RCP); + unsigned long precision = RTW_MESH_EWMA_PRECISION; + + (e->internal) = internal ? (((internal << weight_rcp) - internal) + + (val << precision)) >> weight_rcp : + (val << precision); +} + +static const u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + +static int rtw_mesh_path_sel_frame_tx(enum rtw_mpath_frame_type mpath_action, u8 flags, + const u8 *originator_addr, u32 originator_sn, + u8 target_flags, const u8 *target, + u32 target_sn, const u8 *da, u8 hopcount, u8 ttl, + u32 lifetime, u32 metric, u32 preq_id, + _adapter *adapter) +{ + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + struct xmit_frame *pmgntframe = NULL; + struct rtw_ieee80211_hdr *pwlanhdr = NULL; + struct pkt_attrib *pattrib = NULL; + u8 category = RTW_WLAN_CATEGORY_MESH; + u8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION; + u16 *fctrl = NULL; + u8 *pos, ie_len; + + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return -1; + + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(adapter, pattrib); + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pos; + + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pos, WIFI_ACTION); + + pos += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen)); + pos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen)); + + switch (mpath_action) { + case RTW_MPATH_PREQ: + RTW_HWMP_DBG("sending PREQ to "MAC_FMT"\n", MAC_ARG(target)); + ie_len = 37; + pattrib->pktlen += (ie_len + 2); + *pos++ = WLAN_EID_PREQ; + break; + case RTW_MPATH_PREP: + RTW_HWMP_DBG("sending PREP to "MAC_FMT"\n", MAC_ARG(originator_addr)); + ie_len = 31; + pattrib->pktlen += (ie_len + 2); + *pos++ = WLAN_EID_PREP; + break; + case RTW_MPATH_RANN: + RTW_HWMP_DBG("sending RANN from "MAC_FMT"\n", MAC_ARG(originator_addr)); + ie_len = sizeof(struct rtw_ieee80211_rann_ie); + pattrib->pktlen += (ie_len + 2); + *pos++ = WLAN_EID_RANN; + break; + default: + rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + return _FAIL; + } + *pos++ = ie_len; + *pos++ = flags; + *pos++ = hopcount; + *pos++ = ttl; + if (mpath_action == RTW_MPATH_PREP) { + _rtw_memcpy(pos, target, ETH_ALEN); + pos += ETH_ALEN; + *(u32 *)pos = cpu_to_le32(target_sn); + pos += 4; + } else { + if (mpath_action == RTW_MPATH_PREQ) { + *(u32 *)pos = cpu_to_le32(preq_id); + pos += 4; + } + _rtw_memcpy(pos, originator_addr, ETH_ALEN); + pos += ETH_ALEN; + *(u32 *)pos = cpu_to_le32(originator_sn); + pos += 4; + } + *(u32 *)pos = cpu_to_le32(lifetime); + pos += 4; + *(u32 *)pos = cpu_to_le32(metric); + pos += 4; + if (mpath_action == RTW_MPATH_PREQ) { + *pos++ = 1; /* support only 1 destination now */ + *pos++ = target_flags; + _rtw_memcpy(pos, target, ETH_ALEN); + pos += ETH_ALEN; + *(u32 *)pos = cpu_to_le32(target_sn); + pos += 4; + } else if (mpath_action == RTW_MPATH_PREP) { + _rtw_memcpy(pos, originator_addr, ETH_ALEN); + pos += ETH_ALEN; + *(u32 *)pos = cpu_to_le32(originator_sn); + pos += 4; + } + + pattrib->last_txcmdsz = pattrib->pktlen; + dump_mgntframe(adapter, pmgntframe); + return 0; +} + +int rtw_mesh_path_error_tx(_adapter *adapter, + u8 ttl, const u8 *target, u32 target_sn, + u16 perr_reason_code, const u8 *ra) +{ + + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + struct xmit_frame *pmgntframe = NULL; + struct rtw_ieee80211_hdr *pwlanhdr = NULL; + struct pkt_attrib *pattrib = NULL; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + u8 category = RTW_WLAN_CATEGORY_MESH; + u8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION; + u8 *pos, ie_len; + u16 *fctrl = NULL; + + if (rtw_time_before(rtw_get_current_time(), minfo->next_perr)) + return -1; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return -1; + + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(adapter, pattrib); + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pos; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pos, WIFI_ACTION); + + pos += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen)); + pos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen)); + + ie_len = 15; + pattrib->pktlen += (2 + ie_len); + *pos++ = WLAN_EID_PERR; + *pos++ = ie_len; + /* ttl */ + *pos++ = ttl; + /* The Number of Destinations N */ + *pos++ = 1; + /* Flags format | B7 | B6 | B5:B0 | = | rsvd | AE | rsvd | */ + *pos = 0; + pos++; + _rtw_memcpy(pos, target, ETH_ALEN); + pos += ETH_ALEN; + *(u32 *)pos = cpu_to_le32(target_sn); + pos += 4; + *(u16 *)pos = cpu_to_le16(perr_reason_code); + + adapter->mesh_info.next_perr = RTW_TU_TO_EXP_TIME( + adapter->mesh_cfg.dot11MeshHWMPperrMinInterval); + pattrib->last_txcmdsz = pattrib->pktlen; + /* Send directly. Rewrite it if deferred tx is needed */ + dump_mgntframe(adapter, pmgntframe); + + RTW_HWMP_DBG("TX PERR toward "MAC_FMT", ra = "MAC_FMT"\n", MAC_ARG(target), MAC_ARG(ra)); + + return 0; +} + +static u32 rtw_get_vht_bitrate(u8 mcs, u8 bw, u8 nss, u8 sgi) +{ + static const u32 base[4][10] = { + { 6500000, + 13000000, + 19500000, + 26000000, + 39000000, + 52000000, + 58500000, + 65000000, + 78000000, + /* not in the spec, but some devices use this: */ + 86500000, + }, + { 13500000, + 27000000, + 40500000, + 54000000, + 81000000, + 108000000, + 121500000, + 135000000, + 162000000, + 180000000, + }, + { 29300000, + 58500000, + 87800000, + 117000000, + 175500000, + 234000000, + 263300000, + 292500000, + 351000000, + 390000000, + }, + { 58500000, + 117000000, + 175500000, + 234000000, + 351000000, + 468000000, + 526500000, + 585000000, + 702000000, + 780000000, + }, + }; + u32 bitrate; + int bw_idx; + + if (mcs > 9) { + RTW_HWMP_INFO("Invalid mcs = %d\n", mcs); + return 0; + } + + if (nss > 4 || nss < 1) { + RTW_HWMP_INFO("Now only support nss = 1, 2, 3, 4\n"); + } + + switch (bw) { + case CHANNEL_WIDTH_160: + bw_idx = 3; + break; + case CHANNEL_WIDTH_80: + bw_idx = 2; + break; + case CHANNEL_WIDTH_40: + bw_idx = 1; + break; + case CHANNEL_WIDTH_20: + bw_idx = 0; + break; + default: + RTW_HWMP_INFO("bw = %d currently not supported\n", bw); + return 0; + } + + bitrate = base[bw_idx][mcs]; + bitrate *= nss; + + if (sgi) + bitrate = (bitrate / 9) * 10; + + /* do NOT round down here */ + return (bitrate + 50000) / 100000; +} + +static u32 rtw_get_ht_bitrate(u8 mcs, u8 bw, u8 sgi) +{ + int modulation, streams, bitrate; + + /* the formula below does only work for MCS values smaller than 32 */ + if (mcs >= 32) { + RTW_HWMP_INFO("Invalid mcs = %d\n", mcs); + return 0; + } + + if (bw > 1) { + RTW_HWMP_INFO("Now HT only support bw = 0(20Mhz), 1(40Mhz)\n"); + return 0; + } + + modulation = mcs & 7; + streams = (mcs >> 3) + 1; + + bitrate = (bw == 1) ? 13500000 : 6500000; + + if (modulation < 4) + bitrate *= (modulation + 1); + else if (modulation == 4) + bitrate *= (modulation + 2); + else + bitrate *= (modulation + 3); + + bitrate *= streams; + + if (sgi) + bitrate = (bitrate / 9) * 10; + + /* do NOT round down here */ + return (bitrate + 50000) / 100000; +} + +/** + * @bw: 0(20Mhz), 1(40Mhz), 2(80Mhz), 3(160Mhz) + * @rate_idx: DESC_RATEXXXX & 0x7f + * @sgi: DESC_RATEXXXX >> 7 + * Returns: bitrate in 100kbps + */ +static u32 rtw_desc_rate_to_bitrate(u8 bw, u8 rate_idx, u8 sgi) +{ + u32 bitrate; + + if (rate_idx <= DESC_RATE54M){ + u16 ofdm_rate[12] = {10, 20, 55, 110, + 60, 90, 120, 180, 240, 360, 480, 540}; + bitrate = ofdm_rate[rate_idx]; + } else if ((DESC_RATEMCS0 <= rate_idx) && + (rate_idx <= DESC_RATEMCS31)) { + u8 mcs = rate_idx - DESC_RATEMCS0; + bitrate = rtw_get_ht_bitrate(mcs, bw, sgi); + } else if ((DESC_RATEVHTSS1MCS0 <= rate_idx) && + (rate_idx <= DESC_RATEVHTSS4MCS9)) { + u8 mcs = (rate_idx - DESC_RATEVHTSS1MCS0) % 10; + u8 nss = ((rate_idx - DESC_RATEVHTSS1MCS0) / 10) + 1; + bitrate = rtw_get_vht_bitrate(mcs, bw, nss, sgi); + } else { + /* 60Ghz ??? */ + bitrate = 1; + } + + return bitrate; +} + +static u32 rtw_airtime_link_metric_get(_adapter *adapter, struct sta_info *sta) +{ + struct dm_struct *dm = adapter_to_phydm(adapter); + int device_constant = phydm_get_plcp(dm, sta->cmn.mac_id) << RTW_ARITH_SHIFT; + u32 test_frame_len = RTW_TEST_FRAME_LEN << RTW_ARITH_SHIFT; + u32 s_unit = 1 << RTW_ARITH_SHIFT; + u32 err; + u16 rate; + u32 tx_time, estimated_retx; + u64 result; + /* The fail_avg should <= 100 here */ + u32 fail_avg = (u32)rtw_ewma_err_rate_read(&sta->metrics.err_rate); + + if (fail_avg > RTW_LINK_FAIL_THRESH) + return RTW_MAX_METRIC; + + rate = sta->metrics.data_rate; + /* rate unit is 100Kbps, min rate = 10 */ + if (rate < 10) { + RTW_HWMP_INFO("rate = %d\n", rate); + return RTW_MAX_METRIC; + } + + err = (fail_avg << RTW_ARITH_SHIFT) / 100; + + /* test_frame_len*10 to adjust the unit of rate(100kbps/unit) */ + tx_time = (device_constant + 10 * test_frame_len / rate); + estimated_retx = ((1 << (2 * RTW_ARITH_SHIFT)) / (s_unit - err)); + result = (tx_time * estimated_retx) >> (2 * RTW_ARITH_SHIFT); + /* Convert us to 0.01 TU(10.24us). x/10.24 = x*100/1024 */ + result = (result * 100) >> 10; + + return (u32)result; +} + +void rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id, + u8 per, u8 rate, + u8 bw, u8 total_pkt) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct sta_info *sta; + u8 rate_idx; + u8 sgi; + + sta = macid_ctl->sta[mac_id]; + if (!sta) + return; + + /* if RA, use reported rate */ + if (adapter->fix_rate == 0xff) { + rate_idx = rate & 0x7f; + sgi = rate >> 7; + } else { + rate_idx = adapter->fix_rate & 0x7f; + sgi = adapter->fix_rate >> 7; + } + sta->metrics.data_rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi); + + if (total_pkt < RTW_TOTAL_PKT_MIN_THRESHOLD) + return; + + /* TBD: sta->metrics.overhead = phydm_get_plcp(void *dm_void, u16 macid); */ + sta->metrics.total_pkt = total_pkt; + + rtw_ewma_err_rate_add(&sta->metrics.err_rate, per); + if (rtw_ewma_err_rate_read(&sta->metrics.err_rate) > + RTW_LINK_FAIL_THRESH) + rtw_mesh_plink_broken(sta); +} + +static void rtw_hwmp_preq_frame_process(_adapter *adapter, + struct rtw_ieee80211_hdr_3addr *mgmt, + const u8 *preq_elem, u32 originator_metric) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; + struct rtw_mesh_path *path = NULL; + const u8 *target_addr, *originator_addr; + const u8 *da; + u8 target_flags, ttl, flags, to_gate_ask = 0; + u32 originator_sn, target_sn, lifetime, target_metric = 0; + BOOLEAN reply = _FALSE; + BOOLEAN forward = _TRUE; + BOOLEAN preq_is_gate; + + /* Update target SN, if present */ + target_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem); + originator_addr = RTW_PREQ_IE_ORIG_ADDR(preq_elem); + target_sn = RTW_PREQ_IE_TARGET_SN(preq_elem); + originator_sn = RTW_PREQ_IE_ORIG_SN(preq_elem); + target_flags = RTW_PREQ_IE_TARGET_F(preq_elem); + /* PREQ gate announcements */ + flags = RTW_PREQ_IE_FLAGS(preq_elem); + preq_is_gate = !!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG); + + RTW_HWMP_DBG("received PREQ from "MAC_FMT"\n", MAC_ARG(originator_addr)); + + if (rtw_ether_addr_equal(target_addr, adapter_mac_addr(adapter))) { + RTW_HWMP_DBG("PREQ is for us\n"); +#ifdef CONFIG_RTW_MESH_ON_DMD_GANN + rtw_rcu_read_lock(); + path = rtw_mesh_path_lookup(adapter, originator_addr); + if (path) { + if (preq_is_gate) + rtw_mesh_path_add_gate(path); + else if (path->is_gate) { + enter_critical_bh(&path->state_lock); + rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); + exit_critical_bh(&path->state_lock); + } + } + path = NULL; + rtw_rcu_read_unlock(); +#endif + forward = _FALSE; + reply = _TRUE; + to_gate_ask = 1; + target_metric = 0; + if (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update + + rtw_net_traversal_jiffies(adapter)) || + rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) { + ++minfo->sn; + minfo->last_sn_update = rtw_get_current_time(); + } + target_sn = minfo->sn; + } else if (is_broadcast_mac_addr(target_addr) && + (target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) { + rtw_rcu_read_lock(); + path = rtw_mesh_path_lookup(adapter, originator_addr); + if (path) { + if (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) { + reply = _TRUE; + target_addr = adapter_mac_addr(adapter); + target_sn = ++minfo->sn; + target_metric = 0; + minfo->last_sn_update = rtw_get_current_time(); + } + + if (preq_is_gate) { + lifetime = RTW_PREQ_IE_LIFETIME(preq_elem); + path->gate_ann_int = lifetime; + path->gate_asked = false; + rtw_mesh_path_add_gate(path); + } else if (path->is_gate) { + enter_critical_bh(&path->state_lock); + rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); + exit_critical_bh(&path->state_lock); + } + } + rtw_rcu_read_unlock(); + } else { + rtw_rcu_read_lock(); +#ifdef CONFIG_RTW_MESH_ON_DMD_GANN + path = rtw_mesh_path_lookup(adapter, originator_addr); + if (path) { + if (preq_is_gate) + rtw_mesh_path_add_gate(path); + else if (path->is_gate) { + enter_critical_bh(&path->state_lock); + rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); + exit_critical_bh(&path->state_lock); + } + } + path = NULL; +#endif + path = rtw_mesh_path_lookup(adapter, target_addr); + if (path) { + if ((!(path->flags & RTW_MESH_PATH_SN_VALID)) || + RTW_SN_LT(path->sn, target_sn)) { + path->sn = target_sn; + path->flags |= RTW_MESH_PATH_SN_VALID; + } else if ((!(target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) && + (path->flags & RTW_MESH_PATH_ACTIVE)) { + reply = _TRUE; + target_metric = path->metric; + target_sn = path->sn; + /* Case E2 of sec 13.10.9.3 IEEE 802.11-2012*/ + target_flags |= RTW_IEEE80211_PREQ_TO_FLAG; + } + } + rtw_rcu_read_unlock(); + } + + if (reply) { + lifetime = RTW_PREQ_IE_LIFETIME(preq_elem); + ttl = mshcfg->element_ttl; + if (ttl != 0 && !to_gate_ask) { + RTW_HWMP_DBG("replying to the PREQ\n"); + rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, 0, originator_addr, + originator_sn, 0, target_addr, + target_sn, mgmt->addr2, 0, ttl, + lifetime, target_metric, 0, + adapter); + } else if (ttl != 0 && to_gate_ask) { + RTW_HWMP_DBG("replying to the PREQ (PREQ for us)\n"); + if (mshcfg->dot11MeshGateAnnouncementProtocol) { + /* BIT 7 is used to identify the prep is from mesh gate */ + to_gate_ask = RTW_IEEE80211_PREQ_IS_GATE_FLAG | BIT(7); + } else { + to_gate_ask = 0; + } + + rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, to_gate_ask, originator_addr, + originator_sn, 0, target_addr, + target_sn, mgmt->addr2, 0, ttl, + lifetime, target_metric, 0, + adapter); + } else { + minfo->mshstats.dropped_frames_ttl++; + } + } + + if (forward && mshcfg->dot11MeshForwarding) { + u32 preq_id; + u8 hopcount; + + ttl = RTW_PREQ_IE_TTL(preq_elem); + lifetime = RTW_PREQ_IE_LIFETIME(preq_elem); + if (ttl <= 1) { + minfo->mshstats.dropped_frames_ttl++; + return; + } + RTW_HWMP_DBG("forwarding the PREQ from "MAC_FMT"\n", MAC_ARG(originator_addr)); + --ttl; + preq_id = RTW_PREQ_IE_PREQ_ID(preq_elem); + hopcount = RTW_PREQ_IE_HOPCOUNT(preq_elem) + 1; + da = (path && path->is_root) ? + path->rann_snd_addr : bcast_addr; + + if (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) { + target_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem); + target_sn = RTW_PREQ_IE_TARGET_SN(preq_elem); + } + + rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, originator_addr, + originator_sn, target_flags, target_addr, + target_sn, da, hopcount, ttl, lifetime, + originator_metric, preq_id, adapter); + if (!is_multicast_mac_addr(da)) + minfo->mshstats.fwded_unicast++; + else + minfo->mshstats.fwded_mcast++; + minfo->mshstats.fwded_frames++; + } +} + +static inline struct sta_info * +rtw_next_hop_deref_protected(struct rtw_mesh_path *path) +{ + return rtw_rcu_dereference_protected(path->next_hop, + rtw_lockdep_is_held(&path->state_lock)); +} + +static void rtw_hwmp_prep_frame_process(_adapter *adapter, + struct rtw_ieee80211_hdr_3addr *mgmt, + const u8 *prep_elem, u32 metric) +{ + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; + struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats; + struct rtw_mesh_path *path; + const u8 *target_addr, *originator_addr; + u8 ttl, hopcount, flags; + u8 next_hop[ETH_ALEN]; + u32 target_sn, originator_sn, lifetime; + + RTW_HWMP_DBG("received PREP from "MAC_FMT"\n", + MAC_ARG(RTW_PREP_IE_TARGET_ADDR(prep_elem))); + + originator_addr = RTW_PREP_IE_ORIG_ADDR(prep_elem); + if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) { + /* destination, no forwarding required */ + rtw_rcu_read_lock(); + target_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem); + path = rtw_mesh_path_lookup(adapter, target_addr); + if (path && path->gate_asked) { + enter_critical_bh(&path->state_lock); + path->gate_asked = false; + exit_critical_bh(&path->state_lock); + flags = RTW_PREP_IE_FLAGS(prep_elem); + if ((flags & BIT(7)) && !(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG)) { + enter_critical_bh(&path->state_lock); + rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); + exit_critical_bh(&path->state_lock); + } + } + + rtw_rcu_read_unlock(); + return; + } + + if (!mshcfg->dot11MeshForwarding) + return; + + ttl = RTW_PREP_IE_TTL(prep_elem); + if (ttl <= 1) { + mshstats->dropped_frames_ttl++; + return; + } + + rtw_rcu_read_lock(); + path = rtw_mesh_path_lookup(adapter, originator_addr); + if (path) + enter_critical_bh(&path->state_lock); + else + goto fail; + if (!(path->flags & RTW_MESH_PATH_ACTIVE)) { + exit_critical_bh(&path->state_lock); + goto fail; + } + _rtw_memcpy(next_hop, rtw_next_hop_deref_protected(path)->cmn.mac_addr, ETH_ALEN); + exit_critical_bh(&path->state_lock); + --ttl; + flags = RTW_PREP_IE_FLAGS(prep_elem); + lifetime = RTW_PREP_IE_LIFETIME(prep_elem); + hopcount = RTW_PREP_IE_HOPCOUNT(prep_elem) + 1; + target_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem); + target_sn = RTW_PREP_IE_TARGET_SN(prep_elem); + originator_sn = RTW_PREP_IE_ORIG_SN(prep_elem); + + rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, flags, originator_addr, originator_sn, 0, + target_addr, target_sn, next_hop, hopcount, + ttl, lifetime, metric, 0, adapter); + rtw_rcu_read_unlock(); + + mshstats->fwded_unicast++; + mshstats->fwded_frames++; + return; + +fail: + rtw_rcu_read_unlock(); + mshstats->dropped_frames_no_route++; +} + +static void rtw_hwmp_perr_frame_process(_adapter *adapter, + struct rtw_ieee80211_hdr_3addr *mgmt, + const u8 *perr_elem) +{ + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; + struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats; + struct rtw_mesh_path *path; + u8 ttl; + const u8 *ta, *target_addr; + u32 target_sn; + u16 perr_reason_code; + + ta = mgmt->addr2; + ttl = RTW_PERR_IE_TTL(perr_elem); + if (ttl <= 1) { + mshstats->dropped_frames_ttl++; + return; + } + ttl--; + target_addr = RTW_PERR_IE_TARGET_ADDR(perr_elem); + target_sn = RTW_PERR_IE_TARGET_SN(perr_elem); + perr_reason_code = RTW_PERR_IE_TARGET_RCODE(perr_elem); + + RTW_HWMP_DBG("received PERR toward target "MAC_FMT"\n", MAC_ARG(target_addr)); + + rtw_rcu_read_lock(); + path = rtw_mesh_path_lookup(adapter, target_addr); + if (path) { + struct sta_info *sta; + + enter_critical_bh(&path->state_lock); + sta = rtw_next_hop_deref_protected(path); + if (path->flags & RTW_MESH_PATH_ACTIVE && + rtw_ether_addr_equal(ta, sta->cmn.mac_addr) && + !(path->flags & RTW_MESH_PATH_FIXED) && + (!(path->flags & RTW_MESH_PATH_SN_VALID) || + RTW_SN_GT(target_sn, path->sn) || target_sn == 0)) { + path->flags &= ~RTW_MESH_PATH_ACTIVE; + if (target_sn != 0) + path->sn = target_sn; + else + path->sn += 1; + exit_critical_bh(&path->state_lock); + if (!mshcfg->dot11MeshForwarding) + goto endperr; + rtw_mesh_path_error_tx(adapter, ttl, target_addr, + target_sn, perr_reason_code, + bcast_addr); + } else + exit_critical_bh(&path->state_lock); + } +endperr: + rtw_rcu_read_unlock(); +} + +static void rtw_hwmp_rann_frame_process(_adapter *adapter, + struct rtw_ieee80211_hdr_3addr *mgmt, + const struct rtw_ieee80211_rann_ie *rann) +{ + struct sta_info *sta; + struct sta_priv *pstapriv = &adapter->stapriv; + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; + struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats; + struct rtw_mesh_path *path; + u8 ttl, flags, hopcount; + const u8 *originator_addr; + u32 originator_sn, metric, metric_txsta, interval; + BOOLEAN root_is_gate; + + ttl = rann->rann_ttl; + flags = rann->rann_flags; + root_is_gate = !!(flags & RTW_RANN_FLAG_IS_GATE); + originator_addr = rann->rann_addr; + originator_sn = le32_to_cpu(rann->rann_seq); + interval = le32_to_cpu(rann->rann_interval); + hopcount = rann->rann_hopcount; + hopcount++; + metric = le32_to_cpu(rann->rann_metric); + + /* Ignore our own RANNs */ + if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) + return; + + RTW_HWMP_DBG("received RANN from "MAC_FMT" via neighbour "MAC_FMT" (is_gate=%d)\n", + MAC_ARG(originator_addr), MAC_ARG(mgmt->addr2), root_is_gate); + + rtw_rcu_read_lock(); + sta = rtw_get_stainfo(pstapriv, mgmt->addr2); + if (!sta) { + rtw_rcu_read_unlock(); + return; + } + + metric_txsta = rtw_airtime_link_metric_get(adapter, sta); + + path = rtw_mesh_path_lookup(adapter, originator_addr); + if (!path) { + path = rtw_mesh_path_add(adapter, originator_addr); + if (IS_ERR(path)) { + rtw_rcu_read_unlock(); + mshstats->dropped_frames_no_route++; + return; + } + } + + if (!(RTW_SN_LT(path->sn, originator_sn)) && + !(path->sn == originator_sn && metric < path->rann_metric)) { + rtw_rcu_read_unlock(); + return; + } + + if ((!(path->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING)) || + (rtw_time_after(rtw_get_current_time(), path->last_preq_to_root + + rtw_root_path_confirmation_jiffies(adapter)) || + rtw_time_before(rtw_get_current_time(), path->last_preq_to_root))) && + !(path->flags & RTW_MESH_PATH_FIXED) && (ttl != 0)) { + RTW_HWMP_DBG("time to refresh root path "MAC_FMT"\n", + MAC_ARG(originator_addr)); + rtw_mesh_queue_preq(path, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH); + path->last_preq_to_root = rtw_get_current_time(); + } + + path->sn = originator_sn; + path->rann_metric = metric + metric_txsta; + path->is_root = _TRUE; + /* Recording RANNs sender address to send individually + * addressed PREQs destined for root mesh STA */ + _rtw_memcpy(path->rann_snd_addr, mgmt->addr2, ETH_ALEN); + + if (root_is_gate) { + path->gate_ann_int = interval; + path->gate_asked = false; + rtw_mesh_path_add_gate(path); + } else if (path->is_gate) { + enter_critical_bh(&path->state_lock); + rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); + exit_critical_bh(&path->state_lock); + } + + if (ttl <= 1) { + mshstats->dropped_frames_ttl++; + rtw_rcu_read_unlock(); + return; + } + ttl--; + + if (mshcfg->dot11MeshForwarding) { + rtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, originator_addr, + originator_sn, 0, NULL, 0, bcast_addr, + hopcount, ttl, interval, + metric + metric_txsta, 0, adapter); + } + + rtw_rcu_read_unlock(); +} + +static u32 rtw_hwmp_route_info_get(_adapter *adapter, + struct rtw_ieee80211_hdr_3addr *mgmt, + const u8 *hwmp_ie, enum rtw_mpath_frame_type action) +{ + struct rtw_mesh_path *path; + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *sta; + BOOLEAN fresh_info; + const u8 *originator_addr, *ta; + u32 originator_sn, originator_metric; + unsigned long originator_lifetime, exp_time; + u32 last_hop_metric, new_metric; + BOOLEAN process = _TRUE; + + rtw_rcu_read_lock(); + sta = rtw_get_stainfo(pstapriv, mgmt->addr2); + if (!sta) { + rtw_rcu_read_unlock(); + return 0; + } + + last_hop_metric = rtw_airtime_link_metric_get(adapter, sta); + /* Update and check originator routing info */ + fresh_info = _TRUE; + + switch (action) { + case RTW_MPATH_PREQ: + originator_addr = RTW_PREQ_IE_ORIG_ADDR(hwmp_ie); + originator_sn = RTW_PREQ_IE_ORIG_SN(hwmp_ie); + originator_lifetime = RTW_PREQ_IE_LIFETIME(hwmp_ie); + originator_metric = RTW_PREQ_IE_METRIC(hwmp_ie); + break; + case RTW_MPATH_PREP: + /* Note: For coding, the naming is not consist with spec */ + originator_addr = RTW_PREP_IE_TARGET_ADDR(hwmp_ie); + originator_sn = RTW_PREP_IE_TARGET_SN(hwmp_ie); + originator_lifetime = RTW_PREP_IE_LIFETIME(hwmp_ie); + originator_metric = RTW_PREP_IE_METRIC(hwmp_ie); + break; + default: + rtw_rcu_read_unlock(); + return 0; + } + new_metric = originator_metric + last_hop_metric; + if (new_metric < originator_metric) + new_metric = RTW_MAX_METRIC; + exp_time = RTW_TU_TO_EXP_TIME(originator_lifetime); + + if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) { + process = _FALSE; + fresh_info = _FALSE; + } else { + path = rtw_mesh_path_lookup(adapter, originator_addr); + if (path) { + enter_critical_bh(&path->state_lock); + if (path->flags & RTW_MESH_PATH_FIXED) + fresh_info = _FALSE; + else if ((path->flags & RTW_MESH_PATH_ACTIVE) && + (path->flags & RTW_MESH_PATH_SN_VALID)) { + if (RTW_SN_GT(path->sn, originator_sn) || + (path->sn == originator_sn && + new_metric >= path->metric)) { + process = _FALSE; + fresh_info = _FALSE; + } + } else if (!(path->flags & RTW_MESH_PATH_ACTIVE)) { + BOOLEAN have_sn, newer_sn, bounced; + + have_sn = path->flags & RTW_MESH_PATH_SN_VALID; + newer_sn = have_sn && RTW_SN_GT(originator_sn, path->sn); + bounced = have_sn && + (RTW_SN_DELTA(originator_sn, path->sn) > + RTW_MAX_SANE_SN_DELTA); + + if (!have_sn || newer_sn) { + } else if (bounced) { + } else { + process = _FALSE; + fresh_info = _FALSE; + } + } + } else { + path = rtw_mesh_path_add(adapter, originator_addr); + if (IS_ERR(path)) { + rtw_rcu_read_unlock(); + return 0; + } + enter_critical_bh(&path->state_lock); + } + + if (fresh_info) { + rtw_mesh_path_assign_nexthop(path, sta); + path->flags |= RTW_MESH_PATH_SN_VALID; + path->metric = new_metric; + path->sn = originator_sn; + path->exp_time = rtw_time_after(path->exp_time, exp_time) + ? path->exp_time : exp_time; + rtw_mesh_path_activate(path); + exit_critical_bh(&path->state_lock); + rtw_mesh_path_tx_pending(path); + } else + exit_critical_bh(&path->state_lock); + } + + /* Update and check transmitter routing info */ + ta = mgmt->addr2; + if (rtw_ether_addr_equal(originator_addr, ta)) + fresh_info = _FALSE; + else { + fresh_info = _TRUE; + + path = rtw_mesh_path_lookup(adapter, ta); + if (path) { + enter_critical_bh(&path->state_lock); + if ((path->flags & RTW_MESH_PATH_FIXED) || + ((path->flags & RTW_MESH_PATH_ACTIVE) && + (last_hop_metric > path->metric))) + fresh_info = _FALSE; + } else { + path = rtw_mesh_path_add(adapter, ta); + if (IS_ERR(path)) { + rtw_rcu_read_unlock(); + return 0; + } + enter_critical_bh(&path->state_lock); + } + + if (fresh_info) { + rtw_mesh_path_assign_nexthop(path, sta); + path->metric = last_hop_metric; + path->exp_time = rtw_time_after(path->exp_time, exp_time) + ? path->exp_time : exp_time; + rtw_mesh_path_activate(path); + exit_critical_bh(&path->state_lock); + rtw_mesh_path_tx_pending(path); + } else + exit_critical_bh(&path->state_lock); + } + + rtw_rcu_read_unlock(); + + return process ? new_metric : 0; +} + +void rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe) +{ + struct mesh_plink_ent *plink = NULL; + struct rtw_ieee802_11_elems elems; + u32 path_metric; + struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib; + u8 *pframe = rframe->u.hdr.rx_data, *start; + uint frame_len = rframe->u.hdr.len, left; + struct rtw_ieee80211_hdr_3addr *frame_hdr = (struct rtw_ieee80211_hdr_3addr *)pframe; + u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + ParseRes parse_res; + + plink = rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe)); + if (!plink || plink->plink_state != RTW_MESH_PLINK_ESTAB) + return; + + /* Mesh action frame IE offset = 2 */ + attrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + left = frame_len - attrib->hdrlen - attrib->iv_len - attrib->icv_len - 2; + start = pframe + attrib->hdrlen + 2; + + parse_res = rtw_ieee802_11_parse_elems(start, left, &elems, 1); + if (parse_res == ParseFailed) + RTW_HWMP_INFO(FUNC_ADPT_FMT" Path Select Frame ParseFailed\n" + , FUNC_ADPT_ARG(adapter)); + else if (parse_res == ParseUnknown) + RTW_HWMP_INFO(FUNC_ADPT_FMT" Path Select Frame ParseUnknown\n" + , FUNC_ADPT_ARG(adapter)); + + if (elems.preq) { + if (elems.preq_len != 37) + /* Right now we support just 1 destination and no AE */ + return; + path_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.preq, + MPATH_PREQ); + if (path_metric) + rtw_hwmp_preq_frame_process(adapter, frame_hdr, elems.preq, + path_metric); + } + if (elems.prep) { + if (elems.prep_len != 31) + /* Right now we support no AE */ + return; + path_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.prep, + MPATH_PREP); + if (path_metric) + rtw_hwmp_prep_frame_process(adapter, frame_hdr, elems.prep, + path_metric); + } + if (elems.perr) { + if (elems.perr_len != 15) + /* Right now we support only one destination per PERR */ + return; + rtw_hwmp_perr_frame_process(adapter, frame_hdr, elems.perr); + } + if (elems.rann) + rtw_hwmp_rann_frame_process(adapter, frame_hdr, (struct rtw_ieee80211_rann_ie *)elems.rann); +} + +void rtw_mesh_queue_preq(struct rtw_mesh_path *path, u8 flags) +{ + _adapter *adapter = path->adapter; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_preq_queue *preq_node; + + preq_node = rtw_malloc(sizeof(struct rtw_mesh_preq_queue)); + if (!preq_node) { + RTW_HWMP_INFO("could not allocate PREQ node\n"); + return; + } + + enter_critical_bh(&minfo->mesh_preq_queue_lock); + if (minfo->preq_queue_len == RTW_MAX_PREQ_QUEUE_LEN) { + exit_critical_bh(&minfo->mesh_preq_queue_lock); + rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue)); + if (rtw_print_ratelimit()) + RTW_HWMP_INFO("PREQ node queue full\n"); + return; + } + + _rtw_spinlock(&path->state_lock); + if (path->flags & RTW_MESH_PATH_REQ_QUEUED) { + _rtw_spinunlock(&path->state_lock); + exit_critical_bh(&minfo->mesh_preq_queue_lock); + rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue)); + return; + } + + _rtw_memcpy(preq_node->dst, path->dst, ETH_ALEN); + preq_node->flags = flags; + + path->flags |= RTW_MESH_PATH_REQ_QUEUED; + _rtw_spinunlock(&path->state_lock); + + rtw_list_insert_tail(&preq_node->list, &minfo->preq_queue.list); + ++minfo->preq_queue_len; + exit_critical_bh(&minfo->mesh_preq_queue_lock); + + if (rtw_time_after(rtw_get_current_time(), minfo->last_preq + rtw_min_preq_int_jiff(adapter))) + rtw_mesh_work(&adapter->mesh_work); + + else if (rtw_time_before(rtw_get_current_time(), minfo->last_preq)) { + /* systime wrapped around issue */ + minfo->last_preq = rtw_get_current_time() - rtw_min_preq_int_jiff(adapter) - 1; + rtw_mesh_work(&adapter->mesh_work); + } else + rtw_mod_timer(&adapter->mesh_path_timer, minfo->last_preq + + rtw_min_preq_int_jiff(adapter)); +} + +void rtw_mesh_path_start_discovery(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; + struct rtw_mesh_preq_queue *preq_node; + struct rtw_mesh_path *path; + u8 ttl, target_flags = 0; + const u8 *da; + u32 lifetime; + u8 flags = 0; + + enter_critical_bh(&minfo->mesh_preq_queue_lock); + if (!minfo->preq_queue_len || + rtw_time_before(rtw_get_current_time(), minfo->last_preq + + rtw_min_preq_int_jiff(adapter))) { + exit_critical_bh(&minfo->mesh_preq_queue_lock); + return; + } + + preq_node = rtw_list_first_entry(&minfo->preq_queue.list, + struct rtw_mesh_preq_queue, list); + rtw_list_delete(&preq_node->list); /* list_del_init(&preq_node->list); */ + --minfo->preq_queue_len; + exit_critical_bh(&minfo->mesh_preq_queue_lock); + + rtw_rcu_read_lock(); + path = rtw_mesh_path_lookup(adapter, preq_node->dst); + if (!path) + goto enddiscovery; + + enter_critical_bh(&path->state_lock); + if (path->flags & (RTW_MESH_PATH_DELETED | RTW_MESH_PATH_FIXED)) { + exit_critical_bh(&path->state_lock); + goto enddiscovery; + } + path->flags &= ~RTW_MESH_PATH_REQ_QUEUED; + if (preq_node->flags & RTW_PREQ_Q_F_START) { + if (path->flags & RTW_MESH_PATH_RESOLVING) { + exit_critical_bh(&path->state_lock); + goto enddiscovery; + } else { + path->flags &= ~RTW_MESH_PATH_RESOLVED; + path->flags |= RTW_MESH_PATH_RESOLVING; + path->discovery_retries = 0; + path->discovery_timeout = rtw_disc_timeout_jiff(adapter); + } + } else if (!(path->flags & RTW_MESH_PATH_RESOLVING) || + path->flags & RTW_MESH_PATH_RESOLVED) { + path->flags &= ~RTW_MESH_PATH_RESOLVING; + exit_critical_bh(&path->state_lock); + goto enddiscovery; + } + + minfo->last_preq = rtw_get_current_time(); + + if (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update + + rtw_net_traversal_jiffies(adapter)) || + rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) { + ++minfo->sn; + minfo->last_sn_update = rtw_get_current_time(); + } + lifetime = rtw_default_lifetime(adapter); + ttl = mshcfg->element_ttl; + if (ttl == 0) { + minfo->mshstats.dropped_frames_ttl++; + exit_critical_bh(&path->state_lock); + goto enddiscovery; + } + + if (preq_node->flags & RTW_PREQ_Q_F_REFRESH) + target_flags |= RTW_IEEE80211_PREQ_TO_FLAG; + else + target_flags &= ~RTW_IEEE80211_PREQ_TO_FLAG; + + exit_critical_bh(&path->state_lock); + da = (path->is_root) ? path->rann_snd_addr : bcast_addr; +#ifdef CONFIG_RTW_MESH_ON_DMD_GANN + flags = (mshcfg->dot11MeshGateAnnouncementProtocol) + ? RTW_IEEE80211_PREQ_IS_GATE_FLAG : 0; +#endif + rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter), minfo->sn, + target_flags, path->dst, path->sn, da, 0, + ttl, lifetime, 0, minfo->preq_id++, adapter); + rtw_mod_timer(&path->timer, rtw_get_current_time() + path->discovery_timeout); + +enddiscovery: + rtw_rcu_read_unlock(); + rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue)); +} + +void rtw_mesh_path_timer(void *ctx) +{ + struct rtw_mesh_path *path = (void *) ctx; + _adapter *adapter = path->adapter; + int ret; + + /* TBD: Proctect for suspend */ +#if 0 + if (suspending) + return; +#endif + enter_critical_bh(&path->state_lock); + if (path->flags & RTW_MESH_PATH_RESOLVED || + (!(path->flags & RTW_MESH_PATH_RESOLVING))) { + path->flags &= ~(RTW_MESH_PATH_RESOLVING | RTW_MESH_PATH_RESOLVED); + exit_critical_bh(&path->state_lock); + } else if (path->discovery_retries < rtw_max_preq_retries(adapter)) { + ++path->discovery_retries; + path->discovery_timeout *= 2; + path->flags &= ~RTW_MESH_PATH_REQ_QUEUED; + exit_critical_bh(&path->state_lock); + rtw_mesh_queue_preq(path, 0); + } else { + path->flags &= ~(RTW_MESH_PATH_RESOLVING | + RTW_MESH_PATH_RESOLVED | + RTW_MESH_PATH_REQ_QUEUED); + path->exp_time = rtw_get_current_time(); + exit_critical_bh(&path->state_lock); + if (!path->is_gate && rtw_mesh_gate_num(adapter) > 0) { + ret = rtw_mesh_path_send_to_gates(path); + if (ret) + RTW_HWMP_DBG("no gate was reachable\n"); + } else + rtw_mesh_path_flush_pending(path); + } +} + + +void rtw_mesh_path_tx_root_frame(_adapter *adapter) +{ + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + u32 interval = mshcfg->dot11MeshHWMPRannInterval; + u8 flags, target_flags = 0; + + flags = (mshcfg->dot11MeshGateAnnouncementProtocol) + ? RTW_RANN_FLAG_IS_GATE : 0; + + switch (mshcfg->dot11MeshHWMPRootMode) { + case RTW_IEEE80211_PROACTIVE_RANN: + rtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, adapter_mac_addr(adapter), + ++minfo->sn, 0, NULL, 0, bcast_addr, + 0, mshcfg->element_ttl, + interval, 0, 0, adapter); + break; + case RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP: + flags |= RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG; + case RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP: + interval = mshcfg->dot11MeshHWMPactivePathToRootTimeout; + target_flags |= RTW_IEEE80211_PREQ_TO_FLAG | + RTW_IEEE80211_PREQ_USN_FLAG; + rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter), + ++minfo->sn, target_flags, + (u8 *) bcast_addr, 0, bcast_addr, + 0, mshcfg->element_ttl, interval, + 0, minfo->preq_id++, adapter); + break; + default: + RTW_HWMP_INFO("Proactive mechanism not supported\n"); + return; + } +} + +void rtw_mesh_work(_workitem *work) +{ + /* use kernel global workqueue */ + _set_workitem(work); +} + +void rtw_ieee80211_mesh_path_timer(void *ctx) +{ + _adapter *adapter = (_adapter *)ctx; + rtw_mesh_work(&adapter->mesh_work); +} + +void rtw_ieee80211_mesh_path_root_timer(void *ctx) +{ + _adapter *adapter = (_adapter *)ctx; + + rtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags); + + rtw_mesh_work(&adapter->mesh_work); +} + +static void rtw_ieee80211_mesh_rootpath(_adapter *adapter) +{ + u32 interval; + + rtw_mesh_path_tx_root_frame(adapter); + + if (adapter->mesh_cfg.dot11MeshHWMPRootMode == RTW_IEEE80211_PROACTIVE_RANN) + interval = adapter->mesh_cfg.dot11MeshHWMPRannInterval; + else + interval = adapter->mesh_cfg.dot11MeshHWMProotInterval; + + rtw_mod_timer(&adapter->mesh_path_root_timer, + RTW_TU_TO_EXP_TIME(interval)); +} + +BOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter) +{ + BOOLEAN root_enabled = _FALSE; + + if (adapter->mesh_cfg.dot11MeshHWMPRootMode > RTW_IEEE80211_ROOTMODE_ROOT) { + rtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags); + root_enabled = _TRUE; + } + else { + rtw_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags); + /* stop running timer */ + _cancel_timer_ex(&adapter->mesh_path_root_timer); + root_enabled = _FALSE; + } + + return root_enabled; +} + +void rtw_mesh_work_hdl(_workitem *work) +{ + _adapter *adapter = container_of(work, _adapter, mesh_work); + + if (adapter->mesh_info.preq_queue_len && + rtw_time_after(rtw_get_current_time(), + adapter->mesh_info.last_preq + rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPpreqMinInterval))) + rtw_mesh_path_start_discovery(adapter); + + if (rtw_test_and_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags)) + rtw_ieee80211_mesh_rootpath(adapter); +} + +#ifndef RTW_PER_CMD_SUPPORT_FW +static void rtw_update_metric_directly(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u8 i; + + for (i = 0; i < macid_ctl->num; i++) { + u8 role; + role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]); + if (role == H2C_MSR_ROLE_MESH) { + struct sta_info *sta = macid_ctl->sta[i]; + u8 rate_idx, sgi, bw; + u32 rate; + + if (!sta) + continue; + rate_idx = rtw_get_current_tx_rate(adapter, sta); + sgi = rtw_get_current_tx_sgi(adapter, sta); + bw = sta->cmn.bw_mode; + rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi); + sta->metrics.data_rate = rate; + } + } +} +#endif + +void rtw_mesh_atlm_param_req_timer(void *ctx) +{ + _adapter *adapter = (_adapter *)ctx; + u8 ret = _FAIL; + +#ifdef RTW_PER_CMD_SUPPORT_FW + ret = rtw_req_per_cmd(adapter); + if (ret == _FAIL) + RTW_HWMP_INFO("rtw_req_per_cmd fail\n"); +#else + rtw_update_metric_directly(adapter); +#endif + _set_timer(&adapter->mesh_atlm_param_req_timer, RTW_ATLM_REQ_CYCLE); +} + +#endif /* CONFIG_RTW_MESH */ + diff --git a/core/mesh/rtw_mesh_hwmp.h b/core/mesh/rtw_mesh_hwmp.h new file mode 100644 index 0000000..9433417 --- /dev/null +++ b/core/mesh/rtw_mesh_hwmp.h @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_MESH_HWMP_H_ +#define __RTW_MESH_HWMP_H_ + +#ifndef DBG_RTW_HWMP +#define DBG_RTW_HWMP 0 +#endif +#if DBG_RTW_HWMP +#define RTW_HWMP_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg) +#else +#define RTW_HWMP_DBG(fmt, arg...) RTW_DBG(fmt, ##arg) +#endif + +#ifndef INFO_RTW_HWMP +#define INFO_RTW_HWMP 0 +#endif +#if INFO_RTW_HWMP +#define RTW_HWMP_INFO(fmt, arg...) RTW_PRINT(fmt, ##arg) +#else +#define RTW_HWMP_INFO(fmt, arg...) RTW_INFO(fmt, ##arg) +#endif + + +void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e); +unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e); +void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e, unsigned long val); +int rtw_mesh_path_error_tx(_adapter *adapter, + u8 ttl, const u8 *target, u32 target_sn, + u16 target_rcode, const u8 *ra); +void rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id, + u8 per, u8 rate, + u8 bw, u8 total_pkt); +void rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe); +void rtw_mesh_queue_preq(struct rtw_mesh_path *mpath, u8 flags); +void rtw_mesh_path_start_discovery(_adapter *adapter); +void rtw_mesh_path_timer(void *ctx); +void rtw_mesh_path_tx_root_frame(_adapter *adapter); +void rtw_mesh_work_hdl(_workitem *work); +void rtw_ieee80211_mesh_path_timer(void *ctx); +void rtw_ieee80211_mesh_path_root_timer(void *ctx); +BOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter); +void rtw_mesh_work(_workitem *work); +void rtw_mesh_atlm_param_req_timer(void *ctx); + +#endif /* __RTW_MESH_HWMP_H_ */ + + diff --git a/core/mesh/rtw_mesh_pathtbl.c b/core/mesh/rtw_mesh_pathtbl.c new file mode 100644 index 0000000..d1baaa8 --- /dev/null +++ b/core/mesh/rtw_mesh_pathtbl.c @@ -0,0 +1,1082 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_MESH_PATHTBL_C_ + +#ifdef CONFIG_RTW_MESH +#include +#include + +#ifdef PLATFORM_LINUX +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +static void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath) +{ + kfree_rcu(mpath, rcu); + rtw_mstat_update(MSTAT_TYPE_PHY, MSTAT_FREE, sizeof(struct rtw_mesh_path)); +} +#else +static void rtw_mpath_free_rcu_callback(rtw_rcu_head *head) +{ + struct rtw_mesh_path *mpath; + + mpath = container_of(head, struct rtw_mesh_path, rcu); + rtw_mfree(mpath, sizeof(struct rtw_mesh_path)); +} + +static void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath) +{ + call_rcu(&mpath->rcu, rtw_mpath_free_rcu_callback); +} +#endif +#endif /* PLATFORM_LINUX */ + +static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath); + +static u32 rtw_mesh_table_hash(const void *addr, u32 len, u32 seed) +{ + /* Use last four bytes of hw addr as hash index */ + return jhash_1word(*(u32 *)(addr+2), seed); +} + +static const rtw_rhashtable_params rtw_mesh_rht_params = { + .nelem_hint = 2, + .automatic_shrinking = true, + .key_len = ETH_ALEN, + .key_offset = offsetof(struct rtw_mesh_path, dst), + .head_offset = offsetof(struct rtw_mesh_path, rhash), + .hashfn = rtw_mesh_table_hash, +}; + +static inline bool rtw_mpath_expired(struct rtw_mesh_path *mpath) +{ + return (mpath->flags & RTW_MESH_PATH_ACTIVE) && + rtw_time_after(rtw_get_current_time(), mpath->exp_time) && + !(mpath->flags & RTW_MESH_PATH_FIXED); +} + +static void rtw_mesh_path_rht_free(void *ptr, void *tblptr) +{ + struct rtw_mesh_path *mpath = ptr; + struct rtw_mesh_table *tbl = tblptr; + + rtw_mesh_path_free_rcu(tbl, mpath); +} + +static struct rtw_mesh_table *rtw_mesh_table_alloc(void) +{ + struct rtw_mesh_table *newtbl; + + newtbl = rtw_malloc(sizeof(struct rtw_mesh_table)); + if (!newtbl) + return NULL; + + rtw_hlist_head_init(&newtbl->known_gates); + ATOMIC_SET(&newtbl->entries, 0); + _rtw_spinlock_init(&newtbl->gates_lock); + + return newtbl; +} + +static void rtw_mesh_table_free(struct rtw_mesh_table *tbl) +{ + rtw_rhashtable_free_and_destroy(&tbl->rhead, + rtw_mesh_path_rht_free, tbl); + rtw_mfree(tbl, sizeof(struct rtw_mesh_table)); +} + +/** + * + * rtw_mesh_path_assign_nexthop - update mesh path next hop + * + * @mpath: mesh path to update + * @sta: next hop to assign + * + * Locking: mpath->state_lock must be held when calling this function + */ +void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta) +{ + struct xmit_frame *xframe; + _list *list, *head; + + rtw_rcu_assign_pointer(mpath->next_hop, sta); + + enter_critical_bh(&mpath->frame_queue.lock); + head = &mpath->frame_queue.queue; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + xframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + _rtw_memcpy(xframe->attrib.ra, sta->cmn.mac_addr, ETH_ALEN); + } + + exit_critical_bh(&mpath->frame_queue.lock); +} + +static void rtw_prepare_for_gate(struct xmit_frame *xframe, char *dst_addr, + struct rtw_mesh_path *gate_mpath) +{ + struct pkt_attrib *attrib = &xframe->attrib; + char *next_hop; + + if (attrib->mesh_frame_mode == MESH_UCAST_DATA) + attrib->mesh_frame_mode = MESH_UCAST_PX_DATA; + + /* update next hop */ + rtw_rcu_read_lock(); + next_hop = rtw_rcu_dereference(gate_mpath->next_hop)->cmn.mac_addr; + _rtw_memcpy(attrib->ra, next_hop, ETH_ALEN); + rtw_rcu_read_unlock(); + _rtw_memcpy(attrib->mda, dst_addr, ETH_ALEN); +} + +/** + * + * rtw_mesh_path_move_to_queue - Move or copy frames from one mpath queue to another + * + * This function is used to transfer or copy frames from an unresolved mpath to + * a gate mpath. The function also adds the Address Extension field and + * updates the next hop. + * + * If a frame already has an Address Extension field, only the next hop and + * destination addresses are updated. + * + * The gate mpath must be an active mpath with a valid mpath->next_hop. + * + * @mpath: An active mpath the frames will be sent to (i.e. the gate) + * @from_mpath: The failed mpath + * @copy: When true, copy all the frames to the new mpath queue. When false, + * move them. + */ +static void rtw_mesh_path_move_to_queue(struct rtw_mesh_path *gate_mpath, + struct rtw_mesh_path *from_mpath, + bool copy) +{ + struct xmit_frame *fskb; + _list *list, *head; + _list failq; + u32 failq_len; + _irqL flags; + + if (rtw_warn_on(gate_mpath == from_mpath)) + return; + if (rtw_warn_on(!gate_mpath->next_hop)) + return; + + _rtw_init_listhead(&failq); + + _enter_critical_bh(&from_mpath->frame_queue.lock, &flags); + rtw_list_splice_init(&from_mpath->frame_queue.queue, &failq); + failq_len = from_mpath->frame_queue_len; + from_mpath->frame_queue_len = 0; + _exit_critical_bh(&from_mpath->frame_queue.lock, &flags); + + head = &failq; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + if (gate_mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) { + RTW_MPATH_DBG(FUNC_ADPT_FMT" mpath queue for gate %pM is full!\n" + , FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst); + break; + } + + fskb = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + + rtw_list_delete(&fskb->list); + failq_len--; + rtw_prepare_for_gate(fskb, gate_mpath->dst, gate_mpath); + _enter_critical_bh(&gate_mpath->frame_queue.lock, &flags); + rtw_list_insert_tail(&fskb->list, get_list_head(&gate_mpath->frame_queue)); + gate_mpath->frame_queue_len++; + _exit_critical_bh(&gate_mpath->frame_queue.lock, &flags); + + #if 0 /* TODO: copy */ + skb = rtw_skb_copy(fskb); + if (rtw_warn_on(!skb)) + break; + + rtw_prepare_for_gate(skb, gate_mpath->dst, gate_mpath); + skb_queue_tail(&gate_mpath->frame_queue, skb); + + if (copy) + continue; + + __skb_unlink(fskb, &failq); + rtw_skb_free(fskb); + #endif + } + + RTW_MPATH_DBG(FUNC_ADPT_FMT" mpath queue for gate %pM has %d frames\n" + , FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst, gate_mpath->frame_queue_len); + + if (!copy) + return; + + _enter_critical_bh(&from_mpath->frame_queue.lock, &flags); + rtw_list_splice(&failq, &from_mpath->frame_queue.queue); + from_mpath->frame_queue_len += failq_len; + _exit_critical_bh(&from_mpath->frame_queue.lock, &flags); +} + + +static struct rtw_mesh_path *rtw_mpath_lookup(struct rtw_mesh_table *tbl, const u8 *dst) +{ + struct rtw_mesh_path *mpath; + + if (!tbl) + return NULL; + + mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, dst, rtw_mesh_rht_params); + + if (mpath && rtw_mpath_expired(mpath)) { + enter_critical_bh(&mpath->state_lock); + mpath->flags &= ~RTW_MESH_PATH_ACTIVE; + exit_critical_bh(&mpath->state_lock); + } + return mpath; +} + +/** + * rtw_mesh_path_lookup - look up a path in the mesh path table + * @sdata: local subif + * @dst: hardware address (ETH_ALEN length) of destination + * + * Returns: pointer to the mesh path structure, or NULL if not found + * + * Locking: must be called within a read rcu section. + */ +struct rtw_mesh_path * +rtw_mesh_path_lookup(_adapter *adapter, const u8 *dst) +{ + return rtw_mpath_lookup(adapter->mesh_info.mesh_paths, dst); +} + +struct rtw_mesh_path * +rtw_mpp_path_lookup(_adapter *adapter, const u8 *dst) +{ + return rtw_mpath_lookup(adapter->mesh_info.mpp_paths, dst); +} + +static struct rtw_mesh_path * +__rtw_mesh_path_lookup_by_idx(struct rtw_mesh_table *tbl, int idx) +{ + int i = 0, ret; + struct rtw_mesh_path *mpath = NULL; + rtw_rhashtable_iter iter; + + if (!tbl) + return NULL; + + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); + if (ret) + return NULL; + + ret = rtw_rhashtable_walk_start(&iter); + if (ret && ret != -EAGAIN) + goto err; + + while ((mpath = rtw_rhashtable_walk_next(&iter))) { + if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN) + continue; + if (IS_ERR(mpath)) + break; + if (i++ == idx) + break; + } +err: + rtw_rhashtable_walk_stop(&iter); + rtw_rhashtable_walk_exit(&iter); + + if (IS_ERR(mpath) || !mpath) + return NULL; + + if (rtw_mpath_expired(mpath)) { + enter_critical_bh(&mpath->state_lock); + mpath->flags &= ~RTW_MESH_PATH_ACTIVE; + exit_critical_bh(&mpath->state_lock); + } + return mpath; +} + +/** + * rtw_mesh_path_lookup_by_idx - look up a path in the mesh path table by its index + * @idx: index + * @sdata: local subif, or NULL for all entries + * + * Returns: pointer to the mesh path structure, or NULL if not found. + * + * Locking: must be called within a read rcu section. + */ +struct rtw_mesh_path * +rtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx) +{ + return __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mesh_paths, idx); +} + +/** + * rtw_mpp_path_lookup_by_idx - look up a path in the proxy path table by its index + * @idx: index + * @sdata: local subif, or NULL for all entries + * + * Returns: pointer to the proxy path structure, or NULL if not found. + * + * Locking: must be called within a read rcu section. + */ +struct rtw_mesh_path * +rtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx) +{ + return __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mpp_paths, idx); +} + +/** + * rtw_mesh_path_add_gate - add the given mpath to a mesh gate to our path table + * @mpath: gate path to add to table + */ +int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath) +{ + struct rtw_mesh_cfg *mcfg; + struct rtw_mesh_info *minfo; + struct rtw_mesh_table *tbl; + int err, ori_num_gates; + + rtw_rcu_read_lock(); + tbl = mpath->adapter->mesh_info.mesh_paths; + if (!tbl) { + err = -ENOENT; + goto err_rcu; + } + + enter_critical_bh(&mpath->state_lock); + mcfg = &mpath->adapter->mesh_cfg; + mpath->gate_timeout = rtw_get_current_time() + + rtw_ms_to_systime(mcfg->path_gate_timeout_factor * + mpath->gate_ann_int); + if (mpath->is_gate) { + err = -EEXIST; + exit_critical_bh(&mpath->state_lock); + goto err_rcu; + } + + minfo = &mpath->adapter->mesh_info; + mpath->is_gate = true; + _rtw_spinlock(&tbl->gates_lock); + ori_num_gates = minfo->num_gates; + minfo->num_gates++; + rtw_hlist_add_head_rcu(&mpath->gate_list, &tbl->known_gates); + _rtw_spinunlock(&tbl->gates_lock); + + exit_critical_bh(&mpath->state_lock); + + if (ori_num_gates == 0) + update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE); + + RTW_MPATH_DBG( + FUNC_ADPT_FMT" Mesh path: Recorded new gate: %pM. %d known gates\n", + FUNC_ADPT_ARG(mpath->adapter), + mpath->dst, mpath->adapter->mesh_info.num_gates); + err = 0; +err_rcu: + rtw_rcu_read_unlock(); + return err; +} + +/** + * rtw_mesh_gate_del - remove a mesh gate from the list of known gates + * @tbl: table which holds our list of known gates + * @mpath: gate mpath + */ +void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath) +{ + struct rtw_mesh_cfg *mcfg; + struct rtw_mesh_info *minfo; + int ori_num_gates; + + rtw_lockdep_assert_held(&mpath->state_lock); + if (!mpath->is_gate) + return; + + mcfg = &mpath->adapter->mesh_cfg; + minfo = &mpath->adapter->mesh_info; + + mpath->is_gate = false; + enter_critical_bh(&tbl->gates_lock); + rtw_hlist_del_rcu(&mpath->gate_list); + ori_num_gates = minfo->num_gates; + minfo->num_gates--; + exit_critical_bh(&tbl->gates_lock); + + if (ori_num_gates == 1) + update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE); + + RTW_MPATH_DBG( + FUNC_ADPT_FMT" Mesh path: Deleted gate: %pM. %d known gates\n", + FUNC_ADPT_ARG(mpath->adapter), + mpath->dst, mpath->adapter->mesh_info.num_gates); +} + +/** + * rtw_mesh_gate_search - search a mesh gate from the list of known gates + * @tbl: table which holds our list of known gates + * @addr: address of gate + */ +bool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr) +{ + struct rtw_mesh_path *gate; + rtw_hlist_node *node; + bool exist = 0; + + rtw_rcu_read_lock(); + rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) { + if (_rtw_memcmp(gate->dst, addr, ETH_ALEN) == _TRUE) { + exist = 1; + break; + } + } + + rtw_rcu_read_unlock(); + + return exist; +} + +/** + * rtw_mesh_gate_num - number of gates known to this interface + * @sdata: subif data + */ +int rtw_mesh_gate_num(_adapter *adapter) +{ + return adapter->mesh_info.num_gates; +} + +static +struct rtw_mesh_path *rtw_mesh_path_new(_adapter *adapter, + const u8 *dst) +{ + struct rtw_mesh_path *new_mpath; + + new_mpath = rtw_zmalloc(sizeof(struct rtw_mesh_path)); + if (!new_mpath) + return NULL; + + _rtw_memcpy(new_mpath->dst, dst, ETH_ALEN); + _rtw_memset(new_mpath->rann_snd_addr, 0xFF, ETH_ALEN); + new_mpath->is_root = false; + new_mpath->adapter = adapter; + new_mpath->flags = 0; + new_mpath->gate_asked = false; + _rtw_init_queue(&new_mpath->frame_queue); + new_mpath->frame_queue_len = 0; + new_mpath->exp_time = rtw_get_current_time(); + _rtw_spinlock_init(&new_mpath->state_lock); + rtw_init_timer(&new_mpath->timer, adapter, rtw_mesh_path_timer, new_mpath); + + return new_mpath; +} + +/** + * rtw_mesh_path_add - allocate and add a new path to the mesh path table + * @dst: destination address of the path (ETH_ALEN length) + * @sdata: local subif + * + * Returns: 0 on success + * + * State: the initial state of the new path is set to 0 + */ +struct rtw_mesh_path *rtw_mesh_path_add(_adapter *adapter, + const u8 *dst) +{ + struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths; + struct rtw_mesh_path *mpath, *new_mpath; + int ret; + + if (!tbl) + return ERR_PTR(-ENOTSUPP); + + if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE) + /* never add ourselves as neighbours */ + return ERR_PTR(-ENOTSUPP); + + if (is_multicast_mac_addr(dst)) + return ERR_PTR(-ENOTSUPP); + + if (ATOMIC_INC_UNLESS(&adapter->mesh_info.mpaths, RTW_MESH_MAX_MPATHS) == 0) + return ERR_PTR(-ENOSPC); + + new_mpath = rtw_mesh_path_new(adapter, dst); + if (!new_mpath) + return ERR_PTR(-ENOMEM); + + do { + ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead, + &new_mpath->rhash, + rtw_mesh_rht_params); + + if (ret == -EEXIST) + mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, + dst, + rtw_mesh_rht_params); + + } while (unlikely(ret == -EEXIST && !mpath)); + + if (ret && ret != -EEXIST) + return ERR_PTR(ret); + + /* At this point either new_mpath was added, or we found a + * matching entry already in the table; in the latter case + * free the unnecessary new entry. + */ + if (ret == -EEXIST) { + rtw_mfree(new_mpath, sizeof(struct rtw_mesh_path)); + new_mpath = mpath; + } + adapter->mesh_info.mesh_paths_generation++; + return new_mpath; +} + +int rtw_mpp_path_add(_adapter *adapter, + const u8 *dst, const u8 *mpp) +{ + struct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths; + struct rtw_mesh_path *new_mpath; + int ret; + + if (!tbl) + return -ENOTSUPP; + + if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE) + /* never add ourselves as neighbours */ + return -ENOTSUPP; + + if (is_multicast_mac_addr(dst)) + return -ENOTSUPP; + + new_mpath = rtw_mesh_path_new(adapter, dst); + + if (!new_mpath) + return -ENOMEM; + + _rtw_memcpy(new_mpath->mpp, mpp, ETH_ALEN); + ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead, + &new_mpath->rhash, + rtw_mesh_rht_params); + + adapter->mesh_info.mpp_paths_generation++; + return ret; +} + + +/** + * rtw_mesh_plink_broken - deactivates paths and sends perr when a link breaks + * + * @sta: broken peer link + * + * This function must be called from the rate control algorithm if enough + * delivery errors suggest that a peer link is no longer usable. + */ +void rtw_mesh_plink_broken(struct sta_info *sta) +{ + _adapter *adapter = sta->padapter; + struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths; + static const u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + struct rtw_mesh_path *mpath; + rtw_rhashtable_iter iter; + int ret; + + if (!tbl) + return; + + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); + if (ret) + return; + + ret = rtw_rhashtable_walk_start(&iter); + if (ret && ret != -EAGAIN) + goto out; + + while ((mpath = rtw_rhashtable_walk_next(&iter))) { + if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN) + continue; + if (IS_ERR(mpath)) + break; + if (rtw_rcu_access_pointer(mpath->next_hop) == sta && + mpath->flags & RTW_MESH_PATH_ACTIVE && + !(mpath->flags & RTW_MESH_PATH_FIXED)) { + enter_critical_bh(&mpath->state_lock); + mpath->flags &= ~RTW_MESH_PATH_ACTIVE; + ++mpath->sn; + exit_critical_bh(&mpath->state_lock); + rtw_mesh_path_error_tx(adapter, + adapter->mesh_cfg.element_ttl, + mpath->dst, mpath->sn, + WLAN_REASON_MESH_PATH_DEST_UNREACHABLE, bcast); + } + } +out: + rtw_rhashtable_walk_stop(&iter); + rtw_rhashtable_walk_exit(&iter); +} + +static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl, + struct rtw_mesh_path *mpath) +{ + _adapter *adapter = mpath->adapter; + + enter_critical_bh(&mpath->state_lock); + mpath->flags |= RTW_MESH_PATH_RESOLVING | RTW_MESH_PATH_DELETED; + rtw_mesh_gate_del(tbl, mpath); + exit_critical_bh(&mpath->state_lock); + _cancel_timer_ex(&mpath->timer); + ATOMIC_DEC(&adapter->mesh_info.mpaths); + ATOMIC_DEC(&tbl->entries); + _rtw_spinlock_free(&mpath->state_lock); + + rtw_mesh_path_flush_pending(mpath); + + rtw_mpath_free_rcu(mpath); +} + +static void __rtw_mesh_path_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath) +{ + rtw_rhashtable_remove_fast(&tbl->rhead, &mpath->rhash, rtw_mesh_rht_params); + rtw_mesh_path_free_rcu(tbl, mpath); +} + +/** + * rtw_mesh_path_flush_by_nexthop - Deletes mesh paths if their next hop matches + * + * @sta: mesh peer to match + * + * RCU notes: this function is called when a mesh plink transitions from + * PLINK_ESTAB to any other state, since PLINK_ESTAB state is the only one that + * allows path creation. This will happen before the sta can be freed (because + * sta_info_destroy() calls this) so any reader in a rcu read block will be + * protected against the plink disappearing. + */ +void rtw_mesh_path_flush_by_nexthop(struct sta_info *sta) +{ + _adapter *adapter = sta->padapter; + struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths; + struct rtw_mesh_path *mpath; + rtw_rhashtable_iter iter; + int ret; + + if (!tbl) + return; + + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); + if (ret) + return; + + ret = rtw_rhashtable_walk_start(&iter); + if (ret && ret != -EAGAIN) + goto out; + + while ((mpath = rtw_rhashtable_walk_next(&iter))) { + if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN) + continue; + if (IS_ERR(mpath)) + break; + + if (rtw_rcu_access_pointer(mpath->next_hop) == sta) + __rtw_mesh_path_del(tbl, mpath); + } +out: + rtw_rhashtable_walk_stop(&iter); + rtw_rhashtable_walk_exit(&iter); +} + +static void rtw_mpp_flush_by_proxy(_adapter *adapter, + const u8 *proxy) +{ + struct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths; + struct rtw_mesh_path *mpath; + rtw_rhashtable_iter iter; + int ret; + + if (!tbl) + return; + + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); + if (ret) + return; + + ret = rtw_rhashtable_walk_start(&iter); + if (ret && ret != -EAGAIN) + goto out; + + while ((mpath = rtw_rhashtable_walk_next(&iter))) { + if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN) + continue; + if (IS_ERR(mpath)) + break; + + if (_rtw_memcmp(mpath->mpp, proxy, ETH_ALEN) == _TRUE) + __rtw_mesh_path_del(tbl, mpath); + } +out: + rtw_rhashtable_walk_stop(&iter); + rtw_rhashtable_walk_exit(&iter); +} + +static void rtw_table_flush_by_iface(struct rtw_mesh_table *tbl) +{ + struct rtw_mesh_path *mpath; + rtw_rhashtable_iter iter; + int ret; + + if (!tbl) + return; + + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); + if (ret) + return; + + ret = rtw_rhashtable_walk_start(&iter); + if (ret && ret != -EAGAIN) + goto out; + + while ((mpath = rtw_rhashtable_walk_next(&iter))) { + if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN) + continue; + if (IS_ERR(mpath)) + break; + __rtw_mesh_path_del(tbl, mpath); + } +out: + rtw_rhashtable_walk_stop(&iter); + rtw_rhashtable_walk_exit(&iter); +} + +/** + * rtw_mesh_path_flush_by_iface - Deletes all mesh paths associated with a given iface + * + * This function deletes both mesh paths as well as mesh portal paths. + * + * @sdata: interface data to match + * + */ +void rtw_mesh_path_flush_by_iface(_adapter *adapter) +{ + rtw_table_flush_by_iface(adapter->mesh_info.mesh_paths); + rtw_table_flush_by_iface(adapter->mesh_info.mpp_paths); +} + +/** + * rtw_table_path_del - delete a path from the mesh or mpp table + * + * @tbl: mesh or mpp path table + * @sdata: local subif + * @addr: dst address (ETH_ALEN length) + * + * Returns: 0 if successful + */ +static int rtw_table_path_del(struct rtw_mesh_table *tbl, + const u8 *addr) +{ + struct rtw_mesh_path *mpath; + + if (!tbl) + return -ENXIO; + + rtw_rcu_read_lock(); + mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, addr, rtw_mesh_rht_params); + if (!mpath) { + rtw_rcu_read_unlock(); + return -ENXIO; + } + + __rtw_mesh_path_del(tbl, mpath); + rtw_rcu_read_unlock(); + return 0; +} + + +/** + * rtw_mesh_path_del - delete a mesh path from the table + * + * @addr: dst address (ETH_ALEN length) + * @sdata: local subif + * + * Returns: 0 if successful + */ +int rtw_mesh_path_del(_adapter *adapter, const u8 *addr) +{ + int err; + + /* flush relevant mpp entries first */ + rtw_mpp_flush_by_proxy(adapter, addr); + + err = rtw_table_path_del(adapter->mesh_info.mesh_paths, addr); + adapter->mesh_info.mesh_paths_generation++; + return err; +} + +/** + * rtw_mesh_path_tx_pending - sends pending frames in a mesh path queue + * + * @mpath: mesh path to activate + * + * Locking: the state_lock of the mpath structure must NOT be held when calling + * this function. + */ +void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath) +{ + if (mpath->flags & RTW_MESH_PATH_ACTIVE) { + struct rtw_mesh_info *minfo = &mpath->adapter->mesh_info; + _list q; + u32 q_len = 0; + + _rtw_init_listhead(&q); + + /* move to local queue */ + enter_critical_bh(&mpath->frame_queue.lock); + if (mpath->frame_queue_len) { + rtw_list_splice_init(&mpath->frame_queue.queue, &q); + q_len = mpath->frame_queue_len; + mpath->frame_queue_len = 0; + } + exit_critical_bh(&mpath->frame_queue.lock); + + if (q_len) { + /* move to mpath_tx_queue */ + enter_critical_bh(&minfo->mpath_tx_queue.lock); + rtw_list_splice_tail(&q, &minfo->mpath_tx_queue.queue); + minfo->mpath_tx_queue_len += q_len; + exit_critical_bh(&minfo->mpath_tx_queue.lock); + + /* schedule mpath_tx_tasklet */ + tasklet_hi_schedule(&minfo->mpath_tx_tasklet); + } + } +} + +/** + * rtw_mesh_path_send_to_gates - sends pending frames to all known mesh gates + * + * @mpath: mesh path whose queue will be emptied + * + * If there is only one gate, the frames are transferred from the failed mpath + * queue to that gate's queue. If there are more than one gates, the frames + * are copied from each gate to the next. After frames are copied, the + * mpath queues are emptied onto the transmission queue. + */ +int rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath) +{ + _adapter *adapter = mpath->adapter; + struct rtw_mesh_table *tbl; + struct rtw_mesh_path *from_mpath = mpath; + struct rtw_mesh_path *gate; + bool copy = false; + rtw_hlist_node *node; + + tbl = adapter->mesh_info.mesh_paths; + if (!tbl) + return 0; + + rtw_rcu_read_lock(); + rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) { + if (gate->flags & RTW_MESH_PATH_ACTIVE) { + RTW_MPATH_DBG(FUNC_ADPT_FMT" Forwarding to %pM\n", + FUNC_ADPT_ARG(adapter), gate->dst); + rtw_mesh_path_move_to_queue(gate, from_mpath, copy); + from_mpath = gate; + copy = true; + } else { + RTW_MPATH_DBG( + FUNC_ADPT_FMT" Not forwarding to %pM (flags %#x)\n", + FUNC_ADPT_ARG(adapter), gate->dst, gate->flags); + } + } + + rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) { + RTW_MPATH_DBG(FUNC_ADPT_FMT" Sending to %pM\n", + FUNC_ADPT_ARG(adapter), gate->dst); + rtw_mesh_path_tx_pending(gate); + } + rtw_rcu_read_unlock(); + + return (from_mpath == mpath) ? -EHOSTUNREACH : 0; +} + +/** + * rtw_mesh_path_discard_frame - discard a frame whose path could not be resolved + * + * @skb: frame to discard + * @sdata: network subif the frame was to be sent through + * + * Locking: the function must me called within a rcu_read_lock region + */ +void rtw_mesh_path_discard_frame(_adapter *adapter, + struct xmit_frame *xframe) +{ + rtw_free_xmitframe(&adapter->xmitpriv, xframe); + adapter->mesh_info.mshstats.dropped_frames_no_route++; +} + +/** + * rtw_mesh_path_flush_pending - free the pending queue of a mesh path + * + * @mpath: mesh path whose queue has to be freed + * + * Locking: the function must me called within a rcu_read_lock region + */ +void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath) +{ + struct xmit_frame *xframe; + _list *list, *head; + _list tmp; + + _rtw_init_listhead(&tmp); + + enter_critical_bh(&mpath->frame_queue.lock); + rtw_list_splice_init(&mpath->frame_queue.queue, &tmp); + mpath->frame_queue_len = 0; + exit_critical_bh(&mpath->frame_queue.lock); + + head = &tmp; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + xframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&xframe->list); + rtw_mesh_path_discard_frame(mpath->adapter, xframe); + } +} + +/** + * rtw_mesh_path_fix_nexthop - force a specific next hop for a mesh path + * + * @mpath: the mesh path to modify + * @next_hop: the next hop to force + * + * Locking: this function must be called holding mpath->state_lock + */ +void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop) +{ + enter_critical_bh(&mpath->state_lock); + rtw_mesh_path_assign_nexthop(mpath, next_hop); + mpath->sn = 0xffff; + mpath->metric = 0; + mpath->hop_count = 0; + mpath->exp_time = 0; + mpath->flags = RTW_MESH_PATH_FIXED | RTW_MESH_PATH_SN_VALID; + rtw_mesh_path_activate(mpath); + exit_critical_bh(&mpath->state_lock); + rtw_ewma_err_rate_init(&next_hop->metrics.err_rate); + /* init it at a low value - 0 start is tricky */ + rtw_ewma_err_rate_add(&next_hop->metrics.err_rate, 1); + rtw_mesh_path_tx_pending(mpath); +} + +int rtw_mesh_pathtbl_init(_adapter *adapter) +{ + struct rtw_mesh_table *tbl_path, *tbl_mpp; + int ret; + + tbl_path = rtw_mesh_table_alloc(); + if (!tbl_path) + return -ENOMEM; + + tbl_mpp = rtw_mesh_table_alloc(); + if (!tbl_mpp) { + ret = -ENOMEM; + goto free_path; + } + + rtw_rhashtable_init(&tbl_path->rhead, &rtw_mesh_rht_params); + rtw_rhashtable_init(&tbl_mpp->rhead, &rtw_mesh_rht_params); + + adapter->mesh_info.mesh_paths = tbl_path; + adapter->mesh_info.mpp_paths = tbl_mpp; + + return 0; + +free_path: + rtw_mesh_table_free(tbl_path); + return ret; +} + +static +void rtw_mesh_path_tbl_expire(_adapter *adapter, + struct rtw_mesh_table *tbl) +{ + struct rtw_mesh_path *mpath; + rtw_rhashtable_iter iter; + int ret; + + if (!tbl) + return; + + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); + if (ret) + return; + + ret = rtw_rhashtable_walk_start(&iter); + if (ret && ret != -EAGAIN) + goto out; + + while ((mpath = rtw_rhashtable_walk_next(&iter))) { + if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN) + continue; + if (IS_ERR(mpath)) + break; + if ((!(mpath->flags & RTW_MESH_PATH_RESOLVING)) && + (!(mpath->flags & RTW_MESH_PATH_FIXED)) && + rtw_time_after(rtw_get_current_time(), mpath->exp_time + RTW_MESH_PATH_EXPIRE)) + __rtw_mesh_path_del(tbl, mpath); + + if (mpath->is_gate && /* need not to deal with non-gate case */ + rtw_time_after(rtw_get_current_time(), mpath->gate_timeout)) { + RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] expired systime is %lu systime is %lu\n", + FUNC_ADPT_ARG(adapter), mpath->dst, + mpath->gate_timeout, rtw_get_current_time()); + enter_critical_bh(&mpath->state_lock); + if (mpath->gate_asked) { /* asked gate before */ + rtw_mesh_gate_del(tbl, mpath); + exit_critical_bh(&mpath->state_lock); + } else { + mpath->gate_asked = true; + mpath->gate_timeout = rtw_get_current_time() + rtw_ms_to_systime(mpath->gate_ann_int); + exit_critical_bh(&mpath->state_lock); + rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH); + RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] ask mesh gate existence (is_root=%d)\n", + FUNC_ADPT_ARG(adapter), mpath->dst, mpath->is_root); + } + } + } + +out: + rtw_rhashtable_walk_stop(&iter); + rtw_rhashtable_walk_exit(&iter); +} + +void rtw_mesh_path_expire(_adapter *adapter) +{ + rtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mesh_paths); + rtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mpp_paths); +} + +void rtw_mesh_pathtbl_unregister(_adapter *adapter) +{ + if (adapter->mesh_info.mesh_paths) { + rtw_mesh_table_free(adapter->mesh_info.mesh_paths); + adapter->mesh_info.mesh_paths = NULL; + } + + if (adapter->mesh_info.mpp_paths) { + rtw_mesh_table_free(adapter->mesh_info.mpp_paths); + adapter->mesh_info.mpp_paths = NULL; + } +} +#endif /* CONFIG_RTW_MESH */ + diff --git a/core/mesh/rtw_mesh_pathtbl.h b/core/mesh/rtw_mesh_pathtbl.h new file mode 100644 index 0000000..c53477d --- /dev/null +++ b/core/mesh/rtw_mesh_pathtbl.h @@ -0,0 +1,193 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_MESH_PATHTBL_H_ +#define __RTW_MESH_PATHTBL_H_ + +#ifndef DBG_RTW_MPATH +#define DBG_RTW_MPATH 1 +#endif +#if DBG_RTW_MPATH +#define RTW_MPATH_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg) +#else +#define RTW_MPATH_DBG(fmt, arg...) do {} while (0) +#endif + +/** + * enum rtw_mesh_path_flags - mesh path flags + * + * @RTW_MESH_PATH_ACTIVE: the mesh path can be used for forwarding + * @RTW_MESH_PATH_RESOLVING: the discovery process is running for this mesh path + * @RTW_MESH_PATH_SN_VALID: the mesh path contains a valid destination sequence + * number + * @RTW_MESH_PATH_FIXED: the mesh path has been manually set and should not be + * modified + * @RTW_MESH_PATH_RESOLVED: the mesh path can has been resolved + * @RTW_MESH_PATH_REQ_QUEUED: there is an unsent path request for this destination + * already queued up, waiting for the discovery process to start. + * @RTW_MESH_PATH_DELETED: the mesh path has been deleted and should no longer + * be used + * + * RTW_MESH_PATH_RESOLVED is used by the mesh path timer to + * decide when to stop or cancel the mesh path discovery. + */ +enum rtw_mesh_path_flags { + RTW_MESH_PATH_ACTIVE = BIT(0), + RTW_MESH_PATH_RESOLVING = BIT(1), + RTW_MESH_PATH_SN_VALID = BIT(2), + RTW_MESH_PATH_FIXED = BIT(3), + RTW_MESH_PATH_RESOLVED = BIT(4), + RTW_MESH_PATH_REQ_QUEUED = BIT(5), + RTW_MESH_PATH_DELETED = BIT(6), +}; + +/** + * struct rtw_mesh_path - mesh path structure + * + * @dst: mesh path destination mac address + * @mpp: mesh proxy mac address + * @rhash: rhashtable list pointer + * @gate_list: list pointer for known gates list + * @sdata: mesh subif + * @next_hop: mesh neighbor to which frames for this destination will be + * forwarded + * @timer: mesh path discovery timer + * @frame_queue: pending queue for frames sent to this destination while the + * path is unresolved + * @rcu: rcu head for freeing mesh path + * @sn: target sequence number + * @metric: current metric to this destination + * @hop_count: hops to destination + * @exp_time: in jiffies, when the path will expire or when it expired + * @discovery_timeout: timeout (lapse in jiffies) used for the last discovery + * retry + * @discovery_retries: number of discovery retries + * @flags: mesh path flags, as specified on &enum rtw_mesh_path_flags + * @state_lock: mesh path state lock used to protect changes to the + * mpath itself. No need to take this lock when adding or removing + * an mpath to a hash bucket on a path table. + * @rann_snd_addr: the RANN sender address + * @rann_metric: the aggregated path metric towards the root node + * @last_preq_to_root: Timestamp of last PREQ sent to root + * @is_root: the destination station of this path is a root node + * @is_gate: the destination station of this path is a mesh gate + * + * + * The dst address is unique in the mesh path table. Since the mesh_path is + * protected by RCU, deleting the next_hop STA must remove / substitute the + * mesh_path structure and wait until that is no longer reachable before + * destroying the STA completely. + */ +struct rtw_mesh_path { + u8 dst[ETH_ALEN]; + u8 mpp[ETH_ALEN]; /* used for MPP or MAP */ + rtw_rhash_head rhash; + rtw_hlist_node gate_list; + _adapter *adapter; + struct sta_info __rcu *next_hop; + _timer timer; + _queue frame_queue; + u32 frame_queue_len; + rtw_rcu_head rcu; + u32 sn; + u32 metric; + u8 hop_count; + systime exp_time; + systime discovery_timeout; + systime gate_timeout; + u32 gate_ann_int; /* gate announce interval */ + u8 discovery_retries; + enum rtw_mesh_path_flags flags; + _lock state_lock; + u8 rann_snd_addr[ETH_ALEN]; + u32 rann_metric; + unsigned long last_preq_to_root; + bool is_root; + bool is_gate; + bool gate_asked; +}; + +/** + * struct rtw_mesh_table + * + * @known_gates: list of known mesh gates and their mpaths by the station. The + * gate's mpath may or may not be resolved and active. + * @gates_lock: protects updates to known_gates + * @rhead: the rhashtable containing struct mesh_paths, keyed by dest addr + * @entries: number of entries in the table + */ +struct rtw_mesh_table { + rtw_hlist_head known_gates; + _lock gates_lock; + rtw_rhashtable rhead; + ATOMIC_T entries; +}; + +#define RTW_MESH_PATH_EXPIRE (600 * HZ) + +/* Maximum number of paths per interface */ +#define RTW_MESH_MAX_MPATHS 1024 + +/* Number of frames buffered per destination for unresolved destinations */ +#define RTW_MESH_FRAME_QUEUE_LEN 10 + +int rtw_mesh_nexthop_lookup(_adapter *adapter, + const u8 *mda, const u8 *msa, u8 *ra); +int rtw_mesh_nexthop_resolve(_adapter *adapter, + struct xmit_frame *xframe); + +struct rtw_mesh_path *rtw_mesh_path_lookup(_adapter *adapter, + const u8 *dst); +struct rtw_mesh_path *rtw_mpp_path_lookup(_adapter *adapter, + const u8 *dst); +int rtw_mpp_path_add(_adapter *adapter, + const u8 *dst, const u8 *mpp); +struct rtw_mesh_path * +rtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx); +struct rtw_mesh_path * +rtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx); +void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop); +void rtw_mesh_path_expire(_adapter *adapter); + +struct rtw_mesh_path * +rtw_mesh_path_add(_adapter *adapter, const u8 *dst); + +int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath); +void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath); +bool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr); +int rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath); +int rtw_mesh_gate_num(_adapter *adapter); + +void rtw_mesh_plink_broken(struct sta_info *sta); + +void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta); +void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath); +void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath); +int rtw_mesh_pathtbl_init(_adapter *adapter); +void rtw_mesh_pathtbl_unregister(_adapter *adapter); +int rtw_mesh_path_del(_adapter *adapter, const u8 *addr); + +void rtw_mesh_path_flush_by_nexthop(struct sta_info *sta); +void rtw_mesh_path_discard_frame(_adapter *adapter, + struct xmit_frame *xframe); + +static inline void rtw_mesh_path_activate(struct rtw_mesh_path *mpath) +{ + mpath->flags |= RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVED; +} + +void rtw_mesh_path_flush_by_iface(_adapter *adapter); + +#endif /* __RTW_MESH_PATHTBL_H_ */ + diff --git a/core/rtw_rm.c b/core/rtw_rm.c new file mode 100644 index 0000000..0e76b08 --- /dev/null +++ b/core/rtw_rm.c @@ -0,0 +1,2493 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include +#include +#include "rtw_rm_fsm.h" + +#define pstr(s) s+strlen(s) + +u8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf) +{ +#ifdef CONFIG_RTW_80211K + struct rm_event *pev = (struct rm_event *)pbuf; + + _rm_post_event(padapter, pev->rmid, pev->evid); + rm_handler(padapter, pev); +#endif + return H2C_SUCCESS; +} + +#ifdef CONFIG_RTW_80211K + +/* 802.11-2012 Table E-1 Operationg classes in United States */ +static RT_OPERATING_CLASS RTW_OP_CLASS_US[] = { + /* 0, OP_CLASS_NULL */ { 0, 0, {}}, + /* 1, OP_CLASS_1 */ {115, 4, {36, 40, 44, 48}}, + /* 2, OP_CLASS_2 */ {118, 4, {52, 56, 60, 64}}, + /* 3, OP_CLASS_3 */ {124, 4, {149, 153, 157, 161}}, + /* 4, OP_CLASS_4 */ {121, 11, {100, 104, 108, 112, 116, 120, 124, + 128, 132, 136, 140}}, + /* 5, OP_CLASS_5 */ {125, 5, {149, 153, 157, 161, 165}}, + /* 6, OP_CLASS_12 */ { 81, 11, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}} +}; + +struct cmd_meas_type_ { + u8 id; + char *name; +}; + +char *rm_type_req_name(u8 meas_type) { + + switch (meas_type) { + case basic_req: + return "basic_req"; + case cca_req: + return "cca_req"; + case rpi_histo_req: + return "rpi_histo_req"; + case ch_load_req: + return "ch_load_req"; + case noise_histo_req: + return "noise_histo_req"; + case bcn_req: + return "bcn_req"; + case frame_req: + return "frame_req"; + case sta_statis_req: + return "sta_statis_req"; + } + return "unknown_req"; +}; + +char *rm_type_rep_name(u8 meas_type) { + + switch (meas_type) { + case basic_rep: + return "basic_rep"; + case cca_rep: + return "cca_rep"; + case rpi_histo_rep: + return "rpi_histo_rep"; + case ch_load_rep: + return "ch_load_rep"; + case noise_histo_rep: + return "noise_histo_rep"; + case bcn_rep: + return "bcn_rep"; + case frame_rep: + return "frame_rep"; + case sta_statis_rep: + return "sta_statis_rep"; + } + return "unknown_rep"; +}; + +char *rm_en_cap_name(enum rm_cap_en en) +{ + switch (en) { + case RM_LINK_MEAS_CAP_EN: + return "RM_LINK_MEAS_CAP_EN"; + case RM_NB_REP_CAP_EN: + return "RM_NB_REP_CAP_EN"; + case RM_PARAL_MEAS_CAP_EN: + return "RM_PARAL_MEAS_CAP_EN"; + case RM_REPEAT_MEAS_CAP_EN: + return "RM_REPEAT_MEAS_CAP_EN"; + case RM_BCN_PASSIVE_MEAS_CAP_EN: + return "RM_BCN_PASSIVE_MEAS_CAP_EN"; + case RM_BCN_ACTIVE_MEAS_CAP_EN: + return "RM_BCN_ACTIVE_MEAS_CAP_EN"; + case RM_BCN_TABLE_MEAS_CAP_EN: + return "RM_BCN_TABLE_MEAS_CAP_EN"; + case RM_BCN_MEAS_REP_COND_CAP_EN: + return "RM_BCN_MEAS_REP_COND_CAP_EN"; + + case RM_FRAME_MEAS_CAP_EN: + return "RM_FRAME_MEAS_CAP_EN"; + case RM_CH_LOAD_CAP_EN: + return "RM_CH_LOAD_CAP_EN"; + case RM_NOISE_HISTO_CAP_EN: + return "RM_NOISE_HISTO_CAP_EN"; + case RM_STATIS_MEAS_CAP_EN: + return "RM_STATIS_MEAS_CAP_EN"; + case RM_LCI_MEAS_CAP_EN: + return "RM_LCI_MEAS_CAP_EN"; + case RM_LCI_AMIMUTH_CAP_EN: + return "RM_LCI_AMIMUTH_CAP_EN"; + case RM_TRANS_STREAM_CAT_MEAS_CAP_EN: + return "RM_TRANS_STREAM_CAT_MEAS_CAP_EN"; + case RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN: + return "RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN"; + + case RM_AP_CH_REP_CAP_EN: + return "RM_AP_CH_REP_CAP_EN"; + case RM_RM_MIB_CAP_EN: + return "RM_RM_MIB_CAP_EN"; + case RM_OP_CH_MAX_MEAS_DUR0: + return "RM_OP_CH_MAX_MEAS_DUR0"; + case RM_OP_CH_MAX_MEAS_DUR1: + return "RM_OP_CH_MAX_MEAS_DUR1"; + case RM_OP_CH_MAX_MEAS_DUR2: + return "RM_OP_CH_MAX_MEAS_DUR2"; + case RM_NONOP_CH_MAX_MEAS_DUR0: + return "RM_NONOP_CH_MAX_MEAS_DUR0"; + case RM_NONOP_CH_MAX_MEAS_DUR1: + return "RM_NONOP_CH_MAX_MEAS_DUR1"; + case RM_NONOP_CH_MAX_MEAS_DUR2: + return "RM_NONOP_CH_MAX_MEAS_DUR2"; + + case RM_MEAS_PILOT_CAP0: + return "RM_MEAS_PILOT_CAP0"; /* 24-26 */ + case RM_MEAS_PILOT_CAP1: + return "RM_MEAS_PILOT_CAP1"; + case RM_MEAS_PILOT_CAP2: + return "RM_MEAS_PILOT_CAP2"; + case RM_MEAS_PILOT_TRANS_INFO_CAP_EN: + return "RM_MEAS_PILOT_TRANS_INFO_CAP_EN"; + case RM_NB_REP_TSF_OFFSET_CAP_EN: + return "RM_NB_REP_TSF_OFFSET_CAP_EN"; + case RM_RCPI_MEAS_CAP_EN: + return "RM_RCPI_MEAS_CAP_EN"; /* 29 */ + case RM_RSNI_MEAS_CAP_EN: + return "RM_RSNI_MEAS_CAP_EN"; + case RM_BSS_AVG_ACCESS_DELAY_CAP_EN: + return "RM_BSS_AVG_ACCESS_DELAY_CAP_EN"; + + case RM_AVALB_ADMIS_CAPACITY_CAP_EN: + return "RM_AVALB_ADMIS_CAPACITY_CAP_EN"; + case RM_ANT_CAP_EN: + return "RM_ANT_CAP_EN"; + case RM_RSVD: + case RM_MAX: + default: + break; + } + return "unknown"; +} + +int rm_en_cap_chk_and_set(struct rm_obj *prm, enum rm_cap_en en) +{ + int idx; + u8 cap; + + + if (en >= RM_MAX) + return _FALSE; + + idx = en / 8; + cap = prm->psta->padapter->rmpriv.rm_en_cap_def[idx]; + + if (!(cap & BIT(en - (idx*8)))) { + RTW_INFO("RM: %s incapable\n",rm_en_cap_name(en)); + rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP); + return _FALSE; + } + return _SUCCESS; +} + +static u8 rm_get_oper_class_via_ch(u8 ch) +{ + int i,j,sz; + + + sz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS); + + for (i = 0; i < sz; i++) { + for (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) { + if ( ch == RTW_OP_CLASS_US[i].Channel[j]) { + RTW_INFO("RM: ch %u in oper_calss %u\n", + ch, RTW_OP_CLASS_US[i].global_op_class); + return RTW_OP_CLASS_US[i].global_op_class; + break; + } + } + } + return 0; +} + +static u8 rm_get_ch_set( + struct rtw_ieee80211_channel *pch_set, u8 op_class, u8 ch_num) +{ + int i,j,sz; + u8 ch_amount = 0; + + + sz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS); + + if (ch_num != 0) { + pch_set[0].hw_value = ch_num; + ch_amount = 1; + RTW_INFO("RM: meas_ch->hw_value = %u\n", pch_set->hw_value); + goto done; + } + + for (i = 0; i < sz; i++) { + + if (RTW_OP_CLASS_US[i].global_op_class == op_class) { + + for (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) { + pch_set[j].hw_value = + RTW_OP_CLASS_US[i].Channel[j]; + RTW_INFO("RM: meas_ch[%d].hw_value = %u\n", + j, pch_set[j].hw_value); + } + ch_amount = RTW_OP_CLASS_US[i].Len; + break; + } + } +done: + return ch_amount; +} + +static int is_wildcard_bssid(u8 *bssid) +{ + int i; + u8 val8 = 0xff; + + + for (i=0;i<6;i++) + val8 &= bssid[i]; + + if (val8 == 0xff) + return _SUCCESS; + return _FALSE; +} + +/* for caller outside rm */ +u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct rm_obj *prm; + + + prm = rm_alloc_rmobj(padapter); + + if (prm == NULL) { + RTW_ERR("RM: unable to alloc rm obj for requeset\n"); + return _FALSE; + } + + prm->psta = psta; + prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS; + prm->q.diag_token = pmlmeinfo->dialogToken++; + prm->q.m_token = 1; + + prm->rmid = psta->cmn.aid << 16 + | prm->q.diag_token << 8 + | RM_MASTER; + + prm->q.action_code = RM_ACT_NB_REP_REQ; + + #if 0 + if (pmac) { /* find sta_info according to bssid */ + pmac += 4; /* skip mac= */ + if (hwaddr_parse(pmac, bssid) == NULL) { + sprintf(pstr(s), "Err: \nincorrect mac format\n"); + return _FAIL; + } + psta = rm_get_sta(padapter, 0xff, bssid); + } + #endif + + /* enquee rmobj */ + rm_enqueue_rmobj(padapter, prm, _FALSE); + + RTW_INFO("RM: rmid=%x add req to " MAC_FMT "\n", + prm->rmid, MAC_ARG(psta->cmn.mac_addr)); + + return _SUCCESS; +} + + +static u8 *build_wlan_hdr(_adapter *padapter, struct xmit_frame *pmgntframe, + struct sta_info *psta, u16 frame_type) +{ + u8 *pframe; + u16 *fctrl; + struct pkt_attrib *pattr; + struct rtw_ieee80211_hdr *pwlanhdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + + + /* update attribute */ + pattr = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattr); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, + get_my_bssid(&(pmlmeinfo->network)),ETH_ALEN); + + RTW_INFO("RM: dst = " MAC_FMT "\n", MAC_ARG(pwlanhdr->addr1)); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFragNum(pframe, 0); + + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattr->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + return pframe; +} + +void rm_set_rep_mode(struct rm_obj *prm, u8 mode) +{ + + RTW_INFO("RM: rmid=%x set %s\n", + prm->rmid, + mode|MEAS_REP_MOD_INCAP?"INCAP": + mode|MEAS_REP_MOD_REFUSE?"REFUSE": + mode|MEAS_REP_MOD_LATE?"LATE":""); + + prm->p.m_mode |= mode; +} + +int issue_null_reply(struct rm_obj *prm) +{ + int len=0, my_len; + u8 *pframe, m_mode; + _adapter *padapter = prm->psta->padapter; + struct pkt_attrib *pattr; + struct xmit_frame *pmgntframe; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + + + m_mode = prm->p.m_mode; + if (m_mode || prm->p.rpt == 0) { + RTW_INFO("RM: rmid=%x reply (%s repeat=%d)\n", + prm->rmid, + m_mode&MEAS_REP_MOD_INCAP?"INCAP": + m_mode&MEAS_REP_MOD_REFUSE?"REFUSE": + m_mode&MEAS_REP_MOD_LATE?"LATE":"no content", + prm->p.rpt); + } + + switch (prm->p.action_code) { + case RM_ACT_RADIO_MEAS_REQ: + len = 8; + break; + case RM_ACT_NB_REP_REQ: + len = 3; + break; + case RM_ACT_LINK_MEAS_REQ: + len = 3; + break; + default: + break; + } + + if (len==0) + return _FALSE; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__); + return _FALSE; + } + pattr = &pmgntframe->attrib; + pframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION); + pframe = rtw_set_fixed_ie(pframe, 3, &prm->p.category, &pattr->pktlen); + + my_len = 0; + if (len>5) { + prm->p.len = len - 3 - 2; + pframe = rtw_set_fixed_ie(pframe, len - 3, + &prm->p.e_id, &my_len); + } + + pattr->pktlen += my_len; + pattr->last_txcmdsz = pattr->pktlen; + dump_mgntframe(padapter, pmgntframe); + + return _SUCCESS; +} + +int ready_for_scan(struct rm_obj *prm) +{ + _adapter *padapter = prm->psta->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + + if (rtw_is_scan_deny(padapter)) + return _FALSE; + + if (!rtw_is_adapter_up(padapter)) + return _FALSE; + + if (rtw_mi_busy_traffic_check(padapter, _FALSE)) + return _FALSE; + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) + && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { + RTW_INFO(FUNC_ADPT_FMT" WIFI_AP_STATE && WIFI_UNDER_WPS\n", + FUNC_ADPT_ARG(padapter)); + return _FALSE; + } + if (check_fwstate(pmlmepriv, + (_FW_UNDER_SURVEY | _FW_UNDER_LINKING)) == _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" _FW_UNDER_SURVEY|_FW_UNDER_LINKING\n", + FUNC_ADPT_ARG(padapter)); + return _FALSE; + } + +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_mi_buddy_check_fwstate(padapter, + (_FW_UNDER_SURVEY | _FW_UNDER_LINKING | WIFI_UNDER_WPS))) { + RTW_INFO(FUNC_ADPT_FMT", but buddy_intf is under scanning or linking or wps_phase\n", + FUNC_ADPT_ARG(padapter)); + return _FALSE; + } +#endif + return _SUCCESS; +} + +int rm_sitesurvey(struct rm_obj *prm) +{ + int meas_ch_num=0; + u8 ch_num=0, op_class=0, val8; + struct rtw_ieee80211_channel *pch_set; + struct sitesurvey_parm parm; + + + RTW_INFO("RM: rmid=%x %s\n",prm->rmid, __func__); + + pch_set = &prm->q.ch_set[0]; + + _rtw_memset(pch_set, 0, + sizeof(struct rtw_ieee80211_channel) * MAX_OP_CHANNEL_SET_NUM); + + if (prm->q.ch_num == 0) { + /* ch_num=0 : scan all ch in operating class */ + op_class = prm->q.op_class; + + } else if (prm->q.ch_num == 255) { + /* 802.11 p.499 */ + /* ch_num=255 : scan all ch in current operating class */ + op_class = rm_get_oper_class_via_ch( + (u8)prm->psta->padapter->mlmeextpriv.cur_channel); + } else + ch_num = prm->q.ch_num; + + /* get means channel */ + meas_ch_num = rm_get_ch_set(pch_set, op_class, ch_num); + prm->q.ch_set_ch_amount = meas_ch_num; + + _rtw_memset(&parm, 0, sizeof(struct sitesurvey_parm)); + _rtw_memcpy(parm.ch, pch_set, + sizeof(struct rtw_ieee80211_channel) * MAX_OP_CHANNEL_SET_NUM); + + _rtw_memcpy(&parm.ssid[0], &prm->q.opt.bcn.ssid, IW_ESSID_MAX_SIZE); + + parm.ssid_num = 1; + parm.scan_mode = prm->q.m_mode; + parm.ch_num = meas_ch_num; + parm.igi = 0; + parm.token = prm->rmid; + parm.duration = prm->q.meas_dur; + /* parm.bw = BW_20M; */ + + rtw_sitesurvey_cmd(prm->psta->padapter, &parm); + + return _SUCCESS; +} + +static u8 translate_percentage_to_rcpi(u32 SignalStrengthIndex) +{ + s32 SignalPower; /* in dBm. */ + u8 rcpi; + + /* Translate to dBm (x=y-100) */ + SignalPower = SignalStrengthIndex - 100; + + /* RCPI = Int{(Power in dBm + 110)*2} for 0dBm > Power > -110dBm + * 0 : power <= -110.0 dBm + * 1 : power = -109.5 dBm + * 2 : power = -109.0 dBm + */ + + rcpi = (SignalPower + 110)*2; + return rcpi; +} + +static int rm_parse_ch_load_s_elem(struct rm_obj *prm, u8 *pbody, int req_len) +{ + u8 *popt_id; + int i, p=0; /* position */ + int len = req_len; + + + prm->q.opt_s_elem_len = len; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: opt_s_elem_len=%d\n", len); +#endif + while (len) { + + switch (pbody[p]) { + case ch_load_rep_info: + /* check RM_EN */ + rm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN); + + _rtw_memcpy(&(prm->q.opt.clm.rep_cond), + &pbody[p+2], sizeof(prm->q.opt.clm.rep_cond)); + + RTW_INFO("RM: ch_load_rep_info=%u:%u\n", + prm->q.opt.clm.rep_cond.cond, + prm->q.opt.clm.rep_cond.threshold); + break; + default: + break; + + } + len = len - (int)pbody[p+1] - 2; + p = p + (int)pbody[p+1] + 2; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: opt_s_elem_len=%d\n",len); +#endif + } + return _SUCCESS; +} + +static int rm_parse_noise_histo_s_elem(struct rm_obj *prm, + u8 *pbody, int req_len) +{ + u8 *popt_id; + int i, p=0; /* position */ + int len = req_len; + + + prm->q.opt_s_elem_len = len; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: opt_s_elem_len=%d\n", len); +#endif + + while (len) { + + switch (pbody[p]) { + case noise_histo_rep_info: + /* check RM_EN */ + rm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN); + + _rtw_memcpy(&(prm->q.opt.nhm.rep_cond), + &pbody[p+2], sizeof(prm->q.opt.nhm.rep_cond)); + + RTW_INFO("RM: noise_histo_rep_info=%u:%u\n", + prm->q.opt.nhm.rep_cond.cond, + prm->q.opt.nhm.rep_cond.threshold); + break; + default: + break; + + } + len = len - (int)pbody[p+1] - 2; + p = p + (int)pbody[p+1] + 2; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: opt_s_elem_len=%d\n",len); +#endif + } + return _SUCCESS; +} + +static int rm_parse_bcn_req_s_elem(struct rm_obj *prm, u8 *pbody, int req_len) +{ + u8 *popt_id; + int i, p=0; /* position */ + int len = req_len; + + + /* opt length,2:pbody[0]+ pbody[1] */ + /* first opt id : pbody[18] */ + + prm->q.opt_s_elem_len = len; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: opt_s_elem_len=%d\n", len); +#endif + + popt_id = prm->q.opt.bcn.opt_id; + while (len && prm->q.opt.bcn.opt_id_num < BCN_REQ_OPT_MAX_NUM) { + + switch (pbody[p]) { + case bcn_req_ssid: + RTW_INFO("bcn_req_ssid\n"); + +#if (DBG_BCN_REQ_WILDCARD) + RTW_INFO("DBG set ssid to WILDCARD\n"); +#else +#if (DBG_BCN_REQ_SSID) + RTW_INFO("DBG set ssid to %s\n",DBG_BCN_REQ_SSID_NAME); + i = strlen(DBG_BCN_REQ_SSID_NAME); + prm->q.opt.bcn.ssid.SsidLength = i; + _rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid), + DBG_BCN_REQ_SSID_NAME, i); + +#else /* original */ + prm->q.opt.bcn.ssid.SsidLength = pbody[p+1]; + _rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid), + &pbody[p+2], pbody[p+1]); +#endif +#endif + + RTW_INFO("RM: bcn_req_ssid=%s\n", + prm->q.opt.bcn.ssid.Ssid); + + popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p]; + break; + + case bcn_req_rep_info: + /* check RM_EN */ + rm_en_cap_chk_and_set(prm, RM_BCN_MEAS_REP_COND_CAP_EN); + + _rtw_memcpy(&(prm->q.opt.bcn.rep_cond), + &pbody[p+2], sizeof(prm->q.opt.bcn.rep_cond)); + + RTW_INFO("bcn_req_rep_info=%u:%u\n", + prm->q.opt.bcn.rep_cond.cond, + prm->q.opt.bcn.rep_cond.threshold); + + /*popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];*/ + break; + + case bcn_req_rep_detail: +#if DBG_BCN_REQ_DETAIL + prm->q.opt.bcn.rep_detail = 2; /* all IE in beacon */ +#else + prm->q.opt.bcn.rep_detail = pbody[p+2]; +#endif + popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p]; + +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: report_detail=%d\n", + prm->q.opt.bcn.rep_detail); +#endif + break; + + case bcn_req_req: + RTW_INFO("RM: bcn_req_req\n"); + + prm->q.opt.bcn.req_start = rtw_malloc(pbody[p+1]); + + if (prm->q.opt.bcn.req_start == NULL) { + RTW_ERR("RM: req_start malloc fail!!\n"); + break; + } + + for (i = 0; i < pbody[p+1]; i++) + *((prm->q.opt.bcn.req_start)+i) = + pbody[p+2+i]; + + prm->q.opt.bcn.req_len = pbody[p+1]; + popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p]; + break; + + case bcn_req_ac_ch_rep: +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: bcn_req_ac_ch_rep\n"); +#endif + popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p]; + break; + + default: + break; + + } + len = len - (int)pbody[p+1] - 2; + p = p + (int)pbody[p+1] + 2; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: opt_s_elem_len=%d\n",len); +#endif + } + + return _SUCCESS; +} + +static int rm_parse_meas_req(struct rm_obj *prm, u8 *pbody) +{ + int p; /* position */ + int req_len; + + + req_len = (int)pbody[1]; + p = 5; + + prm->q.op_class = pbody[p++]; + prm->q.ch_num = pbody[p++]; + prm->q.rand_intvl = le16_to_cpu(*(u16*)(&pbody[p])); + p+=2; + prm->q.meas_dur = le16_to_cpu(*(u16*)(&pbody[p])); + p+=2; + + if (prm->q.m_type == bcn_req) { + /* + * 0: passive + * 1: active + * 2: bcn_table + */ + prm->q.m_mode = pbody[p++]; + + /* BSSID */ + _rtw_memcpy(&(prm->q.bssid), &pbody[p], 6); + p+=6; + + /* + * default, used when Reporting detail subelement + * is not included in Beacon Request + */ + prm->q.opt.bcn.rep_detail = 2; + } + + if (req_len-(p-2) <= 0) /* without sub-element */ + return _SUCCESS; + + switch (prm->q.m_type) { + case bcn_req: + rm_parse_bcn_req_s_elem(prm, &pbody[p], req_len-(p-2)); + break; + case ch_load_req: + rm_parse_ch_load_s_elem(prm, &pbody[p], req_len-(p-2)); + break; + case noise_histo_req: + rm_parse_noise_histo_s_elem(prm, &pbody[p], req_len-(p-2)); + break; + default: + break; + } + + return _SUCCESS; +} + +/* receive measurement request */ +int rm_recv_radio_mens_req(_adapter *padapter, + union recv_frame *precv_frame, struct sta_info *psta) +{ + struct rm_obj *prm; + struct rm_priv *prmpriv = &padapter->rmpriv; + u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data + + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 *pmeas_body = &pdiag_body[5]; + u8 rmid, update = 0; + + +#if 0 + /* search existing rm_obj */ + rmid = psta->cmn.aid << 16 + | pdiag_body[2] << 8 + | RM_SLAVE; + + prm = rm_get_rmobj(padapter, rmid); + if (prm) { + RTW_INFO("RM: Found an exist meas rmid=%u\n", rmid); + update = 1; + } else +#endif + prm = rm_alloc_rmobj(padapter); + + if (prm == NULL) { + RTW_ERR("RM: unable to alloc rm obj for requeset\n"); + return _FALSE; + } + + prm->psta = psta; + prm->q.diag_token = pdiag_body[2]; + prm->q.rpt = le16_to_cpu(*(u16*)(&pdiag_body[3])); + + /* Figure 8-104 Measurement Requested format */ + prm->q.e_id = pmeas_body[0]; + prm->q.m_token = pmeas_body[2]; + prm->q.m_mode = pmeas_body[3]; + prm->q.m_type = pmeas_body[4]; + + prm->rmid = psta->cmn.aid << 16 + | prm->q.diag_token << 8 + | RM_SLAVE; + + RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid, + MAC_ARG(prm->psta->cmn.mac_addr)); + +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: element_id = %d\n", prm->q.e_id); + RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]); + RTW_INFO("RM: meas_token = %d\n", prm->q.m_token); + RTW_INFO("RM: meas_mode = %d\n", prm->q.m_mode); + RTW_INFO("RM: meas_type = %d\n", prm->q.m_type); +#endif + + if (prm->q.e_id != _MEAS_REQ_IE_) /* 38 */ + return _FALSE; + + switch (prm->q.m_type) { + case bcn_req: + RTW_INFO("RM: recv beacon_request\n"); + switch (prm->q.m_mode) { + case bcn_req_passive: + rm_en_cap_chk_and_set(prm, RM_BCN_PASSIVE_MEAS_CAP_EN); + break; + case bcn_req_active: + rm_en_cap_chk_and_set(prm, RM_BCN_ACTIVE_MEAS_CAP_EN); + break; + case bcn_req_bcn_table: + rm_en_cap_chk_and_set(prm, RM_BCN_TABLE_MEAS_CAP_EN); + break; + default: + rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP); + break; + } + break; + case ch_load_req: + RTW_INFO("RM: recv ch_load_request\n"); + rm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN); + break; + case noise_histo_req: + RTW_INFO("RM: recv noise_histogram_request\n"); + rm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN); + break; + default: + RTW_INFO("RM: recv unknown request type 0x%02x\n", + prm->q.m_type); + rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP); + goto done; + } + rm_parse_meas_req(prm, pmeas_body); +done: + if (!update) + rm_enqueue_rmobj(padapter, prm, _FALSE); + + return _SUCCESS; +} + +/* receive measurement report */ +int rm_recv_radio_mens_rep(_adapter *padapter, + union recv_frame *precv_frame, struct sta_info *psta) +{ + int ret = _FALSE; + struct rm_obj *prm; + u32 rmid; + u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data + + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 *pmeas_body = &pdiag_body[3]; + + + rmid = psta->cmn.aid << 16 + | pdiag_body[2] << 8 + | RM_MASTER; + + prm = rm_get_rmobj(padapter, rmid); + if (prm == NULL) + return _FALSE; + + prm->p.action_code = pdiag_body[1]; + prm->p.diag_token = pdiag_body[2]; + + /* Figure 8-140 Measuremnt Report format */ + prm->p.e_id = pmeas_body[0]; + prm->p.m_token = pmeas_body[2]; + prm->p.m_mode = pmeas_body[3]; + prm->p.m_type = pmeas_body[4]; + + RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid, + MAC_ARG(prm->psta->cmn.mac_addr)); + +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: element_id = %d\n", prm->p.e_id); + RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]); + RTW_INFO("RM: meas_token = %d\n", prm->p.m_token); + RTW_INFO("RM: meas_mode = %d\n", prm->p.m_mode); + RTW_INFO("RM: meas_type = %d\n", prm->p.m_type); +#endif + if (prm->p.e_id != _MEAS_RSP_IE_) /* 39 */ + return _FALSE; + + RTW_INFO("RM: recv %s\n", rm_type_rep_name(prm->p.m_type)); + rm_post_event(padapter, prm->rmid, RM_EV_recv_rep); + + return ret; +} + +int rm_radio_mens_nb_rep(_adapter *padapter, + union recv_frame *precv_frame, struct sta_info *psta) +{ + u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data + + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 *pmeas_body = &pdiag_body[3]; + u32 len = precv_frame->u.hdr.len; + u32 rmid; + struct rm_obj *prm; + + + rmid = psta->cmn.aid << 16 + | pdiag_body[2] << 8 + | RM_MASTER; + + prm = rm_get_rmobj(padapter, rmid); + if (prm == NULL) + return _FALSE; + + prm->p.action_code = pdiag_body[1]; + prm->p.diag_token = pdiag_body[2]; + prm->p.e_id = pmeas_body[0]; + + RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid, + MAC_ARG(prm->psta->cmn.mac_addr)); + +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: element_id = %d\n", prm->p.e_id); + RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]); +#endif + rm_post_event(padapter, prm->rmid, RM_EV_recv_rep); + +#ifdef CONFIG_LAYER2_ROAMING + if (rtw_wnm_btm_candidates_survey(padapter + ,(pdiag_body + 3) + ,(len - sizeof(struct rtw_ieee80211_hdr_3addr)) + ,_FALSE) == _FAIL) + return _FALSE; +#endif + rtw_cfg80211_rx_rrm_action(padapter, precv_frame); + + return _TRUE; +} + +unsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame) +{ + u32 ret = _FAIL; + u8 *pframe = NULL; + u8 *pframe_body = NULL; + u8 action_code = 0; + u8 diag_token = 0; + struct rtw_ieee80211_hdr_3addr *whdr; + struct sta_info *psta; + + + pframe = precv_frame->u.hdr.rx_data; + + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), + GetAddr1Ptr(pframe), ETH_ALEN)) + goto exit; + + whdr = (struct rtw_ieee80211_hdr_3addr *)pframe; + RTW_INFO("RM: %s bssid = " MAC_FMT "\n", + __func__, MAC_ARG(whdr->addr2)); + + psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2); + + if (!psta) { + RTW_ERR("RM: psta not found\n"); + goto exit; + } + + pframe_body = (unsigned char *)(pframe + + sizeof(struct rtw_ieee80211_hdr_3addr)); + + /* Figure 8-438 radio measurement request frame Action field format */ + /* Category = pframe_body[0] = 5 (Radio Measurement) */ + action_code = pframe_body[1]; + diag_token = pframe_body[2]; + +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: %s radio_action=%x, diag_token=%x\n", __func__, + action_code, diag_token); +#endif + + switch (action_code) { + + case RM_ACT_RADIO_MEAS_REQ: + RTW_INFO("RM: RM_ACT_RADIO_MEAS_REQ\n"); + ret = rm_recv_radio_mens_req(padapter, precv_frame, psta); + break; + + case RM_ACT_RADIO_MEAS_REP: + RTW_INFO("RM: RM_ACT_RADIO_MEAS_REP\n"); + ret = rm_recv_radio_mens_rep(padapter, precv_frame, psta); + break; + + case RM_ACT_LINK_MEAS_REQ: + RTW_INFO("RM: RM_ACT_LINK_MEAS_REQ\n"); + break; + + case RM_ACT_LINK_MEAS_REP: + RTW_INFO("RM: RM_ACT_LINK_MEAS_REP\n"); + break; + + case RM_ACT_NB_REP_REQ: + RTW_INFO("RM: RM_ACT_NB_REP_REQ\n"); + break; + + case RM_ACT_NB_REP_RESP: + RTW_INFO("RM: RM_ACT_NB_REP_RESP\n"); + ret = rm_radio_mens_nb_rep(padapter, precv_frame, psta); + break; + + default: + /* TODO reply incabable */ + RTW_ERR("RM: unknown specturm management action %2x\n", + action_code); + break; + } +exit: + return ret; +} + +static u8 *rm_gen_bcn_detail_elem(_adapter *padapter, u8 *pframe, + struct rm_obj *prm, struct wlan_network *pnetwork, + unsigned int *fr_len) +{ + WLAN_BSSID_EX *pbss = &pnetwork->network; + unsigned int my_len; + int j, k, len; + u8 *plen; + u8 *ptr; + u8 val8, eid; + + + my_len = 0; + /* Reporting Detail values + * 0: No fixed length fields or elements + * 1: All fixed length fields and any requested elements + * in the Request info element if present + * 2: All fixed length fields and elements + * 3-255: Reserved + */ + + /* report_detail = 0 */ + if (prm->q.opt.bcn.rep_detail == 0 + || prm->q.opt.bcn.rep_detail > 2) { + return pframe; + } + + /* ID */ + val8 = 1; /* 1:reported frame body */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + plen = pframe; + val8 = 0; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* report_detail = 2 */ + if (prm->q.opt.bcn.rep_detail == 2) { + pframe = rtw_set_fixed_ie(pframe, pbss->IELength - 4, + pbss->IEs, &my_len); /* -4 remove FCS */ + goto done; + } + + /* report_detail = 1 */ + /* all fixed lenght fields */ + pframe = rtw_set_fixed_ie(pframe, + _FIXED_IE_LENGTH_, pbss->IEs, &my_len); + + for (j = 0; j < prm->q.opt.bcn.opt_id_num; j++) { + switch (prm->q.opt.bcn.opt_id[j]) { + case bcn_req_ssid: + /* SSID */ +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: bcn_req_ssid\n"); +#endif + pframe = rtw_set_ie(pframe, _SSID_IE_, + pbss->Ssid.SsidLength, + pbss->Ssid.Ssid, &my_len); + break; + case bcn_req_req: + if (prm->q.opt.bcn.req_start == NULL) + break; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: bcn_req_req"); +#endif + for (k=0; kq.opt.bcn.req_len; k++) { + eid = prm->q.opt.bcn.req_start[k]; + + val8 = pbss->IELength - _FIXED_IE_LENGTH_; + ptr = rtw_get_ie(pbss->IEs + _FIXED_IE_LENGTH_, + eid, &len, val8); + + if (!ptr) + continue; +#if (RM_MORE_DBG_MSG) + switch (eid) { + case EID_QBSSLoad: + RTW_INFO("RM: EID_QBSSLoad\n"); + break; + case EID_HTCapability: + RTW_INFO("RM: EID_HTCapability\n"); + break; + case _MDIE_: + RTW_INFO("RM: EID_MobilityDomain\n"); + break; + default: + RTW_INFO("RM: EID %d todo\n",eid); + break; + } +#endif + pframe = rtw_set_ie(pframe, eid, + len,ptr+2, &my_len); + } /* for() */ + break; + case bcn_req_ac_ch_rep: + default: + RTW_INFO("RM: OPT %d TODO\n",prm->q.opt.bcn.opt_id[j]); + break; + } + } +done: + /* + * update my length + * content length does NOT include ID and LEN + */ + val8 = my_len - 2; + rtw_set_fixed_ie(plen, 1, &val8, &j); + + /* update length to caller */ + *fr_len += my_len; + + return pframe; +} + +static u8 rm_get_rcpi(struct rm_obj *prm, struct wlan_network *pnetwork) +{ + return translate_percentage_to_rcpi( + pnetwork->network.PhyInfo.SignalStrength); +} + +static u8 rm_get_rsni(struct rm_obj *prm, struct wlan_network *pnetwork) +{ + int i; + u8 val8, snr; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(prm->psta->padapter); + + + if (pnetwork->network.PhyInfo.is_cck_rate) { + /* current HW doesn't have CCK RSNI */ + /* 255 indicates RSNI is unavailable */ + val8 = 255; + } else { + snr = 0; + for (i = 0; i < pHalData->NumTotalRFPath; i++) { + snr += pnetwork->network.PhyInfo.rx_snr[i]; + } + snr = snr / pHalData->NumTotalRFPath; + val8 = (u8)(snr + 10)*2; + } + return val8; +} + +u8 rm_bcn_req_cond_mach(struct rm_obj *prm, struct wlan_network *pnetwork) +{ + u8 val8; + + + switch(prm->q.opt.bcn.rep_cond.cond) { + case bcn_rep_cond_immediately: + return _SUCCESS; + case bcn_req_cond_rcpi_greater: + val8 = rm_get_rcpi(prm, pnetwork); + if (val8 > prm->q.opt.bcn.rep_cond.threshold) + return _SUCCESS; + break; + case bcn_req_cond_rcpi_less: + val8 = rm_get_rcpi(prm, pnetwork); + if (val8 < prm->q.opt.bcn.rep_cond.threshold) + return _SUCCESS; + break; + case bcn_req_cond_rsni_greater: + val8 = rm_get_rsni(prm, pnetwork); + if (val8 != 255 && val8 > prm->q.opt.bcn.rep_cond.threshold) + return _SUCCESS; + break; + case bcn_req_cond_rsni_less: + val8 = rm_get_rsni(prm, pnetwork); + if (val8 != 255 && val8 < prm->q.opt.bcn.rep_cond.threshold) + return _SUCCESS; + break; + default: + RTW_ERR("RM: bcn_req cond %u not support\n", + prm->q.opt.bcn.rep_cond.cond); + break; + } + return _FALSE; +} + +static u8 *rm_bcn_rep_fill_scan_resule (struct rm_obj *prm, + u8 *pframe, struct wlan_network *pnetwork, unsigned int *fr_len) +{ + int snr, i; + u8 val8, *plen; + u16 val16; + u32 val32; + u64 val64; + PWLAN_BSSID_EX pbss; + unsigned int my_len; + _adapter *padapter = prm->psta->padapter; + + + my_len = 0; + /* meas ID */ + val8 = EID_MeasureReport; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* remember position form elelment length */ + plen = pframe; + + /* meas_rpt_len */ + /* default 3 = mode + token + type but no beacon content */ + val8 = 3; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* meas_token */ + val8 = prm->q.m_token; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* meas_rpt_mode F8-141 */ + val8 = prm->p.m_mode; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* meas_type T8-81 */ + val8 = bcn_rep; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + if (pnetwork == NULL) + goto done; + + pframe = rtw_set_fixed_ie(pframe, 1, &prm->q.op_class, &my_len); + + /* channel */ + pbss = &pnetwork->network; + val8 = pbss->Configuration.DSConfig; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* Actual Measurement StartTime */ + val64 = cpu_to_le64(prm->meas_start_time); + pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len); + + /* Measurement Duration */ + val16 = prm->meas_end_time - prm->meas_start_time; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len); + + /* TODO + * ReportedFrameInformation: + * 0 :beacon or probe rsp + * 1 :pilot frame + */ + val8 = 0; /* report frame info */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* RCPI */ + val8 = rm_get_rcpi(prm, pnetwork); + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* RSNI */ + val8 = rm_get_rsni(prm, pnetwork); + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* BSSID */ + pframe = rtw_set_fixed_ie(pframe, 6, (u8 *)&pbss->MacAddress, &my_len); + + /* + * AntennaID + * 0: unknown + * 255: multiple antenna (Diversity) + */ + val8 = 0; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* ParentTSF */ + val32 = prm->meas_start_time + pnetwork->network.PhyInfo.free_cnt; + pframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len); + + /* + * Generate Beacon detail + */ + pframe = rm_gen_bcn_detail_elem(padapter, pframe, + prm, pnetwork, &my_len); +done: + /* + * update my length + * content length does NOT include ID and LEN + */ + val8 = my_len - 2; + rtw_set_fixed_ie(plen, 1, &val8, &i); + + /* update length to caller */ + *fr_len += my_len; + + return pframe; +} + +static u8 *rm_gen_bcn_rep_ie (struct rm_obj *prm, + u8 *pframe, struct wlan_network *pnetwork, unsigned int *fr_len) +{ + int snr, i; + u8 val8, *plen; + u16 val16; + u32 val32; + u64 val64; + unsigned int my_len; + _adapter *padapter = prm->psta->padapter; + + + my_len = 0; + plen = pframe + 1; + pframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len); + + /* Actual Measurement StartTime */ + val64 = cpu_to_le64(prm->meas_start_time); + pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len); + + /* Measurement Duration */ + val16 = prm->meas_end_time - prm->meas_start_time; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, 2, (u8*)&val16, &my_len); + + /* TODO + * ReportedFrameInformation: + * 0 :beacon or probe rsp + * 1 :pilot frame + */ + val8 = 0; /* report frame info */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* RCPI */ + val8 = rm_get_rcpi(prm, pnetwork); + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* RSNI */ + val8 = rm_get_rsni(prm, pnetwork); + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* BSSID */ + pframe = rtw_set_fixed_ie(pframe, 6, + (u8 *)&pnetwork->network.MacAddress, &my_len); + + /* + * AntennaID + * 0: unknown + * 255: multiple antenna (Diversity) + */ + val8 = 0; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* ParentTSF */ + val32 = prm->meas_start_time + pnetwork->network.PhyInfo.free_cnt; + pframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len); + + /* Generate Beacon detail */ + pframe = rm_gen_bcn_detail_elem(padapter, pframe, + prm, pnetwork, &my_len); +done: + /* + * update my length + * content length does NOT include ID and LEN + */ + val8 = my_len - 2; + rtw_set_fixed_ie(plen, 1, &val8, &i); + + /* update length to caller */ + *fr_len += my_len; + + return pframe; +} + +static int retrieve_scan_result(struct rm_obj *prm) +{ + _irqL irqL; + _list *plist, *phead; + _queue *queue; + _adapter *padapter = prm->psta->padapter; + struct rtw_ieee80211_channel *pch_set; + struct wlan_network *pnetwork = NULL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + int i, meas_ch_num=0; + PWLAN_BSSID_EX pbss; + unsigned int matched_network; + int len, my_len; + u8 buf_idx, *pbuf = NULL, *tmp_buf = NULL; + + + tmp_buf = rtw_malloc(MAX_XMIT_EXTBUF_SZ); + if (tmp_buf == NULL) + return 0; + + my_len = 0; + buf_idx = 0; + matched_network = 0; + queue = &(pmlmepriv->scanned_queue); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + /* get requested measurement channel set */ + pch_set = prm->q.ch_set; + meas_ch_num = prm->q.ch_set_ch_amount; + + /* search scan queue to find requested SSID */ + while (1) { + + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + pbss = &pnetwork->network; + + /* + * report network if requested channel set contains + * the channel matchs selected network + */ + if (rtw_chset_search_ch(adapter_to_chset(padapter), + pbss->Configuration.DSConfig) == 0) + goto next; + + if (rtw_mlme_band_check(padapter, pbss->Configuration.DSConfig) + == _FALSE) + goto next; + + if (rtw_validate_ssid(&(pbss->Ssid)) == _FALSE) + goto next; + + /* go through measurement requested channels */ + for (i = 0; i < meas_ch_num; i++) { + + /* match channel */ + if (pch_set[i].hw_value != pbss->Configuration.DSConfig) + continue; + + /* match bssid */ + if (is_wildcard_bssid(prm->q.bssid) == FALSE) + if (_rtw_memcmp(prm->q.bssid, + pbss->MacAddress, 6) == _FALSE) { + continue; + } + /* + * default wildcard SSID. wildcard SSID: + * A SSID value (null) used to represent all SSIDs + */ + + /* match ssid */ + if ((prm->q.opt.bcn.ssid.SsidLength > 0) && + _rtw_memcmp(prm->q.opt.bcn.ssid.Ssid, + pbss->Ssid.Ssid, + prm->q.opt.bcn.ssid.SsidLength) == _FALSE) + continue; + + /* match condition */ + if (rm_bcn_req_cond_mach(prm, pnetwork) == _FALSE) { + RTW_INFO("RM: condition mismatch ch %u ssid %s bssid "MAC_FMT"\n", + pch_set[i].hw_value, pbss->Ssid.Ssid, + MAC_ARG(pbss->MacAddress)); + RTW_INFO("RM: condition %u:%u\n", + prm->q.opt.bcn.rep_cond.cond, + prm->q.opt.bcn.rep_cond.threshold); + continue; + } + + /* Found a matched SSID */ + matched_network++; + + RTW_INFO("RM: ch %u Found %s bssid "MAC_FMT"\n", + pch_set[i].hw_value, pbss->Ssid.Ssid, + MAC_ARG(pbss->MacAddress)); + + len = 0; + _rtw_memset(tmp_buf, 0, MAX_XMIT_EXTBUF_SZ); + rm_gen_bcn_rep_ie(prm, tmp_buf, pnetwork, &len); +new_packet: + if (my_len == 0) { + pbuf = rtw_malloc(MAX_XMIT_EXTBUF_SZ); + if (pbuf == NULL) + goto fail; + prm->buf[buf_idx].pbuf = pbuf; + } + + if ((MAX_XMIT_EXTBUF_SZ - (my_len+len+24+4)) > 0) { + pbuf = rtw_set_fixed_ie(pbuf, + len, tmp_buf, &my_len); + prm->buf[buf_idx].len = my_len; + } else { + if (my_len == 0) /* not enough space */ + goto fail; + + my_len = 0; + buf_idx++; + goto new_packet; + } + } /* for() */ +next: + plist = get_next(plist); + } /* while() */ +fail: + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (tmp_buf) + rtw_mfree(tmp_buf, MAX_XMIT_EXTBUF_SZ); + + RTW_INFO("RM: Found %d matched %s\n", matched_network, + prm->q.opt.bcn.ssid.Ssid); + + if (prm->buf[buf_idx].pbuf) + return buf_idx+1; + + return 0; +} + +int issue_beacon_rep(struct rm_obj *prm) +{ + int i, my_len; + u8 *pframe; + _adapter *padapter = prm->psta->padapter; + struct pkt_attrib *pattr; + struct xmit_frame *pmgntframe; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + int pkt_num; + + + pkt_num = retrieve_scan_result(prm); + + if (pkt_num == 0) { + issue_null_reply(prm); + return _SUCCESS; + } + + for (i=0;iattrib; + pframe = build_wlan_hdr(padapter, + pmgntframe, prm->psta, WIFI_ACTION); + pframe = rtw_set_fixed_ie(pframe, + 3, &prm->p.category, &pattr->pktlen); + + my_len = 0; + pframe = rtw_set_fixed_ie(pframe, + prm->buf[i].len, prm->buf[i].pbuf, &my_len); + + pattr->pktlen += my_len; + pattr->last_txcmdsz = pattr->pktlen; + dump_mgntframe(padapter, pmgntframe); + } +fail: + for (i=0;ibuf[i].pbuf) { + rtw_mfree(prm->buf[i].pbuf, MAX_XMIT_EXTBUF_SZ); + prm->buf[i].pbuf = NULL; + prm->buf[i].len = 0; + } + } + return _SUCCESS; +} + +/* neighbor request */ +int issue_nb_req(struct rm_obj *prm) +{ + _adapter *padapter = prm->psta->padapter; + struct sta_info *psta = prm->psta; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_frame *pmgntframe = NULL; + struct pkt_attrib *pattr = NULL; + u8 val8; + u8 *pframe = NULL; + + + RTW_INFO("RM: %s\n", __func__); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__); + return _FALSE; + } + pattr = &pmgntframe->attrib; + pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION); + pframe = rtw_set_fixed_ie(pframe, + 3, &prm->q.category, &pattr->pktlen); + + if (prm->q.pssid) { + + u8 sub_ie[64] = {0}; + u8 *pie = &sub_ie[2]; + + RTW_INFO("RM: Send NB Req to "MAC_FMT" for(SSID) %s searching\n", + MAC_ARG(pmlmepriv->cur_network.network.MacAddress), + pmlmepriv->cur_network.network.Ssid.Ssid); + + val8 = strlen(prm->q.pssid); + sub_ie[0] = 0; /*SSID*/ + sub_ie[1] = val8; + + _rtw_memcpy(pie, prm->q.pssid, val8); + + pframe = rtw_set_fixed_ie(pframe, val8 + 2, + sub_ie, &pattr->pktlen); + } else { + + if (!pmlmepriv->cur_network.network.Ssid.SsidLength) + RTW_INFO("RM: Send NB Req to "MAC_FMT"\n", + MAC_ARG(pmlmepriv->cur_network.network.MacAddress)); + else { + u8 sub_ie[64] = {0}; + u8 *pie = &sub_ie[2]; + + RTW_INFO("RM: Send NB Req to "MAC_FMT" for(SSID) %s searching\n", + MAC_ARG(pmlmepriv->cur_network.network.MacAddress), + pmlmepriv->cur_network.network.Ssid.Ssid); + + sub_ie[0] = 0; /*SSID*/ + sub_ie[1] = pmlmepriv->cur_network.network.Ssid.SsidLength; + + _rtw_memcpy(pie, pmlmepriv->cur_network.network.Ssid.Ssid, + pmlmepriv->cur_network.network.Ssid.SsidLength); + + pframe = rtw_set_fixed_ie(pframe, + pmlmepriv->cur_network.network.Ssid.SsidLength + 2, + sub_ie, &pattr->pktlen); + } + } + + pattr->last_txcmdsz = pattr->pktlen; + dump_mgntframe(padapter, pmgntframe); + + return _SUCCESS; +} + +static u8 *rm_gen_bcn_req_s_elem(_adapter *padapter, + u8 *pframe, unsigned int *fr_len) +{ + u8 val8; + unsigned int my_len = 0; + u8 bssid[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + + val8 = bcn_req_active; /* measurement mode T8-64 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + pframe = rtw_set_fixed_ie(pframe, 6, bssid, &my_len); + + /* update length to caller */ + *fr_len += my_len; + + /* optional subelements */ + return pframe; +} + +static u8 *rm_gen_ch_load_req_s_elem(_adapter *padapter, + u8 *pframe, unsigned int *fr_len) +{ + u8 val8; + unsigned int my_len = 0; + + + val8 = 1; /* 1: channel load T8-60 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + val8 = 2; /* channel load length = 2 (extensible) */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + val8 = 0; /* channel load condition : 0 (issue when meas done) T8-61 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + val8 = 0; /* channel load reference value : 0 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* update length to caller */ + *fr_len += my_len; + + return pframe; +} + +static u8 *rm_gen_noise_histo_req_s_elem(_adapter *padapter, + u8 *pframe, unsigned int *fr_len) +{ + u8 val8; + unsigned int my_len = 0; + + + val8 = 1; /* 1: noise histogram T8-62 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + val8 = 2; /* noise histogram length = 2 (extensible) */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + val8 = 0; /* noise histogram condition : 0 (issue when meas done) T8-63 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + val8 = 0; /* noise histogram reference value : 0 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* update length to caller */ + *fr_len += my_len; + + return pframe; +} + +int issue_radio_meas_req(struct rm_obj *prm) +{ + u8 val8; + u8 *pframe; + u8 *plen; + u16 val16; + int my_len, i; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattr; + _adapter *padapter = prm->psta->padapter; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + + RTW_INFO("RM: %s - %s\n", __func__, rm_type_req_name(prm->q.m_type)); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__); + return _FALSE; + } + pattr = &pmgntframe->attrib; + pframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION); + pframe = rtw_set_fixed_ie(pframe, 3, &prm->q.category, &pattr->pktlen); + + /* repeat */ + val16 = cpu_to_le16(prm->q.rpt); + pframe = rtw_set_fixed_ie(pframe, 2, + (unsigned char *)&(val16), &pattr->pktlen); + + my_len = 0; + plen = pframe + 1; + pframe = rtw_set_fixed_ie(pframe, 7, &prm->q.e_id, &my_len); + + /* random interval */ + val16 = 100; /* 100 TU */ + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len); + + /* measurement duration */ + val16 = 100; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len); + + /* optional subelement */ + switch (prm->q.m_type) { + case bcn_req: + pframe = rm_gen_bcn_req_s_elem(padapter, pframe, &my_len); + break; + case ch_load_req: + pframe = rm_gen_ch_load_req_s_elem(padapter, pframe, &my_len); + break; + case noise_histo_req: + pframe = rm_gen_noise_histo_req_s_elem(padapter, + pframe, &my_len); + break; + case basic_req: + default: + break; + } + + /* length */ + val8 = (u8)my_len - 2; + rtw_set_fixed_ie(plen, 1, &val8, &i); + + pattr->pktlen += my_len; + + pattr->last_txcmdsz = pattr->pktlen; + dump_mgntframe(padapter, pmgntframe); + + return _SUCCESS; +} + +/* noise histogram */ +static u8 rm_get_anpi(struct rm_obj *prm, struct wlan_network *pnetwork) +{ + return translate_percentage_to_rcpi( + pnetwork->network.PhyInfo.SignalStrength); +} + +int rm_radio_meas_report_cond(struct rm_obj *prm) +{ + u8 val8; + int i; + + + switch (prm->q.m_type) { + case ch_load_req: + + val8 = prm->p.ch_load; + switch (prm->q.opt.clm.rep_cond.cond) { + case ch_load_cond_immediately: + return _SUCCESS; + case ch_load_cond_anpi_equal_greater: + if (val8 >= prm->q.opt.clm.rep_cond.threshold) + return _SUCCESS; + case ch_load_cond_anpi_equal_less: + if (val8 <= prm->q.opt.clm.rep_cond.threshold) + return _SUCCESS; + default: + break; + } + break; + case noise_histo_req: + val8 = prm->p.anpi; + switch (prm->q.opt.nhm.rep_cond.cond) { + case noise_histo_cond_immediately: + return _SUCCESS; + case noise_histo_cond_anpi_equal_greater: + if (val8 >= prm->q.opt.nhm.rep_cond.threshold) + return _SUCCESS; + break; + case noise_histo_cond_anpi_equal_less: + if (val8 <= prm->q.opt.nhm.rep_cond.threshold) + return _SUCCESS; + break; + default: + break; + } + break; + default: + break; + } + return _FAIL; +} + +int retrieve_radio_meas_result(struct rm_obj *prm) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(prm->psta->padapter); + int i, ch = -1; + u8 val8; + + + ch = rtw_chset_search_ch(adapter_to_chset(prm->psta->padapter), + prm->q.ch_num); + + if ((ch == -1) || (ch >= MAX_CHANNEL_NUM)) { + RTW_ERR("RM: get ch(CH:%d) fail\n", prm->q.ch_num); + ch = 0; + } + + switch (prm->q.m_type) { + case ch_load_req: +#ifdef CONFIG_RTW_ACS + val8 = hal_data->acs.clm_ratio[ch]; +#else + val8 = 0; +#endif + prm->p.ch_load = val8; + break; + case noise_histo_req: +#ifdef CONFIG_RTW_ACS + /* ANPI */ + prm->p.anpi = hal_data->acs.nhm_ratio[ch]; + + /* IPI 0~10 */ + for (i=0;i<11;i++) + prm->p.ipi[i] = hal_data->acs.nhm[ch][i]; + +#else + val8 = 0; + prm->p.anpi = val8; + for (i=0;i<11;i++) + prm->p.ipi[i] = val8; +#endif + break; + default: + break; + } + return _SUCCESS; +} + +int issue_radio_meas_rep(struct rm_obj *prm) +{ + u8 val8; + u8 *pframe; + u8 *plen; + u16 val16; + u64 val64; + unsigned int my_len; + _adapter *padapter = prm->psta->padapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattr; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct sta_info *psta = prm->psta; + int i; + + + RTW_INFO("RM: %s\n", __func__); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + RTW_ERR("RM: ERR %s alloc xmit_frame fail\n",__func__); + return _FALSE; + } + pattr = &pmgntframe->attrib; + pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION); + pframe = rtw_set_fixed_ie(pframe, 3, + &prm->p.category, &pattr->pktlen); + + my_len = 0; + plen = pframe + 1; + pframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len); + + /* Actual Meas start time - 8 bytes */ + val64 = cpu_to_le64(prm->meas_start_time); + pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len); + + /* measurement duration */ + val16 = prm->meas_end_time - prm->meas_start_time; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len); + + /* optional subelement */ + switch (prm->q.m_type) { + case ch_load_req: + val8 = prm->p.ch_load; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + break; + case noise_histo_req: + /* + * AntennaID + * 0: unknown + * 255: multiple antenna (Diversity) + */ + val8 = 0; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + /* ANPI */ + val8 = prm->p.anpi; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + /* IPI 0~10 */ + for (i=0;i<11;i++) { + val8 = prm->p.ipi[i]; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + } + break; + default: + break; + } +done: + /* length */ + val8 = (u8)my_len-2; + rtw_set_fixed_ie(plen, 1, &val8, &i); /* use variable i to ignore it */ + + pattr->pktlen += my_len; + pattr->last_txcmdsz = pattr->pktlen; + dump_mgntframe(padapter, pmgntframe); + + return _SUCCESS; +} + +void rtw_ap_parse_sta_rm_en_cap(_adapter *padapter, + struct sta_info *psta, struct rtw_ieee802_11_elems *elem) +{ + if (elem->rm_en_cap) { + RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n", + RM_CAP_ARG(elem->rm_en_cap)); + _rtw_memcpy(psta->rm_en_cap, + (elem->rm_en_cap), elem->rm_en_cap_len); + } +} + +void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + int i; + + _rtw_memcpy(&padapter->rmpriv.rm_en_cap_assoc, pIE->data, pIE->Length); + RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(pIE->data)); +} + +/* Debug command */ + +#if (RM_SUPPORT_IWPRIV_DBG) +static int hex2num(char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + return -1; +} + +int hex2byte(const char *hex) +{ + int a, b; + a = hex2num(*hex++); + if (a < 0) + return -1; + b = hex2num(*hex++); + if (b < 0) + return -1; + return (a << 4) | b; +} + +static char * hwaddr_parse(char *txt, u8 *addr) +{ + size_t i; + + for (i = 0; i < ETH_ALEN; i++) { + int a; + + a = hex2byte(txt); + if (a < 0) + return NULL; + txt += 2; + addr[i] = a; + if (i < ETH_ALEN - 1 && *txt++ != ':') + return NULL; + } + return txt; +} + +void rm_dbg_list_sta(_adapter *padapter, char *s) +{ + int i; + _irqL irqL; + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + _list *plist, *phead; + + + sprintf(pstr(s), "\n"); + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, + struct sta_info, hash_list); + + plist = get_next(plist); + + sprintf(pstr(s), "=========================================\n"); + sprintf(pstr(s), "mac=" MAC_FMT "\n", + MAC_ARG(psta->cmn.mac_addr)); + sprintf(pstr(s), "state=0x%x, aid=%d, macid=%d\n", + psta->state, psta->cmn.aid, psta->cmn.mac_id); + sprintf(pstr(s), "rm_cap="RM_CAP_FMT"\n", + RM_CAP_ARG(psta->rm_en_cap)); + } + + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + sprintf(pstr(s), "=========================================\n"); +} + +void rm_dbg_help(_adapter *padapter, char *s) +{ + int i; + + + sprintf(pstr(s), "\n"); + sprintf(pstr(s), "rrm list_sta\n"); + sprintf(pstr(s), "rrm list_meas\n"); + + sprintf(pstr(s), "rrm add_meas ,m=,rpt=\n"); + sprintf(pstr(s), "rrm run_meas \n"); + sprintf(pstr(s), "rrm del_meas\n"); + + sprintf(pstr(s), "rrm run_meas rmid=xxxx,ev=xx\n"); + sprintf(pstr(s), "rrm activate\n"); + + for (i=0;istapriv; + _list *plist, *phead; + + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, + struct sta_info, hash_list); + + plist = get_next(plist); + + if (psta->cmn.aid == aid) + goto done; + + if (pbssid && _rtw_memcmp(psta->cmn.mac_addr, + pbssid, 6)) + goto done; + } + + } + psta = NULL; +done: + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + return psta; +} + +static int rm_dbg_modify_meas(_adapter *padapter, char *s) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info; + struct rm_obj *prm; + struct sta_info *psta; + char *pmac, *ptr, *paid, *prpt, *pnbp, *pclm, *pnhm, *pbcn; + unsigned val; + u8 bssid[ETH_ALEN]; + + + /* example : + * rrm add_meas ,m=, + * rrm run_meas + */ + paid = strstr(s, "aid="); + pmac = strstr(s, "mac="); + pbcn = strstr(s, "m=bcn"); + pclm = strstr(s, "m=clm"); + pnhm = strstr(s, "m=nhm"); + pnbp = strstr(s, "m=nb"); + prpt = strstr(s, "rpt="); + + /* set all ',' to NULL (end of line) */ + ptr = s; + while (ptr) { + ptr = strchr(ptr, ','); + if (ptr) { + *(ptr) = 0x0; + ptr++; + } + } + prm = (struct rm_obj *)prmpriv->prm_sel; + prm->q.m_token = 1; + psta = prm->psta; + + if (paid) { /* find sta_info according to aid */ + paid += 4; /* skip aid= */ + sscanf(paid, "%u", &val); /* aid=x */ + psta = rm_get_sta(padapter, val, NULL); + + } else if (pmac) { /* find sta_info according to bssid */ + pmac += 4; /* skip mac= */ + if (hwaddr_parse(pmac, bssid) == NULL) { + sprintf(pstr(s), "Err: \nincorrect mac format\n"); + return _FAIL; + } + psta = rm_get_sta(padapter, 0xff, bssid); + } + + if (psta) { + prm->psta = psta; + +#if 0 + prm->q.diag_token = psta->rm_diag_token++; +#else + /* TODO dialog should base on sta_info */ + prm->q.diag_token = pmlmeinfo->dialogToken++; +#endif + prm->rmid = psta->cmn.aid << 16 + | prm->q.diag_token << 8 + | RM_MASTER; + } else + return _FAIL; + + prm->q.action_code = RM_ACT_RADIO_MEAS_REQ; + if (pbcn) { + prm->q.m_type = bcn_req; + } else if (pnhm) { + prm->q.m_type = noise_histo_req; + } else if (pclm) { + prm->q.m_type = ch_load_req; + } else if (pnbp) { + prm->q.action_code = RM_ACT_NB_REP_REQ; + } else + return _FAIL; + + if (prpt) { + prpt += 4; /* skip rpt= */ + sscanf(prpt, "%u", &val); + prm->q.rpt = (u8)val; + } + + return _SUCCESS; +} + +static void rm_dbg_activate_meas(_adapter *padapter, char *s) +{ + struct rm_priv *prmpriv = &(padapter->rmpriv); + struct rm_obj *prm; + + + if (prmpriv->prm_sel == NULL) { + sprintf(pstr(s), "\nErr: No inActivate measurement\n"); + return; + } + prm = (struct rm_obj *)prmpriv->prm_sel; + + /* verify attributes */ + if (prm->psta == NULL) { + sprintf(pstr(s), "\nErr: inActivate meas has no psta\n"); + return; + } + + /* measure current channel */ + prm->q.ch_num = padapter->mlmeextpriv.cur_channel; + prm->q.op_class = rm_get_oper_class_via_ch(prm->q.ch_num); + + /* enquee rmobj */ + rm_enqueue_rmobj(padapter, prm, _FALSE); + + sprintf(pstr(s), "\nActivate rmid=%x, state=%s, meas_type=%s\n", + prm->rmid, rm_state_name(prm->state), + rm_type_req_name(prm->q.m_type)); + + sprintf(pstr(s), "aid=%d, mac=" MAC_FMT "\n", + prm->psta->cmn.aid, MAC_ARG(prm->psta->cmn.mac_addr)); + + /* clearn inActivate prm info */ + prmpriv->prm_sel = NULL; +} + +static void rm_dbg_add_meas(_adapter *padapter, char *s) +{ + struct rm_priv *prmpriv = &(padapter->rmpriv); + struct rm_obj *prm; + char *pact; + + + /* example : + * rrm add_meas ,m= + * rrm run_meas + */ + prm = (struct rm_obj *)prmpriv->prm_sel; + if (prm == NULL) + prm = rm_alloc_rmobj(padapter); + + if (prm == NULL) { + sprintf(pstr(s), "\nErr: alloc meas fail\n"); + return; + } + + prmpriv->prm_sel = prm; + + pact = strstr(s, "act"); + if (rm_dbg_modify_meas(padapter, s) == _FAIL) { + + sprintf(pstr(s), "\nErr: add meas fail\n"); + rm_free_rmobj(prm); + prmpriv->prm_sel = NULL; + return; + } + prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS; + prm->q.e_id = _MEAS_REQ_IE_; /* 38 */ + + if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) + sprintf(pstr(s), "\nAdd rmid=%x, meas_type=%s ok\n", + prm->rmid, rm_type_req_name(prm->q.m_type)); + else if (prm->q.action_code == RM_ACT_NB_REP_REQ) + sprintf(pstr(s), "\nAdd rmid=%x, meas_type=bcn_req ok\n", + prm->rmid); + + if (prm->psta) + sprintf(pstr(s), "mac="MAC_FMT"\n", + MAC_ARG(prm->psta->cmn.mac_addr)); + + if (pact) + rm_dbg_activate_meas(padapter, pstr(s)); +} + +static void rm_dbg_del_meas(_adapter *padapter, char *s) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_obj *prm = (struct rm_obj *)prmpriv->prm_sel; + + + if (prm) { + sprintf(pstr(s), "\ndelete rmid=%x\n",prm->rmid); + + /* free inActivate meas - enqueue yet */ + prmpriv->prm_sel = NULL; + rtw_mfree(prmpriv->prm_sel, sizeof(struct rm_obj)); + } else + sprintf(pstr(s), "Err: no inActivate measurement\n"); +} + +static void rm_dbg_run_meas(_adapter *padapter, char *s) +{ + struct rm_obj *prm; + char *pevid, *prmid; + u32 rmid, evid; + + + prmid = strstr(s, "rmid="); /* hex */ + pevid = strstr(s, "evid="); /* dec */ + + if (prmid && pevid) { + prmid += 5; /* rmid= */ + sscanf(prmid, "%x", &rmid); + + pevid += 5; /* evid= */ + sscanf(pevid, "%u", &evid); + } else { + sprintf(pstr(s), "\nErr: incorrect attribute\n"); + return; + } + + prm = rm_get_rmobj(padapter, rmid); + + if (!prm) { + sprintf(pstr(s), "\nErr: measurement not found\n"); + return; + } + + if (evid >= RM_EV_max) { + sprintf(pstr(s), "\nErr: wrong event id\n"); + return; + } + + rm_post_event(padapter, prm->rmid, evid); + sprintf(pstr(s), "\npost %s to rmid=%x\n",rm_event_name(evid), rmid); +} + +static void rm_dbg_show_meas(struct rm_obj *prm, char *s) +{ + struct sta_info *psta; + + psta = prm->psta; + + if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) { + + sprintf(pstr(s), "\nrmid=%x, meas_type=%s\n", + prm->rmid, rm_type_req_name(prm->q.m_type)); + + } else if (prm->q.action_code == RM_ACT_NB_REP_REQ) { + + sprintf(pstr(s), "\nrmid=%x, action=neighbor_req\n", + prm->rmid); + } else + sprintf(pstr(s), "\nrmid=%x, action=unknown\n", + prm->rmid); + + if (psta) + sprintf(pstr(s), "aid=%d, mac="MAC_FMT"\n", + psta->cmn.aid, MAC_ARG(psta->cmn.mac_addr)); + + sprintf(pstr(s), "clock=%d, state=%s, rpt=%u/%u\n", + (int)ATOMIC_READ(&prm->pclock->counter), + rm_state_name(prm->state), prm->p.rpt, prm->q.rpt); +} + +static void rm_dbg_list_meas(_adapter *padapter, char *s) +{ + int meas_amount; + _irqL irqL; + struct rm_obj *prm; + struct sta_info *psta; + struct rm_priv *prmpriv = &padapter->rmpriv; + _queue *queue = &prmpriv->rm_queue; + _list *plist, *phead; + + + sprintf(pstr(s), "\n"); + _enter_critical(&queue->lock, &irqL); + phead = get_list_head(queue); + plist = get_next(phead); + meas_amount = 0; + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + prm = LIST_CONTAINOR(plist, struct rm_obj, list); + meas_amount++; + plist = get_next(plist); + psta = prm->psta; + sprintf(pstr(s), "=========================================\n"); + + rm_dbg_show_meas(prm, s); + } + _exit_critical(&queue->lock, &irqL); + + sprintf(pstr(s), "=========================================\n"); + + if (meas_amount==0) { + sprintf(pstr(s), "No Activate measurement\n"); + sprintf(pstr(s), "=========================================\n"); + } + + if (prmpriv->prm_sel == NULL) + sprintf(pstr(s), "\nNo inActivate measurement\n"); + else { + sprintf(pstr(s), "\ninActivate measurement\n"); + rm_dbg_show_meas((struct rm_obj *)prmpriv->prm_sel, s); + } +} +#endif /* RM_SUPPORT_IWPRIV_DBG */ + +void rm_dbg_cmd(_adapter *padapter, char *s) +{ + unsigned val; + char *paid; + struct sta_info *psta=NULL; + +#if (RM_SUPPORT_IWPRIV_DBG) + if (_rtw_memcmp(s, "help", 4)) { + rm_dbg_help(padapter, s); + + } else if (_rtw_memcmp(s, "list_sta", 8)) { + rm_dbg_list_sta(padapter, s); + + } else if (_rtw_memcmp(s, "list_meas", 9)) { + rm_dbg_list_meas(padapter, s); + + } else if (_rtw_memcmp(s, "add_meas", 8)) { + rm_dbg_add_meas(padapter, s); + + } else if (_rtw_memcmp(s, "del_meas", 8)) { + rm_dbg_del_meas(padapter, s); + + } else if (_rtw_memcmp(s, "activate", 8)) { + rm_dbg_activate_meas(padapter, s); + + } else if (_rtw_memcmp(s, "run_meas", 8)) { + rm_dbg_run_meas(padapter, s); + } else if (_rtw_memcmp(s, "nb", 2)) { + + paid = strstr(s, "aid="); + + if (paid) { /* find sta_info according to aid */ + paid += 4; /* skip aid= */ + sscanf(paid, "%u", &val); /* aid=x */ + psta = rm_get_sta(padapter, val, NULL); + + if (psta) + rm_add_nb_req(padapter, psta); + } + } +#else + sprintf(pstr(s), "\n"); + sprintf(pstr(s), "rrm debug command was disabled\n"); +#endif +} +#endif /* CONFIG_RTW_80211K */ diff --git a/core/rtw_rm_fsm.c b/core/rtw_rm_fsm.c new file mode 100644 index 0000000..1ed3c9d --- /dev/null +++ b/core/rtw_rm_fsm.c @@ -0,0 +1,998 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include +#include +#include "rtw_rm_fsm.h" + +#ifdef CONFIG_RTW_80211K + +struct fsm_state { + u8 *name; + int(*fsm_func)(struct rm_obj *prm, enum RM_EV_ID evid); +}; + +static void rm_state_initial(struct rm_obj *prm); +static void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state); +static void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid); +static struct rm_event *rm_dequeue_ev(_queue *queue); +static struct rm_obj *rm_dequeue_rm(_queue *queue); + +void rm_timer_callback(void *data) +{ + int i; + _adapter *padapter = (_adapter *)data; + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_clock *pclock; + + + /* deal with clock */ + for (i=0;iclock[i]; + if (pclock->prm == NULL + ||(ATOMIC_READ(&(pclock->counter)) == 0)) + continue; + + ATOMIC_DEC(&(pclock->counter)); + + if (ATOMIC_READ(&(pclock->counter)) == 0) + rm_post_event(pclock->prm->psta->padapter, + pclock->prm->rmid, prmpriv->clock[i].evid); + } + _set_timer(&prmpriv->rm_timer, CLOCK_UNIT); +} + +int rtw_init_rm(_adapter *padapter) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + + + RTW_INFO("RM: %s\n",__func__); + _rtw_init_queue(&(prmpriv->rm_queue)); + _rtw_init_queue(&(prmpriv->ev_queue)); + + /* bit 0-7 */ + prmpriv->rm_en_cap_def[0] = 0 + /*| BIT(RM_LINK_MEAS_CAP_EN)*/ + | BIT(RM_NB_REP_CAP_EN) + /*| BIT(RM_PARAL_MEAS_CAP_EN)*/ + | BIT(RM_REPEAT_MEAS_CAP_EN) + | BIT(RM_BCN_PASSIVE_MEAS_CAP_EN) + | BIT(RM_BCN_ACTIVE_MEAS_CAP_EN) + | BIT(RM_BCN_TABLE_MEAS_CAP_EN) + /*| BIT(RM_BCN_MEAS_REP_COND_CAP_EN)*/; + + /* bit 8-15 */ + prmpriv->rm_en_cap_def[1] = 0 + /*| BIT(RM_FRAME_MEAS_CAP_EN - 8)*/ +#ifdef CONFIG_RTW_ACS + | BIT(RM_CH_LOAD_CAP_EN - 8) + | BIT(RM_NOISE_HISTO_CAP_EN - 8) +#endif + /*| BIT(RM_STATIS_MEAS_CAP_EN - 8)*/ + /*| BIT(RM_LCI_MEAS_CAP_EN - 8)*/ + /*| BIT(RM_LCI_AMIMUTH_CAP_EN - 8)*/ + /*| BIT(RM_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/ + /*| BIT(RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/; + + /* bit 16-23 */ + prmpriv->rm_en_cap_def[2] = 0 + /*| BIT(RM_AP_CH_REP_CAP_EN - 16)*/ + /*| BIT(RM_RM_MIB_CAP_EN - 16)*/ + /*| BIT(RM_OP_CH_MAX_MEAS_DUR0 - 16)*/ + /*| BIT(RM_OP_CH_MAX_MEAS_DUR1 - 16)*/ + /*| BIT(RM_OP_CH_MAX_MEAS_DUR2 - 16)*/ + /*| BIT(RM_NONOP_CH_MAX_MEAS_DUR0 - 16)*/ + /*| BIT(RM_NONOP_CH_MAX_MEAS_DUR1 - 16)*/ + /*| BIT(RM_NONOP_CH_MAX_MEAS_DUR2 - 16)*/; + + /* bit 24-31 */ + prmpriv->rm_en_cap_def[3] = 0 + /*| BIT(RM_MEAS_PILOT_CAP0 - 24)*/ + /*| BIT(RM_MEAS_PILOT_CAP1 - 24)*/ + /*| BIT(RM_MEAS_PILOT_CAP2 - 24)*/ + /*| BIT(RM_MEAS_PILOT_TRANS_INFO_CAP_EN - 24)*/ + /*| BIT(RM_NB_REP_TSF_OFFSET_CAP_EN - 24)*/ + | BIT(RM_RCPI_MEAS_CAP_EN - 24) + | BIT(RM_RSNI_MEAS_CAP_EN - 24) + /*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 24)*/; + + /* bit 32-39 */ + prmpriv->rm_en_cap_def[4] = 0 + /*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 32)*/ + /*| BIT(RM_AVALB_ADMIS_CAPACITY_CAP_EN - 32)*/ + /*| BIT(RM_ANT_CAP_EN - 32)*/; + + prmpriv->enable = _TRUE; + + /* clock timer */ + rtw_init_timer(&prmpriv->rm_timer, + padapter, rm_timer_callback, padapter); + _set_timer(&prmpriv->rm_timer, CLOCK_UNIT); + + return _SUCCESS; +} + +int rtw_deinit_rm(_adapter *padapter) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_obj *prm; + struct rm_event *pev; + + + RTW_INFO("RM: %s\n",__func__); + prmpriv->enable = _FALSE; + _cancel_timer_ex(&prmpriv->rm_timer); + + /* free all events and measurements */ + while((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL) + rtw_mfree((void *)pev, sizeof(struct rm_event)); + + while((prm = rm_dequeue_rm(&prmpriv->rm_queue)) != NULL) + rm_state_run(prm, RM_EV_cancel); + + _rtw_deinit_queue(&(prmpriv->rm_queue)); + _rtw_deinit_queue(&(prmpriv->ev_queue)); + + return _SUCCESS; +} + +int rtw_free_rm_priv(_adapter *padapter) +{ + return rtw_deinit_rm(padapter); +} + +static int rm_enqueue_ev(_queue *queue, struct rm_event *obj, bool to_head) +{ + _irqL irqL; + + + if (obj == NULL) + return _FAIL; + + _enter_critical(&queue->lock, &irqL); + + if (to_head) + rtw_list_insert_head(&obj->list, &queue->queue); + else + rtw_list_insert_tail(&obj->list, &queue->queue); + + _exit_critical(&queue->lock, &irqL); + + return _SUCCESS; +} + +static void rm_set_clock(struct rm_obj *prm, u32 ms, enum RM_EV_ID evid) +{ + ATOMIC_SET(&(prm->pclock->counter), (ms/CLOCK_UNIT)); + prm->pclock->evid = evid; +} + +static struct rm_clock *rm_alloc_clock(_adapter *padapter, struct rm_obj *prm) +{ + int i; + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_clock *pclock = NULL; + + + for (i=0;iclock[i]; + + if (pclock->prm == NULL) { + pclock->prm = prm; + ATOMIC_SET(&(pclock->counter), 0); + pclock->evid = RM_EV_max; + break; + } + } + return pclock; +} + +static void rm_cancel_clock(struct rm_obj *prm) +{ + ATOMIC_SET(&(prm->pclock->counter), 0); + prm->pclock->evid = RM_EV_max; +} + +static void rm_free_clock(struct rm_clock *pclock) +{ + pclock->prm = NULL; + ATOMIC_SET(&(pclock->counter), 0); + pclock->evid = RM_EV_max; +} + +static int is_list_linked(const struct list_head *head) +{ + return head->prev != NULL; +} + +void rm_free_rmobj(struct rm_obj *prm) +{ + if (is_list_linked(&prm->list)) + rtw_list_delete(&prm->list); + + if (prm->q.pssid) + rtw_mfree(prm->q.pssid, strlen(prm->q.pssid)+1); + + if (prm->q.opt.bcn.req_start) + rtw_mfree(prm->q.opt.bcn.req_start, + prm->q.opt.bcn.req_len); + + if (prm->pclock) + rm_free_clock(prm->pclock); + + rtw_mfree((void *)prm, sizeof(struct rm_obj)); +} + +struct rm_obj *rm_alloc_rmobj(_adapter *padapter) +{ + struct rm_obj *prm; + + + prm = (struct rm_obj *)rtw_malloc(sizeof(struct rm_obj)); + if (prm == NULL) + return NULL; + + _rtw_memset(prm, 0, sizeof(struct rm_obj)); + + /* alloc timer */ + if ((prm->pclock = rm_alloc_clock(padapter, prm)) == NULL) { + rm_free_rmobj(prm); + return NULL; + } + return prm; +} + +int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *prm, bool to_head) +{ + _irqL irqL; + struct rm_priv *prmpriv = &padapter->rmpriv; + _queue *queue = &prmpriv->rm_queue; + + + if (prm == NULL) + return _FAIL; + + _enter_critical(&queue->lock, &irqL); + if (to_head) + rtw_list_insert_head(&prm->list, &queue->queue); + else + rtw_list_insert_tail(&prm->list, &queue->queue); + _exit_critical(&queue->lock, &irqL); + + rm_state_initial(prm); + + return _SUCCESS; +} + +static struct rm_obj *rm_dequeue_rm(_queue *queue) +{ + _irqL irqL; + struct rm_obj *prm; + + + _enter_critical(&queue->lock, &irqL); + if (rtw_is_list_empty(&(queue->queue))) + prm = NULL; + else { + prm = LIST_CONTAINOR(get_next(&(queue->queue)), + struct rm_obj, list); + /* rtw_list_delete(&prm->list); */ + } + _exit_critical(&queue->lock, &irqL); + + return prm; +} + +static struct rm_event *rm_dequeue_ev(_queue *queue) +{ + _irqL irqL; + struct rm_event *ev; + + + _enter_critical(&queue->lock, &irqL); + if (rtw_is_list_empty(&(queue->queue))) + ev = NULL; + else { + ev = LIST_CONTAINOR(get_next(&(queue->queue)), + struct rm_event, list); + rtw_list_delete(&ev->list); + } + _exit_critical(&queue->lock, &irqL); + + return ev; +} + +static struct rm_obj *_rm_get_rmobj(_queue *queue, u32 rmid) +{ + _irqL irqL; + _list *phead, *plist; + struct rm_obj *prm = NULL; + + + if (rmid == 0) + return NULL; + + _enter_critical(&queue->lock, &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + + prm = LIST_CONTAINOR(plist, struct rm_obj, list); + if (rmid == (prm->rmid)) { + _exit_critical(&queue->lock, &irqL); + return prm; + } + plist = get_next(plist); + } + _exit_critical(&queue->lock, &irqL); + + return NULL; +} + +struct sta_info *rm_get_psta(_adapter *padapter, u32 rmid) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_obj *prm; + + + prm = _rm_get_rmobj(&prmpriv->rm_queue, rmid); + + if (prm) + return prm->psta; + + return NULL; +} + +struct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + + return _rm_get_rmobj(&prmpriv->rm_queue, rmid); +} + +u8 rtw_rm_post_envent_cmd(_adapter *padapter, u32 rmid, u8 evid) +{ + struct cmd_obj *pcmd; + struct rm_event *pev; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + + pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd == NULL) { + res = _FAIL; + goto exit; + } + pev = (struct rm_event*)rtw_zmalloc(sizeof(struct rm_event)); + + if (pev == NULL) { + rtw_mfree((u8 *) pcmd, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + pev->rmid = rmid; + pev->evid = evid; + + init_h2fwcmd_w_parm_no_rsp(pcmd, pev, GEN_CMD_CODE(_RM_POST_EVENT)); + res = rtw_enqueue_cmd(pcmdpriv, pcmd); +exit: + return res; +} + +int rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid) +{ + if (padapter->rmpriv.enable == _FALSE) + return _FALSE; + + RTW_INFO("RM: post asyn %s to rmid=%x\n", rm_event_name(evid), rmid); + rtw_rm_post_envent_cmd(padapter, rmid, evid); + return _SUCCESS; +} + +int _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_event *pev; + + if (evid >= RM_EV_max || rmid == 0) + return _FALSE; + + pev = (struct rm_event *)rtw_malloc(sizeof(struct rm_event)); + if (pev == NULL) + return _FALSE; + + pev->rmid = rmid; + pev->evid = evid; + + RTW_INFO("RM: post sync %s to rmid=%x\n", rm_event_name(evid), rmid); + rm_enqueue_ev(&prmpriv->ev_queue, pev, FALSE); + + return _SUCCESS; +} + +static void rm_bcast_aid_handler(_adapter *padapter, struct rm_event *pev) +{ + _irqL irqL; + _list *phead, *plist; + _queue *queue = &padapter->rmpriv.rm_queue; + struct rm_obj *prm; + + + _enter_critical(&queue->lock, &irqL); + phead = get_list_head(queue); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + + prm = LIST_CONTAINOR(plist, struct rm_obj, list); + plist = get_next(plist); + if (RM_GET_AID(pev->rmid) == RM_GET_AID(prm->rmid)) { + _exit_critical(&queue->lock, &irqL); + rm_state_run(prm, pev->evid); + _enter_critical(&queue->lock, &irqL); + } + } + _exit_critical(&queue->lock, &irqL); + return; +} + +/* main handler of RM (Resource Management) */ +void rm_handler(_adapter *padapter, struct rm_event *pe) +{ + int i; + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_obj *prm; + struct rm_event *pev; + + + /* dequeue event */ + while((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL) + { + if (RM_IS_ID_FOR_ALL(pev->rmid)) { + /* apply to all aid mateched measurement */ + rm_bcast_aid_handler(padapter, pev); + rtw_mfree((void *)pev, sizeof(struct rm_event)); + continue; + } + + /* retrieve rmobj */ + prm = _rm_get_rmobj(&prmpriv->rm_queue, pev->rmid); + if (prm == NULL) { + RTW_ERR("RM: rmid=%x event=%s doesn't find rm obj\n", + pev->rmid, rm_event_name(pev->evid)); + rtw_mfree((void *)pev, sizeof(struct rm_event)); + return; + } + /* run state machine */ + rm_state_run(prm, pev->evid); + rtw_mfree((void *)pev, sizeof(struct rm_event)); + } +} + +static int rm_issue_meas_req(struct rm_obj *prm) +{ + switch (prm->q.action_code) { + case RM_ACT_RADIO_MEAS_REQ: + switch (prm->q.m_type) { + case bcn_req: + case ch_load_req: + case noise_histo_req: + issue_radio_meas_req(prm); + break; + default: + break; + } /* meas_type */ + break; + case RM_ACT_NB_REP_REQ: + /* issue neighbor request */ + issue_nb_req(prm); + break; + case RM_ACT_LINK_MEAS_REQ: + default: + return _FALSE; + } /* action_code */ + + return _SUCCESS; +} + +/* +* RM state machine +*/ + +static int rm_state_idle(struct rm_obj *prm, enum RM_EV_ID evid) +{ + _adapter *padapter = prm->psta->padapter; + u8 val8; + u32 val32; + + + prm->p.category = RTW_WLAN_CATEGORY_RADIO_MEAS; + + switch (evid) { + case RM_EV_state_in: + switch (prm->q.action_code) { + case RM_ACT_RADIO_MEAS_REQ: + /* copy attrib from meas_req to meas_rep */ + prm->p.action_code = RM_ACT_RADIO_MEAS_REP; + prm->p.diag_token = prm->q.diag_token; + prm->p.e_id = _MEAS_RSP_IE_; + prm->p.m_token = prm->q.m_token; + prm->p.m_type = prm->q.m_type; + prm->p.rpt = prm->q.rpt; + prm->p.ch_num = prm->q.ch_num; + prm->p.op_class = prm->q.op_class; + + if (prm->q.m_type == ch_load_req + || prm->q.m_type == noise_histo_req) { + /* + * phydm measure current ch periodically + * scan current ch is not necessary + */ + val8 = padapter->mlmeextpriv.cur_channel; + if (prm->q.ch_num == val8) + prm->poll_mode = 1; + } + RTW_INFO("RM: rmid=%x %s switch in repeat=%u\n", + prm->rmid, rm_type_req_name(prm->q.m_type), + prm->q.rpt); + break; + case RM_ACT_NB_REP_REQ: + prm->p.action_code = RM_ACT_NB_REP_RESP; + RTW_INFO("RM: rmid=%x Neighbor request switch in\n", + prm->rmid); + break; + case RM_ACT_LINK_MEAS_REQ: + prm->p.action_code = RM_ACT_LINK_MEAS_REP; + rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP); + RTW_INFO("RM: rmid=%x Link meas switch in\n", + prm->rmid); + break; + default: + prm->p.action_code = prm->q.action_code; + rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP); + RTW_INFO("RM: rmid=%x recv unknown action %d\n", + prm->rmid,prm->p.action_code); + break; + } /* switch() */ + + if (prm->rmid & RM_MASTER) { + if (rm_issue_meas_req(prm) == _SUCCESS) + rm_state_goto(prm, RM_ST_WAIT_MEAS); + else + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } else { + rm_state_goto(prm, RM_ST_DO_MEAS); + return _SUCCESS; + } + + if (prm->p.m_mode) { + issue_null_reply(prm); + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + if (prm->q.rand_intvl) { + /* get low tsf to generate random interval */ + val32 = rtw_read32(padapter, REG_TSFTR); + val32 = val32 % prm->q.rand_intvl; + RTW_INFO("RM: rmid=%x rand_intval=%d, rand=%d\n", + prm->rmid, (int)prm->q.rand_intvl,val32); + rm_set_clock(prm, prm->q.rand_intvl, + RM_EV_delay_timer_expire); + return _SUCCESS; + } + break; + case RM_EV_delay_timer_expire: + rm_state_goto(prm, RM_ST_DO_MEAS); + break; + case RM_EV_cancel: + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_state_out: + rm_cancel_clock(prm); + break; + default: + break; + } + return _SUCCESS; +} + +/* we do the measuring */ +static int rm_state_do_meas(struct rm_obj *prm, enum RM_EV_ID evid) +{ + _adapter *padapter = prm->psta->padapter; + u8 val8; + u64 val64; + + + switch (evid) { + case RM_EV_state_in: + if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) { + switch (prm->q.m_type) { + case bcn_req: + if (prm->q.m_mode == bcn_req_bcn_table) { + RTW_INFO("RM: rmid=%x Beacon table\n", + prm->rmid); + _rm_post_event(padapter, prm->rmid, + RM_EV_survey_done); + return _SUCCESS; + } + break; + case ch_load_req: + case noise_histo_req: + if (prm->poll_mode) + _rm_post_event(padapter, prm->rmid, + RM_EV_survey_done); + return _SUCCESS; + default: + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + + if (!ready_for_scan(prm)) { + prm->wait_busy = RM_BUSY_TRAFFIC_TIMES; + RTW_INFO("RM: wait busy traffic - %d\n", + prm->wait_busy); + rm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT, + RM_EV_busy_timer_expire); + return _SUCCESS; + } + } + _rm_post_event(padapter, prm->rmid, RM_EV_start_meas); + break; + case RM_EV_start_meas: + if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) { + /* resotre measurement start time */ + rtw_hal_get_hwreg(padapter, HW_VAR_TSF, (u8 *)&val64); + prm->meas_start_time = val64; + + switch (prm->q.m_type) { + case bcn_req: + val8 = 1; /* Enable free run counter */ + rtw_hal_set_hwreg(padapter, + HW_VAR_FREECNT, &val8); + rm_sitesurvey(prm); + break; + case ch_load_req: + case noise_histo_req: + rm_sitesurvey(prm); + break; + default: + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + break; + } + } + /* handle measurement timeout */ + rm_set_clock(prm, RM_MEAS_TIMEOUT, RM_EV_meas_timer_expire); + break; + case RM_EV_survey_done: + if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) { + switch (prm->q.m_type) { + case bcn_req: + rm_cancel_clock(prm); + rm_state_goto(prm, RM_ST_SEND_REPORT); + return _SUCCESS; + case ch_load_req: + case noise_histo_req: + retrieve_radio_meas_result(prm); + + if (rm_radio_meas_report_cond(prm) == _SUCCESS) + rm_state_goto(prm, RM_ST_SEND_REPORT); + else + rm_set_clock(prm, RM_COND_INTVL, + RM_EV_retry_timer_expire); + break; + default: + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + } + break; + case RM_EV_meas_timer_expire: + RTW_INFO("RM: rmid=%x measurement timeount\n",prm->rmid); + rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE); + issue_null_reply(prm); + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_busy_timer_expire: + if (!ready_for_scan(prm) && prm->wait_busy--) { + RTW_INFO("RM: wait busy - %d\n",prm->wait_busy); + rm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT, + RM_EV_busy_timer_expire); + break; + } + else if (prm->wait_busy <= 0) { + RTW_INFO("RM: wait busy timeout\n"); + rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE); + issue_null_reply(prm); + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + _rm_post_event(padapter, prm->rmid, RM_EV_start_meas); + break; + case RM_EV_request_timer_expire: + rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE); + issue_null_reply(prm); + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_retry_timer_expire: + /* expired due to meas condition mismatch, meas again */ + _rm_post_event(padapter, prm->rmid, RM_EV_start_meas); + break; + case RM_EV_cancel: + rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE); + issue_null_reply(prm); + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_state_out: + rm_cancel_clock(prm); + /* resotre measurement end time */ + rtw_hal_get_hwreg(padapter, HW_VAR_TSF, (u8 *)&val64); + _rtw_memcpy(&prm->meas_end_time, (char *)&val64, sizeof(u64)); + + val8 = 0; /* Disable free run counter */ + rtw_hal_set_hwreg(padapter, HW_VAR_FREECNT, &val8); + break; + default: + break; + } + + return _SUCCESS; +} + +static int rm_state_wait_meas(struct rm_obj *prm, enum RM_EV_ID evid) +{ + u8 val8; + u64 val64; + + + switch (evid) { + case RM_EV_state_in: + /* we create meas_req, waiting for peer report */ + rm_set_clock(prm, RM_REQ_TIMEOUT, + RM_EV_request_timer_expire); + break; + case RM_EV_recv_rep: + rm_state_goto(prm, RM_ST_RECV_REPORT); + break; + case RM_EV_request_timer_expire: + case RM_EV_cancel: + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_state_out: + rm_cancel_clock(prm); + break; + default: + break; + } + return _SUCCESS; +} + +static int rm_state_send_report(struct rm_obj *prm, enum RM_EV_ID evid) +{ + u8 val8; + + + switch (evid) { + case RM_EV_state_in: + /* we have to issue report */ + switch (prm->q.m_type) { + case bcn_req: + issue_beacon_rep(prm); + break; + case ch_load_req: + case noise_histo_req: + issue_radio_meas_rep(prm); + break; + default: + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + + /* check repeat */ + if (prm->p.rpt) { + RTW_INFO("RM: rmid=%x repeat=%u/%u\n", + prm->rmid, prm->p.rpt, + prm->q.rpt); + prm->p.rpt--; + /* + * we recv meas_req, + * delay for a wihile and than meas again + */ + if (prm->poll_mode) + rm_set_clock(prm, RM_REPT_POLL_INTVL, + RM_EV_repeat_delay_expire); + else + rm_set_clock(prm, RM_REPT_SCAN_INTVL, + RM_EV_repeat_delay_expire); + return _SUCCESS; + } + /* we are done */ + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_repeat_delay_expire: + rm_state_goto(prm, RM_ST_DO_MEAS); + break; + case RM_EV_cancel: + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_state_out: + rm_cancel_clock(prm); + break; + default: + break; + } + return _SUCCESS; +} + +static int rm_state_recv_report(struct rm_obj *prm, enum RM_EV_ID evid) +{ + u8 val8; + + + switch (evid) { + case RM_EV_state_in: + /* we issue meas_req, got peer's meas report */ + switch (prm->p.action_code) { + case RM_ACT_RADIO_MEAS_REP: + /* check refuse, incapable and repeat */ + val8 = prm->p.m_mode; + if (val8) { + RTW_INFO("RM: rmid=%x peer reject (%s repeat=%d)\n", + prm->rmid, + val8|MEAS_REP_MOD_INCAP?"INCAP": + val8|MEAS_REP_MOD_REFUSE?"REFUSE": + val8|MEAS_REP_MOD_LATE?"LATE":"", + prm->p.rpt); + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + break; + case RM_ACT_NB_REP_RESP: + /* report to upper layer if needing */ + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + default: + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + /* check repeat */ + if (prm->p.rpt) { + RTW_INFO("RM: rmid=%x repeat=%u/%u\n", + prm->rmid, prm->p.rpt, + prm->q.rpt); + prm->p.rpt--; + /* waitting more report */ + rm_state_goto(prm, RM_ST_WAIT_MEAS); + break; + } + /* we are done */ + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_cancel: + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_state_out: + rm_cancel_clock(prm); + break; + default: + break; + } + return _SUCCESS; +} + +static int rm_state_end(struct rm_obj *prm, enum RM_EV_ID evid) +{ + switch (evid) { + case RM_EV_state_in: + _rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_out); + break; + + case RM_EV_cancel: + case RM_EV_state_out: + default: + rm_free_rmobj(prm); + break; + } + return _SUCCESS; +} + +struct fsm_state rm_fsm[] = { + {"RM_ST_IDLE", rm_state_idle}, + {"RM_ST_DO_MEAS", rm_state_do_meas}, + {"RM_ST_WAIT_MEAS", rm_state_wait_meas}, + {"RM_ST_SEND_REPORT", rm_state_send_report}, + {"RM_ST_RECV_REPORT", rm_state_recv_report}, + {"RM_ST_END", rm_state_end} +}; + +char *rm_state_name(enum RM_STATE state) +{ + return rm_fsm[state].name; +} + +char *rm_event_name(enum RM_EV_ID evid) +{ + switch(evid) { + case RM_EV_state_in: + return "RM_EV_state_in"; + case RM_EV_busy_timer_expire: + return "RM_EV_busy_timer_expire"; + case RM_EV_delay_timer_expire: + return "RM_EV_delay_timer_expire"; + case RM_EV_meas_timer_expire: + return "RM_EV_meas_timer_expire"; + case RM_EV_repeat_delay_expire: + return "RM_EV_repeat_delay_expire"; + case RM_EV_retry_timer_expire: + return "RM_EV_retry_timer_expire"; + case RM_EV_request_timer_expire: + return "RM_EV_request_timer_expire"; + case RM_EV_wait_report: + return "RM_EV_wait_report"; + case RM_EV_start_meas: + return "RM_EV_start_meas"; + case RM_EV_survey_done: + return "RM_EV_survey_done"; + case RM_EV_recv_rep: + return "RM_EV_recv_report"; + case RM_EV_cancel: + return "RM_EV_cancel"; + case RM_EV_state_out: + return "RM_EV_state_out"; + case RM_EV_max: + return "RM_EV_max"; + default: + return "RM_EV_unknown"; + } + return "UNKNOWN"; +} + +static void rm_state_initial(struct rm_obj *prm) +{ + prm->state = RM_ST_IDLE; + + RTW_INFO("\n"); + RTW_INFO("RM: rmid=%x %-18s -> %s\n",prm->rmid, + "new measurement", rm_fsm[prm->state].name); + + rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_in); +} + +static void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid) +{ + RTW_INFO("RM: rmid=%x %-18s %s\n",prm->rmid, + rm_fsm[prm->state].name,rm_event_name(evid)); + + rm_fsm[prm->state].fsm_func(prm, evid); +} + +static void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state) +{ + if (prm->state == rm_state) + return; + + rm_state_run(prm, RM_EV_state_out); + + RTW_INFO("\n"); + RTW_INFO("RM: rmid=%x %-18s -> %s\n",prm->rmid, + rm_fsm[prm->state].name, rm_fsm[rm_state].name); + + prm->state = rm_state; + rm_state_run(prm, RM_EV_state_in); +} +#endif /* CONFIG_RTW_80211K */ diff --git a/core/rtw_rson.c b/core/rtw_rson.c new file mode 100644 index 0000000..0aa5850 --- /dev/null +++ b/core/rtw_rson.c @@ -0,0 +1,595 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_RSON_C_ + +#include + +#ifdef CONFIG_RTW_REPEATER_SON + +/******** Custommize Part ***********************/ + +unsigned char RTW_RSON_OUI[] = {0xFA, 0xFA, 0xFA}; +#define RSON_SCORE_DIFF_TH 8 + +/* + Calculate the corresponding score. +*/ +inline u8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI Rssi) +{ + if ((cand_rson_data->hopcnt == RTW_RSON_HC_NOTREADY) + || (cand_rson_data->connectible == RTW_RSON_DENYCONNECT)) + return RTW_RSON_SCORE_NOTCNNT; + + return RTW_RSON_SCORE_MAX - (cand_rson_data->hopcnt * 10) + (Rssi/10); +} + +/*************************************************/ + + +static u8 rtw_rson_block_bssid_idx = 0; +u8 rtw_rson_block_bssid[10][6] = { + /*{0x02, 0xE0, 0x4C, 0x07, 0xC3, 0xF6}*/ +}; + +/* fake root, regard a real AP as a SO root */ +static u8 rtw_rson_root_bssid_idx = 0; +u8 rtw_rson_root_bssid[10][6] = { + /*{0x1c, 0x5f, 0x2b, 0x5a, 0x60, 0x24}*/ +}; + +int is_match_bssid(u8 *mac, u8 bssid_array[][6], int num) +{ + int i; + + for (i = 0; i < num; i++) + if (_rtw_memcmp(mac, bssid_array[i], 6) == _TRUE) + return _TRUE; + return _FALSE; +} + +void init_rtw_rson_data(struct dvobj_priv *dvobj) +{ + /*Aries todo. if pdvobj->rson_data.ver == 1 */ + dvobj->rson_data.ver = RTW_RSON_VER; + dvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID; +#ifdef CONFIG_RTW_REPEATER_SON_ROOT + dvobj->rson_data.hopcnt = RTW_RSON_HC_ROOT; + dvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT; +#else + dvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY; + dvobj->rson_data.connectible = RTW_RSON_DENYCONNECT; +#endif + dvobj->rson_data.loading = 0; + _rtw_memset(dvobj->rson_data.res, 0xAA, sizeof(dvobj->rson_data.res)); +} + +void rtw_rson_get_property_str(_adapter *padapter, char *rson_data_str) +{ + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + + sprintf(rson_data_str, "version : \t%d\nid : \t\t%08x\nhop count : \t%d\nconnectible : \t%s\nloading : \t%d\nreserve : \t%16ph\n", + pdvobj->rson_data.ver, + pdvobj->rson_data.id, + pdvobj->rson_data.hopcnt, + pdvobj->rson_data.connectible ? "connectable":"unconnectable", + pdvobj->rson_data.loading, + pdvobj->rson_data.res); +} + +int str2hexbuf(char *str, u8 *hexbuf, int len) +{ + u8 *p; + int i, slen, idx = 0; + + p = (unsigned char *)str; + if ((*p != '0') || (*(p+1) != 'x')) + return _FALSE; + slen = strlen(str); + if (slen > (len*2) + 2) + return _FALSE; + p += 2; + for (i = 0 ; i < len; i++, idx = idx+2) { + hexbuf[i] = key_2char2num(p[idx], p[idx + 1]); + if (slen <= idx+2) + break; + } + return _TRUE; +} + +int rtw_rson_set_property(_adapter *padapter, char *field, char *value) +{ + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + int num = 0; + + if (_rtw_memcmp(field, (u8 *)"ver", 3) == _TRUE) + pdvobj->rson_data.ver = rtw_atoi(value); + else if (_rtw_memcmp(field, (u8 *)"id", 2) == _TRUE) + num = sscanf(value, "%08x", &(pdvobj->rson_data.id)); + else if (_rtw_memcmp(field, (u8 *)"hc", 2) == _TRUE) + num = sscanf(value, "%hhu", &(pdvobj->rson_data.hopcnt)); + else if (_rtw_memcmp(field, (u8 *)"cnt", 3) == _TRUE) + num = sscanf(value, "%hhu", &(pdvobj->rson_data.connectible)); + else if (_rtw_memcmp(field, (u8 *)"loading", 2) == _TRUE) + num = sscanf(value, "%hhu", &(pdvobj->rson_data.loading)); + else if (_rtw_memcmp(field, (u8 *)"res", 2) == _TRUE) { + str2hexbuf(value, pdvobj->rson_data.res, 16); + return 1; + } else + return _FALSE; + return num; +} + +/* + return : TRUE -- competitor is taking advantage than condidate + FALSE -- we should continue keeping candidate +*/ +int rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor) +{ + s16 comp_score = 0, cand_score = 0; + struct rtw_rson_struct rson_cand, rson_comp; + + if (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE) + return _FALSE; + + if ((competitor == NULL) + || (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE) + || (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID)) + return _FALSE; + + comp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi); + if (comp_score == RTW_RSON_SCORE_NOTCNNT) + return _FALSE; + + if (*candidate == NULL) + return _TRUE; + if (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE) + return _FALSE; + + cand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi); + RTW_INFO("%s: competitor_score=%d, candidate_score=%d\n", __func__, comp_score, cand_score); + if (comp_score - cand_score > RSON_SCORE_DIFF_TH) + return _TRUE; + + return _FALSE; +} + +inline u8 rtw_rson_varify_ie(u8 *p) +{ + u8 *ptr = NULL; + u8 ver; + u32 id; + u8 hopcnt; + u8 allcnnt; + + ptr = p + 2 + sizeof(RTW_RSON_OUI); + ver = *ptr; + + /* for (ver == 1) */ + if (ver != 1) + return _FALSE; + + return _TRUE; +} + +/* + Parsing RTK self-organization vendor IE +*/ +int rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct rtw_rson_struct *rson_data) +{ + sint limit = 0; + u32 len; + u8 *p; + + if ((rson_data == NULL) || (bssid == NULL)) + return -EINVAL; + + /* Default */ + rson_data->id = 0; + rson_data->ver = 0; + rson_data->hopcnt = 0; + rson_data->connectible = 0; + rson_data->loading = 0; + /* fake root */ + if (is_match_bssid(bssid->MacAddress, rtw_rson_root_bssid, rtw_rson_root_bssid_idx) == _TRUE) { + rson_data->id = CONFIG_RTW_REPEATER_SON_ID; + rson_data->ver = RTW_RSON_VER; + rson_data->hopcnt = RTW_RSON_HC_ROOT; + rson_data->connectible = RTW_RSON_ALLOWCONNECT; + rson_data->loading = 0; + return _TRUE; + } + limit = bssid->IELength - _BEACON_IE_OFFSET_; + + for (p = bssid->IEs + _BEACON_IE_OFFSET_; ; p += (len + 2)) { + p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, limit); + limit -= len; + if ((p == NULL) || (len == 0)) + break; + if (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE) + && rtw_rson_varify_ie(p)) { + p = p + 2 + sizeof(RTW_RSON_OUI); + rson_data->ver = *p; + /* for (ver == 1) */ + p = p + 1; + rson_data->id = le32_to_cpup((__le32 *)p); + p = p + 4; + rson_data->hopcnt = *p; + p = p + 1; + rson_data->connectible = *p; + p = p + 1; + rson_data->loading = *p; + + return _TRUE; + } + } + return -EBADMSG; +} + +u32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len) +{ + u8 *ptr, *ori, ie_len = 0; + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); +/* static int iii = 0;*/ + + if ((!pdvobj) || (!pframe)) + return 0; + ptr = ori = pframe; + *ptr++ = _VENDOR_SPECIFIC_IE_; + *ptr++ = ie_len = sizeof(RTW_RSON_OUI)+sizeof(pdvobj->rson_data); + _rtw_memcpy(ptr, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)); + ptr = ptr + sizeof(RTW_RSON_OUI); + *ptr++ = pdvobj->rson_data.ver; + *(s32 *)ptr = cpu_to_le32(pdvobj->rson_data.id); + ptr = ptr + sizeof(pdvobj->rson_data.id); + *ptr++ = pdvobj->rson_data.hopcnt; + *ptr++ = pdvobj->rson_data.connectible; + *ptr++ = pdvobj->rson_data.loading; + _rtw_memcpy(ptr, pdvobj->rson_data.res, sizeof(pdvobj->rson_data.res)); + pframe = ptr; +/* + iii = iii % 20; + if (iii++ == 0) + RTW_INFO("%s : RTW RSON IE : %20ph\n", __func__, ori); +*/ + *len += (ie_len+2); + return ie_len; + +} + +void rtw_rson_do_disconnect(_adapter *padapter) +{ + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); +#ifndef CONFIG_RTW_REPEATER_SON_ROOT + pdvobj->rson_data.ver = RTW_RSON_VER; + pdvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID; + pdvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY; + pdvobj->rson_data.connectible = RTW_RSON_DENYCONNECT; + pdvobj->rson_data.loading = 0; + rtw_mi_tx_beacon_hdl(padapter); +#endif +} + +void rtw_rson_join_done(_adapter *padapter) +{ + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + WLAN_BSSID_EX *cur_network = NULL; + struct rtw_rson_struct rson_data; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + if (!padapter->mlmepriv.cur_network_scanned) + return; + cur_network = &(padapter->mlmepriv.cur_network_scanned->network); + if (rtw_get_rson_struct(cur_network, &rson_data) != _TRUE) { + RTW_ERR("%s: try to join a improper network(%s)\n", __func__, cur_network->Ssid.Ssid); + return; + } + +#ifndef CONFIG_RTW_REPEATER_SON_ROOT + /* update rson_data */ + pdvobj->rson_data.ver = RTW_RSON_VER; + pdvobj->rson_data.id = rson_data.id; + pdvobj->rson_data.hopcnt = rson_data.hopcnt + 1; + pdvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT; + pdvobj->rson_data.loading = 0; + rtw_mi_tx_beacon_hdl(padapter); +#endif +} + +int rtw_rson_isupdate_roamcan(struct mlme_priv *mlme + , struct wlan_network **candidate, struct wlan_network *competitor) +{ + struct rtw_rson_struct rson_cand, rson_comp, rson_curr; + s16 comp_score, cand_score, curr_score; + + if ((competitor == NULL) + || (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE) + || (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID)) + return _FALSE; + + if (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE) + return _FALSE; + + if ((!mlme->cur_network_scanned) + || (mlme->cur_network_scanned == competitor) + || (rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr)) != _TRUE) + return _FALSE; + + if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms) + return _FALSE; + + comp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi); + curr_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi); + if (comp_score - curr_score < RSON_SCORE_DIFF_TH) + return _FALSE; + + if (*candidate == NULL) + return _TRUE; + + if (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE) { + RTW_ERR("%s : Unable to get rson_struct from candidate(%s -- " MAC_FMT")\n", + __func__, (*candidate)->network.Ssid.Ssid, MAC_ARG((*candidate)->network.MacAddress)); + return _FALSE; + } + cand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi); + RTW_DBG("comp_score=%d , cand_score=%d , curr_score=%d\n", comp_score, cand_score, curr_score); + if (cand_score < comp_score) + return _TRUE; + +#if 0 /* Handle 11R protocol */ +#ifdef CONFIG_RTW_80211R + if (rtw_chk_ft_flags(adapter, RTW_FT_SUPPORTED)) { + ptmp = rtw_get_ie(&competitor->network.IEs[12], _MDIE_, &mdie_len, competitor->network.IELength-12); + if (ptmp) { + if (!_rtw_memcmp(&pftpriv->mdid, ptmp+2, 2)) + goto exit; + + /*The candidate don't support over-the-DS*/ + if (rtw_chk_ft_flags(adapter, RTW_FT_STA_OVER_DS_SUPPORTED)) { + if ((rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && !(*(ptmp+4) & 0x01)) || + (!rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && (*(ptmp+4) & 0x01))) { + RTW_INFO("FT: ignore the candidate(" MAC_FMT ") for over-the-DS\n", MAC_ARG(competitor->network.MacAddress)); + rtw_clr_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED); + goto exit; + } + } + } else + goto exit; + } +#endif +#endif + return _FALSE; +} + +void rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead) +{ + struct wlan_network *pnetwork = NULL; + struct rtw_rson_struct rson_data; + s16 rson_score; + u16 index = 0; + + RTW_PRINT_SEL(m, "%5s %-17s %3s %5s %14s %10s %-3s %5s %32s\n", "index", "bssid", "ch", "id", "hop_cnt", "loading", "RSSI", "score", "ssid"); + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (!pnetwork) + break; + + _rtw_memset(&rson_data, 0, sizeof(rson_data)); + rson_score = 0; + if (rtw_get_rson_struct(&(pnetwork->network), &rson_data) == _TRUE) + rson_score = rtw_cal_rson_score(&rson_data, pnetwork->network.Rssi); + RTW_PRINT_SEL(m, "%5d "MAC_FMT" %3d 0x%08x %6d %10d %6d %6d %32s\n", + ++index, + MAC_ARG(pnetwork->network.MacAddress), + pnetwork->network.Configuration.DSConfig, + rson_data.id, + rson_data.hopcnt, + rson_data.loading, + (int)pnetwork->network.Rssi, + rson_score, + pnetwork->network.Ssid.Ssid); + plist = get_next(plist); + } + +} + +/* + Description : As a AP role, We need to check the qualify of associating STA. + We also need to check if we are ready to be associated. + + return : TRUE -- AP REJECT this STA + FALSE -- AP ACCEPT this STA +*/ +u8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset) +{ + struct wlan_network *pnetwork = NULL; + struct rtw_rson_struct rson_target; + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + int len = 0; + u8 ret = _FALSE; + u8 *p; + +#ifndef CONFIG_RTW_REPEATER_SON_ROOT + _rtw_memset(&rson_target, 0, sizeof(rson_target)); + for (p = pframe + WLAN_HDR_A3_LEN + ie_offset; ; p += (len + 2)) { + p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, pkt_len - WLAN_HDR_A3_LEN - ie_offset); + + if ((p == NULL) || (len == 0)) + break; + + if (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE) + && rtw_rson_varify_ie(p)) { + p = p + 2 + sizeof(RTW_RSON_OUI); + rson_target.ver = *p; + /* for (ver == 1) */ + p = p + 1; + rson_target.id = le32_to_cpup((__le32 *)p); + p = p + 4; + rson_target.hopcnt = *p; + p = p + 1; + rson_target.connectible = *p; + p = p + 1; + rson_target.loading = *p; + break; + } + } + + if (rson_target.id == 0) /* Normal STA, not a RSON STA */ + ret = _FALSE; + else if (rson_target.id != pdvobj->rson_data.id) { + ret = _TRUE; + RTW_INFO("%s : Reject AssoReq because RSON ID not match, STA=%08x, our=%08x\n", + __func__, rson_target.id, pdvobj->rson_data.id); + } else if ((pdvobj->rson_data.hopcnt == RTW_RSON_HC_NOTREADY) + || (pdvobj->rson_data.connectible == RTW_RSON_DENYCONNECT)) { + ret = _TRUE; + RTW_INFO("%s : Reject AssoReq becuase our hopcnt=%d or connectbile=%d\n", + __func__, pdvobj->rson_data.hopcnt, pdvobj->rson_data.connectible); + } +#endif + return ret; +} + +u8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 *extra_cmd_buf; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + pdrvextra_cmd_parm->ec_id = RSON_SCAN_WK_CID; + pdrvextra_cmd_parm->type = op; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + return res; + +} + +void rtw_rson_scan_cmd_hdl(_adapter *padapter, int op) +{ + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 val8; + + if (mlmeext_chk_scan_state(pmlmeext, SCAN_DISABLE) != _TRUE) + return; + if (op == RSON_SCAN_PROCESS) { + padapter->rtw_rson_scanstage = RSON_SCAN_PROCESS; + val8 = 0x1e; + rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE); + val8 = 1; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + issue_probereq(padapter, NULL, NULL); + /* stop rson_scan after 100ms */ + _set_timer(&(pmlmeext->rson_scan_timer), 100); + } else if (op == RSON_SCAN_DISABLE) { + padapter->rtw_rson_scanstage = RSON_SCAN_DISABLE; + val8 = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + val8 = 0xff; + rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE); + /* report_surveydone_event(padapter);*/ + if (pmlmepriv->to_join == _TRUE) { + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) != _TRUE) { + int s_ret; + + set_fwstate(pmlmepriv, _FW_UNDER_LINKING); + pmlmepriv->to_join = _FALSE; + s_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv); + if (s_ret == _SUCCESS) + _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); + else if (s_ret == 2) { + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + rtw_indicate_connect(padapter); + } else { + RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(padapter)); + if (rtw_to_roam(padapter) != 0) { + if (rtw_dec_to_roam(padapter) == 0) { + rtw_set_to_roam(padapter, 0); +#ifdef CONFIG_INTEL_WIDI + if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) { + _rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN); + intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_WK, NULL, 0); + RTW_INFO("change to widi listen\n"); + } +#endif /* CONFIG_INTEL_WIDI */ + rtw_free_assoc_resources(padapter, 1); + rtw_indicate_disconnect(padapter, 0, _FALSE); + } else + pmlmepriv->to_join = _TRUE; + } else + rtw_indicate_disconnect(padapter, 0, _FALSE); + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + } + } + } else { + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) { + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) + && check_fwstate(pmlmepriv, _FW_LINKED)) { + if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) { +#ifdef CONFIG_RTW_80211R + if (rtw_chk_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED)) { + start_clnt_ft_action(adapter, (u8 *)pmlmepriv->roam_network->network.MacAddress); + } else { + /*wait a little time to retrieve packets buffered in the current ap while scan*/ + _set_timer(&pmlmeext->ft_roam_timer, 30); + } +#else + receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress + , WLAN_REASON_ACTIVE_ROAM, _FALSE); +#endif + } + } + } + issue_action_BSSCoexistPacket(padapter); + issue_action_BSSCoexistPacket(padapter); + issue_action_BSSCoexistPacket(padapter); + } + } else { + RTW_ERR("%s : improper parameter -- op = %d\n", __func__, op); + } +} + +#endif /* CONFIG_RTW_REPEATER_SON */ diff --git a/hal/hal_dm_acs.c b/hal/hal_dm_acs.c new file mode 100644 index 0000000..5c19d99 --- /dev/null +++ b/hal/hal_dm_acs.c @@ -0,0 +1,554 @@ +/****************************************************************************** + * + * Copyright(c) 2014 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include +#include + + +#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR) +static void _rtw_bss_nums_count(_adapter *adapter, u8 *pbss_nums) +{ + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + _list *plist, *phead; + _irqL irqL; + int chan_idx = -1; + + if (pbss_nums == NULL) { + RTW_ERR("%s pbss_nums is null pointer\n", __func__); + return; + } + _rtw_memset(pbss_nums, 0, MAX_CHANNEL_NUM); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + phead = get_list_head(queue); + plist = get_next(phead); + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (!pnetwork) + break; + chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), pnetwork->network.Configuration.DSConfig); + if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) { + RTW_ERR("%s can't get chan_idx(CH:%d)\n", + __func__, pnetwork->network.Configuration.DSConfig); + chan_idx = 0; + } + /*if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ)*/ + + pbss_nums[chan_idx]++; + + plist = get_next(plist); + } + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); +} + +u8 rtw_get_ch_num_by_idx(_adapter *adapter, u8 idx) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + RT_CHANNEL_INFO *pch_set = rfctl->channel_set; + u8 max_chan_nums = rfctl->max_chan_nums; + + if (idx >= max_chan_nums) + return 0; + return pch_set[idx].ChannelNum; +} +#endif /*defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)*/ + + +#ifdef CONFIG_RTW_ACS +void rtw_acs_version_dump(void *sel, _adapter *adapter) +{ + _RTW_PRINT_SEL(sel, "RTK_ACS VER_%d\n", RTK_ACS_VERSION); +} +u8 rtw_phydm_clm_ratio(_adapter *adapter) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CLM_RATIO); +} +u8 rtw_phydm_nhm_ratio(_adapter *adapter) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_NHM_RATIO); +} +void rtw_acs_reset(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct auto_chan_sel *pacs = &hal_data->acs; + + _rtw_memset(pacs, 0, sizeof(struct auto_chan_sel)); + #ifdef CONFIG_RTW_ACS_DBG + rtw_acs_adv_reset(adapter); + #endif /*CONFIG_RTW_ACS_DBG*/ +} + +#ifdef CONFIG_RTW_ACS_DBG +u8 rtw_is_acs_igi_valid(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct auto_chan_sel *pacs = &hal_data->acs; + + if ((pacs->igi) && ((pacs->igi >= 0x1E) || (pacs->igi < 0x60))) + return _TRUE; + + return _FALSE; +} +void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct auto_chan_sel *pacs = &hal_data->acs; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + + pacs->scan_type = scan_type; + pacs->scan_time = scan_time; + pacs->igi = igi; + pacs->bw = bw; + RTW_INFO("[ACS] ADV setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n", + pacs->scan_type ? 'A' : 'P', pacs->scan_time, pacs->igi, pacs->bw); +} +void rtw_acs_adv_reset(_adapter *adapter) +{ + rtw_acs_adv_setting(adapter, SCAN_ACTIVE, 0, 0, 0); +} +#endif /*CONFIG_RTW_ACS_DBG*/ + +void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct dm_struct *phydm = adapter_to_phydm(adapter); +#if (RTK_ACS_VERSION == 3) + struct clm_para_info clm_para; + struct nhm_para_info nhm_para; + struct env_trig_rpt trig_rpt; + + scan_time_ms -= 10; + + init_acs_clm(clm_para, scan_time_ms); + + if (pid == NHM_PID_IEEE_11K_HIGH) + init_11K_high_nhm(nhm_para, scan_time_ms); + else if (pid == NHM_PID_IEEE_11K_LOW) + init_11K_low_nhm(nhm_para, scan_time_ms); + else + init_acs_nhm(nhm_para, scan_time_ms); + + hal_data->acs.trig_rst = phydm_env_mntr_trigger(phydm, &nhm_para, &clm_para, &trig_rpt); + if (hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS)) { + hal_data->acs.trig_rpt.clm_rpt_stamp = trig_rpt.clm_rpt_stamp; + hal_data->acs.trig_rpt.nhm_rpt_stamp = trig_rpt.nhm_rpt_stamp; + /*RTW_INFO("[ACS] trigger success (rst = 0x%02x, clm_stamp:%d, nhm_stamp:%d)\n", + hal_data->acs.trig_rst, hal_data->acs.trig_rpt.clm_rpt_stamp, hal_data->acs.trig_rpt.nhm_rpt_stamp);*/ + } else + RTW_ERR("[ACS] trigger failed (rst = 0x%02x)\n", hal_data->acs.trig_rst); +#else + phydm_ccx_monitor_trigger(phydm, scan_time_ms); +#endif + + hal_data->acs.trigger_ch = scan_chan; + hal_data->acs.triggered = _TRUE; + + #ifdef CONFIG_RTW_ACS_DBG + RTW_INFO("[ACS] Trigger CH:%d, Times:%d\n", hal_data->acs.trigger_ch, scan_time_ms); + #endif +} +void rtw_acs_get_rst(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct dm_struct *phydm = adapter_to_phydm(adapter); + int chan_idx = -1; + u8 cur_chan = hal_data->acs.trigger_ch; + + if (cur_chan == 0) + return; + + if (!hal_data->acs.triggered) + return; + + chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), cur_chan); + if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) { + RTW_ERR("[ACS] %s can't get chan_idx(CH:%d)\n", __func__, cur_chan); + return; + } +#if (RTK_ACS_VERSION == 3) + if (!(hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS))) { + RTW_ERR("[ACS] get_rst return, due to acs trigger failed\n"); + return; + } + + { + struct env_mntr_rpt rpt = {0}; + u8 rst; + + rst = phydm_env_mntr_result(phydm, &rpt); + if ((rst == (NHM_SUCCESS | CLM_SUCCESS)) && + (rpt.clm_rpt_stamp == hal_data->acs.trig_rpt.clm_rpt_stamp) && + (rpt.nhm_rpt_stamp == hal_data->acs.trig_rpt.nhm_rpt_stamp)){ + hal_data->acs.clm_ratio[chan_idx] = rpt.clm_ratio; + hal_data->acs.nhm_ratio[chan_idx] = rpt.nhm_ratio; + _rtw_memcpy(&hal_data->acs.nhm[chan_idx][0], rpt.nhm_result, NHM_RPT_NUM); + + /*RTW_INFO("[ACS] get_rst success (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n", + rst, + hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp, + hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);*/ + } else { + RTW_ERR("[ACS] get_rst failed (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n", + rst, + hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp, + hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp); + } + } + +#else + phydm_ccx_monitor_result(phydm); + + hal_data->acs.clm_ratio[chan_idx] = rtw_phydm_clm_ratio(adapter); + hal_data->acs.nhm_ratio[chan_idx] = rtw_phydm_nhm_ratio(adapter); +#endif + hal_data->acs.triggered = _FALSE; + #ifdef CONFIG_RTW_ACS_DBG + RTW_INFO("[ACS] Result CH:%d, CLM:%d NHM:%d\n", + cur_chan, hal_data->acs.clm_ratio[chan_idx], hal_data->acs.nhm_ratio[chan_idx]); + #endif +} + +void _rtw_phydm_acs_select_best_chan(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + u8 ch_idx; + u8 ch_idx_24g = 0xFF, ch_idx_5g = 0xFF; + u8 min_itf_24g = 0xFF, min_itf_5g = 0xFF; + u8 *pbss_nums = hal_data->acs.bss_nums; + u8 *pclm_ratio = hal_data->acs.clm_ratio; + u8 *pnhm_ratio = hal_data->acs.nhm_ratio; + u8 *pinterference_time = hal_data->acs.interference_time; + u8 max_chan_nums = rfctl->max_chan_nums; + + for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) { + if (pbss_nums[ch_idx]) + pinterference_time[ch_idx] = (pclm_ratio[ch_idx] / 2) + pnhm_ratio[ch_idx]; + else + pinterference_time[ch_idx] = pclm_ratio[ch_idx] + pnhm_ratio[ch_idx]; + + if (rtw_get_ch_num_by_idx(adapter, ch_idx) < 14) { + if (pinterference_time[ch_idx] < min_itf_24g) { + min_itf_24g = pinterference_time[ch_idx]; + ch_idx_24g = ch_idx; + } + } else { + if (pinterference_time[ch_idx] < min_itf_5g) { + min_itf_5g = pinterference_time[ch_idx]; + ch_idx_5g = ch_idx; + } + } + } + if (ch_idx_24g != 0xFF) + hal_data->acs.best_chan_24g = rtw_get_ch_num_by_idx(adapter, ch_idx_24g); + + if (ch_idx_5g != 0xFF) + hal_data->acs.best_chan_5g = rtw_get_ch_num_by_idx(adapter, ch_idx_5g); + + hal_data->acs.trigger_ch = 0; +} + +void rtw_acs_info_dump(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + u8 max_chan_nums = rfctl->max_chan_nums; + u8 ch_idx, ch_num; + + _RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION); + _RTW_PRINT_SEL(sel, "Best 24G Channel:%d\n", hal_data->acs.best_chan_24g); + _RTW_PRINT_SEL(sel, "Best 5G Channel:%d\n\n", hal_data->acs.best_chan_5g); + + #ifdef CONFIG_RTW_ACS_DBG + _RTW_PRINT_SEL(sel, "Advanced setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n", + hal_data->acs.scan_type ? 'A' : 'P', hal_data->acs.scan_time, hal_data->acs.igi, hal_data->acs.bw); + + _RTW_PRINT_SEL(sel, "BW 20MHz\n"); + _RTW_PRINT_SEL(sel, "%5s %3s %3s %3s(%%) %3s(%%) %3s\n", + "Index", "CH", "BSS", "CLM", "NHM", "ITF"); + + for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) { + ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx); + _RTW_PRINT_SEL(sel, "%5d %3d %3d %6d %6d %3d\n", + ch_idx, ch_num, hal_data->acs.bss_nums[ch_idx], + hal_data->acs.clm_ratio[ch_idx], + hal_data->acs.nhm_ratio[ch_idx], + hal_data->acs.interference_time[ch_idx]); + } + #endif +} +void rtw_acs_select_best_chan(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + _rtw_bss_nums_count(adapter, hal_data->acs.bss_nums); + _rtw_phydm_acs_select_best_chan(adapter); + rtw_acs_info_dump(RTW_DBGDUMP, adapter); +} + +void rtw_acs_start(_adapter *adapter) +{ + rtw_acs_reset(adapter); + if (GET_ACS_STATE(adapter) != ACS_ENABLE) + SET_ACS_STATE(adapter, ACS_ENABLE); +} +void rtw_acs_stop(_adapter *adapter) +{ + SET_ACS_STATE(adapter, ACS_DISABLE); +} + + +u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + int chan_idx = -1; + + chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan); + if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) { + RTW_ERR("[ACS] Get CLM fail, can't get chan_idx(CH:%d)\n", chan); + return 0; + } + + return hal_data->acs.clm_ratio[chan_idx]; +} +u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + if (ch_idx >= MAX_CHANNEL_NUM) { + RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx); + return 0; + } + + return hal_data->acs.clm_ratio[ch_idx]; +} +u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + int chan_idx = -1; + + chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan); + if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) { + RTW_ERR("[ACS] Get NHM fail, can't get chan_idx(CH:%d)\n", chan); + return 0; + } + + return hal_data->acs.nhm_ratio[chan_idx]; +} +u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + if (ch_idx >= MAX_CHANNEL_NUM) { + RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx); + return 0; + } + + return hal_data->acs.nhm_ratio[ch_idx]; +} +void rtw_acs_chan_info_dump(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + u8 max_chan_nums = rfctl->max_chan_nums; + u8 ch_idx, ch_num; + u8 utilization; + + _RTW_PRINT_SEL(sel, "BW 20MHz\n"); + _RTW_PRINT_SEL(sel, "%5s %3s %7s(%%) %12s(%%) %11s(%%) %9s(%%) %8s(%%)\n", + "Index", "CH", "Quality", "Availability", "Utilization", + "WIFI Util", "Interference Util"); + + for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) { + ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx); + utilization = hal_data->acs.clm_ratio[ch_idx] + hal_data->acs.nhm_ratio[ch_idx]; + _RTW_PRINT_SEL(sel, "%5d %3d %7d %12d %12d %12d %12d\n", + ch_idx, ch_num, + (100-hal_data->acs.interference_time[ch_idx]), + (100-utilization), + utilization, + hal_data->acs.clm_ratio[ch_idx], + hal_data->acs.nhm_ratio[ch_idx]); + } +} +void rtw_acs_current_info_dump(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 ch, cen_ch, bw, offset; + + _RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION); + + ch = rtw_get_oper_ch(adapter); + bw = rtw_get_oper_bw(adapter); + offset = rtw_get_oper_choffset(adapter); + + _RTW_PRINT_SEL(sel, "Current Channel:%d\n", ch); + if ((bw == CHANNEL_WIDTH_80) ||(bw == CHANNEL_WIDTH_40)) { + cen_ch = rtw_get_center_ch(ch, bw, offset); + _RTW_PRINT_SEL(sel, "Center Channel:%d\n", cen_ch); + } + + _RTW_PRINT_SEL(sel, "Current BW %s\n", ch_width_str(bw)); + if (0) + _RTW_PRINT_SEL(sel, "Current IGI 0x%02x\n", rtw_phydm_get_cur_igi(adapter)); + _RTW_PRINT_SEL(sel, "CLM:%d, NHM:%d\n\n", + hal_data->acs.cur_ch_clm_ratio, hal_data->acs.cur_ch_nhm_ratio); +} + +void rtw_acs_update_current_info(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + hal_data->acs.cur_ch_clm_ratio = rtw_phydm_clm_ratio(adapter); + hal_data->acs.cur_ch_nhm_ratio = rtw_phydm_nhm_ratio(adapter); + + #ifdef CONFIG_RTW_ACS_DBG + rtw_acs_current_info_dump(RTW_DBGDUMP, adapter); + #endif +} +#endif /*CONFIG_RTW_ACS*/ + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR +void rtw_noise_monitor_version_dump(void *sel, _adapter *adapter) +{ + _RTW_PRINT_SEL(sel, "RTK_NOISE_MONITOR VER_%d\n", RTK_NOISE_MONITOR_VERSION); +} +void rtw_nm_enable(_adapter *adapter) +{ + SET_NM_STATE(adapter, NM_ENABLE); +} +void rtw_nm_disable(_adapter *adapter) +{ + SET_NM_STATE(adapter, NM_DISABLE); +} +void rtw_noise_info_dump(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + u8 max_chan_nums = rfctl->max_chan_nums; + u8 ch_idx, ch_num; + + _RTW_PRINT_SEL(sel, "========== NM (VER-%d) ==========\n", RTK_NOISE_MONITOR_VERSION); + + _RTW_PRINT_SEL(sel, "%5s %3s %3s %10s", "Index", "CH", "BSS", "Noise(dBm)\n"); + + _rtw_bss_nums_count(adapter, hal_data->nm.bss_nums); + + for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) { + ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx); + _RTW_PRINT_SEL(sel, "%5d %3d %3d %10d\n", + ch_idx, ch_num, hal_data->nm.bss_nums[ch_idx], + hal_data->nm.noise[ch_idx]); + } +} + +void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct dm_struct *phydm = &hal_data->odmpriv; + int chan_idx = -1; + s16 noise = 0; + + #ifdef DBG_NOISE_MONITOR + RTW_INFO("[NM] chan(%d)-PauseDIG:%s, IGIValue:0x%02x, max_time:%d (ms)\n", + chan, (is_pause_dig) ? "Y" : "N", igi_value, max_time); + #endif + + chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan); + if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) { + RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan); + return; + } + noise = odm_inband_noise_monitor(phydm, is_pause_dig, igi_value, max_time); /*dBm*/ + + hal_data->nm.noise[chan_idx] = noise; + + #ifdef DBG_NOISE_MONITOR + RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, hal_data->nm.noise[chan_idx]); + + RTW_INFO("[NM] noise_a = %d, noise_b = %d noise_all:%d\n", + phydm->noise_level.noise[RF_PATH_A], + phydm->noise_level.noise[RF_PATH_B], + phydm->noise_level.noise_all); + #endif /*DBG_NOISE_MONITOR*/ +} + +s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + s16 noise = 0; + int chan_idx = -1; + + chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan); + if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) { + RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan); + return noise; + } + noise = hal_data->nm.noise[chan_idx]; + + #ifdef DBG_NOISE_MONITOR + RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, noise); + #endif/*DBG_NOISE_MONITOR*/ + return noise; +} +s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + s16 noise = 0; + + if (ch_idx >= MAX_CHANNEL_NUM) { + RTW_ERR("[NM] %s ch_idx(%d) is invalid\n", __func__, ch_idx); + return noise; + } + noise = hal_data->nm.noise[ch_idx]; + + #ifdef DBG_NOISE_MONITOR + RTW_INFO("[NM] %s ch_idx %d, noise = %d (dBm)\n", __func__, ch_idx, noise); + #endif/*DBG_NOISE_MONITOR*/ + return noise; +} + +s16 rtw_noise_measure_curchan(_adapter *padapter) +{ + s16 noise = 0; + u8 igi_value = 0x1E; + u32 max_time = 100;/* ms */ + u8 is_pause_dig = _TRUE; + u8 cur_chan = rtw_get_oper_ch(padapter); + + if (rtw_linked_check(padapter) == _FALSE) + return noise; + + rtw_ps_deny(padapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(padapter); + rtw_noise_measure(padapter, cur_chan, is_pause_dig, igi_value, max_time); + noise = rtw_noise_query_by_chan_num(padapter, cur_chan); + rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); + + return noise; +} +#endif /*CONFIG_BACKGROUND_NOISE_MONITOR*/ + diff --git a/hal/hal_dm_acs.h b/hal/hal_dm_acs.h new file mode 100644 index 0000000..871c144 --- /dev/null +++ b/hal/hal_dm_acs.h @@ -0,0 +1,167 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __HAL_DM_ACS_H__ +#define __HAL_DM_ACS_H__ +#ifdef CONFIG_RTW_ACS +#define RTK_ACS_VERSION 3 + +#if (RTK_ACS_VERSION == 3) +enum NHM_PID { + NHM_PID_ACS, + NHM_PID_IEEE_11K_HIGH, + NHM_PID_IEEE_11K_LOW, +}; + +#define init_clm_param(clm, app, lv, time) \ + do {\ + clm.clm_app = app;\ + clm.clm_lv = lv;\ + clm.mntr_time = time;\ + } while (0) + +#define init_nhm_param(nhm, txon, cca, cnt_opt, app, lv, time) \ + do {\ + nhm.incld_txon = txon;\ + nhm.incld_cca = cca;\ + nhm.div_opt = cnt_opt;\ + nhm.nhm_app = app;\ + nhm.nhm_lv = lv;\ + nhm.mntr_time = time;\ + } while (0) + + +#define init_acs_clm(clm, time) \ + init_clm_param(clm, CLM_ACS, CLM_LV_2, time) + +#define init_acs_nhm(nhm, time) \ + init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, NHM_ACS, NHM_LV_2, time) + +#define init_11K_high_nhm(nhm, time) \ + init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_HIGH, NHM_LV_2, time) + +#define init_11K_low_nhm(nhm, time) \ + init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_LOW, NHM_LV_2, time) + + +#endif /*(RTK_ACS_VERSION == 3)*/ +void rtw_acs_version_dump(void *sel, _adapter *adapter); +extern void phydm_ccx_monitor_trigger(void *p_dm_void, u16 monitor_time); +extern void phydm_ccx_monitor_result(void *p_dm_void); + +#define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state)) +#define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state)) +#define IS_ACS_ENABLE(padapter) ((GET_ACS_STATE(padapter) == ACS_ENABLE) ? _TRUE : _FALSE) + +enum ACS_STATE { + ACS_DISABLE, + ACS_ENABLE, +}; + +#define ACS_BW_20M BIT(0) +#define ACS_BW_40M BIT(1) +#define ACS_BW_80M BIT(2) +#define ACS_BW_160M BIT(3) + +struct auto_chan_sel { + ATOMIC_T state; + u8 trigger_ch; + bool triggered; + u8 clm_ratio[MAX_CHANNEL_NUM]; + u8 nhm_ratio[MAX_CHANNEL_NUM]; + #if (RTK_ACS_VERSION == 3) + u8 nhm[MAX_CHANNEL_NUM][NHM_RPT_NUM]; + #endif + u8 bss_nums[MAX_CHANNEL_NUM]; + u8 interference_time[MAX_CHANNEL_NUM]; + u8 cur_ch_clm_ratio; + u8 cur_ch_nhm_ratio; + u8 best_chan_5g; + u8 best_chan_24g; + + #if (RTK_ACS_VERSION == 3) + u8 trig_rst; + struct env_trig_rpt trig_rpt; + #endif + + #ifdef CONFIG_RTW_ACS_DBG + RT_SCAN_TYPE scan_type; + u16 scan_time; + u8 igi; + u8 bw; + #endif +}; + +#define rtw_acs_get_best_chan_24g(adapter) (GET_HAL_DATA(adapter)->acs.best_chan_24g) +#define rtw_acs_get_best_chan_5g(adapter) (GET_HAL_DATA(adapter)->acs.best_chan_5g) + +#ifdef CONFIG_RTW_ACS_DBG +#define rtw_is_acs_passiv_scan(adapter) (((GET_HAL_DATA(adapter)->acs.scan_type) == SCAN_PASSIVE) ? _TRUE : _FALSE) + +#define rtw_acs_get_adv_st(adapter) (GET_HAL_DATA(adapter)->acs.scan_time) +#define rtw_is_acs_st_valid(adapter) ((GET_HAL_DATA(adapter)->acs.scan_time) ? _TRUE : _FALSE) + +#define rtw_acs_get_adv_igi(adapter) (GET_HAL_DATA(adapter)->acs.igi) +u8 rtw_is_acs_igi_valid(_adapter *adapter); + +#define rtw_acs_get_adv_bw(adapter) (GET_HAL_DATA(adapter)->acs.bw) + +void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw); +void rtw_acs_adv_reset(_adapter *adapter); +#endif + +u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan); +u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx); +u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan); +u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx); + +void rtw_acs_reset(_adapter *adapter); +void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid); +void rtw_acs_get_rst(_adapter *adapter); +void rtw_acs_select_best_chan(_adapter *adapter); +void rtw_acs_info_dump(void *sel, _adapter *adapter); +void rtw_acs_update_current_info(_adapter *adapter); +void rtw_acs_chan_info_dump(void *sel, _adapter *adapter); +void rtw_acs_current_info_dump(void *sel, _adapter *adapter); + +void rtw_acs_start(_adapter *adapter); +void rtw_acs_stop(_adapter *adapter); + +#endif /*CONFIG_RTW_ACS*/ + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR +#define RTK_NOISE_MONITOR_VERSION 3 +#define GET_NM_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->nm.state)) +#define SET_NM_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->nm.state, set_state)) +#define IS_NM_ENABLE(padapter) ((GET_NM_STATE(padapter) == NM_ENABLE) ? _TRUE : _FALSE) + +enum NM_STATE { + NM_DISABLE, + NM_ENABLE, +}; + +struct noise_monitor { + ATOMIC_T state; + s16 noise[MAX_CHANNEL_NUM]; + u8 bss_nums[MAX_CHANNEL_NUM]; +}; +void rtw_nm_enable(_adapter *adapter); +void rtw_nm_disable(_adapter *adapter); +void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time); +s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan); +s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx); +s16 rtw_noise_measure_curchan(_adapter *padapter); +void rtw_noise_info_dump(void *sel, _adapter *adapter); +#endif +#endif /* __HAL_DM_ACS_H__ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.c new file mode 100644 index 0000000..fd7ea86 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.c @@ -0,0 +1,168 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_cfg_wmac_8822b.h" +#include "halmac_8822b_cfg.h" + +#if HALMAC_8822B_SUPPORT + +/** + * cfg_drv_info_8822b() - config driver info + * @adapter : the adapter of halmac + * @drv_info : driver information selection + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_drv_info_8822b(struct halmac_adapter *adapter, + enum halmac_drv_info drv_info) +{ + u8 drv_info_size = 0; + u8 phy_status_en = 0; + u8 sniffer_en = 0; + u8 plcp_hdr_en = 0; + u8 value8; + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + struct halmac_mac_rx_ignore_cfg cfg; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]drv info = %d\n", drv_info); + + switch (drv_info) { + case HALMAC_DRV_INFO_NONE: + drv_info_size = 0; + phy_status_en = 0; + sniffer_en = 0; + plcp_hdr_en = 0; + cfg.hdr_chk_en = _FALSE; + break; + case HALMAC_DRV_INFO_PHY_STATUS: + drv_info_size = 4; + phy_status_en = 1; + sniffer_en = 0; + plcp_hdr_en = 0; + cfg.hdr_chk_en = _FALSE; + break; + case HALMAC_DRV_INFO_PHY_SNIFFER: + drv_info_size = 5; /* phy status 4byte, sniffer info 1byte */ + phy_status_en = 1; + sniffer_en = 1; + plcp_hdr_en = 0; + cfg.hdr_chk_en = _FALSE; + break; + case HALMAC_DRV_INFO_PHY_PLCP: + drv_info_size = 6; /* phy status 4byte, plcp header 2byte */ + phy_status_en = 1; + sniffer_en = 0; + plcp_hdr_en = 1; + cfg.hdr_chk_en = _FALSE; + break; + default: + return HALMAC_RET_SW_CASE_NOT_SUPPORT; + } + + if (adapter->txff_alloc.rx_fifo_exp_mode != + HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) + drv_info_size = RX_DESC_DUMMY_SIZE_8822B >> 3; + + api->halmac_set_hw_value(adapter, HALMAC_HW_RX_IGNORE, &cfg); + + HALMAC_REG_W8(REG_RX_DRVINFO_SZ, drv_info_size); + + value8 = HALMAC_REG_R8(REG_TRXFF_BNDY + 1); + value8 &= 0xF0; + /* For rxdesc len = 0 issue */ + value8 |= 0xF; + HALMAC_REG_W8(REG_TRXFF_BNDY + 1, value8); + + adapter->drv_info_size = drv_info_size; + + value32 = HALMAC_REG_R32(REG_RCR); + value32 = (value32 & (~BIT_APP_PHYSTS)); + if (phy_status_en == 1) + value32 = value32 | BIT_APP_PHYSTS; + HALMAC_REG_W32(REG_RCR, value32); + + value32 = HALMAC_REG_R32(REG_WMAC_OPTION_FUNCTION + 4); + value32 = (value32 & (~(BIT(8) | BIT(9)))); + if (sniffer_en == 1) + value32 = value32 | BIT(9); + if (plcp_hdr_en == 1) + value32 = value32 | BIT(8); + HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 4, value32); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * init_low_pwr_8822b() - config WMAC register + * @adapter + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_low_pwr_8822b(struct halmac_adapter *adapter) +{ + return HALMAC_RET_SUCCESS; +} + +void +cfg_rx_ignore_8822b(struct halmac_adapter *adapter, + struct halmac_mac_rx_ignore_cfg *cfg) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + value8 = HALMAC_REG_R8(REG_BBPSF_CTRL); + + /*mac header check enable*/ + if (cfg->hdr_chk_en == _TRUE) + value8 |= BIT_BBPSF_MHCHKEN | BIT_BBPSF_MPDUCHKEN; + else + value8 &= ~(BIT_BBPSF_MHCHKEN) & (~(BIT_BBPSF_MPDUCHKEN)); + + HALMAC_REG_W8(REG_BBPSF_CTRL, value8); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); +} + +enum halmac_ret_status +cfg_ampdu_8822b(struct halmac_adapter *adapter, + struct halmac_ampdu_config *cfg) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (cfg->ht_max_len != cfg->vht_max_len) { + PLTFM_MSG_ERR("[ERR]max len ht != vht!!\n"); + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + HALMAC_REG_W8(REG_PROT_MODE_CTRL + 2, cfg->max_agg_num); + HALMAC_REG_W8(REG_PROT_MODE_CTRL + 3, cfg->max_agg_num); + + if (cfg->max_len_en == 1) + HALMAC_REG_W32(REG_AMPDU_MAX_LENGTH, cfg->ht_max_len); + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_8822B_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.h new file mode 100644 index 0000000..d383cf3 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.h @@ -0,0 +1,40 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_CFG_WMAC_8822B_H_ +#define _HALMAC_CFG_WMAC_8822B_H_ + +#include "../../halmac_api.h" + +#if HALMAC_8822B_SUPPORT + +enum halmac_ret_status +cfg_drv_info_8822b(struct halmac_adapter *adapter, + enum halmac_drv_info drv_info); + +enum halmac_ret_status +init_low_pwr_8822b(struct halmac_adapter *adapter); + +void +cfg_rx_ignore_8822b(struct halmac_adapter *adapter, + struct halmac_mac_rx_ignore_cfg *cfg); + +enum halmac_ret_status +cfg_ampdu_8822b(struct halmac_adapter *adapter, + struct halmac_ampdu_config *cfg); + +#endif/* HALMAC_8822B_SUPPORT */ + +#endif/* _HALMAC_CFG_WMAC_8822B_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.c new file mode 100644 index 0000000..7925aab --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.c @@ -0,0 +1,168 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_8822b_cfg.h" +#include "halmac_common_8822b.h" +#include "../halmac_common_88xx.h" +#include "halmac_cfg_wmac_8822b.h" + +#if HALMAC_8822B_SUPPORT + +static void +cfg_ldo25_8822b(struct halmac_adapter *adapter, u8 enable); + +/** + * get_hw_value_8822b() -get hw config value + * @adapter : the adapter of halmac + * @hw_id : hw id for driver to query + * @pvalue : hw value, reference table to get data type + * Author : KaiYuan Chang / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_hw_value_8822b(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!value) { + PLTFM_MSG_ERR("[ERR]%s (NULL ==pvalue)\n", __func__); + return HALMAC_RET_NULL_POINTER; + } + + if (get_hw_value_88xx(adapter, hw_id, value) == HALMAC_RET_SUCCESS) + return HALMAC_RET_SUCCESS; + + switch (hw_id) { + case HALMAC_HW_FW_MAX_SIZE: + *(u32 *)value = WLAN_FW_MAX_SIZE_8822B; + break; + default: + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * set_hw_value_8822b() -set hw config value + * @adapter : the adapter of halmac + * @hw_id : hw id for driver to config + * @pvalue : hw value, reference table to get data type + * Author : KaiYuan Chang / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +set_hw_value_8822b(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!value) { + PLTFM_MSG_ERR("[ERR]null pointer\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (set_hw_value_88xx(adapter, hw_id, value) == HALMAC_RET_SUCCESS) + return HALMAC_RET_SUCCESS; + + switch (hw_id) { + case HALMAC_HW_AMPDU_CONFIG: + status = cfg_ampdu_8822b(adapter, + (struct halmac_ampdu_config *)value); + break; + case HALMAC_HW_SDIO_TX_FORMAT: + break; + case HALMAC_HW_RXGCK_FIFO: + break; + case HALMAC_HW_RX_IGNORE: + cfg_rx_ignore_8822b(adapter, + (struct halmac_mac_rx_ignore_cfg *)value); + break; + case HALMAC_HW_LDO25_EN: + cfg_ldo25_8822b(adapter, *(u8 *)value); + break; + case HALMAC_HW_PCIE_REF_AUTOK: + break; + default: + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return status; +} + +/** + * halmac_fill_txdesc_check_sum_88xx() - fill in tx desc check sum + * @adapter : the adapter of halmac + * @txdesc : tx desc packet + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +fill_txdesc_check_sum_8822b(struct halmac_adapter *adapter, u8 *txdesc) +{ + u16 chksum = 0; + u16 *data = (u16 *)NULL; + u32 i; + + if (!txdesc) { + PLTFM_MSG_ERR("[ERR]null pointer"); + return HALMAC_RET_NULL_POINTER; + } + + if (adapter->tx_desc_checksum != _TRUE) + PLTFM_MSG_TRACE("[TRACE]chksum disable"); + + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000); + + data = (u16 *)(txdesc); + + /* HW clculates only 32byte */ + for (i = 0; i < 8; i++) + chksum ^= (*(data + 2 * i) ^ *(data + (2 * i + 1))); + + /* *(data + 2 * i) & *(data + (2 * i + 1) have endain issue*/ + /* Process eniadn issue after checksum calculation */ + chksum = rtk_le16_to_cpu(chksum); + + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, chksum); + + return HALMAC_RET_SUCCESS; +} + +static void +cfg_ldo25_8822b(struct halmac_adapter *adapter, u8 enable) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + value8 = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 3); + + if (enable == _TRUE) + HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 | BIT(7))); + else + HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 & ~BIT(7))); +} + +#endif /* HALMAC_8822B_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.h new file mode 100644 index 0000000..952f929 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.h @@ -0,0 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_COMMON_8822B_H_ +#define _HALMAC_COMMON_8822B_H_ + +#include "../../halmac_api.h" + +#if HALMAC_8822B_SUPPORT + +enum halmac_ret_status +get_hw_value_8822b(struct halmac_adapter *adapter, + enum halmac_hw_id hw_id, void *value); + +enum halmac_ret_status +set_hw_value_8822b(struct halmac_adapter *adapter, + enum halmac_hw_id hw_id, void *value); + +enum halmac_ret_status +fill_txdesc_check_sum_8822b(struct halmac_adapter *adapter, u8 *txdesc); + +#endif/* HALMAC_8822B_SUPPORT */ + +#endif/* _HALMAC_COMMON_8822B_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.c new file mode 100644 index 0000000..6ead4b5 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.c @@ -0,0 +1,724 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_init_8822b.h" +#include "halmac_8822b_cfg.h" +#include "halmac_pcie_8822b.h" +#include "halmac_sdio_8822b.h" +#include "halmac_usb_8822b.h" +#include "halmac_gpio_8822b.h" +#include "halmac_common_8822b.h" +#include "halmac_cfg_wmac_8822b.h" +#include "../halmac_common_88xx.h" +#include "../halmac_init_88xx.h" + +#if HALMAC_8822B_SUPPORT + +#define RSVD_PG_DRV_NUM 16 +#define RSVD_PG_H2C_EXTRAINFO_NUM 24 +#define RSVD_PG_H2C_STATICINFO_NUM 8 +#define RSVD_PG_H2CQ_NUM 8 +#define RSVD_PG_CPU_INSTRUCTION_NUM 0 +#define RSVD_PG_FW_TXBUF_NUM 4 +#define RSVD_PG_CSIBUF_NUM 0 +#define RSVD_PG_DLLB_NUM 32 + +#define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \ + BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \ + BIT_MACTXEN | BIT_MACRXEN) + +#define BLK_DESC_NUM 0x3 + +#define WLAN_AMPDU_MAX_TIME 0x70 +#define WLAN_RTS_LEN_TH 0xFF +#define WLAN_RTS_TX_TIME_TH 0x08 +#define WLAN_MAX_AGG_PKT_LIMIT 0x20 +#define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20 +#define WALN_FAST_EDCA_VO_TH 0x06 +#define WLAN_FAST_EDCA_VI_TH 0x06 +#define WLAN_FAST_EDCA_BE_TH 0x06 +#define WLAN_FAST_EDCA_BK_TH 0x06 +#define WLAN_BAR_RETRY_LIMIT 0x01 +#define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 + +#if HALMAC_PLATFORM_WINDOWS +/*SDIO RQPN Mapping for Windows, extra queue is not implemented in Driver code*/ +struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, + HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, +}; +#else +/*SDIO RQPN Mapping*/ +struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, + HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, +}; +#endif + +/*PCIE RQPN Mapping*/ +struct halmac_rqpn HALMAC_RQPN_PCIE_8822B[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, + HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, +}; + +/*USB 2 Bulkout RQPN Mapping*/ +struct halmac_rqpn HALMAC_RQPN_2BULKOUT_8822B[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, +}; + +/*USB 3 Bulkout RQPN Mapping*/ +struct halmac_rqpn HALMAC_RQPN_3BULKOUT_8822B[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, + HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, +}; + +/*USB 4 Bulkout RQPN Mapping*/ +struct halmac_rqpn HALMAC_RQPN_4BULKOUT_8822B[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, + HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, +}; + +#if HALMAC_PLATFORM_WINDOWS +/*SDIO Page Number*/ +struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 0, 1}, + {HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 640}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 640}, +}; +#else +/*SDIO Page Number*/ +struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 32, 1}, + {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640}, +}; +#endif + +/*PCIE Page Number*/ +struct halmac_pg_num HALMAC_PG_NUM_PCIE_8822B[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640}, +}; + +/*USB 2 Bulkout Page Number*/ +struct halmac_pg_num HALMAC_PG_NUM_2BULKOUT_8822B[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 64, 64, 0, 0, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 0, 0, 1}, + {HALMAC_TRX_MODE_WMM, 64, 64, 0, 0, 1}, + {HALMAC_TRX_MODE_P2P, 64, 64, 0, 0, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1024}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1024}, +}; + +/*USB 3 Bulkout Page Number*/ +struct halmac_pg_num HALMAC_PG_NUM_3BULKOUT_8822B[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1024}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1024}, +}; + +/*USB 4 Bulkout Page Number*/ +struct halmac_pg_num HALMAC_PG_NUM_4BULKOUT_8822B[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640}, +}; + +static enum halmac_ret_status +txdma_queue_mapping_8822b(struct halmac_adapter *adapter, + enum halmac_trx_mode mode); + +static enum halmac_ret_status +priority_queue_cfg_8822b(struct halmac_adapter *adapter, + enum halmac_trx_mode mode); + +static enum halmac_ret_status +set_trx_fifo_info_8822b(struct halmac_adapter *adapter, + enum halmac_trx_mode mode); +enum halmac_ret_status +mount_api_8822b(struct halmac_adapter *adapter) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + adapter->chip_id = HALMAC_CHIP_ID_8822B; + adapter->hw_cfg_info.efuse_size = EFUSE_SIZE_8822B; + adapter->hw_cfg_info.eeprom_size = EEPROM_SIZE_8822B; + adapter->hw_cfg_info.bt_efuse_size = BT_EFUSE_SIZE_8822B; + adapter->hw_cfg_info.cam_entry_num = SEC_CAM_NUM_8822B; + adapter->hw_cfg_info.tx_fifo_size = TX_FIFO_SIZE_8822B; + adapter->hw_cfg_info.rx_fifo_size = RX_FIFO_SIZE_8822B; + adapter->hw_cfg_info.ac_oqt_size = OQT_ENTRY_AC_8822B; + adapter->hw_cfg_info.non_ac_oqt_size = OQT_ENTRY_NOAC_8822B; + adapter->hw_cfg_info.usb_txagg_num = BLK_DESC_NUM; + adapter->txff_alloc.rsvd_drv_pg_num = RSVD_PG_DRV_NUM; + + api->halmac_init_trx_cfg = init_trx_cfg_8822b; + api->halmac_init_protocol_cfg = init_protocol_cfg_8822b; + api->halmac_init_h2c = init_h2c_8822b; + api->halmac_pinmux_get_func = pinmux_get_func_8822b; + api->halmac_pinmux_set_func = pinmux_set_func_8822b; + api->halmac_pinmux_free_func = pinmux_free_func_8822b; + api->halmac_get_hw_value = get_hw_value_8822b; + api->halmac_set_hw_value = set_hw_value_8822b; + api->halmac_cfg_drv_info = cfg_drv_info_8822b; + api->halmac_fill_txdesc_checksum = fill_txdesc_check_sum_8822b; + api->halmac_init_low_pwr = init_low_pwr_8822b; + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + api->halmac_mac_power_switch = mac_pwr_switch_sdio_8822b; + api->halmac_phy_cfg = phy_cfg_sdio_8822b; + api->halmac_pcie_switch = pcie_switch_sdio_8822b; + api->halmac_interface_integration_tuning = intf_tun_sdio_8822b; + api->halmac_tx_allowed_sdio = tx_allowed_sdio_8822b; + api->halmac_get_sdio_tx_addr = get_sdio_tx_addr_8822b; + api->halmac_reg_read_8 = reg_r8_sdio_8822b; + api->halmac_reg_write_8 = reg_w8_sdio_8822b; + api->halmac_reg_read_16 = reg_r16_sdio_8822b; + api->halmac_reg_write_16 = reg_w16_sdio_8822b; + api->halmac_reg_read_32 = reg_r32_sdio_8822b; + api->halmac_reg_write_32 = reg_w32_sdio_8822b; + + adapter->sdio_fs.macid_map_size = MACID_MAX_8822B * 2; + if (!adapter->sdio_fs.macid_map) { + adapter->sdio_fs.macid_map = + (u8 *)PLTFM_MALLOC(adapter->sdio_fs.macid_map_size); + if (!adapter->sdio_fs.macid_map) + PLTFM_MSG_ERR("[ERR]allocate macid_map!!\n"); + } + } else if (adapter->intf == HALMAC_INTERFACE_USB) { + api->halmac_mac_power_switch = mac_pwr_switch_usb_8822b; + api->halmac_phy_cfg = phy_cfg_usb_8822b; + api->halmac_pcie_switch = pcie_switch_usb_8822b; + api->halmac_interface_integration_tuning = intf_tun_usb_8822b; + } else if (adapter->intf == HALMAC_INTERFACE_PCIE) { + api->halmac_mac_power_switch = mac_pwr_switch_pcie_8822b; + api->halmac_phy_cfg = phy_cfg_pcie_8822b; + api->halmac_pcie_switch = pcie_switch_8822b; + api->halmac_interface_integration_tuning = intf_tun_pcie_8822b; + } else { + PLTFM_MSG_ERR("[ERR]Undefined IC\n"); + return HALMAC_RET_CHIP_NOT_SUPPORT; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * init_trx_cfg_8822b() - config trx dma register + * @adapter : the adapter of halmac + * @mode : trx mode selection + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_trx_cfg_8822b(struct halmac_adapter *adapter, enum halmac_trx_mode mode) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + adapter->trx_mode = mode; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = txdma_queue_mapping_8822b(adapter, mode); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]queue mapping\n"); + return status; + } + + value8 = 0; + HALMAC_REG_W8(REG_CR, value8); + value8 = MAC_TRX_ENABLE; + HALMAC_REG_W8(REG_CR, value8); + HALMAC_REG_W32(REG_H2CQ_CSR, BIT(31)); + + status = priority_queue_cfg_8822b(adapter, mode); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]halmac_txdma_queue_mapping fail!\n"); + return status; + } + + if (adapter->txff_alloc.rx_fifo_exp_mode != + HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) + HALMAC_REG_W8(REG_RX_DRVINFO_SZ, RX_DESC_DUMMY_SIZE_8822B >> 3); + + status = init_h2c_8822b(adapter); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]init h2cq!\n"); + return status; + } + + if (adapter->intf == HALMAC_INTERFACE_USB) + HALMAC_REG_W8_SET(REG_TXDMA_PQ_MAP, BIT(0)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +txdma_queue_mapping_8822b(struct halmac_adapter *adapter, + enum halmac_trx_mode mode) +{ + u16 value16; + struct halmac_rqpn *cur_rqpn_sel = NULL; + enum halmac_ret_status status; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + cur_rqpn_sel = HALMAC_RQPN_SDIO_8822B; + } else if (adapter->intf == HALMAC_INTERFACE_PCIE) { + cur_rqpn_sel = HALMAC_RQPN_PCIE_8822B; + } else if (adapter->intf == HALMAC_INTERFACE_USB) { + if (adapter->bulkout_num == 2) { + cur_rqpn_sel = HALMAC_RQPN_2BULKOUT_8822B; + } else if (adapter->bulkout_num == 3) { + cur_rqpn_sel = HALMAC_RQPN_3BULKOUT_8822B; + } else if (adapter->bulkout_num == 4) { + cur_rqpn_sel = HALMAC_RQPN_4BULKOUT_8822B; + } else { + PLTFM_MSG_ERR("[ERR]invalid intf\n"); + return HALMAC_RET_NOT_SUPPORT; + } + } else { + return HALMAC_RET_NOT_SUPPORT; + } + + status = rqpn_parser_88xx(adapter, mode, cur_rqpn_sel); + if (status != HALMAC_RET_SUCCESS) + return status; + + value16 = 0; + value16 |= BIT_TXDMA_HIQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_HI]); + value16 |= BIT_TXDMA_MGQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_MG]); + value16 |= BIT_TXDMA_BKQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_BK]); + value16 |= BIT_TXDMA_BEQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_BE]); + value16 |= BIT_TXDMA_VIQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_VI]); + value16 |= BIT_TXDMA_VOQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_VO]); + HALMAC_REG_W16(REG_TXDMA_PQ_MAP, value16); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +priority_queue_cfg_8822b(struct halmac_adapter *adapter, + enum halmac_trx_mode mode) +{ + u8 transfer_mode = 0; + u8 value8; + u32 cnt; + struct halmac_txff_allocation *txff_info = &adapter->txff_alloc; + enum halmac_ret_status status; + struct halmac_pg_num *cur_pg_num = NULL; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + status = set_trx_fifo_info_8822b(adapter, mode); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]set trx fifo!!\n"); + return status; + } + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + cur_pg_num = HALMAC_PG_NUM_SDIO_8822B; + } else if (adapter->intf == HALMAC_INTERFACE_PCIE) { + cur_pg_num = HALMAC_PG_NUM_PCIE_8822B; + } else if (adapter->intf == HALMAC_INTERFACE_USB) { + if (adapter->bulkout_num == 2) { + cur_pg_num = HALMAC_PG_NUM_2BULKOUT_8822B; + } else if (adapter->bulkout_num == 3) { + cur_pg_num = HALMAC_PG_NUM_3BULKOUT_8822B; + } else if (adapter->bulkout_num == 4) { + cur_pg_num = HALMAC_PG_NUM_4BULKOUT_8822B; + } else { + PLTFM_MSG_ERR("[ERR]interface not support\n"); + return HALMAC_RET_NOT_SUPPORT; + } + } else { + return HALMAC_RET_NOT_SUPPORT; + } + + status = pg_num_parser_88xx(adapter, mode, cur_pg_num); + if (status != HALMAC_RET_SUCCESS) + return status; + + HALMAC_REG_W16(REG_FIFOPAGE_INFO_1, txff_info->high_queue_pg_num); + HALMAC_REG_W16(REG_FIFOPAGE_INFO_2, txff_info->low_queue_pg_num); + HALMAC_REG_W16(REG_FIFOPAGE_INFO_3, txff_info->normal_queue_pg_num); + HALMAC_REG_W16(REG_FIFOPAGE_INFO_4, txff_info->extra_queue_pg_num); + HALMAC_REG_W16(REG_FIFOPAGE_INFO_5, txff_info->pub_queue_pg_num); + HALMAC_REG_W32_SET(REG_RQPN_CTRL_2, BIT(31)); + + adapter->sdio_fs.hiq_pg_num = txff_info->high_queue_pg_num; + adapter->sdio_fs.miq_pg_num = txff_info->normal_queue_pg_num; + adapter->sdio_fs.lowq_pg_num = txff_info->low_queue_pg_num; + adapter->sdio_fs.pubq_pg_num = txff_info->pub_queue_pg_num; + adapter->sdio_fs.exq_pg_num = txff_info->extra_queue_pg_num; + + HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, txff_info->rsvd_boundary); + HALMAC_REG_W8_SET(REG_FWHW_TXQ_CTRL + 2, BIT(4)); + + /*20170411 Soar*/ + /* SDIO sometimes use two CMD52 to do HALMAC_REG_W16 */ + /* and may cause a mismatch between HW status and Reg value. */ + /* A patch is to write high byte first, suggested by Argis */ + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + value8 = (u8)(txff_info->rsvd_boundary >> 8 & 0xFF); + HALMAC_REG_W8(REG_BCNQ_BDNY_V1 + 1, value8); + value8 = (u8)(txff_info->rsvd_boundary & 0xFF); + HALMAC_REG_W8(REG_BCNQ_BDNY_V1, value8); + } else { + HALMAC_REG_W16(REG_BCNQ_BDNY_V1, txff_info->rsvd_boundary); + } + + HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2 + 2, txff_info->rsvd_boundary); + + /*20170411 Soar*/ + /* SDIO sometimes use two CMD52 to do HALMAC_REG_W16 */ + /* and may cause a mismatch between HW status and Reg value. */ + /* A patch is to write high byte first, suggested by Argis */ + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + value8 = (u8)(txff_info->rsvd_boundary >> 8 & 0xFF); + HALMAC_REG_W8(REG_BCNQ1_BDNY_V1 + 1, value8); + value8 = (u8)(txff_info->rsvd_boundary & 0xFF); + HALMAC_REG_W8(REG_BCNQ1_BDNY_V1, value8); + } else { + HALMAC_REG_W16(REG_BCNQ1_BDNY_V1, txff_info->rsvd_boundary); + } + + HALMAC_REG_W32(REG_RXFF_BNDY, + adapter->hw_cfg_info.rx_fifo_size - + C2H_PKT_BUF_88XX - 1); + + if (adapter->intf == HALMAC_INTERFACE_USB) { + value8 = HALMAC_REG_R8(REG_AUTO_LLT_V1); + value8 &= ~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM); + value8 |= (BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM); + HALMAC_REG_W8(REG_AUTO_LLT_V1, value8); + + HALMAC_REG_W8(REG_AUTO_LLT_V1 + 3, BLK_DESC_NUM); + HALMAC_REG_W8_SET(REG_TXDMA_OFFSET_CHK + 1, BIT(1)); + } + + HALMAC_REG_W8_SET(REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1); + cnt = 1000; + while (HALMAC_REG_R8(REG_AUTO_LLT_V1) & BIT_AUTO_INIT_LLT_V1) { + cnt--; + if (cnt == 0) + return HALMAC_RET_INIT_LLT_FAIL; + } + + if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) { + transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY; + HALMAC_REG_W16(REG_WMAC_LBK_BUF_HD_V1, + adapter->txff_alloc.rsvd_boundary); + } else if (mode == HALMAC_TRX_MODE_LOOPBACK) { + transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT; + } else { + transfer_mode = HALMAC_TRNSFER_NORMAL; + } + + adapter->hw_cfg_info.trx_mode = transfer_mode; + HALMAC_REG_W8(REG_CR + 3, transfer_mode); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +set_trx_fifo_info_8822b(struct halmac_adapter *adapter, + enum halmac_trx_mode mode) +{ + u16 cur_pg_addr; + u32 txff_size = TX_FIFO_SIZE_8822B; + u32 rxff_size = RX_FIFO_SIZE_8822B; + struct halmac_txff_allocation *info = &adapter->txff_alloc; + + if (info->rx_fifo_exp_mode == HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK) { + txff_size = TX_FIFO_SIZE_RX_EXPAND_1BLK_8822B; + rxff_size = RX_FIFO_SIZE_RX_EXPAND_1BLK_8822B; + } + + if (info->la_mode != HALMAC_LA_MODE_DISABLE) { + txff_size = TX_FIFO_SIZE_LA_8822B; + rxff_size = RX_FIFO_SIZE_8822B; + } + + adapter->hw_cfg_info.tx_fifo_size = txff_size; + adapter->hw_cfg_info.rx_fifo_size = rxff_size; + info->tx_fifo_pg_num = (u16)(txff_size >> TX_PAGE_SIZE_SHIFT_88XX); + + info->rsvd_pg_num = info->rsvd_drv_pg_num + + RSVD_PG_H2C_EXTRAINFO_NUM + + RSVD_PG_H2C_STATICINFO_NUM + + RSVD_PG_H2CQ_NUM + + RSVD_PG_CPU_INSTRUCTION_NUM + + RSVD_PG_FW_TXBUF_NUM + + RSVD_PG_CSIBUF_NUM; + + if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) + info->rsvd_pg_num += RSVD_PG_DLLB_NUM; + + if (info->rsvd_pg_num > info->tx_fifo_pg_num) + return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL; + + info->acq_pg_num = info->tx_fifo_pg_num - info->rsvd_pg_num; + info->rsvd_boundary = info->tx_fifo_pg_num - info->rsvd_pg_num; + + cur_pg_addr = info->tx_fifo_pg_num; + cur_pg_addr -= RSVD_PG_CSIBUF_NUM; + info->rsvd_csibuf_addr = cur_pg_addr; + cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM; + info->rsvd_fw_txbuf_addr = cur_pg_addr; + cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM; + info->rsvd_cpu_instr_addr = cur_pg_addr; + cur_pg_addr -= RSVD_PG_H2CQ_NUM; + info->rsvd_h2cq_addr = cur_pg_addr; + cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM; + info->rsvd_h2c_sta_info_addr = cur_pg_addr; + cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM; + info->rsvd_h2c_info_addr = cur_pg_addr; + cur_pg_addr -= info->rsvd_drv_pg_num; + info->rsvd_drv_addr = cur_pg_addr; + + if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) + info->rsvd_drv_addr -= RSVD_PG_DLLB_NUM; + + if (info->rsvd_boundary != info->rsvd_drv_addr) + return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL; + + return HALMAC_RET_SUCCESS; +} + +/** + * init_protocol_cfg_8822b() - config protocol register + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_protocol_cfg_8822b(struct halmac_adapter *adapter) +{ + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + HALMAC_REG_W8_CLR(REG_SW_AMPDU_BURST_MODE_CTRL, BIT(6)); + + HALMAC_REG_W8(REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); + HALMAC_REG_W8(REG_TX_HANG_CTRL, BIT_EN_EOF_V1); + + value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | + (WLAN_MAX_AGG_PKT_LIMIT << 16) | + (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); + HALMAC_REG_W32(REG_PROT_MODE_CTRL, value32); + + HALMAC_REG_W16(REG_BAR_MODE_CTRL + 2, + WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); + + HALMAC_REG_W8(REG_FAST_EDCA_VOVI_SETTING, WALN_FAST_EDCA_VO_TH); + HALMAC_REG_W8(REG_FAST_EDCA_VOVI_SETTING + 2, WLAN_FAST_EDCA_VI_TH); + HALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING, WLAN_FAST_EDCA_BE_TH); + HALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING + 2, WLAN_FAST_EDCA_BK_TH); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * init_h2c_8822b() - config h2c packet buffer + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_h2c_8822b(struct halmac_adapter *adapter) +{ + u8 value8; + u32 value32; + u32 h2cq_addr; + u32 h2cq_size; + struct halmac_txff_allocation *txff_info = &adapter->txff_alloc; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + h2cq_addr = txff_info->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT_88XX; + h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT_88XX; + + value32 = HALMAC_REG_R32(REG_H2C_HEAD); + value32 = (value32 & 0xFFFC0000) | h2cq_addr; + HALMAC_REG_W32(REG_H2C_HEAD, value32); + + value32 = HALMAC_REG_R32(REG_H2C_READ_ADDR); + value32 = (value32 & 0xFFFC0000) | h2cq_addr; + HALMAC_REG_W32(REG_H2C_READ_ADDR, value32); + + value32 = HALMAC_REG_R32(REG_H2C_TAIL); + value32 &= 0xFFFC0000; + value32 |= (h2cq_addr + h2cq_size); + HALMAC_REG_W32(REG_H2C_TAIL, value32); + + value8 = HALMAC_REG_R8(REG_H2C_INFO); + value8 = (u8)((value8 & 0xFC) | 0x01); + HALMAC_REG_W8(REG_H2C_INFO, value8); + + value8 = HALMAC_REG_R8(REG_H2C_INFO); + value8 = (u8)((value8 & 0xFB) | 0x04); + HALMAC_REG_W8(REG_H2C_INFO, value8); + + value8 = HALMAC_REG_R8(REG_TXDMA_OFFSET_CHK + 1); + value8 = (u8)((value8 & 0x7f) | 0x80); + HALMAC_REG_W8(REG_TXDMA_OFFSET_CHK + 1, value8); + + adapter->h2c_info.buf_size = h2cq_size; + get_h2c_buf_free_space_88xx(adapter); + + if (adapter->h2c_info.buf_size != adapter->h2c_info.buf_fs) { + PLTFM_MSG_ERR("[ERR]get h2c free space error!\n"); + return HALMAC_RET_GET_H2C_SPACE_ERR; + } + + PLTFM_MSG_TRACE("[TRACE]h2c fs : %d\n", adapter->h2c_info.buf_fs); + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_8822B_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.h new file mode 100644 index 0000000..6c26128 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.h @@ -0,0 +1,37 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_INIT_8822B_H_ +#define _HALMAC_INIT_8822B_H_ + +#include "../../halmac_api.h" + +#if HALMAC_8822B_SUPPORT + +enum halmac_ret_status +mount_api_8822b(struct halmac_adapter *adapter); + +enum halmac_ret_status +init_trx_cfg_8822b(struct halmac_adapter *adapter, enum halmac_trx_mode mode); + +enum halmac_ret_status +init_protocol_cfg_8822b(struct halmac_adapter *adapter); + +enum halmac_ret_status +init_h2c_8822b(struct halmac_adapter *adapter); + +#endif /* HALMAC_8822B_SUPPORT */ + +#endif/* _HALMAC_INIT_8822B_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.c new file mode 100644 index 0000000..deb44ff --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.c @@ -0,0 +1,214 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_pcie_8822b.h" +#include "halmac_pwr_seq_8822b.h" +#include "../halmac_init_88xx.h" +#include "../halmac_common_88xx.h" +#include "../halmac_pcie_88xx.h" +#include "../halmac_88xx_cfg.h" + +#if HALMAC_8822B_SUPPORT + +/** + * mac_pwr_switch_pcie_8822b() - switch mac power + * @adapter : the adapter of halmac + * @pwr : power state + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mac_pwr_switch_pcie_8822b(struct halmac_adapter *adapter, + enum halmac_mac_power pwr) +{ + u8 value8; + u8 rpwm; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]pwr = %x\n", pwr); + PLTFM_MSG_TRACE("[TRACE]8822B pwr seq ver = %s\n", + HALMAC_8822B_PWR_SEQ_VER); + + adapter->rpwm = HALMAC_REG_R8(REG_PCIE_HRPWM1_V1); + + /* Check FW still exist or not */ + if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) { + /* Leave 32K */ + rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80); + HALMAC_REG_W8(REG_PCIE_HRPWM1_V1, rpwm); + } + + value8 = HALMAC_REG_R8(REG_CR); + if (value8 == 0xEA) + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF; + else + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON; + + /* Check if power switch is needed */ + if (pwr == HALMAC_MAC_POWER_ON && + adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) { + PLTFM_MSG_WARN("[WARN]power state unchange!!\n"); + return HALMAC_RET_PWR_UNCHANGE; + } + + if (pwr == HALMAC_MAC_POWER_OFF) { + status = trxdma_check_idle_88xx(adapter); + if (status != HALMAC_RET_SUCCESS) + return status; + if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) != + HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n"); + return HALMAC_RET_POWER_OFF_FAIL; + } + + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF; + adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + init_adapter_dynamic_param_88xx(adapter); + } else { + if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) != + HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n"); + return HALMAC_RET_POWER_ON_FAIL; + } + + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pcie_switch_8822b() - pcie gen1/gen2 switch + * @adapter : the adapter of halmac + * @cfg : gen1/gen2 selection + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pcie_switch_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg) +{ + u8 value8; + u32 value32; + u8 speed = 0; + u32 cnt = 0; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (cfg == HALMAC_PCIE_GEN1) { + value8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0; + dbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET, value8 | BIT(0)); + + value32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET); + dbi_w32_88xx(adapter, GEN2_CTRL_OFFSET, value32 | BIT(17)); + + speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F; + cnt = 2000; + + while ((speed != PCIE_GEN1_SPEED) && (cnt != 0)) { + PLTFM_DELAY_US(50); + speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET); + speed &= 0x0F; + cnt--; + } + + if (speed != PCIE_GEN1_SPEED) { + PLTFM_MSG_ERR("[ERR]Speed change to GEN1 fail !\n"); + return HALMAC_RET_FAIL; + } + + } else if (cfg == HALMAC_PCIE_GEN2) { + value8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0; + dbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET, value8 | BIT(1)); + + value32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET); + dbi_w32_88xx(adapter, GEN2_CTRL_OFFSET, value32 | BIT(17)); + + speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F; + cnt = 2000; + + while ((speed != PCIE_GEN2_SPEED) && (cnt != 0)) { + PLTFM_DELAY_US(50); + speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET); + speed &= 0x0F; + cnt--; + } + + if (speed != PCIE_GEN2_SPEED) { + PLTFM_MSG_ERR("[ERR]Speed change to GEN1 fail !\n"); + return HALMAC_RET_FAIL; + } + + } else { + PLTFM_MSG_ERR("[ERR]Error Speed !\n"); + return HALMAC_RET_FAIL; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * phy_cfg_pcie_8822b() - phy config + * @adapter : the adapter of halmac + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +phy_cfg_pcie_8822b(struct halmac_adapter *adapter, + enum halmac_intf_phy_platform pltfm) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = parse_intf_phy_88xx(adapter, pcie_gen1_phy_param_8822b, pltfm, + HAL_INTF_PHY_PCIE_GEN1); + + if (status != HALMAC_RET_SUCCESS) + return status; + + status = parse_intf_phy_88xx(adapter, pcie_gen2_phy_param_8822b, pltfm, + HAL_INTF_PHY_PCIE_GEN2); + + if (status != HALMAC_RET_SUCCESS) + return status; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * intf_tun_pcie_8822b() - pcie interface fine tuning + * @adapter : the adapter of halmac + * Author : Rick Liu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +intf_tun_pcie_8822b(struct halmac_adapter *adapter) +{ + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_8822B_SUPPORT*/ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.h new file mode 100644 index 0000000..9a4daa8 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.h @@ -0,0 +1,42 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_API_8822B_PCIE_H_ +#define _HALMAC_API_8822B_PCIE_H_ + +#include "../../halmac_api.h" + +#if HALMAC_8822B_SUPPORT + +extern struct halmac_intf_phy_para pcie_gen1_phy_param_8822b[]; +extern struct halmac_intf_phy_para pcie_gen2_phy_param_8822b[]; + +enum halmac_ret_status +mac_pwr_switch_pcie_8822b(struct halmac_adapter *adapter, + enum halmac_mac_power pwr); + +enum halmac_ret_status +pcie_switch_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg); + +enum halmac_ret_status +phy_cfg_pcie_8822b(struct halmac_adapter *adapter, + enum halmac_intf_phy_platform pltfm); + +enum halmac_ret_status +intf_tun_pcie_8822b(struct halmac_adapter *adapter); + +#endif /* HALMAC_8822B_SUPPORT*/ + +#endif/* _HALMAC_API_8822B_PCIE_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_phy_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_phy_8822b.c new file mode 100644 index 0000000..03d2e1a --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_phy_8822b.c @@ -0,0 +1,150 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "../../halmac_type.h" + +/** + * ============ip sel item list============ + * HALMAC_IP_INTF_PHY + * USB2 : usb2 phy, 1byte value + * USB3 : usb3 phy, 2byte value + * PCIE1 : pcie gen1 mdio, 2byte value + * PCIE2 : pcie gen2 mdio, 2byte value + * HALMAC_IP_SEL_MAC + * USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value + * HALMAC_IP_PCIE_DBI + * USB2 USB3 : none + * PCIE1, PCIE2 : pcie dbi, 1byte value + */ + +#if HALMAC_8822B_SUPPORT + +struct halmac_intf_phy_para usb2_phy_param_8822b[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0xFFFF, 0x00, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_ALL, + HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +struct halmac_intf_phy_para usb3_phy_8822b[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0x0001, 0xA841, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_D, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0xFFFF, 0x0000, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_ALL, + HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +struct halmac_intf_phy_para pcie_gen1_phy_param_8822b[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0x0001, 0xA841, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0002, 0x60C6, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0008, 0x3596, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0009, 0x321C, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x000A, 0x9623, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0020, 0x94FF, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0021, 0xFFCF, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0026, 0xC006, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0029, 0xFF0E, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x002A, 0x1840, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0xFFFF, 0x0000, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_ALL, + HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +struct halmac_intf_phy_para pcie_gen2_phy_param_8822b[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0x0001, 0xA841, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0002, 0x60C6, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0008, 0x3597, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0009, 0x321C, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x000A, 0x9623, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0020, 0x94FF, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0021, 0xFFCF, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0026, 0xC006, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x0029, 0xFF0E, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0x002A, 0x3040, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_C, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0xFFFF, 0x0000, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_ALL, + HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +#endif /* HALMAC_8822B_SUPPORT*/ \ No newline at end of file diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.c new file mode 100644 index 0000000..3ba9f79 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.c @@ -0,0 +1,914 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_pwr_seq_8822b.h" + +#if HALMAC_8822B_SUPPORT + +struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8822B[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, + {0x004A, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, + {0x0300, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0x0301, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8822B[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0012, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0012, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0020, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0001, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWR_DELAY_MS}, + {0x0000, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), 0}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, + {0x0075, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0006, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, + {0x0075, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0xFF1A, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0x0006, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), 0}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, + {0x10C3, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, BIT(0), 0}, + {0x0020, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, + {0x10A8, + HALMAC_PWR_CUT_C_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0x10A9, + HALMAC_PWR_CUT_C_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xef}, + {0x10AA, + HALMAC_PWR_CUT_C_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x0c}, + {0x0068, + HALMAC_PWR_CUT_C_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, + {0x0029, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xF9}, + {0x0024, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(2), 0}, + {0x0074, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, + {0x00AF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8822B[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0003, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(2), 0}, + {0x0093, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3), 0}, + {0x001F, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0x00EF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0xFF1A, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x30}, + {0x0049, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0006, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x10C3, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, BIT(1), 0}, + {0x0020, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3), 0}, + {0x0000, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822B[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x0007, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0067, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), 0}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, + {0x004A, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0067, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), 0}, + {0x0067, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4), 0}, + {0x004F, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0067, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0046, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6)}, + {0x0067, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(2), 0}, + {0x0046, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x0062, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, + {0x0081, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), 0}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_POLLING, BIT(1), 0}, + {0x0090, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0044, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0x0040, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0041, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0042, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x04}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +/* Card Enable Array */ +struct halmac_wlan_pwr_cfg *card_en_flow_8822b[] = { + TRANS_CARDDIS_TO_CARDEMU_8822B, + TRANS_CARDEMU_TO_ACT_8822B, + NULL +}; + +/* Card Disable Array */ +struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[] = { + TRANS_ACT_TO_CARDEMU_8822B, + TRANS_CARDEMU_TO_CARDDIS_8822B, + NULL +}; + +#if HALMAC_PLATFORM_TESTPROGRAM + +struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8822B[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, + {0x0007, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_POLLING, BIT(1), 0}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8822B[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8822B[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0007, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0006, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8822B[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), 0}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8822B[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0101, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, + {0x0199, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, + {0x019B, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x1138, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)}, + {0x0194, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0093, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x42}, + {0x0092, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0090, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, + {0x0301, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0522, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x05F8, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x05F9, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x05FA, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x05FB, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0100, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F}, + {0x0101, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0553, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, + {0x0008, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, + {0x0109, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)}, + {0x0090, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822B[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0101, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, + {0x0199, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, + {0x019B, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x1138, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)}, + {0x0194, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0093, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x40}, + {0x0092, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0090, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, + {0x0301, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0522, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x05F8, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x05F9, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x05FA, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x05FB, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0100, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F}, + {0x0101, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0553, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, + {0x0008, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, + {0x0109, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)}, + {0x0090, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +struct halmac_wlan_pwr_cfg TRANS_LPS_TO_ACT_8822B[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0080, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS}, + {0x0080, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, BIT(7), 0}, + {0xFE58, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x84}, + {0xFE58, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x04}, + {0x03D9, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS}, + {0x03D9, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), 0}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS}, + {0x0008, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4), 0}, + {0x0109, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, BIT(7), 0}, + {0x0101, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, + {0x0100, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, + {0x0522, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0x113C, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x03}, + {0x0124, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0125, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0126, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0127, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0090, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0101, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(2), 0}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +/* Suspend Array */ +struct halmac_wlan_pwr_cfg *suspend_flow_8822b[] = { + TRANS_ACT_TO_CARDEMU_8822B, + TRANS_CARDEMU_TO_SUS_8822B, + NULL +}; + +/* Resume Array */ +struct halmac_wlan_pwr_cfg *resume_flow_8822b[] = { + TRANS_SUS_TO_CARDEMU_8822B, + TRANS_CARDEMU_TO_ACT_8822B, + NULL +}; + +/* HWPDN Array - HW behavior */ +struct halmac_wlan_pwr_cfg *hwpdn_flow_8822b[] = { + NULL +}; + +/* Enter LPS - FW behavior */ +struct halmac_wlan_pwr_cfg *enter_lps_flow_8822b[] = { + TRANS_ACT_TO_LPS_8822B, + NULL +}; + +/* Enter Deep LPS - FW behavior */ +struct halmac_wlan_pwr_cfg *enter_dlps_flow_8822b[] = { + TRANS_ACT_TO_DEEP_LPS_8822B, + NULL +}; + +/* Leave LPS -FW behavior */ +struct halmac_wlan_pwr_cfg *leave_lps_flow_8822b[] = { + TRANS_LPS_TO_ACT_8822B, + NULL +}; + +#endif + +#endif /* HALMAC_8822B_SUPPORT*/ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.h new file mode 100644 index 0000000..5798bda --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.h @@ -0,0 +1,40 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef HALMAC_POWER_SEQUENCE_8822B +#define HALMAC_POWER_SEQUENCE_8822B + +#include "../../halmac_pwr_seq_cmd.h" +#include "../../halmac_hw_cfg.h" + +#if HALMAC_8822B_SUPPORT + +#define HALMAC_8822B_PWR_SEQ_VER "V24" + +extern struct halmac_wlan_pwr_cfg *card_en_flow_8822b[]; +extern struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[]; + +#if HALMAC_PLATFORM_TESTPROGRAM +extern struct halmac_wlan_pwr_cfg *suspend_flow_8822b[]; +extern struct halmac_wlan_pwr_cfg *resume_flow_8822b[]; +extern struct halmac_wlan_pwr_cfg *hwpdn_flow_8822b[]; +extern struct halmac_wlan_pwr_cfg *enter_lps_flow_8822b[]; +extern struct halmac_wlan_pwr_cfg *enter_dlps_flow_8822b[]; +extern struct halmac_wlan_pwr_cfg *leave_lps_flow_8822b[]; +#endif + +#endif /* HALMAC_8822B_SUPPORT*/ + +#endif diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.c new file mode 100644 index 0000000..0a691b6 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.c @@ -0,0 +1,868 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_sdio_8822b.h" +#include "halmac_pwr_seq_8822b.h" +#include "../halmac_init_88xx.h" +#include "../halmac_common_88xx.h" +#include "../halmac_sdio_88xx.h" + +#if HALMAC_8822B_SUPPORT + +#define WLAN_ACQ_NUM_MAX 8 + +static enum halmac_ret_status +chk_oqt_8822b(struct halmac_adapter *adapter, u32 tx_agg_num, u8 *buf, + u8 macid_cnt); + +static enum halmac_ret_status +update_oqt_free_space_8822b(struct halmac_adapter *adapter); + +static enum halmac_ret_status +update_sdio_free_page_8822b(struct halmac_adapter *adapter); + +static enum halmac_ret_status +chk_qsel_8822b(struct halmac_adapter *adapter, u8 qsel_first, u8 *pkt, + u8 *macid_cnt); + +static enum halmac_ret_status +chk_dma_mapping_8822b(struct halmac_adapter *adapter, u16 **cur_fs, + u8 qsel_first); + +static enum halmac_ret_status +chk_rqd_page_num_8822b(struct halmac_adapter *adapter, u8 *buf, u32 *rqd_pg_num, + u16 **cur_fs, u8 *macid_cnt, u32 tx_agg_num); + +/** + * mac_pwr_switch_sdio_8822b() - switch mac power + * @adapter : the adapter of halmac + * @pwr : power state + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mac_pwr_switch_sdio_8822b(struct halmac_adapter *adapter, + enum halmac_mac_power pwr) +{ + u8 value8; + u8 rpwm; + u32 imr_backup; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]8822B pwr seq ver = %s\n", + HALMAC_8822B_PWR_SEQ_VER); + + adapter->rpwm = HALMAC_REG_R8(REG_SDIO_HRPWM1); + + /* Check FW still exist or not */ + if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) { + /* Leave 32K */ + rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80); + HALMAC_REG_W8(REG_SDIO_HRPWM1, rpwm); + } + + value8 = HALMAC_REG_R8(REG_CR); + if (value8 == 0xEA) + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF; + else + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON; + + /*Check if power switch is needed*/ + if (pwr == HALMAC_MAC_POWER_ON && + adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) { + PLTFM_MSG_WARN("[WARN]power state unchange!!\n"); + return HALMAC_RET_PWR_UNCHANGE; + } + + imr_backup = HALMAC_REG_R32(REG_SDIO_HIMR); + HALMAC_REG_W32(REG_SDIO_HIMR, 0); + + if (pwr == HALMAC_MAC_POWER_OFF) { + adapter->pwr_off_flow_flag = 1; + if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) != + HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n"); + HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup); + return HALMAC_RET_POWER_OFF_FAIL; + } + + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF; + adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + adapter->pwr_off_flow_flag = 0; + init_adapter_dynamic_param_88xx(adapter); + } else { + if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) != + HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n"); + HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup); + return HALMAC_RET_POWER_ON_FAIL; + } + + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON; + } + + HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_tx_allowed_sdio_88xx() - check tx status + * @adapter : the adapter of halmac + * @buf : tx packet, include txdesc + * @size : tx packet size, include txdesc + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +tx_allowed_sdio_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u16 *cur_fs = NULL; + u32 cnt; + u32 tx_agg_num; + u32 rqd_pg_num = 0; + u8 macid_cnt = 0; + struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!fs_info->macid_map) { + PLTFM_MSG_ERR("[ERR]halmac allocate Macid_map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + + PLTFM_MEMSET(fs_info->macid_map, 0x00, fs_info->macid_map_size); + + tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(buf); + tx_agg_num = (tx_agg_num == 0) ? 1 : tx_agg_num; + + status = chk_rqd_page_num_8822b(adapter, buf, &rqd_pg_num, &cur_fs, + &macid_cnt, tx_agg_num); + if (status != HALMAC_RET_SUCCESS) + return status; + + cnt = 10; + do { + if ((u32)(*cur_fs + fs_info->pubq_pg_num) > rqd_pg_num) { + status = chk_oqt_8822b(adapter, tx_agg_num, buf, + macid_cnt); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_WARN("[WARN]oqt buffer full!!\n"); + return status; + } + + if (*cur_fs >= rqd_pg_num) { + *cur_fs -= (u16)rqd_pg_num; + } else { + fs_info->pubq_pg_num -= + (u16)(rqd_pg_num - *cur_fs); + *cur_fs = 0; + } + + break; + } + + update_sdio_free_page_8822b(adapter); + + cnt--; + if (cnt == 0) + return HALMAC_RET_FREE_SPACE_NOT_ENOUGH; + } while (1); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_reg_read_8_sdio_88xx() - read 1byte register + * @adapter : the adapter of halmac + * @offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u8 +reg_r8_sdio_8822b(struct halmac_adapter *adapter, u32 offset) +{ + u8 value8; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if ((offset & 0xFFFF0000) == 0) { + value8 = (u8)r_indir_sdio_88xx(adapter, offset, HALMAC_IO_BYTE); + } else { + status = cnv_to_sdio_bus_offset_88xx(adapter, &offset); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]convert offset\n"); + return status; + } + value8 = PLTFM_SDIO_CMD52_R(offset); + } + + return value8; +} + +/** + * halmac_reg_write_8_sdio_88xx() - write 1byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @value : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reg_w8_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u8 value) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if ((offset & 0xFFFF0000) == 0) + offset |= WLAN_IOREG_OFFSET; + + status = cnv_to_sdio_bus_offset_88xx(adapter, &offset); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]convert offset\n"); + return status; + } + + PLTFM_SDIO_CMD52_W(offset, value); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_reg_read_16_sdio_88xx() - read 2byte register + * @adapter : the adapter of halmac + * @offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u16 +reg_r16_sdio_8822b(struct halmac_adapter *adapter, u32 offset) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + union { + u16 word; + u8 byte[2]; + } value16 = { 0x0000 }; + + if ((offset & 0xFFFF0000) == 0) + return (u16)r_indir_sdio_88xx(adapter, offset, HALMAC_IO_WORD); + + status = cnv_to_sdio_bus_offset_88xx(adapter, &offset); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]convert offset\n"); + return status; + } + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF || + ((offset & (2 - 1)) != 0) || + adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW || + adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_R) { + value16.byte[0] = PLTFM_SDIO_CMD52_R(offset); + value16.byte[1] = PLTFM_SDIO_CMD52_R(offset + 1); + value16.word = rtk_le16_to_cpu(value16.word); + } else { + value16.word = PLTFM_SDIO_CMD53_R16(offset); + } + + return value16.word; +} + +/** + * halmac_reg_write_16_sdio_88xx() - write 2byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @value : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reg_w16_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u16 value) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF || + ((offset & (2 - 1)) != 0) || + adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW || + adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_W) { + if ((offset & 0xFFFF0000) == 0 && ((offset & (2 - 1)) == 0)) { + status = w_indir_sdio_88xx(adapter, offset, value, + HALMAC_IO_WORD); + } else { + if ((offset & 0xFFFF0000) == 0) + offset |= WLAN_IOREG_OFFSET; + + status = cnv_to_sdio_bus_offset_88xx(adapter, &offset); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]convert offset\n"); + return status; + } + PLTFM_SDIO_CMD52_W(offset, (u8)(value & 0xFF)); + PLTFM_SDIO_CMD52_W(offset + 1, + (u8)((value & 0xFF00) >> 8)); + } + } else { + if ((offset & 0xFFFF0000) == 0) + offset |= WLAN_IOREG_OFFSET; + + status = cnv_to_sdio_bus_offset_88xx(adapter, &offset); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]convert offset\n"); + return status; + } + + PLTFM_SDIO_CMD53_W16(offset, value); + } + return status; +} + +/** + * halmac_reg_read_32_sdio_88xx() - read 4byte register + * @adapter : the adapter of halmac + * @offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u32 +reg_r32_sdio_8822b(struct halmac_adapter *adapter, u32 offset) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + union { + u32 dword; + u8 byte[4]; + } value32 = { 0x00000000 }; + + if ((offset & 0xFFFF0000) == 0) + return r_indir_sdio_88xx(adapter, offset, HALMAC_IO_DWORD); + + status = cnv_to_sdio_bus_offset_88xx(adapter, &offset); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]convert offset\n"); + return status; + } + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF || + (offset & (4 - 1)) != 0) { + value32.byte[0] = PLTFM_SDIO_CMD52_R(offset); + value32.byte[1] = PLTFM_SDIO_CMD52_R(offset + 1); + value32.byte[2] = PLTFM_SDIO_CMD52_R(offset + 2); + value32.byte[3] = PLTFM_SDIO_CMD52_R(offset + 3); + value32.dword = rtk_le32_to_cpu(value32.dword); + } else { + value32.dword = PLTFM_SDIO_CMD53_R32(offset); + } + + return value32.dword; +} + +/** + * halmac_reg_write_32_sdio_88xx() - write 4byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @value : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reg_w32_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u32 value) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF || + (offset & (4 - 1)) != 0) { + if ((offset & 0xFFFF0000) == 0 && ((offset & (4 - 1)) == 0)) { + status = w_indir_sdio_88xx(adapter, offset, value, + HALMAC_IO_DWORD); + } else { + if ((offset & 0xFFFF0000) == 0) + offset |= WLAN_IOREG_OFFSET; + + status = cnv_to_sdio_bus_offset_88xx(adapter, &offset); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]convert offset\n"); + return status; + } + PLTFM_SDIO_CMD52_W(offset, (u8)(value & 0xFF)); + PLTFM_SDIO_CMD52_W(offset + 1, + (u8)((value >> 8) & 0xFF)); + PLTFM_SDIO_CMD52_W(offset + 2, + (u8)((value >> 16) & 0xFF)); + PLTFM_SDIO_CMD52_W(offset + 3, + (u8)((value >> 24) & 0xFF)); + } + } else { + if ((offset & 0xFFFF0000) == 0) + offset |= WLAN_IOREG_OFFSET; + + status = cnv_to_sdio_bus_offset_88xx(adapter, &offset); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]convert offset\n"); + return status; + } + PLTFM_SDIO_CMD53_W32(offset, value); + } + + return status; +} + +static enum halmac_ret_status +chk_oqt_8822b(struct halmac_adapter *adapter, u32 tx_agg_num, u8 *buf, + u8 macid_cnt) +{ + u32 cnt = 10; + struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs; + + /*S0, S1 are not allowed to use, 0x4E4[0] should be 0. Soar 20160323*/ + /*no need to check non_ac_oqt_number*/ + /*HI and MGQ blocked will cause protocal issue before H_OQT being full*/ + switch ((enum halmac_qsel)GET_TX_DESC_QSEL(buf)) { + case HALMAC_QSEL_VO: + case HALMAC_QSEL_VO_V2: + case HALMAC_QSEL_VI: + case HALMAC_QSEL_VI_V2: + case HALMAC_QSEL_BE: + case HALMAC_QSEL_BE_V2: + case HALMAC_QSEL_BK: + case HALMAC_QSEL_BK_V2: + if (macid_cnt > WLAN_ACQ_NUM_MAX && + tx_agg_num > OQT_ENTRY_AC_8822B) { + PLTFM_MSG_WARN("[WARN]txagg num %d > oqt entry\n", + tx_agg_num); + PLTFM_MSG_WARN("[WARN]macid cnt %d > acq max\n", + macid_cnt); + } + + cnt = 10; + do { + if (fs_info->ac_empty >= macid_cnt) { + fs_info->ac_empty -= macid_cnt; + break; + } + + if (fs_info->ac_oqt_num >= tx_agg_num) { + fs_info->ac_empty = 0; + fs_info->ac_oqt_num -= (u8)tx_agg_num; + break; + } + + update_oqt_free_space_8822b(adapter); + + cnt--; + if (cnt == 0) + return HALMAC_RET_OQT_NOT_ENOUGH; + } while (1); + break; + case HALMAC_QSEL_MGNT: + case HALMAC_QSEL_HIGH: + if (tx_agg_num > OQT_ENTRY_NOAC_8822B) + PLTFM_MSG_WARN("[WARN]tx_agg_num %d > oqt entry\n", + tx_agg_num, OQT_ENTRY_NOAC_8822B); + + cnt = 10; + do { + if (fs_info->non_ac_oqt_num >= tx_agg_num) { + fs_info->non_ac_oqt_num -= (u8)tx_agg_num; + break; + } + + update_oqt_free_space_8822b(adapter); + + cnt--; + if (cnt == 0) + return HALMAC_RET_OQT_NOT_ENOUGH; + } while (1); + break; + default: + break; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +update_oqt_free_space_8822b(struct halmac_adapter *adapter) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs; + u8 value; + u32 oqt_free_page; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + oqt_free_page = HALMAC_REG_R32(REG_SDIO_OQT_FREE_TXPG_V1); + fs_info->ac_oqt_num = (u8)BIT_GET_AC_OQT_FREEPG_V1(oqt_free_page); + fs_info->non_ac_oqt_num = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(oqt_free_page); + fs_info->ac_empty = 0; + if (fs_info->ac_oqt_num == OQT_ENTRY_AC_8822B) { + value = HALMAC_REG_R8(REG_TXPKT_EMPTY); + while (value > 0) { + value = value & (value - 1); + fs_info->ac_empty++; + }; + } else { + PLTFM_MSG_TRACE("[TRACE]free_space->ac_oqt_num %d != %d\n", + fs_info->ac_oqt_num, OQT_ENTRY_AC_8822B); + } + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +update_sdio_free_page_8822b(struct halmac_adapter *adapter) +{ + u32 free_page = 0; + u32 free_page2 = 0; + u32 free_page3 = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs; + u8 data[12] = {0}; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + HALMAC_REG_SDIO_RN(REG_SDIO_FREE_TXPG, 12, data); + + free_page = rtk_le32_to_cpu(*(u32 *)(data + 0)); + free_page2 = rtk_le32_to_cpu(*(u32 *)(data + 4)); + free_page3 = rtk_le32_to_cpu(*(u32 *)(data + 8)); + + fs_info->hiq_pg_num = (u16)BIT_GET_HIQ_FREEPG_V1(free_page); + fs_info->miq_pg_num = (u16)BIT_GET_MID_FREEPG_V1(free_page); + fs_info->lowq_pg_num = (u16)BIT_GET_LOW_FREEPG_V1(free_page2); + fs_info->pubq_pg_num = (u16)BIT_GET_PUB_FREEPG_V1(free_page2); + fs_info->exq_pg_num = (u16)BIT_GET_EXQ_FREEPG_V1(free_page3); + fs_info->ac_oqt_num = (u8)BIT_GET_AC_OQT_FREEPG_V1(free_page3); + fs_info->non_ac_oqt_num = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(free_page3); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * phy_cfg_sdio_8822b() - phy config + * @adapter : the adapter of halmac + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +phy_cfg_sdio_8822b(struct halmac_adapter *adapter, + enum halmac_intf_phy_platform pltfm) +{ + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pcie_switch_8821c() - pcie gen1/gen2 switch + * @adapter : the adapter of halmac + * @cfg : gen1/gen2 selection + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pcie_switch_sdio_8822b(struct halmac_adapter *adapter, + enum halmac_pcie_cfg cfg) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * intf_tun_sdio_8822b() - sdio interface fine tuning + * @adapter : the adapter of halmac + * Author : Ivan + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +intf_tun_sdio_8822b(struct halmac_adapter *adapter) +{ + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_get_sdio_tx_addr_sdio_88xx() - get CMD53 addr for the TX packet + * @adapter : the adapter of halmac + * @buf : tx packet, include txdesc + * @size : tx packet size + * @cmd53_addr : cmd53 addr value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_sdio_tx_addr_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size, + u32 *cmd53_addr) +{ + u32 len_unit4; + enum halmac_qsel queue_sel; + enum halmac_dma_mapping dma_mapping; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!buf) { + PLTFM_MSG_ERR("[ERR]buf is NULL!!\n"); + return HALMAC_RET_DATA_BUF_NULL; + } + + if (size == 0) { + PLTFM_MSG_ERR("[ERR]size is 0!!\n"); + return HALMAC_RET_DATA_SIZE_INCORRECT; + } + + queue_sel = (enum halmac_qsel)GET_TX_DESC_QSEL(buf); + + switch (queue_sel) { + case HALMAC_QSEL_VO: + case HALMAC_QSEL_VO_V2: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO]; + break; + case HALMAC_QSEL_VI: + case HALMAC_QSEL_VI_V2: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI]; + break; + case HALMAC_QSEL_BE: + case HALMAC_QSEL_BE_V2: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE]; + break; + case HALMAC_QSEL_BK: + case HALMAC_QSEL_BK_V2: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK]; + break; + case HALMAC_QSEL_MGNT: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG]; + break; + case HALMAC_QSEL_HIGH: + case HALMAC_QSEL_BCN: + case HALMAC_QSEL_CMD: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_HI]; + break; + default: + PLTFM_MSG_ERR("[ERR]Qsel is out of range\n"); + return HALMAC_RET_QSEL_INCORRECT; + } + + len_unit4 = (size >> 2) + ((size & (4 - 1)) ? 1 : 0); + + switch (dma_mapping) { + case HALMAC_DMA_MAPPING_HIGH: + *cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_HIGH; + break; + case HALMAC_DMA_MAPPING_NORMAL: + *cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL; + break; + case HALMAC_DMA_MAPPING_LOW: + *cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_LOW; + break; + case HALMAC_DMA_MAPPING_EXTRA: + *cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA; + break; + default: + PLTFM_MSG_ERR("[ERR]DmaMapping is out of range\n"); + return HALMAC_RET_DMA_MAP_INCORRECT; + } + + *cmd53_addr = (*cmd53_addr << 13) | + (len_unit4 & HALMAC_SDIO_4BYTE_LEN_MASK); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +chk_qsel_8822b(struct halmac_adapter *adapter, u8 qsel_first, u8 *pkt, + u8 *macid_cnt) +{ + u8 flag = 0; + u8 qsel_now; + u8 macid; + struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs; + + macid = (u8)GET_TX_DESC_MACID(pkt); + qsel_now = (u8)GET_TX_DESC_QSEL(pkt); + if (qsel_first == qsel_now) { + if (*(fs_info->macid_map + macid) == 0) { + *(fs_info->macid_map + macid) = 1; + (*macid_cnt)++; + } + } else { + switch ((enum halmac_qsel)qsel_now) { + case HALMAC_QSEL_VO: + if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VO_V2) + flag = 1; + break; + case HALMAC_QSEL_VO_V2: + if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VO) + flag = 1; + break; + case HALMAC_QSEL_VI: + if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VI_V2) + flag = 1; + break; + case HALMAC_QSEL_VI_V2: + if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VI) + flag = 1; + break; + case HALMAC_QSEL_BE: + if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BE_V2) + flag = 1; + break; + case HALMAC_QSEL_BE_V2: + if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BE) + flag = 1; + break; + case HALMAC_QSEL_BK: + if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BK_V2) + flag = 1; + break; + case HALMAC_QSEL_BK_V2: + if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BK) + flag = 1; + break; + case HALMAC_QSEL_MGNT: + case HALMAC_QSEL_HIGH: + case HALMAC_QSEL_BCN: + case HALMAC_QSEL_CMD: + flag = 1; + break; + default: + PLTFM_MSG_ERR("[ERR]Qsel is out of range\n"); + return HALMAC_RET_QSEL_INCORRECT; + } + if (flag == 1) { + PLTFM_MSG_ERR("[ERR]Multi-Qsel is not allowed\n"); + PLTFM_MSG_ERR("[ERR]qsel = %d, %d\n", + qsel_first, qsel_now); + return HALMAC_RET_QSEL_INCORRECT; + } + if (*(fs_info->macid_map + macid + MACID_MAX_8822B) == 0) { + *(fs_info->macid_map + macid + MACID_MAX_8822B) = 1; + (*macid_cnt)++; + } + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +chk_dma_mapping_8822b(struct halmac_adapter *adapter, u16 **cur_fs, + u8 qsel_first) +{ + enum halmac_dma_mapping dma_mapping; + + switch ((enum halmac_qsel)qsel_first) { + case HALMAC_QSEL_VO: + case HALMAC_QSEL_VO_V2: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO]; + break; + case HALMAC_QSEL_VI: + case HALMAC_QSEL_VI_V2: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI]; + break; + case HALMAC_QSEL_BE: + case HALMAC_QSEL_BE_V2: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE]; + break; + case HALMAC_QSEL_BK: + case HALMAC_QSEL_BK_V2: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK]; + break; + case HALMAC_QSEL_MGNT: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG]; + break; + case HALMAC_QSEL_HIGH: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_HI]; + break; + case HALMAC_QSEL_BCN: + case HALMAC_QSEL_CMD: + return HALMAC_RET_SUCCESS; + default: + PLTFM_MSG_ERR("[ERR]Qsel is out of range: %d\n", qsel_first); + return HALMAC_RET_QSEL_INCORRECT; + } + + switch (dma_mapping) { + case HALMAC_DMA_MAPPING_HIGH: + *cur_fs = &adapter->sdio_fs.hiq_pg_num; + break; + case HALMAC_DMA_MAPPING_NORMAL: + *cur_fs = &adapter->sdio_fs.miq_pg_num; + break; + case HALMAC_DMA_MAPPING_LOW: + *cur_fs = &adapter->sdio_fs.lowq_pg_num; + break; + case HALMAC_DMA_MAPPING_EXTRA: + *cur_fs = &adapter->sdio_fs.exq_pg_num; + break; + default: + PLTFM_MSG_ERR("[ERR]DmaMapping is out of range\n"); + return HALMAC_RET_DMA_MAP_INCORRECT; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +chk_rqd_page_num_8822b(struct halmac_adapter *adapter, u8 *buf, u32 *rqd_pg_num, + u16 **cur_fs, u8 *macid_cnt, u32 tx_agg_num) +{ + u8 *pkt; + u8 qsel_first; + u32 i; + u32 pkt_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + pkt = buf; + + qsel_first = (u8)GET_TX_DESC_QSEL(pkt); + + status = chk_dma_mapping_8822b(adapter, cur_fs, qsel_first); + if (status != HALMAC_RET_SUCCESS) + return status; + + for (i = 0; i < tx_agg_num; i++) { + /*QSEL parser*/ + status = chk_qsel_8822b(adapter, qsel_first, pkt, macid_cnt); + if (status != HALMAC_RET_SUCCESS) + return status; + + /*Page number parser*/ + pkt_size = GET_TX_DESC_TXPKTSIZE(pkt) + GET_TX_DESC_OFFSET(pkt); + *rqd_pg_num += (pkt_size >> TX_PAGE_SIZE_SHIFT_88XX) + + ((pkt_size & (TX_PAGE_SIZE_88XX - 1)) ? 1 : 0); + + pkt += HALMAC_ALIGN(GET_TX_DESC_TXPKTSIZE(pkt) + + (GET_TX_DESC_PKT_OFFSET(pkt) << 3) + + TX_DESC_SIZE_88XX, 8); + } + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_8822B_SUPPORT*/ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.h new file mode 100644 index 0000000..486787d --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.h @@ -0,0 +1,66 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_API_8822B_SDIO_H_ +#define _HALMAC_API_8822B_SDIO_H_ + +#include "../../halmac_api.h" +#include "halmac_8822b_cfg.h" + +#if HALMAC_8822B_SUPPORT + +enum halmac_ret_status +mac_pwr_switch_sdio_8822b(struct halmac_adapter *adapter, + enum halmac_mac_power pwr); + +enum halmac_ret_status +tx_allowed_sdio_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size); + +u8 +reg_r8_sdio_8822b(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +reg_w8_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u8 value); + +u16 +reg_r16_sdio_8822b(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +reg_w16_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u16 value); + +u32 +reg_r32_sdio_8822b(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +reg_w32_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u32 value); + +enum halmac_ret_status +phy_cfg_sdio_8822b(struct halmac_adapter *adapter, + enum halmac_intf_phy_platform pltfm); + +enum halmac_ret_status +pcie_switch_sdio_8822b(struct halmac_adapter *adapter, + enum halmac_pcie_cfg cfg); + +enum halmac_ret_status +intf_tun_sdio_8822b(struct halmac_adapter *adapter); + +enum halmac_ret_status +get_sdio_tx_addr_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size, + u32 *cmd53_addr); + +#endif /* HALMAC_8822B_SUPPORT*/ + +#endif/* _HALMAC_API_8822B_SDIO_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.c new file mode 100644 index 0000000..6d0e2be --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.c @@ -0,0 +1,159 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_usb_8822b.h" +#include "halmac_pwr_seq_8822b.h" +#include "../halmac_init_88xx.h" +#include "../halmac_common_88xx.h" + +#if HALMAC_8822B_SUPPORT + +/** + * mac_pwr_switch_usb_8822b() - switch mac power + * @adapter : the adapter of halmac + * @pwr : power state + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mac_pwr_switch_usb_8822b(struct halmac_adapter *adapter, + enum halmac_mac_power pwr) +{ + u8 value8; + u8 rpwm; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s\n", __func__); + PLTFM_MSG_TRACE("[TRACE]%x\n", pwr); + PLTFM_MSG_TRACE("[TRACE]8821C pwr seq ver = %s\n", + HALMAC_8822B_PWR_SEQ_VER); + + adapter->rpwm = HALMAC_REG_R8(0xFE58); + + /* Check FW still exist or not */ + if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) { + /* Leave 32K */ + rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80); + HALMAC_REG_W8(0xFE58, rpwm); + } + + value8 = HALMAC_REG_R8(REG_CR); + if (value8 == 0xEA) { + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF; + } else { + if (BIT(0) == (HALMAC_REG_R8(REG_SYS_STATUS1 + 1) & BIT(0))) + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF; + else + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON; + } + + /*Check if power switch is needed*/ + if (pwr == HALMAC_MAC_POWER_ON && + adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) { + PLTFM_MSG_WARN("[WARN]power state unchange!!\n"); + return HALMAC_RET_PWR_UNCHANGE; + } + + if (pwr == HALMAC_MAC_POWER_OFF) { + if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) != + HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n"); + return HALMAC_RET_POWER_OFF_FAIL; + } + + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF; + adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + init_adapter_dynamic_param_88xx(adapter); + } else { + if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) != + HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n"); + return HALMAC_RET_POWER_ON_FAIL; + } + + HALMAC_REG_W8_CLR(REG_SYS_STATUS1 + 1, BIT(0)); + + if ((HALMAC_REG_R8(REG_SW_MDIO + 3) & BIT(0)) == BIT(0)) + PLTFM_MSG_ALWAYS("[ALWAYS]shall R reg twice!!\n"); + + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * phy_cfg_usb_8822b() - phy config + * @adapter : the adapter of halmac + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +phy_cfg_usb_8822b(struct halmac_adapter *adapter, + enum halmac_intf_phy_platform pltfm) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = parse_intf_phy_88xx(adapter, usb2_phy_param_8822b, pltfm, + HAL_INTF_PHY_USB2); + + if (status != HALMAC_RET_SUCCESS) + return status; + + status = parse_intf_phy_88xx(adapter, usb3_phy_8822b, pltfm, + HAL_INTF_PHY_USB3); + + if (status != HALMAC_RET_SUCCESS) + return status; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pcie_switch_8822b() - pcie gen1/gen2 switch + * @adapter : the adapter of halmac + * @cfg : gen1/gen2 selection + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pcie_switch_usb_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * intf_tun_usb_8822b() - usb interface fine tuning + * @adapter : the adapter of halmac + * Author : Ivan + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +intf_tun_usb_8822b(struct halmac_adapter *adapter) +{ + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_8822B_SUPPORT*/ \ No newline at end of file diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.h new file mode 100644 index 0000000..b55c75d --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.h @@ -0,0 +1,42 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_API_8822B_USB_H_ +#define _HALMAC_API_8822B_USB_H_ + +#include "../../halmac_api.h" + +#if HALMAC_8822B_SUPPORT + +extern struct halmac_intf_phy_para usb2_phy_param_8822b[]; +extern struct halmac_intf_phy_para usb3_phy_8822b[]; + +enum halmac_ret_status +mac_pwr_switch_usb_8822b(struct halmac_adapter *adapter, + enum halmac_mac_power pwr); + +enum halmac_ret_status +phy_cfg_usb_8822b(struct halmac_adapter *adapter, + enum halmac_intf_phy_platform pltfm); + +enum halmac_ret_status +pcie_switch_usb_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg); + +enum halmac_ret_status +intf_tun_usb_8822b(struct halmac_adapter *adapter); + +#endif /* HALMAC_8822B_SUPPORT*/ + +#endif/* _HALMAC_API_8822B_USB_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c b/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c new file mode 100644 index 0000000..eb0085a --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c @@ -0,0 +1,392 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_bb_rf_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_common_88xx.h" +#include "halmac_init_88xx.h" + +#if HALMAC_88XX_SUPPORT + +/** + * start_iqk_88xx() -trigger FW IQK + * @adapter : the adapter of halmac + * @param : IQK parameter + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +start_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_h2c_header_info hdr_info; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.iqk_state.proc_status; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_TRACE("[TRACE]Wait event(iqk)\n"); + return HALMAC_RET_BUSY_STATE; + } + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + IQK_SET_CLEAR(h2c_buf, param->clear); + IQK_SET_SEGMENT_IQK(h2c_buf, param->segment_iqk); + + hdr_info.sub_cmd_id = SUB_CMD_ID_IQK; + hdr_info.content_size = 1; + hdr_info.ack = _TRUE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + adapter->halmac_state.iqk_state.seq_num = seq_num; + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_IQK); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * ctrl_pwr_tracking_88xx() -trigger FW power tracking + * @adapter : the adapter of halmac + * @opt : power tracking option + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter, + struct halmac_pwr_tracking_option *opt) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_h2c_header_info hdr_info; + struct halmac_pwr_tracking_para *param; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.pwr_trk_state.proc_status; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_TRACE("[TRACE]Wait event(pwr tracking)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + PWR_TRK_SET_TYPE(h2c_buf, opt->type); + PWR_TRK_SET_BBSWING_INDEX(h2c_buf, opt->bbswing_index); + + param = &opt->pwr_tracking_para[HALMAC_RF_PATH_A]; + PWR_TRK_SET_ENABLE_A(h2c_buf, param->enable); + PWR_TRK_SET_TX_PWR_INDEX_A(h2c_buf, param->tx_pwr_index); + PWR_TRK_SET_TSSI_VALUE_A(h2c_buf, param->tssi_value); + PWR_TRK_SET_OFFSET_VALUE_A(h2c_buf, param->pwr_tracking_offset_value); + + PWR_TRK_SET_ENABLE_B(h2c_buf, param->enable); + PWR_TRK_SET_TX_PWR_INDEX_B(h2c_buf, param->tx_pwr_index); + PWR_TRK_SET_TSSI_VALUE_B(h2c_buf, param->tssi_value); + PWR_TRK_SET_OFFSET_VALUE_B(h2c_buf, param->pwr_tracking_offset_value); + + PWR_TRK_SET_ENABLE_C(h2c_buf, param->enable); + PWR_TRK_SET_TX_PWR_INDEX_C(h2c_buf, param->tx_pwr_index); + PWR_TRK_SET_TSSI_VALUE_C(h2c_buf, param->tssi_value); + PWR_TRK_SET_OFFSET_VALUE_C(h2c_buf, param->pwr_tracking_offset_value); + + PWR_TRK_SET_ENABLE_D(h2c_buf, param->enable); + PWR_TRK_SET_TX_PWR_INDEX_D(h2c_buf, param->tx_pwr_index); + PWR_TRK_SET_TSSI_VALUE_D(h2c_buf, param->tssi_value); + PWR_TRK_SET_OFFSET_VALUE_D(h2c_buf, param->pwr_tracking_offset_value); + + hdr_info.sub_cmd_id = SUB_CMD_ID_PWR_TRK; + hdr_info.content_size = 20; + hdr_info.ack = _TRUE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + adapter->halmac_state.pwr_trk_state.seq_num = seq_num; + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_POWER_TRACKING); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_iqk_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status) +{ + *proc_status = adapter->halmac_state.iqk_state.proc_status; + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_pwr_trk_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status) +{ + *proc_status = adapter->halmac_state.pwr_trk_state.proc_status; + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_psd_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status, u8 *data, + u32 *size) +{ + struct halmac_psd_state *state = &adapter->halmac_state.psd_state; + + *proc_status = state->proc_status; + + if (!data) + return HALMAC_RET_NULL_POINTER; + + if (!size) + return HALMAC_RET_NULL_POINTER; + + if (*proc_status == HALMAC_CMD_PROCESS_DONE) { + if (*size < state->data_size) { + *size = state->data_size; + return HALMAC_RET_BUFFER_TOO_SMALL; + } + + *size = state->data_size; + PLTFM_MEMCPY(data, state->data, *size); + } + + return HALMAC_RET_SUCCESS; +} + +/** + * psd_88xx() - trigger fw psd + * @adapter : the adapter of halmac + * @start_psd : start PSD + * @end_psd : end PSD + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +psd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_h2c_header_info hdr_info; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.psd_state.proc_status; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_TRACE("[TRACE]Wait event(psd)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (adapter->halmac_state.psd_state.data) { + PLTFM_FREE(adapter->halmac_state.psd_state.data, + adapter->halmac_state.psd_state.data_size); + adapter->halmac_state.psd_state.data = (u8 *)NULL; + } + + adapter->halmac_state.psd_state.data_size = 0; + adapter->halmac_state.psd_state.seg_size = 0; + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + PSD_SET_START_PSD(h2c_buf, start_psd); + PSD_SET_END_PSD(h2c_buf, end_psd); + + hdr_info.sub_cmd_id = SUB_CMD_ID_PSD; + hdr_info.content_size = 4; + hdr_info.ack = _TRUE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_PSD); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num; + u8 fw_rc; + struct halmac_iqk_state *state = &adapter->halmac_state.iqk_state; + enum halmac_cmd_process_status proc_status; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + + if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) { + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_IQK, proc_status, NULL, 0); + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_IQK, proc_status, &fw_rc, 1); + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num; + u8 fw_rc; + struct halmac_pwr_tracking_state *state; + enum halmac_cmd_process_status proc_status; + + state = &adapter->halmac_state.pwr_trk_state; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + + if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) { + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_POWER_TRACKING, proc_status, + NULL, 0); + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_POWER_TRACKING, proc_status, + &fw_rc, 1); + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seg_id; + u8 seg_size; + u8 seq_num; + u16 total_size; + enum halmac_cmd_process_status proc_status; + struct halmac_psd_state *state = &adapter->halmac_state.psd_state; + + seq_num = (u8)PSD_DATA_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + total_size = (u16)PSD_DATA_GET_TOTAL_SIZE(buf); + seg_id = (u8)PSD_DATA_GET_SEGMENT_ID(buf); + seg_size = (u8)PSD_DATA_GET_SEGMENT_SIZE(buf); + state->data_size = total_size; + + if (!state->data) + state->data = (u8 *)PLTFM_MALLOC(state->data_size); + + if (seg_id == 0) + state->seg_size = seg_size; + + PLTFM_MEMCPY(state->data + seg_id * state->seg_size, + buf + C2H_DATA_OFFSET_88XX, seg_size); + + if (PSD_DATA_GET_END_SEGMENT(buf) == _FALSE) + return HALMAC_RET_SUCCESS; + + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + + PLTFM_EVENT_SIG(HALMAC_FEATURE_PSD, proc_status, state->data, + state->data_size); + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h b/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h new file mode 100644 index 0000000..bd107e6 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_BB_RF_88XX_H_ +#define _HALMAC_BB_RF_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +start_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param); + +enum halmac_ret_status +ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter, + struct halmac_pwr_tracking_option *opt); + +enum halmac_ret_status +get_iqk_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status); + +enum halmac_ret_status +get_pwr_trk_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status); + +enum halmac_ret_status +get_psd_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status, u8 *data, + u32 *size); + +enum halmac_ret_status +psd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd); + +enum halmac_ret_status +get_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +enum halmac_ret_status +get_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +enum halmac_ret_status +get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_BB_RF_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c b/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c new file mode 100644 index 0000000..f598050 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c @@ -0,0 +1,1168 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_cfg_wmac_88xx.h" +#include "halmac_88xx_cfg.h" + +#if HALMAC_88XX_SUPPORT + +#define MAC_CLK_SPEED 80 /* 80M */ + +enum mac_clock_hw_def { + MAC_CLK_HW_DEF_80M = 0, + MAC_CLK_HW_DEF_40M = 1, + MAC_CLK_HW_DEF_20M = 2, +}; + +/** + * cfg_mac_addr_88xx() - config mac address + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @addr : mac address + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr) +{ + u16 mac_addr_h; + u32 mac_addr_l; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (port >= HALMAC_PORTID_NUM) { + PLTFM_MSG_ERR("[ERR]port index >= 5\n"); + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + mac_addr_l = addr->addr_l_h.low; + mac_addr_h = addr->addr_l_h.high; + + mac_addr_l = rtk_le32_to_cpu(mac_addr_l); + mac_addr_h = rtk_le16_to_cpu(mac_addr_h); + + switch (port) { + case HALMAC_PORTID0: + HALMAC_REG_W32(REG_MACID, mac_addr_l); + HALMAC_REG_W16(REG_MACID + 4, mac_addr_h); + break; + case HALMAC_PORTID1: + HALMAC_REG_W32(REG_MACID1, mac_addr_l); + HALMAC_REG_W16(REG_MACID1 + 4, mac_addr_h); + break; + case HALMAC_PORTID2: + HALMAC_REG_W32(REG_MACID2, mac_addr_l); + HALMAC_REG_W16(REG_MACID2 + 4, mac_addr_h); + break; + case HALMAC_PORTID3: + HALMAC_REG_W32(REG_MACID3, mac_addr_l); + HALMAC_REG_W16(REG_MACID3 + 4, mac_addr_h); + break; + case HALMAC_PORTID4: + HALMAC_REG_W32(REG_MACID4, mac_addr_l); + HALMAC_REG_W16(REG_MACID4 + 4, mac_addr_h); + break; + default: + break; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_bssid_88xx() - config BSSID + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @addr : bssid + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr) +{ + u16 bssid_addr_h; + u32 bssid_addr_l; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (port >= HALMAC_PORTID_NUM) { + PLTFM_MSG_ERR("[ERR]port index > 5\n"); + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + bssid_addr_l = addr->addr_l_h.low; + bssid_addr_h = addr->addr_l_h.high; + + bssid_addr_l = rtk_le32_to_cpu(bssid_addr_l); + bssid_addr_h = rtk_le16_to_cpu(bssid_addr_h); + + switch (port) { + case HALMAC_PORTID0: + HALMAC_REG_W32(REG_BSSID, bssid_addr_l); + HALMAC_REG_W16(REG_BSSID + 4, bssid_addr_h); + break; + case HALMAC_PORTID1: + HALMAC_REG_W32(REG_BSSID1, bssid_addr_l); + HALMAC_REG_W16(REG_BSSID1 + 4, bssid_addr_h); + break; + case HALMAC_PORTID2: + HALMAC_REG_W32(REG_BSSID2, bssid_addr_l); + HALMAC_REG_W16(REG_BSSID2 + 4, bssid_addr_h); + break; + case HALMAC_PORTID3: + HALMAC_REG_W32(REG_BSSID3, bssid_addr_l); + HALMAC_REG_W16(REG_BSSID3 + 4, bssid_addr_h); + break; + case HALMAC_PORTID4: + HALMAC_REG_W32(REG_BSSID4, bssid_addr_l); + HALMAC_REG_W16(REG_BSSID4 + 4, bssid_addr_h); + break; + default: + break; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_transmitter_addr_88xx() - config transmitter address + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @addr : + * Author : Alan + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr) +{ + u16 mac_addr_h; + u32 mac_addr_l; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (port >= HALMAC_PORTID_NUM) { + PLTFM_MSG_ERR("[ERR]port index > 5\n"); + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + mac_addr_l = addr->addr_l_h.low; + mac_addr_h = addr->addr_l_h.high; + + mac_addr_l = rtk_le32_to_cpu(mac_addr_l); + mac_addr_h = rtk_le16_to_cpu(mac_addr_h); + + switch (port) { + case HALMAC_PORTID0: + HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_0, mac_addr_l); + HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_0 + 4, mac_addr_h); + break; + case HALMAC_PORTID1: + HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_1, mac_addr_l); + HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_1 + 4, mac_addr_h); + break; + case HALMAC_PORTID2: + HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_2, mac_addr_l); + HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_2 + 4, mac_addr_h); + break; + case HALMAC_PORTID3: + HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_3, mac_addr_l); + HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_3 + 4, mac_addr_h); + break; + case HALMAC_PORTID4: + HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_4, mac_addr_l); + HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_4 + 4, mac_addr_h); + break; + default: + break; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_net_type_88xx() - config network type + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @addr : mac address + * Author : Alan + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +cfg_net_type_88xx(struct halmac_adapter *adapter, u8 port, + enum halmac_network_type_select net_type) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 value8 = 0; + u8 net_type_tmp = 0; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (net_type == HALMAC_NETWORK_AP) { + if (port >= HALMAC_PORTID1) { + PLTFM_MSG_ERR("[ERR]AP port > 1\n"); + return HALMAC_RET_PORT_NOT_SUPPORT; + } + } + + switch (port) { + case HALMAC_PORTID0: + net_type_tmp = net_type; + value8 = ((HALMAC_REG_R8(REG_CR + 2) & 0xFC) | net_type_tmp); + HALMAC_REG_W8(REG_CR + 2, value8); + break; + case HALMAC_PORTID1: + net_type_tmp = (net_type << 2); + value8 = ((HALMAC_REG_R8(REG_CR + 2) & 0xF3) | net_type_tmp); + HALMAC_REG_W8(REG_CR + 2, value8); + break; + case HALMAC_PORTID2: + net_type_tmp = net_type; + value8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xFC) | net_type_tmp); + HALMAC_REG_W8(REG_CR_EXT, value8); + break; + case HALMAC_PORTID3: + net_type_tmp = (net_type << 2); + value8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xF3) | net_type_tmp); + HALMAC_REG_W8(REG_CR_EXT, value8); + break; + case HALMAC_PORTID4: + net_type_tmp = (net_type << 4); + value8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xCF) | net_type_tmp); + HALMAC_REG_W8(REG_CR_EXT, value8); + break; + default: + break; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_tsf_rst_88xx() - tsf reset + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * Author : Alan + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +cfg_tsf_rst_88xx(struct halmac_adapter *adapter, u8 port) +{ + u8 tsf_rst = 0; + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (port) { + case HALMAC_PORTID0: + tsf_rst = BIT_TSFTR_RST; + break; + case HALMAC_PORTID1: + tsf_rst = BIT_TSFTR_CLI0_RST; + break; + case HALMAC_PORTID2: + tsf_rst = BIT_TSFTR_CLI1_RST; + break; + case HALMAC_PORTID3: + tsf_rst = BIT_TSFTR_CLI2_RST; + break; + case HALMAC_PORTID4: + tsf_rst = BIT_TSFTR_CLI3_RST; + break; + default: + break; + } + + value8 = HALMAC_REG_R8(REG_DUAL_TSF_RST); + HALMAC_REG_W8(REG_DUAL_TSF_RST, value8 | tsf_rst); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_bcn_space_88xx() - config beacon space + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @bcn_space : beacon space + * Author : Alan + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +cfg_bcn_space_88xx(struct halmac_adapter *adapter, u8 port, u32 bcn_space) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u16 bcn_space_real = 0; + u16 value16 = 0; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + bcn_space_real = ((u16)bcn_space); + + switch (port) { + case HALMAC_PORTID0: + HALMAC_REG_W16(REG_MBSSID_BCN_SPACE, bcn_space_real); + break; + case HALMAC_PORTID1: + value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE + 2) & 0xF000; + value16 |= bcn_space_real; + HALMAC_REG_W16(REG_MBSSID_BCN_SPACE + 2, value16); + break; + case HALMAC_PORTID2: + value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE2) & 0xF000; + value16 |= bcn_space_real; + HALMAC_REG_W16(REG_MBSSID_BCN_SPACE2, value16); + break; + case HALMAC_PORTID3: + value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE2 + 2) & 0xF000; + value16 |= bcn_space_real; + HALMAC_REG_W16(REG_MBSSID_BCN_SPACE2 + 2, value16); + break; + case HALMAC_PORTID4: + value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE3) & 0xF000; + value16 |= bcn_space_real; + HALMAC_REG_W16(REG_MBSSID_BCN_SPACE3, value16); + break; + default: + break; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * rw_bcn_ctrl_88xx() - r/w beacon control + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @write_en : 1->write beacon function 0->read beacon function + * @pBcn_ctrl : beacon control info + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en, + struct halmac_bcn_ctrl *ctrl) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 ctrl_value = 0; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (write_en) { + if (ctrl->dis_rx_bssid_fit == _TRUE) + ctrl_value |= BIT_DIS_RX_BSSID_FIT; + + if (ctrl->en_txbcn_rpt == _TRUE) + ctrl_value |= BIT_P0_EN_TXBCN_RPT; + + if (ctrl->dis_tsf_udt == _TRUE) + ctrl_value |= BIT_DIS_TSF_UDT; + + if (ctrl->en_bcn == _TRUE) + ctrl_value |= BIT_EN_BCN_FUNCTION; + + if (ctrl->en_rxbcn_rpt == _TRUE) + ctrl_value |= BIT_P0_EN_RXBCN_RPT; + + if (ctrl->en_p2p_ctwin == _TRUE) + ctrl_value |= BIT_EN_P2P_CTWINDOW; + + if (ctrl->en_p2p_bcn_area == _TRUE) + ctrl_value |= BIT_EN_P2P_BCNQ_AREA; + + switch (port) { + case HALMAC_PORTID0: + HALMAC_REG_W8(REG_BCN_CTRL, ctrl_value); + break; + + case HALMAC_PORTID1: + HALMAC_REG_W8(REG_BCN_CTRL_CLINT0, ctrl_value); + break; + + case HALMAC_PORTID2: + HALMAC_REG_W8(REG_BCN_CTRL_CLINT1, ctrl_value); + break; + + case HALMAC_PORTID3: + HALMAC_REG_W8(REG_BCN_CTRL_CLINT2, ctrl_value); + break; + + case HALMAC_PORTID4: + HALMAC_REG_W8(REG_BCN_CTRL_CLINT3, ctrl_value); + break; + + default: + break; + } + + } else { + switch (port) { + case HALMAC_PORTID0: + ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL); + break; + + case HALMAC_PORTID1: + ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT0); + break; + + case HALMAC_PORTID2: + ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT1); + break; + + case HALMAC_PORTID3: + ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT2); + break; + + case HALMAC_PORTID4: + ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT3); + break; + + default: + break; + } + + if (ctrl_value & BIT_EN_P2P_BCNQ_AREA) + ctrl->en_p2p_bcn_area = _TRUE; + else + ctrl->en_p2p_bcn_area = _FALSE; + + if (ctrl_value & BIT_EN_P2P_CTWINDOW) + ctrl->en_p2p_ctwin = _TRUE; + else + ctrl->en_p2p_ctwin = _FALSE; + + if (ctrl_value & BIT_P0_EN_RXBCN_RPT) + ctrl->en_rxbcn_rpt = _TRUE; + else + ctrl->en_rxbcn_rpt = _FALSE; + + if (ctrl_value & BIT_EN_BCN_FUNCTION) + ctrl->en_bcn = _TRUE; + else + ctrl->en_bcn = _FALSE; + + if (ctrl_value & BIT_DIS_TSF_UDT) + ctrl->dis_tsf_udt = _TRUE; + else + ctrl->dis_tsf_udt = _FALSE; + + if (ctrl_value & BIT_P0_EN_TXBCN_RPT) + ctrl->en_txbcn_rpt = _TRUE; + else + ctrl->en_txbcn_rpt = _FALSE; + + if (ctrl_value & BIT_DIS_RX_BSSID_FIT) + ctrl->dis_rx_bssid_fit = _TRUE; + else + ctrl->dis_rx_bssid_fit = _FALSE; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_multicast_addr_88xx() - config multicast address + * @adapter : the adapter of halmac + * @addr : multicast address + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_multicast_addr_88xx(struct halmac_adapter *adapter, + union halmac_wlan_addr *addr) +{ + u16 addr_h; + u32 addr_l; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + addr_l = addr->addr_l_h.low; + addr_h = addr->addr_l_h.high; + + addr_l = rtk_le32_to_cpu(addr_l); + addr_h = rtk_le16_to_cpu(addr_h); + + HALMAC_REG_W32(REG_MAR, addr_l); + HALMAC_REG_W16(REG_MAR + 4, addr_h); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_operation_mode_88xx() - config operation mode + * @adapter : the adapter of halmac + * @mode : 802.11 standard(b/g/n/ac) + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_operation_mode_88xx(struct halmac_adapter *adapter, + enum halmac_wireless_mode mode) +{ + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_ch_bw_88xx() - config channel & bandwidth + * @adapter : the adapter of halmac + * @ch : WLAN channel, support 2.4G & 5G + * @idx : primary channel index, idx1, idx2, idx3, idx4 + * @bw : band width, 20, 40, 80, 160, 5 ,10 + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_ch_bw_88xx(struct halmac_adapter *adapter, u8 ch, + enum halmac_pri_ch_idx idx, enum halmac_bw bw) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + cfg_pri_ch_idx_88xx(adapter, idx); + cfg_bw_88xx(adapter, bw); + cfg_ch_88xx(adapter, ch); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +cfg_ch_88xx(struct halmac_adapter *adapter, u8 ch) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + value8 = HALMAC_REG_R8(REG_CCK_CHECK); + value8 = value8 & (~(BIT(7))); + + if (ch > 35) + value8 = value8 | BIT(7); + + HALMAC_REG_W8(REG_CCK_CHECK, value8); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +cfg_pri_ch_idx_88xx(struct halmac_adapter *adapter, enum halmac_pri_ch_idx idx) +{ + u8 txsc40 = 0, txsc20 = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + txsc20 = idx; + if (txsc20 == HALMAC_CH_IDX_1 || txsc20 == HALMAC_CH_IDX_3) + txsc40 = 9; + else + txsc40 = 10; + + HALMAC_REG_W8(REG_DATA_SC, BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_bw_88xx() - config bandwidth + * @adapter : the adapter of halmac + * @bw : band width, 20, 40, 80, 160, 5 ,10 + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw) +{ + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + value32 = HALMAC_REG_R32(REG_WMAC_TRXPTCL_CTL); + value32 = value32 & (~(BIT(7) | BIT(8))); + + switch (bw) { + case HALMAC_BW_80: + value32 = value32 | BIT(7); + break; + case HALMAC_BW_40: + value32 = value32 | BIT(8); + break; + case HALMAC_BW_20: + case HALMAC_BW_10: + case HALMAC_BW_5: + break; + default: + break; + } + + HALMAC_REG_W32(REG_WMAC_TRXPTCL_CTL, value32); + + /* TODO:Move to change mac clk api later... */ + value32 = HALMAC_REG_R32(REG_AFE_CTRL1) & ~(BIT(20) | BIT(21)); + value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL); + HALMAC_REG_W32(REG_AFE_CTRL1, value32); + + HALMAC_REG_W8(REG_USTIME_TSF, MAC_CLK_SPEED); + HALMAC_REG_W8(REG_USTIME_EDCA, MAC_CLK_SPEED); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +void +enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable) +{ + u8 value8; + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (enable == 1) { + value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN); + value8 = value8 | BIT(0) | BIT(1); + HALMAC_REG_W8(REG_SYS_FUNC_EN, value8); + + value8 = HALMAC_REG_R8(REG_RF_CTRL); + value8 = value8 | BIT(0) | BIT(1) | BIT(2); + HALMAC_REG_W8(REG_RF_CTRL, value8); + + value32 = HALMAC_REG_R32(REG_WLRF1); + value32 = value32 | BIT(24) | BIT(25) | BIT(26); + HALMAC_REG_W32(REG_WLRF1, value32); + } else { + value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN); + value8 = value8 & (~(BIT(0) | BIT(1))); + HALMAC_REG_W8(REG_SYS_FUNC_EN, value8); + + value8 = HALMAC_REG_R8(REG_RF_CTRL); + value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2))); + HALMAC_REG_W8(REG_RF_CTRL, value8); + + value32 = HALMAC_REG_R32(REG_WLRF1); + value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26))); + HALMAC_REG_W32(REG_WLRF1, value32); + } +} + +/** + * cfg_la_mode_88xx() - config la mode + * @adapter : the adapter of halmac + * @mode : + * disable : no TXFF space reserved for LA debug + * partial : partial TXFF space is reserved for LA debug + * full : all TXFF space is reserved for LA debug + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_la_mode_88xx(struct halmac_adapter *adapter, enum halmac_la_mode mode) +{ + if (adapter->api_registry.la_mode_en == 0) + return HALMAC_RET_NOT_SUPPORT; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + adapter->txff_alloc.la_mode = mode; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_rxfifo_expand_mode_88xx() - rx fifo expanding + * @adapter : the adapter of halmac + * @mode : + * disable : normal mode + * 1 block : Rx FIFO + 1 FIFO block; Tx fifo - 1 FIFO block + * 2 block : Rx FIFO + 2 FIFO block; Tx fifo - 2 FIFO block + * 3 block : Rx FIFO + 3 FIFO block; Tx fifo - 3 FIFO block + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_rxfifo_expand_mode_88xx(struct halmac_adapter *adapter, + enum halmac_rx_fifo_expanding_mode mode) +{ + if (adapter->api_registry.rx_exp_en == 0) + return HALMAC_RET_NOT_SUPPORT; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + adapter->txff_alloc.rx_fifo_exp_mode = mode; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +config_security_88xx(struct halmac_adapter *adapter, + struct halmac_security_setting *setting) +{ + u8 sec_cfg; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + HALMAC_REG_W16(REG_CR, (u16)(HALMAC_REG_R16(REG_CR) | BIT_MAC_SEC_EN)); + + if (setting->compare_keyid == 1) { + sec_cfg = HALMAC_REG_R8(REG_SECCFG + 1) | BIT(0); + HALMAC_REG_W8(REG_SECCFG + 1, sec_cfg); + adapter->hw_cfg_info.chk_security_keyid = 1; + } else { + adapter->hw_cfg_info.chk_security_keyid = 0; + } + + sec_cfg = HALMAC_REG_R8(REG_SECCFG); + + /* BC/MC uses default key */ + /* cam entry 0~3, kei id = 0 -> entry0, kei id = 1 -> entry1... */ + sec_cfg |= (BIT_TXBCUSEDK | BIT_RXBCUSEDK); + + if (setting->tx_encryption == 1) + sec_cfg |= BIT_TXENC; + else + sec_cfg &= ~BIT_TXENC; + + if (setting->rx_decryption == 1) + sec_cfg |= BIT_RXDEC; + else + sec_cfg &= ~BIT_RXDEC; + + HALMAC_REG_W8(REG_SECCFG, sec_cfg); + + if (setting->bip_enable == 1) { + if (adapter->chip_id == HALMAC_CHIP_ID_8822B) + return HALMAC_RET_BIP_NO_SUPPORT; +#if HALMAC_8821C_SUPPORT + sec_cfg = HALMAC_REG_R8(REG_WSEC_OPTION + 2); + + if (setting->tx_encryption == 1) + sec_cfg |= (BIT(3) | BIT(5)); + else + sec_cfg &= ~(BIT(3) | BIT(5)); + + if (setting->rx_decryption == 1) + sec_cfg |= (BIT(4) | BIT(6)); + else + sec_cfg &= ~(BIT(4) | BIT(6)); + + HALMAC_REG_W8(REG_WSEC_OPTION + 2, sec_cfg); +#endif + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +u8 +get_used_cam_entry_num_88xx(struct halmac_adapter *adapter, + enum hal_security_type sec_type) +{ + u8 entry_num; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (sec_type) { + case HAL_SECURITY_TYPE_WEP40: + case HAL_SECURITY_TYPE_WEP104: + case HAL_SECURITY_TYPE_TKIP: + case HAL_SECURITY_TYPE_AES128: + case HAL_SECURITY_TYPE_GCMP128: + case HAL_SECURITY_TYPE_GCMSMS4: + case HAL_SECURITY_TYPE_BIP: + entry_num = 1; + break; + case HAL_SECURITY_TYPE_WAPI: + case HAL_SECURITY_TYPE_AES256: + case HAL_SECURITY_TYPE_GCMP256: + entry_num = 2; + break; + default: + entry_num = 0; + break; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return entry_num; +} + +enum halmac_ret_status +write_cam_88xx(struct halmac_adapter *adapter, u32 idx, + struct halmac_cam_entry_info *info) +{ + u32 i; + u32 cmd = 0x80010000; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + struct halmac_cam_entry_format *fmt = NULL; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (idx >= adapter->hw_cfg_info.cam_entry_num) + return HALMAC_RET_ENTRY_INDEX_ERROR; + + if (info->key_id > 3) + return HALMAC_RET_FAIL; + + fmt = (struct halmac_cam_entry_format *)PLTFM_MALLOC(sizeof(*fmt)); + if (!fmt) + return HALMAC_RET_NULL_POINTER; + PLTFM_MEMSET(fmt, 0x00, sizeof(*fmt)); + + if (adapter->hw_cfg_info.chk_security_keyid == 1) + fmt->key_id = info->key_id; + fmt->valid = info->valid; + PLTFM_MEMCPY(fmt->mac_address, info->mac_address, 6); + PLTFM_MEMCPY(fmt->key, info->key, 16); + + switch (info->security_type) { + case HAL_SECURITY_TYPE_NONE: + fmt->type = 0; + break; + case HAL_SECURITY_TYPE_WEP40: + fmt->type = 1; + break; + case HAL_SECURITY_TYPE_WEP104: + fmt->type = 5; + break; + case HAL_SECURITY_TYPE_TKIP: + fmt->type = 2; + break; + case HAL_SECURITY_TYPE_AES128: + fmt->type = 4; + break; + case HAL_SECURITY_TYPE_WAPI: + fmt->type = 6; + break; + case HAL_SECURITY_TYPE_AES256: + fmt->type = 4; + fmt->ext_sectype = 1; + break; + case HAL_SECURITY_TYPE_GCMP128: + fmt->type = 7; + break; + case HAL_SECURITY_TYPE_GCMP256: + case HAL_SECURITY_TYPE_GCMSMS4: + fmt->type = 7; + fmt->ext_sectype = 1; + break; + case HAL_SECURITY_TYPE_BIP: + fmt->type = (info->unicast == 1) ? 4 : 0; + fmt->mgnt = 1; + fmt->grp = (info->unicast == 1) ? 0 : 1; + break; + default: + PLTFM_FREE(fmt, sizeof(*fmt)); + return HALMAC_RET_FAIL; + } + + for (i = 0; i < 8; i++) { + HALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i)); + HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i)); + } + + if (info->security_type == HAL_SECURITY_TYPE_WAPI || + info->security_type == HAL_SECURITY_TYPE_AES256 || + info->security_type == HAL_SECURITY_TYPE_GCMP256 || + info->security_type == HAL_SECURITY_TYPE_GCMSMS4) { + fmt->mic = 1; + PLTFM_MEMCPY(fmt->key, info->key_ext, 16); + idx++; + for (i = 0; i < 8; i++) { + HALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i)); + HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i)); + } + } + + PLTFM_FREE(fmt, sizeof(*fmt)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +read_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx, + struct halmac_cam_entry_format *content) +{ + u32 i; + u32 cmd = 0x80000000; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (idx >= adapter->hw_cfg_info.cam_entry_num) + return HALMAC_RET_ENTRY_INDEX_ERROR; + + for (i = 0; i < 8; i++) { + HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i)); + *((u32 *)content + i) = HALMAC_REG_R32(REG_CAMREAD); + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +clear_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx) +{ + u32 i; + u32 cmd = 0x80010000; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + struct halmac_cam_entry_format *fmt = NULL; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (idx >= adapter->hw_cfg_info.cam_entry_num) + return HALMAC_RET_ENTRY_INDEX_ERROR; + + fmt = (struct halmac_cam_entry_format *)PLTFM_MALLOC(sizeof(*fmt)); + if (!fmt) + return HALMAC_RET_NULL_POINTER; + PLTFM_MEMSET(fmt, 0x00, sizeof(*fmt)); + + for (i = 0; i < 8; i++) { + HALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i)); + HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i)); + } + + PLTFM_FREE(fmt, sizeof(*fmt)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +void +rx_shift_88xx(struct halmac_adapter *adapter, u8 enable) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + value8 = HALMAC_REG_R8(REG_TXDMA_PQ_MAP); + + if (enable == 1) + HALMAC_REG_W8(REG_TXDMA_PQ_MAP, value8 | BIT(1)); + else + HALMAC_REG_W8(REG_TXDMA_PQ_MAP, value8 & ~(BIT(1))); +} + +/** + * cfg_edca_para_88xx() - config edca parameter + * @adapter : the adapter of halmac + * @acq_id : VO/VI/BE/BK + * @param : aifs, cw, txop limit + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_edca_para_88xx(struct halmac_adapter *adapter, enum halmac_acq_id acq_id, + struct halmac_edca_para *param) +{ + u32 offset; + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (acq_id) { + case HALMAC_ACQ_ID_VO: + offset = REG_EDCA_VO_PARAM; + break; + case HALMAC_ACQ_ID_VI: + offset = REG_EDCA_VI_PARAM; + break; + case HALMAC_ACQ_ID_BE: + offset = REG_EDCA_BE_PARAM; + break; + case HALMAC_ACQ_ID_BK: + offset = REG_EDCA_BK_PARAM; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + param->txop_limit &= 0x7FF; + value32 = (param->aifs) | (param->cw << 8) | (param->txop_limit << 16); + + HALMAC_REG_W32(offset, value32); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +void +rx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + value8 = HALMAC_REG_R8(REG_RCR + 2); + + if (enable == _TRUE) + HALMAC_REG_W8(REG_RCR + 2, value8 & ~(BIT(3))); + else + HALMAC_REG_W8(REG_RCR + 2, value8 | BIT(3)); +} + +enum halmac_ret_status +rx_cut_amsdu_cfg_88xx(struct halmac_adapter *adapter, + struct halmac_cut_amsdu_cfg *cfg) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +enum halmac_ret_status +fast_edca_cfg_88xx(struct halmac_adapter *adapter, + struct halmac_fast_edca_cfg *cfg) +{ + u16 value16; + u32 offset; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (cfg->acq_id) { + case HALMAC_ACQ_ID_VO: + offset = REG_FAST_EDCA_VOVI_SETTING; + break; + case HALMAC_ACQ_ID_VI: + offset = REG_FAST_EDCA_VOVI_SETTING + 2; + break; + case HALMAC_ACQ_ID_BE: + offset = REG_FAST_EDCA_BEBK_SETTING; + break; + case HALMAC_ACQ_ID_BK: + offset = REG_FAST_EDCA_BEBK_SETTING + 2; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + value16 = HALMAC_REG_R16(offset); + value16 &= 0xFF; + value16 = value16 | (cfg->queue_to << 8); + + HALMAC_REG_W16(offset, value16); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * get_mac_addr_88xx() - get mac address + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @addr : mac address + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr) +{ + u16 mac_addr_h; + u32 mac_addr_l; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (port >= HALMAC_PORTID_NUM) { + PLTFM_MSG_ERR("[ERR]port index >= 5\n"); + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + switch (port) { + case HALMAC_PORTID0: + mac_addr_l = HALMAC_REG_R32(REG_MACID); + mac_addr_h = HALMAC_REG_R16(REG_MACID + 4); + break; + case HALMAC_PORTID1: + mac_addr_l = HALMAC_REG_R32(REG_MACID1); + mac_addr_h = HALMAC_REG_R16(REG_MACID1 + 4); + break; + case HALMAC_PORTID2: + mac_addr_l = HALMAC_REG_R32(REG_MACID2); + mac_addr_h = HALMAC_REG_R16(REG_MACID2 + 4); + break; + case HALMAC_PORTID3: + mac_addr_l = HALMAC_REG_R32(REG_MACID3); + mac_addr_h = HALMAC_REG_R16(REG_MACID3 + 4); + break; + case HALMAC_PORTID4: + mac_addr_l = HALMAC_REG_R32(REG_MACID4); + mac_addr_h = HALMAC_REG_R16(REG_MACID4 + 4); + break; + default: + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + mac_addr_l = rtk_le32_to_cpu(mac_addr_l); + mac_addr_h = rtk_le16_to_cpu(mac_addr_h); + + addr->addr_l_h.low = mac_addr_l; + addr->addr_l_h.high = mac_addr_h; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h b/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h new file mode 100644 index 0000000..0a6b4e1 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h @@ -0,0 +1,123 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_CFG_WMAC_88XX_H_ +#define _HALMAC_CFG_WMAC_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + +enum halmac_ret_status +cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + +enum halmac_ret_status +cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + +enum halmac_ret_status +cfg_net_type_88xx(struct halmac_adapter *adapter, u8 port, + enum halmac_network_type_select net_type); + +enum halmac_ret_status +cfg_tsf_rst_88xx(struct halmac_adapter *adapter, u8 port); + +enum halmac_ret_status +cfg_bcn_space_88xx(struct halmac_adapter *adapter, u8 port, u32 bcn_space); + +enum halmac_ret_status +rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en, + struct halmac_bcn_ctrl *ctrl); + +enum halmac_ret_status +cfg_multicast_addr_88xx(struct halmac_adapter *adapter, + union halmac_wlan_addr *addr); + +enum halmac_ret_status +cfg_operation_mode_88xx(struct halmac_adapter *adapter, + enum halmac_wireless_mode mode); + +enum halmac_ret_status +cfg_ch_bw_88xx(struct halmac_adapter *adapter, u8 ch, + enum halmac_pri_ch_idx idx, enum halmac_bw bw); + +enum halmac_ret_status +cfg_ch_88xx(struct halmac_adapter *adapter, u8 ch); + +enum halmac_ret_status +cfg_pri_ch_idx_88xx(struct halmac_adapter *adapter, enum halmac_pri_ch_idx idx); + +enum halmac_ret_status +cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw); + +void +enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable); + +enum halmac_ret_status +cfg_la_mode_88xx(struct halmac_adapter *adapter, enum halmac_la_mode mode); + +enum halmac_ret_status +cfg_rxfifo_expand_mode_88xx(struct halmac_adapter *adapter, + enum halmac_rx_fifo_expanding_mode mode); + +enum halmac_ret_status +config_security_88xx(struct halmac_adapter *adapter, + struct halmac_security_setting *setting); + +u8 +get_used_cam_entry_num_88xx(struct halmac_adapter *adapter, + enum hal_security_type sec_type); + +enum halmac_ret_status +write_cam_88xx(struct halmac_adapter *adapter, u32 idx, + struct halmac_cam_entry_info *info); + +enum halmac_ret_status +read_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx, + struct halmac_cam_entry_format *content); + +enum halmac_ret_status +clear_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx); + +void +rx_shift_88xx(struct halmac_adapter *adapter, u8 enable); + +enum halmac_ret_status +cfg_edca_para_88xx(struct halmac_adapter *adapter, enum halmac_acq_id acq_id, + struct halmac_edca_para *param); + +void +rx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable); + +enum halmac_ret_status +rx_cut_amsdu_cfg_88xx(struct halmac_adapter *adapter, + struct halmac_cut_amsdu_cfg *cfg); + +enum halmac_ret_status +fast_edca_cfg_88xx(struct halmac_adapter *adapter, + struct halmac_fast_edca_cfg *cfg); + +enum halmac_ret_status +get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + +#endif/* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_CFG_WMAC_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_common_88xx.c b/hal/halmac/halmac_88xx/halmac_common_88xx.c new file mode 100644 index 0000000..6e08060 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_common_88xx.c @@ -0,0 +1,2858 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_common_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_init_88xx.h" +#include "halmac_cfg_wmac_88xx.h" +#include "halmac_efuse_88xx.h" +#include "halmac_bb_rf_88xx.h" +#include "halmac_usb_88xx.h" +#include "halmac_sdio_88xx.h" +#include "halmac_pcie_88xx.h" +#include "halmac_mimo_88xx.h" + +#if HALMAC_88XX_SUPPORT + +#define CFG_PARAM_H2C_INFO_SIZE 12 +#define ORIGINAL_H2C_CMD_SIZE 8 + +#define WLHDR_PROT_VER 0 + +#define WLHDR_TYPE_MGMT 0 +#define WLHDR_TYPE_CTRL 1 +#define WLHDR_TYPE_DATA 2 + +/* mgmt frame */ +#define WLHDR_SUB_TYPE_ASSOC_REQ 0 +#define WLHDR_SUB_TYPE_ASSOC_RSPNS 1 +#define WLHDR_SUB_TYPE_REASSOC_REQ 2 +#define WLHDR_SUB_TYPE_REASSOC_RSPNS 3 +#define WLHDR_SUB_TYPE_PROBE_REQ 4 +#define WLHDR_SUB_TYPE_PROBE_RSPNS 5 +#define WLHDR_SUB_TYPE_BCN 8 +#define WLHDR_SUB_TYPE_DISASSOC 10 +#define WLHDR_SUB_TYPE_AUTH 11 +#define WLHDR_SUB_TYPE_DEAUTH 12 +#define WLHDR_SUB_TYPE_ACTION 13 +#define WLHDR_SUB_TYPE_ACTION_NOACK 14 + +/* ctrl frame */ +#define WLHDR_SUB_TYPE_BF_RPT_POLL 4 +#define WLHDR_SUB_TYPE_NDPA 5 + +/* data frame */ +#define WLHDR_SUB_TYPE_DATA 0 +#define WLHDR_SUB_TYPE_NULL 4 +#define WLHDR_SUB_TYPE_QOS_DATA 8 +#define WLHDR_SUB_TYPE_QOS_NULL 12 + +#define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 + +struct wlhdr_frame_ctrl { + u16 protocol:2; + u16 type:2; + u16 sub_type:4; + u16 to_ds:1; + u16 from_ds:1; + u16 more_frag:1; + u16 retry:1; + u16 pwr_mgmt:1; + u16 more_data:1; + u16 protect_frame:1; + u16 order:1; +}; + +static enum halmac_ret_status +parse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_c2h_dbg_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_h2c_ack_cfg_param_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_h2c_ack_update_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, + u32 size); + +static enum halmac_ret_status +get_h2c_ack_run_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +malloc_cfg_param_buf_88xx(struct halmac_adapter *adapter, u8 full_fifo); + +static enum halmac_cmd_construct_state +cfg_param_cmd_cnstr_state_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +proc_cfg_param_88xx(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *param, u8 full_fifo); + +static enum halmac_ret_status +send_cfg_param_h2c_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +cnv_cfg_param_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state); + +static enum halmac_ret_status +add_param_buf_88xx(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *param, u8 *buf, + u8 *end_cmd); + +static enum halmac_ret_status +gen_cfg_param_h2c_88xx(struct halmac_adapter *adapter, u8 *buff); + +static enum halmac_ret_status +send_h2c_update_packet_88xx(struct halmac_adapter *adapter, + enum halmac_packet_id pkt_id, u8 *pkt, u32 size); + +static enum halmac_ret_status +send_bt_coex_cmd_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u8 ack); + +static enum halmac_ret_status +read_buf_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + enum hal_fifo_sel sel, u8 *data); + +static enum halmac_cmd_construct_state +scan_cmd_cnstr_state_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +cnv_scan_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state); + +static enum halmac_ret_status +proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter, + struct halmac_ch_switch_option *opt); + +static enum halmac_ret_status +proc_p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info); + +static enum halmac_ret_status +get_cfg_param_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status); + +static enum halmac_ret_status +get_ch_switch_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status); + +static enum halmac_ret_status +get_update_packet_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status); + +static enum halmac_ret_status +pwr_sub_seq_parser_88xx(struct halmac_adapter *adapter, u8 cut, u8 intf, + struct halmac_wlan_pwr_cfg *cmd); + +static void +pwr_state_88xx(struct halmac_adapter *adapter, enum halmac_mac_power *state); + +static enum halmac_ret_status +pwr_cmd_polling_88xx(struct halmac_adapter *adapter, + struct halmac_wlan_pwr_cfg *cmd); + +static void +get_pq_mapping_88xx(struct halmac_adapter *adapter, + struct halmac_rqpn_map *mapping); + +static void +dump_reg_sdio_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +wlhdr_valid_88xx(struct halmac_adapter *adapter, u8 *buf); + +static u8 +wlhdr_mgmt_valid_88xx(struct halmac_adapter *adapter, + struct wlhdr_frame_ctrl *wlhdr); + +static u8 +wlhdr_ctrl_valid_88xx(struct halmac_adapter *adapter, + struct wlhdr_frame_ctrl *wlhdr); + +static u8 +wlhdr_data_valid_88xx(struct halmac_adapter *adapter, + struct wlhdr_frame_ctrl *wlhdr); + +static void +dump_reg_88xx(struct halmac_adapter *adapter); + +/** + * ofld_func_cfg_88xx() - config offload function + * @adapter : the adapter of halmac + * @info : offload function information + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +ofld_func_cfg_88xx(struct halmac_adapter *adapter, + struct halmac_ofld_func_info *info) +{ + if (adapter->intf == HALMAC_INTERFACE_SDIO && + info->rsvd_pg_drv_buf_max_sz > SDIO_TX_MAX_SIZE_88XX) + return HALMAC_RET_FAIL; + + adapter->pltfm_info.malloc_size = info->halmac_malloc_max_sz; + adapter->pltfm_info.rsvd_pg_size = info->rsvd_pg_drv_buf_max_sz; + + return HALMAC_RET_SUCCESS; +} + +/** + * dl_drv_rsvd_page_88xx() - download packet to rsvd page + * @adapter : the adapter of halmac + * @pg_offset : page offset of driver's rsvd page + * @halmac_buf : data to be downloaded, tx_desc is not included + * @halmac_size : data size to be downloaded + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +dl_drv_rsvd_page_88xx(struct halmac_adapter *adapter, u8 pg_offset, u8 *buf, + u32 size) +{ + enum halmac_ret_status status; + u32 pg_size; + u32 pg_num = 0; + u16 pg_addr = 0; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + pg_size = adapter->hw_cfg_info.page_size; + pg_num = size / pg_size + ((size & (pg_size - 1)) ? 1 : 0); + if (pg_offset + pg_num > adapter->txff_alloc.rsvd_drv_pg_num) { + PLTFM_MSG_ERR("[ERR] pkt overflow!!\n"); + return HALMAC_RET_DRV_DL_ERR; + } + + pg_addr = adapter->txff_alloc.rsvd_drv_addr + pg_offset; + + status = dl_rsvd_page_88xx(adapter, pg_addr, buf, size); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dl rsvd page fail!!\n"); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +dl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf, + u32 size) +{ + u8 restore[2]; + u8 value8; + u16 rsvd_pg_head; + u32 cnt; + enum halmac_rsvd_pg_state *state = &adapter->halmac_state.rsvd_pg_state; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (size == 0) { + PLTFM_MSG_TRACE("[TRACE]pkt size = 0\n"); + return HALMAC_RET_ZERO_LEN_RSVD_PACKET; + } + + if (*state == HALMAC_RSVD_PG_STATE_BUSY) + return HALMAC_RET_BUSY_STATE; + + *state = HALMAC_RSVD_PG_STATE_BUSY; + + pg_addr &= BIT_MASK_BCN_HEAD_1_V1; + HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, (u16)(pg_addr | BIT(15))); + + value8 = HALMAC_REG_R8(REG_CR + 1); + restore[0] = value8; + value8 = (u8)(value8 | BIT(0)); + HALMAC_REG_W8(REG_CR + 1, value8); + + value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2); + restore[1] = value8; + value8 = (u8)(value8 & ~(BIT(6))); + HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8); + + if (PLTFM_SEND_RSVD_PAGE(buf, size) == _FALSE) { + PLTFM_MSG_ERR("[ERR]send rvsd pg(pltfm)!!\n"); + status = HALMAC_RET_DL_RSVD_PAGE_FAIL; + goto DL_RSVD_PG_END; + } + + cnt = 1000; + while (!(HALMAC_REG_R8(REG_FIFOPAGE_CTRL_2 + 1) & BIT(7))) { + PLTFM_DELAY_US(10); + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]bcn valid!!\n"); + status = HALMAC_RET_POLLING_BCN_VALID_FAIL; + break; + } + } +DL_RSVD_PG_END: + rsvd_pg_head = adapter->txff_alloc.rsvd_boundary; + HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, rsvd_pg_head | BIT(15)); + HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[1]); + HALMAC_REG_W8(REG_CR + 1, restore[0]); + + *state = HALMAC_RSVD_PG_STATE_IDLE; + + return status; +} + +enum halmac_ret_status +get_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (hw_id) { + case HALMAC_HW_RQPN_MAPPING: + get_pq_mapping_88xx(adapter, (struct halmac_rqpn_map *)value); + break; + case HALMAC_HW_EFUSE_SIZE: + *(u32 *)value = adapter->hw_cfg_info.efuse_size; + break; + case HALMAC_HW_EEPROM_SIZE: + *(u32 *)value = adapter->hw_cfg_info.eeprom_size; + break; + case HALMAC_HW_BT_BANK_EFUSE_SIZE: + *(u32 *)value = adapter->hw_cfg_info.bt_efuse_size; + break; + case HALMAC_HW_BT_BANK1_EFUSE_SIZE: + case HALMAC_HW_BT_BANK2_EFUSE_SIZE: + *(u32 *)value = 0; + break; + case HALMAC_HW_TXFIFO_SIZE: + *(u32 *)value = adapter->hw_cfg_info.tx_fifo_size; + break; + case HALMAC_HW_RXFIFO_SIZE: + *(u32 *)value = adapter->hw_cfg_info.rx_fifo_size; + break; + case HALMAC_HW_RSVD_PG_BNDY: + *(u16 *)value = adapter->txff_alloc.rsvd_drv_addr; + break; + case HALMAC_HW_CAM_ENTRY_NUM: + *(u8 *)value = adapter->hw_cfg_info.cam_entry_num; + break; + case HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE: + get_efuse_available_size_88xx(adapter, (u32 *)value); + break; + case HALMAC_HW_IC_VERSION: + *(u8 *)value = adapter->chip_ver; + break; + case HALMAC_HW_PAGE_SIZE: + *(u32 *)value = adapter->hw_cfg_info.page_size; + break; + case HALMAC_HW_TX_AGG_ALIGN_SIZE: + *(u16 *)value = adapter->hw_cfg_info.tx_align_size; + break; + case HALMAC_HW_RX_AGG_ALIGN_SIZE: + *(u8 *)value = 8; + break; + case HALMAC_HW_DRV_INFO_SIZE: + *(u8 *)value = adapter->drv_info_size; + break; + case HALMAC_HW_TXFF_ALLOCATION: + PLTFM_MEMCPY(value, &adapter->txff_alloc, + sizeof(struct halmac_txff_allocation)); + break; + case HALMAC_HW_RSVD_EFUSE_SIZE: + *(u32 *)value = get_rsvd_efuse_size_88xx(adapter); + break; + case HALMAC_HW_FW_HDR_SIZE: + *(u32 *)value = WLAN_FW_HDR_SIZE; + break; + case HALMAC_HW_TX_DESC_SIZE: + *(u32 *)value = adapter->hw_cfg_info.txdesc_size; + break; + case HALMAC_HW_RX_DESC_SIZE: + *(u32 *)value = adapter->hw_cfg_info.rxdesc_size; + break; + case HALMAC_HW_ORI_H2C_SIZE: + *(u32 *)value = ORIGINAL_H2C_CMD_SIZE; + break; + case HALMAC_HW_RSVD_DRV_PGNUM: + *(u16 *)value = adapter->txff_alloc.rsvd_drv_pg_num; + break; + case HALMAC_HW_TX_PAGE_SIZE: + *(u16 *)value = TX_PAGE_SIZE_88XX; + break; + case HALMAC_HW_USB_TXAGG_DESC_NUM: + *(u8 *)value = adapter->hw_cfg_info.usb_txagg_num; + break; + case HALMAC_HW_AC_OQT_SIZE: + *(u8 *)value = adapter->hw_cfg_info.ac_oqt_size; + break; + case HALMAC_HW_NON_AC_OQT_SIZE: + *(u8 *)value = adapter->hw_cfg_info.non_ac_oqt_size; + break; + case HALMAC_HW_AC_QUEUE_NUM: + *(u8 *)value = adapter->hw_cfg_info.acq_num; + break; + case HALMAC_HW_PWR_STATE: + pwr_state_88xx(adapter, (enum halmac_mac_power *)value); + break; + default: + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static void +get_pq_mapping_88xx(struct halmac_adapter *adapter, + struct halmac_rqpn_map *mapping) +{ + mapping->dma_map_vo = adapter->pq_map[HALMAC_PQ_MAP_VO]; + mapping->dma_map_vi = adapter->pq_map[HALMAC_PQ_MAP_VI]; + mapping->dma_map_be = adapter->pq_map[HALMAC_PQ_MAP_BE]; + mapping->dma_map_bk = adapter->pq_map[HALMAC_PQ_MAP_BK]; + mapping->dma_map_mg = adapter->pq_map[HALMAC_PQ_MAP_MG]; + mapping->dma_map_hi = adapter->pq_map[HALMAC_PQ_MAP_HI]; +} + +/** + * set_hw_value_88xx() -set hw config value + * @adapter : the adapter of halmac + * @hw_id : hw id for driver to config + * @value : hw value, reference table to get data type + * Author : KaiYuan Chang / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value) +{ + enum halmac_ret_status status; + struct halmac_tx_page_threshold_info *tx_th_info; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!value) { + PLTFM_MSG_ERR("[ERR]null ptr-set hw value\n"); + return HALMAC_RET_NULL_POINTER; + } + + switch (hw_id) { + case HALMAC_HW_USB_MODE: + status = set_usb_mode_88xx(adapter, + *(enum halmac_usb_mode *)value); + if (status != HALMAC_RET_SUCCESS) + return status; + break; + case HALMAC_HW_BANDWIDTH: + cfg_bw_88xx(adapter, *(enum halmac_bw *)value); + break; + case HALMAC_HW_CHANNEL: + cfg_ch_88xx(adapter, *(u8 *)value); + break; + case HALMAC_HW_PRI_CHANNEL_IDX: + cfg_pri_ch_idx_88xx(adapter, *(enum halmac_pri_ch_idx *)value); + break; + case HALMAC_HW_EN_BB_RF: + enable_bb_rf_88xx(adapter, *(u8 *)value); + break; + case HALMAC_HW_SDIO_TX_PAGE_THRESHOLD: + tx_th_info = (struct halmac_tx_page_threshold_info *)value; + cfg_sdio_tx_page_threshold_88xx(adapter, tx_th_info); + break; + case HALMAC_HW_RX_SHIFT: + rx_shift_88xx(adapter, *(u8 *)value); + break; + case HALMAC_HW_TXDESC_CHECKSUM: + tx_desc_chksum_88xx(adapter, *(u8 *)value); + break; + case HALMAC_HW_RX_CLK_GATE: + rx_clk_gate_88xx(adapter, *(u8 *)value); + break; + case HALMAC_HW_FAST_EDCA: + fast_edca_cfg_88xx(adapter, + (struct halmac_fast_edca_cfg *)value); + break; + default: + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +set_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr, + struct halmac_h2c_header_info *info, u16 *seq_num) +{ + u16 total_size; + + PLTFM_MSG_TRACE("[TRACE]%s!!\n", __func__); + + total_size = H2C_PKT_HDR_SIZE_88XX + info->content_size; + FW_OFFLOAD_H2C_SET_TOTAL_LEN(hdr, total_size); + FW_OFFLOAD_H2C_SET_SUB_CMD_ID(hdr, info->sub_cmd_id); + + FW_OFFLOAD_H2C_SET_CATEGORY(hdr, 0x01); + FW_OFFLOAD_H2C_SET_CMD_ID(hdr, 0xFF); + + PLTFM_MUTEX_LOCK(&adapter->h2c_seq_mutex); + FW_OFFLOAD_H2C_SET_SEQ_NUM(hdr, adapter->h2c_info.seq_num); + *seq_num = adapter->h2c_info.seq_num; + (adapter->h2c_info.seq_num)++; + PLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex); + + if (info->ack == _TRUE) + FW_OFFLOAD_H2C_SET_ACK(hdr, _TRUE); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +send_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt) +{ + u32 cnt = 100; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + while (adapter->h2c_info.buf_fs <= H2C_PKT_SIZE_88XX) { + get_h2c_buf_free_space_88xx(adapter); + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]h2c free space!!\n"); + return HALMAC_RET_H2C_SPACE_FULL; + } + } + + cnt = 100; + do { + if (PLTFM_SEND_H2C_PKT(pkt, H2C_PKT_SIZE_88XX) == _TRUE) + break; + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]pltfm - sned h2c pkt!!\n"); + return HALMAC_RET_SEND_H2C_FAIL; + } + PLTFM_DELAY_US(5); + + } while (1); + + adapter->h2c_info.buf_fs -= H2C_PKT_SIZE_88XX; + + return status; +} + +enum halmac_ret_status +get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter) +{ + u32 hw_wptr; + u32 fw_rptr; + struct halmac_h2c_info *info = &adapter->h2c_info; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + hw_wptr = HALMAC_REG_R32(REG_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_WR_ADDR; + fw_rptr = HALMAC_REG_R32(REG_H2C_PKT_READADDR) & BIT_MASK_H2C_READ_ADDR; + + if (hw_wptr >= fw_rptr) + info->buf_fs = info->buf_size - (hw_wptr - fw_rptr); + else + info->buf_fs = fw_rptr - hw_wptr; + + return HALMAC_RET_SUCCESS; +} + +/** + * get_c2h_info_88xx() - process halmac C2H packet + * @adapter : the adapter of halmac + * @buf : RX Packet pointer + * @size : RX Packet size + * Author : KaiYuan Chang/Ivan Lin + * + * Used to process c2h packet info from RX path. After receiving the packet, + * user need to call this api and pass the packet pointer. + * + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (GET_RX_DESC_C2H(buf) == _TRUE) { + PLTFM_MSG_TRACE("[TRACE]Parse c2h pkt\n"); + + status = parse_c2h_pkt_88xx(adapter, buf, size); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]Parse c2h pkt\n"); + return status; + } + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +parse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 cmd_id, sub_cmd_id; + u8 *c2h_pkt = buf + adapter->hw_cfg_info.rxdesc_size; + u32 c2h_size = size - adapter->hw_cfg_info.rxdesc_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + cmd_id = (u8)C2H_HDR_GET_CMD_ID(c2h_pkt); + + if (cmd_id != 0xFF) { + PLTFM_MSG_TRACE("[TRACE]Not 0xFF cmd!!\n"); + return HALMAC_RET_C2H_NOT_HANDLED; + } + + sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt); + + switch (sub_cmd_id) { + case C2H_SUB_CMD_ID_C2H_DBG: + status = get_c2h_dbg_88xx(adapter, c2h_pkt, c2h_size); + break; + case C2H_SUB_CMD_ID_H2C_ACK_HDR: + status = get_h2c_ack_88xx(adapter, c2h_pkt, c2h_size); + break; + case C2H_SUB_CMD_ID_BT_COEX_INFO: + status = HALMAC_RET_C2H_NOT_HANDLED; + break; + case C2H_SUB_CMD_ID_SCAN_STATUS_RPT: + status = get_scan_rpt_88xx(adapter, c2h_pkt, c2h_size); + break; + case C2H_SUB_CMD_ID_PSD_DATA: + status = get_psd_data_88xx(adapter, c2h_pkt, c2h_size); + break; + case C2H_SUB_CMD_ID_EFUSE_DATA: + status = get_efuse_data_88xx(adapter, c2h_pkt, c2h_size); + break; + default: + PLTFM_MSG_WARN("[WARN]Sub cmd id!!\n"); + status = HALMAC_RET_C2H_NOT_HANDLED; + break; + } + + return status; +} + +static enum halmac_ret_status +get_c2h_dbg_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 i; + u8 next_msg = 0; + u8 cur_msg = 0; + u8 msg_len = 0; + char *c2h_buf = (char *)NULL; + u8 content_len = 0; + u8 seq_num = 0; + + content_len = (u8)C2H_HDR_GET_LEN((u8 *)buf); + + if (content_len > C2H_DBG_CONTENT_MAX_LENGTH) { + PLTFM_MSG_ERR("[ERR]c2h size > max len!\n"); + return HALMAC_RET_C2H_NOT_HANDLED; + } + + for (i = 0; i < content_len; i++) { + if (*(buf + C2H_DBG_HDR_LEN + i) == '\n') { + if ((*(buf + C2H_DBG_HDR_LEN + i + 1) == '\0') || + (*(buf + C2H_DBG_HDR_LEN + i + 1) == 0xff)) { + next_msg = C2H_DBG_HDR_LEN + i + 1; + goto _ENDFOUND; + } + } + } + +_ENDFOUND: + msg_len = next_msg - C2H_DBG_HDR_LEN; + + c2h_buf = (char *)PLTFM_MALLOC(msg_len); + if (!c2h_buf) + return HALMAC_RET_MALLOC_FAIL; + + PLTFM_MEMCPY(c2h_buf, buf + C2H_DBG_HDR_LEN, msg_len); + + seq_num = (u8)(*(c2h_buf)); + *(c2h_buf + msg_len - 1) = '\0'; + PLTFM_MSG_ALWAYS("[RTKFW, SEQ=%d]: %s\n", + seq_num, (char *)(c2h_buf + 1)); + PLTFM_FREE(c2h_buf, msg_len); + + while (*(buf + next_msg) != '\0') { + cur_msg = next_msg; + + msg_len = (u8)(*(buf + cur_msg + 3)) - 1; + next_msg += C2H_DBG_HDR_LEN + msg_len; + + c2h_buf = (char *)PLTFM_MALLOC(msg_len); + if (!c2h_buf) + return HALMAC_RET_MALLOC_FAIL; + + PLTFM_MEMCPY(c2h_buf, buf + cur_msg + C2H_DBG_HDR_LEN, msg_len); + *(c2h_buf + msg_len - 1) = '\0'; + seq_num = (u8)(*(c2h_buf)); + PLTFM_MSG_ALWAYS("[RTKFW, SEQ=%d]: %s\n", + seq_num, (char *)(c2h_buf + 1)); + PLTFM_FREE(c2h_buf, msg_len); + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 cmd_id, sub_cmd_id; + u8 fw_rc; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]Ack for C2H!!\n"); + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + if (HALMAC_H2C_RETURN_SUCCESS != (enum halmac_h2c_return_code)fw_rc) + PLTFM_MSG_TRACE("[TRACE]fw rc = %d\n", fw_rc); + + cmd_id = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(buf); + + if (cmd_id != 0xFF) { + PLTFM_MSG_ERR("[ERR]h2c ack cmd id!!\n"); + return HALMAC_RET_C2H_NOT_HANDLED; + } + + sub_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(buf); + + switch (sub_cmd_id) { + case H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK: + status = get_h2c_ack_phy_efuse_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_CFG_PARAM_ACK: + status = get_h2c_ack_cfg_param_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_UPDATE_PKT_ACK: + status = get_h2c_ack_update_pkt_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK: + status = get_h2c_ack_update_datapkt_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_RUN_DATAPACK_ACK: + status = get_h2c_ack_run_datapkt_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_CH_SWITCH_ACK: + status = get_h2c_ack_ch_switch_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_IQK_ACK: + status = get_h2c_ack_iqk_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_PWR_TRK_ACK: + status = get_h2c_ack_pwr_trk_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_PSD_ACK: + break; + case H2C_SUB_CMD_ID_FW_SNDING_ACK: + status = get_h2c_ack_fw_snding_88xx(adapter, buf, size); + break; + default: + status = HALMAC_RET_C2H_NOT_HANDLED; + break; + } + + return status; +} + +static enum halmac_ret_status +get_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 fw_rc; + enum halmac_cmd_process_status proc_status; + + fw_rc = (u8)SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(buf); + proc_status = (HALMAC_H2C_RETURN_SUCCESS == + (enum halmac_h2c_return_code)fw_rc) ? + HALMAC_CMD_PROCESS_DONE : HALMAC_CMD_PROCESS_ERROR; + + PLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status, NULL, 0); + + adapter->halmac_state.scan_state.proc_status = proc_status; + + PLTFM_MSG_TRACE("[TRACE]scan : %X\n", proc_status); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_h2c_ack_cfg_param_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num; + u8 fw_rc; + u32 offset_accum; + u32 value_accum; + struct halmac_cfg_param_state *state = + &adapter->halmac_state.cfg_param_state; + enum halmac_cmd_process_status proc_status = + HALMAC_CMD_PROCESS_UNDEFINE; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + offset_accum = CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(buf); + value_accum = CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(buf); + + if (offset_accum != adapter->cfg_param_info.offset_accum || + value_accum != adapter->cfg_param_info.value_accum) { + PLTFM_MSG_ERR("[ERR][C2H]offset_accu : %x, value_accu : %xn", + offset_accum, value_accum); + PLTFM_MSG_ERR("[ERR][Ada]offset_accu : %x, value_accu : %x\n", + adapter->cfg_param_info.offset_accum, + adapter->cfg_param_info.value_accum); + proc_status = HALMAC_CMD_PROCESS_ERROR; + } + + if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS && + proc_status != HALMAC_CMD_PROCESS_ERROR) { + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, proc_status, NULL, 0); + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, proc_status, + &fw_rc, 1); + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_h2c_ack_update_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num; + u8 fw_rc; + struct halmac_update_pkt_state *state = + &adapter->halmac_state.update_pkt_state; + enum halmac_cmd_process_status proc_status; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + + if (HALMAC_H2C_RETURN_SUCCESS == (enum halmac_h2c_return_code)fw_rc) { + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_UPDATE_PACKET, proc_status, + NULL, 0); + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_UPDATE_PACKET, proc_status, + &state->fw_rc, 1); + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, + u32 size) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +static enum halmac_ret_status +get_h2c_ack_run_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +static enum halmac_ret_status +get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num; + u8 fw_rc; + struct halmac_scan_state *state = &adapter->halmac_state.scan_state; + enum halmac_cmd_process_status proc_status; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + + if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) { + proc_status = HALMAC_CMD_PROCESS_RCVD; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status, + NULL, 0); + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status, + &fw_rc, 1); + } + + return HALMAC_RET_SUCCESS; +} + +/** + * mac_debug_88xx() - dump debug information + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mac_debug_88xx(struct halmac_adapter *adapter) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (adapter->intf == HALMAC_INTERFACE_SDIO) + dump_reg_sdio_88xx(adapter); + else + dump_reg_88xx(adapter); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static void +dump_reg_sdio_88xx(struct halmac_adapter *adapter) +{ + u8 tmp8; + u32 i; + + /* Dump CCCR, it needs new platform api */ + + /*Dump SDIO Local Register, use CMD52*/ + for (i = 0x10250000; i < 0x102500ff; i++) { + tmp8 = PLTFM_SDIO_CMD52_R(i); + PLTFM_MSG_TRACE("[TRACE]dbg-sdio[%x]=%x\n", i, tmp8); + } + + /*Dump MAC Register*/ + for (i = 0x0000; i < 0x17ff; i++) { + tmp8 = PLTFM_SDIO_CMD52_R(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8); + } + + tmp8 = PLTFM_SDIO_CMD52_R(REG_SDIO_CRC_ERR_IDX); + if (tmp8) + PLTFM_MSG_ERR("[ERR]sdio crc=%x\n", tmp8); + + /*Check RX Fifo status*/ + i = REG_RXFF_PTR_V1; + tmp8 = PLTFM_SDIO_CMD52_R(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8); + i = REG_RXFF_WTR_V1; + tmp8 = PLTFM_SDIO_CMD52_R(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8); + i = REG_RXFF_PTR_V1; + tmp8 = PLTFM_SDIO_CMD52_R(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8); + i = REG_RXFF_WTR_V1; + tmp8 = PLTFM_SDIO_CMD52_R(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8); +} + +static void +dump_reg_88xx(struct halmac_adapter *adapter) +{ + u32 tmp32; + u32 i; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + /*Dump MAC Register*/ + for (i = 0x0000; i < 0x17fc; i += 4) { + tmp32 = HALMAC_REG_R32(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32); + } + + /*Check RX Fifo status*/ + i = REG_RXFF_PTR_V1; + tmp32 = HALMAC_REG_R32(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32); + i = REG_RXFF_WTR_V1; + tmp32 = HALMAC_REG_R32(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32); + i = REG_RXFF_PTR_V1; + tmp32 = HALMAC_REG_R32(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32); + i = REG_RXFF_WTR_V1; + tmp32 = HALMAC_REG_R32(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32); +} + +/** + * cfg_parameter_88xx() - config parameter by FW + * @adapter : the adapter of halmac + * @info : cmd id, content + * @full_fifo : parameter information + * + * If msk_en = _TRUE, the format of array is {reg_info, mask, value}. + * If msk_en =_FAUSE, the format of array is {reg_info, value} + * The format of reg_info is + * reg_info[31]=rf_reg, 0: MAC_BB reg, 1: RF reg + * reg_info[27:24]=rf_path, 0: path_A, 1: path_B + * if rf_reg=0(MAC_BB reg), rf_path is meaningless. + * ref_info[15:0]=offset + * + * Example: msk_en = _FALSE + * {0x8100000a, 0x00001122} + * =>Set RF register, path_B, offset 0xA to 0x00001122 + * {0x00000824, 0x11224433} + * =>Set MAC_BB register, offset 0x800 to 0x11224433 + * + * Note : full fifo mode only for init flow + * + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_parameter_88xx(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *info, u8 full_fifo) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + enum halmac_cmd_construct_state cmd_state; + + proc_status = &adapter->halmac_state.cfg_param_state.proc_status; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (adapter->fw_ver.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_TRACE("[TRACE]Wait event(para)\n"); + return HALMAC_RET_BUSY_STATE; + } + + cmd_state = cfg_param_cmd_cnstr_state_88xx(adapter); + if (cmd_state != HALMAC_CMD_CNSTR_IDLE && + cmd_state != HALMAC_CMD_CNSTR_CNSTR) { + PLTFM_MSG_TRACE("[TRACE]Not idle(para)\n"); + return HALMAC_RET_BUSY_STATE; + } + + *proc_status = HALMAC_CMD_PROCESS_IDLE; + + status = proc_cfg_param_88xx(adapter, info, full_fifo); + + if (status != HALMAC_RET_SUCCESS && status != HALMAC_RET_PARA_SENDING) { + PLTFM_MSG_ERR("[ERR]send param h2c\n"); + return status; + } + + return status; +} + +static enum halmac_cmd_construct_state +cfg_param_cmd_cnstr_state_88xx(struct halmac_adapter *adapter) +{ + return adapter->halmac_state.cfg_param_state.cmd_cnstr_state; +} + +static enum halmac_ret_status +proc_cfg_param_88xx(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *param, u8 full_fifo) +{ + u8 end_cmd = _FALSE; + u32 rsvd_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_cfg_param_info *info = &adapter->cfg_param_info; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.cfg_param_state.proc_status; + + status = malloc_cfg_param_buf_88xx(adapter, full_fifo); + if (status != HALMAC_RET_SUCCESS) + return status; + + if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + add_param_buf_88xx(adapter, param, info->buf_wptr, &end_cmd); + if (param->cmd_id != HALMAC_PARAMETER_CMD_END) { + info->num++; + info->buf_wptr += CFG_PARAM_H2C_INFO_SIZE; + info->avl_buf_size -= CFG_PARAM_H2C_INFO_SIZE; + } + + rsvd_size = info->avl_buf_size - adapter->hw_cfg_info.txdesc_size; + if (rsvd_size > CFG_PARAM_H2C_INFO_SIZE && end_cmd == _FALSE) + return HALMAC_RET_SUCCESS; + + if (info->num == 0) { + PLTFM_FREE(info->buf, info->buf_size); + info->buf = NULL; + info->buf_wptr = NULL; + PLTFM_MSG_TRACE("[TRACE]param num = 0!!\n"); + + *proc_status = HALMAC_CMD_PROCESS_DONE; + PLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, *proc_status, NULL, 0); + + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CFG_PARA); + + return HALMAC_RET_SUCCESS; + } + + status = send_cfg_param_h2c_88xx(adapter); + if (status != HALMAC_RET_SUCCESS) + return status; + + if (end_cmd == _FALSE) { + PLTFM_MSG_TRACE("[TRACE]send h2c-buf full\n"); + return HALMAC_RET_PARA_SENDING; + } + + return status; +} + +static enum halmac_ret_status +send_cfg_param_h2c_88xx(struct halmac_adapter *adapter) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 pg_addr; + u16 seq_num = 0; + u32 info_size; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_cfg_param_info *info = &adapter->cfg_param_info; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.cfg_param_state.proc_status; + + if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + if (info->full_fifo_mode == _TRUE) + pg_addr = 0; + else + pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + + info_size = info->num * CFG_PARAM_H2C_INFO_SIZE; + + status = dl_rsvd_page_88xx(adapter, pg_addr, info->buf, info_size); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n"); + goto CFG_PARAM_H2C_FAIL; + } + + gen_cfg_param_h2c_88xx(adapter, h2c_buf); + + hdr_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAM; + hdr_info.content_size = 4; + hdr_info.ack = _TRUE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + adapter->halmac_state.cfg_param_state.seq_num = seq_num; + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CFG_PARA); + } + +CFG_PARAM_H2C_FAIL: + PLTFM_FREE(info->buf, info->buf_size); + info->buf = NULL; + info->buf_wptr = NULL; + + if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + return status; +} + +static enum halmac_ret_status +cnv_cfg_param_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state) +{ + enum halmac_cmd_construct_state *state; + + state = &adapter->halmac_state.cfg_param_state.cmd_cnstr_state; + + if ((*state != HALMAC_CMD_CNSTR_IDLE) && + (*state != HALMAC_CMD_CNSTR_CNSTR) && + (*state != HALMAC_CMD_CNSTR_H2C_SENT)) + return HALMAC_RET_ERROR_STATE; + + if (dest_state == HALMAC_CMD_CNSTR_IDLE) { + if (*state == HALMAC_CMD_CNSTR_CNSTR) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_CNSTR) { + if (*state == HALMAC_CMD_CNSTR_H2C_SENT) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) { + if ((*state == HALMAC_CMD_CNSTR_IDLE) || + (*state == HALMAC_CMD_CNSTR_H2C_SENT)) + return HALMAC_RET_ERROR_STATE; + } + + *state = dest_state; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +add_param_buf_88xx(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *param, u8 *buf, + u8 *end_cmd) +{ + struct halmac_cfg_param_info *info = &adapter->cfg_param_info; + union halmac_parameter_content *content = ¶m->content; + + *end_cmd = _FALSE; + + PARAM_INFO_SET_LEN(buf, CFG_PARAM_H2C_INFO_SIZE); + PARAM_INFO_SET_IO_CMD(buf, param->cmd_id); + + switch (param->cmd_id) { + case HALMAC_PARAMETER_CMD_BB_W8: + case HALMAC_PARAMETER_CMD_BB_W16: + case HALMAC_PARAMETER_CMD_BB_W32: + case HALMAC_PARAMETER_CMD_MAC_W8: + case HALMAC_PARAMETER_CMD_MAC_W16: + case HALMAC_PARAMETER_CMD_MAC_W32: + PARAM_INFO_SET_IO_ADDR(buf, content->MAC_REG_W.offset); + PARAM_INFO_SET_DATA(buf, content->MAC_REG_W.value); + PARAM_INFO_SET_MASK(buf, content->MAC_REG_W.msk); + PARAM_INFO_SET_MSK_EN(buf, content->MAC_REG_W.msk_en); + info->value_accum += content->MAC_REG_W.value; + info->offset_accum += content->MAC_REG_W.offset; + break; + case HALMAC_PARAMETER_CMD_RF_W: + /*In rf register, the address is only 1 byte*/ + PARAM_INFO_SET_RF_ADDR(buf, content->RF_REG_W.offset); + PARAM_INFO_SET_RF_PATH(buf, content->RF_REG_W.rf_path); + PARAM_INFO_SET_DATA(buf, content->RF_REG_W.value); + PARAM_INFO_SET_MASK(buf, content->RF_REG_W.msk); + PARAM_INFO_SET_MSK_EN(buf, content->RF_REG_W.msk_en); + info->value_accum += content->RF_REG_W.value; + info->offset_accum += (content->RF_REG_W.offset + + (content->RF_REG_W.rf_path << 8)); + break; + case HALMAC_PARAMETER_CMD_DELAY_US: + case HALMAC_PARAMETER_CMD_DELAY_MS: + PARAM_INFO_SET_DELAY_VAL(buf, content->DELAY_TIME.delay_time); + break; + case HALMAC_PARAMETER_CMD_END: + *end_cmd = _TRUE; + break; + default: + PLTFM_MSG_ERR("[ERR]cmd id!!\n"); + break; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +gen_cfg_param_h2c_88xx(struct halmac_adapter *adapter, u8 *buff) +{ + struct halmac_cfg_param_info *info = &adapter->cfg_param_info; + u16 h2c_info_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + u16 rsvd_pg_addr = adapter->txff_alloc.rsvd_boundary; + + CFG_PARAM_SET_NUM(buff, info->num); + + if (info->full_fifo_mode == _TRUE) { + CFG_PARAM_SET_INIT_CASE(buff, 0x1); + CFG_PARAM_SET_LOC(buff, 0); + } else { + CFG_PARAM_SET_INIT_CASE(buff, 0x0); + CFG_PARAM_SET_LOC(buff, h2c_info_addr - rsvd_pg_addr); + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +malloc_cfg_param_buf_88xx(struct halmac_adapter *adapter, u8 full_fifo) +{ + struct halmac_cfg_param_info *info = &adapter->cfg_param_info; + struct halmac_pltfm_cfg_info *pltfm_info = &adapter->pltfm_info; + + if (info->buf) + return HALMAC_RET_SUCCESS; + + if (full_fifo == _TRUE) + info->buf_size = pltfm_info->malloc_size; + else + info->buf_size = CFG_PARAM_RSVDPG_SIZE; + + if (info->buf_size > pltfm_info->rsvd_pg_size) + info->buf_size = pltfm_info->rsvd_pg_size; + + info->buf = smart_malloc_88xx(adapter, info->buf_size, &info->buf_size); + if (info->buf) { + PLTFM_MEMSET(info->buf, 0x00, info->buf_size); + info->full_fifo_mode = full_fifo; + info->buf_wptr = info->buf; + info->num = 0; + info->avl_buf_size = info->buf_size; + info->value_accum = 0; + info->offset_accum = 0; + } else { + return HALMAC_RET_MALLOC_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * update_packet_88xx() - send specific packet to FW + * @adapter : the adapter of halmac + * @pkt_id : packet id, to know the purpose of this packet + * @pkt : packet + * @size : packet size + * + * Note : TX_DESC is not included in the pkt + * + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id, + u8 *pkt, u32 size) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status = + &adapter->halmac_state.update_pkt_state.proc_status; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (adapter->fw_ver.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + if (size > UPDATE_PKT_RSVDPG_SIZE) + return HALMAC_RET_RSVD_PG_OVERFLOW_FAIL; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_TRACE("[TRACE]Wait event(upd)\n"); + return HALMAC_RET_BUSY_STATE; + } + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + status = send_h2c_update_packet_88xx(adapter, pkt_id, pkt, size); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + PLTFM_MSG_ERR("[ERR]pkt id : %X!!\n", pkt_id); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +send_h2c_update_packet_88xx(struct halmac_adapter *adapter, + enum halmac_packet_id pkt_id, u8 *pkt, u32 size) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + u16 pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + u16 pg_offset; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + status = dl_rsvd_page_88xx(adapter, pg_addr, pkt, size); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n"); + return status; + } + + pg_offset = pg_addr - adapter->txff_alloc.rsvd_boundary; + UPDATE_PKT_SET_SIZE(h2c_buf, size + adapter->hw_cfg_info.txdesc_size); + UPDATE_PKT_SET_ID(h2c_buf, pkt_id); + UPDATE_PKT_SET_LOC(h2c_buf, pg_offset); + + hdr_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PKT; + hdr_info.content_size = 8; + hdr_info.ack = _TRUE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + adapter->halmac_state.update_pkt_state.seq_num = seq_num; + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_UPDATE_PACKET); + return status; + } + + return status; +} + +enum halmac_ret_status +bcn_ie_filter_88xx(struct halmac_adapter *adapter, + struct halmac_bcn_ie_info *info) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +enum halmac_ret_status +update_datapack_88xx(struct halmac_adapter *adapter, + enum halmac_data_type data_type, + struct halmac_phy_parameter_info *info) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +enum halmac_ret_status +run_datapack_88xx(struct halmac_adapter *adapter, + enum halmac_data_type data_type) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +enum halmac_ret_status +send_bt_coex_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, u8 ack) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = send_bt_coex_cmd_88xx(adapter, buf, size, ack); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]bt coex cmd!!\n"); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +send_bt_coex_cmd_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u8 ack) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + PLTFM_MEMCPY(h2c_buf + 8, buf, size); + + hdr_info.sub_cmd_id = SUB_CMD_ID_BT_COEX; + hdr_info.content_size = (u16)size; + hdr_info.ack = ack; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + return status; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * dump_fifo_88xx() - dump fifo data + * @adapter : the adapter of halmac + * @sel : FIFO selection + * @start_addr : start address of selected FIFO + * @size : dump size of selected FIFO + * @data : FIFO data + * + * Note : before dump fifo, user need to call halmac_get_fifo_size to + * get fifo size. Then input this size to halmac_dump_fifo. + * + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +dump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel, + u32 start_addr, u32 size, u8 *data) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + u8 tmp8; + u8 enable; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (sel == HAL_FIFO_SEL_TX && + (start_addr + size) > adapter->hw_cfg_info.tx_fifo_size) { + PLTFM_MSG_ERR("[ERR]size overflow!!\n"); + return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; + } + + if (sel == HAL_FIFO_SEL_RX && + (start_addr + size) > adapter->hw_cfg_info.rx_fifo_size) { + PLTFM_MSG_ERR("[ERR]size overflow!!\n"); + return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; + } + + if ((size & (4 - 1)) != 0) { + PLTFM_MSG_ERR("[ERR]not 4byte alignment!!\n"); + return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; + } + + if (!data) + return HALMAC_RET_NULL_POINTER; + + tmp8 = HALMAC_REG_R8(REG_RCR + 2); + enable = _FALSE; + status = api->halmac_set_hw_value(adapter, HALMAC_HW_RX_CLK_GATE, + &enable); + if (status != HALMAC_RET_SUCCESS) + return status; + status = read_buf_88xx(adapter, start_addr, size, sel, data); + + HALMAC_REG_W8(REG_RCR + 2, tmp8); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]read buf!!\n"); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +read_buf_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + enum hal_fifo_sel sel, u8 *data) +{ + u32 start_pg; + u32 value32; + u32 i; + u32 residue; + u32 cnt = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (sel == HAL_FIFO_SEL_RSVD_PAGE) + offset += (adapter->txff_alloc.rsvd_boundary << + TX_PAGE_SIZE_SHIFT_88XX); + + start_pg = offset >> 12; + residue = offset & (4096 - 1); + + if (sel == HAL_FIFO_SEL_TX || sel == HAL_FIFO_SEL_RSVD_PAGE) + start_pg += 0x780; + else if (sel == HAL_FIFO_SEL_RX) + start_pg += 0x700; + else if (sel == HAL_FIFO_SEL_REPORT) + start_pg += 0x660; + else if (sel == HAL_FIFO_SEL_LLT) + start_pg += 0x650; + else if (sel == HAL_FIFO_SEL_RXBUF_FW) + start_pg += 0x680; + else + return HALMAC_RET_NOT_SUPPORT; + + value32 = HALMAC_REG_R16(REG_PKTBUF_DBG_CTRL) & 0xF000; + + do { + HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)(start_pg | value32)); + + for (i = 0x8000 + residue; i <= 0x8FFF; i += 4) { + *(u32 *)(data + cnt) = HALMAC_REG_R32(i); + *(u32 *)(data + cnt) = + rtk_le32_to_cpu(*(u32 *)(data + cnt)); + cnt += 4; + if (size == cnt) + goto HALMAC_BUF_READ_OK; + } + + residue = 0; + start_pg++; + } while (1); + +HALMAC_BUF_READ_OK: + HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)value32); + + return HALMAC_RET_SUCCESS; +} + +/** + * get_fifo_size_88xx() - get fifo size + * @adapter : the adapter of halmac + * @sel : FIFO selection + * Author : Ivan Lin/KaiYuan Chang + * Return : u32 + * More details of status code can be found in prototype document + */ +u32 +get_fifo_size_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel) +{ + u32 size = 0; + + if (sel == HAL_FIFO_SEL_TX) + size = adapter->hw_cfg_info.tx_fifo_size; + else if (sel == HAL_FIFO_SEL_RX) + size = adapter->hw_cfg_info.rx_fifo_size; + else if (sel == HAL_FIFO_SEL_RSVD_PAGE) + size = adapter->hw_cfg_info.tx_fifo_size - + (adapter->txff_alloc.rsvd_boundary << + TX_PAGE_SIZE_SHIFT_88XX); + else if (sel == HAL_FIFO_SEL_REPORT) + size = 65536; + else if (sel == HAL_FIFO_SEL_LLT) + size = 65536; + else if (sel == HAL_FIFO_SEL_RXBUF_FW) + size = RX_BUF_FW_88XX; + + return size; +} + +enum halmac_ret_status +set_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack) +{ + PLTFM_MSG_TRACE("[TRACE]%s!!\n", __func__); + + H2C_CMD_HEADER_SET_CATEGORY(hdr, 0x00); + H2C_CMD_HEADER_SET_TOTAL_LEN(hdr, 16); + + PLTFM_MUTEX_LOCK(&adapter->h2c_seq_mutex); + H2C_CMD_HEADER_SET_SEQ_NUM(hdr, adapter->h2c_info.seq_num); + *seq = adapter->h2c_info.seq_num; + (adapter->h2c_info.seq_num)++; + PLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex); + + if (ack == _TRUE) + H2C_CMD_HEADER_SET_ACK(hdr, _TRUE); + + return HALMAC_RET_SUCCESS; +} + +/** + * add_ch_info_88xx() -add channel information + * @adapter : the adapter of halmac + * @info : channel information + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +add_ch_info_88xx(struct halmac_adapter *adapter, struct halmac_ch_info *info) +{ + struct halmac_ch_sw_info *ch_sw_info = &adapter->ch_sw_info; + enum halmac_cmd_construct_state state; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT) { + PLTFM_MSG_ERR("[ERR]gen info\n"); + return HALMAC_RET_GEN_INFO_NOT_SENT; + } + + state = scan_cmd_cnstr_state_88xx(adapter); + if (state != HALMAC_CMD_CNSTR_BUF_CLR && + state != HALMAC_CMD_CNSTR_CNSTR) { + PLTFM_MSG_WARN("[WARN]cmd state (scan)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (!ch_sw_info->buf) { + ch_sw_info->buf = (u8 *)PLTFM_MALLOC(SCAN_INFO_RSVDPG_SIZE); + if (!ch_sw_info->buf) + return HALMAC_RET_NULL_POINTER; + ch_sw_info->buf_wptr = ch_sw_info->buf; + ch_sw_info->buf_size = SCAN_INFO_RSVDPG_SIZE; + ch_sw_info->avl_buf_size = SCAN_INFO_RSVDPG_SIZE; + ch_sw_info->total_size = 0; + ch_sw_info->extra_info_en = 0; + ch_sw_info->ch_num = 0; + } + + if (ch_sw_info->extra_info_en == 1) { + PLTFM_MSG_ERR("[ERR]extra info = 1!!\n"); + return HALMAC_RET_CH_SW_SEQ_WRONG; + } + + if (ch_sw_info->avl_buf_size < 4) { + PLTFM_MSG_ERR("[ERR]buf full!!\n"); + return HALMAC_RET_CH_SW_NO_BUF; + } + + if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + CH_INFO_SET_CH(ch_sw_info->buf_wptr, info->channel); + CH_INFO_SET_PRI_CH_IDX(ch_sw_info->buf_wptr, info->pri_ch_idx); + CH_INFO_SET_BW(ch_sw_info->buf_wptr, info->bw); + CH_INFO_SET_TIMEOUT(ch_sw_info->buf_wptr, info->timeout); + CH_INFO_SET_ACTION_ID(ch_sw_info->buf_wptr, info->action_id); + CH_INFO_SET_EXTRA_INFO(ch_sw_info->buf_wptr, info->extra_info); + + ch_sw_info->avl_buf_size = ch_sw_info->avl_buf_size - 4; + ch_sw_info->total_size = ch_sw_info->total_size + 4; + ch_sw_info->ch_num++; + ch_sw_info->extra_info_en = info->extra_info; + ch_sw_info->buf_wptr = ch_sw_info->buf_wptr + 4; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_cmd_construct_state +scan_cmd_cnstr_state_88xx(struct halmac_adapter *adapter) +{ + return adapter->halmac_state.scan_state.cmd_cnstr_state; +} + +static enum halmac_ret_status +cnv_scan_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state) +{ + enum halmac_cmd_construct_state *state; + + state = &adapter->halmac_state.scan_state.cmd_cnstr_state; + + if (dest_state == HALMAC_CMD_CNSTR_IDLE) { + if ((*state == HALMAC_CMD_CNSTR_BUF_CLR) || + (*state == HALMAC_CMD_CNSTR_CNSTR)) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_BUF_CLR) { + if (*state == HALMAC_CMD_CNSTR_H2C_SENT) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_CNSTR) { + if ((*state == HALMAC_CMD_CNSTR_IDLE) || + (*state == HALMAC_CMD_CNSTR_H2C_SENT)) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) { + if ((*state != HALMAC_CMD_CNSTR_CNSTR) && + (*state != HALMAC_CMD_CNSTR_BUF_CLR)) + return HALMAC_RET_ERROR_STATE; + } + + *state = dest_state; + + return HALMAC_RET_SUCCESS; +} + +/** + * add_extra_ch_info_88xx() -add extra channel information + * @adapter : the adapter of halmac + * @info : extra channel information + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +add_extra_ch_info_88xx(struct halmac_adapter *adapter, + struct halmac_ch_extra_info *info) +{ + struct halmac_ch_sw_info *ch_sw_info = &adapter->ch_sw_info; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!ch_sw_info->buf) { + PLTFM_MSG_ERR("[ERR]buf = null!!\n"); + return HALMAC_RET_CH_SW_SEQ_WRONG; + } + + if (ch_sw_info->extra_info_en == 0) { + PLTFM_MSG_ERR("[ERR]extra info = 0!!\n"); + return HALMAC_RET_CH_SW_SEQ_WRONG; + } + + if (ch_sw_info->avl_buf_size < (u32)(info->extra_info_size + 2)) { + PLTFM_MSG_ERR("[ERR]no available buffer!!\n"); + return HALMAC_RET_CH_SW_NO_BUF; + } + + if (scan_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_CNSTR) { + PLTFM_MSG_WARN("[WARN]cmd state (ex scan)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + CH_EXTRA_INFO_SET_ID(ch_sw_info->buf_wptr, info->extra_action_id); + CH_EXTRA_INFO_SET_INFO(ch_sw_info->buf_wptr, info->extra_info); + CH_EXTRA_INFO_SET_SIZE(ch_sw_info->buf_wptr, info->extra_info_size); + PLTFM_MEMCPY(ch_sw_info->buf_wptr + 2, info->extra_info_data, + info->extra_info_size); + + ch_sw_info->avl_buf_size -= (2 + info->extra_info_size); + ch_sw_info->total_size += (2 + info->extra_info_size); + ch_sw_info->extra_info_en = info->extra_info; + ch_sw_info->buf_wptr += (2 + info->extra_info_size); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * ctrl_ch_switch_88xx() -send channel switch cmd + * @adapter : the adapter of halmac + * @opt : channel switch config + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +ctrl_ch_switch_88xx(struct halmac_adapter *adapter, + struct halmac_ch_switch_option *opt) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_construct_state state; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.scan_state.proc_status; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (adapter->fw_ver.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (opt->switch_en == _FALSE) + *proc_status = HALMAC_CMD_PROCESS_IDLE; + + if ((*proc_status == HALMAC_CMD_PROCESS_SENDING) || + (*proc_status == HALMAC_CMD_PROCESS_RCVD)) { + PLTFM_MSG_TRACE("[TRACE]Wait event(scan)\n"); + return HALMAC_RET_BUSY_STATE; + } + + state = scan_cmd_cnstr_state_88xx(adapter); + if (opt->switch_en == _TRUE) { + if (state != HALMAC_CMD_CNSTR_CNSTR) { + PLTFM_MSG_ERR("[ERR]state(en = 1)\n"); + return HALMAC_RET_ERROR_STATE; + } + } else { + if (state != HALMAC_CMD_CNSTR_BUF_CLR) { + PLTFM_MSG_ERR("[ERR]state(en = 0)\n"); + return HALMAC_RET_ERROR_STATE; + } + } + + status = proc_ctrl_ch_switch_88xx(adapter, opt); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]ctrl ch sw!!\n"); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter, + struct halmac_ch_switch_option *opt) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + u16 pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.scan_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + if (opt->switch_en != 0) { + status = dl_rsvd_page_88xx(adapter, pg_addr, + adapter->ch_sw_info.buf, + adapter->ch_sw_info.total_size); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n"); + return status; + } + } + + CH_SWITCH_SET_START(h2c_buf, opt->switch_en); + CH_SWITCH_SET_CH_NUM(h2c_buf, adapter->ch_sw_info.ch_num); + CH_SWITCH_SET_INFO_LOC(h2c_buf, + pg_addr - adapter->txff_alloc.rsvd_boundary); + CH_SWITCH_SET_DEST_CH_EN(h2c_buf, opt->dest_ch_en); + CH_SWITCH_SET_DEST_CH(h2c_buf, opt->dest_ch); + CH_SWITCH_SET_PRI_CH_IDX(h2c_buf, opt->dest_pri_ch_idx); + CH_SWITCH_SET_ABSOLUTE_TIME(h2c_buf, opt->absolute_time_en); + CH_SWITCH_SET_TSF_LOW(h2c_buf, opt->tsf_low); + CH_SWITCH_SET_PERIODIC_OPT(h2c_buf, opt->periodic_option); + CH_SWITCH_SET_NORMAL_CYCLE(h2c_buf, opt->normal_cycle); + CH_SWITCH_SET_NORMAL_PERIOD(h2c_buf, opt->normal_period); + CH_SWITCH_SET_SLOW_PERIOD(h2c_buf, opt->phase_2_period); + CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_buf, opt->normal_period_sel); + CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_buf, opt->phase_2_period_sel); + CH_SWITCH_SET_INFO_SIZE(h2c_buf, adapter->ch_sw_info.total_size); + + hdr_info.sub_cmd_id = SUB_CMD_ID_CH_SWITCH; + hdr_info.content_size = 20; + hdr_info.ack = _TRUE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + adapter->halmac_state.scan_state.seq_num = seq_num; + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CHANNEL_SWITCH); + } + PLTFM_FREE(adapter->ch_sw_info.buf, adapter->ch_sw_info.buf_size); + adapter->ch_sw_info.buf = NULL; + adapter->ch_sw_info.buf_wptr = NULL; + adapter->ch_sw_info.extra_info_en = 0; + adapter->ch_sw_info.buf_size = 0; + adapter->ch_sw_info.avl_buf_size = 0; + adapter->ch_sw_info.total_size = 0; + adapter->ch_sw_info.ch_num = 0; + + if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + return status; +} + +/** + * clear_ch_info_88xx() -clear channel information + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +clear_ch_info_88xx(struct halmac_adapter *adapter) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (scan_cmd_cnstr_state_88xx(adapter) == HALMAC_CMD_CNSTR_H2C_SENT) { + PLTFM_MSG_WARN("[WARN]state(clear)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_BUF_CLR) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_FREE(adapter->ch_sw_info.buf, adapter->ch_sw_info.buf_size); + adapter->ch_sw_info.buf = NULL; + adapter->ch_sw_info.buf_wptr = NULL; + adapter->ch_sw_info.extra_info_en = 0; + adapter->ch_sw_info.buf_size = 0; + adapter->ch_sw_info.avl_buf_size = 0; + adapter->ch_sw_info.total_size = 0; + adapter->ch_sw_info.ch_num = 0; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * chk_txdesc_88xx() -check if the tx packet format is incorrect + * @adapter : the adapter of halmac + * @buf : tx Packet buffer, tx desc is included + * @size : tx packet size + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u32 mac_clk = 0; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (GET_TX_DESC_BMC(buf) == _TRUE && GET_TX_DESC_AGG_EN(buf) == _TRUE) + PLTFM_MSG_ERR("[ERR]txdesc - agg + bmc\n"); + + if (size < (GET_TX_DESC_TXPKTSIZE(buf) + + adapter->hw_cfg_info.txdesc_size + + (GET_TX_DESC_PKT_OFFSET(buf) << 3))) { + PLTFM_MSG_ERR("[ERR]txdesc - total size\n"); + status = HALMAC_RET_TXDESC_SET_FAIL; + } + + if (wlhdr_valid_88xx(adapter, buf) != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]wlhdr\n"); + status = HALMAC_RET_WLHDR_FAIL; + } + + if (GET_TX_DESC_AMSDU_PAD_EN(buf) != 0) { + PLTFM_MSG_ERR("[ERR]txdesc - amsdu_pad\n"); + status = HALMAC_RET_TXDESC_SET_FAIL; + } + + switch (BIT_GET_MAC_CLK_SEL(HALMAC_REG_R32(REG_AFE_CTRL1))) { + case 0x0: + mac_clk = 80; + break; + case 0x1: + mac_clk = 40; + break; + case 0x2: + mac_clk = 20; + break; + case 0x3: + mac_clk = 10; + break; + } + + PLTFM_MSG_ALWAYS("MAC clock : 0x%XM\n", mac_clk); + PLTFM_MSG_ALWAYS("mac agg en : 0x%X\n", GET_TX_DESC_AGG_EN(buf)); + PLTFM_MSG_ALWAYS("mac agg num : 0x%X\n", GET_TX_DESC_MAX_AGG_NUM(buf)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return status; +} + +static enum halmac_ret_status +wlhdr_valid_88xx(struct halmac_adapter *adapter, u8 *buf) +{ + u32 txdesc_size = adapter->hw_cfg_info.txdesc_size + + GET_TX_DESC_PKT_OFFSET(buf); + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct wlhdr_frame_ctrl *wlhdr; + + wlhdr = (struct wlhdr_frame_ctrl *)(buf + txdesc_size); + + if (wlhdr->protocol != WLHDR_PROT_VER) { + PLTFM_MSG_ERR("[ERR]prot ver!!\n"); + return HALMAC_RET_WLHDR_FAIL; + } + + switch (wlhdr->type) { + case WLHDR_TYPE_MGMT: + if (wlhdr_mgmt_valid_88xx(adapter, wlhdr) != _TRUE) + status = HALMAC_RET_WLHDR_FAIL; + break; + case WLHDR_TYPE_CTRL: + if (wlhdr_ctrl_valid_88xx(adapter, wlhdr) != _TRUE) + status = HALMAC_RET_WLHDR_FAIL; + break; + case WLHDR_TYPE_DATA: + if (wlhdr_data_valid_88xx(adapter, wlhdr) != _TRUE) + status = HALMAC_RET_WLHDR_FAIL; + break; + default: + PLTFM_MSG_ERR("[ERR]undefined type!!\n"); + status = HALMAC_RET_WLHDR_FAIL; + break; + } + + return status; +} + +static u8 +wlhdr_mgmt_valid_88xx(struct halmac_adapter *adapter, + struct wlhdr_frame_ctrl *wlhdr) +{ + u8 state; + + switch (wlhdr->sub_type) { + case WLHDR_SUB_TYPE_ASSOC_REQ: + case WLHDR_SUB_TYPE_ASSOC_RSPNS: + case WLHDR_SUB_TYPE_REASSOC_REQ: + case WLHDR_SUB_TYPE_REASSOC_RSPNS: + case WLHDR_SUB_TYPE_PROBE_REQ: + case WLHDR_SUB_TYPE_PROBE_RSPNS: + case WLHDR_SUB_TYPE_BCN: + case WLHDR_SUB_TYPE_DISASSOC: + case WLHDR_SUB_TYPE_AUTH: + case WLHDR_SUB_TYPE_DEAUTH: + case WLHDR_SUB_TYPE_ACTION: + case WLHDR_SUB_TYPE_ACTION_NOACK: + state = _TRUE; + break; + default: + PLTFM_MSG_ERR("[ERR]mgmt invalid!!\n"); + state = _FALSE; + break; + } + + return state; +} + +static u8 +wlhdr_ctrl_valid_88xx(struct halmac_adapter *adapter, + struct wlhdr_frame_ctrl *wlhdr) +{ + u8 state; + + switch (wlhdr->sub_type) { + case WLHDR_SUB_TYPE_BF_RPT_POLL: + case WLHDR_SUB_TYPE_NDPA: + state = _TRUE; + break; + default: + PLTFM_MSG_ERR("[ERR]ctrl invalid!!\n"); + state = _FALSE; + break; + } + + return state; +} + +static u8 +wlhdr_data_valid_88xx(struct halmac_adapter *adapter, + struct wlhdr_frame_ctrl *wlhdr) +{ + u8 state; + + switch (wlhdr->sub_type) { + case WLHDR_SUB_TYPE_DATA: + case WLHDR_SUB_TYPE_NULL: + case WLHDR_SUB_TYPE_QOS_DATA: + case WLHDR_SUB_TYPE_QOS_NULL: + state = _TRUE; + break; + default: + PLTFM_MSG_ERR("[ERR]data invalid!!\n"); + state = _FALSE; + break; + } + + return state; +} + +/** + * halmac_get_version() - get HALMAC version + * @ver : return version of major, prototype and minor information + * Author : KaiYuan Chang / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_version_88xx(struct halmac_adapter *adapter, struct halmac_ver *ver) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + ver->major_ver = (u8)HALMAC_MAJOR_VER; + ver->prototype_ver = (u8)HALMAC_PROTOTYPE_VER; + ver->minor_ver = (u8)HALMAC_MINOR_VER; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (adapter->fw_ver.h2c_version < 6) + return HALMAC_RET_FW_NO_SUPPORT; + + status = proc_p2pps_88xx(adapter, info); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]p2pps!!\n"); + return status; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +proc_p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + P2PPS_SET_OFFLOAD_EN(h2c_buf, info->offload_en); + P2PPS_SET_ROLE(h2c_buf, info->role); + P2PPS_SET_CTWINDOW_EN(h2c_buf, info->ctwindow_en); + P2PPS_SET_NOA_EN(h2c_buf, info->noa_en); + P2PPS_SET_NOA_SEL(h2c_buf, info->noa_sel); + P2PPS_SET_ALLSTASLEEP(h2c_buf, info->all_sta_sleep); + P2PPS_SET_DISCOVERY(h2c_buf, info->discovery); + P2PPS_SET_DISABLE_CLOSERF(h2c_buf, info->disable_close_rf); + P2PPS_SET_P2P_PORT_ID(h2c_buf, info->p2p_port_id); + P2PPS_SET_P2P_GROUP(h2c_buf, info->p2p_group); + P2PPS_SET_P2P_MACID(h2c_buf, info->p2p_macid); + + P2PPS_SET_CTWINDOW_LENGTH(h2c_buf, info->ctwindow_length); + + P2PPS_SET_NOA_DURATION_PARA(h2c_buf, info->noa_duration_para); + P2PPS_SET_NOA_INTERVAL_PARA(h2c_buf, info->noa_interval_para); + P2PPS_SET_NOA_START_TIME_PARA(h2c_buf, info->noa_start_time_para); + P2PPS_SET_NOA_COUNT_PARA(h2c_buf, info->noa_count_para); + + hdr_info.sub_cmd_id = SUB_CMD_ID_P2PPS; + hdr_info.content_size = 24; + hdr_info.ack = _FALSE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + + return status; +} + +/** + * query_status_88xx() -query the offload feature status + * @adapter : the adapter of halmac + * @feature_id : feature_id + * @proc_status : feature_status + * @data : data buffer + * @size : data size + * + * Note : + * If user wants to know the data size, user can allocate zero + * size buffer first. If this size less than the data size, halmac + * will return HALMAC_RET_BUFFER_TOO_SMALL. User need to + * re-allocate data buffer with correct data size. + * + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +query_status_88xx(struct halmac_adapter *adapter, + enum halmac_feature_id feature_id, + enum halmac_cmd_process_status *proc_status, u8 *data, + u32 *size) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (!proc_status) + return HALMAC_RET_NULL_POINTER; + + switch (feature_id) { + case HALMAC_FEATURE_CFG_PARA: + status = get_cfg_param_status_88xx(adapter, proc_status); + break; + case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE: + status = get_dump_phy_efuse_status_88xx(adapter, proc_status, + data, size); + break; + case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE: + status = get_dump_log_efuse_status_88xx(adapter, proc_status, + data, size); + break; + case HALMAC_FEATURE_CHANNEL_SWITCH: + status = get_ch_switch_status_88xx(adapter, proc_status); + break; + case HALMAC_FEATURE_UPDATE_PACKET: + status = get_update_packet_status_88xx(adapter, proc_status); + break; + case HALMAC_FEATURE_IQK: + status = get_iqk_status_88xx(adapter, proc_status); + break; + case HALMAC_FEATURE_POWER_TRACKING: + status = get_pwr_trk_status_88xx(adapter, proc_status); + break; + case HALMAC_FEATURE_PSD: + status = get_psd_status_88xx(adapter, proc_status, data, size); + break; + case HALMAC_FEATURE_FW_SNDING: + status = get_fw_snding_status_88xx(adapter, proc_status); + break; + default: + return HALMAC_RET_INVALID_FEATURE_ID; + } + + return status; +} + +static enum halmac_ret_status +get_cfg_param_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status) +{ + *proc_status = adapter->halmac_state.cfg_param_state.proc_status; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_ch_switch_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status) +{ + *proc_status = adapter->halmac_state.scan_state.proc_status; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_update_packet_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status) +{ + *proc_status = adapter->halmac_state.update_pkt_state.proc_status; + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_drv_rsvd_pg_num_88xx() -config reserved page number for driver + * @adapter : the adapter of halmac + * @pg_num : page number + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter, + enum halmac_drv_rsvd_pg_num pg_num) +{ + if (adapter->api_registry.cfg_drv_rsvd_pg_en == 0) + return HALMAC_RET_NOT_SUPPORT; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]pg_num = %d\n", pg_num); + + switch (pg_num) { + case HALMAC_RSVD_PG_NUM8: + adapter->txff_alloc.rsvd_drv_pg_num = 8; + break; + case HALMAC_RSVD_PG_NUM16: + adapter->txff_alloc.rsvd_drv_pg_num = 16; + break; + case HALMAC_RSVD_PG_NUM24: + adapter->txff_alloc.rsvd_drv_pg_num = 24; + break; + case HALMAC_RSVD_PG_NUM32: + adapter->txff_alloc.rsvd_drv_pg_num = 32; + break; + case HALMAC_RSVD_PG_NUM64: + adapter->txff_alloc.rsvd_drv_pg_num = 64; + break; + case HALMAC_RSVD_PG_NUM128: + adapter->txff_alloc.rsvd_drv_pg_num = 128; + break; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * (debug API)h2c_lb_88xx() - send h2c loopback packet + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +h2c_lb_88xx(struct halmac_adapter *adapter) +{ + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +pwr_seq_parser_88xx(struct halmac_adapter *adapter, + struct halmac_wlan_pwr_cfg **cmd_seq) +{ + u8 cut; + u8 intf; + u32 idx = 0; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_wlan_pwr_cfg *cmd; + + switch (adapter->chip_ver) { + case HALMAC_CHIP_VER_A_CUT: + cut = HALMAC_PWR_CUT_A_MSK; + break; + case HALMAC_CHIP_VER_B_CUT: + cut = HALMAC_PWR_CUT_B_MSK; + break; + case HALMAC_CHIP_VER_C_CUT: + cut = HALMAC_PWR_CUT_C_MSK; + break; + case HALMAC_CHIP_VER_D_CUT: + cut = HALMAC_PWR_CUT_D_MSK; + break; + case HALMAC_CHIP_VER_E_CUT: + cut = HALMAC_PWR_CUT_E_MSK; + break; + case HALMAC_CHIP_VER_F_CUT: + cut = HALMAC_PWR_CUT_F_MSK; + break; + case HALMAC_CHIP_VER_TEST: + cut = HALMAC_PWR_CUT_TESTCHIP_MSK; + break; + default: + PLTFM_MSG_ERR("[ERR]cut version!!\n"); + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + switch (adapter->intf) { + case HALMAC_INTERFACE_PCIE: + case HALMAC_INTERFACE_AXI: + intf = HALMAC_PWR_INTF_PCI_MSK; + break; + case HALMAC_INTERFACE_USB: + intf = HALMAC_PWR_INTF_USB_MSK; + break; + case HALMAC_INTERFACE_SDIO: + intf = HALMAC_PWR_INTF_SDIO_MSK; + break; + default: + PLTFM_MSG_ERR("[ERR]interface!!\n"); + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + do { + cmd = cmd_seq[idx]; + + if (!cmd) + break; + + status = pwr_sub_seq_parser_88xx(adapter, cut, intf, cmd); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]pwr sub seq!!\n"); + return status; + } + + idx++; + } while (1); + + return status; +} + +static enum halmac_ret_status +pwr_sub_seq_parser_88xx(struct halmac_adapter *adapter, u8 cut, u8 intf, + struct halmac_wlan_pwr_cfg *cmd) +{ + u8 value; + u32 offset; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + do { + if ((cmd->interface_msk & intf) && (cmd->cut_msk & cut)) { + switch (cmd->cmd) { + case HALMAC_PWR_CMD_WRITE: + offset = cmd->offset; + + if (cmd->base == HALMAC_PWR_ADDR_SDIO) + offset |= SDIO_LOCAL_OFFSET; + + value = HALMAC_REG_R8(offset); + value = (u8)(value & (u8)(~(cmd->msk))); + value = (u8)(value | (cmd->value & cmd->msk)); + + HALMAC_REG_W8(offset, value); + break; + case HALMAC_PWR_CMD_POLLING: + if (pwr_cmd_polling_88xx(adapter, cmd) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_PWRSEQ_POLLING_FAIL; + break; + case HALMAC_PWR_CMD_DELAY: + if (cmd->value == HALMAC_PWR_DELAY_US) + PLTFM_DELAY_US(cmd->offset); + else + PLTFM_DELAY_US(1000 * cmd->offset); + break; + case HALMAC_PWR_CMD_READ: + break; + case HALMAC_PWR_CMD_END: + return HALMAC_RET_SUCCESS; + default: + return HALMAC_RET_PWRSEQ_CMD_INCORRECT; + } + } + cmd++; + } while (1); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +pwr_cmd_polling_88xx(struct halmac_adapter *adapter, + struct halmac_wlan_pwr_cfg *cmd) +{ + u8 value; + u8 flg; + u8 poll_bit; + u32 offset; + u32 cnt; + static u32 stats; + enum halmac_interface intf; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + poll_bit = 0; + cnt = HALMAC_PWR_POLLING_CNT; + flg = 0; + intf = adapter->intf; + + if (cmd->base == HALMAC_PWR_ADDR_SDIO) + offset = cmd->offset | SDIO_LOCAL_OFFSET; + else + offset = cmd->offset; + + do { + cnt--; + value = HALMAC_REG_R8(offset); + value = (u8)(value & cmd->msk); + + if (value == (cmd->value & cmd->msk)) { + poll_bit = 1; + } else { + if (cnt == 0) { + if (intf == HALMAC_INTERFACE_PCIE && flg == 0) { + /* PCIE + USB package */ + /* power bit polling timeout issue */ + stats++; + PLTFM_MSG_WARN("[WARN]PCIE stats:%d\n", + stats); + value = HALMAC_REG_R8(REG_SYS_PW_CTRL); + value |= BIT(3); + HALMAC_REG_W8(REG_SYS_PW_CTRL, value); + value &= ~BIT(3); + HALMAC_REG_W8(REG_SYS_PW_CTRL, value); + poll_bit = 0; + cnt = HALMAC_PWR_POLLING_CNT; + flg = 1; + } else { + PLTFM_MSG_ERR("[ERR]polling to!!\n"); + PLTFM_MSG_ERR("[ERR]cmd offset:%X\n", + cmd->offset); + PLTFM_MSG_ERR("[ERR]cmd value:%X\n", + cmd->value); + PLTFM_MSG_ERR("[ERR]cmd msk:%X\n", + cmd->msk); + PLTFM_MSG_ERR("[ERR]offset = %X\n", + offset); + PLTFM_MSG_ERR("[ERR]value = %X\n", + value); + return HALMAC_RET_PWRSEQ_POLLING_FAIL; + } + } else { + PLTFM_DELAY_US(50); + } + } + } while (!poll_bit); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +parse_intf_phy_88xx(struct halmac_adapter *adapter, + struct halmac_intf_phy_para *param, + enum halmac_intf_phy_platform pltfm, + enum hal_intf_phy intf_phy) +{ + u16 value; + u16 cur_cut; + u16 offset; + u16 ip_sel; + struct halmac_intf_phy_para *cur_param; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 result = HALMAC_RET_SUCCESS; + + switch (adapter->chip_ver) { + case HALMAC_CHIP_VER_A_CUT: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_A; + break; + case HALMAC_CHIP_VER_B_CUT: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_B; + break; + case HALMAC_CHIP_VER_C_CUT: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_C; + break; + case HALMAC_CHIP_VER_D_CUT: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_D; + break; + case HALMAC_CHIP_VER_E_CUT: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_E; + break; + case HALMAC_CHIP_VER_F_CUT: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_F; + break; + case HALMAC_CHIP_VER_TEST: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_TESTCHIP; + break; + default: + return HALMAC_RET_FAIL; + } + + cur_param = param; + + do { + if ((cur_param->cut & cur_cut) && + (cur_param->plaform & (u16)pltfm)) { + offset = cur_param->offset; + value = cur_param->value; + ip_sel = cur_param->ip_sel; + + if (offset == 0xFFFF) + break; + + if (ip_sel == HALMAC_IP_SEL_MAC) { + HALMAC_REG_W8((u32)offset, (u8)value); + } else if (intf_phy == HAL_INTF_PHY_USB2 || + intf_phy == HAL_INTF_PHY_USB3) { + result = usbphy_write_88xx(adapter, (u8)offset, + value, intf_phy); + if (result != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]usb phy!!\n"); + + } else if (intf_phy == HAL_INTF_PHY_PCIE_GEN1 || + intf_phy == HAL_INTF_PHY_PCIE_GEN2) { + if (ip_sel == HALMAC_IP_INTF_PHY) + result = mdio_write_88xx(adapter, + (u8)offset, + value, + intf_phy); + else + result = dbi_w8_88xx(adapter, offset, + (u8)value); + if (result != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]mdio/dbi!!\n"); + + } else { + PLTFM_MSG_ERR("[ERR]intf phy sel!!\n"); + } + } + cur_param++; + } while (1); + + return HALMAC_RET_SUCCESS; +} + +/** + * txfifo_is_empty_88xx() -check if txfifo is empty + * @adapter : the adapter of halmac + * @chk_num : check number + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +txfifo_is_empty_88xx(struct halmac_adapter *adapter, u32 chk_num) +{ + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + cnt = (chk_num <= 10) ? 10 : chk_num; + do { + if (HALMAC_REG_R8(REG_TXPKT_EMPTY) != 0xFF) + return HALMAC_RET_TXFIFO_NO_EMPTY; + + if ((HALMAC_REG_R8(REG_TXPKT_EMPTY + 1) & 0x06) != 0x06) + return HALMAC_RET_TXFIFO_NO_EMPTY; + cnt--; + + } while (cnt != 0); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * (internal use) + * smart_malloc_88xx() - adapt malloc size + * @adapter : the adapter of halmac + * @size : expected malloc size + * @pNew_size : real malloc size + * Author : Ivan Lin + * Return : address pointer + */ +u8* +smart_malloc_88xx(struct halmac_adapter *adapter, u32 size, u32 *new_size) +{ + u8 retry_num; + u8 *malloc_buf = NULL; + + for (retry_num = 0; retry_num < 5; retry_num++) { + malloc_buf = (u8 *)PLTFM_MALLOC(size); + + if (malloc_buf) { + *new_size = size; + return malloc_buf; + } + + size = size >> 1; + + if (size == 0) + break; + } + + PLTFM_MSG_ERR("[ERR]adptive malloc!!\n"); + + return NULL; +} + +/** + * (internal use) + * ltecoex_reg_read_88xx() - read ltecoex register + * @adapter : the adapter of halmac + * @offset : offset + * @pValue : value + * Author : Ivan Lin + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +ltecoex_reg_read_88xx(struct halmac_adapter *adapter, u16 offset, u32 *value) +{ + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + cnt = 10000; + while ((HALMAC_REG_R8(LTECOEX_ACCESS_CTRL + 3) & BIT(5)) == 0) { + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]lte ready(R)\n"); + return HALMAC_RET_LTECOEX_READY_FAIL; + } + cnt--; + PLTFM_DELAY_US(50); + } + + HALMAC_REG_W32(LTECOEX_ACCESS_CTRL, 0x800F0000 | offset); + *value = HALMAC_REG_R32(REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1); + + return HALMAC_RET_SUCCESS; +} + +/** + * (internal use) + * ltecoex_reg_write_88xx() - write ltecoex register + * @adapter : the adapter of halmac + * @offset : offset + * @value : value + * Author : Ivan Lin + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +ltecoex_reg_write_88xx(struct halmac_adapter *adapter, u16 offset, u32 value) +{ + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + cnt = 10000; + while ((HALMAC_REG_R8(LTECOEX_ACCESS_CTRL + 3) & BIT(5)) == 0) { + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]lte ready(W)\n"); + return HALMAC_RET_LTECOEX_READY_FAIL; + } + cnt--; + PLTFM_DELAY_US(50); + } + + HALMAC_REG_W32(REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1, value); + HALMAC_REG_W32(LTECOEX_ACCESS_CTRL, 0xC00F0000 | offset); + + return HALMAC_RET_SUCCESS; +} + +static void +pwr_state_88xx(struct halmac_adapter *adapter, enum halmac_mac_power *state) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if ((HALMAC_REG_R8(REG_SYS_FUNC_EN + 1) & BIT(3)) == 0) + *state = HALMAC_MAC_POWER_OFF; + else + *state = HALMAC_MAC_POWER_ON; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_common_88xx.h b/hal/halmac/halmac_88xx/halmac_common_88xx.h new file mode 100644 index 0000000..8b77a5d --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_common_88xx.h @@ -0,0 +1,155 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_COMMON_88XX_H_ +#define _HALMAC_COMMON_88XX_H_ + +#include "../halmac_api.h" +#include "../halmac_pwr_seq_cmd.h" +#include "../halmac_gpio_cmd.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +ofld_func_cfg_88xx(struct halmac_adapter *adapter, + struct halmac_ofld_func_info *info); + +enum halmac_ret_status +dl_drv_rsvd_page_88xx(struct halmac_adapter *adapter, u8 pg_offset, u8 *buf, + u32 size); + +enum halmac_ret_status +dl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf, + u32 size); + +enum halmac_ret_status +get_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value); + +enum halmac_ret_status +set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value); + +enum halmac_ret_status +set_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr, + struct halmac_h2c_header_info *info, u16 *seq_num); + +enum halmac_ret_status +send_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt); + +enum halmac_ret_status +get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +enum halmac_ret_status +mac_debug_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +cfg_parameter_88xx(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *info, u8 full_fifo); + +enum halmac_ret_status +update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id, + u8 *pkt, u32 size); + +enum halmac_ret_status +bcn_ie_filter_88xx(struct halmac_adapter *adapter, + struct halmac_bcn_ie_info *info); + +enum halmac_ret_status +update_datapack_88xx(struct halmac_adapter *adapter, + enum halmac_data_type data_type, + struct halmac_phy_parameter_info *info); + +enum halmac_ret_status +run_datapack_88xx(struct halmac_adapter *adapter, + enum halmac_data_type data_type); + +enum halmac_ret_status +send_bt_coex_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, u8 ack); + +enum halmac_ret_status +dump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel, + u32 start_addr, u32 size, u8 *data); + +u32 +get_fifo_size_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel); + +enum halmac_ret_status +set_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack); + +enum halmac_ret_status +add_ch_info_88xx(struct halmac_adapter *adapter, struct halmac_ch_info *info); + +enum halmac_ret_status +add_extra_ch_info_88xx(struct halmac_adapter *adapter, + struct halmac_ch_extra_info *info); + +enum halmac_ret_status +ctrl_ch_switch_88xx(struct halmac_adapter *adapter, + struct halmac_ch_switch_option *opt); + +enum halmac_ret_status +clear_ch_info_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +enum halmac_ret_status +get_version_88xx(struct halmac_adapter *adapter, struct halmac_ver *ver); + +enum halmac_ret_status +p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info); + +enum halmac_ret_status +query_status_88xx(struct halmac_adapter *adapter, + enum halmac_feature_id feature_id, + enum halmac_cmd_process_status *proc_status, u8 *data, + u32 *size); + +enum halmac_ret_status +cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter, + enum halmac_drv_rsvd_pg_num pg_num); + +enum halmac_ret_status +h2c_lb_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +pwr_seq_parser_88xx(struct halmac_adapter *adapter, + struct halmac_wlan_pwr_cfg **cmd_seq); + +enum halmac_ret_status +parse_intf_phy_88xx(struct halmac_adapter *adapter, + struct halmac_intf_phy_para *param, + enum halmac_intf_phy_platform pltfm, + enum hal_intf_phy intf_phy); + +enum halmac_ret_status +txfifo_is_empty_88xx(struct halmac_adapter *adapter, u32 chk_num); + +u8* +smart_malloc_88xx(struct halmac_adapter *adapter, u32 size, u32 *new_size); + +enum halmac_ret_status +ltecoex_reg_read_88xx(struct halmac_adapter *adapter, u16 offset, u32 *value); + +enum halmac_ret_status +ltecoex_reg_write_88xx(struct halmac_adapter *adapter, u16 offset, u32 value); + +#endif/* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_COMMON_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_efuse_88xx.c b/hal/halmac/halmac_88xx/halmac_efuse_88xx.c new file mode 100644 index 0000000..d271b0c --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_efuse_88xx.c @@ -0,0 +1,1902 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_efuse_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_common_88xx.h" +#include "halmac_init_88xx.h" + +#if HALMAC_88XX_SUPPORT + +#define RSVD_EFUSE_SIZE 16 +#define RSVD_CS_EFUSE_SIZE 24 +#define PROTECT_EFUSE_SIZE 96 +#define FEATURE_DUMP_PHY_EFUSE HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE +#define FEATURE_DUMP_LOG_EFUSE HALMAC_FEATURE_DUMP_LOGICAL_EFUSE + +static enum halmac_cmd_construct_state +efuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +proc_dump_efuse_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg); + +static enum halmac_ret_status +read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + u8 *map); + +static enum halmac_ret_status +eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map); + +static enum halmac_ret_status +read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map); + +static enum halmac_ret_status +proc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, + enum halmac_efuse_read_cfg cfg); + +static enum halmac_ret_status +dump_efuse_fw_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +dump_efuse_drv_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value); + +static enum halmac_ret_status +update_eeprom_mask_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 *updated_mask); + +static enum halmac_ret_status +check_efuse_enough_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 *updated_mask); + +static enum halmac_ret_status +pg_extend_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 word_en, + u8 pre_word_en, u32 eeprom_offset); + +static enum halmac_ret_status +proc_pg_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 word_en, + u8 pre_word_en, u32 eeprom_offset); + +static enum halmac_ret_status +program_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 *updated_mask); + +static void +mask_eeprom_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info); + +/** + * dump_efuse_map_88xx() - dump "physical" efuse map + * @adapter : the adapter of halmac + * @cfg : dump efuse method + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +dump_efuse_map_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg) +{ + u8 *map = NULL; + u8 *efuse_map; + u32 efuse_size = adapter->hw_cfg_info.efuse_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + if (cfg == HALMAC_EFUSE_R_FW && + halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) + PLTFM_MSG_ERR("[ERR]Dump efuse in suspend\n"); + + *proc_status = HALMAC_CMD_PROCESS_IDLE; + adapter->evnt.phy_efuse_map = 1; + + status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + return status; + } + + status = proc_dump_efuse_88xx(adapter, cfg); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dump efuse!!\n"); + return status; + } + + if (adapter->efuse_map_valid == _TRUE) { + *proc_status = HALMAC_CMD_PROCESS_DONE; + efuse_map = adapter->efuse_map; + + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, efuse_size); + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + PLTFM_MEMCPY(map, efuse_map, efuse_size - PROTECT_EFUSE_SIZE); + PLTFM_MEMCPY(map + efuse_size - PROTECT_EFUSE_SIZE + + RSVD_CS_EFUSE_SIZE, + efuse_map + efuse_size - PROTECT_EFUSE_SIZE + + RSVD_CS_EFUSE_SIZE, + PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE - + RSVD_CS_EFUSE_SIZE); + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, + *proc_status, map, efuse_size); + adapter->evnt.phy_efuse_map = 0; + + PLTFM_FREE(map, efuse_size); + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * dump_efuse_map_bt_88xx() - dump "BT physical" efuse map + * @adapter : the adapter of halmac + * @bank : bt efuse bank + * @size : bt efuse map size. get from halmac_get_efuse_size API + * @map : bt efuse map + * Author : Soar / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +dump_efuse_map_bt_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_bank bank, u32 size, u8 *map) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (adapter->hw_cfg_info.bt_efuse_size != size) + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + + if (bank >= HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) { + PLTFM_MSG_ERR("[ERR]Undefined BT bank\n"); + return HALMAC_RET_EFUSE_BANK_INCORRECT; + } + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + status = switch_efuse_bank_88xx(adapter, bank); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + return status; + } + + status = read_hw_efuse_88xx(adapter, 0, size, map); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]read hw efuse\n"); + return status; + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * write_efuse_bt_88xx() - write "BT physical" efuse offset + * @adapter : the adapter of halmac + * @offset : offset + * @value : Write value + * @map : bt efuse map + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +write_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value, + enum halmac_efuse_bank bank) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (offset >= adapter->hw_cfg_info.efuse_size) { + PLTFM_MSG_ERR("[ERR]Offset is too large\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (bank > HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) { + PLTFM_MSG_ERR("[ERR]Undefined BT bank\n"); + return HALMAC_RET_EFUSE_BANK_INCORRECT; + } + + status = switch_efuse_bank_88xx(adapter, bank); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + return status; + } + + status = write_hw_efuse_88xx(adapter, offset, value); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse\n"); + return status; + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * read_efuse_bt_88xx() - read "BT physical" efuse offset + * @adapter : the adapter of halmac + * @offset : offset + * @value : 1 byte efuse value + * @bank : efuse bank + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value, + enum halmac_efuse_bank bank) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status = + &adapter->halmac_state.efuse_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (offset >= adapter->hw_cfg_info.efuse_size) { + PLTFM_MSG_ERR("[ERR]Offset is too large\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (bank > HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) { + PLTFM_MSG_ERR("[ERR]Undefined BT bank\n"); + return HALMAC_RET_EFUSE_BANK_INCORRECT; + } + + status = switch_efuse_bank_88xx(adapter, bank); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + return status; + } + + status = read_efuse_88xx(adapter, offset, 1, value); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]read efuse\n"); + return status; + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_efuse_auto_check_88xx() - check efuse after writing it + * @adapter : the adapter of halmac + * @enable : 1, enable efuse auto check. others, disable + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_efuse_auto_check_88xx(struct halmac_adapter *adapter, u8 enable) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + adapter->efuse_auto_check_en = enable; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * get_efuse_available_size_88xx() - get efuse available size + * @adapter : the adapter of halmac + * @size : physical efuse available size + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size) +{ + enum halmac_ret_status status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = dump_log_efuse_map_88xx(adapter, HALMAC_EFUSE_R_DRV); + + if (status != HALMAC_RET_SUCCESS) + return status; + + *size = adapter->hw_cfg_info.efuse_size - PROTECT_EFUSE_SIZE - + adapter->efuse_end; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * get_efuse_size_88xx() - get "physical" efuse size + * @adapter : the adapter of halmac + * @size : physical efuse size + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + *size = adapter->hw_cfg_info.efuse_size; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * get_log_efuse_size_88xx() - get "logical" efuse size + * @adapter : the adapter of halmac + * @size : logical efuse size + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + *size = adapter->hw_cfg_info.eeprom_size; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * dump_log_efuse_map_88xx() - dump "logical" efuse map + * @adapter : the adapter of halmac + * @cfg : dump efuse method + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +dump_log_efuse_map_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg) +{ + u8 *map = NULL; + u32 size = adapter->hw_cfg_info.eeprom_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status = + &adapter->halmac_state.efuse_state.proc_status; + + if (cfg == HALMAC_EFUSE_R_FW && + halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) + PLTFM_MSG_ERR("[ERR]Dump efuse in suspend\n"); + + *proc_status = HALMAC_CMD_PROCESS_IDLE; + adapter->evnt.log_efuse_map = 1; + + status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + return status; + } + + status = proc_dump_efuse_88xx(adapter, cfg); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dump efuse\n"); + return status; + } + + if (adapter->efuse_map_valid == _TRUE) { + *proc_status = HALMAC_CMD_PROCESS_DONE; + + map = (u8 *)PLTFM_MALLOC(size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, size); + + if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) != + HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, size); + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + + PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, + *proc_status, map, size); + adapter->evnt.log_efuse_map = 0; + + PLTFM_FREE(map, size); + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * read_logical_efuse_88xx() - read logical efuse map 1 byte + * @adapter : the adapter of halmac + * @offset : offset + * @value : 1 byte efuse value + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +read_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value) +{ + u8 *map = NULL; + u32 size = adapter->hw_cfg_info.eeprom_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (offset >= size) { + PLTFM_MSG_ERR("[ERR]Offset is too large\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + return status; + } + + map = (u8 *)PLTFM_MALLOC(size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, size); + + status = read_log_efuse_map_88xx(adapter, map); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]read logical efuse\n"); + PLTFM_FREE(map, size); + return status; + } + + *value = *(map + offset); + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, size); + return HALMAC_RET_ERROR_STATE; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + PLTFM_FREE(map, size); + + return HALMAC_RET_SUCCESS; +} + +/** + * write_log_efuse_88xx() - write "logical" efuse offset + * @adapter : the adapter of halmac + * @offset : offset + * @value : value + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (offset >= adapter->hw_cfg_info.eeprom_size) { + PLTFM_MSG_ERR("[ERR]Offset is too large\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + return status; + } + + status = proc_write_log_efuse_88xx(adapter, offset, value); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write logical efuse\n"); + return status; + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * pg_efuse_by_map_88xx() - pg logical efuse by map + * @adapter : the adapter of halmac + * @info : efuse map information + * @cfg : dump efuse method + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pg_efuse_by_map_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, + enum halmac_efuse_read_cfg cfg) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (info->efuse_map_size != adapter->hw_cfg_info.eeprom_size) { + PLTFM_MSG_ERR("[ERR]map size error\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if ((info->efuse_map_size & 0xF) > 0) { + PLTFM_MSG_ERR("[ERR]not multiple of 16\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (info->efuse_mask_size != info->efuse_map_size >> 4) { + PLTFM_MSG_ERR("[ERR]mask size error\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (!info->efuse_map) { + PLTFM_MSG_ERR("[ERR]map is NULL\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (!info->efuse_mask) { + PLTFM_MSG_ERR("[ERR]mask is NULL\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + return status; + } + + status = proc_pg_efuse_by_map_88xx(adapter, info, cfg); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]pg efuse\n"); + return status; + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * mask_log_efuse_88xx() - mask logical efuse + * @adapter : the adapter of halmac + * @info : efuse map information + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mask_log_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (info->efuse_map_size != adapter->hw_cfg_info.eeprom_size) { + PLTFM_MSG_ERR("[ERR]map size error\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if ((info->efuse_map_size & 0xF) > 0) { + PLTFM_MSG_ERR("[ERR]not multiple of 16\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (info->efuse_mask_size != info->efuse_map_size >> 4) { + PLTFM_MSG_ERR("[ERR]mask size error\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (!info->efuse_map) { + PLTFM_MSG_ERR("[ERR]map is NULL\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (!info->efuse_mask) { + PLTFM_MSG_ERR("[ERR]mask is NULL\n"); + return HALMAC_RET_NULL_POINTER; + } + + mask_eeprom_88xx(adapter, info); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_cmd_construct_state +efuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter) +{ + return adapter->halmac_state.efuse_state.cmd_cnstr_state; +} + +enum halmac_ret_status +switch_efuse_bank_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_bank bank) +{ + u8 reg_value; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_BUSY) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + reg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1); + + if (bank == (reg_value & (BIT(0) | BIT(1)))) + return HALMAC_RET_SUCCESS; + + reg_value &= ~(BIT(0) | BIT(1)); + reg_value |= bank; + HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 1, reg_value); + + reg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1); + if ((reg_value & (BIT(0) | BIT(1))) != bank) + return HALMAC_RET_SWITCH_EFUSE_BANK_FAIL; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +proc_dump_efuse_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg) +{ + u32 h2c_init; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + if (cfg == HALMAC_EFUSE_R_AUTO) { + h2c_init = HALMAC_REG_R32(REG_H2C_PKT_READADDR); + if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE || + h2c_init == 0) + status = dump_efuse_drv_88xx(adapter); + else + status = dump_efuse_fw_88xx(adapter); + } else if (cfg == HALMAC_EFUSE_R_FW) { + status = dump_efuse_fw_88xx(adapter); + } else { + status = dump_efuse_drv_88xx(adapter); + } + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dump efsue drv/fw\n"); + return status; + } + + return status; +} + +enum halmac_ret_status +cnv_efuse_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state) +{ + struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state; + + if (state->cmd_cnstr_state != HALMAC_CMD_CNSTR_IDLE && + state->cmd_cnstr_state != HALMAC_CMD_CNSTR_BUSY && + state->cmd_cnstr_state != HALMAC_CMD_CNSTR_H2C_SENT) + return HALMAC_RET_ERROR_STATE; + + if (state->cmd_cnstr_state == dest_state) + return HALMAC_RET_ERROR_STATE; + + if (dest_state == HALMAC_CMD_CNSTR_BUSY) { + if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_H2C_SENT) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) { + if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_IDLE) + return HALMAC_RET_ERROR_STATE; + } + + state->cmd_cnstr_state = dest_state; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + u8 *map) +{ + u8 enable; + u32 value32; + u32 addr; + u32 tmp32; + u32 cnt; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + /* Read efuse no need 2.5V LDO */ + enable = _FALSE; + status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dis ldo25\n"); + return status; + } + value32 = HALMAC_REG_R32(REG_EFUSE_CTRL); + + for (addr = offset; addr < offset + size; addr++) { + value32 &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR); + value32 |= ((addr & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR); + HALMAC_REG_W32(REG_EFUSE_CTRL, value32 & (~BIT_EF_FLAG)); + + cnt = 1000000; + do { + PLTFM_DELAY_US(1); + tmp32 = HALMAC_REG_R32(REG_EFUSE_CTRL); + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]read\n"); + return HALMAC_RET_EFUSE_R_FAIL; + } + } while ((tmp32 & BIT_EF_FLAG) == 0); + + *(map + addr - offset) = (u8)(tmp32 & BIT_MASK_EF_DATA); + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value) +{ + const u8 unlock_code = 0x69; + u8 value_read = 0, enable; + u32 value32; + u32 tmp32; + u32 cnt; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + adapter->efuse_map_valid = _FALSE; + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, unlock_code); + + /* Enable 2.5V LDO */ + enable = _TRUE; + status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]en ldo25\n"); + return status; + } + + value32 = HALMAC_REG_R32(REG_EFUSE_CTRL); + value32 &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR); + value32 = value32 | ((offset & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) | + (value & BIT_MASK_EF_DATA); + HALMAC_REG_W32(REG_EFUSE_CTRL, value32 | BIT_EF_FLAG); + + cnt = 1000000; + do { + PLTFM_DELAY_US(1); + tmp32 = HALMAC_REG_R32(REG_EFUSE_CTRL); + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]write!!\n"); + return HALMAC_RET_EFUSE_W_FAIL; + } + } while (BIT_EF_FLAG == (tmp32 & BIT_EF_FLAG)); + + HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, 0x00); + + /* Disable 2.5V LDO */ + enable = _FALSE; + status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dis ldo25\n"); + return status; + } + + if (adapter->efuse_auto_check_en == 1) { + if (read_hw_efuse_88xx(adapter, offset, 1, &value_read) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_EFUSE_R_FAIL; + if (value_read != value) { + PLTFM_MSG_ERR("[ERR]efuse compare\n"); + return HALMAC_RET_EFUSE_W_FAIL; + } + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map) +{ + u8 i; + u8 value8; + u8 blk_idx; + u8 word_en; + u8 valid; + u8 hdr; + u8 hdr2 = 0; + u32 eeprom_idx; + u32 efuse_idx = 0; + struct halmac_hw_cfg_info *hw_info = &adapter->hw_cfg_info; + + PLTFM_MEMSET(log_map, 0xFF, hw_info->eeprom_size); + + do { + value8 = *(phy_map + efuse_idx); + hdr = value8; + + if ((hdr & 0x1f) == 0x0f) { + efuse_idx++; + value8 = *(phy_map + efuse_idx); + hdr2 = value8; + if (hdr2 == 0xff) + break; + blk_idx = ((hdr2 & 0xF0) >> 1) | ((hdr >> 5) & 0x07); + word_en = hdr2 & 0x0F; + } else { + blk_idx = (hdr & 0xF0) >> 4; + word_en = hdr & 0x0F; + } + + if (hdr == 0xff) + break; + + efuse_idx++; + + if (efuse_idx >= hw_info->efuse_size - PROTECT_EFUSE_SIZE - 1) + return HALMAC_RET_EEPROM_PARSING_FAIL; + + for (i = 0; i < 4; i++) { + valid = (u8)((~(word_en >> i)) & BIT(0)); + if (valid == 1) { + eeprom_idx = (blk_idx << 3) + (i << 1); + + if ((eeprom_idx + 1) > hw_info->eeprom_size) { + PLTFM_MSG_ERR("[ERR]efuse idx:0x%X\n", + efuse_idx - 1); + + PLTFM_MSG_ERR("[ERR]read hdr:0x%X\n", + hdr); + + PLTFM_MSG_ERR("[ERR]rad hdr2:0x%X\n", + hdr2); + + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + + value8 = *(phy_map + efuse_idx); + *(log_map + eeprom_idx) = value8; + + eeprom_idx++; + efuse_idx++; + + if (efuse_idx > hw_info->efuse_size - + PROTECT_EFUSE_SIZE - 1) + return HALMAC_RET_EEPROM_PARSING_FAIL; + + value8 = *(phy_map + efuse_idx); + *(log_map + eeprom_idx) = value8; + + efuse_idx++; + + if (efuse_idx > hw_info->efuse_size - + PROTECT_EFUSE_SIZE) + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + } + } while (1); + + adapter->efuse_end = efuse_idx; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map) +{ + u8 *local_map = NULL; + u32 efuse_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (adapter->efuse_map_valid == _FALSE) { + efuse_size = adapter->hw_cfg_info.efuse_size; + + local_map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!local_map) { + PLTFM_MSG_ERR("[ERR]local map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + + status = read_efuse_88xx(adapter, 0, efuse_size, local_map); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]read efuse\n"); + PLTFM_FREE(local_map, efuse_size); + return status; + } + + if (!adapter->efuse_map) { + adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!adapter->efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc adapter map\n"); + PLTFM_FREE(local_map, efuse_size); + return HALMAC_RET_MALLOC_FAIL; + } + } + + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + PLTFM_MEMCPY(adapter->efuse_map, local_map, efuse_size); + adapter->efuse_map_valid = _TRUE; + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + PLTFM_FREE(local_map, efuse_size); + } + + if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_EEPROM_PARSING_FAIL; + + return status; +} + +static enum halmac_ret_status +proc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, + enum halmac_efuse_read_cfg cfg) +{ + u8 *updated_mask = NULL; + u32 mask_size = adapter->hw_cfg_info.eeprom_size >> 4; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + updated_mask = (u8 *)PLTFM_MALLOC(mask_size); + if (!updated_mask) { + PLTFM_MSG_ERR("[ERR]malloc updated mask\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(updated_mask, 0x00, mask_size); + + status = update_eeprom_mask_88xx(adapter, info, updated_mask); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]update eeprom mask\n"); + PLTFM_FREE(updated_mask, mask_size); + return status; + } + + status = check_efuse_enough_88xx(adapter, info, updated_mask); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]chk efuse enough\n"); + PLTFM_FREE(updated_mask, mask_size); + return status; + } + + status = program_efuse_88xx(adapter, info, updated_mask); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]pg efuse\n"); + PLTFM_FREE(updated_mask, mask_size); + return status; + } + + PLTFM_FREE(updated_mask, mask_size); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +dump_efuse_drv_88xx(struct halmac_adapter *adapter) +{ + u8 *map = NULL; + u32 efuse_size = adapter->hw_cfg_info.efuse_size; + + if (!adapter->efuse_map) { + adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!adapter->efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc adapter map!!\n"); + reset_ofld_feature_88xx(adapter, + FEATURE_DUMP_PHY_EFUSE); + return HALMAC_RET_MALLOC_FAIL; + } + } + + if (adapter->efuse_map_valid == _FALSE) { + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + + if (read_hw_efuse_88xx(adapter, 0, efuse_size, map) != + HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, efuse_size); + return HALMAC_RET_EFUSE_R_FAIL; + } + + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + PLTFM_MEMCPY(adapter->efuse_map, map, efuse_size); + adapter->efuse_map_valid = _TRUE; + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + PLTFM_FREE(map, efuse_size); + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +dump_efuse_fw_88xx(struct halmac_adapter *adapter) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + u32 efuse_size = adapter->hw_cfg_info.efuse_size; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + hdr_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE; + hdr_info.content_size = 0; + hdr_info.ack = _TRUE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + adapter->halmac_state.efuse_state.seq_num = seq_num; + + if (!adapter->efuse_map) { + adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!adapter->efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc adapter map\n"); + reset_ofld_feature_88xx(adapter, + FEATURE_DUMP_PHY_EFUSE); + return HALMAC_RET_MALLOC_FAIL; + } + } + + if (adapter->efuse_map_valid == _FALSE) { + status = send_h2c_pkt_88xx(adapter, h2c_buf); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c pkt\n"); + reset_ofld_feature_88xx(adapter, + FEATURE_DUMP_PHY_EFUSE); + return status; + } + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value) +{ + u8 byte1; + u8 byte2; + u8 blk; + u8 blk_idx; + u8 hdr; + u8 hdr2; + u8 *map = NULL; + u32 eeprom_size = adapter->hw_cfg_info.eeprom_size; + u32 end; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + map = (u8 *)PLTFM_MALLOC(eeprom_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, eeprom_size); + + status = read_log_efuse_map_88xx(adapter, map); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]read logical efuse\n"); + PLTFM_FREE(map, eeprom_size); + return status; + } + + if (*(map + offset) != value) { + end = adapter->efuse_end; + blk = (u8)(offset >> 3); + blk_idx = (u8)((offset & (8 - 1)) >> 1); + + if (offset > 0x7f) { + hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F; + hdr2 = (u8)(((blk & 0x78) << 1) + + ((0x1 << blk_idx) ^ 0x0F)); + } else { + hdr = (u8)((blk << 4) + ((0x01 << blk_idx) ^ 0x0F)); + } + + if ((offset & 1) == 0) { + byte1 = value; + byte2 = *(map + offset + 1); + } else { + byte1 = *(map + offset - 1); + byte2 = value; + } + + if (offset > 0x7f) { + if (adapter->hw_cfg_info.efuse_size <= + 4 + PROTECT_EFUSE_SIZE + end) { + PLTFM_FREE(map, eeprom_size); + return HALMAC_RET_EFUSE_NOT_ENOUGH; + } + + status = write_hw_efuse_88xx(adapter, end, hdr); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + + status = write_hw_efuse_88xx(adapter, end + 1, hdr2); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + + status = write_hw_efuse_88xx(adapter, end + 2, byte1); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + + status = write_hw_efuse_88xx(adapter, end + 3, byte2); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + } else { + if (adapter->hw_cfg_info.efuse_size <= + 3 + PROTECT_EFUSE_SIZE + end) { + PLTFM_FREE(map, eeprom_size); + return HALMAC_RET_EFUSE_NOT_ENOUGH; + } + + status = write_hw_efuse_88xx(adapter, end, hdr); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + + status = write_hw_efuse_88xx(adapter, end + 1, byte1); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + + status = write_hw_efuse_88xx(adapter, end + 2, byte2); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + } + } + + PLTFM_FREE(map, eeprom_size); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map) +{ + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (adapter->efuse_map_valid == _TRUE) { + PLTFM_MEMCPY(map, adapter->efuse_map + offset, size); + } else { + if (read_hw_efuse_88xx(adapter, offset, size, map) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_EFUSE_R_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +update_eeprom_mask_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 *updated_mask) +{ + u8 *map = NULL; + u8 clr_bit = 0; + u32 eeprom_size = adapter->hw_cfg_info.eeprom_size; + u8 *map_pg; + u8 *efuse_mask; + u16 i; + u16 j; + u16 map_offset; + u16 mask_offset; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + map = (u8 *)PLTFM_MALLOC(eeprom_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, eeprom_size); + + PLTFM_MEMSET(updated_mask, 0x00, info->efuse_mask_size); + + status = read_log_efuse_map_88xx(adapter, map); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + + map_pg = info->efuse_map; + efuse_mask = info->efuse_mask; + + for (i = 0; i < info->efuse_mask_size; i++) + *(updated_mask + i) = *(efuse_mask + i); + + for (i = 0; i < info->efuse_map_size; i += 16) { + for (j = 0; j < 16; j += 2) { + map_offset = i + j; + mask_offset = i >> 4; + if (*(u16 *)(map_pg + map_offset) == + *(u16 *)(map + map_offset)) { + switch (j) { + case 0: + clr_bit = BIT(4); + break; + case 2: + clr_bit = BIT(5); + break; + case 4: + clr_bit = BIT(6); + break; + case 6: + clr_bit = BIT(7); + break; + case 8: + clr_bit = BIT(0); + break; + case 10: + clr_bit = BIT(1); + break; + case 12: + clr_bit = BIT(2); + break; + case 14: + clr_bit = BIT(3); + break; + default: + break; + } + *(updated_mask + mask_offset) &= ~clr_bit; + } + } + } + + PLTFM_FREE(map, eeprom_size); + + return status; +} + +static enum halmac_ret_status +check_efuse_enough_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 *updated_mask) +{ + u8 pre_word_en; + u16 i; + u16 j; + u32 eeprom_offset; + u32 pg_num = 0; + + for (i = 0; i < info->efuse_map_size; i = i + 8) { + eeprom_offset = i; + + if ((eeprom_offset & 7) > 0) + pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F); + else + pre_word_en = (*(updated_mask + (i >> 4)) >> 4); + + if (pre_word_en > 0) { + if (eeprom_offset > 0x7f) { + pg_num += 2; + for (j = 0; j < 4; j++) { + if (((pre_word_en >> j) & 0x1) > 0) + pg_num += 2; + } + } else { + pg_num++; + for (j = 0; j < 4; j++) { + if (((pre_word_en >> j) & 0x1) > 0) + pg_num += 2; + } + } + } + } + + if (adapter->hw_cfg_info.efuse_size <= + (pg_num + PROTECT_EFUSE_SIZE + adapter->efuse_end)) + return HALMAC_RET_EFUSE_NOT_ENOUGH; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +pg_extend_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 word_en, + u8 pre_word_en, u32 eeprom_offset) +{ + u8 blk; + u8 hdr; + u8 hdr2; + u16 i; + u32 efuse_end; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + efuse_end = adapter->efuse_end; + + blk = (u8)(eeprom_offset >> 3); + hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F; + hdr2 = (u8)(((blk & 0x78) << 1) + word_en); + + status = write_hw_efuse_88xx(adapter, efuse_end, hdr); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse\n"); + return status; + } + + status = write_hw_efuse_88xx(adapter, efuse_end + 1, hdr2); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse(+1)\n"); + return status; + } + + efuse_end = efuse_end + 2; + for (i = 0; i < 4; i++) { + if (((pre_word_en >> i) & 0x1) > 0) { + status = write_hw_efuse_88xx(adapter, efuse_end, + *(info->efuse_map + + eeprom_offset + + (i << 1))); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse(<<1)\n"); + return status; + } + + status = write_hw_efuse_88xx(adapter, efuse_end + 1, + *(info->efuse_map + + eeprom_offset + (i << 1) + + 1)); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse(<<1)+1\n"); + return status; + } + efuse_end = efuse_end + 2; + } + } + adapter->efuse_end = efuse_end; + return status; +} + +static enum halmac_ret_status +proc_pg_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 word_en, + u8 pre_word_en, u32 eeprom_offset) +{ + u8 blk; + u8 hdr; + u16 i; + u32 efuse_end; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + efuse_end = adapter->efuse_end; + + blk = (u8)(eeprom_offset >> 3); + hdr = (u8)((blk << 4) + word_en); + + status = write_hw_efuse_88xx(adapter, efuse_end, hdr); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse\n"); + return status; + } + efuse_end = efuse_end + 1; + for (i = 0; i < 4; i++) { + if (((pre_word_en >> i) & 0x1) > 0) { + status = write_hw_efuse_88xx(adapter, efuse_end, + *(info->efuse_map + + eeprom_offset + + (i << 1))); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse(<<1)\n"); + return status; + } + status = write_hw_efuse_88xx(adapter, efuse_end + 1, + *(info->efuse_map + + eeprom_offset + (i << 1) + + 1)); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse(<<1)+1\n"); + return status; + } + efuse_end = efuse_end + 2; + } + } + adapter->efuse_end = efuse_end; + return status; +} + +static enum halmac_ret_status +program_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 *updated_mask) +{ + u8 pre_word_en; + u8 word_en; + u16 i; + u32 eeprom_offset; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + for (i = 0; i < info->efuse_map_size; i = i + 8) { + eeprom_offset = i; + + if (((eeprom_offset >> 3) & 1) > 0) { + pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F); + word_en = pre_word_en ^ 0x0F; + } else { + pre_word_en = (*(updated_mask + (i >> 4)) >> 4); + word_en = pre_word_en ^ 0x0F; + } + + if (pre_word_en > 0) { + if (eeprom_offset > 0x7f) { + status = pg_extend_efuse_88xx(adapter, info, + word_en, + pre_word_en, + eeprom_offset); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]extend efuse\n"); + return status; + } + } else { + status = proc_pg_efuse_88xx(adapter, info, + word_en, + pre_word_en, + eeprom_offset); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]extend efuse"); + return status; + } + } + } + } + + return status; +} + +static void +mask_eeprom_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info) +{ + u8 pre_word_en; + u8 *updated_mask; + u8 *efuse_map; + u16 i; + u16 j; + u32 offset; + + updated_mask = info->efuse_mask; + efuse_map = info->efuse_map; + + for (i = 0; i < info->efuse_map_size; i = i + 8) { + offset = i; + + if (((offset >> 3) & 1) > 0) + pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F); + else + pre_word_en = (*(updated_mask + (i >> 4)) >> 4); + + for (j = 0; j < 4; j++) { + if (((pre_word_en >> j) & 0x1) == 0) { + *(efuse_map + offset + (j << 1)) = 0xFF; + *(efuse_map + offset + (j << 1) + 1) = 0xFF; + } + } + } +} + +enum halmac_ret_status +get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seg_id; + u8 seg_size; + u8 seq_num; + u8 fw_rc; + u8 *map = NULL; + u32 eeprom_size = adapter->hw_cfg_info.eeprom_size; + struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state; + enum halmac_cmd_process_status proc_status; + + seq_num = (u8)EFUSE_DATA_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + seg_id = (u8)EFUSE_DATA_GET_SEGMENT_ID(buf); + seg_size = (u8)EFUSE_DATA_GET_SEGMENT_SIZE(buf); + if (seg_id == 0) + adapter->efuse_seg_size = seg_size; + + map = (u8 *)PLTFM_MALLOC(eeprom_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, eeprom_size); + + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + PLTFM_MEMCPY(adapter->efuse_map + seg_id * adapter->efuse_seg_size, + buf + C2H_DATA_OFFSET_88XX, seg_size); + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + if (EFUSE_DATA_GET_END_SEGMENT(buf) == _FALSE) { + PLTFM_FREE(map, eeprom_size); + return HALMAC_RET_SUCCESS; + } + + fw_rc = state->fw_rc; + + if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) { + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + adapter->efuse_map_valid = _TRUE; + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + if (adapter->evnt.phy_efuse_map == 1) { + PLTFM_EVENT_SIG(FEATURE_DUMP_PHY_EFUSE, + proc_status, adapter->efuse_map, + adapter->hw_cfg_info.efuse_size); + adapter->evnt.phy_efuse_map = 0; + } + + if (adapter->evnt.log_efuse_map == 1) { + if (eeprom_parser_88xx(adapter, adapter->efuse_map, + map) != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + PLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE, proc_status, + map, eeprom_size); + adapter->evnt.log_efuse_map = 0; + } + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + + if (adapter->evnt.phy_efuse_map == 1) { + PLTFM_EVENT_SIG(FEATURE_DUMP_PHY_EFUSE, proc_status, + &state->fw_rc, 1); + adapter->evnt.phy_efuse_map = 0; + } + + if (adapter->evnt.log_efuse_map == 1) { + PLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE, proc_status, + &state->fw_rc, 1); + adapter->evnt.log_efuse_map = 0; + } + } + + PLTFM_FREE(map, eeprom_size); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status, + u8 *data, u32 *size) +{ + u8 *map = NULL; + u32 efuse_size = adapter->hw_cfg_info.efuse_size; + struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state; + + *proc_status = state->proc_status; + + if (!data) + return HALMAC_RET_NULL_POINTER; + + if (!size) + return HALMAC_RET_NULL_POINTER; + + if (*proc_status == HALMAC_CMD_PROCESS_DONE) { + if (*size < efuse_size) { + *size = efuse_size; + return HALMAC_RET_BUFFER_TOO_SMALL; + } + + *size = efuse_size; + + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, efuse_size); + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + PLTFM_MEMCPY(map, adapter->efuse_map, + efuse_size - PROTECT_EFUSE_SIZE); + PLTFM_MEMCPY(map + efuse_size - PROTECT_EFUSE_SIZE + + RSVD_CS_EFUSE_SIZE, + adapter->efuse_map + efuse_size - + PROTECT_EFUSE_SIZE + RSVD_CS_EFUSE_SIZE, + PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE - + RSVD_CS_EFUSE_SIZE); + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + PLTFM_MEMCPY(data, map, *size); + + PLTFM_FREE(map, efuse_size); + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_dump_log_efuse_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status, + u8 *data, u32 *size) +{ + u8 *map = NULL; + u32 eeprom_size = adapter->hw_cfg_info.eeprom_size; + struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state; + + *proc_status = state->proc_status; + + if (!data) + return HALMAC_RET_NULL_POINTER; + + if (!size) + return HALMAC_RET_NULL_POINTER; + + if (*proc_status == HALMAC_CMD_PROCESS_DONE) { + if (*size < eeprom_size) { + *size = eeprom_size; + return HALMAC_RET_BUFFER_TOO_SMALL; + } + + *size = eeprom_size; + + map = (u8 *)PLTFM_MALLOC(eeprom_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, eeprom_size); + + if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) != + HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + + PLTFM_MEMCPY(data, map, *size); + + PLTFM_FREE(map, eeprom_size); + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num = 0; + u8 fw_rc; + struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + + return HALMAC_RET_SUCCESS; +} + +u32 +get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter) +{ + return PROTECT_EFUSE_SIZE; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_efuse_88xx.h b/hal/halmac/halmac_88xx/halmac_efuse_88xx.h new file mode 100644 index 0000000..5bf97fa --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_efuse_88xx.h @@ -0,0 +1,105 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_EFUSE_88XX_H_ +#define _HALMAC_EFUSE_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +dump_efuse_map_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg); + +enum halmac_ret_status +dump_efuse_map_bt_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_bank bank, u32 size, u8 *map); + +enum halmac_ret_status +write_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value, + enum halmac_efuse_bank bank); + +enum halmac_ret_status +read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value, + enum halmac_efuse_bank bank); + +enum halmac_ret_status +cfg_efuse_auto_check_88xx(struct halmac_adapter *adapter, u8 enable); + +enum halmac_ret_status +get_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size); + +enum halmac_ret_status +get_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size); + +enum halmac_ret_status +get_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size); + +enum halmac_ret_status +dump_log_efuse_map_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg); + +enum halmac_ret_status +read_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value); + +enum halmac_ret_status +write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value); + +enum halmac_ret_status +pg_efuse_by_map_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, + enum halmac_efuse_read_cfg cfg); + +enum halmac_ret_status +mask_log_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info); + +enum halmac_ret_status +read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map); + +enum halmac_ret_status +write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value); + +enum halmac_ret_status +switch_efuse_bank_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_bank bank); + +enum halmac_ret_status +get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +enum halmac_ret_status +cnv_efuse_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state); + +enum halmac_ret_status +get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status, + u8 *data, u32 *size); + +enum halmac_ret_status +get_dump_log_efuse_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status, + u8 *data, u32 *size); + +enum halmac_ret_status +get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +u32 +get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_EFUSE_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_flash_88xx.c b/hal/halmac/halmac_88xx/halmac_flash_88xx.c new file mode 100644 index 0000000..07b2e36 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_flash_88xx.c @@ -0,0 +1,316 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_flash_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_common_88xx.h" + +#if HALMAC_88XX_SUPPORT + +/** + * download_flash_88xx() -download firmware to flash + * @adapter : the adapter of halmac + * @fw_bin : pointer to fw + * @size : fw size + * @rom_addr : flash start address where fw should be download + * Author : Pablo Chiu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size, + u32 rom_addr) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status rc; + struct halmac_h2c_header_info hdr_info; + u8 value8; + u8 restore[3]; + u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0}; + u16 seq_num = 0; + u16 h2c_info_offset; + u32 pkt_size; + u32 mem_offset; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + value8 = HALMAC_REG_R8(REG_CR + 1); + restore[0] = value8; + value8 = (u8)(value8 | BIT(0)); + HALMAC_REG_W8(REG_CR + 1, value8); + + value8 = HALMAC_REG_R8(REG_BCN_CTRL); + restore[1] = value8; + value8 = (u8)((value8 & ~(BIT(3))) | BIT(4)); + HALMAC_REG_W8(REG_BCN_CTRL, value8); + + value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2); + restore[2] = value8; + value8 = (u8)(value8 & ~(BIT(6))); + HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8); + + /* Download FW to Flash flow */ + h2c_info_offset = adapter->txff_alloc.rsvd_h2c_info_addr - + adapter->txff_alloc.rsvd_boundary; + mem_offset = 0; + + while (size != 0) { + if (size >= (DL_FLASH_RSVDPG_SIZE - 48)) + pkt_size = DL_FLASH_RSVDPG_SIZE - 48; + else + pkt_size = size; + + rc = dl_rsvd_page_88xx(adapter, + adapter->txff_alloc.rsvd_h2c_info_addr, + fw_bin + mem_offset, pkt_size); + if (rc != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n"); + return rc; + } + + DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x02); + DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_offset); + DOWNLOAD_FLASH_SET_SIZE(h2c_buf, pkt_size); + DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, rom_addr); + + hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH; + hdr_info.content_size = 20; + hdr_info.ack = _TRUE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + rc = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (rc != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + return rc; + } + + value8 = HALMAC_REG_R8(REG_MCUTST_I); + value8 |= BIT(0); + HALMAC_REG_W8(REG_MCUTST_I, value8); + + rom_addr += pkt_size; + mem_offset += pkt_size; + size -= pkt_size; + + while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) + PLTFM_DELAY_US(1000); + + if (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) { + PLTFM_MSG_ERR("[ERR]dl flash!!\n"); + return HALMAC_RET_DLFW_FAIL; + } + } + + HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]); + HALMAC_REG_W8(REG_BCN_CTRL, restore[1]); + HALMAC_REG_W8(REG_CR + 1, restore[0]); + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * read_flash_88xx() -read data from flash + * @adapter : the adapter of halmac + * @addr : flash start address where fw should be read + * Author : Pablo Chiu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +read_flash_88xx(struct halmac_adapter *adapter, u32 addr) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status; + struct halmac_h2c_header_info hdr_info; + u8 value8; + u8 restore[3]; + u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0}; + u16 seq_num = 0; + u16 h2c_info_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + u16 rsvd_pg_addr = adapter->txff_alloc.rsvd_boundary; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + value8 = HALMAC_REG_R8(REG_CR + 1); + restore[0] = value8; + value8 = (u8)(value8 | BIT(0)); + HALMAC_REG_W8(REG_CR + 1, value8); + + value8 = HALMAC_REG_R8(REG_BCN_CTRL); + restore[1] = value8; + value8 = (u8)((value8 & ~(BIT(3))) | BIT(4)); + HALMAC_REG_W8(REG_BCN_CTRL, value8); + + value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2); + restore[2] = value8; + value8 = (u8)(value8 & ~(BIT(6))); + HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8); + + HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, h2c_info_addr); + value8 = HALMAC_REG_R8(REG_MCUTST_I); + value8 |= BIT(0); + HALMAC_REG_W8(REG_MCUTST_I, value8); + + /* Construct H2C Content */ + DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x03); + DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_addr - rsvd_pg_addr); + DOWNLOAD_FLASH_SET_SIZE(h2c_buf, 4096); + DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr); + + /* Fill in H2C Header */ + hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH; + hdr_info.content_size = 16; + hdr_info.ack = _TRUE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + /* Send H2C Cmd Packet */ + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + return status; + } + + while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) + PLTFM_DELAY_US(1000); + + HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, rsvd_pg_addr); + HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]); + HALMAC_REG_W8(REG_BCN_CTRL, restore[1]); + HALMAC_REG_W8(REG_CR + 1, restore[0]); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * erase_flash_88xx() -erase flash data + * @adapter : the adapter of halmac + * @erase_cmd : erase command + * @addr : flash start address where fw should be erased + * Author : Pablo Chiu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr) +{ + enum halmac_ret_status status; + struct halmac_h2c_header_info hdr_info; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 value8; + u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0}; + u16 seq_num = 0; + u32 cnt; + + /* Construct H2C Content */ + DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, erase_cmd); + DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, 0); + DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr); + DOWNLOAD_FLASH_SET_SIZE(h2c_buf, 0); + + value8 = HALMAC_REG_R8(REG_MCUTST_I); + value8 |= BIT(0); + HALMAC_REG_W8(REG_MCUTST_I, value8); + + /* Fill in H2C Header */ + hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH; + hdr_info.content_size = 16; + hdr_info.ack = _TRUE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + /* Send H2C Cmd Packet */ + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + + cnt = 5000; + while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0 && cnt != 0) { + PLTFM_DELAY_US(1000); + cnt--; + } + + if (cnt == 0) + return HALMAC_RET_FAIL; + else + return HALMAC_RET_SUCCESS; +} + +/** + * check_flash_88xx() -check flash data + * @adapter : the adapter of halmac + * @fw_bin : pointer to fw + * @size : fw size + * @addr : flash start address where fw should be checked + * Author : Pablo Chiu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size, + u32 addr) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 value8; + u16 i; + u16 residue; + u16 pg_addr; + u32 pkt_size; + u32 start_page; + u32 cnt; + + pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + + while (size != 0) { + start_page = ((pg_addr << 7) >> 12) + 0x780; + residue = (pg_addr << 7) & (4096 - 1); + + if (size >= DL_FLASH_RSVDPG_SIZE) + pkt_size = DL_FLASH_RSVDPG_SIZE; + else + pkt_size = size; + + read_flash_88xx(adapter, addr); + + cnt = 0; + while (cnt < pkt_size) { + HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)(start_page)); + for (i = 0x8000 + residue; i <= 0x8FFF; i++) { + value8 = HALMAC_REG_R8(i); + if (*fw_bin != value8) { + PLTFM_MSG_ERR("[ERR]check flash!!\n"); + return HALMAC_RET_FAIL; + } + + fw_bin++; + cnt++; + if (cnt == pkt_size) + break; + } + residue = 0; + start_page++; + } + addr += pkt_size; + size -= pkt_size; + } + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_flash_88xx.h b/hal/halmac/halmac_88xx/halmac_flash_88xx.h new file mode 100644 index 0000000..932ec15 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_flash_88xx.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_FLASH_88XX_H_ +#define _HALMAC_FLASH_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size, + u32 rom_addr); + +enum halmac_ret_status +read_flash_88xx(struct halmac_adapter *adapter, u32 addr); + +enum halmac_ret_status +erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr); + +enum halmac_ret_status +check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size, + u32 addr); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_FLASH_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_fw_88xx.c b/hal/halmac/halmac_88xx/halmac_fw_88xx.c new file mode 100644 index 0000000..1a6d44e --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_fw_88xx.c @@ -0,0 +1,1134 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_fw_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_common_88xx.h" +#include "halmac_init_88xx.h" + +#if HALMAC_88XX_SUPPORT + +#define DLFW_RESTORE_REG_NUM 6 +#define ILLEGAL_KEY_GROUP 0xFAAAAA00 + +/* Max dlfw size can not over 31K, due to SDIO HW limitation */ +#define DLFW_PKT_SIZE_LIMIT 31744 + +#define ID_INFORM_DLEMEM_RDY 0x80 +#define ID_INFORM_ENETR_CPU_SLEEP 0x20 +#define ID_CHECK_DLEMEM_RDY 0x80 +#define ID_CHECK_ENETR_CPU_SLEEP 0x05 + +#define FW_STATUS_CHK_FATAL (BIT(1) | BIT(20)) +#define FW_STATUS_CHK_ERR (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | \ + BIT(9) | BIT(12) | BIT(14) | BIT(15) | \ + BIT(16) | BIT(17) | BIT(18) | BIT(19) | \ + BIT(21) | BIT(22) | BIT(25)) +#define FW_STATUS_CHK_WARN ~(FW_STATUS_CHK_FATAL | FW_STATUS_CHK_ERR) + +struct halmac_backup_info { + u32 mac_register; + u32 value; + u8 length; +}; + +static enum halmac_ret_status +update_fw_info_88xx(struct halmac_adapter *adapter, u8 *fw_bin); + +static void +restore_mac_reg_88xx(struct halmac_adapter *adapter, + struct halmac_backup_info *info, u32 num); + +static enum halmac_ret_status +dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest, + u32 size); + +static enum halmac_ret_status +dlfw_end_flow_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +free_dl_fw_end_flow_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +send_fwpkt_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *fw_bin, + u32 size); + +static enum halmac_ret_status +iddma_dlfw_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 len, + u8 first); + +static enum halmac_ret_status +iddma_en_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 ctrl); + +static enum halmac_ret_status +check_fw_chksum_88xx(struct halmac_adapter *adapter, u32 mem_addr); + +static void +fw_fatal_status_debug_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +start_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size, + u32 dl_addr, u8 emem_only); + +static enum halmac_ret_status +chk_fw_size_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size); + +static void +chk_h2c_ver_88xx(struct halmac_adapter *adapter, u8 *fw_bin); + +static void +wlan_cpu_en_88xx(struct halmac_adapter *adapter, u8 enable); + +static void +pltfm_reset_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +proc_send_general_info_88xx(struct halmac_adapter *adapter, + struct halmac_general_info *info); + +static enum halmac_ret_status +proc_send_phydm_info_88xx(struct halmac_adapter *adapter, + struct halmac_general_info *info); + +/** + * download_firmware_88xx() - download Firmware + * @adapter : the adapter of halmac + * @fw_bin : firmware bin + * @size : firmware size + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +download_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size) +{ + u8 value8; + u32 bckp_idx = 0; + u32 lte_coex_backup = 0; + struct halmac_backup_info bckp[DLFW_RESTORE_REG_NUM]; + enum halmac_ret_status status; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) + return HALMAC_RET_POWER_STATE_INVALID; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = chk_fw_size_88xx(adapter, fw_bin, size); + if (status != HALMAC_RET_SUCCESS) + return status; + + chk_h2c_ver_88xx(adapter, fw_bin); + + if (adapter->halmac_state.wlcpu_mode == HALMAC_WLCPU_ENTER_SLEEP) + PLTFM_MSG_WARN("[WARN]Enter Sleep..zZZ\n"); + + adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + + status = ltecoex_reg_read_88xx(adapter, 0x38, <e_coex_backup); + if (status != HALMAC_RET_SUCCESS) + return status; + + wlan_cpu_en_88xx(adapter, 0); + + /* set HIQ to hi priority */ + bckp[bckp_idx].length = 1; + bckp[bckp_idx].mac_register = REG_TXDMA_PQ_MAP + 1; + bckp[bckp_idx].value = HALMAC_REG_R8(REG_TXDMA_PQ_MAP + 1); + bckp_idx++; + value8 = HALMAC_DMA_MAPPING_HIGH << 6; + HALMAC_REG_W8(REG_TXDMA_PQ_MAP + 1, value8); + + /* DLFW only use HIQ, map HIQ to hi priority */ + adapter->pq_map[HALMAC_PQ_MAP_HI] = HALMAC_DMA_MAPPING_HIGH; + bckp[bckp_idx].length = 1; + bckp[bckp_idx].mac_register = REG_CR; + bckp[bckp_idx].value = HALMAC_REG_R8(REG_CR); + bckp_idx++; + bckp[bckp_idx].length = 4; + bckp[bckp_idx].mac_register = REG_H2CQ_CSR; + bckp[bckp_idx].value = BIT(31); + bckp_idx++; + value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; + HALMAC_REG_W8(REG_CR, value8); + HALMAC_REG_W32(REG_H2CQ_CSR, BIT(31)); + + /* Config hi priority queue and public priority queue page number */ + bckp[bckp_idx].length = 2; + bckp[bckp_idx].mac_register = REG_FIFOPAGE_INFO_1; + bckp[bckp_idx].value = HALMAC_REG_R16(REG_FIFOPAGE_INFO_1); + bckp_idx++; + bckp[bckp_idx].length = 4; + bckp[bckp_idx].mac_register = REG_RQPN_CTRL_2; + bckp[bckp_idx].value = HALMAC_REG_R32(REG_RQPN_CTRL_2) | BIT(31); + bckp_idx++; + HALMAC_REG_W16(REG_FIFOPAGE_INFO_1, 0x200); + HALMAC_REG_W32(REG_RQPN_CTRL_2, bckp[bckp_idx - 1].value); + + /* Disable beacon related functions */ + value8 = HALMAC_REG_R8(REG_BCN_CTRL); + bckp[bckp_idx].length = 1; + bckp[bckp_idx].mac_register = REG_BCN_CTRL; + bckp[bckp_idx].value = value8; + bckp_idx++; + value8 = (u8)((value8 & (~BIT(3))) | BIT(4)); + HALMAC_REG_W8(REG_BCN_CTRL, value8); + + if (adapter->intf == HALMAC_INTERFACE_SDIO) + HALMAC_REG_R32(REG_SDIO_FREE_TXPG); + + pltfm_reset_88xx(adapter); + + status = start_dlfw_88xx(adapter, fw_bin, size, 0, 0); + + restore_mac_reg_88xx(adapter, bckp, DLFW_RESTORE_REG_NUM); + + if (status != HALMAC_RET_SUCCESS) + goto DLFW_FAIL; + + status = dlfw_end_flow_88xx(adapter); + if (status != HALMAC_RET_SUCCESS) + goto DLFW_FAIL; + + status = ltecoex_reg_write_88xx(adapter, 0x38, lte_coex_backup); + if (status != HALMAC_RET_SUCCESS) + return status; + + adapter->halmac_state.dlfw_state = HALMAC_DLFW_DONE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; + +DLFW_FAIL: + + /* Disable FWDL_EN */ + value8 = HALMAC_REG_R8(REG_MCUFW_CTRL); + value8 &= ~BIT(0); + HALMAC_REG_W8(REG_MCUFW_CTRL, value8); + + value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1); + value8 |= BIT(2); + HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8); + + if (ltecoex_reg_write_88xx(adapter, 0x38, lte_coex_backup) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_LTECOEX_READY_FAIL; + + return status; +} + +static enum halmac_ret_status +start_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size, + u32 dl_addr, u8 emem_only) +{ + u8 *cur_fw; + u16 value16; + u32 imem_size; + u32 dmem_size; + u32 emem_size = 0; + u32 addr; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status; + + dmem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE)); + imem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE)); + if (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4))) + emem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE)); + + dmem_size = rtk_le32_to_cpu(dmem_size); + imem_size = rtk_le32_to_cpu(imem_size); + emem_size = rtk_le32_to_cpu(emem_size); + + dmem_size += WLAN_FW_HDR_CHKSUM_SIZE; + imem_size += WLAN_FW_HDR_CHKSUM_SIZE; + if (emem_size != 0) + emem_size += WLAN_FW_HDR_CHKSUM_SIZE; + + if (emem_only == 1) { + if (!emem_size) + return HALMAC_RET_SUCCESS; + goto DLFW_EMEM; + } + + value16 = (u16)(HALMAC_REG_R16(REG_MCUFW_CTRL) & 0x3800); + value16 |= BIT(0); + HALMAC_REG_W16(REG_MCUFW_CTRL, value16); + + cur_fw = fw_bin + WLAN_FW_HDR_SIZE; + addr = *((u32 *)(fw_bin + WLAN_FW_HDR_DMEM_ADDR)); + addr = rtk_le32_to_cpu(addr) & ~BIT(31); + status = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, dmem_size); + if (status != HALMAC_RET_SUCCESS) + return status; + + cur_fw = fw_bin + WLAN_FW_HDR_SIZE + dmem_size; + addr = *((u32 *)(fw_bin + WLAN_FW_HDR_IMEM_ADDR)); + addr = rtk_le32_to_cpu(addr) & ~BIT(31); + status = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, imem_size); + if (status != HALMAC_RET_SUCCESS) + return status; + +DLFW_EMEM: + if (emem_size) { + cur_fw = fw_bin + WLAN_FW_HDR_SIZE + + dmem_size + imem_size; + addr = *((u32 *)(fw_bin + WLAN_FW_HDR_EMEM_ADDR)); + addr = rtk_le32_to_cpu(addr) & ~BIT(31); + status = dlfw_to_mem_88xx(adapter, cur_fw, dl_addr << 7, addr, + emem_size); + if (status != HALMAC_RET_SUCCESS) + return status; + + if (emem_only == 1) + return HALMAC_RET_SUCCESS; + } + + update_fw_info_88xx(adapter, fw_bin); + init_ofld_feature_state_machine_88xx(adapter); + + return HALMAC_RET_SUCCESS; +} + +static void +chk_h2c_ver_88xx(struct halmac_adapter *adapter, u8 *fw_bin) +{ + u16 halmac_h2c_ver; + u16 fw_h2c_ver; + + fw_h2c_ver = *((u16 *)(fw_bin + WLAN_FW_HDR_H2C_FMT_VER)); + fw_h2c_ver = rtk_le16_to_cpu(fw_h2c_ver); + halmac_h2c_ver = H2C_FORMAT_VERSION; + + PLTFM_MSG_TRACE("[TRACE]halmac h2c ver = %x, fw h2c ver = %x!!\n", + halmac_h2c_ver, fw_h2c_ver); + + if (fw_h2c_ver != halmac_h2c_ver) + PLTFM_MSG_WARN("[WARN]H2C/C2H ver is compatible!!\n"); +} + +static enum halmac_ret_status +chk_fw_size_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size) +{ + u32 imem_size; + u32 dmem_size; + u32 emem_size = 0; + u32 real_size; + + if (size < WLAN_FW_HDR_SIZE) { + PLTFM_MSG_ERR("[ERR]FW size error!\n"); + return HALMAC_RET_FW_SIZE_ERR; + } + + dmem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE)); + imem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE)); + if (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4))) + emem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE)); + + dmem_size = rtk_le32_to_cpu(dmem_size); + imem_size = rtk_le32_to_cpu(imem_size); + emem_size = rtk_le32_to_cpu(emem_size); + + dmem_size += WLAN_FW_HDR_CHKSUM_SIZE; + imem_size += WLAN_FW_HDR_CHKSUM_SIZE; + if (emem_size != 0) + emem_size += WLAN_FW_HDR_CHKSUM_SIZE; + + real_size = WLAN_FW_HDR_SIZE + dmem_size + imem_size + emem_size; + if (size != real_size) { + PLTFM_MSG_ERR("[ERR]size != real size!\n"); + return HALMAC_RET_FW_SIZE_ERR; + } + + return HALMAC_RET_SUCCESS; +} + +static void +wlan_cpu_en_88xx(struct halmac_adapter *adapter, u8 enable) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (enable == 1) { + /* cpu io interface enable or disable */ + value8 = HALMAC_REG_R8(REG_RSV_CTRL + 1); + value8 |= BIT(0); + HALMAC_REG_W8(REG_RSV_CTRL + 1, value8); + + /* cpu enable or disable */ + value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1); + value8 |= BIT(2); + HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8); + + } else { + /* cpu enable or disable */ + value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1); + value8 &= ~BIT(2); + HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8); + + /* cpu io interface enable or disable */ + value8 = HALMAC_REG_R8(REG_RSV_CTRL + 1); + value8 &= ~BIT(0); + HALMAC_REG_W8(REG_RSV_CTRL + 1, value8); + } +} + +static void +pltfm_reset_88xx(struct halmac_adapter *adapter) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + value8 = HALMAC_REG_R8(REG_CPU_DMEM_CON + 2) & ~BIT(0); + HALMAC_REG_W8(REG_CPU_DMEM_CON + 2, value8); + + /* For 8822B & 8821C clock sync issue */ + if (adapter->chip_id == HALMAC_CHIP_ID_8821C || + adapter->chip_id == HALMAC_CHIP_ID_8822B) { + value8 = HALMAC_REG_R8(REG_SYS_CLK_CTRL + 1) & ~BIT(6); + HALMAC_REG_W8(REG_SYS_CLK_CTRL + 1, value8); + } + + value8 = HALMAC_REG_R8(REG_CPU_DMEM_CON + 2) | BIT(0); + HALMAC_REG_W8(REG_CPU_DMEM_CON + 2, value8); + + if (adapter->chip_id == HALMAC_CHIP_ID_8821C || + adapter->chip_id == HALMAC_CHIP_ID_8822B) { + value8 = HALMAC_REG_R8(REG_SYS_CLK_CTRL + 1) | BIT(6); + HALMAC_REG_W8(REG_SYS_CLK_CTRL + 1, value8); + } +} + +/** + * free_download_firmware_88xx() - download specific memory firmware + * @adapter + * @mem_sel : memory selection + * @fw_bin : firmware bin + * @size : firmware size + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +free_download_firmware_88xx(struct halmac_adapter *adapter, + enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size) +{ + u8 tx_pause_bckp; + u32 dl_addr; + u32 dlfw_size_bckp; + enum halmac_ret_status status; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = chk_fw_size_88xx(adapter, fw_bin, size); + if (status != HALMAC_RET_SUCCESS) + return status; + + if (((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)) == 0) + return HALMAC_RET_SUCCESS; + + dlfw_size_bckp = adapter->dlfw_pkt_size; + if (mem_sel == HALMAC_DLFW_MEM_EMEM) { + dl_addr = 0; + } else { + dl_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + adapter->dlfw_pkt_size = (dlfw_size_bckp > DLFW_RSVDPG_SIZE) ? + DLFW_RSVDPG_SIZE : dlfw_size_bckp; + } + + tx_pause_bckp = HALMAC_REG_R8(REG_TXPAUSE); + HALMAC_REG_W8(REG_TXPAUSE, tx_pause_bckp | BIT(7)); + + status = start_dlfw_88xx(adapter, fw_bin, size, dl_addr, 1); + if (status != HALMAC_RET_SUCCESS) + goto DL_FREE_FW_END; + + status = free_dl_fw_end_flow_88xx(adapter); + +DL_FREE_FW_END: + HALMAC_REG_W8(REG_TXPAUSE, tx_pause_bckp); + adapter->dlfw_pkt_size = dlfw_size_bckp; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return status; +} + +/** + * get_fw_version_88xx() - get FW version + * @adapter : the adapter of halmac + * @ver : fw version info + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_fw_version_88xx(struct halmac_adapter *adapter, + struct halmac_fw_version *ver) +{ + struct halmac_fw_version *info = &adapter->fw_ver; + + if (!ver) + return HALMAC_RET_NULL_POINTER; + + if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) + return HALMAC_RET_NO_DLFW; + + ver->version = info->version; + ver->sub_version = info->sub_version; + ver->sub_index = info->sub_index; + ver->h2c_version = info->h2c_version; + ver->build_time.month = info->build_time.month; + ver->build_time.date = info->build_time.date; + ver->build_time.hour = info->build_time.hour; + ver->build_time.min = info->build_time.min; + ver->build_time.year = info->build_time.year; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +update_fw_info_88xx(struct halmac_adapter *adapter, u8 *fw_bin) +{ + struct halmac_fw_version *info = &adapter->fw_ver; + + info->version = *((u16 *)(fw_bin + WLAN_FW_HDR_VERSION)); + info->version = rtk_le16_to_cpu(info->version); + info->sub_version = *(fw_bin + WLAN_FW_HDR_SUBVERSION); + info->sub_index = *(fw_bin + WLAN_FW_HDR_SUBINDEX); + info->h2c_version = *((u16 *)(fw_bin + WLAN_FW_HDR_H2C_FMT_VER)); + info->h2c_version = rtk_le16_to_cpu(info->h2c_version); + info->build_time.month = *(fw_bin + WLAN_FW_HDR_MONTH); + info->build_time.date = *(fw_bin + WLAN_FW_HDR_DATE); + info->build_time.hour = *(fw_bin + WLAN_FW_HDR_HOUR); + info->build_time.min = *(fw_bin + WLAN_FW_HDR_MIN); + info->build_time.year = *((u16 *)(fw_bin + WLAN_FW_HDR_YEAR)); + info->build_time.year = rtk_le16_to_cpu(info->build_time.year); + + PLTFM_MSG_TRACE("[TRACE]=== FW info ===\n"); + PLTFM_MSG_TRACE("[TRACE]ver : %X\n", info->version); + PLTFM_MSG_TRACE("[TRACE]sub-ver : %X\n", + info->sub_version); + PLTFM_MSG_TRACE("[TRACE]sub-idx : %X\n", + info->sub_index); + PLTFM_MSG_TRACE("[TRACE]build : %d/%d/%d %d:%d\n", + info->build_time.year, info->build_time.month, + info->build_time.date, info->build_time.hour, + info->build_time.min); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest, + u32 size) +{ + u8 first_part; + u32 mem_offset; + u32 residue_size; + u32 pkt_size; + enum halmac_ret_status status; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + mem_offset = 0; + first_part = 1; + residue_size = size; + + HALMAC_REG_W32_SET(REG_DDMA_CH0CTRL, BIT_DDMACH0_RESET_CHKSUM_STS); + + while (residue_size != 0) { + if (residue_size >= adapter->dlfw_pkt_size) + pkt_size = adapter->dlfw_pkt_size; + else + pkt_size = residue_size; + + status = send_fwpkt_88xx(adapter, (u16)(src >> 7), + fw_bin + mem_offset, pkt_size); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send fw pkt!!"); + return status; + } + + status = iddma_dlfw_88xx(adapter, + OCPBASE_TXBUF_88XX + + src + adapter->hw_cfg_info.txdesc_size, + dest + mem_offset, pkt_size, + first_part); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]iddma dlfw!!"); + return status; + } + + first_part = 0; + mem_offset += pkt_size; + residue_size -= pkt_size; + } + + status = check_fw_chksum_88xx(adapter, dest); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]chk fw chksum!!"); + return status; + } + + return HALMAC_RET_SUCCESS; +} + +static void +restore_mac_reg_88xx(struct halmac_adapter *adapter, + struct halmac_backup_info *info, u32 num) +{ + u8 len; + u32 i; + u32 reg; + u32 value; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + struct halmac_backup_info *curr_info = info; + + for (i = 0; i < num; i++) { + reg = curr_info->mac_register; + value = curr_info->value; + len = curr_info->length; + + if (len == 1) + HALMAC_REG_W8(reg, (u8)value); + else if (len == 2) + HALMAC_REG_W16(reg, (u16)value); + else if (len == 4) + HALMAC_REG_W32(reg, value); + + curr_info++; + } +} + +static enum halmac_ret_status +dlfw_end_flow_88xx(struct halmac_adapter *adapter) +{ + u16 fw_ctrl; + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W32(REG_TXDMA_STATUS, BIT(2)); + + /* Check IMEM & DMEM checksum is OK or not */ + fw_ctrl = HALMAC_REG_R16(REG_MCUFW_CTRL); + if ((fw_ctrl & 0x50) != 0x50) + return HALMAC_RET_IDMEM_CHKSUM_FAIL; + + HALMAC_REG_W16(REG_MCUFW_CTRL, (fw_ctrl | BIT_FW_DW_RDY) & ~BIT(0)); + + wlan_cpu_en_88xx(adapter, 1); + PLTFM_MSG_TRACE("[TRACE]Dlfw OK, enable CPU\n"); + + cnt = 5000; + while (HALMAC_REG_R16(REG_MCUFW_CTRL) != 0xC078) { + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]Check 0x80 = 0xC078 fail\n"); + if ((HALMAC_REG_R32(REG_FW_DBG7) & 0xFFFFFF00) == + ILLEGAL_KEY_GROUP) { + PLTFM_MSG_ERR("[ERR]Key!!\n"); + return HALMAC_RET_ILLEGAL_KEY_FAIL; + } + return HALMAC_RET_FW_READY_CHK_FAIL; + } + cnt--; + PLTFM_DELAY_US(50); + } + + PLTFM_MSG_TRACE("[TRACE]0x80=0xC078, cnt=%d\n", cnt); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +free_dl_fw_end_flow_88xx(struct halmac_adapter *adapter) +{ + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + cnt = 100; + while (HALMAC_REG_R8(REG_HMETFR + 3) != 0) { + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]0x1CF != 0\n"); + return HALMAC_RET_DLFW_FAIL; + } + PLTFM_DELAY_US(50); + } + + HALMAC_REG_W8(REG_HMETFR + 3, ID_INFORM_DLEMEM_RDY); + + cnt = 10000; + while (HALMAC_REG_R8(REG_MCU_TST_CFG) != ID_CHECK_DLEMEM_RDY) { + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]0x84 != 0x80\n"); + return HALMAC_RET_DLFW_FAIL; + } + PLTFM_DELAY_US(50); + } + + HALMAC_REG_W8(REG_MCU_TST_CFG, 0); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +send_fwpkt_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *fw_bin, + u32 size) +{ + enum halmac_ret_status status; + + status = dl_rsvd_page_88xx(adapter, pg_addr, fw_bin, size); + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]dl rsvd page!!\n"); + + return status; +} + +static enum halmac_ret_status +iddma_dlfw_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 len, + u8 first) +{ + u32 cnt; + u32 ch0_ctrl = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN); + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + cnt = HALMC_DDMA_POLLING_COUNT; + while (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]ch0 ready!!\n"); + return HALMAC_RET_DDMA_FAIL; + } + } + + ch0_ctrl |= (len & BIT_MASK_DDMACH0_DLEN); + if (first == 0) + ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT; + + if (iddma_en_88xx(adapter, src, dest, ch0_ctrl) != + HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]iddma en!!\n"); + return HALMAC_RET_DDMA_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +iddma_en_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 ctrl) +{ + u32 cnt = HALMC_DDMA_POLLING_COUNT; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W32(REG_DDMA_CH0SA, src); + HALMAC_REG_W32(REG_DDMA_CH0DA, dest); + HALMAC_REG_W32(REG_DDMA_CH0CTRL, ctrl); + + while (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { + cnt--; + if (cnt == 0) + return HALMAC_RET_DDMA_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +check_fw_chksum_88xx(struct halmac_adapter *adapter, u32 mem_addr) +{ + u8 fw_ctrl; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + fw_ctrl = HALMAC_REG_R8(REG_MCUFW_CTRL); + + if (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) { + if (mem_addr < OCPBASE_DMEM_88XX) { + fw_ctrl |= BIT_IMEM_DW_OK; + fw_ctrl &= ~BIT_IMEM_CHKSUM_OK; + HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl); + } else { + fw_ctrl |= BIT_DMEM_DW_OK; + fw_ctrl &= ~BIT_DMEM_CHKSUM_OK; + HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl); + } + + PLTFM_MSG_ERR("[ERR]fw chksum!!\n"); + + return HALMAC_RET_FW_CHECKSUM_FAIL; + } + + if (mem_addr < OCPBASE_DMEM_88XX) { + fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK); + HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl); + } else { + fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK); + HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl); + } + + return HALMAC_RET_SUCCESS; +} + +/** + * check_fw_status_88xx() -check fw status + * @adapter : the adapter of halmac + * @status : fw status + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status) +{ + u32 cnt; + u32 fw_dbg6; + u32 fw_pc; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + *fw_status = _TRUE; + + fw_dbg6 = HALMAC_REG_R32(REG_FW_DBG6); + + if (fw_dbg6 != 0) { + PLTFM_MSG_ERR("[ERR]REG_FW_DBG6 !=0\n"); + if ((fw_dbg6 & FW_STATUS_CHK_WARN) != 0) + PLTFM_MSG_WARN("[WARN]fw status(warn):%X\n", fw_dbg6); + + if ((fw_dbg6 & FW_STATUS_CHK_ERR) != 0) + PLTFM_MSG_ERR("[ERR]fw status(err):%X\n", fw_dbg6); + + if ((fw_dbg6 & FW_STATUS_CHK_FATAL) != 0) { + PLTFM_MSG_ERR("[ERR]fw status(fatal):%X\n", fw_dbg6); + fw_fatal_status_debug_88xx(adapter); + *fw_status = _FALSE; + return status; + } + } + + fw_pc = HALMAC_REG_R32(REG_FW_DBG7); + cnt = 10; + while (HALMAC_REG_R32(REG_FW_DBG7) == fw_pc) { + cnt--; + if (cnt == 0) + break; + } + + if (cnt == 0) { + cnt = 200; + while (HALMAC_REG_R32(REG_FW_DBG7) == fw_pc) { + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]fw pc\n"); + *fw_status = _FALSE; + return status; + } + PLTFM_DELAY_US(50); + } + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return status; +} + +static void +fw_fatal_status_debug_88xx(struct halmac_adapter *adapter) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_ERR("[ERR]0x%X = %X\n", + REG_FW_DBG6, HALMAC_REG_R32(REG_FW_DBG6)); + + PLTFM_MSG_ERR("[ERR]0x%X = %X\n", + REG_ARFR5, HALMAC_REG_R32(REG_ARFR5)); + + PLTFM_MSG_ERR("[ERR]0x%X = %X\n", + REG_MCUTST_I, HALMAC_REG_R32(REG_MCUTST_I)); +} + +enum halmac_ret_status +dump_fw_dmem_88xx(struct halmac_adapter *adapter, u8 *dmem, u32 *size) +{ + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_max_dl_size_88xx() - config max download FW size + * @adapter : the adapter of halmac + * @size : max download fw size + * + * Halmac uses this setting to set max packet size for + * download FW. + * If user has not called this API, halmac use default + * setting for download FW + * Note1 : size need multiple of 2 + * Note2 : max size is 31K + * + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_max_dl_size_88xx(struct halmac_adapter *adapter, u32 size) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (size > DLFW_PKT_SIZE_LIMIT) { + PLTFM_MSG_ERR("[ERR]size > max dl size!\n"); + return HALMAC_RET_CFG_DLFW_SIZE_FAIL; + } + + if ((size & (2 - 1)) != 0) { + PLTFM_MSG_ERR("[ERR]not multiple of 2!\n"); + return HALMAC_RET_CFG_DLFW_SIZE_FAIL; + } + + adapter->dlfw_pkt_size = size; + + PLTFM_MSG_TRACE("[TRACE]Cfg max size:%X\n", size); + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * enter_cpu_sleep_mode_88xx() -wlan cpu enter sleep mode + * @adapter : the adapter of halmac + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +enter_cpu_sleep_mode_88xx(struct halmac_adapter *adapter) +{ + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_wlcpu_mode *cur_mode = &adapter->halmac_state.wlcpu_mode; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (*cur_mode != HALMAC_WLCPU_ACTIVE) + return HALMAC_RET_ERROR_STATE; + + cnt = 100; + while (HALMAC_REG_R8(REG_HMETFR + 3) != 0) { + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]0x1CF != 0\n"); + return HALMAC_RET_STATE_INCORRECT; + } + PLTFM_DELAY_US(50); + } + + HALMAC_REG_W8(REG_HMETFR + 3, ID_INFORM_ENETR_CPU_SLEEP); + + *cur_mode = HALMAC_WLCPU_ENTER_SLEEP; + + return HALMAC_RET_SUCCESS; +} + +/** + * get_cpu_mode_88xx() -get wlcpu mode + * @adapter : the adapter of halmac + * @mode : cpu mode + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_cpu_mode_88xx(struct halmac_adapter *adapter, + enum halmac_wlcpu_mode *mode) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_wlcpu_mode *cur_mode = &adapter->halmac_state.wlcpu_mode; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (*cur_mode == HALMAC_WLCPU_ACTIVE) { + *mode = HALMAC_WLCPU_ACTIVE; + return HALMAC_RET_SUCCESS; + } + + if (*cur_mode == HALMAC_WLCPU_SLEEP) { + *mode = HALMAC_WLCPU_SLEEP; + return HALMAC_RET_SUCCESS; + } + + if (HALMAC_REG_R8(REG_MCU_TST_CFG) == ID_CHECK_ENETR_CPU_SLEEP) { + *mode = HALMAC_WLCPU_SLEEP; + HALMAC_REG_W8(REG_MCU_TST_CFG, 0); + } else { + *mode = HALMAC_WLCPU_ENTER_SLEEP; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * send_general_info_88xx() -send general information to FW + * @adapter : the adapter of halmac + * @info : general information + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +send_general_info_88xx(struct halmac_adapter *adapter, + struct halmac_general_info *info) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (adapter->fw_ver.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) { + PLTFM_MSG_ERR("[ERR]no dl fw!!\n"); + return HALMAC_RET_NO_DLFW; + } + + status = proc_send_general_info_88xx(adapter, info); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send gen info!!\n"); + return status; + } + + status = proc_send_phydm_info_88xx(adapter, info); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send phydm info\n"); + return status; + } + + if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_DONE) + adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +proc_send_general_info_88xx(struct halmac_adapter *adapter, + struct halmac_general_info *info) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s\n", __func__); + + GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_buf, + adapter->txff_alloc.rsvd_fw_txbuf_addr - + adapter->txff_alloc.rsvd_boundary); + + hdr_info.sub_cmd_id = SUB_CMD_ID_GENERAL_INFO; + hdr_info.content_size = 4; + hdr_info.ack = _FALSE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + + return status; +} + +static enum halmac_ret_status +proc_send_phydm_info_88xx(struct halmac_adapter *adapter, + struct halmac_general_info *info) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s\n", __func__); + + PHYDM_INFO_SET_REF_TYPE(h2c_buf, info->rfe_type); + PHYDM_INFO_SET_RF_TYPE(h2c_buf, info->rf_type); + PHYDM_INFO_SET_CUT_VER(h2c_buf, adapter->chip_ver); + PHYDM_INFO_SET_RX_ANT_STATUS(h2c_buf, info->rx_ant_status); + PHYDM_INFO_SET_TX_ANT_STATUS(h2c_buf, info->tx_ant_status); + + hdr_info.sub_cmd_id = SUB_CMD_ID_PHYDM_INFO; + hdr_info.content_size = 8; + hdr_info.ack = _FALSE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + + return status; +} + +/** + * drv_fwctrl_88xx() - send drv-defined h2c pkt + * @adapter : the adapter of halmac + * @payload : no include offload pkt h2c header + * @size : no include offload pkt h2c header + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +drv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!payload) + return HALMAC_RET_DATA_BUF_NULL; + + if (size > H2C_PKT_SIZE_88XX - H2C_PKT_HDR_SIZE_88XX) + return HALMAC_RET_DATA_SIZE_INCORRECT; + + PLTFM_MEMCPY(h2c_buf + H2C_PKT_HDR_SIZE_88XX, payload, size); + + hdr_info.sub_cmd_id = SUB_CMD_ID_FW_FWCTRL; + hdr_info.content_size = (u16)size; + hdr_info.ack = ack; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return status; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_fw_88xx.h b/hal/halmac/halmac_88xx/halmac_fw_88xx.h new file mode 100644 index 0000000..f7015f6 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_fw_88xx.h @@ -0,0 +1,61 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_FW_88XX_H_ +#define _HALMAC_FW_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +#define HALMC_DDMA_POLLING_COUNT 1000 + +#endif /* HALMAC_88XX_SUPPORT */ + +enum halmac_ret_status +download_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size); + +enum halmac_ret_status +free_download_firmware_88xx(struct halmac_adapter *adapter, + enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size); + +enum halmac_ret_status +get_fw_version_88xx(struct halmac_adapter *adapter, + struct halmac_fw_version *ver); + +enum halmac_ret_status +check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status); + +enum halmac_ret_status +dump_fw_dmem_88xx(struct halmac_adapter *adapter, u8 *dmem, u32 *size); + +enum halmac_ret_status +cfg_max_dl_size_88xx(struct halmac_adapter *adapter, u32 size); + +enum halmac_ret_status +enter_cpu_sleep_mode_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +get_cpu_mode_88xx(struct halmac_adapter *adapter, + enum halmac_wlcpu_mode *mode); + +enum halmac_ret_status +send_general_info_88xx(struct halmac_adapter *adapter, + struct halmac_general_info *info); + +enum halmac_ret_status +drv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack); + +#endif/* _HALMAC_FW_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_init_88xx.c b/hal/halmac/halmac_88xx/halmac_init_88xx.c new file mode 100644 index 0000000..93fbcf7 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_init_88xx.c @@ -0,0 +1,1081 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_init_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_fw_88xx.h" +#include "halmac_common_88xx.h" +#include "halmac_cfg_wmac_88xx.h" +#include "halmac_efuse_88xx.h" +#include "halmac_mimo_88xx.h" +#include "halmac_bb_rf_88xx.h" +#include "halmac_sdio_88xx.h" +#include "halmac_usb_88xx.h" +#include "halmac_pcie_88xx.h" +#include "halmac_gpio_88xx.h" +#include "halmac_flash_88xx.h" + +#if HALMAC_8822B_SUPPORT +#include "halmac_8822b/halmac_init_8822b.h" +#endif + +#if HALMAC_8821C_SUPPORT +#include "halmac_8821c/halmac_init_8821c.h" +#endif + +#if HALMAC_8822C_SUPPORT +#include "halmac_8822c/halmac_init_8822c.h" +#endif + +#if HALMAC_PLATFORM_TESTPROGRAM +#include "halmisc_api_88xx.h" +#endif + +#if HALMAC_88XX_SUPPORT + +#define PLTFM_INFO_MALLOC_MAX_SIZE 16384 +#define PLTFM_INFO_RSVD_PG_SIZE 16384 +#define DLFW_PKT_MAX_SIZE 8192 /* need multiple of 2 */ + +#define SYS_FUNC_EN 0xDC +#define WLAN_SLOT_TIME 0x05 +#define WLAN_PIFS_TIME 0x19 +#define WLAN_SIFS_CCK_CONT_TX 0xA +#define WLAN_SIFS_OFDM_CONT_TX 0xA +#define WLAN_SIFS_CCK_TRX 0x10 +#define WLAN_SIFS_OFDM_TRX 0x10 +#define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */ +#define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */ +#define WLAN_RDG_NAV 0x05 +#define WLAN_TXOP_NAV 0x1B +#define WLAN_CCK_RX_TSF 0x30 +#define WLAN_OFDM_RX_TSF 0x30 +#define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ +#define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ +#define WLAN_DRV_EARLY_INT 0x04 +#define WLAN_BCN_DMA_TIME 0x02 +#define WLAN_ACK_TO_CCK 0x40 + +#define WLAN_RX_FILTER0 0x0FFFFFFF +#define WLAN_RX_FILTER2 0xFFFF +#define WLAN_RCR_CFG 0xE400220E +#define WLAN_RXPKT_MAX_SZ 12288 +#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) + +#define WLAN_TX_FUNC_CFG1 0x30 +#define WLAN_TX_FUNC_CFG2 0x30 +#define WLAN_MAC_OPT_NORM_FUNC1 0x98 +#define WLAN_MAC_OPT_LB_FUNC1 0x80 +#define WLAN_MAC_OPT_FUNC2 0x30810041 + +#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ + (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ + (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ + (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) + +#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ + (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) + +#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) +#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) + +static void +init_state_machine_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +verify_io_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +verify_send_rsvd_page_88xx(struct halmac_adapter *adapter); + +void +init_adapter_param_88xx(struct halmac_adapter *adapter) +{ + adapter->api_registry.rx_exp_en = 1; + adapter->api_registry.la_mode_en = 1; + adapter->api_registry.cfg_drv_rsvd_pg_en = 1; + adapter->api_registry.sdio_cmd53_4byte_en = 1; + + adapter->efuse_map = (u8 *)NULL; + adapter->efuse_map_valid = _FALSE; + adapter->efuse_end = 0; + + adapter->dlfw_pkt_size = DLFW_PKT_MAX_SIZE; + adapter->pltfm_info.malloc_size = PLTFM_INFO_MALLOC_MAX_SIZE; + adapter->pltfm_info.rsvd_pg_size = PLTFM_INFO_RSVD_PG_SIZE; + + adapter->cfg_param_info.buf = NULL; + adapter->cfg_param_info.buf_wptr = NULL; + adapter->cfg_param_info.num = 0; + adapter->cfg_param_info.full_fifo_mode = _FALSE; + adapter->cfg_param_info.buf_size = 0; + adapter->cfg_param_info.avl_buf_size = 0; + adapter->cfg_param_info.offset_accum = 0; + adapter->cfg_param_info.value_accum = 0; + + adapter->ch_sw_info.buf = NULL; + adapter->ch_sw_info.buf_wptr = NULL; + adapter->ch_sw_info.extra_info_en = 0; + adapter->ch_sw_info.buf_size = 0; + adapter->ch_sw_info.avl_buf_size = 0; + adapter->ch_sw_info.total_size = 0; + adapter->ch_sw_info.ch_num = 0; + + adapter->drv_info_size = 0; + adapter->tx_desc_transfer = _FALSE; + + adapter->txff_alloc.tx_fifo_pg_num = 0; + adapter->txff_alloc.acq_pg_num = 0; + adapter->txff_alloc.rsvd_boundary = 0; + adapter->txff_alloc.rsvd_drv_addr = 0; + adapter->txff_alloc.rsvd_h2c_info_addr = 0; + adapter->txff_alloc.rsvd_h2cq_addr = 0; + adapter->txff_alloc.rsvd_cpu_instr_addr = 0; + adapter->txff_alloc.rsvd_fw_txbuf_addr = 0; + adapter->txff_alloc.pub_queue_pg_num = 0; + adapter->txff_alloc.high_queue_pg_num = 0; + adapter->txff_alloc.low_queue_pg_num = 0; + adapter->txff_alloc.normal_queue_pg_num = 0; + adapter->txff_alloc.extra_queue_pg_num = 0; + + adapter->txff_alloc.la_mode = HALMAC_LA_MODE_DISABLE; + adapter->txff_alloc.rx_fifo_exp_mode = + HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE; + + adapter->hw_cfg_info.chk_security_keyid = 0; + adapter->hw_cfg_info.acq_num = 8; + adapter->hw_cfg_info.page_size = TX_PAGE_SIZE_88XX; + adapter->hw_cfg_info.tx_align_size = TX_ALIGN_SIZE_88XX; + adapter->hw_cfg_info.txdesc_size = TX_DESC_SIZE_88XX; + adapter->hw_cfg_info.rxdesc_size = RX_DESC_SIZE_88XX; + adapter->hw_cfg_info.rx_desc_fifo_size = 0; + + adapter->sdio_cmd53_4byte = HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE; + adapter->sdio_hw_info.io_hi_speed_flag = 0; + adapter->sdio_hw_info.io_indir_flag = 0; + adapter->sdio_hw_info.spec_ver = HALMAC_SDIO_SPEC_VER_2_00; + adapter->sdio_hw_info.clock_speed = 50; + adapter->sdio_hw_info.block_size = 512; + adapter->sdio_hw_info.tx_seq = 1; + adapter->sdio_fs.macid_map = (u8 *)NULL; + + adapter->pinmux_info.wl_led = 0; + adapter->pinmux_info.sdio_int = 0; + adapter->pinmux_info.sw_io_0 = 0; + adapter->pinmux_info.sw_io_1 = 0; + adapter->pinmux_info.sw_io_2 = 0; + adapter->pinmux_info.sw_io_3 = 0; + adapter->pinmux_info.sw_io_4 = 0; + adapter->pinmux_info.sw_io_5 = 0; + adapter->pinmux_info.sw_io_6 = 0; + adapter->pinmux_info.sw_io_7 = 0; + adapter->pinmux_info.sw_io_8 = 0; + adapter->pinmux_info.sw_io_9 = 0; + adapter->pinmux_info.sw_io_10 = 0; + adapter->pinmux_info.sw_io_11 = 0; + adapter->pinmux_info.sw_io_12 = 0; + adapter->pinmux_info.sw_io_13 = 0; + adapter->pinmux_info.sw_io_14 = 0; + adapter->pinmux_info.sw_io_15 = 0; + + adapter->pcie_refautok_en = 1; + adapter->pwr_off_flow_flag = 0; + + init_adapter_dynamic_param_88xx(adapter); + init_state_machine_88xx(adapter); +} + +void +init_adapter_dynamic_param_88xx(struct halmac_adapter *adapter) +{ + adapter->h2c_info.seq_num = 0; + adapter->h2c_info.buf_fs = 0; +} + +enum halmac_ret_status +mount_api_88xx(struct halmac_adapter *adapter) +{ + struct halmac_api *api = NULL; + + adapter->halmac_api = + (struct halmac_api *)PLTFM_MALLOC(sizeof(struct halmac_api)); + if (!adapter->halmac_api) + return HALMAC_RET_MALLOC_FAIL; + + api = (struct halmac_api *)adapter->halmac_api; + + api->halmac_read_efuse = NULL; + api->halmac_write_efuse = NULL; + + /* Mount function pointer */ + api->halmac_register_api = register_api_88xx; + api->halmac_download_firmware = download_firmware_88xx; + api->halmac_free_download_firmware = free_download_firmware_88xx; + api->halmac_get_fw_version = get_fw_version_88xx; + api->halmac_cfg_mac_addr = cfg_mac_addr_88xx; + api->halmac_cfg_bssid = cfg_bssid_88xx; + api->halmac_cfg_transmitter_addr = cfg_transmitter_addr_88xx; + api->halmac_cfg_net_type = cfg_net_type_88xx; + api->halmac_cfg_tsf_rst = cfg_tsf_rst_88xx; + api->halmac_cfg_bcn_space = cfg_bcn_space_88xx; + api->halmac_rw_bcn_ctrl = rw_bcn_ctrl_88xx; + api->halmac_cfg_multicast_addr = cfg_multicast_addr_88xx; + api->halmac_pre_init_system_cfg = pre_init_system_cfg_88xx; + api->halmac_init_system_cfg = init_system_cfg_88xx; + api->halmac_init_edca_cfg = init_edca_cfg_88xx; + api->halmac_cfg_operation_mode = cfg_operation_mode_88xx; + api->halmac_cfg_ch_bw = cfg_ch_bw_88xx; + api->halmac_cfg_bw = cfg_bw_88xx; + api->halmac_init_wmac_cfg = init_wmac_cfg_88xx; + api->halmac_init_mac_cfg = init_mac_cfg_88xx; + api->halmac_dump_efuse_map = dump_efuse_map_88xx; + api->halmac_dump_efuse_map_bt = dump_efuse_map_bt_88xx; + api->halmac_write_efuse_bt = write_efuse_bt_88xx; + api->halmac_read_efuse_bt = read_efuse_bt_88xx; + api->halmac_cfg_efuse_auto_check = cfg_efuse_auto_check_88xx; + api->halmac_dump_logical_efuse_map = dump_log_efuse_map_88xx; + api->halmac_pg_efuse_by_map = pg_efuse_by_map_88xx; + api->halmac_mask_logical_efuse = mask_log_efuse_88xx; + api->halmac_get_efuse_size = get_efuse_size_88xx; + api->halmac_get_efuse_available_size = get_efuse_available_size_88xx; + api->halmac_get_c2h_info = get_c2h_info_88xx; + + api->halmac_get_logical_efuse_size = get_log_efuse_size_88xx; + + api->halmac_write_logical_efuse = write_log_efuse_88xx; + api->halmac_read_logical_efuse = read_logical_efuse_88xx; + + api->halmac_ofld_func_cfg = ofld_func_cfg_88xx; + api->halmac_h2c_lb = h2c_lb_88xx; + api->halmac_debug = mac_debug_88xx; + api->halmac_cfg_parameter = cfg_parameter_88xx; + api->halmac_update_datapack = update_datapack_88xx; + api->halmac_run_datapack = run_datapack_88xx; + api->halmac_send_bt_coex = send_bt_coex_88xx; + api->halmac_verify_platform_api = verify_platform_api_88xx; + api->halmac_update_packet = update_packet_88xx; + api->halmac_bcn_ie_filter = bcn_ie_filter_88xx; + api->halmac_cfg_txbf = cfg_txbf_88xx; + api->halmac_cfg_mumimo = cfg_mumimo_88xx; + api->halmac_cfg_sounding = cfg_sounding_88xx; + api->halmac_del_sounding = del_sounding_88xx; + api->halmac_su_bfer_entry_init = su_bfer_entry_init_88xx; + api->halmac_su_bfee_entry_init = su_bfee_entry_init_88xx; + api->halmac_mu_bfer_entry_init = mu_bfer_entry_init_88xx; + api->halmac_mu_bfee_entry_init = mu_bfee_entry_init_88xx; + api->halmac_su_bfer_entry_del = su_bfer_entry_del_88xx; + api->halmac_su_bfee_entry_del = su_bfee_entry_del_88xx; + api->halmac_mu_bfer_entry_del = mu_bfer_entry_del_88xx; + api->halmac_mu_bfee_entry_del = mu_bfee_entry_del_88xx; + + api->halmac_add_ch_info = add_ch_info_88xx; + api->halmac_add_extra_ch_info = add_extra_ch_info_88xx; + api->halmac_ctrl_ch_switch = ctrl_ch_switch_88xx; + api->halmac_p2pps = p2pps_88xx; + api->halmac_clear_ch_info = clear_ch_info_88xx; + api->halmac_send_general_info = send_general_info_88xx; + + api->halmac_start_iqk = start_iqk_88xx; + api->halmac_ctrl_pwr_tracking = ctrl_pwr_tracking_88xx; + api->halmac_psd = psd_88xx; + api->halmac_cfg_la_mode = cfg_la_mode_88xx; + api->halmac_cfg_rxff_expand_mode = cfg_rxfifo_expand_mode_88xx; + + api->halmac_config_security = config_security_88xx; + api->halmac_get_used_cam_entry_num = get_used_cam_entry_num_88xx; + api->halmac_read_cam_entry = read_cam_entry_88xx; + api->halmac_write_cam = write_cam_88xx; + api->halmac_clear_cam_entry = clear_cam_entry_88xx; + + api->halmac_cfg_drv_rsvd_pg_num = cfg_drv_rsvd_pg_num_88xx; + api->halmac_get_chip_version = get_version_88xx; + + api->halmac_query_status = query_status_88xx; + api->halmac_reset_feature = reset_ofld_feature_88xx; + api->halmac_check_fw_status = check_fw_status_88xx; + api->halmac_dump_fw_dmem = dump_fw_dmem_88xx; + api->halmac_cfg_max_dl_size = cfg_max_dl_size_88xx; + + api->halmac_dump_fifo = dump_fifo_88xx; + api->halmac_get_fifo_size = get_fifo_size_88xx; + + api->halmac_chk_txdesc = chk_txdesc_88xx; + api->halmac_dl_drv_rsvd_page = dl_drv_rsvd_page_88xx; + api->halmac_cfg_csi_rate = cfg_csi_rate_88xx; + + api->halmac_sdio_cmd53_4byte = sdio_cmd53_4byte_88xx; + api->halmac_sdio_hw_info = sdio_hw_info_88xx; + + api->halmac_init_sdio_cfg = init_sdio_cfg_88xx; + api->halmac_init_usb_cfg = init_usb_cfg_88xx; + api->halmac_init_pcie_cfg = init_pcie_cfg_88xx; + api->halmac_deinit_sdio_cfg = deinit_sdio_cfg_88xx; + api->halmac_deinit_usb_cfg = deinit_usb_cfg_88xx; + api->halmac_deinit_pcie_cfg = deinit_pcie_cfg_88xx; + api->halmac_txfifo_is_empty = txfifo_is_empty_88xx; + api->halmac_download_flash = download_flash_88xx; + api->halmac_read_flash = read_flash_88xx; + api->halmac_erase_flash = erase_flash_88xx; + api->halmac_check_flash = check_flash_88xx; + api->halmac_cfg_edca_para = cfg_edca_para_88xx; + api->halmac_pinmux_wl_led_mode = pinmux_wl_led_mode_88xx; + api->halmac_pinmux_wl_led_sw_ctrl = pinmux_wl_led_sw_ctrl_88xx; + api->halmac_pinmux_sdio_int_polarity = pinmux_sdio_int_polarity_88xx; + api->halmac_pinmux_gpio_mode = pinmux_gpio_mode_88xx; + api->halmac_pinmux_gpio_output = pinmux_gpio_output_88xx; + api->halmac_pinmux_pin_status = pinmux_pin_status_88xx; + + api->halmac_rx_cut_amsdu_cfg = rx_cut_amsdu_cfg_88xx; + api->halmac_fw_snding = fw_snding_88xx; + api->halmac_get_mac_addr = get_mac_addr_88xx; + + api->halmac_enter_cpu_sleep_mode = enter_cpu_sleep_mode_88xx; + api->halmac_get_cpu_mode = get_cpu_mode_88xx; + api->halmac_drv_fwctrl = drv_fwctrl_88xx; + api->halmac_en_ref_autok_pcie = en_ref_autok_88xx; + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + api->halmac_cfg_rx_aggregation = cfg_sdio_rx_agg_88xx; + api->halmac_init_interface_cfg = init_sdio_cfg_88xx; + api->halmac_deinit_interface_cfg = deinit_sdio_cfg_88xx; + api->halmac_cfg_tx_agg_align = cfg_txagg_sdio_align_88xx; + api->halmac_set_bulkout_num = set_sdio_bulkout_num_88xx; + api->halmac_get_usb_bulkout_id = get_sdio_bulkout_id_88xx; + api->halmac_reg_read_indirect_32 = sdio_indirect_reg_r32_88xx; + api->halmac_reg_sdio_cmd53_read_n = sdio_reg_rn_88xx; + } else if (adapter->intf == HALMAC_INTERFACE_USB) { + api->halmac_cfg_rx_aggregation = cfg_usb_rx_agg_88xx; + api->halmac_init_interface_cfg = init_usb_cfg_88xx; + api->halmac_deinit_interface_cfg = deinit_usb_cfg_88xx; + api->halmac_cfg_tx_agg_align = cfg_txagg_usb_align_88xx; + api->halmac_tx_allowed_sdio = tx_allowed_usb_88xx; + api->halmac_set_bulkout_num = set_usb_bulkout_num_88xx; + api->halmac_get_sdio_tx_addr = get_usb_tx_addr_88xx; + api->halmac_get_usb_bulkout_id = get_usb_bulkout_id_88xx; + api->halmac_reg_read_8 = reg_r8_usb_88xx; + api->halmac_reg_write_8 = reg_w8_usb_88xx; + api->halmac_reg_read_16 = reg_r16_usb_88xx; + api->halmac_reg_write_16 = reg_w16_usb_88xx; + api->halmac_reg_read_32 = reg_r32_usb_88xx; + api->halmac_reg_write_32 = reg_w32_usb_88xx; + api->halmac_reg_read_indirect_32 = usb_indirect_reg_r32_88xx; + api->halmac_reg_sdio_cmd53_read_n = usb_reg_rn_88xx; + } else if (adapter->intf == HALMAC_INTERFACE_PCIE) { + api->halmac_cfg_rx_aggregation = cfg_pcie_rx_agg_88xx; + api->halmac_init_interface_cfg = init_pcie_cfg_88xx; + api->halmac_deinit_interface_cfg = deinit_pcie_cfg_88xx; + api->halmac_cfg_tx_agg_align = cfg_txagg_pcie_align_88xx; + api->halmac_tx_allowed_sdio = tx_allowed_pcie_88xx; + api->halmac_set_bulkout_num = set_pcie_bulkout_num_88xx; + api->halmac_get_sdio_tx_addr = get_pcie_tx_addr_88xx; + api->halmac_get_usb_bulkout_id = get_pcie_bulkout_id_88xx; + api->halmac_reg_read_8 = reg_r8_pcie_88xx; + api->halmac_reg_write_8 = reg_w8_pcie_88xx; + api->halmac_reg_read_16 = reg_r16_pcie_88xx; + api->halmac_reg_write_16 = reg_w16_pcie_88xx; + api->halmac_reg_read_32 = reg_r32_pcie_88xx; + api->halmac_reg_write_32 = reg_w32_pcie_88xx; + api->halmac_reg_read_indirect_32 = pcie_indirect_reg_r32_88xx; + api->halmac_reg_sdio_cmd53_read_n = pcie_reg_rn_88xx; + } else { + PLTFM_MSG_ERR("[ERR]Set halmac io function Error!!\n"); + } + + if (adapter->chip_id == HALMAC_CHIP_ID_8822B) { +#if HALMAC_8822B_SUPPORT + mount_api_8822b(adapter); +#endif + } else if (adapter->chip_id == HALMAC_CHIP_ID_8821C) { +#if HALMAC_8821C_SUPPORT + mount_api_8821c(adapter); +#endif + } else if (adapter->chip_id == HALMAC_CHIP_ID_8822C) { +#if HALMAC_8822C_SUPPORT + mount_api_8822c(adapter); +#endif + } else { + PLTFM_MSG_ERR("[ERR]Chip ID undefine!!\n"); + return HALMAC_RET_CHIP_NOT_SUPPORT; + } + +#if HALMAC_PLATFORM_TESTPROGRAM + halmac_mount_misc_api_88xx(adapter); +#endif + + return HALMAC_RET_SUCCESS; +} + +static void +init_state_machine_88xx(struct halmac_adapter *adapter) +{ + struct halmac_state *state = &adapter->halmac_state; + + init_ofld_feature_state_machine_88xx(adapter); + + state->api_state = HALMAC_API_STATE_INIT; + + state->dlfw_state = HALMAC_DLFW_NONE; + state->mac_pwr = HALMAC_MAC_POWER_OFF; + state->gpio_cfg_state = HALMAC_GPIO_CFG_STATE_IDLE; + state->rsvd_pg_state = HALMAC_RSVD_PG_STATE_IDLE; +} + +void +init_ofld_feature_state_machine_88xx(struct halmac_adapter *adapter) +{ + struct halmac_state *state = &adapter->halmac_state; + + state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->efuse_state.seq_num = adapter->h2c_info.seq_num; + + state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->cfg_param_state.seq_num = adapter->h2c_info.seq_num; + + state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->scan_state.seq_num = adapter->h2c_info.seq_num; + + state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->update_pkt_state.seq_num = adapter->h2c_info.seq_num; + + state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->iqk_state.seq_num = adapter->h2c_info.seq_num; + + state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->pwr_trk_state.seq_num = adapter->h2c_info.seq_num; + + state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->psd_state.seq_num = adapter->h2c_info.seq_num; + state->psd_state.data_size = 0; + state->psd_state.seg_size = 0; + state->psd_state.data = NULL; + + state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->fw_snding_state.seq_num = adapter->h2c_info.seq_num; + + state->wlcpu_mode = HALMAC_WLCPU_ACTIVE; +} + +/** + * register_api_88xx() - register feature list + * @adapter + * @registry : feature list, 1->enable 0->disable + * Author : Ivan Lin + * + * Default is enable all api registry + * + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +register_api_88xx(struct halmac_adapter *adapter, + struct halmac_api_registry *registry) +{ + if (!registry) + return HALMAC_RET_NULL_POINTER; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + PLTFM_MEMCPY(&adapter->api_registry, registry, sizeof(*registry)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * pre_init_system_cfg_88xx() - pre-init system config + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pre_init_system_cfg_88xx(struct halmac_adapter *adapter) +{ + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 enable_bb; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + HALMAC_REG_W8(REG_RSV_CTRL, 0); + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + if (leave_sdio_suspend_88xx(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL; + } else if (adapter->intf == HALMAC_INTERFACE_USB) { + if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) + HALMAC_REG_W8(0xFE5B, HALMAC_REG_R8(0xFE5B) | BIT(4)); + } else if (adapter->intf == HALMAC_INTERFACE_PCIE) { + /* For PCIE power on fail issue */ + HALMAC_REG_W8(REG_HCI_OPT_CTRL + 1, + HALMAC_REG_R8(REG_HCI_OPT_CTRL + 1) | BIT(0)); + } + + /* Config PIN Mux */ + value32 = HALMAC_REG_R32(REG_PAD_CTRL1); + value32 = value32 & (~(BIT(28) | BIT(29))); + value32 = value32 | BIT(28) | BIT(29); + HALMAC_REG_W32(REG_PAD_CTRL1, value32); + + value32 = HALMAC_REG_R32(REG_LED_CFG); + value32 = value32 & (~(BIT(25) | BIT(26))); + HALMAC_REG_W32(REG_LED_CFG, value32); + + value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG); + value32 = value32 & (~(BIT(2))); + value32 = value32 | BIT(2); + HALMAC_REG_W32(REG_GPIO_MUXCFG, value32); + + enable_bb = _FALSE; + set_hw_value_88xx(adapter, HALMAC_HW_EN_BB_RF, &enable_bb); + + if (HALMAC_REG_R8(REG_SYS_CFG1 + 2) & BIT(4)) { + PLTFM_MSG_ERR("[ERR]test mode!!\n"); + return HALMAC_RET_WLAN_MODE_FAIL; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * init_system_cfg_88xx() - init system config + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_system_cfg_88xx(struct halmac_adapter *adapter) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u32 tmp = 0; + u32 value32; + enum halmac_ret_status status; + u8 hwval; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (adapter->intf == HALMAC_INTERFACE_PCIE) { + hwval = 1; + status = api->halmac_set_hw_value(adapter, + HALMAC_HW_PCIE_REF_AUTOK, + &hwval); + if (status != HALMAC_RET_SUCCESS) + return status; + } + + HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, SYS_FUNC_EN); + + value32 = HALMAC_REG_R32(REG_SYS_SDIO_CTRL) | BIT_LTE_MUX_CTRL_PATH; + HALMAC_REG_W32(REG_SYS_SDIO_CTRL, value32); + + value32 = HALMAC_REG_R32(REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST; +#if HALMAC_8822C_SUPPORT + if (adapter->chip_id != HALMAC_CHIP_ID_8822B && + adapter->chip_id != HALMAC_CHIP_ID_8821C) + value32 |= BIT_DDMA_EN; +#endif + HALMAC_REG_W32(REG_CPU_DMEM_CON, value32); + + /*disable boot-from-flash for driver's DL FW*/ + tmp = HALMAC_REG_R32(REG_MCUFW_CTRL); + if (tmp & BIT_BOOT_FSPI_EN) { + HALMAC_REG_W32(REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN)); + value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG) & (~BIT_FSPI_EN); + HALMAC_REG_W32(REG_GPIO_MUXCFG, value32); + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * init_edca_cfg_88xx() - init EDCA config + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_edca_cfg_88xx(struct halmac_adapter *adapter) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + /* Clear TX pause */ + HALMAC_REG_W16(REG_TXPAUSE, 0x0000); + + HALMAC_REG_W8(REG_SLOT, WLAN_SLOT_TIME); + HALMAC_REG_W8(REG_PIFS, WLAN_PIFS_TIME); + HALMAC_REG_W32(REG_SIFS, WLAN_SIFS_CFG); + + HALMAC_REG_W16(REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); + HALMAC_REG_W16(REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); + + HALMAC_REG_W32(REG_RD_NAV_NXT, WLAN_NAV_CFG); + HALMAC_REG_W16(REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); + + /* Set beacon cotnrol - enable TSF and other related functions */ + HALMAC_REG_W8(REG_BCN_CTRL, (u8)(HALMAC_REG_R8(REG_BCN_CTRL) | + BIT_EN_BCN_FUNCTION)); + + /* Set send beacon related registers */ + HALMAC_REG_W32(REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); + HALMAC_REG_W8(REG_DRVERLYINT, WLAN_DRV_EARLY_INT); + HALMAC_REG_W8(REG_BCNDMATIM, WLAN_BCN_DMA_TIME); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * init_wmac_cfg_88xx() - init wmac config + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_wmac_cfg_88xx(struct halmac_adapter *adapter) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + HALMAC_REG_W32(REG_RXFLTMAP0, WLAN_RX_FILTER0); + HALMAC_REG_W16(REG_RXFLTMAP2, WLAN_RX_FILTER2); + + HALMAC_REG_W32(REG_RCR, WLAN_RCR_CFG); + + HALMAC_REG_W8(REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); + + HALMAC_REG_W8(REG_TCR + 2, WLAN_TX_FUNC_CFG2); + HALMAC_REG_W8(REG_TCR + 1, WLAN_TX_FUNC_CFG1); + +#if HALMAC_8821C_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8821C) + HALMAC_REG_W8(REG_ACKTO_CCK, WLAN_ACK_TO_CCK); +#endif + HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); + + if (adapter->hw_cfg_info.trx_mode == HALMAC_TRNSFER_NORMAL) + value8 = WLAN_MAC_OPT_NORM_FUNC1; + else + value8 = WLAN_MAC_OPT_LB_FUNC1; + + HALMAC_REG_W8(REG_WMAC_OPTION_FUNCTION + 4, value8); + + status = api->halmac_init_low_pwr(adapter); + if (status != HALMAC_RET_SUCCESS) + return status; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * init_mac_cfg_88xx() - config page1~page7 register + * @adapter : the adapter of halmac + * @mode : trx mode + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__, mode); + + status = api->halmac_init_trx_cfg(adapter, mode); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]init trx %x\n", status); + return status; + } + + status = api->halmac_init_protocol_cfg(adapter); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]init ptcl %x\n", status); + return status; + } + + status = init_edca_cfg_88xx(adapter); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]init edca %x\n", status); + return status; + } + + status = init_wmac_cfg_88xx(adapter); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]init wmac %x\n", status); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return status; +} + +/** + * reset_ofld_feature_88xx() -reset async api cmd status + * @adapter : the adapter of halmac + * @feature_id : feature_id + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status. + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reset_ofld_feature_88xx(struct halmac_adapter *adapter, + enum halmac_feature_id feature_id) +{ + struct halmac_state *state = &adapter->halmac_state; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (feature_id) { + case HALMAC_FEATURE_CFG_PARA: + state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + break; + case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE: + case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE: + state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + break; + case HALMAC_FEATURE_CHANNEL_SWITCH: + state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + break; + case HALMAC_FEATURE_UPDATE_PACKET: + state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + break; + case HALMAC_FEATURE_IQK: + state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + break; + case HALMAC_FEATURE_POWER_TRACKING: + state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + break; + case HALMAC_FEATURE_PSD: + state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + break; + case HALMAC_FEATURE_FW_SNDING: + state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + break; + case HALMAC_FEATURE_ALL: + state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + break; + default: + PLTFM_MSG_ERR("[ERR]invalid feature id\n"); + return HALMAC_RET_INVALID_FEATURE_ID; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * (debug API)verify_platform_api_88xx() - verify platform api + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +verify_platform_api_88xx(struct halmac_adapter *adapter) +{ + enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + ret_status = verify_io_88xx(adapter); + + if (ret_status != HALMAC_RET_SUCCESS) + return ret_status; + + if (adapter->txff_alloc.la_mode != HALMAC_LA_MODE_FULL) + ret_status = verify_send_rsvd_page_88xx(adapter); + + if (ret_status != HALMAC_RET_SUCCESS) + return ret_status; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return ret_status; +} + +void +tx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable) +{ + u16 value16; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + adapter->tx_desc_checksum = enable; + + value16 = HALMAC_REG_R16(REG_TXDMA_OFFSET_CHK); + if (enable == _TRUE) + HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 | BIT(13)); + else + HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 & ~BIT(13)); +} + +static enum halmac_ret_status +verify_io_88xx(struct halmac_adapter *adapter) +{ + u8 value8; + u8 wvalue8; + u32 value32; + u32 value32_2; + u32 wvalue32; + u32 offset; + enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS; + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + offset = REG_PAGE5_DUMMY; + if (0 == (offset & 0xFFFF0000)) + offset |= WLAN_IOREG_OFFSET; + + ret_status = cnv_to_sdio_bus_offset_88xx(adapter, &offset); + + /* Verify CMD52 R/W */ + wvalue8 = 0xab; + PLTFM_SDIO_CMD52_W(offset, wvalue8); + + value8 = PLTFM_SDIO_CMD52_R(offset); + + if (value8 != wvalue8) { + PLTFM_MSG_ERR("[ERR]cmd52 r/w\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + + /* Verify CMD53 R/W */ + PLTFM_SDIO_CMD52_W(offset, 0xaa); + PLTFM_SDIO_CMD52_W(offset + 1, 0xbb); + PLTFM_SDIO_CMD52_W(offset + 2, 0xcc); + PLTFM_SDIO_CMD52_W(offset + 3, 0xdd); + + value32 = PLTFM_SDIO_CMD53_R32(offset); + + if (value32 != 0xddccbbaa) { + PLTFM_MSG_ERR("[ERR]cmd53 r\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + + wvalue32 = 0x11223344; + PLTFM_SDIO_CMD53_W32(offset, wvalue32); + + value32 = PLTFM_SDIO_CMD53_R32(offset); + + if (value32 != wvalue32) { + PLTFM_MSG_ERR("[ERR]cmd53 w\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + + /* value32 should be 0x33441122 */ + value32 = PLTFM_SDIO_CMD53_R32(offset + 2); + + wvalue32 = 0x11225566; + PLTFM_SDIO_CMD53_W32(offset, wvalue32); + + /* value32 should be 0x55661122 */ + value32_2 = PLTFM_SDIO_CMD53_R32(offset + 2); + if (value32_2 == value32) { + PLTFM_MSG_ERR("[ERR]cmd52 is used\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + } else { + wvalue32 = 0x77665511; + PLTFM_REG_W32(REG_PAGE5_DUMMY, wvalue32); + + value32 = PLTFM_REG_R32(REG_PAGE5_DUMMY); + if (value32 != wvalue32) { + PLTFM_MSG_ERR("[ERR]reg rw\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + } + + return ret_status; +} + +static enum halmac_ret_status +verify_send_rsvd_page_88xx(struct halmac_adapter *adapter) +{ + u8 txdesc_size = adapter->hw_cfg_info.txdesc_size; + u8 *rsvd_buf = NULL; + u8 *rsvd_page = NULL; + u32 i; + u32 pkt_size = 64, payload = 0xab; + enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS; + + rsvd_buf = (u8 *)PLTFM_MALLOC(pkt_size); + + if (!rsvd_buf) { + PLTFM_MSG_ERR("[ERR]rsvd buf malloc!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + + PLTFM_MEMSET(rsvd_buf, (u8)payload, pkt_size); + + ret_status = dl_rsvd_page_88xx(adapter, + adapter->txff_alloc.rsvd_boundary, + rsvd_buf, pkt_size); + if (ret_status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(rsvd_buf, pkt_size); + return ret_status; + } + + rsvd_page = (u8 *)PLTFM_MALLOC(pkt_size + txdesc_size); + + if (!rsvd_page) { + PLTFM_MSG_ERR("[ERR]rsvd page malloc!!\n"); + PLTFM_FREE(rsvd_buf, pkt_size); + return HALMAC_RET_MALLOC_FAIL; + } + + PLTFM_MEMSET(rsvd_page, 0x00, pkt_size + txdesc_size); + + ret_status = dump_fifo_88xx(adapter, HAL_FIFO_SEL_RSVD_PAGE, 0, + pkt_size + txdesc_size, rsvd_page); + + if (ret_status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(rsvd_buf, pkt_size); + PLTFM_FREE(rsvd_page, pkt_size + txdesc_size); + return ret_status; + } + + for (i = 0; i < pkt_size; i++) { + if (*(rsvd_buf + i) != *(rsvd_page + (i + txdesc_size))) { + PLTFM_MSG_ERR("[ERR]Compare RSVD page Fail\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + } + + PLTFM_FREE(rsvd_buf, pkt_size); + PLTFM_FREE(rsvd_page, pkt_size + txdesc_size); + + return ret_status; +} + +enum halmac_ret_status +pg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode, + struct halmac_pg_num *tbl) +{ + u8 flag; + u16 hpq_num = 0, lpq_num = 0, npq_num = 0, gapq_num = 0; + u16 expq_num = 0, pubq_num = 0; + u32 i = 0; + + flag = 0; + for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) { + if (mode == tbl[i].mode) { + hpq_num = tbl[i].hq_num; + lpq_num = tbl[i].lq_num; + npq_num = tbl[i].nq_num; + expq_num = tbl[i].exq_num; + gapq_num = tbl[i].gap_num; + pubq_num = adapter->txff_alloc.acq_pg_num - hpq_num - + lpq_num - npq_num - expq_num - gapq_num; + flag = 1; + PLTFM_MSG_TRACE("[TRACE]%s done\n", __func__); + break; + } + } + + if (flag == 0) { + PLTFM_MSG_ERR("[ERR]trx mode!!\n"); + return HALMAC_RET_TRX_MODE_NOT_SUPPORT; + } + + if (adapter->txff_alloc.acq_pg_num < + hpq_num + lpq_num + npq_num + expq_num + gapq_num) { + PLTFM_MSG_ERR("[ERR]acqnum = %d\n", + adapter->txff_alloc.acq_pg_num); + PLTFM_MSG_ERR("[ERR]hpq_num = %d\n", hpq_num); + PLTFM_MSG_ERR("[ERR]LPQ_num = %d\n", lpq_num); + PLTFM_MSG_ERR("[ERR]npq_num = %d\n", npq_num); + PLTFM_MSG_ERR("[ERR]EPQ_num = %d\n", expq_num); + PLTFM_MSG_ERR("[ERR]gapq_num = %d\n", gapq_num); + return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL; + } + + adapter->txff_alloc.high_queue_pg_num = hpq_num; + adapter->txff_alloc.low_queue_pg_num = lpq_num; + adapter->txff_alloc.normal_queue_pg_num = npq_num; + adapter->txff_alloc.extra_queue_pg_num = expq_num; + adapter->txff_alloc.pub_queue_pg_num = pubq_num; + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +rqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode, + struct halmac_rqpn *tbl) +{ + u8 flag; + u32 i; + + flag = 0; + for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) { + if (mode == tbl[i].mode) { + adapter->pq_map[HALMAC_PQ_MAP_VO] = tbl[i].dma_map_vo; + adapter->pq_map[HALMAC_PQ_MAP_VI] = tbl[i].dma_map_vi; + adapter->pq_map[HALMAC_PQ_MAP_BE] = tbl[i].dma_map_be; + adapter->pq_map[HALMAC_PQ_MAP_BK] = tbl[i].dma_map_bk; + adapter->pq_map[HALMAC_PQ_MAP_MG] = tbl[i].dma_map_mg; + adapter->pq_map[HALMAC_PQ_MAP_HI] = tbl[i].dma_map_hi; + flag = 1; + PLTFM_MSG_TRACE("[TRACE]%s done\n", __func__); + break; + } + } + + if (flag == 0) { + PLTFM_MSG_ERR("[ERR]trx mdoe!!\n"); + return HALMAC_RET_TRX_MODE_NOT_SUPPORT; + } + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_init_88xx.h b/hal/halmac/halmac_88xx/halmac_init_88xx.h new file mode 100644 index 0000000..3fa4623 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_init_88xx.h @@ -0,0 +1,74 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_INIT_88XX_H_ +#define _HALMAC_INIT_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +register_api_88xx(struct halmac_adapter *adapter, + struct halmac_api_registry *registry); + +void +init_adapter_param_88xx(struct halmac_adapter *adapter); + +void +init_adapter_dynamic_param_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +mount_api_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +pre_init_system_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +init_system_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +init_edca_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +init_wmac_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode); + +enum halmac_ret_status +reset_ofld_feature_88xx(struct halmac_adapter *adapter, + enum halmac_feature_id feature_id); + +enum halmac_ret_status +verify_platform_api_88xx(struct halmac_adapter *adapter); + +void +tx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable); + +enum halmac_ret_status +pg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode, + struct halmac_pg_num *tbl); + +enum halmac_ret_status +rqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode, + struct halmac_rqpn *tbl); + +void +init_ofld_feature_state_machine_88xx(struct halmac_adapter *adapter); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_INIT_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_mimo_88xx.c b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c new file mode 100644 index 0000000..31bd3bc --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c @@ -0,0 +1,876 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_mimo_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_common_88xx.h" +#include "halmac_init_88xx.h" + +#if HALMAC_88XX_SUPPORT + +#define TXBF_CTRL_CFG (BIT_R_ENABLE_NDPA | BIT_USE_NDPA_PARAMETER | \ + BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN) + +static void +cfg_mu_bfee_88xx(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param); + +static void +cfg_mu_bfer_88xx(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param); + +static enum halmac_cmd_construct_state +fw_snding_cmd_cnstr_state_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +cnv_fw_snding_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state); + +static u8 +snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt); + +/** + * cfg_txbf_88xx() - enable/disable specific user's txbf + * @adapter : the adapter of halmac + * @userid : su bfee userid = 0 or 1 to apply TXBF + * @bw : the sounding bandwidth + * @txbf_en : 0: disable TXBF, 1: enable TXBF + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw, + u8 txbf_en) +{ + u16 tmp42c = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (txbf_en) { + switch (bw) { + case HALMAC_BW_80: + tmp42c |= BIT_R_TXBF0_80M; + case HALMAC_BW_40: + tmp42c |= BIT_R_TXBF0_40M; + case HALMAC_BW_20: + tmp42c |= BIT_R_TXBF0_20M; + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + } + + switch (userid) { + case 0: + tmp42c |= HALMAC_REG_R16(REG_TXBF_CTRL) & + ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_W16(REG_TXBF_CTRL, tmp42c); + break; + case 1: + tmp42c |= HALMAC_REG_R16(REG_TXBF_CTRL + 2) & + ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_W16(REG_TXBF_CTRL + 2, tmp42c); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_mumimo_88xx() -config mumimo + * @adapter : the adapter of halmac + * @param : parameters to configure MU PPDU Tx/Rx + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_mumimo_88xx(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param) +{ + if (param->role == HAL_BFEE) + cfg_mu_bfee_88xx(adapter, param); + else + cfg_mu_bfer_88xx(adapter, param); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static void +cfg_mu_bfee_88xx(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param) +{ + u8 mu_tbl_sel; + u8 tmp14c0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + tmp14c0 = HALMAC_REG_R8(REG_MU_TX_CTL) & ~BIT_MASK_R_MU_TABLE_VALID; + HALMAC_REG_W8(REG_MU_TX_CTL, (tmp14c0 | BIT(0) | BIT(1)) & ~(BIT(7))); + + /*config GID valid table and user position table*/ + mu_tbl_sel = HALMAC_REG_R8(REG_MU_TX_CTL + 1) & 0xF8; + + HALMAC_REG_W8(REG_MU_TX_CTL + 1, mu_tbl_sel); + HALMAC_REG_W32(REG_MU_STA_GID_VLD, param->given_gid_tab[0]); + HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]); + HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->given_user_pos[1]); + + HALMAC_REG_W8(REG_MU_TX_CTL + 1, mu_tbl_sel | 1); + HALMAC_REG_W32(REG_MU_STA_GID_VLD, param->given_gid_tab[1]); + HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]); + HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->given_user_pos[3]); +} + +static void +cfg_mu_bfer_88xx(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param) +{ + u8 i; + u8 idx; + u8 id0; + u8 id1; + u8 gid; + u8 mu_tbl_sel; + u8 mu_tbl_valid = 0; + u32 gid_valid[6] = {0}; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (param->mu_tx_en == _FALSE) { + HALMAC_REG_W8(REG_MU_TX_CTL, + HALMAC_REG_R8(REG_MU_TX_CTL) & ~(BIT(7))); + return; + } + + for (idx = 0; idx < 15; idx++) { + if (idx < 5) { + /*grouping_bitmap bit0~4, MU_STA0 with MUSTA1~5*/ + id0 = 0; + id1 = (u8)(idx + 1); + } else if (idx < 9) { + /*grouping_bitmap bit5~8, MU_STA1 with MUSTA2~5*/ + id0 = 1; + id1 = (u8)(idx - 3); + } else if (idx < 12) { + /*grouping_bitmap bit9~11, MU_STA2 with MUSTA3~5*/ + id0 = 2; + id1 = (u8)(idx - 6); + } else if (idx < 14) { + /*grouping_bitmap bit12~13, MU_STA3 with MUSTA4~5*/ + id0 = 3; + id1 = (u8)(idx - 8); + } else { + /*grouping_bitmap bit14, MU_STA4 with MUSTA5*/ + id0 = 4; + id1 = (u8)(idx - 9); + } + if (param->grouping_bitmap & BIT(idx)) { + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + /*Pair 2*/ + gid += 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + } else { + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + /*Pair 2*/ + gid += 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + } + } + + /*set MU STA GID valid TABLE*/ + mu_tbl_sel = HALMAC_REG_R8(REG_MU_TX_CTL + 1) & 0xF8; + for (idx = 0; idx < 6; idx++) { + HALMAC_REG_W8(REG_MU_TX_CTL + 1, idx | mu_tbl_sel); + HALMAC_REG_W32(REG_MU_STA_GID_VLD, gid_valid[idx]); + } + + /*To validate the sounding successful MU STA and enable MU TX*/ + for (i = 0; i < 6; i++) { + if (param->sounding_sts[i] == _TRUE) + mu_tbl_valid |= BIT(i); + } + HALMAC_REG_W8(REG_MU_TX_CTL, mu_tbl_valid | BIT(7)); +} + +/** + * cfg_sounding_88xx() - configure general sounding + * @adapter : the adapter of halmac + * @role : driver's role, BFer or BFee + * @rate : set ndpa tx rate if driver is BFer, + * or set csi response rate if driver is BFee + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role, + enum halmac_data_rate rate) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u32 tmp6dc = 0; + u8 csi_rsc = 0x1; + + /*use ndpa rx rate to decide csi rate*/ + tmp6dc = HALMAC_REG_R32(REG_BBPSF_CTRL) | BIT_WMAC_USE_NDPARATE + | (csi_rsc << 13); + + switch (role) { + case HAL_BFER: + HALMAC_REG_W32_SET(REG_TXBF_CTRL, TXBF_CTRL_CFG); + HALMAC_REG_W8(REG_NDPA_RATE, rate); + HALMAC_REG_W8_CLR(REG_NDPA_OPT_CTRL, BIT(0) | BIT(1)); + HALMAC_REG_W8(REG_SND_PTCL_CTRL + 1, 0x2 | BIT(7)); + HALMAC_REG_W8(REG_SND_PTCL_CTRL + 2, 0x2); + break; + case HAL_BFEE: + HALMAC_REG_W8(REG_SND_PTCL_CTRL, 0xDB); + HALMAC_REG_W8(REG_SND_PTCL_CTRL + 3, 0x26); + HALMAC_REG_W8_CLR(REG_RXFLTMAP1, BIT(4)); + HALMAC_REG_W8_CLR(REG_RXFLTMAP4, BIT(4)); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + /*AP mode set tx gid to 63*/ + /*STA mode set tx gid to 0*/ + if (BIT_GET_NETYPE0(HALMAC_REG_R32(REG_CR)) == 0x3) + HALMAC_REG_W32(REG_BBPSF_CTRL, tmp6dc | BIT(12)); + else + HALMAC_REG_W32(REG_BBPSF_CTRL, tmp6dc & ~(BIT(12))); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * del_sounding_88xx() - reset general sounding + * @adapter : the adapter of halmac + * @role : driver's role, BFer or BFee + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +del_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + switch (role) { + case HAL_BFER: + HALMAC_REG_W8(REG_TXBF_CTRL + 3, 0); + break; + case HAL_BFEE: + HALMAC_REG_W8(REG_SND_PTCL_CTRL, 0); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * su_bfee_entry_init_88xx() - config SU beamformee's registers + * @adapter : the adapter of halmac + * @userid : SU bfee userid = 0 or 1 to be added + * @paid : partial AID of this bfee + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +su_bfee_entry_init_88xx(struct halmac_adapter *adapter, u8 userid, u16 paid) +{ + u16 tmp42c = 0; + u16 tmp168x = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + switch (userid) { + case 0: + tmp42c = HALMAC_REG_R16(REG_TXBF_CTRL) & + ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | + BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_W16(REG_TXBF_CTRL, tmp42c | paid); + HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, paid); + #if HALMAC_8822C_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8822C) + HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, paid | BIT(9)); + #endif + break; + case 1: + tmp42c = HALMAC_REG_R16(REG_TXBF_CTRL + 2) & + ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | + BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_W16(REG_TXBF_CTRL + 2, tmp42c | paid); + HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL + 2, paid | BIT(9)); + break; + case 2: + tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE2); + tmp168x = BIT_CLEAR_WMAC_MU_BFEE2_AID(tmp168x); + tmp168x |= (paid | BIT(9)); + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE2, tmp168x); + break; + case 3: + tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE3); + tmp168x = BIT_CLEAR_WMAC_MU_BFEE3_AID(tmp168x); + tmp168x |= (paid | BIT(9)); + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE3, tmp168x); + break; + case 4: + tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE4); + tmp168x = BIT_CLEAR_WMAC_MU_BFEE4_AID(tmp168x); + tmp168x |= (paid | BIT(9)); + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE4, tmp168x); + break; + case 5: + tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE5); + tmp168x = BIT_CLEAR_WMAC_MU_BFEE5_AID(tmp168x); + tmp168x |= (paid | BIT(9)); + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE5, tmp168x); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * su_bfee_entry_init_88xx() - config SU beamformer's registers + * @adapter : the adapter of halmac + * @param : parameters to configure SU BFER entry + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +su_bfer_entry_init_88xx(struct halmac_adapter *adapter, + struct halmac_su_bfer_init_para *param) +{ + u16 mac_addr_h; + u32 mac_addr_l; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + mac_addr_l = rtk_le32_to_cpu(param->bfer_address.addr_l_h.low); + mac_addr_h = rtk_le16_to_cpu(param->bfer_address.addr_l_h.high); + + switch (param->userid) { + case 0: + HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, mac_addr_l); + HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 4, mac_addr_h); + HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 6, param->paid); + HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20, param->csi_para); + break; + case 1: + HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO, mac_addr_l); + HALMAC_REG_W16(REG_ASSOCIATED_BFMER1_INFO + 4, mac_addr_h); + HALMAC_REG_W16(REG_ASSOCIATED_BFMER1_INFO + 6, param->paid); + HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20 + 2, param->csi_para); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * mu_bfee_entry_init_88xx() - config MU beamformee's registers + * @adapter : the adapter of halmac + * @param : parameters to configure MU BFEE entry + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mu_bfee_entry_init_88xx(struct halmac_adapter *adapter, + struct halmac_mu_bfee_init_para *param) +{ + u16 tmp168x = 0; + u16 tmp14c0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + tmp168x |= param->paid | BIT(9); + HALMAC_REG_W16((0x1680 + param->userid * 2), tmp168x); + + tmp14c0 = HALMAC_REG_R16(REG_MU_TX_CTL) & ~(BIT(8) | BIT(9) | BIT(10)); + HALMAC_REG_W16(REG_MU_TX_CTL, tmp14c0 | ((param->userid - 2) << 8)); + HALMAC_REG_W32(REG_MU_STA_GID_VLD, 0); + HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->user_position_l); + HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->user_position_h); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * mu_bfer_entry_init_88xx() - config MU beamformer's registers + * @adapter : the adapter of halmac + * @param : parameters to configure MU BFER entry + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mu_bfer_entry_init_88xx(struct halmac_adapter *adapter, + struct halmac_mu_bfer_init_para *param) +{ + u16 tmp1680 = 0; + u16 mac_addr_h; + u32 mac_addr_l; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + mac_addr_l = rtk_le32_to_cpu(param->bfer_address.addr_l_h.low); + mac_addr_h = rtk_le16_to_cpu(param->bfer_address.addr_l_h.high); + + HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, mac_addr_l); + HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 4, mac_addr_h); + HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 6, param->paid); + HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20, param->csi_para); + + tmp1680 = HALMAC_REG_R16(0x1680) & 0xC000; + tmp1680 |= param->my_aid | (param->csi_length_sel << 12); + HALMAC_REG_W16(0x1680, tmp1680); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * su_bfee_entry_del_88xx() - reset SU beamformee's registers + * @adapter : the adapter of halmac + * @userid : the SU BFee userid to be deleted + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +su_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid) +{ + u16 value16; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + switch (userid) { + case 0: + value16 = HALMAC_REG_R16(REG_TXBF_CTRL); + value16 &= ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | + BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_W16(REG_TXBF_CTRL, value16); + HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, 0); + break; + case 1: + value16 = HALMAC_REG_R16(REG_TXBF_CTRL + 2); + value16 &= ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | + BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_W16(REG_TXBF_CTRL + 2, value16); + HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL + 2, 0); + break; + case 2: + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE2, 0); + break; + case 3: + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE3, 0); + break; + case 4: + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE4, 0); + break; + case 5: + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE5, 0); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * su_bfee_entry_del_88xx() - reset SU beamformer's registers + * @adapter : the adapter of halmac + * @userid : the SU BFer userid to be deleted + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +su_bfer_entry_del_88xx(struct halmac_adapter *adapter, u8 userid) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + switch (userid) { + case 0: + HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, 0); + HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO + 4, 0); + break; + case 1: + HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO, 0); + HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO + 4, 0); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * mu_bfee_entry_del_88xx() - reset MU beamformee's registers + * @adapter : the adapter of halmac + * @userid : the MU STA userid to be deleted + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W16(0x1680 + userid * 2, 0); + HALMAC_REG_W8_CLR(REG_MU_TX_CTL, BIT(userid - 2)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * mu_bfer_entry_del_88xx() -reset MU beamformer's registers + * @adapter : the adapter of halmac + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mu_bfer_entry_del_88xx(struct halmac_adapter *adapter) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, 0); + HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO + 4, 0); + HALMAC_REG_W16(0x1680, 0); + HALMAC_REG_W8(REG_MU_TX_CTL, 0); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_csi_rate_88xx() - config CSI frame Tx rate + * @adapter : the adapter of halmac + * @rssi : rssi in decimal value + * @cur_rate : current CSI frame rate + * @fixrate_en : enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate + * @new_rate : API returns the final CSI frame rate + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate, + u8 fixrate_en, u8 *new_rate) +{ + u32 csi_cfg; + u16 cur_rrsr; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + +#if HALMAC_8821C_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8821C && fixrate_en) { + csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE; + HALMAC_REG_W32(REG_BBPSF_CTRL, + csi_cfg | BIT_CSI_FORCE_RATE_EN | + BIT_CSI_RSC(1) | + BIT_WMAC_CSI_RATE(HALMAC_VHT_NSS1_MCS3)); + *new_rate = HALMAC_VHT_NSS1_MCS3; + return HALMAC_RET_SUCCESS; + } + csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE & + ~BIT_CSI_FORCE_RATE_EN; +#else + csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE; +#endif + + cur_rrsr = HALMAC_REG_R16(REG_RRSR); + + if (rssi >= 40) { + if (cur_rate != HALMAC_OFDM54) { + cur_rrsr |= BIT(HALMAC_OFDM54); + csi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM54); + HALMAC_REG_W16(REG_RRSR, cur_rrsr); + HALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg); + } + *new_rate = HALMAC_OFDM54; + } else { + if (cur_rate != HALMAC_OFDM24) { + cur_rrsr &= ~(BIT(HALMAC_OFDM54)); + csi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM24); + HALMAC_REG_W16(REG_RRSR, cur_rrsr); + HALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg); + } + *new_rate = HALMAC_OFDM24; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * fw_snding_88xx() - fw sounding control + * @adapter : the adapter of halmac + * @su_info : + * su0_en : enable/disable fw sounding + * su0_ndpa_pkt : ndpa pkt, shall include txdesc + * su0_pkt_sz : ndpa pkt size, shall include txdesc + * @mu_info : currently not in use, input NULL is acceptable + * @period : sounding period, unit is 5ms + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +fw_snding_88xx(struct halmac_adapter *adapter, + struct halmac_su_snding_info *su_info, + struct halmac_mu_snding_info *mu_info, u8 period) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num; + u16 snding_info_addr; + struct halmac_h2c_header_info hdr_info; + enum halmac_cmd_process_status *proc_status; + enum halmac_ret_status status; + + proc_status = &adapter->halmac_state.fw_snding_state.proc_status; + + if (adapter->chip_id == HALMAC_CHIP_ID_8821C) + return HALMAC_RET_NOT_SUPPORT; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (adapter->fw_ver.h2c_version < 9) + return HALMAC_RET_FW_NO_SUPPORT; + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_TRACE("[TRACE]Wait event(snd)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (su_info->su0_en == 1) { + if (!su_info->su0_ndpa_pkt) + return HALMAC_RET_NULL_POINTER; + + if (su_info->su0_pkt_sz > (u32)SU0_SNDING_PKT_RSVDPG_SIZE - + adapter->hw_cfg_info.txdesc_size) + return HALMAC_RET_DATA_SIZE_INCORRECT; + + if (!snding_pkt_chk_88xx(adapter, su_info->su0_ndpa_pkt)) + return HALMAC_RET_TXDESC_SET_FAIL; + + if (fw_snding_cmd_cnstr_state_88xx(adapter) != + HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_ERR("[ERR]Not idle(snd)\n"); + return HALMAC_RET_ERROR_STATE; + } + + snding_info_addr = adapter->txff_alloc.rsvd_h2c_sta_info_addr + + SU0_SNDING_PKT_OFFSET; + status = dl_rsvd_page_88xx(adapter, snding_info_addr, + su_info->su0_ndpa_pkt, + su_info->su0_pkt_sz); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dl rsvd page\n"); + return status; + } + + FW_SNDING_SET_SU0(h2c_buf, 1); + FW_SNDING_SET_PERIOD(h2c_buf, period); + FW_SNDING_SET_NDPA0_HEAD_PG(h2c_buf, snding_info_addr - + adapter->txff_alloc.rsvd_boundary); + } else { + if (fw_snding_cmd_cnstr_state_88xx(adapter) != + HALMAC_CMD_CNSTR_BUSY) { + PLTFM_MSG_ERR("[ERR]Not snd(snd)\n"); + return HALMAC_RET_ERROR_STATE; + } + FW_SNDING_SET_SU0(h2c_buf, 0); + } + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + hdr_info.sub_cmd_id = SUB_CMD_ID_FW_SNDING; + hdr_info.content_size = 8; + hdr_info.ack = _TRUE; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + adapter->halmac_state.fw_snding_state.seq_num = seq_num; + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_FW_SNDING); + return status; + } + + if (cnv_fw_snding_state_88xx(adapter, su_info->su0_en == 1 ? + HALMAC_CMD_CNSTR_BUSY : + HALMAC_CMD_CNSTR_IDLE) + != HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + return HALMAC_RET_SUCCESS; +} + +static u8 +snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt) +{ + u8 data_rate; + + if (GET_TX_DESC_NDPA(pkt) == 0) { + PLTFM_MSG_ERR("[ERR]txdesc ndpa = 0\n"); + return _FALSE; + } + + data_rate = (u8)GET_TX_DESC_DATARATE(pkt); + if (!(data_rate >= HALMAC_VHT_NSS2_MCS0 && + data_rate <= HALMAC_VHT_NSS2_MCS9)) { + if (!(data_rate >= HALMAC_MCS8 && data_rate <= HALMAC_MCS15)) { + PLTFM_MSG_ERR("[ERR]txdesc rate\n"); + return _FALSE; + } + } + + if (GET_TX_DESC_NAVUSEHDR(pkt) == 0) { + PLTFM_MSG_ERR("[ERR]txdesc navusehdr = 0\n"); + return _FALSE; + } + + if (GET_TX_DESC_USE_RATE(pkt) == 0) { + PLTFM_MSG_ERR("[ERR]txdesc userate = 0\n"); + return _FALSE; + } + + return _TRUE; +} + +static enum halmac_cmd_construct_state +fw_snding_cmd_cnstr_state_88xx(struct halmac_adapter *adapter) +{ + return adapter->halmac_state.fw_snding_state.cmd_cnstr_state; +} + +enum halmac_ret_status +get_h2c_ack_fw_snding_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num = 0; + u8 fw_rc; + struct halmac_fw_snding_state *state; + enum halmac_cmd_process_status proc_status; + + state = &adapter->halmac_state.fw_snding_state; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num:h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch:h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not sending(snd)\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + + if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) { + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_FW_SNDING, proc_status, + NULL, 0); + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_FW_SNDING, proc_status, + &fw_rc, 1); + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_fw_snding_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status) +{ + *proc_status = adapter->halmac_state.fw_snding_state.proc_status; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +cnv_fw_snding_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state) +{ + struct halmac_fw_snding_state *state; + + state = &adapter->halmac_state.fw_snding_state; + + if (state->cmd_cnstr_state != HALMAC_CMD_CNSTR_IDLE && + state->cmd_cnstr_state != HALMAC_CMD_CNSTR_BUSY) + return HALMAC_RET_ERROR_STATE; + + if (dest_state == HALMAC_CMD_CNSTR_IDLE) { + if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_IDLE) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_BUSY) { + if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_BUSY) + return HALMAC_RET_ERROR_STATE; + } + + state->cmd_cnstr_state = dest_state; + + return HALMAC_RET_SUCCESS; +} +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_mimo_88xx.h b/hal/halmac/halmac_88xx/halmac_mimo_88xx.h new file mode 100644 index 0000000..95d0372 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_mimo_88xx.h @@ -0,0 +1,83 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_MIMO_88XX_H_ +#define _HALMAC_MIMO_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw, + u8 txbf_en); + +enum halmac_ret_status +cfg_mumimo_88xx(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param); + +enum halmac_ret_status +cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role, + enum halmac_data_rate rate); + +enum halmac_ret_status +del_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role); + +enum halmac_ret_status +su_bfee_entry_init_88xx(struct halmac_adapter *adapter, u8 userid, u16 paid); + +enum halmac_ret_status +su_bfer_entry_init_88xx(struct halmac_adapter *adapter, + struct halmac_su_bfer_init_para *param); + +enum halmac_ret_status +mu_bfee_entry_init_88xx(struct halmac_adapter *adapter, + struct halmac_mu_bfee_init_para *param); + +enum halmac_ret_status +mu_bfer_entry_init_88xx(struct halmac_adapter *adapter, + struct halmac_mu_bfer_init_para *param); + +enum halmac_ret_status +su_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid); + +enum halmac_ret_status +su_bfer_entry_del_88xx(struct halmac_adapter *adapter, u8 userid); + +enum halmac_ret_status +mu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid); + +enum halmac_ret_status +mu_bfer_entry_del_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate, + u8 fixrate_en, u8 *new_rate); + +enum halmac_ret_status +fw_snding_88xx(struct halmac_adapter *adapter, + struct halmac_su_snding_info *su_info, + struct halmac_mu_snding_info *mu_info, u8 period); + +enum halmac_ret_status +get_h2c_ack_fw_snding_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +enum halmac_ret_status +get_fw_snding_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_MIMO_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_pcie_88xx.c b/hal/halmac/halmac_88xx/halmac_pcie_88xx.c new file mode 100644 index 0000000..4842325 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_pcie_88xx.c @@ -0,0 +1,543 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_pcie_88xx.h" + +#if HALMAC_88XX_SUPPORT + +/** + * init_pcie_cfg_88xx() - init PCIe + * @adapter : the adapter of halmac + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_pcie_cfg_88xx(struct halmac_adapter *adapter) +{ + if (adapter->intf != HALMAC_INTERFACE_PCIE) + return HALMAC_RET_WRONG_INTF; + + return HALMAC_RET_SUCCESS; +} + +/** + * deinit_pcie_cfg_88xx() - deinit PCIE + * @adapter : the adapter of halmac + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +deinit_pcie_cfg_88xx(struct halmac_adapter *adapter) +{ + if (adapter->intf != HALMAC_INTERFACE_PCIE) + return HALMAC_RET_WRONG_INTF; + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_pcie_rx_agg_88xx() - config rx aggregation + * @adapter : the adapter of halmac + * @halmac_rx_agg_mode + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter, + struct halmac_rxagg_cfg *cfg) +{ + return HALMAC_RET_SUCCESS; +} + +/** + * reg_r8_pcie_88xx() - read 1byte register + * @adapter : the adapter of halmac + * @offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u8 +reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset) +{ + return PLTFM_REG_R8(offset); +} + +/** + * reg_w8_pcie_88xx() - write 1byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @value : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value) +{ + PLTFM_REG_W8(offset, value); + + return HALMAC_RET_SUCCESS; +} + +/** + * reg_r16_pcie_88xx() - read 2byte register + * @adapter : the adapter of halmac + * @offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u16 +reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset) +{ + return PLTFM_REG_R16(offset); +} + +/** + * reg_w16_pcie_88xx() - write 2byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @value : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value) +{ + PLTFM_REG_W16(offset, value); + + return HALMAC_RET_SUCCESS; +} + +/** + * reg_r32_pcie_88xx() - read 4byte register + * @adapter : the adapter of halmac + * @offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u32 +reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset) +{ + return PLTFM_REG_R32(offset); +} + +/** + * reg_w32_pcie_88xx() - write 4byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @value : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value) +{ + PLTFM_REG_W32(offset, value); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_txagg_pcie_align_88xx() -config sdio bus tx agg alignment + * @adapter : the adapter of halmac + * @enable : function enable(1)/disable(0) + * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11) + * Author : Soar Tu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable, + u16 align_size) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * tx_allowed_pcie_88xx() - check tx status + * @adapter : the adapter of halmac + * @buf : tx packet, include txdesc + * @size : tx packet size, include txdesc + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * pcie_indirect_reg_r32_88xx() - read MAC reg by SDIO reg + * @adapter : the adapter of halmac + * @offset : register offset + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u32 +pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset) +{ + return 0xFFFFFFFF; +} + +/** + * pcie_reg_rn_88xx() - read n byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @size : register value size + * @value : register value + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + u8 *value) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * set_pcie_bulkout_num_88xx() - inform bulk-out num + * @adapter : the adapter of halmac + * @num : usb bulk-out number + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * get_pcie_tx_addr_88xx() - get CMD53 addr for the TX packet + * @adapter : the adapter of halmac + * @buf : tx packet, include txdesc + * @size : tx packet size + * @cmd53_addr : cmd53 addr value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u32 *cmd53_addr) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * get_pcie_bulkout_id_88xx() - get bulk out id for the TX packet + * @adapter : the adapter of halmac + * @buf : tx packet, include txdesc + * @size : tx packet size + * @id : usb bulk-out id + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u8 *id) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +enum halmac_ret_status +mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed) +{ + u8 tmp_u1b = 0; + u32 cnt = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 real_addr = 0; + + HALMAC_REG_W16(REG_MDIO_V1, data); + + real_addr = (addr & 0x1F); + HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr); + + if (speed == HAL_INTF_PHY_PCIE_GEN1) { + if (addr < 0x20) + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00); + else + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01); + } else if (speed == HAL_INTF_PHY_PCIE_GEN2) { + if (addr < 0x20) + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02); + else + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03); + } else { + PLTFM_MSG_ERR("[ERR]Error Speed !\n"); + } + + HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1); + + tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1; + cnt = 20; + + while (tmp_u1b && (cnt != 0)) { + PLTFM_DELAY_US(10); + tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1; + cnt--; + } + + if (tmp_u1b) { + PLTFM_MSG_ERR("[ERR]MDIO write fail!\n"); + return HALMAC_RET_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +u16 +mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed) +{ + u16 ret = 0; + u8 tmp_u1b = 0; + u32 cnt = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 real_addr = 0; + + real_addr = (addr & 0x1F); + HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr); + + if (speed == HAL_INTF_PHY_PCIE_GEN1) { + if (addr < 0x20) + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00); + else + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01); + } else if (speed == HAL_INTF_PHY_PCIE_GEN2) { + if (addr < 0x20) + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02); + else + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03); + } else { + PLTFM_MSG_ERR("[ERR]Error Speed !\n"); + } + + HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_RFLAG_V1); + + tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1; + cnt = 20; + while (tmp_u1b && (cnt != 0)) { + PLTFM_DELAY_US(10); + tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1; + cnt--; + } + + if (tmp_u1b) { + ret = 0xFFFF; + PLTFM_MSG_ERR("[ERR]MDIO read fail!\n"); + } else { + ret = HALMAC_REG_R16(REG_MDIO_V1 + 2); + PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret); + } + + return ret; +} + +enum halmac_ret_status +dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data) +{ + u8 tmp_u1b = 0; + u32 cnt = 0; + u16 write_addr = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W32(REG_DBI_WDATA_V1, data); + + write_addr = ((addr & 0x0ffc) | (0x000F << 12)); + HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr); + + PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr); + + HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01); + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + + cnt = 20; + while (tmp_u1b && (cnt != 0)) { + PLTFM_DELAY_US(10); + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + cnt--; + } + + if (tmp_u1b) { + PLTFM_MSG_ERR("[ERR]DBI write fail!\n"); + return HALMAC_RET_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +u32 +dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr) +{ + u16 read_addr = addr & 0x0ffc; + u8 tmp_u1b = 0; + u32 cnt = 0; + u32 ret = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr); + + HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2); + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + + cnt = 20; + while (tmp_u1b && (cnt != 0)) { + PLTFM_DELAY_US(10); + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + cnt--; + } + + if (tmp_u1b) { + ret = 0xFFFF; + PLTFM_MSG_ERR("[ERR]DBI read fail!\n"); + } else { + ret = HALMAC_REG_R32(REG_DBI_RDATA_V1); + PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret); + } + + return ret; +} + +enum halmac_ret_status +dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data) +{ + u8 tmp_u1b = 0; + u32 cnt = 0; + u16 write_addr = 0; + u16 remainder = addr & (4 - 1); + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W8(REG_DBI_WDATA_V1 + remainder, data); + + write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12))); + + HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr); + + PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr); + + HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01); + + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + + cnt = 20; + while (tmp_u1b && (cnt != 0)) { + PLTFM_DELAY_US(10); + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + cnt--; + } + + if (tmp_u1b) { + PLTFM_MSG_ERR("[ERR]DBI write fail!\n"); + return HALMAC_RET_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +u8 +dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr) +{ + u16 read_addr = addr & 0x0ffc; + u8 tmp_u1b = 0; + u32 cnt = 0; + u8 ret = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr); + HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2); + + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + + cnt = 20; + while (tmp_u1b && (cnt != 0)) { + PLTFM_DELAY_US(10); + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + cnt--; + } + + if (tmp_u1b) { + ret = 0xFF; + PLTFM_MSG_ERR("[ERR]DBI read fail!\n"); + } else { + ret = HALMAC_REG_R8(REG_DBI_RDATA_V1 + (addr & (4 - 1))); + PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret); + } + + return ret; +} + +enum halmac_ret_status +trxdma_check_idle_88xx(struct halmac_adapter *adapter) +{ + u32 cnt = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + /* Stop Tx & Rx DMA */ + HALMAC_REG_W32_SET(REG_RXPKT_NUM, BIT(18)); + HALMAC_REG_W16_SET(REG_PCIE_CTRL, ~(BIT(15) | BIT(8))); + + /* Stop FW */ + HALMAC_REG_W16_CLR(REG_SYS_FUNC_EN, BIT(10)); + + /* Check Tx DMA is idle */ + cnt = 20; + while ((HALMAC_REG_R8(REG_SYS_CFG5) & BIT(2)) == BIT(2)) { + PLTFM_DELAY_US(10); + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]Chk tx idle\n"); + return HALMAC_RET_POWER_OFF_FAIL; + } + } + + /* Check Rx DMA is idle */ + cnt = 20; + while ((HALMAC_REG_R32(REG_RXPKT_NUM) & BIT(17)) != BIT(17)) { + PLTFM_DELAY_US(10); + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]Chk rx idle\n"); + return HALMAC_RET_POWER_OFF_FAIL; + } + } + + return HALMAC_RET_SUCCESS; +} + +void +en_ref_autok_88xx(struct halmac_adapter *adapter, u8 en) +{ + if (en == 1) + adapter->pcie_refautok_en = 1; + else + adapter->pcie_refautok_en = 0; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_pcie_88xx.h b/hal/halmac/halmac_88xx/halmac_pcie_88xx.h new file mode 100644 index 0000000..c3956b9 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_pcie_88xx.h @@ -0,0 +1,102 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_PCIE_88XX_H_ +#define _HALMAC_PCIE_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +init_pcie_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +deinit_pcie_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter, + struct halmac_rxagg_cfg *cfg); + +u8 +reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value); + +u16 +reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value); + +u32 +reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value); + +enum halmac_ret_status +cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable, + u16 align_size); + +enum halmac_ret_status +tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +u32 +pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + u8 *value); + +enum halmac_ret_status +set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num); + +enum halmac_ret_status +get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u32 *cmd53_addr); + +enum halmac_ret_status +get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u8 *id); + +enum halmac_ret_status +mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed); + +u16 +mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed); + +enum halmac_ret_status +dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data); + +u32 +dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr); + +enum halmac_ret_status +dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data); + +u8 +dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr); + +enum halmac_ret_status +trxdma_check_idle_88xx(struct halmac_adapter *adapter); + +void +en_ref_autok_88xx(struct halmac_adapter *dapter, u8 en); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_PCIE_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_sdio_88xx.c b/hal/halmac/halmac_88xx/halmac_sdio_88xx.c new file mode 100644 index 0000000..ef9fb89 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_sdio_88xx.c @@ -0,0 +1,892 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_sdio_88xx.h" +#include "halmac_88xx_cfg.h" + +#if HALMAC_88XX_SUPPORT + +/* define the SDIO Bus CLK threshold */ +/* for avoiding CMD53 fails that result from SDIO CLK sync to ana_clk fail */ +#define SDIO_CLK_HIGH_SPEED_TH 50 /* 50MHz */ +#define SDIO_CLK_SPEED_MAX 208 /* 208MHz */ + +/*only for r_indir_sdio_88xx !!, Soar 20171222*/ +static u8 +r_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 offset); + +/*only for r_indir_sdio_88xx !!, Soar 20171222*/ +static u32 +r_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 offset); + +/*only for r_indir_sdio_88xx !!, Soar 20171222*/ +static u32 +r8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr); + +/*only for r_indir_sdio_88xx !!, Soar 20171222*/ +static u32 +r16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr); + +/*only for r_indir_sdio_88xx !!, Soar 20171222*/ +static u32 +r32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr); + +/*only for w_indir_sdio_88xx !!, Soar 20171222*/ +static enum halmac_ret_status +w_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 adr, u32 val, + enum halmac_io_size size); + +/*only for w_indir_sdio_88xx !!, Soar 20171222*/ +static enum halmac_ret_status +w_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 adr, u32 val, + enum halmac_io_size size); + +/*only for w_indir_sdio_88xx !!, Soar 20171222*/ +static enum halmac_ret_status +w8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val); + +/*only for w_indir_sdio_88xx !!, Soar 20171222*/ +static enum halmac_ret_status +w16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val); + +/*only for w_indir_sdio_88xx !!, Soar 20171222*/ +static enum halmac_ret_status +w32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val); + +/** + * init_sdio_cfg_88xx() - init SDIO + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_sdio_cfg_88xx(struct halmac_adapter *adapter) +{ + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (adapter->intf != HALMAC_INTERFACE_SDIO) + return HALMAC_RET_WRONG_INTF; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + HALMAC_REG_R32(REG_SDIO_FREE_TXPG); + + value32 = HALMAC_REG_R32(REG_SDIO_TX_CTRL) & 0xFFFF; + value32 &= ~(BIT_CMD_ERR_STOP_INT_EN | BIT_EN_MASK_TIMER | + BIT_EN_RXDMA_MASK_INT); + HALMAC_REG_W32(REG_SDIO_TX_CTRL, value32); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * deinit_sdio_cfg_88xx() - deinit SDIO + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +deinit_sdio_cfg_88xx(struct halmac_adapter *adapter) +{ + if (adapter->intf != HALMAC_INTERFACE_SDIO) + return HALMAC_RET_WRONG_INTF; + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_sdio_rx_agg_88xx() - config rx aggregation + * @adapter : the adapter of halmac + * @halmac_rx_agg_mode + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_sdio_rx_agg_88xx(struct halmac_adapter *adapter, + struct halmac_rxagg_cfg *cfg) +{ + u8 value8; + u8 size; + u8 timeout; + u8 agg_enable; + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + agg_enable = HALMAC_REG_R8(REG_TXDMA_PQ_MAP); + + switch (cfg->mode) { + case HALMAC_RX_AGG_MODE_NONE: + agg_enable &= ~(BIT_RXDMA_AGG_EN); + break; + case HALMAC_RX_AGG_MODE_DMA: + case HALMAC_RX_AGG_MODE_USB: + agg_enable |= BIT_RXDMA_AGG_EN; + break; + default: + PLTFM_MSG_ERR("[ERR]unsupported mode\n"); + agg_enable &= ~BIT_RXDMA_AGG_EN; + break; + } + + if (cfg->threshold.drv_define == _FALSE) { + size = 0xFF; + timeout = 0x01; + } else { + size = cfg->threshold.size; + timeout = cfg->threshold.timeout; + } + + value32 = HALMAC_REG_R32(REG_RXDMA_AGG_PG_TH); + if (cfg->threshold.size_limit_en == _FALSE) + HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 & ~BIT_EN_PRE_CALC); + else + HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 | BIT_EN_PRE_CALC); + + HALMAC_REG_W8(REG_TXDMA_PQ_MAP, agg_enable); + HALMAC_REG_W16(REG_RXDMA_AGG_PG_TH, + (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1))); + + value8 = HALMAC_REG_R8(REG_RXDMA_MODE); + if (0 != (agg_enable & BIT_RXDMA_AGG_EN)) + HALMAC_REG_W8(REG_RXDMA_MODE, value8 | BIT_DMA_MODE); + else + HALMAC_REG_W8(REG_RXDMA_MODE, value8 & ~(BIT_DMA_MODE)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * sdio_reg_rn_88xx() - read n byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @halmac_size : register value size + * @value : register value + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +sdio_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + u8 *value) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (0 == (offset & 0xFFFF0000)) { + PLTFM_MSG_ERR("[ERR]offset 0x%x\n", offset); + return HALMAC_RET_FAIL; + } + + status = cnv_to_sdio_bus_offset_88xx(adapter, &offset); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]convert offset\n"); + return status; + } + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) { + PLTFM_MSG_ERR("[ERR]power off\n"); + return HALMAC_RET_FAIL; + } + + PLTFM_SDIO_CMD53_RN(offset, size, value); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_txagg_sdio_align_88xx() -config sdio bus tx agg alignment + * @adapter : the adapter of halmac + * @enable : function enable(1)/disable(0) + * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11) + * Author : Soar Tu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_txagg_sdio_align_88xx(struct halmac_adapter *adapter, u8 enable, + u16 align_size) +{ + u8 i; + u8 flag = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (adapter->chip_id == HALMAC_CHIP_ID_8822B) + return HALMAC_RET_NOT_SUPPORT; + + if ((align_size & 0xF000) != 0) { + PLTFM_MSG_ERR("[ERR]out of range\n"); + return HALMAC_RET_FAIL; + } + + for (i = 3; i <= 11; i++) { + if (align_size == 1 << i) { + flag = 1; + break; + } + } + + if (flag == 0) { + PLTFM_MSG_ERR("[ERR]not 2^3 ~ 2^11\n"); + return HALMAC_RET_FAIL; + } + + adapter->hw_cfg_info.tx_align_size = align_size; + + if (enable) + HALMAC_REG_W16(REG_RQPN_CTRL_2, 0x8000 | align_size); + else + HALMAC_REG_W16(REG_RQPN_CTRL_2, align_size); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * sdio_indirect_reg_r32_88xx() - read MAC reg by SDIO reg + * @adapter : the adapter of halmac + * @offset : register offset + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u32 +sdio_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset) +{ + return r_indir_sdio_88xx(adapter, offset, HALMAC_IO_DWORD); +} + +/** + * set_sdio_bulkout_num_88xx() - inform bulk-out num + * @adapter : the adapter of halmac + * @bulkout_num : usb bulk-out number + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +set_sdio_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * get_sdio_bulkout_id_88xx() - get bulk out id for the TX packet + * @adapter : the adapter of halmac + * @halmac_buf : tx packet, include txdesc + * @halmac_size : tx packet size + * @bulkout_id : usb bulk-out id + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_sdio_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u8 *id) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * sdio_cmd53_4byte_88xx() - cmd53 only for 4byte len register IO + * @adapter : the adapter of halmac + * @enable : 1->CMD53 only use in 4byte reg, 0 : No limitation + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +sdio_cmd53_4byte_88xx(struct halmac_adapter *adapter, + enum halmac_sdio_cmd53_4byte_mode mode) +{ + if (adapter->intf != HALMAC_INTERFACE_SDIO) + return HALMAC_RET_WRONG_INTF; + + if (adapter->api_registry.sdio_cmd53_4byte_en == 0) + return HALMAC_RET_NOT_SUPPORT; + + adapter->sdio_cmd53_4byte = mode; + + return HALMAC_RET_SUCCESS; +} + +/** + * sdio_hw_info_88xx() - info sdio hw info + * @adapter : the adapter of halmac + * @HALMAC_SDIO_CMD53_4BYTE_MODE : + * clock_speed : sdio bus clock. Unit -> MHz + * spec_ver : sdio spec version + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +sdio_hw_info_88xx(struct halmac_adapter *adapter, + struct halmac_sdio_hw_info *info) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (adapter->intf != HALMAC_INTERFACE_SDIO) + return HALMAC_RET_WRONG_INTF; + + PLTFM_MSG_TRACE("[TRACE]SDIO clock:%d, spec:%d\n", + info->clock_speed, info->spec_ver); + + if (info->clock_speed > SDIO_CLK_SPEED_MAX) + return HALMAC_RET_SDIO_CLOCK_ERR; + + if (info->clock_speed > SDIO_CLK_HIGH_SPEED_TH) + adapter->sdio_hw_info.io_hi_speed_flag = 1; + + adapter->sdio_hw_info.io_indir_flag = info->io_indir_flag; + if (info->clock_speed > SDIO_CLK_HIGH_SPEED_TH && + adapter->sdio_hw_info.io_indir_flag == 0) + PLTFM_MSG_WARN("[WARN]SDIO clock:%d, indir access is better\n", + info->clock_speed); + + adapter->sdio_hw_info.clock_speed = info->clock_speed; + adapter->sdio_hw_info.spec_ver = info->spec_ver; + adapter->sdio_hw_info.block_size = info->block_size; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +void +cfg_sdio_tx_page_threshold_88xx(struct halmac_adapter *adapter, + struct halmac_tx_page_threshold_info *info) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u32 threshold = info->threshold; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (info->enable == 1) { + threshold = BIT(31) | threshold; + PLTFM_MSG_TRACE("[TRACE]enable\n"); + } else { + threshold = ~(BIT(31)) & threshold; + PLTFM_MSG_TRACE("[TRACE]disable\n"); + } + + switch (info->dma_queue_sel) { + case HALMAC_MAP2_HQ: + HALMAC_REG_W32(REG_TQPNT1, threshold); + break; + case HALMAC_MAP2_NQ: + HALMAC_REG_W32(REG_TQPNT2, threshold); + break; + case HALMAC_MAP2_LQ: + HALMAC_REG_W32(REG_TQPNT3, threshold); + break; + case HALMAC_MAP2_EXQ: + HALMAC_REG_W32(REG_TQPNT4, threshold); + break; + default: + break; + } + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); +} + +enum halmac_ret_status +cnv_to_sdio_bus_offset_88xx(struct halmac_adapter *adapter, u32 *offset) +{ + switch ((*offset) & 0xFFFF0000) { + case WLAN_IOREG_OFFSET: + *offset &= HALMAC_WLAN_MAC_REG_MSK; + *offset |= HALMAC_SDIO_CMD_ADDR_MAC_REG << 13; + break; + case SDIO_LOCAL_OFFSET: + *offset &= HALMAC_SDIO_LOCAL_MSK; + *offset |= HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13; + break; + default: + *offset = 0xFFFFFFFF; + PLTFM_MSG_ERR("[ERR]base address!!\n"); + return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +leave_sdio_suspend_88xx(struct halmac_adapter *adapter) +{ + u8 value8; + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + value8 = HALMAC_REG_R8(REG_SDIO_HSUS_CTRL); + HALMAC_REG_W8(REG_SDIO_HSUS_CTRL, value8 & ~(BIT(0))); + + cnt = 10000; + while (!(HALMAC_REG_R8(REG_SDIO_HSUS_CTRL) & 0x02)) { + cnt--; + if (cnt == 0) + return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL; + } + + value8 = HALMAC_REG_R8(REG_HCI_OPT_CTRL + 2); + if (adapter->sdio_hw_info.spec_ver == HALMAC_SDIO_SPEC_VER_3_00) + HALMAC_REG_W8(REG_HCI_OPT_CTRL + 2, value8 | BIT(2)); + else + HALMAC_REG_W8(REG_HCI_OPT_CTRL + 2, value8 & ~(BIT(2))); + + return HALMAC_RET_SUCCESS; +} + +/*only for r_indir_sdio_88xx !!, Soar 20171222*/ +static u8 +r_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 offset) +{ + u8 value8, tmp, cnt = 50; + u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG; + u32 reg_data = REG_SDIO_INDIRECT_REG_DATA; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg); + if (status != HALMAC_RET_SUCCESS) + return status; + status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data); + if (status != HALMAC_RET_SUCCESS) + return status; + + PLTFM_SDIO_CMD52_W(reg_cfg, (u8)offset); + PLTFM_SDIO_CMD52_W(reg_cfg + 1, (u8)(offset >> 8)); + PLTFM_SDIO_CMD52_W(reg_cfg + 2, (u8)(BIT(3) | BIT(4))); + + do { + tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2); + cnt--; + } while (((tmp & BIT(4)) == 0) && (cnt > 0)); + + if (((cnt & BIT(4)) == 0) && cnt == 0) + PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 read\n"); + + value8 = PLTFM_SDIO_CMD52_R(reg_data); + + return value8; +} + +/*only for r_indir_sdio_88xx !!, Soar 20171222*/ +static u32 +r_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 offset) +{ + u8 tmp, cnt = 50; + u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG; + u32 reg_data = REG_SDIO_INDIRECT_REG_DATA; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + union { + u32 dword; + u8 byte[4]; + } value32 = { 0x00000000 }; + + status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg); + if (status != HALMAC_RET_SUCCESS) + return status; + status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data); + if (status != HALMAC_RET_SUCCESS) + return status; + + PLTFM_SDIO_CMD53_W32(reg_cfg, offset | BIT(19) | BIT(20)); + + do { + tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2); + cnt--; + } while (((tmp & BIT(4)) == 0) && (cnt > 0)); + + if (((cnt & BIT(4)) == 0) && cnt == 0) + PLTFM_MSG_ERR("[ERR]sdio indirect CMD53 read\n"); + + value32.dword = PLTFM_SDIO_CMD53_R32(reg_data); + + return value32.dword; +} + +/*only for r_indir_sdio_88xx !!, Soar 20171222*/ +static u32 +r8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr) +{ + union { + u32 dword; + u8 byte[4]; + } val = { 0x00000000 }; + + if (adapter->pwr_off_flow_flag == 1 || + adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) { + val.byte[0] = r_indir_cmd52_88xx(adapter, adr); + val.dword = rtk_le32_to_cpu(val.dword); + } else { + val.dword = r_indir_cmd53_88xx(adapter, adr); + } + + return val.dword; +} + +/*only for r_indir_sdio_88xx !!, Soar 20171222*/ +static u32 +r16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr) +{ + u32 reg_data = REG_SDIO_INDIRECT_REG_DATA; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + union { + u32 dword; + u8 byte[4]; + } val = { 0x00000000 }; + + status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data); + if (status != HALMAC_RET_SUCCESS) + return status; + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) { + if (0 != (adr & (2 - 1))) { + val.byte[0] = r_indir_cmd52_88xx(adapter, adr); + val.byte[1] = r_indir_cmd52_88xx(adapter, adr + 1); + } else { + val.byte[0] = r_indir_cmd52_88xx(adapter, adr); + val.byte[1] = PLTFM_SDIO_CMD52_R(reg_data + 1); + } + val.dword = rtk_le32_to_cpu(val.dword); + } else { + if (0 != (adr & (2 - 1))) { + val.byte[0] = (u8)r_indir_cmd53_88xx(adapter, adr); + val.byte[1] = (u8)r_indir_cmd53_88xx(adapter, adr + 1); + val.dword = rtk_le32_to_cpu(val.dword); + } else { + val.dword = r_indir_cmd53_88xx(adapter, adr); + } + } + return val.dword; +} + +/*only for r_indir_sdio_88xx !!, Soar 20171222*/ +static u32 +r32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr) +{ + u32 reg_data = REG_SDIO_INDIRECT_REG_DATA; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + union { + u32 dword; + u8 byte[4]; + } val = { 0x00000000 }; + + status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data); + if (status != HALMAC_RET_SUCCESS) + return status; + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) { + if (0 != (adr & (4 - 1))) { + val.byte[0] = r_indir_cmd52_88xx(adapter, adr); + val.byte[1] = r_indir_cmd52_88xx(adapter, adr + 1); + val.byte[2] = r_indir_cmd52_88xx(adapter, adr + 2); + val.byte[3] = r_indir_cmd52_88xx(adapter, adr + 3); + } else { + val.byte[0] = r_indir_cmd52_88xx(adapter, adr); + val.byte[1] = PLTFM_SDIO_CMD52_R(reg_data + 1); + val.byte[2] = PLTFM_SDIO_CMD52_R(reg_data + 2); + val.byte[3] = PLTFM_SDIO_CMD52_R(reg_data + 3); + } + val.dword = rtk_le32_to_cpu(val.dword); + } else { + if (0 != (adr & (4 - 1))) { + val.byte[0] = (u8)r_indir_cmd53_88xx(adapter, adr); + val.byte[1] = (u8)r_indir_cmd53_88xx(adapter, adr + 1); + val.byte[2] = (u8)r_indir_cmd53_88xx(adapter, adr + 2); + val.byte[3] = (u8)r_indir_cmd53_88xx(adapter, adr + 3); + val.dword = rtk_le32_to_cpu(val.dword); + } else { + val.dword = r_indir_cmd53_88xx(adapter, adr); + } + } + return val.dword; +} + +u32 +r_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, + enum halmac_io_size size) +{ + u32 reg_data = REG_SDIO_INDIRECT_REG_DATA; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + union { + u32 dword; + u8 byte[4]; + } val = { 0x00000000 }; + + status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data); + if (status != HALMAC_RET_SUCCESS) + return status; + + PLTFM_MUTEX_LOCK(&adapter->sdio_indir_mutex); + + switch (size) { + case HALMAC_IO_BYTE: + val.dword = r8_indir_sdio_88xx(adapter, adr); + break; + case HALMAC_IO_WORD: + val.dword = r16_indir_sdio_88xx(adapter, adr); + break; + case HALMAC_IO_DWORD: + val.dword = r32_indir_sdio_88xx(adapter, adr); + break; + default: + break; + } + + PLTFM_MUTEX_UNLOCK(&adapter->sdio_indir_mutex); + + return val.dword; +} + +/*only for w_indir_sdio_88xx !!, Soar 20171222*/ +static enum halmac_ret_status +w_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 adr, u32 val, + enum halmac_io_size size) +{ + u8 tmp, cnt = 50; + u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG; + u32 reg_data = REG_SDIO_INDIRECT_REG_DATA; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg); + if (status != HALMAC_RET_SUCCESS) + return status; + status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data); + if (status != HALMAC_RET_SUCCESS) + return status; + + PLTFM_SDIO_CMD52_W(reg_cfg, (u8)adr); + PLTFM_SDIO_CMD52_W(reg_cfg + 1, (u8)(adr >> 8)); + switch (size) { + case HALMAC_IO_BYTE: + PLTFM_SDIO_CMD52_W(reg_data, (u8)val); + PLTFM_SDIO_CMD52_W(reg_cfg + 2, (u8)(BIT(2) | BIT(4))); + break; + case HALMAC_IO_WORD: + PLTFM_SDIO_CMD52_W(reg_data, (u8)val); + PLTFM_SDIO_CMD52_W(reg_data + 1, (u8)(val >> 8)); + PLTFM_SDIO_CMD52_W(reg_cfg + 2, + (u8)(BIT(0) | BIT(2) | BIT(4))); + break; + case HALMAC_IO_DWORD: + PLTFM_SDIO_CMD52_W(reg_data, (u8)val); + PLTFM_SDIO_CMD52_W(reg_data + 1, (u8)(val >> 8)); + PLTFM_SDIO_CMD52_W(reg_data + 2, (u8)(val >> 16)); + PLTFM_SDIO_CMD52_W(reg_data + 3, (u8)(val >> 24)); + PLTFM_SDIO_CMD52_W(reg_cfg + 2, + (u8)(BIT(1) | BIT(2) | BIT(4))); + break; + default: + break; + } + + do { + tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2); + cnt--; + } while (((tmp & BIT(4)) == 0) && (cnt > 0)); + + if (((cnt & BIT(4)) == 0) && cnt == 0) + PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 write\n"); + + return status; +} + +/*only for w_indir_sdio_88xx !!, Soar 20171222*/ +static enum halmac_ret_status +w_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 adr, u32 val, + enum halmac_io_size size) +{ + u8 tmp, cnt = 50; + u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG; + u32 reg_data = REG_SDIO_INDIRECT_REG_DATA; + u32 value32 = 0; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg); + if (status != HALMAC_RET_SUCCESS) + return status; + status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data); + if (status != HALMAC_RET_SUCCESS) + return status; + + switch (size) { + case HALMAC_IO_BYTE: + value32 = adr | BIT(18) | BIT(20); + break; + case HALMAC_IO_WORD: + value32 = adr | BIT(16) | BIT(18) | BIT(20); + break; + case HALMAC_IO_DWORD: + value32 = adr | BIT(17) | BIT(18) | BIT(20); + break; + default: + return HALMAC_RET_FAIL; + } + + PLTFM_SDIO_CMD53_W32(reg_data, val); + PLTFM_SDIO_CMD53_W32(reg_cfg, value32); + + do { + tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2); + cnt--; + } while (((tmp & BIT(4)) == 0) && (cnt > 0)); + + if (((cnt & BIT(4)) == 0) && cnt == 0) + PLTFM_MSG_ERR("[ERR]sdio indirect CMD53 read\n"); + + return status; +} + +/*only for w_indir_sdio_88xx !!, Soar 20171222*/ +static enum halmac_ret_status +w8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (adapter->pwr_off_flow_flag == 1 || + adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) + status = w_indir_cmd52_88xx(adapter, adr, val, HALMAC_IO_BYTE); + else + status = w_indir_cmd53_88xx(adapter, adr, val, HALMAC_IO_BYTE); + return status; +} + +/*only for w_indir_sdio_88xx !!, Soar 20171222*/ +static enum halmac_ret_status +w16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) { + if (0 != (adr & (2 - 1))) { + status = w_indir_cmd52_88xx(adapter, adr, val, + HALMAC_IO_BYTE); + if (status != HALMAC_RET_SUCCESS) + return status; + status = w_indir_cmd52_88xx(adapter, adr + 1, val >> 8, + HALMAC_IO_BYTE); + } else { + status = w_indir_cmd52_88xx(adapter, adr, val, + HALMAC_IO_WORD); + } + } else { + if (0 != (adr & (2 - 1))) { + status = w_indir_cmd53_88xx(adapter, adr, val, + HALMAC_IO_BYTE); + if (status != HALMAC_RET_SUCCESS) + return status; + status = w_indir_cmd53_88xx(adapter, adr + 1, val >> 8, + HALMAC_IO_BYTE); + } else { + status = w_indir_cmd53_88xx(adapter, adr, val, + HALMAC_IO_WORD); + } + } + return status; +} + +/*only for w_indir_sdio_88xx !!, Soar 20171222*/ +static enum halmac_ret_status +w32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) { + if (0 != (adr & (4 - 1))) { + status = w_indir_cmd52_88xx(adapter, adr, val, + HALMAC_IO_BYTE); + if (status != HALMAC_RET_SUCCESS) + return status; + status = w_indir_cmd52_88xx(adapter, adr + 1, val >> 8, + HALMAC_IO_BYTE); + if (status != HALMAC_RET_SUCCESS) + return status; + status = w_indir_cmd52_88xx(adapter, adr + 2, val >> 16, + HALMAC_IO_BYTE); + if (status != HALMAC_RET_SUCCESS) + return status; + status = w_indir_cmd52_88xx(adapter, adr + 3, val >> 24, + HALMAC_IO_BYTE); + } else { + status = w_indir_cmd52_88xx(adapter, adr, val, + HALMAC_IO_DWORD); + } + } else { + if (0 != (adr & (4 - 1))) { + status = w_indir_cmd53_88xx(adapter, adr, val, + HALMAC_IO_BYTE); + if (status != HALMAC_RET_SUCCESS) + return status; + status = w_indir_cmd53_88xx(adapter, adr + 1, val >> 8, + HALMAC_IO_BYTE); + if (status != HALMAC_RET_SUCCESS) + return status; + status = w_indir_cmd53_88xx(adapter, adr + 2, val >> 16, + HALMAC_IO_BYTE); + if (status != HALMAC_RET_SUCCESS) + return status; + status = w_indir_cmd53_88xx(adapter, adr + 3, val >> 24, + HALMAC_IO_BYTE); + } else { + status = w_indir_cmd53_88xx(adapter, adr, val, + HALMAC_IO_DWORD); + } + } + return status; +} + +enum halmac_ret_status +w_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val, + enum halmac_io_size size) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MUTEX_LOCK(&adapter->sdio_indir_mutex); + + switch (size) { + case HALMAC_IO_BYTE: + status = w8_indir_sdio_88xx(adapter, adr, val); + break; + case HALMAC_IO_WORD: + status = w16_indir_sdio_88xx(adapter, adr, val); + break; + case HALMAC_IO_DWORD: + status = w32_indir_sdio_88xx(adapter, adr, val); + break; + default: + break; + } + + PLTFM_MUTEX_UNLOCK(&adapter->sdio_indir_mutex); + + return status; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_sdio_88xx.h b/hal/halmac/halmac_88xx/halmac_sdio_88xx.h new file mode 100644 index 0000000..0d89156 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_sdio_88xx.h @@ -0,0 +1,79 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_SDIO_88XX_H_ +#define _HALMAC_SDIO_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +init_sdio_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +deinit_sdio_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +cfg_sdio_rx_agg_88xx(struct halmac_adapter *adapter, + struct halmac_rxagg_cfg *cfg); + +enum halmac_ret_status +cfg_txagg_sdio_align_88xx(struct halmac_adapter *adapter, u8 enable, + u16 align_size); + +u32 +sdio_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +sdio_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + u8 *value); + +enum halmac_ret_status +set_sdio_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num); + +enum halmac_ret_status +get_sdio_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u8 *id); + +enum halmac_ret_status +sdio_cmd53_4byte_88xx(struct halmac_adapter *adapter, + enum halmac_sdio_cmd53_4byte_mode mode); + +enum halmac_ret_status +sdio_hw_info_88xx(struct halmac_adapter *adapter, + struct halmac_sdio_hw_info *info); + +void +cfg_sdio_tx_page_threshold_88xx(struct halmac_adapter *adapter, + struct halmac_tx_page_threshold_info *info); + +enum halmac_ret_status +cnv_to_sdio_bus_offset_88xx(struct halmac_adapter *adapter, u32 *offset); + +enum halmac_ret_status +leave_sdio_suspend_88xx(struct halmac_adapter *adapter); + +u32 +r_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, + enum halmac_io_size size); + +enum halmac_ret_status +w_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val, + enum halmac_io_size size); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_SDIO_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_usb_88xx.c b/hal/halmac/halmac_88xx/halmac_usb_88xx.c new file mode 100644 index 0000000..ca3003f --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_usb_88xx.c @@ -0,0 +1,533 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_usb_88xx.h" + +#if HALMAC_88XX_SUPPORT + +enum usb_burst_size { + USB_BURST_SIZE_3_0 = 0x0, + USB_BURST_SIZE_2_0_HS = 0x1, + USB_BURST_SIZE_2_0_FS = 0x2, + USB_BURST_SIZE_2_0_OTHERS = 0x3, + USB_BURST_SIZE_UNDEFINE = 0x7F, +}; + +/** + * init_usb_cfg_88xx() - init USB + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_usb_cfg_88xx(struct halmac_adapter *adapter) +{ + u8 value8 = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + value8 |= (BIT_DMA_MODE | (0x3 << BIT_SHIFT_BURST_CNT)); + + if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) { + /* usb3.0 */ + value8 |= (USB_BURST_SIZE_3_0 << BIT_SHIFT_BURST_SIZE); + } else { + if ((HALMAC_REG_R8(REG_USB_USBSTAT) & 0x3) == 0x1)/* usb2.0 */ + value8 |= USB_BURST_SIZE_2_0_HS << BIT_SHIFT_BURST_SIZE; + else /* usb1.1 */ + value8 |= USB_BURST_SIZE_2_0_FS << BIT_SHIFT_BURST_SIZE; + } + + HALMAC_REG_W8(REG_RXDMA_MODE, value8); + HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, + HALMAC_REG_R16(REG_TXDMA_OFFSET_CHK) | BIT_DROP_DATA_EN); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * deinit_usb_cfg_88xx() - deinit USB + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +deinit_usb_cfg_88xx(struct halmac_adapter *adapter) +{ + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_usb_rx_agg_88xx() - config rx aggregation + * @adapter : the adapter of halmac + * @halmac_rx_agg_mode + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_usb_rx_agg_88xx(struct halmac_adapter *adapter, + struct halmac_rxagg_cfg *cfg) +{ + u8 dma_usb_agg; + u8 size; + u8 timeout; + u8 agg_enable; + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + dma_usb_agg = HALMAC_REG_R8(REG_RXDMA_AGG_PG_TH + 3); + agg_enable = HALMAC_REG_R8(REG_TXDMA_PQ_MAP); + + switch (cfg->mode) { + case HALMAC_RX_AGG_MODE_NONE: + agg_enable &= ~BIT_RXDMA_AGG_EN; + break; + case HALMAC_RX_AGG_MODE_DMA: + agg_enable |= BIT_RXDMA_AGG_EN; + dma_usb_agg |= BIT(7); + break; + + case HALMAC_RX_AGG_MODE_USB: + agg_enable |= BIT_RXDMA_AGG_EN; + dma_usb_agg &= ~BIT(7); + break; + default: + PLTFM_MSG_ERR("[ERR]unsupported mode\n"); + agg_enable &= ~BIT_RXDMA_AGG_EN; + break; + } + + if (cfg->threshold.drv_define == _FALSE) { + if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) { + /* usb3.0 */ + size = 0x5; + timeout = 0xA; + } else { + /* usb2.0 */ + size = 0x5; + timeout = 0x20; + } + } else { + size = cfg->threshold.size; + timeout = cfg->threshold.timeout; + } + + value32 = HALMAC_REG_R32(REG_RXDMA_AGG_PG_TH); + if (cfg->threshold.size_limit_en == _FALSE) + HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 & ~BIT_EN_PRE_CALC); + else + HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 | BIT_EN_PRE_CALC); + + HALMAC_REG_W8(REG_TXDMA_PQ_MAP, agg_enable); + HALMAC_REG_W8(REG_RXDMA_AGG_PG_TH + 3, dma_usb_agg); + HALMAC_REG_W16(REG_RXDMA_AGG_PG_TH, + (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1))); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * reg_r8_usb_88xx() - read 1byte register + * @adapter : the adapter of halmac + * @offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u8 +reg_r8_usb_88xx(struct halmac_adapter *adapter, u32 offset) +{ + u8 value8; + + value8 = PLTFM_REG_R8(offset); + + return value8; +} + +/** + * reg_w8_usb_88xx() - write 1byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @value : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reg_w8_usb_88xx(struct halmac_adapter *adapter, u32 offset, u8 value) +{ + PLTFM_REG_W8(offset, value); + + return HALMAC_RET_SUCCESS; +} + +/** + * reg_r16_usb_88xx() - read 2byte register + * @adapter : the adapter of halmac + * @offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u16 +reg_r16_usb_88xx(struct halmac_adapter *adapter, u32 offset) +{ + u16 value16; + + value16 = PLTFM_REG_R16(offset); + + return value16; +} + +/** + * reg_w16_usb_88xx() - write 2byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @value : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reg_w16_usb_88xx(struct halmac_adapter *adapter, u32 offset, u16 value) +{ + PLTFM_REG_W16(offset, value); + + return HALMAC_RET_SUCCESS; +} + +/** + * reg_r32_usb_88xx() - read 4byte register + * @adapter : the adapter of halmac + * @offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u32 +reg_r32_usb_88xx(struct halmac_adapter *adapter, u32 offset) +{ + u32 value32; + + value32 = PLTFM_REG_R32(offset); + + return value32; +} + +/** + * reg_w32_usb_88xx() - write 4byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @value : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reg_w32_usb_88xx(struct halmac_adapter *adapter, u32 offset, u32 value) +{ + PLTFM_REG_W32(offset, value); + + return HALMAC_RET_SUCCESS; +} + +/** + * set_usb_bulkout_num_88xx() - inform bulk-out num + * @adapter : the adapter of halmac + * @bulkout_num : usb bulk-out number + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +set_usb_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num) +{ + adapter->bulkout_num = num; + + return HALMAC_RET_SUCCESS; +} + +/** + * get_usb_bulkout_id_88xx() - get bulk out id for the TX packet + * @adapter : the adapter of halmac + * @buf : tx packet, include txdesc + * @size : tx packet size + * @id : usb bulk-out id + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_usb_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u8 *id) +{ + enum halmac_qsel queue_sel; + enum halmac_dma_mapping dma_mapping; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!buf) { + PLTFM_MSG_ERR("[ERR]buf is NULL!!\n"); + return HALMAC_RET_DATA_BUF_NULL; + } + + if (size == 0) { + PLTFM_MSG_ERR("[ERR]size is 0!!\n"); + return HALMAC_RET_DATA_SIZE_INCORRECT; + } + + queue_sel = (enum halmac_qsel)GET_TX_DESC_QSEL(buf); + + switch (queue_sel) { + case HALMAC_QSEL_VO: + case HALMAC_QSEL_VO_V2: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO]; + break; + case HALMAC_QSEL_VI: + case HALMAC_QSEL_VI_V2: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI]; + break; + case HALMAC_QSEL_BE: + case HALMAC_QSEL_BE_V2: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE]; + break; + case HALMAC_QSEL_BK: + case HALMAC_QSEL_BK_V2: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK]; + break; + case HALMAC_QSEL_MGNT: + dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG]; + break; + case HALMAC_QSEL_HIGH: + case HALMAC_QSEL_BCN: + case HALMAC_QSEL_CMD: + dma_mapping = HALMAC_DMA_MAPPING_HIGH; + break; + default: + PLTFM_MSG_ERR("[ERR]Qsel is out of range\n"); + return HALMAC_RET_QSEL_INCORRECT; + } + + switch (dma_mapping) { + case HALMAC_DMA_MAPPING_HIGH: + *id = 0; + break; + case HALMAC_DMA_MAPPING_NORMAL: + *id = 1; + break; + case HALMAC_DMA_MAPPING_LOW: + *id = 2; + break; + case HALMAC_DMA_MAPPING_EXTRA: + *id = 3; + break; + default: + PLTFM_MSG_ERR("[ERR]out of range\n"); + return HALMAC_RET_DMA_MAP_INCORRECT; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_txagg_usb_align_88xx() -config sdio bus tx agg alignment + * @adapter : the adapter of halmac + * @enable : function enable(1)/disable(0) + * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11) + * Author : Soar Tu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_txagg_usb_align_88xx(struct halmac_adapter *adapter, u8 enable, + u16 align_size) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * tx_allowed_usb_88xx() - check tx status + * @adapter : the adapter of halmac + * @buf : tx packet, include txdesc + * @size : tx packet size, include txdesc + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +tx_allowed_usb_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * usb_indirect_reg_r32_88xx() - read MAC reg by SDIO reg + * @adapter : the adapter of halmac + * @offset : register offset + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u32 +usb_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset) +{ + return 0xFFFFFFFF; +} + +/** + * usb_reg_rn_88xx() - read n byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @size : register value size + * @value : register value + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +usb_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + u8 *value) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * get_usb_tx_addr_88xx() - get CMD53 addr for the TX packet + * @adapter : the adapter of halmac + * @buf : tx packet, include txdesc + * @size : tx packet size + * @pcmd53_addr : cmd53 addr value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_usb_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u32 *cmd53_addr) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +enum halmac_ret_status +set_usb_mode_88xx(struct halmac_adapter *adapter, enum halmac_usb_mode mode) +{ + u32 usb_tmp; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_usb_mode cur_mode; + + cur_mode = (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) ? + HALMAC_USB_MODE_U3 : HALMAC_USB_MODE_U2; + + /*check if HW supports usb2_usb3 switch*/ + usb_tmp = HALMAC_REG_R32(REG_PAD_CTRL2); + if (_FALSE == (BIT_GET_USB23_SW_MODE_V1(usb_tmp) | + (usb_tmp & BIT_USB3_USB2_TRANSITION))) { + PLTFM_MSG_ERR("[ERR]u2/u3 switch\n"); + return HALMAC_RET_USB2_3_SWITCH_UNSUPPORT; + } + + if (mode == cur_mode) { + PLTFM_MSG_ERR("[ERR]u2/u3 unchange\n"); + return HALMAC_RET_USB_MODE_UNCHANGE; + } + + /* Enable IO wrapper timeout */ + if (adapter->chip_id == HALMAC_CHIP_ID_8822B || + adapter->chip_id == HALMAC_CHIP_ID_8821C) + HALMAC_REG_W8_CLR(REG_SW_MDIO + 3, BIT(0)); + + usb_tmp &= ~(BIT_USB23_SW_MODE_V1(0x3)); + + if (mode == HALMAC_USB_MODE_U2) + HALMAC_REG_W32(REG_PAD_CTRL2, + usb_tmp | + BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U2) | + BIT_RSM_EN_V1); + else + HALMAC_REG_W32(REG_PAD_CTRL2, + usb_tmp | + BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U3) | + BIT_RSM_EN_V1); + + HALMAC_REG_W8(REG_PAD_CTRL2 + 1, 4); + HALMAC_REG_W16_SET(REG_SYS_PW_CTRL, BIT_APFM_OFFMAC); + PLTFM_DELAY_US(1000); + HALMAC_REG_W32_SET(REG_PAD_CTRL2, BIT_NO_PDN_CHIPOFF_V1); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +usbphy_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (speed == HAL_INTF_PHY_USB3) { + HALMAC_REG_W8(0xff0d, (u8)data); + HALMAC_REG_W8(0xff0e, (u8)(data >> 8)); + HALMAC_REG_W8(0xff0c, addr | BIT(7)); + } else if (speed == HAL_INTF_PHY_USB2) { + HALMAC_REG_W8(0xfe41, (u8)data); + HALMAC_REG_W8(0xfe40, addr); + HALMAC_REG_W8(0xfe42, 0x81); + } else { + PLTFM_MSG_ERR("[ERR]Error USB Speed !\n"); + return HALMAC_RET_NOT_SUPPORT; + } + + return HALMAC_RET_SUCCESS; +} + +u16 +usbphy_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u16 value = 0; + + if (speed == HAL_INTF_PHY_USB3) { + HALMAC_REG_W8(0xff0c, addr | BIT(6)); + value = (u16)(HALMAC_REG_R32(0xff0c) >> 8); + } else if (speed == HAL_INTF_PHY_USB2) { + if (addr >= 0xE0 && addr <= 0xFF) + addr -= 0x20; + if (addr >= 0xC0 && addr <= 0xDF) { + HALMAC_REG_W8(0xfe40, addr); + HALMAC_REG_W8(0xfe42, 0x81); + value = HALMAC_REG_R8(0xfe43); + } else { + PLTFM_MSG_ERR("[ERR]phy offset\n"); + return HALMAC_RET_NOT_SUPPORT; + } + } else { + PLTFM_MSG_ERR("[ERR]usb speed !\n"); + return HALMAC_RET_NOT_SUPPORT; + } + + return value; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_usb_88xx.h b/hal/halmac/halmac_88xx/halmac_usb_88xx.h new file mode 100644 index 0000000..64ae09a --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_usb_88xx.h @@ -0,0 +1,87 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_USB_88XX_H_ +#define _HALMAC_USB_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +init_usb_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +deinit_usb_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +cfg_usb_rx_agg_88xx(struct halmac_adapter *adapter, + struct halmac_rxagg_cfg *cfg); + +u8 +reg_r8_usb_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +reg_w8_usb_88xx(struct halmac_adapter *adapter, u32 offset, u8 value); + +u16 +reg_r16_usb_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +reg_w16_usb_88xx(struct halmac_adapter *adapter, u32 offset, u16 value); + +u32 +reg_r32_usb_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +reg_w32_usb_88xx(struct halmac_adapter *adapter, u32 offset, u32 value); + +enum halmac_ret_status +set_usb_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num); + +enum halmac_ret_status +get_usb_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u8 *id); + +enum halmac_ret_status +cfg_txagg_usb_align_88xx(struct halmac_adapter *adapter, u8 enable, + u16 align_size); + +enum halmac_ret_status +tx_allowed_usb_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +u32 +usb_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +usb_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + u8 *value); + +enum halmac_ret_status +get_usb_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u32 *cmd53_addr); + +enum halmac_ret_status +set_usb_mode_88xx(struct halmac_adapter *adapter, enum halmac_usb_mode mode); + +enum halmac_ret_status +usbphy_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed); + +u16 +usbphy_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_API_88XX_USB_H_ */ diff --git a/hal/halmac/halmac_bit_8822c.h b/hal/halmac/halmac_bit_8822c.h new file mode 100644 index 0000000..7666902 --- /dev/null +++ b/hal/halmac/halmac_bit_8822c.h @@ -0,0 +1,21816 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef __INC_HALMAC_BIT_8822C_H +#define __INC_HALMAC_BIT_8822C_H + +#define CPU_OPT_WIDTH 0x1F + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SYS_ISO_CTRL_8822C */ +#define BIT_PWC_EV12V_8822C BIT(15) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_PA33V_EN_8822C BIT(13) +#define BIT_PA12V_EN_8822C BIT(12) +#define BIT_UA33V_EN_8822C BIT(11) +#define BIT_UA12V_EN_8822C BIT(10) +#define BIT_ISO_RFDIO_8822C BIT(9) +#define BIT_ISO_EB2CORE_8822C BIT(8) +#define BIT_ISO_DIOE_8822C BIT(7) +#define BIT_ISO_WLPON2PP_8822C BIT(6) +#define BIT_ISO_IP2MAC_WA2PP_8822C BIT(5) +#define BIT_ISO_PD2CORE_8822C BIT(4) +#define BIT_ISO_PA2PCIE_8822C BIT(3) +#define BIT_ISO_UD2CORE_8822C BIT(2) +#define BIT_ISO_UA2USB_8822C BIT(1) +#define BIT_ISO_WD2PP_8822C BIT(0) + +/* 2 REG_SYS_FUNC_EN_8822C */ +#define BIT_FEN_MREGEN_8822C BIT(15) +#define BIT_FEN_HWPDN_8822C BIT(14) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_FEN_ELDR_8822C BIT(12) +#define BIT_FEN_DCORE_8822C BIT(11) +#define BIT_FEN_CPUEN_8822C BIT(10) +#define BIT_FEN_DIOE_8822C BIT(9) +#define BIT_FEN_PCIED_8822C BIT(8) +#define BIT_FEN_PPLL_8822C BIT(7) +#define BIT_FEN_PCIEA_8822C BIT(6) +#define BIT_FEN_DIO_PCIE_8822C BIT(5) +#define BIT_FEN_USBD_8822C BIT(4) +#define BIT_FEN_UPLL_8822C BIT(3) +#define BIT_FEN_USBA_8822C BIT(2) +#define BIT_FEN_BB_GLB_RSTN_8822C BIT(1) +#define BIT_FEN_BBRSTB_8822C BIT(0) + +/* 2 REG_SYS_PW_CTRL_8822C */ +#define BIT_SOP_EABM_8822C BIT(31) +#define BIT_SOP_ACKF_8822C BIT(30) +#define BIT_SOP_ERCK_8822C BIT(29) +#define BIT_SOP_ESWR_8822C BIT(28) +#define BIT_SOP_PWMM_8822C BIT(27) +#define BIT_SOP_EECK_8822C BIT(26) +#define BIT_SOP_ANA_CLK_DIVISION_2_8822C BIT(25) +#define BIT_SOP_EXTL_8822C BIT(24) +#define BIT_SYM_OP_RING_12M_8822C BIT(22) +#define BIT_ROP_SWPR_8822C BIT(21) +#define BIT_DIS_HW_LPLDM_8822C BIT(20) +#define BIT_OPT_SWRST_WLMCU_8822C BIT(19) +#define BIT_RDY_SYSPWR_8822C BIT(17) +#define BIT_EN_WLON_8822C BIT(16) +#define BIT_APDM_HPDN_8822C BIT(15) +#define BIT_AFSM_PCIE_SUS_EN_8822C BIT(12) +#define BIT_AFSM_WLSUS_EN_8822C BIT(11) +#define BIT_APFM_SWLPS_8822C BIT(10) +#define BIT_APFM_OFFMAC_8822C BIT(9) +#define BIT_APFN_ONMAC_8822C BIT(8) +#define BIT_CHIP_PDN_EN_8822C BIT(7) +#define BIT_RDY_MACDIS_8822C BIT(6) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_PFM_WOWL_8822C BIT(3) +#define BIT_PFM_LDKP_8822C BIT(2) +#define BIT_WL_HCI_ALD_8822C BIT(1) +#define BIT_PFM_LDALL_8822C BIT(0) + +/* 2 REG_SYS_CLK_CTRL_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_CPU_CLK_EN_8822C BIT(14) +#define BIT_SYMREG_CLK_EN_8822C BIT(13) +#define BIT_HCI_CLK_EN_8822C BIT(12) +#define BIT_MAC_CLK_EN_8822C BIT(11) +#define BIT_SEC_CLK_EN_8822C BIT(10) +#define BIT_PHY_SSC_RSTB_8822C BIT(9) +#define BIT_EXT_32K_EN_8822C BIT(8) +#define BIT_WL_CLK_TEST_8822C BIT(7) +#define BIT_OP_SPS_PWM_EN_8822C BIT(6) +#define BIT_LOADER_CLK_EN_8822C BIT(5) +#define BIT_MACSLP_8822C BIT(4) +#define BIT_WAKEPAD_EN_8822C BIT(3) +#define BIT_ROMD16V_EN_8822C BIT(2) +#define BIT_ANA_CLK_DIVISION_2_8822C BIT(1) +#define BIT_CNTD16V_EN_8822C BIT(0) + +/* 2 REG_SYS_EEPROM_CTRL_8822C */ + +#define BIT_SHIFT_VPDIDX_8822C 8 +#define BIT_MASK_VPDIDX_8822C 0xff +#define BIT_VPDIDX_8822C(x) \ + (((x) & BIT_MASK_VPDIDX_8822C) << BIT_SHIFT_VPDIDX_8822C) +#define BITS_VPDIDX_8822C (BIT_MASK_VPDIDX_8822C << BIT_SHIFT_VPDIDX_8822C) +#define BIT_CLEAR_VPDIDX_8822C(x) ((x) & (~BITS_VPDIDX_8822C)) +#define BIT_GET_VPDIDX_8822C(x) \ + (((x) >> BIT_SHIFT_VPDIDX_8822C) & BIT_MASK_VPDIDX_8822C) +#define BIT_SET_VPDIDX_8822C(x, v) \ + (BIT_CLEAR_VPDIDX_8822C(x) | BIT_VPDIDX_8822C(v)) + +#define BIT_SHIFT_EEM1_0_8822C 6 +#define BIT_MASK_EEM1_0_8822C 0x3 +#define BIT_EEM1_0_8822C(x) \ + (((x) & BIT_MASK_EEM1_0_8822C) << BIT_SHIFT_EEM1_0_8822C) +#define BITS_EEM1_0_8822C (BIT_MASK_EEM1_0_8822C << BIT_SHIFT_EEM1_0_8822C) +#define BIT_CLEAR_EEM1_0_8822C(x) ((x) & (~BITS_EEM1_0_8822C)) +#define BIT_GET_EEM1_0_8822C(x) \ + (((x) >> BIT_SHIFT_EEM1_0_8822C) & BIT_MASK_EEM1_0_8822C) +#define BIT_SET_EEM1_0_8822C(x, v) \ + (BIT_CLEAR_EEM1_0_8822C(x) | BIT_EEM1_0_8822C(v)) + +#define BIT_AUTOLOAD_SUS_8822C BIT(5) +#define BIT_EERPOMSEL_8822C BIT(4) +#define BIT_EECS_V1_8822C BIT(3) +#define BIT_EESK_V1_8822C BIT(2) +#define BIT_EEDI_V1_8822C BIT(1) +#define BIT_EEDO_V1_8822C BIT(0) + +/* 2 REG_EE_VPD_8822C */ + +#define BIT_SHIFT_VPD_DATA_8822C 0 +#define BIT_MASK_VPD_DATA_8822C 0xffffffffL +#define BIT_VPD_DATA_8822C(x) \ + (((x) & BIT_MASK_VPD_DATA_8822C) << BIT_SHIFT_VPD_DATA_8822C) +#define BITS_VPD_DATA_8822C \ + (BIT_MASK_VPD_DATA_8822C << BIT_SHIFT_VPD_DATA_8822C) +#define BIT_CLEAR_VPD_DATA_8822C(x) ((x) & (~BITS_VPD_DATA_8822C)) +#define BIT_GET_VPD_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_VPD_DATA_8822C) & BIT_MASK_VPD_DATA_8822C) +#define BIT_SET_VPD_DATA_8822C(x, v) \ + (BIT_CLEAR_VPD_DATA_8822C(x) | BIT_VPD_DATA_8822C(v)) + +/* 2 REG_SYS_SWR_CTRL1_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_HW_AUTO_CTRL_EXT_SWR_8822C BIT(9) +#define BIT_USE_INTERNAL_SWR_AND_LDO_8822C BIT(8) +#define BIT_MAC_ID_EN_8822C BIT(7) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SYS_SWR_CTRL2_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_SW18_SEL_8822C BIT(13) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_SW18_SD_8822C BIT(10) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SYS_SWR_CTRL3_8822C */ +#define BIT_SPS18_OCP_DIS_8822C BIT(31) + +#define BIT_SHIFT_SPS18_OCP_TH_8822C 16 +#define BIT_MASK_SPS18_OCP_TH_8822C 0x7fff +#define BIT_SPS18_OCP_TH_8822C(x) \ + (((x) & BIT_MASK_SPS18_OCP_TH_8822C) << BIT_SHIFT_SPS18_OCP_TH_8822C) +#define BITS_SPS18_OCP_TH_8822C \ + (BIT_MASK_SPS18_OCP_TH_8822C << BIT_SHIFT_SPS18_OCP_TH_8822C) +#define BIT_CLEAR_SPS18_OCP_TH_8822C(x) ((x) & (~BITS_SPS18_OCP_TH_8822C)) +#define BIT_GET_SPS18_OCP_TH_8822C(x) \ + (((x) >> BIT_SHIFT_SPS18_OCP_TH_8822C) & BIT_MASK_SPS18_OCP_TH_8822C) +#define BIT_SET_SPS18_OCP_TH_8822C(x, v) \ + (BIT_CLEAR_SPS18_OCP_TH_8822C(x) | BIT_SPS18_OCP_TH_8822C(v)) + +#define BIT_SHIFT_OCP_WINDOW_8822C 0 +#define BIT_MASK_OCP_WINDOW_8822C 0xffff +#define BIT_OCP_WINDOW_8822C(x) \ + (((x) & BIT_MASK_OCP_WINDOW_8822C) << BIT_SHIFT_OCP_WINDOW_8822C) +#define BITS_OCP_WINDOW_8822C \ + (BIT_MASK_OCP_WINDOW_8822C << BIT_SHIFT_OCP_WINDOW_8822C) +#define BIT_CLEAR_OCP_WINDOW_8822C(x) ((x) & (~BITS_OCP_WINDOW_8822C)) +#define BIT_GET_OCP_WINDOW_8822C(x) \ + (((x) >> BIT_SHIFT_OCP_WINDOW_8822C) & BIT_MASK_OCP_WINDOW_8822C) +#define BIT_SET_OCP_WINDOW_8822C(x, v) \ + (BIT_CLEAR_OCP_WINDOW_8822C(x) | BIT_OCP_WINDOW_8822C(v)) + +/* 2 REG_RSV_CTRL_8822C */ +#define BIT_HREG_DBG_8822C BIT(23) +#define BIT_WLMCUIOIF_8822C BIT(8) +#define BIT_LOCK_ALL_EN_8822C BIT(7) +#define BIT_R_DIS_PRST_8822C BIT(6) +#define BIT_WLOCK_1C_B6_8822C BIT(5) +#define BIT_WLOCK_40_8822C BIT(4) +#define BIT_WLOCK_08_8822C BIT(3) +#define BIT_WLOCK_04_8822C BIT(2) +#define BIT_WLOCK_00_8822C BIT(1) +#define BIT_WLOCK_ALL_8822C BIT(0) + +/* 2 REG_RF_CTRL_8822C */ +#define BIT_RF_SDMRSTB_8822C BIT(2) +#define BIT_RF_RSTB_8822C BIT(1) +#define BIT_RF_EN_8822C BIT(0) + +/* 2 REG_AFE_LDO_CTRL_8822C */ +#define BIT_R_SYM_WLBBOFF1_P4_EN_8822C BIT(9) +#define BIT_R_SYM_WLBBOFF1_P3_EN_8822C BIT(8) +#define BIT_R_SYM_WLBBOFF1_P2_EN_8822C BIT(7) +#define BIT_R_SYM_WLBBOFF1_P1_EN_8822C BIT(6) +#define BIT_R_SYM_WLBBOFF_P4_EN_8822C BIT(4) +#define BIT_R_SYM_WLBBOFF_P3_EN_8822C BIT(3) +#define BIT_R_SYM_WLBBOFF_P2_EN_8822C BIT(2) +#define BIT_R_SYM_WLBBOFF_P1_EN_8822C BIT(1) +#define BIT_R_SYM_WLBBOFF_EN_8822C BIT(0) + +/* 2 REG_AFE_CTRL1_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_MAC_CLK_SEL_8822C 20 +#define BIT_MASK_MAC_CLK_SEL_8822C 0x3 +#define BIT_MAC_CLK_SEL_8822C(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL_8822C) << BIT_SHIFT_MAC_CLK_SEL_8822C) +#define BITS_MAC_CLK_SEL_8822C \ + (BIT_MASK_MAC_CLK_SEL_8822C << BIT_SHIFT_MAC_CLK_SEL_8822C) +#define BIT_CLEAR_MAC_CLK_SEL_8822C(x) ((x) & (~BITS_MAC_CLK_SEL_8822C)) +#define BIT_GET_MAC_CLK_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL_8822C) & BIT_MASK_MAC_CLK_SEL_8822C) +#define BIT_SET_MAC_CLK_SEL_8822C(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL_8822C(x) | BIT_MAC_CLK_SEL_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ANAPARSW_POW_MAC_8822C */ +#define BIT_POW_LDO15_8822C BIT(2) +#define BIT_POW_SW_8822C BIT(1) +#define BIT_POW_LDO14_8822C BIT(0) + +/* 2 REG_ANAPARLDO_POW_MAC_8822C */ +#define BIT_LDOE25_POW_L_8822C BIT(0) + +/* 2 REG_ANAPAR_POW_MAC_8822C */ +#define BIT_DUMMY_V4_8822C BIT(7) +#define BIT_DUMMY_V3_8822C BIT(6) +#define BIT_DUMMY_V2_8822C BIT(5) +#define BIT_DUMMY_V1_8822C BIT(4) +#define BIT_POW_PC_LDO_PORT1_8822C BIT(3) +#define BIT_POW_PC_LDO_PORT0_8822C BIT(2) +#define BIT_POW_PLL_V1_8822C BIT(1) +#define BIT_POW_POWER_CUT_POW_LDO_8822C BIT(0) + +/* 2 REG_ANAPAR_POW_XTAL_8822C */ +#define BIT_POW_XTAL_8822C BIT(1) +#define BIT_POW_BG_8822C BIT(0) + +/* 2 REG_ANAPARLDO_MAC_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_REG_STANDBY_L_8822C BIT(19) +#define BIT_PD_REGU_L_8822C BIT(18) +#define BIT_EN_PC_BT_L_8822C BIT(17) + +#define BIT_SHIFT_REG_LDOADJ_L_8822C 13 +#define BIT_MASK_REG_LDOADJ_L_8822C 0xf +#define BIT_REG_LDOADJ_L_8822C(x) \ + (((x) & BIT_MASK_REG_LDOADJ_L_8822C) << BIT_SHIFT_REG_LDOADJ_L_8822C) +#define BITS_REG_LDOADJ_L_8822C \ + (BIT_MASK_REG_LDOADJ_L_8822C << BIT_SHIFT_REG_LDOADJ_L_8822C) +#define BIT_CLEAR_REG_LDOADJ_L_8822C(x) ((x) & (~BITS_REG_LDOADJ_L_8822C)) +#define BIT_GET_REG_LDOADJ_L_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LDOADJ_L_8822C) & BIT_MASK_REG_LDOADJ_L_8822C) +#define BIT_SET_REG_LDOADJ_L_8822C(x, v) \ + (BIT_CLEAR_REG_LDOADJ_L_8822C(x) | BIT_REG_LDOADJ_L_8822C(v)) + +#define BIT_CK12M_EN_8822C BIT(11) +#define BIT_CK12M_SEL_8822C BIT(10) +#define BIT_EN_25_L_8822C BIT(9) +#define BIT_EN_SLEEP_8822C BIT(8) + +#define BIT_SHIFT_LDOH12_V12ADJ_L_8822C 4 +#define BIT_MASK_LDOH12_V12ADJ_L_8822C 0xf +#define BIT_LDOH12_V12ADJ_L_8822C(x) \ + (((x) & BIT_MASK_LDOH12_V12ADJ_L_8822C) \ + << BIT_SHIFT_LDOH12_V12ADJ_L_8822C) +#define BITS_LDOH12_V12ADJ_L_8822C \ + (BIT_MASK_LDOH12_V12ADJ_L_8822C << BIT_SHIFT_LDOH12_V12ADJ_L_8822C) +#define BIT_CLEAR_LDOH12_V12ADJ_L_8822C(x) ((x) & (~BITS_LDOH12_V12ADJ_L_8822C)) +#define BIT_GET_LDOH12_V12ADJ_L_8822C(x) \ + (((x) >> BIT_SHIFT_LDOH12_V12ADJ_L_8822C) & \ + BIT_MASK_LDOH12_V12ADJ_L_8822C) +#define BIT_SET_LDOH12_V12ADJ_L_8822C(x, v) \ + (BIT_CLEAR_LDOH12_V12ADJ_L_8822C(x) | BIT_LDOH12_V12ADJ_L_8822C(v)) + +#define BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C 0 +#define BIT_MASK_LDOE25_V12ADJ_L_V1_8822C 0xf +#define BIT_LDOE25_V12ADJ_L_V1_8822C(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L_V1_8822C) \ + << BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C) +#define BITS_LDOE25_V12ADJ_L_V1_8822C \ + (BIT_MASK_LDOE25_V12ADJ_L_V1_8822C \ + << BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C) +#define BIT_CLEAR_LDOE25_V12ADJ_L_V1_8822C(x) \ + ((x) & (~BITS_LDOE25_V12ADJ_L_V1_8822C)) +#define BIT_GET_LDOE25_V12ADJ_L_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C) & \ + BIT_MASK_LDOE25_V12ADJ_L_V1_8822C) +#define BIT_SET_LDOE25_V12ADJ_L_V1_8822C(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L_V1_8822C(x) | \ + BIT_LDOE25_V12ADJ_L_V1_8822C(v)) + +/* 2 REG_EFUSE_CTRL_8822C */ +#define BIT_EF_FLAG_8822C BIT(31) + +#define BIT_SHIFT_EF_PGPD_8822C 28 +#define BIT_MASK_EF_PGPD_8822C 0x7 +#define BIT_EF_PGPD_8822C(x) \ + (((x) & BIT_MASK_EF_PGPD_8822C) << BIT_SHIFT_EF_PGPD_8822C) +#define BITS_EF_PGPD_8822C (BIT_MASK_EF_PGPD_8822C << BIT_SHIFT_EF_PGPD_8822C) +#define BIT_CLEAR_EF_PGPD_8822C(x) ((x) & (~BITS_EF_PGPD_8822C)) +#define BIT_GET_EF_PGPD_8822C(x) \ + (((x) >> BIT_SHIFT_EF_PGPD_8822C) & BIT_MASK_EF_PGPD_8822C) +#define BIT_SET_EF_PGPD_8822C(x, v) \ + (BIT_CLEAR_EF_PGPD_8822C(x) | BIT_EF_PGPD_8822C(v)) + +#define BIT_SHIFT_EF_RDT_8822C 24 +#define BIT_MASK_EF_RDT_8822C 0xf +#define BIT_EF_RDT_8822C(x) \ + (((x) & BIT_MASK_EF_RDT_8822C) << BIT_SHIFT_EF_RDT_8822C) +#define BITS_EF_RDT_8822C (BIT_MASK_EF_RDT_8822C << BIT_SHIFT_EF_RDT_8822C) +#define BIT_CLEAR_EF_RDT_8822C(x) ((x) & (~BITS_EF_RDT_8822C)) +#define BIT_GET_EF_RDT_8822C(x) \ + (((x) >> BIT_SHIFT_EF_RDT_8822C) & BIT_MASK_EF_RDT_8822C) +#define BIT_SET_EF_RDT_8822C(x, v) \ + (BIT_CLEAR_EF_RDT_8822C(x) | BIT_EF_RDT_8822C(v)) + +#define BIT_SHIFT_EF_PGTS_8822C 20 +#define BIT_MASK_EF_PGTS_8822C 0xf +#define BIT_EF_PGTS_8822C(x) \ + (((x) & BIT_MASK_EF_PGTS_8822C) << BIT_SHIFT_EF_PGTS_8822C) +#define BITS_EF_PGTS_8822C (BIT_MASK_EF_PGTS_8822C << BIT_SHIFT_EF_PGTS_8822C) +#define BIT_CLEAR_EF_PGTS_8822C(x) ((x) & (~BITS_EF_PGTS_8822C)) +#define BIT_GET_EF_PGTS_8822C(x) \ + (((x) >> BIT_SHIFT_EF_PGTS_8822C) & BIT_MASK_EF_PGTS_8822C) +#define BIT_SET_EF_PGTS_8822C(x, v) \ + (BIT_CLEAR_EF_PGTS_8822C(x) | BIT_EF_PGTS_8822C(v)) + +#define BIT_EF_PDWN_8822C BIT(19) +#define BIT_EF_ALDEN_8822C BIT(18) + +#define BIT_SHIFT_EF_ADDR_8822C 8 +#define BIT_MASK_EF_ADDR_8822C 0x3ff +#define BIT_EF_ADDR_8822C(x) \ + (((x) & BIT_MASK_EF_ADDR_8822C) << BIT_SHIFT_EF_ADDR_8822C) +#define BITS_EF_ADDR_8822C (BIT_MASK_EF_ADDR_8822C << BIT_SHIFT_EF_ADDR_8822C) +#define BIT_CLEAR_EF_ADDR_8822C(x) ((x) & (~BITS_EF_ADDR_8822C)) +#define BIT_GET_EF_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_EF_ADDR_8822C) & BIT_MASK_EF_ADDR_8822C) +#define BIT_SET_EF_ADDR_8822C(x, v) \ + (BIT_CLEAR_EF_ADDR_8822C(x) | BIT_EF_ADDR_8822C(v)) + +#define BIT_SHIFT_EF_DATA_8822C 0 +#define BIT_MASK_EF_DATA_8822C 0xff +#define BIT_EF_DATA_8822C(x) \ + (((x) & BIT_MASK_EF_DATA_8822C) << BIT_SHIFT_EF_DATA_8822C) +#define BITS_EF_DATA_8822C (BIT_MASK_EF_DATA_8822C << BIT_SHIFT_EF_DATA_8822C) +#define BIT_CLEAR_EF_DATA_8822C(x) ((x) & (~BITS_EF_DATA_8822C)) +#define BIT_GET_EF_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_EF_DATA_8822C) & BIT_MASK_EF_DATA_8822C) +#define BIT_SET_EF_DATA_8822C(x, v) \ + (BIT_CLEAR_EF_DATA_8822C(x) | BIT_EF_DATA_8822C(v)) + +/* 2 REG_LDO_EFUSE_CTRL_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_EF_CRES_SEL_8822C BIT(26) + +#define BIT_SHIFT_EF_SCAN_START_V1_8822C 16 +#define BIT_MASK_EF_SCAN_START_V1_8822C 0x3ff +#define BIT_EF_SCAN_START_V1_8822C(x) \ + (((x) & BIT_MASK_EF_SCAN_START_V1_8822C) \ + << BIT_SHIFT_EF_SCAN_START_V1_8822C) +#define BITS_EF_SCAN_START_V1_8822C \ + (BIT_MASK_EF_SCAN_START_V1_8822C << BIT_SHIFT_EF_SCAN_START_V1_8822C) +#define BIT_CLEAR_EF_SCAN_START_V1_8822C(x) \ + ((x) & (~BITS_EF_SCAN_START_V1_8822C)) +#define BIT_GET_EF_SCAN_START_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822C) & \ + BIT_MASK_EF_SCAN_START_V1_8822C) +#define BIT_SET_EF_SCAN_START_V1_8822C(x, v) \ + (BIT_CLEAR_EF_SCAN_START_V1_8822C(x) | BIT_EF_SCAN_START_V1_8822C(v)) + +#define BIT_SHIFT_EF_SCAN_END_8822C 12 +#define BIT_MASK_EF_SCAN_END_8822C 0xf +#define BIT_EF_SCAN_END_8822C(x) \ + (((x) & BIT_MASK_EF_SCAN_END_8822C) << BIT_SHIFT_EF_SCAN_END_8822C) +#define BITS_EF_SCAN_END_8822C \ + (BIT_MASK_EF_SCAN_END_8822C << BIT_SHIFT_EF_SCAN_END_8822C) +#define BIT_CLEAR_EF_SCAN_END_8822C(x) ((x) & (~BITS_EF_SCAN_END_8822C)) +#define BIT_GET_EF_SCAN_END_8822C(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_END_8822C) & BIT_MASK_EF_SCAN_END_8822C) +#define BIT_SET_EF_SCAN_END_8822C(x, v) \ + (BIT_CLEAR_EF_SCAN_END_8822C(x) | BIT_EF_SCAN_END_8822C(v)) + +#define BIT_EF_PD_DIS_8822C BIT(11) + +#define BIT_SHIFT_EF_CELL_SEL_8822C 8 +#define BIT_MASK_EF_CELL_SEL_8822C 0x3 +#define BIT_EF_CELL_SEL_8822C(x) \ + (((x) & BIT_MASK_EF_CELL_SEL_8822C) << BIT_SHIFT_EF_CELL_SEL_8822C) +#define BITS_EF_CELL_SEL_8822C \ + (BIT_MASK_EF_CELL_SEL_8822C << BIT_SHIFT_EF_CELL_SEL_8822C) +#define BIT_CLEAR_EF_CELL_SEL_8822C(x) ((x) & (~BITS_EF_CELL_SEL_8822C)) +#define BIT_GET_EF_CELL_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_EF_CELL_SEL_8822C) & BIT_MASK_EF_CELL_SEL_8822C) +#define BIT_SET_EF_CELL_SEL_8822C(x, v) \ + (BIT_CLEAR_EF_CELL_SEL_8822C(x) | BIT_EF_CELL_SEL_8822C(v)) + +#define BIT_EF_TRPT_8822C BIT(7) + +#define BIT_SHIFT_EF_TTHD_8822C 0 +#define BIT_MASK_EF_TTHD_8822C 0x7f +#define BIT_EF_TTHD_8822C(x) \ + (((x) & BIT_MASK_EF_TTHD_8822C) << BIT_SHIFT_EF_TTHD_8822C) +#define BITS_EF_TTHD_8822C (BIT_MASK_EF_TTHD_8822C << BIT_SHIFT_EF_TTHD_8822C) +#define BIT_CLEAR_EF_TTHD_8822C(x) ((x) & (~BITS_EF_TTHD_8822C)) +#define BIT_GET_EF_TTHD_8822C(x) \ + (((x) >> BIT_SHIFT_EF_TTHD_8822C) & BIT_MASK_EF_TTHD_8822C) +#define BIT_SET_EF_TTHD_8822C(x, v) \ + (BIT_CLEAR_EF_TTHD_8822C(x) | BIT_EF_TTHD_8822C(v)) + +/* 2 REG_PWR_OPTION_CTRL_8822C */ + +#define BIT_SHIFT_DBG_SEL_V1_8822C 16 +#define BIT_MASK_DBG_SEL_V1_8822C 0xff +#define BIT_DBG_SEL_V1_8822C(x) \ + (((x) & BIT_MASK_DBG_SEL_V1_8822C) << BIT_SHIFT_DBG_SEL_V1_8822C) +#define BITS_DBG_SEL_V1_8822C \ + (BIT_MASK_DBG_SEL_V1_8822C << BIT_SHIFT_DBG_SEL_V1_8822C) +#define BIT_CLEAR_DBG_SEL_V1_8822C(x) ((x) & (~BITS_DBG_SEL_V1_8822C)) +#define BIT_GET_DBG_SEL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_V1_8822C) & BIT_MASK_DBG_SEL_V1_8822C) +#define BIT_SET_DBG_SEL_V1_8822C(x, v) \ + (BIT_CLEAR_DBG_SEL_V1_8822C(x) | BIT_DBG_SEL_V1_8822C(v)) + +#define BIT_SHIFT_DBG_SEL_BYTE_8822C 14 +#define BIT_MASK_DBG_SEL_BYTE_8822C 0x3 +#define BIT_DBG_SEL_BYTE_8822C(x) \ + (((x) & BIT_MASK_DBG_SEL_BYTE_8822C) << BIT_SHIFT_DBG_SEL_BYTE_8822C) +#define BITS_DBG_SEL_BYTE_8822C \ + (BIT_MASK_DBG_SEL_BYTE_8822C << BIT_SHIFT_DBG_SEL_BYTE_8822C) +#define BIT_CLEAR_DBG_SEL_BYTE_8822C(x) ((x) & (~BITS_DBG_SEL_BYTE_8822C)) +#define BIT_GET_DBG_SEL_BYTE_8822C(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822C) & BIT_MASK_DBG_SEL_BYTE_8822C) +#define BIT_SET_DBG_SEL_BYTE_8822C(x, v) \ + (BIT_CLEAR_DBG_SEL_BYTE_8822C(x) | BIT_DBG_SEL_BYTE_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_SYSON_DBG_PAD_E2_8822C BIT(11) +#define BIT_SYSON_LED_PAD_E2_8822C BIT(10) +#define BIT_SYSON_GPEE_PAD_E2_8822C BIT(9) +#define BIT_SYSON_PCI_PAD_E2_8822C BIT(8) +#define BIT_AUTO_SW_LDO_VOL_EN_8822C BIT(7) + +#define BIT_SHIFT_SYSON_SPS0WWV_WT_8822C 4 +#define BIT_MASK_SYSON_SPS0WWV_WT_8822C 0x3 +#define BIT_SYSON_SPS0WWV_WT_8822C(x) \ + (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822C) \ + << BIT_SHIFT_SYSON_SPS0WWV_WT_8822C) +#define BITS_SYSON_SPS0WWV_WT_8822C \ + (BIT_MASK_SYSON_SPS0WWV_WT_8822C << BIT_SHIFT_SYSON_SPS0WWV_WT_8822C) +#define BIT_CLEAR_SYSON_SPS0WWV_WT_8822C(x) \ + ((x) & (~BITS_SYSON_SPS0WWV_WT_8822C)) +#define BIT_GET_SYSON_SPS0WWV_WT_8822C(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822C) & \ + BIT_MASK_SYSON_SPS0WWV_WT_8822C) +#define BIT_SET_SYSON_SPS0WWV_WT_8822C(x, v) \ + (BIT_CLEAR_SYSON_SPS0WWV_WT_8822C(x) | BIT_SYSON_SPS0WWV_WT_8822C(v)) + +#define BIT_SHIFT_SYSON_SPS0LDO_WT_8822C 2 +#define BIT_MASK_SYSON_SPS0LDO_WT_8822C 0x3 +#define BIT_SYSON_SPS0LDO_WT_8822C(x) \ + (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822C) \ + << BIT_SHIFT_SYSON_SPS0LDO_WT_8822C) +#define BITS_SYSON_SPS0LDO_WT_8822C \ + (BIT_MASK_SYSON_SPS0LDO_WT_8822C << BIT_SHIFT_SYSON_SPS0LDO_WT_8822C) +#define BIT_CLEAR_SYSON_SPS0LDO_WT_8822C(x) \ + ((x) & (~BITS_SYSON_SPS0LDO_WT_8822C)) +#define BIT_GET_SYSON_SPS0LDO_WT_8822C(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822C) & \ + BIT_MASK_SYSON_SPS0LDO_WT_8822C) +#define BIT_SET_SYSON_SPS0LDO_WT_8822C(x, v) \ + (BIT_CLEAR_SYSON_SPS0LDO_WT_8822C(x) | BIT_SYSON_SPS0LDO_WT_8822C(v)) + +#define BIT_SHIFT_SYSON_RCLK_SCALE_8822C 0 +#define BIT_MASK_SYSON_RCLK_SCALE_8822C 0x3 +#define BIT_SYSON_RCLK_SCALE_8822C(x) \ + (((x) & BIT_MASK_SYSON_RCLK_SCALE_8822C) \ + << BIT_SHIFT_SYSON_RCLK_SCALE_8822C) +#define BITS_SYSON_RCLK_SCALE_8822C \ + (BIT_MASK_SYSON_RCLK_SCALE_8822C << BIT_SHIFT_SYSON_RCLK_SCALE_8822C) +#define BIT_CLEAR_SYSON_RCLK_SCALE_8822C(x) \ + ((x) & (~BITS_SYSON_RCLK_SCALE_8822C)) +#define BIT_GET_SYSON_RCLK_SCALE_8822C(x) \ + (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822C) & \ + BIT_MASK_SYSON_RCLK_SCALE_8822C) +#define BIT_SET_SYSON_RCLK_SCALE_8822C(x, v) \ + (BIT_CLEAR_SYSON_RCLK_SCALE_8822C(x) | BIT_SYSON_RCLK_SCALE_8822C(v)) + +/* 2 REG_CAL_TIMER_8822C */ + +#define BIT_SHIFT_MATCH_CNT_8822C 8 +#define BIT_MASK_MATCH_CNT_8822C 0xff +#define BIT_MATCH_CNT_8822C(x) \ + (((x) & BIT_MASK_MATCH_CNT_8822C) << BIT_SHIFT_MATCH_CNT_8822C) +#define BITS_MATCH_CNT_8822C \ + (BIT_MASK_MATCH_CNT_8822C << BIT_SHIFT_MATCH_CNT_8822C) +#define BIT_CLEAR_MATCH_CNT_8822C(x) ((x) & (~BITS_MATCH_CNT_8822C)) +#define BIT_GET_MATCH_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8822C) & BIT_MASK_MATCH_CNT_8822C) +#define BIT_SET_MATCH_CNT_8822C(x, v) \ + (BIT_CLEAR_MATCH_CNT_8822C(x) | BIT_MATCH_CNT_8822C(v)) + +#define BIT_SHIFT_CAL_SCAL_8822C 0 +#define BIT_MASK_CAL_SCAL_8822C 0xff +#define BIT_CAL_SCAL_8822C(x) \ + (((x) & BIT_MASK_CAL_SCAL_8822C) << BIT_SHIFT_CAL_SCAL_8822C) +#define BITS_CAL_SCAL_8822C \ + (BIT_MASK_CAL_SCAL_8822C << BIT_SHIFT_CAL_SCAL_8822C) +#define BIT_CLEAR_CAL_SCAL_8822C(x) ((x) & (~BITS_CAL_SCAL_8822C)) +#define BIT_GET_CAL_SCAL_8822C(x) \ + (((x) >> BIT_SHIFT_CAL_SCAL_8822C) & BIT_MASK_CAL_SCAL_8822C) +#define BIT_SET_CAL_SCAL_8822C(x, v) \ + (BIT_CLEAR_CAL_SCAL_8822C(x) | BIT_CAL_SCAL_8822C(v)) + +/* 2 REG_ACLK_MON_8822C */ + +#define BIT_SHIFT_RCLK_MON_8822C 5 +#define BIT_MASK_RCLK_MON_8822C 0x7ff +#define BIT_RCLK_MON_8822C(x) \ + (((x) & BIT_MASK_RCLK_MON_8822C) << BIT_SHIFT_RCLK_MON_8822C) +#define BITS_RCLK_MON_8822C \ + (BIT_MASK_RCLK_MON_8822C << BIT_SHIFT_RCLK_MON_8822C) +#define BIT_CLEAR_RCLK_MON_8822C(x) ((x) & (~BITS_RCLK_MON_8822C)) +#define BIT_GET_RCLK_MON_8822C(x) \ + (((x) >> BIT_SHIFT_RCLK_MON_8822C) & BIT_MASK_RCLK_MON_8822C) +#define BIT_SET_RCLK_MON_8822C(x, v) \ + (BIT_CLEAR_RCLK_MON_8822C(x) | BIT_RCLK_MON_8822C(v)) + +#define BIT_CAL_EN_8822C BIT(4) + +#define BIT_SHIFT_DPSTU_8822C 2 +#define BIT_MASK_DPSTU_8822C 0x3 +#define BIT_DPSTU_8822C(x) \ + (((x) & BIT_MASK_DPSTU_8822C) << BIT_SHIFT_DPSTU_8822C) +#define BITS_DPSTU_8822C (BIT_MASK_DPSTU_8822C << BIT_SHIFT_DPSTU_8822C) +#define BIT_CLEAR_DPSTU_8822C(x) ((x) & (~BITS_DPSTU_8822C)) +#define BIT_GET_DPSTU_8822C(x) \ + (((x) >> BIT_SHIFT_DPSTU_8822C) & BIT_MASK_DPSTU_8822C) +#define BIT_SET_DPSTU_8822C(x, v) \ + (BIT_CLEAR_DPSTU_8822C(x) | BIT_DPSTU_8822C(v)) + +#define BIT_SUS_16X_8822C BIT(1) + +/* 2 REG_GPIO_MUXCFG_2_8822C */ +#define BIT_SOUT_GPIO8_8822C BIT(7) +#define BIT_SOUT_GPIO5_8822C BIT(6) +#define BIT_RFE_CTRL_5_GPIO14_V1_8822C BIT(5) +#define BIT_RFE_CTRL_10_GPIO13_V1_8822C BIT(4) +#define BIT_RFE_CTRL_11_GPIO4_V1_8822C BIT(3) +#define BIT_RFE_CTRL_5_GPIO14_8822C BIT(2) +#define BIT_RFE_CTRL_10_GPIO13_8822C BIT(1) +#define BIT_RFE_CTRL_11_GPIO4_8822C BIT(0) + +/* 2 REG_GPIO_MUXCFG_8822C */ +#define BIT_RFE_CTRL_3_GPIO12_8822C BIT(31) +#define BIT_BT_RFE_CTRL_5_GPIO12_8822C BIT(30) +#define BIT_S0_TRSW_GPIO12_8822C BIT(29) +#define BIT_RFE_CTRL_9_GPIO13_8822C BIT(28) +#define BIT_RFE_CTRL_9_GPIO12_8822C BIT(27) +#define BIT_RFE_CTRL_8_GPIO4_8822C BIT(26) +#define BIT_BT_RFE_CTRL_1_GPIO13_8822C BIT(25) +#define BIT_BT_RFE_CTRL_1_GPIO12_8822C BIT(24) +#define BIT_BT_RFE_CTRL_0_GPIO4_8822C BIT(23) +#define BIT_ANTSW_GPIO13_8822C BIT(22) +#define BIT_ANTSW_GPIO12_8822C BIT(21) +#define BIT_ANTSWB_GPIO4_8822C BIT(20) +#define BIT_FSPI_EN_8822C BIT(19) +#define BIT_WL_RTS_EXT_32K_SEL_8822C BIT(18) +#define BIT_WLBT_DPDT_SEL_EN_8822C BIT(17) +#define BIT_WLBT_LNAON_SEL_EN_8822C BIT(16) +#define BIT_SIC_LBK_8822C BIT(15) +#define BIT_ENHTP_8822C BIT(14) +#define BIT_BT_AOD_GPIO3_8822C BIT(13) +#define BIT_ENSIC_8822C BIT(12) +#define BIT_SIC_SWRST_8822C BIT(11) +#define BIT_PO_WIFI_PTA_PINS_8822C BIT(10) +#define BIT_PO_BT_PTA_PINS_8822C BIT(9) +#define BIT_ENUART_8822C BIT(8) + +#define BIT_SHIFT_BTMODE_8822C 6 +#define BIT_MASK_BTMODE_8822C 0x3 +#define BIT_BTMODE_8822C(x) \ + (((x) & BIT_MASK_BTMODE_8822C) << BIT_SHIFT_BTMODE_8822C) +#define BITS_BTMODE_8822C (BIT_MASK_BTMODE_8822C << BIT_SHIFT_BTMODE_8822C) +#define BIT_CLEAR_BTMODE_8822C(x) ((x) & (~BITS_BTMODE_8822C)) +#define BIT_GET_BTMODE_8822C(x) \ + (((x) >> BIT_SHIFT_BTMODE_8822C) & BIT_MASK_BTMODE_8822C) +#define BIT_SET_BTMODE_8822C(x, v) \ + (BIT_CLEAR_BTMODE_8822C(x) | BIT_BTMODE_8822C(v)) + +#define BIT_ENBT_8822C BIT(5) +#define BIT_EROM_EN_8822C BIT(4) +#define BIT_WLRFE_6_7_EN_8822C BIT(3) +#define BIT_WLRFE_4_5_EN_8822C BIT(2) + +#define BIT_SHIFT_GPIOSEL_8822C 0 +#define BIT_MASK_GPIOSEL_8822C 0x3 +#define BIT_GPIOSEL_8822C(x) \ + (((x) & BIT_MASK_GPIOSEL_8822C) << BIT_SHIFT_GPIOSEL_8822C) +#define BITS_GPIOSEL_8822C (BIT_MASK_GPIOSEL_8822C << BIT_SHIFT_GPIOSEL_8822C) +#define BIT_CLEAR_GPIOSEL_8822C(x) ((x) & (~BITS_GPIOSEL_8822C)) +#define BIT_GET_GPIOSEL_8822C(x) \ + (((x) >> BIT_SHIFT_GPIOSEL_8822C) & BIT_MASK_GPIOSEL_8822C) +#define BIT_SET_GPIOSEL_8822C(x, v) \ + (BIT_CLEAR_GPIOSEL_8822C(x) | BIT_GPIOSEL_8822C(v)) + +/* 2 REG_GPIO_PIN_CTRL_8822C */ + +#define BIT_SHIFT_GPIO_MOD_7_TO_0_8822C 24 +#define BIT_MASK_GPIO_MOD_7_TO_0_8822C 0xff +#define BIT_GPIO_MOD_7_TO_0_8822C(x) \ + (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822C) \ + << BIT_SHIFT_GPIO_MOD_7_TO_0_8822C) +#define BITS_GPIO_MOD_7_TO_0_8822C \ + (BIT_MASK_GPIO_MOD_7_TO_0_8822C << BIT_SHIFT_GPIO_MOD_7_TO_0_8822C) +#define BIT_CLEAR_GPIO_MOD_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8822C)) +#define BIT_GET_GPIO_MOD_7_TO_0_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822C) & \ + BIT_MASK_GPIO_MOD_7_TO_0_8822C) +#define BIT_SET_GPIO_MOD_7_TO_0_8822C(x, v) \ + (BIT_CLEAR_GPIO_MOD_7_TO_0_8822C(x) | BIT_GPIO_MOD_7_TO_0_8822C(v)) + +#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C 16 +#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C 0xff +#define BIT_GPIO_IO_SEL_7_TO_0_8822C(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C) \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C) +#define BITS_GPIO_IO_SEL_7_TO_0_8822C \ + (BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822C(x) \ + ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8822C)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C) & \ + BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C) +#define BIT_SET_GPIO_IO_SEL_7_TO_0_8822C(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822C(x) | \ + BIT_GPIO_IO_SEL_7_TO_0_8822C(v)) + +#define BIT_SHIFT_GPIO_OUT_7_TO_0_8822C 8 +#define BIT_MASK_GPIO_OUT_7_TO_0_8822C 0xff +#define BIT_GPIO_OUT_7_TO_0_8822C(x) \ + (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822C) \ + << BIT_SHIFT_GPIO_OUT_7_TO_0_8822C) +#define BITS_GPIO_OUT_7_TO_0_8822C \ + (BIT_MASK_GPIO_OUT_7_TO_0_8822C << BIT_SHIFT_GPIO_OUT_7_TO_0_8822C) +#define BIT_CLEAR_GPIO_OUT_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8822C)) +#define BIT_GET_GPIO_OUT_7_TO_0_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822C) & \ + BIT_MASK_GPIO_OUT_7_TO_0_8822C) +#define BIT_SET_GPIO_OUT_7_TO_0_8822C(x, v) \ + (BIT_CLEAR_GPIO_OUT_7_TO_0_8822C(x) | BIT_GPIO_OUT_7_TO_0_8822C(v)) + +#define BIT_SHIFT_GPIO_IN_7_TO_0_8822C 0 +#define BIT_MASK_GPIO_IN_7_TO_0_8822C 0xff +#define BIT_GPIO_IN_7_TO_0_8822C(x) \ + (((x) & BIT_MASK_GPIO_IN_7_TO_0_8822C) \ + << BIT_SHIFT_GPIO_IN_7_TO_0_8822C) +#define BITS_GPIO_IN_7_TO_0_8822C \ + (BIT_MASK_GPIO_IN_7_TO_0_8822C << BIT_SHIFT_GPIO_IN_7_TO_0_8822C) +#define BIT_CLEAR_GPIO_IN_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8822C)) +#define BIT_GET_GPIO_IN_7_TO_0_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822C) & \ + BIT_MASK_GPIO_IN_7_TO_0_8822C) +#define BIT_SET_GPIO_IN_7_TO_0_8822C(x, v) \ + (BIT_CLEAR_GPIO_IN_7_TO_0_8822C(x) | BIT_GPIO_IN_7_TO_0_8822C(v)) + +/* 2 REG_GPIO_INTM_8822C */ + +#define BIT_SHIFT_MUXDBG_SEL_8822C 30 +#define BIT_MASK_MUXDBG_SEL_8822C 0x3 +#define BIT_MUXDBG_SEL_8822C(x) \ + (((x) & BIT_MASK_MUXDBG_SEL_8822C) << BIT_SHIFT_MUXDBG_SEL_8822C) +#define BITS_MUXDBG_SEL_8822C \ + (BIT_MASK_MUXDBG_SEL_8822C << BIT_SHIFT_MUXDBG_SEL_8822C) +#define BIT_CLEAR_MUXDBG_SEL_8822C(x) ((x) & (~BITS_MUXDBG_SEL_8822C)) +#define BIT_GET_MUXDBG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL_8822C) & BIT_MASK_MUXDBG_SEL_8822C) +#define BIT_SET_MUXDBG_SEL_8822C(x, v) \ + (BIT_CLEAR_MUXDBG_SEL_8822C(x) | BIT_MUXDBG_SEL_8822C(v)) + +#define BIT_EXTWOL_SEL_8822C BIT(17) +#define BIT_EXTWOL_EN_8822C BIT(16) +#define BIT_GPIOF_INT_MD_8822C BIT(15) +#define BIT_GPIOE_INT_MD_8822C BIT(14) +#define BIT_GPIOD_INT_MD_8822C BIT(13) +#define BIT_GPIOF_INT_MD_8822C BIT(15) +#define BIT_GPIOE_INT_MD_8822C BIT(14) +#define BIT_GPIOD_INT_MD_8822C BIT(13) +#define BIT_GPIOC_INT_MD_8822C BIT(12) +#define BIT_GPIOB_INT_MD_8822C BIT(11) +#define BIT_GPIOA_INT_MD_8822C BIT(10) +#define BIT_GPIO9_INT_MD_8822C BIT(9) +#define BIT_GPIO8_INT_MD_8822C BIT(8) +#define BIT_GPIO7_INT_MD_8822C BIT(7) +#define BIT_GPIO6_INT_MD_8822C BIT(6) +#define BIT_GPIO5_INT_MD_8822C BIT(5) +#define BIT_GPIO4_INT_MD_8822C BIT(4) +#define BIT_GPIO3_INT_MD_8822C BIT(3) +#define BIT_GPIO2_INT_MD_8822C BIT(2) +#define BIT_GPIO1_INT_MD_8822C BIT(1) +#define BIT_GPIO0_INT_MD_8822C BIT(0) + +/* 2 REG_LED_CFG_8822C */ +#define BIT_MAILBOX_1WIRE_GPIO_CFG_8822C BIT(31) +#define BIT_BT_RF_GPIO_CFG_8822C BIT(30) +#define BIT_BT_SDIO_INT_GPIO_CFG_8822C BIT(29) +#define BIT_MAILBOX_3WIRE_GPIO_CFG_8822C BIT(28) +#define BIT_WLBT_PAPE_SEL_EN_8822C BIT(27) +#define BIT_LNAON_SEL_EN_8822C BIT(26) +#define BIT_PAPE_SEL_EN_8822C BIT(25) +#define BIT_DPDT_WLBT_SEL_8822C BIT(24) +#define BIT_DPDT_SEL_EN_8822C BIT(23) +#define BIT_GPIO13_14_WL_CTRL_EN_8822C BIT(22) +#define BIT_LED2DIS_8822C BIT(21) +#define BIT_LED2PL_8822C BIT(20) +#define BIT_LED2SV_8822C BIT(19) + +#define BIT_SHIFT_LED2CM_8822C 16 +#define BIT_MASK_LED2CM_8822C 0x7 +#define BIT_LED2CM_8822C(x) \ + (((x) & BIT_MASK_LED2CM_8822C) << BIT_SHIFT_LED2CM_8822C) +#define BITS_LED2CM_8822C (BIT_MASK_LED2CM_8822C << BIT_SHIFT_LED2CM_8822C) +#define BIT_CLEAR_LED2CM_8822C(x) ((x) & (~BITS_LED2CM_8822C)) +#define BIT_GET_LED2CM_8822C(x) \ + (((x) >> BIT_SHIFT_LED2CM_8822C) & BIT_MASK_LED2CM_8822C) +#define BIT_SET_LED2CM_8822C(x, v) \ + (BIT_CLEAR_LED2CM_8822C(x) | BIT_LED2CM_8822C(v)) + +#define BIT_LED1DIS_8822C BIT(15) +#define BIT_LED1PL_8822C BIT(12) +#define BIT_LED1SV_8822C BIT(11) + +#define BIT_SHIFT_LED1CM_8822C 8 +#define BIT_MASK_LED1CM_8822C 0x7 +#define BIT_LED1CM_8822C(x) \ + (((x) & BIT_MASK_LED1CM_8822C) << BIT_SHIFT_LED1CM_8822C) +#define BITS_LED1CM_8822C (BIT_MASK_LED1CM_8822C << BIT_SHIFT_LED1CM_8822C) +#define BIT_CLEAR_LED1CM_8822C(x) ((x) & (~BITS_LED1CM_8822C)) +#define BIT_GET_LED1CM_8822C(x) \ + (((x) >> BIT_SHIFT_LED1CM_8822C) & BIT_MASK_LED1CM_8822C) +#define BIT_SET_LED1CM_8822C(x, v) \ + (BIT_CLEAR_LED1CM_8822C(x) | BIT_LED1CM_8822C(v)) + +#define BIT_LED0DIS_8822C BIT(7) + +#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C 5 +#define BIT_MASK_AFE_LDO_SWR_CHECK_8822C 0x3 +#define BIT_AFE_LDO_SWR_CHECK_8822C(x) \ + (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822C) \ + << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C) +#define BITS_AFE_LDO_SWR_CHECK_8822C \ + (BIT_MASK_AFE_LDO_SWR_CHECK_8822C << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8822C(x) \ + ((x) & (~BITS_AFE_LDO_SWR_CHECK_8822C)) +#define BIT_GET_AFE_LDO_SWR_CHECK_8822C(x) \ + (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C) & \ + BIT_MASK_AFE_LDO_SWR_CHECK_8822C) +#define BIT_SET_AFE_LDO_SWR_CHECK_8822C(x, v) \ + (BIT_CLEAR_AFE_LDO_SWR_CHECK_8822C(x) | BIT_AFE_LDO_SWR_CHECK_8822C(v)) + +#define BIT_LED0PL_8822C BIT(4) +#define BIT_LED0SV_8822C BIT(3) + +#define BIT_SHIFT_LED0CM_8822C 0 +#define BIT_MASK_LED0CM_8822C 0x7 +#define BIT_LED0CM_8822C(x) \ + (((x) & BIT_MASK_LED0CM_8822C) << BIT_SHIFT_LED0CM_8822C) +#define BITS_LED0CM_8822C (BIT_MASK_LED0CM_8822C << BIT_SHIFT_LED0CM_8822C) +#define BIT_CLEAR_LED0CM_8822C(x) ((x) & (~BITS_LED0CM_8822C)) +#define BIT_GET_LED0CM_8822C(x) \ + (((x) >> BIT_SHIFT_LED0CM_8822C) & BIT_MASK_LED0CM_8822C) +#define BIT_SET_LED0CM_8822C(x, v) \ + (BIT_CLEAR_LED0CM_8822C(x) | BIT_LED0CM_8822C(v)) + +/* 2 REG_FSIMR_8822C */ +#define BIT_FS_PDNINT_EN_8822C BIT(31) +#define BIT_FS_SPS_OCP_INT_EN_8822C BIT(29) +#define BIT_FS_PWMERR_INT_EN_8822C BIT(28) +#define BIT_FS_GPIOF_INT_EN_8822C BIT(27) +#define BIT_FS_GPIOE_INT_EN_8822C BIT(26) +#define BIT_FS_GPIOD_INT_EN_8822C BIT(25) +#define BIT_FS_GPIOC_INT_EN_8822C BIT(24) +#define BIT_FS_GPIOB_INT_EN_8822C BIT(23) +#define BIT_FS_GPIOA_INT_EN_8822C BIT(22) +#define BIT_FS_GPIO9_INT_EN_8822C BIT(21) +#define BIT_FS_GPIO8_INT_EN_8822C BIT(20) +#define BIT_FS_GPIO7_INT_EN_8822C BIT(19) +#define BIT_FS_GPIO6_INT_EN_8822C BIT(18) +#define BIT_FS_GPIO5_INT_EN_8822C BIT(17) +#define BIT_FS_GPIO4_INT_EN_8822C BIT(16) +#define BIT_FS_GPIO3_INT_EN_8822C BIT(15) +#define BIT_FS_GPIO2_INT_EN_8822C BIT(14) +#define BIT_FS_GPIO1_INT_EN_8822C BIT(13) +#define BIT_FS_GPIO0_INT_EN_8822C BIT(12) +#define BIT_FS_HCI_SUS_EN_8822C BIT(11) +#define BIT_FS_HCI_RES_EN_8822C BIT(10) +#define BIT_FS_HCI_RESET_EN_8822C BIT(9) +#define BIT_USB_SCSI_CMD_EN_8822C BIT(8) +#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8822C BIT(7) +#define BIT_ACT2RECOVERY_INT_EN_V1_8822C BIT(6) +#define BIT_GEN1GEN2_SWITCH_8822C BIT(5) +#define BIT_HCI_TXDMA_REQ_HIMR_8822C BIT(4) +#define BIT_FS_32K_LEAVE_SETTING_MAK_8822C BIT(3) +#define BIT_FS_32K_ENTER_SETTING_MAK_8822C BIT(2) +#define BIT_FS_USB_LPMRSM_MSK_8822C BIT(1) +#define BIT_FS_USB_LPMINT_MSK_8822C BIT(0) + +/* 2 REG_FSISR_8822C */ +#define BIT_FS_PDNINT_8822C BIT(31) +#define BIT_FS_SPS_OCP_INT_8822C BIT(29) +#define BIT_FS_PWMERR_INT_8822C BIT(28) +#define BIT_FS_GPIOF_INT_8822C BIT(27) +#define BIT_FS_GPIOE_INT_8822C BIT(26) +#define BIT_FS_GPIOD_INT_8822C BIT(25) +#define BIT_FS_GPIOC_INT_8822C BIT(24) +#define BIT_FS_GPIOB_INT_8822C BIT(23) +#define BIT_FS_GPIOA_INT_8822C BIT(22) +#define BIT_FS_GPIO9_INT_8822C BIT(21) +#define BIT_FS_GPIO8_INT_8822C BIT(20) +#define BIT_FS_GPIO7_INT_8822C BIT(19) +#define BIT_FS_GPIO6_INT_8822C BIT(18) +#define BIT_FS_GPIO5_INT_8822C BIT(17) +#define BIT_FS_GPIO4_INT_8822C BIT(16) +#define BIT_FS_GPIO3_INT_8822C BIT(15) +#define BIT_FS_GPIO2_INT_8822C BIT(14) +#define BIT_FS_GPIO1_INT_8822C BIT(13) +#define BIT_FS_GPIO0_INT_8822C BIT(12) +#define BIT_FS_HCI_SUS_INT_8822C BIT(11) +#define BIT_FS_HCI_RES_INT_8822C BIT(10) +#define BIT_FS_HCI_RESET_INT_8822C BIT(9) +#define BIT_USB_SCSI_CMD_INT_8822C BIT(8) +#define BIT_ACT2RECOVERY_8822C BIT(6) +#define BIT_GEN1GEN2_SWITCH_8822C BIT(5) +#define BIT_HCI_TXDMA_REQ_HISR_8822C BIT(4) +#define BIT_FS_32K_LEAVE_SETTING_INT_8822C BIT(3) +#define BIT_FS_32K_ENTER_SETTING_INT_8822C BIT(2) +#define BIT_FS_USB_LPMRSM_INT_8822C BIT(1) +#define BIT_FS_USB_LPMINT_INT_8822C BIT(0) + +/* 2 REG_HSIMR_8822C */ +#define BIT_GPIOF_INT_EN_8822C BIT(31) +#define BIT_GPIOE_INT_EN_8822C BIT(30) +#define BIT_GPIOD_INT_EN_8822C BIT(29) +#define BIT_GPIOC_INT_EN_8822C BIT(28) +#define BIT_GPIOB_INT_EN_8822C BIT(27) +#define BIT_GPIOA_INT_EN_8822C BIT(26) +#define BIT_GPIO9_INT_EN_8822C BIT(25) +#define BIT_GPIO8_INT_EN_8822C BIT(24) +#define BIT_GPIO7_INT_EN_8822C BIT(23) +#define BIT_GPIO6_INT_EN_8822C BIT(22) +#define BIT_GPIO5_INT_EN_8822C BIT(21) +#define BIT_GPIO4_INT_EN_8822C BIT(20) +#define BIT_GPIO3_INT_EN_8822C BIT(19) +#define BIT_GPIO2_INT_EN_V1_8822C BIT(18) +#define BIT_GPIO1_INT_EN_8822C BIT(17) +#define BIT_GPIO0_INT_EN_8822C BIT(16) +#define BIT_PDNINT_EN_8822C BIT(7) +#define BIT_RON_INT_EN_8822C BIT(6) +#define BIT_SPS_OCP_INT_EN_8822C BIT(5) +#define BIT_GPIO15_0_INT_EN_8822C BIT(0) + +/* 2 REG_HSISR_8822C */ +#define BIT_GPIOF_INT_8822C BIT(31) +#define BIT_GPIOE_INT_8822C BIT(30) +#define BIT_GPIOD_INT_8822C BIT(29) +#define BIT_GPIOC_INT_8822C BIT(28) +#define BIT_GPIOB_INT_8822C BIT(27) +#define BIT_GPIOA_INT_8822C BIT(26) +#define BIT_GPIO9_INT_8822C BIT(25) +#define BIT_GPIO8_INT_8822C BIT(24) +#define BIT_GPIO7_INT_8822C BIT(23) +#define BIT_GPIO6_INT_8822C BIT(22) +#define BIT_GPIO5_INT_8822C BIT(21) +#define BIT_GPIO4_INT_8822C BIT(20) +#define BIT_GPIO3_INT_8822C BIT(19) +#define BIT_GPIO2_INT_V1_8822C BIT(18) +#define BIT_GPIO1_INT_8822C BIT(17) +#define BIT_GPIO0_INT_8822C BIT(16) +#define BIT_PDNINT_8822C BIT(7) +#define BIT_RON_INT_8822C BIT(6) +#define BIT_SPS_OCP_INT_8822C BIT(5) +#define BIT_GPIO15_0_INT_8822C BIT(0) + +/* 2 REG_GPIO_EXT_CTRL_8822C */ + +#define BIT_SHIFT_GPIO_MOD_15_TO_8_8822C 24 +#define BIT_MASK_GPIO_MOD_15_TO_8_8822C 0xff +#define BIT_GPIO_MOD_15_TO_8_8822C(x) \ + (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822C) \ + << BIT_SHIFT_GPIO_MOD_15_TO_8_8822C) +#define BITS_GPIO_MOD_15_TO_8_8822C \ + (BIT_MASK_GPIO_MOD_15_TO_8_8822C << BIT_SHIFT_GPIO_MOD_15_TO_8_8822C) +#define BIT_CLEAR_GPIO_MOD_15_TO_8_8822C(x) \ + ((x) & (~BITS_GPIO_MOD_15_TO_8_8822C)) +#define BIT_GET_GPIO_MOD_15_TO_8_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822C) & \ + BIT_MASK_GPIO_MOD_15_TO_8_8822C) +#define BIT_SET_GPIO_MOD_15_TO_8_8822C(x, v) \ + (BIT_CLEAR_GPIO_MOD_15_TO_8_8822C(x) | BIT_GPIO_MOD_15_TO_8_8822C(v)) + +#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C 16 +#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C 0xff +#define BIT_GPIO_IO_SEL_15_TO_8_8822C(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C) \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C) +#define BITS_GPIO_IO_SEL_15_TO_8_8822C \ + (BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822C(x) \ + ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8822C)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C) & \ + BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C) +#define BIT_SET_GPIO_IO_SEL_15_TO_8_8822C(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822C(x) | \ + BIT_GPIO_IO_SEL_15_TO_8_8822C(v)) + +#define BIT_SHIFT_GPIO_OUT_15_TO_8_8822C 8 +#define BIT_MASK_GPIO_OUT_15_TO_8_8822C 0xff +#define BIT_GPIO_OUT_15_TO_8_8822C(x) \ + (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822C) \ + << BIT_SHIFT_GPIO_OUT_15_TO_8_8822C) +#define BITS_GPIO_OUT_15_TO_8_8822C \ + (BIT_MASK_GPIO_OUT_15_TO_8_8822C << BIT_SHIFT_GPIO_OUT_15_TO_8_8822C) +#define BIT_CLEAR_GPIO_OUT_15_TO_8_8822C(x) \ + ((x) & (~BITS_GPIO_OUT_15_TO_8_8822C)) +#define BIT_GET_GPIO_OUT_15_TO_8_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822C) & \ + BIT_MASK_GPIO_OUT_15_TO_8_8822C) +#define BIT_SET_GPIO_OUT_15_TO_8_8822C(x, v) \ + (BIT_CLEAR_GPIO_OUT_15_TO_8_8822C(x) | BIT_GPIO_OUT_15_TO_8_8822C(v)) + +#define BIT_SHIFT_GPIO_IN_15_TO_8_8822C 0 +#define BIT_MASK_GPIO_IN_15_TO_8_8822C 0xff +#define BIT_GPIO_IN_15_TO_8_8822C(x) \ + (((x) & BIT_MASK_GPIO_IN_15_TO_8_8822C) \ + << BIT_SHIFT_GPIO_IN_15_TO_8_8822C) +#define BITS_GPIO_IN_15_TO_8_8822C \ + (BIT_MASK_GPIO_IN_15_TO_8_8822C << BIT_SHIFT_GPIO_IN_15_TO_8_8822C) +#define BIT_CLEAR_GPIO_IN_15_TO_8_8822C(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8822C)) +#define BIT_GET_GPIO_IN_15_TO_8_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822C) & \ + BIT_MASK_GPIO_IN_15_TO_8_8822C) +#define BIT_SET_GPIO_IN_15_TO_8_8822C(x, v) \ + (BIT_CLEAR_GPIO_IN_15_TO_8_8822C(x) | BIT_GPIO_IN_15_TO_8_8822C(v)) + +/* 2 REG_PAD_CTRL1_8822C */ +#define BIT_PAPE_WLBT_SEL_8822C BIT(29) +#define BIT_LNAON_WLBT_SEL_8822C BIT(28) +#define BIT_BT_BQB_GPIO_SEL_8822C BIT(27) +#define BIT_BTGP_GPG3_FEN_8822C BIT(26) +#define BIT_BTGP_GPG2_FEN_8822C BIT(25) +#define BIT_BTGP_JTAG_EN_8822C BIT(24) +#define BIT_XTAL_CLK_EXTARNAL_EN_8822C BIT(23) +#define BIT_BTGP_UART0_EN_8822C BIT(22) +#define BIT_BTGP_UART1_EN_8822C BIT(21) +#define BIT_BTGP_SPI_EN_8822C BIT(20) +#define BIT_BTGP_GPIO_E2_8822C BIT(19) +#define BIT_BTGP_GPIO_EN_8822C BIT(18) + +#define BIT_SHIFT_BTGP_GPIO_SL_8822C 16 +#define BIT_MASK_BTGP_GPIO_SL_8822C 0x3 +#define BIT_BTGP_GPIO_SL_8822C(x) \ + (((x) & BIT_MASK_BTGP_GPIO_SL_8822C) << BIT_SHIFT_BTGP_GPIO_SL_8822C) +#define BITS_BTGP_GPIO_SL_8822C \ + (BIT_MASK_BTGP_GPIO_SL_8822C << BIT_SHIFT_BTGP_GPIO_SL_8822C) +#define BIT_CLEAR_BTGP_GPIO_SL_8822C(x) ((x) & (~BITS_BTGP_GPIO_SL_8822C)) +#define BIT_GET_BTGP_GPIO_SL_8822C(x) \ + (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822C) & BIT_MASK_BTGP_GPIO_SL_8822C) +#define BIT_SET_BTGP_GPIO_SL_8822C(x, v) \ + (BIT_CLEAR_BTGP_GPIO_SL_8822C(x) | BIT_BTGP_GPIO_SL_8822C(v)) + +#define BIT_PAD_SDIO_SR_8822C BIT(14) +#define BIT_GPIO14_OUTPUT_PL_8822C BIT(13) +#define BIT_HOST_WAKE_PAD_PULL_EN_8822C BIT(12) +#define BIT_HOST_WAKE_PAD_SL_8822C BIT(11) +#define BIT_PAD_LNAON_SR_8822C BIT(10) +#define BIT_PAD_LNAON_E2_8822C BIT(9) +#define BIT_SW_LNAON_G_SEL_DATA_8822C BIT(8) +#define BIT_SW_LNAON_A_SEL_DATA_8822C BIT(7) +#define BIT_PAD_PAPE_SR_8822C BIT(6) +#define BIT_PAD_PAPE_E2_8822C BIT(5) +#define BIT_SW_PAPE_G_SEL_DATA_8822C BIT(4) +#define BIT_SW_PAPE_A_SEL_DATA_8822C BIT(3) +#define BIT_PAD_DPDT_SR_8822C BIT(2) +#define BIT_PAD_DPDT_PAD_E2_8822C BIT(1) +#define BIT_SW_DPDT_SEL_DATA_8822C BIT(0) + +/* 2 REG_WL_BT_PWR_CTRL_8822C */ +#define BIT_ISO_BD2PP_8822C BIT(31) +#define BIT_LDOV12B_EN_8822C BIT(30) +#define BIT_CKEN_BTGPS_8822C BIT(29) +#define BIT_FEN_BTGPS_8822C BIT(28) +#define BIT_BTCPU_BOOTSEL_8822C BIT(27) +#define BIT_SPI_SPEEDUP_8822C BIT(26) +#define BIT_BT_LDO_MODE_8822C BIT(25) +#define BIT_DEVWAKE_PAD_TYPE_SEL_8822C BIT(24) +#define BIT_CLKREQ_PAD_TYPE_SEL_8822C BIT(23) +#define BIT_ISO_BTPON2PP_8822C BIT(22) +#define BIT_BT_HWROF_EN_8822C BIT(19) +#define BIT_BT_FUNC_EN_8822C BIT(18) +#define BIT_BT_HWPDN_SL_8822C BIT(17) +#define BIT_BT_DISN_EN_8822C BIT(16) +#define BIT_BT_PDN_PULL_EN_8822C BIT(15) +#define BIT_WL_PDN_PULL_EN_8822C BIT(14) +#define BIT_EXTERNAL_REQUEST_PL_8822C BIT(13) +#define BIT_GPIO0_2_3_PULL_LOW_EN_8822C BIT(12) +#define BIT_ISO_BA2PP_8822C BIT(11) +#define BIT_BT_AFE_LDO_EN_8822C BIT(10) +#define BIT_BT_AFE_PLL_EN_8822C BIT(9) +#define BIT_BT_DIG_CLK_EN_8822C BIT(8) +#define BIT_WLAN_32K_SEL_8822C BIT(6) +#define BIT_WL_DRV_EXIST_IDX_8822C BIT(5) +#define BIT_DOP_EHPAD_8822C BIT(4) +#define BIT_WL_HWROF_EN_8822C BIT(3) +#define BIT_WL_FUNC_EN_8822C BIT(2) +#define BIT_WL_HWPDN_SL_8822C BIT(1) +#define BIT_WL_HWPDN_EN_8822C BIT(0) + +/* 2 REG_SDM_DEBUG_8822C */ +#define BIT_GPIO_IE_V18_8822C BIT(10) +#define BIT_PCIE_IE_V18_8822C BIT(9) +#define BIT_UART_IE_V18_8822C BIT(8) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_WLCLK_PHASE_8822C 0 +#define BIT_MASK_WLCLK_PHASE_8822C 0x1f +#define BIT_WLCLK_PHASE_8822C(x) \ + (((x) & BIT_MASK_WLCLK_PHASE_8822C) << BIT_SHIFT_WLCLK_PHASE_8822C) +#define BITS_WLCLK_PHASE_8822C \ + (BIT_MASK_WLCLK_PHASE_8822C << BIT_SHIFT_WLCLK_PHASE_8822C) +#define BIT_CLEAR_WLCLK_PHASE_8822C(x) ((x) & (~BITS_WLCLK_PHASE_8822C)) +#define BIT_GET_WLCLK_PHASE_8822C(x) \ + (((x) >> BIT_SHIFT_WLCLK_PHASE_8822C) & BIT_MASK_WLCLK_PHASE_8822C) +#define BIT_SET_WLCLK_PHASE_8822C(x, v) \ + (BIT_CLEAR_WLCLK_PHASE_8822C(x) | BIT_WLCLK_PHASE_8822C(v)) + +/* 2 REG_SYS_SDIO_CTRL_8822C */ +#define BIT_DBG_GNT_WL_BT_8822C BIT(27) +#define BIT_LTE_MUX_CTRL_PATH_8822C BIT(26) +#define BIT_LTE_COEX_UART_8822C BIT(25) +#define BIT_3W_LTE_WL_GPIO_8822C BIT(24) +#define BIT_SDIO_INT_POLARITY_8822C BIT(19) +#define BIT_SDIO_INT_8822C BIT(18) +#define BIT_SDIO_OFF_EN_8822C BIT(17) +#define BIT_SDIO_ON_EN_8822C BIT(16) +#define BIT_PCIE_FORCE_PWR_NGAT_8822C BIT(13) +#define BIT_PCIE_CALIB_EN_V1_8822C BIT(12) +#define BIT_PAGE3_AUXCLK_GATE_8822C BIT(11) +#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8822C BIT(10) +#define BIT_PCIE_WAIT_TIME_8822C BIT(9) +#define BIT_MPCIE_REFCLK_XTAL_SEL_8822C BIT(8) +#define BIT_BT_CTRL_USB_PWR_BACKDOOR_8822C BIT(5) +#define BIT_USB_D_STATE_HOLD_8822C BIT(4) +#define BIT_REG_FORCE_DP_8822C BIT(3) +#define BIT_REG_DP_MODE_8822C BIT(2) +#define BIT_RES_USB_MASS_STORAGE_DESC_8822C BIT(1) +#define BIT_USB_WAIT_TIME_8822C BIT(0) + +/* 2 REG_HCI_OPT_CTRL_8822C */ + +#define BIT_SHIFT_TSFT_SEL_8822C 29 +#define BIT_MASK_TSFT_SEL_8822C 0x7 +#define BIT_TSFT_SEL_8822C(x) \ + (((x) & BIT_MASK_TSFT_SEL_8822C) << BIT_SHIFT_TSFT_SEL_8822C) +#define BITS_TSFT_SEL_8822C \ + (BIT_MASK_TSFT_SEL_8822C << BIT_SHIFT_TSFT_SEL_8822C) +#define BIT_CLEAR_TSFT_SEL_8822C(x) ((x) & (~BITS_TSFT_SEL_8822C)) +#define BIT_GET_TSFT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_8822C) & BIT_MASK_TSFT_SEL_8822C) +#define BIT_SET_TSFT_SEL_8822C(x, v) \ + (BIT_CLEAR_TSFT_SEL_8822C(x) | BIT_TSFT_SEL_8822C(v)) + +#define BIT_SDIO_PAD_E5_8822C BIT(18) +#define BIT_USB_HOST_PWR_OFF_EN_8822C BIT(12) +#define BIT_SYM_LPS_BLOCK_EN_8822C BIT(11) +#define BIT_USB_LPM_ACT_EN_8822C BIT(10) +#define BIT_USB_LPM_NY_8822C BIT(9) +#define BIT_USB_SUS_DIS_8822C BIT(8) + +#define BIT_SHIFT_SDIO_PAD_E_8822C 5 +#define BIT_MASK_SDIO_PAD_E_8822C 0x7 +#define BIT_SDIO_PAD_E_8822C(x) \ + (((x) & BIT_MASK_SDIO_PAD_E_8822C) << BIT_SHIFT_SDIO_PAD_E_8822C) +#define BITS_SDIO_PAD_E_8822C \ + (BIT_MASK_SDIO_PAD_E_8822C << BIT_SHIFT_SDIO_PAD_E_8822C) +#define BIT_CLEAR_SDIO_PAD_E_8822C(x) ((x) & (~BITS_SDIO_PAD_E_8822C)) +#define BIT_GET_SDIO_PAD_E_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_PAD_E_8822C) & BIT_MASK_SDIO_PAD_E_8822C) +#define BIT_SET_SDIO_PAD_E_8822C(x, v) \ + (BIT_CLEAR_SDIO_PAD_E_8822C(x) | BIT_SDIO_PAD_E_8822C(v)) + +#define BIT_USB_LPPLL_EN_8822C BIT(4) +#define BIT_USB1_1_USB2_0_DECISION_8822C BIT(3) +#define BIT_ROP_SW15_8822C BIT(2) +#define BIT_PCI_CKRDY_OPT_8822C BIT(1) +#define BIT_PCI_VAUX_EN_8822C BIT(0) + +/* 2 REG_HCI_BG_CTRL_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_IBX_EN_VALUE_8822C BIT(9) +#define BIT_IB_EN_VALUE_8822C BIT(8) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_FORCED_IB_EN_8822C BIT(4) +#define BIT_EN_REGBG_8822C BIT(3) +#define BIT_REG_BG_LPF_8822C BIT(2) + +#define BIT_SHIFT_REG_BG_8822C 0 +#define BIT_MASK_REG_BG_8822C 0x3 +#define BIT_REG_BG_8822C(x) \ + (((x) & BIT_MASK_REG_BG_8822C) << BIT_SHIFT_REG_BG_8822C) +#define BITS_REG_BG_8822C (BIT_MASK_REG_BG_8822C << BIT_SHIFT_REG_BG_8822C) +#define BIT_CLEAR_REG_BG_8822C(x) ((x) & (~BITS_REG_BG_8822C)) +#define BIT_GET_REG_BG_8822C(x) \ + (((x) >> BIT_SHIFT_REG_BG_8822C) & BIT_MASK_REG_BG_8822C) +#define BIT_SET_REG_BG_8822C(x, v) \ + (BIT_CLEAR_REG_BG_8822C(x) | BIT_REG_BG_8822C(v)) + +/* 2 REG_HCI_LDO_CTRL_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_EN_LW_PWR_8822C BIT(6) +#define BIT_EN_REGU_8822C BIT(5) +#define BIT_EN_PC_8822C BIT(4) + +#define BIT_SHIFT_REG_VADJ_8822C 0 +#define BIT_MASK_REG_VADJ_8822C 0xf +#define BIT_REG_VADJ_8822C(x) \ + (((x) & BIT_MASK_REG_VADJ_8822C) << BIT_SHIFT_REG_VADJ_8822C) +#define BITS_REG_VADJ_8822C \ + (BIT_MASK_REG_VADJ_8822C << BIT_SHIFT_REG_VADJ_8822C) +#define BIT_CLEAR_REG_VADJ_8822C(x) ((x) & (~BITS_REG_VADJ_8822C)) +#define BIT_GET_REG_VADJ_8822C(x) \ + (((x) >> BIT_SHIFT_REG_VADJ_8822C) & BIT_MASK_REG_VADJ_8822C) +#define BIT_SET_REG_VADJ_8822C(x, v) \ + (BIT_CLEAR_REG_VADJ_8822C(x) | BIT_REG_VADJ_8822C(v)) + +/* 2 REG_LDO_SWR_CTRL_8822C */ +#define BIT_EXT_SWR_CTRL_EN_8822C BIT(31) +#define BIT_ZCD_HW_AUTO_EN_8822C BIT(27) +#define BIT_ZCD_REGSEL_8822C BIT(26) + +#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C 21 +#define BIT_MASK_AUTO_ZCD_IN_CODE_8822C 0x1f +#define BIT_AUTO_ZCD_IN_CODE_8822C(x) \ + (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822C) \ + << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C) +#define BITS_AUTO_ZCD_IN_CODE_8822C \ + (BIT_MASK_AUTO_ZCD_IN_CODE_8822C << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C) +#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8822C(x) \ + ((x) & (~BITS_AUTO_ZCD_IN_CODE_8822C)) +#define BIT_GET_AUTO_ZCD_IN_CODE_8822C(x) \ + (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C) & \ + BIT_MASK_AUTO_ZCD_IN_CODE_8822C) +#define BIT_SET_AUTO_ZCD_IN_CODE_8822C(x, v) \ + (BIT_CLEAR_AUTO_ZCD_IN_CODE_8822C(x) | BIT_AUTO_ZCD_IN_CODE_8822C(v)) + +#define BIT_SHIFT_ZCD_CODE_IN_L_8822C 16 +#define BIT_MASK_ZCD_CODE_IN_L_8822C 0x1f +#define BIT_ZCD_CODE_IN_L_8822C(x) \ + (((x) & BIT_MASK_ZCD_CODE_IN_L_8822C) << BIT_SHIFT_ZCD_CODE_IN_L_8822C) +#define BITS_ZCD_CODE_IN_L_8822C \ + (BIT_MASK_ZCD_CODE_IN_L_8822C << BIT_SHIFT_ZCD_CODE_IN_L_8822C) +#define BIT_CLEAR_ZCD_CODE_IN_L_8822C(x) ((x) & (~BITS_ZCD_CODE_IN_L_8822C)) +#define BIT_GET_ZCD_CODE_IN_L_8822C(x) \ + (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822C) & BIT_MASK_ZCD_CODE_IN_L_8822C) +#define BIT_SET_ZCD_CODE_IN_L_8822C(x, v) \ + (BIT_CLEAR_ZCD_CODE_IN_L_8822C(x) | BIT_ZCD_CODE_IN_L_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_MCUFW_CTRL_8822C */ + +#define BIT_SHIFT_RPWM_8822C 24 +#define BIT_MASK_RPWM_8822C 0xff +#define BIT_RPWM_8822C(x) (((x) & BIT_MASK_RPWM_8822C) << BIT_SHIFT_RPWM_8822C) +#define BITS_RPWM_8822C (BIT_MASK_RPWM_8822C << BIT_SHIFT_RPWM_8822C) +#define BIT_CLEAR_RPWM_8822C(x) ((x) & (~BITS_RPWM_8822C)) +#define BIT_GET_RPWM_8822C(x) \ + (((x) >> BIT_SHIFT_RPWM_8822C) & BIT_MASK_RPWM_8822C) +#define BIT_SET_RPWM_8822C(x, v) (BIT_CLEAR_RPWM_8822C(x) | BIT_RPWM_8822C(v)) + +#define BIT_ANA_PORT_EN_8822C BIT(22) +#define BIT_MAC_PORT_EN_8822C BIT(21) +#define BIT_BOOT_FSPI_EN_8822C BIT(20) +#define BIT_ROM_DLEN_8822C BIT(19) + +#define BIT_SHIFT_ROM_PGE_8822C 16 +#define BIT_MASK_ROM_PGE_8822C 0x7 +#define BIT_ROM_PGE_8822C(x) \ + (((x) & BIT_MASK_ROM_PGE_8822C) << BIT_SHIFT_ROM_PGE_8822C) +#define BITS_ROM_PGE_8822C (BIT_MASK_ROM_PGE_8822C << BIT_SHIFT_ROM_PGE_8822C) +#define BIT_CLEAR_ROM_PGE_8822C(x) ((x) & (~BITS_ROM_PGE_8822C)) +#define BIT_GET_ROM_PGE_8822C(x) \ + (((x) >> BIT_SHIFT_ROM_PGE_8822C) & BIT_MASK_ROM_PGE_8822C) +#define BIT_SET_ROM_PGE_8822C(x, v) \ + (BIT_CLEAR_ROM_PGE_8822C(x) | BIT_ROM_PGE_8822C(v)) + +#define BIT_FW_INIT_RDY_8822C BIT(15) +#define BIT_FW_DW_RDY_8822C BIT(14) + +#define BIT_SHIFT_CPU_CLK_SEL_8822C 12 +#define BIT_MASK_CPU_CLK_SEL_8822C 0x3 +#define BIT_CPU_CLK_SEL_8822C(x) \ + (((x) & BIT_MASK_CPU_CLK_SEL_8822C) << BIT_SHIFT_CPU_CLK_SEL_8822C) +#define BITS_CPU_CLK_SEL_8822C \ + (BIT_MASK_CPU_CLK_SEL_8822C << BIT_SHIFT_CPU_CLK_SEL_8822C) +#define BIT_CLEAR_CPU_CLK_SEL_8822C(x) ((x) & (~BITS_CPU_CLK_SEL_8822C)) +#define BIT_GET_CPU_CLK_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_CPU_CLK_SEL_8822C) & BIT_MASK_CPU_CLK_SEL_8822C) +#define BIT_SET_CPU_CLK_SEL_8822C(x, v) \ + (BIT_CLEAR_CPU_CLK_SEL_8822C(x) | BIT_CPU_CLK_SEL_8822C(v)) + +#define BIT_CCLK_CHG_MASK_8822C BIT(11) +#define BIT_EMEM__TXBUF_CHKSUM_OK_8822C BIT(10) +#define BIT_EMEM_TXBUF_DW_RDY_8822C BIT(9) +#define BIT_EMEM_CHKSUM_OK_8822C BIT(8) +#define BIT_EMEM_DW_OK_8822C BIT(7) +#define BIT_DMEM_CHKSUM_OK_8822C BIT(6) +#define BIT_DMEM_DW_OK_8822C BIT(5) +#define BIT_IMEM_CHKSUM_OK_8822C BIT(4) +#define BIT_IMEM_DW_OK_8822C BIT(3) +#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8822C BIT(2) +#define BIT_IMEM_BOOT_LOAD_DW_OK_8822C BIT(1) +#define BIT_MCUFWDL_EN_8822C BIT(0) + +/* 2 REG_MCU_TST_CFG_8822C */ + +#define BIT_SHIFT_LBKTST_8822C 0 +#define BIT_MASK_LBKTST_8822C 0xffff +#define BIT_LBKTST_8822C(x) \ + (((x) & BIT_MASK_LBKTST_8822C) << BIT_SHIFT_LBKTST_8822C) +#define BITS_LBKTST_8822C (BIT_MASK_LBKTST_8822C << BIT_SHIFT_LBKTST_8822C) +#define BIT_CLEAR_LBKTST_8822C(x) ((x) & (~BITS_LBKTST_8822C)) +#define BIT_GET_LBKTST_8822C(x) \ + (((x) >> BIT_SHIFT_LBKTST_8822C) & BIT_MASK_LBKTST_8822C) +#define BIT_SET_LBKTST_8822C(x, v) \ + (BIT_CLEAR_LBKTST_8822C(x) | BIT_LBKTST_8822C(v)) + +/* 2 REG_HMEBOX_E0_E1_8822C */ + +#define BIT_SHIFT_HOST_MSG_E1_8822C 16 +#define BIT_MASK_HOST_MSG_E1_8822C 0xffff +#define BIT_HOST_MSG_E1_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_E1_8822C) << BIT_SHIFT_HOST_MSG_E1_8822C) +#define BITS_HOST_MSG_E1_8822C \ + (BIT_MASK_HOST_MSG_E1_8822C << BIT_SHIFT_HOST_MSG_E1_8822C) +#define BIT_CLEAR_HOST_MSG_E1_8822C(x) ((x) & (~BITS_HOST_MSG_E1_8822C)) +#define BIT_GET_HOST_MSG_E1_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E1_8822C) & BIT_MASK_HOST_MSG_E1_8822C) +#define BIT_SET_HOST_MSG_E1_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_E1_8822C(x) | BIT_HOST_MSG_E1_8822C(v)) + +#define BIT_SHIFT_HOST_MSG_E0_8822C 0 +#define BIT_MASK_HOST_MSG_E0_8822C 0xffff +#define BIT_HOST_MSG_E0_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_E0_8822C) << BIT_SHIFT_HOST_MSG_E0_8822C) +#define BITS_HOST_MSG_E0_8822C \ + (BIT_MASK_HOST_MSG_E0_8822C << BIT_SHIFT_HOST_MSG_E0_8822C) +#define BIT_CLEAR_HOST_MSG_E0_8822C(x) ((x) & (~BITS_HOST_MSG_E0_8822C)) +#define BIT_GET_HOST_MSG_E0_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E0_8822C) & BIT_MASK_HOST_MSG_E0_8822C) +#define BIT_SET_HOST_MSG_E0_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_E0_8822C(x) | BIT_HOST_MSG_E0_8822C(v)) + +/* 2 REG_HMEBOX_E2_E3_8822C */ + +#define BIT_SHIFT_HOST_MSG_E3_8822C 16 +#define BIT_MASK_HOST_MSG_E3_8822C 0xffff +#define BIT_HOST_MSG_E3_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_E3_8822C) << BIT_SHIFT_HOST_MSG_E3_8822C) +#define BITS_HOST_MSG_E3_8822C \ + (BIT_MASK_HOST_MSG_E3_8822C << BIT_SHIFT_HOST_MSG_E3_8822C) +#define BIT_CLEAR_HOST_MSG_E3_8822C(x) ((x) & (~BITS_HOST_MSG_E3_8822C)) +#define BIT_GET_HOST_MSG_E3_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E3_8822C) & BIT_MASK_HOST_MSG_E3_8822C) +#define BIT_SET_HOST_MSG_E3_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_E3_8822C(x) | BIT_HOST_MSG_E3_8822C(v)) + +#define BIT_SHIFT_HOST_MSG_E2_8822C 0 +#define BIT_MASK_HOST_MSG_E2_8822C 0xffff +#define BIT_HOST_MSG_E2_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_E2_8822C) << BIT_SHIFT_HOST_MSG_E2_8822C) +#define BITS_HOST_MSG_E2_8822C \ + (BIT_MASK_HOST_MSG_E2_8822C << BIT_SHIFT_HOST_MSG_E2_8822C) +#define BIT_CLEAR_HOST_MSG_E2_8822C(x) ((x) & (~BITS_HOST_MSG_E2_8822C)) +#define BIT_GET_HOST_MSG_E2_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E2_8822C) & BIT_MASK_HOST_MSG_E2_8822C) +#define BIT_SET_HOST_MSG_E2_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_E2_8822C(x) | BIT_HOST_MSG_E2_8822C(v)) + +/* 2 REG_WLLPS_CTRL_8822C */ +#define BIT_WLLPSOP_EABM_8822C BIT(31) +#define BIT_WLLPSOP_ACKF_8822C BIT(30) +#define BIT_WLLPSOP_DLDM_8822C BIT(29) +#define BIT_WLLPSOP_ESWR_8822C BIT(28) +#define BIT_WLLPSOP_PWMM_8822C BIT(27) +#define BIT_WLLPSOP_EECK_8822C BIT(26) +#define BIT_WLLPSOP_WLMACOFF_8822C BIT(25) +#define BIT_WLLPSOP_EXTAL_8822C BIT(24) +#define BIT_WL_SYNPON_VOLTSPDN_8822C BIT(23) +#define BIT_WLLPSOP_WLBBOFF_8822C BIT(22) +#define BIT_WLLPSOP_WLMEM_DS_8822C BIT(21) +#define BIT_WLLPSOP_LDO_WAIT_TIME_8822C BIT(20) +#define BIT_WLLPSOP_ANA_CLK_DIVISION_2_8822C BIT(19) +#define BIT_AFE_BCN_8822C BIT(18) + +#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C 12 +#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C 0xf +#define BIT_LPLDH12_VADJ_STEP_DN_8822C(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C) \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C) +#define BITS_LPLDH12_VADJ_STEP_DN_8822C \ + (BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C) +#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822C(x) \ + ((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8822C)) +#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822C(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C) & \ + BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C) +#define BIT_SET_LPLDH12_VADJ_STEP_DN_8822C(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822C(x) | \ + BIT_LPLDH12_VADJ_STEP_DN_8822C(v)) + +#define BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C 8 +#define BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C 0xf +#define BIT_V15ADJ_L1_STEP_DN_V1_8822C(x) \ + (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C) \ + << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C) +#define BITS_V15ADJ_L1_STEP_DN_V1_8822C \ + (BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C \ + << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C) +#define BIT_CLEAR_V15ADJ_L1_STEP_DN_V1_8822C(x) \ + ((x) & (~BITS_V15ADJ_L1_STEP_DN_V1_8822C)) +#define BIT_GET_V15ADJ_L1_STEP_DN_V1_8822C(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C) & \ + BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C) +#define BIT_SET_V15ADJ_L1_STEP_DN_V1_8822C(x, v) \ + (BIT_CLEAR_V15ADJ_L1_STEP_DN_V1_8822C(x) | \ + BIT_V15ADJ_L1_STEP_DN_V1_8822C(v)) + +#define BIT_FORCE_LEAVE_LPS_8822C BIT(3) +#define BIT_SW_AFE_MODE_8822C BIT(2) +#define BIT_REGU_32K_CLK_EN_8822C BIT(1) +#define BIT_WL_LPS_EN_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_GPIO_DEBOUNCE_CTRL_8822C */ +#define BIT_WLGP_DBC1EN_8822C BIT(15) + +#define BIT_SHIFT_WLGP_DBC1_8822C 8 +#define BIT_MASK_WLGP_DBC1_8822C 0xf +#define BIT_WLGP_DBC1_8822C(x) \ + (((x) & BIT_MASK_WLGP_DBC1_8822C) << BIT_SHIFT_WLGP_DBC1_8822C) +#define BITS_WLGP_DBC1_8822C \ + (BIT_MASK_WLGP_DBC1_8822C << BIT_SHIFT_WLGP_DBC1_8822C) +#define BIT_CLEAR_WLGP_DBC1_8822C(x) ((x) & (~BITS_WLGP_DBC1_8822C)) +#define BIT_GET_WLGP_DBC1_8822C(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC1_8822C) & BIT_MASK_WLGP_DBC1_8822C) +#define BIT_SET_WLGP_DBC1_8822C(x, v) \ + (BIT_CLEAR_WLGP_DBC1_8822C(x) | BIT_WLGP_DBC1_8822C(v)) + +#define BIT_WLGP_DBC0EN_8822C BIT(7) + +#define BIT_SHIFT_WLGP_DBC0_8822C 0 +#define BIT_MASK_WLGP_DBC0_8822C 0xf +#define BIT_WLGP_DBC0_8822C(x) \ + (((x) & BIT_MASK_WLGP_DBC0_8822C) << BIT_SHIFT_WLGP_DBC0_8822C) +#define BITS_WLGP_DBC0_8822C \ + (BIT_MASK_WLGP_DBC0_8822C << BIT_SHIFT_WLGP_DBC0_8822C) +#define BIT_CLEAR_WLGP_DBC0_8822C(x) ((x) & (~BITS_WLGP_DBC0_8822C)) +#define BIT_GET_WLGP_DBC0_8822C(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC0_8822C) & BIT_MASK_WLGP_DBC0_8822C) +#define BIT_SET_WLGP_DBC0_8822C(x, v) \ + (BIT_CLEAR_WLGP_DBC0_8822C(x) | BIT_WLGP_DBC0_8822C(v)) + +/* 2 REG_RPWM2_8822C */ + +#define BIT_SHIFT_RPWM2_8822C 16 +#define BIT_MASK_RPWM2_8822C 0xffff +#define BIT_RPWM2_8822C(x) \ + (((x) & BIT_MASK_RPWM2_8822C) << BIT_SHIFT_RPWM2_8822C) +#define BITS_RPWM2_8822C (BIT_MASK_RPWM2_8822C << BIT_SHIFT_RPWM2_8822C) +#define BIT_CLEAR_RPWM2_8822C(x) ((x) & (~BITS_RPWM2_8822C)) +#define BIT_GET_RPWM2_8822C(x) \ + (((x) >> BIT_SHIFT_RPWM2_8822C) & BIT_MASK_RPWM2_8822C) +#define BIT_SET_RPWM2_8822C(x, v) \ + (BIT_CLEAR_RPWM2_8822C(x) | BIT_RPWM2_8822C(v)) + +/* 2 REG_SYSON_FSM_MON_8822C */ + +#define BIT_SHIFT_FSM_MON_SEL_8822C 24 +#define BIT_MASK_FSM_MON_SEL_8822C 0x7 +#define BIT_FSM_MON_SEL_8822C(x) \ + (((x) & BIT_MASK_FSM_MON_SEL_8822C) << BIT_SHIFT_FSM_MON_SEL_8822C) +#define BITS_FSM_MON_SEL_8822C \ + (BIT_MASK_FSM_MON_SEL_8822C << BIT_SHIFT_FSM_MON_SEL_8822C) +#define BIT_CLEAR_FSM_MON_SEL_8822C(x) ((x) & (~BITS_FSM_MON_SEL_8822C)) +#define BIT_GET_FSM_MON_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_FSM_MON_SEL_8822C) & BIT_MASK_FSM_MON_SEL_8822C) +#define BIT_SET_FSM_MON_SEL_8822C(x, v) \ + (BIT_CLEAR_FSM_MON_SEL_8822C(x) | BIT_FSM_MON_SEL_8822C(v)) + +#define BIT_DOP_ELDO_8822C BIT(23) +#define BIT_FSM_MON_UPD_8822C BIT(15) + +#define BIT_SHIFT_FSM_PAR_8822C 0 +#define BIT_MASK_FSM_PAR_8822C 0x7fff +#define BIT_FSM_PAR_8822C(x) \ + (((x) & BIT_MASK_FSM_PAR_8822C) << BIT_SHIFT_FSM_PAR_8822C) +#define BITS_FSM_PAR_8822C (BIT_MASK_FSM_PAR_8822C << BIT_SHIFT_FSM_PAR_8822C) +#define BIT_CLEAR_FSM_PAR_8822C(x) ((x) & (~BITS_FSM_PAR_8822C)) +#define BIT_GET_FSM_PAR_8822C(x) \ + (((x) >> BIT_SHIFT_FSM_PAR_8822C) & BIT_MASK_FSM_PAR_8822C) +#define BIT_SET_FSM_PAR_8822C(x, v) \ + (BIT_CLEAR_FSM_PAR_8822C(x) | BIT_FSM_PAR_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_PMC_DBG_CTRL1_8822C */ +#define BIT_BT_INT_EN_8822C BIT(31) + +#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C 16 +#define BIT_MASK_RD_WR_WIFI_BT_INFO_8822C 0x7fff +#define BIT_RD_WR_WIFI_BT_INFO_8822C(x) \ + (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822C) \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C) +#define BITS_RD_WR_WIFI_BT_INFO_8822C \ + (BIT_MASK_RD_WR_WIFI_BT_INFO_8822C \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822C(x) \ + ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8822C)) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C) & \ + BIT_MASK_RD_WR_WIFI_BT_INFO_8822C) +#define BIT_SET_RD_WR_WIFI_BT_INFO_8822C(x, v) \ + (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822C(x) | \ + BIT_RD_WR_WIFI_BT_INFO_8822C(v)) + +#define BIT_PMC_WR_OVF_8822C BIT(8) + +#define BIT_SHIFT_WLPMC_ERRINT_8822C 0 +#define BIT_MASK_WLPMC_ERRINT_8822C 0xff +#define BIT_WLPMC_ERRINT_8822C(x) \ + (((x) & BIT_MASK_WLPMC_ERRINT_8822C) << BIT_SHIFT_WLPMC_ERRINT_8822C) +#define BITS_WLPMC_ERRINT_8822C \ + (BIT_MASK_WLPMC_ERRINT_8822C << BIT_SHIFT_WLPMC_ERRINT_8822C) +#define BIT_CLEAR_WLPMC_ERRINT_8822C(x) ((x) & (~BITS_WLPMC_ERRINT_8822C)) +#define BIT_GET_WLPMC_ERRINT_8822C(x) \ + (((x) >> BIT_SHIFT_WLPMC_ERRINT_8822C) & BIT_MASK_WLPMC_ERRINT_8822C) +#define BIT_SET_WLPMC_ERRINT_8822C(x, v) \ + (BIT_CLEAR_WLPMC_ERRINT_8822C(x) | BIT_WLPMC_ERRINT_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_HIMR0_8822C */ +#define BIT_TIMEOUT_INTERRUPT2_MASK_8822C BIT(31) +#define BIT_TIMEOUT_INTERRUTP1_MASK_8822C BIT(30) +#define BIT_PSTIMEOUT_MSK_8822C BIT(29) +#define BIT_GTINT4_MSK_8822C BIT(28) +#define BIT_GTINT3_MSK_8822C BIT(27) +#define BIT_TXBCN0ERR_MSK_8822C BIT(26) +#define BIT_TXBCN0OK_MSK_8822C BIT(25) +#define BIT_TSF_BIT32_TOGGLE_MSK_8822C BIT(24) +#define BIT_BCNDMAINT0_MSK_8822C BIT(20) +#define BIT_BCNDERR0_MSK_8822C BIT(16) +#define BIT_HSISR_IND_ON_INT_MSK_8822C BIT(15) +#define BIT_BCNDMAINT_E_MSK_8822C BIT(14) +#define BIT_CTWEND_MSK_8822C BIT(12) +#define BIT_HISR1_IND_MSK_8822C BIT(11) +#define BIT_C2HCMD_MSK_8822C BIT(10) +#define BIT_CPWM2_MSK_8822C BIT(9) +#define BIT_CPWM_MSK_8822C BIT(8) +#define BIT_HIGHDOK_MSK_8822C BIT(7) +#define BIT_MGTDOK_MSK_8822C BIT(6) +#define BIT_BKDOK_MSK_8822C BIT(5) +#define BIT_BEDOK_MSK_8822C BIT(4) +#define BIT_VIDOK_MSK_8822C BIT(3) +#define BIT_VODOK_MSK_8822C BIT(2) +#define BIT_RDU_MSK_8822C BIT(1) +#define BIT_RXOK_MSK_8822C BIT(0) + +/* 2 REG_HISR0_8822C */ +#define BIT_PSTIMEOUT2_8822C BIT(31) +#define BIT_PSTIMEOUT1_8822C BIT(30) +#define BIT_PSTIMEOUT_8822C BIT(29) +#define BIT_GTINT4_8822C BIT(28) +#define BIT_GTINT3_8822C BIT(27) +#define BIT_TXBCN0ERR_8822C BIT(26) +#define BIT_TXBCN0OK_8822C BIT(25) +#define BIT_TSF_BIT32_TOGGLE_8822C BIT(24) +#define BIT_BCNDMAINT0_8822C BIT(20) +#define BIT_BCNDERR0_8822C BIT(16) +#define BIT_HSISR_IND_ON_INT_8822C BIT(15) +#define BIT_BCNDMAINT_E_8822C BIT(14) +#define BIT_CTWEND_8822C BIT(12) +#define BIT_HISR1_IND_INT_8822C BIT(11) +#define BIT_C2HCMD_8822C BIT(10) +#define BIT_CPWM2_8822C BIT(9) +#define BIT_CPWM_8822C BIT(8) +#define BIT_HIGHDOK_8822C BIT(7) +#define BIT_MGTDOK_8822C BIT(6) +#define BIT_BKDOK_8822C BIT(5) +#define BIT_BEDOK_8822C BIT(4) +#define BIT_VIDOK_8822C BIT(3) +#define BIT_VODOK_8822C BIT(2) +#define BIT_RDU_8822C BIT(1) +#define BIT_RXOK_8822C BIT(0) + +/* 2 REG_HIMR1_8822C */ +#define BIT_TXFIFO_TH_INT_8822C BIT(30) +#define BIT_BTON_STS_UPDATE_MASK_8822C BIT(29) +#define BIT_MCU_ERR_MASK_8822C BIT(28) +#define BIT_BCNDMAINT7__MSK_8822C BIT(27) +#define BIT_BCNDMAINT6__MSK_8822C BIT(26) +#define BIT_BCNDMAINT5__MSK_8822C BIT(25) +#define BIT_BCNDMAINT4__MSK_8822C BIT(24) +#define BIT_BCNDMAINT3_MSK_8822C BIT(23) +#define BIT_BCNDMAINT2_MSK_8822C BIT(22) +#define BIT_BCNDMAINT1_MSK_8822C BIT(21) +#define BIT_BCNDERR7_MSK_8822C BIT(20) +#define BIT_BCNDERR6_MSK_8822C BIT(19) +#define BIT_BCNDERR5_MSK_8822C BIT(18) +#define BIT_BCNDERR4_MSK_8822C BIT(17) +#define BIT_BCNDERR3_MSK_8822C BIT(16) +#define BIT_BCNDERR2_MSK_8822C BIT(15) +#define BIT_BCNDERR1_MSK_8822C BIT(14) +#define BIT_ATIMEND_E_MSK_8822C BIT(13) +#define BIT_ATIMEND__MSK_8822C BIT(12) +#define BIT_TXERR_MSK_8822C BIT(11) +#define BIT_RXERR_MSK_8822C BIT(10) +#define BIT_TXFOVW_MSK_8822C BIT(9) +#define BIT_FOVW_MSK_8822C BIT(8) +#define BIT_CPU_MGQ_TXDONE_MSK_8822C BIT(5) +#define BIT_PS_TIMER_C_MSK_8822C BIT(4) +#define BIT_PS_TIMER_B_MSK_8822C BIT(3) +#define BIT_PS_TIMER_A_MSK_8822C BIT(2) +#define BIT_CPUMGQ_TX_TIMER_MSK_8822C BIT(1) + +/* 2 REG_HISR1_8822C */ +#define BIT_TXFIFO_TH_INT_8822C BIT(30) +#define BIT_BTON_STS_UPDATE_INT_8822C BIT(29) +#define BIT_MCU_ERR_8822C BIT(28) +#define BIT_BCNDMAINT7_8822C BIT(27) +#define BIT_BCNDMAINT6_8822C BIT(26) +#define BIT_BCNDMAINT5_8822C BIT(25) +#define BIT_BCNDMAINT4_8822C BIT(24) +#define BIT_BCNDMAINT3_8822C BIT(23) +#define BIT_BCNDMAINT2_8822C BIT(22) +#define BIT_BCNDMAINT1_8822C BIT(21) +#define BIT_BCNDERR7_8822C BIT(20) +#define BIT_BCNDERR6_8822C BIT(19) +#define BIT_BCNDERR5_8822C BIT(18) +#define BIT_BCNDERR4_8822C BIT(17) +#define BIT_BCNDERR3_8822C BIT(16) +#define BIT_BCNDERR2_8822C BIT(15) +#define BIT_BCNDERR1_8822C BIT(14) +#define BIT_ATIMEND_E_8822C BIT(13) +#define BIT_ATIMEND_8822C BIT(12) +#define BIT_TXERR_INT_8822C BIT(11) +#define BIT_RXERR_INT_8822C BIT(10) +#define BIT_TXFOVW_8822C BIT(9) +#define BIT_FOVW_8822C BIT(8) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_CPU_MGQ_TXDONE_8822C BIT(5) +#define BIT_PS_TIMER_C_8822C BIT(4) +#define BIT_PS_TIMER_B_8822C BIT(3) +#define BIT_PS_TIMER_A_8822C BIT(2) +#define BIT_CPUMGQ_TX_TIMER_8822C BIT(1) + +/* 2 REG_DBG_PORT_SEL_8822C */ + +#define BIT_SHIFT_DEBUG_ST_8822C 0 +#define BIT_MASK_DEBUG_ST_8822C 0xffffffffL +#define BIT_DEBUG_ST_8822C(x) \ + (((x) & BIT_MASK_DEBUG_ST_8822C) << BIT_SHIFT_DEBUG_ST_8822C) +#define BITS_DEBUG_ST_8822C \ + (BIT_MASK_DEBUG_ST_8822C << BIT_SHIFT_DEBUG_ST_8822C) +#define BIT_CLEAR_DEBUG_ST_8822C(x) ((x) & (~BITS_DEBUG_ST_8822C)) +#define BIT_GET_DEBUG_ST_8822C(x) \ + (((x) >> BIT_SHIFT_DEBUG_ST_8822C) & BIT_MASK_DEBUG_ST_8822C) +#define BIT_SET_DEBUG_ST_8822C(x, v) \ + (BIT_CLEAR_DEBUG_ST_8822C(x) | BIT_DEBUG_ST_8822C(v)) + +/* 2 REG_PAD_CTRL2_8822C */ +#define BIT_USB3_USB2_TRANSITION_8822C BIT(20) + +#define BIT_SHIFT_USB23_SW_MODE_V1_8822C 18 +#define BIT_MASK_USB23_SW_MODE_V1_8822C 0x3 +#define BIT_USB23_SW_MODE_V1_8822C(x) \ + (((x) & BIT_MASK_USB23_SW_MODE_V1_8822C) \ + << BIT_SHIFT_USB23_SW_MODE_V1_8822C) +#define BITS_USB23_SW_MODE_V1_8822C \ + (BIT_MASK_USB23_SW_MODE_V1_8822C << BIT_SHIFT_USB23_SW_MODE_V1_8822C) +#define BIT_CLEAR_USB23_SW_MODE_V1_8822C(x) \ + ((x) & (~BITS_USB23_SW_MODE_V1_8822C)) +#define BIT_GET_USB23_SW_MODE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822C) & \ + BIT_MASK_USB23_SW_MODE_V1_8822C) +#define BIT_SET_USB23_SW_MODE_V1_8822C(x, v) \ + (BIT_CLEAR_USB23_SW_MODE_V1_8822C(x) | BIT_USB23_SW_MODE_V1_8822C(v)) + +#define BIT_NO_PDN_CHIPOFF_V1_8822C BIT(17) +#define BIT_RSM_EN_V1_8822C BIT(16) + +#define BIT_SHIFT_MATCH_CNT_8822C 8 +#define BIT_MASK_MATCH_CNT_8822C 0xff +#define BIT_MATCH_CNT_8822C(x) \ + (((x) & BIT_MASK_MATCH_CNT_8822C) << BIT_SHIFT_MATCH_CNT_8822C) +#define BITS_MATCH_CNT_8822C \ + (BIT_MASK_MATCH_CNT_8822C << BIT_SHIFT_MATCH_CNT_8822C) +#define BIT_CLEAR_MATCH_CNT_8822C(x) ((x) & (~BITS_MATCH_CNT_8822C)) +#define BIT_GET_MATCH_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8822C) & BIT_MASK_MATCH_CNT_8822C) +#define BIT_SET_MATCH_CNT_8822C(x, v) \ + (BIT_CLEAR_MATCH_CNT_8822C(x) | BIT_MATCH_CNT_8822C(v)) + +#define BIT_LD_B12V_EN_8822C BIT(7) +#define BIT_EECS_IOSEL_V1_8822C BIT(6) +#define BIT_EECS_DATA_O_V1_8822C BIT(5) +#define BIT_EECS_DATA_I_V1_8822C BIT(4) +#define BIT_EESK_IOSEL_V1_8822C BIT(2) +#define BIT_EESK_DATA_O_V1_8822C BIT(1) +#define BIT_EESK_DATA_I_V1_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_PMC_DBG_CTRL2_8822C */ + +#define BIT_SHIFT_EFUSE_BURN_GNT_8822C 24 +#define BIT_MASK_EFUSE_BURN_GNT_8822C 0xff +#define BIT_EFUSE_BURN_GNT_8822C(x) \ + (((x) & BIT_MASK_EFUSE_BURN_GNT_8822C) \ + << BIT_SHIFT_EFUSE_BURN_GNT_8822C) +#define BITS_EFUSE_BURN_GNT_8822C \ + (BIT_MASK_EFUSE_BURN_GNT_8822C << BIT_SHIFT_EFUSE_BURN_GNT_8822C) +#define BIT_CLEAR_EFUSE_BURN_GNT_8822C(x) ((x) & (~BITS_EFUSE_BURN_GNT_8822C)) +#define BIT_GET_EFUSE_BURN_GNT_8822C(x) \ + (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822C) & \ + BIT_MASK_EFUSE_BURN_GNT_8822C) +#define BIT_SET_EFUSE_BURN_GNT_8822C(x, v) \ + (BIT_CLEAR_EFUSE_BURN_GNT_8822C(x) | BIT_EFUSE_BURN_GNT_8822C(v)) + +#define BIT_STOP_WL_PMC_8822C BIT(9) +#define BIT_STOP_SYM_PMC_8822C BIT(8) +#define BIT_BT_ACCESS_WL_PAGE0_8822C BIT(6) +#define BIT_REG_RST_WLPMC_8822C BIT(5) +#define BIT_REG_RST_PD12N_8822C BIT(4) +#define BIT_SYSON_DIS_WLREG_WRMSK_8822C BIT(3) +#define BIT_SYSON_DIS_PMCREG_WRMSK_8822C BIT(2) + +#define BIT_SHIFT_SYSON_REG_ARB_8822C 0 +#define BIT_MASK_SYSON_REG_ARB_8822C 0x3 +#define BIT_SYSON_REG_ARB_8822C(x) \ + (((x) & BIT_MASK_SYSON_REG_ARB_8822C) << BIT_SHIFT_SYSON_REG_ARB_8822C) +#define BITS_SYSON_REG_ARB_8822C \ + (BIT_MASK_SYSON_REG_ARB_8822C << BIT_SHIFT_SYSON_REG_ARB_8822C) +#define BIT_CLEAR_SYSON_REG_ARB_8822C(x) ((x) & (~BITS_SYSON_REG_ARB_8822C)) +#define BIT_GET_SYSON_REG_ARB_8822C(x) \ + (((x) >> BIT_SHIFT_SYSON_REG_ARB_8822C) & BIT_MASK_SYSON_REG_ARB_8822C) +#define BIT_SET_SYSON_REG_ARB_8822C(x, v) \ + (BIT_CLEAR_SYSON_REG_ARB_8822C(x) | BIT_SYSON_REG_ARB_8822C(v)) + +/* 2 REG_BIST_CTRL_8822C */ +#define BIT_BIST_USB_DIS_8822C BIT(27) +#define BIT_BIST_PCI_DIS_8822C BIT(26) +#define BIT_BIST_BT_DIS_8822C BIT(25) +#define BIT_BIST_WL_DIS_8822C BIT(24) + +#define BIT_SHIFT_BIST_RPT_SEL_8822C 16 +#define BIT_MASK_BIST_RPT_SEL_8822C 0xf +#define BIT_BIST_RPT_SEL_8822C(x) \ + (((x) & BIT_MASK_BIST_RPT_SEL_8822C) << BIT_SHIFT_BIST_RPT_SEL_8822C) +#define BITS_BIST_RPT_SEL_8822C \ + (BIT_MASK_BIST_RPT_SEL_8822C << BIT_SHIFT_BIST_RPT_SEL_8822C) +#define BIT_CLEAR_BIST_RPT_SEL_8822C(x) ((x) & (~BITS_BIST_RPT_SEL_8822C)) +#define BIT_GET_BIST_RPT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_BIST_RPT_SEL_8822C) & BIT_MASK_BIST_RPT_SEL_8822C) +#define BIT_SET_BIST_RPT_SEL_8822C(x, v) \ + (BIT_CLEAR_BIST_RPT_SEL_8822C(x) | BIT_BIST_RPT_SEL_8822C(v)) + +#define BIT_BIST_RESUME_PS_8822C BIT(4) +#define BIT_BIST_RESUME_8822C BIT(3) +#define BIT_BIST_NORMAL_8822C BIT(2) +#define BIT_BIST_RSTN_8822C BIT(1) +#define BIT_BIST_CLK_EN_8822C BIT(0) + +/* 2 REG_BIST_RPT_8822C */ + +#define BIT_SHIFT_MBIST_REPORT_8822C 0 +#define BIT_MASK_MBIST_REPORT_8822C 0xffffffffL +#define BIT_MBIST_REPORT_8822C(x) \ + (((x) & BIT_MASK_MBIST_REPORT_8822C) << BIT_SHIFT_MBIST_REPORT_8822C) +#define BITS_MBIST_REPORT_8822C \ + (BIT_MASK_MBIST_REPORT_8822C << BIT_SHIFT_MBIST_REPORT_8822C) +#define BIT_CLEAR_MBIST_REPORT_8822C(x) ((x) & (~BITS_MBIST_REPORT_8822C)) +#define BIT_GET_MBIST_REPORT_8822C(x) \ + (((x) >> BIT_SHIFT_MBIST_REPORT_8822C) & BIT_MASK_MBIST_REPORT_8822C) +#define BIT_SET_MBIST_REPORT_8822C(x, v) \ + (BIT_CLEAR_MBIST_REPORT_8822C(x) | BIT_MBIST_REPORT_8822C(v)) + +/* 2 REG_MEM_CTRL_8822C */ +#define BIT_UMEM_RME_8822C BIT(31) + +#define BIT_SHIFT_BT_SPRAM_8822C 28 +#define BIT_MASK_BT_SPRAM_8822C 0x3 +#define BIT_BT_SPRAM_8822C(x) \ + (((x) & BIT_MASK_BT_SPRAM_8822C) << BIT_SHIFT_BT_SPRAM_8822C) +#define BITS_BT_SPRAM_8822C \ + (BIT_MASK_BT_SPRAM_8822C << BIT_SHIFT_BT_SPRAM_8822C) +#define BIT_CLEAR_BT_SPRAM_8822C(x) ((x) & (~BITS_BT_SPRAM_8822C)) +#define BIT_GET_BT_SPRAM_8822C(x) \ + (((x) >> BIT_SHIFT_BT_SPRAM_8822C) & BIT_MASK_BT_SPRAM_8822C) +#define BIT_SET_BT_SPRAM_8822C(x, v) \ + (BIT_CLEAR_BT_SPRAM_8822C(x) | BIT_BT_SPRAM_8822C(v)) + +#define BIT_SHIFT_BT_ROM_8822C 24 +#define BIT_MASK_BT_ROM_8822C 0xf +#define BIT_BT_ROM_8822C(x) \ + (((x) & BIT_MASK_BT_ROM_8822C) << BIT_SHIFT_BT_ROM_8822C) +#define BITS_BT_ROM_8822C (BIT_MASK_BT_ROM_8822C << BIT_SHIFT_BT_ROM_8822C) +#define BIT_CLEAR_BT_ROM_8822C(x) ((x) & (~BITS_BT_ROM_8822C)) +#define BIT_GET_BT_ROM_8822C(x) \ + (((x) >> BIT_SHIFT_BT_ROM_8822C) & BIT_MASK_BT_ROM_8822C) +#define BIT_SET_BT_ROM_8822C(x, v) \ + (BIT_CLEAR_BT_ROM_8822C(x) | BIT_BT_ROM_8822C(v)) + +#define BIT_SHIFT_PCI_DPRAM_8822C 10 +#define BIT_MASK_PCI_DPRAM_8822C 0x3 +#define BIT_PCI_DPRAM_8822C(x) \ + (((x) & BIT_MASK_PCI_DPRAM_8822C) << BIT_SHIFT_PCI_DPRAM_8822C) +#define BITS_PCI_DPRAM_8822C \ + (BIT_MASK_PCI_DPRAM_8822C << BIT_SHIFT_PCI_DPRAM_8822C) +#define BIT_CLEAR_PCI_DPRAM_8822C(x) ((x) & (~BITS_PCI_DPRAM_8822C)) +#define BIT_GET_PCI_DPRAM_8822C(x) \ + (((x) >> BIT_SHIFT_PCI_DPRAM_8822C) & BIT_MASK_PCI_DPRAM_8822C) +#define BIT_SET_PCI_DPRAM_8822C(x, v) \ + (BIT_CLEAR_PCI_DPRAM_8822C(x) | BIT_PCI_DPRAM_8822C(v)) + +#define BIT_SHIFT_PCI_SPRAM_8822C 8 +#define BIT_MASK_PCI_SPRAM_8822C 0x3 +#define BIT_PCI_SPRAM_8822C(x) \ + (((x) & BIT_MASK_PCI_SPRAM_8822C) << BIT_SHIFT_PCI_SPRAM_8822C) +#define BITS_PCI_SPRAM_8822C \ + (BIT_MASK_PCI_SPRAM_8822C << BIT_SHIFT_PCI_SPRAM_8822C) +#define BIT_CLEAR_PCI_SPRAM_8822C(x) ((x) & (~BITS_PCI_SPRAM_8822C)) +#define BIT_GET_PCI_SPRAM_8822C(x) \ + (((x) >> BIT_SHIFT_PCI_SPRAM_8822C) & BIT_MASK_PCI_SPRAM_8822C) +#define BIT_SET_PCI_SPRAM_8822C(x, v) \ + (BIT_CLEAR_PCI_SPRAM_8822C(x) | BIT_PCI_SPRAM_8822C(v)) + +#define BIT_SHIFT_USB_SPRAM_8822C 6 +#define BIT_MASK_USB_SPRAM_8822C 0x3 +#define BIT_USB_SPRAM_8822C(x) \ + (((x) & BIT_MASK_USB_SPRAM_8822C) << BIT_SHIFT_USB_SPRAM_8822C) +#define BITS_USB_SPRAM_8822C \ + (BIT_MASK_USB_SPRAM_8822C << BIT_SHIFT_USB_SPRAM_8822C) +#define BIT_CLEAR_USB_SPRAM_8822C(x) ((x) & (~BITS_USB_SPRAM_8822C)) +#define BIT_GET_USB_SPRAM_8822C(x) \ + (((x) >> BIT_SHIFT_USB_SPRAM_8822C) & BIT_MASK_USB_SPRAM_8822C) +#define BIT_SET_USB_SPRAM_8822C(x, v) \ + (BIT_CLEAR_USB_SPRAM_8822C(x) | BIT_USB_SPRAM_8822C(v)) + +#define BIT_SHIFT_USB_SPRF_8822C 4 +#define BIT_MASK_USB_SPRF_8822C 0x3 +#define BIT_USB_SPRF_8822C(x) \ + (((x) & BIT_MASK_USB_SPRF_8822C) << BIT_SHIFT_USB_SPRF_8822C) +#define BITS_USB_SPRF_8822C \ + (BIT_MASK_USB_SPRF_8822C << BIT_SHIFT_USB_SPRF_8822C) +#define BIT_CLEAR_USB_SPRF_8822C(x) ((x) & (~BITS_USB_SPRF_8822C)) +#define BIT_GET_USB_SPRF_8822C(x) \ + (((x) >> BIT_SHIFT_USB_SPRF_8822C) & BIT_MASK_USB_SPRF_8822C) +#define BIT_SET_USB_SPRF_8822C(x, v) \ + (BIT_CLEAR_USB_SPRF_8822C(x) | BIT_USB_SPRF_8822C(v)) + +#define BIT_SHIFT_MCU_ROM_8822C 0 +#define BIT_MASK_MCU_ROM_8822C 0xf +#define BIT_MCU_ROM_8822C(x) \ + (((x) & BIT_MASK_MCU_ROM_8822C) << BIT_SHIFT_MCU_ROM_8822C) +#define BITS_MCU_ROM_8822C (BIT_MASK_MCU_ROM_8822C << BIT_SHIFT_MCU_ROM_8822C) +#define BIT_CLEAR_MCU_ROM_8822C(x) ((x) & (~BITS_MCU_ROM_8822C)) +#define BIT_GET_MCU_ROM_8822C(x) \ + (((x) >> BIT_SHIFT_MCU_ROM_8822C) & BIT_MASK_MCU_ROM_8822C) +#define BIT_SET_MCU_ROM_8822C(x, v) \ + (BIT_CLEAR_MCU_ROM_8822C(x) | BIT_MCU_ROM_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_USB_SIE_INTF_8822C */ +#define BIT_RD_SEL_8822C BIT(31) +#define BIT_USB_SIE_INTF_WE_V1_8822C BIT(30) +#define BIT_USB_SIE_INTF_BYIOREG_V1_8822C BIT(29) +#define BIT_USB_SIE_SELECT_8822C BIT(28) + +#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C 16 +#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C 0x1ff +#define BIT_USB_SIE_INTF_ADDR_V1_8822C(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C) \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C) +#define BITS_USB_SIE_INTF_ADDR_V1_8822C \ + (BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C) +#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822C(x) \ + ((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8822C)) +#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822C(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C) & \ + BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C) +#define BIT_SET_USB_SIE_INTF_ADDR_V1_8822C(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822C(x) | \ + BIT_USB_SIE_INTF_ADDR_V1_8822C(v)) + +#define BIT_SHIFT_USB_SIE_INTF_RD_8822C 8 +#define BIT_MASK_USB_SIE_INTF_RD_8822C 0xff +#define BIT_USB_SIE_INTF_RD_8822C(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_RD_8822C) \ + << BIT_SHIFT_USB_SIE_INTF_RD_8822C) +#define BITS_USB_SIE_INTF_RD_8822C \ + (BIT_MASK_USB_SIE_INTF_RD_8822C << BIT_SHIFT_USB_SIE_INTF_RD_8822C) +#define BIT_CLEAR_USB_SIE_INTF_RD_8822C(x) ((x) & (~BITS_USB_SIE_INTF_RD_8822C)) +#define BIT_GET_USB_SIE_INTF_RD_8822C(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822C) & \ + BIT_MASK_USB_SIE_INTF_RD_8822C) +#define BIT_SET_USB_SIE_INTF_RD_8822C(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_RD_8822C(x) | BIT_USB_SIE_INTF_RD_8822C(v)) + +#define BIT_SHIFT_USB_SIE_INTF_WD_8822C 0 +#define BIT_MASK_USB_SIE_INTF_WD_8822C 0xff +#define BIT_USB_SIE_INTF_WD_8822C(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_WD_8822C) \ + << BIT_SHIFT_USB_SIE_INTF_WD_8822C) +#define BITS_USB_SIE_INTF_WD_8822C \ + (BIT_MASK_USB_SIE_INTF_WD_8822C << BIT_SHIFT_USB_SIE_INTF_WD_8822C) +#define BIT_CLEAR_USB_SIE_INTF_WD_8822C(x) ((x) & (~BITS_USB_SIE_INTF_WD_8822C)) +#define BIT_GET_USB_SIE_INTF_WD_8822C(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822C) & \ + BIT_MASK_USB_SIE_INTF_WD_8822C) +#define BIT_SET_USB_SIE_INTF_WD_8822C(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_WD_8822C(x) | BIT_USB_SIE_INTF_WD_8822C(v)) + +/* 2 REG_PCIE_MIO_INTF_8822C */ + +#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C 16 +#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C 0x3 +#define BIT_PCIE_MIO_ADDR_PAGE_8822C(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C) \ + << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C) +#define BITS_PCIE_MIO_ADDR_PAGE_8822C \ + (BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C \ + << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C) +#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8822C(x) \ + ((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8822C)) +#define BIT_GET_PCIE_MIO_ADDR_PAGE_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C) & \ + BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C) +#define BIT_SET_PCIE_MIO_ADDR_PAGE_8822C(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8822C(x) | \ + BIT_PCIE_MIO_ADDR_PAGE_8822C(v)) + +#define BIT_PCIE_MIO_BYIOREG_8822C BIT(13) +#define BIT_PCIE_MIO_RE_8822C BIT(12) + +#define BIT_SHIFT_PCIE_MIO_WE_8822C 8 +#define BIT_MASK_PCIE_MIO_WE_8822C 0xf +#define BIT_PCIE_MIO_WE_8822C(x) \ + (((x) & BIT_MASK_PCIE_MIO_WE_8822C) << BIT_SHIFT_PCIE_MIO_WE_8822C) +#define BITS_PCIE_MIO_WE_8822C \ + (BIT_MASK_PCIE_MIO_WE_8822C << BIT_SHIFT_PCIE_MIO_WE_8822C) +#define BIT_CLEAR_PCIE_MIO_WE_8822C(x) ((x) & (~BITS_PCIE_MIO_WE_8822C)) +#define BIT_GET_PCIE_MIO_WE_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_WE_8822C) & BIT_MASK_PCIE_MIO_WE_8822C) +#define BIT_SET_PCIE_MIO_WE_8822C(x, v) \ + (BIT_CLEAR_PCIE_MIO_WE_8822C(x) | BIT_PCIE_MIO_WE_8822C(v)) + +#define BIT_SHIFT_PCIE_MIO_ADDR_8822C 0 +#define BIT_MASK_PCIE_MIO_ADDR_8822C 0xff +#define BIT_PCIE_MIO_ADDR_8822C(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_8822C) << BIT_SHIFT_PCIE_MIO_ADDR_8822C) +#define BITS_PCIE_MIO_ADDR_8822C \ + (BIT_MASK_PCIE_MIO_ADDR_8822C << BIT_SHIFT_PCIE_MIO_ADDR_8822C) +#define BIT_CLEAR_PCIE_MIO_ADDR_8822C(x) ((x) & (~BITS_PCIE_MIO_ADDR_8822C)) +#define BIT_GET_PCIE_MIO_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822C) & BIT_MASK_PCIE_MIO_ADDR_8822C) +#define BIT_SET_PCIE_MIO_ADDR_8822C(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_8822C(x) | BIT_PCIE_MIO_ADDR_8822C(v)) + +/* 2 REG_PCIE_MIO_INTD_8822C */ + +#define BIT_SHIFT_PCIE_MIO_DATA_8822C 0 +#define BIT_MASK_PCIE_MIO_DATA_8822C 0xffffffffL +#define BIT_PCIE_MIO_DATA_8822C(x) \ + (((x) & BIT_MASK_PCIE_MIO_DATA_8822C) << BIT_SHIFT_PCIE_MIO_DATA_8822C) +#define BITS_PCIE_MIO_DATA_8822C \ + (BIT_MASK_PCIE_MIO_DATA_8822C << BIT_SHIFT_PCIE_MIO_DATA_8822C) +#define BIT_CLEAR_PCIE_MIO_DATA_8822C(x) ((x) & (~BITS_PCIE_MIO_DATA_8822C)) +#define BIT_GET_PCIE_MIO_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822C) & BIT_MASK_PCIE_MIO_DATA_8822C) +#define BIT_SET_PCIE_MIO_DATA_8822C(x, v) \ + (BIT_CLEAR_PCIE_MIO_DATA_8822C(x) | BIT_PCIE_MIO_DATA_8822C(v)) + +/* 2 REG_WLRF1_8822C */ + +#define BIT_SHIFT_WLRF1_CTRL_8822C 24 +#define BIT_MASK_WLRF1_CTRL_8822C 0xff +#define BIT_WLRF1_CTRL_8822C(x) \ + (((x) & BIT_MASK_WLRF1_CTRL_8822C) << BIT_SHIFT_WLRF1_CTRL_8822C) +#define BITS_WLRF1_CTRL_8822C \ + (BIT_MASK_WLRF1_CTRL_8822C << BIT_SHIFT_WLRF1_CTRL_8822C) +#define BIT_CLEAR_WLRF1_CTRL_8822C(x) ((x) & (~BITS_WLRF1_CTRL_8822C)) +#define BIT_GET_WLRF1_CTRL_8822C(x) \ + (((x) >> BIT_SHIFT_WLRF1_CTRL_8822C) & BIT_MASK_WLRF1_CTRL_8822C) +#define BIT_SET_WLRF1_CTRL_8822C(x, v) \ + (BIT_CLEAR_WLRF1_CTRL_8822C(x) | BIT_WLRF1_CTRL_8822C(v)) + +/* 2 REG_SYS_CFG1_8822C */ + +#define BIT_SHIFT_TRP_ICFG_8822C 28 +#define BIT_MASK_TRP_ICFG_8822C 0xf +#define BIT_TRP_ICFG_8822C(x) \ + (((x) & BIT_MASK_TRP_ICFG_8822C) << BIT_SHIFT_TRP_ICFG_8822C) +#define BITS_TRP_ICFG_8822C \ + (BIT_MASK_TRP_ICFG_8822C << BIT_SHIFT_TRP_ICFG_8822C) +#define BIT_CLEAR_TRP_ICFG_8822C(x) ((x) & (~BITS_TRP_ICFG_8822C)) +#define BIT_GET_TRP_ICFG_8822C(x) \ + (((x) >> BIT_SHIFT_TRP_ICFG_8822C) & BIT_MASK_TRP_ICFG_8822C) +#define BIT_SET_TRP_ICFG_8822C(x, v) \ + (BIT_CLEAR_TRP_ICFG_8822C(x) | BIT_TRP_ICFG_8822C(v)) + +#define BIT_RF_TYPE_ID_8822C BIT(27) +#define BIT_BD_HCI_SEL_8822C BIT(26) +#define BIT_BD_PKG_SEL_8822C BIT(25) +#define BIT_INTERNAL_EXTERNAL_SWR_8822C BIT(24) +#define BIT_RTL_ID_8822C BIT(23) +#define BIT_PAD_HWPD_IDN_8822C BIT(22) +#define BIT_TESTMODE_8822C BIT(20) + +#define BIT_SHIFT_VENDOR_ID_8822C 16 +#define BIT_MASK_VENDOR_ID_8822C 0xf +#define BIT_VENDOR_ID_8822C(x) \ + (((x) & BIT_MASK_VENDOR_ID_8822C) << BIT_SHIFT_VENDOR_ID_8822C) +#define BITS_VENDOR_ID_8822C \ + (BIT_MASK_VENDOR_ID_8822C << BIT_SHIFT_VENDOR_ID_8822C) +#define BIT_CLEAR_VENDOR_ID_8822C(x) ((x) & (~BITS_VENDOR_ID_8822C)) +#define BIT_GET_VENDOR_ID_8822C(x) \ + (((x) >> BIT_SHIFT_VENDOR_ID_8822C) & BIT_MASK_VENDOR_ID_8822C) +#define BIT_SET_VENDOR_ID_8822C(x, v) \ + (BIT_CLEAR_VENDOR_ID_8822C(x) | BIT_VENDOR_ID_8822C(v)) + +#define BIT_SHIFT_CHIP_VER_8822C 12 +#define BIT_MASK_CHIP_VER_8822C 0xf +#define BIT_CHIP_VER_8822C(x) \ + (((x) & BIT_MASK_CHIP_VER_8822C) << BIT_SHIFT_CHIP_VER_8822C) +#define BITS_CHIP_VER_8822C \ + (BIT_MASK_CHIP_VER_8822C << BIT_SHIFT_CHIP_VER_8822C) +#define BIT_CLEAR_CHIP_VER_8822C(x) ((x) & (~BITS_CHIP_VER_8822C)) +#define BIT_GET_CHIP_VER_8822C(x) \ + (((x) >> BIT_SHIFT_CHIP_VER_8822C) & BIT_MASK_CHIP_VER_8822C) +#define BIT_SET_CHIP_VER_8822C(x, v) \ + (BIT_CLEAR_CHIP_VER_8822C(x) | BIT_CHIP_VER_8822C(v)) + +#define BIT_BD_MAC3_8822C BIT(11) +#define BIT_BD_MAC1_8822C BIT(10) +#define BIT_BD_MAC2_8822C BIT(9) +#define BIT_SIC_IDLE_8822C BIT(8) +#define BIT_SW_OFFLOAD_EN_8822C BIT(7) +#define BIT_OCP_SHUTDN_8822C BIT(6) +#define BIT_V15_VLD_8822C BIT(5) +#define BIT_PCIRSTB_8822C BIT(4) +#define BIT_PCLK_VLD_8822C BIT(3) +#define BIT_UCLK_VLD_8822C BIT(2) +#define BIT_ACLK_VLD_8822C BIT(1) +#define BIT_XCLK_VLD_8822C BIT(0) + +/* 2 REG_SYS_STATUS1_8822C */ + +#define BIT_SHIFT_RF_RL_ID_8822C 28 +#define BIT_MASK_RF_RL_ID_8822C 0xf +#define BIT_RF_RL_ID_8822C(x) \ + (((x) & BIT_MASK_RF_RL_ID_8822C) << BIT_SHIFT_RF_RL_ID_8822C) +#define BITS_RF_RL_ID_8822C \ + (BIT_MASK_RF_RL_ID_8822C << BIT_SHIFT_RF_RL_ID_8822C) +#define BIT_CLEAR_RF_RL_ID_8822C(x) ((x) & (~BITS_RF_RL_ID_8822C)) +#define BIT_GET_RF_RL_ID_8822C(x) \ + (((x) >> BIT_SHIFT_RF_RL_ID_8822C) & BIT_MASK_RF_RL_ID_8822C) +#define BIT_SET_RF_RL_ID_8822C(x, v) \ + (BIT_CLEAR_RF_RL_ID_8822C(x) | BIT_RF_RL_ID_8822C(v)) + +#define BIT_HPHY_ICFG_8822C BIT(19) + +#define BIT_SHIFT_SEL_0XC0_8822C 16 +#define BIT_MASK_SEL_0XC0_8822C 0x3 +#define BIT_SEL_0XC0_8822C(x) \ + (((x) & BIT_MASK_SEL_0XC0_8822C) << BIT_SHIFT_SEL_0XC0_8822C) +#define BITS_SEL_0XC0_8822C \ + (BIT_MASK_SEL_0XC0_8822C << BIT_SHIFT_SEL_0XC0_8822C) +#define BIT_CLEAR_SEL_0XC0_8822C(x) ((x) & (~BITS_SEL_0XC0_8822C)) +#define BIT_GET_SEL_0XC0_8822C(x) \ + (((x) >> BIT_SHIFT_SEL_0XC0_8822C) & BIT_MASK_SEL_0XC0_8822C) +#define BIT_SET_SEL_0XC0_8822C(x, v) \ + (BIT_CLEAR_SEL_0XC0_8822C(x) | BIT_SEL_0XC0_8822C(v)) + +#define BIT_SHIFT_HCI_SEL_V4_8822C 12 +#define BIT_MASK_HCI_SEL_V4_8822C 0x3 +#define BIT_HCI_SEL_V4_8822C(x) \ + (((x) & BIT_MASK_HCI_SEL_V4_8822C) << BIT_SHIFT_HCI_SEL_V4_8822C) +#define BITS_HCI_SEL_V4_8822C \ + (BIT_MASK_HCI_SEL_V4_8822C << BIT_SHIFT_HCI_SEL_V4_8822C) +#define BIT_CLEAR_HCI_SEL_V4_8822C(x) ((x) & (~BITS_HCI_SEL_V4_8822C)) +#define BIT_GET_HCI_SEL_V4_8822C(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V4_8822C) & BIT_MASK_HCI_SEL_V4_8822C) +#define BIT_SET_HCI_SEL_V4_8822C(x, v) \ + (BIT_CLEAR_HCI_SEL_V4_8822C(x) | BIT_HCI_SEL_V4_8822C(v)) + +#define BIT_USB_OPERATION_MODE_8822C BIT(10) +#define BIT_BT_PDN_8822C BIT(9) +#define BIT_AUTO_WLPON_8822C BIT(8) +#define BIT_WL_MODE_8822C BIT(7) +#define BIT_PKG_SEL_HCI_8822C BIT(6) + +#define BIT_SHIFT_PAD_HCI_SEL_V2_8822C 3 +#define BIT_MASK_PAD_HCI_SEL_V2_8822C 0x3 +#define BIT_PAD_HCI_SEL_V2_8822C(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_V2_8822C) \ + << BIT_SHIFT_PAD_HCI_SEL_V2_8822C) +#define BITS_PAD_HCI_SEL_V2_8822C \ + (BIT_MASK_PAD_HCI_SEL_V2_8822C << BIT_SHIFT_PAD_HCI_SEL_V2_8822C) +#define BIT_CLEAR_PAD_HCI_SEL_V2_8822C(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8822C)) +#define BIT_GET_PAD_HCI_SEL_V2_8822C(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8822C) & \ + BIT_MASK_PAD_HCI_SEL_V2_8822C) +#define BIT_SET_PAD_HCI_SEL_V2_8822C(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_V2_8822C(x) | BIT_PAD_HCI_SEL_V2_8822C(v)) + +#define BIT_SHIFT_EFS_HCI_SEL_V1_8822C 0 +#define BIT_MASK_EFS_HCI_SEL_V1_8822C 0x7 +#define BIT_EFS_HCI_SEL_V1_8822C(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL_V1_8822C) \ + << BIT_SHIFT_EFS_HCI_SEL_V1_8822C) +#define BITS_EFS_HCI_SEL_V1_8822C \ + (BIT_MASK_EFS_HCI_SEL_V1_8822C << BIT_SHIFT_EFS_HCI_SEL_V1_8822C) +#define BIT_CLEAR_EFS_HCI_SEL_V1_8822C(x) ((x) & (~BITS_EFS_HCI_SEL_V1_8822C)) +#define BIT_GET_EFS_HCI_SEL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822C) & \ + BIT_MASK_EFS_HCI_SEL_V1_8822C) +#define BIT_SET_EFS_HCI_SEL_V1_8822C(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL_V1_8822C(x) | BIT_EFS_HCI_SEL_V1_8822C(v)) + +/* 2 REG_SYS_STATUS2_8822C */ +#define BIT_HIOE_ON_TIMEOUT_8822C BIT(23) +#define BIT_SIC_ON_TIMEOUT_8822C BIT(22) +#define BIT_CPU_ON_TIMEOUT_8822C BIT(21) +#define BIT_HCI_ON_TIMEOUT_8822C BIT(20) +#define BIT_SIO_ALDN_8822C BIT(19) +#define BIT_USB_ALDN_8822C BIT(18) +#define BIT_PCI_ALDN_8822C BIT(17) +#define BIT_SYS_ALDN_8822C BIT(16) + +#define BIT_SHIFT_EPVID1_8822C 8 +#define BIT_MASK_EPVID1_8822C 0xff +#define BIT_EPVID1_8822C(x) \ + (((x) & BIT_MASK_EPVID1_8822C) << BIT_SHIFT_EPVID1_8822C) +#define BITS_EPVID1_8822C (BIT_MASK_EPVID1_8822C << BIT_SHIFT_EPVID1_8822C) +#define BIT_CLEAR_EPVID1_8822C(x) ((x) & (~BITS_EPVID1_8822C)) +#define BIT_GET_EPVID1_8822C(x) \ + (((x) >> BIT_SHIFT_EPVID1_8822C) & BIT_MASK_EPVID1_8822C) +#define BIT_SET_EPVID1_8822C(x, v) \ + (BIT_CLEAR_EPVID1_8822C(x) | BIT_EPVID1_8822C(v)) + +#define BIT_SHIFT_EPVID0_8822C 0 +#define BIT_MASK_EPVID0_8822C 0xff +#define BIT_EPVID0_8822C(x) \ + (((x) & BIT_MASK_EPVID0_8822C) << BIT_SHIFT_EPVID0_8822C) +#define BITS_EPVID0_8822C (BIT_MASK_EPVID0_8822C << BIT_SHIFT_EPVID0_8822C) +#define BIT_CLEAR_EPVID0_8822C(x) ((x) & (~BITS_EPVID0_8822C)) +#define BIT_GET_EPVID0_8822C(x) \ + (((x) >> BIT_SHIFT_EPVID0_8822C) & BIT_MASK_EPVID0_8822C) +#define BIT_SET_EPVID0_8822C(x, v) \ + (BIT_CLEAR_EPVID0_8822C(x) | BIT_EPVID0_8822C(v)) + +/* 2 REG_SYS_CFG2_8822C */ +#define BIT_HCI_SEL_EMBEDDED_8822C BIT(8) + +#define BIT_SHIFT_HW_ID_8822C 0 +#define BIT_MASK_HW_ID_8822C 0xff +#define BIT_HW_ID_8822C(x) \ + (((x) & BIT_MASK_HW_ID_8822C) << BIT_SHIFT_HW_ID_8822C) +#define BITS_HW_ID_8822C (BIT_MASK_HW_ID_8822C << BIT_SHIFT_HW_ID_8822C) +#define BIT_CLEAR_HW_ID_8822C(x) ((x) & (~BITS_HW_ID_8822C)) +#define BIT_GET_HW_ID_8822C(x) \ + (((x) >> BIT_SHIFT_HW_ID_8822C) & BIT_MASK_HW_ID_8822C) +#define BIT_SET_HW_ID_8822C(x, v) \ + (BIT_CLEAR_HW_ID_8822C(x) | BIT_HW_ID_8822C(v)) + +/* 2 REG_SYS_CFG3_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ANAPARSW_MAC_0_8822C */ +#define BIT_OCP_L_8822C BIT(31) +#define BIT_POWOCP_L_8822C BIT(30) + +#define BIT_SHIFT_CF_L_V2_8822C 28 +#define BIT_MASK_CF_L_V2_8822C 0x3 +#define BIT_CF_L_V2_8822C(x) \ + (((x) & BIT_MASK_CF_L_V2_8822C) << BIT_SHIFT_CF_L_V2_8822C) +#define BITS_CF_L_V2_8822C (BIT_MASK_CF_L_V2_8822C << BIT_SHIFT_CF_L_V2_8822C) +#define BIT_CLEAR_CF_L_V2_8822C(x) ((x) & (~BITS_CF_L_V2_8822C)) +#define BIT_GET_CF_L_V2_8822C(x) \ + (((x) >> BIT_SHIFT_CF_L_V2_8822C) & BIT_MASK_CF_L_V2_8822C) +#define BIT_SET_CF_L_V2_8822C(x, v) \ + (BIT_CLEAR_CF_L_V2_8822C(x) | BIT_CF_L_V2_8822C(v)) + +#define BIT_SHIFT_CFC_L_V2_8822C 26 +#define BIT_MASK_CFC_L_V2_8822C 0x3 +#define BIT_CFC_L_V2_8822C(x) \ + (((x) & BIT_MASK_CFC_L_V2_8822C) << BIT_SHIFT_CFC_L_V2_8822C) +#define BITS_CFC_L_V2_8822C \ + (BIT_MASK_CFC_L_V2_8822C << BIT_SHIFT_CFC_L_V2_8822C) +#define BIT_CLEAR_CFC_L_V2_8822C(x) ((x) & (~BITS_CFC_L_V2_8822C)) +#define BIT_GET_CFC_L_V2_8822C(x) \ + (((x) >> BIT_SHIFT_CFC_L_V2_8822C) & BIT_MASK_CFC_L_V2_8822C) +#define BIT_SET_CFC_L_V2_8822C(x, v) \ + (BIT_CLEAR_CFC_L_V2_8822C(x) | BIT_CFC_L_V2_8822C(v)) + +#define BIT_SHIFT_R3_L_V2_8822C 24 +#define BIT_MASK_R3_L_V2_8822C 0x3 +#define BIT_R3_L_V2_8822C(x) \ + (((x) & BIT_MASK_R3_L_V2_8822C) << BIT_SHIFT_R3_L_V2_8822C) +#define BITS_R3_L_V2_8822C (BIT_MASK_R3_L_V2_8822C << BIT_SHIFT_R3_L_V2_8822C) +#define BIT_CLEAR_R3_L_V2_8822C(x) ((x) & (~BITS_R3_L_V2_8822C)) +#define BIT_GET_R3_L_V2_8822C(x) \ + (((x) >> BIT_SHIFT_R3_L_V2_8822C) & BIT_MASK_R3_L_V2_8822C) +#define BIT_SET_R3_L_V2_8822C(x, v) \ + (BIT_CLEAR_R3_L_V2_8822C(x) | BIT_R3_L_V2_8822C(v)) + +#define BIT_SHIFT_R2_L_8822C 22 +#define BIT_MASK_R2_L_8822C 0x3 +#define BIT_R2_L_8822C(x) (((x) & BIT_MASK_R2_L_8822C) << BIT_SHIFT_R2_L_8822C) +#define BITS_R2_L_8822C (BIT_MASK_R2_L_8822C << BIT_SHIFT_R2_L_8822C) +#define BIT_CLEAR_R2_L_8822C(x) ((x) & (~BITS_R2_L_8822C)) +#define BIT_GET_R2_L_8822C(x) \ + (((x) >> BIT_SHIFT_R2_L_8822C) & BIT_MASK_R2_L_8822C) +#define BIT_SET_R2_L_8822C(x, v) (BIT_CLEAR_R2_L_8822C(x) | BIT_R2_L_8822C(v)) + +#define BIT_SHIFT_R1_L_8822C 20 +#define BIT_MASK_R1_L_8822C 0x3 +#define BIT_R1_L_8822C(x) (((x) & BIT_MASK_R1_L_8822C) << BIT_SHIFT_R1_L_8822C) +#define BITS_R1_L_8822C (BIT_MASK_R1_L_8822C << BIT_SHIFT_R1_L_8822C) +#define BIT_CLEAR_R1_L_8822C(x) ((x) & (~BITS_R1_L_8822C)) +#define BIT_GET_R1_L_8822C(x) \ + (((x) >> BIT_SHIFT_R1_L_8822C) & BIT_MASK_R1_L_8822C) +#define BIT_SET_R1_L_8822C(x, v) (BIT_CLEAR_R1_L_8822C(x) | BIT_R1_L_8822C(v)) + +#define BIT_SHIFT_C3_L_8822C 18 +#define BIT_MASK_C3_L_8822C 0x3 +#define BIT_C3_L_8822C(x) (((x) & BIT_MASK_C3_L_8822C) << BIT_SHIFT_C3_L_8822C) +#define BITS_C3_L_8822C (BIT_MASK_C3_L_8822C << BIT_SHIFT_C3_L_8822C) +#define BIT_CLEAR_C3_L_8822C(x) ((x) & (~BITS_C3_L_8822C)) +#define BIT_GET_C3_L_8822C(x) \ + (((x) >> BIT_SHIFT_C3_L_8822C) & BIT_MASK_C3_L_8822C) +#define BIT_SET_C3_L_8822C(x, v) (BIT_CLEAR_C3_L_8822C(x) | BIT_C3_L_8822C(v)) + +#define BIT_SHIFT_C2_L_8822C 16 +#define BIT_MASK_C2_L_8822C 0x3 +#define BIT_C2_L_8822C(x) (((x) & BIT_MASK_C2_L_8822C) << BIT_SHIFT_C2_L_8822C) +#define BITS_C2_L_8822C (BIT_MASK_C2_L_8822C << BIT_SHIFT_C2_L_8822C) +#define BIT_CLEAR_C2_L_8822C(x) ((x) & (~BITS_C2_L_8822C)) +#define BIT_GET_C2_L_8822C(x) \ + (((x) >> BIT_SHIFT_C2_L_8822C) & BIT_MASK_C2_L_8822C) +#define BIT_SET_C2_L_8822C(x, v) (BIT_CLEAR_C2_L_8822C(x) | BIT_C2_L_8822C(v)) + +#define BIT_SHIFT_C1_L_V2_8822C 14 +#define BIT_MASK_C1_L_V2_8822C 0x3 +#define BIT_C1_L_V2_8822C(x) \ + (((x) & BIT_MASK_C1_L_V2_8822C) << BIT_SHIFT_C1_L_V2_8822C) +#define BITS_C1_L_V2_8822C (BIT_MASK_C1_L_V2_8822C << BIT_SHIFT_C1_L_V2_8822C) +#define BIT_CLEAR_C1_L_V2_8822C(x) ((x) & (~BITS_C1_L_V2_8822C)) +#define BIT_GET_C1_L_V2_8822C(x) \ + (((x) >> BIT_SHIFT_C1_L_V2_8822C) & BIT_MASK_C1_L_V2_8822C) +#define BIT_SET_C1_L_V2_8822C(x, v) \ + (BIT_CLEAR_C1_L_V2_8822C(x) | BIT_C1_L_V2_8822C(v)) + +#define BIT_REG_OCPS_L_V2_8822C BIT(13) +#define BIT_REG_PWM_L_8822C BIT(12) + +#define BIT_SHIFT_V15ADJ_L_8822C 9 +#define BIT_MASK_V15ADJ_L_8822C 0x7 +#define BIT_V15ADJ_L_8822C(x) \ + (((x) & BIT_MASK_V15ADJ_L_8822C) << BIT_SHIFT_V15ADJ_L_8822C) +#define BITS_V15ADJ_L_8822C \ + (BIT_MASK_V15ADJ_L_8822C << BIT_SHIFT_V15ADJ_L_8822C) +#define BIT_CLEAR_V15ADJ_L_8822C(x) ((x) & (~BITS_V15ADJ_L_8822C)) +#define BIT_GET_V15ADJ_L_8822C(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L_8822C) & BIT_MASK_V15ADJ_L_8822C) +#define BIT_SET_V15ADJ_L_8822C(x, v) \ + (BIT_CLEAR_V15ADJ_L_8822C(x) | BIT_V15ADJ_L_8822C(v)) + +#define BIT_SHIFT_IN_L_8822C 6 +#define BIT_MASK_IN_L_8822C 0x7 +#define BIT_IN_L_8822C(x) (((x) & BIT_MASK_IN_L_8822C) << BIT_SHIFT_IN_L_8822C) +#define BITS_IN_L_8822C (BIT_MASK_IN_L_8822C << BIT_SHIFT_IN_L_8822C) +#define BIT_CLEAR_IN_L_8822C(x) ((x) & (~BITS_IN_L_8822C)) +#define BIT_GET_IN_L_8822C(x) \ + (((x) >> BIT_SHIFT_IN_L_8822C) & BIT_MASK_IN_L_8822C) +#define BIT_SET_IN_L_8822C(x, v) (BIT_CLEAR_IN_L_8822C(x) | BIT_IN_L_8822C(v)) + +#define BIT_SHIFT_STD_L_8822C 4 +#define BIT_MASK_STD_L_8822C 0x3 +#define BIT_STD_L_8822C(x) \ + (((x) & BIT_MASK_STD_L_8822C) << BIT_SHIFT_STD_L_8822C) +#define BITS_STD_L_8822C (BIT_MASK_STD_L_8822C << BIT_SHIFT_STD_L_8822C) +#define BIT_CLEAR_STD_L_8822C(x) ((x) & (~BITS_STD_L_8822C)) +#define BIT_GET_STD_L_8822C(x) \ + (((x) >> BIT_SHIFT_STD_L_8822C) & BIT_MASK_STD_L_8822C) +#define BIT_SET_STD_L_8822C(x, v) \ + (BIT_CLEAR_STD_L_8822C(x) | BIT_STD_L_8822C(v)) + +#define BIT_SHIFT_VOL_L_8822C 0 +#define BIT_MASK_VOL_L_8822C 0xf +#define BIT_VOL_L_8822C(x) \ + (((x) & BIT_MASK_VOL_L_8822C) << BIT_SHIFT_VOL_L_8822C) +#define BITS_VOL_L_8822C (BIT_MASK_VOL_L_8822C << BIT_SHIFT_VOL_L_8822C) +#define BIT_CLEAR_VOL_L_8822C(x) ((x) & (~BITS_VOL_L_8822C)) +#define BIT_GET_VOL_L_8822C(x) \ + (((x) >> BIT_SHIFT_VOL_L_8822C) & BIT_MASK_VOL_L_8822C) +#define BIT_SET_VOL_L_8822C(x, v) \ + (BIT_CLEAR_VOL_L_8822C(x) | BIT_VOL_L_8822C(v)) + +/* 2 REG_ANAPARSW_MAC_1_8822C */ + +#define BIT_SHIFT_OCP_L_PFM_8822C 29 +#define BIT_MASK_OCP_L_PFM_8822C 0x7 +#define BIT_OCP_L_PFM_8822C(x) \ + (((x) & BIT_MASK_OCP_L_PFM_8822C) << BIT_SHIFT_OCP_L_PFM_8822C) +#define BITS_OCP_L_PFM_8822C \ + (BIT_MASK_OCP_L_PFM_8822C << BIT_SHIFT_OCP_L_PFM_8822C) +#define BIT_CLEAR_OCP_L_PFM_8822C(x) ((x) & (~BITS_OCP_L_PFM_8822C)) +#define BIT_GET_OCP_L_PFM_8822C(x) \ + (((x) >> BIT_SHIFT_OCP_L_PFM_8822C) & BIT_MASK_OCP_L_PFM_8822C) +#define BIT_SET_OCP_L_PFM_8822C(x, v) \ + (BIT_CLEAR_OCP_L_PFM_8822C(x) | BIT_OCP_L_PFM_8822C(v)) + +#define BIT_SHIFT_CFC_L_PFM_8822C 27 +#define BIT_MASK_CFC_L_PFM_8822C 0x3 +#define BIT_CFC_L_PFM_8822C(x) \ + (((x) & BIT_MASK_CFC_L_PFM_8822C) << BIT_SHIFT_CFC_L_PFM_8822C) +#define BITS_CFC_L_PFM_8822C \ + (BIT_MASK_CFC_L_PFM_8822C << BIT_SHIFT_CFC_L_PFM_8822C) +#define BIT_CLEAR_CFC_L_PFM_8822C(x) ((x) & (~BITS_CFC_L_PFM_8822C)) +#define BIT_GET_CFC_L_PFM_8822C(x) \ + (((x) >> BIT_SHIFT_CFC_L_PFM_8822C) & BIT_MASK_CFC_L_PFM_8822C) +#define BIT_SET_CFC_L_PFM_8822C(x, v) \ + (BIT_CLEAR_CFC_L_PFM_8822C(x) | BIT_CFC_L_PFM_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_REG_FREQ_L_V1_8822C 20 +#define BIT_MASK_REG_FREQ_L_V1_8822C 0x7 +#define BIT_REG_FREQ_L_V1_8822C(x) \ + (((x) & BIT_MASK_REG_FREQ_L_V1_8822C) << BIT_SHIFT_REG_FREQ_L_V1_8822C) +#define BITS_REG_FREQ_L_V1_8822C \ + (BIT_MASK_REG_FREQ_L_V1_8822C << BIT_SHIFT_REG_FREQ_L_V1_8822C) +#define BIT_CLEAR_REG_FREQ_L_V1_8822C(x) ((x) & (~BITS_REG_FREQ_L_V1_8822C)) +#define BIT_GET_REG_FREQ_L_V1_8822C(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L_V1_8822C) & BIT_MASK_REG_FREQ_L_V1_8822C) +#define BIT_SET_REG_FREQ_L_V1_8822C(x, v) \ + (BIT_CLEAR_REG_FREQ_L_V1_8822C(x) | BIT_REG_FREQ_L_V1_8822C(v)) + +#define BIT_EN_DUTY_8822C BIT(19) + +#define BIT_SHIFT_REG_MODE_V2_8822C 17 +#define BIT_MASK_REG_MODE_V2_8822C 0x3 +#define BIT_REG_MODE_V2_8822C(x) \ + (((x) & BIT_MASK_REG_MODE_V2_8822C) << BIT_SHIFT_REG_MODE_V2_8822C) +#define BITS_REG_MODE_V2_8822C \ + (BIT_MASK_REG_MODE_V2_8822C << BIT_SHIFT_REG_MODE_V2_8822C) +#define BIT_CLEAR_REG_MODE_V2_8822C(x) ((x) & (~BITS_REG_MODE_V2_8822C)) +#define BIT_GET_REG_MODE_V2_8822C(x) \ + (((x) >> BIT_SHIFT_REG_MODE_V2_8822C) & BIT_MASK_REG_MODE_V2_8822C) +#define BIT_SET_REG_MODE_V2_8822C(x, v) \ + (BIT_CLEAR_REG_MODE_V2_8822C(x) | BIT_REG_MODE_V2_8822C(v)) + +#define BIT_EN_SP_8822C BIT(16) +#define BIT_REG_AUTO_L_V2_8822C BIT(15) +#define BIT_REG_LDOF_L_V2_8822C BIT(14) +#define BIT_REG_TYPE_L_V2_8822C BIT(13) +#define BIT_VO15_V1P05_H_8822C BIT(12) +#define BIT_ARENB_L_V2_8822C BIT(11) + +#define BIT_SHIFT_TBOX_L1_V2_8822C 9 +#define BIT_MASK_TBOX_L1_V2_8822C 0x3 +#define BIT_TBOX_L1_V2_8822C(x) \ + (((x) & BIT_MASK_TBOX_L1_V2_8822C) << BIT_SHIFT_TBOX_L1_V2_8822C) +#define BITS_TBOX_L1_V2_8822C \ + (BIT_MASK_TBOX_L1_V2_8822C << BIT_SHIFT_TBOX_L1_V2_8822C) +#define BIT_CLEAR_TBOX_L1_V2_8822C(x) ((x) & (~BITS_TBOX_L1_V2_8822C)) +#define BIT_GET_TBOX_L1_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_V2_8822C) & BIT_MASK_TBOX_L1_V2_8822C) +#define BIT_SET_TBOX_L1_V2_8822C(x, v) \ + (BIT_CLEAR_TBOX_L1_V2_8822C(x) | BIT_TBOX_L1_V2_8822C(v)) + +#define BIT_SHIFT_REG_DELAY_L_8822C 7 +#define BIT_MASK_REG_DELAY_L_8822C 0x3 +#define BIT_REG_DELAY_L_8822C(x) \ + (((x) & BIT_MASK_REG_DELAY_L_8822C) << BIT_SHIFT_REG_DELAY_L_8822C) +#define BITS_REG_DELAY_L_8822C \ + (BIT_MASK_REG_DELAY_L_8822C << BIT_SHIFT_REG_DELAY_L_8822C) +#define BIT_CLEAR_REG_DELAY_L_8822C(x) ((x) & (~BITS_REG_DELAY_L_8822C)) +#define BIT_GET_REG_DELAY_L_8822C(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_L_8822C) & BIT_MASK_REG_DELAY_L_8822C) +#define BIT_SET_REG_DELAY_L_8822C(x, v) \ + (BIT_CLEAR_REG_DELAY_L_8822C(x) | BIT_REG_DELAY_L_8822C(v)) + +#define BIT_REG_CLAMP_D_L_8822C BIT(6) +#define BIT_REG_BYPASS_L_V2_8822C BIT(5) +#define BIT_REG_AUTOZCD_L_8822C BIT(4) +#define BIT_POW_ZCD_L_V2_8822C BIT(3) +#define BIT_REG_HALF_L_8822C BIT(2) + +#define BIT_SHIFT_OCP_L_V2_8822C 0 +#define BIT_MASK_OCP_L_V2_8822C 0x3 +#define BIT_OCP_L_V2_8822C(x) \ + (((x) & BIT_MASK_OCP_L_V2_8822C) << BIT_SHIFT_OCP_L_V2_8822C) +#define BITS_OCP_L_V2_8822C \ + (BIT_MASK_OCP_L_V2_8822C << BIT_SHIFT_OCP_L_V2_8822C) +#define BIT_CLEAR_OCP_L_V2_8822C(x) ((x) & (~BITS_OCP_L_V2_8822C)) +#define BIT_GET_OCP_L_V2_8822C(x) \ + (((x) >> BIT_SHIFT_OCP_L_V2_8822C) & BIT_MASK_OCP_L_V2_8822C) +#define BIT_SET_OCP_L_V2_8822C(x, v) \ + (BIT_CLEAR_OCP_L_V2_8822C(x) | BIT_OCP_L_V2_8822C(v)) + +/* 2 REG_ANAPAR_MAC_0_8822C */ + +#define BIT_SHIFT_REG_LPF_R3_8822C 29 +#define BIT_MASK_REG_LPF_R3_8822C 0x7 +#define BIT_REG_LPF_R3_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_R3_8822C) << BIT_SHIFT_REG_LPF_R3_8822C) +#define BITS_REG_LPF_R3_8822C \ + (BIT_MASK_REG_LPF_R3_8822C << BIT_SHIFT_REG_LPF_R3_8822C) +#define BIT_CLEAR_REG_LPF_R3_8822C(x) ((x) & (~BITS_REG_LPF_R3_8822C)) +#define BIT_GET_REG_LPF_R3_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R3_8822C) & BIT_MASK_REG_LPF_R3_8822C) +#define BIT_SET_REG_LPF_R3_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_R3_8822C(x) | BIT_REG_LPF_R3_8822C(v)) + +#define BIT_SHIFT_REG_LPF_R2_8822C 24 +#define BIT_MASK_REG_LPF_R2_8822C 0x1f +#define BIT_REG_LPF_R2_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_R2_8822C) << BIT_SHIFT_REG_LPF_R2_8822C) +#define BITS_REG_LPF_R2_8822C \ + (BIT_MASK_REG_LPF_R2_8822C << BIT_SHIFT_REG_LPF_R2_8822C) +#define BIT_CLEAR_REG_LPF_R2_8822C(x) ((x) & (~BITS_REG_LPF_R2_8822C)) +#define BIT_GET_REG_LPF_R2_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R2_8822C) & BIT_MASK_REG_LPF_R2_8822C) +#define BIT_SET_REG_LPF_R2_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_R2_8822C(x) | BIT_REG_LPF_R2_8822C(v)) + +#define BIT_SHIFT_REG_LPF_C3_8822C 21 +#define BIT_MASK_REG_LPF_C3_8822C 0x7 +#define BIT_REG_LPF_C3_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_C3_8822C) << BIT_SHIFT_REG_LPF_C3_8822C) +#define BITS_REG_LPF_C3_8822C \ + (BIT_MASK_REG_LPF_C3_8822C << BIT_SHIFT_REG_LPF_C3_8822C) +#define BIT_CLEAR_REG_LPF_C3_8822C(x) ((x) & (~BITS_REG_LPF_C3_8822C)) +#define BIT_GET_REG_LPF_C3_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C3_8822C) & BIT_MASK_REG_LPF_C3_8822C) +#define BIT_SET_REG_LPF_C3_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_C3_8822C(x) | BIT_REG_LPF_C3_8822C(v)) + +#define BIT_SHIFT_REG_LPF_C2_8822C 18 +#define BIT_MASK_REG_LPF_C2_8822C 0x7 +#define BIT_REG_LPF_C2_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_C2_8822C) << BIT_SHIFT_REG_LPF_C2_8822C) +#define BITS_REG_LPF_C2_8822C \ + (BIT_MASK_REG_LPF_C2_8822C << BIT_SHIFT_REG_LPF_C2_8822C) +#define BIT_CLEAR_REG_LPF_C2_8822C(x) ((x) & (~BITS_REG_LPF_C2_8822C)) +#define BIT_GET_REG_LPF_C2_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C2_8822C) & BIT_MASK_REG_LPF_C2_8822C) +#define BIT_SET_REG_LPF_C2_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_C2_8822C(x) | BIT_REG_LPF_C2_8822C(v)) + +#define BIT_SHIFT_REG_LPF_C1_8822C 15 +#define BIT_MASK_REG_LPF_C1_8822C 0x7 +#define BIT_REG_LPF_C1_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_C1_8822C) << BIT_SHIFT_REG_LPF_C1_8822C) +#define BITS_REG_LPF_C1_8822C \ + (BIT_MASK_REG_LPF_C1_8822C << BIT_SHIFT_REG_LPF_C1_8822C) +#define BIT_CLEAR_REG_LPF_C1_8822C(x) ((x) & (~BITS_REG_LPF_C1_8822C)) +#define BIT_GET_REG_LPF_C1_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C1_8822C) & BIT_MASK_REG_LPF_C1_8822C) +#define BIT_SET_REG_LPF_C1_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_C1_8822C(x) | BIT_REG_LPF_C1_8822C(v)) + +#define BIT_SHIFT_REG_LDO_SEL_V1_8822C 13 +#define BIT_MASK_REG_LDO_SEL_V1_8822C 0x3 +#define BIT_REG_LDO_SEL_V1_8822C(x) \ + (((x) & BIT_MASK_REG_LDO_SEL_V1_8822C) \ + << BIT_SHIFT_REG_LDO_SEL_V1_8822C) +#define BITS_REG_LDO_SEL_V1_8822C \ + (BIT_MASK_REG_LDO_SEL_V1_8822C << BIT_SHIFT_REG_LDO_SEL_V1_8822C) +#define BIT_CLEAR_REG_LDO_SEL_V1_8822C(x) ((x) & (~BITS_REG_LDO_SEL_V1_8822C)) +#define BIT_GET_REG_LDO_SEL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LDO_SEL_V1_8822C) & \ + BIT_MASK_REG_LDO_SEL_V1_8822C) +#define BIT_SET_REG_LDO_SEL_V1_8822C(x, v) \ + (BIT_CLEAR_REG_LDO_SEL_V1_8822C(x) | BIT_REG_LDO_SEL_V1_8822C(v)) + +#define BIT_REG_CP_ICPX2_8822C BIT(12) + +#define BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C 9 +#define BIT_MASK_REG_CP_ICP_SEL_FAST_8822C 0x7 +#define BIT_REG_CP_ICP_SEL_FAST_8822C(x) \ + (((x) & BIT_MASK_REG_CP_ICP_SEL_FAST_8822C) \ + << BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C) +#define BITS_REG_CP_ICP_SEL_FAST_8822C \ + (BIT_MASK_REG_CP_ICP_SEL_FAST_8822C \ + << BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C) +#define BIT_CLEAR_REG_CP_ICP_SEL_FAST_8822C(x) \ + ((x) & (~BITS_REG_CP_ICP_SEL_FAST_8822C)) +#define BIT_GET_REG_CP_ICP_SEL_FAST_8822C(x) \ + (((x) >> BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C) & \ + BIT_MASK_REG_CP_ICP_SEL_FAST_8822C) +#define BIT_SET_REG_CP_ICP_SEL_FAST_8822C(x, v) \ + (BIT_CLEAR_REG_CP_ICP_SEL_FAST_8822C(x) | \ + BIT_REG_CP_ICP_SEL_FAST_8822C(v)) + +#define BIT_SHIFT_REG_CP_ICP_SEL_8822C 6 +#define BIT_MASK_REG_CP_ICP_SEL_8822C 0x7 +#define BIT_REG_CP_ICP_SEL_8822C(x) \ + (((x) & BIT_MASK_REG_CP_ICP_SEL_8822C) \ + << BIT_SHIFT_REG_CP_ICP_SEL_8822C) +#define BITS_REG_CP_ICP_SEL_8822C \ + (BIT_MASK_REG_CP_ICP_SEL_8822C << BIT_SHIFT_REG_CP_ICP_SEL_8822C) +#define BIT_CLEAR_REG_CP_ICP_SEL_8822C(x) ((x) & (~BITS_REG_CP_ICP_SEL_8822C)) +#define BIT_GET_REG_CP_ICP_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_REG_CP_ICP_SEL_8822C) & \ + BIT_MASK_REG_CP_ICP_SEL_8822C) +#define BIT_SET_REG_CP_ICP_SEL_8822C(x, v) \ + (BIT_CLEAR_REG_CP_ICP_SEL_8822C(x) | BIT_REG_CP_ICP_SEL_8822C(v)) + +#define BIT_SHIFT_REG_IB_PI_8822C 4 +#define BIT_MASK_REG_IB_PI_8822C 0x3 +#define BIT_REG_IB_PI_8822C(x) \ + (((x) & BIT_MASK_REG_IB_PI_8822C) << BIT_SHIFT_REG_IB_PI_8822C) +#define BITS_REG_IB_PI_8822C \ + (BIT_MASK_REG_IB_PI_8822C << BIT_SHIFT_REG_IB_PI_8822C) +#define BIT_CLEAR_REG_IB_PI_8822C(x) ((x) & (~BITS_REG_IB_PI_8822C)) +#define BIT_GET_REG_IB_PI_8822C(x) \ + (((x) >> BIT_SHIFT_REG_IB_PI_8822C) & BIT_MASK_REG_IB_PI_8822C) +#define BIT_SET_REG_IB_PI_8822C(x, v) \ + (BIT_CLEAR_REG_IB_PI_8822C(x) | BIT_REG_IB_PI_8822C(v)) + +#define BIT_LDO2PWRCUT_8822C BIT(3) +#define BIT_VPULSE_LDO_8822C BIT(2) + +#define BIT_SHIFT_LDO_VSEL_8822C 0 +#define BIT_MASK_LDO_VSEL_8822C 0x3 +#define BIT_LDO_VSEL_8822C(x) \ + (((x) & BIT_MASK_LDO_VSEL_8822C) << BIT_SHIFT_LDO_VSEL_8822C) +#define BITS_LDO_VSEL_8822C \ + (BIT_MASK_LDO_VSEL_8822C << BIT_SHIFT_LDO_VSEL_8822C) +#define BIT_CLEAR_LDO_VSEL_8822C(x) ((x) & (~BITS_LDO_VSEL_8822C)) +#define BIT_GET_LDO_VSEL_8822C(x) \ + (((x) >> BIT_SHIFT_LDO_VSEL_8822C) & BIT_MASK_LDO_VSEL_8822C) +#define BIT_SET_LDO_VSEL_8822C(x, v) \ + (BIT_CLEAR_LDO_VSEL_8822C(x) | BIT_LDO_VSEL_8822C(v)) + +/* 2 REG_ANAPAR_MAC_1_8822C */ + +#define BIT_SHIFT_REG_CK_MON_SEL_8822C 29 +#define BIT_MASK_REG_CK_MON_SEL_8822C 0x7 +#define BIT_REG_CK_MON_SEL_8822C(x) \ + (((x) & BIT_MASK_REG_CK_MON_SEL_8822C) \ + << BIT_SHIFT_REG_CK_MON_SEL_8822C) +#define BITS_REG_CK_MON_SEL_8822C \ + (BIT_MASK_REG_CK_MON_SEL_8822C << BIT_SHIFT_REG_CK_MON_SEL_8822C) +#define BIT_CLEAR_REG_CK_MON_SEL_8822C(x) ((x) & (~BITS_REG_CK_MON_SEL_8822C)) +#define BIT_GET_REG_CK_MON_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_REG_CK_MON_SEL_8822C) & \ + BIT_MASK_REG_CK_MON_SEL_8822C) +#define BIT_SET_REG_CK_MON_SEL_8822C(x, v) \ + (BIT_CLEAR_REG_CK_MON_SEL_8822C(x) | BIT_REG_CK_MON_SEL_8822C(v)) + +#define BIT_REG_CK_MON_EN_8822C BIT(28) +#define BIT_REG_XTAL_FREQ_SEL_8822C BIT(27) +#define BIT_REG_XTAL_EDGE_SEL_8822C BIT(26) +#define BIT_REG_VCO_KVCO_8822C BIT(25) +#define BIT_REG_SDM_EDGE_SEL_8822C BIT(24) +#define BIT_REG_SDM_CK_SEL_8822C BIT(23) +#define BIT_REG_SDM_CK_GATED_8822C BIT(22) +#define BIT_REG_PFD_RESET_GATED_8822C BIT(21) + +#define BIT_SHIFT_REG_LPF_R3_FAST_8822C 16 +#define BIT_MASK_REG_LPF_R3_FAST_8822C 0x1f +#define BIT_REG_LPF_R3_FAST_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_R3_FAST_8822C) \ + << BIT_SHIFT_REG_LPF_R3_FAST_8822C) +#define BITS_REG_LPF_R3_FAST_8822C \ + (BIT_MASK_REG_LPF_R3_FAST_8822C << BIT_SHIFT_REG_LPF_R3_FAST_8822C) +#define BIT_CLEAR_REG_LPF_R3_FAST_8822C(x) ((x) & (~BITS_REG_LPF_R3_FAST_8822C)) +#define BIT_GET_REG_LPF_R3_FAST_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R3_FAST_8822C) & \ + BIT_MASK_REG_LPF_R3_FAST_8822C) +#define BIT_SET_REG_LPF_R3_FAST_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_R3_FAST_8822C(x) | BIT_REG_LPF_R3_FAST_8822C(v)) + +#define BIT_SHIFT_REG_LPF_R2_FAST_8822C 11 +#define BIT_MASK_REG_LPF_R2_FAST_8822C 0x1f +#define BIT_REG_LPF_R2_FAST_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_R2_FAST_8822C) \ + << BIT_SHIFT_REG_LPF_R2_FAST_8822C) +#define BITS_REG_LPF_R2_FAST_8822C \ + (BIT_MASK_REG_LPF_R2_FAST_8822C << BIT_SHIFT_REG_LPF_R2_FAST_8822C) +#define BIT_CLEAR_REG_LPF_R2_FAST_8822C(x) ((x) & (~BITS_REG_LPF_R2_FAST_8822C)) +#define BIT_GET_REG_LPF_R2_FAST_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R2_FAST_8822C) & \ + BIT_MASK_REG_LPF_R2_FAST_8822C) +#define BIT_SET_REG_LPF_R2_FAST_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_R2_FAST_8822C(x) | BIT_REG_LPF_R2_FAST_8822C(v)) + +#define BIT_SHIFT_REG_LPF_C3_FAST_8822C 8 +#define BIT_MASK_REG_LPF_C3_FAST_8822C 0x7 +#define BIT_REG_LPF_C3_FAST_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_C3_FAST_8822C) \ + << BIT_SHIFT_REG_LPF_C3_FAST_8822C) +#define BITS_REG_LPF_C3_FAST_8822C \ + (BIT_MASK_REG_LPF_C3_FAST_8822C << BIT_SHIFT_REG_LPF_C3_FAST_8822C) +#define BIT_CLEAR_REG_LPF_C3_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C3_FAST_8822C)) +#define BIT_GET_REG_LPF_C3_FAST_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C3_FAST_8822C) & \ + BIT_MASK_REG_LPF_C3_FAST_8822C) +#define BIT_SET_REG_LPF_C3_FAST_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_C3_FAST_8822C(x) | BIT_REG_LPF_C3_FAST_8822C(v)) + +#define BIT_SHIFT_REG_LPF_C2_FAST_8822C 5 +#define BIT_MASK_REG_LPF_C2_FAST_8822C 0x7 +#define BIT_REG_LPF_C2_FAST_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_C2_FAST_8822C) \ + << BIT_SHIFT_REG_LPF_C2_FAST_8822C) +#define BITS_REG_LPF_C2_FAST_8822C \ + (BIT_MASK_REG_LPF_C2_FAST_8822C << BIT_SHIFT_REG_LPF_C2_FAST_8822C) +#define BIT_CLEAR_REG_LPF_C2_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C2_FAST_8822C)) +#define BIT_GET_REG_LPF_C2_FAST_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C2_FAST_8822C) & \ + BIT_MASK_REG_LPF_C2_FAST_8822C) +#define BIT_SET_REG_LPF_C2_FAST_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_C2_FAST_8822C(x) | BIT_REG_LPF_C2_FAST_8822C(v)) + +#define BIT_SHIFT_REG_LPF_C1_FAST_8822C 2 +#define BIT_MASK_REG_LPF_C1_FAST_8822C 0x7 +#define BIT_REG_LPF_C1_FAST_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_C1_FAST_8822C) \ + << BIT_SHIFT_REG_LPF_C1_FAST_8822C) +#define BITS_REG_LPF_C1_FAST_8822C \ + (BIT_MASK_REG_LPF_C1_FAST_8822C << BIT_SHIFT_REG_LPF_C1_FAST_8822C) +#define BIT_CLEAR_REG_LPF_C1_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C1_FAST_8822C)) +#define BIT_GET_REG_LPF_C1_FAST_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C1_FAST_8822C) & \ + BIT_MASK_REG_LPF_C1_FAST_8822C) +#define BIT_SET_REG_LPF_C1_FAST_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_C1_FAST_8822C(x) | BIT_REG_LPF_C1_FAST_8822C(v)) + +#define BIT_SHIFT_REG_LPF_R3_V1_8822C 0 +#define BIT_MASK_REG_LPF_R3_V1_8822C 0x3 +#define BIT_REG_LPF_R3_V1_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_R3_V1_8822C) << BIT_SHIFT_REG_LPF_R3_V1_8822C) +#define BITS_REG_LPF_R3_V1_8822C \ + (BIT_MASK_REG_LPF_R3_V1_8822C << BIT_SHIFT_REG_LPF_R3_V1_8822C) +#define BIT_CLEAR_REG_LPF_R3_V1_8822C(x) ((x) & (~BITS_REG_LPF_R3_V1_8822C)) +#define BIT_GET_REG_LPF_R3_V1_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R3_V1_8822C) & BIT_MASK_REG_LPF_R3_V1_8822C) +#define BIT_SET_REG_LPF_R3_V1_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_R3_V1_8822C(x) | BIT_REG_LPF_R3_V1_8822C(v)) + +/* 2 REG_ANAPAR_MAC_2_8822C */ + +#define BIT_SHIFT_AGPIO_DRV_V1_8822C 30 +#define BIT_MASK_AGPIO_DRV_V1_8822C 0x3 +#define BIT_AGPIO_DRV_V1_8822C(x) \ + (((x) & BIT_MASK_AGPIO_DRV_V1_8822C) << BIT_SHIFT_AGPIO_DRV_V1_8822C) +#define BITS_AGPIO_DRV_V1_8822C \ + (BIT_MASK_AGPIO_DRV_V1_8822C << BIT_SHIFT_AGPIO_DRV_V1_8822C) +#define BIT_CLEAR_AGPIO_DRV_V1_8822C(x) ((x) & (~BITS_AGPIO_DRV_V1_8822C)) +#define BIT_GET_AGPIO_DRV_V1_8822C(x) \ + (((x) >> BIT_SHIFT_AGPIO_DRV_V1_8822C) & BIT_MASK_AGPIO_DRV_V1_8822C) +#define BIT_SET_AGPIO_DRV_V1_8822C(x, v) \ + (BIT_CLEAR_AGPIO_DRV_V1_8822C(x) | BIT_AGPIO_DRV_V1_8822C(v)) + +#define BIT_AGPIO_GPO_V1_8822C BIT(29) +#define BIT_AGPIO_GPE_V1_8822C BIT(28) +#define BIT_SEL_CLK_8822C BIT(27) + +#define BIT_SHIFT_LS_XTAL_SEL_8822C 23 +#define BIT_MASK_LS_XTAL_SEL_8822C 0xf +#define BIT_LS_XTAL_SEL_8822C(x) \ + (((x) & BIT_MASK_LS_XTAL_SEL_8822C) << BIT_SHIFT_LS_XTAL_SEL_8822C) +#define BITS_LS_XTAL_SEL_8822C \ + (BIT_MASK_LS_XTAL_SEL_8822C << BIT_SHIFT_LS_XTAL_SEL_8822C) +#define BIT_CLEAR_LS_XTAL_SEL_8822C(x) ((x) & (~BITS_LS_XTAL_SEL_8822C)) +#define BIT_GET_LS_XTAL_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_LS_XTAL_SEL_8822C) & BIT_MASK_LS_XTAL_SEL_8822C) +#define BIT_SET_LS_XTAL_SEL_8822C(x, v) \ + (BIT_CLEAR_LS_XTAL_SEL_8822C(x) | BIT_LS_XTAL_SEL_8822C(v)) + +#define BIT_LS_SDM_ORDER_V1_8822C BIT(22) +#define BIT_LS_DELAY_PH_8822C BIT(21) +#define BIT_DIVIDER_SEL_8822C BIT(20) + +#define BIT_SHIFT_PCODE_8822C 15 +#define BIT_MASK_PCODE_8822C 0x1f +#define BIT_PCODE_8822C(x) \ + (((x) & BIT_MASK_PCODE_8822C) << BIT_SHIFT_PCODE_8822C) +#define BITS_PCODE_8822C (BIT_MASK_PCODE_8822C << BIT_SHIFT_PCODE_8822C) +#define BIT_CLEAR_PCODE_8822C(x) ((x) & (~BITS_PCODE_8822C)) +#define BIT_GET_PCODE_8822C(x) \ + (((x) >> BIT_SHIFT_PCODE_8822C) & BIT_MASK_PCODE_8822C) +#define BIT_SET_PCODE_8822C(x, v) \ + (BIT_CLEAR_PCODE_8822C(x) | BIT_PCODE_8822C(v)) + +#define BIT_SHIFT_NCODE_8822C 7 +#define BIT_MASK_NCODE_8822C 0xff +#define BIT_NCODE_8822C(x) \ + (((x) & BIT_MASK_NCODE_8822C) << BIT_SHIFT_NCODE_8822C) +#define BITS_NCODE_8822C (BIT_MASK_NCODE_8822C << BIT_SHIFT_NCODE_8822C) +#define BIT_CLEAR_NCODE_8822C(x) ((x) & (~BITS_NCODE_8822C)) +#define BIT_GET_NCODE_8822C(x) \ + (((x) >> BIT_SHIFT_NCODE_8822C) & BIT_MASK_NCODE_8822C) +#define BIT_SET_NCODE_8822C(x, v) \ + (BIT_CLEAR_NCODE_8822C(x) | BIT_NCODE_8822C(v)) + +#define BIT_REG_BEACON_8822C BIT(6) +#define BIT_REG_MBIASE_8822C BIT(5) + +#define BIT_SHIFT_REG_FAST_SEL_8822C 3 +#define BIT_MASK_REG_FAST_SEL_8822C 0x3 +#define BIT_REG_FAST_SEL_8822C(x) \ + (((x) & BIT_MASK_REG_FAST_SEL_8822C) << BIT_SHIFT_REG_FAST_SEL_8822C) +#define BITS_REG_FAST_SEL_8822C \ + (BIT_MASK_REG_FAST_SEL_8822C << BIT_SHIFT_REG_FAST_SEL_8822C) +#define BIT_CLEAR_REG_FAST_SEL_8822C(x) ((x) & (~BITS_REG_FAST_SEL_8822C)) +#define BIT_GET_REG_FAST_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_REG_FAST_SEL_8822C) & BIT_MASK_REG_FAST_SEL_8822C) +#define BIT_SET_REG_FAST_SEL_8822C(x, v) \ + (BIT_CLEAR_REG_FAST_SEL_8822C(x) | BIT_REG_FAST_SEL_8822C(v)) + +#define BIT_REG_CK960M_EN_8822C BIT(2) +#define BIT_REG_CK320M_EN_8822C BIT(1) +#define BIT_REG_CK_5M_EN_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ANAPAR_XTAL_0_8822C */ +#define BIT_XTAL_SC_LPS_8822C BIT(31) + +#define BIT_SHIFT_XTAL_SC_INIT_8822C 24 +#define BIT_MASK_XTAL_SC_INIT_8822C 0x7f +#define BIT_XTAL_SC_INIT_8822C(x) \ + (((x) & BIT_MASK_XTAL_SC_INIT_8822C) << BIT_SHIFT_XTAL_SC_INIT_8822C) +#define BITS_XTAL_SC_INIT_8822C \ + (BIT_MASK_XTAL_SC_INIT_8822C << BIT_SHIFT_XTAL_SC_INIT_8822C) +#define BIT_CLEAR_XTAL_SC_INIT_8822C(x) ((x) & (~BITS_XTAL_SC_INIT_8822C)) +#define BIT_GET_XTAL_SC_INIT_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_INIT_8822C) & BIT_MASK_XTAL_SC_INIT_8822C) +#define BIT_SET_XTAL_SC_INIT_8822C(x, v) \ + (BIT_CLEAR_XTAL_SC_INIT_8822C(x) | BIT_XTAL_SC_INIT_8822C(v)) + +#define BIT_SHIFT_XTAL_SC_XO_8822C 17 +#define BIT_MASK_XTAL_SC_XO_8822C 0x7f +#define BIT_XTAL_SC_XO_8822C(x) \ + (((x) & BIT_MASK_XTAL_SC_XO_8822C) << BIT_SHIFT_XTAL_SC_XO_8822C) +#define BITS_XTAL_SC_XO_8822C \ + (BIT_MASK_XTAL_SC_XO_8822C << BIT_SHIFT_XTAL_SC_XO_8822C) +#define BIT_CLEAR_XTAL_SC_XO_8822C(x) ((x) & (~BITS_XTAL_SC_XO_8822C)) +#define BIT_GET_XTAL_SC_XO_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XO_8822C) & BIT_MASK_XTAL_SC_XO_8822C) +#define BIT_SET_XTAL_SC_XO_8822C(x, v) \ + (BIT_CLEAR_XTAL_SC_XO_8822C(x) | BIT_XTAL_SC_XO_8822C(v)) + +#define BIT_SHIFT_XTAL_SC_XI_8822C 10 +#define BIT_MASK_XTAL_SC_XI_8822C 0x7f +#define BIT_XTAL_SC_XI_8822C(x) \ + (((x) & BIT_MASK_XTAL_SC_XI_8822C) << BIT_SHIFT_XTAL_SC_XI_8822C) +#define BITS_XTAL_SC_XI_8822C \ + (BIT_MASK_XTAL_SC_XI_8822C << BIT_SHIFT_XTAL_SC_XI_8822C) +#define BIT_CLEAR_XTAL_SC_XI_8822C(x) ((x) & (~BITS_XTAL_SC_XI_8822C)) +#define BIT_GET_XTAL_SC_XI_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XI_8822C) & BIT_MASK_XTAL_SC_XI_8822C) +#define BIT_SET_XTAL_SC_XI_8822C(x, v) \ + (BIT_CLEAR_XTAL_SC_XI_8822C(x) | BIT_XTAL_SC_XI_8822C(v)) + +#define BIT_SHIFT_XTAL_GMN_V3_8822C 5 +#define BIT_MASK_XTAL_GMN_V3_8822C 0x1f +#define BIT_XTAL_GMN_V3_8822C(x) \ + (((x) & BIT_MASK_XTAL_GMN_V3_8822C) << BIT_SHIFT_XTAL_GMN_V3_8822C) +#define BITS_XTAL_GMN_V3_8822C \ + (BIT_MASK_XTAL_GMN_V3_8822C << BIT_SHIFT_XTAL_GMN_V3_8822C) +#define BIT_CLEAR_XTAL_GMN_V3_8822C(x) ((x) & (~BITS_XTAL_GMN_V3_8822C)) +#define BIT_GET_XTAL_GMN_V3_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V3_8822C) & BIT_MASK_XTAL_GMN_V3_8822C) +#define BIT_SET_XTAL_GMN_V3_8822C(x, v) \ + (BIT_CLEAR_XTAL_GMN_V3_8822C(x) | BIT_XTAL_GMN_V3_8822C(v)) + +#define BIT_SHIFT_XTAL_GMP_V3_8822C 0 +#define BIT_MASK_XTAL_GMP_V3_8822C 0x1f +#define BIT_XTAL_GMP_V3_8822C(x) \ + (((x) & BIT_MASK_XTAL_GMP_V3_8822C) << BIT_SHIFT_XTAL_GMP_V3_8822C) +#define BITS_XTAL_GMP_V3_8822C \ + (BIT_MASK_XTAL_GMP_V3_8822C << BIT_SHIFT_XTAL_GMP_V3_8822C) +#define BIT_CLEAR_XTAL_GMP_V3_8822C(x) ((x) & (~BITS_XTAL_GMP_V3_8822C)) +#define BIT_GET_XTAL_GMP_V3_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V3_8822C) & BIT_MASK_XTAL_GMP_V3_8822C) +#define BIT_SET_XTAL_GMP_V3_8822C(x, v) \ + (BIT_CLEAR_XTAL_GMP_V3_8822C(x) | BIT_XTAL_GMP_V3_8822C(v)) + +/* 2 REG_ANAPAR_XTAL_1_8822C */ +#define BIT_XTAL_SEL_TOK_V1_8822C BIT(31) +#define BIT_XTAL_DELAY_DIGI_V2_8822C BIT(30) +#define BIT_XTAL_DELAY_USB_V2_8822C BIT(29) +#define BIT_XTAL_DELAY_AFE_V2_8822C BIT(28) + +#define BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C 26 +#define BIT_MASK_XTAL_DRV_DIGI_V2_8822C 0x3 +#define BIT_XTAL_DRV_DIGI_V2_8822C(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_V2_8822C) \ + << BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C) +#define BITS_XTAL_DRV_DIGI_V2_8822C \ + (BIT_MASK_XTAL_DRV_DIGI_V2_8822C << BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C) +#define BIT_CLEAR_XTAL_DRV_DIGI_V2_8822C(x) \ + ((x) & (~BITS_XTAL_DRV_DIGI_V2_8822C)) +#define BIT_GET_XTAL_DRV_DIGI_V2_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C) & \ + BIT_MASK_XTAL_DRV_DIGI_V2_8822C) +#define BIT_SET_XTAL_DRV_DIGI_V2_8822C(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_V2_8822C(x) | BIT_XTAL_DRV_DIGI_V2_8822C(v)) + +#define BIT_EN_XTAL_DRV_LPS_8822C BIT(25) +#define BIT_EN_XTAL_DRV_DIGI_V2_8822C BIT(24) + +#define BIT_SHIFT_XTAL_DRV_USB_8822C 22 +#define BIT_MASK_XTAL_DRV_USB_8822C 0x3 +#define BIT_XTAL_DRV_USB_8822C(x) \ + (((x) & BIT_MASK_XTAL_DRV_USB_8822C) << BIT_SHIFT_XTAL_DRV_USB_8822C) +#define BITS_XTAL_DRV_USB_8822C \ + (BIT_MASK_XTAL_DRV_USB_8822C << BIT_SHIFT_XTAL_DRV_USB_8822C) +#define BIT_CLEAR_XTAL_DRV_USB_8822C(x) ((x) & (~BITS_XTAL_DRV_USB_8822C)) +#define BIT_GET_XTAL_DRV_USB_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_USB_8822C) & BIT_MASK_XTAL_DRV_USB_8822C) +#define BIT_SET_XTAL_DRV_USB_8822C(x, v) \ + (BIT_CLEAR_XTAL_DRV_USB_8822C(x) | BIT_XTAL_DRV_USB_8822C(v)) + +#define BIT_EN_XTAL_DRV_USB_8822C BIT(21) + +#define BIT_SHIFT_XTAL_DRV_AFE_V2_8822C 19 +#define BIT_MASK_XTAL_DRV_AFE_V2_8822C 0x3 +#define BIT_XTAL_DRV_AFE_V2_8822C(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_V2_8822C) \ + << BIT_SHIFT_XTAL_DRV_AFE_V2_8822C) +#define BITS_XTAL_DRV_AFE_V2_8822C \ + (BIT_MASK_XTAL_DRV_AFE_V2_8822C << BIT_SHIFT_XTAL_DRV_AFE_V2_8822C) +#define BIT_CLEAR_XTAL_DRV_AFE_V2_8822C(x) ((x) & (~BITS_XTAL_DRV_AFE_V2_8822C)) +#define BIT_GET_XTAL_DRV_AFE_V2_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_V2_8822C) & \ + BIT_MASK_XTAL_DRV_AFE_V2_8822C) +#define BIT_SET_XTAL_DRV_AFE_V2_8822C(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_V2_8822C(x) | BIT_XTAL_DRV_AFE_V2_8822C(v)) + +#define BIT_EN_XTAL_DRV_AFE_8822C BIT(18) + +#define BIT_SHIFT_XTAL_DRV_RF2_V2_8822C 16 +#define BIT_MASK_XTAL_DRV_RF2_V2_8822C 0x3 +#define BIT_XTAL_DRV_RF2_V2_8822C(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_V2_8822C) \ + << BIT_SHIFT_XTAL_DRV_RF2_V2_8822C) +#define BITS_XTAL_DRV_RF2_V2_8822C \ + (BIT_MASK_XTAL_DRV_RF2_V2_8822C << BIT_SHIFT_XTAL_DRV_RF2_V2_8822C) +#define BIT_CLEAR_XTAL_DRV_RF2_V2_8822C(x) ((x) & (~BITS_XTAL_DRV_RF2_V2_8822C)) +#define BIT_GET_XTAL_DRV_RF2_V2_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_V2_8822C) & \ + BIT_MASK_XTAL_DRV_RF2_V2_8822C) +#define BIT_SET_XTAL_DRV_RF2_V2_8822C(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_V2_8822C(x) | BIT_XTAL_DRV_RF2_V2_8822C(v)) + +#define BIT_EN_XTAL_DRV_RF2_8822C BIT(15) + +#define BIT_SHIFT_XTAL_DRV_RF1_8822C 13 +#define BIT_MASK_XTAL_DRV_RF1_8822C 0x3 +#define BIT_XTAL_DRV_RF1_8822C(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF1_8822C) << BIT_SHIFT_XTAL_DRV_RF1_8822C) +#define BITS_XTAL_DRV_RF1_8822C \ + (BIT_MASK_XTAL_DRV_RF1_8822C << BIT_SHIFT_XTAL_DRV_RF1_8822C) +#define BIT_CLEAR_XTAL_DRV_RF1_8822C(x) ((x) & (~BITS_XTAL_DRV_RF1_8822C)) +#define BIT_GET_XTAL_DRV_RF1_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822C) & BIT_MASK_XTAL_DRV_RF1_8822C) +#define BIT_SET_XTAL_DRV_RF1_8822C(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF1_8822C(x) | BIT_XTAL_DRV_RF1_8822C(v)) + +#define BIT_EN_XTAL_DRV_RF1_8822C BIT(12) +#define BIT_XTAL_DRV_RF_LATCH_V4_8822C BIT(11) +#define BIT_XTAL_GM_SEP_V3_8822C BIT(10) +#define BIT_XQSEL_RF_AWAKE_V3_8822C BIT(9) +#define BIT_XQSEL_RF_INITIAL_V3_8822C BIT(8) +#define BIT_XQSEL_V2_8822C BIT(7) +#define BIT_GATED_XTAL_OK0_V2_8822C BIT(6) + +#define BIT_SHIFT_XTAL_SC_LPS_V2_8822C 0 +#define BIT_MASK_XTAL_SC_LPS_V2_8822C 0x3f +#define BIT_XTAL_SC_LPS_V2_8822C(x) \ + (((x) & BIT_MASK_XTAL_SC_LPS_V2_8822C) \ + << BIT_SHIFT_XTAL_SC_LPS_V2_8822C) +#define BITS_XTAL_SC_LPS_V2_8822C \ + (BIT_MASK_XTAL_SC_LPS_V2_8822C << BIT_SHIFT_XTAL_SC_LPS_V2_8822C) +#define BIT_CLEAR_XTAL_SC_LPS_V2_8822C(x) ((x) & (~BITS_XTAL_SC_LPS_V2_8822C)) +#define BIT_GET_XTAL_SC_LPS_V2_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_LPS_V2_8822C) & \ + BIT_MASK_XTAL_SC_LPS_V2_8822C) +#define BIT_SET_XTAL_SC_LPS_V2_8822C(x, v) \ + (BIT_CLEAR_XTAL_SC_LPS_V2_8822C(x) | BIT_XTAL_SC_LPS_V2_8822C(v)) + +/* 2 REG_ANAPAR_XTAL_2_8822C */ +#define BIT_XTAL_AAC_CAP_8822C BIT(31) + +#define BIT_SHIFT_XTAL_PDSW_8822C 29 +#define BIT_MASK_XTAL_PDSW_8822C 0x3 +#define BIT_XTAL_PDSW_8822C(x) \ + (((x) & BIT_MASK_XTAL_PDSW_8822C) << BIT_SHIFT_XTAL_PDSW_8822C) +#define BITS_XTAL_PDSW_8822C \ + (BIT_MASK_XTAL_PDSW_8822C << BIT_SHIFT_XTAL_PDSW_8822C) +#define BIT_CLEAR_XTAL_PDSW_8822C(x) ((x) & (~BITS_XTAL_PDSW_8822C)) +#define BIT_GET_XTAL_PDSW_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_PDSW_8822C) & BIT_MASK_XTAL_PDSW_8822C) +#define BIT_SET_XTAL_PDSW_8822C(x, v) \ + (BIT_CLEAR_XTAL_PDSW_8822C(x) | BIT_XTAL_PDSW_8822C(v)) + +#define BIT_SHIFT_XTAL_LPS_BUF_VB_8822C 27 +#define BIT_MASK_XTAL_LPS_BUF_VB_8822C 0x3 +#define BIT_XTAL_LPS_BUF_VB_8822C(x) \ + (((x) & BIT_MASK_XTAL_LPS_BUF_VB_8822C) \ + << BIT_SHIFT_XTAL_LPS_BUF_VB_8822C) +#define BITS_XTAL_LPS_BUF_VB_8822C \ + (BIT_MASK_XTAL_LPS_BUF_VB_8822C << BIT_SHIFT_XTAL_LPS_BUF_VB_8822C) +#define BIT_CLEAR_XTAL_LPS_BUF_VB_8822C(x) ((x) & (~BITS_XTAL_LPS_BUF_VB_8822C)) +#define BIT_GET_XTAL_LPS_BUF_VB_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_LPS_BUF_VB_8822C) & \ + BIT_MASK_XTAL_LPS_BUF_VB_8822C) +#define BIT_SET_XTAL_LPS_BUF_VB_8822C(x, v) \ + (BIT_CLEAR_XTAL_LPS_BUF_VB_8822C(x) | BIT_XTAL_LPS_BUF_VB_8822C(v)) + +#define BIT_XTAL_PDCK_MANU_8822C BIT(26) +#define BIT_XTAL_PDCK_OK_MANU_8822C BIT(25) + +#define BIT_SHIFT_XTAL_VREF_SEL_8822C 20 +#define BIT_MASK_XTAL_VREF_SEL_8822C 0x1f +#define BIT_XTAL_VREF_SEL_8822C(x) \ + (((x) & BIT_MASK_XTAL_VREF_SEL_8822C) << BIT_SHIFT_XTAL_VREF_SEL_8822C) +#define BITS_XTAL_VREF_SEL_8822C \ + (BIT_MASK_XTAL_VREF_SEL_8822C << BIT_SHIFT_XTAL_VREF_SEL_8822C) +#define BIT_CLEAR_XTAL_VREF_SEL_8822C(x) ((x) & (~BITS_XTAL_VREF_SEL_8822C)) +#define BIT_GET_XTAL_VREF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_VREF_SEL_8822C) & BIT_MASK_XTAL_VREF_SEL_8822C) +#define BIT_SET_XTAL_VREF_SEL_8822C(x, v) \ + (BIT_CLEAR_XTAL_VREF_SEL_8822C(x) | BIT_XTAL_VREF_SEL_8822C(v)) + +#define BIT_EN_XTAL_PDCK_VREF_8822C BIT(19) +#define BIT_XTAL_SEL_PWR_V1_8822C BIT(18) +#define BIT_XTAL_LPS_DIVISOR_8822C BIT(17) +#define BIT_XTAL_CKDIGI_SEL_8822C BIT(16) +#define BIT_EN_XTAL_LPS_CLK_8822C BIT(15) +#define BIT_EN_XTAL_SCHMITT_8822C BIT(14) +#define BIT_XTAL_PK_SEL_OFFSET_8822C BIT(13) + +#define BIT_SHIFT_XTAL_MANU_PK_SEL_8822C 11 +#define BIT_MASK_XTAL_MANU_PK_SEL_8822C 0x3 +#define BIT_XTAL_MANU_PK_SEL_8822C(x) \ + (((x) & BIT_MASK_XTAL_MANU_PK_SEL_8822C) \ + << BIT_SHIFT_XTAL_MANU_PK_SEL_8822C) +#define BITS_XTAL_MANU_PK_SEL_8822C \ + (BIT_MASK_XTAL_MANU_PK_SEL_8822C << BIT_SHIFT_XTAL_MANU_PK_SEL_8822C) +#define BIT_CLEAR_XTAL_MANU_PK_SEL_8822C(x) \ + ((x) & (~BITS_XTAL_MANU_PK_SEL_8822C)) +#define BIT_GET_XTAL_MANU_PK_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_MANU_PK_SEL_8822C) & \ + BIT_MASK_XTAL_MANU_PK_SEL_8822C) +#define BIT_SET_XTAL_MANU_PK_SEL_8822C(x, v) \ + (BIT_CLEAR_XTAL_MANU_PK_SEL_8822C(x) | BIT_XTAL_MANU_PK_SEL_8822C(v)) + +#define BIT_XTAL_AACK_PK_MANU_8822C BIT(10) +#define BIT_EN_XTAL_AAC_PKDET_V1_8822C BIT(9) +#define BIT_EN_XTAL_AAC_GM_V1_8822C BIT(8) +#define BIT_XTAL_LDO_OPVB_SEL_8822C BIT(7) +#define BIT_XTAL_LDO_NC_8822C BIT(6) + +#define BIT_SHIFT_XTAL_LDO_VREF_V2_8822C 3 +#define BIT_MASK_XTAL_LDO_VREF_V2_8822C 0x7 +#define BIT_XTAL_LDO_VREF_V2_8822C(x) \ + (((x) & BIT_MASK_XTAL_LDO_VREF_V2_8822C) \ + << BIT_SHIFT_XTAL_LDO_VREF_V2_8822C) +#define BITS_XTAL_LDO_VREF_V2_8822C \ + (BIT_MASK_XTAL_LDO_VREF_V2_8822C << BIT_SHIFT_XTAL_LDO_VREF_V2_8822C) +#define BIT_CLEAR_XTAL_LDO_VREF_V2_8822C(x) \ + ((x) & (~BITS_XTAL_LDO_VREF_V2_8822C)) +#define BIT_GET_XTAL_LDO_VREF_V2_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_VREF_V2_8822C) & \ + BIT_MASK_XTAL_LDO_VREF_V2_8822C) +#define BIT_SET_XTAL_LDO_VREF_V2_8822C(x, v) \ + (BIT_CLEAR_XTAL_LDO_VREF_V2_8822C(x) | BIT_XTAL_LDO_VREF_V2_8822C(v)) + +#define BIT_XTAL_LPMODE_V1_8822C BIT(2) + +#define BIT_SHIFT_XTAL_SEL_TOK_V3_8822C 0 +#define BIT_MASK_XTAL_SEL_TOK_V3_8822C 0x3 +#define BIT_XTAL_SEL_TOK_V3_8822C(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_V3_8822C) \ + << BIT_SHIFT_XTAL_SEL_TOK_V3_8822C) +#define BITS_XTAL_SEL_TOK_V3_8822C \ + (BIT_MASK_XTAL_SEL_TOK_V3_8822C << BIT_SHIFT_XTAL_SEL_TOK_V3_8822C) +#define BIT_CLEAR_XTAL_SEL_TOK_V3_8822C(x) ((x) & (~BITS_XTAL_SEL_TOK_V3_8822C)) +#define BIT_GET_XTAL_SEL_TOK_V3_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V3_8822C) & \ + BIT_MASK_XTAL_SEL_TOK_V3_8822C) +#define BIT_SET_XTAL_SEL_TOK_V3_8822C(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_V3_8822C(x) | BIT_XTAL_SEL_TOK_V3_8822C(v)) + +/* 2 REG_ANAPAR_XTAL_3_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_XTAL_DUMMY_V1_8822C 7 +#define BIT_MASK_XTAL_DUMMY_V1_8822C 0x3f +#define BIT_XTAL_DUMMY_V1_8822C(x) \ + (((x) & BIT_MASK_XTAL_DUMMY_V1_8822C) << BIT_SHIFT_XTAL_DUMMY_V1_8822C) +#define BITS_XTAL_DUMMY_V1_8822C \ + (BIT_MASK_XTAL_DUMMY_V1_8822C << BIT_SHIFT_XTAL_DUMMY_V1_8822C) +#define BIT_CLEAR_XTAL_DUMMY_V1_8822C(x) ((x) & (~BITS_XTAL_DUMMY_V1_8822C)) +#define BIT_GET_XTAL_DUMMY_V1_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_DUMMY_V1_8822C) & BIT_MASK_XTAL_DUMMY_V1_8822C) +#define BIT_SET_XTAL_DUMMY_V1_8822C(x, v) \ + (BIT_CLEAR_XTAL_DUMMY_V1_8822C(x) | BIT_XTAL_DUMMY_V1_8822C(v)) + +#define BIT_XTAL_EN_LNBUF_8822C BIT(6) +#define BIT_XTAL__AAC_TIE_MID_8822C BIT(5) + +#define BIT_SHIFT_XTAL_AAC_OPCUR_8822C 3 +#define BIT_MASK_XTAL_AAC_OPCUR_8822C 0x3 +#define BIT_XTAL_AAC_OPCUR_8822C(x) \ + (((x) & BIT_MASK_XTAL_AAC_OPCUR_8822C) \ + << BIT_SHIFT_XTAL_AAC_OPCUR_8822C) +#define BITS_XTAL_AAC_OPCUR_8822C \ + (BIT_MASK_XTAL_AAC_OPCUR_8822C << BIT_SHIFT_XTAL_AAC_OPCUR_8822C) +#define BIT_CLEAR_XTAL_AAC_OPCUR_8822C(x) ((x) & (~BITS_XTAL_AAC_OPCUR_8822C)) +#define BIT_GET_XTAL_AAC_OPCUR_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_AAC_OPCUR_8822C) & \ + BIT_MASK_XTAL_AAC_OPCUR_8822C) +#define BIT_SET_XTAL_AAC_OPCUR_8822C(x, v) \ + (BIT_CLEAR_XTAL_AAC_OPCUR_8822C(x) | BIT_XTAL_AAC_OPCUR_8822C(v)) + +#define BIT_SHIFT_XTAL_AAC_IOFFSET_8822C 1 +#define BIT_MASK_XTAL_AAC_IOFFSET_8822C 0x3 +#define BIT_XTAL_AAC_IOFFSET_8822C(x) \ + (((x) & BIT_MASK_XTAL_AAC_IOFFSET_8822C) \ + << BIT_SHIFT_XTAL_AAC_IOFFSET_8822C) +#define BITS_XTAL_AAC_IOFFSET_8822C \ + (BIT_MASK_XTAL_AAC_IOFFSET_8822C << BIT_SHIFT_XTAL_AAC_IOFFSET_8822C) +#define BIT_CLEAR_XTAL_AAC_IOFFSET_8822C(x) \ + ((x) & (~BITS_XTAL_AAC_IOFFSET_8822C)) +#define BIT_GET_XTAL_AAC_IOFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_AAC_IOFFSET_8822C) & \ + BIT_MASK_XTAL_AAC_IOFFSET_8822C) +#define BIT_SET_XTAL_AAC_IOFFSET_8822C(x, v) \ + (BIT_CLEAR_XTAL_AAC_IOFFSET_8822C(x) | BIT_XTAL_AAC_IOFFSET_8822C(v)) + +#define BIT_XTAL_AAC_CAP_V1_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ANAPAR_XTAL_AACK_0_8822C */ +#define BIT_XAAC_LPOW_8822C BIT(31) + +#define BIT_SHIFT_AAC_MODE_8822C 29 +#define BIT_MASK_AAC_MODE_8822C 0x3 +#define BIT_AAC_MODE_8822C(x) \ + (((x) & BIT_MASK_AAC_MODE_8822C) << BIT_SHIFT_AAC_MODE_8822C) +#define BITS_AAC_MODE_8822C \ + (BIT_MASK_AAC_MODE_8822C << BIT_SHIFT_AAC_MODE_8822C) +#define BIT_CLEAR_AAC_MODE_8822C(x) ((x) & (~BITS_AAC_MODE_8822C)) +#define BIT_GET_AAC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_AAC_MODE_8822C) & BIT_MASK_AAC_MODE_8822C) +#define BIT_SET_AAC_MODE_8822C(x, v) \ + (BIT_CLEAR_AAC_MODE_8822C(x) | BIT_AAC_MODE_8822C(v)) + +#define BIT_EN_XTAL_AAC_TRIG_8822C BIT(28) +#define BIT_EN_XTAL_AAC_8822C BIT(27) +#define BIT_EN_XTAL_AAC_DIGI_8822C BIT(26) + +#define BIT_SHIFT_GM_MANUAL_8822C 21 +#define BIT_MASK_GM_MANUAL_8822C 0x1f +#define BIT_GM_MANUAL_8822C(x) \ + (((x) & BIT_MASK_GM_MANUAL_8822C) << BIT_SHIFT_GM_MANUAL_8822C) +#define BITS_GM_MANUAL_8822C \ + (BIT_MASK_GM_MANUAL_8822C << BIT_SHIFT_GM_MANUAL_8822C) +#define BIT_CLEAR_GM_MANUAL_8822C(x) ((x) & (~BITS_GM_MANUAL_8822C)) +#define BIT_GET_GM_MANUAL_8822C(x) \ + (((x) >> BIT_SHIFT_GM_MANUAL_8822C) & BIT_MASK_GM_MANUAL_8822C) +#define BIT_SET_GM_MANUAL_8822C(x, v) \ + (BIT_CLEAR_GM_MANUAL_8822C(x) | BIT_GM_MANUAL_8822C(v)) + +#define BIT_SHIFT_GM_STUP_8822C 16 +#define BIT_MASK_GM_STUP_8822C 0x1f +#define BIT_GM_STUP_8822C(x) \ + (((x) & BIT_MASK_GM_STUP_8822C) << BIT_SHIFT_GM_STUP_8822C) +#define BITS_GM_STUP_8822C (BIT_MASK_GM_STUP_8822C << BIT_SHIFT_GM_STUP_8822C) +#define BIT_CLEAR_GM_STUP_8822C(x) ((x) & (~BITS_GM_STUP_8822C)) +#define BIT_GET_GM_STUP_8822C(x) \ + (((x) >> BIT_SHIFT_GM_STUP_8822C) & BIT_MASK_GM_STUP_8822C) +#define BIT_SET_GM_STUP_8822C(x, v) \ + (BIT_CLEAR_GM_STUP_8822C(x) | BIT_GM_STUP_8822C(v)) + +#define BIT_SHIFT_XTAL_CK_SET_8822C 13 +#define BIT_MASK_XTAL_CK_SET_8822C 0x7 +#define BIT_XTAL_CK_SET_8822C(x) \ + (((x) & BIT_MASK_XTAL_CK_SET_8822C) << BIT_SHIFT_XTAL_CK_SET_8822C) +#define BITS_XTAL_CK_SET_8822C \ + (BIT_MASK_XTAL_CK_SET_8822C << BIT_SHIFT_XTAL_CK_SET_8822C) +#define BIT_CLEAR_XTAL_CK_SET_8822C(x) ((x) & (~BITS_XTAL_CK_SET_8822C)) +#define BIT_GET_XTAL_CK_SET_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_CK_SET_8822C) & BIT_MASK_XTAL_CK_SET_8822C) +#define BIT_SET_XTAL_CK_SET_8822C(x, v) \ + (BIT_CLEAR_XTAL_CK_SET_8822C(x) | BIT_XTAL_CK_SET_8822C(v)) + +#define BIT_SHIFT_GM_INIT_8822C 8 +#define BIT_MASK_GM_INIT_8822C 0x1f +#define BIT_GM_INIT_8822C(x) \ + (((x) & BIT_MASK_GM_INIT_8822C) << BIT_SHIFT_GM_INIT_8822C) +#define BITS_GM_INIT_8822C (BIT_MASK_GM_INIT_8822C << BIT_SHIFT_GM_INIT_8822C) +#define BIT_CLEAR_GM_INIT_8822C(x) ((x) & (~BITS_GM_INIT_8822C)) +#define BIT_GET_GM_INIT_8822C(x) \ + (((x) >> BIT_SHIFT_GM_INIT_8822C) & BIT_MASK_GM_INIT_8822C) +#define BIT_SET_GM_INIT_8822C(x, v) \ + (BIT_CLEAR_GM_INIT_8822C(x) | BIT_GM_INIT_8822C(v)) + +#define BIT_GM_STEP_8822C BIT(7) + +#define BIT_SHIFT_XAAC_GM_OFFSET_8822C 2 +#define BIT_MASK_XAAC_GM_OFFSET_8822C 0x1f +#define BIT_XAAC_GM_OFFSET_8822C(x) \ + (((x) & BIT_MASK_XAAC_GM_OFFSET_8822C) \ + << BIT_SHIFT_XAAC_GM_OFFSET_8822C) +#define BITS_XAAC_GM_OFFSET_8822C \ + (BIT_MASK_XAAC_GM_OFFSET_8822C << BIT_SHIFT_XAAC_GM_OFFSET_8822C) +#define BIT_CLEAR_XAAC_GM_OFFSET_8822C(x) ((x) & (~BITS_XAAC_GM_OFFSET_8822C)) +#define BIT_GET_XAAC_GM_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_XAAC_GM_OFFSET_8822C) & \ + BIT_MASK_XAAC_GM_OFFSET_8822C) +#define BIT_SET_XAAC_GM_OFFSET_8822C(x, v) \ + (BIT_CLEAR_XAAC_GM_OFFSET_8822C(x) | BIT_XAAC_GM_OFFSET_8822C(v)) + +#define BIT_OFFSET_PLUS_8822C BIT(1) +#define BIT_RESET_N_8822C BIT(0) + +/* 2 REG_ANAPAR_XTAL_AACK_1_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_PK_END_AR_8822C 3 +#define BIT_MASK_PK_END_AR_8822C 0x3 +#define BIT_PK_END_AR_8822C(x) \ + (((x) & BIT_MASK_PK_END_AR_8822C) << BIT_SHIFT_PK_END_AR_8822C) +#define BITS_PK_END_AR_8822C \ + (BIT_MASK_PK_END_AR_8822C << BIT_SHIFT_PK_END_AR_8822C) +#define BIT_CLEAR_PK_END_AR_8822C(x) ((x) & (~BITS_PK_END_AR_8822C)) +#define BIT_GET_PK_END_AR_8822C(x) \ + (((x) >> BIT_SHIFT_PK_END_AR_8822C) & BIT_MASK_PK_END_AR_8822C) +#define BIT_SET_PK_END_AR_8822C(x, v) \ + (BIT_CLEAR_PK_END_AR_8822C(x) | BIT_PK_END_AR_8822C(v)) + +#define BIT_SHIFT_PK_START_AR_8822C 1 +#define BIT_MASK_PK_START_AR_8822C 0x3 +#define BIT_PK_START_AR_8822C(x) \ + (((x) & BIT_MASK_PK_START_AR_8822C) << BIT_SHIFT_PK_START_AR_8822C) +#define BITS_PK_START_AR_8822C \ + (BIT_MASK_PK_START_AR_8822C << BIT_SHIFT_PK_START_AR_8822C) +#define BIT_CLEAR_PK_START_AR_8822C(x) ((x) & (~BITS_PK_START_AR_8822C)) +#define BIT_GET_PK_START_AR_8822C(x) \ + (((x) >> BIT_SHIFT_PK_START_AR_8822C) & BIT_MASK_PK_START_AR_8822C) +#define BIT_SET_PK_START_AR_8822C(x, v) \ + (BIT_CLEAR_PK_START_AR_8822C(x) | BIT_PK_START_AR_8822C(v)) + +#define BIT_XAAC_LUT_MANUAL_EN_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ANAPAR_XTAL_MODE_DECODER_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_XTAL_LDO_LPS_8822C 21 +#define BIT_MASK_XTAL_LDO_LPS_8822C 0x7 +#define BIT_XTAL_LDO_LPS_8822C(x) \ + (((x) & BIT_MASK_XTAL_LDO_LPS_8822C) << BIT_SHIFT_XTAL_LDO_LPS_8822C) +#define BITS_XTAL_LDO_LPS_8822C \ + (BIT_MASK_XTAL_LDO_LPS_8822C << BIT_SHIFT_XTAL_LDO_LPS_8822C) +#define BIT_CLEAR_XTAL_LDO_LPS_8822C(x) ((x) & (~BITS_XTAL_LDO_LPS_8822C)) +#define BIT_GET_XTAL_LDO_LPS_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_LPS_8822C) & BIT_MASK_XTAL_LDO_LPS_8822C) +#define BIT_SET_XTAL_LDO_LPS_8822C(x, v) \ + (BIT_CLEAR_XTAL_LDO_LPS_8822C(x) | BIT_XTAL_LDO_LPS_8822C(v)) + +#define BIT_SHIFT_XTAL_WAIT_CYC_8822C 15 +#define BIT_MASK_XTAL_WAIT_CYC_8822C 0x3f +#define BIT_XTAL_WAIT_CYC_8822C(x) \ + (((x) & BIT_MASK_XTAL_WAIT_CYC_8822C) << BIT_SHIFT_XTAL_WAIT_CYC_8822C) +#define BITS_XTAL_WAIT_CYC_8822C \ + (BIT_MASK_XTAL_WAIT_CYC_8822C << BIT_SHIFT_XTAL_WAIT_CYC_8822C) +#define BIT_CLEAR_XTAL_WAIT_CYC_8822C(x) ((x) & (~BITS_XTAL_WAIT_CYC_8822C)) +#define BIT_GET_XTAL_WAIT_CYC_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_WAIT_CYC_8822C) & BIT_MASK_XTAL_WAIT_CYC_8822C) +#define BIT_SET_XTAL_WAIT_CYC_8822C(x, v) \ + (BIT_CLEAR_XTAL_WAIT_CYC_8822C(x) | BIT_XTAL_WAIT_CYC_8822C(v)) + +#define BIT_SHIFT_XTAL_LDO_OK_8822C 12 +#define BIT_MASK_XTAL_LDO_OK_8822C 0x7 +#define BIT_XTAL_LDO_OK_8822C(x) \ + (((x) & BIT_MASK_XTAL_LDO_OK_8822C) << BIT_SHIFT_XTAL_LDO_OK_8822C) +#define BITS_XTAL_LDO_OK_8822C \ + (BIT_MASK_XTAL_LDO_OK_8822C << BIT_SHIFT_XTAL_LDO_OK_8822C) +#define BIT_CLEAR_XTAL_LDO_OK_8822C(x) ((x) & (~BITS_XTAL_LDO_OK_8822C)) +#define BIT_GET_XTAL_LDO_OK_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_OK_8822C) & BIT_MASK_XTAL_LDO_OK_8822C) +#define BIT_SET_XTAL_LDO_OK_8822C(x, v) \ + (BIT_CLEAR_XTAL_LDO_OK_8822C(x) | BIT_XTAL_LDO_OK_8822C(v)) + +#define BIT_XTAL_MD_LPOW_8822C BIT(11) + +#define BIT_SHIFT_XTAL_OV_RATIO_8822C 9 +#define BIT_MASK_XTAL_OV_RATIO_8822C 0x3 +#define BIT_XTAL_OV_RATIO_8822C(x) \ + (((x) & BIT_MASK_XTAL_OV_RATIO_8822C) << BIT_SHIFT_XTAL_OV_RATIO_8822C) +#define BITS_XTAL_OV_RATIO_8822C \ + (BIT_MASK_XTAL_OV_RATIO_8822C << BIT_SHIFT_XTAL_OV_RATIO_8822C) +#define BIT_CLEAR_XTAL_OV_RATIO_8822C(x) ((x) & (~BITS_XTAL_OV_RATIO_8822C)) +#define BIT_GET_XTAL_OV_RATIO_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_OV_RATIO_8822C) & BIT_MASK_XTAL_OV_RATIO_8822C) +#define BIT_SET_XTAL_OV_RATIO_8822C(x, v) \ + (BIT_CLEAR_XTAL_OV_RATIO_8822C(x) | BIT_XTAL_OV_RATIO_8822C(v)) + +#define BIT_SHIFT_XTAL_OV_UNIT_8822C 6 +#define BIT_MASK_XTAL_OV_UNIT_8822C 0x7 +#define BIT_XTAL_OV_UNIT_8822C(x) \ + (((x) & BIT_MASK_XTAL_OV_UNIT_8822C) << BIT_SHIFT_XTAL_OV_UNIT_8822C) +#define BITS_XTAL_OV_UNIT_8822C \ + (BIT_MASK_XTAL_OV_UNIT_8822C << BIT_SHIFT_XTAL_OV_UNIT_8822C) +#define BIT_CLEAR_XTAL_OV_UNIT_8822C(x) ((x) & (~BITS_XTAL_OV_UNIT_8822C)) +#define BIT_GET_XTAL_OV_UNIT_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_OV_UNIT_8822C) & BIT_MASK_XTAL_OV_UNIT_8822C) +#define BIT_SET_XTAL_OV_UNIT_8822C(x, v) \ + (BIT_CLEAR_XTAL_OV_UNIT_8822C(x) | BIT_XTAL_OV_UNIT_8822C(v)) + +#define BIT_SHIFT_XTAL_MODE_MANUAL_8822C 4 +#define BIT_MASK_XTAL_MODE_MANUAL_8822C 0x3 +#define BIT_XTAL_MODE_MANUAL_8822C(x) \ + (((x) & BIT_MASK_XTAL_MODE_MANUAL_8822C) \ + << BIT_SHIFT_XTAL_MODE_MANUAL_8822C) +#define BITS_XTAL_MODE_MANUAL_8822C \ + (BIT_MASK_XTAL_MODE_MANUAL_8822C << BIT_SHIFT_XTAL_MODE_MANUAL_8822C) +#define BIT_CLEAR_XTAL_MODE_MANUAL_8822C(x) \ + ((x) & (~BITS_XTAL_MODE_MANUAL_8822C)) +#define BIT_GET_XTAL_MODE_MANUAL_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_MODE_MANUAL_8822C) & \ + BIT_MASK_XTAL_MODE_MANUAL_8822C) +#define BIT_SET_XTAL_MODE_MANUAL_8822C(x, v) \ + (BIT_CLEAR_XTAL_MODE_MANUAL_8822C(x) | BIT_XTAL_MODE_MANUAL_8822C(v)) + +#define BIT_XTAL_MANU_SEL_8822C BIT(3) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_XTAL_MODE_8822C BIT(1) +#define BIT_RESET_N_DECODER_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SYS_CFG5_8822C */ +#define BIT_LPS_STATUS_8822C BIT(3) +#define BIT_HCI_TXDMA_BUSY_8822C BIT(2) +#define BIT_HCI_TXDMA_ALLOW_8822C BIT(1) +#define BIT_FW_CTRL_HCI_TXDMA_EN_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_CPU_DMEM_CON_8822C */ +#define BIT_WDT_AUTO_MODE_8822C BIT(22) +#define BIT_WDT_PLATFORM_EN_8822C BIT(21) +#define BIT_WDT_CPU_EN_8822C BIT(20) +#define BIT_WDT_OPT_IOWRAPPER_8822C BIT(19) +#define BIT_ANA_PORT_IDLE_8822C BIT(18) +#define BIT_MAC_PORT_IDLE_8822C BIT(17) +#define BIT_WL_PLATFORM_RST_8822C BIT(16) +#define BIT_WL_SECURITY_CLK_8822C BIT(15) +#define BIT_DDMA_EN_8822C BIT(8) + +#define BIT_SHIFT_CPU_DMEM_CON_8822C 0 +#define BIT_MASK_CPU_DMEM_CON_8822C 0xff +#define BIT_CPU_DMEM_CON_8822C(x) \ + (((x) & BIT_MASK_CPU_DMEM_CON_8822C) << BIT_SHIFT_CPU_DMEM_CON_8822C) +#define BITS_CPU_DMEM_CON_8822C \ + (BIT_MASK_CPU_DMEM_CON_8822C << BIT_SHIFT_CPU_DMEM_CON_8822C) +#define BIT_CLEAR_CPU_DMEM_CON_8822C(x) ((x) & (~BITS_CPU_DMEM_CON_8822C)) +#define BIT_GET_CPU_DMEM_CON_8822C(x) \ + (((x) >> BIT_SHIFT_CPU_DMEM_CON_8822C) & BIT_MASK_CPU_DMEM_CON_8822C) +#define BIT_SET_CPU_DMEM_CON_8822C(x, v) \ + (BIT_CLEAR_CPU_DMEM_CON_8822C(x) | BIT_CPU_DMEM_CON_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_BOOT_REASON_8822C */ + +#define BIT_SHIFT_BOOT_REASON_V1_8822C 0 +#define BIT_MASK_BOOT_REASON_V1_8822C 0x7 +#define BIT_BOOT_REASON_V1_8822C(x) \ + (((x) & BIT_MASK_BOOT_REASON_V1_8822C) \ + << BIT_SHIFT_BOOT_REASON_V1_8822C) +#define BITS_BOOT_REASON_V1_8822C \ + (BIT_MASK_BOOT_REASON_V1_8822C << BIT_SHIFT_BOOT_REASON_V1_8822C) +#define BIT_CLEAR_BOOT_REASON_V1_8822C(x) ((x) & (~BITS_BOOT_REASON_V1_8822C)) +#define BIT_GET_BOOT_REASON_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BOOT_REASON_V1_8822C) & \ + BIT_MASK_BOOT_REASON_V1_8822C) +#define BIT_SET_BOOT_REASON_V1_8822C(x, v) \ + (BIT_CLEAR_BOOT_REASON_V1_8822C(x) | BIT_BOOT_REASON_V1_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_HIMR2_8822C */ +#define BIT_BCNDMAINT_P4_MSK_8822C BIT(31) +#define BIT_BCNDMAINT_P3_MSK_8822C BIT(30) +#define BIT_BCNDMAINT_P2_MSK_8822C BIT(29) +#define BIT_BCNDMAINT_P1_MSK_8822C BIT(28) +#define BIT_ATIMEND7_MSK_8822C BIT(22) +#define BIT_ATIMEND6_MSK_8822C BIT(21) +#define BIT_ATIMEND5_MSK_8822C BIT(20) +#define BIT_ATIMEND4_MSK_8822C BIT(19) +#define BIT_ATIMEND3_MSK_8822C BIT(18) +#define BIT_ATIMEND2_MSK_8822C BIT(17) +#define BIT_ATIMEND1_MSK_8822C BIT(16) +#define BIT_TXBCN7OK_MSK_8822C BIT(14) +#define BIT_TXBCN6OK_MSK_8822C BIT(13) +#define BIT_TXBCN5OK_MSK_8822C BIT(12) +#define BIT_TXBCN4OK_MSK_8822C BIT(11) +#define BIT_TXBCN3OK_MSK_8822C BIT(10) +#define BIT_TXBCN2OK_MSK_8822C BIT(9) +#define BIT_TXBCN1OK_MSK_V1_8822C BIT(8) +#define BIT_TXBCN7ERR_MSK_8822C BIT(6) +#define BIT_TXBCN6ERR_MSK_8822C BIT(5) +#define BIT_TXBCN5ERR_MSK_8822C BIT(4) +#define BIT_TXBCN4ERR_MSK_8822C BIT(3) +#define BIT_TXBCN3ERR_MSK_8822C BIT(2) +#define BIT_TXBCN2ERR_MSK_8822C BIT(1) +#define BIT_TXBCN1ERR_MSK_V1_8822C BIT(0) + +/* 2 REG_HISR2_8822C */ +#define BIT_BCNDMAINT_P4_8822C BIT(31) +#define BIT_BCNDMAINT_P3_8822C BIT(30) +#define BIT_BCNDMAINT_P2_8822C BIT(29) +#define BIT_BCNDMAINT_P1_8822C BIT(28) +#define BIT_ATIMEND7_8822C BIT(22) +#define BIT_ATIMEND6_8822C BIT(21) +#define BIT_ATIMEND5_8822C BIT(20) +#define BIT_ATIMEND4_8822C BIT(19) +#define BIT_ATIMEND3_8822C BIT(18) +#define BIT_ATIMEND2_8822C BIT(17) +#define BIT_ATIMEND1_8822C BIT(16) +#define BIT_TXBCN7OK_8822C BIT(14) +#define BIT_TXBCN6OK_8822C BIT(13) +#define BIT_TXBCN5OK_8822C BIT(12) +#define BIT_TXBCN4OK_8822C BIT(11) +#define BIT_TXBCN3OK_8822C BIT(10) +#define BIT_TXBCN2OK_8822C BIT(9) +#define BIT_TXBCN1OK_8822C BIT(8) +#define BIT_TXBCN7ERR_8822C BIT(6) +#define BIT_TXBCN6ERR_8822C BIT(5) +#define BIT_TXBCN5ERR_8822C BIT(4) +#define BIT_TXBCN4ERR_8822C BIT(3) +#define BIT_TXBCN3ERR_8822C BIT(2) +#define BIT_TXBCN2ERR_8822C BIT(1) +#define BIT_TXBCN1ERR_8822C BIT(0) + +/* 2 REG_HIMR3_8822C */ +#define BIT_WDT_PLATFORM_INT_MSK_8822C BIT(18) +#define BIT_WDT_CPU_INT_MSK_8822C BIT(17) +#define BIT_SETH2CDOK_MASK_8822C BIT(16) +#define BIT_H2C_CMD_FULL_MASK_8822C BIT(15) +#define BIT_PWR_INT_127_MASK_8822C BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8822C BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8822C BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8822C BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8822C BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8822C BIT(9) +#define BIT_PWR_INT_127_MASK_V1_8822C BIT(8) +#define BIT_PWR_INT_126TO96_MASK_8822C BIT(7) +#define BIT_PWR_INT_95TO64_MASK_8822C BIT(6) +#define BIT_PWR_INT_63TO32_MASK_8822C BIT(5) +#define BIT_PWR_INT_31TO0_MASK_8822C BIT(4) +#define BIT_RX_DMA_STUCK_MSK_8822C BIT(3) +#define BIT_TX_DMA_STUCK_MSK_8822C BIT(2) +#define BIT_DDMA0_LP_INT_MSK_8822C BIT(1) +#define BIT_DDMA0_HP_INT_MSK_8822C BIT(0) + +/* 2 REG_HISR3_8822C */ +#define BIT_WDT_PLATFORM_INT_8822C BIT(18) +#define BIT_WDT_CPU_INT_8822C BIT(17) +#define BIT_SETH2CDOK_8822C BIT(16) +#define BIT_H2C_CMD_FULL_8822C BIT(15) +#define BIT_PWR_INT_127_8822C BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822C BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_8822C BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_8822C BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_8822C BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_8822C BIT(9) +#define BIT_PWR_INT_127_V1_8822C BIT(8) +#define BIT_PWR_INT_126TO96_8822C BIT(7) +#define BIT_PWR_INT_95TO64_8822C BIT(6) +#define BIT_PWR_INT_63TO32_8822C BIT(5) +#define BIT_PWR_INT_31TO0_8822C BIT(4) +#define BIT_RX_DMA_STUCK_8822C BIT(3) +#define BIT_TX_DMA_STUCK_8822C BIT(2) +#define BIT_DDMA0_LP_INT_8822C BIT(1) +#define BIT_DDMA0_HP_INT_8822C BIT(0) + +/* 2 REG_SW_MDIO_8822C */ +#define BIT_DIS_TIMEOUT_IO_8822C BIT(24) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_H2C_PKT_READADDR_8822C */ + +#define BIT_SHIFT_H2C_PKT_READADDR_8822C 0 +#define BIT_MASK_H2C_PKT_READADDR_8822C 0x3ffff +#define BIT_H2C_PKT_READADDR_8822C(x) \ + (((x) & BIT_MASK_H2C_PKT_READADDR_8822C) \ + << BIT_SHIFT_H2C_PKT_READADDR_8822C) +#define BITS_H2C_PKT_READADDR_8822C \ + (BIT_MASK_H2C_PKT_READADDR_8822C << BIT_SHIFT_H2C_PKT_READADDR_8822C) +#define BIT_CLEAR_H2C_PKT_READADDR_8822C(x) \ + ((x) & (~BITS_H2C_PKT_READADDR_8822C)) +#define BIT_GET_H2C_PKT_READADDR_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822C) & \ + BIT_MASK_H2C_PKT_READADDR_8822C) +#define BIT_SET_H2C_PKT_READADDR_8822C(x, v) \ + (BIT_CLEAR_H2C_PKT_READADDR_8822C(x) | BIT_H2C_PKT_READADDR_8822C(v)) + +/* 2 REG_H2C_PKT_WRITEADDR_8822C */ + +#define BIT_SHIFT_H2C_PKT_WRITEADDR_8822C 0 +#define BIT_MASK_H2C_PKT_WRITEADDR_8822C 0x3ffff +#define BIT_H2C_PKT_WRITEADDR_8822C(x) \ + (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822C) \ + << BIT_SHIFT_H2C_PKT_WRITEADDR_8822C) +#define BITS_H2C_PKT_WRITEADDR_8822C \ + (BIT_MASK_H2C_PKT_WRITEADDR_8822C << BIT_SHIFT_H2C_PKT_WRITEADDR_8822C) +#define BIT_CLEAR_H2C_PKT_WRITEADDR_8822C(x) \ + ((x) & (~BITS_H2C_PKT_WRITEADDR_8822C)) +#define BIT_GET_H2C_PKT_WRITEADDR_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822C) & \ + BIT_MASK_H2C_PKT_WRITEADDR_8822C) +#define BIT_SET_H2C_PKT_WRITEADDR_8822C(x, v) \ + (BIT_CLEAR_H2C_PKT_WRITEADDR_8822C(x) | BIT_H2C_PKT_WRITEADDR_8822C(v)) + +/* 2 REG_MEM_PWR_CRTL_8822C */ +#define BIT_MEM_BB_SD_8822C BIT(17) +#define BIT_MEM_BB_DS_8822C BIT(16) +#define BIT_MEM_BT_DS_8822C BIT(10) +#define BIT_MEM_SDIO_LS_8822C BIT(9) +#define BIT_MEM_SDIO_DS_8822C BIT(8) +#define BIT_MEM_USB_LS_8822C BIT(7) +#define BIT_MEM_USB_DS_8822C BIT(6) +#define BIT_MEM_PCI_LS_8822C BIT(5) +#define BIT_MEM_PCI_DS_8822C BIT(4) +#define BIT_MEM_WLMAC_LS_8822C BIT(3) +#define BIT_MEM_WLMAC_DS_8822C BIT(2) +#define BIT_MEM_WLMCU_LS_8822C BIT(1) +#define BIT_MEM_WLMCU_DS_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_FW_DBG6_8822C */ + +#define BIT_SHIFT_FW_DBG6_8822C 0 +#define BIT_MASK_FW_DBG6_8822C 0xffffffffL +#define BIT_FW_DBG6_8822C(x) \ + (((x) & BIT_MASK_FW_DBG6_8822C) << BIT_SHIFT_FW_DBG6_8822C) +#define BITS_FW_DBG6_8822C (BIT_MASK_FW_DBG6_8822C << BIT_SHIFT_FW_DBG6_8822C) +#define BIT_CLEAR_FW_DBG6_8822C(x) ((x) & (~BITS_FW_DBG6_8822C)) +#define BIT_GET_FW_DBG6_8822C(x) \ + (((x) >> BIT_SHIFT_FW_DBG6_8822C) & BIT_MASK_FW_DBG6_8822C) +#define BIT_SET_FW_DBG6_8822C(x, v) \ + (BIT_CLEAR_FW_DBG6_8822C(x) | BIT_FW_DBG6_8822C(v)) + +/* 2 REG_FW_DBG7_8822C */ + +#define BIT_SHIFT_FW_DBG7_8822C 0 +#define BIT_MASK_FW_DBG7_8822C 0xffffffffL +#define BIT_FW_DBG7_8822C(x) \ + (((x) & BIT_MASK_FW_DBG7_8822C) << BIT_SHIFT_FW_DBG7_8822C) +#define BITS_FW_DBG7_8822C (BIT_MASK_FW_DBG7_8822C << BIT_SHIFT_FW_DBG7_8822C) +#define BIT_CLEAR_FW_DBG7_8822C(x) ((x) & (~BITS_FW_DBG7_8822C)) +#define BIT_GET_FW_DBG7_8822C(x) \ + (((x) >> BIT_SHIFT_FW_DBG7_8822C) & BIT_MASK_FW_DBG7_8822C) +#define BIT_SET_FW_DBG7_8822C(x, v) \ + (BIT_CLEAR_FW_DBG7_8822C(x) | BIT_FW_DBG7_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_CR_8822C */ + +#define BIT_SHIFT_LBMODE_8822C 24 +#define BIT_MASK_LBMODE_8822C 0x1f +#define BIT_LBMODE_8822C(x) \ + (((x) & BIT_MASK_LBMODE_8822C) << BIT_SHIFT_LBMODE_8822C) +#define BITS_LBMODE_8822C (BIT_MASK_LBMODE_8822C << BIT_SHIFT_LBMODE_8822C) +#define BIT_CLEAR_LBMODE_8822C(x) ((x) & (~BITS_LBMODE_8822C)) +#define BIT_GET_LBMODE_8822C(x) \ + (((x) >> BIT_SHIFT_LBMODE_8822C) & BIT_MASK_LBMODE_8822C) +#define BIT_SET_LBMODE_8822C(x, v) \ + (BIT_CLEAR_LBMODE_8822C(x) | BIT_LBMODE_8822C(v)) + +#define BIT_SHIFT_NETYPE1_8822C 18 +#define BIT_MASK_NETYPE1_8822C 0x3 +#define BIT_NETYPE1_8822C(x) \ + (((x) & BIT_MASK_NETYPE1_8822C) << BIT_SHIFT_NETYPE1_8822C) +#define BITS_NETYPE1_8822C (BIT_MASK_NETYPE1_8822C << BIT_SHIFT_NETYPE1_8822C) +#define BIT_CLEAR_NETYPE1_8822C(x) ((x) & (~BITS_NETYPE1_8822C)) +#define BIT_GET_NETYPE1_8822C(x) \ + (((x) >> BIT_SHIFT_NETYPE1_8822C) & BIT_MASK_NETYPE1_8822C) +#define BIT_SET_NETYPE1_8822C(x, v) \ + (BIT_CLEAR_NETYPE1_8822C(x) | BIT_NETYPE1_8822C(v)) + +#define BIT_SHIFT_NETYPE0_8822C 16 +#define BIT_MASK_NETYPE0_8822C 0x3 +#define BIT_NETYPE0_8822C(x) \ + (((x) & BIT_MASK_NETYPE0_8822C) << BIT_SHIFT_NETYPE0_8822C) +#define BITS_NETYPE0_8822C (BIT_MASK_NETYPE0_8822C << BIT_SHIFT_NETYPE0_8822C) +#define BIT_CLEAR_NETYPE0_8822C(x) ((x) & (~BITS_NETYPE0_8822C)) +#define BIT_GET_NETYPE0_8822C(x) \ + (((x) >> BIT_SHIFT_NETYPE0_8822C) & BIT_MASK_NETYPE0_8822C) +#define BIT_SET_NETYPE0_8822C(x, v) \ + (BIT_CLEAR_NETYPE0_8822C(x) | BIT_NETYPE0_8822C(v)) + +#define BIT_COUNTER_STS_EN_8822C BIT(13) +#define BIT_I2C_MAILBOX_EN_8822C BIT(12) +#define BIT_SHCUT_EN_8822C BIT(11) +#define BIT_32K_CAL_TMR_EN_8822C BIT(10) +#define BIT_MAC_SEC_EN_8822C BIT(9) +#define BIT_ENSWBCN_8822C BIT(8) +#define BIT_MACRXEN_8822C BIT(7) +#define BIT_MACTXEN_8822C BIT(6) +#define BIT_SCHEDULE_EN_8822C BIT(5) +#define BIT_PROTOCOL_EN_8822C BIT(4) +#define BIT_RXDMA_EN_8822C BIT(3) +#define BIT_TXDMA_EN_8822C BIT(2) +#define BIT_HCI_RXDMA_EN_8822C BIT(1) +#define BIT_HCI_TXDMA_EN_8822C BIT(0) + +/* 2 REG_PG_SIZE_8822C */ + +#define BIT_SHIFT_DBG_FIFO_SEL_8822C 16 +#define BIT_MASK_DBG_FIFO_SEL_8822C 0xff +#define BIT_DBG_FIFO_SEL_8822C(x) \ + (((x) & BIT_MASK_DBG_FIFO_SEL_8822C) << BIT_SHIFT_DBG_FIFO_SEL_8822C) +#define BITS_DBG_FIFO_SEL_8822C \ + (BIT_MASK_DBG_FIFO_SEL_8822C << BIT_SHIFT_DBG_FIFO_SEL_8822C) +#define BIT_CLEAR_DBG_FIFO_SEL_8822C(x) ((x) & (~BITS_DBG_FIFO_SEL_8822C)) +#define BIT_GET_DBG_FIFO_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_DBG_FIFO_SEL_8822C) & BIT_MASK_DBG_FIFO_SEL_8822C) +#define BIT_SET_DBG_FIFO_SEL_8822C(x, v) \ + (BIT_CLEAR_DBG_FIFO_SEL_8822C(x) | BIT_DBG_FIFO_SEL_8822C(v)) + +/* 2 REG_PKT_BUFF_ACCESS_CTRL_8822C */ + +#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C 0 +#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C 0xff +#define BIT_PKT_BUFF_ACCESS_CTRL_8822C(x) \ + (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C) \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C) +#define BITS_PKT_BUFF_ACCESS_CTRL_8822C \ + (BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C) +#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8822C(x) \ + ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8822C)) +#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8822C(x) \ + (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C) & \ + BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C) +#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8822C(x, v) \ + (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8822C(x) | \ + BIT_PKT_BUFF_ACCESS_CTRL_8822C(v)) + +/* 2 REG_TSF_CLK_STATE_8822C */ +#define BIT_TSF_CLK_STABLE_8822C BIT(15) + +/* 2 REG_TXDMA_PQ_MAP_8822C */ +#define BIT_CSI_BW_EN_8822C BIT(31) + +#define BIT_SHIFT_TXDMA_H2C_MAP_8822C 16 +#define BIT_MASK_TXDMA_H2C_MAP_8822C 0x3 +#define BIT_TXDMA_H2C_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_H2C_MAP_8822C) << BIT_SHIFT_TXDMA_H2C_MAP_8822C) +#define BITS_TXDMA_H2C_MAP_8822C \ + (BIT_MASK_TXDMA_H2C_MAP_8822C << BIT_SHIFT_TXDMA_H2C_MAP_8822C) +#define BIT_CLEAR_TXDMA_H2C_MAP_8822C(x) ((x) & (~BITS_TXDMA_H2C_MAP_8822C)) +#define BIT_GET_TXDMA_H2C_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8822C) & BIT_MASK_TXDMA_H2C_MAP_8822C) +#define BIT_SET_TXDMA_H2C_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_H2C_MAP_8822C(x) | BIT_TXDMA_H2C_MAP_8822C(v)) + +#define BIT_SHIFT_TXDMA_HIQ_MAP_8822C 14 +#define BIT_MASK_TXDMA_HIQ_MAP_8822C 0x3 +#define BIT_TXDMA_HIQ_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP_8822C) << BIT_SHIFT_TXDMA_HIQ_MAP_8822C) +#define BITS_TXDMA_HIQ_MAP_8822C \ + (BIT_MASK_TXDMA_HIQ_MAP_8822C << BIT_SHIFT_TXDMA_HIQ_MAP_8822C) +#define BIT_CLEAR_TXDMA_HIQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8822C)) +#define BIT_GET_TXDMA_HIQ_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822C) & BIT_MASK_TXDMA_HIQ_MAP_8822C) +#define BIT_SET_TXDMA_HIQ_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP_8822C(x) | BIT_TXDMA_HIQ_MAP_8822C(v)) + +#define BIT_SHIFT_TXDMA_MGQ_MAP_8822C 12 +#define BIT_MASK_TXDMA_MGQ_MAP_8822C 0x3 +#define BIT_TXDMA_MGQ_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP_8822C) << BIT_SHIFT_TXDMA_MGQ_MAP_8822C) +#define BITS_TXDMA_MGQ_MAP_8822C \ + (BIT_MASK_TXDMA_MGQ_MAP_8822C << BIT_SHIFT_TXDMA_MGQ_MAP_8822C) +#define BIT_CLEAR_TXDMA_MGQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8822C)) +#define BIT_GET_TXDMA_MGQ_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822C) & BIT_MASK_TXDMA_MGQ_MAP_8822C) +#define BIT_SET_TXDMA_MGQ_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP_8822C(x) | BIT_TXDMA_MGQ_MAP_8822C(v)) + +#define BIT_SHIFT_TXDMA_BKQ_MAP_8822C 10 +#define BIT_MASK_TXDMA_BKQ_MAP_8822C 0x3 +#define BIT_TXDMA_BKQ_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP_8822C) << BIT_SHIFT_TXDMA_BKQ_MAP_8822C) +#define BITS_TXDMA_BKQ_MAP_8822C \ + (BIT_MASK_TXDMA_BKQ_MAP_8822C << BIT_SHIFT_TXDMA_BKQ_MAP_8822C) +#define BIT_CLEAR_TXDMA_BKQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8822C)) +#define BIT_GET_TXDMA_BKQ_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822C) & BIT_MASK_TXDMA_BKQ_MAP_8822C) +#define BIT_SET_TXDMA_BKQ_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP_8822C(x) | BIT_TXDMA_BKQ_MAP_8822C(v)) + +#define BIT_SHIFT_TXDMA_BEQ_MAP_8822C 8 +#define BIT_MASK_TXDMA_BEQ_MAP_8822C 0x3 +#define BIT_TXDMA_BEQ_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP_8822C) << BIT_SHIFT_TXDMA_BEQ_MAP_8822C) +#define BITS_TXDMA_BEQ_MAP_8822C \ + (BIT_MASK_TXDMA_BEQ_MAP_8822C << BIT_SHIFT_TXDMA_BEQ_MAP_8822C) +#define BIT_CLEAR_TXDMA_BEQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8822C)) +#define BIT_GET_TXDMA_BEQ_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822C) & BIT_MASK_TXDMA_BEQ_MAP_8822C) +#define BIT_SET_TXDMA_BEQ_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP_8822C(x) | BIT_TXDMA_BEQ_MAP_8822C(v)) + +#define BIT_SHIFT_TXDMA_VIQ_MAP_8822C 6 +#define BIT_MASK_TXDMA_VIQ_MAP_8822C 0x3 +#define BIT_TXDMA_VIQ_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP_8822C) << BIT_SHIFT_TXDMA_VIQ_MAP_8822C) +#define BITS_TXDMA_VIQ_MAP_8822C \ + (BIT_MASK_TXDMA_VIQ_MAP_8822C << BIT_SHIFT_TXDMA_VIQ_MAP_8822C) +#define BIT_CLEAR_TXDMA_VIQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8822C)) +#define BIT_GET_TXDMA_VIQ_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822C) & BIT_MASK_TXDMA_VIQ_MAP_8822C) +#define BIT_SET_TXDMA_VIQ_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP_8822C(x) | BIT_TXDMA_VIQ_MAP_8822C(v)) + +#define BIT_SHIFT_TXDMA_VOQ_MAP_8822C 4 +#define BIT_MASK_TXDMA_VOQ_MAP_8822C 0x3 +#define BIT_TXDMA_VOQ_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP_8822C) << BIT_SHIFT_TXDMA_VOQ_MAP_8822C) +#define BITS_TXDMA_VOQ_MAP_8822C \ + (BIT_MASK_TXDMA_VOQ_MAP_8822C << BIT_SHIFT_TXDMA_VOQ_MAP_8822C) +#define BIT_CLEAR_TXDMA_VOQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8822C)) +#define BIT_GET_TXDMA_VOQ_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822C) & BIT_MASK_TXDMA_VOQ_MAP_8822C) +#define BIT_SET_TXDMA_VOQ_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP_8822C(x) | BIT_TXDMA_VOQ_MAP_8822C(v)) + +#define BIT_TXDMA_BW_EN_8822C BIT(3) +#define BIT_RXDMA_AGG_EN_8822C BIT(2) +#define BIT_RXSHFT_EN_8822C BIT(1) +#define BIT_RXDMA_ARBBW_EN_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_TRXFF_BNDY_8822C */ + +#define BIT_SHIFT_FWFFOVFL_RSV_8822C 16 +#define BIT_MASK_FWFFOVFL_RSV_8822C 0xf +#define BIT_FWFFOVFL_RSV_8822C(x) \ + (((x) & BIT_MASK_FWFFOVFL_RSV_8822C) << BIT_SHIFT_FWFFOVFL_RSV_8822C) +#define BITS_FWFFOVFL_RSV_8822C \ + (BIT_MASK_FWFFOVFL_RSV_8822C << BIT_SHIFT_FWFFOVFL_RSV_8822C) +#define BIT_CLEAR_FWFFOVFL_RSV_8822C(x) ((x) & (~BITS_FWFFOVFL_RSV_8822C)) +#define BIT_GET_FWFFOVFL_RSV_8822C(x) \ + (((x) >> BIT_SHIFT_FWFFOVFL_RSV_8822C) & BIT_MASK_FWFFOVFL_RSV_8822C) +#define BIT_SET_FWFFOVFL_RSV_8822C(x, v) \ + (BIT_CLEAR_FWFFOVFL_RSV_8822C(x) | BIT_FWFFOVFL_RSV_8822C(v)) + +#define BIT_SHIFT_RXFFOVFL_RSV_V2_8822C 8 +#define BIT_MASK_RXFFOVFL_RSV_V2_8822C 0xf +#define BIT_RXFFOVFL_RSV_V2_8822C(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822C) \ + << BIT_SHIFT_RXFFOVFL_RSV_V2_8822C) +#define BITS_RXFFOVFL_RSV_V2_8822C \ + (BIT_MASK_RXFFOVFL_RSV_V2_8822C << BIT_SHIFT_RXFFOVFL_RSV_V2_8822C) +#define BIT_CLEAR_RXFFOVFL_RSV_V2_8822C(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8822C)) +#define BIT_GET_RXFFOVFL_RSV_V2_8822C(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822C) & \ + BIT_MASK_RXFFOVFL_RSV_V2_8822C) +#define BIT_SET_RXFFOVFL_RSV_V2_8822C(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V2_8822C(x) | BIT_RXFFOVFL_RSV_V2_8822C(v)) + +/* 2 REG_PTA_I2C_MBOX_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_I2C_M_STATUS_8822C 8 +#define BIT_MASK_I2C_M_STATUS_8822C 0xf +#define BIT_I2C_M_STATUS_8822C(x) \ + (((x) & BIT_MASK_I2C_M_STATUS_8822C) << BIT_SHIFT_I2C_M_STATUS_8822C) +#define BITS_I2C_M_STATUS_8822C \ + (BIT_MASK_I2C_M_STATUS_8822C << BIT_SHIFT_I2C_M_STATUS_8822C) +#define BIT_CLEAR_I2C_M_STATUS_8822C(x) ((x) & (~BITS_I2C_M_STATUS_8822C)) +#define BIT_GET_I2C_M_STATUS_8822C(x) \ + (((x) >> BIT_SHIFT_I2C_M_STATUS_8822C) & BIT_MASK_I2C_M_STATUS_8822C) +#define BIT_SET_I2C_M_STATUS_8822C(x, v) \ + (BIT_CLEAR_I2C_M_STATUS_8822C(x) | BIT_I2C_M_STATUS_8822C(v)) + +#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C 4 +#define BIT_MASK_I2C_M_BUS_GNT_FW_8822C 0x7 +#define BIT_I2C_M_BUS_GNT_FW_8822C(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822C) \ + << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C) +#define BITS_I2C_M_BUS_GNT_FW_8822C \ + (BIT_MASK_I2C_M_BUS_GNT_FW_8822C << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8822C(x) \ + ((x) & (~BITS_I2C_M_BUS_GNT_FW_8822C)) +#define BIT_GET_I2C_M_BUS_GNT_FW_8822C(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C) & \ + BIT_MASK_I2C_M_BUS_GNT_FW_8822C) +#define BIT_SET_I2C_M_BUS_GNT_FW_8822C(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT_FW_8822C(x) | BIT_I2C_M_BUS_GNT_FW_8822C(v)) + +#define BIT_I2C_M_GNT_FW_8822C BIT(3) + +#define BIT_SHIFT_I2C_M_SPEED_8822C 1 +#define BIT_MASK_I2C_M_SPEED_8822C 0x3 +#define BIT_I2C_M_SPEED_8822C(x) \ + (((x) & BIT_MASK_I2C_M_SPEED_8822C) << BIT_SHIFT_I2C_M_SPEED_8822C) +#define BITS_I2C_M_SPEED_8822C \ + (BIT_MASK_I2C_M_SPEED_8822C << BIT_SHIFT_I2C_M_SPEED_8822C) +#define BIT_CLEAR_I2C_M_SPEED_8822C(x) ((x) & (~BITS_I2C_M_SPEED_8822C)) +#define BIT_GET_I2C_M_SPEED_8822C(x) \ + (((x) >> BIT_SHIFT_I2C_M_SPEED_8822C) & BIT_MASK_I2C_M_SPEED_8822C) +#define BIT_SET_I2C_M_SPEED_8822C(x, v) \ + (BIT_CLEAR_I2C_M_SPEED_8822C(x) | BIT_I2C_M_SPEED_8822C(v)) + +#define BIT_I2C_M_UNLOCK_8822C BIT(0) + +/* 2 REG_RXFF_BNDY_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_RXFF0_BNDY_V2_8822C 0 +#define BIT_MASK_RXFF0_BNDY_V2_8822C 0x3ffff +#define BIT_RXFF0_BNDY_V2_8822C(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V2_8822C) << BIT_SHIFT_RXFF0_BNDY_V2_8822C) +#define BITS_RXFF0_BNDY_V2_8822C \ + (BIT_MASK_RXFF0_BNDY_V2_8822C << BIT_SHIFT_RXFF0_BNDY_V2_8822C) +#define BIT_CLEAR_RXFF0_BNDY_V2_8822C(x) ((x) & (~BITS_RXFF0_BNDY_V2_8822C)) +#define BIT_GET_RXFF0_BNDY_V2_8822C(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822C) & BIT_MASK_RXFF0_BNDY_V2_8822C) +#define BIT_SET_RXFF0_BNDY_V2_8822C(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V2_8822C(x) | BIT_RXFF0_BNDY_V2_8822C(v)) + +/* 2 REG_FE1IMR_8822C */ +#define BIT_FS_SW_PLL_LEAVE_32K_INT_EN_8822C BIT(31) +#define BIT_FS_FWFF_FULL_INT_EN_8822C BIT(30) +#define BIT_FS_BB_STOP_RX_INT_EN_8822C BIT(29) +#define BIT_FS_RXDMA2_DONE_INT_EN_8822C BIT(28) +#define BIT_FS_RXDONE2_INT_EN_8822C BIT(26) +#define BIT_FS_RX_BCN_P4_INT_EN_8822C BIT(25) +#define BIT_FS_RX_BCN_P3_INT_EN_8822C BIT(24) +#define BIT_FS_RX_BCN_P2_INT_EN_8822C BIT(23) +#define BIT_FS_RX_BCN_P1_INT_EN_8822C BIT(22) +#define BIT_FS_RX_BCN_P0_INT_EN_8822C BIT(21) +#define BIT_FS_RX_UMD0_INT_EN_8822C BIT(20) +#define BIT_FS_RX_UMD1_INT_EN_8822C BIT(19) +#define BIT_FS_RX_BMD0_INT_EN_8822C BIT(18) +#define BIT_FS_RX_BMD1_INT_EN_8822C BIT(17) +#define BIT_FS_RXDONE_INT_EN_8822C BIT(16) +#define BIT_FS_WWLAN_INT_EN_8822C BIT(15) +#define BIT_FS_SOUND_DONE_INT_EN_8822C BIT(14) +#define BIT_FS_BF1_PRETO_INT_EN_8822C BIT(11) +#define BIT_FS_BF0_PRETO_INT_EN_8822C BIT(10) +#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8822C BIT(9) +#define BIT_FS_PRETX_ERRHLD_INT_EN_8822C BIT(8) +#define BIT_FS_LTE_COEX_EN_8822C BIT(6) +#define BIT_FS_WLACTOFF_INT_EN_8822C BIT(5) +#define BIT_FS_WLACTON_INT_EN_8822C BIT(4) +#define BIT_FS_BTCMD_INT_EN_8822C BIT(3) +#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8822C BIT(2) +#define BIT_FS_TRPC_TO_INT_EN_V1_8822C BIT(1) +#define BIT_FS_RPC_O_T_INT_EN_V1_8822C BIT(0) + +/* 2 REG_FE1ISR_8822C */ +#define BIT_FS_SW_PLL_LEAVE_32K_INT_8822C BIT(31) +#define BIT_FS_FS_FWFF_FULL_INT_8822C BIT(30) +#define BIT_FS_BB_STOP_RX_INT_8822C BIT(29) +#define BIT_FS_RXDMA2_DONE_INT_8822C BIT(28) +#define BIT_FS_RXDONE2_INT_8822C BIT(26) +#define BIT_FS_RX_BCN_P4_INT_8822C BIT(25) +#define BIT_FS_RX_BCN_P3_INT_8822C BIT(24) +#define BIT_FS_RX_BCN_P2_INT_8822C BIT(23) +#define BIT_FS_RX_BCN_P1_INT_8822C BIT(22) +#define BIT_FS_RX_BCN_P0_INT_8822C BIT(21) +#define BIT_FS_RX_UMD0_INT_8822C BIT(20) +#define BIT_FS_RX_UMD1_INT_8822C BIT(19) +#define BIT_FS_RX_BMD0_INT_8822C BIT(18) +#define BIT_FS_RX_BMD1_INT_8822C BIT(17) +#define BIT_FS_RXDONE_INT_8822C BIT(16) +#define BIT_FS_WWLAN_INT_8822C BIT(15) +#define BIT_FS_SOUND_DONE_INT_8822C BIT(14) +#define BIT_FS_BF1_PRETO_INT_8822C BIT(11) +#define BIT_FS_BF0_PRETO_INT_8822C BIT(10) +#define BIT_FS_PTCL_RELEASE_MACID_INT_8822C BIT(9) +#define BIT_FS_PRETX_ERRHLD_INT_8822C BIT(8) +#define BIT_FS_LTE_COEX_INT_8822C BIT(6) +#define BIT_FS_WLACTOFF_INT_8822C BIT(5) +#define BIT_FS_WLACTON_INT_8822C BIT(4) +#define BIT_FS_BCN_RX_INT_INT_8822C BIT(3) +#define BIT_FS_MAILBOX_TO_I2C_INT_8822C BIT(2) +#define BIT_FS_TRPC_TO_INT_8822C BIT(1) +#define BIT_FS_RPC_O_T_INT_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_CPWM_8822C */ +#define BIT_CPWM_TOGGLING_8822C BIT(31) + +#define BIT_SHIFT_CPWM_MOD_8822C 24 +#define BIT_MASK_CPWM_MOD_8822C 0x7f +#define BIT_CPWM_MOD_8822C(x) \ + (((x) & BIT_MASK_CPWM_MOD_8822C) << BIT_SHIFT_CPWM_MOD_8822C) +#define BITS_CPWM_MOD_8822C \ + (BIT_MASK_CPWM_MOD_8822C << BIT_SHIFT_CPWM_MOD_8822C) +#define BIT_CLEAR_CPWM_MOD_8822C(x) ((x) & (~BITS_CPWM_MOD_8822C)) +#define BIT_GET_CPWM_MOD_8822C(x) \ + (((x) >> BIT_SHIFT_CPWM_MOD_8822C) & BIT_MASK_CPWM_MOD_8822C) +#define BIT_SET_CPWM_MOD_8822C(x, v) \ + (BIT_CLEAR_CPWM_MOD_8822C(x) | BIT_CPWM_MOD_8822C(v)) + +/* 2 REG_FWIMR_8822C */ +#define BIT_FS_TXBCNOK_MB7_INT_EN_8822C BIT(31) +#define BIT_FS_TXBCNOK_MB6_INT_EN_8822C BIT(30) +#define BIT_FS_TXBCNOK_MB5_INT_EN_8822C BIT(29) +#define BIT_FS_TXBCNOK_MB4_INT_EN_8822C BIT(28) +#define BIT_FS_TXBCNOK_MB3_INT_EN_8822C BIT(27) +#define BIT_FS_TXBCNOK_MB2_INT_EN_8822C BIT(26) +#define BIT_FS_TXBCNOK_MB1_INT_EN_8822C BIT(25) +#define BIT_FS_TXBCNOK_MB0_INT_EN_8822C BIT(24) +#define BIT_FS_TXBCNERR_MB7_INT_EN_8822C BIT(23) +#define BIT_FS_TXBCNERR_MB6_INT_EN_8822C BIT(22) +#define BIT_FS_TXBCNERR_MB5_INT_EN_8822C BIT(21) +#define BIT_FS_TXBCNERR_MB4_INT_EN_8822C BIT(20) +#define BIT_FS_TXBCNERR_MB3_INT_EN_8822C BIT(19) +#define BIT_FS_TXBCNERR_MB2_INT_EN_8822C BIT(18) +#define BIT_FS_TXBCNERR_MB1_INT_EN_8822C BIT(17) +#define BIT_FS_TXBCNERR_MB0_INT_EN_8822C BIT(16) +#define BIT_CPU_MGQ_TXDONE_INT_EN_8822C BIT(15) +#define BIT_SIFS_OVERSPEC_INT_EN_8822C BIT(14) +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8822C BIT(13) +#define BIT_FS_MGNTQFF_TO_INT_EN_8822C BIT(12) +#define BIT_FS_CPUMGQ_ERR_INT_EN_8822C BIT(11) +#define BIT_FS_DDMA0_LP_INT_EN_8822C BIT(9) +#define BIT_FS_DDMA0_HP_INT_EN_8822C BIT(8) +#define BIT_FS_TRXRPT_INT_EN_8822C BIT(7) +#define BIT_FS_C2H_W_READY_INT_EN_8822C BIT(6) +#define BIT_FS_HRCV_INT_EN_8822C BIT(5) +#define BIT_FS_H2CCMD_INT_EN_8822C BIT(4) +#define BIT_FS_TXPKTIN_INT_EN_8822C BIT(3) +#define BIT_FS_ERRORHDL_INT_EN_8822C BIT(2) +#define BIT_FS_TXCCX_INT_EN_8822C BIT(1) +#define BIT_FS_TXCLOSE_INT_EN_8822C BIT(0) + +/* 2 REG_FWISR_8822C */ +#define BIT_FS_TXBCNOK_MB7_INT_8822C BIT(31) +#define BIT_FS_TXBCNOK_MB6_INT_8822C BIT(30) +#define BIT_FS_TXBCNOK_MB5_INT_8822C BIT(29) +#define BIT_FS_TXBCNOK_MB4_INT_8822C BIT(28) +#define BIT_FS_TXBCNOK_MB3_INT_8822C BIT(27) +#define BIT_FS_TXBCNOK_MB2_INT_8822C BIT(26) +#define BIT_FS_TXBCNOK_MB1_INT_8822C BIT(25) +#define BIT_FS_TXBCNOK_MB0_INT_8822C BIT(24) +#define BIT_FS_TXBCNERR_MB7_INT_8822C BIT(23) +#define BIT_FS_TXBCNERR_MB6_INT_8822C BIT(22) +#define BIT_FS_TXBCNERR_MB5_INT_8822C BIT(21) +#define BIT_FS_TXBCNERR_MB4_INT_8822C BIT(20) +#define BIT_FS_TXBCNERR_MB3_INT_8822C BIT(19) +#define BIT_FS_TXBCNERR_MB2_INT_8822C BIT(18) +#define BIT_FS_TXBCNERR_MB1_INT_8822C BIT(17) +#define BIT_FS_TXBCNERR_MB0_INT_8822C BIT(16) +#define BIT_CPU_MGQ_TXDONE_INT_8822C BIT(15) +#define BIT_SIFS_OVERSPEC_INT_8822C BIT(14) +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8822C BIT(13) +#define BIT_FS_MGNTQFF_TO_INT_8822C BIT(12) +#define BIT_FS_CPUMGQ_ERR_INT_8822C BIT(11) +#define BIT_FS_DDMA0_LP_INT_8822C BIT(9) +#define BIT_FS_DDMA0_HP_INT_8822C BIT(8) +#define BIT_FS_TRXRPT_INT_8822C BIT(7) +#define BIT_FS_C2H_W_READY_INT_8822C BIT(6) +#define BIT_FS_HRCV_INT_8822C BIT(5) +#define BIT_FS_H2CCMD_INT_8822C BIT(4) +#define BIT_FS_TXPKTIN_INT_8822C BIT(3) +#define BIT_FS_ERRORHDL_INT_8822C BIT(2) +#define BIT_FS_TXCCX_INT_8822C BIT(1) +#define BIT_FS_TXCLOSE_INT_8822C BIT(0) + +/* 2 REG_FTIMR_8822C */ +#define BIT_PS_TIMER_C_EARLY_INT_EN_8822C BIT(23) +#define BIT_PS_TIMER_B_EARLY_INT_EN_8822C BIT(22) +#define BIT_PS_TIMER_A_EARLY_INT_EN_8822C BIT(21) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8822C BIT(20) +#define BIT_PS_TIMER_C_INT_EN_8822C BIT(19) +#define BIT_PS_TIMER_B_INT_EN_8822C BIT(18) +#define BIT_PS_TIMER_A_INT_EN_8822C BIT(17) +#define BIT_CPUMGQ_TX_TIMER_INT_EN_8822C BIT(16) +#define BIT_FS_PS_TIMEOUT2_EN_8822C BIT(15) +#define BIT_FS_PS_TIMEOUT1_EN_8822C BIT(14) +#define BIT_FS_PS_TIMEOUT0_EN_8822C BIT(13) +#define BIT_FS_GTINT8_EN_8822C BIT(8) +#define BIT_FS_GTINT7_EN_8822C BIT(7) +#define BIT_FS_GTINT6_EN_8822C BIT(6) +#define BIT_FS_GTINT5_EN_8822C BIT(5) +#define BIT_FS_GTINT4_EN_8822C BIT(4) +#define BIT_FS_GTINT3_EN_8822C BIT(3) +#define BIT_FS_GTINT2_EN_8822C BIT(2) +#define BIT_FS_GTINT1_EN_8822C BIT(1) +#define BIT_FS_GTINT0_EN_8822C BIT(0) + +/* 2 REG_FTISR_8822C */ +#define BIT_PS_TIMER_C_EARLY__INT_8822C BIT(23) +#define BIT_PS_TIMER_B_EARLY__INT_8822C BIT(22) +#define BIT_PS_TIMER_A_EARLY__INT_8822C BIT(21) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8822C BIT(20) +#define BIT_PS_TIMER_C_INT_8822C BIT(19) +#define BIT_PS_TIMER_B_INT_8822C BIT(18) +#define BIT_PS_TIMER_A_INT_8822C BIT(17) +#define BIT_CPUMGQ_TX_TIMER_INT_8822C BIT(16) +#define BIT_FS_PS_TIMEOUT2_INT_8822C BIT(15) +#define BIT_FS_PS_TIMEOUT1_INT_8822C BIT(14) +#define BIT_FS_PS_TIMEOUT0_INT_8822C BIT(13) +#define BIT_FS_GTINT8_INT_8822C BIT(8) +#define BIT_FS_GTINT7_INT_8822C BIT(7) +#define BIT_FS_GTINT6_INT_8822C BIT(6) +#define BIT_FS_GTINT5_INT_8822C BIT(5) +#define BIT_FS_GTINT4_INT_8822C BIT(4) +#define BIT_FS_GTINT3_INT_8822C BIT(3) +#define BIT_FS_GTINT2_INT_8822C BIT(2) +#define BIT_FS_GTINT1_INT_8822C BIT(1) +#define BIT_FS_GTINT0_INT_8822C BIT(0) + +/* 2 REG_PKTBUF_DBG_CTRL_8822C */ + +#define BIT_SHIFT_PKTBUF_WRITE_EN_8822C 24 +#define BIT_MASK_PKTBUF_WRITE_EN_8822C 0xff +#define BIT_PKTBUF_WRITE_EN_8822C(x) \ + (((x) & BIT_MASK_PKTBUF_WRITE_EN_8822C) \ + << BIT_SHIFT_PKTBUF_WRITE_EN_8822C) +#define BITS_PKTBUF_WRITE_EN_8822C \ + (BIT_MASK_PKTBUF_WRITE_EN_8822C << BIT_SHIFT_PKTBUF_WRITE_EN_8822C) +#define BIT_CLEAR_PKTBUF_WRITE_EN_8822C(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8822C)) +#define BIT_GET_PKTBUF_WRITE_EN_8822C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822C) & \ + BIT_MASK_PKTBUF_WRITE_EN_8822C) +#define BIT_SET_PKTBUF_WRITE_EN_8822C(x, v) \ + (BIT_CLEAR_PKTBUF_WRITE_EN_8822C(x) | BIT_PKTBUF_WRITE_EN_8822C(v)) + +#define BIT_TXRPTBUF_DBG_8822C BIT(23) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_TXPKTBUF_DBG_V2_8822C BIT(20) +#define BIT_RXPKTBUF_DBG_8822C BIT(16) + +#define BIT_SHIFT_PKTBUF_DBG_ADDR_8822C 0 +#define BIT_MASK_PKTBUF_DBG_ADDR_8822C 0x1fff +#define BIT_PKTBUF_DBG_ADDR_8822C(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822C) \ + << BIT_SHIFT_PKTBUF_DBG_ADDR_8822C) +#define BITS_PKTBUF_DBG_ADDR_8822C \ + (BIT_MASK_PKTBUF_DBG_ADDR_8822C << BIT_SHIFT_PKTBUF_DBG_ADDR_8822C) +#define BIT_CLEAR_PKTBUF_DBG_ADDR_8822C(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8822C)) +#define BIT_GET_PKTBUF_DBG_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822C) & \ + BIT_MASK_PKTBUF_DBG_ADDR_8822C) +#define BIT_SET_PKTBUF_DBG_ADDR_8822C(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_ADDR_8822C(x) | BIT_PKTBUF_DBG_ADDR_8822C(v)) + +/* 2 REG_PKTBUF_DBG_DATA_L_8822C */ + +#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C 0 +#define BIT_MASK_PKTBUF_DBG_DATA_L_8822C 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_L_8822C(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822C) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C) +#define BITS_PKTBUF_DBG_DATA_L_8822C \ + (BIT_MASK_PKTBUF_DBG_DATA_L_8822C << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8822C(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_L_8822C)) +#define BIT_GET_PKTBUF_DBG_DATA_L_8822C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C) & \ + BIT_MASK_PKTBUF_DBG_DATA_L_8822C) +#define BIT_SET_PKTBUF_DBG_DATA_L_8822C(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_L_8822C(x) | BIT_PKTBUF_DBG_DATA_L_8822C(v)) + +/* 2 REG_PKTBUF_DBG_DATA_H_8822C */ + +#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C 0 +#define BIT_MASK_PKTBUF_DBG_DATA_H_8822C 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_H_8822C(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822C) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C) +#define BITS_PKTBUF_DBG_DATA_H_8822C \ + (BIT_MASK_PKTBUF_DBG_DATA_H_8822C << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8822C(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_H_8822C)) +#define BIT_GET_PKTBUF_DBG_DATA_H_8822C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C) & \ + BIT_MASK_PKTBUF_DBG_DATA_H_8822C) +#define BIT_SET_PKTBUF_DBG_DATA_H_8822C(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_H_8822C(x) | BIT_PKTBUF_DBG_DATA_H_8822C(v)) + +/* 2 REG_CPWM2_8822C */ + +#define BIT_SHIFT_L0S_TO_RCVY_NUM_8822C 16 +#define BIT_MASK_L0S_TO_RCVY_NUM_8822C 0xff +#define BIT_L0S_TO_RCVY_NUM_8822C(x) \ + (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822C) \ + << BIT_SHIFT_L0S_TO_RCVY_NUM_8822C) +#define BITS_L0S_TO_RCVY_NUM_8822C \ + (BIT_MASK_L0S_TO_RCVY_NUM_8822C << BIT_SHIFT_L0S_TO_RCVY_NUM_8822C) +#define BIT_CLEAR_L0S_TO_RCVY_NUM_8822C(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8822C)) +#define BIT_GET_L0S_TO_RCVY_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822C) & \ + BIT_MASK_L0S_TO_RCVY_NUM_8822C) +#define BIT_SET_L0S_TO_RCVY_NUM_8822C(x, v) \ + (BIT_CLEAR_L0S_TO_RCVY_NUM_8822C(x) | BIT_L0S_TO_RCVY_NUM_8822C(v)) + +#define BIT_CPWM2_TOGGLING_8822C BIT(15) + +#define BIT_SHIFT_CPWM2_MOD_8822C 0 +#define BIT_MASK_CPWM2_MOD_8822C 0x7fff +#define BIT_CPWM2_MOD_8822C(x) \ + (((x) & BIT_MASK_CPWM2_MOD_8822C) << BIT_SHIFT_CPWM2_MOD_8822C) +#define BITS_CPWM2_MOD_8822C \ + (BIT_MASK_CPWM2_MOD_8822C << BIT_SHIFT_CPWM2_MOD_8822C) +#define BIT_CLEAR_CPWM2_MOD_8822C(x) ((x) & (~BITS_CPWM2_MOD_8822C)) +#define BIT_GET_CPWM2_MOD_8822C(x) \ + (((x) >> BIT_SHIFT_CPWM2_MOD_8822C) & BIT_MASK_CPWM2_MOD_8822C) +#define BIT_SET_CPWM2_MOD_8822C(x, v) \ + (BIT_CLEAR_CPWM2_MOD_8822C(x) | BIT_CPWM2_MOD_8822C(v)) + +/* 2 REG_TC0_CTRL_8822C */ +#define BIT_TC0INT_EN_8822C BIT(26) +#define BIT_TC0MODE_8822C BIT(25) +#define BIT_TC0EN_8822C BIT(24) + +#define BIT_SHIFT_TC0DATA_8822C 0 +#define BIT_MASK_TC0DATA_8822C 0xffffff +#define BIT_TC0DATA_8822C(x) \ + (((x) & BIT_MASK_TC0DATA_8822C) << BIT_SHIFT_TC0DATA_8822C) +#define BITS_TC0DATA_8822C (BIT_MASK_TC0DATA_8822C << BIT_SHIFT_TC0DATA_8822C) +#define BIT_CLEAR_TC0DATA_8822C(x) ((x) & (~BITS_TC0DATA_8822C)) +#define BIT_GET_TC0DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC0DATA_8822C) & BIT_MASK_TC0DATA_8822C) +#define BIT_SET_TC0DATA_8822C(x, v) \ + (BIT_CLEAR_TC0DATA_8822C(x) | BIT_TC0DATA_8822C(v)) + +/* 2 REG_TC1_CTRL_8822C */ +#define BIT_TC1INT_EN_8822C BIT(26) +#define BIT_TC1MODE_8822C BIT(25) +#define BIT_TC1EN_8822C BIT(24) + +#define BIT_SHIFT_TC1DATA_8822C 0 +#define BIT_MASK_TC1DATA_8822C 0xffffff +#define BIT_TC1DATA_8822C(x) \ + (((x) & BIT_MASK_TC1DATA_8822C) << BIT_SHIFT_TC1DATA_8822C) +#define BITS_TC1DATA_8822C (BIT_MASK_TC1DATA_8822C << BIT_SHIFT_TC1DATA_8822C) +#define BIT_CLEAR_TC1DATA_8822C(x) ((x) & (~BITS_TC1DATA_8822C)) +#define BIT_GET_TC1DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC1DATA_8822C) & BIT_MASK_TC1DATA_8822C) +#define BIT_SET_TC1DATA_8822C(x, v) \ + (BIT_CLEAR_TC1DATA_8822C(x) | BIT_TC1DATA_8822C(v)) + +/* 2 REG_TC2_CTRL_8822C */ +#define BIT_TC2INT_EN_8822C BIT(26) +#define BIT_TC2MODE_8822C BIT(25) +#define BIT_TC2EN_8822C BIT(24) + +#define BIT_SHIFT_TC2DATA_8822C 0 +#define BIT_MASK_TC2DATA_8822C 0xffffff +#define BIT_TC2DATA_8822C(x) \ + (((x) & BIT_MASK_TC2DATA_8822C) << BIT_SHIFT_TC2DATA_8822C) +#define BITS_TC2DATA_8822C (BIT_MASK_TC2DATA_8822C << BIT_SHIFT_TC2DATA_8822C) +#define BIT_CLEAR_TC2DATA_8822C(x) ((x) & (~BITS_TC2DATA_8822C)) +#define BIT_GET_TC2DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC2DATA_8822C) & BIT_MASK_TC2DATA_8822C) +#define BIT_SET_TC2DATA_8822C(x, v) \ + (BIT_CLEAR_TC2DATA_8822C(x) | BIT_TC2DATA_8822C(v)) + +/* 2 REG_TC3_CTRL_8822C */ +#define BIT_TC3INT_EN_8822C BIT(26) +#define BIT_TC3MODE_8822C BIT(25) +#define BIT_TC3EN_8822C BIT(24) + +#define BIT_SHIFT_TC3DATA_8822C 0 +#define BIT_MASK_TC3DATA_8822C 0xffffff +#define BIT_TC3DATA_8822C(x) \ + (((x) & BIT_MASK_TC3DATA_8822C) << BIT_SHIFT_TC3DATA_8822C) +#define BITS_TC3DATA_8822C (BIT_MASK_TC3DATA_8822C << BIT_SHIFT_TC3DATA_8822C) +#define BIT_CLEAR_TC3DATA_8822C(x) ((x) & (~BITS_TC3DATA_8822C)) +#define BIT_GET_TC3DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC3DATA_8822C) & BIT_MASK_TC3DATA_8822C) +#define BIT_SET_TC3DATA_8822C(x, v) \ + (BIT_CLEAR_TC3DATA_8822C(x) | BIT_TC3DATA_8822C(v)) + +/* 2 REG_TC4_CTRL_8822C */ +#define BIT_TC4INT_EN_8822C BIT(26) +#define BIT_TC4MODE_8822C BIT(25) +#define BIT_TC4EN_8822C BIT(24) + +#define BIT_SHIFT_TC4DATA_8822C 0 +#define BIT_MASK_TC4DATA_8822C 0xffffff +#define BIT_TC4DATA_8822C(x) \ + (((x) & BIT_MASK_TC4DATA_8822C) << BIT_SHIFT_TC4DATA_8822C) +#define BITS_TC4DATA_8822C (BIT_MASK_TC4DATA_8822C << BIT_SHIFT_TC4DATA_8822C) +#define BIT_CLEAR_TC4DATA_8822C(x) ((x) & (~BITS_TC4DATA_8822C)) +#define BIT_GET_TC4DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC4DATA_8822C) & BIT_MASK_TC4DATA_8822C) +#define BIT_SET_TC4DATA_8822C(x, v) \ + (BIT_CLEAR_TC4DATA_8822C(x) | BIT_TC4DATA_8822C(v)) + +/* 2 REG_TCUNIT_BASE_8822C */ + +#define BIT_SHIFT_TCUNIT_BASE_8822C 0 +#define BIT_MASK_TCUNIT_BASE_8822C 0x3fff +#define BIT_TCUNIT_BASE_8822C(x) \ + (((x) & BIT_MASK_TCUNIT_BASE_8822C) << BIT_SHIFT_TCUNIT_BASE_8822C) +#define BITS_TCUNIT_BASE_8822C \ + (BIT_MASK_TCUNIT_BASE_8822C << BIT_SHIFT_TCUNIT_BASE_8822C) +#define BIT_CLEAR_TCUNIT_BASE_8822C(x) ((x) & (~BITS_TCUNIT_BASE_8822C)) +#define BIT_GET_TCUNIT_BASE_8822C(x) \ + (((x) >> BIT_SHIFT_TCUNIT_BASE_8822C) & BIT_MASK_TCUNIT_BASE_8822C) +#define BIT_SET_TCUNIT_BASE_8822C(x, v) \ + (BIT_CLEAR_TCUNIT_BASE_8822C(x) | BIT_TCUNIT_BASE_8822C(v)) + +/* 2 REG_TC5_CTRL_8822C */ +#define BIT_TC5INT_EN_8822C BIT(26) +#define BIT_TC5MODE_8822C BIT(25) +#define BIT_TC5EN_8822C BIT(24) + +#define BIT_SHIFT_TC5DATA_8822C 0 +#define BIT_MASK_TC5DATA_8822C 0xffffff +#define BIT_TC5DATA_8822C(x) \ + (((x) & BIT_MASK_TC5DATA_8822C) << BIT_SHIFT_TC5DATA_8822C) +#define BITS_TC5DATA_8822C (BIT_MASK_TC5DATA_8822C << BIT_SHIFT_TC5DATA_8822C) +#define BIT_CLEAR_TC5DATA_8822C(x) ((x) & (~BITS_TC5DATA_8822C)) +#define BIT_GET_TC5DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC5DATA_8822C) & BIT_MASK_TC5DATA_8822C) +#define BIT_SET_TC5DATA_8822C(x, v) \ + (BIT_CLEAR_TC5DATA_8822C(x) | BIT_TC5DATA_8822C(v)) + +/* 2 REG_TC6_CTRL_8822C */ +#define BIT_TC6INT_EN_8822C BIT(26) +#define BIT_TC6MODE_8822C BIT(25) +#define BIT_TC6EN_8822C BIT(24) + +#define BIT_SHIFT_TC6DATA_8822C 0 +#define BIT_MASK_TC6DATA_8822C 0xffffff +#define BIT_TC6DATA_8822C(x) \ + (((x) & BIT_MASK_TC6DATA_8822C) << BIT_SHIFT_TC6DATA_8822C) +#define BITS_TC6DATA_8822C (BIT_MASK_TC6DATA_8822C << BIT_SHIFT_TC6DATA_8822C) +#define BIT_CLEAR_TC6DATA_8822C(x) ((x) & (~BITS_TC6DATA_8822C)) +#define BIT_GET_TC6DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC6DATA_8822C) & BIT_MASK_TC6DATA_8822C) +#define BIT_SET_TC6DATA_8822C(x, v) \ + (BIT_CLEAR_TC6DATA_8822C(x) | BIT_TC6DATA_8822C(v)) + +/* 2 REG_MBIST_DRF_FAIL_8822C */ + +#define BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C 26 +#define BIT_MASK_8051_MBIST_DRF_FAIL_8822C 0x3f +#define BIT_8051_MBIST_DRF_FAIL_8822C(x) \ + (((x) & BIT_MASK_8051_MBIST_DRF_FAIL_8822C) \ + << BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C) +#define BITS_8051_MBIST_DRF_FAIL_8822C \ + (BIT_MASK_8051_MBIST_DRF_FAIL_8822C \ + << BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C) +#define BIT_CLEAR_8051_MBIST_DRF_FAIL_8822C(x) \ + ((x) & (~BITS_8051_MBIST_DRF_FAIL_8822C)) +#define BIT_GET_8051_MBIST_DRF_FAIL_8822C(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C) & \ + BIT_MASK_8051_MBIST_DRF_FAIL_8822C) +#define BIT_SET_8051_MBIST_DRF_FAIL_8822C(x, v) \ + (BIT_CLEAR_8051_MBIST_DRF_FAIL_8822C(x) | \ + BIT_8051_MBIST_DRF_FAIL_8822C(v)) + +#define BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C 24 +#define BIT_MASK_USB_MBIST_DRF_FAIL_8822C 0x3 +#define BIT_USB_MBIST_DRF_FAIL_8822C(x) \ + (((x) & BIT_MASK_USB_MBIST_DRF_FAIL_8822C) \ + << BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C) +#define BITS_USB_MBIST_DRF_FAIL_8822C \ + (BIT_MASK_USB_MBIST_DRF_FAIL_8822C \ + << BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C) +#define BIT_CLEAR_USB_MBIST_DRF_FAIL_8822C(x) \ + ((x) & (~BITS_USB_MBIST_DRF_FAIL_8822C)) +#define BIT_GET_USB_MBIST_DRF_FAIL_8822C(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C) & \ + BIT_MASK_USB_MBIST_DRF_FAIL_8822C) +#define BIT_SET_USB_MBIST_DRF_FAIL_8822C(x, v) \ + (BIT_CLEAR_USB_MBIST_DRF_FAIL_8822C(x) | \ + BIT_USB_MBIST_DRF_FAIL_8822C(v)) + +#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C 18 +#define BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C 0x3f +#define BIT_PCIE_MBIST_DRF_FAIL_8822C(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C) \ + << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C) +#define BITS_PCIE_MBIST_DRF_FAIL_8822C \ + (BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C \ + << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C) +#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8822C(x) \ + ((x) & (~BITS_PCIE_MBIST_DRF_FAIL_8822C)) +#define BIT_GET_PCIE_MBIST_DRF_FAIL_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C) & \ + BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C) +#define BIT_SET_PCIE_MBIST_DRF_FAIL_8822C(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8822C(x) | \ + BIT_PCIE_MBIST_DRF_FAIL_8822C(v)) + +#define BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C 0 +#define BIT_MASK_MAC_MBIST_DRF_FAIL_8822C 0x3ffff +#define BIT_MAC_MBIST_DRF_FAIL_8822C(x) \ + (((x) & BIT_MASK_MAC_MBIST_DRF_FAIL_8822C) \ + << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C) +#define BITS_MAC_MBIST_DRF_FAIL_8822C \ + (BIT_MASK_MAC_MBIST_DRF_FAIL_8822C \ + << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C) +#define BIT_CLEAR_MAC_MBIST_DRF_FAIL_8822C(x) \ + ((x) & (~BITS_MAC_MBIST_DRF_FAIL_8822C)) +#define BIT_GET_MAC_MBIST_DRF_FAIL_8822C(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C) & \ + BIT_MASK_MAC_MBIST_DRF_FAIL_8822C) +#define BIT_SET_MAC_MBIST_DRF_FAIL_8822C(x, v) \ + (BIT_CLEAR_MAC_MBIST_DRF_FAIL_8822C(x) | \ + BIT_MAC_MBIST_DRF_FAIL_8822C(v)) + +/* 2 REG_MBIST_START_PAUSE_8822C */ + +#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C 26 +#define BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C 0x3f +#define BIT_8051_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C) \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C) +#define BITS_8051_MBIST_START_PAUSE_V1_8822C \ + (BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C) +#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8822C(x) \ + ((x) & (~BITS_8051_MBIST_START_PAUSE_V1_8822C)) +#define BIT_GET_8051_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C) & \ + BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C) +#define BIT_SET_8051_MBIST_START_PAUSE_V1_8822C(x, v) \ + (BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8822C(x) | \ + BIT_8051_MBIST_START_PAUSE_V1_8822C(v)) + +#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C 24 +#define BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C 0x3 +#define BIT_USB_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C) +#define BITS_USB_MBIST_START_PAUSE_V1_8822C \ + (BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C) +#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8822C(x) \ + ((x) & (~BITS_USB_MBIST_START_PAUSE_V1_8822C)) +#define BIT_GET_USB_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C) & \ + BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C) +#define BIT_SET_USB_MBIST_START_PAUSE_V1_8822C(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8822C(x) | \ + BIT_USB_MBIST_START_PAUSE_V1_8822C(v)) + +#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C 18 +#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C 0x3f +#define BIT_PCIE_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C) +#define BITS_PCIE_MBIST_START_PAUSE_V1_8822C \ + (BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8822C(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1_8822C)) +#define BIT_GET_PCIE_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C) +#define BIT_SET_PCIE_MBIST_START_PAUSE_V1_8822C(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8822C(x) | \ + BIT_PCIE_MBIST_START_PAUSE_V1_8822C(v)) + +#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C 0 +#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C 0x3ffff +#define BIT_MAC_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C) \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C) +#define BITS_MAC_MBIST_START_PAUSE_V1_8822C \ + (BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8822C(x) \ + ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8822C)) +#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C) & \ + BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C) +#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8822C(x, v) \ + (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8822C(x) | \ + BIT_MAC_MBIST_START_PAUSE_V1_8822C(v)) + +/* 2 REG_MBIST_DONE_8822C */ + +#define BIT_SHIFT_8051_MBIST_DONE_V1_8822C 26 +#define BIT_MASK_8051_MBIST_DONE_V1_8822C 0x3f +#define BIT_8051_MBIST_DONE_V1_8822C(x) \ + (((x) & BIT_MASK_8051_MBIST_DONE_V1_8822C) \ + << BIT_SHIFT_8051_MBIST_DONE_V1_8822C) +#define BITS_8051_MBIST_DONE_V1_8822C \ + (BIT_MASK_8051_MBIST_DONE_V1_8822C \ + << BIT_SHIFT_8051_MBIST_DONE_V1_8822C) +#define BIT_CLEAR_8051_MBIST_DONE_V1_8822C(x) \ + ((x) & (~BITS_8051_MBIST_DONE_V1_8822C)) +#define BIT_GET_8051_MBIST_DONE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DONE_V1_8822C) & \ + BIT_MASK_8051_MBIST_DONE_V1_8822C) +#define BIT_SET_8051_MBIST_DONE_V1_8822C(x, v) \ + (BIT_CLEAR_8051_MBIST_DONE_V1_8822C(x) | \ + BIT_8051_MBIST_DONE_V1_8822C(v)) + +#define BIT_SHIFT_USB_MBIST_DONE_V1_8822C 24 +#define BIT_MASK_USB_MBIST_DONE_V1_8822C 0x3 +#define BIT_USB_MBIST_DONE_V1_8822C(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE_V1_8822C) \ + << BIT_SHIFT_USB_MBIST_DONE_V1_8822C) +#define BITS_USB_MBIST_DONE_V1_8822C \ + (BIT_MASK_USB_MBIST_DONE_V1_8822C << BIT_SHIFT_USB_MBIST_DONE_V1_8822C) +#define BIT_CLEAR_USB_MBIST_DONE_V1_8822C(x) \ + ((x) & (~BITS_USB_MBIST_DONE_V1_8822C)) +#define BIT_GET_USB_MBIST_DONE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE_V1_8822C) & \ + BIT_MASK_USB_MBIST_DONE_V1_8822C) +#define BIT_SET_USB_MBIST_DONE_V1_8822C(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE_V1_8822C(x) | BIT_USB_MBIST_DONE_V1_8822C(v)) + +#define BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C 18 +#define BIT_MASK_PCIE_MBIST_DONE_V1_8822C 0x3f +#define BIT_PCIE_MBIST_DONE_V1_8822C(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE_V1_8822C) \ + << BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C) +#define BITS_PCIE_MBIST_DONE_V1_8822C \ + (BIT_MASK_PCIE_MBIST_DONE_V1_8822C \ + << BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C) +#define BIT_CLEAR_PCIE_MBIST_DONE_V1_8822C(x) \ + ((x) & (~BITS_PCIE_MBIST_DONE_V1_8822C)) +#define BIT_GET_PCIE_MBIST_DONE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C) & \ + BIT_MASK_PCIE_MBIST_DONE_V1_8822C) +#define BIT_SET_PCIE_MBIST_DONE_V1_8822C(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE_V1_8822C(x) | \ + BIT_PCIE_MBIST_DONE_V1_8822C(v)) + +#define BIT_SHIFT_MAC_MBIST_DONE_V1_8822C 0 +#define BIT_MASK_MAC_MBIST_DONE_V1_8822C 0x3ffff +#define BIT_MAC_MBIST_DONE_V1_8822C(x) \ + (((x) & BIT_MASK_MAC_MBIST_DONE_V1_8822C) \ + << BIT_SHIFT_MAC_MBIST_DONE_V1_8822C) +#define BITS_MAC_MBIST_DONE_V1_8822C \ + (BIT_MASK_MAC_MBIST_DONE_V1_8822C << BIT_SHIFT_MAC_MBIST_DONE_V1_8822C) +#define BIT_CLEAR_MAC_MBIST_DONE_V1_8822C(x) \ + ((x) & (~BITS_MAC_MBIST_DONE_V1_8822C)) +#define BIT_GET_MAC_MBIST_DONE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8822C) & \ + BIT_MASK_MAC_MBIST_DONE_V1_8822C) +#define BIT_SET_MAC_MBIST_DONE_V1_8822C(x, v) \ + (BIT_CLEAR_MAC_MBIST_DONE_V1_8822C(x) | BIT_MAC_MBIST_DONE_V1_8822C(v)) + +/* 2 REG_MBIST_READ_BIST_RPT_8822C */ + +#define BIT_SHIFT_MBIST_READ_BIST_RPT_8822C 0 +#define BIT_MASK_MBIST_READ_BIST_RPT_8822C 0xffffffffL +#define BIT_MBIST_READ_BIST_RPT_8822C(x) \ + (((x) & BIT_MASK_MBIST_READ_BIST_RPT_8822C) \ + << BIT_SHIFT_MBIST_READ_BIST_RPT_8822C) +#define BITS_MBIST_READ_BIST_RPT_8822C \ + (BIT_MASK_MBIST_READ_BIST_RPT_8822C \ + << BIT_SHIFT_MBIST_READ_BIST_RPT_8822C) +#define BIT_CLEAR_MBIST_READ_BIST_RPT_8822C(x) \ + ((x) & (~BITS_MBIST_READ_BIST_RPT_8822C)) +#define BIT_GET_MBIST_READ_BIST_RPT_8822C(x) \ + (((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT_8822C) & \ + BIT_MASK_MBIST_READ_BIST_RPT_8822C) +#define BIT_SET_MBIST_READ_BIST_RPT_8822C(x, v) \ + (BIT_CLEAR_MBIST_READ_BIST_RPT_8822C(x) | \ + BIT_MBIST_READ_BIST_RPT_8822C(v)) + +/* 2 REG_AES_DECRPT_DATA_8822C */ + +#define BIT_SHIFT_IPS_CFG_ADDR_8822C 0 +#define BIT_MASK_IPS_CFG_ADDR_8822C 0xff +#define BIT_IPS_CFG_ADDR_8822C(x) \ + (((x) & BIT_MASK_IPS_CFG_ADDR_8822C) << BIT_SHIFT_IPS_CFG_ADDR_8822C) +#define BITS_IPS_CFG_ADDR_8822C \ + (BIT_MASK_IPS_CFG_ADDR_8822C << BIT_SHIFT_IPS_CFG_ADDR_8822C) +#define BIT_CLEAR_IPS_CFG_ADDR_8822C(x) ((x) & (~BITS_IPS_CFG_ADDR_8822C)) +#define BIT_GET_IPS_CFG_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822C) & BIT_MASK_IPS_CFG_ADDR_8822C) +#define BIT_SET_IPS_CFG_ADDR_8822C(x, v) \ + (BIT_CLEAR_IPS_CFG_ADDR_8822C(x) | BIT_IPS_CFG_ADDR_8822C(v)) + +/* 2 REG_AES_DECRPT_CFG_8822C */ + +#define BIT_SHIFT_IPS_CFG_DATA_8822C 0 +#define BIT_MASK_IPS_CFG_DATA_8822C 0xffffffffL +#define BIT_IPS_CFG_DATA_8822C(x) \ + (((x) & BIT_MASK_IPS_CFG_DATA_8822C) << BIT_SHIFT_IPS_CFG_DATA_8822C) +#define BITS_IPS_CFG_DATA_8822C \ + (BIT_MASK_IPS_CFG_DATA_8822C << BIT_SHIFT_IPS_CFG_DATA_8822C) +#define BIT_CLEAR_IPS_CFG_DATA_8822C(x) ((x) & (~BITS_IPS_CFG_DATA_8822C)) +#define BIT_GET_IPS_CFG_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_DATA_8822C) & BIT_MASK_IPS_CFG_DATA_8822C) +#define BIT_SET_IPS_CFG_DATA_8822C(x, v) \ + (BIT_CLEAR_IPS_CFG_DATA_8822C(x) | BIT_IPS_CFG_DATA_8822C(v)) + +/* 2 REG_HIOE_CTRL_8822C */ +#define BIT_HIOE_CFG_FILE_LOC_SEL_8822C BIT(31) +#define BIT_HIOE_WRITE_REQ_8822C BIT(30) +#define BIT_HIOE_READ_REQ_8822C BIT(29) +#define BIT_INST_FORMAT_ERR_8822C BIT(25) +#define BIT_OP_TIMEOUT_ERR_8822C BIT(24) + +#define BIT_SHIFT_HIOE_OP_TIMEOUT_8822C 16 +#define BIT_MASK_HIOE_OP_TIMEOUT_8822C 0xff +#define BIT_HIOE_OP_TIMEOUT_8822C(x) \ + (((x) & BIT_MASK_HIOE_OP_TIMEOUT_8822C) \ + << BIT_SHIFT_HIOE_OP_TIMEOUT_8822C) +#define BITS_HIOE_OP_TIMEOUT_8822C \ + (BIT_MASK_HIOE_OP_TIMEOUT_8822C << BIT_SHIFT_HIOE_OP_TIMEOUT_8822C) +#define BIT_CLEAR_HIOE_OP_TIMEOUT_8822C(x) ((x) & (~BITS_HIOE_OP_TIMEOUT_8822C)) +#define BIT_GET_HIOE_OP_TIMEOUT_8822C(x) \ + (((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT_8822C) & \ + BIT_MASK_HIOE_OP_TIMEOUT_8822C) +#define BIT_SET_HIOE_OP_TIMEOUT_8822C(x, v) \ + (BIT_CLEAR_HIOE_OP_TIMEOUT_8822C(x) | BIT_HIOE_OP_TIMEOUT_8822C(v)) + +#define BIT_SHIFT_BITDATA_CHECKSUM_8822C 0 +#define BIT_MASK_BITDATA_CHECKSUM_8822C 0xffff +#define BIT_BITDATA_CHECKSUM_8822C(x) \ + (((x) & BIT_MASK_BITDATA_CHECKSUM_8822C) \ + << BIT_SHIFT_BITDATA_CHECKSUM_8822C) +#define BITS_BITDATA_CHECKSUM_8822C \ + (BIT_MASK_BITDATA_CHECKSUM_8822C << BIT_SHIFT_BITDATA_CHECKSUM_8822C) +#define BIT_CLEAR_BITDATA_CHECKSUM_8822C(x) \ + ((x) & (~BITS_BITDATA_CHECKSUM_8822C)) +#define BIT_GET_BITDATA_CHECKSUM_8822C(x) \ + (((x) >> BIT_SHIFT_BITDATA_CHECKSUM_8822C) & \ + BIT_MASK_BITDATA_CHECKSUM_8822C) +#define BIT_SET_BITDATA_CHECKSUM_8822C(x, v) \ + (BIT_CLEAR_BITDATA_CHECKSUM_8822C(x) | BIT_BITDATA_CHECKSUM_8822C(v)) + +/* 2 REG_HIOE_CFG_FILE_8822C */ + +#define BIT_SHIFT_TXBF_END_ADDR_8822C 16 +#define BIT_MASK_TXBF_END_ADDR_8822C 0xffff +#define BIT_TXBF_END_ADDR_8822C(x) \ + (((x) & BIT_MASK_TXBF_END_ADDR_8822C) << BIT_SHIFT_TXBF_END_ADDR_8822C) +#define BITS_TXBF_END_ADDR_8822C \ + (BIT_MASK_TXBF_END_ADDR_8822C << BIT_SHIFT_TXBF_END_ADDR_8822C) +#define BIT_CLEAR_TXBF_END_ADDR_8822C(x) ((x) & (~BITS_TXBF_END_ADDR_8822C)) +#define BIT_GET_TXBF_END_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_TXBF_END_ADDR_8822C) & BIT_MASK_TXBF_END_ADDR_8822C) +#define BIT_SET_TXBF_END_ADDR_8822C(x, v) \ + (BIT_CLEAR_TXBF_END_ADDR_8822C(x) | BIT_TXBF_END_ADDR_8822C(v)) + +#define BIT_SHIFT_TXBF_STR_ADDR_8822C 0 +#define BIT_MASK_TXBF_STR_ADDR_8822C 0xffff +#define BIT_TXBF_STR_ADDR_8822C(x) \ + (((x) & BIT_MASK_TXBF_STR_ADDR_8822C) << BIT_SHIFT_TXBF_STR_ADDR_8822C) +#define BITS_TXBF_STR_ADDR_8822C \ + (BIT_MASK_TXBF_STR_ADDR_8822C << BIT_SHIFT_TXBF_STR_ADDR_8822C) +#define BIT_CLEAR_TXBF_STR_ADDR_8822C(x) ((x) & (~BITS_TXBF_STR_ADDR_8822C)) +#define BIT_GET_TXBF_STR_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_TXBF_STR_ADDR_8822C) & BIT_MASK_TXBF_STR_ADDR_8822C) +#define BIT_SET_TXBF_STR_ADDR_8822C(x, v) \ + (BIT_CLEAR_TXBF_STR_ADDR_8822C(x) | BIT_TXBF_STR_ADDR_8822C(v)) + +/* 2 REG_TMETER_8822C */ +#define BIT_TEMP_VALID_8822C BIT(31) + +#define BIT_SHIFT_TEMP_VALUE_8822C 24 +#define BIT_MASK_TEMP_VALUE_8822C 0x3f +#define BIT_TEMP_VALUE_8822C(x) \ + (((x) & BIT_MASK_TEMP_VALUE_8822C) << BIT_SHIFT_TEMP_VALUE_8822C) +#define BITS_TEMP_VALUE_8822C \ + (BIT_MASK_TEMP_VALUE_8822C << BIT_SHIFT_TEMP_VALUE_8822C) +#define BIT_CLEAR_TEMP_VALUE_8822C(x) ((x) & (~BITS_TEMP_VALUE_8822C)) +#define BIT_GET_TEMP_VALUE_8822C(x) \ + (((x) >> BIT_SHIFT_TEMP_VALUE_8822C) & BIT_MASK_TEMP_VALUE_8822C) +#define BIT_SET_TEMP_VALUE_8822C(x, v) \ + (BIT_CLEAR_TEMP_VALUE_8822C(x) | BIT_TEMP_VALUE_8822C(v)) + +#define BIT_SHIFT_REG_TMETER_TIMER_8822C 8 +#define BIT_MASK_REG_TMETER_TIMER_8822C 0xfff +#define BIT_REG_TMETER_TIMER_8822C(x) \ + (((x) & BIT_MASK_REG_TMETER_TIMER_8822C) \ + << BIT_SHIFT_REG_TMETER_TIMER_8822C) +#define BITS_REG_TMETER_TIMER_8822C \ + (BIT_MASK_REG_TMETER_TIMER_8822C << BIT_SHIFT_REG_TMETER_TIMER_8822C) +#define BIT_CLEAR_REG_TMETER_TIMER_8822C(x) \ + ((x) & (~BITS_REG_TMETER_TIMER_8822C)) +#define BIT_GET_REG_TMETER_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822C) & \ + BIT_MASK_REG_TMETER_TIMER_8822C) +#define BIT_SET_REG_TMETER_TIMER_8822C(x, v) \ + (BIT_CLEAR_REG_TMETER_TIMER_8822C(x) | BIT_REG_TMETER_TIMER_8822C(v)) + +#define BIT_SHIFT_REG_TEMP_DELTA_8822C 2 +#define BIT_MASK_REG_TEMP_DELTA_8822C 0x3f +#define BIT_REG_TEMP_DELTA_8822C(x) \ + (((x) & BIT_MASK_REG_TEMP_DELTA_8822C) \ + << BIT_SHIFT_REG_TEMP_DELTA_8822C) +#define BITS_REG_TEMP_DELTA_8822C \ + (BIT_MASK_REG_TEMP_DELTA_8822C << BIT_SHIFT_REG_TEMP_DELTA_8822C) +#define BIT_CLEAR_REG_TEMP_DELTA_8822C(x) ((x) & (~BITS_REG_TEMP_DELTA_8822C)) +#define BIT_GET_REG_TEMP_DELTA_8822C(x) \ + (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822C) & \ + BIT_MASK_REG_TEMP_DELTA_8822C) +#define BIT_SET_REG_TEMP_DELTA_8822C(x, v) \ + (BIT_CLEAR_REG_TEMP_DELTA_8822C(x) | BIT_REG_TEMP_DELTA_8822C(v)) + +#define BIT_REG_TMETER_EN_8822C BIT(0) + +/* 2 REG_OSC_32K_CTRL_8822C */ + +#define BIT_SHIFT_OSC_32K_CLKGEN_0_8822C 16 +#define BIT_MASK_OSC_32K_CLKGEN_0_8822C 0xffff +#define BIT_OSC_32K_CLKGEN_0_8822C(x) \ + (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822C) \ + << BIT_SHIFT_OSC_32K_CLKGEN_0_8822C) +#define BITS_OSC_32K_CLKGEN_0_8822C \ + (BIT_MASK_OSC_32K_CLKGEN_0_8822C << BIT_SHIFT_OSC_32K_CLKGEN_0_8822C) +#define BIT_CLEAR_OSC_32K_CLKGEN_0_8822C(x) \ + ((x) & (~BITS_OSC_32K_CLKGEN_0_8822C)) +#define BIT_GET_OSC_32K_CLKGEN_0_8822C(x) \ + (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822C) & \ + BIT_MASK_OSC_32K_CLKGEN_0_8822C) +#define BIT_SET_OSC_32K_CLKGEN_0_8822C(x, v) \ + (BIT_CLEAR_OSC_32K_CLKGEN_0_8822C(x) | BIT_OSC_32K_CLKGEN_0_8822C(v)) + +#define BIT_SHIFT_OSC_32K_RES_COMP_8822C 4 +#define BIT_MASK_OSC_32K_RES_COMP_8822C 0x3 +#define BIT_OSC_32K_RES_COMP_8822C(x) \ + (((x) & BIT_MASK_OSC_32K_RES_COMP_8822C) \ + << BIT_SHIFT_OSC_32K_RES_COMP_8822C) +#define BITS_OSC_32K_RES_COMP_8822C \ + (BIT_MASK_OSC_32K_RES_COMP_8822C << BIT_SHIFT_OSC_32K_RES_COMP_8822C) +#define BIT_CLEAR_OSC_32K_RES_COMP_8822C(x) \ + ((x) & (~BITS_OSC_32K_RES_COMP_8822C)) +#define BIT_GET_OSC_32K_RES_COMP_8822C(x) \ + (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822C) & \ + BIT_MASK_OSC_32K_RES_COMP_8822C) +#define BIT_SET_OSC_32K_RES_COMP_8822C(x, v) \ + (BIT_CLEAR_OSC_32K_RES_COMP_8822C(x) | BIT_OSC_32K_RES_COMP_8822C(v)) + +#define BIT_OSC_32K_OUT_SEL_8822C BIT(3) +#define BIT_ISO_WL_2_OSC_32K_8822C BIT(1) +#define BIT_POW_CKGEN_8822C BIT(0) + +/* 2 REG_32K_CAL_REG1_8822C */ +#define BIT_CAL_32K_REG_WR_8822C BIT(31) +#define BIT_CAL_32K_DBG_SEL_8822C BIT(22) + +#define BIT_SHIFT_CAL_32K_REG_ADDR_8822C 16 +#define BIT_MASK_CAL_32K_REG_ADDR_8822C 0x3f +#define BIT_CAL_32K_REG_ADDR_8822C(x) \ + (((x) & BIT_MASK_CAL_32K_REG_ADDR_8822C) \ + << BIT_SHIFT_CAL_32K_REG_ADDR_8822C) +#define BITS_CAL_32K_REG_ADDR_8822C \ + (BIT_MASK_CAL_32K_REG_ADDR_8822C << BIT_SHIFT_CAL_32K_REG_ADDR_8822C) +#define BIT_CLEAR_CAL_32K_REG_ADDR_8822C(x) \ + ((x) & (~BITS_CAL_32K_REG_ADDR_8822C)) +#define BIT_GET_CAL_32K_REG_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822C) & \ + BIT_MASK_CAL_32K_REG_ADDR_8822C) +#define BIT_SET_CAL_32K_REG_ADDR_8822C(x, v) \ + (BIT_CLEAR_CAL_32K_REG_ADDR_8822C(x) | BIT_CAL_32K_REG_ADDR_8822C(v)) + +#define BIT_SHIFT_CAL_32K_REG_DATA_8822C 0 +#define BIT_MASK_CAL_32K_REG_DATA_8822C 0xffff +#define BIT_CAL_32K_REG_DATA_8822C(x) \ + (((x) & BIT_MASK_CAL_32K_REG_DATA_8822C) \ + << BIT_SHIFT_CAL_32K_REG_DATA_8822C) +#define BITS_CAL_32K_REG_DATA_8822C \ + (BIT_MASK_CAL_32K_REG_DATA_8822C << BIT_SHIFT_CAL_32K_REG_DATA_8822C) +#define BIT_CLEAR_CAL_32K_REG_DATA_8822C(x) \ + ((x) & (~BITS_CAL_32K_REG_DATA_8822C)) +#define BIT_GET_CAL_32K_REG_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822C) & \ + BIT_MASK_CAL_32K_REG_DATA_8822C) +#define BIT_SET_CAL_32K_REG_DATA_8822C(x, v) \ + (BIT_CLEAR_CAL_32K_REG_DATA_8822C(x) | BIT_CAL_32K_REG_DATA_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_C2HEVT_8822C */ + +#define BIT_SHIFT_C2HEVT_MSG_V1_8822C 0 +#define BIT_MASK_C2HEVT_MSG_V1_8822C 0xffffffffL +#define BIT_C2HEVT_MSG_V1_8822C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_V1_8822C) << BIT_SHIFT_C2HEVT_MSG_V1_8822C) +#define BITS_C2HEVT_MSG_V1_8822C \ + (BIT_MASK_C2HEVT_MSG_V1_8822C << BIT_SHIFT_C2HEVT_MSG_V1_8822C) +#define BIT_CLEAR_C2HEVT_MSG_V1_8822C(x) ((x) & (~BITS_C2HEVT_MSG_V1_8822C)) +#define BIT_GET_C2HEVT_MSG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8822C) & BIT_MASK_C2HEVT_MSG_V1_8822C) +#define BIT_SET_C2HEVT_MSG_V1_8822C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_V1_8822C(x) | BIT_C2HEVT_MSG_V1_8822C(v)) + +/* 2 REG_C2HEVT_1_8822C */ + +#define BIT_SHIFT_C2HEVT_MSG_1_8822C 0 +#define BIT_MASK_C2HEVT_MSG_1_8822C 0xffffffffL +#define BIT_C2HEVT_MSG_1_8822C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_1_8822C) << BIT_SHIFT_C2HEVT_MSG_1_8822C) +#define BITS_C2HEVT_MSG_1_8822C \ + (BIT_MASK_C2HEVT_MSG_1_8822C << BIT_SHIFT_C2HEVT_MSG_1_8822C) +#define BIT_CLEAR_C2HEVT_MSG_1_8822C(x) ((x) & (~BITS_C2HEVT_MSG_1_8822C)) +#define BIT_GET_C2HEVT_MSG_1_8822C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8822C) & BIT_MASK_C2HEVT_MSG_1_8822C) +#define BIT_SET_C2HEVT_MSG_1_8822C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_1_8822C(x) | BIT_C2HEVT_MSG_1_8822C(v)) + +/* 2 REG_C2HEVT_2_8822C */ + +#define BIT_SHIFT_C2HEVT_MSG_2_8822C 0 +#define BIT_MASK_C2HEVT_MSG_2_8822C 0xffffffffL +#define BIT_C2HEVT_MSG_2_8822C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_2_8822C) << BIT_SHIFT_C2HEVT_MSG_2_8822C) +#define BITS_C2HEVT_MSG_2_8822C \ + (BIT_MASK_C2HEVT_MSG_2_8822C << BIT_SHIFT_C2HEVT_MSG_2_8822C) +#define BIT_CLEAR_C2HEVT_MSG_2_8822C(x) ((x) & (~BITS_C2HEVT_MSG_2_8822C)) +#define BIT_GET_C2HEVT_MSG_2_8822C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8822C) & BIT_MASK_C2HEVT_MSG_2_8822C) +#define BIT_SET_C2HEVT_MSG_2_8822C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_2_8822C(x) | BIT_C2HEVT_MSG_2_8822C(v)) + +/* 2 REG_C2HEVT_3_8822C */ + +#define BIT_SHIFT_C2HEVT_MSG_3_8822C 0 +#define BIT_MASK_C2HEVT_MSG_3_8822C 0xffffffffL +#define BIT_C2HEVT_MSG_3_8822C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_3_8822C) << BIT_SHIFT_C2HEVT_MSG_3_8822C) +#define BITS_C2HEVT_MSG_3_8822C \ + (BIT_MASK_C2HEVT_MSG_3_8822C << BIT_SHIFT_C2HEVT_MSG_3_8822C) +#define BIT_CLEAR_C2HEVT_MSG_3_8822C(x) ((x) & (~BITS_C2HEVT_MSG_3_8822C)) +#define BIT_GET_C2HEVT_MSG_3_8822C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8822C) & BIT_MASK_C2HEVT_MSG_3_8822C) +#define BIT_SET_C2HEVT_MSG_3_8822C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_3_8822C(x) | BIT_C2HEVT_MSG_3_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SW_DEFINED_PAGE1_8822C */ + +#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C 0 +#define BIT_MASK_SW_DEFINED_PAGE1_V1_8822C 0xffffffffL +#define BIT_SW_DEFINED_PAGE1_V1_8822C(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8822C) \ + << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C) +#define BITS_SW_DEFINED_PAGE1_V1_8822C \ + (BIT_MASK_SW_DEFINED_PAGE1_V1_8822C \ + << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C) +#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8822C(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE1_V1_8822C)) +#define BIT_GET_SW_DEFINED_PAGE1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C) & \ + BIT_MASK_SW_DEFINED_PAGE1_V1_8822C) +#define BIT_SET_SW_DEFINED_PAGE1_V1_8822C(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1_V1_8822C(x) | \ + BIT_SW_DEFINED_PAGE1_V1_8822C(v)) + +/* 2 REG_SW_DEFINED_PAGE2_8822C */ + +#define BIT_SHIFT_SW_DEFINED_PAGE2_8822C 0 +#define BIT_MASK_SW_DEFINED_PAGE2_8822C 0xffffffffL +#define BIT_SW_DEFINED_PAGE2_8822C(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE2_8822C) \ + << BIT_SHIFT_SW_DEFINED_PAGE2_8822C) +#define BITS_SW_DEFINED_PAGE2_8822C \ + (BIT_MASK_SW_DEFINED_PAGE2_8822C << BIT_SHIFT_SW_DEFINED_PAGE2_8822C) +#define BIT_CLEAR_SW_DEFINED_PAGE2_8822C(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE2_8822C)) +#define BIT_GET_SW_DEFINED_PAGE2_8822C(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8822C) & \ + BIT_MASK_SW_DEFINED_PAGE2_8822C) +#define BIT_SET_SW_DEFINED_PAGE2_8822C(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE2_8822C(x) | BIT_SW_DEFINED_PAGE2_8822C(v)) + +/* 2 REG_MCUTST_I_8822C */ + +#define BIT_SHIFT_MCUDMSG_I_8822C 0 +#define BIT_MASK_MCUDMSG_I_8822C 0xffffffffL +#define BIT_MCUDMSG_I_8822C(x) \ + (((x) & BIT_MASK_MCUDMSG_I_8822C) << BIT_SHIFT_MCUDMSG_I_8822C) +#define BITS_MCUDMSG_I_8822C \ + (BIT_MASK_MCUDMSG_I_8822C << BIT_SHIFT_MCUDMSG_I_8822C) +#define BIT_CLEAR_MCUDMSG_I_8822C(x) ((x) & (~BITS_MCUDMSG_I_8822C)) +#define BIT_GET_MCUDMSG_I_8822C(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_I_8822C) & BIT_MASK_MCUDMSG_I_8822C) +#define BIT_SET_MCUDMSG_I_8822C(x, v) \ + (BIT_CLEAR_MCUDMSG_I_8822C(x) | BIT_MCUDMSG_I_8822C(v)) + +/* 2 REG_MCUTST_II_8822C */ + +#define BIT_SHIFT_MCUDMSG_II_8822C 0 +#define BIT_MASK_MCUDMSG_II_8822C 0xffffffffL +#define BIT_MCUDMSG_II_8822C(x) \ + (((x) & BIT_MASK_MCUDMSG_II_8822C) << BIT_SHIFT_MCUDMSG_II_8822C) +#define BITS_MCUDMSG_II_8822C \ + (BIT_MASK_MCUDMSG_II_8822C << BIT_SHIFT_MCUDMSG_II_8822C) +#define BIT_CLEAR_MCUDMSG_II_8822C(x) ((x) & (~BITS_MCUDMSG_II_8822C)) +#define BIT_GET_MCUDMSG_II_8822C(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_II_8822C) & BIT_MASK_MCUDMSG_II_8822C) +#define BIT_SET_MCUDMSG_II_8822C(x, v) \ + (BIT_CLEAR_MCUDMSG_II_8822C(x) | BIT_MCUDMSG_II_8822C(v)) + +/* 2 REG_FMETHR_8822C */ +#define BIT_FMSG_INT_8822C BIT(31) + +#define BIT_SHIFT_FW_MSG_8822C 0 +#define BIT_MASK_FW_MSG_8822C 0xffffffffL +#define BIT_FW_MSG_8822C(x) \ + (((x) & BIT_MASK_FW_MSG_8822C) << BIT_SHIFT_FW_MSG_8822C) +#define BITS_FW_MSG_8822C (BIT_MASK_FW_MSG_8822C << BIT_SHIFT_FW_MSG_8822C) +#define BIT_CLEAR_FW_MSG_8822C(x) ((x) & (~BITS_FW_MSG_8822C)) +#define BIT_GET_FW_MSG_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG_8822C) & BIT_MASK_FW_MSG_8822C) +#define BIT_SET_FW_MSG_8822C(x, v) \ + (BIT_CLEAR_FW_MSG_8822C(x) | BIT_FW_MSG_8822C(v)) + +/* 2 REG_HMETFR_8822C */ + +#define BIT_SHIFT_HRCV_MSG_8822C 24 +#define BIT_MASK_HRCV_MSG_8822C 0xff +#define BIT_HRCV_MSG_8822C(x) \ + (((x) & BIT_MASK_HRCV_MSG_8822C) << BIT_SHIFT_HRCV_MSG_8822C) +#define BITS_HRCV_MSG_8822C \ + (BIT_MASK_HRCV_MSG_8822C << BIT_SHIFT_HRCV_MSG_8822C) +#define BIT_CLEAR_HRCV_MSG_8822C(x) ((x) & (~BITS_HRCV_MSG_8822C)) +#define BIT_GET_HRCV_MSG_8822C(x) \ + (((x) >> BIT_SHIFT_HRCV_MSG_8822C) & BIT_MASK_HRCV_MSG_8822C) +#define BIT_SET_HRCV_MSG_8822C(x, v) \ + (BIT_CLEAR_HRCV_MSG_8822C(x) | BIT_HRCV_MSG_8822C(v)) + +#define BIT_INT_BOX3_8822C BIT(3) +#define BIT_INT_BOX2_8822C BIT(2) +#define BIT_INT_BOX1_8822C BIT(1) +#define BIT_INT_BOX0_8822C BIT(0) + +/* 2 REG_HMEBOX0_8822C */ + +#define BIT_SHIFT_HOST_MSG_0_8822C 0 +#define BIT_MASK_HOST_MSG_0_8822C 0xffffffffL +#define BIT_HOST_MSG_0_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_0_8822C) << BIT_SHIFT_HOST_MSG_0_8822C) +#define BITS_HOST_MSG_0_8822C \ + (BIT_MASK_HOST_MSG_0_8822C << BIT_SHIFT_HOST_MSG_0_8822C) +#define BIT_CLEAR_HOST_MSG_0_8822C(x) ((x) & (~BITS_HOST_MSG_0_8822C)) +#define BIT_GET_HOST_MSG_0_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_0_8822C) & BIT_MASK_HOST_MSG_0_8822C) +#define BIT_SET_HOST_MSG_0_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_0_8822C(x) | BIT_HOST_MSG_0_8822C(v)) + +/* 2 REG_HMEBOX1_8822C */ + +#define BIT_SHIFT_HOST_MSG_1_8822C 0 +#define BIT_MASK_HOST_MSG_1_8822C 0xffffffffL +#define BIT_HOST_MSG_1_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_1_8822C) << BIT_SHIFT_HOST_MSG_1_8822C) +#define BITS_HOST_MSG_1_8822C \ + (BIT_MASK_HOST_MSG_1_8822C << BIT_SHIFT_HOST_MSG_1_8822C) +#define BIT_CLEAR_HOST_MSG_1_8822C(x) ((x) & (~BITS_HOST_MSG_1_8822C)) +#define BIT_GET_HOST_MSG_1_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_1_8822C) & BIT_MASK_HOST_MSG_1_8822C) +#define BIT_SET_HOST_MSG_1_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_1_8822C(x) | BIT_HOST_MSG_1_8822C(v)) + +/* 2 REG_HMEBOX2_8822C */ + +#define BIT_SHIFT_HOST_MSG_2_8822C 0 +#define BIT_MASK_HOST_MSG_2_8822C 0xffffffffL +#define BIT_HOST_MSG_2_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_2_8822C) << BIT_SHIFT_HOST_MSG_2_8822C) +#define BITS_HOST_MSG_2_8822C \ + (BIT_MASK_HOST_MSG_2_8822C << BIT_SHIFT_HOST_MSG_2_8822C) +#define BIT_CLEAR_HOST_MSG_2_8822C(x) ((x) & (~BITS_HOST_MSG_2_8822C)) +#define BIT_GET_HOST_MSG_2_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_2_8822C) & BIT_MASK_HOST_MSG_2_8822C) +#define BIT_SET_HOST_MSG_2_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_2_8822C(x) | BIT_HOST_MSG_2_8822C(v)) + +/* 2 REG_HMEBOX3_8822C */ + +#define BIT_SHIFT_HOST_MSG_3_8822C 0 +#define BIT_MASK_HOST_MSG_3_8822C 0xffffffffL +#define BIT_HOST_MSG_3_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_3_8822C) << BIT_SHIFT_HOST_MSG_3_8822C) +#define BITS_HOST_MSG_3_8822C \ + (BIT_MASK_HOST_MSG_3_8822C << BIT_SHIFT_HOST_MSG_3_8822C) +#define BIT_CLEAR_HOST_MSG_3_8822C(x) ((x) & (~BITS_HOST_MSG_3_8822C)) +#define BIT_GET_HOST_MSG_3_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_3_8822C) & BIT_MASK_HOST_MSG_3_8822C) +#define BIT_SET_HOST_MSG_3_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_3_8822C(x) | BIT_HOST_MSG_3_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_BB_ACCESS_CTRL_8822C */ + +#define BIT_SHIFT_BB_WRITE_READ_8822C 30 +#define BIT_MASK_BB_WRITE_READ_8822C 0x3 +#define BIT_BB_WRITE_READ_8822C(x) \ + (((x) & BIT_MASK_BB_WRITE_READ_8822C) << BIT_SHIFT_BB_WRITE_READ_8822C) +#define BITS_BB_WRITE_READ_8822C \ + (BIT_MASK_BB_WRITE_READ_8822C << BIT_SHIFT_BB_WRITE_READ_8822C) +#define BIT_CLEAR_BB_WRITE_READ_8822C(x) ((x) & (~BITS_BB_WRITE_READ_8822C)) +#define BIT_GET_BB_WRITE_READ_8822C(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_READ_8822C) & BIT_MASK_BB_WRITE_READ_8822C) +#define BIT_SET_BB_WRITE_READ_8822C(x, v) \ + (BIT_CLEAR_BB_WRITE_READ_8822C(x) | BIT_BB_WRITE_READ_8822C(v)) + +#define BIT_SHIFT_BB_WRITE_EN_8822C 12 +#define BIT_MASK_BB_WRITE_EN_8822C 0xf +#define BIT_BB_WRITE_EN_8822C(x) \ + (((x) & BIT_MASK_BB_WRITE_EN_8822C) << BIT_SHIFT_BB_WRITE_EN_8822C) +#define BITS_BB_WRITE_EN_8822C \ + (BIT_MASK_BB_WRITE_EN_8822C << BIT_SHIFT_BB_WRITE_EN_8822C) +#define BIT_CLEAR_BB_WRITE_EN_8822C(x) ((x) & (~BITS_BB_WRITE_EN_8822C)) +#define BIT_GET_BB_WRITE_EN_8822C(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN_8822C) & BIT_MASK_BB_WRITE_EN_8822C) +#define BIT_SET_BB_WRITE_EN_8822C(x, v) \ + (BIT_CLEAR_BB_WRITE_EN_8822C(x) | BIT_BB_WRITE_EN_8822C(v)) + +#define BIT_SHIFT_BB_ADDR_8822C 2 +#define BIT_MASK_BB_ADDR_8822C 0x1ff +#define BIT_BB_ADDR_8822C(x) \ + (((x) & BIT_MASK_BB_ADDR_8822C) << BIT_SHIFT_BB_ADDR_8822C) +#define BITS_BB_ADDR_8822C (BIT_MASK_BB_ADDR_8822C << BIT_SHIFT_BB_ADDR_8822C) +#define BIT_CLEAR_BB_ADDR_8822C(x) ((x) & (~BITS_BB_ADDR_8822C)) +#define BIT_GET_BB_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_BB_ADDR_8822C) & BIT_MASK_BB_ADDR_8822C) +#define BIT_SET_BB_ADDR_8822C(x, v) \ + (BIT_CLEAR_BB_ADDR_8822C(x) | BIT_BB_ADDR_8822C(v)) + +#define BIT_BB_ERRACC_8822C BIT(0) + +/* 2 REG_BB_ACCESS_DATA_8822C */ + +#define BIT_SHIFT_BB_DATA_8822C 0 +#define BIT_MASK_BB_DATA_8822C 0xffffffffL +#define BIT_BB_DATA_8822C(x) \ + (((x) & BIT_MASK_BB_DATA_8822C) << BIT_SHIFT_BB_DATA_8822C) +#define BITS_BB_DATA_8822C (BIT_MASK_BB_DATA_8822C << BIT_SHIFT_BB_DATA_8822C) +#define BIT_CLEAR_BB_DATA_8822C(x) ((x) & (~BITS_BB_DATA_8822C)) +#define BIT_GET_BB_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_BB_DATA_8822C) & BIT_MASK_BB_DATA_8822C) +#define BIT_SET_BB_DATA_8822C(x, v) \ + (BIT_CLEAR_BB_DATA_8822C(x) | BIT_BB_DATA_8822C(v)) + +/* 2 REG_HMEBOX_E0_8822C */ + +#define BIT_SHIFT_HMEBOX_E0_8822C 0 +#define BIT_MASK_HMEBOX_E0_8822C 0xffffffffL +#define BIT_HMEBOX_E0_8822C(x) \ + (((x) & BIT_MASK_HMEBOX_E0_8822C) << BIT_SHIFT_HMEBOX_E0_8822C) +#define BITS_HMEBOX_E0_8822C \ + (BIT_MASK_HMEBOX_E0_8822C << BIT_SHIFT_HMEBOX_E0_8822C) +#define BIT_CLEAR_HMEBOX_E0_8822C(x) ((x) & (~BITS_HMEBOX_E0_8822C)) +#define BIT_GET_HMEBOX_E0_8822C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E0_8822C) & BIT_MASK_HMEBOX_E0_8822C) +#define BIT_SET_HMEBOX_E0_8822C(x, v) \ + (BIT_CLEAR_HMEBOX_E0_8822C(x) | BIT_HMEBOX_E0_8822C(v)) + +/* 2 REG_HMEBOX_E1_8822C */ + +#define BIT_SHIFT_HMEBOX_E1_8822C 0 +#define BIT_MASK_HMEBOX_E1_8822C 0xffffffffL +#define BIT_HMEBOX_E1_8822C(x) \ + (((x) & BIT_MASK_HMEBOX_E1_8822C) << BIT_SHIFT_HMEBOX_E1_8822C) +#define BITS_HMEBOX_E1_8822C \ + (BIT_MASK_HMEBOX_E1_8822C << BIT_SHIFT_HMEBOX_E1_8822C) +#define BIT_CLEAR_HMEBOX_E1_8822C(x) ((x) & (~BITS_HMEBOX_E1_8822C)) +#define BIT_GET_HMEBOX_E1_8822C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E1_8822C) & BIT_MASK_HMEBOX_E1_8822C) +#define BIT_SET_HMEBOX_E1_8822C(x, v) \ + (BIT_CLEAR_HMEBOX_E1_8822C(x) | BIT_HMEBOX_E1_8822C(v)) + +/* 2 REG_HMEBOX_E2_8822C */ + +#define BIT_SHIFT_HMEBOX_E2_8822C 0 +#define BIT_MASK_HMEBOX_E2_8822C 0xffffffffL +#define BIT_HMEBOX_E2_8822C(x) \ + (((x) & BIT_MASK_HMEBOX_E2_8822C) << BIT_SHIFT_HMEBOX_E2_8822C) +#define BITS_HMEBOX_E2_8822C \ + (BIT_MASK_HMEBOX_E2_8822C << BIT_SHIFT_HMEBOX_E2_8822C) +#define BIT_CLEAR_HMEBOX_E2_8822C(x) ((x) & (~BITS_HMEBOX_E2_8822C)) +#define BIT_GET_HMEBOX_E2_8822C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E2_8822C) & BIT_MASK_HMEBOX_E2_8822C) +#define BIT_SET_HMEBOX_E2_8822C(x, v) \ + (BIT_CLEAR_HMEBOX_E2_8822C(x) | BIT_HMEBOX_E2_8822C(v)) + +/* 2 REG_HMEBOX_E3_8822C */ + +#define BIT_SHIFT_HMEBOX_E3_8822C 0 +#define BIT_MASK_HMEBOX_E3_8822C 0xffffffffL +#define BIT_HMEBOX_E3_8822C(x) \ + (((x) & BIT_MASK_HMEBOX_E3_8822C) << BIT_SHIFT_HMEBOX_E3_8822C) +#define BITS_HMEBOX_E3_8822C \ + (BIT_MASK_HMEBOX_E3_8822C << BIT_SHIFT_HMEBOX_E3_8822C) +#define BIT_CLEAR_HMEBOX_E3_8822C(x) ((x) & (~BITS_HMEBOX_E3_8822C)) +#define BIT_GET_HMEBOX_E3_8822C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E3_8822C) & BIT_MASK_HMEBOX_E3_8822C) +#define BIT_SET_HMEBOX_E3_8822C(x, v) \ + (BIT_CLEAR_HMEBOX_E3_8822C(x) | BIT_HMEBOX_E3_8822C(v)) + +/* 2 REG_CR_EXT_8822C */ + +#define BIT_SHIFT_PHY_REQ_DELAY_8822C 24 +#define BIT_MASK_PHY_REQ_DELAY_8822C 0xf +#define BIT_PHY_REQ_DELAY_8822C(x) \ + (((x) & BIT_MASK_PHY_REQ_DELAY_8822C) << BIT_SHIFT_PHY_REQ_DELAY_8822C) +#define BITS_PHY_REQ_DELAY_8822C \ + (BIT_MASK_PHY_REQ_DELAY_8822C << BIT_SHIFT_PHY_REQ_DELAY_8822C) +#define BIT_CLEAR_PHY_REQ_DELAY_8822C(x) ((x) & (~BITS_PHY_REQ_DELAY_8822C)) +#define BIT_GET_PHY_REQ_DELAY_8822C(x) \ + (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822C) & BIT_MASK_PHY_REQ_DELAY_8822C) +#define BIT_SET_PHY_REQ_DELAY_8822C(x, v) \ + (BIT_CLEAR_PHY_REQ_DELAY_8822C(x) | BIT_PHY_REQ_DELAY_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_SPD_DOWN_8822C BIT(16) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_NETYPE4_8822C 4 +#define BIT_MASK_NETYPE4_8822C 0x3 +#define BIT_NETYPE4_8822C(x) \ + (((x) & BIT_MASK_NETYPE4_8822C) << BIT_SHIFT_NETYPE4_8822C) +#define BITS_NETYPE4_8822C (BIT_MASK_NETYPE4_8822C << BIT_SHIFT_NETYPE4_8822C) +#define BIT_CLEAR_NETYPE4_8822C(x) ((x) & (~BITS_NETYPE4_8822C)) +#define BIT_GET_NETYPE4_8822C(x) \ + (((x) >> BIT_SHIFT_NETYPE4_8822C) & BIT_MASK_NETYPE4_8822C) +#define BIT_SET_NETYPE4_8822C(x, v) \ + (BIT_CLEAR_NETYPE4_8822C(x) | BIT_NETYPE4_8822C(v)) + +#define BIT_SHIFT_NETYPE3_8822C 2 +#define BIT_MASK_NETYPE3_8822C 0x3 +#define BIT_NETYPE3_8822C(x) \ + (((x) & BIT_MASK_NETYPE3_8822C) << BIT_SHIFT_NETYPE3_8822C) +#define BITS_NETYPE3_8822C (BIT_MASK_NETYPE3_8822C << BIT_SHIFT_NETYPE3_8822C) +#define BIT_CLEAR_NETYPE3_8822C(x) ((x) & (~BITS_NETYPE3_8822C)) +#define BIT_GET_NETYPE3_8822C(x) \ + (((x) >> BIT_SHIFT_NETYPE3_8822C) & BIT_MASK_NETYPE3_8822C) +#define BIT_SET_NETYPE3_8822C(x, v) \ + (BIT_CLEAR_NETYPE3_8822C(x) | BIT_NETYPE3_8822C(v)) + +#define BIT_SHIFT_NETYPE2_8822C 0 +#define BIT_MASK_NETYPE2_8822C 0x3 +#define BIT_NETYPE2_8822C(x) \ + (((x) & BIT_MASK_NETYPE2_8822C) << BIT_SHIFT_NETYPE2_8822C) +#define BITS_NETYPE2_8822C (BIT_MASK_NETYPE2_8822C << BIT_SHIFT_NETYPE2_8822C) +#define BIT_CLEAR_NETYPE2_8822C(x) ((x) & (~BITS_NETYPE2_8822C)) +#define BIT_GET_NETYPE2_8822C(x) \ + (((x) >> BIT_SHIFT_NETYPE2_8822C) & BIT_MASK_NETYPE2_8822C) +#define BIT_SET_NETYPE2_8822C(x, v) \ + (BIT_CLEAR_NETYPE2_8822C(x) | BIT_NETYPE2_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_FWFF_8822C */ + +#define BIT_SHIFT_PKTNUM_TH_V1_8822C 24 +#define BIT_MASK_PKTNUM_TH_V1_8822C 0xff +#define BIT_PKTNUM_TH_V1_8822C(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V1_8822C) << BIT_SHIFT_PKTNUM_TH_V1_8822C) +#define BITS_PKTNUM_TH_V1_8822C \ + (BIT_MASK_PKTNUM_TH_V1_8822C << BIT_SHIFT_PKTNUM_TH_V1_8822C) +#define BIT_CLEAR_PKTNUM_TH_V1_8822C(x) ((x) & (~BITS_PKTNUM_TH_V1_8822C)) +#define BIT_GET_PKTNUM_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822C) & BIT_MASK_PKTNUM_TH_V1_8822C) +#define BIT_SET_PKTNUM_TH_V1_8822C(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V1_8822C(x) | BIT_PKTNUM_TH_V1_8822C(v)) + +#define BIT_SHIFT_TIMER_TH_8822C 16 +#define BIT_MASK_TIMER_TH_8822C 0xff +#define BIT_TIMER_TH_8822C(x) \ + (((x) & BIT_MASK_TIMER_TH_8822C) << BIT_SHIFT_TIMER_TH_8822C) +#define BITS_TIMER_TH_8822C \ + (BIT_MASK_TIMER_TH_8822C << BIT_SHIFT_TIMER_TH_8822C) +#define BIT_CLEAR_TIMER_TH_8822C(x) ((x) & (~BITS_TIMER_TH_8822C)) +#define BIT_GET_TIMER_TH_8822C(x) \ + (((x) >> BIT_SHIFT_TIMER_TH_8822C) & BIT_MASK_TIMER_TH_8822C) +#define BIT_SET_TIMER_TH_8822C(x, v) \ + (BIT_CLEAR_TIMER_TH_8822C(x) | BIT_TIMER_TH_8822C(v)) + +#define BIT_SHIFT_RXPKT1ENADDR_8822C 0 +#define BIT_MASK_RXPKT1ENADDR_8822C 0xffff +#define BIT_RXPKT1ENADDR_8822C(x) \ + (((x) & BIT_MASK_RXPKT1ENADDR_8822C) << BIT_SHIFT_RXPKT1ENADDR_8822C) +#define BITS_RXPKT1ENADDR_8822C \ + (BIT_MASK_RXPKT1ENADDR_8822C << BIT_SHIFT_RXPKT1ENADDR_8822C) +#define BIT_CLEAR_RXPKT1ENADDR_8822C(x) ((x) & (~BITS_RXPKT1ENADDR_8822C)) +#define BIT_GET_RXPKT1ENADDR_8822C(x) \ + (((x) >> BIT_SHIFT_RXPKT1ENADDR_8822C) & BIT_MASK_RXPKT1ENADDR_8822C) +#define BIT_SET_RXPKT1ENADDR_8822C(x, v) \ + (BIT_CLEAR_RXPKT1ENADDR_8822C(x) | BIT_RXPKT1ENADDR_8822C(v)) + +/* 2 REG_RXFF_PTR_V1_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_RXFF0_RDPTR_V2_8822C 0 +#define BIT_MASK_RXFF0_RDPTR_V2_8822C 0x3ffff +#define BIT_RXFF0_RDPTR_V2_8822C(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V2_8822C) \ + << BIT_SHIFT_RXFF0_RDPTR_V2_8822C) +#define BITS_RXFF0_RDPTR_V2_8822C \ + (BIT_MASK_RXFF0_RDPTR_V2_8822C << BIT_SHIFT_RXFF0_RDPTR_V2_8822C) +#define BIT_CLEAR_RXFF0_RDPTR_V2_8822C(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8822C)) +#define BIT_GET_RXFF0_RDPTR_V2_8822C(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822C) & \ + BIT_MASK_RXFF0_RDPTR_V2_8822C) +#define BIT_SET_RXFF0_RDPTR_V2_8822C(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V2_8822C(x) | BIT_RXFF0_RDPTR_V2_8822C(v)) + +/* 2 REG_RXFF_WTR_V1_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_RXFF0_WTPTR_V2_8822C 0 +#define BIT_MASK_RXFF0_WTPTR_V2_8822C 0x3ffff +#define BIT_RXFF0_WTPTR_V2_8822C(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V2_8822C) \ + << BIT_SHIFT_RXFF0_WTPTR_V2_8822C) +#define BITS_RXFF0_WTPTR_V2_8822C \ + (BIT_MASK_RXFF0_WTPTR_V2_8822C << BIT_SHIFT_RXFF0_WTPTR_V2_8822C) +#define BIT_CLEAR_RXFF0_WTPTR_V2_8822C(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8822C)) +#define BIT_GET_RXFF0_WTPTR_V2_8822C(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822C) & \ + BIT_MASK_RXFF0_WTPTR_V2_8822C) +#define BIT_SET_RXFF0_WTPTR_V2_8822C(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V2_8822C(x) | BIT_RXFF0_WTPTR_V2_8822C(v)) + +/* 2 REG_FE2IMR_8822C */ +#define BIT__FE4ISR__IND_MSK_8822C BIT(29) +#define BIT_FS_TXSC_DESC_DONE_INT_EN_8822C BIT(28) +#define BIT_FS_TXSC_BKDONE_INT_EN_8822C BIT(27) +#define BIT_FS_TXSC_BEDONE_INT_EN_8822C BIT(26) +#define BIT_FS_TXSC_VIDONE_INT_EN_8822C BIT(25) +#define BIT_FS_TXSC_VODONE_INT_EN_8822C BIT(24) +#define BIT_FS_ATIM_MB7_INT_EN_8822C BIT(23) +#define BIT_FS_ATIM_MB6_INT_EN_8822C BIT(22) +#define BIT_FS_ATIM_MB5_INT_EN_8822C BIT(21) +#define BIT_FS_ATIM_MB4_INT_EN_8822C BIT(20) +#define BIT_FS_ATIM_MB3_INT_EN_8822C BIT(19) +#define BIT_FS_ATIM_MB2_INT_EN_8822C BIT(18) +#define BIT_FS_ATIM_MB1_INT_EN_8822C BIT(17) +#define BIT_FS_ATIM_MB0_INT_EN_8822C BIT(16) +#define BIT_FS_TBTT4INT_EN_8822C BIT(11) +#define BIT_FS_TBTT3INT_EN_8822C BIT(10) +#define BIT_FS_TBTT2INT_EN_8822C BIT(9) +#define BIT_FS_TBTT1INT_EN_8822C BIT(8) +#define BIT_FS_TBTT0_MB7INT_EN_8822C BIT(7) +#define BIT_FS_TBTT0_MB6INT_EN_8822C BIT(6) +#define BIT_FS_TBTT0_MB5INT_EN_8822C BIT(5) +#define BIT_FS_TBTT0_MB4INT_EN_8822C BIT(4) +#define BIT_FS_TBTT0_MB3INT_EN_8822C BIT(3) +#define BIT_FS_TBTT0_MB2INT_EN_8822C BIT(2) +#define BIT_FS_TBTT0_MB1INT_EN_8822C BIT(1) +#define BIT_FS_TBTT0_INT_EN_8822C BIT(0) + +/* 2 REG_FE2ISR_8822C */ +#define BIT__FE4ISR__IND_INT_8822C BIT(29) +#define BIT_FS_TXSC_DESC_DONE_INT_8822C BIT(28) +#define BIT_FS_TXSC_BKDONE_INT_8822C BIT(27) +#define BIT_FS_TXSC_BEDONE_INT_8822C BIT(26) +#define BIT_FS_TXSC_VIDONE_INT_8822C BIT(25) +#define BIT_FS_TXSC_VODONE_INT_8822C BIT(24) +#define BIT_FS_ATIM_MB7_INT_8822C BIT(23) +#define BIT_FS_ATIM_MB6_INT_8822C BIT(22) +#define BIT_FS_ATIM_MB5_INT_8822C BIT(21) +#define BIT_FS_ATIM_MB4_INT_8822C BIT(20) +#define BIT_FS_ATIM_MB3_INT_8822C BIT(19) +#define BIT_FS_ATIM_MB2_INT_8822C BIT(18) +#define BIT_FS_ATIM_MB1_INT_8822C BIT(17) +#define BIT_FS_ATIM_MB0_INT_8822C BIT(16) +#define BIT_FS_TBTT4INT_8822C BIT(11) +#define BIT_FS_TBTT3INT_8822C BIT(10) +#define BIT_FS_TBTT2INT_8822C BIT(9) +#define BIT_FS_TBTT1INT_8822C BIT(8) +#define BIT_FS_TBTT0_MB7INT_8822C BIT(7) +#define BIT_FS_TBTT0_MB6INT_8822C BIT(6) +#define BIT_FS_TBTT0_MB5INT_8822C BIT(5) +#define BIT_FS_TBTT0_MB4INT_8822C BIT(4) +#define BIT_FS_TBTT0_MB3INT_8822C BIT(3) +#define BIT_FS_TBTT0_MB2INT_8822C BIT(2) +#define BIT_FS_TBTT0_MB1INT_8822C BIT(1) +#define BIT_FS_TBTT0_INT_8822C BIT(0) + +/* 2 REG_FE3IMR_8822C */ +#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8822C BIT(31) +#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8822C BIT(30) +#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8822C BIT(29) +#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8822C BIT(28) +#define BIT_FS_BCNDMA4_INT_EN_8822C BIT(27) +#define BIT_FS_BCNDMA3_INT_EN_8822C BIT(26) +#define BIT_FS_BCNDMA2_INT_EN_8822C BIT(25) +#define BIT_FS_BCNDMA1_INT_EN_8822C BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT_EN_8822C BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT_EN_8822C BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT_EN_8822C BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT_EN_8822C BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT_EN_8822C BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT_EN_8822C BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT_EN_8822C BIT(17) +#define BIT_FS_BCNDMA0_INT_EN_8822C BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8822C BIT(15) +#define BIT_FS_BCNERLY4_INT_EN_8822C BIT(11) +#define BIT_FS_BCNERLY3_INT_EN_8822C BIT(10) +#define BIT_FS_BCNERLY2_INT_EN_8822C BIT(9) +#define BIT_FS_BCNERLY1_INT_EN_8822C BIT(8) +#define BIT_FS_BCNERLY0_MB7INT_EN_8822C BIT(7) +#define BIT_FS_BCNERLY0_MB6INT_EN_8822C BIT(6) +#define BIT_FS_BCNERLY0_MB5INT_EN_8822C BIT(5) +#define BIT_FS_BCNERLY0_MB4INT_EN_8822C BIT(4) +#define BIT_FS_BCNERLY0_MB3INT_EN_8822C BIT(3) +#define BIT_FS_BCNERLY0_MB2INT_EN_8822C BIT(2) +#define BIT_FS_BCNERLY0_MB1INT_EN_8822C BIT(1) +#define BIT_FS_BCNERLY0_INT_EN_8822C BIT(0) + +/* 2 REG_FE3ISR_8822C */ +#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8822C BIT(31) +#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8822C BIT(30) +#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8822C BIT(29) +#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8822C BIT(28) +#define BIT_FS_BCNDMA4_INT_8822C BIT(27) +#define BIT_FS_BCNDMA3_INT_8822C BIT(26) +#define BIT_FS_BCNDMA2_INT_8822C BIT(25) +#define BIT_FS_BCNDMA1_INT_8822C BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT_8822C BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT_8822C BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT_8822C BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT_8822C BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT_8822C BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT_8822C BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT_8822C BIT(17) +#define BIT_FS_BCNDMA0_INT_8822C BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT_8822C BIT(15) +#define BIT_FS_BCNERLY4_INT_8822C BIT(11) +#define BIT_FS_BCNERLY3_INT_8822C BIT(10) +#define BIT_FS_BCNERLY2_INT_8822C BIT(9) +#define BIT_FS_BCNERLY1_INT_8822C BIT(8) +#define BIT_FS_BCNERLY0_MB7INT_8822C BIT(7) +#define BIT_FS_BCNERLY0_MB6INT_8822C BIT(6) +#define BIT_FS_BCNERLY0_MB5INT_8822C BIT(5) +#define BIT_FS_BCNERLY0_MB4INT_8822C BIT(4) +#define BIT_FS_BCNERLY0_MB3INT_8822C BIT(3) +#define BIT_FS_BCNERLY0_MB2INT_8822C BIT(2) +#define BIT_FS_BCNERLY0_MB1INT_8822C BIT(1) +#define BIT_FS_BCNERLY0_INT_8822C BIT(0) + +/* 2 REG_FE4IMR_8822C */ +#define BIT_FS_CLI3_TXPKTIN_INT_EN_8822C BIT(19) +#define BIT_FS_CLI2_TXPKTIN_INT_EN_8822C BIT(18) +#define BIT_FS_CLI1_TXPKTIN_INT_EN_8822C BIT(17) +#define BIT_FS_CLI0_TXPKTIN_INT_EN_8822C BIT(16) +#define BIT_FS_CLI3_RX_UMD0_INT_EN_8822C BIT(15) +#define BIT_FS_CLI3_RX_UMD1_INT_EN_8822C BIT(14) +#define BIT_FS_CLI3_RX_BMD0_INT_EN_8822C BIT(13) +#define BIT_FS_CLI3_RX_BMD1_INT_EN_8822C BIT(12) +#define BIT_FS_CLI2_RX_UMD0_INT_EN_8822C BIT(11) +#define BIT_FS_CLI2_RX_UMD1_INT_EN_8822C BIT(10) +#define BIT_FS_CLI2_RX_BMD0_INT_EN_8822C BIT(9) +#define BIT_FS_CLI2_RX_BMD1_INT_EN_8822C BIT(8) +#define BIT_FS_CLI1_RX_UMD0_INT_EN_8822C BIT(7) +#define BIT_FS_CLI1_RX_UMD1_INT_EN_8822C BIT(6) +#define BIT_FS_CLI1_RX_BMD0_INT_EN_8822C BIT(5) +#define BIT_FS_CLI1_RX_BMD1_INT_EN_8822C BIT(4) +#define BIT_FS_CLI0_RX_UMD0_INT_EN_8822C BIT(3) +#define BIT_FS_CLI0_RX_UMD1_INT_EN_8822C BIT(2) +#define BIT_FS_CLI0_RX_BMD0_INT_EN_8822C BIT(1) +#define BIT_FS_CLI0_RX_BMD1_INT_EN_8822C BIT(0) + +/* 2 REG_FE4ISR_8822C */ +#define BIT_FS_CLI3_TXPKTIN_INT_8822C BIT(19) +#define BIT_FS_CLI2_TXPKTIN_INT_8822C BIT(18) +#define BIT_FS_CLI1_TXPKTIN_INT_8822C BIT(17) +#define BIT_FS_CLI0_TXPKTIN_INT_8822C BIT(16) +#define BIT_FS_CLI3_RX_UMD0_INT_8822C BIT(15) +#define BIT_FS_CLI3_RX_UMD1_INT_8822C BIT(14) +#define BIT_FS_CLI3_RX_BMD0_INT_8822C BIT(13) +#define BIT_FS_CLI3_RX_BMD1_INT_8822C BIT(12) +#define BIT_FS_CLI2_RX_UMD0_INT_8822C BIT(11) +#define BIT_FS_CLI2_RX_UMD1_INT_8822C BIT(10) +#define BIT_FS_CLI2_RX_BMD0_INT_8822C BIT(9) +#define BIT_FS_CLI2_RX_BMD1_INT_8822C BIT(8) +#define BIT_FS_CLI1_RX_UMD0_INT_8822C BIT(7) +#define BIT_FS_CLI1_RX_UMD1_INT_8822C BIT(6) +#define BIT_FS_CLI1_RX_BMD0_INT_8822C BIT(5) +#define BIT_FS_CLI1_RX_BMD1_INT_8822C BIT(4) +#define BIT_FS_CLI0_RX_UMD0_INT_8822C BIT(3) +#define BIT_FS_CLI0_RX_UMD1_INT_8822C BIT(2) +#define BIT_FS_CLI0_RX_BMD0_INT_8822C BIT(1) +#define BIT_FS_CLI0_RX_BMD1_INT_8822C BIT(0) + +/* 2 REG_FT1IMR_8822C */ +#define BIT__FT2ISR__IND_MSK_8822C BIT(30) +#define BIT_FTM_PTT_INT_EN_8822C BIT(29) +#define BIT_RXFTMREQ_INT_EN_8822C BIT(28) +#define BIT_RXFTM_INT_EN_8822C BIT(27) +#define BIT_TXFTM_INT_EN_8822C BIT(26) +#define BIT_FS_H2C_CMD_OK_INT_EN_8822C BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT_EN_8822C BIT(24) +#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8822C BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8822C BIT(22) +#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8822C BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8822C BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8822C BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8822C BIT(18) +#define BIT_FS_CTWEND2_INT_EN_8822C BIT(17) +#define BIT_FS_CTWEND1_INT_EN_8822C BIT(16) +#define BIT_FS_CTWEND0_INT_EN_8822C BIT(15) +#define BIT_FS_TX_NULL1_INT_EN_8822C BIT(14) +#define BIT_FS_TX_NULL0_INT_EN_8822C BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_EN_8822C BIT(12) +#define BIT_FS_P2P_RFON2_INT_EN_8822C BIT(11) +#define BIT_FS_P2P_RFOFF2_INT_EN_8822C BIT(10) +#define BIT_FS_P2P_RFON1_INT_EN_8822C BIT(9) +#define BIT_FS_P2P_RFOFF1_INT_EN_8822C BIT(8) +#define BIT_FS_P2P_RFON0_INT_EN_8822C BIT(7) +#define BIT_FS_P2P_RFOFF0_INT_EN_8822C BIT(6) +#define BIT_FS_RX_UAPSDMD1_EN_8822C BIT(5) +#define BIT_FS_RX_UAPSDMD0_EN_8822C BIT(4) +#define BIT_FS_TRIGGER_PKT_EN_8822C BIT(3) +#define BIT_FS_EOSP_INT_EN_8822C BIT(2) +#define BIT_FS_RPWM2_INT_EN_8822C BIT(1) +#define BIT_FS_RPWM_INT_EN_8822C BIT(0) + +/* 2 REG_FT1ISR_8822C */ +#define BIT__FT2ISR__IND_INT_8822C BIT(30) +#define BIT_FTM_PTT_INT_8822C BIT(29) +#define BIT_RXFTMREQ_INT_8822C BIT(28) +#define BIT_RXFTM_INT_8822C BIT(27) +#define BIT_TXFTM_INT_8822C BIT(26) +#define BIT_FS_H2C_CMD_OK_INT_8822C BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT_8822C BIT(24) +#define BIT_FS_MACID_PWRCHANGE5_INT_8822C BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT_8822C BIT(22) +#define BIT_FS_MACID_PWRCHANGE3_INT_8822C BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT_8822C BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT_8822C BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT_8822C BIT(18) +#define BIT_FS_CTWEND2_INT_8822C BIT(17) +#define BIT_FS_CTWEND1_INT_8822C BIT(16) +#define BIT_FS_CTWEND0_INT_8822C BIT(15) +#define BIT_FS_TX_NULL1_INT_8822C BIT(14) +#define BIT_FS_TX_NULL0_INT_8822C BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_INT_8822C BIT(12) +#define BIT_FS_P2P_RFON2_INT_8822C BIT(11) +#define BIT_FS_P2P_RFOFF2_INT_8822C BIT(10) +#define BIT_FS_P2P_RFON1_INT_8822C BIT(9) +#define BIT_FS_P2P_RFOFF1_INT_8822C BIT(8) +#define BIT_FS_P2P_RFON0_INT_8822C BIT(7) +#define BIT_FS_P2P_RFOFF0_INT_8822C BIT(6) +#define BIT_FS_RX_UAPSDMD1_INT_8822C BIT(5) +#define BIT_FS_RX_UAPSDMD0_INT_8822C BIT(4) +#define BIT_FS_TRIGGER_PKT_INT_8822C BIT(3) +#define BIT_FS_EOSP_INT_8822C BIT(2) +#define BIT_FS_RPWM2_INT_8822C BIT(1) +#define BIT_FS_RPWM_INT_8822C BIT(0) + +/* 2 REG_SPWR0_8822C */ + +#define BIT_SHIFT_MID_31TO0_8822C 0 +#define BIT_MASK_MID_31TO0_8822C 0xffffffffL +#define BIT_MID_31TO0_8822C(x) \ + (((x) & BIT_MASK_MID_31TO0_8822C) << BIT_SHIFT_MID_31TO0_8822C) +#define BITS_MID_31TO0_8822C \ + (BIT_MASK_MID_31TO0_8822C << BIT_SHIFT_MID_31TO0_8822C) +#define BIT_CLEAR_MID_31TO0_8822C(x) ((x) & (~BITS_MID_31TO0_8822C)) +#define BIT_GET_MID_31TO0_8822C(x) \ + (((x) >> BIT_SHIFT_MID_31TO0_8822C) & BIT_MASK_MID_31TO0_8822C) +#define BIT_SET_MID_31TO0_8822C(x, v) \ + (BIT_CLEAR_MID_31TO0_8822C(x) | BIT_MID_31TO0_8822C(v)) + +/* 2 REG_SPWR1_8822C */ + +#define BIT_SHIFT_MID_63TO32_8822C 0 +#define BIT_MASK_MID_63TO32_8822C 0xffffffffL +#define BIT_MID_63TO32_8822C(x) \ + (((x) & BIT_MASK_MID_63TO32_8822C) << BIT_SHIFT_MID_63TO32_8822C) +#define BITS_MID_63TO32_8822C \ + (BIT_MASK_MID_63TO32_8822C << BIT_SHIFT_MID_63TO32_8822C) +#define BIT_CLEAR_MID_63TO32_8822C(x) ((x) & (~BITS_MID_63TO32_8822C)) +#define BIT_GET_MID_63TO32_8822C(x) \ + (((x) >> BIT_SHIFT_MID_63TO32_8822C) & BIT_MASK_MID_63TO32_8822C) +#define BIT_SET_MID_63TO32_8822C(x, v) \ + (BIT_CLEAR_MID_63TO32_8822C(x) | BIT_MID_63TO32_8822C(v)) + +/* 2 REG_SPWR2_8822C */ + +#define BIT_SHIFT_MID_95O64_8822C 0 +#define BIT_MASK_MID_95O64_8822C 0xffffffffL +#define BIT_MID_95O64_8822C(x) \ + (((x) & BIT_MASK_MID_95O64_8822C) << BIT_SHIFT_MID_95O64_8822C) +#define BITS_MID_95O64_8822C \ + (BIT_MASK_MID_95O64_8822C << BIT_SHIFT_MID_95O64_8822C) +#define BIT_CLEAR_MID_95O64_8822C(x) ((x) & (~BITS_MID_95O64_8822C)) +#define BIT_GET_MID_95O64_8822C(x) \ + (((x) >> BIT_SHIFT_MID_95O64_8822C) & BIT_MASK_MID_95O64_8822C) +#define BIT_SET_MID_95O64_8822C(x, v) \ + (BIT_CLEAR_MID_95O64_8822C(x) | BIT_MID_95O64_8822C(v)) + +/* 2 REG_SPWR3_8822C */ + +#define BIT_SHIFT_MID_127TO96_8822C 0 +#define BIT_MASK_MID_127TO96_8822C 0xffffffffL +#define BIT_MID_127TO96_8822C(x) \ + (((x) & BIT_MASK_MID_127TO96_8822C) << BIT_SHIFT_MID_127TO96_8822C) +#define BITS_MID_127TO96_8822C \ + (BIT_MASK_MID_127TO96_8822C << BIT_SHIFT_MID_127TO96_8822C) +#define BIT_CLEAR_MID_127TO96_8822C(x) ((x) & (~BITS_MID_127TO96_8822C)) +#define BIT_GET_MID_127TO96_8822C(x) \ + (((x) >> BIT_SHIFT_MID_127TO96_8822C) & BIT_MASK_MID_127TO96_8822C) +#define BIT_SET_MID_127TO96_8822C(x, v) \ + (BIT_CLEAR_MID_127TO96_8822C(x) | BIT_MID_127TO96_8822C(v)) + +/* 2 REG_POWSEQ_8822C */ + +#define BIT_SHIFT_SEQNUM_MID_8822C 16 +#define BIT_MASK_SEQNUM_MID_8822C 0xffff +#define BIT_SEQNUM_MID_8822C(x) \ + (((x) & BIT_MASK_SEQNUM_MID_8822C) << BIT_SHIFT_SEQNUM_MID_8822C) +#define BITS_SEQNUM_MID_8822C \ + (BIT_MASK_SEQNUM_MID_8822C << BIT_SHIFT_SEQNUM_MID_8822C) +#define BIT_CLEAR_SEQNUM_MID_8822C(x) ((x) & (~BITS_SEQNUM_MID_8822C)) +#define BIT_GET_SEQNUM_MID_8822C(x) \ + (((x) >> BIT_SHIFT_SEQNUM_MID_8822C) & BIT_MASK_SEQNUM_MID_8822C) +#define BIT_SET_SEQNUM_MID_8822C(x, v) \ + (BIT_CLEAR_SEQNUM_MID_8822C(x) | BIT_SEQNUM_MID_8822C(v)) + +#define BIT_SHIFT_REF_MID_8822C 0 +#define BIT_MASK_REF_MID_8822C 0x7f +#define BIT_REF_MID_8822C(x) \ + (((x) & BIT_MASK_REF_MID_8822C) << BIT_SHIFT_REF_MID_8822C) +#define BITS_REF_MID_8822C (BIT_MASK_REF_MID_8822C << BIT_SHIFT_REF_MID_8822C) +#define BIT_CLEAR_REF_MID_8822C(x) ((x) & (~BITS_REF_MID_8822C)) +#define BIT_GET_REF_MID_8822C(x) \ + (((x) >> BIT_SHIFT_REF_MID_8822C) & BIT_MASK_REF_MID_8822C) +#define BIT_SET_REF_MID_8822C(x, v) \ + (BIT_CLEAR_REF_MID_8822C(x) | BIT_REF_MID_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_TC7_CTRL_V1_8822C */ +#define BIT_TC7INT_EN_8822C BIT(26) +#define BIT_TC7MODE_8822C BIT(25) +#define BIT_TC7EN_8822C BIT(24) + +#define BIT_SHIFT_TC7DATA_8822C 0 +#define BIT_MASK_TC7DATA_8822C 0xffffff +#define BIT_TC7DATA_8822C(x) \ + (((x) & BIT_MASK_TC7DATA_8822C) << BIT_SHIFT_TC7DATA_8822C) +#define BITS_TC7DATA_8822C (BIT_MASK_TC7DATA_8822C << BIT_SHIFT_TC7DATA_8822C) +#define BIT_CLEAR_TC7DATA_8822C(x) ((x) & (~BITS_TC7DATA_8822C)) +#define BIT_GET_TC7DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC7DATA_8822C) & BIT_MASK_TC7DATA_8822C) +#define BIT_SET_TC7DATA_8822C(x, v) \ + (BIT_CLEAR_TC7DATA_8822C(x) | BIT_TC7DATA_8822C(v)) + +/* 2 REG_TC8_CTRL_V1_8822C */ +#define BIT_TC8INT_EN_8822C BIT(26) +#define BIT_TC8MODE_8822C BIT(25) +#define BIT_TC8EN_8822C BIT(24) + +#define BIT_SHIFT_TC8DATA_8822C 0 +#define BIT_MASK_TC8DATA_8822C 0xffffff +#define BIT_TC8DATA_8822C(x) \ + (((x) & BIT_MASK_TC8DATA_8822C) << BIT_SHIFT_TC8DATA_8822C) +#define BITS_TC8DATA_8822C (BIT_MASK_TC8DATA_8822C << BIT_SHIFT_TC8DATA_8822C) +#define BIT_CLEAR_TC8DATA_8822C(x) ((x) & (~BITS_TC8DATA_8822C)) +#define BIT_GET_TC8DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC8DATA_8822C) & BIT_MASK_TC8DATA_8822C) +#define BIT_SET_TC8DATA_8822C(x, v) \ + (BIT_CLEAR_TC8DATA_8822C(x) | BIT_TC8DATA_8822C(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL0_8822C */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C 24 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8822C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8822C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT2_8822C(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C 16 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8822C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8822C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT1_8822C(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C 8 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8822C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8822C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT0_8822C(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C 0xff +#define BIT_RX_BCN_TBTT_ITVL_PORT0_8822C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C) +#define BITS_RX_BCN_TBTT_ITVL_PORT0_8822C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8822C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8822C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8822C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C) +#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8822C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8822C(x) | \ + BIT_RX_BCN_TBTT_ITVL_PORT0_8822C(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL1_8822C */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8822C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8822C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT3_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_IO_WRAP_ERR_FLAG_8822C */ +#define BIT_IO_WRAP_ERR_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SPEED_SENSOR_8822C */ +#define BIT_DSS_1_RST_N_8822C BIT(31) +#define BIT_DSS_1_SPEED_EN_8822C BIT(30) +#define BIT_DSS_1_WIRE_SEL_8822C BIT(29) +#define BIT_DSS_ENCLK_8822C BIT(28) + +#define BIT_SHIFT_DSS_1_RO_SEL_8822C 24 +#define BIT_MASK_DSS_1_RO_SEL_8822C 0x7 +#define BIT_DSS_1_RO_SEL_8822C(x) \ + (((x) & BIT_MASK_DSS_1_RO_SEL_8822C) << BIT_SHIFT_DSS_1_RO_SEL_8822C) +#define BITS_DSS_1_RO_SEL_8822C \ + (BIT_MASK_DSS_1_RO_SEL_8822C << BIT_SHIFT_DSS_1_RO_SEL_8822C) +#define BIT_CLEAR_DSS_1_RO_SEL_8822C(x) ((x) & (~BITS_DSS_1_RO_SEL_8822C)) +#define BIT_GET_DSS_1_RO_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_1_RO_SEL_8822C) & BIT_MASK_DSS_1_RO_SEL_8822C) +#define BIT_SET_DSS_1_RO_SEL_8822C(x, v) \ + (BIT_CLEAR_DSS_1_RO_SEL_8822C(x) | BIT_DSS_1_RO_SEL_8822C(v)) + +#define BIT_SHIFT_DSS_1_DATA_IN_8822C 0 +#define BIT_MASK_DSS_1_DATA_IN_8822C 0xfffff +#define BIT_DSS_1_DATA_IN_8822C(x) \ + (((x) & BIT_MASK_DSS_1_DATA_IN_8822C) << BIT_SHIFT_DSS_1_DATA_IN_8822C) +#define BITS_DSS_1_DATA_IN_8822C \ + (BIT_MASK_DSS_1_DATA_IN_8822C << BIT_SHIFT_DSS_1_DATA_IN_8822C) +#define BIT_CLEAR_DSS_1_DATA_IN_8822C(x) ((x) & (~BITS_DSS_1_DATA_IN_8822C)) +#define BIT_GET_DSS_1_DATA_IN_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_1_DATA_IN_8822C) & BIT_MASK_DSS_1_DATA_IN_8822C) +#define BIT_SET_DSS_1_DATA_IN_8822C(x, v) \ + (BIT_CLEAR_DSS_1_DATA_IN_8822C(x) | BIT_DSS_1_DATA_IN_8822C(v)) + +/* 2 REG_SPEED_SENSOR1_8822C */ +#define BIT_DSS_1_READY_8822C BIT(31) +#define BIT_DSS_1_WSORT_GO_8822C BIT(30) + +#define BIT_SHIFT_DSS_1_COUNT_OUT_8822C 0 +#define BIT_MASK_DSS_1_COUNT_OUT_8822C 0xfffff +#define BIT_DSS_1_COUNT_OUT_8822C(x) \ + (((x) & BIT_MASK_DSS_1_COUNT_OUT_8822C) \ + << BIT_SHIFT_DSS_1_COUNT_OUT_8822C) +#define BITS_DSS_1_COUNT_OUT_8822C \ + (BIT_MASK_DSS_1_COUNT_OUT_8822C << BIT_SHIFT_DSS_1_COUNT_OUT_8822C) +#define BIT_CLEAR_DSS_1_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8822C)) +#define BIT_GET_DSS_1_COUNT_OUT_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8822C) & \ + BIT_MASK_DSS_1_COUNT_OUT_8822C) +#define BIT_SET_DSS_1_COUNT_OUT_8822C(x, v) \ + (BIT_CLEAR_DSS_1_COUNT_OUT_8822C(x) | BIT_DSS_1_COUNT_OUT_8822C(v)) + +/* 2 REG_SPEED_SENSOR2_8822C */ +#define BIT_DSS_2_RST_N_8822C BIT(31) +#define BIT_DSS_2_SPEED_EN_8822C BIT(30) +#define BIT_DSS_2_WIRE_SEL_8822C BIT(29) +#define BIT_DSS_ENCLK_8822C BIT(28) + +#define BIT_SHIFT_DSS_2_RO_SEL_8822C 24 +#define BIT_MASK_DSS_2_RO_SEL_8822C 0x7 +#define BIT_DSS_2_RO_SEL_8822C(x) \ + (((x) & BIT_MASK_DSS_2_RO_SEL_8822C) << BIT_SHIFT_DSS_2_RO_SEL_8822C) +#define BITS_DSS_2_RO_SEL_8822C \ + (BIT_MASK_DSS_2_RO_SEL_8822C << BIT_SHIFT_DSS_2_RO_SEL_8822C) +#define BIT_CLEAR_DSS_2_RO_SEL_8822C(x) ((x) & (~BITS_DSS_2_RO_SEL_8822C)) +#define BIT_GET_DSS_2_RO_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_2_RO_SEL_8822C) & BIT_MASK_DSS_2_RO_SEL_8822C) +#define BIT_SET_DSS_2_RO_SEL_8822C(x, v) \ + (BIT_CLEAR_DSS_2_RO_SEL_8822C(x) | BIT_DSS_2_RO_SEL_8822C(v)) + +#define BIT_SHIFT_DSS_2_DATA_IN_8822C 0 +#define BIT_MASK_DSS_2_DATA_IN_8822C 0xfffff +#define BIT_DSS_2_DATA_IN_8822C(x) \ + (((x) & BIT_MASK_DSS_2_DATA_IN_8822C) << BIT_SHIFT_DSS_2_DATA_IN_8822C) +#define BITS_DSS_2_DATA_IN_8822C \ + (BIT_MASK_DSS_2_DATA_IN_8822C << BIT_SHIFT_DSS_2_DATA_IN_8822C) +#define BIT_CLEAR_DSS_2_DATA_IN_8822C(x) ((x) & (~BITS_DSS_2_DATA_IN_8822C)) +#define BIT_GET_DSS_2_DATA_IN_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_2_DATA_IN_8822C) & BIT_MASK_DSS_2_DATA_IN_8822C) +#define BIT_SET_DSS_2_DATA_IN_8822C(x, v) \ + (BIT_CLEAR_DSS_2_DATA_IN_8822C(x) | BIT_DSS_2_DATA_IN_8822C(v)) + +/* 2 REG_SPEED_SENSOR3_8822C */ +#define BIT_DSS_2_READY_8822C BIT(31) +#define BIT_DSS_2_WSORT_GO_8822C BIT(30) + +#define BIT_SHIFT_DSS_2_COUNT_OUT_8822C 0 +#define BIT_MASK_DSS_2_COUNT_OUT_8822C 0xfffff +#define BIT_DSS_2_COUNT_OUT_8822C(x) \ + (((x) & BIT_MASK_DSS_2_COUNT_OUT_8822C) \ + << BIT_SHIFT_DSS_2_COUNT_OUT_8822C) +#define BITS_DSS_2_COUNT_OUT_8822C \ + (BIT_MASK_DSS_2_COUNT_OUT_8822C << BIT_SHIFT_DSS_2_COUNT_OUT_8822C) +#define BIT_CLEAR_DSS_2_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8822C)) +#define BIT_GET_DSS_2_COUNT_OUT_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8822C) & \ + BIT_MASK_DSS_2_COUNT_OUT_8822C) +#define BIT_SET_DSS_2_COUNT_OUT_8822C(x, v) \ + (BIT_CLEAR_DSS_2_COUNT_OUT_8822C(x) | BIT_DSS_2_COUNT_OUT_8822C(v)) + +/* 2 REG_SPEED_SENSOR4_8822C */ +#define BIT_DSS_3_RST_N_8822C BIT(31) +#define BIT_DSS_3_SPEED_EN_8822C BIT(30) +#define BIT_DSS_3_WIRE_SEL_8822C BIT(29) +#define BIT_DSS_ENCLK_8822C BIT(28) + +#define BIT_SHIFT_DSS_3_RO_SEL_8822C 24 +#define BIT_MASK_DSS_3_RO_SEL_8822C 0x7 +#define BIT_DSS_3_RO_SEL_8822C(x) \ + (((x) & BIT_MASK_DSS_3_RO_SEL_8822C) << BIT_SHIFT_DSS_3_RO_SEL_8822C) +#define BITS_DSS_3_RO_SEL_8822C \ + (BIT_MASK_DSS_3_RO_SEL_8822C << BIT_SHIFT_DSS_3_RO_SEL_8822C) +#define BIT_CLEAR_DSS_3_RO_SEL_8822C(x) ((x) & (~BITS_DSS_3_RO_SEL_8822C)) +#define BIT_GET_DSS_3_RO_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_3_RO_SEL_8822C) & BIT_MASK_DSS_3_RO_SEL_8822C) +#define BIT_SET_DSS_3_RO_SEL_8822C(x, v) \ + (BIT_CLEAR_DSS_3_RO_SEL_8822C(x) | BIT_DSS_3_RO_SEL_8822C(v)) + +#define BIT_SHIFT_DSS_3_DATA_IN_8822C 0 +#define BIT_MASK_DSS_3_DATA_IN_8822C 0xfffff +#define BIT_DSS_3_DATA_IN_8822C(x) \ + (((x) & BIT_MASK_DSS_3_DATA_IN_8822C) << BIT_SHIFT_DSS_3_DATA_IN_8822C) +#define BITS_DSS_3_DATA_IN_8822C \ + (BIT_MASK_DSS_3_DATA_IN_8822C << BIT_SHIFT_DSS_3_DATA_IN_8822C) +#define BIT_CLEAR_DSS_3_DATA_IN_8822C(x) ((x) & (~BITS_DSS_3_DATA_IN_8822C)) +#define BIT_GET_DSS_3_DATA_IN_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_3_DATA_IN_8822C) & BIT_MASK_DSS_3_DATA_IN_8822C) +#define BIT_SET_DSS_3_DATA_IN_8822C(x, v) \ + (BIT_CLEAR_DSS_3_DATA_IN_8822C(x) | BIT_DSS_3_DATA_IN_8822C(v)) + +/* 2 REG_SPEED_SENSOR5_8822C */ +#define BIT_DSS_3_READY_8822C BIT(31) +#define BIT_DSS_3_WSORT_GO_8822C BIT(30) + +#define BIT_SHIFT_DSS_3_COUNT_OUT_8822C 0 +#define BIT_MASK_DSS_3_COUNT_OUT_8822C 0xfffff +#define BIT_DSS_3_COUNT_OUT_8822C(x) \ + (((x) & BIT_MASK_DSS_3_COUNT_OUT_8822C) \ + << BIT_SHIFT_DSS_3_COUNT_OUT_8822C) +#define BITS_DSS_3_COUNT_OUT_8822C \ + (BIT_MASK_DSS_3_COUNT_OUT_8822C << BIT_SHIFT_DSS_3_COUNT_OUT_8822C) +#define BIT_CLEAR_DSS_3_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8822C)) +#define BIT_GET_DSS_3_COUNT_OUT_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8822C) & \ + BIT_MASK_DSS_3_COUNT_OUT_8822C) +#define BIT_SET_DSS_3_COUNT_OUT_8822C(x, v) \ + (BIT_CLEAR_DSS_3_COUNT_OUT_8822C(x) | BIT_DSS_3_COUNT_OUT_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_COUNTER_CTRL_8822C */ + +#define BIT_SHIFT_COUNTER_BASE_8822C 16 +#define BIT_MASK_COUNTER_BASE_8822C 0x1fff +#define BIT_COUNTER_BASE_8822C(x) \ + (((x) & BIT_MASK_COUNTER_BASE_8822C) << BIT_SHIFT_COUNTER_BASE_8822C) +#define BITS_COUNTER_BASE_8822C \ + (BIT_MASK_COUNTER_BASE_8822C << BIT_SHIFT_COUNTER_BASE_8822C) +#define BIT_CLEAR_COUNTER_BASE_8822C(x) ((x) & (~BITS_COUNTER_BASE_8822C)) +#define BIT_GET_COUNTER_BASE_8822C(x) \ + (((x) >> BIT_SHIFT_COUNTER_BASE_8822C) & BIT_MASK_COUNTER_BASE_8822C) +#define BIT_SET_COUNTER_BASE_8822C(x, v) \ + (BIT_CLEAR_COUNTER_BASE_8822C(x) | BIT_COUNTER_BASE_8822C(v)) + +#define BIT_EN_RTS_REQ_8822C BIT(9) +#define BIT_EN_EDCA_REQ_8822C BIT(8) +#define BIT_EN_PTCL_REQ_8822C BIT(7) +#define BIT_EN_SCH_REQ_8822C BIT(6) +#define BIT_USB_COUNT_EN_8822C BIT(5) +#define BIT_PCIE_COUNT_EN_8822C BIT(4) +#define BIT_RQPN_COUNT_EN_8822C BIT(3) +#define BIT_RDE_COUNT_EN_8822C BIT(2) +#define BIT_TDE_COUNT_EN_8822C BIT(1) +#define BIT_DISABLE_COUNTER_8822C BIT(0) + +/* 2 REG_COUNTER_THRESHOLD_8822C */ +#define BIT_SEL_ALL_MACID_8822C BIT(31) + +#define BIT_SHIFT_COUNTER_MACID_8822C 24 +#define BIT_MASK_COUNTER_MACID_8822C 0x7f +#define BIT_COUNTER_MACID_8822C(x) \ + (((x) & BIT_MASK_COUNTER_MACID_8822C) << BIT_SHIFT_COUNTER_MACID_8822C) +#define BITS_COUNTER_MACID_8822C \ + (BIT_MASK_COUNTER_MACID_8822C << BIT_SHIFT_COUNTER_MACID_8822C) +#define BIT_CLEAR_COUNTER_MACID_8822C(x) ((x) & (~BITS_COUNTER_MACID_8822C)) +#define BIT_GET_COUNTER_MACID_8822C(x) \ + (((x) >> BIT_SHIFT_COUNTER_MACID_8822C) & BIT_MASK_COUNTER_MACID_8822C) +#define BIT_SET_COUNTER_MACID_8822C(x, v) \ + (BIT_CLEAR_COUNTER_MACID_8822C(x) | BIT_COUNTER_MACID_8822C(v)) + +#define BIT_SHIFT_AGG_VALUE2_8822C 16 +#define BIT_MASK_AGG_VALUE2_8822C 0x7f +#define BIT_AGG_VALUE2_8822C(x) \ + (((x) & BIT_MASK_AGG_VALUE2_8822C) << BIT_SHIFT_AGG_VALUE2_8822C) +#define BITS_AGG_VALUE2_8822C \ + (BIT_MASK_AGG_VALUE2_8822C << BIT_SHIFT_AGG_VALUE2_8822C) +#define BIT_CLEAR_AGG_VALUE2_8822C(x) ((x) & (~BITS_AGG_VALUE2_8822C)) +#define BIT_GET_AGG_VALUE2_8822C(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE2_8822C) & BIT_MASK_AGG_VALUE2_8822C) +#define BIT_SET_AGG_VALUE2_8822C(x, v) \ + (BIT_CLEAR_AGG_VALUE2_8822C(x) | BIT_AGG_VALUE2_8822C(v)) + +#define BIT_SHIFT_AGG_VALUE1_8822C 8 +#define BIT_MASK_AGG_VALUE1_8822C 0x7f +#define BIT_AGG_VALUE1_8822C(x) \ + (((x) & BIT_MASK_AGG_VALUE1_8822C) << BIT_SHIFT_AGG_VALUE1_8822C) +#define BITS_AGG_VALUE1_8822C \ + (BIT_MASK_AGG_VALUE1_8822C << BIT_SHIFT_AGG_VALUE1_8822C) +#define BIT_CLEAR_AGG_VALUE1_8822C(x) ((x) & (~BITS_AGG_VALUE1_8822C)) +#define BIT_GET_AGG_VALUE1_8822C(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE1_8822C) & BIT_MASK_AGG_VALUE1_8822C) +#define BIT_SET_AGG_VALUE1_8822C(x, v) \ + (BIT_CLEAR_AGG_VALUE1_8822C(x) | BIT_AGG_VALUE1_8822C(v)) + +#define BIT_SHIFT_AGG_VALUE0_8822C 0 +#define BIT_MASK_AGG_VALUE0_8822C 0x7f +#define BIT_AGG_VALUE0_8822C(x) \ + (((x) & BIT_MASK_AGG_VALUE0_8822C) << BIT_SHIFT_AGG_VALUE0_8822C) +#define BITS_AGG_VALUE0_8822C \ + (BIT_MASK_AGG_VALUE0_8822C << BIT_SHIFT_AGG_VALUE0_8822C) +#define BIT_CLEAR_AGG_VALUE0_8822C(x) ((x) & (~BITS_AGG_VALUE0_8822C)) +#define BIT_GET_AGG_VALUE0_8822C(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE0_8822C) & BIT_MASK_AGG_VALUE0_8822C) +#define BIT_SET_AGG_VALUE0_8822C(x, v) \ + (BIT_CLEAR_AGG_VALUE0_8822C(x) | BIT_AGG_VALUE0_8822C(v)) + +/* 2 REG_COUNTER_SET_8822C */ + +#define BIT_SHIFT_REQUEST_RESET_8822C 16 +#define BIT_MASK_REQUEST_RESET_8822C 0xffff +#define BIT_REQUEST_RESET_8822C(x) \ + (((x) & BIT_MASK_REQUEST_RESET_8822C) << BIT_SHIFT_REQUEST_RESET_8822C) +#define BITS_REQUEST_RESET_8822C \ + (BIT_MASK_REQUEST_RESET_8822C << BIT_SHIFT_REQUEST_RESET_8822C) +#define BIT_CLEAR_REQUEST_RESET_8822C(x) ((x) & (~BITS_REQUEST_RESET_8822C)) +#define BIT_GET_REQUEST_RESET_8822C(x) \ + (((x) >> BIT_SHIFT_REQUEST_RESET_8822C) & BIT_MASK_REQUEST_RESET_8822C) +#define BIT_SET_REQUEST_RESET_8822C(x, v) \ + (BIT_CLEAR_REQUEST_RESET_8822C(x) | BIT_REQUEST_RESET_8822C(v)) + +#define BIT_SHIFT_REQUEST_START_8822C 0 +#define BIT_MASK_REQUEST_START_8822C 0xffff +#define BIT_REQUEST_START_8822C(x) \ + (((x) & BIT_MASK_REQUEST_START_8822C) << BIT_SHIFT_REQUEST_START_8822C) +#define BITS_REQUEST_START_8822C \ + (BIT_MASK_REQUEST_START_8822C << BIT_SHIFT_REQUEST_START_8822C) +#define BIT_CLEAR_REQUEST_START_8822C(x) ((x) & (~BITS_REQUEST_START_8822C)) +#define BIT_GET_REQUEST_START_8822C(x) \ + (((x) >> BIT_SHIFT_REQUEST_START_8822C) & BIT_MASK_REQUEST_START_8822C) +#define BIT_SET_REQUEST_START_8822C(x, v) \ + (BIT_CLEAR_REQUEST_START_8822C(x) | BIT_REQUEST_START_8822C(v)) + +/* 2 REG_COUNTER_OVERFLOW_8822C */ + +#define BIT_SHIFT_CNT_OVF_REG_8822C 0 +#define BIT_MASK_CNT_OVF_REG_8822C 0xffff +#define BIT_CNT_OVF_REG_8822C(x) \ + (((x) & BIT_MASK_CNT_OVF_REG_8822C) << BIT_SHIFT_CNT_OVF_REG_8822C) +#define BITS_CNT_OVF_REG_8822C \ + (BIT_MASK_CNT_OVF_REG_8822C << BIT_SHIFT_CNT_OVF_REG_8822C) +#define BIT_CLEAR_CNT_OVF_REG_8822C(x) ((x) & (~BITS_CNT_OVF_REG_8822C)) +#define BIT_GET_CNT_OVF_REG_8822C(x) \ + (((x) >> BIT_SHIFT_CNT_OVF_REG_8822C) & BIT_MASK_CNT_OVF_REG_8822C) +#define BIT_SET_CNT_OVF_REG_8822C(x, v) \ + (BIT_CLEAR_CNT_OVF_REG_8822C(x) | BIT_CNT_OVF_REG_8822C(v)) + +/* 2 REG_TXDMA_LEN_THRESHOLD_8822C */ + +#define BIT_SHIFT_TDE_LEN_TH1_8822C 16 +#define BIT_MASK_TDE_LEN_TH1_8822C 0xffff +#define BIT_TDE_LEN_TH1_8822C(x) \ + (((x) & BIT_MASK_TDE_LEN_TH1_8822C) << BIT_SHIFT_TDE_LEN_TH1_8822C) +#define BITS_TDE_LEN_TH1_8822C \ + (BIT_MASK_TDE_LEN_TH1_8822C << BIT_SHIFT_TDE_LEN_TH1_8822C) +#define BIT_CLEAR_TDE_LEN_TH1_8822C(x) ((x) & (~BITS_TDE_LEN_TH1_8822C)) +#define BIT_GET_TDE_LEN_TH1_8822C(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH1_8822C) & BIT_MASK_TDE_LEN_TH1_8822C) +#define BIT_SET_TDE_LEN_TH1_8822C(x, v) \ + (BIT_CLEAR_TDE_LEN_TH1_8822C(x) | BIT_TDE_LEN_TH1_8822C(v)) + +#define BIT_SHIFT_TDE_LEN_TH0_8822C 0 +#define BIT_MASK_TDE_LEN_TH0_8822C 0xffff +#define BIT_TDE_LEN_TH0_8822C(x) \ + (((x) & BIT_MASK_TDE_LEN_TH0_8822C) << BIT_SHIFT_TDE_LEN_TH0_8822C) +#define BITS_TDE_LEN_TH0_8822C \ + (BIT_MASK_TDE_LEN_TH0_8822C << BIT_SHIFT_TDE_LEN_TH0_8822C) +#define BIT_CLEAR_TDE_LEN_TH0_8822C(x) ((x) & (~BITS_TDE_LEN_TH0_8822C)) +#define BIT_GET_TDE_LEN_TH0_8822C(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH0_8822C) & BIT_MASK_TDE_LEN_TH0_8822C) +#define BIT_SET_TDE_LEN_TH0_8822C(x, v) \ + (BIT_CLEAR_TDE_LEN_TH0_8822C(x) | BIT_TDE_LEN_TH0_8822C(v)) + +/* 2 REG_RXDMA_LEN_THRESHOLD_8822C */ + +#define BIT_SHIFT_RDE_LEN_TH1_8822C 16 +#define BIT_MASK_RDE_LEN_TH1_8822C 0xffff +#define BIT_RDE_LEN_TH1_8822C(x) \ + (((x) & BIT_MASK_RDE_LEN_TH1_8822C) << BIT_SHIFT_RDE_LEN_TH1_8822C) +#define BITS_RDE_LEN_TH1_8822C \ + (BIT_MASK_RDE_LEN_TH1_8822C << BIT_SHIFT_RDE_LEN_TH1_8822C) +#define BIT_CLEAR_RDE_LEN_TH1_8822C(x) ((x) & (~BITS_RDE_LEN_TH1_8822C)) +#define BIT_GET_RDE_LEN_TH1_8822C(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH1_8822C) & BIT_MASK_RDE_LEN_TH1_8822C) +#define BIT_SET_RDE_LEN_TH1_8822C(x, v) \ + (BIT_CLEAR_RDE_LEN_TH1_8822C(x) | BIT_RDE_LEN_TH1_8822C(v)) + +#define BIT_SHIFT_RDE_LEN_TH0_8822C 0 +#define BIT_MASK_RDE_LEN_TH0_8822C 0xffff +#define BIT_RDE_LEN_TH0_8822C(x) \ + (((x) & BIT_MASK_RDE_LEN_TH0_8822C) << BIT_SHIFT_RDE_LEN_TH0_8822C) +#define BITS_RDE_LEN_TH0_8822C \ + (BIT_MASK_RDE_LEN_TH0_8822C << BIT_SHIFT_RDE_LEN_TH0_8822C) +#define BIT_CLEAR_RDE_LEN_TH0_8822C(x) ((x) & (~BITS_RDE_LEN_TH0_8822C)) +#define BIT_GET_RDE_LEN_TH0_8822C(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH0_8822C) & BIT_MASK_RDE_LEN_TH0_8822C) +#define BIT_SET_RDE_LEN_TH0_8822C(x, v) \ + (BIT_CLEAR_RDE_LEN_TH0_8822C(x) | BIT_RDE_LEN_TH0_8822C(v)) + +/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8822C */ + +#define BIT_SHIFT_COUNT_INT_SEL_8822C 16 +#define BIT_MASK_COUNT_INT_SEL_8822C 0x3 +#define BIT_COUNT_INT_SEL_8822C(x) \ + (((x) & BIT_MASK_COUNT_INT_SEL_8822C) << BIT_SHIFT_COUNT_INT_SEL_8822C) +#define BITS_COUNT_INT_SEL_8822C \ + (BIT_MASK_COUNT_INT_SEL_8822C << BIT_SHIFT_COUNT_INT_SEL_8822C) +#define BIT_CLEAR_COUNT_INT_SEL_8822C(x) ((x) & (~BITS_COUNT_INT_SEL_8822C)) +#define BIT_GET_COUNT_INT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_COUNT_INT_SEL_8822C) & BIT_MASK_COUNT_INT_SEL_8822C) +#define BIT_SET_COUNT_INT_SEL_8822C(x, v) \ + (BIT_CLEAR_COUNT_INT_SEL_8822C(x) | BIT_COUNT_INT_SEL_8822C(v)) + +#define BIT_SHIFT_EXEC_TIME_TH_8822C 0 +#define BIT_MASK_EXEC_TIME_TH_8822C 0xffff +#define BIT_EXEC_TIME_TH_8822C(x) \ + (((x) & BIT_MASK_EXEC_TIME_TH_8822C) << BIT_SHIFT_EXEC_TIME_TH_8822C) +#define BITS_EXEC_TIME_TH_8822C \ + (BIT_MASK_EXEC_TIME_TH_8822C << BIT_SHIFT_EXEC_TIME_TH_8822C) +#define BIT_CLEAR_EXEC_TIME_TH_8822C(x) ((x) & (~BITS_EXEC_TIME_TH_8822C)) +#define BIT_GET_EXEC_TIME_TH_8822C(x) \ + (((x) >> BIT_SHIFT_EXEC_TIME_TH_8822C) & BIT_MASK_EXEC_TIME_TH_8822C) +#define BIT_SET_EXEC_TIME_TH_8822C(x, v) \ + (BIT_CLEAR_EXEC_TIME_TH_8822C(x) | BIT_EXEC_TIME_TH_8822C(v)) + +/* 2 REG_FT2IMR_8822C */ +#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8822C BIT(31) +#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8822C BIT(30) +#define BIT_FS_CLI3_TRIGGER_PKT_EN_8822C BIT(29) +#define BIT_FS_CLI3_EOSP_INT_EN_8822C BIT(28) +#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8822C BIT(27) +#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8822C BIT(26) +#define BIT_FS_CLI2_TRIGGER_PKT_EN_8822C BIT(25) +#define BIT_FS_CLI2_EOSP_INT_EN_8822C BIT(24) +#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8822C BIT(23) +#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8822C BIT(22) +#define BIT_FS_CLI1_TRIGGER_PKT_EN_8822C BIT(21) +#define BIT_FS_CLI1_EOSP_INT_EN_8822C BIT(20) +#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8822C BIT(19) +#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8822C BIT(18) +#define BIT_FS_CLI0_TRIGGER_PKT_EN_8822C BIT(17) +#define BIT_FS_CLI0_EOSP_INT_EN_8822C BIT(16) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8822C BIT(9) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8822C BIT(8) +#define BIT_FS_CLI3_TX_NULL1_INT_EN_8822C BIT(7) +#define BIT_FS_CLI3_TX_NULL0_INT_EN_8822C BIT(6) +#define BIT_FS_CLI2_TX_NULL1_INT_EN_8822C BIT(5) +#define BIT_FS_CLI2_TX_NULL0_INT_EN_8822C BIT(4) +#define BIT_FS_CLI1_TX_NULL1_INT_EN_8822C BIT(3) +#define BIT_FS_CLI1_TX_NULL0_INT_EN_8822C BIT(2) +#define BIT_FS_CLI0_TX_NULL1_INT_EN_8822C BIT(1) +#define BIT_FS_CLI0_TX_NULL0_INT_EN_8822C BIT(0) + +/* 2 REG_FT2ISR_8822C */ +#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8822C BIT(31) +#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8822C BIT(30) +#define BIT_FS_CLI3_TRIGGER_PKT_INT_8822C BIT(29) +#define BIT_FS_CLI3_EOSP_INT_8822C BIT(28) +#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8822C BIT(27) +#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8822C BIT(26) +#define BIT_FS_CLI2_TRIGGER_PKT_INT_8822C BIT(25) +#define BIT_FS_CLI2_EOSP_INT_8822C BIT(24) +#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8822C BIT(23) +#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8822C BIT(22) +#define BIT_FS_CLI1_TRIGGER_PKT_INT_8822C BIT(21) +#define BIT_FS_CLI1_EOSP_INT_8822C BIT(20) +#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8822C BIT(19) +#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8822C BIT(18) +#define BIT_FS_CLI0_TRIGGER_PKT_INT_8822C BIT(17) +#define BIT_FS_CLI0_EOSP_INT_8822C BIT(16) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8822C BIT(9) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8822C BIT(8) +#define BIT_FS_CLI3_TX_NULL1_INT_8822C BIT(7) +#define BIT_FS_CLI3_TX_NULL0_INT_8822C BIT(6) +#define BIT_FS_CLI2_TX_NULL1_INT_8822C BIT(5) +#define BIT_FS_CLI2_TX_NULL0_INT_8822C BIT(4) +#define BIT_FS_CLI1_TX_NULL1_INT_8822C BIT(3) +#define BIT_FS_CLI1_TX_NULL0_INT_8822C BIT(2) +#define BIT_FS_CLI0_TX_NULL1_INT_8822C BIT(1) +#define BIT_FS_CLI0_TX_NULL0_INT_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_MSG2_8822C */ + +#define BIT_SHIFT_FW_MSG2_8822C 0 +#define BIT_MASK_FW_MSG2_8822C 0xffffffffL +#define BIT_FW_MSG2_8822C(x) \ + (((x) & BIT_MASK_FW_MSG2_8822C) << BIT_SHIFT_FW_MSG2_8822C) +#define BITS_FW_MSG2_8822C (BIT_MASK_FW_MSG2_8822C << BIT_SHIFT_FW_MSG2_8822C) +#define BIT_CLEAR_FW_MSG2_8822C(x) ((x) & (~BITS_FW_MSG2_8822C)) +#define BIT_GET_FW_MSG2_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG2_8822C) & BIT_MASK_FW_MSG2_8822C) +#define BIT_SET_FW_MSG2_8822C(x, v) \ + (BIT_CLEAR_FW_MSG2_8822C(x) | BIT_FW_MSG2_8822C(v)) + +/* 2 REG_MSG3_8822C */ + +#define BIT_SHIFT_FW_MSG3_8822C 0 +#define BIT_MASK_FW_MSG3_8822C 0xffffffffL +#define BIT_FW_MSG3_8822C(x) \ + (((x) & BIT_MASK_FW_MSG3_8822C) << BIT_SHIFT_FW_MSG3_8822C) +#define BITS_FW_MSG3_8822C (BIT_MASK_FW_MSG3_8822C << BIT_SHIFT_FW_MSG3_8822C) +#define BIT_CLEAR_FW_MSG3_8822C(x) ((x) & (~BITS_FW_MSG3_8822C)) +#define BIT_GET_FW_MSG3_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG3_8822C) & BIT_MASK_FW_MSG3_8822C) +#define BIT_SET_FW_MSG3_8822C(x, v) \ + (BIT_CLEAR_FW_MSG3_8822C(x) | BIT_FW_MSG3_8822C(v)) + +/* 2 REG_MSG4_8822C */ + +#define BIT_SHIFT_FW_MSG4_8822C 0 +#define BIT_MASK_FW_MSG4_8822C 0xffffffffL +#define BIT_FW_MSG4_8822C(x) \ + (((x) & BIT_MASK_FW_MSG4_8822C) << BIT_SHIFT_FW_MSG4_8822C) +#define BITS_FW_MSG4_8822C (BIT_MASK_FW_MSG4_8822C << BIT_SHIFT_FW_MSG4_8822C) +#define BIT_CLEAR_FW_MSG4_8822C(x) ((x) & (~BITS_FW_MSG4_8822C)) +#define BIT_GET_FW_MSG4_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG4_8822C) & BIT_MASK_FW_MSG4_8822C) +#define BIT_SET_FW_MSG4_8822C(x, v) \ + (BIT_CLEAR_FW_MSG4_8822C(x) | BIT_FW_MSG4_8822C(v)) + +/* 2 REG_MSG5_8822C */ + +#define BIT_SHIFT_FW_MSG5_8822C 0 +#define BIT_MASK_FW_MSG5_8822C 0xffffffffL +#define BIT_FW_MSG5_8822C(x) \ + (((x) & BIT_MASK_FW_MSG5_8822C) << BIT_SHIFT_FW_MSG5_8822C) +#define BITS_FW_MSG5_8822C (BIT_MASK_FW_MSG5_8822C << BIT_SHIFT_FW_MSG5_8822C) +#define BIT_CLEAR_FW_MSG5_8822C(x) ((x) & (~BITS_FW_MSG5_8822C)) +#define BIT_GET_FW_MSG5_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG5_8822C) & BIT_MASK_FW_MSG5_8822C) +#define BIT_SET_FW_MSG5_8822C(x, v) \ + (BIT_CLEAR_FW_MSG5_8822C(x) | BIT_FW_MSG5_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_FIFOPAGE_CTRL_1_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C 16 +#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C 0xff +#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822C(x) \ + (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C) \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C) +#define BITS_TX_OQT_HE_FREE_SPACE_V1_8822C \ + (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822C(x) \ + ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8822C)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C) & \ + BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C) +#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8822C(x, v) \ + (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822C(x) | \ + BIT_TX_OQT_HE_FREE_SPACE_V1_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C 0 +#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C 0xff +#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822C(x) \ + (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C) \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C) +#define BITS_TX_OQT_NL_FREE_SPACE_V1_8822C \ + (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822C(x) \ + ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8822C)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C) & \ + BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C) +#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8822C(x, v) \ + (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822C(x) | \ + BIT_TX_OQT_NL_FREE_SPACE_V1_8822C(v)) + +/* 2 REG_FIFOPAGE_CTRL_2_8822C */ +#define BIT_BCN_VALID_1_V1_8822C BIT(31) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_BCN_HEAD_1_V1_8822C 16 +#define BIT_MASK_BCN_HEAD_1_V1_8822C 0xfff +#define BIT_BCN_HEAD_1_V1_8822C(x) \ + (((x) & BIT_MASK_BCN_HEAD_1_V1_8822C) << BIT_SHIFT_BCN_HEAD_1_V1_8822C) +#define BITS_BCN_HEAD_1_V1_8822C \ + (BIT_MASK_BCN_HEAD_1_V1_8822C << BIT_SHIFT_BCN_HEAD_1_V1_8822C) +#define BIT_CLEAR_BCN_HEAD_1_V1_8822C(x) ((x) & (~BITS_BCN_HEAD_1_V1_8822C)) +#define BIT_GET_BCN_HEAD_1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822C) & BIT_MASK_BCN_HEAD_1_V1_8822C) +#define BIT_SET_BCN_HEAD_1_V1_8822C(x, v) \ + (BIT_CLEAR_BCN_HEAD_1_V1_8822C(x) | BIT_BCN_HEAD_1_V1_8822C(v)) + +#define BIT_BCN_VALID_V1_8822C BIT(15) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_BCN_HEAD_V1_8822C 0 +#define BIT_MASK_BCN_HEAD_V1_8822C 0xfff +#define BIT_BCN_HEAD_V1_8822C(x) \ + (((x) & BIT_MASK_BCN_HEAD_V1_8822C) << BIT_SHIFT_BCN_HEAD_V1_8822C) +#define BITS_BCN_HEAD_V1_8822C \ + (BIT_MASK_BCN_HEAD_V1_8822C << BIT_SHIFT_BCN_HEAD_V1_8822C) +#define BIT_CLEAR_BCN_HEAD_V1_8822C(x) ((x) & (~BITS_BCN_HEAD_V1_8822C)) +#define BIT_GET_BCN_HEAD_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_V1_8822C) & BIT_MASK_BCN_HEAD_V1_8822C) +#define BIT_SET_BCN_HEAD_V1_8822C(x, v) \ + (BIT_CLEAR_BCN_HEAD_V1_8822C(x) | BIT_BCN_HEAD_V1_8822C(v)) + +/* 2 REG_AUTO_LLT_V1_8822C */ + +#define BIT_SHIFT_MAX_TX_PKT_V1_8822C 24 +#define BIT_MASK_MAX_TX_PKT_V1_8822C 0xff +#define BIT_MAX_TX_PKT_V1_8822C(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_V1_8822C) << BIT_SHIFT_MAX_TX_PKT_V1_8822C) +#define BITS_MAX_TX_PKT_V1_8822C \ + (BIT_MASK_MAX_TX_PKT_V1_8822C << BIT_SHIFT_MAX_TX_PKT_V1_8822C) +#define BIT_CLEAR_MAX_TX_PKT_V1_8822C(x) ((x) & (~BITS_MAX_TX_PKT_V1_8822C)) +#define BIT_GET_MAX_TX_PKT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_V1_8822C) & BIT_MASK_MAX_TX_PKT_V1_8822C) +#define BIT_SET_MAX_TX_PKT_V1_8822C(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_V1_8822C(x) | BIT_MAX_TX_PKT_V1_8822C(v)) + +#define BIT_TDE_ERROR_STOP_V1_8822C BIT(23) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_LLT_FREE_PAGE_V2_8822C 8 +#define BIT_MASK_LLT_FREE_PAGE_V2_8822C 0xfff +#define BIT_LLT_FREE_PAGE_V2_8822C(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V2_8822C) \ + << BIT_SHIFT_LLT_FREE_PAGE_V2_8822C) +#define BITS_LLT_FREE_PAGE_V2_8822C \ + (BIT_MASK_LLT_FREE_PAGE_V2_8822C << BIT_SHIFT_LLT_FREE_PAGE_V2_8822C) +#define BIT_CLEAR_LLT_FREE_PAGE_V2_8822C(x) \ + ((x) & (~BITS_LLT_FREE_PAGE_V2_8822C)) +#define BIT_GET_LLT_FREE_PAGE_V2_8822C(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2_8822C) & \ + BIT_MASK_LLT_FREE_PAGE_V2_8822C) +#define BIT_SET_LLT_FREE_PAGE_V2_8822C(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V2_8822C(x) | BIT_LLT_FREE_PAGE_V2_8822C(v)) + +#define BIT_SHIFT_BLK_DESC_NUM_8822C 4 +#define BIT_MASK_BLK_DESC_NUM_8822C 0xf +#define BIT_BLK_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_BLK_DESC_NUM_8822C) << BIT_SHIFT_BLK_DESC_NUM_8822C) +#define BITS_BLK_DESC_NUM_8822C \ + (BIT_MASK_BLK_DESC_NUM_8822C << BIT_SHIFT_BLK_DESC_NUM_8822C) +#define BIT_CLEAR_BLK_DESC_NUM_8822C(x) ((x) & (~BITS_BLK_DESC_NUM_8822C)) +#define BIT_GET_BLK_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_BLK_DESC_NUM_8822C) & BIT_MASK_BLK_DESC_NUM_8822C) +#define BIT_SET_BLK_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_BLK_DESC_NUM_8822C(x) | BIT_BLK_DESC_NUM_8822C(v)) + +#define BIT_R_BCN_HEAD_SEL_8822C BIT(3) +#define BIT_R_EN_BCN_SW_HEAD_SEL_8822C BIT(2) +#define BIT_LLT_DBG_SEL_8822C BIT(1) +#define BIT_AUTO_INIT_LLT_V1_8822C BIT(0) + +/* 2 REG_TXDMA_OFFSET_CHK_8822C */ +#define BIT_EM_CHKSUM_FIN_8822C BIT(31) +#define BIT_EMN_PCIE_DMA_MOD_8822C BIT(30) +#define BIT_EN_TXQUE_CLR_8822C BIT(29) +#define BIT_EN_PCIE_FIFO_MODE_8822C BIT(28) + +#define BIT_SHIFT_PG_UNDER_TH_V1_8822C 16 +#define BIT_MASK_PG_UNDER_TH_V1_8822C 0xfff +#define BIT_PG_UNDER_TH_V1_8822C(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V1_8822C) \ + << BIT_SHIFT_PG_UNDER_TH_V1_8822C) +#define BITS_PG_UNDER_TH_V1_8822C \ + (BIT_MASK_PG_UNDER_TH_V1_8822C << BIT_SHIFT_PG_UNDER_TH_V1_8822C) +#define BIT_CLEAR_PG_UNDER_TH_V1_8822C(x) ((x) & (~BITS_PG_UNDER_TH_V1_8822C)) +#define BIT_GET_PG_UNDER_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822C) & \ + BIT_MASK_PG_UNDER_TH_V1_8822C) +#define BIT_SET_PG_UNDER_TH_V1_8822C(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V1_8822C(x) | BIT_PG_UNDER_TH_V1_8822C(v)) + +#define BIT_R_EN_RESET_RESTORE_H2C_8822C BIT(15) +#define BIT_SDIO_TDE_FINISH_8822C BIT(14) +#define BIT_SDIO_TXDESC_CHKSUM_EN_8822C BIT(13) +#define BIT_RST_RDPTR_8822C BIT(12) +#define BIT_RST_WRPTR_8822C BIT(11) +#define BIT_CHK_PG_TH_EN_8822C BIT(10) +#define BIT_DROP_DATA_EN_8822C BIT(9) +#define BIT_CHECK_OFFSET_EN_8822C BIT(8) + +#define BIT_SHIFT_CHECK_OFFSET_8822C 0 +#define BIT_MASK_CHECK_OFFSET_8822C 0xff +#define BIT_CHECK_OFFSET_8822C(x) \ + (((x) & BIT_MASK_CHECK_OFFSET_8822C) << BIT_SHIFT_CHECK_OFFSET_8822C) +#define BITS_CHECK_OFFSET_8822C \ + (BIT_MASK_CHECK_OFFSET_8822C << BIT_SHIFT_CHECK_OFFSET_8822C) +#define BIT_CLEAR_CHECK_OFFSET_8822C(x) ((x) & (~BITS_CHECK_OFFSET_8822C)) +#define BIT_GET_CHECK_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_CHECK_OFFSET_8822C) & BIT_MASK_CHECK_OFFSET_8822C) +#define BIT_SET_CHECK_OFFSET_8822C(x, v) \ + (BIT_CLEAR_CHECK_OFFSET_8822C(x) | BIT_CHECK_OFFSET_8822C(v)) + +/* 2 REG_TXDMA_STATUS_8822C */ +#define BIT_TXPKTBUF_REQ_ERR_8822C BIT(18) +#define BIT_HI_OQT_UDN_8822C BIT(17) +#define BIT_HI_OQT_OVF_8822C BIT(16) +#define BIT_PAYLOAD_CHKSUM_ERR_8822C BIT(15) +#define BIT_PAYLOAD_UDN_8822C BIT(14) +#define BIT_PAYLOAD_OVF_8822C BIT(13) +#define BIT_DSC_CHKSUM_FAIL_8822C BIT(12) +#define BIT_UNKNOWN_QSEL_8822C BIT(11) +#define BIT_EP_QSEL_DIFF_8822C BIT(10) +#define BIT_TX_OFFS_UNMATCH_8822C BIT(9) +#define BIT_TXOQT_UDN_8822C BIT(8) +#define BIT_TXOQT_OVF_8822C BIT(7) +#define BIT_TXDMA_SFF_UDN_8822C BIT(6) +#define BIT_TXDMA_SFF_OVF_8822C BIT(5) +#define BIT_LLT_NULL_PG_8822C BIT(4) +#define BIT_PAGE_UDN_8822C BIT(3) +#define BIT_PAGE_OVF_8822C BIT(2) +#define BIT_TXFF_PG_UDN_8822C BIT(1) +#define BIT_TXFF_PG_OVF_8822C BIT(0) + +/* 2 REG_TX_DMA_DBG_8822C */ + +/* 2 REG_TQPNT1_8822C */ +#define BIT_HPQ_INT_EN_8822C BIT(31) + +#define BIT_SHIFT_HPQ_HIGH_TH_V1_8822C 16 +#define BIT_MASK_HPQ_HIGH_TH_V1_8822C 0xfff +#define BIT_HPQ_HIGH_TH_V1_8822C(x) \ + (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822C) \ + << BIT_SHIFT_HPQ_HIGH_TH_V1_8822C) +#define BITS_HPQ_HIGH_TH_V1_8822C \ + (BIT_MASK_HPQ_HIGH_TH_V1_8822C << BIT_SHIFT_HPQ_HIGH_TH_V1_8822C) +#define BIT_CLEAR_HPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8822C)) +#define BIT_GET_HPQ_HIGH_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822C) & \ + BIT_MASK_HPQ_HIGH_TH_V1_8822C) +#define BIT_SET_HPQ_HIGH_TH_V1_8822C(x, v) \ + (BIT_CLEAR_HPQ_HIGH_TH_V1_8822C(x) | BIT_HPQ_HIGH_TH_V1_8822C(v)) + +#define BIT_SHIFT_HPQ_LOW_TH_V1_8822C 0 +#define BIT_MASK_HPQ_LOW_TH_V1_8822C 0xfff +#define BIT_HPQ_LOW_TH_V1_8822C(x) \ + (((x) & BIT_MASK_HPQ_LOW_TH_V1_8822C) << BIT_SHIFT_HPQ_LOW_TH_V1_8822C) +#define BITS_HPQ_LOW_TH_V1_8822C \ + (BIT_MASK_HPQ_LOW_TH_V1_8822C << BIT_SHIFT_HPQ_LOW_TH_V1_8822C) +#define BIT_CLEAR_HPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8822C)) +#define BIT_GET_HPQ_LOW_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822C) & BIT_MASK_HPQ_LOW_TH_V1_8822C) +#define BIT_SET_HPQ_LOW_TH_V1_8822C(x, v) \ + (BIT_CLEAR_HPQ_LOW_TH_V1_8822C(x) | BIT_HPQ_LOW_TH_V1_8822C(v)) + +/* 2 REG_TQPNT2_8822C */ +#define BIT_NPQ_INT_EN_8822C BIT(31) + +#define BIT_SHIFT_NPQ_HIGH_TH_V1_8822C 16 +#define BIT_MASK_NPQ_HIGH_TH_V1_8822C 0xfff +#define BIT_NPQ_HIGH_TH_V1_8822C(x) \ + (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822C) \ + << BIT_SHIFT_NPQ_HIGH_TH_V1_8822C) +#define BITS_NPQ_HIGH_TH_V1_8822C \ + (BIT_MASK_NPQ_HIGH_TH_V1_8822C << BIT_SHIFT_NPQ_HIGH_TH_V1_8822C) +#define BIT_CLEAR_NPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8822C)) +#define BIT_GET_NPQ_HIGH_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822C) & \ + BIT_MASK_NPQ_HIGH_TH_V1_8822C) +#define BIT_SET_NPQ_HIGH_TH_V1_8822C(x, v) \ + (BIT_CLEAR_NPQ_HIGH_TH_V1_8822C(x) | BIT_NPQ_HIGH_TH_V1_8822C(v)) + +#define BIT_SHIFT_NPQ_LOW_TH_V1_8822C 0 +#define BIT_MASK_NPQ_LOW_TH_V1_8822C 0xfff +#define BIT_NPQ_LOW_TH_V1_8822C(x) \ + (((x) & BIT_MASK_NPQ_LOW_TH_V1_8822C) << BIT_SHIFT_NPQ_LOW_TH_V1_8822C) +#define BITS_NPQ_LOW_TH_V1_8822C \ + (BIT_MASK_NPQ_LOW_TH_V1_8822C << BIT_SHIFT_NPQ_LOW_TH_V1_8822C) +#define BIT_CLEAR_NPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8822C)) +#define BIT_GET_NPQ_LOW_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822C) & BIT_MASK_NPQ_LOW_TH_V1_8822C) +#define BIT_SET_NPQ_LOW_TH_V1_8822C(x, v) \ + (BIT_CLEAR_NPQ_LOW_TH_V1_8822C(x) | BIT_NPQ_LOW_TH_V1_8822C(v)) + +/* 2 REG_TQPNT3_8822C */ +#define BIT_LPQ_INT_EN_8822C BIT(31) + +#define BIT_SHIFT_LPQ_HIGH_TH_V1_8822C 16 +#define BIT_MASK_LPQ_HIGH_TH_V1_8822C 0xfff +#define BIT_LPQ_HIGH_TH_V1_8822C(x) \ + (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822C) \ + << BIT_SHIFT_LPQ_HIGH_TH_V1_8822C) +#define BITS_LPQ_HIGH_TH_V1_8822C \ + (BIT_MASK_LPQ_HIGH_TH_V1_8822C << BIT_SHIFT_LPQ_HIGH_TH_V1_8822C) +#define BIT_CLEAR_LPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8822C)) +#define BIT_GET_LPQ_HIGH_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822C) & \ + BIT_MASK_LPQ_HIGH_TH_V1_8822C) +#define BIT_SET_LPQ_HIGH_TH_V1_8822C(x, v) \ + (BIT_CLEAR_LPQ_HIGH_TH_V1_8822C(x) | BIT_LPQ_HIGH_TH_V1_8822C(v)) + +#define BIT_SHIFT_LPQ_LOW_TH_V1_8822C 0 +#define BIT_MASK_LPQ_LOW_TH_V1_8822C 0xfff +#define BIT_LPQ_LOW_TH_V1_8822C(x) \ + (((x) & BIT_MASK_LPQ_LOW_TH_V1_8822C) << BIT_SHIFT_LPQ_LOW_TH_V1_8822C) +#define BITS_LPQ_LOW_TH_V1_8822C \ + (BIT_MASK_LPQ_LOW_TH_V1_8822C << BIT_SHIFT_LPQ_LOW_TH_V1_8822C) +#define BIT_CLEAR_LPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8822C)) +#define BIT_GET_LPQ_LOW_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822C) & BIT_MASK_LPQ_LOW_TH_V1_8822C) +#define BIT_SET_LPQ_LOW_TH_V1_8822C(x, v) \ + (BIT_CLEAR_LPQ_LOW_TH_V1_8822C(x) | BIT_LPQ_LOW_TH_V1_8822C(v)) + +/* 2 REG_TQPNT4_8822C */ +#define BIT_EXQ_INT_EN_8822C BIT(31) + +#define BIT_SHIFT_EXQ_HIGH_TH_V1_8822C 16 +#define BIT_MASK_EXQ_HIGH_TH_V1_8822C 0xfff +#define BIT_EXQ_HIGH_TH_V1_8822C(x) \ + (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822C) \ + << BIT_SHIFT_EXQ_HIGH_TH_V1_8822C) +#define BITS_EXQ_HIGH_TH_V1_8822C \ + (BIT_MASK_EXQ_HIGH_TH_V1_8822C << BIT_SHIFT_EXQ_HIGH_TH_V1_8822C) +#define BIT_CLEAR_EXQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8822C)) +#define BIT_GET_EXQ_HIGH_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822C) & \ + BIT_MASK_EXQ_HIGH_TH_V1_8822C) +#define BIT_SET_EXQ_HIGH_TH_V1_8822C(x, v) \ + (BIT_CLEAR_EXQ_HIGH_TH_V1_8822C(x) | BIT_EXQ_HIGH_TH_V1_8822C(v)) + +#define BIT_SHIFT_EXQ_LOW_TH_V1_8822C 0 +#define BIT_MASK_EXQ_LOW_TH_V1_8822C 0xfff +#define BIT_EXQ_LOW_TH_V1_8822C(x) \ + (((x) & BIT_MASK_EXQ_LOW_TH_V1_8822C) << BIT_SHIFT_EXQ_LOW_TH_V1_8822C) +#define BITS_EXQ_LOW_TH_V1_8822C \ + (BIT_MASK_EXQ_LOW_TH_V1_8822C << BIT_SHIFT_EXQ_LOW_TH_V1_8822C) +#define BIT_CLEAR_EXQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8822C)) +#define BIT_GET_EXQ_LOW_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822C) & BIT_MASK_EXQ_LOW_TH_V1_8822C) +#define BIT_SET_EXQ_LOW_TH_V1_8822C(x, v) \ + (BIT_CLEAR_EXQ_LOW_TH_V1_8822C(x) | BIT_EXQ_LOW_TH_V1_8822C(v)) + +/* 2 REG_RQPN_CTRL_1_8822C */ + +#define BIT_SHIFT_TXPKTNUM_H_V2_8822C 16 +#define BIT_MASK_TXPKTNUM_H_V2_8822C 0xfff +#define BIT_TXPKTNUM_H_V2_8822C(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_V2_8822C) << BIT_SHIFT_TXPKTNUM_H_V2_8822C) +#define BITS_TXPKTNUM_H_V2_8822C \ + (BIT_MASK_TXPKTNUM_H_V2_8822C << BIT_SHIFT_TXPKTNUM_H_V2_8822C) +#define BIT_CLEAR_TXPKTNUM_H_V2_8822C(x) ((x) & (~BITS_TXPKTNUM_H_V2_8822C)) +#define BIT_GET_TXPKTNUM_H_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_V2_8822C) & BIT_MASK_TXPKTNUM_H_V2_8822C) +#define BIT_SET_TXPKTNUM_H_V2_8822C(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_V2_8822C(x) | BIT_TXPKTNUM_H_V2_8822C(v)) + +#define BIT_SHIFT_TXPKTNUM_V3_8822C 0 +#define BIT_MASK_TXPKTNUM_V3_8822C 0xfff +#define BIT_TXPKTNUM_V3_8822C(x) \ + (((x) & BIT_MASK_TXPKTNUM_V3_8822C) << BIT_SHIFT_TXPKTNUM_V3_8822C) +#define BITS_TXPKTNUM_V3_8822C \ + (BIT_MASK_TXPKTNUM_V3_8822C << BIT_SHIFT_TXPKTNUM_V3_8822C) +#define BIT_CLEAR_TXPKTNUM_V3_8822C(x) ((x) & (~BITS_TXPKTNUM_V3_8822C)) +#define BIT_GET_TXPKTNUM_V3_8822C(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_V3_8822C) & BIT_MASK_TXPKTNUM_V3_8822C) +#define BIT_SET_TXPKTNUM_V3_8822C(x, v) \ + (BIT_CLEAR_TXPKTNUM_V3_8822C(x) | BIT_TXPKTNUM_V3_8822C(v)) + +/* 2 REG_RQPN_CTRL_2_8822C */ +#define BIT_LD_RQPN_8822C BIT(31) +#define BIT_EXQ_PUBLIC_DIS_V1_8822C BIT(19) +#define BIT_NPQ_PUBLIC_DIS_V1_8822C BIT(18) +#define BIT_LPQ_PUBLIC_DIS_V1_8822C BIT(17) +#define BIT_HPQ_PUBLIC_DIS_V1_8822C BIT(16) +#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_8822C BIT(15) + +#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C 0 +#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C 0xfff +#define BIT_SDIO_TXAGG_ALIGN_SIZE_8822C(x) \ + (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C) \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C) +#define BITS_SDIO_TXAGG_ALIGN_SIZE_8822C \ + (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C) +#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8822C(x) \ + ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_8822C)) +#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C) & \ + BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C) +#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_8822C(x, v) \ + (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8822C(x) | \ + BIT_SDIO_TXAGG_ALIGN_SIZE_8822C(v)) + +/* 2 REG_FIFOPAGE_INFO_1_8822C */ + +#define BIT_SHIFT_HPQ_AVAL_PG_V1_8822C 16 +#define BIT_MASK_HPQ_AVAL_PG_V1_8822C 0xfff +#define BIT_HPQ_AVAL_PG_V1_8822C(x) \ + (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822C) \ + << BIT_SHIFT_HPQ_AVAL_PG_V1_8822C) +#define BITS_HPQ_AVAL_PG_V1_8822C \ + (BIT_MASK_HPQ_AVAL_PG_V1_8822C << BIT_SHIFT_HPQ_AVAL_PG_V1_8822C) +#define BIT_CLEAR_HPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8822C)) +#define BIT_GET_HPQ_AVAL_PG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822C) & \ + BIT_MASK_HPQ_AVAL_PG_V1_8822C) +#define BIT_SET_HPQ_AVAL_PG_V1_8822C(x, v) \ + (BIT_CLEAR_HPQ_AVAL_PG_V1_8822C(x) | BIT_HPQ_AVAL_PG_V1_8822C(v)) + +#define BIT_SHIFT_HPQ_V1_8822C 0 +#define BIT_MASK_HPQ_V1_8822C 0xfff +#define BIT_HPQ_V1_8822C(x) \ + (((x) & BIT_MASK_HPQ_V1_8822C) << BIT_SHIFT_HPQ_V1_8822C) +#define BITS_HPQ_V1_8822C (BIT_MASK_HPQ_V1_8822C << BIT_SHIFT_HPQ_V1_8822C) +#define BIT_CLEAR_HPQ_V1_8822C(x) ((x) & (~BITS_HPQ_V1_8822C)) +#define BIT_GET_HPQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HPQ_V1_8822C) & BIT_MASK_HPQ_V1_8822C) +#define BIT_SET_HPQ_V1_8822C(x, v) \ + (BIT_CLEAR_HPQ_V1_8822C(x) | BIT_HPQ_V1_8822C(v)) + +/* 2 REG_FIFOPAGE_INFO_2_8822C */ + +#define BIT_SHIFT_LPQ_AVAL_PG_V1_8822C 16 +#define BIT_MASK_LPQ_AVAL_PG_V1_8822C 0xfff +#define BIT_LPQ_AVAL_PG_V1_8822C(x) \ + (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822C) \ + << BIT_SHIFT_LPQ_AVAL_PG_V1_8822C) +#define BITS_LPQ_AVAL_PG_V1_8822C \ + (BIT_MASK_LPQ_AVAL_PG_V1_8822C << BIT_SHIFT_LPQ_AVAL_PG_V1_8822C) +#define BIT_CLEAR_LPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8822C)) +#define BIT_GET_LPQ_AVAL_PG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822C) & \ + BIT_MASK_LPQ_AVAL_PG_V1_8822C) +#define BIT_SET_LPQ_AVAL_PG_V1_8822C(x, v) \ + (BIT_CLEAR_LPQ_AVAL_PG_V1_8822C(x) | BIT_LPQ_AVAL_PG_V1_8822C(v)) + +#define BIT_SHIFT_LPQ_V1_8822C 0 +#define BIT_MASK_LPQ_V1_8822C 0xfff +#define BIT_LPQ_V1_8822C(x) \ + (((x) & BIT_MASK_LPQ_V1_8822C) << BIT_SHIFT_LPQ_V1_8822C) +#define BITS_LPQ_V1_8822C (BIT_MASK_LPQ_V1_8822C << BIT_SHIFT_LPQ_V1_8822C) +#define BIT_CLEAR_LPQ_V1_8822C(x) ((x) & (~BITS_LPQ_V1_8822C)) +#define BIT_GET_LPQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LPQ_V1_8822C) & BIT_MASK_LPQ_V1_8822C) +#define BIT_SET_LPQ_V1_8822C(x, v) \ + (BIT_CLEAR_LPQ_V1_8822C(x) | BIT_LPQ_V1_8822C(v)) + +/* 2 REG_FIFOPAGE_INFO_3_8822C */ + +#define BIT_SHIFT_NPQ_AVAL_PG_V1_8822C 16 +#define BIT_MASK_NPQ_AVAL_PG_V1_8822C 0xfff +#define BIT_NPQ_AVAL_PG_V1_8822C(x) \ + (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822C) \ + << BIT_SHIFT_NPQ_AVAL_PG_V1_8822C) +#define BITS_NPQ_AVAL_PG_V1_8822C \ + (BIT_MASK_NPQ_AVAL_PG_V1_8822C << BIT_SHIFT_NPQ_AVAL_PG_V1_8822C) +#define BIT_CLEAR_NPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8822C)) +#define BIT_GET_NPQ_AVAL_PG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822C) & \ + BIT_MASK_NPQ_AVAL_PG_V1_8822C) +#define BIT_SET_NPQ_AVAL_PG_V1_8822C(x, v) \ + (BIT_CLEAR_NPQ_AVAL_PG_V1_8822C(x) | BIT_NPQ_AVAL_PG_V1_8822C(v)) + +#define BIT_SHIFT_NPQ_V1_8822C 0 +#define BIT_MASK_NPQ_V1_8822C 0xfff +#define BIT_NPQ_V1_8822C(x) \ + (((x) & BIT_MASK_NPQ_V1_8822C) << BIT_SHIFT_NPQ_V1_8822C) +#define BITS_NPQ_V1_8822C (BIT_MASK_NPQ_V1_8822C << BIT_SHIFT_NPQ_V1_8822C) +#define BIT_CLEAR_NPQ_V1_8822C(x) ((x) & (~BITS_NPQ_V1_8822C)) +#define BIT_GET_NPQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NPQ_V1_8822C) & BIT_MASK_NPQ_V1_8822C) +#define BIT_SET_NPQ_V1_8822C(x, v) \ + (BIT_CLEAR_NPQ_V1_8822C(x) | BIT_NPQ_V1_8822C(v)) + +/* 2 REG_FIFOPAGE_INFO_4_8822C */ + +#define BIT_SHIFT_EXQ_AVAL_PG_V1_8822C 16 +#define BIT_MASK_EXQ_AVAL_PG_V1_8822C 0xfff +#define BIT_EXQ_AVAL_PG_V1_8822C(x) \ + (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822C) \ + << BIT_SHIFT_EXQ_AVAL_PG_V1_8822C) +#define BITS_EXQ_AVAL_PG_V1_8822C \ + (BIT_MASK_EXQ_AVAL_PG_V1_8822C << BIT_SHIFT_EXQ_AVAL_PG_V1_8822C) +#define BIT_CLEAR_EXQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8822C)) +#define BIT_GET_EXQ_AVAL_PG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822C) & \ + BIT_MASK_EXQ_AVAL_PG_V1_8822C) +#define BIT_SET_EXQ_AVAL_PG_V1_8822C(x, v) \ + (BIT_CLEAR_EXQ_AVAL_PG_V1_8822C(x) | BIT_EXQ_AVAL_PG_V1_8822C(v)) + +#define BIT_SHIFT_EXQ_V1_8822C 0 +#define BIT_MASK_EXQ_V1_8822C 0xfff +#define BIT_EXQ_V1_8822C(x) \ + (((x) & BIT_MASK_EXQ_V1_8822C) << BIT_SHIFT_EXQ_V1_8822C) +#define BITS_EXQ_V1_8822C (BIT_MASK_EXQ_V1_8822C << BIT_SHIFT_EXQ_V1_8822C) +#define BIT_CLEAR_EXQ_V1_8822C(x) ((x) & (~BITS_EXQ_V1_8822C)) +#define BIT_GET_EXQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EXQ_V1_8822C) & BIT_MASK_EXQ_V1_8822C) +#define BIT_SET_EXQ_V1_8822C(x, v) \ + (BIT_CLEAR_EXQ_V1_8822C(x) | BIT_EXQ_V1_8822C(v)) + +/* 2 REG_FIFOPAGE_INFO_5_8822C */ + +#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C 16 +#define BIT_MASK_PUBQ_AVAL_PG_V1_8822C 0xfff +#define BIT_PUBQ_AVAL_PG_V1_8822C(x) \ + (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822C) \ + << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C) +#define BITS_PUBQ_AVAL_PG_V1_8822C \ + (BIT_MASK_PUBQ_AVAL_PG_V1_8822C << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C) +#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8822C)) +#define BIT_GET_PUBQ_AVAL_PG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C) & \ + BIT_MASK_PUBQ_AVAL_PG_V1_8822C) +#define BIT_SET_PUBQ_AVAL_PG_V1_8822C(x, v) \ + (BIT_CLEAR_PUBQ_AVAL_PG_V1_8822C(x) | BIT_PUBQ_AVAL_PG_V1_8822C(v)) + +#define BIT_SHIFT_PUBQ_V1_8822C 0 +#define BIT_MASK_PUBQ_V1_8822C 0xfff +#define BIT_PUBQ_V1_8822C(x) \ + (((x) & BIT_MASK_PUBQ_V1_8822C) << BIT_SHIFT_PUBQ_V1_8822C) +#define BITS_PUBQ_V1_8822C (BIT_MASK_PUBQ_V1_8822C << BIT_SHIFT_PUBQ_V1_8822C) +#define BIT_CLEAR_PUBQ_V1_8822C(x) ((x) & (~BITS_PUBQ_V1_8822C)) +#define BIT_GET_PUBQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PUBQ_V1_8822C) & BIT_MASK_PUBQ_V1_8822C) +#define BIT_SET_PUBQ_V1_8822C(x, v) \ + (BIT_CLEAR_PUBQ_V1_8822C(x) | BIT_PUBQ_V1_8822C(v)) + +/* 2 REG_H2C_HEAD_8822C */ + +#define BIT_SHIFT_H2C_HEAD_8822C 0 +#define BIT_MASK_H2C_HEAD_8822C 0x3ffff +#define BIT_H2C_HEAD_8822C(x) \ + (((x) & BIT_MASK_H2C_HEAD_8822C) << BIT_SHIFT_H2C_HEAD_8822C) +#define BITS_H2C_HEAD_8822C \ + (BIT_MASK_H2C_HEAD_8822C << BIT_SHIFT_H2C_HEAD_8822C) +#define BIT_CLEAR_H2C_HEAD_8822C(x) ((x) & (~BITS_H2C_HEAD_8822C)) +#define BIT_GET_H2C_HEAD_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_8822C) & BIT_MASK_H2C_HEAD_8822C) +#define BIT_SET_H2C_HEAD_8822C(x, v) \ + (BIT_CLEAR_H2C_HEAD_8822C(x) | BIT_H2C_HEAD_8822C(v)) + +/* 2 REG_H2C_TAIL_8822C */ + +#define BIT_SHIFT_H2C_TAIL_8822C 0 +#define BIT_MASK_H2C_TAIL_8822C 0x3ffff +#define BIT_H2C_TAIL_8822C(x) \ + (((x) & BIT_MASK_H2C_TAIL_8822C) << BIT_SHIFT_H2C_TAIL_8822C) +#define BITS_H2C_TAIL_8822C \ + (BIT_MASK_H2C_TAIL_8822C << BIT_SHIFT_H2C_TAIL_8822C) +#define BIT_CLEAR_H2C_TAIL_8822C(x) ((x) & (~BITS_H2C_TAIL_8822C)) +#define BIT_GET_H2C_TAIL_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_8822C) & BIT_MASK_H2C_TAIL_8822C) +#define BIT_SET_H2C_TAIL_8822C(x, v) \ + (BIT_CLEAR_H2C_TAIL_8822C(x) | BIT_H2C_TAIL_8822C(v)) + +/* 2 REG_H2C_READ_ADDR_8822C */ + +#define BIT_SHIFT_H2C_READ_ADDR_8822C 0 +#define BIT_MASK_H2C_READ_ADDR_8822C 0x3ffff +#define BIT_H2C_READ_ADDR_8822C(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_8822C) << BIT_SHIFT_H2C_READ_ADDR_8822C) +#define BITS_H2C_READ_ADDR_8822C \ + (BIT_MASK_H2C_READ_ADDR_8822C << BIT_SHIFT_H2C_READ_ADDR_8822C) +#define BIT_CLEAR_H2C_READ_ADDR_8822C(x) ((x) & (~BITS_H2C_READ_ADDR_8822C)) +#define BIT_GET_H2C_READ_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_8822C) & BIT_MASK_H2C_READ_ADDR_8822C) +#define BIT_SET_H2C_READ_ADDR_8822C(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_8822C(x) | BIT_H2C_READ_ADDR_8822C(v)) + +/* 2 REG_H2C_WR_ADDR_8822C */ + +#define BIT_SHIFT_H2C_WR_ADDR_8822C 0 +#define BIT_MASK_H2C_WR_ADDR_8822C 0x3ffff +#define BIT_H2C_WR_ADDR_8822C(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_8822C) << BIT_SHIFT_H2C_WR_ADDR_8822C) +#define BITS_H2C_WR_ADDR_8822C \ + (BIT_MASK_H2C_WR_ADDR_8822C << BIT_SHIFT_H2C_WR_ADDR_8822C) +#define BIT_CLEAR_H2C_WR_ADDR_8822C(x) ((x) & (~BITS_H2C_WR_ADDR_8822C)) +#define BIT_GET_H2C_WR_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_8822C) & BIT_MASK_H2C_WR_ADDR_8822C) +#define BIT_SET_H2C_WR_ADDR_8822C(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_8822C(x) | BIT_H2C_WR_ADDR_8822C(v)) + +/* 2 REG_H2C_INFO_8822C */ +#define BIT_H2C_SPACE_VLD_8822C BIT(3) +#define BIT_H2C_WR_ADDR_RST_8822C BIT(2) + +#define BIT_SHIFT_H2C_LEN_SEL_8822C 0 +#define BIT_MASK_H2C_LEN_SEL_8822C 0x3 +#define BIT_H2C_LEN_SEL_8822C(x) \ + (((x) & BIT_MASK_H2C_LEN_SEL_8822C) << BIT_SHIFT_H2C_LEN_SEL_8822C) +#define BITS_H2C_LEN_SEL_8822C \ + (BIT_MASK_H2C_LEN_SEL_8822C << BIT_SHIFT_H2C_LEN_SEL_8822C) +#define BIT_CLEAR_H2C_LEN_SEL_8822C(x) ((x) & (~BITS_H2C_LEN_SEL_8822C)) +#define BIT_GET_H2C_LEN_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_LEN_SEL_8822C) & BIT_MASK_H2C_LEN_SEL_8822C) +#define BIT_SET_H2C_LEN_SEL_8822C(x, v) \ + (BIT_CLEAR_H2C_LEN_SEL_8822C(x) | BIT_H2C_LEN_SEL_8822C(v)) + +/* 2 REG_PGSUB_CNT_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_RST_PGSUB_CNT_8822C BIT(1) +#define BIT_PGSUB_CNT_EN_8822C BIT(0) + +/* 2 REG_PGSUB_H_8822C */ + +#define BIT_SHIFT_HPQ_PGSUB_CNT_8822C 0 +#define BIT_MASK_HPQ_PGSUB_CNT_8822C 0xffffffffL +#define BIT_HPQ_PGSUB_CNT_8822C(x) \ + (((x) & BIT_MASK_HPQ_PGSUB_CNT_8822C) << BIT_SHIFT_HPQ_PGSUB_CNT_8822C) +#define BITS_HPQ_PGSUB_CNT_8822C \ + (BIT_MASK_HPQ_PGSUB_CNT_8822C << BIT_SHIFT_HPQ_PGSUB_CNT_8822C) +#define BIT_CLEAR_HPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_HPQ_PGSUB_CNT_8822C)) +#define BIT_GET_HPQ_PGSUB_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_HPQ_PGSUB_CNT_8822C) & BIT_MASK_HPQ_PGSUB_CNT_8822C) +#define BIT_SET_HPQ_PGSUB_CNT_8822C(x, v) \ + (BIT_CLEAR_HPQ_PGSUB_CNT_8822C(x) | BIT_HPQ_PGSUB_CNT_8822C(v)) + +/* 2 REG_PGSUB_N_8822C */ + +#define BIT_SHIFT_NPQ_PGSUB_CNT_8822C 0 +#define BIT_MASK_NPQ_PGSUB_CNT_8822C 0xffffffffL +#define BIT_NPQ_PGSUB_CNT_8822C(x) \ + (((x) & BIT_MASK_NPQ_PGSUB_CNT_8822C) << BIT_SHIFT_NPQ_PGSUB_CNT_8822C) +#define BITS_NPQ_PGSUB_CNT_8822C \ + (BIT_MASK_NPQ_PGSUB_CNT_8822C << BIT_SHIFT_NPQ_PGSUB_CNT_8822C) +#define BIT_CLEAR_NPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_NPQ_PGSUB_CNT_8822C)) +#define BIT_GET_NPQ_PGSUB_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_NPQ_PGSUB_CNT_8822C) & BIT_MASK_NPQ_PGSUB_CNT_8822C) +#define BIT_SET_NPQ_PGSUB_CNT_8822C(x, v) \ + (BIT_CLEAR_NPQ_PGSUB_CNT_8822C(x) | BIT_NPQ_PGSUB_CNT_8822C(v)) + +/* 2 REG_PGSUB_L_8822C */ + +#define BIT_SHIFT_LPQ_PGSUB_CNT_8822C 0 +#define BIT_MASK_LPQ_PGSUB_CNT_8822C 0xffffffffL +#define BIT_LPQ_PGSUB_CNT_8822C(x) \ + (((x) & BIT_MASK_LPQ_PGSUB_CNT_8822C) << BIT_SHIFT_LPQ_PGSUB_CNT_8822C) +#define BITS_LPQ_PGSUB_CNT_8822C \ + (BIT_MASK_LPQ_PGSUB_CNT_8822C << BIT_SHIFT_LPQ_PGSUB_CNT_8822C) +#define BIT_CLEAR_LPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_LPQ_PGSUB_CNT_8822C)) +#define BIT_GET_LPQ_PGSUB_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_LPQ_PGSUB_CNT_8822C) & BIT_MASK_LPQ_PGSUB_CNT_8822C) +#define BIT_SET_LPQ_PGSUB_CNT_8822C(x, v) \ + (BIT_CLEAR_LPQ_PGSUB_CNT_8822C(x) | BIT_LPQ_PGSUB_CNT_8822C(v)) + +/* 2 REG_PGSUB_E_8822C */ + +#define BIT_SHIFT_EPQ_PGSUB_CNT_8822C 0 +#define BIT_MASK_EPQ_PGSUB_CNT_8822C 0xffffffffL +#define BIT_EPQ_PGSUB_CNT_8822C(x) \ + (((x) & BIT_MASK_EPQ_PGSUB_CNT_8822C) << BIT_SHIFT_EPQ_PGSUB_CNT_8822C) +#define BITS_EPQ_PGSUB_CNT_8822C \ + (BIT_MASK_EPQ_PGSUB_CNT_8822C << BIT_SHIFT_EPQ_PGSUB_CNT_8822C) +#define BIT_CLEAR_EPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_EPQ_PGSUB_CNT_8822C)) +#define BIT_GET_EPQ_PGSUB_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_EPQ_PGSUB_CNT_8822C) & BIT_MASK_EPQ_PGSUB_CNT_8822C) +#define BIT_SET_EPQ_PGSUB_CNT_8822C(x, v) \ + (BIT_CLEAR_EPQ_PGSUB_CNT_8822C(x) | BIT_EPQ_PGSUB_CNT_8822C(v)) + +/* 2 REG_RXDMA_AGG_PG_TH_8822C */ +#define BIT_USB_RXDMA_AGG_EN_8822C BIT(31) +#define BIT_EN_FW_ADD_8822C BIT(30) +#define BIT_EN_PRE_CALC_8822C BIT(29) +#define BIT_RXAGG_SW_EN_8822C BIT(28) +#define BIT_RXAGG_SW_TRIG_8822C BIT(27) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_DMA_AGG_TO_V1_8822C 8 +#define BIT_MASK_DMA_AGG_TO_V1_8822C 0xff +#define BIT_DMA_AGG_TO_V1_8822C(x) \ + (((x) & BIT_MASK_DMA_AGG_TO_V1_8822C) << BIT_SHIFT_DMA_AGG_TO_V1_8822C) +#define BITS_DMA_AGG_TO_V1_8822C \ + (BIT_MASK_DMA_AGG_TO_V1_8822C << BIT_SHIFT_DMA_AGG_TO_V1_8822C) +#define BIT_CLEAR_DMA_AGG_TO_V1_8822C(x) ((x) & (~BITS_DMA_AGG_TO_V1_8822C)) +#define BIT_GET_DMA_AGG_TO_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8822C) & BIT_MASK_DMA_AGG_TO_V1_8822C) +#define BIT_SET_DMA_AGG_TO_V1_8822C(x, v) \ + (BIT_CLEAR_DMA_AGG_TO_V1_8822C(x) | BIT_DMA_AGG_TO_V1_8822C(v)) + +#define BIT_SHIFT_RXDMA_AGG_PG_TH_8822C 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_8822C 0xff +#define BIT_RXDMA_AGG_PG_TH_8822C(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8822C) \ + << BIT_SHIFT_RXDMA_AGG_PG_TH_8822C) +#define BITS_RXDMA_AGG_PG_TH_8822C \ + (BIT_MASK_RXDMA_AGG_PG_TH_8822C << BIT_SHIFT_RXDMA_AGG_PG_TH_8822C) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_8822C(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8822C)) +#define BIT_GET_RXDMA_AGG_PG_TH_8822C(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8822C) & \ + BIT_MASK_RXDMA_AGG_PG_TH_8822C) +#define BIT_SET_RXDMA_AGG_PG_TH_8822C(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_8822C(x) | BIT_RXDMA_AGG_PG_TH_8822C(v)) + +/* 2 REG_RXPKT_NUM_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C 20 +#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C 0xf +#define BIT_FW_UPD_RDPTR19_TO_16_8822C(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C) \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C) +#define BITS_FW_UPD_RDPTR19_TO_16_8822C \ + (BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822C(x) \ + ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8822C)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822C(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C) & \ + BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C) +#define BIT_SET_FW_UPD_RDPTR19_TO_16_8822C(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822C(x) | \ + BIT_FW_UPD_RDPTR19_TO_16_8822C(v)) + +#define BIT_RXDMA_REQ_8822C BIT(19) +#define BIT_RW_RELEASE_EN_8822C BIT(18) +#define BIT_RXDMA_IDLE_8822C BIT(17) +#define BIT_RXPKT_RELEASE_POLL_8822C BIT(16) + +#define BIT_SHIFT_FW_UPD_RDPTR_8822C 0 +#define BIT_MASK_FW_UPD_RDPTR_8822C 0xffff +#define BIT_FW_UPD_RDPTR_8822C(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR_8822C) << BIT_SHIFT_FW_UPD_RDPTR_8822C) +#define BITS_FW_UPD_RDPTR_8822C \ + (BIT_MASK_FW_UPD_RDPTR_8822C << BIT_SHIFT_FW_UPD_RDPTR_8822C) +#define BIT_CLEAR_FW_UPD_RDPTR_8822C(x) ((x) & (~BITS_FW_UPD_RDPTR_8822C)) +#define BIT_GET_FW_UPD_RDPTR_8822C(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822C) & BIT_MASK_FW_UPD_RDPTR_8822C) +#define BIT_SET_FW_UPD_RDPTR_8822C(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR_8822C(x) | BIT_FW_UPD_RDPTR_8822C(v)) + +/* 2 REG_RXDMA_STATUS_8822C */ +#define BIT_C2H_PKT_OVF_8822C BIT(7) +#define BIT_AGG_CONFGI_ISSUE_8822C BIT(6) +#define BIT_FW_POLL_ISSUE_8822C BIT(5) +#define BIT_RX_DATA_UDN_8822C BIT(4) +#define BIT_RX_SFF_UDN_8822C BIT(3) +#define BIT_RX_SFF_OVF_8822C BIT(2) +#define BIT_RXPKT_OVF_8822C BIT(0) + +/* 2 REG_RXDMA_DPR_8822C */ + +#define BIT_SHIFT_RDE_DEBUG_8822C 0 +#define BIT_MASK_RDE_DEBUG_8822C 0xffffffffL +#define BIT_RDE_DEBUG_8822C(x) \ + (((x) & BIT_MASK_RDE_DEBUG_8822C) << BIT_SHIFT_RDE_DEBUG_8822C) +#define BITS_RDE_DEBUG_8822C \ + (BIT_MASK_RDE_DEBUG_8822C << BIT_SHIFT_RDE_DEBUG_8822C) +#define BIT_CLEAR_RDE_DEBUG_8822C(x) ((x) & (~BITS_RDE_DEBUG_8822C)) +#define BIT_GET_RDE_DEBUG_8822C(x) \ + (((x) >> BIT_SHIFT_RDE_DEBUG_8822C) & BIT_MASK_RDE_DEBUG_8822C) +#define BIT_SET_RDE_DEBUG_8822C(x, v) \ + (BIT_CLEAR_RDE_DEBUG_8822C(x) | BIT_RDE_DEBUG_8822C(v)) + +/* 2 REG_RXDMA_MODE_8822C */ + +#define BIT_SHIFT_PKTNUM_TH_V2_8822C 24 +#define BIT_MASK_PKTNUM_TH_V2_8822C 0x1f +#define BIT_PKTNUM_TH_V2_8822C(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V2_8822C) << BIT_SHIFT_PKTNUM_TH_V2_8822C) +#define BITS_PKTNUM_TH_V2_8822C \ + (BIT_MASK_PKTNUM_TH_V2_8822C << BIT_SHIFT_PKTNUM_TH_V2_8822C) +#define BIT_CLEAR_PKTNUM_TH_V2_8822C(x) ((x) & (~BITS_PKTNUM_TH_V2_8822C)) +#define BIT_GET_PKTNUM_TH_V2_8822C(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822C) & BIT_MASK_PKTNUM_TH_V2_8822C) +#define BIT_SET_PKTNUM_TH_V2_8822C(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V2_8822C(x) | BIT_PKTNUM_TH_V2_8822C(v)) + +#define BIT_TXBA_BREAK_USBAGG_8822C BIT(23) + +#define BIT_SHIFT_PKTLEN_PARA_8822C 16 +#define BIT_MASK_PKTLEN_PARA_8822C 0x7 +#define BIT_PKTLEN_PARA_8822C(x) \ + (((x) & BIT_MASK_PKTLEN_PARA_8822C) << BIT_SHIFT_PKTLEN_PARA_8822C) +#define BITS_PKTLEN_PARA_8822C \ + (BIT_MASK_PKTLEN_PARA_8822C << BIT_SHIFT_PKTLEN_PARA_8822C) +#define BIT_CLEAR_PKTLEN_PARA_8822C(x) ((x) & (~BITS_PKTLEN_PARA_8822C)) +#define BIT_GET_PKTLEN_PARA_8822C(x) \ + (((x) >> BIT_SHIFT_PKTLEN_PARA_8822C) & BIT_MASK_PKTLEN_PARA_8822C) +#define BIT_SET_PKTLEN_PARA_8822C(x, v) \ + (BIT_CLEAR_PKTLEN_PARA_8822C(x) | BIT_PKTLEN_PARA_8822C(v)) + +#define BIT_RX_DBG_SEL_8822C BIT(7) +#define BIT_EN_SPD_8822C BIT(6) + +#define BIT_SHIFT_BURST_SIZE_8822C 4 +#define BIT_MASK_BURST_SIZE_8822C 0x3 +#define BIT_BURST_SIZE_8822C(x) \ + (((x) & BIT_MASK_BURST_SIZE_8822C) << BIT_SHIFT_BURST_SIZE_8822C) +#define BITS_BURST_SIZE_8822C \ + (BIT_MASK_BURST_SIZE_8822C << BIT_SHIFT_BURST_SIZE_8822C) +#define BIT_CLEAR_BURST_SIZE_8822C(x) ((x) & (~BITS_BURST_SIZE_8822C)) +#define BIT_GET_BURST_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_BURST_SIZE_8822C) & BIT_MASK_BURST_SIZE_8822C) +#define BIT_SET_BURST_SIZE_8822C(x, v) \ + (BIT_CLEAR_BURST_SIZE_8822C(x) | BIT_BURST_SIZE_8822C(v)) + +#define BIT_SHIFT_BURST_CNT_8822C 2 +#define BIT_MASK_BURST_CNT_8822C 0x3 +#define BIT_BURST_CNT_8822C(x) \ + (((x) & BIT_MASK_BURST_CNT_8822C) << BIT_SHIFT_BURST_CNT_8822C) +#define BITS_BURST_CNT_8822C \ + (BIT_MASK_BURST_CNT_8822C << BIT_SHIFT_BURST_CNT_8822C) +#define BIT_CLEAR_BURST_CNT_8822C(x) ((x) & (~BITS_BURST_CNT_8822C)) +#define BIT_GET_BURST_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_BURST_CNT_8822C) & BIT_MASK_BURST_CNT_8822C) +#define BIT_SET_BURST_CNT_8822C(x, v) \ + (BIT_CLEAR_BURST_CNT_8822C(x) | BIT_BURST_CNT_8822C(v)) + +#define BIT_DMA_MODE_8822C BIT(1) + +/* 2 REG_C2H_PKT_8822C */ + +#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C 24 +#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C 0xf +#define BIT_R_C2H_STR_ADDR_16_TO_19_8822C(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C) \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C) +#define BITS_R_C2H_STR_ADDR_16_TO_19_8822C \ + (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822C(x) \ + ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8822C)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822C(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C) & \ + BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8822C(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822C(x) | \ + BIT_R_C2H_STR_ADDR_16_TO_19_8822C(v)) + +#define BIT_R_C2H_PKT_REQ_8822C BIT(16) + +#define BIT_SHIFT_R_C2H_STR_ADDR_8822C 0 +#define BIT_MASK_R_C2H_STR_ADDR_8822C 0xffff +#define BIT_R_C2H_STR_ADDR_8822C(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_8822C) \ + << BIT_SHIFT_R_C2H_STR_ADDR_8822C) +#define BITS_R_C2H_STR_ADDR_8822C \ + (BIT_MASK_R_C2H_STR_ADDR_8822C << BIT_SHIFT_R_C2H_STR_ADDR_8822C) +#define BIT_CLEAR_R_C2H_STR_ADDR_8822C(x) ((x) & (~BITS_R_C2H_STR_ADDR_8822C)) +#define BIT_GET_R_C2H_STR_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822C) & \ + BIT_MASK_R_C2H_STR_ADDR_8822C) +#define BIT_SET_R_C2H_STR_ADDR_8822C(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_8822C(x) | BIT_R_C2H_STR_ADDR_8822C(v)) + +/* 2 REG_FWFF_C2H_8822C */ + +#define BIT_SHIFT_C2H_DMA_ADDR_8822C 0 +#define BIT_MASK_C2H_DMA_ADDR_8822C 0x3ffff +#define BIT_C2H_DMA_ADDR_8822C(x) \ + (((x) & BIT_MASK_C2H_DMA_ADDR_8822C) << BIT_SHIFT_C2H_DMA_ADDR_8822C) +#define BITS_C2H_DMA_ADDR_8822C \ + (BIT_MASK_C2H_DMA_ADDR_8822C << BIT_SHIFT_C2H_DMA_ADDR_8822C) +#define BIT_CLEAR_C2H_DMA_ADDR_8822C(x) ((x) & (~BITS_C2H_DMA_ADDR_8822C)) +#define BIT_GET_C2H_DMA_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822C) & BIT_MASK_C2H_DMA_ADDR_8822C) +#define BIT_SET_C2H_DMA_ADDR_8822C(x, v) \ + (BIT_CLEAR_C2H_DMA_ADDR_8822C(x) | BIT_C2H_DMA_ADDR_8822C(v)) + +/* 2 REG_FWFF_CTRL_8822C */ +#define BIT_FWFF_DMAPKT_REQ_8822C BIT(31) + +#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C 16 +#define BIT_MASK_FWFF_DMA_PKT_NUM_8822C 0xff +#define BIT_FWFF_DMA_PKT_NUM_8822C(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822C) \ + << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C) +#define BITS_FWFF_DMA_PKT_NUM_8822C \ + (BIT_MASK_FWFF_DMA_PKT_NUM_8822C << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8822C(x) \ + ((x) & (~BITS_FWFF_DMA_PKT_NUM_8822C)) +#define BIT_GET_FWFF_DMA_PKT_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C) & \ + BIT_MASK_FWFF_DMA_PKT_NUM_8822C) +#define BIT_SET_FWFF_DMA_PKT_NUM_8822C(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM_8822C(x) | BIT_FWFF_DMA_PKT_NUM_8822C(v)) + +#define BIT_SHIFT_FWFF_STR_ADDR_8822C 0 +#define BIT_MASK_FWFF_STR_ADDR_8822C 0xffff +#define BIT_FWFF_STR_ADDR_8822C(x) \ + (((x) & BIT_MASK_FWFF_STR_ADDR_8822C) << BIT_SHIFT_FWFF_STR_ADDR_8822C) +#define BITS_FWFF_STR_ADDR_8822C \ + (BIT_MASK_FWFF_STR_ADDR_8822C << BIT_SHIFT_FWFF_STR_ADDR_8822C) +#define BIT_CLEAR_FWFF_STR_ADDR_8822C(x) ((x) & (~BITS_FWFF_STR_ADDR_8822C)) +#define BIT_GET_FWFF_STR_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822C) & BIT_MASK_FWFF_STR_ADDR_8822C) +#define BIT_SET_FWFF_STR_ADDR_8822C(x, v) \ + (BIT_CLEAR_FWFF_STR_ADDR_8822C(x) | BIT_FWFF_STR_ADDR_8822C(v)) + +/* 2 REG_FWFF_PKT_INFO_8822C */ + +#define BIT_SHIFT_FWFF_PKT_QUEUED_8822C 16 +#define BIT_MASK_FWFF_PKT_QUEUED_8822C 0xff +#define BIT_FWFF_PKT_QUEUED_8822C(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED_8822C) \ + << BIT_SHIFT_FWFF_PKT_QUEUED_8822C) +#define BITS_FWFF_PKT_QUEUED_8822C \ + (BIT_MASK_FWFF_PKT_QUEUED_8822C << BIT_SHIFT_FWFF_PKT_QUEUED_8822C) +#define BIT_CLEAR_FWFF_PKT_QUEUED_8822C(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8822C)) +#define BIT_GET_FWFF_PKT_QUEUED_8822C(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822C) & \ + BIT_MASK_FWFF_PKT_QUEUED_8822C) +#define BIT_SET_FWFF_PKT_QUEUED_8822C(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED_8822C(x) | BIT_FWFF_PKT_QUEUED_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C 0 +#define BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C 0x3fff +#define BIT_FWFF_PKT_STR_ADDR_V2_8822C(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C) \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C) +#define BITS_FWFF_PKT_STR_ADDR_V2_8822C \ + (BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V2_8822C(x) \ + ((x) & (~BITS_FWFF_PKT_STR_ADDR_V2_8822C)) +#define BIT_GET_FWFF_PKT_STR_ADDR_V2_8822C(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C) & \ + BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C) +#define BIT_SET_FWFF_PKT_STR_ADDR_V2_8822C(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR_V2_8822C(x) | \ + BIT_FWFF_PKT_STR_ADDR_V2_8822C(v)) + +/* 2 REG_RXPKTNUM_8822C */ + +#define BIT_SHIFT_PKT_NUM_WOL_V1_8822C 16 +#define BIT_MASK_PKT_NUM_WOL_V1_8822C 0xffff +#define BIT_PKT_NUM_WOL_V1_8822C(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL_V1_8822C) \ + << BIT_SHIFT_PKT_NUM_WOL_V1_8822C) +#define BITS_PKT_NUM_WOL_V1_8822C \ + (BIT_MASK_PKT_NUM_WOL_V1_8822C << BIT_SHIFT_PKT_NUM_WOL_V1_8822C) +#define BIT_CLEAR_PKT_NUM_WOL_V1_8822C(x) ((x) & (~BITS_PKT_NUM_WOL_V1_8822C)) +#define BIT_GET_PKT_NUM_WOL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL_V1_8822C) & \ + BIT_MASK_PKT_NUM_WOL_V1_8822C) +#define BIT_SET_PKT_NUM_WOL_V1_8822C(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL_V1_8822C(x) | BIT_PKT_NUM_WOL_V1_8822C(v)) + +#define BIT_SHIFT_RXPKT_NUM_V1_8822C 0 +#define BIT_MASK_RXPKT_NUM_V1_8822C 0xffff +#define BIT_RXPKT_NUM_V1_8822C(x) \ + (((x) & BIT_MASK_RXPKT_NUM_V1_8822C) << BIT_SHIFT_RXPKT_NUM_V1_8822C) +#define BITS_RXPKT_NUM_V1_8822C \ + (BIT_MASK_RXPKT_NUM_V1_8822C << BIT_SHIFT_RXPKT_NUM_V1_8822C) +#define BIT_CLEAR_RXPKT_NUM_V1_8822C(x) ((x) & (~BITS_RXPKT_NUM_V1_8822C)) +#define BIT_GET_RXPKT_NUM_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_V1_8822C) & BIT_MASK_RXPKT_NUM_V1_8822C) +#define BIT_SET_RXPKT_NUM_V1_8822C(x, v) \ + (BIT_CLEAR_RXPKT_NUM_V1_8822C(x) | BIT_RXPKT_NUM_V1_8822C(v)) + +/* 2 REG_RXPKTNUM_TH_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_RXPKT_NUM_TH_8822C 0 +#define BIT_MASK_RXPKT_NUM_TH_8822C 0xff +#define BIT_RXPKT_NUM_TH_8822C(x) \ + (((x) & BIT_MASK_RXPKT_NUM_TH_8822C) << BIT_SHIFT_RXPKT_NUM_TH_8822C) +#define BITS_RXPKT_NUM_TH_8822C \ + (BIT_MASK_RXPKT_NUM_TH_8822C << BIT_SHIFT_RXPKT_NUM_TH_8822C) +#define BIT_CLEAR_RXPKT_NUM_TH_8822C(x) ((x) & (~BITS_RXPKT_NUM_TH_8822C)) +#define BIT_GET_RXPKT_NUM_TH_8822C(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_TH_8822C) & BIT_MASK_RXPKT_NUM_TH_8822C) +#define BIT_SET_RXPKT_NUM_TH_8822C(x, v) \ + (BIT_CLEAR_RXPKT_NUM_TH_8822C(x) | BIT_RXPKT_NUM_TH_8822C(v)) + +/* 2 REG_FW_MSG1_8822C */ + +#define BIT_SHIFT_FW_MSG_REG1_8822C 0 +#define BIT_MASK_FW_MSG_REG1_8822C 0xffffffffL +#define BIT_FW_MSG_REG1_8822C(x) \ + (((x) & BIT_MASK_FW_MSG_REG1_8822C) << BIT_SHIFT_FW_MSG_REG1_8822C) +#define BITS_FW_MSG_REG1_8822C \ + (BIT_MASK_FW_MSG_REG1_8822C << BIT_SHIFT_FW_MSG_REG1_8822C) +#define BIT_CLEAR_FW_MSG_REG1_8822C(x) ((x) & (~BITS_FW_MSG_REG1_8822C)) +#define BIT_GET_FW_MSG_REG1_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG1_8822C) & BIT_MASK_FW_MSG_REG1_8822C) +#define BIT_SET_FW_MSG_REG1_8822C(x, v) \ + (BIT_CLEAR_FW_MSG_REG1_8822C(x) | BIT_FW_MSG_REG1_8822C(v)) + +/* 2 REG_FW_MSG2_8822C */ + +#define BIT_SHIFT_FW_MSG_REG2_8822C 0 +#define BIT_MASK_FW_MSG_REG2_8822C 0xffffffffL +#define BIT_FW_MSG_REG2_8822C(x) \ + (((x) & BIT_MASK_FW_MSG_REG2_8822C) << BIT_SHIFT_FW_MSG_REG2_8822C) +#define BITS_FW_MSG_REG2_8822C \ + (BIT_MASK_FW_MSG_REG2_8822C << BIT_SHIFT_FW_MSG_REG2_8822C) +#define BIT_CLEAR_FW_MSG_REG2_8822C(x) ((x) & (~BITS_FW_MSG_REG2_8822C)) +#define BIT_GET_FW_MSG_REG2_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG2_8822C) & BIT_MASK_FW_MSG_REG2_8822C) +#define BIT_SET_FW_MSG_REG2_8822C(x, v) \ + (BIT_CLEAR_FW_MSG_REG2_8822C(x) | BIT_FW_MSG_REG2_8822C(v)) + +/* 2 REG_FW_MSG3_8822C */ + +#define BIT_SHIFT_FW_MSG_REG3_8822C 0 +#define BIT_MASK_FW_MSG_REG3_8822C 0xffffffffL +#define BIT_FW_MSG_REG3_8822C(x) \ + (((x) & BIT_MASK_FW_MSG_REG3_8822C) << BIT_SHIFT_FW_MSG_REG3_8822C) +#define BITS_FW_MSG_REG3_8822C \ + (BIT_MASK_FW_MSG_REG3_8822C << BIT_SHIFT_FW_MSG_REG3_8822C) +#define BIT_CLEAR_FW_MSG_REG3_8822C(x) ((x) & (~BITS_FW_MSG_REG3_8822C)) +#define BIT_GET_FW_MSG_REG3_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG3_8822C) & BIT_MASK_FW_MSG_REG3_8822C) +#define BIT_SET_FW_MSG_REG3_8822C(x, v) \ + (BIT_CLEAR_FW_MSG_REG3_8822C(x) | BIT_FW_MSG_REG3_8822C(v)) + +/* 2 REG_FW_MSG4_8822C */ + +#define BIT_SHIFT_FW_MSG_REG4_8822C 0 +#define BIT_MASK_FW_MSG_REG4_8822C 0xffffffffL +#define BIT_FW_MSG_REG4_8822C(x) \ + (((x) & BIT_MASK_FW_MSG_REG4_8822C) << BIT_SHIFT_FW_MSG_REG4_8822C) +#define BITS_FW_MSG_REG4_8822C \ + (BIT_MASK_FW_MSG_REG4_8822C << BIT_SHIFT_FW_MSG_REG4_8822C) +#define BIT_CLEAR_FW_MSG_REG4_8822C(x) ((x) & (~BITS_FW_MSG_REG4_8822C)) +#define BIT_GET_FW_MSG_REG4_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG4_8822C) & BIT_MASK_FW_MSG_REG4_8822C) +#define BIT_SET_FW_MSG_REG4_8822C(x, v) \ + (BIT_CLEAR_FW_MSG_REG4_8822C(x) | BIT_FW_MSG_REG4_8822C(v)) + +/* 2 REG_DDMA_CH0SA_8822C */ + +#define BIT_SHIFT_DDMACH0_SA_8822C 0 +#define BIT_MASK_DDMACH0_SA_8822C 0xffffffffL +#define BIT_DDMACH0_SA_8822C(x) \ + (((x) & BIT_MASK_DDMACH0_SA_8822C) << BIT_SHIFT_DDMACH0_SA_8822C) +#define BITS_DDMACH0_SA_8822C \ + (BIT_MASK_DDMACH0_SA_8822C << BIT_SHIFT_DDMACH0_SA_8822C) +#define BIT_CLEAR_DDMACH0_SA_8822C(x) ((x) & (~BITS_DDMACH0_SA_8822C)) +#define BIT_GET_DDMACH0_SA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH0_SA_8822C) & BIT_MASK_DDMACH0_SA_8822C) +#define BIT_SET_DDMACH0_SA_8822C(x, v) \ + (BIT_CLEAR_DDMACH0_SA_8822C(x) | BIT_DDMACH0_SA_8822C(v)) + +/* 2 REG_DDMA_CH0DA_8822C */ + +#define BIT_SHIFT_DDMACH0_DA_8822C 0 +#define BIT_MASK_DDMACH0_DA_8822C 0xffffffffL +#define BIT_DDMACH0_DA_8822C(x) \ + (((x) & BIT_MASK_DDMACH0_DA_8822C) << BIT_SHIFT_DDMACH0_DA_8822C) +#define BITS_DDMACH0_DA_8822C \ + (BIT_MASK_DDMACH0_DA_8822C << BIT_SHIFT_DDMACH0_DA_8822C) +#define BIT_CLEAR_DDMACH0_DA_8822C(x) ((x) & (~BITS_DDMACH0_DA_8822C)) +#define BIT_GET_DDMACH0_DA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DA_8822C) & BIT_MASK_DDMACH0_DA_8822C) +#define BIT_SET_DDMACH0_DA_8822C(x, v) \ + (BIT_CLEAR_DDMACH0_DA_8822C(x) | BIT_DDMACH0_DA_8822C(v)) + +/* 2 REG_DDMA_CH0CTRL_8822C */ +#define BIT_DDMACH0_OWN_8822C BIT(31) +#define BIT_DDMACH0_IDMEM_ERR_8822C BIT(30) +#define BIT_DDMACH0_CHKSUM_EN_8822C BIT(29) +#define BIT_DDMACH0_DA_W_DISABLE_8822C BIT(28) +#define BIT_DDMACH0_CHKSUM_STS_8822C BIT(27) +#define BIT_DDMACH0_DDMA_MODE_8822C BIT(26) +#define BIT_DDMACH0_RESET_CHKSUM_STS_8822C BIT(25) +#define BIT_DDMACH0_CHKSUM_CONT_8822C BIT(24) + +#define BIT_SHIFT_DDMACH0_DLEN_8822C 0 +#define BIT_MASK_DDMACH0_DLEN_8822C 0x3ffff +#define BIT_DDMACH0_DLEN_8822C(x) \ + (((x) & BIT_MASK_DDMACH0_DLEN_8822C) << BIT_SHIFT_DDMACH0_DLEN_8822C) +#define BITS_DDMACH0_DLEN_8822C \ + (BIT_MASK_DDMACH0_DLEN_8822C << BIT_SHIFT_DDMACH0_DLEN_8822C) +#define BIT_CLEAR_DDMACH0_DLEN_8822C(x) ((x) & (~BITS_DDMACH0_DLEN_8822C)) +#define BIT_GET_DDMACH0_DLEN_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DLEN_8822C) & BIT_MASK_DDMACH0_DLEN_8822C) +#define BIT_SET_DDMACH0_DLEN_8822C(x, v) \ + (BIT_CLEAR_DDMACH0_DLEN_8822C(x) | BIT_DDMACH0_DLEN_8822C(v)) + +/* 2 REG_DDMA_CH1SA_8822C */ + +#define BIT_SHIFT_DDMACH1_SA_8822C 0 +#define BIT_MASK_DDMACH1_SA_8822C 0xffffffffL +#define BIT_DDMACH1_SA_8822C(x) \ + (((x) & BIT_MASK_DDMACH1_SA_8822C) << BIT_SHIFT_DDMACH1_SA_8822C) +#define BITS_DDMACH1_SA_8822C \ + (BIT_MASK_DDMACH1_SA_8822C << BIT_SHIFT_DDMACH1_SA_8822C) +#define BIT_CLEAR_DDMACH1_SA_8822C(x) ((x) & (~BITS_DDMACH1_SA_8822C)) +#define BIT_GET_DDMACH1_SA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH1_SA_8822C) & BIT_MASK_DDMACH1_SA_8822C) +#define BIT_SET_DDMACH1_SA_8822C(x, v) \ + (BIT_CLEAR_DDMACH1_SA_8822C(x) | BIT_DDMACH1_SA_8822C(v)) + +/* 2 REG_DDMA_CH1DA_8822C */ + +#define BIT_SHIFT_DDMACH1_DA_8822C 0 +#define BIT_MASK_DDMACH1_DA_8822C 0xffffffffL +#define BIT_DDMACH1_DA_8822C(x) \ + (((x) & BIT_MASK_DDMACH1_DA_8822C) << BIT_SHIFT_DDMACH1_DA_8822C) +#define BITS_DDMACH1_DA_8822C \ + (BIT_MASK_DDMACH1_DA_8822C << BIT_SHIFT_DDMACH1_DA_8822C) +#define BIT_CLEAR_DDMACH1_DA_8822C(x) ((x) & (~BITS_DDMACH1_DA_8822C)) +#define BIT_GET_DDMACH1_DA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DA_8822C) & BIT_MASK_DDMACH1_DA_8822C) +#define BIT_SET_DDMACH1_DA_8822C(x, v) \ + (BIT_CLEAR_DDMACH1_DA_8822C(x) | BIT_DDMACH1_DA_8822C(v)) + +/* 2 REG_DDMA_CH1CTRL_8822C */ +#define BIT_DDMACH1_OWN_8822C BIT(31) +#define BIT_DDMACH1_IDMEM_ERR_8822C BIT(30) +#define BIT_DDMACH1_CHKSUM_EN_8822C BIT(29) +#define BIT_DDMACH1_DA_W_DISABLE_8822C BIT(28) +#define BIT_DDMACH1_CHKSUM_STS_8822C BIT(27) +#define BIT_DDMACH1_DDMA_MODE_8822C BIT(26) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_DDMACH1_DLEN_8822C 0 +#define BIT_MASK_DDMACH1_DLEN_8822C 0x3ffff +#define BIT_DDMACH1_DLEN_8822C(x) \ + (((x) & BIT_MASK_DDMACH1_DLEN_8822C) << BIT_SHIFT_DDMACH1_DLEN_8822C) +#define BITS_DDMACH1_DLEN_8822C \ + (BIT_MASK_DDMACH1_DLEN_8822C << BIT_SHIFT_DDMACH1_DLEN_8822C) +#define BIT_CLEAR_DDMACH1_DLEN_8822C(x) ((x) & (~BITS_DDMACH1_DLEN_8822C)) +#define BIT_GET_DDMACH1_DLEN_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DLEN_8822C) & BIT_MASK_DDMACH1_DLEN_8822C) +#define BIT_SET_DDMACH1_DLEN_8822C(x, v) \ + (BIT_CLEAR_DDMACH1_DLEN_8822C(x) | BIT_DDMACH1_DLEN_8822C(v)) + +/* 2 REG_DDMA_CH2SA_8822C */ + +#define BIT_SHIFT_DDMACH2_SA_8822C 0 +#define BIT_MASK_DDMACH2_SA_8822C 0xffffffffL +#define BIT_DDMACH2_SA_8822C(x) \ + (((x) & BIT_MASK_DDMACH2_SA_8822C) << BIT_SHIFT_DDMACH2_SA_8822C) +#define BITS_DDMACH2_SA_8822C \ + (BIT_MASK_DDMACH2_SA_8822C << BIT_SHIFT_DDMACH2_SA_8822C) +#define BIT_CLEAR_DDMACH2_SA_8822C(x) ((x) & (~BITS_DDMACH2_SA_8822C)) +#define BIT_GET_DDMACH2_SA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH2_SA_8822C) & BIT_MASK_DDMACH2_SA_8822C) +#define BIT_SET_DDMACH2_SA_8822C(x, v) \ + (BIT_CLEAR_DDMACH2_SA_8822C(x) | BIT_DDMACH2_SA_8822C(v)) + +/* 2 REG_DDMA_CH2DA_8822C */ + +#define BIT_SHIFT_DDMACH2_DA_8822C 0 +#define BIT_MASK_DDMACH2_DA_8822C 0xffffffffL +#define BIT_DDMACH2_DA_8822C(x) \ + (((x) & BIT_MASK_DDMACH2_DA_8822C) << BIT_SHIFT_DDMACH2_DA_8822C) +#define BITS_DDMACH2_DA_8822C \ + (BIT_MASK_DDMACH2_DA_8822C << BIT_SHIFT_DDMACH2_DA_8822C) +#define BIT_CLEAR_DDMACH2_DA_8822C(x) ((x) & (~BITS_DDMACH2_DA_8822C)) +#define BIT_GET_DDMACH2_DA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DA_8822C) & BIT_MASK_DDMACH2_DA_8822C) +#define BIT_SET_DDMACH2_DA_8822C(x, v) \ + (BIT_CLEAR_DDMACH2_DA_8822C(x) | BIT_DDMACH2_DA_8822C(v)) + +/* 2 REG_DDMA_CH2CTRL_8822C */ +#define BIT_DDMACH2_OWN_8822C BIT(31) +#define BIT_DDMACH2_IDMEM_ERR_8822C BIT(30) +#define BIT_DDMACH2_CHKSUM_EN_8822C BIT(29) +#define BIT_DDMACH2_DA_W_DISABLE_8822C BIT(28) +#define BIT_DDMACH2_CHKSUM_STS_8822C BIT(27) +#define BIT_DDMACH2_DDMA_MODE_8822C BIT(26) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_DDMACH2_DLEN_8822C 0 +#define BIT_MASK_DDMACH2_DLEN_8822C 0x3ffff +#define BIT_DDMACH2_DLEN_8822C(x) \ + (((x) & BIT_MASK_DDMACH2_DLEN_8822C) << BIT_SHIFT_DDMACH2_DLEN_8822C) +#define BITS_DDMACH2_DLEN_8822C \ + (BIT_MASK_DDMACH2_DLEN_8822C << BIT_SHIFT_DDMACH2_DLEN_8822C) +#define BIT_CLEAR_DDMACH2_DLEN_8822C(x) ((x) & (~BITS_DDMACH2_DLEN_8822C)) +#define BIT_GET_DDMACH2_DLEN_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DLEN_8822C) & BIT_MASK_DDMACH2_DLEN_8822C) +#define BIT_SET_DDMACH2_DLEN_8822C(x, v) \ + (BIT_CLEAR_DDMACH2_DLEN_8822C(x) | BIT_DDMACH2_DLEN_8822C(v)) + +/* 2 REG_DDMA_CH3SA_8822C */ + +#define BIT_SHIFT_DDMACH3_SA_8822C 0 +#define BIT_MASK_DDMACH3_SA_8822C 0xffffffffL +#define BIT_DDMACH3_SA_8822C(x) \ + (((x) & BIT_MASK_DDMACH3_SA_8822C) << BIT_SHIFT_DDMACH3_SA_8822C) +#define BITS_DDMACH3_SA_8822C \ + (BIT_MASK_DDMACH3_SA_8822C << BIT_SHIFT_DDMACH3_SA_8822C) +#define BIT_CLEAR_DDMACH3_SA_8822C(x) ((x) & (~BITS_DDMACH3_SA_8822C)) +#define BIT_GET_DDMACH3_SA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH3_SA_8822C) & BIT_MASK_DDMACH3_SA_8822C) +#define BIT_SET_DDMACH3_SA_8822C(x, v) \ + (BIT_CLEAR_DDMACH3_SA_8822C(x) | BIT_DDMACH3_SA_8822C(v)) + +/* 2 REG_DDMA_CH3DA_8822C */ + +#define BIT_SHIFT_DDMACH3_DA_8822C 0 +#define BIT_MASK_DDMACH3_DA_8822C 0xffffffffL +#define BIT_DDMACH3_DA_8822C(x) \ + (((x) & BIT_MASK_DDMACH3_DA_8822C) << BIT_SHIFT_DDMACH3_DA_8822C) +#define BITS_DDMACH3_DA_8822C \ + (BIT_MASK_DDMACH3_DA_8822C << BIT_SHIFT_DDMACH3_DA_8822C) +#define BIT_CLEAR_DDMACH3_DA_8822C(x) ((x) & (~BITS_DDMACH3_DA_8822C)) +#define BIT_GET_DDMACH3_DA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DA_8822C) & BIT_MASK_DDMACH3_DA_8822C) +#define BIT_SET_DDMACH3_DA_8822C(x, v) \ + (BIT_CLEAR_DDMACH3_DA_8822C(x) | BIT_DDMACH3_DA_8822C(v)) + +/* 2 REG_DDMA_CH3CTRL_8822C */ +#define BIT_DDMACH3_OWN_8822C BIT(31) +#define BIT_DDMACH3_IDMEM_ERR_8822C BIT(30) +#define BIT_DDMACH3_CHKSUM_EN_8822C BIT(29) +#define BIT_DDMACH3_DA_W_DISABLE_8822C BIT(28) +#define BIT_DDMACH3_CHKSUM_STS_8822C BIT(27) +#define BIT_DDMACH3_DDMA_MODE_8822C BIT(26) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_DDMACH3_DLEN_8822C 0 +#define BIT_MASK_DDMACH3_DLEN_8822C 0x3ffff +#define BIT_DDMACH3_DLEN_8822C(x) \ + (((x) & BIT_MASK_DDMACH3_DLEN_8822C) << BIT_SHIFT_DDMACH3_DLEN_8822C) +#define BITS_DDMACH3_DLEN_8822C \ + (BIT_MASK_DDMACH3_DLEN_8822C << BIT_SHIFT_DDMACH3_DLEN_8822C) +#define BIT_CLEAR_DDMACH3_DLEN_8822C(x) ((x) & (~BITS_DDMACH3_DLEN_8822C)) +#define BIT_GET_DDMACH3_DLEN_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DLEN_8822C) & BIT_MASK_DDMACH3_DLEN_8822C) +#define BIT_SET_DDMACH3_DLEN_8822C(x, v) \ + (BIT_CLEAR_DDMACH3_DLEN_8822C(x) | BIT_DDMACH3_DLEN_8822C(v)) + +/* 2 REG_DDMA_CH4SA_8822C */ + +#define BIT_SHIFT_DDMACH4_SA_8822C 0 +#define BIT_MASK_DDMACH4_SA_8822C 0xffffffffL +#define BIT_DDMACH4_SA_8822C(x) \ + (((x) & BIT_MASK_DDMACH4_SA_8822C) << BIT_SHIFT_DDMACH4_SA_8822C) +#define BITS_DDMACH4_SA_8822C \ + (BIT_MASK_DDMACH4_SA_8822C << BIT_SHIFT_DDMACH4_SA_8822C) +#define BIT_CLEAR_DDMACH4_SA_8822C(x) ((x) & (~BITS_DDMACH4_SA_8822C)) +#define BIT_GET_DDMACH4_SA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH4_SA_8822C) & BIT_MASK_DDMACH4_SA_8822C) +#define BIT_SET_DDMACH4_SA_8822C(x, v) \ + (BIT_CLEAR_DDMACH4_SA_8822C(x) | BIT_DDMACH4_SA_8822C(v)) + +/* 2 REG_DDMA_CH4DA_8822C */ + +#define BIT_SHIFT_DDMACH4_DA_8822C 0 +#define BIT_MASK_DDMACH4_DA_8822C 0xffffffffL +#define BIT_DDMACH4_DA_8822C(x) \ + (((x) & BIT_MASK_DDMACH4_DA_8822C) << BIT_SHIFT_DDMACH4_DA_8822C) +#define BITS_DDMACH4_DA_8822C \ + (BIT_MASK_DDMACH4_DA_8822C << BIT_SHIFT_DDMACH4_DA_8822C) +#define BIT_CLEAR_DDMACH4_DA_8822C(x) ((x) & (~BITS_DDMACH4_DA_8822C)) +#define BIT_GET_DDMACH4_DA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DA_8822C) & BIT_MASK_DDMACH4_DA_8822C) +#define BIT_SET_DDMACH4_DA_8822C(x, v) \ + (BIT_CLEAR_DDMACH4_DA_8822C(x) | BIT_DDMACH4_DA_8822C(v)) + +/* 2 REG_DDMA_CH4CTRL_8822C */ +#define BIT_DDMACH4_OWN_8822C BIT(31) +#define BIT_DDMACH4_IDMEM_ERR_8822C BIT(30) +#define BIT_DDMACH4_CHKSUM_EN_8822C BIT(29) +#define BIT_DDMACH4_DA_W_DISABLE_8822C BIT(28) +#define BIT_DDMACH4_CHKSUM_STS_8822C BIT(27) +#define BIT_DDMACH4_DDMA_MODE_8822C BIT(26) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_DDMACH4_DLEN_8822C 0 +#define BIT_MASK_DDMACH4_DLEN_8822C 0x3ffff +#define BIT_DDMACH4_DLEN_8822C(x) \ + (((x) & BIT_MASK_DDMACH4_DLEN_8822C) << BIT_SHIFT_DDMACH4_DLEN_8822C) +#define BITS_DDMACH4_DLEN_8822C \ + (BIT_MASK_DDMACH4_DLEN_8822C << BIT_SHIFT_DDMACH4_DLEN_8822C) +#define BIT_CLEAR_DDMACH4_DLEN_8822C(x) ((x) & (~BITS_DDMACH4_DLEN_8822C)) +#define BIT_GET_DDMACH4_DLEN_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DLEN_8822C) & BIT_MASK_DDMACH4_DLEN_8822C) +#define BIT_SET_DDMACH4_DLEN_8822C(x, v) \ + (BIT_CLEAR_DDMACH4_DLEN_8822C(x) | BIT_DDMACH4_DLEN_8822C(v)) + +/* 2 REG_DDMA_CH5SA_8822C */ + +#define BIT_SHIFT_DDMACH5_SA_8822C 0 +#define BIT_MASK_DDMACH5_SA_8822C 0xffffffffL +#define BIT_DDMACH5_SA_8822C(x) \ + (((x) & BIT_MASK_DDMACH5_SA_8822C) << BIT_SHIFT_DDMACH5_SA_8822C) +#define BITS_DDMACH5_SA_8822C \ + (BIT_MASK_DDMACH5_SA_8822C << BIT_SHIFT_DDMACH5_SA_8822C) +#define BIT_CLEAR_DDMACH5_SA_8822C(x) ((x) & (~BITS_DDMACH5_SA_8822C)) +#define BIT_GET_DDMACH5_SA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH5_SA_8822C) & BIT_MASK_DDMACH5_SA_8822C) +#define BIT_SET_DDMACH5_SA_8822C(x, v) \ + (BIT_CLEAR_DDMACH5_SA_8822C(x) | BIT_DDMACH5_SA_8822C(v)) + +/* 2 REG_DDMA_CH5DA_8822C */ + +#define BIT_SHIFT_DDMACH5_DA_8822C 0 +#define BIT_MASK_DDMACH5_DA_8822C 0xffffffffL +#define BIT_DDMACH5_DA_8822C(x) \ + (((x) & BIT_MASK_DDMACH5_DA_8822C) << BIT_SHIFT_DDMACH5_DA_8822C) +#define BITS_DDMACH5_DA_8822C \ + (BIT_MASK_DDMACH5_DA_8822C << BIT_SHIFT_DDMACH5_DA_8822C) +#define BIT_CLEAR_DDMACH5_DA_8822C(x) ((x) & (~BITS_DDMACH5_DA_8822C)) +#define BIT_GET_DDMACH5_DA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DA_8822C) & BIT_MASK_DDMACH5_DA_8822C) +#define BIT_SET_DDMACH5_DA_8822C(x, v) \ + (BIT_CLEAR_DDMACH5_DA_8822C(x) | BIT_DDMACH5_DA_8822C(v)) + +/* 2 REG_DDMA_CH5CTRL_8822C */ +#define BIT_DDMACH5_OWN_8822C BIT(31) +#define BIT_DDMACH5_IDMEM_ERR_8822C BIT(30) +#define BIT_DDMACH5_CHKSUM_EN_8822C BIT(29) +#define BIT_DDMACH5_DA_W_DISABLE_8822C BIT(28) +#define BIT_DDMACH5_CHKSUM_STS_8822C BIT(27) +#define BIT_DDMACH5_DDMA_MODE_8822C BIT(26) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_DDMACH5_DLEN_8822C 0 +#define BIT_MASK_DDMACH5_DLEN_8822C 0x3ffff +#define BIT_DDMACH5_DLEN_8822C(x) \ + (((x) & BIT_MASK_DDMACH5_DLEN_8822C) << BIT_SHIFT_DDMACH5_DLEN_8822C) +#define BITS_DDMACH5_DLEN_8822C \ + (BIT_MASK_DDMACH5_DLEN_8822C << BIT_SHIFT_DDMACH5_DLEN_8822C) +#define BIT_CLEAR_DDMACH5_DLEN_8822C(x) ((x) & (~BITS_DDMACH5_DLEN_8822C)) +#define BIT_GET_DDMACH5_DLEN_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DLEN_8822C) & BIT_MASK_DDMACH5_DLEN_8822C) +#define BIT_SET_DDMACH5_DLEN_8822C(x, v) \ + (BIT_CLEAR_DDMACH5_DLEN_8822C(x) | BIT_DDMACH5_DLEN_8822C(v)) + +/* 2 REG_DDMA_INT_MSK_8822C */ +#define BIT_DDMACH5_MSK_8822C BIT(5) +#define BIT_DDMACH4_MSK_8822C BIT(4) +#define BIT_DDMACH3_MSK_8822C BIT(3) +#define BIT_DDMACH2_MSK_8822C BIT(2) +#define BIT_DDMACH1_MSK_8822C BIT(1) +#define BIT_DDMACH0_MSK_8822C BIT(0) + +/* 2 REG_DDMA_CHSTATUS_8822C */ +#define BIT_DDMACH5_BUSY_8822C BIT(5) +#define BIT_DDMACH4_BUSY_8822C BIT(4) +#define BIT_DDMACH3_BUSY_8822C BIT(3) +#define BIT_DDMACH2_BUSY_8822C BIT(2) +#define BIT_DDMACH1_BUSY_8822C BIT(1) +#define BIT_DDMACH0_BUSY_8822C BIT(0) + +/* 2 REG_DDMA_CHKSUM_8822C */ + +#define BIT_SHIFT_IDDMA0_CHKSUM_8822C 0 +#define BIT_MASK_IDDMA0_CHKSUM_8822C 0xffff +#define BIT_IDDMA0_CHKSUM_8822C(x) \ + (((x) & BIT_MASK_IDDMA0_CHKSUM_8822C) << BIT_SHIFT_IDDMA0_CHKSUM_8822C) +#define BITS_IDDMA0_CHKSUM_8822C \ + (BIT_MASK_IDDMA0_CHKSUM_8822C << BIT_SHIFT_IDDMA0_CHKSUM_8822C) +#define BIT_CLEAR_IDDMA0_CHKSUM_8822C(x) ((x) & (~BITS_IDDMA0_CHKSUM_8822C)) +#define BIT_GET_IDDMA0_CHKSUM_8822C(x) \ + (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822C) & BIT_MASK_IDDMA0_CHKSUM_8822C) +#define BIT_SET_IDDMA0_CHKSUM_8822C(x, v) \ + (BIT_CLEAR_IDDMA0_CHKSUM_8822C(x) | BIT_IDDMA0_CHKSUM_8822C(v)) + +/* 2 REG_DDMA_MONITOR_8822C */ +#define BIT_IDDMA0_PERMU_UNDERFLOW_8822C BIT(14) +#define BIT_IDDMA0_FIFO_UNDERFLOW_8822C BIT(13) +#define BIT_IDDMA0_FIFO_OVERFLOW_8822C BIT(12) +#define BIT_CH5_ERR_8822C BIT(5) +#define BIT_CH4_ERR_8822C BIT(4) +#define BIT_CH3_ERR_8822C BIT(3) +#define BIT_CH2_ERR_8822C BIT(2) +#define BIT_CH1_ERR_8822C BIT(1) +#define BIT_CH0_ERR_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_PCIE_CTRL_8822C */ +#define BIT_PCIEIO_PERSTB_SEL_8822C BIT(31) + +#define BIT_SHIFT_PCIE_MAX_RXDMA_8822C 28 +#define BIT_MASK_PCIE_MAX_RXDMA_8822C 0x7 +#define BIT_PCIE_MAX_RXDMA_8822C(x) \ + (((x) & BIT_MASK_PCIE_MAX_RXDMA_8822C) \ + << BIT_SHIFT_PCIE_MAX_RXDMA_8822C) +#define BITS_PCIE_MAX_RXDMA_8822C \ + (BIT_MASK_PCIE_MAX_RXDMA_8822C << BIT_SHIFT_PCIE_MAX_RXDMA_8822C) +#define BIT_CLEAR_PCIE_MAX_RXDMA_8822C(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8822C)) +#define BIT_GET_PCIE_MAX_RXDMA_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822C) & \ + BIT_MASK_PCIE_MAX_RXDMA_8822C) +#define BIT_SET_PCIE_MAX_RXDMA_8822C(x, v) \ + (BIT_CLEAR_PCIE_MAX_RXDMA_8822C(x) | BIT_PCIE_MAX_RXDMA_8822C(v)) + +#define BIT_SHIFT_PCIE_MAX_TXDMA_8822C 24 +#define BIT_MASK_PCIE_MAX_TXDMA_8822C 0x7 +#define BIT_PCIE_MAX_TXDMA_8822C(x) \ + (((x) & BIT_MASK_PCIE_MAX_TXDMA_8822C) \ + << BIT_SHIFT_PCIE_MAX_TXDMA_8822C) +#define BITS_PCIE_MAX_TXDMA_8822C \ + (BIT_MASK_PCIE_MAX_TXDMA_8822C << BIT_SHIFT_PCIE_MAX_TXDMA_8822C) +#define BIT_CLEAR_PCIE_MAX_TXDMA_8822C(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8822C)) +#define BIT_GET_PCIE_MAX_TXDMA_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822C) & \ + BIT_MASK_PCIE_MAX_TXDMA_8822C) +#define BIT_SET_PCIE_MAX_TXDMA_8822C(x, v) \ + (BIT_CLEAR_PCIE_MAX_TXDMA_8822C(x) | BIT_PCIE_MAX_TXDMA_8822C(v)) + +#define BIT_EN_CPL_TIMEOUT_PS_8822C BIT(22) +#define BIT_REG_TXDMA_FAIL_PS_8822C BIT(21) +#define BIT_PCIE_RST_TRXDMA_INTF_8822C BIT(20) +#define BIT_EN_HWENTR_L1_8822C BIT(19) +#define BIT_EN_ADV_CLKGATE_8822C BIT(18) +#define BIT_PCIE_EN_SWENT_L23_8822C BIT(17) +#define BIT_PCIE_EN_HWEXT_L1_8822C BIT(16) +#define BIT_RX_CLOSE_EN_8822C BIT(15) +#define BIT_STOP_BCNQ_8822C BIT(14) +#define BIT_STOP_MGQ_8822C BIT(13) +#define BIT_STOP_VOQ_8822C BIT(12) +#define BIT_STOP_VIQ_8822C BIT(11) +#define BIT_STOP_BEQ_8822C BIT(10) +#define BIT_STOP_BKQ_8822C BIT(9) +#define BIT_STOP_RXQ_8822C BIT(8) +#define BIT_STOP_HI7Q_8822C BIT(7) +#define BIT_STOP_HI6Q_8822C BIT(6) +#define BIT_STOP_HI5Q_8822C BIT(5) +#define BIT_STOP_HI4Q_8822C BIT(4) +#define BIT_STOP_HI3Q_8822C BIT(3) +#define BIT_STOP_HI2Q_8822C BIT(2) +#define BIT_STOP_HI1Q_8822C BIT(1) +#define BIT_STOP_HI0Q_8822C BIT(0) + +/* 2 REG_INT_MIG_8822C */ + +#define BIT_SHIFT_TRXCOUNTER_MATCH_8822C 24 +#define BIT_MASK_TRXCOUNTER_MATCH_8822C 0xff +#define BIT_TRXCOUNTER_MATCH_8822C(x) \ + (((x) & BIT_MASK_TRXCOUNTER_MATCH_8822C) \ + << BIT_SHIFT_TRXCOUNTER_MATCH_8822C) +#define BITS_TRXCOUNTER_MATCH_8822C \ + (BIT_MASK_TRXCOUNTER_MATCH_8822C << BIT_SHIFT_TRXCOUNTER_MATCH_8822C) +#define BIT_CLEAR_TRXCOUNTER_MATCH_8822C(x) \ + ((x) & (~BITS_TRXCOUNTER_MATCH_8822C)) +#define BIT_GET_TRXCOUNTER_MATCH_8822C(x) \ + (((x) >> BIT_SHIFT_TRXCOUNTER_MATCH_8822C) & \ + BIT_MASK_TRXCOUNTER_MATCH_8822C) +#define BIT_SET_TRXCOUNTER_MATCH_8822C(x, v) \ + (BIT_CLEAR_TRXCOUNTER_MATCH_8822C(x) | BIT_TRXCOUNTER_MATCH_8822C(v)) + +#define BIT_SHIFT_TRXTIMER_MATCH_8822C 16 +#define BIT_MASK_TRXTIMER_MATCH_8822C 0xff +#define BIT_TRXTIMER_MATCH_8822C(x) \ + (((x) & BIT_MASK_TRXTIMER_MATCH_8822C) \ + << BIT_SHIFT_TRXTIMER_MATCH_8822C) +#define BITS_TRXTIMER_MATCH_8822C \ + (BIT_MASK_TRXTIMER_MATCH_8822C << BIT_SHIFT_TRXTIMER_MATCH_8822C) +#define BIT_CLEAR_TRXTIMER_MATCH_8822C(x) ((x) & (~BITS_TRXTIMER_MATCH_8822C)) +#define BIT_GET_TRXTIMER_MATCH_8822C(x) \ + (((x) >> BIT_SHIFT_TRXTIMER_MATCH_8822C) & \ + BIT_MASK_TRXTIMER_MATCH_8822C) +#define BIT_SET_TRXTIMER_MATCH_8822C(x, v) \ + (BIT_CLEAR_TRXTIMER_MATCH_8822C(x) | BIT_TRXTIMER_MATCH_8822C(v)) + +#define BIT_SHIFT_TRXTIMER_UNIT_8822C 0 +#define BIT_MASK_TRXTIMER_UNIT_8822C 0x3 +#define BIT_TRXTIMER_UNIT_8822C(x) \ + (((x) & BIT_MASK_TRXTIMER_UNIT_8822C) << BIT_SHIFT_TRXTIMER_UNIT_8822C) +#define BITS_TRXTIMER_UNIT_8822C \ + (BIT_MASK_TRXTIMER_UNIT_8822C << BIT_SHIFT_TRXTIMER_UNIT_8822C) +#define BIT_CLEAR_TRXTIMER_UNIT_8822C(x) ((x) & (~BITS_TRXTIMER_UNIT_8822C)) +#define BIT_GET_TRXTIMER_UNIT_8822C(x) \ + (((x) >> BIT_SHIFT_TRXTIMER_UNIT_8822C) & BIT_MASK_TRXTIMER_UNIT_8822C) +#define BIT_SET_TRXTIMER_UNIT_8822C(x, v) \ + (BIT_CLEAR_TRXTIMER_UNIT_8822C(x) | BIT_TRXTIMER_UNIT_8822C(v)) + +/* 2 REG_BCNQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_BCNQ_TXBD_DESA_8822C 0 +#define BIT_MASK_BCNQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_BCNQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_BCNQ_TXBD_DESA_8822C) \ + << BIT_SHIFT_BCNQ_TXBD_DESA_8822C) +#define BITS_BCNQ_TXBD_DESA_8822C \ + (BIT_MASK_BCNQ_TXBD_DESA_8822C << BIT_SHIFT_BCNQ_TXBD_DESA_8822C) +#define BIT_CLEAR_BCNQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8822C)) +#define BIT_GET_BCNQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822C) & \ + BIT_MASK_BCNQ_TXBD_DESA_8822C) +#define BIT_SET_BCNQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_BCNQ_TXBD_DESA_8822C(x) | BIT_BCNQ_TXBD_DESA_8822C(v)) + +/* 2 REG_MGQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_MGQ_TXBD_DESA_8822C 0 +#define BIT_MASK_MGQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_MGQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_MGQ_TXBD_DESA_8822C) << BIT_SHIFT_MGQ_TXBD_DESA_8822C) +#define BITS_MGQ_TXBD_DESA_8822C \ + (BIT_MASK_MGQ_TXBD_DESA_8822C << BIT_SHIFT_MGQ_TXBD_DESA_8822C) +#define BIT_CLEAR_MGQ_TXBD_DESA_8822C(x) ((x) & (~BITS_MGQ_TXBD_DESA_8822C)) +#define BIT_GET_MGQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822C) & BIT_MASK_MGQ_TXBD_DESA_8822C) +#define BIT_SET_MGQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_MGQ_TXBD_DESA_8822C(x) | BIT_MGQ_TXBD_DESA_8822C(v)) + +/* 2 REG_VOQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_VOQ_TXBD_DESA_8822C 0 +#define BIT_MASK_VOQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_VOQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_VOQ_TXBD_DESA_8822C) << BIT_SHIFT_VOQ_TXBD_DESA_8822C) +#define BITS_VOQ_TXBD_DESA_8822C \ + (BIT_MASK_VOQ_TXBD_DESA_8822C << BIT_SHIFT_VOQ_TXBD_DESA_8822C) +#define BIT_CLEAR_VOQ_TXBD_DESA_8822C(x) ((x) & (~BITS_VOQ_TXBD_DESA_8822C)) +#define BIT_GET_VOQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822C) & BIT_MASK_VOQ_TXBD_DESA_8822C) +#define BIT_SET_VOQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_VOQ_TXBD_DESA_8822C(x) | BIT_VOQ_TXBD_DESA_8822C(v)) + +/* 2 REG_VIQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_VIQ_TXBD_DESA_8822C 0 +#define BIT_MASK_VIQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_VIQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_VIQ_TXBD_DESA_8822C) << BIT_SHIFT_VIQ_TXBD_DESA_8822C) +#define BITS_VIQ_TXBD_DESA_8822C \ + (BIT_MASK_VIQ_TXBD_DESA_8822C << BIT_SHIFT_VIQ_TXBD_DESA_8822C) +#define BIT_CLEAR_VIQ_TXBD_DESA_8822C(x) ((x) & (~BITS_VIQ_TXBD_DESA_8822C)) +#define BIT_GET_VIQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822C) & BIT_MASK_VIQ_TXBD_DESA_8822C) +#define BIT_SET_VIQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_VIQ_TXBD_DESA_8822C(x) | BIT_VIQ_TXBD_DESA_8822C(v)) + +/* 2 REG_BEQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_BEQ_TXBD_DESA_8822C 0 +#define BIT_MASK_BEQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_BEQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_BEQ_TXBD_DESA_8822C) << BIT_SHIFT_BEQ_TXBD_DESA_8822C) +#define BITS_BEQ_TXBD_DESA_8822C \ + (BIT_MASK_BEQ_TXBD_DESA_8822C << BIT_SHIFT_BEQ_TXBD_DESA_8822C) +#define BIT_CLEAR_BEQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BEQ_TXBD_DESA_8822C)) +#define BIT_GET_BEQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822C) & BIT_MASK_BEQ_TXBD_DESA_8822C) +#define BIT_SET_BEQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_BEQ_TXBD_DESA_8822C(x) | BIT_BEQ_TXBD_DESA_8822C(v)) + +/* 2 REG_BKQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_BKQ_TXBD_DESA_8822C 0 +#define BIT_MASK_BKQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_BKQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_BKQ_TXBD_DESA_8822C) << BIT_SHIFT_BKQ_TXBD_DESA_8822C) +#define BITS_BKQ_TXBD_DESA_8822C \ + (BIT_MASK_BKQ_TXBD_DESA_8822C << BIT_SHIFT_BKQ_TXBD_DESA_8822C) +#define BIT_CLEAR_BKQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BKQ_TXBD_DESA_8822C)) +#define BIT_GET_BKQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822C) & BIT_MASK_BKQ_TXBD_DESA_8822C) +#define BIT_SET_BKQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_BKQ_TXBD_DESA_8822C(x) | BIT_BKQ_TXBD_DESA_8822C(v)) + +/* 2 REG_RXQ_RXBD_DESA_8822C */ + +#define BIT_SHIFT_RXQ_RXBD_DESA_8822C 0 +#define BIT_MASK_RXQ_RXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_RXQ_RXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_RXQ_RXBD_DESA_8822C) << BIT_SHIFT_RXQ_RXBD_DESA_8822C) +#define BITS_RXQ_RXBD_DESA_8822C \ + (BIT_MASK_RXQ_RXBD_DESA_8822C << BIT_SHIFT_RXQ_RXBD_DESA_8822C) +#define BIT_CLEAR_RXQ_RXBD_DESA_8822C(x) ((x) & (~BITS_RXQ_RXBD_DESA_8822C)) +#define BIT_GET_RXQ_RXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822C) & BIT_MASK_RXQ_RXBD_DESA_8822C) +#define BIT_SET_RXQ_RXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_RXQ_RXBD_DESA_8822C(x) | BIT_RXQ_RXBD_DESA_8822C(v)) + +/* 2 REG_HI0Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI0Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI0Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI0Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI0Q_TXBD_DESA_8822C) +#define BITS_HI0Q_TXBD_DESA_8822C \ + (BIT_MASK_HI0Q_TXBD_DESA_8822C << BIT_SHIFT_HI0Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI0Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8822C)) +#define BIT_GET_HI0Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI0Q_TXBD_DESA_8822C) +#define BIT_SET_HI0Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_8822C(x) | BIT_HI0Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI1Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI1Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI1Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI1Q_TXBD_DESA_8822C) +#define BITS_HI1Q_TXBD_DESA_8822C \ + (BIT_MASK_HI1Q_TXBD_DESA_8822C << BIT_SHIFT_HI1Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI1Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8822C)) +#define BIT_GET_HI1Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI1Q_TXBD_DESA_8822C) +#define BIT_SET_HI1Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_8822C(x) | BIT_HI1Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI2Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI2Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI2Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI2Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI2Q_TXBD_DESA_8822C) +#define BITS_HI2Q_TXBD_DESA_8822C \ + (BIT_MASK_HI2Q_TXBD_DESA_8822C << BIT_SHIFT_HI2Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI2Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8822C)) +#define BIT_GET_HI2Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI2Q_TXBD_DESA_8822C) +#define BIT_SET_HI2Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_8822C(x) | BIT_HI2Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI3Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI3Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI3Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI3Q_TXBD_DESA_8822C) +#define BITS_HI3Q_TXBD_DESA_8822C \ + (BIT_MASK_HI3Q_TXBD_DESA_8822C << BIT_SHIFT_HI3Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI3Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8822C)) +#define BIT_GET_HI3Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI3Q_TXBD_DESA_8822C) +#define BIT_SET_HI3Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_8822C(x) | BIT_HI3Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI4Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI4Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI4Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI4Q_TXBD_DESA_8822C) +#define BITS_HI4Q_TXBD_DESA_8822C \ + (BIT_MASK_HI4Q_TXBD_DESA_8822C << BIT_SHIFT_HI4Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI4Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8822C)) +#define BIT_GET_HI4Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI4Q_TXBD_DESA_8822C) +#define BIT_SET_HI4Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_8822C(x) | BIT_HI4Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI5Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI5Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI5Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI5Q_TXBD_DESA_8822C) +#define BITS_HI5Q_TXBD_DESA_8822C \ + (BIT_MASK_HI5Q_TXBD_DESA_8822C << BIT_SHIFT_HI5Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI5Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8822C)) +#define BIT_GET_HI5Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI5Q_TXBD_DESA_8822C) +#define BIT_SET_HI5Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_8822C(x) | BIT_HI5Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI6Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI6Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI6Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI6Q_TXBD_DESA_8822C) +#define BITS_HI6Q_TXBD_DESA_8822C \ + (BIT_MASK_HI6Q_TXBD_DESA_8822C << BIT_SHIFT_HI6Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI6Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8822C)) +#define BIT_GET_HI6Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI6Q_TXBD_DESA_8822C) +#define BIT_SET_HI6Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_8822C(x) | BIT_HI6Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI7Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI7Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI7Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI7Q_TXBD_DESA_8822C) +#define BITS_HI7Q_TXBD_DESA_8822C \ + (BIT_MASK_HI7Q_TXBD_DESA_8822C << BIT_SHIFT_HI7Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI7Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8822C)) +#define BIT_GET_HI7Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI7Q_TXBD_DESA_8822C) +#define BIT_SET_HI7Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_8822C(x) | BIT_HI7Q_TXBD_DESA_8822C(v)) + +/* 2 REG_MGQ_TXBD_NUM_8822C */ +#define BIT_PCIE_MGQ_FLAG_8822C BIT(14) + +#define BIT_SHIFT_MGQ_DESC_MODE_8822C 12 +#define BIT_MASK_MGQ_DESC_MODE_8822C 0x3 +#define BIT_MGQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_MGQ_DESC_MODE_8822C) << BIT_SHIFT_MGQ_DESC_MODE_8822C) +#define BITS_MGQ_DESC_MODE_8822C \ + (BIT_MASK_MGQ_DESC_MODE_8822C << BIT_SHIFT_MGQ_DESC_MODE_8822C) +#define BIT_CLEAR_MGQ_DESC_MODE_8822C(x) ((x) & (~BITS_MGQ_DESC_MODE_8822C)) +#define BIT_GET_MGQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822C) & BIT_MASK_MGQ_DESC_MODE_8822C) +#define BIT_SET_MGQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_MGQ_DESC_MODE_8822C(x) | BIT_MGQ_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_MGQ_DESC_NUM_8822C 0 +#define BIT_MASK_MGQ_DESC_NUM_8822C 0xfff +#define BIT_MGQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_MGQ_DESC_NUM_8822C) << BIT_SHIFT_MGQ_DESC_NUM_8822C) +#define BITS_MGQ_DESC_NUM_8822C \ + (BIT_MASK_MGQ_DESC_NUM_8822C << BIT_SHIFT_MGQ_DESC_NUM_8822C) +#define BIT_CLEAR_MGQ_DESC_NUM_8822C(x) ((x) & (~BITS_MGQ_DESC_NUM_8822C)) +#define BIT_GET_MGQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822C) & BIT_MASK_MGQ_DESC_NUM_8822C) +#define BIT_SET_MGQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_MGQ_DESC_NUM_8822C(x) | BIT_MGQ_DESC_NUM_8822C(v)) + +/* 2 REG_RX_RXBD_NUM_8822C */ +#define BIT_SYS_32_64_8822C BIT(15) + +#define BIT_SHIFT_BCNQ_DESC_MODE_8822C 13 +#define BIT_MASK_BCNQ_DESC_MODE_8822C 0x3 +#define BIT_BCNQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_BCNQ_DESC_MODE_8822C) \ + << BIT_SHIFT_BCNQ_DESC_MODE_8822C) +#define BITS_BCNQ_DESC_MODE_8822C \ + (BIT_MASK_BCNQ_DESC_MODE_8822C << BIT_SHIFT_BCNQ_DESC_MODE_8822C) +#define BIT_CLEAR_BCNQ_DESC_MODE_8822C(x) ((x) & (~BITS_BCNQ_DESC_MODE_8822C)) +#define BIT_GET_BCNQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822C) & \ + BIT_MASK_BCNQ_DESC_MODE_8822C) +#define BIT_SET_BCNQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_BCNQ_DESC_MODE_8822C(x) | BIT_BCNQ_DESC_MODE_8822C(v)) + +#define BIT_PCIE_BCNQ_FLAG_8822C BIT(12) + +#define BIT_SHIFT_RXQ_DESC_NUM_8822C 0 +#define BIT_MASK_RXQ_DESC_NUM_8822C 0xfff +#define BIT_RXQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_RXQ_DESC_NUM_8822C) << BIT_SHIFT_RXQ_DESC_NUM_8822C) +#define BITS_RXQ_DESC_NUM_8822C \ + (BIT_MASK_RXQ_DESC_NUM_8822C << BIT_SHIFT_RXQ_DESC_NUM_8822C) +#define BIT_CLEAR_RXQ_DESC_NUM_8822C(x) ((x) & (~BITS_RXQ_DESC_NUM_8822C)) +#define BIT_GET_RXQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822C) & BIT_MASK_RXQ_DESC_NUM_8822C) +#define BIT_SET_RXQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_RXQ_DESC_NUM_8822C(x) | BIT_RXQ_DESC_NUM_8822C(v)) + +/* 2 REG_VOQ_TXBD_NUM_8822C */ +#define BIT_PCIE_VOQ_FLAG_8822C BIT(14) + +#define BIT_SHIFT_VOQ_DESC_MODE_8822C 12 +#define BIT_MASK_VOQ_DESC_MODE_8822C 0x3 +#define BIT_VOQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_VOQ_DESC_MODE_8822C) << BIT_SHIFT_VOQ_DESC_MODE_8822C) +#define BITS_VOQ_DESC_MODE_8822C \ + (BIT_MASK_VOQ_DESC_MODE_8822C << BIT_SHIFT_VOQ_DESC_MODE_8822C) +#define BIT_CLEAR_VOQ_DESC_MODE_8822C(x) ((x) & (~BITS_VOQ_DESC_MODE_8822C)) +#define BIT_GET_VOQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822C) & BIT_MASK_VOQ_DESC_MODE_8822C) +#define BIT_SET_VOQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_VOQ_DESC_MODE_8822C(x) | BIT_VOQ_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_VOQ_DESC_NUM_8822C 0 +#define BIT_MASK_VOQ_DESC_NUM_8822C 0xfff +#define BIT_VOQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_VOQ_DESC_NUM_8822C) << BIT_SHIFT_VOQ_DESC_NUM_8822C) +#define BITS_VOQ_DESC_NUM_8822C \ + (BIT_MASK_VOQ_DESC_NUM_8822C << BIT_SHIFT_VOQ_DESC_NUM_8822C) +#define BIT_CLEAR_VOQ_DESC_NUM_8822C(x) ((x) & (~BITS_VOQ_DESC_NUM_8822C)) +#define BIT_GET_VOQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822C) & BIT_MASK_VOQ_DESC_NUM_8822C) +#define BIT_SET_VOQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_VOQ_DESC_NUM_8822C(x) | BIT_VOQ_DESC_NUM_8822C(v)) + +/* 2 REG_VIQ_TXBD_NUM_8822C */ +#define BIT_PCIE_VIQ_FLAG_8822C BIT(14) + +#define BIT_SHIFT_VIQ_DESC_MODE_8822C 12 +#define BIT_MASK_VIQ_DESC_MODE_8822C 0x3 +#define BIT_VIQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_VIQ_DESC_MODE_8822C) << BIT_SHIFT_VIQ_DESC_MODE_8822C) +#define BITS_VIQ_DESC_MODE_8822C \ + (BIT_MASK_VIQ_DESC_MODE_8822C << BIT_SHIFT_VIQ_DESC_MODE_8822C) +#define BIT_CLEAR_VIQ_DESC_MODE_8822C(x) ((x) & (~BITS_VIQ_DESC_MODE_8822C)) +#define BIT_GET_VIQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822C) & BIT_MASK_VIQ_DESC_MODE_8822C) +#define BIT_SET_VIQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_VIQ_DESC_MODE_8822C(x) | BIT_VIQ_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_VIQ_DESC_NUM_8822C 0 +#define BIT_MASK_VIQ_DESC_NUM_8822C 0xfff +#define BIT_VIQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_VIQ_DESC_NUM_8822C) << BIT_SHIFT_VIQ_DESC_NUM_8822C) +#define BITS_VIQ_DESC_NUM_8822C \ + (BIT_MASK_VIQ_DESC_NUM_8822C << BIT_SHIFT_VIQ_DESC_NUM_8822C) +#define BIT_CLEAR_VIQ_DESC_NUM_8822C(x) ((x) & (~BITS_VIQ_DESC_NUM_8822C)) +#define BIT_GET_VIQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822C) & BIT_MASK_VIQ_DESC_NUM_8822C) +#define BIT_SET_VIQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_VIQ_DESC_NUM_8822C(x) | BIT_VIQ_DESC_NUM_8822C(v)) + +/* 2 REG_BEQ_TXBD_NUM_8822C */ +#define BIT_PCIE_BEQ_FLAG_8822C BIT(14) + +#define BIT_SHIFT_BEQ_DESC_MODE_8822C 12 +#define BIT_MASK_BEQ_DESC_MODE_8822C 0x3 +#define BIT_BEQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_BEQ_DESC_MODE_8822C) << BIT_SHIFT_BEQ_DESC_MODE_8822C) +#define BITS_BEQ_DESC_MODE_8822C \ + (BIT_MASK_BEQ_DESC_MODE_8822C << BIT_SHIFT_BEQ_DESC_MODE_8822C) +#define BIT_CLEAR_BEQ_DESC_MODE_8822C(x) ((x) & (~BITS_BEQ_DESC_MODE_8822C)) +#define BIT_GET_BEQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822C) & BIT_MASK_BEQ_DESC_MODE_8822C) +#define BIT_SET_BEQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_BEQ_DESC_MODE_8822C(x) | BIT_BEQ_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_BEQ_DESC_NUM_8822C 0 +#define BIT_MASK_BEQ_DESC_NUM_8822C 0xfff +#define BIT_BEQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_BEQ_DESC_NUM_8822C) << BIT_SHIFT_BEQ_DESC_NUM_8822C) +#define BITS_BEQ_DESC_NUM_8822C \ + (BIT_MASK_BEQ_DESC_NUM_8822C << BIT_SHIFT_BEQ_DESC_NUM_8822C) +#define BIT_CLEAR_BEQ_DESC_NUM_8822C(x) ((x) & (~BITS_BEQ_DESC_NUM_8822C)) +#define BIT_GET_BEQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822C) & BIT_MASK_BEQ_DESC_NUM_8822C) +#define BIT_SET_BEQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_BEQ_DESC_NUM_8822C(x) | BIT_BEQ_DESC_NUM_8822C(v)) + +/* 2 REG_BKQ_TXBD_NUM_8822C */ +#define BIT_PCIE_BKQ_FLAG_8822C BIT(14) + +#define BIT_SHIFT_BKQ_DESC_MODE_8822C 12 +#define BIT_MASK_BKQ_DESC_MODE_8822C 0x3 +#define BIT_BKQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_BKQ_DESC_MODE_8822C) << BIT_SHIFT_BKQ_DESC_MODE_8822C) +#define BITS_BKQ_DESC_MODE_8822C \ + (BIT_MASK_BKQ_DESC_MODE_8822C << BIT_SHIFT_BKQ_DESC_MODE_8822C) +#define BIT_CLEAR_BKQ_DESC_MODE_8822C(x) ((x) & (~BITS_BKQ_DESC_MODE_8822C)) +#define BIT_GET_BKQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822C) & BIT_MASK_BKQ_DESC_MODE_8822C) +#define BIT_SET_BKQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_BKQ_DESC_MODE_8822C(x) | BIT_BKQ_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_BKQ_DESC_NUM_8822C 0 +#define BIT_MASK_BKQ_DESC_NUM_8822C 0xfff +#define BIT_BKQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_BKQ_DESC_NUM_8822C) << BIT_SHIFT_BKQ_DESC_NUM_8822C) +#define BITS_BKQ_DESC_NUM_8822C \ + (BIT_MASK_BKQ_DESC_NUM_8822C << BIT_SHIFT_BKQ_DESC_NUM_8822C) +#define BIT_CLEAR_BKQ_DESC_NUM_8822C(x) ((x) & (~BITS_BKQ_DESC_NUM_8822C)) +#define BIT_GET_BKQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822C) & BIT_MASK_BKQ_DESC_NUM_8822C) +#define BIT_SET_BKQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_BKQ_DESC_NUM_8822C(x) | BIT_BKQ_DESC_NUM_8822C(v)) + +/* 2 REG_HI0Q_TXBD_NUM_8822C */ +#define BIT_HI0Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI0Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI0Q_DESC_MODE_8822C 0x3 +#define BIT_HI0Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI0Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI0Q_DESC_MODE_8822C) +#define BITS_HI0Q_DESC_MODE_8822C \ + (BIT_MASK_HI0Q_DESC_MODE_8822C << BIT_SHIFT_HI0Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI0Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI0Q_DESC_MODE_8822C)) +#define BIT_GET_HI0Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822C) & \ + BIT_MASK_HI0Q_DESC_MODE_8822C) +#define BIT_SET_HI0Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI0Q_DESC_MODE_8822C(x) | BIT_HI0Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI0Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI0Q_DESC_NUM_8822C 0xfff +#define BIT_HI0Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI0Q_DESC_NUM_8822C) << BIT_SHIFT_HI0Q_DESC_NUM_8822C) +#define BITS_HI0Q_DESC_NUM_8822C \ + (BIT_MASK_HI0Q_DESC_NUM_8822C << BIT_SHIFT_HI0Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI0Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI0Q_DESC_NUM_8822C)) +#define BIT_GET_HI0Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822C) & BIT_MASK_HI0Q_DESC_NUM_8822C) +#define BIT_SET_HI0Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI0Q_DESC_NUM_8822C(x) | BIT_HI0Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI1Q_TXBD_NUM_8822C */ +#define BIT_HI1Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI1Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI1Q_DESC_MODE_8822C 0x3 +#define BIT_HI1Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI1Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI1Q_DESC_MODE_8822C) +#define BITS_HI1Q_DESC_MODE_8822C \ + (BIT_MASK_HI1Q_DESC_MODE_8822C << BIT_SHIFT_HI1Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI1Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI1Q_DESC_MODE_8822C)) +#define BIT_GET_HI1Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822C) & \ + BIT_MASK_HI1Q_DESC_MODE_8822C) +#define BIT_SET_HI1Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI1Q_DESC_MODE_8822C(x) | BIT_HI1Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI1Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI1Q_DESC_NUM_8822C 0xfff +#define BIT_HI1Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI1Q_DESC_NUM_8822C) << BIT_SHIFT_HI1Q_DESC_NUM_8822C) +#define BITS_HI1Q_DESC_NUM_8822C \ + (BIT_MASK_HI1Q_DESC_NUM_8822C << BIT_SHIFT_HI1Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI1Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI1Q_DESC_NUM_8822C)) +#define BIT_GET_HI1Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822C) & BIT_MASK_HI1Q_DESC_NUM_8822C) +#define BIT_SET_HI1Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI1Q_DESC_NUM_8822C(x) | BIT_HI1Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI2Q_TXBD_NUM_8822C */ +#define BIT_HI2Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI2Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI2Q_DESC_MODE_8822C 0x3 +#define BIT_HI2Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI2Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI2Q_DESC_MODE_8822C) +#define BITS_HI2Q_DESC_MODE_8822C \ + (BIT_MASK_HI2Q_DESC_MODE_8822C << BIT_SHIFT_HI2Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI2Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI2Q_DESC_MODE_8822C)) +#define BIT_GET_HI2Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822C) & \ + BIT_MASK_HI2Q_DESC_MODE_8822C) +#define BIT_SET_HI2Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI2Q_DESC_MODE_8822C(x) | BIT_HI2Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI2Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI2Q_DESC_NUM_8822C 0xfff +#define BIT_HI2Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI2Q_DESC_NUM_8822C) << BIT_SHIFT_HI2Q_DESC_NUM_8822C) +#define BITS_HI2Q_DESC_NUM_8822C \ + (BIT_MASK_HI2Q_DESC_NUM_8822C << BIT_SHIFT_HI2Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI2Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI2Q_DESC_NUM_8822C)) +#define BIT_GET_HI2Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822C) & BIT_MASK_HI2Q_DESC_NUM_8822C) +#define BIT_SET_HI2Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI2Q_DESC_NUM_8822C(x) | BIT_HI2Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI3Q_TXBD_NUM_8822C */ +#define BIT_HI3Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI3Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI3Q_DESC_MODE_8822C 0x3 +#define BIT_HI3Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI3Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI3Q_DESC_MODE_8822C) +#define BITS_HI3Q_DESC_MODE_8822C \ + (BIT_MASK_HI3Q_DESC_MODE_8822C << BIT_SHIFT_HI3Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI3Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI3Q_DESC_MODE_8822C)) +#define BIT_GET_HI3Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822C) & \ + BIT_MASK_HI3Q_DESC_MODE_8822C) +#define BIT_SET_HI3Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI3Q_DESC_MODE_8822C(x) | BIT_HI3Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI3Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI3Q_DESC_NUM_8822C 0xfff +#define BIT_HI3Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI3Q_DESC_NUM_8822C) << BIT_SHIFT_HI3Q_DESC_NUM_8822C) +#define BITS_HI3Q_DESC_NUM_8822C \ + (BIT_MASK_HI3Q_DESC_NUM_8822C << BIT_SHIFT_HI3Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI3Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI3Q_DESC_NUM_8822C)) +#define BIT_GET_HI3Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822C) & BIT_MASK_HI3Q_DESC_NUM_8822C) +#define BIT_SET_HI3Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI3Q_DESC_NUM_8822C(x) | BIT_HI3Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI4Q_TXBD_NUM_8822C */ +#define BIT_HI4Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI4Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI4Q_DESC_MODE_8822C 0x3 +#define BIT_HI4Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI4Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI4Q_DESC_MODE_8822C) +#define BITS_HI4Q_DESC_MODE_8822C \ + (BIT_MASK_HI4Q_DESC_MODE_8822C << BIT_SHIFT_HI4Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI4Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI4Q_DESC_MODE_8822C)) +#define BIT_GET_HI4Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822C) & \ + BIT_MASK_HI4Q_DESC_MODE_8822C) +#define BIT_SET_HI4Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI4Q_DESC_MODE_8822C(x) | BIT_HI4Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI4Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI4Q_DESC_NUM_8822C 0xfff +#define BIT_HI4Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI4Q_DESC_NUM_8822C) << BIT_SHIFT_HI4Q_DESC_NUM_8822C) +#define BITS_HI4Q_DESC_NUM_8822C \ + (BIT_MASK_HI4Q_DESC_NUM_8822C << BIT_SHIFT_HI4Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI4Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI4Q_DESC_NUM_8822C)) +#define BIT_GET_HI4Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822C) & BIT_MASK_HI4Q_DESC_NUM_8822C) +#define BIT_SET_HI4Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI4Q_DESC_NUM_8822C(x) | BIT_HI4Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI5Q_TXBD_NUM_8822C */ +#define BIT_HI5Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI5Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI5Q_DESC_MODE_8822C 0x3 +#define BIT_HI5Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI5Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI5Q_DESC_MODE_8822C) +#define BITS_HI5Q_DESC_MODE_8822C \ + (BIT_MASK_HI5Q_DESC_MODE_8822C << BIT_SHIFT_HI5Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI5Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI5Q_DESC_MODE_8822C)) +#define BIT_GET_HI5Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822C) & \ + BIT_MASK_HI5Q_DESC_MODE_8822C) +#define BIT_SET_HI5Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI5Q_DESC_MODE_8822C(x) | BIT_HI5Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI5Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI5Q_DESC_NUM_8822C 0xfff +#define BIT_HI5Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI5Q_DESC_NUM_8822C) << BIT_SHIFT_HI5Q_DESC_NUM_8822C) +#define BITS_HI5Q_DESC_NUM_8822C \ + (BIT_MASK_HI5Q_DESC_NUM_8822C << BIT_SHIFT_HI5Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI5Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI5Q_DESC_NUM_8822C)) +#define BIT_GET_HI5Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822C) & BIT_MASK_HI5Q_DESC_NUM_8822C) +#define BIT_SET_HI5Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI5Q_DESC_NUM_8822C(x) | BIT_HI5Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI6Q_TXBD_NUM_8822C */ +#define BIT_HI6Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI6Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI6Q_DESC_MODE_8822C 0x3 +#define BIT_HI6Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI6Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI6Q_DESC_MODE_8822C) +#define BITS_HI6Q_DESC_MODE_8822C \ + (BIT_MASK_HI6Q_DESC_MODE_8822C << BIT_SHIFT_HI6Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI6Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI6Q_DESC_MODE_8822C)) +#define BIT_GET_HI6Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822C) & \ + BIT_MASK_HI6Q_DESC_MODE_8822C) +#define BIT_SET_HI6Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI6Q_DESC_MODE_8822C(x) | BIT_HI6Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI6Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI6Q_DESC_NUM_8822C 0xfff +#define BIT_HI6Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI6Q_DESC_NUM_8822C) << BIT_SHIFT_HI6Q_DESC_NUM_8822C) +#define BITS_HI6Q_DESC_NUM_8822C \ + (BIT_MASK_HI6Q_DESC_NUM_8822C << BIT_SHIFT_HI6Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI6Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI6Q_DESC_NUM_8822C)) +#define BIT_GET_HI6Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822C) & BIT_MASK_HI6Q_DESC_NUM_8822C) +#define BIT_SET_HI6Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI6Q_DESC_NUM_8822C(x) | BIT_HI6Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI7Q_TXBD_NUM_8822C */ +#define BIT_HI7Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI7Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI7Q_DESC_MODE_8822C 0x3 +#define BIT_HI7Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI7Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI7Q_DESC_MODE_8822C) +#define BITS_HI7Q_DESC_MODE_8822C \ + (BIT_MASK_HI7Q_DESC_MODE_8822C << BIT_SHIFT_HI7Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI7Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI7Q_DESC_MODE_8822C)) +#define BIT_GET_HI7Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822C) & \ + BIT_MASK_HI7Q_DESC_MODE_8822C) +#define BIT_SET_HI7Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI7Q_DESC_MODE_8822C(x) | BIT_HI7Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI7Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI7Q_DESC_NUM_8822C 0xfff +#define BIT_HI7Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI7Q_DESC_NUM_8822C) << BIT_SHIFT_HI7Q_DESC_NUM_8822C) +#define BITS_HI7Q_DESC_NUM_8822C \ + (BIT_MASK_HI7Q_DESC_NUM_8822C << BIT_SHIFT_HI7Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI7Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI7Q_DESC_NUM_8822C)) +#define BIT_GET_HI7Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822C) & BIT_MASK_HI7Q_DESC_NUM_8822C) +#define BIT_SET_HI7Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI7Q_DESC_NUM_8822C(x) | BIT_HI7Q_DESC_NUM_8822C(v)) + +/* 2 REG_TSFTIMER_HCI_8822C */ + +#define BIT_SHIFT_TSFT2_HCI_8822C 16 +#define BIT_MASK_TSFT2_HCI_8822C 0xffff +#define BIT_TSFT2_HCI_8822C(x) \ + (((x) & BIT_MASK_TSFT2_HCI_8822C) << BIT_SHIFT_TSFT2_HCI_8822C) +#define BITS_TSFT2_HCI_8822C \ + (BIT_MASK_TSFT2_HCI_8822C << BIT_SHIFT_TSFT2_HCI_8822C) +#define BIT_CLEAR_TSFT2_HCI_8822C(x) ((x) & (~BITS_TSFT2_HCI_8822C)) +#define BIT_GET_TSFT2_HCI_8822C(x) \ + (((x) >> BIT_SHIFT_TSFT2_HCI_8822C) & BIT_MASK_TSFT2_HCI_8822C) +#define BIT_SET_TSFT2_HCI_8822C(x, v) \ + (BIT_CLEAR_TSFT2_HCI_8822C(x) | BIT_TSFT2_HCI_8822C(v)) + +#define BIT_SHIFT_TSFT1_HCI_8822C 0 +#define BIT_MASK_TSFT1_HCI_8822C 0xffff +#define BIT_TSFT1_HCI_8822C(x) \ + (((x) & BIT_MASK_TSFT1_HCI_8822C) << BIT_SHIFT_TSFT1_HCI_8822C) +#define BITS_TSFT1_HCI_8822C \ + (BIT_MASK_TSFT1_HCI_8822C << BIT_SHIFT_TSFT1_HCI_8822C) +#define BIT_CLEAR_TSFT1_HCI_8822C(x) ((x) & (~BITS_TSFT1_HCI_8822C)) +#define BIT_GET_TSFT1_HCI_8822C(x) \ + (((x) >> BIT_SHIFT_TSFT1_HCI_8822C) & BIT_MASK_TSFT1_HCI_8822C) +#define BIT_SET_TSFT1_HCI_8822C(x, v) \ + (BIT_CLEAR_TSFT1_HCI_8822C(x) | BIT_TSFT1_HCI_8822C(v)) + +/* 2 REG_BD_RWPTR_CLR_8822C */ +#define BIT_CLR_HI7Q_HW_IDX_8822C BIT(29) +#define BIT_CLR_HI6Q_HW_IDX_8822C BIT(28) +#define BIT_CLR_HI5Q_HW_IDX_8822C BIT(27) +#define BIT_CLR_HI4Q_HW_IDX_8822C BIT(26) +#define BIT_CLR_HI3Q_HW_IDX_8822C BIT(25) +#define BIT_CLR_HI2Q_HW_IDX_8822C BIT(24) +#define BIT_CLR_HI1Q_HW_IDX_8822C BIT(23) +#define BIT_CLR_HI0Q_HW_IDX_8822C BIT(22) +#define BIT_CLR_BKQ_HW_IDX_8822C BIT(21) +#define BIT_CLR_BEQ_HW_IDX_8822C BIT(20) +#define BIT_CLR_VIQ_HW_IDX_8822C BIT(19) +#define BIT_CLR_VOQ_HW_IDX_8822C BIT(18) +#define BIT_CLR_MGQ_HW_IDX_8822C BIT(17) +#define BIT_CLR_RXQ_HW_IDX_8822C BIT(16) +#define BIT_CLR_HI7Q_HOST_IDX_8822C BIT(13) +#define BIT_CLR_HI6Q_HOST_IDX_8822C BIT(12) +#define BIT_CLR_HI5Q_HOST_IDX_8822C BIT(11) +#define BIT_CLR_HI4Q_HOST_IDX_8822C BIT(10) +#define BIT_CLR_HI3Q_HOST_IDX_8822C BIT(9) +#define BIT_CLR_HI2Q_HOST_IDX_8822C BIT(8) +#define BIT_CLR_HI1Q_HOST_IDX_8822C BIT(7) +#define BIT_CLR_HI0Q_HOST_IDX_8822C BIT(6) +#define BIT_CLR_BKQ_HOST_IDX_8822C BIT(5) +#define BIT_CLR_BEQ_HOST_IDX_8822C BIT(4) +#define BIT_CLR_VIQ_HOST_IDX_8822C BIT(3) +#define BIT_CLR_VOQ_HOST_IDX_8822C BIT(2) +#define BIT_CLR_MGQ_HOST_IDX_8822C BIT(1) +#define BIT_CLR_RXQ_HOST_IDX_8822C BIT(0) + +/* 2 REG_VOQ_TXBD_IDX_8822C */ + +#define BIT_SHIFT_VOQ_HW_IDX_8822C 16 +#define BIT_MASK_VOQ_HW_IDX_8822C 0xfff +#define BIT_VOQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_VOQ_HW_IDX_8822C) << BIT_SHIFT_VOQ_HW_IDX_8822C) +#define BITS_VOQ_HW_IDX_8822C \ + (BIT_MASK_VOQ_HW_IDX_8822C << BIT_SHIFT_VOQ_HW_IDX_8822C) +#define BIT_CLEAR_VOQ_HW_IDX_8822C(x) ((x) & (~BITS_VOQ_HW_IDX_8822C)) +#define BIT_GET_VOQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_VOQ_HW_IDX_8822C) & BIT_MASK_VOQ_HW_IDX_8822C) +#define BIT_SET_VOQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_VOQ_HW_IDX_8822C(x) | BIT_VOQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_VOQ_HOST_IDX_8822C 0 +#define BIT_MASK_VOQ_HOST_IDX_8822C 0xfff +#define BIT_VOQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_VOQ_HOST_IDX_8822C) << BIT_SHIFT_VOQ_HOST_IDX_8822C) +#define BITS_VOQ_HOST_IDX_8822C \ + (BIT_MASK_VOQ_HOST_IDX_8822C << BIT_SHIFT_VOQ_HOST_IDX_8822C) +#define BIT_CLEAR_VOQ_HOST_IDX_8822C(x) ((x) & (~BITS_VOQ_HOST_IDX_8822C)) +#define BIT_GET_VOQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822C) & BIT_MASK_VOQ_HOST_IDX_8822C) +#define BIT_SET_VOQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_VOQ_HOST_IDX_8822C(x) | BIT_VOQ_HOST_IDX_8822C(v)) + +/* 2 REG_VIQ_TXBD_IDX_8822C */ + +#define BIT_SHIFT_VIQ_HW_IDX_8822C 16 +#define BIT_MASK_VIQ_HW_IDX_8822C 0xfff +#define BIT_VIQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_VIQ_HW_IDX_8822C) << BIT_SHIFT_VIQ_HW_IDX_8822C) +#define BITS_VIQ_HW_IDX_8822C \ + (BIT_MASK_VIQ_HW_IDX_8822C << BIT_SHIFT_VIQ_HW_IDX_8822C) +#define BIT_CLEAR_VIQ_HW_IDX_8822C(x) ((x) & (~BITS_VIQ_HW_IDX_8822C)) +#define BIT_GET_VIQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_VIQ_HW_IDX_8822C) & BIT_MASK_VIQ_HW_IDX_8822C) +#define BIT_SET_VIQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_VIQ_HW_IDX_8822C(x) | BIT_VIQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_VIQ_HOST_IDX_8822C 0 +#define BIT_MASK_VIQ_HOST_IDX_8822C 0xfff +#define BIT_VIQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_VIQ_HOST_IDX_8822C) << BIT_SHIFT_VIQ_HOST_IDX_8822C) +#define BITS_VIQ_HOST_IDX_8822C \ + (BIT_MASK_VIQ_HOST_IDX_8822C << BIT_SHIFT_VIQ_HOST_IDX_8822C) +#define BIT_CLEAR_VIQ_HOST_IDX_8822C(x) ((x) & (~BITS_VIQ_HOST_IDX_8822C)) +#define BIT_GET_VIQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822C) & BIT_MASK_VIQ_HOST_IDX_8822C) +#define BIT_SET_VIQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_VIQ_HOST_IDX_8822C(x) | BIT_VIQ_HOST_IDX_8822C(v)) + +/* 2 REG_BEQ_TXBD_IDX_8822C */ + +#define BIT_SHIFT_BEQ_HW_IDX_8822C 16 +#define BIT_MASK_BEQ_HW_IDX_8822C 0xfff +#define BIT_BEQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_BEQ_HW_IDX_8822C) << BIT_SHIFT_BEQ_HW_IDX_8822C) +#define BITS_BEQ_HW_IDX_8822C \ + (BIT_MASK_BEQ_HW_IDX_8822C << BIT_SHIFT_BEQ_HW_IDX_8822C) +#define BIT_CLEAR_BEQ_HW_IDX_8822C(x) ((x) & (~BITS_BEQ_HW_IDX_8822C)) +#define BIT_GET_BEQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_BEQ_HW_IDX_8822C) & BIT_MASK_BEQ_HW_IDX_8822C) +#define BIT_SET_BEQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_BEQ_HW_IDX_8822C(x) | BIT_BEQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_BEQ_HOST_IDX_8822C 0 +#define BIT_MASK_BEQ_HOST_IDX_8822C 0xfff +#define BIT_BEQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_BEQ_HOST_IDX_8822C) << BIT_SHIFT_BEQ_HOST_IDX_8822C) +#define BITS_BEQ_HOST_IDX_8822C \ + (BIT_MASK_BEQ_HOST_IDX_8822C << BIT_SHIFT_BEQ_HOST_IDX_8822C) +#define BIT_CLEAR_BEQ_HOST_IDX_8822C(x) ((x) & (~BITS_BEQ_HOST_IDX_8822C)) +#define BIT_GET_BEQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822C) & BIT_MASK_BEQ_HOST_IDX_8822C) +#define BIT_SET_BEQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_BEQ_HOST_IDX_8822C(x) | BIT_BEQ_HOST_IDX_8822C(v)) + +/* 2 REG_BKQ_TXBD_IDX_8822C */ + +#define BIT_SHIFT_BKQ_HW_IDX_8822C 16 +#define BIT_MASK_BKQ_HW_IDX_8822C 0xfff +#define BIT_BKQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_BKQ_HW_IDX_8822C) << BIT_SHIFT_BKQ_HW_IDX_8822C) +#define BITS_BKQ_HW_IDX_8822C \ + (BIT_MASK_BKQ_HW_IDX_8822C << BIT_SHIFT_BKQ_HW_IDX_8822C) +#define BIT_CLEAR_BKQ_HW_IDX_8822C(x) ((x) & (~BITS_BKQ_HW_IDX_8822C)) +#define BIT_GET_BKQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_BKQ_HW_IDX_8822C) & BIT_MASK_BKQ_HW_IDX_8822C) +#define BIT_SET_BKQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_BKQ_HW_IDX_8822C(x) | BIT_BKQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_BKQ_HOST_IDX_8822C 0 +#define BIT_MASK_BKQ_HOST_IDX_8822C 0xfff +#define BIT_BKQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_BKQ_HOST_IDX_8822C) << BIT_SHIFT_BKQ_HOST_IDX_8822C) +#define BITS_BKQ_HOST_IDX_8822C \ + (BIT_MASK_BKQ_HOST_IDX_8822C << BIT_SHIFT_BKQ_HOST_IDX_8822C) +#define BIT_CLEAR_BKQ_HOST_IDX_8822C(x) ((x) & (~BITS_BKQ_HOST_IDX_8822C)) +#define BIT_GET_BKQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822C) & BIT_MASK_BKQ_HOST_IDX_8822C) +#define BIT_SET_BKQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_BKQ_HOST_IDX_8822C(x) | BIT_BKQ_HOST_IDX_8822C(v)) + +/* 2 REG_MGQ_TXBD_IDX_8822C */ + +#define BIT_SHIFT_MGQ_HW_IDX_8822C 16 +#define BIT_MASK_MGQ_HW_IDX_8822C 0xfff +#define BIT_MGQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_MGQ_HW_IDX_8822C) << BIT_SHIFT_MGQ_HW_IDX_8822C) +#define BITS_MGQ_HW_IDX_8822C \ + (BIT_MASK_MGQ_HW_IDX_8822C << BIT_SHIFT_MGQ_HW_IDX_8822C) +#define BIT_CLEAR_MGQ_HW_IDX_8822C(x) ((x) & (~BITS_MGQ_HW_IDX_8822C)) +#define BIT_GET_MGQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_HW_IDX_8822C) & BIT_MASK_MGQ_HW_IDX_8822C) +#define BIT_SET_MGQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_MGQ_HW_IDX_8822C(x) | BIT_MGQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_MGQ_HOST_IDX_8822C 0 +#define BIT_MASK_MGQ_HOST_IDX_8822C 0xfff +#define BIT_MGQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_MGQ_HOST_IDX_8822C) << BIT_SHIFT_MGQ_HOST_IDX_8822C) +#define BITS_MGQ_HOST_IDX_8822C \ + (BIT_MASK_MGQ_HOST_IDX_8822C << BIT_SHIFT_MGQ_HOST_IDX_8822C) +#define BIT_CLEAR_MGQ_HOST_IDX_8822C(x) ((x) & (~BITS_MGQ_HOST_IDX_8822C)) +#define BIT_GET_MGQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822C) & BIT_MASK_MGQ_HOST_IDX_8822C) +#define BIT_SET_MGQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_MGQ_HOST_IDX_8822C(x) | BIT_MGQ_HOST_IDX_8822C(v)) + +/* 2 REG_RXQ_RXBD_IDX_8822C */ + +#define BIT_SHIFT_RXQ_HW_IDX_8822C 16 +#define BIT_MASK_RXQ_HW_IDX_8822C 0xfff +#define BIT_RXQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_RXQ_HW_IDX_8822C) << BIT_SHIFT_RXQ_HW_IDX_8822C) +#define BITS_RXQ_HW_IDX_8822C \ + (BIT_MASK_RXQ_HW_IDX_8822C << BIT_SHIFT_RXQ_HW_IDX_8822C) +#define BIT_CLEAR_RXQ_HW_IDX_8822C(x) ((x) & (~BITS_RXQ_HW_IDX_8822C)) +#define BIT_GET_RXQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RXQ_HW_IDX_8822C) & BIT_MASK_RXQ_HW_IDX_8822C) +#define BIT_SET_RXQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_RXQ_HW_IDX_8822C(x) | BIT_RXQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_RXQ_HOST_IDX_8822C 0 +#define BIT_MASK_RXQ_HOST_IDX_8822C 0xfff +#define BIT_RXQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_RXQ_HOST_IDX_8822C) << BIT_SHIFT_RXQ_HOST_IDX_8822C) +#define BITS_RXQ_HOST_IDX_8822C \ + (BIT_MASK_RXQ_HOST_IDX_8822C << BIT_SHIFT_RXQ_HOST_IDX_8822C) +#define BIT_CLEAR_RXQ_HOST_IDX_8822C(x) ((x) & (~BITS_RXQ_HOST_IDX_8822C)) +#define BIT_GET_RXQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822C) & BIT_MASK_RXQ_HOST_IDX_8822C) +#define BIT_SET_RXQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_RXQ_HOST_IDX_8822C(x) | BIT_RXQ_HOST_IDX_8822C(v)) + +/* 2 REG_HI0Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI0Q_HW_IDX_8822C 16 +#define BIT_MASK_HI0Q_HW_IDX_8822C 0xfff +#define BIT_HI0Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI0Q_HW_IDX_8822C) << BIT_SHIFT_HI0Q_HW_IDX_8822C) +#define BITS_HI0Q_HW_IDX_8822C \ + (BIT_MASK_HI0Q_HW_IDX_8822C << BIT_SHIFT_HI0Q_HW_IDX_8822C) +#define BIT_CLEAR_HI0Q_HW_IDX_8822C(x) ((x) & (~BITS_HI0Q_HW_IDX_8822C)) +#define BIT_GET_HI0Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822C) & BIT_MASK_HI0Q_HW_IDX_8822C) +#define BIT_SET_HI0Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI0Q_HW_IDX_8822C(x) | BIT_HI0Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI0Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI0Q_HOST_IDX_8822C 0xfff +#define BIT_HI0Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI0Q_HOST_IDX_8822C) << BIT_SHIFT_HI0Q_HOST_IDX_8822C) +#define BITS_HI0Q_HOST_IDX_8822C \ + (BIT_MASK_HI0Q_HOST_IDX_8822C << BIT_SHIFT_HI0Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI0Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI0Q_HOST_IDX_8822C)) +#define BIT_GET_HI0Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822C) & BIT_MASK_HI0Q_HOST_IDX_8822C) +#define BIT_SET_HI0Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI0Q_HOST_IDX_8822C(x) | BIT_HI0Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI1Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI1Q_HW_IDX_8822C 16 +#define BIT_MASK_HI1Q_HW_IDX_8822C 0xfff +#define BIT_HI1Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI1Q_HW_IDX_8822C) << BIT_SHIFT_HI1Q_HW_IDX_8822C) +#define BITS_HI1Q_HW_IDX_8822C \ + (BIT_MASK_HI1Q_HW_IDX_8822C << BIT_SHIFT_HI1Q_HW_IDX_8822C) +#define BIT_CLEAR_HI1Q_HW_IDX_8822C(x) ((x) & (~BITS_HI1Q_HW_IDX_8822C)) +#define BIT_GET_HI1Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822C) & BIT_MASK_HI1Q_HW_IDX_8822C) +#define BIT_SET_HI1Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI1Q_HW_IDX_8822C(x) | BIT_HI1Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI1Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI1Q_HOST_IDX_8822C 0xfff +#define BIT_HI1Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI1Q_HOST_IDX_8822C) << BIT_SHIFT_HI1Q_HOST_IDX_8822C) +#define BITS_HI1Q_HOST_IDX_8822C \ + (BIT_MASK_HI1Q_HOST_IDX_8822C << BIT_SHIFT_HI1Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI1Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI1Q_HOST_IDX_8822C)) +#define BIT_GET_HI1Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822C) & BIT_MASK_HI1Q_HOST_IDX_8822C) +#define BIT_SET_HI1Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI1Q_HOST_IDX_8822C(x) | BIT_HI1Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI2Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI2Q_HW_IDX_8822C 16 +#define BIT_MASK_HI2Q_HW_IDX_8822C 0xfff +#define BIT_HI2Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI2Q_HW_IDX_8822C) << BIT_SHIFT_HI2Q_HW_IDX_8822C) +#define BITS_HI2Q_HW_IDX_8822C \ + (BIT_MASK_HI2Q_HW_IDX_8822C << BIT_SHIFT_HI2Q_HW_IDX_8822C) +#define BIT_CLEAR_HI2Q_HW_IDX_8822C(x) ((x) & (~BITS_HI2Q_HW_IDX_8822C)) +#define BIT_GET_HI2Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822C) & BIT_MASK_HI2Q_HW_IDX_8822C) +#define BIT_SET_HI2Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI2Q_HW_IDX_8822C(x) | BIT_HI2Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI2Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI2Q_HOST_IDX_8822C 0xfff +#define BIT_HI2Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI2Q_HOST_IDX_8822C) << BIT_SHIFT_HI2Q_HOST_IDX_8822C) +#define BITS_HI2Q_HOST_IDX_8822C \ + (BIT_MASK_HI2Q_HOST_IDX_8822C << BIT_SHIFT_HI2Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI2Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI2Q_HOST_IDX_8822C)) +#define BIT_GET_HI2Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822C) & BIT_MASK_HI2Q_HOST_IDX_8822C) +#define BIT_SET_HI2Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI2Q_HOST_IDX_8822C(x) | BIT_HI2Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI3Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI3Q_HW_IDX_8822C 16 +#define BIT_MASK_HI3Q_HW_IDX_8822C 0xfff +#define BIT_HI3Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI3Q_HW_IDX_8822C) << BIT_SHIFT_HI3Q_HW_IDX_8822C) +#define BITS_HI3Q_HW_IDX_8822C \ + (BIT_MASK_HI3Q_HW_IDX_8822C << BIT_SHIFT_HI3Q_HW_IDX_8822C) +#define BIT_CLEAR_HI3Q_HW_IDX_8822C(x) ((x) & (~BITS_HI3Q_HW_IDX_8822C)) +#define BIT_GET_HI3Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822C) & BIT_MASK_HI3Q_HW_IDX_8822C) +#define BIT_SET_HI3Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI3Q_HW_IDX_8822C(x) | BIT_HI3Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI3Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI3Q_HOST_IDX_8822C 0xfff +#define BIT_HI3Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI3Q_HOST_IDX_8822C) << BIT_SHIFT_HI3Q_HOST_IDX_8822C) +#define BITS_HI3Q_HOST_IDX_8822C \ + (BIT_MASK_HI3Q_HOST_IDX_8822C << BIT_SHIFT_HI3Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI3Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI3Q_HOST_IDX_8822C)) +#define BIT_GET_HI3Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822C) & BIT_MASK_HI3Q_HOST_IDX_8822C) +#define BIT_SET_HI3Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI3Q_HOST_IDX_8822C(x) | BIT_HI3Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI4Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI4Q_HW_IDX_8822C 16 +#define BIT_MASK_HI4Q_HW_IDX_8822C 0xfff +#define BIT_HI4Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI4Q_HW_IDX_8822C) << BIT_SHIFT_HI4Q_HW_IDX_8822C) +#define BITS_HI4Q_HW_IDX_8822C \ + (BIT_MASK_HI4Q_HW_IDX_8822C << BIT_SHIFT_HI4Q_HW_IDX_8822C) +#define BIT_CLEAR_HI4Q_HW_IDX_8822C(x) ((x) & (~BITS_HI4Q_HW_IDX_8822C)) +#define BIT_GET_HI4Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822C) & BIT_MASK_HI4Q_HW_IDX_8822C) +#define BIT_SET_HI4Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI4Q_HW_IDX_8822C(x) | BIT_HI4Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI4Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI4Q_HOST_IDX_8822C 0xfff +#define BIT_HI4Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI4Q_HOST_IDX_8822C) << BIT_SHIFT_HI4Q_HOST_IDX_8822C) +#define BITS_HI4Q_HOST_IDX_8822C \ + (BIT_MASK_HI4Q_HOST_IDX_8822C << BIT_SHIFT_HI4Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI4Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI4Q_HOST_IDX_8822C)) +#define BIT_GET_HI4Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822C) & BIT_MASK_HI4Q_HOST_IDX_8822C) +#define BIT_SET_HI4Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI4Q_HOST_IDX_8822C(x) | BIT_HI4Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI5Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI5Q_HW_IDX_8822C 16 +#define BIT_MASK_HI5Q_HW_IDX_8822C 0xfff +#define BIT_HI5Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI5Q_HW_IDX_8822C) << BIT_SHIFT_HI5Q_HW_IDX_8822C) +#define BITS_HI5Q_HW_IDX_8822C \ + (BIT_MASK_HI5Q_HW_IDX_8822C << BIT_SHIFT_HI5Q_HW_IDX_8822C) +#define BIT_CLEAR_HI5Q_HW_IDX_8822C(x) ((x) & (~BITS_HI5Q_HW_IDX_8822C)) +#define BIT_GET_HI5Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822C) & BIT_MASK_HI5Q_HW_IDX_8822C) +#define BIT_SET_HI5Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI5Q_HW_IDX_8822C(x) | BIT_HI5Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI5Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI5Q_HOST_IDX_8822C 0xfff +#define BIT_HI5Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI5Q_HOST_IDX_8822C) << BIT_SHIFT_HI5Q_HOST_IDX_8822C) +#define BITS_HI5Q_HOST_IDX_8822C \ + (BIT_MASK_HI5Q_HOST_IDX_8822C << BIT_SHIFT_HI5Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI5Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI5Q_HOST_IDX_8822C)) +#define BIT_GET_HI5Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822C) & BIT_MASK_HI5Q_HOST_IDX_8822C) +#define BIT_SET_HI5Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI5Q_HOST_IDX_8822C(x) | BIT_HI5Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI6Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI6Q_HW_IDX_8822C 16 +#define BIT_MASK_HI6Q_HW_IDX_8822C 0xfff +#define BIT_HI6Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI6Q_HW_IDX_8822C) << BIT_SHIFT_HI6Q_HW_IDX_8822C) +#define BITS_HI6Q_HW_IDX_8822C \ + (BIT_MASK_HI6Q_HW_IDX_8822C << BIT_SHIFT_HI6Q_HW_IDX_8822C) +#define BIT_CLEAR_HI6Q_HW_IDX_8822C(x) ((x) & (~BITS_HI6Q_HW_IDX_8822C)) +#define BIT_GET_HI6Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822C) & BIT_MASK_HI6Q_HW_IDX_8822C) +#define BIT_SET_HI6Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI6Q_HW_IDX_8822C(x) | BIT_HI6Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI6Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI6Q_HOST_IDX_8822C 0xfff +#define BIT_HI6Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI6Q_HOST_IDX_8822C) << BIT_SHIFT_HI6Q_HOST_IDX_8822C) +#define BITS_HI6Q_HOST_IDX_8822C \ + (BIT_MASK_HI6Q_HOST_IDX_8822C << BIT_SHIFT_HI6Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI6Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI6Q_HOST_IDX_8822C)) +#define BIT_GET_HI6Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822C) & BIT_MASK_HI6Q_HOST_IDX_8822C) +#define BIT_SET_HI6Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI6Q_HOST_IDX_8822C(x) | BIT_HI6Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI7Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI7Q_HW_IDX_8822C 16 +#define BIT_MASK_HI7Q_HW_IDX_8822C 0xfff +#define BIT_HI7Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI7Q_HW_IDX_8822C) << BIT_SHIFT_HI7Q_HW_IDX_8822C) +#define BITS_HI7Q_HW_IDX_8822C \ + (BIT_MASK_HI7Q_HW_IDX_8822C << BIT_SHIFT_HI7Q_HW_IDX_8822C) +#define BIT_CLEAR_HI7Q_HW_IDX_8822C(x) ((x) & (~BITS_HI7Q_HW_IDX_8822C)) +#define BIT_GET_HI7Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822C) & BIT_MASK_HI7Q_HW_IDX_8822C) +#define BIT_SET_HI7Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI7Q_HW_IDX_8822C(x) | BIT_HI7Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI7Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI7Q_HOST_IDX_8822C 0xfff +#define BIT_HI7Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI7Q_HOST_IDX_8822C) << BIT_SHIFT_HI7Q_HOST_IDX_8822C) +#define BITS_HI7Q_HOST_IDX_8822C \ + (BIT_MASK_HI7Q_HOST_IDX_8822C << BIT_SHIFT_HI7Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI7Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI7Q_HOST_IDX_8822C)) +#define BIT_GET_HI7Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822C) & BIT_MASK_HI7Q_HOST_IDX_8822C) +#define BIT_SET_HI7Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI7Q_HOST_IDX_8822C(x) | BIT_HI7Q_HOST_IDX_8822C(v)) + +/* 2 REG_DBG_SEL_V1_8822C */ + +#define BIT_SHIFT_DBG_SEL_8822C 0 +#define BIT_MASK_DBG_SEL_8822C 0xff +#define BIT_DBG_SEL_8822C(x) \ + (((x) & BIT_MASK_DBG_SEL_8822C) << BIT_SHIFT_DBG_SEL_8822C) +#define BITS_DBG_SEL_8822C (BIT_MASK_DBG_SEL_8822C << BIT_SHIFT_DBG_SEL_8822C) +#define BIT_CLEAR_DBG_SEL_8822C(x) ((x) & (~BITS_DBG_SEL_8822C)) +#define BIT_GET_DBG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_8822C) & BIT_MASK_DBG_SEL_8822C) +#define BIT_SET_DBG_SEL_8822C(x, v) \ + (BIT_CLEAR_DBG_SEL_8822C(x) | BIT_DBG_SEL_8822C(v)) + +/* 2 REG_PCIE_HRPWM1_V1_8822C */ + +#define BIT_SHIFT_PCIE_HRPWM_8822C 0 +#define BIT_MASK_PCIE_HRPWM_8822C 0xff +#define BIT_PCIE_HRPWM_8822C(x) \ + (((x) & BIT_MASK_PCIE_HRPWM_8822C) << BIT_SHIFT_PCIE_HRPWM_8822C) +#define BITS_PCIE_HRPWM_8822C \ + (BIT_MASK_PCIE_HRPWM_8822C << BIT_SHIFT_PCIE_HRPWM_8822C) +#define BIT_CLEAR_PCIE_HRPWM_8822C(x) ((x) & (~BITS_PCIE_HRPWM_8822C)) +#define BIT_GET_PCIE_HRPWM_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM_8822C) & BIT_MASK_PCIE_HRPWM_8822C) +#define BIT_SET_PCIE_HRPWM_8822C(x, v) \ + (BIT_CLEAR_PCIE_HRPWM_8822C(x) | BIT_PCIE_HRPWM_8822C(v)) + +/* 2 REG_PCIE_HCPWM1_V1_8822C */ + +#define BIT_SHIFT_PCIE_HCPWM_8822C 0 +#define BIT_MASK_PCIE_HCPWM_8822C 0xff +#define BIT_PCIE_HCPWM_8822C(x) \ + (((x) & BIT_MASK_PCIE_HCPWM_8822C) << BIT_SHIFT_PCIE_HCPWM_8822C) +#define BITS_PCIE_HCPWM_8822C \ + (BIT_MASK_PCIE_HCPWM_8822C << BIT_SHIFT_PCIE_HCPWM_8822C) +#define BIT_CLEAR_PCIE_HCPWM_8822C(x) ((x) & (~BITS_PCIE_HCPWM_8822C)) +#define BIT_GET_PCIE_HCPWM_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM_8822C) & BIT_MASK_PCIE_HCPWM_8822C) +#define BIT_SET_PCIE_HCPWM_8822C(x, v) \ + (BIT_CLEAR_PCIE_HCPWM_8822C(x) | BIT_PCIE_HCPWM_8822C(v)) + +/* 2 REG_PCIE_CTRL2_8822C */ +#define BIT_DIS_TXDMA_PRE_8822C BIT(7) +#define BIT_DIS_RXDMA_PRE_8822C BIT(6) + +#define BIT_SHIFT_HPS_CLKR_PCIE_8822C 4 +#define BIT_MASK_HPS_CLKR_PCIE_8822C 0x3 +#define BIT_HPS_CLKR_PCIE_8822C(x) \ + (((x) & BIT_MASK_HPS_CLKR_PCIE_8822C) << BIT_SHIFT_HPS_CLKR_PCIE_8822C) +#define BITS_HPS_CLKR_PCIE_8822C \ + (BIT_MASK_HPS_CLKR_PCIE_8822C << BIT_SHIFT_HPS_CLKR_PCIE_8822C) +#define BIT_CLEAR_HPS_CLKR_PCIE_8822C(x) ((x) & (~BITS_HPS_CLKR_PCIE_8822C)) +#define BIT_GET_HPS_CLKR_PCIE_8822C(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822C) & BIT_MASK_HPS_CLKR_PCIE_8822C) +#define BIT_SET_HPS_CLKR_PCIE_8822C(x, v) \ + (BIT_CLEAR_HPS_CLKR_PCIE_8822C(x) | BIT_HPS_CLKR_PCIE_8822C(v)) + +#define BIT_PCIE_INT_8822C BIT(3) +#define BIT_TXFLAG_EXIT_L1_EN_8822C BIT(2) +#define BIT_EN_RXDMA_ALIGN_8822C BIT(1) +#define BIT_EN_TXDMA_ALIGN_8822C BIT(0) + +/* 2 REG_PCIE_HRPWM2_V1_8822C */ + +#define BIT_SHIFT_PCIE_HRPWM2_8822C 0 +#define BIT_MASK_PCIE_HRPWM2_8822C 0xffff +#define BIT_PCIE_HRPWM2_8822C(x) \ + (((x) & BIT_MASK_PCIE_HRPWM2_8822C) << BIT_SHIFT_PCIE_HRPWM2_8822C) +#define BITS_PCIE_HRPWM2_8822C \ + (BIT_MASK_PCIE_HRPWM2_8822C << BIT_SHIFT_PCIE_HRPWM2_8822C) +#define BIT_CLEAR_PCIE_HRPWM2_8822C(x) ((x) & (~BITS_PCIE_HRPWM2_8822C)) +#define BIT_GET_PCIE_HRPWM2_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM2_8822C) & BIT_MASK_PCIE_HRPWM2_8822C) +#define BIT_SET_PCIE_HRPWM2_8822C(x, v) \ + (BIT_CLEAR_PCIE_HRPWM2_8822C(x) | BIT_PCIE_HRPWM2_8822C(v)) + +/* 2 REG_PCIE_HCPWM2_V1_8822C */ + +#define BIT_SHIFT_PCIE_HCPWM2_8822C 0 +#define BIT_MASK_PCIE_HCPWM2_8822C 0xffff +#define BIT_PCIE_HCPWM2_8822C(x) \ + (((x) & BIT_MASK_PCIE_HCPWM2_8822C) << BIT_SHIFT_PCIE_HCPWM2_8822C) +#define BITS_PCIE_HCPWM2_8822C \ + (BIT_MASK_PCIE_HCPWM2_8822C << BIT_SHIFT_PCIE_HCPWM2_8822C) +#define BIT_CLEAR_PCIE_HCPWM2_8822C(x) ((x) & (~BITS_PCIE_HCPWM2_8822C)) +#define BIT_GET_PCIE_HCPWM2_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM2_8822C) & BIT_MASK_PCIE_HCPWM2_8822C) +#define BIT_SET_PCIE_HCPWM2_8822C(x, v) \ + (BIT_CLEAR_PCIE_HCPWM2_8822C(x) | BIT_PCIE_HCPWM2_8822C(v)) + +/* 2 REG_PCIE_H2C_MSG_V1_8822C */ + +#define BIT_SHIFT_DRV2FW_INFO_8822C 0 +#define BIT_MASK_DRV2FW_INFO_8822C 0xffffffffL +#define BIT_DRV2FW_INFO_8822C(x) \ + (((x) & BIT_MASK_DRV2FW_INFO_8822C) << BIT_SHIFT_DRV2FW_INFO_8822C) +#define BITS_DRV2FW_INFO_8822C \ + (BIT_MASK_DRV2FW_INFO_8822C << BIT_SHIFT_DRV2FW_INFO_8822C) +#define BIT_CLEAR_DRV2FW_INFO_8822C(x) ((x) & (~BITS_DRV2FW_INFO_8822C)) +#define BIT_GET_DRV2FW_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_DRV2FW_INFO_8822C) & BIT_MASK_DRV2FW_INFO_8822C) +#define BIT_SET_DRV2FW_INFO_8822C(x, v) \ + (BIT_CLEAR_DRV2FW_INFO_8822C(x) | BIT_DRV2FW_INFO_8822C(v)) + +/* 2 REG_PCIE_C2H_MSG_V1_8822C */ + +#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C 0 +#define BIT_MASK_HCI_PCIE_C2H_MSG_8822C 0xffffffffL +#define BIT_HCI_PCIE_C2H_MSG_8822C(x) \ + (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822C) \ + << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C) +#define BITS_HCI_PCIE_C2H_MSG_8822C \ + (BIT_MASK_HCI_PCIE_C2H_MSG_8822C << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C) +#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8822C(x) \ + ((x) & (~BITS_HCI_PCIE_C2H_MSG_8822C)) +#define BIT_GET_HCI_PCIE_C2H_MSG_8822C(x) \ + (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C) & \ + BIT_MASK_HCI_PCIE_C2H_MSG_8822C) +#define BIT_SET_HCI_PCIE_C2H_MSG_8822C(x, v) \ + (BIT_CLEAR_HCI_PCIE_C2H_MSG_8822C(x) | BIT_HCI_PCIE_C2H_MSG_8822C(v)) + +/* 2 REG_DBI_WDATA_V1_8822C */ + +#define BIT_SHIFT_DBI_WDATA_8822C 0 +#define BIT_MASK_DBI_WDATA_8822C 0xffffffffL +#define BIT_DBI_WDATA_8822C(x) \ + (((x) & BIT_MASK_DBI_WDATA_8822C) << BIT_SHIFT_DBI_WDATA_8822C) +#define BITS_DBI_WDATA_8822C \ + (BIT_MASK_DBI_WDATA_8822C << BIT_SHIFT_DBI_WDATA_8822C) +#define BIT_CLEAR_DBI_WDATA_8822C(x) ((x) & (~BITS_DBI_WDATA_8822C)) +#define BIT_GET_DBI_WDATA_8822C(x) \ + (((x) >> BIT_SHIFT_DBI_WDATA_8822C) & BIT_MASK_DBI_WDATA_8822C) +#define BIT_SET_DBI_WDATA_8822C(x, v) \ + (BIT_CLEAR_DBI_WDATA_8822C(x) | BIT_DBI_WDATA_8822C(v)) + +/* 2 REG_DBI_RDATA_V1_8822C */ + +#define BIT_SHIFT_DBI_RDATA_8822C 0 +#define BIT_MASK_DBI_RDATA_8822C 0xffffffffL +#define BIT_DBI_RDATA_8822C(x) \ + (((x) & BIT_MASK_DBI_RDATA_8822C) << BIT_SHIFT_DBI_RDATA_8822C) +#define BITS_DBI_RDATA_8822C \ + (BIT_MASK_DBI_RDATA_8822C << BIT_SHIFT_DBI_RDATA_8822C) +#define BIT_CLEAR_DBI_RDATA_8822C(x) ((x) & (~BITS_DBI_RDATA_8822C)) +#define BIT_GET_DBI_RDATA_8822C(x) \ + (((x) >> BIT_SHIFT_DBI_RDATA_8822C) & BIT_MASK_DBI_RDATA_8822C) +#define BIT_SET_DBI_RDATA_8822C(x, v) \ + (BIT_CLEAR_DBI_RDATA_8822C(x) | BIT_DBI_RDATA_8822C(v)) + +/* 2 REG_DBI_FLAG_V1_8822C */ +#define BIT_EN_STUCK_DBG_8822C BIT(26) +#define BIT_RX_STUCK_8822C BIT(25) +#define BIT_TX_STUCK_8822C BIT(24) +#define BIT_DBI_RFLAG_8822C BIT(17) +#define BIT_DBI_WFLAG_8822C BIT(16) + +#define BIT_SHIFT_DBI_WREN_8822C 12 +#define BIT_MASK_DBI_WREN_8822C 0xf +#define BIT_DBI_WREN_8822C(x) \ + (((x) & BIT_MASK_DBI_WREN_8822C) << BIT_SHIFT_DBI_WREN_8822C) +#define BITS_DBI_WREN_8822C \ + (BIT_MASK_DBI_WREN_8822C << BIT_SHIFT_DBI_WREN_8822C) +#define BIT_CLEAR_DBI_WREN_8822C(x) ((x) & (~BITS_DBI_WREN_8822C)) +#define BIT_GET_DBI_WREN_8822C(x) \ + (((x) >> BIT_SHIFT_DBI_WREN_8822C) & BIT_MASK_DBI_WREN_8822C) +#define BIT_SET_DBI_WREN_8822C(x, v) \ + (BIT_CLEAR_DBI_WREN_8822C(x) | BIT_DBI_WREN_8822C(v)) + +#define BIT_SHIFT_DBI_ADDR_8822C 0 +#define BIT_MASK_DBI_ADDR_8822C 0xfff +#define BIT_DBI_ADDR_8822C(x) \ + (((x) & BIT_MASK_DBI_ADDR_8822C) << BIT_SHIFT_DBI_ADDR_8822C) +#define BITS_DBI_ADDR_8822C \ + (BIT_MASK_DBI_ADDR_8822C << BIT_SHIFT_DBI_ADDR_8822C) +#define BIT_CLEAR_DBI_ADDR_8822C(x) ((x) & (~BITS_DBI_ADDR_8822C)) +#define BIT_GET_DBI_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_DBI_ADDR_8822C) & BIT_MASK_DBI_ADDR_8822C) +#define BIT_SET_DBI_ADDR_8822C(x, v) \ + (BIT_CLEAR_DBI_ADDR_8822C(x) | BIT_DBI_ADDR_8822C(v)) + +/* 2 REG_MDIO_V1_8822C */ + +#define BIT_SHIFT_MDIO_RDATA_8822C 16 +#define BIT_MASK_MDIO_RDATA_8822C 0xffff +#define BIT_MDIO_RDATA_8822C(x) \ + (((x) & BIT_MASK_MDIO_RDATA_8822C) << BIT_SHIFT_MDIO_RDATA_8822C) +#define BITS_MDIO_RDATA_8822C \ + (BIT_MASK_MDIO_RDATA_8822C << BIT_SHIFT_MDIO_RDATA_8822C) +#define BIT_CLEAR_MDIO_RDATA_8822C(x) ((x) & (~BITS_MDIO_RDATA_8822C)) +#define BIT_GET_MDIO_RDATA_8822C(x) \ + (((x) >> BIT_SHIFT_MDIO_RDATA_8822C) & BIT_MASK_MDIO_RDATA_8822C) +#define BIT_SET_MDIO_RDATA_8822C(x, v) \ + (BIT_CLEAR_MDIO_RDATA_8822C(x) | BIT_MDIO_RDATA_8822C(v)) + +#define BIT_SHIFT_MDIO_WDATA_8822C 0 +#define BIT_MASK_MDIO_WDATA_8822C 0xffff +#define BIT_MDIO_WDATA_8822C(x) \ + (((x) & BIT_MASK_MDIO_WDATA_8822C) << BIT_SHIFT_MDIO_WDATA_8822C) +#define BITS_MDIO_WDATA_8822C \ + (BIT_MASK_MDIO_WDATA_8822C << BIT_SHIFT_MDIO_WDATA_8822C) +#define BIT_CLEAR_MDIO_WDATA_8822C(x) ((x) & (~BITS_MDIO_WDATA_8822C)) +#define BIT_GET_MDIO_WDATA_8822C(x) \ + (((x) >> BIT_SHIFT_MDIO_WDATA_8822C) & BIT_MASK_MDIO_WDATA_8822C) +#define BIT_SET_MDIO_WDATA_8822C(x, v) \ + (BIT_CLEAR_MDIO_WDATA_8822C(x) | BIT_MDIO_WDATA_8822C(v)) + +/* 2 REG_PCIE_MIX_CFG_8822C */ + +#define BIT_SHIFT_MDIO_PHY_ADDR_8822C 24 +#define BIT_MASK_MDIO_PHY_ADDR_8822C 0x1f +#define BIT_MDIO_PHY_ADDR_8822C(x) \ + (((x) & BIT_MASK_MDIO_PHY_ADDR_8822C) << BIT_SHIFT_MDIO_PHY_ADDR_8822C) +#define BITS_MDIO_PHY_ADDR_8822C \ + (BIT_MASK_MDIO_PHY_ADDR_8822C << BIT_SHIFT_MDIO_PHY_ADDR_8822C) +#define BIT_CLEAR_MDIO_PHY_ADDR_8822C(x) ((x) & (~BITS_MDIO_PHY_ADDR_8822C)) +#define BIT_GET_MDIO_PHY_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822C) & BIT_MASK_MDIO_PHY_ADDR_8822C) +#define BIT_SET_MDIO_PHY_ADDR_8822C(x, v) \ + (BIT_CLEAR_MDIO_PHY_ADDR_8822C(x) | BIT_MDIO_PHY_ADDR_8822C(v)) + +#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C 10 +#define BIT_MASK_WATCH_DOG_RECORD_V1_8822C 0x3fff +#define BIT_WATCH_DOG_RECORD_V1_8822C(x) \ + (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822C) \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C) +#define BITS_WATCH_DOG_RECORD_V1_8822C \ + (BIT_MASK_WATCH_DOG_RECORD_V1_8822C \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8822C(x) \ + ((x) & (~BITS_WATCH_DOG_RECORD_V1_8822C)) +#define BIT_GET_WATCH_DOG_RECORD_V1_8822C(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C) & \ + BIT_MASK_WATCH_DOG_RECORD_V1_8822C) +#define BIT_SET_WATCH_DOG_RECORD_V1_8822C(x, v) \ + (BIT_CLEAR_WATCH_DOG_RECORD_V1_8822C(x) | \ + BIT_WATCH_DOG_RECORD_V1_8822C(v)) + +#define BIT_R_IO_TIMEOUT_FLAG_V1_8822C BIT(9) +#define BIT_EN_WATCH_DOG_8822C BIT(8) +#define BIT_ECRC_EN_V1_8822C BIT(7) +#define BIT_MDIO_RFLAG_V1_8822C BIT(6) +#define BIT_MDIO_WFLAG_V1_8822C BIT(5) + +#define BIT_SHIFT_MDIO_REG_ADDR_V1_8822C 0 +#define BIT_MASK_MDIO_REG_ADDR_V1_8822C 0x1f +#define BIT_MDIO_REG_ADDR_V1_8822C(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822C) \ + << BIT_SHIFT_MDIO_REG_ADDR_V1_8822C) +#define BITS_MDIO_REG_ADDR_V1_8822C \ + (BIT_MASK_MDIO_REG_ADDR_V1_8822C << BIT_SHIFT_MDIO_REG_ADDR_V1_8822C) +#define BIT_CLEAR_MDIO_REG_ADDR_V1_8822C(x) \ + ((x) & (~BITS_MDIO_REG_ADDR_V1_8822C)) +#define BIT_GET_MDIO_REG_ADDR_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822C) & \ + BIT_MASK_MDIO_REG_ADDR_V1_8822C) +#define BIT_SET_MDIO_REG_ADDR_V1_8822C(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR_V1_8822C(x) | BIT_MDIO_REG_ADDR_V1_8822C(v)) + +/* 2 REG_HCI_MIX_CFG_8822C */ + +#define BIT_SHIFT_WATCH_DOG_TIMER_8822C 28 +#define BIT_MASK_WATCH_DOG_TIMER_8822C 0xf +#define BIT_WATCH_DOG_TIMER_8822C(x) \ + (((x) & BIT_MASK_WATCH_DOG_TIMER_8822C) \ + << BIT_SHIFT_WATCH_DOG_TIMER_8822C) +#define BITS_WATCH_DOG_TIMER_8822C \ + (BIT_MASK_WATCH_DOG_TIMER_8822C << BIT_SHIFT_WATCH_DOG_TIMER_8822C) +#define BIT_CLEAR_WATCH_DOG_TIMER_8822C(x) ((x) & (~BITS_WATCH_DOG_TIMER_8822C)) +#define BIT_GET_WATCH_DOG_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_TIMER_8822C) & \ + BIT_MASK_WATCH_DOG_TIMER_8822C) +#define BIT_SET_WATCH_DOG_TIMER_8822C(x, v) \ + (BIT_CLEAR_WATCH_DOG_TIMER_8822C(x) | BIT_WATCH_DOG_TIMER_8822C(v)) + +#define BIT_EN_ALIGN_MTU_8822C BIT(23) + +#define BIT_SHIFT_LATENCY_CONTROL_8822C 21 +#define BIT_MASK_LATENCY_CONTROL_8822C 0x3 +#define BIT_LATENCY_CONTROL_8822C(x) \ + (((x) & BIT_MASK_LATENCY_CONTROL_8822C) \ + << BIT_SHIFT_LATENCY_CONTROL_8822C) +#define BITS_LATENCY_CONTROL_8822C \ + (BIT_MASK_LATENCY_CONTROL_8822C << BIT_SHIFT_LATENCY_CONTROL_8822C) +#define BIT_CLEAR_LATENCY_CONTROL_8822C(x) ((x) & (~BITS_LATENCY_CONTROL_8822C)) +#define BIT_GET_LATENCY_CONTROL_8822C(x) \ + (((x) >> BIT_SHIFT_LATENCY_CONTROL_8822C) & \ + BIT_MASK_LATENCY_CONTROL_8822C) +#define BIT_SET_LATENCY_CONTROL_8822C(x, v) \ + (BIT_CLEAR_LATENCY_CONTROL_8822C(x) | BIT_LATENCY_CONTROL_8822C(v)) + +#define BIT_HOST_GEN2_SUPPORT_8822C BIT(20) + +#define BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C 15 +#define BIT_MASK_TXDMA_ERR_FLAG_V1_8822C 0x1f +#define BIT_TXDMA_ERR_FLAG_V1_8822C(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG_V1_8822C) \ + << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C) +#define BITS_TXDMA_ERR_FLAG_V1_8822C \ + (BIT_MASK_TXDMA_ERR_FLAG_V1_8822C << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C) +#define BIT_CLEAR_TXDMA_ERR_FLAG_V1_8822C(x) \ + ((x) & (~BITS_TXDMA_ERR_FLAG_V1_8822C)) +#define BIT_GET_TXDMA_ERR_FLAG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C) & \ + BIT_MASK_TXDMA_ERR_FLAG_V1_8822C) +#define BIT_SET_TXDMA_ERR_FLAG_V1_8822C(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG_V1_8822C(x) | BIT_TXDMA_ERR_FLAG_V1_8822C(v)) + +#define BIT_EPHY_RX50_EN_8822C BIT(11) + +#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C 8 +#define BIT_MASK_MSI_TIMEOUT_ID_V1_8822C 0x7 +#define BIT_MSI_TIMEOUT_ID_V1_8822C(x) \ + (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822C) \ + << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C) +#define BITS_MSI_TIMEOUT_ID_V1_8822C \ + (BIT_MASK_MSI_TIMEOUT_ID_V1_8822C << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822C(x) \ + ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8822C)) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C) & \ + BIT_MASK_MSI_TIMEOUT_ID_V1_8822C) +#define BIT_SET_MSI_TIMEOUT_ID_V1_8822C(x, v) \ + (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822C(x) | BIT_MSI_TIMEOUT_ID_V1_8822C(v)) + +#define BIT_RADDR_RD_8822C BIT(7) +#define BIT_L1OFF_PWR_OFF_EN_8822C BIT(6) +#define BIT_L0S_LINK_OFF_8822C BIT(4) +#define BIT_ACT_LINK_OFF_8822C BIT(3) +#define BIT_EN_SLOW_MAC_TX_8822C BIT(2) +#define BIT_EN_SLOW_MAC_RX_8822C BIT(1) +#define BIT_EN_SLOW_MAC_HW_8822C BIT(0) + +/* 2 REG_STC_INT_CS_8822C(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */ +#define BIT_STC_INT_EN_8822C BIT(31) + +#define BIT_SHIFT_STC_INT_FLAG_8822C 16 +#define BIT_MASK_STC_INT_FLAG_8822C 0xff +#define BIT_STC_INT_FLAG_8822C(x) \ + (((x) & BIT_MASK_STC_INT_FLAG_8822C) << BIT_SHIFT_STC_INT_FLAG_8822C) +#define BITS_STC_INT_FLAG_8822C \ + (BIT_MASK_STC_INT_FLAG_8822C << BIT_SHIFT_STC_INT_FLAG_8822C) +#define BIT_CLEAR_STC_INT_FLAG_8822C(x) ((x) & (~BITS_STC_INT_FLAG_8822C)) +#define BIT_GET_STC_INT_FLAG_8822C(x) \ + (((x) >> BIT_SHIFT_STC_INT_FLAG_8822C) & BIT_MASK_STC_INT_FLAG_8822C) +#define BIT_SET_STC_INT_FLAG_8822C(x, v) \ + (BIT_CLEAR_STC_INT_FLAG_8822C(x) | BIT_STC_INT_FLAG_8822C(v)) + +#define BIT_SHIFT_STC_INT_IDX_8822C 8 +#define BIT_MASK_STC_INT_IDX_8822C 0x7 +#define BIT_STC_INT_IDX_8822C(x) \ + (((x) & BIT_MASK_STC_INT_IDX_8822C) << BIT_SHIFT_STC_INT_IDX_8822C) +#define BITS_STC_INT_IDX_8822C \ + (BIT_MASK_STC_INT_IDX_8822C << BIT_SHIFT_STC_INT_IDX_8822C) +#define BIT_CLEAR_STC_INT_IDX_8822C(x) ((x) & (~BITS_STC_INT_IDX_8822C)) +#define BIT_GET_STC_INT_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_STC_INT_IDX_8822C) & BIT_MASK_STC_INT_IDX_8822C) +#define BIT_SET_STC_INT_IDX_8822C(x, v) \ + (BIT_CLEAR_STC_INT_IDX_8822C(x) | BIT_STC_INT_IDX_8822C(v)) + +#define BIT_SHIFT_STC_INT_REALTIME_CS_8822C 0 +#define BIT_MASK_STC_INT_REALTIME_CS_8822C 0x3f +#define BIT_STC_INT_REALTIME_CS_8822C(x) \ + (((x) & BIT_MASK_STC_INT_REALTIME_CS_8822C) \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8822C) +#define BITS_STC_INT_REALTIME_CS_8822C \ + (BIT_MASK_STC_INT_REALTIME_CS_8822C \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8822C) +#define BIT_CLEAR_STC_INT_REALTIME_CS_8822C(x) \ + ((x) & (~BITS_STC_INT_REALTIME_CS_8822C)) +#define BIT_GET_STC_INT_REALTIME_CS_8822C(x) \ + (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822C) & \ + BIT_MASK_STC_INT_REALTIME_CS_8822C) +#define BIT_SET_STC_INT_REALTIME_CS_8822C(x, v) \ + (BIT_CLEAR_STC_INT_REALTIME_CS_8822C(x) | \ + BIT_STC_INT_REALTIME_CS_8822C(v)) + +#define BIT_STC_INT_GRP_EN_8822C BIT(31) + +#define BIT_SHIFT_STC_INT_EXPECT_LS_8822C 8 +#define BIT_MASK_STC_INT_EXPECT_LS_8822C 0x3f +#define BIT_STC_INT_EXPECT_LS_8822C(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_LS_8822C) \ + << BIT_SHIFT_STC_INT_EXPECT_LS_8822C) +#define BITS_STC_INT_EXPECT_LS_8822C \ + (BIT_MASK_STC_INT_EXPECT_LS_8822C << BIT_SHIFT_STC_INT_EXPECT_LS_8822C) +#define BIT_CLEAR_STC_INT_EXPECT_LS_8822C(x) \ + ((x) & (~BITS_STC_INT_EXPECT_LS_8822C)) +#define BIT_GET_STC_INT_EXPECT_LS_8822C(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822C) & \ + BIT_MASK_STC_INT_EXPECT_LS_8822C) +#define BIT_SET_STC_INT_EXPECT_LS_8822C(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_LS_8822C(x) | BIT_STC_INT_EXPECT_LS_8822C(v)) + +#define BIT_SHIFT_STC_INT_EXPECT_CS_8822C 0 +#define BIT_MASK_STC_INT_EXPECT_CS_8822C 0x3f +#define BIT_STC_INT_EXPECT_CS_8822C(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_CS_8822C) \ + << BIT_SHIFT_STC_INT_EXPECT_CS_8822C) +#define BITS_STC_INT_EXPECT_CS_8822C \ + (BIT_MASK_STC_INT_EXPECT_CS_8822C << BIT_SHIFT_STC_INT_EXPECT_CS_8822C) +#define BIT_CLEAR_STC_INT_EXPECT_CS_8822C(x) \ + ((x) & (~BITS_STC_INT_EXPECT_CS_8822C)) +#define BIT_GET_STC_INT_EXPECT_CS_8822C(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822C) & \ + BIT_MASK_STC_INT_EXPECT_CS_8822C) +#define BIT_SET_STC_INT_EXPECT_CS_8822C(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_CS_8822C(x) | BIT_STC_INT_EXPECT_CS_8822C(v)) + +/* 2 REG_H2CQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_H2CQ_TXBD_DESA_8822C 0 +#define BIT_MASK_H2CQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_H2CQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_8822C) \ + << BIT_SHIFT_H2CQ_TXBD_DESA_8822C) +#define BITS_H2CQ_TXBD_DESA_8822C \ + (BIT_MASK_H2CQ_TXBD_DESA_8822C << BIT_SHIFT_H2CQ_TXBD_DESA_8822C) +#define BIT_CLEAR_H2CQ_TXBD_DESA_8822C(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8822C)) +#define BIT_GET_H2CQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822C) & \ + BIT_MASK_H2CQ_TXBD_DESA_8822C) +#define BIT_SET_H2CQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_8822C(x) | BIT_H2CQ_TXBD_DESA_8822C(v)) + +/* 2 REG_H2CQ_TXBD_NUM_8822C */ +#define BIT_PCIE_H2CQ_FLAG_8822C BIT(14) + +#define BIT_SHIFT_H2CQ_DESC_MODE_8822C 12 +#define BIT_MASK_H2CQ_DESC_MODE_8822C 0x3 +#define BIT_H2CQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_H2CQ_DESC_MODE_8822C) \ + << BIT_SHIFT_H2CQ_DESC_MODE_8822C) +#define BITS_H2CQ_DESC_MODE_8822C \ + (BIT_MASK_H2CQ_DESC_MODE_8822C << BIT_SHIFT_H2CQ_DESC_MODE_8822C) +#define BIT_CLEAR_H2CQ_DESC_MODE_8822C(x) ((x) & (~BITS_H2CQ_DESC_MODE_8822C)) +#define BIT_GET_H2CQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822C) & \ + BIT_MASK_H2CQ_DESC_MODE_8822C) +#define BIT_SET_H2CQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_H2CQ_DESC_MODE_8822C(x) | BIT_H2CQ_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_H2CQ_DESC_NUM_8822C 0 +#define BIT_MASK_H2CQ_DESC_NUM_8822C 0xfff +#define BIT_H2CQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_H2CQ_DESC_NUM_8822C) << BIT_SHIFT_H2CQ_DESC_NUM_8822C) +#define BITS_H2CQ_DESC_NUM_8822C \ + (BIT_MASK_H2CQ_DESC_NUM_8822C << BIT_SHIFT_H2CQ_DESC_NUM_8822C) +#define BIT_CLEAR_H2CQ_DESC_NUM_8822C(x) ((x) & (~BITS_H2CQ_DESC_NUM_8822C)) +#define BIT_GET_H2CQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822C) & BIT_MASK_H2CQ_DESC_NUM_8822C) +#define BIT_SET_H2CQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_H2CQ_DESC_NUM_8822C(x) | BIT_H2CQ_DESC_NUM_8822C(v)) + +/* 2 REG_H2CQ_TXBD_IDX_8822C */ + +#define BIT_SHIFT_H2CQ_HW_IDX_8822C 16 +#define BIT_MASK_H2CQ_HW_IDX_8822C 0xfff +#define BIT_H2CQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_H2CQ_HW_IDX_8822C) << BIT_SHIFT_H2CQ_HW_IDX_8822C) +#define BITS_H2CQ_HW_IDX_8822C \ + (BIT_MASK_H2CQ_HW_IDX_8822C << BIT_SHIFT_H2CQ_HW_IDX_8822C) +#define BIT_CLEAR_H2CQ_HW_IDX_8822C(x) ((x) & (~BITS_H2CQ_HW_IDX_8822C)) +#define BIT_GET_H2CQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822C) & BIT_MASK_H2CQ_HW_IDX_8822C) +#define BIT_SET_H2CQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_H2CQ_HW_IDX_8822C(x) | BIT_H2CQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_H2CQ_HOST_IDX_8822C 0 +#define BIT_MASK_H2CQ_HOST_IDX_8822C 0xfff +#define BIT_H2CQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_H2CQ_HOST_IDX_8822C) << BIT_SHIFT_H2CQ_HOST_IDX_8822C) +#define BITS_H2CQ_HOST_IDX_8822C \ + (BIT_MASK_H2CQ_HOST_IDX_8822C << BIT_SHIFT_H2CQ_HOST_IDX_8822C) +#define BIT_CLEAR_H2CQ_HOST_IDX_8822C(x) ((x) & (~BITS_H2CQ_HOST_IDX_8822C)) +#define BIT_GET_H2CQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822C) & BIT_MASK_H2CQ_HOST_IDX_8822C) +#define BIT_SET_H2CQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_H2CQ_HOST_IDX_8822C(x) | BIT_H2CQ_HOST_IDX_8822C(v)) + +/* 2 REG_H2CQ_CSR_8822C[31:0] (H2CQ CONTROL AND STATUS) */ +#define BIT_H2CQ_FULL_8822C BIT(31) +#define BIT_CLR_H2CQ_HOST_IDX_8822C BIT(16) +#define BIT_CLR_H2CQ_HW_IDX_8822C BIT(8) +#define BIT_STOP_H2CQ_8822C BIT(0) + +/* 2 REG_CHANGE_PCIE_SPEED_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_RXDMA_ERR_CNT_8822C 8 +#define BIT_MASK_RXDMA_ERR_CNT_8822C 0xff +#define BIT_RXDMA_ERR_CNT_8822C(x) \ + (((x) & BIT_MASK_RXDMA_ERR_CNT_8822C) << BIT_SHIFT_RXDMA_ERR_CNT_8822C) +#define BITS_RXDMA_ERR_CNT_8822C \ + (BIT_MASK_RXDMA_ERR_CNT_8822C << BIT_SHIFT_RXDMA_ERR_CNT_8822C) +#define BIT_CLEAR_RXDMA_ERR_CNT_8822C(x) ((x) & (~BITS_RXDMA_ERR_CNT_8822C)) +#define BIT_GET_RXDMA_ERR_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_RXDMA_ERR_CNT_8822C) & BIT_MASK_RXDMA_ERR_CNT_8822C) +#define BIT_SET_RXDMA_ERR_CNT_8822C(x, v) \ + (BIT_CLEAR_RXDMA_ERR_CNT_8822C(x) | BIT_RXDMA_ERR_CNT_8822C(v)) + +#define BIT_TXDMA_ERR_HANDLE_REQ_8822C BIT(7) +#define BIT_TXDMA_ERROR_PS_8822C BIT(6) +#define BIT_EN_TXDMA_STUCK_ERR_HANDLE_8822C BIT(5) +#define BIT_EN_TXDMA_RTN_ERR_HANDLE_8822C BIT(4) +#define BIT_RXDMA_ERR_HANDLE_REQ_8822C BIT(3) +#define BIT_RXDMA_ERROR_PS_8822C BIT(2) +#define BIT_EN_RXDMA_STUCK_ERR_HANDLE_8822C BIT(1) +#define BIT_EN_RXDMA_RTN_ERR_HANDLE_8822C BIT(0) + +/* 2 REG_DEBUG_STATE1_8822C */ + +#define BIT_SHIFT_DEBUG_STATE1_8822C 0 +#define BIT_MASK_DEBUG_STATE1_8822C 0xffffffffL +#define BIT_DEBUG_STATE1_8822C(x) \ + (((x) & BIT_MASK_DEBUG_STATE1_8822C) << BIT_SHIFT_DEBUG_STATE1_8822C) +#define BITS_DEBUG_STATE1_8822C \ + (BIT_MASK_DEBUG_STATE1_8822C << BIT_SHIFT_DEBUG_STATE1_8822C) +#define BIT_CLEAR_DEBUG_STATE1_8822C(x) ((x) & (~BITS_DEBUG_STATE1_8822C)) +#define BIT_GET_DEBUG_STATE1_8822C(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE1_8822C) & BIT_MASK_DEBUG_STATE1_8822C) +#define BIT_SET_DEBUG_STATE1_8822C(x, v) \ + (BIT_CLEAR_DEBUG_STATE1_8822C(x) | BIT_DEBUG_STATE1_8822C(v)) + +/* 2 REG_DEBUG_STATE2_8822C */ + +#define BIT_SHIFT_DEBUG_STATE2_8822C 0 +#define BIT_MASK_DEBUG_STATE2_8822C 0xffffffffL +#define BIT_DEBUG_STATE2_8822C(x) \ + (((x) & BIT_MASK_DEBUG_STATE2_8822C) << BIT_SHIFT_DEBUG_STATE2_8822C) +#define BITS_DEBUG_STATE2_8822C \ + (BIT_MASK_DEBUG_STATE2_8822C << BIT_SHIFT_DEBUG_STATE2_8822C) +#define BIT_CLEAR_DEBUG_STATE2_8822C(x) ((x) & (~BITS_DEBUG_STATE2_8822C)) +#define BIT_GET_DEBUG_STATE2_8822C(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE2_8822C) & BIT_MASK_DEBUG_STATE2_8822C) +#define BIT_SET_DEBUG_STATE2_8822C(x, v) \ + (BIT_CLEAR_DEBUG_STATE2_8822C(x) | BIT_DEBUG_STATE2_8822C(v)) + +/* 2 REG_DEBUG_STATE3_8822C */ + +#define BIT_SHIFT_DEBUG_STATE3_8822C 0 +#define BIT_MASK_DEBUG_STATE3_8822C 0xffffffffL +#define BIT_DEBUG_STATE3_8822C(x) \ + (((x) & BIT_MASK_DEBUG_STATE3_8822C) << BIT_SHIFT_DEBUG_STATE3_8822C) +#define BITS_DEBUG_STATE3_8822C \ + (BIT_MASK_DEBUG_STATE3_8822C << BIT_SHIFT_DEBUG_STATE3_8822C) +#define BIT_CLEAR_DEBUG_STATE3_8822C(x) ((x) & (~BITS_DEBUG_STATE3_8822C)) +#define BIT_GET_DEBUG_STATE3_8822C(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE3_8822C) & BIT_MASK_DEBUG_STATE3_8822C) +#define BIT_SET_DEBUG_STATE3_8822C(x, v) \ + (BIT_CLEAR_DEBUG_STATE3_8822C(x) | BIT_DEBUG_STATE3_8822C(v)) + +/* 2 REG_CHNL_DMA_CFG_V1_8822C */ +#define BIT_TXHCI_EN_V1_8822C BIT(26) +#define BIT_TXHCI_IDLE_V1_8822C BIT(25) +#define BIT_DMA_PRI_EN_V1_8822C BIT(24) + +/* 2 REG_PCIE_HISR0_V1_8822C */ +#define BIT_PSTIMER_2_8822C BIT(31) +#define BIT_PSTIMER_1_8822C BIT(30) +#define BIT_PSTIMER_0_8822C BIT(29) +#define BIT_GTINT4_8822C BIT(28) +#define BIT_GTINT3_8822C BIT(27) +#define BIT_TXBCN0ERR_8822C BIT(26) +#define BIT_TXBCN0OK_8822C BIT(25) +#define BIT_TSF_BIT32_TOGGLE_8822C BIT(24) +#define BIT_TXDMA_START_INT_8822C BIT(23) +#define BIT_TXDMA_STOP_INT_8822C BIT(22) +#define BIT_HISR7_IND_8822C BIT(21) +#define BIT_BCNDMAINT0_8822C BIT(20) +#define BIT_HISR6_IND_8822C BIT(19) +#define BIT_HISR5_IND_8822C BIT(18) +#define BIT_HISR4_IND_8822C BIT(17) +#define BIT_BCNDERR0_8822C BIT(16) +#define BIT_HSISR_IND_ON_INT_8822C BIT(15) +#define BIT_HISR3_IND_8822C BIT(14) +#define BIT_HISR2_IND_8822C BIT(13) +#define BIT_HISR1_IND_8822C BIT(11) +#define BIT_C2HCMD_8822C BIT(10) +#define BIT_CPWM2_8822C BIT(9) +#define BIT_CPWM_8822C BIT(8) +#define BIT_TXDMAOK_CHANNEL15_8822C BIT(7) +#define BIT_TXDMAOK_CHANNEL14_8822C BIT(6) +#define BIT_TXDMAOK_CHANNEL3_8822C BIT(5) +#define BIT_TXDMAOK_CHANNEL2_8822C BIT(4) +#define BIT_TXDMAOK_CHANNEL1_8822C BIT(3) +#define BIT_TXDMAOK_CHANNEL0_8822C BIT(2) +#define BIT_RDU_8822C BIT(1) +#define BIT_RXOK_8822C BIT(0) + +/* 2 REG_PCIE_HISR1_V1_8822C */ +#define BIT_PRE_TX_ERR_INT_8822C BIT(31) +#define BIT_TXFIFO_TH_INT_8822C BIT(30) +#define BIT_BTON_STS_UPDATE_INT_8822C BIT(29) +#define BIT_BCNDMAINT7_8822C BIT(27) +#define BIT_BCNDMAINT6_8822C BIT(26) +#define BIT_BCNDMAINT5_8822C BIT(25) +#define BIT_BCNDMAINT4_8822C BIT(24) +#define BIT_BCNDMAINT3_8822C BIT(23) +#define BIT_BCNDMAINT2_8822C BIT(22) +#define BIT_BCNDMAINT1_8822C BIT(21) +#define BIT_BCNDERR7_8822C BIT(20) +#define BIT_BCNDERR6_8822C BIT(19) +#define BIT_BCNDERR5_8822C BIT(18) +#define BIT_BCNDERR4_8822C BIT(17) +#define BIT_BCNDERR3_8822C BIT(16) +#define BIT_BCNDERR2_8822C BIT(15) +#define BIT_BCNDERR1_8822C BIT(14) +#define BIT_ATIMEND_8822C BIT(12) +#define BIT_TXERR_INT_8822C BIT(11) +#define BIT_RXERR_INT_8822C BIT(10) +#define BIT_TXFOVW_8822C BIT(9) +#define BIT_FOVW_8822C BIT(8) +#define BIT_CPU_MGQ_EARLY_INT_8822C BIT(6) +#define BIT_CPU_MGQ_TXDONE_8822C BIT(5) +#define BIT_PSTIMER_5_8822C BIT(4) +#define BIT_PSTIMER_4_8822C BIT(3) +#define BIT_PSTIMER_3_8822C BIT(2) +#define BIT_CPUMGQ_TX_TIMER_8822C BIT(1) +#define BIT_BB_STOPRX_INT_8822C BIT(0) + +/* 2 REG_PCIE_HISR2_V1_8822C */ +#define BIT_BCNDMAINT_P4_8822C BIT(31) +#define BIT_BCNDMAINT_P3_8822C BIT(30) +#define BIT_BCNDMAINT_P2_8822C BIT(29) +#define BIT_BCNDMAINT_P1_8822C BIT(28) +#define BIT_SCH_PHY_TXOP_SIFS_INT_8822C BIT(23) +#define BIT_ATIMEND7_8822C BIT(22) +#define BIT_ATIMEND6_8822C BIT(21) +#define BIT_ATIMEND5_8822C BIT(20) +#define BIT_ATIMEND4_8822C BIT(19) +#define BIT_ATIMEND3_8822C BIT(18) +#define BIT_ATIMEND2_8822C BIT(17) +#define BIT_ATIMEND1_8822C BIT(16) +#define BIT_TXBCN7OK_8822C BIT(14) +#define BIT_TXBCN6OK_8822C BIT(13) +#define BIT_TXBCN5OK_8822C BIT(12) +#define BIT_TXBCN4OK_8822C BIT(11) +#define BIT_TXBCN3OK_8822C BIT(10) +#define BIT_TXBCN2OK_8822C BIT(9) +#define BIT_TXBCN1OK_8822C BIT(8) +#define BIT_TXBCN7ERR_8822C BIT(6) +#define BIT_TXBCN6ERR_8822C BIT(5) +#define BIT_TXBCN5ERR_8822C BIT(4) +#define BIT_TXBCN4ERR_8822C BIT(3) +#define BIT_TXBCN3ERR_8822C BIT(2) +#define BIT_TXBCN2ERR_8822C BIT(1) +#define BIT_TXBCN1ERR_8822C BIT(0) + +/* 2 REG_PCIE_HISR3_V1_8822C */ +#define BIT_GTINT12_8822C BIT(24) +#define BIT_GTINT11_8822C BIT(23) +#define BIT_GTINT10_8822C BIT(22) +#define BIT_GTINT9_8822C BIT(21) +#define BIT_RX_DESC_BUF_FULL_8822C BIT(20) +#define BIT_CPHY_LDO_OCP_DET_INT_8822C BIT(19) +#define BIT_WDT_PLATFORM_INT_8822C BIT(18) +#define BIT_WDT_CPU_INT_8822C BIT(17) +#define BIT_SETH2CDOK_8822C BIT(16) +#define BIT_H2C_CMD_FULL_8822C BIT(15) +#define BIT_PKT_TRANS_ERR_8822C BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822C BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_8822C BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_8822C BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_8822C BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_8822C BIT(9) +#define BIT_SEARCH_FAIL_8822C BIT(8) +#define BIT_PWR_INT_127TO96_8822C BIT(7) +#define BIT_PWR_INT_95TO64_8822C BIT(6) +#define BIT_PWR_INT_63TO32_8822C BIT(5) +#define BIT_PWR_INT_31TO0_8822C BIT(4) +#define BIT_RX_DMA_STUCK_8822C BIT(3) +#define BIT_TX_DMA_STUCK_8822C BIT(2) +#define BIT_DDMA0_LP_INT_8822C BIT(1) +#define BIT_DDMA0_HP_INT_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_Q0_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q0_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q0_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q0_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q0_V1_8822C) +#define BITS_QUEUEMACID_Q0_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q0_V1_8822C << BIT_SHIFT_QUEUEMACID_Q0_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q0_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q0_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q0_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q0_V1_8822C) +#define BIT_SET_QUEUEMACID_Q0_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q0_V1_8822C(x) | BIT_QUEUEMACID_Q0_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q0_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q0_V1_8822C 0x3 +#define BIT_QUEUEAC_Q0_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q0_V1_8822C) << BIT_SHIFT_QUEUEAC_Q0_V1_8822C) +#define BITS_QUEUEAC_Q0_V1_8822C \ + (BIT_MASK_QUEUEAC_Q0_V1_8822C << BIT_SHIFT_QUEUEAC_Q0_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q0_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8822C)) +#define BIT_GET_QUEUEAC_Q0_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822C) & BIT_MASK_QUEUEAC_Q0_V1_8822C) +#define BIT_SET_QUEUEAC_Q0_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q0_V1_8822C(x) | BIT_QUEUEAC_Q0_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q0_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q0_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q0_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q0_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q0_V2_8822C) +#define BITS_TAIL_PKT_Q0_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q0_V2_8822C << BIT_SHIFT_TAIL_PKT_Q0_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q0_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q0_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q0_V2_8822C) +#define BIT_SET_TAIL_PKT_Q0_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q0_V2_8822C(x) | BIT_TAIL_PKT_Q0_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q0_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q0_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q0_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q0_V1_8822C) +#define BITS_HEAD_PKT_Q0_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q0_V1_8822C << BIT_SHIFT_HEAD_PKT_Q0_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q0_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q0_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q0_V1_8822C) +#define BIT_SET_HEAD_PKT_Q0_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q0_V1_8822C(x) | BIT_HEAD_PKT_Q0_V1_8822C(v)) + +/* 2 REG_Q1_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q1_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q1_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q1_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q1_V1_8822C) +#define BITS_QUEUEMACID_Q1_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q1_V1_8822C << BIT_SHIFT_QUEUEMACID_Q1_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q1_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q1_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q1_V1_8822C) +#define BIT_SET_QUEUEMACID_Q1_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q1_V1_8822C(x) | BIT_QUEUEMACID_Q1_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q1_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q1_V1_8822C 0x3 +#define BIT_QUEUEAC_Q1_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q1_V1_8822C) << BIT_SHIFT_QUEUEAC_Q1_V1_8822C) +#define BITS_QUEUEAC_Q1_V1_8822C \ + (BIT_MASK_QUEUEAC_Q1_V1_8822C << BIT_SHIFT_QUEUEAC_Q1_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q1_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8822C)) +#define BIT_GET_QUEUEAC_Q1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822C) & BIT_MASK_QUEUEAC_Q1_V1_8822C) +#define BIT_SET_QUEUEAC_Q1_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q1_V1_8822C(x) | BIT_QUEUEAC_Q1_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q1_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q1_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q1_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q1_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q1_V2_8822C) +#define BITS_TAIL_PKT_Q1_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q1_V2_8822C << BIT_SHIFT_TAIL_PKT_Q1_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q1_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q1_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q1_V2_8822C) +#define BIT_SET_TAIL_PKT_Q1_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q1_V2_8822C(x) | BIT_TAIL_PKT_Q1_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q1_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q1_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q1_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q1_V1_8822C) +#define BITS_HEAD_PKT_Q1_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q1_V1_8822C << BIT_SHIFT_HEAD_PKT_Q1_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q1_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q1_V1_8822C) +#define BIT_SET_HEAD_PKT_Q1_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q1_V1_8822C(x) | BIT_HEAD_PKT_Q1_V1_8822C(v)) + +/* 2 REG_Q2_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q2_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q2_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q2_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q2_V1_8822C) +#define BITS_QUEUEMACID_Q2_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q2_V1_8822C << BIT_SHIFT_QUEUEMACID_Q2_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q2_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q2_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q2_V1_8822C) +#define BIT_SET_QUEUEMACID_Q2_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q2_V1_8822C(x) | BIT_QUEUEMACID_Q2_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q2_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q2_V1_8822C 0x3 +#define BIT_QUEUEAC_Q2_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q2_V1_8822C) << BIT_SHIFT_QUEUEAC_Q2_V1_8822C) +#define BITS_QUEUEAC_Q2_V1_8822C \ + (BIT_MASK_QUEUEAC_Q2_V1_8822C << BIT_SHIFT_QUEUEAC_Q2_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q2_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8822C)) +#define BIT_GET_QUEUEAC_Q2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822C) & BIT_MASK_QUEUEAC_Q2_V1_8822C) +#define BIT_SET_QUEUEAC_Q2_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q2_V1_8822C(x) | BIT_QUEUEAC_Q2_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q2_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q2_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q2_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q2_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q2_V2_8822C) +#define BITS_TAIL_PKT_Q2_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q2_V2_8822C << BIT_SHIFT_TAIL_PKT_Q2_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q2_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q2_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q2_V2_8822C) +#define BIT_SET_TAIL_PKT_Q2_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q2_V2_8822C(x) | BIT_TAIL_PKT_Q2_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q2_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q2_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q2_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q2_V1_8822C) +#define BITS_HEAD_PKT_Q2_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q2_V1_8822C << BIT_SHIFT_HEAD_PKT_Q2_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q2_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q2_V1_8822C) +#define BIT_SET_HEAD_PKT_Q2_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q2_V1_8822C(x) | BIT_HEAD_PKT_Q2_V1_8822C(v)) + +/* 2 REG_Q3_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q3_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q3_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q3_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q3_V1_8822C) +#define BITS_QUEUEMACID_Q3_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q3_V1_8822C << BIT_SHIFT_QUEUEMACID_Q3_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q3_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q3_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q3_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q3_V1_8822C) +#define BIT_SET_QUEUEMACID_Q3_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q3_V1_8822C(x) | BIT_QUEUEMACID_Q3_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q3_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q3_V1_8822C 0x3 +#define BIT_QUEUEAC_Q3_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q3_V1_8822C) << BIT_SHIFT_QUEUEAC_Q3_V1_8822C) +#define BITS_QUEUEAC_Q3_V1_8822C \ + (BIT_MASK_QUEUEAC_Q3_V1_8822C << BIT_SHIFT_QUEUEAC_Q3_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q3_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8822C)) +#define BIT_GET_QUEUEAC_Q3_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822C) & BIT_MASK_QUEUEAC_Q3_V1_8822C) +#define BIT_SET_QUEUEAC_Q3_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q3_V1_8822C(x) | BIT_QUEUEAC_Q3_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q3_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q3_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q3_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q3_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q3_V2_8822C) +#define BITS_TAIL_PKT_Q3_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q3_V2_8822C << BIT_SHIFT_TAIL_PKT_Q3_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q3_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q3_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q3_V2_8822C) +#define BIT_SET_TAIL_PKT_Q3_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q3_V2_8822C(x) | BIT_TAIL_PKT_Q3_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q3_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q3_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q3_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q3_V1_8822C) +#define BITS_HEAD_PKT_Q3_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q3_V1_8822C << BIT_SHIFT_HEAD_PKT_Q3_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q3_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q3_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q3_V1_8822C) +#define BIT_SET_HEAD_PKT_Q3_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q3_V1_8822C(x) | BIT_HEAD_PKT_Q3_V1_8822C(v)) + +/* 2 REG_MGQ_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_MGQ_V1_8822C 0x7f +#define BIT_QUEUEMACID_MGQ_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C) +#define BITS_QUEUEMACID_MGQ_V1_8822C \ + (BIT_MASK_QUEUEMACID_MGQ_V1_8822C << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_MGQ_V1_8822C)) +#define BIT_GET_QUEUEMACID_MGQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C) & \ + BIT_MASK_QUEUEMACID_MGQ_V1_8822C) +#define BIT_SET_QUEUEMACID_MGQ_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_MGQ_V1_8822C(x) | BIT_QUEUEMACID_MGQ_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_MGQ_V1_8822C 23 +#define BIT_MASK_QUEUEAC_MGQ_V1_8822C 0x3 +#define BIT_QUEUEAC_MGQ_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822C) \ + << BIT_SHIFT_QUEUEAC_MGQ_V1_8822C) +#define BITS_QUEUEAC_MGQ_V1_8822C \ + (BIT_MASK_QUEUEAC_MGQ_V1_8822C << BIT_SHIFT_QUEUEAC_MGQ_V1_8822C) +#define BIT_CLEAR_QUEUEAC_MGQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8822C)) +#define BIT_GET_QUEUEAC_MGQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822C) & \ + BIT_MASK_QUEUEAC_MGQ_V1_8822C) +#define BIT_SET_QUEUEAC_MGQ_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_MGQ_V1_8822C(x) | BIT_QUEUEAC_MGQ_V1_8822C(v)) + +#define BIT_TIDEMPTY_MGQ_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_MGQ_V2_8822C 0x7ff +#define BIT_TAIL_PKT_MGQ_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C) +#define BITS_TAIL_PKT_MGQ_V2_8822C \ + (BIT_MASK_TAIL_PKT_MGQ_V2_8822C << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8822C)) +#define BIT_GET_TAIL_PKT_MGQ_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C) & \ + BIT_MASK_TAIL_PKT_MGQ_V2_8822C) +#define BIT_SET_TAIL_PKT_MGQ_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_MGQ_V2_8822C(x) | BIT_TAIL_PKT_MGQ_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_MGQ_V1_8822C 0x7ff +#define BIT_HEAD_PKT_MGQ_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C) +#define BITS_HEAD_PKT_MGQ_V1_8822C \ + (BIT_MASK_HEAD_PKT_MGQ_V1_8822C << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8822C)) +#define BIT_GET_HEAD_PKT_MGQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C) & \ + BIT_MASK_HEAD_PKT_MGQ_V1_8822C) +#define BIT_SET_HEAD_PKT_MGQ_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_MGQ_V1_8822C(x) | BIT_HEAD_PKT_MGQ_V1_8822C(v)) + +/* 2 REG_HIQ_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_HIQ_V1_8822C 0x7f +#define BIT_QUEUEMACID_HIQ_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C) +#define BITS_QUEUEMACID_HIQ_V1_8822C \ + (BIT_MASK_QUEUEMACID_HIQ_V1_8822C << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_HIQ_V1_8822C)) +#define BIT_GET_QUEUEMACID_HIQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C) & \ + BIT_MASK_QUEUEMACID_HIQ_V1_8822C) +#define BIT_SET_QUEUEMACID_HIQ_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_HIQ_V1_8822C(x) | BIT_QUEUEMACID_HIQ_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_HIQ_V1_8822C 23 +#define BIT_MASK_QUEUEAC_HIQ_V1_8822C 0x3 +#define BIT_QUEUEAC_HIQ_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822C) \ + << BIT_SHIFT_QUEUEAC_HIQ_V1_8822C) +#define BITS_QUEUEAC_HIQ_V1_8822C \ + (BIT_MASK_QUEUEAC_HIQ_V1_8822C << BIT_SHIFT_QUEUEAC_HIQ_V1_8822C) +#define BIT_CLEAR_QUEUEAC_HIQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8822C)) +#define BIT_GET_QUEUEAC_HIQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822C) & \ + BIT_MASK_QUEUEAC_HIQ_V1_8822C) +#define BIT_SET_QUEUEAC_HIQ_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_HIQ_V1_8822C(x) | BIT_QUEUEAC_HIQ_V1_8822C(v)) + +#define BIT_TIDEMPTY_HIQ_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_HIQ_V2_8822C 0x7ff +#define BIT_TAIL_PKT_HIQ_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C) +#define BITS_TAIL_PKT_HIQ_V2_8822C \ + (BIT_MASK_TAIL_PKT_HIQ_V2_8822C << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8822C)) +#define BIT_GET_TAIL_PKT_HIQ_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C) & \ + BIT_MASK_TAIL_PKT_HIQ_V2_8822C) +#define BIT_SET_TAIL_PKT_HIQ_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_HIQ_V2_8822C(x) | BIT_TAIL_PKT_HIQ_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_HIQ_V1_8822C 0x7ff +#define BIT_HEAD_PKT_HIQ_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C) +#define BITS_HEAD_PKT_HIQ_V1_8822C \ + (BIT_MASK_HEAD_PKT_HIQ_V1_8822C << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8822C)) +#define BIT_GET_HEAD_PKT_HIQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C) & \ + BIT_MASK_HEAD_PKT_HIQ_V1_8822C) +#define BIT_SET_HEAD_PKT_HIQ_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_HIQ_V1_8822C(x) | BIT_HEAD_PKT_HIQ_V1_8822C(v)) + +/* 2 REG_BCNQ_INFO_8822C */ + +#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C 0 +#define BIT_MASK_BCNQ_HEAD_PG_V1_8822C 0xfff +#define BIT_BCNQ_HEAD_PG_V1_8822C(x) \ + (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822C) \ + << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C) +#define BITS_BCNQ_HEAD_PG_V1_8822C \ + (BIT_MASK_BCNQ_HEAD_PG_V1_8822C << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C) +#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8822C(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8822C)) +#define BIT_GET_BCNQ_HEAD_PG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C) & \ + BIT_MASK_BCNQ_HEAD_PG_V1_8822C) +#define BIT_SET_BCNQ_HEAD_PG_V1_8822C(x, v) \ + (BIT_CLEAR_BCNQ_HEAD_PG_V1_8822C(x) | BIT_BCNQ_HEAD_PG_V1_8822C(v)) + +/* 2 REG_TXPKT_EMPTY_8822C */ +#define BIT_BCNQ_EMPTY_8822C BIT(11) +#define BIT_HQQ_EMPTY_8822C BIT(10) +#define BIT_MQQ_EMPTY_8822C BIT(9) +#define BIT_MGQ_CPU_EMPTY_8822C BIT(8) +#define BIT_AC7Q_EMPTY_8822C BIT(7) +#define BIT_AC6Q_EMPTY_8822C BIT(6) +#define BIT_AC5Q_EMPTY_8822C BIT(5) +#define BIT_AC4Q_EMPTY_8822C BIT(4) +#define BIT_AC3Q_EMPTY_8822C BIT(3) +#define BIT_AC2Q_EMPTY_8822C BIT(2) +#define BIT_AC1Q_EMPTY_8822C BIT(1) +#define BIT_AC0Q_EMPTY_8822C BIT(0) + +/* 2 REG_CPU_MGQ_INFO_8822C */ +#define BIT_BCN1_POLL_8822C BIT(30) +#define BIT_CPUMGT_POLL_8822C BIT(29) +#define BIT_BCN_POLL_8822C BIT(28) +#define BIT_CPUMGQ_FW_NUM_V1_8822C BIT(12) + +#define BIT_SHIFT_FW_FREE_TAIL_V1_8822C 0 +#define BIT_MASK_FW_FREE_TAIL_V1_8822C 0xfff +#define BIT_FW_FREE_TAIL_V1_8822C(x) \ + (((x) & BIT_MASK_FW_FREE_TAIL_V1_8822C) \ + << BIT_SHIFT_FW_FREE_TAIL_V1_8822C) +#define BITS_FW_FREE_TAIL_V1_8822C \ + (BIT_MASK_FW_FREE_TAIL_V1_8822C << BIT_SHIFT_FW_FREE_TAIL_V1_8822C) +#define BIT_CLEAR_FW_FREE_TAIL_V1_8822C(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8822C)) +#define BIT_GET_FW_FREE_TAIL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822C) & \ + BIT_MASK_FW_FREE_TAIL_V1_8822C) +#define BIT_SET_FW_FREE_TAIL_V1_8822C(x, v) \ + (BIT_CLEAR_FW_FREE_TAIL_V1_8822C(x) | BIT_FW_FREE_TAIL_V1_8822C(v)) + +/* 2 REG_FWHW_TXQ_CTRL_8822C */ +#define BIT_RTS_LIMIT_IN_OFDM_8822C BIT(23) +#define BIT_EN_BCNQ_DL_8822C BIT(22) +#define BIT_EN_RD_RESP_NAV_BK_8822C BIT(21) +#define BIT_EN_WR_FREE_TAIL_8822C BIT(20) +#define BIT_NOTXRPT_USERATE_EN_8822C BIT(19) +#define BIT_DIS_TXFAIL_RPT_8822C BIT(18) +#define BIT_FTM_TIMEOUT_BYPASS_8822C BIT(16) + +#define BIT_SHIFT_EN_QUEUE_RPT_8822C 8 +#define BIT_MASK_EN_QUEUE_RPT_8822C 0xff +#define BIT_EN_QUEUE_RPT_8822C(x) \ + (((x) & BIT_MASK_EN_QUEUE_RPT_8822C) << BIT_SHIFT_EN_QUEUE_RPT_8822C) +#define BITS_EN_QUEUE_RPT_8822C \ + (BIT_MASK_EN_QUEUE_RPT_8822C << BIT_SHIFT_EN_QUEUE_RPT_8822C) +#define BIT_CLEAR_EN_QUEUE_RPT_8822C(x) ((x) & (~BITS_EN_QUEUE_RPT_8822C)) +#define BIT_GET_EN_QUEUE_RPT_8822C(x) \ + (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822C) & BIT_MASK_EN_QUEUE_RPT_8822C) +#define BIT_SET_EN_QUEUE_RPT_8822C(x, v) \ + (BIT_CLEAR_EN_QUEUE_RPT_8822C(x) | BIT_EN_QUEUE_RPT_8822C(v)) + +#define BIT_EN_RTY_BK_8822C BIT(7) +#define BIT_EN_USE_INI_RAT_8822C BIT(6) +#define BIT_EN_RTS_NAV_BK_8822C BIT(5) +#define BIT_DIS_SSN_CHECK_8822C BIT(4) +#define BIT_MACID_MATCH_RTS_8822C BIT(3) +#define BIT_EN_BCN_TRXRPT_V1_8822C BIT(2) +#define BIT_R_EN_FTMRPT_V1_8822C BIT(1) +#define BIT_R_BMC_NAV_PROTECT_8822C BIT(0) + +/* 2 REG_DATAFB_SEL_8822C */ +#define BIT_BROADCAST_RTY_EN_8822C BIT(3) +#define BIT_EN_RTY_BK_COD_8822C BIT(2) + +#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C 0 +#define BIT_MASK__R_DATA_FALLBACK_SEL_8822C 0x3 +#define BIT__R_DATA_FALLBACK_SEL_8822C(x) \ + (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822C) \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C) +#define BITS__R_DATA_FALLBACK_SEL_8822C \ + (BIT_MASK__R_DATA_FALLBACK_SEL_8822C \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C) +#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8822C(x) \ + ((x) & (~BITS__R_DATA_FALLBACK_SEL_8822C)) +#define BIT_GET__R_DATA_FALLBACK_SEL_8822C(x) \ + (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C) & \ + BIT_MASK__R_DATA_FALLBACK_SEL_8822C) +#define BIT_SET__R_DATA_FALLBACK_SEL_8822C(x, v) \ + (BIT_CLEAR__R_DATA_FALLBACK_SEL_8822C(x) | \ + BIT__R_DATA_FALLBACK_SEL_8822C(v)) + +/* 2 REG_BCNQ_BDNY_V1_8822C */ + +#define BIT_SHIFT_BCNQ_PGBNDY_V1_8822C 0 +#define BIT_MASK_BCNQ_PGBNDY_V1_8822C 0xfff +#define BIT_BCNQ_PGBNDY_V1_8822C(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822C) \ + << BIT_SHIFT_BCNQ_PGBNDY_V1_8822C) +#define BITS_BCNQ_PGBNDY_V1_8822C \ + (BIT_MASK_BCNQ_PGBNDY_V1_8822C << BIT_SHIFT_BCNQ_PGBNDY_V1_8822C) +#define BIT_CLEAR_BCNQ_PGBNDY_V1_8822C(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8822C)) +#define BIT_GET_BCNQ_PGBNDY_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822C) & \ + BIT_MASK_BCNQ_PGBNDY_V1_8822C) +#define BIT_SET_BCNQ_PGBNDY_V1_8822C(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_V1_8822C(x) | BIT_BCNQ_PGBNDY_V1_8822C(v)) + +/* 2 REG_LIFETIME_EN_8822C */ +#define BIT_BT_INT_CPU_8822C BIT(7) +#define BIT_BT_INT_PTA_8822C BIT(6) +#define BIT_EN_CTRL_RTYBIT_8822C BIT(4) +#define BIT_LIFETIME_BK_EN_8822C BIT(3) +#define BIT_LIFETIME_BE_EN_8822C BIT(2) +#define BIT_LIFETIME_VI_EN_8822C BIT(1) +#define BIT_LIFETIME_VO_EN_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SPEC_SIFS_8822C */ + +#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C 8 +#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C 0xff +#define BIT_SPEC_SIFS_OFDM_PTCL_8822C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C) +#define BITS_SPEC_SIFS_OFDM_PTCL_8822C \ + (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822C(x) \ + ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8822C)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C) & \ + BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8822C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822C(x) | \ + BIT_SPEC_SIFS_OFDM_PTCL_8822C(v)) + +#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C 0 +#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C 0xff +#define BIT_SPEC_SIFS_CCK_PTCL_8822C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C) \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C) +#define BITS_SPEC_SIFS_CCK_PTCL_8822C \ + (BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822C(x) \ + ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8822C)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C) & \ + BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C) +#define BIT_SET_SPEC_SIFS_CCK_PTCL_8822C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822C(x) | \ + BIT_SPEC_SIFS_CCK_PTCL_8822C(v)) + +/* 2 REG_RETRY_LIMIT_8822C */ + +#define BIT_SHIFT_SRL_8822C 8 +#define BIT_MASK_SRL_8822C 0x3f +#define BIT_SRL_8822C(x) (((x) & BIT_MASK_SRL_8822C) << BIT_SHIFT_SRL_8822C) +#define BITS_SRL_8822C (BIT_MASK_SRL_8822C << BIT_SHIFT_SRL_8822C) +#define BIT_CLEAR_SRL_8822C(x) ((x) & (~BITS_SRL_8822C)) +#define BIT_GET_SRL_8822C(x) (((x) >> BIT_SHIFT_SRL_8822C) & BIT_MASK_SRL_8822C) +#define BIT_SET_SRL_8822C(x, v) (BIT_CLEAR_SRL_8822C(x) | BIT_SRL_8822C(v)) + +#define BIT_SHIFT_LRL_8822C 0 +#define BIT_MASK_LRL_8822C 0x3f +#define BIT_LRL_8822C(x) (((x) & BIT_MASK_LRL_8822C) << BIT_SHIFT_LRL_8822C) +#define BITS_LRL_8822C (BIT_MASK_LRL_8822C << BIT_SHIFT_LRL_8822C) +#define BIT_CLEAR_LRL_8822C(x) ((x) & (~BITS_LRL_8822C)) +#define BIT_GET_LRL_8822C(x) (((x) >> BIT_SHIFT_LRL_8822C) & BIT_MASK_LRL_8822C) +#define BIT_SET_LRL_8822C(x, v) (BIT_CLEAR_LRL_8822C(x) | BIT_LRL_8822C(v)) + +/* 2 REG_TXBF_CTRL_8822C */ +#define BIT_R_ENABLE_NDPA_8822C BIT(31) +#define BIT_USE_NDPA_PARAMETER_8822C BIT(30) +#define BIT_R_PROP_TXBF_8822C BIT(29) +#define BIT_R_EN_NDPA_INT_8822C BIT(28) +#define BIT_R_TXBF1_80M_8822C BIT(27) +#define BIT_R_TXBF1_40M_8822C BIT(26) +#define BIT_R_TXBF1_20M_8822C BIT(25) + +#define BIT_SHIFT_R_TXBF1_AID_8822C 16 +#define BIT_MASK_R_TXBF1_AID_8822C 0x1ff +#define BIT_R_TXBF1_AID_8822C(x) \ + (((x) & BIT_MASK_R_TXBF1_AID_8822C) << BIT_SHIFT_R_TXBF1_AID_8822C) +#define BITS_R_TXBF1_AID_8822C \ + (BIT_MASK_R_TXBF1_AID_8822C << BIT_SHIFT_R_TXBF1_AID_8822C) +#define BIT_CLEAR_R_TXBF1_AID_8822C(x) ((x) & (~BITS_R_TXBF1_AID_8822C)) +#define BIT_GET_R_TXBF1_AID_8822C(x) \ + (((x) >> BIT_SHIFT_R_TXBF1_AID_8822C) & BIT_MASK_R_TXBF1_AID_8822C) +#define BIT_SET_R_TXBF1_AID_8822C(x, v) \ + (BIT_CLEAR_R_TXBF1_AID_8822C(x) | BIT_R_TXBF1_AID_8822C(v)) + +#define BIT_DIS_NDP_BFEN_8822C BIT(15) +#define BIT_R_TXBCN_NOBLOCK_NDP_8822C BIT(14) +#define BIT_R_TXBF0_80M_8822C BIT(11) +#define BIT_R_TXBF0_40M_8822C BIT(10) +#define BIT_R_TXBF0_20M_8822C BIT(9) + +#define BIT_SHIFT_R_TXBF0_AID_8822C 0 +#define BIT_MASK_R_TXBF0_AID_8822C 0x1ff +#define BIT_R_TXBF0_AID_8822C(x) \ + (((x) & BIT_MASK_R_TXBF0_AID_8822C) << BIT_SHIFT_R_TXBF0_AID_8822C) +#define BITS_R_TXBF0_AID_8822C \ + (BIT_MASK_R_TXBF0_AID_8822C << BIT_SHIFT_R_TXBF0_AID_8822C) +#define BIT_CLEAR_R_TXBF0_AID_8822C(x) ((x) & (~BITS_R_TXBF0_AID_8822C)) +#define BIT_GET_R_TXBF0_AID_8822C(x) \ + (((x) >> BIT_SHIFT_R_TXBF0_AID_8822C) & BIT_MASK_R_TXBF0_AID_8822C) +#define BIT_SET_R_TXBF0_AID_8822C(x, v) \ + (BIT_CLEAR_R_TXBF0_AID_8822C(x) | BIT_R_TXBF0_AID_8822C(v)) + +/* 2 REG_DARFRC_8822C */ + +#define BIT_SHIFT_DARF_RC4_8822C 24 +#define BIT_MASK_DARF_RC4_8822C 0x1f +#define BIT_DARF_RC4_8822C(x) \ + (((x) & BIT_MASK_DARF_RC4_8822C) << BIT_SHIFT_DARF_RC4_8822C) +#define BITS_DARF_RC4_8822C \ + (BIT_MASK_DARF_RC4_8822C << BIT_SHIFT_DARF_RC4_8822C) +#define BIT_CLEAR_DARF_RC4_8822C(x) ((x) & (~BITS_DARF_RC4_8822C)) +#define BIT_GET_DARF_RC4_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_8822C) & BIT_MASK_DARF_RC4_8822C) +#define BIT_SET_DARF_RC4_8822C(x, v) \ + (BIT_CLEAR_DARF_RC4_8822C(x) | BIT_DARF_RC4_8822C(v)) + +#define BIT_SHIFT_DARF_RC3_8822C 16 +#define BIT_MASK_DARF_RC3_8822C 0x1f +#define BIT_DARF_RC3_8822C(x) \ + (((x) & BIT_MASK_DARF_RC3_8822C) << BIT_SHIFT_DARF_RC3_8822C) +#define BITS_DARF_RC3_8822C \ + (BIT_MASK_DARF_RC3_8822C << BIT_SHIFT_DARF_RC3_8822C) +#define BIT_CLEAR_DARF_RC3_8822C(x) ((x) & (~BITS_DARF_RC3_8822C)) +#define BIT_GET_DARF_RC3_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_8822C) & BIT_MASK_DARF_RC3_8822C) +#define BIT_SET_DARF_RC3_8822C(x, v) \ + (BIT_CLEAR_DARF_RC3_8822C(x) | BIT_DARF_RC3_8822C(v)) + +#define BIT_SHIFT_DARF_RC2_8822C 8 +#define BIT_MASK_DARF_RC2_8822C 0x1f +#define BIT_DARF_RC2_8822C(x) \ + (((x) & BIT_MASK_DARF_RC2_8822C) << BIT_SHIFT_DARF_RC2_8822C) +#define BITS_DARF_RC2_8822C \ + (BIT_MASK_DARF_RC2_8822C << BIT_SHIFT_DARF_RC2_8822C) +#define BIT_CLEAR_DARF_RC2_8822C(x) ((x) & (~BITS_DARF_RC2_8822C)) +#define BIT_GET_DARF_RC2_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_8822C) & BIT_MASK_DARF_RC2_8822C) +#define BIT_SET_DARF_RC2_8822C(x, v) \ + (BIT_CLEAR_DARF_RC2_8822C(x) | BIT_DARF_RC2_8822C(v)) + +#define BIT_SHIFT_DARF_RC1_8822C 0 +#define BIT_MASK_DARF_RC1_8822C 0x1f +#define BIT_DARF_RC1_8822C(x) \ + (((x) & BIT_MASK_DARF_RC1_8822C) << BIT_SHIFT_DARF_RC1_8822C) +#define BITS_DARF_RC1_8822C \ + (BIT_MASK_DARF_RC1_8822C << BIT_SHIFT_DARF_RC1_8822C) +#define BIT_CLEAR_DARF_RC1_8822C(x) ((x) & (~BITS_DARF_RC1_8822C)) +#define BIT_GET_DARF_RC1_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_8822C) & BIT_MASK_DARF_RC1_8822C) +#define BIT_SET_DARF_RC1_8822C(x, v) \ + (BIT_CLEAR_DARF_RC1_8822C(x) | BIT_DARF_RC1_8822C(v)) + +/* 2 REG_DARFRCH_8822C */ + +#define BIT_SHIFT_DARF_RC8_V1_8822C 24 +#define BIT_MASK_DARF_RC8_V1_8822C 0x1f +#define BIT_DARF_RC8_V1_8822C(x) \ + (((x) & BIT_MASK_DARF_RC8_V1_8822C) << BIT_SHIFT_DARF_RC8_V1_8822C) +#define BITS_DARF_RC8_V1_8822C \ + (BIT_MASK_DARF_RC8_V1_8822C << BIT_SHIFT_DARF_RC8_V1_8822C) +#define BIT_CLEAR_DARF_RC8_V1_8822C(x) ((x) & (~BITS_DARF_RC8_V1_8822C)) +#define BIT_GET_DARF_RC8_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_V1_8822C) & BIT_MASK_DARF_RC8_V1_8822C) +#define BIT_SET_DARF_RC8_V1_8822C(x, v) \ + (BIT_CLEAR_DARF_RC8_V1_8822C(x) | BIT_DARF_RC8_V1_8822C(v)) + +#define BIT_SHIFT_DARF_RC7_V1_8822C 16 +#define BIT_MASK_DARF_RC7_V1_8822C 0x1f +#define BIT_DARF_RC7_V1_8822C(x) \ + (((x) & BIT_MASK_DARF_RC7_V1_8822C) << BIT_SHIFT_DARF_RC7_V1_8822C) +#define BITS_DARF_RC7_V1_8822C \ + (BIT_MASK_DARF_RC7_V1_8822C << BIT_SHIFT_DARF_RC7_V1_8822C) +#define BIT_CLEAR_DARF_RC7_V1_8822C(x) ((x) & (~BITS_DARF_RC7_V1_8822C)) +#define BIT_GET_DARF_RC7_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_V1_8822C) & BIT_MASK_DARF_RC7_V1_8822C) +#define BIT_SET_DARF_RC7_V1_8822C(x, v) \ + (BIT_CLEAR_DARF_RC7_V1_8822C(x) | BIT_DARF_RC7_V1_8822C(v)) + +#define BIT_SHIFT_DARF_RC6_V1_8822C 8 +#define BIT_MASK_DARF_RC6_V1_8822C 0x1f +#define BIT_DARF_RC6_V1_8822C(x) \ + (((x) & BIT_MASK_DARF_RC6_V1_8822C) << BIT_SHIFT_DARF_RC6_V1_8822C) +#define BITS_DARF_RC6_V1_8822C \ + (BIT_MASK_DARF_RC6_V1_8822C << BIT_SHIFT_DARF_RC6_V1_8822C) +#define BIT_CLEAR_DARF_RC6_V1_8822C(x) ((x) & (~BITS_DARF_RC6_V1_8822C)) +#define BIT_GET_DARF_RC6_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_V1_8822C) & BIT_MASK_DARF_RC6_V1_8822C) +#define BIT_SET_DARF_RC6_V1_8822C(x, v) \ + (BIT_CLEAR_DARF_RC6_V1_8822C(x) | BIT_DARF_RC6_V1_8822C(v)) + +#define BIT_SHIFT_DARF_RC5_V1_8822C 0 +#define BIT_MASK_DARF_RC5_V1_8822C 0x1f +#define BIT_DARF_RC5_V1_8822C(x) \ + (((x) & BIT_MASK_DARF_RC5_V1_8822C) << BIT_SHIFT_DARF_RC5_V1_8822C) +#define BITS_DARF_RC5_V1_8822C \ + (BIT_MASK_DARF_RC5_V1_8822C << BIT_SHIFT_DARF_RC5_V1_8822C) +#define BIT_CLEAR_DARF_RC5_V1_8822C(x) ((x) & (~BITS_DARF_RC5_V1_8822C)) +#define BIT_GET_DARF_RC5_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_V1_8822C) & BIT_MASK_DARF_RC5_V1_8822C) +#define BIT_SET_DARF_RC5_V1_8822C(x, v) \ + (BIT_CLEAR_DARF_RC5_V1_8822C(x) | BIT_DARF_RC5_V1_8822C(v)) + +/* 2 REG_RARFRC_8822C */ + +#define BIT_SHIFT_RARF_RC4_8822C 24 +#define BIT_MASK_RARF_RC4_8822C 0x1f +#define BIT_RARF_RC4_8822C(x) \ + (((x) & BIT_MASK_RARF_RC4_8822C) << BIT_SHIFT_RARF_RC4_8822C) +#define BITS_RARF_RC4_8822C \ + (BIT_MASK_RARF_RC4_8822C << BIT_SHIFT_RARF_RC4_8822C) +#define BIT_CLEAR_RARF_RC4_8822C(x) ((x) & (~BITS_RARF_RC4_8822C)) +#define BIT_GET_RARF_RC4_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC4_8822C) & BIT_MASK_RARF_RC4_8822C) +#define BIT_SET_RARF_RC4_8822C(x, v) \ + (BIT_CLEAR_RARF_RC4_8822C(x) | BIT_RARF_RC4_8822C(v)) + +#define BIT_SHIFT_RARF_RC3_8822C 16 +#define BIT_MASK_RARF_RC3_8822C 0x1f +#define BIT_RARF_RC3_8822C(x) \ + (((x) & BIT_MASK_RARF_RC3_8822C) << BIT_SHIFT_RARF_RC3_8822C) +#define BITS_RARF_RC3_8822C \ + (BIT_MASK_RARF_RC3_8822C << BIT_SHIFT_RARF_RC3_8822C) +#define BIT_CLEAR_RARF_RC3_8822C(x) ((x) & (~BITS_RARF_RC3_8822C)) +#define BIT_GET_RARF_RC3_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC3_8822C) & BIT_MASK_RARF_RC3_8822C) +#define BIT_SET_RARF_RC3_8822C(x, v) \ + (BIT_CLEAR_RARF_RC3_8822C(x) | BIT_RARF_RC3_8822C(v)) + +#define BIT_SHIFT_RARF_RC2_8822C 8 +#define BIT_MASK_RARF_RC2_8822C 0x1f +#define BIT_RARF_RC2_8822C(x) \ + (((x) & BIT_MASK_RARF_RC2_8822C) << BIT_SHIFT_RARF_RC2_8822C) +#define BITS_RARF_RC2_8822C \ + (BIT_MASK_RARF_RC2_8822C << BIT_SHIFT_RARF_RC2_8822C) +#define BIT_CLEAR_RARF_RC2_8822C(x) ((x) & (~BITS_RARF_RC2_8822C)) +#define BIT_GET_RARF_RC2_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC2_8822C) & BIT_MASK_RARF_RC2_8822C) +#define BIT_SET_RARF_RC2_8822C(x, v) \ + (BIT_CLEAR_RARF_RC2_8822C(x) | BIT_RARF_RC2_8822C(v)) + +#define BIT_SHIFT_RARF_RC1_8822C 0 +#define BIT_MASK_RARF_RC1_8822C 0x1f +#define BIT_RARF_RC1_8822C(x) \ + (((x) & BIT_MASK_RARF_RC1_8822C) << BIT_SHIFT_RARF_RC1_8822C) +#define BITS_RARF_RC1_8822C \ + (BIT_MASK_RARF_RC1_8822C << BIT_SHIFT_RARF_RC1_8822C) +#define BIT_CLEAR_RARF_RC1_8822C(x) ((x) & (~BITS_RARF_RC1_8822C)) +#define BIT_GET_RARF_RC1_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC1_8822C) & BIT_MASK_RARF_RC1_8822C) +#define BIT_SET_RARF_RC1_8822C(x, v) \ + (BIT_CLEAR_RARF_RC1_8822C(x) | BIT_RARF_RC1_8822C(v)) + +/* 2 REG_RARFRCH_8822C */ + +#define BIT_SHIFT_RARF_RC8_V1_8822C 24 +#define BIT_MASK_RARF_RC8_V1_8822C 0x1f +#define BIT_RARF_RC8_V1_8822C(x) \ + (((x) & BIT_MASK_RARF_RC8_V1_8822C) << BIT_SHIFT_RARF_RC8_V1_8822C) +#define BITS_RARF_RC8_V1_8822C \ + (BIT_MASK_RARF_RC8_V1_8822C << BIT_SHIFT_RARF_RC8_V1_8822C) +#define BIT_CLEAR_RARF_RC8_V1_8822C(x) ((x) & (~BITS_RARF_RC8_V1_8822C)) +#define BIT_GET_RARF_RC8_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC8_V1_8822C) & BIT_MASK_RARF_RC8_V1_8822C) +#define BIT_SET_RARF_RC8_V1_8822C(x, v) \ + (BIT_CLEAR_RARF_RC8_V1_8822C(x) | BIT_RARF_RC8_V1_8822C(v)) + +#define BIT_SHIFT_RARF_RC7_V1_8822C 16 +#define BIT_MASK_RARF_RC7_V1_8822C 0x1f +#define BIT_RARF_RC7_V1_8822C(x) \ + (((x) & BIT_MASK_RARF_RC7_V1_8822C) << BIT_SHIFT_RARF_RC7_V1_8822C) +#define BITS_RARF_RC7_V1_8822C \ + (BIT_MASK_RARF_RC7_V1_8822C << BIT_SHIFT_RARF_RC7_V1_8822C) +#define BIT_CLEAR_RARF_RC7_V1_8822C(x) ((x) & (~BITS_RARF_RC7_V1_8822C)) +#define BIT_GET_RARF_RC7_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC7_V1_8822C) & BIT_MASK_RARF_RC7_V1_8822C) +#define BIT_SET_RARF_RC7_V1_8822C(x, v) \ + (BIT_CLEAR_RARF_RC7_V1_8822C(x) | BIT_RARF_RC7_V1_8822C(v)) + +#define BIT_SHIFT_RARF_RC6_V1_8822C 8 +#define BIT_MASK_RARF_RC6_V1_8822C 0x1f +#define BIT_RARF_RC6_V1_8822C(x) \ + (((x) & BIT_MASK_RARF_RC6_V1_8822C) << BIT_SHIFT_RARF_RC6_V1_8822C) +#define BITS_RARF_RC6_V1_8822C \ + (BIT_MASK_RARF_RC6_V1_8822C << BIT_SHIFT_RARF_RC6_V1_8822C) +#define BIT_CLEAR_RARF_RC6_V1_8822C(x) ((x) & (~BITS_RARF_RC6_V1_8822C)) +#define BIT_GET_RARF_RC6_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC6_V1_8822C) & BIT_MASK_RARF_RC6_V1_8822C) +#define BIT_SET_RARF_RC6_V1_8822C(x, v) \ + (BIT_CLEAR_RARF_RC6_V1_8822C(x) | BIT_RARF_RC6_V1_8822C(v)) + +#define BIT_SHIFT_RARF_RC5_V1_8822C 0 +#define BIT_MASK_RARF_RC5_V1_8822C 0x1f +#define BIT_RARF_RC5_V1_8822C(x) \ + (((x) & BIT_MASK_RARF_RC5_V1_8822C) << BIT_SHIFT_RARF_RC5_V1_8822C) +#define BITS_RARF_RC5_V1_8822C \ + (BIT_MASK_RARF_RC5_V1_8822C << BIT_SHIFT_RARF_RC5_V1_8822C) +#define BIT_CLEAR_RARF_RC5_V1_8822C(x) ((x) & (~BITS_RARF_RC5_V1_8822C)) +#define BIT_GET_RARF_RC5_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC5_V1_8822C) & BIT_MASK_RARF_RC5_V1_8822C) +#define BIT_SET_RARF_RC5_V1_8822C(x, v) \ + (BIT_CLEAR_RARF_RC5_V1_8822C(x) | BIT_RARF_RC5_V1_8822C(v)) + +/* 2 REG_RRSR_8822C */ + +#define BIT_SHIFT_RRSR_RSC_8822C 21 +#define BIT_MASK_RRSR_RSC_8822C 0x3 +#define BIT_RRSR_RSC_8822C(x) \ + (((x) & BIT_MASK_RRSR_RSC_8822C) << BIT_SHIFT_RRSR_RSC_8822C) +#define BITS_RRSR_RSC_8822C \ + (BIT_MASK_RRSR_RSC_8822C << BIT_SHIFT_RRSR_RSC_8822C) +#define BIT_CLEAR_RRSR_RSC_8822C(x) ((x) & (~BITS_RRSR_RSC_8822C)) +#define BIT_GET_RRSR_RSC_8822C(x) \ + (((x) >> BIT_SHIFT_RRSR_RSC_8822C) & BIT_MASK_RRSR_RSC_8822C) +#define BIT_SET_RRSR_RSC_8822C(x, v) \ + (BIT_CLEAR_RRSR_RSC_8822C(x) | BIT_RRSR_RSC_8822C(v)) + +#define BIT_SHIFT_RRSC_BITMAP_8822C 0 +#define BIT_MASK_RRSC_BITMAP_8822C 0xfffff +#define BIT_RRSC_BITMAP_8822C(x) \ + (((x) & BIT_MASK_RRSC_BITMAP_8822C) << BIT_SHIFT_RRSC_BITMAP_8822C) +#define BITS_RRSC_BITMAP_8822C \ + (BIT_MASK_RRSC_BITMAP_8822C << BIT_SHIFT_RRSC_BITMAP_8822C) +#define BIT_CLEAR_RRSC_BITMAP_8822C(x) ((x) & (~BITS_RRSC_BITMAP_8822C)) +#define BIT_GET_RRSC_BITMAP_8822C(x) \ + (((x) >> BIT_SHIFT_RRSC_BITMAP_8822C) & BIT_MASK_RRSC_BITMAP_8822C) +#define BIT_SET_RRSC_BITMAP_8822C(x, v) \ + (BIT_CLEAR_RRSC_BITMAP_8822C(x) | BIT_RRSC_BITMAP_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ARFR0_8822C */ + +#define BIT_SHIFT_ARFRL0_8822C 0 +#define BIT_MASK_ARFRL0_8822C 0xffffffffL +#define BIT_ARFRL0_8822C(x) \ + (((x) & BIT_MASK_ARFRL0_8822C) << BIT_SHIFT_ARFRL0_8822C) +#define BITS_ARFRL0_8822C (BIT_MASK_ARFRL0_8822C << BIT_SHIFT_ARFRL0_8822C) +#define BIT_CLEAR_ARFRL0_8822C(x) ((x) & (~BITS_ARFRL0_8822C)) +#define BIT_GET_ARFRL0_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRL0_8822C) & BIT_MASK_ARFRL0_8822C) +#define BIT_SET_ARFRL0_8822C(x, v) \ + (BIT_CLEAR_ARFRL0_8822C(x) | BIT_ARFRL0_8822C(v)) + +/* 2 REG_ARFRH0_8822C */ + +#define BIT_SHIFT_ARFRH0_8822C 0 +#define BIT_MASK_ARFRH0_8822C 0xffffffffL +#define BIT_ARFRH0_8822C(x) \ + (((x) & BIT_MASK_ARFRH0_8822C) << BIT_SHIFT_ARFRH0_8822C) +#define BITS_ARFRH0_8822C (BIT_MASK_ARFRH0_8822C << BIT_SHIFT_ARFRH0_8822C) +#define BIT_CLEAR_ARFRH0_8822C(x) ((x) & (~BITS_ARFRH0_8822C)) +#define BIT_GET_ARFRH0_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRH0_8822C) & BIT_MASK_ARFRH0_8822C) +#define BIT_SET_ARFRH0_8822C(x, v) \ + (BIT_CLEAR_ARFRH0_8822C(x) | BIT_ARFRH0_8822C(v)) + +/* 2 REG_ARFR1_V1_8822C */ + +#define BIT_SHIFT_ARFRL1_8822C 0 +#define BIT_MASK_ARFRL1_8822C 0xffffffffL +#define BIT_ARFRL1_8822C(x) \ + (((x) & BIT_MASK_ARFRL1_8822C) << BIT_SHIFT_ARFRL1_8822C) +#define BITS_ARFRL1_8822C (BIT_MASK_ARFRL1_8822C << BIT_SHIFT_ARFRL1_8822C) +#define BIT_CLEAR_ARFRL1_8822C(x) ((x) & (~BITS_ARFRL1_8822C)) +#define BIT_GET_ARFRL1_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRL1_8822C) & BIT_MASK_ARFRL1_8822C) +#define BIT_SET_ARFRL1_8822C(x, v) \ + (BIT_CLEAR_ARFRL1_8822C(x) | BIT_ARFRL1_8822C(v)) + +/* 2 REG_ARFRH1_V1_8822C */ + +#define BIT_SHIFT_ARFRH1_8822C 0 +#define BIT_MASK_ARFRH1_8822C 0xffffffffL +#define BIT_ARFRH1_8822C(x) \ + (((x) & BIT_MASK_ARFRH1_8822C) << BIT_SHIFT_ARFRH1_8822C) +#define BITS_ARFRH1_8822C (BIT_MASK_ARFRH1_8822C << BIT_SHIFT_ARFRH1_8822C) +#define BIT_CLEAR_ARFRH1_8822C(x) ((x) & (~BITS_ARFRH1_8822C)) +#define BIT_GET_ARFRH1_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRH1_8822C) & BIT_MASK_ARFRH1_8822C) +#define BIT_SET_ARFRH1_8822C(x, v) \ + (BIT_CLEAR_ARFRH1_8822C(x) | BIT_ARFRH1_8822C(v)) + +/* 2 REG_CCK_CHECK_8822C */ +#define BIT_CHECK_CCK_EN_8822C BIT(7) +#define BIT_EN_BCN_PKT_REL_8822C BIT(6) +#define BIT_BCN_PORT_SEL_8822C BIT(5) +#define BIT_MOREDATA_BYPASS_8822C BIT(4) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_8822C BIT(3) +#define BIT_R_EN_SET_MOREDATA_8822C BIT(2) +#define BIT__R_DIS_CLEAR_MACID_RELEASE_8822C BIT(1) +#define BIT__R_MACID_RELEASE_EN_8822C BIT(0) + +/* 2 REG_AMPDU_MAX_TIME_V1_8822C */ + +#define BIT_SHIFT_AMPDU_MAX_TIME_8822C 0 +#define BIT_MASK_AMPDU_MAX_TIME_8822C 0xff +#define BIT_AMPDU_MAX_TIME_8822C(x) \ + (((x) & BIT_MASK_AMPDU_MAX_TIME_8822C) \ + << BIT_SHIFT_AMPDU_MAX_TIME_8822C) +#define BITS_AMPDU_MAX_TIME_8822C \ + (BIT_MASK_AMPDU_MAX_TIME_8822C << BIT_SHIFT_AMPDU_MAX_TIME_8822C) +#define BIT_CLEAR_AMPDU_MAX_TIME_8822C(x) ((x) & (~BITS_AMPDU_MAX_TIME_8822C)) +#define BIT_GET_AMPDU_MAX_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822C) & \ + BIT_MASK_AMPDU_MAX_TIME_8822C) +#define BIT_SET_AMPDU_MAX_TIME_8822C(x, v) \ + (BIT_CLEAR_AMPDU_MAX_TIME_8822C(x) | BIT_AMPDU_MAX_TIME_8822C(v)) + +/* 2 REG_BCNQ1_BDNY_V1_8822C */ + +#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C 0 +#define BIT_MASK_BCNQ1_PGBNDY_V1_8822C 0xfff +#define BIT_BCNQ1_PGBNDY_V1_8822C(x) \ + (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822C) \ + << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C) +#define BITS_BCNQ1_PGBNDY_V1_8822C \ + (BIT_MASK_BCNQ1_PGBNDY_V1_8822C << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C) +#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8822C(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8822C)) +#define BIT_GET_BCNQ1_PGBNDY_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C) & \ + BIT_MASK_BCNQ1_PGBNDY_V1_8822C) +#define BIT_SET_BCNQ1_PGBNDY_V1_8822C(x, v) \ + (BIT_CLEAR_BCNQ1_PGBNDY_V1_8822C(x) | BIT_BCNQ1_PGBNDY_V1_8822C(v)) + +/* 2 REG_AMPDU_MAX_LENGTH_HT_8822C */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C 0xffff +#define BIT_AMPDU_MAX_LENGTH_HT_8822C(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C) +#define BITS_AMPDU_MAX_LENGTH_HT_8822C \ + (BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8822C(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_HT_8822C)) +#define BIT_GET_AMPDU_MAX_LENGTH_HT_8822C(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C) & \ + BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C) +#define BIT_SET_AMPDU_MAX_LENGTH_HT_8822C(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8822C(x) | \ + BIT_AMPDU_MAX_LENGTH_HT_8822C(v)) + +/* 2 REG_ACQ_STOP_8822C */ +#define BIT_AC7Q_STOP_8822C BIT(7) +#define BIT_AC6Q_STOP_8822C BIT(6) +#define BIT_AC5Q_STOP_8822C BIT(5) +#define BIT_AC4Q_STOP_8822C BIT(4) +#define BIT_AC3Q_STOP_8822C BIT(3) +#define BIT_AC2Q_STOP_8822C BIT(2) +#define BIT_AC1Q_STOP_8822C BIT(1) +#define BIT_AC0Q_STOP_8822C BIT(0) + +/* 2 REG_NDPA_RATE_8822C */ + +#define BIT_SHIFT_R_NDPA_RATE_V1_8822C 0 +#define BIT_MASK_R_NDPA_RATE_V1_8822C 0xff +#define BIT_R_NDPA_RATE_V1_8822C(x) \ + (((x) & BIT_MASK_R_NDPA_RATE_V1_8822C) \ + << BIT_SHIFT_R_NDPA_RATE_V1_8822C) +#define BITS_R_NDPA_RATE_V1_8822C \ + (BIT_MASK_R_NDPA_RATE_V1_8822C << BIT_SHIFT_R_NDPA_RATE_V1_8822C) +#define BIT_CLEAR_R_NDPA_RATE_V1_8822C(x) ((x) & (~BITS_R_NDPA_RATE_V1_8822C)) +#define BIT_GET_R_NDPA_RATE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822C) & \ + BIT_MASK_R_NDPA_RATE_V1_8822C) +#define BIT_SET_R_NDPA_RATE_V1_8822C(x, v) \ + (BIT_CLEAR_R_NDPA_RATE_V1_8822C(x) | BIT_R_NDPA_RATE_V1_8822C(v)) + +/* 2 REG_TX_HANG_CTRL_8822C */ +#define BIT_R_EN_GNT_BT_AWAKE_8822C BIT(3) +#define BIT_EN_EOF_V1_8822C BIT(2) +#define BIT_DIS_OQT_BLOCK_8822C BIT(1) +#define BIT_SEARCH_QUEUE_EN_8822C BIT(0) + +/* 2 REG_NDPA_OPT_CTRL_8822C */ +#define BIT_R_DIS_MACID_RELEASE_RTY_8822C BIT(5) + +#define BIT_SHIFT_BW_SIGTA_8822C 3 +#define BIT_MASK_BW_SIGTA_8822C 0x3 +#define BIT_BW_SIGTA_8822C(x) \ + (((x) & BIT_MASK_BW_SIGTA_8822C) << BIT_SHIFT_BW_SIGTA_8822C) +#define BITS_BW_SIGTA_8822C \ + (BIT_MASK_BW_SIGTA_8822C << BIT_SHIFT_BW_SIGTA_8822C) +#define BIT_CLEAR_BW_SIGTA_8822C(x) ((x) & (~BITS_BW_SIGTA_8822C)) +#define BIT_GET_BW_SIGTA_8822C(x) \ + (((x) >> BIT_SHIFT_BW_SIGTA_8822C) & BIT_MASK_BW_SIGTA_8822C) +#define BIT_SET_BW_SIGTA_8822C(x, v) \ + (BIT_CLEAR_BW_SIGTA_8822C(x) | BIT_BW_SIGTA_8822C(v)) + +#define BIT_EN_BAR_SIGTA_8822C BIT(2) + +#define BIT_SHIFT_R_NDPA_BW_8822C 0 +#define BIT_MASK_R_NDPA_BW_8822C 0x3 +#define BIT_R_NDPA_BW_8822C(x) \ + (((x) & BIT_MASK_R_NDPA_BW_8822C) << BIT_SHIFT_R_NDPA_BW_8822C) +#define BITS_R_NDPA_BW_8822C \ + (BIT_MASK_R_NDPA_BW_8822C << BIT_SHIFT_R_NDPA_BW_8822C) +#define BIT_CLEAR_R_NDPA_BW_8822C(x) ((x) & (~BITS_R_NDPA_BW_8822C)) +#define BIT_GET_R_NDPA_BW_8822C(x) \ + (((x) >> BIT_SHIFT_R_NDPA_BW_8822C) & BIT_MASK_R_NDPA_BW_8822C) +#define BIT_SET_R_NDPA_BW_8822C(x, v) \ + (BIT_CLEAR_R_NDPA_BW_8822C(x) | BIT_R_NDPA_BW_8822C(v)) + +/* 2 REG_AMPDU_MAX_LENGTH_VHT_8822C */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C 0xfffff +#define BIT_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C) +#define BITS_AMPDU_MAX_LENGTH_VHT_V1_8822C \ + (BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_V1_8822C)) +#define BIT_GET_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C) & \ + BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C) +#define BIT_SET_AMPDU_MAX_LENGTH_VHT_V1_8822C(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) | \ + BIT_AMPDU_MAX_LENGTH_VHT_V1_8822C(v)) + +/* 2 REG_RD_RESP_PKT_TH_8822C */ + +#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C 0 +#define BIT_MASK_RD_RESP_PKT_TH_V1_8822C 0x3f +#define BIT_RD_RESP_PKT_TH_V1_8822C(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822C) \ + << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C) +#define BITS_RD_RESP_PKT_TH_V1_8822C \ + (BIT_MASK_RD_RESP_PKT_TH_V1_8822C << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8822C(x) \ + ((x) & (~BITS_RD_RESP_PKT_TH_V1_8822C)) +#define BIT_GET_RD_RESP_PKT_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C) & \ + BIT_MASK_RD_RESP_PKT_TH_V1_8822C) +#define BIT_SET_RD_RESP_PKT_TH_V1_8822C(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH_V1_8822C(x) | BIT_RD_RESP_PKT_TH_V1_8822C(v)) + +/* 2 REG_CMDQ_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_CMDQ_V1_8822C 0x7f +#define BIT_QUEUEMACID_CMDQ_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C) +#define BITS_QUEUEMACID_CMDQ_V1_8822C \ + (BIT_MASK_QUEUEMACID_CMDQ_V1_8822C \ + << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_CMDQ_V1_8822C)) +#define BIT_GET_QUEUEMACID_CMDQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C) & \ + BIT_MASK_QUEUEMACID_CMDQ_V1_8822C) +#define BIT_SET_QUEUEMACID_CMDQ_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822C(x) | \ + BIT_QUEUEMACID_CMDQ_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C 23 +#define BIT_MASK_QUEUEAC_CMDQ_V1_8822C 0x3 +#define BIT_QUEUEAC_CMDQ_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822C) \ + << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C) +#define BITS_QUEUEAC_CMDQ_V1_8822C \ + (BIT_MASK_QUEUEAC_CMDQ_V1_8822C << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C) +#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8822C)) +#define BIT_GET_QUEUEAC_CMDQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C) & \ + BIT_MASK_QUEUEAC_CMDQ_V1_8822C) +#define BIT_SET_QUEUEAC_CMDQ_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_CMDQ_V1_8822C(x) | BIT_QUEUEAC_CMDQ_V1_8822C(v)) + +#define BIT_TIDEMPTY_CMDQ_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q4_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q4_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) +#define BITS_TAIL_PKT_Q4_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q4_V2_8822C << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q4_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q4_V2_8822C) +#define BIT_SET_TAIL_PKT_Q4_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) | BIT_TAIL_PKT_Q4_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_CMDQ_V1_8822C 0x7ff +#define BIT_HEAD_PKT_CMDQ_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C) +#define BITS_HEAD_PKT_CMDQ_V1_8822C \ + (BIT_MASK_HEAD_PKT_CMDQ_V1_8822C << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822C(x) \ + ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8822C)) +#define BIT_GET_HEAD_PKT_CMDQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C) & \ + BIT_MASK_HEAD_PKT_CMDQ_V1_8822C) +#define BIT_SET_HEAD_PKT_CMDQ_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822C(x) | BIT_HEAD_PKT_CMDQ_V1_8822C(v)) + +/* 2 REG_Q4_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q4_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q4_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q4_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q4_V1_8822C) +#define BITS_QUEUEMACID_Q4_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q4_V1_8822C << BIT_SHIFT_QUEUEMACID_Q4_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q4_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q4_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q4_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q4_V1_8822C) +#define BIT_SET_QUEUEMACID_Q4_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q4_V1_8822C(x) | BIT_QUEUEMACID_Q4_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q4_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q4_V1_8822C 0x3 +#define BIT_QUEUEAC_Q4_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q4_V1_8822C) << BIT_SHIFT_QUEUEAC_Q4_V1_8822C) +#define BITS_QUEUEAC_Q4_V1_8822C \ + (BIT_MASK_QUEUEAC_Q4_V1_8822C << BIT_SHIFT_QUEUEAC_Q4_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q4_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8822C)) +#define BIT_GET_QUEUEAC_Q4_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822C) & BIT_MASK_QUEUEAC_Q4_V1_8822C) +#define BIT_SET_QUEUEAC_Q4_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q4_V1_8822C(x) | BIT_QUEUEAC_Q4_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q4_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q4_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q4_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) +#define BITS_TAIL_PKT_Q4_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q4_V2_8822C << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q4_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q4_V2_8822C) +#define BIT_SET_TAIL_PKT_Q4_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) | BIT_TAIL_PKT_Q4_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q4_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q4_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q4_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q4_V1_8822C) +#define BITS_HEAD_PKT_Q4_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q4_V1_8822C << BIT_SHIFT_HEAD_PKT_Q4_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q4_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q4_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q4_V1_8822C) +#define BIT_SET_HEAD_PKT_Q4_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q4_V1_8822C(x) | BIT_HEAD_PKT_Q4_V1_8822C(v)) + +/* 2 REG_Q5_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q5_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q5_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q5_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q5_V1_8822C) +#define BITS_QUEUEMACID_Q5_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q5_V1_8822C << BIT_SHIFT_QUEUEMACID_Q5_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q5_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q5_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q5_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q5_V1_8822C) +#define BIT_SET_QUEUEMACID_Q5_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q5_V1_8822C(x) | BIT_QUEUEMACID_Q5_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q5_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q5_V1_8822C 0x3 +#define BIT_QUEUEAC_Q5_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q5_V1_8822C) << BIT_SHIFT_QUEUEAC_Q5_V1_8822C) +#define BITS_QUEUEAC_Q5_V1_8822C \ + (BIT_MASK_QUEUEAC_Q5_V1_8822C << BIT_SHIFT_QUEUEAC_Q5_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q5_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8822C)) +#define BIT_GET_QUEUEAC_Q5_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822C) & BIT_MASK_QUEUEAC_Q5_V1_8822C) +#define BIT_SET_QUEUEAC_Q5_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q5_V1_8822C(x) | BIT_QUEUEAC_Q5_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q5_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q5_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q5_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q5_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q5_V2_8822C) +#define BITS_TAIL_PKT_Q5_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q5_V2_8822C << BIT_SHIFT_TAIL_PKT_Q5_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q5_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q5_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q5_V2_8822C) +#define BIT_SET_TAIL_PKT_Q5_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q5_V2_8822C(x) | BIT_TAIL_PKT_Q5_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q5_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q5_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q5_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q5_V1_8822C) +#define BITS_HEAD_PKT_Q5_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q5_V1_8822C << BIT_SHIFT_HEAD_PKT_Q5_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q5_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q5_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q5_V1_8822C) +#define BIT_SET_HEAD_PKT_Q5_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q5_V1_8822C(x) | BIT_HEAD_PKT_Q5_V1_8822C(v)) + +/* 2 REG_Q6_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q6_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q6_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q6_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q6_V1_8822C) +#define BITS_QUEUEMACID_Q6_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q6_V1_8822C << BIT_SHIFT_QUEUEMACID_Q6_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q6_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q6_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q6_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q6_V1_8822C) +#define BIT_SET_QUEUEMACID_Q6_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q6_V1_8822C(x) | BIT_QUEUEMACID_Q6_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q6_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q6_V1_8822C 0x3 +#define BIT_QUEUEAC_Q6_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q6_V1_8822C) << BIT_SHIFT_QUEUEAC_Q6_V1_8822C) +#define BITS_QUEUEAC_Q6_V1_8822C \ + (BIT_MASK_QUEUEAC_Q6_V1_8822C << BIT_SHIFT_QUEUEAC_Q6_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q6_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8822C)) +#define BIT_GET_QUEUEAC_Q6_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822C) & BIT_MASK_QUEUEAC_Q6_V1_8822C) +#define BIT_SET_QUEUEAC_Q6_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q6_V1_8822C(x) | BIT_QUEUEAC_Q6_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q6_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q6_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q6_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q6_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q6_V2_8822C) +#define BITS_TAIL_PKT_Q6_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q6_V2_8822C << BIT_SHIFT_TAIL_PKT_Q6_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q6_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q6_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q6_V2_8822C) +#define BIT_SET_TAIL_PKT_Q6_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q6_V2_8822C(x) | BIT_TAIL_PKT_Q6_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q6_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q6_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q6_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q6_V1_8822C) +#define BITS_HEAD_PKT_Q6_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q6_V1_8822C << BIT_SHIFT_HEAD_PKT_Q6_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q6_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q6_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q6_V1_8822C) +#define BIT_SET_HEAD_PKT_Q6_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q6_V1_8822C(x) | BIT_HEAD_PKT_Q6_V1_8822C(v)) + +/* 2 REG_Q7_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q7_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q7_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q7_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q7_V1_8822C) +#define BITS_QUEUEMACID_Q7_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q7_V1_8822C << BIT_SHIFT_QUEUEMACID_Q7_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q7_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q7_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q7_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q7_V1_8822C) +#define BIT_SET_QUEUEMACID_Q7_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q7_V1_8822C(x) | BIT_QUEUEMACID_Q7_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q7_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q7_V1_8822C 0x3 +#define BIT_QUEUEAC_Q7_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q7_V1_8822C) << BIT_SHIFT_QUEUEAC_Q7_V1_8822C) +#define BITS_QUEUEAC_Q7_V1_8822C \ + (BIT_MASK_QUEUEAC_Q7_V1_8822C << BIT_SHIFT_QUEUEAC_Q7_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q7_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8822C)) +#define BIT_GET_QUEUEAC_Q7_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822C) & BIT_MASK_QUEUEAC_Q7_V1_8822C) +#define BIT_SET_QUEUEAC_Q7_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q7_V1_8822C(x) | BIT_QUEUEAC_Q7_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q7_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q7_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q7_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q7_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q7_V2_8822C) +#define BITS_TAIL_PKT_Q7_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q7_V2_8822C << BIT_SHIFT_TAIL_PKT_Q7_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q7_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q7_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q7_V2_8822C) +#define BIT_SET_TAIL_PKT_Q7_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q7_V2_8822C(x) | BIT_TAIL_PKT_Q7_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q7_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q7_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q7_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q7_V1_8822C) +#define BITS_HEAD_PKT_Q7_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q7_V1_8822C << BIT_SHIFT_HEAD_PKT_Q7_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q7_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q7_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q7_V1_8822C) +#define BIT_SET_HEAD_PKT_Q7_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q7_V1_8822C(x) | BIT_HEAD_PKT_Q7_V1_8822C(v)) + +/* 2 REG_WMAC_LBK_BUF_HD_V1_8822C */ + +#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C 0 +#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C 0xfff +#define BIT_WMAC_LBK_BUF_HEAD_V1_8822C(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C) \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C) +#define BITS_WMAC_LBK_BUF_HEAD_V1_8822C \ + (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822C(x) \ + ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8822C)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C) & \ + BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8822C(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822C(x) | \ + BIT_WMAC_LBK_BUF_HEAD_V1_8822C(v)) + +/* 2 REG_MGQ_BDNY_V1_8822C */ + +#define BIT_SHIFT_MGQ_PGBNDY_V1_8822C 0 +#define BIT_MASK_MGQ_PGBNDY_V1_8822C 0xfff +#define BIT_MGQ_PGBNDY_V1_8822C(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V1_8822C) << BIT_SHIFT_MGQ_PGBNDY_V1_8822C) +#define BITS_MGQ_PGBNDY_V1_8822C \ + (BIT_MASK_MGQ_PGBNDY_V1_8822C << BIT_SHIFT_MGQ_PGBNDY_V1_8822C) +#define BIT_CLEAR_MGQ_PGBNDY_V1_8822C(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8822C)) +#define BIT_GET_MGQ_PGBNDY_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822C) & BIT_MASK_MGQ_PGBNDY_V1_8822C) +#define BIT_SET_MGQ_PGBNDY_V1_8822C(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V1_8822C(x) | BIT_MGQ_PGBNDY_V1_8822C(v)) + +/* 2 REG_TXRPT_CTRL_8822C */ + +#define BIT_SHIFT_TRXRPT_TIMER_TH_8822C 24 +#define BIT_MASK_TRXRPT_TIMER_TH_8822C 0xff +#define BIT_TRXRPT_TIMER_TH_8822C(x) \ + (((x) & BIT_MASK_TRXRPT_TIMER_TH_8822C) \ + << BIT_SHIFT_TRXRPT_TIMER_TH_8822C) +#define BITS_TRXRPT_TIMER_TH_8822C \ + (BIT_MASK_TRXRPT_TIMER_TH_8822C << BIT_SHIFT_TRXRPT_TIMER_TH_8822C) +#define BIT_CLEAR_TRXRPT_TIMER_TH_8822C(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8822C)) +#define BIT_GET_TRXRPT_TIMER_TH_8822C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822C) & \ + BIT_MASK_TRXRPT_TIMER_TH_8822C) +#define BIT_SET_TRXRPT_TIMER_TH_8822C(x, v) \ + (BIT_CLEAR_TRXRPT_TIMER_TH_8822C(x) | BIT_TRXRPT_TIMER_TH_8822C(v)) + +#define BIT_SHIFT_TRXRPT_LEN_TH_8822C 16 +#define BIT_MASK_TRXRPT_LEN_TH_8822C 0xff +#define BIT_TRXRPT_LEN_TH_8822C(x) \ + (((x) & BIT_MASK_TRXRPT_LEN_TH_8822C) << BIT_SHIFT_TRXRPT_LEN_TH_8822C) +#define BITS_TRXRPT_LEN_TH_8822C \ + (BIT_MASK_TRXRPT_LEN_TH_8822C << BIT_SHIFT_TRXRPT_LEN_TH_8822C) +#define BIT_CLEAR_TRXRPT_LEN_TH_8822C(x) ((x) & (~BITS_TRXRPT_LEN_TH_8822C)) +#define BIT_GET_TRXRPT_LEN_TH_8822C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822C) & BIT_MASK_TRXRPT_LEN_TH_8822C) +#define BIT_SET_TRXRPT_LEN_TH_8822C(x, v) \ + (BIT_CLEAR_TRXRPT_LEN_TH_8822C(x) | BIT_TRXRPT_LEN_TH_8822C(v)) + +#define BIT_SHIFT_TRXRPT_READ_PTR_8822C 8 +#define BIT_MASK_TRXRPT_READ_PTR_8822C 0xff +#define BIT_TRXRPT_READ_PTR_8822C(x) \ + (((x) & BIT_MASK_TRXRPT_READ_PTR_8822C) \ + << BIT_SHIFT_TRXRPT_READ_PTR_8822C) +#define BITS_TRXRPT_READ_PTR_8822C \ + (BIT_MASK_TRXRPT_READ_PTR_8822C << BIT_SHIFT_TRXRPT_READ_PTR_8822C) +#define BIT_CLEAR_TRXRPT_READ_PTR_8822C(x) ((x) & (~BITS_TRXRPT_READ_PTR_8822C)) +#define BIT_GET_TRXRPT_READ_PTR_8822C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822C) & \ + BIT_MASK_TRXRPT_READ_PTR_8822C) +#define BIT_SET_TRXRPT_READ_PTR_8822C(x, v) \ + (BIT_CLEAR_TRXRPT_READ_PTR_8822C(x) | BIT_TRXRPT_READ_PTR_8822C(v)) + +#define BIT_SHIFT_TRXRPT_WRITE_PTR_8822C 0 +#define BIT_MASK_TRXRPT_WRITE_PTR_8822C 0xff +#define BIT_TRXRPT_WRITE_PTR_8822C(x) \ + (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822C) \ + << BIT_SHIFT_TRXRPT_WRITE_PTR_8822C) +#define BITS_TRXRPT_WRITE_PTR_8822C \ + (BIT_MASK_TRXRPT_WRITE_PTR_8822C << BIT_SHIFT_TRXRPT_WRITE_PTR_8822C) +#define BIT_CLEAR_TRXRPT_WRITE_PTR_8822C(x) \ + ((x) & (~BITS_TRXRPT_WRITE_PTR_8822C)) +#define BIT_GET_TRXRPT_WRITE_PTR_8822C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822C) & \ + BIT_MASK_TRXRPT_WRITE_PTR_8822C) +#define BIT_SET_TRXRPT_WRITE_PTR_8822C(x, v) \ + (BIT_CLEAR_TRXRPT_WRITE_PTR_8822C(x) | BIT_TRXRPT_WRITE_PTR_8822C(v)) + +/* 2 REG_INIRTS_RATE_SEL_8822C */ +#define BIT_LEAG_RTS_BW_DUP_8822C BIT(5) + +/* 2 REG_BASIC_CFEND_RATE_8822C */ + +#define BIT_SHIFT_BASIC_CFEND_RATE_8822C 0 +#define BIT_MASK_BASIC_CFEND_RATE_8822C 0x1f +#define BIT_BASIC_CFEND_RATE_8822C(x) \ + (((x) & BIT_MASK_BASIC_CFEND_RATE_8822C) \ + << BIT_SHIFT_BASIC_CFEND_RATE_8822C) +#define BITS_BASIC_CFEND_RATE_8822C \ + (BIT_MASK_BASIC_CFEND_RATE_8822C << BIT_SHIFT_BASIC_CFEND_RATE_8822C) +#define BIT_CLEAR_BASIC_CFEND_RATE_8822C(x) \ + ((x) & (~BITS_BASIC_CFEND_RATE_8822C)) +#define BIT_GET_BASIC_CFEND_RATE_8822C(x) \ + (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822C) & \ + BIT_MASK_BASIC_CFEND_RATE_8822C) +#define BIT_SET_BASIC_CFEND_RATE_8822C(x, v) \ + (BIT_CLEAR_BASIC_CFEND_RATE_8822C(x) | BIT_BASIC_CFEND_RATE_8822C(v)) + +/* 2 REG_STBC_CFEND_RATE_8822C */ + +#define BIT_SHIFT_STBC_CFEND_RATE_8822C 0 +#define BIT_MASK_STBC_CFEND_RATE_8822C 0x1f +#define BIT_STBC_CFEND_RATE_8822C(x) \ + (((x) & BIT_MASK_STBC_CFEND_RATE_8822C) \ + << BIT_SHIFT_STBC_CFEND_RATE_8822C) +#define BITS_STBC_CFEND_RATE_8822C \ + (BIT_MASK_STBC_CFEND_RATE_8822C << BIT_SHIFT_STBC_CFEND_RATE_8822C) +#define BIT_CLEAR_STBC_CFEND_RATE_8822C(x) ((x) & (~BITS_STBC_CFEND_RATE_8822C)) +#define BIT_GET_STBC_CFEND_RATE_8822C(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822C) & \ + BIT_MASK_STBC_CFEND_RATE_8822C) +#define BIT_SET_STBC_CFEND_RATE_8822C(x, v) \ + (BIT_CLEAR_STBC_CFEND_RATE_8822C(x) | BIT_STBC_CFEND_RATE_8822C(v)) + +/* 2 REG_DATA_SC_8822C */ + +#define BIT_SHIFT_TXSC_40M_8822C 4 +#define BIT_MASK_TXSC_40M_8822C 0xf +#define BIT_TXSC_40M_8822C(x) \ + (((x) & BIT_MASK_TXSC_40M_8822C) << BIT_SHIFT_TXSC_40M_8822C) +#define BITS_TXSC_40M_8822C \ + (BIT_MASK_TXSC_40M_8822C << BIT_SHIFT_TXSC_40M_8822C) +#define BIT_CLEAR_TXSC_40M_8822C(x) ((x) & (~BITS_TXSC_40M_8822C)) +#define BIT_GET_TXSC_40M_8822C(x) \ + (((x) >> BIT_SHIFT_TXSC_40M_8822C) & BIT_MASK_TXSC_40M_8822C) +#define BIT_SET_TXSC_40M_8822C(x, v) \ + (BIT_CLEAR_TXSC_40M_8822C(x) | BIT_TXSC_40M_8822C(v)) + +#define BIT_SHIFT_TXSC_20M_8822C 0 +#define BIT_MASK_TXSC_20M_8822C 0xf +#define BIT_TXSC_20M_8822C(x) \ + (((x) & BIT_MASK_TXSC_20M_8822C) << BIT_SHIFT_TXSC_20M_8822C) +#define BITS_TXSC_20M_8822C \ + (BIT_MASK_TXSC_20M_8822C << BIT_SHIFT_TXSC_20M_8822C) +#define BIT_CLEAR_TXSC_20M_8822C(x) ((x) & (~BITS_TXSC_20M_8822C)) +#define BIT_GET_TXSC_20M_8822C(x) \ + (((x) >> BIT_SHIFT_TXSC_20M_8822C) & BIT_MASK_TXSC_20M_8822C) +#define BIT_SET_TXSC_20M_8822C(x, v) \ + (BIT_CLEAR_TXSC_20M_8822C(x) | BIT_TXSC_20M_8822C(v)) + +/* 2 REG_MACID_SLEEP3_8822C */ + +#define BIT_SHIFT_MACID127_96_PKTSLEEP_8822C 0 +#define BIT_MASK_MACID127_96_PKTSLEEP_8822C 0xffffffffL +#define BIT_MACID127_96_PKTSLEEP_8822C(x) \ + (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822C) \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8822C) +#define BITS_MACID127_96_PKTSLEEP_8822C \ + (BIT_MASK_MACID127_96_PKTSLEEP_8822C \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8822C) +#define BIT_CLEAR_MACID127_96_PKTSLEEP_8822C(x) \ + ((x) & (~BITS_MACID127_96_PKTSLEEP_8822C)) +#define BIT_GET_MACID127_96_PKTSLEEP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822C) & \ + BIT_MASK_MACID127_96_PKTSLEEP_8822C) +#define BIT_SET_MACID127_96_PKTSLEEP_8822C(x, v) \ + (BIT_CLEAR_MACID127_96_PKTSLEEP_8822C(x) | \ + BIT_MACID127_96_PKTSLEEP_8822C(v)) + +/* 2 REG_MACID_SLEEP1_8822C */ + +#define BIT_SHIFT_MACID63_32_PKTSLEEP_8822C 0 +#define BIT_MASK_MACID63_32_PKTSLEEP_8822C 0xffffffffL +#define BIT_MACID63_32_PKTSLEEP_8822C(x) \ + (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822C) \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8822C) +#define BITS_MACID63_32_PKTSLEEP_8822C \ + (BIT_MASK_MACID63_32_PKTSLEEP_8822C \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8822C) +#define BIT_CLEAR_MACID63_32_PKTSLEEP_8822C(x) \ + ((x) & (~BITS_MACID63_32_PKTSLEEP_8822C)) +#define BIT_GET_MACID63_32_PKTSLEEP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822C) & \ + BIT_MASK_MACID63_32_PKTSLEEP_8822C) +#define BIT_SET_MACID63_32_PKTSLEEP_8822C(x, v) \ + (BIT_CLEAR_MACID63_32_PKTSLEEP_8822C(x) | \ + BIT_MACID63_32_PKTSLEEP_8822C(v)) + +/* 2 REG_ARFR2_V1_8822C */ + +#define BIT_SHIFT_ARFRL2_8822C 0 +#define BIT_MASK_ARFRL2_8822C 0xffffffffL +#define BIT_ARFRL2_8822C(x) \ + (((x) & BIT_MASK_ARFRL2_8822C) << BIT_SHIFT_ARFRL2_8822C) +#define BITS_ARFRL2_8822C (BIT_MASK_ARFRL2_8822C << BIT_SHIFT_ARFRL2_8822C) +#define BIT_CLEAR_ARFRL2_8822C(x) ((x) & (~BITS_ARFRL2_8822C)) +#define BIT_GET_ARFRL2_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRL2_8822C) & BIT_MASK_ARFRL2_8822C) +#define BIT_SET_ARFRL2_8822C(x, v) \ + (BIT_CLEAR_ARFRL2_8822C(x) | BIT_ARFRL2_8822C(v)) + +/* 2 REG_ARFRH2_V1_8822C */ + +#define BIT_SHIFT_ARFRH2_8822C 0 +#define BIT_MASK_ARFRH2_8822C 0xffffffffL +#define BIT_ARFRH2_8822C(x) \ + (((x) & BIT_MASK_ARFRH2_8822C) << BIT_SHIFT_ARFRH2_8822C) +#define BITS_ARFRH2_8822C (BIT_MASK_ARFRH2_8822C << BIT_SHIFT_ARFRH2_8822C) +#define BIT_CLEAR_ARFRH2_8822C(x) ((x) & (~BITS_ARFRH2_8822C)) +#define BIT_GET_ARFRH2_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRH2_8822C) & BIT_MASK_ARFRH2_8822C) +#define BIT_SET_ARFRH2_8822C(x, v) \ + (BIT_CLEAR_ARFRH2_8822C(x) | BIT_ARFRH2_8822C(v)) + +/* 2 REG_ARFR3_V1_8822C */ + +#define BIT_SHIFT_ARFRL3_8822C 0 +#define BIT_MASK_ARFRL3_8822C 0xffffffffL +#define BIT_ARFRL3_8822C(x) \ + (((x) & BIT_MASK_ARFRL3_8822C) << BIT_SHIFT_ARFRL3_8822C) +#define BITS_ARFRL3_8822C (BIT_MASK_ARFRL3_8822C << BIT_SHIFT_ARFRL3_8822C) +#define BIT_CLEAR_ARFRL3_8822C(x) ((x) & (~BITS_ARFRL3_8822C)) +#define BIT_GET_ARFRL3_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRL3_8822C) & BIT_MASK_ARFRL3_8822C) +#define BIT_SET_ARFRL3_8822C(x, v) \ + (BIT_CLEAR_ARFRL3_8822C(x) | BIT_ARFRL3_8822C(v)) + +/* 2 REG_ARFRH3_V1_8822C */ + +#define BIT_SHIFT_ARFRH3_8822C 0 +#define BIT_MASK_ARFRH3_8822C 0xffffffffL +#define BIT_ARFRH3_8822C(x) \ + (((x) & BIT_MASK_ARFRH3_8822C) << BIT_SHIFT_ARFRH3_8822C) +#define BITS_ARFRH3_8822C (BIT_MASK_ARFRH3_8822C << BIT_SHIFT_ARFRH3_8822C) +#define BIT_CLEAR_ARFRH3_8822C(x) ((x) & (~BITS_ARFRH3_8822C)) +#define BIT_GET_ARFRH3_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRH3_8822C) & BIT_MASK_ARFRH3_8822C) +#define BIT_SET_ARFRH3_8822C(x, v) \ + (BIT_CLEAR_ARFRH3_8822C(x) | BIT_ARFRH3_8822C(v)) + +/* 2 REG_ARFR4_8822C */ + +#define BIT_SHIFT_ARFRL4_8822C 0 +#define BIT_MASK_ARFRL4_8822C 0xffffffffL +#define BIT_ARFRL4_8822C(x) \ + (((x) & BIT_MASK_ARFRL4_8822C) << BIT_SHIFT_ARFRL4_8822C) +#define BITS_ARFRL4_8822C (BIT_MASK_ARFRL4_8822C << BIT_SHIFT_ARFRL4_8822C) +#define BIT_CLEAR_ARFRL4_8822C(x) ((x) & (~BITS_ARFRL4_8822C)) +#define BIT_GET_ARFRL4_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRL4_8822C) & BIT_MASK_ARFRL4_8822C) +#define BIT_SET_ARFRL4_8822C(x, v) \ + (BIT_CLEAR_ARFRL4_8822C(x) | BIT_ARFRL4_8822C(v)) + +/* 2 REG_ARFRH4_8822C */ + +#define BIT_SHIFT_ARFRH4_8822C 0 +#define BIT_MASK_ARFRH4_8822C 0xffffffffL +#define BIT_ARFRH4_8822C(x) \ + (((x) & BIT_MASK_ARFRH4_8822C) << BIT_SHIFT_ARFRH4_8822C) +#define BITS_ARFRH4_8822C (BIT_MASK_ARFRH4_8822C << BIT_SHIFT_ARFRH4_8822C) +#define BIT_CLEAR_ARFRH4_8822C(x) ((x) & (~BITS_ARFRH4_8822C)) +#define BIT_GET_ARFRH4_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRH4_8822C) & BIT_MASK_ARFRH4_8822C) +#define BIT_SET_ARFRH4_8822C(x, v) \ + (BIT_CLEAR_ARFRH4_8822C(x) | BIT_ARFRH4_8822C(v)) + +/* 2 REG_ARFR5_8822C */ + +#define BIT_SHIFT_ARFRL5_8822C 0 +#define BIT_MASK_ARFRL5_8822C 0xffffffffL +#define BIT_ARFRL5_8822C(x) \ + (((x) & BIT_MASK_ARFRL5_8822C) << BIT_SHIFT_ARFRL5_8822C) +#define BITS_ARFRL5_8822C (BIT_MASK_ARFRL5_8822C << BIT_SHIFT_ARFRL5_8822C) +#define BIT_CLEAR_ARFRL5_8822C(x) ((x) & (~BITS_ARFRL5_8822C)) +#define BIT_GET_ARFRL5_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRL5_8822C) & BIT_MASK_ARFRL5_8822C) +#define BIT_SET_ARFRL5_8822C(x, v) \ + (BIT_CLEAR_ARFRL5_8822C(x) | BIT_ARFRL5_8822C(v)) + +/* 2 REG_ARFRH5_8822C */ + +#define BIT_SHIFT_ARFRH5_8822C 0 +#define BIT_MASK_ARFRH5_8822C 0xffffffffL +#define BIT_ARFRH5_8822C(x) \ + (((x) & BIT_MASK_ARFRH5_8822C) << BIT_SHIFT_ARFRH5_8822C) +#define BITS_ARFRH5_8822C (BIT_MASK_ARFRH5_8822C << BIT_SHIFT_ARFRH5_8822C) +#define BIT_CLEAR_ARFRH5_8822C(x) ((x) & (~BITS_ARFRH5_8822C)) +#define BIT_GET_ARFRH5_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRH5_8822C) & BIT_MASK_ARFRH5_8822C) +#define BIT_SET_ARFRH5_8822C(x, v) \ + (BIT_CLEAR_ARFRH5_8822C(x) | BIT_ARFRH5_8822C(v)) + +/* 2 REG_TXRPT_START_OFFSET_8822C */ + +#define BIT_SHIFT_MACID_MURATE_OFFSET_8822C 24 +#define BIT_MASK_MACID_MURATE_OFFSET_8822C 0xff +#define BIT_MACID_MURATE_OFFSET_8822C(x) \ + (((x) & BIT_MASK_MACID_MURATE_OFFSET_8822C) \ + << BIT_SHIFT_MACID_MURATE_OFFSET_8822C) +#define BITS_MACID_MURATE_OFFSET_8822C \ + (BIT_MASK_MACID_MURATE_OFFSET_8822C \ + << BIT_SHIFT_MACID_MURATE_OFFSET_8822C) +#define BIT_CLEAR_MACID_MURATE_OFFSET_8822C(x) \ + ((x) & (~BITS_MACID_MURATE_OFFSET_8822C)) +#define BIT_GET_MACID_MURATE_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822C) & \ + BIT_MASK_MACID_MURATE_OFFSET_8822C) +#define BIT_SET_MACID_MURATE_OFFSET_8822C(x, v) \ + (BIT_CLEAR_MACID_MURATE_OFFSET_8822C(x) | \ + BIT_MACID_MURATE_OFFSET_8822C(v)) + +#define BIT_SHIFT_TXRPT_MISS_COUNT_8822C 17 +#define BIT_MASK_TXRPT_MISS_COUNT_8822C 0x7 +#define BIT_TXRPT_MISS_COUNT_8822C(x) \ + (((x) & BIT_MASK_TXRPT_MISS_COUNT_8822C) \ + << BIT_SHIFT_TXRPT_MISS_COUNT_8822C) +#define BITS_TXRPT_MISS_COUNT_8822C \ + (BIT_MASK_TXRPT_MISS_COUNT_8822C << BIT_SHIFT_TXRPT_MISS_COUNT_8822C) +#define BIT_CLEAR_TXRPT_MISS_COUNT_8822C(x) \ + ((x) & (~BITS_TXRPT_MISS_COUNT_8822C)) +#define BIT_GET_TXRPT_MISS_COUNT_8822C(x) \ + (((x) >> BIT_SHIFT_TXRPT_MISS_COUNT_8822C) & \ + BIT_MASK_TXRPT_MISS_COUNT_8822C) +#define BIT_SET_TXRPT_MISS_COUNT_8822C(x, v) \ + (BIT_CLEAR_TXRPT_MISS_COUNT_8822C(x) | BIT_TXRPT_MISS_COUNT_8822C(v)) + +#define BIT_RPTFIFO_SIZE_OPT_8822C BIT(16) + +#define BIT_SHIFT_MACID_CTRL_OFFSET_8822C 8 +#define BIT_MASK_MACID_CTRL_OFFSET_8822C 0xff +#define BIT_MACID_CTRL_OFFSET_8822C(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET_8822C) \ + << BIT_SHIFT_MACID_CTRL_OFFSET_8822C) +#define BITS_MACID_CTRL_OFFSET_8822C \ + (BIT_MASK_MACID_CTRL_OFFSET_8822C << BIT_SHIFT_MACID_CTRL_OFFSET_8822C) +#define BIT_CLEAR_MACID_CTRL_OFFSET_8822C(x) \ + ((x) & (~BITS_MACID_CTRL_OFFSET_8822C)) +#define BIT_GET_MACID_CTRL_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822C) & \ + BIT_MASK_MACID_CTRL_OFFSET_8822C) +#define BIT_SET_MACID_CTRL_OFFSET_8822C(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET_8822C(x) | BIT_MACID_CTRL_OFFSET_8822C(v)) + +#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C 0 +#define BIT_MASK_AMPDU_TXRPT_OFFSET_8822C 0xff +#define BIT_AMPDU_TXRPT_OFFSET_8822C(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822C) \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C) +#define BITS_AMPDU_TXRPT_OFFSET_8822C \ + (BIT_MASK_AMPDU_TXRPT_OFFSET_8822C \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822C(x) \ + ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8822C)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C) & \ + BIT_MASK_AMPDU_TXRPT_OFFSET_8822C) +#define BIT_SET_AMPDU_TXRPT_OFFSET_8822C(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822C(x) | \ + BIT_AMPDU_TXRPT_OFFSET_8822C(v)) + +/* 2 REG_POWER_STAGE1_8822C */ +#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8822C BIT(31) +#define BIT_PTA_WL_PRI_MASK_BCNQ_8822C BIT(30) +#define BIT_PTA_WL_PRI_MASK_HIQ_8822C BIT(29) +#define BIT_PTA_WL_PRI_MASK_MGQ_8822C BIT(28) +#define BIT_PTA_WL_PRI_MASK_BK_8822C BIT(27) +#define BIT_PTA_WL_PRI_MASK_BE_8822C BIT(26) +#define BIT_PTA_WL_PRI_MASK_VI_8822C BIT(25) +#define BIT_PTA_WL_PRI_MASK_VO_8822C BIT(24) + +#define BIT_SHIFT_POWER_STAGE1_8822C 0 +#define BIT_MASK_POWER_STAGE1_8822C 0xffffff +#define BIT_POWER_STAGE1_8822C(x) \ + (((x) & BIT_MASK_POWER_STAGE1_8822C) << BIT_SHIFT_POWER_STAGE1_8822C) +#define BITS_POWER_STAGE1_8822C \ + (BIT_MASK_POWER_STAGE1_8822C << BIT_SHIFT_POWER_STAGE1_8822C) +#define BIT_CLEAR_POWER_STAGE1_8822C(x) ((x) & (~BITS_POWER_STAGE1_8822C)) +#define BIT_GET_POWER_STAGE1_8822C(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1_8822C) & BIT_MASK_POWER_STAGE1_8822C) +#define BIT_SET_POWER_STAGE1_8822C(x, v) \ + (BIT_CLEAR_POWER_STAGE1_8822C(x) | BIT_POWER_STAGE1_8822C(v)) + +/* 2 REG_POWER_STAGE2_8822C */ +#define BIT__R_CTRL_PKT_POW_ADJ_8822C BIT(24) + +#define BIT_SHIFT_POWER_STAGE2_8822C 0 +#define BIT_MASK_POWER_STAGE2_8822C 0xffffff +#define BIT_POWER_STAGE2_8822C(x) \ + (((x) & BIT_MASK_POWER_STAGE2_8822C) << BIT_SHIFT_POWER_STAGE2_8822C) +#define BITS_POWER_STAGE2_8822C \ + (BIT_MASK_POWER_STAGE2_8822C << BIT_SHIFT_POWER_STAGE2_8822C) +#define BIT_CLEAR_POWER_STAGE2_8822C(x) ((x) & (~BITS_POWER_STAGE2_8822C)) +#define BIT_GET_POWER_STAGE2_8822C(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2_8822C) & BIT_MASK_POWER_STAGE2_8822C) +#define BIT_SET_POWER_STAGE2_8822C(x, v) \ + (BIT_CLEAR_POWER_STAGE2_8822C(x) | BIT_POWER_STAGE2_8822C(v)) + +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8822C */ + +#define BIT_SHIFT_PAD_NUM_THRES_8822C 24 +#define BIT_MASK_PAD_NUM_THRES_8822C 0x3f +#define BIT_PAD_NUM_THRES_8822C(x) \ + (((x) & BIT_MASK_PAD_NUM_THRES_8822C) << BIT_SHIFT_PAD_NUM_THRES_8822C) +#define BITS_PAD_NUM_THRES_8822C \ + (BIT_MASK_PAD_NUM_THRES_8822C << BIT_SHIFT_PAD_NUM_THRES_8822C) +#define BIT_CLEAR_PAD_NUM_THRES_8822C(x) ((x) & (~BITS_PAD_NUM_THRES_8822C)) +#define BIT_GET_PAD_NUM_THRES_8822C(x) \ + (((x) >> BIT_SHIFT_PAD_NUM_THRES_8822C) & BIT_MASK_PAD_NUM_THRES_8822C) +#define BIT_SET_PAD_NUM_THRES_8822C(x, v) \ + (BIT_CLEAR_PAD_NUM_THRES_8822C(x) | BIT_PAD_NUM_THRES_8822C(v)) + +#define BIT_R_DMA_THIS_QUEUE_BK_8822C BIT(23) +#define BIT_R_DMA_THIS_QUEUE_BE_8822C BIT(22) +#define BIT_R_DMA_THIS_QUEUE_VI_8822C BIT(21) +#define BIT_R_DMA_THIS_QUEUE_VO_8822C BIT(20) + +#define BIT_SHIFT_R_TOTAL_LEN_TH_8822C 8 +#define BIT_MASK_R_TOTAL_LEN_TH_8822C 0xfff +#define BIT_R_TOTAL_LEN_TH_8822C(x) \ + (((x) & BIT_MASK_R_TOTAL_LEN_TH_8822C) \ + << BIT_SHIFT_R_TOTAL_LEN_TH_8822C) +#define BITS_R_TOTAL_LEN_TH_8822C \ + (BIT_MASK_R_TOTAL_LEN_TH_8822C << BIT_SHIFT_R_TOTAL_LEN_TH_8822C) +#define BIT_CLEAR_R_TOTAL_LEN_TH_8822C(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8822C)) +#define BIT_GET_R_TOTAL_LEN_TH_8822C(x) \ + (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822C) & \ + BIT_MASK_R_TOTAL_LEN_TH_8822C) +#define BIT_SET_R_TOTAL_LEN_TH_8822C(x, v) \ + (BIT_CLEAR_R_TOTAL_LEN_TH_8822C(x) | BIT_R_TOTAL_LEN_TH_8822C(v)) + +#define BIT_EN_NEW_EARLY_8822C BIT(7) +#define BIT_PRE_TX_CMD_8822C BIT(6) + +#define BIT_SHIFT_NUM_SCL_EN_8822C 4 +#define BIT_MASK_NUM_SCL_EN_8822C 0x3 +#define BIT_NUM_SCL_EN_8822C(x) \ + (((x) & BIT_MASK_NUM_SCL_EN_8822C) << BIT_SHIFT_NUM_SCL_EN_8822C) +#define BITS_NUM_SCL_EN_8822C \ + (BIT_MASK_NUM_SCL_EN_8822C << BIT_SHIFT_NUM_SCL_EN_8822C) +#define BIT_CLEAR_NUM_SCL_EN_8822C(x) ((x) & (~BITS_NUM_SCL_EN_8822C)) +#define BIT_GET_NUM_SCL_EN_8822C(x) \ + (((x) >> BIT_SHIFT_NUM_SCL_EN_8822C) & BIT_MASK_NUM_SCL_EN_8822C) +#define BIT_SET_NUM_SCL_EN_8822C(x, v) \ + (BIT_CLEAR_NUM_SCL_EN_8822C(x) | BIT_NUM_SCL_EN_8822C(v)) + +#define BIT_BK_EN_8822C BIT(3) +#define BIT_BE_EN_8822C BIT(2) +#define BIT_VI_EN_8822C BIT(1) +#define BIT_VO_EN_8822C BIT(0) + +/* 2 REG_PKT_LIFE_TIME_8822C */ + +#define BIT_SHIFT_PKT_LIFTIME_BEBK_8822C 16 +#define BIT_MASK_PKT_LIFTIME_BEBK_8822C 0xffff +#define BIT_PKT_LIFTIME_BEBK_8822C(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822C) \ + << BIT_SHIFT_PKT_LIFTIME_BEBK_8822C) +#define BITS_PKT_LIFTIME_BEBK_8822C \ + (BIT_MASK_PKT_LIFTIME_BEBK_8822C << BIT_SHIFT_PKT_LIFTIME_BEBK_8822C) +#define BIT_CLEAR_PKT_LIFTIME_BEBK_8822C(x) \ + ((x) & (~BITS_PKT_LIFTIME_BEBK_8822C)) +#define BIT_GET_PKT_LIFTIME_BEBK_8822C(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822C) & \ + BIT_MASK_PKT_LIFTIME_BEBK_8822C) +#define BIT_SET_PKT_LIFTIME_BEBK_8822C(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_BEBK_8822C(x) | BIT_PKT_LIFTIME_BEBK_8822C(v)) + +#define BIT_SHIFT_PKT_LIFTIME_VOVI_8822C 0 +#define BIT_MASK_PKT_LIFTIME_VOVI_8822C 0xffff +#define BIT_PKT_LIFTIME_VOVI_8822C(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822C) \ + << BIT_SHIFT_PKT_LIFTIME_VOVI_8822C) +#define BITS_PKT_LIFTIME_VOVI_8822C \ + (BIT_MASK_PKT_LIFTIME_VOVI_8822C << BIT_SHIFT_PKT_LIFTIME_VOVI_8822C) +#define BIT_CLEAR_PKT_LIFTIME_VOVI_8822C(x) \ + ((x) & (~BITS_PKT_LIFTIME_VOVI_8822C)) +#define BIT_GET_PKT_LIFTIME_VOVI_8822C(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822C) & \ + BIT_MASK_PKT_LIFTIME_VOVI_8822C) +#define BIT_SET_PKT_LIFTIME_VOVI_8822C(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_VOVI_8822C(x) | BIT_PKT_LIFTIME_VOVI_8822C(v)) + +/* 2 REG_STBC_SETTING_8822C */ + +#define BIT_SHIFT_CDEND_TXTIME_L_8822C 4 +#define BIT_MASK_CDEND_TXTIME_L_8822C 0xf +#define BIT_CDEND_TXTIME_L_8822C(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_L_8822C) \ + << BIT_SHIFT_CDEND_TXTIME_L_8822C) +#define BITS_CDEND_TXTIME_L_8822C \ + (BIT_MASK_CDEND_TXTIME_L_8822C << BIT_SHIFT_CDEND_TXTIME_L_8822C) +#define BIT_CLEAR_CDEND_TXTIME_L_8822C(x) ((x) & (~BITS_CDEND_TXTIME_L_8822C)) +#define BIT_GET_CDEND_TXTIME_L_8822C(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822C) & \ + BIT_MASK_CDEND_TXTIME_L_8822C) +#define BIT_SET_CDEND_TXTIME_L_8822C(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_L_8822C(x) | BIT_CDEND_TXTIME_L_8822C(v)) + +#define BIT_SHIFT_NESS_8822C 2 +#define BIT_MASK_NESS_8822C 0x3 +#define BIT_NESS_8822C(x) (((x) & BIT_MASK_NESS_8822C) << BIT_SHIFT_NESS_8822C) +#define BITS_NESS_8822C (BIT_MASK_NESS_8822C << BIT_SHIFT_NESS_8822C) +#define BIT_CLEAR_NESS_8822C(x) ((x) & (~BITS_NESS_8822C)) +#define BIT_GET_NESS_8822C(x) \ + (((x) >> BIT_SHIFT_NESS_8822C) & BIT_MASK_NESS_8822C) +#define BIT_SET_NESS_8822C(x, v) (BIT_CLEAR_NESS_8822C(x) | BIT_NESS_8822C(v)) + +#define BIT_SHIFT_STBC_CFEND_8822C 0 +#define BIT_MASK_STBC_CFEND_8822C 0x3 +#define BIT_STBC_CFEND_8822C(x) \ + (((x) & BIT_MASK_STBC_CFEND_8822C) << BIT_SHIFT_STBC_CFEND_8822C) +#define BITS_STBC_CFEND_8822C \ + (BIT_MASK_STBC_CFEND_8822C << BIT_SHIFT_STBC_CFEND_8822C) +#define BIT_CLEAR_STBC_CFEND_8822C(x) ((x) & (~BITS_STBC_CFEND_8822C)) +#define BIT_GET_STBC_CFEND_8822C(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_8822C) & BIT_MASK_STBC_CFEND_8822C) +#define BIT_SET_STBC_CFEND_8822C(x, v) \ + (BIT_CLEAR_STBC_CFEND_8822C(x) | BIT_STBC_CFEND_8822C(v)) + +/* 2 REG_STBC_SETTING2_8822C */ + +#define BIT_SHIFT_CDEND_TXTIME_H_8822C 0 +#define BIT_MASK_CDEND_TXTIME_H_8822C 0x1f +#define BIT_CDEND_TXTIME_H_8822C(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_H_8822C) \ + << BIT_SHIFT_CDEND_TXTIME_H_8822C) +#define BITS_CDEND_TXTIME_H_8822C \ + (BIT_MASK_CDEND_TXTIME_H_8822C << BIT_SHIFT_CDEND_TXTIME_H_8822C) +#define BIT_CLEAR_CDEND_TXTIME_H_8822C(x) ((x) & (~BITS_CDEND_TXTIME_H_8822C)) +#define BIT_GET_CDEND_TXTIME_H_8822C(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822C) & \ + BIT_MASK_CDEND_TXTIME_H_8822C) +#define BIT_SET_CDEND_TXTIME_H_8822C(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_H_8822C(x) | BIT_CDEND_TXTIME_H_8822C(v)) + +/* 2 REG_QUEUE_CTRL_8822C */ +#define BIT_FORCE_RND_PRI_8822C BIT(6) +#define BIT_PTA_EDCCA_EN_8822C BIT(5) +#define BIT_PTA_WL_TX_EN_8822C BIT(4) +#define BIT_R_USE_DATA_BW_8822C BIT(3) +#define BIT_TRI_PKT_INT_MODE1_8822C BIT(2) +#define BIT_TRI_PKT_INT_MODE0_8822C BIT(1) +#define BIT_ACQ_MODE_SEL_8822C BIT(0) + +/* 2 REG_SINGLE_AMPDU_CTRL_8822C */ +#define BIT_EN_SINGLE_APMDU_8822C BIT(7) + +#define BIT_SHIFT_SNDTX_MAXTIME_8822C 0 +#define BIT_MASK_SNDTX_MAXTIME_8822C 0x7f +#define BIT_SNDTX_MAXTIME_8822C(x) \ + (((x) & BIT_MASK_SNDTX_MAXTIME_8822C) << BIT_SHIFT_SNDTX_MAXTIME_8822C) +#define BITS_SNDTX_MAXTIME_8822C \ + (BIT_MASK_SNDTX_MAXTIME_8822C << BIT_SHIFT_SNDTX_MAXTIME_8822C) +#define BIT_CLEAR_SNDTX_MAXTIME_8822C(x) ((x) & (~BITS_SNDTX_MAXTIME_8822C)) +#define BIT_GET_SNDTX_MAXTIME_8822C(x) \ + (((x) >> BIT_SHIFT_SNDTX_MAXTIME_8822C) & BIT_MASK_SNDTX_MAXTIME_8822C) +#define BIT_SET_SNDTX_MAXTIME_8822C(x, v) \ + (BIT_CLEAR_SNDTX_MAXTIME_8822C(x) | BIT_SNDTX_MAXTIME_8822C(v)) + +/* 2 REG_PROT_MODE_CTRL_8822C */ +#define BIT_SND_SIFS_TXDATA_8822C BIT(31) +#define BIT_TX_SND_MATCH_MACID_8822C BIT(30) + +#define BIT_SHIFT_RTS_MAX_AGG_NUM_8822C 24 +#define BIT_MASK_RTS_MAX_AGG_NUM_8822C 0x3f +#define BIT_RTS_MAX_AGG_NUM_8822C(x) \ + (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822C) \ + << BIT_SHIFT_RTS_MAX_AGG_NUM_8822C) +#define BITS_RTS_MAX_AGG_NUM_8822C \ + (BIT_MASK_RTS_MAX_AGG_NUM_8822C << BIT_SHIFT_RTS_MAX_AGG_NUM_8822C) +#define BIT_CLEAR_RTS_MAX_AGG_NUM_8822C(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8822C)) +#define BIT_GET_RTS_MAX_AGG_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822C) & \ + BIT_MASK_RTS_MAX_AGG_NUM_8822C) +#define BIT_SET_RTS_MAX_AGG_NUM_8822C(x, v) \ + (BIT_CLEAR_RTS_MAX_AGG_NUM_8822C(x) | BIT_RTS_MAX_AGG_NUM_8822C(v)) + +#define BIT_SHIFT_MAX_AGG_NUM_8822C 16 +#define BIT_MASK_MAX_AGG_NUM_8822C 0x3f +#define BIT_MAX_AGG_NUM_8822C(x) \ + (((x) & BIT_MASK_MAX_AGG_NUM_8822C) << BIT_SHIFT_MAX_AGG_NUM_8822C) +#define BITS_MAX_AGG_NUM_8822C \ + (BIT_MASK_MAX_AGG_NUM_8822C << BIT_SHIFT_MAX_AGG_NUM_8822C) +#define BIT_CLEAR_MAX_AGG_NUM_8822C(x) ((x) & (~BITS_MAX_AGG_NUM_8822C)) +#define BIT_GET_MAX_AGG_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_AGG_NUM_8822C) & BIT_MASK_MAX_AGG_NUM_8822C) +#define BIT_SET_MAX_AGG_NUM_8822C(x, v) \ + (BIT_CLEAR_MAX_AGG_NUM_8822C(x) | BIT_MAX_AGG_NUM_8822C(v)) + +#define BIT_SHIFT_RTS_TXTIME_TH_8822C 8 +#define BIT_MASK_RTS_TXTIME_TH_8822C 0xff +#define BIT_RTS_TXTIME_TH_8822C(x) \ + (((x) & BIT_MASK_RTS_TXTIME_TH_8822C) << BIT_SHIFT_RTS_TXTIME_TH_8822C) +#define BITS_RTS_TXTIME_TH_8822C \ + (BIT_MASK_RTS_TXTIME_TH_8822C << BIT_SHIFT_RTS_TXTIME_TH_8822C) +#define BIT_CLEAR_RTS_TXTIME_TH_8822C(x) ((x) & (~BITS_RTS_TXTIME_TH_8822C)) +#define BIT_GET_RTS_TXTIME_TH_8822C(x) \ + (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822C) & BIT_MASK_RTS_TXTIME_TH_8822C) +#define BIT_SET_RTS_TXTIME_TH_8822C(x, v) \ + (BIT_CLEAR_RTS_TXTIME_TH_8822C(x) | BIT_RTS_TXTIME_TH_8822C(v)) + +#define BIT_SHIFT_RTS_LEN_TH_8822C 0 +#define BIT_MASK_RTS_LEN_TH_8822C 0xff +#define BIT_RTS_LEN_TH_8822C(x) \ + (((x) & BIT_MASK_RTS_LEN_TH_8822C) << BIT_SHIFT_RTS_LEN_TH_8822C) +#define BITS_RTS_LEN_TH_8822C \ + (BIT_MASK_RTS_LEN_TH_8822C << BIT_SHIFT_RTS_LEN_TH_8822C) +#define BIT_CLEAR_RTS_LEN_TH_8822C(x) ((x) & (~BITS_RTS_LEN_TH_8822C)) +#define BIT_GET_RTS_LEN_TH_8822C(x) \ + (((x) >> BIT_SHIFT_RTS_LEN_TH_8822C) & BIT_MASK_RTS_LEN_TH_8822C) +#define BIT_SET_RTS_LEN_TH_8822C(x, v) \ + (BIT_CLEAR_RTS_LEN_TH_8822C(x) | BIT_RTS_LEN_TH_8822C(v)) + +/* 2 REG_BAR_MODE_CTRL_8822C */ + +#define BIT_SHIFT_BAR_RTY_LMT_8822C 16 +#define BIT_MASK_BAR_RTY_LMT_8822C 0x3 +#define BIT_BAR_RTY_LMT_8822C(x) \ + (((x) & BIT_MASK_BAR_RTY_LMT_8822C) << BIT_SHIFT_BAR_RTY_LMT_8822C) +#define BITS_BAR_RTY_LMT_8822C \ + (BIT_MASK_BAR_RTY_LMT_8822C << BIT_SHIFT_BAR_RTY_LMT_8822C) +#define BIT_CLEAR_BAR_RTY_LMT_8822C(x) ((x) & (~BITS_BAR_RTY_LMT_8822C)) +#define BIT_GET_BAR_RTY_LMT_8822C(x) \ + (((x) >> BIT_SHIFT_BAR_RTY_LMT_8822C) & BIT_MASK_BAR_RTY_LMT_8822C) +#define BIT_SET_BAR_RTY_LMT_8822C(x, v) \ + (BIT_CLEAR_BAR_RTY_LMT_8822C(x) | BIT_BAR_RTY_LMT_8822C(v)) + +#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C 8 +#define BIT_MASK_BAR_PKT_TXTIME_TH_8822C 0xff +#define BIT_BAR_PKT_TXTIME_TH_8822C(x) \ + (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822C) \ + << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C) +#define BITS_BAR_PKT_TXTIME_TH_8822C \ + (BIT_MASK_BAR_PKT_TXTIME_TH_8822C << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8822C(x) \ + ((x) & (~BITS_BAR_PKT_TXTIME_TH_8822C)) +#define BIT_GET_BAR_PKT_TXTIME_TH_8822C(x) \ + (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C) & \ + BIT_MASK_BAR_PKT_TXTIME_TH_8822C) +#define BIT_SET_BAR_PKT_TXTIME_TH_8822C(x, v) \ + (BIT_CLEAR_BAR_PKT_TXTIME_TH_8822C(x) | BIT_BAR_PKT_TXTIME_TH_8822C(v)) + +#define BIT_BAR_EN_V1_8822C BIT(6) + +#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C 0 +#define BIT_MASK_BAR_PKTNUM_TH_V1_8822C 0x3f +#define BIT_BAR_PKTNUM_TH_V1_8822C(x) \ + (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822C) \ + << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C) +#define BITS_BAR_PKTNUM_TH_V1_8822C \ + (BIT_MASK_BAR_PKTNUM_TH_V1_8822C << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8822C(x) \ + ((x) & (~BITS_BAR_PKTNUM_TH_V1_8822C)) +#define BIT_GET_BAR_PKTNUM_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C) & \ + BIT_MASK_BAR_PKTNUM_TH_V1_8822C) +#define BIT_SET_BAR_PKTNUM_TH_V1_8822C(x, v) \ + (BIT_CLEAR_BAR_PKTNUM_TH_V1_8822C(x) | BIT_BAR_PKTNUM_TH_V1_8822C(v)) + +/* 2 REG_RA_TRY_RATE_AGG_LMT_8822C */ + +#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C 0 +#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C 0x3f +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822C(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C) \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C) +#define BITS_RA_TRY_RATE_AGG_LMT_V1_8822C \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822C(x) \ + ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8822C)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C) & \ + BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8822C(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822C(x) | \ + BIT_RA_TRY_RATE_AGG_LMT_V1_8822C(v)) + +/* 2 REG_MACID_SLEEP2_8822C */ + +#define BIT_SHIFT_MACID95_64PKTSLEEP_8822C 0 +#define BIT_MASK_MACID95_64PKTSLEEP_8822C 0xffffffffL +#define BIT_MACID95_64PKTSLEEP_8822C(x) \ + (((x) & BIT_MASK_MACID95_64PKTSLEEP_8822C) \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8822C) +#define BITS_MACID95_64PKTSLEEP_8822C \ + (BIT_MASK_MACID95_64PKTSLEEP_8822C \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8822C) +#define BIT_CLEAR_MACID95_64PKTSLEEP_8822C(x) \ + ((x) & (~BITS_MACID95_64PKTSLEEP_8822C)) +#define BIT_GET_MACID95_64PKTSLEEP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822C) & \ + BIT_MASK_MACID95_64PKTSLEEP_8822C) +#define BIT_SET_MACID95_64PKTSLEEP_8822C(x, v) \ + (BIT_CLEAR_MACID95_64PKTSLEEP_8822C(x) | \ + BIT_MACID95_64PKTSLEEP_8822C(v)) + +/* 2 REG_MACID_SLEEP_8822C */ + +#define BIT_SHIFT_MACID31_0_PKTSLEEP_8822C 0 +#define BIT_MASK_MACID31_0_PKTSLEEP_8822C 0xffffffffL +#define BIT_MACID31_0_PKTSLEEP_8822C(x) \ + (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822C) \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8822C) +#define BITS_MACID31_0_PKTSLEEP_8822C \ + (BIT_MASK_MACID31_0_PKTSLEEP_8822C \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8822C) +#define BIT_CLEAR_MACID31_0_PKTSLEEP_8822C(x) \ + ((x) & (~BITS_MACID31_0_PKTSLEEP_8822C)) +#define BIT_GET_MACID31_0_PKTSLEEP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822C) & \ + BIT_MASK_MACID31_0_PKTSLEEP_8822C) +#define BIT_SET_MACID31_0_PKTSLEEP_8822C(x, v) \ + (BIT_CLEAR_MACID31_0_PKTSLEEP_8822C(x) | \ + BIT_MACID31_0_PKTSLEEP_8822C(v)) + +/* 2 REG_HW_SEQ0_8822C */ + +#define BIT_SHIFT_HW_SSN_SEQ0_8822C 0 +#define BIT_MASK_HW_SSN_SEQ0_8822C 0xfff +#define BIT_HW_SSN_SEQ0_8822C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ0_8822C) << BIT_SHIFT_HW_SSN_SEQ0_8822C) +#define BITS_HW_SSN_SEQ0_8822C \ + (BIT_MASK_HW_SSN_SEQ0_8822C << BIT_SHIFT_HW_SSN_SEQ0_8822C) +#define BIT_CLEAR_HW_SSN_SEQ0_8822C(x) ((x) & (~BITS_HW_SSN_SEQ0_8822C)) +#define BIT_GET_HW_SSN_SEQ0_8822C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822C) & BIT_MASK_HW_SSN_SEQ0_8822C) +#define BIT_SET_HW_SSN_SEQ0_8822C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ0_8822C(x) | BIT_HW_SSN_SEQ0_8822C(v)) + +/* 2 REG_HW_SEQ1_8822C */ + +#define BIT_SHIFT_HW_SSN_SEQ1_8822C 0 +#define BIT_MASK_HW_SSN_SEQ1_8822C 0xfff +#define BIT_HW_SSN_SEQ1_8822C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ1_8822C) << BIT_SHIFT_HW_SSN_SEQ1_8822C) +#define BITS_HW_SSN_SEQ1_8822C \ + (BIT_MASK_HW_SSN_SEQ1_8822C << BIT_SHIFT_HW_SSN_SEQ1_8822C) +#define BIT_CLEAR_HW_SSN_SEQ1_8822C(x) ((x) & (~BITS_HW_SSN_SEQ1_8822C)) +#define BIT_GET_HW_SSN_SEQ1_8822C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822C) & BIT_MASK_HW_SSN_SEQ1_8822C) +#define BIT_SET_HW_SSN_SEQ1_8822C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ1_8822C(x) | BIT_HW_SSN_SEQ1_8822C(v)) + +/* 2 REG_HW_SEQ2_8822C */ + +#define BIT_SHIFT_HW_SSN_SEQ2_8822C 0 +#define BIT_MASK_HW_SSN_SEQ2_8822C 0xfff +#define BIT_HW_SSN_SEQ2_8822C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ2_8822C) << BIT_SHIFT_HW_SSN_SEQ2_8822C) +#define BITS_HW_SSN_SEQ2_8822C \ + (BIT_MASK_HW_SSN_SEQ2_8822C << BIT_SHIFT_HW_SSN_SEQ2_8822C) +#define BIT_CLEAR_HW_SSN_SEQ2_8822C(x) ((x) & (~BITS_HW_SSN_SEQ2_8822C)) +#define BIT_GET_HW_SSN_SEQ2_8822C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822C) & BIT_MASK_HW_SSN_SEQ2_8822C) +#define BIT_SET_HW_SSN_SEQ2_8822C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ2_8822C(x) | BIT_HW_SSN_SEQ2_8822C(v)) + +/* 2 REG_HW_SEQ3_8822C */ + +#define BIT_SHIFT_CSI_HWSEQ_SEL_8822C 12 +#define BIT_MASK_CSI_HWSEQ_SEL_8822C 0x3 +#define BIT_CSI_HWSEQ_SEL_8822C(x) \ + (((x) & BIT_MASK_CSI_HWSEQ_SEL_8822C) << BIT_SHIFT_CSI_HWSEQ_SEL_8822C) +#define BITS_CSI_HWSEQ_SEL_8822C \ + (BIT_MASK_CSI_HWSEQ_SEL_8822C << BIT_SHIFT_CSI_HWSEQ_SEL_8822C) +#define BIT_CLEAR_CSI_HWSEQ_SEL_8822C(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8822C)) +#define BIT_GET_CSI_HWSEQ_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8822C) & BIT_MASK_CSI_HWSEQ_SEL_8822C) +#define BIT_SET_CSI_HWSEQ_SEL_8822C(x, v) \ + (BIT_CLEAR_CSI_HWSEQ_SEL_8822C(x) | BIT_CSI_HWSEQ_SEL_8822C(v)) + +#define BIT_SHIFT_HW_SSN_SEQ3_8822C 0 +#define BIT_MASK_HW_SSN_SEQ3_8822C 0xfff +#define BIT_HW_SSN_SEQ3_8822C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ3_8822C) << BIT_SHIFT_HW_SSN_SEQ3_8822C) +#define BITS_HW_SSN_SEQ3_8822C \ + (BIT_MASK_HW_SSN_SEQ3_8822C << BIT_SHIFT_HW_SSN_SEQ3_8822C) +#define BIT_CLEAR_HW_SSN_SEQ3_8822C(x) ((x) & (~BITS_HW_SSN_SEQ3_8822C)) +#define BIT_GET_HW_SSN_SEQ3_8822C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822C) & BIT_MASK_HW_SSN_SEQ3_8822C) +#define BIT_SET_HW_SSN_SEQ3_8822C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ3_8822C(x) | BIT_HW_SSN_SEQ3_8822C(v)) + +/* 2 REG_NULL_PKT_STATUS_V1_8822C */ + +#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C 2 +#define BIT_MASK_PTCL_TOTAL_PG_V2_8822C 0x3fff +#define BIT_PTCL_TOTAL_PG_V2_8822C(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822C) \ + << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C) +#define BITS_PTCL_TOTAL_PG_V2_8822C \ + (BIT_MASK_PTCL_TOTAL_PG_V2_8822C << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C) +#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8822C(x) \ + ((x) & (~BITS_PTCL_TOTAL_PG_V2_8822C)) +#define BIT_GET_PTCL_TOTAL_PG_V2_8822C(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C) & \ + BIT_MASK_PTCL_TOTAL_PG_V2_8822C) +#define BIT_SET_PTCL_TOTAL_PG_V2_8822C(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V2_8822C(x) | BIT_PTCL_TOTAL_PG_V2_8822C(v)) + +#define BIT_TX_NULL_1_8822C BIT(1) +#define BIT_TX_NULL_0_8822C BIT(0) + +/* 2 REG_PTCL_ERR_STATUS_8822C */ +#define BIT_PTCL_RATE_TABLE_INVALID_8822C BIT(7) +#define BIT_FTM_T2R_ERROR_8822C BIT(6) +#define BIT_PTCL_ERR0_8822C BIT(5) +#define BIT_PTCL_ERR1_8822C BIT(4) +#define BIT_PTCL_ERR2_8822C BIT(3) +#define BIT_PTCL_ERR3_8822C BIT(2) +#define BIT_PTCL_ERR4_8822C BIT(1) +#define BIT_PTCL_ERR5_8822C BIT(0) + +/* 2 REG_NULL_PKT_STATUS_EXTEND_8822C */ +#define BIT_CLI3_TX_NULL_1_8822C BIT(7) +#define BIT_CLI3_TX_NULL_0_8822C BIT(6) +#define BIT_CLI2_TX_NULL_1_8822C BIT(5) +#define BIT_CLI2_TX_NULL_0_8822C BIT(4) +#define BIT_CLI1_TX_NULL_1_8822C BIT(3) +#define BIT_CLI1_TX_NULL_0_8822C BIT(2) +#define BIT_CLI0_TX_NULL_1_8822C BIT(1) +#define BIT_CLI0_TX_NULL_0_8822C BIT(0) + +/* 2 REG_HQMGQ_DROP_8822C */ +#define BIT_HIQ_DROP_8822C BIT(7) +#define BIT_MGQ_DROP_8822C BIT(6) +#define BIT_CLR_HGQ_REQ_BLOCK_8822C BIT(5) + +/* 2 REG_PRECNT_CTRL_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_EN_PRECNT_8822C BIT(11) + +#define BIT_SHIFT_PRECNT_TH_8822C 0 +#define BIT_MASK_PRECNT_TH_8822C 0x7ff +#define BIT_PRECNT_TH_8822C(x) \ + (((x) & BIT_MASK_PRECNT_TH_8822C) << BIT_SHIFT_PRECNT_TH_8822C) +#define BITS_PRECNT_TH_8822C \ + (BIT_MASK_PRECNT_TH_8822C << BIT_SHIFT_PRECNT_TH_8822C) +#define BIT_CLEAR_PRECNT_TH_8822C(x) ((x) & (~BITS_PRECNT_TH_8822C)) +#define BIT_GET_PRECNT_TH_8822C(x) \ + (((x) >> BIT_SHIFT_PRECNT_TH_8822C) & BIT_MASK_PRECNT_TH_8822C) +#define BIT_SET_PRECNT_TH_8822C(x, v) \ + (BIT_CLEAR_PRECNT_TH_8822C(x) | BIT_PRECNT_TH_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_BT_POLLUTE_PKT_CNT_8822C */ + +#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C 0 +#define BIT_MASK_BT_POLLUTE_PKT_CNT_8822C 0xffff +#define BIT_BT_POLLUTE_PKT_CNT_8822C(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822C) \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C) +#define BITS_BT_POLLUTE_PKT_CNT_8822C \ + (BIT_MASK_BT_POLLUTE_PKT_CNT_8822C \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C) +#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822C(x) \ + ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8822C)) +#define BIT_GET_BT_POLLUTE_PKT_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C) & \ + BIT_MASK_BT_POLLUTE_PKT_CNT_8822C) +#define BIT_SET_BT_POLLUTE_PKT_CNT_8822C(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822C(x) | \ + BIT_BT_POLLUTE_PKT_CNT_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_PTCL_DBG_8822C */ + +#define BIT_SHIFT_PTCL_DBG_8822C 0 +#define BIT_MASK_PTCL_DBG_8822C 0xffffffffL +#define BIT_PTCL_DBG_8822C(x) \ + (((x) & BIT_MASK_PTCL_DBG_8822C) << BIT_SHIFT_PTCL_DBG_8822C) +#define BITS_PTCL_DBG_8822C \ + (BIT_MASK_PTCL_DBG_8822C << BIT_SHIFT_PTCL_DBG_8822C) +#define BIT_CLEAR_PTCL_DBG_8822C(x) ((x) & (~BITS_PTCL_DBG_8822C)) +#define BIT_GET_PTCL_DBG_8822C(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_8822C) & BIT_MASK_PTCL_DBG_8822C) +#define BIT_SET_PTCL_DBG_8822C(x, v) \ + (BIT_CLEAR_PTCL_DBG_8822C(x) | BIT_PTCL_DBG_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_CPUMGQ_TIMER_CTRL2_8822C */ + +#define BIT_SHIFT_TRI_HEAD_ADDR_8822C 16 +#define BIT_MASK_TRI_HEAD_ADDR_8822C 0xfff +#define BIT_TRI_HEAD_ADDR_8822C(x) \ + (((x) & BIT_MASK_TRI_HEAD_ADDR_8822C) << BIT_SHIFT_TRI_HEAD_ADDR_8822C) +#define BITS_TRI_HEAD_ADDR_8822C \ + (BIT_MASK_TRI_HEAD_ADDR_8822C << BIT_SHIFT_TRI_HEAD_ADDR_8822C) +#define BIT_CLEAR_TRI_HEAD_ADDR_8822C(x) ((x) & (~BITS_TRI_HEAD_ADDR_8822C)) +#define BIT_GET_TRI_HEAD_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822C) & BIT_MASK_TRI_HEAD_ADDR_8822C) +#define BIT_SET_TRI_HEAD_ADDR_8822C(x, v) \ + (BIT_CLEAR_TRI_HEAD_ADDR_8822C(x) | BIT_TRI_HEAD_ADDR_8822C(v)) + +#define BIT_DROP_TH_EN_8822C BIT(8) + +#define BIT_SHIFT_DROP_TH_8822C 0 +#define BIT_MASK_DROP_TH_8822C 0xff +#define BIT_DROP_TH_8822C(x) \ + (((x) & BIT_MASK_DROP_TH_8822C) << BIT_SHIFT_DROP_TH_8822C) +#define BITS_DROP_TH_8822C (BIT_MASK_DROP_TH_8822C << BIT_SHIFT_DROP_TH_8822C) +#define BIT_CLEAR_DROP_TH_8822C(x) ((x) & (~BITS_DROP_TH_8822C)) +#define BIT_GET_DROP_TH_8822C(x) \ + (((x) >> BIT_SHIFT_DROP_TH_8822C) & BIT_MASK_DROP_TH_8822C) +#define BIT_SET_DROP_TH_8822C(x, v) \ + (BIT_CLEAR_DROP_TH_8822C(x) | BIT_DROP_TH_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_DUMMY_PAGE4_V1_8822C */ + +/* 2 REG_MOREDATA_8822C */ +#define BIT_MOREDATA_CTRL2_EN_V1_8822C BIT(3) +#define BIT_MOREDATA_CTRL1_EN_V1_8822C BIT(2) +#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8822C BIT(0) + +/* 2 REG_Q0_Q1_INFO_8822C */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31) + +#define BIT_SHIFT_GTAB_ID_8822C 28 +#define BIT_MASK_GTAB_ID_8822C 0x7 +#define BIT_GTAB_ID_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C) +#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C) +#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C)) +#define BIT_GET_GTAB_ID_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C) +#define BIT_SET_GTAB_ID_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v)) + +#define BIT_SHIFT_AC1_PKT_INFO_8822C 16 +#define BIT_MASK_AC1_PKT_INFO_8822C 0xfff +#define BIT_AC1_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC1_PKT_INFO_8822C) << BIT_SHIFT_AC1_PKT_INFO_8822C) +#define BITS_AC1_PKT_INFO_8822C \ + (BIT_MASK_AC1_PKT_INFO_8822C << BIT_SHIFT_AC1_PKT_INFO_8822C) +#define BIT_CLEAR_AC1_PKT_INFO_8822C(x) ((x) & (~BITS_AC1_PKT_INFO_8822C)) +#define BIT_GET_AC1_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC1_PKT_INFO_8822C) & BIT_MASK_AC1_PKT_INFO_8822C) +#define BIT_SET_AC1_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC1_PKT_INFO_8822C(x) | BIT_AC1_PKT_INFO_8822C(v)) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8822C 12 +#define BIT_MASK_GTAB_ID_V1_8822C 0x7 +#define BIT_GTAB_ID_V1_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BITS_GTAB_ID_V1_8822C \ + (BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C)) +#define BIT_GET_GTAB_ID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C) +#define BIT_SET_GTAB_ID_V1_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v)) + +#define BIT_SHIFT_AC0_PKT_INFO_8822C 0 +#define BIT_MASK_AC0_PKT_INFO_8822C 0xfff +#define BIT_AC0_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC0_PKT_INFO_8822C) << BIT_SHIFT_AC0_PKT_INFO_8822C) +#define BITS_AC0_PKT_INFO_8822C \ + (BIT_MASK_AC0_PKT_INFO_8822C << BIT_SHIFT_AC0_PKT_INFO_8822C) +#define BIT_CLEAR_AC0_PKT_INFO_8822C(x) ((x) & (~BITS_AC0_PKT_INFO_8822C)) +#define BIT_GET_AC0_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC0_PKT_INFO_8822C) & BIT_MASK_AC0_PKT_INFO_8822C) +#define BIT_SET_AC0_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC0_PKT_INFO_8822C(x) | BIT_AC0_PKT_INFO_8822C(v)) + +/* 2 REG_Q2_Q3_INFO_8822C */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31) + +#define BIT_SHIFT_GTAB_ID_8822C 28 +#define BIT_MASK_GTAB_ID_8822C 0x7 +#define BIT_GTAB_ID_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C) +#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C) +#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C)) +#define BIT_GET_GTAB_ID_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C) +#define BIT_SET_GTAB_ID_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v)) + +#define BIT_SHIFT_AC3_PKT_INFO_8822C 16 +#define BIT_MASK_AC3_PKT_INFO_8822C 0xfff +#define BIT_AC3_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC3_PKT_INFO_8822C) << BIT_SHIFT_AC3_PKT_INFO_8822C) +#define BITS_AC3_PKT_INFO_8822C \ + (BIT_MASK_AC3_PKT_INFO_8822C << BIT_SHIFT_AC3_PKT_INFO_8822C) +#define BIT_CLEAR_AC3_PKT_INFO_8822C(x) ((x) & (~BITS_AC3_PKT_INFO_8822C)) +#define BIT_GET_AC3_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC3_PKT_INFO_8822C) & BIT_MASK_AC3_PKT_INFO_8822C) +#define BIT_SET_AC3_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC3_PKT_INFO_8822C(x) | BIT_AC3_PKT_INFO_8822C(v)) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8822C 12 +#define BIT_MASK_GTAB_ID_V1_8822C 0x7 +#define BIT_GTAB_ID_V1_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BITS_GTAB_ID_V1_8822C \ + (BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C)) +#define BIT_GET_GTAB_ID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C) +#define BIT_SET_GTAB_ID_V1_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v)) + +#define BIT_SHIFT_AC2_PKT_INFO_8822C 0 +#define BIT_MASK_AC2_PKT_INFO_8822C 0xfff +#define BIT_AC2_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC2_PKT_INFO_8822C) << BIT_SHIFT_AC2_PKT_INFO_8822C) +#define BITS_AC2_PKT_INFO_8822C \ + (BIT_MASK_AC2_PKT_INFO_8822C << BIT_SHIFT_AC2_PKT_INFO_8822C) +#define BIT_CLEAR_AC2_PKT_INFO_8822C(x) ((x) & (~BITS_AC2_PKT_INFO_8822C)) +#define BIT_GET_AC2_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC2_PKT_INFO_8822C) & BIT_MASK_AC2_PKT_INFO_8822C) +#define BIT_SET_AC2_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC2_PKT_INFO_8822C(x) | BIT_AC2_PKT_INFO_8822C(v)) + +/* 2 REG_Q4_Q5_INFO_8822C */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31) + +#define BIT_SHIFT_GTAB_ID_8822C 28 +#define BIT_MASK_GTAB_ID_8822C 0x7 +#define BIT_GTAB_ID_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C) +#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C) +#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C)) +#define BIT_GET_GTAB_ID_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C) +#define BIT_SET_GTAB_ID_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v)) + +#define BIT_SHIFT_AC5_PKT_INFO_8822C 16 +#define BIT_MASK_AC5_PKT_INFO_8822C 0xfff +#define BIT_AC5_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC5_PKT_INFO_8822C) << BIT_SHIFT_AC5_PKT_INFO_8822C) +#define BITS_AC5_PKT_INFO_8822C \ + (BIT_MASK_AC5_PKT_INFO_8822C << BIT_SHIFT_AC5_PKT_INFO_8822C) +#define BIT_CLEAR_AC5_PKT_INFO_8822C(x) ((x) & (~BITS_AC5_PKT_INFO_8822C)) +#define BIT_GET_AC5_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC5_PKT_INFO_8822C) & BIT_MASK_AC5_PKT_INFO_8822C) +#define BIT_SET_AC5_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC5_PKT_INFO_8822C(x) | BIT_AC5_PKT_INFO_8822C(v)) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8822C 12 +#define BIT_MASK_GTAB_ID_V1_8822C 0x7 +#define BIT_GTAB_ID_V1_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BITS_GTAB_ID_V1_8822C \ + (BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C)) +#define BIT_GET_GTAB_ID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C) +#define BIT_SET_GTAB_ID_V1_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v)) + +#define BIT_SHIFT_AC4_PKT_INFO_8822C 0 +#define BIT_MASK_AC4_PKT_INFO_8822C 0xfff +#define BIT_AC4_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC4_PKT_INFO_8822C) << BIT_SHIFT_AC4_PKT_INFO_8822C) +#define BITS_AC4_PKT_INFO_8822C \ + (BIT_MASK_AC4_PKT_INFO_8822C << BIT_SHIFT_AC4_PKT_INFO_8822C) +#define BIT_CLEAR_AC4_PKT_INFO_8822C(x) ((x) & (~BITS_AC4_PKT_INFO_8822C)) +#define BIT_GET_AC4_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC4_PKT_INFO_8822C) & BIT_MASK_AC4_PKT_INFO_8822C) +#define BIT_SET_AC4_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC4_PKT_INFO_8822C(x) | BIT_AC4_PKT_INFO_8822C(v)) + +/* 2 REG_Q6_Q7_INFO_8822C */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31) + +#define BIT_SHIFT_GTAB_ID_8822C 28 +#define BIT_MASK_GTAB_ID_8822C 0x7 +#define BIT_GTAB_ID_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C) +#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C) +#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C)) +#define BIT_GET_GTAB_ID_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C) +#define BIT_SET_GTAB_ID_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v)) + +#define BIT_SHIFT_AC7_PKT_INFO_8822C 16 +#define BIT_MASK_AC7_PKT_INFO_8822C 0xfff +#define BIT_AC7_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC7_PKT_INFO_8822C) << BIT_SHIFT_AC7_PKT_INFO_8822C) +#define BITS_AC7_PKT_INFO_8822C \ + (BIT_MASK_AC7_PKT_INFO_8822C << BIT_SHIFT_AC7_PKT_INFO_8822C) +#define BIT_CLEAR_AC7_PKT_INFO_8822C(x) ((x) & (~BITS_AC7_PKT_INFO_8822C)) +#define BIT_GET_AC7_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC7_PKT_INFO_8822C) & BIT_MASK_AC7_PKT_INFO_8822C) +#define BIT_SET_AC7_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC7_PKT_INFO_8822C(x) | BIT_AC7_PKT_INFO_8822C(v)) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8822C 12 +#define BIT_MASK_GTAB_ID_V1_8822C 0x7 +#define BIT_GTAB_ID_V1_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BITS_GTAB_ID_V1_8822C \ + (BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C)) +#define BIT_GET_GTAB_ID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C) +#define BIT_SET_GTAB_ID_V1_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v)) + +#define BIT_SHIFT_AC6_PKT_INFO_8822C 0 +#define BIT_MASK_AC6_PKT_INFO_8822C 0xfff +#define BIT_AC6_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC6_PKT_INFO_8822C) << BIT_SHIFT_AC6_PKT_INFO_8822C) +#define BITS_AC6_PKT_INFO_8822C \ + (BIT_MASK_AC6_PKT_INFO_8822C << BIT_SHIFT_AC6_PKT_INFO_8822C) +#define BIT_CLEAR_AC6_PKT_INFO_8822C(x) ((x) & (~BITS_AC6_PKT_INFO_8822C)) +#define BIT_GET_AC6_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC6_PKT_INFO_8822C) & BIT_MASK_AC6_PKT_INFO_8822C) +#define BIT_SET_AC6_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC6_PKT_INFO_8822C(x) | BIT_AC6_PKT_INFO_8822C(v)) + +/* 2 REG_MGQ_HIQ_INFO_8822C */ + +#define BIT_SHIFT_HIQ_PKT_INFO_8822C 16 +#define BIT_MASK_HIQ_PKT_INFO_8822C 0xfff +#define BIT_HIQ_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_HIQ_PKT_INFO_8822C) << BIT_SHIFT_HIQ_PKT_INFO_8822C) +#define BITS_HIQ_PKT_INFO_8822C \ + (BIT_MASK_HIQ_PKT_INFO_8822C << BIT_SHIFT_HIQ_PKT_INFO_8822C) +#define BIT_CLEAR_HIQ_PKT_INFO_8822C(x) ((x) & (~BITS_HIQ_PKT_INFO_8822C)) +#define BIT_GET_HIQ_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822C) & BIT_MASK_HIQ_PKT_INFO_8822C) +#define BIT_SET_HIQ_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_HIQ_PKT_INFO_8822C(x) | BIT_HIQ_PKT_INFO_8822C(v)) + +#define BIT_SHIFT_MGQ_PKT_INFO_8822C 0 +#define BIT_MASK_MGQ_PKT_INFO_8822C 0xfff +#define BIT_MGQ_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_MGQ_PKT_INFO_8822C) << BIT_SHIFT_MGQ_PKT_INFO_8822C) +#define BITS_MGQ_PKT_INFO_8822C \ + (BIT_MASK_MGQ_PKT_INFO_8822C << BIT_SHIFT_MGQ_PKT_INFO_8822C) +#define BIT_CLEAR_MGQ_PKT_INFO_8822C(x) ((x) & (~BITS_MGQ_PKT_INFO_8822C)) +#define BIT_GET_MGQ_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822C) & BIT_MASK_MGQ_PKT_INFO_8822C) +#define BIT_SET_MGQ_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_MGQ_PKT_INFO_8822C(x) | BIT_MGQ_PKT_INFO_8822C(v)) + +/* 2 REG_CMDQ_BCNQ_INFO_8822C */ + +#define BIT_SHIFT_CMDQ_PKT_INFO_8822C 16 +#define BIT_MASK_CMDQ_PKT_INFO_8822C 0xfff +#define BIT_CMDQ_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_CMDQ_PKT_INFO_8822C) << BIT_SHIFT_CMDQ_PKT_INFO_8822C) +#define BITS_CMDQ_PKT_INFO_8822C \ + (BIT_MASK_CMDQ_PKT_INFO_8822C << BIT_SHIFT_CMDQ_PKT_INFO_8822C) +#define BIT_CLEAR_CMDQ_PKT_INFO_8822C(x) ((x) & (~BITS_CMDQ_PKT_INFO_8822C)) +#define BIT_GET_CMDQ_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822C) & BIT_MASK_CMDQ_PKT_INFO_8822C) +#define BIT_SET_CMDQ_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_CMDQ_PKT_INFO_8822C(x) | BIT_CMDQ_PKT_INFO_8822C(v)) + +#define BIT_SHIFT_BCNQ_PKT_INFO_8822C 0 +#define BIT_MASK_BCNQ_PKT_INFO_8822C 0xfff +#define BIT_BCNQ_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_BCNQ_PKT_INFO_8822C) << BIT_SHIFT_BCNQ_PKT_INFO_8822C) +#define BITS_BCNQ_PKT_INFO_8822C \ + (BIT_MASK_BCNQ_PKT_INFO_8822C << BIT_SHIFT_BCNQ_PKT_INFO_8822C) +#define BIT_CLEAR_BCNQ_PKT_INFO_8822C(x) ((x) & (~BITS_BCNQ_PKT_INFO_8822C)) +#define BIT_GET_BCNQ_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822C) & BIT_MASK_BCNQ_PKT_INFO_8822C) +#define BIT_SET_BCNQ_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_BCNQ_PKT_INFO_8822C(x) | BIT_BCNQ_PKT_INFO_8822C(v)) + +/* 2 REG_USEREG_SETTING_8822C */ +#define BIT_NDPA_USEREG_8822C BIT(21) + +#define BIT_SHIFT_RETRY_USEREG_8822C 19 +#define BIT_MASK_RETRY_USEREG_8822C 0x3 +#define BIT_RETRY_USEREG_8822C(x) \ + (((x) & BIT_MASK_RETRY_USEREG_8822C) << BIT_SHIFT_RETRY_USEREG_8822C) +#define BITS_RETRY_USEREG_8822C \ + (BIT_MASK_RETRY_USEREG_8822C << BIT_SHIFT_RETRY_USEREG_8822C) +#define BIT_CLEAR_RETRY_USEREG_8822C(x) ((x) & (~BITS_RETRY_USEREG_8822C)) +#define BIT_GET_RETRY_USEREG_8822C(x) \ + (((x) >> BIT_SHIFT_RETRY_USEREG_8822C) & BIT_MASK_RETRY_USEREG_8822C) +#define BIT_SET_RETRY_USEREG_8822C(x, v) \ + (BIT_CLEAR_RETRY_USEREG_8822C(x) | BIT_RETRY_USEREG_8822C(v)) + +#define BIT_SHIFT_TRYPKT_USEREG_8822C 17 +#define BIT_MASK_TRYPKT_USEREG_8822C 0x3 +#define BIT_TRYPKT_USEREG_8822C(x) \ + (((x) & BIT_MASK_TRYPKT_USEREG_8822C) << BIT_SHIFT_TRYPKT_USEREG_8822C) +#define BITS_TRYPKT_USEREG_8822C \ + (BIT_MASK_TRYPKT_USEREG_8822C << BIT_SHIFT_TRYPKT_USEREG_8822C) +#define BIT_CLEAR_TRYPKT_USEREG_8822C(x) ((x) & (~BITS_TRYPKT_USEREG_8822C)) +#define BIT_GET_TRYPKT_USEREG_8822C(x) \ + (((x) >> BIT_SHIFT_TRYPKT_USEREG_8822C) & BIT_MASK_TRYPKT_USEREG_8822C) +#define BIT_SET_TRYPKT_USEREG_8822C(x, v) \ + (BIT_CLEAR_TRYPKT_USEREG_8822C(x) | BIT_TRYPKT_USEREG_8822C(v)) + +#define BIT_CTLPKT_USEREG_8822C BIT(16) + +/* 2 REG_AESIV_SETTING_8822C */ + +#define BIT_SHIFT_AESIV_OFFSET_8822C 0 +#define BIT_MASK_AESIV_OFFSET_8822C 0xfff +#define BIT_AESIV_OFFSET_8822C(x) \ + (((x) & BIT_MASK_AESIV_OFFSET_8822C) << BIT_SHIFT_AESIV_OFFSET_8822C) +#define BITS_AESIV_OFFSET_8822C \ + (BIT_MASK_AESIV_OFFSET_8822C << BIT_SHIFT_AESIV_OFFSET_8822C) +#define BIT_CLEAR_AESIV_OFFSET_8822C(x) ((x) & (~BITS_AESIV_OFFSET_8822C)) +#define BIT_GET_AESIV_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_AESIV_OFFSET_8822C) & BIT_MASK_AESIV_OFFSET_8822C) +#define BIT_SET_AESIV_OFFSET_8822C(x, v) \ + (BIT_CLEAR_AESIV_OFFSET_8822C(x) | BIT_AESIV_OFFSET_8822C(v)) + +/* 2 REG_BF0_TIME_SETTING_8822C */ +#define BIT_BF0_TIMER_SET_8822C BIT(31) +#define BIT_BF0_TIMER_CLR_8822C BIT(30) +#define BIT_BF0_UPDATE_EN_8822C BIT(29) +#define BIT_BF0_TIMER_EN_8822C BIT(28) + +#define BIT_SHIFT_BF0_PRETIME_OVER_8822C 16 +#define BIT_MASK_BF0_PRETIME_OVER_8822C 0xfff +#define BIT_BF0_PRETIME_OVER_8822C(x) \ + (((x) & BIT_MASK_BF0_PRETIME_OVER_8822C) \ + << BIT_SHIFT_BF0_PRETIME_OVER_8822C) +#define BITS_BF0_PRETIME_OVER_8822C \ + (BIT_MASK_BF0_PRETIME_OVER_8822C << BIT_SHIFT_BF0_PRETIME_OVER_8822C) +#define BIT_CLEAR_BF0_PRETIME_OVER_8822C(x) \ + ((x) & (~BITS_BF0_PRETIME_OVER_8822C)) +#define BIT_GET_BF0_PRETIME_OVER_8822C(x) \ + (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822C) & \ + BIT_MASK_BF0_PRETIME_OVER_8822C) +#define BIT_SET_BF0_PRETIME_OVER_8822C(x, v) \ + (BIT_CLEAR_BF0_PRETIME_OVER_8822C(x) | BIT_BF0_PRETIME_OVER_8822C(v)) + +#define BIT_SHIFT_BF0_LIFETIME_8822C 0 +#define BIT_MASK_BF0_LIFETIME_8822C 0xffff +#define BIT_BF0_LIFETIME_8822C(x) \ + (((x) & BIT_MASK_BF0_LIFETIME_8822C) << BIT_SHIFT_BF0_LIFETIME_8822C) +#define BITS_BF0_LIFETIME_8822C \ + (BIT_MASK_BF0_LIFETIME_8822C << BIT_SHIFT_BF0_LIFETIME_8822C) +#define BIT_CLEAR_BF0_LIFETIME_8822C(x) ((x) & (~BITS_BF0_LIFETIME_8822C)) +#define BIT_GET_BF0_LIFETIME_8822C(x) \ + (((x) >> BIT_SHIFT_BF0_LIFETIME_8822C) & BIT_MASK_BF0_LIFETIME_8822C) +#define BIT_SET_BF0_LIFETIME_8822C(x, v) \ + (BIT_CLEAR_BF0_LIFETIME_8822C(x) | BIT_BF0_LIFETIME_8822C(v)) + +/* 2 REG_BF1_TIME_SETTING_8822C */ +#define BIT_BF1_TIMER_SET_8822C BIT(31) +#define BIT_BF1_TIMER_CLR_8822C BIT(30) +#define BIT_BF1_UPDATE_EN_8822C BIT(29) +#define BIT_BF1_TIMER_EN_8822C BIT(28) + +#define BIT_SHIFT_BF1_PRETIME_OVER_8822C 16 +#define BIT_MASK_BF1_PRETIME_OVER_8822C 0xfff +#define BIT_BF1_PRETIME_OVER_8822C(x) \ + (((x) & BIT_MASK_BF1_PRETIME_OVER_8822C) \ + << BIT_SHIFT_BF1_PRETIME_OVER_8822C) +#define BITS_BF1_PRETIME_OVER_8822C \ + (BIT_MASK_BF1_PRETIME_OVER_8822C << BIT_SHIFT_BF1_PRETIME_OVER_8822C) +#define BIT_CLEAR_BF1_PRETIME_OVER_8822C(x) \ + ((x) & (~BITS_BF1_PRETIME_OVER_8822C)) +#define BIT_GET_BF1_PRETIME_OVER_8822C(x) \ + (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822C) & \ + BIT_MASK_BF1_PRETIME_OVER_8822C) +#define BIT_SET_BF1_PRETIME_OVER_8822C(x, v) \ + (BIT_CLEAR_BF1_PRETIME_OVER_8822C(x) | BIT_BF1_PRETIME_OVER_8822C(v)) + +#define BIT_SHIFT_BF1_LIFETIME_8822C 0 +#define BIT_MASK_BF1_LIFETIME_8822C 0xffff +#define BIT_BF1_LIFETIME_8822C(x) \ + (((x) & BIT_MASK_BF1_LIFETIME_8822C) << BIT_SHIFT_BF1_LIFETIME_8822C) +#define BITS_BF1_LIFETIME_8822C \ + (BIT_MASK_BF1_LIFETIME_8822C << BIT_SHIFT_BF1_LIFETIME_8822C) +#define BIT_CLEAR_BF1_LIFETIME_8822C(x) ((x) & (~BITS_BF1_LIFETIME_8822C)) +#define BIT_GET_BF1_LIFETIME_8822C(x) \ + (((x) >> BIT_SHIFT_BF1_LIFETIME_8822C) & BIT_MASK_BF1_LIFETIME_8822C) +#define BIT_SET_BF1_LIFETIME_8822C(x, v) \ + (BIT_CLEAR_BF1_LIFETIME_8822C(x) | BIT_BF1_LIFETIME_8822C(v)) + +/* 2 REG_BF_TIMEOUT_EN_8822C */ +#define BIT_EN_VHT_LDPC_8822C BIT(9) +#define BIT_EN_HT_LDPC_8822C BIT(8) +#define BIT_BF1_TIMEOUT_EN_8822C BIT(1) +#define BIT_BF0_TIMEOUT_EN_8822C BIT(0) + +/* 2 REG_MACID_RELEASE0_8822C */ + +#define BIT_SHIFT_MACID31_0_RELEASE_8822C 0 +#define BIT_MASK_MACID31_0_RELEASE_8822C 0xffffffffL +#define BIT_MACID31_0_RELEASE_8822C(x) \ + (((x) & BIT_MASK_MACID31_0_RELEASE_8822C) \ + << BIT_SHIFT_MACID31_0_RELEASE_8822C) +#define BITS_MACID31_0_RELEASE_8822C \ + (BIT_MASK_MACID31_0_RELEASE_8822C << BIT_SHIFT_MACID31_0_RELEASE_8822C) +#define BIT_CLEAR_MACID31_0_RELEASE_8822C(x) \ + ((x) & (~BITS_MACID31_0_RELEASE_8822C)) +#define BIT_GET_MACID31_0_RELEASE_8822C(x) \ + (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822C) & \ + BIT_MASK_MACID31_0_RELEASE_8822C) +#define BIT_SET_MACID31_0_RELEASE_8822C(x, v) \ + (BIT_CLEAR_MACID31_0_RELEASE_8822C(x) | BIT_MACID31_0_RELEASE_8822C(v)) + +/* 2 REG_MACID_RELEASE1_8822C */ + +#define BIT_SHIFT_MACID63_32_RELEASE_8822C 0 +#define BIT_MASK_MACID63_32_RELEASE_8822C 0xffffffffL +#define BIT_MACID63_32_RELEASE_8822C(x) \ + (((x) & BIT_MASK_MACID63_32_RELEASE_8822C) \ + << BIT_SHIFT_MACID63_32_RELEASE_8822C) +#define BITS_MACID63_32_RELEASE_8822C \ + (BIT_MASK_MACID63_32_RELEASE_8822C \ + << BIT_SHIFT_MACID63_32_RELEASE_8822C) +#define BIT_CLEAR_MACID63_32_RELEASE_8822C(x) \ + ((x) & (~BITS_MACID63_32_RELEASE_8822C)) +#define BIT_GET_MACID63_32_RELEASE_8822C(x) \ + (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822C) & \ + BIT_MASK_MACID63_32_RELEASE_8822C) +#define BIT_SET_MACID63_32_RELEASE_8822C(x, v) \ + (BIT_CLEAR_MACID63_32_RELEASE_8822C(x) | \ + BIT_MACID63_32_RELEASE_8822C(v)) + +/* 2 REG_MACID_RELEASE2_8822C */ + +#define BIT_SHIFT_MACID95_64_RELEASE_8822C 0 +#define BIT_MASK_MACID95_64_RELEASE_8822C 0xffffffffL +#define BIT_MACID95_64_RELEASE_8822C(x) \ + (((x) & BIT_MASK_MACID95_64_RELEASE_8822C) \ + << BIT_SHIFT_MACID95_64_RELEASE_8822C) +#define BITS_MACID95_64_RELEASE_8822C \ + (BIT_MASK_MACID95_64_RELEASE_8822C \ + << BIT_SHIFT_MACID95_64_RELEASE_8822C) +#define BIT_CLEAR_MACID95_64_RELEASE_8822C(x) \ + ((x) & (~BITS_MACID95_64_RELEASE_8822C)) +#define BIT_GET_MACID95_64_RELEASE_8822C(x) \ + (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822C) & \ + BIT_MASK_MACID95_64_RELEASE_8822C) +#define BIT_SET_MACID95_64_RELEASE_8822C(x, v) \ + (BIT_CLEAR_MACID95_64_RELEASE_8822C(x) | \ + BIT_MACID95_64_RELEASE_8822C(v)) + +/* 2 REG_MACID_RELEASE3_8822C */ + +#define BIT_SHIFT_MACID127_96_RELEASE_8822C 0 +#define BIT_MASK_MACID127_96_RELEASE_8822C 0xffffffffL +#define BIT_MACID127_96_RELEASE_8822C(x) \ + (((x) & BIT_MASK_MACID127_96_RELEASE_8822C) \ + << BIT_SHIFT_MACID127_96_RELEASE_8822C) +#define BITS_MACID127_96_RELEASE_8822C \ + (BIT_MASK_MACID127_96_RELEASE_8822C \ + << BIT_SHIFT_MACID127_96_RELEASE_8822C) +#define BIT_CLEAR_MACID127_96_RELEASE_8822C(x) \ + ((x) & (~BITS_MACID127_96_RELEASE_8822C)) +#define BIT_GET_MACID127_96_RELEASE_8822C(x) \ + (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822C) & \ + BIT_MASK_MACID127_96_RELEASE_8822C) +#define BIT_SET_MACID127_96_RELEASE_8822C(x, v) \ + (BIT_CLEAR_MACID127_96_RELEASE_8822C(x) | \ + BIT_MACID127_96_RELEASE_8822C(v)) + +/* 2 REG_MACID_RELEASE_SETTING_8822C */ +#define BIT_MACID_VALUE_8822C BIT(7) + +#define BIT_SHIFT_MACID_OFFSET_8822C 0 +#define BIT_MASK_MACID_OFFSET_8822C 0x7f +#define BIT_MACID_OFFSET_8822C(x) \ + (((x) & BIT_MASK_MACID_OFFSET_8822C) << BIT_SHIFT_MACID_OFFSET_8822C) +#define BITS_MACID_OFFSET_8822C \ + (BIT_MASK_MACID_OFFSET_8822C << BIT_SHIFT_MACID_OFFSET_8822C) +#define BIT_CLEAR_MACID_OFFSET_8822C(x) ((x) & (~BITS_MACID_OFFSET_8822C)) +#define BIT_GET_MACID_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_MACID_OFFSET_8822C) & BIT_MASK_MACID_OFFSET_8822C) +#define BIT_SET_MACID_OFFSET_8822C(x, v) \ + (BIT_CLEAR_MACID_OFFSET_8822C(x) | BIT_MACID_OFFSET_8822C(v)) + +/* 2 REG_FAST_EDCA_VOVI_SETTING_8822C */ + +#define BIT_SHIFT_VI_FAST_EDCA_TO_8822C 24 +#define BIT_MASK_VI_FAST_EDCA_TO_8822C 0xff +#define BIT_VI_FAST_EDCA_TO_8822C(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_TO_8822C) \ + << BIT_SHIFT_VI_FAST_EDCA_TO_8822C) +#define BITS_VI_FAST_EDCA_TO_8822C \ + (BIT_MASK_VI_FAST_EDCA_TO_8822C << BIT_SHIFT_VI_FAST_EDCA_TO_8822C) +#define BIT_CLEAR_VI_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8822C)) +#define BIT_GET_VI_FAST_EDCA_TO_8822C(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822C) & \ + BIT_MASK_VI_FAST_EDCA_TO_8822C) +#define BIT_SET_VI_FAST_EDCA_TO_8822C(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_TO_8822C(x) | BIT_VI_FAST_EDCA_TO_8822C(v)) + +#define BIT_VI_THRESHOLD_SEL_8822C BIT(23) + +#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C 16 +#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C 0x7f +#define BIT_VI_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C) \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C) +#define BITS_VI_FAST_EDCA_PKT_TH_8822C \ + (BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822C(x) \ + ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8822C)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C) & \ + BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C) +#define BIT_SET_VI_FAST_EDCA_PKT_TH_8822C(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822C(x) | \ + BIT_VI_FAST_EDCA_PKT_TH_8822C(v)) + +#define BIT_SHIFT_VO_FAST_EDCA_TO_8822C 8 +#define BIT_MASK_VO_FAST_EDCA_TO_8822C 0xff +#define BIT_VO_FAST_EDCA_TO_8822C(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO_8822C) \ + << BIT_SHIFT_VO_FAST_EDCA_TO_8822C) +#define BITS_VO_FAST_EDCA_TO_8822C \ + (BIT_MASK_VO_FAST_EDCA_TO_8822C << BIT_SHIFT_VO_FAST_EDCA_TO_8822C) +#define BIT_CLEAR_VO_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8822C)) +#define BIT_GET_VO_FAST_EDCA_TO_8822C(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822C) & \ + BIT_MASK_VO_FAST_EDCA_TO_8822C) +#define BIT_SET_VO_FAST_EDCA_TO_8822C(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO_8822C(x) | BIT_VO_FAST_EDCA_TO_8822C(v)) + +#define BIT_VO_THRESHOLD_SEL_8822C BIT(7) + +#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C 0 +#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C 0x7f +#define BIT_VO_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C) \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C) +#define BITS_VO_FAST_EDCA_PKT_TH_8822C \ + (BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822C(x) \ + ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8822C)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C) & \ + BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C) +#define BIT_SET_VO_FAST_EDCA_PKT_TH_8822C(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822C(x) | \ + BIT_VO_FAST_EDCA_PKT_TH_8822C(v)) + +/* 2 REG_FAST_EDCA_BEBK_SETTING_8822C */ + +#define BIT_SHIFT_BK_FAST_EDCA_TO_8822C 24 +#define BIT_MASK_BK_FAST_EDCA_TO_8822C 0xff +#define BIT_BK_FAST_EDCA_TO_8822C(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_TO_8822C) \ + << BIT_SHIFT_BK_FAST_EDCA_TO_8822C) +#define BITS_BK_FAST_EDCA_TO_8822C \ + (BIT_MASK_BK_FAST_EDCA_TO_8822C << BIT_SHIFT_BK_FAST_EDCA_TO_8822C) +#define BIT_CLEAR_BK_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8822C)) +#define BIT_GET_BK_FAST_EDCA_TO_8822C(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822C) & \ + BIT_MASK_BK_FAST_EDCA_TO_8822C) +#define BIT_SET_BK_FAST_EDCA_TO_8822C(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_TO_8822C(x) | BIT_BK_FAST_EDCA_TO_8822C(v)) + +#define BIT_BK_THRESHOLD_SEL_8822C BIT(23) + +#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C 16 +#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C 0x7f +#define BIT_BK_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C) \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C) +#define BITS_BK_FAST_EDCA_PKT_TH_8822C \ + (BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822C(x) \ + ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8822C)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C) & \ + BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C) +#define BIT_SET_BK_FAST_EDCA_PKT_TH_8822C(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822C(x) | \ + BIT_BK_FAST_EDCA_PKT_TH_8822C(v)) + +#define BIT_SHIFT_BE_FAST_EDCA_TO_8822C 8 +#define BIT_MASK_BE_FAST_EDCA_TO_8822C 0xff +#define BIT_BE_FAST_EDCA_TO_8822C(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO_8822C) \ + << BIT_SHIFT_BE_FAST_EDCA_TO_8822C) +#define BITS_BE_FAST_EDCA_TO_8822C \ + (BIT_MASK_BE_FAST_EDCA_TO_8822C << BIT_SHIFT_BE_FAST_EDCA_TO_8822C) +#define BIT_CLEAR_BE_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8822C)) +#define BIT_GET_BE_FAST_EDCA_TO_8822C(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822C) & \ + BIT_MASK_BE_FAST_EDCA_TO_8822C) +#define BIT_SET_BE_FAST_EDCA_TO_8822C(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO_8822C(x) | BIT_BE_FAST_EDCA_TO_8822C(v)) + +#define BIT_BE_THRESHOLD_SEL_8822C BIT(7) + +#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C 0 +#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C 0x7f +#define BIT_BE_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C) \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C) +#define BITS_BE_FAST_EDCA_PKT_TH_8822C \ + (BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822C(x) \ + ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8822C)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C) & \ + BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C) +#define BIT_SET_BE_FAST_EDCA_PKT_TH_8822C(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822C(x) | \ + BIT_BE_FAST_EDCA_PKT_TH_8822C(v)) + +/* 2 REG_MACID_DROP0_8822C */ + +#define BIT_SHIFT_MACID31_0_DROP_8822C 0 +#define BIT_MASK_MACID31_0_DROP_8822C 0xffffffffL +#define BIT_MACID31_0_DROP_8822C(x) \ + (((x) & BIT_MASK_MACID31_0_DROP_8822C) \ + << BIT_SHIFT_MACID31_0_DROP_8822C) +#define BITS_MACID31_0_DROP_8822C \ + (BIT_MASK_MACID31_0_DROP_8822C << BIT_SHIFT_MACID31_0_DROP_8822C) +#define BIT_CLEAR_MACID31_0_DROP_8822C(x) ((x) & (~BITS_MACID31_0_DROP_8822C)) +#define BIT_GET_MACID31_0_DROP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID31_0_DROP_8822C) & \ + BIT_MASK_MACID31_0_DROP_8822C) +#define BIT_SET_MACID31_0_DROP_8822C(x, v) \ + (BIT_CLEAR_MACID31_0_DROP_8822C(x) | BIT_MACID31_0_DROP_8822C(v)) + +/* 2 REG_MACID_DROP1_8822C */ + +#define BIT_SHIFT_MACID63_32_DROP_8822C 0 +#define BIT_MASK_MACID63_32_DROP_8822C 0xffffffffL +#define BIT_MACID63_32_DROP_8822C(x) \ + (((x) & BIT_MASK_MACID63_32_DROP_8822C) \ + << BIT_SHIFT_MACID63_32_DROP_8822C) +#define BITS_MACID63_32_DROP_8822C \ + (BIT_MASK_MACID63_32_DROP_8822C << BIT_SHIFT_MACID63_32_DROP_8822C) +#define BIT_CLEAR_MACID63_32_DROP_8822C(x) ((x) & (~BITS_MACID63_32_DROP_8822C)) +#define BIT_GET_MACID63_32_DROP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID63_32_DROP_8822C) & \ + BIT_MASK_MACID63_32_DROP_8822C) +#define BIT_SET_MACID63_32_DROP_8822C(x, v) \ + (BIT_CLEAR_MACID63_32_DROP_8822C(x) | BIT_MACID63_32_DROP_8822C(v)) + +/* 2 REG_MACID_DROP2_8822C */ + +#define BIT_SHIFT_MACID95_64_DROP_8822C 0 +#define BIT_MASK_MACID95_64_DROP_8822C 0xffffffffL +#define BIT_MACID95_64_DROP_8822C(x) \ + (((x) & BIT_MASK_MACID95_64_DROP_8822C) \ + << BIT_SHIFT_MACID95_64_DROP_8822C) +#define BITS_MACID95_64_DROP_8822C \ + (BIT_MASK_MACID95_64_DROP_8822C << BIT_SHIFT_MACID95_64_DROP_8822C) +#define BIT_CLEAR_MACID95_64_DROP_8822C(x) ((x) & (~BITS_MACID95_64_DROP_8822C)) +#define BIT_GET_MACID95_64_DROP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID95_64_DROP_8822C) & \ + BIT_MASK_MACID95_64_DROP_8822C) +#define BIT_SET_MACID95_64_DROP_8822C(x, v) \ + (BIT_CLEAR_MACID95_64_DROP_8822C(x) | BIT_MACID95_64_DROP_8822C(v)) + +/* 2 REG_MACID_DROP3_8822C */ + +#define BIT_SHIFT_MACID127_96_DROP_8822C 0 +#define BIT_MASK_MACID127_96_DROP_8822C 0xffffffffL +#define BIT_MACID127_96_DROP_8822C(x) \ + (((x) & BIT_MASK_MACID127_96_DROP_8822C) \ + << BIT_SHIFT_MACID127_96_DROP_8822C) +#define BITS_MACID127_96_DROP_8822C \ + (BIT_MASK_MACID127_96_DROP_8822C << BIT_SHIFT_MACID127_96_DROP_8822C) +#define BIT_CLEAR_MACID127_96_DROP_8822C(x) \ + ((x) & (~BITS_MACID127_96_DROP_8822C)) +#define BIT_GET_MACID127_96_DROP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID127_96_DROP_8822C) & \ + BIT_MASK_MACID127_96_DROP_8822C) +#define BIT_SET_MACID127_96_DROP_8822C(x, v) \ + (BIT_CLEAR_MACID127_96_DROP_8822C(x) | BIT_MACID127_96_DROP_8822C(v)) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8822C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_0_8822C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C) +#define BITS_R_MACID_RELEASE_SUCCESS_0_8822C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8822C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8822C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_0_8822C(v)) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8822C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_1_8822C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C) +#define BITS_R_MACID_RELEASE_SUCCESS_1_8822C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8822C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8822C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_1_8822C(v)) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8822C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_2_8822C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C) +#define BITS_R_MACID_RELEASE_SUCCESS_2_8822C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8822C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8822C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_2_8822C(v)) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8822C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_3_8822C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C) +#define BITS_R_MACID_RELEASE_SUCCESS_3_8822C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8822C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8822C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_3_8822C(v)) + +/* 2 REG_MGQ_FIFO_WRITE_POINTER_8822C */ +#define BIT_MGQ_FIFO_OV_8822C BIT(7) +#define BIT_MGQ_FIFO_WPTR_ERROR_8822C BIT(6) +#define BIT_EN_MGQ_FIFO_LIFETIME_8822C BIT(5) + +#define BIT_SHIFT_MGQ_FIFO_WPTR_8822C 0 +#define BIT_MASK_MGQ_FIFO_WPTR_8822C 0x1f +#define BIT_MGQ_FIFO_WPTR_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_WPTR_8822C) << BIT_SHIFT_MGQ_FIFO_WPTR_8822C) +#define BITS_MGQ_FIFO_WPTR_8822C \ + (BIT_MASK_MGQ_FIFO_WPTR_8822C << BIT_SHIFT_MGQ_FIFO_WPTR_8822C) +#define BIT_CLEAR_MGQ_FIFO_WPTR_8822C(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8822C)) +#define BIT_GET_MGQ_FIFO_WPTR_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8822C) & BIT_MASK_MGQ_FIFO_WPTR_8822C) +#define BIT_SET_MGQ_FIFO_WPTR_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_WPTR_8822C(x) | BIT_MGQ_FIFO_WPTR_8822C(v)) + +/* 2 REG_MGQ_FIFO_READ_POINTER_8822C */ + +#define BIT_SHIFT_MGQ_FIFO_SIZE_8822C 14 +#define BIT_MASK_MGQ_FIFO_SIZE_8822C 0x3 +#define BIT_MGQ_FIFO_SIZE_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_SIZE_8822C) << BIT_SHIFT_MGQ_FIFO_SIZE_8822C) +#define BITS_MGQ_FIFO_SIZE_8822C \ + (BIT_MASK_MGQ_FIFO_SIZE_8822C << BIT_SHIFT_MGQ_FIFO_SIZE_8822C) +#define BIT_CLEAR_MGQ_FIFO_SIZE_8822C(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8822C)) +#define BIT_GET_MGQ_FIFO_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8822C) & BIT_MASK_MGQ_FIFO_SIZE_8822C) +#define BIT_SET_MGQ_FIFO_SIZE_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_SIZE_8822C(x) | BIT_MGQ_FIFO_SIZE_8822C(v)) + +#define BIT_MGQ_FIFO_PAUSE_8822C BIT(13) + +#define BIT_SHIFT_MGQ_FIFO_RPTR_8822C 8 +#define BIT_MASK_MGQ_FIFO_RPTR_8822C 0x1f +#define BIT_MGQ_FIFO_RPTR_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_RPTR_8822C) << BIT_SHIFT_MGQ_FIFO_RPTR_8822C) +#define BITS_MGQ_FIFO_RPTR_8822C \ + (BIT_MASK_MGQ_FIFO_RPTR_8822C << BIT_SHIFT_MGQ_FIFO_RPTR_8822C) +#define BIT_CLEAR_MGQ_FIFO_RPTR_8822C(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8822C)) +#define BIT_GET_MGQ_FIFO_RPTR_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8822C) & BIT_MASK_MGQ_FIFO_RPTR_8822C) +#define BIT_SET_MGQ_FIFO_RPTR_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_RPTR_8822C(x) | BIT_MGQ_FIFO_RPTR_8822C(v)) + +/* 2 REG_MGQ_FIFO_ENABLE_8822C */ +#define BIT_MGQ_FIFO_EN_8822C BIT(15) + +#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C 12 +#define BIT_MASK_MGQ_FIFO_PG_SIZE_8822C 0x7 +#define BIT_MGQ_FIFO_PG_SIZE_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8822C) \ + << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C) +#define BITS_MGQ_FIFO_PG_SIZE_8822C \ + (BIT_MASK_MGQ_FIFO_PG_SIZE_8822C << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C) +#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8822C(x) \ + ((x) & (~BITS_MGQ_FIFO_PG_SIZE_8822C)) +#define BIT_GET_MGQ_FIFO_PG_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C) & \ + BIT_MASK_MGQ_FIFO_PG_SIZE_8822C) +#define BIT_SET_MGQ_FIFO_PG_SIZE_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PG_SIZE_8822C(x) | BIT_MGQ_FIFO_PG_SIZE_8822C(v)) + +#define BIT_SHIFT_MGQ_FIFO_START_PG_8822C 0 +#define BIT_MASK_MGQ_FIFO_START_PG_8822C 0xfff +#define BIT_MGQ_FIFO_START_PG_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_START_PG_8822C) \ + << BIT_SHIFT_MGQ_FIFO_START_PG_8822C) +#define BITS_MGQ_FIFO_START_PG_8822C \ + (BIT_MASK_MGQ_FIFO_START_PG_8822C << BIT_SHIFT_MGQ_FIFO_START_PG_8822C) +#define BIT_CLEAR_MGQ_FIFO_START_PG_8822C(x) \ + ((x) & (~BITS_MGQ_FIFO_START_PG_8822C)) +#define BIT_GET_MGQ_FIFO_START_PG_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8822C) & \ + BIT_MASK_MGQ_FIFO_START_PG_8822C) +#define BIT_SET_MGQ_FIFO_START_PG_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_START_PG_8822C(x) | BIT_MGQ_FIFO_START_PG_8822C(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8822C */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C 0xffff +#define BIT_MGQ_FIFO_REL_INT_MASK_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C) +#define BITS_MGQ_FIFO_REL_INT_MASK_8822C \ + (BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8822C(x) \ + ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8822C)) +#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C) & \ + BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C) +#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8822C(x) | \ + BIT_MGQ_FIFO_REL_INT_MASK_8822C(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8822C */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C 0xffff +#define BIT_MGQ_FIFO_REL_INT_FLAG_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C) +#define BITS_MGQ_FIFO_REL_INT_FLAG_8822C \ + (BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8822C(x) \ + ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8822C)) +#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C) & \ + BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C) +#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8822C(x) | \ + BIT_MGQ_FIFO_REL_INT_FLAG_8822C(v)) + +/* 2 REG_MGQ_FIFO_VALID_MAP_8822C */ + +#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C 0 +#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C 0xffff +#define BIT_MGQ_FIFO_PKT_VALID_MAP_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C) \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C) +#define BITS_MGQ_FIFO_PKT_VALID_MAP_8822C \ + (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C) +#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8822C(x) \ + ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8822C)) +#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C) & \ + BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C) +#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8822C(x) | \ + BIT_MGQ_FIFO_PKT_VALID_MAP_8822C(v)) + +/* 2 REG_MGQ_FIFO_LIFETIME_8822C */ + +#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C 0 +#define BIT_MASK_MGQ_FIFO_LIFETIME_8822C 0xffff +#define BIT_MGQ_FIFO_LIFETIME_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8822C) \ + << BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C) +#define BITS_MGQ_FIFO_LIFETIME_8822C \ + (BIT_MASK_MGQ_FIFO_LIFETIME_8822C << BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C) +#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8822C(x) \ + ((x) & (~BITS_MGQ_FIFO_LIFETIME_8822C)) +#define BIT_GET_MGQ_FIFO_LIFETIME_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C) & \ + BIT_MASK_MGQ_FIFO_LIFETIME_8822C) +#define BIT_SET_MGQ_FIFO_LIFETIME_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_LIFETIME_8822C(x) | BIT_MGQ_FIFO_LIFETIME_8822C(v)) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0x7f +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) +#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(v)) + +/* 2 REG_SHCUT_SETTING_8822C */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE0_8822C */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE1_8822C */ + +/* 2 REG_SHCUT_LLC_OUI0_8822C */ + +/* 2 REG_SHCUT_LLC_OUI1_8822C */ + +/* 2 REG_SHCUT_LLC_OUI2_8822C */ + +/* 2 REG_MU_TX_CTL_8822C */ +#define BIT_R_MU_P1_WAIT_STATE_EN_8822C BIT(16) + +#define BIT_SHIFT_R_MU_RL_8822C 12 +#define BIT_MASK_R_MU_RL_8822C 0xf +#define BIT_R_MU_RL_8822C(x) \ + (((x) & BIT_MASK_R_MU_RL_8822C) << BIT_SHIFT_R_MU_RL_8822C) +#define BITS_R_MU_RL_8822C (BIT_MASK_R_MU_RL_8822C << BIT_SHIFT_R_MU_RL_8822C) +#define BIT_CLEAR_R_MU_RL_8822C(x) ((x) & (~BITS_R_MU_RL_8822C)) +#define BIT_GET_R_MU_RL_8822C(x) \ + (((x) >> BIT_SHIFT_R_MU_RL_8822C) & BIT_MASK_R_MU_RL_8822C) +#define BIT_SET_R_MU_RL_8822C(x, v) \ + (BIT_CLEAR_R_MU_RL_8822C(x) | BIT_R_MU_RL_8822C(v)) + +#define BIT_R_FORCE_P1_RATEDOWN_8822C BIT(11) + +#define BIT_SHIFT_R_MU_TAB_SEL_8822C 8 +#define BIT_MASK_R_MU_TAB_SEL_8822C 0x7 +#define BIT_R_MU_TAB_SEL_8822C(x) \ + (((x) & BIT_MASK_R_MU_TAB_SEL_8822C) << BIT_SHIFT_R_MU_TAB_SEL_8822C) +#define BITS_R_MU_TAB_SEL_8822C \ + (BIT_MASK_R_MU_TAB_SEL_8822C << BIT_SHIFT_R_MU_TAB_SEL_8822C) +#define BIT_CLEAR_R_MU_TAB_SEL_8822C(x) ((x) & (~BITS_R_MU_TAB_SEL_8822C)) +#define BIT_GET_R_MU_TAB_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8822C) & BIT_MASK_R_MU_TAB_SEL_8822C) +#define BIT_SET_R_MU_TAB_SEL_8822C(x, v) \ + (BIT_CLEAR_R_MU_TAB_SEL_8822C(x) | BIT_R_MU_TAB_SEL_8822C(v)) + +#define BIT_R_EN_MU_MIMO_8822C BIT(7) +#define BIT_R_EN_REVERS_GTAB_8822C BIT(6) + +#define BIT_SHIFT_R_MU_TABLE_VALID_8822C 0 +#define BIT_MASK_R_MU_TABLE_VALID_8822C 0x3f +#define BIT_R_MU_TABLE_VALID_8822C(x) \ + (((x) & BIT_MASK_R_MU_TABLE_VALID_8822C) \ + << BIT_SHIFT_R_MU_TABLE_VALID_8822C) +#define BITS_R_MU_TABLE_VALID_8822C \ + (BIT_MASK_R_MU_TABLE_VALID_8822C << BIT_SHIFT_R_MU_TABLE_VALID_8822C) +#define BIT_CLEAR_R_MU_TABLE_VALID_8822C(x) \ + ((x) & (~BITS_R_MU_TABLE_VALID_8822C)) +#define BIT_GET_R_MU_TABLE_VALID_8822C(x) \ + (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822C) & \ + BIT_MASK_R_MU_TABLE_VALID_8822C) +#define BIT_SET_R_MU_TABLE_VALID_8822C(x, v) \ + (BIT_CLEAR_R_MU_TABLE_VALID_8822C(x) | BIT_R_MU_TABLE_VALID_8822C(v)) + +/* 2 REG_MU_STA_GID_VLD_8822C */ + +#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C 0 +#define BIT_MASK_R_MU_STA_GTAB_VALID_8822C 0xffffffffL +#define BIT_R_MU_STA_GTAB_VALID_8822C(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822C) \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C) +#define BITS_R_MU_STA_GTAB_VALID_8822C \ + (BIT_MASK_R_MU_STA_GTAB_VALID_8822C \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822C(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822C)) +#define BIT_GET_R_MU_STA_GTAB_VALID_8822C(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C) & \ + BIT_MASK_R_MU_STA_GTAB_VALID_8822C) +#define BIT_SET_R_MU_STA_GTAB_VALID_8822C(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822C(x) | \ + BIT_R_MU_STA_GTAB_VALID_8822C(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_8822C */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C 0xffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_L_8822C(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C) +#define BITS_R_MU_STA_GTAB_POSITION_L_8822C \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8822C(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_L_8822C)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_L_8822C(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C) +#define BIT_SET_R_MU_STA_GTAB_POSITION_L_8822C(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8822C(x) | \ + BIT_R_MU_STA_GTAB_POSITION_L_8822C(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_H_8822C */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C 0xffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_H_8822C(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C) +#define BITS_R_MU_STA_GTAB_POSITION_H_8822C \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8822C(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_H_8822C)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_H_8822C(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C) +#define BIT_SET_R_MU_STA_GTAB_POSITION_H_8822C(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8822C(x) | \ + BIT_R_MU_STA_GTAB_POSITION_H_8822C(v)) + +/* 2 REG_CHNL_INFO_CTRL_8822C */ +#define BIT_CHNL_REF_RXNAV_8822C BIT(7) +#define BIT_CHNL_REF_VBON_8822C BIT(6) +#define BIT_CHNL_REF_EDCA_8822C BIT(5) +#define BIT_CHNL_REF_CCA_8822C BIT(4) +#define BIT_RST_CHNL_BUSY_8822C BIT(3) +#define BIT_RST_CHNL_IDLE_8822C BIT(2) +#define BIT_CHNL_INFO_RST_8822C BIT(1) +#define BIT_ATM_AIRTIME_EN_8822C BIT(0) + +/* 2 REG_CHNL_IDLE_TIME_8822C */ + +#define BIT_SHIFT_CHNL_IDLE_TIME_8822C 0 +#define BIT_MASK_CHNL_IDLE_TIME_8822C 0xffffffffL +#define BIT_CHNL_IDLE_TIME_8822C(x) \ + (((x) & BIT_MASK_CHNL_IDLE_TIME_8822C) \ + << BIT_SHIFT_CHNL_IDLE_TIME_8822C) +#define BITS_CHNL_IDLE_TIME_8822C \ + (BIT_MASK_CHNL_IDLE_TIME_8822C << BIT_SHIFT_CHNL_IDLE_TIME_8822C) +#define BIT_CLEAR_CHNL_IDLE_TIME_8822C(x) ((x) & (~BITS_CHNL_IDLE_TIME_8822C)) +#define BIT_GET_CHNL_IDLE_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8822C) & \ + BIT_MASK_CHNL_IDLE_TIME_8822C) +#define BIT_SET_CHNL_IDLE_TIME_8822C(x, v) \ + (BIT_CLEAR_CHNL_IDLE_TIME_8822C(x) | BIT_CHNL_IDLE_TIME_8822C(v)) + +/* 2 REG_CHNL_BUSY_TIME_8822C */ + +#define BIT_SHIFT_CHNL_BUSY_TIME_8822C 0 +#define BIT_MASK_CHNL_BUSY_TIME_8822C 0xffffffffL +#define BIT_CHNL_BUSY_TIME_8822C(x) \ + (((x) & BIT_MASK_CHNL_BUSY_TIME_8822C) \ + << BIT_SHIFT_CHNL_BUSY_TIME_8822C) +#define BITS_CHNL_BUSY_TIME_8822C \ + (BIT_MASK_CHNL_BUSY_TIME_8822C << BIT_SHIFT_CHNL_BUSY_TIME_8822C) +#define BIT_CLEAR_CHNL_BUSY_TIME_8822C(x) ((x) & (~BITS_CHNL_BUSY_TIME_8822C)) +#define BIT_GET_CHNL_BUSY_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8822C) & \ + BIT_MASK_CHNL_BUSY_TIME_8822C) +#define BIT_SET_CHNL_BUSY_TIME_8822C(x, v) \ + (BIT_CLEAR_CHNL_BUSY_TIME_8822C(x) | BIT_CHNL_BUSY_TIME_8822C(v)) + +/* 2 REG_MU_TRX_DBG_CNT_V1_8822C */ +#define BIT_MU_DNGCNT_RST_8822C BIT(20) + +#define BIT_SHIFT_MU_DNGCNT_SEL_8822C 16 +#define BIT_MASK_MU_DNGCNT_SEL_8822C 0xf +#define BIT_MU_DNGCNT_SEL_8822C(x) \ + (((x) & BIT_MASK_MU_DNGCNT_SEL_8822C) << BIT_SHIFT_MU_DNGCNT_SEL_8822C) +#define BITS_MU_DNGCNT_SEL_8822C \ + (BIT_MASK_MU_DNGCNT_SEL_8822C << BIT_SHIFT_MU_DNGCNT_SEL_8822C) +#define BIT_CLEAR_MU_DNGCNT_SEL_8822C(x) ((x) & (~BITS_MU_DNGCNT_SEL_8822C)) +#define BIT_GET_MU_DNGCNT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_SEL_8822C) & BIT_MASK_MU_DNGCNT_SEL_8822C) +#define BIT_SET_MU_DNGCNT_SEL_8822C(x, v) \ + (BIT_CLEAR_MU_DNGCNT_SEL_8822C(x) | BIT_MU_DNGCNT_SEL_8822C(v)) + +#define BIT_SHIFT_MU_DNGCNT_8822C 0 +#define BIT_MASK_MU_DNGCNT_8822C 0xffff +#define BIT_MU_DNGCNT_8822C(x) \ + (((x) & BIT_MASK_MU_DNGCNT_8822C) << BIT_SHIFT_MU_DNGCNT_8822C) +#define BITS_MU_DNGCNT_8822C \ + (BIT_MASK_MU_DNGCNT_8822C << BIT_SHIFT_MU_DNGCNT_8822C) +#define BIT_CLEAR_MU_DNGCNT_8822C(x) ((x) & (~BITS_MU_DNGCNT_8822C)) +#define BIT_GET_MU_DNGCNT_8822C(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_8822C) & BIT_MASK_MU_DNGCNT_8822C) +#define BIT_SET_MU_DNGCNT_8822C(x, v) \ + (BIT_CLEAR_MU_DNGCNT_8822C(x) | BIT_MU_DNGCNT_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_EDCA_VO_PARAM_8822C */ + +#define BIT_SHIFT_TXOPLIMIT_8822C 16 +#define BIT_MASK_TXOPLIMIT_8822C 0x7ff +#define BIT_TXOPLIMIT_8822C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C) +#define BITS_TXOPLIMIT_8822C \ + (BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C) +#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C)) +#define BIT_GET_TXOPLIMIT_8822C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C) +#define BIT_SET_TXOPLIMIT_8822C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v)) + +#define BIT_SHIFT_CW_8822C 8 +#define BIT_MASK_CW_8822C 0xff +#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C) +#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C) +#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C)) +#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C) +#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v)) + +#define BIT_SHIFT_AIFS_8822C 0 +#define BIT_MASK_AIFS_8822C 0xff +#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C) +#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C) +#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C)) +#define BIT_GET_AIFS_8822C(x) \ + (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C) +#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v)) + +/* 2 REG_EDCA_VI_PARAM_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_TXOPLIMIT_8822C 16 +#define BIT_MASK_TXOPLIMIT_8822C 0x7ff +#define BIT_TXOPLIMIT_8822C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C) +#define BITS_TXOPLIMIT_8822C \ + (BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C) +#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C)) +#define BIT_GET_TXOPLIMIT_8822C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C) +#define BIT_SET_TXOPLIMIT_8822C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v)) + +#define BIT_SHIFT_CW_8822C 8 +#define BIT_MASK_CW_8822C 0xff +#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C) +#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C) +#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C)) +#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C) +#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v)) + +#define BIT_SHIFT_AIFS_8822C 0 +#define BIT_MASK_AIFS_8822C 0xff +#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C) +#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C) +#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C)) +#define BIT_GET_AIFS_8822C(x) \ + (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C) +#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v)) + +/* 2 REG_EDCA_BE_PARAM_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_TXOPLIMIT_8822C 16 +#define BIT_MASK_TXOPLIMIT_8822C 0x7ff +#define BIT_TXOPLIMIT_8822C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C) +#define BITS_TXOPLIMIT_8822C \ + (BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C) +#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C)) +#define BIT_GET_TXOPLIMIT_8822C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C) +#define BIT_SET_TXOPLIMIT_8822C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v)) + +#define BIT_SHIFT_CW_8822C 8 +#define BIT_MASK_CW_8822C 0xff +#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C) +#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C) +#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C)) +#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C) +#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v)) + +#define BIT_SHIFT_AIFS_8822C 0 +#define BIT_MASK_AIFS_8822C 0xff +#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C) +#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C) +#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C)) +#define BIT_GET_AIFS_8822C(x) \ + (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C) +#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v)) + +/* 2 REG_EDCA_BK_PARAM_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_TXOPLIMIT_8822C 16 +#define BIT_MASK_TXOPLIMIT_8822C 0x7ff +#define BIT_TXOPLIMIT_8822C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C) +#define BITS_TXOPLIMIT_8822C \ + (BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C) +#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C)) +#define BIT_GET_TXOPLIMIT_8822C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C) +#define BIT_SET_TXOPLIMIT_8822C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v)) + +#define BIT_SHIFT_CW_8822C 8 +#define BIT_MASK_CW_8822C 0xff +#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C) +#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C) +#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C)) +#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C) +#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v)) + +#define BIT_SHIFT_AIFS_8822C 0 +#define BIT_MASK_AIFS_8822C 0xff +#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C) +#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C) +#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C)) +#define BIT_GET_AIFS_8822C(x) \ + (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C) +#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v)) + +/* 2 REG_BCNTCFG_8822C */ + +#define BIT_SHIFT_BCNCW_MAX_8822C 12 +#define BIT_MASK_BCNCW_MAX_8822C 0xf +#define BIT_BCNCW_MAX_8822C(x) \ + (((x) & BIT_MASK_BCNCW_MAX_8822C) << BIT_SHIFT_BCNCW_MAX_8822C) +#define BITS_BCNCW_MAX_8822C \ + (BIT_MASK_BCNCW_MAX_8822C << BIT_SHIFT_BCNCW_MAX_8822C) +#define BIT_CLEAR_BCNCW_MAX_8822C(x) ((x) & (~BITS_BCNCW_MAX_8822C)) +#define BIT_GET_BCNCW_MAX_8822C(x) \ + (((x) >> BIT_SHIFT_BCNCW_MAX_8822C) & BIT_MASK_BCNCW_MAX_8822C) +#define BIT_SET_BCNCW_MAX_8822C(x, v) \ + (BIT_CLEAR_BCNCW_MAX_8822C(x) | BIT_BCNCW_MAX_8822C(v)) + +#define BIT_SHIFT_BCNCW_MIN_8822C 8 +#define BIT_MASK_BCNCW_MIN_8822C 0xf +#define BIT_BCNCW_MIN_8822C(x) \ + (((x) & BIT_MASK_BCNCW_MIN_8822C) << BIT_SHIFT_BCNCW_MIN_8822C) +#define BITS_BCNCW_MIN_8822C \ + (BIT_MASK_BCNCW_MIN_8822C << BIT_SHIFT_BCNCW_MIN_8822C) +#define BIT_CLEAR_BCNCW_MIN_8822C(x) ((x) & (~BITS_BCNCW_MIN_8822C)) +#define BIT_GET_BCNCW_MIN_8822C(x) \ + (((x) >> BIT_SHIFT_BCNCW_MIN_8822C) & BIT_MASK_BCNCW_MIN_8822C) +#define BIT_SET_BCNCW_MIN_8822C(x, v) \ + (BIT_CLEAR_BCNCW_MIN_8822C(x) | BIT_BCNCW_MIN_8822C(v)) + +#define BIT_SHIFT_BCNIFS_8822C 0 +#define BIT_MASK_BCNIFS_8822C 0xff +#define BIT_BCNIFS_8822C(x) \ + (((x) & BIT_MASK_BCNIFS_8822C) << BIT_SHIFT_BCNIFS_8822C) +#define BITS_BCNIFS_8822C (BIT_MASK_BCNIFS_8822C << BIT_SHIFT_BCNIFS_8822C) +#define BIT_CLEAR_BCNIFS_8822C(x) ((x) & (~BITS_BCNIFS_8822C)) +#define BIT_GET_BCNIFS_8822C(x) \ + (((x) >> BIT_SHIFT_BCNIFS_8822C) & BIT_MASK_BCNIFS_8822C) +#define BIT_SET_BCNIFS_8822C(x, v) \ + (BIT_CLEAR_BCNIFS_8822C(x) | BIT_BCNIFS_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_PIFS_8822C */ + +#define BIT_SHIFT_PIFS_8822C 0 +#define BIT_MASK_PIFS_8822C 0xff +#define BIT_PIFS_8822C(x) (((x) & BIT_MASK_PIFS_8822C) << BIT_SHIFT_PIFS_8822C) +#define BITS_PIFS_8822C (BIT_MASK_PIFS_8822C << BIT_SHIFT_PIFS_8822C) +#define BIT_CLEAR_PIFS_8822C(x) ((x) & (~BITS_PIFS_8822C)) +#define BIT_GET_PIFS_8822C(x) \ + (((x) >> BIT_SHIFT_PIFS_8822C) & BIT_MASK_PIFS_8822C) +#define BIT_SET_PIFS_8822C(x, v) (BIT_CLEAR_PIFS_8822C(x) | BIT_PIFS_8822C(v)) + +/* 2 REG_RDG_PIFS_8822C */ + +#define BIT_SHIFT_RDG_PIFS_8822C 0 +#define BIT_MASK_RDG_PIFS_8822C 0xff +#define BIT_RDG_PIFS_8822C(x) \ + (((x) & BIT_MASK_RDG_PIFS_8822C) << BIT_SHIFT_RDG_PIFS_8822C) +#define BITS_RDG_PIFS_8822C \ + (BIT_MASK_RDG_PIFS_8822C << BIT_SHIFT_RDG_PIFS_8822C) +#define BIT_CLEAR_RDG_PIFS_8822C(x) ((x) & (~BITS_RDG_PIFS_8822C)) +#define BIT_GET_RDG_PIFS_8822C(x) \ + (((x) >> BIT_SHIFT_RDG_PIFS_8822C) & BIT_MASK_RDG_PIFS_8822C) +#define BIT_SET_RDG_PIFS_8822C(x, v) \ + (BIT_CLEAR_RDG_PIFS_8822C(x) | BIT_RDG_PIFS_8822C(v)) + +/* 2 REG_SIFS_8822C */ + +#define BIT_SHIFT_SIFS_OFDM_TRX_8822C 24 +#define BIT_MASK_SIFS_OFDM_TRX_8822C 0xff +#define BIT_SIFS_OFDM_TRX_8822C(x) \ + (((x) & BIT_MASK_SIFS_OFDM_TRX_8822C) << BIT_SHIFT_SIFS_OFDM_TRX_8822C) +#define BITS_SIFS_OFDM_TRX_8822C \ + (BIT_MASK_SIFS_OFDM_TRX_8822C << BIT_SHIFT_SIFS_OFDM_TRX_8822C) +#define BIT_CLEAR_SIFS_OFDM_TRX_8822C(x) ((x) & (~BITS_SIFS_OFDM_TRX_8822C)) +#define BIT_GET_SIFS_OFDM_TRX_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822C) & BIT_MASK_SIFS_OFDM_TRX_8822C) +#define BIT_SET_SIFS_OFDM_TRX_8822C(x, v) \ + (BIT_CLEAR_SIFS_OFDM_TRX_8822C(x) | BIT_SIFS_OFDM_TRX_8822C(v)) + +#define BIT_SHIFT_SIFS_CCK_TRX_8822C 16 +#define BIT_MASK_SIFS_CCK_TRX_8822C 0xff +#define BIT_SIFS_CCK_TRX_8822C(x) \ + (((x) & BIT_MASK_SIFS_CCK_TRX_8822C) << BIT_SHIFT_SIFS_CCK_TRX_8822C) +#define BITS_SIFS_CCK_TRX_8822C \ + (BIT_MASK_SIFS_CCK_TRX_8822C << BIT_SHIFT_SIFS_CCK_TRX_8822C) +#define BIT_CLEAR_SIFS_CCK_TRX_8822C(x) ((x) & (~BITS_SIFS_CCK_TRX_8822C)) +#define BIT_GET_SIFS_CCK_TRX_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822C) & BIT_MASK_SIFS_CCK_TRX_8822C) +#define BIT_SET_SIFS_CCK_TRX_8822C(x, v) \ + (BIT_CLEAR_SIFS_CCK_TRX_8822C(x) | BIT_SIFS_CCK_TRX_8822C(v)) + +#define BIT_SHIFT_SIFS_OFDM_CTX_8822C 8 +#define BIT_MASK_SIFS_OFDM_CTX_8822C 0xff +#define BIT_SIFS_OFDM_CTX_8822C(x) \ + (((x) & BIT_MASK_SIFS_OFDM_CTX_8822C) << BIT_SHIFT_SIFS_OFDM_CTX_8822C) +#define BITS_SIFS_OFDM_CTX_8822C \ + (BIT_MASK_SIFS_OFDM_CTX_8822C << BIT_SHIFT_SIFS_OFDM_CTX_8822C) +#define BIT_CLEAR_SIFS_OFDM_CTX_8822C(x) ((x) & (~BITS_SIFS_OFDM_CTX_8822C)) +#define BIT_GET_SIFS_OFDM_CTX_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822C) & BIT_MASK_SIFS_OFDM_CTX_8822C) +#define BIT_SET_SIFS_OFDM_CTX_8822C(x, v) \ + (BIT_CLEAR_SIFS_OFDM_CTX_8822C(x) | BIT_SIFS_OFDM_CTX_8822C(v)) + +#define BIT_SHIFT_SIFS_CCK_CTX_8822C 0 +#define BIT_MASK_SIFS_CCK_CTX_8822C 0xff +#define BIT_SIFS_CCK_CTX_8822C(x) \ + (((x) & BIT_MASK_SIFS_CCK_CTX_8822C) << BIT_SHIFT_SIFS_CCK_CTX_8822C) +#define BITS_SIFS_CCK_CTX_8822C \ + (BIT_MASK_SIFS_CCK_CTX_8822C << BIT_SHIFT_SIFS_CCK_CTX_8822C) +#define BIT_CLEAR_SIFS_CCK_CTX_8822C(x) ((x) & (~BITS_SIFS_CCK_CTX_8822C)) +#define BIT_GET_SIFS_CCK_CTX_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822C) & BIT_MASK_SIFS_CCK_CTX_8822C) +#define BIT_SET_SIFS_CCK_CTX_8822C(x, v) \ + (BIT_CLEAR_SIFS_CCK_CTX_8822C(x) | BIT_SIFS_CCK_CTX_8822C(v)) + +/* 2 REG_TSFTR_SYN_OFFSET_8822C */ + +#define BIT_SHIFT_TSFTR_SNC_OFFSET_8822C 0 +#define BIT_MASK_TSFTR_SNC_OFFSET_8822C 0xffff +#define BIT_TSFTR_SNC_OFFSET_8822C(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822C) \ + << BIT_SHIFT_TSFTR_SNC_OFFSET_8822C) +#define BITS_TSFTR_SNC_OFFSET_8822C \ + (BIT_MASK_TSFTR_SNC_OFFSET_8822C << BIT_SHIFT_TSFTR_SNC_OFFSET_8822C) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_8822C(x) \ + ((x) & (~BITS_TSFTR_SNC_OFFSET_8822C)) +#define BIT_GET_TSFTR_SNC_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822C) & \ + BIT_MASK_TSFTR_SNC_OFFSET_8822C) +#define BIT_SET_TSFTR_SNC_OFFSET_8822C(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET_8822C(x) | BIT_TSFTR_SNC_OFFSET_8822C(v)) + +/* 2 REG_AGGR_BREAK_TIME_8822C */ + +#define BIT_SHIFT_AGGR_BK_TIME_8822C 0 +#define BIT_MASK_AGGR_BK_TIME_8822C 0xff +#define BIT_AGGR_BK_TIME_8822C(x) \ + (((x) & BIT_MASK_AGGR_BK_TIME_8822C) << BIT_SHIFT_AGGR_BK_TIME_8822C) +#define BITS_AGGR_BK_TIME_8822C \ + (BIT_MASK_AGGR_BK_TIME_8822C << BIT_SHIFT_AGGR_BK_TIME_8822C) +#define BIT_CLEAR_AGGR_BK_TIME_8822C(x) ((x) & (~BITS_AGGR_BK_TIME_8822C)) +#define BIT_GET_AGGR_BK_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_AGGR_BK_TIME_8822C) & BIT_MASK_AGGR_BK_TIME_8822C) +#define BIT_SET_AGGR_BK_TIME_8822C(x, v) \ + (BIT_CLEAR_AGGR_BK_TIME_8822C(x) | BIT_AGGR_BK_TIME_8822C(v)) + +/* 2 REG_SLOT_8822C */ + +#define BIT_SHIFT_SLOT_8822C 0 +#define BIT_MASK_SLOT_8822C 0xff +#define BIT_SLOT_8822C(x) (((x) & BIT_MASK_SLOT_8822C) << BIT_SHIFT_SLOT_8822C) +#define BITS_SLOT_8822C (BIT_MASK_SLOT_8822C << BIT_SHIFT_SLOT_8822C) +#define BIT_CLEAR_SLOT_8822C(x) ((x) & (~BITS_SLOT_8822C)) +#define BIT_GET_SLOT_8822C(x) \ + (((x) >> BIT_SHIFT_SLOT_8822C) & BIT_MASK_SLOT_8822C) +#define BIT_SET_SLOT_8822C(x, v) (BIT_CLEAR_SLOT_8822C(x) | BIT_SLOT_8822C(v)) + +/* 2 REG_NOA_ON_ERLY_TIME_8822C */ + +#define BIT_SHIFT__NOA_ON_ERLY_TIME_8822C 0 +#define BIT_MASK__NOA_ON_ERLY_TIME_8822C 0xff +#define BIT__NOA_ON_ERLY_TIME_8822C(x) \ + (((x) & BIT_MASK__NOA_ON_ERLY_TIME_8822C) \ + << BIT_SHIFT__NOA_ON_ERLY_TIME_8822C) +#define BITS__NOA_ON_ERLY_TIME_8822C \ + (BIT_MASK__NOA_ON_ERLY_TIME_8822C << BIT_SHIFT__NOA_ON_ERLY_TIME_8822C) +#define BIT_CLEAR__NOA_ON_ERLY_TIME_8822C(x) \ + ((x) & (~BITS__NOA_ON_ERLY_TIME_8822C)) +#define BIT_GET__NOA_ON_ERLY_TIME_8822C(x) \ + (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8822C) & \ + BIT_MASK__NOA_ON_ERLY_TIME_8822C) +#define BIT_SET__NOA_ON_ERLY_TIME_8822C(x, v) \ + (BIT_CLEAR__NOA_ON_ERLY_TIME_8822C(x) | BIT__NOA_ON_ERLY_TIME_8822C(v)) + +/* 2 REG_NOA_OFF_ERLY_TIME_8822C */ + +#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C 0 +#define BIT_MASK__NOA_OFF_ERLY_TIME_8822C 0xff +#define BIT__NOA_OFF_ERLY_TIME_8822C(x) \ + (((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8822C) \ + << BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C) +#define BITS__NOA_OFF_ERLY_TIME_8822C \ + (BIT_MASK__NOA_OFF_ERLY_TIME_8822C \ + << BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C) +#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8822C(x) \ + ((x) & (~BITS__NOA_OFF_ERLY_TIME_8822C)) +#define BIT_GET__NOA_OFF_ERLY_TIME_8822C(x) \ + (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C) & \ + BIT_MASK__NOA_OFF_ERLY_TIME_8822C) +#define BIT_SET__NOA_OFF_ERLY_TIME_8822C(x, v) \ + (BIT_CLEAR__NOA_OFF_ERLY_TIME_8822C(x) | \ + BIT__NOA_OFF_ERLY_TIME_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_TX_PTCL_CTRL_8822C */ +#define BIT_DIS_EDCCA_8822C BIT(15) +#define BIT_DIS_CCA_8822C BIT(14) +#define BIT_LSIG_TXOP_TXCMD_NAV_8822C BIT(13) +#define BIT_SIFS_BK_EN_8822C BIT(12) + +#define BIT_SHIFT_TXQ_NAV_MSK_8822C 8 +#define BIT_MASK_TXQ_NAV_MSK_8822C 0xf +#define BIT_TXQ_NAV_MSK_8822C(x) \ + (((x) & BIT_MASK_TXQ_NAV_MSK_8822C) << BIT_SHIFT_TXQ_NAV_MSK_8822C) +#define BITS_TXQ_NAV_MSK_8822C \ + (BIT_MASK_TXQ_NAV_MSK_8822C << BIT_SHIFT_TXQ_NAV_MSK_8822C) +#define BIT_CLEAR_TXQ_NAV_MSK_8822C(x) ((x) & (~BITS_TXQ_NAV_MSK_8822C)) +#define BIT_GET_TXQ_NAV_MSK_8822C(x) \ + (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822C) & BIT_MASK_TXQ_NAV_MSK_8822C) +#define BIT_SET_TXQ_NAV_MSK_8822C(x, v) \ + (BIT_CLEAR_TXQ_NAV_MSK_8822C(x) | BIT_TXQ_NAV_MSK_8822C(v)) + +#define BIT_DIS_CW_8822C BIT(7) +#define BIT_NAV_END_TXOP_8822C BIT(6) +#define BIT_RDG_END_TXOP_8822C BIT(5) +#define BIT_AC_INBCN_HOLD_8822C BIT(4) +#define BIT_MGTQ_TXOP_EN_8822C BIT(3) +#define BIT_MGTQ_RTSMF_EN_8822C BIT(2) +#define BIT_HIQ_RTSMF_EN_8822C BIT(1) +#define BIT_BCN_RTSMF_EN_8822C BIT(0) + +/* 2 REG_TXPAUSE_8822C */ +#define BIT_STOP_BCN_HI_MGT_8822C BIT(7) +#define BIT_MAC_STOPBCNQ_8822C BIT(6) +#define BIT_MAC_STOPHIQ_8822C BIT(5) +#define BIT_MAC_STOPMGQ_8822C BIT(4) +#define BIT_MAC_STOPBK_8822C BIT(3) +#define BIT_MAC_STOPBE_8822C BIT(2) +#define BIT_MAC_STOPVI_8822C BIT(1) +#define BIT_MAC_STOPVO_8822C BIT(0) + +/* 2 REG_DIS_TXREQ_CLR_8822C */ +#define BIT_DIS_BT_CCA_8822C BIT(7) +#define BIT_DIS_TXREQ_CLR_HI_8822C BIT(5) +#define BIT_DIS_TXREQ_CLR_MGQ_8822C BIT(4) +#define BIT_DIS_TXREQ_CLR_VO_8822C BIT(3) +#define BIT_DIS_TXREQ_CLR_VI_8822C BIT(2) +#define BIT_DIS_TXREQ_CLR_BE_8822C BIT(1) +#define BIT_DIS_TXREQ_CLR_BK_8822C BIT(0) + +/* 2 REG_RD_CTRL_8822C */ +#define BIT_EN_CLR_TXREQ_INCCA_8822C BIT(15) +#define BIT_DIS_TX_OVER_BCNQ_8822C BIT(14) +#define BIT_EN_BCNERR_INCCCA_8822C BIT(13) +#define BIT_EDCCA_MSK_CNTDOWN_EN_8822C BIT(11) +#define BIT_DIS_TXOP_CFE_8822C BIT(10) +#define BIT_DIS_LSIG_CFE_8822C BIT(9) +#define BIT_DIS_STBC_CFE_8822C BIT(8) +#define BIT_BKQ_RD_INIT_EN_8822C BIT(7) +#define BIT_BEQ_RD_INIT_EN_8822C BIT(6) +#define BIT_VIQ_RD_INIT_EN_8822C BIT(5) +#define BIT_VOQ_RD_INIT_EN_8822C BIT(4) +#define BIT_BKQ_RD_RESP_EN_8822C BIT(3) +#define BIT_BEQ_RD_RESP_EN_8822C BIT(2) +#define BIT_VIQ_RD_RESP_EN_8822C BIT(1) +#define BIT_VOQ_RD_RESP_EN_8822C BIT(0) + +/* 2 REG_MBSSID_CTRL_8822C */ +#define BIT_MBID_BCNQ7_EN_8822C BIT(7) +#define BIT_MBID_BCNQ6_EN_8822C BIT(6) +#define BIT_MBID_BCNQ5_EN_8822C BIT(5) +#define BIT_MBID_BCNQ4_EN_8822C BIT(4) +#define BIT_MBID_BCNQ3_EN_8822C BIT(3) +#define BIT_MBID_BCNQ2_EN_8822C BIT(2) +#define BIT_MBID_BCNQ1_EN_8822C BIT(1) +#define BIT_MBID_BCNQ0_EN_8822C BIT(0) + +/* 2 REG_P2PPS_CTRL_8822C */ +#define BIT_P2P_CTW_ALLSTASLEEP_8822C BIT(7) +#define BIT_P2P_OFF_DISTX_EN_8822C BIT(6) +#define BIT_PWR_MGT_EN_8822C BIT(5) +#define BIT_P2P_NOA1_EN_8822C BIT(2) +#define BIT_P2P_NOA0_EN_8822C BIT(1) + +/* 2 REG_PKT_LIFETIME_CTRL_8822C */ +#define BIT_EN_P2P_CTWND1_8822C BIT(23) +#define BIT_EN_BKF_CLR_TXREQ_8822C BIT(22) +#define BIT_EN_TSFBIT32_RST_P2P_8822C BIT(21) +#define BIT_EN_BCN_TX_BTCCA_8822C BIT(20) +#define BIT_DIS_PKT_TX_ATIM_8822C BIT(19) +#define BIT_DIS_BCN_DIS_CTN_8822C BIT(18) +#define BIT_EN_NAVEND_RST_TXOP_8822C BIT(17) +#define BIT_EN_FILTER_CCA_8822C BIT(16) + +#define BIT_SHIFT_CCA_FILTER_THRS_8822C 8 +#define BIT_MASK_CCA_FILTER_THRS_8822C 0xff +#define BIT_CCA_FILTER_THRS_8822C(x) \ + (((x) & BIT_MASK_CCA_FILTER_THRS_8822C) \ + << BIT_SHIFT_CCA_FILTER_THRS_8822C) +#define BITS_CCA_FILTER_THRS_8822C \ + (BIT_MASK_CCA_FILTER_THRS_8822C << BIT_SHIFT_CCA_FILTER_THRS_8822C) +#define BIT_CLEAR_CCA_FILTER_THRS_8822C(x) ((x) & (~BITS_CCA_FILTER_THRS_8822C)) +#define BIT_GET_CCA_FILTER_THRS_8822C(x) \ + (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822C) & \ + BIT_MASK_CCA_FILTER_THRS_8822C) +#define BIT_SET_CCA_FILTER_THRS_8822C(x, v) \ + (BIT_CLEAR_CCA_FILTER_THRS_8822C(x) | BIT_CCA_FILTER_THRS_8822C(v)) + +#define BIT_SHIFT_EDCCA_THRS_8822C 0 +#define BIT_MASK_EDCCA_THRS_8822C 0xff +#define BIT_EDCCA_THRS_8822C(x) \ + (((x) & BIT_MASK_EDCCA_THRS_8822C) << BIT_SHIFT_EDCCA_THRS_8822C) +#define BITS_EDCCA_THRS_8822C \ + (BIT_MASK_EDCCA_THRS_8822C << BIT_SHIFT_EDCCA_THRS_8822C) +#define BIT_CLEAR_EDCCA_THRS_8822C(x) ((x) & (~BITS_EDCCA_THRS_8822C)) +#define BIT_GET_EDCCA_THRS_8822C(x) \ + (((x) >> BIT_SHIFT_EDCCA_THRS_8822C) & BIT_MASK_EDCCA_THRS_8822C) +#define BIT_SET_EDCCA_THRS_8822C(x, v) \ + (BIT_CLEAR_EDCCA_THRS_8822C(x) | BIT_EDCCA_THRS_8822C(v)) + +/* 2 REG_P2PPS_SPEC_STATE_8822C */ +#define BIT_SPEC_POWER_STATE_8822C BIT(7) +#define BIT_SPEC_CTWINDOW_ON_8822C BIT(6) +#define BIT_SPEC_BEACON_AREA_ON_8822C BIT(5) +#define BIT_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4) +#define BIT_SPEC_NOA1_OFF_PERIOD_8822C BIT(3) +#define BIT_SPEC_FORCE_DOZE1_8822C BIT(2) +#define BIT_SPEC_NOA0_OFF_PERIOD_8822C BIT(1) +#define BIT_SPEC_FORCE_DOZE0_8822C BIT(0) + +/* 2 REG_TXOP_LIMIT_CTRL_8822C */ + +#define BIT_SHIFT_TXOP_TBTT_CNT_8822C 24 +#define BIT_MASK_TXOP_TBTT_CNT_8822C 0xff +#define BIT_TXOP_TBTT_CNT_8822C(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_8822C) << BIT_SHIFT_TXOP_TBTT_CNT_8822C) +#define BITS_TXOP_TBTT_CNT_8822C \ + (BIT_MASK_TXOP_TBTT_CNT_8822C << BIT_SHIFT_TXOP_TBTT_CNT_8822C) +#define BIT_CLEAR_TXOP_TBTT_CNT_8822C(x) ((x) & (~BITS_TXOP_TBTT_CNT_8822C)) +#define BIT_GET_TXOP_TBTT_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8822C) & BIT_MASK_TXOP_TBTT_CNT_8822C) +#define BIT_SET_TXOP_TBTT_CNT_8822C(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_8822C(x) | BIT_TXOP_TBTT_CNT_8822C(v)) + +#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C 20 +#define BIT_MASK_TXOP_TBTT_CNT_SEL_8822C 0xf +#define BIT_TXOP_TBTT_CNT_SEL_8822C(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8822C) \ + << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C) +#define BITS_TXOP_TBTT_CNT_SEL_8822C \ + (BIT_MASK_TXOP_TBTT_CNT_SEL_8822C << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C) +#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822C(x) \ + ((x) & (~BITS_TXOP_TBTT_CNT_SEL_8822C)) +#define BIT_GET_TXOP_TBTT_CNT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C) & \ + BIT_MASK_TXOP_TBTT_CNT_SEL_8822C) +#define BIT_SET_TXOP_TBTT_CNT_SEL_8822C(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822C(x) | BIT_TXOP_TBTT_CNT_SEL_8822C(v)) + +#define BIT_SHIFT_TXOP_LMT_EN_8822C 16 +#define BIT_MASK_TXOP_LMT_EN_8822C 0xf +#define BIT_TXOP_LMT_EN_8822C(x) \ + (((x) & BIT_MASK_TXOP_LMT_EN_8822C) << BIT_SHIFT_TXOP_LMT_EN_8822C) +#define BITS_TXOP_LMT_EN_8822C \ + (BIT_MASK_TXOP_LMT_EN_8822C << BIT_SHIFT_TXOP_LMT_EN_8822C) +#define BIT_CLEAR_TXOP_LMT_EN_8822C(x) ((x) & (~BITS_TXOP_LMT_EN_8822C)) +#define BIT_GET_TXOP_LMT_EN_8822C(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_EN_8822C) & BIT_MASK_TXOP_LMT_EN_8822C) +#define BIT_SET_TXOP_LMT_EN_8822C(x, v) \ + (BIT_CLEAR_TXOP_LMT_EN_8822C(x) | BIT_TXOP_LMT_EN_8822C(v)) + +#define BIT_SHIFT_TXOP_LMT_TX_TIME_8822C 8 +#define BIT_MASK_TXOP_LMT_TX_TIME_8822C 0xff +#define BIT_TXOP_LMT_TX_TIME_8822C(x) \ + (((x) & BIT_MASK_TXOP_LMT_TX_TIME_8822C) \ + << BIT_SHIFT_TXOP_LMT_TX_TIME_8822C) +#define BITS_TXOP_LMT_TX_TIME_8822C \ + (BIT_MASK_TXOP_LMT_TX_TIME_8822C << BIT_SHIFT_TXOP_LMT_TX_TIME_8822C) +#define BIT_CLEAR_TXOP_LMT_TX_TIME_8822C(x) \ + ((x) & (~BITS_TXOP_LMT_TX_TIME_8822C)) +#define BIT_GET_TXOP_LMT_TX_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8822C) & \ + BIT_MASK_TXOP_LMT_TX_TIME_8822C) +#define BIT_SET_TXOP_LMT_TX_TIME_8822C(x, v) \ + (BIT_CLEAR_TXOP_LMT_TX_TIME_8822C(x) | BIT_TXOP_LMT_TX_TIME_8822C(v)) + +#define BIT_TXOP_CNT_TRIGGER_RESET_8822C BIT(7) + +#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C 0 +#define BIT_MASK_TXOP_LMT_PKT_NUM_8822C 0x3f +#define BIT_TXOP_LMT_PKT_NUM_8822C(x) \ + (((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8822C) \ + << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C) +#define BITS_TXOP_LMT_PKT_NUM_8822C \ + (BIT_MASK_TXOP_LMT_PKT_NUM_8822C << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C) +#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8822C(x) \ + ((x) & (~BITS_TXOP_LMT_PKT_NUM_8822C)) +#define BIT_GET_TXOP_LMT_PKT_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C) & \ + BIT_MASK_TXOP_LMT_PKT_NUM_8822C) +#define BIT_SET_TXOP_LMT_PKT_NUM_8822C(x, v) \ + (BIT_CLEAR_TXOP_LMT_PKT_NUM_8822C(x) | BIT_TXOP_LMT_PKT_NUM_8822C(v)) + +/* 2 REG_BAR_TX_CTRL_8822C */ + +/* 2 REG_P2PON_DIS_TXTIME_8822C */ + +#define BIT_SHIFT_P2PON_DIS_TXTIME_8822C 0 +#define BIT_MASK_P2PON_DIS_TXTIME_8822C 0xff +#define BIT_P2PON_DIS_TXTIME_8822C(x) \ + (((x) & BIT_MASK_P2PON_DIS_TXTIME_8822C) \ + << BIT_SHIFT_P2PON_DIS_TXTIME_8822C) +#define BITS_P2PON_DIS_TXTIME_8822C \ + (BIT_MASK_P2PON_DIS_TXTIME_8822C << BIT_SHIFT_P2PON_DIS_TXTIME_8822C) +#define BIT_CLEAR_P2PON_DIS_TXTIME_8822C(x) \ + ((x) & (~BITS_P2PON_DIS_TXTIME_8822C)) +#define BIT_GET_P2PON_DIS_TXTIME_8822C(x) \ + (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822C) & \ + BIT_MASK_P2PON_DIS_TXTIME_8822C) +#define BIT_SET_P2PON_DIS_TXTIME_8822C(x, v) \ + (BIT_CLEAR_P2PON_DIS_TXTIME_8822C(x) | BIT_P2PON_DIS_TXTIME_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_CCA_TXEN_CNT_8822C */ +#define BIT_CCA_TXEN_CNT_SWITCH_8822C BIT(17) +#define BIT_CCA_TXEN_CNT_EN_8822C BIT(16) + +#define BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C 8 +#define BIT_MASK_CCA_TXEN_BIG_CNT_8822C 0xff +#define BIT_CCA_TXEN_BIG_CNT_8822C(x) \ + (((x) & BIT_MASK_CCA_TXEN_BIG_CNT_8822C) \ + << BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C) +#define BITS_CCA_TXEN_BIG_CNT_8822C \ + (BIT_MASK_CCA_TXEN_BIG_CNT_8822C << BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C) +#define BIT_CLEAR_CCA_TXEN_BIG_CNT_8822C(x) \ + ((x) & (~BITS_CCA_TXEN_BIG_CNT_8822C)) +#define BIT_GET_CCA_TXEN_BIG_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C) & \ + BIT_MASK_CCA_TXEN_BIG_CNT_8822C) +#define BIT_SET_CCA_TXEN_BIG_CNT_8822C(x, v) \ + (BIT_CLEAR_CCA_TXEN_BIG_CNT_8822C(x) | BIT_CCA_TXEN_BIG_CNT_8822C(v)) + +#define BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C 0 +#define BIT_MASK_CCA_TXEN_SMALL_CNT_8822C 0xff +#define BIT_CCA_TXEN_SMALL_CNT_8822C(x) \ + (((x) & BIT_MASK_CCA_TXEN_SMALL_CNT_8822C) \ + << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C) +#define BITS_CCA_TXEN_SMALL_CNT_8822C \ + (BIT_MASK_CCA_TXEN_SMALL_CNT_8822C \ + << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C) +#define BIT_CLEAR_CCA_TXEN_SMALL_CNT_8822C(x) \ + ((x) & (~BITS_CCA_TXEN_SMALL_CNT_8822C)) +#define BIT_GET_CCA_TXEN_SMALL_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C) & \ + BIT_MASK_CCA_TXEN_SMALL_CNT_8822C) +#define BIT_SET_CCA_TXEN_SMALL_CNT_8822C(x, v) \ + (BIT_CLEAR_CCA_TXEN_SMALL_CNT_8822C(x) | \ + BIT_CCA_TXEN_SMALL_CNT_8822C(v)) + +/* 2 REG_MAX_INTER_COLLISION_8822C */ + +#define BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C 24 +#define BIT_MASK_MAX_INTER_COLLISION_BK_8822C 0xff +#define BIT_MAX_INTER_COLLISION_BK_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_BK_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C) +#define BITS_MAX_INTER_COLLISION_BK_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_BK_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_BK_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_BK_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_BK_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_BK_8822C) +#define BIT_SET_MAX_INTER_COLLISION_BK_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_BK_8822C(x) | \ + BIT_MAX_INTER_COLLISION_BK_8822C(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C 16 +#define BIT_MASK_MAX_INTER_COLLISION_BE_8822C 0xff +#define BIT_MAX_INTER_COLLISION_BE_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_BE_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C) +#define BITS_MAX_INTER_COLLISION_BE_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_BE_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_BE_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_BE_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_BE_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_BE_8822C) +#define BIT_SET_MAX_INTER_COLLISION_BE_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_BE_8822C(x) | \ + BIT_MAX_INTER_COLLISION_BE_8822C(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C 8 +#define BIT_MASK_MAX_INTER_COLLISION_VI_8822C 0xff +#define BIT_MAX_INTER_COLLISION_VI_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_VI_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C) +#define BITS_MAX_INTER_COLLISION_VI_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_VI_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_VI_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_VI_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_VI_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_VI_8822C) +#define BIT_SET_MAX_INTER_COLLISION_VI_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_VI_8822C(x) | \ + BIT_MAX_INTER_COLLISION_VI_8822C(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C 0 +#define BIT_MASK_MAX_INTER_COLLISION_VO_8822C 0xff +#define BIT_MAX_INTER_COLLISION_VO_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_VO_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C) +#define BITS_MAX_INTER_COLLISION_VO_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_VO_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_VO_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_VO_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_VO_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_VO_8822C) +#define BIT_SET_MAX_INTER_COLLISION_VO_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_VO_8822C(x) | \ + BIT_MAX_INTER_COLLISION_VO_8822C(v)) + +/* 2 REG_MAX_INTER_COLLISION_CNT_8822C */ +#define BIT_MAX_INTER_COLLISION_EN_8822C BIT(16) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C 12 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C 0xf +#define BIT_MAX_INTER_COLLISION_CNT_BK_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C) +#define BITS_MAX_INTER_COLLISION_CNT_BK_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_BK_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C) +#define BIT_SET_MAX_INTER_COLLISION_CNT_BK_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8822C(x) | \ + BIT_MAX_INTER_COLLISION_CNT_BK_8822C(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C 8 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C 0xf +#define BIT_MAX_INTER_COLLISION_CNT_BE_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C) +#define BITS_MAX_INTER_COLLISION_CNT_BE_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_BE_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C) +#define BIT_SET_MAX_INTER_COLLISION_CNT_BE_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8822C(x) | \ + BIT_MAX_INTER_COLLISION_CNT_BE_8822C(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C 4 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C 0xf +#define BIT_MAX_INTER_COLLISION_CNT_VI_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C) +#define BITS_MAX_INTER_COLLISION_CNT_VI_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_VI_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C) +#define BIT_SET_MAX_INTER_COLLISION_CNT_VI_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8822C(x) | \ + BIT_MAX_INTER_COLLISION_CNT_VI_8822C(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C 0 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C 0xf +#define BIT_MAX_INTER_COLLISION_CNT_VO_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C) +#define BITS_MAX_INTER_COLLISION_CNT_VO_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_VO_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C) +#define BIT_SET_MAX_INTER_COLLISION_CNT_VO_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8822C(x) | \ + BIT_MAX_INTER_COLLISION_CNT_VO_8822C(v)) + +/* 2 REG_TBTT_PROHIBIT_8822C */ + +#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C 8 +#define BIT_MASK_TBTT_HOLD_TIME_AP_8822C 0xfff +#define BIT_TBTT_HOLD_TIME_AP_8822C(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822C) \ + << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C) +#define BITS_TBTT_HOLD_TIME_AP_8822C \ + (BIT_MASK_TBTT_HOLD_TIME_AP_8822C << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C) +#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8822C(x) \ + ((x) & (~BITS_TBTT_HOLD_TIME_AP_8822C)) +#define BIT_GET_TBTT_HOLD_TIME_AP_8822C(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C) & \ + BIT_MASK_TBTT_HOLD_TIME_AP_8822C) +#define BIT_SET_TBTT_HOLD_TIME_AP_8822C(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_AP_8822C(x) | BIT_TBTT_HOLD_TIME_AP_8822C(v)) + +#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C 0 +#define BIT_MASK_TBTT_PROHIBIT_SETUP_8822C 0xf +#define BIT_TBTT_PROHIBIT_SETUP_8822C(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822C) \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C) +#define BITS_TBTT_PROHIBIT_SETUP_8822C \ + (BIT_MASK_TBTT_PROHIBIT_SETUP_8822C \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822C(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8822C)) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8822C(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C) & \ + BIT_MASK_TBTT_PROHIBIT_SETUP_8822C) +#define BIT_SET_TBTT_PROHIBIT_SETUP_8822C(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822C(x) | \ + BIT_TBTT_PROHIBIT_SETUP_8822C(v)) + +/* 2 REG_P2PPS_STATE_8822C */ +#define BIT_POWER_STATE_8822C BIT(7) +#define BIT_CTWINDOW_ON_8822C BIT(6) +#define BIT_BEACON_AREA_ON_8822C BIT(5) +#define BIT_CTWIN_EARLY_DISTX_8822C BIT(4) +#define BIT_NOA1_OFF_PERIOD_8822C BIT(3) +#define BIT_FORCE_DOZE1_8822C BIT(2) +#define BIT_NOA0_OFF_PERIOD_8822C BIT(1) +#define BIT_FORCE_DOZE0_8822C BIT(0) + +/* 2 REG_RD_NAV_NXT_8822C */ + +#define BIT_SHIFT_RD_NAV_PROT_NXT_8822C 0 +#define BIT_MASK_RD_NAV_PROT_NXT_8822C 0xffff +#define BIT_RD_NAV_PROT_NXT_8822C(x) \ + (((x) & BIT_MASK_RD_NAV_PROT_NXT_8822C) \ + << BIT_SHIFT_RD_NAV_PROT_NXT_8822C) +#define BITS_RD_NAV_PROT_NXT_8822C \ + (BIT_MASK_RD_NAV_PROT_NXT_8822C << BIT_SHIFT_RD_NAV_PROT_NXT_8822C) +#define BIT_CLEAR_RD_NAV_PROT_NXT_8822C(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8822C)) +#define BIT_GET_RD_NAV_PROT_NXT_8822C(x) \ + (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822C) & \ + BIT_MASK_RD_NAV_PROT_NXT_8822C) +#define BIT_SET_RD_NAV_PROT_NXT_8822C(x, v) \ + (BIT_CLEAR_RD_NAV_PROT_NXT_8822C(x) | BIT_RD_NAV_PROT_NXT_8822C(v)) + +/* 2 REG_NAV_PROT_LEN_8822C */ + +#define BIT_SHIFT_NAV_PROT_LEN_8822C 0 +#define BIT_MASK_NAV_PROT_LEN_8822C 0xffff +#define BIT_NAV_PROT_LEN_8822C(x) \ + (((x) & BIT_MASK_NAV_PROT_LEN_8822C) << BIT_SHIFT_NAV_PROT_LEN_8822C) +#define BITS_NAV_PROT_LEN_8822C \ + (BIT_MASK_NAV_PROT_LEN_8822C << BIT_SHIFT_NAV_PROT_LEN_8822C) +#define BIT_CLEAR_NAV_PROT_LEN_8822C(x) ((x) & (~BITS_NAV_PROT_LEN_8822C)) +#define BIT_GET_NAV_PROT_LEN_8822C(x) \ + (((x) >> BIT_SHIFT_NAV_PROT_LEN_8822C) & BIT_MASK_NAV_PROT_LEN_8822C) +#define BIT_SET_NAV_PROT_LEN_8822C(x, v) \ + (BIT_CLEAR_NAV_PROT_LEN_8822C(x) | BIT_NAV_PROT_LEN_8822C(v)) + +/* 2 REG_FTM_PTT_8822C */ + +#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C 22 +#define BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C 0x7 +#define BIT_FTM_PTT_TSF_R2T_SEL_8822C(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C) \ + << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C) +#define BITS_FTM_PTT_TSF_R2T_SEL_8822C \ + (BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C \ + << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C) +#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8822C(x) \ + ((x) & (~BITS_FTM_PTT_TSF_R2T_SEL_8822C)) +#define BIT_GET_FTM_PTT_TSF_R2T_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C) & \ + BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C) +#define BIT_SET_FTM_PTT_TSF_R2T_SEL_8822C(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8822C(x) | \ + BIT_FTM_PTT_TSF_R2T_SEL_8822C(v)) + +#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C 19 +#define BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C 0x7 +#define BIT_FTM_PTT_TSF_T2R_SEL_8822C(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C) \ + << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C) +#define BITS_FTM_PTT_TSF_T2R_SEL_8822C \ + (BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C \ + << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C) +#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8822C(x) \ + ((x) & (~BITS_FTM_PTT_TSF_T2R_SEL_8822C)) +#define BIT_GET_FTM_PTT_TSF_T2R_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C) & \ + BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C) +#define BIT_SET_FTM_PTT_TSF_T2R_SEL_8822C(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8822C(x) | \ + BIT_FTM_PTT_TSF_T2R_SEL_8822C(v)) + +#define BIT_SHIFT_FTM_PTT_TSF_SEL_8822C 16 +#define BIT_MASK_FTM_PTT_TSF_SEL_8822C 0x7 +#define BIT_FTM_PTT_TSF_SEL_8822C(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_SEL_8822C) \ + << BIT_SHIFT_FTM_PTT_TSF_SEL_8822C) +#define BITS_FTM_PTT_TSF_SEL_8822C \ + (BIT_MASK_FTM_PTT_TSF_SEL_8822C << BIT_SHIFT_FTM_PTT_TSF_SEL_8822C) +#define BIT_CLEAR_FTM_PTT_TSF_SEL_8822C(x) ((x) & (~BITS_FTM_PTT_TSF_SEL_8822C)) +#define BIT_GET_FTM_PTT_TSF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL_8822C) & \ + BIT_MASK_FTM_PTT_TSF_SEL_8822C) +#define BIT_SET_FTM_PTT_TSF_SEL_8822C(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_SEL_8822C(x) | BIT_FTM_PTT_TSF_SEL_8822C(v)) + +#define BIT_SHIFT_FTM_PTT_VALUE_8822C 0 +#define BIT_MASK_FTM_PTT_VALUE_8822C 0xffff +#define BIT_FTM_PTT_VALUE_8822C(x) \ + (((x) & BIT_MASK_FTM_PTT_VALUE_8822C) << BIT_SHIFT_FTM_PTT_VALUE_8822C) +#define BITS_FTM_PTT_VALUE_8822C \ + (BIT_MASK_FTM_PTT_VALUE_8822C << BIT_SHIFT_FTM_PTT_VALUE_8822C) +#define BIT_CLEAR_FTM_PTT_VALUE_8822C(x) ((x) & (~BITS_FTM_PTT_VALUE_8822C)) +#define BIT_GET_FTM_PTT_VALUE_8822C(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_VALUE_8822C) & BIT_MASK_FTM_PTT_VALUE_8822C) +#define BIT_SET_FTM_PTT_VALUE_8822C(x, v) \ + (BIT_CLEAR_FTM_PTT_VALUE_8822C(x) | BIT_FTM_PTT_VALUE_8822C(v)) + +/* 2 REG_FTM_TSF_8822C */ + +#define BIT_SHIFT_FTM_T2_TSF_8822C 16 +#define BIT_MASK_FTM_T2_TSF_8822C 0xffff +#define BIT_FTM_T2_TSF_8822C(x) \ + (((x) & BIT_MASK_FTM_T2_TSF_8822C) << BIT_SHIFT_FTM_T2_TSF_8822C) +#define BITS_FTM_T2_TSF_8822C \ + (BIT_MASK_FTM_T2_TSF_8822C << BIT_SHIFT_FTM_T2_TSF_8822C) +#define BIT_CLEAR_FTM_T2_TSF_8822C(x) ((x) & (~BITS_FTM_T2_TSF_8822C)) +#define BIT_GET_FTM_T2_TSF_8822C(x) \ + (((x) >> BIT_SHIFT_FTM_T2_TSF_8822C) & BIT_MASK_FTM_T2_TSF_8822C) +#define BIT_SET_FTM_T2_TSF_8822C(x, v) \ + (BIT_CLEAR_FTM_T2_TSF_8822C(x) | BIT_FTM_T2_TSF_8822C(v)) + +#define BIT_SHIFT_FTM_T1_TSF_8822C 0 +#define BIT_MASK_FTM_T1_TSF_8822C 0xffff +#define BIT_FTM_T1_TSF_8822C(x) \ + (((x) & BIT_MASK_FTM_T1_TSF_8822C) << BIT_SHIFT_FTM_T1_TSF_8822C) +#define BITS_FTM_T1_TSF_8822C \ + (BIT_MASK_FTM_T1_TSF_8822C << BIT_SHIFT_FTM_T1_TSF_8822C) +#define BIT_CLEAR_FTM_T1_TSF_8822C(x) ((x) & (~BITS_FTM_T1_TSF_8822C)) +#define BIT_GET_FTM_T1_TSF_8822C(x) \ + (((x) >> BIT_SHIFT_FTM_T1_TSF_8822C) & BIT_MASK_FTM_T1_TSF_8822C) +#define BIT_SET_FTM_T1_TSF_8822C(x, v) \ + (BIT_CLEAR_FTM_T1_TSF_8822C(x) | BIT_FTM_T1_TSF_8822C(v)) + +/* 2 REG_BCN_CTRL_8822C */ +#define BIT_DIS_RX_BSSID_FIT_8822C BIT(6) +#define BIT_P0_EN_TXBCN_RPT_8822C BIT(5) +#define BIT_DIS_TSF_UDT_8822C BIT(4) +#define BIT_EN_BCN_FUNCTION_8822C BIT(3) +#define BIT_P0_EN_RXBCN_RPT_8822C BIT(2) +#define BIT_EN_P2P_CTWINDOW_8822C BIT(1) +#define BIT_EN_P2P_BCNQ_AREA_8822C BIT(0) + +/* 2 REG_BCN_CTRL_CLINT0_8822C */ +#define BIT_CLI0_DIS_RX_BSSID_FIT_8822C BIT(6) +#define BIT_CLI0_DIS_TSF_UDT_8822C BIT(4) +#define BIT_CLI0_EN_BCN_FUNCTION_8822C BIT(3) +#define BIT_CLI0_EN_RXBCN_RPT_8822C BIT(2) +#define BIT_CLI0_ENP2P_CTWINDOW_8822C BIT(1) +#define BIT_CLI0_ENP2P_BCNQ_AREA_8822C BIT(0) + +/* 2 REG_MBID_NUM_8822C */ +#define BIT_EN_PRE_DL_BEACON_8822C BIT(3) + +#define BIT_SHIFT_MBID_BCN_NUM_8822C 0 +#define BIT_MASK_MBID_BCN_NUM_8822C 0x7 +#define BIT_MBID_BCN_NUM_8822C(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_8822C) << BIT_SHIFT_MBID_BCN_NUM_8822C) +#define BITS_MBID_BCN_NUM_8822C \ + (BIT_MASK_MBID_BCN_NUM_8822C << BIT_SHIFT_MBID_BCN_NUM_8822C) +#define BIT_CLEAR_MBID_BCN_NUM_8822C(x) ((x) & (~BITS_MBID_BCN_NUM_8822C)) +#define BIT_GET_MBID_BCN_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_8822C) & BIT_MASK_MBID_BCN_NUM_8822C) +#define BIT_SET_MBID_BCN_NUM_8822C(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_8822C(x) | BIT_MBID_BCN_NUM_8822C(v)) + +/* 2 REG_DUAL_TSF_RST_8822C */ +#define BIT_FREECNT_RST_8822C BIT(5) +#define BIT_TSFTR_CLI3_RST_8822C BIT(4) +#define BIT_TSFTR_CLI2_RST_8822C BIT(3) +#define BIT_TSFTR_CLI1_RST_8822C BIT(2) +#define BIT_TSFTR_CLI0_RST_8822C BIT(1) +#define BIT_TSFTR_RST_8822C BIT(0) + +/* 2 REG_MBSSID_BCN_SPACE_8822C */ + +#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C 28 +#define BIT_MASK_BCN_TIMER_SEL_FWRD_8822C 0x7 +#define BIT_BCN_TIMER_SEL_FWRD_8822C(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822C) \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C) +#define BITS_BCN_TIMER_SEL_FWRD_8822C \ + (BIT_MASK_BCN_TIMER_SEL_FWRD_8822C \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822C(x) \ + ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8822C)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C) & \ + BIT_MASK_BCN_TIMER_SEL_FWRD_8822C) +#define BIT_SET_BCN_TIMER_SEL_FWRD_8822C(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822C(x) | \ + BIT_BCN_TIMER_SEL_FWRD_8822C(v)) + +#define BIT_SHIFT_BCN_SPACE_CLINT0_8822C 16 +#define BIT_MASK_BCN_SPACE_CLINT0_8822C 0xfff +#define BIT_BCN_SPACE_CLINT0_8822C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT0_8822C) \ + << BIT_SHIFT_BCN_SPACE_CLINT0_8822C) +#define BITS_BCN_SPACE_CLINT0_8822C \ + (BIT_MASK_BCN_SPACE_CLINT0_8822C << BIT_SHIFT_BCN_SPACE_CLINT0_8822C) +#define BIT_CLEAR_BCN_SPACE_CLINT0_8822C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT0_8822C)) +#define BIT_GET_BCN_SPACE_CLINT0_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822C) & \ + BIT_MASK_BCN_SPACE_CLINT0_8822C) +#define BIT_SET_BCN_SPACE_CLINT0_8822C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT0_8822C(x) | BIT_BCN_SPACE_CLINT0_8822C(v)) + +#define BIT_SHIFT_BCN_SPACE0_8822C 0 +#define BIT_MASK_BCN_SPACE0_8822C 0xffff +#define BIT_BCN_SPACE0_8822C(x) \ + (((x) & BIT_MASK_BCN_SPACE0_8822C) << BIT_SHIFT_BCN_SPACE0_8822C) +#define BITS_BCN_SPACE0_8822C \ + (BIT_MASK_BCN_SPACE0_8822C << BIT_SHIFT_BCN_SPACE0_8822C) +#define BIT_CLEAR_BCN_SPACE0_8822C(x) ((x) & (~BITS_BCN_SPACE0_8822C)) +#define BIT_GET_BCN_SPACE0_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE0_8822C) & BIT_MASK_BCN_SPACE0_8822C) +#define BIT_SET_BCN_SPACE0_8822C(x, v) \ + (BIT_CLEAR_BCN_SPACE0_8822C(x) | BIT_BCN_SPACE0_8822C(v)) + +/* 2 REG_DRVERLYINT_8822C */ + +#define BIT_SHIFT_DRVERLYITV_8822C 0 +#define BIT_MASK_DRVERLYITV_8822C 0xff +#define BIT_DRVERLYITV_8822C(x) \ + (((x) & BIT_MASK_DRVERLYITV_8822C) << BIT_SHIFT_DRVERLYITV_8822C) +#define BITS_DRVERLYITV_8822C \ + (BIT_MASK_DRVERLYITV_8822C << BIT_SHIFT_DRVERLYITV_8822C) +#define BIT_CLEAR_DRVERLYITV_8822C(x) ((x) & (~BITS_DRVERLYITV_8822C)) +#define BIT_GET_DRVERLYITV_8822C(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV_8822C) & BIT_MASK_DRVERLYITV_8822C) +#define BIT_SET_DRVERLYITV_8822C(x, v) \ + (BIT_CLEAR_DRVERLYITV_8822C(x) | BIT_DRVERLYITV_8822C(v)) + +/* 2 REG_BCNDMATIM_8822C */ + +#define BIT_SHIFT_BCNDMATIM_8822C 0 +#define BIT_MASK_BCNDMATIM_8822C 0xff +#define BIT_BCNDMATIM_8822C(x) \ + (((x) & BIT_MASK_BCNDMATIM_8822C) << BIT_SHIFT_BCNDMATIM_8822C) +#define BITS_BCNDMATIM_8822C \ + (BIT_MASK_BCNDMATIM_8822C << BIT_SHIFT_BCNDMATIM_8822C) +#define BIT_CLEAR_BCNDMATIM_8822C(x) ((x) & (~BITS_BCNDMATIM_8822C)) +#define BIT_GET_BCNDMATIM_8822C(x) \ + (((x) >> BIT_SHIFT_BCNDMATIM_8822C) & BIT_MASK_BCNDMATIM_8822C) +#define BIT_SET_BCNDMATIM_8822C(x, v) \ + (BIT_CLEAR_BCNDMATIM_8822C(x) | BIT_BCNDMATIM_8822C(v)) + +/* 2 REG_ATIMWND_8822C */ + +#define BIT_SHIFT_ATIMWND0_8822C 0 +#define BIT_MASK_ATIMWND0_8822C 0xffff +#define BIT_ATIMWND0_8822C(x) \ + (((x) & BIT_MASK_ATIMWND0_8822C) << BIT_SHIFT_ATIMWND0_8822C) +#define BITS_ATIMWND0_8822C \ + (BIT_MASK_ATIMWND0_8822C << BIT_SHIFT_ATIMWND0_8822C) +#define BIT_CLEAR_ATIMWND0_8822C(x) ((x) & (~BITS_ATIMWND0_8822C)) +#define BIT_GET_ATIMWND0_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND0_8822C) & BIT_MASK_ATIMWND0_8822C) +#define BIT_SET_ATIMWND0_8822C(x, v) \ + (BIT_CLEAR_ATIMWND0_8822C(x) | BIT_ATIMWND0_8822C(v)) + +/* 2 REG_USTIME_TSF_8822C */ + +#define BIT_SHIFT_USTIME_TSF_V1_8822C 0 +#define BIT_MASK_USTIME_TSF_V1_8822C 0xff +#define BIT_USTIME_TSF_V1_8822C(x) \ + (((x) & BIT_MASK_USTIME_TSF_V1_8822C) << BIT_SHIFT_USTIME_TSF_V1_8822C) +#define BITS_USTIME_TSF_V1_8822C \ + (BIT_MASK_USTIME_TSF_V1_8822C << BIT_SHIFT_USTIME_TSF_V1_8822C) +#define BIT_CLEAR_USTIME_TSF_V1_8822C(x) ((x) & (~BITS_USTIME_TSF_V1_8822C)) +#define BIT_GET_USTIME_TSF_V1_8822C(x) \ + (((x) >> BIT_SHIFT_USTIME_TSF_V1_8822C) & BIT_MASK_USTIME_TSF_V1_8822C) +#define BIT_SET_USTIME_TSF_V1_8822C(x, v) \ + (BIT_CLEAR_USTIME_TSF_V1_8822C(x) | BIT_USTIME_TSF_V1_8822C(v)) + +/* 2 REG_BCN_MAX_ERR_8822C */ + +#define BIT_SHIFT_BCN_MAX_ERR_8822C 0 +#define BIT_MASK_BCN_MAX_ERR_8822C 0xff +#define BIT_BCN_MAX_ERR_8822C(x) \ + (((x) & BIT_MASK_BCN_MAX_ERR_8822C) << BIT_SHIFT_BCN_MAX_ERR_8822C) +#define BITS_BCN_MAX_ERR_8822C \ + (BIT_MASK_BCN_MAX_ERR_8822C << BIT_SHIFT_BCN_MAX_ERR_8822C) +#define BIT_CLEAR_BCN_MAX_ERR_8822C(x) ((x) & (~BITS_BCN_MAX_ERR_8822C)) +#define BIT_GET_BCN_MAX_ERR_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_MAX_ERR_8822C) & BIT_MASK_BCN_MAX_ERR_8822C) +#define BIT_SET_BCN_MAX_ERR_8822C(x, v) \ + (BIT_CLEAR_BCN_MAX_ERR_8822C(x) | BIT_BCN_MAX_ERR_8822C(v)) + +/* 2 REG_RXTSF_OFFSET_CCK_8822C */ + +#define BIT_SHIFT_CCK_RXTSF_OFFSET_8822C 0 +#define BIT_MASK_CCK_RXTSF_OFFSET_8822C 0xff +#define BIT_CCK_RXTSF_OFFSET_8822C(x) \ + (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822C) \ + << BIT_SHIFT_CCK_RXTSF_OFFSET_8822C) +#define BITS_CCK_RXTSF_OFFSET_8822C \ + (BIT_MASK_CCK_RXTSF_OFFSET_8822C << BIT_SHIFT_CCK_RXTSF_OFFSET_8822C) +#define BIT_CLEAR_CCK_RXTSF_OFFSET_8822C(x) \ + ((x) & (~BITS_CCK_RXTSF_OFFSET_8822C)) +#define BIT_GET_CCK_RXTSF_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822C) & \ + BIT_MASK_CCK_RXTSF_OFFSET_8822C) +#define BIT_SET_CCK_RXTSF_OFFSET_8822C(x, v) \ + (BIT_CLEAR_CCK_RXTSF_OFFSET_8822C(x) | BIT_CCK_RXTSF_OFFSET_8822C(v)) + +/* 2 REG_RXTSF_OFFSET_OFDM_8822C */ + +#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C 0 +#define BIT_MASK_OFDM_RXTSF_OFFSET_8822C 0xff +#define BIT_OFDM_RXTSF_OFFSET_8822C(x) \ + (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822C) \ + << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C) +#define BITS_OFDM_RXTSF_OFFSET_8822C \ + (BIT_MASK_OFDM_RXTSF_OFFSET_8822C << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8822C(x) \ + ((x) & (~BITS_OFDM_RXTSF_OFFSET_8822C)) +#define BIT_GET_OFDM_RXTSF_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C) & \ + BIT_MASK_OFDM_RXTSF_OFFSET_8822C) +#define BIT_SET_OFDM_RXTSF_OFFSET_8822C(x, v) \ + (BIT_CLEAR_OFDM_RXTSF_OFFSET_8822C(x) | BIT_OFDM_RXTSF_OFFSET_8822C(v)) + +/* 2 REG_TSFTR_8822C */ + +#define BIT_SHIFT_TSF_TIMER_V1_8822C 0 +#define BIT_MASK_TSF_TIMER_V1_8822C 0xffffffffL +#define BIT_TSF_TIMER_V1_8822C(x) \ + (((x) & BIT_MASK_TSF_TIMER_V1_8822C) << BIT_SHIFT_TSF_TIMER_V1_8822C) +#define BITS_TSF_TIMER_V1_8822C \ + (BIT_MASK_TSF_TIMER_V1_8822C << BIT_SHIFT_TSF_TIMER_V1_8822C) +#define BIT_CLEAR_TSF_TIMER_V1_8822C(x) ((x) & (~BITS_TSF_TIMER_V1_8822C)) +#define BIT_GET_TSF_TIMER_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_V1_8822C) & BIT_MASK_TSF_TIMER_V1_8822C) +#define BIT_SET_TSF_TIMER_V1_8822C(x, v) \ + (BIT_CLEAR_TSF_TIMER_V1_8822C(x) | BIT_TSF_TIMER_V1_8822C(v)) + +/* 2 REG_TSFTR_1_8822C */ + +#define BIT_SHIFT_TSF_TIMER_V2_8822C 0 +#define BIT_MASK_TSF_TIMER_V2_8822C 0xffffffffL +#define BIT_TSF_TIMER_V2_8822C(x) \ + (((x) & BIT_MASK_TSF_TIMER_V2_8822C) << BIT_SHIFT_TSF_TIMER_V2_8822C) +#define BITS_TSF_TIMER_V2_8822C \ + (BIT_MASK_TSF_TIMER_V2_8822C << BIT_SHIFT_TSF_TIMER_V2_8822C) +#define BIT_CLEAR_TSF_TIMER_V2_8822C(x) ((x) & (~BITS_TSF_TIMER_V2_8822C)) +#define BIT_GET_TSF_TIMER_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_V2_8822C) & BIT_MASK_TSF_TIMER_V2_8822C) +#define BIT_SET_TSF_TIMER_V2_8822C(x, v) \ + (BIT_CLEAR_TSF_TIMER_V2_8822C(x) | BIT_TSF_TIMER_V2_8822C(v)) + +/* 2 REG_FREERUN_CNT_8822C */ + +#define BIT_SHIFT_FREERUN_CNT_V1_8822C 0 +#define BIT_MASK_FREERUN_CNT_V1_8822C 0xffffffffL +#define BIT_FREERUN_CNT_V1_8822C(x) \ + (((x) & BIT_MASK_FREERUN_CNT_V1_8822C) \ + << BIT_SHIFT_FREERUN_CNT_V1_8822C) +#define BITS_FREERUN_CNT_V1_8822C \ + (BIT_MASK_FREERUN_CNT_V1_8822C << BIT_SHIFT_FREERUN_CNT_V1_8822C) +#define BIT_CLEAR_FREERUN_CNT_V1_8822C(x) ((x) & (~BITS_FREERUN_CNT_V1_8822C)) +#define BIT_GET_FREERUN_CNT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8822C) & \ + BIT_MASK_FREERUN_CNT_V1_8822C) +#define BIT_SET_FREERUN_CNT_V1_8822C(x, v) \ + (BIT_CLEAR_FREERUN_CNT_V1_8822C(x) | BIT_FREERUN_CNT_V1_8822C(v)) + +/* 2 REG_FREERUN_CNT_1_8822C */ + +#define BIT_SHIFT_FREERUN_CNT_V2_8822C 0 +#define BIT_MASK_FREERUN_CNT_V2_8822C 0xffffffffL +#define BIT_FREERUN_CNT_V2_8822C(x) \ + (((x) & BIT_MASK_FREERUN_CNT_V2_8822C) \ + << BIT_SHIFT_FREERUN_CNT_V2_8822C) +#define BITS_FREERUN_CNT_V2_8822C \ + (BIT_MASK_FREERUN_CNT_V2_8822C << BIT_SHIFT_FREERUN_CNT_V2_8822C) +#define BIT_CLEAR_FREERUN_CNT_V2_8822C(x) ((x) & (~BITS_FREERUN_CNT_V2_8822C)) +#define BIT_GET_FREERUN_CNT_V2_8822C(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8822C) & \ + BIT_MASK_FREERUN_CNT_V2_8822C) +#define BIT_SET_FREERUN_CNT_V2_8822C(x, v) \ + (BIT_CLEAR_FREERUN_CNT_V2_8822C(x) | BIT_FREERUN_CNT_V2_8822C(v)) + +/* 2 REG_ATIMWND1_V1_8822C */ + +#define BIT_SHIFT_ATIMWND1_V1_8822C 0 +#define BIT_MASK_ATIMWND1_V1_8822C 0xff +#define BIT_ATIMWND1_V1_8822C(x) \ + (((x) & BIT_MASK_ATIMWND1_V1_8822C) << BIT_SHIFT_ATIMWND1_V1_8822C) +#define BITS_ATIMWND1_V1_8822C \ + (BIT_MASK_ATIMWND1_V1_8822C << BIT_SHIFT_ATIMWND1_V1_8822C) +#define BIT_CLEAR_ATIMWND1_V1_8822C(x) ((x) & (~BITS_ATIMWND1_V1_8822C)) +#define BIT_GET_ATIMWND1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND1_V1_8822C) & BIT_MASK_ATIMWND1_V1_8822C) +#define BIT_SET_ATIMWND1_V1_8822C(x, v) \ + (BIT_CLEAR_ATIMWND1_V1_8822C(x) | BIT_ATIMWND1_V1_8822C(v)) + +/* 2 REG_TBTT_PROHIBIT_INFRA_8822C */ + +#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C 0 +#define BIT_MASK_TBTT_PROHIBIT_INFRA_8822C 0xff +#define BIT_TBTT_PROHIBIT_INFRA_8822C(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822C) \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C) +#define BITS_TBTT_PROHIBIT_INFRA_8822C \ + (BIT_MASK_TBTT_PROHIBIT_INFRA_8822C \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C) +#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822C(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8822C)) +#define BIT_GET_TBTT_PROHIBIT_INFRA_8822C(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C) & \ + BIT_MASK_TBTT_PROHIBIT_INFRA_8822C) +#define BIT_SET_TBTT_PROHIBIT_INFRA_8822C(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822C(x) | \ + BIT_TBTT_PROHIBIT_INFRA_8822C(v)) + +/* 2 REG_CTWND_8822C */ + +#define BIT_SHIFT_CTWND_8822C 0 +#define BIT_MASK_CTWND_8822C 0xff +#define BIT_CTWND_8822C(x) \ + (((x) & BIT_MASK_CTWND_8822C) << BIT_SHIFT_CTWND_8822C) +#define BITS_CTWND_8822C (BIT_MASK_CTWND_8822C << BIT_SHIFT_CTWND_8822C) +#define BIT_CLEAR_CTWND_8822C(x) ((x) & (~BITS_CTWND_8822C)) +#define BIT_GET_CTWND_8822C(x) \ + (((x) >> BIT_SHIFT_CTWND_8822C) & BIT_MASK_CTWND_8822C) +#define BIT_SET_CTWND_8822C(x, v) \ + (BIT_CLEAR_CTWND_8822C(x) | BIT_CTWND_8822C(v)) + +/* 2 REG_BCNIVLCUNT_8822C */ + +#define BIT_SHIFT_BCNIVLCUNT_8822C 0 +#define BIT_MASK_BCNIVLCUNT_8822C 0x7f +#define BIT_BCNIVLCUNT_8822C(x) \ + (((x) & BIT_MASK_BCNIVLCUNT_8822C) << BIT_SHIFT_BCNIVLCUNT_8822C) +#define BITS_BCNIVLCUNT_8822C \ + (BIT_MASK_BCNIVLCUNT_8822C << BIT_SHIFT_BCNIVLCUNT_8822C) +#define BIT_CLEAR_BCNIVLCUNT_8822C(x) ((x) & (~BITS_BCNIVLCUNT_8822C)) +#define BIT_GET_BCNIVLCUNT_8822C(x) \ + (((x) >> BIT_SHIFT_BCNIVLCUNT_8822C) & BIT_MASK_BCNIVLCUNT_8822C) +#define BIT_SET_BCNIVLCUNT_8822C(x, v) \ + (BIT_CLEAR_BCNIVLCUNT_8822C(x) | BIT_BCNIVLCUNT_8822C(v)) + +/* 2 REG_BCNDROPCTRL_8822C */ +#define BIT_BEACON_DROP_EN_8822C BIT(7) + +#define BIT_SHIFT_BEACON_DROP_IVL_8822C 0 +#define BIT_MASK_BEACON_DROP_IVL_8822C 0x7f +#define BIT_BEACON_DROP_IVL_8822C(x) \ + (((x) & BIT_MASK_BEACON_DROP_IVL_8822C) \ + << BIT_SHIFT_BEACON_DROP_IVL_8822C) +#define BITS_BEACON_DROP_IVL_8822C \ + (BIT_MASK_BEACON_DROP_IVL_8822C << BIT_SHIFT_BEACON_DROP_IVL_8822C) +#define BIT_CLEAR_BEACON_DROP_IVL_8822C(x) ((x) & (~BITS_BEACON_DROP_IVL_8822C)) +#define BIT_GET_BEACON_DROP_IVL_8822C(x) \ + (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822C) & \ + BIT_MASK_BEACON_DROP_IVL_8822C) +#define BIT_SET_BEACON_DROP_IVL_8822C(x, v) \ + (BIT_CLEAR_BEACON_DROP_IVL_8822C(x) | BIT_BEACON_DROP_IVL_8822C(v)) + +/* 2 REG_HGQ_TIMEOUT_PERIOD_8822C */ + +#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C 0 +#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C 0xff +#define BIT_HGQ_TIMEOUT_PERIOD_8822C(x) \ + (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C) \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C) +#define BITS_HGQ_TIMEOUT_PERIOD_8822C \ + (BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822C(x) \ + ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8822C)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822C(x) \ + (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C) & \ + BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C) +#define BIT_SET_HGQ_TIMEOUT_PERIOD_8822C(x, v) \ + (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822C(x) | \ + BIT_HGQ_TIMEOUT_PERIOD_8822C(v)) + +/* 2 REG_TXCMD_TIMEOUT_PERIOD_8822C */ + +#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C 0 +#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C 0xff +#define BIT_TXCMD_TIMEOUT_PERIOD_8822C(x) \ + (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C) \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C) +#define BITS_TXCMD_TIMEOUT_PERIOD_8822C \ + (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822C(x) \ + ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8822C)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822C(x) \ + (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C) & \ + BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8822C(x, v) \ + (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822C(x) | \ + BIT_TXCMD_TIMEOUT_PERIOD_8822C(v)) + +/* 2 REG_MISC_CTRL_8822C */ +#define BIT_DIS_MARK_TSF_US_V2_8822C BIT(7) +#define BIT_AUTO_SYNC_BY_TBTT_8822C BIT(6) +#define BIT_DIS_TRX_CAL_BCN_8822C BIT(5) +#define BIT_DIS_TX_CAL_TBTT_8822C BIT(4) +#define BIT_EN_FREECNT_8822C BIT(3) +#define BIT_BCN_AGGRESSION_8822C BIT(2) + +#define BIT_SHIFT_DIS_SECONDARY_CCA_8822C 0 +#define BIT_MASK_DIS_SECONDARY_CCA_8822C 0x3 +#define BIT_DIS_SECONDARY_CCA_8822C(x) \ + (((x) & BIT_MASK_DIS_SECONDARY_CCA_8822C) \ + << BIT_SHIFT_DIS_SECONDARY_CCA_8822C) +#define BITS_DIS_SECONDARY_CCA_8822C \ + (BIT_MASK_DIS_SECONDARY_CCA_8822C << BIT_SHIFT_DIS_SECONDARY_CCA_8822C) +#define BIT_CLEAR_DIS_SECONDARY_CCA_8822C(x) \ + ((x) & (~BITS_DIS_SECONDARY_CCA_8822C)) +#define BIT_GET_DIS_SECONDARY_CCA_8822C(x) \ + (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822C) & \ + BIT_MASK_DIS_SECONDARY_CCA_8822C) +#define BIT_SET_DIS_SECONDARY_CCA_8822C(x, v) \ + (BIT_CLEAR_DIS_SECONDARY_CCA_8822C(x) | BIT_DIS_SECONDARY_CCA_8822C(v)) + +/* 2 REG_BCN_CTRL_CLINT1_8822C */ +#define BIT_CLI1_DIS_RX_BSSID_FIT_8822C BIT(6) +#define BIT_CLI1_DIS_TSF_UDT_8822C BIT(4) +#define BIT_CLI1_EN_BCN_FUNCTION_8822C BIT(3) +#define BIT_CLI1_EN_RXBCN_RPT_8822C BIT(2) +#define BIT_CLI1_ENP2P_CTWINDOW_8822C BIT(1) +#define BIT_CLI1_ENP2P_BCNQ_AREA_8822C BIT(0) + +/* 2 REG_BCN_CTRL_CLINT2_8822C */ +#define BIT_CLI2_DIS_RX_BSSID_FIT_8822C BIT(6) +#define BIT_CLI2_DIS_TSF_UDT_8822C BIT(4) +#define BIT_CLI2_EN_BCN_FUNCTION_8822C BIT(3) +#define BIT_CLI2_EN_RXBCN_RPT_8822C BIT(2) +#define BIT_CLI2_ENP2P_CTWINDOW_8822C BIT(1) +#define BIT_CLI2_ENP2P_BCNQ_AREA_8822C BIT(0) + +/* 2 REG_BCN_CTRL_CLINT3_8822C */ +#define BIT_CLI3_DIS_RX_BSSID_FIT_8822C BIT(6) +#define BIT_CLI3_DIS_TSF_UDT_8822C BIT(4) +#define BIT_CLI3_EN_BCN_FUNCTION_8822C BIT(3) +#define BIT_CLI3_EN_RXBCN_RPT_8822C BIT(2) +#define BIT_CLI3_ENP2P_CTWINDOW_8822C BIT(1) +#define BIT_CLI3_ENP2P_BCNQ_AREA_8822C BIT(0) + +/* 2 REG_EXTEND_CTRL_8822C */ +#define BIT_EN_TSFBIT32_RST_P2P2_8822C BIT(5) +#define BIT_EN_TSFBIT32_RST_P2P1_8822C BIT(4) + +#define BIT_SHIFT_PORT_SEL_8822C 0 +#define BIT_MASK_PORT_SEL_8822C 0x7 +#define BIT_PORT_SEL_8822C(x) \ + (((x) & BIT_MASK_PORT_SEL_8822C) << BIT_SHIFT_PORT_SEL_8822C) +#define BITS_PORT_SEL_8822C \ + (BIT_MASK_PORT_SEL_8822C << BIT_SHIFT_PORT_SEL_8822C) +#define BIT_CLEAR_PORT_SEL_8822C(x) ((x) & (~BITS_PORT_SEL_8822C)) +#define BIT_GET_PORT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_PORT_SEL_8822C) & BIT_MASK_PORT_SEL_8822C) +#define BIT_SET_PORT_SEL_8822C(x, v) \ + (BIT_CLEAR_PORT_SEL_8822C(x) | BIT_PORT_SEL_8822C(v)) + +/* 2 REG_P2PPS1_SPEC_STATE_8822C */ +#define BIT_P2P1_SPEC_POWER_STATE_8822C BIT(7) +#define BIT_P2P1_SPEC_CTWINDOW_ON_8822C BIT(6) +#define BIT_P2P1_SPEC_BCN_AREA_ON_8822C BIT(5) +#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4) +#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8822C BIT(3) +#define BIT_P2P1_SPEC_FORCE_DOZE1_8822C BIT(2) +#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8822C BIT(1) +#define BIT_P2P1_SPEC_FORCE_DOZE0_8822C BIT(0) + +/* 2 REG_P2PPS1_STATE_8822C */ +#define BIT_P2P1_POWER_STATE_8822C BIT(7) +#define BIT_P2P1_CTWINDOW_ON_8822C BIT(6) +#define BIT_P2P1_BEACON_AREA_ON_8822C BIT(5) +#define BIT_P2P1_CTWIN_EARLY_DISTX_8822C BIT(4) +#define BIT_P2P1_NOA1_OFF_PERIOD_8822C BIT(3) +#define BIT_P2P1_FORCE_DOZE1_8822C BIT(2) +#define BIT_P2P1_NOA0_OFF_PERIOD_8822C BIT(1) +#define BIT_P2P1_FORCE_DOZE0_8822C BIT(0) + +/* 2 REG_P2PPS2_SPEC_STATE_8822C */ +#define BIT_P2P2_SPEC_POWER_STATE_8822C BIT(7) +#define BIT_P2P2_SPEC_CTWINDOW_ON_8822C BIT(6) +#define BIT_P2P2_SPEC_BCN_AREA_ON_8822C BIT(5) +#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4) +#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8822C BIT(3) +#define BIT_P2P2_SPEC_FORCE_DOZE1_8822C BIT(2) +#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8822C BIT(1) +#define BIT_P2P2_SPEC_FORCE_DOZE0_8822C BIT(0) + +/* 2 REG_P2PPS2_STATE_8822C */ +#define BIT_P2P2_POWER_STATE_8822C BIT(7) +#define BIT_P2P2_CTWINDOW_ON_8822C BIT(6) +#define BIT_P2P2_BEACON_AREA_ON_8822C BIT(5) +#define BIT_P2P2_CTWIN_EARLY_DISTX_8822C BIT(4) +#define BIT_P2P2_NOA1_OFF_PERIOD_8822C BIT(3) +#define BIT_P2P2_FORCE_DOZE1_8822C BIT(2) +#define BIT_P2P2_NOA0_OFF_PERIOD_8822C BIT(1) +#define BIT_P2P2_FORCE_DOZE0_8822C BIT(0) + +/* 2 REG_PS_TIMER0_8822C */ + +#define BIT_SHIFT_PSTIMER0_INT_8822C 5 +#define BIT_MASK_PSTIMER0_INT_8822C 0x7ffffff +#define BIT_PSTIMER0_INT_8822C(x) \ + (((x) & BIT_MASK_PSTIMER0_INT_8822C) << BIT_SHIFT_PSTIMER0_INT_8822C) +#define BITS_PSTIMER0_INT_8822C \ + (BIT_MASK_PSTIMER0_INT_8822C << BIT_SHIFT_PSTIMER0_INT_8822C) +#define BIT_CLEAR_PSTIMER0_INT_8822C(x) ((x) & (~BITS_PSTIMER0_INT_8822C)) +#define BIT_GET_PSTIMER0_INT_8822C(x) \ + (((x) >> BIT_SHIFT_PSTIMER0_INT_8822C) & BIT_MASK_PSTIMER0_INT_8822C) +#define BIT_SET_PSTIMER0_INT_8822C(x, v) \ + (BIT_CLEAR_PSTIMER0_INT_8822C(x) | BIT_PSTIMER0_INT_8822C(v)) + +/* 2 REG_PS_TIMER1_8822C */ + +#define BIT_SHIFT_PSTIMER1_INT_8822C 5 +#define BIT_MASK_PSTIMER1_INT_8822C 0x7ffffff +#define BIT_PSTIMER1_INT_8822C(x) \ + (((x) & BIT_MASK_PSTIMER1_INT_8822C) << BIT_SHIFT_PSTIMER1_INT_8822C) +#define BITS_PSTIMER1_INT_8822C \ + (BIT_MASK_PSTIMER1_INT_8822C << BIT_SHIFT_PSTIMER1_INT_8822C) +#define BIT_CLEAR_PSTIMER1_INT_8822C(x) ((x) & (~BITS_PSTIMER1_INT_8822C)) +#define BIT_GET_PSTIMER1_INT_8822C(x) \ + (((x) >> BIT_SHIFT_PSTIMER1_INT_8822C) & BIT_MASK_PSTIMER1_INT_8822C) +#define BIT_SET_PSTIMER1_INT_8822C(x, v) \ + (BIT_CLEAR_PSTIMER1_INT_8822C(x) | BIT_PSTIMER1_INT_8822C(v)) + +/* 2 REG_PS_TIMER2_8822C */ + +#define BIT_SHIFT_PSTIMER2_INT_8822C 5 +#define BIT_MASK_PSTIMER2_INT_8822C 0x7ffffff +#define BIT_PSTIMER2_INT_8822C(x) \ + (((x) & BIT_MASK_PSTIMER2_INT_8822C) << BIT_SHIFT_PSTIMER2_INT_8822C) +#define BITS_PSTIMER2_INT_8822C \ + (BIT_MASK_PSTIMER2_INT_8822C << BIT_SHIFT_PSTIMER2_INT_8822C) +#define BIT_CLEAR_PSTIMER2_INT_8822C(x) ((x) & (~BITS_PSTIMER2_INT_8822C)) +#define BIT_GET_PSTIMER2_INT_8822C(x) \ + (((x) >> BIT_SHIFT_PSTIMER2_INT_8822C) & BIT_MASK_PSTIMER2_INT_8822C) +#define BIT_SET_PSTIMER2_INT_8822C(x, v) \ + (BIT_CLEAR_PSTIMER2_INT_8822C(x) | BIT_PSTIMER2_INT_8822C(v)) + +/* 2 REG_TBTT_CTN_AREA_8822C */ + +#define BIT_SHIFT_TBTT_CTN_AREA_8822C 0 +#define BIT_MASK_TBTT_CTN_AREA_8822C 0xff +#define BIT_TBTT_CTN_AREA_8822C(x) \ + (((x) & BIT_MASK_TBTT_CTN_AREA_8822C) << BIT_SHIFT_TBTT_CTN_AREA_8822C) +#define BITS_TBTT_CTN_AREA_8822C \ + (BIT_MASK_TBTT_CTN_AREA_8822C << BIT_SHIFT_TBTT_CTN_AREA_8822C) +#define BIT_CLEAR_TBTT_CTN_AREA_8822C(x) ((x) & (~BITS_TBTT_CTN_AREA_8822C)) +#define BIT_GET_TBTT_CTN_AREA_8822C(x) \ + (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822C) & BIT_MASK_TBTT_CTN_AREA_8822C) +#define BIT_SET_TBTT_CTN_AREA_8822C(x, v) \ + (BIT_CLEAR_TBTT_CTN_AREA_8822C(x) | BIT_TBTT_CTN_AREA_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_FORCE_BCN_IFS_8822C */ + +#define BIT_SHIFT_FORCE_BCN_IFS_8822C 0 +#define BIT_MASK_FORCE_BCN_IFS_8822C 0xff +#define BIT_FORCE_BCN_IFS_8822C(x) \ + (((x) & BIT_MASK_FORCE_BCN_IFS_8822C) << BIT_SHIFT_FORCE_BCN_IFS_8822C) +#define BITS_FORCE_BCN_IFS_8822C \ + (BIT_MASK_FORCE_BCN_IFS_8822C << BIT_SHIFT_FORCE_BCN_IFS_8822C) +#define BIT_CLEAR_FORCE_BCN_IFS_8822C(x) ((x) & (~BITS_FORCE_BCN_IFS_8822C)) +#define BIT_GET_FORCE_BCN_IFS_8822C(x) \ + (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822C) & BIT_MASK_FORCE_BCN_IFS_8822C) +#define BIT_SET_FORCE_BCN_IFS_8822C(x, v) \ + (BIT_CLEAR_FORCE_BCN_IFS_8822C(x) | BIT_FORCE_BCN_IFS_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_TXOP_MIN_8822C */ +#define BIT_HIQ_NAV_BREAK_EN_8822C BIT(15) +#define BIT_MGQ_NAV_BREAK_EN_8822C BIT(14) + +#define BIT_SHIFT_TXOP_MIN_8822C 0 +#define BIT_MASK_TXOP_MIN_8822C 0x3fff +#define BIT_TXOP_MIN_8822C(x) \ + (((x) & BIT_MASK_TXOP_MIN_8822C) << BIT_SHIFT_TXOP_MIN_8822C) +#define BITS_TXOP_MIN_8822C \ + (BIT_MASK_TXOP_MIN_8822C << BIT_SHIFT_TXOP_MIN_8822C) +#define BIT_CLEAR_TXOP_MIN_8822C(x) ((x) & (~BITS_TXOP_MIN_8822C)) +#define BIT_GET_TXOP_MIN_8822C(x) \ + (((x) >> BIT_SHIFT_TXOP_MIN_8822C) & BIT_MASK_TXOP_MIN_8822C) +#define BIT_SET_TXOP_MIN_8822C(x, v) \ + (BIT_CLEAR_TXOP_MIN_8822C(x) | BIT_TXOP_MIN_8822C(v)) + +/* 2 REG_PRE_BKF_TIME_8822C */ + +#define BIT_SHIFT_PRE_BKF_TIME_8822C 0 +#define BIT_MASK_PRE_BKF_TIME_8822C 0xff +#define BIT_PRE_BKF_TIME_8822C(x) \ + (((x) & BIT_MASK_PRE_BKF_TIME_8822C) << BIT_SHIFT_PRE_BKF_TIME_8822C) +#define BITS_PRE_BKF_TIME_8822C \ + (BIT_MASK_PRE_BKF_TIME_8822C << BIT_SHIFT_PRE_BKF_TIME_8822C) +#define BIT_CLEAR_PRE_BKF_TIME_8822C(x) ((x) & (~BITS_PRE_BKF_TIME_8822C)) +#define BIT_GET_PRE_BKF_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_PRE_BKF_TIME_8822C) & BIT_MASK_PRE_BKF_TIME_8822C) +#define BIT_SET_PRE_BKF_TIME_8822C(x, v) \ + (BIT_CLEAR_PRE_BKF_TIME_8822C(x) | BIT_PRE_BKF_TIME_8822C(v)) + +/* 2 REG_CROSS_TXOP_CTRL_8822C */ +#define BIT_TXFAIL_BREACK_TXOP_EN_8822C BIT(3) +#define BIT_DTIM_BYPASS_8822C BIT(2) +#define BIT_RTS_NAV_TXOP_8822C BIT(1) +#define BIT_NOT_CROSS_TXOP_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_RX_TBTT_SHIFT_V1_8822C */ +#define BIT_RX_TBTT_SHIFT_RW_FLAG_V1_8822C BIT(31) + +#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C 16 +#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C 0xfff +#define BIT_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C) \ + << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C) +#define BITS_RX_TBTT_SHIFT_OFFSET_V1_8822C \ + (BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C \ + << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C) +#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) \ + ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_V1_8822C)) +#define BIT_GET_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C) & \ + BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C) +#define BIT_SET_RX_TBTT_SHIFT_OFFSET_V1_8822C(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) | \ + BIT_RX_TBTT_SHIFT_OFFSET_V1_8822C(v)) + +#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C 8 +#define BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C 0x7 +#define BIT_RX_TBTT_SHIFT_SEL_V1_8822C(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C) \ + << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C) +#define BITS_RX_TBTT_SHIFT_SEL_V1_8822C \ + (BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C \ + << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C) +#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1_8822C(x) \ + ((x) & (~BITS_RX_TBTT_SHIFT_SEL_V1_8822C)) +#define BIT_GET_RX_TBTT_SHIFT_SEL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C) & \ + BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C) +#define BIT_SET_RX_TBTT_SHIFT_SEL_V1_8822C(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1_8822C(x) | \ + BIT_RX_TBTT_SHIFT_SEL_V1_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ATIMWND2_8822C */ + +#define BIT_SHIFT_ATIMWND2_8822C 0 +#define BIT_MASK_ATIMWND2_8822C 0xff +#define BIT_ATIMWND2_8822C(x) \ + (((x) & BIT_MASK_ATIMWND2_8822C) << BIT_SHIFT_ATIMWND2_8822C) +#define BITS_ATIMWND2_8822C \ + (BIT_MASK_ATIMWND2_8822C << BIT_SHIFT_ATIMWND2_8822C) +#define BIT_CLEAR_ATIMWND2_8822C(x) ((x) & (~BITS_ATIMWND2_8822C)) +#define BIT_GET_ATIMWND2_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND2_8822C) & BIT_MASK_ATIMWND2_8822C) +#define BIT_SET_ATIMWND2_8822C(x, v) \ + (BIT_CLEAR_ATIMWND2_8822C(x) | BIT_ATIMWND2_8822C(v)) + +/* 2 REG_ATIMWND3_8822C */ + +#define BIT_SHIFT_ATIMWND3_8822C 0 +#define BIT_MASK_ATIMWND3_8822C 0xff +#define BIT_ATIMWND3_8822C(x) \ + (((x) & BIT_MASK_ATIMWND3_8822C) << BIT_SHIFT_ATIMWND3_8822C) +#define BITS_ATIMWND3_8822C \ + (BIT_MASK_ATIMWND3_8822C << BIT_SHIFT_ATIMWND3_8822C) +#define BIT_CLEAR_ATIMWND3_8822C(x) ((x) & (~BITS_ATIMWND3_8822C)) +#define BIT_GET_ATIMWND3_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND3_8822C) & BIT_MASK_ATIMWND3_8822C) +#define BIT_SET_ATIMWND3_8822C(x, v) \ + (BIT_CLEAR_ATIMWND3_8822C(x) | BIT_ATIMWND3_8822C(v)) + +/* 2 REG_ATIMWND4_8822C */ + +#define BIT_SHIFT_ATIMWND4_8822C 0 +#define BIT_MASK_ATIMWND4_8822C 0xff +#define BIT_ATIMWND4_8822C(x) \ + (((x) & BIT_MASK_ATIMWND4_8822C) << BIT_SHIFT_ATIMWND4_8822C) +#define BITS_ATIMWND4_8822C \ + (BIT_MASK_ATIMWND4_8822C << BIT_SHIFT_ATIMWND4_8822C) +#define BIT_CLEAR_ATIMWND4_8822C(x) ((x) & (~BITS_ATIMWND4_8822C)) +#define BIT_GET_ATIMWND4_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND4_8822C) & BIT_MASK_ATIMWND4_8822C) +#define BIT_SET_ATIMWND4_8822C(x, v) \ + (BIT_CLEAR_ATIMWND4_8822C(x) | BIT_ATIMWND4_8822C(v)) + +/* 2 REG_ATIMWND5_8822C */ + +#define BIT_SHIFT_ATIMWND5_8822C 0 +#define BIT_MASK_ATIMWND5_8822C 0xff +#define BIT_ATIMWND5_8822C(x) \ + (((x) & BIT_MASK_ATIMWND5_8822C) << BIT_SHIFT_ATIMWND5_8822C) +#define BITS_ATIMWND5_8822C \ + (BIT_MASK_ATIMWND5_8822C << BIT_SHIFT_ATIMWND5_8822C) +#define BIT_CLEAR_ATIMWND5_8822C(x) ((x) & (~BITS_ATIMWND5_8822C)) +#define BIT_GET_ATIMWND5_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND5_8822C) & BIT_MASK_ATIMWND5_8822C) +#define BIT_SET_ATIMWND5_8822C(x, v) \ + (BIT_CLEAR_ATIMWND5_8822C(x) | BIT_ATIMWND5_8822C(v)) + +/* 2 REG_ATIMWND6_8822C */ + +#define BIT_SHIFT_ATIMWND6_8822C 0 +#define BIT_MASK_ATIMWND6_8822C 0xff +#define BIT_ATIMWND6_8822C(x) \ + (((x) & BIT_MASK_ATIMWND6_8822C) << BIT_SHIFT_ATIMWND6_8822C) +#define BITS_ATIMWND6_8822C \ + (BIT_MASK_ATIMWND6_8822C << BIT_SHIFT_ATIMWND6_8822C) +#define BIT_CLEAR_ATIMWND6_8822C(x) ((x) & (~BITS_ATIMWND6_8822C)) +#define BIT_GET_ATIMWND6_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND6_8822C) & BIT_MASK_ATIMWND6_8822C) +#define BIT_SET_ATIMWND6_8822C(x, v) \ + (BIT_CLEAR_ATIMWND6_8822C(x) | BIT_ATIMWND6_8822C(v)) + +/* 2 REG_ATIMWND7_8822C */ + +#define BIT_SHIFT_ATIMWND7_8822C 0 +#define BIT_MASK_ATIMWND7_8822C 0xff +#define BIT_ATIMWND7_8822C(x) \ + (((x) & BIT_MASK_ATIMWND7_8822C) << BIT_SHIFT_ATIMWND7_8822C) +#define BITS_ATIMWND7_8822C \ + (BIT_MASK_ATIMWND7_8822C << BIT_SHIFT_ATIMWND7_8822C) +#define BIT_CLEAR_ATIMWND7_8822C(x) ((x) & (~BITS_ATIMWND7_8822C)) +#define BIT_GET_ATIMWND7_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND7_8822C) & BIT_MASK_ATIMWND7_8822C) +#define BIT_SET_ATIMWND7_8822C(x, v) \ + (BIT_CLEAR_ATIMWND7_8822C(x) | BIT_ATIMWND7_8822C(v)) + +/* 2 REG_ATIMUGT_8822C */ + +#define BIT_SHIFT_ATIM_URGENT_8822C 0 +#define BIT_MASK_ATIM_URGENT_8822C 0xff +#define BIT_ATIM_URGENT_8822C(x) \ + (((x) & BIT_MASK_ATIM_URGENT_8822C) << BIT_SHIFT_ATIM_URGENT_8822C) +#define BITS_ATIM_URGENT_8822C \ + (BIT_MASK_ATIM_URGENT_8822C << BIT_SHIFT_ATIM_URGENT_8822C) +#define BIT_CLEAR_ATIM_URGENT_8822C(x) ((x) & (~BITS_ATIM_URGENT_8822C)) +#define BIT_GET_ATIM_URGENT_8822C(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT_8822C) & BIT_MASK_ATIM_URGENT_8822C) +#define BIT_SET_ATIM_URGENT_8822C(x, v) \ + (BIT_CLEAR_ATIM_URGENT_8822C(x) | BIT_ATIM_URGENT_8822C(v)) + +/* 2 REG_HIQ_NO_LMT_EN_8822C */ +#define BIT_HIQ_NO_LMT_EN_VAP7_8822C BIT(7) +#define BIT_HIQ_NO_LMT_EN_VAP6_8822C BIT(6) +#define BIT_HIQ_NO_LMT_EN_VAP5_8822C BIT(5) +#define BIT_HIQ_NO_LMT_EN_VAP4_8822C BIT(4) +#define BIT_HIQ_NO_LMT_EN_VAP3_8822C BIT(3) +#define BIT_HIQ_NO_LMT_EN_VAP2_8822C BIT(2) +#define BIT_HIQ_NO_LMT_EN_VAP1_8822C BIT(1) +#define BIT_HIQ_NO_LMT_EN_ROOT_8822C BIT(0) + +/* 2 REG_DTIM_COUNTER_ROOT_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_ROOT_8822C 0 +#define BIT_MASK_DTIM_COUNT_ROOT_8822C 0xff +#define BIT_DTIM_COUNT_ROOT_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_ROOT_8822C) \ + << BIT_SHIFT_DTIM_COUNT_ROOT_8822C) +#define BITS_DTIM_COUNT_ROOT_8822C \ + (BIT_MASK_DTIM_COUNT_ROOT_8822C << BIT_SHIFT_DTIM_COUNT_ROOT_8822C) +#define BIT_CLEAR_DTIM_COUNT_ROOT_8822C(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8822C)) +#define BIT_GET_DTIM_COUNT_ROOT_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822C) & \ + BIT_MASK_DTIM_COUNT_ROOT_8822C) +#define BIT_SET_DTIM_COUNT_ROOT_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_ROOT_8822C(x) | BIT_DTIM_COUNT_ROOT_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP1_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP1_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP1_8822C 0xff +#define BIT_DTIM_COUNT_VAP1_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP1_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP1_8822C) +#define BITS_DTIM_COUNT_VAP1_8822C \ + (BIT_MASK_DTIM_COUNT_VAP1_8822C << BIT_SHIFT_DTIM_COUNT_VAP1_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP1_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8822C)) +#define BIT_GET_DTIM_COUNT_VAP1_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP1_8822C) +#define BIT_SET_DTIM_COUNT_VAP1_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP1_8822C(x) | BIT_DTIM_COUNT_VAP1_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP2_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP2_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP2_8822C 0xff +#define BIT_DTIM_COUNT_VAP2_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP2_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP2_8822C) +#define BITS_DTIM_COUNT_VAP2_8822C \ + (BIT_MASK_DTIM_COUNT_VAP2_8822C << BIT_SHIFT_DTIM_COUNT_VAP2_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP2_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8822C)) +#define BIT_GET_DTIM_COUNT_VAP2_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP2_8822C) +#define BIT_SET_DTIM_COUNT_VAP2_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP2_8822C(x) | BIT_DTIM_COUNT_VAP2_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP3_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP3_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP3_8822C 0xff +#define BIT_DTIM_COUNT_VAP3_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP3_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP3_8822C) +#define BITS_DTIM_COUNT_VAP3_8822C \ + (BIT_MASK_DTIM_COUNT_VAP3_8822C << BIT_SHIFT_DTIM_COUNT_VAP3_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP3_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8822C)) +#define BIT_GET_DTIM_COUNT_VAP3_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP3_8822C) +#define BIT_SET_DTIM_COUNT_VAP3_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP3_8822C(x) | BIT_DTIM_COUNT_VAP3_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP4_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP4_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP4_8822C 0xff +#define BIT_DTIM_COUNT_VAP4_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP4_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP4_8822C) +#define BITS_DTIM_COUNT_VAP4_8822C \ + (BIT_MASK_DTIM_COUNT_VAP4_8822C << BIT_SHIFT_DTIM_COUNT_VAP4_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP4_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8822C)) +#define BIT_GET_DTIM_COUNT_VAP4_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP4_8822C) +#define BIT_SET_DTIM_COUNT_VAP4_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP4_8822C(x) | BIT_DTIM_COUNT_VAP4_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP5_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP5_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP5_8822C 0xff +#define BIT_DTIM_COUNT_VAP5_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP5_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP5_8822C) +#define BITS_DTIM_COUNT_VAP5_8822C \ + (BIT_MASK_DTIM_COUNT_VAP5_8822C << BIT_SHIFT_DTIM_COUNT_VAP5_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP5_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8822C)) +#define BIT_GET_DTIM_COUNT_VAP5_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP5_8822C) +#define BIT_SET_DTIM_COUNT_VAP5_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP5_8822C(x) | BIT_DTIM_COUNT_VAP5_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP6_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP6_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP6_8822C 0xff +#define BIT_DTIM_COUNT_VAP6_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP6_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP6_8822C) +#define BITS_DTIM_COUNT_VAP6_8822C \ + (BIT_MASK_DTIM_COUNT_VAP6_8822C << BIT_SHIFT_DTIM_COUNT_VAP6_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP6_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8822C)) +#define BIT_GET_DTIM_COUNT_VAP6_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP6_8822C) +#define BIT_SET_DTIM_COUNT_VAP6_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP6_8822C(x) | BIT_DTIM_COUNT_VAP6_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP7_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP7_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP7_8822C 0xff +#define BIT_DTIM_COUNT_VAP7_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP7_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP7_8822C) +#define BITS_DTIM_COUNT_VAP7_8822C \ + (BIT_MASK_DTIM_COUNT_VAP7_8822C << BIT_SHIFT_DTIM_COUNT_VAP7_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP7_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8822C)) +#define BIT_GET_DTIM_COUNT_VAP7_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP7_8822C) +#define BIT_SET_DTIM_COUNT_VAP7_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP7_8822C(x) | BIT_DTIM_COUNT_VAP7_8822C(v)) + +/* 2 REG_DIS_ATIM_8822C */ +#define BIT_DIS_ATIM_VAP7_8822C BIT(7) +#define BIT_DIS_ATIM_VAP6_8822C BIT(6) +#define BIT_DIS_ATIM_VAP5_8822C BIT(5) +#define BIT_DIS_ATIM_VAP4_8822C BIT(4) +#define BIT_DIS_ATIM_VAP3_8822C BIT(3) +#define BIT_DIS_ATIM_VAP2_8822C BIT(2) +#define BIT_DIS_ATIM_VAP1_8822C BIT(1) +#define BIT_DIS_ATIM_ROOT_8822C BIT(0) + +/* 2 REG_EARLY_128US_8822C */ + +#define BIT_SHIFT_TSFT_SEL_TIMER1_8822C 3 +#define BIT_MASK_TSFT_SEL_TIMER1_8822C 0x7 +#define BIT_TSFT_SEL_TIMER1_8822C(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER1_8822C) \ + << BIT_SHIFT_TSFT_SEL_TIMER1_8822C) +#define BITS_TSFT_SEL_TIMER1_8822C \ + (BIT_MASK_TSFT_SEL_TIMER1_8822C << BIT_SHIFT_TSFT_SEL_TIMER1_8822C) +#define BIT_CLEAR_TSFT_SEL_TIMER1_8822C(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8822C)) +#define BIT_GET_TSFT_SEL_TIMER1_8822C(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822C) & \ + BIT_MASK_TSFT_SEL_TIMER1_8822C) +#define BIT_SET_TSFT_SEL_TIMER1_8822C(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER1_8822C(x) | BIT_TSFT_SEL_TIMER1_8822C(v)) + +#define BIT_SHIFT_EARLY_128US_8822C 0 +#define BIT_MASK_EARLY_128US_8822C 0x7 +#define BIT_EARLY_128US_8822C(x) \ + (((x) & BIT_MASK_EARLY_128US_8822C) << BIT_SHIFT_EARLY_128US_8822C) +#define BITS_EARLY_128US_8822C \ + (BIT_MASK_EARLY_128US_8822C << BIT_SHIFT_EARLY_128US_8822C) +#define BIT_CLEAR_EARLY_128US_8822C(x) ((x) & (~BITS_EARLY_128US_8822C)) +#define BIT_GET_EARLY_128US_8822C(x) \ + (((x) >> BIT_SHIFT_EARLY_128US_8822C) & BIT_MASK_EARLY_128US_8822C) +#define BIT_SET_EARLY_128US_8822C(x, v) \ + (BIT_CLEAR_EARLY_128US_8822C(x) | BIT_EARLY_128US_8822C(v)) + +/* 2 REG_P2PPS1_CTRL_8822C */ +#define BIT_P2P1_CTW_ALLSTASLEEP_8822C BIT(7) +#define BIT_P2P1_OFF_DISTX_EN_8822C BIT(6) +#define BIT_P2P1_PWR_MGT_EN_8822C BIT(5) +#define BIT_P2P1_NOA1_EN_8822C BIT(2) +#define BIT_P2P1_NOA0_EN_8822C BIT(1) + +/* 2 REG_P2PPS2_CTRL_8822C */ +#define BIT_P2P2_CTW_ALLSTASLEEP_8822C BIT(7) +#define BIT_P2P2_OFF_DISTX_EN_8822C BIT(6) +#define BIT_P2P2_PWR_MGT_EN_8822C BIT(5) +#define BIT_P2P2_NOA1_EN_8822C BIT(2) +#define BIT_P2P2_NOA0_EN_8822C BIT(1) + +/* 2 REG_TIMER0_SRC_SEL_8822C */ + +#define BIT_SHIFT_SYNC_CLI_SEL_8822C 4 +#define BIT_MASK_SYNC_CLI_SEL_8822C 0x7 +#define BIT_SYNC_CLI_SEL_8822C(x) \ + (((x) & BIT_MASK_SYNC_CLI_SEL_8822C) << BIT_SHIFT_SYNC_CLI_SEL_8822C) +#define BITS_SYNC_CLI_SEL_8822C \ + (BIT_MASK_SYNC_CLI_SEL_8822C << BIT_SHIFT_SYNC_CLI_SEL_8822C) +#define BIT_CLEAR_SYNC_CLI_SEL_8822C(x) ((x) & (~BITS_SYNC_CLI_SEL_8822C)) +#define BIT_GET_SYNC_CLI_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822C) & BIT_MASK_SYNC_CLI_SEL_8822C) +#define BIT_SET_SYNC_CLI_SEL_8822C(x, v) \ + (BIT_CLEAR_SYNC_CLI_SEL_8822C(x) | BIT_SYNC_CLI_SEL_8822C(v)) + +#define BIT_SHIFT_TSFT_SEL_TIMER0_8822C 0 +#define BIT_MASK_TSFT_SEL_TIMER0_8822C 0x7 +#define BIT_TSFT_SEL_TIMER0_8822C(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER0_8822C) \ + << BIT_SHIFT_TSFT_SEL_TIMER0_8822C) +#define BITS_TSFT_SEL_TIMER0_8822C \ + (BIT_MASK_TSFT_SEL_TIMER0_8822C << BIT_SHIFT_TSFT_SEL_TIMER0_8822C) +#define BIT_CLEAR_TSFT_SEL_TIMER0_8822C(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8822C)) +#define BIT_GET_TSFT_SEL_TIMER0_8822C(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822C) & \ + BIT_MASK_TSFT_SEL_TIMER0_8822C) +#define BIT_SET_TSFT_SEL_TIMER0_8822C(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER0_8822C(x) | BIT_TSFT_SEL_TIMER0_8822C(v)) + +/* 2 REG_NOA_UNIT_SEL_8822C */ + +#define BIT_SHIFT_NOA_UNIT2_SEL_8822C 8 +#define BIT_MASK_NOA_UNIT2_SEL_8822C 0x7 +#define BIT_NOA_UNIT2_SEL_8822C(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL_8822C) << BIT_SHIFT_NOA_UNIT2_SEL_8822C) +#define BITS_NOA_UNIT2_SEL_8822C \ + (BIT_MASK_NOA_UNIT2_SEL_8822C << BIT_SHIFT_NOA_UNIT2_SEL_8822C) +#define BIT_CLEAR_NOA_UNIT2_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT2_SEL_8822C)) +#define BIT_GET_NOA_UNIT2_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822C) & BIT_MASK_NOA_UNIT2_SEL_8822C) +#define BIT_SET_NOA_UNIT2_SEL_8822C(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL_8822C(x) | BIT_NOA_UNIT2_SEL_8822C(v)) + +#define BIT_SHIFT_NOA_UNIT1_SEL_8822C 4 +#define BIT_MASK_NOA_UNIT1_SEL_8822C 0x7 +#define BIT_NOA_UNIT1_SEL_8822C(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL_8822C) << BIT_SHIFT_NOA_UNIT1_SEL_8822C) +#define BITS_NOA_UNIT1_SEL_8822C \ + (BIT_MASK_NOA_UNIT1_SEL_8822C << BIT_SHIFT_NOA_UNIT1_SEL_8822C) +#define BIT_CLEAR_NOA_UNIT1_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT1_SEL_8822C)) +#define BIT_GET_NOA_UNIT1_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822C) & BIT_MASK_NOA_UNIT1_SEL_8822C) +#define BIT_SET_NOA_UNIT1_SEL_8822C(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL_8822C(x) | BIT_NOA_UNIT1_SEL_8822C(v)) + +#define BIT_SHIFT_NOA_UNIT0_SEL_8822C 0 +#define BIT_MASK_NOA_UNIT0_SEL_8822C 0x7 +#define BIT_NOA_UNIT0_SEL_8822C(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL_8822C) << BIT_SHIFT_NOA_UNIT0_SEL_8822C) +#define BITS_NOA_UNIT0_SEL_8822C \ + (BIT_MASK_NOA_UNIT0_SEL_8822C << BIT_SHIFT_NOA_UNIT0_SEL_8822C) +#define BIT_CLEAR_NOA_UNIT0_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT0_SEL_8822C)) +#define BIT_GET_NOA_UNIT0_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822C) & BIT_MASK_NOA_UNIT0_SEL_8822C) +#define BIT_SET_NOA_UNIT0_SEL_8822C(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL_8822C(x) | BIT_NOA_UNIT0_SEL_8822C(v)) + +/* 2 REG_P2POFF_DIS_TXTIME_8822C */ + +#define BIT_SHIFT_P2POFF_DIS_TXTIME_8822C 0 +#define BIT_MASK_P2POFF_DIS_TXTIME_8822C 0xff +#define BIT_P2POFF_DIS_TXTIME_8822C(x) \ + (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822C) \ + << BIT_SHIFT_P2POFF_DIS_TXTIME_8822C) +#define BITS_P2POFF_DIS_TXTIME_8822C \ + (BIT_MASK_P2POFF_DIS_TXTIME_8822C << BIT_SHIFT_P2POFF_DIS_TXTIME_8822C) +#define BIT_CLEAR_P2POFF_DIS_TXTIME_8822C(x) \ + ((x) & (~BITS_P2POFF_DIS_TXTIME_8822C)) +#define BIT_GET_P2POFF_DIS_TXTIME_8822C(x) \ + (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822C) & \ + BIT_MASK_P2POFF_DIS_TXTIME_8822C) +#define BIT_SET_P2POFF_DIS_TXTIME_8822C(x, v) \ + (BIT_CLEAR_P2POFF_DIS_TXTIME_8822C(x) | BIT_P2POFF_DIS_TXTIME_8822C(v)) + +/* 2 REG_MBSSID_BCN_SPACE2_8822C */ + +#define BIT_SHIFT_BCN_SPACE_CLINT2_8822C 16 +#define BIT_MASK_BCN_SPACE_CLINT2_8822C 0xfff +#define BIT_BCN_SPACE_CLINT2_8822C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT2_8822C) \ + << BIT_SHIFT_BCN_SPACE_CLINT2_8822C) +#define BITS_BCN_SPACE_CLINT2_8822C \ + (BIT_MASK_BCN_SPACE_CLINT2_8822C << BIT_SHIFT_BCN_SPACE_CLINT2_8822C) +#define BIT_CLEAR_BCN_SPACE_CLINT2_8822C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT2_8822C)) +#define BIT_GET_BCN_SPACE_CLINT2_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822C) & \ + BIT_MASK_BCN_SPACE_CLINT2_8822C) +#define BIT_SET_BCN_SPACE_CLINT2_8822C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT2_8822C(x) | BIT_BCN_SPACE_CLINT2_8822C(v)) + +#define BIT_SHIFT_BCN_SPACE_CLINT1_8822C 0 +#define BIT_MASK_BCN_SPACE_CLINT1_8822C 0xfff +#define BIT_BCN_SPACE_CLINT1_8822C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT1_8822C) \ + << BIT_SHIFT_BCN_SPACE_CLINT1_8822C) +#define BITS_BCN_SPACE_CLINT1_8822C \ + (BIT_MASK_BCN_SPACE_CLINT1_8822C << BIT_SHIFT_BCN_SPACE_CLINT1_8822C) +#define BIT_CLEAR_BCN_SPACE_CLINT1_8822C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT1_8822C)) +#define BIT_GET_BCN_SPACE_CLINT1_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822C) & \ + BIT_MASK_BCN_SPACE_CLINT1_8822C) +#define BIT_SET_BCN_SPACE_CLINT1_8822C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT1_8822C(x) | BIT_BCN_SPACE_CLINT1_8822C(v)) + +/* 2 REG_MBSSID_BCN_SPACE3_8822C */ + +#define BIT_SHIFT_SUB_BCN_SPACE_8822C 16 +#define BIT_MASK_SUB_BCN_SPACE_8822C 0xff +#define BIT_SUB_BCN_SPACE_8822C(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE_8822C) << BIT_SHIFT_SUB_BCN_SPACE_8822C) +#define BITS_SUB_BCN_SPACE_8822C \ + (BIT_MASK_SUB_BCN_SPACE_8822C << BIT_SHIFT_SUB_BCN_SPACE_8822C) +#define BIT_CLEAR_SUB_BCN_SPACE_8822C(x) ((x) & (~BITS_SUB_BCN_SPACE_8822C)) +#define BIT_GET_SUB_BCN_SPACE_8822C(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822C) & BIT_MASK_SUB_BCN_SPACE_8822C) +#define BIT_SET_SUB_BCN_SPACE_8822C(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE_8822C(x) | BIT_SUB_BCN_SPACE_8822C(v)) + +#define BIT_SHIFT_BCN_SPACE_CLINT3_8822C 0 +#define BIT_MASK_BCN_SPACE_CLINT3_8822C 0xfff +#define BIT_BCN_SPACE_CLINT3_8822C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT3_8822C) \ + << BIT_SHIFT_BCN_SPACE_CLINT3_8822C) +#define BITS_BCN_SPACE_CLINT3_8822C \ + (BIT_MASK_BCN_SPACE_CLINT3_8822C << BIT_SHIFT_BCN_SPACE_CLINT3_8822C) +#define BIT_CLEAR_BCN_SPACE_CLINT3_8822C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT3_8822C)) +#define BIT_GET_BCN_SPACE_CLINT3_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822C) & \ + BIT_MASK_BCN_SPACE_CLINT3_8822C) +#define BIT_SET_BCN_SPACE_CLINT3_8822C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT3_8822C(x) | BIT_BCN_SPACE_CLINT3_8822C(v)) + +/* 2 REG_ACMHWCTRL_8822C */ +#define BIT_BEQ_ACM_STATUS_8822C BIT(7) +#define BIT_VIQ_ACM_STATUS_8822C BIT(6) +#define BIT_VOQ_ACM_STATUS_8822C BIT(5) +#define BIT_BEQ_ACM_EN_8822C BIT(3) +#define BIT_VIQ_ACM_EN_8822C BIT(2) +#define BIT_VOQ_ACM_EN_8822C BIT(1) +#define BIT_ACMHWEN_8822C BIT(0) + +/* 2 REG_ACMRSTCTRL_8822C */ +#define BIT_BE_ACM_RESET_USED_TIME_8822C BIT(2) +#define BIT_VI_ACM_RESET_USED_TIME_8822C BIT(1) +#define BIT_VO_ACM_RESET_USED_TIME_8822C BIT(0) + +/* 2 REG_ACMAVG_8822C */ + +#define BIT_SHIFT_AVGPERIOD_8822C 0 +#define BIT_MASK_AVGPERIOD_8822C 0xffff +#define BIT_AVGPERIOD_8822C(x) \ + (((x) & BIT_MASK_AVGPERIOD_8822C) << BIT_SHIFT_AVGPERIOD_8822C) +#define BITS_AVGPERIOD_8822C \ + (BIT_MASK_AVGPERIOD_8822C << BIT_SHIFT_AVGPERIOD_8822C) +#define BIT_CLEAR_AVGPERIOD_8822C(x) ((x) & (~BITS_AVGPERIOD_8822C)) +#define BIT_GET_AVGPERIOD_8822C(x) \ + (((x) >> BIT_SHIFT_AVGPERIOD_8822C) & BIT_MASK_AVGPERIOD_8822C) +#define BIT_SET_AVGPERIOD_8822C(x, v) \ + (BIT_CLEAR_AVGPERIOD_8822C(x) | BIT_AVGPERIOD_8822C(v)) + +/* 2 REG_VO_ADMTIME_8822C */ + +#define BIT_SHIFT_VO_ADMITTED_TIME_8822C 0 +#define BIT_MASK_VO_ADMITTED_TIME_8822C 0xffff +#define BIT_VO_ADMITTED_TIME_8822C(x) \ + (((x) & BIT_MASK_VO_ADMITTED_TIME_8822C) \ + << BIT_SHIFT_VO_ADMITTED_TIME_8822C) +#define BITS_VO_ADMITTED_TIME_8822C \ + (BIT_MASK_VO_ADMITTED_TIME_8822C << BIT_SHIFT_VO_ADMITTED_TIME_8822C) +#define BIT_CLEAR_VO_ADMITTED_TIME_8822C(x) \ + ((x) & (~BITS_VO_ADMITTED_TIME_8822C)) +#define BIT_GET_VO_ADMITTED_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822C) & \ + BIT_MASK_VO_ADMITTED_TIME_8822C) +#define BIT_SET_VO_ADMITTED_TIME_8822C(x, v) \ + (BIT_CLEAR_VO_ADMITTED_TIME_8822C(x) | BIT_VO_ADMITTED_TIME_8822C(v)) + +/* 2 REG_VI_ADMTIME_8822C */ + +#define BIT_SHIFT_VI_ADMITTED_TIME_8822C 0 +#define BIT_MASK_VI_ADMITTED_TIME_8822C 0xffff +#define BIT_VI_ADMITTED_TIME_8822C(x) \ + (((x) & BIT_MASK_VI_ADMITTED_TIME_8822C) \ + << BIT_SHIFT_VI_ADMITTED_TIME_8822C) +#define BITS_VI_ADMITTED_TIME_8822C \ + (BIT_MASK_VI_ADMITTED_TIME_8822C << BIT_SHIFT_VI_ADMITTED_TIME_8822C) +#define BIT_CLEAR_VI_ADMITTED_TIME_8822C(x) \ + ((x) & (~BITS_VI_ADMITTED_TIME_8822C)) +#define BIT_GET_VI_ADMITTED_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822C) & \ + BIT_MASK_VI_ADMITTED_TIME_8822C) +#define BIT_SET_VI_ADMITTED_TIME_8822C(x, v) \ + (BIT_CLEAR_VI_ADMITTED_TIME_8822C(x) | BIT_VI_ADMITTED_TIME_8822C(v)) + +/* 2 REG_BE_ADMTIME_8822C */ + +#define BIT_SHIFT_BE_ADMITTED_TIME_8822C 0 +#define BIT_MASK_BE_ADMITTED_TIME_8822C 0xffff +#define BIT_BE_ADMITTED_TIME_8822C(x) \ + (((x) & BIT_MASK_BE_ADMITTED_TIME_8822C) \ + << BIT_SHIFT_BE_ADMITTED_TIME_8822C) +#define BITS_BE_ADMITTED_TIME_8822C \ + (BIT_MASK_BE_ADMITTED_TIME_8822C << BIT_SHIFT_BE_ADMITTED_TIME_8822C) +#define BIT_CLEAR_BE_ADMITTED_TIME_8822C(x) \ + ((x) & (~BITS_BE_ADMITTED_TIME_8822C)) +#define BIT_GET_BE_ADMITTED_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822C) & \ + BIT_MASK_BE_ADMITTED_TIME_8822C) +#define BIT_SET_BE_ADMITTED_TIME_8822C(x, v) \ + (BIT_CLEAR_BE_ADMITTED_TIME_8822C(x) | BIT_BE_ADMITTED_TIME_8822C(v)) + +/* 2 REG_MAC_HEADER_NAV_OFFSET_8822C */ + +#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C 0 +#define BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C 0xff +#define BIT_MAC_HEADER_NAV_OFFSET_8822C(x) \ + (((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C) \ + << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C) +#define BITS_MAC_HEADER_NAV_OFFSET_8822C \ + (BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C \ + << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C) +#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8822C(x) \ + ((x) & (~BITS_MAC_HEADER_NAV_OFFSET_8822C)) +#define BIT_GET_MAC_HEADER_NAV_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C) & \ + BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C) +#define BIT_SET_MAC_HEADER_NAV_OFFSET_8822C(x, v) \ + (BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8822C(x) | \ + BIT_MAC_HEADER_NAV_OFFSET_8822C(v)) + +/* 2 REG_DIS_NDPA_NAV_CHECK_8822C */ +#define BIT_CHG_POWER_BCN_AREA_V1_8822C BIT(1) +#define BIT_DIS_NDPA_NAV_CHECK_8822C BIT(0) + +/* 2 REG_EDCA_RANDOM_GEN_8822C */ + +#define BIT_SHIFT_RANDOM_GEN_8822C 0 +#define BIT_MASK_RANDOM_GEN_8822C 0xffffff +#define BIT_RANDOM_GEN_8822C(x) \ + (((x) & BIT_MASK_RANDOM_GEN_8822C) << BIT_SHIFT_RANDOM_GEN_8822C) +#define BITS_RANDOM_GEN_8822C \ + (BIT_MASK_RANDOM_GEN_8822C << BIT_SHIFT_RANDOM_GEN_8822C) +#define BIT_CLEAR_RANDOM_GEN_8822C(x) ((x) & (~BITS_RANDOM_GEN_8822C)) +#define BIT_GET_RANDOM_GEN_8822C(x) \ + (((x) >> BIT_SHIFT_RANDOM_GEN_8822C) & BIT_MASK_RANDOM_GEN_8822C) +#define BIT_SET_RANDOM_GEN_8822C(x, v) \ + (BIT_CLEAR_RANDOM_GEN_8822C(x) | BIT_RANDOM_GEN_8822C(v)) + +/* 2 REG_TXCMD_NOA_SEL_8822C */ + +#define BIT_SHIFT_NOA_SEL_V2_8822C 4 +#define BIT_MASK_NOA_SEL_V2_8822C 0x7 +#define BIT_NOA_SEL_V2_8822C(x) \ + (((x) & BIT_MASK_NOA_SEL_V2_8822C) << BIT_SHIFT_NOA_SEL_V2_8822C) +#define BITS_NOA_SEL_V2_8822C \ + (BIT_MASK_NOA_SEL_V2_8822C << BIT_SHIFT_NOA_SEL_V2_8822C) +#define BIT_CLEAR_NOA_SEL_V2_8822C(x) ((x) & (~BITS_NOA_SEL_V2_8822C)) +#define BIT_GET_NOA_SEL_V2_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V2_8822C) & BIT_MASK_NOA_SEL_V2_8822C) +#define BIT_SET_NOA_SEL_V2_8822C(x, v) \ + (BIT_CLEAR_NOA_SEL_V2_8822C(x) | BIT_NOA_SEL_V2_8822C(v)) + +#define BIT_SHIFT_TXCMD_SEG_SEL_8822C 0 +#define BIT_MASK_TXCMD_SEG_SEL_8822C 0xf +#define BIT_TXCMD_SEG_SEL_8822C(x) \ + (((x) & BIT_MASK_TXCMD_SEG_SEL_8822C) << BIT_SHIFT_TXCMD_SEG_SEL_8822C) +#define BITS_TXCMD_SEG_SEL_8822C \ + (BIT_MASK_TXCMD_SEG_SEL_8822C << BIT_SHIFT_TXCMD_SEG_SEL_8822C) +#define BIT_CLEAR_TXCMD_SEG_SEL_8822C(x) ((x) & (~BITS_TXCMD_SEG_SEL_8822C)) +#define BIT_GET_TXCMD_SEG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822C) & BIT_MASK_TXCMD_SEG_SEL_8822C) +#define BIT_SET_TXCMD_SEG_SEL_8822C(x, v) \ + (BIT_CLEAR_TXCMD_SEG_SEL_8822C(x) | BIT_TXCMD_SEG_SEL_8822C(v)) + +/* 2 REG_32K_CLK_SEL_8822C */ +#define BIT_R_BCNERR_CNT_EN_8822C BIT(20) + +#define BIT_SHIFT_R_BCNERR_PORT_SEL_8822C 16 +#define BIT_MASK_R_BCNERR_PORT_SEL_8822C 0x7 +#define BIT_R_BCNERR_PORT_SEL_8822C(x) \ + (((x) & BIT_MASK_R_BCNERR_PORT_SEL_8822C) \ + << BIT_SHIFT_R_BCNERR_PORT_SEL_8822C) +#define BITS_R_BCNERR_PORT_SEL_8822C \ + (BIT_MASK_R_BCNERR_PORT_SEL_8822C << BIT_SHIFT_R_BCNERR_PORT_SEL_8822C) +#define BIT_CLEAR_R_BCNERR_PORT_SEL_8822C(x) \ + ((x) & (~BITS_R_BCNERR_PORT_SEL_8822C)) +#define BIT_GET_R_BCNERR_PORT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_BCNERR_PORT_SEL_8822C) & \ + BIT_MASK_R_BCNERR_PORT_SEL_8822C) +#define BIT_SET_R_BCNERR_PORT_SEL_8822C(x, v) \ + (BIT_CLEAR_R_BCNERR_PORT_SEL_8822C(x) | BIT_R_BCNERR_PORT_SEL_8822C(v)) + +#define BIT_SHIFT_R_TXPAUSE1_8822C 8 +#define BIT_MASK_R_TXPAUSE1_8822C 0xff +#define BIT_R_TXPAUSE1_8822C(x) \ + (((x) & BIT_MASK_R_TXPAUSE1_8822C) << BIT_SHIFT_R_TXPAUSE1_8822C) +#define BITS_R_TXPAUSE1_8822C \ + (BIT_MASK_R_TXPAUSE1_8822C << BIT_SHIFT_R_TXPAUSE1_8822C) +#define BIT_CLEAR_R_TXPAUSE1_8822C(x) ((x) & (~BITS_R_TXPAUSE1_8822C)) +#define BIT_GET_R_TXPAUSE1_8822C(x) \ + (((x) >> BIT_SHIFT_R_TXPAUSE1_8822C) & BIT_MASK_R_TXPAUSE1_8822C) +#define BIT_SET_R_TXPAUSE1_8822C(x, v) \ + (BIT_CLEAR_R_TXPAUSE1_8822C(x) | BIT_R_TXPAUSE1_8822C(v)) + +#define BIT_SLEEP_32K_EN_V1_8822C BIT(2) + +#define BIT_SHIFT_BW_CFG_8822C 0 +#define BIT_MASK_BW_CFG_8822C 0x3 +#define BIT_BW_CFG_8822C(x) \ + (((x) & BIT_MASK_BW_CFG_8822C) << BIT_SHIFT_BW_CFG_8822C) +#define BITS_BW_CFG_8822C (BIT_MASK_BW_CFG_8822C << BIT_SHIFT_BW_CFG_8822C) +#define BIT_CLEAR_BW_CFG_8822C(x) ((x) & (~BITS_BW_CFG_8822C)) +#define BIT_GET_BW_CFG_8822C(x) \ + (((x) >> BIT_SHIFT_BW_CFG_8822C) & BIT_MASK_BW_CFG_8822C) +#define BIT_SET_BW_CFG_8822C(x, v) \ + (BIT_CLEAR_BW_CFG_8822C(x) | BIT_BW_CFG_8822C(v)) + +/* 2 REG_EARLYINT_ADJUST_8822C */ + +#define BIT_SHIFT_RXBCN_TIMER_8822C 16 +#define BIT_MASK_RXBCN_TIMER_8822C 0xffff +#define BIT_RXBCN_TIMER_8822C(x) \ + (((x) & BIT_MASK_RXBCN_TIMER_8822C) << BIT_SHIFT_RXBCN_TIMER_8822C) +#define BITS_RXBCN_TIMER_8822C \ + (BIT_MASK_RXBCN_TIMER_8822C << BIT_SHIFT_RXBCN_TIMER_8822C) +#define BIT_CLEAR_RXBCN_TIMER_8822C(x) ((x) & (~BITS_RXBCN_TIMER_8822C)) +#define BIT_GET_RXBCN_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_RXBCN_TIMER_8822C) & BIT_MASK_RXBCN_TIMER_8822C) +#define BIT_SET_RXBCN_TIMER_8822C(x, v) \ + (BIT_CLEAR_RXBCN_TIMER_8822C(x) | BIT_RXBCN_TIMER_8822C(v)) + +#define BIT_SHIFT_R_ERLYINTADJ_8822C 0 +#define BIT_MASK_R_ERLYINTADJ_8822C 0xffff +#define BIT_R_ERLYINTADJ_8822C(x) \ + (((x) & BIT_MASK_R_ERLYINTADJ_8822C) << BIT_SHIFT_R_ERLYINTADJ_8822C) +#define BITS_R_ERLYINTADJ_8822C \ + (BIT_MASK_R_ERLYINTADJ_8822C << BIT_SHIFT_R_ERLYINTADJ_8822C) +#define BIT_CLEAR_R_ERLYINTADJ_8822C(x) ((x) & (~BITS_R_ERLYINTADJ_8822C)) +#define BIT_GET_R_ERLYINTADJ_8822C(x) \ + (((x) >> BIT_SHIFT_R_ERLYINTADJ_8822C) & BIT_MASK_R_ERLYINTADJ_8822C) +#define BIT_SET_R_ERLYINTADJ_8822C(x, v) \ + (BIT_CLEAR_R_ERLYINTADJ_8822C(x) | BIT_R_ERLYINTADJ_8822C(v)) + +/* 2 REG_BCNERR_CNT_8822C */ + +#define BIT_SHIFT_BCNERR_CNT_OTHERS_8822C 24 +#define BIT_MASK_BCNERR_CNT_OTHERS_8822C 0xff +#define BIT_BCNERR_CNT_OTHERS_8822C(x) \ + (((x) & BIT_MASK_BCNERR_CNT_OTHERS_8822C) \ + << BIT_SHIFT_BCNERR_CNT_OTHERS_8822C) +#define BITS_BCNERR_CNT_OTHERS_8822C \ + (BIT_MASK_BCNERR_CNT_OTHERS_8822C << BIT_SHIFT_BCNERR_CNT_OTHERS_8822C) +#define BIT_CLEAR_BCNERR_CNT_OTHERS_8822C(x) \ + ((x) & (~BITS_BCNERR_CNT_OTHERS_8822C)) +#define BIT_GET_BCNERR_CNT_OTHERS_8822C(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8822C) & \ + BIT_MASK_BCNERR_CNT_OTHERS_8822C) +#define BIT_SET_BCNERR_CNT_OTHERS_8822C(x, v) \ + (BIT_CLEAR_BCNERR_CNT_OTHERS_8822C(x) | BIT_BCNERR_CNT_OTHERS_8822C(v)) + +#define BIT_SHIFT_BCNERR_CNT_INVALID_8822C 16 +#define BIT_MASK_BCNERR_CNT_INVALID_8822C 0xff +#define BIT_BCNERR_CNT_INVALID_8822C(x) \ + (((x) & BIT_MASK_BCNERR_CNT_INVALID_8822C) \ + << BIT_SHIFT_BCNERR_CNT_INVALID_8822C) +#define BITS_BCNERR_CNT_INVALID_8822C \ + (BIT_MASK_BCNERR_CNT_INVALID_8822C \ + << BIT_SHIFT_BCNERR_CNT_INVALID_8822C) +#define BIT_CLEAR_BCNERR_CNT_INVALID_8822C(x) \ + ((x) & (~BITS_BCNERR_CNT_INVALID_8822C)) +#define BIT_GET_BCNERR_CNT_INVALID_8822C(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8822C) & \ + BIT_MASK_BCNERR_CNT_INVALID_8822C) +#define BIT_SET_BCNERR_CNT_INVALID_8822C(x, v) \ + (BIT_CLEAR_BCNERR_CNT_INVALID_8822C(x) | \ + BIT_BCNERR_CNT_INVALID_8822C(v)) + +#define BIT_SHIFT_BCNERR_CNT_MAC_8822C 8 +#define BIT_MASK_BCNERR_CNT_MAC_8822C 0xff +#define BIT_BCNERR_CNT_MAC_8822C(x) \ + (((x) & BIT_MASK_BCNERR_CNT_MAC_8822C) \ + << BIT_SHIFT_BCNERR_CNT_MAC_8822C) +#define BITS_BCNERR_CNT_MAC_8822C \ + (BIT_MASK_BCNERR_CNT_MAC_8822C << BIT_SHIFT_BCNERR_CNT_MAC_8822C) +#define BIT_CLEAR_BCNERR_CNT_MAC_8822C(x) ((x) & (~BITS_BCNERR_CNT_MAC_8822C)) +#define BIT_GET_BCNERR_CNT_MAC_8822C(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8822C) & \ + BIT_MASK_BCNERR_CNT_MAC_8822C) +#define BIT_SET_BCNERR_CNT_MAC_8822C(x, v) \ + (BIT_CLEAR_BCNERR_CNT_MAC_8822C(x) | BIT_BCNERR_CNT_MAC_8822C(v)) + +#define BIT_SHIFT_BCNERR_CNT_CCA_8822C 0 +#define BIT_MASK_BCNERR_CNT_CCA_8822C 0xff +#define BIT_BCNERR_CNT_CCA_8822C(x) \ + (((x) & BIT_MASK_BCNERR_CNT_CCA_8822C) \ + << BIT_SHIFT_BCNERR_CNT_CCA_8822C) +#define BITS_BCNERR_CNT_CCA_8822C \ + (BIT_MASK_BCNERR_CNT_CCA_8822C << BIT_SHIFT_BCNERR_CNT_CCA_8822C) +#define BIT_CLEAR_BCNERR_CNT_CCA_8822C(x) ((x) & (~BITS_BCNERR_CNT_CCA_8822C)) +#define BIT_GET_BCNERR_CNT_CCA_8822C(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8822C) & \ + BIT_MASK_BCNERR_CNT_CCA_8822C) +#define BIT_SET_BCNERR_CNT_CCA_8822C(x, v) \ + (BIT_CLEAR_BCNERR_CNT_CCA_8822C(x) | BIT_BCNERR_CNT_CCA_8822C(v)) + +/* 2 REG_BCNERR_CNT_2_8822C */ + +#define BIT_SHIFT_BCNERR_CNT_EDCCA_8822C 0 +#define BIT_MASK_BCNERR_CNT_EDCCA_8822C 0xff +#define BIT_BCNERR_CNT_EDCCA_8822C(x) \ + (((x) & BIT_MASK_BCNERR_CNT_EDCCA_8822C) \ + << BIT_SHIFT_BCNERR_CNT_EDCCA_8822C) +#define BITS_BCNERR_CNT_EDCCA_8822C \ + (BIT_MASK_BCNERR_CNT_EDCCA_8822C << BIT_SHIFT_BCNERR_CNT_EDCCA_8822C) +#define BIT_CLEAR_BCNERR_CNT_EDCCA_8822C(x) \ + ((x) & (~BITS_BCNERR_CNT_EDCCA_8822C)) +#define BIT_GET_BCNERR_CNT_EDCCA_8822C(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_EDCCA_8822C) & \ + BIT_MASK_BCNERR_CNT_EDCCA_8822C) +#define BIT_SET_BCNERR_CNT_EDCCA_8822C(x, v) \ + (BIT_CLEAR_BCNERR_CNT_EDCCA_8822C(x) | BIT_BCNERR_CNT_EDCCA_8822C(v)) + +/* 2 REG_NOA_PARAM_8822C */ + +#define BIT_SHIFT_NOA_DURATION_V1_8822C 0 +#define BIT_MASK_NOA_DURATION_V1_8822C 0xffffffffL +#define BIT_NOA_DURATION_V1_8822C(x) \ + (((x) & BIT_MASK_NOA_DURATION_V1_8822C) \ + << BIT_SHIFT_NOA_DURATION_V1_8822C) +#define BITS_NOA_DURATION_V1_8822C \ + (BIT_MASK_NOA_DURATION_V1_8822C << BIT_SHIFT_NOA_DURATION_V1_8822C) +#define BIT_CLEAR_NOA_DURATION_V1_8822C(x) ((x) & (~BITS_NOA_DURATION_V1_8822C)) +#define BIT_GET_NOA_DURATION_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION_V1_8822C) & \ + BIT_MASK_NOA_DURATION_V1_8822C) +#define BIT_SET_NOA_DURATION_V1_8822C(x, v) \ + (BIT_CLEAR_NOA_DURATION_V1_8822C(x) | BIT_NOA_DURATION_V1_8822C(v)) + +/* 2 REG_NOA_PARAM_1_8822C */ + +#define BIT_SHIFT_NOA_INTERVAL_V1_8822C 0 +#define BIT_MASK_NOA_INTERVAL_V1_8822C 0xffffffffL +#define BIT_NOA_INTERVAL_V1_8822C(x) \ + (((x) & BIT_MASK_NOA_INTERVAL_V1_8822C) \ + << BIT_SHIFT_NOA_INTERVAL_V1_8822C) +#define BITS_NOA_INTERVAL_V1_8822C \ + (BIT_MASK_NOA_INTERVAL_V1_8822C << BIT_SHIFT_NOA_INTERVAL_V1_8822C) +#define BIT_CLEAR_NOA_INTERVAL_V1_8822C(x) ((x) & (~BITS_NOA_INTERVAL_V1_8822C)) +#define BIT_GET_NOA_INTERVAL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8822C) & \ + BIT_MASK_NOA_INTERVAL_V1_8822C) +#define BIT_SET_NOA_INTERVAL_V1_8822C(x, v) \ + (BIT_CLEAR_NOA_INTERVAL_V1_8822C(x) | BIT_NOA_INTERVAL_V1_8822C(v)) + +/* 2 REG_NOA_PARAM_2_8822C */ + +#define BIT_SHIFT_NOA_START_TIME_V1_8822C 0 +#define BIT_MASK_NOA_START_TIME_V1_8822C 0xffffffffL +#define BIT_NOA_START_TIME_V1_8822C(x) \ + (((x) & BIT_MASK_NOA_START_TIME_V1_8822C) \ + << BIT_SHIFT_NOA_START_TIME_V1_8822C) +#define BITS_NOA_START_TIME_V1_8822C \ + (BIT_MASK_NOA_START_TIME_V1_8822C << BIT_SHIFT_NOA_START_TIME_V1_8822C) +#define BIT_CLEAR_NOA_START_TIME_V1_8822C(x) \ + ((x) & (~BITS_NOA_START_TIME_V1_8822C)) +#define BIT_GET_NOA_START_TIME_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8822C) & \ + BIT_MASK_NOA_START_TIME_V1_8822C) +#define BIT_SET_NOA_START_TIME_V1_8822C(x, v) \ + (BIT_CLEAR_NOA_START_TIME_V1_8822C(x) | BIT_NOA_START_TIME_V1_8822C(v)) + +/* 2 REG_NOA_PARAM_3_8822C */ + +#define BIT_SHIFT_NOA_COUNT_V1_8822C 0 +#define BIT_MASK_NOA_COUNT_V1_8822C 0xffffffffL +#define BIT_NOA_COUNT_V1_8822C(x) \ + (((x) & BIT_MASK_NOA_COUNT_V1_8822C) << BIT_SHIFT_NOA_COUNT_V1_8822C) +#define BITS_NOA_COUNT_V1_8822C \ + (BIT_MASK_NOA_COUNT_V1_8822C << BIT_SHIFT_NOA_COUNT_V1_8822C) +#define BIT_CLEAR_NOA_COUNT_V1_8822C(x) ((x) & (~BITS_NOA_COUNT_V1_8822C)) +#define BIT_GET_NOA_COUNT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_V1_8822C) & BIT_MASK_NOA_COUNT_V1_8822C) +#define BIT_SET_NOA_COUNT_V1_8822C(x, v) \ + (BIT_CLEAR_NOA_COUNT_V1_8822C(x) | BIT_NOA_COUNT_V1_8822C(v)) + +/* 2 REG_P2P_RST_8822C */ +#define BIT_P2P2_PWR_RST1_8822C BIT(5) +#define BIT_P2P2_PWR_RST0_8822C BIT(4) +#define BIT_P2P1_PWR_RST1_8822C BIT(3) +#define BIT_P2P1_PWR_RST0_8822C BIT(2) +#define BIT_P2P_PWR_RST1_V1_8822C BIT(1) +#define BIT_P2P_PWR_RST0_V1_8822C BIT(0) + +/* 2 REG_SCHEDULER_RST_8822C */ +#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8822C BIT(2) +#define BIT_SYNC_CLI_ONCE_BY_TBTT_8822C BIT(1) +#define BIT_SCHEDULER_RST_V1_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SCH_DBG_VALUE_8822C */ + +#define BIT_SHIFT_SCH_DBG_VALUE_8822C 0 +#define BIT_MASK_SCH_DBG_VALUE_8822C 0xffffffffL +#define BIT_SCH_DBG_VALUE_8822C(x) \ + (((x) & BIT_MASK_SCH_DBG_VALUE_8822C) << BIT_SHIFT_SCH_DBG_VALUE_8822C) +#define BITS_SCH_DBG_VALUE_8822C \ + (BIT_MASK_SCH_DBG_VALUE_8822C << BIT_SHIFT_SCH_DBG_VALUE_8822C) +#define BIT_CLEAR_SCH_DBG_VALUE_8822C(x) ((x) & (~BITS_SCH_DBG_VALUE_8822C)) +#define BIT_GET_SCH_DBG_VALUE_8822C(x) \ + (((x) >> BIT_SHIFT_SCH_DBG_VALUE_8822C) & BIT_MASK_SCH_DBG_VALUE_8822C) +#define BIT_SET_SCH_DBG_VALUE_8822C(x, v) \ + (BIT_CLEAR_SCH_DBG_VALUE_8822C(x) | BIT_SCH_DBG_VALUE_8822C(v)) + +/* 2 REG_SCH_TXCMD_8822C */ + +#define BIT_SHIFT_SCH_TXCMD_8822C 0 +#define BIT_MASK_SCH_TXCMD_8822C 0xffffffffL +#define BIT_SCH_TXCMD_8822C(x) \ + (((x) & BIT_MASK_SCH_TXCMD_8822C) << BIT_SHIFT_SCH_TXCMD_8822C) +#define BITS_SCH_TXCMD_8822C \ + (BIT_MASK_SCH_TXCMD_8822C << BIT_SHIFT_SCH_TXCMD_8822C) +#define BIT_CLEAR_SCH_TXCMD_8822C(x) ((x) & (~BITS_SCH_TXCMD_8822C)) +#define BIT_GET_SCH_TXCMD_8822C(x) \ + (((x) >> BIT_SHIFT_SCH_TXCMD_8822C) & BIT_MASK_SCH_TXCMD_8822C) +#define BIT_SET_SCH_TXCMD_8822C(x, v) \ + (BIT_CLEAR_SCH_TXCMD_8822C(x) | BIT_SCH_TXCMD_8822C(v)) + +/* 2 REG_PAGE5_DUMMY_8822C */ + +/* 2 REG_CPUMGQ_TX_TIMER_8822C */ + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C 0xffffffffL +#define BIT_CPUMGQ_TX_TIMER_V1_8822C(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C) +#define BITS_CPUMGQ_TX_TIMER_V1_8822C \ + (BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822C(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8822C)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822C(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C) & \ + BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C) +#define BIT_SET_CPUMGQ_TX_TIMER_V1_8822C(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822C(x) | \ + BIT_CPUMGQ_TX_TIMER_V1_8822C(v)) + +/* 2 REG_PS_TIMER_A_8822C */ + +#define BIT_SHIFT_PS_TIMER_A_V1_8822C 0 +#define BIT_MASK_PS_TIMER_A_V1_8822C 0xffffffffL +#define BIT_PS_TIMER_A_V1_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_A_V1_8822C) << BIT_SHIFT_PS_TIMER_A_V1_8822C) +#define BITS_PS_TIMER_A_V1_8822C \ + (BIT_MASK_PS_TIMER_A_V1_8822C << BIT_SHIFT_PS_TIMER_A_V1_8822C) +#define BIT_CLEAR_PS_TIMER_A_V1_8822C(x) ((x) & (~BITS_PS_TIMER_A_V1_8822C)) +#define BIT_GET_PS_TIMER_A_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822C) & BIT_MASK_PS_TIMER_A_V1_8822C) +#define BIT_SET_PS_TIMER_A_V1_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_A_V1_8822C(x) | BIT_PS_TIMER_A_V1_8822C(v)) + +/* 2 REG_PS_TIMER_B_8822C */ + +#define BIT_SHIFT_PS_TIMER_B_V1_8822C 0 +#define BIT_MASK_PS_TIMER_B_V1_8822C 0xffffffffL +#define BIT_PS_TIMER_B_V1_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_B_V1_8822C) << BIT_SHIFT_PS_TIMER_B_V1_8822C) +#define BITS_PS_TIMER_B_V1_8822C \ + (BIT_MASK_PS_TIMER_B_V1_8822C << BIT_SHIFT_PS_TIMER_B_V1_8822C) +#define BIT_CLEAR_PS_TIMER_B_V1_8822C(x) ((x) & (~BITS_PS_TIMER_B_V1_8822C)) +#define BIT_GET_PS_TIMER_B_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822C) & BIT_MASK_PS_TIMER_B_V1_8822C) +#define BIT_SET_PS_TIMER_B_V1_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_B_V1_8822C(x) | BIT_PS_TIMER_B_V1_8822C(v)) + +/* 2 REG_PS_TIMER_C_8822C */ + +#define BIT_SHIFT_PS_TIMER_C_V1_8822C 0 +#define BIT_MASK_PS_TIMER_C_V1_8822C 0xffffffffL +#define BIT_PS_TIMER_C_V1_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_C_V1_8822C) << BIT_SHIFT_PS_TIMER_C_V1_8822C) +#define BITS_PS_TIMER_C_V1_8822C \ + (BIT_MASK_PS_TIMER_C_V1_8822C << BIT_SHIFT_PS_TIMER_C_V1_8822C) +#define BIT_CLEAR_PS_TIMER_C_V1_8822C(x) ((x) & (~BITS_PS_TIMER_C_V1_8822C)) +#define BIT_GET_PS_TIMER_C_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822C) & BIT_MASK_PS_TIMER_C_V1_8822C) +#define BIT_SET_PS_TIMER_C_V1_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_C_V1_8822C(x) | BIT_PS_TIMER_C_V1_8822C(v)) + +/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822C */ +#define BIT_CPUMGQ_TIMER_EN_8822C BIT(31) +#define BIT_CPUMGQ_TX_EN_8822C BIT(28) + +#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C 24 +#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C 0x7 +#define BIT_CPUMGQ_TIMER_TSF_SEL_8822C(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C) +#define BITS_CPUMGQ_TIMER_TSF_SEL_8822C \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822C(x) \ + ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8822C)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8822C(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822C(x) | \ + BIT_CPUMGQ_TIMER_TSF_SEL_8822C(v)) + +#define BIT_PS_TIMER_C_EN_8822C BIT(23) + +#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C 16 +#define BIT_MASK_PS_TIMER_C_TSF_SEL_8822C 0x7 +#define BIT_PS_TIMER_C_TSF_SEL_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822C) \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C) +#define BITS_PS_TIMER_C_TSF_SEL_8822C \ + (BIT_MASK_PS_TIMER_C_TSF_SEL_8822C \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C) +#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822C(x) \ + ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8822C)) +#define BIT_GET_PS_TIMER_C_TSF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C) & \ + BIT_MASK_PS_TIMER_C_TSF_SEL_8822C) +#define BIT_SET_PS_TIMER_C_TSF_SEL_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822C(x) | \ + BIT_PS_TIMER_C_TSF_SEL_8822C(v)) + +#define BIT_PS_TIMER_B_EN_8822C BIT(15) + +#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C 8 +#define BIT_MASK_PS_TIMER_B_TSF_SEL_8822C 0x7 +#define BIT_PS_TIMER_B_TSF_SEL_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822C) \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C) +#define BITS_PS_TIMER_B_TSF_SEL_8822C \ + (BIT_MASK_PS_TIMER_B_TSF_SEL_8822C \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C) +#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822C(x) \ + ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8822C)) +#define BIT_GET_PS_TIMER_B_TSF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C) & \ + BIT_MASK_PS_TIMER_B_TSF_SEL_8822C) +#define BIT_SET_PS_TIMER_B_TSF_SEL_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822C(x) | \ + BIT_PS_TIMER_B_TSF_SEL_8822C(v)) + +#define BIT_PS_TIMER_A_EN_8822C BIT(7) + +#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C 0 +#define BIT_MASK_PS_TIMER_A_TSF_SEL_8822C 0x7 +#define BIT_PS_TIMER_A_TSF_SEL_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822C) \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C) +#define BITS_PS_TIMER_A_TSF_SEL_8822C \ + (BIT_MASK_PS_TIMER_A_TSF_SEL_8822C \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C) +#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822C(x) \ + ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8822C)) +#define BIT_GET_PS_TIMER_A_TSF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C) & \ + BIT_MASK_PS_TIMER_A_TSF_SEL_8822C) +#define BIT_SET_PS_TIMER_A_TSF_SEL_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822C(x) | \ + BIT_PS_TIMER_A_TSF_SEL_8822C(v)) + +/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8822C */ + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C 0xff +#define BIT_CPUMGQ_TX_TIMER_EARLY_8822C(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C) +#define BITS_CPUMGQ_TX_TIMER_EARLY_8822C \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822C(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8822C)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822C(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8822C(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822C(x) | \ + BIT_CPUMGQ_TX_TIMER_EARLY_8822C(v)) + +/* 2 REG_PS_TIMER_A_EARLY_8822C */ + +#define BIT_SHIFT_PS_TIMER_A_EARLY_8822C 0 +#define BIT_MASK_PS_TIMER_A_EARLY_8822C 0xff +#define BIT_PS_TIMER_A_EARLY_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_A_EARLY_8822C) \ + << BIT_SHIFT_PS_TIMER_A_EARLY_8822C) +#define BITS_PS_TIMER_A_EARLY_8822C \ + (BIT_MASK_PS_TIMER_A_EARLY_8822C << BIT_SHIFT_PS_TIMER_A_EARLY_8822C) +#define BIT_CLEAR_PS_TIMER_A_EARLY_8822C(x) \ + ((x) & (~BITS_PS_TIMER_A_EARLY_8822C)) +#define BIT_GET_PS_TIMER_A_EARLY_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822C) & \ + BIT_MASK_PS_TIMER_A_EARLY_8822C) +#define BIT_SET_PS_TIMER_A_EARLY_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_A_EARLY_8822C(x) | BIT_PS_TIMER_A_EARLY_8822C(v)) + +/* 2 REG_PS_TIMER_B_EARLY_8822C */ + +#define BIT_SHIFT_PS_TIMER_B_EARLY_8822C 0 +#define BIT_MASK_PS_TIMER_B_EARLY_8822C 0xff +#define BIT_PS_TIMER_B_EARLY_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_B_EARLY_8822C) \ + << BIT_SHIFT_PS_TIMER_B_EARLY_8822C) +#define BITS_PS_TIMER_B_EARLY_8822C \ + (BIT_MASK_PS_TIMER_B_EARLY_8822C << BIT_SHIFT_PS_TIMER_B_EARLY_8822C) +#define BIT_CLEAR_PS_TIMER_B_EARLY_8822C(x) \ + ((x) & (~BITS_PS_TIMER_B_EARLY_8822C)) +#define BIT_GET_PS_TIMER_B_EARLY_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822C) & \ + BIT_MASK_PS_TIMER_B_EARLY_8822C) +#define BIT_SET_PS_TIMER_B_EARLY_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_B_EARLY_8822C(x) | BIT_PS_TIMER_B_EARLY_8822C(v)) + +/* 2 REG_PS_TIMER_C_EARLY_8822C */ + +#define BIT_SHIFT_PS_TIMER_C_EARLY_8822C 0 +#define BIT_MASK_PS_TIMER_C_EARLY_8822C 0xff +#define BIT_PS_TIMER_C_EARLY_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_C_EARLY_8822C) \ + << BIT_SHIFT_PS_TIMER_C_EARLY_8822C) +#define BITS_PS_TIMER_C_EARLY_8822C \ + (BIT_MASK_PS_TIMER_C_EARLY_8822C << BIT_SHIFT_PS_TIMER_C_EARLY_8822C) +#define BIT_CLEAR_PS_TIMER_C_EARLY_8822C(x) \ + ((x) & (~BITS_PS_TIMER_C_EARLY_8822C)) +#define BIT_GET_PS_TIMER_C_EARLY_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822C) & \ + BIT_MASK_PS_TIMER_C_EARLY_8822C) +#define BIT_SET_PS_TIMER_C_EARLY_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_C_EARLY_8822C(x) | BIT_PS_TIMER_C_EARLY_8822C(v)) + +/* 2 REG_CPUMGQ_PARAMETER_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_MAC_STOP_CPUMGQ_8822C BIT(16) + +#define BIT_SHIFT_CW_8822C 8 +#define BIT_MASK_CW_8822C 0xff +#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C) +#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C) +#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C)) +#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C) +#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v)) + +#define BIT_SHIFT_AIFS_8822C 0 +#define BIT_MASK_AIFS_8822C 0xff +#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C) +#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C) +#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C)) +#define BIT_GET_AIFS_8822C(x) \ + (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C) +#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_TSF_SYNC_ADJ_8822C */ + +#define BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C 16 +#define BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C 0xffff +#define BIT_R_P0_TSFT_ADJ_VAL_8822C(x) \ + (((x) & BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C) \ + << BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C) +#define BITS_R_P0_TSFT_ADJ_VAL_8822C \ + (BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C << BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C) +#define BIT_CLEAR_R_P0_TSFT_ADJ_VAL_8822C(x) \ + ((x) & (~BITS_R_P0_TSFT_ADJ_VAL_8822C)) +#define BIT_GET_R_P0_TSFT_ADJ_VAL_8822C(x) \ + (((x) >> BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C) & \ + BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C) +#define BIT_SET_R_P0_TSFT_ADJ_VAL_8822C(x, v) \ + (BIT_CLEAR_R_P0_TSFT_ADJ_VAL_8822C(x) | BIT_R_P0_TSFT_ADJ_VAL_8822C(v)) + +#define BIT_R_X_COMP_Y_OVER_8822C BIT(8) + +#define BIT_SHIFT_R_X_SYNC_SEL_8822C 3 +#define BIT_MASK_R_X_SYNC_SEL_8822C 0x7 +#define BIT_R_X_SYNC_SEL_8822C(x) \ + (((x) & BIT_MASK_R_X_SYNC_SEL_8822C) << BIT_SHIFT_R_X_SYNC_SEL_8822C) +#define BITS_R_X_SYNC_SEL_8822C \ + (BIT_MASK_R_X_SYNC_SEL_8822C << BIT_SHIFT_R_X_SYNC_SEL_8822C) +#define BIT_CLEAR_R_X_SYNC_SEL_8822C(x) ((x) & (~BITS_R_X_SYNC_SEL_8822C)) +#define BIT_GET_R_X_SYNC_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_X_SYNC_SEL_8822C) & BIT_MASK_R_X_SYNC_SEL_8822C) +#define BIT_SET_R_X_SYNC_SEL_8822C(x, v) \ + (BIT_CLEAR_R_X_SYNC_SEL_8822C(x) | BIT_R_X_SYNC_SEL_8822C(v)) + +#define BIT_SHIFT_R_SYNC_Y_SEL_8822C 0 +#define BIT_MASK_R_SYNC_Y_SEL_8822C 0x7 +#define BIT_R_SYNC_Y_SEL_8822C(x) \ + (((x) & BIT_MASK_R_SYNC_Y_SEL_8822C) << BIT_SHIFT_R_SYNC_Y_SEL_8822C) +#define BITS_R_SYNC_Y_SEL_8822C \ + (BIT_MASK_R_SYNC_Y_SEL_8822C << BIT_SHIFT_R_SYNC_Y_SEL_8822C) +#define BIT_CLEAR_R_SYNC_Y_SEL_8822C(x) ((x) & (~BITS_R_SYNC_Y_SEL_8822C)) +#define BIT_GET_R_SYNC_Y_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_SYNC_Y_SEL_8822C) & BIT_MASK_R_SYNC_Y_SEL_8822C) +#define BIT_SET_R_SYNC_Y_SEL_8822C(x, v) \ + (BIT_CLEAR_R_SYNC_Y_SEL_8822C(x) | BIT_R_SYNC_Y_SEL_8822C(v)) + +/* 2 REG_TSF_ADJ_VLAUE_8822C */ + +#define BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C 16 +#define BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C 0xffff +#define BIT_R_CLI1_TSFT_ADJ_VAL_8822C(x) \ + (((x) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C) \ + << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C) +#define BITS_R_CLI1_TSFT_ADJ_VAL_8822C \ + (BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C \ + << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C) +#define BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL_8822C(x) \ + ((x) & (~BITS_R_CLI1_TSFT_ADJ_VAL_8822C)) +#define BIT_GET_R_CLI1_TSFT_ADJ_VAL_8822C(x) \ + (((x) >> BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C) & \ + BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C) +#define BIT_SET_R_CLI1_TSFT_ADJ_VAL_8822C(x, v) \ + (BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL_8822C(x) | \ + BIT_R_CLI1_TSFT_ADJ_VAL_8822C(v)) + +#define BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C 0 +#define BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C 0xffff +#define BIT_R_CLI0_TSFT_ADJ_VAL_8822C(x) \ + (((x) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C) \ + << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C) +#define BITS_R_CLI0_TSFT_ADJ_VAL_8822C \ + (BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C \ + << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C) +#define BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL_8822C(x) \ + ((x) & (~BITS_R_CLI0_TSFT_ADJ_VAL_8822C)) +#define BIT_GET_R_CLI0_TSFT_ADJ_VAL_8822C(x) \ + (((x) >> BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C) & \ + BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C) +#define BIT_SET_R_CLI0_TSFT_ADJ_VAL_8822C(x, v) \ + (BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL_8822C(x) | \ + BIT_R_CLI0_TSFT_ADJ_VAL_8822C(v)) + +/* 2 REG_TSF_ADJ_VLAUE_2_8822C */ + +#define BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C 16 +#define BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C 0xffff +#define BIT_R_CLI3_TSFT_ADJ_VAL_8822C(x) \ + (((x) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C) \ + << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C) +#define BITS_R_CLI3_TSFT_ADJ_VAL_8822C \ + (BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C \ + << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C) +#define BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL_8822C(x) \ + ((x) & (~BITS_R_CLI3_TSFT_ADJ_VAL_8822C)) +#define BIT_GET_R_CLI3_TSFT_ADJ_VAL_8822C(x) \ + (((x) >> BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C) & \ + BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C) +#define BIT_SET_R_CLI3_TSFT_ADJ_VAL_8822C(x, v) \ + (BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL_8822C(x) | \ + BIT_R_CLI3_TSFT_ADJ_VAL_8822C(v)) + +#define BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C 0 +#define BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C 0xffff +#define BIT_R_CLI2_TSFT_ADJ_VAL_8822C(x) \ + (((x) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C) \ + << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C) +#define BITS_R_CLI2_TSFT_ADJ_VAL_8822C \ + (BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C \ + << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C) +#define BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL_8822C(x) \ + ((x) & (~BITS_R_CLI2_TSFT_ADJ_VAL_8822C)) +#define BIT_GET_R_CLI2_TSFT_ADJ_VAL_8822C(x) \ + (((x) >> BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C) & \ + BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C) +#define BIT_SET_R_CLI2_TSFT_ADJ_VAL_8822C(x, v) \ + (BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL_8822C(x) | \ + BIT_R_CLI2_TSFT_ADJ_VAL_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C */ +#define BIT_P2PPS_NOA_STOP_TX_HANG_8822C BIT(31) +#define BIT_P2PPS_MACID_PAUSE_EN_8822C BIT(11) +#define BIT_P2PPS__MGQ_PAUSE_8822C BIT(10) +#define BIT_P2PPS__HIQ_PAUSE_8822C BIT(9) +#define BIT_P2PPS__BCNQ_PAUSE_8822C BIT(8) + +#define BIT_SHIFT_P2PPS_MACID_PAUSE_8822C 0 +#define BIT_MASK_P2PPS_MACID_PAUSE_8822C 0xff +#define BIT_P2PPS_MACID_PAUSE_8822C(x) \ + (((x) & BIT_MASK_P2PPS_MACID_PAUSE_8822C) \ + << BIT_SHIFT_P2PPS_MACID_PAUSE_8822C) +#define BITS_P2PPS_MACID_PAUSE_8822C \ + (BIT_MASK_P2PPS_MACID_PAUSE_8822C << BIT_SHIFT_P2PPS_MACID_PAUSE_8822C) +#define BIT_CLEAR_P2PPS_MACID_PAUSE_8822C(x) \ + ((x) & (~BITS_P2PPS_MACID_PAUSE_8822C)) +#define BIT_GET_P2PPS_MACID_PAUSE_8822C(x) \ + (((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE_8822C) & \ + BIT_MASK_P2PPS_MACID_PAUSE_8822C) +#define BIT_SET_P2PPS_MACID_PAUSE_8822C(x, v) \ + (BIT_CLEAR_P2PPS_MACID_PAUSE_8822C(x) | BIT_P2PPS_MACID_PAUSE_8822C(v)) + +/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C */ +#define BIT_P2PPS1_NOA_STOP_TX_HANG_8822C BIT(31) +#define BIT_P2PPS1_MACID_PAUSE_EN_8822C BIT(11) +#define BIT_P2PPS1__MGQ_PAUSE_8822C BIT(10) +#define BIT_P2PPS1__HIQ_PAUSE_8822C BIT(9) +#define BIT_P2PPS1__BCNQ_PAUSE_8822C BIT(8) + +#define BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C 0 +#define BIT_MASK_P2PPS1_MACID_PAUSE_8822C 0xff +#define BIT_P2PPS1_MACID_PAUSE_8822C(x) \ + (((x) & BIT_MASK_P2PPS1_MACID_PAUSE_8822C) \ + << BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C) +#define BITS_P2PPS1_MACID_PAUSE_8822C \ + (BIT_MASK_P2PPS1_MACID_PAUSE_8822C \ + << BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C) +#define BIT_CLEAR_P2PPS1_MACID_PAUSE_8822C(x) \ + ((x) & (~BITS_P2PPS1_MACID_PAUSE_8822C)) +#define BIT_GET_P2PPS1_MACID_PAUSE_8822C(x) \ + (((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C) & \ + BIT_MASK_P2PPS1_MACID_PAUSE_8822C) +#define BIT_SET_P2PPS1_MACID_PAUSE_8822C(x, v) \ + (BIT_CLEAR_P2PPS1_MACID_PAUSE_8822C(x) | \ + BIT_P2PPS1_MACID_PAUSE_8822C(v)) + +/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C */ +#define BIT_P2PPS2_NOA_STOP_TX_HANG_8822C BIT(31) +#define BIT_P2PPS2_MACID_PAUSE_EN_8822C BIT(11) +#define BIT_P2PPS2__MGQ_PAUSE_8822C BIT(10) +#define BIT_P2PPS2__HIQ_PAUSE_8822C BIT(9) +#define BIT_P2PPS2__BCNQ_PAUSE_8822C BIT(8) + +#define BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C 0 +#define BIT_MASK_P2PPS2_MACID_PAUSE_8822C 0xff +#define BIT_P2PPS2_MACID_PAUSE_8822C(x) \ + (((x) & BIT_MASK_P2PPS2_MACID_PAUSE_8822C) \ + << BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C) +#define BITS_P2PPS2_MACID_PAUSE_8822C \ + (BIT_MASK_P2PPS2_MACID_PAUSE_8822C \ + << BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C) +#define BIT_CLEAR_P2PPS2_MACID_PAUSE_8822C(x) \ + ((x) & (~BITS_P2PPS2_MACID_PAUSE_8822C)) +#define BIT_GET_P2PPS2_MACID_PAUSE_8822C(x) \ + (((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C) & \ + BIT_MASK_P2PPS2_MACID_PAUSE_8822C) +#define BIT_SET_P2PPS2_MACID_PAUSE_8822C(x, v) \ + (BIT_CLEAR_P2PPS2_MACID_PAUSE_8822C(x) | \ + BIT_P2PPS2_MACID_PAUSE_8822C(v)) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_WMAC_CR_8822C (WMAC CR AND APSD CONTROL REGISTER) */ +#define BIT_IC_MACPHY_M_8822C BIT(0) + +/* 2 REG_WMAC_FWPKT_CR_8822C */ +#define BIT_FWEN_8822C BIT(7) +#define BIT_PHYSTS_PKT_CTRL_8822C BIT(6) +#define BIT_APPHDR_MIDSRCH_FAIL_8822C BIT(4) +#define BIT_FWPARSING_EN_8822C BIT(3) + +#define BIT_SHIFT_APPEND_MHDR_LEN_8822C 0 +#define BIT_MASK_APPEND_MHDR_LEN_8822C 0x7 +#define BIT_APPEND_MHDR_LEN_8822C(x) \ + (((x) & BIT_MASK_APPEND_MHDR_LEN_8822C) \ + << BIT_SHIFT_APPEND_MHDR_LEN_8822C) +#define BITS_APPEND_MHDR_LEN_8822C \ + (BIT_MASK_APPEND_MHDR_LEN_8822C << BIT_SHIFT_APPEND_MHDR_LEN_8822C) +#define BIT_CLEAR_APPEND_MHDR_LEN_8822C(x) ((x) & (~BITS_APPEND_MHDR_LEN_8822C)) +#define BIT_GET_APPEND_MHDR_LEN_8822C(x) \ + (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822C) & \ + BIT_MASK_APPEND_MHDR_LEN_8822C) +#define BIT_SET_APPEND_MHDR_LEN_8822C(x, v) \ + (BIT_CLEAR_APPEND_MHDR_LEN_8822C(x) | BIT_APPEND_MHDR_LEN_8822C(v)) + +/* 2 REG_FW_STS_FILTER_8822C */ +#define BIT_DATA_FW_STS_FILTER_8822C BIT(2) +#define BIT_CTRL_FW_STS_FILTER_8822C BIT(1) +#define BIT_MGNT_FW_STS_FILTER_8822C BIT(0) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_TCR_8822C (TRANSMISSION CONFIGURATION REGISTER) */ +#define BIT_WMAC_EN_RTS_ADDR_8822C BIT(31) +#define BIT_WMAC_DISABLE_CCK_8822C BIT(30) +#define BIT_WMAC_RAW_LEN_8822C BIT(29) +#define BIT_WMAC_NOTX_IN_RXNDP_8822C BIT(28) +#define BIT_WMAC_EN_EOF_8822C BIT(27) +#define BIT_WMAC_BF_SEL_8822C BIT(26) +#define BIT_WMAC_ANTMODE_SEL_8822C BIT(25) +#define BIT_WMAC_TCRPWRMGT_HWCTL_8822C BIT(24) +#define BIT_WMAC_SMOOTH_VAL_8822C BIT(23) +#define BIT_WMAC_EN_SCRAM_INC_8822C BIT(22) +#define BIT_UNDERFLOWEN_CMPLEN_SEL_8822C BIT(21) +#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8822C BIT(20) +#define BIT_WMAC_TCR_EN_20MST_8822C BIT(19) +#define BIT_WMAC_DIS_SIGTA_8822C BIT(18) +#define BIT_WMAC_DIS_A2B0_8822C BIT(17) +#define BIT_WMAC_MSK_SIGBCRC_8822C BIT(16) +#define BIT_WMAC_TCR_ERRSTEN_3_8822C BIT(15) +#define BIT_WMAC_TCR_ERRSTEN_2_8822C BIT(14) +#define BIT_WMAC_TCR_ERRSTEN_1_8822C BIT(13) +#define BIT_WMAC_TCR_ERRSTEN_0_8822C BIT(12) +#define BIT_WMAC_TCR_TXSK_PERPKT_8822C BIT(11) +#define BIT_ICV_8822C BIT(10) +#define BIT_CFEND_FORMAT_8822C BIT(9) +#define BIT_CRC_8822C BIT(8) +#define BIT_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(7) +#define BIT_PWR_ST_8822C BIT(6) +#define BIT_WMAC_TCR_UPD_TIMIE_8822C BIT(5) +#define BIT_WMAC_TCR_UPD_HGQMD_8822C BIT(4) +#define BIT_VHTSIGA1_TXPS_8822C BIT(3) +#define BIT_PAD_SEL_8822C BIT(2) +#define BIT_DIS_GCLK_8822C BIT(1) +#define BIT_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(0) + +/* 2 REG_RCR_8822C (RECEIVE CONFIGURATION REGISTER) */ +#define BIT_APP_FCS_8822C BIT(31) +#define BIT_APP_MIC_8822C BIT(30) +#define BIT_APP_ICV_8822C BIT(29) +#define BIT_APP_PHYSTS_8822C BIT(28) +#define BIT_APP_BASSN_8822C BIT(27) +#define BIT_VHT_DACK_8822C BIT(26) +#define BIT_TCPOFLD_EN_8822C BIT(25) +#define BIT_ENMBID_8822C BIT(24) +#define BIT_LSIGEN_8822C BIT(23) +#define BIT_MFBEN_8822C BIT(22) +#define BIT_DISCHKPPDLLEN_8822C BIT(21) +#define BIT_PKTCTL_DLEN_8822C BIT(20) +#define BIT_DISGCLK_8822C BIT(19) +#define BIT_TIM_PARSER_EN_8822C BIT(18) +#define BIT_BC_MD_EN_8822C BIT(17) +#define BIT_UC_MD_EN_8822C BIT(16) +#define BIT_RXSK_PERPKT_8822C BIT(15) +#define BIT_HTC_LOC_CTRL_8822C BIT(14) +#define BIT_ACK_WITH_CBSSID_DATA_OPTION_8822C BIT(13) +#define BIT_RPFM_CAM_ENABLE_8822C BIT(12) +#define BIT_TA_BCN_8822C BIT(11) +#define BIT_DISDECMYPKT_8822C BIT(10) +#define BIT_AICV_8822C BIT(9) +#define BIT_ACRC32_8822C BIT(8) +#define BIT_CBSSID_BCN_8822C BIT(7) +#define BIT_CBSSID_DATA_8822C BIT(6) +#define BIT_APWRMGT_8822C BIT(5) +#define BIT_ADD3_8822C BIT(4) +#define BIT_AB_8822C BIT(3) +#define BIT_AM_8822C BIT(2) +#define BIT_APM_8822C BIT(1) +#define BIT_AAP_8822C BIT(0) + +/* 2 REG_RX_PKT_LIMIT_8822C (RX PACKET LENGTH LIMIT REGISTER) */ + +#define BIT_SHIFT_RXPKTLMT_8822C 0 +#define BIT_MASK_RXPKTLMT_8822C 0x3f +#define BIT_RXPKTLMT_8822C(x) \ + (((x) & BIT_MASK_RXPKTLMT_8822C) << BIT_SHIFT_RXPKTLMT_8822C) +#define BITS_RXPKTLMT_8822C \ + (BIT_MASK_RXPKTLMT_8822C << BIT_SHIFT_RXPKTLMT_8822C) +#define BIT_CLEAR_RXPKTLMT_8822C(x) ((x) & (~BITS_RXPKTLMT_8822C)) +#define BIT_GET_RXPKTLMT_8822C(x) \ + (((x) >> BIT_SHIFT_RXPKTLMT_8822C) & BIT_MASK_RXPKTLMT_8822C) +#define BIT_SET_RXPKTLMT_8822C(x, v) \ + (BIT_CLEAR_RXPKTLMT_8822C(x) | BIT_RXPKTLMT_8822C(v)) + +/* 2 REG_RX_DLK_TIME_8822C (RX DEADLOCK TIME REGISTER) */ + +#define BIT_SHIFT_RX_DLK_TIME_8822C 0 +#define BIT_MASK_RX_DLK_TIME_8822C 0xff +#define BIT_RX_DLK_TIME_8822C(x) \ + (((x) & BIT_MASK_RX_DLK_TIME_8822C) << BIT_SHIFT_RX_DLK_TIME_8822C) +#define BITS_RX_DLK_TIME_8822C \ + (BIT_MASK_RX_DLK_TIME_8822C << BIT_SHIFT_RX_DLK_TIME_8822C) +#define BIT_CLEAR_RX_DLK_TIME_8822C(x) ((x) & (~BITS_RX_DLK_TIME_8822C)) +#define BIT_GET_RX_DLK_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_RX_DLK_TIME_8822C) & BIT_MASK_RX_DLK_TIME_8822C) +#define BIT_SET_RX_DLK_TIME_8822C(x, v) \ + (BIT_CLEAR_RX_DLK_TIME_8822C(x) | BIT_RX_DLK_TIME_8822C(v)) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RX_DRVINFO_SZ_8822C (RX DRIVER INFO SIZE REGISTER) */ +#define BIT_PHYSTS_PER_PKT_MODE_8822C BIT(7) + +#define BIT_SHIFT_DRVINFO_SZ_V1_8822C 0 +#define BIT_MASK_DRVINFO_SZ_V1_8822C 0xf +#define BIT_DRVINFO_SZ_V1_8822C(x) \ + (((x) & BIT_MASK_DRVINFO_SZ_V1_8822C) << BIT_SHIFT_DRVINFO_SZ_V1_8822C) +#define BITS_DRVINFO_SZ_V1_8822C \ + (BIT_MASK_DRVINFO_SZ_V1_8822C << BIT_SHIFT_DRVINFO_SZ_V1_8822C) +#define BIT_CLEAR_DRVINFO_SZ_V1_8822C(x) ((x) & (~BITS_DRVINFO_SZ_V1_8822C)) +#define BIT_GET_DRVINFO_SZ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822C) & BIT_MASK_DRVINFO_SZ_V1_8822C) +#define BIT_SET_DRVINFO_SZ_V1_8822C(x, v) \ + (BIT_CLEAR_DRVINFO_SZ_V1_8822C(x) | BIT_DRVINFO_SZ_V1_8822C(v)) + +/* 2 REG_MACID_8822C (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_V1_8822C 0 +#define BIT_MASK_MACID_V1_8822C 0xffffffffL +#define BIT_MACID_V1_8822C(x) \ + (((x) & BIT_MASK_MACID_V1_8822C) << BIT_SHIFT_MACID_V1_8822C) +#define BITS_MACID_V1_8822C \ + (BIT_MASK_MACID_V1_8822C << BIT_SHIFT_MACID_V1_8822C) +#define BIT_CLEAR_MACID_V1_8822C(x) ((x) & (~BITS_MACID_V1_8822C)) +#define BIT_GET_MACID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID_V1_8822C) & BIT_MASK_MACID_V1_8822C) +#define BIT_SET_MACID_V1_8822C(x, v) \ + (BIT_CLEAR_MACID_V1_8822C(x) | BIT_MACID_V1_8822C(v)) + +/* 2 REG_MACID_H_8822C (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_H_V1_8822C 0 +#define BIT_MASK_MACID_H_V1_8822C 0xffff +#define BIT_MACID_H_V1_8822C(x) \ + (((x) & BIT_MASK_MACID_H_V1_8822C) << BIT_SHIFT_MACID_H_V1_8822C) +#define BITS_MACID_H_V1_8822C \ + (BIT_MASK_MACID_H_V1_8822C << BIT_SHIFT_MACID_H_V1_8822C) +#define BIT_CLEAR_MACID_H_V1_8822C(x) ((x) & (~BITS_MACID_H_V1_8822C)) +#define BIT_GET_MACID_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID_H_V1_8822C) & BIT_MASK_MACID_H_V1_8822C) +#define BIT_SET_MACID_H_V1_8822C(x, v) \ + (BIT_CLEAR_MACID_H_V1_8822C(x) | BIT_MACID_H_V1_8822C(v)) + +/* 2 REG_BSSID_8822C (BSSID REGISTER) */ + +#define BIT_SHIFT_BSSID_V1_8822C 0 +#define BIT_MASK_BSSID_V1_8822C 0xffffffffL +#define BIT_BSSID_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID_V1_8822C) << BIT_SHIFT_BSSID_V1_8822C) +#define BITS_BSSID_V1_8822C \ + (BIT_MASK_BSSID_V1_8822C << BIT_SHIFT_BSSID_V1_8822C) +#define BIT_CLEAR_BSSID_V1_8822C(x) ((x) & (~BITS_BSSID_V1_8822C)) +#define BIT_GET_BSSID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID_V1_8822C) & BIT_MASK_BSSID_V1_8822C) +#define BIT_SET_BSSID_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID_V1_8822C(x) | BIT_BSSID_V1_8822C(v)) + +/* 2 REG_BSSID_H_8822C (BSSID REGISTER) */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_BSSID_H_V1_8822C 0 +#define BIT_MASK_BSSID_H_V1_8822C 0xffff +#define BIT_BSSID_H_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID_H_V1_8822C) << BIT_SHIFT_BSSID_H_V1_8822C) +#define BITS_BSSID_H_V1_8822C \ + (BIT_MASK_BSSID_H_V1_8822C << BIT_SHIFT_BSSID_H_V1_8822C) +#define BIT_CLEAR_BSSID_H_V1_8822C(x) ((x) & (~BITS_BSSID_H_V1_8822C)) +#define BIT_GET_BSSID_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID_H_V1_8822C) & BIT_MASK_BSSID_H_V1_8822C) +#define BIT_SET_BSSID_H_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID_H_V1_8822C(x) | BIT_BSSID_H_V1_8822C(v)) + +/* 2 REG_MAR_8822C (MULTICAST ADDRESS REGISTER) */ + +#define BIT_SHIFT_MAR_V1_8822C 0 +#define BIT_MASK_MAR_V1_8822C 0xffffffffL +#define BIT_MAR_V1_8822C(x) \ + (((x) & BIT_MASK_MAR_V1_8822C) << BIT_SHIFT_MAR_V1_8822C) +#define BITS_MAR_V1_8822C (BIT_MASK_MAR_V1_8822C << BIT_SHIFT_MAR_V1_8822C) +#define BIT_CLEAR_MAR_V1_8822C(x) ((x) & (~BITS_MAR_V1_8822C)) +#define BIT_GET_MAR_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MAR_V1_8822C) & BIT_MASK_MAR_V1_8822C) +#define BIT_SET_MAR_V1_8822C(x, v) \ + (BIT_CLEAR_MAR_V1_8822C(x) | BIT_MAR_V1_8822C(v)) + +/* 2 REG_MAR_H_8822C (MULTICAST ADDRESS REGISTER) */ + +#define BIT_SHIFT_MAR_H_V1_8822C 0 +#define BIT_MASK_MAR_H_V1_8822C 0xffffffffL +#define BIT_MAR_H_V1_8822C(x) \ + (((x) & BIT_MASK_MAR_H_V1_8822C) << BIT_SHIFT_MAR_H_V1_8822C) +#define BITS_MAR_H_V1_8822C \ + (BIT_MASK_MAR_H_V1_8822C << BIT_SHIFT_MAR_H_V1_8822C) +#define BIT_CLEAR_MAR_H_V1_8822C(x) ((x) & (~BITS_MAR_H_V1_8822C)) +#define BIT_GET_MAR_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MAR_H_V1_8822C) & BIT_MASK_MAR_H_V1_8822C) +#define BIT_SET_MAR_H_V1_8822C(x, v) \ + (BIT_CLEAR_MAR_H_V1_8822C(x) | BIT_MAR_H_V1_8822C(v)) + +/* 2 REG_MBIDCAMCFG_1_8822C (MBSSID CAM CONFIGURATION REGISTER) */ + +#define BIT_SHIFT_MBIDCAM_RWDATA_L_8822C 0 +#define BIT_MASK_MBIDCAM_RWDATA_L_8822C 0xffffffffL +#define BIT_MBIDCAM_RWDATA_L_8822C(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822C) \ + << BIT_SHIFT_MBIDCAM_RWDATA_L_8822C) +#define BITS_MBIDCAM_RWDATA_L_8822C \ + (BIT_MASK_MBIDCAM_RWDATA_L_8822C << BIT_SHIFT_MBIDCAM_RWDATA_L_8822C) +#define BIT_CLEAR_MBIDCAM_RWDATA_L_8822C(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_L_8822C)) +#define BIT_GET_MBIDCAM_RWDATA_L_8822C(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822C) & \ + BIT_MASK_MBIDCAM_RWDATA_L_8822C) +#define BIT_SET_MBIDCAM_RWDATA_L_8822C(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_L_8822C(x) | BIT_MBIDCAM_RWDATA_L_8822C(v)) + +/* 2 REG_MBIDCAMCFG_2_8822C (MBSSID CAM CONFIGURATION REGISTER) */ +#define BIT_MBIDCAM_POLL_8822C BIT(31) +#define BIT_MBIDCAM_WT_EN_8822C BIT(30) + +#define BIT_SHIFT_MBIDCAM_ADDR_V1_8822C 24 +#define BIT_MASK_MBIDCAM_ADDR_V1_8822C 0x3f +#define BIT_MBIDCAM_ADDR_V1_8822C(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR_V1_8822C) \ + << BIT_SHIFT_MBIDCAM_ADDR_V1_8822C) +#define BITS_MBIDCAM_ADDR_V1_8822C \ + (BIT_MASK_MBIDCAM_ADDR_V1_8822C << BIT_SHIFT_MBIDCAM_ADDR_V1_8822C) +#define BIT_CLEAR_MBIDCAM_ADDR_V1_8822C(x) ((x) & (~BITS_MBIDCAM_ADDR_V1_8822C)) +#define BIT_GET_MBIDCAM_ADDR_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1_8822C) & \ + BIT_MASK_MBIDCAM_ADDR_V1_8822C) +#define BIT_SET_MBIDCAM_ADDR_V1_8822C(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR_V1_8822C(x) | BIT_MBIDCAM_ADDR_V1_8822C(v)) + +#define BIT_MBIDCAM_VALID_8822C BIT(23) +#define BIT_LSIC_TXOP_EN_8822C BIT(17) +#define BIT_CTS_EN_8822C BIT(16) + +#define BIT_SHIFT_MBIDCAM_RWDATA_H_8822C 0 +#define BIT_MASK_MBIDCAM_RWDATA_H_8822C 0xffff +#define BIT_MBIDCAM_RWDATA_H_8822C(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822C) \ + << BIT_SHIFT_MBIDCAM_RWDATA_H_8822C) +#define BITS_MBIDCAM_RWDATA_H_8822C \ + (BIT_MASK_MBIDCAM_RWDATA_H_8822C << BIT_SHIFT_MBIDCAM_RWDATA_H_8822C) +#define BIT_CLEAR_MBIDCAM_RWDATA_H_8822C(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_H_8822C)) +#define BIT_GET_MBIDCAM_RWDATA_H_8822C(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822C) & \ + BIT_MASK_MBIDCAM_RWDATA_H_8822C) +#define BIT_SET_MBIDCAM_RWDATA_H_8822C(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_H_8822C(x) | BIT_MBIDCAM_RWDATA_H_8822C(v)) + +/* 2 REG_WMAC_TCR_TSFT_OFS_8822C */ + +#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C 0 +#define BIT_MASK_WMAC_TCR_TSFT_OFS_8822C 0xffff +#define BIT_WMAC_TCR_TSFT_OFS_8822C(x) \ + (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822C) \ + << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C) +#define BITS_WMAC_TCR_TSFT_OFS_8822C \ + (BIT_MASK_WMAC_TCR_TSFT_OFS_8822C << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822C(x) \ + ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8822C)) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C) & \ + BIT_MASK_WMAC_TCR_TSFT_OFS_8822C) +#define BIT_SET_WMAC_TCR_TSFT_OFS_8822C(x, v) \ + (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822C(x) | BIT_WMAC_TCR_TSFT_OFS_8822C(v)) + +/* 2 REG_UDF_THSD_8822C */ +#define BIT_UDF_THSD_V1_8822C BIT(7) + +#define BIT_SHIFT_UDF_THSD_VALUE_8822C 0 +#define BIT_MASK_UDF_THSD_VALUE_8822C 0x7f +#define BIT_UDF_THSD_VALUE_8822C(x) \ + (((x) & BIT_MASK_UDF_THSD_VALUE_8822C) \ + << BIT_SHIFT_UDF_THSD_VALUE_8822C) +#define BITS_UDF_THSD_VALUE_8822C \ + (BIT_MASK_UDF_THSD_VALUE_8822C << BIT_SHIFT_UDF_THSD_VALUE_8822C) +#define BIT_CLEAR_UDF_THSD_VALUE_8822C(x) ((x) & (~BITS_UDF_THSD_VALUE_8822C)) +#define BIT_GET_UDF_THSD_VALUE_8822C(x) \ + (((x) >> BIT_SHIFT_UDF_THSD_VALUE_8822C) & \ + BIT_MASK_UDF_THSD_VALUE_8822C) +#define BIT_SET_UDF_THSD_VALUE_8822C(x, v) \ + (BIT_CLEAR_UDF_THSD_VALUE_8822C(x) | BIT_UDF_THSD_VALUE_8822C(v)) + +/* 2 REG_ZLD_NUM_8822C */ + +#define BIT_SHIFT_ZLD_NUM_8822C 0 +#define BIT_MASK_ZLD_NUM_8822C 0xff +#define BIT_ZLD_NUM_8822C(x) \ + (((x) & BIT_MASK_ZLD_NUM_8822C) << BIT_SHIFT_ZLD_NUM_8822C) +#define BITS_ZLD_NUM_8822C (BIT_MASK_ZLD_NUM_8822C << BIT_SHIFT_ZLD_NUM_8822C) +#define BIT_CLEAR_ZLD_NUM_8822C(x) ((x) & (~BITS_ZLD_NUM_8822C)) +#define BIT_GET_ZLD_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_ZLD_NUM_8822C) & BIT_MASK_ZLD_NUM_8822C) +#define BIT_SET_ZLD_NUM_8822C(x, v) \ + (BIT_CLEAR_ZLD_NUM_8822C(x) | BIT_ZLD_NUM_8822C(v)) + +/* 2 REG_STMP_THSD_8822C */ + +#define BIT_SHIFT_STMP_THSD_8822C 0 +#define BIT_MASK_STMP_THSD_8822C 0xff +#define BIT_STMP_THSD_8822C(x) \ + (((x) & BIT_MASK_STMP_THSD_8822C) << BIT_SHIFT_STMP_THSD_8822C) +#define BITS_STMP_THSD_8822C \ + (BIT_MASK_STMP_THSD_8822C << BIT_SHIFT_STMP_THSD_8822C) +#define BIT_CLEAR_STMP_THSD_8822C(x) ((x) & (~BITS_STMP_THSD_8822C)) +#define BIT_GET_STMP_THSD_8822C(x) \ + (((x) >> BIT_SHIFT_STMP_THSD_8822C) & BIT_MASK_STMP_THSD_8822C) +#define BIT_SET_STMP_THSD_8822C(x, v) \ + (BIT_CLEAR_STMP_THSD_8822C(x) | BIT_STMP_THSD_8822C(v)) + +/* 2 REG_WMAC_TXTIMEOUT_8822C */ + +#define BIT_SHIFT_WMAC_TXTIMEOUT_8822C 0 +#define BIT_MASK_WMAC_TXTIMEOUT_8822C 0xff +#define BIT_WMAC_TXTIMEOUT_8822C(x) \ + (((x) & BIT_MASK_WMAC_TXTIMEOUT_8822C) \ + << BIT_SHIFT_WMAC_TXTIMEOUT_8822C) +#define BITS_WMAC_TXTIMEOUT_8822C \ + (BIT_MASK_WMAC_TXTIMEOUT_8822C << BIT_SHIFT_WMAC_TXTIMEOUT_8822C) +#define BIT_CLEAR_WMAC_TXTIMEOUT_8822C(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8822C)) +#define BIT_GET_WMAC_TXTIMEOUT_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822C) & \ + BIT_MASK_WMAC_TXTIMEOUT_8822C) +#define BIT_SET_WMAC_TXTIMEOUT_8822C(x, v) \ + (BIT_CLEAR_WMAC_TXTIMEOUT_8822C(x) | BIT_WMAC_TXTIMEOUT_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_USTIME_EDCA_8822C (US TIME TUNING FOR EDCA REGISTER) */ + +#define BIT_SHIFT_USTIME_EDCA_8822C 0 +#define BIT_MASK_USTIME_EDCA_8822C 0xff +#define BIT_USTIME_EDCA_8822C(x) \ + (((x) & BIT_MASK_USTIME_EDCA_8822C) << BIT_SHIFT_USTIME_EDCA_8822C) +#define BITS_USTIME_EDCA_8822C \ + (BIT_MASK_USTIME_EDCA_8822C << BIT_SHIFT_USTIME_EDCA_8822C) +#define BIT_CLEAR_USTIME_EDCA_8822C(x) ((x) & (~BITS_USTIME_EDCA_8822C)) +#define BIT_GET_USTIME_EDCA_8822C(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA_8822C) & BIT_MASK_USTIME_EDCA_8822C) +#define BIT_SET_USTIME_EDCA_8822C(x, v) \ + (BIT_CLEAR_USTIME_EDCA_8822C(x) | BIT_USTIME_EDCA_8822C(v)) + +/* 2 REG_ACKTO_CCK_8822C (ACK TIMEOUT REGISTER FOR CCK RATE) */ + +#define BIT_SHIFT_ACKTO_CCK_8822C 0 +#define BIT_MASK_ACKTO_CCK_8822C 0xff +#define BIT_ACKTO_CCK_8822C(x) \ + (((x) & BIT_MASK_ACKTO_CCK_8822C) << BIT_SHIFT_ACKTO_CCK_8822C) +#define BITS_ACKTO_CCK_8822C \ + (BIT_MASK_ACKTO_CCK_8822C << BIT_SHIFT_ACKTO_CCK_8822C) +#define BIT_CLEAR_ACKTO_CCK_8822C(x) ((x) & (~BITS_ACKTO_CCK_8822C)) +#define BIT_GET_ACKTO_CCK_8822C(x) \ + (((x) >> BIT_SHIFT_ACKTO_CCK_8822C) & BIT_MASK_ACKTO_CCK_8822C) +#define BIT_SET_ACKTO_CCK_8822C(x, v) \ + (BIT_CLEAR_ACKTO_CCK_8822C(x) | BIT_ACKTO_CCK_8822C(v)) + +/* 2 REG_MAC_SPEC_SIFS_8822C (SPECIFICATION SIFS REGISTER) */ + +#define BIT_SHIFT_SPEC_SIFS_OFDM_8822C 8 +#define BIT_MASK_SPEC_SIFS_OFDM_8822C 0xff +#define BIT_SPEC_SIFS_OFDM_8822C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_8822C) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_8822C) +#define BITS_SPEC_SIFS_OFDM_8822C \ + (BIT_MASK_SPEC_SIFS_OFDM_8822C << BIT_SHIFT_SPEC_SIFS_OFDM_8822C) +#define BIT_CLEAR_SPEC_SIFS_OFDM_8822C(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8822C)) +#define BIT_GET_SPEC_SIFS_OFDM_8822C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822C) & \ + BIT_MASK_SPEC_SIFS_OFDM_8822C) +#define BIT_SET_SPEC_SIFS_OFDM_8822C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_8822C(x) | BIT_SPEC_SIFS_OFDM_8822C(v)) + +#define BIT_SHIFT_SPEC_SIFS_CCK_8822C 0 +#define BIT_MASK_SPEC_SIFS_CCK_8822C 0xff +#define BIT_SPEC_SIFS_CCK_8822C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_8822C) << BIT_SHIFT_SPEC_SIFS_CCK_8822C) +#define BITS_SPEC_SIFS_CCK_8822C \ + (BIT_MASK_SPEC_SIFS_CCK_8822C << BIT_SHIFT_SPEC_SIFS_CCK_8822C) +#define BIT_CLEAR_SPEC_SIFS_CCK_8822C(x) ((x) & (~BITS_SPEC_SIFS_CCK_8822C)) +#define BIT_GET_SPEC_SIFS_CCK_8822C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822C) & BIT_MASK_SPEC_SIFS_CCK_8822C) +#define BIT_SET_SPEC_SIFS_CCK_8822C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_8822C(x) | BIT_SPEC_SIFS_CCK_8822C(v)) + +/* 2 REG_RESP_SIFS_CCK_8822C (RESPONSE SIFS FOR CCK REGISTER) */ + +#define BIT_SHIFT_SIFS_R2T_CCK_8822C 8 +#define BIT_MASK_SIFS_R2T_CCK_8822C 0xff +#define BIT_SIFS_R2T_CCK_8822C(x) \ + (((x) & BIT_MASK_SIFS_R2T_CCK_8822C) << BIT_SHIFT_SIFS_R2T_CCK_8822C) +#define BITS_SIFS_R2T_CCK_8822C \ + (BIT_MASK_SIFS_R2T_CCK_8822C << BIT_SHIFT_SIFS_R2T_CCK_8822C) +#define BIT_CLEAR_SIFS_R2T_CCK_8822C(x) ((x) & (~BITS_SIFS_R2T_CCK_8822C)) +#define BIT_GET_SIFS_R2T_CCK_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822C) & BIT_MASK_SIFS_R2T_CCK_8822C) +#define BIT_SET_SIFS_R2T_CCK_8822C(x, v) \ + (BIT_CLEAR_SIFS_R2T_CCK_8822C(x) | BIT_SIFS_R2T_CCK_8822C(v)) + +#define BIT_SHIFT_SIFS_T2T_CCK_8822C 0 +#define BIT_MASK_SIFS_T2T_CCK_8822C 0xff +#define BIT_SIFS_T2T_CCK_8822C(x) \ + (((x) & BIT_MASK_SIFS_T2T_CCK_8822C) << BIT_SHIFT_SIFS_T2T_CCK_8822C) +#define BITS_SIFS_T2T_CCK_8822C \ + (BIT_MASK_SIFS_T2T_CCK_8822C << BIT_SHIFT_SIFS_T2T_CCK_8822C) +#define BIT_CLEAR_SIFS_T2T_CCK_8822C(x) ((x) & (~BITS_SIFS_T2T_CCK_8822C)) +#define BIT_GET_SIFS_T2T_CCK_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822C) & BIT_MASK_SIFS_T2T_CCK_8822C) +#define BIT_SET_SIFS_T2T_CCK_8822C(x, v) \ + (BIT_CLEAR_SIFS_T2T_CCK_8822C(x) | BIT_SIFS_T2T_CCK_8822C(v)) + +/* 2 REG_RESP_SIFS_OFDM_8822C (RESPONSE SIFS FOR OFDM REGISTER) */ + +#define BIT_SHIFT_SIFS_R2T_OFDM_8822C 8 +#define BIT_MASK_SIFS_R2T_OFDM_8822C 0xff +#define BIT_SIFS_R2T_OFDM_8822C(x) \ + (((x) & BIT_MASK_SIFS_R2T_OFDM_8822C) << BIT_SHIFT_SIFS_R2T_OFDM_8822C) +#define BITS_SIFS_R2T_OFDM_8822C \ + (BIT_MASK_SIFS_R2T_OFDM_8822C << BIT_SHIFT_SIFS_R2T_OFDM_8822C) +#define BIT_CLEAR_SIFS_R2T_OFDM_8822C(x) ((x) & (~BITS_SIFS_R2T_OFDM_8822C)) +#define BIT_GET_SIFS_R2T_OFDM_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822C) & BIT_MASK_SIFS_R2T_OFDM_8822C) +#define BIT_SET_SIFS_R2T_OFDM_8822C(x, v) \ + (BIT_CLEAR_SIFS_R2T_OFDM_8822C(x) | BIT_SIFS_R2T_OFDM_8822C(v)) + +#define BIT_SHIFT_SIFS_T2T_OFDM_8822C 0 +#define BIT_MASK_SIFS_T2T_OFDM_8822C 0xff +#define BIT_SIFS_T2T_OFDM_8822C(x) \ + (((x) & BIT_MASK_SIFS_T2T_OFDM_8822C) << BIT_SHIFT_SIFS_T2T_OFDM_8822C) +#define BITS_SIFS_T2T_OFDM_8822C \ + (BIT_MASK_SIFS_T2T_OFDM_8822C << BIT_SHIFT_SIFS_T2T_OFDM_8822C) +#define BIT_CLEAR_SIFS_T2T_OFDM_8822C(x) ((x) & (~BITS_SIFS_T2T_OFDM_8822C)) +#define BIT_GET_SIFS_T2T_OFDM_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822C) & BIT_MASK_SIFS_T2T_OFDM_8822C) +#define BIT_SET_SIFS_T2T_OFDM_8822C(x, v) \ + (BIT_CLEAR_SIFS_T2T_OFDM_8822C(x) | BIT_SIFS_T2T_OFDM_8822C(v)) + +/* 2 REG_ACKTO_8822C (ACK TIMEOUT REGISTER) */ + +#define BIT_SHIFT_ACKTO_8822C 0 +#define BIT_MASK_ACKTO_8822C 0xff +#define BIT_ACKTO_8822C(x) \ + (((x) & BIT_MASK_ACKTO_8822C) << BIT_SHIFT_ACKTO_8822C) +#define BITS_ACKTO_8822C (BIT_MASK_ACKTO_8822C << BIT_SHIFT_ACKTO_8822C) +#define BIT_CLEAR_ACKTO_8822C(x) ((x) & (~BITS_ACKTO_8822C)) +#define BIT_GET_ACKTO_8822C(x) \ + (((x) >> BIT_SHIFT_ACKTO_8822C) & BIT_MASK_ACKTO_8822C) +#define BIT_SET_ACKTO_8822C(x, v) \ + (BIT_CLEAR_ACKTO_8822C(x) | BIT_ACKTO_8822C(v)) + +/* 2 REG_CTS2TO_8822C (CTS2 TIMEOUT REGISTER) */ + +#define BIT_SHIFT_CTS2TO_8822C 0 +#define BIT_MASK_CTS2TO_8822C 0xff +#define BIT_CTS2TO_8822C(x) \ + (((x) & BIT_MASK_CTS2TO_8822C) << BIT_SHIFT_CTS2TO_8822C) +#define BITS_CTS2TO_8822C (BIT_MASK_CTS2TO_8822C << BIT_SHIFT_CTS2TO_8822C) +#define BIT_CLEAR_CTS2TO_8822C(x) ((x) & (~BITS_CTS2TO_8822C)) +#define BIT_GET_CTS2TO_8822C(x) \ + (((x) >> BIT_SHIFT_CTS2TO_8822C) & BIT_MASK_CTS2TO_8822C) +#define BIT_SET_CTS2TO_8822C(x, v) \ + (BIT_CLEAR_CTS2TO_8822C(x) | BIT_CTS2TO_8822C(v)) + +/* 2 REG_EIFS_8822C (EIFS REGISTER) */ + +#define BIT_SHIFT_EIFS_8822C 0 +#define BIT_MASK_EIFS_8822C 0xffff +#define BIT_EIFS_8822C(x) (((x) & BIT_MASK_EIFS_8822C) << BIT_SHIFT_EIFS_8822C) +#define BITS_EIFS_8822C (BIT_MASK_EIFS_8822C << BIT_SHIFT_EIFS_8822C) +#define BIT_CLEAR_EIFS_8822C(x) ((x) & (~BITS_EIFS_8822C)) +#define BIT_GET_EIFS_8822C(x) \ + (((x) >> BIT_SHIFT_EIFS_8822C) & BIT_MASK_EIFS_8822C) +#define BIT_SET_EIFS_8822C(x, v) (BIT_CLEAR_EIFS_8822C(x) | BIT_EIFS_8822C(v)) + +/* 2 REG_RPFM_MAP0_8822C */ +#define BIT_MGT_RPFM15EN_8822C BIT(15) +#define BIT_MGT_RPFM14EN_8822C BIT(14) +#define BIT_MGT_RPFM13EN_8822C BIT(13) +#define BIT_MGT_RPFM12EN_8822C BIT(12) +#define BIT_MGT_RPFM11EN_8822C BIT(11) +#define BIT_MGT_RPFM10EN_8822C BIT(10) +#define BIT_MGT_RPFM9EN_8822C BIT(9) +#define BIT_MGT_RPFM8EN_8822C BIT(8) +#define BIT_MGT_RPFM7EN_8822C BIT(7) +#define BIT_MGT_RPFM6EN_8822C BIT(6) +#define BIT_MGT_RPFM5EN_8822C BIT(5) +#define BIT_MGT_RPFM4EN_8822C BIT(4) +#define BIT_MGT_RPFM3EN_8822C BIT(3) +#define BIT_MGT_RPFM2EN_8822C BIT(2) +#define BIT_MGT_RPFM1EN_8822C BIT(1) +#define BIT_MGT_RPFM0EN_8822C BIT(0) + +/* 2 REG_RPFM_MAP1_V1_8822C */ +#define BIT_DATA_RPFM15EN_8822C BIT(15) +#define BIT_DATA_RPFM14EN_8822C BIT(14) +#define BIT_DATA_RPFM13EN_8822C BIT(13) +#define BIT_DATA_RPFM12EN_8822C BIT(12) +#define BIT_DATA_RPFM11EN_8822C BIT(11) +#define BIT_DATA_RPFM10EN_8822C BIT(10) +#define BIT_DATA_RPFM9EN_8822C BIT(9) +#define BIT_DATA_RPFM8EN_8822C BIT(8) +#define BIT_DATA_RPFM7EN_8822C BIT(7) +#define BIT_DATA_RPFM6EN_8822C BIT(6) +#define BIT_DATA_RPFM5EN_8822C BIT(5) +#define BIT_DATA_RPFM4EN_8822C BIT(4) +#define BIT_DATA_RPFM3EN_8822C BIT(3) +#define BIT_DATA_RPFM2EN_8822C BIT(2) +#define BIT_DATA_RPFM1EN_8822C BIT(1) +#define BIT_DATA_RPFM0EN_8822C BIT(0) + +/* 2 REG_RPFM_CAM_CMD_8822C (RX PAYLOAD FRAME MASK CAM COMMAND REGISTER) */ +#define BIT_RPFM_CAM_POLLING_8822C BIT(31) +#define BIT_RPFM_CAM_CLR_8822C BIT(30) +#define BIT_RPFM_CAM_WE_8822C BIT(16) + +#define BIT_SHIFT_RPFM_CAM_ADDR_8822C 0 +#define BIT_MASK_RPFM_CAM_ADDR_8822C 0x7f +#define BIT_RPFM_CAM_ADDR_8822C(x) \ + (((x) & BIT_MASK_RPFM_CAM_ADDR_8822C) << BIT_SHIFT_RPFM_CAM_ADDR_8822C) +#define BITS_RPFM_CAM_ADDR_8822C \ + (BIT_MASK_RPFM_CAM_ADDR_8822C << BIT_SHIFT_RPFM_CAM_ADDR_8822C) +#define BIT_CLEAR_RPFM_CAM_ADDR_8822C(x) ((x) & (~BITS_RPFM_CAM_ADDR_8822C)) +#define BIT_GET_RPFM_CAM_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8822C) & BIT_MASK_RPFM_CAM_ADDR_8822C) +#define BIT_SET_RPFM_CAM_ADDR_8822C(x, v) \ + (BIT_CLEAR_RPFM_CAM_ADDR_8822C(x) | BIT_RPFM_CAM_ADDR_8822C(v)) + +/* 2 REG_RPFM_CAM_RWD_8822C (ACK TIMEOUT REGISTER) */ + +#define BIT_SHIFT_RPFM_CAM_RWD_8822C 0 +#define BIT_MASK_RPFM_CAM_RWD_8822C 0xffffffffL +#define BIT_RPFM_CAM_RWD_8822C(x) \ + (((x) & BIT_MASK_RPFM_CAM_RWD_8822C) << BIT_SHIFT_RPFM_CAM_RWD_8822C) +#define BITS_RPFM_CAM_RWD_8822C \ + (BIT_MASK_RPFM_CAM_RWD_8822C << BIT_SHIFT_RPFM_CAM_RWD_8822C) +#define BIT_CLEAR_RPFM_CAM_RWD_8822C(x) ((x) & (~BITS_RPFM_CAM_RWD_8822C)) +#define BIT_GET_RPFM_CAM_RWD_8822C(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8822C) & BIT_MASK_RPFM_CAM_RWD_8822C) +#define BIT_SET_RPFM_CAM_RWD_8822C(x, v) \ + (BIT_CLEAR_RPFM_CAM_RWD_8822C(x) | BIT_RPFM_CAM_RWD_8822C(v)) + +/* 2 REG_NAV_CTRL_8822C (NAV CONTROL REGISTER) */ + +#define BIT_SHIFT_NAV_UPPER_8822C 16 +#define BIT_MASK_NAV_UPPER_8822C 0xff +#define BIT_NAV_UPPER_8822C(x) \ + (((x) & BIT_MASK_NAV_UPPER_8822C) << BIT_SHIFT_NAV_UPPER_8822C) +#define BITS_NAV_UPPER_8822C \ + (BIT_MASK_NAV_UPPER_8822C << BIT_SHIFT_NAV_UPPER_8822C) +#define BIT_CLEAR_NAV_UPPER_8822C(x) ((x) & (~BITS_NAV_UPPER_8822C)) +#define BIT_GET_NAV_UPPER_8822C(x) \ + (((x) >> BIT_SHIFT_NAV_UPPER_8822C) & BIT_MASK_NAV_UPPER_8822C) +#define BIT_SET_NAV_UPPER_8822C(x, v) \ + (BIT_CLEAR_NAV_UPPER_8822C(x) | BIT_NAV_UPPER_8822C(v)) + +#define BIT_SHIFT_RXMYRTS_NAV_8822C 8 +#define BIT_MASK_RXMYRTS_NAV_8822C 0xf +#define BIT_RXMYRTS_NAV_8822C(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_8822C) << BIT_SHIFT_RXMYRTS_NAV_8822C) +#define BITS_RXMYRTS_NAV_8822C \ + (BIT_MASK_RXMYRTS_NAV_8822C << BIT_SHIFT_RXMYRTS_NAV_8822C) +#define BIT_CLEAR_RXMYRTS_NAV_8822C(x) ((x) & (~BITS_RXMYRTS_NAV_8822C)) +#define BIT_GET_RXMYRTS_NAV_8822C(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_8822C) & BIT_MASK_RXMYRTS_NAV_8822C) +#define BIT_SET_RXMYRTS_NAV_8822C(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_8822C(x) | BIT_RXMYRTS_NAV_8822C(v)) + +#define BIT_SHIFT_RTSRST_8822C 0 +#define BIT_MASK_RTSRST_8822C 0xff +#define BIT_RTSRST_8822C(x) \ + (((x) & BIT_MASK_RTSRST_8822C) << BIT_SHIFT_RTSRST_8822C) +#define BITS_RTSRST_8822C (BIT_MASK_RTSRST_8822C << BIT_SHIFT_RTSRST_8822C) +#define BIT_CLEAR_RTSRST_8822C(x) ((x) & (~BITS_RTSRST_8822C)) +#define BIT_GET_RTSRST_8822C(x) \ + (((x) >> BIT_SHIFT_RTSRST_8822C) & BIT_MASK_RTSRST_8822C) +#define BIT_SET_RTSRST_8822C(x, v) \ + (BIT_CLEAR_RTSRST_8822C(x) | BIT_RTSRST_8822C(v)) + +/* 2 REG_BACAMCMD_8822C (BLOCK ACK CAM COMMAND REGISTER) */ +#define BIT_BACAM_POLL_8822C BIT(31) +#define BIT_BACAM_RST_8822C BIT(17) +#define BIT_BACAM_RW_8822C BIT(16) + +#define BIT_SHIFT_TXSBM_8822C 14 +#define BIT_MASK_TXSBM_8822C 0x3 +#define BIT_TXSBM_8822C(x) \ + (((x) & BIT_MASK_TXSBM_8822C) << BIT_SHIFT_TXSBM_8822C) +#define BITS_TXSBM_8822C (BIT_MASK_TXSBM_8822C << BIT_SHIFT_TXSBM_8822C) +#define BIT_CLEAR_TXSBM_8822C(x) ((x) & (~BITS_TXSBM_8822C)) +#define BIT_GET_TXSBM_8822C(x) \ + (((x) >> BIT_SHIFT_TXSBM_8822C) & BIT_MASK_TXSBM_8822C) +#define BIT_SET_TXSBM_8822C(x, v) \ + (BIT_CLEAR_TXSBM_8822C(x) | BIT_TXSBM_8822C(v)) + +#define BIT_SHIFT_BACAM_ADDR_8822C 0 +#define BIT_MASK_BACAM_ADDR_8822C 0x3f +#define BIT_BACAM_ADDR_8822C(x) \ + (((x) & BIT_MASK_BACAM_ADDR_8822C) << BIT_SHIFT_BACAM_ADDR_8822C) +#define BITS_BACAM_ADDR_8822C \ + (BIT_MASK_BACAM_ADDR_8822C << BIT_SHIFT_BACAM_ADDR_8822C) +#define BIT_CLEAR_BACAM_ADDR_8822C(x) ((x) & (~BITS_BACAM_ADDR_8822C)) +#define BIT_GET_BACAM_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_BACAM_ADDR_8822C) & BIT_MASK_BACAM_ADDR_8822C) +#define BIT_SET_BACAM_ADDR_8822C(x, v) \ + (BIT_CLEAR_BACAM_ADDR_8822C(x) | BIT_BACAM_ADDR_8822C(v)) + +/* 2 REG_BACAMCONTENT_8822C (BLOCK ACK CAM CONTENT REGISTER) */ + +#define BIT_SHIFT_BA_CONTENT_L_8822C 0 +#define BIT_MASK_BA_CONTENT_L_8822C 0xffffffffL +#define BIT_BA_CONTENT_L_8822C(x) \ + (((x) & BIT_MASK_BA_CONTENT_L_8822C) << BIT_SHIFT_BA_CONTENT_L_8822C) +#define BITS_BA_CONTENT_L_8822C \ + (BIT_MASK_BA_CONTENT_L_8822C << BIT_SHIFT_BA_CONTENT_L_8822C) +#define BIT_CLEAR_BA_CONTENT_L_8822C(x) ((x) & (~BITS_BA_CONTENT_L_8822C)) +#define BIT_GET_BA_CONTENT_L_8822C(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_L_8822C) & BIT_MASK_BA_CONTENT_L_8822C) +#define BIT_SET_BA_CONTENT_L_8822C(x, v) \ + (BIT_CLEAR_BA_CONTENT_L_8822C(x) | BIT_BA_CONTENT_L_8822C(v)) + +/* 2 REG_BACAMCONTENT_H_8822C (BLOCK ACK CAM CONTENT REGISTER) */ + +#define BIT_SHIFT_BA_CONTENT_H_8822C 0 +#define BIT_MASK_BA_CONTENT_H_8822C 0xffffffffL +#define BIT_BA_CONTENT_H_8822C(x) \ + (((x) & BIT_MASK_BA_CONTENT_H_8822C) << BIT_SHIFT_BA_CONTENT_H_8822C) +#define BITS_BA_CONTENT_H_8822C \ + (BIT_MASK_BA_CONTENT_H_8822C << BIT_SHIFT_BA_CONTENT_H_8822C) +#define BIT_CLEAR_BA_CONTENT_H_8822C(x) ((x) & (~BITS_BA_CONTENT_H_8822C)) +#define BIT_GET_BA_CONTENT_H_8822C(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_H_8822C) & BIT_MASK_BA_CONTENT_H_8822C) +#define BIT_SET_BA_CONTENT_H_8822C(x, v) \ + (BIT_CLEAR_BA_CONTENT_H_8822C(x) | BIT_BA_CONTENT_H_8822C(v)) + +/* 2 REG_LBDLY_8822C (LOOPBACK DELAY REGISTER) */ + +#define BIT_SHIFT_LBDLY_8822C 0 +#define BIT_MASK_LBDLY_8822C 0x1f +#define BIT_LBDLY_8822C(x) \ + (((x) & BIT_MASK_LBDLY_8822C) << BIT_SHIFT_LBDLY_8822C) +#define BITS_LBDLY_8822C (BIT_MASK_LBDLY_8822C << BIT_SHIFT_LBDLY_8822C) +#define BIT_CLEAR_LBDLY_8822C(x) ((x) & (~BITS_LBDLY_8822C)) +#define BIT_GET_LBDLY_8822C(x) \ + (((x) >> BIT_SHIFT_LBDLY_8822C) & BIT_MASK_LBDLY_8822C) +#define BIT_SET_LBDLY_8822C(x, v) \ + (BIT_CLEAR_LBDLY_8822C(x) | BIT_LBDLY_8822C(v)) + +/* 2 REG_WMAC_BACAM_RPMEN_8822C */ + +#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C 2 +#define BIT_MASK_BITMAP_SSNBK_COUNTER_8822C 0x3f +#define BIT_BITMAP_SSNBK_COUNTER_8822C(x) \ + (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822C) \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C) +#define BITS_BITMAP_SSNBK_COUNTER_8822C \ + (BIT_MASK_BITMAP_SSNBK_COUNTER_8822C \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822C(x) \ + ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8822C)) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8822C(x) \ + (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C) & \ + BIT_MASK_BITMAP_SSNBK_COUNTER_8822C) +#define BIT_SET_BITMAP_SSNBK_COUNTER_8822C(x, v) \ + (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822C(x) | \ + BIT_BITMAP_SSNBK_COUNTER_8822C(v)) + +#define BIT_BITMAP_EN_8822C BIT(1) +#define BIT_WMAC_BACAM_RPMEN_8822C BIT(0) + +/* 2 REG_TX_RX_8822C STATUS */ + +#define BIT_SHIFT_RXPKT_TYPE_8822C 2 +#define BIT_MASK_RXPKT_TYPE_8822C 0x3f +#define BIT_RXPKT_TYPE_8822C(x) \ + (((x) & BIT_MASK_RXPKT_TYPE_8822C) << BIT_SHIFT_RXPKT_TYPE_8822C) +#define BITS_RXPKT_TYPE_8822C \ + (BIT_MASK_RXPKT_TYPE_8822C << BIT_SHIFT_RXPKT_TYPE_8822C) +#define BIT_CLEAR_RXPKT_TYPE_8822C(x) ((x) & (~BITS_RXPKT_TYPE_8822C)) +#define BIT_GET_RXPKT_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_RXPKT_TYPE_8822C) & BIT_MASK_RXPKT_TYPE_8822C) +#define BIT_SET_RXPKT_TYPE_8822C(x, v) \ + (BIT_CLEAR_RXPKT_TYPE_8822C(x) | BIT_RXPKT_TYPE_8822C(v)) + +#define BIT_TXACT_IND_8822C BIT(1) +#define BIT_RXACT_IND_8822C BIT(0) + +/* 2 REG_WMAC_BITMAP_CTL_8822C */ +#define BIT_BITMAP_VO_8822C BIT(7) +#define BIT_BITMAP_VI_8822C BIT(6) +#define BIT_BITMAP_BE_8822C BIT(5) +#define BIT_BITMAP_BK_8822C BIT(4) + +#define BIT_SHIFT_BITMAP_CONDITION_8822C 2 +#define BIT_MASK_BITMAP_CONDITION_8822C 0x3 +#define BIT_BITMAP_CONDITION_8822C(x) \ + (((x) & BIT_MASK_BITMAP_CONDITION_8822C) \ + << BIT_SHIFT_BITMAP_CONDITION_8822C) +#define BITS_BITMAP_CONDITION_8822C \ + (BIT_MASK_BITMAP_CONDITION_8822C << BIT_SHIFT_BITMAP_CONDITION_8822C) +#define BIT_CLEAR_BITMAP_CONDITION_8822C(x) \ + ((x) & (~BITS_BITMAP_CONDITION_8822C)) +#define BIT_GET_BITMAP_CONDITION_8822C(x) \ + (((x) >> BIT_SHIFT_BITMAP_CONDITION_8822C) & \ + BIT_MASK_BITMAP_CONDITION_8822C) +#define BIT_SET_BITMAP_CONDITION_8822C(x, v) \ + (BIT_CLEAR_BITMAP_CONDITION_8822C(x) | BIT_BITMAP_CONDITION_8822C(v)) + +#define BIT_BITMAP_SSNBK_COUNTER_CLR_8822C BIT(1) +#define BIT_BITMAP_FORCE_8822C BIT(0) + +/* 2 REG_RXERR_RPT_8822C (RX ERROR REPORT REGISTER) */ + +#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C 28 +#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C 0xf +#define BIT_RXERR_RPT_SEL_V1_3_0_8822C(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C) \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C) +#define BITS_RXERR_RPT_SEL_V1_3_0_8822C \ + (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822C(x) \ + ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8822C)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822C(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C) & \ + BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8822C(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822C(x) | \ + BIT_RXERR_RPT_SEL_V1_3_0_8822C(v)) + +#define BIT_RXERR_RPT_RST_8822C BIT(27) +#define BIT_RXERR_RPT_SEL_V1_4_8822C BIT(26) + +#define BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C 24 +#define BIT_MASK_UD_SELECT_BSSID_2_1_8822C 0x3 +#define BIT_UD_SELECT_BSSID_2_1_8822C(x) \ + (((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8822C) \ + << BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C) +#define BITS_UD_SELECT_BSSID_2_1_8822C \ + (BIT_MASK_UD_SELECT_BSSID_2_1_8822C \ + << BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C) +#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8822C(x) \ + ((x) & (~BITS_UD_SELECT_BSSID_2_1_8822C)) +#define BIT_GET_UD_SELECT_BSSID_2_1_8822C(x) \ + (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C) & \ + BIT_MASK_UD_SELECT_BSSID_2_1_8822C) +#define BIT_SET_UD_SELECT_BSSID_2_1_8822C(x, v) \ + (BIT_CLEAR_UD_SELECT_BSSID_2_1_8822C(x) | \ + BIT_UD_SELECT_BSSID_2_1_8822C(v)) + +#define BIT_W1S_8822C BIT(23) +#define BIT_UD_SELECT_BSSID_0_8822C BIT(22) + +#define BIT_SHIFT_UD_SUB_TYPE_8822C 18 +#define BIT_MASK_UD_SUB_TYPE_8822C 0xf +#define BIT_UD_SUB_TYPE_8822C(x) \ + (((x) & BIT_MASK_UD_SUB_TYPE_8822C) << BIT_SHIFT_UD_SUB_TYPE_8822C) +#define BITS_UD_SUB_TYPE_8822C \ + (BIT_MASK_UD_SUB_TYPE_8822C << BIT_SHIFT_UD_SUB_TYPE_8822C) +#define BIT_CLEAR_UD_SUB_TYPE_8822C(x) ((x) & (~BITS_UD_SUB_TYPE_8822C)) +#define BIT_GET_UD_SUB_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_UD_SUB_TYPE_8822C) & BIT_MASK_UD_SUB_TYPE_8822C) +#define BIT_SET_UD_SUB_TYPE_8822C(x, v) \ + (BIT_CLEAR_UD_SUB_TYPE_8822C(x) | BIT_UD_SUB_TYPE_8822C(v)) + +#define BIT_SHIFT_UD_TYPE_8822C 16 +#define BIT_MASK_UD_TYPE_8822C 0x3 +#define BIT_UD_TYPE_8822C(x) \ + (((x) & BIT_MASK_UD_TYPE_8822C) << BIT_SHIFT_UD_TYPE_8822C) +#define BITS_UD_TYPE_8822C (BIT_MASK_UD_TYPE_8822C << BIT_SHIFT_UD_TYPE_8822C) +#define BIT_CLEAR_UD_TYPE_8822C(x) ((x) & (~BITS_UD_TYPE_8822C)) +#define BIT_GET_UD_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_UD_TYPE_8822C) & BIT_MASK_UD_TYPE_8822C) +#define BIT_SET_UD_TYPE_8822C(x, v) \ + (BIT_CLEAR_UD_TYPE_8822C(x) | BIT_UD_TYPE_8822C(v)) + +#define BIT_SHIFT_RPT_COUNTER_8822C 0 +#define BIT_MASK_RPT_COUNTER_8822C 0xffff +#define BIT_RPT_COUNTER_8822C(x) \ + (((x) & BIT_MASK_RPT_COUNTER_8822C) << BIT_SHIFT_RPT_COUNTER_8822C) +#define BITS_RPT_COUNTER_8822C \ + (BIT_MASK_RPT_COUNTER_8822C << BIT_SHIFT_RPT_COUNTER_8822C) +#define BIT_CLEAR_RPT_COUNTER_8822C(x) ((x) & (~BITS_RPT_COUNTER_8822C)) +#define BIT_GET_RPT_COUNTER_8822C(x) \ + (((x) >> BIT_SHIFT_RPT_COUNTER_8822C) & BIT_MASK_RPT_COUNTER_8822C) +#define BIT_SET_RPT_COUNTER_8822C(x, v) \ + (BIT_CLEAR_RPT_COUNTER_8822C(x) | BIT_RPT_COUNTER_8822C(v)) + +/* 2 REG_WMAC_TRXPTCL_CTL_8822C (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ +#define BIT_ACKTO_BLOCK_SCH_EN_8822C BIT(27) +#define BIT_EIFS_BLOCK_SCH_EN_8822C BIT(26) +#define BIT_PLCPCHK_RST_EIFS_8822C BIT(25) +#define BIT_CCA_RST_EIFS_8822C BIT(24) +#define BIT_DIS_UPD_MYRXPKTNAV_8822C BIT(23) +#define BIT_EARLY_TXBA_8822C BIT(22) + +#define BIT_SHIFT_RESP_CHNBUSY_8822C 20 +#define BIT_MASK_RESP_CHNBUSY_8822C 0x3 +#define BIT_RESP_CHNBUSY_8822C(x) \ + (((x) & BIT_MASK_RESP_CHNBUSY_8822C) << BIT_SHIFT_RESP_CHNBUSY_8822C) +#define BITS_RESP_CHNBUSY_8822C \ + (BIT_MASK_RESP_CHNBUSY_8822C << BIT_SHIFT_RESP_CHNBUSY_8822C) +#define BIT_CLEAR_RESP_CHNBUSY_8822C(x) ((x) & (~BITS_RESP_CHNBUSY_8822C)) +#define BIT_GET_RESP_CHNBUSY_8822C(x) \ + (((x) >> BIT_SHIFT_RESP_CHNBUSY_8822C) & BIT_MASK_RESP_CHNBUSY_8822C) +#define BIT_SET_RESP_CHNBUSY_8822C(x, v) \ + (BIT_CLEAR_RESP_CHNBUSY_8822C(x) | BIT_RESP_CHNBUSY_8822C(v)) + +#define BIT_RESP_DCTS_EN_8822C BIT(19) +#define BIT_RESP_DCFE_EN_8822C BIT(18) +#define BIT_RESP_SPLCPEN_8822C BIT(17) +#define BIT_RESP_SGIEN_8822C BIT(16) +#define BIT_RESP_LDPC_EN_8822C BIT(15) +#define BIT_DIS_RESP_ACKINCCA_8822C BIT(14) +#define BIT_DIS_RESP_CTSINCCA_8822C BIT(13) + +#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C 10 +#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C 0x7 +#define BIT_R_WMAC_SECOND_CCA_TIMER_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C) \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C) +#define BITS_R_WMAC_SECOND_CCA_TIMER_8822C \ + (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822C(x) \ + ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8822C)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C) & \ + BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822C(x) | \ + BIT_R_WMAC_SECOND_CCA_TIMER_8822C(v)) + +#define BIT_SHIFT_RFMOD_8822C 7 +#define BIT_MASK_RFMOD_8822C 0x3 +#define BIT_RFMOD_8822C(x) \ + (((x) & BIT_MASK_RFMOD_8822C) << BIT_SHIFT_RFMOD_8822C) +#define BITS_RFMOD_8822C (BIT_MASK_RFMOD_8822C << BIT_SHIFT_RFMOD_8822C) +#define BIT_CLEAR_RFMOD_8822C(x) ((x) & (~BITS_RFMOD_8822C)) +#define BIT_GET_RFMOD_8822C(x) \ + (((x) >> BIT_SHIFT_RFMOD_8822C) & BIT_MASK_RFMOD_8822C) +#define BIT_SET_RFMOD_8822C(x, v) \ + (BIT_CLEAR_RFMOD_8822C(x) | BIT_RFMOD_8822C(v)) + +#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C 5 +#define BIT_MASK_RESP_CTS_DYNBW_SEL_8822C 0x3 +#define BIT_RESP_CTS_DYNBW_SEL_8822C(x) \ + (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822C) \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C) +#define BITS_RESP_CTS_DYNBW_SEL_8822C \ + (BIT_MASK_RESP_CTS_DYNBW_SEL_8822C \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822C(x) \ + ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8822C)) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C) & \ + BIT_MASK_RESP_CTS_DYNBW_SEL_8822C) +#define BIT_SET_RESP_CTS_DYNBW_SEL_8822C(x, v) \ + (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822C(x) | \ + BIT_RESP_CTS_DYNBW_SEL_8822C(v)) + +#define BIT_DLY_TX_WAIT_RXANTSEL_8822C BIT(4) +#define BIT_TXRESP_BY_RXANTSEL_8822C BIT(3) + +#define BIT_SHIFT_ORIG_DCTS_CHK_8822C 0 +#define BIT_MASK_ORIG_DCTS_CHK_8822C 0x3 +#define BIT_ORIG_DCTS_CHK_8822C(x) \ + (((x) & BIT_MASK_ORIG_DCTS_CHK_8822C) << BIT_SHIFT_ORIG_DCTS_CHK_8822C) +#define BITS_ORIG_DCTS_CHK_8822C \ + (BIT_MASK_ORIG_DCTS_CHK_8822C << BIT_SHIFT_ORIG_DCTS_CHK_8822C) +#define BIT_CLEAR_ORIG_DCTS_CHK_8822C(x) ((x) & (~BITS_ORIG_DCTS_CHK_8822C)) +#define BIT_GET_ORIG_DCTS_CHK_8822C(x) \ + (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822C) & BIT_MASK_ORIG_DCTS_CHK_8822C) +#define BIT_SET_ORIG_DCTS_CHK_8822C(x, v) \ + (BIT_CLEAR_ORIG_DCTS_CHK_8822C(x) | BIT_ORIG_DCTS_CHK_8822C(v)) + +/* 2 REG_WMAC_TRXPTCL_CTL_H_8822C */ + +#define BIT_SHIFT_ACKBA_TYPSEL_8822C 28 +#define BIT_MASK_ACKBA_TYPSEL_8822C 0xf +#define BIT_ACKBA_TYPSEL_8822C(x) \ + (((x) & BIT_MASK_ACKBA_TYPSEL_8822C) << BIT_SHIFT_ACKBA_TYPSEL_8822C) +#define BITS_ACKBA_TYPSEL_8822C \ + (BIT_MASK_ACKBA_TYPSEL_8822C << BIT_SHIFT_ACKBA_TYPSEL_8822C) +#define BIT_CLEAR_ACKBA_TYPSEL_8822C(x) ((x) & (~BITS_ACKBA_TYPSEL_8822C)) +#define BIT_GET_ACKBA_TYPSEL_8822C(x) \ + (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822C) & BIT_MASK_ACKBA_TYPSEL_8822C) +#define BIT_SET_ACKBA_TYPSEL_8822C(x, v) \ + (BIT_CLEAR_ACKBA_TYPSEL_8822C(x) | BIT_ACKBA_TYPSEL_8822C(v)) + +#define BIT_SHIFT_ACKBA_ACKPCHK_8822C 24 +#define BIT_MASK_ACKBA_ACKPCHK_8822C 0xf +#define BIT_ACKBA_ACKPCHK_8822C(x) \ + (((x) & BIT_MASK_ACKBA_ACKPCHK_8822C) << BIT_SHIFT_ACKBA_ACKPCHK_8822C) +#define BITS_ACKBA_ACKPCHK_8822C \ + (BIT_MASK_ACKBA_ACKPCHK_8822C << BIT_SHIFT_ACKBA_ACKPCHK_8822C) +#define BIT_CLEAR_ACKBA_ACKPCHK_8822C(x) ((x) & (~BITS_ACKBA_ACKPCHK_8822C)) +#define BIT_GET_ACKBA_ACKPCHK_8822C(x) \ + (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822C) & BIT_MASK_ACKBA_ACKPCHK_8822C) +#define BIT_SET_ACKBA_ACKPCHK_8822C(x, v) \ + (BIT_CLEAR_ACKBA_ACKPCHK_8822C(x) | BIT_ACKBA_ACKPCHK_8822C(v)) + +#define BIT_SHIFT_ACKBAR_TYPESEL_8822C 16 +#define BIT_MASK_ACKBAR_TYPESEL_8822C 0xff +#define BIT_ACKBAR_TYPESEL_8822C(x) \ + (((x) & BIT_MASK_ACKBAR_TYPESEL_8822C) \ + << BIT_SHIFT_ACKBAR_TYPESEL_8822C) +#define BITS_ACKBAR_TYPESEL_8822C \ + (BIT_MASK_ACKBAR_TYPESEL_8822C << BIT_SHIFT_ACKBAR_TYPESEL_8822C) +#define BIT_CLEAR_ACKBAR_TYPESEL_8822C(x) ((x) & (~BITS_ACKBAR_TYPESEL_8822C)) +#define BIT_GET_ACKBAR_TYPESEL_8822C(x) \ + (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822C) & \ + BIT_MASK_ACKBAR_TYPESEL_8822C) +#define BIT_SET_ACKBAR_TYPESEL_8822C(x, v) \ + (BIT_CLEAR_ACKBAR_TYPESEL_8822C(x) | BIT_ACKBAR_TYPESEL_8822C(v)) + +#define BIT_SHIFT_ACKBAR_ACKPCHK_8822C 12 +#define BIT_MASK_ACKBAR_ACKPCHK_8822C 0xf +#define BIT_ACKBAR_ACKPCHK_8822C(x) \ + (((x) & BIT_MASK_ACKBAR_ACKPCHK_8822C) \ + << BIT_SHIFT_ACKBAR_ACKPCHK_8822C) +#define BITS_ACKBAR_ACKPCHK_8822C \ + (BIT_MASK_ACKBAR_ACKPCHK_8822C << BIT_SHIFT_ACKBAR_ACKPCHK_8822C) +#define BIT_CLEAR_ACKBAR_ACKPCHK_8822C(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8822C)) +#define BIT_GET_ACKBAR_ACKPCHK_8822C(x) \ + (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822C) & \ + BIT_MASK_ACKBAR_ACKPCHK_8822C) +#define BIT_SET_ACKBAR_ACKPCHK_8822C(x, v) \ + (BIT_CLEAR_ACKBAR_ACKPCHK_8822C(x) | BIT_ACKBAR_ACKPCHK_8822C(v)) + +#define BIT_RXBA_IGNOREA2_V1_8822C BIT(10) +#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8822C BIT(9) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8822C BIT(8) +#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8822C BIT(7) +#define BIT_DIS_TXBA_RXBARINFULL_V1_8822C BIT(6) +#define BIT_DIS_TXCFE_INFULL_V1_8822C BIT(5) +#define BIT_DIS_TXCTS_INFULL_V1_8822C BIT(4) +#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8822C BIT(3) +#define BIT_EN_TXACKBA_IN_TXOP_V1_8822C BIT(2) +#define BIT_EN_TXCTS_IN_RXNAV_V1_8822C BIT(1) +#define BIT_EN_TXCTS_INTXOP_V1_8822C BIT(0) + +/* 2 REG_CAMCMD_8822C (CAM COMMAND REGISTER) */ +#define BIT_SECCAM_POLLING_8822C BIT(31) +#define BIT_SECCAM_CLR_8822C BIT(30) +#define BIT_SECCAM_WE_8822C BIT(16) + +#define BIT_SHIFT_SECCAM_ADDR_V2_8822C 0 +#define BIT_MASK_SECCAM_ADDR_V2_8822C 0x3ff +#define BIT_SECCAM_ADDR_V2_8822C(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V2_8822C) \ + << BIT_SHIFT_SECCAM_ADDR_V2_8822C) +#define BITS_SECCAM_ADDR_V2_8822C \ + (BIT_MASK_SECCAM_ADDR_V2_8822C << BIT_SHIFT_SECCAM_ADDR_V2_8822C) +#define BIT_CLEAR_SECCAM_ADDR_V2_8822C(x) ((x) & (~BITS_SECCAM_ADDR_V2_8822C)) +#define BIT_GET_SECCAM_ADDR_V2_8822C(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822C) & \ + BIT_MASK_SECCAM_ADDR_V2_8822C) +#define BIT_SET_SECCAM_ADDR_V2_8822C(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V2_8822C(x) | BIT_SECCAM_ADDR_V2_8822C(v)) + +/* 2 REG_CAMWRITE_8822C (CAM WRITE REGISTER) */ + +#define BIT_SHIFT_CAMW_DATA_8822C 0 +#define BIT_MASK_CAMW_DATA_8822C 0xffffffffL +#define BIT_CAMW_DATA_8822C(x) \ + (((x) & BIT_MASK_CAMW_DATA_8822C) << BIT_SHIFT_CAMW_DATA_8822C) +#define BITS_CAMW_DATA_8822C \ + (BIT_MASK_CAMW_DATA_8822C << BIT_SHIFT_CAMW_DATA_8822C) +#define BIT_CLEAR_CAMW_DATA_8822C(x) ((x) & (~BITS_CAMW_DATA_8822C)) +#define BIT_GET_CAMW_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_CAMW_DATA_8822C) & BIT_MASK_CAMW_DATA_8822C) +#define BIT_SET_CAMW_DATA_8822C(x, v) \ + (BIT_CLEAR_CAMW_DATA_8822C(x) | BIT_CAMW_DATA_8822C(v)) + +/* 2 REG_CAMREAD_8822C (CAM READ REGISTER) */ + +#define BIT_SHIFT_CAMR_DATA_8822C 0 +#define BIT_MASK_CAMR_DATA_8822C 0xffffffffL +#define BIT_CAMR_DATA_8822C(x) \ + (((x) & BIT_MASK_CAMR_DATA_8822C) << BIT_SHIFT_CAMR_DATA_8822C) +#define BITS_CAMR_DATA_8822C \ + (BIT_MASK_CAMR_DATA_8822C << BIT_SHIFT_CAMR_DATA_8822C) +#define BIT_CLEAR_CAMR_DATA_8822C(x) ((x) & (~BITS_CAMR_DATA_8822C)) +#define BIT_GET_CAMR_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_CAMR_DATA_8822C) & BIT_MASK_CAMR_DATA_8822C) +#define BIT_SET_CAMR_DATA_8822C(x, v) \ + (BIT_CLEAR_CAMR_DATA_8822C(x) | BIT_CAMR_DATA_8822C(v)) + +/* 2 REG_CAMDBG_8822C (CAM DEBUG REGISTER) */ +#define BIT_SECCAM_INFO_8822C BIT(31) +#define BIT_SEC_KEYFOUND_8822C BIT(15) + +#define BIT_SHIFT_CAMDBG_SEC_TYPE_8822C 12 +#define BIT_MASK_CAMDBG_SEC_TYPE_8822C 0x7 +#define BIT_CAMDBG_SEC_TYPE_8822C(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822C) \ + << BIT_SHIFT_CAMDBG_SEC_TYPE_8822C) +#define BITS_CAMDBG_SEC_TYPE_8822C \ + (BIT_MASK_CAMDBG_SEC_TYPE_8822C << BIT_SHIFT_CAMDBG_SEC_TYPE_8822C) +#define BIT_CLEAR_CAMDBG_SEC_TYPE_8822C(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8822C)) +#define BIT_GET_CAMDBG_SEC_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822C) & \ + BIT_MASK_CAMDBG_SEC_TYPE_8822C) +#define BIT_SET_CAMDBG_SEC_TYPE_8822C(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE_8822C(x) | BIT_CAMDBG_SEC_TYPE_8822C(v)) + +#define BIT_CAMDBG_EXT_SECTYPE_8822C BIT(11) + +#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C 5 +#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C 0x1f +#define BIT_CAMDBG_MIC_KEY_IDX_8822C(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C) \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C) +#define BITS_CAMDBG_MIC_KEY_IDX_8822C \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822C(x) \ + ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8822C)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C) & \ + BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_8822C(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822C(x) | \ + BIT_CAMDBG_MIC_KEY_IDX_8822C(v)) + +#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C 0 +#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C 0x1f +#define BIT_CAMDBG_SEC_KEY_IDX_8822C(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C) \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C) +#define BITS_CAMDBG_SEC_KEY_IDX_8822C \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822C(x) \ + ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8822C)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C) & \ + BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_8822C(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822C(x) | \ + BIT_CAMDBG_SEC_KEY_IDX_8822C(v)) + +/* 2 REG_SECCFG_8822C (SECURITY CONFIGURATION REGISTER) */ +#define BIT_DIS_GCLK_WAPI_8822C BIT(15) +#define BIT_DIS_GCLK_AES_8822C BIT(14) +#define BIT_DIS_GCLK_TKIP_8822C BIT(13) +#define BIT_AES_SEL_QC_1_8822C BIT(12) +#define BIT_AES_SEL_QC_0_8822C BIT(11) +#define BIT_CHK_BMC_8822C BIT(9) +#define BIT_CHK_KEYID_8822C BIT(8) +#define BIT_RXBCUSEDK_8822C BIT(7) +#define BIT_TXBCUSEDK_8822C BIT(6) +#define BIT_NOSKMC_8822C BIT(5) +#define BIT_SKBYA2_8822C BIT(4) +#define BIT_RXDEC_8822C BIT(3) +#define BIT_TXENC_8822C BIT(2) +#define BIT_RXUHUSEDK_8822C BIT(1) +#define BIT_TXUHUSEDK_8822C BIT(0) + +/* 2 REG_RXFILTER_CATEGORY_1_8822C */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_1_8822C 0 +#define BIT_MASK_RXFILTER_CATEGORY_1_8822C 0xff +#define BIT_RXFILTER_CATEGORY_1_8822C(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822C) \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8822C) +#define BITS_RXFILTER_CATEGORY_1_8822C \ + (BIT_MASK_RXFILTER_CATEGORY_1_8822C \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8822C) +#define BIT_CLEAR_RXFILTER_CATEGORY_1_8822C(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_1_8822C)) +#define BIT_GET_RXFILTER_CATEGORY_1_8822C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822C) & \ + BIT_MASK_RXFILTER_CATEGORY_1_8822C) +#define BIT_SET_RXFILTER_CATEGORY_1_8822C(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_1_8822C(x) | \ + BIT_RXFILTER_CATEGORY_1_8822C(v)) + +/* 2 REG_RXFILTER_ACTION_1_8822C */ + +#define BIT_SHIFT_RXFILTER_ACTION_1_8822C 0 +#define BIT_MASK_RXFILTER_ACTION_1_8822C 0xff +#define BIT_RXFILTER_ACTION_1_8822C(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_1_8822C) \ + << BIT_SHIFT_RXFILTER_ACTION_1_8822C) +#define BITS_RXFILTER_ACTION_1_8822C \ + (BIT_MASK_RXFILTER_ACTION_1_8822C << BIT_SHIFT_RXFILTER_ACTION_1_8822C) +#define BIT_CLEAR_RXFILTER_ACTION_1_8822C(x) \ + ((x) & (~BITS_RXFILTER_ACTION_1_8822C)) +#define BIT_GET_RXFILTER_ACTION_1_8822C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822C) & \ + BIT_MASK_RXFILTER_ACTION_1_8822C) +#define BIT_SET_RXFILTER_ACTION_1_8822C(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_1_8822C(x) | BIT_RXFILTER_ACTION_1_8822C(v)) + +/* 2 REG_RXFILTER_CATEGORY_2_8822C */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_2_8822C 0 +#define BIT_MASK_RXFILTER_CATEGORY_2_8822C 0xff +#define BIT_RXFILTER_CATEGORY_2_8822C(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822C) \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8822C) +#define BITS_RXFILTER_CATEGORY_2_8822C \ + (BIT_MASK_RXFILTER_CATEGORY_2_8822C \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8822C) +#define BIT_CLEAR_RXFILTER_CATEGORY_2_8822C(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_2_8822C)) +#define BIT_GET_RXFILTER_CATEGORY_2_8822C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822C) & \ + BIT_MASK_RXFILTER_CATEGORY_2_8822C) +#define BIT_SET_RXFILTER_CATEGORY_2_8822C(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_2_8822C(x) | \ + BIT_RXFILTER_CATEGORY_2_8822C(v)) + +/* 2 REG_RXFILTER_ACTION_2_8822C */ + +#define BIT_SHIFT_RXFILTER_ACTION_2_8822C 0 +#define BIT_MASK_RXFILTER_ACTION_2_8822C 0xff +#define BIT_RXFILTER_ACTION_2_8822C(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_2_8822C) \ + << BIT_SHIFT_RXFILTER_ACTION_2_8822C) +#define BITS_RXFILTER_ACTION_2_8822C \ + (BIT_MASK_RXFILTER_ACTION_2_8822C << BIT_SHIFT_RXFILTER_ACTION_2_8822C) +#define BIT_CLEAR_RXFILTER_ACTION_2_8822C(x) \ + ((x) & (~BITS_RXFILTER_ACTION_2_8822C)) +#define BIT_GET_RXFILTER_ACTION_2_8822C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822C) & \ + BIT_MASK_RXFILTER_ACTION_2_8822C) +#define BIT_SET_RXFILTER_ACTION_2_8822C(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_2_8822C(x) | BIT_RXFILTER_ACTION_2_8822C(v)) + +/* 2 REG_RXFILTER_CATEGORY_3_8822C */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_3_8822C 0 +#define BIT_MASK_RXFILTER_CATEGORY_3_8822C 0xff +#define BIT_RXFILTER_CATEGORY_3_8822C(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822C) \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8822C) +#define BITS_RXFILTER_CATEGORY_3_8822C \ + (BIT_MASK_RXFILTER_CATEGORY_3_8822C \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8822C) +#define BIT_CLEAR_RXFILTER_CATEGORY_3_8822C(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_3_8822C)) +#define BIT_GET_RXFILTER_CATEGORY_3_8822C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822C) & \ + BIT_MASK_RXFILTER_CATEGORY_3_8822C) +#define BIT_SET_RXFILTER_CATEGORY_3_8822C(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_3_8822C(x) | \ + BIT_RXFILTER_CATEGORY_3_8822C(v)) + +/* 2 REG_RXFILTER_ACTION_3_8822C */ + +#define BIT_SHIFT_RXFILTER_ACTION_3_8822C 0 +#define BIT_MASK_RXFILTER_ACTION_3_8822C 0xff +#define BIT_RXFILTER_ACTION_3_8822C(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_3_8822C) \ + << BIT_SHIFT_RXFILTER_ACTION_3_8822C) +#define BITS_RXFILTER_ACTION_3_8822C \ + (BIT_MASK_RXFILTER_ACTION_3_8822C << BIT_SHIFT_RXFILTER_ACTION_3_8822C) +#define BIT_CLEAR_RXFILTER_ACTION_3_8822C(x) \ + ((x) & (~BITS_RXFILTER_ACTION_3_8822C)) +#define BIT_GET_RXFILTER_ACTION_3_8822C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822C) & \ + BIT_MASK_RXFILTER_ACTION_3_8822C) +#define BIT_SET_RXFILTER_ACTION_3_8822C(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_3_8822C(x) | BIT_RXFILTER_ACTION_3_8822C(v)) + +/* 2 REG_RXFLTMAP3_8822C (RX FILTER MAP GROUP 3) */ +#define BIT_MGTFLT15EN_FW_8822C BIT(15) +#define BIT_MGTFLT14EN_FW_8822C BIT(14) +#define BIT_MGTFLT13EN_FW_8822C BIT(13) +#define BIT_MGTFLT12EN_FW_8822C BIT(12) +#define BIT_MGTFLT11EN_FW_8822C BIT(11) +#define BIT_MGTFLT10EN_FW_8822C BIT(10) +#define BIT_MGTFLT9EN_FW_8822C BIT(9) +#define BIT_MGTFLT8EN_FW_8822C BIT(8) +#define BIT_MGTFLT7EN_FW_8822C BIT(7) +#define BIT_MGTFLT6EN_FW_8822C BIT(6) +#define BIT_MGTFLT5EN_FW_8822C BIT(5) +#define BIT_MGTFLT4EN_FW_8822C BIT(4) +#define BIT_MGTFLT3EN_FW_8822C BIT(3) +#define BIT_MGTFLT2EN_FW_8822C BIT(2) +#define BIT_MGTFLT1EN_FW_8822C BIT(1) +#define BIT_MGTFLT0EN_FW_8822C BIT(0) + +/* 2 REG_RXFLTMAP4_8822C (RX FILTER MAP GROUP 4) */ +#define BIT_CTRLFLT15EN_FW_8822C BIT(15) +#define BIT_CTRLFLT14EN_FW_8822C BIT(14) +#define BIT_CTRLFLT13EN_FW_8822C BIT(13) +#define BIT_CTRLFLT12EN_FW_8822C BIT(12) +#define BIT_CTRLFLT11EN_FW_8822C BIT(11) +#define BIT_CTRLFLT10EN_FW_8822C BIT(10) +#define BIT_CTRLFLT9EN_FW_8822C BIT(9) +#define BIT_CTRLFLT8EN_FW_8822C BIT(8) +#define BIT_CTRLFLT7EN_FW_8822C BIT(7) +#define BIT_CTRLFLT6EN_FW_8822C BIT(6) +#define BIT_CTRLFLT5EN_FW_8822C BIT(5) +#define BIT_CTRLFLT4EN_FW_8822C BIT(4) +#define BIT_CTRLFLT3EN_FW_8822C BIT(3) +#define BIT_CTRLFLT2EN_FW_8822C BIT(2) +#define BIT_CTRLFLT1EN_FW_8822C BIT(1) +#define BIT_CTRLFLT0EN_FW_8822C BIT(0) + +/* 2 REG_RXFLTMAP5_8822C (RX FILTER MAP GROUP 5) */ +#define BIT_DATAFLT15EN_FW_8822C BIT(15) +#define BIT_DATAFLT14EN_FW_8822C BIT(14) +#define BIT_DATAFLT13EN_FW_8822C BIT(13) +#define BIT_DATAFLT12EN_FW_8822C BIT(12) +#define BIT_DATAFLT11EN_FW_8822C BIT(11) +#define BIT_DATAFLT10EN_FW_8822C BIT(10) +#define BIT_DATAFLT9EN_FW_8822C BIT(9) +#define BIT_DATAFLT8EN_FW_8822C BIT(8) +#define BIT_DATAFLT7EN_FW_8822C BIT(7) +#define BIT_DATAFLT6EN_FW_8822C BIT(6) +#define BIT_DATAFLT5EN_FW_8822C BIT(5) +#define BIT_DATAFLT4EN_FW_8822C BIT(4) +#define BIT_DATAFLT3EN_FW_8822C BIT(3) +#define BIT_DATAFLT2EN_FW_8822C BIT(2) +#define BIT_DATAFLT1EN_FW_8822C BIT(1) +#define BIT_DATAFLT0EN_FW_8822C BIT(0) + +/* 2 REG_RXFLTMAP6_8822C (RX FILTER MAP GROUP 6) */ +#define BIT_ACTIONFLT15EN_FW_8822C BIT(15) +#define BIT_ACTIONFLT14EN_FW_8822C BIT(14) +#define BIT_ACTIONFLT13EN_FW_8822C BIT(13) +#define BIT_ACTIONFLT12EN_FW_8822C BIT(12) +#define BIT_ACTIONFLT11EN_FW_8822C BIT(11) +#define BIT_ACTIONFLT10EN_FW_8822C BIT(10) +#define BIT_ACTIONFLT9EN_FW_8822C BIT(9) +#define BIT_ACTIONFLT8EN_FW_8822C BIT(8) +#define BIT_ACTIONFLT7EN_FW_8822C BIT(7) +#define BIT_ACTIONFLT6EN_FW_8822C BIT(6) +#define BIT_ACTIONFLT5EN_FW_8822C BIT(5) +#define BIT_ACTIONFLT4EN_FW_8822C BIT(4) +#define BIT_ACTIONFLT3EN_FW_8822C BIT(3) +#define BIT_ACTIONFLT2EN_FW_8822C BIT(2) +#define BIT_ACTIONFLT1EN_FW_8822C BIT(1) +#define BIT_ACTIONFLT0EN_FW_8822C BIT(0) + +/* 2 REG_WOW_CTRL_8822C (WAKE ON WLAN CONTROL REGISTER) */ + +#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C 6 +#define BIT_MASK_PSF_BSSIDSEL_B2B1_8822C 0x3 +#define BIT_PSF_BSSIDSEL_B2B1_8822C(x) \ + (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822C) \ + << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C) +#define BITS_PSF_BSSIDSEL_B2B1_8822C \ + (BIT_MASK_PSF_BSSIDSEL_B2B1_8822C << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822C(x) \ + ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8822C)) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8822C(x) \ + (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C) & \ + BIT_MASK_PSF_BSSIDSEL_B2B1_8822C) +#define BIT_SET_PSF_BSSIDSEL_B2B1_8822C(x, v) \ + (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822C(x) | BIT_PSF_BSSIDSEL_B2B1_8822C(v)) + +#define BIT_WOWHCI_8822C BIT(5) +#define BIT_PSF_BSSIDSEL_B0_8822C BIT(4) +#define BIT_UWF_8822C BIT(3) +#define BIT_MAGIC_8822C BIT(2) +#define BIT_WOWEN_8822C BIT(1) +#define BIT_FORCE_WAKEUP_8822C BIT(0) + +/* 2 REG_NAN_RX_TSF_FILTER_8822C(NAN_RX_TSF_ADDRESS_FILTER) */ +#define BIT_CHK_TSF_TA_8822C BIT(2) +#define BIT_CHK_TSF_CBSSID_8822C BIT(1) +#define BIT_CHK_TSF_EN_8822C BIT(0) + +/* 2 REG_PS_RX_INFO_8822C (POWER SAVE RX INFORMATION REGISTER) */ + +#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C 5 +#define BIT_MASK_PORTSEL__PS_RX_INFO_8822C 0x7 +#define BIT_PORTSEL__PS_RX_INFO_8822C(x) \ + (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822C) \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C) +#define BITS_PORTSEL__PS_RX_INFO_8822C \ + (BIT_MASK_PORTSEL__PS_RX_INFO_8822C \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8822C(x) \ + ((x) & (~BITS_PORTSEL__PS_RX_INFO_8822C)) +#define BIT_GET_PORTSEL__PS_RX_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C) & \ + BIT_MASK_PORTSEL__PS_RX_INFO_8822C) +#define BIT_SET_PORTSEL__PS_RX_INFO_8822C(x, v) \ + (BIT_CLEAR_PORTSEL__PS_RX_INFO_8822C(x) | \ + BIT_PORTSEL__PS_RX_INFO_8822C(v)) + +#define BIT_RXCTRLIN0_8822C BIT(4) +#define BIT_RXMGTIN0_8822C BIT(3) +#define BIT_RXDATAIN2_8822C BIT(2) +#define BIT_RXDATAIN1_8822C BIT(1) +#define BIT_RXDATAIN0_8822C BIT(0) + +/* 2 REG_WMMPS_UAPSD_TID_8822C (WMM POWER SAVE UAPSD TID REGISTER) */ +#define BIT_WMMPS_UAPSD_TID7_8822C BIT(7) +#define BIT_WMMPS_UAPSD_TID6_8822C BIT(6) +#define BIT_WMMPS_UAPSD_TID5_8822C BIT(5) +#define BIT_WMMPS_UAPSD_TID4_8822C BIT(4) +#define BIT_WMMPS_UAPSD_TID3_8822C BIT(3) +#define BIT_WMMPS_UAPSD_TID2_8822C BIT(2) +#define BIT_WMMPS_UAPSD_TID1_8822C BIT(1) +#define BIT_WMMPS_UAPSD_TID0_8822C BIT(0) + +/* 2 REG_LPNAV_CTRL_8822C (LOW POWER NAV CONTROL REGISTER) */ + +/* 2 REG_WKFMCAM_CMD_8822C (WAKEUP FRAME CAM COMMAND REGISTER) */ +#define BIT_WKFCAM_POLLING_V1_8822C BIT(31) +#define BIT_WKFCAM_CLR_V1_8822C BIT(30) +#define BIT_WKFCAM_WE_8822C BIT(16) + +#define BIT_SHIFT_WKFCAM_ADDR_V2_8822C 8 +#define BIT_MASK_WKFCAM_ADDR_V2_8822C 0xff +#define BIT_WKFCAM_ADDR_V2_8822C(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR_V2_8822C) \ + << BIT_SHIFT_WKFCAM_ADDR_V2_8822C) +#define BITS_WKFCAM_ADDR_V2_8822C \ + (BIT_MASK_WKFCAM_ADDR_V2_8822C << BIT_SHIFT_WKFCAM_ADDR_V2_8822C) +#define BIT_CLEAR_WKFCAM_ADDR_V2_8822C(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8822C)) +#define BIT_GET_WKFCAM_ADDR_V2_8822C(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822C) & \ + BIT_MASK_WKFCAM_ADDR_V2_8822C) +#define BIT_SET_WKFCAM_ADDR_V2_8822C(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR_V2_8822C(x) | BIT_WKFCAM_ADDR_V2_8822C(v)) + +#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C 0 +#define BIT_MASK_WKFCAM_CAM_NUM_V1_8822C 0xff +#define BIT_WKFCAM_CAM_NUM_V1_8822C(x) \ + (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822C) \ + << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C) +#define BITS_WKFCAM_CAM_NUM_V1_8822C \ + (BIT_MASK_WKFCAM_CAM_NUM_V1_8822C << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822C(x) \ + ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8822C)) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8822C(x) \ + (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C) & \ + BIT_MASK_WKFCAM_CAM_NUM_V1_8822C) +#define BIT_SET_WKFCAM_CAM_NUM_V1_8822C(x, v) \ + (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822C(x) | BIT_WKFCAM_CAM_NUM_V1_8822C(v)) + +/* 2 REG_WKFMCAM_RWD_8822C (WAKEUP FRAME READ/WRITE DATA) */ + +#define BIT_SHIFT_WKFMCAM_RWD_8822C 0 +#define BIT_MASK_WKFMCAM_RWD_8822C 0xffffffffL +#define BIT_WKFMCAM_RWD_8822C(x) \ + (((x) & BIT_MASK_WKFMCAM_RWD_8822C) << BIT_SHIFT_WKFMCAM_RWD_8822C) +#define BITS_WKFMCAM_RWD_8822C \ + (BIT_MASK_WKFMCAM_RWD_8822C << BIT_SHIFT_WKFMCAM_RWD_8822C) +#define BIT_CLEAR_WKFMCAM_RWD_8822C(x) ((x) & (~BITS_WKFMCAM_RWD_8822C)) +#define BIT_GET_WKFMCAM_RWD_8822C(x) \ + (((x) >> BIT_SHIFT_WKFMCAM_RWD_8822C) & BIT_MASK_WKFMCAM_RWD_8822C) +#define BIT_SET_WKFMCAM_RWD_8822C(x, v) \ + (BIT_CLEAR_WKFMCAM_RWD_8822C(x) | BIT_WKFMCAM_RWD_8822C(v)) + +/* 2 REG_RXFLTMAP0_8822C (RX FILTER MAP GROUP 0) */ +#define BIT_MGTFLT15EN_8822C BIT(15) +#define BIT_MGTFLT14EN_8822C BIT(14) +#define BIT_MGTFLT13EN_8822C BIT(13) +#define BIT_MGTFLT12EN_8822C BIT(12) +#define BIT_MGTFLT11EN_8822C BIT(11) +#define BIT_MGTFLT10EN_8822C BIT(10) +#define BIT_MGTFLT9EN_8822C BIT(9) +#define BIT_MGTFLT8EN_8822C BIT(8) +#define BIT_MGTFLT7EN_8822C BIT(7) +#define BIT_MGTFLT6EN_8822C BIT(6) +#define BIT_MGTFLT5EN_8822C BIT(5) +#define BIT_MGTFLT4EN_8822C BIT(4) +#define BIT_MGTFLT3EN_8822C BIT(3) +#define BIT_MGTFLT2EN_8822C BIT(2) +#define BIT_MGTFLT1EN_8822C BIT(1) +#define BIT_MGTFLT0EN_8822C BIT(0) + +/* 2 REG_RXFLTMAP1_8822C (RX FILTER MAP GROUP 1) */ +#define BIT_CTRLFLT15EN_8822C BIT(15) +#define BIT_CTRLFLT14EN_8822C BIT(14) +#define BIT_CTRLFLT13EN_8822C BIT(13) +#define BIT_CTRLFLT12EN_8822C BIT(12) +#define BIT_CTRLFLT11EN_8822C BIT(11) +#define BIT_CTRLFLT10EN_8822C BIT(10) +#define BIT_CTRLFLT9EN_8822C BIT(9) +#define BIT_CTRLFLT8EN_8822C BIT(8) +#define BIT_CTRLFLT7EN_8822C BIT(7) +#define BIT_CTRLFLT6EN_8822C BIT(6) +#define BIT_CTRLFLT5EN_8822C BIT(5) +#define BIT_CTRLFLT4EN_8822C BIT(4) +#define BIT_CTRLFLT3EN_8822C BIT(3) +#define BIT_CTRLFLT2EN_8822C BIT(2) +#define BIT_CTRLFLT1EN_8822C BIT(1) +#define BIT_CTRLFLT0EN_8822C BIT(0) + +/* 2 REG_RXFLTMAP2_8822C (RX FILTER MAP GROUP 2) */ +#define BIT_DATAFLT15EN_8822C BIT(15) +#define BIT_DATAFLT14EN_8822C BIT(14) +#define BIT_DATAFLT13EN_8822C BIT(13) +#define BIT_DATAFLT12EN_8822C BIT(12) +#define BIT_DATAFLT11EN_8822C BIT(11) +#define BIT_DATAFLT10EN_8822C BIT(10) +#define BIT_DATAFLT9EN_8822C BIT(9) +#define BIT_DATAFLT8EN_8822C BIT(8) +#define BIT_DATAFLT7EN_8822C BIT(7) +#define BIT_DATAFLT6EN_8822C BIT(6) +#define BIT_DATAFLT5EN_8822C BIT(5) +#define BIT_DATAFLT4EN_8822C BIT(4) +#define BIT_DATAFLT3EN_8822C BIT(3) +#define BIT_DATAFLT2EN_8822C BIT(2) +#define BIT_DATAFLT1EN_8822C BIT(1) +#define BIT_DATAFLT0EN_8822C BIT(0) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_BCN_PSR_RPT_8822C (BEACON PARSER REPORT REGISTER) */ + +#define BIT_SHIFT_DTIM_CNT_8822C 24 +#define BIT_MASK_DTIM_CNT_8822C 0xff +#define BIT_DTIM_CNT_8822C(x) \ + (((x) & BIT_MASK_DTIM_CNT_8822C) << BIT_SHIFT_DTIM_CNT_8822C) +#define BITS_DTIM_CNT_8822C \ + (BIT_MASK_DTIM_CNT_8822C << BIT_SHIFT_DTIM_CNT_8822C) +#define BIT_CLEAR_DTIM_CNT_8822C(x) ((x) & (~BITS_DTIM_CNT_8822C)) +#define BIT_GET_DTIM_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT_8822C) & BIT_MASK_DTIM_CNT_8822C) +#define BIT_SET_DTIM_CNT_8822C(x, v) \ + (BIT_CLEAR_DTIM_CNT_8822C(x) | BIT_DTIM_CNT_8822C(v)) + +#define BIT_SHIFT_DTIM_PERIOD_8822C 16 +#define BIT_MASK_DTIM_PERIOD_8822C 0xff +#define BIT_DTIM_PERIOD_8822C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD_8822C) << BIT_SHIFT_DTIM_PERIOD_8822C) +#define BITS_DTIM_PERIOD_8822C \ + (BIT_MASK_DTIM_PERIOD_8822C << BIT_SHIFT_DTIM_PERIOD_8822C) +#define BIT_CLEAR_DTIM_PERIOD_8822C(x) ((x) & (~BITS_DTIM_PERIOD_8822C)) +#define BIT_GET_DTIM_PERIOD_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD_8822C) & BIT_MASK_DTIM_PERIOD_8822C) +#define BIT_SET_DTIM_PERIOD_8822C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD_8822C(x) | BIT_DTIM_PERIOD_8822C(v)) + +#define BIT_DTIM_8822C BIT(15) +#define BIT_TIM_8822C BIT(14) +#define BIT_RPT_VALID_8822C BIT(13) + +#define BIT_SHIFT_PS_AID_0_8822C 0 +#define BIT_MASK_PS_AID_0_8822C 0x7ff +#define BIT_PS_AID_0_8822C(x) \ + (((x) & BIT_MASK_PS_AID_0_8822C) << BIT_SHIFT_PS_AID_0_8822C) +#define BITS_PS_AID_0_8822C \ + (BIT_MASK_PS_AID_0_8822C << BIT_SHIFT_PS_AID_0_8822C) +#define BIT_CLEAR_PS_AID_0_8822C(x) ((x) & (~BITS_PS_AID_0_8822C)) +#define BIT_GET_PS_AID_0_8822C(x) \ + (((x) >> BIT_SHIFT_PS_AID_0_8822C) & BIT_MASK_PS_AID_0_8822C) +#define BIT_SET_PS_AID_0_8822C(x, v) \ + (BIT_CLEAR_PS_AID_0_8822C(x) | BIT_PS_AID_0_8822C(v)) + +/* 2 REG_FLC_RPC_8822C (FW LPS CONDITION -- RX PKT COUNTER) */ + +#define BIT_SHIFT_FLC_RPC_8822C 0 +#define BIT_MASK_FLC_RPC_8822C 0xff +#define BIT_FLC_RPC_8822C(x) \ + (((x) & BIT_MASK_FLC_RPC_8822C) << BIT_SHIFT_FLC_RPC_8822C) +#define BITS_FLC_RPC_8822C (BIT_MASK_FLC_RPC_8822C << BIT_SHIFT_FLC_RPC_8822C) +#define BIT_CLEAR_FLC_RPC_8822C(x) ((x) & (~BITS_FLC_RPC_8822C)) +#define BIT_GET_FLC_RPC_8822C(x) \ + (((x) >> BIT_SHIFT_FLC_RPC_8822C) & BIT_MASK_FLC_RPC_8822C) +#define BIT_SET_FLC_RPC_8822C(x, v) \ + (BIT_CLEAR_FLC_RPC_8822C(x) | BIT_FLC_RPC_8822C(v)) + +/* 2 REG_FLC_RPCT_8822C (FLC_RPC THRESHOLD) */ + +#define BIT_SHIFT_FLC_RPCT_8822C 0 +#define BIT_MASK_FLC_RPCT_8822C 0xff +#define BIT_FLC_RPCT_8822C(x) \ + (((x) & BIT_MASK_FLC_RPCT_8822C) << BIT_SHIFT_FLC_RPCT_8822C) +#define BITS_FLC_RPCT_8822C \ + (BIT_MASK_FLC_RPCT_8822C << BIT_SHIFT_FLC_RPCT_8822C) +#define BIT_CLEAR_FLC_RPCT_8822C(x) ((x) & (~BITS_FLC_RPCT_8822C)) +#define BIT_GET_FLC_RPCT_8822C(x) \ + (((x) >> BIT_SHIFT_FLC_RPCT_8822C) & BIT_MASK_FLC_RPCT_8822C) +#define BIT_SET_FLC_RPCT_8822C(x, v) \ + (BIT_CLEAR_FLC_RPCT_8822C(x) | BIT_FLC_RPCT_8822C(v)) + +/* 2 REG_FLC_PTS_8822C (PKT TYPE SELECTION OF FLC_RPC T) */ +#define BIT_CMF_8822C BIT(2) +#define BIT_CCF_8822C BIT(1) +#define BIT_CDF_8822C BIT(0) + +/* 2 REG_FLC_TRPC_8822C (TIMER OF FLC_RPC) */ +#define BIT_FLC_RPCT_V1_8822C BIT(7) +#define BIT_MODE_8822C BIT(6) + +#define BIT_SHIFT_TRPCD_8822C 0 +#define BIT_MASK_TRPCD_8822C 0x3f +#define BIT_TRPCD_8822C(x) \ + (((x) & BIT_MASK_TRPCD_8822C) << BIT_SHIFT_TRPCD_8822C) +#define BITS_TRPCD_8822C (BIT_MASK_TRPCD_8822C << BIT_SHIFT_TRPCD_8822C) +#define BIT_CLEAR_TRPCD_8822C(x) ((x) & (~BITS_TRPCD_8822C)) +#define BIT_GET_TRPCD_8822C(x) \ + (((x) >> BIT_SHIFT_TRPCD_8822C) & BIT_MASK_TRPCD_8822C) +#define BIT_SET_TRPCD_8822C(x, v) \ + (BIT_CLEAR_TRPCD_8822C(x) | BIT_TRPCD_8822C(v)) + +/* 2 REG_RXPKTMON_CTRL_8822C */ + +#define BIT_SHIFT_RXBKQPKT_SEQ_8822C 20 +#define BIT_MASK_RXBKQPKT_SEQ_8822C 0xf +#define BIT_RXBKQPKT_SEQ_8822C(x) \ + (((x) & BIT_MASK_RXBKQPKT_SEQ_8822C) << BIT_SHIFT_RXBKQPKT_SEQ_8822C) +#define BITS_RXBKQPKT_SEQ_8822C \ + (BIT_MASK_RXBKQPKT_SEQ_8822C << BIT_SHIFT_RXBKQPKT_SEQ_8822C) +#define BIT_CLEAR_RXBKQPKT_SEQ_8822C(x) ((x) & (~BITS_RXBKQPKT_SEQ_8822C)) +#define BIT_GET_RXBKQPKT_SEQ_8822C(x) \ + (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822C) & BIT_MASK_RXBKQPKT_SEQ_8822C) +#define BIT_SET_RXBKQPKT_SEQ_8822C(x, v) \ + (BIT_CLEAR_RXBKQPKT_SEQ_8822C(x) | BIT_RXBKQPKT_SEQ_8822C(v)) + +#define BIT_SHIFT_RXBEQPKT_SEQ_8822C 16 +#define BIT_MASK_RXBEQPKT_SEQ_8822C 0xf +#define BIT_RXBEQPKT_SEQ_8822C(x) \ + (((x) & BIT_MASK_RXBEQPKT_SEQ_8822C) << BIT_SHIFT_RXBEQPKT_SEQ_8822C) +#define BITS_RXBEQPKT_SEQ_8822C \ + (BIT_MASK_RXBEQPKT_SEQ_8822C << BIT_SHIFT_RXBEQPKT_SEQ_8822C) +#define BIT_CLEAR_RXBEQPKT_SEQ_8822C(x) ((x) & (~BITS_RXBEQPKT_SEQ_8822C)) +#define BIT_GET_RXBEQPKT_SEQ_8822C(x) \ + (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822C) & BIT_MASK_RXBEQPKT_SEQ_8822C) +#define BIT_SET_RXBEQPKT_SEQ_8822C(x, v) \ + (BIT_CLEAR_RXBEQPKT_SEQ_8822C(x) | BIT_RXBEQPKT_SEQ_8822C(v)) + +#define BIT_SHIFT_RXVIQPKT_SEQ_8822C 12 +#define BIT_MASK_RXVIQPKT_SEQ_8822C 0xf +#define BIT_RXVIQPKT_SEQ_8822C(x) \ + (((x) & BIT_MASK_RXVIQPKT_SEQ_8822C) << BIT_SHIFT_RXVIQPKT_SEQ_8822C) +#define BITS_RXVIQPKT_SEQ_8822C \ + (BIT_MASK_RXVIQPKT_SEQ_8822C << BIT_SHIFT_RXVIQPKT_SEQ_8822C) +#define BIT_CLEAR_RXVIQPKT_SEQ_8822C(x) ((x) & (~BITS_RXVIQPKT_SEQ_8822C)) +#define BIT_GET_RXVIQPKT_SEQ_8822C(x) \ + (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822C) & BIT_MASK_RXVIQPKT_SEQ_8822C) +#define BIT_SET_RXVIQPKT_SEQ_8822C(x, v) \ + (BIT_CLEAR_RXVIQPKT_SEQ_8822C(x) | BIT_RXVIQPKT_SEQ_8822C(v)) + +#define BIT_SHIFT_RXVOQPKT_SEQ_8822C 8 +#define BIT_MASK_RXVOQPKT_SEQ_8822C 0xf +#define BIT_RXVOQPKT_SEQ_8822C(x) \ + (((x) & BIT_MASK_RXVOQPKT_SEQ_8822C) << BIT_SHIFT_RXVOQPKT_SEQ_8822C) +#define BITS_RXVOQPKT_SEQ_8822C \ + (BIT_MASK_RXVOQPKT_SEQ_8822C << BIT_SHIFT_RXVOQPKT_SEQ_8822C) +#define BIT_CLEAR_RXVOQPKT_SEQ_8822C(x) ((x) & (~BITS_RXVOQPKT_SEQ_8822C)) +#define BIT_GET_RXVOQPKT_SEQ_8822C(x) \ + (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822C) & BIT_MASK_RXVOQPKT_SEQ_8822C) +#define BIT_SET_RXVOQPKT_SEQ_8822C(x, v) \ + (BIT_CLEAR_RXVOQPKT_SEQ_8822C(x) | BIT_RXVOQPKT_SEQ_8822C(v)) + +#define BIT_RXBKQPKT_ERR_8822C BIT(7) +#define BIT_RXBEQPKT_ERR_8822C BIT(6) +#define BIT_RXVIQPKT_ERR_8822C BIT(5) +#define BIT_RXVOQPKT_ERR_8822C BIT(4) +#define BIT_RXDMA_MON_EN_8822C BIT(2) +#define BIT_RXPKT_MON_RST_8822C BIT(1) +#define BIT_RXPKT_MON_EN_8822C BIT(0) + +/* 2 REG_STATE_MON_8822C */ + +#define BIT_SHIFT_STATE_SEL_8822C 24 +#define BIT_MASK_STATE_SEL_8822C 0x1f +#define BIT_STATE_SEL_8822C(x) \ + (((x) & BIT_MASK_STATE_SEL_8822C) << BIT_SHIFT_STATE_SEL_8822C) +#define BITS_STATE_SEL_8822C \ + (BIT_MASK_STATE_SEL_8822C << BIT_SHIFT_STATE_SEL_8822C) +#define BIT_CLEAR_STATE_SEL_8822C(x) ((x) & (~BITS_STATE_SEL_8822C)) +#define BIT_GET_STATE_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_STATE_SEL_8822C) & BIT_MASK_STATE_SEL_8822C) +#define BIT_SET_STATE_SEL_8822C(x, v) \ + (BIT_CLEAR_STATE_SEL_8822C(x) | BIT_STATE_SEL_8822C(v)) + +#define BIT_SHIFT_STATE_INFO_8822C 8 +#define BIT_MASK_STATE_INFO_8822C 0xff +#define BIT_STATE_INFO_8822C(x) \ + (((x) & BIT_MASK_STATE_INFO_8822C) << BIT_SHIFT_STATE_INFO_8822C) +#define BITS_STATE_INFO_8822C \ + (BIT_MASK_STATE_INFO_8822C << BIT_SHIFT_STATE_INFO_8822C) +#define BIT_CLEAR_STATE_INFO_8822C(x) ((x) & (~BITS_STATE_INFO_8822C)) +#define BIT_GET_STATE_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_STATE_INFO_8822C) & BIT_MASK_STATE_INFO_8822C) +#define BIT_SET_STATE_INFO_8822C(x, v) \ + (BIT_CLEAR_STATE_INFO_8822C(x) | BIT_STATE_INFO_8822C(v)) + +#define BIT_UPD_NXT_STATE_8822C BIT(7) + +#define BIT_SHIFT_CUR_STATE_8822C 0 +#define BIT_MASK_CUR_STATE_8822C 0x7f +#define BIT_CUR_STATE_8822C(x) \ + (((x) & BIT_MASK_CUR_STATE_8822C) << BIT_SHIFT_CUR_STATE_8822C) +#define BITS_CUR_STATE_8822C \ + (BIT_MASK_CUR_STATE_8822C << BIT_SHIFT_CUR_STATE_8822C) +#define BIT_CLEAR_CUR_STATE_8822C(x) ((x) & (~BITS_CUR_STATE_8822C)) +#define BIT_GET_CUR_STATE_8822C(x) \ + (((x) >> BIT_SHIFT_CUR_STATE_8822C) & BIT_MASK_CUR_STATE_8822C) +#define BIT_SET_CUR_STATE_8822C(x, v) \ + (BIT_CLEAR_CUR_STATE_8822C(x) | BIT_CUR_STATE_8822C(v)) + +/* 2 REG_ERROR_MON_8822C */ +#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC_8822C BIT(23) +#define BIT_CSI_CHKSUM_ERROR_8822C BIT(22) +#define BIT_MACRX_ERR_4_8822C BIT(20) +#define BIT_MACRX_ERR_3_8822C BIT(19) +#define BIT_MACRX_ERR_2_8822C BIT(18) +#define BIT_MACRX_ERR_1_8822C BIT(17) +#define BIT_MACRX_ERR_0_8822C BIT(16) +#define BIT_WMAC_PRETX_ERRHDL_EN_8822C BIT(15) +#define BIT_MACTX_ERR_5_8822C BIT(5) +#define BIT_MACTX_ERR_4_8822C BIT(4) +#define BIT_MACTX_ERR_3_8822C BIT(3) +#define BIT_MACTX_ERR_2_8822C BIT(2) +#define BIT_MACTX_ERR_1_8822C BIT(1) +#define BIT_MACTX_ERR_0_8822C BIT(0) + +/* 2 REG_SEARCH_MACID_8822C */ +#define BIT_EN_TXRPTBUF_CLK_8822C BIT(31) + +#define BIT_SHIFT_INFO_INDEX_OFFSET_8822C 16 +#define BIT_MASK_INFO_INDEX_OFFSET_8822C 0x1fff +#define BIT_INFO_INDEX_OFFSET_8822C(x) \ + (((x) & BIT_MASK_INFO_INDEX_OFFSET_8822C) \ + << BIT_SHIFT_INFO_INDEX_OFFSET_8822C) +#define BITS_INFO_INDEX_OFFSET_8822C \ + (BIT_MASK_INFO_INDEX_OFFSET_8822C << BIT_SHIFT_INFO_INDEX_OFFSET_8822C) +#define BIT_CLEAR_INFO_INDEX_OFFSET_8822C(x) \ + ((x) & (~BITS_INFO_INDEX_OFFSET_8822C)) +#define BIT_GET_INFO_INDEX_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822C) & \ + BIT_MASK_INFO_INDEX_OFFSET_8822C) +#define BIT_SET_INFO_INDEX_OFFSET_8822C(x, v) \ + (BIT_CLEAR_INFO_INDEX_OFFSET_8822C(x) | BIT_INFO_INDEX_OFFSET_8822C(v)) + +#define BIT_WMAC_SRCH_FIFOFULL_8822C BIT(15) +#define BIT_DIS_INFOSRCH_8822C BIT(14) + +#define BIT_SHIFT_INFO_ADDR_OFFSET_8822C 0 +#define BIT_MASK_INFO_ADDR_OFFSET_8822C 0x1fff +#define BIT_INFO_ADDR_OFFSET_8822C(x) \ + (((x) & BIT_MASK_INFO_ADDR_OFFSET_8822C) \ + << BIT_SHIFT_INFO_ADDR_OFFSET_8822C) +#define BITS_INFO_ADDR_OFFSET_8822C \ + (BIT_MASK_INFO_ADDR_OFFSET_8822C << BIT_SHIFT_INFO_ADDR_OFFSET_8822C) +#define BIT_CLEAR_INFO_ADDR_OFFSET_8822C(x) \ + ((x) & (~BITS_INFO_ADDR_OFFSET_8822C)) +#define BIT_GET_INFO_ADDR_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822C) & \ + BIT_MASK_INFO_ADDR_OFFSET_8822C) +#define BIT_SET_INFO_ADDR_OFFSET_8822C(x, v) \ + (BIT_CLEAR_INFO_ADDR_OFFSET_8822C(x) | BIT_INFO_ADDR_OFFSET_8822C(v)) + +/* 2 REG_BT_COEX_TABLE_8822C (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_COEX_TABLE_1_8822C 0 +#define BIT_MASK_COEX_TABLE_1_8822C 0xffffffffL +#define BIT_COEX_TABLE_1_8822C(x) \ + (((x) & BIT_MASK_COEX_TABLE_1_8822C) << BIT_SHIFT_COEX_TABLE_1_8822C) +#define BITS_COEX_TABLE_1_8822C \ + (BIT_MASK_COEX_TABLE_1_8822C << BIT_SHIFT_COEX_TABLE_1_8822C) +#define BIT_CLEAR_COEX_TABLE_1_8822C(x) ((x) & (~BITS_COEX_TABLE_1_8822C)) +#define BIT_GET_COEX_TABLE_1_8822C(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_1_8822C) & BIT_MASK_COEX_TABLE_1_8822C) +#define BIT_SET_COEX_TABLE_1_8822C(x, v) \ + (BIT_CLEAR_COEX_TABLE_1_8822C(x) | BIT_COEX_TABLE_1_8822C(v)) + +/* 2 REG_BT_COEX_TABLE2_8822C (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_COEX_TABLE_2_8822C 0 +#define BIT_MASK_COEX_TABLE_2_8822C 0xffffffffL +#define BIT_COEX_TABLE_2_8822C(x) \ + (((x) & BIT_MASK_COEX_TABLE_2_8822C) << BIT_SHIFT_COEX_TABLE_2_8822C) +#define BITS_COEX_TABLE_2_8822C \ + (BIT_MASK_COEX_TABLE_2_8822C << BIT_SHIFT_COEX_TABLE_2_8822C) +#define BIT_CLEAR_COEX_TABLE_2_8822C(x) ((x) & (~BITS_COEX_TABLE_2_8822C)) +#define BIT_GET_COEX_TABLE_2_8822C(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_2_8822C) & BIT_MASK_COEX_TABLE_2_8822C) +#define BIT_SET_COEX_TABLE_2_8822C(x, v) \ + (BIT_CLEAR_COEX_TABLE_2_8822C(x) | BIT_COEX_TABLE_2_8822C(v)) + +/* 2 REG_BT_COEX_BREAK_TABLE_8822C (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_BREAK_TABLE_2_8822C 16 +#define BIT_MASK_BREAK_TABLE_2_8822C 0xffff +#define BIT_BREAK_TABLE_2_8822C(x) \ + (((x) & BIT_MASK_BREAK_TABLE_2_8822C) << BIT_SHIFT_BREAK_TABLE_2_8822C) +#define BITS_BREAK_TABLE_2_8822C \ + (BIT_MASK_BREAK_TABLE_2_8822C << BIT_SHIFT_BREAK_TABLE_2_8822C) +#define BIT_CLEAR_BREAK_TABLE_2_8822C(x) ((x) & (~BITS_BREAK_TABLE_2_8822C)) +#define BIT_GET_BREAK_TABLE_2_8822C(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_2_8822C) & BIT_MASK_BREAK_TABLE_2_8822C) +#define BIT_SET_BREAK_TABLE_2_8822C(x, v) \ + (BIT_CLEAR_BREAK_TABLE_2_8822C(x) | BIT_BREAK_TABLE_2_8822C(v)) + +#define BIT_SHIFT_BREAK_TABLE_1_8822C 0 +#define BIT_MASK_BREAK_TABLE_1_8822C 0xffff +#define BIT_BREAK_TABLE_1_8822C(x) \ + (((x) & BIT_MASK_BREAK_TABLE_1_8822C) << BIT_SHIFT_BREAK_TABLE_1_8822C) +#define BITS_BREAK_TABLE_1_8822C \ + (BIT_MASK_BREAK_TABLE_1_8822C << BIT_SHIFT_BREAK_TABLE_1_8822C) +#define BIT_CLEAR_BREAK_TABLE_1_8822C(x) ((x) & (~BITS_BREAK_TABLE_1_8822C)) +#define BIT_GET_BREAK_TABLE_1_8822C(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_1_8822C) & BIT_MASK_BREAK_TABLE_1_8822C) +#define BIT_SET_BREAK_TABLE_1_8822C(x, v) \ + (BIT_CLEAR_BREAK_TABLE_1_8822C(x) | BIT_BREAK_TABLE_1_8822C(v)) + +/* 2 REG_BT_COEX_TABLE_H_8822C (BT-COEXISTENCE CONTROL REGISTER) */ +#define BIT_PRI_MASK_RX_RESP_V1_8822C BIT(30) +#define BIT_PRI_MASK_RXOFDM_V1_8822C BIT(29) +#define BIT_PRI_MASK_RXCCK_V1_8822C BIT(28) + +#define BIT_SHIFT_PRI_MASK_TXAC_8822C 21 +#define BIT_MASK_PRI_MASK_TXAC_8822C 0x7f +#define BIT_PRI_MASK_TXAC_8822C(x) \ + (((x) & BIT_MASK_PRI_MASK_TXAC_8822C) << BIT_SHIFT_PRI_MASK_TXAC_8822C) +#define BITS_PRI_MASK_TXAC_8822C \ + (BIT_MASK_PRI_MASK_TXAC_8822C << BIT_SHIFT_PRI_MASK_TXAC_8822C) +#define BIT_CLEAR_PRI_MASK_TXAC_8822C(x) ((x) & (~BITS_PRI_MASK_TXAC_8822C)) +#define BIT_GET_PRI_MASK_TXAC_8822C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822C) & BIT_MASK_PRI_MASK_TXAC_8822C) +#define BIT_SET_PRI_MASK_TXAC_8822C(x, v) \ + (BIT_CLEAR_PRI_MASK_TXAC_8822C(x) | BIT_PRI_MASK_TXAC_8822C(v)) + +#define BIT_SHIFT_PRI_MASK_NAV_8822C 13 +#define BIT_MASK_PRI_MASK_NAV_8822C 0xff +#define BIT_PRI_MASK_NAV_8822C(x) \ + (((x) & BIT_MASK_PRI_MASK_NAV_8822C) << BIT_SHIFT_PRI_MASK_NAV_8822C) +#define BITS_PRI_MASK_NAV_8822C \ + (BIT_MASK_PRI_MASK_NAV_8822C << BIT_SHIFT_PRI_MASK_NAV_8822C) +#define BIT_CLEAR_PRI_MASK_NAV_8822C(x) ((x) & (~BITS_PRI_MASK_NAV_8822C)) +#define BIT_GET_PRI_MASK_NAV_8822C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NAV_8822C) & BIT_MASK_PRI_MASK_NAV_8822C) +#define BIT_SET_PRI_MASK_NAV_8822C(x, v) \ + (BIT_CLEAR_PRI_MASK_NAV_8822C(x) | BIT_PRI_MASK_NAV_8822C(v)) + +#define BIT_PRI_MASK_CCK_V1_8822C BIT(12) +#define BIT_PRI_MASK_OFDM_V1_8822C BIT(11) +#define BIT_PRI_MASK_RTY_V1_8822C BIT(10) + +#define BIT_SHIFT_PRI_MASK_NUM_8822C 6 +#define BIT_MASK_PRI_MASK_NUM_8822C 0xf +#define BIT_PRI_MASK_NUM_8822C(x) \ + (((x) & BIT_MASK_PRI_MASK_NUM_8822C) << BIT_SHIFT_PRI_MASK_NUM_8822C) +#define BITS_PRI_MASK_NUM_8822C \ + (BIT_MASK_PRI_MASK_NUM_8822C << BIT_SHIFT_PRI_MASK_NUM_8822C) +#define BIT_CLEAR_PRI_MASK_NUM_8822C(x) ((x) & (~BITS_PRI_MASK_NUM_8822C)) +#define BIT_GET_PRI_MASK_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NUM_8822C) & BIT_MASK_PRI_MASK_NUM_8822C) +#define BIT_SET_PRI_MASK_NUM_8822C(x, v) \ + (BIT_CLEAR_PRI_MASK_NUM_8822C(x) | BIT_PRI_MASK_NUM_8822C(v)) + +#define BIT_SHIFT_PRI_MASK_TYPE_8822C 2 +#define BIT_MASK_PRI_MASK_TYPE_8822C 0xf +#define BIT_PRI_MASK_TYPE_8822C(x) \ + (((x) & BIT_MASK_PRI_MASK_TYPE_8822C) << BIT_SHIFT_PRI_MASK_TYPE_8822C) +#define BITS_PRI_MASK_TYPE_8822C \ + (BIT_MASK_PRI_MASK_TYPE_8822C << BIT_SHIFT_PRI_MASK_TYPE_8822C) +#define BIT_CLEAR_PRI_MASK_TYPE_8822C(x) ((x) & (~BITS_PRI_MASK_TYPE_8822C)) +#define BIT_GET_PRI_MASK_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822C) & BIT_MASK_PRI_MASK_TYPE_8822C) +#define BIT_SET_PRI_MASK_TYPE_8822C(x, v) \ + (BIT_CLEAR_PRI_MASK_TYPE_8822C(x) | BIT_PRI_MASK_TYPE_8822C(v)) + +#define BIT_OOB_V1_8822C BIT(1) +#define BIT_ANT_SEL_V1_8822C BIT(0) + +/* 2 REG_RXCMD_0_8822C */ +#define BIT_RXCMD_EN_8822C BIT(31) + +#define BIT_SHIFT_RXCMD_INFO_8822C 0 +#define BIT_MASK_RXCMD_INFO_8822C 0x7fffffffL +#define BIT_RXCMD_INFO_8822C(x) \ + (((x) & BIT_MASK_RXCMD_INFO_8822C) << BIT_SHIFT_RXCMD_INFO_8822C) +#define BITS_RXCMD_INFO_8822C \ + (BIT_MASK_RXCMD_INFO_8822C << BIT_SHIFT_RXCMD_INFO_8822C) +#define BIT_CLEAR_RXCMD_INFO_8822C(x) ((x) & (~BITS_RXCMD_INFO_8822C)) +#define BIT_GET_RXCMD_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_RXCMD_INFO_8822C) & BIT_MASK_RXCMD_INFO_8822C) +#define BIT_SET_RXCMD_INFO_8822C(x, v) \ + (BIT_CLEAR_RXCMD_INFO_8822C(x) | BIT_RXCMD_INFO_8822C(v)) + +/* 2 REG_RXCMD_1_8822C */ + +#define BIT_SHIFT_RXCMD_PRD_8822C 0 +#define BIT_MASK_RXCMD_PRD_8822C 0xffff +#define BIT_RXCMD_PRD_8822C(x) \ + (((x) & BIT_MASK_RXCMD_PRD_8822C) << BIT_SHIFT_RXCMD_PRD_8822C) +#define BITS_RXCMD_PRD_8822C \ + (BIT_MASK_RXCMD_PRD_8822C << BIT_SHIFT_RXCMD_PRD_8822C) +#define BIT_CLEAR_RXCMD_PRD_8822C(x) ((x) & (~BITS_RXCMD_PRD_8822C)) +#define BIT_GET_RXCMD_PRD_8822C(x) \ + (((x) >> BIT_SHIFT_RXCMD_PRD_8822C) & BIT_MASK_RXCMD_PRD_8822C) +#define BIT_SET_RXCMD_PRD_8822C(x, v) \ + (BIT_CLEAR_RXCMD_PRD_8822C(x) | BIT_RXCMD_PRD_8822C(v)) + +/* 2 REG_WMAC_RESP_TXINFO_8822C (RESPONSE TXINFO REGISTER) */ + +#define BIT_SHIFT_WMAC_RESP_MFB_8822C 25 +#define BIT_MASK_WMAC_RESP_MFB_8822C 0x7f +#define BIT_WMAC_RESP_MFB_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_MFB_8822C) << BIT_SHIFT_WMAC_RESP_MFB_8822C) +#define BITS_WMAC_RESP_MFB_8822C \ + (BIT_MASK_WMAC_RESP_MFB_8822C << BIT_SHIFT_WMAC_RESP_MFB_8822C) +#define BIT_CLEAR_WMAC_RESP_MFB_8822C(x) ((x) & (~BITS_WMAC_RESP_MFB_8822C)) +#define BIT_GET_WMAC_RESP_MFB_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822C) & BIT_MASK_WMAC_RESP_MFB_8822C) +#define BIT_SET_WMAC_RESP_MFB_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_MFB_8822C(x) | BIT_WMAC_RESP_MFB_8822C(v)) + +#define BIT_SHIFT_WMAC_ANTINF_SEL_8822C 23 +#define BIT_MASK_WMAC_ANTINF_SEL_8822C 0x3 +#define BIT_WMAC_ANTINF_SEL_8822C(x) \ + (((x) & BIT_MASK_WMAC_ANTINF_SEL_8822C) \ + << BIT_SHIFT_WMAC_ANTINF_SEL_8822C) +#define BITS_WMAC_ANTINF_SEL_8822C \ + (BIT_MASK_WMAC_ANTINF_SEL_8822C << BIT_SHIFT_WMAC_ANTINF_SEL_8822C) +#define BIT_CLEAR_WMAC_ANTINF_SEL_8822C(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8822C)) +#define BIT_GET_WMAC_ANTINF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822C) & \ + BIT_MASK_WMAC_ANTINF_SEL_8822C) +#define BIT_SET_WMAC_ANTINF_SEL_8822C(x, v) \ + (BIT_CLEAR_WMAC_ANTINF_SEL_8822C(x) | BIT_WMAC_ANTINF_SEL_8822C(v)) + +#define BIT_SHIFT_WMAC_ANTSEL_SEL_8822C 21 +#define BIT_MASK_WMAC_ANTSEL_SEL_8822C 0x3 +#define BIT_WMAC_ANTSEL_SEL_8822C(x) \ + (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822C) \ + << BIT_SHIFT_WMAC_ANTSEL_SEL_8822C) +#define BITS_WMAC_ANTSEL_SEL_8822C \ + (BIT_MASK_WMAC_ANTSEL_SEL_8822C << BIT_SHIFT_WMAC_ANTSEL_SEL_8822C) +#define BIT_CLEAR_WMAC_ANTSEL_SEL_8822C(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8822C)) +#define BIT_GET_WMAC_ANTSEL_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822C) & \ + BIT_MASK_WMAC_ANTSEL_SEL_8822C) +#define BIT_SET_WMAC_ANTSEL_SEL_8822C(x, v) \ + (BIT_CLEAR_WMAC_ANTSEL_SEL_8822C(x) | BIT_WMAC_ANTSEL_SEL_8822C(v)) + +#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C 18 +#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C 0x3 +#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) \ + << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) +#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C \ + (BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C \ + << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) +#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) \ + ((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)) +#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) & \ + BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) +#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) | \ + BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(v)) + +#define BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C 6 +#define BIT_MASK_WMAC_RESP_TXANT_V1_8822C 0xfff +#define BIT_WMAC_RESP_TXANT_V1_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT_V1_8822C) \ + << BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C) +#define BITS_WMAC_RESP_TXANT_V1_8822C \ + (BIT_MASK_WMAC_RESP_TXANT_V1_8822C \ + << BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C) +#define BIT_CLEAR_WMAC_RESP_TXANT_V1_8822C(x) \ + ((x) & (~BITS_WMAC_RESP_TXANT_V1_8822C)) +#define BIT_GET_WMAC_RESP_TXANT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C) & \ + BIT_MASK_WMAC_RESP_TXANT_V1_8822C) +#define BIT_SET_WMAC_RESP_TXANT_V1_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT_V1_8822C(x) | \ + BIT_WMAC_RESP_TXANT_V1_8822C(v)) + +/* 2 REG_BBPSF_CTRL_8822C */ +#define BIT_CTL_IDLE_CLR_CSI_RPT_8822C BIT(31) +#define BIT_WMAC_USE_NDPARATE_8822C BIT(30) + +#define BIT_SHIFT_WMAC_CSI_RATE_8822C 24 +#define BIT_MASK_WMAC_CSI_RATE_8822C 0x3f +#define BIT_WMAC_CSI_RATE_8822C(x) \ + (((x) & BIT_MASK_WMAC_CSI_RATE_8822C) << BIT_SHIFT_WMAC_CSI_RATE_8822C) +#define BITS_WMAC_CSI_RATE_8822C \ + (BIT_MASK_WMAC_CSI_RATE_8822C << BIT_SHIFT_WMAC_CSI_RATE_8822C) +#define BIT_CLEAR_WMAC_CSI_RATE_8822C(x) ((x) & (~BITS_WMAC_CSI_RATE_8822C)) +#define BIT_GET_WMAC_CSI_RATE_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822C) & BIT_MASK_WMAC_CSI_RATE_8822C) +#define BIT_SET_WMAC_CSI_RATE_8822C(x, v) \ + (BIT_CLEAR_WMAC_CSI_RATE_8822C(x) | BIT_WMAC_CSI_RATE_8822C(v)) + +#define BIT_SHIFT_WMAC_RESP_TXRATE_8822C 16 +#define BIT_MASK_WMAC_RESP_TXRATE_8822C 0xff +#define BIT_WMAC_RESP_TXRATE_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXRATE_8822C) \ + << BIT_SHIFT_WMAC_RESP_TXRATE_8822C) +#define BITS_WMAC_RESP_TXRATE_8822C \ + (BIT_MASK_WMAC_RESP_TXRATE_8822C << BIT_SHIFT_WMAC_RESP_TXRATE_8822C) +#define BIT_CLEAR_WMAC_RESP_TXRATE_8822C(x) \ + ((x) & (~BITS_WMAC_RESP_TXRATE_8822C)) +#define BIT_GET_WMAC_RESP_TXRATE_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822C) & \ + BIT_MASK_WMAC_RESP_TXRATE_8822C) +#define BIT_SET_WMAC_RESP_TXRATE_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXRATE_8822C(x) | BIT_WMAC_RESP_TXRATE_8822C(v)) + +#define BIT_SHIFT_CSI_RSC_8822C 13 +#define BIT_MASK_CSI_RSC_8822C 0x3 +#define BIT_CSI_RSC_8822C(x) \ + (((x) & BIT_MASK_CSI_RSC_8822C) << BIT_SHIFT_CSI_RSC_8822C) +#define BITS_CSI_RSC_8822C (BIT_MASK_CSI_RSC_8822C << BIT_SHIFT_CSI_RSC_8822C) +#define BIT_CLEAR_CSI_RSC_8822C(x) ((x) & (~BITS_CSI_RSC_8822C)) +#define BIT_GET_CSI_RSC_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_RSC_8822C) & BIT_MASK_CSI_RSC_8822C) +#define BIT_SET_CSI_RSC_8822C(x, v) \ + (BIT_CLEAR_CSI_RSC_8822C(x) | BIT_CSI_RSC_8822C(v)) + +#define BIT_CSI_GID_SEL_8822C BIT(12) +#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8822C BIT(9) +#define BIT_RDCSI_EMPTY_APPZERO_8822C BIT(8) +#define BIT_CSI_RATE_FB_EN_8822C BIT(7) +#define BIT_RXFIFO_WRPTR_WO_CHKSUM_8822C BIT(6) + +/* 2 REG_P2P_RX_BCN_NOA_8822C (P2P RX BEACON NOA REGISTER) */ +#define BIT_NOA_PARSER_EN_8822C BIT(15) + +#define BIT_SHIFT_BSSID_SEL_V1_8822C 12 +#define BIT_MASK_BSSID_SEL_V1_8822C 0x7 +#define BIT_BSSID_SEL_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID_SEL_V1_8822C) << BIT_SHIFT_BSSID_SEL_V1_8822C) +#define BITS_BSSID_SEL_V1_8822C \ + (BIT_MASK_BSSID_SEL_V1_8822C << BIT_SHIFT_BSSID_SEL_V1_8822C) +#define BIT_CLEAR_BSSID_SEL_V1_8822C(x) ((x) & (~BITS_BSSID_SEL_V1_8822C)) +#define BIT_GET_BSSID_SEL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID_SEL_V1_8822C) & BIT_MASK_BSSID_SEL_V1_8822C) +#define BIT_SET_BSSID_SEL_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID_SEL_V1_8822C(x) | BIT_BSSID_SEL_V1_8822C(v)) + +#define BIT_SHIFT_P2P_OUI_TYPE_8822C 0 +#define BIT_MASK_P2P_OUI_TYPE_8822C 0xff +#define BIT_P2P_OUI_TYPE_8822C(x) \ + (((x) & BIT_MASK_P2P_OUI_TYPE_8822C) << BIT_SHIFT_P2P_OUI_TYPE_8822C) +#define BITS_P2P_OUI_TYPE_8822C \ + (BIT_MASK_P2P_OUI_TYPE_8822C << BIT_SHIFT_P2P_OUI_TYPE_8822C) +#define BIT_CLEAR_P2P_OUI_TYPE_8822C(x) ((x) & (~BITS_P2P_OUI_TYPE_8822C)) +#define BIT_GET_P2P_OUI_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822C) & BIT_MASK_P2P_OUI_TYPE_8822C) +#define BIT_SET_P2P_OUI_TYPE_8822C(x, v) \ + (BIT_CLEAR_P2P_OUI_TYPE_8822C(x) | BIT_P2P_OUI_TYPE_8822C(v)) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_ASSOCIATED_BFMER0_INFO_8822C (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8822C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(v)) + +/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8822C */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C 16 +#define BIT_MASK_R_WMAC_TXCSI_AID0_8822C 0x1ff +#define BIT_R_WMAC_TXCSI_AID0_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822C) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C) +#define BITS_R_WMAC_TXCSI_AID0_8822C \ + (BIT_MASK_R_WMAC_TXCSI_AID0_8822C << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C) +#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8822C(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID0_8822C)) +#define BIT_GET_R_WMAC_TXCSI_AID0_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C) & \ + BIT_MASK_R_WMAC_TXCSI_AID0_8822C) +#define BIT_SET_R_WMAC_TXCSI_AID0_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID0_8822C(x) | BIT_R_WMAC_TXCSI_AID0_8822C(v)) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(v)) + +/* 2 REG_ASSOCIATED_BFMER1_INFO_8822C (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8822C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(v)) + +/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8822C */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C 16 +#define BIT_MASK_R_WMAC_TXCSI_AID1_8822C 0x1ff +#define BIT_R_WMAC_TXCSI_AID1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822C) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C) +#define BITS_R_WMAC_TXCSI_AID1_8822C \ + (BIT_MASK_R_WMAC_TXCSI_AID1_8822C << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C) +#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8822C(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID1_8822C)) +#define BIT_GET_R_WMAC_TXCSI_AID1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C) & \ + BIT_MASK_R_WMAC_TXCSI_AID1_8822C) +#define BIT_SET_R_WMAC_TXCSI_AID1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID1_8822C(x) | BIT_R_WMAC_TXCSI_AID1_8822C(v)) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(v)) + +/* 2 REG_TX_CSI_RPT_PARAM_BW20_8822C (TX CSI REPORT PARAMETER REGISTER) */ + +#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C 16 +#define BIT_MASK_R_WMAC_BFINFO_20M_1_8822C 0xfff +#define BIT_R_WMAC_BFINFO_20M_1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822C) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C) +#define BITS_R_WMAC_BFINFO_20M_1_8822C \ + (BIT_MASK_R_WMAC_BFINFO_20M_1_8822C \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822C(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8822C)) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C) & \ + BIT_MASK_R_WMAC_BFINFO_20M_1_8822C) +#define BIT_SET_R_WMAC_BFINFO_20M_1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822C(x) | \ + BIT_R_WMAC_BFINFO_20M_1_8822C(v)) + +#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C 0 +#define BIT_MASK_R_WMAC_BFINFO_20M_0_8822C 0xfff +#define BIT_R_WMAC_BFINFO_20M_0_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822C) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C) +#define BITS_R_WMAC_BFINFO_20M_0_8822C \ + (BIT_MASK_R_WMAC_BFINFO_20M_0_8822C \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822C(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8822C)) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C) & \ + BIT_MASK_R_WMAC_BFINFO_20M_0_8822C) +#define BIT_SET_R_WMAC_BFINFO_20M_0_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822C(x) | \ + BIT_R_WMAC_BFINFO_20M_0_8822C(v)) + +/* 2 REG_TX_CSI_RPT_PARAM_BW40_8822C (TX CSI REPORT PARAMETER_BW40 REGISTER) */ + +#define BIT_SHIFT_WMAC_RESP_ANTD_8822C 12 +#define BIT_MASK_WMAC_RESP_ANTD_8822C 0xf +#define BIT_WMAC_RESP_ANTD_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTD_8822C) \ + << BIT_SHIFT_WMAC_RESP_ANTD_8822C) +#define BITS_WMAC_RESP_ANTD_8822C \ + (BIT_MASK_WMAC_RESP_ANTD_8822C << BIT_SHIFT_WMAC_RESP_ANTD_8822C) +#define BIT_CLEAR_WMAC_RESP_ANTD_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTD_8822C)) +#define BIT_GET_WMAC_RESP_ANTD_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTD_8822C) & \ + BIT_MASK_WMAC_RESP_ANTD_8822C) +#define BIT_SET_WMAC_RESP_ANTD_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTD_8822C(x) | BIT_WMAC_RESP_ANTD_8822C(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTC_8822C 8 +#define BIT_MASK_WMAC_RESP_ANTC_8822C 0xf +#define BIT_WMAC_RESP_ANTC_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTC_8822C) \ + << BIT_SHIFT_WMAC_RESP_ANTC_8822C) +#define BITS_WMAC_RESP_ANTC_8822C \ + (BIT_MASK_WMAC_RESP_ANTC_8822C << BIT_SHIFT_WMAC_RESP_ANTC_8822C) +#define BIT_CLEAR_WMAC_RESP_ANTC_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTC_8822C)) +#define BIT_GET_WMAC_RESP_ANTC_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTC_8822C) & \ + BIT_MASK_WMAC_RESP_ANTC_8822C) +#define BIT_SET_WMAC_RESP_ANTC_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTC_8822C(x) | BIT_WMAC_RESP_ANTC_8822C(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTB_8822C 4 +#define BIT_MASK_WMAC_RESP_ANTB_8822C 0xf +#define BIT_WMAC_RESP_ANTB_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTB_8822C) \ + << BIT_SHIFT_WMAC_RESP_ANTB_8822C) +#define BITS_WMAC_RESP_ANTB_8822C \ + (BIT_MASK_WMAC_RESP_ANTB_8822C << BIT_SHIFT_WMAC_RESP_ANTB_8822C) +#define BIT_CLEAR_WMAC_RESP_ANTB_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTB_8822C)) +#define BIT_GET_WMAC_RESP_ANTB_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTB_8822C) & \ + BIT_MASK_WMAC_RESP_ANTB_8822C) +#define BIT_SET_WMAC_RESP_ANTB_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTB_8822C(x) | BIT_WMAC_RESP_ANTB_8822C(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTA_8822C 0 +#define BIT_MASK_WMAC_RESP_ANTA_8822C 0xf +#define BIT_WMAC_RESP_ANTA_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTA_8822C) \ + << BIT_SHIFT_WMAC_RESP_ANTA_8822C) +#define BITS_WMAC_RESP_ANTA_8822C \ + (BIT_MASK_WMAC_RESP_ANTA_8822C << BIT_SHIFT_WMAC_RESP_ANTA_8822C) +#define BIT_CLEAR_WMAC_RESP_ANTA_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTA_8822C)) +#define BIT_GET_WMAC_RESP_ANTA_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTA_8822C) & \ + BIT_MASK_WMAC_RESP_ANTA_8822C) +#define BIT_SET_WMAC_RESP_ANTA_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTA_8822C(x) | BIT_WMAC_RESP_ANTA_8822C(v)) + +/* 2 REG_CSI_PTR_8822C */ + +#define BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C 16 +#define BIT_MASK_CSI_RADDR_LATCH_V2_8822C 0xffff +#define BIT_CSI_RADDR_LATCH_V2_8822C(x) \ + (((x) & BIT_MASK_CSI_RADDR_LATCH_V2_8822C) \ + << BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C) +#define BITS_CSI_RADDR_LATCH_V2_8822C \ + (BIT_MASK_CSI_RADDR_LATCH_V2_8822C \ + << BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C) +#define BIT_CLEAR_CSI_RADDR_LATCH_V2_8822C(x) \ + ((x) & (~BITS_CSI_RADDR_LATCH_V2_8822C)) +#define BIT_GET_CSI_RADDR_LATCH_V2_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C) & \ + BIT_MASK_CSI_RADDR_LATCH_V2_8822C) +#define BIT_SET_CSI_RADDR_LATCH_V2_8822C(x, v) \ + (BIT_CLEAR_CSI_RADDR_LATCH_V2_8822C(x) | \ + BIT_CSI_RADDR_LATCH_V2_8822C(v)) + +#define BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C 0 +#define BIT_MASK_CSI_WADDR_LATCH_V2_8822C 0xffff +#define BIT_CSI_WADDR_LATCH_V2_8822C(x) \ + (((x) & BIT_MASK_CSI_WADDR_LATCH_V2_8822C) \ + << BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C) +#define BITS_CSI_WADDR_LATCH_V2_8822C \ + (BIT_MASK_CSI_WADDR_LATCH_V2_8822C \ + << BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C) +#define BIT_CLEAR_CSI_WADDR_LATCH_V2_8822C(x) \ + ((x) & (~BITS_CSI_WADDR_LATCH_V2_8822C)) +#define BIT_GET_CSI_WADDR_LATCH_V2_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C) & \ + BIT_MASK_CSI_WADDR_LATCH_V2_8822C) +#define BIT_SET_CSI_WADDR_LATCH_V2_8822C(x, v) \ + (BIT_CLEAR_CSI_WADDR_LATCH_V2_8822C(x) | \ + BIT_CSI_WADDR_LATCH_V2_8822C(v)) + +/* 2 REG_BCN_PSR_RPT2_8822C (BEACON PARSER REPORT REGISTER2) */ + +#define BIT_SHIFT_DTIM_CNT2_8822C 24 +#define BIT_MASK_DTIM_CNT2_8822C 0xff +#define BIT_DTIM_CNT2_8822C(x) \ + (((x) & BIT_MASK_DTIM_CNT2_8822C) << BIT_SHIFT_DTIM_CNT2_8822C) +#define BITS_DTIM_CNT2_8822C \ + (BIT_MASK_DTIM_CNT2_8822C << BIT_SHIFT_DTIM_CNT2_8822C) +#define BIT_CLEAR_DTIM_CNT2_8822C(x) ((x) & (~BITS_DTIM_CNT2_8822C)) +#define BIT_GET_DTIM_CNT2_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT2_8822C) & BIT_MASK_DTIM_CNT2_8822C) +#define BIT_SET_DTIM_CNT2_8822C(x, v) \ + (BIT_CLEAR_DTIM_CNT2_8822C(x) | BIT_DTIM_CNT2_8822C(v)) + +#define BIT_SHIFT_DTIM_PERIOD2_8822C 16 +#define BIT_MASK_DTIM_PERIOD2_8822C 0xff +#define BIT_DTIM_PERIOD2_8822C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD2_8822C) << BIT_SHIFT_DTIM_PERIOD2_8822C) +#define BITS_DTIM_PERIOD2_8822C \ + (BIT_MASK_DTIM_PERIOD2_8822C << BIT_SHIFT_DTIM_PERIOD2_8822C) +#define BIT_CLEAR_DTIM_PERIOD2_8822C(x) ((x) & (~BITS_DTIM_PERIOD2_8822C)) +#define BIT_GET_DTIM_PERIOD2_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD2_8822C) & BIT_MASK_DTIM_PERIOD2_8822C) +#define BIT_SET_DTIM_PERIOD2_8822C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD2_8822C(x) | BIT_DTIM_PERIOD2_8822C(v)) + +#define BIT_DTIM2_8822C BIT(15) +#define BIT_TIM2_8822C BIT(14) +#define BIT_RPT_VALID_8822C BIT(13) + +#define BIT_SHIFT_PS_AID_2_8822C 0 +#define BIT_MASK_PS_AID_2_8822C 0x7ff +#define BIT_PS_AID_2_8822C(x) \ + (((x) & BIT_MASK_PS_AID_2_8822C) << BIT_SHIFT_PS_AID_2_8822C) +#define BITS_PS_AID_2_8822C \ + (BIT_MASK_PS_AID_2_8822C << BIT_SHIFT_PS_AID_2_8822C) +#define BIT_CLEAR_PS_AID_2_8822C(x) ((x) & (~BITS_PS_AID_2_8822C)) +#define BIT_GET_PS_AID_2_8822C(x) \ + (((x) >> BIT_SHIFT_PS_AID_2_8822C) & BIT_MASK_PS_AID_2_8822C) +#define BIT_SET_PS_AID_2_8822C(x, v) \ + (BIT_CLEAR_PS_AID_2_8822C(x) | BIT_PS_AID_2_8822C(v)) + +/* 2 REG_BCN_PSR_RPT3_8822C (BEACON PARSER REPORT REGISTER3) */ + +#define BIT_SHIFT_DTIM_CNT3_8822C 24 +#define BIT_MASK_DTIM_CNT3_8822C 0xff +#define BIT_DTIM_CNT3_8822C(x) \ + (((x) & BIT_MASK_DTIM_CNT3_8822C) << BIT_SHIFT_DTIM_CNT3_8822C) +#define BITS_DTIM_CNT3_8822C \ + (BIT_MASK_DTIM_CNT3_8822C << BIT_SHIFT_DTIM_CNT3_8822C) +#define BIT_CLEAR_DTIM_CNT3_8822C(x) ((x) & (~BITS_DTIM_CNT3_8822C)) +#define BIT_GET_DTIM_CNT3_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT3_8822C) & BIT_MASK_DTIM_CNT3_8822C) +#define BIT_SET_DTIM_CNT3_8822C(x, v) \ + (BIT_CLEAR_DTIM_CNT3_8822C(x) | BIT_DTIM_CNT3_8822C(v)) + +#define BIT_SHIFT_DTIM_PERIOD3_8822C 16 +#define BIT_MASK_DTIM_PERIOD3_8822C 0xff +#define BIT_DTIM_PERIOD3_8822C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD3_8822C) << BIT_SHIFT_DTIM_PERIOD3_8822C) +#define BITS_DTIM_PERIOD3_8822C \ + (BIT_MASK_DTIM_PERIOD3_8822C << BIT_SHIFT_DTIM_PERIOD3_8822C) +#define BIT_CLEAR_DTIM_PERIOD3_8822C(x) ((x) & (~BITS_DTIM_PERIOD3_8822C)) +#define BIT_GET_DTIM_PERIOD3_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD3_8822C) & BIT_MASK_DTIM_PERIOD3_8822C) +#define BIT_SET_DTIM_PERIOD3_8822C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD3_8822C(x) | BIT_DTIM_PERIOD3_8822C(v)) + +#define BIT_DTIM3_8822C BIT(15) +#define BIT_TIM3_8822C BIT(14) +#define BIT_RPT_VALID_8822C BIT(13) + +#define BIT_SHIFT_PS_AID_3_8822C 0 +#define BIT_MASK_PS_AID_3_8822C 0x7ff +#define BIT_PS_AID_3_8822C(x) \ + (((x) & BIT_MASK_PS_AID_3_8822C) << BIT_SHIFT_PS_AID_3_8822C) +#define BITS_PS_AID_3_8822C \ + (BIT_MASK_PS_AID_3_8822C << BIT_SHIFT_PS_AID_3_8822C) +#define BIT_CLEAR_PS_AID_3_8822C(x) ((x) & (~BITS_PS_AID_3_8822C)) +#define BIT_GET_PS_AID_3_8822C(x) \ + (((x) >> BIT_SHIFT_PS_AID_3_8822C) & BIT_MASK_PS_AID_3_8822C) +#define BIT_SET_PS_AID_3_8822C(x, v) \ + (BIT_CLEAR_PS_AID_3_8822C(x) | BIT_PS_AID_3_8822C(v)) + +/* 2 REG_BCN_PSR_RPT4_8822C (BEACON PARSER REPORT REGISTER4) */ + +#define BIT_SHIFT_DTIM_CNT4_8822C 24 +#define BIT_MASK_DTIM_CNT4_8822C 0xff +#define BIT_DTIM_CNT4_8822C(x) \ + (((x) & BIT_MASK_DTIM_CNT4_8822C) << BIT_SHIFT_DTIM_CNT4_8822C) +#define BITS_DTIM_CNT4_8822C \ + (BIT_MASK_DTIM_CNT4_8822C << BIT_SHIFT_DTIM_CNT4_8822C) +#define BIT_CLEAR_DTIM_CNT4_8822C(x) ((x) & (~BITS_DTIM_CNT4_8822C)) +#define BIT_GET_DTIM_CNT4_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT4_8822C) & BIT_MASK_DTIM_CNT4_8822C) +#define BIT_SET_DTIM_CNT4_8822C(x, v) \ + (BIT_CLEAR_DTIM_CNT4_8822C(x) | BIT_DTIM_CNT4_8822C(v)) + +#define BIT_SHIFT_DTIM_PERIOD4_8822C 16 +#define BIT_MASK_DTIM_PERIOD4_8822C 0xff +#define BIT_DTIM_PERIOD4_8822C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD4_8822C) << BIT_SHIFT_DTIM_PERIOD4_8822C) +#define BITS_DTIM_PERIOD4_8822C \ + (BIT_MASK_DTIM_PERIOD4_8822C << BIT_SHIFT_DTIM_PERIOD4_8822C) +#define BIT_CLEAR_DTIM_PERIOD4_8822C(x) ((x) & (~BITS_DTIM_PERIOD4_8822C)) +#define BIT_GET_DTIM_PERIOD4_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD4_8822C) & BIT_MASK_DTIM_PERIOD4_8822C) +#define BIT_SET_DTIM_PERIOD4_8822C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD4_8822C(x) | BIT_DTIM_PERIOD4_8822C(v)) + +#define BIT_DTIM4_8822C BIT(15) +#define BIT_TIM4_8822C BIT(14) +#define BIT_RPT_VALID_8822C BIT(13) + +#define BIT_SHIFT_PS_AID_4_8822C 0 +#define BIT_MASK_PS_AID_4_8822C 0x7ff +#define BIT_PS_AID_4_8822C(x) \ + (((x) & BIT_MASK_PS_AID_4_8822C) << BIT_SHIFT_PS_AID_4_8822C) +#define BITS_PS_AID_4_8822C \ + (BIT_MASK_PS_AID_4_8822C << BIT_SHIFT_PS_AID_4_8822C) +#define BIT_CLEAR_PS_AID_4_8822C(x) ((x) & (~BITS_PS_AID_4_8822C)) +#define BIT_GET_PS_AID_4_8822C(x) \ + (((x) >> BIT_SHIFT_PS_AID_4_8822C) & BIT_MASK_PS_AID_4_8822C) +#define BIT_SET_PS_AID_4_8822C(x, v) \ + (BIT_CLEAR_PS_AID_4_8822C(x) | BIT_PS_AID_4_8822C(v)) + +/* 2 REG_A1_ADDR_MASK_8822C (A1 ADDR MASK REGISTER) */ + +#define BIT_SHIFT_A1_ADDR_MASK_8822C 0 +#define BIT_MASK_A1_ADDR_MASK_8822C 0xffffffffL +#define BIT_A1_ADDR_MASK_8822C(x) \ + (((x) & BIT_MASK_A1_ADDR_MASK_8822C) << BIT_SHIFT_A1_ADDR_MASK_8822C) +#define BITS_A1_ADDR_MASK_8822C \ + (BIT_MASK_A1_ADDR_MASK_8822C << BIT_SHIFT_A1_ADDR_MASK_8822C) +#define BIT_CLEAR_A1_ADDR_MASK_8822C(x) ((x) & (~BITS_A1_ADDR_MASK_8822C)) +#define BIT_GET_A1_ADDR_MASK_8822C(x) \ + (((x) >> BIT_SHIFT_A1_ADDR_MASK_8822C) & BIT_MASK_A1_ADDR_MASK_8822C) +#define BIT_SET_A1_ADDR_MASK_8822C(x, v) \ + (BIT_CLEAR_A1_ADDR_MASK_8822C(x) | BIT_A1_ADDR_MASK_8822C(v)) + +/* 2 REG_RXPSF_CTRL_8822C */ +#define BIT_RXGCK_FIFOTHR_EN_8822C BIT(28) + +#define BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C 26 +#define BIT_MASK_RXGCK_VHT_FIFOTHR_8822C 0x3 +#define BIT_RXGCK_VHT_FIFOTHR_8822C(x) \ + (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR_8822C) \ + << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C) +#define BITS_RXGCK_VHT_FIFOTHR_8822C \ + (BIT_MASK_RXGCK_VHT_FIFOTHR_8822C << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C) +#define BIT_CLEAR_RXGCK_VHT_FIFOTHR_8822C(x) \ + ((x) & (~BITS_RXGCK_VHT_FIFOTHR_8822C)) +#define BIT_GET_RXGCK_VHT_FIFOTHR_8822C(x) \ + (((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C) & \ + BIT_MASK_RXGCK_VHT_FIFOTHR_8822C) +#define BIT_SET_RXGCK_VHT_FIFOTHR_8822C(x, v) \ + (BIT_CLEAR_RXGCK_VHT_FIFOTHR_8822C(x) | BIT_RXGCK_VHT_FIFOTHR_8822C(v)) + +#define BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C 24 +#define BIT_MASK_RXGCK_HT_FIFOTHR_8822C 0x3 +#define BIT_RXGCK_HT_FIFOTHR_8822C(x) \ + (((x) & BIT_MASK_RXGCK_HT_FIFOTHR_8822C) \ + << BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C) +#define BITS_RXGCK_HT_FIFOTHR_8822C \ + (BIT_MASK_RXGCK_HT_FIFOTHR_8822C << BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C) +#define BIT_CLEAR_RXGCK_HT_FIFOTHR_8822C(x) \ + ((x) & (~BITS_RXGCK_HT_FIFOTHR_8822C)) +#define BIT_GET_RXGCK_HT_FIFOTHR_8822C(x) \ + (((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C) & \ + BIT_MASK_RXGCK_HT_FIFOTHR_8822C) +#define BIT_SET_RXGCK_HT_FIFOTHR_8822C(x, v) \ + (BIT_CLEAR_RXGCK_HT_FIFOTHR_8822C(x) | BIT_RXGCK_HT_FIFOTHR_8822C(v)) + +#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C 22 +#define BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C 0x3 +#define BIT_RXGCK_OFDM_FIFOTHR_8822C(x) \ + (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C) \ + << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C) +#define BITS_RXGCK_OFDM_FIFOTHR_8822C \ + (BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C \ + << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C) +#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8822C(x) \ + ((x) & (~BITS_RXGCK_OFDM_FIFOTHR_8822C)) +#define BIT_GET_RXGCK_OFDM_FIFOTHR_8822C(x) \ + (((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C) & \ + BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C) +#define BIT_SET_RXGCK_OFDM_FIFOTHR_8822C(x, v) \ + (BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8822C(x) | \ + BIT_RXGCK_OFDM_FIFOTHR_8822C(v)) + +#define BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C 20 +#define BIT_MASK_RXGCK_CCK_FIFOTHR_8822C 0x3 +#define BIT_RXGCK_CCK_FIFOTHR_8822C(x) \ + (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR_8822C) \ + << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C) +#define BITS_RXGCK_CCK_FIFOTHR_8822C \ + (BIT_MASK_RXGCK_CCK_FIFOTHR_8822C << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C) +#define BIT_CLEAR_RXGCK_CCK_FIFOTHR_8822C(x) \ + ((x) & (~BITS_RXGCK_CCK_FIFOTHR_8822C)) +#define BIT_GET_RXGCK_CCK_FIFOTHR_8822C(x) \ + (((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C) & \ + BIT_MASK_RXGCK_CCK_FIFOTHR_8822C) +#define BIT_SET_RXGCK_CCK_FIFOTHR_8822C(x, v) \ + (BIT_CLEAR_RXGCK_CCK_FIFOTHR_8822C(x) | BIT_RXGCK_CCK_FIFOTHR_8822C(v)) + +#define BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C 17 +#define BIT_MASK_RXGCK_ENTRY_DELAY_8822C 0x7 +#define BIT_RXGCK_ENTRY_DELAY_8822C(x) \ + (((x) & BIT_MASK_RXGCK_ENTRY_DELAY_8822C) \ + << BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C) +#define BITS_RXGCK_ENTRY_DELAY_8822C \ + (BIT_MASK_RXGCK_ENTRY_DELAY_8822C << BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C) +#define BIT_CLEAR_RXGCK_ENTRY_DELAY_8822C(x) \ + ((x) & (~BITS_RXGCK_ENTRY_DELAY_8822C)) +#define BIT_GET_RXGCK_ENTRY_DELAY_8822C(x) \ + (((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C) & \ + BIT_MASK_RXGCK_ENTRY_DELAY_8822C) +#define BIT_SET_RXGCK_ENTRY_DELAY_8822C(x, v) \ + (BIT_CLEAR_RXGCK_ENTRY_DELAY_8822C(x) | BIT_RXGCK_ENTRY_DELAY_8822C(v)) + +#define BIT_RXGCK_OFDMCCA_EN_8822C BIT(16) + +#define BIT_SHIFT_RXPSF_PKTLENTHR_8822C 13 +#define BIT_MASK_RXPSF_PKTLENTHR_8822C 0x7 +#define BIT_RXPSF_PKTLENTHR_8822C(x) \ + (((x) & BIT_MASK_RXPSF_PKTLENTHR_8822C) \ + << BIT_SHIFT_RXPSF_PKTLENTHR_8822C) +#define BITS_RXPSF_PKTLENTHR_8822C \ + (BIT_MASK_RXPSF_PKTLENTHR_8822C << BIT_SHIFT_RXPSF_PKTLENTHR_8822C) +#define BIT_CLEAR_RXPSF_PKTLENTHR_8822C(x) ((x) & (~BITS_RXPSF_PKTLENTHR_8822C)) +#define BIT_GET_RXPSF_PKTLENTHR_8822C(x) \ + (((x) >> BIT_SHIFT_RXPSF_PKTLENTHR_8822C) & \ + BIT_MASK_RXPSF_PKTLENTHR_8822C) +#define BIT_SET_RXPSF_PKTLENTHR_8822C(x, v) \ + (BIT_CLEAR_RXPSF_PKTLENTHR_8822C(x) | BIT_RXPSF_PKTLENTHR_8822C(v)) + +#define BIT_RXPSF_CTRLEN_8822C BIT(12) +#define BIT_RXPSF_VHTCHKEN_8822C BIT(11) +#define BIT_RXPSF_HTCHKEN_8822C BIT(10) +#define BIT_RXPSF_OFDMCHKEN_8822C BIT(9) +#define BIT_RXPSF_CCKCHKEN_8822C BIT(8) +#define BIT_RXPSF_OFDMRST_8822C BIT(7) +#define BIT_RXPSF_CCKRST_8822C BIT(6) +#define BIT_RXPSF_MHCHKEN_8822C BIT(5) +#define BIT_RXPSF_CONT_ERRCHKEN_8822C BIT(4) +#define BIT_RXPSF_ALL_ERRCHKEN_8822C BIT(3) + +#define BIT_SHIFT_RXPSF_ERRTHR_8822C 0 +#define BIT_MASK_RXPSF_ERRTHR_8822C 0x7 +#define BIT_RXPSF_ERRTHR_8822C(x) \ + (((x) & BIT_MASK_RXPSF_ERRTHR_8822C) << BIT_SHIFT_RXPSF_ERRTHR_8822C) +#define BITS_RXPSF_ERRTHR_8822C \ + (BIT_MASK_RXPSF_ERRTHR_8822C << BIT_SHIFT_RXPSF_ERRTHR_8822C) +#define BIT_CLEAR_RXPSF_ERRTHR_8822C(x) ((x) & (~BITS_RXPSF_ERRTHR_8822C)) +#define BIT_GET_RXPSF_ERRTHR_8822C(x) \ + (((x) >> BIT_SHIFT_RXPSF_ERRTHR_8822C) & BIT_MASK_RXPSF_ERRTHR_8822C) +#define BIT_SET_RXPSF_ERRTHR_8822C(x, v) \ + (BIT_CLEAR_RXPSF_ERRTHR_8822C(x) | BIT_RXPSF_ERRTHR_8822C(v)) + +/* 2 REG_RXPSF_TYPE_CTRL_8822C */ +#define BIT_RXPSF_DATA15EN_8822C BIT(31) +#define BIT_RXPSF_DATA14EN_8822C BIT(30) +#define BIT_RXPSF_DATA13EN_8822C BIT(29) +#define BIT_RXPSF_DATA12EN_8822C BIT(28) +#define BIT_RXPSF_DATA11EN_8822C BIT(27) +#define BIT_RXPSF_DATA10EN_8822C BIT(26) +#define BIT_RXPSF_DATA9EN_8822C BIT(25) +#define BIT_RXPSF_DATA8EN_8822C BIT(24) +#define BIT_RXPSF_DATA7EN_8822C BIT(23) +#define BIT_RXPSF_DATA6EN_8822C BIT(22) +#define BIT_RXPSF_DATA5EN_8822C BIT(21) +#define BIT_RXPSF_DATA4EN_8822C BIT(20) +#define BIT_RXPSF_DATA3EN_8822C BIT(19) +#define BIT_RXPSF_DATA2EN_8822C BIT(18) +#define BIT_RXPSF_DATA1EN_8822C BIT(17) +#define BIT_RXPSF_DATA0EN_8822C BIT(16) +#define BIT_RXPSF_MGT15EN_8822C BIT(15) +#define BIT_RXPSF_MGT14EN_8822C BIT(14) +#define BIT_RXPSF_MGT13EN_8822C BIT(13) +#define BIT_RXPSF_MGT12EN_8822C BIT(12) +#define BIT_RXPSF_MGT11EN_8822C BIT(11) +#define BIT_RXPSF_MGT10EN_8822C BIT(10) +#define BIT_RXPSF_MGT9EN_8822C BIT(9) +#define BIT_RXPSF_MGT8EN_8822C BIT(8) +#define BIT_RXPSF_MGT7EN_8822C BIT(7) +#define BIT_RXPSF_MGT6EN_8822C BIT(6) +#define BIT_RXPSF_MGT5EN_8822C BIT(5) +#define BIT_RXPSF_MGT4EN_8822C BIT(4) +#define BIT_RXPSF_MGT3EN_8822C BIT(3) +#define BIT_RXPSF_MGT2EN_8822C BIT(2) +#define BIT_RXPSF_MGT1EN_8822C BIT(1) +#define BIT_RXPSF_MGT0EN_8822C BIT(0) + +/* 2 REG_CAM_ACCESS_CTRL_8822C */ +#define BIT_INDIRECT_ERR_8822C BIT(6) +#define BIT_DIRECT_ERR_8822C BIT(5) +#define BIT_DIR_ACCESS_EN_RX_BA_8822C BIT(4) +#define BIT_DIR_ACCESS_EN_MBSSIDCAM_8822C BIT(3) +#define BIT_DIR_ACCESS_EN_KEY_8822C BIT(2) +#define BIT_DIR_ACCESS_EN_WOWLAN_8822C BIT(1) +#define BIT_DIR_ACCESS_EN_FW_FILTER_8822C BIT(0) + +/* 2 REG_HT_SND_REF_RATE_8822C */ + +#define BIT_SHIFT_WMAC_HT_CSI_RATE_8822C 0 +#define BIT_MASK_WMAC_HT_CSI_RATE_8822C 0x3f +#define BIT_WMAC_HT_CSI_RATE_8822C(x) \ + (((x) & BIT_MASK_WMAC_HT_CSI_RATE_8822C) \ + << BIT_SHIFT_WMAC_HT_CSI_RATE_8822C) +#define BITS_WMAC_HT_CSI_RATE_8822C \ + (BIT_MASK_WMAC_HT_CSI_RATE_8822C << BIT_SHIFT_WMAC_HT_CSI_RATE_8822C) +#define BIT_CLEAR_WMAC_HT_CSI_RATE_8822C(x) \ + ((x) & (~BITS_WMAC_HT_CSI_RATE_8822C)) +#define BIT_GET_WMAC_HT_CSI_RATE_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_HT_CSI_RATE_8822C) & \ + BIT_MASK_WMAC_HT_CSI_RATE_8822C) +#define BIT_SET_WMAC_HT_CSI_RATE_8822C(x, v) \ + (BIT_CLEAR_WMAC_HT_CSI_RATE_8822C(x) | BIT_WMAC_HT_CSI_RATE_8822C(v)) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_MACID2_8822C (MAC ID2 REGISTER) */ + +#define BIT_SHIFT_MACID2_V1_8822C 0 +#define BIT_MASK_MACID2_V1_8822C 0xffffffffL +#define BIT_MACID2_V1_8822C(x) \ + (((x) & BIT_MASK_MACID2_V1_8822C) << BIT_SHIFT_MACID2_V1_8822C) +#define BITS_MACID2_V1_8822C \ + (BIT_MASK_MACID2_V1_8822C << BIT_SHIFT_MACID2_V1_8822C) +#define BIT_CLEAR_MACID2_V1_8822C(x) ((x) & (~BITS_MACID2_V1_8822C)) +#define BIT_GET_MACID2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID2_V1_8822C) & BIT_MASK_MACID2_V1_8822C) +#define BIT_SET_MACID2_V1_8822C(x, v) \ + (BIT_CLEAR_MACID2_V1_8822C(x) | BIT_MACID2_V1_8822C(v)) + +/* 2 REG_MACID2_H_8822C (MAC ID2 REGISTER) */ + +#define BIT_SHIFT_MACID2_H_V1_8822C 0 +#define BIT_MASK_MACID2_H_V1_8822C 0xffff +#define BIT_MACID2_H_V1_8822C(x) \ + (((x) & BIT_MASK_MACID2_H_V1_8822C) << BIT_SHIFT_MACID2_H_V1_8822C) +#define BITS_MACID2_H_V1_8822C \ + (BIT_MASK_MACID2_H_V1_8822C << BIT_SHIFT_MACID2_H_V1_8822C) +#define BIT_CLEAR_MACID2_H_V1_8822C(x) ((x) & (~BITS_MACID2_H_V1_8822C)) +#define BIT_GET_MACID2_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID2_H_V1_8822C) & BIT_MASK_MACID2_H_V1_8822C) +#define BIT_SET_MACID2_H_V1_8822C(x, v) \ + (BIT_CLEAR_MACID2_H_V1_8822C(x) | BIT_MACID2_H_V1_8822C(v)) + +/* 2 REG_BSSID2_8822C (BSSID2 REGISTER) */ + +#define BIT_SHIFT_BSSID2_V1_8822C 0 +#define BIT_MASK_BSSID2_V1_8822C 0xffffffffL +#define BIT_BSSID2_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID2_V1_8822C) << BIT_SHIFT_BSSID2_V1_8822C) +#define BITS_BSSID2_V1_8822C \ + (BIT_MASK_BSSID2_V1_8822C << BIT_SHIFT_BSSID2_V1_8822C) +#define BIT_CLEAR_BSSID2_V1_8822C(x) ((x) & (~BITS_BSSID2_V1_8822C)) +#define BIT_GET_BSSID2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID2_V1_8822C) & BIT_MASK_BSSID2_V1_8822C) +#define BIT_SET_BSSID2_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID2_V1_8822C(x) | BIT_BSSID2_V1_8822C(v)) + +/* 2 REG_BSSID2_H_8822C (BSSID2 REGISTER) */ + +#define BIT_SHIFT_BSSID2_H_V1_8822C 0 +#define BIT_MASK_BSSID2_H_V1_8822C 0xffff +#define BIT_BSSID2_H_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID2_H_V1_8822C) << BIT_SHIFT_BSSID2_H_V1_8822C) +#define BITS_BSSID2_H_V1_8822C \ + (BIT_MASK_BSSID2_H_V1_8822C << BIT_SHIFT_BSSID2_H_V1_8822C) +#define BIT_CLEAR_BSSID2_H_V1_8822C(x) ((x) & (~BITS_BSSID2_H_V1_8822C)) +#define BIT_GET_BSSID2_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID2_H_V1_8822C) & BIT_MASK_BSSID2_H_V1_8822C) +#define BIT_SET_BSSID2_H_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID2_H_V1_8822C(x) | BIT_BSSID2_H_V1_8822C(v)) + +/* 2 REG_MACID3_8822C (MAC ID3 REGISTER) */ + +#define BIT_SHIFT_MACID3_V1_8822C 0 +#define BIT_MASK_MACID3_V1_8822C 0xffffffffL +#define BIT_MACID3_V1_8822C(x) \ + (((x) & BIT_MASK_MACID3_V1_8822C) << BIT_SHIFT_MACID3_V1_8822C) +#define BITS_MACID3_V1_8822C \ + (BIT_MASK_MACID3_V1_8822C << BIT_SHIFT_MACID3_V1_8822C) +#define BIT_CLEAR_MACID3_V1_8822C(x) ((x) & (~BITS_MACID3_V1_8822C)) +#define BIT_GET_MACID3_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID3_V1_8822C) & BIT_MASK_MACID3_V1_8822C) +#define BIT_SET_MACID3_V1_8822C(x, v) \ + (BIT_CLEAR_MACID3_V1_8822C(x) | BIT_MACID3_V1_8822C(v)) + +/* 2 REG_MACID3_H_8822C (MAC ID3 REGISTER) */ + +#define BIT_SHIFT_MACID3_H_V1_8822C 0 +#define BIT_MASK_MACID3_H_V1_8822C 0xffff +#define BIT_MACID3_H_V1_8822C(x) \ + (((x) & BIT_MASK_MACID3_H_V1_8822C) << BIT_SHIFT_MACID3_H_V1_8822C) +#define BITS_MACID3_H_V1_8822C \ + (BIT_MASK_MACID3_H_V1_8822C << BIT_SHIFT_MACID3_H_V1_8822C) +#define BIT_CLEAR_MACID3_H_V1_8822C(x) ((x) & (~BITS_MACID3_H_V1_8822C)) +#define BIT_GET_MACID3_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID3_H_V1_8822C) & BIT_MASK_MACID3_H_V1_8822C) +#define BIT_SET_MACID3_H_V1_8822C(x, v) \ + (BIT_CLEAR_MACID3_H_V1_8822C(x) | BIT_MACID3_H_V1_8822C(v)) + +/* 2 REG_BSSID3_8822C (BSSID3 REGISTER) */ + +#define BIT_SHIFT_BSSID3_V1_8822C 0 +#define BIT_MASK_BSSID3_V1_8822C 0xffffffffL +#define BIT_BSSID3_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID3_V1_8822C) << BIT_SHIFT_BSSID3_V1_8822C) +#define BITS_BSSID3_V1_8822C \ + (BIT_MASK_BSSID3_V1_8822C << BIT_SHIFT_BSSID3_V1_8822C) +#define BIT_CLEAR_BSSID3_V1_8822C(x) ((x) & (~BITS_BSSID3_V1_8822C)) +#define BIT_GET_BSSID3_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID3_V1_8822C) & BIT_MASK_BSSID3_V1_8822C) +#define BIT_SET_BSSID3_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID3_V1_8822C(x) | BIT_BSSID3_V1_8822C(v)) + +/* 2 REG_BSSID3_H_8822C (BSSID3 REGISTER) */ + +#define BIT_SHIFT_BSSID3_H_V1_8822C 0 +#define BIT_MASK_BSSID3_H_V1_8822C 0xffff +#define BIT_BSSID3_H_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID3_H_V1_8822C) << BIT_SHIFT_BSSID3_H_V1_8822C) +#define BITS_BSSID3_H_V1_8822C \ + (BIT_MASK_BSSID3_H_V1_8822C << BIT_SHIFT_BSSID3_H_V1_8822C) +#define BIT_CLEAR_BSSID3_H_V1_8822C(x) ((x) & (~BITS_BSSID3_H_V1_8822C)) +#define BIT_GET_BSSID3_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID3_H_V1_8822C) & BIT_MASK_BSSID3_H_V1_8822C) +#define BIT_SET_BSSID3_H_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID3_H_V1_8822C(x) | BIT_BSSID3_H_V1_8822C(v)) + +/* 2 REG_MACID4_8822C (MAC ID4 REGISTER) */ + +#define BIT_SHIFT_MACID4_V1_8822C 0 +#define BIT_MASK_MACID4_V1_8822C 0xffffffffL +#define BIT_MACID4_V1_8822C(x) \ + (((x) & BIT_MASK_MACID4_V1_8822C) << BIT_SHIFT_MACID4_V1_8822C) +#define BITS_MACID4_V1_8822C \ + (BIT_MASK_MACID4_V1_8822C << BIT_SHIFT_MACID4_V1_8822C) +#define BIT_CLEAR_MACID4_V1_8822C(x) ((x) & (~BITS_MACID4_V1_8822C)) +#define BIT_GET_MACID4_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID4_V1_8822C) & BIT_MASK_MACID4_V1_8822C) +#define BIT_SET_MACID4_V1_8822C(x, v) \ + (BIT_CLEAR_MACID4_V1_8822C(x) | BIT_MACID4_V1_8822C(v)) + +/* 2 REG_MACID4_H_8822C (MAC ID4 REGISTER) */ + +#define BIT_SHIFT_MACID4_H_V1_8822C 0 +#define BIT_MASK_MACID4_H_V1_8822C 0xffff +#define BIT_MACID4_H_V1_8822C(x) \ + (((x) & BIT_MASK_MACID4_H_V1_8822C) << BIT_SHIFT_MACID4_H_V1_8822C) +#define BITS_MACID4_H_V1_8822C \ + (BIT_MASK_MACID4_H_V1_8822C << BIT_SHIFT_MACID4_H_V1_8822C) +#define BIT_CLEAR_MACID4_H_V1_8822C(x) ((x) & (~BITS_MACID4_H_V1_8822C)) +#define BIT_GET_MACID4_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID4_H_V1_8822C) & BIT_MASK_MACID4_H_V1_8822C) +#define BIT_SET_MACID4_H_V1_8822C(x, v) \ + (BIT_CLEAR_MACID4_H_V1_8822C(x) | BIT_MACID4_H_V1_8822C(v)) + +/* 2 REG_BSSID4_8822C (BSSID4 REGISTER) */ + +#define BIT_SHIFT_BSSID4_V1_8822C 0 +#define BIT_MASK_BSSID4_V1_8822C 0xffffffffL +#define BIT_BSSID4_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID4_V1_8822C) << BIT_SHIFT_BSSID4_V1_8822C) +#define BITS_BSSID4_V1_8822C \ + (BIT_MASK_BSSID4_V1_8822C << BIT_SHIFT_BSSID4_V1_8822C) +#define BIT_CLEAR_BSSID4_V1_8822C(x) ((x) & (~BITS_BSSID4_V1_8822C)) +#define BIT_GET_BSSID4_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID4_V1_8822C) & BIT_MASK_BSSID4_V1_8822C) +#define BIT_SET_BSSID4_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID4_V1_8822C(x) | BIT_BSSID4_V1_8822C(v)) + +/* 2 REG_BSSID4_H_8822C (BSSID4 REGISTER) */ + +#define BIT_SHIFT_BSSID4_H_V1_8822C 0 +#define BIT_MASK_BSSID4_H_V1_8822C 0xffff +#define BIT_BSSID4_H_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID4_H_V1_8822C) << BIT_SHIFT_BSSID4_H_V1_8822C) +#define BITS_BSSID4_H_V1_8822C \ + (BIT_MASK_BSSID4_H_V1_8822C << BIT_SHIFT_BSSID4_H_V1_8822C) +#define BIT_CLEAR_BSSID4_H_V1_8822C(x) ((x) & (~BITS_BSSID4_H_V1_8822C)) +#define BIT_GET_BSSID4_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID4_H_V1_8822C) & BIT_MASK_BSSID4_H_V1_8822C) +#define BIT_SET_BSSID4_H_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID4_H_V1_8822C(x) | BIT_BSSID4_H_V1_8822C(v)) + +/* 2 REG_NOA_REPORT_8822C */ + +/* 2 REG_NOA_REPORT_1_8822C */ + +/* 2 REG_NOA_REPORT_2_8822C */ + +/* 2 REG_NOA_REPORT_3_8822C */ + +/* 2 REG_PWRBIT_SETTING_8822C */ +#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(15) +#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(14) +#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(13) +#define BIT_CLI3_PWR_ST_V1_8822C BIT(12) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(11) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(10) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(9) +#define BIT_CLI2_PWR_ST_V1_8822C BIT(8) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(7) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(6) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(5) +#define BIT_CLI1_PWR_ST_V1_8822C BIT(4) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(3) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(2) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(1) +#define BIT_CLI0_PWR_ST_V1_8822C BIT(0) + +/* 2 REG_GENERAL_OPTION_8822C */ +#define BIT_WMAC_EXT_DBG_SEL_V1_8822C BIT(6) +#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS_8822C BIT(5) +#define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA_8822C BIT(4) +#define BIT_RX_DMA_BYPASS_CHECK_MGTBIT_RX_DMA_BYPASS_CHECK_MGT_8822C BIT(3) +#define BIT_TXSERV_FIELD_SEL_8822C BIT(2) +#define BIT_RXVHT_LEN_SEL_8822C BIT(1) +#define BIT_RXMIC_PROTECT_EN_8822C BIT(0) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_CSI_RRSR_8822C */ +#define BIT_CSI_LDPC_EN_8822C BIT(29) +#define BIT_CSI_STBC_EN_8822C BIT(28) + +#define BIT_SHIFT_CSI_RRSC_BITMAP_8822C 4 +#define BIT_MASK_CSI_RRSC_BITMAP_8822C 0xffffff +#define BIT_CSI_RRSC_BITMAP_8822C(x) \ + (((x) & BIT_MASK_CSI_RRSC_BITMAP_8822C) \ + << BIT_SHIFT_CSI_RRSC_BITMAP_8822C) +#define BITS_CSI_RRSC_BITMAP_8822C \ + (BIT_MASK_CSI_RRSC_BITMAP_8822C << BIT_SHIFT_CSI_RRSC_BITMAP_8822C) +#define BIT_CLEAR_CSI_RRSC_BITMAP_8822C(x) ((x) & (~BITS_CSI_RRSC_BITMAP_8822C)) +#define BIT_GET_CSI_RRSC_BITMAP_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_RRSC_BITMAP_8822C) & \ + BIT_MASK_CSI_RRSC_BITMAP_8822C) +#define BIT_SET_CSI_RRSC_BITMAP_8822C(x, v) \ + (BIT_CLEAR_CSI_RRSC_BITMAP_8822C(x) | BIT_CSI_RRSC_BITMAP_8822C(v)) + +#define BIT_SHIFT_OFDM_LEN_TH_8822C 0 +#define BIT_MASK_OFDM_LEN_TH_8822C 0xf +#define BIT_OFDM_LEN_TH_8822C(x) \ + (((x) & BIT_MASK_OFDM_LEN_TH_8822C) << BIT_SHIFT_OFDM_LEN_TH_8822C) +#define BITS_OFDM_LEN_TH_8822C \ + (BIT_MASK_OFDM_LEN_TH_8822C << BIT_SHIFT_OFDM_LEN_TH_8822C) +#define BIT_CLEAR_OFDM_LEN_TH_8822C(x) ((x) & (~BITS_OFDM_LEN_TH_8822C)) +#define BIT_GET_OFDM_LEN_TH_8822C(x) \ + (((x) >> BIT_SHIFT_OFDM_LEN_TH_8822C) & BIT_MASK_OFDM_LEN_TH_8822C) +#define BIT_SET_OFDM_LEN_TH_8822C(x, v) \ + (BIT_CLEAR_OFDM_LEN_TH_8822C(x) | BIT_OFDM_LEN_TH_8822C(v)) + +/* 2 REG_MU_BF_OPTION_8822C */ +#define BIT_WMAC_RESP_NONSTA1_DIS_8822C BIT(7) +#define BIT_WMAC_TXMU_ACKPOLICY_EN_8822C BIT(6) + +#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C 4 +#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C 0x3 +#define BIT_WMAC_TXMU_ACKPOLICY_8822C(x) \ + (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C) \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C) +#define BITS_WMAC_TXMU_ACKPOLICY_8822C \ + (BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822C(x) \ + ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8822C)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C) & \ + BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C) +#define BIT_SET_WMAC_TXMU_ACKPOLICY_8822C(x, v) \ + (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822C(x) | \ + BIT_WMAC_TXMU_ACKPOLICY_8822C(v)) + +#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C 1 +#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C 0x7 +#define BIT_WMAC_MU_BFEE_PORT_SEL_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C) +#define BITS_WMAC_MU_BFEE_PORT_SEL_8822C \ + (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8822C)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C) & \ + BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822C(x) | \ + BIT_WMAC_MU_BFEE_PORT_SEL_8822C(v)) + +#define BIT_WMAC_MU_BFEE_DIS_8822C BIT(0) + +/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8822C */ + +#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C 0 +#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C 0xff +#define BIT_WMAC_PAUSE_BB_CLR_TH_8822C(x) \ + (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C) \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C) +#define BITS_WMAC_PAUSE_BB_CLR_TH_8822C \ + (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822C(x) \ + ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8822C)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C) & \ + BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8822C(x, v) \ + (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822C(x) | \ + BIT_WMAC_PAUSE_BB_CLR_TH_8822C(v)) + +/* 2 REG__WMAC_MULBK_BUF_8822C */ + +#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C 0 +#define BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C 0xff +#define BIT_WMAC_MULBK_PAGE_SIZE_8822C(x) \ + (((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C) \ + << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C) +#define BITS_WMAC_MULBK_PAGE_SIZE_8822C \ + (BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C \ + << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C) +#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8822C(x) \ + ((x) & (~BITS_WMAC_MULBK_PAGE_SIZE_8822C)) +#define BIT_GET_WMAC_MULBK_PAGE_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C) & \ + BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C) +#define BIT_SET_WMAC_MULBK_PAGE_SIZE_8822C(x, v) \ + (BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8822C(x) | \ + BIT_WMAC_MULBK_PAGE_SIZE_8822C(v)) + +/* 2 REG_WMAC_MU_OPTION_8822C */ + +/* 2 REG_WMAC_MU_BF_CTL_8822C */ +#define BIT_WMAC_INVLD_BFPRT_CHK_8822C BIT(15) +#define BIT_WMAC_RETXBFRPTSEQ_UPD_8822C BIT(14) + +#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C 12 +#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C 0x3 +#define BIT_WMAC_MU_BFRPTSEG_SEL_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C) \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C) +#define BITS_WMAC_MU_BFRPTSEG_SEL_8822C \ + (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8822C)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C) & \ + BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822C(x) | \ + BIT_WMAC_MU_BFRPTSEG_SEL_8822C(v)) + +#define BIT_SHIFT_WMAC_MU_BF_MYAID_8822C 0 +#define BIT_MASK_WMAC_MU_BF_MYAID_8822C 0xfff +#define BIT_WMAC_MU_BF_MYAID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822C) \ + << BIT_SHIFT_WMAC_MU_BF_MYAID_8822C) +#define BITS_WMAC_MU_BF_MYAID_8822C \ + (BIT_MASK_WMAC_MU_BF_MYAID_8822C << BIT_SHIFT_WMAC_MU_BF_MYAID_8822C) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BF_MYAID_8822C)) +#define BIT_GET_WMAC_MU_BF_MYAID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822C) & \ + BIT_MASK_WMAC_MU_BF_MYAID_8822C) +#define BIT_SET_WMAC_MU_BF_MYAID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BF_MYAID_8822C(x) | BIT_WMAC_MU_BF_MYAID_8822C(v)) + +/* 2 REG_WMAC_MU_BFRPT_PARA_8822C */ + +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C 13 +#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C 0x7 +#define BIT_BFRPT_PARA_USERID_SEL_V1_8822C(x) \ + (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C) \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C) +#define BITS_BFRPT_PARA_USERID_SEL_V1_8822C \ + (BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8822C(x) \ + ((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1_8822C)) +#define BIT_GET_BFRPT_PARA_USERID_SEL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C) & \ + BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C) +#define BIT_SET_BFRPT_PARA_USERID_SEL_V1_8822C(x, v) \ + (BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8822C(x) | \ + BIT_BFRPT_PARA_USERID_SEL_V1_8822C(v)) + +#define BIT_SHIFT_BFRPT_PARA_V1_8822C 0 +#define BIT_MASK_BFRPT_PARA_V1_8822C 0x1fff +#define BIT_BFRPT_PARA_V1_8822C(x) \ + (((x) & BIT_MASK_BFRPT_PARA_V1_8822C) << BIT_SHIFT_BFRPT_PARA_V1_8822C) +#define BITS_BFRPT_PARA_V1_8822C \ + (BIT_MASK_BFRPT_PARA_V1_8822C << BIT_SHIFT_BFRPT_PARA_V1_8822C) +#define BIT_CLEAR_BFRPT_PARA_V1_8822C(x) ((x) & (~BITS_BFRPT_PARA_V1_8822C)) +#define BIT_GET_BFRPT_PARA_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_V1_8822C) & BIT_MASK_BFRPT_PARA_V1_8822C) +#define BIT_SET_BFRPT_PARA_V1_8822C(x, v) \ + (BIT_CLEAR_BFRPT_PARA_V1_8822C(x) | BIT_BFRPT_PARA_V1_8822C(v)) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C */ +#define BIT_STATUS_BFEE2_8822C BIT(10) +#define BIT_WMAC_MU_BFEE2_EN_8822C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C 0 +#define BIT_MASK_WMAC_MU_BFEE2_AID_8822C 0x1ff +#define BIT_WMAC_MU_BFEE2_AID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C) +#define BITS_WMAC_MU_BFEE2_AID_8822C \ + (BIT_MASK_WMAC_MU_BFEE2_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE2_AID_8822C)) +#define BIT_GET_WMAC_MU_BFEE2_AID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C) & \ + BIT_MASK_WMAC_MU_BFEE2_AID_8822C) +#define BIT_SET_WMAC_MU_BFEE2_AID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE2_AID_8822C(x) | BIT_WMAC_MU_BFEE2_AID_8822C(v)) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C */ +#define BIT_STATUS_BFEE3_8822C BIT(10) +#define BIT_WMAC_MU_BFEE3_EN_8822C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C 0 +#define BIT_MASK_WMAC_MU_BFEE3_AID_8822C 0x1ff +#define BIT_WMAC_MU_BFEE3_AID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C) +#define BITS_WMAC_MU_BFEE3_AID_8822C \ + (BIT_MASK_WMAC_MU_BFEE3_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE3_AID_8822C)) +#define BIT_GET_WMAC_MU_BFEE3_AID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C) & \ + BIT_MASK_WMAC_MU_BFEE3_AID_8822C) +#define BIT_SET_WMAC_MU_BFEE3_AID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE3_AID_8822C(x) | BIT_WMAC_MU_BFEE3_AID_8822C(v)) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C */ +#define BIT_STATUS_BFEE4_8822C BIT(10) +#define BIT_WMAC_MU_BFEE4_EN_8822C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C 0 +#define BIT_MASK_WMAC_MU_BFEE4_AID_8822C 0x1ff +#define BIT_WMAC_MU_BFEE4_AID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C) +#define BITS_WMAC_MU_BFEE4_AID_8822C \ + (BIT_MASK_WMAC_MU_BFEE4_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE4_AID_8822C)) +#define BIT_GET_WMAC_MU_BFEE4_AID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C) & \ + BIT_MASK_WMAC_MU_BFEE4_AID_8822C) +#define BIT_SET_WMAC_MU_BFEE4_AID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE4_AID_8822C(x) | BIT_WMAC_MU_BFEE4_AID_8822C(v)) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C */ +#define BIT_BIT_STATUS_BFEE5_8822C BIT(10) +#define BIT_WMAC_MU_BFEE5_EN_8822C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C 0 +#define BIT_MASK_WMAC_MU_BFEE5_AID_8822C 0x1ff +#define BIT_WMAC_MU_BFEE5_AID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C) +#define BITS_WMAC_MU_BFEE5_AID_8822C \ + (BIT_MASK_WMAC_MU_BFEE5_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE5_AID_8822C)) +#define BIT_GET_WMAC_MU_BFEE5_AID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C) & \ + BIT_MASK_WMAC_MU_BFEE5_AID_8822C) +#define BIT_SET_WMAC_MU_BFEE5_AID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE5_AID_8822C(x) | BIT_WMAC_MU_BFEE5_AID_8822C(v)) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C */ +#define BIT_STATUS_BFEE6_8822C BIT(10) +#define BIT_WMAC_MU_BFEE6_EN_8822C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C 0 +#define BIT_MASK_WMAC_MU_BFEE6_AID_8822C 0x1ff +#define BIT_WMAC_MU_BFEE6_AID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C) +#define BITS_WMAC_MU_BFEE6_AID_8822C \ + (BIT_MASK_WMAC_MU_BFEE6_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE6_AID_8822C)) +#define BIT_GET_WMAC_MU_BFEE6_AID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C) & \ + BIT_MASK_WMAC_MU_BFEE6_AID_8822C) +#define BIT_SET_WMAC_MU_BFEE6_AID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE6_AID_8822C(x) | BIT_WMAC_MU_BFEE6_AID_8822C(v)) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C */ +#define BIT_STATUS_BFEE7_8822C BIT(10) +#define BIT_WMAC_MU_BFEE7_EN_8822C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C 0 +#define BIT_MASK_WMAC_MU_BFEE7_AID_8822C 0x1ff +#define BIT_WMAC_MU_BFEE7_AID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C) +#define BITS_WMAC_MU_BFEE7_AID_8822C \ + (BIT_MASK_WMAC_MU_BFEE7_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE7_AID_8822C)) +#define BIT_GET_WMAC_MU_BFEE7_AID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C) & \ + BIT_MASK_WMAC_MU_BFEE7_AID_8822C) +#define BIT_SET_WMAC_MU_BFEE7_AID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE7_AID_8822C(x) | BIT_WMAC_MU_BFEE7_AID_8822C(v)) + +/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8822C */ +#define BIT_RST_ALL_COUNTER_8822C BIT(31) + +#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C 16 +#define BIT_MASK_ABORT_RX_VBON_COUNTER_8822C 0xff +#define BIT_ABORT_RX_VBON_COUNTER_8822C(x) \ + (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822C) \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C) +#define BITS_ABORT_RX_VBON_COUNTER_8822C \ + (BIT_MASK_ABORT_RX_VBON_COUNTER_8822C \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822C(x) \ + ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8822C)) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8822C(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C) & \ + BIT_MASK_ABORT_RX_VBON_COUNTER_8822C) +#define BIT_SET_ABORT_RX_VBON_COUNTER_8822C(x, v) \ + (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822C(x) | \ + BIT_ABORT_RX_VBON_COUNTER_8822C(v)) + +#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C 8 +#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C 0xff +#define BIT_ABORT_RX_RDRDY_COUNTER_8822C(x) \ + (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C) \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C) +#define BITS_ABORT_RX_RDRDY_COUNTER_8822C \ + (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822C(x) \ + ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8822C)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822C(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C) & \ + BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8822C(x, v) \ + (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822C(x) | \ + BIT_ABORT_RX_RDRDY_COUNTER_8822C(v)) + +#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C 0 +#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C 0xff +#define BIT_VBON_EARLY_FALLING_COUNTER_8822C(x) \ + (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C) \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C) +#define BITS_VBON_EARLY_FALLING_COUNTER_8822C \ + (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822C(x) \ + ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8822C)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822C(x) \ + (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C) & \ + BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8822C(x, v) \ + (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822C(x) | \ + BIT_VBON_EARLY_FALLING_COUNTER_8822C(v)) + +/* 2 REG_WMAC_PLCP_MONITOR_8822C */ +#define BIT_WMAC_PLCP_TRX_SEL_8822C BIT(31) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C 28 +#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C 0x7 +#define BIT_WMAC_PLCP_RDSIG_SEL_8822C(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C) +#define BITS_WMAC_PLCP_RDSIG_SEL_8822C \ + (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822C(x) \ + ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8822C)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C) & \ + BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8822C(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822C(x) | \ + BIT_WMAC_PLCP_RDSIG_SEL_8822C(v)) + +#define BIT_SHIFT_WMAC_RATE_IDX_8822C 24 +#define BIT_MASK_WMAC_RATE_IDX_8822C 0xf +#define BIT_WMAC_RATE_IDX_8822C(x) \ + (((x) & BIT_MASK_WMAC_RATE_IDX_8822C) << BIT_SHIFT_WMAC_RATE_IDX_8822C) +#define BITS_WMAC_RATE_IDX_8822C \ + (BIT_MASK_WMAC_RATE_IDX_8822C << BIT_SHIFT_WMAC_RATE_IDX_8822C) +#define BIT_CLEAR_WMAC_RATE_IDX_8822C(x) ((x) & (~BITS_WMAC_RATE_IDX_8822C)) +#define BIT_GET_WMAC_RATE_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822C) & BIT_MASK_WMAC_RATE_IDX_8822C) +#define BIT_SET_WMAC_RATE_IDX_8822C(x, v) \ + (BIT_CLEAR_WMAC_RATE_IDX_8822C(x) | BIT_WMAC_RATE_IDX_8822C(v)) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822C 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8822C 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8822C(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822C) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) +#define BITS_WMAC_PLCP_RDSIG_8822C \ + (BIT_MASK_WMAC_PLCP_RDSIG_8822C << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822C)) +#define BIT_GET_WMAC_PLCP_RDSIG_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8822C) +#define BIT_SET_WMAC_PLCP_RDSIG_8822C(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) | BIT_WMAC_PLCP_RDSIG_8822C(v)) + +/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8822C */ +#define BIT_WMAC_MUTX_IDX_8822C BIT(24) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822C 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8822C 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8822C(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822C) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) +#define BITS_WMAC_PLCP_RDSIG_8822C \ + (BIT_MASK_WMAC_PLCP_RDSIG_8822C << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822C)) +#define BIT_GET_WMAC_PLCP_RDSIG_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8822C) +#define BIT_SET_WMAC_PLCP_RDSIG_8822C(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) | BIT_WMAC_PLCP_RDSIG_8822C(v)) + +/* 2 REG_WMAC_CSIDMA_CFG_8822C */ + +#define BIT_SHIFT_CSI_SEG_SIZE_8822C 16 +#define BIT_MASK_CSI_SEG_SIZE_8822C 0xfff +#define BIT_CSI_SEG_SIZE_8822C(x) \ + (((x) & BIT_MASK_CSI_SEG_SIZE_8822C) << BIT_SHIFT_CSI_SEG_SIZE_8822C) +#define BITS_CSI_SEG_SIZE_8822C \ + (BIT_MASK_CSI_SEG_SIZE_8822C << BIT_SHIFT_CSI_SEG_SIZE_8822C) +#define BIT_CLEAR_CSI_SEG_SIZE_8822C(x) ((x) & (~BITS_CSI_SEG_SIZE_8822C)) +#define BIT_GET_CSI_SEG_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_SEG_SIZE_8822C) & BIT_MASK_CSI_SEG_SIZE_8822C) +#define BIT_SET_CSI_SEG_SIZE_8822C(x, v) \ + (BIT_CLEAR_CSI_SEG_SIZE_8822C(x) | BIT_CSI_SEG_SIZE_8822C(v)) + +#define BIT_SHIFT_CSI_START_PAGE_8822C 0 +#define BIT_MASK_CSI_START_PAGE_8822C 0xfff +#define BIT_CSI_START_PAGE_8822C(x) \ + (((x) & BIT_MASK_CSI_START_PAGE_8822C) \ + << BIT_SHIFT_CSI_START_PAGE_8822C) +#define BITS_CSI_START_PAGE_8822C \ + (BIT_MASK_CSI_START_PAGE_8822C << BIT_SHIFT_CSI_START_PAGE_8822C) +#define BIT_CLEAR_CSI_START_PAGE_8822C(x) ((x) & (~BITS_CSI_START_PAGE_8822C)) +#define BIT_GET_CSI_START_PAGE_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_START_PAGE_8822C) & \ + BIT_MASK_CSI_START_PAGE_8822C) +#define BIT_SET_CSI_START_PAGE_8822C(x, v) \ + (BIT_CLEAR_CSI_START_PAGE_8822C(x) | BIT_CSI_START_PAGE_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_0_8822C (TA0 REGISTER) */ + +#define BIT_SHIFT_TA0_V1_8822C 0 +#define BIT_MASK_TA0_V1_8822C 0xffffffffL +#define BIT_TA0_V1_8822C(x) \ + (((x) & BIT_MASK_TA0_V1_8822C) << BIT_SHIFT_TA0_V1_8822C) +#define BITS_TA0_V1_8822C (BIT_MASK_TA0_V1_8822C << BIT_SHIFT_TA0_V1_8822C) +#define BIT_CLEAR_TA0_V1_8822C(x) ((x) & (~BITS_TA0_V1_8822C)) +#define BIT_GET_TA0_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA0_V1_8822C) & BIT_MASK_TA0_V1_8822C) +#define BIT_SET_TA0_V1_8822C(x, v) \ + (BIT_CLEAR_TA0_V1_8822C(x) | BIT_TA0_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_0_H_8822C (TA0 REGISTER) */ + +#define BIT_SHIFT_TA0_H_V1_8822C 0 +#define BIT_MASK_TA0_H_V1_8822C 0xffff +#define BIT_TA0_H_V1_8822C(x) \ + (((x) & BIT_MASK_TA0_H_V1_8822C) << BIT_SHIFT_TA0_H_V1_8822C) +#define BITS_TA0_H_V1_8822C \ + (BIT_MASK_TA0_H_V1_8822C << BIT_SHIFT_TA0_H_V1_8822C) +#define BIT_CLEAR_TA0_H_V1_8822C(x) ((x) & (~BITS_TA0_H_V1_8822C)) +#define BIT_GET_TA0_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA0_H_V1_8822C) & BIT_MASK_TA0_H_V1_8822C) +#define BIT_SET_TA0_H_V1_8822C(x, v) \ + (BIT_CLEAR_TA0_H_V1_8822C(x) | BIT_TA0_H_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_1_8822C (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_V1_8822C 0 +#define BIT_MASK_TA1_V1_8822C 0xffffffffL +#define BIT_TA1_V1_8822C(x) \ + (((x) & BIT_MASK_TA1_V1_8822C) << BIT_SHIFT_TA1_V1_8822C) +#define BITS_TA1_V1_8822C (BIT_MASK_TA1_V1_8822C << BIT_SHIFT_TA1_V1_8822C) +#define BIT_CLEAR_TA1_V1_8822C(x) ((x) & (~BITS_TA1_V1_8822C)) +#define BIT_GET_TA1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA1_V1_8822C) & BIT_MASK_TA1_V1_8822C) +#define BIT_SET_TA1_V1_8822C(x, v) \ + (BIT_CLEAR_TA1_V1_8822C(x) | BIT_TA1_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_1_H_8822C (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_H_V1_8822C 0 +#define BIT_MASK_TA1_H_V1_8822C 0xffff +#define BIT_TA1_H_V1_8822C(x) \ + (((x) & BIT_MASK_TA1_H_V1_8822C) << BIT_SHIFT_TA1_H_V1_8822C) +#define BITS_TA1_H_V1_8822C \ + (BIT_MASK_TA1_H_V1_8822C << BIT_SHIFT_TA1_H_V1_8822C) +#define BIT_CLEAR_TA1_H_V1_8822C(x) ((x) & (~BITS_TA1_H_V1_8822C)) +#define BIT_GET_TA1_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA1_H_V1_8822C) & BIT_MASK_TA1_H_V1_8822C) +#define BIT_SET_TA1_H_V1_8822C(x, v) \ + (BIT_CLEAR_TA1_H_V1_8822C(x) | BIT_TA1_H_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_2_8822C (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_V1_8822C 0 +#define BIT_MASK_TA2_V1_8822C 0xffffffffL +#define BIT_TA2_V1_8822C(x) \ + (((x) & BIT_MASK_TA2_V1_8822C) << BIT_SHIFT_TA2_V1_8822C) +#define BITS_TA2_V1_8822C (BIT_MASK_TA2_V1_8822C << BIT_SHIFT_TA2_V1_8822C) +#define BIT_CLEAR_TA2_V1_8822C(x) ((x) & (~BITS_TA2_V1_8822C)) +#define BIT_GET_TA2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA2_V1_8822C) & BIT_MASK_TA2_V1_8822C) +#define BIT_SET_TA2_V1_8822C(x, v) \ + (BIT_CLEAR_TA2_V1_8822C(x) | BIT_TA2_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_2_H_8822C (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_H_V1_8822C 0 +#define BIT_MASK_TA2_H_V1_8822C 0xffff +#define BIT_TA2_H_V1_8822C(x) \ + (((x) & BIT_MASK_TA2_H_V1_8822C) << BIT_SHIFT_TA2_H_V1_8822C) +#define BITS_TA2_H_V1_8822C \ + (BIT_MASK_TA2_H_V1_8822C << BIT_SHIFT_TA2_H_V1_8822C) +#define BIT_CLEAR_TA2_H_V1_8822C(x) ((x) & (~BITS_TA2_H_V1_8822C)) +#define BIT_GET_TA2_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA2_H_V1_8822C) & BIT_MASK_TA2_H_V1_8822C) +#define BIT_SET_TA2_H_V1_8822C(x, v) \ + (BIT_CLEAR_TA2_H_V1_8822C(x) | BIT_TA2_H_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_3_8822C (TA3 REGISTER) */ + +#define BIT_SHIFT_TA2_V1_8822C 0 +#define BIT_MASK_TA2_V1_8822C 0xffffffffL +#define BIT_TA2_V1_8822C(x) \ + (((x) & BIT_MASK_TA2_V1_8822C) << BIT_SHIFT_TA2_V1_8822C) +#define BITS_TA2_V1_8822C (BIT_MASK_TA2_V1_8822C << BIT_SHIFT_TA2_V1_8822C) +#define BIT_CLEAR_TA2_V1_8822C(x) ((x) & (~BITS_TA2_V1_8822C)) +#define BIT_GET_TA2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA2_V1_8822C) & BIT_MASK_TA2_V1_8822C) +#define BIT_SET_TA2_V1_8822C(x, v) \ + (BIT_CLEAR_TA2_V1_8822C(x) | BIT_TA2_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_3_H_8822C (TA3 REGISTER) */ + +#define BIT_SHIFT_TA3_H_V1_8822C 0 +#define BIT_MASK_TA3_H_V1_8822C 0xffff +#define BIT_TA3_H_V1_8822C(x) \ + (((x) & BIT_MASK_TA3_H_V1_8822C) << BIT_SHIFT_TA3_H_V1_8822C) +#define BITS_TA3_H_V1_8822C \ + (BIT_MASK_TA3_H_V1_8822C << BIT_SHIFT_TA3_H_V1_8822C) +#define BIT_CLEAR_TA3_H_V1_8822C(x) ((x) & (~BITS_TA3_H_V1_8822C)) +#define BIT_GET_TA3_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA3_H_V1_8822C) & BIT_MASK_TA3_H_V1_8822C) +#define BIT_SET_TA3_H_V1_8822C(x, v) \ + (BIT_CLEAR_TA3_H_V1_8822C(x) | BIT_TA3_H_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_4_8822C (TA4 REGISTER) */ + +#define BIT_SHIFT_TA4_V1_8822C 0 +#define BIT_MASK_TA4_V1_8822C 0xffffffffL +#define BIT_TA4_V1_8822C(x) \ + (((x) & BIT_MASK_TA4_V1_8822C) << BIT_SHIFT_TA4_V1_8822C) +#define BITS_TA4_V1_8822C (BIT_MASK_TA4_V1_8822C << BIT_SHIFT_TA4_V1_8822C) +#define BIT_CLEAR_TA4_V1_8822C(x) ((x) & (~BITS_TA4_V1_8822C)) +#define BIT_GET_TA4_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA4_V1_8822C) & BIT_MASK_TA4_V1_8822C) +#define BIT_SET_TA4_V1_8822C(x, v) \ + (BIT_CLEAR_TA4_V1_8822C(x) | BIT_TA4_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_4_H_8822C (TA4 REGISTER) */ + +#define BIT_SHIFT_TA4_H_V1_8822C 0 +#define BIT_MASK_TA4_H_V1_8822C 0xffff +#define BIT_TA4_H_V1_8822C(x) \ + (((x) & BIT_MASK_TA4_H_V1_8822C) << BIT_SHIFT_TA4_H_V1_8822C) +#define BITS_TA4_H_V1_8822C \ + (BIT_MASK_TA4_H_V1_8822C << BIT_SHIFT_TA4_H_V1_8822C) +#define BIT_CLEAR_TA4_H_V1_8822C(x) ((x) & (~BITS_TA4_H_V1_8822C)) +#define BIT_GET_TA4_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA4_H_V1_8822C) & BIT_MASK_TA4_H_V1_8822C) +#define BIT_SET_TA4_H_V1_8822C(x, v) \ + (BIT_CLEAR_TA4_H_V1_8822C(x) | BIT_TA4_H_V1_8822C(v)) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_MACID1_8822C */ + +#define BIT_SHIFT_MACID1_0_8822C 0 +#define BIT_MASK_MACID1_0_8822C 0xffffffffL +#define BIT_MACID1_0_8822C(x) \ + (((x) & BIT_MASK_MACID1_0_8822C) << BIT_SHIFT_MACID1_0_8822C) +#define BITS_MACID1_0_8822C \ + (BIT_MASK_MACID1_0_8822C << BIT_SHIFT_MACID1_0_8822C) +#define BIT_CLEAR_MACID1_0_8822C(x) ((x) & (~BITS_MACID1_0_8822C)) +#define BIT_GET_MACID1_0_8822C(x) \ + (((x) >> BIT_SHIFT_MACID1_0_8822C) & BIT_MASK_MACID1_0_8822C) +#define BIT_SET_MACID1_0_8822C(x, v) \ + (BIT_CLEAR_MACID1_0_8822C(x) | BIT_MACID1_0_8822C(v)) + +/* 2 REG_MACID1_1_8822C */ + +#define BIT_SHIFT_MACID1_1_8822C 0 +#define BIT_MASK_MACID1_1_8822C 0xffff +#define BIT_MACID1_1_8822C(x) \ + (((x) & BIT_MASK_MACID1_1_8822C) << BIT_SHIFT_MACID1_1_8822C) +#define BITS_MACID1_1_8822C \ + (BIT_MASK_MACID1_1_8822C << BIT_SHIFT_MACID1_1_8822C) +#define BIT_CLEAR_MACID1_1_8822C(x) ((x) & (~BITS_MACID1_1_8822C)) +#define BIT_GET_MACID1_1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID1_1_8822C) & BIT_MASK_MACID1_1_8822C) +#define BIT_SET_MACID1_1_8822C(x, v) \ + (BIT_CLEAR_MACID1_1_8822C(x) | BIT_MACID1_1_8822C(v)) + +/* 2 REG_BSSID1_8822C */ + +#define BIT_SHIFT_BSSID1_0_8822C 0 +#define BIT_MASK_BSSID1_0_8822C 0xffffffffL +#define BIT_BSSID1_0_8822C(x) \ + (((x) & BIT_MASK_BSSID1_0_8822C) << BIT_SHIFT_BSSID1_0_8822C) +#define BITS_BSSID1_0_8822C \ + (BIT_MASK_BSSID1_0_8822C << BIT_SHIFT_BSSID1_0_8822C) +#define BIT_CLEAR_BSSID1_0_8822C(x) ((x) & (~BITS_BSSID1_0_8822C)) +#define BIT_GET_BSSID1_0_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID1_0_8822C) & BIT_MASK_BSSID1_0_8822C) +#define BIT_SET_BSSID1_0_8822C(x, v) \ + (BIT_CLEAR_BSSID1_0_8822C(x) | BIT_BSSID1_0_8822C(v)) + +/* 2 REG_BSSID1_1_8822C */ + +#define BIT_SHIFT_BSSID1_1_8822C 0 +#define BIT_MASK_BSSID1_1_8822C 0xffff +#define BIT_BSSID1_1_8822C(x) \ + (((x) & BIT_MASK_BSSID1_1_8822C) << BIT_SHIFT_BSSID1_1_8822C) +#define BITS_BSSID1_1_8822C \ + (BIT_MASK_BSSID1_1_8822C << BIT_SHIFT_BSSID1_1_8822C) +#define BIT_CLEAR_BSSID1_1_8822C(x) ((x) & (~BITS_BSSID1_1_8822C)) +#define BIT_GET_BSSID1_1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID1_1_8822C) & BIT_MASK_BSSID1_1_8822C) +#define BIT_SET_BSSID1_1_8822C(x, v) \ + (BIT_CLEAR_BSSID1_1_8822C(x) | BIT_BSSID1_1_8822C(v)) + +/* 2 REG_BCN_PSR_RPT1_8822C */ + +#define BIT_SHIFT_DTIM_CNT1_8822C 24 +#define BIT_MASK_DTIM_CNT1_8822C 0xff +#define BIT_DTIM_CNT1_8822C(x) \ + (((x) & BIT_MASK_DTIM_CNT1_8822C) << BIT_SHIFT_DTIM_CNT1_8822C) +#define BITS_DTIM_CNT1_8822C \ + (BIT_MASK_DTIM_CNT1_8822C << BIT_SHIFT_DTIM_CNT1_8822C) +#define BIT_CLEAR_DTIM_CNT1_8822C(x) ((x) & (~BITS_DTIM_CNT1_8822C)) +#define BIT_GET_DTIM_CNT1_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT1_8822C) & BIT_MASK_DTIM_CNT1_8822C) +#define BIT_SET_DTIM_CNT1_8822C(x, v) \ + (BIT_CLEAR_DTIM_CNT1_8822C(x) | BIT_DTIM_CNT1_8822C(v)) + +#define BIT_SHIFT_DTIM_PERIOD1_8822C 16 +#define BIT_MASK_DTIM_PERIOD1_8822C 0xff +#define BIT_DTIM_PERIOD1_8822C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD1_8822C) << BIT_SHIFT_DTIM_PERIOD1_8822C) +#define BITS_DTIM_PERIOD1_8822C \ + (BIT_MASK_DTIM_PERIOD1_8822C << BIT_SHIFT_DTIM_PERIOD1_8822C) +#define BIT_CLEAR_DTIM_PERIOD1_8822C(x) ((x) & (~BITS_DTIM_PERIOD1_8822C)) +#define BIT_GET_DTIM_PERIOD1_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD1_8822C) & BIT_MASK_DTIM_PERIOD1_8822C) +#define BIT_SET_DTIM_PERIOD1_8822C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD1_8822C(x) | BIT_DTIM_PERIOD1_8822C(v)) + +#define BIT_DTIM1_8822C BIT(15) +#define BIT_TIM1_8822C BIT(14) +#define BIT_BCN_VALID_V2_8822C BIT(13) + +#define BIT_SHIFT_PS_AID_1_8822C 0 +#define BIT_MASK_PS_AID_1_8822C 0x7ff +#define BIT_PS_AID_1_8822C(x) \ + (((x) & BIT_MASK_PS_AID_1_8822C) << BIT_SHIFT_PS_AID_1_8822C) +#define BITS_PS_AID_1_8822C \ + (BIT_MASK_PS_AID_1_8822C << BIT_SHIFT_PS_AID_1_8822C) +#define BIT_CLEAR_PS_AID_1_8822C(x) ((x) & (~BITS_PS_AID_1_8822C)) +#define BIT_GET_PS_AID_1_8822C(x) \ + (((x) >> BIT_SHIFT_PS_AID_1_8822C) & BIT_MASK_PS_AID_1_8822C) +#define BIT_SET_PS_AID_1_8822C(x, v) \ + (BIT_CLEAR_PS_AID_1_8822C(x) | BIT_PS_AID_1_8822C(v)) + +/* 2 REG_ASSOCIATED_BFMEE_SEL_8822C */ +#define BIT_TXUSER_ID1_8822C BIT(25) + +#define BIT_SHIFT_AID1_8822C 16 +#define BIT_MASK_AID1_8822C 0x1ff +#define BIT_AID1_8822C(x) (((x) & BIT_MASK_AID1_8822C) << BIT_SHIFT_AID1_8822C) +#define BITS_AID1_8822C (BIT_MASK_AID1_8822C << BIT_SHIFT_AID1_8822C) +#define BIT_CLEAR_AID1_8822C(x) ((x) & (~BITS_AID1_8822C)) +#define BIT_GET_AID1_8822C(x) \ + (((x) >> BIT_SHIFT_AID1_8822C) & BIT_MASK_AID1_8822C) +#define BIT_SET_AID1_8822C(x, v) (BIT_CLEAR_AID1_8822C(x) | BIT_AID1_8822C(v)) + +#define BIT_TXUSER_ID0_8822C BIT(9) + +#define BIT_SHIFT_AID0_8822C 0 +#define BIT_MASK_AID0_8822C 0x1ff +#define BIT_AID0_8822C(x) (((x) & BIT_MASK_AID0_8822C) << BIT_SHIFT_AID0_8822C) +#define BITS_AID0_8822C (BIT_MASK_AID0_8822C << BIT_SHIFT_AID0_8822C) +#define BIT_CLEAR_AID0_8822C(x) ((x) & (~BITS_AID0_8822C)) +#define BIT_GET_AID0_8822C(x) \ + (((x) >> BIT_SHIFT_AID0_8822C) & BIT_MASK_AID0_8822C) +#define BIT_SET_AID0_8822C(x, v) (BIT_CLEAR_AID0_8822C(x) | BIT_AID0_8822C(v)) + +/* 2 REG_SND_PTCL_CTRL_8822C */ + +#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C 24 +#define BIT_MASK_NDP_RX_STANDBY_TIMER_8822C 0xff +#define BIT_NDP_RX_STANDBY_TIMER_8822C(x) \ + (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822C) \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C) +#define BITS_NDP_RX_STANDBY_TIMER_8822C \ + (BIT_MASK_NDP_RX_STANDBY_TIMER_8822C \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822C(x) \ + ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8822C)) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C) & \ + BIT_MASK_NDP_RX_STANDBY_TIMER_8822C) +#define BIT_SET_NDP_RX_STANDBY_TIMER_8822C(x, v) \ + (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822C(x) | \ + BIT_NDP_RX_STANDBY_TIMER_8822C(v)) + +#define BIT_R_WMAC_CHK_RPTPOLL_A2_DIS_8822C BIT(23) +#define BIT_R_WMAC_CHK_UCNDPA_A2_DIS_8822C BIT(22) + +#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C 16 +#define BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C 0x3f +#define BIT_CSI_RPT_OFFSET_HT_V1_8822C(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C) \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C) +#define BITS_CSI_RPT_OFFSET_HT_V1_8822C \ + (BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822C(x) \ + ((x) & (~BITS_CSI_RPT_OFFSET_HT_V1_8822C)) +#define BIT_GET_CSI_RPT_OFFSET_HT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C) & \ + BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C) +#define BIT_SET_CSI_RPT_OFFSET_HT_V1_8822C(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822C(x) | \ + BIT_CSI_RPT_OFFSET_HT_V1_8822C(v)) + +#define BIT_R_WMAC_OFFSET_RPTPOLL_EN_8822C BIT(15) +#define BIT_R_WMAC_CSI_CHKSUM_DIS_8822C BIT(14) + +#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C 8 +#define BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C 0x3f +#define BIT_R_WMAC_VHT_CATEGORY_V1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C) \ + << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C) +#define BITS_R_WMAC_VHT_CATEGORY_V1_8822C \ + (BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C \ + << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C) +#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1_8822C(x) \ + ((x) & (~BITS_R_WMAC_VHT_CATEGORY_V1_8822C)) +#define BIT_GET_R_WMAC_VHT_CATEGORY_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C) & \ + BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C) +#define BIT_SET_R_WMAC_VHT_CATEGORY_V1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1_8822C(x) | \ + BIT_R_WMAC_VHT_CATEGORY_V1_8822C(v)) + +#define BIT_R_WMAC_USE_NSTS_8822C BIT(7) +#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8822C BIT(6) +#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8822C BIT(5) +#define BIT_R_WMAC_BFPARAM_SEL_8822C BIT(4) +#define BIT_R_WMAC_CSISEQ_SEL_8822C BIT(3) +#define BIT_R_WMAC_CSI_WITHHTC_EN_8822C BIT(2) +#define BIT_R_WMAC_HT_NDPA_EN_8822C BIT(1) +#define BIT_R_WMAC_VHT_NDPA_EN_8822C BIT(0) + +/* 2 REG_RX_CSI_RPT_INFO_8822C */ +#define BIT_WRITE_ENABLE_8822C BIT(31) +#define BIT_WMAC_CHECK_SOUNDING_SEQ_8822C BIT(30) + +#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C 1 +#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C 0xffffff +#define BIT_VHTHT_MIMO_CTRL_FIELD_8822C(x) \ + (((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C) \ + << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C) +#define BITS_VHTHT_MIMO_CTRL_FIELD_8822C \ + (BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C \ + << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C) +#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8822C(x) \ + ((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD_8822C)) +#define BIT_GET_VHTHT_MIMO_CTRL_FIELD_8822C(x) \ + (((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C) & \ + BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C) +#define BIT_SET_VHTHT_MIMO_CTRL_FIELD_8822C(x, v) \ + (BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8822C(x) | \ + BIT_VHTHT_MIMO_CTRL_FIELD_8822C(v)) + +#define BIT_CSI_INTERRUPT_STATUS_8822C BIT(0) + +/* 2 REG_NS_ARP_CTRL_8822C */ +#define BIT_R_WMAC_NSARP_RSPEN_8822C BIT(15) +#define BIT_R_WMAC_NSARP_RARP_8822C BIT(9) +#define BIT_R_WMAC_NSARP_RIPV6_8822C BIT(8) + +#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C 6 +#define BIT_MASK_R_WMAC_NSARP_MODEN_8822C 0x3 +#define BIT_R_WMAC_NSARP_MODEN_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822C) \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C) +#define BITS_R_WMAC_NSARP_MODEN_8822C \ + (BIT_MASK_R_WMAC_NSARP_MODEN_8822C \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8822C(x) \ + ((x) & (~BITS_R_WMAC_NSARP_MODEN_8822C)) +#define BIT_GET_R_WMAC_NSARP_MODEN_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C) & \ + BIT_MASK_R_WMAC_NSARP_MODEN_8822C) +#define BIT_SET_R_WMAC_NSARP_MODEN_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_MODEN_8822C(x) | \ + BIT_R_WMAC_NSARP_MODEN_8822C(v)) + +#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C 4 +#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C 0x3 +#define BIT_R_WMAC_NSARP_RSPFTP_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C) +#define BITS_R_WMAC_NSARP_RSPFTP_8822C \ + (BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822C(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8822C)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C) & \ + BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C) +#define BIT_SET_R_WMAC_NSARP_RSPFTP_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822C(x) | \ + BIT_R_WMAC_NSARP_RSPFTP_8822C(v)) + +#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C 0 +#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C 0xf +#define BIT_R_WMAC_NSARP_RSPSEC_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C) +#define BITS_R_WMAC_NSARP_RSPSEC_8822C \ + (BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822C(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8822C)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C) & \ + BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C) +#define BIT_SET_R_WMAC_NSARP_RSPSEC_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822C(x) | \ + BIT_R_WMAC_NSARP_RSPSEC_8822C(v)) + +/* 2 REG_NS_ARP_INFO_8822C */ +#define BIT_REQ_IS_MCNS_8822C BIT(23) +#define BIT_REQ_IS_UCNS_8822C BIT(22) +#define BIT_REQ_IS_USNS_8822C BIT(21) +#define BIT_REQ_IS_ARP_8822C BIT(20) +#define BIT_EXPRSP_MH_WITHQC_8822C BIT(19) + +#define BIT_SHIFT_EXPRSP_SECTYPE_8822C 16 +#define BIT_MASK_EXPRSP_SECTYPE_8822C 0x7 +#define BIT_EXPRSP_SECTYPE_8822C(x) \ + (((x) & BIT_MASK_EXPRSP_SECTYPE_8822C) \ + << BIT_SHIFT_EXPRSP_SECTYPE_8822C) +#define BITS_EXPRSP_SECTYPE_8822C \ + (BIT_MASK_EXPRSP_SECTYPE_8822C << BIT_SHIFT_EXPRSP_SECTYPE_8822C) +#define BIT_CLEAR_EXPRSP_SECTYPE_8822C(x) ((x) & (~BITS_EXPRSP_SECTYPE_8822C)) +#define BIT_GET_EXPRSP_SECTYPE_8822C(x) \ + (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822C) & \ + BIT_MASK_EXPRSP_SECTYPE_8822C) +#define BIT_SET_EXPRSP_SECTYPE_8822C(x, v) \ + (BIT_CLEAR_EXPRSP_SECTYPE_8822C(x) | BIT_EXPRSP_SECTYPE_8822C(v)) + +#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C 8 +#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C 0xff +#define BIT_EXPRSP_CHKSM_7_TO_0_8822C(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C) \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C) +#define BITS_EXPRSP_CHKSM_7_TO_0_8822C \ + (BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C) +#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822C(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8822C)) +#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822C(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C) & \ + BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C) +#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8822C(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822C(x) | \ + BIT_EXPRSP_CHKSM_7_TO_0_8822C(v)) + +#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C 0 +#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C 0xff +#define BIT_EXPRSP_CHKSM_15_TO_8_8822C(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C) \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C) +#define BITS_EXPRSP_CHKSM_15_TO_8_8822C \ + (BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C) +#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822C(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8822C)) +#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822C(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C) & \ + BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C) +#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8822C(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822C(x) | \ + BIT_EXPRSP_CHKSM_15_TO_8_8822C(v)) + +/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8822C */ + +#define BIT_SHIFT_WMAC_ARPIP_8822C 0 +#define BIT_MASK_WMAC_ARPIP_8822C 0xffffffffL +#define BIT_WMAC_ARPIP_8822C(x) \ + (((x) & BIT_MASK_WMAC_ARPIP_8822C) << BIT_SHIFT_WMAC_ARPIP_8822C) +#define BITS_WMAC_ARPIP_8822C \ + (BIT_MASK_WMAC_ARPIP_8822C << BIT_SHIFT_WMAC_ARPIP_8822C) +#define BIT_CLEAR_WMAC_ARPIP_8822C(x) ((x) & (~BITS_WMAC_ARPIP_8822C)) +#define BIT_GET_WMAC_ARPIP_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_ARPIP_8822C) & BIT_MASK_WMAC_ARPIP_8822C) +#define BIT_SET_WMAC_ARPIP_8822C(x, v) \ + (BIT_CLEAR_WMAC_ARPIP_8822C(x) | BIT_WMAC_ARPIP_8822C(v)) + +/* 2 REG_BEAMFORMING_INFO_NSARP_8822C */ + +#define BIT_SHIFT_UPD_BFMEE_USERID_8822C 13 +#define BIT_MASK_UPD_BFMEE_USERID_8822C 0x7 +#define BIT_UPD_BFMEE_USERID_8822C(x) \ + (((x) & BIT_MASK_UPD_BFMEE_USERID_8822C) \ + << BIT_SHIFT_UPD_BFMEE_USERID_8822C) +#define BITS_UPD_BFMEE_USERID_8822C \ + (BIT_MASK_UPD_BFMEE_USERID_8822C << BIT_SHIFT_UPD_BFMEE_USERID_8822C) +#define BIT_CLEAR_UPD_BFMEE_USERID_8822C(x) \ + ((x) & (~BITS_UPD_BFMEE_USERID_8822C)) +#define BIT_GET_UPD_BFMEE_USERID_8822C(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_USERID_8822C) & \ + BIT_MASK_UPD_BFMEE_USERID_8822C) +#define BIT_SET_UPD_BFMEE_USERID_8822C(x, v) \ + (BIT_CLEAR_UPD_BFMEE_USERID_8822C(x) | BIT_UPD_BFMEE_USERID_8822C(v)) + +#define BIT_UPD_BFMEE_FBTP_8822C BIT(12) + +#define BIT_SHIFT_UPD_BFMEE_BW_8822C 0 +#define BIT_MASK_UPD_BFMEE_BW_8822C 0xfff +#define BIT_UPD_BFMEE_BW_8822C(x) \ + (((x) & BIT_MASK_UPD_BFMEE_BW_8822C) << BIT_SHIFT_UPD_BFMEE_BW_8822C) +#define BITS_UPD_BFMEE_BW_8822C \ + (BIT_MASK_UPD_BFMEE_BW_8822C << BIT_SHIFT_UPD_BFMEE_BW_8822C) +#define BIT_CLEAR_UPD_BFMEE_BW_8822C(x) ((x) & (~BITS_UPD_BFMEE_BW_8822C)) +#define BIT_GET_UPD_BFMEE_BW_8822C(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_BW_8822C) & BIT_MASK_UPD_BFMEE_BW_8822C) +#define BIT_SET_UPD_BFMEE_BW_8822C(x, v) \ + (BIT_CLEAR_UPD_BFMEE_BW_8822C(x) | BIT_UPD_BFMEE_BW_8822C(v)) + +#define BIT_SHIFT_UPD_BFMEE_CB_8822C 8 +#define BIT_MASK_UPD_BFMEE_CB_8822C 0x3 +#define BIT_UPD_BFMEE_CB_8822C(x) \ + (((x) & BIT_MASK_UPD_BFMEE_CB_8822C) << BIT_SHIFT_UPD_BFMEE_CB_8822C) +#define BITS_UPD_BFMEE_CB_8822C \ + (BIT_MASK_UPD_BFMEE_CB_8822C << BIT_SHIFT_UPD_BFMEE_CB_8822C) +#define BIT_CLEAR_UPD_BFMEE_CB_8822C(x) ((x) & (~BITS_UPD_BFMEE_CB_8822C)) +#define BIT_GET_UPD_BFMEE_CB_8822C(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_CB_8822C) & BIT_MASK_UPD_BFMEE_CB_8822C) +#define BIT_SET_UPD_BFMEE_CB_8822C(x, v) \ + (BIT_CLEAR_UPD_BFMEE_CB_8822C(x) | BIT_UPD_BFMEE_CB_8822C(v)) + +#define BIT_SHIFT_UPD_BFMEE_NG_8822C 6 +#define BIT_MASK_UPD_BFMEE_NG_8822C 0x3 +#define BIT_UPD_BFMEE_NG_8822C(x) \ + (((x) & BIT_MASK_UPD_BFMEE_NG_8822C) << BIT_SHIFT_UPD_BFMEE_NG_8822C) +#define BITS_UPD_BFMEE_NG_8822C \ + (BIT_MASK_UPD_BFMEE_NG_8822C << BIT_SHIFT_UPD_BFMEE_NG_8822C) +#define BIT_CLEAR_UPD_BFMEE_NG_8822C(x) ((x) & (~BITS_UPD_BFMEE_NG_8822C)) +#define BIT_GET_UPD_BFMEE_NG_8822C(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_NG_8822C) & BIT_MASK_UPD_BFMEE_NG_8822C) +#define BIT_SET_UPD_BFMEE_NG_8822C(x, v) \ + (BIT_CLEAR_UPD_BFMEE_NG_8822C(x) | BIT_UPD_BFMEE_NG_8822C(v)) + +#define BIT_SHIFT_UPD_BFMEE_NR_8822C 3 +#define BIT_MASK_UPD_BFMEE_NR_8822C 0x7 +#define BIT_UPD_BFMEE_NR_8822C(x) \ + (((x) & BIT_MASK_UPD_BFMEE_NR_8822C) << BIT_SHIFT_UPD_BFMEE_NR_8822C) +#define BITS_UPD_BFMEE_NR_8822C \ + (BIT_MASK_UPD_BFMEE_NR_8822C << BIT_SHIFT_UPD_BFMEE_NR_8822C) +#define BIT_CLEAR_UPD_BFMEE_NR_8822C(x) ((x) & (~BITS_UPD_BFMEE_NR_8822C)) +#define BIT_GET_UPD_BFMEE_NR_8822C(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_NR_8822C) & BIT_MASK_UPD_BFMEE_NR_8822C) +#define BIT_SET_UPD_BFMEE_NR_8822C(x, v) \ + (BIT_CLEAR_UPD_BFMEE_NR_8822C(x) | BIT_UPD_BFMEE_NR_8822C(v)) + +#define BIT_SHIFT_UPD_BFMEE_NC_8822C 0 +#define BIT_MASK_UPD_BFMEE_NC_8822C 0x7 +#define BIT_UPD_BFMEE_NC_8822C(x) \ + (((x) & BIT_MASK_UPD_BFMEE_NC_8822C) << BIT_SHIFT_UPD_BFMEE_NC_8822C) +#define BITS_UPD_BFMEE_NC_8822C \ + (BIT_MASK_UPD_BFMEE_NC_8822C << BIT_SHIFT_UPD_BFMEE_NC_8822C) +#define BIT_CLEAR_UPD_BFMEE_NC_8822C(x) ((x) & (~BITS_UPD_BFMEE_NC_8822C)) +#define BIT_GET_UPD_BFMEE_NC_8822C(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_NC_8822C) & BIT_MASK_UPD_BFMEE_NC_8822C) +#define BIT_SET_UPD_BFMEE_NC_8822C(x, v) \ + (BIT_CLEAR_UPD_BFMEE_NC_8822C(x) | BIT_UPD_BFMEE_NC_8822C(v)) + +/* 2 REG_IPV6_8822C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_0_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C) +#define BITS_R_WMAC_IPV6_MYIPAD_0_8822C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8822C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8822C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8822C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_0_8822C(v)) + +/* 2 REG_IPV6_1_8822C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C) +#define BITS_R_WMAC_IPV6_MYIPAD_1_8822C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8822C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8822C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8822C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_1_8822C(v)) + +/* 2 REG_IPV6_2_8822C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_2_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C) +#define BITS_R_WMAC_IPV6_MYIPAD_2_8822C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8822C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8822C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8822C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_2_8822C(v)) + +/* 2 REG_IPV6_3_8822C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_3_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C) +#define BITS_R_WMAC_IPV6_MYIPAD_3_8822C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8822C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8822C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8822C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_3_8822C(v)) + +/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822C */ + +#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C 4 +#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C 0xf +#define BIT_R_WMAC_CTX_SUBTYPE_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C) \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C) +#define BITS_R_WMAC_CTX_SUBTYPE_8822C \ + (BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822C(x) \ + ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8822C)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C) & \ + BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C) +#define BIT_SET_R_WMAC_CTX_SUBTYPE_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822C(x) | \ + BIT_R_WMAC_CTX_SUBTYPE_8822C(v)) + +#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C 0 +#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C 0xf +#define BIT_R_WMAC_RTX_SUBTYPE_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C) \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C) +#define BITS_R_WMAC_RTX_SUBTYPE_8822C \ + (BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822C(x) \ + ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8822C)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C) & \ + BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C) +#define BIT_SET_R_WMAC_RTX_SUBTYPE_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822C(x) | \ + BIT_R_WMAC_RTX_SUBTYPE_8822C(v)) + +/* 2 REG_WMAC_SWAES_DIO_B63_B32_8822C */ + +#define BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C 0 +#define BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C 0xffffffffL +#define BIT_WMAC_SWAES_DIO_B63_B32_8822C(x) \ + (((x) & BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C) \ + << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C) +#define BITS_WMAC_SWAES_DIO_B63_B32_8822C \ + (BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C \ + << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C) +#define BIT_CLEAR_WMAC_SWAES_DIO_B63_B32_8822C(x) \ + ((x) & (~BITS_WMAC_SWAES_DIO_B63_B32_8822C)) +#define BIT_GET_WMAC_SWAES_DIO_B63_B32_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C) & \ + BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C) +#define BIT_SET_WMAC_SWAES_DIO_B63_B32_8822C(x, v) \ + (BIT_CLEAR_WMAC_SWAES_DIO_B63_B32_8822C(x) | \ + BIT_WMAC_SWAES_DIO_B63_B32_8822C(v)) + +/* 2 REG_WMAC_SWAES_DIO_B95_B64_8822C */ + +#define BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C 0 +#define BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C 0xffffffffL +#define BIT_WMAC_SWAES_DIO_B95_B64_8822C(x) \ + (((x) & BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C) \ + << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C) +#define BITS_WMAC_SWAES_DIO_B95_B64_8822C \ + (BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C \ + << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C) +#define BIT_CLEAR_WMAC_SWAES_DIO_B95_B64_8822C(x) \ + ((x) & (~BITS_WMAC_SWAES_DIO_B95_B64_8822C)) +#define BIT_GET_WMAC_SWAES_DIO_B95_B64_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C) & \ + BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C) +#define BIT_SET_WMAC_SWAES_DIO_B95_B64_8822C(x, v) \ + (BIT_CLEAR_WMAC_SWAES_DIO_B95_B64_8822C(x) | \ + BIT_WMAC_SWAES_DIO_B95_B64_8822C(v)) + +/* 2 REG_WMAC_SWAES_DIO_B127_B96_8822C */ + +#define BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C 0 +#define BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C 0xffffffffL +#define BIT_WMAC_SWAES_DIO_B127_B96_8822C(x) \ + (((x) & BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C) \ + << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C) +#define BITS_WMAC_SWAES_DIO_B127_B96_8822C \ + (BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C \ + << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C) +#define BIT_CLEAR_WMAC_SWAES_DIO_B127_B96_8822C(x) \ + ((x) & (~BITS_WMAC_SWAES_DIO_B127_B96_8822C)) +#define BIT_GET_WMAC_SWAES_DIO_B127_B96_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C) & \ + BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C) +#define BIT_SET_WMAC_SWAES_DIO_B127_B96_8822C(x, v) \ + (BIT_CLEAR_WMAC_SWAES_DIO_B127_B96_8822C(x) | \ + BIT_WMAC_SWAES_DIO_B127_B96_8822C(v)) + +/* 2 REG_WMAC_SWAES_CFG_8822C */ + +/* 2 REG_BT_COEX_V2_8822C */ +#define BIT_GNT_BT_POLARITY_8822C BIT(12) +#define BIT_GNT_BT_BYPASS_PRIORITY_8822C BIT(8) + +#define BIT_SHIFT_TIMER_8822C 0 +#define BIT_MASK_TIMER_8822C 0xff +#define BIT_TIMER_8822C(x) \ + (((x) & BIT_MASK_TIMER_8822C) << BIT_SHIFT_TIMER_8822C) +#define BITS_TIMER_8822C (BIT_MASK_TIMER_8822C << BIT_SHIFT_TIMER_8822C) +#define BIT_CLEAR_TIMER_8822C(x) ((x) & (~BITS_TIMER_8822C)) +#define BIT_GET_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_TIMER_8822C) & BIT_MASK_TIMER_8822C) +#define BIT_SET_TIMER_8822C(x, v) \ + (BIT_CLEAR_TIMER_8822C(x) | BIT_TIMER_8822C(v)) + +/* 2 REG_BT_COEX_8822C */ +#define BIT_R_GNT_BT_RFC_SW_8822C BIT(12) +#define BIT_R_GNT_BT_RFC_SW_EN_8822C BIT(11) +#define BIT_R_GNT_BT_BB_SW_8822C BIT(10) +#define BIT_R_GNT_BT_BB_SW_EN_8822C BIT(9) +#define BIT_R_BT_CNT_THREN_8822C BIT(8) + +#define BIT_SHIFT_R_BT_CNT_THR_8822C 0 +#define BIT_MASK_R_BT_CNT_THR_8822C 0xff +#define BIT_R_BT_CNT_THR_8822C(x) \ + (((x) & BIT_MASK_R_BT_CNT_THR_8822C) << BIT_SHIFT_R_BT_CNT_THR_8822C) +#define BITS_R_BT_CNT_THR_8822C \ + (BIT_MASK_R_BT_CNT_THR_8822C << BIT_SHIFT_R_BT_CNT_THR_8822C) +#define BIT_CLEAR_R_BT_CNT_THR_8822C(x) ((x) & (~BITS_R_BT_CNT_THR_8822C)) +#define BIT_GET_R_BT_CNT_THR_8822C(x) \ + (((x) >> BIT_SHIFT_R_BT_CNT_THR_8822C) & BIT_MASK_R_BT_CNT_THR_8822C) +#define BIT_SET_R_BT_CNT_THR_8822C(x, v) \ + (BIT_CLEAR_R_BT_CNT_THR_8822C(x) | BIT_R_BT_CNT_THR_8822C(v)) + +/* 2 REG_WLAN_ACT_MASK_CTRL_8822C */ + +#define BIT_SHIFT_RXMYRTS_NAV_V1_8822C 8 +#define BIT_MASK_RXMYRTS_NAV_V1_8822C 0xff +#define BIT_RXMYRTS_NAV_V1_8822C(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_V1_8822C) \ + << BIT_SHIFT_RXMYRTS_NAV_V1_8822C) +#define BITS_RXMYRTS_NAV_V1_8822C \ + (BIT_MASK_RXMYRTS_NAV_V1_8822C << BIT_SHIFT_RXMYRTS_NAV_V1_8822C) +#define BIT_CLEAR_RXMYRTS_NAV_V1_8822C(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8822C)) +#define BIT_GET_RXMYRTS_NAV_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822C) & \ + BIT_MASK_RXMYRTS_NAV_V1_8822C) +#define BIT_SET_RXMYRTS_NAV_V1_8822C(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_V1_8822C(x) | BIT_RXMYRTS_NAV_V1_8822C(v)) + +#define BIT_SHIFT_RTSRST_V1_8822C 0 +#define BIT_MASK_RTSRST_V1_8822C 0xff +#define BIT_RTSRST_V1_8822C(x) \ + (((x) & BIT_MASK_RTSRST_V1_8822C) << BIT_SHIFT_RTSRST_V1_8822C) +#define BITS_RTSRST_V1_8822C \ + (BIT_MASK_RTSRST_V1_8822C << BIT_SHIFT_RTSRST_V1_8822C) +#define BIT_CLEAR_RTSRST_V1_8822C(x) ((x) & (~BITS_RTSRST_V1_8822C)) +#define BIT_GET_RTSRST_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RTSRST_V1_8822C) & BIT_MASK_RTSRST_V1_8822C) +#define BIT_SET_RTSRST_V1_8822C(x, v) \ + (BIT_CLEAR_RTSRST_V1_8822C(x) | BIT_RTSRST_V1_8822C(v)) + +/* 2 REG_WLAN_ACT_MASK_CTRL_1_8822C */ +#define BIT_WLRX_TER_BY_CTL_1_8822C BIT(11) +#define BIT_WLRX_TER_BY_AD_1_8822C BIT(10) +#define BIT_ANT_DIVERSITY_SEL_1_8822C BIT(9) +#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8822C BIT(8) +#define BIT_WLACT_LOW_GNTWL_EN_1_8822C BIT(2) +#define BIT_WLACT_HIGH_GNTBT_EN_1_8822C BIT(1) +#define BIT_NAV_UPPER_1_V1_8822C BIT(0) + +/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8822C */ + +#define BIT_SHIFT_BT_STAT_DELAY_8822C 12 +#define BIT_MASK_BT_STAT_DELAY_8822C 0xf +#define BIT_BT_STAT_DELAY_8822C(x) \ + (((x) & BIT_MASK_BT_STAT_DELAY_8822C) << BIT_SHIFT_BT_STAT_DELAY_8822C) +#define BITS_BT_STAT_DELAY_8822C \ + (BIT_MASK_BT_STAT_DELAY_8822C << BIT_SHIFT_BT_STAT_DELAY_8822C) +#define BIT_CLEAR_BT_STAT_DELAY_8822C(x) ((x) & (~BITS_BT_STAT_DELAY_8822C)) +#define BIT_GET_BT_STAT_DELAY_8822C(x) \ + (((x) >> BIT_SHIFT_BT_STAT_DELAY_8822C) & BIT_MASK_BT_STAT_DELAY_8822C) +#define BIT_SET_BT_STAT_DELAY_8822C(x, v) \ + (BIT_CLEAR_BT_STAT_DELAY_8822C(x) | BIT_BT_STAT_DELAY_8822C(v)) + +#define BIT_SHIFT_BT_TRX_INIT_DETECT_8822C 8 +#define BIT_MASK_BT_TRX_INIT_DETECT_8822C 0xf +#define BIT_BT_TRX_INIT_DETECT_8822C(x) \ + (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822C) \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8822C) +#define BITS_BT_TRX_INIT_DETECT_8822C \ + (BIT_MASK_BT_TRX_INIT_DETECT_8822C \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8822C) +#define BIT_CLEAR_BT_TRX_INIT_DETECT_8822C(x) \ + ((x) & (~BITS_BT_TRX_INIT_DETECT_8822C)) +#define BIT_GET_BT_TRX_INIT_DETECT_8822C(x) \ + (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822C) & \ + BIT_MASK_BT_TRX_INIT_DETECT_8822C) +#define BIT_SET_BT_TRX_INIT_DETECT_8822C(x, v) \ + (BIT_CLEAR_BT_TRX_INIT_DETECT_8822C(x) | \ + BIT_BT_TRX_INIT_DETECT_8822C(v)) + +#define BIT_SHIFT_BT_PRI_DETECT_TO_8822C 4 +#define BIT_MASK_BT_PRI_DETECT_TO_8822C 0xf +#define BIT_BT_PRI_DETECT_TO_8822C(x) \ + (((x) & BIT_MASK_BT_PRI_DETECT_TO_8822C) \ + << BIT_SHIFT_BT_PRI_DETECT_TO_8822C) +#define BITS_BT_PRI_DETECT_TO_8822C \ + (BIT_MASK_BT_PRI_DETECT_TO_8822C << BIT_SHIFT_BT_PRI_DETECT_TO_8822C) +#define BIT_CLEAR_BT_PRI_DETECT_TO_8822C(x) \ + ((x) & (~BITS_BT_PRI_DETECT_TO_8822C)) +#define BIT_GET_BT_PRI_DETECT_TO_8822C(x) \ + (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822C) & \ + BIT_MASK_BT_PRI_DETECT_TO_8822C) +#define BIT_SET_BT_PRI_DETECT_TO_8822C(x, v) \ + (BIT_CLEAR_BT_PRI_DETECT_TO_8822C(x) | BIT_BT_PRI_DETECT_TO_8822C(v)) + +#define BIT_R_GRANTALL_WLMASK_8822C BIT(3) +#define BIT_STATIS_BT_EN_8822C BIT(2) +#define BIT_WL_ACT_MASK_ENABLE_8822C BIT(1) +#define BIT_ENHANCED_BT_8822C BIT(0) + +/* 2 REG_BT_ACT_STATISTICS_8822C */ + +#define BIT_SHIFT_STATIS_BT_HI_RX_8822C 16 +#define BIT_MASK_STATIS_BT_HI_RX_8822C 0xffff +#define BIT_STATIS_BT_HI_RX_8822C(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_RX_8822C) \ + << BIT_SHIFT_STATIS_BT_HI_RX_8822C) +#define BITS_STATIS_BT_HI_RX_8822C \ + (BIT_MASK_STATIS_BT_HI_RX_8822C << BIT_SHIFT_STATIS_BT_HI_RX_8822C) +#define BIT_CLEAR_STATIS_BT_HI_RX_8822C(x) ((x) & (~BITS_STATIS_BT_HI_RX_8822C)) +#define BIT_GET_STATIS_BT_HI_RX_8822C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822C) & \ + BIT_MASK_STATIS_BT_HI_RX_8822C) +#define BIT_SET_STATIS_BT_HI_RX_8822C(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_RX_8822C(x) | BIT_STATIS_BT_HI_RX_8822C(v)) + +#define BIT_SHIFT_STATIS_BT_HI_TX_8822C 0 +#define BIT_MASK_STATIS_BT_HI_TX_8822C 0xffff +#define BIT_STATIS_BT_HI_TX_8822C(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_TX_8822C) \ + << BIT_SHIFT_STATIS_BT_HI_TX_8822C) +#define BITS_STATIS_BT_HI_TX_8822C \ + (BIT_MASK_STATIS_BT_HI_TX_8822C << BIT_SHIFT_STATIS_BT_HI_TX_8822C) +#define BIT_CLEAR_STATIS_BT_HI_TX_8822C(x) ((x) & (~BITS_STATIS_BT_HI_TX_8822C)) +#define BIT_GET_STATIS_BT_HI_TX_8822C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822C) & \ + BIT_MASK_STATIS_BT_HI_TX_8822C) +#define BIT_SET_STATIS_BT_HI_TX_8822C(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_TX_8822C(x) | BIT_STATIS_BT_HI_TX_8822C(v)) + +/* 2 REG_BT_ACT_STATISTICS_1_8822C */ + +#define BIT_SHIFT_STATIS_BT_LO_RX_1_8822C 16 +#define BIT_MASK_STATIS_BT_LO_RX_1_8822C 0xffff +#define BIT_STATIS_BT_LO_RX_1_8822C(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8822C) \ + << BIT_SHIFT_STATIS_BT_LO_RX_1_8822C) +#define BITS_STATIS_BT_LO_RX_1_8822C \ + (BIT_MASK_STATIS_BT_LO_RX_1_8822C << BIT_SHIFT_STATIS_BT_LO_RX_1_8822C) +#define BIT_CLEAR_STATIS_BT_LO_RX_1_8822C(x) \ + ((x) & (~BITS_STATIS_BT_LO_RX_1_8822C)) +#define BIT_GET_STATIS_BT_LO_RX_1_8822C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8822C) & \ + BIT_MASK_STATIS_BT_LO_RX_1_8822C) +#define BIT_SET_STATIS_BT_LO_RX_1_8822C(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX_1_8822C(x) | BIT_STATIS_BT_LO_RX_1_8822C(v)) + +#define BIT_SHIFT_STATIS_BT_LO_TX_1_8822C 0 +#define BIT_MASK_STATIS_BT_LO_TX_1_8822C 0xffff +#define BIT_STATIS_BT_LO_TX_1_8822C(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8822C) \ + << BIT_SHIFT_STATIS_BT_LO_TX_1_8822C) +#define BITS_STATIS_BT_LO_TX_1_8822C \ + (BIT_MASK_STATIS_BT_LO_TX_1_8822C << BIT_SHIFT_STATIS_BT_LO_TX_1_8822C) +#define BIT_CLEAR_STATIS_BT_LO_TX_1_8822C(x) \ + ((x) & (~BITS_STATIS_BT_LO_TX_1_8822C)) +#define BIT_GET_STATIS_BT_LO_TX_1_8822C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8822C) & \ + BIT_MASK_STATIS_BT_LO_TX_1_8822C) +#define BIT_SET_STATIS_BT_LO_TX_1_8822C(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX_1_8822C(x) | BIT_STATIS_BT_LO_TX_1_8822C(v)) + +/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8822C */ + +#define BIT_SHIFT_R_BT_CMD_RPT_8822C 16 +#define BIT_MASK_R_BT_CMD_RPT_8822C 0xffff +#define BIT_R_BT_CMD_RPT_8822C(x) \ + (((x) & BIT_MASK_R_BT_CMD_RPT_8822C) << BIT_SHIFT_R_BT_CMD_RPT_8822C) +#define BITS_R_BT_CMD_RPT_8822C \ + (BIT_MASK_R_BT_CMD_RPT_8822C << BIT_SHIFT_R_BT_CMD_RPT_8822C) +#define BIT_CLEAR_R_BT_CMD_RPT_8822C(x) ((x) & (~BITS_R_BT_CMD_RPT_8822C)) +#define BIT_GET_R_BT_CMD_RPT_8822C(x) \ + (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822C) & BIT_MASK_R_BT_CMD_RPT_8822C) +#define BIT_SET_R_BT_CMD_RPT_8822C(x, v) \ + (BIT_CLEAR_R_BT_CMD_RPT_8822C(x) | BIT_R_BT_CMD_RPT_8822C(v)) + +#define BIT_SHIFT_R_RPT_FROM_BT_8822C 8 +#define BIT_MASK_R_RPT_FROM_BT_8822C 0xff +#define BIT_R_RPT_FROM_BT_8822C(x) \ + (((x) & BIT_MASK_R_RPT_FROM_BT_8822C) << BIT_SHIFT_R_RPT_FROM_BT_8822C) +#define BITS_R_RPT_FROM_BT_8822C \ + (BIT_MASK_R_RPT_FROM_BT_8822C << BIT_SHIFT_R_RPT_FROM_BT_8822C) +#define BIT_CLEAR_R_RPT_FROM_BT_8822C(x) ((x) & (~BITS_R_RPT_FROM_BT_8822C)) +#define BIT_GET_R_RPT_FROM_BT_8822C(x) \ + (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822C) & BIT_MASK_R_RPT_FROM_BT_8822C) +#define BIT_SET_R_RPT_FROM_BT_8822C(x, v) \ + (BIT_CLEAR_R_RPT_FROM_BT_8822C(x) | BIT_R_RPT_FROM_BT_8822C(v)) + +#define BIT_SHIFT_BT_HID_ISR_SET_8822C 6 +#define BIT_MASK_BT_HID_ISR_SET_8822C 0x3 +#define BIT_BT_HID_ISR_SET_8822C(x) \ + (((x) & BIT_MASK_BT_HID_ISR_SET_8822C) \ + << BIT_SHIFT_BT_HID_ISR_SET_8822C) +#define BITS_BT_HID_ISR_SET_8822C \ + (BIT_MASK_BT_HID_ISR_SET_8822C << BIT_SHIFT_BT_HID_ISR_SET_8822C) +#define BIT_CLEAR_BT_HID_ISR_SET_8822C(x) ((x) & (~BITS_BT_HID_ISR_SET_8822C)) +#define BIT_GET_BT_HID_ISR_SET_8822C(x) \ + (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822C) & \ + BIT_MASK_BT_HID_ISR_SET_8822C) +#define BIT_SET_BT_HID_ISR_SET_8822C(x, v) \ + (BIT_CLEAR_BT_HID_ISR_SET_8822C(x) | BIT_BT_HID_ISR_SET_8822C(v)) + +#define BIT_TDMA_BT_START_NOTIFY_8822C BIT(5) +#define BIT_ENABLE_TDMA_FW_MODE_8822C BIT(4) +#define BIT_ENABLE_PTA_TDMA_MODE_8822C BIT(3) +#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8822C BIT(2) +#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8822C BIT(1) +#define BIT_RTK_BT_ENABLE_8822C BIT(0) + +/* 2 REG_BT_STATUS_REPORT_REGISTER_8822C */ + +#define BIT_SHIFT_BT_PROFILE_8822C 24 +#define BIT_MASK_BT_PROFILE_8822C 0xff +#define BIT_BT_PROFILE_8822C(x) \ + (((x) & BIT_MASK_BT_PROFILE_8822C) << BIT_SHIFT_BT_PROFILE_8822C) +#define BITS_BT_PROFILE_8822C \ + (BIT_MASK_BT_PROFILE_8822C << BIT_SHIFT_BT_PROFILE_8822C) +#define BIT_CLEAR_BT_PROFILE_8822C(x) ((x) & (~BITS_BT_PROFILE_8822C)) +#define BIT_GET_BT_PROFILE_8822C(x) \ + (((x) >> BIT_SHIFT_BT_PROFILE_8822C) & BIT_MASK_BT_PROFILE_8822C) +#define BIT_SET_BT_PROFILE_8822C(x, v) \ + (BIT_CLEAR_BT_PROFILE_8822C(x) | BIT_BT_PROFILE_8822C(v)) + +#define BIT_SHIFT_BT_POWER_8822C 16 +#define BIT_MASK_BT_POWER_8822C 0xff +#define BIT_BT_POWER_8822C(x) \ + (((x) & BIT_MASK_BT_POWER_8822C) << BIT_SHIFT_BT_POWER_8822C) +#define BITS_BT_POWER_8822C \ + (BIT_MASK_BT_POWER_8822C << BIT_SHIFT_BT_POWER_8822C) +#define BIT_CLEAR_BT_POWER_8822C(x) ((x) & (~BITS_BT_POWER_8822C)) +#define BIT_GET_BT_POWER_8822C(x) \ + (((x) >> BIT_SHIFT_BT_POWER_8822C) & BIT_MASK_BT_POWER_8822C) +#define BIT_SET_BT_POWER_8822C(x, v) \ + (BIT_CLEAR_BT_POWER_8822C(x) | BIT_BT_POWER_8822C(v)) + +#define BIT_SHIFT_BT_PREDECT_STATUS_8822C 8 +#define BIT_MASK_BT_PREDECT_STATUS_8822C 0xff +#define BIT_BT_PREDECT_STATUS_8822C(x) \ + (((x) & BIT_MASK_BT_PREDECT_STATUS_8822C) \ + << BIT_SHIFT_BT_PREDECT_STATUS_8822C) +#define BITS_BT_PREDECT_STATUS_8822C \ + (BIT_MASK_BT_PREDECT_STATUS_8822C << BIT_SHIFT_BT_PREDECT_STATUS_8822C) +#define BIT_CLEAR_BT_PREDECT_STATUS_8822C(x) \ + ((x) & (~BITS_BT_PREDECT_STATUS_8822C)) +#define BIT_GET_BT_PREDECT_STATUS_8822C(x) \ + (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822C) & \ + BIT_MASK_BT_PREDECT_STATUS_8822C) +#define BIT_SET_BT_PREDECT_STATUS_8822C(x, v) \ + (BIT_CLEAR_BT_PREDECT_STATUS_8822C(x) | BIT_BT_PREDECT_STATUS_8822C(v)) + +#define BIT_SHIFT_BT_CMD_INFO_8822C 0 +#define BIT_MASK_BT_CMD_INFO_8822C 0xff +#define BIT_BT_CMD_INFO_8822C(x) \ + (((x) & BIT_MASK_BT_CMD_INFO_8822C) << BIT_SHIFT_BT_CMD_INFO_8822C) +#define BITS_BT_CMD_INFO_8822C \ + (BIT_MASK_BT_CMD_INFO_8822C << BIT_SHIFT_BT_CMD_INFO_8822C) +#define BIT_CLEAR_BT_CMD_INFO_8822C(x) ((x) & (~BITS_BT_CMD_INFO_8822C)) +#define BIT_GET_BT_CMD_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_BT_CMD_INFO_8822C) & BIT_MASK_BT_CMD_INFO_8822C) +#define BIT_SET_BT_CMD_INFO_8822C(x, v) \ + (BIT_CLEAR_BT_CMD_INFO_8822C(x) | BIT_BT_CMD_INFO_8822C(v)) + +/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8822C */ +#define BIT_EN_MAC_NULL_PKT_NOTIFY_8822C BIT(31) +#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8822C BIT(30) +#define BIT_EN_BT_STSTUS_RPT_8822C BIT(29) +#define BIT_EN_BT_POWER_8822C BIT(28) +#define BIT_EN_BT_CHANNEL_8822C BIT(27) +#define BIT_EN_BT_SLOT_CHANGE_8822C BIT(26) +#define BIT_EN_BT_PROFILE_OR_HID_8822C BIT(25) +#define BIT_WLAN_RPT_NOTIFY_8822C BIT(24) + +#define BIT_SHIFT_WLAN_RPT_DATA_8822C 16 +#define BIT_MASK_WLAN_RPT_DATA_8822C 0xff +#define BIT_WLAN_RPT_DATA_8822C(x) \ + (((x) & BIT_MASK_WLAN_RPT_DATA_8822C) << BIT_SHIFT_WLAN_RPT_DATA_8822C) +#define BITS_WLAN_RPT_DATA_8822C \ + (BIT_MASK_WLAN_RPT_DATA_8822C << BIT_SHIFT_WLAN_RPT_DATA_8822C) +#define BIT_CLEAR_WLAN_RPT_DATA_8822C(x) ((x) & (~BITS_WLAN_RPT_DATA_8822C)) +#define BIT_GET_WLAN_RPT_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822C) & BIT_MASK_WLAN_RPT_DATA_8822C) +#define BIT_SET_WLAN_RPT_DATA_8822C(x, v) \ + (BIT_CLEAR_WLAN_RPT_DATA_8822C(x) | BIT_WLAN_RPT_DATA_8822C(v)) + +#define BIT_SHIFT_CMD_ID_8822C 8 +#define BIT_MASK_CMD_ID_8822C 0xff +#define BIT_CMD_ID_8822C(x) \ + (((x) & BIT_MASK_CMD_ID_8822C) << BIT_SHIFT_CMD_ID_8822C) +#define BITS_CMD_ID_8822C (BIT_MASK_CMD_ID_8822C << BIT_SHIFT_CMD_ID_8822C) +#define BIT_CLEAR_CMD_ID_8822C(x) ((x) & (~BITS_CMD_ID_8822C)) +#define BIT_GET_CMD_ID_8822C(x) \ + (((x) >> BIT_SHIFT_CMD_ID_8822C) & BIT_MASK_CMD_ID_8822C) +#define BIT_SET_CMD_ID_8822C(x, v) \ + (BIT_CLEAR_CMD_ID_8822C(x) | BIT_CMD_ID_8822C(v)) + +#define BIT_SHIFT_BT_DATA_8822C 0 +#define BIT_MASK_BT_DATA_8822C 0xff +#define BIT_BT_DATA_8822C(x) \ + (((x) & BIT_MASK_BT_DATA_8822C) << BIT_SHIFT_BT_DATA_8822C) +#define BITS_BT_DATA_8822C (BIT_MASK_BT_DATA_8822C << BIT_SHIFT_BT_DATA_8822C) +#define BIT_CLEAR_BT_DATA_8822C(x) ((x) & (~BITS_BT_DATA_8822C)) +#define BIT_GET_BT_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_BT_DATA_8822C) & BIT_MASK_BT_DATA_8822C) +#define BIT_SET_BT_DATA_8822C(x, v) \ + (BIT_CLEAR_BT_DATA_8822C(x) | BIT_BT_DATA_8822C(v)) + +/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822C */ + +#define BIT_SHIFT_WLAN_RPT_TO_8822C 0 +#define BIT_MASK_WLAN_RPT_TO_8822C 0xff +#define BIT_WLAN_RPT_TO_8822C(x) \ + (((x) & BIT_MASK_WLAN_RPT_TO_8822C) << BIT_SHIFT_WLAN_RPT_TO_8822C) +#define BITS_WLAN_RPT_TO_8822C \ + (BIT_MASK_WLAN_RPT_TO_8822C << BIT_SHIFT_WLAN_RPT_TO_8822C) +#define BIT_CLEAR_WLAN_RPT_TO_8822C(x) ((x) & (~BITS_WLAN_RPT_TO_8822C)) +#define BIT_GET_WLAN_RPT_TO_8822C(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_TO_8822C) & BIT_MASK_WLAN_RPT_TO_8822C) +#define BIT_SET_WLAN_RPT_TO_8822C(x, v) \ + (BIT_CLEAR_WLAN_RPT_TO_8822C(x) | BIT_WLAN_RPT_TO_8822C(v)) + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822C */ + +#define BIT_SHIFT_ISOLATION_CHK_0_8822C 1 +#define BIT_MASK_ISOLATION_CHK_0_8822C 0x7fffff +#define BIT_ISOLATION_CHK_0_8822C(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_0_8822C) \ + << BIT_SHIFT_ISOLATION_CHK_0_8822C) +#define BITS_ISOLATION_CHK_0_8822C \ + (BIT_MASK_ISOLATION_CHK_0_8822C << BIT_SHIFT_ISOLATION_CHK_0_8822C) +#define BIT_CLEAR_ISOLATION_CHK_0_8822C(x) ((x) & (~BITS_ISOLATION_CHK_0_8822C)) +#define BIT_GET_ISOLATION_CHK_0_8822C(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8822C) & \ + BIT_MASK_ISOLATION_CHK_0_8822C) +#define BIT_SET_ISOLATION_CHK_0_8822C(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_0_8822C(x) | BIT_ISOLATION_CHK_0_8822C(v)) + +#define BIT_ISOLATION_EN_8822C BIT(0) + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8822C */ + +#define BIT_SHIFT_ISOLATION_CHK_1_8822C 0 +#define BIT_MASK_ISOLATION_CHK_1_8822C 0xffffffffL +#define BIT_ISOLATION_CHK_1_8822C(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_1_8822C) \ + << BIT_SHIFT_ISOLATION_CHK_1_8822C) +#define BITS_ISOLATION_CHK_1_8822C \ + (BIT_MASK_ISOLATION_CHK_1_8822C << BIT_SHIFT_ISOLATION_CHK_1_8822C) +#define BIT_CLEAR_ISOLATION_CHK_1_8822C(x) ((x) & (~BITS_ISOLATION_CHK_1_8822C)) +#define BIT_GET_ISOLATION_CHK_1_8822C(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8822C) & \ + BIT_MASK_ISOLATION_CHK_1_8822C) +#define BIT_SET_ISOLATION_CHK_1_8822C(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_1_8822C(x) | BIT_ISOLATION_CHK_1_8822C(v)) + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8822C */ + +#define BIT_SHIFT_ISOLATION_CHK_2_8822C 0 +#define BIT_MASK_ISOLATION_CHK_2_8822C 0xffffff +#define BIT_ISOLATION_CHK_2_8822C(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_2_8822C) \ + << BIT_SHIFT_ISOLATION_CHK_2_8822C) +#define BITS_ISOLATION_CHK_2_8822C \ + (BIT_MASK_ISOLATION_CHK_2_8822C << BIT_SHIFT_ISOLATION_CHK_2_8822C) +#define BIT_CLEAR_ISOLATION_CHK_2_8822C(x) ((x) & (~BITS_ISOLATION_CHK_2_8822C)) +#define BIT_GET_ISOLATION_CHK_2_8822C(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8822C) & \ + BIT_MASK_ISOLATION_CHK_2_8822C) +#define BIT_SET_ISOLATION_CHK_2_8822C(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_2_8822C(x) | BIT_ISOLATION_CHK_2_8822C(v)) + +/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8822C */ +#define BIT_BT_HID_ISR_8822C BIT(7) +#define BIT_BT_QUERY_ISR_8822C BIT(6) +#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8822C BIT(5) +#define BIT_WLAN_RPT_ISR_8822C BIT(4) +#define BIT_BT_POWER_ISR_8822C BIT(3) +#define BIT_BT_CHANNEL_ISR_8822C BIT(2) +#define BIT_BT_SLOT_CHANGE_ISR_8822C BIT(1) +#define BIT_BT_PROFILE_ISR_8822C BIT(0) + +/* 2 REG_BT_TDMA_TIME_REGISTER_8822C */ + +#define BIT_SHIFT_BT_TIME_8822C 6 +#define BIT_MASK_BT_TIME_8822C 0x3ffffff +#define BIT_BT_TIME_8822C(x) \ + (((x) & BIT_MASK_BT_TIME_8822C) << BIT_SHIFT_BT_TIME_8822C) +#define BITS_BT_TIME_8822C (BIT_MASK_BT_TIME_8822C << BIT_SHIFT_BT_TIME_8822C) +#define BIT_CLEAR_BT_TIME_8822C(x) ((x) & (~BITS_BT_TIME_8822C)) +#define BIT_GET_BT_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_BT_TIME_8822C) & BIT_MASK_BT_TIME_8822C) +#define BIT_SET_BT_TIME_8822C(x, v) \ + (BIT_CLEAR_BT_TIME_8822C(x) | BIT_BT_TIME_8822C(v)) + +#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C 0 +#define BIT_MASK_BT_RPT_SAMPLE_RATE_8822C 0x3f +#define BIT_BT_RPT_SAMPLE_RATE_8822C(x) \ + (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822C) \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C) +#define BITS_BT_RPT_SAMPLE_RATE_8822C \ + (BIT_MASK_BT_RPT_SAMPLE_RATE_8822C \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822C(x) \ + ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8822C)) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8822C(x) \ + (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C) & \ + BIT_MASK_BT_RPT_SAMPLE_RATE_8822C) +#define BIT_SET_BT_RPT_SAMPLE_RATE_8822C(x, v) \ + (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822C(x) | \ + BIT_BT_RPT_SAMPLE_RATE_8822C(v)) + +/* 2 REG_BT_ACT_REGISTER_8822C */ + +#define BIT_SHIFT_BT_EISR_EN_8822C 16 +#define BIT_MASK_BT_EISR_EN_8822C 0xff +#define BIT_BT_EISR_EN_8822C(x) \ + (((x) & BIT_MASK_BT_EISR_EN_8822C) << BIT_SHIFT_BT_EISR_EN_8822C) +#define BITS_BT_EISR_EN_8822C \ + (BIT_MASK_BT_EISR_EN_8822C << BIT_SHIFT_BT_EISR_EN_8822C) +#define BIT_CLEAR_BT_EISR_EN_8822C(x) ((x) & (~BITS_BT_EISR_EN_8822C)) +#define BIT_GET_BT_EISR_EN_8822C(x) \ + (((x) >> BIT_SHIFT_BT_EISR_EN_8822C) & BIT_MASK_BT_EISR_EN_8822C) +#define BIT_SET_BT_EISR_EN_8822C(x, v) \ + (BIT_CLEAR_BT_EISR_EN_8822C(x) | BIT_BT_EISR_EN_8822C(v)) + +#define BIT_BT_ACT_FALLING_ISR_8822C BIT(10) +#define BIT_BT_ACT_RISING_ISR_8822C BIT(9) +#define BIT_TDMA_TO_ISR_8822C BIT(8) + +#define BIT_SHIFT_BT_CH_V1_8822C 0 +#define BIT_MASK_BT_CH_V1_8822C 0x7f +#define BIT_BT_CH_V1_8822C(x) \ + (((x) & BIT_MASK_BT_CH_V1_8822C) << BIT_SHIFT_BT_CH_V1_8822C) +#define BITS_BT_CH_V1_8822C \ + (BIT_MASK_BT_CH_V1_8822C << BIT_SHIFT_BT_CH_V1_8822C) +#define BIT_CLEAR_BT_CH_V1_8822C(x) ((x) & (~BITS_BT_CH_V1_8822C)) +#define BIT_GET_BT_CH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BT_CH_V1_8822C) & BIT_MASK_BT_CH_V1_8822C) +#define BIT_SET_BT_CH_V1_8822C(x, v) \ + (BIT_CLEAR_BT_CH_V1_8822C(x) | BIT_BT_CH_V1_8822C(v)) + +/* 2 REG_OBFF_CTRL_BASIC_8822C */ +#define BIT_OBFF_EN_V1_8822C BIT(31) + +#define BIT_SHIFT_OBFF_STATE_V1_8822C 28 +#define BIT_MASK_OBFF_STATE_V1_8822C 0x3 +#define BIT_OBFF_STATE_V1_8822C(x) \ + (((x) & BIT_MASK_OBFF_STATE_V1_8822C) << BIT_SHIFT_OBFF_STATE_V1_8822C) +#define BITS_OBFF_STATE_V1_8822C \ + (BIT_MASK_OBFF_STATE_V1_8822C << BIT_SHIFT_OBFF_STATE_V1_8822C) +#define BIT_CLEAR_OBFF_STATE_V1_8822C(x) ((x) & (~BITS_OBFF_STATE_V1_8822C)) +#define BIT_GET_OBFF_STATE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_OBFF_STATE_V1_8822C) & BIT_MASK_OBFF_STATE_V1_8822C) +#define BIT_SET_OBFF_STATE_V1_8822C(x, v) \ + (BIT_CLEAR_OBFF_STATE_V1_8822C(x) | BIT_OBFF_STATE_V1_8822C(v)) + +#define BIT_OBFF_ACT_RXDMA_EN_8822C BIT(27) +#define BIT_OBFF_BLOCK_INT_EN_8822C BIT(26) +#define BIT_OBFF_AUTOACT_EN_8822C BIT(25) +#define BIT_OBFF_AUTOIDLE_EN_8822C BIT(24) + +#define BIT_SHIFT_WAKE_MAX_PLS_8822C 20 +#define BIT_MASK_WAKE_MAX_PLS_8822C 0x7 +#define BIT_WAKE_MAX_PLS_8822C(x) \ + (((x) & BIT_MASK_WAKE_MAX_PLS_8822C) << BIT_SHIFT_WAKE_MAX_PLS_8822C) +#define BITS_WAKE_MAX_PLS_8822C \ + (BIT_MASK_WAKE_MAX_PLS_8822C << BIT_SHIFT_WAKE_MAX_PLS_8822C) +#define BIT_CLEAR_WAKE_MAX_PLS_8822C(x) ((x) & (~BITS_WAKE_MAX_PLS_8822C)) +#define BIT_GET_WAKE_MAX_PLS_8822C(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822C) & BIT_MASK_WAKE_MAX_PLS_8822C) +#define BIT_SET_WAKE_MAX_PLS_8822C(x, v) \ + (BIT_CLEAR_WAKE_MAX_PLS_8822C(x) | BIT_WAKE_MAX_PLS_8822C(v)) + +#define BIT_SHIFT_WAKE_MIN_PLS_8822C 16 +#define BIT_MASK_WAKE_MIN_PLS_8822C 0x7 +#define BIT_WAKE_MIN_PLS_8822C(x) \ + (((x) & BIT_MASK_WAKE_MIN_PLS_8822C) << BIT_SHIFT_WAKE_MIN_PLS_8822C) +#define BITS_WAKE_MIN_PLS_8822C \ + (BIT_MASK_WAKE_MIN_PLS_8822C << BIT_SHIFT_WAKE_MIN_PLS_8822C) +#define BIT_CLEAR_WAKE_MIN_PLS_8822C(x) ((x) & (~BITS_WAKE_MIN_PLS_8822C)) +#define BIT_GET_WAKE_MIN_PLS_8822C(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822C) & BIT_MASK_WAKE_MIN_PLS_8822C) +#define BIT_SET_WAKE_MIN_PLS_8822C(x, v) \ + (BIT_CLEAR_WAKE_MIN_PLS_8822C(x) | BIT_WAKE_MIN_PLS_8822C(v)) + +#define BIT_SHIFT_WAKE_MAX_F2F_8822C 12 +#define BIT_MASK_WAKE_MAX_F2F_8822C 0x7 +#define BIT_WAKE_MAX_F2F_8822C(x) \ + (((x) & BIT_MASK_WAKE_MAX_F2F_8822C) << BIT_SHIFT_WAKE_MAX_F2F_8822C) +#define BITS_WAKE_MAX_F2F_8822C \ + (BIT_MASK_WAKE_MAX_F2F_8822C << BIT_SHIFT_WAKE_MAX_F2F_8822C) +#define BIT_CLEAR_WAKE_MAX_F2F_8822C(x) ((x) & (~BITS_WAKE_MAX_F2F_8822C)) +#define BIT_GET_WAKE_MAX_F2F_8822C(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822C) & BIT_MASK_WAKE_MAX_F2F_8822C) +#define BIT_SET_WAKE_MAX_F2F_8822C(x, v) \ + (BIT_CLEAR_WAKE_MAX_F2F_8822C(x) | BIT_WAKE_MAX_F2F_8822C(v)) + +#define BIT_SHIFT_WAKE_MIN_F2F_8822C 8 +#define BIT_MASK_WAKE_MIN_F2F_8822C 0x7 +#define BIT_WAKE_MIN_F2F_8822C(x) \ + (((x) & BIT_MASK_WAKE_MIN_F2F_8822C) << BIT_SHIFT_WAKE_MIN_F2F_8822C) +#define BITS_WAKE_MIN_F2F_8822C \ + (BIT_MASK_WAKE_MIN_F2F_8822C << BIT_SHIFT_WAKE_MIN_F2F_8822C) +#define BIT_CLEAR_WAKE_MIN_F2F_8822C(x) ((x) & (~BITS_WAKE_MIN_F2F_8822C)) +#define BIT_GET_WAKE_MIN_F2F_8822C(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822C) & BIT_MASK_WAKE_MIN_F2F_8822C) +#define BIT_SET_WAKE_MIN_F2F_8822C(x, v) \ + (BIT_CLEAR_WAKE_MIN_F2F_8822C(x) | BIT_WAKE_MIN_F2F_8822C(v)) + +#define BIT_APP_CPU_ACT_V1_8822C BIT(3) +#define BIT_APP_OBFF_V1_8822C BIT(2) +#define BIT_APP_IDLE_V1_8822C BIT(1) +#define BIT_APP_INIT_V1_8822C BIT(0) + +/* 2 REG_OBFF_CTRL2_TIMER_8822C */ + +#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C 24 +#define BIT_MASK_RX_HIGH_TIMER_IDX_8822C 0x7 +#define BIT_RX_HIGH_TIMER_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822C) \ + << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C) +#define BITS_RX_HIGH_TIMER_IDX_8822C \ + (BIT_MASK_RX_HIGH_TIMER_IDX_8822C << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8822C(x) \ + ((x) & (~BITS_RX_HIGH_TIMER_IDX_8822C)) +#define BIT_GET_RX_HIGH_TIMER_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C) & \ + BIT_MASK_RX_HIGH_TIMER_IDX_8822C) +#define BIT_SET_RX_HIGH_TIMER_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_HIGH_TIMER_IDX_8822C(x) | BIT_RX_HIGH_TIMER_IDX_8822C(v)) + +#define BIT_SHIFT_RX_MED_TIMER_IDX_8822C 16 +#define BIT_MASK_RX_MED_TIMER_IDX_8822C 0x7 +#define BIT_RX_MED_TIMER_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_MED_TIMER_IDX_8822C) \ + << BIT_SHIFT_RX_MED_TIMER_IDX_8822C) +#define BITS_RX_MED_TIMER_IDX_8822C \ + (BIT_MASK_RX_MED_TIMER_IDX_8822C << BIT_SHIFT_RX_MED_TIMER_IDX_8822C) +#define BIT_CLEAR_RX_MED_TIMER_IDX_8822C(x) \ + ((x) & (~BITS_RX_MED_TIMER_IDX_8822C)) +#define BIT_GET_RX_MED_TIMER_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822C) & \ + BIT_MASK_RX_MED_TIMER_IDX_8822C) +#define BIT_SET_RX_MED_TIMER_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_MED_TIMER_IDX_8822C(x) | BIT_RX_MED_TIMER_IDX_8822C(v)) + +#define BIT_SHIFT_RX_LOW_TIMER_IDX_8822C 8 +#define BIT_MASK_RX_LOW_TIMER_IDX_8822C 0x7 +#define BIT_RX_LOW_TIMER_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822C) \ + << BIT_SHIFT_RX_LOW_TIMER_IDX_8822C) +#define BITS_RX_LOW_TIMER_IDX_8822C \ + (BIT_MASK_RX_LOW_TIMER_IDX_8822C << BIT_SHIFT_RX_LOW_TIMER_IDX_8822C) +#define BIT_CLEAR_RX_LOW_TIMER_IDX_8822C(x) \ + ((x) & (~BITS_RX_LOW_TIMER_IDX_8822C)) +#define BIT_GET_RX_LOW_TIMER_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822C) & \ + BIT_MASK_RX_LOW_TIMER_IDX_8822C) +#define BIT_SET_RX_LOW_TIMER_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_LOW_TIMER_IDX_8822C(x) | BIT_RX_LOW_TIMER_IDX_8822C(v)) + +#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C 0 +#define BIT_MASK_OBFF_INT_TIMER_IDX_8822C 0x7 +#define BIT_OBFF_INT_TIMER_IDX_8822C(x) \ + (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822C) \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C) +#define BITS_OBFF_INT_TIMER_IDX_8822C \ + (BIT_MASK_OBFF_INT_TIMER_IDX_8822C \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8822C(x) \ + ((x) & (~BITS_OBFF_INT_TIMER_IDX_8822C)) +#define BIT_GET_OBFF_INT_TIMER_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C) & \ + BIT_MASK_OBFF_INT_TIMER_IDX_8822C) +#define BIT_SET_OBFF_INT_TIMER_IDX_8822C(x, v) \ + (BIT_CLEAR_OBFF_INT_TIMER_IDX_8822C(x) | \ + BIT_OBFF_INT_TIMER_IDX_8822C(v)) + +/* 2 REG_LTR_CTRL_BASIC_8822C */ +#define BIT_LTR_EN_V1_8822C BIT(31) +#define BIT_LTR_HW_EN_V1_8822C BIT(30) +#define BIT_LRT_ACT_CTS_EN_8822C BIT(29) +#define BIT_LTR_ACT_RXPKT_EN_8822C BIT(28) +#define BIT_LTR_ACT_RXDMA_EN_8822C BIT(27) +#define BIT_LTR_IDLE_NO_SNOOP_8822C BIT(26) +#define BIT_SPDUP_MGTPKT_8822C BIT(25) +#define BIT_RX_AGG_EN_8822C BIT(24) +#define BIT_APP_LTR_ACT_8822C BIT(23) +#define BIT_APP_LTR_IDLE_8822C BIT(22) + +#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C 20 +#define BIT_MASK_HIGH_RATE_TRIG_SEL_8822C 0x3 +#define BIT_HIGH_RATE_TRIG_SEL_8822C(x) \ + (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822C) \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C) +#define BITS_HIGH_RATE_TRIG_SEL_8822C \ + (BIT_MASK_HIGH_RATE_TRIG_SEL_8822C \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822C(x) \ + ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8822C)) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C) & \ + BIT_MASK_HIGH_RATE_TRIG_SEL_8822C) +#define BIT_SET_HIGH_RATE_TRIG_SEL_8822C(x, v) \ + (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822C(x) | \ + BIT_HIGH_RATE_TRIG_SEL_8822C(v)) + +#define BIT_SHIFT_MED_RATE_TRIG_SEL_8822C 18 +#define BIT_MASK_MED_RATE_TRIG_SEL_8822C 0x3 +#define BIT_MED_RATE_TRIG_SEL_8822C(x) \ + (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822C) \ + << BIT_SHIFT_MED_RATE_TRIG_SEL_8822C) +#define BITS_MED_RATE_TRIG_SEL_8822C \ + (BIT_MASK_MED_RATE_TRIG_SEL_8822C << BIT_SHIFT_MED_RATE_TRIG_SEL_8822C) +#define BIT_CLEAR_MED_RATE_TRIG_SEL_8822C(x) \ + ((x) & (~BITS_MED_RATE_TRIG_SEL_8822C)) +#define BIT_GET_MED_RATE_TRIG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822C) & \ + BIT_MASK_MED_RATE_TRIG_SEL_8822C) +#define BIT_SET_MED_RATE_TRIG_SEL_8822C(x, v) \ + (BIT_CLEAR_MED_RATE_TRIG_SEL_8822C(x) | BIT_MED_RATE_TRIG_SEL_8822C(v)) + +#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C 16 +#define BIT_MASK_LOW_RATE_TRIG_SEL_8822C 0x3 +#define BIT_LOW_RATE_TRIG_SEL_8822C(x) \ + (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822C) \ + << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C) +#define BITS_LOW_RATE_TRIG_SEL_8822C \ + (BIT_MASK_LOW_RATE_TRIG_SEL_8822C << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8822C(x) \ + ((x) & (~BITS_LOW_RATE_TRIG_SEL_8822C)) +#define BIT_GET_LOW_RATE_TRIG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C) & \ + BIT_MASK_LOW_RATE_TRIG_SEL_8822C) +#define BIT_SET_LOW_RATE_TRIG_SEL_8822C(x, v) \ + (BIT_CLEAR_LOW_RATE_TRIG_SEL_8822C(x) | BIT_LOW_RATE_TRIG_SEL_8822C(v)) + +#define BIT_SHIFT_HIGH_RATE_BD_IDX_8822C 8 +#define BIT_MASK_HIGH_RATE_BD_IDX_8822C 0x7f +#define BIT_HIGH_RATE_BD_IDX_8822C(x) \ + (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822C) \ + << BIT_SHIFT_HIGH_RATE_BD_IDX_8822C) +#define BITS_HIGH_RATE_BD_IDX_8822C \ + (BIT_MASK_HIGH_RATE_BD_IDX_8822C << BIT_SHIFT_HIGH_RATE_BD_IDX_8822C) +#define BIT_CLEAR_HIGH_RATE_BD_IDX_8822C(x) \ + ((x) & (~BITS_HIGH_RATE_BD_IDX_8822C)) +#define BIT_GET_HIGH_RATE_BD_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822C) & \ + BIT_MASK_HIGH_RATE_BD_IDX_8822C) +#define BIT_SET_HIGH_RATE_BD_IDX_8822C(x, v) \ + (BIT_CLEAR_HIGH_RATE_BD_IDX_8822C(x) | BIT_HIGH_RATE_BD_IDX_8822C(v)) + +#define BIT_SHIFT_LOW_RATE_BD_IDX_8822C 0 +#define BIT_MASK_LOW_RATE_BD_IDX_8822C 0x7f +#define BIT_LOW_RATE_BD_IDX_8822C(x) \ + (((x) & BIT_MASK_LOW_RATE_BD_IDX_8822C) \ + << BIT_SHIFT_LOW_RATE_BD_IDX_8822C) +#define BITS_LOW_RATE_BD_IDX_8822C \ + (BIT_MASK_LOW_RATE_BD_IDX_8822C << BIT_SHIFT_LOW_RATE_BD_IDX_8822C) +#define BIT_CLEAR_LOW_RATE_BD_IDX_8822C(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8822C)) +#define BIT_GET_LOW_RATE_BD_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822C) & \ + BIT_MASK_LOW_RATE_BD_IDX_8822C) +#define BIT_SET_LOW_RATE_BD_IDX_8822C(x, v) \ + (BIT_CLEAR_LOW_RATE_BD_IDX_8822C(x) | BIT_LOW_RATE_BD_IDX_8822C(v)) + +/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8822C */ + +#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C 24 +#define BIT_MASK_RX_EMPTY_TIMER_IDX_8822C 0x7 +#define BIT_RX_EMPTY_TIMER_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822C) \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C) +#define BITS_RX_EMPTY_TIMER_IDX_8822C \ + (BIT_MASK_RX_EMPTY_TIMER_IDX_8822C \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822C(x) \ + ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8822C)) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C) & \ + BIT_MASK_RX_EMPTY_TIMER_IDX_8822C) +#define BIT_SET_RX_EMPTY_TIMER_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822C(x) | \ + BIT_RX_EMPTY_TIMER_IDX_8822C(v)) + +#define BIT_SHIFT_RX_AFULL_TH_IDX_8822C 20 +#define BIT_MASK_RX_AFULL_TH_IDX_8822C 0x7 +#define BIT_RX_AFULL_TH_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_AFULL_TH_IDX_8822C) \ + << BIT_SHIFT_RX_AFULL_TH_IDX_8822C) +#define BITS_RX_AFULL_TH_IDX_8822C \ + (BIT_MASK_RX_AFULL_TH_IDX_8822C << BIT_SHIFT_RX_AFULL_TH_IDX_8822C) +#define BIT_CLEAR_RX_AFULL_TH_IDX_8822C(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8822C)) +#define BIT_GET_RX_AFULL_TH_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822C) & \ + BIT_MASK_RX_AFULL_TH_IDX_8822C) +#define BIT_SET_RX_AFULL_TH_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_AFULL_TH_IDX_8822C(x) | BIT_RX_AFULL_TH_IDX_8822C(v)) + +#define BIT_SHIFT_RX_HIGH_TH_IDX_8822C 16 +#define BIT_MASK_RX_HIGH_TH_IDX_8822C 0x7 +#define BIT_RX_HIGH_TH_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_HIGH_TH_IDX_8822C) \ + << BIT_SHIFT_RX_HIGH_TH_IDX_8822C) +#define BITS_RX_HIGH_TH_IDX_8822C \ + (BIT_MASK_RX_HIGH_TH_IDX_8822C << BIT_SHIFT_RX_HIGH_TH_IDX_8822C) +#define BIT_CLEAR_RX_HIGH_TH_IDX_8822C(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8822C)) +#define BIT_GET_RX_HIGH_TH_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822C) & \ + BIT_MASK_RX_HIGH_TH_IDX_8822C) +#define BIT_SET_RX_HIGH_TH_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_HIGH_TH_IDX_8822C(x) | BIT_RX_HIGH_TH_IDX_8822C(v)) + +#define BIT_SHIFT_RX_MED_TH_IDX_8822C 12 +#define BIT_MASK_RX_MED_TH_IDX_8822C 0x7 +#define BIT_RX_MED_TH_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_MED_TH_IDX_8822C) << BIT_SHIFT_RX_MED_TH_IDX_8822C) +#define BITS_RX_MED_TH_IDX_8822C \ + (BIT_MASK_RX_MED_TH_IDX_8822C << BIT_SHIFT_RX_MED_TH_IDX_8822C) +#define BIT_CLEAR_RX_MED_TH_IDX_8822C(x) ((x) & (~BITS_RX_MED_TH_IDX_8822C)) +#define BIT_GET_RX_MED_TH_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822C) & BIT_MASK_RX_MED_TH_IDX_8822C) +#define BIT_SET_RX_MED_TH_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_MED_TH_IDX_8822C(x) | BIT_RX_MED_TH_IDX_8822C(v)) + +#define BIT_SHIFT_RX_LOW_TH_IDX_8822C 8 +#define BIT_MASK_RX_LOW_TH_IDX_8822C 0x7 +#define BIT_RX_LOW_TH_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_LOW_TH_IDX_8822C) << BIT_SHIFT_RX_LOW_TH_IDX_8822C) +#define BITS_RX_LOW_TH_IDX_8822C \ + (BIT_MASK_RX_LOW_TH_IDX_8822C << BIT_SHIFT_RX_LOW_TH_IDX_8822C) +#define BIT_CLEAR_RX_LOW_TH_IDX_8822C(x) ((x) & (~BITS_RX_LOW_TH_IDX_8822C)) +#define BIT_GET_RX_LOW_TH_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822C) & BIT_MASK_RX_LOW_TH_IDX_8822C) +#define BIT_SET_RX_LOW_TH_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_LOW_TH_IDX_8822C(x) | BIT_RX_LOW_TH_IDX_8822C(v)) + +#define BIT_SHIFT_LTR_SPACE_IDX_8822C 4 +#define BIT_MASK_LTR_SPACE_IDX_8822C 0x3 +#define BIT_LTR_SPACE_IDX_8822C(x) \ + (((x) & BIT_MASK_LTR_SPACE_IDX_8822C) << BIT_SHIFT_LTR_SPACE_IDX_8822C) +#define BITS_LTR_SPACE_IDX_8822C \ + (BIT_MASK_LTR_SPACE_IDX_8822C << BIT_SHIFT_LTR_SPACE_IDX_8822C) +#define BIT_CLEAR_LTR_SPACE_IDX_8822C(x) ((x) & (~BITS_LTR_SPACE_IDX_8822C)) +#define BIT_GET_LTR_SPACE_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822C) & BIT_MASK_LTR_SPACE_IDX_8822C) +#define BIT_SET_LTR_SPACE_IDX_8822C(x, v) \ + (BIT_CLEAR_LTR_SPACE_IDX_8822C(x) | BIT_LTR_SPACE_IDX_8822C(v)) + +#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C 0 +#define BIT_MASK_LTR_IDLE_TIMER_IDX_8822C 0x7 +#define BIT_LTR_IDLE_TIMER_IDX_8822C(x) \ + (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822C) \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C) +#define BITS_LTR_IDLE_TIMER_IDX_8822C \ + (BIT_MASK_LTR_IDLE_TIMER_IDX_8822C \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822C(x) \ + ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8822C)) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C) & \ + BIT_MASK_LTR_IDLE_TIMER_IDX_8822C) +#define BIT_SET_LTR_IDLE_TIMER_IDX_8822C(x, v) \ + (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822C(x) | \ + BIT_LTR_IDLE_TIMER_IDX_8822C(v)) + +/* 2 REG_LTR_IDLE_LATENCY_V1_8822C */ + +#define BIT_SHIFT_LTR_IDLE_L_8822C 0 +#define BIT_MASK_LTR_IDLE_L_8822C 0xffffffffL +#define BIT_LTR_IDLE_L_8822C(x) \ + (((x) & BIT_MASK_LTR_IDLE_L_8822C) << BIT_SHIFT_LTR_IDLE_L_8822C) +#define BITS_LTR_IDLE_L_8822C \ + (BIT_MASK_LTR_IDLE_L_8822C << BIT_SHIFT_LTR_IDLE_L_8822C) +#define BIT_CLEAR_LTR_IDLE_L_8822C(x) ((x) & (~BITS_LTR_IDLE_L_8822C)) +#define BIT_GET_LTR_IDLE_L_8822C(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_L_8822C) & BIT_MASK_LTR_IDLE_L_8822C) +#define BIT_SET_LTR_IDLE_L_8822C(x, v) \ + (BIT_CLEAR_LTR_IDLE_L_8822C(x) | BIT_LTR_IDLE_L_8822C(v)) + +/* 2 REG_LTR_ACTIVE_LATENCY_V1_8822C */ + +#define BIT_SHIFT_LTR_ACT_L_8822C 0 +#define BIT_MASK_LTR_ACT_L_8822C 0xffffffffL +#define BIT_LTR_ACT_L_8822C(x) \ + (((x) & BIT_MASK_LTR_ACT_L_8822C) << BIT_SHIFT_LTR_ACT_L_8822C) +#define BITS_LTR_ACT_L_8822C \ + (BIT_MASK_LTR_ACT_L_8822C << BIT_SHIFT_LTR_ACT_L_8822C) +#define BIT_CLEAR_LTR_ACT_L_8822C(x) ((x) & (~BITS_LTR_ACT_L_8822C)) +#define BIT_GET_LTR_ACT_L_8822C(x) \ + (((x) >> BIT_SHIFT_LTR_ACT_L_8822C) & BIT_MASK_LTR_ACT_L_8822C) +#define BIT_SET_LTR_ACT_L_8822C(x, v) \ + (BIT_CLEAR_LTR_ACT_L_8822C(x) | BIT_LTR_ACT_L_8822C(v)) + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822C */ + +#define BIT_SHIFT_TRAIN_STA_ADDR_0_8822C 0 +#define BIT_MASK_TRAIN_STA_ADDR_0_8822C 0xffffffffL +#define BIT_TRAIN_STA_ADDR_0_8822C(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8822C) \ + << BIT_SHIFT_TRAIN_STA_ADDR_0_8822C) +#define BITS_TRAIN_STA_ADDR_0_8822C \ + (BIT_MASK_TRAIN_STA_ADDR_0_8822C << BIT_SHIFT_TRAIN_STA_ADDR_0_8822C) +#define BIT_CLEAR_TRAIN_STA_ADDR_0_8822C(x) \ + ((x) & (~BITS_TRAIN_STA_ADDR_0_8822C)) +#define BIT_GET_TRAIN_STA_ADDR_0_8822C(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8822C) & \ + BIT_MASK_TRAIN_STA_ADDR_0_8822C) +#define BIT_SET_TRAIN_STA_ADDR_0_8822C(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_0_8822C(x) | BIT_TRAIN_STA_ADDR_0_8822C(v)) + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8822C */ +#define BIT_ANTTRN_SWITCH_8822C BIT(19) +#define BIT_APPEND_MACID_IN_RESP_EN_1_8822C BIT(18) +#define BIT_ADDR2_MATCH_EN_1_8822C BIT(17) +#define BIT_ANTTRN_EN_1_8822C BIT(16) + +#define BIT_SHIFT_TRAIN_STA_ADDR_1_8822C 0 +#define BIT_MASK_TRAIN_STA_ADDR_1_8822C 0xffff +#define BIT_TRAIN_STA_ADDR_1_8822C(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8822C) \ + << BIT_SHIFT_TRAIN_STA_ADDR_1_8822C) +#define BITS_TRAIN_STA_ADDR_1_8822C \ + (BIT_MASK_TRAIN_STA_ADDR_1_8822C << BIT_SHIFT_TRAIN_STA_ADDR_1_8822C) +#define BIT_CLEAR_TRAIN_STA_ADDR_1_8822C(x) \ + ((x) & (~BITS_TRAIN_STA_ADDR_1_8822C)) +#define BIT_GET_TRAIN_STA_ADDR_1_8822C(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8822C) & \ + BIT_MASK_TRAIN_STA_ADDR_1_8822C) +#define BIT_SET_TRAIN_STA_ADDR_1_8822C(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_1_8822C(x) | BIT_TRAIN_STA_ADDR_1_8822C(v)) + +/* 2 REG_WMAC_PKTCNT_RWD_8822C */ + +#define BIT_SHIFT_PKTCNT_BSSIDMAP_8822C 4 +#define BIT_MASK_PKTCNT_BSSIDMAP_8822C 0xf +#define BIT_PKTCNT_BSSIDMAP_8822C(x) \ + (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822C) \ + << BIT_SHIFT_PKTCNT_BSSIDMAP_8822C) +#define BITS_PKTCNT_BSSIDMAP_8822C \ + (BIT_MASK_PKTCNT_BSSIDMAP_8822C << BIT_SHIFT_PKTCNT_BSSIDMAP_8822C) +#define BIT_CLEAR_PKTCNT_BSSIDMAP_8822C(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8822C)) +#define BIT_GET_PKTCNT_BSSIDMAP_8822C(x) \ + (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822C) & \ + BIT_MASK_PKTCNT_BSSIDMAP_8822C) +#define BIT_SET_PKTCNT_BSSIDMAP_8822C(x, v) \ + (BIT_CLEAR_PKTCNT_BSSIDMAP_8822C(x) | BIT_PKTCNT_BSSIDMAP_8822C(v)) + +#define BIT_PKTCNT_CNTRST_8822C BIT(1) +#define BIT_PKTCNT_CNTEN_8822C BIT(0) + +/* 2 REG_WMAC_PKTCNT_CTRL_8822C */ +#define BIT_WMAC_PKTCNT_TRST_8822C BIT(9) +#define BIT_WMAC_PKTCNT_FEN_8822C BIT(8) + +#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C 0 +#define BIT_MASK_WMAC_PKTCNT_CFGAD_8822C 0xff +#define BIT_WMAC_PKTCNT_CFGAD_8822C(x) \ + (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822C) \ + << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C) +#define BITS_WMAC_PKTCNT_CFGAD_8822C \ + (BIT_MASK_WMAC_PKTCNT_CFGAD_8822C << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C) +#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822C(x) \ + ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8822C)) +#define BIT_GET_WMAC_PKTCNT_CFGAD_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C) & \ + BIT_MASK_WMAC_PKTCNT_CFGAD_8822C) +#define BIT_SET_WMAC_PKTCNT_CFGAD_8822C(x, v) \ + (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822C(x) | BIT_WMAC_PKTCNT_CFGAD_8822C(v)) + +/* 2 REG_IQ_DUMP_8822C */ + +#define BIT_SHIFT_DUMP_OK_ADDR_8822C 16 +#define BIT_MASK_DUMP_OK_ADDR_8822C 0xffff +#define BIT_DUMP_OK_ADDR_8822C(x) \ + (((x) & BIT_MASK_DUMP_OK_ADDR_8822C) << BIT_SHIFT_DUMP_OK_ADDR_8822C) +#define BITS_DUMP_OK_ADDR_8822C \ + (BIT_MASK_DUMP_OK_ADDR_8822C << BIT_SHIFT_DUMP_OK_ADDR_8822C) +#define BIT_CLEAR_DUMP_OK_ADDR_8822C(x) ((x) & (~BITS_DUMP_OK_ADDR_8822C)) +#define BIT_GET_DUMP_OK_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822C) & BIT_MASK_DUMP_OK_ADDR_8822C) +#define BIT_SET_DUMP_OK_ADDR_8822C(x, v) \ + (BIT_CLEAR_DUMP_OK_ADDR_8822C(x) | BIT_DUMP_OK_ADDR_8822C(v)) + +#define BIT_MACDBG_TRIG_IQDUMP_8822C BIT(15) + +#define BIT_SHIFT_R_TRIG_TIME_SEL_8822C 8 +#define BIT_MASK_R_TRIG_TIME_SEL_8822C 0x7f +#define BIT_R_TRIG_TIME_SEL_8822C(x) \ + (((x) & BIT_MASK_R_TRIG_TIME_SEL_8822C) \ + << BIT_SHIFT_R_TRIG_TIME_SEL_8822C) +#define BITS_R_TRIG_TIME_SEL_8822C \ + (BIT_MASK_R_TRIG_TIME_SEL_8822C << BIT_SHIFT_R_TRIG_TIME_SEL_8822C) +#define BIT_CLEAR_R_TRIG_TIME_SEL_8822C(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8822C)) +#define BIT_GET_R_TRIG_TIME_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822C) & \ + BIT_MASK_R_TRIG_TIME_SEL_8822C) +#define BIT_SET_R_TRIG_TIME_SEL_8822C(x, v) \ + (BIT_CLEAR_R_TRIG_TIME_SEL_8822C(x) | BIT_R_TRIG_TIME_SEL_8822C(v)) + +#define BIT_SHIFT_R_MAC_TRIG_SEL_8822C 6 +#define BIT_MASK_R_MAC_TRIG_SEL_8822C 0x3 +#define BIT_R_MAC_TRIG_SEL_8822C(x) \ + (((x) & BIT_MASK_R_MAC_TRIG_SEL_8822C) \ + << BIT_SHIFT_R_MAC_TRIG_SEL_8822C) +#define BITS_R_MAC_TRIG_SEL_8822C \ + (BIT_MASK_R_MAC_TRIG_SEL_8822C << BIT_SHIFT_R_MAC_TRIG_SEL_8822C) +#define BIT_CLEAR_R_MAC_TRIG_SEL_8822C(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8822C)) +#define BIT_GET_R_MAC_TRIG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822C) & \ + BIT_MASK_R_MAC_TRIG_SEL_8822C) +#define BIT_SET_R_MAC_TRIG_SEL_8822C(x, v) \ + (BIT_CLEAR_R_MAC_TRIG_SEL_8822C(x) | BIT_R_MAC_TRIG_SEL_8822C(v)) + +#define BIT_MAC_TRIG_REG_8822C BIT(5) + +#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C 3 +#define BIT_MASK_R_LEVEL_PULSE_SEL_8822C 0x3 +#define BIT_R_LEVEL_PULSE_SEL_8822C(x) \ + (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822C) \ + << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C) +#define BITS_R_LEVEL_PULSE_SEL_8822C \ + (BIT_MASK_R_LEVEL_PULSE_SEL_8822C << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8822C(x) \ + ((x) & (~BITS_R_LEVEL_PULSE_SEL_8822C)) +#define BIT_GET_R_LEVEL_PULSE_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C) & \ + BIT_MASK_R_LEVEL_PULSE_SEL_8822C) +#define BIT_SET_R_LEVEL_PULSE_SEL_8822C(x, v) \ + (BIT_CLEAR_R_LEVEL_PULSE_SEL_8822C(x) | BIT_R_LEVEL_PULSE_SEL_8822C(v)) + +#define BIT_EN_LA_MAC_8822C BIT(2) +#define BIT_R_EN_IQDUMP_8822C BIT(1) +#define BIT_R_IQDATA_DUMP_8822C BIT(0) + +/* 2 REG_IQ_DUMP_1_8822C */ + +#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C 0 +#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C 0xffffffffL +#define BIT_R_WMAC_MASK_LA_MAC_1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C) \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C) +#define BITS_R_WMAC_MASK_LA_MAC_1_8822C \ + (BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8822C(x) \ + ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8822C)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C) & \ + BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C) +#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8822C(x) | \ + BIT_R_WMAC_MASK_LA_MAC_1_8822C(v)) + +/* 2 REG_IQ_DUMP_2_8822C */ + +#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C 0 +#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C 0xffffffffL +#define BIT_R_WMAC_MATCH_REF_MAC_2_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C) +#define BITS_R_WMAC_MATCH_REF_MAC_2_8822C \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8822C(x) \ + ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8822C)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8822C(x) | \ + BIT_R_WMAC_MATCH_REF_MAC_2_8822C(v)) + +/* 2 REG_WMAC_FTM_CTL_8822C */ +#define BIT_RXFTM_TXACK_SC_8822C BIT(6) +#define BIT_RXFTM_TXACK_BW_8822C BIT(5) +#define BIT_RXFTM_EN_8822C BIT(3) +#define BIT_RXFTMREQ_BYDRV_8822C BIT(2) +#define BIT_RXFTMREQ_EN_8822C BIT(1) +#define BIT_FTM_EN_8822C BIT(0) + +/* 2 REG_WMAC_IQ_MDPK_FUNC_8822C */ + +/* 2 REG_WMAC_OPTION_FUNCTION_8822C */ + +#define BIT_SHIFT_R_OFDM_LEN_V1_8822C 16 +#define BIT_MASK_R_OFDM_LEN_V1_8822C 0xffff +#define BIT_R_OFDM_LEN_V1_8822C(x) \ + (((x) & BIT_MASK_R_OFDM_LEN_V1_8822C) << BIT_SHIFT_R_OFDM_LEN_V1_8822C) +#define BITS_R_OFDM_LEN_V1_8822C \ + (BIT_MASK_R_OFDM_LEN_V1_8822C << BIT_SHIFT_R_OFDM_LEN_V1_8822C) +#define BIT_CLEAR_R_OFDM_LEN_V1_8822C(x) ((x) & (~BITS_R_OFDM_LEN_V1_8822C)) +#define BIT_GET_R_OFDM_LEN_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN_V1_8822C) & BIT_MASK_R_OFDM_LEN_V1_8822C) +#define BIT_SET_R_OFDM_LEN_V1_8822C(x, v) \ + (BIT_CLEAR_R_OFDM_LEN_V1_8822C(x) | BIT_R_OFDM_LEN_V1_8822C(v)) + +#define BIT_SHIFT_R_CCK_LEN_8822C 0 +#define BIT_MASK_R_CCK_LEN_8822C 0xffff +#define BIT_R_CCK_LEN_8822C(x) \ + (((x) & BIT_MASK_R_CCK_LEN_8822C) << BIT_SHIFT_R_CCK_LEN_8822C) +#define BITS_R_CCK_LEN_8822C \ + (BIT_MASK_R_CCK_LEN_8822C << BIT_SHIFT_R_CCK_LEN_8822C) +#define BIT_CLEAR_R_CCK_LEN_8822C(x) ((x) & (~BITS_R_CCK_LEN_8822C)) +#define BIT_GET_R_CCK_LEN_8822C(x) \ + (((x) >> BIT_SHIFT_R_CCK_LEN_8822C) & BIT_MASK_R_CCK_LEN_8822C) +#define BIT_SET_R_CCK_LEN_8822C(x, v) \ + (BIT_CLEAR_R_CCK_LEN_8822C(x) | BIT_R_CCK_LEN_8822C(v)) + +/* 2 REG_WMAC_OPTION_FUNCTION_1_8822C */ + +#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C 24 +#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C 0xff +#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C) +#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8822C \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) \ + ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8822C)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) | \ + BIT_R_WMAC_RXFIFO_FULL_TH_1_8822C(v)) + +#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8822C BIT(23) +#define BIT_R_WMAC_RXRST_DLY_1_8822C BIT(22) +#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8822C BIT(21) +#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8822C BIT(20) +#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8822C BIT(19) +#define BIT_R_WMAC_NDP_RST_1_8822C BIT(18) +#define BIT_R_WMAC_POWINT_EN_1_8822C BIT(17) +#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8822C BIT(16) +#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8822C BIT(15) +#define BIT_R_WMAC_PFIN_TOEN_1_8822C BIT(14) +#define BIT_R_WMAC_FIL_SECERR_1_8822C BIT(13) +#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8822C BIT(12) +#define BIT_R_WMAC_FIL_FCTYPE_1_8822C BIT(11) +#define BIT_R_WMAC_FIL_FCPROVER_1_8822C BIT(10) +#define BIT_R_WMAC_PHYSTS_SNIF_1_8822C BIT(9) +#define BIT_R_WMAC_PHYSTS_PLCP_1_8822C BIT(8) +#define BIT_R_MAC_TCR_VBONF_RD_1_8822C BIT(7) +#define BIT_R_WMAC_TCR_MPAR_NDP_1_8822C BIT(6) +#define BIT_R_WMAC_NDP_FILTER_1_8822C BIT(5) +#define BIT_R_WMAC_RXLEN_SEL_1_8822C BIT(4) +#define BIT_R_WMAC_RXLEN_SEL1_1_8822C BIT(3) +#define BIT_R_OFDM_FILTER_1_8822C BIT(2) +#define BIT_R_WMAC_CHK_OFDM_LEN_1_8822C BIT(1) +#define BIT_R_WMAC_CHK_CCK_LEN_1_8822C BIT(0) + +/* 2 REG_WMAC_OPTION_FUNCTION_2_8822C */ + +#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C 0 +#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C 0xffff +#define BIT_R_WMAC_RX_FIL_LEN_2_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C) \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C) +#define BITS_R_WMAC_RX_FIL_LEN_2_8822C \ + (BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8822C(x) \ + ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8822C)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C) & \ + BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C) +#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8822C(x) | \ + BIT_R_WMAC_RX_FIL_LEN_2_8822C(v)) + +/* 2 REG_RX_FILTER_FUNCTION_8822C */ +#define BIT_RXHANG_EN_8822C BIT(15) +#define BIT_R_WMAC_MHRDDY_LATCH_8822C BIT(14) +#define BIT_R_WMAC_MHRDDY_CLR_8822C BIT(13) +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8822C BIT(12) +#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8822C BIT(11) +#define BIT_R_CHK_DELIMIT_LEN_8822C BIT(10) +#define BIT_R_REAPTER_ADDR_MATCH_8822C BIT(9) +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8822C BIT(8) +#define BIT_R_LATCH_MACHRDY_8822C BIT(7) +#define BIT_R_WMAC_RXFIL_REND_8822C BIT(6) +#define BIT_R_WMAC_MPDURDY_CLR_8822C BIT(5) +#define BIT_R_WMAC_CLRRXSEC_8822C BIT(4) +#define BIT_R_WMAC_RXFIL_RDEL_8822C BIT(3) +#define BIT_R_WMAC_RXFIL_FCSE_8822C BIT(2) +#define BIT_R_WMAC_RXFIL_MESH_DEL_8822C BIT(1) +#define BIT_R_WMAC_RXFIL_MASKM_8822C BIT(0) + +/* 2 REG_NDP_SIG_8822C */ + +#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C 0 +#define BIT_MASK_R_WMAC_TXNDP_SIGB_8822C 0x1fffff +#define BIT_R_WMAC_TXNDP_SIGB_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822C) \ + << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C) +#define BITS_R_WMAC_TXNDP_SIGB_8822C \ + (BIT_MASK_R_WMAC_TXNDP_SIGB_8822C << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822C(x) \ + ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8822C)) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C) & \ + BIT_MASK_R_WMAC_TXNDP_SIGB_8822C) +#define BIT_SET_R_WMAC_TXNDP_SIGB_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822C(x) | BIT_R_WMAC_TXNDP_SIGB_8822C(v)) + +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8822C */ + +#define BIT_SHIFT_R_MAC_DBG_SHIFT_8822C 8 +#define BIT_MASK_R_MAC_DBG_SHIFT_8822C 0x7 +#define BIT_R_MAC_DBG_SHIFT_8822C(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822C) \ + << BIT_SHIFT_R_MAC_DBG_SHIFT_8822C) +#define BITS_R_MAC_DBG_SHIFT_8822C \ + (BIT_MASK_R_MAC_DBG_SHIFT_8822C << BIT_SHIFT_R_MAC_DBG_SHIFT_8822C) +#define BIT_CLEAR_R_MAC_DBG_SHIFT_8822C(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8822C)) +#define BIT_GET_R_MAC_DBG_SHIFT_8822C(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822C) & \ + BIT_MASK_R_MAC_DBG_SHIFT_8822C) +#define BIT_SET_R_MAC_DBG_SHIFT_8822C(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SHIFT_8822C(x) | BIT_R_MAC_DBG_SHIFT_8822C(v)) + +#define BIT_SHIFT_R_MAC_DBG_SEL_8822C 0 +#define BIT_MASK_R_MAC_DBG_SEL_8822C 0x3 +#define BIT_R_MAC_DBG_SEL_8822C(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SEL_8822C) << BIT_SHIFT_R_MAC_DBG_SEL_8822C) +#define BITS_R_MAC_DBG_SEL_8822C \ + (BIT_MASK_R_MAC_DBG_SEL_8822C << BIT_SHIFT_R_MAC_DBG_SEL_8822C) +#define BIT_CLEAR_R_MAC_DBG_SEL_8822C(x) ((x) & (~BITS_R_MAC_DBG_SEL_8822C)) +#define BIT_GET_R_MAC_DBG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822C) & BIT_MASK_R_MAC_DBG_SEL_8822C) +#define BIT_SET_R_MAC_DBG_SEL_8822C(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SEL_8822C(x) | BIT_R_MAC_DBG_SEL_8822C(v)) + +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8822C */ + +#define BIT_SHIFT_R_MAC_DEBUG_1_8822C 0 +#define BIT_MASK_R_MAC_DEBUG_1_8822C 0xffffffffL +#define BIT_R_MAC_DEBUG_1_8822C(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG_1_8822C) << BIT_SHIFT_R_MAC_DEBUG_1_8822C) +#define BITS_R_MAC_DEBUG_1_8822C \ + (BIT_MASK_R_MAC_DEBUG_1_8822C << BIT_SHIFT_R_MAC_DEBUG_1_8822C) +#define BIT_CLEAR_R_MAC_DEBUG_1_8822C(x) ((x) & (~BITS_R_MAC_DEBUG_1_8822C)) +#define BIT_GET_R_MAC_DEBUG_1_8822C(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8822C) & BIT_MASK_R_MAC_DEBUG_1_8822C) +#define BIT_SET_R_MAC_DEBUG_1_8822C(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG_1_8822C(x) | BIT_R_MAC_DEBUG_1_8822C(v)) + +/* 2 REG_WSEC_OPTION_8822C */ +#define BIT_RXDEC_BM_MGNT_8822C BIT(22) +#define BIT_TXENC_BM_MGNT_8822C BIT(21) +#define BIT_RXDEC_UNI_MGNT_8822C BIT(20) +#define BIT_TXENC_UNI_MGNT_8822C BIT(19) +#define BIT_WMAC_SEC_MASKIV_8822C BIT(18) + +#define BIT_SHIFT_WMAC_SEC_PN_SEL_8822C 16 +#define BIT_MASK_WMAC_SEC_PN_SEL_8822C 0x3 +#define BIT_WMAC_SEC_PN_SEL_8822C(x) \ + (((x) & BIT_MASK_WMAC_SEC_PN_SEL_8822C) \ + << BIT_SHIFT_WMAC_SEC_PN_SEL_8822C) +#define BITS_WMAC_SEC_PN_SEL_8822C \ + (BIT_MASK_WMAC_SEC_PN_SEL_8822C << BIT_SHIFT_WMAC_SEC_PN_SEL_8822C) +#define BIT_CLEAR_WMAC_SEC_PN_SEL_8822C(x) ((x) & (~BITS_WMAC_SEC_PN_SEL_8822C)) +#define BIT_GET_WMAC_SEC_PN_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_SEC_PN_SEL_8822C) & \ + BIT_MASK_WMAC_SEC_PN_SEL_8822C) +#define BIT_SET_WMAC_SEC_PN_SEL_8822C(x, v) \ + (BIT_CLEAR_WMAC_SEC_PN_SEL_8822C(x) | BIT_WMAC_SEC_PN_SEL_8822C(v)) + +#define BIT_SHIFT_BT_TIME_CNT_8822C 0 +#define BIT_MASK_BT_TIME_CNT_8822C 0xff +#define BIT_BT_TIME_CNT_8822C(x) \ + (((x) & BIT_MASK_BT_TIME_CNT_8822C) << BIT_SHIFT_BT_TIME_CNT_8822C) +#define BITS_BT_TIME_CNT_8822C \ + (BIT_MASK_BT_TIME_CNT_8822C << BIT_SHIFT_BT_TIME_CNT_8822C) +#define BIT_CLEAR_BT_TIME_CNT_8822C(x) ((x) & (~BITS_BT_TIME_CNT_8822C)) +#define BIT_GET_BT_TIME_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_BT_TIME_CNT_8822C) & BIT_MASK_BT_TIME_CNT_8822C) +#define BIT_SET_BT_TIME_CNT_8822C(x, v) \ + (BIT_CLEAR_BT_TIME_CNT_8822C(x) | BIT_BT_TIME_CNT_8822C(v)) + +/* 2 REG_RTS_ADDRESS_0_8822C */ + +/* 2 REG_RTS_ADDRESS_0_1_8822C */ + +/* 2 REG_RTS_ADDRESS_1_8822C */ + +/* 2 REG_RTS_ADDRESS_1_1_8822C */ + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822C */ +#define BIT_LTECOEX_ACCESS_START_V1_8822C BIT(31) +#define BIT_LTECOEX_WRITE_MODE_V1_8822C BIT(30) +#define BIT_LTECOEX_READY_BIT_V1_8822C BIT(29) + +#define BIT_SHIFT_WRITE_BYTE_EN_V1_8822C 16 +#define BIT_MASK_WRITE_BYTE_EN_V1_8822C 0xf +#define BIT_WRITE_BYTE_EN_V1_8822C(x) \ + (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822C) \ + << BIT_SHIFT_WRITE_BYTE_EN_V1_8822C) +#define BITS_WRITE_BYTE_EN_V1_8822C \ + (BIT_MASK_WRITE_BYTE_EN_V1_8822C << BIT_SHIFT_WRITE_BYTE_EN_V1_8822C) +#define BIT_CLEAR_WRITE_BYTE_EN_V1_8822C(x) \ + ((x) & (~BITS_WRITE_BYTE_EN_V1_8822C)) +#define BIT_GET_WRITE_BYTE_EN_V1_8822C(x) \ + (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822C) & \ + BIT_MASK_WRITE_BYTE_EN_V1_8822C) +#define BIT_SET_WRITE_BYTE_EN_V1_8822C(x, v) \ + (BIT_CLEAR_WRITE_BYTE_EN_V1_8822C(x) | BIT_WRITE_BYTE_EN_V1_8822C(v)) + +#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C 0 +#define BIT_MASK_LTECOEX_REG_ADDR_V1_8822C 0xffff +#define BIT_LTECOEX_REG_ADDR_V1_8822C(x) \ + (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822C) \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C) +#define BITS_LTECOEX_REG_ADDR_V1_8822C \ + (BIT_MASK_LTECOEX_REG_ADDR_V1_8822C \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C) +#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822C(x) \ + ((x) & (~BITS_LTECOEX_REG_ADDR_V1_8822C)) +#define BIT_GET_LTECOEX_REG_ADDR_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C) & \ + BIT_MASK_LTECOEX_REG_ADDR_V1_8822C) +#define BIT_SET_LTECOEX_REG_ADDR_V1_8822C(x, v) \ + (BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822C(x) | \ + BIT_LTECOEX_REG_ADDR_V1_8822C(v)) + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822C */ + +#define BIT_SHIFT_LTECOEX_W_DATA_V1_8822C 0 +#define BIT_MASK_LTECOEX_W_DATA_V1_8822C 0xffffffffL +#define BIT_LTECOEX_W_DATA_V1_8822C(x) \ + (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822C) \ + << BIT_SHIFT_LTECOEX_W_DATA_V1_8822C) +#define BITS_LTECOEX_W_DATA_V1_8822C \ + (BIT_MASK_LTECOEX_W_DATA_V1_8822C << BIT_SHIFT_LTECOEX_W_DATA_V1_8822C) +#define BIT_CLEAR_LTECOEX_W_DATA_V1_8822C(x) \ + ((x) & (~BITS_LTECOEX_W_DATA_V1_8822C)) +#define BIT_GET_LTECOEX_W_DATA_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822C) & \ + BIT_MASK_LTECOEX_W_DATA_V1_8822C) +#define BIT_SET_LTECOEX_W_DATA_V1_8822C(x, v) \ + (BIT_CLEAR_LTECOEX_W_DATA_V1_8822C(x) | BIT_LTECOEX_W_DATA_V1_8822C(v)) + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C */ + +#define BIT_SHIFT_LTECOEX_R_DATA_V1_8822C 0 +#define BIT_MASK_LTECOEX_R_DATA_V1_8822C 0xffffffffL +#define BIT_LTECOEX_R_DATA_V1_8822C(x) \ + (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822C) \ + << BIT_SHIFT_LTECOEX_R_DATA_V1_8822C) +#define BITS_LTECOEX_R_DATA_V1_8822C \ + (BIT_MASK_LTECOEX_R_DATA_V1_8822C << BIT_SHIFT_LTECOEX_R_DATA_V1_8822C) +#define BIT_CLEAR_LTECOEX_R_DATA_V1_8822C(x) \ + ((x) & (~BITS_LTECOEX_R_DATA_V1_8822C)) +#define BIT_GET_LTECOEX_R_DATA_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822C) & \ + BIT_MASK_LTECOEX_R_DATA_V1_8822C) +#define BIT_SET_LTECOEX_R_DATA_V1_8822C(x, v) \ + (BIT_CLEAR_LTECOEX_R_DATA_V1_8822C(x) | BIT_LTECOEX_R_DATA_V1_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SDIO_TX_CTRL_8822C */ + +#define BIT_SHIFT_SDIO_INT_TIMEOUT_8822C 16 +#define BIT_MASK_SDIO_INT_TIMEOUT_8822C 0xffff +#define BIT_SDIO_INT_TIMEOUT_8822C(x) \ + (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822C) \ + << BIT_SHIFT_SDIO_INT_TIMEOUT_8822C) +#define BITS_SDIO_INT_TIMEOUT_8822C \ + (BIT_MASK_SDIO_INT_TIMEOUT_8822C << BIT_SHIFT_SDIO_INT_TIMEOUT_8822C) +#define BIT_CLEAR_SDIO_INT_TIMEOUT_8822C(x) \ + ((x) & (~BITS_SDIO_INT_TIMEOUT_8822C)) +#define BIT_GET_SDIO_INT_TIMEOUT_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822C) & \ + BIT_MASK_SDIO_INT_TIMEOUT_8822C) +#define BIT_SET_SDIO_INT_TIMEOUT_8822C(x, v) \ + (BIT_CLEAR_SDIO_INT_TIMEOUT_8822C(x) | BIT_SDIO_INT_TIMEOUT_8822C(v)) + +#define BIT_IO_ERR_STATUS_8822C BIT(15) +#define BIT_CMD53_W_MIX_8822C BIT(14) +#define BIT_CMD53_TX_FORMAT_8822C BIT(13) +#define BIT_CMD53_R_TIMEOUT_MASK_8822C BIT(12) + +#define BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C 10 +#define BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C 0x3 +#define BIT_CMD53_R_TIMEOUT_UNIT_8822C(x) \ + (((x) & BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C) \ + << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C) +#define BITS_CMD53_R_TIMEOUT_UNIT_8822C \ + (BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C \ + << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C) +#define BIT_CLEAR_CMD53_R_TIMEOUT_UNIT_8822C(x) \ + ((x) & (~BITS_CMD53_R_TIMEOUT_UNIT_8822C)) +#define BIT_GET_CMD53_R_TIMEOUT_UNIT_8822C(x) \ + (((x) >> BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C) & \ + BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C) +#define BIT_SET_CMD53_R_TIMEOUT_UNIT_8822C(x, v) \ + (BIT_CLEAR_CMD53_R_TIMEOUT_UNIT_8822C(x) | \ + BIT_CMD53_R_TIMEOUT_UNIT_8822C(v)) + +#define BIT_REPLY_ERRCRC_IN_DATA_8822C BIT(9) +#define BIT_EN_CMD53_OVERLAP_8822C BIT(8) +#define BIT_REPLY_ERR_IN_R5_8822C BIT(7) +#define BIT_R18A_EN_8822C BIT(6) +#define BIT_SDIO_CMD_FORCE_VLD_8822C BIT(5) +#define BIT_INIT_CMD_EN_8822C BIT(4) +#define BIT_RXINT_READ_MASK_DIS_8822C BIT(3) +#define BIT_EN_RXDMA_MASK_INT_8822C BIT(2) +#define BIT_EN_MASK_TIMER_8822C BIT(1) +#define BIT_CMD_ERR_STOP_INT_EN_8822C BIT(0) + +/* 2 REG_SDIO_CMD11_VOL_SWITCH_8822C */ + +#define BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C 4 +#define BIT_MASK_CMD11_SEQ_END_DELAY_8822C 0xf +#define BIT_CMD11_SEQ_END_DELAY_8822C(x) \ + (((x) & BIT_MASK_CMD11_SEQ_END_DELAY_8822C) \ + << BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C) +#define BITS_CMD11_SEQ_END_DELAY_8822C \ + (BIT_MASK_CMD11_SEQ_END_DELAY_8822C \ + << BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C) +#define BIT_CLEAR_CMD11_SEQ_END_DELAY_8822C(x) \ + ((x) & (~BITS_CMD11_SEQ_END_DELAY_8822C)) +#define BIT_GET_CMD11_SEQ_END_DELAY_8822C(x) \ + (((x) >> BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C) & \ + BIT_MASK_CMD11_SEQ_END_DELAY_8822C) +#define BIT_SET_CMD11_SEQ_END_DELAY_8822C(x, v) \ + (BIT_CLEAR_CMD11_SEQ_END_DELAY_8822C(x) | \ + BIT_CMD11_SEQ_END_DELAY_8822C(v)) + +#define BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C 1 +#define BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C 0x7 +#define BIT_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) \ + (((x) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C) \ + << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C) +#define BITS_CMD11_SEQ_SAMPLE_INTERVAL_8822C \ + (BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C \ + << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C) +#define BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) \ + ((x) & (~BITS_CMD11_SEQ_SAMPLE_INTERVAL_8822C)) +#define BIT_GET_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) \ + (((x) >> BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C) & \ + BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C) +#define BIT_SET_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x, v) \ + (BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) | \ + BIT_CMD11_SEQ_SAMPLE_INTERVAL_8822C(v)) + +#define BIT_CMD11_SEQ_EN_8822C BIT(0) + +/* 2 REG_SDIO_DRIVING_8822C */ + +#define BIT_SHIFT_SDIO_DRV_TYPE_D_8822C 12 +#define BIT_MASK_SDIO_DRV_TYPE_D_8822C 0xf +#define BIT_SDIO_DRV_TYPE_D_8822C(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_D_8822C) \ + << BIT_SHIFT_SDIO_DRV_TYPE_D_8822C) +#define BITS_SDIO_DRV_TYPE_D_8822C \ + (BIT_MASK_SDIO_DRV_TYPE_D_8822C << BIT_SHIFT_SDIO_DRV_TYPE_D_8822C) +#define BIT_CLEAR_SDIO_DRV_TYPE_D_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_D_8822C)) +#define BIT_GET_SDIO_DRV_TYPE_D_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_D_8822C) & \ + BIT_MASK_SDIO_DRV_TYPE_D_8822C) +#define BIT_SET_SDIO_DRV_TYPE_D_8822C(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_D_8822C(x) | BIT_SDIO_DRV_TYPE_D_8822C(v)) + +#define BIT_SHIFT_SDIO_DRV_TYPE_C_8822C 8 +#define BIT_MASK_SDIO_DRV_TYPE_C_8822C 0xf +#define BIT_SDIO_DRV_TYPE_C_8822C(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_C_8822C) \ + << BIT_SHIFT_SDIO_DRV_TYPE_C_8822C) +#define BITS_SDIO_DRV_TYPE_C_8822C \ + (BIT_MASK_SDIO_DRV_TYPE_C_8822C << BIT_SHIFT_SDIO_DRV_TYPE_C_8822C) +#define BIT_CLEAR_SDIO_DRV_TYPE_C_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_C_8822C)) +#define BIT_GET_SDIO_DRV_TYPE_C_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_C_8822C) & \ + BIT_MASK_SDIO_DRV_TYPE_C_8822C) +#define BIT_SET_SDIO_DRV_TYPE_C_8822C(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_C_8822C(x) | BIT_SDIO_DRV_TYPE_C_8822C(v)) + +#define BIT_SHIFT_SDIO_DRV_TYPE_B_8822C 4 +#define BIT_MASK_SDIO_DRV_TYPE_B_8822C 0xf +#define BIT_SDIO_DRV_TYPE_B_8822C(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_B_8822C) \ + << BIT_SHIFT_SDIO_DRV_TYPE_B_8822C) +#define BITS_SDIO_DRV_TYPE_B_8822C \ + (BIT_MASK_SDIO_DRV_TYPE_B_8822C << BIT_SHIFT_SDIO_DRV_TYPE_B_8822C) +#define BIT_CLEAR_SDIO_DRV_TYPE_B_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_B_8822C)) +#define BIT_GET_SDIO_DRV_TYPE_B_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_B_8822C) & \ + BIT_MASK_SDIO_DRV_TYPE_B_8822C) +#define BIT_SET_SDIO_DRV_TYPE_B_8822C(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_B_8822C(x) | BIT_SDIO_DRV_TYPE_B_8822C(v)) + +#define BIT_SHIFT_SDIO_DRV_TYPE_A_8822C 0 +#define BIT_MASK_SDIO_DRV_TYPE_A_8822C 0xf +#define BIT_SDIO_DRV_TYPE_A_8822C(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_A_8822C) \ + << BIT_SHIFT_SDIO_DRV_TYPE_A_8822C) +#define BITS_SDIO_DRV_TYPE_A_8822C \ + (BIT_MASK_SDIO_DRV_TYPE_A_8822C << BIT_SHIFT_SDIO_DRV_TYPE_A_8822C) +#define BIT_CLEAR_SDIO_DRV_TYPE_A_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_A_8822C)) +#define BIT_GET_SDIO_DRV_TYPE_A_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_A_8822C) & \ + BIT_MASK_SDIO_DRV_TYPE_A_8822C) +#define BIT_SET_SDIO_DRV_TYPE_A_8822C(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_A_8822C(x) | BIT_SDIO_DRV_TYPE_A_8822C(v)) + +/* 2 REG_SDIO_MONITOR_8822C */ + +#define BIT_SHIFT_SDIO_INT_START_8822C 0 +#define BIT_MASK_SDIO_INT_START_8822C 0xffffffffL +#define BIT_SDIO_INT_START_8822C(x) \ + (((x) & BIT_MASK_SDIO_INT_START_8822C) \ + << BIT_SHIFT_SDIO_INT_START_8822C) +#define BITS_SDIO_INT_START_8822C \ + (BIT_MASK_SDIO_INT_START_8822C << BIT_SHIFT_SDIO_INT_START_8822C) +#define BIT_CLEAR_SDIO_INT_START_8822C(x) ((x) & (~BITS_SDIO_INT_START_8822C)) +#define BIT_GET_SDIO_INT_START_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_START_8822C) & \ + BIT_MASK_SDIO_INT_START_8822C) +#define BIT_SET_SDIO_INT_START_8822C(x, v) \ + (BIT_CLEAR_SDIO_INT_START_8822C(x) | BIT_SDIO_INT_START_8822C(v)) + +/* 2 REG_SDIO_MONITOR_2_8822C */ +#define BIT_CMD53_WT_EN_8822C BIT(23) + +#define BIT_SHIFT_SDIO_CLK_MONITOR_8822C 21 +#define BIT_MASK_SDIO_CLK_MONITOR_8822C 0x3 +#define BIT_SDIO_CLK_MONITOR_8822C(x) \ + (((x) & BIT_MASK_SDIO_CLK_MONITOR_8822C) \ + << BIT_SHIFT_SDIO_CLK_MONITOR_8822C) +#define BITS_SDIO_CLK_MONITOR_8822C \ + (BIT_MASK_SDIO_CLK_MONITOR_8822C << BIT_SHIFT_SDIO_CLK_MONITOR_8822C) +#define BIT_CLEAR_SDIO_CLK_MONITOR_8822C(x) \ + ((x) & (~BITS_SDIO_CLK_MONITOR_8822C)) +#define BIT_GET_SDIO_CLK_MONITOR_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_CLK_MONITOR_8822C) & \ + BIT_MASK_SDIO_CLK_MONITOR_8822C) +#define BIT_SET_SDIO_CLK_MONITOR_8822C(x, v) \ + (BIT_CLEAR_SDIO_CLK_MONITOR_8822C(x) | BIT_SDIO_CLK_MONITOR_8822C(v)) + +#define BIT_SHIFT_SDIO_CLK_CNT_8822C 0 +#define BIT_MASK_SDIO_CLK_CNT_8822C 0x1fffff +#define BIT_SDIO_CLK_CNT_8822C(x) \ + (((x) & BIT_MASK_SDIO_CLK_CNT_8822C) << BIT_SHIFT_SDIO_CLK_CNT_8822C) +#define BITS_SDIO_CLK_CNT_8822C \ + (BIT_MASK_SDIO_CLK_CNT_8822C << BIT_SHIFT_SDIO_CLK_CNT_8822C) +#define BIT_CLEAR_SDIO_CLK_CNT_8822C(x) ((x) & (~BITS_SDIO_CLK_CNT_8822C)) +#define BIT_GET_SDIO_CLK_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_CLK_CNT_8822C) & BIT_MASK_SDIO_CLK_CNT_8822C) +#define BIT_SET_SDIO_CLK_CNT_8822C(x, v) \ + (BIT_CLEAR_SDIO_CLK_CNT_8822C(x) | BIT_SDIO_CLK_CNT_8822C(v)) + +/* 2 REG_SDIO_HIMR_8822C */ +#define BIT_SDIO_CRCERR_MSK_8822C BIT(31) +#define BIT_SDIO_HSISR3_IND_MSK_8822C BIT(30) +#define BIT_SDIO_HSISR2_IND_MSK_8822C BIT(29) +#define BIT_SDIO_HEISR_IND_MSK_8822C BIT(28) +#define BIT_SDIO_CTWEND_MSK_8822C BIT(27) +#define BIT_SDIO_ATIMEND_E_MSK_8822C BIT(26) +#define BIT_SDIIO_ATIMEND_MSK_8822C BIT(25) +#define BIT_SDIO_OCPINT_MSK_8822C BIT(24) +#define BIT_SDIO_PSTIMEOUT_MSK_8822C BIT(23) +#define BIT_SDIO_GTINT4_MSK_8822C BIT(22) +#define BIT_SDIO_GTINT3_MSK_8822C BIT(21) +#define BIT_SDIO_HSISR_IND_MSK_8822C BIT(20) +#define BIT_SDIO_CPWM2_MSK_8822C BIT(19) +#define BIT_SDIO_CPWM1_MSK_8822C BIT(18) +#define BIT_SDIO_C2HCMD_INT_MSK_8822C BIT(17) +#define BIT_SDIO_BCNERLY_INT_MSK_8822C BIT(16) +#define BIT_SDIO_TXBCNERR_MSK_8822C BIT(7) +#define BIT_SDIO_TXBCNOK_MSK_8822C BIT(6) +#define BIT_SDIO_RXFOVW_MSK_8822C BIT(5) +#define BIT_SDIO_TXFOVW_MSK_8822C BIT(4) +#define BIT_SDIO_RXERR_MSK_8822C BIT(3) +#define BIT_SDIO_TXERR_MSK_8822C BIT(2) +#define BIT_SDIO_AVAL_MSK_8822C BIT(1) +#define BIT_RX_REQUEST_MSK_8822C BIT(0) + +/* 2 REG_SDIO_HISR_8822C */ +#define BIT_SDIO_CRCERR_8822C BIT(31) +#define BIT_SDIO_HSISR3_IND_8822C BIT(30) +#define BIT_SDIO_HSISR2_IND_8822C BIT(29) +#define BIT_SDIO_HEISR_IND_8822C BIT(28) +#define BIT_SDIO_CTWEND_8822C BIT(27) +#define BIT_SDIO_ATIMEND_E_8822C BIT(26) +#define BIT_SDIO_ATIMEND_8822C BIT(25) +#define BIT_SDIO_OCPINT_8822C BIT(24) +#define BIT_SDIO_PSTIMEOUT_8822C BIT(23) +#define BIT_SDIO_GTINT4_8822C BIT(22) +#define BIT_SDIO_GTINT3_8822C BIT(21) +#define BIT_SDIO_HSISR_IND_8822C BIT(20) +#define BIT_SDIO_CPWM2_8822C BIT(19) +#define BIT_SDIO_CPWM1_8822C BIT(18) +#define BIT_SDIO_C2HCMD_INT_8822C BIT(17) +#define BIT_SDIO_BCNERLY_INT_8822C BIT(16) +#define BIT_SDIO_TXBCNERR_8822C BIT(7) +#define BIT_SDIO_TXBCNOK_8822C BIT(6) +#define BIT_SDIO_RXFOVW_8822C BIT(5) +#define BIT_SDIO_TXFOVW_8822C BIT(4) +#define BIT_SDIO_RXERR_8822C BIT(3) +#define BIT_SDIO_TXERR_8822C BIT(2) +#define BIT_SDIO_AVAL_8822C BIT(1) +#define BIT_RX_REQUEST_8822C BIT(0) + +/* 2 REG_SDIO_RX_REQ_LEN_8822C */ + +#define BIT_SHIFT_RX_REQ_LEN_V1_8822C 0 +#define BIT_MASK_RX_REQ_LEN_V1_8822C 0x3ffff +#define BIT_RX_REQ_LEN_V1_8822C(x) \ + (((x) & BIT_MASK_RX_REQ_LEN_V1_8822C) << BIT_SHIFT_RX_REQ_LEN_V1_8822C) +#define BITS_RX_REQ_LEN_V1_8822C \ + (BIT_MASK_RX_REQ_LEN_V1_8822C << BIT_SHIFT_RX_REQ_LEN_V1_8822C) +#define BIT_CLEAR_RX_REQ_LEN_V1_8822C(x) ((x) & (~BITS_RX_REQ_LEN_V1_8822C)) +#define BIT_GET_RX_REQ_LEN_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822C) & BIT_MASK_RX_REQ_LEN_V1_8822C) +#define BIT_SET_RX_REQ_LEN_V1_8822C(x, v) \ + (BIT_CLEAR_RX_REQ_LEN_V1_8822C(x) | BIT_RX_REQ_LEN_V1_8822C(v)) + +/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8822C */ + +#define BIT_SHIFT_FREE_TXPG_SEQ_8822C 0 +#define BIT_MASK_FREE_TXPG_SEQ_8822C 0xff +#define BIT_FREE_TXPG_SEQ_8822C(x) \ + (((x) & BIT_MASK_FREE_TXPG_SEQ_8822C) << BIT_SHIFT_FREE_TXPG_SEQ_8822C) +#define BITS_FREE_TXPG_SEQ_8822C \ + (BIT_MASK_FREE_TXPG_SEQ_8822C << BIT_SHIFT_FREE_TXPG_SEQ_8822C) +#define BIT_CLEAR_FREE_TXPG_SEQ_8822C(x) ((x) & (~BITS_FREE_TXPG_SEQ_8822C)) +#define BIT_GET_FREE_TXPG_SEQ_8822C(x) \ + (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822C) & BIT_MASK_FREE_TXPG_SEQ_8822C) +#define BIT_SET_FREE_TXPG_SEQ_8822C(x, v) \ + (BIT_CLEAR_FREE_TXPG_SEQ_8822C(x) | BIT_FREE_TXPG_SEQ_8822C(v)) + +/* 2 REG_SDIO_FREE_TXPG_8822C */ + +#define BIT_SHIFT_MID_FREEPG_V1_8822C 16 +#define BIT_MASK_MID_FREEPG_V1_8822C 0xfff +#define BIT_MID_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_MID_FREEPG_V1_8822C) << BIT_SHIFT_MID_FREEPG_V1_8822C) +#define BITS_MID_FREEPG_V1_8822C \ + (BIT_MASK_MID_FREEPG_V1_8822C << BIT_SHIFT_MID_FREEPG_V1_8822C) +#define BIT_CLEAR_MID_FREEPG_V1_8822C(x) ((x) & (~BITS_MID_FREEPG_V1_8822C)) +#define BIT_GET_MID_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MID_FREEPG_V1_8822C) & BIT_MASK_MID_FREEPG_V1_8822C) +#define BIT_SET_MID_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_MID_FREEPG_V1_8822C(x) | BIT_MID_FREEPG_V1_8822C(v)) + +#define BIT_SHIFT_HIQ_FREEPG_V1_8822C 0 +#define BIT_MASK_HIQ_FREEPG_V1_8822C 0xfff +#define BIT_HIQ_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_HIQ_FREEPG_V1_8822C) << BIT_SHIFT_HIQ_FREEPG_V1_8822C) +#define BITS_HIQ_FREEPG_V1_8822C \ + (BIT_MASK_HIQ_FREEPG_V1_8822C << BIT_SHIFT_HIQ_FREEPG_V1_8822C) +#define BIT_CLEAR_HIQ_FREEPG_V1_8822C(x) ((x) & (~BITS_HIQ_FREEPG_V1_8822C)) +#define BIT_GET_HIQ_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822C) & BIT_MASK_HIQ_FREEPG_V1_8822C) +#define BIT_SET_HIQ_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_HIQ_FREEPG_V1_8822C(x) | BIT_HIQ_FREEPG_V1_8822C(v)) + +/* 2 REG_SDIO_FREE_TXPG2_8822C */ + +#define BIT_SHIFT_PUB_FREEPG_V1_8822C 16 +#define BIT_MASK_PUB_FREEPG_V1_8822C 0xfff +#define BIT_PUB_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_PUB_FREEPG_V1_8822C) << BIT_SHIFT_PUB_FREEPG_V1_8822C) +#define BITS_PUB_FREEPG_V1_8822C \ + (BIT_MASK_PUB_FREEPG_V1_8822C << BIT_SHIFT_PUB_FREEPG_V1_8822C) +#define BIT_CLEAR_PUB_FREEPG_V1_8822C(x) ((x) & (~BITS_PUB_FREEPG_V1_8822C)) +#define BIT_GET_PUB_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822C) & BIT_MASK_PUB_FREEPG_V1_8822C) +#define BIT_SET_PUB_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_PUB_FREEPG_V1_8822C(x) | BIT_PUB_FREEPG_V1_8822C(v)) + +#define BIT_SHIFT_LOW_FREEPG_V1_8822C 0 +#define BIT_MASK_LOW_FREEPG_V1_8822C 0xfff +#define BIT_LOW_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_LOW_FREEPG_V1_8822C) << BIT_SHIFT_LOW_FREEPG_V1_8822C) +#define BITS_LOW_FREEPG_V1_8822C \ + (BIT_MASK_LOW_FREEPG_V1_8822C << BIT_SHIFT_LOW_FREEPG_V1_8822C) +#define BIT_CLEAR_LOW_FREEPG_V1_8822C(x) ((x) & (~BITS_LOW_FREEPG_V1_8822C)) +#define BIT_GET_LOW_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822C) & BIT_MASK_LOW_FREEPG_V1_8822C) +#define BIT_SET_LOW_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_LOW_FREEPG_V1_8822C(x) | BIT_LOW_FREEPG_V1_8822C(v)) + +/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8822C */ + +#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C 24 +#define BIT_MASK_NOAC_OQT_FREEPG_V1_8822C 0xff +#define BIT_NOAC_OQT_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822C) \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C) +#define BITS_NOAC_OQT_FREEPG_V1_8822C \ + (BIT_MASK_NOAC_OQT_FREEPG_V1_8822C \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C) +#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822C(x) \ + ((x) & (~BITS_NOAC_OQT_FREEPG_V1_8822C)) +#define BIT_GET_NOAC_OQT_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C) & \ + BIT_MASK_NOAC_OQT_FREEPG_V1_8822C) +#define BIT_SET_NOAC_OQT_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822C(x) | \ + BIT_NOAC_OQT_FREEPG_V1_8822C(v)) + +#define BIT_SHIFT_AC_OQT_FREEPG_V1_8822C 16 +#define BIT_MASK_AC_OQT_FREEPG_V1_8822C 0xff +#define BIT_AC_OQT_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822C) \ + << BIT_SHIFT_AC_OQT_FREEPG_V1_8822C) +#define BITS_AC_OQT_FREEPG_V1_8822C \ + (BIT_MASK_AC_OQT_FREEPG_V1_8822C << BIT_SHIFT_AC_OQT_FREEPG_V1_8822C) +#define BIT_CLEAR_AC_OQT_FREEPG_V1_8822C(x) \ + ((x) & (~BITS_AC_OQT_FREEPG_V1_8822C)) +#define BIT_GET_AC_OQT_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822C) & \ + BIT_MASK_AC_OQT_FREEPG_V1_8822C) +#define BIT_SET_AC_OQT_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_AC_OQT_FREEPG_V1_8822C(x) | BIT_AC_OQT_FREEPG_V1_8822C(v)) + +#define BIT_SHIFT_EXQ_FREEPG_V1_8822C 0 +#define BIT_MASK_EXQ_FREEPG_V1_8822C 0xfff +#define BIT_EXQ_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_EXQ_FREEPG_V1_8822C) << BIT_SHIFT_EXQ_FREEPG_V1_8822C) +#define BITS_EXQ_FREEPG_V1_8822C \ + (BIT_MASK_EXQ_FREEPG_V1_8822C << BIT_SHIFT_EXQ_FREEPG_V1_8822C) +#define BIT_CLEAR_EXQ_FREEPG_V1_8822C(x) ((x) & (~BITS_EXQ_FREEPG_V1_8822C)) +#define BIT_GET_EXQ_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822C) & BIT_MASK_EXQ_FREEPG_V1_8822C) +#define BIT_SET_EXQ_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_EXQ_FREEPG_V1_8822C(x) | BIT_EXQ_FREEPG_V1_8822C(v)) + +/* 2 REG_SDIO_TXPKT_EMPTY_8822C */ +#define BIT_SDIO_BCNQ_EMPTY_8822C BIT(11) +#define BIT_SDIO_HQQ_EMPTY_8822C BIT(10) +#define BIT_SDIO_MQQ_EMPTY_8822C BIT(9) +#define BIT_SDIO_MGQ_CPU_EMPTY_8822C BIT(8) +#define BIT_SDIO_AC7Q_EMPTY_8822C BIT(7) +#define BIT_SDIO_AC6Q_EMPTY_8822C BIT(6) +#define BIT_SDIO_AC5Q_EMPTY_8822C BIT(5) +#define BIT_SDIO_AC4Q_EMPTY_8822C BIT(4) +#define BIT_SDIO_AC3Q_EMPTY_8822C BIT(3) +#define BIT_SDIO_AC2Q_EMPTY_8822C BIT(2) +#define BIT_SDIO_AC1Q_EMPTY_8822C BIT(1) +#define BIT_SDIO_AC0Q_EMPTY_8822C BIT(0) + +/* 2 REG_SDIO_HTSFR_INFO_8822C */ + +#define BIT_SHIFT_HTSFR1_8822C 16 +#define BIT_MASK_HTSFR1_8822C 0xffff +#define BIT_HTSFR1_8822C(x) \ + (((x) & BIT_MASK_HTSFR1_8822C) << BIT_SHIFT_HTSFR1_8822C) +#define BITS_HTSFR1_8822C (BIT_MASK_HTSFR1_8822C << BIT_SHIFT_HTSFR1_8822C) +#define BIT_CLEAR_HTSFR1_8822C(x) ((x) & (~BITS_HTSFR1_8822C)) +#define BIT_GET_HTSFR1_8822C(x) \ + (((x) >> BIT_SHIFT_HTSFR1_8822C) & BIT_MASK_HTSFR1_8822C) +#define BIT_SET_HTSFR1_8822C(x, v) \ + (BIT_CLEAR_HTSFR1_8822C(x) | BIT_HTSFR1_8822C(v)) + +#define BIT_SHIFT_HTSFR0_8822C 0 +#define BIT_MASK_HTSFR0_8822C 0xffff +#define BIT_HTSFR0_8822C(x) \ + (((x) & BIT_MASK_HTSFR0_8822C) << BIT_SHIFT_HTSFR0_8822C) +#define BITS_HTSFR0_8822C (BIT_MASK_HTSFR0_8822C << BIT_SHIFT_HTSFR0_8822C) +#define BIT_CLEAR_HTSFR0_8822C(x) ((x) & (~BITS_HTSFR0_8822C)) +#define BIT_GET_HTSFR0_8822C(x) \ + (((x) >> BIT_SHIFT_HTSFR0_8822C) & BIT_MASK_HTSFR0_8822C) +#define BIT_SET_HTSFR0_8822C(x, v) \ + (BIT_CLEAR_HTSFR0_8822C(x) | BIT_HTSFR0_8822C(v)) + +/* 2 REG_SDIO_HCPWM1_V2_8822C */ +#define BIT_TOGGLE_8822C BIT(7) +#define BIT_CUR_PS_8822C BIT(0) + +/* 2 REG_SDIO_HCPWM2_V2_8822C */ + +/* 2 REG_SDIO_INDIRECT_REG_CFG_8822C */ +#define BIT_INDIRECT_REG_RDY_8822C BIT(20) +#define BIT_INDIRECT_REG_R_8822C BIT(19) +#define BIT_INDIRECT_REG_W_8822C BIT(18) + +#define BIT_SHIFT_INDIRECT_REG_SIZE_8822C 16 +#define BIT_MASK_INDIRECT_REG_SIZE_8822C 0x3 +#define BIT_INDIRECT_REG_SIZE_8822C(x) \ + (((x) & BIT_MASK_INDIRECT_REG_SIZE_8822C) \ + << BIT_SHIFT_INDIRECT_REG_SIZE_8822C) +#define BITS_INDIRECT_REG_SIZE_8822C \ + (BIT_MASK_INDIRECT_REG_SIZE_8822C << BIT_SHIFT_INDIRECT_REG_SIZE_8822C) +#define BIT_CLEAR_INDIRECT_REG_SIZE_8822C(x) \ + ((x) & (~BITS_INDIRECT_REG_SIZE_8822C)) +#define BIT_GET_INDIRECT_REG_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822C) & \ + BIT_MASK_INDIRECT_REG_SIZE_8822C) +#define BIT_SET_INDIRECT_REG_SIZE_8822C(x, v) \ + (BIT_CLEAR_INDIRECT_REG_SIZE_8822C(x) | BIT_INDIRECT_REG_SIZE_8822C(v)) + +#define BIT_SHIFT_INDIRECT_REG_ADDR_8822C 0 +#define BIT_MASK_INDIRECT_REG_ADDR_8822C 0xffff +#define BIT_INDIRECT_REG_ADDR_8822C(x) \ + (((x) & BIT_MASK_INDIRECT_REG_ADDR_8822C) \ + << BIT_SHIFT_INDIRECT_REG_ADDR_8822C) +#define BITS_INDIRECT_REG_ADDR_8822C \ + (BIT_MASK_INDIRECT_REG_ADDR_8822C << BIT_SHIFT_INDIRECT_REG_ADDR_8822C) +#define BIT_CLEAR_INDIRECT_REG_ADDR_8822C(x) \ + ((x) & (~BITS_INDIRECT_REG_ADDR_8822C)) +#define BIT_GET_INDIRECT_REG_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822C) & \ + BIT_MASK_INDIRECT_REG_ADDR_8822C) +#define BIT_SET_INDIRECT_REG_ADDR_8822C(x, v) \ + (BIT_CLEAR_INDIRECT_REG_ADDR_8822C(x) | BIT_INDIRECT_REG_ADDR_8822C(v)) + +/* 2 REG_SDIO_INDIRECT_REG_DATA_8822C */ + +#define BIT_SHIFT_INDIRECT_REG_DATA_8822C 0 +#define BIT_MASK_INDIRECT_REG_DATA_8822C 0xffffffffL +#define BIT_INDIRECT_REG_DATA_8822C(x) \ + (((x) & BIT_MASK_INDIRECT_REG_DATA_8822C) \ + << BIT_SHIFT_INDIRECT_REG_DATA_8822C) +#define BITS_INDIRECT_REG_DATA_8822C \ + (BIT_MASK_INDIRECT_REG_DATA_8822C << BIT_SHIFT_INDIRECT_REG_DATA_8822C) +#define BIT_CLEAR_INDIRECT_REG_DATA_8822C(x) \ + ((x) & (~BITS_INDIRECT_REG_DATA_8822C)) +#define BIT_GET_INDIRECT_REG_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822C) & \ + BIT_MASK_INDIRECT_REG_DATA_8822C) +#define BIT_SET_INDIRECT_REG_DATA_8822C(x, v) \ + (BIT_CLEAR_INDIRECT_REG_DATA_8822C(x) | BIT_INDIRECT_REG_DATA_8822C(v)) + +/* 2 REG_SDIO_H2C_8822C */ + +#define BIT_SHIFT_SDIO_H2C_MSG_8822C 0 +#define BIT_MASK_SDIO_H2C_MSG_8822C 0xffffffffL +#define BIT_SDIO_H2C_MSG_8822C(x) \ + (((x) & BIT_MASK_SDIO_H2C_MSG_8822C) << BIT_SHIFT_SDIO_H2C_MSG_8822C) +#define BITS_SDIO_H2C_MSG_8822C \ + (BIT_MASK_SDIO_H2C_MSG_8822C << BIT_SHIFT_SDIO_H2C_MSG_8822C) +#define BIT_CLEAR_SDIO_H2C_MSG_8822C(x) ((x) & (~BITS_SDIO_H2C_MSG_8822C)) +#define BIT_GET_SDIO_H2C_MSG_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822C) & BIT_MASK_SDIO_H2C_MSG_8822C) +#define BIT_SET_SDIO_H2C_MSG_8822C(x, v) \ + (BIT_CLEAR_SDIO_H2C_MSG_8822C(x) | BIT_SDIO_H2C_MSG_8822C(v)) + +/* 2 REG_SDIO_C2H_8822C */ + +#define BIT_SHIFT_SDIO_C2H_MSG_8822C 0 +#define BIT_MASK_SDIO_C2H_MSG_8822C 0xffffffffL +#define BIT_SDIO_C2H_MSG_8822C(x) \ + (((x) & BIT_MASK_SDIO_C2H_MSG_8822C) << BIT_SHIFT_SDIO_C2H_MSG_8822C) +#define BITS_SDIO_C2H_MSG_8822C \ + (BIT_MASK_SDIO_C2H_MSG_8822C << BIT_SHIFT_SDIO_C2H_MSG_8822C) +#define BIT_CLEAR_SDIO_C2H_MSG_8822C(x) ((x) & (~BITS_SDIO_C2H_MSG_8822C)) +#define BIT_GET_SDIO_C2H_MSG_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822C) & BIT_MASK_SDIO_C2H_MSG_8822C) +#define BIT_SET_SDIO_C2H_MSG_8822C(x, v) \ + (BIT_CLEAR_SDIO_C2H_MSG_8822C(x) | BIT_SDIO_C2H_MSG_8822C(v)) + +/* 2 REG_SDIO_HRPWM1_8822C */ +#define BIT_TOGGLE_8822C BIT(7) +#define BIT_ACK_8822C BIT(6) +#define BIT_REQ_PS_8822C BIT(0) + +/* 2 REG_SDIO_HRPWM2_8822C */ + +/* 2 REG_SDIO_HPS_CLKR_8822C */ + +/* 2 REG_SDIO_BUS_CTRL_8822C */ +#define BIT_INT_MASK_DIS_8822C BIT(4) +#define BIT_PAD_CLK_XHGE_EN_8822C BIT(3) +#define BIT_INTER_CLK_EN_8822C BIT(2) +#define BIT_EN_RPT_TXCRC_8822C BIT(1) +#define BIT_DIS_RXDMA_STS_8822C BIT(0) + +/* 2 REG_SDIO_HSUS_CTRL_8822C */ +#define BIT_INTR_CTRL_8822C BIT(4) +#define BIT_SDIO_VOLTAGE_8822C BIT(3) +#define BIT_BYPASS_INIT_8822C BIT(2) +#define BIT_HCI_RESUME_RDY_8822C BIT(1) +#define BIT_HCI_SUS_REQ_8822C BIT(0) + +/* 2 REG_SDIO_RESPONSE_TIMER_8822C */ + +#define BIT_SHIFT_CMDIN_2RESP_TIMER_8822C 0 +#define BIT_MASK_CMDIN_2RESP_TIMER_8822C 0xffff +#define BIT_CMDIN_2RESP_TIMER_8822C(x) \ + (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822C) \ + << BIT_SHIFT_CMDIN_2RESP_TIMER_8822C) +#define BITS_CMDIN_2RESP_TIMER_8822C \ + (BIT_MASK_CMDIN_2RESP_TIMER_8822C << BIT_SHIFT_CMDIN_2RESP_TIMER_8822C) +#define BIT_CLEAR_CMDIN_2RESP_TIMER_8822C(x) \ + ((x) & (~BITS_CMDIN_2RESP_TIMER_8822C)) +#define BIT_GET_CMDIN_2RESP_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822C) & \ + BIT_MASK_CMDIN_2RESP_TIMER_8822C) +#define BIT_SET_CMDIN_2RESP_TIMER_8822C(x, v) \ + (BIT_CLEAR_CMDIN_2RESP_TIMER_8822C(x) | BIT_CMDIN_2RESP_TIMER_8822C(v)) + +/* 2 REG_SDIO_CMD_CRC_8822C */ + +#define BIT_SHIFT_SDIO_CMD_CRC_V1_8822C 0 +#define BIT_MASK_SDIO_CMD_CRC_V1_8822C 0xff +#define BIT_SDIO_CMD_CRC_V1_8822C(x) \ + (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822C) \ + << BIT_SHIFT_SDIO_CMD_CRC_V1_8822C) +#define BITS_SDIO_CMD_CRC_V1_8822C \ + (BIT_MASK_SDIO_CMD_CRC_V1_8822C << BIT_SHIFT_SDIO_CMD_CRC_V1_8822C) +#define BIT_CLEAR_SDIO_CMD_CRC_V1_8822C(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8822C)) +#define BIT_GET_SDIO_CMD_CRC_V1_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822C) & \ + BIT_MASK_SDIO_CMD_CRC_V1_8822C) +#define BIT_SET_SDIO_CMD_CRC_V1_8822C(x, v) \ + (BIT_CLEAR_SDIO_CMD_CRC_V1_8822C(x) | BIT_SDIO_CMD_CRC_V1_8822C(v)) + +/* 2 REG_SDIO_HSISR_8822C */ +#define BIT_DRV_WLAN_INT_CLR_8822C BIT(1) +#define BIT_DRV_WLAN_INT_8822C BIT(0) + +/* 2 REG_SDIO_HSIMR_8822C */ +#define BIT_HISR_MASK_8822C BIT(0) + +/* 2 REG_SDIO_DIOERR_RPT_8822C */ +#define BIT_SDIO_PAGE_ERR_8822C BIT(0) + +/* 2 REG_SDIO_CMD_ERRCNT_8822C */ + +#define BIT_SHIFT_CMD_CRC_ERR_CNT_8822C 0 +#define BIT_MASK_CMD_CRC_ERR_CNT_8822C 0xff +#define BIT_CMD_CRC_ERR_CNT_8822C(x) \ + (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822C) \ + << BIT_SHIFT_CMD_CRC_ERR_CNT_8822C) +#define BITS_CMD_CRC_ERR_CNT_8822C \ + (BIT_MASK_CMD_CRC_ERR_CNT_8822C << BIT_SHIFT_CMD_CRC_ERR_CNT_8822C) +#define BIT_CLEAR_CMD_CRC_ERR_CNT_8822C(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8822C)) +#define BIT_GET_CMD_CRC_ERR_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822C) & \ + BIT_MASK_CMD_CRC_ERR_CNT_8822C) +#define BIT_SET_CMD_CRC_ERR_CNT_8822C(x, v) \ + (BIT_CLEAR_CMD_CRC_ERR_CNT_8822C(x) | BIT_CMD_CRC_ERR_CNT_8822C(v)) + +/* 2 REG_SDIO_DATA_ERRCNT_8822C */ + +#define BIT_SHIFT_DATA_CRC_ERR_CNT_8822C 0 +#define BIT_MASK_DATA_CRC_ERR_CNT_8822C 0xff +#define BIT_DATA_CRC_ERR_CNT_8822C(x) \ + (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822C) \ + << BIT_SHIFT_DATA_CRC_ERR_CNT_8822C) +#define BITS_DATA_CRC_ERR_CNT_8822C \ + (BIT_MASK_DATA_CRC_ERR_CNT_8822C << BIT_SHIFT_DATA_CRC_ERR_CNT_8822C) +#define BIT_CLEAR_DATA_CRC_ERR_CNT_8822C(x) \ + ((x) & (~BITS_DATA_CRC_ERR_CNT_8822C)) +#define BIT_GET_DATA_CRC_ERR_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822C) & \ + BIT_MASK_DATA_CRC_ERR_CNT_8822C) +#define BIT_SET_DATA_CRC_ERR_CNT_8822C(x, v) \ + (BIT_CLEAR_DATA_CRC_ERR_CNT_8822C(x) | BIT_DATA_CRC_ERR_CNT_8822C(v)) + +/* 2 REG_SDIO_CMD_ERR_CONTENT_8822C */ + +#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C 0 +#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C 0xffffffffffL +#define BIT_SDIO_CMD_ERR_CONTENT_8822C(x) \ + (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C) \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C) +#define BITS_SDIO_CMD_ERR_CONTENT_8822C \ + (BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C) +#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822C(x) \ + ((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8822C)) +#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C) & \ + BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C) +#define BIT_SET_SDIO_CMD_ERR_CONTENT_8822C(x, v) \ + (BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822C(x) | \ + BIT_SDIO_CMD_ERR_CONTENT_8822C(v)) + +/* 2 REG_SDIO_CRC_ERR_IDX_8822C */ +#define BIT_D3_CRC_ERR_8822C BIT(4) +#define BIT_D2_CRC_ERR_8822C BIT(3) +#define BIT_D1_CRC_ERR_8822C BIT(2) +#define BIT_D0_CRC_ERR_8822C BIT(1) +#define BIT_CMD_CRC_ERR_8822C BIT(0) + +/* 2 REG_SDIO_DATA_CRC_8822C */ + +#define BIT_SHIFT_SDIO_DATA_CRC_8822C 0 +#define BIT_MASK_SDIO_DATA_CRC_8822C 0xffff +#define BIT_SDIO_DATA_CRC_8822C(x) \ + (((x) & BIT_MASK_SDIO_DATA_CRC_8822C) << BIT_SHIFT_SDIO_DATA_CRC_8822C) +#define BITS_SDIO_DATA_CRC_8822C \ + (BIT_MASK_SDIO_DATA_CRC_8822C << BIT_SHIFT_SDIO_DATA_CRC_8822C) +#define BIT_CLEAR_SDIO_DATA_CRC_8822C(x) ((x) & (~BITS_SDIO_DATA_CRC_8822C)) +#define BIT_GET_SDIO_DATA_CRC_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822C) & BIT_MASK_SDIO_DATA_CRC_8822C) +#define BIT_SET_SDIO_DATA_CRC_8822C(x, v) \ + (BIT_CLEAR_SDIO_DATA_CRC_8822C(x) | BIT_SDIO_DATA_CRC_8822C(v)) + +/* 2 REG_SDIO_TRANS_FIFO_STATUS_8822C */ +#define BIT_TRANS_FIFO_UNDERFLOW_8822C BIT(1) +#define BIT_TRANS_FIFO_OVERFLOW_8822C BIT(0) + +#endif diff --git a/hal/halmac/halmac_reg_8822c.h b/hal/halmac/halmac_reg_8822c.h new file mode 100644 index 0000000..b71418f --- /dev/null +++ b/hal/halmac/halmac_reg_8822c.h @@ -0,0 +1,875 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef __INC_HALMAC_REG_8822C_H +#define __INC_HALMAC_REG_8822C_H + +#define REG_SYS_ISO_CTRL_8822C 0x0000 +#define REG_SYS_FUNC_EN_8822C 0x0002 +#define REG_SYS_PW_CTRL_8822C 0x0004 +#define REG_SYS_CLK_CTRL_8822C 0x0008 +#define REG_SYS_EEPROM_CTRL_8822C 0x000A +#define REG_EE_VPD_8822C 0x000C +#define REG_SYS_SWR_CTRL1_8822C 0x0010 +#define REG_SYS_SWR_CTRL2_8822C 0x0014 +#define REG_SYS_SWR_CTRL3_8822C 0x0018 +#define REG_RSV_CTRL_8822C 0x001C +#define REG_RF_CTRL_8822C 0x001F +#define REG_AFE_LDO_CTRL_8822C 0x0020 +#define REG_AFE_CTRL1_8822C 0x0024 +#define REG_ANAPARSW_POW_MAC_8822C 0x0028 +#define REG_ANAPARLDO_POW_MAC_8822C 0x0029 +#define REG_ANAPAR_POW_MAC_8822C 0x002A +#define REG_ANAPAR_POW_XTAL_8822C 0x002B +#define REG_ANAPARLDO_MAC_8822C 0x002C +#define REG_EFUSE_CTRL_8822C 0x0030 +#define REG_LDO_EFUSE_CTRL_8822C 0x0034 +#define REG_PWR_OPTION_CTRL_8822C 0x0038 +#define REG_CAL_TIMER_8822C 0x003C +#define REG_ACLK_MON_8822C 0x003E +#define REG_GPIO_MUXCFG_2_8822C 0x003F +#define REG_GPIO_MUXCFG_8822C 0x0040 +#define REG_GPIO_PIN_CTRL_8822C 0x0044 +#define REG_GPIO_INTM_8822C 0x0048 +#define REG_LED_CFG_8822C 0x004C +#define REG_FSIMR_8822C 0x0050 +#define REG_FSISR_8822C 0x0054 +#define REG_HSIMR_8822C 0x0058 +#define REG_HSISR_8822C 0x005C +#define REG_GPIO_EXT_CTRL_8822C 0x0060 +#define REG_PAD_CTRL1_8822C 0x0064 +#define REG_WL_BT_PWR_CTRL_8822C 0x0068 +#define REG_SDM_DEBUG_8822C 0x006C +#define REG_SYS_SDIO_CTRL_8822C 0x0070 +#define REG_HCI_OPT_CTRL_8822C 0x0074 +#define REG_HCI_BG_CTRL_8822C 0x0078 +#define REG_HCI_LDO_CTRL_8822C 0x007A +#define REG_LDO_SWR_CTRL_8822C 0x007C +#define REG_MCUFW_CTRL_8822C 0x0080 +#define REG_MCU_TST_CFG_8822C 0x0084 +#define REG_HMEBOX_E0_E1_8822C 0x0088 +#define REG_HMEBOX_E2_E3_8822C 0x008C +#define REG_WLLPS_CTRL_8822C 0x0090 +#define REG_GPIO_DEBOUNCE_CTRL_8822C 0x0098 +#define REG_RPWM2_8822C 0x009C +#define REG_SYSON_FSM_MON_8822C 0x00A0 +#define REG_PMC_DBG_CTRL1_8822C 0x00A8 +#define REG_HIMR0_8822C 0x00B0 +#define REG_HISR0_8822C 0x00B4 +#define REG_HIMR1_8822C 0x00B8 +#define REG_HISR1_8822C 0x00BC +#define REG_DBG_PORT_SEL_8822C 0x00C0 +#define REG_PAD_CTRL2_8822C 0x00C4 +#define REG_PMC_DBG_CTRL2_8822C 0x00CC +#define REG_BIST_CTRL_8822C 0x00D0 +#define REG_BIST_RPT_8822C 0x00D4 +#define REG_MEM_CTRL_8822C 0x00D8 +#define REG_USB_SIE_INTF_8822C 0x00E0 +#define REG_PCIE_MIO_INTF_8822C 0x00E4 +#define REG_PCIE_MIO_INTD_8822C 0x00E8 +#define REG_WLRF1_8822C 0x00EC +#define REG_SYS_CFG1_8822C 0x00F0 +#define REG_SYS_STATUS1_8822C 0x00F4 +#define REG_SYS_STATUS2_8822C 0x00F8 +#define REG_SYS_CFG2_8822C 0x00FC +#define REG_SYS_CFG3_8822C 0x1000 +#define REG_ANAPARSW_MAC_0_8822C 0x1010 +#define REG_ANAPARSW_MAC_1_8822C 0x1014 +#define REG_ANAPAR_MAC_0_8822C 0x1018 +#define REG_ANAPAR_MAC_1_8822C 0x101C +#define REG_ANAPAR_MAC_2_8822C 0x1020 +#define REG_ANAPAR_XTAL_0_8822C 0x1040 +#define REG_ANAPAR_XTAL_1_8822C 0x1044 +#define REG_ANAPAR_XTAL_2_8822C 0x1048 +#define REG_ANAPAR_XTAL_3_8822C 0x104C +#define REG_ANAPAR_XTAL_AACK_0_8822C 0x1054 +#define REG_ANAPAR_XTAL_AACK_1_8822C 0x1058 +#define REG_ANAPAR_XTAL_MODE_DECODER_8822C 0x1064 +#define REG_SYS_CFG5_8822C 0x1070 +#define REG_CPU_DMEM_CON_8822C 0x1080 +#define REG_BOOT_REASON_8822C 0x1088 +#define REG_HIMR2_8822C 0x10B0 +#define REG_HISR2_8822C 0x10B4 +#define REG_HIMR3_8822C 0x10B8 +#define REG_HISR3_8822C 0x10BC +#define REG_SW_MDIO_8822C 0x10C0 +#define REG_H2C_PKT_READADDR_8822C 0x10D0 +#define REG_H2C_PKT_WRITEADDR_8822C 0x10D4 +#define REG_MEM_PWR_CRTL_8822C 0x10D8 +#define REG_FW_DBG6_8822C 0x10F8 +#define REG_FW_DBG7_8822C 0x10FC +#define REG_CR_8822C 0x0100 +#define REG_PG_SIZE_8822C 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL_8822C 0x0106 +#define REG_TSF_CLK_STATE_8822C 0x0108 +#define REG_TXDMA_PQ_MAP_8822C 0x010C +#define REG_TRXFF_BNDY_8822C 0x0114 +#define REG_PTA_I2C_MBOX_8822C 0x0118 +#define REG_RXFF_BNDY_8822C 0x011C +#define REG_FE1IMR_8822C 0x0120 +#define REG_FE1ISR_8822C 0x0124 +#define REG_CPWM_8822C 0x012C +#define REG_FWIMR_8822C 0x0130 +#define REG_FWISR_8822C 0x0134 +#define REG_FTIMR_8822C 0x0138 +#define REG_FTISR_8822C 0x013C +#define REG_PKTBUF_DBG_CTRL_8822C 0x0140 +#define REG_PKTBUF_DBG_DATA_L_8822C 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8822C 0x0148 +#define REG_CPWM2_8822C 0x014C +#define REG_TC0_CTRL_8822C 0x0150 +#define REG_TC1_CTRL_8822C 0x0154 +#define REG_TC2_CTRL_8822C 0x0158 +#define REG_TC3_CTRL_8822C 0x015C +#define REG_TC4_CTRL_8822C 0x0160 +#define REG_TCUNIT_BASE_8822C 0x0164 +#define REG_TC5_CTRL_8822C 0x0168 +#define REG_TC6_CTRL_8822C 0x016C +#define REG_MBIST_DRF_FAIL_8822C 0x0170 +#define REG_MBIST_START_PAUSE_8822C 0x0174 +#define REG_MBIST_DONE_8822C 0x0178 +#define REG_MBIST_READ_BIST_RPT_8822C 0x017C +#define REG_AES_DECRPT_DATA_8822C 0x0180 +#define REG_AES_DECRPT_CFG_8822C 0x0184 +#define REG_HIOE_CTRL_8822C 0x0188 +#define REG_HIOE_CFG_FILE_8822C 0x018C +#define REG_TMETER_8822C 0x0190 +#define REG_OSC_32K_CTRL_8822C 0x0194 +#define REG_32K_CAL_REG1_8822C 0x0198 +#define REG_C2HEVT_8822C 0x01A0 +#define REG_C2HEVT_1_8822C 0x01A4 +#define REG_C2HEVT_2_8822C 0x01A8 +#define REG_C2HEVT_3_8822C 0x01AC +#define REG_SW_DEFINED_PAGE1_8822C 0x01B8 +#define REG_SW_DEFINED_PAGE2_8822C 0x01BC +#define REG_MCUTST_I_8822C 0x01C0 +#define REG_MCUTST_II_8822C 0x01C4 +#define REG_FMETHR_8822C 0x01C8 +#define REG_HMETFR_8822C 0x01CC +#define REG_HMEBOX0_8822C 0x01D0 +#define REG_HMEBOX1_8822C 0x01D4 +#define REG_HMEBOX2_8822C 0x01D8 +#define REG_HMEBOX3_8822C 0x01DC +#define REG_BB_ACCESS_CTRL_8822C 0x01E8 +#define REG_BB_ACCESS_DATA_8822C 0x01EC +#define REG_HMEBOX_E0_8822C 0x01F0 +#define REG_HMEBOX_E1_8822C 0x01F4 +#define REG_HMEBOX_E2_8822C 0x01F8 +#define REG_HMEBOX_E3_8822C 0x01FC +#define REG_CR_EXT_8822C 0x1100 +#define REG_FWFF_8822C 0x1114 +#define REG_RXFF_PTR_V1_8822C 0x1118 +#define REG_RXFF_WTR_V1_8822C 0x111C +#define REG_FE2IMR_8822C 0x1120 +#define REG_FE2ISR_8822C 0x1124 +#define REG_FE3IMR_8822C 0x1128 +#define REG_FE3ISR_8822C 0x112C +#define REG_FE4IMR_8822C 0x1130 +#define REG_FE4ISR_8822C 0x1134 +#define REG_FT1IMR_8822C 0x1138 +#define REG_FT1ISR_8822C 0x113C +#define REG_SPWR0_8822C 0x1140 +#define REG_SPWR1_8822C 0x1144 +#define REG_SPWR2_8822C 0x1148 +#define REG_SPWR3_8822C 0x114C +#define REG_POWSEQ_8822C 0x1150 +#define REG_TC7_CTRL_V1_8822C 0x1158 +#define REG_TC8_CTRL_V1_8822C 0x115C +#define REG_RX_BCN_TBTT_ITVL0_8822C 0x1160 +#define REG_RX_BCN_TBTT_ITVL1_8822C 0x1164 +#define REG_IO_WRAP_ERR_FLAG_8822C 0x1170 +#define REG_SPEED_SENSOR_8822C 0x1180 +#define REG_SPEED_SENSOR1_8822C 0x1184 +#define REG_SPEED_SENSOR2_8822C 0x1188 +#define REG_SPEED_SENSOR3_8822C 0x118C +#define REG_SPEED_SENSOR4_8822C 0x1190 +#define REG_SPEED_SENSOR5_8822C 0x1194 +#define REG_COUNTER_CTRL_8822C 0x11C4 +#define REG_COUNTER_THRESHOLD_8822C 0x11C8 +#define REG_COUNTER_SET_8822C 0x11CC +#define REG_COUNTER_OVERFLOW_8822C 0x11D0 +#define REG_TXDMA_LEN_THRESHOLD_8822C 0x11D4 +#define REG_RXDMA_LEN_THRESHOLD_8822C 0x11D8 +#define REG_PCIE_EXEC_TIME_THRESHOLD_8822C 0x11DC +#define REG_FT2IMR_8822C 0x11E0 +#define REG_FT2ISR_8822C 0x11E4 +#define REG_MSG2_8822C 0x11F0 +#define REG_MSG3_8822C 0x11F4 +#define REG_MSG4_8822C 0x11F8 +#define REG_MSG5_8822C 0x11FC +#define REG_FIFOPAGE_CTRL_1_8822C 0x0200 +#define REG_FIFOPAGE_CTRL_2_8822C 0x0204 +#define REG_AUTO_LLT_V1_8822C 0x0208 +#define REG_TXDMA_OFFSET_CHK_8822C 0x020C +#define REG_TXDMA_STATUS_8822C 0x0210 +#define REG_TX_DMA_DBG_8822C 0x0214 +#define REG_TQPNT1_8822C 0x0218 +#define REG_TQPNT2_8822C 0x021C +#define REG_TQPNT3_8822C 0x0220 +#define REG_TQPNT4_8822C 0x0224 +#define REG_RQPN_CTRL_1_8822C 0x0228 +#define REG_RQPN_CTRL_2_8822C 0x022C +#define REG_FIFOPAGE_INFO_1_8822C 0x0230 +#define REG_FIFOPAGE_INFO_2_8822C 0x0234 +#define REG_FIFOPAGE_INFO_3_8822C 0x0238 +#define REG_FIFOPAGE_INFO_4_8822C 0x023C +#define REG_FIFOPAGE_INFO_5_8822C 0x0240 +#define REG_H2C_HEAD_8822C 0x0244 +#define REG_H2C_TAIL_8822C 0x0248 +#define REG_H2C_READ_ADDR_8822C 0x024C +#define REG_H2C_WR_ADDR_8822C 0x0250 +#define REG_H2C_INFO_8822C 0x0254 +#define REG_PGSUB_CNT_8822C 0x026C +#define REG_PGSUB_H_8822C 0x0270 +#define REG_PGSUB_N_8822C 0x0274 +#define REG_PGSUB_L_8822C 0x0278 +#define REG_PGSUB_E_8822C 0x027C +#define REG_RXDMA_AGG_PG_TH_8822C 0x0280 +#define REG_RXPKT_NUM_8822C 0x0284 +#define REG_RXDMA_STATUS_8822C 0x0288 +#define REG_RXDMA_DPR_8822C 0x028C +#define REG_RXDMA_MODE_8822C 0x0290 +#define REG_C2H_PKT_8822C 0x0294 +#define REG_FWFF_C2H_8822C 0x0298 +#define REG_FWFF_CTRL_8822C 0x029C +#define REG_FWFF_PKT_INFO_8822C 0x02A0 +#define REG_RXPKTNUM_8822C 0x02B0 +#define REG_RXPKTNUM_TH_8822C 0x02B4 +#define REG_FW_MSG1_8822C 0x02E0 +#define REG_FW_MSG2_8822C 0x02E4 +#define REG_FW_MSG3_8822C 0x02E8 +#define REG_FW_MSG4_8822C 0x02EC +#define REG_DDMA_CH0SA_8822C 0x1200 +#define REG_DDMA_CH0DA_8822C 0x1204 +#define REG_DDMA_CH0CTRL_8822C 0x1208 +#define REG_DDMA_CH1SA_8822C 0x1210 +#define REG_DDMA_CH1DA_8822C 0x1214 +#define REG_DDMA_CH1CTRL_8822C 0x1218 +#define REG_DDMA_CH2SA_8822C 0x1220 +#define REG_DDMA_CH2DA_8822C 0x1224 +#define REG_DDMA_CH2CTRL_8822C 0x1228 +#define REG_DDMA_CH3SA_8822C 0x1230 +#define REG_DDMA_CH3DA_8822C 0x1234 +#define REG_DDMA_CH3CTRL_8822C 0x1238 +#define REG_DDMA_CH4SA_8822C 0x1240 +#define REG_DDMA_CH4DA_8822C 0x1244 +#define REG_DDMA_CH4CTRL_8822C 0x1248 +#define REG_DDMA_CH5SA_8822C 0x1250 +#define REG_DDMA_CH5DA_8822C 0x1254 +#define REG_DDMA_CH5CTRL_8822C 0x1258 +#define REG_DDMA_INT_MSK_8822C 0x12E0 +#define REG_DDMA_CHSTATUS_8822C 0x12E8 +#define REG_DDMA_CHKSUM_8822C 0x12F0 +#define REG_DDMA_MONITOR_8822C 0x12FC +#define REG_PCIE_CTRL_8822C 0x0300 +#define REG_INT_MIG_8822C 0x0304 +#define REG_BCNQ_TXBD_DESA_8822C 0x0308 +#define REG_MGQ_TXBD_DESA_8822C 0x0310 +#define REG_VOQ_TXBD_DESA_8822C 0x0318 +#define REG_VIQ_TXBD_DESA_8822C 0x0320 +#define REG_BEQ_TXBD_DESA_8822C 0x0328 +#define REG_BKQ_TXBD_DESA_8822C 0x0330 +#define REG_RXQ_RXBD_DESA_8822C 0x0338 +#define REG_HI0Q_TXBD_DESA_8822C 0x0340 +#define REG_HI1Q_TXBD_DESA_8822C 0x0348 +#define REG_HI2Q_TXBD_DESA_8822C 0x0350 +#define REG_HI3Q_TXBD_DESA_8822C 0x0358 +#define REG_HI4Q_TXBD_DESA_8822C 0x0360 +#define REG_HI5Q_TXBD_DESA_8822C 0x0368 +#define REG_HI6Q_TXBD_DESA_8822C 0x0370 +#define REG_HI7Q_TXBD_DESA_8822C 0x0378 +#define REG_MGQ_TXBD_NUM_8822C 0x0380 +#define REG_RX_RXBD_NUM_8822C 0x0382 +#define REG_VOQ_TXBD_NUM_8822C 0x0384 +#define REG_VIQ_TXBD_NUM_8822C 0x0386 +#define REG_BEQ_TXBD_NUM_8822C 0x0388 +#define REG_BKQ_TXBD_NUM_8822C 0x038A +#define REG_HI0Q_TXBD_NUM_8822C 0x038C +#define REG_HI1Q_TXBD_NUM_8822C 0x038E +#define REG_HI2Q_TXBD_NUM_8822C 0x0390 +#define REG_HI3Q_TXBD_NUM_8822C 0x0392 +#define REG_HI4Q_TXBD_NUM_8822C 0x0394 +#define REG_HI5Q_TXBD_NUM_8822C 0x0396 +#define REG_HI6Q_TXBD_NUM_8822C 0x0398 +#define REG_HI7Q_TXBD_NUM_8822C 0x039A +#define REG_TSFTIMER_HCI_8822C 0x039C +#define REG_BD_RWPTR_CLR_8822C 0x039C +#define REG_VOQ_TXBD_IDX_8822C 0x03A0 +#define REG_VIQ_TXBD_IDX_8822C 0x03A4 +#define REG_BEQ_TXBD_IDX_8822C 0x03A8 +#define REG_BKQ_TXBD_IDX_8822C 0x03AC +#define REG_MGQ_TXBD_IDX_8822C 0x03B0 +#define REG_RXQ_RXBD_IDX_8822C 0x03B4 +#define REG_HI0Q_TXBD_IDX_8822C 0x03B8 +#define REG_HI1Q_TXBD_IDX_8822C 0x03BC +#define REG_HI2Q_TXBD_IDX_8822C 0x03C0 +#define REG_HI3Q_TXBD_IDX_8822C 0x03C4 +#define REG_HI4Q_TXBD_IDX_8822C 0x03C8 +#define REG_HI5Q_TXBD_IDX_8822C 0x03CC +#define REG_HI6Q_TXBD_IDX_8822C 0x03D0 +#define REG_HI7Q_TXBD_IDX_8822C 0x03D4 +#define REG_DBG_SEL_V1_8822C 0x03D8 +#define REG_PCIE_HRPWM1_V1_8822C 0x03D9 +#define REG_PCIE_HCPWM1_V1_8822C 0x03DA +#define REG_PCIE_CTRL2_8822C 0x03DB +#define REG_PCIE_HRPWM2_V1_8822C 0x03DC +#define REG_PCIE_HCPWM2_V1_8822C 0x03DE +#define REG_PCIE_H2C_MSG_V1_8822C 0x03E0 +#define REG_PCIE_C2H_MSG_V1_8822C 0x03E4 +#define REG_DBI_WDATA_V1_8822C 0x03E8 +#define REG_DBI_RDATA_V1_8822C 0x03EC +#define REG_DBI_FLAG_V1_8822C 0x03F0 +#define REG_MDIO_V1_8822C 0x03F4 +#define REG_PCIE_MIX_CFG_8822C 0x03F8 +#define REG_HCI_MIX_CFG_8822C 0x03FC +#define REG_STC_INT_CS_8822C 0x1300 +#define REG_ST_INT_CFG_8822C 0x1304 +#define REG_H2CQ_TXBD_DESA_8822C 0x1320 +#define REG_H2CQ_TXBD_NUM_8822C 0x1328 +#define REG_H2CQ_TXBD_IDX_8822C 0x132C +#define REG_H2CQ_CSR_8822C 0x1330 +#define REG_CHANGE_PCIE_SPEED_8822C 0x1350 +#define REG_DEBUG_STATE1_8822C 0x1354 +#define REG_DEBUG_STATE2_8822C 0x1358 +#define REG_DEBUG_STATE3_8822C 0x135C +#define REG_CHNL_DMA_CFG_V1_8822C 0x137C +#define REG_PCIE_HISR0_V1_8822C 0x13B4 +#define REG_PCIE_HISR1_V1_8822C 0x13BC +#define REG_PCIE_HISR2_V1_8822C 0x23B4 +#define REG_PCIE_HISR3_V1_8822C 0x23BC +#define REG_Q0_INFO_8822C 0x0400 +#define REG_Q1_INFO_8822C 0x0404 +#define REG_Q2_INFO_8822C 0x0408 +#define REG_Q3_INFO_8822C 0x040C +#define REG_MGQ_INFO_8822C 0x0410 +#define REG_HIQ_INFO_8822C 0x0414 +#define REG_BCNQ_INFO_8822C 0x0418 +#define REG_TXPKT_EMPTY_8822C 0x041A +#define REG_CPU_MGQ_INFO_8822C 0x041C +#define REG_FWHW_TXQ_CTRL_8822C 0x0420 +#define REG_DATAFB_SEL_8822C 0x0423 +#define REG_BCNQ_BDNY_V1_8822C 0x0424 +#define REG_LIFETIME_EN_8822C 0x0426 +#define REG_SPEC_SIFS_8822C 0x0428 +#define REG_RETRY_LIMIT_8822C 0x042A +#define REG_TXBF_CTRL_8822C 0x042C +#define REG_DARFRC_8822C 0x0430 +#define REG_DARFRCH_8822C 0x0434 +#define REG_RARFRC_8822C 0x0438 +#define REG_RARFRCH_8822C 0x043C +#define REG_RRSR_8822C 0x0440 +#define REG_ARFR0_8822C 0x0444 +#define REG_ARFRH0_8822C 0x0448 +#define REG_ARFR1_V1_8822C 0x044C +#define REG_ARFRH1_V1_8822C 0x0450 +#define REG_CCK_CHECK_8822C 0x0454 +#define REG_AMPDU_MAX_TIME_V1_8822C 0x0455 +#define REG_BCNQ1_BDNY_V1_8822C 0x0456 +#define REG_AMPDU_MAX_LENGTH_HT_8822C 0x0458 +#define REG_ACQ_STOP_8822C 0x045C +#define REG_NDPA_RATE_8822C 0x045D +#define REG_TX_HANG_CTRL_8822C 0x045E +#define REG_NDPA_OPT_CTRL_8822C 0x045F +#define REG_AMPDU_MAX_LENGTH_VHT_8822C 0x0460 +#define REG_RD_RESP_PKT_TH_8822C 0x0463 +#define REG_CMDQ_INFO_8822C 0x0464 +#define REG_Q4_INFO_8822C 0x0468 +#define REG_Q5_INFO_8822C 0x046C +#define REG_Q6_INFO_8822C 0x0470 +#define REG_Q7_INFO_8822C 0x0474 +#define REG_WMAC_LBK_BUF_HD_V1_8822C 0x0478 +#define REG_MGQ_BDNY_V1_8822C 0x047A +#define REG_TXRPT_CTRL_8822C 0x047C +#define REG_INIRTS_RATE_SEL_8822C 0x0480 +#define REG_BASIC_CFEND_RATE_8822C 0x0481 +#define REG_STBC_CFEND_RATE_8822C 0x0482 +#define REG_DATA_SC_8822C 0x0483 +#define REG_MACID_SLEEP3_8822C 0x0484 +#define REG_MACID_SLEEP1_8822C 0x0488 +#define REG_ARFR2_V1_8822C 0x048C +#define REG_ARFRH2_V1_8822C 0x0490 +#define REG_ARFR3_V1_8822C 0x0494 +#define REG_ARFRH3_V1_8822C 0x0498 +#define REG_ARFR4_8822C 0x049C +#define REG_ARFRH4_8822C 0x04A0 +#define REG_ARFR5_8822C 0x04A4 +#define REG_ARFRH5_8822C 0x04A8 +#define REG_TXRPT_START_OFFSET_8822C 0x04AC +#define REG_POWER_STAGE1_8822C 0x04B4 +#define REG_POWER_STAGE2_8822C 0x04B8 +#define REG_SW_AMPDU_BURST_MODE_CTRL_8822C 0x04BC +#define REG_PKT_LIFE_TIME_8822C 0x04C0 +#define REG_STBC_SETTING_8822C 0x04C4 +#define REG_STBC_SETTING2_8822C 0x04C5 +#define REG_QUEUE_CTRL_8822C 0x04C6 +#define REG_SINGLE_AMPDU_CTRL_8822C 0x04C7 +#define REG_PROT_MODE_CTRL_8822C 0x04C8 +#define REG_BAR_MODE_CTRL_8822C 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8822C 0x04CF +#define REG_MACID_SLEEP2_8822C 0x04D0 +#define REG_MACID_SLEEP_8822C 0x04D4 +#define REG_HW_SEQ0_8822C 0x04D8 +#define REG_HW_SEQ1_8822C 0x04DA +#define REG_HW_SEQ2_8822C 0x04DC +#define REG_HW_SEQ3_8822C 0x04DE +#define REG_NULL_PKT_STATUS_V1_8822C 0x04E0 +#define REG_PTCL_ERR_STATUS_8822C 0x04E2 +#define REG_NULL_PKT_STATUS_EXTEND_8822C 0x04E3 +#define REG_HQMGQ_DROP_8822C 0x04E4 +#define REG_PRECNT_CTRL_8822C 0x04E5 +#define REG_BT_POLLUTE_PKT_CNT_8822C 0x04E8 +#define REG_PTCL_DBG_8822C 0x04EC +#define REG_CPUMGQ_TIMER_CTRL2_8822C 0x04F4 +#define REG_DUMMY_PAGE4_V1_8822C 0x04FC +#define REG_MOREDATA_8822C 0x04FE +#define REG_Q0_Q1_INFO_8822C 0x1400 +#define REG_Q2_Q3_INFO_8822C 0x1404 +#define REG_Q4_Q5_INFO_8822C 0x1408 +#define REG_Q6_Q7_INFO_8822C 0x140C +#define REG_MGQ_HIQ_INFO_8822C 0x1410 +#define REG_CMDQ_BCNQ_INFO_8822C 0x1414 +#define REG_USEREG_SETTING_8822C 0x1420 +#define REG_AESIV_SETTING_8822C 0x1424 +#define REG_BF0_TIME_SETTING_8822C 0x1428 +#define REG_BF1_TIME_SETTING_8822C 0x142C +#define REG_BF_TIMEOUT_EN_8822C 0x1430 +#define REG_MACID_RELEASE0_8822C 0x1434 +#define REG_MACID_RELEASE1_8822C 0x1438 +#define REG_MACID_RELEASE2_8822C 0x143C +#define REG_MACID_RELEASE3_8822C 0x1440 +#define REG_MACID_RELEASE_SETTING_8822C 0x1444 +#define REG_FAST_EDCA_VOVI_SETTING_8822C 0x1448 +#define REG_FAST_EDCA_BEBK_SETTING_8822C 0x144C +#define REG_MACID_DROP0_8822C 0x1450 +#define REG_MACID_DROP1_8822C 0x1454 +#define REG_MACID_DROP2_8822C 0x1458 +#define REG_MACID_DROP3_8822C 0x145C +#define REG_R_MACID_RELEASE_SUCCESS_0_8822C 0x1460 +#define REG_R_MACID_RELEASE_SUCCESS_1_8822C 0x1464 +#define REG_R_MACID_RELEASE_SUCCESS_2_8822C 0x1468 +#define REG_R_MACID_RELEASE_SUCCESS_3_8822C 0x146C +#define REG_MGQ_FIFO_WRITE_POINTER_8822C 0x1470 +#define REG_MGQ_FIFO_READ_POINTER_8822C 0x1472 +#define REG_MGQ_FIFO_ENABLE_8822C 0x1472 +#define REG_MGQ_FIFO_RELEASE_INT_MASK_8822C 0x1474 +#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8822C 0x1476 +#define REG_MGQ_FIFO_VALID_MAP_8822C 0x1478 +#define REG_MGQ_FIFO_LIFETIME_8822C 0x147A +#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0x147C +#define REG_SHCUT_SETTING_8822C 0x1480 +#define REG_SHCUT_LLC_ETH_TYPE0_8822C 0x1484 +#define REG_SHCUT_LLC_ETH_TYPE1_8822C 0x1488 +#define REG_SHCUT_LLC_OUI0_8822C 0x148C +#define REG_SHCUT_LLC_OUI1_8822C 0x1490 +#define REG_SHCUT_LLC_OUI2_8822C 0x1494 +#define REG_MU_TX_CTL_8822C 0x14C0 +#define REG_MU_STA_GID_VLD_8822C 0x14C4 +#define REG_MU_STA_USER_POS_INFO_8822C 0x14C8 +#define REG_MU_STA_USER_POS_INFO_H_8822C 0x14CC +#define REG_CHNL_INFO_CTRL_8822C 0x14D0 +#define REG_CHNL_IDLE_TIME_8822C 0x14D4 +#define REG_CHNL_BUSY_TIME_8822C 0x14D8 +#define REG_MU_TRX_DBG_CNT_V1_8822C 0x14DC +#define REG_EDCA_VO_PARAM_8822C 0x0500 +#define REG_EDCA_VI_PARAM_8822C 0x0504 +#define REG_EDCA_BE_PARAM_8822C 0x0508 +#define REG_EDCA_BK_PARAM_8822C 0x050C +#define REG_BCNTCFG_8822C 0x0510 +#define REG_PIFS_8822C 0x0512 +#define REG_RDG_PIFS_8822C 0x0513 +#define REG_SIFS_8822C 0x0514 +#define REG_TSFTR_SYN_OFFSET_8822C 0x0518 +#define REG_AGGR_BREAK_TIME_8822C 0x051A +#define REG_SLOT_8822C 0x051B +#define REG_NOA_ON_ERLY_TIME_8822C 0x051C +#define REG_NOA_OFF_ERLY_TIME_8822C 0x051D +#define REG_TX_PTCL_CTRL_8822C 0x0520 +#define REG_TXPAUSE_8822C 0x0522 +#define REG_DIS_TXREQ_CLR_8822C 0x0523 +#define REG_RD_CTRL_8822C 0x0524 +#define REG_MBSSID_CTRL_8822C 0x0526 +#define REG_P2PPS_CTRL_8822C 0x0527 +#define REG_PKT_LIFETIME_CTRL_8822C 0x0528 +#define REG_P2PPS_SPEC_STATE_8822C 0x052B +#define REG_TXOP_LIMIT_CTRL_8822C 0x052C +#define REG_BAR_TX_CTRL_8822C 0x0530 +#define REG_P2PON_DIS_TXTIME_8822C 0x0531 +#define REG_CCA_TXEN_CNT_8822C 0x0534 +#define REG_MAX_INTER_COLLISION_8822C 0x0538 +#define REG_MAX_INTER_COLLISION_CNT_8822C 0x053C +#define REG_TBTT_PROHIBIT_8822C 0x0540 +#define REG_P2PPS_STATE_8822C 0x0543 +#define REG_RD_NAV_NXT_8822C 0x0544 +#define REG_NAV_PROT_LEN_8822C 0x0546 +#define REG_FTM_PTT_8822C 0x0548 +#define REG_FTM_TSF_8822C 0x054C +#define REG_BCN_CTRL_8822C 0x0550 +#define REG_BCN_CTRL_CLINT0_8822C 0x0551 +#define REG_MBID_NUM_8822C 0x0552 +#define REG_DUAL_TSF_RST_8822C 0x0553 +#define REG_MBSSID_BCN_SPACE_8822C 0x0554 +#define REG_DRVERLYINT_8822C 0x0558 +#define REG_BCNDMATIM_8822C 0x0559 +#define REG_ATIMWND_8822C 0x055A +#define REG_USTIME_TSF_8822C 0x055C +#define REG_BCN_MAX_ERR_8822C 0x055D +#define REG_RXTSF_OFFSET_CCK_8822C 0x055E +#define REG_RXTSF_OFFSET_OFDM_8822C 0x055F +#define REG_TSFTR_8822C 0x0560 +#define REG_TSFTR_1_8822C 0x0564 +#define REG_FREERUN_CNT_8822C 0x0568 +#define REG_FREERUN_CNT_1_8822C 0x056C +#define REG_ATIMWND1_V1_8822C 0x0570 +#define REG_TBTT_PROHIBIT_INFRA_8822C 0x0571 +#define REG_CTWND_8822C 0x0572 +#define REG_BCNIVLCUNT_8822C 0x0573 +#define REG_BCNDROPCTRL_8822C 0x0574 +#define REG_HGQ_TIMEOUT_PERIOD_8822C 0x0575 +#define REG_TXCMD_TIMEOUT_PERIOD_8822C 0x0576 +#define REG_MISC_CTRL_8822C 0x0577 +#define REG_BCN_CTRL_CLINT1_8822C 0x0578 +#define REG_BCN_CTRL_CLINT2_8822C 0x0579 +#define REG_BCN_CTRL_CLINT3_8822C 0x057A +#define REG_EXTEND_CTRL_8822C 0x057B +#define REG_P2PPS1_SPEC_STATE_8822C 0x057C +#define REG_P2PPS1_STATE_8822C 0x057D +#define REG_P2PPS2_SPEC_STATE_8822C 0x057E +#define REG_P2PPS2_STATE_8822C 0x057F +#define REG_PS_TIMER0_8822C 0x0580 +#define REG_PS_TIMER1_8822C 0x0584 +#define REG_PS_TIMER2_8822C 0x0588 +#define REG_TBTT_CTN_AREA_8822C 0x058C +#define REG_FORCE_BCN_IFS_8822C 0x058E +#define REG_TXOP_MIN_8822C 0x0590 +#define REG_PRE_BKF_TIME_8822C 0x0592 +#define REG_CROSS_TXOP_CTRL_8822C 0x0593 +#define REG_RX_TBTT_SHIFT_V1_8822C 0x0598 +#define REG_ATIMWND2_8822C 0x05A0 +#define REG_ATIMWND3_8822C 0x05A1 +#define REG_ATIMWND4_8822C 0x05A2 +#define REG_ATIMWND5_8822C 0x05A3 +#define REG_ATIMWND6_8822C 0x05A4 +#define REG_ATIMWND7_8822C 0x05A5 +#define REG_ATIMUGT_8822C 0x05A6 +#define REG_HIQ_NO_LMT_EN_8822C 0x05A7 +#define REG_DTIM_COUNTER_ROOT_8822C 0x05A8 +#define REG_DTIM_COUNTER_VAP1_8822C 0x05A9 +#define REG_DTIM_COUNTER_VAP2_8822C 0x05AA +#define REG_DTIM_COUNTER_VAP3_8822C 0x05AB +#define REG_DTIM_COUNTER_VAP4_8822C 0x05AC +#define REG_DTIM_COUNTER_VAP5_8822C 0x05AD +#define REG_DTIM_COUNTER_VAP6_8822C 0x05AE +#define REG_DTIM_COUNTER_VAP7_8822C 0x05AF +#define REG_DIS_ATIM_8822C 0x05B0 +#define REG_EARLY_128US_8822C 0x05B1 +#define REG_P2PPS1_CTRL_8822C 0x05B2 +#define REG_P2PPS2_CTRL_8822C 0x05B3 +#define REG_TIMER0_SRC_SEL_8822C 0x05B4 +#define REG_NOA_UNIT_SEL_8822C 0x05B5 +#define REG_P2POFF_DIS_TXTIME_8822C 0x05B7 +#define REG_MBSSID_BCN_SPACE2_8822C 0x05B8 +#define REG_MBSSID_BCN_SPACE3_8822C 0x05BC +#define REG_ACMHWCTRL_8822C 0x05C0 +#define REG_ACMRSTCTRL_8822C 0x05C1 +#define REG_ACMAVG_8822C 0x05C2 +#define REG_VO_ADMTIME_8822C 0x05C4 +#define REG_VI_ADMTIME_8822C 0x05C6 +#define REG_BE_ADMTIME_8822C 0x05C8 +#define REG_MAC_HEADER_NAV_OFFSET_8822C 0x05CA +#define REG_DIS_NDPA_NAV_CHECK_8822C 0x05CB +#define REG_EDCA_RANDOM_GEN_8822C 0x05CC +#define REG_TXCMD_NOA_SEL_8822C 0x05CF +#define REG_32K_CLK_SEL_8822C 0x05D0 +#define REG_EARLYINT_ADJUST_8822C 0x05D4 +#define REG_BCNERR_CNT_8822C 0x05D8 +#define REG_BCNERR_CNT_2_8822C 0x05DC +#define REG_NOA_PARAM_8822C 0x05E0 +#define REG_NOA_PARAM_1_8822C 0x05E4 +#define REG_NOA_PARAM_2_8822C 0x05E8 +#define REG_NOA_PARAM_3_8822C 0x05EC +#define REG_P2P_RST_8822C 0x05F0 +#define REG_SCHEDULER_RST_8822C 0x05F1 +#define REG_SCH_DBG_VALUE_8822C 0x05F4 +#define REG_SCH_TXCMD_8822C 0x05F8 +#define REG_PAGE5_DUMMY_8822C 0x05FC +#define REG_CPUMGQ_TX_TIMER_8822C 0x1500 +#define REG_PS_TIMER_A_8822C 0x1504 +#define REG_PS_TIMER_B_8822C 0x1508 +#define REG_PS_TIMER_C_8822C 0x150C +#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822C 0x1510 +#define REG_CPUMGQ_TX_TIMER_EARLY_8822C 0x1514 +#define REG_PS_TIMER_A_EARLY_8822C 0x1515 +#define REG_PS_TIMER_B_EARLY_8822C 0x1516 +#define REG_PS_TIMER_C_EARLY_8822C 0x1517 +#define REG_CPUMGQ_PARAMETER_8822C 0x1518 +#define REG_TSF_SYNC_ADJ_8822C 0x1520 +#define REG_TSF_ADJ_VLAUE_8822C 0x1524 +#define REG_TSF_ADJ_VLAUE_2_8822C 0x1528 +#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C 0x156C +#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C 0x1570 +#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C 0x1574 +#define REG_WMAC_CR_8822C 0x0600 +#define REG_WMAC_FWPKT_CR_8822C 0x0601 +#define REG_FW_STS_FILTER_8822C 0x0602 +#define REG_TCR_8822C 0x0604 +#define REG_RCR_8822C 0x0608 +#define REG_RX_PKT_LIMIT_8822C 0x060C +#define REG_RX_DLK_TIME_8822C 0x060D +#define REG_RX_DRVINFO_SZ_8822C 0x060F +#define REG_MACID_8822C 0x0610 +#define REG_MACID_H_8822C 0x0614 +#define REG_BSSID_8822C 0x0618 +#define REG_BSSID_H_8822C 0x061C +#define REG_MAR_8822C 0x0620 +#define REG_MAR_H_8822C 0x0624 +#define REG_MBIDCAMCFG_1_8822C 0x0628 +#define REG_MBIDCAMCFG_2_8822C 0x062C +#define REG_WMAC_TCR_TSFT_OFS_8822C 0x0630 +#define REG_UDF_THSD_8822C 0x0632 +#define REG_ZLD_NUM_8822C 0x0633 +#define REG_STMP_THSD_8822C 0x0634 +#define REG_WMAC_TXTIMEOUT_8822C 0x0635 +#define REG_USTIME_EDCA_8822C 0x0638 +#define REG_ACKTO_CCK_8822C 0x0639 +#define REG_MAC_SPEC_SIFS_8822C 0x063A +#define REG_RESP_SIFS_CCK_8822C 0x063C +#define REG_RESP_SIFS_OFDM_8822C 0x063E +#define REG_ACKTO_8822C 0x0640 +#define REG_CTS2TO_8822C 0x0641 +#define REG_EIFS_8822C 0x0642 +#define REG_RPFM_MAP0_8822C 0x0644 +#define REG_RPFM_MAP1_V1_8822C 0x0646 +#define REG_RPFM_CAM_CMD_8822C 0x0648 +#define REG_RPFM_CAM_RWD_8822C 0x064C +#define REG_NAV_CTRL_8822C 0x0650 +#define REG_BACAMCMD_8822C 0x0654 +#define REG_BACAMCONTENT_8822C 0x0658 +#define REG_BACAMCONTENT_H_8822C 0x065C +#define REG_LBDLY_8822C 0x0660 +#define REG_WMAC_BACAM_RPMEN_8822C 0x0661 +#define REG_TX_RX_8822C 0x0662 +#define REG_WMAC_BITMAP_CTL_8822C 0x0663 +#define REG_RXERR_RPT_8822C 0x0664 +#define REG_WMAC_TRXPTCL_CTL_8822C 0x0668 +#define REG_WMAC_TRXPTCL_CTL_H_8822C 0x066C +#define REG_CAMCMD_8822C 0x0670 +#define REG_CAMWRITE_8822C 0x0674 +#define REG_CAMREAD_8822C 0x0678 +#define REG_CAMDBG_8822C 0x067C +#define REG_SECCFG_8822C 0x0680 +#define REG_RXFILTER_CATEGORY_1_8822C 0x0682 +#define REG_RXFILTER_ACTION_1_8822C 0x0683 +#define REG_RXFILTER_CATEGORY_2_8822C 0x0684 +#define REG_RXFILTER_ACTION_2_8822C 0x0685 +#define REG_RXFILTER_CATEGORY_3_8822C 0x0686 +#define REG_RXFILTER_ACTION_3_8822C 0x0687 +#define REG_RXFLTMAP3_8822C 0x0688 +#define REG_RXFLTMAP4_8822C 0x068A +#define REG_RXFLTMAP5_8822C 0x068C +#define REG_RXFLTMAP6_8822C 0x068E +#define REG_WOW_CTRL_8822C 0x0690 +#define REG_NAN_RX_TSF_FILTER_8822C 0x0691 +#define REG_PS_RX_INFO_8822C 0x0692 +#define REG_WMMPS_UAPSD_TID_8822C 0x0693 +#define REG_LPNAV_CTRL_8822C 0x0694 +#define REG_WKFMCAM_CMD_8822C 0x0698 +#define REG_WKFMCAM_RWD_8822C 0x069C +#define REG_RXFLTMAP0_8822C 0x06A0 +#define REG_RXFLTMAP1_8822C 0x06A2 +#define REG_RXFLTMAP2_8822C 0x06A4 +#define REG_BCN_PSR_RPT_8822C 0x06A8 +#define REG_FLC_RPC_8822C 0x06AC +#define REG_FLC_RPCT_8822C 0x06AD +#define REG_FLC_PTS_8822C 0x06AE +#define REG_FLC_TRPC_8822C 0x06AF +#define REG_RXPKTMON_CTRL_8822C 0x06B0 +#define REG_STATE_MON_8822C 0x06B4 +#define REG_ERROR_MON_8822C 0x06B8 +#define REG_SEARCH_MACID_8822C 0x06BC +#define REG_BT_COEX_TABLE_8822C 0x06C0 +#define REG_BT_COEX_TABLE2_8822C 0x06C4 +#define REG_BT_COEX_BREAK_TABLE_8822C 0x06C8 +#define REG_BT_COEX_TABLE_H_8822C 0x06CC +#define REG_RXCMD_0_8822C 0x06D0 +#define REG_RXCMD_1_8822C 0x06D4 +#define REG_WMAC_RESP_TXINFO_8822C 0x06D8 +#define REG_BBPSF_CTRL_8822C 0x06DC +#define REG_P2P_RX_BCN_NOA_8822C 0x06E0 +#define REG_ASSOCIATED_BFMER0_INFO_8822C 0x06E4 +#define REG_ASSOCIATED_BFMER0_INFO_H_8822C 0x06E8 +#define REG_ASSOCIATED_BFMER1_INFO_8822C 0x06EC +#define REG_ASSOCIATED_BFMER1_INFO_H_8822C 0x06F0 +#define REG_TX_CSI_RPT_PARAM_BW20_8822C 0x06F4 +#define REG_TX_CSI_RPT_PARAM_BW40_8822C 0x06F8 +#define REG_CSI_PTR_8822C 0x06FC +#define REG_BCN_PSR_RPT2_8822C 0x1600 +#define REG_BCN_PSR_RPT3_8822C 0x1604 +#define REG_BCN_PSR_RPT4_8822C 0x1608 +#define REG_A1_ADDR_MASK_8822C 0x160C +#define REG_RXPSF_CTRL_8822C 0x1610 +#define REG_RXPSF_TYPE_CTRL_8822C 0x1614 +#define REG_CAM_ACCESS_CTRL_8822C 0x1618 +#define REG_HT_SND_REF_RATE_8822C 0x161C +#define REG_MACID2_8822C 0x1620 +#define REG_MACID2_H_8822C 0x1624 +#define REG_BSSID2_8822C 0x1628 +#define REG_BSSID2_H_8822C 0x162C +#define REG_MACID3_8822C 0x1630 +#define REG_MACID3_H_8822C 0x1634 +#define REG_BSSID3_8822C 0x1638 +#define REG_BSSID3_H_8822C 0x163C +#define REG_MACID4_8822C 0x1640 +#define REG_MACID4_H_8822C 0x1644 +#define REG_BSSID4_8822C 0x1648 +#define REG_BSSID4_H_8822C 0x164C +#define REG_NOA_REPORT_8822C 0x1650 +#define REG_NOA_REPORT_1_8822C 0x1654 +#define REG_NOA_REPORT_2_8822C 0x1658 +#define REG_NOA_REPORT_3_8822C 0x165C +#define REG_PWRBIT_SETTING_8822C 0x1660 +#define REG_GENERAL_OPTION_8822C 0x1664 +#define REG_CSI_RRSR_8822C 0x1678 +#define REG_MU_BF_OPTION_8822C 0x167C +#define REG_WMAC_PAUSE_BB_CLR_TH_8822C 0x167D +#define REG__WMAC_MULBK_BUF_8822C 0x167E +#define REG_WMAC_MU_OPTION_8822C 0x167F +#define REG_WMAC_MU_BF_CTL_8822C 0x1680 +#define REG_WMAC_MU_BFRPT_PARA_8822C 0x1682 +#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C 0x1684 +#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C 0x1686 +#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C 0x1688 +#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C 0x168A +#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C 0x168C +#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C 0x168E +#define REG_WMAC_BB_STOP_RX_COUNTER_8822C 0x1690 +#define REG_WMAC_PLCP_MONITOR_8822C 0x1694 +#define REG_WMAC_PLCP_MONITOR_MUTX_8822C 0x1698 +#define REG_WMAC_CSIDMA_CFG_8822C 0x169C +#define REG_TRANSMIT_ADDRSS_0_8822C 0x16A0 +#define REG_TRANSMIT_ADDRSS_0_H_8822C 0x16A4 +#define REG_TRANSMIT_ADDRSS_1_8822C 0x16A8 +#define REG_TRANSMIT_ADDRSS_1_H_8822C 0x16AC +#define REG_TRANSMIT_ADDRSS_2_8822C 0x16B0 +#define REG_TRANSMIT_ADDRSS_2_H_8822C 0x16B4 +#define REG_TRANSMIT_ADDRSS_3_8822C 0x16B8 +#define REG_TRANSMIT_ADDRSS_3_H_8822C 0x16BC +#define REG_TRANSMIT_ADDRSS_4_8822C 0x16C0 +#define REG_TRANSMIT_ADDRSS_4_H_8822C 0x16C4 +#define REG_MACID1_8822C 0x0700 +#define REG_MACID1_1_8822C 0x0704 +#define REG_BSSID1_8822C 0x0708 +#define REG_BSSID1_1_8822C 0x070C +#define REG_BCN_PSR_RPT1_8822C 0x0710 +#define REG_ASSOCIATED_BFMEE_SEL_8822C 0x0714 +#define REG_SND_PTCL_CTRL_8822C 0x0718 +#define REG_RX_CSI_RPT_INFO_8822C 0x071C +#define REG_NS_ARP_CTRL_8822C 0x0720 +#define REG_NS_ARP_INFO_8822C 0x0724 +#define REG_BEAMFORMING_INFO_NSARP_V1_8822C 0x0728 +#define REG_BEAMFORMING_INFO_NSARP_8822C 0x072C +#define REG_IPV6_8822C 0x0730 +#define REG_IPV6_1_8822C 0x0734 +#define REG_IPV6_2_8822C 0x0738 +#define REG_IPV6_3_8822C 0x073C +#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822C 0x0750 +#define REG_WMAC_SWAES_DIO_B63_B32_8822C 0x0754 +#define REG_WMAC_SWAES_DIO_B95_B64_8822C 0x0758 +#define REG_WMAC_SWAES_DIO_B127_B96_8822C 0x075C +#define REG_WMAC_SWAES_CFG_8822C 0x0760 +#define REG_BT_COEX_V2_8822C 0x0762 +#define REG_BT_COEX_8822C 0x0764 +#define REG_WLAN_ACT_MASK_CTRL_8822C 0x0768 +#define REG_WLAN_ACT_MASK_CTRL_1_8822C 0x076C +#define REG_BT_COEX_ENHANCED_INTR_CTRL_8822C 0x076E +#define REG_BT_ACT_STATISTICS_8822C 0x0770 +#define REG_BT_ACT_STATISTICS_1_8822C 0x0774 +#define REG_BT_STATISTICS_CONTROL_REGISTER_8822C 0x0778 +#define REG_BT_STATUS_REPORT_REGISTER_8822C 0x077C +#define REG_BT_INTERRUPT_CONTROL_REGISTER_8822C 0x0780 +#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822C 0x0784 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822C 0x0785 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8822C 0x0788 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8822C 0x078C +#define REG_BT_INTERRUPT_STATUS_REGISTER_8822C 0x078F +#define REG_BT_TDMA_TIME_REGISTER_8822C 0x0790 +#define REG_BT_ACT_REGISTER_8822C 0x0794 +#define REG_OBFF_CTRL_BASIC_8822C 0x0798 +#define REG_OBFF_CTRL2_TIMER_8822C 0x079C +#define REG_LTR_CTRL_BASIC_8822C 0x07A0 +#define REG_LTR_CTRL2_TIMER_THRESHOLD_8822C 0x07A4 +#define REG_LTR_IDLE_LATENCY_V1_8822C 0x07A8 +#define REG_LTR_ACTIVE_LATENCY_V1_8822C 0x07AC +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822C 0x07B0 +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8822C 0x07B4 +#define REG_WMAC_PKTCNT_RWD_8822C 0x07B8 +#define REG_WMAC_PKTCNT_CTRL_8822C 0x07BC +#define REG_IQ_DUMP_8822C 0x07C0 +#define REG_IQ_DUMP_1_8822C 0x07C4 +#define REG_IQ_DUMP_2_8822C 0x07C8 +#define REG_WMAC_FTM_CTL_8822C 0x07CC +#define REG_WMAC_IQ_MDPK_FUNC_8822C 0x07CE +#define REG_WMAC_OPTION_FUNCTION_8822C 0x07D0 +#define REG_WMAC_OPTION_FUNCTION_1_8822C 0x07D4 +#define REG_WMAC_OPTION_FUNCTION_2_8822C 0x07D8 +#define REG_RX_FILTER_FUNCTION_8822C 0x07DA +#define REG_NDP_SIG_8822C 0x07E0 +#define REG_TXCMD_INFO_FOR_RSP_PKT_8822C 0x07E4 +#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8822C 0x07E8 +#define REG_WSEC_OPTION_8822C 0x07EC +#define REG_RTS_ADDRESS_0_8822C 0x07F0 +#define REG_RTS_ADDRESS_0_1_8822C 0x07F4 +#define REG_RTS_ADDRESS_1_8822C 0x07F8 +#define REG_RTS_ADDRESS_1_1_8822C 0x07FC +#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822C 0x1700 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822C 0x1704 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C 0x1708 +#define REG_SDIO_TX_CTRL_8822C 0x10250000 +#define REG_SDIO_CMD11_VOL_SWITCH_8822C 0x10250004 +#define REG_SDIO_DRIVING_8822C 0x10250006 +#define REG_SDIO_MONITOR_8822C 0x10250008 +#define REG_SDIO_MONITOR_2_8822C 0x1025000C +#define REG_SDIO_HIMR_8822C 0x10250014 +#define REG_SDIO_HISR_8822C 0x10250018 +#define REG_SDIO_RX_REQ_LEN_8822C 0x1025001C +#define REG_SDIO_FREE_TXPG_SEQ_V1_8822C 0x1025001F +#define REG_SDIO_FREE_TXPG_8822C 0x10250020 +#define REG_SDIO_FREE_TXPG2_8822C 0x10250024 +#define REG_SDIO_OQT_FREE_TXPG_V1_8822C 0x10250028 +#define REG_SDIO_TXPKT_EMPTY_8822C 0x1025002C +#define REG_SDIO_HTSFR_INFO_8822C 0x10250030 +#define REG_SDIO_HCPWM1_V2_8822C 0x10250038 +#define REG_SDIO_HCPWM2_V2_8822C 0x1025003A +#define REG_SDIO_INDIRECT_REG_CFG_8822C 0x10250040 +#define REG_SDIO_INDIRECT_REG_DATA_8822C 0x10250044 +#define REG_SDIO_H2C_8822C 0x10250060 +#define REG_SDIO_C2H_8822C 0x10250064 +#define REG_SDIO_HRPWM1_8822C 0x10250080 +#define REG_SDIO_HRPWM2_8822C 0x10250082 +#define REG_SDIO_HPS_CLKR_8822C 0x10250084 +#define REG_SDIO_BUS_CTRL_8822C 0x10250085 +#define REG_SDIO_HSUS_CTRL_8822C 0x10250086 +#define REG_SDIO_RESPONSE_TIMER_8822C 0x10250088 +#define REG_SDIO_CMD_CRC_8822C 0x1025008A +#define REG_SDIO_HSISR_8822C 0x10250090 +#define REG_SDIO_HSIMR_8822C 0x10250091 +#define REG_SDIO_DIOERR_RPT_8822C 0x102500C0 +#define REG_SDIO_CMD_ERRCNT_8822C 0x102500C2 +#define REG_SDIO_DATA_ERRCNT_8822C 0x102500C3 +#define REG_SDIO_CMD_ERR_CONTENT_8822C 0x102500C4 +#define REG_SDIO_CRC_ERR_IDX_8822C 0x102500C9 +#define REG_SDIO_DATA_CRC_8822C 0x102500CA +#define REG_SDIO_TRANS_FIFO_STATUS_8822C 0x102500CC + +#endif diff --git a/hal/halmac/halmac_state_machine.h b/hal/halmac/halmac_state_machine.h new file mode 100644 index 0000000..d6cce79 --- /dev/null +++ b/hal/halmac/halmac_state_machine.h @@ -0,0 +1,157 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_STATE_MACHINE_H_ +#define _HALMAC_STATE_MACHINE_H_ + +enum halmac_dlfw_state { + HALMAC_DLFW_NONE = 0, + HALMAC_DLFW_DONE = 1, + HALMAC_GEN_INFO_SENT = 2, + + /* Data CPU firmware download framework */ + HALMAC_DLFW_INIT = 0x11, + HALMAC_DLFW_START = 0x12, + HALMAC_DLFW_CONF_READY = 0x13, + HALMAC_DLFW_CPU_READY = 0x14, + HALMAC_DLFW_MEM_READY = 0x15, + HALMAC_DLFW_SW_READY = 0x16, + HALMAC_DLFW_OFLD_READY = 0x17, + + HALMAC_DLFW_UNDEFINED = 0x7F, +}; + +enum halmac_gpio_cfg_state { + HALMAC_GPIO_CFG_STATE_IDLE = 0, + HALMAC_GPIO_CFG_STATE_BUSY = 1, + HALMAC_GPIO_CFG_STATE_UNDEFINED = 0x7F, +}; + +enum halmac_rsvd_pg_state { + HALMAC_RSVD_PG_STATE_IDLE = 0, + HALMAC_RSVD_PG_STATE_BUSY = 1, + HALMAC_RSVD_PG_STATE_UNDEFINED = 0x7F, +}; + +enum halmac_api_state { + HALMAC_API_STATE_INIT = 0, + HALMAC_API_STATE_HALT = 1, + HALMAC_API_STATE_UNDEFINED = 0x7F, +}; + +enum halmac_cmd_construct_state { + HALMAC_CMD_CNSTR_IDLE = 0, + HALMAC_CMD_CNSTR_BUSY = 1, + HALMAC_CMD_CNSTR_H2C_SENT = 2, + HALMAC_CMD_CNSTR_CNSTR = 3, + HALMAC_CMD_CNSTR_BUF_CLR = 4, + HALMAC_CMD_CNSTR_UNDEFINED = 0x7F, +}; + +enum halmac_cmd_process_status { + HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */ + HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */ + HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */ + HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */ + HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */ + HALMAC_CMD_PROCESS_UNDEFINE = 0x7F, +}; + +enum halmac_mac_power { + HALMAC_MAC_POWER_OFF = 0x0, + HALMAC_MAC_POWER_ON = 0x1, + HALMAC_MAC_POWER_UNDEFINE = 0x7F, +}; + +enum halmac_wlcpu_mode { + HALMAC_WLCPU_ACTIVE = 0x0, + HALMAC_WLCPU_ENTER_SLEEP = 0x1, + HALMAC_WLCPU_SLEEP = 0x2, + HALMAC_WLCPU_UNDEFINE = 0x7F, +}; + +struct halmac_efuse_state { + enum halmac_cmd_construct_state cmd_cnstr_state; + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_cfg_param_state { + enum halmac_cmd_construct_state cmd_cnstr_state; + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_scan_state { + enum halmac_cmd_construct_state cmd_cnstr_state; + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_update_pkt_state { + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_iqk_state { + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_pwr_tracking_state { + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_psd_state { + enum halmac_cmd_process_status proc_status; + u16 data_size; + u16 seg_size; + u8 *data; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_fw_snding_state { + enum halmac_cmd_construct_state cmd_cnstr_state; + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_state { + struct halmac_efuse_state efuse_state; + struct halmac_cfg_param_state cfg_param_state; + struct halmac_scan_state scan_state; + struct halmac_update_pkt_state update_pkt_state; + struct halmac_iqk_state iqk_state; + struct halmac_pwr_tracking_state pwr_trk_state; + struct halmac_psd_state psd_state; + struct halmac_fw_snding_state fw_snding_state; + enum halmac_api_state api_state; + enum halmac_mac_power mac_pwr; + enum halmac_dlfw_state dlfw_state; + enum halmac_wlcpu_mode wlcpu_mode; + enum halmac_gpio_cfg_state gpio_cfg_state; + enum halmac_rsvd_pg_state rsvd_pg_state; +}; + +#endif diff --git a/hal/halmac/halmac_tx_desc_buffer_ap.h b/hal/halmac/halmac_tx_desc_buffer_ap.h new file mode 100644 index 0000000..353571a --- /dev/null +++ b/hal/halmac/halmac_tx_desc_buffer_ap.h @@ -0,0 +1,1078 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_TX_DESC_BUFFER_AP_H_ +#define _HALMAC_TX_DESC_BUFFER_AP_H_ +#if (HALMAC_8814B_SUPPORT) + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_BUFFER_RDG_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 31) +#define SET_TX_DESC_BUFFER_RDG_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31) +#define GET_TX_DESC_BUFFER_RDG_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 31) +#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 30) +#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30) +#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 30) +#define SET_TX_DESC_BUFFER_AGG_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 29) +#define SET_TX_DESC_BUFFER_AGG_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29) +#define GET_TX_DESC_BUFFER_AGG_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 29) +#define SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1f, 24) +#define SET_TX_DESC_BUFFER_PKT_OFFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1f, 24) +#define GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1f, \ + 24) +#define SET_TX_DESC_BUFFER_OFFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0xff, 16) +#define SET_TX_DESC_BUFFER_OFFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0xff, 16) +#define GET_TX_DESC_BUFFER_OFFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0xff, \ + 16) +#define SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0xffff, 0) +#define SET_TX_DESC_BUFFER_TXPKTSIZE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0xffff, 0) +#define GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, \ + 0xffff, 0) + +/*TXDESC_WORD1*/ + +#define SET_TX_DESC_BUFFER_USERATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 31) +#define SET_TX_DESC_BUFFER_USERATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 31) +#define GET_TX_DESC_BUFFER_USERATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 31) +#define SET_TX_DESC_BUFFER_AMSDU(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 30) +#define SET_TX_DESC_BUFFER_AMSDU_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30) +#define GET_TX_DESC_BUFFER_AMSDU(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 30) +#define SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 29) +#define SET_TX_DESC_BUFFER_EN_HWSEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29) +#define GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 29) +#define SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 28) +#define SET_TX_DESC_BUFFER_EN_HWEXSEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 28) +#define GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 28) +#define SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0xfff, 16) +#define SET_TX_DESC_BUFFER_SW_SEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0xfff, 16) +#define GET_TX_DESC_BUFFER_SW_SEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, \ + 0xfff, 16) +#define SET_TX_DESC_BUFFER_DROP_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x3, 14) +#define SET_TX_DESC_BUFFER_DROP_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x3, 14) +#define GET_TX_DESC_BUFFER_DROP_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x3, \ + 14) +#define SET_TX_DESC_BUFFER_MOREDATA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 13) +#define SET_TX_DESC_BUFFER_MOREDATA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13) +#define GET_TX_DESC_BUFFER_MOREDATA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 13) +#define SET_TX_DESC_BUFFER_QSEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1f, 8) +#define SET_TX_DESC_BUFFER_QSEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 8) +#define GET_TX_DESC_BUFFER_QSEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \ + 8) +#define SET_TX_DESC_BUFFER_MACID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0xff, 0) +#define SET_TX_DESC_BUFFER_MACID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0xff, 0) +#define GET_TX_DESC_BUFFER_MACID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0xff, \ + 0) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_BUFFER_CHK_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 31) +#define SET_TX_DESC_BUFFER_CHK_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31) +#define GET_TX_DESC_BUFFER_CHK_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 31) +#define SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 30) +#define SET_TX_DESC_BUFFER_DISQSELSEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 30) +#define GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 30) +#define SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x3, 28) +#define SET_TX_DESC_BUFFER_SND_PKT_SEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3, 28) +#define GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3, \ + 28) +#define SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 27) +#define SET_TX_DESC_BUFFER_DMA_PRI_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 27) +#define GET_TX_DESC_BUFFER_DMA_PRI(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 27) +#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x7, 24) +#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 24) +#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7, \ + 24) +#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0xff, 16) +#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xff, 16) +#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xff, \ + 16) +#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0xffff, 0) +#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xffff, 0) +#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, \ + 0xffff, 0) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x7fff, 16) +#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7fff, 16) +#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, \ + 0x7fff, 16) +#define SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1f, 11) +#define SET_TX_DESC_BUFFER_CHANNEL_DMA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 11) +#define GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \ + 11) +#define SET_TX_DESC_BUFFER_MBSSID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0xf, 7) +#define SET_TX_DESC_BUFFER_MBSSID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0xf, 7) +#define GET_TX_DESC_BUFFER_MBSSID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0xf, 7) +#define SET_TX_DESC_BUFFER_BK(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 6) +#define SET_TX_DESC_BUFFER_BK_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 6) +#define GET_TX_DESC_BUFFER_BK(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 6) +#define SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1f, 0) +#define SET_TX_DESC_BUFFER_WHEADER_LEN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0) +#define GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \ + 0) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1, 26) +#define SET_TX_DESC_BUFFER_TRY_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 26) +#define GET_TX_DESC_BUFFER_TRY_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \ + 26) +#define SET_TX_DESC_BUFFER_DATA_BW(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x3, 24) +#define SET_TX_DESC_BUFFER_DATA_BW_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3, 24) +#define GET_TX_DESC_BUFFER_DATA_BW(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3, \ + 24) +#define SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1, 23) +#define SET_TX_DESC_BUFFER_DATA_SHORT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 23) +#define GET_TX_DESC_BUFFER_DATA_SHORT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \ + 23) +#define SET_TX_DESC_BUFFER_DATARATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x7f, 16) +#define SET_TX_DESC_BUFFER_DATARATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7f, 16) +#define GET_TX_DESC_BUFFER_DATARATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x7f, \ + 16) +#define SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1, 11) +#define SET_TX_DESC_BUFFER_TXBF_PATH_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 11) +#define GET_TX_DESC_BUFFER_TXBF_PATH(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \ + 11) +#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x7ff, 0) +#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7ff, 0) +#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, \ + 0x7ff, 0) + +/*TXDESC_WORD5*/ + +#define SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 31) +#define SET_TX_DESC_BUFFER_RTY_LMT_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 31) +#define GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 31) +#define SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 30) +#define SET_TX_DESC_BUFFER_HW_RTS_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 30) +#define GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 30) +#define SET_TX_DESC_BUFFER_RTS_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 29) +#define SET_TX_DESC_BUFFER_RTS_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 29) +#define GET_TX_DESC_BUFFER_RTS_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 29) +#define SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 28) +#define SET_TX_DESC_BUFFER_CTS2SELF_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 28) +#define GET_TX_DESC_BUFFER_CTS2SELF(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 28) +#define SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0xf, 24) +#define SET_TX_DESC_BUFFER_TAILPAGE_H_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 24) +#define GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, \ + 24) +#define SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0xff, 16) +#define SET_TX_DESC_BUFFER_TAILPAGE_L_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xff, 16) +#define GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xff, \ + 16) +#define SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 15) +#define SET_TX_DESC_BUFFER_NAVUSEHDR_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 15) +#define GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 15) +#define SET_TX_DESC_BUFFER_BMC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 14) +#define SET_TX_DESC_BUFFER_BMC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 14) +#define GET_TX_DESC_BUFFER_BMC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 14) +#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3f, 8) +#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3f, 8) +#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3f, \ + 8) +#define SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 7) +#define SET_TX_DESC_BUFFER_HW_AES_IV_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 7) +#define GET_TX_DESC_BUFFER_HW_AES_IV(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 7) +#define SET_TX_DESC_BUFFER_BT_NULL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 3) +#define SET_TX_DESC_BUFFER_BT_NULL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 3) +#define GET_TX_DESC_BUFFER_BT_NULL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 3) +#define SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 2) +#define SET_TX_DESC_BUFFER_EN_DESC_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 2) +#define GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 2) +#define SET_TX_DESC_BUFFER_SECTYPE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3, 0) +#define SET_TX_DESC_BUFFER_SECTYPE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 0) +#define GET_TX_DESC_BUFFER_SECTYPE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 0) + +/*TXDESC_WORD6*/ + +#define SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x7, 29) +#define SET_TX_DESC_BUFFER_MULTIPLE_PORT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7, 29) +#define GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7, \ + 29) +#define SET_TX_DESC_BUFFER_POLLUTED(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1, 28) +#define SET_TX_DESC_BUFFER_POLLUTED_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 28) +#define GET_TX_DESC_BUFFER_POLLUTED(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \ + 28) +#define SET_TX_DESC_BUFFER_NULL_1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1, 27) +#define SET_TX_DESC_BUFFER_NULL_1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 27) +#define GET_TX_DESC_BUFFER_NULL_1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \ + 27) +#define SET_TX_DESC_BUFFER_NULL_0(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1, 26) +#define SET_TX_DESC_BUFFER_NULL_0_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 26) +#define GET_TX_DESC_BUFFER_NULL_0(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \ + 26) +#define SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1, 25) +#define SET_TX_DESC_BUFFER_TRI_FRAME_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 25) +#define GET_TX_DESC_BUFFER_TRI_FRAME(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \ + 25) +#define SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1, 24) +#define SET_TX_DESC_BUFFER_SPE_RPT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 24) +#define GET_TX_DESC_BUFFER_SPE_RPT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \ + 24) +#define SET_TX_DESC_BUFFER_FTM_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1, 23) +#define SET_TX_DESC_BUFFER_FTM_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 23) +#define GET_TX_DESC_BUFFER_FTM_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \ + 23) +#define SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x7f, 16) +#define SET_TX_DESC_BUFFER_MU_DATARATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7f, 16) +#define GET_TX_DESC_BUFFER_MU_DATARATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7f, \ + 16) +#define SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 14) +#define SET_TX_DESC_BUFFER_CCA_RTS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 14) +#define GET_TX_DESC_BUFFER_CCA_RTS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 14) +#define SET_TX_DESC_BUFFER_NDPA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 12) +#define SET_TX_DESC_BUFFER_NDPA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 12) +#define GET_TX_DESC_BUFFER_NDPA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 12) +#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 9) +#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 9) +#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, 9) +#define SET_TX_DESC_BUFFER_P_AID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1ff, 0) +#define SET_TX_DESC_BUFFER_P_AID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1ff, 0) +#define GET_TX_DESC_BUFFER_P_AID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, \ + 0x1ff, 0) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xfff, 16) +#define SET_TX_DESC_BUFFER_SW_DEFINE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xfff, 16) +#define GET_TX_DESC_BUFFER_SW_DEFINE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \ + 0xfff, 16) +#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0x1, 9) +#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 9) +#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1, 9) +#define SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xf, 5) +#define SET_TX_DESC_BUFFER_CTRL_CNT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xf, 5) +#define GET_TX_DESC_BUFFER_CTRL_CNT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xf, 5) +#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0x1f, 0) +#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1f, 0) +#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1f, \ + 0) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3, 30) +#define SET_TX_DESC_BUFFER_PATH_MAPA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 30) +#define GET_TX_DESC_BUFFER_PATH_MAPA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \ + 30) +#define SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3, 28) +#define SET_TX_DESC_BUFFER_PATH_MAPB_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 28) +#define GET_TX_DESC_BUFFER_PATH_MAPB(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \ + 28) +#define SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3, 26) +#define SET_TX_DESC_BUFFER_PATH_MAPC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 26) +#define GET_TX_DESC_BUFFER_PATH_MAPC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \ + 26) +#define SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3, 24) +#define SET_TX_DESC_BUFFER_PATH_MAPD_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 24) +#define GET_TX_DESC_BUFFER_PATH_MAPD(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \ + 24) +#define SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xf, 20) +#define SET_TX_DESC_BUFFER_ANTSEL_A_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 20) +#define GET_TX_DESC_BUFFER_ANTSEL_A(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, \ + 20) +#define SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xf, 16) +#define SET_TX_DESC_BUFFER_ANTSEL_B_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 16) +#define GET_TX_DESC_BUFFER_ANTSEL_B(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, \ + 16) +#define SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xf, 12) +#define SET_TX_DESC_BUFFER_ANTSEL_C_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 12) +#define GET_TX_DESC_BUFFER_ANTSEL_C(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, \ + 12) +#define SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xf, 8) +#define SET_TX_DESC_BUFFER_ANTSEL_D_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 8) +#define GET_TX_DESC_BUFFER_ANTSEL_D(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, 8) +#define SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xf, 4) +#define SET_TX_DESC_BUFFER_NTX_PATH_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 4) +#define GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, 4) +#define SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 3) +#define SET_TX_DESC_BUFFER_ANTLSEL_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 3) +#define GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, 3) +#define SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x7, 0) +#define SET_TX_DESC_BUFFER_AMPDU_DENSITY_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x7, 0) +#define GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x7, 0) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x3, 30) +#define SET_TX_DESC_BUFFER_VCS_STBC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x3, 30) +#define GET_TX_DESC_BUFFER_VCS_STBC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x3, \ + 30) +#define SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x3, 28) +#define SET_TX_DESC_BUFFER_DATA_STBC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x3, 28) +#define GET_TX_DESC_BUFFER_DATA_STBC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x3, \ + 28) +#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0xf, 24) +#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 24) +#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf, \ + 24) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 23) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 23) +#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \ + 23) +#define SET_TX_DESC_BUFFER_MHR_CP(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 22) +#define SET_TX_DESC_BUFFER_MHR_CP_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 22) +#define GET_TX_DESC_BUFFER_MHR_CP(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \ + 22) +#define SET_TX_DESC_BUFFER_SMH_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 21) +#define SET_TX_DESC_BUFFER_SMH_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 21) +#define GET_TX_DESC_BUFFER_SMH_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \ + 21) +#define SET_TX_DESC_BUFFER_RTSRATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1f, 16) +#define SET_TX_DESC_BUFFER_RTSRATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1f, 16) +#define GET_TX_DESC_BUFFER_RTSRATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1f, \ + 16) +#define SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0xff, 8) +#define SET_TX_DESC_BUFFER_SMH_CAM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 8) +#define GET_TX_DESC_BUFFER_SMH_CAM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \ + 8) +#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 7) +#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 7) +#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 7) +#define SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 6) +#define SET_TX_DESC_BUFFER_ARFR_HT_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 6) +#define GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 6) +#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 5) +#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 5) +#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 5) +#define SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 4) +#define SET_TX_DESC_BUFFER_ARFR_CCK_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 4) +#define GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 4) +#define SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 3) +#define SET_TX_DESC_BUFFER_RTS_SHORT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 3) +#define GET_TX_DESC_BUFFER_RTS_SHORT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 3) +#define SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 2) +#define SET_TX_DESC_BUFFER_DISDATAFB_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 2) +#define GET_TX_DESC_BUFFER_DISDATAFB(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 2) +#define SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 1) +#define SET_TX_DESC_BUFFER_DISRTSFB_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 1) +#define GET_TX_DESC_BUFFER_DISRTSFB(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 1) +#define SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 0) +#define SET_TX_DESC_BUFFER_EXT_EDCA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 0) +#define GET_TX_DESC_BUFFER_EXT_EDCA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 0) + +/*TXDESC_WORD10*/ + +#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0xff, 24) +#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 24) +#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \ + 0xff, 24) +#define SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 23) +#define SET_TX_DESC_BUFFER_SPECIAL_CW_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 23) +#define GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 23) +#define SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 22) +#define SET_TX_DESC_BUFFER_RDG_NAV_EXT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 22) +#define GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 22) +#define SET_TX_DESC_BUFFER_RAW(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 21) +#define SET_TX_DESC_BUFFER_RAW_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 21) +#define GET_TX_DESC_BUFFER_RAW(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 21) +#define SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1f, 16) +#define SET_TX_DESC_BUFFER_MAX_AGG_NUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1f, 16) +#define GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \ + 0x1f, 16) +#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0xff, 8) +#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 8) +#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \ + 0xff, 8) +#define SET_TX_DESC_BUFFER_GF(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 7) +#define SET_TX_DESC_BUFFER_GF_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 7) +#define GET_TX_DESC_BUFFER_GF(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 7) +#define SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 6) +#define SET_TX_DESC_BUFFER_MOREFRAG_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 6) +#define GET_TX_DESC_BUFFER_MOREFRAG(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 6) +#define SET_TX_DESC_BUFFER_NOACM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 5) +#define SET_TX_DESC_BUFFER_NOACM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 5) +#define GET_TX_DESC_BUFFER_NOACM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 5) +#define SET_TX_DESC_BUFFER_HTC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 4) +#define SET_TX_DESC_BUFFER_HTC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 4) +#define GET_TX_DESC_BUFFER_HTC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 4) +#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 3) +#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 3) +#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 3) +#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 2) +#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 2) +#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 2) +#define SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x3, 0) +#define SET_TX_DESC_BUFFER_HW_SSN_SEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3, 0) +#define GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x3, \ + 0) + +/*TXDESC_WORD11*/ + +#define SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0xff, 24) +#define SET_TX_DESC_BUFFER_ADDR_CAM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0xff, 24) +#define GET_TX_DESC_BUFFER_ADDR_CAM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, \ + 0xff, 24) +#define SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0xff, 16) +#define SET_TX_DESC_BUFFER_SND_TARGET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0xff, 16) +#define GET_TX_DESC_BUFFER_SND_TARGET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, \ + 0xff, 16) +#define SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0x1, 15) +#define SET_TX_DESC_BUFFER_DATA_LDPC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0x1, 15) +#define GET_TX_DESC_BUFFER_DATA_LDPC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0x1, \ + 15) +#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0x1, 14) +#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0x1, 14) +#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0x1, \ + 14) +#define SET_TX_DESC_BUFFER_G_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0x3f, 8) +#define SET_TX_DESC_BUFFER_G_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0x3f, 8) +#define GET_TX_DESC_BUFFER_G_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, \ + 0x3f, 8) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0xf, 4) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0xf, 4) +#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0xf, \ + 4) +#define SET_TX_DESC_BUFFER_DATA_SC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0xf, 0) +#define SET_TX_DESC_BUFFER_DATA_SC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0xf, 0) +#define GET_TX_DESC_BUFFER_DATA_SC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0xf, \ + 0) + +/*TXDESC_WORD12*/ + +#define SET_TX_DESC_BUFFER_LEN1_L(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12, \ + value, 0x7f, 17) +#define SET_TX_DESC_BUFFER_LEN1_L_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword12, value, 0x7f, 17) +#define GET_TX_DESC_BUFFER_LEN1_L(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12, \ + 0x7f, 17) +#define SET_TX_DESC_BUFFER_LEN0(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12, \ + value, 0x1fff, 4) +#define SET_TX_DESC_BUFFER_LEN0_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword12, value, 0x1fff, 4) +#define GET_TX_DESC_BUFFER_LEN0(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12, \ + 0x1fff, 4) +#define SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12, \ + value, 0xf, 0) +#define SET_TX_DESC_BUFFER_PKT_NUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword12, value, 0xf, 0) +#define GET_TX_DESC_BUFFER_PKT_NUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12, 0xf, \ + 0) + +/*TXDESC_WORD13*/ + +#define SET_TX_DESC_BUFFER_LEN3(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13, \ + value, 0x1fff, 19) +#define SET_TX_DESC_BUFFER_LEN3_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword13, value, 0x1fff, 19) +#define GET_TX_DESC_BUFFER_LEN3(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13, \ + 0x1fff, 19) +#define SET_TX_DESC_BUFFER_LEN2(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13, \ + value, 0x1fff, 6) +#define SET_TX_DESC_BUFFER_LEN2_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword13, value, 0x1fff, 6) +#define GET_TX_DESC_BUFFER_LEN2(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13, \ + 0x1fff, 6) +#define SET_TX_DESC_BUFFER_LEN1_H(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13, \ + value, 0x3f, 0) +#define SET_TX_DESC_BUFFER_LEN1_H_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword13, value, 0x3f, 0) +#define GET_TX_DESC_BUFFER_LEN1_H(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13, \ + 0x3f, 0) + +#endif + +#endif diff --git a/hal/halmac/halmac_tx_desc_buffer_chip.h b/hal/halmac/halmac_tx_desc_buffer_chip.h new file mode 100644 index 0000000..a3e80ca --- /dev/null +++ b/hal/halmac/halmac_tx_desc_buffer_chip.h @@ -0,0 +1,509 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_TX_DESC_BUFFER_CHIP_H_ +#define _HALMAC_TX_DESC_BUFFER_CHIP_H_ +#if (HALMAC_8814B_SUPPORT) + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_BUFFER_RDG_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RDG_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_RDG_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RDG_EN(txdesc) +#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_8814B(txdesc) \ + GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_BUFFER_AGG_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_AGG_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_AGG_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_AGG_EN(txdesc) +#define SET_TX_DESC_BUFFER_PKT_OFFSET_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_BUFFER_PKT_OFFSET_8814B(txdesc) \ + GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc) +#define SET_TX_DESC_BUFFER_OFFSET_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_OFFSET(txdesc, value) +#define GET_TX_DESC_BUFFER_OFFSET_8814B(txdesc) \ + GET_TX_DESC_BUFFER_OFFSET(txdesc) +#define SET_TX_DESC_BUFFER_TXPKTSIZE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_BUFFER_TXPKTSIZE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc) + +/*TXDESC_WORD1*/ + +#define SET_TX_DESC_BUFFER_USERATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_USERATE(txdesc, value) +#define GET_TX_DESC_BUFFER_USERATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_USERATE(txdesc) +#define SET_TX_DESC_BUFFER_AMSDU_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_AMSDU(txdesc, value) +#define GET_TX_DESC_BUFFER_AMSDU_8814B(txdesc) GET_TX_DESC_BUFFER_AMSDU(txdesc) +#define SET_TX_DESC_BUFFER_EN_HWSEQ_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_BUFFER_EN_HWSEQ_8814B(txdesc) \ + GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc) +#define SET_TX_DESC_BUFFER_EN_HWEXSEQ_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_BUFFER_EN_HWEXSEQ_8814B(txdesc) \ + GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_BUFFER_SW_SEQ_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value) +#define GET_TX_DESC_BUFFER_SW_SEQ_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SW_SEQ(txdesc) +#define SET_TX_DESC_BUFFER_DROP_ID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DROP_ID(txdesc, value) +#define GET_TX_DESC_BUFFER_DROP_ID_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DROP_ID(txdesc) +#define SET_TX_DESC_BUFFER_MOREDATA_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MOREDATA(txdesc, value) +#define GET_TX_DESC_BUFFER_MOREDATA_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MOREDATA(txdesc) +#define SET_TX_DESC_BUFFER_QSEL_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_QSEL(txdesc, value) +#define GET_TX_DESC_BUFFER_QSEL_8814B(txdesc) GET_TX_DESC_BUFFER_QSEL(txdesc) +#define SET_TX_DESC_BUFFER_MACID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MACID(txdesc, value) +#define GET_TX_DESC_BUFFER_MACID_8814B(txdesc) GET_TX_DESC_BUFFER_MACID(txdesc) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_BUFFER_CHK_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_CHK_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_CHK_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_CHK_EN(txdesc) +#define SET_TX_DESC_BUFFER_DISQSELSEQ_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_BUFFER_DISQSELSEQ_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc) +#define SET_TX_DESC_BUFFER_SND_PKT_SEL_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value) +#define GET_TX_DESC_BUFFER_SND_PKT_SEL_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc) +#define SET_TX_DESC_BUFFER_DMA_PRI_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value) +#define GET_TX_DESC_BUFFER_DMA_PRI_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DMA_PRI(txdesc) +#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value) +#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc) +#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value) +#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc) +#define SET_TX_DESC_BUFFER_CHANNEL_DMA_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value) +#define GET_TX_DESC_BUFFER_CHANNEL_DMA_8814B(txdesc) \ + GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc) +#define SET_TX_DESC_BUFFER_MBSSID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MBSSID(txdesc, value) +#define GET_TX_DESC_BUFFER_MBSSID_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MBSSID(txdesc) +#define SET_TX_DESC_BUFFER_BK_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_BK(txdesc, value) +#define GET_TX_DESC_BUFFER_BK_8814B(txdesc) GET_TX_DESC_BUFFER_BK(txdesc) +#define SET_TX_DESC_BUFFER_WHEADER_LEN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_BUFFER_WHEADER_LEN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_BUFFER_TRY_RATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value) +#define GET_TX_DESC_BUFFER_TRY_RATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TRY_RATE(txdesc) +#define SET_TX_DESC_BUFFER_DATA_BW_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATA_BW(txdesc, value) +#define GET_TX_DESC_BUFFER_DATA_BW_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATA_BW(txdesc) +#define SET_TX_DESC_BUFFER_DATA_SHORT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_BUFFER_DATA_SHORT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATA_SHORT(txdesc) +#define SET_TX_DESC_BUFFER_DATARATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATARATE(txdesc, value) +#define GET_TX_DESC_BUFFER_DATARATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATARATE(txdesc) +#define SET_TX_DESC_BUFFER_TXBF_PATH_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_BUFFER_TXBF_PATH_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TXBF_PATH(txdesc) +#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_8814B(txdesc) \ + GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc) + +/*TXDESC_WORD5*/ + +#define SET_TX_DESC_BUFFER_RTY_LMT_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_RTY_LMT_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_BUFFER_HW_RTS_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_HW_RTS_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc) +#define SET_TX_DESC_BUFFER_RTS_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RTS_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_RTS_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RTS_EN(txdesc) +#define SET_TX_DESC_BUFFER_CTS2SELF_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value) +#define GET_TX_DESC_BUFFER_CTS2SELF_8814B(txdesc) \ + GET_TX_DESC_BUFFER_CTS2SELF(txdesc) +#define SET_TX_DESC_BUFFER_TAILPAGE_H_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_BUFFER_TAILPAGE_H_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc) +#define SET_TX_DESC_BUFFER_TAILPAGE_L_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_BUFFER_TAILPAGE_L_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc) +#define SET_TX_DESC_BUFFER_NAVUSEHDR_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_BUFFER_NAVUSEHDR_8814B(txdesc) \ + GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc) +#define SET_TX_DESC_BUFFER_BMC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_BMC(txdesc, value) +#define GET_TX_DESC_BUFFER_BMC_8814B(txdesc) GET_TX_DESC_BUFFER_BMC(txdesc) +#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_BUFFER_HW_AES_IV_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_BUFFER_HW_AES_IV_8814B(txdesc) \ + GET_TX_DESC_BUFFER_HW_AES_IV(txdesc) +#define SET_TX_DESC_BUFFER_BT_NULL_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_BT_NULL(txdesc, value) +#define GET_TX_DESC_BUFFER_BT_NULL_8814B(txdesc) \ + GET_TX_DESC_BUFFER_BT_NULL(txdesc) +#define SET_TX_DESC_BUFFER_EN_DESC_ID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_BUFFER_EN_DESC_ID_8814B(txdesc) \ + GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc) +#define SET_TX_DESC_BUFFER_SECTYPE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SECTYPE(txdesc, value) +#define GET_TX_DESC_BUFFER_SECTYPE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SECTYPE(txdesc) + +/*TXDESC_WORD6*/ + +#define SET_TX_DESC_BUFFER_MULTIPLE_PORT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_BUFFER_MULTIPLE_PORT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_BUFFER_POLLUTED_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_POLLUTED(txdesc, value) +#define GET_TX_DESC_BUFFER_POLLUTED_8814B(txdesc) \ + GET_TX_DESC_BUFFER_POLLUTED(txdesc) +#define SET_TX_DESC_BUFFER_NULL_1_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_NULL_1(txdesc, value) +#define GET_TX_DESC_BUFFER_NULL_1_8814B(txdesc) \ + GET_TX_DESC_BUFFER_NULL_1(txdesc) +#define SET_TX_DESC_BUFFER_NULL_0_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_NULL_0(txdesc, value) +#define GET_TX_DESC_BUFFER_NULL_0_8814B(txdesc) \ + GET_TX_DESC_BUFFER_NULL_0(txdesc) +#define SET_TX_DESC_BUFFER_TRI_FRAME_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_BUFFER_TRI_FRAME_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TRI_FRAME(txdesc) +#define SET_TX_DESC_BUFFER_SPE_RPT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value) +#define GET_TX_DESC_BUFFER_SPE_RPT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SPE_RPT(txdesc) +#define SET_TX_DESC_BUFFER_FTM_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_FTM_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_FTM_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_FTM_EN(txdesc) +#define SET_TX_DESC_BUFFER_MU_DATARATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value) +#define GET_TX_DESC_BUFFER_MU_DATARATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MU_DATARATE(txdesc) +#define SET_TX_DESC_BUFFER_CCA_RTS_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value) +#define GET_TX_DESC_BUFFER_CCA_RTS_8814B(txdesc) \ + GET_TX_DESC_BUFFER_CCA_RTS(txdesc) +#define SET_TX_DESC_BUFFER_NDPA_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_NDPA(txdesc, value) +#define GET_TX_DESC_BUFFER_NDPA_8814B(txdesc) GET_TX_DESC_BUFFER_NDPA(txdesc) +#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value) +#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc) +#define SET_TX_DESC_BUFFER_P_AID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_P_AID(txdesc, value) +#define GET_TX_DESC_BUFFER_P_AID_8814B(txdesc) GET_TX_DESC_BUFFER_P_AID(txdesc) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_BUFFER_SW_DEFINE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_BUFFER_SW_DEFINE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SW_DEFINE(txdesc) +#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value) +#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID_8814B(txdesc) \ + GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc) +#define SET_TX_DESC_BUFFER_CTRL_CNT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value) +#define GET_TX_DESC_BUFFER_CTRL_CNT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_CTRL_CNT(txdesc) +#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_BUFFER_PATH_MAPA_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value) +#define GET_TX_DESC_BUFFER_PATH_MAPA_8814B(txdesc) \ + GET_TX_DESC_BUFFER_PATH_MAPA(txdesc) +#define SET_TX_DESC_BUFFER_PATH_MAPB_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value) +#define GET_TX_DESC_BUFFER_PATH_MAPB_8814B(txdesc) \ + GET_TX_DESC_BUFFER_PATH_MAPB(txdesc) +#define SET_TX_DESC_BUFFER_PATH_MAPC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value) +#define GET_TX_DESC_BUFFER_PATH_MAPC_8814B(txdesc) \ + GET_TX_DESC_BUFFER_PATH_MAPC(txdesc) +#define SET_TX_DESC_BUFFER_PATH_MAPD_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value) +#define GET_TX_DESC_BUFFER_PATH_MAPD_8814B(txdesc) \ + GET_TX_DESC_BUFFER_PATH_MAPD(txdesc) +#define SET_TX_DESC_BUFFER_ANTSEL_A_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_BUFFER_ANTSEL_A_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ANTSEL_A(txdesc) +#define SET_TX_DESC_BUFFER_ANTSEL_B_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_BUFFER_ANTSEL_B_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ANTSEL_B(txdesc) +#define SET_TX_DESC_BUFFER_ANTSEL_C_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_BUFFER_ANTSEL_C_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ANTSEL_C(txdesc) +#define SET_TX_DESC_BUFFER_ANTSEL_D_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_BUFFER_ANTSEL_D_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ANTSEL_D(txdesc) +#define SET_TX_DESC_BUFFER_NTX_PATH_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_NTX_PATH_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc) +#define SET_TX_DESC_BUFFER_ANTLSEL_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_ANTLSEL_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc) +#define SET_TX_DESC_BUFFER_AMPDU_DENSITY_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_BUFFER_AMPDU_DENSITY_8814B(txdesc) \ + GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_BUFFER_VCS_STBC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value) +#define GET_TX_DESC_BUFFER_VCS_STBC_8814B(txdesc) \ + GET_TX_DESC_BUFFER_VCS_STBC(txdesc) +#define SET_TX_DESC_BUFFER_DATA_STBC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value) +#define GET_TX_DESC_BUFFER_DATA_STBC_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATA_STBC(txdesc) +#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc) +#define SET_TX_DESC_BUFFER_MHR_CP_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MHR_CP(txdesc, value) +#define GET_TX_DESC_BUFFER_MHR_CP_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MHR_CP(txdesc) +#define SET_TX_DESC_BUFFER_SMH_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SMH_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_SMH_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SMH_EN(txdesc) +#define SET_TX_DESC_BUFFER_RTSRATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RTSRATE(txdesc, value) +#define GET_TX_DESC_BUFFER_RTSRATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RTSRATE(txdesc) +#define SET_TX_DESC_BUFFER_SMH_CAM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value) +#define GET_TX_DESC_BUFFER_SMH_CAM_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SMH_CAM(txdesc) +#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value) +#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc) +#define SET_TX_DESC_BUFFER_ARFR_HT_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_ARFR_HT_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc) +#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc) +#define SET_TX_DESC_BUFFER_ARFR_CCK_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_ARFR_CCK_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc) +#define SET_TX_DESC_BUFFER_RTS_SHORT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_BUFFER_RTS_SHORT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RTS_SHORT(txdesc) +#define SET_TX_DESC_BUFFER_DISDATAFB_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value) +#define GET_TX_DESC_BUFFER_DISDATAFB_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DISDATAFB(txdesc) +#define SET_TX_DESC_BUFFER_DISRTSFB_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value) +#define GET_TX_DESC_BUFFER_DISRTSFB_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DISRTSFB(txdesc) +#define SET_TX_DESC_BUFFER_EXT_EDCA_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value) +#define GET_TX_DESC_BUFFER_EXT_EDCA_8814B(txdesc) \ + GET_TX_DESC_BUFFER_EXT_EDCA(txdesc) + +/*TXDESC_WORD10*/ + +#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME_8814B(txdesc) \ + GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_BUFFER_SPECIAL_CW_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value) +#define GET_TX_DESC_BUFFER_SPECIAL_CW_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc) +#define SET_TX_DESC_BUFFER_RDG_NAV_EXT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value) +#define GET_TX_DESC_BUFFER_RDG_NAV_EXT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc) +#define SET_TX_DESC_BUFFER_RAW_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RAW(txdesc, value) +#define GET_TX_DESC_BUFFER_RAW_8814B(txdesc) GET_TX_DESC_BUFFER_RAW(txdesc) +#define SET_TX_DESC_BUFFER_MAX_AGG_NUM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_BUFFER_MAX_AGG_NUM_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_BUFFER_GF_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_GF(txdesc, value) +#define GET_TX_DESC_BUFFER_GF_8814B(txdesc) GET_TX_DESC_BUFFER_GF(txdesc) +#define SET_TX_DESC_BUFFER_MOREFRAG_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value) +#define GET_TX_DESC_BUFFER_MOREFRAG_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MOREFRAG(txdesc) +#define SET_TX_DESC_BUFFER_NOACM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_NOACM(txdesc, value) +#define GET_TX_DESC_BUFFER_NOACM_8814B(txdesc) GET_TX_DESC_BUFFER_NOACM(txdesc) +#define SET_TX_DESC_BUFFER_HTC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_HTC(txdesc, value) +#define GET_TX_DESC_BUFFER_HTC_8814B(txdesc) GET_TX_DESC_BUFFER_HTC(txdesc) +#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value) +#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc) +#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_BUFFER_HW_SSN_SEL_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_BUFFER_HW_SSN_SEL_8814B(txdesc) \ + GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc) + +/*TXDESC_WORD11*/ + +#define SET_TX_DESC_BUFFER_ADDR_CAM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value) +#define GET_TX_DESC_BUFFER_ADDR_CAM_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ADDR_CAM(txdesc) +#define SET_TX_DESC_BUFFER_SND_TARGET_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value) +#define GET_TX_DESC_BUFFER_SND_TARGET_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SND_TARGET(txdesc) +#define SET_TX_DESC_BUFFER_DATA_LDPC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_BUFFER_DATA_LDPC_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATA_LDPC(txdesc) +#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_BUFFER_G_ID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_G_ID(txdesc, value) +#define GET_TX_DESC_BUFFER_G_ID_8814B(txdesc) GET_TX_DESC_BUFFER_G_ID(txdesc) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value) +#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc) +#define SET_TX_DESC_BUFFER_DATA_SC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATA_SC(txdesc, value) +#define GET_TX_DESC_BUFFER_DATA_SC_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATA_SC(txdesc) + +/*TXDESC_WORD12*/ + +#define SET_TX_DESC_BUFFER_LEN1_L_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_LEN1_L(txdesc, value) +#define GET_TX_DESC_BUFFER_LEN1_L_8814B(txdesc) \ + GET_TX_DESC_BUFFER_LEN1_L(txdesc) +#define SET_TX_DESC_BUFFER_LEN0_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_LEN0(txdesc, value) +#define GET_TX_DESC_BUFFER_LEN0_8814B(txdesc) GET_TX_DESC_BUFFER_LEN0(txdesc) +#define SET_TX_DESC_BUFFER_PKT_NUM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value) +#define GET_TX_DESC_BUFFER_PKT_NUM_8814B(txdesc) \ + GET_TX_DESC_BUFFER_PKT_NUM(txdesc) + +/*TXDESC_WORD13*/ + +#define SET_TX_DESC_BUFFER_LEN3_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_LEN3(txdesc, value) +#define GET_TX_DESC_BUFFER_LEN3_8814B(txdesc) GET_TX_DESC_BUFFER_LEN3(txdesc) +#define SET_TX_DESC_BUFFER_LEN2_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_LEN2(txdesc, value) +#define GET_TX_DESC_BUFFER_LEN2_8814B(txdesc) GET_TX_DESC_BUFFER_LEN2(txdesc) +#define SET_TX_DESC_BUFFER_LEN1_H_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_LEN1_H(txdesc, value) +#define GET_TX_DESC_BUFFER_LEN1_H_8814B(txdesc) \ + GET_TX_DESC_BUFFER_LEN1_H(txdesc) + +#endif + +#endif diff --git a/hal/halmac/halmac_tx_desc_buffer_nic.h b/hal/halmac/halmac_tx_desc_buffer_nic.h new file mode 100644 index 0000000..6274102 --- /dev/null +++ b/hal/halmac/halmac_tx_desc_buffer_nic.h @@ -0,0 +1,491 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_TX_DESC_BUFFER_NIC_H_ +#define _HALMAC_TX_DESC_BUFFER_NIC_H_ +#if (HALMAC_8814B_SUPPORT) + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_BUFFER_RDG_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value) +#define GET_TX_DESC_BUFFER_RDG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1) +#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value) +#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1) +#define SET_TX_DESC_BUFFER_AGG_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value) +#define GET_TX_DESC_BUFFER_AGG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1) +#define SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 5, value) +#define GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 5) +#define SET_TX_DESC_BUFFER_OFFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value) +#define GET_TX_DESC_BUFFER_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 16, 8) +#define SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 0, 16, value) +#define GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x00, 0, 16) + +/*TXDESC_WORD1*/ + +#define SET_TX_DESC_BUFFER_USERATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 31, 1, value) +#define GET_TX_DESC_BUFFER_USERATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x04, 31, 1) +#define SET_TX_DESC_BUFFER_AMSDU(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value) +#define GET_TX_DESC_BUFFER_AMSDU(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1) +#define SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value) +#define GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1) +#define SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 28, 1, value) +#define GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x04, 28, 1) +#define SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 12, value) +#define GET_TX_DESC_BUFFER_SW_SEQ(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 12) +#define SET_TX_DESC_BUFFER_DROP_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 14, 2, value) +#define GET_TX_DESC_BUFFER_DROP_ID(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x04, 14, 2) +#define SET_TX_DESC_BUFFER_MOREDATA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value) +#define GET_TX_DESC_BUFFER_MOREDATA(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1) +#define SET_TX_DESC_BUFFER_QSEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value) +#define GET_TX_DESC_BUFFER_QSEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 8, 5) +#define SET_TX_DESC_BUFFER_MACID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 8, value) +#define GET_TX_DESC_BUFFER_MACID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 8) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_BUFFER_CHK_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value) +#define GET_TX_DESC_BUFFER_CHK_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1) +#define SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value) +#define GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 30, 1) +#define SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 28, 2, value) +#define GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 28, 2) +#define SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 27, 1, value) +#define GET_TX_DESC_BUFFER_DMA_PRI(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 27, 1) +#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 3, value) +#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 3) +#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 8, value) +#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 8) +#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 16, value) +#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 16) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 15, value) +#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 15) +#define SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 5, value) +#define GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 5) +#define SET_TX_DESC_BUFFER_MBSSID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 7, 4, value) +#define GET_TX_DESC_BUFFER_MBSSID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 7, 4) +#define SET_TX_DESC_BUFFER_BK(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 1, value) +#define GET_TX_DESC_BUFFER_BK(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 1) +#define SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value) +#define GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 26, 1, value) +#define GET_TX_DESC_BUFFER_TRY_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 26, 1) +#define SET_TX_DESC_BUFFER_DATA_BW(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 24, 2, value) +#define GET_TX_DESC_BUFFER_DATA_BW(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 24, 2) +#define SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 23, 1, value) +#define GET_TX_DESC_BUFFER_DATA_SHORT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 23, 1) +#define SET_TX_DESC_BUFFER_DATARATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 16, 7, value) +#define GET_TX_DESC_BUFFER_DATARATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 16, 7) +#define SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 11, 1, value) +#define GET_TX_DESC_BUFFER_TXBF_PATH(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 11, 1) +#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 0, 11, value) +#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 0, 11) + +/*TXDESC_WORD5*/ + +#define SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 31, 1, value) +#define GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 31, 1) +#define SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value) +#define GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 30, 1) +#define SET_TX_DESC_BUFFER_RTS_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 29, 1, value) +#define GET_TX_DESC_BUFFER_RTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 29, 1) +#define SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 1, value) +#define GET_TX_DESC_BUFFER_CTS2SELF(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 1) +#define SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value) +#define GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 4) +#define SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 16, 8, value) +#define GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 16, 8) +#define SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 15, 1, value) +#define GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 15, 1) +#define SET_TX_DESC_BUFFER_BMC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 14, 1, value) +#define GET_TX_DESC_BUFFER_BMC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 14, 1) +#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 8, 6, value) +#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 8, 6) +#define SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 7, 1, value) +#define GET_TX_DESC_BUFFER_HW_AES_IV(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 7, 1) +#define SET_TX_DESC_BUFFER_BT_NULL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 3, 1, value) +#define GET_TX_DESC_BUFFER_BT_NULL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 3, 1) +#define SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 2, 1, value) +#define GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 2, 1) +#define SET_TX_DESC_BUFFER_SECTYPE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 0, 2, value) +#define GET_TX_DESC_BUFFER_SECTYPE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 0, 2) + +/*TXDESC_WORD6*/ + +#define SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 29, 3, value) +#define GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 29, 3) +#define SET_TX_DESC_BUFFER_POLLUTED(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 1, value) +#define GET_TX_DESC_BUFFER_POLLUTED(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 1) +#define SET_TX_DESC_BUFFER_NULL_1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 27, 1, value) +#define GET_TX_DESC_BUFFER_NULL_1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 27, 1) +#define SET_TX_DESC_BUFFER_NULL_0(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 1, value) +#define GET_TX_DESC_BUFFER_NULL_0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 1) +#define SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 25, 1, value) +#define GET_TX_DESC_BUFFER_TRI_FRAME(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 25, 1) +#define SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 1, value) +#define GET_TX_DESC_BUFFER_SPE_RPT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 1) +#define SET_TX_DESC_BUFFER_FTM_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 23, 1, value) +#define GET_TX_DESC_BUFFER_FTM_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 23, 1) +#define SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 7, value) +#define GET_TX_DESC_BUFFER_MU_DATARATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 7) +#define SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 14, 2, value) +#define GET_TX_DESC_BUFFER_CCA_RTS(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 14, 2) +#define SET_TX_DESC_BUFFER_NDPA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 2, value) +#define GET_TX_DESC_BUFFER_NDPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 12, 2) +#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 9, 2, value) +#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 9, 2) +#define SET_TX_DESC_BUFFER_P_AID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 9, value) +#define GET_TX_DESC_BUFFER_P_AID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 9) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 12, value) +#define GET_TX_DESC_BUFFER_SW_DEFINE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 12) +#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 9, 1, value) +#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x1C, 9, 1) +#define SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 5, 4, value) +#define GET_TX_DESC_BUFFER_CTRL_CNT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x1C, 5, 4) +#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 5, value) +#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 5) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 30, 2, value) +#define GET_TX_DESC_BUFFER_PATH_MAPA(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 30, 2) +#define SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 28, 2, value) +#define GET_TX_DESC_BUFFER_PATH_MAPB(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 28, 2) +#define SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 26, 2, value) +#define GET_TX_DESC_BUFFER_PATH_MAPC(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 26, 2) +#define SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 2, value) +#define GET_TX_DESC_BUFFER_PATH_MAPD(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 2) +#define SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 20, 4, value) +#define GET_TX_DESC_BUFFER_ANTSEL_A(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 20, 4) +#define SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 4, value) +#define GET_TX_DESC_BUFFER_ANTSEL_B(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 4) +#define SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 12, 4, value) +#define GET_TX_DESC_BUFFER_ANTSEL_C(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 12, 4) +#define SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 4, value) +#define GET_TX_DESC_BUFFER_ANTSEL_D(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 4) +#define SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 4, 4, value) +#define GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 4, 4) +#define SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 3, 1, value) +#define GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 3, 1) +#define SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 3, value) +#define GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 3) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 30, 2, value) +#define GET_TX_DESC_BUFFER_VCS_STBC(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 30, 2) +#define SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 28, 2, value) +#define GET_TX_DESC_BUFFER_DATA_STBC(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 28, 2) +#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value) +#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 23, 1, value) +#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 23, 1) +#define SET_TX_DESC_BUFFER_MHR_CP(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 22, 1, value) +#define GET_TX_DESC_BUFFER_MHR_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 22, 1) +#define SET_TX_DESC_BUFFER_SMH_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 21, 1, value) +#define GET_TX_DESC_BUFFER_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 21, 1) +#define SET_TX_DESC_BUFFER_RTSRATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 16, 5, value) +#define GET_TX_DESC_BUFFER_RTSRATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 16, 5) +#define SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 8, 8, value) +#define GET_TX_DESC_BUFFER_SMH_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 8, 8) +#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 7, 1, value) +#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 7, 1) +#define SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 6, 1, value) +#define GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 6, 1) +#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 5, 1, value) +#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 5, 1) +#define SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 4, 1, value) +#define GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 4, 1) +#define SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 3, 1, value) +#define GET_TX_DESC_BUFFER_RTS_SHORT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 3, 1) +#define SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 2, 1, value) +#define GET_TX_DESC_BUFFER_DISDATAFB(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 2, 1) +#define SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 1, 1, value) +#define GET_TX_DESC_BUFFER_DISRTSFB(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 1, 1) +#define SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 1, value) +#define GET_TX_DESC_BUFFER_EXT_EDCA(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 1) + +/*TXDESC_WORD10*/ + +#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 24, 8, value) +#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 24, 8) +#define SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 23, 1, value) +#define GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 23, 1) +#define SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 22, 1, value) +#define GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 22, 1) +#define SET_TX_DESC_BUFFER_RAW(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 21, 1, value) +#define GET_TX_DESC_BUFFER_RAW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 21, 1) +#define SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 16, 5, value) +#define GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 16, 5) +#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value) +#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8) +#define SET_TX_DESC_BUFFER_GF(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 7, 1, value) +#define GET_TX_DESC_BUFFER_GF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 7, 1) +#define SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 6, 1, value) +#define GET_TX_DESC_BUFFER_MOREFRAG(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 6, 1) +#define SET_TX_DESC_BUFFER_NOACM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 5, 1, value) +#define GET_TX_DESC_BUFFER_NOACM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 5, 1) +#define SET_TX_DESC_BUFFER_HTC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 1, value) +#define GET_TX_DESC_BUFFER_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 1) +#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 3, 1, value) +#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 3, 1) +#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 2, 1, value) +#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 2, 1) +#define SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value) +#define GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2) + +/*TXDESC_WORD11*/ + +#define SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 24, 8, value) +#define GET_TX_DESC_BUFFER_ADDR_CAM(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x2C, 24, 8) +#define SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 16, 8, value) +#define GET_TX_DESC_BUFFER_SND_TARGET(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x2C, 16, 8) +#define SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 15, 1, value) +#define GET_TX_DESC_BUFFER_DATA_LDPC(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x2C, 15, 1) +#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 14, 1, value) +#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x2C, 14, 1) +#define SET_TX_DESC_BUFFER_G_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 8, 6, value) +#define GET_TX_DESC_BUFFER_G_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x2C, 8, 6) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 4, 4, value) +#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x2C, 4, 4) +#define SET_TX_DESC_BUFFER_DATA_SC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 0, 4, value) +#define GET_TX_DESC_BUFFER_DATA_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x2C, 0, 4) + +/*TXDESC_WORD12*/ + +#define SET_TX_DESC_BUFFER_LEN1_L(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 17, 7, value) +#define GET_TX_DESC_BUFFER_LEN1_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 17, 7) +#define SET_TX_DESC_BUFFER_LEN0(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 4, 13, value) +#define GET_TX_DESC_BUFFER_LEN0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 4, 13) +#define SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 0, 4, value) +#define GET_TX_DESC_BUFFER_PKT_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 0, 4) + +/*TXDESC_WORD13*/ + +#define SET_TX_DESC_BUFFER_LEN3(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 19, 13, value) +#define GET_TX_DESC_BUFFER_LEN3(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 19, 13) +#define SET_TX_DESC_BUFFER_LEN2(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 6, 13, value) +#define GET_TX_DESC_BUFFER_LEN2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 6, 13) +#define SET_TX_DESC_BUFFER_LEN1_H(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 0, 6, value) +#define GET_TX_DESC_BUFFER_LEN1_H(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 0, 6) + +#endif + +#endif diff --git a/hal/halmac/halmac_tx_desc_ie_ap.h b/hal/halmac/halmac_tx_desc_ie_ap.h new file mode 100644 index 0000000..a6d215f --- /dev/null +++ b/hal/halmac/halmac_tx_desc_ie_ap.h @@ -0,0 +1,1005 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_TX_DESC_IE_AP_H_ +#define _HALMAC_TX_DESC_IE_AP_H_ +#if (HALMAC_8814B_SUPPORT) + +#define IE0_GET_TX_DESC_IE_END(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 31) +#define IE0_SET_TX_DESC_IE_END(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE0_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE0_GET_TX_DESC_IE_UP(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 30) +#define IE0_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE0_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE0_GET_TX_DESC_IE_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 24) +#define IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE0_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 19) +#define IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 19) +#define IE0_SET_TX_DESC_ARFR_TABLE_SEL_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 19) +#define IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 18) +#define IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 18) +#define IE0_SET_TX_DESC_ARFR_HT_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 18) +#define IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 17) +#define IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 17) +#define IE0_SET_TX_DESC_ARFR_OFDM_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 17) +#define IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 16) +#define IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 16) +#define IE0_SET_TX_DESC_ARFR_CCK_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 16) +#define IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 9) +#define IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9) +#define IE0_SET_TX_DESC_HW_RTS_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9) +#define IE0_GET_TX_DESC_RTS_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 8) +#define IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8) +#define IE0_SET_TX_DESC_RTS_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8) +#define IE0_GET_TX_DESC_CTS2SELF(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 7) +#define IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7) +#define IE0_SET_TX_DESC_CTS2SELF_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7) +#define IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 6) +#define IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6) +#define IE0_SET_TX_DESC_RTY_LMT_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6) +#define IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 5) +#define IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5) +#define IE0_SET_TX_DESC_RTS_SHORT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5) +#define IE0_GET_TX_DESC_DISDATAFB(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 4) +#define IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4) +#define IE0_SET_TX_DESC_DISDATAFB_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4) +#define IE0_GET_TX_DESC_DISRTSFB(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 3) +#define IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3) +#define IE0_SET_TX_DESC_DISRTSFB_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3) +#define IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 2) +#define IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE0_SET_TX_DESC_DATA_SHORT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE0_GET_TX_DESC_TRY_RATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 1) +#define IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE0_SET_TX_DESC_TRY_RATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE0_GET_TX_DESC_USERATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 0) +#define IE0_SET_TX_DESC_USERATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE0_SET_TX_DESC_USERATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 27) +#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27) +#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27) +#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1f, 22) +#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1f, 22) +#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1f, 22) +#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3f, 16) +#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 16) +#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 16) +#define IE0_GET_TX_DESC_DATA_BW(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 12) +#define IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12) +#define IE0_SET_TX_DESC_DATA_BW_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12) +#define IE0_GET_TX_DESC_RTSRATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 7) +#define IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 7) +#define IE0_SET_TX_DESC_RTSRATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 7) +#define IE0_GET_TX_DESC_DATARATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x7f, 0) +#define IE0_SET_TX_DESC_DATARATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0) +#define IE0_SET_TX_DESC_DATARATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0) +#define IE1_GET_TX_DESC_IE_END(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 31) +#define IE1_SET_TX_DESC_IE_END(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE1_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE1_GET_TX_DESC_IE_UP(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 30) +#define IE1_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE1_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE1_GET_TX_DESC_IE_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 24) +#define IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE1_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x7, 21) +#define IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 21) +#define IE1_SET_TX_DESC_AMPDU_DENSITY_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 21) +#define IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1f, 16) +#define IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1f, 16) +#define IE1_SET_TX_DESC_MAX_AGG_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1f, 16) +#define IE1_GET_TX_DESC_SECTYPE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x3, 14) +#define IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 14) +#define IE1_SET_TX_DESC_SECTYPE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 14) +#define IE1_GET_TX_DESC_MOREFRAG(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 13) +#define IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 13) +#define IE1_SET_TX_DESC_MOREFRAG_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 13) +#define IE1_GET_TX_DESC_NOACM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 12) +#define IE1_SET_TX_DESC_NOACM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 12) +#define IE1_SET_TX_DESC_NOACM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 12) +#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 11) +#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11) +#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11) +#define IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 10) +#define IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10) +#define IE1_SET_TX_DESC_NAVUSEHDR_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10) +#define IE1_GET_TX_DESC_HTC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 9) +#define IE1_SET_TX_DESC_HTC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9) +#define IE1_SET_TX_DESC_HTC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9) +#define IE1_GET_TX_DESC_BMC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 8) +#define IE1_SET_TX_DESC_BMC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8) +#define IE1_SET_TX_DESC_BMC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8) +#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 7) +#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7) +#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7) +#define IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 6) +#define IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6) +#define IE1_SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6) +#define IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x3, 4) +#define IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 4) +#define IE1_SET_TX_DESC_HW_SSN_SEL_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 4) +#define IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 3) +#define IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3) +#define IE1_SET_TX_DESC_DISQSELSEQ_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3) +#define IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 2) +#define IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE1_SET_TX_DESC_EN_HWSEQ_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 1) +#define IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE1_SET_TX_DESC_EN_HWEXSEQ_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 0) +#define IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE1_SET_TX_DESC_EN_DESC_ID_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xff, 24) +#define IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 24) +#define IE1_SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 24) +#define IE1_GET_TX_DESC_P_AID(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1ff, 15) +#define IE1_SET_TX_DESC_P_AID(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1ff, \ + 15) +#define IE1_SET_TX_DESC_P_AID_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1ff, \ + 15) +#define IE1_GET_TX_DESC_MOREDATA(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1, 14) +#define IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 14) +#define IE1_SET_TX_DESC_MOREDATA_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 14) +#define IE1_GET_TX_DESC_SW_SEQ(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xfff, 0) +#define IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0) +#define IE1_SET_TX_DESC_SW_SEQ_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0) +#define IE2_GET_TX_DESC_IE_END(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 31) +#define IE2_SET_TX_DESC_IE_END(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE2_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE2_GET_TX_DESC_IE_UP(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 30) +#define IE2_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE2_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE2_GET_TX_DESC_IE_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 24) +#define IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE2_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xff, 16) +#define IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xff, 16) +#define IE2_SET_TX_DESC_ADDR_CAM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xff, 16) +#define IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x7, 12) +#define IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 12) +#define IE2_SET_TX_DESC_MULTIPLE_PORT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 12) +#define IE2_GET_TX_DESC_RAW(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 11) +#define IE2_SET_TX_DESC_RAW(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11) +#define IE2_SET_TX_DESC_RAW_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11) +#define IE2_GET_TX_DESC_RDG_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 10) +#define IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10) +#define IE2_SET_TX_DESC_RDG_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10) +#define IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 7) +#define IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7) +#define IE2_SET_TX_DESC_SPECIAL_CW_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7) +#define IE2_GET_TX_DESC_POLLUTED(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 6) +#define IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6) +#define IE2_SET_TX_DESC_POLLUTED_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6) +#define IE2_GET_TX_DESC_BT_NULL(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 5) +#define IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5) +#define IE2_SET_TX_DESC_BT_NULL_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5) +#define IE2_GET_TX_DESC_NULL_1(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 4) +#define IE2_SET_TX_DESC_NULL_1(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4) +#define IE2_SET_TX_DESC_NULL_1_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4) +#define IE2_GET_TX_DESC_NULL_0(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 3) +#define IE2_SET_TX_DESC_NULL_0(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3) +#define IE2_SET_TX_DESC_NULL_0_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3) +#define IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 2) +#define IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE2_SET_TX_DESC_TRI_FRAME_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE2_GET_TX_DESC_SPE_RPT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 1) +#define IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE2_SET_TX_DESC_SPE_RPT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE2_GET_TX_DESC_FTM_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 0) +#define IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE2_SET_TX_DESC_FTM_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE2_GET_TX_DESC_MBSSID(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 27) +#define IE2_SET_TX_DESC_MBSSID(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27) +#define IE2_SET_TX_DESC_MBSSID_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27) +#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x7ff, 16) +#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7ff, \ + 16) +#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7ff, \ + 16) +#define IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1, 15) +#define IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 15) +#define IE2_SET_TX_DESC_RDG_NAV_EXT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 15) +#define IE2_GET_TX_DESC_DROP_ID(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 12) +#define IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12) +#define IE2_SET_TX_DESC_DROP_ID_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12) +#define IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xfff, 0) +#define IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0) +#define IE2_SET_TX_DESC_SW_DEFINE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0) +#define IE3_GET_TX_DESC_IE_END(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 31) +#define IE3_SET_TX_DESC_IE_END(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE3_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE3_GET_TX_DESC_IE_UP(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 30) +#define IE3_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE3_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE3_GET_TX_DESC_IE_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 24) +#define IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE3_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE3_GET_TX_DESC_DATA_SC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 20) +#define IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 20) +#define IE3_SET_TX_DESC_DATA_SC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 20) +#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 16) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 16) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 16) +#define IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 8) +#define IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 8) +#define IE3_SET_TX_DESC_CTRL_CNT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 8) +#define IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 1) +#define IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE3_SET_TX_DESC_CTRL_CNT_VALID_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 0) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE3_GET_TX_DESC_G_ID(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3f, 24) +#define IE3_SET_TX_DESC_G_ID(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 24) +#define IE3_SET_TX_DESC_G_ID_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 24) +#define IE3_GET_TX_DESC_SND_TARGET(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xff, 16) +#define IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 16) +#define IE3_SET_TX_DESC_SND_TARGET_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 16) +#define IE3_GET_TX_DESC_CCA_RTS(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 11) +#define IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 11) +#define IE3_SET_TX_DESC_CCA_RTS_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 11) +#define IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 9) +#define IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 9) +#define IE3_SET_TX_DESC_SND_PKT_SEL_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 9) +#define IE3_GET_TX_DESC_NDPA(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 7) +#define IE3_SET_TX_DESC_NDPA(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 7) +#define IE3_SET_TX_DESC_NDPA_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 7) +#define IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x7f, 0) +#define IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0) +#define IE3_SET_TX_DESC_MU_DATARATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0) +#define IE4_GET_TX_DESC_IE_END(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 31) +#define IE4_SET_TX_DESC_IE_END(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE4_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE4_GET_TX_DESC_IE_UP(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 30) +#define IE4_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE4_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE4_GET_TX_DESC_IE_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 24) +#define IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE4_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE4_GET_TX_DESC_VCS_STBC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x3, 10) +#define IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 10) +#define IE4_SET_TX_DESC_VCS_STBC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 10) +#define IE4_GET_TX_DESC_DATA_STBC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x3, 8) +#define IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 8) +#define IE4_SET_TX_DESC_DATA_STBC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 8) +#define IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 2) +#define IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE4_SET_TX_DESC_DATA_LDPC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE4_GET_TX_DESC_GF(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 1) +#define IE4_SET_TX_DESC_GF(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE4_SET_TX_DESC_GF_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 0) +#define IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE4_SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 30) +#define IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 30) +#define IE4_SET_TX_DESC_PATH_MAPA_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 30) +#define IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 28) +#define IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 28) +#define IE4_SET_TX_DESC_PATH_MAPB_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 28) +#define IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 26) +#define IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 26) +#define IE4_SET_TX_DESC_PATH_MAPC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 26) +#define IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 24) +#define IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 24) +#define IE4_SET_TX_DESC_PATH_MAPD_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 24) +#define IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 20) +#define IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 20) +#define IE4_SET_TX_DESC_ANTSEL_A_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 20) +#define IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 16) +#define IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 16) +#define IE4_SET_TX_DESC_ANTSEL_B_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 16) +#define IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 12) +#define IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 12) +#define IE4_SET_TX_DESC_ANTSEL_C_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 12) +#define IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 8) +#define IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 8) +#define IE4_SET_TX_DESC_ANTSEL_D_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 8) +#define IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 4) +#define IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 4) +#define IE4_SET_TX_DESC_NTX_PATH_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 4) +#define IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1, 3) +#define IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 3) +#define IE4_SET_TX_DESC_ANTLSEL_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 3) +#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 0) +#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 0) +#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 0) +#define IE5_GET_TX_DESC_IE_END(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 31) +#define IE5_SET_TX_DESC_IE_END(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE5_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE5_GET_TX_DESC_IE_UP(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 30) +#define IE5_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE5_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE5_GET_TX_DESC_IE_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 24) +#define IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE5_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE5_GET_TX_DESC_LEN1_L(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x7f, 17) +#define IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7f, 17) +#define IE5_SET_TX_DESC_LEN1_L_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7f, 17) +#define IE5_GET_TX_DESC_LEN0(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1fff, 4) +#define IE5_SET_TX_DESC_LEN0(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1fff, \ + 4) +#define IE5_SET_TX_DESC_LEN0_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1fff, \ + 4) +#define IE5_GET_TX_DESC_PKT_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 0) +#define IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 0) +#define IE5_SET_TX_DESC_PKT_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 0) +#define IE5_GET_TX_DESC_LEN3(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1fff, 19) +#define IE5_SET_TX_DESC_LEN3(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff, \ + 19) +#define IE5_SET_TX_DESC_LEN3_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff, \ + 19) +#define IE5_GET_TX_DESC_LEN2(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1fff, 6) +#define IE5_SET_TX_DESC_LEN2(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff, \ + 6) +#define IE5_SET_TX_DESC_LEN2_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff, \ + 6) +#define IE5_GET_TX_DESC_LEN1_H(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3f, 0) +#define IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 0) +#define IE5_SET_TX_DESC_LEN1_H_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 0) + +#endif + +#endif diff --git a/hal/halmac/halmac_tx_desc_ie_chip.h b/hal/halmac/halmac_tx_desc_ie_chip.h new file mode 100644 index 0000000..8126a0c --- /dev/null +++ b/hal/halmac/halmac_tx_desc_ie_chip.h @@ -0,0 +1,438 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_TX_DESC_IE_CHIP_H_ +#define _HALMAC_TX_DESC_IE_CHIP_H_ +#if (HALMAC_8814B_SUPPORT) + +#define IE0_GET_TX_DESC_IE_END_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_IE_END(txdesc_ie) +#define IE0_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_IE_END(txdesc_ie, value) +#define IE0_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE0_GET_TX_DESC_IE_UP(txdesc_ie) +#define IE0_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_IE_UP(txdesc_ie, value) +#define IE0_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_IE_NUM(txdesc_ie) +#define IE0_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value) +#define IE0_GET_TX_DESC_ARFR_TABLE_SEL_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie) +#define IE0_SET_TX_DESC_ARFR_TABLE_SEL_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value) +#define IE0_GET_TX_DESC_ARFR_HT_EN_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie) +#define IE0_SET_TX_DESC_ARFR_HT_EN_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value) +#define IE0_GET_TX_DESC_ARFR_OFDM_EN_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie) +#define IE0_SET_TX_DESC_ARFR_OFDM_EN_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value) +#define IE0_GET_TX_DESC_ARFR_CCK_EN_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie) +#define IE0_SET_TX_DESC_ARFR_CCK_EN_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value) +#define IE0_GET_TX_DESC_HW_RTS_EN_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie) +#define IE0_SET_TX_DESC_HW_RTS_EN_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value) +#define IE0_GET_TX_DESC_RTS_EN_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_RTS_EN(txdesc_ie) +#define IE0_SET_TX_DESC_RTS_EN_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value) +#define IE0_GET_TX_DESC_CTS2SELF_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_CTS2SELF(txdesc_ie) +#define IE0_SET_TX_DESC_CTS2SELF_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value) +#define IE0_GET_TX_DESC_RTY_LMT_EN_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie) +#define IE0_SET_TX_DESC_RTY_LMT_EN_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value) +#define IE0_GET_TX_DESC_RTS_SHORT_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie) +#define IE0_SET_TX_DESC_RTS_SHORT_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value) +#define IE0_GET_TX_DESC_DISDATAFB_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_DISDATAFB(txdesc_ie) +#define IE0_SET_TX_DESC_DISDATAFB_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value) +#define IE0_GET_TX_DESC_DISRTSFB_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_DISRTSFB(txdesc_ie) +#define IE0_SET_TX_DESC_DISRTSFB_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value) +#define IE0_GET_TX_DESC_DATA_SHORT_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie) +#define IE0_SET_TX_DESC_DATA_SHORT_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value) +#define IE0_GET_TX_DESC_TRY_RATE_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_TRY_RATE(txdesc_ie) +#define IE0_SET_TX_DESC_TRY_RATE_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value) +#define IE0_GET_TX_DESC_USERATE_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_USERATE(txdesc_ie) +#define IE0_SET_TX_DESC_USERATE_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_USERATE(txdesc_ie, value) +#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie) +#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value) +#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie) +#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value) +#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie) +#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value) +#define IE0_GET_TX_DESC_DATA_BW_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_DATA_BW(txdesc_ie) +#define IE0_SET_TX_DESC_DATA_BW_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value) +#define IE0_GET_TX_DESC_RTSRATE_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_RTSRATE(txdesc_ie) +#define IE0_SET_TX_DESC_RTSRATE_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value) +#define IE0_GET_TX_DESC_DATARATE_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_DATARATE(txdesc_ie) +#define IE0_SET_TX_DESC_DATARATE_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_DATARATE(txdesc_ie, value) +#define IE1_GET_TX_DESC_IE_END_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_IE_END(txdesc_ie) +#define IE1_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_IE_END(txdesc_ie, value) +#define IE1_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE1_GET_TX_DESC_IE_UP(txdesc_ie) +#define IE1_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_IE_UP(txdesc_ie, value) +#define IE1_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_IE_NUM(txdesc_ie) +#define IE1_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value) +#define IE1_GET_TX_DESC_AMPDU_DENSITY_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie) +#define IE1_SET_TX_DESC_AMPDU_DENSITY_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value) +#define IE1_GET_TX_DESC_MAX_AGG_NUM_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie) +#define IE1_SET_TX_DESC_MAX_AGG_NUM_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value) +#define IE1_GET_TX_DESC_SECTYPE_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_SECTYPE(txdesc_ie) +#define IE1_SET_TX_DESC_SECTYPE_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value) +#define IE1_GET_TX_DESC_MOREFRAG_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_MOREFRAG(txdesc_ie) +#define IE1_SET_TX_DESC_MOREFRAG_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value) +#define IE1_GET_TX_DESC_NOACM_8814B(txdesc_ie) IE1_GET_TX_DESC_NOACM(txdesc_ie) +#define IE1_SET_TX_DESC_NOACM_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_NOACM(txdesc_ie, value) +#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie) +#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value) +#define IE1_GET_TX_DESC_NAVUSEHDR_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie) +#define IE1_SET_TX_DESC_NAVUSEHDR_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value) +#define IE1_GET_TX_DESC_HTC_8814B(txdesc_ie) IE1_GET_TX_DESC_HTC(txdesc_ie) +#define IE1_SET_TX_DESC_HTC_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_HTC(txdesc_ie, value) +#define IE1_GET_TX_DESC_BMC_8814B(txdesc_ie) IE1_GET_TX_DESC_BMC(txdesc_ie) +#define IE1_SET_TX_DESC_BMC_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_BMC(txdesc_ie, value) +#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie) +#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value) +#define IE1_GET_TX_DESC_USE_MAX_TIME_EN_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie) +#define IE1_SET_TX_DESC_USE_MAX_TIME_EN_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value) +#define IE1_GET_TX_DESC_HW_SSN_SEL_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie) +#define IE1_SET_TX_DESC_HW_SSN_SEL_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value) +#define IE1_GET_TX_DESC_DISQSELSEQ_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie) +#define IE1_SET_TX_DESC_DISQSELSEQ_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value) +#define IE1_GET_TX_DESC_EN_HWSEQ_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie) +#define IE1_SET_TX_DESC_EN_HWSEQ_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value) +#define IE1_GET_TX_DESC_EN_HWEXSEQ_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie) +#define IE1_SET_TX_DESC_EN_HWEXSEQ_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value) +#define IE1_GET_TX_DESC_EN_DESC_ID_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie) +#define IE1_SET_TX_DESC_EN_DESC_ID_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value) +#define IE1_GET_TX_DESC_AMPDU_MAX_TIME_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie) +#define IE1_SET_TX_DESC_AMPDU_MAX_TIME_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value) +#define IE1_GET_TX_DESC_P_AID_8814B(txdesc_ie) IE1_GET_TX_DESC_P_AID(txdesc_ie) +#define IE1_SET_TX_DESC_P_AID_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_P_AID(txdesc_ie, value) +#define IE1_GET_TX_DESC_MOREDATA_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_MOREDATA(txdesc_ie) +#define IE1_SET_TX_DESC_MOREDATA_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value) +#define IE1_GET_TX_DESC_SW_SEQ_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_SW_SEQ(txdesc_ie) +#define IE1_SET_TX_DESC_SW_SEQ_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value) +#define IE2_GET_TX_DESC_IE_END_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_IE_END(txdesc_ie) +#define IE2_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_IE_END(txdesc_ie, value) +#define IE2_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE2_GET_TX_DESC_IE_UP(txdesc_ie) +#define IE2_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_IE_UP(txdesc_ie, value) +#define IE2_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_IE_NUM(txdesc_ie) +#define IE2_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value) +#define IE2_GET_TX_DESC_ADDR_CAM_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie) +#define IE2_SET_TX_DESC_ADDR_CAM_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value) +#define IE2_GET_TX_DESC_MULTIPLE_PORT_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie) +#define IE2_SET_TX_DESC_MULTIPLE_PORT_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value) +#define IE2_GET_TX_DESC_RAW_8814B(txdesc_ie) IE2_GET_TX_DESC_RAW(txdesc_ie) +#define IE2_SET_TX_DESC_RAW_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_RAW(txdesc_ie, value) +#define IE2_GET_TX_DESC_RDG_EN_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_RDG_EN(txdesc_ie) +#define IE2_SET_TX_DESC_RDG_EN_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value) +#define IE2_GET_TX_DESC_SPECIAL_CW_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie) +#define IE2_SET_TX_DESC_SPECIAL_CW_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value) +#define IE2_GET_TX_DESC_POLLUTED_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_POLLUTED(txdesc_ie) +#define IE2_SET_TX_DESC_POLLUTED_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value) +#define IE2_GET_TX_DESC_BT_NULL_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_BT_NULL(txdesc_ie) +#define IE2_SET_TX_DESC_BT_NULL_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value) +#define IE2_GET_TX_DESC_NULL_1_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_NULL_1(txdesc_ie) +#define IE2_SET_TX_DESC_NULL_1_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_NULL_1(txdesc_ie, value) +#define IE2_GET_TX_DESC_NULL_0_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_NULL_0(txdesc_ie) +#define IE2_SET_TX_DESC_NULL_0_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_NULL_0(txdesc_ie, value) +#define IE2_GET_TX_DESC_TRI_FRAME_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie) +#define IE2_SET_TX_DESC_TRI_FRAME_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value) +#define IE2_GET_TX_DESC_SPE_RPT_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_SPE_RPT(txdesc_ie) +#define IE2_SET_TX_DESC_SPE_RPT_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value) +#define IE2_GET_TX_DESC_FTM_EN_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_FTM_EN(txdesc_ie) +#define IE2_SET_TX_DESC_FTM_EN_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value) +#define IE2_GET_TX_DESC_MBSSID_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_MBSSID(txdesc_ie) +#define IE2_SET_TX_DESC_MBSSID_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_MBSSID(txdesc_ie, value) +#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie) +#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value) +#define IE2_GET_TX_DESC_RDG_NAV_EXT_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie) +#define IE2_SET_TX_DESC_RDG_NAV_EXT_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value) +#define IE2_GET_TX_DESC_DROP_ID_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_DROP_ID(txdesc_ie) +#define IE2_SET_TX_DESC_DROP_ID_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value) +#define IE2_GET_TX_DESC_SW_DEFINE_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie) +#define IE2_SET_TX_DESC_SW_DEFINE_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value) +#define IE3_GET_TX_DESC_IE_END_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_IE_END(txdesc_ie) +#define IE3_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_IE_END(txdesc_ie, value) +#define IE3_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE3_GET_TX_DESC_IE_UP(txdesc_ie) +#define IE3_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_IE_UP(txdesc_ie, value) +#define IE3_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_IE_NUM(txdesc_ie) +#define IE3_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value) +#define IE3_GET_TX_DESC_DATA_SC_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_DATA_SC(txdesc_ie) +#define IE3_SET_TX_DESC_DATA_SC_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value) +#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value) +#define IE3_GET_TX_DESC_CTRL_CNT_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie) +#define IE3_SET_TX_DESC_CTRL_CNT_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value) +#define IE3_GET_TX_DESC_CTRL_CNT_VALID_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie) +#define IE3_SET_TX_DESC_CTRL_CNT_VALID_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value) +#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value) +#define IE3_GET_TX_DESC_G_ID_8814B(txdesc_ie) IE3_GET_TX_DESC_G_ID(txdesc_ie) +#define IE3_SET_TX_DESC_G_ID_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_G_ID(txdesc_ie, value) +#define IE3_GET_TX_DESC_SND_TARGET_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_SND_TARGET(txdesc_ie) +#define IE3_SET_TX_DESC_SND_TARGET_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value) +#define IE3_GET_TX_DESC_CCA_RTS_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_CCA_RTS(txdesc_ie) +#define IE3_SET_TX_DESC_CCA_RTS_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value) +#define IE3_GET_TX_DESC_SND_PKT_SEL_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie) +#define IE3_SET_TX_DESC_SND_PKT_SEL_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value) +#define IE3_GET_TX_DESC_NDPA_8814B(txdesc_ie) IE3_GET_TX_DESC_NDPA(txdesc_ie) +#define IE3_SET_TX_DESC_NDPA_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_NDPA(txdesc_ie, value) +#define IE3_GET_TX_DESC_MU_DATARATE_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie) +#define IE3_SET_TX_DESC_MU_DATARATE_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value) +#define IE4_GET_TX_DESC_IE_END_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_IE_END(txdesc_ie) +#define IE4_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_IE_END(txdesc_ie, value) +#define IE4_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE4_GET_TX_DESC_IE_UP(txdesc_ie) +#define IE4_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_IE_UP(txdesc_ie, value) +#define IE4_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_IE_NUM(txdesc_ie) +#define IE4_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value) +#define IE4_GET_TX_DESC_VCS_STBC_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_VCS_STBC(txdesc_ie) +#define IE4_SET_TX_DESC_VCS_STBC_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value) +#define IE4_GET_TX_DESC_DATA_STBC_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_DATA_STBC(txdesc_ie) +#define IE4_SET_TX_DESC_DATA_STBC_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value) +#define IE4_GET_TX_DESC_DATA_LDPC_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie) +#define IE4_SET_TX_DESC_DATA_LDPC_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value) +#define IE4_GET_TX_DESC_GF_8814B(txdesc_ie) IE4_GET_TX_DESC_GF(txdesc_ie) +#define IE4_SET_TX_DESC_GF_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_GF(txdesc_ie, value) +#define IE4_GET_TX_DESC_LSIG_TXOP_EN_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie) +#define IE4_SET_TX_DESC_LSIG_TXOP_EN_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value) +#define IE4_GET_TX_DESC_PATH_MAPA_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie) +#define IE4_SET_TX_DESC_PATH_MAPA_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value) +#define IE4_GET_TX_DESC_PATH_MAPB_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie) +#define IE4_SET_TX_DESC_PATH_MAPB_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value) +#define IE4_GET_TX_DESC_PATH_MAPC_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie) +#define IE4_SET_TX_DESC_PATH_MAPC_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value) +#define IE4_GET_TX_DESC_PATH_MAPD_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie) +#define IE4_SET_TX_DESC_PATH_MAPD_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value) +#define IE4_GET_TX_DESC_ANTSEL_A_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie) +#define IE4_SET_TX_DESC_ANTSEL_A_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value) +#define IE4_GET_TX_DESC_ANTSEL_B_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie) +#define IE4_SET_TX_DESC_ANTSEL_B_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value) +#define IE4_GET_TX_DESC_ANTSEL_C_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie) +#define IE4_SET_TX_DESC_ANTSEL_C_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value) +#define IE4_GET_TX_DESC_ANTSEL_D_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie) +#define IE4_SET_TX_DESC_ANTSEL_D_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value) +#define IE4_GET_TX_DESC_NTX_PATH_EN_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie) +#define IE4_SET_TX_DESC_NTX_PATH_EN_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value) +#define IE4_GET_TX_DESC_ANTLSEL_EN_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie) +#define IE4_SET_TX_DESC_ANTLSEL_EN_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value) +#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie) +#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value) +#define IE5_GET_TX_DESC_IE_END_8814B(txdesc_ie) \ + IE5_GET_TX_DESC_IE_END(txdesc_ie) +#define IE5_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_IE_END(txdesc_ie, value) +#define IE5_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE5_GET_TX_DESC_IE_UP(txdesc_ie) +#define IE5_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_IE_UP(txdesc_ie, value) +#define IE5_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \ + IE5_GET_TX_DESC_IE_NUM(txdesc_ie) +#define IE5_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value) +#define IE5_GET_TX_DESC_LEN1_L_8814B(txdesc_ie) \ + IE5_GET_TX_DESC_LEN1_L(txdesc_ie) +#define IE5_SET_TX_DESC_LEN1_L_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value) +#define IE5_GET_TX_DESC_LEN0_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN0(txdesc_ie) +#define IE5_SET_TX_DESC_LEN0_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_LEN0(txdesc_ie, value) +#define IE5_GET_TX_DESC_PKT_NUM_8814B(txdesc_ie) \ + IE5_GET_TX_DESC_PKT_NUM(txdesc_ie) +#define IE5_SET_TX_DESC_PKT_NUM_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value) +#define IE5_GET_TX_DESC_LEN3_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN3(txdesc_ie) +#define IE5_SET_TX_DESC_LEN3_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_LEN3(txdesc_ie, value) +#define IE5_GET_TX_DESC_LEN2_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN2(txdesc_ie) +#define IE5_SET_TX_DESC_LEN2_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_LEN2(txdesc_ie, value) +#define IE5_GET_TX_DESC_LEN1_H_8814B(txdesc_ie) \ + IE5_GET_TX_DESC_LEN1_H(txdesc_ie) +#define IE5_SET_TX_DESC_LEN1_H_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value) + +#endif + +#endif diff --git a/hal/halmac/halmac_tx_desc_ie_nic.h b/hal/halmac/halmac_tx_desc_ie_nic.h new file mode 100644 index 0000000..c88f8fa --- /dev/null +++ b/hal/halmac/halmac_tx_desc_ie_nic.h @@ -0,0 +1,450 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_TX_DESC_IE_NIC_H_ +#define _HALMAC_TX_DESC_IE_NIC_H_ +#if (HALMAC_8814B_SUPPORT) + +#define IE0_GET_TX_DESC_IE_END(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1) +#define IE0_SET_TX_DESC_IE_END(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value) +#define IE0_GET_TX_DESC_IE_UP(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1) +#define IE0_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value) +#define IE0_GET_TX_DESC_IE_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4) +#define IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value) +#define IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 19, 1) +#define IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 19, 1, value) +#define IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 18, 1) +#define IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 18, 1, value) +#define IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 17, 1) +#define IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 17, 1, value) +#define IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 1) +#define IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 1, value) +#define IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 9, 1) +#define IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 9, 1, value) +#define IE0_GET_TX_DESC_RTS_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 1) +#define IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 1, value) +#define IE0_GET_TX_DESC_CTS2SELF(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1) +#define IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value) +#define IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1) +#define IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value) +#define IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 5, 1) +#define IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 5, 1, value) +#define IE0_GET_TX_DESC_DISDATAFB(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 1) +#define IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 1, value) +#define IE0_GET_TX_DESC_DISRTSFB(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1) +#define IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value) +#define IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1) +#define IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value) +#define IE0_GET_TX_DESC_TRY_RATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1) +#define IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value) +#define IE0_GET_TX_DESC_USERATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1) +#define IE0_SET_TX_DESC_USERATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value) +#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 27, 4) +#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 27, 4, value) +#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 22, 5) +#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 22, 5, value) +#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 6) +#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 6, value) +#define IE0_GET_TX_DESC_DATA_BW(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 2) +#define IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 2, value) +#define IE0_GET_TX_DESC_RTSRATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 7, 4) +#define IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 7, 4, value) +#define IE0_GET_TX_DESC_DATARATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 7) +#define IE0_SET_TX_DESC_DATARATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 7, value) +#define IE1_GET_TX_DESC_IE_END(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1) +#define IE1_SET_TX_DESC_IE_END(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value) +#define IE1_GET_TX_DESC_IE_UP(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1) +#define IE1_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value) +#define IE1_GET_TX_DESC_IE_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4) +#define IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value) +#define IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 21, 3) +#define IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 21, 3, value) +#define IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 5) +#define IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 5, value) +#define IE1_GET_TX_DESC_SECTYPE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 14, 2) +#define IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 14, 2, value) +#define IE1_GET_TX_DESC_MOREFRAG(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 13, 1) +#define IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 13, 1, value) +#define IE1_GET_TX_DESC_NOACM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 12, 1) +#define IE1_SET_TX_DESC_NOACM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 12, 1, value) +#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 11, 1) +#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 11, 1, value) +#define IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 1) +#define IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 1, value) +#define IE1_GET_TX_DESC_HTC(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 9, 1) +#define IE1_SET_TX_DESC_HTC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 9, 1, value) +#define IE1_GET_TX_DESC_BMC(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 1) +#define IE1_SET_TX_DESC_BMC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 1, value) +#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1) +#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value) +#define IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1) +#define IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value) +#define IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 2) +#define IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 2, value) +#define IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1) +#define IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value) +#define IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1) +#define IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value) +#define IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1) +#define IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value) +#define IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1) +#define IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value) +#define IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 8) +#define IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 8, value) +#define IE1_GET_TX_DESC_P_AID(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 15, 9) +#define IE1_SET_TX_DESC_P_AID(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 15, 9, value) +#define IE1_GET_TX_DESC_MOREDATA(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 14, 1) +#define IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 14, 1, value) +#define IE1_GET_TX_DESC_SW_SEQ(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 12) +#define IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 12, value) +#define IE2_GET_TX_DESC_IE_END(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1) +#define IE2_SET_TX_DESC_IE_END(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value) +#define IE2_GET_TX_DESC_IE_UP(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1) +#define IE2_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value) +#define IE2_GET_TX_DESC_IE_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4) +#define IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value) +#define IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 8) +#define IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 8, value) +#define IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 12, 3) +#define IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 12, 3, value) +#define IE2_GET_TX_DESC_RAW(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 11, 1) +#define IE2_SET_TX_DESC_RAW(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 11, 1, value) +#define IE2_GET_TX_DESC_RDG_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 1) +#define IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 1, value) +#define IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1) +#define IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value) +#define IE2_GET_TX_DESC_POLLUTED(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1) +#define IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value) +#define IE2_GET_TX_DESC_BT_NULL(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 5, 1) +#define IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 5, 1, value) +#define IE2_GET_TX_DESC_NULL_1(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 1) +#define IE2_SET_TX_DESC_NULL_1(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 1, value) +#define IE2_GET_TX_DESC_NULL_0(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1) +#define IE2_SET_TX_DESC_NULL_0(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value) +#define IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1) +#define IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value) +#define IE2_GET_TX_DESC_SPE_RPT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1) +#define IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value) +#define IE2_GET_TX_DESC_FTM_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1) +#define IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value) +#define IE2_GET_TX_DESC_MBSSID(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 27, 4) +#define IE2_SET_TX_DESC_MBSSID(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 27, 4, value) +#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 11) +#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 11, value) +#define IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 15, 1) +#define IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 15, 1, value) +#define IE2_GET_TX_DESC_DROP_ID(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 2) +#define IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 2, value) +#define IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 12) +#define IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 12, value) +#define IE3_GET_TX_DESC_IE_END(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1) +#define IE3_SET_TX_DESC_IE_END(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value) +#define IE3_GET_TX_DESC_IE_UP(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1) +#define IE3_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value) +#define IE3_GET_TX_DESC_IE_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4) +#define IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value) +#define IE3_GET_TX_DESC_DATA_SC(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 20, 4) +#define IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 20, 4, value) +#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 4) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 4, value) +#define IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 4) +#define IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 4, value) +#define IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1) +#define IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value) +#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value) +#define IE3_GET_TX_DESC_G_ID(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 6) +#define IE3_SET_TX_DESC_G_ID(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 6, value) +#define IE3_GET_TX_DESC_SND_TARGET(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 8) +#define IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 8, value) +#define IE3_GET_TX_DESC_CCA_RTS(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 11, 2) +#define IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 11, 2, value) +#define IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 9, 2) +#define IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 9, 2, value) +#define IE3_GET_TX_DESC_NDPA(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 7, 2) +#define IE3_SET_TX_DESC_NDPA(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 7, 2, value) +#define IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 7) +#define IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 7, value) +#define IE4_GET_TX_DESC_IE_END(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1) +#define IE4_SET_TX_DESC_IE_END(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value) +#define IE4_GET_TX_DESC_IE_UP(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1) +#define IE4_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value) +#define IE4_GET_TX_DESC_IE_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4) +#define IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value) +#define IE4_GET_TX_DESC_VCS_STBC(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 2) +#define IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 2, value) +#define IE4_GET_TX_DESC_DATA_STBC(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 2) +#define IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 2, value) +#define IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1) +#define IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value) +#define IE4_GET_TX_DESC_GF(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1) +#define IE4_SET_TX_DESC_GF(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value) +#define IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1) +#define IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value) +#define IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 30, 2) +#define IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 30, 2, value) +#define IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 28, 2) +#define IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 28, 2, value) +#define IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 26, 2) +#define IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 26, 2, value) +#define IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 2) +#define IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 2, value) +#define IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 20, 4) +#define IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 20, 4, value) +#define IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 4) +#define IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 4, value) +#define IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 4) +#define IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 4, value) +#define IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 8, 4) +#define IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 8, 4, value) +#define IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 4, 4) +#define IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 4, 4, value) +#define IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 3, 1) +#define IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 3, 1, value) +#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 2) +#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 2, value) +#define IE5_GET_TX_DESC_IE_END(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1) +#define IE5_SET_TX_DESC_IE_END(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value) +#define IE5_GET_TX_DESC_IE_UP(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1) +#define IE5_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value) +#define IE5_GET_TX_DESC_IE_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4) +#define IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value) +#define IE5_GET_TX_DESC_LEN1_L(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 17, 7) +#define IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 17, 7, value) +#define IE5_GET_TX_DESC_LEN0(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 13) +#define IE5_SET_TX_DESC_LEN0(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 13, value) +#define IE5_GET_TX_DESC_PKT_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 4) +#define IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 4, value) +#define IE5_GET_TX_DESC_LEN3(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 19, 13) +#define IE5_SET_TX_DESC_LEN3(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 19, 13, value) +#define IE5_GET_TX_DESC_LEN2(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 6, 13) +#define IE5_SET_TX_DESC_LEN2(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 6, 13, value) +#define IE5_GET_TX_DESC_LEN1_H(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 6) +#define IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 6, value) + +#endif + +#endif diff --git a/hal/led/hal_led.c b/hal/led/hal_led.c new file mode 100644 index 0000000..95d3daa --- /dev/null +++ b/hal/led/hal_led.c @@ -0,0 +1,254 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include +#include + +#ifdef CONFIG_RTW_LED +void dump_led_config(void *sel, _adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct led_priv *ledpriv = adapter_to_led(adapter); + int i; + + RTW_PRINT_SEL(sel, "strategy:%u\n", ledpriv->LedStrategy); +#ifdef CONFIG_RTW_SW_LED + RTW_PRINT_SEL(sel, "bRegUseLed:%u\n", ledpriv->bRegUseLed); + RTW_PRINT_SEL(sel, "iface_en_mask:0x%02X\n", ledpriv->iface_en_mask); + for (i = 0; i < dvobj->iface_nums; i++) + RTW_PRINT_SEL(sel, "ctl_en_mask[%d]:0x%08X\n", i, ledpriv->ctl_en_mask[i]); +#endif +} + +void rtw_led_set_strategy(_adapter *adapter, u8 strategy) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + _adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter); + +#ifndef CONFIG_RTW_SW_LED + if (IS_SW_LED_STRATEGY(strategy)) { + RTW_WARN("CONFIG_RTW_SW_LED is not defined\n"); + return; + } +#endif + +#ifdef CONFIG_RTW_SW_LED + if (!ledpriv->bRegUseLed) + return; +#endif + + if (ledpriv->LedStrategy == strategy) + return; + + if (IS_HW_LED_STRATEGY(strategy) || IS_HW_LED_STRATEGY(ledpriv->LedStrategy)) { + RTW_WARN("switching on/off HW_LED strategy is not supported\n"); + return; + } + + ledpriv->LedStrategy = strategy; + +#ifdef CONFIG_RTW_SW_LED + rtw_hal_sw_led_deinit(pri_adapter); +#endif + + rtw_led_control(pri_adapter, RTW_LED_OFF); +} + +#ifdef CONFIG_RTW_SW_LED +#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY +void rtw_sw_led_blink_uc_trx_only(LED_DATA *led) +{ + _adapter *adapter = led->padapter; + BOOLEAN bStopBlinking = _FALSE; + + if (led->BlinkingLedState == RTW_LED_ON) + SwLedOn(adapter, led); + else + SwLedOff(adapter, led); + + switch (led->CurrLedState) { + case RTW_LED_ON: + SwLedOn(adapter, led); + break; + + case RTW_LED_OFF: + SwLedOff(adapter, led); + break; + + case LED_BLINK_TXRX: + led->BlinkTimes--; + if (led->BlinkTimes == 0) + bStopBlinking = _TRUE; + + if (adapter_to_pwrctl(adapter)->rf_pwrstate != rf_on + && adapter_to_pwrctl(adapter)->rfoff_reason > RF_CHANGE_BY_PS + ) { + SwLedOff(adapter, led); + led->bLedBlinkInProgress = _FALSE; + } else { + if (led->bLedOn) + led->BlinkingLedState = RTW_LED_OFF; + else + led->BlinkingLedState = RTW_LED_ON; + + if (bStopBlinking) { + led->CurrLedState = RTW_LED_OFF; + led->bLedBlinkInProgress = _FALSE; + } + _set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + break; + + default: + break; + } +} + +void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + LED_DATA *led = &(ledpriv->SwLed0); + LED_DATA *led1 = &(ledpriv->SwLed1); + LED_DATA *led2 = &(ledpriv->SwLed2); + + switch (ctl) { + case LED_CTL_UC_TX: + case LED_CTL_UC_RX: + if (led->bLedBlinkInProgress == _FALSE) { + led->bLedBlinkInProgress = _TRUE; + led->CurrLedState = LED_BLINK_TXRX; + led->BlinkTimes = 2; + if (led->bLedOn) + led->BlinkingLedState = RTW_LED_OFF; + else + led->BlinkingLedState = RTW_LED_ON; + _set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + break; + + case LED_CTL_POWER_OFF: + led->CurrLedState = RTW_LED_OFF; + led->BlinkingLedState = RTW_LED_OFF; + + if (led->bLedBlinkInProgress) { + _cancel_timer_ex(&(led->BlinkTimer)); + led->bLedBlinkInProgress = _FALSE; + } + + SwLedOff(adapter, led); + SwLedOff(adapter, led1); + SwLedOff(adapter, led2); + break; + + default: + break; + } +} +#endif /* CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY */ + +void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + + if (ledpriv->LedControlHandler) { + #if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY + if (ledpriv->LedStrategy != SW_LED_MODE_UC_TRX_ONLY) { + if (ctl == LED_CTL_UC_TX || ctl == LED_CTL_BMC_TX) { + if (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_TX)) + ctl = LED_CTL_TX; /* transform specific TX ctl to general TX ctl */ + } else if (ctl == LED_CTL_UC_RX || ctl == LED_CTL_BMC_RX) { + if (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_RX)) + ctl = LED_CTL_RX; /* transform specific RX ctl to general RX ctl */ + } + } + #endif + + if ((ledpriv->iface_en_mask & BIT(adapter->iface_id)) + && (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(ctl))) + ledpriv->LedControlHandler(adapter, ctl); + } +} + +void rtw_led_tx_control(_adapter *adapter, const u8 *da) +{ +#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY + if (IS_MCAST(da)) + rtw_led_control(adapter, LED_CTL_BMC_TX); + else + rtw_led_control(adapter, LED_CTL_UC_TX); +#else + rtw_led_control(adapter, LED_CTL_TX); +#endif +} + +void rtw_led_rx_control(_adapter *adapter, const u8 *da) +{ +#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY + if (IS_MCAST(da)) + rtw_led_control(adapter, LED_CTL_BMC_RX); + else + rtw_led_control(adapter, LED_CTL_UC_RX); +#else + rtw_led_control(adapter, LED_CTL_RX); +#endif +} + +void rtw_led_set_iface_en(_adapter *adapter, u8 en) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + + if (en) + ledpriv->iface_en_mask |= BIT(adapter->iface_id); + else + ledpriv->iface_en_mask &= ~BIT(adapter->iface_id); +} + +void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + + ledpriv->iface_en_mask = mask; +} + +void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + +#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY + if (ctl_mask & BIT(LED_CTL_TX)) + ctl_mask |= BIT(LED_CTL_UC_TX) | BIT(LED_CTL_BMC_TX); + if (ctl_mask & BIT(LED_CTL_RX)) + ctl_mask |= BIT(LED_CTL_UC_RX) | BIT(LED_CTL_BMC_RX); +#endif + + ledpriv->ctl_en_mask[adapter->iface_id] = ctl_mask; +} + +void rtw_led_set_ctl_en_mask_primary(_adapter *adapter) +{ + rtw_led_set_ctl_en_mask(adapter, 0xFFFFFFFF); +} + +void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter) +{ + rtw_led_set_ctl_en_mask(adapter + , BIT(LED_CTL_POWER_ON) | BIT(LED_CTL_POWER_OFF) + | BIT(LED_CTL_TX) | BIT(LED_CTL_RX) + ); +} +#endif /* CONFIG_RTW_SW_LED */ + +#endif /* CONFIG_RTW_LED */ + diff --git a/hal/phydm/halrf/halrf_powertracking.c b/hal/phydm/halrf/halrf_powertracking.c new file mode 100644 index 0000000..db751bd --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking.c @@ -0,0 +1,159 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +boolean +odm_check_power_status( + void *dm_void +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct dm_struct *dm = (struct dm_struct *)dm_void; + PADAPTER adapter = (PADAPTER)dm->adapter; + + RT_RF_POWER_STATE rt_state; + MGNT_INFO *mgnt_info = &adapter->MgntInfo; + + /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */ + if (mgnt_info->init_adpt_in_progress == true) { + PHYDM_DBG(dm, ODM_COMP_INIT, "check_pow_status Return true, due to initadapter\n"); + return true; + } + + /* */ + /* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */ + /* */ + adapter->HalFunc.GetHwRegHandler(adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state)); + if (adapter->bDriverStopped || adapter->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) { + PHYDM_DBG(dm, ODM_COMP_INIT, "check_pow_status Return false, due to %d/%d/%d\n", + adapter->bDriverStopped, adapter->bDriverIsGoingToPnpSetPowerSleep, rt_state); + return false; + } +#endif + return true; + +} + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +void +halrf_update_pwr_track( + void *dm_void, + u8 rate +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + u8 path_idx = 0; +#endif + + PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n", rate); + + dm->tx_rate = rate; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +#if USE_WORKITEM + odm_schedule_work_item(&dm->ra_rpt_workitem); +#else + if (dm->support_ic_type == ODM_RTL8821) { +#if (RTL8821A_SUPPORT == 1) + odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0); +#endif + } else if (dm->support_ic_type == ODM_RTL8812) { + for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) { +#if (RTL8812A_SUPPORT == 1) + odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, path_idx, 0); +#endif + } + } else if (dm->support_ic_type == ODM_RTL8723B) { +#if (RTL8723B_SUPPORT == 1) + odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0); +#endif + } else if (dm->support_ic_type == ODM_RTL8192E) { + for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) { +#if (RTL8192E_SUPPORT == 1) + odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, path_idx, 0); +#endif + } + } else if (dm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0); +#endif + } +#endif +#else + odm_schedule_work_item(&dm->ra_rpt_workitem); +#endif +#endif + +} + +#endif + + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void +halrf_update_init_rate_work_item_callback( + void *context +) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + u8 p = 0; + + if (dm->support_ic_type == ODM_RTL8821) { + odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0); + /**/ + } else if (dm->support_ic_type == ODM_RTL8812) { + for (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) { /*DOn't know how to include &c*/ + + odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, p, 0); + /**/ + } + } else if (dm->support_ic_type == ODM_RTL8723B) { + odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0); + /**/ + } else if (dm->support_ic_type == ODM_RTL8192E) { + for (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) { /*DOn't know how to include &c*/ + odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, p, 0); + /**/ + } + } else if (dm->support_ic_type == ODM_RTL8188E) { + odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0); + /**/ + } +} +#endif + + + diff --git a/hal/phydm/halrf/halrf_powertracking.h b/hal/phydm/halrf/halrf_powertracking.h new file mode 100644 index 0000000..15e056b --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking.h @@ -0,0 +1,50 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_POWER_TRACKING_H__ +#define __HALRF_POWER_TRACKING_H__ + + +boolean +odm_check_power_status( + void *dm_void +); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +void +halrf_update_pwr_track( + void *dm_void, + u8 rate +); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void +halrf_update_init_rate_work_item_callback( + void *context +); +#endif + +#endif diff --git a/hal/phydm/halrf/halrf_psd.c b/hal/phydm/halrf/halrf_psd.c new file mode 100644 index 0000000..3193ebe --- /dev/null +++ b/hal/phydm/halrf/halrf_psd.c @@ -0,0 +1,321 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#if 0 +u32 _sqrt(u64 n) +{ + u64 ans = 0, q = 0; + s64 i; + + /*for (i = sizeof(n) * 8 - 2; i > -1; i = i - 2) {*/ + for (i = 8 * 8 - 2; i > -1; i = i - 2) { + q = (q << 2) | ((n & (3 << i)) >> i); + if (q >= ((ans << 2) | 1)) + { + q = q - ((ans << 2) | 1); + ans = (ans << 1) | 1; + } + else + ans = ans << 1; + } + DbgPrint("ans=0x%x\n", ans); + + return (u32)ans; +} +#endif + + + +u64 _sqrt(u64 x) +{ + u64 i = 0; + u64 j = x / 2 + 1; + + while (i <= j) { + u64 mid = (i + j) / 2; + + u64 sq = mid * mid; + + if (sq == x) + return mid; + else if (sq < x) + i = mid + 1; + else + j = mid - 1; + } + + return j; +} + + + +u32 +halrf_get_psd_data( + struct dm_struct *dm, + u32 point + ) +{ + struct _hal_rf_ *rf = &(dm->rf_table); + struct _halrf_psd_data *psd = &(rf->halrf_psd_data); + u32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time; + +#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE) + if (psd->average == 0) + delay_time = 100; + else + delay_time = 0; +#else + if (psd->average == 0) + delay_time = 1000; + else + delay_time = 100; +#endif + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) { + psd_reg = 0x910; + psd_report = 0xf44; + } else { + psd_reg = 0x808; + psd_report = 0x8b4; + } + + if (dm->support_ic_type & ODM_RTL8710B) { + psd_point = 0xeffffc00; + psd_start = 0x10000000; + } else { + psd_point = 0xffbffc00; + psd_start = 0x00400000; + } + + psd_val = odm_get_bb_reg(dm, psd_reg, MASKDWORD); + + psd_val &= psd_point; + psd_val |= point; + + odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val); + + psd_val |= psd_start; + + odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val); + + for (i = 0; i < delay_time; i++) + ODM_delay_us(1); + + psd_val = odm_get_bb_reg(dm, psd_report, MASKDWORD); + + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8710B)) { + psd_val &= MASKL3BYTES; + psd_val = psd_val / 32; + } else + psd_val &= MASKLWORD; + + return psd_val; +} + + + +void +halrf_psd( + struct dm_struct *dm, + u32 point, + u32 start_point, + u32 stop_point, + u32 average + ) +{ + struct _hal_rf_ *rf = &(dm->rf_table); + struct _halrf_psd_data *psd = &(rf->halrf_psd_data); + + u32 i = 0, j = 0, k = 0; + u32 psd_reg, avg_org, point_temp, average_tmp; + u64 data_tatal = 0, data_temp[64] = {0}; + + psd->buf_size = 256; + + if (average == 0) + average_tmp = 1; + else + average_tmp = average; + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) + psd_reg = 0x910; + else + psd_reg = 0x808; + +#if 0 + dbg_print("[PSD]point=%d, start_point=%d, stop_point=%d, average=%d, average_tmp=%d, buf_size=%d\n", + point, start_point, stop_point, average, average_tmp, psd->buf_size); +#endif + + for (i = 0; i < psd->buf_size; i++) + psd->psd_data[i] = 0; + + if (dm->support_ic_type & ODM_RTL8710B) + avg_org = odm_get_bb_reg(dm, psd_reg, 0x30000); + else + avg_org = odm_get_bb_reg(dm, psd_reg, 0x3000); + + if (average != 0) + { + if (dm->support_ic_type & ODM_RTL8710B) + odm_set_bb_reg(dm, psd_reg, 0x30000, 0x1); + else + odm_set_bb_reg(dm, psd_reg, 0x3000, 0x1); + } + +#if 0 + if (avg_temp == 0) + avg = 1; + else if (avg_temp == 1) + avg = 8; + else if (avg_temp == 2) + avg = 16; + else if (avg_temp == 3) + avg = 32; +#endif + + i = start_point; + while (i < stop_point) { + data_tatal = 0; + + if (i >= point) + point_temp = i - point; + else + point_temp = i; + + for (k = 0; k < average_tmp; k++) { + data_temp[k] = halrf_get_psd_data(dm, point_temp); + data_tatal = data_tatal + (data_temp[k] * data_temp[k]); + +#if 0 + if ((k % 20) == 0) + dbg_print("\n "); + + dbg_print("0x%x ", data_temp[k]); +#endif + } + /*dbg_print("\n");*/ + + data_tatal = ((data_tatal * 100) / average_tmp); + psd->psd_data[j] = (u32)_sqrt(data_tatal); + + i++; + j++; + } + +#if 0 + for (i = 0; i < psd->buf_size; i++) { + if ((i % 20) == 0) + dbg_print("\n "); + + dbg_print("0x%x ", psd->psd_data[i]); + } + dbg_print("\n\n"); +#endif + + if (dm->support_ic_type & ODM_RTL8710B) + odm_set_bb_reg(dm, psd_reg, 0x30000, avg_org); + else + odm_set_bb_reg(dm, psd_reg, 0x3000, avg_org); +} + + + +enum rt_status +halrf_psd_init( + struct dm_struct *dm + ) +{ + enum rt_status ret_status = RT_STATUS_SUCCESS; + struct _hal_rf_ *rf = &(dm->rf_table); + struct _halrf_psd_data *psd = &(rf->halrf_psd_data); + + if (psd->psd_progress) + ret_status = RT_STATUS_PENDING; + else { + psd->psd_progress = 1; + halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average); + psd->psd_progress = 0; + } + + return ret_status; +} + + + +enum rt_status +halrf_psd_query( + struct dm_struct *dm, + u32 *outbuf, + u32 buf_size + ) +{ + enum rt_status ret_status = RT_STATUS_SUCCESS; + struct _hal_rf_ *rf = &(dm->rf_table); + struct _halrf_psd_data *psd = &(rf->halrf_psd_data); + + if (psd->psd_progress) + ret_status = RT_STATUS_PENDING; + else + PlatformMoveMemory(outbuf, psd->psd_data, 0x400); + + return ret_status; +} + + + +enum rt_status +halrf_psd_init_query( + struct dm_struct *dm, + u32 *outbuf, + u32 point, + u32 start_point, + u32 stop_point, + u32 average, + u32 buf_size + ) +{ + enum rt_status ret_status = RT_STATUS_SUCCESS; + struct _hal_rf_ *rf = &(dm->rf_table); + struct _halrf_psd_data *psd = &(rf->halrf_psd_data); + + psd->point = point; + psd->start_point = start_point; + psd->stop_point = stop_point; + psd->average = average; + + if (psd->psd_progress) + ret_status = RT_STATUS_PENDING; + else { + psd->psd_progress = 1; + halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average); + PlatformMoveMemory(outbuf, psd->psd_data, 0x400); + psd->psd_progress = 0; + } + + return ret_status; +} + +#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/ + diff --git a/hal/phydm/halrf/halrf_psd.h b/hal/phydm/halrf/halrf_psd.h new file mode 100644 index 0000000..8e4b7f4 --- /dev/null +++ b/hal/phydm/halrf/halrf_psd.h @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __HALRF_PSD_H__ +#define __HALRF_PSD_H__ + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + +struct _halrf_psd_data { + u32 point; + u32 start_point; + u32 stop_point; + u32 average; + u32 buf_size; + u32 psd_data[256]; + u32 psd_progress; +}; + + + +enum rt_status +halrf_psd_init ( + struct dm_struct *dm + ); + + + +enum rt_status +halrf_psd_query ( + struct dm_struct *dm, + u32 *outbuf, + u32 buf_size +); + +enum rt_status +halrf_psd_init_query( + struct dm_struct *dm, + u32 *outbuf, + u32 point, + u32 start_point, + u32 stop_point, + u32 average, + u32 buf_size +); + +#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/ +#endif /*#ifndef __HALRF_PSD_H__*/ + diff --git a/hal/phydm/halrf/halrf_txgapcal.c b/hal/phydm/halrf/halrf_txgapcal.c new file mode 100644 index 0000000..713f811 --- /dev/null +++ b/hal/phydm/halrf/halrf_txgapcal.c @@ -0,0 +1,303 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + + + +void odm_bub_sort(pu4Byte data, u4Byte n) +{ + int i, j, temp, sp; + + for (i = n - 1;i >= 0;i--) { + sp = 1; + for (j = 0;j < i;j++) { + if (data[j] < data[j + 1]) { + temp = data[j]; + data[j] = data[j + 1]; + data[j + 1] = temp; + sp = 0; + } + } + if (sp == 1) + break; + } +} + + +#if (RTL8197F_SUPPORT == 1) + +u4Byte +odm_tx_gain_gap_psd_8197f( + void *dm_void, + u1Byte rf_path, + u4Byte rf56 +) +{ + PDM_ODM_T dm = (PDM_ODM_T)dm_void; + + u1Byte i, j; + u4Byte psd_vaule[5], psd_avg_time = 5, psd_vaule_temp; + + u4Byte iqk_ctl_addr[2][6] = {{0xe30, 0xe34, 0xe50, 0xe54, 0xe38, 0xe3c}, + {0xe50, 0xe54, 0xe30, 0xe34, 0xe58, 0xe5c}}; + + u4Byte psd_finish_bit[2] = {0x04000000, 0x20000000}; + u4Byte psd_fail_bit[2] = {0x08000000, 0x40000000}; + + u4Byte psd_cntl_value[2][2] = {{0x38008c1c, 0x10008c1c}, + {0x38008c2c, 0x10008c2c}}; + + u4Byte psd_report_addr[2] = {0xea0, 0xec0}; + + odm_set_rf_reg(dm, rf_path, 0xdf, bRFRegOffsetMask, 0x00e02); + + ODM_delay_us(100); + + odm_set_bb_reg(dm, 0xe28, 0xffffffff, 0x0); + + odm_set_rf_reg(dm, rf_path, 0x56, 0xfff, rf56); + while(rf56 != (odm_get_rf_reg(dm, rf_path, 0x56, 0xfff))) + odm_set_rf_reg(dm, rf_path, 0x56, 0xfff, rf56); + + odm_set_bb_reg(dm, 0xd94, 0xffffffff, 0x44FFBB44); + odm_set_bb_reg(dm, 0xe70, 0xffffffff, 0x00400040); + odm_set_bb_reg(dm, 0xc04, 0xffffffff, 0x6f005403); + odm_set_bb_reg(dm, 0xc08, 0xffffffff, 0x000804e4); + odm_set_bb_reg(dm, 0x874, 0xffffffff, 0x04203400); + odm_set_bb_reg(dm, 0xe28, 0xffffffff, 0x80800000); + + odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][0], 0xffffffff, psd_cntl_value[rf_path][0]); + odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][1], 0xffffffff, psd_cntl_value[rf_path][1]); + odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][2], 0xffffffff, psd_cntl_value[rf_path][0]); + odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][3], 0xffffffff, psd_cntl_value[rf_path][0]); + odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][4], 0xffffffff, 0x8215001F); + odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][5], 0xffffffff, 0x2805001F); + + odm_set_bb_reg(dm, 0xe40, 0xffffffff, 0x81007C00); + odm_set_bb_reg(dm, 0xe44, 0xffffffff, 0x81004800); + odm_set_bb_reg(dm, 0xe4c, 0xffffffff, 0x0046a8d0); + + + for (i = 0; i < psd_avg_time; i++) { + + for(j = 0; j < 1000 ; j++) { + odm_set_bb_reg(dm, 0xe48, 0xffffffff, 0xfa005800); + odm_set_bb_reg(dm, 0xe48, 0xffffffff, 0xf8005800); + + while(!odm_get_bb_reg(dm, 0xeac, psd_finish_bit[rf_path])); /*wait finish bit*/ + + if (!odm_get_bb_reg(dm, 0xeac, psd_fail_bit[rf_path])) { /*check fail bit*/ + + psd_vaule[i] = odm_get_bb_reg(dm, psd_report_addr[rf_path], 0xffffffff); + + if (psd_vaule[i] > 0xffff) + break; + } + } + + + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x time=%d psd_vaule=0x%x\n", + odm_get_rf_reg(dm, rf_path, 0x0, 0xff), + rf56, odm_get_rf_reg(dm, rf_path, 0x56, 0xfff), j, psd_vaule[i]); + } + + odm_bub_sort(psd_vaule, psd_avg_time); + + psd_vaule_temp = psd_vaule[(UINT)(psd_avg_time / 2)]; + + odm_set_bb_reg(dm, 0xd94, 0xffffffff, 0x44BBBB44); + odm_set_bb_reg(dm, 0xe70, 0xffffffff, 0x80408040); + odm_set_bb_reg(dm, 0xc04, 0xffffffff, 0x6f005433); + odm_set_bb_reg(dm, 0xc08, 0xffffffff, 0x000004e4); + odm_set_bb_reg(dm, 0x874, 0xffffffff, 0x04003400); + odm_set_bb_reg(dm, 0xe28, 0xffffffff, 0x00000000); + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x psd_vaule_temp=0x%x\n", + odm_get_rf_reg(dm, rf_path, 0x0, 0xff), + rf56, odm_get_rf_reg(dm, rf_path, 0x56, 0xfff), psd_vaule_temp); + + odm_set_rf_reg(dm, rf_path, 0xdf, bRFRegOffsetMask, 0x00602); + + return psd_vaule_temp; + +} + + + +void +odm_tx_gain_gap_calibration_8197f( + void *dm_void +) +{ + PDM_ODM_T dm = (PDM_ODM_T)dm_void; + + u1Byte rf_path, rf0_idx, rf0_idx_current, rf0_idx_next, i, delta_gain_retry = 3; + + s1Byte delta_gain_gap_pre, delta_gain_gap[2][11]; + u4Byte rf56_current, rf56_next, psd_value_current, psd_value_next; + u4Byte psd_gap, rf56_current_temp[2][11]; + s4Byte rf33[2][11]; + + memset(rf33, 0x0, sizeof(rf33)); + + for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) { + + if (rf_path == RF_PATH_A) + odm_set_bb_reg(dm, 0x88c, (BIT(21) | BIT(20)), 0x3); /*disable 3-wire*/ + else if (rf_path == RF_PATH_B) + odm_set_bb_reg(dm, 0x88c, (BIT(23) | BIT(22)), 0x3); /*disable 3-wire*/ + + ODM_delay_us(100); + + for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) { + + rf0_idx_current = 3 * (rf0_idx - 1) + 1; + odm_set_rf_reg(dm, rf_path, 0x0, 0xff, rf0_idx_current); + ODM_delay_us(100); + rf56_current_temp[rf_path][rf0_idx] = odm_get_rf_reg(dm, rf_path, 0x56, 0xfff); + rf56_current = rf56_current_temp[rf_path][rf0_idx]; + + rf0_idx_next = 3 * rf0_idx + 1; + odm_set_rf_reg(dm, rf_path, 0x0, 0xff, rf0_idx_next); + ODM_delay_us(100); + rf56_next= odm_get_rf_reg(dm, rf_path, 0x56, 0xfff); + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56_current[%d][%d]=0x%x rf56_next[%d][%d]=0x%x\n", + rf_path, rf0_idx, rf56_current, rf_path, rf0_idx, rf56_next); + + if ((rf56_current >> 5) == (rf56_next >> 5)) { + delta_gain_gap[rf_path][rf0_idx] = 0; + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56_current[11:5] == rf56_next[%d][%d][11:5]=0x%x delta_gain_gap[%d][%d]=%d\n", + rf_path, rf0_idx, (rf56_next >> 5), rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx]); + + continue; + } + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56_current[%d][%d][11:5]=0x%x != rf56_next[%d][%d][11:5]=0x%x\n", + rf_path, rf0_idx, (rf56_current >> 5), rf_path, rf0_idx, (rf56_next >> 5)); + + for (i = 0; i < delta_gain_retry; i++) { + psd_value_current = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_current); + + psd_value_next = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_next - 2); + + psd_gap = psd_value_next / (psd_value_current / 1000); + +#if 0 + if (psd_gap > 1413) + delta_gain_gap[rf_path][rf0_idx] = 1; + else if (psd_gap > 1122) + delta_gain_gap[rf_path][rf0_idx] = 0; + else + delta_gain_gap[rf_path][rf0_idx] = -1; +#endif + + if (psd_gap > 1445) + delta_gain_gap[rf_path][rf0_idx] = 1; + else if (psd_gap > 1096) + delta_gain_gap[rf_path][rf0_idx] = 0; + else + delta_gain_gap[rf_path][rf0_idx] = -1; + + if (i == 0) + delta_gain_gap_pre = delta_gain_gap[rf_path][rf0_idx]; + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] psd_value_current=0x%x psd_value_next=0x%x psd_value_next/psd_value_current=%d delta_gain_gap[%d][%d]=%d\n", + psd_value_current, psd_value_next, psd_gap, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx]); + + if ((i == 0) && (delta_gain_gap[rf_path][rf0_idx] == 0)) + break; + + if (delta_gain_gap_pre != delta_gain_gap[rf_path][rf0_idx]) { + delta_gain_gap[rf_path][rf0_idx] = 0; + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] delta_gain_gap_pre(%d) != delta_gain_gap[%d][%d](%d) time=%d\n", + delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i); + + break; + } else { + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] delta_gain_gap_pre(%d) == delta_gain_gap[%d][%d](%d) time=%d\n", + delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i); + } + } + } + + if (rf_path == RF_PATH_A) + odm_set_bb_reg(dm, 0x88c, (BIT(21) | BIT(20)), 0x0); /*enable 3-wire*/ + else if (rf_path == RF_PATH_B) + odm_set_bb_reg(dm, 0x88c, (BIT(23) | BIT(22)), 0x0); /*enable 3-wire*/ + + ODM_delay_us(100); + + } + + /*odm_set_bb_reg(dm, 0x88c, (BIT(23) | BIT(22) | BIT(21) | BIT(20)), 0x0);*/ /*enable 3-wire*/ + + for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) { + + odm_set_rf_reg(dm, rf_path, 0xef, bRFRegOffsetMask, 0x00100); + + for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) { + + rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + (rf56_current_temp[rf_path][rf0_idx] & 0x1f); + + for (i = rf0_idx; i <= 10; i++) + rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + delta_gain_gap[rf_path][i]; + + if (rf33[rf_path][rf0_idx] >= 0x1d) + rf33[rf_path][rf0_idx] = 0x1d; + else if (rf33[rf_path][rf0_idx] <= 0x2) + rf33[rf_path][rf0_idx] = 0x2; + + rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + ((rf0_idx - 1) * 0x4000) + (rf56_current_temp[rf_path][rf0_idx] & 0xfffe0); + + PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56[%d][%d]=0x%05x rf33[%d][%d]=0x%05x\n", rf_path, rf0_idx, rf56_current_temp[rf_path][rf0_idx], rf_path, rf0_idx, rf33[rf_path][rf0_idx]); + + odm_set_rf_reg(dm, rf_path, 0x33, bRFRegOffsetMask, rf33[rf_path][rf0_idx]); + } + + odm_set_rf_reg(dm, rf_path, 0xef, bRFRegOffsetMask, 0x00000); + } + +} +#endif + + +void +odm_tx_gain_gap_calibration( + void *dm_void +) +{ + PDM_ODM_T dm = (PDM_ODM_T)dm_void; + + #if (RTL8197F_SUPPORT == 1) + if (dm->SupportICType & ODM_RTL8197F) + odm_tx_gain_gap_calibration_8197f(dm_void); + #endif + +} diff --git a/hal/phydm/halrf/halrf_txgapcal.h b/hal/phydm/halrf/halrf_txgapcal.h new file mode 100644 index 0000000..c404114 --- /dev/null +++ b/hal/phydm/halrf/halrf_txgapcal.h @@ -0,0 +1,29 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +void +odm_tx_gain_gap_calibration( + void *dm_void +); + diff --git a/hal/phydm/phydm_api.c b/hal/phydm/phydm_api.c new file mode 100644 index 0000000..9b959b4 --- /dev/null +++ b/hal/phydm/phydm_api.c @@ -0,0 +1,1424 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void +phydm_dynamic_ant_weighting( + void *dm_void +) +{ +struct dm_struct *dm = (struct dm_struct *)dm_void; + +#ifdef DYN_ANT_WEIGHTING_SUPPORT + #if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8197F)) + phydm_dynamic_ant_weighting_8197f(dm); + #endif + + #if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8812)) { + phydm_dynamic_ant_weighting_8812a(dm); + } + #endif + + #if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8822B)) { + phydm_dynamic_ant_weighting_8822b(dm); + } + #endif +#endif +} + +#ifdef DYN_ANT_WEIGHTING_SUPPORT +void +phydm_dyn_ant_weight_dbg( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, "echo dis_dym_ant_weighting {0/1}\n"); + + } else { + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 1) { + dm->is_disable_dym_ant_weighting = 1; + PDM_SNPF(out_len, used, output + used, out_len - used, "Disable dyn-ant-weighting\n"); + } else { + dm->is_disable_dym_ant_weighting = 0; + PDM_SNPF(out_len, used, output + used, out_len - used, "Enable dyn-ant-weighting\n"); + } + } + *_used = used; + *_out_len = out_len; +} +#endif + +void +phydm_iq_gen_en( + void *dm_void +) +{ +#ifdef PHYDM_COMPILE_IC_2SS + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i; + + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + for (i = RF_PATH_A; i <= RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, 0xEF, BIT(19), 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, (enum rf_path)i, 0x33, 0xF, 3); /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, 0x3E, 0xfffff, 0x00036); /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, 0x3F, 0xfffff, 0x5AFCE); /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, 0xEF, BIT(19), 0x0); /*RF mode table write disable*/ + } + } + #endif +#endif +} + +void +phydm_dis_cdd( + void *dm_void +) +{ +#ifdef PHYDM_COMPILE_IC_2SS + struct dm_struct *dm = (struct dm_struct *)dm_void; + + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, 0x808, 0x3ffff00, 0); + odm_set_bb_reg(dm, 0x9ac, 0x1fff, 0); + odm_set_bb_reg(dm, 0x9ac, BIT(13), 1); + } + #endif +#endif +} + +void +phydm_pathb_q_matrix_rotate_en( + void *dm_void +) +{ +#ifdef PHYDM_COMPILE_IC_2SS + struct dm_struct *dm = (struct dm_struct *)dm_void; + + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + phydm_iq_gen_en(dm); + + #ifdef PHYDM_COMMON_API_SUPPORT + if (phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, true) == false) + return; + #endif + + phydm_dis_cdd(dm); + odm_set_bb_reg(dm, 0x195c, MASKDWORD, 0x40000); /*Set Q matrix r_v11 =1*/ + phydm_pathb_q_matrix_rotate(dm, 0); + odm_set_bb_reg(dm, 0x191c, BIT(7), 1); /*Set Q matrix enable*/ + } + #endif +#endif +} + +void +phydm_pathb_q_matrix_rotate( + void *dm_void, + u16 phase_idx +) +{ +#ifdef PHYDM_COMPILE_IC_2SS + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 phase_table_0[12] = {0x40000, 0x376CF, 0x20000, 0x00000, 0xFE0000, 0xFC8930, + 0xFC0000, 0xFC8930, 0xFDFFFF, 0x000000, 0x020000, 0x0376CF}; + u32 phase_table_1[12] = {0x00000, 0x1FFFF, 0x376CF, 0x40000, 0x0376CF, 0x01FFFF, + 0x000000, 0xFDFFFF, 0xFC8930, 0xFC0000, 0xFC8930, 0xFDFFFF}; + + if (phase_idx >= 12) { + PHYDM_DBG(dm, ODM_COMP_API, "Phase Set Error: %d\n", phase_idx); + return; + } + + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, 0x1954, 0xffffff, phase_table_0[phase_idx]); /*Set Q matrix r_v21*/ + odm_set_bb_reg(dm, 0x1950, 0xffffff, phase_table_1[phase_idx]); + } + #endif +#endif +} + +void +phydm_init_trx_antenna_setting( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & (ODM_RTL8814A)) { + u8 rx_ant = 0, tx_ant = 0; + + rx_ant = (u8)odm_get_bb_reg(dm, ODM_REG(BB_RX_PATH, dm), ODM_BIT(BB_RX_PATH, dm)); + tx_ant = (u8)odm_get_bb_reg(dm, ODM_REG(BB_TX_PATH, dm), ODM_BIT(BB_TX_PATH, dm)); + dm->tx_ant_status = (tx_ant & 0xf); + dm->rx_ant_status = (rx_ant & 0xf); + } else if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B)) {/* JJ ADD 20161014 */ + dm->tx_ant_status = 0x1; + dm->rx_ant_status = 0x1; + + } +} + +void +phydm_config_ofdm_tx_path( + void *dm_void, + u32 path +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) + u8 ofdm_tx_path = 0x33; +#endif + +#if (RTL8192E_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8192E)) { + if (path == BB_PATH_A) { + odm_set_bb_reg(dm, 0x90c, MASKDWORD, 0x81121111); + /**/ + } else if (path == BB_PATH_B) { + odm_set_bb_reg(dm, 0x90c, MASKDWORD, 0x82221222); + /**/ + } else if (path == BB_PATH_AB) { + odm_set_bb_reg(dm, 0x90c, MASKDWORD, 0x83321333); + /**/ + } + + + } +#endif + +#if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8812)) { + if (path == BB_PATH_A) { + ofdm_tx_path = 0x11; + /**/ + } else if (path == BB_PATH_B) { + ofdm_tx_path = 0x22; + /**/ + } else if (path == BB_PATH_AB) { + ofdm_tx_path = 0x33; + /**/ + } + + odm_set_bb_reg(dm, 0x80c, 0xff00, ofdm_tx_path); + } +#endif +} + +void +phydm_config_ofdm_rx_path( + void *dm_void, + u32 path +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ofdm_rx_path = 0; + + + if (dm->support_ic_type & (ODM_RTL8192E)) { +#if (RTL8192E_SUPPORT == 1) + if (path == BB_PATH_A) { + ofdm_rx_path = 1; + /**/ + } else if (path == BB_PATH_B) { + ofdm_rx_path = 2; + /**/ + } else if (path == BB_PATH_AB) { + ofdm_rx_path = 3; + /**/ + } + + odm_set_bb_reg(dm, 0xC04, 0xff, (((ofdm_rx_path) << 4) | ofdm_rx_path)); + odm_set_bb_reg(dm, 0xD04, 0xf, ofdm_rx_path); +#endif + } +#if (RTL8812A_SUPPORT || RTL8822B_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) { + if (path == BB_PATH_A) { + ofdm_rx_path = 1; + /**/ + } else if (path == BB_PATH_B) { + ofdm_rx_path = 2; + /**/ + } else if (path == BB_PATH_AB) { + ofdm_rx_path = 3; + /**/ + } + + odm_set_bb_reg(dm, 0x808, MASKBYTE0, ((ofdm_rx_path << 4) | ofdm_rx_path)); + } +#endif +} + +void +phydm_config_cck_rx_antenna_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + /*CCK 2R CCA parameters*/ + odm_set_bb_reg(dm, 0xa00, BIT(15), 0x0); /*Disable antenna diversity*/ + odm_set_bb_reg(dm, 0xa70, BIT(7), 0); /*Concurrent CCA at LSB & USB*/ + odm_set_bb_reg(dm, 0xa74, BIT(8), 0); /*RX path diversity enable*/ + odm_set_bb_reg(dm, 0xa14, BIT(7), 0); /*r_en_mrc_antsel*/ + odm_set_bb_reg(dm, 0xa20, (BIT(5) | BIT(4)), 1); /*MBC weighting*/ + + if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) { + odm_set_bb_reg(dm, 0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/ + /**/ + } else if (dm->support_ic_type & ODM_RTL8814A) { + odm_set_bb_reg(dm, 0xa84, BIT(28), 1); /*2R CCA only*/ + /**/ + } +#endif +} + +void +phydm_config_cck_rx_path( + void *dm_void, + enum bb_path path +) +{ +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 path_div_select = 0; + u8 cck_path[2] = {0}; + u8 en_2R_path = 0; + u8 en_2R_mrc = 0; + u8 i = 0, j =0; + u8 num_enable_path = 0; + u8 cck_mrc_max_path = 2; + + for (i = 0; i < 4; i++) { + if (path & BIT(i)) { /*ex: PHYDM_ABCD*/ + num_enable_path++; + cck_path[j] = i; + j++; + } + if (num_enable_path >= cck_mrc_max_path) + break; + } + + if (num_enable_path > 1) { + path_div_select = 1; + en_2R_path = 1; + en_2R_mrc = 1; + } else { + path_div_select = 0; + en_2R_path = 0; + en_2R_mrc = 0; + } + + odm_set_bb_reg(dm, 0xa04, (BIT(27) | BIT(26)), cck_path[0]); /*CCK_1 input signal path*/ + odm_set_bb_reg(dm, 0xa04, (BIT(25) | BIT(24)), cck_path[1]); /*CCK_2 input signal path*/ + odm_set_bb_reg(dm, 0xa74, BIT(8), path_div_select); /*enable Rx path diversity*/ + odm_set_bb_reg(dm, 0xa2c, BIT(18), en_2R_path); /*enable 2R Rx path*/ + odm_set_bb_reg(dm, 0xa2c, BIT(22), en_2R_mrc); /*enable 2R MRC*/ + +#endif +} + +void +phydm_config_cck_tx_path( + void *dm_void, + enum bb_path path +) +{ +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (path == BB_PATH_A) + odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x8); + else if (path == BB_PATH_B) + odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x4); + else if (path == BB_PATH_AB) + odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0xc); +#endif +} + +void +phydm_config_trx_path( + void *dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + /* + dm_value[0]: 0:CCK, 1:OFDM + dm_value[1]: 1:TX, 2:RX + dm_value[2]: 1:path_A, 2:path_B, 3:path_AB + */ + + /* CCK */ + if (dm_value[0] == 0) { + if (dm_value[1] == 1) { /*TX*/ + if (dm_value[2] == 1) + phydm_config_cck_tx_path(dm, BB_PATH_A); + else if (dm_value[2] == 2) + phydm_config_cck_tx_path(dm, BB_PATH_B); + else if (dm_value[2] == 3) + phydm_config_cck_tx_path(dm, BB_PATH_AB); + } else if (dm_value[1] == 2) { /*RX*/ + + phydm_config_cck_rx_antenna_init(dm); + + if (dm_value[2] == 1) + phydm_config_cck_rx_path(dm, BB_PATH_A); + else if (dm_value[2] == 2) + phydm_config_cck_rx_path(dm, BB_PATH_B); + else if (dm_value[2] == 3) { + phydm_config_cck_rx_path(dm, BB_PATH_AB); + } + } + } + /* OFDM */ + else if (dm_value[0] == 1) { + if (dm_value[1] == 1) { /*TX*/ + phydm_config_ofdm_tx_path(dm, dm_value[2]); + /**/ + } else if (dm_value[1] == 2) { /*RX*/ + phydm_config_ofdm_rx_path(dm, dm_value[2]); + /**/ + } + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n", + (dm_value[0] == 1) ? "OFDM" : "CCK", + (dm_value[1] == 1) ? "TX" : "RX", + (dm_value[2] & 0x1) ? "A" : "", + (dm_value[2] & 0x2) ? "B" : "", + (dm_value[2] & 0x4) ? "C" : "", + (dm_value[2] & 0x8) ? "D" : "" + ); + +} + +void +phydm_tx_2path( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__); + +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) { + phydm_api_trx_mode(dm, BB_PATH_AB, (enum bb_path)dm->rx_ant_status, true); + } +#endif + +#if (RTL8812A_SUPPORT == 1 || RTL8192E_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) { + phydm_config_cck_tx_path(dm, BB_PATH_AB); + phydm_config_ofdm_tx_path(dm, BB_PATH_AB); + } +#endif +} + +void +phydm_stop_3_wire( + void *dm_void, + u8 set_type +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (set_type == PHYDM_SET) { + /*[Stop 3-wires]*/ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, 0xc00, 0xf, 0x4);/* hardware 3-wire off */ + odm_set_bb_reg(dm, 0xe00, 0xf, 0x4);/* hardware 3-wire off */ + } else { + odm_set_bb_reg(dm, 0x88c, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ + } + + } else { /*if (set_type == PHYDM_REVERT)*/ + + /*[Start 3-wires]*/ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, 0xc00, 0xf, 0x7);/* hardware 3-wire on */ + odm_set_bb_reg(dm, 0xe00, 0xf, 0x7);/* hardware 3-wire on */ + } else { + odm_set_bb_reg(dm, 0x88c, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ + } + } +} + +u8 +phydm_stop_ic_trx( + void *dm_void, + u8 set_type + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_api_stuc *api = &dm->api_table; + u32 i; + u8 trx_idle_success = false; + u32 dbg_port_value = 0; + + if (set_type == PHYDM_SET) { + /*[Stop TRX]---------------------------------------------------------------------*/ + if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3, 0x0) == false) /*set debug port to 0x0*/ + return PHYDM_SET_FAIL; + + for (i = 0; i<10000; i++) { + dbg_port_value = phydm_get_bb_dbg_port_value(dm); + if ((dbg_port_value & (BIT(17) | BIT(3))) == 0) /* PHYTXON && CCA_all */ { + PHYDM_DBG(dm, ODM_COMP_API, "PSD wait for ((%d)) times\n", i); + + trx_idle_success = true; + break; + } + } + phydm_release_bb_dbg_port(dm); + + if (trx_idle_success) { + api->tx_queue_bitmap = (u8)odm_get_bb_reg(dm, 0x520, 0xff0000); + + odm_set_bb_reg(dm, 0x520, 0xff0000, 0xff); /*pause all TX queue*/ + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, 0x808, BIT(28), 0); /*disable CCK block*/ + odm_set_bb_reg(dm, 0x838, BIT(1), 1); /*disable OFDM RX CCA*/ + } else { + /*TBD*/ + odm_set_bb_reg(dm, 0x800, BIT(24), 0); /* disable whole CCK block */ + + + api->rx_iqc_reg_1 = odm_get_bb_reg(dm, 0xc14, MASKDWORD); + api->rx_iqc_reg_2 = odm_get_bb_reg(dm, 0xc1c, MASKDWORD); + + odm_set_bb_reg(dm, 0xc14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */ + odm_set_bb_reg(dm, 0xc1c, MASKDWORD, 0x0); + } + + } else { + return PHYDM_SET_FAIL; + } + + return PHYDM_SET_SUCCESS; + + } else { /*if (set_type == PHYDM_REVERT)*/ + + odm_set_bb_reg(dm, 0x520, 0xff0000, (u32)(api->tx_queue_bitmap)); /*Release all TX queue*/ + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, 0x808, BIT(28), 1); /*enable CCK block*/ + odm_set_bb_reg(dm, 0x838, BIT(1), 0); /*enable OFDM RX CCA*/ + } else { + /*TBD*/ + odm_set_bb_reg(dm, 0x800, BIT(24), 1); /* enable whole CCK block */ + + odm_set_bb_reg(dm, 0xc14, MASKDWORD, api->rx_iqc_reg_1); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */ + odm_set_bb_reg(dm, 0xc1c, MASKDWORD, api->rx_iqc_reg_2); + } + + return PHYDM_SET_SUCCESS; + } + +} + +void +phydm_set_ext_switch( + void *dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 ext_ant_switch = dm_value[0]; + +#if (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { + /*Output Pin Settings*/ + odm_set_mac_reg(dm, 0x4C, BIT(23), 0); /*select DPDT_P and DPDT_N as output pin*/ + odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /*by WLAN control*/ + + odm_set_bb_reg(dm, 0xCB4, 0xFF, 77); /*DPDT_N = 1b'0*/ /*DPDT_P = 1b'0*/ + + if (ext_ant_switch == MAIN_ANT) { + odm_set_bb_reg(dm, 0xCB4, (BIT(29) | BIT(28)), 1); + PHYDM_DBG(dm, ODM_COMP_API, "***8821A set ant switch = 2b'01 (Main)\n"); + } else if (ext_ant_switch == AUX_ANT) { + odm_set_bb_reg(dm, 0xCB4, BIT(29) | BIT(28), 2); + PHYDM_DBG(dm, ODM_COMP_API, "***8821A set ant switch = 2b'10 (Aux)\n"); + } + } +#endif +} + +void +phydm_csi_mask_enable( + void *dm_void, + u32 enable +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_value = 0; + + reg_value = (enable == FUNC_ENABLE) ? 1 : 0; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, 0xD2C, BIT(28), reg_value); + PHYDM_DBG(dm, ODM_COMP_API, "Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", reg_value); + + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, 0x874, BIT(0), reg_value); + PHYDM_DBG(dm, ODM_COMP_API, "Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", reg_value); + } + +} + +void +phydm_clean_all_csi_mask( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, 0xD40, MASKDWORD, 0); + odm_set_bb_reg(dm, 0xD44, MASKDWORD, 0); + odm_set_bb_reg(dm, 0xD48, MASKDWORD, 0); + odm_set_bb_reg(dm, 0xD4c, MASKDWORD, 0); + + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, 0x880, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x884, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x888, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x88c, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x890, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x894, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x898, MASKDWORD, 0); + odm_set_bb_reg(dm, 0x89c, MASKDWORD, 0); + } +} + +void +phydm_set_csi_mask_reg( + void *dm_void, + u32 tone_idx_tmp, + u8 tone_direction +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 byte_offset, bit_offset; + u32 target_reg; + u8 reg_tmp_value; + u32 tone_num = 64; + u32 tone_num_shift = 0; + u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0; + + /* calculate real tone idx*/ + if ((tone_idx_tmp % 10) >= 5) + tone_idx_tmp += 10; + + tone_idx_tmp = (tone_idx_tmp / 10); + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + tone_num = 64; + csi_mask_reg_p = 0xD40; + csi_mask_reg_n = 0xD48; + + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + tone_num = 128; + csi_mask_reg_p = 0x880; + csi_mask_reg_n = 0x890; + } + + if (tone_direction == FREQ_POSITIVE) { + if (tone_idx_tmp >= (tone_num - 1)) + tone_idx_tmp = (tone_num - 1); + + byte_offset = (u8)(tone_idx_tmp >> 3); + bit_offset = (u8)(tone_idx_tmp & 0x7); + target_reg = csi_mask_reg_p + byte_offset; + + } else { + tone_num_shift = tone_num; + + if (tone_idx_tmp >= tone_num) + tone_idx_tmp = tone_num; + + tone_idx_tmp = tone_num - tone_idx_tmp; + + byte_offset = (u8)(tone_idx_tmp >> 3); + bit_offset = (u8)(tone_idx_tmp & 0x7); + target_reg = csi_mask_reg_n + byte_offset; + } + + reg_tmp_value = odm_read_1byte(dm, target_reg); + PHYDM_DBG(dm, ODM_COMP_API, "Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value); + reg_tmp_value |= BIT(bit_offset); + odm_write_1byte(dm, target_reg, reg_tmp_value); + PHYDM_DBG(dm, ODM_COMP_API, "New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value); +} + +void +phydm_set_nbi_reg( + void *dm_void, + u32 tone_idx_tmp, + u32 bw +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 nbi_table_128[NBI_TABLE_SIZE_128] = {25, 55, 85, 115, 135, 155, 185, 205, 225, 245, /*1~10*/ /*tone_idx X 10*/ + 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/ + 485, 505, 525, 555, 585, 615, 635 + }; /*21~27*/ + + u32 nbi_table_256[NBI_TABLE_SIZE_256] = { 25, 55, 85, 115, 135, 155, 175, 195, 225, 245, /*1~10*/ + 265, 285, 305, 325, 345, 365, 385, 405, 425, 445, /*11~20*/ + 465, 485, 505, 525, 545, 565, 585, 605, 625, 645, /*21~30*/ + 665, 695, 715, 735, 755, 775, 795, 815, 835, 855, /*31~40*/ + 875, 895, 915, 935, 955, 975, 995, 1015, 1035, 1055, /*41~50*/ + 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275 + }; /*51~59*/ + + u32 reg_idx = 0; + u32 i; + u8 nbi_table_idx = FFT_128_TYPE; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) + + nbi_table_idx = FFT_128_TYPE; + else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) + + nbi_table_idx = FFT_256_TYPE; + else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) { + if (bw == 80) + nbi_table_idx = FFT_256_TYPE; + else /*20M, 40M*/ + nbi_table_idx = FFT_128_TYPE; + } + + if (nbi_table_idx == FFT_128_TYPE) { + for (i = 0; i < NBI_TABLE_SIZE_128; i++) { + if (tone_idx_tmp < nbi_table_128[i]) { + reg_idx = i + 1; + break; + } + } + + } else if (nbi_table_idx == FFT_256_TYPE) { + for (i = 0; i < NBI_TABLE_SIZE_256; i++) { + if (tone_idx_tmp < nbi_table_256[i]) { + reg_idx = i + 1; + break; + } + } + } + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, 0xc40, 0x1f000000, reg_idx); + PHYDM_DBG(dm, ODM_COMP_API, "Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", reg_idx); + /**/ + } else { + odm_set_bb_reg(dm, 0x87c, 0xfc000, reg_idx); + PHYDM_DBG(dm, ODM_COMP_API, "Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", reg_idx); + /**/ + } +} + + +void +phydm_nbi_enable( + void *dm_void, + u32 enable +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_value = 0; + + reg_value = (enable == FUNC_ENABLE) ? 1 : 0; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, 0xc40, BIT(9), reg_value); + PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value); + + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (dm->support_ic_type & (ODM_RTL8822B|ODM_RTL8821C)) { + odm_set_bb_reg(dm, 0x87c, BIT(13), reg_value); + odm_set_bb_reg(dm, 0xc20, BIT(28), reg_value); + if (dm->rf_type > RF_1T1R) + odm_set_bb_reg(dm, 0xe20, BIT(28), reg_value); + } else + odm_set_bb_reg(dm, 0x87c, BIT(13), reg_value); + PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value); + } +} + +u8 +phydm_calculate_fc( + void *dm_void, + u32 channel, + u32 bw, + u32 second_ch, + u32 *fc_in +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = *fc_in; + u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173}; + u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, 149, 165}; + u32 *start_ch = &start_ch_per_40m[0]; + u32 num_start_channel = NUM_START_CH_40M; + u32 channel_offset = 0; + u32 i; + + /*2.4G*/ + if (channel <= 14 && channel > 0) { + if (bw == 80) + return PHYDM_SET_FAIL; + + fc = 2412 + (channel - 1) * 5; + + if (bw == 40 && (second_ch == PHYDM_ABOVE)) { + if (channel >= 10) { + PHYDM_DBG(dm, ODM_COMP_API, "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch); + return PHYDM_SET_FAIL; + } + fc += 10; + } else if (bw == 40 && (second_ch == PHYDM_BELOW)) { + if (channel <= 2) { + PHYDM_DBG(dm, ODM_COMP_API, "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch); + return PHYDM_SET_FAIL; + } + fc -= 10; + } + } + /*5G*/ + else if (channel >= 36 && channel <= 177) { + if (bw != 20) { + if (bw == 40) { + num_start_channel = NUM_START_CH_40M; + start_ch = &start_ch_per_40m[0]; + channel_offset = CH_OFFSET_40M; + } else if (bw == 80) { + num_start_channel = NUM_START_CH_80M; + start_ch = &start_ch_per_80m[0]; + channel_offset = CH_OFFSET_80M; + } + + for (i = 0; i < (num_start_channel - 1); i++) { + if (channel < start_ch[i + 1]) { + channel = start_ch[i] + channel_offset; + break; + } + } + PHYDM_DBG(dm, ODM_COMP_API, "Mod_CH = ((%d))\n", channel); + } + + fc = 5180 + (channel - 36) * 5; + + } else { + PHYDM_DBG(dm, ODM_COMP_API, "CH = ((%d)) Error setting\n", channel); + return PHYDM_SET_FAIL; + } + + *fc_in = fc; + + return PHYDM_SET_SUCCESS; +} + + +u8 +phydm_calculate_intf_distance( + void *dm_void, + u32 bw, + u32 fc, + u32 f_interference, + u32 *tone_idx_tmp_in +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 bw_up, bw_low; + u32 int_distance; + u32 tone_idx_tmp; + u8 set_result = PHYDM_SET_NO_NEED; + + bw_up = fc + bw / 2; + bw_low = fc - bw / 2; + + PHYDM_DBG(dm, ODM_COMP_API, "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, fc, bw_up, f_interference); + + if ((f_interference >= bw_low) && (f_interference <= bw_up)) { + int_distance = (fc >= f_interference) ? (fc - f_interference) : (f_interference - fc); + tone_idx_tmp = (int_distance << 5); /* =10*(int_distance /0.3125) */ + PHYDM_DBG(dm, ODM_COMP_API, "int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", int_distance, (tone_idx_tmp / 10), (tone_idx_tmp % 10)); + *tone_idx_tmp_in = tone_idx_tmp; + set_result = PHYDM_SET_SUCCESS; + } + + return set_result; + +} + + +u8 +phydm_csi_mask_setting( + void *dm_void, + u32 enable, + u32 channel, + u32 bw, + u32 f_interference, + u32 second_ch +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = 2412; + u8 tone_direction; + u32 tone_idx_tmp; + u8 set_result = PHYDM_SET_SUCCESS; + + if (enable == FUNC_DISABLE) { + set_result = PHYDM_SET_SUCCESS; + phydm_clean_all_csi_mask(dm); + + } else { + PHYDM_DBG(dm, ODM_COMP_API, "[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, (((bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L")); + + /*calculate fc*/ + if (phydm_calculate_fc(dm, channel, bw, second_ch, &fc) == PHYDM_SET_FAIL) + set_result = PHYDM_SET_FAIL; + + else { + /*calculate interference distance*/ + if (phydm_calculate_intf_distance(dm, bw, fc, f_interference, &tone_idx_tmp) == PHYDM_SET_SUCCESS) { + tone_direction = (f_interference >= fc) ? FREQ_POSITIVE : FREQ_NEGATIVE; + phydm_set_csi_mask_reg(dm, tone_idx_tmp, tone_direction); + set_result = PHYDM_SET_SUCCESS; + } else + set_result = PHYDM_SET_NO_NEED; + } + } + + if (set_result == PHYDM_SET_SUCCESS) + phydm_csi_mask_enable(dm, enable); + else + phydm_csi_mask_enable(dm, FUNC_DISABLE); + + return set_result; +} + +u8 +phydm_nbi_setting( + void *dm_void, + u32 enable, + u32 channel, + u32 bw, + u32 f_interference, + u32 second_ch +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = 2412; + u32 tone_idx_tmp; + u8 set_result = PHYDM_SET_SUCCESS; + + if (enable == FUNC_DISABLE) + set_result = PHYDM_SET_SUCCESS; + + else { + PHYDM_DBG(dm, ODM_COMP_API, "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L")); + + /*calculate fc*/ + if (phydm_calculate_fc(dm, channel, bw, second_ch, &fc) == PHYDM_SET_FAIL) + set_result = PHYDM_SET_FAIL; + + else { + /*calculate interference distance*/ + if (phydm_calculate_intf_distance(dm, bw, fc, f_interference, &tone_idx_tmp) == PHYDM_SET_SUCCESS) { + phydm_set_nbi_reg(dm, tone_idx_tmp, bw); + set_result = PHYDM_SET_SUCCESS; + } else + set_result = PHYDM_SET_NO_NEED; + } + } + + if (set_result == PHYDM_SET_SUCCESS) + phydm_nbi_enable(dm, enable); + else + phydm_nbi_enable(dm, FUNC_DISABLE); + + return set_result; +} + +void +phydm_api_debug( + void *dm_void, + u32 function_map, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 channel = dm_value[1]; + u32 bw = dm_value[2]; + u32 f_interference = dm_value[3]; + u32 second_ch = dm_value[4]; + u8 set_result = 0; + + /*PHYDM_API_NBI*/ + /*-------------------------------------------------------------------------------------------------------------------------------*/ + if (function_map == PHYDM_API_NBI) { + if (dm_value[0] == 100) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n"); + return; + + } else if (dm_value[0] == FUNC_ENABLE) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, + ((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : ((second_ch == PHYDM_ABOVE) ? "H" : "L")); + set_result = phydm_nbi_setting(dm, FUNC_ENABLE, channel, bw, f_interference, second_ch); + + } else if (dm_value[0] == FUNC_DISABLE) { + PDM_SNPF(out_len, used, output + used, + out_len - used, "[Disable NBI]\n"); + set_result = phydm_nbi_setting(dm, FUNC_DISABLE, channel, bw, f_interference, second_ch); + + } else + + set_result = PHYDM_SET_FAIL; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[NBI set result: %s]\n", + (set_result == PHYDM_SET_SUCCESS) ? "Success" : ((set_result == PHYDM_SET_NO_NEED) ? "No need" : "Error")); + + } + + /*PHYDM_CSI_MASK*/ + /*-------------------------------------------------------------------------------------------------------------------------------*/ + else if (function_map == PHYDM_API_CSI_MASK) { + if (dm_value[0] == 100) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n"); + return; + + } else if (dm_value[0] == FUNC_ENABLE) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, + (channel > 14) ? "Don't care" : (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "H" : "L")); + set_result = phydm_csi_mask_setting(dm, FUNC_ENABLE, channel, bw, f_interference, second_ch); + + } else if (dm_value[0] == FUNC_DISABLE) { + PDM_SNPF(out_len, used, output + used, + out_len - used, "[Disable CSI MASK]\n"); + set_result = phydm_csi_mask_setting(dm, FUNC_DISABLE, channel, bw, f_interference, second_ch); + + } else + + set_result = PHYDM_SET_FAIL; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[CSI MASK set result: %s]\n", + (set_result == PHYDM_SET_SUCCESS) ? "Success" : ((set_result == PHYDM_SET_NO_NEED) ? "No need" : "Error")); + } + *_used = used; + *_out_len = out_len; +} + +void +phydm_stop_ck320( + void *dm_void, + u8 enable +) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_value = enable ? 1 : 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, 0x8b4, BIT(6), reg_value); + /**/ + } else { + + if (dm->support_ic_type & ODM_IC_N_2SS) { /*N-2SS*/ + odm_set_bb_reg(dm, 0x87c, BIT(29), reg_value); + /**/ + } else { /*N-1SS*/ + odm_set_bb_reg(dm, 0x87c, BIT(31), reg_value); + /**/ + } + } +} + +boolean +phydm_set_bb_txagc_offset( + void *dm_void, + s8 power_offset, /*(unit: dB)*/ + u8 add_half_db /*(+0.5 dB)*/ +) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + s8 power_idx = power_offset * 2; + boolean set_success = false; + + PHYDM_DBG(dm, ODM_COMP_API, "power_offset=%d, add_half_db =%d\n", power_offset, add_half_db); + + #if ODM_IC_11AC_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (power_offset > -16 || power_offset < 15) { + if (add_half_db) + power_idx += 1; + + power_idx &= 0x3f; + + PHYDM_DBG(dm, ODM_COMP_API, "Reg_idx =0x%x\n", power_idx); + odm_set_bb_reg(dm, 0x8b4, 0x3f, power_idx); + set_success = true; + } else { + pr_debug("[Warning] TX AGC Offset Setting error!"); + } + } + #endif + + #if ODM_IC_11N_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (power_offset > -8 || power_offset < 7) { + if (add_half_db) + power_idx += 1; + + power_idx &= 0x1f; + + PHYDM_DBG(dm, ODM_COMP_API, "Reg_idx =0x%x\n", power_idx); + odm_set_bb_reg(dm, 0x80c, 0x1f00, power_idx); + odm_set_bb_reg(dm, 0x80c, 0x3e000, power_idx); + set_success = true; + } else { + pr_debug("[Warning] TX AGC Offset Setting error!"); + } + } + #endif + + return set_success; +} + +#ifdef PHYDM_COMMON_API_SUPPORT +boolean +phydm_api_set_txagc( + void *dm_void, + u32 power_index, + enum rf_path path, + u8 hw_rate, + boolean is_single_rate +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; + u8 i; + +#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + if (is_single_rate) { + + #if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) + ret = phydm_write_txagc_1byte_8822b(dm, power_index, path, hw_rate); + #endif + + #if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821C) + ret = phydm_write_txagc_1byte_8821c(dm, power_index, path, hw_rate); + #endif + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + set_current_tx_agc(dm->priv, path, hw_rate, (u8)power_index); + #endif + + } else { + #if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) + ret = config_phydm_write_txagc_8822b(dm, power_index, path, hw_rate); + #endif + + #if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821C) + ret = config_phydm_write_txagc_8821c(dm, power_index, path, hw_rate); + #endif + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + for (i = 0; i < 4; i++) + set_current_tx_agc(dm->priv, path, (hw_rate + i), (u8)power_index); + #endif + } + } +#endif + + +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_write_txagc_8197f(dm, power_index, path, hw_rate); +#endif + + return ret; +} + +u8 +phydm_api_get_txagc( + void *dm_void, + enum rf_path path, + u8 hw_rate +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ret = 0; + +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8822B) + ret = config_phydm_read_txagc_8822b(dm, path, hw_rate); +#endif + +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_read_txagc_8197f(dm, path, hw_rate); +#endif + +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821C) + ret = config_phydm_read_txagc_8821c(dm, path, hw_rate); +#endif + + return ret; +} + + +boolean +phydm_api_switch_bw_channel( + void *dm_void, + u8 central_ch, + u8 primary_ch_idx, + enum channel_width bandwidth +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; + +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8822B) + ret = config_phydm_switch_channel_bw_8822b(dm, central_ch, primary_ch_idx, bandwidth); +#endif + +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_switch_channel_bw_8197f(dm, central_ch, primary_ch_idx, bandwidth); +#endif + +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821C) + ret = config_phydm_switch_channel_bw_8821c(dm, central_ch, primary_ch_idx, bandwidth); +#endif + + return ret; +} + +boolean +phydm_api_trx_mode( + void *dm_void, + enum bb_path tx_path, + enum bb_path rx_path, + boolean is_tx2_path +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; + +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8822B) + ret = config_phydm_trx_mode_8822b(dm, tx_path, rx_path, is_tx2_path); +#endif + +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_trx_mode_8197f(dm, tx_path, rx_path, is_tx2_path); +#endif + + return ret; +} +#endif + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void +phydm_normal_driver_rx_sniffer( + struct dm_struct *dm, + u8 *desc, + PRT_RFD_STATUS rt_rfd_status, + u8 *drv_info, + u8 phy_status +) +{ +#if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING)) + u32 *msg; + u16 seq_num; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + if (rt_rfd_status->packet_report_type != NORMAL_RX) + return; + + if (!dm->is_linked) { + if (rt_rfd_status->is_hw_error) + return; + } + + if (!(fat_tab->fat_state == FAT_TRAINING_STATE)) + return; + + if (phy_status == true) { + if ((dm->rx_pkt_type == type_block_ack) || (dm->rx_pkt_type == type_rts) || (dm->rx_pkt_type == type_cts)) + seq_num = 0; + else + seq_num = rt_rfd_status->seq_num; + + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, "%04d , %01s, rate=0x%02x, L=%04d , %s , %s", + seq_num, + /*rt_rfd_status->mac_id,*/ + ((rt_rfd_status->is_crc) ? "C" : (rt_rfd_status->is_ampdu) ? "A" : "_"), + rt_rfd_status->data_rate, + rt_rfd_status->length, + ((rt_rfd_status->band_width == 0) ? "20M" : ((rt_rfd_status->band_width == 1) ? "40M" : "80M")), + ((rt_rfd_status->is_ldpc) ? "LDP" : "BCC")); + + if (dm->rx_pkt_type == type_asoc_req) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_REQ"); + /**/ + } else if (dm->rx_pkt_type == type_asoc_rsp) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_RSP"); + /**/ + } else if (dm->rx_pkt_type == type_probe_req) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_REQ"); + /**/ + } else if (dm->rx_pkt_type == type_probe_rsp) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_RSP"); + /**/ + } else if (dm->rx_pkt_type == type_deauth) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "DEAUTH"); + /**/ + } else if (dm->rx_pkt_type == type_beacon) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BEACON"); + /**/ + } else if (dm->rx_pkt_type == type_block_ack_req) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BA_REQ"); + /**/ + } else if (dm->rx_pkt_type == type_rts) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__RTS_"); + /**/ + } else if (dm->rx_pkt_type == type_cts) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__CTS_"); + /**/ + } else if (dm->rx_pkt_type == type_ack) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__ACK_"); + /**/ + } else if (dm->rx_pkt_type == type_block_ack) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__BA__"); + /**/ + } else if (dm->rx_pkt_type == type_data) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "_DATA_"); + /**/ + } else if (dm->rx_pkt_type == type_data_ack) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "Data_Ack"); + /**/ + } else if (dm->rx_pkt_type == type_qos_data) { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "QoS_Data"); + /**/ + } else { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [0x%x]", dm->rx_pkt_type); + /**/ + } + + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [RSSI=%d,%d,%d,%d ]", + dm->rssi_a, + dm->rssi_b, + dm->rssi_c, + dm->rssi_d); + + msg = (u32 *)drv_info; + + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n", + msg[6], msg[5], msg[4], msg[3], msg[2], msg[1], msg[1]); + } else { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, "%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n", + rt_rfd_status->seq_num, + /*rt_rfd_status->mac_id,*/ + ((rt_rfd_status->is_crc) ? "C" : (rt_rfd_status->is_ampdu) ? "A" : "_"), + rt_rfd_status->data_rate, + rt_rfd_status->length, + ((rt_rfd_status->band_width == 0) ? "20M" : ((rt_rfd_status->band_width == 1) ? "40M" : "80M")), + ((rt_rfd_status->is_ldpc) ? "LDP" : "BCC")); + } + + +#endif +} +#endif + diff --git a/hal/phydm/phydm_api.h b/hal/phydm/phydm_api.h new file mode 100644 index 0000000..69ac533 --- /dev/null +++ b/hal/phydm/phydm_api.h @@ -0,0 +1,250 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + + +#ifndef __PHYDM_API_H__ +#define __PHYDM_API_H__ + +#define PHYDM_API_VERSION "1.0" /* 2017.07.10 Dino, Add phydm_api.h*/ + + +/* 1 ============================================================ + * 1 Definition + * 1 ============================================================ */ + + +#define FUNC_ENABLE 1 +#define FUNC_DISABLE 2 + +/*NBI API------------------------------------*/ +#define NBI_TABLE_SIZE_128 27 +#define NBI_TABLE_SIZE_256 59 + +#define NUM_START_CH_80M 7 +#define NUM_START_CH_40M 14 + +#define CH_OFFSET_40M 2 +#define CH_OFFSET_80M 6 + +#define FFT_128_TYPE 1 +#define FFT_256_TYPE 2 + +#define FREQ_POSITIVE 1 +#define FREQ_NEGATIVE 2 +/*------------------------------------------------*/ + +/* 1 ============================================================ + * 1 structure + * 1 ============================================================ */ + +struct phydm_api_stuc { + u32 rx_iqc_reg_1; /*N-mode: for pathA REG0xc14*/ + u32 rx_iqc_reg_2; /*N-mode: for pathB REG0xc1c*/ + u8 tx_queue_bitmap;/*REG0x520[23:16]*/ + +}; + +/* 1 ============================================================ + * 1 enumeration + * 1 ============================================================ */ + + + +/* 1 ============================================================ + * 1 function prototype + * 1 ============================================================ */ + +void +phydm_dynamic_ant_weighting( + void *dm_void +); + +#ifdef DYN_ANT_WEIGHTING_SUPPORT +void +phydm_dyn_ant_weight_dbg( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); +#endif + +void +phydm_pathb_q_matrix_rotate_en( + void *dm_void +); + +void +phydm_pathb_q_matrix_rotate( + void *dm_void, + u16 phase_idx +); + +void +phydm_init_trx_antenna_setting( + void *dm_void +); + +void +phydm_config_ofdm_rx_path( + void *dm_void, + u32 path +); + +void +phydm_config_cck_rx_path( + void *dm_void, + enum bb_path path +); + +void +phydm_config_cck_rx_antenna_init( + void *dm_void +); + +void +phydm_config_trx_path( + void *dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +void +phydm_tx_2path( + void *dm_void +); + +void +phydm_stop_3_wire( + void *dm_void, + u8 set_type +); + +u8 +phydm_stop_ic_trx( + void *dm_void, + u8 set_type +); + +void +phydm_set_ext_switch( + void *dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +void +phydm_nbi_enable( + void *dm_void, + u32 enable +); + +u8 +phydm_csi_mask_setting( + void *dm_void, + u32 enable, + u32 channel, + u32 bw, + u32 f_interference, + u32 Second_ch +); + +u8 +phydm_nbi_setting( + void *dm_void, + u32 enable, + u32 channel, + u32 bw, + u32 f_interference, + u32 second_ch +); + + +void +phydm_api_debug( + void *dm_void, + u32 function_map, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +void +phydm_stop_ck320( + void *dm_void, + u8 enable +); + +boolean +phydm_set_bb_txagc_offset( + void *dm_void, + s8 power_offset, + u8 add_half_db +); + +#ifdef PHYDM_COMMON_API_SUPPORT + +boolean +phydm_api_set_txagc( + void *dm_void, + u32 power_index, + enum rf_path path, + u8 hw_rate, + boolean is_single_rate +); + +u8 +phydm_api_get_txagc( + void *dm_void, + enum rf_path path, + u8 hw_rate +); + +boolean +phydm_api_switch_bw_channel( + void *dm_void, + u8 central_ch, + u8 primary_ch_idx, + enum channel_width bandwidth +); + +boolean +phydm_api_trx_mode( + void *dm_void, + enum bb_path tx_path, + enum bb_path rx_path, + boolean is_tx2_path +); + +#endif + +#endif diff --git a/hal/phydm/phydm_auto_dbg.c b/hal/phydm/phydm_auto_dbg.c new file mode 100644 index 0000000..b907661 --- /dev/null +++ b/hal/phydm/phydm_auto_dbg.c @@ -0,0 +1,682 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_AUTO_DEGBUG + +void +phydm_check_hang_reset( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table; + + atd_t->dbg_step = 0; + atd_t->auto_dbg_type = AUTO_DBG_STOP; + phydm_pause_dm_watchdog(dm, PHYDM_RESUME); + dm->debug_components &= (~ODM_COMP_API); +} + +#if (ODM_IC_11N_SERIES_SUPPORT == 1) +void +phydm_auto_check_hang_engine_n( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table; + struct n_dbgport_803 dbgport_803 = {0}; + u32 value32_tmp = 0, value32_tmp_2 = 0; + u8 i; + u32 curr_dbg_port_val[DBGPORT_CHK_NUM]; + u16 curr_ofdm_t_cnt; + u16 curr_ofdm_r_cnt; + u16 curr_cck_t_cnt; + u16 curr_cck_r_cnt; + u16 curr_ofdm_crc_error_cnt; + u16 curr_cck_crc_error_cnt; + u16 diff_ofdm_t_cnt; + u16 diff_ofdm_r_cnt; + u16 diff_cck_t_cnt; + u16 diff_cck_r_cnt; + u16 diff_ofdm_crc_error_cnt; + u16 diff_cck_crc_error_cnt; + u8 rf_mode; + + + if (atd_t->auto_dbg_type == AUTO_DBG_STOP) + return; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + phydm_check_hang_reset(dm); + return; + } + + if (atd_t->dbg_step == 0) { + pr_debug("dbg_step=0\n\n"); + + /*Reset all packet counter*/ + odm_set_bb_reg(dm, 0xf14, BIT(16), 1); + odm_set_bb_reg(dm, 0xf14, BIT(16), 0); + + + + } else if (atd_t->dbg_step == 1) { + pr_debug("dbg_step=1\n\n"); + + /*Check packet counter Register*/ + atd_t->ofdm_t_cnt = (u16)odm_get_bb_reg(dm, 0x9cc, MASKHWORD); + atd_t->ofdm_r_cnt = (u16)odm_get_bb_reg(dm, 0xf94, MASKLWORD); + atd_t->ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, 0xf94, MASKHWORD); + + atd_t->cck_t_cnt = (u16)odm_get_bb_reg(dm, 0x9d0, MASKHWORD);; + atd_t->cck_r_cnt = (u16)odm_get_bb_reg(dm, 0xfa0, MASKHWORD); + atd_t->cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, 0xf84, 0x3fff); + + + /*Check Debug Port*/ + for (i = 0; i < DBGPORT_CHK_NUM; i++) { + + if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3, (u32)atd_t->dbg_port_table[i])) { + atd_t->dbg_port_val[i] = phydm_get_bb_dbg_port_value(dm); + phydm_release_bb_dbg_port(dm); + } + } + + } else if (atd_t->dbg_step == 2) { + pr_debug("dbg_step=2\n\n"); + + /*Check packet counter Register*/ + curr_ofdm_t_cnt = (u16)odm_get_bb_reg(dm, 0x9cc, MASKHWORD); + curr_ofdm_r_cnt = (u16)odm_get_bb_reg(dm, 0xf94, MASKLWORD); + curr_ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, 0xf94, MASKHWORD); + + curr_cck_t_cnt = (u16)odm_get_bb_reg(dm, 0x9d0, MASKHWORD);; + curr_cck_r_cnt = (u16)odm_get_bb_reg(dm, 0xfa0, MASKHWORD); + curr_cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, 0xf84, 0x3fff); + + /*Check Debug Port*/ + for (i = 0; i < DBGPORT_CHK_NUM; i++) { + + if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3, (u32)atd_t->dbg_port_table[i])) { + curr_dbg_port_val[i] = phydm_get_bb_dbg_port_value(dm); + phydm_release_bb_dbg_port(dm); + } + } + + /*=== Make check hang decision ================================*/ + pr_debug("Check Hang Decision\n\n"); + + /* ----- Check RF Register -----------------------------------*/ + for (i = 0; i < dm->num_rf_path; i++) { + + rf_mode = (u8)odm_get_rf_reg(dm, i, 0x0, 0xf0000); + + pr_debug("RF0x0[%d] = 0x%x\n", i, rf_mode); + + if (rf_mode > 3) { + pr_debug("Incorrect RF mode\n"); + pr_debug("ReasonCode:RHN-1\n"); + + + } + } + + value32_tmp = odm_get_rf_reg(dm, 0, 0xb0, 0xf0000); + + if (dm->support_ic_type == ODM_RTL8188E) { + if (value32_tmp != 0xff8c8) { + pr_debug("ReasonCode:RHN-3\n"); + } + } + + /* ----- Check BB Register -----------------------------------*/ + + /*BB mode table*/ + value32_tmp = odm_get_bb_reg(dm, 0x824, 0xe); + value32_tmp_2 = odm_get_bb_reg(dm, 0x82c, 0xe); + pr_debug("BB TX mode table {A, B}= {%d, %d}\n", value32_tmp, value32_tmp_2); + + if ((value32_tmp > 3) || (value32_tmp_2 > 3)) { + + pr_debug("ReasonCode:RHN-2\n"); + } + + value32_tmp = odm_get_bb_reg(dm, 0x824, 0x700000); + value32_tmp_2 = odm_get_bb_reg(dm, 0x82c, 0x700000); + pr_debug("BB RX mode table {A, B}= {%d, %d}\n", value32_tmp, value32_tmp_2); + + if ((value32_tmp > 3) || (value32_tmp_2 > 3)) { + + pr_debug("ReasonCode:RHN-2\n"); + } + + + /*BB HW Block*/ + value32_tmp = odm_get_bb_reg(dm, 0x800, MASKDWORD); + + if (!(value32_tmp & BIT(24))) { + pr_debug("Reg0x800[24] = 0, CCK BLK is disabled\n"); + pr_debug("ReasonCode: THN-3\n"); + } + + if (!(value32_tmp & BIT(25))) { + pr_debug("Reg0x800[24] = 0, OFDM BLK is disabled\n"); + pr_debug("ReasonCode:THN-3\n"); + } + + /*BB Continue TX*/ + value32_tmp = odm_get_bb_reg(dm, 0xd00, 0x70000000); + pr_debug("Continue TX=%d\n", value32_tmp); + if (value32_tmp != 0) { + pr_debug("ReasonCode: THN-4\n"); + } + + + /* ----- Check Packet Counter --------------------------------*/ + diff_ofdm_t_cnt = curr_ofdm_t_cnt - atd_t->ofdm_t_cnt; + diff_ofdm_r_cnt = curr_ofdm_r_cnt - atd_t->ofdm_r_cnt; + diff_ofdm_crc_error_cnt = curr_ofdm_crc_error_cnt - atd_t->ofdm_crc_error_cnt; + + diff_cck_t_cnt = curr_cck_t_cnt - atd_t->cck_t_cnt; + diff_cck_r_cnt = curr_cck_r_cnt - atd_t->cck_r_cnt; + diff_cck_crc_error_cnt = curr_cck_crc_error_cnt - atd_t->cck_crc_error_cnt; + + pr_debug("OFDM[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n", + atd_t->ofdm_t_cnt, atd_t->ofdm_r_cnt, atd_t->ofdm_crc_error_cnt); + pr_debug("OFDM[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n", + curr_ofdm_t_cnt, curr_ofdm_r_cnt, curr_ofdm_crc_error_cnt); + pr_debug("OFDM_diff {TX, RX, CRC_error} = {%d, %d, %d}\n", + diff_ofdm_t_cnt, diff_ofdm_r_cnt, diff_ofdm_crc_error_cnt); + + pr_debug("CCK[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n", + atd_t->cck_t_cnt, atd_t->cck_r_cnt, atd_t->cck_crc_error_cnt); + pr_debug("CCK[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n", + curr_cck_t_cnt, curr_cck_r_cnt, curr_cck_crc_error_cnt); + pr_debug("CCK_diff {TX, RX, CRC_error} = {%d, %d, %d}\n", + diff_cck_t_cnt, diff_cck_r_cnt, diff_cck_crc_error_cnt); + + /* ----- Check Dbg Port --------------------------------*/ + + for (i = 0; i < DBGPORT_CHK_NUM; i++) { + pr_debug("Dbg_port=((0x%x))\n", atd_t->dbg_port_table[i]); + pr_debug("Val{pre, curr}={0x%x, 0x%x}\n", atd_t->dbg_port_val[i], curr_dbg_port_val[i]); + + if ((atd_t->dbg_port_table[i]) == 0) { + if (atd_t->dbg_port_val[i] == curr_dbg_port_val[i]) { + + pr_debug("BB state hang\n"); + pr_debug("ReasonCode:\n"); + } + + } else if (atd_t->dbg_port_table[i] == 0x803) { + if (atd_t->dbg_port_val[i] == curr_dbg_port_val[i]) { + //dbgport_803 = (struct n_dbgport_803 )(atd_t->dbg_port_val[i]); + + odm_move_memory(dm, &dbgport_803, + &atd_t->dbg_port_val[i], + sizeof(struct n_dbgport_803)); + + pr_debug("RSTB{BB, GLB, OFDM}={%d, %d, %d}\n", dbgport_803.bb_rst_b, dbgport_803.glb_rst_b, dbgport_803.ofdm_rst_b); + pr_debug("{ofdm_tx_en, cck_tx_en, phy_tx_on}={%d, %d, %d}\n", dbgport_803.ofdm_tx_en, dbgport_803.cck_tx_en, dbgport_803.phy_tx_on); + pr_debug("CCA_PP{OFDM, CCK}={%d, %d}\n", dbgport_803.ofdm_cca_pp, dbgport_803.cck_cca_pp); + + if (dbgport_803.phy_tx_on) + pr_debug("Maybe TX Hang\n"); + else if (dbgport_803.ofdm_cca_pp || dbgport_803.cck_cca_pp) + pr_debug("Maybe RX Hang\n"); + } + + } else if (atd_t->dbg_port_table[i] == 0x208) { + if ((atd_t->dbg_port_val[i] & BIT(30)) && (curr_dbg_port_val[i] & BIT(30))) { + + pr_debug("EDCCA Pause TX\n"); + pr_debug("ReasonCode: THN-2\n"); + } + + } else if (atd_t->dbg_port_table[i] == 0xab0) { + if (((atd_t->dbg_port_val[i] & 0xffffff) == 0) || + ((curr_dbg_port_val[i] & 0xffffff) == 0)) { + + pr_debug("Wrong L-SIG formate\n"); + pr_debug("ReasonCode: THN-1\n"); + } + } + } + + phydm_check_hang_reset(dm); + } + + atd_t->dbg_step++; + +} + +void +phydm_bb_auto_check_hang_start_n( + void *dm_void, + u32 *_used, + char *output, + u32 *_out_len +) +{ + u32 value32 = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table; + u32 used = *_used; + u32 out_len = *_out_len; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + return; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "PHYDM auto check hang (N-series) is started, Please check the system log\n"); + + dm->debug_components |= ODM_COMP_API; + atd_t->auto_dbg_type = AUTO_DBG_CHECK_HANG; + atd_t->dbg_step = 0; + + + phydm_pause_dm_watchdog(dm, PHYDM_PAUSE); + + + + *_used = used; + *_out_len = out_len; +} + +void +phydm_bb_rx_hang_info_n( + void *dm_void, + u32 *_used, + char *output, + u32 *_out_len +) +{ + u32 value32 = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + return; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "not support now\n"); + + *_used = used; + *_out_len = out_len; +} + +#endif + +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) +void +phydm_bb_rx_hang_info_ac( + void *dm_void, + u32 *_used, + char *output, + u32 *_out_len +) +{ + u32 value32 = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) + return; + + value32 = odm_get_bb_reg(dm, 0xF80, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", + value32); + + if (dm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(dm, 0x198c, BIT(2) | BIT(1) | BIT(0), 7); + + /* dbg_port = basic state machine */ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "basic state machine", + value32); + } + + /* dbg_port = state machine */ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "state machine", value32); + } + + /* dbg_port = CCA-related*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "CCA-related", value32); + } + + + /* dbg_port = edcca/rxd*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "edcca/rxd", value32); + } + + /* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", + "rx_state/mux_state/ADC_MASK_OFDM", value32); + } + + /* dbg_port = bf-related*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "bf-related", value32); + } + + /* dbg_port = bf-related*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "bf-related", value32); + } + + /* dbg_port = txon/rxd*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "txon/rxd", value32); + } + + /* dbg_port = l_rate/l_length*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "l_rate/l_length", + value32); + } + + /* dbg_port = rxd/rxd_hit*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32); + } + + /* dbg_port = dis_cca*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "dis_cca", value32); + } + + + /* dbg_port = tx*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "tx", value32); + } + + /* dbg_port = rx plcp*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rx plcp", value32); + + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rx plcp", value32); + + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rx plcp", value32); + + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rx plcp", value32); + } + *_used = used; + *_out_len = out_len; +} +#endif + +void +phydm_auto_dbg_console( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Show dbg port: {1} {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Auto check hang: {1} {2}\n"); + return; + } else if (var1[0] == 1) { + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); + + if (var1[1] == 1) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + #if (ODM_IC_11AC_SERIES_SUPPORT == 1) + phydm_bb_rx_hang_info_ac(dm, &used, output, &out_len); + #else + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Not support\n"); + #endif + } else { + #if (ODM_IC_11N_SERIES_SUPPORT == 1) + phydm_bb_rx_hang_info_n(dm, &used, output, &out_len); + #else + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Not support\n"); + #endif + } + } else if (var1[1] == 2) { + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Not support\n"); + } else { + #if (ODM_IC_11N_SERIES_SUPPORT == 1) + phydm_bb_auto_check_hang_start_n(dm, &used, output, &out_len); + #else + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Not support\n"); + #endif + } + } + } + + *_used = used; + *_out_len = out_len; +} + + +#endif + +void +phydm_auto_dbg_engine( + void *dm_void +) +{ +#ifdef PHYDM_AUTO_DEGBUG + u32 value32 = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table; + + if (atd_t->auto_dbg_type == AUTO_DBG_STOP) + return; + + pr_debug("%s ======>\n", __func__); + + if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_HANG) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + pr_debug("Not Support\n"); + } else { + #if (ODM_IC_11N_SERIES_SUPPORT == 1) + phydm_auto_check_hang_engine_n(dm); + #else + pr_debug("Not Support\n"); + #endif + } + + } else if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_RA) { + + pr_debug("Not Support\n"); + + } +#endif +} + +void +phydm_auto_dbg_engine_init( + void *dm_void +) +{ +#ifdef PHYDM_AUTO_DEGBUG + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table; + u16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0, 0xab1, 0xab2}; + + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>n", __func__); + + odm_move_memory(dm, &atd_t->dbg_port_table[0], + &dbg_port_table[0], (DBGPORT_CHK_NUM * 2)); + + phydm_check_hang_reset(dm); +#endif +} + + diff --git a/hal/phydm/phydm_auto_dbg.h b/hal/phydm/phydm_auto_dbg.h new file mode 100644 index 0000000..d6ea5b3 --- /dev/null +++ b/hal/phydm/phydm_auto_dbg.h @@ -0,0 +1,124 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + + +#ifndef __PHYDM_AUTO_DBG_H__ +#define __PHYDM_AUTO_DBG_H__ + +#define AUTO_DBG_VERSION "1.0" /* 2017.05.015 Dino, Add phydm_auto_dbg.h*/ + + +/* 1 ============================================================ + * 1 Definition + * 1 ============================================================ */ + +#define AUTO_CHK_HANG_STEP_MAX 3 +#define DBGPORT_CHK_NUM 6 + +#ifdef PHYDM_AUTO_DEGBUG + + +/* 1 ============================================================ + * 1 enumeration + * 1 ============================================================ */ + +enum auto_dbg_type_e{ + AUTO_DBG_STOP = 0, + AUTO_DBG_CHECK_HANG = 1, + AUTO_DBG_CHECK_RA = 2, + AUTO_DBG_CHECK_DIG = 3 +}; + +/* 1 ============================================================ + * 1 structure + * 1 ============================================================ */ + +struct n_dbgport_803 { + /*BYTE 3*/ + u8 bb_rst_b: 1; + u8 glb_rst_b: 1; + u8 zero_1bit_1:1; + u8 ofdm_rst_b: 1; + u8 cck_txpe: 1; + u8 ofdm_txpe: 1; + u8 phy_tx_on: 1; + u8 tdrdy: 1; + /*BYTE 2*/ + u8 txd:8; + /*BYTE 1*/ + u8 cck_cca_pp: 1; + u8 ofdm_cca_pp: 1; + u8 rx_rst: 1; + u8 rdrdy: 1; + u8 rxd_7_4: 4; + /*BYTE 0*/ + u8 rxd_3_0: 4; + u8 ofdm_tx_en: 1; + u8 cck_tx_en: 1; + u8 zero_1bit_2:1; + u8 clk_80m: 1; +}; + +struct phydm_auto_dbg_struc { + enum auto_dbg_type_e auto_dbg_type; + u8 dbg_step; + u16 dbg_port_table[DBGPORT_CHK_NUM]; + u32 dbg_port_val[DBGPORT_CHK_NUM]; + u16 ofdm_t_cnt; + u16 ofdm_r_cnt; + u16 cck_t_cnt; + u16 cck_r_cnt; + u16 ofdm_crc_error_cnt; + u16 cck_crc_error_cnt; + +}; + + +/* 1 ============================================================ + * 1 function prototype + * 1 ============================================================ */ + + +void +phydm_auto_dbg_console( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); +#endif + +void +phydm_auto_dbg_engine( + void *dm_void +); + +void +phydm_auto_dbg_engine_init( + void *dm_void +); +#endif \ No newline at end of file diff --git a/hal/phydm/phydm_cck_pd.c b/hal/phydm/phydm_cck_pd.c new file mode 100644 index 0000000..87b41da --- /dev/null +++ b/hal/phydm/phydm_cck_pd.c @@ -0,0 +1,471 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_SUPPORT_CCKPD + +void +phydm_write_cck_cca_th_new_cs_ratio( + void *dm_void, + u8 cca_th, + u8 cca_th_aaa +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_CCKPD, "[New] pd_th=0x%x, cs_ratio=0x%x\n\n", cca_th, cca_th_aaa); + + if (cckpd_t->cur_cck_cca_thres != cca_th) { + + cckpd_t->cur_cck_cca_thres = cca_th; + odm_set_bb_reg(dm, 0xa08, 0xf0000, cca_th); + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + + } + + if (cckpd_t->cck_cca_th_aaa != cca_th_aaa) { + + cckpd_t->cck_cca_th_aaa = cca_th_aaa; + odm_set_bb_reg(dm, 0xaa8, 0x1f0000, cca_th_aaa); + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + } + +} + +void +phydm_write_cck_cca_th( + void *dm_void, + u8 cca_th +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_CCKPD, "New cck_cca_th=((0x%x))\n\n", cca_th); + + if (cckpd_t->cur_cck_cca_thres != cca_th) { + + odm_write_1byte(dm, ODM_REG(CCK_CCA, dm), cca_th); + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + } + cckpd_t->cur_cck_cca_thres = cca_th; +} + +void +phydm_set_cckpd_val( + void *dm_void, + u32 *val_buf, + u8 val_len +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + + if (val_len != 2) { + PHYDM_DBG(dm, ODM_COMP_API, "[Error][CCKPD]Need val_len=2\n"); + return; + } + + /*val_buf[0]: 0xa0a*/ + /*val_buf[1]: 0xaaa*/ + + if (dm->support_ic_type & EXTEND_CCK_CCATH_AAA_IC) { + phydm_write_cck_cca_th_new_cs_ratio(dm, (u8)val_buf[0], (u8)val_buf[1]); + } else { + phydm_write_cck_cca_th(dm, (u8)val_buf[0]); + } + +} + +boolean +phydm_stop_cck_pd_th( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & (ODM_BB_CCK_PD | ODM_BB_FA_CNT))) { + + PHYDM_DBG(dm, DBG_CCKPD, "Not Support\n"); + + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #ifdef MCR_WIRELESS_EXTEND + phydm_write_cck_cca_th(dm, 0x43); + #endif + #endif + + return true; + } + + if (dm->pause_ability & ODM_BB_CCK_PD) { + + PHYDM_DBG(dm, DBG_CCKPD, "Return: Pause CCKPD in LV=%d\n", dm->pause_lv_table.lv_cckpd); + return true; + } + + #if 0/*(DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))*/ + if (dm->ext_lna) + return true; + #endif + + return false; + +} + +void +phydm_cckpd( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 cur_cck_cca_th= cckpd_t->cur_cck_cca_thres; + + if (dm->is_linked) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + + /*Add hp_hw_id condition due to 22B LPS power consumption issue and [PCIE-1596]*/ + if (dm->hp_hw_id && (dm->traffic_load == TRAFFIC_ULTRA_LOW)) + cur_cck_cca_th = 0x40; + else if (dm->rssi_min > 35) + cur_cck_cca_th = 0xcd; + else if (dm->rssi_min > 20) { + + if (cckpd_t->cck_fa_ma > 500) + cur_cck_cca_th = 0xcd; + else if (cckpd_t->cck_fa_ma < 250) + cur_cck_cca_th = 0x83; + + } else { + if((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) && (cckpd_t->cck_fa_ma > 200)) + cur_cck_cca_th = 0xc3; /*for ASUS OTA test*/ + else + cur_cck_cca_th = 0x83; + } + +#else /*ODM_AP*/ + if (dig_t->cur_ig_value > 0x32) + cur_cck_cca_th = 0xed; + else if (dig_t->cur_ig_value > 0x2a) + cur_cck_cca_th = 0xdd; + else if (dig_t->cur_ig_value > 0x24) + cur_cck_cca_th = 0xcd; + else + cur_cck_cca_th = 0x83; + +#endif + } else { + + if (cckpd_t->cck_fa_ma > 1000) + cur_cck_cca_th = 0x83; + else if (cckpd_t->cck_fa_ma < 500) + cur_cck_cca_th = 0x40; + } + + phydm_write_cck_cca_th(dm, cur_cck_cca_th); + /*PHYDM_DBG(dm, DBG_CCKPD, "New cck_cca_th=((0x%x))\n\n", cur_cck_cca_th);*/ + +} + +void +phydm_cckpd_new_cs_ratio( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 pd_th = 0, cs_ration = 0, cs_2r_offset = 0; + u8 igi_curr = dig_t->cur_ig_value; + u8 en_2rcca; + boolean is_update = true; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + + en_2rcca = (u8)(odm_get_bb_reg(dm, 0xa2c, BIT(18)) && odm_get_bb_reg(dm, 0xa2c, BIT(22))); + + if (dm->is_linked) { + + if ((igi_curr > 0x38) && (dm->rssi_min > 32)) { + cs_ration = dig_t->aaa_default + AAA_BASE + AAA_STEP * 2; + cs_2r_offset = 5; + pd_th = 0xd; + } else if ((igi_curr > 0x2a) && (dm->rssi_min > 32)) { + cs_ration = dig_t->aaa_default + AAA_BASE + AAA_STEP; + cs_2r_offset = 4; + pd_th = 0xd; + } else if ((igi_curr > 0x24) || (dm->rssi_min > 24 && dm->rssi_min <= 30)) { + cs_ration = dig_t->aaa_default + AAA_BASE; + cs_2r_offset = 3; + pd_th = 0xd; + } else if ((igi_curr <= 0x24) || (dm->rssi_min < 22)) { + + if (cckpd_t->cck_fa_ma > 1000) { + cs_ration = dig_t->aaa_default + AAA_STEP; + cs_2r_offset = 1; + pd_th = 0x7; + } else if (cckpd_t->cck_fa_ma < 500) { + cs_ration = dig_t->aaa_default; + pd_th = 0x3; + } else { + is_update = false; + cs_ration = cckpd_t->cck_cca_th_aaa; + pd_th = cckpd_t->cur_cck_cca_thres; + } + } + } else { + + if (cckpd_t->cck_fa_ma > 1000) { + cs_ration = dig_t->aaa_default + AAA_STEP; + cs_2r_offset = 1; + pd_th = 0x7; + } else if (cckpd_t->cck_fa_ma < 500) { + cs_ration = dig_t->aaa_default; + pd_th = 0x3; + } else { + is_update = false; + cs_ration = cckpd_t->cck_cca_th_aaa; + pd_th = cckpd_t->cur_cck_cca_thres; + } + } + + if (en_2rcca) + cs_ration = (cs_ration >= cs_2r_offset) ? (cs_ration - cs_2r_offset) : 0; + + PHYDM_DBG(dm, DBG_CCKPD, + "[New] cs_ratio=0x%x, pd_th=0x%x\n", cs_ration, pd_th); + + if (is_update) { + cckpd_t->cur_cck_cca_thres = pd_th; + cckpd_t->cck_cca_th_aaa = cs_ration; + odm_set_bb_reg(dm, 0xa08, 0xf0000, pd_th); + odm_set_bb_reg(dm, 0xaa8, 0x1f0000, cs_ration); + } + /*phydm_write_cck_cca_th_new_cs_ratio(dm, pd_th, cs_ration);*/ +} + +#endif + +void +phydm_cck_pd_th( + void *dm_void +) +{ +#ifdef PHYDM_SUPPORT_CCKPD + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t= &dm->false_alm_cnt; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u32 cnt_cck_fail_tmp = fa_t->cnt_cck_fail; + #ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_fa_acc_struct *fa_acc_t = &dm->false_alm_cnt_acc; + #endif + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + + if (phydm_stop_cck_pd_th(dm) == true) + return; + +#ifdef PHYDM_TDMA_DIG_SUPPORT + cnt_cck_fail_tmp = (dm->original_dig_restore) ? (fa_t->cnt_cck_fail) : (fa_acc_t->cnt_cck_fail_1sec); +#endif + + if (cckpd_t->cck_fa_ma == CCK_FA_MA_RESET) + cckpd_t->cck_fa_ma = cnt_cck_fail_tmp; + else { + cckpd_t->cck_fa_ma = ((cckpd_t->cck_fa_ma << 1) + + cckpd_t->cck_fa_ma + cnt_cck_fail_tmp) >> 2; + } + + PHYDM_DBG(dm, DBG_CCKPD, "CCK FA=%d\n", cckpd_t->cck_fa_ma); + + if (dm->support_ic_type & EXTEND_CCK_CCATH_AAA_IC) + phydm_cckpd_new_cs_ratio(dm); + else + phydm_cckpd(dm); + +#endif +} + +void +odm_pause_cck_packet_detection( + void *dm_void, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_lv, + u8 cck_pd_th +) +{ +#ifdef PHYDM_SUPPORT_CCKPD + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + s8 max_level; + u8 i; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + + if ((cckpd_t->pause_bitmap == 0) && + (!(dm->support_ability & (ODM_BB_CCK_PD | ODM_BB_FA_CNT)))) { + + PHYDM_DBG(dm, DBG_CCKPD, "Return: not support\n"); + return; + } + + if (pause_lv >= PHYDM_PAUSE_MAX_NUM) { + PHYDM_DBG(dm, DBG_CCKPD, "Return: Wrong LV !\n"); + return; + } + PHYDM_DBG(dm, DBG_CCKPD, "Set pause{Type, LV, val} = {%d, %d, 0x%x}\n", + pause_type, pause_lv, cck_pd_th); + + PHYDM_DBG(dm, DBG_CCKPD, "pause LV=0x%x\n", cckpd_t->pause_bitmap); + + for (i = 0; i < PHYDM_PAUSE_MAX_NUM; i ++) { + PHYDM_DBG(dm, DBG_CCKPD, "pause val[%d]=0x%x\n", + i, cckpd_t->pause_cckpd_value[i]); + } + + switch (pause_type) { + case PHYDM_PAUSE: + { + /* Disable CCK PD */ + dm->support_ability &= ~ODM_BB_CCK_PD; + + PHYDM_DBG(dm, DBG_CCKPD, "Pause CCK PD th\n"); + + /* Backup original CCK PD threshold decided by CCK PD mechanism */ + if (cckpd_t->pause_bitmap == 0) { + + cckpd_t->cckpd_bkp = cckpd_t->cur_cck_cca_thres; + + PHYDM_DBG(dm, DBG_CCKPD, "cckpd_bkp=0x%x\n", + cckpd_t->cckpd_bkp); + } + + cckpd_t->pause_bitmap |= BIT(pause_lv); /* Update pause level */ + cckpd_t->pause_cckpd_value[pause_lv] = cck_pd_th; + + /* Write new CCK PD threshold */ + if (BIT(pause_lv + 1) > cckpd_t->pause_bitmap) { + PHYDM_DBG(dm, DBG_CCKPD, "> ori pause LV=0x%x\n", + cckpd_t->pause_bitmap); + + phydm_write_cck_cca_th(dm, cck_pd_th); + } + break; + } + case PHYDM_RESUME: + { + /* check if the level is illegal or not */ + if ((cckpd_t->pause_bitmap & (BIT(pause_lv))) != 0) { + + cckpd_t->pause_bitmap &= (~(BIT(pause_lv))); + cckpd_t->pause_cckpd_value[pause_lv] = 0; + PHYDM_DBG(dm, DBG_CCKPD, "Resume CCK PD\n"); + } else { + + PHYDM_DBG(dm, DBG_CCKPD, "Wrong resume LV\n"); + break; + } + + /* Resume CCKPD */ + if (cckpd_t->pause_bitmap == 0) { + + PHYDM_DBG(dm, DBG_CCKPD, "Revert bkp_CCKPD=0x%x\n", + cckpd_t->cckpd_bkp); + + phydm_write_cck_cca_th(dm, cckpd_t->cckpd_bkp); + dm->support_ability |= ODM_BB_CCK_PD;/* Enable CCKPD */ + break; + } + + if (BIT(pause_lv) <= cckpd_t->pause_bitmap) + break; + + /* Calculate the maximum level now */ + for (max_level = (pause_lv - 1); max_level >= 0; max_level--) { + if (cckpd_t->pause_bitmap & BIT(max_level)) + break; + } + + /* write CCKPD of lower level */ + phydm_write_cck_cca_th(dm, cckpd_t->pause_cckpd_value[max_level]); + PHYDM_DBG(dm, DBG_CCKPD, "Write CCKPD=0x%x for max_LV=%d\n", + cckpd_t->pause_cckpd_value[max_level], max_level); + break; + } + default: + PHYDM_DBG(dm, DBG_CCKPD, "Wrong type\n"); + break; + } + + PHYDM_DBG(dm, DBG_CCKPD, "New pause bitmap=0x%x\n", + cckpd_t->pause_bitmap); + + for (i = 0; i < PHYDM_PAUSE_MAX_NUM; i ++) { + PHYDM_DBG(dm, DBG_CCKPD, "pause val[%d]=0x%x\n", + i, cckpd_t->pause_cckpd_value[i]); + } +#endif +} + +void +phydm_cck_pd_init( + void *dm_void +) +{ +#ifdef PHYDM_SUPPORT_CCKPD + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + cckpd_t->cur_cck_cca_thres = 0; + cckpd_t->cck_cca_th_aaa = 0; + + cckpd_t->pause_bitmap = 0; + + if (dm->support_ic_type & EXTEND_CCK_CCATH_AAA_IC) { + dig_t->aaa_default = odm_read_1byte(dm, 0xaaa) & 0x1f; + dig_t->a0a_default = (u8)odm_get_bb_reg(dm, R_0xa08, 0xff0000); + cckpd_t->cck_cca_th_aaa = dig_t->aaa_default; + cckpd_t->cur_cck_cca_thres = dig_t->a0a_default; + } else { + dig_t->a0a_default = (u8)odm_get_bb_reg(dm, R_0xa08, 0xff0000); + cckpd_t->cur_cck_cca_thres = dig_t->a0a_default; + } + + odm_memory_set(dm, cckpd_t->pause_cckpd_value, 0, PHYDM_PAUSE_MAX_NUM); +#endif +} + + diff --git a/hal/phydm/phydm_cck_pd.h b/hal/phydm/phydm_cck_pd.h new file mode 100644 index 0000000..e56f768 --- /dev/null +++ b/hal/phydm/phydm_cck_pd.h @@ -0,0 +1,94 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + + +#ifndef __PHYDM_CCK_PD_H__ +#define __PHYDM_CCK_PD_H__ + +#define CCK_PD_VERSION "1.0" /* 2017.05.09 Dino, Add phydm_cck_pd.h*/ + + +/* 1 ============================================================ + * 1 Definition + * 1 ============================================================ */ + + +#define AAA_BASE 4 +#define AAA_STEP 2 + +#define CCK_FA_MA_RESET 0xffffffff + +#define EXTEND_CCK_CCATH_AAA_IC (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |ODM_RTL8710B) +/* 1 ============================================================ + * 1 structure + * 1 ============================================================ */ + +#ifdef PHYDM_SUPPORT_CCKPD +struct phydm_cckpd_struct { + u8 cur_cck_cca_thres; /*0xA0A*/ + u8 cck_cca_th_aaa; /*0xAAA*/ + u32 cck_fa_ma; + u8 cckpd_bkp; + u32 rvrt_val[2]; + u8 pause_bitmap;/*will be removed*/ + u8 pause_lv; + u8 pause_cckpd_value[PHYDM_PAUSE_MAX_NUM]; /*will be removed*/ +}; +#endif + +/* 1 ============================================================ + * 1 enumeration + * 1 ============================================================ */ + +/* 1 ============================================================ + * 1 function prototype + * 1 ============================================================ */ + +void +phydm_set_cckpd_val( + void *dm_void, + u32 *val_buf, + u8 val_len +); + +void +phydm_cck_pd_th( + void *dm_void +); + +void +odm_pause_cck_packet_detection( + void *dm_void, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_level, + u8 cck_pd_threshold +); + +void +phydm_cck_pd_init( + void *dm_void +); + +#endif diff --git a/hal/phydm/phydm_features_ap.h b/hal/phydm/phydm_features_ap.h new file mode 100644 index 0000000..f986e8f --- /dev/null +++ b/hal/phydm/phydm_features_ap.h @@ -0,0 +1,131 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_AP_H__ +#define __PHYDM_FEATURES_AP_H__ + +#if (RTL8822B_SUPPORT == 1 || RTL8812A_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + #define FAHM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +#if (RTL8822B_SUPPORT == 1) + /*#define PHYDM_PHYSTAUS_SMP_MODE*/ +#endif + +#if (RTL8197F_SUPPORT == 1) + /*#define PHYDM_TDMA_DIG_SUPPORT*/ +#endif + +#if (RTL8197F_SUPPORT == 1) + #define PHYDM_LNA_SAT_CHK_SUPPORT +#endif + +#if (RTL8822B_SUPPORT == 1) + /*#define PHYDM_POWER_TRAINING_SUPPORT*/ +#endif + +#if (RTL8822B_SUPPORT == 1) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) + #define PHYDM_PRIMARY_CCA +#endif + +#if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822B_SUPPORT == 1) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8822B_SUPPORT == 1) + /*#define CONFIG_DYNAMIC_RX_PATH*/ +#endif + +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + /*#define CONFIG_ADAPTIVE_SOML*/ +#endif + +#if (RTL8812A_SUPPORT == 1 || RTL8821A_SUPPORT == 1 || RTL8881A_SUPPORT == 1 || RTL8192E_SUPPORT == 1 || RTL8723B_SUPPORT == 1) + /*#define CONFIG_RA_FW_DBG_CODE*/ +#endif + +/* #define CONFIG_DYNAMIC_TX_TWR */ +#define PHYDM_DIG_MODE_DECISION_SUPPORT +/*#define CONFIG_PSD_TOOL*/ +#define PHYDM_SUPPORT_CCKPD +#define RA_MASK_PHYDMLIZE_AP +/* #define CONFIG_RA_DBG_CMD*/ +/*#define CONFIG_PATH_DIVERSITY*/ +/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ +#define CONFIG_RA_DYNAMIC_RATE_ID +#define CONFIG_BB_TXBF_API +/*#define ODM_CONFIG_BT_COEXIST*/ +/*#define PHYDM_3RD_REFORM_RA_MASK*/ +#define PHYDM_3RD_REFORM_RSSI_MONOTOR +#define PHYDM_SUPPORT_RSSI_MONITOR +#if !defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION) + #define CONFIG_PHYDM_DEBUG_FUNCTION +#endif + +/* [ Configure Antenna Diversity ] */ +#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + #define ODM_EVM_ENHANCE_ANTDIV + #define SKIP_EVM_ANTDIV_TRAINING_PATCH + + /*----------*/ + + #if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + #define CONFIG_NO_2G_DIVERSITY + #endif + + #ifdef CONFIG_NO_5G_DIVERSITY_8881A + #define CONFIG_NO_5G_DIVERSITY + #elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A) + #define CONFIG_5G_CGCS_RX_DIVERSITY + #elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A) + #define CONFIG_5G_CG_TRX_DIVERSITY + #elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) + #define CONFIG_2G5G_CG_TRX_DIVERSITY + #endif + #if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) + #define CONFIG_NO_5G_DIVERSITY + #endif + /*----------*/ + #if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_NOT_SUPPORT_ANTDIV + #elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_2G_SUPPORT_ANTDIV + #elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_5G_SUPPORT_ANTDIV + #elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY)) + #define CONFIG_2G5G_SUPPORT_ANTDIV + #endif + /*----------*/ +#endif /*Antenna Diveristy*/ + +/*[SmartAntenna]*/ +/*#define CONFIG_SMART_ANTENNA*/ +#ifdef CONFIG_SMART_ANTENNA + /*#define CONFIG_CUMITEK_SMART_ANTENNA*/ +#endif +/* --------------------------------------------------*/ + +#endif diff --git a/hal/phydm/phydm_features_ce.h b/hal/phydm/phydm_features_ce.h new file mode 100644 index 0000000..a9e4e4e --- /dev/null +++ b/hal/phydm/phydm_features_ce.h @@ -0,0 +1,132 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_CE_H__ +#define __PHYDM_FEATURES_CE_H__ + +#if (RTL8822B_SUPPORT == 1 || RTL8812A_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + #define FAHM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +#if (RTL8822B_SUPPORT == 1) + /*#define PHYDM_PHYSTAUS_SMP_MODE*/ +#endif + +/*#define PHYDM_TDMA_DIG_SUPPORT*/ +/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/ + +#if (RTL8822B_SUPPORT == 1) + #define PHYDM_POWER_TRAINING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT == 1) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188E_SUPPORT == 1) + #define PHYDM_PRIMARY_CCA +#endif + +#if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822B_SUPPORT == 1) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + #define CONFIG_ADAPTIVE_SOML +#endif + + + +#if (RTL8822B_SUPPORT == 1) + /*#define CONFIG_DYNAMIC_RX_PATH*/ +#endif + +#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) + #define CONFIG_RECEIVER_BLOCKING +#endif + +/* #define CONFIG_DYNAMIC_TX_TWR */ +#define PHYDM_SUPPORT_CCKPD +#define RA_MASK_PHYDMLIZE_CE + +/*Antenna Diversity*/ +#ifdef CONFIG_ANTENNA_DIVERSITY + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + + #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + #if (RTL8821A_SUPPORT == 1) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT == 1) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ + #endif + #endif +#endif + +/*[SmartAntenna]*/ +/*#define CONFIG_SMART_ANTENNA*/ +#ifdef CONFIG_SMART_ANTENNA + /*#define CONFIG_CUMITEK_SMART_ANTENNA*/ +#endif +/* --------------------------------------------------*/ + +#ifdef CONFIG_DFS_MASTER + #define CONFIG_PHYDM_DFS_MASTER +#endif + +#if (RTL8812A_SUPPORT == 1 || RTL8821A_SUPPORT == 1 || RTL8881A_SUPPORT == 1 || RTL8192E_SUPPORT == 1 || RTL8723B_SUPPORT == 1) + /*#define CONFIG_RA_FW_DBG_CODE*/ +#endif + +/*#define PHYDM_DIG_MODE_DECISION_SUPPORT*/ +#define CONFIG_PSD_TOOL +/*#define CONFIG_RA_DBG_CMD*/ +/*#define CONFIG_ANT_DETECTION*/ +/*#define CONFIG_PATH_DIVERSITY*/ +/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ +#define CONFIG_BB_TXBF_API +#define CONFIG_PHYDM_DEBUG_FUNCTION + +#ifdef CONFIG_BT_COEXIST + #define ODM_CONFIG_BT_COEXIST +#endif +#define PHYDM_3RD_REFORM_RA_MASK +#define PHYDM_3RD_REFORM_RSSI_MONOTOR +#define PHYDM_SUPPORT_RSSI_MONITOR +/*#define PHYDM_AUTO_DEGBUG*/ + +#endif diff --git a/hal/phydm/phydm_features_win.h b/hal/phydm/phydm_features_win.h new file mode 100644 index 0000000..47b8bef --- /dev/null +++ b/hal/phydm/phydm_features_win.h @@ -0,0 +1,120 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_WIN_H__ +#define __PHYDM_FEATURES_WIN_H__ + +#if (RTL8822B_SUPPORT == 1 || RTL8812A_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + #define FAHM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +#if (RTL8822B_SUPPORT == 1) + /*#define PHYDM_PHYSTAUS_SMP_MODE*/ +#endif + +/*#define PHYDM_TDMA_DIG_SUPPORT*/ +/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/ + +#if (RTL8822B_SUPPORT == 1) + #define PHYDM_POWER_TRAINING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT == 1) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) + #define PHYDM_PRIMARY_CCA +#endif + +#if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822B_SUPPORT == 1) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + /*#define CONFIG_ADAPTIVE_SOML*/ +#endif + + +/*Antenna Diversity*/ +#define CONFIG_PHYDM_ANTENNA_DIVERSITY +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + + #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + /* --[SmtAnt]-----------------------------------------*/ + #if (RTL8821A_SUPPORT == 1) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #define CONFIG_FAT_PATCH + #endif + + #if (RTL8822B_SUPPORT == 1) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ + #endif + + #if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1) || defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) + #define CONFIG_HL_SMART_ANTENNA + #endif + + /* --------------------------------------------------*/ + +#endif + +/*[SmartAntenna]*/ +#define CONFIG_SMART_ANTENNA +#ifdef CONFIG_SMART_ANTENNA + /*#define CONFIG_CUMITEK_SMART_ANTENNA*/ +#endif + /* --------------------------------------------------*/ + +#if (RTL8822B_SUPPORT == 1) + /*#define CONFIG_DYNAMIC_RX_PATH*/ +#endif + +#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) + #define CONFIG_RECEIVER_BLOCKING +#endif + +#if (RTL8812A_SUPPORT == 1 || RTL8821A_SUPPORT == 1 || RTL8881A_SUPPORT == 1 || RTL8192E_SUPPORT == 1 || RTL8723B_SUPPORT == 1) + #define CONFIG_RA_FW_DBG_CODE +#endif + +/* #define CONFIG_DYNAMIC_TX_TWR */ +/*#define PHYDM_DIG_MODE_DECISION_SUPPORT */ +#define CONFIG_PSD_TOOL +#define PHYDM_SUPPORT_CCKPD +#define RA_MASK_PHYDMLIZE_WIN +/*#define CONFIG_PATH_DIVERSITY*/ +/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ +#define CONFIG_ANT_DETECTION +/*#define CONFIG_RA_DBG_CMD*/ +#define CONFIG_BB_TXBF_API +#define ODM_CONFIG_BT_COEXIST +#define PHYDM_3RD_REFORM_RA_MASK +#define PHYDM_3RD_REFORM_RSSI_MONOTOR +#define CONFIG_PHYDM_DFS_MASTER +#define PHYDM_SUPPORT_RSSI_MONITOR +#define PHYDM_AUTO_DEGBUG +#define CONFIG_PHYDM_DEBUG_FUNCTION + +#endif diff --git a/hal/phydm/phydm_math_lib.c b/hal/phydm/phydm_math_lib.c new file mode 100644 index 0000000..16480f6 --- /dev/null +++ b/hal/phydm/phydm_math_lib.c @@ -0,0 +1,179 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +const u16 db_invert_table[12][8] = { + { 1, 1, 1, 2, 2, 2, 2, 3}, + { 3, 3, 4, 4, 4, 5, 6, 6}, + { 7, 8, 9, 10, 11, 13, 14, 16}, + { 18, 20, 22, 25, 28, 32, 35, 40}, + { 45, 50, 56, 63, 71, 79, 89, 100}, + { 112, 126, 141, 158, 178, 200, 224, 251}, + { 282, 316, 355, 398, 447, 501, 562, 631}, + { 708, 794, 891, 1000, 1122, 1259, 1413, 1585}, + { 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, + { 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000}, + { 11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119}, + { 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} +}; + + +/*Y = 10*log(X)*/ +s32 +odm_pwdb_conversion( + s32 X, + u32 total_bit, + u32 decimal_bit +) +{ + s32 Y, integer = 0, decimal = 0; + u32 i; + + if (X == 0) + X = 1; /* log2(x), x can't be 0 */ + + for (i = (total_bit - 1); i > 0; i--) { + if (X & BIT(i)) { + integer = i; + if (i > 0) + decimal = (X & BIT(i - 1)) ? 2 : 0; /* decimal is 0.5dB*3=1.5dB~=2dB */ + break; + } + } + + Y = 3 * (integer - decimal_bit) + decimal; /* 10*log(x)=3*log2(x), */ + + return Y; +} + +s32 +odm_sign_conversion( + s32 value, + u32 total_bit +) +{ + if (value & BIT(total_bit - 1)) + value -= BIT(total_bit); + + return value; +} + +void +phydm_seq_sorting( + void *dm_void, + u32 *value, + u32 *rank_idx, + u32 *idx_out, + u8 seq_length +) +{ + u8 i = 0, j = 0; + u32 tmp_a, tmp_b; + u32 tmp_idx_a, tmp_idx_b; + + for (i = 0; i < seq_length; i++) { + rank_idx[i] = i; + /**/ + } + + for (i = 0; i < (seq_length - 1); i++) { + for (j = 0; j < (seq_length - 1 - i); j++) { + tmp_a = value[j]; + tmp_b = value[j + 1]; + + tmp_idx_a = rank_idx[j]; + tmp_idx_b = rank_idx[j + 1]; + + if (tmp_a < tmp_b) { + value[j] = tmp_b; + value[j + 1] = tmp_a; + + rank_idx[j] = tmp_idx_b; + rank_idx[j + 1] = tmp_idx_a; + } + } + } + + for (i = 0; i < seq_length; i++) { + idx_out[rank_idx[i]] = i + 1; + /**/ + } +} + +u32 +odm_convert_to_db( + u32 value) +{ + u8 i; + u8 j; + u32 dB; + + value = value & 0xFFFF; + + for (i = 0; i < 12; i++) { + if (value <= db_invert_table[i][7]) + break; + } + + if (i >= 12) { + return 96; /* maximum 96 dB */ + } + + for (j = 0; j < 8; j++) { + if (value <= db_invert_table[i][j]) + break; + } + + dB = (i << 3) + j + 1; + + return dB; +} + +u32 +odm_convert_to_linear( + u32 value) +{ + u8 i; + u8 j; + u32 linear; + + /* 1dB~96dB */ + + value = value & 0xFF; + + i = (u8)((value - 1) >> 3); + j = (u8)(value - 1) - (i << 3); + + linear = db_invert_table[i][j]; + + return linear; +} + diff --git a/hal/phydm/phydm_math_lib.h b/hal/phydm/phydm_math_lib.h new file mode 100644 index 0000000..80124f9 --- /dev/null +++ b/hal/phydm/phydm_math_lib.h @@ -0,0 +1,87 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + + +#ifndef __PHYDM_MATH_LIB_H__ +#define __PHYDM_MATH_LIB_H__ + +#define AUTO_MATH_LIB_VERSION "1.0" /* 2017.06.06*/ + + +/* 1 ============================================================ + * 1 Definition + * 1 ============================================================ */ + + + + +/* 1 ============================================================ + * 1 enumeration + * 1 ============================================================ */ + + + +/* 1 ============================================================ + * 1 structure + * 1 ============================================================ */ + + +/* 1 ============================================================ + * 1 function prototype + * 1 ============================================================ */ + +s32 +odm_pwdb_conversion( + s32 X, + u32 total_bit, + u32 decimal_bit +); + +s32 +odm_sign_conversion( + s32 value, + u32 total_bit +); + +void +phydm_seq_sorting( + void *dm_void, + u32 *value, + u32 *rank_idx, + u32 *idx_out, + u8 seq_length +); + +u32 +odm_convert_to_db( + u32 value +); + +u32 +odm_convert_to_linear( + u32 value +); + +#endif diff --git a/hal/phydm/phydm_phystatus.c b/hal/phydm/phydm_phystatus.c new file mode 100644 index 0000000..8661ff2 --- /dev/null +++ b/hal/phydm/phydm_phystatus.c @@ -0,0 +1,2554 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void +phydm_rx_statistic_cal( + struct dm_struct *phydm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo +) +{ +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + struct phy_status_rpt_jaguar2_type1 *phy_sta_rpt = (struct phy_status_rpt_jaguar2_type1 *)phy_status_inf; + u8 phy_status_type = (*phy_status_inf & 0xf); +#endif + u8 date_rate = (pktinfo->data_rate & 0x7f); + u8 bw_idx = phy_info->band_width ; + + if (date_rate <= ODM_RATE54M) { + phydm->phy_dbg_info.num_qry_legacy_pkt[date_rate]++; + /**/ + } else if (date_rate <= ODM_RATEMCS31) { + phydm->phy_dbg_info.ht_pkt_not_zero = true; + + if (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) { + if ((bw_idx == *phydm->band_width)) { + + phydm->phy_dbg_info.num_qry_ht_pkt[date_rate - ODM_RATEMCS0]++; + + } else if (bw_idx == CHANNEL_WIDTH_20) { + + phydm->phy_dbg_info.num_qry_pkt_sc_20m[date_rate - ODM_RATEMCS0]++; + phydm->phy_dbg_info.low_bw_20_occur = true; + } + } else { + phydm->phy_dbg_info.num_qry_ht_pkt[date_rate - ODM_RATEMCS0]++; + } + } + #if ODM_IC_11AC_SERIES_SUPPORT + else if (date_rate <= ODM_RATEVHTSS4MCS9) { + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + if ((phy_status_type == 1) && + (phy_sta_rpt->gid != 0) && + (phy_sta_rpt->gid != 63) && + (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC)) { + phydm->phy_dbg_info.num_qry_mu_vht_pkt[date_rate - ODM_RATEVHTSS1MCS0]++; + if (pktinfo->ppdu_cnt < 4) { + phydm->phy_dbg_info.num_of_ppdu[pktinfo->ppdu_cnt] = date_rate | BIT(7); + phydm->phy_dbg_info.gid_num[pktinfo->ppdu_cnt] = phy_sta_rpt->gid; + } + } else + #endif + { + phydm->phy_dbg_info.vht_pkt_not_zero = true; + + if (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) { + if ((bw_idx == *phydm->band_width)) { + phydm->phy_dbg_info.num_qry_vht_pkt[date_rate - ODM_RATEVHTSS1MCS0]++; + + } else if (bw_idx == CHANNEL_WIDTH_20) { + phydm->phy_dbg_info.num_qry_pkt_sc_20m[date_rate - ODM_RATEVHTSS1MCS0]++; + phydm->phy_dbg_info.low_bw_20_occur = true; + } else /*if (bw_idx == CHANNEL_WIDTH_40)*/ { + phydm->phy_dbg_info.num_qry_pkt_sc_40m[date_rate - ODM_RATEVHTSS1MCS0]++; + phydm->phy_dbg_info.low_bw_40_occur = true; + } + } else { + phydm->phy_dbg_info.num_qry_vht_pkt[date_rate - ODM_RATEVHTSS1MCS0]++; + } + + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + if (pktinfo->ppdu_cnt < 4) { + phydm->phy_dbg_info.num_of_ppdu[pktinfo->ppdu_cnt] = date_rate; + phydm->phy_dbg_info.gid_num[pktinfo->ppdu_cnt] = phy_sta_rpt->gid; + } + #endif + } + } + #endif +} + +void +phydm_reset_phystatus_avg( + struct dm_struct *dm +) +{ + struct phydm_phystatus_avg *dbg_avg = &dm->phy_dbg_info.phystatus_statistic_avg; + + odm_memory_set(dm, &dbg_avg->rssi_cck_avg, 0, + sizeof(struct phydm_phystatus_avg)); +} + +void +phydm_reset_phystatus_statistic( + struct dm_struct *dm +) +{ + struct phydm_phystatus_statistic *dbg_statistic = &dm->phy_dbg_info.phystatus_statistic_info; + + odm_memory_set(dm, &dbg_statistic->rssi_cck_sum, 0, + sizeof(struct phydm_phystatus_statistic)); +} + +void +phydm_avg_phystatus_index( + struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo +) +{ + struct phydm_phystatus_statistic *dbg_statistic = &dm->phy_dbg_info.phystatus_statistic_info; + + if (pktinfo->data_rate <= ODM_RATE11M) { + /*RSSI*/ + dbg_statistic->rssi_cck_sum += phy_info->rx_mimo_signal_strength[0]; + dbg_statistic->rssi_cck_cnt++; + } else if (pktinfo->data_rate <= ODM_RATE54M) { + /*evm*/ + dbg_statistic->evm_ofdm_sum += phy_info->rx_mimo_evm_dbm[0]; + + /*SNR*/ + dbg_statistic->snr_ofdm_sum += phy_info->rx_snr[0]; + + /*RSSI*/ + dbg_statistic->rssi_ofdm_sum += phy_info->rx_mimo_signal_strength[0]; + dbg_statistic->rssi_ofdm_cnt++; + } else if (pktinfo->rate_ss == 1) { + /*evm*/ + dbg_statistic->evm_1ss_sum += phy_info->rx_mimo_evm_dbm[0]; + + /*SNR*/ + dbg_statistic->snr_1ss_sum += phy_info->rx_snr[0]; + + dbg_statistic->rssi_1ss_sum += phy_info->rx_mimo_signal_strength[0]; + dbg_statistic->rssi_1ss_cnt++; + } else if (pktinfo->rate_ss == 2) { + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + /*evm*/ + dbg_statistic->evm_2ss_sum[0] += phy_info->rx_mimo_evm_dbm[0]; + dbg_statistic->evm_2ss_sum[1] += phy_info->rx_mimo_evm_dbm[1]; + + /*SNR*/ + dbg_statistic->snr_2ss_sum[0] += phy_info->rx_snr[0]; + dbg_statistic->snr_2ss_sum[1] += phy_info->rx_snr[1]; + + /*RSSI*/ + dbg_statistic->rssi_2ss_sum[0] += phy_info->rx_mimo_signal_strength[0]; + dbg_statistic->rssi_2ss_sum[1] += phy_info->rx_mimo_signal_strength[1]; + dbg_statistic->rssi_2ss_cnt++; + #endif + } else if (pktinfo->rate_ss == 3) { + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + /*evm*/ + dbg_statistic->evm_3ss_sum[0] += phy_info->rx_mimo_evm_dbm[0]; + dbg_statistic->evm_3ss_sum[1] += phy_info->rx_mimo_evm_dbm[1]; + dbg_statistic->evm_3ss_sum[2] += phy_info->rx_mimo_evm_dbm[2]; + + /*SNR*/ + dbg_statistic->snr_3ss_sum[0] += phy_info->rx_snr[0]; + dbg_statistic->snr_3ss_sum[1] += phy_info->rx_snr[1]; + dbg_statistic->snr_3ss_sum[2] += phy_info->rx_snr[2]; + + /*RSSI*/ + dbg_statistic->rssi_3ss_sum[0] += phy_info->rx_mimo_signal_strength[0]; + dbg_statistic->rssi_3ss_sum[1] += phy_info->rx_mimo_signal_strength[1]; + dbg_statistic->rssi_3ss_sum[2] += phy_info->rx_mimo_signal_strength[2]; + dbg_statistic->rssi_3ss_cnt++; + #endif + } else if (pktinfo->rate_ss == 4) { + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + /*evm*/ + dbg_statistic->evm_4ss_sum[0] += phy_info->rx_mimo_evm_dbm[0]; + dbg_statistic->evm_4ss_sum[1] += phy_info->rx_mimo_evm_dbm[1]; + dbg_statistic->evm_4ss_sum[2] += phy_info->rx_mimo_evm_dbm[2]; + dbg_statistic->evm_4ss_sum[3] += phy_info->rx_mimo_evm_dbm[3]; + + /*SNR*/ + dbg_statistic->snr_4ss_sum[0] += phy_info->rx_snr[0]; + dbg_statistic->snr_4ss_sum[1] += phy_info->rx_snr[1]; + dbg_statistic->snr_4ss_sum[2] += phy_info->rx_snr[2]; + dbg_statistic->snr_4ss_sum[3] += phy_info->rx_snr[3]; + + /*RSSI*/ + dbg_statistic->rssi_4ss_sum[0] += phy_info->rx_mimo_signal_strength[0]; + dbg_statistic->rssi_4ss_sum[1] += phy_info->rx_mimo_signal_strength[1]; + dbg_statistic->rssi_4ss_sum[2] += phy_info->rx_mimo_signal_strength[2]; + dbg_statistic->rssi_4ss_sum[3] += phy_info->rx_mimo_signal_strength[3]; + dbg_statistic->rssi_4ss_cnt++; + #endif + } +} + +u8 phydm_get_signal_quality( + struct phydm_phyinfo_struct *phy_info, + struct dm_struct *dm, + struct phy_status_rpt_8192cd *phy_sta_rpt + ) +{ + u8 sq_rpt; + u8 result = 0; + + if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test) + result = 100; + else { + sq_rpt = phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all; + + if (sq_rpt > 64) + result = 0; + else if (sq_rpt < 20) + result = 100; + else + result = ((64 - sq_rpt) * 100) / 44; + + } + + return result; +} + +u8 +phydm_query_rx_pwr_percentage( + s8 ant_power +) +{ + if ((ant_power <= -100) || (ant_power >= 20)) + return 0; + else if (ant_power >= 0) + return 100; + else + return 100 + ant_power; +} + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +s32 +phydm_signal_scale_mapping_92c_series( + struct dm_struct *dm, + s32 curr_sig +) +{ + s32 ret_sig = 0; +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + if (dm->support_interface == ODM_ITRF_PCIE) { + /* step 1. Scale mapping. */ + if (curr_sig >= 61 && curr_sig <= 100) + ret_sig = 90 + ((curr_sig - 60) / 4); + else if (curr_sig >= 41 && curr_sig <= 60) + ret_sig = 78 + ((curr_sig - 40) / 2); + else if (curr_sig >= 31 && curr_sig <= 40) + ret_sig = 66 + (curr_sig - 30); + else if (curr_sig >= 21 && curr_sig <= 30) + ret_sig = 54 + (curr_sig - 20); + else if (curr_sig >= 5 && curr_sig <= 20) + ret_sig = 42 + (((curr_sig - 5) * 2) / 3); + else if (curr_sig == 4) + ret_sig = 36; + else if (curr_sig == 3) + ret_sig = 27; + else if (curr_sig == 2) + ret_sig = 18; + else if (curr_sig == 1) + ret_sig = 9; + else + ret_sig = curr_sig; + } +#endif + +#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + if ((dm->support_interface == ODM_ITRF_USB) || (dm->support_interface == ODM_ITRF_SDIO)) { + if (curr_sig >= 51 && curr_sig <= 100) + ret_sig = 100; + else if (curr_sig >= 41 && curr_sig <= 50) + ret_sig = 80 + ((curr_sig - 40) * 2); + else if (curr_sig >= 31 && curr_sig <= 40) + ret_sig = 66 + (curr_sig - 30); + else if (curr_sig >= 21 && curr_sig <= 30) + ret_sig = 54 + (curr_sig - 20); + else if (curr_sig >= 10 && curr_sig <= 20) + ret_sig = 42 + (((curr_sig - 10) * 2) / 3); + else if (curr_sig >= 5 && curr_sig <= 9) + ret_sig = 22 + (((curr_sig - 5) * 3) / 2); + else if (curr_sig >= 1 && curr_sig <= 4) + ret_sig = 6 + (((curr_sig - 1) * 3) / 2); + else + ret_sig = curr_sig; + } + +#endif + return ret_sig; +} + +s32 +phydm_signal_scale_mapping( + struct dm_struct *dm, + s32 curr_sig +) +{ + #ifdef CONFIG_SIGNAL_SCALE_MAPPING + return phydm_signal_scale_mapping_92c_series(dm, curr_sig); + #else + return curr_sig; + #endif + +} +#endif + +void +phydm_process_signal_strength( + struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo +) +{ + u8 avg_rssi = 0, tmp_rssi = 0, best_rssi = 0, second_rssi = 0; + u8 i; + + /* 2015/01 Sean, use the best two RSSI only, suggested by Ynlin and ChenYu.*/ + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + + tmp_rssi = phy_info->rx_mimo_signal_strength[i]; + + /*Get the best two RSSI*/ + if (tmp_rssi > best_rssi && tmp_rssi > second_rssi) { + second_rssi = best_rssi; + best_rssi = tmp_rssi; + } else if (tmp_rssi > second_rssi && tmp_rssi <= best_rssi) + second_rssi = tmp_rssi; + } + + if (best_rssi == 0) + return; + + avg_rssi = (pktinfo->rate_ss == 1) ? best_rssi : ((best_rssi + second_rssi) >> 1); + + if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) { + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + + /* Update signal strength to UI, and phy_info->rx_pwdb_all is the maximum RSSI of all path */ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + phy_info->signal_strength = SignalScaleProc((PADAPTER)dm->adapter, phy_info->rx_pwdb_all, false, false); + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + phy_info->signal_strength = (u8)(phydm_signal_scale_mapping(dm, phy_info->rx_pwdb_all)); + #endif + + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + #if ODM_IC_11AC_SERIES_SUPPORT + + /*UI BSS List signal strength(in percentage), make it good looking, from 0~100.*/ + /*It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().*/ + if (pktinfo->is_cck_rate) { + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /*2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ + phy_info->signal_strength = SignalScaleProc((PADAPTER)dm->adapter, phy_info->rx_pwdb_all, false, true); + #else + phy_info->signal_strength = (u8)(phydm_signal_scale_mapping(dm, phy_info->rx_pwdb_all));/*pwdb_all;*/ + #endif + } else { + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ + phy_info->signal_strength = SignalScaleProc((PADAPTER)dm->adapter, avg_rssi, false, false); + #else + phy_info->signal_strength = (u8)(phydm_signal_scale_mapping(dm, avg_rssi)); + #endif + } + #endif + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + #if ODM_IC_11N_SERIES_SUPPORT + + /* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */ + /* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */ + if (pktinfo->is_cck_rate) { + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */ + phy_info->signal_strength = SignalScaleProc((PADAPTER)dm->adapter, phy_info->rx_pwdb_all, true, true); + #else + phy_info->signal_strength = (u8)(phydm_signal_scale_mapping(dm, phy_info->rx_pwdb_all));/*pwdb_all;*/ + #endif + } else { + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */ + phy_info->signal_strength = SignalScaleProc((PADAPTER)dm->adapter, avg_rssi, true, false); + #else + phy_info->signal_strength = (u8)(phydm_signal_scale_mapping(dm, avg_rssi)); + #endif + } + #endif + } +} +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +static u8 phydm_sq_patch_rt_cid_819x_lenovo( + struct dm_struct *dm, + u8 is_cck_rate, + u8 pwdb_all, + u8 path, + u8 RSSI +) +{ + u8 sq = 0; + + if (is_cck_rate) { + if (IS_HARDWARE_TYPE_8192E(dm->adapter)) { + /* */ + /* Expected signal strength and bars indication at Lenovo lab. 2013.04.11 */ + /* 802.11n, 802.11b, 802.11g only at channel 6 */ + /* */ + /* Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm) */ + /* 50 5 -49 */ + /* 55 5 -49 */ + /* 60 5 -50 */ + /* 65 5 -51 */ + /* 70 5 -52 */ + /* 75 5 -54 */ + /* 80 5 -55 */ + /* 85 4 -60 */ + /* 90 3 -63 */ + /* 95 3 -65 */ + /* 100 2 -67 */ + /* 102 2 -67 */ + /* 104 1 -70 */ + /* */ + + if (pwdb_all >= 50) + sq = 100; + else if (pwdb_all >= 35 && pwdb_all < 50) + sq = 80; + else if (pwdb_all >= 31 && pwdb_all < 35) + sq = 60; + else if (pwdb_all >= 22 && pwdb_all < 31) + sq = 40; + else if (pwdb_all >= 18 && pwdb_all < 22) + sq = 20; + else + sq = 10; + } else { + if (pwdb_all >= 50) + sq = 100; + else if (pwdb_all >= 35 && pwdb_all < 50) + sq = 80; + else if (pwdb_all >= 22 && pwdb_all < 35) + sq = 60; + else if (pwdb_all >= 18 && pwdb_all < 22) + sq = 40; + else + sq = 10; + } + + } else { + /* OFDM rate */ + + if (IS_HARDWARE_TYPE_8192E(dm->adapter)) { + if (RSSI >= 45) + sq = 100; + else if (RSSI >= 22 && RSSI < 45) + sq = 80; + else if (RSSI >= 18 && RSSI < 22) + sq = 40; + else + sq = 20; + } else { + if (RSSI >= 45) + sq = 100; + else if (RSSI >= 22 && RSSI < 45) + sq = 80; + else if (RSSI >= 18 && RSSI < 22) + sq = 40; + else + sq = 20; + } + } + + RT_TRACE(COMP_DBG, DBG_TRACE, ("is_cck_rate(%#d), pwdb_all(%#d), RSSI(%#d), sq(%#d)\n", is_cck_rate, pwdb_all, RSSI, sq)); + + + return sq; +} + +static u8 phydm_sq_patch_rt_cid_819x_acer( + struct dm_struct *dm, + u8 is_cck_rate, + u8 pwdb_all, + u8 path, + u8 RSSI +) +{ + u8 sq = 0; + + if (is_cck_rate) { + RT_TRACE(COMP_DBG, DBG_WARNING, ("odm_SQ_process_patch_RT_Acer\n")); + +#if OS_WIN_FROM_WIN8(OS_VERSION) + + if (pwdb_all >= 50) + sq = 100; + else if (pwdb_all >= 35 && pwdb_all < 50) + sq = 80; + else if (pwdb_all >= 30 && pwdb_all < 35) + sq = 60; + else if (pwdb_all >= 25 && pwdb_all < 30) + sq = 40; + else if (pwdb_all >= 20 && pwdb_all < 25) + sq = 20; + else + sq = 10; +#else + if (pwdb_all >= 50) + sq = 100; + else if (pwdb_all >= 35 && pwdb_all < 50) + sq = 80; + else if (pwdb_all >= 30 && pwdb_all < 35) + sq = 60; + else if (pwdb_all >= 25 && pwdb_all < 30) + sq = 40; + else if (pwdb_all >= 20 && pwdb_all < 25) + sq = 20; + else + sq = 10; + + if (pwdb_all == 0) /* Abnormal case, do not indicate the value above 20 on Win7 */ + sq = 20; +#endif + + + + } else { + /* OFDM rate */ + + if (IS_HARDWARE_TYPE_8192E(dm->adapter)) { + if (RSSI >= 45) + sq = 100; + else if (RSSI >= 22 && RSSI < 45) + sq = 80; + else if (RSSI >= 18 && RSSI < 22) + sq = 40; + else + sq = 20; + } else { + if (RSSI >= 35) + sq = 100; + else if (RSSI >= 30 && RSSI < 35) + sq = 80; + else if (RSSI >= 25 && RSSI < 30) + sq = 40; + else + sq = 20; + } + } + + RT_TRACE(COMP_DBG, DBG_LOUD, ("is_cck_rate(%#d), pwdb_all(%#d), RSSI(%#d), sq(%#d)\n", is_cck_rate, pwdb_all, RSSI, sq)); + + + return sq; +} +#endif + +static u8 +phydm_evm_db_to_percentage( + s8 value +) +{ + /* */ + /* -33dB~0dB to 0%~99% */ + /* */ + s8 ret_val; + + ret_val = value; + ret_val /= 2; + + /*dbg_print("value=%d\n", value);*/ + /*ODM_RT_DISP(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C value=%d / %x\n", ret_val, ret_val));*/ +#ifdef ODM_EVM_ENHANCE_ANTDIV + if (ret_val >= 0) + ret_val = 0; + + if (ret_val <= -40) + ret_val = -40; + + ret_val = 0 - ret_val; + ret_val *= 3; +#else + if (ret_val >= 0) + ret_val = 0; + + if (ret_val <= -33) + ret_val = -33; + + ret_val = 0 - ret_val; + ret_val *= 3; + + if (ret_val == 99) + ret_val = 100; +#endif + + return (u8)ret_val; +} + +static u8 +phydm_evm_dbm_jaguar_series( + s8 value +) +{ + s8 ret_val = value; + + /* -33dB~0dB to 33dB ~ 0dB */ + if (ret_val == -128) + ret_val = 127; + else if (ret_val < 0) + ret_val = 0 - ret_val; + + ret_val = ret_val >> 1; + return (u8)ret_val; +} + +static s16 +phydm_cfo( + s8 value +) +{ + s16 ret_val; + + if (value < 0) { + ret_val = 0 - value; + ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */ + ret_val = ret_val | BIT(12); /* set bit12 as 1 for negative cfo */ + } else { + ret_val = value; + ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */ + } + return ret_val; +} + +s8 +phydm_cck_rssi_convert( + struct dm_struct *dm, + u16 lna_idx, + u8 vga_idx +) +{ + return (dm->cck_lna_gain_table[lna_idx] - (vga_idx << 1)); +} + +void +phydm_get_cck_rssi_table_from_reg( + struct dm_struct *dm +) +{ + u8 used_lna_idx_tmp; + u32 reg_0xa80 = 0x7431, reg_0xabc = 0xcbe5edfd; /*example: {-53, -43, -33, -27, -19, -13, -3, 1}*/ /*{0xCB, 0xD5, 0xDF, 0xE5, 0xED, 0xF3, 0xFD, 0x2}*/ + u8 i; + + PHYDM_DBG(dm, ODM_COMP_INIT, "CCK LNA Gain table init\n"); + + if (!(dm->support_ic_type & (ODM_RTL8197F))) + return; + + reg_0xa80 = odm_get_bb_reg(dm, 0xa80, 0xFFFF); + reg_0xabc = odm_get_bb_reg(dm, 0xabc, MASKDWORD); + + PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xa80 = 0x%x\n", reg_0xa80); + PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xabc = 0x%x\n", reg_0xabc); + + for (i = 0; i <= 3; i++) { + used_lna_idx_tmp = (u8)((reg_0xa80 >> (4*i)) & 0x7); + dm->cck_lna_gain_table[used_lna_idx_tmp] = (s8)((reg_0xabc >> (8*i)) & 0xff); + } + + PHYDM_DBG(dm, ODM_COMP_INIT, "cck_lna_gain_table = {%d,%d,%d,%d,%d,%d,%d,%d}\n", + dm->cck_lna_gain_table[0], + dm->cck_lna_gain_table[1], + dm->cck_lna_gain_table[2], + dm->cck_lna_gain_table[3], + dm->cck_lna_gain_table[4], + dm->cck_lna_gain_table[5], + dm->cck_lna_gain_table[6], + dm->cck_lna_gain_table[7]); + +} + +u8 +phydm_rate_to_num_ss( + struct dm_struct *dm, + u8 data_rate +) +{ + u8 num_ss = 1; + + if (data_rate <= ODM_RATE54M) + num_ss = 1; + else if (data_rate <= ODM_RATEMCS31) + num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1; + else if (data_rate <= ODM_RATEVHTSS1MCS9) + num_ss = 1; + else if (data_rate <= ODM_RATEVHTSS2MCS9) + num_ss = 2; + else if (data_rate <= ODM_RATEVHTSS3MCS9) + num_ss = 3; + else if (data_rate <= ODM_RATEVHTSS4MCS9) + num_ss = 4; + + return num_ss; +} + + + +#if (RTL8703B_SUPPORT == 1) +s8 +phydm_cck_rssi_8703B( + u16 LNA_idx, + u8 VGA_idx +) +{ + s8 rx_pwr_all = 0x00; + + switch (LNA_idx) { + case 0xf: + rx_pwr_all = -48 - (2 * VGA_idx); + break; + case 0xb: + rx_pwr_all = -42 - (2 * VGA_idx); /*TBD*/ + break; + case 0xa: + rx_pwr_all = -36 - (2 * VGA_idx); + break; + case 8: + rx_pwr_all = -32 - (2 * VGA_idx); + break; + case 7: + rx_pwr_all = -19 - (2 * VGA_idx); + break; + case 4: + rx_pwr_all = -6 - (2 * VGA_idx); + break; + case 0: + rx_pwr_all = -2 - (2 * VGA_idx); + break; + default: + /*rx_pwr_all = -53+(2*(31-VGA_idx));*/ + /*dbg_print("wrong LNA index\n");*/ + break; + + } + return rx_pwr_all; +} +#endif + +#if (RTL8195A_SUPPORT == 1) +s8 +phydm_cck_rssi_8195a( + struct dm_struct *dm, + u16 LNA_idx, + u8 VGA_idx +) +{ + s8 rx_pwr_all = 0; + s8 lna_gain = 0; + s8 lna_gain_table_0[8] = {0, -8, -15, -22, -29, -36, -45, -54}; + s8 lna_gain_table_1[8] = {0, -8, -15, -22, -29, -36, -45, -54};/*use 8195A to calibrate this table. 2016.06.24, Dino*/ + + if (dm->cck_agc_report_type == 0) + lna_gain = lna_gain_table_0[LNA_idx]; + else + lna_gain = lna_gain_table_1[LNA_idx]; + + rx_pwr_all = lna_gain - (2 * VGA_idx); + + return rx_pwr_all; +} +#endif + +#if (RTL8192E_SUPPORT == 1) +s8 +phydm_cck_rssi_8192e( + struct dm_struct *dm, + u16 LNA_idx, + u8 VGA_idx +) +{ + s8 rx_pwr_all = 0; + s8 lna_gain = 0; + s8 lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44}; + s8 lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36};/*use 8192EU to calibrate this table. 2015.12.15, Dino*/ + + if (dm->cck_agc_report_type == 0) + lna_gain = lna_gain_table_0[LNA_idx]; + else + lna_gain = lna_gain_table_1[LNA_idx]; + + rx_pwr_all = lna_gain - (2 * VGA_idx); + + return rx_pwr_all; +} +#endif + +#if (RTL8188E_SUPPORT == 1) +s8 +phydm_cck_rssi_8188e( + struct dm_struct *dm, + u16 LNA_idx, + u8 VGA_idx +) +{ + s8 rx_pwr_all = 0; + s8 lna_gain = 0; + s8 lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41};/*only use lna0/1/2/3/7*/ + s8 lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; /*only use lna3 /7*/ + + if (dm->cut_version >= ODM_CUT_I) /*SMIC*/ + lna_gain = lna_gain_table_0[LNA_idx]; + else /*TSMC*/ + lna_gain = lna_gain_table_1[LNA_idx]; + + rx_pwr_all = lna_gain - (2 * VGA_idx); + + return rx_pwr_all; +} +#endif + +#if (RTL8821C_SUPPORT == 1) +s8 +phydm_cck_rssi_8821c( + struct dm_struct *dm, + u8 LNA_idx, + u8 VGA_idx +) +{ + s8 rx_pwr_all = 0; + s8 lna_gain = 0; + s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};/*only use lna2/3/5/7*/ + s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17, + -20, -24, -28, -31, -34, -37, -40, -44}; /*only use lna4/8/C/F*/ + + if (dm->cck_agc_report_type == 0) + lna_gain = lna_gain_table_0[LNA_idx]; + else + lna_gain = lna_gain_table_1[LNA_idx]; + + rx_pwr_all = lna_gain - (2 * VGA_idx); + + return rx_pwr_all; +} +#endif + +#if (ODM_IC_11N_SERIES_SUPPORT == 1) +void +phydm_rx_phy_status92c_series_parsing( + struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo +) +{ + u8 i, max_spatial_stream; + s8 rx_pwr[4], rx_pwr_all = 0; + u8 EVM, pwdb_all = 0, pwdb_all_bt; + u8 RSSI, total_rssi = 0; + u8 rf_rx_num = 0; + u8 LNA_idx = 0; + u8 VGA_idx = 0; + u8 cck_agc_rpt; + u8 stream_rxevm_tmp = 0; + u8 sq; + struct phy_status_rpt_8192cd *phy_sta_rpt = (struct phy_status_rpt_8192cd *)phy_status_inf; + + if (pktinfo->is_to_self) + dm->curr_station_id = pktinfo->station_id; + + if (pktinfo->is_cck_rate) { + + cck_agc_rpt = phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a; + + if (dm->support_ic_type & (ODM_RTL8703B)) { +#if (RTL8703B_SUPPORT == 1) + if (dm->cck_agc_report_type == 1) { /*4 bit LNA*/ + + u8 cck_agc_rpt_b = (phy_sta_rpt->cck_rpt_b_ofdm_cfosho_b & BIT(7)) ? 1 : 0; + + LNA_idx = (cck_agc_rpt_b << 3) | ((cck_agc_rpt & 0xE0) >> 5); + VGA_idx = (cck_agc_rpt & 0x1F); + + rx_pwr_all = phydm_cck_rssi_8703B(LNA_idx, VGA_idx); + } +#endif + } else { /*3 bit LNA*/ + + LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); + VGA_idx = (cck_agc_rpt & 0x1F); + + if (dm->support_ic_type & (ODM_RTL8188E)) { +#if (RTL8188E_SUPPORT == 1) + rx_pwr_all = phydm_cck_rssi_8188e(dm, LNA_idx, VGA_idx); + /**/ +#endif + } +#if (RTL8192E_SUPPORT == 1) + else if (dm->support_ic_type & (ODM_RTL8192E)) { + rx_pwr_all = phydm_cck_rssi_8192e(dm, LNA_idx, VGA_idx); + /**/ + } +#endif +#if (RTL8723B_SUPPORT == 1) + else if (dm->support_ic_type & (ODM_RTL8723B)) { + rx_pwr_all = odm_CCKRSSI_8723B(LNA_idx, VGA_idx); + /**/ + } +#endif +#if (RTL8188F_SUPPORT == 1) + else if (dm->support_ic_type & (ODM_RTL8188F)) { + rx_pwr_all = odm_CCKRSSI_8188F(LNA_idx, VGA_idx); + /**/ + } +#endif +#if (RTL8195A_SUPPORT == 1) + else if (dm->support_ic_type & (ODM_RTL8195A)) { + rx_pwr_all = phydm_cck_rssi_8195a(LNA_idx, VGA_idx); + /**/ + } +#endif + } + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "ext_lna_gain (( %d )), LNA_idx: (( 0x%x )), VGA_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n", + dm->ext_lna_gain, LNA_idx, VGA_idx, rx_pwr_all); + + if (dm->board_type & ODM_BOARD_EXT_LNA) + rx_pwr_all -= dm->ext_lna_gain; + + pwdb_all = phydm_query_rx_pwr_percentage(rx_pwr_all); + + if (pktinfo->is_to_self) { + dm->cck_lna_idx = LNA_idx; + dm->cck_vga_idx = VGA_idx; + } + + phy_info->rx_pwdb_all = pwdb_all; + phy_info->bt_rx_rssi_percentage = pwdb_all; + phy_info->recv_signal_power = rx_pwr_all; + + /* (3) Get Signal Quality (EVM) */ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) + sq = phydm_sq_patch_rt_cid_819x_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0); + else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER) + sq = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0); + else + #endif + sq = phydm_get_signal_quality(phy_info, dm, phy_sta_rpt); + + /* dbg_print("cck sq = %d\n", sq); */ + phy_info->signal_quality = sq; + phy_info->rx_mimo_signal_quality[RF_PATH_A] = sq; + phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1; + + + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (i == 0) + phy_info->rx_mimo_signal_strength[0] = pwdb_all; + else + phy_info->rx_mimo_signal_strength[i] = 0; + } + } else { /* 2 is OFDM rate */ + + /* */ + /* (1)Get RSSI for HT rate */ + /* */ + + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH_N; i++) { + + if (dm->rf_path_rx_enable & BIT(i)) + rf_rx_num++; + + rx_pwr[i] = ((phy_sta_rpt->path_agc[i].gain & 0x3F) * 2) - 110; + + if (pktinfo->is_to_self) { + dm->ofdm_agc_idx[i] = (phy_sta_rpt->path_agc[i].gain & 0x3F); + /**/ + } + + phy_info->rx_pwr[i] = rx_pwr[i]; + RSSI = phydm_query_rx_pwr_percentage(rx_pwr[i]); + total_rssi += RSSI; + /* RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); */ + + phy_info->rx_mimo_signal_strength[i] = (u8) RSSI; + + /* Get Rx snr value in DB */ + phy_info->rx_snr[i] = (s8)(phy_sta_rpt->path_rxsnr[i] / 2); + + /* Record Signal Strength for next packet */ + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (i == RF_PATH_A) { + if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) { + phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, i, RSSI); + } else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER) + phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, RSSI); + } + #endif + } + + /* (2)PWDB, Average PWDB calculated by hardware (for rate adaptive) */ + rx_pwr_all = (((phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all) >> 1) & 0x7f) - 110; + + pwdb_all_bt = pwdb_all = phydm_query_rx_pwr_percentage(rx_pwr_all); + + phy_info->rx_pwdb_all = pwdb_all; + phy_info->bt_rx_rssi_percentage = pwdb_all_bt; + phy_info->rx_power = rx_pwr_all; + phy_info->recv_signal_power = rx_pwr_all; + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) { + /* do nothing */ + } else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER) { + /* do nothing */ + } else { +#endif + /* (3)EVM of HT rate */ + + if (pktinfo->data_rate >= ODM_RATEMCS8 && pktinfo->data_rate <= ODM_RATEMCS15) + max_spatial_stream = 2; /* both spatial stream make sense */ + else + max_spatial_stream = 1; /* only spatial stream 1 makes sense */ + + for (i = 0; i < max_spatial_stream; i++) { + /* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */ + /* fill most significant bit to "zero" when doing shifting operation which may change a negative */ + /* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */ + EVM = phydm_evm_db_to_percentage((phy_sta_rpt->stream_rxevm[i])); /* dbm */ + + if (i == RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */ + phy_info->signal_quality = (u8)(EVM & 0xff); + + phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff); + + if (phy_sta_rpt->stream_rxevm[i] < 0) + stream_rxevm_tmp = (u8)(0 - (phy_sta_rpt->stream_rxevm[i])); + + if (stream_rxevm_tmp == 64) + stream_rxevm_tmp = 0; + + phy_info->rx_mimo_evm_dbm[i] = stream_rxevm_tmp; + + } +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + } +#endif + + phydm_parsing_cfo(dm, pktinfo, phy_sta_rpt->path_cfotail, pktinfo->rate_ss); + + } + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + dm->dm_fat_table.antsel_rx_keep_0 = phy_sta_rpt->ant_sel; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sta_rpt->ant_sel_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sta_rpt->antsel_rx_keep_2; +#endif + +} +#endif + +#if ODM_IC_11AC_SERIES_SUPPORT + +void +phydm_rx_phy_bw_jaguar_series_parsing( + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo, + struct phy_status_rpt_8812 *phy_sta_rpt +) +{ + if (pktinfo->data_rate <= ODM_RATE54M) { + switch (phy_sta_rpt->r_RFMOD) { + case 1: + if (phy_sta_rpt->sub_chnl == 0) + phy_info->band_width = 1; + else + phy_info->band_width = 0; + break; + + case 2: + if (phy_sta_rpt->sub_chnl == 0) + phy_info->band_width = 2; + else if (phy_sta_rpt->sub_chnl == 9 || phy_sta_rpt->sub_chnl == 10) + phy_info->band_width = 1; + else + phy_info->band_width = 0; + break; + + default: + case 0: + phy_info->band_width = 0; + break; + } + } + +} + +void +phydm_rx_phy_status_jaguar_series_parsing( + struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo +) +{ + u8 i, max_spatial_stream; + s8 rx_pwr[4], rx_pwr_all = 0; + u8 EVM = 0, evm_dbm, pwdb_all = 0, pwdb_all_bt; + u8 RSSI, avg_rssi = 0; + u8 rf_rx_num = 0; + u8 cck_highpwr = 0; + u8 LNA_idx, VGA_idx; + struct phy_status_rpt_8812 *phy_sta_rpt = (struct phy_status_rpt_8812 *)phy_status_inf; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + phydm_rx_phy_bw_jaguar_series_parsing(phy_info, pktinfo, phy_sta_rpt); + + if (pktinfo->is_to_self) + dm->curr_station_id = pktinfo->station_id; + else + dm->curr_station_id = 0xff; + + + + if (pktinfo->is_cck_rate) { + u8 cck_agc_rpt; + + /*(1)Hardware does not provide RSSI for CCK*/ + /*(2)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ + + /*if(hal_data->e_rf_power_state == e_rf_on)*/ + cck_highpwr = dm->is_cck_high_power; + /*else*/ + /*cck_highpwr = false;*/ + + cck_agc_rpt = phy_sta_rpt->cfosho[0]; + LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); + VGA_idx = (cck_agc_rpt & 0x1F); + + if (dm->support_ic_type == ODM_RTL8812) { + switch (LNA_idx) { + case 7: + if (VGA_idx <= 27) + rx_pwr_all = -100 + 2 * (27 - VGA_idx); /*VGA_idx = 27~2*/ + else + rx_pwr_all = -100; + break; + case 6: + rx_pwr_all = -48 + 2 * (2 - VGA_idx); /*VGA_idx = 2~0*/ + break; + case 5: + rx_pwr_all = -42 + 2 * (7 - VGA_idx); /*VGA_idx = 7~5*/ + break; + case 4: + rx_pwr_all = -36 + 2 * (7 - VGA_idx); /*VGA_idx = 7~4*/ + break; + case 3: + /*rx_pwr_all = -28 + 2*(7-VGA_idx); VGA_idx = 7~0*/ + rx_pwr_all = -24 + 2 * (7 - VGA_idx); /*VGA_idx = 7~0*/ + break; + case 2: + if (cck_highpwr) + rx_pwr_all = -12 + 2 * (5 - VGA_idx); /*VGA_idx = 5~0*/ + else + rx_pwr_all = -6 + 2 * (5 - VGA_idx); + break; + case 1: + rx_pwr_all = 8 - 2 * VGA_idx; + break; + case 0: + rx_pwr_all = 14 - 2 * VGA_idx; + break; + default: + /*dbg_print("CCK Exception default\n");*/ + break; + } + rx_pwr_all += 6; + pwdb_all = phydm_query_rx_pwr_percentage(rx_pwr_all); + + if (cck_highpwr == false) { + if (pwdb_all >= 80) + pwdb_all = ((pwdb_all - 80) << 1) + ((pwdb_all - 80) >> 1) + 80; + else if ((pwdb_all <= 78) && (pwdb_all >= 20)) + pwdb_all += 3; + if (pwdb_all > 100) + pwdb_all = 100; + } + } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { + s8 pout = -6; + + switch (LNA_idx) { + case 5: + rx_pwr_all = pout - 32 - (2 * VGA_idx); + break; + case 4: + rx_pwr_all = pout - 24 - (2 * VGA_idx); + break; + case 2: + rx_pwr_all = pout - 11 - (2 * VGA_idx); + break; + case 1: + rx_pwr_all = pout + 5 - (2 * VGA_idx); + break; + case 0: + rx_pwr_all = pout + 21 - (2 * VGA_idx); + break; + } + pwdb_all = phydm_query_rx_pwr_percentage(rx_pwr_all); + } else if (dm->support_ic_type == ODM_RTL8814A) { + s8 pout = -6; + + switch (LNA_idx) { + /*CCK only use LNA: 2, 3, 5, 7*/ + case 7: + rx_pwr_all = pout - 32 - (2 * VGA_idx); + break; + case 5: + rx_pwr_all = pout - 22 - (2 * VGA_idx); + break; + case 3: + rx_pwr_all = pout - 2 - (2 * VGA_idx); + break; + case 2: + rx_pwr_all = pout + 5 - (2 * VGA_idx); + break; + /*case 6:*/ + /*rx_pwr_all = pout -26 - (2*VGA_idx);*/ + /*break;*/ + /*case 4:*/ + /*rx_pwr_all = pout - 8 - (2*VGA_idx);*/ + /*break;*/ + /*case 1:*/ + /*rx_pwr_all = pout + 21 - (2*VGA_idx);*/ + /*break;*/ + /*case 0:*/ + /*rx_pwr_all = pout + 10 - (2*VGA_idx);*/ + /* break; */ + default: + /* dbg_print("CCK Exception default\n"); */ + break; + } + pwdb_all = phydm_query_rx_pwr_percentage(rx_pwr_all); + } + + dm->cck_lna_idx = LNA_idx; + dm->cck_vga_idx = VGA_idx; + phy_info->rx_pwdb_all = pwdb_all; + /* if(pktinfo->station_id == 0) */ + /* { */ + /* dbg_print("CCK: LNA_idx = %d, VGA_idx = %d, phy_info->rx_pwdb_all = %d\n", */ + /* LNA_idx, VGA_idx, phy_info->rx_pwdb_all); */ + /* } */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + phy_info->bt_rx_rssi_percentage = pwdb_all; + phy_info->recv_signal_power = rx_pwr_all; +#endif + /*(3) Get Signal Quality (EVM)*/ + /*if (pktinfo->is_packet_match_bssid)*/ + { + u8 sq, sq_rpt; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) + sq = phydm_sq_patch_rt_cid_819x_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0); + else +#endif + if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test) + sq = 100; + else { + sq_rpt = phy_sta_rpt->pwdb_all; + + if (sq_rpt > 64) + sq = 0; + else if (sq_rpt < 20) + sq = 100; + else + sq = ((64 - sq_rpt) * 100) / 44; + } + + /* dbg_print("cck sq = %d\n", sq); */ + phy_info->signal_quality = sq; + phy_info->rx_mimo_signal_quality[RF_PATH_A] = sq; + } + + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (i == 0) + phy_info->rx_mimo_signal_strength[0] = pwdb_all; + else + phy_info->rx_mimo_signal_strength[i] = 0; + } + } else { + /*is OFDM rate*/ + fat_tab->hw_antsw_occur = phy_sta_rpt->hw_antsw_occur; + + /*(1)Get RSSI for OFDM rate*/ + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + /*2008/01/30 MH we will judge RF RX path now.*/ + /* dbg_print("dm->rf_path_rx_enable = %x\n", dm->rf_path_rx_enable); */ + if (dm->rf_path_rx_enable & BIT(i)) + rf_rx_num++; + /* else */ + /* continue; */ + /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ + /* if((dm->support_ic_type & (ODM_RTL8812|ODM_RTL8821)) && (!dm->is_mp_chip)) */ + if (i < RF_PATH_C) { + rx_pwr[i] = (phy_sta_rpt->gain_trsw[i] & 0x7F) - 110; + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = phy_sta_rpt->gain_trsw[i]; + + } else + rx_pwr[i] = (phy_sta_rpt->gain_trsw_cd[i - 2] & 0x7F) - 110; + /* else */ + /*rx_pwr[i] = ((phy_sta_rpt->gain_trsw[i]& 0x3F)*2) - 110; OLD FORMULA*/ + + phy_info->rx_pwr[i] = rx_pwr[i]; + + /* Translate DBM to percentage. */ + RSSI = phydm_query_rx_pwr_percentage(rx_pwr[i]); + + phy_info->rx_mimo_signal_strength[i] = (u8) RSSI; + + + /*Get Rx snr value in DB*/ + if (i < RF_PATH_C) + phy_info->rx_snr[i] = phy_sta_rpt->rxsnr[i] / 2; + else if (dm->support_ic_type & (ODM_RTL8814A)) + phy_info->rx_snr[i] = phy_sta_rpt->csi_current[i - 2] / 2; + +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + /*(2) CFO_short & CFO_tail*/ + if (i < RF_PATH_C) { + phy_info->cfo_short[i] = phydm_cfo((phy_sta_rpt->cfosho[i])); + phy_info->cfo_tail[i] = phydm_cfo((phy_sta_rpt->cfotail[i])); + } +#endif + /* Record Signal Strength for next packet */ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (pktinfo->is_packet_match_bssid && (i == RF_PATH_A)) { + if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) { + phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, i, RSSI); + } + } +#endif + } + + /*(3)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ + + /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ + if ((dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) && (!dm->is_mp_chip)) + rx_pwr_all = (phy_sta_rpt->pwdb_all & 0x7f) - 110; + else + rx_pwr_all = (((phy_sta_rpt->pwdb_all) >> 1) & 0x7f) - 110; /*OLD FORMULA*/ + + pwdb_all_bt = pwdb_all = phydm_query_rx_pwr_percentage(rx_pwr_all); + + phy_info->rx_pwdb_all = pwdb_all; + /*PHYDM_DBG(dm,DBG_RSSI_MNTR, "ODM OFDM RSSI=%d\n",phy_info->rx_pwdb_all);*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + phy_info->bt_rx_rssi_percentage = pwdb_all_bt; + phy_info->rx_power = rx_pwr_all; + phy_info->recv_signal_power = rx_pwr_all; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) { + /*do nothing*/ + } else { +#endif + /*(4)EVM of OFDM rate*/ + + if ((pktinfo->data_rate >= ODM_RATEMCS8) && + (pktinfo->data_rate <= ODM_RATEMCS15)) + max_spatial_stream = 2; + else if ((pktinfo->data_rate >= ODM_RATEVHTSS2MCS0) && + (pktinfo->data_rate <= ODM_RATEVHTSS2MCS9)) + max_spatial_stream = 2; + else if ((pktinfo->data_rate >= ODM_RATEMCS16) && + (pktinfo->data_rate <= ODM_RATEMCS23)) + max_spatial_stream = 3; + else if ((pktinfo->data_rate >= ODM_RATEVHTSS3MCS0) && + (pktinfo->data_rate <= ODM_RATEVHTSS3MCS9)) + max_spatial_stream = 3; + else + max_spatial_stream = 1; + + /*if (pktinfo->is_packet_match_bssid) */ + /*dbg_print("pktinfo->data_rate = %d\n", pktinfo->data_rate);*/ + + for (i = 0; i < max_spatial_stream; i++) { + /*Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment*/ + /*fill most significant bit to "zero" when doing shifting operation which may change a negative*/ + /*value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.*/ + + if (pktinfo->data_rate >= ODM_RATE6M && pktinfo->data_rate <= ODM_RATE54M) { + if (i == RF_PATH_A) { + EVM = phydm_evm_db_to_percentage((phy_sta_rpt->sigevm)); /*dbm*/ + EVM += 20; + if (EVM > 100) + EVM = 100; + } + } else { + if (i < RF_PATH_C) { + if (phy_sta_rpt->rxevm[i] == -128) + phy_sta_rpt->rxevm[i] = -25; + EVM = phydm_evm_db_to_percentage((phy_sta_rpt->rxevm[i])); /*dbm*/ + } else { + if (phy_sta_rpt->rxevm_cd[i - 2] == -128) + phy_sta_rpt->rxevm_cd[i - 2] = -25; + EVM = phydm_evm_db_to_percentage((phy_sta_rpt->rxevm_cd[i - 2])); /*dbm*/ + } + } + + if (i < RF_PATH_C) + evm_dbm = phydm_evm_dbm_jaguar_series(phy_sta_rpt->rxevm[i]); + else + evm_dbm = phydm_evm_dbm_jaguar_series(phy_sta_rpt->rxevm_cd[i - 2]); + /*RT_DISP(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",*/ + /*pktinfo->data_rate, phy_sta_rpt->rxevm[i], "%", EVM));*/ + + if (i == RF_PATH_A) { + /*Fill value in RFD, Get the first spatial stream only*/ + phy_info->signal_quality = EVM; + } + phy_info->rx_mimo_signal_quality[i] = EVM; +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + phy_info->rx_mimo_evm_dbm[i] = evm_dbm; +#endif + } +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + } +#endif + + phydm_parsing_cfo(dm, pktinfo, phy_sta_rpt->cfotail, pktinfo->rate_ss); + + } + /* dbg_print("is_cck_rate= %d, phy_info->signal_strength=%d % PWDB_AL=%d rf_rx_num=%d\n", is_cck_rate, phy_info->signal_strength, pwdb_all, rf_rx_num); */ + + dm->rx_pwdb_ave = dm->rx_pwdb_ave + phy_info->rx_pwdb_all; + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + dm->dm_fat_table.antsel_rx_keep_0 = phy_sta_rpt->antidx_anta; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sta_rpt->antidx_antb; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sta_rpt->antidx_antc; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sta_rpt->antidx_antd; +#endif + + /*PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]: antidx_anta = ((%d)), MatchBSSID = ((%d))\n", pktinfo->station_id, phy_sta_rpt->antidx_anta, pktinfo->is_packet_match_bssid);*/ + + + /* dbg_print("phy_sta_rpt->antidx_anta = %d, phy_sta_rpt->antidx_antb = %d\n",*/ + /* phy_sta_rpt->antidx_anta, phy_sta_rpt->antidx_antb);*/ + /* dbg_print("----------------------------\n");*/ + /* dbg_print("pktinfo->station_id=%d, pktinfo->data_rate=0x%x\n",pktinfo->station_id, pktinfo->data_rate);*/ + /* dbg_print("phy_sta_rpt->r_RFMOD = %d\n", phy_sta_rpt->r_RFMOD);*/ + /* dbg_print("phy_sta_rpt->gain_trsw[0]=0x%x, phy_sta_rpt->gain_trsw[1]=0x%x\n",*/ + /* phy_sta_rpt->gain_trsw[0],phy_sta_rpt->gain_trsw[1]);*/ + /* dbg_print("phy_sta_rpt->gain_trsw[2]=0x%x, phy_sta_rpt->gain_trsw[3]=0x%x\n",*/ + /* phy_sta_rpt->gain_trsw_cd[0],phy_sta_rpt->gain_trsw_cd[1]);*/ + /* dbg_print("phy_sta_rpt->pwdb_all = 0x%x, phy_info->rx_pwdb_all = %d\n", phy_sta_rpt->pwdb_all, phy_info->rx_pwdb_all);*/ + /* dbg_print("phy_sta_rpt->cfotail[i] = 0x%x, phy_sta_rpt->CFO_tail[i] = 0x%x\n", phy_sta_rpt->cfotail[0], phy_sta_rpt->cfotail[1]);*/ + /* dbg_print("phy_sta_rpt->rxevm[0] = %d, phy_sta_rpt->rxevm[1] = %d\n", phy_sta_rpt->rxevm[0], phy_sta_rpt->rxevm[1]);*/ + /* dbg_print("phy_sta_rpt->rxevm[2] = %d, phy_sta_rpt->rxevm[3] = %d\n", phy_sta_rpt->rxevm_cd[0], phy_sta_rpt->rxevm_cd[1]);*/ + /* dbg_print("phy_info->rx_mimo_signal_strength[0]=%d, phy_info->rx_mimo_signal_strength[1]=%d, rx_pwdb_all=%d\n",*/ + /* phy_info->rx_mimo_signal_strength[0], phy_info->rx_mimo_signal_strength[1], phy_info->rx_pwdb_all);*/ + /* dbg_print("phy_info->rx_mimo_signal_strength[2]=%d, phy_info->rx_mimo_signal_strength[3]=%d\n",*/ + /* phy_info->rx_mimo_signal_strength[2], phy_info->rx_mimo_signal_strength[3]);*/ + /* dbg_print("ppPhyInfo->rx_mimo_signal_quality[0]=%d, phy_info->rx_mimo_signal_quality[1]=%d\n",*/ + /* phy_info->rx_mimo_signal_quality[0], phy_info->rx_mimo_signal_quality[1]);*/ + /* dbg_print("ppPhyInfo->rx_mimo_signal_quality[2]=%d, phy_info->rx_mimo_signal_quality[3]=%d\n",*/ + /* phy_info->rx_mimo_signal_quality[2], phy_info->rx_mimo_signal_quality[3]);*/ + +} + +#endif + +void +phydm_reset_rssi_for_dm( + struct dm_struct *dm, + u8 station_id +) +{ + struct cmn_sta_info *sta; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); +#endif + sta = dm->phydm_sta_info[station_id]; + + if (!is_sta_active(sta)) { + /**/ + return; + } + PHYDM_DBG(dm, DBG_RSSI_MNTR, "Reset RSSI for macid = (( %d ))\n", station_id); + + + sta->rssi_stat.rssi_cck = -1; + sta->rssi_stat.rssi_ofdm = -1; + sta->rssi_stat.rssi = -1; + sta->rssi_stat.ofdm_pkt_cnt = 0; + sta->rssi_stat.cck_pkt_cnt = 0; + sta->rssi_stat.cck_sum_power = 0; + sta->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT; + sta->rssi_stat.packet_map = 0; + sta->rssi_stat.valid_bit = 0; +} + +void +phydm_process_rssi_for_dm( + struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo +) +{ + s32 rssi_ave; + s8 undecorated_smoothed_pwdb, undecorated_smoothed_cck, undecorated_smoothed_ofdm; + u8 i; + u8 rssi_max, rssi_min; + u32 weighting = 0; + u8 send_rssi_2_fw = 0; + struct cmn_sta_info *sta; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); +#endif + + if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) + return; + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(dm, phy_info, pktinfo); +#endif + + sta = dm->phydm_sta_info[pktinfo->station_id]; + + if (!is_sta_active(sta)) { + return; + /**/ + } + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if ((dm->support_ability & ODM_BB_ANT_DIV) && + (fat_tab->enable_ctrl_frame_antdiv) + ) { + if (pktinfo->is_packet_match_bssid) + dm->data_frame_num++; + + if ((fat_tab->use_ctrl_frame_antdiv)) { + if (!pktinfo->is_to_self)/*data frame + CTRL frame*/ + return; + } else { + if ((!pktinfo->is_packet_match_bssid))/*data frame only*/ + return; + } + } else +#endif + { + if ((!pktinfo->is_packet_match_bssid))/*data frame only*/ + return; + } + + if (pktinfo->is_packet_beacon) + dm->phy_dbg_info.num_qry_beacon_pkt++; + + /* --------------Statistic for antenna/path diversity------------------ */ + if (dm->support_ability & ODM_BB_ANT_DIV) { +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + odm_process_rssi_for_ant_div(dm, phy_info, pktinfo); +#endif + } +#if (defined(CONFIG_PATH_DIVERSITY)) + else if (dm->support_ability & ODM_BB_PATH_DIV) + phydm_process_rssi_for_path_div(dm, phy_info, pktinfo); +#endif + /* -----------------Smart Antenna Debug Message------------------ */ + + undecorated_smoothed_cck = sta->rssi_stat.rssi_cck; + undecorated_smoothed_ofdm = sta->rssi_stat.rssi_ofdm; + undecorated_smoothed_pwdb = sta->rssi_stat.rssi; + + if (pktinfo->is_packet_to_self || pktinfo->is_packet_beacon) { + if (!pktinfo->is_cck_rate) { /* ofdm rate */ +#if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8814A)) { + u8 rx_count = 0; + u32 rssi_linear = 0; + + if (dm->rx_ant_status & BB_PATH_A) { + rx_count++; + rssi_linear += odm_convert_to_linear(phy_info->rx_mimo_signal_strength[RF_PATH_A]); + } + + if (dm->rx_ant_status & BB_PATH_B) { + rx_count++; + rssi_linear += odm_convert_to_linear(phy_info->rx_mimo_signal_strength[RF_PATH_B]); + } + + if (dm->rx_ant_status & BB_PATH_C) { + rx_count++; + rssi_linear += odm_convert_to_linear(phy_info->rx_mimo_signal_strength[RF_PATH_C]); + } + + if (dm->rx_ant_status & BB_PATH_D) { + rx_count++; + rssi_linear += odm_convert_to_linear(phy_info->rx_mimo_signal_strength[RF_PATH_D]); + } + + /* Calculate average RSSI */ + switch (rx_count) { + case 2: + rssi_linear = (rssi_linear >> 1); + break; + case 3: + rssi_linear = ((rssi_linear) + (rssi_linear << 1) + (rssi_linear << 3)) >> 5; /* rssi_linear/3 ~ rssi_linear*11/32 */ + break; + case 4: + rssi_linear = (rssi_linear >> 2); + break; + } + rssi_ave = odm_convert_to_db(rssi_linear); + } else +#endif + { + if (phy_info->rx_mimo_signal_strength[RF_PATH_B] == 0) { + rssi_ave = phy_info->rx_mimo_signal_strength[RF_PATH_A]; + } else { + /*dbg_print("rfd->status.rx_mimo_signal_strength[0] = %d, rfd->status.rx_mimo_signal_strength[1] = %d\n",*/ + /*rfd->status.rx_mimo_signal_strength[0], rfd->status.rx_mimo_signal_strength[1]);*/ + + if (phy_info->rx_mimo_signal_strength[RF_PATH_A] > phy_info->rx_mimo_signal_strength[RF_PATH_B]) { + rssi_max = phy_info->rx_mimo_signal_strength[RF_PATH_A]; + rssi_min = phy_info->rx_mimo_signal_strength[RF_PATH_B]; + } else { + rssi_max = phy_info->rx_mimo_signal_strength[RF_PATH_B]; + rssi_min = phy_info->rx_mimo_signal_strength[RF_PATH_A]; + } + if ((rssi_max - rssi_min) < 3) + rssi_ave = rssi_max; + else if ((rssi_max - rssi_min) < 6) + rssi_ave = rssi_max - 1; + else if ((rssi_max - rssi_min) < 10) + rssi_ave = rssi_max - 2; + else + rssi_ave = rssi_max - 3; + } + } + + /* 1 Process OFDM RSSI */ + if (undecorated_smoothed_ofdm <= 0) { /* initialize */ + undecorated_smoothed_ofdm = (s8)phy_info->rx_pwdb_all; + PHYDM_DBG(dm, DBG_RSSI_MNTR, "OFDM_INIT: (( %d ))\n", undecorated_smoothed_ofdm); + } else { + if (phy_info->rx_pwdb_all > (u32)undecorated_smoothed_ofdm) { + undecorated_smoothed_ofdm = + (s8)((((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) + + (rssi_ave)) / (RX_SMOOTH_FACTOR)); + undecorated_smoothed_ofdm = undecorated_smoothed_ofdm + 1; + PHYDM_DBG(dm, DBG_RSSI_MNTR, "OFDM_1: (( %d ))\n", undecorated_smoothed_ofdm); + } else { + undecorated_smoothed_ofdm = + (s8)((((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) + + (rssi_ave)) / (RX_SMOOTH_FACTOR)); + PHYDM_DBG(dm, DBG_RSSI_MNTR, "OFDM_2: (( %d ))\n", undecorated_smoothed_ofdm); + } + } + if (sta->rssi_stat.ofdm_pkt_cnt != 64) { + i = 63; + sta->rssi_stat.ofdm_pkt_cnt -= (u8)(((sta->rssi_stat.packet_map >> i) & BIT(0)) - 1); + } + sta->rssi_stat.packet_map = (sta->rssi_stat.packet_map << 1) | BIT(0); + + } else { + rssi_ave = phy_info->rx_pwdb_all; + + if (sta->rssi_stat.cck_pkt_cnt <= 63) + sta->rssi_stat.cck_pkt_cnt++; + + /* 1 Process CCK RSSI */ + if (undecorated_smoothed_cck <= 0) { /* initialize */ + undecorated_smoothed_cck = (s8)phy_info->rx_pwdb_all; + sta->rssi_stat.cck_sum_power = (u16)phy_info->rx_pwdb_all ; /*reset*/ + sta->rssi_stat.cck_pkt_cnt = 1; /*reset*/ + PHYDM_DBG(dm, DBG_RSSI_MNTR, "CCK_INIT: (( %d ))\n", undecorated_smoothed_cck); + } else if (sta->rssi_stat.cck_pkt_cnt <= CCK_RSSI_INIT_COUNT) { + sta->rssi_stat.cck_sum_power = sta->rssi_stat.cck_sum_power + (u16)phy_info->rx_pwdb_all; + undecorated_smoothed_cck = sta->rssi_stat.cck_sum_power / sta->rssi_stat.cck_pkt_cnt; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "CCK_0: (( %d )), SumPow = (( %d )), cck_pkt = (( %d ))\n", + undecorated_smoothed_cck, sta->rssi_stat.cck_sum_power, sta->rssi_stat.cck_pkt_cnt); + } else { + if (phy_info->rx_pwdb_all > (u32)undecorated_smoothed_cck) { + undecorated_smoothed_cck = + (s8)((((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) + + (phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR)); + undecorated_smoothed_cck = undecorated_smoothed_cck + 1; + PHYDM_DBG(dm, DBG_RSSI_MNTR, "CCK_1: (( %d ))\n", undecorated_smoothed_cck); + } else { + undecorated_smoothed_cck = + (s8)((((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) + + (phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR)); + PHYDM_DBG(dm, DBG_RSSI_MNTR, "CCK_2: (( %d ))\n", undecorated_smoothed_cck); + } + } + i = 63; + sta->rssi_stat.ofdm_pkt_cnt -= (u8)((sta->rssi_stat.packet_map >> i) & BIT(0)); + sta->rssi_stat.packet_map = sta->rssi_stat.packet_map << 1; + } + + /* if(entry) */ + + /* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */ + if (sta->rssi_stat.ofdm_pkt_cnt == 64) { /* speed up when all packets are OFDM*/ + undecorated_smoothed_pwdb = undecorated_smoothed_ofdm; + PHYDM_DBG(dm, DBG_RSSI_MNTR, "PWDB_0[%d] = (( %d ))\n", pktinfo->station_id, undecorated_smoothed_cck); + } else { + if (sta->rssi_stat.valid_bit < 64) + sta->rssi_stat.valid_bit++; + + if (sta->rssi_stat.valid_bit == 64) { + weighting = ((sta->rssi_stat.ofdm_pkt_cnt) > 4) ? 64 : (sta->rssi_stat.ofdm_pkt_cnt << 4); + undecorated_smoothed_pwdb = (s8)((weighting * undecorated_smoothed_ofdm + (64 - weighting) * undecorated_smoothed_cck) >> 6); + PHYDM_DBG(dm, DBG_RSSI_MNTR, "PWDB_1[%d] = (( %d )), W = (( %d ))\n", pktinfo->station_id, undecorated_smoothed_cck, weighting); + } else { + if (sta->rssi_stat.valid_bit != 0) + undecorated_smoothed_pwdb = + (sta->rssi_stat.ofdm_pkt_cnt * undecorated_smoothed_ofdm + (sta->rssi_stat.valid_bit - sta->rssi_stat.ofdm_pkt_cnt) * undecorated_smoothed_cck) / sta->rssi_stat.valid_bit; + else + undecorated_smoothed_pwdb = 0; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "PWDB_2[%d] = (( %d )), ofdm_pkt = (( %d )), Valid_Bit = (( %d ))\n", + pktinfo->station_id, undecorated_smoothed_cck, sta->rssi_stat.ofdm_pkt_cnt, sta->rssi_stat.valid_bit); + } + } + + + if ((sta->rssi_stat.ofdm_pkt_cnt >= 1 || sta->rssi_stat.cck_pkt_cnt >= 5) && (sta->rssi_stat.is_send_rssi == RA_RSSI_STATE_INIT)) { + send_rssi_2_fw = 1; + sta->rssi_stat.is_send_rssi = RA_RSSI_STATE_SEND; + } + + sta->rssi_stat.rssi_cck = undecorated_smoothed_cck; + sta->rssi_stat.rssi_ofdm = undecorated_smoothed_ofdm; + sta->rssi_stat.rssi = undecorated_smoothed_pwdb; + + + + if (send_rssi_2_fw) { /* Trigger init rate by RSSI */ + + if (sta->rssi_stat.ofdm_pkt_cnt != 0) + sta->rssi_stat.rssi = undecorated_smoothed_ofdm; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, + "[Send to FW] PWDB = (( %d )), ofdm_pkt = (( %d )), cck_pkt = (( %d ))\n", + undecorated_smoothed_pwdb, sta->rssi_stat.ofdm_pkt_cnt, sta->rssi_stat.cck_pkt_cnt); + + } + + /* dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt_cnt, weighting); */ + /* dbg_print("undecorated_smoothed_ofdm=%d, undecorated_smoothed_pwdb=%d, undecorated_smoothed_cck=%d\n", */ + /* undecorated_smoothed_ofdm, undecorated_smoothed_pwdb, undecorated_smoothed_cck); */ + + + } +} + +/* + * Endianness before calling this API + * */ + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) +/* For 8822B only!! need to move to FW finally */ +/*==============================================*/ + +boolean +phydm_query_is_mu_api( + struct dm_struct *phydm, + u8 ppdu_idx, + u8 *p_data_rate, + u8 *p_gid +) +{ + u8 data_rate = 0, gid = 0; + boolean is_mu = false; + + data_rate = phydm->phy_dbg_info.num_of_ppdu[ppdu_idx]; + gid = phydm->phy_dbg_info.gid_num[ppdu_idx]; + + if (data_rate & BIT(7)) { + is_mu = true; + data_rate = data_rate & ~(BIT(7)); + } else + is_mu = false; + + *p_data_rate = data_rate; + *p_gid = gid; + + return is_mu; + +} + +void +phydm_reset_phy_info( + struct dm_struct *phydm, + struct phydm_phyinfo_struct *phy_info +) +{ + phy_info->rx_pwdb_all = 0; + phy_info->signal_quality = 0; + phy_info->band_width = 0; + phy_info->rx_count = 0; + odm_memory_set(phydm, phy_info->rx_mimo_signal_quality, 0, 4); + odm_memory_set(phydm, phy_info->rx_mimo_signal_strength, 0, 4); + odm_memory_set(phydm, phy_info->rx_snr, 0, 4); + + phy_info->rx_power = -110; + phy_info->recv_signal_power = -110; + phy_info->bt_rx_rssi_percentage = 0; + phy_info->signal_strength = 0; + phy_info->channel = 0; + phy_info->is_mu_packet = 0; + phy_info->is_beamformed = 0; + phy_info->rxsc = 0; + odm_memory_set(phydm, phy_info->rx_pwr, -110, 4); + odm_memory_set(phydm, phy_info->cfo_short, 0, 8); + odm_memory_set(phydm, phy_info->cfo_tail, 0, 8); + + odm_memory_set(phydm, phy_info->rx_mimo_evm_dbm, 0, 4); +} + +void +phydm_print_phy_status_jarguar2( + struct dm_struct *dm, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info, + u8 phy_status_page_num +) +{ + struct phy_status_rpt_jaguar2_type0 *rpt0 = (struct phy_status_rpt_jaguar2_type0 *)phy_status_inf; + struct phy_status_rpt_jaguar2_type1 *rpt = (struct phy_status_rpt_jaguar2_type1 *)phy_status_inf; + struct phy_status_rpt_jaguar2_type2 *rpt2 = (struct phy_status_rpt_jaguar2_type2 *)phy_status_inf; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + u32 phy_status[PHY_STATUS_JRGUAR2_DW_LEN] = {0}; + u8 i; + + odm_move_memory(dm, phy_status, phy_status_inf, (PHY_STATUS_JRGUAR2_DW_LEN<<2)); + + if (!(dm->debug_components & DBG_PHY_STATUS)) + return; + + if (dbg->show_phy_sts_all_pkt == 0) { + if (!pktinfo->is_packet_match_bssid) + { + return; + } + } + + dbg->show_phy_sts_cnt++; + /*dbg_print("cnt=%d, max=%d\n", dbg->show_phy_sts_cnt, dbg->show_phy_sts_max_cnt);*/ + + if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) { + if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt) { + return; + } + } + + pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num); + pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d\n", pktinfo->station_id, pktinfo->data_rate, pktinfo->is_packet_match_bssid); + + for (i = 0; i < PHY_STATUS_JRGUAR2_DW_LEN; i++) { + pr_debug("Offset[%d:%d] = 0x%x\n", ((4 * i) + 3), (4*i), phy_status[i]); + } + + if (phy_status_page_num == 0) { + pr_debug("[0] TRSW=%d, MP_gain_idx=%d, pwdb=%d\n", rpt0->trsw, rpt0->gain, rpt0->pwdb); + pr_debug("[4] band=%d, CH=%d, agc_table = %d, rxsc = %d\n", rpt0->band, rpt0->channel, rpt0->agc_table, rpt0->rxsc); + pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n", + rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b, rpt0->antidx_a, rpt0->length); + pr_debug("[12] lna_h=%d, bb_power=%d, lna_l=%d, vga=%d, sq=%d\n", + rpt0->lna_h, rpt0->bb_power, rpt0->lna_l, rpt0->vga, rpt0->signal_quality); + + } else if (phy_status_page_num == 1) { + pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n", + rpt->pwdb[3], rpt->pwdb[2], rpt->pwdb[1], rpt->pwdb[0]); + pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht, l]={%d, %d}\n", + rpt->beamformed, rpt->ldpc, rpt->stbc, rpt->gnt_bt, + rpt->hw_antsw_occu, rpt->band, rpt->channel, rpt->ht_rxsc, rpt->l_rxsc); + pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n", + rpt->antidx_d, rpt->antidx_c, rpt->antidx_b, rpt->antidx_a, rpt->lsig_length); + pr_debug("[12] rf_mode=%d, NBI=%d, Intf_pos=%d, GID=%d, PAID=%d\n", + rpt->rf_mode, rpt->nb_intf_flag, + (rpt->intf_pos + (rpt->intf_pos_msb<<8)), rpt->gid, + (rpt->paid + (rpt->paid_msb<<8))); + pr_debug("[16] EVM[D:A]={%d, %d, %d, %d}\n", rpt->rxevm[3], rpt->rxevm[2], rpt->rxevm[1], rpt->rxevm[0]); + pr_debug("[20] CFO[D:A]={%d, %d, %d, %d}\n", rpt->cfo_tail[3], rpt->cfo_tail[2], rpt->cfo_tail[1], rpt->cfo_tail[0]); + pr_debug("[24] SNR[D:A]={%d, %d, %d, %d}\n\n", rpt->rxsnr[3], rpt->rxsnr[2], rpt->rxsnr[1], rpt->rxsnr[0]); + + } else if (phy_status_page_num == 2) { + + pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n", + rpt2->pwdb[3], rpt2->pwdb[2], rpt2->pwdb[1], rpt2->pwdb[0]); + pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht, l]={%d, %d}\n", + rpt2->beamformed, rpt2->ldpc, rpt2->stbc, rpt2->gnt_bt, + rpt2->hw_antsw_occu, rpt2->band, rpt2->channel, rpt2->ht_rxsc, rpt2->l_rxsc); + pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, cnt_pw2cca=%d, shift_l_map=%d\n", + rpt2->agc_table_d, rpt2->agc_table_c, rpt2->agc_table_b, rpt2->agc_table_a, + rpt2->cnt_pw2cca, rpt2->shift_l_map); + pr_debug("[12] (TRSW|Gain)[D:A]={%d %d, %d %d, %d %d, %d %d}, cnt_cca2agc_rdy=%d\n", + rpt2->trsw_d, rpt2->gain_d, rpt2->trsw_c, rpt2->gain_c, + rpt2->trsw_b,rpt2->gain_b, rpt2->trsw_a, rpt2->gain_a, rpt2->cnt_cca2agc_rdy); + pr_debug("[16] AAGC step[D:A]={%d, %d, %d, %d} HT AAGC gain[D:A]={%d, %d, %d, %d}\n", + rpt2->aagc_step_d, rpt2->aagc_step_c, rpt2->aagc_step_b, rpt2->aagc_step_a, + rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2], rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0]); + pr_debug("[20] DAGC gain[D:A]={%d, %d, %d, %d}\n", rpt2->dagc_gain[3], + rpt2->dagc_gain[2], rpt2->dagc_gain[1], rpt2->dagc_gain[0]); + pr_debug("[24] syn_cnt: %d, Cnt=%d\n\n", rpt2->syn_count, rpt2->counter); + } + +} + +void +phydm_set_per_path_phy_info( + u8 rx_path, + s8 rx_pwr, + s8 rx_evm, + s8 cfo_tail, + s8 rx_snr, + struct phydm_phyinfo_struct *phy_info +) +{ + u8 evm_dbm = 0; + u8 evm_percentage = 0; + + /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */ + + if (rx_evm < 0) { + /* Calculate EVM in dBm */ + evm_dbm = ((u8)(0 - rx_evm) >> 1); + + if (evm_dbm == 64) + evm_dbm = 0; /*if 1SS rate, evm_dbm [2nd stream] =64*/ + + if (evm_dbm != 0) { + /* Convert EVM to 0%~100% percentage */ + if (evm_dbm >= 34) + evm_percentage = 100; + else + evm_percentage = (evm_dbm << 1) + (evm_dbm); + } + } + + phy_info->rx_pwr[rx_path] = rx_pwr; + + phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1; /* CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/ + phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm; + phy_info->rx_mimo_signal_strength[rx_path] = phydm_query_rx_pwr_percentage(rx_pwr); + phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage; + phy_info->rx_snr[rx_path] = rx_snr >> 1; + +#if 0 + /* if (pktinfo->is_packet_match_bssid) */ + { + dbg_print("path (%d)--------\n", rx_path); + dbg_print("rx_pwr = %d, Signal strength = %d\n", phy_info->rx_pwr[rx_path], phy_info->rx_mimo_signal_strength[rx_path]); + dbg_print("evm_dbm = %d, Signal quality = %d\n", phy_info->rx_mimo_evm_dbm[rx_path], phy_info->rx_mimo_signal_quality[rx_path]); + dbg_print("CFO = %d, SNR = %d\n", phy_info->cfo_tail[rx_path], phy_info->rx_snr[rx_path]); + } +#endif +} + +void +phydm_set_common_phy_info( + s8 rx_power, + u8 channel, + boolean is_beamformed, + boolean is_mu_packet, + u8 bandwidth, + u8 signal_quality, + u8 rxsc, + struct phydm_phyinfo_struct *phy_info +) +{ + phy_info->rx_power = rx_power; /* RSSI in dB */ + phy_info->recv_signal_power = rx_power; /* RSSI in dB */ + phy_info->channel = channel; /* channel number */ + phy_info->is_beamformed = is_beamformed; /* apply BF */ + phy_info->is_mu_packet = is_mu_packet; /* MU packet */ + phy_info->rxsc = rxsc; + + phy_info->rx_pwdb_all = phydm_query_rx_pwr_percentage(rx_power); /* RSSI in percentage */ + phy_info->signal_quality = signal_quality; /* signal quality */ + phy_info->band_width = bandwidth; /* bandwidth */ + +#if 0 + /* if (pktinfo->is_packet_match_bssid) */ + { + dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", phy_info->rx_pwdb_all, phy_info->rx_power, phy_info->recv_signal_power); + dbg_print("signal_quality = %d\n", phy_info->signal_quality); + dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", phy_info->is_beamformed, phy_info->is_mu_packet, phy_info->rx_count + 1); + dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel, rxsc, bandwidth); + } +#endif +} + +void +phydm_get_rx_phy_status_type0( + struct dm_struct *dm, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info +) +{ + /* type 0 is used for cck packet */ + struct phy_status_rpt_jaguar2_type0 *phy_sta_rpt = (struct phy_status_rpt_jaguar2_type0 *)phy_status_inf; + u8 sq = 0; + s8 rx_power = phy_sta_rpt->pwdb - 110; + + + if (dm->support_ic_type & ODM_RTL8723D) { +#if (RTL8723D_SUPPORT == 1) + rx_power = phy_sta_rpt->pwdb - 97; +#endif + } +/*#if (RTL8710B_SUPPORT == 1)*/ + /*if (dm->support_ic_type & ODM_RTL8710B)*/ + /*rx_power = phy_sta_rpt->pwdb - 97;*/ +/*#endif*/ + +#if (RTL8821C_SUPPORT == 1) + else if (dm->support_ic_type & ODM_RTL8821C) { + if (phy_sta_rpt->pwdb >= -57) + rx_power = phy_sta_rpt->pwdb - 100; + else + rx_power = phy_sta_rpt->pwdb - 102; + } +#endif + + if (pktinfo->is_to_self) { + dm->ofdm_agc_idx[0] = phy_sta_rpt->pwdb; + dm->ofdm_agc_idx[1] = 0; + dm->ofdm_agc_idx[2] = 0; + dm->ofdm_agc_idx[3] = 0; + } + + + /* Calculate Signal Quality*/ + if (pktinfo->is_packet_match_bssid) { + if (phy_sta_rpt->signal_quality >= 64) + sq = 0; + else if (phy_sta_rpt->signal_quality <= 20) + sq = 100; + else { + /* mapping to 2~99% */ + sq = 64 - phy_sta_rpt->signal_quality; + sq = ((sq << 3) + sq) >> 2; + } + } + + /* Modify CCK PWDB if old AGC */ + if (dm->cck_new_agc == false) { + #if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8197F) + rx_power = phydm_cck_rssi_convert(dm, phy_sta_rpt->lna_l, phy_sta_rpt->vga); + else + #endif + { + u8 lna_idx, vga_idx; + + lna_idx = ((phy_sta_rpt->lna_h << 3) | phy_sta_rpt->lna_l); + vga_idx = phy_sta_rpt->vga; + + #if (RTL8723D_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8723D) + rx_power = odm_cckrssi_8723d(lna_idx, vga_idx); + #endif + + #if (RTL8710B_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8710B) + rx_power = odm_cckrssi_8710b(lna_idx, vga_idx); + #endif + + #if (RTL8822B_SUPPORT == 1) + /* Need to do !! */ + /*if (dm->support_ic_type & ODM_RTL8822B) */ + /*rx_power = odm_CCKRSSI_8822B(LNA_idx, VGA_idx);*/ + #endif + + #if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821C) + rx_power = phydm_cck_rssi_8821c(dm, lna_idx, vga_idx); + #endif + } + + } + + /* Confirm CCK RSSI */ + #if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8197F) { + u8 bb_pwr_th_l = 5; /* round( 31*0.15 ) */ + u8 bb_pwr_th_h = 27; /* round( 31*0.85 ) */ + + if ((phy_sta_rpt->bb_power < bb_pwr_th_l) || (phy_sta_rpt->bb_power > bb_pwr_th_h)) + rx_power = 0; /* Error RSSI for CCK ; set 100*/ + } + #endif + + /*CCK no STBC and LDPC*/ + dm->phy_dbg_info.is_ldpc_pkt = false; + dm->phy_dbg_info.is_stbc_pkt = false; + + /* Update Common information */ + phydm_set_common_phy_info(rx_power, phy_sta_rpt->channel, false, + false, CHANNEL_WIDTH_20, sq, phy_sta_rpt->rxsc, phy_info); + + /* Update CCK pwdb */ + phydm_set_per_path_phy_info(RF_PATH_A, rx_power, 0, 0, 0, phy_info); /* Update per-path information */ + + dm->dm_fat_table.antsel_rx_keep_0 = phy_sta_rpt->antidx_a; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sta_rpt->antidx_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sta_rpt->antidx_c; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sta_rpt->antidx_d; + +} + +void +phydm_get_rx_phy_status_type1( + struct dm_struct *dm, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info +) +{ + /* type 1 is used for ofdm packet */ + struct phy_status_rpt_jaguar2_type1 *phy_sta_rpt = (struct phy_status_rpt_jaguar2_type1 *)phy_status_inf; + s8 rx_pwr_db = -120; + s8 rx_path_pwr_db; + u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0; + boolean is_mu; + + /* Update per-path information */ + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (dm->rx_ant_status & BIT(i)) { + rx_count++; + + if (rx_count > dm->num_rf_path) + break; + + /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO sq) */ + /* EVM report is reported by stream, not path */ + rx_path_pwr_db = phy_sta_rpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = phy_sta_rpt->pwdb[i]; + + phydm_set_per_path_phy_info(i, rx_path_pwr_db, phy_sta_rpt->rxevm[rx_count - 1], + phy_sta_rpt->cfo_tail[i], phy_sta_rpt->rxsnr[i], phy_info); + + /* search maximum pwdb */ + if (rx_path_pwr_db > rx_pwr_db) + rx_pwr_db = rx_path_pwr_db; + } + } + + /* mapping RX counter from 1~4 to 0~3 */ + if (rx_count > 0) + phy_info->rx_count = rx_count - 1; + + /* Check if MU packet or not */ + if ((phy_sta_rpt->gid != 0) && (phy_sta_rpt->gid != 63)) { + is_mu = true; + dm->phy_dbg_info.num_qry_mu_pkt++; + } else + is_mu = false; + + /* count BF packet */ + dm->phy_dbg_info.num_qry_bf_pkt = dm->phy_dbg_info.num_qry_bf_pkt + phy_sta_rpt->beamformed; + + /*STBC or LDPC pkt*/ + dm->phy_dbg_info.is_ldpc_pkt = phy_sta_rpt->ldpc; + dm->phy_dbg_info.is_stbc_pkt = phy_sta_rpt->stbc; + + /* Check sub-channel */ + if ((pktinfo->data_rate > ODM_RATE11M) && (pktinfo->data_rate < ODM_RATEMCS0)) + rxsc = phy_sta_rpt->l_rxsc; + else + rxsc = phy_sta_rpt->ht_rxsc; + + /* Check RX bandwidth */ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if ((rxsc >= 1) && (rxsc <= 8)) + bw = CHANNEL_WIDTH_20; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = CHANNEL_WIDTH_40; + else if (rxsc >= 13) + bw = CHANNEL_WIDTH_80; + else + bw = phy_sta_rpt->rf_mode; + + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (phy_sta_rpt->rf_mode == 0) + bw = CHANNEL_WIDTH_20; + else if ((rxsc == 1) || (rxsc == 2)) + bw = CHANNEL_WIDTH_20; + else + bw = CHANNEL_WIDTH_40; + } + + /* Update packet information */ + phydm_set_common_phy_info(rx_pwr_db, phy_sta_rpt->channel, (boolean)phy_sta_rpt->beamformed, + is_mu, bw, phy_info->rx_mimo_signal_quality[0], rxsc, phy_info); + + phydm_parsing_cfo(dm, pktinfo, phy_sta_rpt->cfo_tail, pktinfo->rate_ss); + + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + dm->dm_fat_table.antsel_rx_keep_0 = phy_sta_rpt->antidx_a; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sta_rpt->antidx_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sta_rpt->antidx_c; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sta_rpt->antidx_d; + #endif +} + +void +phydm_get_rx_phy_status_type2( + struct dm_struct *dm, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info +) +{ + struct phy_status_rpt_jaguar2_type2 *phy_sta_rpt = (struct phy_status_rpt_jaguar2_type2 *)phy_status_inf; + s8 rx_pwr_db_max = -120; + s8 rx_path_pwr_db; + u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0; + + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (dm->rx_ant_status & BIT(i)) { + + rx_count++; + + if (rx_count > dm->num_rf_path) + break; + + /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO sq) */ + #if (RTL8197F_SUPPORT == 1) + if ((dm->support_ic_type & ODM_RTL8197F) && (phy_sta_rpt->pwdb[i] == 0x7f)) { /*for 97f workaround*/ + + if (i == RF_PATH_A) { + rx_path_pwr_db = (phy_sta_rpt->gain_a) << 1; + rx_path_pwr_db = rx_path_pwr_db - 110; + } else if (i == RF_PATH_B) { + rx_path_pwr_db = (phy_sta_rpt->gain_b) << 1; + rx_path_pwr_db = rx_path_pwr_db - 110; + } else + rx_path_pwr_db = 0; + } else + #endif + rx_path_pwr_db = phy_sta_rpt->pwdb[i] - 110; /*unit: (dBm)*/ + + phydm_set_per_path_phy_info(i, rx_path_pwr_db, 0, 0, 0, phy_info); + + if (rx_path_pwr_db > rx_pwr_db_max /* search maximum pwdb */) + rx_pwr_db_max = rx_path_pwr_db; + } + } + + /* mapping RX counter from 1~4 to 0~3 */ + if (rx_count > 0) + phy_info->rx_count = rx_count - 1; + + /* Check RX sub-channel */ + if ((pktinfo->data_rate > ODM_RATE11M) && (pktinfo->data_rate < ODM_RATEMCS0)) + rxsc = phy_sta_rpt->l_rxsc; + else + rxsc = phy_sta_rpt->ht_rxsc; + + /*STBC or LDPC pkt*/ + dm->phy_dbg_info.is_ldpc_pkt = phy_sta_rpt->ldpc; + dm->phy_dbg_info.is_stbc_pkt = phy_sta_rpt->stbc; + + /* Check RX bandwidth */ + /* the BW information of sc=0 is useless, because there is no information of RF mode*/ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if ((rxsc >= 1) && (rxsc <= 8)) + bw = CHANNEL_WIDTH_20; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = CHANNEL_WIDTH_40; + else if (rxsc >= 13) + bw = CHANNEL_WIDTH_80; + + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (rxsc == 3) + bw = CHANNEL_WIDTH_40; + else if ((rxsc == 1) || (rxsc == 2)) + bw = CHANNEL_WIDTH_20; + } + + /* Update packet information */ + phydm_set_common_phy_info(rx_pwr_db_max, phy_sta_rpt->channel, (boolean)phy_sta_rpt->beamformed, + false, bw, 0, rxsc, phy_info); +} + +void +phydm_process_rssi_for_dm_new_type( + struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo +) +{ + s32 rssi_pre; + u32 rssi_linear = 0; + s16 rssi_avg_db = 0; + u8 i; + struct cmn_sta_info *sta; + + if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + sta = dm->phydm_sta_info[pktinfo->station_id]; + + if (!is_sta_active(sta)) + return; + + if ((!pktinfo->is_packet_match_bssid))/*data frame only*/ + return; + + if (pktinfo->is_packet_beacon) + dm->phy_dbg_info.num_qry_beacon_pkt++; + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + if (dm->support_ability & ODM_BB_ANT_DIV) + odm_process_rssi_for_ant_div(dm, phy_info, pktinfo); +#endif + +#ifdef CONFIG_ADAPTIVE_SOML +phydm_rx_qam_for_soml(dm, pktinfo); +#endif + +#ifdef CONFIG_DYNAMIC_RX_PATH + phydm_process_phy_status_for_dynamic_rx_path(dm, phy_info, pktinfo); +#endif + + if (pktinfo->is_packet_to_self || pktinfo->is_packet_beacon) { + rssi_pre = sta->rssi_stat.rssi; + + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (phy_info->rx_mimo_signal_strength[i] != 0) + rssi_linear += odm_convert_to_linear(phy_info->rx_mimo_signal_strength[i]); + } + + switch (phy_info->rx_count + 1) { + case 2: + rssi_linear = (rssi_linear >> 1); + break; + case 3: + rssi_linear = ((rssi_linear) + (rssi_linear << 1) + (rssi_linear << 3)) >> 5; /* rssi_linear/3 ~ rssi_linear*11/32 */ + break; + case 4: + rssi_linear = (rssi_linear >> 2); + break; + } + + rssi_avg_db = (s16)odm_convert_to_db(rssi_linear); + + if (rssi_pre <= 0) { + sta->rssi_stat.rssi_acc = (s16)(phy_info->rx_pwdb_all << RSSI_MA_FACTOR); + sta->rssi_stat.rssi = (s8)(phy_info->rx_pwdb_all); + } else { + sta->rssi_stat.rssi_acc = sta->rssi_stat.rssi_acc - (sta->rssi_stat.rssi_acc >> RSSI_MA_FACTOR) + rssi_avg_db; + sta->rssi_stat.rssi = (s8)((sta->rssi_stat.rssi_acc + (1 << (RSSI_MA_FACTOR - 1))) >> RSSI_MA_FACTOR); + } + + #if 0 + if (pktinfo->is_packet_match_bssid) { + PHYDM_DBG(dm, DBG_TMP, "RSSI[%d]{A,B,Avg}=%d, %d, %d\n", + pktinfo->station_id, phy_info->rx_mimo_signal_strength[0], + phy_info->rx_mimo_signal_strength[1], rssi_ave); + PHYDM_DBG(dm, DBG_TMP, "{new, old}=%d, %d\n", sta->rssi_stat.rssi, rssi_pre); + } + #endif + + if (pktinfo->is_cck_rate) + sta->rssi_stat.rssi_cck = (s8)rssi_avg_db; + else + sta->rssi_stat.rssi_ofdm = (s8)rssi_avg_db; + + + } +} + +void +phydm_rx_phy_status_new_type( + void *dm_void, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#ifdef PHYDM_PHYSTAUS_SMP_MODE + struct pkt_process_info *pkt_process = &dm->pkt_proc_struct; +#endif + u8 phy_status_type = (*phy_status_inf & 0xf); + +#ifdef PHYDM_PHYSTAUS_SMP_MODE + if (pkt_process->phystatus_smp_mode_en && phy_status_type != 0) { + if (pkt_process->pre_ppdu_cnt == pktinfo->ppdu_cnt) + return; + + pkt_process->pre_ppdu_cnt = pktinfo->ppdu_cnt; + } +#endif + + phydm_reset_phy_info(dm, phy_info); /* Memory reset */ + + /* Phy status parsing */ + switch (phy_status_type) { + case 0: /*CCK*/ + phydm_get_rx_phy_status_type0(dm, phy_status_inf, pktinfo, phy_info); + break; + case 1: + phydm_get_rx_phy_status_type1(dm, phy_status_inf, pktinfo, phy_info); + break; + case 2: + phydm_get_rx_phy_status_type2(dm, phy_status_inf, pktinfo, phy_info); + break; + default: + break; + } + + #if (RTL8822B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822B) + phydm_print_phy_status_jarguar2(dm, phy_status_inf, pktinfo, phy_info, phy_status_type); + #endif + +} +/*==============================================*/ +#endif + +void +odm_phy_status_query( + struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo +) +{ + pktinfo->is_cck_rate = (pktinfo->data_rate <= ODM_RATE11M) ? true : false; + pktinfo->rate_ss = phydm_rate_to_num_ss(dm, pktinfo->data_rate); + dm->rate_ss = pktinfo->rate_ss; /*For AP EVM SW antenna diversity use*/ + + if (pktinfo->is_cck_rate) + dm->phy_dbg_info.num_qry_phy_status_cck++; + else + dm->phy_dbg_info.num_qry_phy_status_ofdm++; + + /*Reset phy_info*/ + odm_memory_set(dm, phy_info->rx_mimo_signal_strength, 0, 4); + odm_memory_set(dm, phy_info->rx_mimo_signal_quality, 0, 4); + + if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) { + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + phydm_rx_phy_status_new_type(dm, phy_status_inf, pktinfo, phy_info); + phydm_process_rssi_for_dm_new_type(dm, phy_info, pktinfo); + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + #if ODM_IC_11AC_SERIES_SUPPORT + phydm_rx_phy_status_jaguar_series_parsing(dm, phy_info, phy_status_inf, pktinfo); + phydm_process_rssi_for_dm(dm, phy_info, pktinfo); + #endif + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + #if ODM_IC_11N_SERIES_SUPPORT + phydm_rx_phy_status92c_series_parsing(dm, phy_info, phy_status_inf, pktinfo); + phydm_process_rssi_for_dm(dm, phy_info, pktinfo); + #endif + } + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + phydm_process_signal_strength(dm, phy_info, pktinfo); + #endif + + if (pktinfo->is_packet_match_bssid) { + + dm->rx_rate = pktinfo->data_rate; + dm->rssi_a = phy_info->rx_mimo_signal_strength[RF_PATH_A]; + dm->rssi_b = phy_info->rx_mimo_signal_strength[RF_PATH_B]; + dm->rssi_c = phy_info->rx_mimo_signal_strength[RF_PATH_C]; + dm->rssi_d = phy_info->rx_mimo_signal_strength[RF_PATH_D]; + + phydm_avg_phystatus_index(dm, phy_info, pktinfo); + phydm_rx_statistic_cal(dm, phy_info, phy_status_inf, pktinfo); + } +} + +void +phydm_rx_phy_status_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; +#ifdef PHYDM_PHYSTAUS_SMP_MODE + struct pkt_process_info *pkt_process = &dm->pkt_proc_struct; + + if (dm->support_ic_type == ODM_RTL8822B) { + pkt_process->phystatus_smp_mode_en = 1; + pkt_process->pre_ppdu_cnt = 0xff; + + odm_set_mac_reg(dm, 0x60f, BIT(7), 1); /*phystatus sampling mode enable*/ + + odm_set_bb_reg(dm, 0x9e4, 0x3ff, 0x0); /*First update timming*/ + odm_set_bb_reg(dm, 0x9e4, 0xfc00, 0x0); /*Update Sampling time*/ + } +#endif + + dbg->show_phy_sts_all_pkt = 0; + dbg->show_phy_sts_max_cnt = 1; + dbg->show_phy_sts_cnt = 0; + + +} diff --git a/hal/phydm/phydm_phystatus.h b/hal/phydm/phydm_phystatus.h new file mode 100644 index 0000000..453d75b --- /dev/null +++ b/hal/phydm/phydm_phystatus.h @@ -0,0 +1,1083 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + + +#ifndef __PHYDM_PHYSTATUS_H__ +#define __PHYDM_PHYSTATUS_H__ + + +/*--------------------------Define -------------------------------------------*/ +#define CCK_RSSI_INIT_COUNT 5 + +#define RA_RSSI_STATE_INIT 0 +#define RA_RSSI_STATE_SEND 1 +#define RA_RSSI_STATE_HOLD 2 + +#define CFO_HW_RPT_2_KHZ(val) ((val<<1) + (val>>1)) +/* (X* 312.5 Khz)>>7 ~= X*2.5 Khz= (X<<1 + X>>1)Khz */ + +#define IGI_2_RSSI(igi) (igi - 10) + +#define PHY_STATUS_JRGUAR2_DW_LEN 7 /* 7*4 = 28 Byte */ +#define SHOW_PHY_STATUS_UNLIMITED 0 +#define RSSI_MA_FACTOR 4 + +/* ************************************************************ + * structure and define + * ************************************************************ */ + +__PACK struct phy_rx_agc_info { +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain: 7, trsw: 1; +#else + u8 trsw: 1, gain: 7; +#endif +}; + +__PACK struct phy_status_rpt_8192cd { + struct phy_rx_agc_info path_agc[2]; + u8 ch_corr[2]; + u8 cck_sig_qual_ofdm_pwdb_all; + u8 cck_agc_rpt_ofdm_cfosho_a; + u8 cck_rpt_b_ofdm_cfosho_b; + u8 rsvd_1;/*ch_corr_msb;*/ + u8 noise_power_db_msb; + s8 path_cfotail[2]; + u8 pcts_mask[2]; + s8 stream_rxevm[2]; + u8 path_rxsnr[2]; + u8 noise_power_db_lsb; + u8 rsvd_2[3]; + u8 stream_csi[2]; + u8 stream_target_csi[2]; + s8 sig_evm; + u8 rsvd_3; + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/ + u8 sgi_en: 1; + u8 rxsc: 2; + u8 idle_long: 1; + u8 r_ant_train_en: 1; + u8 ant_sel_b: 1; + u8 ant_sel: 1; +#else /*_BIG_ENDIAN_ */ + u8 ant_sel: 1; + u8 ant_sel_b: 1; + u8 r_ant_train_en: 1; + u8 idle_long: 1; + u8 rxsc: 2; + u8 sgi_en: 1; + u8 antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/ +#endif +}; + +struct phy_status_rpt_8812 { + /* DWORD 0*/ + u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ + u8 chl_num_LSB; /*channel number[7:0]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 chl_num_MSB: 2; /*channel number[9:8]*/ + u8 sub_chnl: 4; /*sub-channel location[3:0]*/ + u8 r_RFMOD: 2; /*RF mode[1:0]*/ +#else /*_BIG_ENDIAN_ */ + u8 r_RFMOD: 2; + u8 sub_chnl: 4; + u8 chl_num_MSB: 2; +#endif + + /* DWORD 1*/ + u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/ + s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + /*this should be checked again because the definition of 8812 and 8814 is different*/ + /* u8 r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/ + /* u8 cck_rx_path:4; cck rx path[3:0]*/ + u8 resvd_0: 6; + u8 bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/ +#else /*_BIG_ENDIAN_*/ + u8 bt_RF_ch_MSB: 2; + u8 resvd_0: 6; +#endif + + /* DWORD 2*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/ + u8 ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/ + u8 bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ +#else /*_BIG_ENDIAN_ */ + u8 bt_RF_ch_LSB: 6; + u8 ant_div_sw_b: 1; + u8 ant_div_sw_a: 1; +#endif + s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ + u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ + u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ + + /* DWORD 3*/ + s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ + s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ + + /* DWORD 4*/ + u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/ + u8 pcts_rpt_valid: 1; /*pcts_rpt_valid*/ + u8 resvd_1: 1; /*1'b0*/ +#else /*_BIG_ENDIAN_*/ + u8 resvd_1: 1; + u8 pcts_rpt_valid: 1; + u8 PCTS_MSK_RPT_3: 6; +#endif + s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/ + + /* DWORD 5*/ + u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/ + u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/ + + /* DWORD 6*/ + s8 sigevm; /*signal field EVM*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/ + u8 antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/ + u8 dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/ + u8 GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/ +#else /*_BIG_ENDIAN_*/ + u8 GNT_BT_keep: 1; + u8 dpdt_ctrl_keep: 1; + u8 antidx_antd: 3; + u8 antidx_antc: 3; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_anta: 3; /*antidx_anta[2:0]*/ + u8 antidx_antb: 3; /*antidx_antb[2:0]*/ + u8 hw_antsw_occur: 2; /*1'b0*/ +#else /*_BIG_ENDIAN_*/ + u8 hw_antsw_occur: 2; + u8 antidx_antb: 3; + u8 antidx_anta: 3; +#endif +}; + + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + +__PACK struct phy_status_rpt_jaguar2_type0 { + /* DW0 */ + u8 page_num; + u8 pwdb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain: 6; + u8 rsvd_0: 1; + u8 trsw: 1; +#else + u8 trsw: 1; + u8 rsvd_0: 1; + u8 gain: 6; +#endif + u8 rsvd_1; + + /* DW1 */ + u8 rsvd_2; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rxsc: 4; + u8 agc_table: 4; +#else + u8 agc_table: 4; + u8 rxsc: 4; +#endif + u8 channel; + u8 band; + + /* DW2 */ + u16 length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a: 3; + u8 antidx_b: 3; + u8 rsvd_3: 2; + u8 antidx_c: 3; + u8 antidx_d: 3; + u8 rsvd_4:2; +#else + u8 rsvd_3: 2; + u8 antidx_b: 3; + u8 antidx_a: 3; + u8 rsvd_4:2; + u8 antidx_d: 3; + u8 antidx_c: 3; +#endif + + /* DW3 */ + u8 signal_quality; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga:5; + u8 lna_l:3; + u8 bb_power:6; + u8 rsvd_9:1; + u8 lna_h:1; +#else + u8 lna_l:3; + u8 vga:5; + u8 lna_h:1; + u8 rsvd_9:1; + u8 bb_power:6; +#endif + u8 rsvd_5; + + /* DW4 */ + u32 rsvd_6; + + /* DW5 */ + u32 rsvd_7; + + /* DW6 */ + u32 rsvd_8; +}; + +__PACK struct phy_status_rpt_jaguar2_type1 { + /* DW0 and DW1 */ + u8 page_num; + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc: 4; + u8 ht_rxsc: 4; +#else + u8 ht_rxsc: 4; + u8 l_rxsc: 4; +#endif + u8 channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band: 2; + u8 rsvd_0: 1; + u8 hw_antsw_occu: 1; + u8 gnt_bt: 1; + u8 ldpc: 1; + u8 stbc: 1; + u8 beamformed: 1; +#else + u8 beamformed: 1; + u8 stbc: 1; + u8 ldpc: 1; + u8 gnt_bt: 1; + u8 hw_antsw_occu: 1; + u8 rsvd_0: 1; + u8 band: 2; +#endif + + /* DW2 */ + u16 lsig_length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a: 3; + u8 antidx_b: 3; + u8 rsvd_1: 2; + u8 antidx_c: 3; + u8 antidx_d: 3; + u8 rsvd_2: 2; +#else + u8 rsvd_1: 2; + u8 antidx_b: 3; + u8 antidx_a: 3; + u8 rsvd_2: 2; + u8 antidx_d: 3; + u8 antidx_c: 3; +#endif + + /* DW3 */ + u8 paid; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 paid_msb: 1; + u8 gid: 6; + u8 rsvd_3: 1; +#else + u8 rsvd_3: 1; + u8 gid: 6; + u8 paid_msb: 1; +#endif + u8 intf_pos; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 intf_pos_msb: 1; + u8 rsvd_4: 2; + u8 nb_intf_flag: 1; + u8 rf_mode: 2; + u8 rsvd_5: 2; +#else + u8 rsvd_5: 2; + u8 rf_mode: 2; + u8 nb_intf_flag: 1; + u8 rsvd_4: 2; + u8 intf_pos_msb: 1; +#endif + + /* DW4 */ + s8 rxevm[4]; /* s(8,1) */ + + /* DW5 */ + s8 cfo_tail[4]; /* s(8,7) */ + + /* DW6 */ + s8 rxsnr[4]; /* s(8,1) */ +}; + +__PACK struct phy_status_rpt_jaguar2_type2 { + /* DW0 ane DW1 */ + u8 page_num; + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc: 4; + u8 ht_rxsc: 4; +#else + u8 ht_rxsc: 4; + u8 l_rxsc: 4; +#endif + u8 channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band: 2; + u8 rsvd_0: 1; + u8 hw_antsw_occu: 1; + u8 gnt_bt: 1; + u8 ldpc: 1; + u8 stbc: 1; + u8 beamformed: 1; +#else + u8 beamformed: 1; + u8 stbc: 1; + u8 ldpc: 1; + u8 gnt_bt: 1; + u8 hw_antsw_occu: 1; + u8 rsvd_0: 1; + u8 band: 2; +#endif + + /* DW2 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 shift_l_map: 6; + u8 rsvd_1: 2; +#else + u8 rsvd_1: 2; + u8 shift_l_map: 6; +#endif + u8 cnt_pw2cca; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_a: 4; + u8 agc_table_b: 4; + u8 agc_table_c: 4; + u8 agc_table_d: 4; +#else + u8 agc_table_b: 4; + u8 agc_table_a: 4; + u8 agc_table_d: 4; + u8 agc_table_c: 4; +#endif + + /* DW3 ~ DW6*/ + u8 cnt_cca2agc_rdy; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_a: 6; + u8 rsvd_2: 1; + u8 trsw_a: 1; + u8 gain_b: 6; + u8 rsvd_3: 1; + u8 trsw_b: 1; + u8 gain_c: 6; + u8 rsvd_4: 1; + u8 trsw_c: 1; + u8 gain_d: 6; + u8 rsvd_5: 1; + u8 trsw_d: 1; + u8 aagc_step_a: 2; + u8 aagc_step_b: 2; + u8 aagc_step_c: 2; + u8 aagc_step_d: 2; +#else + u8 trsw_a: 1; + u8 rsvd_2: 1; + u8 gain_a: 6; + u8 trsw_b: 1; + u8 rsvd_3: 1; + u8 gain_b: 6; + u8 trsw_c: 1; + u8 rsvd_4: 1; + u8 gain_c: 6; + u8 trsw_d: 1; + u8 rsvd_5: 1; + u8 gain_d: 6; + u8 aagc_step_d: 2; + u8 aagc_step_c: 2; + u8 aagc_step_b: 2; + u8 aagc_step_a: 2; +#endif + u8 ht_aagc_gain[4]; + u8 dagc_gain[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 counter: 6; + u8 rsvd_6: 2; + u8 syn_count: 5; + u8 rsvd_7:3; +#else + u8 rsvd_6: 2; + u8 counter: 6; + u8 rsvd_7:3; + u8 syn_count: 5; +#endif +}; +#endif + +/*==============================================*/ +#if (CONFIG_PHYSTS_3RD_TYPE) +__PACK struct _phy_status_rpt_jaguar3_type0 { + /* DW0 : Offset 0 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num:4; + u8 pkt_cnt:2; + u8 channel_msb:2; +#else + u8 channel_msb:2; + u8 pkt_cnt:2; + u8 page_num:4; +#endif + u8 pwdb_a; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_a: 6; + u8 rsvd_0: 1; + u8 trsw: 1; +#else + u8 trsw: 1; + u8 rsvd_0: 1; + u8 gain_a: 6; +#endif + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_b:4; + u8 agc_table_c:4; +#else + u8 agc_table_c:4; + u8 agc_table_b:4; +#endif + + /* DW1 : Offset 4 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rsvd_1: 4; + u8 agc_table_d: 4; +#else + u8 agc_table_d: 4; + u8 rsvd_1: 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc: 4; + u8 agc_table_a: 4; +#else + u8 agc_table_a: 4; + u8 l_rxsc: 4; +#endif + u8 channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band:2; + u8 rsvd_2_1: 1; + u8 hw_antsw_occur_keep_cck:1; + u8 gnt_bt_keep_cck:1; + u8 rsvd_2_2:3; +#else + u8 rsvd_2_2:3; + u8 gnt_bt_keep_cck:1; + u8 hw_antsw_occur_keep_cck:1; + u8 rsvd_2_1: 1; + u8 band:2; +#endif + + /* DW2 : Offset 8 */ + u16 length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a: 4; + u8 antidx_b: 4; + u8 antidx_c: 4; + u8 antidx_d: 4; +#else + u8 antidx_b: 4; + u8 antidx_a: 4; + u8 antidx_d: 4; + u8 antidx_c: 4; +#endif + + /* DW3 : Offset 12 */ + u8 signal_quality; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga_a:5; + u8 lna_l_a:3; + u8 bb_power_a:6; + u8 rsvd_3_1:1; + u8 lna_h_a:1; +#else + u8 lna_l_a:3; + u8 vga_a:5; + u8 lna_h_a:1; + u8 rsvd_3_1:1; + u8 bb_power_a:6; +#endif + u8 rsvd_3_2; + + /* DW4 : Offset 16 */ + u8 pwdb_b; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga_b:5; + u8 lna_l_b:3; + u8 bb_power_b:6; + u8 rsvd_4_1:1; + u8 lna_h_b:1; + u8 gain_b: 6; + u8 rsvd_4_2:2; +#else + u8 lna_l_b:3; + u8 vga_b:5; + u8 lna_h_b:1; + u8 rsvd_4_1:1; + u8 bb_power_b:6; + u8 rsvd_4_2:2; + u8 gain_b: 6; +#endif + + /* DW5 : Offset 20 */ + u8 pwdb_c; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga_c:5; + u8 lna_l_c:3; + u8 bb_power_c:6; + u8 rsvd_5_1:1; + u8 lna_h_c:1; + u8 gain_c: 6; + u8 rsvd_5_2:2; +#else + u8 lna_l_c:3; + u8 vga_c:5; + u8 lna_h_c:1; + u8 rsvd_5_1:1; + u8 bb_power_c:6; + u8 rsvd_5_2:2; + u8 gain_c: 6; +#endif + + /* DW6 : Offset 24 */ + u8 pwdb_d; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga_d:5; + u8 lna_l_d:3; + u8 bb_power_d:6; + u8 rsvd_6_1:1; + u8 lna_h_d:1; + u8 gain_d: 6; + u8 rsvd_6_2:2; +#else + u8 lna_l_d:3; + u8 vga_d:5; + u8 lna_h_d:1; + u8 rsvd_6_1:1; + u8 bb_power_d:6; + u8 rsvd_6_2:2; + u8 gain_d: 6; +#endif +}; + +__PACK struct _phy_status_rpt_jaguar3_type1 { + /* DW0 : Offset 0 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num:4; + u8 pkt_cnt:2; + u8 channel_pri_msb:2; +#else + u8 channel_pri_msb:2; + u8 pkt_cnt:2; + u8 page_num:4; +#endif + u8 pwdb_a; + u8 pwdb_b; + u8 pwdb_c; + + /* DW1 : Offset 4 */ + u8 pwdb_d; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc: 4; + u8 ht_rxsc: 4; +#else + u8 ht_rxsc: 4; + u8 l_rxsc: 4; +#endif + u8 channel_pri_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band: 2; + u8 rsvd_0: 2; + u8 gnt_bt: 1; + u8 ldpc: 1; + u8 stbc: 1; + u8 beamformed: 1; +#else + u8 beamformed: 1; + u8 stbc: 1; + u8 ldpc: 1; + u8 gnt_bt: 1; + u8 rsvd_0: 2; + u8 band: 2; +#endif + + /* DW2 : Offset 8 */ + u8 channel_sec_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 channel_sec_msb:2; + u8 rsvd_1: 2; + u8 hw_antsw_occur_a:1; + u8 hw_antsw_occur_b:1; + u8 hw_antsw_occur_c:1; + u8 hw_antsw_occur_d:1; +#else + u8 hw_antsw_occur_d:1; + u8 hw_antsw_occur_c:1; + u8 hw_antsw_occur_b:1; + u8 hw_antsw_occur_a:1; + u8 rsvd_1: 2; + u8 channel_sec_msb:2; + +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a: 4; + u8 antidx_b: 4; + u8 antidx_c: 4; + u8 antidx_d: 4; +#else + u8 antidx_b: 4; + u8 antidx_a: 4; + u8 antidx_d: 4; + u8 antidx_c: 4; +#endif + + /* DW3 : Offset 12 */ + u8 paid; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 paid_msb: 1; + u8 gid: 6; + u8 rsvd_3: 1; +#else + u8 rsvd_3: 1; + u8 gid: 6; + u8 paid_msb: 1; +#endif + u16 rsvd_4; +/* + u8 rsvd_4; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rsvd_5: 6; + u8 rf_mode: 2; +#else + u8 rf_mode: 2; + u8 rsvd_5: 6; +#endif +*/ + /* DW4 */ + s8 rxevm[4]; /* s(8,1) */ + + /* DW5 */ + s8 cfo_tail[4]; /* s(8,7) */ + + /* DW6 */ + s8 rxsnr[4]; /* s(8,1) */ +}; +__PACK struct _phy_status_rpt_jaguar3_type2_type3 { + /* Type2 is primary channel & type3 is secondary channel */ + /* DW0 ane DW1 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num:4; + u8 pkt_cnt:2; + u8 channel_msb:2; +#else + u8 channel_msb:2; + u8 pkt_cnt:2; + u8 page_num:4; +#endif + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc: 4; + u8 ht_rxsc: 4; +#else + u8 ht_rxsc: 4; + u8 l_rxsc: 4; +#endif + u8 channel_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band: 2; + u8 rsvd_0: 1; + u8 hw_antsw_occu: 1; + u8 gnt_bt: 1; + u8 ldpc: 1; + u8 stbc: 1; + u8 beamformed: 1; +#else + u8 beamformed: 1; + u8 stbc: 1; + u8 ldpc: 1; + u8 gnt_bt: 1; + u8 hw_antsw_occu: 1; + u8 rsvd_0: 1; + u8 band: 2; +#endif + + /* DW2 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 shift_l_map: 6; + u8 rsvd_1: 2; +#else + u8 rsvd_1: 2; + u8 shift_l_map: 6; +#endif + s8 pwed_th; /* dynamic energy threshold S(8,2) */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_a: 4; + u8 agc_table_b: 4; + u8 agc_table_c: 4; + u8 agc_table_d: 4; +#else + u8 agc_table_b: 4; + u8 agc_table_a: 4; + u8 agc_table_d: 4; + u8 agc_table_c: 4; +#endif + + /* DW3 ~ DW6*/ + u8 cnt_cca2agc_rdy; /* Time(ns) = cnt_cca2agc_ready*25 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 mp_gain_a: 6; + u8 mp_gain_b_lsb: 2; + u8 mp_gain_b_msb: 4; + u8 mp_gain_c_lsb: 4; + u8 mp_gain_c_msb: 2; + u8 avg_noise_pwr_lsb: 4; + u8 rsvd_3:2; + /* u8 r_rfmod:2; */ + u8 mp_gain_d: 6; + u8 is_freq_select_fading: 1; + u8 rsvd_2: 1; + u8 aagc_step_a: 2; + u8 aagc_step_b: 2; + u8 aagc_step_c: 2; + u8 aagc_step_d: 2; +#else + u8 mp_gain_b_lsb: 2; + u8 mp_gain_a: 6; + u8 mp_gain_c_lsb: 4; + u8 mp_gain_b_msb: 4; + u8 rsvd_3:2; + /* u8 r_rfmod:2; */ + u8 avg_noise_pwr_lsb: 4; + u8 mp_gain_c_msb: 2; + u8 rsvd_2: 1; + u8 is_freq_select_fading: 1; + u8 mp_gain_d: 6; + u8 aagc_step_d: 2; + u8 aagc_step_c: 2; + u8 aagc_step_b: 2; + u8 aagc_step_a: 2; +#endif + u8 ht_aagc_gain[4]; + u8 dagc_gain[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 counter: 6; + u8 syn_count_lsb: 2; + u8 syn_count_msb: 3; + u8 avg_noise_pwr_msb:5; +#else + u8 syn_count_lsb: 2; + u8 counter: 6; + u8 avg_noise_pwr_msb:5; + u8 syn_count_msb: 3; +#endif +}; + +__PACK struct _phy_status_rpt_jaguar3_type4 { + /* smart antenna */ + /* DW0 ane DW1 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num:4; + u8 pkt_cnt:2; + u8 channel_msb:2; +#else + u8 channel_msb:2; + u8 pkt_cnt:2; + u8 page_num:4; +#endif + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc: 4; + u8 ht_rxsc: 4; +#else + u8 ht_rxsc: 4; + u8 l_rxsc: 4; +#endif + u8 channel_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band: 2; + u8 rsvd_0: 1; + u8 hw_antsw_occu: 1; + u8 gnt_bt: 1; + u8 ldpc: 1; + u8 stbc: 1; + u8 beamformed: 1; +#else + u8 beamformed: 1; + u8 stbc: 1; + u8 ldpc: 1; + u8 gnt_bt: 1; + u8 hw_antsw_occu: 1; + u8 rsvd_0: 1; + u8 band: 2; +#endif + + /* DW2 ~ DW3 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bad_tone_cnt_min_eign_0:4; + u8 bad_tone_cnt_cn_excess_0:4; + u8 training_done_a:1; + u8 training_done_b:1; + u8 training_done_c:1; + u8 training_done_d:1; + u8 hw_antsw_occur_a:1; + u8 hw_antsw_occur_b:1; + u8 hw_antsw_occur_c:1; + u8 hw_antsw_occur_d:1; + u8 antidx_a: 4; + u8 antidx_b: 4; + u8 antidx_c: 4; + u8 antidx_d: 4; +#else + u8 bad_tone_cnt_cn_excess_0:4; + u8 bad_tone_cnt_min_eign_0:4; + u8 hw_antsw_occur_d:1; + u8 hw_antsw_occur_c:1; + u8 hw_antsw_occur_b:1; + u8 hw_antsw_occur_a:1; + u8 training_done_d:1; + u8 training_done_c:1; + u8 training_done_b:1; + u8 training_done_a:1; + u8 antidx_b: 4; + u8 antidx_a: 4; + u8 antidx_d: 4; + u8 antidx_c: 4; +#endif + u8 tx_pkt_cnt; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bad_tone_cnt_min_eign_1:4; + u8 bad_tone_cnt_cn_excess_1:4; + u8 avg_cond_num_0:7; + u8 avg_cond_num_1_lsb:1; + u8 avg_cond_num_1_msb:6; + u8 rsvd_1:2; +#else + u8 bad_tone_cnt_cn_excess_1:4; + u8 bad_tone_cnt_min_eign_1:4; + u8 avg_cond_num_1_lsb:1; + u8 avg_cond_num_0:7; + u8 rsvd_1:2; + u8 avg_cond_num_1_msb:6; +#endif + + /* DW4 */ + s8 rxevm[4]; /* s(8,1) */ + + /* DW5 */ + u8 eigenvalue[4]; /* eigenvalue or eigenvalue of seg0 (in dB) */ + + /* DW6 */ + s8 rxsnr[4]; /* s(8,1) */ +}; + +__PACK struct _phy_status_rpt_jaguar2_type5 { + /* smart antenna */ + /* DW0 ane DW1 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num:4; + u8 pkt_cnt:2; + u8 channel_msb:2; +#else + u8 channel_msb:2; + u8 pkt_cnt:2; + u8 page_num:4; +#endif + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc: 4; + u8 ht_rxsc: 4; +#else + u8 ht_rxsc: 4; + u8 l_rxsc: 4; +#endif + u8 channel_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band: 2; + u8 rsvd_0: 1; + u8 hw_antsw_occu: 1; + u8 gnt_bt: 1; + u8 ldpc: 1; + u8 stbc: 1; + u8 beamformed: 1; +#else + u8 beamformed: 1; + u8 stbc: 1; + u8 ldpc: 1; + u8 gnt_bt: 1; + u8 hw_antsw_occu: 1; + u8 rsvd_0: 1; + u8 band: 2; +#endif + /* DW2 ~ DW5 */ + u8 rsvd_1; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rsvd_2:4; + u8 hw_antsw_occur_a:1; + u8 hw_antsw_occur_b:1; + u8 hw_antsw_occur_c:1; + u8 hw_antsw_occur_d:1; + u8 antidx_a: 4; + u8 antidx_b: 4; + u8 antidx_c: 4; + u8 antidx_d: 4; +#else + u8 hw_antsw_occur_d:1; + u8 hw_antsw_occur_c:1; + u8 hw_antsw_occur_b:1; + u8 hw_antsw_occur_a:1; + u8 rsvd_2:4; + u8 antidx_b: 4; + u8 antidx_a: 4; + u8 antidx_d: 4; + u8 antidx_c: 4; +#endif + u8 tx_pkt_cnt; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 inf_pos_0_A_flg:1; + u8 inf_pos_1_A_flg:1; + u8 inf_pos_0_B_flg:1; + u8 inf_pos_1_B_flg:1; + u8 inf_pos_0_C_flg:1; + u8 inf_pos_1_C_flg:1; + u8 inf_pos_0_D_flg:1; + u8 inf_pos_1_D_flg:1; +#else + u8 inf_pos_1_D_flg:1; + u8 inf_pos_0_D_flg:1; + u8 inf_pos_1_C_flg:1; + u8 inf_pos_0_C_flg:1; + u8 inf_pos_1_B_flg:1; + u8 inf_pos_0_B_flg:1; + u8 inf_pos_1_A_flg:1; + u8 inf_pos_0_A_flg:1; +#endif + u8 rsvd_3; + u8 rsvd_4; + u8 inf_pos_0_a; + u8 inf_pos_1_a; + u8 inf_pos_0_b; + u8 inf_pos_1_b; + u8 inf_pos_0_c; + u8 inf_pos_1_c; + u8 inf_pos_0_d; + u8 inf_pos_1_d; +}; +#endif /*#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)*/ + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + +void +phydm_rx_phy_status_new_type( + void *dm_void, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info +); + +boolean +phydm_query_is_mu_api( + struct dm_struct *phydm, + u8 ppdu_idx, + u8 *p_data_rate, + u8 *p_gid +); +#endif + +void +phydm_reset_phystatus_avg( + struct dm_struct *dm +); + +void +phydm_reset_phystatus_statistic( + struct dm_struct *dm +); + +void +phydm_reset_rssi_for_dm( + struct dm_struct *dm, + u8 station_id +); + +void +phydm_get_cck_rssi_table_from_reg( + struct dm_struct *dm +); + +u8 +phydm_rate_to_num_ss( + struct dm_struct *dm, + u8 data_rate +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void +phydm_normal_driver_rx_sniffer( + struct dm_struct *dm, + u8 *desc, + PRT_RFD_STATUS rt_rfd_status, + u8 *drv_info, + u8 phy_status +); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +s32 +phydm_signal_scale_mapping( + struct dm_struct *dm, + s32 curr_sig +); +#endif + +void +odm_phy_status_query( + struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo +); + +void +phydm_rx_phy_status_init( + void *dm_void +); + +#endif /*#ifndef __HALHWOUTSRC_H__*/ diff --git a/hal/phydm/phydm_pow_train.c b/hal/phydm/phydm_pow_train.c new file mode 100644 index 0000000..477f5d1 --- /dev/null +++ b/hal/phydm/phydm_pow_train.c @@ -0,0 +1,228 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_POWER_TRAINING_SUPPORT +void +phydm_reset_pt_para( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pow_train_stuc *pow_train_t = &dm->pow_train_table; + + pow_train_t->pow_train_score = 0; + dm->phy_dbg_info.num_qry_phy_status_ofdm = 0; + dm->phy_dbg_info.num_qry_phy_status_cck = 0; +} + +void +phydm_update_power_training_state( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pow_train_stuc *pow_train_t = &dm->pow_train_table; + struct phydm_fa_struct *fa_cnt = &dm->false_alm_cnt; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u32 pt_score_tmp = 0; + u32 crc_ok_cnt; + u32 cca_all_cnt; + + + /*is_disable_power_training is the key to H2C to disable/enable power training*/ + /*if is_disable_power_training == 1, it will use largest power*/ + if (!(dm->support_ability & ODM_BB_PWR_TRAIN)) { + dm->is_disable_power_training = true; + phydm_reset_pt_para(dm); + return; + } + + PHYDM_DBG(dm, DBG_PWR_TRAIN, "%s ======>\n", __FUNCTION__); + + if (pow_train_t->force_power_training_state == DISABLE_POW_TRAIN) { + + dm->is_disable_power_training = true; + phydm_reset_pt_para(dm); + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable PT\n"); + return; + + } else if (pow_train_t->force_power_training_state == ENABLE_POW_TRAIN) { + + dm->is_disable_power_training = false; + phydm_reset_pt_para(dm); + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Enable PT\n"); + return; + + } else if (pow_train_t->force_power_training_state == DYNAMIC_POW_TRAIN) { + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Dynamic PT\n"); + + if (!dm->is_linked) { + dm->is_disable_power_training = true; + pow_train_t->pow_train_score = 0; + dm->phy_dbg_info.num_qry_phy_status_ofdm = 0; + dm->phy_dbg_info.num_qry_phy_status_cck = 0; + + PHYDM_DBG(dm, DBG_PWR_TRAIN, "PT is disabled due to no link.\n"); + return; + } + + /* First connect */ + if ((dm->is_linked) && (!dig_t->is_media_connect)) { + pow_train_t->pow_train_score = 0; + dm->phy_dbg_info.num_qry_phy_status_ofdm = 0; + dm->phy_dbg_info.num_qry_phy_status_cck = 0; + PHYDM_DBG(dm, DBG_PWR_TRAIN, "(PT)First Connect\n"); + return; + } + + /* Compute score */ + crc_ok_cnt = dm->phy_dbg_info.num_qry_phy_status_ofdm + dm->phy_dbg_info.num_qry_phy_status_cck; + cca_all_cnt = fa_cnt->cnt_cca_all; + + if (crc_ok_cnt < cca_all_cnt) { + /* crc_ok <= (2/3)*cca */ + if ((crc_ok_cnt + (crc_ok_cnt >> 1)) <= cca_all_cnt) + pt_score_tmp = DISABLE_PT_SCORE; + + /* crc_ok <= (4/5)*cca */ + else if ((crc_ok_cnt + (crc_ok_cnt >> 2)) <= cca_all_cnt) + pt_score_tmp = KEEP_PRE_PT_SCORE; + + /* crc_ok > (4/5)*cca */ + else + pt_score_tmp = ENABLE_PT_SCORE; + } else { + pt_score_tmp = ENABLE_PT_SCORE; + } + + PHYDM_DBG(dm, DBG_PWR_TRAIN, "crc_ok_cnt = %d, cnt_cca_all = %d\n", + crc_ok_cnt, cca_all_cnt); + + PHYDM_DBG(dm, DBG_PWR_TRAIN, "num_qry_phy_status_ofdm = %d, num_qry_phy_status_cck = %d\n", + dm->phy_dbg_info.num_qry_phy_status_ofdm, dm->phy_dbg_info.num_qry_phy_status_cck); + + PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp = %d\n", pt_score_tmp); + PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp = 0(DISABLE), 1(KEEP), 2(ENABLE)\n"); + + /* smoothing */ + pow_train_t->pow_train_score = (pt_score_tmp << 4) + (pow_train_t->pow_train_score >> 1) + (pow_train_t->pow_train_score >> 2); + pt_score_tmp = (pow_train_t->pow_train_score + 32) >> 6; + PHYDM_DBG(dm, DBG_PWR_TRAIN, "pow_train_score = %d, score after smoothing = %d\n", + pow_train_t->pow_train_score, pt_score_tmp); + + /* mode decision */ + if (pt_score_tmp == ENABLE_PT_SCORE) { + + dm->is_disable_power_training = false; + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Enable power training under dynamic.\n"); + + } else if (pt_score_tmp == DISABLE_PT_SCORE) { + + dm->is_disable_power_training = true; + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable PT due to noisy.\n"); + } + + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Final, score = %d, is_disable_power_training = %d\n", + pt_score_tmp, dm->is_disable_power_training); + + dm->phy_dbg_info.num_qry_phy_status_ofdm = 0; + dm->phy_dbg_info.num_qry_phy_status_cck = 0; + } else { + + dm->is_disable_power_training = true; + phydm_reset_pt_para(dm); + + PHYDM_DBG(dm, DBG_PWR_TRAIN, "PT is disabled due to unknown pt state.\n"); + return; + } +} + +void +phydm_pow_train_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pow_train_stuc *pow_train_t = &dm->pow_train_table; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 i; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "0: Dynamic state\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "1: Enable PT\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "2: Disable PT\n"); + + } else { + for (i = 0; i < 10; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + } + } + + if (var1[0] == 0) { + pow_train_t->force_power_training_state = DYNAMIC_POW_TRAIN; + PDM_SNPF(out_len, used, output + used, + out_len - used, "Dynamic state\n"); + } else if (var1[0] == 1) { + pow_train_t->force_power_training_state = ENABLE_POW_TRAIN; + PDM_SNPF(out_len, used, output + used, + out_len - used, "Enable PT\n"); + } else if (var1[0] == 2) { + pow_train_t->force_power_training_state = DISABLE_POW_TRAIN; + PDM_SNPF(out_len, used, output + used, + out_len - used, "Disable PT\n"); + } else { + PDM_SNPF(out_len, used, output + used, + out_len - used, "Set Error\n"); + } + } + + *_used = used; + *_out_len = out_len; +} + + +#endif + + + diff --git a/hal/phydm/phydm_pow_train.h b/hal/phydm/phydm_pow_train.h new file mode 100644 index 0000000..0b4e938 --- /dev/null +++ b/hal/phydm/phydm_pow_train.h @@ -0,0 +1,86 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + + +#ifndef __PHYDM_POW_TRAIN_H__ +#define __PHYDM_POW_TRAIN_H__ + +#define POW_TRAIN_VERSION "1.0" /* 2017.07.0141 Dino, Add phydm_pow_train.h*/ + + +/* 1 ============================================================ + * 1 Definition + * 1 ============================================================ */ + + +#ifdef PHYDM_POWER_TRAINING_SUPPORT +/* 1 ============================================================ + * 1 structure + * 1 ============================================================ */ + + +struct phydm_pow_train_stuc { + u8 force_power_training_state; + u32 pow_train_score; +}; + +/* 1 ============================================================ + * 1 enumeration + * 1 ============================================================ */ + + +enum pow_train_state { + DYNAMIC_POW_TRAIN = 0, + ENABLE_POW_TRAIN = 1, + DISABLE_POW_TRAIN = 2 +}; + +enum power_training_score { + DISABLE_PT_SCORE = 0, + KEEP_PRE_PT_SCORE = 1, + ENABLE_PT_SCORE = 2 +}; + +/* 1 ============================================================ + * 1 function prototype + * 1 ============================================================ */ + +void +phydm_update_power_training_state( + void *dm_void +); + +void +phydm_pow_train_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); + +#endif +#endif diff --git a/hal/phydm/phydm_primary_cca.c b/hal/phydm/phydm_primary_cca.c new file mode 100644 index 0000000..71677be --- /dev/null +++ b/hal/phydm/phydm_primary_cca.c @@ -0,0 +1,730 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" +#ifdef PHYDM_PRIMARY_CCA + +void +phydm_write_dynamic_cca( + void *dm_void, + u8 curr_mf_state + +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *primary_cca = &dm->dm_pri_cca; + + if (primary_cca->mf_state == curr_mf_state) + return; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (curr_mf_state == MF_USC_LSC) { + odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), MF_USC_LSC); + odm_set_bb_reg(dm, 0xc84, 0xf0000000, primary_cca->cca_th_40m_bkp); /*40M OFDM MF CCA threshold*/ + } else { + odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), curr_mf_state); + odm_set_bb_reg(dm, 0xc84, 0xf0000000, 0); /*40M OFDM MF CCA threshold*/ + } + } + + primary_cca->mf_state = curr_mf_state; + PHYDM_DBG(dm, DBG_PRI_CCA, + "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n", ((curr_mf_state == MF_USC_LSC)?"D":((curr_mf_state == MF_LSC)?"L":"U")), curr_mf_state); +} + +void +phydm_primary_cca_reset( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *primary_cca = &dm->dm_pri_cca; + + PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Reset\n"); + primary_cca->mf_state = 0xff; + primary_cca->pre_bw = (enum channel_width)0xff; + phydm_write_dynamic_cca(dm, MF_USC_LSC); +} + +void +phydm_primary_cca_11n( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *primary_cca = &dm->dm_pri_cca; + enum channel_width curr_bw = (enum channel_width)*dm->band_width; + + if (!(dm->support_ability & ODM_BB_PRIMARY_CCA)) + return; + + if (!dm->is_linked) { /* is_linked==False */ + PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][No Link!!!]\n"); + + if (primary_cca->pri_cca_is_become_linked == true) { + phydm_primary_cca_reset(dm); + primary_cca->pri_cca_is_become_linked = dm->is_linked; + } + return; + + } else { + if (primary_cca->pri_cca_is_become_linked == false) { + PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][Linked !!!]\n"); + primary_cca->pri_cca_is_become_linked = dm->is_linked; + } + } + + if (curr_bw != primary_cca->pre_bw) { + PHYDM_DBG(dm, DBG_PRI_CCA, "[Primary CCA] start ==>\n"); + primary_cca->pre_bw = curr_bw; + + if (curr_bw == CHANNEL_WIDTH_40) { + + if (*dm->sec_ch_offset == SECOND_CH_AT_LSB) {/* Primary CH @ upper sideband*/ + + PHYDM_DBG(dm, DBG_PRI_CCA, "BW40M, Primary CH at USB\n"); + phydm_write_dynamic_cca(dm, MF_USC); + + } else { /*Primary CH @ lower sideband*/ + + PHYDM_DBG(dm, DBG_PRI_CCA, "BW40M, Primary CH at LSB\n"); + phydm_write_dynamic_cca(dm, MF_LSC); + } + } else { + + PHYDM_DBG(dm, DBG_PRI_CCA, "Not BW40M, USB + LSB\n"); + phydm_primary_cca_reset(dm); + } + } +} + +#if 0 +#if (RTL8188E_SUPPORT == 1) +void +odm_dynamic_primary_cca_8188e( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sta_info *entry; + struct cmn_sta_info *sta; + struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT); + struct phydm_pricca_struct *primary_cca = &(dm->dm_pri_cca); + boolean client_40mhz = false, client_tmp = false; /* connected client BW */ + boolean is_connected = false; /* connected or not */ + u8 client_40mhz_pre = 0; + u32 counter = 0; + u8 delay = 1; + u64 cur_tx_ok_cnt; + u64 cur_rx_ok_cnt; + u8 sec_ch_offset = *(dm->sec_ch_offset); + u8 i; + + if (!dm->is_linked) + return; + + if (!(dm->support_ability & ODM_BB_PRIMARY_CCA)) + return; + + if (*(dm->band_width) == CHANNEL_WIDTH_20) { /*curr bw*/ + odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 0); + return; + } + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) || (DM_ODM_SUPPORT_TYPE == ODM_CE) + sec_ch_offset = sec_ch_offset % 2 + 1; /* NIC's definition is reverse to AP 1:secondary below, 2: secondary above */ + #endif + + PHYDM_DBG(dm, DBG_PRI_CCA, "Second CH Offset = %d\n", sec_ch_offset); + + /* 3 Check Current WLAN Traffic */ + cur_tx_ok_cnt = dm->tx_tp; + cur_rx_ok_cnt = dm->rx_tp; + + /* ==================Debug Message==================== */ + PHYDM_DBG(dm, DBG_PRI_CCA, "TP = %llu\n", cur_tx_ok_cnt + cur_rx_ok_cnt); + PHYDM_DBG(dm, DBG_PRI_CCA, "is_BW40 = %d\n", *(dm->band_width)); + PHYDM_DBG(dm, DBG_PRI_CCA, "BW_LSC = %d\n", false_alm_cnt->cnt_bw_lsc); + PHYDM_DBG(dm, DBG_PRI_CCA, "BW_USC = %d\n", false_alm_cnt->cnt_bw_usc); + PHYDM_DBG(dm, DBG_PRI_CCA, "CCA OFDM = %d\n", false_alm_cnt->cnt_ofdm_cca); + PHYDM_DBG(dm, DBG_PRI_CCA, "CCA CCK = %d\n", false_alm_cnt->cnt_cck_cca); + PHYDM_DBG(dm, DBG_PRI_CCA, "OFDM FA = %d\n", false_alm_cnt->cnt_ofdm_fail); + PHYDM_DBG(dm, DBG_PRI_CCA, "CCK FA = %d\n", false_alm_cnt->cnt_cck_fail); + /* ================================================ */ + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (ACTING_AS_AP(dm->adapter)) /* primary cca process only do at AP mode */ +#endif + { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHYDM_DBG(dm, DBG_PRI_CCA, "ACTING as AP mode=%d\n", ACTING_AS_AP(dm->adapter)); + /* 3 To get entry's connection and BW infomation status. */ + for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) { + if (IsAPModeExist(dm->adapter) && GetFirstExtAdapter(dm->adapter) != NULL) + entry = AsocEntry_EnumStation(GetFirstExtAdapter(dm->adapter), i); + else + entry = AsocEntry_EnumStation(GetDefaultAdapter(dm->adapter), i); + if (entry != NULL) { + client_tmp = entry->BandWidth; /* client BW */ + PHYDM_DBG(dm, DBG_PRI_CCA, "Client_BW=%d\n", client_tmp); + if (client_tmp > client_40mhz) + client_40mhz = client_tmp; /* 40M/20M coexist => 40M priority is High */ + + if (entry->bAssociated) { + is_connected = true; /* client is connected or not */ + break; + } + } else + break; + } +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + /* 3 To get entry's connection and BW infomation status. */ + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + sta = dm->phydm_sta_info[i]; + if (is_sta_active(sta)) { + client_tmp = sta->bw_mode; + if (client_tmp > client_40mhz) + client_40mhz = client_tmp; /* 40M/20M coexist => 40M priority is High */ + + is_connected = true; + } + } +#endif + PHYDM_DBG(dm, DBG_PRI_CCA, "is_connected=%d\n", is_connected); + PHYDM_DBG(dm, DBG_PRI_CCA, "Is Client 40MHz=%d\n", client_40mhz); + /* 1 Monitor whether the interference exists or not */ + if (primary_cca->monitor_flag == 1) { + if (sec_ch_offset == 1) { /* secondary channel is below the primary channel */ + if ((false_alm_cnt->cnt_ofdm_cca > 500) && (false_alm_cnt->cnt_bw_lsc > false_alm_cnt->cnt_bw_usc + 500)) { + if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) { + primary_cca->intf_type = 1; + primary_cca->pri_cca_flag = 1; + odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT7, 2); /* USC MF */ + if (primary_cca->dup_rts_flag == 1) + primary_cca->dup_rts_flag = 0; + } else { + primary_cca->intf_type = 2; + if (primary_cca->dup_rts_flag == 0) + primary_cca->dup_rts_flag = 1; + } + + } else { /* interferecne disappear */ + primary_cca->dup_rts_flag = 0; + primary_cca->intf_flag = 0; + primary_cca->intf_type = 0; + } + } else if (sec_ch_offset == 2) { /* secondary channel is above the primary channel */ + if ((false_alm_cnt->cnt_ofdm_cca > 500) && (false_alm_cnt->cnt_bw_usc > false_alm_cnt->cnt_bw_lsc + 500)) { + if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) { + primary_cca->intf_type = 1; + primary_cca->pri_cca_flag = 1; + odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT7, 1); /* LSC MF */ + if (primary_cca->dup_rts_flag == 1) + primary_cca->dup_rts_flag = 0; + } else { + primary_cca->intf_type = 2; + if (primary_cca->dup_rts_flag == 0) + primary_cca->dup_rts_flag = 1; + } + + } else { /* interferecne disappear */ + primary_cca->dup_rts_flag = 0; + primary_cca->intf_flag = 0; + primary_cca->intf_type = 0; + } + + + } + primary_cca->monitor_flag = 0; + } + + /* 1 Dynamic Primary CCA Main Function */ + if (primary_cca->monitor_flag == 0) { + if (*(dm->band_width) == CHANNEL_WIDTH_40) { /* if RFBW==40M mode which require to process primary cca */ + /* 2 STA is NOT Connected */ + if (!is_connected) { + PHYDM_DBG(dm, DBG_PRI_CCA, "STA NOT Connected!!!!\n"); + + if (primary_cca->pri_cca_flag == 1) { /* reset primary cca when STA is disconnected */ + primary_cca->pri_cca_flag = 0; + odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 0); + } + if (primary_cca->dup_rts_flag == 1) /* reset Duplicate RTS when STA is disconnected */ + primary_cca->dup_rts_flag = 0; + + if (sec_ch_offset == 1) { /* secondary channel is below the primary channel */ + if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_lsc * 5 > false_alm_cnt->cnt_bw_usc * 9)) { + primary_cca->intf_flag = 1; /* secondary channel interference is detected!!! */ + if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) + primary_cca->intf_type = 1; /* interference is shift */ + else + primary_cca->intf_type = 2; /* interference is in-band */ + } else { + primary_cca->intf_flag = 0; + primary_cca->intf_type = 0; + } + } else if (sec_ch_offset == 2) { /* secondary channel is above the primary channel */ + if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_usc * 5 > false_alm_cnt->cnt_bw_lsc * 9)) { + primary_cca->intf_flag = 1; /* secondary channel interference is detected!!! */ + if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) + primary_cca->intf_type = 1; /* interference is shift */ + else + primary_cca->intf_type = 2; /* interference is in-band */ + } else { + primary_cca->intf_flag = 0; + primary_cca->intf_type = 0; + } + } + PHYDM_DBG(dm, DBG_PRI_CCA, "primary_cca=%d\n", primary_cca->pri_cca_flag); + PHYDM_DBG(dm, DBG_PRI_CCA, "Intf_Type=%d\n", primary_cca->intf_type); + } + /* 2 STA is Connected */ + else { + if (client_40mhz == 0) /* 3 */ { /* client BW = 20MHz */ + if (primary_cca->pri_cca_flag == 0) { + primary_cca->pri_cca_flag = 1; + if (sec_ch_offset == 1) + odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 2); + else if (sec_ch_offset == 2) + odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 1); + } + PHYDM_DBG(dm, DBG_PRI_CCA, "STA Connected 20M!!! primary_cca=%d\n", primary_cca->pri_cca_flag); + } else /* 3 */ { /* client BW = 40MHz */ + if (primary_cca->intf_flag == 1) { /* interference is detected!! */ + if (primary_cca->intf_type == 1) { + if (primary_cca->pri_cca_flag != 1) { + primary_cca->pri_cca_flag = 1; + if (sec_ch_offset == 1) + odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 2); + else if (sec_ch_offset == 2) + odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 1); + } + } else if (primary_cca->intf_type == 2) { + if (primary_cca->dup_rts_flag != 1) + primary_cca->dup_rts_flag = 1; + } + } else { /* if intf_flag==0 */ + if ((cur_tx_ok_cnt + cur_rx_ok_cnt) < 1) { /* idle mode or TP traffic is very low */ + if (sec_ch_offset == 1) { + if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_lsc * 5 > false_alm_cnt->cnt_bw_usc * 9)) { + primary_cca->intf_flag = 1; + if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) + primary_cca->intf_type = 1; /* interference is shift */ + else + primary_cca->intf_type = 2; /* interference is in-band */ + } + } else if (sec_ch_offset == 2) { + if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_usc * 5 > false_alm_cnt->cnt_bw_lsc * 9)) { + primary_cca->intf_flag = 1; + if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) + primary_cca->intf_type = 1; /* interference is shift */ + else + primary_cca->intf_type = 2; /* interference is in-band */ + } + + } + } else { /* TP Traffic is High */ + if (sec_ch_offset == 1) { + if (false_alm_cnt->cnt_bw_lsc > (false_alm_cnt->cnt_bw_usc + 500)) { + if (delay == 0) { /* add delay to avoid interference occurring abruptly, jump one time */ + primary_cca->intf_flag = 1; + if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) + primary_cca->intf_type = 1; /* interference is shift */ + else + primary_cca->intf_type = 2; /* interference is in-band */ + delay = 1; + } else + delay = 0; + } + } else if (sec_ch_offset == 2) { + if (false_alm_cnt->cnt_bw_usc > (false_alm_cnt->cnt_bw_lsc + 500)) { + if (delay == 0) { /* add delay to avoid interference occurring abruptly */ + primary_cca->intf_flag = 1; + if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) + primary_cca->intf_type = 1; /* interference is shift */ + else + primary_cca->intf_type = 2; /* interference is in-band */ + delay = 1; + } else + delay = 0; + } + } + } + } + PHYDM_DBG(dm, DBG_PRI_CCA, "Primary CCA=%d\n", primary_cca->pri_cca_flag); + PHYDM_DBG(dm, DBG_PRI_CCA, "Duplicate RTS=%d\n", primary_cca->dup_rts_flag); + } + + } /* end of connected */ + } + } + /* 1 Dynamic Primary CCA Monitor counter */ + if ((primary_cca->pri_cca_flag == 1) || (primary_cca->dup_rts_flag == 1)) { + if (client_40mhz == 0) { /* client=20M no need to monitor primary cca flag */ + client_40mhz_pre = client_40mhz; + return; + } + counter++; + PHYDM_DBG(dm, DBG_PRI_CCA, "counter=%d\n", counter); + if ((counter == 30) || ((client_40mhz - client_40mhz_pre) == 1)) { /* Every 60 sec to monitor one time */ + primary_cca->monitor_flag = 1; /* monitor flag is triggered!!!!! */ + if (primary_cca->pri_cca_flag == 1) { + primary_cca->pri_cca_flag = 0; + odm_set_bb_reg(dm, 0xc6c, BIT(8) | BIT(7), 0); + } + counter = 0; + } + } + } + + client_40mhz_pre = client_40mhz; +} +#endif + +#if (RTL8192E_SUPPORT == 1) + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void +odm_dynamic_primary_cca_mp_8192e( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + PADAPTER adapter = (PADAPTER)dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct phydm_fa_struct *false_alm_cnt = &(dm->false_alm_cnt); + struct phydm_pricca_struct *primary_cca = &(dm->dm_pri_cca); + u64 OFDM_CCA, OFDM_FA, bw_usc_cnt, bw_lsc_cnt; + u8 sec_ch_offset; + static u8 count_down = PRI_CCA_MONITOR_TIME; + + if (!dm->is_linked) + return; + + if (!(dm->support_ability & ODM_BB_PRIMARY_CCA)) + return; + + OFDM_CCA = false_alm_cnt->cnt_ofdm_cca; + OFDM_FA = false_alm_cnt->cnt_ofdm_fail; + bw_usc_cnt = false_alm_cnt->cnt_bw_usc; + bw_lsc_cnt = false_alm_cnt->cnt_bw_lsc; + PHYDM_DBG(dm, DBG_PRI_CCA, "92E: OFDM CCA=%d\n", OFDM_CCA); + PHYDM_DBG(dm, DBG_PRI_CCA, "92E: OFDM FA=%d\n", OFDM_FA); + PHYDM_DBG(dm, DBG_PRI_CCA, "92E: BW_USC=%d\n", bw_usc_cnt); + PHYDM_DBG(dm, DBG_PRI_CCA, "92E: BW_LSC=%d\n", bw_lsc_cnt); + sec_ch_offset = *(dm->sec_ch_offset); /* NIC: 2: sec is below, 1: sec is above */ + + + if (IsAPModeExist(adapter)) { + phydm_write_dynamic_cca(dm, MF_USC_LSC); + return; + } + + if (*(dm->band_width) != CHANNEL_WIDTH_40) + return; + + PHYDM_DBG(dm, DBG_PRI_CCA, "92E: Cont Down= %d\n", count_down); + PHYDM_DBG(dm, DBG_PRI_CCA, "92E: Primary_CCA_flag=%d\n", primary_cca->pri_cca_flag); + PHYDM_DBG(dm, DBG_PRI_CCA, "92E: Intf_Type=%d\n", primary_cca->intf_type); + PHYDM_DBG(dm, DBG_PRI_CCA, "92E: Intf_flag=%d\n", primary_cca->intf_flag); + PHYDM_DBG(dm, DBG_PRI_CCA, "92E: Duplicate RTS Flag=%d\n", primary_cca->dup_rts_flag); + + if (primary_cca->pri_cca_flag == 0) { + if (sec_ch_offset == SECOND_CH_AT_LSB) { /* Primary channel is above NOTE: duplicate CTS can remove this condition */ + + if ((OFDM_CCA > OFDMCCA_TH) && (bw_lsc_cnt > (bw_usc_cnt + bw_ind_bias)) + && (OFDM_FA > (OFDM_CCA >> 1))) { + primary_cca->intf_type = 1; + primary_cca->intf_flag = 1; + phydm_write_dynamic_cca(dm, MF_USC); + primary_cca->pri_cca_flag = 1; + } else if ((OFDM_CCA > OFDMCCA_TH) && (bw_lsc_cnt > (bw_usc_cnt + bw_ind_bias)) + && (OFDM_FA < (OFDM_CCA >> 1))) { + primary_cca->intf_type = 2; + primary_cca->intf_flag = 1; + phydm_write_dynamic_cca(dm, MF_USC); + primary_cca->pri_cca_flag = 1; + primary_cca->dup_rts_flag = 1; + hal_data->RTSEN = 1; + } else { + primary_cca->intf_type = 0; + primary_cca->intf_flag = 0; + phydm_write_dynamic_cca(dm, MF_USC_LSC); + hal_data->RTSEN = 0; + primary_cca->dup_rts_flag = 0; + } + + } else if (sec_ch_offset == SECOND_CH_AT_USB) { + if ((OFDM_CCA > OFDMCCA_TH) && (bw_usc_cnt > (bw_lsc_cnt + bw_ind_bias)) + && (OFDM_FA > (OFDM_CCA >> 1))) { + primary_cca->intf_type = 1; + primary_cca->intf_flag = 1; + phydm_write_dynamic_cca(dm, MF_LSC); + primary_cca->pri_cca_flag = 1; + } else if ((OFDM_CCA > OFDMCCA_TH) && (bw_usc_cnt > (bw_lsc_cnt + bw_ind_bias)) + && (OFDM_FA < (OFDM_CCA >> 1))) { + primary_cca->intf_type = 2; + primary_cca->intf_flag = 1; + phydm_write_dynamic_cca(dm, MF_LSC); + primary_cca->pri_cca_flag = 1; + primary_cca->dup_rts_flag = 1; + hal_data->RTSEN = 1; + } else { + primary_cca->intf_type = 0; + primary_cca->intf_flag = 0; + phydm_write_dynamic_cca(dm, MF_USC_LSC); + hal_data->RTSEN = 0; + primary_cca->dup_rts_flag = 0; + } + + } + + } else { /* primary_cca->pri_cca_flag==1 */ + + count_down--; + if (count_down == 0) { + count_down = PRI_CCA_MONITOR_TIME; + primary_cca->pri_cca_flag = 0; + phydm_write_dynamic_cca(dm, MF_USC_LSC); /* default */ + hal_data->RTSEN = 0; + primary_cca->dup_rts_flag = 0; + primary_cca->intf_type = 0; + primary_cca->intf_flag = 0; + } + + } +} + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + +void +odm_intf_detection( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *false_alm_cnt = &(dm->false_alm_cnt); + struct phydm_pricca_struct *primary_cca = &(dm->dm_pri_cca); + + if ((false_alm_cnt->cnt_ofdm_cca > OFDMCCA_TH) + && (false_alm_cnt->cnt_bw_lsc > (false_alm_cnt->cnt_bw_usc + bw_ind_bias))) { + primary_cca->intf_flag = 1; + primary_cca->ch_offset = 1; /* 1:LSC, 2:USC */ + if (false_alm_cnt->cnt_ofdm_fail > (false_alm_cnt->cnt_ofdm_cca >> 1)) + primary_cca->intf_type = 1; + else + primary_cca->intf_type = 2; + } else if ((false_alm_cnt->cnt_ofdm_cca > OFDMCCA_TH) + && (false_alm_cnt->cnt_bw_usc > (false_alm_cnt->cnt_bw_lsc + bw_ind_bias))) { + primary_cca->intf_flag = 1; + primary_cca->ch_offset = 2; /* 1:LSC, 2:USC */ + if (false_alm_cnt->cnt_ofdm_fail > (false_alm_cnt->cnt_ofdm_cca >> 1)) + primary_cca->intf_type = 1; + else + primary_cca->intf_type = 2; + } else { + primary_cca->intf_flag = 0; + primary_cca->intf_type = 0; + primary_cca->ch_offset = 0; + } + +} + +void +odm_dynamic_primary_cca_ap_8192e( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *primary_cca = &(dm->dm_pri_cca); + u8 i; + static u32 count_down = PRI_CCA_MONITOR_TIME; + u8 STA_BW = false, STA_BW_pre = false, STA_BW_TMP = false; + boolean is_connected = false; + u8 sec_ch_offset; + u8 cur_mf_state; + struct cmn_sta_info *entry; + + if (!dm->is_linked) + return; + + if (!(dm->support_ability & ODM_BB_PRIMARY_CCA)) + return; + + sec_ch_offset = *(dm->sec_ch_offset); /* AP: 1: sec is below, 2: sec is above */ + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + entry = dm->phydm_sta_info[i]; + if (is_sta_active(entry)) { + STA_BW_TMP = entry->bw_mode; + if (STA_BW_TMP > STA_BW) + STA_BW = STA_BW_TMP; + is_connected = true; + } + } + + if (*(dm->band_width) == CHANNEL_WIDTH_40) { + + if (primary_cca->pri_cca_flag == 0) { + if (is_connected) { + if (STA_BW == CHANNEL_WIDTH_20) { /* 2 STA BW=20M */ + primary_cca->pri_cca_flag = 1; + if (sec_ch_offset == 1) { + cur_mf_state = MF_USC; + phydm_write_dynamic_cca(dm, cur_mf_state); + } else if (sec_ch_offset == 2) { + cur_mf_state = MF_USC; + phydm_write_dynamic_cca(dm, cur_mf_state); + } + } else { /* 2 STA BW=40M */ + if (primary_cca->intf_flag == 0) + odm_intf_detection(dm); + else { /* intf_flag = 1 */ + if (primary_cca->intf_type == 1) { + if (primary_cca->ch_offset == 1) { + cur_mf_state = MF_USC; + if (sec_ch_offset == 1) /* AP, 1: primary is above 2: primary is below */ + phydm_write_dynamic_cca(dm, cur_mf_state); + } else if (primary_cca->ch_offset == 2) { + cur_mf_state = MF_LSC; + if (sec_ch_offset == 2) + phydm_write_dynamic_cca(dm, cur_mf_state); + } + } else if (primary_cca->intf_type == 2) + PHYDM_DBG(dm, DBG_PRI_CCA, "92E: primary_cca->intf_type = 2\n"); + } + } + + } else /* disconnected interference detection */ + odm_intf_detection(dm); /* end of disconnected */ + + + } else { /* primary_cca->pri_cca_flag == 1 */ + + if (STA_BW == 0) { + STA_BW_pre = STA_BW; + return; + } + + count_down--; + if ((count_down == 0) || ((STA_BW & STA_BW_pre) != 1)) { + count_down = PRI_CCA_MONITOR_TIME; + primary_cca->pri_cca_flag = 0; + primary_cca->intf_type = 0; + primary_cca->intf_flag = 0; + cur_mf_state = MF_USC_LSC; + phydm_write_dynamic_cca(dm, cur_mf_state); /* default */ + } + } + STA_BW_pre = STA_BW; + + } else { + /* 2 Reset */ + phydm_primary_cca_init(dm); + cur_mf_state = MF_USC_LSC; + phydm_write_dynamic_cca(dm, cur_mf_state); + count_down = PRI_CCA_MONITOR_TIME; + } + +} +#endif + + +#endif /* RTL8192E_SUPPORT == 1 */ +#endif + + +#endif + +boolean +odm_dynamic_primary_cca_dup_rts( + void *dm_void +) +{ +#ifdef PHYDM_PRIMARY_CCA + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *primary_cca = &dm->dm_pri_cca; + + return primary_cca->dup_rts_flag; +#else + return 0; +#endif +} + +void +phydm_primary_cca_init( + void *dm_void +) +{ +#ifdef PHYDM_PRIMARY_CCA + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *primary_cca = &dm->dm_pri_cca; + + if (!(dm->support_ability & ODM_BB_PRIMARY_CCA)) + return; + + PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Init ==>\n"); + #if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) + primary_cca->dup_rts_flag = 0; + primary_cca->intf_flag = 0; + primary_cca->intf_type = 0; + primary_cca->monitor_flag = 0; + primary_cca->pri_cca_flag = 0; + primary_cca->ch_offset = 0; + #endif + primary_cca->mf_state = 0xff; + primary_cca->pre_bw = (enum channel_width)0xff; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) + primary_cca->cca_th_40m_bkp = (u8)odm_get_bb_reg(dm, 0xc84, 0xf0000000); +#endif +} + +void +phydm_primary_cca( + void *dm_void +) +{ +#ifdef PHYDM_PRIMARY_CCA + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ic_type & ODM_IC_11N_SERIES)) + return; + + if (!(dm->support_ability & ODM_BB_PRIMARY_CCA)) + return; + + phydm_primary_cca_11n(dm); + +#endif +} + + diff --git a/hal/phydm/phydm_primary_cca.h b/hal/phydm/phydm_primary_cca.h new file mode 100644 index 0000000..c619de5 --- /dev/null +++ b/hal/phydm/phydm_primary_cca.h @@ -0,0 +1,126 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_PRIMARYCCA_H__ +#define __PHYDM_PRIMARYCCA_H__ + +#define PRIMARYCCA_VERSION "1.0" /*2017.03.23, Dino*/ + +/*============================================================*/ +/*Definition */ +/*============================================================*/ + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define SECOND_CH_AT_LSB 2 /*primary CH @ MSB, SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/ +#define SECOND_CH_AT_USB 1 /*primary CH @ LSB, SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/ +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define SECOND_CH_AT_LSB 2 /*primary CH @ MSB, SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/ +#define SECOND_CH_AT_USB 1 /*primary CH @ LSB, SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/ +#else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/ +#define SECOND_CH_AT_LSB 1 /*primary CH @ MSB, SD8: HT_2NDCH_OFFSET_BELOW*/ +#define SECOND_CH_AT_USB 2 /*primary CH @ LSB, SD8: HT_2NDCH_OFFSET_ABOVE*/ +#endif + +#define OFDMCCA_TH 500 +#define bw_ind_bias 500 +#define PRI_CCA_MONITOR_TIME 30 + +#ifdef PHYDM_PRIMARY_CCA + +/*============================================================*/ +/*structure and define*/ +/*============================================================*/ +enum primary_cca_ch_position { /*N-series REG0xc6c[8:7]*/ + MF_USC_LSC = 0, + MF_LSC = 1, + MF_USC = 2 +}; + +struct phydm_pricca_struct { + #if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) + u8 pri_cca_flag; + u8 intf_flag; + u8 intf_type; + u8 monitor_flag; + u8 ch_offset; + #endif + u8 dup_rts_flag; + u8 cca_th_40m_bkp; /*c84[31:28]*/ + enum channel_width pre_bw; + u8 pri_cca_is_become_linked; + u8 mf_state; +}; + +/*============================================================*/ +/*function prototype*/ +/*============================================================*/ + +#if 0 +#if (RTL8192E_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void +odm_dynamic_primary_cca_mp_8192e( + void *dm_void +); + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + +void +odm_dynamic_primary_cca_ap_8192e( + void *dm_void +); +#endif +#endif + +#if (RTL8188E_SUPPORT == 1) + +void +odm_dynamic_primary_cca_8188e( + void *dm_void +); +#endif +#endif + +#endif /*#ifdef PHYDM_PRIMARY_CCA*/ + + +boolean +odm_dynamic_primary_cca_dup_rts( + void *dm_void +); + +void +phydm_primary_cca_init( + void *dm_void +); + +void +phydm_primary_cca( + void *dm_void +); + + +#endif /*#ifndef __PHYDM_PRIMARYCCA_H__*/ diff --git a/hal/phydm/phydm_regtable.h b/hal/phydm/phydm_regtable.h new file mode 100644 index 0000000..70be071 --- /dev/null +++ b/hal/phydm/phydm_regtable.h @@ -0,0 +1,563 @@ +#define R_0x0 0x0 +#define R_0x00 0x00 +#define R_0x0140 0x0140 +#define R_0x040 0x040 +#define R_0x10 0x10 +#define R_0x1080 0x1080 +#define R_0x14c0 0x14c0 +#define R_0x14c4 0x14c4 +#define R_0x14c8 0x14c8 +#define R_0x14cc 0x14cc +#define R_0x1518 0x1518 +#define R_0x1684 0x1684 +#define R_0x1688 0x1688 +#define R_0x168c 0x168c +#define R_0x1700 0x1700 +#define R_0x1704 0x1704 +#define R_0x1800 0x1800 +#define R_0x183c 0x183c +#define R_0x1840 0x1840 +#define R_0x1844 0x1844 +#define R_0x1848 0x1848 +#define R_0x188c 0x188c +#define R_0x1894 0x1894 +#define R_0x18ac 0x18ac +#define R_0x1900 0x1900 +#define R_0x1904 0x1904 +#define R_0x1908 0x1908 +#define R_0x1918 0x1918 +#define R_0x191c 0x191c +#define R_0x1928 0x1928 +#define R_0x1950 0x1950 +#define R_0x1954 0x1954 +#define R_0x195c 0x195c +#define R_0x1984 0x1984 +#define R_0x1988 0x1988 +#define R_0x198c 0x198c +#define R_0x1990 0x1990 +#define R_0x1991 0x1991 +#define R_0x1998 0x1998 +#define R_0x19a8 0x19a8 +#define R_0x19d4 0x19d4 +#define R_0x19d8 0x19d8 +#define R_0x19e0 0x19e0 +#define R_0x19f0 0x19f0 +#define R_0x19f8 0x19f8 +#define R_0x1a00 0x1a00 +#define R_0x1a04 0x1a04 +#define R_0x1a24 0x1a24 +#define R_0x1a28 0x1a28 +#define R_0x1a2c 0x1a2c +#define R_0x1a5c 0x1a5c +#define R_0x1a84 0x1a84 +#define R_0x1a8c 0x1a8c +#define R_0x1a94 0x1a94 +#define R_0x1aac 0x1aac +#define R_0x1abc 0x1abc +#define R_0x1ac0 0x1ac0 +#define R_0x1b00 0x1b00 +#define R_0x1b08 0x1b08 +#define R_0x1b0c 0x1b0c +#define R_0x1b2c 0x1b2c +#define R_0x1b38 0x1b38 +#define R_0x1b3c 0x1b3c +#define R_0x1b8c 0x1b8c +#define R_0x1b98 0x1b98 +#define R_0x1bc8 0x1bc8 +#define R_0x1bcc 0x1bcc +#define R_0x1bd0 0x1bd0 +#define R_0x1bd4 0x1bd4 +#define R_0x1bd8 0x1bd8 +#define R_0x1bf0 0x1bf0 +#define R_0x1bfc 0x1bfc +#define R_0x1c28 0x1c28 +#define R_0x1c38 0x1c38 +#define R_0x1c3c 0x1c3c +#define R_0x1c68 0x1c68 +#define R_0x1c74 0x1c74 +#define R_0x1c78 0x1c78 +#define R_0x1c7c 0x1c7c +#define R_0x1c90 0x1c90 +#define R_0x1c94 0x1c94 +#define R_0x1c98 0x1c98 +#define R_0x1c9c 0x1c9c +#define R_0x1ca0 0x1ca0 +#define R_0x1cb8 0x1cb8 +#define R_0x1cf8 0x1cf8 +#define R_0x1d70 0x1d70 +#define R_0x1e2c 0x1e2c +#define R_0x1e5c 0x1e5c +#define R_0x1eb4 0x1eb4 +#define R_0x2c04 0x2c04 +#define R_0x2c08 0x2c08 +#define R_0x2c10 0x2c10 +#define R_0x2c14 0x2c14 +#define R_0x2d00 0x2d00 +#define R_0x2d04 0x2d04 +#define R_0x2d08 0x2d08 +#define R_0x2d10 0x2d10 +#define R_0x2d20 0x2d20 +#define R_0x2de8 0x2de8 +#define R_0x300 0x300 +#define R_0x38 0x38 +#define R_0x40 0x40 +#define R_0x4000 0x4000 +#define R_0x4008 0x4008 +#define R_0x4018 0x4018 +#define R_0x401c 0x401c +#define R_0x4028 0x4028 +#define R_0x4100 0x4100 +#define R_0x413c 0x413c +#define R_0x4140 0x4140 +#define R_0x4144 0x4144 +#define R_0x4148 0x4148 +#define R_0x430 0x430 +#define R_0x434 0x434 +#define R_0x44 0x44 +#define R_0x444 0x444 +#define R_0x448 0x448 +#define R_0x450 0x450 +#define R_0x454 0x454 +#define R_0x49c 0x49c +#define R_0x4a0 0x4a0 +#define R_0x4a4 0x4a4 +#define R_0x4a8 0x4a8 +#define R_0x4c 0x4c +#define R_0x4c8 0x4c8 +#define R_0x4cc 0x4cc +#define R_0x5000 0x5000 +#define R_0x5008 0x5008 +#define R_0x5018 0x5018 +#define R_0x501c 0x501c +#define R_0x5028 0x5028 +#define R_0x5100 0x5100 +#define R_0x5108 0x5108 +#define R_0x5118 0x5118 +#define R_0x511c 0x511c +#define R_0x5128 0x5128 +#define R_0x520 0x520 +#define R_0x5200 0x5200 +#define R_0x522 0x522 +#define R_0x523c 0x523c +#define R_0x5240 0x5240 +#define R_0x5244 0x5244 +#define R_0x5248 0x5248 +#define R_0x5300 0x5300 +#define R_0x533c 0x533c +#define R_0x5340 0x5340 +#define R_0x5344 0x5344 +#define R_0x5348 0x5348 +#define R_0x550 0x550 +#define R_0x551 0x551 +#define R_0x568 0x568 +#define R_0x588 0x588 +#define R_0x604 0x604 +#define R_0x608 0x608 +#define R_0x60f 0x60f +#define R_0x64 0x64 +#define R_0x66 0x66 +#define R_0x660 0x660 +#define R_0x668 0x668 +#define R_0x688 0x688 +#define R_0x6a0 0x6a0 +#define R_0x6d8 0x6d8 +#define R_0x6dc 0x6dc +#define R_0x70 0x70 +#define R_0x74 0x74 +#define R_0x764 0x764 +#define R_0x7b0 0x7b0 +#define R_0x7b4 0x7b4 +#define R_0x7c0 0x7c0 +#define R_0x7c4 0x7c4 +#define R_0x7c8 0x7c8 +#define R_0x7cc 0x7cc +#define R_0x7f0 0x7f0 +#define R_0x7f4 0x7f4 +#define R_0x7f8 0x7f8 +#define R_0x7fc 0x7fc +#define R_0x800 0x800 +#define R_0x804 0x804 +#define R_0x808 0x808 +#define R_0x80c 0x80c +#define R_0x810 0x810 +#define R_0x814 0x814 +#define R_0x818 0x818 +#define R_0x820 0x820 +#define R_0x824 0x824 +#define R_0x828 0x828 +#define R_0x82c 0x82c +#define R_0x830 0x830 +#define R_0x834 0x834 +#define R_0x838 0x838 +#define R_0x83c 0x83c +#define R_0x840 0x840 +#define R_0x848 0x848 +#define R_0x850 0x850 +#define R_0x854 0x854 +#define R_0x858 0x858 +#define R_0x860 0x860 +#define R_0x864 0x864 +#define R_0x86c 0x86c +#define R_0x870 0x870 +#define R_0x874 0x874 +#define R_0x878 0x878 +#define R_0x87c 0x87c +#define R_0x880 0x880 +#define R_0x884 0x884 +#define R_0x888 0x888 +#define R_0x88c 0x88c +#define R_0x890 0x890 +#define R_0x894 0x894 +#define R_0x898 0x898 +#define R_0x89c 0x89c +#define R_0x8a0 0x8a0 +#define R_0x8a4 0x8a4 +#define R_0x8ac 0x8ac +#define R_0x8b4 0x8b4 +#define R_0x8c4 0x8c4 +#define R_0x8c8 0x8c8 +#define R_0x8cc 0x8cc +#define R_0x8d0 0x8d0 +#define R_0x8d4 0x8d4 +#define R_0x8d8 0x8d8 +#define R_0x8dc 0x8dc +#define R_0x8f0 0x8f0 +#define R_0x8f8 0x8f8 +#define R_0x8fc 0x8fc +#define R_0x900 0x900 +#define R_0x908 0x908 +#define R_0x90c 0x90c +#define R_0x910 0x910 +#define R_0x914 0x914 +#define R_0x918 0x918 +#define R_0x91c 0x91c +#define R_0x920 0x920 +#define R_0x924 0x924 +#define R_0x92c 0x92c +#define R_0x930 0x930 +#define R_0x934 0x934 +#define R_0x938 0x938 +#define R_0x93c 0x93c +#define R_0x940 0x940 +#define R_0x944 0x944 +#define R_0x948 0x948 +#define R_0x94c 0x94c +#define R_0x950 0x950 +#define R_0x958 0x958 +#define R_0x95c 0x95c +#define R_0x970 0x970 +#define R_0x974 0x974 +#define R_0x978 0x978 +#define R_0x97c 0x97c +#define R_0x98c 0x98c +#define R_0x990 0x990 +#define R_0x994 0x994 +#define R_0x998 0x998 +#define R_0x9a0 0x9a0 +#define R_0x9a4 0x9a4 +#define R_0x9ac 0x9ac +#define R_0x9b0 0x9b0 +#define R_0x9b4 0x9b4 +#define R_0x9cc 0x9cc +#define R_0x9d0 0x9d0 +#define R_0x9e4 0x9e4 +#define R_0xa0 0xa0 +#define R_0xa00 0xa00 +#define R_0xa04 0xa04 +#define R_0xa08 0xa08 +#define R_0xa0c 0xa0c +#define R_0xa10 0xa10 +#define R_0xa14 0xa14 +#define R_0xa20 0xa20 +#define R_0xa24 0xa24 +#define R_0xa28 0xa28 +#define R_0xa2c 0xa2c +#define R_0xa70 0xa70 +#define R_0xa74 0xa74 +#define R_0xa78 0xa78 +#define R_0xa8 0xa8 +#define R_0xa80 0xa80 +#define R_0xa84 0xa84 +#define R_0xa9c 0xa9c +#define R_0xaa8 0xaa8 +#define R_0xaac 0xaac +#define R_0xab4 0xab4 +#define R_0xabc 0xabc +#define R_0xac8 0xac8 +#define R_0xacc 0xacc +#define R_0xad0 0xad0 +#define R_0xb0 0xb0 +#define R_0xb00 0xb00 +#define R_0xb04 0xb04 +#define R_0xb07 0xb07 +#define R_0xb08 0xb08 +#define R_0xb0c 0xb0c +#define R_0xb10 0xb10 +#define R_0xb14 0xb14 +#define R_0xb18 0xb18 +#define R_0xb1c 0xb1c +#define R_0xb20 0xb20 +#define R_0xb24 0xb24 +#define R_0xb28 0xb28 +#define R_0xb2b 0xb2b +#define R_0xb2c 0xb2c +#define R_0xb30 0xb30 +#define R_0xb34 0xb34 +#define R_0xb38 0xb38 +#define R_0xb3c 0xb3c +#define R_0xb40 0xb40 +#define R_0xb44 0xb44 +#define R_0xb48 0xb48 +#define R_0xb54 0xb54 +#define R_0xb58 0xb58 +#define R_0xb60 0xb60 +#define R_0xb64 0xb64 +#define R_0xb68 0xb68 +#define R_0xb6a 0xb6a +#define R_0xb6c 0xb6c +#define R_0xb6e 0xb6e +#define R_0xb70 0xb70 +#define R_0xb74 0xb74 +#define R_0xb77 0xb77 +#define R_0xb78 0xb78 +#define R_0xb7c 0xb7c +#define R_0xb80 0xb80 +#define R_0xb84 0xb84 +#define R_0xb88 0xb88 +#define R_0xb8c 0xb8c +#define R_0xb90 0xb90 +#define R_0xb94 0xb94 +#define R_0xb98 0xb98 +#define R_0xb9b 0xb9b +#define R_0xb9c 0xb9c +#define R_0xba0 0xba0 +#define R_0xba4 0xba4 +#define R_0xba8 0xba8 +#define R_0xbac 0xbac +#define R_0xbad 0xbad +#define R_0xbc0 0xbc0 +#define R_0xbc4 0xbc4 +#define R_0xbc8 0xbc8 +#define R_0xbcc 0xbcc +#define R_0xbd8 0xbd8 +#define R_0xbdc 0xbdc +#define R_0xbe0 0xbe0 +#define R_0xbe4 0xbe4 +#define R_0xbe8 0xbe8 +#define R_0xbec 0xbec +#define R_0xbf0 0xbf0 +#define R_0xbf4 0xbf4 +#define R_0xbf8 0xbf8 +#define R_0xc00 0xc00 +#define R_0xc04 0xc04 +#define R_0xc08 0xc08 +#define R_0xc0c 0xc0c +#define R_0xc10 0xc10 +#define R_0xc14 0xc14 +#define R_0xc1c 0xc1c +#define R_0xc20 0xc20 +#define R_0xc24 0xc24 +#define R_0xc30 0xc30 +#define R_0xc38 0xc38 +#define R_0xc3c 0xc3c +#define R_0xc40 0xc40 +#define R_0xc44 0xc44 +#define R_0xc4c 0xc4c +#define R_0xc50 0xc50 +#define R_0xc54 0xc54 +#define R_0xc58 0xc58 +#define R_0xc5c 0xc5c +#define R_0xc6c 0xc6c +#define R_0xc70 0xc70 +#define R_0xc74 0xc74 +#define R_0xc78 0xc78 +#define R_0xc7c 0xc7c +#define R_0xc80 0xc80 +#define R_0xc84 0xc84 +#define R_0xc88 0xc88 +#define R_0xc8c 0xc8c +#define R_0xc90 0xc90 +#define R_0xc94 0xc94 +#define R_0xc9c 0xc9c +#define R_0xca0 0xca0 +#define R_0xca4 0xca4 +#define R_0xca8 0xca8 +#define R_0xcac 0xcac +#define R_0xcb0 0xcb0 +#define R_0xcb4 0xcb4 +#define R_0xcb8 0xcb8 +#define R_0xcbc 0xcbc +#define R_0xcbd 0xcbd +#define R_0xcbe 0xcbe +#define R_0xcc4 0xcc4 +#define R_0xcc8 0xcc8 +#define R_0xccc 0xccc +#define R_0xcd0 0xcd0 +#define R_0xcd4 0xcd4 +#define R_0xcd8 0xcd8 +#define R_0xce0 0xce0 +#define R_0xce4 0xce4 +#define R_0xce8 0xce8 +#define R_0xd00 0xd00 +#define R_0xd04 0xd04 +#define R_0xd0c 0xd0c +#define R_0xd10 0xd10 +#define R_0xd14 0xd14 +#define R_0xd2c 0xd2c +#define R_0xd30 0xd30 +#define R_0xd40 0xd40 +#define R_0xd44 0xd44 +#define R_0xd48 0xd48 +#define R_0xd4c 0xd4c +#define R_0xd50 0xd50 +#define R_0xd54 0xd54 +#define R_0xd5c 0xd5c +#define R_0xd6c 0xd6c +#define R_0xd7c 0xd7c +#define R_0xd80 0xd80 +#define R_0xd84 0xd84 +#define R_0xd8c 0xd8c +#define R_0xd90 0xd90 +#define R_0xd94 0xd94 +#define R_0xdac 0xdac +#define R_0xdb0 0xdb0 +#define R_0xdb4 0xdb4 +#define R_0xdb8 0xdb8 +#define R_0xdbc 0xdbc +#define R_0xdcc 0xdcc +#define R_0xdd0 0xdd0 +#define R_0xdd4 0xdd4 +#define R_0xdd8 0xdd8 +#define R_0xde0 0xde0 +#define R_0xdec 0xdec +#define R_0xdf4 0xdf4 +#define R_0xe00 0xe00 +#define R_0xe04 0xe04 +#define R_0xe08 0xe08 +#define R_0xe10 0xe10 +#define R_0xe14 0xe14 +#define R_0xe1c 0xe1c +#define R_0xe20 0xe20 +#define R_0xe24 0xe24 +#define R_0xe28 0xe28 +#define R_0xe30 0xe30 +#define R_0xe34 0xe34 +#define R_0xe38 0xe38 +#define R_0xe3c 0xe3c +#define R_0xe40 0xe40 +#define R_0xe44 0xe44 +#define R_0xe48 0xe48 +#define R_0xe4c 0xe4c +#define R_0xe50 0xe50 +#define R_0xe54 0xe54 +#define R_0xe5c 0xe5c +#define R_0xe64 0xe64 +#define R_0xe70 0xe70 +#define R_0xe80 0xe80 +#define R_0xe84 0xe84 +#define R_0xe8c 0xe8c +#define R_0xe90 0xe90 +#define R_0xe94 0xe94 +#define R_0xe98 0xe98 +#define R_0xe9c 0xe9c +#define R_0xea0 0xea0 +#define R_0xea4 0xea4 +#define R_0xea8 0xea8 +#define R_0xeac 0xeac +#define R_0xeb0 0xeb0 +#define R_0xeb4 0xeb4 +#define R_0xeb8 0xeb8 +#define R_0xebc 0xebc +#define R_0xec0 0xec0 +#define R_0xec4 0xec4 +#define R_0xec8 0xec8 +#define R_0xecc 0xecc +#define R_0xed4 0xed4 +#define R_0xee8 0xee8 +#define R_0xf0 0xf0 +#define R_0xf08 0xf08 +#define R_0xf0c 0xf0c +#define R_0xf10 0xf10 +#define R_0xf14 0xf14 +#define R_0xf20 0xf20 +#define R_0xf2c 0xf2c +#define R_0xf30 0xf30 +#define R_0xf34 0xf34 +#define R_0xf4 0xf4 +#define R_0xf44 0xf44 +#define R_0xf48 0xf48 +#define R_0xf4c 0xf4c +#define R_0xf80 0xf80 +#define R_0xf84 0xf84 +#define R_0xf88 0xf88 +#define R_0xf8c 0xf8c +#define R_0xf90 0xf90 +#define R_0xf94 0xf94 +#define R_0xf98 0xf98 +#define R_0xfa0 0xfa0 +#define R_0xfa4 0xfa4 +#define R_0xfbc 0xfbc +#define R_0xfc0 0xfc0 +#define R_0xfc4 0xfc4 +#define R_0xfc8 0xfc8 +#define R_0xfcc 0xfcc +#define R_0xfd0 0xfd0 +#define R_0xff0 0xff0 +#define RF_0x0 0x0 +#define RF_0x00 0x00 +#define RF_0x08 0x08 +#define RF_0x0c 0x0c +#define RF_0x0d 0x0d +#define RF_0x1 0x1 +#define RF_0x18 0x18 +#define RF_0x1bf0 0x1bf0 +#define RF_0x2 0x2 +#define RF_0x3 0x3 +#define RF_0x30 0x30 +#define RF_0x31 0x31 +#define RF_0x32 0x32 +#define RF_0x33 0x33 +#define RF_0x35 0x35 +#define RF_0x3e 0x3e +#define RF_0x3f 0x3f +#define RF_0x4 0x4 +#define RF_0x42 0x42 +#define RF_0x43 0x43 +#define RF_0x51 0x51 +#define RF_0x52 0x52 +#define RF_0x54 0x54 +#define RF_0x55 0x55 +#define RF_0x56 0x56 +#define RF_0x58 0x58 +#define RF_0x5c 0x5c +#define RF_0x61 0x61 +#define RF_0x64 0x64 +#define RF_0x65 0x65 +#define RF_0x66 0x66 +#define RF_0x75 0x75 +#define RF_0x76 0x76 +#define RF_0x78 0x78 +#define RF_0x7f 0x7f +#define RF_0x8 0x8 +#define RF_0x80 0x80 +#define RF_0x81 0x81 +#define RF_0x86 0x86 +#define RF_0x8d 0x8d +#define RF_0x8f 0x8f +#define RF_0xae 0xae +#define RF_0xb0 0xb0 +#define RF_0xb8 0xb8 +#define RF_0xbc 0xbc +#define RF_0xbe 0xbe +#define RF_0xc4 0xc4 +#define RF_0xc9 0xc9 +#define RF_0xca 0xca +#define RF_0xcc 0xcc +#define RF_0xd 0xd +#define RF_0xdd 0xdd +#define RF_0xde 0xde +#define RF_0xdf 0xdf +#define RF_0xed 0xed +#define RF_0xee 0xee +#define RF_0xef 0xef +#define RF_0xf5 0xf5 diff --git a/hal/phydm/phydm_rssi_monitor.c b/hal/phydm/phydm_rssi_monitor.c new file mode 100644 index 0000000..d6bcb02 --- /dev/null +++ b/hal/phydm/phydm_rssi_monitor.c @@ -0,0 +1,450 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_SUPPORT_RSSI_MONITOR + +#ifdef PHYDM_3RD_REFORM_RSSI_MONOTOR +void +phydm_rssi_monitor_h2c( + void *dm_void, + u8 macid +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct ra_sta_info *ra = NULL; + u8 h2c_val[H2C_MAX_LENGTH] = {0}; + u8 stbc_en, ldpc_en; + u8 bf_en = 0; + u8 is_rx, is_tx; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RSSI_MNTR, "[Warning] %s invalid sta_info\n", __func__); + return; + } + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RSSI_MNTR, "MACID=%d\n", sta->mac_id); + + is_rx = (ra->txrx_state == RX_STATE) ? 1 : 0; + is_tx = (ra->txrx_state == TX_STATE) ? 1 : 0; + stbc_en = (sta->stbc_en) ? 1 : 0; + ldpc_en = (sta->ldpc_en) ? 1 : 0; + + #ifdef CONFIG_BEAMFORMING + if ((sta->bf_info.ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE) || + (sta->bf_info.vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) { + bf_en = 1; + } + #endif + + if (ra_t->RA_threshold_offset != 0) { + PHYDM_DBG(dm, DBG_RSSI_MNTR, "RA_th_ofst = (( %s%d ))\n", + ((ra_t->RA_offset_direction) ? "+" : "-"), ra_t->RA_threshold_offset); + } + + h2c_val[0] = sta->mac_id; + h2c_val[1] = 0; + h2c_val[2] = sta->rssi_stat.rssi; + h2c_val[3] = is_rx | (stbc_en << 1) | ((dm->noisy_decision & 0x1) << 2) | (bf_en << 6); + h2c_val[4] = (ra_t->RA_threshold_offset & 0x7f) | ((ra_t->RA_offset_direction & 0x1) << 7); + h2c_val[5] = 0; + h2c_val[6] = 0; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "PHYDM h2c[0x42]=0x%x %x %x %x %x %x %x\n", + h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2], h2c_val[1], h2c_val[0]); + + #if (RTL8188E_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) + odm_ra_set_rssi_8188e(dm, (u8)(sta->mac_id & 0xFF), sta->rssi_stat.rssi & 0x7F); + else + #endif + { + odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, H2C_MAX_LENGTH, h2c_val); + } +} + +void +phydm_calculate_rssi_min_max( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta; + s8 rssi_max_tmp = 0, rssi_min_tmp = 100; + u8 i; + u8 sta_cnt = 0; + + if (!dm->is_linked) + return; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__); + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + sta = dm->phydm_sta_info[i]; + if (is_sta_active(sta)) { + sta_cnt++; + + if (sta->rssi_stat.rssi < rssi_min_tmp) + rssi_min_tmp = sta->rssi_stat.rssi; + + if (sta->rssi_stat.rssi > rssi_max_tmp) + rssi_max_tmp = sta->rssi_stat.rssi; + + /*[Send RSSI to FW]*/ + if (sta->ra_info.disable_ra == false) + phydm_rssi_monitor_h2c(dm, i); + + if (sta_cnt == dm->number_linked_client) + break; + } + } + + dm->rssi_max = (u8)rssi_max_tmp; + dm->rssi_min = (u8)rssi_min_tmp; + +} +#endif + + +#if 0/*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + +s32 +phydm_find_minimum_rssi( + struct dm_struct *dm, + void *adapter, + boolean *is_link_temp + +) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + PMGNT_INFO mgnt_info = &adapter->MgntInfo; + boolean act_as_ap = ACTING_AS_AP(adapter); + + /* 1.Determine the minimum RSSI */ + if ((!mgnt_info->bMediaConnect) || + (act_as_ap && (hal_data->EntryMinUndecoratedSmoothedPWDB == 0))) {/* We should check AP mode and Entry info.into consideration, revised by Roger, 2013.10.18*/ + + hal_data->MinUndecoratedPWDBForDM = 0; + *is_link_temp = false; + + } else + *is_link_temp = true; + + + if (mgnt_info->bMediaConnect) { /* Default port*/ + + if (act_as_ap || mgnt_info->mIbss) { + hal_data->MinUndecoratedPWDBForDM = hal_data->EntryMinUndecoratedSmoothedPWDB; + /**/ + } else { + hal_data->MinUndecoratedPWDBForDM = GET_DEFAULT_RSSI(mgnt_info); + /**/ + } + } else { /* associated entry pwdb*/ + hal_data->MinUndecoratedPWDBForDM = hal_data->EntryMinUndecoratedSmoothedPWDB; + /**/ + } + + return hal_data->MinUndecoratedPWDBForDM; +} + +void +odm_rssi_monitor_check_mp( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; + u32 i; + boolean is_ext_ra_info = true; + u8 cmdlen = H2C_0X42_LENGTH; + u8 tx_bf_en = 0, stbc_en = 0; + + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct sta_info *entry = NULL; + s32 tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff; + PMGNT_INFO mgnt_info = &adapter->MgntInfo; + PMGNT_INFO p_default_mgnt_info = &adapter->MgntInfo; + u64 cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0; +#if (BEAMFORMING_SUPPORT == 1) +#ifndef BEAMFORMING_VERSION_1 + enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; +#endif +#endif + void *loop_adapter = GetDefaultAdapter(adapter); + + if (dm->support_ic_type == ODM_RTL8188E) { + is_ext_ra_info = false; + cmdlen = 3; + } + + while (loop_adapter) { + if (loop_adapter != NULL) { + mgnt_info = &loop_adapter->MgntInfo; + cur_tx_ok_cnt = loop_adapter->TxStats.NumTxBytesUnicast - mgnt_info->lastTxOkCnt; + cur_rx_ok_cnt = loop_adapter->RxStats.NumRxBytesUnicast - mgnt_info->lastRxOkCnt; + mgnt_info->lastTxOkCnt = cur_tx_ok_cnt; + mgnt_info->lastRxOkCnt = cur_rx_ok_cnt; + } + + for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) { + if (IsAPModeExist(loop_adapter)) { + if (GetFirstExtAdapter(loop_adapter) != NULL && + GetFirstExtAdapter(loop_adapter) == loop_adapter) + entry = AsocEntry_EnumStation(loop_adapter, i); + else if (GetFirstGOPort(loop_adapter) != NULL && + IsFirstGoAdapter(loop_adapter)) + entry = AsocEntry_EnumStation(loop_adapter, i); + } else { + if (GetDefaultAdapter(loop_adapter) == loop_adapter) + entry = AsocEntry_EnumStation(loop_adapter, i); + } + + if (entry != NULL) { + if (entry->bAssociated) { + RT_DISP_ADDR(FDM, DM_PWDB, ("entry->mac_addr ="), GET_STA_INFO(entry).mac_addr); + RT_DISP(FDM, DM_PWDB, ("entry->rssi = 0x%x(%d)\n", + GET_STA_INFO(entry).rssi_stat.rssi, GET_STA_INFO(entry).rssi_stat.rssi)); + + /* 2 BF_en */ +#if (BEAMFORMING_SUPPORT == 1) +#ifndef BEAMFORMING_VERSION_1 + beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(dm, GET_STA_INFO(entry).mac_id); + if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + tx_bf_en = 1; +#else + if (Beamform_GetSupportBeamformerCap(GetDefaultAdapter(adapter), entry)) + tx_bf_en = 1; +#endif +#endif + /* 2 STBC_en */ + if ((IS_WIRELESS_MODE_AC(adapter) && TEST_FLAG(entry->VHTInfo.STBC, STBC_VHT_ENABLE_TX)) || + TEST_FLAG(entry->HTInfo.STBC, STBC_HT_ENABLE_TX)) + stbc_en = 1; + + if (GET_STA_INFO(entry).rssi_stat.rssi < tmp_entry_min_pwdb) + tmp_entry_min_pwdb = GET_STA_INFO(entry).rssi_stat.rssi; + if (GET_STA_INFO(entry).rssi_stat.rssi > tmp_entry_max_pwdb) + tmp_entry_max_pwdb = GET_STA_INFO(entry).rssi_stat.rssi; + + h2c_parameter[4] = (ra_tab->RA_threshold_offset & 0x7f) | (ra_tab->RA_offset_direction << 7); + PHYDM_DBG(dm, DBG_RSSI_MNTR, "RA_threshold_offset = (( %s%d ))\n", ((ra_tab->RA_threshold_offset == 0) ? " " : ((ra_tab->RA_offset_direction) ? "+" : "-")), ra_tab->RA_threshold_offset); + + if (is_ext_ra_info) { + if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6)) + h2c_parameter[3] |= RAINFO_BE_RX_STATE; + + if (tx_bf_en) + h2c_parameter[3] |= RAINFO_BF_STATE; + else { + if (stbc_en) + h2c_parameter[3] |= RAINFO_STBC_STATE; + } + + if (dm->noisy_decision) + h2c_parameter[3] |= RAINFO_NOISY_STATE; + else + h2c_parameter[3] &= (~RAINFO_NOISY_STATE); + + if (dm->h2c_rarpt_connect) { + h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + PHYDM_DBG(dm, DBG_RSSI_MNTR, "h2c_rarpt_connect = (( %d ))\n", dm->h2c_rarpt_connect); + } + + } + + h2c_parameter[2] = (u8)(GET_STA_INFO(entry).rssi_stat.rssi & 0xFF); + /* h2c_parameter[1] = 0x20;*/ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 */ + h2c_parameter[0] = (GET_STA_INFO(entry).mac_id); + + odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); + } + } else + break; + } + + loop_adapter = GetNextExtAdapter(loop_adapter); + } + + + /*Default port*/ + if (tmp_entry_max_pwdb != 0) { /* If associated entry is found */ + hal_data->EntryMaxUndecoratedSmoothedPWDB = tmp_entry_max_pwdb; + RT_DISP(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n", tmp_entry_max_pwdb, tmp_entry_max_pwdb)); + } else + hal_data->EntryMaxUndecoratedSmoothedPWDB = 0; + + if (tmp_entry_min_pwdb != 0xff) { /* If associated entry is found */ + hal_data->EntryMinUndecoratedSmoothedPWDB = tmp_entry_min_pwdb; + RT_DISP(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", tmp_entry_min_pwdb, tmp_entry_min_pwdb)); + + } else + hal_data->EntryMinUndecoratedSmoothedPWDB = 0; + + /* Default porti sent RSSI to FW */ + if (hal_data->bUseRAMask) { + PHYDM_DBG(dm, DBG_RSSI_MNTR, "1 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", + WIN_DEFAULT_PORT_MACID, GET_DEFAULT_RSSI(mgnt_info), hal_data->ra_rpt_linked); + if (GET_DEFAULT_RSSI(mgnt_info) > 0) { + PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_default_mgnt_info); + PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_default_mgnt_info); + + /* BF_en*/ +#if (BEAMFORMING_SUPPORT == 1) +#ifndef BEAMFORMING_VERSION_1 + beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(dm, p_default_mgnt_info->m_mac_id); + + if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + tx_bf_en = 1; +#else + if (Beamform_GetSupportBeamformerCap(GetDefaultAdapter(adapter), NULL)) + tx_bf_en = 1; +#endif +#endif + + /* STBC_en*/ + if ((IS_WIRELESS_MODE_AC(adapter) && TEST_FLAG(p_vht_info->VhtCurStbc, STBC_VHT_ENABLE_TX)) || + TEST_FLAG(p_ht_info->HtCurStbc, STBC_HT_ENABLE_TX)) + stbc_en = 1; + + h2c_parameter[4] = (ra_tab->RA_threshold_offset & 0x7f) | (ra_tab->RA_offset_direction << 7); + PHYDM_DBG(dm, DBG_RSSI_MNTR, "RA_threshold_offset = (( %s%d ))\n", ((ra_tab->RA_threshold_offset == 0) ? " " : ((ra_tab->RA_offset_direction) ? "+" : "-")), ra_tab->RA_threshold_offset); + + if (is_ext_ra_info) { + if (tx_bf_en) + h2c_parameter[3] |= RAINFO_BF_STATE; + else { + if (stbc_en) + h2c_parameter[3] |= RAINFO_STBC_STATE; + } + + if (dm->h2c_rarpt_connect) { + h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + PHYDM_DBG(dm, DBG_RSSI_MNTR, "h2c_rarpt_connect = (( %d ))\n", dm->h2c_rarpt_connect); + } + + + if (dm->noisy_decision == 1) { + h2c_parameter[3] |= RAINFO_NOISY_STATE; + PHYDM_DBG(dm, DBG_RSSI_MNTR, "[RSSIMonitorCheckMP] Send H2C to FW\n"); + } else + h2c_parameter[3] &= (~RAINFO_NOISY_STATE); + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "[RSSIMonitorCheckMP] h2c_parameter=%x\n", h2c_parameter[3]); + } + + h2c_parameter[2] = (u8)(GET_DEFAULT_RSSI(mgnt_info) & 0xFF); + /*h2c_parameter[1] = 0x20;*/ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ + h2c_parameter[0] = WIN_DEFAULT_PORT_MACID; /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ + + odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); + } + + } else + PlatformEFIOWrite1Byte(adapter, 0x4fe, (u8)GET_DEFAULT_RSSI(mgnt_info)); + + { + void *loop_adapter = GetDefaultAdapter(adapter); + boolean default_pointer_value, *is_link_temp = &default_pointer_value; + s32 global_rssi_min = 0xFF, local_rssi_min; + boolean is_link = false; + + while (loop_adapter) { + local_rssi_min = phydm_find_minimum_rssi(dm, loop_adapter, is_link_temp); + /* dbg_print("hal_data->is_linked=%d, local_rssi_min=%d\n", hal_data->is_linked, local_rssi_min); */ + + if (*is_link_temp) + is_link = true; + + if ((local_rssi_min < global_rssi_min) && (*is_link_temp)) + global_rssi_min = local_rssi_min; + + loop_adapter = GetNextExtAdapter(loop_adapter); + } + + hal_data->bLinked = is_link; + + dm->is_linked = is_link; + dm->rssi_min = (u8)((is_link) ? global_rssi_min : 0); + + } + + +} + +#endif + +void +phydm_rssi_monitor_check( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_RSSI_MONITOR)) + return; + + if ((dm->phydm_sys_up_time % 2) == 1) /*for AP watchdog period = 1 sec*/ + return; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__); + + + phydm_calculate_rssi_min_max(dm); + + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "RSSI {max, min} = {%d, %d}\n", + dm->rssi_max, dm->rssi_min); + +} + +void +phydm_rssi_monitor_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + + ra_tab->firstconnect = false; + dm->rssi_max = 0; + dm->rssi_min = 0; + +} + +#endif diff --git a/hal/phydm/phydm_rssi_monitor.h b/hal/phydm/phydm_rssi_monitor.h new file mode 100644 index 0000000..15c9e0a --- /dev/null +++ b/hal/phydm/phydm_rssi_monitor.h @@ -0,0 +1,75 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + + +#ifndef __PHYDM_RSSI_MONITOR_H__ +#define __PHYDM_RSSI_MONITOR_H__ + +#define RSSI_MONITOR_VERSION "1.0" /* 2017.05.011 Dino, Add phydm_rssi_monitor.h*/ + + +/* 1 ============================================================ + * 1 Definition + * 1 ============================================================ */ + +#define H2C_0X42_LENGTH 5 + +#define RAINFO_BE_RX_STATE BIT(0) /* 1:RX*/ /* ULDL */ +#define RAINFO_STBC_STATE BIT(1) +#define RAINFO_NOISY_STATE BIT(2) /* set by Noisy_Detection */ +/*#define RAINFO_SHURTCUT_STATE BIT(3)*/ +/*#define RAINFO_SHURTCUT_FLAG BIT(4)*/ +#define RAINFO_INIT_RSSI_RATE_STATE BIT(5) +#define RAINFO_BF_STATE BIT(6) +#define RAINFO_BE_TX_STATE BIT(7) /* 1:TX */ + +/* 1 ============================================================ + * 1 structure + * 1 ============================================================ */ + + + + +/* 1 ============================================================ + * 1 enumeration + * 1 ============================================================ */ + + + +/* 1 ============================================================ + * 1 function prototype + * 1 ============================================================ */ + +void +phydm_rssi_monitor_check( + void *dm_void +); + +void +phydm_rssi_monitor_init( + void *dm_void +); + +#endif diff --git a/hal/phydm/phydm_smt_ant.c b/hal/phydm/phydm_smt_ant.c new file mode 100644 index 0000000..323a953 --- /dev/null +++ b/hal/phydm/phydm_smt_ant.c @@ -0,0 +1,2228 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/* ****************************************************** + * when antenna test utility is on or some testing need to disable antenna diversity + * call this function to disable all ODM related mechanisms which will switch antenna. + * ****************************************************** */ +#if (defined(CONFIG_SMART_ANTENNA)) +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) +void +phydm_cumitek_smt_ant_mapping_table_8822b( + void *dm_void, + u8 *table_path_a, + u8 *table_path_b +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 path_a_0to3_idx = 0; + u32 path_b_0to3_idx = 0; + u32 path_a_4to7_idx = 0; + u32 path_b_4to7_idx = 0; + + path_a_0to3_idx = ((table_path_a[3] & 0xf) << 24) | ((table_path_a[2] & 0xf) << 16) + | ((table_path_a[1] & 0xf) << 8) | (table_path_a[0] & 0xf); + + path_b_0to3_idx = ((table_path_b[3] & 0xf) << 28) | ((table_path_b[2] & 0xf) << 20) + | ((table_path_b[1] & 0xf) << 12) | ((table_path_b[0] & 0xf) << 4); + + path_a_4to7_idx = ((table_path_a[7] & 0xf) << 24) | ((table_path_a[6] & 0xf) << 16) + | ((table_path_a[5] & 0xf) << 8) | (table_path_a[4] & 0xf); + + path_b_4to7_idx = ((table_path_b[7] & 0xf) << 28) | ((table_path_b[6] & 0xf) << 20) + | ((table_path_b[5] & 0xf) << 12) | ((table_path_b[4] & 0xf) << 4); + + + /*PHYDM_DBG(dm, DBG_SMT_ANT, "mapping table{A, B} = {0x%x, 0x%x}\n", path_a_0to3_idx, path_b_0to3_idx);*/ + + /*pathA*/ + odm_set_bb_reg(dm, 0xca4, MASKDWORD, path_a_0to3_idx); /*ant map 1*/ + odm_set_bb_reg(dm, 0xca8, MASKDWORD, path_a_4to7_idx); /*ant map 2*/ + + /*pathB*/ + odm_set_bb_reg(dm, 0xea4, MASKDWORD, path_b_0to3_idx); /*ant map 1*/ + odm_set_bb_reg(dm, 0xea8, MASKDWORD, path_b_4to7_idx); /*ant map 2*/ + +} + + +void +phydm_cumitek_smt_ant_init_8822b( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + u32 value32; + + PHYDM_DBG(dm, DBG_SMT_ANT, "[8822B Cumitek SmtAnt Int]\n"); + + /*========= MAC GPIO setting =================================*/ + + /* Pin, pin_name, RFE_CTRL_NUM*/ + + /* A0, 55, 5G_TRSW, 3*/ + /* A1, 52, 5G_TRSW, 0*/ + /* A2, 25, 5G_TRSW, 8*/ + + /* B0, 16, 5G_TRSW, 4*/ + /* B1, 13, 5G_TRSW, 11*/ + /* B2, 24, 5G_TRSW, 9*/ + + /*for RFE_CTRL 8 & 9*/ + odm_set_mac_reg(dm, 0x4c, BIT(24) | BIT(23), 2); + odm_set_mac_reg(dm, 0x44, BIT(27) | BIT(26), 0); + + /*for RFE_CTRL 0*/ + odm_set_mac_reg(dm, 0x4c, BIT(25), 0); + odm_set_mac_reg(dm, 0x64, BIT(29), 1); + + /*for RFE_CTRL 2 & 3*/ + odm_set_mac_reg(dm, 0x4c, BIT(26), 0); + odm_set_mac_reg(dm, 0x64, BIT(28), 1); + + /*for RFE_CTRL 11*/ + odm_set_mac_reg(dm, 0x40, BIT(3), 1); + + + /*0x604[25]=1 : 2bit mode for pathA&B&C&D*/ + /*0x604[25]=0 : 3bit mode for pathA&B*/ + smtant_table->tx_desc_mode = 0; + odm_set_mac_reg(dm, 0x604, BIT(25), (u32)smtant_table->tx_desc_mode); + + /*========= BB RFE setting =================================*/ + #if 0 + /*path A*/ + odm_set_bb_reg(dm, 0x1990, BIT(3), 0); /*RFE_CTRL_3*/ /*A_0*/ + odm_set_bb_reg(dm, 0xcbc, BIT(3), 0); /*inv*/ + odm_set_bb_reg(dm, 0xcb0, 0xf000, 8); + + odm_set_bb_reg(dm, 0x1990, BIT(0), 0); /*RFE_CTRL_0*/ /*A_1*/ + odm_set_bb_reg(dm, 0xcbc, BIT(0), 0); /*inv*/ + odm_set_bb_reg(dm, 0xcb0, 0xf, 0x9); + + odm_set_bb_reg(dm, 0x1990, BIT(8), 0); /*RFE_CTRL_8*/ /*A_2*/ + odm_set_bb_reg(dm, 0xcbc, BIT(8), 0); /*inv*/ + odm_set_bb_reg(dm, 0xcb4, 0xf, 0xa); + + + /*path B*/ + odm_set_bb_reg(dm, 0x1990, BIT(4), 1); /*RFE_CTRL_4*/ /*B_0*/ + odm_set_bb_reg(dm, 0xdbc, BIT(4), 0); /*inv*/ + odm_set_bb_reg(dm, 0xdb0, 0xf0000, 0xb); + + odm_set_bb_reg(dm, 0x1990, BIT(11), 1); /*RFE_CTRL_11*/ /*B_1*/ + odm_set_bb_reg(dm, 0xdbc, BIT(11), 0); /*inv*/ + odm_set_bb_reg(dm, 0xdb4, 0xf000, 0xc); + + odm_set_bb_reg(dm, 0x1990, BIT(9), 1); /*RFE_CTRL_9*/ /*B_2*/ + odm_set_bb_reg(dm, 0xdbc, BIT(9), 0); /*inv*/ + odm_set_bb_reg(dm, 0xdb4, 0xf0, 0xd); + #endif + /*========= BB SmtAnt setting =================================*/ + odm_set_mac_reg(dm, 0x6d8, BIT(22) | BIT(21), 2); /*resp tx by register*/ + odm_set_mac_reg(dm, 0x668, BIT(3), 1); + odm_set_bb_reg(dm, 0x804, BIT(4), 0); /*lathch antsel*/ + odm_set_bb_reg(dm, 0x818, 0xf00000, 0); /*keep tx by rx*/ + odm_set_bb_reg(dm, 0x900, BIT(19), 0); /*fast train*/ + odm_set_bb_reg(dm, 0x900, BIT(18), 1); /*1: by TXDESC*/ + + /*pathA*/ + odm_set_bb_reg(dm, 0xca4, MASKDWORD, 0x03020100); /*ant map 1*/ + odm_set_bb_reg(dm, 0xca8, MASKDWORD, 0x07060504); /*ant map 2*/ + odm_set_bb_reg(dm, 0xcac, BIT(9), 0); /*keep antsel map by GNT_BT*/ + + /*pathB*/ + odm_set_bb_reg(dm, 0xea4, MASKDWORD, 0x30201000); /*ant map 1*/ + odm_set_bb_reg(dm, 0xea8, MASKDWORD, 0x70605040); /*ant map 2*/ + odm_set_bb_reg(dm, 0xeac, BIT(9), 0); /*keep antsel map by GNT_BT*/ +} + +void +phydm_cumitek_smt_ant_init_8197f( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + u32 value32; + + PHYDM_DBG(dm, DBG_SMT_ANT, "[8197F Cumitek SmtAnt Int]\n"); + + /*GPIO setting*/ + + +} + +void +phydm_cumitek_smt_tx_ant_update( + void *dm_void, + u8 tx_ant_idx_path_a, + u8 tx_ant_idx_path_b, + u32 mac_id +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[Cumitek] Set TX-ANT[%d] = (( A:0x%x , B:0x%x ))\n", + mac_id, tx_ant_idx_path_a, tx_ant_idx_path_b); + + /*path-A*/ + cumi_smtant_table->tx_ant_idx[0][mac_id] = tx_ant_idx_path_a; /*fill this value into TXDESC*/ + + /*path-B*/ + cumi_smtant_table->tx_ant_idx[1][mac_id] = tx_ant_idx_path_b; /*fill this value into TXDESC*/ +} + +void +phydm_cumitek_smt_rx_default_ant_update( + void *dm_void, + u8 rx_ant_idx_path_a, + u8 rx_ant_idx_path_b +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[Cumitek] Set RX-ANT = (( A:0x%x, B:0x%x ))\n", + rx_ant_idx_path_a, rx_ant_idx_path_b); + + /*path-A*/ + if (cumi_smtant_table->rx_default_ant_idx[0] != rx_ant_idx_path_a) { + + #if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + + odm_set_bb_reg(dm, 0xc08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_a); /*default RX antenna*/ + odm_set_mac_reg(dm, 0x6d8, BIT(2) | BIT(1) | BIT(0), rx_ant_idx_path_a); /*default response TX antenna*/ + } + #endif + + #if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F) { + } + #endif + + cumi_smtant_table->rx_default_ant_idx[0] = rx_ant_idx_path_a; + } + + /*path-B*/ + if (cumi_smtant_table->rx_default_ant_idx[1] != rx_ant_idx_path_b) { + + #if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + + odm_set_bb_reg(dm, 0xe08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_b); /*default antenna*/ + odm_set_mac_reg(dm, 0x6d8, BIT(5) | BIT(4) | BIT(3), rx_ant_idx_path_b); /*default response TX antenna*/ + } + #endif + + #if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F) { + } + #endif + + cumi_smtant_table->rx_default_ant_idx[1] = rx_ant_idx_path_b; + } + +} + +void +phydm_cumitek_smt_ant_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + u32 used = *_used; + u32 out_len = *_out_len; + char help[] = "-h"; + u32 dm_value[10] = {0}; + u8 i; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]); + + if (strcmp(input[1], help) == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {PathA rx_ant_idx} {pathB rx_ant_idx}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2} {PathA tx_ant_idx} {pathB tx_ant_idx} {macid}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{3} {PathA mapping table} {PathB mapping table}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{4} {txdesc_mode 0:3bit, 1:2bit}\n"); + + } else if (dm_value[0] == 1) { /*fix rx_idle pattern*/ + + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]); + + phydm_cumitek_smt_rx_default_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "RX Ant{A, B}={%d, %d}\n", dm_value[1], + dm_value[2]); + + } else if (dm_value[0] == 2) { /*fix tx pattern*/ + + + for (i = 1; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "STA[%d] TX Ant{A, B}={%d, %d}\n",dm_value[3], + dm_value[1], dm_value[2]); + phydm_cumitek_smt_tx_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2], (u8)dm_value[3]); + + } else if (dm_value[0] == 3) { + u8 table_path_a[8] = {0}; + u8 table_path_b[8] = {0}; + + for (i = 1; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set Path-AB mapping table={%d, %d}\n", + dm_value[1], dm_value[2]); + + for (i = 0; i <8; i++) { + table_path_a[i] = (u8)((dm_value[1] >> (4 * i)) & 0xf); + table_path_b[i] = (u8)((dm_value[2] >> (4 * i)) & 0xf); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Ant_Table_A[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\n", + + table_path_a[7], table_path_a[6], + table_path_a[5], table_path_a[4], + table_path_a[3], table_path_a[2], + table_path_a[1], table_path_a[0]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Ant_Table_B[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\n", + + table_path_b[7], table_path_b[6], + table_path_b[5], table_path_b[4], + table_path_b[3], table_path_b[2], + table_path_b[1], table_path_b[0]); + + phydm_cumitek_smt_ant_mapping_table_8822b(dm, + &table_path_a[0], + &table_path_b[0]); + }else if (dm_value[0] == 4) { + smtant_table->tx_desc_mode = (u8)dm_value[1]; + odm_set_mac_reg(dm, 0x604, BIT(25), (u32)smtant_table->tx_desc_mode); + } + *_used = used; + *_out_len = out_len; +} + +#endif + +#if (defined(CONFIG_HL_SMART_ANTENNA)) +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + +#if (RTL8822B_SUPPORT == 1) +void +phydm_hl_smart_ant_type2_init_8822b( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 j; + u8 rfu_codeword_table_init_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = { + {1, 1},/*0*/ + {1, 2}, + {2, 1}, + {2, 2}, + {4, 0}, + {5, 0}, + {6, 0}, + {7, 0}, + {8, 0},/*8*/ + {9, 0}, + {0xa, 0}, + {0xb, 0}, + {0xc, 0}, + {0xd, 0}, + {0xe, 0}, + {0xf, 0} + }; + u8 rfu_codeword_table_init_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] ={ + #if 1 + {9, 1},/*0*/ + {9, 9}, + {1, 9}, + {9, 6}, + {2, 1}, + {2, 9}, + {9, 2}, + {2, 2},/*8*/ + {6, 1}, + {6, 9}, + {2, 9}, + {2, 2}, + {6, 2}, + {6, 6}, + {2, 6}, + {1, 1} + #else + {1, 1},/*0*/ + {9, 1}, + {9, 9}, + {1, 9}, + {1, 2}, + {9, 2}, + {9, 6}, + {1, 6}, + {2, 1},/*8*/ + {6, 1}, + {6, 9}, + {2, 9}, + {2, 2}, + {6, 2}, + {6, 6}, + {2, 6} + #endif + }; + + PHYDM_DBG(dm, DBG_ANT_DIV, "***RTK 8822B SmartAnt_Init: Hong-Bo SmrtAnt Type2]\n"); + + /* ---------------------------------------- */ + /* GPIO 0-1 for Beam control */ + /* reg0x66[2:0]=0 */ + /* reg0x44[25:24] = 0 */ + /* reg0x44[23:16] enable_output for P_GPIO[7:0] */ + /* reg0x44[15:8] output_value for P_GPIO[7:0] */ + /* reg0x40[1:0] = 0 GPIO function */ + /* ------------------------------------------ */ + + odm_move_memory(dm, sat_tab->rfu_codeword_table_2g, rfu_codeword_table_init_2g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B)); + odm_move_memory(dm, sat_tab->rfu_codeword_table_5g, rfu_codeword_table_init_5g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B)); + + /*GPIO setting*/ + odm_set_mac_reg(dm, 0x64, (BIT(18) | BIT(17) | BIT(16)), 0); + odm_set_mac_reg(dm, 0x44, BIT(25) | BIT(24), 0); /*config P_GPIO[3:2] to data port*/ + odm_set_mac_reg(dm, 0x44, BIT(17) | BIT(16), 0x3); /*enable_output for P_GPIO[3:2]*/ + /*odm_set_mac_reg(dm, 0x44, BIT(9)|BIT(8), 0);*/ /*P_GPIO[3:2] output value*/ + odm_set_mac_reg(dm, 0x40, BIT(1) | BIT(0), 0); /*GPIO function*/ + + /*Hong_lin smart antenna HW setting*/ + sat_tab->rfu_protocol_type = 2; + sat_tab->rfu_protocol_delay_time = 45; + + sat_tab->rfu_codeword_total_bit_num = 16;/*max=32bit*/ + sat_tab->rfu_each_ant_bit_num = 4; + + sat_tab->total_beam_set_num = 4; + sat_tab->total_beam_set_num_2g = 4; + sat_tab->total_beam_set_num_5g = 8; + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + sat_tab->latch_time = 100; /*mu sec*/ +#elif DEV_BUS_TYPE == RT_USB_INTERFACE + sat_tab->latch_time = 100; /*mu sec*/ +#endif + sat_tab->pkt_skip_statistic_en = 0; + + sat_tab->ant_num = 2; + sat_tab->ant_num_total = MAX_PATH_NUM_8822B; + sat_tab->first_train_ant = MAIN_ANT; + + + + sat_tab->fix_beam_pattern_en = 0; + sat_tab->decision_holding_period = 0; + + /*beam training setting*/ + sat_tab->pkt_counter = 0; + sat_tab->per_beam_training_pkt_num = 10; + + /*set default beam*/ + sat_tab->fast_training_beam_num = 0; + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + + for (j = 0; j < SUPPORT_BEAM_SET_PATTERN_NUM; j++) { + + sat_tab->beam_set_avg_rssi_pre[j] = 0; + sat_tab->beam_set_train_val_diff[j] = 0; + sat_tab->beam_set_train_cnt[j] = 0; + } + phydm_set_rfu_beam_pattern_type2(dm); + fat_tab->fat_state = FAT_BEFORE_LINK_STATE; + +} +#endif + + +u32 +phydm_construct_hb_rfu_codeword_type2( + void *dm_void, + u32 beam_set_idx +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 sync_codeword = 0x7f; + u32 codeword = 0; + u32 data_tmp = 0; + u32 i; + + for (i = 0; i < sat_tab->ant_num_total; i++) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[beam_set_idx][i]; + else + data_tmp = sat_tab->rfu_codeword_table_2g[beam_set_idx][i]; + + codeword |= (data_tmp << (i * sat_tab->rfu_each_ant_bit_num)); + } + + codeword = (codeword<<8) | sync_codeword; + + return codeword; +} + +void +phydm_update_beam_pattern_type2( + void *dm_void, + u32 codeword, + u32 codeword_length +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u8 i; + boolean beam_ctrl_signal; + u32 one = 0x1; + u32 reg44_tmp_p, reg44_tmp_n, reg44_ori; + u8 devide_num = 4; + + PHYDM_DBG(dm, DBG_ANT_DIV, "Set codeword = ((0x%x))\n", codeword); + + reg44_ori = odm_get_mac_reg(dm, 0x44, MASKDWORD); + reg44_tmp_p = reg44_ori; + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_ori =0x%x\n", reg44_ori);*/ + + /*devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/ + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i); + + #if 1 + if (dm->debug_components & DBG_ANT_DIV) { + if (i == (codeword_length - 1)) { + pr_debug("%d ]\n", beam_ctrl_signal); + /**/ + } else if (i == 0) { + pr_debug("Start sending codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal); + /**/ + } else if ((i % devide_num) == (devide_num-1)) { + pr_debug("%d | ", beam_ctrl_signal); + /**/ + } else { + pr_debug("%d ", beam_ctrl_signal); + /**/ + } + } + #endif + + if (dm->support_ic_type == ODM_RTL8821) { + #if (RTL8821A_SUPPORT == 1) + reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*clean bit 10 & 11*/ + reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10)); + reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10))); + + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n);*/ + odm_set_mac_reg(dm, 0x44, MASKDWORD, reg44_tmp_p); + odm_set_mac_reg(dm, 0x44, MASKDWORD, reg44_tmp_n); + #endif + } + #if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) { + if (sat_tab->rfu_protocol_type == 2) { + reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*clean bit 8*/ + reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*get new clk high/low, exclusive-or*/ + + + reg44_tmp_p |= (beam_ctrl_signal << 8); + + odm_set_mac_reg(dm, 0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(sat_tab->rfu_protocol_delay_time); + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/ + + } else { + reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*clean bit 9 & 8*/ + reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8)); + reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8))); + + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n); */ + odm_set_mac_reg(dm, 0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(10); + odm_set_mac_reg(dm, 0x44, MASKDWORD, reg44_tmp_n); + ODM_delay_us(10); + } + } + #endif + } +} + +void +phydm_update_rx_idle_beam_type2( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 i; + + sat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->rx_idle_beam_set_idx); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-Beam ] BeamSet idx = ((%d))\n", sat_tab->rx_idle_beam_set_idx); + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); +#else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); + /*odm_stall_execution(1);*/ +#endif + + sat_tab->pre_codeword = sat_tab->update_beam_codeword; +} + + +void +phydm_hl_smart_ant_debug_type2( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 used = *_used; + u32 out_len = *_out_len; + u32 one = 0x1; + u32 codeword_length = sat_tab->rfu_codeword_total_bit_num; + u32 beam_ctrl_signal, i; + u8 devide_num = 4; + char help[] = "-h"; + u32 dm_value[10] = {0}; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]); + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]); + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &dm_value[3]); + PHYDM_SSCANF(input[5], DCMD_DECIMAL, &dm_value[4]); + + + if (strcmp(input[1], help) == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + " 1 {fix_en} {codeword(Hex)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " 3 {Fix_training_num_en} {Per_beam_training_pkt_num} {Decision_holding_period}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " 5 {0:show, 1:2G, 2:5G} {beam_num} {idxA(Hex)} {idxB(Hex)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " 7 {0:show, 1:2G, 2:5G} {total_beam_set_num}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " 8 {0:show, 1:set} {RFU delay time(us)}\n"); + + } else if (dm_value[0] == 1) { /*fix beam pattern*/ + + sat_tab->fix_beam_pattern_en = dm_value[1]; + + if (sat_tab->fix_beam_pattern_en == 1) { + PHYDM_SSCANF(input[3], DCMD_HEX, &dm_value[2]); + sat_tab->fix_beam_pattern_codeword = dm_value[2]; + + if (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n", + sat_tab->fix_beam_pattern_codeword, codeword_length); + + (sat_tab->fix_beam_pattern_codeword) &= 0xffffff; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Auto modify to (0x%x)\n", sat_tab->fix_beam_pattern_codeword); + } + + sat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword; + + /*---------------------------------------------------------*/ + PDM_SNPF(out_len, used, output + used, + out_len - used, "Fix Beam Pattern\n"); + + /*devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/ + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i); + + if (i == (codeword_length - 1)) { + PDM_SNPF(out_len, used, + output + used, + out_len - used, + "%d]\n", + beam_ctrl_signal); + /**/ + } else if (i == 0) { + PDM_SNPF(out_len, used, + output + used, + out_len - used, + "Send Codeword[1:%d] to RFU -> [%d", + sat_tab->rfu_codeword_total_bit_num, + beam_ctrl_signal); + /**/ + } else if ((i % devide_num) == (devide_num-1)) { + PDM_SNPF(out_len, used, + output + used, + out_len - used, "%d|", + beam_ctrl_signal); + /**/ + } else { + PDM_SNPF(out_len, used, + output + used, + out_len - used, "%d", + beam_ctrl_signal); + /**/ + } + } + /*---------------------------------------------------------*/ + + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + #else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); + /*odm_stall_execution(1);*/ + #endif + } else if (sat_tab->fix_beam_pattern_en == 0) + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Smart Antenna: Enable\n"); + + } else if (dm_value[0] == 2) { /*set latch time*/ + + sat_tab->latch_time = dm_value[1]; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] latch_time =0x%x\n", sat_tab->latch_time); + } else if (dm_value[0] == 3) { + sat_tab->fix_training_num_en = dm_value[1]; + + if (sat_tab->fix_training_num_en == 1) { + sat_tab->per_beam_training_pkt_num = (u8)dm_value[2]; + sat_tab->decision_holding_period = (u8)dm_value[3]; + + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[SmtAnt] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", + sat_tab->fix_training_num_en, + sat_tab->per_beam_training_pkt_num, + sat_tab->decision_holding_period); + + } else if (sat_tab->fix_training_num_en == 0) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] AUTO per_beam_training_pkt_num\n"); + /**/ + } + } else if (dm_value[0] == 4) { + #if 0 + if (dm_value[1] == 1) { + sat_tab->ant_num = 1; + sat_tab->first_train_ant = MAIN_ANT; + + } else if (dm_value[1] == 2) { + sat_tab->ant_num = 1; + sat_tab->first_train_ant = AUX_ANT; + + } else if (dm_value[1] == 3) { + sat_tab->ant_num = 2; + sat_tab->first_train_ant = MAIN_ANT; + } + + PDM_SNPF((output + used, out_len - used, "[ SmartAnt ] Set ant Num = (( %d )), first_train_ant = (( %d ))\n", + sat_tab->ant_num, (sat_tab->first_train_ant - 1))); + #endif + } else if (dm_value[0] == 5) { /*set beam set table*/ + + PHYDM_SSCANF(input[4], DCMD_HEX, &dm_value[3]); + PHYDM_SSCANF(input[5], DCMD_HEX, &dm_value[4]); + + if (dm_value[1] == 1) { /*2G*/ + if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { + sat_tab->rfu_codeword_table_2g[dm_value[2] ][0] = (u8)dm_value[3]; + sat_tab->rfu_codeword_table_2g[dm_value[2] ][1] = (u8)dm_value[4]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[SmtAnt] Set 2G Table[%d] = [A:0x%x, B:0x%x]\n", + dm_value[2], dm_value[3], + dm_value[4]); + } + + } else if (dm_value[1] == 2) { /*5G*/ + if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { + sat_tab->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3]; + sat_tab->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n", + dm_value[2], dm_value[3], + dm_value[4]); + } + } else if (dm_value[1] == 0) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[SmtAnt] 2G Beam Table==============>\n"); + for (i = 0; i < sat_tab->total_beam_set_num_2g; i++) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "2G Table[%d] = [A:0x%x, B:0x%x]\n", + i, + sat_tab->rfu_codeword_table_2g[i][0], + sat_tab->rfu_codeword_table_2g[i][1]); + } + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[SmtAnt] 5G Beam Table==============>\n"); + for (i = 0; i < sat_tab->total_beam_set_num_5g; i++) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "5G Table[%d] = [A:0x%x, B:0x%x]\n", + i, + sat_tab->rfu_codeword_table_5g[i][0], + sat_tab->rfu_codeword_table_5g[i][1]); + } + } + + } else if (dm_value[0] == 6) { + #if 0 + if (dm_value[1] == 0) { + if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { + sat_tab->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3]; + sat_tab->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4]; + PDM_SNPF((output + used, out_len - used, "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",dm_value[2], dm_value[3], dm_value[4])); + } + } else { + for (i = 0; i < sat_tab->total_beam_set_num_5g; i++) { + PDM_SNPF((output + used, out_len - used, "[SmtAnt] Read 5G Table[%d] = [A:0x%x, B:0x%x]\n", + i, sat_tab->rfu_codeword_table_5g[i][0], sat_tab->rfu_codeword_table_5g[i][1])); + } + } + #endif + } else if (dm_value[0] == 7) { + if (dm_value[1] == 1) { + sat_tab->total_beam_set_num_2g = (u8)(dm_value[2]); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] total_beam_set_num_2g = ((%d))\n", + sat_tab->total_beam_set_num_2g); + + } else if (dm_value[1] == 2) { + sat_tab->total_beam_set_num_5g = (u8)(dm_value[2]); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] total_beam_set_num_5g = ((%d))\n", + sat_tab->total_beam_set_num_5g); + } else if (dm_value[1] == 0) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Show total_beam_set_num{2g,5g} = {%d,%d}\n", + + sat_tab->total_beam_set_num_2g, + sat_tab->total_beam_set_num_5g); + } + + } else if (dm_value[0] == 8) { + if (dm_value[1] == 1) { + sat_tab->rfu_protocol_delay_time = (u16)(dm_value[2]); + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[SmtAnt] Set rfu_protocol_delay_time = ((%d))\n", + sat_tab->rfu_protocol_delay_time); + } else if (dm_value[1] == 0) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[SmtAnt] Read rfu_protocol_delay_time = ((%d))\n", + sat_tab->rfu_protocol_delay_time); + } + } + + *_used = used; + *_out_len = out_len; +} + +void +phydm_set_rfu_beam_pattern_type2( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + + if (dm->ant_div_type != HL_SW_SMART_ANT_TYPE2) + return; + + PHYDM_DBG(dm, DBG_ANT_DIV, "Training beam_set index = (( 0x%x ))\n", sat_tab->fast_training_beam_num); + sat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->fast_training_beam_num); + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + #else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); + /*odm_stall_execution(1);*/ + #endif +} + +void +phydm_fast_ant_training_hl_smart_antenna_type2( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + u32 codeword = 0; + u8 i = 0, j=0; + u8 avg_rssi_tmp; + u8 avg_rssi_tmp_ma; + u8 max_beam_ant_rssi = 0; + u8 rssi_target_beam = 0, target_beam_max_rssi = 0; + u8 evm1ss_target_beam = 0, evm2ss_target_beam = 0; + u32 target_beam_max_evm1ss = 0, target_beam_max_evm2ss = 0; + u32 beam_tmp; + u8 per_beam_val_diff_tmp = 0, training_pkt_num_offset; + u32 avg_evm2ss[2] = {0}, avg_evm2ss_sum = 0; + u32 avg_evm1ss = 0; + u32 beam_path_evm_2ss_cnt_all = 0; /*sum of all 2SS-pattern cnt*/ + u32 beam_path_evm_1ss_cnt_all = 0; /*sum of all 1SS-pattern cnt*/ + u8 decision_type; + + if (!dm->is_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); + + if (fat_tab->is_become_linked == true) { + sat_tab->decision_holding_period = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "Link->no Link\n"); + fat_tab->fat_state = FAT_BEFORE_LINK_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "change to (( %d )) FAT_state\n", fat_tab->fat_state); + fat_tab->is_become_linked = dm->is_linked; + } + return; + + } else { + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n"); + + fat_tab->fat_state = FAT_PREPARE_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "change to (( %d )) FAT_state\n", fat_tab->fat_state); + + /*sat_tab->fast_training_beam_num = 0;*/ + /*phydm_set_rfu_beam_pattern_type2(dm);*/ + + fat_tab->is_become_linked = dm->is_linked; + } + } + + + /*PHYDM_DBG(dm, DBG_ANT_DIV, "HL Smart ant Training: state (( %d ))\n", fat_tab->fat_state);*/ + + /* [DECISION STATE] */ + /*=======================================================================================*/ + if (fat_tab->fat_state == FAT_DECISION_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 3. In Decision state]\n"); + + /*compute target beam in each antenna*/ + + for (j = 0; j < (sat_tab->total_beam_set_num); j++) { + /*[Decision1: RSSI]-------------------------------------------------------------------*/ + if (sat_tab->statistic_pkt_cnt[j] == 0) { /*if new RSSI = 0 -> MA_RSSI-=2*/ + avg_rssi_tmp = sat_tab->beam_set_avg_rssi_pre[j]; + avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; + avg_rssi_tmp_ma = avg_rssi_tmp; + } else { + avg_rssi_tmp = (u8)((sat_tab->beam_set_rssi_avg_sum[j]) / (sat_tab->statistic_pkt_cnt[j])); + avg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->beam_set_avg_rssi_pre[j]) >> 1; + } + + sat_tab->beam_set_avg_rssi_pre[j] = avg_rssi_tmp; + + if (avg_rssi_tmp > target_beam_max_rssi) { + rssi_target_beam = j; + target_beam_max_rssi = avg_rssi_tmp; + } + + /*[Decision2: EVM 2ss]-------------------------------------------------------------------*/ + if (sat_tab->beam_path_evm_2ss_cnt[j] != 0) { + avg_evm2ss[0] = sat_tab->beam_path_evm_2ss_sum[j][0] / sat_tab->beam_path_evm_2ss_cnt[j]; + avg_evm2ss[1] = sat_tab->beam_path_evm_2ss_sum[j][1] / sat_tab->beam_path_evm_2ss_cnt[j]; + avg_evm2ss_sum = avg_evm2ss[0] + avg_evm2ss[1]; + beam_path_evm_2ss_cnt_all += sat_tab->beam_path_evm_2ss_cnt[j]; + + sat_tab->beam_set_avg_evm_2ss_pre[j] = (u8)avg_evm2ss_sum; + } + + if (avg_evm2ss_sum > target_beam_max_evm2ss) { + evm2ss_target_beam = j; + target_beam_max_evm2ss = avg_evm2ss_sum; + } + + /*[Decision3: EVM 1ss]-------------------------------------------------------------------*/ + if (sat_tab->beam_path_evm_1ss_cnt[j] != 0) { + avg_evm1ss = sat_tab->beam_path_evm_1ss_sum[j] / sat_tab->beam_path_evm_1ss_cnt[j]; + beam_path_evm_1ss_cnt_all += sat_tab->beam_path_evm_1ss_cnt[j]; + + sat_tab->beam_set_avg_evm_1ss_pre[j] = (u8)avg_evm1ss; + } + + if (avg_evm1ss > target_beam_max_evm1ss) { + evm1ss_target_beam = j; + target_beam_max_evm1ss = avg_evm1ss; + } + + PHYDM_DBG(dm, DBG_ANT_DIV, "Beam[%d] Pkt_cnt=(( %d )), avg{MA,rssi}={%d, %d}, EVM1={%d}, EVM2={%d, %d, %d}\n", + j, sat_tab->statistic_pkt_cnt[j], avg_rssi_tmp_ma, avg_rssi_tmp, avg_evm1ss, avg_evm2ss[0], avg_evm2ss[1], avg_evm2ss_sum); + + /*reset counter value*/ + sat_tab->beam_set_rssi_avg_sum[j] = 0; + sat_tab->beam_path_rssi_sum[j][0] = 0; + sat_tab->beam_path_rssi_sum[j][1] = 0; + sat_tab->statistic_pkt_cnt[j] = 0; + + sat_tab->beam_path_evm_2ss_sum[j][0] = 0; + sat_tab->beam_path_evm_2ss_sum[j][1] = 0; + sat_tab->beam_path_evm_2ss_cnt[j] = 0; + + sat_tab->beam_path_evm_1ss_sum[j] = 0; + sat_tab->beam_path_evm_1ss_cnt[j] = 0; + } + + /*[Joint Decision]-------------------------------------------------------------------*/ + PHYDM_DBG(dm, DBG_ANT_DIV, "--->1.[RSSI] Target Beam(( %d )) RSSI_max=((%d))\n", rssi_target_beam, target_beam_max_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, "--->2.[Evm2SS] Target Beam(( %d )) EVM2SS_max=((%d))\n", evm2ss_target_beam, target_beam_max_evm2ss); + PHYDM_DBG(dm, DBG_ANT_DIV, "--->3.[Evm1SS] Target Beam(( %d )) EVM1SS_max=((%d))\n", evm1ss_target_beam, target_beam_max_evm1ss); + + if (target_beam_max_rssi <= 10) { + sat_tab->rx_idle_beam_set_idx = rssi_target_beam; + decision_type = 1; + } else { + if (beam_path_evm_2ss_cnt_all != 0) { + sat_tab->rx_idle_beam_set_idx = evm2ss_target_beam; + decision_type = 2; + } else if (beam_path_evm_1ss_cnt_all != 0) { + sat_tab->rx_idle_beam_set_idx = evm1ss_target_beam; + decision_type = 3; + } else { + sat_tab->rx_idle_beam_set_idx = rssi_target_beam; + decision_type = 1; + } + } + + PHYDM_DBG(dm, DBG_ANT_DIV, "---> Decision_type=((%d)), Final Target Beam(( %d ))\n", decision_type, sat_tab->rx_idle_beam_set_idx); + + /*Calculate packet counter offset*/ + for (j = 0; j < (sat_tab->total_beam_set_num); j++) { + if (decision_type == 1) { + per_beam_val_diff_tmp = target_beam_max_rssi - sat_tab->beam_set_avg_rssi_pre[j]; + + } else if (decision_type == 2) { + per_beam_val_diff_tmp = ((u8)target_beam_max_evm2ss - sat_tab->beam_set_avg_evm_2ss_pre[j]) >> 1; + } else if (decision_type == 3) { + per_beam_val_diff_tmp = (u8)target_beam_max_evm1ss - sat_tab->beam_set_avg_evm_1ss_pre[j]; + } + sat_tab->beam_set_train_val_diff[j] = per_beam_val_diff_tmp; + PHYDM_DBG(dm, DBG_ANT_DIV, "Beam_Set[%d]: diff= ((%d))\n", j, per_beam_val_diff_tmp); + } + + /*set beam in each antenna*/ + phydm_update_rx_idle_beam_type2(dm); + fat_tab->fat_state = FAT_PREPARE_STATE; + + } + /* [TRAINING STATE] */ + else if (fat_tab->fat_state == FAT_TRAINING_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2. In Training state]\n"); + + PHYDM_DBG(dm, DBG_ANT_DIV, "curr_beam_idx = (( %d )), pre_beam_idx = (( %d ))\n", + sat_tab->fast_training_beam_num, sat_tab->pre_fast_training_beam_num); + + if (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num) + + sat_tab->force_update_beam_en = 0; + + else { + sat_tab->force_update_beam_en = 1; + + sat_tab->pkt_counter = 0; + beam_tmp = sat_tab->fast_training_beam_num; + if (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", sat_tab->fast_training_beam_num); + fat_tab->fat_state = FAT_DECISION_STATE; + phydm_fast_ant_training_hl_smart_antenna_type2(dm); + + } else { + sat_tab->fast_training_beam_num++; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num); + phydm_set_rfu_beam_pattern_type2(dm); + fat_tab->fat_state = FAT_TRAINING_STATE; + + } + } + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + PHYDM_DBG(dm, DBG_ANT_DIV, "Update Pre_Beam =(( %d ))\n", sat_tab->pre_fast_training_beam_num); + } + /* [Prepare state] */ + /*=======================================================================================*/ + else if (fat_tab->fat_state == FAT_PREPARE_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "\n\n[ 1. In Prepare state]\n"); + + if (dm->pre_traffic_load == (dm->traffic_load)) { + if (sat_tab->decision_holding_period != 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Holding_period = (( %d )), return!!!\n", sat_tab->decision_holding_period); + sat_tab->decision_holding_period--; + return; + } + } + + /* Set training packet number*/ + if (sat_tab->fix_training_num_en == 0) { + switch (dm->traffic_load) { + case TRAFFIC_HIGH: + sat_tab->per_beam_training_pkt_num = 8; + sat_tab->decision_holding_period = 2; + break; + case TRAFFIC_MID: + sat_tab->per_beam_training_pkt_num = 6; + sat_tab->decision_holding_period = 3; + break; + case TRAFFIC_LOW: + sat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/ + sat_tab->decision_holding_period = 4; + break; + case TRAFFIC_ULTRA_LOW: + sat_tab->per_beam_training_pkt_num = 1; + sat_tab->decision_holding_period = 6; + break; + default: + break; + } + } + + PHYDM_DBG(dm, DBG_ANT_DIV, "TrafficLoad = (( %d )), Fix_beam = (( %d )), per_beam_training_pkt_num = (( %d )), decision_holding_period = ((%d))\n", + dm->traffic_load, sat_tab->fix_training_num_en, sat_tab->per_beam_training_pkt_num, sat_tab->decision_holding_period); + + /*Beam_set number*/ + if (*dm->band_type == ODM_BAND_5G) { + sat_tab->total_beam_set_num = sat_tab->total_beam_set_num_5g; + PHYDM_DBG(dm, DBG_ANT_DIV, "5G beam_set num = ((%d))\n", sat_tab->total_beam_set_num); + } else { + sat_tab->total_beam_set_num = sat_tab->total_beam_set_num_2g; + PHYDM_DBG(dm, DBG_ANT_DIV, "2G beam_set num = ((%d))\n", sat_tab->total_beam_set_num); + } + + for (j = 0; j < (sat_tab->total_beam_set_num); j++) { + training_pkt_num_offset = sat_tab->beam_set_train_val_diff[j]; + + if ((sat_tab->per_beam_training_pkt_num) > training_pkt_num_offset) + sat_tab->beam_set_train_cnt[j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset; + else + sat_tab->beam_set_train_cnt[j] = 1; + + PHYDM_DBG(dm, DBG_ANT_DIV, "Beam_Set[ %d ] training_pkt_offset = ((%d)), training_pkt_num = ((%d))\n", + j, sat_tab->beam_set_train_val_diff[j], sat_tab->beam_set_train_cnt[j]); + } + + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->update_beam_idx = 0; + sat_tab->pkt_counter = 0; + + sat_tab->fast_training_beam_num = 0; + phydm_set_rfu_beam_pattern_type2(dm); + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + fat_tab->fat_state = FAT_TRAINING_STATE; + } + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void +phydm_beam_switch_workitem_callback( + void *context +) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE + sat_tab->pkt_skip_statistic_en = 1; +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", sat_tab->pkt_skip_statistic_en); + + phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE + /*odm_stall_execution(sat_tab->latch_time);*/ + sat_tab->pkt_skip_statistic_en = 0; +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, "pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", sat_tab->pkt_skip_statistic_en, sat_tab->latch_time); +} + +void +phydm_beam_decision_workitem_callback( + void *context +) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Beam decision Workitem Callback\n"); + phydm_fast_ant_training_hl_smart_antenna_type2(dm); +} +#endif + +void +phydm_process_rssi_for_hb_smtant_type2( + void *dm_void, + void *phy_info_void, + void *pkt_info_void, + u8 rssi_avg +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u8 train_pkt_number; + u32 beam_tmp; + u8 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0]; + u8 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1]; + u8 rx_evm_ant0 = phy_info->rx_mimo_evm_dbm[0]; + u8 rx_evm_ant1 = phy_info->rx_mimo_evm_dbm[1]; + + /*[Beacon]*/ + if (pktinfo->is_packet_beacon) { + sat_tab->beacon_counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, "MatchBSSID_beacon_counter = ((%d))\n", sat_tab->beacon_counter); + + if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) { + sat_tab->update_beam_idx++; + PHYDM_DBG(dm, DBG_ANT_DIV, "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", + sat_tab->pre_beacon_counter, sat_tab->pkt_counter, sat_tab->update_beam_idx); + + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->pkt_counter = 0; + } + } + /*[data]*/ + else if (pktinfo->is_packet_to_self) { + if (sat_tab->pkt_skip_statistic_en == 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, "ID[%d] pkt_cnt=((%d)): Beam_set = ((%d)), RSSI{A,B,avg} = {%d, %d, %d}\n", + pktinfo->station_id, sat_tab->pkt_counter, sat_tab->fast_training_beam_num, rx_power_ant0, rx_power_ant1, rssi_avg); + + PHYDM_DBG(dm, DBG_ANT_DIV, "Rate_ss = ((%d)), EVM{A,B} = {%d, %d}, RX Rate =", pktinfo->rate_ss, rx_evm_ant0, rx_evm_ant1); + phydm_print_rate(dm, dm->rx_rate, DBG_ANT_DIV); + + + if (sat_tab->pkt_counter >= 1) /*packet skip count*/ + { + sat_tab->beam_set_rssi_avg_sum[sat_tab->fast_training_beam_num] += rssi_avg; + sat_tab->statistic_pkt_cnt[sat_tab->fast_training_beam_num]++; + + sat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][0] += rx_power_ant0; + sat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][1] += rx_power_ant1; + + if (pktinfo->rate_ss == 2) { + sat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][0] += rx_evm_ant0; + sat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][1] += rx_evm_ant1; + sat_tab->beam_path_evm_2ss_cnt[sat_tab->fast_training_beam_num]++; + } else { + sat_tab->beam_path_evm_1ss_sum[sat_tab->fast_training_beam_num] += rx_evm_ant0; + sat_tab->beam_path_evm_1ss_cnt[sat_tab->fast_training_beam_num]++; + } + } + + sat_tab->pkt_counter++; + + train_pkt_number = sat_tab->beam_set_train_cnt[sat_tab->fast_training_beam_num]; + + if (sat_tab->pkt_counter >= train_pkt_number) { + sat_tab->update_beam_idx++; + PHYDM_DBG(dm, DBG_ANT_DIV, "pre_beacon_counter = ((%d)), Update_new_beam = ((%d))\n", + sat_tab->pre_beacon_counter, sat_tab->update_beam_idx); + + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->pkt_counter = 0; + } + } + } + + if (sat_tab->update_beam_idx > 0) { + + sat_tab->update_beam_idx = 0; + + if (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) { + fat_tab->fat_state = FAT_DECISION_STATE; + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_fast_ant_training_hl_smart_antenna_type2(dm); /*go to make decision*/ + #else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem); + #endif + + + } else { + beam_tmp = sat_tab->fast_training_beam_num; + sat_tab->fast_training_beam_num++; + PHYDM_DBG(dm, DBG_ANT_DIV, "Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num); + phydm_set_rfu_beam_pattern_type2(dm); + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + + fat_tab->fat_state = FAT_TRAINING_STATE; + } + } + +} +#endif + +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) + +void +phydm_hl_smart_ant_type1_init_8821a( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 value32; + + PHYDM_DBG(dm, DBG_ANT_DIV, "***8821A SmartAnt_Init => ant_div_type=[Hong-Lin Smart ant Type1]\n"); + +#if 0 + /* ---------------------------------------- */ + /* GPIO 2-3 for Beam control */ + /* reg0x66[2]=0 */ + /* reg0x44[27:26] = 0 */ + /* reg0x44[23:16] enable_output for P_GPIO[7:0] */ + /* reg0x44[15:8] output_value for P_GPIO[7:0] */ + /* reg0x40[1:0] = 0 GPIO function */ + /* ------------------------------------------ */ +#endif + + /*GPIO setting*/ + odm_set_mac_reg(dm, 0x64, BIT(18), 0); + odm_set_mac_reg(dm, 0x44, BIT(27) | BIT(26), 0); + odm_set_mac_reg(dm, 0x44, BIT(19) | BIT(18), 0x3); /*enable_output for P_GPIO[3:2]*/ + /*odm_set_mac_reg(dm, 0x44, BIT(11)|BIT(10), 0);*/ /*output value*/ + odm_set_mac_reg(dm, 0x40, BIT(1) | BIT(0), 0); /*GPIO function*/ + + /*Hong_lin smart antenna HW setting*/ + sat_tab->rfu_codeword_total_bit_num = 24;/*max=32*/ + sat_tab->rfu_each_ant_bit_num = 4; + sat_tab->beam_patten_num_each_ant = 4; + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + sat_tab->latch_time = 100; /*mu sec*/ +#elif DEV_BUS_TYPE == RT_USB_INTERFACE + sat_tab->latch_time = 100; /*mu sec*/ +#endif + sat_tab->pkt_skip_statistic_en = 0; + + sat_tab->ant_num = 1;/*max=8*/ + sat_tab->ant_num_total = NUM_ANTENNA_8821A; + sat_tab->first_train_ant = MAIN_ANT; + + sat_tab->rfu_codeword_table[0] = 0x0; + sat_tab->rfu_codeword_table[1] = 0x4; + sat_tab->rfu_codeword_table[2] = 0x8; + sat_tab->rfu_codeword_table[3] = 0xc; + + sat_tab->rfu_codeword_table_5g[0] = 0x1; + sat_tab->rfu_codeword_table_5g[1] = 0x2; + sat_tab->rfu_codeword_table_5g[2] = 0x4; + sat_tab->rfu_codeword_table_5g[3] = 0x8; + + sat_tab->fix_beam_pattern_en = 0; + sat_tab->decision_holding_period = 0; + + /*beam training setting*/ + sat_tab->pkt_counter = 0; + sat_tab->per_beam_training_pkt_num = 10; + + /*set default beam*/ + sat_tab->fast_training_beam_num = 0; + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + phydm_set_all_ant_same_beam_num(dm); + + fat_tab->fat_state = FAT_BEFORE_LINK_STATE; + + odm_set_bb_reg(dm, 0xCA4, MASKDWORD, 0x01000100); + odm_set_bb_reg(dm, 0xCA8, MASKDWORD, 0x01000100); + + /*[BB] FAT setting*/ + odm_set_bb_reg(dm, 0xc08, BIT(18) | BIT(17) | BIT(16), sat_tab->ant_num); + odm_set_bb_reg(dm, 0xc08, BIT(31), 0); /*increase ant num every FAT period 0:+1, 1+2*/ + odm_set_bb_reg(dm, 0x8c4, BIT(2) | BIT(1), 1); /*change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/ + odm_set_bb_reg(dm, 0x8c4, BIT(0), 1); /*FAT_watchdog_en*/ + + value32 = odm_get_mac_reg(dm, 0x7B4, MASKDWORD); + odm_set_mac_reg(dm, 0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /*Reg7B4[16]=1 enable antenna training */ + /*Reg7B4[17]=1 enable match MAC addr*/ + odm_set_mac_reg(dm, 0x7b4, 0xFFFF, 0);/*Match MAC ADDR*/ + odm_set_mac_reg(dm, 0x7b0, MASKDWORD, 0); + +} + +u32 +phydm_construct_hl_beam_codeword( + void *dm_void, + u32 *beam_pattern_idx, + u32 ant_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 codeword = 0; + u32 data_tmp; + u32 i; + u32 break_counter = 0; + + if (ant_num < 8) { + for (i = 0; i < (sat_tab->ant_num_total); i++) { + /*PHYDM_DBG(dm,DBG_ANT_DIV, "beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] );*/ + if ((i < (sat_tab->first_train_ant - 1)) || (break_counter >= (sat_tab->ant_num))) { + data_tmp = 0; + /**/ + } else { + break_counter++; + + if (beam_pattern_idx[i] == 0) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[0]; + else + data_tmp = sat_tab->rfu_codeword_table[0]; + + } else if (beam_pattern_idx[i] == 1) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[1]; + else + data_tmp = sat_tab->rfu_codeword_table[1]; + + } else if (beam_pattern_idx[i] == 2) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[2]; + else + data_tmp = sat_tab->rfu_codeword_table[2]; + + } else if (beam_pattern_idx[i] == 3) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[3]; + else + data_tmp = sat_tab->rfu_codeword_table[3]; + } + } + + + codeword |= (data_tmp << (i * 4)); + + } + } + + return codeword; +} + +void +phydm_update_beam_pattern( + void *dm_void, + u32 codeword, + u32 codeword_length +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u8 i; + boolean beam_ctrl_signal; + u32 one = 0x1; + u32 reg44_tmp_p, reg44_tmp_n, reg44_ori; + u8 devide_num = 4; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Set Beam Pattern =0x%x\n", codeword); + + reg44_ori = odm_get_mac_reg(dm, 0x44, MASKDWORD); + reg44_tmp_p = reg44_ori; + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_ori =0x%x\n", reg44_ori);*/ + + devide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4; + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i); + + if (dm->debug_components & DBG_ANT_DIV) { + if (i == (codeword_length - 1)) { + pr_debug("%d ]\n", beam_ctrl_signal); + /**/ + } else if (i == 0) { + pr_debug("Send codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal); + /**/ + } else if ((i % devide_num) == (devide_num-1)) { + pr_debug("%d | ", beam_ctrl_signal); + /**/ + } else { + pr_debug("%d ", beam_ctrl_signal); + /**/ + } + } + + if (dm->support_ic_type == ODM_RTL8821) { + #if (RTL8821A_SUPPORT == 1) + reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*clean bit 10 & 11*/ + reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10)); + reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10))); + + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n);*/ + odm_set_mac_reg(dm, 0x44, MASKDWORD, reg44_tmp_p); + odm_set_mac_reg(dm, 0x44, MASKDWORD, reg44_tmp_n); + #endif + } + #if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) { + if (sat_tab->rfu_protocol_type == 2) { + reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*clean bit 8*/ + reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*get new clk high/low, exclusive-or*/ + + + reg44_tmp_p |= (beam_ctrl_signal << 8); + + odm_set_mac_reg(dm, 0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(10); + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/ + + } else { + reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*clean bit 9 & 8*/ + reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8)); + reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8))); + + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n); */ + odm_set_mac_reg(dm, 0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(10); + odm_set_mac_reg(dm, 0x44, MASKDWORD, reg44_tmp_n); + ODM_delay_us(10); + } + } + #endif + } +} + +void +phydm_update_rx_idle_beam( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 i; + + sat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm, + &sat_tab->rx_idle_beam[0], + sat_tab->ant_num); + PHYDM_DBG(dm, DBG_ANT_DIV, "Set target beam_pattern codeword = (( 0x%x ))\n", sat_tab->update_beam_codeword); + + for (i = 0; i < (sat_tab->ant_num); i++) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i, sat_tab->rx_idle_beam[i]); + /**/ + } + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); +#else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); + /*odm_stall_execution(1);*/ +#endif + + sat_tab->pre_codeword = sat_tab->update_beam_codeword; +} + +void +phydm_hl_smart_ant_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 used = *_used; + u32 out_len = *_out_len; + u32 one = 0x1; + u32 codeword_length = sat_tab->rfu_codeword_total_bit_num; + u32 beam_ctrl_signal, i; + u8 devide_num = 4; + + if (dm_value[0] == 1) { /*fix beam pattern*/ + + sat_tab->fix_beam_pattern_en = dm_value[1]; + + if (sat_tab->fix_beam_pattern_en == 1) { + sat_tab->fix_beam_pattern_codeword = dm_value[2]; + + if (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n", + sat_tab->fix_beam_pattern_codeword, codeword_length); + + (sat_tab->fix_beam_pattern_codeword) &= 0xffffff; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Auto modify to (0x%x)\n", sat_tab->fix_beam_pattern_codeword); + } + + sat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword; + + /*---------------------------------------------------------*/ + PDM_SNPF(out_len, used, output + used, + out_len - used, "Fix Beam Pattern\n"); + + devide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4; + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i); + + if (i == (codeword_length - 1)) { + PDM_SNPF(out_len, used, + output + used, + out_len - used, + "%d]\n", + beam_ctrl_signal); + /**/ + } else if (i == 0) { + PDM_SNPF(out_len, used, + output + used, + out_len - used, + "Send Codeword[1:24] to RFU -> [%d", + beam_ctrl_signal); + /**/ + } else if ((i % devide_num) == (devide_num-1)) { + PDM_SNPF(out_len, used, + output + used, + out_len - used, "%d|", + beam_ctrl_signal); + /**/ + } else { + PDM_SNPF(out_len, used, + output + used, + out_len - used, "%d", + beam_ctrl_signal); + /**/ + } + } + /*---------------------------------------------------------*/ + + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); +#else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); + /*odm_stall_execution(1);*/ +#endif + } else if (sat_tab->fix_beam_pattern_en == 0) + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Smart Antenna: Enable\n"); + + } else if (dm_value[0] == 2) { /*set latch time*/ + + sat_tab->latch_time = dm_value[1]; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] latch_time =0x%x\n", sat_tab->latch_time); + } else if (dm_value[0] == 3) { + sat_tab->fix_training_num_en = dm_value[1]; + + if (sat_tab->fix_training_num_en == 1) { + sat_tab->per_beam_training_pkt_num = (u8)dm_value[2]; + sat_tab->decision_holding_period = (u8)dm_value[3]; + + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", + sat_tab->fix_training_num_en, + sat_tab->per_beam_training_pkt_num, + sat_tab->decision_holding_period); + + } else if (sat_tab->fix_training_num_en == 0) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] AUTO per_beam_training_pkt_num\n"); + /**/ + } + } else if (dm_value[0] == 4) { + if (dm_value[1] == 1) { + sat_tab->ant_num = 1; + sat_tab->first_train_ant = MAIN_ANT; + + } else if (dm_value[1] == 2) { + sat_tab->ant_num = 1; + sat_tab->first_train_ant = AUX_ANT; + + } else if (dm_value[1] == 3) { + sat_tab->ant_num = 2; + sat_tab->first_train_ant = MAIN_ANT; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Set ant Num = (( %d )), first_train_ant = (( %d ))\n", + sat_tab->ant_num, + (sat_tab->first_train_ant - 1)); + } else if (dm_value[0] == 5) { + if (dm_value[1] <= 3) { + sat_tab->rfu_codeword_table[dm_value[1]] = dm_value[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", + dm_value[1], dm_value[2]); + } else { + for (i = 0; i < 4; i++) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", + i, + sat_tab->rfu_codeword_table[i]); + } + } + } else if (dm_value[0] == 6) { + if (dm_value[1] <= 3) { + sat_tab->rfu_codeword_table_5g[dm_value[1]] = dm_value[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", + dm_value[1], dm_value[2]); + } else { + for (i = 0; i < 4; i++) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", + i, + sat_tab->rfu_codeword_table_5g[i]); + } + } + } else if (dm_value[0] == 7) { + if (dm_value[1] <= 4) { + sat_tab->beam_patten_num_each_ant = dm_value[1]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Set Beam number = (( %d ))\n", + sat_tab->beam_patten_num_each_ant); + } else { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Show Beam number = (( %d ))\n", + sat_tab->beam_patten_num_each_ant); + } + } + *_used = used; + *_out_len = out_len; +} + + +void +phydm_set_all_ant_same_beam_num( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { /*2ant for 8821A*/ + + sat_tab->rx_idle_beam[0] = sat_tab->fast_training_beam_num; + sat_tab->rx_idle_beam[1] = sat_tab->fast_training_beam_num; + } + + sat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm, + &sat_tab->rx_idle_beam[0], + sat_tab->ant_num); + + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n", sat_tab->update_beam_codeword); + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); +#else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); + /*odm_stall_execution(1);*/ +#endif +} + +void +odm_fast_ant_training_hl_smart_antenna_type1( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + u32 codeword = 0, i, j; + u32 target_ant; + u32 avg_rssi_tmp, avg_rssi_tmp_ma; + u32 target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0}; + u32 max_beam_ant_rssi = 0; + u32 target_ant_beam[SUPPORT_RF_PATH_NUM] = {0}; + u32 beam_tmp; + u8 next_ant; + u32 rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u32 rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u32 rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u8 per_beam_rssi_diff_tmp = 0, training_pkt_num_offset; + u32 break_counter = 0; + u32 used_ant; + + + if (!dm->is_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); + + if (fat_tab->is_become_linked == true) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Link->no Link\n"); + fat_tab->fat_state = FAT_BEFORE_LINK_STATE; + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + PHYDM_DBG(dm, DBG_ANT_DIV, "change to (( %d )) FAT_state\n", fat_tab->fat_state); + + fat_tab->is_become_linked = dm->is_linked; + } + return; + + } else { + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n"); + + fat_tab->fat_state = FAT_PREPARE_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "change to (( %d )) FAT_state\n", fat_tab->fat_state); + + /*sat_tab->fast_training_beam_num = 0;*/ + /*phydm_set_all_ant_same_beam_num(dm);*/ + + fat_tab->is_become_linked = dm->is_linked; + } + } + + if (*fat_tab->p_force_tx_ant_by_desc == false) { + if (dm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + else + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + } + + /*PHYDM_DBG(dm, DBG_ANT_DIV, "HL Smart ant Training: state (( %d ))\n", fat_tab->fat_state);*/ + + /* [DECISION STATE] */ + /*=======================================================================================*/ + if (fat_tab->fat_state == FAT_DECISION_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 3. In Decision state]\n"); + phydm_fast_training_enable(dm, FAT_OFF); + + break_counter = 0; + /*compute target beam in each antenna*/ + for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) { + for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) { + if (sat_tab->pkt_rssi_cnt[i][j] == 0) { + avg_rssi_tmp = sat_tab->pkt_rssi_pre[i][j]; + avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; + avg_rssi_tmp_ma = avg_rssi_tmp; + } else { + avg_rssi_tmp = (sat_tab->pkt_rssi_sum[i][j]) / (sat_tab->pkt_rssi_cnt[i][j]); + avg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->pkt_rssi_pre[i][j]) >> 1; + } + + rssi_sorting_seq[j] = avg_rssi_tmp; + sat_tab->pkt_rssi_pre[i][j] = avg_rssi_tmp; + + PHYDM_DBG(dm, DBG_ANT_DIV, "ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n", + i, j, sat_tab->pkt_rssi_cnt[i][j], avg_rssi_tmp_ma, avg_rssi_tmp); + + if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) { + target_ant_beam[i] = j; + target_ant_beam_max_rssi[i] = avg_rssi_tmp; + } + + /*reset counter value*/ + sat_tab->pkt_rssi_sum[i][j] = 0; + sat_tab->pkt_rssi_cnt[i][j] = 0; + + } + sat_tab->rx_idle_beam[i] = target_ant_beam[i]; + PHYDM_DBG(dm, DBG_ANT_DIV, "---------> Target of ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n", + i, target_ant_beam[i], target_ant_beam_max_rssi[i]); + + /*sorting*/ + /* + PHYDM_DBG(dm, DBG_ANT_DIV, "[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]); + */ + + /*phydm_seq_sorting(dm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/ + + /* + PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rank_idx_seq = [%d, %d, %d, %d]\n", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3]); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rank_idx_out = [%d, %d, %d, %d]\n", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3]); + */ + + if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) { + target_ant = i; + max_beam_ant_rssi = target_ant_beam_max_rssi[i]; + /*PHYDM_DBG(dm, DBG_ANT_DIV, "Target of ant = (( %d )) max_beam_ant_rssi = (( %d ))\n", + target_ant, max_beam_ant_rssi);*/ + } + break_counter++; + if (break_counter >= (sat_tab->ant_num)) + break; + } + +#ifdef CONFIG_FAT_PATCH + break_counter = 0; + for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) { + for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) { + per_beam_rssi_diff_tmp = (u8)(max_beam_ant_rssi - sat_tab->pkt_rssi_pre[i][j]); + sat_tab->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp; + + PHYDM_DBG(dm, DBG_ANT_DIV, "ant[%d], Beam[%d]: RSSI_diff= ((%d))\n", + i, j, per_beam_rssi_diff_tmp); + } + break_counter++; + if (break_counter >= (sat_tab->ant_num)) + break; + } +#endif + + if (target_ant == 0) + target_ant = MAIN_ANT; + else if (target_ant == 1) + target_ant = AUX_ANT; + + if (sat_tab->ant_num > 1) { + /* [ update RX ant ]*/ + odm_update_rx_idle_ant(dm, (u8)target_ant); + + /* [ update TX ant ]*/ + odm_update_tx_ant(dm, (u8)target_ant, (fat_tab->train_idx)); + } + + /*set beam in each antenna*/ + phydm_update_rx_idle_beam(dm); + + odm_ant_div_on_off(dm, ANTDIV_ON); + fat_tab->fat_state = FAT_PREPARE_STATE; + return; + + } + /* [TRAINING STATE] */ + else if (fat_tab->fat_state == FAT_TRAINING_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2. In Training state]\n"); + + PHYDM_DBG(dm, DBG_ANT_DIV, "fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n", + sat_tab->fast_training_beam_num, sat_tab->pre_fast_training_beam_num); + + if (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num) + + sat_tab->force_update_beam_en = 0; + + else { + sat_tab->force_update_beam_en = 1; + + sat_tab->pkt_counter = 0; + beam_tmp = sat_tab->fast_training_beam_num; + if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", sat_tab->fast_training_beam_num); + fat_tab->fat_state = FAT_DECISION_STATE; + odm_fast_ant_training_hl_smart_antenna_type1(dm); + + } else { + sat_tab->fast_training_beam_num++; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num); + phydm_set_all_ant_same_beam_num(dm); + fat_tab->fat_state = FAT_TRAINING_STATE; + + } + } + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + PHYDM_DBG(dm, DBG_ANT_DIV, "[prepare state] Update Pre_Beam =(( %d ))\n", sat_tab->pre_fast_training_beam_num); + } + /* [Prepare state] */ + /*=======================================================================================*/ + else if (fat_tab->fat_state == FAT_PREPARE_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "\n\n[ 1. In Prepare state]\n"); + + if (dm->pre_traffic_load == (dm->traffic_load)) { + if (sat_tab->decision_holding_period != 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Holding_period = (( %d )), return!!!\n", sat_tab->decision_holding_period); + sat_tab->decision_holding_period--; + return; + } + } + + + /* Set training packet number*/ + if (sat_tab->fix_training_num_en == 0) { + switch (dm->traffic_load) { + case TRAFFIC_HIGH: + sat_tab->per_beam_training_pkt_num = 8; + sat_tab->decision_holding_period = 2; + break; + case TRAFFIC_MID: + sat_tab->per_beam_training_pkt_num = 6; + sat_tab->decision_holding_period = 3; + break; + case TRAFFIC_LOW: + sat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/ + sat_tab->decision_holding_period = 4; + break; + case TRAFFIC_ULTRA_LOW: + sat_tab->per_beam_training_pkt_num = 1; + sat_tab->decision_holding_period = 6; + break; + default: + break; + } + } + PHYDM_DBG(dm, DBG_ANT_DIV, "Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\n", + sat_tab->fix_training_num_en, sat_tab->per_beam_training_pkt_num, sat_tab->decision_holding_period); + + +#ifdef CONFIG_FAT_PATCH + break_counter = 0; + for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) { + for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) { + per_beam_rssi_diff_tmp = sat_tab->beam_train_rssi_diff[i][j]; + training_pkt_num_offset = per_beam_rssi_diff_tmp; + + if ((sat_tab->per_beam_training_pkt_num) > training_pkt_num_offset) + sat_tab->beam_train_cnt[i][j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset; + else + sat_tab->beam_train_cnt[i][j] = 1; + + + PHYDM_DBG(dm, DBG_ANT_DIV, "ant[%d]: Beam_num-(( %d )) training_pkt_num = ((%d))\n", + i, j, sat_tab->beam_train_cnt[i][j]); + } + break_counter++; + if (break_counter >= (sat_tab->ant_num)) + break; + } + + + phydm_fast_training_enable(dm, FAT_OFF); + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->update_beam_idx = 0; + + if (*dm->band_type == ODM_BAND_5G) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Set 5G ant\n"); + /*used_ant = (sat_tab->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/ + used_ant = sat_tab->first_train_ant; + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, "Set 2.4G ant\n"); + used_ant = sat_tab->first_train_ant; + } + + odm_update_rx_idle_ant(dm, (u8)used_ant); + +#else + /* Set training MAC addr. of target */ + odm_set_next_mac_addr_target(dm); + phydm_fast_training_enable(dm, FAT_ON); +#endif + + odm_ant_div_on_off(dm, ANTDIV_OFF); + sat_tab->pkt_counter = 0; + sat_tab->fast_training_beam_num = 0; + phydm_set_all_ant_same_beam_num(dm); + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + fat_tab->fat_state = FAT_TRAINING_STATE; + } + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void +phydm_beam_switch_workitem_callback( + void *context +) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE + sat_tab->pkt_skip_statistic_en = 1; +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", sat_tab->pkt_skip_statistic_en); + + phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE + /*odm_stall_execution(sat_tab->latch_time);*/ + sat_tab->pkt_skip_statistic_en = 0; +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, "pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", sat_tab->pkt_skip_statistic_en, sat_tab->latch_time); +} + +void +phydm_beam_decision_workitem_callback( + void *context +) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Beam decision Workitem Callback\n"); + odm_fast_ant_training_hl_smart_antenna_type1(dm); +} +#endif + + +#endif /*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ + + +#endif/*#ifdef CONFIG_HL_SMART_ANTENNA*/ + + + +void +phydm_smt_ant_config( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + + #if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) + + dm->support_ability |= ODM_BB_SMT_ANT; + smtant_table->smt_ant_vendor = SMTANT_CUMITEK; + smtant_table->smt_ant_type = 1; + #if (RTL8822B_SUPPORT == 1) + dm->rfe_type = SMTANT_TMP_RFE_TYPE; + #endif + #elif (defined(CONFIG_HL_SMART_ANTENNA)) + + dm->support_ability |= ODM_BB_SMT_ANT; + smtant_table->smt_ant_vendor = SMTANT_HON_BO; + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + smtant_table->smt_ant_type = 1; + #endif + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + smtant_table->smt_ant_type = 2; + #endif + #endif + + PHYDM_DBG(dm, DBG_SMT_ANT, "[SmtAnt Config] Vendor=((%d)), Smt_ant_type =((%d))\n", + smtant_table->smt_ant_vendor, smtant_table->smt_ant_type); +} +#endif + + +void +phydm_smt_ant_init( + void *dm_void +) +{ +#if (defined(CONFIG_SMART_ANTENNA)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + + phydm_smt_ant_config(dm); + + + if (smtant_table->smt_ant_vendor == SMTANT_CUMITEK) { + + #if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) + #if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + phydm_cumitek_smt_ant_init_8822b(dm); + /**/ + } + #endif + + #if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F) { + phydm_cumitek_smt_ant_init_8197f(dm); + /**/ + } + #endif + #endif /*#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))*/ + + } else if (smtant_table->smt_ant_vendor == SMTANT_HON_BO) { + #if (defined(CONFIG_HL_SMART_ANTENNA)) + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + if (dm->support_ic_type == ODM_RTL8821) { + phydm_hl_smart_ant_type1_init_8821a(dm); + /**/ + } + #endif + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + if (dm->support_ic_type == ODM_RTL8822B) { + phydm_hl_smart_ant_type2_init_8822b(dm); + /**/ + } + #endif + #endif/*#if (defined(CONFIG_HL_SMART_ANTENNA))*/ + } +#endif +} + + diff --git a/hal/phydm/phydm_smt_ant.h b/hal/phydm/phydm_smt_ant.h new file mode 100644 index 0000000..d2f88e1 --- /dev/null +++ b/hal/phydm/phydm_smt_ant.h @@ -0,0 +1,249 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMSMTANT_H__ +#define __PHYDMSMTANT_H__ + +/*#define SMT_ANT_VERSION "1.1"*/ /*2017.03.13*/ +/*#define SMT_ANT_VERSION "1.2"*/ /*2017.03.28*/ +#define SMT_ANT_VERSION "2.0" /* Add Cumitek SmtAnt 2017.05.25*/ + +#define SMTANT_RTK 1 +#define SMTANT_HON_BO 2 +#define SMTANT_CUMITEK 3 + +#if (defined(CONFIG_SMART_ANTENNA)) + + +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) +struct smt_ant_cumitek { + u8 tx_ant_idx[2][ODM_ASSOCIATE_ENTRY_NUM]; /*[pathA~B] [MACID 0~128]*/ + u8 rx_default_ant_idx[2]; /*[pathA~B]*/ +}; +#endif + +#if (defined(CONFIG_HL_SMART_ANTENNA)) +struct smt_ant_honbo { + u32 latch_time; + boolean pkt_skip_statistic_en; + u32 fix_beam_pattern_en; + u32 fix_training_num_en; + u32 fix_beam_pattern_codeword; + u32 update_beam_codeword; + u32 ant_num; /*number of "used" smart beam antenna*/ + u32 ant_num_total;/*number of "total" smart beam antenna*/ + u32 first_train_ant; /*decide witch antenna to train first*/ + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + u32 pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];/*rssi of each path with a certain beam pattern*/ + u8 beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u8 beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u32 rfu_codeword_table[4]; /*2G beam truth table*/ + u32 rfu_codeword_table_5g[4]; /*5G beam truth table*/ + u32 beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/ + u32 rx_idle_beam[SUPPORT_RF_PATH_NUM]; + u32 pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM]; + u32 pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM]; + #endif + + u32 fast_training_beam_num;/*current training beam_set index*/ + u32 pre_fast_training_beam_num;/*pre training beam_set index*/ + u32 rfu_codeword_total_bit_num; /* total bit number of RFU protocol*/ + u32 rfu_each_ant_bit_num; /* bit number of RFU protocol for each ant*/ + u8 per_beam_training_pkt_num; + u8 decision_holding_period; + + + u32 pre_codeword; + boolean force_update_beam_en; + u32 beacon_counter; + u32 pre_beacon_counter; + u8 pkt_counter; /*packet number that each beam-set should be colected in training state*/ + u8 update_beam_idx; /*the index announce that the beam can be updated*/ + u8 rfu_protocol_type; + u16 rfu_protocol_delay_time; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_WORK_ITEM hl_smart_antenna_workitem; + RT_WORK_ITEM hl_smart_antenna_decision_workitem; + #endif + + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + u8 beam_set_avg_rssi_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; /*avg pre_rssi of each beam set*/ + u8 beam_set_train_val_diff[SUPPORT_BEAM_SET_PATTERN_NUM]; /*rssi of a beam pattern set, ex: a set = {ant1_beam=1, ant2_beam=3}*/ + u8 beam_set_train_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*training pkt num of each beam set*/ + u32 beam_set_rssi_avg_sum[SUPPORT_BEAM_SET_PATTERN_NUM]; /*RSSI_sum of avg(pathA,pathB) for each beam-set)*/ + u32 beam_path_rssi_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*RSSI_sum of each path for each beam-set)*/ + + u8 beam_set_avg_evm_2ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; + u32 beam_path_evm_2ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*2SS evm_sum of each path for each beam-set)*/ + u32 beam_path_evm_2ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; + + u8 beam_set_avg_evm_1ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; + u32 beam_path_evm_1ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM];/*1SS evm_sum of each path for each beam-set)*/ + u32 beam_path_evm_1ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; + + u32 statistic_pkt_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*statistic_pkt_cnt for SmtAnt make decision*/ + + u8 total_beam_set_num; /*number of beam set can be switched*/ + u8 total_beam_set_num_2g;/*number of beam set can be switched in 2G*/ + u8 total_beam_set_num_5g;/*number of beam set can be switched in 5G*/ + + u8 rfu_codeword_table_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*2G beam truth table*/ + u8 rfu_codeword_table_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*5G beam truth table*/ + u8 rx_idle_beam_set_idx; /*the filanl decsion result*/ + #endif + + +}; +#endif /*#if (defined(CONFIG_HL_SMART_ANTENNA))*/ + +struct smt_ant { + u8 smt_ant_vendor; + u8 smt_ant_type; + u8 tx_desc_mode; /*0:3 bit mode, 1:2 bit mode*/ + #if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) + struct smt_ant_cumitek cumi_smtant_table; + #endif +}; + +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) +void +phydm_cumitek_smt_tx_ant_update( + void *dm_void, + u8 tx_ant_idx_path_a, + u8 tx_ant_idx_path_b, + u32 mac_id +); + +void +phydm_cumitek_smt_rx_default_ant_update( + void *dm_void, + u8 rx_ant_idx_path_a, + u8 rx_ant_idx_path_b +); + +void +phydm_cumitek_smt_ant_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); + +#endif + + +#if (defined(CONFIG_HL_SMART_ANTENNA)) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void +phydm_beam_switch_workitem_callback( + void *context +); + +void +phydm_beam_decision_workitem_callback( + void *context +); +#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + + + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 +void +phydm_hl_smart_ant_type2_init_8822b( + void *dm_void +); + +void +phydm_update_beam_pattern_type2( + void *dm_void, + u32 codeword, + u32 codeword_length +); + +void +phydm_set_rfu_beam_pattern_type2( + void *dm_void +); + +void +phydm_hl_smart_ant_debug_type2( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); + +void +phydm_process_rssi_for_hb_smtant_type2( + void *dm_void, + void *phy_info_void, + void *pkt_info_void, + u8 rssi_avg +); + +#endif/*#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))*/ + + +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) + +void +phydm_update_beam_pattern( + void *dm_void, + u32 codeword, + u32 codeword_length +); + +void +phydm_set_all_ant_same_beam_num( + void *dm_void +); + +void +phydm_hl_smart_ant_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); + +#endif/*#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))*/ +#endif/*#if (defined(CONFIG_HL_SMART_ANTENNA))*/ +#endif/*#if (defined(CONFIG_SMART_ANTENNA))*/ + +void +phydm_smt_ant_init( + void *dm_void +); + +#endif \ No newline at end of file diff --git a/hal/phydm/phydm_soml.c b/hal/phydm/phydm_soml.c new file mode 100644 index 0000000..d4706ec --- /dev/null +++ b/hal/phydm/phydm_soml.c @@ -0,0 +1,862 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void +phydm_dynamicsoftmletting( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 ret_val; + +#if (RTL8822B_SUPPORT == 1) + if (*dm->mp_mode == false) { + if (dm->support_ic_type & ODM_RTL8822B) { + if ((!dm->is_linked)|(dm->iot_table.is_linked_cmw500)) + return; + + if (true == dm->bsomlenabled) { + PHYDM_DBG(dm, ODM_COMP_API, "PHYDM_DynamicSoftMLSetting(): SoML has been enable, skip dynamic SoML switch\n"); + return; + } + + ret_val = odm_get_bb_reg(dm, 0xf8c, MASKBYTE0); + PHYDM_DBG(dm, ODM_COMP_API, "PHYDM_DynamicSoftMLSetting(): Read 0xF8C = 0x%08X\n", ret_val); + + if (ret_val < 0x16) { + PHYDM_DBG(dm, ODM_COMP_API, "PHYDM_DynamicSoftMLSetting(): 0xF8C(== 0x%08X) < 0x16, enable SoML\n", ret_val); + phydm_somlrxhp_setting(dm, true); + /*odm_set_bb_reg(dm, 0x19a8, MASKDWORD, 0xc10a0000);*/ + dm->bsomlenabled = true; + } + } + } +#endif + +} + +#ifdef CONFIG_ADAPTIVE_SOML +void +phydm_soml_on_off( + void *dm_void, + u8 swch +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + if (swch == SOML_ON) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "(( Turn on )) SOML\n"); + + if (dm->support_ic_type == ODM_RTL8822B) + phydm_somlrxhp_setting(dm, true); + else if (dm->support_ic_type == ODM_RTL8197F) + odm_set_bb_reg(dm, 0x998, BIT(6), swch); + + } else if (swch == SOML_OFF) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "(( Turn off )) SOML\n"); + + if (dm->support_ic_type == ODM_RTL8822B) + phydm_somlrxhp_setting(dm, false); + else if (dm->support_ic_type == ODM_RTL8197F) + odm_set_bb_reg(dm, 0x998, BIT(6), swch); + } + dm_soml_table->soml_on_off = swch; +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void +phydm_adaptive_soml_callback( + struct phydm_timer_list *timer +) +{ + void *adapter = (void *)timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +#if USE_WORKITEM + odm_schedule_work_item(&dm_soml_table->phydm_adaptive_soml_workitem); +#else + { + /*dbg_print("phydm_adaptive_soml-phydm_adaptive_soml_callback\n");*/ + phydm_adsl(dm); + } +#endif +#else + odm_schedule_work_item(&dm_soml_table->phydm_adaptive_soml_workitem); +#endif +} + +void +phydm_adaptive_soml_workitem_callback( + void *context +) +{ +#ifdef CONFIG_ADAPTIVE_SOML + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + /*dbg_print("phydm_adaptive_soml-phydm_adaptive_soml_workitem_callback\n");*/ + phydm_adsl(dm); +#endif +} + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void +phydm_adaptive_soml_callback( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *padapter = dm->adapter; + if (*(dm->is_net_closed) == true) + return; + if (dm->support_interface == ODM_ITRF_PCIE) + phydm_adsl(dm); + else { + /* Can't do I/O in timer callback*/ + rtw_run_in_thread_cmd(padapter, phydm_adaptive_soml_workitem_callback, padapter); + } +} + +void +phydm_adaptive_soml_workitem_callback( + void *context +) +{ + void * adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->odmpriv; + + /*dbg_print("phydm_adaptive_soml-phydm_adaptive_soml_workitem_callback\n");*/ + phydm_adsl(dm); +} + +#else + +void +phydm_adaptive_soml_callback( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "******SOML_Callback******\n"); + phydm_adsl(dm); + +} +#endif + +void +phydm_rx_qam_for_soml( + void *dm_void, + void *pkt_info_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + u8 date_rate = (pktinfo->data_rate & 0x7f); + + if (dm_soml_table->soml_state_cnt < ((dm_soml_table->soml_train_num)<<1)) { + if (dm_soml_table->soml_on_off == SOML_ON) + return; + else if (dm_soml_table->soml_on_off == SOML_OFF) { + if ((date_rate >= ODM_RATEMCS8) && (date_rate <= ODM_RATEMCS10)) + dm_soml_table->num_ht_qam[BPSK_QPSK]++; + + else if ((date_rate >= ODM_RATEMCS11) && (date_rate <= ODM_RATEMCS12)) + dm_soml_table->num_ht_qam[QAM16]++; + + else if ((date_rate >= ODM_RATEMCS13) && (date_rate <= ODM_RATEMCS15)) + dm_soml_table->num_ht_qam[QAM64]++; + + else if ((date_rate >= ODM_RATEVHTSS2MCS0) && (date_rate <= ODM_RATEVHTSS2MCS2)) + dm_soml_table->num_vht_qam[BPSK_QPSK]++; + + else if ((date_rate >= ODM_RATEVHTSS2MCS3) && (date_rate <= ODM_RATEVHTSS2MCS4)) + dm_soml_table->num_vht_qam[QAM16]++; + + else if ((date_rate >= ODM_RATEVHTSS2MCS5) && (date_rate <= ODM_RATEVHTSS2MCS5)) + dm_soml_table->num_vht_qam[QAM64]++; + + else if ((date_rate >= ODM_RATEVHTSS2MCS8) && (date_rate <= ODM_RATEVHTSS2MCS9)) + dm_soml_table->num_vht_qam[QAM256]++; + } + } +} + +void +phydm_soml_reset_rx_rate( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + u8 order; + + for (order = 0; order < HT_ORDER_TYPE; order++) + dm_soml_table->num_ht_qam[order] = 0; + + for (order = 0; order < VHT_ORDER_TYPE; order++) + dm_soml_table->num_vht_qam[order] = 0; +} + +void +phydm_soml_cfo_process( + void *dm_void, + s32 *diff_a, + s32 *diff_b +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + u32 value32, value32_1, value32_2, value32_3; + s32 cfo_acq_a, cfo_acq_b, cfo_end_a, cfo_end_b; + s32 cfo_diff_a, cfo_diff_b; + + value32 = odm_get_bb_reg(dm, 0xd10, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, 0xd14, MASKDWORD); + value32_2 = odm_get_bb_reg(dm, 0xd50, MASKDWORD); + value32_3 = odm_get_bb_reg(dm, 0xd54, MASKDWORD); + + cfo_acq_a = (s32)((value32 & 0x1fff0000) >> 16); + cfo_end_a = (s32)((value32_1 & 0x1fff0000) >> 16); + cfo_acq_b = (s32)((value32_2 & 0x1fff0000) >> 16); + cfo_end_b = (s32)((value32_3 & 0x1fff0000) >> 16); + + *diff_a = ((cfo_acq_a >= cfo_end_a) ? (cfo_acq_a - cfo_end_a) : (cfo_end_a - cfo_acq_a)); + *diff_b = ((cfo_acq_b >= cfo_end_b) ? (cfo_acq_b - cfo_end_b) : (cfo_end_b - cfo_acq_b)); + + *diff_a = ((*diff_a * 312) + (*diff_a >> 1)) >> 12; /* 312.5/2^12 */ + *diff_b = ((*diff_b * 312) + (*diff_b >> 1)) >> 12; /* 312.5/2^12 */ + +} + +void +phydm_soml_debug( + void *dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + u32 used = *_used; + u32 out_len = *_out_len; + + if (dm_value[0] == 1) { /*Turn on/off SOML*/ + dm_soml_table->soml_select = (u8)dm_value[1]; + + } else if (dm_value[0] == 2) { /*training number for SOML*/ + + dm_soml_table->soml_train_num = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_train_num = ((%d))\n", + dm_soml_table->soml_train_num); + } else if (dm_value[0] == 3) { /*training interval for SOML*/ + + dm_soml_table->soml_intvl = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_intvl = ((%d))\n", + dm_soml_table->soml_intvl); + } else if (dm_value[0] == 4) { /*function period for SOML*/ + + dm_soml_table->soml_period = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_period = ((%d))\n", + dm_soml_table->soml_period); + } else if (dm_value[0] == 5) { /*delay_time for SOML*/ + + dm_soml_table->soml_delay_time = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_delay_time = ((%d))\n", + dm_soml_table->soml_delay_time); + } else if (dm_value[0] == 6) { /* for SOML Rx QAM distribution th*/ + if (dm_value[1] == 256) { + dm_soml_table->qam256_dist_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "qam256_dist_th = ((%d))\n", + dm_soml_table->qam256_dist_th); + } else if (dm_value[1] == 64) { + dm_soml_table->qam64_dist_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "qam64_dist_th = ((%d))\n", + dm_soml_table->qam64_dist_th); + } else if (dm_value[1] == 16) { + dm_soml_table->qam16_dist_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "qam16_dist_th = ((%d))\n", + dm_soml_table->qam16_dist_th); + } else if (dm_value[1] == 4) { + dm_soml_table->bpsk_qpsk_dist_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "bpsk_qpsk_dist_th = ((%d))\n", + dm_soml_table->bpsk_qpsk_dist_th); + } + } else if (dm_value[0] == 7) { /* for SOML cfo th*/ + if (dm_value[1] == 256) { + dm_soml_table->cfo_qam256_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "cfo_qam256_th = ((%d KHz))\n", + dm_soml_table->cfo_qam256_th); + } else if (dm_value[1] == 64) { + dm_soml_table->cfo_qam64_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "cfo_qam64_th = ((%d KHz))\n", + dm_soml_table->cfo_qam64_th); + } else if (dm_value[1] == 16) { + dm_soml_table->cfo_qam16_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "cfo_qam16_th = ((%d KHz))\n", + dm_soml_table->cfo_qam16_th); + } else if (dm_value[1] == 4) { + dm_soml_table->cfo_qpsk_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "cfo_qpsk_th = ((%d KHz))\n", + dm_soml_table->cfo_qpsk_th); + } + } else if (dm_value[0] == 100) { /*show parameters*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_select = ((%d))\n", + dm_soml_table->soml_select); + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_train_num = ((%d))\n", + dm_soml_table->soml_train_num); + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_intvl = ((%d))\n", + dm_soml_table->soml_intvl); + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_period = ((%d))\n", + dm_soml_table->soml_period); + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_delay_time = ((%d))\n\n", + dm_soml_table->soml_delay_time); + PDM_SNPF(out_len, used, output + used, out_len - used, + "qam256_dist_th = ((%d)), qam64_dist_th = ((%d)), ", + dm_soml_table->qam256_dist_th, + dm_soml_table->qam64_dist_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "qam16_dist_th = ((%d)), bpsk_qpsk_dist_th = ((%d))\n", + dm_soml_table->qam16_dist_th, + dm_soml_table->bpsk_qpsk_dist_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qam256_th = ((%d KHz)), cfo_qam64_th = ((%d KHz)), ", + dm_soml_table->cfo_qam256_th, + dm_soml_table->cfo_qam64_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qam16_th = ((%d KHz)), cfo_qpsk_th = ((%d KHz))\n", + dm_soml_table->cfo_qam16_th, + dm_soml_table->cfo_qpsk_th); + } + *_used = used; + *_out_len = out_len; +} + +void +phydm_soml_statistics( + void *dm_void, + u8 on_off_state + +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + u8 i; + u32 num_bytes_diff; + + if (dm->support_ic_type == ODM_RTL8197F) { + if (on_off_state == SOML_ON) { + for (i = 0; i < HT_RATE_IDX; i++) { + num_bytes_diff = dm_soml_table->num_ht_bytes[i] - dm_soml_table->pre_num_ht_bytes[i]; + dm_soml_table->num_ht_bytes_on[i] += num_bytes_diff; + dm_soml_table->pre_num_ht_bytes[i] = dm_soml_table->num_ht_bytes[i]; + } + } else if (on_off_state == SOML_OFF) { + for (i = 0; i < HT_RATE_IDX; i++) { + num_bytes_diff = dm_soml_table->num_ht_bytes[i] - dm_soml_table->pre_num_ht_bytes[i]; + dm_soml_table->num_ht_bytes_off[i] += num_bytes_diff; + dm_soml_table->pre_num_ht_bytes[i] = dm_soml_table->num_ht_bytes[i]; + } + } + } else if (dm->support_ic_type == ODM_RTL8822B) { + if (on_off_state == SOML_ON) { + for (i = 0; i < VHT_RATE_IDX; i++) { + num_bytes_diff = dm_soml_table->num_vht_bytes[i] - dm_soml_table->pre_num_vht_bytes[i]; + dm_soml_table->num_vht_bytes_on[i] += num_bytes_diff; + dm_soml_table->pre_num_vht_bytes[i] = dm_soml_table->num_vht_bytes[i]; + } + } else if (on_off_state == SOML_OFF) { + for (i = 0; i < VHT_RATE_IDX; i++) { + num_bytes_diff = dm_soml_table->num_vht_bytes[i] - dm_soml_table->pre_num_vht_bytes[i]; + dm_soml_table->num_vht_bytes_off[i] += num_bytes_diff; + dm_soml_table->pre_num_vht_bytes[i] = dm_soml_table->num_vht_bytes[i]; + } + } + } +} + +void +phydm_adsl( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + u8 i; + u8 next_on_off; + u8 rate_num = 1, rate_ss_shift = 0; + u32 byte_total_on = 0, byte_total_off = 0, num_total_qam = 0; + u32 ht_reset[HT_RATE_IDX] = {0}, vht_reset[VHT_RATE_IDX] = {0}; + u8 size = sizeof(ht_reset[0]); + + if (dm->support_ic_type & ODM_IC_4SS) + rate_num = 4; + else if (dm->support_ic_type & ODM_IC_3SS) + rate_num = 3; + else if (dm->support_ic_type & ODM_IC_2SS) + rate_num = 2; + + if ((dm->support_ic_type & ODM_ADAPTIVE_SOML_SUPPORT_IC)) { + if (TRUE) { + if ((dm->rssi_min >= SOML_RSSI_TH_HIGH) || (dm_soml_table->is_soml_method_enable == 1)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "> TH_H || is_soml_method_enable==1\n"); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "soml_state_cnt =((%d)), soml_on_off =((%s))\n", dm_soml_table->soml_state_cnt, (dm_soml_table->soml_on_off == SOML_ON) ? "SOML_ON" : "SOML_OFF"); + /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/ + if (dm_soml_table->soml_state_cnt < ((dm_soml_table->soml_train_num)<<1)) { + if (dm_soml_table->soml_state_cnt == 0) { + if (dm->support_ic_type == ODM_RTL8197F) { + odm_move_memory(dm, dm_soml_table->num_ht_bytes, ht_reset, HT_RATE_IDX*size); + odm_move_memory(dm, dm_soml_table->num_ht_bytes_on, ht_reset, HT_RATE_IDX*size); + odm_move_memory(dm, dm_soml_table->num_ht_bytes_off, ht_reset, HT_RATE_IDX*size); + } else if (dm->support_ic_type == ODM_RTL8822B) { + odm_move_memory(dm, dm_soml_table->num_vht_bytes, vht_reset, VHT_RATE_IDX*size); + odm_move_memory(dm, dm_soml_table->num_vht_bytes_on, vht_reset, VHT_RATE_IDX*size); + odm_move_memory(dm, dm_soml_table->num_vht_bytes_off, vht_reset, VHT_RATE_IDX*size); + dm_soml_table->cfo_counter++; + phydm_soml_cfo_process(dm, + &dm_soml_table->cfo_diff_a, + &dm_soml_table->cfo_diff_b); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n", dm_soml_table->cfo_counter, dm_soml_table->cfo_diff_a, dm_soml_table->cfo_diff_b); + dm_soml_table->cfo_diff_sum_a += dm_soml_table->cfo_diff_a; + dm_soml_table->cfo_diff_sum_b += dm_soml_table->cfo_diff_b; + } + + dm_soml_table->is_soml_method_enable = 1; + dm_soml_table->soml_state_cnt++; + next_on_off = (dm_soml_table->soml_on_off == SOML_ON) ? SOML_ON : SOML_OFF; + phydm_soml_on_off(dm, next_on_off); + odm_set_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer, dm_soml_table->soml_delay_time); /*ms*/ + } else if ((dm_soml_table->soml_state_cnt % 2) != 0) { + dm_soml_table->soml_state_cnt++; + if (dm->support_ic_type == ODM_RTL8197F) + odm_move_memory(dm, dm_soml_table->pre_num_ht_bytes, dm_soml_table->num_ht_bytes, HT_RATE_IDX*size); + else if (dm->support_ic_type == ODM_RTL8822B) { + odm_move_memory(dm, dm_soml_table->pre_num_vht_bytes, dm_soml_table->num_vht_bytes, VHT_RATE_IDX*size); + dm_soml_table->cfo_counter++; + phydm_soml_cfo_process(dm, + &dm_soml_table->cfo_diff_a, + &dm_soml_table->cfo_diff_b); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n", dm_soml_table->cfo_counter, dm_soml_table->cfo_diff_a, dm_soml_table->cfo_diff_b); + dm_soml_table->cfo_diff_sum_a += dm_soml_table->cfo_diff_a; + dm_soml_table->cfo_diff_sum_b += dm_soml_table->cfo_diff_b; + } + odm_set_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer, dm_soml_table->soml_intvl); /*ms*/ + } else if ((dm_soml_table->soml_state_cnt % 2) == 0) { + if (dm->support_ic_type == ODM_RTL8822B) { + dm_soml_table->cfo_counter++; + phydm_soml_cfo_process(dm, + &dm_soml_table->cfo_diff_a, + &dm_soml_table->cfo_diff_b); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n", dm_soml_table->cfo_counter, dm_soml_table->cfo_diff_a, dm_soml_table->cfo_diff_b); + dm_soml_table->cfo_diff_sum_a += dm_soml_table->cfo_diff_a; + dm_soml_table->cfo_diff_sum_b += dm_soml_table->cfo_diff_b; + } + dm_soml_table->soml_state_cnt++; + phydm_soml_statistics(dm, dm_soml_table->soml_on_off); + next_on_off = (dm_soml_table->soml_on_off == SOML_ON) ? SOML_OFF : SOML_ON; + phydm_soml_on_off(dm, next_on_off); + odm_set_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer, dm_soml_table->soml_delay_time); /*ms*/ + } + } + /*Decision state: ==============================================================*/ + else { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[Decisoin state ]\n"); + phydm_soml_statistics(dm, dm_soml_table->soml_on_off); + dm_soml_table->cfo_diff_avg_a = (dm_soml_table->cfo_counter != 0) ? (dm_soml_table->cfo_diff_sum_a / dm_soml_table->cfo_counter) : 0; + dm_soml_table->cfo_diff_avg_b = (dm_soml_table->cfo_counter != 0) ? (dm_soml_table->cfo_diff_sum_b / dm_soml_table->cfo_counter) : 0; + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ cfo_diff_avg_a = %d KHz; cfo_diff_avg_b = %d KHz]\n", dm_soml_table->cfo_diff_avg_a, dm_soml_table->cfo_diff_avg_b); + + /* [Search 1st and 2ed rate by counter] */ + if (dm->support_ic_type == ODM_RTL8197F) { + for (i = 0; i < rate_num; i++) { + rate_ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "*num_ht_bytes_on HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (rate_ss_shift), (rate_ss_shift+7), + dm_soml_table->num_ht_bytes_on[rate_ss_shift + 0], dm_soml_table->num_ht_bytes_on[rate_ss_shift + 1], + dm_soml_table->num_ht_bytes_on[rate_ss_shift + 2], dm_soml_table->num_ht_bytes_on[rate_ss_shift + 3], + dm_soml_table->num_ht_bytes_on[rate_ss_shift + 4], dm_soml_table->num_ht_bytes_on[rate_ss_shift + 5], + dm_soml_table->num_ht_bytes_on[rate_ss_shift + 6], dm_soml_table->num_ht_bytes_on[rate_ss_shift + 7]); + } + + for (i = 0; i < rate_num; i++) { + rate_ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "*num_ht_bytes_off HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (rate_ss_shift), (rate_ss_shift+7), + dm_soml_table->num_ht_bytes_off[rate_ss_shift + 0], dm_soml_table->num_ht_bytes_off[rate_ss_shift + 1], + dm_soml_table->num_ht_bytes_off[rate_ss_shift + 2], dm_soml_table->num_ht_bytes_off[rate_ss_shift + 3], + dm_soml_table->num_ht_bytes_off[rate_ss_shift + 4], dm_soml_table->num_ht_bytes_off[rate_ss_shift + 5], + dm_soml_table->num_ht_bytes_off[rate_ss_shift + 6], dm_soml_table->num_ht_bytes_off[rate_ss_shift + 7]); + } + + for (i = 0; i < HT_RATE_IDX; i++) { + byte_total_on += dm_soml_table->num_ht_bytes_on[i]; + byte_total_off += dm_soml_table->num_ht_bytes_off[i]; + } + + } else if (dm->support_ic_type == ODM_RTL8822B) { + for (i = 0; i < VHT_ORDER_TYPE; i++) + num_total_qam += dm_soml_table->num_vht_qam[i]; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ ((2SS)) BPSK_QPSK_count = %d ; 16QAM_count = %d ; 64QAM_count = %d ; 256QAM_count = %d ; num_total_qam = %d]\n", dm_soml_table->num_vht_qam[BPSK_QPSK], dm_soml_table->num_vht_qam[QAM16], dm_soml_table->num_vht_qam[QAM64], dm_soml_table->num_vht_qam[QAM256], num_total_qam); + if (((dm_soml_table->num_vht_qam[QAM256] * 100) > (num_total_qam * dm_soml_table->qam256_dist_th)) && (dm_soml_table->cfo_diff_avg_a > dm_soml_table->cfo_qam256_th) && (dm_soml_table->cfo_diff_avg_b > dm_soml_table->cfo_qam256_th)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ QAM256_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", dm_soml_table->qam256_dist_th, dm_soml_table->cfo_qam256_th); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, SOML_OFF); + return; + } else if (((dm_soml_table->num_vht_qam[QAM64] * 100) > (num_total_qam * dm_soml_table->qam64_dist_th)) && (dm_soml_table->cfo_diff_avg_a > dm_soml_table->cfo_qam64_th) && (dm_soml_table->cfo_diff_avg_b > dm_soml_table->cfo_qam64_th)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ QAM64_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", dm_soml_table->qam64_dist_th, dm_soml_table->cfo_qam64_th); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, SOML_OFF); + return; + } else if (((dm_soml_table->num_vht_qam[QAM16] * 100) > (num_total_qam * dm_soml_table->qam16_dist_th)) && (dm_soml_table->cfo_diff_avg_a > dm_soml_table->cfo_qam16_th) && (dm_soml_table->cfo_diff_avg_b > dm_soml_table->cfo_qam16_th)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ QAM16_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", dm_soml_table->qam16_dist_th, dm_soml_table->cfo_qam16_th); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, SOML_OFF); + return; + } else if (((dm_soml_table->num_vht_qam[BPSK_QPSK] * 100) > (num_total_qam * dm_soml_table->bpsk_qpsk_dist_th)) && (dm_soml_table->cfo_diff_avg_a > dm_soml_table->cfo_qpsk_th) && (dm_soml_table->cfo_diff_avg_b > dm_soml_table->cfo_qpsk_th)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ BPSK_QPSK_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", dm_soml_table->bpsk_qpsk_dist_th, dm_soml_table->cfo_qpsk_th); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, SOML_OFF); + return; + } + + for (i = 0; i < rate_num; i++) { + rate_ss_shift = 10 * i; + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ num_vht_bytes_on VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n", + (i + 1), + dm_soml_table->num_vht_bytes_on[rate_ss_shift + 0], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 1], + dm_soml_table->num_vht_bytes_on[rate_ss_shift + 2], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 3], + dm_soml_table->num_vht_bytes_on[rate_ss_shift + 4], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 5], + dm_soml_table->num_vht_bytes_on[rate_ss_shift + 6], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 7], + dm_soml_table->num_vht_bytes_on[rate_ss_shift + 8], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 9]); + } + + for (i = 0; i < rate_num; i++) { + rate_ss_shift = 10 * i; + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ num_vht_bytes_off VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n", + (i + 1), + dm_soml_table->num_vht_bytes_off[rate_ss_shift + 0], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 1], + dm_soml_table->num_vht_bytes_off[rate_ss_shift + 2], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 3], + dm_soml_table->num_vht_bytes_off[rate_ss_shift + 4], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 5], + dm_soml_table->num_vht_bytes_off[rate_ss_shift + 6], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 7], + dm_soml_table->num_vht_bytes_off[rate_ss_shift + 8], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 9]); + } + + for (i = 0; i < VHT_RATE_IDX; i++) { + byte_total_on += dm_soml_table->num_vht_bytes_on[i]; + byte_total_off += dm_soml_table->num_vht_bytes_off[i]; + } + + } + + /* [Decision] */ + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ byte_total_on = %d ; byte_total_off = %d ]\n", byte_total_on, byte_total_off); + if (byte_total_on > byte_total_off) { + next_on_off = SOML_ON; + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ byte_total_on > byte_total_off ==> SOML_ON ]\n"); + } else if (byte_total_on < byte_total_off) { + next_on_off = SOML_OFF; + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ byte_total_on < byte_total_off ==> SOML_OFF ]\n"); + } else { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ stay at soml_last_state ]\n"); + next_on_off = dm_soml_table->soml_last_state; + } + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, next_on_off); + dm_soml_table->soml_last_state = next_on_off; + } + } else { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[escape from > TH_H || is_soml_method_enable==1]\n"); + phydm_adaptive_soml_reset(dm); + phydm_soml_on_off(dm, SOML_ON); + } + } else { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[number_active_client != 1]\n"); + phydm_adaptive_soml_reset(dm); + phydm_soml_on_off(dm, SOML_OFF); + } + } +} + +void +phydm_adaptive_soml_reset( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + dm_soml_table->soml_state_cnt = 0; + dm_soml_table->is_soml_method_enable = 0; + dm_soml_table->soml_counter = 0; +} + +#endif /* end of CONFIG_ADAPTIVE_SOML*/ + +void +phydm_soml_bytes_acq( + void *dm_void, + u8 rate_id, + u32 length +) +{ +#ifdef CONFIG_ADAPTIVE_SOML + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + if ((rate_id >= ODM_RATEMCS0) && (rate_id <= ODM_RATEMCS31)) + dm_soml_table->num_ht_bytes[rate_id - ODM_RATEMCS0] += length; + else if ((rate_id >= ODM_RATEVHTSS1MCS0) && (rate_id <= ODM_RATEVHTSS4MCS9)) + dm_soml_table->num_vht_bytes[rate_id - ODM_RATEVHTSS1MCS0] += length; + +#endif +} + +void +phydm_adaptive_soml_timers( + void *dm_void, + u8 state +) +{ +#ifdef CONFIG_ADAPTIVE_SOML + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + if (state == INIT_SOML_TIMMER) { + odm_initialize_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer, + (void *)phydm_adaptive_soml_callback, NULL, "phydm_adaptive_soml_timer"); + } else if (state == CANCEL_SOML_TIMMER) { + odm_cancel_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer); + } else if (state == RELEASE_SOML_TIMMER) { + odm_release_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer); + } +#endif +} + +void +phydm_adaptive_soml_init( + void *dm_void +) +{ +#ifdef CONFIG_ADAPTIVE_SOML + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; +#if 0 + if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[Return] Not Support Adaptive SOML\n"); + return; + } +#endif + PHYDM_DBG(dm, DBG_ADPTV_SOML, "phydm_adaptive_soml_init\n"); + + dm_soml_table->soml_state_cnt = 0; + dm_soml_table->soml_delay_time = 40; + dm_soml_table->soml_intvl = 150; + dm_soml_table->soml_train_num = 4; + dm_soml_table->is_soml_method_enable = 0; + dm_soml_table->soml_counter = 0; + dm_soml_table->soml_period = 1; + dm_soml_table->soml_select = 0; + dm_soml_table->cfo_counter = 0; + dm_soml_table->cfo_diff_sum_a = 0; + dm_soml_table->cfo_diff_sum_b = 0; + + dm_soml_table->cfo_qpsk_th = 94; + dm_soml_table->cfo_qam16_th = 38; + dm_soml_table->cfo_qam64_th = 17; + dm_soml_table->cfo_qam256_th = 7; + + dm_soml_table->bpsk_qpsk_dist_th = 20; + dm_soml_table->qam16_dist_th = 20; + dm_soml_table->qam64_dist_th = 20; + dm_soml_table->qam256_dist_th = 20; + + if (dm->support_ic_type == ODM_RTL8197F) + odm_set_bb_reg(dm, 0x998, BIT(25), 1); +#endif +} + +void +phydm_adaptive_soml( + void *dm_void +) +{ +#ifdef CONFIG_ADAPTIVE_SOML + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[Return!!!] Not Support Adaptive SOML Function\n"); + return; + } + + if (dm_soml_table->soml_counter < dm_soml_table->soml_period) { + dm_soml_table->soml_counter++; + return; + } + dm_soml_table->soml_counter = 0; + dm_soml_table->soml_state_cnt = 0; + dm_soml_table->cfo_counter = 0; + dm_soml_table->cfo_diff_sum_a = 0; + dm_soml_table->cfo_diff_sum_b = 0; + + phydm_soml_reset_rx_rate(dm); + + if (dm_soml_table->soml_select == 0) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Adaptive SOML Training !!!]\n"); + } else if (dm_soml_table->soml_select == 1) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Stop Adaptive SOML !!!]\n"); + phydm_soml_on_off(dm, SOML_ON); + return; + } else if (dm_soml_table->soml_select == 2) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Stop Adaptive SOML !!!]\n"); + phydm_soml_on_off(dm, SOML_OFF); + return; + } + + phydm_adsl(dm); + +#endif +} + +void +phydm_enable_adaptive_soml( + void *dm_void +) +{ +#ifdef CONFIG_ADAPTIVE_SOML + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[%s][Return!!!] enable Adaptive SOML\n", __func__); + dm->support_ability |= ODM_BB_ADAPTIVE_SOML; + phydm_soml_on_off(dm, SOML_ON); +#endif +} + +void +phydm_stop_adaptive_soml( + void *dm_void +) +{ +#ifdef CONFIG_ADAPTIVE_SOML + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[%s][Return!!!] Stop Adaptive SOML\n", __func__); + dm->support_ability &= ~ODM_BB_ADAPTIVE_SOML; + phydm_soml_on_off(dm, SOML_ON); + +#endif +} + +void +phydm_adaptive_soml_para_set( + void *dm_void, + u8 train_num, + u8 intvl, + u8 period, + u8 delay_time + +) +{ +#ifdef CONFIG_ADAPTIVE_SOML + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + dm_soml_table->soml_train_num = train_num; + dm_soml_table->soml_intvl = intvl; + dm_soml_table->soml_period = period; + dm_soml_table->soml_delay_time = delay_time; +#endif +} + +void +phydm_init_soft_ml_setting( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if (RTL8822B_SUPPORT == 1) + if (*dm->mp_mode == false) { + if (dm->support_ic_type & ODM_RTL8822B) { + /*odm_set_bb_reg(dm, 0x19a8, MASKDWORD, 0xd10a0000);*/ + phydm_somlrxhp_setting(dm, true); + dm->bsomlenabled = true; + } + } +#endif +#if (RTL8821C_SUPPORT == 1) + if (*dm->mp_mode == false) { + if (dm->support_ic_type & ODM_RTL8821C) + odm_set_bb_reg(dm, 0x19a8, BIT(31)|BIT(30)|BIT(29)|BIT(28), 0xd); + } +#endif +} + diff --git a/hal/phydm/phydm_soml.h b/hal/phydm/phydm_soml.h new file mode 100644 index 0000000..7f3c1fb --- /dev/null +++ b/hal/phydm/phydm_soml.h @@ -0,0 +1,254 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __PHYDMSOML_H__ +#define __PHYDMSOML_H__ + +#define ADAPTIVE_SOML_VERSION "1.0" + +#define ODM_ADAPTIVE_SOML_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F) + +#define INIT_SOML_TIMMER 0 +#define CANCEL_SOML_TIMMER 1 +#define RELEASE_SOML_TIMMER 2 + +#define SOML_RSSI_TH_HIGH 25 +#define SOML_RSSI_TH_LOW 20 + +#define HT_RATE_IDX 32 +#define VHT_RATE_IDX 40 + +#define HT_ORDER_TYPE 3 +#define VHT_ORDER_TYPE 4 + +/* +#define CFO_QPSK_TH 20 +#define CFO_QAM16_TH 20 +#define CFO_QAM64_TH 20 +#define CFO_QAM256_TH 20 + +#define BPSK_QPSK_DIST 20 +#define QAM16_DIST 30 +#define QAM64_DIST 30 +#define QAM256_DIST 20 +*/ +#define HT_TYPE 1 +#define VHT_TYPE 2 + +#define SOML_ON 1 +#define SOML_OFF 0 + +#ifdef CONFIG_ADAPTIVE_SOML + +struct adaptive_soml { + boolean is_soml_method_enable; + u8 soml_on_off; + u8 soml_state_cnt; + u8 soml_delay_time; + u8 soml_intvl; + u8 soml_train_num; + u8 soml_counter; + u8 soml_period; + u8 soml_select; + u8 soml_last_state; + u8 cfo_qpsk_th; + u8 cfo_qam16_th; + u8 cfo_qam64_th; + u8 cfo_qam256_th; + u8 bpsk_qpsk_dist_th; + u8 qam16_dist_th; + u8 qam64_dist_th; + u8 qam256_dist_th; + u8 cfo_counter; + s32 cfo_diff_a; + s32 cfo_diff_b; + s32 cfo_diff_sum_a; + s32 cfo_diff_sum_b; + s32 cfo_diff_avg_a; + s32 cfo_diff_avg_b; + u32 num_ht_qam[HT_ORDER_TYPE]; + u32 num_ht_bytes[HT_RATE_IDX]; + u32 pre_num_ht_bytes[HT_RATE_IDX]; + u32 num_ht_bytes_on[HT_RATE_IDX]; + u32 num_ht_bytes_off[HT_RATE_IDX]; + #if ODM_IC_11AC_SERIES_SUPPORT + u32 num_vht_qam[VHT_ORDER_TYPE]; + u32 num_qry_mu_vht_pkt[VHT_RATE_IDX]; + u32 num_vht_bytes[VHT_RATE_IDX]; + u32 pre_num_vht_bytes[VHT_RATE_IDX]; + u32 num_vht_bytes_on[VHT_RATE_IDX]; + u32 num_vht_bytes_off[VHT_RATE_IDX]; + #endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if USE_WORKITEM + RT_WORK_ITEM phydm_adaptive_soml_workitem; +#endif +#endif + struct phydm_timer_list phydm_adaptive_soml_timer; + +}; + +enum qam_order { + BPSK_QPSK = 0, + QAM16 = 1, + QAM64 = 2, + QAM256 = 3 +}; + +void +phydm_dynamicsoftmletting( + void *dm_void +); + +void +phydm_soml_on_off( + void *dm_void, + u8 swch +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void +phydm_adaptive_soml_callback( + struct phydm_timer_list *timer +); + +void +phydm_adaptive_soml_workitem_callback( + void *context +); + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void +phydm_adaptive_soml_callback( + void *dm_void +); + +void +phydm_adaptive_soml_workitem_callback( + void *context +); + +#else +void +phydm_adaptive_soml_callback( + void *dm_void +); + +#endif + +void +phydm_rx_qam_for_soml( + void *dm_void, + void *pkt_info_void +); + +void +phydm_soml_reset_rx_rate( + void *dm_void +); + +void +phydm_soml_cfo_process( + void *dm_void, + s32 *diff_a, + s32 *diff_b +); + +void +phydm_soml_debug( + void *dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +void +phydm_soml_statistics( + void *dm_void, + u8 on_off_state + +); + +void +phydm_adsl( + void *dm_void +); + +void +phydm_adaptive_soml_reset( + void *dm_void +); + +#endif +void +phydm_soml_bytes_acq( + void *dm_void, + u8 rate_id, + u32 length +); + +void +phydm_adaptive_soml_timers( + void *dm_void, + u8 state +); + +void +phydm_adaptive_soml_init( + void *dm_void +); + +void +phydm_adaptive_soml( + void *dm_void +); + +void +phydm_enable_adaptive_soml( + void *dm_void +); + +void +phydm_stop_adaptive_soml( + void *dm_void +); + +void +phydm_adaptive_soml_para_set( + void *dm_void, + u8 train_num, + u8 intvl, + u8 period, + u8 delay_time + +); + +void +phydm_init_soft_ml_setting( + void *dm_void +); + +#endif /*#ifndef __PHYDMSOML_H__*/ diff --git a/include/cmn_info/rtw_sta_info.h b/include/cmn_info/rtw_sta_info.h new file mode 100644 index 0000000..afc07aa --- /dev/null +++ b/include/cmn_info/rtw_sta_info.h @@ -0,0 +1,253 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + /*This header file is for all driver teams to use the same station info. +If you want to change this file please make sure notify all driver teams maintainers.*/ + +/*Created by YuChen 20170301*/ + +#ifndef __INC_RTW_STA_INFO_H +#define __INC_RTW_STA_INFO_H + +/*--------------------Define ---------------------------------------*/ + +#define STA_DM_CTRL_ACTIVE BIT(0) +#define STA_DM_CTRL_CFO_TRACKING BIT(1) + +#ifdef CONFIG_BEAMFORMING +#define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT(0) /*Declare sta support beamformer*/ +#define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT(1) /*Declare sta support beamformee*/ +#define BEAMFORMING_HT_BEAMFORMER_TEST BIT(2) /*Transmiting Beamforming no matter the target supports it or not*/ +#define BEAMFORMING_HT_BEAMFORMER_STEER_NUM (BIT(4)|BIT(5)) /*Sta Bfer's capability*/ +#define BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP (BIT(6)|BIT(7)) /*Sta BFee's capability*/ + +#define BEAMFORMING_VHT_BEAMFORMER_ENABLE BIT(0) /*Declare sta support beamformer*/ +#define BEAMFORMING_VHT_BEAMFORMEE_ENABLE BIT(1) /*Declare sta support beamformee*/ +#define BEAMFORMING_VHT_MU_MIMO_AP_ENABLE BIT(2) /*Declare sta support MU beamformer*/ +#define BEAMFORMING_VHT_MU_MIMO_STA_ENABLE BIT(3) /*Declare sta support MU beamformer*/ +#define BEAMFORMING_VHT_BEAMFORMER_TEST BIT(4) /*Transmiting Beamforming no matter the target supports it or not*/ +#define BEAMFORMING_VHT_BEAMFORMER_STS_CAP (BIT(8)|BIT(9)|BIT(10)) /*Sta BFee's capability*/ +#define BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM (BIT(12)|BIT(13)|BIT(14)) /*Sta Bfer's capability*/ +#endif + +#define HT_STBC_EN BIT(0) +#define VHT_STBC_EN BIT(1) + +#define HT_LDPC_EN BIT(0) +#define VHT_LDPC_EN BIT(1) + +#define SM_PS_STATIC 0 +#define SM_PS_DYNAMIC 1 +#define SM_PS_INVALID 2 +#define SM_PS_DISABLE 3 + + +/*cmn_sta_info.ra_sta_info.txrx_state*/ +#define TX_STATE 0 +#define RX_STATE 1 +#define BI_DIRECTION_STATE 2 + +/*--------------------Define Enum-----------------------------------*/ +enum channel_width { + CHANNEL_WIDTH_20 = 0, + CHANNEL_WIDTH_40 = 1, + CHANNEL_WIDTH_80 = 2, + CHANNEL_WIDTH_160 = 3, + CHANNEL_WIDTH_80_80 = 4, + CHANNEL_WIDTH_5 = 5, + CHANNEL_WIDTH_10 = 6, + CHANNEL_WIDTH_MAX = 7, +}; + +enum rf_type { + RF_1T1R = 0, + RF_1T2R = 1, + RF_2T2R = 2, + RF_2T3R = 3, + RF_2T4R = 4, + RF_3T3R = 5, + RF_3T4R = 6, + RF_4T4R = 7, + RF_TYPE_MAX, +}; + +enum bb_path { + BB_PATH_A = 0x00000001, + BB_PATH_B = 0x00000002, + BB_PATH_C = 0x00000004, + BB_PATH_D = 0x00000008, + + BB_PATH_AB = (BB_PATH_A | BB_PATH_B), + BB_PATH_AC = (BB_PATH_A | BB_PATH_C), + BB_PATH_AD = (BB_PATH_A | BB_PATH_D), + BB_PATH_BC = (BB_PATH_B | BB_PATH_C), + BB_PATH_BD = (BB_PATH_B | BB_PATH_D), + BB_PATH_CD = (BB_PATH_C | BB_PATH_D), + + BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), + BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), + BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), + BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), + + BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), +}; + +enum rf_path { + RF_PATH_A = 0, + RF_PATH_B = 1, + RF_PATH_C = 2, + RF_PATH_D = 3, + RF_PATH_AB, + RF_PATH_AC, + RF_PATH_AD, + RF_PATH_BC, + RF_PATH_BD, + RF_PATH_CD, + RF_PATH_ABC, + RF_PATH_ACD, + RF_PATH_BCD, + RF_PATH_ABCD, +}; + +enum wireless_set { + WIRELESS_CCK = 0x00000001, + WIRELESS_OFDM = 0x00000002, + WIRELESS_HT = 0x00000004, + WIRELESS_VHT = 0x00000008, +}; + +/*--------------------Define MACRO---------------------------------*/ + +/*--------------------Define Struct-----------------------------------*/ + +#ifdef CONFIG_BEAMFORMING +struct bf_cmn_info { + u8 ht_beamform_cap; /*Sta capablity*/ + u16 vht_beamform_cap; /*Sta capablity*/ + u16 p_aid; + u8 g_id; +}; +#endif +struct rssi_info { + s8 rssi; + s8 rssi_cck; + s8 rssi_ofdm; + u8 packet_map; + u8 ofdm_pkt_cnt; + u8 cck_pkt_cnt; + u16 cck_sum_power; + u8 is_send_rssi; + u8 valid_bit; + s16 rssi_acc; /*accumulate RSSI for per packet MA sum*/ +}; + +struct ra_sta_info { + u8 rate_id; /*ratr_idx*/ + u8 rssi_level; + + /*New*/ + u8 is_first_connect:1; /*CE: ra_rpt_linked, AP: H2C_rssi_rpt*/ + u8 is_support_sgi:1; /*driver*/ + u8 is_vht_enable:2; /*driver*/ + u8 disable_ra:1; /*driver*/ + u8 disable_pt:1; /*driver*/ /*remove is_disable_power_training*/ + u8 txrx_state:2; /*0: Tx, 1:Rx, 2:bi-direction*/ + u8 is_noisy:1; + + u8 curr_tx_rate; /*FW->Driver*/ + enum channel_width ra_bw_mode; /*max bandwidth, for RA only*/ + enum channel_width curr_tx_bw; /*FW->Driver*/ + u8 curr_retry_ratio; /*FW->Driver*/ + + u64 ramask; +}; + +struct dtp_info { + u8 dyn_tx_power; /*Dynamic Tx power offset*/ + u8 sta_tx_high_power_lvl:4; + u8 sta_last_dtp_lvl:4; +}; + +struct cmn_sta_info { + u16 dm_ctrl; + enum channel_width bw_mode; /*max bandwidth*/ + u8 mac_id; + u8 mac_addr[6]; + u16 aid; + enum rf_type mimo_type; /*sta XTXR*/ + struct rssi_info rssi_stat; + struct ra_sta_info ra_info; + u16 tx_moving_average_tp; /*tx average MBps*/ + u16 rx_moving_average_tp; /*rx average MBps*/ + u8 stbc_en:2; /*Driver : really use stbc!!*/ + u8 ldpc_en:2; + enum wireless_set support_wireless_set; +#ifdef CONFIG_BEAMFORMING + struct bf_cmn_info bf_info; +#endif + u8 sm_ps:2; + struct dtp_info dtp_stat; /*Dynamic Tx power offset*/ + /*u8 pw2cca_over_TH_cnt;*/ + /*u8 total_pw2cca_cnt;*/ +}; + +struct phydm_phyinfo_struct { + u8 rx_pwdb_all; + u8 signal_quality; /* OFDM: signal_quality=rx_mimo_signal_quality[0], CCK: signal qualityin 0-100 index. */ + u8 rx_mimo_signal_strength[4]; /* RSSI in 0~100 index */ + s8 rx_mimo_signal_quality[4]; /* OFDM: per-path's EVM translate to 0~100% , no used for CCK*/ + u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */ + s16 cfo_short[4]; /* per-path's cfo_short */ + s16 cfo_tail[4]; /* per-path's cfo_tail */ + s8 rx_power; /* in dBm Translate from PWdB */ + s8 recv_signal_power; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ + u8 bt_rx_rssi_percentage; + u8 signal_strength; /* in 0-100 index. */ + s8 rx_pwr[4]; /* per-path's pwdb */ + s8 rx_snr[4]; /* per-path's SNR */ +/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/ + u8 rx_count:2; /* RX path counter---*/ + u8 band_width:2; + u8 rxsc:4; /* sub-channel---*/ + u8 channel; /* channel number---*/ + u8 is_mu_packet:1; /* is MU packet or not---boolean*/ + u8 is_beamformed:1; /* BF packet---boolean*/ + u8 cnt_pw2cca; + u8 cnt_cca2agc_rdy; +/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/ +}; + +struct phydm_perpkt_info_struct { + u8 data_rate; + u8 station_id; + u8 is_cck_rate: 1; + u8 rate_ss:3; /*spatial stream of data rate*/ + u8 is_packet_match_bssid:1; /*boolean*/ + u8 is_packet_to_self:1; /*boolean*/ + u8 is_packet_beacon:1; /*boolean*/ + u8 is_to_self:1; /*boolean*/ + u8 ppdu_cnt; +}; + +/*--------------------Export global variable----------------------------*/ + +/*--------------------Function declaration-----------------------------*/ + +#endif diff --git a/include/rtw_rm.h b/include/rtw_rm.h new file mode 100644 index 0000000..9efcf13 --- /dev/null +++ b/include/rtw_rm.h @@ -0,0 +1,88 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __RTW_RM_H_ +#define __RTW_RM_H_ + +u8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf); + +#define RM_TIMER_NUM 32 +#define RM_ALL_MEAS BIT(1) +#define RM_ID_FOR_ALL(aid) ((aid<<16)|RM_ALL_MEAS) + +#define RM_CAP_ARG(x) ((u8 *)(x))[4], ((u8 *)(x))[3], ((u8 *)(x))[2], ((u8 *)(x))[1], ((u8 *)(x))[0] +#define RM_CAP_FMT "%02x %02x%02x %02x%02x" + +/* remember to modify rm_event_name() when adding new event */ +enum RM_EV_ID { + RM_EV_state_in, + RM_EV_busy_timer_expire, + RM_EV_delay_timer_expire, + RM_EV_meas_timer_expire, + RM_EV_retry_timer_expire, + RM_EV_repeat_delay_expire, + RM_EV_request_timer_expire, + RM_EV_wait_report, + RM_EV_start_meas, + RM_EV_survey_done, + RM_EV_recv_rep, + RM_EV_cancel, + RM_EV_state_out, + RM_EV_max +}; + +struct rm_event { + u32 rmid; + enum RM_EV_ID evid; + _list list; +}; + +#ifdef CONFIG_RTW_80211K + +struct rm_clock { + struct rm_obj *prm; + ATOMIC_T counter; + enum RM_EV_ID evid; +}; + +struct rm_priv { + u8 enable; + _queue ev_queue; + _queue rm_queue; + _timer rm_timer; + + struct rm_clock clock[RM_TIMER_NUM]; + u8 rm_en_cap_def[5]; + u8 rm_en_cap_assoc[5]; + + /* rm debug */ + void *prm_sel; +}; + +int rtw_init_rm(_adapter *padapter); +int rtw_free_rm_priv(_adapter *padapter); + +unsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame); +void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void rtw_ap_parse_sta_rm_en_cap(_adapter *padapter, + struct sta_info *psta, struct rtw_ieee802_11_elems *elems); + +int rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid); +void rm_handler(_adapter *padapter, struct rm_event *pev); + +u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta); + +#endif /*CONFIG_RTW_80211K */ +#endif /* __RTW_RM_H_ */ diff --git a/include/rtw_rm_fsm.h b/include/rtw_rm_fsm.h new file mode 100644 index 0000000..ba903a9 --- /dev/null +++ b/include/rtw_rm_fsm.h @@ -0,0 +1,389 @@ + +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __RTW_RM_FSM_H_ +#define __RTW_RM_FSM_H_ + +#ifdef CONFIG_RTW_80211K + +#define RM_SUPPORT_IWPRIV_DBG 1 +#define RM_MORE_DBG_MSG 0 + +#define DBG_BCN_REQ_DETAIL 0 +#define DBG_BCN_REQ_WILDCARD 0 +#define DBG_BCN_REQ_SSID 0 +#define DBG_BCN_REQ_SSID_NAME "RealKungFu" + +#define RM_REQ_TIMEOUT 10000 /* 10 seconds */ +#define RM_MEAS_TIMEOUT 10000 /* 10 seconds */ +#define RM_REPT_SCAN_INTVL 5000 /* 5 seconds */ +#define RM_REPT_POLL_INTVL 2000 /* 2 seconds */ +#define RM_COND_INTVL 2000 /* 2 seconds */ +#define RM_SCAN_DENY_TIMES 10 +#define RM_BUSY_TRAFFIC_TIMES 10 +#define RM_WAIT_BUSY_TIMEOUT 1000 /* 1 seconds */ + +#define MEAS_REQ_MOD_PARALLEL BIT(0) +#define MEAS_REQ_MOD_ENABLE BIT(1) +#define MEAS_REQ_MOD_REQUEST BIT(2) +#define MEAS_REQ_MOD_REPORT BIT(3) +#define MEAS_REQ_MOD_DUR_MAND BIT(4) + +#define MEAS_REP_MOD_LATE BIT(0) +#define MEAS_REP_MOD_INCAP BIT(1) +#define MEAS_REP_MOD_REFUSE BIT(2) + +#define RM_MASTER BIT(0) /* STA who issue meas_req */ +#define RM_SLAVE 0 /* STA who do measurement */ + +#define CLOCK_UNIT 10 /* ms */ +#define RTW_MAX_NB_RPT_IE_NUM 16 + +#define RM_GET_AID(rmid) ((rmid&0xffff0000)>>16) +#define RM_IS_ID_FOR_ALL(rmid) (rmid&RM_ALL_MEAS) + +/* + * define the following channels as the max channels in each channel plan. + * 2G, total 14 chnls + * {1,2,3,4,5,6,7,8,9,10,11,12,13,14} + * 5G, total 25 chnls + * {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,144,149,153,157,161,165} + */ +#define MAX_OP_CHANNEL_SET_NUM 11 +typedef struct _RT_OPERATING_CLASS { + int global_op_class; + int Len; + u16 Channel[MAX_OP_CHANNEL_SET_NUM]; +} RT_OPERATING_CLASS, *PRT_OPERATING_CLASS; + +/* IEEE 802.11-2012 Table 8-59 Measurement Type definitions +* for measurement request +* modify rm_meas_type_req_name() when adding new type +*/ +enum meas_type_of_req { + basic_req, /* spectrum measurement */ + cca_req, + rpi_histo_req, + ch_load_req, + noise_histo_req, + bcn_req, + frame_req, + sta_statis_req, + lci_req, + meas_type_req_max, +}; + +/* IEEE 802.11-2012 Table 8-81 Measurement Type definitions +* for measurement report +* modify rm_type_rep_name() when adding new type +*/ +enum meas_type_of_rep { + basic_rep, /* spectrum measurement */ + cca_rep, + rpi_histo_rep, + ch_load_rep, /* radio measurement */ + noise_histo_rep, + bcn_rep, + frame_rep, + sta_statis_rep, /* Radio measurement and WNM */ + lci_rep, + meas_type_rep_max +}; + +/* +* Beacon request +*/ +/* IEEE 802.11-2012 Table 8-64 Measurement mode for Beacon Request element */ +enum bcn_req_meas_mode { + bcn_req_passive, + bcn_req_active, + bcn_req_bcn_table +}; + +/* IEEE 802.11-2012 Table 8-65 optional subelement IDs for Beacon Request */ +enum bcn_req_opt_sub_id{ + bcn_req_ssid = 0, /* len 0-32 */ + bcn_req_rep_info = 1, /* len 2 */ + bcn_req_rep_detail = 2, /* len 1 */ + bcn_req_req = 10, /* len 0-237 */ + bcn_req_ac_ch_rep = 51 /* len 1-237 */ +}; + +/* IEEE 802.11-2012 Table 8-66 Reporting condition of Beacon Report */ +enum bcn_rep_cound_id{ + bcn_rep_cond_immediately, /* default */ + bcn_req_cond_rcpi_greater, + bcn_req_cond_rcpi_less, + bcn_req_cond_rsni_greater, + bcn_req_cond_rsni_less, + bcn_req_cond_max +}; + +struct opt_rep_info { + u8 cond; + u8 threshold; +}; + +#define BCN_REQ_OPT_MAX_NUM 16 +struct bcn_req_opt { + /* all req cmd id */ + u8 opt_id[BCN_REQ_OPT_MAX_NUM]; + u8 opt_id_num; + u8 rep_detail; + NDIS_802_11_SSID ssid; + + /* bcn report condition */ + struct opt_rep_info rep_cond; + + /* 0:default(Report to be issued after each measurement) */ + u8 *req_start; /*id : 10 request;start */ + u8 req_len; /*id : 10 request;length */ +}; + +/* +* channel load +*/ +/* IEEE 802.11-2012 Table 8-60 optional subelement IDs for channel load request */ +enum ch_load_opt_sub_id{ + ch_load_rsvd, + ch_load_rep_info +}; + +/* IEEE 802.11-2012 Table 8-61 Reporting condition for channel load Report */ +enum ch_load_cound_id{ + ch_load_cond_immediately, /* default */ + ch_load_cond_anpi_equal_greater, + ch_load_cond_anpi_equal_less, + ch_load_cond_max +}; + +/* +* Noise histogram +*/ +/* IEEE 802.11-2012 Table 8-62 optional subelement IDs for noise histogram */ +enum noise_histo_opt_sub_id{ + noise_histo_rsvd, + noise_histo_rep_info +}; + +/* IEEE 802.11-2012 Table 8-63 Reporting condition for noise historgarm Report */ +enum noise_histo_cound_id{ + noise_histo_cond_immediately, /* default */ + noise_histo_cond_anpi_equal_greater, + noise_histo_cond_anpi_equal_less, + noise_histo_cond_max +}; + +struct meas_req_opt { + /* report condition */ + struct opt_rep_info rep_cond; +}; + +/* +* State machine +*/ + +enum RM_STATE { + RM_ST_IDLE, + RM_ST_DO_MEAS, + RM_ST_WAIT_MEAS, + RM_ST_SEND_REPORT, + RM_ST_RECV_REPORT, + RM_ST_END, + RM_ST_MAX +}; + +struct rm_meas_req { + u8 category; + u8 action_code; /* T8-206 */ + u8 diag_token; + u16 rpt; + + u8 e_id; + u8 len; + u8 m_token; + u8 m_mode; /* req:F8-105, rep:F8-141 */ + u8 m_type; /* T8-59 */ + u8 op_class; + u8 ch_num; + u16 rand_intvl; /* units of TU */ + u16 meas_dur; /* units of TU */ + + u8 bssid[6]; /* for bcn_req */ + + u8 *pssid; + u8 *opt_s_elem_start; + int opt_s_elem_len; + + union { + struct bcn_req_opt bcn; + struct meas_req_opt clm; + struct meas_req_opt nhm; + }opt; + + struct rtw_ieee80211_channel ch_set[MAX_OP_CHANNEL_SET_NUM]; + u8 ch_set_ch_amount; +}; + +struct rm_meas_rep { + u8 category; + u8 action_code; /* T8-206 */ + u8 diag_token; + + u8 e_id; /* T8-54, 38 request; 39 report */ + u8 len; + u8 m_token; + u8 m_mode; /* req:F8-105, rep:F8-141 */ + u8 m_type; /* T8-59 */ + u8 op_class; + u8 ch_num; + + u8 ch_load; + u8 anpi; + u8 ipi[11]; + + u16 rpt; + u8 bssid[6]; /* for bcn_req */ +}; + +#define MAX_BUF_NUM 128 +struct data_buf { + u8 *pbuf; + u16 len; +}; + +struct rm_obj { + + /* aid << 16 + |diag_token << 8 + |B(1) 1/0:All_AID/UNIC + |B(0) 1/0:RM_MASTER/RM_SLAVE */ + u32 rmid; + + enum RM_STATE state; + struct rm_meas_req q; + struct rm_meas_rep p; + struct sta_info *psta; + struct rm_clock *pclock; + + /* meas report */ + u64 meas_start_time; + u64 meas_end_time; + int wait_busy; + u8 poll_mode; + + struct data_buf buf[MAX_BUF_NUM]; + + _list list; +}; + +/* +* Measurement +*/ +struct opt_subelement { + u8 id; + u8 length; + u8 *data; +}; + +/* 802.11-2012 Table 8-206 Radio Measurment Action field */ +enum rm_action_code { + RM_ACT_RADIO_MEAS_REQ, + RM_ACT_RADIO_MEAS_REP, + RM_ACT_LINK_MEAS_REQ, + RM_ACT_LINK_MEAS_REP, + RM_ACT_NB_REP_REQ, /* 4 */ + RM_ACT_NB_REP_RESP, + RM_ACT_RESV, + RM_ACT_MAX +}; + +/* 802.11-2012 Table 8-119 RM Enabled Capabilities definition */ +enum rm_cap_en { + RM_LINK_MEAS_CAP_EN, + RM_NB_REP_CAP_EN, /* neighbor report */ + RM_PARAL_MEAS_CAP_EN, /* parallel report */ + RM_REPEAT_MEAS_CAP_EN, + RM_BCN_PASSIVE_MEAS_CAP_EN, + RM_BCN_ACTIVE_MEAS_CAP_EN, + RM_BCN_TABLE_MEAS_CAP_EN, + RM_BCN_MEAS_REP_COND_CAP_EN, /* conditions */ + + RM_FRAME_MEAS_CAP_EN, + RM_CH_LOAD_CAP_EN, + RM_NOISE_HISTO_CAP_EN, /* noise historgram */ + RM_STATIS_MEAS_CAP_EN, /* statistics */ + RM_LCI_MEAS_CAP_EN, /* 12 */ + RM_LCI_AMIMUTH_CAP_EN, + RM_TRANS_STREAM_CAT_MEAS_CAP_EN, + RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN, + + RM_AP_CH_REP_CAP_EN, + RM_RM_MIB_CAP_EN, + RM_OP_CH_MAX_MEAS_DUR0, /* 18-20 */ + RM_OP_CH_MAX_MEAS_DUR1, + RM_OP_CH_MAX_MEAS_DUR2, + RM_NONOP_CH_MAX_MEAS_DUR0, /* 21-23 */ + RM_NONOP_CH_MAX_MEAS_DUR1, + RM_NONOP_CH_MAX_MEAS_DUR2, + + RM_MEAS_PILOT_CAP0, /* 24-26 */ + RM_MEAS_PILOT_CAP1, + RM_MEAS_PILOT_CAP2, + RM_MEAS_PILOT_TRANS_INFO_CAP_EN, + RM_NB_REP_TSF_OFFSET_CAP_EN, + RM_RCPI_MEAS_CAP_EN, /* 29 */ + RM_RSNI_MEAS_CAP_EN, + RM_BSS_AVG_ACCESS_DELAY_CAP_EN, + + RM_AVALB_ADMIS_CAPACITY_CAP_EN, + RM_ANT_CAP_EN, + RM_RSVD, /* 34-39 */ + RM_MAX +}; + +char *rm_state_name(enum RM_STATE state); +char *rm_event_name(enum RM_EV_ID evid); +char *rm_type_req_name(u8 meas_type); +int _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid); +int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *obj, bool to_head); + +void rm_free_rmobj(struct rm_obj *prm); +struct rm_obj *rm_alloc_rmobj(_adapter *padapter); +struct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid); +struct sta_info *rm_get_psta(_adapter *padapter, u32 rmid); + +int retrieve_radio_meas_result(struct rm_obj *prm); +int rm_radio_meas_report_cond(struct rm_obj *prm); +int rm_recv_radio_mens_req(_adapter *padapter, + union recv_frame *precv_frame,struct sta_info *psta); +int rm_recv_radio_mens_rep(_adapter *padapter, + union recv_frame *precv_frame, struct sta_info *psta); +int rm_radio_mens_nb_rep(_adapter *padapter, + union recv_frame *precv_frame, struct sta_info *psta); +int issue_null_reply(struct rm_obj *prm); +int issue_beacon_rep(struct rm_obj *prm); +int issue_nb_req(struct rm_obj *prm); +int issue_radio_meas_req(struct rm_obj *prm); +int issue_radio_meas_rep(struct rm_obj *prm); + +void rm_set_rep_mode(struct rm_obj *prm, u8 mode); + +int ready_for_scan(struct rm_obj *prm); +int rm_sitesurvey(struct rm_obj *prm); + +#endif /*CONFIG_RTW_80211K*/ +#endif /*__RTW_RM_FSM_H_*/ diff --git a/include/rtw_rson.h b/include/rtw_rson.h new file mode 100644 index 0000000..6996738 --- /dev/null +++ b/include/rtw_rson.h @@ -0,0 +1,61 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_RSON_H_ +#define __RTW_RSON_H_ + + +#define RTW_RSON_VER 1 + +#define RTW_RSON_SCORE_NOTSUP 0x0 +#define RTW_RSON_SCORE_NOTCNNT 0x1 +#define RTW_RSON_SCORE_MAX 0xFF +#define RTW_RSON_HC_NOTREADY 0xFF +#define RTW_RSON_HC_ROOT 0x0 +#define RTW_RSON_ALLOWCONNECT 0x1 +#define RTW_RSON_DENYCONNECT 0x0 + + + +/* for rtw self-origanization spec 1 */ +struct rtw_rson_struct { + u8 ver; + u32 id; + u8 hopcnt; + u8 connectible; + u8 loading; + u8 res[16]; +} __attribute__((__packed__)); + +void init_rtw_rson_data(struct dvobj_priv *dvobj); +void rtw_rson_get_property_str(_adapter *padapter, char *rson_data_str); +int rtw_rson_set_property(_adapter *padapter, char *field, char *value); +int rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor); +int rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct rtw_rson_struct *rson_data); +u8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI Rssi); +void rtw_rson_handle_ie(WLAN_BSSID_EX *bssid, u8 ie_offset); +u32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len); +void rtw_rson_do_disconnect(_adapter *padapter); +void rtw_rson_join_done(_adapter *padapter); +int rtw_rson_isupdate_roamcan(struct mlme_priv *mlme, struct wlan_network **candidate, struct wlan_network *competitor); +void rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead); +u8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset); +u8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op); +void rtw_rson_scan_cmd_hdl(_adapter *padapter, int op); +#endif /* __RTW_RSON_H_ */ diff --git a/os_dep/linux/rhashtable.c b/os_dep/linux/rhashtable.c new file mode 100644 index 0000000..af9c9ae --- /dev/null +++ b/os_dep/linux/rhashtable.c @@ -0,0 +1,844 @@ +/* + * Resizable, Scalable, Concurrent Hash Table + * + * Copyright (c) 2015 Herbert Xu + * Copyright (c) 2014-2015 Thomas Graf + * Copyright (c) 2008-2014 Patrick McHardy + * + * Code partially derived from nft_hash + * Rewritten with rehash code from br_multicast plus single list + * pointer as suggested by Josh Triplett + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HASH_DEFAULT_SIZE 64UL +#define HASH_MIN_SIZE 4U +#define BUCKET_LOCKS_PER_CPU 128UL + +static u32 head_hashfn(struct rhashtable *ht, + const struct bucket_table *tbl, + const struct rhash_head *he) +{ + return rht_head_hashfn(ht, tbl, he, ht->p); +} + +#ifdef CONFIG_PROVE_LOCKING +#define ASSERT_RHT_MUTEX(HT) BUG_ON(!lockdep_rht_mutex_is_held(HT)) + +int lockdep_rht_mutex_is_held(struct rhashtable *ht) +{ + return (debug_locks) ? lockdep_is_held(&ht->mutex) : 1; +} + +int lockdep_rht_bucket_is_held(const struct bucket_table *tbl, u32 hash) +{ + spinlock_t *lock = rht_bucket_lock(tbl, hash); + + return (debug_locks) ? lockdep_is_held(lock) : 1; +} +#else +#define ASSERT_RHT_MUTEX(HT) +#endif + + +static int alloc_bucket_locks(struct rhashtable *ht, struct bucket_table *tbl, + gfp_t gfp) +{ + unsigned int i, size; +#if defined(CONFIG_PROVE_LOCKING) + unsigned int nr_pcpus = 2; +#else + unsigned int nr_pcpus = num_possible_cpus(); +#endif + + nr_pcpus = min_t(unsigned int, nr_pcpus, 32UL); + size = roundup_pow_of_two(nr_pcpus * ht->p.locks_mul); + + /* Never allocate more than 0.5 locks per bucket */ + size = min_t(unsigned int, size, tbl->size >> 1); + + if (sizeof(spinlock_t) != 0) { +#ifdef CONFIG_NUMA + if (size * sizeof(spinlock_t) > PAGE_SIZE && + gfp == GFP_KERNEL) + tbl->locks = vmalloc(size * sizeof(spinlock_t)); + else +#endif + tbl->locks = kmalloc_array(size, sizeof(spinlock_t), + gfp); + if (!tbl->locks) + return -ENOMEM; + for (i = 0; i < size; i++) + spin_lock_init(&tbl->locks[i]); + } + tbl->locks_mask = size - 1; + + return 0; +} + +static void bucket_table_free(const struct bucket_table *tbl) +{ + if (tbl) + kvfree(tbl->locks); + + kvfree(tbl); +} + +static void bucket_table_free_rcu(struct rcu_head *head) +{ + bucket_table_free(container_of(head, struct bucket_table, rcu)); +} + +static struct bucket_table *bucket_table_alloc(struct rhashtable *ht, + size_t nbuckets, + gfp_t gfp) +{ + struct bucket_table *tbl = NULL; + size_t size; + int i; + + size = sizeof(*tbl) + nbuckets * sizeof(tbl->buckets[0]); + if (size <= (PAGE_SIZE << PAGE_ALLOC_COSTLY_ORDER) || + gfp != GFP_KERNEL) + tbl = kzalloc(size, gfp | __GFP_NOWARN | __GFP_NORETRY); + if (tbl == NULL && gfp == GFP_KERNEL) + tbl = vzalloc(size); + if (tbl == NULL) + return NULL; + + tbl->size = nbuckets; + + if (alloc_bucket_locks(ht, tbl, gfp) < 0) { + bucket_table_free(tbl); + return NULL; + } + + INIT_LIST_HEAD(&tbl->walkers); + + get_random_bytes(&tbl->hash_rnd, sizeof(tbl->hash_rnd)); + + for (i = 0; i < nbuckets; i++) + INIT_RHT_NULLS_HEAD(tbl->buckets[i], ht, i); + + return tbl; +} + +static struct bucket_table *rhashtable_last_table(struct rhashtable *ht, + struct bucket_table *tbl) +{ + struct bucket_table *new_tbl; + + do { + new_tbl = tbl; + tbl = rht_dereference_rcu(tbl->future_tbl, ht); + } while (tbl); + + return new_tbl; +} + +static int rhashtable_rehash_one(struct rhashtable *ht, unsigned int old_hash) +{ + struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht); + struct bucket_table *new_tbl = rhashtable_last_table(ht, + rht_dereference_rcu(old_tbl->future_tbl, ht)); + struct rhash_head __rcu **pprev = &old_tbl->buckets[old_hash]; + int err = -ENOENT; + struct rhash_head *head, *next, *entry; + spinlock_t *new_bucket_lock; + unsigned int new_hash; + + rht_for_each(entry, old_tbl, old_hash) { + err = 0; + next = rht_dereference_bucket(entry->next, old_tbl, old_hash); + + if (rht_is_a_nulls(next)) + break; + + pprev = &entry->next; + } + + if (err) + goto out; + + new_hash = head_hashfn(ht, new_tbl, entry); + + new_bucket_lock = rht_bucket_lock(new_tbl, new_hash); + + spin_lock_nested(new_bucket_lock, SINGLE_DEPTH_NESTING); + head = rht_dereference_bucket(new_tbl->buckets[new_hash], + new_tbl, new_hash); + + RCU_INIT_POINTER(entry->next, head); + + rcu_assign_pointer(new_tbl->buckets[new_hash], entry); + spin_unlock(new_bucket_lock); + + rcu_assign_pointer(*pprev, next); + +out: + return err; +} + +static void rhashtable_rehash_chain(struct rhashtable *ht, + unsigned int old_hash) +{ + struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht); + spinlock_t *old_bucket_lock; + + old_bucket_lock = rht_bucket_lock(old_tbl, old_hash); + + spin_lock_bh(old_bucket_lock); + while (!rhashtable_rehash_one(ht, old_hash)) + ; + old_tbl->rehash++; + spin_unlock_bh(old_bucket_lock); +} + +static int rhashtable_rehash_attach(struct rhashtable *ht, + struct bucket_table *old_tbl, + struct bucket_table *new_tbl) +{ + /* Protect future_tbl using the first bucket lock. */ + spin_lock_bh(old_tbl->locks); + + /* Did somebody beat us to it? */ + if (rcu_access_pointer(old_tbl->future_tbl)) { + spin_unlock_bh(old_tbl->locks); + return -EEXIST; + } + + /* Make insertions go into the new, empty table right away. Deletions + * and lookups will be attempted in both tables until we synchronize. + */ + rcu_assign_pointer(old_tbl->future_tbl, new_tbl); + + /* Ensure the new table is visible to readers. */ + smp_wmb(); + + spin_unlock_bh(old_tbl->locks); + + return 0; +} + +static int rhashtable_rehash_table(struct rhashtable *ht) +{ + struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht); + struct bucket_table *new_tbl; + struct rhashtable_walker *walker; + unsigned int old_hash; + + new_tbl = rht_dereference(old_tbl->future_tbl, ht); + if (!new_tbl) + return 0; + + for (old_hash = 0; old_hash < old_tbl->size; old_hash++) + rhashtable_rehash_chain(ht, old_hash); + + /* Publish the new table pointer. */ + rcu_assign_pointer(ht->tbl, new_tbl); + + spin_lock(&ht->lock); + list_for_each_entry(walker, &old_tbl->walkers, list) + walker->tbl = NULL; + spin_unlock(&ht->lock); + + /* Wait for readers. All new readers will see the new + * table, and thus no references to the old table will + * remain. + */ + call_rcu(&old_tbl->rcu, bucket_table_free_rcu); + + return rht_dereference(new_tbl->future_tbl, ht) ? -EAGAIN : 0; +} + +/** + * rhashtable_expand - Expand hash table while allowing concurrent lookups + * @ht: the hash table to expand + * + * A secondary bucket array is allocated and the hash entries are migrated. + * + * This function may only be called in a context where it is safe to call + * synchronize_rcu(), e.g. not within a rcu_read_lock() section. + * + * The caller must ensure that no concurrent resizing occurs by holding + * ht->mutex. + * + * It is valid to have concurrent insertions and deletions protected by per + * bucket locks or concurrent RCU protected lookups and traversals. + */ +static int rhashtable_expand(struct rhashtable *ht) +{ + struct bucket_table *new_tbl, *old_tbl = rht_dereference(ht->tbl, ht); + int err; + + ASSERT_RHT_MUTEX(ht); + + old_tbl = rhashtable_last_table(ht, old_tbl); + + new_tbl = bucket_table_alloc(ht, old_tbl->size * 2, GFP_KERNEL); + if (new_tbl == NULL) + return -ENOMEM; + + err = rhashtable_rehash_attach(ht, old_tbl, new_tbl); + if (err) + bucket_table_free(new_tbl); + + return err; +} + +/** + * rhashtable_shrink - Shrink hash table while allowing concurrent lookups + * @ht: the hash table to shrink + * + * This function shrinks the hash table to fit, i.e., the smallest + * size would not cause it to expand right away automatically. + * + * The caller must ensure that no concurrent resizing occurs by holding + * ht->mutex. + * + * The caller must ensure that no concurrent table mutations take place. + * It is however valid to have concurrent lookups if they are RCU protected. + * + * It is valid to have concurrent insertions and deletions protected by per + * bucket locks or concurrent RCU protected lookups and traversals. + */ +static int rhashtable_shrink(struct rhashtable *ht) +{ + struct bucket_table *new_tbl, *old_tbl = rht_dereference(ht->tbl, ht); + unsigned int size; + int err; + + ASSERT_RHT_MUTEX(ht); + + size = roundup_pow_of_two(atomic_read(&ht->nelems) * 3 / 2); + if (size < ht->p.min_size) + size = ht->p.min_size; + + if (old_tbl->size <= size) + return 0; + + if (rht_dereference(old_tbl->future_tbl, ht)) + return -EEXIST; + + new_tbl = bucket_table_alloc(ht, size, GFP_KERNEL); + if (new_tbl == NULL) + return -ENOMEM; + + err = rhashtable_rehash_attach(ht, old_tbl, new_tbl); + if (err) + bucket_table_free(new_tbl); + + return err; +} + +static void rht_deferred_worker(struct work_struct *work) +{ + struct rhashtable *ht; + struct bucket_table *tbl; + int err = 0; + + ht = container_of(work, struct rhashtable, run_work); + mutex_lock(&ht->mutex); + + tbl = rht_dereference(ht->tbl, ht); + tbl = rhashtable_last_table(ht, tbl); + + if (rht_grow_above_75(ht, tbl)) + rhashtable_expand(ht); + else if (ht->p.automatic_shrinking && rht_shrink_below_30(ht, tbl)) + rhashtable_shrink(ht); + + err = rhashtable_rehash_table(ht); + + mutex_unlock(&ht->mutex); + + if (err) + schedule_work(&ht->run_work); +} + +static bool rhashtable_check_elasticity(struct rhashtable *ht, + struct bucket_table *tbl, + unsigned int hash) +{ + unsigned int elasticity = ht->elasticity; + struct rhash_head *head; + + rht_for_each(head, tbl, hash) + if (!--elasticity) + return true; + + return false; +} + +int rhashtable_insert_rehash(struct rhashtable *ht, + struct bucket_table *tbl) +{ + struct bucket_table *old_tbl; + struct bucket_table *new_tbl; + unsigned int size; + int err; + + old_tbl = rht_dereference_rcu(ht->tbl, ht); + + size = tbl->size; + + err = -EBUSY; + + if (rht_grow_above_75(ht, tbl)) + size *= 2; + /* Do not schedule more than one rehash */ + else if (old_tbl != tbl) + goto fail; + + err = -ENOMEM; + + new_tbl = bucket_table_alloc(ht, size, GFP_ATOMIC); + if (new_tbl == NULL) + goto fail; + + err = rhashtable_rehash_attach(ht, tbl, new_tbl); + if (err) { + bucket_table_free(new_tbl); + if (err == -EEXIST) + err = 0; + } else + schedule_work(&ht->run_work); + + return err; + +fail: + /* Do not fail the insert if someone else did a rehash. */ + if (likely(rcu_dereference_raw(tbl->future_tbl))) + return 0; + + /* Schedule async rehash to retry allocation in process context. */ + if (err == -ENOMEM) + schedule_work(&ht->run_work); + + return err; +} + +struct bucket_table *rhashtable_insert_slow(struct rhashtable *ht, + const void *key, + struct rhash_head *obj, + struct bucket_table *tbl) +{ + struct rhash_head *head; + unsigned int hash; + int err; + + tbl = rhashtable_last_table(ht, tbl); + hash = head_hashfn(ht, tbl, obj); + spin_lock_nested(rht_bucket_lock(tbl, hash), SINGLE_DEPTH_NESTING); + + err = -EEXIST; + if (key && rhashtable_lookup_fast(ht, key, ht->p)) + goto exit; + + err = -E2BIG; + if (unlikely(rht_grow_above_max(ht, tbl))) + goto exit; + + err = -EAGAIN; + if (rhashtable_check_elasticity(ht, tbl, hash) || + rht_grow_above_100(ht, tbl)) + goto exit; + + err = 0; + + head = rht_dereference_bucket(tbl->buckets[hash], tbl, hash); + + RCU_INIT_POINTER(obj->next, head); + + rcu_assign_pointer(tbl->buckets[hash], obj); + + atomic_inc(&ht->nelems); + +exit: + spin_unlock(rht_bucket_lock(tbl, hash)); + + if (err == 0) + return NULL; + else if (err == -EAGAIN) + return tbl; + else + return ERR_PTR(err); +} + +/** + * rhashtable_walk_init - Initialise an iterator + * @ht: Table to walk over + * @iter: Hash table Iterator + * + * This function prepares a hash table walk. + * + * Note that if you restart a walk after rhashtable_walk_stop you + * may see the same object twice. Also, you may miss objects if + * there are removals in between rhashtable_walk_stop and the next + * call to rhashtable_walk_start. + * + * For a completely stable walk you should construct your own data + * structure outside the hash table. + * + * This function may sleep so you must not call it from interrupt + * context or with spin locks held. + * + * You must call rhashtable_walk_exit if this function returns + * successfully. + */ +int rhashtable_walk_init(struct rhashtable *ht, struct rhashtable_iter *iter) +{ + iter->ht = ht; + iter->p = NULL; + iter->slot = 0; + iter->skip = 0; + + iter->walker = kmalloc(sizeof(*iter->walker), GFP_KERNEL); + if (!iter->walker) + return -ENOMEM; + + spin_lock(&ht->lock); + iter->walker->tbl = + rcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock)); + list_add(&iter->walker->list, &iter->walker->tbl->walkers); + spin_unlock(&ht->lock); + + return 0; +} + +/** + * rhashtable_walk_exit - Free an iterator + * @iter: Hash table Iterator + * + * This function frees resources allocated by rhashtable_walk_init. + */ +void rhashtable_walk_exit(struct rhashtable_iter *iter) +{ + spin_lock(&iter->ht->lock); + if (iter->walker->tbl) + list_del(&iter->walker->list); + spin_unlock(&iter->ht->lock); + kfree(iter->walker); +} + +/** + * rhashtable_walk_start - Start a hash table walk + * @iter: Hash table iterator + * + * Start a hash table walk. Note that we take the RCU lock in all + * cases including when we return an error. So you must always call + * rhashtable_walk_stop to clean up. + * + * Returns zero if successful. + * + * Returns -EAGAIN if resize event occured. Note that the iterator + * will rewind back to the beginning and you may use it immediately + * by calling rhashtable_walk_next. + */ +int rhashtable_walk_start(struct rhashtable_iter *iter) + __acquires(RCU) +{ + struct rhashtable *ht = iter->ht; + + rcu_read_lock(); + + spin_lock(&ht->lock); + if (iter->walker->tbl) + list_del(&iter->walker->list); + spin_unlock(&ht->lock); + + if (!iter->walker->tbl) { + iter->walker->tbl = rht_dereference_rcu(ht->tbl, ht); + return -EAGAIN; + } + + return 0; +} + +/** + * rhashtable_walk_next - Return the next object and advance the iterator + * @iter: Hash table iterator + * + * Note that you must call rhashtable_walk_stop when you are finished + * with the walk. + * + * Returns the next object or NULL when the end of the table is reached. + * + * Returns -EAGAIN if resize event occured. Note that the iterator + * will rewind back to the beginning and you may continue to use it. + */ +void *rhashtable_walk_next(struct rhashtable_iter *iter) +{ + struct bucket_table *tbl = iter->walker->tbl; + struct rhashtable *ht = iter->ht; + struct rhash_head *p = iter->p; + + if (p) { + p = rht_dereference_bucket_rcu(p->next, tbl, iter->slot); + goto next; + } + + for (; iter->slot < tbl->size; iter->slot++) { + int skip = iter->skip; + + rht_for_each_rcu(p, tbl, iter->slot) { + if (!skip) + break; + skip--; + } + +next: + if (!rht_is_a_nulls(p)) { + iter->skip++; + iter->p = p; + return rht_obj(ht, p); + } + + iter->skip = 0; + } + + iter->p = NULL; + + /* Ensure we see any new tables. */ + smp_rmb(); + + iter->walker->tbl = rht_dereference_rcu(tbl->future_tbl, ht); + if (iter->walker->tbl) { + iter->slot = 0; + iter->skip = 0; + return ERR_PTR(-EAGAIN); + } + + return NULL; +} + +/** + * rhashtable_walk_stop - Finish a hash table walk + * @iter: Hash table iterator + * + * Finish a hash table walk. + */ +void rhashtable_walk_stop(struct rhashtable_iter *iter) + __releases(RCU) +{ + struct rhashtable *ht; + struct bucket_table *tbl = iter->walker->tbl; + + if (!tbl) + goto out; + + ht = iter->ht; + + spin_lock(&ht->lock); + if (tbl->rehash < tbl->size) + list_add(&iter->walker->list, &tbl->walkers); + else + iter->walker->tbl = NULL; + spin_unlock(&ht->lock); + + iter->p = NULL; + +out: + rcu_read_unlock(); +} + +static size_t rounded_hashtable_size(const struct rhashtable_params *params) +{ + return max(roundup_pow_of_two(params->nelem_hint * 4 / 3), + (unsigned long)params->min_size); +} + +static u32 rhashtable_jhash2(const void *key, u32 length, u32 seed) +{ + return jhash2(key, length, seed); +} + +/** + * rhashtable_init - initialize a new hash table + * @ht: hash table to be initialized + * @params: configuration parameters + * + * Initializes a new hash table based on the provided configuration + * parameters. A table can be configured either with a variable or + * fixed length key: + * + * Configuration Example 1: Fixed length keys + * struct test_obj { + * int key; + * void * my_member; + * struct rhash_head node; + * }; + * + * struct rhashtable_params params = { + * .head_offset = offsetof(struct test_obj, node), + * .key_offset = offsetof(struct test_obj, key), + * .key_len = sizeof(int), + * .hashfn = jhash, + * .nulls_base = (1U << RHT_BASE_SHIFT), + * }; + * + * Configuration Example 2: Variable length keys + * struct test_obj { + * [...] + * struct rhash_head node; + * }; + * + * u32 my_hash_fn(const void *data, u32 len, u32 seed) + * { + * struct test_obj *obj = data; + * + * return [... hash ...]; + * } + * + * struct rhashtable_params params = { + * .head_offset = offsetof(struct test_obj, node), + * .hashfn = jhash, + * .obj_hashfn = my_hash_fn, + * }; + */ +int rhashtable_init(struct rhashtable *ht, + const struct rhashtable_params *params) +{ + struct bucket_table *tbl; + size_t size; + + size = HASH_DEFAULT_SIZE; + + if ((!params->key_len && !params->obj_hashfn) || + (params->obj_hashfn && !params->obj_cmpfn)) + return -EINVAL; + + if (params->nulls_base && params->nulls_base < (1U << RHT_BASE_SHIFT)) + return -EINVAL; + + memset(ht, 0, sizeof(*ht)); + mutex_init(&ht->mutex); + spin_lock_init(&ht->lock); + memcpy(&ht->p, params, sizeof(*params)); + + if (params->min_size) + ht->p.min_size = roundup_pow_of_two(params->min_size); + + if (params->max_size) + ht->p.max_size = rounddown_pow_of_two(params->max_size); + + if (params->insecure_max_entries) + ht->p.insecure_max_entries = + rounddown_pow_of_two(params->insecure_max_entries); + else + ht->p.insecure_max_entries = ht->p.max_size * 2; + + ht->p.min_size = max(ht->p.min_size, HASH_MIN_SIZE); + + if (params->nelem_hint) + size = rounded_hashtable_size(&ht->p); + + /* The maximum (not average) chain length grows with the + * size of the hash table, at a rate of (log N)/(log log N). + * The value of 16 is selected so that even if the hash + * table grew to 2^32 you would not expect the maximum + * chain length to exceed it unless we are under attack + * (or extremely unlucky). + * + * As this limit is only to detect attacks, we don't need + * to set it to a lower value as you'd need the chain + * length to vastly exceed 16 to have any real effect + * on the system. + */ + if (!params->insecure_elasticity) + ht->elasticity = 16; + + if (params->locks_mul) + ht->p.locks_mul = roundup_pow_of_two(params->locks_mul); + else + ht->p.locks_mul = BUCKET_LOCKS_PER_CPU; + + ht->key_len = ht->p.key_len; + if (!params->hashfn) { + ht->p.hashfn = jhash; + + if (!(ht->key_len & (sizeof(u32) - 1))) { + ht->key_len /= sizeof(u32); + ht->p.hashfn = rhashtable_jhash2; + } + } + + tbl = bucket_table_alloc(ht, size, GFP_KERNEL); + if (tbl == NULL) + return -ENOMEM; + + atomic_set(&ht->nelems, 0); + + RCU_INIT_POINTER(ht->tbl, tbl); + + INIT_WORK(&ht->run_work, rht_deferred_worker); + + return 0; +} + +/** + * rhashtable_free_and_destroy - free elements and destroy hash table + * @ht: the hash table to destroy + * @free_fn: callback to release resources of element + * @arg: pointer passed to free_fn + * + * Stops an eventual async resize. If defined, invokes free_fn for each + * element to releasal resources. Please note that RCU protected + * readers may still be accessing the elements. Releasing of resources + * must occur in a compatible manner. Then frees the bucket array. + * + * This function will eventually sleep to wait for an async resize + * to complete. The caller is responsible that no further write operations + * occurs in parallel. + */ +void rhashtable_free_and_destroy(struct rhashtable *ht, + void (*free_fn)(void *ptr, void *arg), + void *arg) +{ + const struct bucket_table *tbl; + unsigned int i; + + cancel_work_sync(&ht->run_work); + + mutex_lock(&ht->mutex); + tbl = rht_dereference(ht->tbl, ht); + if (free_fn) { + for (i = 0; i < tbl->size; i++) { + struct rhash_head *pos, *next; + + for (pos = rht_dereference(tbl->buckets[i], ht), + next = !rht_is_a_nulls(pos) ? + rht_dereference(pos->next, ht) : NULL; + !rht_is_a_nulls(pos); + pos = next, + next = !rht_is_a_nulls(pos) ? + rht_dereference(pos->next, ht) : NULL) + free_fn(rht_obj(ht, pos), arg); + } + } + + bucket_table_free(tbl); + mutex_unlock(&ht->mutex); +} + +void rhashtable_destroy(struct rhashtable *ht) +{ + return rhashtable_free_and_destroy(ht, NULL, NULL); +} + diff --git a/os_dep/linux/rhashtable.h b/os_dep/linux/rhashtable.h new file mode 100644 index 0000000..a6db325 --- /dev/null +++ b/os_dep/linux/rhashtable.h @@ -0,0 +1,827 @@ +/* + * Resizable, Scalable, Concurrent Hash Table + * + * Copyright (c) 2015 Herbert Xu + * Copyright (c) 2014-2015 Thomas Graf + * Copyright (c) 2008-2014 Patrick McHardy + * + * Code partially derived from nft_hash + * Rewritten with rehash code from br_multicast plus single list + * pointer as suggested by Josh Triplett + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _LINUX_RHASHTABLE_H +#define _LINUX_RHASHTABLE_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The end of the chain is marked with a special nulls marks which has + * the following format: + * + * +-------+-----------------------------------------------------+-+ + * | Base | Hash |1| + * +-------+-----------------------------------------------------+-+ + * + * Base (4 bits) : Reserved to distinguish between multiple tables. + * Specified via &struct rhashtable_params.nulls_base. + * Hash (27 bits): Full hash (unmasked) of first element added to bucket + * 1 (1 bit) : Nulls marker (always set) + * + * The remaining bits of the next pointer remain unused for now. + */ +#define RHT_BASE_BITS 4 +#define RHT_HASH_BITS 27 +#define RHT_BASE_SHIFT RHT_HASH_BITS + +/* Base bits plus 1 bit for nulls marker */ +#define RHT_HASH_RESERVED_SPACE (RHT_BASE_BITS + 1) + +struct rhash_head { + struct rhash_head __rcu *next; +}; + +/** + * struct bucket_table - Table of hash buckets + * @size: Number of hash buckets + * @rehash: Current bucket being rehashed + * @hash_rnd: Random seed to fold into hash + * @locks_mask: Mask to apply before accessing locks[] + * @locks: Array of spinlocks protecting individual buckets + * @walkers: List of active walkers + * @rcu: RCU structure for freeing the table + * @future_tbl: Table under construction during rehashing + * @buckets: size * hash buckets + */ +struct bucket_table { + unsigned int size; + unsigned int rehash; + u32 hash_rnd; + unsigned int locks_mask; + spinlock_t *locks; + struct list_head walkers; + struct rcu_head rcu; + + struct bucket_table __rcu *future_tbl; + + struct rhash_head __rcu *buckets[] ____cacheline_aligned_in_smp; +}; + +/** + * struct rhashtable_compare_arg - Key for the function rhashtable_compare + * @ht: Hash table + * @key: Key to compare against + */ +struct rhashtable_compare_arg { + struct rhashtable *ht; + const void *key; +}; + +typedef u32 (*rht_hashfn_t)(const void *data, u32 len, u32 seed); +typedef u32 (*rht_obj_hashfn_t)(const void *data, u32 len, u32 seed); +typedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *arg, + const void *obj); + +struct rhashtable; + +/** + * struct rhashtable_params - Hash table construction parameters + * @nelem_hint: Hint on number of elements, should be 75% of desired size + * @key_len: Length of key + * @key_offset: Offset of key in struct to be hashed + * @head_offset: Offset of rhash_head in struct to be hashed + * @insecure_max_entries: Maximum number of entries (may be exceeded) + * @max_size: Maximum size while expanding + * @min_size: Minimum size while shrinking + * @nulls_base: Base value to generate nulls marker + * @insecure_elasticity: Set to true to disable chain length checks + * @automatic_shrinking: Enable automatic shrinking of tables + * @locks_mul: Number of bucket locks to allocate per cpu (default: 128) + * @hashfn: Hash function (default: jhash2 if !(key_len % 4), or jhash) + * @obj_hashfn: Function to hash object + * @obj_cmpfn: Function to compare key with object + */ +struct rhashtable_params { + size_t nelem_hint; + size_t key_len; + size_t key_offset; + size_t head_offset; + unsigned int insecure_max_entries; + unsigned int max_size; + unsigned int min_size; + u32 nulls_base; + bool insecure_elasticity; + bool automatic_shrinking; + size_t locks_mul; + rht_hashfn_t hashfn; + rht_obj_hashfn_t obj_hashfn; + rht_obj_cmpfn_t obj_cmpfn; +}; + +/** + * struct rhashtable - Hash table handle + * @tbl: Bucket table + * @nelems: Number of elements in table + * @key_len: Key length for hashfn + * @elasticity: Maximum chain length before rehash + * @p: Configuration parameters + * @run_work: Deferred worker to expand/shrink asynchronously + * @mutex: Mutex to protect current/future table swapping + * @lock: Spin lock to protect walker list + */ +struct rhashtable { + struct bucket_table __rcu *tbl; + atomic_t nelems; + unsigned int key_len; + unsigned int elasticity; + struct rhashtable_params p; + struct work_struct run_work; + struct mutex mutex; + spinlock_t lock; +}; + +/** + * struct rhashtable_walker - Hash table walker + * @list: List entry on list of walkers + * @tbl: The table that we were walking over + */ +struct rhashtable_walker { + struct list_head list; + struct bucket_table *tbl; +}; + +/** + * struct rhashtable_iter - Hash table iterator, fits into netlink cb + * @ht: Table to iterate through + * @p: Current pointer + * @walker: Associated rhashtable walker + * @slot: Current slot + * @skip: Number of entries to skip in slot + */ +struct rhashtable_iter { + struct rhashtable *ht; + struct rhash_head *p; + struct rhashtable_walker *walker; + unsigned int slot; + unsigned int skip; +}; + +static inline unsigned long rht_marker(const struct rhashtable *ht, u32 hash) +{ + return NULLS_MARKER(ht->p.nulls_base + hash); +} + +#define INIT_RHT_NULLS_HEAD(ptr, ht, hash) \ + ((ptr) = (typeof(ptr)) rht_marker(ht, hash)) + +static inline bool rht_is_a_nulls(const struct rhash_head *ptr) +{ + return ((unsigned long) ptr & 1); +} + +static inline unsigned long rht_get_nulls_value(const struct rhash_head *ptr) +{ + return ((unsigned long) ptr) >> 1; +} + +static inline void *rht_obj(const struct rhashtable *ht, + const struct rhash_head *he) +{ + return (char *)he - ht->p.head_offset; +} + +static inline unsigned int rht_bucket_index(const struct bucket_table *tbl, + unsigned int hash) +{ + return (hash >> RHT_HASH_RESERVED_SPACE) & (tbl->size - 1); +} + +static inline unsigned int rht_key_hashfn( + struct rhashtable *ht, const struct bucket_table *tbl, + const void *key, const struct rhashtable_params params) +{ + unsigned int hash; + + /* params must be equal to ht->p if it isn't constant. */ + if (!__builtin_constant_p(params.key_len)) + hash = ht->p.hashfn(key, ht->key_len, tbl->hash_rnd); + else if (params.key_len) { + unsigned int key_len = params.key_len; + + if (params.hashfn) + hash = params.hashfn(key, key_len, tbl->hash_rnd); + else if (key_len & (sizeof(u32) - 1)) + hash = jhash(key, key_len, tbl->hash_rnd); + else + hash = jhash2(key, key_len / sizeof(u32), + tbl->hash_rnd); + } else { + unsigned int key_len = ht->p.key_len; + + if (params.hashfn) + hash = params.hashfn(key, key_len, tbl->hash_rnd); + else + hash = jhash(key, key_len, tbl->hash_rnd); + } + + return rht_bucket_index(tbl, hash); +} + +static inline unsigned int rht_head_hashfn( + struct rhashtable *ht, const struct bucket_table *tbl, + const struct rhash_head *he, const struct rhashtable_params params) +{ + const char *ptr = rht_obj(ht, he); + + return likely(params.obj_hashfn) ? + rht_bucket_index(tbl, params.obj_hashfn(ptr, params.key_len ?: + ht->p.key_len, + tbl->hash_rnd)) : + rht_key_hashfn(ht, tbl, ptr + params.key_offset, params); +} + +/** + * rht_grow_above_75 - returns true if nelems > 0.75 * table-size + * @ht: hash table + * @tbl: current table + */ +static inline bool rht_grow_above_75(const struct rhashtable *ht, + const struct bucket_table *tbl) +{ + /* Expand table when exceeding 75% load */ + return atomic_read(&ht->nelems) > (tbl->size / 4 * 3) && + (!ht->p.max_size || tbl->size < ht->p.max_size); +} + +/** + * rht_shrink_below_30 - returns true if nelems < 0.3 * table-size + * @ht: hash table + * @tbl: current table + */ +static inline bool rht_shrink_below_30(const struct rhashtable *ht, + const struct bucket_table *tbl) +{ + /* Shrink table beneath 30% load */ + return atomic_read(&ht->nelems) < (tbl->size * 3 / 10) && + tbl->size > ht->p.min_size; +} + +/** + * rht_grow_above_100 - returns true if nelems > table-size + * @ht: hash table + * @tbl: current table + */ +static inline bool rht_grow_above_100(const struct rhashtable *ht, + const struct bucket_table *tbl) +{ + return atomic_read(&ht->nelems) > tbl->size && + (!ht->p.max_size || tbl->size < ht->p.max_size); +} + +/** + * rht_grow_above_max - returns true if table is above maximum + * @ht: hash table + * @tbl: current table + */ +static inline bool rht_grow_above_max(const struct rhashtable *ht, + const struct bucket_table *tbl) +{ + return ht->p.insecure_max_entries && + atomic_read(&ht->nelems) >= ht->p.insecure_max_entries; +} + +/* The bucket lock is selected based on the hash and protects mutations + * on a group of hash buckets. + * + * A maximum of tbl->size/2 bucket locks is allocated. This ensures that + * a single lock always covers both buckets which may both contains + * entries which link to the same bucket of the old table during resizing. + * This allows to simplify the locking as locking the bucket in both + * tables during resize always guarantee protection. + * + * IMPORTANT: When holding the bucket lock of both the old and new table + * during expansions and shrinking, the old bucket lock must always be + * acquired first. + */ +static inline spinlock_t *rht_bucket_lock(const struct bucket_table *tbl, + unsigned int hash) +{ + return &tbl->locks[hash & tbl->locks_mask]; +} + +#ifdef CONFIG_PROVE_LOCKING +int lockdep_rht_mutex_is_held(struct rhashtable *ht); +int lockdep_rht_bucket_is_held(const struct bucket_table *tbl, u32 hash); +#else +static inline int lockdep_rht_mutex_is_held(struct rhashtable *ht) +{ + return 1; +} + +static inline int lockdep_rht_bucket_is_held(const struct bucket_table *tbl, + u32 hash) +{ + return 1; +} +#endif /* CONFIG_PROVE_LOCKING */ + +int rhashtable_init(struct rhashtable *ht, + const struct rhashtable_params *params); + +struct bucket_table *rhashtable_insert_slow(struct rhashtable *ht, + const void *key, + struct rhash_head *obj, + struct bucket_table *old_tbl); +int rhashtable_insert_rehash(struct rhashtable *ht, struct bucket_table *tbl); + +int rhashtable_walk_init(struct rhashtable *ht, struct rhashtable_iter *iter); +void rhashtable_walk_exit(struct rhashtable_iter *iter); +int rhashtable_walk_start(struct rhashtable_iter *iter) __acquires(RCU); +void *rhashtable_walk_next(struct rhashtable_iter *iter); +void rhashtable_walk_stop(struct rhashtable_iter *iter) __releases(RCU); + +void rhashtable_free_and_destroy(struct rhashtable *ht, + void (*free_fn)(void *ptr, void *arg), + void *arg); +void rhashtable_destroy(struct rhashtable *ht); + +#define rht_dereference(p, ht) \ + rcu_dereference_protected(p, lockdep_rht_mutex_is_held(ht)) + +#define rht_dereference_rcu(p, ht) \ + rcu_dereference_check(p, lockdep_rht_mutex_is_held(ht)) + +#define rht_dereference_bucket(p, tbl, hash) \ + rcu_dereference_protected(p, lockdep_rht_bucket_is_held(tbl, hash)) + +#define rht_dereference_bucket_rcu(p, tbl, hash) \ + rcu_dereference_check(p, lockdep_rht_bucket_is_held(tbl, hash)) + +#define rht_entry(tpos, pos, member) \ + ({ tpos = container_of(pos, typeof(*tpos), member); 1; }) + +/** + * rht_for_each_continue - continue iterating over hash chain + * @pos: the &struct rhash_head to use as a loop cursor. + * @head: the previous &struct rhash_head to continue from + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + */ +#define rht_for_each_continue(pos, head, tbl, hash) \ + for (pos = rht_dereference_bucket(head, tbl, hash); \ + !rht_is_a_nulls(pos); \ + pos = rht_dereference_bucket((pos)->next, tbl, hash)) + +/** + * rht_for_each - iterate over hash chain + * @pos: the &struct rhash_head to use as a loop cursor. + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + */ +#define rht_for_each(pos, tbl, hash) \ + rht_for_each_continue(pos, (tbl)->buckets[hash], tbl, hash) + +/** + * rht_for_each_entry_continue - continue iterating over hash chain + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct rhash_head to use as a loop cursor. + * @head: the previous &struct rhash_head to continue from + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * @member: name of the &struct rhash_head within the hashable struct. + */ +#define rht_for_each_entry_continue(tpos, pos, head, tbl, hash, member) \ + for (pos = rht_dereference_bucket(head, tbl, hash); \ + (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member); \ + pos = rht_dereference_bucket((pos)->next, tbl, hash)) + +/** + * rht_for_each_entry - iterate over hash chain of given type + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct rhash_head to use as a loop cursor. + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * @member: name of the &struct rhash_head within the hashable struct. + */ +#define rht_for_each_entry(tpos, pos, tbl, hash, member) \ + rht_for_each_entry_continue(tpos, pos, (tbl)->buckets[hash], \ + tbl, hash, member) + +/** + * rht_for_each_entry_safe - safely iterate over hash chain of given type + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct rhash_head to use as a loop cursor. + * @next: the &struct rhash_head to use as next in loop cursor. + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * @member: name of the &struct rhash_head within the hashable struct. + * + * This hash chain list-traversal primitive allows for the looped code to + * remove the loop cursor from the list. + */ +#define rht_for_each_entry_safe(tpos, pos, next, tbl, hash, member) \ + for (pos = rht_dereference_bucket((tbl)->buckets[hash], tbl, hash), \ + next = !rht_is_a_nulls(pos) ? \ + rht_dereference_bucket(pos->next, tbl, hash) : NULL; \ + (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member); \ + pos = next, \ + next = !rht_is_a_nulls(pos) ? \ + rht_dereference_bucket(pos->next, tbl, hash) : NULL) + +/** + * rht_for_each_rcu_continue - continue iterating over rcu hash chain + * @pos: the &struct rhash_head to use as a loop cursor. + * @head: the previous &struct rhash_head to continue from + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * + * This hash chain list-traversal primitive may safely run concurrently with + * the _rcu mutation primitives such as rhashtable_insert() as long as the + * traversal is guarded by rcu_read_lock(). + */ +#define rht_for_each_rcu_continue(pos, head, tbl, hash) \ + for (({barrier(); }), \ + pos = rht_dereference_bucket_rcu(head, tbl, hash); \ + !rht_is_a_nulls(pos); \ + pos = rcu_dereference_raw(pos->next)) + +/** + * rht_for_each_rcu - iterate over rcu hash chain + * @pos: the &struct rhash_head to use as a loop cursor. + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * + * This hash chain list-traversal primitive may safely run concurrently with + * the _rcu mutation primitives such as rhashtable_insert() as long as the + * traversal is guarded by rcu_read_lock(). + */ +#define rht_for_each_rcu(pos, tbl, hash) \ + rht_for_each_rcu_continue(pos, (tbl)->buckets[hash], tbl, hash) + +/** + * rht_for_each_entry_rcu_continue - continue iterating over rcu hash chain + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct rhash_head to use as a loop cursor. + * @head: the previous &struct rhash_head to continue from + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * @member: name of the &struct rhash_head within the hashable struct. + * + * This hash chain list-traversal primitive may safely run concurrently with + * the _rcu mutation primitives such as rhashtable_insert() as long as the + * traversal is guarded by rcu_read_lock(). + */ +#define rht_for_each_entry_rcu_continue(tpos, pos, head, tbl, hash, member) \ + for (({barrier(); }), \ + pos = rht_dereference_bucket_rcu(head, tbl, hash); \ + (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member); \ + pos = rht_dereference_bucket_rcu(pos->next, tbl, hash)) + +/** + * rht_for_each_entry_rcu - iterate over rcu hash chain of given type + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct rhash_head to use as a loop cursor. + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * @member: name of the &struct rhash_head within the hashable struct. + * + * This hash chain list-traversal primitive may safely run concurrently with + * the _rcu mutation primitives such as rhashtable_insert() as long as the + * traversal is guarded by rcu_read_lock(). + */ +#define rht_for_each_entry_rcu(tpos, pos, tbl, hash, member) \ + rht_for_each_entry_rcu_continue(tpos, pos, (tbl)->buckets[hash],\ + tbl, hash, member) + +static inline int rhashtable_compare(struct rhashtable_compare_arg *arg, + const void *obj) +{ + struct rhashtable *ht = arg->ht; + const char *ptr = obj; + + return memcmp(ptr + ht->p.key_offset, arg->key, ht->p.key_len); +} + +/** + * rhashtable_lookup_fast - search hash table, inlined version + * @ht: hash table + * @key: the pointer to the key + * @params: hash table parameters + * + * Computes the hash value for the key and traverses the bucket chain looking + * for a entry with an identical key. The first matching entry is returned. + * + * Returns the first entry on which the compare function returned true. + */ +static inline void *rhashtable_lookup_fast( + struct rhashtable *ht, const void *key, + const struct rhashtable_params params) +{ + struct rhashtable_compare_arg arg = { + .ht = ht, + .key = key, + }; + const struct bucket_table *tbl; + struct rhash_head *he; + unsigned int hash; + + rcu_read_lock(); + + tbl = rht_dereference_rcu(ht->tbl, ht); +restart: + hash = rht_key_hashfn(ht, tbl, key, params); + rht_for_each_rcu(he, tbl, hash) { + if (params.obj_cmpfn ? + params.obj_cmpfn(&arg, rht_obj(ht, he)) : + rhashtable_compare(&arg, rht_obj(ht, he))) + continue; + rcu_read_unlock(); + return rht_obj(ht, he); + } + + /* Ensure we see any new tables. */ + smp_rmb(); + + tbl = rht_dereference_rcu(tbl->future_tbl, ht); + if (unlikely(tbl)) + goto restart; + rcu_read_unlock(); + + return NULL; +} + +/* Internal function, please use rhashtable_insert_fast() instead */ +static inline int __rhashtable_insert_fast( + struct rhashtable *ht, const void *key, struct rhash_head *obj, + const struct rhashtable_params params) +{ + struct rhashtable_compare_arg arg = { + .ht = ht, + .key = key, + }; + struct bucket_table *tbl, *new_tbl; + struct rhash_head *head; + spinlock_t *lock; + unsigned int elasticity; + unsigned int hash; + int err; + +restart: + rcu_read_lock(); + + tbl = rht_dereference_rcu(ht->tbl, ht); + + /* All insertions must grab the oldest table containing + * the hashed bucket that is yet to be rehashed. + */ + for (;;) { + hash = rht_head_hashfn(ht, tbl, obj, params); + lock = rht_bucket_lock(tbl, hash); + spin_lock_bh(lock); + + if (tbl->rehash <= hash) + break; + + spin_unlock_bh(lock); + tbl = rht_dereference_rcu(tbl->future_tbl, ht); + } + + new_tbl = rht_dereference_rcu(tbl->future_tbl, ht); + if (unlikely(new_tbl)) { + tbl = rhashtable_insert_slow(ht, key, obj, new_tbl); + if (!IS_ERR_OR_NULL(tbl)) + goto slow_path; + + err = PTR_ERR(tbl); + goto out; + } + + err = -E2BIG; + if (unlikely(rht_grow_above_max(ht, tbl))) + goto out; + + if (unlikely(rht_grow_above_100(ht, tbl))) { +slow_path: + spin_unlock_bh(lock); + err = rhashtable_insert_rehash(ht, tbl); + rcu_read_unlock(); + if (err) + return err; + + goto restart; + } + + err = -EEXIST; + elasticity = ht->elasticity; + rht_for_each(head, tbl, hash) { + if (key && + unlikely(!(params.obj_cmpfn ? + params.obj_cmpfn(&arg, rht_obj(ht, head)) : + rhashtable_compare(&arg, rht_obj(ht, head))))) + goto out; + if (!--elasticity) + goto slow_path; + } + + err = 0; + + head = rht_dereference_bucket(tbl->buckets[hash], tbl, hash); + + RCU_INIT_POINTER(obj->next, head); + + rcu_assign_pointer(tbl->buckets[hash], obj); + + atomic_inc(&ht->nelems); + if (rht_grow_above_75(ht, tbl)) + schedule_work(&ht->run_work); + +out: + spin_unlock_bh(lock); + rcu_read_unlock(); + + return err; +} + +/** + * rhashtable_insert_fast - insert object into hash table + * @ht: hash table + * @obj: pointer to hash head inside object + * @params: hash table parameters + * + * Will take a per bucket spinlock to protect against mutual mutations + * on the same bucket. Multiple insertions may occur in parallel unless + * they map to the same bucket lock. + * + * It is safe to call this function from atomic context. + * + * Will trigger an automatic deferred table resizing if the size grows + * beyond the watermark indicated by grow_decision() which can be passed + * to rhashtable_init(). + */ +static inline int rhashtable_insert_fast( + struct rhashtable *ht, struct rhash_head *obj, + const struct rhashtable_params params) +{ + return __rhashtable_insert_fast(ht, NULL, obj, params); +} + +/** + * rhashtable_lookup_insert_fast - lookup and insert object into hash table + * @ht: hash table + * @obj: pointer to hash head inside object + * @params: hash table parameters + * + * Locks down the bucket chain in both the old and new table if a resize + * is in progress to ensure that writers can't remove from the old table + * and can't insert to the new table during the atomic operation of search + * and insertion. Searches for duplicates in both the old and new table if + * a resize is in progress. + * + * This lookup function may only be used for fixed key hash table (key_len + * parameter set). It will BUG() if used inappropriately. + * + * It is safe to call this function from atomic context. + * + * Will trigger an automatic deferred table resizing if the size grows + * beyond the watermark indicated by grow_decision() which can be passed + * to rhashtable_init(). + */ +static inline int rhashtable_lookup_insert_fast( + struct rhashtable *ht, struct rhash_head *obj, + const struct rhashtable_params params) +{ + const char *key = rht_obj(ht, obj); + + BUG_ON(ht->p.obj_hashfn); + + return __rhashtable_insert_fast(ht, key + ht->p.key_offset, obj, + params); +} + +/** + * rhashtable_lookup_insert_key - search and insert object to hash table + * with explicit key + * @ht: hash table + * @key: key + * @obj: pointer to hash head inside object + * @params: hash table parameters + * + * Locks down the bucket chain in both the old and new table if a resize + * is in progress to ensure that writers can't remove from the old table + * and can't insert to the new table during the atomic operation of search + * and insertion. Searches for duplicates in both the old and new table if + * a resize is in progress. + * + * Lookups may occur in parallel with hashtable mutations and resizing. + * + * Will trigger an automatic deferred table resizing if the size grows + * beyond the watermark indicated by grow_decision() which can be passed + * to rhashtable_init(). + * + * Returns zero on success. + */ +static inline int rhashtable_lookup_insert_key( + struct rhashtable *ht, const void *key, struct rhash_head *obj, + const struct rhashtable_params params) +{ + BUG_ON(!ht->p.obj_hashfn || !key); + + return __rhashtable_insert_fast(ht, key, obj, params); +} + +/* Internal function, please use rhashtable_remove_fast() instead */ +static inline int __rhashtable_remove_fast( + struct rhashtable *ht, struct bucket_table *tbl, + struct rhash_head *obj, const struct rhashtable_params params) +{ + struct rhash_head __rcu **pprev; + struct rhash_head *he; + spinlock_t * lock; + unsigned int hash; + int err = -ENOENT; + + hash = rht_head_hashfn(ht, tbl, obj, params); + lock = rht_bucket_lock(tbl, hash); + + spin_lock_bh(lock); + + pprev = &tbl->buckets[hash]; + rht_for_each(he, tbl, hash) { + if (he != obj) { + pprev = &he->next; + continue; + } + + rcu_assign_pointer(*pprev, obj->next); + err = 0; + break; + } + + spin_unlock_bh(lock); + + return err; +} + +/** + * rhashtable_remove_fast - remove object from hash table + * @ht: hash table + * @obj: pointer to hash head inside object + * @params: hash table parameters + * + * Since the hash chain is single linked, the removal operation needs to + * walk the bucket chain upon removal. The removal operation is thus + * considerable slow if the hash table is not correctly sized. + * + * Will automatically shrink the table via rhashtable_expand() if the + * shrink_decision function specified at rhashtable_init() returns true. + * + * Returns zero on success, -ENOENT if the entry could not be found. + */ +static inline int rhashtable_remove_fast( + struct rhashtable *ht, struct rhash_head *obj, + const struct rhashtable_params params) +{ + struct bucket_table *tbl; + int err; + + rcu_read_lock(); + + tbl = rht_dereference_rcu(ht->tbl, ht); + + /* Because we have already taken (and released) the bucket + * lock in old_tbl, if we find that future_tbl is not yet + * visible then that guarantees the entry to still be in + * the old tbl if it exists. + */ + while ((err = __rhashtable_remove_fast(ht, tbl, obj, params)) && + (tbl = rht_dereference_rcu(tbl->future_tbl, ht))) + ; + + if (err) + goto out; + + atomic_dec(&ht->nelems); + if (unlikely(ht->p.automatic_shrinking && + rht_shrink_below_30(ht, tbl))) + schedule_work(&ht->run_work); + +out: + rcu_read_unlock(); + + return err; +} + +#endif /* _LINUX_RHASHTABLE_H */ + diff --git a/os_dep/linux/rtw_rhashtable.c b/os_dep/linux/rtw_rhashtable.c new file mode 100644 index 0000000..4d51f04 --- /dev/null +++ b/os_dep/linux/rtw_rhashtable.c @@ -0,0 +1,74 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifdef CONFIG_RTW_MESH /* for now, only promised for kernel versions we support mesh */ + +#include + +int rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) + return rhashtable_walk_init((ht), (iter), GFP_ATOMIC); +#else + /* kernel >= 4.4.0 rhashtable_walk_init use GFP_KERNEL to alloc, spin_lock for assignment */ + iter->ht = ht; + iter->p = NULL; + iter->slot = 0; + iter->skip = 0; + + iter->walker = kmalloc(sizeof(*iter->walker), GFP_ATOMIC); + if (!iter->walker) + return -ENOMEM; + + spin_lock(&ht->lock); + iter->walker->tbl = + rcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock)); + list_add(&iter->walker->list, &iter->walker->tbl->walkers); + spin_unlock(&ht->lock); + + return 0; +#endif +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) +static inline int is_vmalloc_addr(const void *x) +{ +#ifdef CONFIG_MMU + unsigned long addr = (unsigned long)x; + + return addr >= VMALLOC_START && addr < VMALLOC_END; +#else + return 0; +#endif +} +#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) */ + +void kvfree(const void *addr) +{ + if (is_vmalloc_addr(addr)) + vfree(addr); + else + kfree(addr); +} +#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) */ + +#include "rhashtable.c" + +#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */ + +#endif /* CONFIG_RTW_MESH */ + diff --git a/os_dep/linux/rtw_rhashtable.h b/os_dep/linux/rtw_rhashtable.h new file mode 100644 index 0000000..567ab39 --- /dev/null +++ b/os_dep/linux/rtw_rhashtable.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_RHASHTABLE_H__ +#define __RTW_RHASHTABLE_H__ + +#ifdef CONFIG_RTW_MESH /* for now, only promised for kernel versions we support mesh */ + +/* directly reference rhashtable in kernel */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) +#include +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) */ + +/* Use rhashtable from kernel 4.4 */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)) +#define NULLS_MARKER(value) (1UL | (((long)value) << 1)) +#endif +#include "rhashtable.h" +#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */ + +typedef struct rhashtable rtw_rhashtable; +typedef struct rhash_head rtw_rhash_head; +typedef struct rhashtable_params rtw_rhashtable_params; + +#define rtw_rhashtable_init(ht, params) rhashtable_init(ht, params) + +typedef struct rhashtable_iter rtw_rhashtable_iter; + +int rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter); +#define rtw_rhashtable_walk_exit(iter) rhashtable_walk_exit(iter) +#define rtw_rhashtable_walk_start(iter) rhashtable_walk_start(iter) +#define rtw_rhashtable_walk_next(iter) rhashtable_walk_next(iter) +#define rtw_rhashtable_walk_stop(iter) rhashtable_walk_stop(iter) + +#define rtw_rhashtable_free_and_destroy(ht, free_fn, arg) rhashtable_free_and_destroy((ht), (free_fn), (arg)) +#define rtw_rhashtable_lookup_fast(ht, key, params) rhashtable_lookup_fast((ht), (key), (params)) +#define rtw_rhashtable_lookup_insert_fast(ht, obj, params) rhashtable_lookup_insert_fast((ht), (obj), (params)) +#define rtw_rhashtable_remove_fast(ht, obj, params) rhashtable_remove_fast((ht), (obj), (params)) + +#endif /* CONFIG_RTW_MESH */ + +#endif /* __RTW_RHASHTABLE_H__ */ + diff --git a/platform/platform_aml_s905_sdio.c b/platform/platform_aml_s905_sdio.c new file mode 100644 index 0000000..334ca03 --- /dev/null +++ b/platform/platform_aml_s905_sdio.c @@ -0,0 +1,54 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include /* pr_info(() */ +#include /* msleep() */ +#include "platform_aml_s905_sdio.h" /* sdio_reinit() and etc */ + + +/* + * Return: + * 0: power on successfully + * others: power on failed + */ +int platform_wifi_power_on(void) +{ + int ret = 0; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + ret = wifi_setup_dt(); + if (ret) { + pr_err("%s: setup dt failed!!(%d)\n", __func__, ret); + return -1; + } +#endif /* kernel < 3.14.0 */ + +#if 0 /* Seems redundancy? Already done before insert driver */ + pr_info("######%s:\n", __func__); + extern_wifi_set_enable(0); + msleep(500); + extern_wifi_set_enable(1); + msleep(500); + sdio_reinit(); +#endif + + return ret; +} + +void platform_wifi_power_off(void) +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + wifi_teardown_dt(); +#endif /* kernel < 3.14.0 */ +} diff --git a/platform/platform_aml_s905_sdio.h b/platform/platform_aml_s905_sdio.h new file mode 100644 index 0000000..2b87576 --- /dev/null +++ b/platform/platform_aml_s905_sdio.h @@ -0,0 +1,28 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PLATFORM_AML_S905_SDIO_H__ +#define __PLATFORM_AML_S905_SDIO_H__ + +#include /* Linux vresion */ + +extern void sdio_reinit(void); +extern void extern_wifi_set_enable(int is_on); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) +extern void wifi_teardown_dt(void); +extern int wifi_setup_dt(void); +#endif /* kernel < 3.14.0 */ + +#endif /* __PLATFORM_AML_S905_SDIO_H__ */ diff --git a/platform/platform_hisilicon_hi3798_sdio.c b/platform/platform_hisilicon_hi3798_sdio.c new file mode 100644 index 0000000..11a0832 --- /dev/null +++ b/platform/platform_hisilicon_hi3798_sdio.c @@ -0,0 +1,110 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include /* mdelay() */ +#include /* __io_address(), readl(), writel() */ +#include "platform_hisilicon_hi3798_sdio.h" /* HI_S32() and etc. */ + +typedef enum hi_GPIO_DIR_E { + HI_DIR_OUT = 0, + HI_DIR_IN = 1, +} HI_GPIO_DIR_E; + +#define RTL_REG_ON_GPIO (4*8 + 3) + +#define REG_BASE_CTRL __io_address(0xf8a20008) + +int gpio_wlan_reg_on = RTL_REG_ON_GPIO; +#if 0 +module_param(gpio_wlan_reg_on, uint, 0644); +MODULE_PARM_DESC(gpio_wlan_reg_on, "wlan reg_on gpio num (default:gpio4_3)"); +#endif + +static int hi_gpio_set_value(u32 gpio, u32 value) +{ + HI_S32 s32Status; + + s32Status = HI_DRV_GPIO_SetDirBit(gpio, HI_DIR_OUT); + if (s32Status != HI_SUCCESS) { + pr_err("gpio(%d) HI_DRV_GPIO_SetDirBit HI_DIR_OUT failed\n", + gpio); + return -1; + } + + s32Status = HI_DRV_GPIO_WriteBit(gpio, value); + if (s32Status != HI_SUCCESS) { + pr_err("gpio(%d) HI_DRV_GPIO_WriteBit value(%d) failed\n", + gpio, value); + return -1; + } + + return 0; +} + +static int hisi_wlan_set_carddetect(bool present) +{ + u32 regval; + u32 mask; + + +#ifndef CONFIG_HISI_SDIO_ID + return; +#endif + pr_info("SDIO ID=%d\n", CONFIG_HISI_SDIO_ID); +#if (CONFIG_HISI_SDIO_ID == 1) + mask = 1; +#elif (CONFIG_HISI_SDIO_ID == 0) + mask = 2; +#endif + + regval = readl(REG_BASE_CTRL); + if (present) { + pr_info("====== Card detection to detect SDIO card! ======\n"); + /* set card_detect low to detect card */ + regval |= mask; + } else { + pr_info("====== Card detection to remove SDIO card! ======\n"); + /* set card_detect high to remove card */ + regval &= ~(mask); + } + writel(regval, REG_BASE_CTRL); + + return 0; +} + +/* + * Return: + * 0: power on successfully + * others: power on failed + */ +int platform_wifi_power_on(void) +{ + int ret = 0; + + + hi_gpio_set_value(gpio_wlan_reg_on, 1); + mdelay(100); + hisi_wlan_set_carddetect(1); + mdelay(2000); + pr_info("======== set_carddetect delay 2s! ========\n"); + + return ret; +} + +void platform_wifi_power_off(void) +{ + hisi_wlan_set_carddetect(0); + mdelay(100); + hi_gpio_set_value(gpio_wlan_reg_on, 0); +} diff --git a/platform/platform_hisilicon_hi3798_sdio.h b/platform/platform_hisilicon_hi3798_sdio.h new file mode 100644 index 0000000..1ad4240 --- /dev/null +++ b/platform/platform_hisilicon_hi3798_sdio.h @@ -0,0 +1,28 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PLATFORM_HISILICON_HI3798_SDIO_H__ +#define __PLATFORM_HISILICON_HI3798_SDIO_H__ + +typedef unsigned int HI_U32; + +typedef int HI_S32; + +#define HI_SUCCESS 0 +#define HI_FAILURE (-1) + +extern HI_S32 HI_DRV_GPIO_SetDirBit(HI_U32 u32GpioNo, HI_U32 u32DirBit); +extern HI_S32 HI_DRV_GPIO_WriteBit(HI_U32 u32GpioNo, HI_U32 u32BitValue); + +#endif /* __PLATFORM_HISILICON_HI3798_SDIO_H__ */ diff --git a/platform/platform_zte_zx296716_sdio.c b/platform/platform_zte_zx296716_sdio.c new file mode 100644 index 0000000..472d24d --- /dev/null +++ b/platform/platform_zte_zx296716_sdio.c @@ -0,0 +1,53 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include /* pr_info(() */ +#include /* msleep() */ +#include "platform_zte_zx296716_sdio.h" /* sdio_reinit() and etc */ + + +/* + * Return: + * 0: power on successfully + * others: power on failed + */ +int platform_wifi_power_on(void) +{ + int ret = 0; + + pr_info("######%s: disable--1--\n", __func__); + extern_wifi_set_enable(0); + /*msleep(500);*/ /* add in function:extern_wifi_set_enable */ + pr_info("######%s: enable--2---\n", __func__); + extern_wifi_set_enable(1); + /*msleep(500);*/ + sdio_reinit(); + + return ret; +} + +void platform_wifi_power_off(void) +{ + int card_val; + + pr_info("######%s:\n", __func__); +#ifdef CONFIG_A16T03_BOARD + card_val = sdio_host_is_null(); + if (card_val) + remove_card(); +#endif /* CONFIG_A16T03_BOARD */ + extern_wifi_set_enable(0); + + /*msleep(500);*/ +} diff --git a/platform/platform_zte_zx296716_sdio.h b/platform/platform_zte_zx296716_sdio.h new file mode 100644 index 0000000..3a4fba1 --- /dev/null +++ b/platform/platform_zte_zx296716_sdio.h @@ -0,0 +1,25 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PLATFORM_ZTE_ZX296716_SDIO_H__ +#define __PLATFORM_ZTE_ZX296716_SDIO_H__ + +extern void sdio_reinit(void); +extern void extern_wifi_set_enable(int val); +#ifdef CONFIG_A16T03_BOARD +extern int sdio_host_is_null(void); +extern void remove_card(void); +#endif /* CONFIG_A16T03_BOARD */ + +#endif /* __PLATFORM_ZTE_ZX296716_SDIO_H__ */ From c0035afd64c5957f3a46654905bb0d42e8f932a1 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Sun, 7 Oct 2018 13:56:16 +0200 Subject: [PATCH 14/48] improve 4.19 fix --- Makefile | 5 +++-- include/wifi.h | 7 ++++--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index 60370cc..c326a80 100644 --- a/Makefile +++ b/Makefile @@ -95,11 +95,12 @@ CONFIG_RTW_SDIO_PM_KEEP_POWER = y ###################### MP HW TX MODE FOR VHT ####################### CONFIG_MP_VHT_HW_TX_MODE = n ###################### Platform Related ####################### -CONFIG_PLATFORM_I386_PC = y +CONFIG_PLATFORM_I386_PC = n +CONFIG_PLATFORM_ARM_RPI = n CONFIG_PLATFORM_ANDROID_X86 = n CONFIG_PLATFORM_ANDROID_INTEL_X86 = n CONFIG_PLATFORM_JB_X86 = n -CONFIG_PLATFORM_ARM_S3C2K4 = n +CONFIG_PLATFORM_ARM_S3C2K4 = y CONFIG_PLATFORM_ARM_PXA2XX = n CONFIG_PLATFORM_ARM_S3C6K4 = n CONFIG_PLATFORM_MIPS_RMI = n diff --git a/include/wifi.h b/include/wifi.h index 979860d..5e28044 100644 --- a/include/wifi.h +++ b/include/wifi.h @@ -1027,9 +1027,10 @@ typedef enum _HT_CAP_AMPDU_DENSITY { * A-PMDU buffer sizes * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2) */ -//#define IEEE80211_MIN_AMPDU_BUF 0x8 -//#define IEEE80211_MAX_AMPDU_BUF 0x40 - +#define IEEE80211_MIN_AMPDU_BUF 0x8 +if (LINUX_VERSION_CODE < KERNEL_VERSION(4,19,0)) + #define IEEE80211_MAX_AMPDU_BUF 0x40 +#endif /* Spatial Multiplexing Power Save Modes */ #define WLAN_HT_CAP_SM_PS_STATIC 0 From 3a695a5ee5c7ed960272ebe0af914146c934f176 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Sun, 7 Oct 2018 14:01:55 +0200 Subject: [PATCH 15/48] added ARM_RPI once more, please test --- Makefile | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index c326a80..08b5a49 100644 --- a/Makefile +++ b/Makefile @@ -95,12 +95,12 @@ CONFIG_RTW_SDIO_PM_KEEP_POWER = y ###################### MP HW TX MODE FOR VHT ####################### CONFIG_MP_VHT_HW_TX_MODE = n ###################### Platform Related ####################### -CONFIG_PLATFORM_I386_PC = n +CONFIG_PLATFORM_I386_PC = y CONFIG_PLATFORM_ARM_RPI = n CONFIG_PLATFORM_ANDROID_X86 = n CONFIG_PLATFORM_ANDROID_INTEL_X86 = n CONFIG_PLATFORM_JB_X86 = n -CONFIG_PLATFORM_ARM_S3C2K4 = y +CONFIG_PLATFORM_ARM_S3C2K4 = n CONFIG_PLATFORM_ARM_PXA2XX = n CONFIG_PLATFORM_ARM_S3C6K4 = n CONFIG_PLATFORM_MIPS_RMI = n @@ -1041,6 +1041,18 @@ INSTALL_PREFIX := STAGINGMODDIR := /lib/modules/$(KVER)/kernel/drivers/staging endif +ifeq ($(CONFIG_PLATFORM_ARM_RPI), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +EXTRA_CFLAGS += -DPLATFORM_LINUX +ARCH ?= arm +CROSS_COMPILE ?= +KVER ?= $(shell uname -r) +KSRC := /lib/modules/$(KVER)/build +MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/ +INSTALL_PREFIX := +endif + ifeq ($(CONFIG_PLATFORM_NV_TK1), y) EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1 EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN From 3adbe92d576fec1d58d2ad03a02ef56ce77a6106 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Sun, 7 Oct 2018 15:40:26 +0200 Subject: [PATCH 16/48] fix missing # --- include/wifi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/wifi.h b/include/wifi.h index 5e28044..dfa59d4 100644 --- a/include/wifi.h +++ b/include/wifi.h @@ -1028,7 +1028,7 @@ typedef enum _HT_CAP_AMPDU_DENSITY { * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2) */ #define IEEE80211_MIN_AMPDU_BUF 0x8 -if (LINUX_VERSION_CODE < KERNEL_VERSION(4,19,0)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,19,0)) #define IEEE80211_MAX_AMPDU_BUF 0x40 #endif From a60aa88140a76aae946c3bfbafc757097a58f63b Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Wed, 26 Dec 2018 18:23:57 +0200 Subject: [PATCH 17/48] Kernel 4.20 fix --- Makefile | 2 ++ os_dep/linux/ioctl_cfg80211.c | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 08b5a49..375c3f4 100644 --- a/Makefile +++ b/Makefile @@ -20,6 +20,8 @@ ifeq ($(GCC_VER_49),1) EXTRA_CFLAGS += -Wno-date-time # Fix compile error && warning on gcc 4.9 and later endif +EXTRA_CFLAGS += -Wno-vla + EXTRA_CFLAGS += -I$(src)/include EXTRA_LDFLAGS += --strip-debug diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index e7e8930..5c7311d 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -688,7 +688,11 @@ static u64 rtw_get_systime_us(void) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) struct timespec ts; - get_monotonic_boottime(&ts); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)) + getboottime(&ts); + #else + get_monotonic_boottime(&ts); + #endif return ((u64)ts.tv_sec * 1000000) + ts.tv_nsec / 1000; #else struct timeval tv; From 5630b13e1076aeec410ad184f97f4cdf8bf8ddb8 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Sat, 5 Jan 2019 21:35:38 +0200 Subject: [PATCH 18/48] Added support for TP-Link Archer T4U V3 1300Mbps --- os_dep/linux/usb_intf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/os_dep/linux/usb_intf.c b/os_dep/linux/usb_intf.c index 7e764f3..ff2b83a 100644 --- a/os_dep/linux/usb_intf.c +++ b/os_dep/linux/usb_intf.c @@ -243,6 +243,7 @@ static struct usb_device_id rtw_usb_id_tbl[] = { {USB_DEVICE(0x0b05, 0x184c), .driver_info = RTL8822B}, /* ASUS USB AC53 */ {USB_DEVICE(0x7392, 0xC822), .driver_info = RTL8822B}, /* Edimax - EW-7822UTC */ {USB_DEVICE(0x2001, 0x331c), .driver_info = RTL8822B}, /* D-Link - DWA-182 Rev D */ + {USB_DEVICE(0x2357, 0x0115), .driver_info = RTL8822B}, /* Archer USB T4Uv3 */ /*=== Customer ID ===*/ {USB_DEVICE_AND_INTERFACE_INFO(0x13b1, 0x0043, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Alpha - Alpha*/ #endif /* CONFIG_RTL8822B */ From 41f431e2f535019aec8edd3930444de9021dba1f Mon Sep 17 00:00:00 2001 From: Ian Glen Date: Fri, 11 Jan 2019 21:20:15 -0500 Subject: [PATCH 19/48] Added support for Hawking Tech HW12ACU USB dongle --- os_dep/linux/usb_intf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/os_dep/linux/usb_intf.c b/os_dep/linux/usb_intf.c index ff2b83a..d106d8d 100644 --- a/os_dep/linux/usb_intf.c +++ b/os_dep/linux/usb_intf.c @@ -244,6 +244,7 @@ static struct usb_device_id rtw_usb_id_tbl[] = { {USB_DEVICE(0x7392, 0xC822), .driver_info = RTL8822B}, /* Edimax - EW-7822UTC */ {USB_DEVICE(0x2001, 0x331c), .driver_info = RTL8822B}, /* D-Link - DWA-182 Rev D */ {USB_DEVICE(0x2357, 0x0115), .driver_info = RTL8822B}, /* Archer USB T4Uv3 */ + {USB_DEVICE(0x0E66, 0x0025), .driver_info = RTL8822B}, /* Hawking Tech HW12ACU */ /*=== Customer ID ===*/ {USB_DEVICE_AND_INTERFACE_INFO(0x13b1, 0x0043, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Alpha - Alpha*/ #endif /* CONFIG_RTL8822B */ From 347f8fa9eedf58d10f021dd9ced9a64fe4ef25dd Mon Sep 17 00:00:00 2001 From: Simon Lui <502929+simonlui@users.noreply.github.com> Date: Thu, 31 Jan 2019 22:08:32 -0800 Subject: [PATCH 20/48] Fix Linux 5.0 compilation --- os_dep/linux/rtw_android.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/os_dep/linux/rtw_android.c b/os_dep/linux/rtw_android.c index b8b4377..8cde93c 100644 --- a/os_dep/linux/rtw_android.c +++ b/os_dep/linux/rtw_android.c @@ -657,7 +657,11 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) goto exit; } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)) + if (!access_ok(priv_cmd.buf, priv_cmd.total_len)) { +#else if (!access_ok(VERIFY_READ, priv_cmd.buf, priv_cmd.total_len)) { +#endif RTW_INFO("%s: failed to access memory\n", __FUNCTION__); ret = -EFAULT; goto exit; From ee9c890c548bbc7803a7a05423f5894778773562 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Sat, 16 Mar 2019 14:30:02 +0200 Subject: [PATCH 21/48] don't track cache --- .cache.mk | 70 ------------------------------------------------------- 1 file changed, 70 deletions(-) delete mode 100644 .cache.mk diff --git a/.cache.mk b/.cache.mk deleted file mode 100644 index 18907ce..0000000 --- a/.cache.mk +++ /dev/null @@ -1,70 +0,0 @@ -__cached_gcc_-v_2>&1_|_grep_-q_"clang_version"_&&_echo_clang_||_echo_gcc := gcc -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-mretpoline-external-thunk_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mretpoline-external-thunk";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-mindirect-branch_thunk-extern_-mindirect-branch-register_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mindirect-branch_thunk-extern_-mindirect-branch-register";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mindirect-branch=thunk-extern -mindirect-branch-register -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-PIE";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-PIE -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-fno-PIE_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-PIE";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-PIE -__cached_/bin/sh_./scripts/gcc-goto.sh_gcc_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE := y -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-fno-tree-loop-im_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-tree-loop-im";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-tree-loop-im -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-Wmaybe-uninitialized_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-maybe-uninitialized";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-maybe-uninitialized -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO__-mpreferred-stack-boundary_4_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-mpreferred-stack-boundary_4";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mpreferred-stack-boundary=4 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO__-m16_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-m16";_else_echo_"_-m32_-Wa_./arch/x86/boot/code16gcc.h";_fi;_rm_-f_"_TMP"_"_TMPO" := -m16 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-m16_-g_-Os_-DDISABLE_BRANCH_PROFILING_-Wall_-Wstrict-prototypes_-march_i386_-mregparm_3_-fno-strict-aliasing_-fomit-frame-pointer_-fno-pic_-mno-mmx_-mno-sse__-ffreestanding_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-ffreestanding";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -ffreestanding -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-m16_-g_-Os_-DDISABLE_BRANCH_PROFILING_-Wall_-Wstrict-prototypes_-march_i386_-mregparm_3_-fno-strict-aliasing_-fomit-frame-pointer_-fno-pic_-mno-mmx_-mno-sse_-ffreestanding__-fno-stack-protector_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-fno-stack-protector";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-stack-protector -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-m16_-g_-Os_-DDISABLE_BRANCH_PROFILING_-Wall_-Wstrict-prototypes_-march_i386_-mregparm_3_-fno-strict-aliasing_-fomit-frame-pointer_-fno-pic_-mno-mmx_-mno-sse_-ffreestanding_-fno-stack-protector__-mpreferred-stack-boundary_2_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-mpreferred-stack-boundary_2";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mpreferred-stack-boundary=2 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mno-avx";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mno-avx -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-falign-jumps_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -falign-jumps=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-falign-loops_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -falign-loops=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mno-80387";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mno-80387 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mno-fp-ret-in-387";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mno-fp-ret-in-387 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mpreferred-stack-boundary_3";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mpreferred-stack-boundary=3 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mskip-rax-setup";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mskip-rax-setup -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-mtune_skylake_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-mtune_skylake";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mtune=skylake -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-march_skylake";_else_echo_"-mtune_skylake";_fi;_rm_-f_"_TMP"_"_TMPO" := -march=skylake -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-funit-at-a-time";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -funit-at-a-time -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time__-mfentry_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"y";_else_echo_"n";_fi;_rm_-f_"_TMP"_"_TMPO" := y -__cached_/bin/sh_./scripts/gcc-version.sh_-p_gcc := 080101 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_".cfi_startproc_n.cfi_rel_offset_rsp_0_n.cfi_endproc"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_CFI_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_CFI=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_".cfi_startproc_n.cfi_signal_frame_n.cfi_endproc"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_CFI_SIGNAL_FRAME_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_CFI_SIGNAL_FRAME=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_".cfi_sections_.debug_frame"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_CFI_SECTIONS_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_CFI_SECTIONS=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"fxsaveq__%rax_"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_FXSAVEQ_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_FXSAVEQ=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"pshufb_%xmm0_%xmm0"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_SSSE3_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_SSSE3=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"crc32l_%eax_%eax"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_CRC32_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_CRC32=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"vxorps_%ymm0_%ymm1_%ymm2"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_AVX_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_AVX=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"vpbroadcastb_%xmm0_%ymm1"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_AVX2_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_AVX2=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"vpmovm2b_%k1_%zmm5"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_AVX512_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_AVX512=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"sha1msg1_%xmm0_%xmm1"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_SHA1_NI_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_SHA1_NI=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___printf_"%b_n"_"sha256msg1_%xmm0_%xmm1"_|_gcc_-D__ASSEMBLY___-fno-PIE_-DCC_HAVE_ASM_GOTO_-m64_-c_-x_assembler_-o_"_TMP"_-__>/dev/null_2>&1;_then_echo_"-DCONFIG_AS_SHA256_NI_1";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -DCONFIG_AS_SHA256_NI=1 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___ld_-m_elf_x86_64__-z_max-page-size_0x200000_-v__>/dev/null_2>&1;_then_echo_"_-z_max-page-size_0x200000";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -z max-page-size=0x200000 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-delete-null-pointer-checks";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-delete-null-pointer-checks -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wframe-address_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-frame-address";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-frame-address -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wformat-truncation_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-format-truncation";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-format-truncation -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wformat-overflow_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-format-overflow";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-format-overflow -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wint-in-bool-context_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-int-in-bool-context";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-int-in-bool-context -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_-Wmaybe-uninitialized_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-maybe-uninitialized";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-maybe-uninitialized -__cached_/bin/sh_./scripts/gcc-version.sh_gcc := 0801 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"--param_allow-store-data-races_0";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := --param=allow-store-data-races=0 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wframe-larger-than_2048";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wframe-larger-than=2048 -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fstack-protector";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fstack-protector -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fstack-protector-strong";_else_echo_"-fstack-protector";_fi;_rm_-f_"_TMP"_"_TMPO" := -fstack-protector-strong -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wunused-but-set-variable_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-unused-but-set-variable";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-unused-but-set-variable -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wunused-const-variable_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-unused-const-variable";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-unused-const-variable -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable__-fno-var-tracking-assignments_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-fno-var-tracking-assignments";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-var-tracking-assignments -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments__-mfentry_-DCC_USING_FENTRY_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"_-mfentry_-DCC_USING_FENTRY";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -mfentry -DCC_USING_FENTRY -__cached_gcc_-print-file-name_include := /usr/lib/gcc/x86_64-pc-linux-gnu/8.1.1/include -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wdeclaration-after-statement";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wdeclaration-after-statement -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wpointer-sign_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-pointer-sign";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-pointer-sign -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-strict-overflow";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-strict-overflow -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-merge-all-constants";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-merge-all-constants -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fmerge-constants";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fmerge-constants -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fno-stack-check";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fno-stack-check -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fconserve-stack";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fconserve-stack -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Werror_implicit-int";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Werror=implicit-int -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-Werror_strict-prototypes_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Werror_strict-prototypes";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Werror=strict-prototypes -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-Werror_strict-prototypes_-Werror_date-time_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Werror_date-time";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Werror=date-time -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-Werror_strict-prototypes_-Werror_date-time_-Werror_incompatible-pointer-types_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Werror_incompatible-pointer-types";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Werror=incompatible-pointer-types -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-Werror_strict-prototypes_-Werror_date-time_-Werror_incompatible-pointer-types_-Werror_designated-init_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Werror_designated-init";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Werror=designated-init -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if____gcc_-Werror__-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-Werror_strict-prototypes_-Werror_date-time_-Werror_incompatible-pointer-types_-Werror_designated-init_-fmacro-prefix-map_./__-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-fmacro-prefix-map_./_";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -fmacro-prefix-map=./= -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___ar_rcD_"_TMP"__>/dev/null_2>&1;_then_echo_"D";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := D -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___gcc_-Werror_-D__KERNEL___-DCONFIG_CC_STACKPROTECTOR_-Wall_-Wundef_-Wstrict-prototypes_-Wno-trigraphs_-fno-strict-aliasing_-fno-common_-fshort-wchar_-Werror-implicit-function-declaration_-Wno-format-security_-std_gnu89_-fno-PIE_-DCC_HAVE_ASM_GOTO_-mno-sse_-mno-mmx_-mno-sse2_-mno-3dnow_-mno-avx_-m64_-falign-jumps_1_-falign-loops_1_-mno-80387_-mno-fp-ret-in-387_-mpreferred-stack-boundary_3_-mskip-rax-setup_-march_skylake_-mno-red-zone_-mcmodel_kernel_-funit-at-a-time_-DCONFIG_AS_CFI_1_-DCONFIG_AS_CFI_SIGNAL_FRAME_1_-DCONFIG_AS_CFI_SECTIONS_1_-DCONFIG_AS_FXSAVEQ_1_-DCONFIG_AS_SSSE3_1_-DCONFIG_AS_CRC32_1_-DCONFIG_AS_AVX_1_-DCONFIG_AS_AVX2_1_-DCONFIG_AS_AVX512_1_-DCONFIG_AS_SHA1_NI_1_-DCONFIG_AS_SHA256_NI_1_-pipe_-Wno-sign-compare_-fno-asynchronous-unwind-tables_-mindirect-branch_thunk-extern_-mindirect-branch-register_-DRETPOLINE_-fno-delete-null-pointer-checks_-Wno-frame-address_-Wno-format-truncation_-Wno-format-overflow_-Wno-int-in-bool-context_-O2_--param_allow-store-data-races_0_-Wframe-larger-than_2048_-fstack-protector-strong_-Wno-unused-but-set-variable_-Wno-unused-const-variable_-fno-var-tracking-assignments_-pg_-mfentry_-DCC_USING_FENTRY_-Wdeclaration-after-statement_-Wno-pointer-sign_-fno-strict-overflow_-fno-merge-all-constants_-fmerge-constants_-fno-stack-check_-fconserve-stack_-Werror_implicit-int_-Werror_strict-prototypes_-Werror_date-time_-Werror_incompatible-pointer-types_-Werror_designated-init_-fmacro-prefix-map_./__-Wpacked-not-aligned_-c_-x_c_/dev/null_-o_"_TMP"__>/dev/null_2>&1;_then_echo_"-Wno-packed-not-aligned";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -Wno-packed-not-aligned -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___ld_-m_elf_x86_64_-z_max-page-size_0x200000__--build-id_-v__>/dev/null_2>&1;_then_echo_"_--build-id";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := --build-id -__cached_set_-e;_TMP_"/home/will/git_repos/rtl8822bu/.__.tmp";_TMPO_"/home/will/git_repos/rtl8822bu/.__.o";_if___ld_-m_elf_x86_64_-z_max-page-size_0x200000__-X_-v__>/dev/null_2>&1;_then_echo_"_-X";_else_echo_"";_fi;_rm_-f_"_TMP"_"_TMPO" := -X From 41aeba091849912f7fa4ae8d734f8682394d1445 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Mon, 1 Apr 2019 08:28:20 +0200 Subject: [PATCH 22/48] use ! instead of ~ --- hal/btc/halbtc8822b1ant.c | 2 +- hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hal/btc/halbtc8822b1ant.c b/hal/btc/halbtc8822b1ant.c index 00f15c4..d95168c 100644 --- a/hal/btc/halbtc8822b1ant.c +++ b/hal/btc/halbtc8822b1ant.c @@ -2477,7 +2477,7 @@ void halbtc8822b1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, * 0xcbd[1:0] = 2b'10 => Ant to WLG */ switch_polatiry_inverse = (rfe_type->ext_ant_switch_ctrl_polarity == 1 ? - ~switch_polatiry_inverse : switch_polatiry_inverse); + !switch_polatiry_inverse : switch_polatiry_inverse); switch (pos_type) { diff --git a/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c index 0c4813d..8017135 100644 --- a/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c +++ b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c @@ -456,9 +456,9 @@ _iqk_reload_iqk_setting_8822b( odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (iqk_info->iqk_cfir_imag[channel][path][idx][i] << 9)); } if (idx == 0) - odm_set_bb_reg(dm, iqk_apply[path], BIT(0), ~(iqk_info->iqk_fail_report[channel][path][idx])); + odm_set_bb_reg(dm, iqk_apply[path], BIT(0), !(iqk_info->iqk_fail_report[channel][path][idx])); else - odm_set_bb_reg(dm, iqk_apply[path], BIT(10), ~(iqk_info->iqk_fail_report[channel][path][idx])); + odm_set_bb_reg(dm, iqk_apply[path], BIT(10), !(iqk_info->iqk_fail_report[channel][path][idx])); } odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0); odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0); From 7abedb1a51b4b0cb541efc5668554e923908b9df Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Mon, 22 Apr 2019 18:28:08 +0200 Subject: [PATCH 23/48] update usb_intf.c --- os_dep/linux/usb_intf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/os_dep/linux/usb_intf.c b/os_dep/linux/usb_intf.c index d106d8d..ca1766c 100644 --- a/os_dep/linux/usb_intf.c +++ b/os_dep/linux/usb_intf.c @@ -244,6 +244,7 @@ static struct usb_device_id rtw_usb_id_tbl[] = { {USB_DEVICE(0x7392, 0xC822), .driver_info = RTL8822B}, /* Edimax - EW-7822UTC */ {USB_DEVICE(0x2001, 0x331c), .driver_info = RTL8822B}, /* D-Link - DWA-182 Rev D */ {USB_DEVICE(0x2357, 0x0115), .driver_info = RTL8822B}, /* Archer USB T4Uv3 */ + {USB_DEVICE(0x2357, 0x012d), .driver_info = RTL8822B}, /* Archer USB T3U */ {USB_DEVICE(0x0E66, 0x0025), .driver_info = RTL8822B}, /* Hawking Tech HW12ACU */ /*=== Customer ID ===*/ {USB_DEVICE_AND_INTERFACE_INFO(0x13b1, 0x0043, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Alpha - Alpha*/ From dbbf4f7c3527f1bff38054349f01a4a8438db0f4 Mon Sep 17 00:00:00 2001 From: MeissnerEffect Date: Sat, 27 Apr 2019 09:12:27 +0200 Subject: [PATCH 24/48] Kernel 5.1 fix --- os_dep/osdep_service.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/os_dep/osdep_service.c b/os_dep/osdep_service.c index 2dca007..8b35ef2 100644 --- a/os_dep/osdep_service.c +++ b/os_dep/osdep_service.c @@ -2169,6 +2169,10 @@ static int writeFile(struct file *fp, char *buf, int len) } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0)) + #define get_ds() (KERNEL_DS) +#endif + /* * Test if the specifi @param path is a file and readable * If readable, @param sz is got From a78a581b775556696313f6c0be74a85943c271ac Mon Sep 17 00:00:00 2001 From: sparkie3 <40219937+sparkie3@users.noreply.github.com> Date: Sun, 19 May 2019 23:59:50 -0400 Subject: [PATCH 25/48] Update README.md --- README.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/README.md b/README.md index 1a92175..4ef2569 100644 --- a/README.md +++ b/README.md @@ -37,6 +37,14 @@ This driver allows use of wpa_supplicant by using the nl80211 driver If installing on Rasberry Pi or other "armv71" devices, edit the Makefile and set `CONFIG_PLATFORM_ARM_RPI = y` and `CONFIG_PLATFORM_I386_PC = n` +On Debian with some wireless managers (KDE confirmed) you must append the following to /etc/NetworkManager/NetworkManager.conf: + +[device] +wifi.scan-rand-mac-address=no + +Otherwise, you may get stuck in an infinte loop of failed connection and a prompt for password. Source page here: +https://wiki.debian.org/WiFi + **STATUS** Driver works fine (some sort of) Most of the work is done is cleaning the driver and make this mess **readable** for conversion. From 70d7b10a2eafdbf36ee64790646d74b5baf3a807 Mon Sep 17 00:00:00 2001 From: parly Date: Tue, 9 Jul 2019 15:58:44 +0900 Subject: [PATCH 26/48] Kernel 5.2 fix --- os_dep/linux/os_intfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/os_dep/linux/os_intfs.c b/os_dep/linux/os_intfs.c index f1a93f4..f382b2b 100644 --- a/os_dep/linux/os_intfs.c +++ b/os_dep/linux/os_intfs.c @@ -1297,7 +1297,7 @@ static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb #else , struct net_device *sb_dev #endif - #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)) , select_queue_fallback_t fallback #endif #endif From 17caa856172d85fa7df01c4759ae7e17df204263 Mon Sep 17 00:00:00 2001 From: Roland Ruckerbauer Date: Fri, 20 Sep 2019 23:07:19 +0200 Subject: [PATCH 27/48] Added policy to vendor commands --- os_dep/linux/rtw_cfgvendor.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/os_dep/linux/rtw_cfgvendor.c b/os_dep/linux/rtw_cfgvendor.c index 0f0f24f..9192a68 100644 --- a/os_dep/linux/rtw_cfgvendor.c +++ b/os_dep/linux/rtw_cfgvendor.c @@ -1399,7 +1399,8 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LSTATS_SUBCMD_GET_INFO }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_lstats_get_info + .doit = rtw_cfgvendor_lstats_get_info, + .policy = VENDOR_CMD_RAW_DATA, }, { { @@ -1407,7 +1408,8 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LSTATS_SUBCMD_SET_INFO }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_lstats_set_info + .doit = rtw_cfgvendor_lstats_set_info, + .policy = VENDOR_CMD_RAW_DATA, }, { { @@ -1415,7 +1417,8 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = LSTATS_SUBCMD_CLEAR_INFO }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_lstats_clear_info + .doit = rtw_cfgvendor_lstats_clear_info, + .policy = VENDOR_CMD_RAW_DATA, }, #endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ { @@ -1424,7 +1427,8 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = WIFI_SUBCMD_GET_FEATURE_SET }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_get_feature_set + .doit = rtw_cfgvendor_get_feature_set, + .policy = VENDOR_CMD_RAW_DATA, }, { { @@ -1432,7 +1436,8 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = WIFI_SUBCMD_GET_FEATURE_SET_MATRIX }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = rtw_cfgvendor_get_feature_set_matrix + .doit = rtw_cfgvendor_get_feature_set_matrix, + .policy = VENDOR_CMD_RAW_DATA, } }; From a92a07fa61367ee16130b4c77e54d9c0c3634f8d Mon Sep 17 00:00:00 2001 From: Brock Martin Date: Mon, 14 Oct 2019 21:44:51 +0000 Subject: [PATCH 28/48] Guard reference to wiphy_vendor_command policy attribute --- os_dep/linux/rtw_cfgvendor.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/os_dep/linux/rtw_cfgvendor.c b/os_dep/linux/rtw_cfgvendor.c index 9192a68..36ae076 100644 --- a/os_dep/linux/rtw_cfgvendor.c +++ b/os_dep/linux/rtw_cfgvendor.c @@ -37,6 +37,9 @@ #include +#define KERNEL_HAS_CFG80211_WIPHY_VENDOR_COMMAND_POLICY \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) + #ifdef DBG_MEM_ALLOC extern bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size); struct sk_buff *dbg_rtw_cfg80211_vendor_event_alloc(struct wiphy *wiphy, struct wireless_dev *wdev, int len, int event_id, gfp_t gfp @@ -1400,7 +1403,9 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, .doit = rtw_cfgvendor_lstats_get_info, +#if KERNEL_HAS_CFG80211_WIPHY_VENDOR_COMMAND_POLICY .policy = VENDOR_CMD_RAW_DATA, +#endif /* KERNEL_HAS_CFG80211_WIPHY_VENDOR_COMMAND_POLICY */ }, { { @@ -1409,7 +1414,9 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, .doit = rtw_cfgvendor_lstats_set_info, +#if KERNEL_HAS_CFG80211_WIPHY_VENDOR_COMMAND_POLICY .policy = VENDOR_CMD_RAW_DATA, +#endif /* KERNEL_HAS_CFG80211_WIPHY_VENDOR_COMMAND_POLICY */ }, { { @@ -1418,7 +1425,9 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, .doit = rtw_cfgvendor_lstats_clear_info, +#if KERNEL_HAS_CFG80211_WIPHY_VENDOR_COMMAND_POLICY .policy = VENDOR_CMD_RAW_DATA, +#endif /* KERNEL_HAS_CFG80211_WIPHY_VENDOR_COMMAND_POLICY */ }, #endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ { @@ -1428,7 +1437,9 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, .doit = rtw_cfgvendor_get_feature_set, +#if KERNEL_HAS_CFG80211_WIPHY_VENDOR_COMMAND_POLICY .policy = VENDOR_CMD_RAW_DATA, +#endif /* KERNEL_HAS_CFG80211_WIPHY_VENDOR_COMMAND_POLICY */ }, { { @@ -1437,7 +1448,9 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, .doit = rtw_cfgvendor_get_feature_set_matrix, +#if KERNEL_HAS_CFG80211_WIPHY_VENDOR_COMMAND_POLICY .policy = VENDOR_CMD_RAW_DATA, +#endif /* KERNEL_HAS_CFG80211_WIPHY_VENDOR_COMMAND_POLICY */ } }; From 99b0c5af55220cc877a8658ff4a531c00ce6bc28 Mon Sep 17 00:00:00 2001 From: Itamar Schen Date: Wed, 23 Oct 2019 13:08:36 +0300 Subject: [PATCH 29/48] Added dkms.conf --- README.md | 36 +++++++++++++++++++++++++++++------- dkms.conf | 9 +++++++++ 2 files changed, 38 insertions(+), 7 deletions(-) create mode 100644 dkms.conf diff --git a/README.md b/README.md index 4ef2569..ce95d8b 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -**8822BU for Linux** +# 8822BU for Linux Driver for 802.11ac USB Adapter with RTL8822BU chipset @@ -17,12 +17,17 @@ A few known wireless cards that use this driver include Currently tested on X86_64 and ARM platform(s) **only**, cross compile possible. +## Installing For compiling type -`make` +``` +make +``` in source dir To install the firmware files -`sudo make install` +``` +sudo make install +``` To Unload driver you may need to disconnect the device @@ -30,8 +35,24 @@ To Unload driver you may need to disconnect the device If the driver fails building consult your distro how to install the kernel sources and build an external module. - -**NOTES** +## DKMS +Automatically rebuilds and installs on kernel updates. DKMS is in official sources of Ubuntu, for installation do: +``` +sudo apt-get install build-essential dkms +``` + +Then install the module using dkms do in source dir: +``` +sudo dkms add . +sudo dkms install -m 88x2bu -v 1.1 +``` +In order to uninstall the module: +``` +sudo dkms remove -m 88x2bu -v 1.1 --all +sudo rm -rf /usr/src/88x2bu-1.1 +``` + +## NOTES This driver allows use of wpa_supplicant by using the nl80211 driver `wpa_supplicant -Dnl80211` @@ -45,10 +66,11 @@ wifi.scan-rand-mac-address=no Otherwise, you may get stuck in an infinte loop of failed connection and a prompt for password. Source page here: https://wiki.debian.org/WiFi -**STATUS** +## STATUS Driver works fine (some sort of) Most of the work is done is cleaning the driver and make this mess **readable** for conversion. Updates for wireless-ext/cfg80211 are not accepted. -**BUGS** +## BUGS + diff --git a/dkms.conf b/dkms.conf new file mode 100644 index 0000000..8b081d0 --- /dev/null +++ b/dkms.conf @@ -0,0 +1,9 @@ +PACKAGE_NAME=88x2bu +PACKAGE_VERSION=1.1 + +DEST_MODULE_LOCATION=/kernel/drivers/net/wireless +BUILT_MODULE_NAME=88x2bu + +MAKE="'make' all KVER=${kernelver}" +CLEAN="'make' clean" +AUTOINSTALL="yes" From 5816d296fec736cac5323e142748a2e9455065ae Mon Sep 17 00:00:00 2001 From: Gavin Li Date: Mon, 27 Jan 2020 15:34:10 -0800 Subject: [PATCH 30/48] Added Trendnet TEW-808UBM --- os_dep/linux/usb_intf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/os_dep/linux/usb_intf.c b/os_dep/linux/usb_intf.c index ca1766c..c6d1504 100644 --- a/os_dep/linux/usb_intf.c +++ b/os_dep/linux/usb_intf.c @@ -246,6 +246,7 @@ static struct usb_device_id rtw_usb_id_tbl[] = { {USB_DEVICE(0x2357, 0x0115), .driver_info = RTL8822B}, /* Archer USB T4Uv3 */ {USB_DEVICE(0x2357, 0x012d), .driver_info = RTL8822B}, /* Archer USB T3U */ {USB_DEVICE(0x0E66, 0x0025), .driver_info = RTL8822B}, /* Hawking Tech HW12ACU */ + {USB_DEVICE(0x20F4, 0x808A), .driver_info = RTL8822B}, /* Trendnet TEW-808UBM */ /*=== Customer ID ===*/ {USB_DEVICE_AND_INTERFACE_INFO(0x13b1, 0x0043, 0xff, 0xff, 0xff), .driver_info = RTL8822B}, /* Alpha - Alpha*/ #endif /* CONFIG_RTL8822B */ From 7fd195194a418f7dc2c923a39611b19ed310712c Mon Sep 17 00:00:00 2001 From: j_rutzmoser Date: Thu, 6 Feb 2020 09:35:19 +0100 Subject: [PATCH 31/48] Add ASUS USB AC57 to supported USB devices --- os_dep/linux/usb_intf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/os_dep/linux/usb_intf.c b/os_dep/linux/usb_intf.c index ca1766c..baa78d7 100644 --- a/os_dep/linux/usb_intf.c +++ b/os_dep/linux/usb_intf.c @@ -241,6 +241,7 @@ static struct usb_device_id rtw_usb_id_tbl[] = { {USB_DEVICE(0x0B05, 0x1812), .driver_info = RTL8812}, /* ASUS - Edimax */ {USB_DEVICE(0x7392, 0xB822), .driver_info = RTL8822B}, /* Edimax - EW-7822ULC */ {USB_DEVICE(0x0b05, 0x184c), .driver_info = RTL8822B}, /* ASUS USB AC53 */ + {USB_DEVICE(0x0b05, 0x1841), .driver_info = RTL8822B}, /* ASUS USB AC57 */ {USB_DEVICE(0x7392, 0xC822), .driver_info = RTL8822B}, /* Edimax - EW-7822UTC */ {USB_DEVICE(0x2001, 0x331c), .driver_info = RTL8822B}, /* D-Link - DWA-182 Rev D */ {USB_DEVICE(0x2357, 0x0115), .driver_info = RTL8822B}, /* Archer USB T4Uv3 */ From 8db9660f33ee188819126304e67e73f871726a4a Mon Sep 17 00:00:00 2001 From: parly Date: Mon, 6 Apr 2020 23:28:35 +0900 Subject: [PATCH 32/48] Kernel 5.6 fix --- os_dep/linux/ioctl_cfg80211.c | 13 ++++-- os_dep/linux/rtw_proc.c | 79 ++++++++++++++++++++++++++++++++++- 2 files changed, 87 insertions(+), 5 deletions(-) diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index 5c7311d..ed432ac 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -687,11 +687,16 @@ static int rtw_cfg80211_sync_iftype(_adapter *adapter) static u64 rtw_get_systime_us(void) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) - struct timespec ts; - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)) - getboottime(&ts); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) + struct timespec64 ts; + getboottime64(&ts); #else - get_monotonic_boottime(&ts); + struct timespec ts; + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)) + getboottime(&ts); + #else + get_monotonic_boottime(&ts); + #endif #endif return ((u64)ts.tv_sec * 1000000) + ts.tv_nsec / 1000; #else diff --git a/os_dep/linux/rtw_proc.c b/os_dep/linux/rtw_proc.c index e5577de..032e437 100644 --- a/os_dep/linux/rtw_proc.c +++ b/os_dep/linux/rtw_proc.c @@ -62,7 +62,12 @@ inline struct proc_dir_entry *rtw_proc_create_dir(const char *name, struct proc_ } inline struct proc_dir_entry *rtw_proc_create_entry(const char *name, struct proc_dir_entry *parent, - const struct file_operations *fops, void * data) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) + const struct proc_ops *fops, +#else + const struct file_operations *fops, +#endif + void * data) { struct proc_dir_entry *entry; @@ -230,6 +235,23 @@ static ssize_t rtw_drv_proc_write(struct file *file, const char __user *buffer, return -EROFS; } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) +static const struct proc_ops rtw_drv_proc_seq_fops = { + .proc_open = rtw_drv_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = seq_release, + .proc_write = rtw_drv_proc_write, +}; + +static const struct proc_ops rtw_drv_proc_sseq_fops = { + .proc_open = rtw_drv_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = single_release, + .proc_write = rtw_drv_proc_write, +}; +#else static const struct file_operations rtw_drv_proc_seq_fops = { .owner = THIS_MODULE, .open = rtw_drv_proc_open, @@ -247,6 +269,7 @@ static const struct file_operations rtw_drv_proc_sseq_fops = { .release = single_release, .write = rtw_drv_proc_write, }; +#endif int rtw_drv_proc_init(void) { @@ -3499,6 +3522,23 @@ static ssize_t rtw_adapter_proc_write(struct file *file, const char __user *buff return -EROFS; } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) +static const struct proc_ops rtw_adapter_proc_seq_fops = { + .proc_open = rtw_adapter_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = seq_release, + .proc_write = rtw_adapter_proc_write, +}; + +static const struct proc_ops rtw_adapter_proc_sseq_fops = { + .proc_open = rtw_adapter_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = single_release, + .proc_write = rtw_adapter_proc_write, +}; +#else static const struct file_operations rtw_adapter_proc_seq_fops = { .owner = THIS_MODULE, .open = rtw_adapter_proc_open, @@ -3516,6 +3556,7 @@ static const struct file_operations rtw_adapter_proc_sseq_fops = { .release = single_release, .write = rtw_adapter_proc_write, }; +#endif int proc_get_odm_adaptivity(struct seq_file *m, void *v) { @@ -3671,6 +3712,23 @@ static ssize_t rtw_odm_proc_write(struct file *file, const char __user *buffer, return -EROFS; } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) +static const struct proc_ops rtw_odm_proc_seq_fops = { + .proc_open = rtw_odm_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = seq_release, + .proc_write = rtw_odm_proc_write, +}; + +static const struct proc_ops rtw_odm_proc_sseq_fops = { + .proc_open = rtw_odm_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = single_release, + .proc_write = rtw_odm_proc_write, +}; +#else static const struct file_operations rtw_odm_proc_seq_fops = { .owner = THIS_MODULE, .open = rtw_odm_proc_open, @@ -3688,6 +3746,7 @@ static const struct file_operations rtw_odm_proc_sseq_fops = { .release = single_release, .write = rtw_odm_proc_write, }; +#endif struct proc_dir_entry *rtw_odm_proc_init(struct net_device *dev) { @@ -3812,6 +3871,23 @@ static ssize_t rtw_mcc_proc_write(struct file *file, const char __user *buffer, return -EROFS; } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)) +static const struct proc_ops rtw_mcc_proc_seq_fops = { + .proc_open = rtw_mcc_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = seq_release, + .proc_write = rtw_mcc_proc_write, +}; + +static const struct proc_ops rtw_mcc_proc_sseq_fops = { + .proc_open = rtw_mcc_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = single_release, + .proc_write = rtw_mcc_proc_write, +}; +#else static const struct file_operations rtw_mcc_proc_seq_fops = { .owner = THIS_MODULE, .open = rtw_mcc_proc_open, @@ -3829,6 +3905,7 @@ static const struct file_operations rtw_mcc_proc_sseq_fops = { .release = single_release, .write = rtw_mcc_proc_write, }; +#endif struct proc_dir_entry *rtw_mcc_proc_init(struct net_device *dev) { From a64fda36d946fddab70e77c2c2fadbfb52b93149 Mon Sep 17 00:00:00 2001 From: Philip Prindeville Date: Mon, 13 Jul 2020 21:27:47 +0000 Subject: [PATCH 33/48] Add more targets to ignore list Signed-off-by: Philip Prindeville --- .gitignore | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index cee10ae..f985abd 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,10 @@ sftp-config.json *.o -*.ko \ No newline at end of file +*.ko +.*.o.cmd +.88x2bu.ko.cmd +.88x2bu.mod.cmd +88x2bu.mod +88x2bu.mod.c +Module.symvers +modules.order From 8a0a919afcfcd33cfcebd74cf9004145b4f4e0fd Mon Sep 17 00:00:00 2001 From: Philip Prindeville Date: Mon, 13 Jul 2020 21:53:46 +0000 Subject: [PATCH 34/48] Get clean compile without -Wimplicit-fallthroug warnings Signed-off-by: Philip Prindeville --- core/rtw_mlme_ext.c | 2 +- hal/hal_halmac.c | 2 +- hal/hal_intf.c | 1 + hal/halmac/halmac_88xx/halmac_mimo_88xx.c | 2 ++ os_dep/linux/ioctl_cfg80211.c | 2 ++ 5 files changed, 7 insertions(+), 2 deletions(-) diff --git a/core/rtw_mlme_ext.c b/core/rtw_mlme_ext.c index 3bcb3fa..e01d533 100644 --- a/core/rtw_mlme_ext.c +++ b/core/rtw_mlme_ext.c @@ -1826,7 +1826,7 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) ptable->func = &OnAuth; else ptable->func = &OnAuthClient; - /* pass through */ + fallthrough; case WIFI_ASSOCREQ: case WIFI_REASSOCREQ: _mgt_dispatcher(padapter, ptable, precv_frame); diff --git a/hal/hal_halmac.c b/hal/hal_halmac.c index 046d15c..89a7fd2 100644 --- a/hal/hal_halmac.c +++ b/hal/hal_halmac.c @@ -2695,7 +2695,7 @@ static int _send_general_info(struct dvobj_priv *d) case HALMAC_RET_NO_DLFW: RTW_WARN("%s: halmac_send_general_info() fail because fw not dl!\n", __FUNCTION__); - /* go through */ + fallthrough; default: return -1; } diff --git a/hal/hal_intf.c b/hal/hal_intf.c index 351e923..20336c9 100644 --- a/hal/hal_intf.c +++ b/hal/hal_intf.c @@ -942,6 +942,7 @@ s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) case C2H_EXTEND: sub_id = payload[0]; /* no handle, goto default */ + fallthrough; default: if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE) diff --git a/hal/halmac/halmac_88xx/halmac_mimo_88xx.c b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c index 31bd3bc..0a9bd05 100644 --- a/hal/halmac/halmac_88xx/halmac_mimo_88xx.c +++ b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c @@ -62,8 +62,10 @@ cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw, switch (bw) { case HALMAC_BW_80: tmp42c |= BIT_R_TXBF0_80M; + fallthrough; case HALMAC_BW_40: tmp42c |= BIT_R_TXBF0_40M; + fallthrough; case HALMAC_BW_20: tmp42c |= BIT_R_TXBF0_20M; break; diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index 5c7311d..081affb 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -2361,6 +2361,7 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_CLIENT: is_p2p = _TRUE; + fallthrough; #endif case NL80211_IFTYPE_STATION: networkType = Ndis802_11Infrastructure; @@ -2385,6 +2386,7 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_GO: is_p2p = _TRUE; + fallthrough; #endif case NL80211_IFTYPE_AP: networkType = Ndis802_11APMode; From 0d591afe759027e0f2bc909b98d1d3ca898a2f60 Mon Sep 17 00:00:00 2001 From: Philip Prindeville Date: Tue, 21 Jul 2020 21:53:04 +0000 Subject: [PATCH 35/48] Set SElinux context on module Signed-off-by: Philip Prindeville --- Makefile | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 375c3f4..29da0bf 100644 --- a/Makefile +++ b/Makefile @@ -1998,13 +1998,16 @@ export CONFIG_RTL8822BU = m all: modules modules: - $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules + $(MAKE) ARCH="$(ARCH)" CROSS_COMPILE="$(CROSS_COMPILE)" -C $(KSRC) M="$(shell pwd)" modules strip: $(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded install: - install -p -m 644 $(MODULE_NAME).ko $(MODDESTDIR) + install -p -m 644 $(MODULE_NAME).ko $(MODDESTDIR) + if [ -n "$$(which selinuxenabled)" ] && selinuxenabled ; then \ + restorecon $(MODDESTDIR)/$(MODULE_NAME).ko ; \ + fi /sbin/depmod -a ${KVER} uninstall: @@ -2053,7 +2056,7 @@ config_r: .PHONY: modules clean clean: - #$(MAKE) -C $(KSRC) M=$(shell pwd) clean + #$(MAKE) -C $(KSRC) M="$(shell pwd)" clean cd hal ; rm -fr */*/*/*.mod.c */*/*/*.mod */*/*/*.o */*/*/.*.cmd */*/*/*.ko cd hal ; rm -fr */*/*.mod.c */*/*.mod */*/*.o */*/.*.cmd */*/*.ko cd hal ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko From 1a05698f287add9e7e67b503806fbfcdace4270c Mon Sep 17 00:00:00 2001 From: Fabrice Fontaine Date: Sat, 19 Sep 2020 10:38:09 +0200 Subject: [PATCH 36/48] Fix build with kernel 5.8 This patch has been retrieved (and slightly updated to remove empty lines, fix indentation) from: https://github.com/aircrack-ng/rtl8188eus/commit/ad543d26166c24fee4aae9940f28dce4dcbd32d3 Signed-off-by: Fabrice Fontaine --- core/rtw_security.c | 14 ++++++++++++++ include/rtw_security.h | 2 ++ os_dep/linux/ioctl_cfg80211.c | 24 ++++++++++++++++++++++++ os_dep/linux/ioctl_cfg80211.h | 3 +++ 4 files changed, 43 insertions(+) diff --git a/core/rtw_security.c b/core/rtw_security.c index 52d5e3d..318dc52 100644 --- a/core/rtw_security.c +++ b/core/rtw_security.c @@ -2140,6 +2140,7 @@ u32 rtw_BIP_verify(_adapter *padapter, u8 *whdr_pos, sint flen #ifndef PLATFORM_FREEBSD /* compress 512-bits */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) static int sha256_compress(struct sha256_state *md, unsigned char *buf) { u32 S[8], W[64], t0, t1; @@ -2186,8 +2187,10 @@ static int sha256_compress(struct sha256_state *md, unsigned char *buf) md->state[i] = md->state[i] + S[i]; return 0; } +#endif /* Initialize the hash state */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) static void sha256_init(struct sha256_state *md) { md->curlen = 0; @@ -2201,6 +2204,7 @@ static void sha256_init(struct sha256_state *md) md->state[6] = 0x1F83D9ABUL; md->state[7] = 0x5BE0CD19UL; } +#endif /** Process a block of memory though the hash @@ -2209,6 +2213,7 @@ static void sha256_init(struct sha256_state *md) @param inlen The length of the data (octets) @return CRYPT_OK if successful */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) static int sha256_process(struct sha256_state *md, unsigned char *in, unsigned long inlen) { @@ -2242,6 +2247,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in, return 0; } +#endif /** @@ -2250,6 +2256,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in, @param out [out] The destination of the hash (32 bytes) @return CRYPT_OK if successful */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) static int sha256_done(struct sha256_state *md, unsigned char *out) { int i; @@ -2288,6 +2295,7 @@ static int sha256_done(struct sha256_state *md, unsigned char *out) return 0; } +#endif /** * sha256_vector - SHA256 hash for data vector @@ -2297,6 +2305,7 @@ static int sha256_done(struct sha256_state *md, unsigned char *out) * @mac: Buffer for the hash * Returns: 0 on success, -1 of failure */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len, u8 *mac) { @@ -2311,6 +2320,7 @@ static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len, return -1; return 0; } +#endif static u8 os_strlen(const char *s) { @@ -2347,6 +2357,7 @@ static int os_memcmp(const void *s1, const void *s2, u8 n) * @len: Lengths of the data blocks * @mac: Buffer for the hash (32 bytes) */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) static void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem, u8 *addr[], size_t *len, u8 *mac) { @@ -2423,6 +2434,7 @@ static void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem, * given key. */ #ifndef PLATFORM_FREEBSD /* Baron */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) static void sha256_prf(u8 *key, size_t key_len, char *label, u8 *data, size_t data_len, u8 *buf, size_t buf_len) { @@ -2459,6 +2471,7 @@ static void sha256_prf(u8 *key, size_t key_len, char *label, counter++; } } +#endif #endif /* PLATFORM_FREEBSD Baron */ /* AES tables*/ @@ -3299,6 +3312,7 @@ int tdls_verify_mic(u8 *kck, u8 trans_seq, return _FAIL; } +#endif #endif /* CONFIG_TDLS */ /* Restore HW wep key setting according to key_mask */ diff --git a/include/rtw_security.h b/include/rtw_security.h index ac8432e..6e40499 100644 --- a/include/rtw_security.h +++ b/include/rtw_security.h @@ -249,11 +249,13 @@ struct security_priv { #define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE #endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) struct sha256_state { u64 length; u32 state[8], curlen; u8 buf[64]; }; +#endif #define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\ do {\ diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index 2d0d0ec..74e258f 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -7030,6 +7030,7 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, return ret; } +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) struct wireless_dev *wdev, @@ -7037,7 +7038,15 @@ static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy, struct net_device *ndev, #endif u16 frame_type, bool reg) +#else +static void cfg80211_rtw_update_mgmt_frame_register(struct wiphy *wiphy, + struct wireless_dev *wdev, + struct mgmt_frame_regs *upd) +#endif { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0)) + u32 rtw_mask = BIT(IEEE80211_STYPE_PROBE_REQ >> 4); +#endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) struct net_device *ndev = wdev_to_ndev(wdev); #endif @@ -7052,13 +7061,19 @@ static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy, pwdev_priv = adapter_wdev_data(adapter); #ifdef CONFIG_DEBUG_CFG80211 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) RTW_INFO(FUNC_ADPT_FMT" frame_type:%x, reg:%d\n", FUNC_ADPT_ARG(adapter), frame_type, reg); +#else + RTW_INFO(FUNC_ADPT_FMT " old_regs:%x new_regs:%x\n", + FUNC_ADPT_ARG(adapter), pwdev_priv->mgmt_mask, upd->interface_stypes); +#endif #endif /* Wait QC Verify */ return; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) switch (frame_type) { case IEEE80211_STYPE_PROBE_REQ: /* 0x0040 */ SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_PROBE_REQ, reg); @@ -7069,7 +7084,12 @@ static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy, default: break; } +#else + if ((upd->interface_stypes & rtw_mask) == (pwdev_priv->mgmt_mask & rtw_mask)) + return; + pwdev_priv->mgmt_mask = upd->interface_stypes; +#endif exit: return; } @@ -9344,7 +9364,11 @@ static struct cfg80211_ops rtw_cfg80211_ops = { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) .mgmt_tx = cfg80211_rtw_mgmt_tx, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) .mgmt_frame_register = cfg80211_rtw_mgmt_frame_register, +#else + .update_mgmt_frame_registrations = cfg80211_rtw_update_mgmt_frame_register, +#endif #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) .action = cfg80211_rtw_mgmt_tx, #endif diff --git a/os_dep/linux/ioctl_cfg80211.h b/os_dep/linux/ioctl_cfg80211.h index 54a319f..b8775c8 100644 --- a/os_dep/linux/ioctl_cfg80211.h +++ b/os_dep/linux/ioctl_cfg80211.h @@ -164,6 +164,9 @@ struct rtw_wdev_priv { bool block; bool block_scan; bool power_mgmt; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0) + u32 mgmt_mask; +#endif /* report mgmt_frame registered */ u16 report_mgmt; From fc3ad1f38cb21b392e3935fefdba1137d4f560a6 Mon Sep 17 00:00:00 2001 From: Alexander Rechitskiy Date: Wed, 7 Oct 2020 23:45:19 +0300 Subject: [PATCH 37/48] Addition of tp-link Archer T4U to known devices Addition of tp-link Archer T4U (Revision V3 only) to known devices Tested and confirmed on Kali Linux with kernel version 5.8.0-kali2-amd64 --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index ce95d8b..c2f2a38 100644 --- a/README.md +++ b/README.md @@ -8,6 +8,8 @@ A few known wireless cards that use this driver include * [Edimax EW-7822ULC](http://us.edimax.com/edimax/merchandise/merchandise_detail/data/edimax/us/wireless_adapters_ac1200_dual-band/ew-7822ulc/) * [ASUS AC-53 NANO](https://www.asus.com/Networking/USB-AC53-Nano/) * [D-Link DWA-182 (Revision D1 only)](http://ca.dlink.com/products/connect/wireless-ac1200-dual-band-usb-adapter/) +* [tp-link Archer T4U (Revision V3 only)](https://www.tp-link.com/us/home-networking/usb-adapter/archer-t4u/) + > NOTE: At least v4.7 is needed to compile this module From 11f5cdd213c589862b925c094ed27a41734d6bc3 Mon Sep 17 00:00:00 2001 From: Ilija Hadzic Date: Thu, 15 Oct 2020 21:05:06 -0400 Subject: [PATCH 38/48] use fallthrough statement only in gcc version that supports it Allows the module to build (and work) distributions that have gcc prior to gcc-7. Signed-off-by: Ilija Hadzic --- core/rtw_mlme_ext.c | 2 ++ hal/hal_halmac.c | 2 ++ hal/hal_intf.c | 3 ++- hal/halmac/halmac_88xx/halmac_mimo_88xx.c | 4 ++++ os_dep/linux/ioctl_cfg80211.c | 4 ++++ 5 files changed, 14 insertions(+), 1 deletion(-) diff --git a/core/rtw_mlme_ext.c b/core/rtw_mlme_ext.c index e01d533..a68899f 100644 --- a/core/rtw_mlme_ext.c +++ b/core/rtw_mlme_ext.c @@ -1826,7 +1826,9 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) ptable->func = &OnAuth; else ptable->func = &OnAuthClient; +#if __GNUC__ > 6 fallthrough; +#endif case WIFI_ASSOCREQ: case WIFI_REASSOCREQ: _mgt_dispatcher(padapter, ptable, precv_frame); diff --git a/hal/hal_halmac.c b/hal/hal_halmac.c index 89a7fd2..db62ad3 100644 --- a/hal/hal_halmac.c +++ b/hal/hal_halmac.c @@ -2695,7 +2695,9 @@ static int _send_general_info(struct dvobj_priv *d) case HALMAC_RET_NO_DLFW: RTW_WARN("%s: halmac_send_general_info() fail because fw not dl!\n", __FUNCTION__); +#if __GNUC__ > 6 fallthrough; +#endif default: return -1; } diff --git a/hal/hal_intf.c b/hal/hal_intf.c index 20336c9..22d6b71 100644 --- a/hal/hal_intf.c +++ b/hal/hal_intf.c @@ -942,8 +942,9 @@ s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) case C2H_EXTEND: sub_id = payload[0]; /* no handle, goto default */ +#if __GNUC__ > 6 fallthrough; - +#endif default: if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE) ret = _FAIL; diff --git a/hal/halmac/halmac_88xx/halmac_mimo_88xx.c b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c index 0a9bd05..943f8f0 100644 --- a/hal/halmac/halmac_88xx/halmac_mimo_88xx.c +++ b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c @@ -62,10 +62,14 @@ cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw, switch (bw) { case HALMAC_BW_80: tmp42c |= BIT_R_TXBF0_80M; +#if __GNUC__ > 6 fallthrough; +#endif case HALMAC_BW_40: tmp42c |= BIT_R_TXBF0_40M; +#if __GNUC__ > 6 fallthrough; +#endif case HALMAC_BW_20: tmp42c |= BIT_R_TXBF0_20M; break; diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index 74e258f..7331a1c 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -2366,7 +2366,9 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_CLIENT: is_p2p = _TRUE; +#if __GNUC__ > 6 fallthrough; +#endif #endif case NL80211_IFTYPE_STATION: networkType = Ndis802_11Infrastructure; @@ -2391,7 +2393,9 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_GO: is_p2p = _TRUE; +#if __GNUC__ > 6 fallthrough; +#endif #endif case NL80211_IFTYPE_AP: networkType = Ndis802_11APMode; From c8ba5e87352ec76f3c4f3bf5fb6e81633e7594a7 Mon Sep 17 00:00:00 2001 From: Fabrice Fontaine Date: Sun, 18 Oct 2020 21:54:51 +0200 Subject: [PATCH 39/48] fix implicit fallthrough Fix the following build failure: /home/kali/rtl8822bu/core/rtw_mlme_ext.c:1829:3: error: 'fallthrough' undeclared (first use in this function) 1829 | fallthrough; | ^~~~~~~~~~~ Signed-off-by: Fabrice Fontaine --- core/rtw_mlme_ext.c | 2 +- hal/hal_halmac.c | 2 +- hal/hal_intf.c | 2 +- hal/halmac/halmac_88xx/halmac_mimo_88xx.c | 4 ++-- os_dep/linux/ioctl_cfg80211.c | 4 ++-- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/core/rtw_mlme_ext.c b/core/rtw_mlme_ext.c index e01d533..3f00ae0 100644 --- a/core/rtw_mlme_ext.c +++ b/core/rtw_mlme_ext.c @@ -1826,7 +1826,7 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) ptable->func = &OnAuth; else ptable->func = &OnAuthClient; - fallthrough; + [[fallthrough]]; case WIFI_ASSOCREQ: case WIFI_REASSOCREQ: _mgt_dispatcher(padapter, ptable, precv_frame); diff --git a/hal/hal_halmac.c b/hal/hal_halmac.c index 89a7fd2..5f1cecf 100644 --- a/hal/hal_halmac.c +++ b/hal/hal_halmac.c @@ -2695,7 +2695,7 @@ static int _send_general_info(struct dvobj_priv *d) case HALMAC_RET_NO_DLFW: RTW_WARN("%s: halmac_send_general_info() fail because fw not dl!\n", __FUNCTION__); - fallthrough; + [[fallthrough]]; default: return -1; } diff --git a/hal/hal_intf.c b/hal/hal_intf.c index 20336c9..07ab5a6 100644 --- a/hal/hal_intf.c +++ b/hal/hal_intf.c @@ -942,7 +942,7 @@ s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) case C2H_EXTEND: sub_id = payload[0]; /* no handle, goto default */ - fallthrough; + [[fallthrough]]; default: if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE) diff --git a/hal/halmac/halmac_88xx/halmac_mimo_88xx.c b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c index 0a9bd05..0a123a6 100644 --- a/hal/halmac/halmac_88xx/halmac_mimo_88xx.c +++ b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c @@ -62,10 +62,10 @@ cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw, switch (bw) { case HALMAC_BW_80: tmp42c |= BIT_R_TXBF0_80M; - fallthrough; + [[fallthrough]]; case HALMAC_BW_40: tmp42c |= BIT_R_TXBF0_40M; - fallthrough; + [[fallthrough]]; case HALMAC_BW_20: tmp42c |= BIT_R_TXBF0_20M; break; diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index 74e258f..fe59883 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -2366,7 +2366,7 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_CLIENT: is_p2p = _TRUE; - fallthrough; + [[fallthrough]]; #endif case NL80211_IFTYPE_STATION: networkType = Ndis802_11Infrastructure; @@ -2391,7 +2391,7 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_GO: is_p2p = _TRUE; - fallthrough; + [[fallthrough]]; #endif case NL80211_IFTYPE_AP: networkType = Ndis802_11APMode; From 2d0faf61434af0feaa80886cadcd91f90eddcf3a Mon Sep 17 00:00:00 2001 From: William Grunow Date: Tue, 20 Oct 2020 11:40:31 -0400 Subject: [PATCH 40/48] Update README.md --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index c2f2a38..9449edf 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,7 @@ # 8822BU for Linux +Note: I no longer have a device that requires this driver, thus no guarantees that it still works, only that it compiles on my machine. + Driver for 802.11ac USB Adapter with RTL8822BU chipset Only STA/Monitor Mode is supported, no AP. From d8ad1184d045982fa0ffdc668e0bedc5e36ebfc6 Mon Sep 17 00:00:00 2001 From: Fabrice Fontaine Date: Wed, 21 Oct 2020 23:14:41 +0200 Subject: [PATCH 41/48] fix build with gcc < 10 due to fallthrough [[fallthrough]] is a C++17 statement so it can't be used in plain C code and will raise a build failure with at least gcc 8 The standard and portable way could be to use __attribute__ ((fallthrough)); but it does not seem to be really supported (e.g https://github.com/antoineco/broadcom-wl/pull/12) So just use a magical comment that should be understood by gcc > 7 and ignored by older compilers, this is ugly but it works Signed-off-by: Fabrice Fontaine --- core/rtw_mlme_ext.c | 5 +---- hal/hal_halmac.c | 6 +----- hal/hal_intf.c | 6 +----- hal/halmac/halmac_88xx/halmac_mimo_88xx.c | 10 ++-------- os_dep/linux/ioctl_cfg80211.c | 12 ++---------- 5 files changed, 7 insertions(+), 32 deletions(-) diff --git a/core/rtw_mlme_ext.c b/core/rtw_mlme_ext.c index 537deec..427cfd8 100644 --- a/core/rtw_mlme_ext.c +++ b/core/rtw_mlme_ext.c @@ -1826,10 +1826,7 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) ptable->func = &OnAuth; else ptable->func = &OnAuthClient; - -#if __GNUC__ > 6 - [[fallthrough]]; -#endif + // fallthrough case WIFI_ASSOCREQ: case WIFI_REASSOCREQ: diff --git a/hal/hal_halmac.c b/hal/hal_halmac.c index 001a1f0..06cdb99 100644 --- a/hal/hal_halmac.c +++ b/hal/hal_halmac.c @@ -2695,11 +2695,7 @@ static int _send_general_info(struct dvobj_priv *d) case HALMAC_RET_NO_DLFW: RTW_WARN("%s: halmac_send_general_info() fail because fw not dl!\n", __FUNCTION__); - -#if __GNUC__ > 6 - [[fallthrough]]; -#endif - + // fallthrough default: return -1; } diff --git a/hal/hal_intf.c b/hal/hal_intf.c index 551eca0..18d1a66 100644 --- a/hal/hal_intf.c +++ b/hal/hal_intf.c @@ -942,11 +942,7 @@ s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) case C2H_EXTEND: sub_id = payload[0]; /* no handle, goto default */ - -#if __GNUC__ > 6 - [[fallthrough]]; -#endif - + // fallthrough default: if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE) ret = _FAIL; diff --git a/hal/halmac/halmac_88xx/halmac_mimo_88xx.c b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c index aa4850a..dfd78c0 100644 --- a/hal/halmac/halmac_88xx/halmac_mimo_88xx.c +++ b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c @@ -62,16 +62,10 @@ cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw, switch (bw) { case HALMAC_BW_80: tmp42c |= BIT_R_TXBF0_80M; - - #if __GNUC__ > 6 - [[fallthrough]]; - #endif + // fallthrough case HALMAC_BW_40: tmp42c |= BIT_R_TXBF0_40M; - #if __GNUC__ > 6 - [[fallthrough]]; - #endif - + // fallthrough case HALMAC_BW_20: tmp42c |= BIT_R_TXBF0_20M; break; diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index d20e8e3..860fc5a 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -2366,11 +2366,7 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_CLIENT: is_p2p = _TRUE; - -#if __GNUC__ > 6 - [[fallthrough]]; -#endif - + // fallthrough #endif case NL80211_IFTYPE_STATION: networkType = Ndis802_11Infrastructure; @@ -2395,11 +2391,7 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_GO: is_p2p = _TRUE; - -#if __GNUC__ > 6 - [[fallthrough]]; -#endif - + // fallthrough #endif case NL80211_IFTYPE_AP: networkType = Ndis802_11APMode; From ab3bbb78b474878169ac9e65b110c2d892650984 Mon Sep 17 00:00:00 2001 From: Fabrice Fontaine Date: Thu, 22 Oct 2020 20:28:21 +0200 Subject: [PATCH 42/48] ioctl_cfg80211.c: move fallthrough comment outside ifdef gcc seems to have issue understanding the fallthrough comment because of the endif statement that is added after this comment so move the comment outside of the #ifdef block Signed-off-by: Fabrice Fontaine --- os_dep/linux/ioctl_cfg80211.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index 860fc5a..b7e8fea 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -2366,8 +2366,8 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_CLIENT: is_p2p = _TRUE; - // fallthrough #endif + // fallthrough case NL80211_IFTYPE_STATION: networkType = Ndis802_11Infrastructure; @@ -2391,8 +2391,8 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) case NL80211_IFTYPE_P2P_GO: is_p2p = _TRUE; - // fallthrough #endif + // fallthrough case NL80211_IFTYPE_AP: networkType = Ndis802_11APMode; From 687e3c2d9f37d62ba8ca8d80cc7fc3ee5ca6a3a4 Mon Sep 17 00:00:00 2001 From: Ilija Hadzic Date: Wed, 21 Oct 2020 23:03:29 -0400 Subject: [PATCH 43/48] scan: notify the kernel early of discovered networks During the scan, driver receives the notification about discovered networks spread over approximately 4-second period. Descriptor is constructed and placed into internal list that is then flushed in a callback function when the scan is complete. This will cause the timestamp associated with the network to be delayed up to 4 seconds compared to the actual time when the network is observed. Specifically, the reported 'last seen' field in 'iw dev scan dump' will be wrong. To fix this, call cfg80211_inform_bss as soon as the network is observed and finish the remaining housekeeping in the callback. This will cause the common kernel wifi framework to generate the timestamp with less delay than if the cfg80211_inform_bss were called in the callback. The remaining (and irreducable) delay is between the hardware and the driver reciving the notification, but this should be much less than if we waited for the scan to complete. Signed-off-by: Ilija Hadzic --- core/rtw_mlme.c | 10 ++++++++++ os_dep/linux/ioctl_cfg80211.c | 11 +++-------- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/core/rtw_mlme.c b/core/rtw_mlme.c index d37dd72..4a08dbe 100644 --- a/core/rtw_mlme.c +++ b/core/rtw_mlme.c @@ -1082,6 +1082,16 @@ bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) update_network(&(pnetwork->network), target, adapter, update_ie); } + /* + * report network only if the current channel set contains the channel + * to which this network belongs. Report early so that we have a valid + * scan timestamp, finish up in scan-done callback. + */ + if (rtw_chset_search_ch(adapter_to_chset(adapter), + pnetwork->network.Configuration.DSConfig) >= 0 + && rtw_mlme_band_check(adapter, pnetwork->network.Configuration.DSConfig) == _TRUE + && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))) + rtw_cfg80211_inform_bss(adapter, pnetwork); unlock_scan_queue: _exit_critical_bh(&queue->lock, &irqL); diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index b7e8fea..c218059 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -2600,15 +2600,10 @@ static void _rtw_cfg80211_surveydone_event_callback(_adapter *padapter, struct c pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - /* report network only if the current channel set contains the channel to which this network belongs */ if (rtw_chset_search_ch(adapter_to_chset(padapter), pnetwork->network.Configuration.DSConfig) >= 0 - && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE - && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) - ) { - if (target_wps_scan) - rtw_cfg80211_clear_wps_sr_of_non_target_bss(padapter, pnetwork, &target_ssid); - rtw_cfg80211_inform_bss(padapter, pnetwork); - } + && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE + && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) && target_wps_scan) + rtw_cfg80211_clear_wps_sr_of_non_target_bss(padapter, pnetwork, &target_ssid); #if 0 /* check ralink testbed RSN IE length */ { From 868ac27796f5f85c04c22f7bb50d792b96f6dc77 Mon Sep 17 00:00:00 2001 From: Ilija Hadzic Date: Wed, 21 Oct 2020 23:06:27 -0400 Subject: [PATCH 44/48] core: remove unnecessary declarations they are not doing anything useful right next to the function definitions Signed-off-by: Ilija Hadzic --- core/rtw_mlme.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/core/rtw_mlme.c b/core/rtw_mlme.c index 4a08dbe..baee8e4 100644 --- a/core/rtw_mlme.c +++ b/core/rtw_mlme.c @@ -1107,7 +1107,6 @@ bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) return update_ie; } -void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork); void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) { _irqL irqL; @@ -1142,7 +1141,6 @@ void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) * (3) WMM * (4) HT * (5) others */ -int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork); int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork) { struct security_priv *psecuritypriv = &adapter->securitypriv; From 4bb3813b6f67cc67919497b3a4ede5f07854902c Mon Sep 17 00:00:00 2001 From: LucentW Date: Sat, 19 Dec 2020 01:42:58 +0100 Subject: [PATCH 45/48] Fix for kernel 5.10 --- core/rtw_btcoex.c | 6 ++++++ core/rtw_ieee80211.c | 1 - core/rtw_wlan_util.c | 6 ++++++ os_dep/linux/os_intfs.c | 16 ++++++++++++++-- os_dep/osdep_service.c | 20 ++++++++++++++++++-- 5 files changed, 44 insertions(+), 5 deletions(-) diff --git a/core/rtw_btcoex.c b/core/rtw_btcoex.c index d1d8355..6b33e73 100644 --- a/core/rtw_btcoex.c +++ b/core/rtw_btcoex.c @@ -1444,7 +1444,9 @@ u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool for { u8 error; struct msghdr udpmsg; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) mm_segment_t oldfs; +#endif struct iovec iov; struct bt_coex_info *pcoex_info = &padapter->coex_info; @@ -1474,15 +1476,19 @@ u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool for udpmsg.msg_control = NULL; udpmsg.msg_controllen = 0; udpmsg.msg_flags = MSG_DONTWAIT | MSG_NOSIGNAL; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) oldfs = get_fs(); set_fs(KERNEL_DS); +#endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) error = sock_sendmsg(pcoex_info->udpsock, &udpmsg); #else error = sock_sendmsg(pcoex_info->udpsock, &udpmsg, msg_size); #endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) set_fs(oldfs); +#endif if (error < 0) { RTW_INFO("Error when sendimg msg, error:%d\n", error); return _FAIL; diff --git a/core/rtw_ieee80211.c b/core/rtw_ieee80211.c index 4609336..c4a9bd2 100644 --- a/core/rtw_ieee80211.c +++ b/core/rtw_ieee80211.c @@ -1396,7 +1396,6 @@ int rtw_get_mac_addr_intel(unsigned char *buf) int ret = 0; int i; struct file *fp = NULL; - mm_segment_t oldfs; unsigned char c_mac[MAC_ADDRESS_LEN]; char fname[] = "/config/wifi/mac.txt"; int jj, kk; diff --git a/core/rtw_wlan_util.c b/core/rtw_wlan_util.c index 45c273b..f9e4bb8 100644 --- a/core/rtw_wlan_util.c +++ b/core/rtw_wlan_util.c @@ -4511,7 +4511,9 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid, int i = 0; struct file *fp; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) mm_segment_t fs; +#endif loff_t pos = 0; u8 *source = NULL; long len = 0; @@ -4548,8 +4550,10 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid, return 0; } +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) fs = get_fs(); set_fs(KERNEL_DS); +#endif source = rtw_zmalloc(2048); @@ -4559,7 +4563,9 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid, rtw_mfree(source, 2048); } +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) set_fs(fs); +#endif filp_close(fp, NULL); RTW_INFO("-%s-\n", __func__); diff --git a/os_dep/linux/os_intfs.c b/os_dep/linux/os_intfs.c index f382b2b..3422b0e 100644 --- a/os_dep/linux/os_intfs.c +++ b/os_dep/linux/os_intfs.c @@ -3657,7 +3657,9 @@ static int route_dump(u32 *gw_addr , int *gw_index) struct msghdr msg; struct iovec iov; struct sockaddr_nl nladdr; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) mm_segment_t oldfs; +#endif char *pg; int size = 0; @@ -3696,14 +3698,18 @@ static int route_dump(u32 *gw_addr , int *gw_index) msg.msg_controllen = 0; msg.msg_flags = MSG_DONTWAIT; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) oldfs = get_fs(); set_fs(KERNEL_DS); +#endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) err = sock_sendmsg(sock, &msg); #else err = sock_sendmsg(sock, &msg, sizeof(req)); #endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) set_fs(oldfs); +#endif if (err < 0) goto out_sock; @@ -3727,15 +3733,18 @@ static int route_dump(u32 *gw_addr , int *gw_index) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) iov_iter_init(&msg.msg_iter, READ, &iov, 1, PAGE_SIZE); #endif - +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) oldfs = get_fs(); set_fs(KERNEL_DS); +#endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) err = sock_recvmsg(sock, &msg, MSG_DONTWAIT); #else err = sock_recvmsg(sock, &msg, PAGE_SIZE, MSG_DONTWAIT); #endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) set_fs(oldfs); +#endif if (err < 0) goto out_sock_pg; @@ -3806,15 +3815,18 @@ static int route_dump(u32 *gw_addr , int *gw_index) msg.msg_controllen = 0; msg.msg_flags = MSG_DONTWAIT; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) oldfs = get_fs(); set_fs(KERNEL_DS); +#endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) err = sock_sendmsg(sock, &msg); #else err = sock_sendmsg(sock, &msg, sizeof(req)); #endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) set_fs(oldfs); - +#endif if (err > 0) goto restart; } diff --git a/os_dep/osdep_service.c b/os_dep/osdep_service.c index 8b35ef2..918f1f7 100644 --- a/os_dep/osdep_service.c +++ b/os_dep/osdep_service.c @@ -2183,15 +2183,19 @@ static int isFileReadable(const char *path, u32 *sz) { struct file *fp; int ret = 0; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) mm_segment_t oldfs; +#endif char buf; fp = filp_open(path, O_RDONLY, 0); if (IS_ERR(fp)) ret = PTR_ERR(fp); else { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) oldfs = get_fs(); set_fs(get_ds()); +#endif if (1 != readFile(fp, &buf, 1)) ret = PTR_ERR(fp); @@ -2203,8 +2207,9 @@ static int isFileReadable(const char *path, u32 *sz) *sz = i_size_read(fp->f_dentry->d_inode); #endif } - +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) set_fs(oldfs); +#endif filp_close(fp, NULL); } return ret; @@ -2220,18 +2225,23 @@ static int isFileReadable(const char *path, u32 *sz) static int retriveFromFile(const char *path, u8 *buf, u32 sz) { int ret = -1; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) mm_segment_t oldfs; +#endif struct file *fp; if (path && buf) { ret = openFile(&fp, path, O_RDONLY, 0); if (0 == ret) { RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp); - +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) oldfs = get_fs(); set_fs(get_ds()); +#endif ret = readFile(fp, buf, sz); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) set_fs(oldfs); +#endif closeFile(fp); RTW_INFO("%s readFile, ret:%d\n", __FUNCTION__, ret); @@ -2255,7 +2265,9 @@ static int retriveFromFile(const char *path, u8 *buf, u32 sz) static int storeToFile(const char *path, u8 *buf, u32 sz) { int ret = 0; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) mm_segment_t oldfs; +#endif struct file *fp; if (path && buf) { @@ -2263,10 +2275,14 @@ static int storeToFile(const char *path, u8 *buf, u32 sz) if (0 == ret) { RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) oldfs = get_fs(); set_fs(get_ds()); +#endif ret = writeFile(fp, buf, sz); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) set_fs(oldfs); +#endif closeFile(fp); RTW_INFO("%s writeFile, ret:%d\n", __FUNCTION__, ret); From 65c80080369722be98bf605828f2daa748bff2e0 Mon Sep 17 00:00:00 2001 From: Fredrik Eriksson <39879328+bazeon@users.noreply.github.com> Date: Sun, 28 Feb 2021 15:48:48 +0100 Subject: [PATCH 46/48] Added Linksys WUSB6400M to known devices Confirmed on Pop Os 20.10 with kernel 5.8 --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 9449edf..76a8d2f 100644 --- a/README.md +++ b/README.md @@ -11,7 +11,7 @@ A few known wireless cards that use this driver include * [ASUS AC-53 NANO](https://www.asus.com/Networking/USB-AC53-Nano/) * [D-Link DWA-182 (Revision D1 only)](http://ca.dlink.com/products/connect/wireless-ac1200-dual-band-usb-adapter/) * [tp-link Archer T4U (Revision V3 only)](https://www.tp-link.com/us/home-networking/usb-adapter/archer-t4u/) - +* [Linksys WUSB6400M](https://www.linksys.com/us/support-product?pid=01t340000042wpSAAQ) > NOTE: At least v4.7 is needed to compile this module From cef7c8ad44981b816e4ccb535617f118b9c5d38e Mon Sep 17 00:00:00 2001 From: Christophe Blaess Date: Wed, 14 Jul 2021 10:31:43 +0200 Subject: [PATCH 47/48] Allow configuring `KSRC` before running `make`. This is especially usefull for cross-compilation. --- Makefile | 92 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/Makefile b/Makefile index 29da0bf..3f53ff1 100644 --- a/Makefile +++ b/Makefile @@ -1037,7 +1037,7 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/) ARCH ?= $(SUBARCH) CROSS_COMPILE ?= KVER := $(shell uname -r) -KSRC := /lib/modules/$(KVER)/build +KSRC ?= /lib/modules/$(KVER)/build MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/ INSTALL_PREFIX := STAGINGMODDIR := /lib/modules/$(KVER)/kernel/drivers/staging @@ -1050,7 +1050,7 @@ EXTRA_CFLAGS += -DPLATFORM_LINUX ARCH ?= arm CROSS_COMPILE ?= KVER ?= $(shell uname -r) -KSRC := /lib/modules/$(KVER)/build +KSRC ?= /lib/modules/$(KVER)/build MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/ INSTALL_PREFIX := endif @@ -1069,7 +1069,7 @@ EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC ARCH ?= arm CROSS_COMPILE := /mnt/newdisk/android_sdk/nvidia_tk1/android_L/prebuilts/gcc/linux-x86/arm/arm-eabi-4.8/bin/arm-eabi- -KSRC :=/mnt/newdisk/android_sdk/nvidia_tk1/android_L/out/target/product/shieldtablet/obj/KERNEL/ +KSRC ?=/mnt/newdisk/android_sdk/nvidia_tk1/android_L/out/target/product/shieldtablet/obj/KERNEL/ MODULE_NAME = wlan endif @@ -1082,7 +1082,7 @@ ARCH ?= arm CROSS_COMPILE ?= KVER := $(shell uname -r) -KSRC := /lib/modules/$(KVER)/build +KSRC ?= /lib/modules/$(KVER)/build MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/ INSTALL_PREFIX := endif @@ -1094,8 +1094,8 @@ ARCH := $(R_ARCH) #CROSS_COMPILE := arm-none-linux-gnueabi- CROSS_COMPILE := $(R_CROSS_COMPILE) KVER:= 3.4.0 -#KSRC := ../../../../build/out/kernel -KSRC := $(KERNEL_BUILD_PATH) +#KSRC ?= ../../../../build/out/kernel +KSRC ?= $(KERNEL_BUILD_PATH) MODULE_NAME :=wlan endif @@ -1118,7 +1118,7 @@ endif ARCH := arm CROSS_COMPILE := /opt/arm-2011.09/bin/arm-none-linux-gnueabi- -KSRC := /home/android_sdk/Action-semi/705a_android_L/android/kernel +KSRC ?= /home/android_sdk/Action-semi/705a_android_L/android/kernel endif ifeq ($(CONFIG_PLATFORM_ARM_SUN50IW1P1), y) @@ -1145,13 +1145,13 @@ endif ARCH := arm64 # ===Cross compile setting for Android 5.1(64) SDK === CROSS_COMPILE := /home/android_sdk/Allwinner/a64/android-51/lichee/out/sun50iw1p1/android/common/buildroot/external-toolchain/bin/aarch64-linux-gnu- -KSRC :=/home/android_sdk/Allwinner/a64/android-51/lichee/linux-3.10/ +KSRC ?=/home/android_sdk/Allwinner/a64/android-51/lichee/linux-3.10/ endif ifeq ($(CONFIG_PLATFORM_TI_AM3517), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE CROSS_COMPILE := arm-eabi- -KSRC := $(shell pwd)/../../../Android/kernel +KSRC ?= $(shell pwd)/../../../Android/kernel ARCH := arm endif @@ -1183,7 +1183,7 @@ EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN SUBARCH := $(shell uname -m | sed -e s/i.86/i386/) ARCH := $(SUBARCH) CROSS_COMPILE := /media/DATA-2/android-x86/ics-x86_20120130/prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/bin/i686-unknown-linux-gnu- -KSRC := /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel +KSRC ?= /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel MODULE_NAME :=wlan endif @@ -1206,7 +1206,7 @@ EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT SUBARCH := $(shell uname -m | sed -e s/i.86/i386/) ARCH := $(SUBARCH) CROSS_COMPILE := /home/android_sdk/android-x86_JB/prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/bin/i686-linux-android- -KSRC := /home/android_sdk/android-x86_JB/out/target/product/x86/obj/kernel/ +KSRC ?= /home/android_sdk/android-x86_JB/out/target/product/x86/obj/kernel/ MODULE_NAME :=wlan endif @@ -1223,7 +1223,7 @@ EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ARCH := arm CROSS_COMPILE := arm-linux- KVER := 2.6.24.7_$(ARCH) -KSRC := /usr/src/kernels/linux-$(KVER) +KSRC ?= /usr/src/kernels/linux-$(KVER) endif ifeq ($(CONFIG_PLATFORM_ARM_S3C6K4), y) @@ -1270,7 +1270,7 @@ ifeq ($(CONFIG_PLATFORM_MIPS_AR9132), y) EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN ARCH := mips CROSS_COMPILE := mips-openwrt-linux- -KSRC := /home/alex/test_openwrt/tmp/linux-2.6.30.9 +KSRC ?= /home/alex/test_openwrt/tmp/linux-2.6.30.9 endif ifeq ($(CONFIG_PLATFORM_DMP_PHILIPS), y) @@ -1323,7 +1323,7 @@ EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATJ227X ARCH := mips CROSS_COMPILE := /home/cnsd4/project/actions/tools-2.6.27/bin/mipsel-linux-gnu- KVER := 2.6.27 -KSRC := /home/cnsd4/project/actions/linux-2.6.27.28 +KSRC ?= /home/cnsd4/project/actions/linux-2.6.27.28 endif ifeq ($(CONFIG_PLATFORM_TI_DM365), y) @@ -1332,7 +1332,7 @@ EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX EXTRA_CFLAGS += -DCONFIG_SINGLE_XMIT_BUF -DCONFIG_SINGLE_RECV_BUF ARCH := arm #CROSS_COMPILE := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/arm/v5t_le/bin/arm_v5t_le- -#KSRC := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365 +#KSRC ?= /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365 CROSS_COMPILE := /opt/montavista/pro5.0/devkit/arm/v5t_le/bin/arm-linux- KSRC:= /home/vivotek/lsp/DM365/kernel_platform/kernel/linux-2.6.18 KERNELOUTPUT := ${PRODUCTDIR}/tmp @@ -1356,7 +1356,7 @@ EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT ARCH := arm CROSS_COMPILE := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- -KSRC := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/out/target/product/cardhu/obj/KERNEL +KSRC ?= /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/out/target/product/cardhu/obj/KERNEL MODULE_NAME := wlan endif @@ -1368,7 +1368,7 @@ EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT ARCH := arm CROSS_COMPILE := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi- -KSRC := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/out/target/product/dalmore/obj/KERNEL +KSRC ?= /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/out/target/product/dalmore/obj/KERNEL MODULE_NAME := wlan endif @@ -1376,7 +1376,7 @@ ifeq ($(CONFIG_PLATFORM_ARM_TCC8900), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ARCH := arm CROSS_COMPILE := /home/android_sdk/Telechips/SDK_2304_20110613/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- -KSRC := /home/android_sdk/Telechips/SDK_2304_20110613/kernel +KSRC ?= /home/android_sdk/Telechips/SDK_2304_20110613/kernel MODULE_NAME := wlan endif @@ -1384,7 +1384,7 @@ ifeq ($(CONFIG_PLATFORM_ARM_TCC8920), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ARCH := arm CROSS_COMPILE := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- -KSRC := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/kernel +KSRC ?= /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/kernel MODULE_NAME := wlan endif @@ -1395,7 +1395,7 @@ EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT ARCH := arm CROSS_COMPILE := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi- -KSRC := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/kernel +KSRC ?= /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/kernel MODULE_NAME := wlan endif @@ -1403,7 +1403,7 @@ ifeq ($(CONFIG_PLATFORM_ARM_RK2818), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS ARCH := arm CROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi- -KSRC := /usr/src/release_fae_version/kernel25_A7_281x +KSRC ?= /usr/src/release_fae_version/kernel25_A7_281x MODULE_NAME := wlan endif @@ -1418,7 +1418,7 @@ EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN # default setting for Special function ARCH := arm CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3188/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi- -KSRC := /home/android_sdk/Rockchip/Rk3188/kernel +KSRC ?= /home/android_sdk/Rockchip/Rk3188/kernel MODULE_NAME := wlan endif @@ -1435,7 +1435,7 @@ EXTRA_CFLAGS += -fno-pic ARCH := arm CROSS_COMPILE := /home/android_sdk/Rockchip/rk3066_20130607/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi- #CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3066sdk/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi- -KSRC := /home/android_sdk/Rockchip/Rk3066sdk/kernel +KSRC ?= /home/android_sdk/Rockchip/Rk3066sdk/kernel MODULE_NAME :=wlan endif @@ -1443,7 +1443,7 @@ ifeq ($(CONFIG_PLATFORM_ARM_URBETTER), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE ARCH := arm CROSS_COMPILE := /media/DATA-1/urbetter/arm-2009q3/bin/arm-none-linux-gnueabi- -KSRC := /media/DATA-1/urbetter/ics-urbetter/kernel +KSRC ?= /media/DATA-1/urbetter/ics-urbetter/kernel MODULE_NAME := wlan endif @@ -1451,9 +1451,9 @@ ifeq ($(CONFIG_PLATFORM_ARM_TI_PANDA), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE ARCH := arm #CROSS_COMPILE := /media/DATA-1/aosp/ics-aosp_20111227/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- -#KSRC := /media/DATA-1/aosp/android-omap-panda-3.0_20120104 +#KSRC ?= /media/DATA-1/aosp/android-omap-panda-3.0_20120104 CROSS_COMPILE := /media/DATA-1/android-4.0/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- -KSRC := /media/DATA-1/android-4.0/panda_kernel/omap +KSRC ?= /media/DATA-1/android-4.0/panda_kernel/omap MODULE_NAME := wlan endif @@ -1521,13 +1521,13 @@ endif ARCH := arm #Android-JB42 #CROSS_COMPILE := /home/android_sdk/Allwinner/a31/android-jb42/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi- -#KSRC :=/home/android_sdk/Allwinner/a31/android-jb42/lichee/linux-3.3 +#KSRC ?=/home/android_sdk/Allwinner/a31/android-jb42/lichee/linux-3.3 #ifeq ($(CONFIG_USB_HCI), y) #MODULE_NAME := 8188eu_sw #endif # ==== Cross compile setting for kitkat-a3x_v4.5 ===== CROSS_COMPILE := /home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi- -KSRC :=/home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/linux-3.3 +KSRC ?=/home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/linux-3.3 endif ifeq ($(CONFIG_PLATFORM_ARM_SUN7I), y) @@ -1551,13 +1551,13 @@ endif ARCH := arm # ===Cross compile setting for Android 4.2 SDK === #CROSS_COMPILE := /home/android_sdk/Allwinner/a20_evb/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- -#KSRC := /home/android_sdk/Allwinner/a20_evb/lichee/linux-3.3 +#KSRC ?= /home/android_sdk/Allwinner/a20_evb/lichee/linux-3.3 # ==== Cross compile setting for Android 4.3 SDK ===== #CROSS_COMPILE := /home/android_sdk/Allwinner/a20/android-jb43/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- -#KSRC := /home/android_sdk/Allwinner/a20/android-jb43/lichee/linux-3.4 +#KSRC ?= /home/android_sdk/Allwinner/a20/android-jb43/lichee/linux-3.4 # ==== Cross compile setting for kitkat-a20_v4.4 ===== CROSS_COMPILE := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- -KSRC := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/linux-3.4 +KSRC ?= /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/linux-3.4 endif ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W3P1), y) @@ -1581,10 +1581,10 @@ endif ARCH := arm # ===Cross compile setting for Android 4.2 SDK === #CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-jb42/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- -#KSRC :=/home/android_sdk/Allwinner/a23/android-jb42/lichee/linux-3.4 +#KSRC ?=/home/android_sdk/Allwinner/a23/android-jb42/lichee/linux-3.4 # ===Cross compile setting for Android 4.4 SDK === CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-kk44/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- -KSRC :=/home/android_sdk/Allwinner/a23/android-kk44/lichee/linux-3.4 +KSRC ?=/home/android_sdk/Allwinner/a23/android-kk44/lichee/linux-3.4 endif ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W5P1), y) @@ -1611,7 +1611,7 @@ endif ARCH := arm # ===Cross compile setting for Android L SDK === CROSS_COMPILE := /home/android_sdk/Allwinner/a33/android-L/lichee/out/sun8iw5p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi- -KSRC :=/home/android_sdk/Allwinner/a33/android-L/lichee/linux-3.4 +KSRC ?=/home/android_sdk/Allwinner/a33/android-L/lichee/linux-3.4 endif ifeq ($(CONFIG_PLATFORM_ACTIONS_ATV5201), y) @@ -1647,7 +1647,7 @@ ifeq ($(CROSS_COMPILE),) endif MODULE_NAME := rtl8192eu ifeq ($(KSRC),) - KSRC := ../../../../../../kernel/linux-3.4.y + KSRC ?= ../../../../../../kernel/linux-3.4.y endif endif @@ -1671,7 +1671,7 @@ endif ARCH ?= arm CROSS_COMPILE ?= /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/tools/linux/toolchains/arm-histbv310-linux/bin/arm-histbv310-linux- ifndef KSRC -KSRC := /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/source/kernel/linux-3.18.y +KSRC ?= /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/source/kernel/linux-3.18.y KSRC += O=/HiSTBAndroidV600R003C00SPC021_git_0512/out/target/product/Hi3798MV200/obj/KERNEL_OBJ endif @@ -1727,7 +1727,7 @@ _PLATFORM_FILES += platform/platform_ARM_WMT_sdio.o endif ARCH := arm CROSS_COMPILE := /home/android_sdk/WonderMedia/wm8880-android4.4/toolchain/arm_201103_gcc4.5.2/mybin/arm_1103_le- -KSRC := /home/android_sdk/WonderMedia/wm8880-android4.4/kernel4.4/ +KSRC ?= /home/android_sdk/WonderMedia/wm8880-android4.4/kernel4.4/ MODULE_NAME :=8189es_kk endif @@ -1756,9 +1756,9 @@ ARCH := arm # ==== Cross compile setting for Android 4.4 SDK ===== #CROSS_COMPILE := arm-linux-gnueabihf- KVER := 3.10.24 -#KSRC :=/home/android_sdk/Allwinner/a20/android-kitkat44/lichee/linux-3.4 +#KSRC ?=/home/android_sdk/Allwinner/a20/android-kitkat44/lichee/linux-3.4 CROSS_COMPILE := /home/realtek/software_phoenix/phoenix/toolchain/usr/local/arm-2013.11/bin/arm-linux-gnueabihf- -KSRC := /home/realtek/software_phoenix/linux-kernel +KSRC ?= /home/realtek/software_phoenix/linux-kernel MODULE_NAME := 8192eu endif @@ -1794,9 +1794,9 @@ ARCH := arm64 #CROSS_COMPILE := arm-linux-gnueabihf- #KVER := 4.1.10 #CROSS_COMPILE := $(CROSS) -#KSRC := $(LINUX_KERNEL_PATH) +#KSRC ?= $(LINUX_KERNEL_PATH) CROSS_COMPILE := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/phoenix/toolchain/asdk64-4.9.4-a53-EL-3.10-g2.19-a64nt-160307/bin/asdk64-linux- -KSRC := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/linux-kernel +KSRC ?= /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/linux-kernel endif ifeq ($(CONFIG_PLATFORM_NOVATEK_NT72668), y) @@ -1809,8 +1809,8 @@ EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX ARCH ?= arm CROSS_COMPILE := arm-linux-gnueabihf- KVER := 3.8.0 -KSRC := /Custom/Novatek/TCL/linux-3.8_header -#KSRC := $(KERNELDIR) +KSRC ?= /Custom/Novatek/TCL/linux-3.8_header +#KSRC ?= $(KERNELDIR) endif ifeq ($(CONFIG_PLATFORM_ARM_TCC8930_JB42), y) @@ -1820,7 +1820,7 @@ EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT ARCH := arm CROSS_COMPILE := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi- -KSRC := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/kernel +KSRC ?= /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/kernel MODULE_NAME := wlan endif @@ -1829,7 +1829,7 @@ EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTL8197D export DIR_LINUX=$(shell pwd)/../SDK/rlxlinux-sdk321-v50/linux-2.6.30 ARCH ?= rlx CROSS_COMPILE:= $(DIR_LINUX)/../toolchain/rsdk-1.5.5-5281-EB-2.6.30-0.9.30.3-110714/bin/rsdk-linux- -KSRC := $(DIR_LINUX) +KSRC ?= $(DIR_LINUX) endif ifeq ($(CONFIG_PLATFORM_AML_S905), y) @@ -1850,7 +1850,7 @@ endif ARCH ?= arm64 CROSS_COMPILE ?= /4.4_S905L_8822bs_compile/gcc-linaro-aarch64-linux-gnu-4.9-2014.09_linux/bin/aarch64-linux-gnu- ifndef KSRC -KSRC := /4.4_S905L_8822bs_compile/common +KSRC ?= /4.4_S905L_8822bs_compile/common # To locate output files in a separate directory. KSRC += O=/4.4_S905L_8822bs_compile/KERNEL_OBJ endif From e27b9cd7976a888662a6bf73557c7bbb61eeda32 Mon Sep 17 00:00:00 2001 From: William Grunow Date: Mon, 1 Nov 2021 12:06:37 -0400 Subject: [PATCH 48/48] Update README.md --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index 76a8d2f..0fe8f06 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,7 @@ # 8822BU for Linux +This repo is obsolete. Try this instead (https://github.com/cilynx/rtl88x2bu) + Note: I no longer have a device that requires this driver, thus no guarantees that it still works, only that it compiles on my machine. Driver for 802.11ac USB Adapter with